diff --git a/Lauterbach_scripts/kw_dimm200.cmm b/Lauterbach_scripts/kw_dimm200.cmm new file mode 100644 index 0000000..cfc7557 --- /dev/null +++ b/Lauterbach_scripts/kw_dimm200.cmm @@ -0,0 +1,102 @@ +; initialize system +;SYStem.RESet + + +; disable the id check because the cpu does not send the debugger the pattern the debugger expects +sys.option noircheck on + +; other 946 cpu bug fix seen also on 926 +sys.option MULTIPLESFIX on + + + + SYStem.CPU 88FR331 + SYStem.Option BigEndian OFF + + ;start debugger. This will also reset the board. + SYStem.JtagClock 1MHz + SYStem.mode attach + SYStem.Up + + SYStem.JtagClock 10MHz + Data.Set C15:1 %LONG 0x00052078 + + ; dram init + + d.s 0xD0001400 %LONG 0x43000618 ; DDR SDRAM Configuration Register + d.s 0xD0001404 %LONG 0x35143000 ; Dunit Control Low Register + d.s 0xD0001408 %LONG 0x11012227 ; DDR SDRAM Timing (Low) Register + d.s 0xD000140C %LONG 0x00000814 ; DDR SDRAM Timing (High) Register + d.s 0xD0001410 %LONG 0x00000099 ; DDR SDRAM Address Control Register + d.s 0xD0001414 %LONG 0x00000000 ; DDR SDRAM Open Pages Control Register + d.s 0xD0001418 %LONG 0x00000000 ; DDR SDRAM Operation Register + d.s 0xD000141C %LONG 0x00000632 ; DDR SDRAM Mode Register + d.s 0xD0001420 %LONG 0x00000040 ; DDR SDRAM Extended Mode Register + d.s 0xD0001424 %LONG 0x0000F0FF ; Dunit Control High Register + d.s 0xD0001504 %LONG 0x07FFFFF1 ; CS[0]n Size Register + d.s 0xD000150C %LONG 0x00000000 ; CS[1]n Size Register + d.s 0xD0001514 %LONG 0x00000000 ; CS[2]n Size Register + d.s 0xD000151C %LONG 0x00000000 ; CS[3]n Size Register + d.s 0xD0001494 %LONG 0x84210000 ; DDR2 SDRAM ODT Control (Low) Register + d.s 0xD0001498 %LONG 0x00000000 ; DDR2 SDRAM ODT Control (High) Register + d.s 0xD000149C %LONG 0x0000E80F ; DDR2 Dunit ODT Control Register + d.s 0xD0001480 %LONG 0x00000001 ; DDR SDRAM Initialization Control Register + d.s 0xD0020204 %LONG 0x00000000 ; Main IRQ Interrupt Mask Register + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + +; set program counter at program start +Register.Set pc 0xFFFF0000 + +; open some windows + winpos 0% 0% 100% 50% + Data.List + winpos 0% 50% 50% 50% + SYStem + + enddo + + + + + + + + + + + diff --git a/Lauterbach_scripts/kw_dimm400.cmm b/Lauterbach_scripts/kw_dimm400.cmm new file mode 100644 index 0000000..810741f --- /dev/null +++ b/Lauterbach_scripts/kw_dimm400.cmm @@ -0,0 +1,105 @@ +; initialize system +;SYStem.RESet + + +; disable the id check because the cpu does not send the debugger the pattern the debugger expects +sys.option noircheck on + +; other 946 cpu bug fix seen also on 926 +sys.option MULTIPLESFIX on + + + + SYStem.CPU 88FR331 + SYStem.Option BigEndian OFF + + ;start debugger. This will also reset the board. + SYStem.JtagClock 1MHz + SYStem.mode attach + SYStem.Up + + SYStem.JtagClock 10MHz + Data.Set C15:1 %LONG 0x00052078 + + ; dram init + + d.s 0xD0001400 %LONG 0x43000c30 ; DDR SDRAM Configuration Register + d.s 0xD0001404 %LONG 0x39543000 ; Dunit Control Low Register + d.s 0xD0001408 %LONG 0x22125451 ; DDR SDRAM Timing (Low) Register + d.s 0xD000140C %LONG 0x00000833 ; DDR SDRAM Timing (High) Register + d.s 0xD0001410 %LONG 0x000000cc ; DDR SDRAM Address Control Register + d.s 0xD0001414 %LONG 0x00000000 ; DDR SDRAM Open Pages Control Register + d.s 0xD0001418 %LONG 0x00000000 ; DDR SDRAM Operation Register + d.s 0xD000141C %LONG 0x00000c52 ; DDR SDRAM Mode Register + d.s 0xD0001420 %LONG 0x00000042 ; DDR SDRAM Extended Mode Register + d.s 0xD0001424 %LONG 0x0000F1FF ; Dunit Control High Register + d.s 0xD0001428 %LONG 0x00085520 ; Dunit Control High Register + d.s 0xD000147c %LONG 0x00008552 ; Dunit Control High Register + d.s 0xD0001504 %LONG 0x0fFFFFF1 ; CS[0]n Size Register + d.s 0xD0001508 %LONG 0x10000000 ; CS[1]n Base Register + d.s 0xD000150C %LONG 0x0fFFFFF5 ; CS[1]n Size Register + d.s 0xD0001514 %LONG 0x00000000 ; CS[2]n Size Register + d.s 0xD000151C %LONG 0x00000000 ; CS[3]n Size Register + d.s 0xD0001494 %LONG 0x003c0000 ; DDR2 SDRAM ODT Control (Low) Register + d.s 0xD0001498 %LONG 0x00000000 ; DDR2 SDRAM ODT Control (High) Register + d.s 0xD000149C %LONG 0x0000F80F ; DDR2 Dunit ODT Control Register + d.s 0xD0001480 %LONG 0x00000001 ; DDR SDRAM Initialization Control Register + d.s 0xD0020204 %LONG 0x00000000 ; Main IRQ Interrupt Mask Register + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + d.s 0xD0020204 %LONG 0x00000000 ; " + +; set program counter at program start +Register.Set pc 0xFFFF0000 + +; open some windows + winpos 0% 0% 100% 50% + Data.List + winpos 0% 50% 50% 50% + SYStem + + enddo + + + + + + + + + + + diff --git a/Makefile b/Makefile index 9305cab..f0a8660 100644 --- a/Makefile +++ b/Makefile @@ -41,7 +41,8 @@ VENDOR= TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi) export TOPDIR - +SRCTREE := $(TOPDIR) +export SRCTREE ifeq (include/config.mk,$(wildcard include/config.mk)) # load ARCH, BOARD, and CPU configuration include include/config.mk @@ -57,8 +58,10 @@ ifeq ($(ARCH),ppc) CROSS_COMPILE = powerpc-linux- endif ifeq ($(ARCH),arm) +ifeq ($(CROSS),armlinux) CROSS_COMPILE = arm-linux- endif +endif ifeq ($(ARCH),i386) ifeq ($(HOSTARCH),i386) CROSS_COMPILE = @@ -118,7 +121,12 @@ LIBS += disk/libdisk.a LIBS += rtc/librtc.a LIBS += dtt/libdtt.a LIBS += drivers/libdrivers.a +LIBS += drivers/nand/libnand.a +LIBS += drivers/usb/libusb.a LIBS += drivers/sk98lin/libsk98lin.a +ifeq ($(CFG_DIAG), 1) +LIBS += diag/libdiag.a +endif LIBS += post/libpost.a post/cpu/libcpu.a LIBS += common/libcommon.a .PHONY : $(LIBS) @@ -130,7 +138,6 @@ PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) - # The "tools" are needed early, so put this first # Don't include stuff already done in $(LIBS) SUBDIRS = tools \ - examples \ post \ post/cpu .PHONY : $(SUBDIRS) @@ -139,6 +146,17 @@ SUBDIRS = tools \ ######################################################################### ALL = u-boot.srec u-boot.bin System.map +BINCPY = cp -f u-boot.bin u-boot-${MV_OUTPUT}.bin +ELFCPY = cp -f u-boot u-boot-${MV_OUTPUT} +SRECCPY = cp -f u-boot.srec u-boot-${MV_OUTPUT}.srec + +DO_IMAGE_NAND = ./tools/doimage -T nand -D 0x600000 -E 0x670000 -P 2048 -R \ +dramregs_$(MV_DDR_FREQ)_A.txt u-boot-${MV_OUTPUT}.bin u-boot-${MV_OUTPUT}_$(MV_DDR_FREQ)_nand.bin +DO_IMAGE_UART = ./tools/doimage -T uart -D 0x600000 -E 0x670000 -R \ +dramregs_$(MV_DDR_FREQ)_A.txt u-boot-${MV_OUTPUT}.bin u-boot-${MV_OUTPUT}_$(MV_DDR_FREQ)_uart.bin +DO_IMAGE_FLASH = ./tools/doimage -T flash -D 0x600000 -E 0x670000 -R \ +dramregs_$(MV_DDR_FREQ)_A.txt u-boot-${MV_OUTPUT}.bin u-boot-${MV_OUTPUT}_$(MV_DDR_FREQ)_flash.bin + all: $(ALL) @@ -147,9 +165,21 @@ u-boot.hex: u-boot u-boot.srec: u-boot $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ + $(SRECCPY) u-boot.bin: u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + $(BINCPY) + +ifeq ($(BOARD), config_kw) +ifeq ($(NAND_BOOT), y) + $(DO_IMAGE_NAND) +endif +ifeq ($(SPI_BOOT), y) + $(DO_IMAGE_FLASH) +endif + $(DO_IMAGE_UART) +endif u-boot.img: u-boot.bin ./tools/mkimage -A $(ARCH) -T firmware -C none \ @@ -161,6 +191,15 @@ u-boot.img: u-boot.bin u-boot.dis: u-boot $(OBJDUMP) -d $< > $@ +nboot: $(NAND_OBJS) + $(LD) $(NAND_LDFLAGS) $(NAND_OBJS) --start-group $(LIBS) $(PLATFORM_LIBS) --end-group\ + -e nbootStart -Map nboot.map -o nboot + $(OBJCOPY) ${OBJCFLAGS} -O binary $@ $@.bin + $(OBJDUMP) -d $@ > $@.dis + +cnboot: + rm -f nboot* + u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT) UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \ @@ -197,6 +236,7 @@ System.map: u-boot @$(NM) $< | \ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ sort > System.map + $(ELFCPY) ######################################################################### else @@ -1349,8 +1389,1330 @@ AmigaOneG3SE_config: unconfig BAB7xx_config: unconfig @./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec -CPCI750_config: unconfig - @./mkconfig CPCI750 ppc 74xx_7xx cpci750 esd +MV64XXX_PPC_LE_config \ +MV64XXX_PPC_config : unconfig + @./mkconfig MV64XXX_PPC ppc 74xx_7xx db64xxx_ppc Marvell + @[ -z "$(findstring LE,$@)" ] || \ + { echo "CONFIG_MARVELL_LE = y" >>include/config.mk ;\ + echo "export CONFIG_MARVELL_LE" >> include/config.mk ;\ + echo "** Little Endian ** config " ; \ + } + @[ -z "$(findstring MV64XXX_PPC,$@)" ] || \ + { echo "CROSS_COMPILE = powerpc-linux-" >> include/config.mk ;\ + echo "export CROSS_COMPILE" >> include/config.mk ; \ + echo "using powerpc-linux- cross compiler" ;\ + } + +######################################################################### +## Marvell KW based Socs +######################################################################### + +ifeq ($(CROSS),armlinux) +else +CSL = arm-none-linux-gnueabi- +CSLBE = armeb-none-linux-gnueabi- +endif + +rd88f6281a_config \ +db88f6281abp_config \ +db88f6282abp_config \ +db88f6280abp_config \ +rd88f6192a_config \ +db88f6192abp_config \ +db88f6180abp_config \ +rd88f6190a_config \ +db88f6190abp_config \ +rd88f6281apcac_config \ +rd88f6281Sheevaplug_config \ +db88f6281customer_config \ +db88f6192customer_config \ +db88f6180customer_config \ +buffalo_mvlsxh_6281_config \ +buffalo_mvwxl_6281_config \ +buffalo_mvlsvl_6282_config \ +buffalo_mvlswvl_6282_config \ +buffalo_mvlsxlv2_6192_config \ +: + @$(MAKE) -s mv_kw RULE=$@ + +mv_kw: unconfig + @./mkconfig $(@:_config=) arm arm926ejs config_kw mv_feroceon; + @cp board/mv_feroceon/config_kw/config_def.mk board/mv_feroceon/config_kw/config.mk; + @echo "MV_OUTPUT = $(RULE:_config=)" >> include/config.mk; \ +#======================= +# Buffalo Platform flag +#======================= + @[ -z "$(findstring buffalo,$(RULE))" ] || \ + { echo "MV_FLAGS += -DCONFIG_BUFFALO_PLATFORM" >> include/config.mk; \ + echo "** Buffalo Platform image ** config " ; \ + } + +#======================= +# Soc Compilation flag +#======================= + @[ -z "$(findstring 6281,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV88F6281" >> include/config.mk; \ + echo "** MV_88F6281 image ** config " ; \ + } + @[ -z "$(findstring 6280,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV88F6280" >> include/config.mk; \ + echo "** MV_88F6280 image ** config " ; \ + } + @[ -z "$(findstring 6192,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV88F6192" >> include/config.mk; \ + echo "** MV_88F6192 image ** config " ; \ + } + @[ -z "$(findstring 6190,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV88F6190" >> include/config.mk; \ + echo "** MV_88F6190 image ** config " ; \ + } + @[ -z "$(findstring 6180,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV88F6180" >> include/config.mk; \ + echo "** MV_88F6180 image ** config " ; \ + } + @[ -z "$(findstring 6282,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV88F6282" >> include/config.mk; \ + echo "** MV_88F6282 image ** config " ; \ + } +#======================= +# Board Compilation flags +#======================= + @[ -z "$(findstring db88f6281abp_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6281A" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_MMC" >> include/config.mk; \ + echo "MV_DDR_FREQ = 400db" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** DB 88F6281A BP ** config " ; \ + } + @[ -z "$(findstring db88f6280abp_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6280A" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_MMC" >> include/config.mk; \ + echo "MV_DDR_FREQ = 200db6280" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** DB 88F6280A BP ** config " ; \ + } + @[ -z "$(findstring rd88f6281a_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F6281A" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_DDR_FREQ = 400rd" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** RD 88F6281A ** config " ; \ + } + @[ -z "$(findstring db88f6192abp_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6192A" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_MMC" >> include/config.mk; \ + echo "MV_DDR_FREQ = 200db619x" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** DB 88F6192A BP ** config " ; \ + } + @[ -z "$(findstring rd88f6192a_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F6192A" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_DDR_FREQ = 200rd" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** RD 88F6192A ** config " ; \ + } + @[ -z "$(findstring db88f6180abp_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6180A" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_MMC" >> include/config.mk; \ + echo "MV_DDR_FREQ = 200db" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** DB 88F6180A BP ** config " ; \ + } + @[ -z "$(findstring db88f6190abp_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6190A" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_MMC" >> include/config.mk; \ + echo "MV_DDR_FREQ = 200db" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** DB 88F6190A BP ** config " ; \ + } + @[ -z "$(findstring rd88f6190a_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F6190A" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_DDR_FREQ = 200rd" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** RD 88F6190A ** config " ; \ + } + @[ -z "$(findstring rd88f6281apcac_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F6281A_PCAC" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_DDR_FREQ = 200pcac" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** RD 88F6281A PCAC** config " ; \ + } + @[ -z "$(findstring rd88f6281Sheevaplug_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F6281A_SHEEVA_PLUG" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_DDR_FREQ = 400db" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** SHEEVA PLUG** config " ; \ + } + @[ -z "$(findstring db88f6282abp_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6282A" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_MMC" >> include/config.mk; \ + echo "MV_DDR_FREQ = 400db" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** DB 88F6282A BP ** config " ; \ + } + @[ -z "$(findstring customer_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_CUSTOMER" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_DDR_FREQ = customer" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-sec256k.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** DB CUSTOMER** config " ; \ + } + @[ -z "$(findstring buffalo_mvlsxh,$(RULE))" ] || \ + { echo "MV_FLAGS += -DBF_MVLSXH" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_FLAGS += -DTCLK_AUTO_DETECT" >> include/config.mk; \ + echo "MV_DDR_FREQ = 400mvlsxh" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-mvlsxh.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** MVLSXH ** config " ; \ + } + @[ -z "$(findstring buffalo_mvwxl,$(RULE))" ] || \ + { echo "MV_FLAGS += -DBF_MVWXL" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_MMC" >> include/config.mk; \ + echo "MV_FLAGS += -DTCLK_AUTO_DETECT" >> include/config.mk; \ + echo "MV_DDR_FREQ = 300wxl" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-mvlsxh.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** MVWXL ** config " ; \ + } + @[ -z "$(findstring buffalo_mvlsvl,$(RULE))" ] || \ + { echo "MV_FLAGS += -DBF_MVLSVL" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_FLAGS += -DTCLK_AUTO_DETECT" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-mvlsxh.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** MVLSVL ** config " ; \ + } + @[ -z "$(findstring buffalo_mvlswvl,$(RULE))" ] || \ + { echo "MV_FLAGS += -DBF_MVLSWVL" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_FLAGS += -DTCLK_AUTO_DETECT" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-mvlsxh.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** MVLSWVL ** config " ; \ + } + @[ -z "$(findstring buffalo_mvlsxlv2,$(RULE))" ] || \ + { echo "MV_FLAGS += -DBF_MVLSXLV2" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; \ + echo "MV_FLAGS += -DTCLK_AUTO_DETECT" >> include/config.mk; \ + echo "MV_DDR_FREQ = 400mvlsxh" >> include/config.mk; \ + cp board/mv_feroceon/config_kw/u-boot-mvlsxh.lds board/mv_feroceon/config_kw/u-boot.lds; \ + echo "** MVLSXLV2 ** config " ; \ + } + +#============================== +# Little Endian Cross Compiler +#============================== +ifeq ($(BE),) +ifeq ($(CSL),) + @echo "CROSS_COMPILE = arm-none-linux-gnueabi-" >> include/config.mk; +else + @echo "CROSS_COMPILE = $(CSL)" >> include/config.mk; +endif +endif +#============================== +# Big Endian Cross Compiler +#============================== +ifeq ($(BE),1) + @echo "MV_FLAGS += -mbig-endian -D__BE" >> include/config.mk; + @echo "BIG_ENDIAN =y" >> include/config.mk; + @echo "LDFLAGS += -EB" >> include/config.mk; +ifeq ($(CSLBE),) + @echo "CROSS_COMPILE = armeb-none-linux-gnueabi-" >> include/config.mk; +else + @echo "CROSS_COMPILE = $(CSLBE)" >> include/config.mk; +endif + @echo "** Big Endian ** config "; +endif + +#================= +# DDR3 support +#================= +ifeq ($(DDR3),1) + @echo "** DDR3 support image ** config " ; + echo "MV_DDR_FREQ = 533ddr3db" >> include/config.mk; +endif +#================= +# USB support +#================= +#ifeq ($(USB),1) + @echo "MV_FLAGS += -DMV_USB -DCONFIG_CMD_USB" >> include/config.mk; + @echo "MV_USB=y" >> include/config.mk; + @echo "** With USB ** config " ; +#endif +#================= +# NAND support +#================= +ifeq ($(NAND),1) + @echo "** NAND support image ** config " ; + @echo "MV_FLAGS += -DMV_NAND" >> include/config.mk; +endif +#================= +# Boot from NAND support +#================= +ifeq ($(NBOOT),1) + @echo "** Boot from NAND support image ** config " ; + @echo "MV_FLAGS += -DMV_NAND_BOOT" >> include/config.mk; + @echo "MV_FLAGS += -DMV_NAND" >> include/config.mk; + @echo "NAND_BOOT =y" >> include/config.mk; + @cat board/mv_feroceon/config_kw/config_nand.mk >> board/mv_feroceon/config_kw/config.mk; + cp board/mv_feroceon/config_kw/u-boot-sec128k.lds board/mv_feroceon/config_kw/u-boot.lds; +endif +#================= +# SPI support +#================= +ifeq ($(SPI),1) + @echo "** SPI support image ** config " ; + @echo "MV_FLAGS += -DMV_SPI" >> include/config.mk; +endif +ifeq ($(SPIBOOT),1) + @echo "** Boot from SPI support image ** config " ; + @echo "MV_FLAGS += -DMV_SPI" >> include/config.mk; + @echo "MV_FLAGS += -DMV_SPI_BOOT" >> include/config.mk; + @echo "SPI_BOOT =y" >> include/config.mk; +endif +#================= +# MFlash support +#================= +ifeq ($(MFLASH),1) + @echo "** MFLASH support image ** config " ; + @echo "MV_FLAGS += -DMV_FLASH" >> include/config.mk; +endif +ifeq ($(MFLASHBOOT),1) + @echo "** Boot from MFLASH support image ** config " ; + @echo "MV_FLAGS += -DMV_FLASH" >> include/config.mk; + @echo "MV_FLAGS += -DMV_FLASH_BOOT" >> include/config.mk; +endif +#================= +# BOOTROM support +#================= +#ifeq ($(BOOTROM),1) +# @echo "** BOOTROM support image ** config " ; +# @echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; +ifeq ($(NBOOT),1) + @cp board/mv_feroceon/config/u-boot-sec64k-header-nand.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec64k-header.lds board/mv_feroceon/config/u-boot.lds; +endif +#endif + +#========================== +# Diagnostic tests support +#========================== +ifeq ($(DIAG),1) + @echo "** diagnostic tests support image ** config " ; + @echo "MV_FLAGS += -DCFG_DIAG" >> include/config.mk; + @echo "CFG_DIAG=1" >> include/config.mk; +endif +#=================== +# Tiny Image support +#=================== +ifneq ($(TINY),) + @echo "MV_FLAGS += -DMV_TINY_IMAGE" >> include/config.mk; + @echo "MV_TINY_IMAGE=y" >> include/config.mk; +ifeq ($(TINY),256K_32K) + @echo "** TINY image BootSize=256K SEC=32K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec32k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec32k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_32K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_256K" >> include/config.mk; +else +ifeq ($(TINY),256K_64K) + @echo "** TINY image BootSize=256K SEC=64K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec64k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec64k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_256K" >> include/config.mk; +else +ifeq ($(TINY),512K_64K) + @echo "** TINY image BootSize=512K SEC=64K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec64k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec64k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; +else +ifeq ($(TINY),4M_128K) + @echo "** TINY image BootSize=4M SEC=128K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec128k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec128k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_4M" >> include/config.mk; +else +ifeq ($(TINY),8M_128K) + @echo "** TINY image BootSize=8M SEC=128K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec128k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec128k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_8M" >> include/config.mk; +else +ifeq ($(TINY),16M_64K) + @echo "** TINY image BootSize=16M SEC=64K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec64k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec64k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; +else +ifeq ($(TINY),16M_128K) + @echo "** TINY image BootSize=16M SEC=128K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec128k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec128k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; +else +ifeq ($(TINY),256K_4K) + @echo "** TINY image BootSize=256K SEC=4K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec4k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec4k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_4K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_256K" >> include/config.mk; +else + @make mrproper; + @echo "" ; + @echo "** ERROR : Illegal TINY image configuration" ; + @echo "" ; + @echo "Legal values for TINY are :" ; + @echo "" ; + @echo "512K_64K, 16M_64K, 16M_128K, 256K_32K or 256K_4K" ; + @echo "" ; +endif +endif +endif +endif +endif +endif +endif +endif +endif +#============================= +# Summary of compilation flags +#============================= + @echo -e "CPPFLAGS += \044(MV_IMAGE_FLAGS) \044(MV_FLAGS)" >> include/config.mk; + +######################################################################### +## END of Marvell KW based Socs +######################################################################### + +######################################################################### +## Marvell Feroceon based Socs +######################################################################### +# Parameters: Target Architecture CPU Board [VENDOR] [SOC] # +# + +rd78XX0_PCAC_config \ +rd78XX0_H3C_config \ +rd78XX0_MP_H3C_config \ +rd78XX0_AMC_config \ +rd78200_MP_AMC_config \ +rd78XX0_MASA_config \ +rd78XX0_MP_MASA_config \ +rd78XX0_MP_MASA_2DIMM_config \ +rd78200_MP_MASA_config \ +rd78200_MP_MASA_2DIMM_config \ +db78200_MP_config \ +db76100_config \ +db78XX0_config \ +db88f632x_config : + @$(MAKE) -s mv_dd RULE=$@ +mv_dd: unconfig + @./mkconfig $(@:_config=) arm arm926ejs config_dd mv_feroceon; + @cp -f board/mv_feroceon/config_dd/config_def.mk board/mv_feroceon/config_dd/config.mk; + @cp -f board/mv_feroceon/config_dd/u-boot_def.lds board/mv_feroceon/config_dd/u-boot.lds; + @echo "MV_OUTPUT = $(RULE:_config=)" >> include/config.mk; \ +#======================= +# Soc Compilation flag +#======================= + @[ -z "$(findstring 78XX0_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV78XX0" >> include/config.mk; \ + echo "** MV_78XX0 image ** config " ; \ + } + @[ -z "$(findstring 76100_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV78XX0" >> include/config.mk; \ + echo "MV_FLAGS += -DMV76100" >> include/config.mk; \ + echo "** MV_76100 image ** config " ; \ + } + @[ -z "$(findstring 78200_MP,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV78XX0" >> include/config.mk; \ + echo "MV_FLAGS += -DMV78200" >> include/config.mk; \ + echo "MV78200 =y" >> include/config.mk; \ + echo "** MV78200 image ** config " ; \ + } + @[ -z "$(findstring 88f632x,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV632X" >> include/config.mk; \ + echo "MV_FLAGS += -DMV6323" >> include/config.mk; \ + echo "MV_FLAGS += -DMV78XX0" >> include/config.mk; \ + echo "MV_FLAGS += -DMV78200" >> include/config.mk; \ + echo "MV88F632X =y" >> include/config.mk; \ + echo "MV78200 =y" >> include/config.mk; \ + echo "** MV88F632X image ** config " ; \ + } +#======================= +# Board Compilation flags +#======================= + @[ -z "$(findstring db78XX0_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_MV78XX0" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_32M" >> include/config.mk; \ +# echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ +# echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp -f board/mv_feroceon/config_dd/u-boot-sec256k.lds board/mv_feroceon/config_dd/u-boot.lds; \ + echo "** DB 78XX0 BP ** config " ; \ + } + @[ -z "$(findstring db76100_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_MV78XX0" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + echo "** DB 78XX0 BP ** config " ; \ + } + @[ -z "$(findstring db78200_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_MV78XX0" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_32M" >> include/config.mk; \ + cp -f board/mv_feroceon/config_dd/u-boot-sec128k.lds board/mv_feroceon/config_dd/u-boot.lds; \ + echo "** DB 78200 A BP ** config " ; \ + } + @[ -z "$(findstring _AMC_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_MV78XX0_AMC" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + echo "** RD 78XX0 AMC ** config " ; \ + } + @[ -z "$(findstring _H3C_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_MV78XX0_H3C" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_2M" >> include/config.mk; \ + echo "** RD 78XX0 H3C ** config " ; \ + } + @[ -z "$(findstring _MASA_2DIMM_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_MV78XX0_MASA" >> include/config.mk; \ + echo "MV_FLAGS += -DRD_MV78XX0_MASA_2DIMM" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + echo "** RD 78XX0 MASA ** config " ; \ + } + @[ -z "$(findstring _MASA_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_MV78XX0_MASA" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + echo "** RD 78XX0 MASA ** config " ; \ + } + @[ -z "$(findstring _PCAC_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_MV78XX0_PCAC" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + echo "** RD 78XX0 PCAC ** config " ; \ + } + @[ -z "$(findstring db88f632x_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_MV88F632X" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_32M" >> include/config.mk; \ + echo "** DB 88F632X BP ** config " ; \ + } + +#============================== +# Little Endian Cross Compiler +#============================== +ifeq ($(BE),) +ifeq ($(CSL),) + @echo "CROSS_COMPILE = arm-none-linux-gnueabi-" >> include/config.mk; +else + @echo "CROSS_COMPILE = $(CSL)" >> include/config.mk; +endif + @echo "CONFIG_MARVELL_LE = y" >>include/config.mk ; + @echo "export CONFIG_MARVELL_LE" >> include/config.mk ; + @echo "** Little Endian ** config " ; + @echo "MV_FLAGS += -D__LE" >> include/config.mk; +endif +#============================== +# Big Endian Cross Compiler +#============================== +ifeq ($(BE),1) + @echo "MV_FLAGS += -mbig-endian -D__BE" >> include/config.mk; + @echo "BIG_ENDIAN =y" >> include/config.mk; + @echo "LDFLAGS += -EB" >> include/config.mk; +ifeq ($(CSLBE),) + @echo "CROSS_COMPILE = armeb-none-linux-gnueabi-" >> include/config.mk; +else + @echo "CROSS_COMPILE = $(CSLBE)" >> include/config.mk; +endif + @echo "** Big Endian ** config "; +endif + +#================= +# MV 78200 image option +#================= +ifeq ($(LNX),1) + @echo "** Dual Boot for Linux ** config " ; + @echo "MV_FLAGS += -DDUAL_OS_78200" >> include/config.mk; +endif + + +ifeq ($(LNX_SHARED),1) + @echo "** Dual Boot with Shared Memory for Linux ** config " ; + @echo "MV_FLAGS += -DDUAL_OS_SHARED_MEM_78200" >> include/config.mk; +endif + +#================= +# USB support +#================= +#ifeq ($(USB),1) + @echo "MV_FLAGS += -DMV_USB -DCONFIG_CMD_USB" >> include/config.mk; + @echo "MV_USB=y" >> include/config.mk; + @echo "** With USB ** config " ; +#endif +#================= +# Boot from NAND support +#================= + @echo "MV_FLAGS += -DMV_NAND" >> include/config.mk; +ifeq ($(NBOOT),1) + @echo "** Boot from NAND support image ** config " ; + @echo "MV_FLAGS += -DMV_NAND_BOOT" >> include/config.mk; +ifeq ($(LARGE_PAGE),1) + @echo "** NAND Large page support** config " ; + @echo "MV_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; +endif + @echo "NAND_BOOT =y" >> include/config.mk; + @cat board/mv_feroceon/config_dd/config_nand.mk >> board/mv_feroceon/config_dd/config.mk; + @cp board/mv_feroceon/config_dd/u-boot-sec128k.lds board/mv_feroceon/config_dd/u-boot.lds; +endif +#================= +# Boot from SPI support +#================= +ifeq ($(SPIBOOT),1) + @echo "** Boot from SPI support image ** config " ; + @echo "MV_FLAGS += -DMV_SPI_BOOT" >> include/config.mk; + @echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_8M" >> include/config.mk; +endif + +#=================== +# Tiny Image support +#=================== +ifneq ($(TINY),) + @echo "MV_FLAGS += -DMV_TINY_IMAGE" >> include/config.mk; + @echo "MV_TINY_IMAGE=y" >> include/config.mk; +ifeq ($(TINY),256K_4K) + @echo "** TINY image BootSize=256K SEC=4K" ; + @cp board/mv_feroceon/config_dd/u-boot-sec4k-tiny.lds board/mv_feroceon/config_dd/u-boot.lds; + @echo "MV_IMAGE_FLAGS = -DMV_SEC_4K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_256K" >> include/config.mk; + +else + @make mrproper; + @echo "" ; + @echo "** ERROR : Illegal TINY image configuration" ; + @echo "" ; + @echo "Legal values for TINY are :" ; + @echo "" ; + @echo "512K_64K or 256K_4K" ; + @echo "" ; +endif +endif +#============================= +# Summary of compilation flags +#============================= + @echo -e "CPPFLAGS += \044(MV_IMAGE_FLAGS) \044(MV_FLAGS)" >> include/config.mk; + + +######################################################################### +## Marvell Feroceon based Socs +######################################################################### + +ifeq ($(CROSS),armlinux) +else +CSL = arm-none-linux-gnueabi- +CSLBE = armeb-none-linux-gnueabi- +endif + +db88f1181_config \ +db88f5181L_VOIP2_config \ +rd88f5181L_VOIP2_FE_config \ +rd88f5181L_VOIP2_GE_config \ +rd88f5181L_FXO_GE_config \ +db88f5181_VOIP2_config \ +rd88f5181_GTW_FE_config \ +rd88f5181_GTW_GE_config \ +db88f5182_config \ +db88f5182_A_config \ +rd88f5182_NAS2_config \ +rd88f5182_NAS3_config \ +db88f5082_config \ +rd88f5082_NAS2_config \ +rd88f5082_NAS3_config \ +rd88w8660_config \ +db88w8660_config \ +rd88w8660_AP82S_config\ +db88f5181_POS_NAS_config \ +db88f5181_VOIP1_config \ +db88f5181_PRPMC_config \ +db88f5181_PEX_PCI_config \ +db88f5181_MNG_config \ +db88f5180n_config \ +db88f1281_config \ +db88f6082bp_config \ +db88f6082Lbp_config \ +db88f6082sa_config \ +rd88f6082nas_config \ +rd88f6082u_das_nas_config \ +rd88f6082das_plus_config \ +rd88f6082ge_sata_config \ +rd88f6082_dx243_24g_config \ +rd_88f5181L_Customer1_config \ +db88f5x8x_fpga_config \ +db88f6183Lbp_config \ +db88f6183_bp_config \ +db88f6183_bp_LargeSpi_config \ +rd88f6183_gp_config \ +rd88f6183_ap_config \ +db88f5181_old_config \ +db88f5181_config : + @$(MAKE) -s mv_feroceon RULE=$@ + +mv_feroceon: unconfig + @./mkconfig $(@:_config=) arm arm926ejs config mv_feroceon; + @cp board/mv_feroceon/config/config_def.mk board/mv_feroceon/config/config.mk; + @echo "MV_OUTPUT = $(RULE:_config=)" >> include/config.mk; \ +#======================= +# Soc Compilation flag +#======================= + @[ -z "$(findstring 1181_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F1181" >> include/config.mk; \ + echo "** MV_88F1181 image ** config " ; \ + } + @[ -z "$(findstring 1281_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F1281" >> include/config.mk; \ + echo "MV_88F1281=y" >> include/config.mk; \ + echo "** MV_88F1281 image ** config " ; \ + } + @[ -z "$(findstring 5181_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F5181" >> include/config.mk; \ + echo "** MV_88F5181 image ** config " ; \ + } + @[ -z "$(findstring 5182_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F5182" >> include/config.mk; \ + echo "** MV_88F5182 image ** config " ; \ + } + @[ -z "$(findstring 5082_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F5082" >> include/config.mk; \ + echo "** MV_88F5082 image ** config " ; \ + } + @[ -z "$(findstring 88w8660_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88W8660" >> include/config.mk; \ + echo "MV_88W8660=y" >> include/config.mk; \ + echo "** MV_88W8660 image ** config " ; \ + } + @[ -z "$(findstring 5181L_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F5181L" >> include/config.mk; \ + echo "** MV_88F5181L image ** config " ; \ + } + @[ -z "$(findstring 5180n_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F5180N" >> include/config.mk; \ + echo "** MV_88F5180N image ** config " ; \ + } + @[ -z "$(findstring 6082,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F6082" >> include/config.mk; \ + echo "MV_88F6082=y" >> include/config.mk; \ + echo "** MV_88F6082 image ** config " ; \ + } + @[ -z "$(findstring 6082L,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F6082L" >> include/config.mk; \ + echo "MV_88F6082L=y" >> include/config.mk; \ + echo "** MV_88F6082L image ** config " ; \ + } + @[ -z "$(findstring 5x8x,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F5181" >> include/config.mk; \ + echo "MV_88F5181=y" >> include/config.mk; \ + echo "** MV_88F5X8X image ** config " ; \ + } + @[ -z "$(findstring 6183_,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F6183" >> include/config.mk; \ + echo "MV_88F6183=y" >> include/config.mk; \ + echo "** MV_88F6183 image ** config " ; \ + } + @[ -z "$(findstring 6183L,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_88F6183L" >> include/config.mk; \ + echo "MV_88F6183L=y" >> include/config.mk; \ + echo "** MV_88F6183L image ** config " ; \ + } +#======================= +# Board Compilation flags +#======================= + @[ -z "$(findstring db88f1181_config,$(RULE))" ] || \ + { echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + } + @[ -z "$(findstring db88f1281_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F1281" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + } + @[ -z "$(findstring db88f5181_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F5181" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB88F5181 BP-A/B ** config " ; \ + } + @[ -z "$(findstring db88f5181_old_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F5181_OLD" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB88F5181 OLD BP ** config " ; \ + } + @[ -z "$(findstring db88f5x8x_fpga_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_FPGA" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB88F5X8X FPGA ** config " ; \ + } + @[ -z "$(findstring db88f5182_config,$(RULE))" ] || \ + { echo "CPPFLAGS += -DDB_88F5182" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F5182 ** config " ; \ + } + @[ -z "$(findstring db88f5182_A_config,$(RULE))" ] || \ + { echo "CPPFLAGS += -DDB_88F5182_A" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F5182 A ** config " ; \ + } + @[ -z "$(findstring rd88f5182_NAS2,$(RULE))" ] || \ + { echo "CPPFLAGS += -DRD_88F5182" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F5182 ** config " ; \ + } + @[ -z "$(findstring rd88f5182_NAS3,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F5182_3" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec128k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F5182_3 ** config " ; \ + } + @[ -z "$(findstring db88f5082_config,$(RULE))" ] || \ + { echo "CPPFLAGS += -DDB_88F5082" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F5082 ** config " ; \ + } + @[ -z "$(findstring rd88f5082_NAS2,$(RULE))" ] || \ + { echo "CPPFLAGS += -DRD_88F5082" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_4K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_256K" >> include/config.mk; \ + echo "** RD_88F5082 ** config " ; \ + } + @[ -z "$(findstring rd88f5082_NAS3,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F5082_3" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec128k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F5082_3 ** config " ; \ + } + @[ -z "$(findstring Customer1,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_CUSTOMER1" >> include/config.mk; \ + echo "MV_FLAGS += -DDB_CUSTOMER" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_32M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec128k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** Customer 1 image ** config " ; \ + } + @[ -z "$(findstring POS_NAS,$(RULE))" ] || \ + { echo "MV_FLAGS += -DMV_POS_NAS" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** POS_NAS image ** config " ; \ + } + @[ -z "$(findstring PRPMC,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_PRPMC" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** PRPMC image ** config " ; \ + } + @[ -z "$(findstring MNG,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_MNG" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** MNG image ** config " ; \ + } + @[ -z "$(findstring PEX_PCI,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_PEX_PCI" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** PEX_PCI image ** config " ; \ + } + @[ -z "$(findstring db88f5181_VOIP1,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_VOIP" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** VOIP1 image ** config " ; \ + } + @[ -z "$(findstring db88w8660_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88W8660" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + } + @[ -z "$(findstring rd88w8660_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88W8660" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec128k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88W8660 image ** config " ; \ + } + @[ -z "$(findstring rd88w8660_AP82S_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88W8660_AP82S" >> include/config.mk; \ + echo "MV_FLAGS += -DMV_DRAM_16M" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_8M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec128k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88W8660_AP82S image ** config " ; \ + } + @[ -z "$(findstring db88f5181_VOIP2,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_DB_88F5181L" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F5181L_VOIP2 image ** config " ; \ + } + @[ -z "$(findstring db88f5181L_VOIP2,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F5181L" >> include/config.mk; \ + echo "MV_FLAGS += -DRD_DB_88F5181L" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F5181L_VOIP2 image ** config " ; \ + } + @[ -z "$(findstring rd88f5181L_VOIP2_FE,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F5181L_FE" >> include/config.mk; \ + echo "MV_FLAGS += -DRD_DB_88F5181L" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec128k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F5181L_FE image ** config " ; \ + } + @[ -z "$(findstring rd88f5181L_VOIP2_GE,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F5181L_GE" >> include/config.mk; \ + echo "MV_FLAGS += -DRD_DB_88F5181L" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec128k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F5181L_GE image ** config " ; \ + } + @[ -z "$(findstring rd88f5181L_FXO_GE,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F5181L_FXO_GE" >> include/config.mk; \ + echo "MV_FLAGS += -DRD_DB_88F5181L" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_8M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F5181L_FXO_GE image ** config " ; \ + } + @[ -z "$(findstring rd88f5181_GTW_FE,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F5181_GTWFE" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec128k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F5181_GTW_FE image ** config " ; \ + } + @[ -z "$(findstring rd88f5181_GTW_GE,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F5181_GTWGE" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec128k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F5181_GTW_GE image ** config " ; \ + } + @[ -z "$(findstring db88f5180n_config,$(RULE))" ] || \ + { echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + } + @[ -z "$(findstring db88f6082bp_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6082BP" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F6082 image ** config " ; \ + } + @[ -z "$(findstring db88f6082bp_LP_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6082BP" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_LARGE_PAGE" >> include/config.mk; \ + echo "NAND_LARGE_PAGE =y" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F6082 image ** config " ; \ + } + @[ -z "$(findstring db88f6082Lbp_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6082LBP" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F6082L image ** config " ; \ + } + @[ -z "$(findstring db88f6082sa_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6082SA" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F6082 image ** config " ; \ + } + @[ -z "$(findstring rd88f6082nas_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F6082NAS" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F6082_NAS image ** config " ; \ + } + @[ -z "$(findstring rd88f6082u_das_nas_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F6082MICRO_DAS_NAS" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F6082_MICRO_DAS_NAS image ** config " ; \ + } + @[ -z "$(findstring rd88f6082das_plus_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F6082DAS_PLUS" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F6082_DAS_PLUS image ** config " ; \ + } + @[ -z "$(findstring rd88f6082ge_sata_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F6082GE_SATA" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F6082_GE_SATA image ** config " ; \ + } + @[ -z "$(findstring db88f6183Lbp_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6183LBP" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_8M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F6183LBP image ** config " ; \ + } + @[ -z "$(findstring db88f6183_bp_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6183BP" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_8M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F6183BP image ** config " ; \ + } + @[ -z "$(findstring db88f6183_bp_LargeSpi_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DDB_88F6183BP" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_256K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_MMC" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec256k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** DB_88F6183BP image ** config " ; \ + } + @[ -z "$(findstring rd88f6183_gp_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F6183GP" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_MMC" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F6183GP image ** config " ; \ + } + @[ -z "$(findstring rd88f6183_ap_config,$(RULE))" ] || \ + { echo "MV_FLAGS += -DRD_88F6183AP" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; \ + echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_8M" >> include/config.mk; \ + cp board/mv_feroceon/config/u-boot-sec64k.lds board/mv_feroceon/config/u-boot.lds; \ + echo "** RD_88F6183AP image ** config " ; \ + } + +#============================== +# Little Endian Cross Compiler +#============================== +ifeq ($(BE),) +ifeq ($(CSL),) + @echo "CROSS_COMPILE = arm-none-linux-gnueabi-" >> include/config.mk; +else + @echo "CROSS_COMPILE = $(CSL)" >> include/config.mk; +endif +endif +#============================== +# Big Endian Cross Compiler +#============================== +ifeq ($(BE),1) + @echo "MV_FLAGS += -mbig-endian -D__BE" >> include/config.mk; + @echo "BIG_ENDIAN =y" >> include/config.mk; + @echo "LDFLAGS += -EB" >> include/config.mk; +ifeq ($(CSLBE),) + @echo "CROSS_COMPILE = armeb-none-linux-gnueabi-" >> include/config.mk; +else + @echo "CROSS_COMPILE = $(CSLBE)" >> include/config.mk; +endif + @echo "** Big Endian ** config "; +endif + +#================= +# USB support +#================= +ifeq ($(USB),1) + @echo "MV_FLAGS += -DMV_USB -DCONFIG_CMD_USB" >> include/config.mk; + @echo "MV_USB=y" >> include/config.mk; + @echo "** With USB ** config " ; +endif +#================= +# NAND support +#================= +ifeq ($(NAND),1) + @echo "** NAND support image ** config " ; + @echo "MV_FLAGS += -DMV_NAND" >> include/config.mk; +endif +#================= +# Boot from NAND support +#================= +ifeq ($(NBOOT),1) + @echo "** Boot from NAND support image ** config " ; + @echo "MV_FLAGS += -DMV_NAND_BOOT" >> include/config.mk; + @echo "NAND_BOOT =y" >> include/config.mk; + @cat board/mv_feroceon/config/config_nand.mk >> board/mv_feroceon/config/config.mk; + cp board/mv_feroceon/config/u-boot-sec128k.lds board/mv_feroceon/config/u-boot.lds; +endif +#================= +# SPI support +#================= +ifeq ($(SPI),1) + @echo "** SPI support image ** config " ; + @echo "MV_FLAGS += -DMV_SPI" >> include/config.mk; +endif +ifeq ($(SPIBOOT),1) + @echo "** Boot from SPI support image ** config " ; + @echo "MV_FLAGS += -DMV_SPI" >> include/config.mk; + @echo "MV_FLAGS += -DMV_SPI_BOOT" >> include/config.mk; +endif +#================= +# MFlash support +#================= +ifeq ($(MFLASH),1) + @echo "** MFLASH support image ** config " ; + @echo "MV_FLAGS += -DMV_FLASH" >> include/config.mk; +endif +ifeq ($(MFLASHBOOT),1) + @echo "** Boot from MFLASH support image ** config " ; + @echo "MV_FLAGS += -DMV_FLASH" >> include/config.mk; + @echo "MV_FLAGS += -DMV_FLASH_BOOT" >> include/config.mk; +endif +#================= +# BOOTROM support +#================= +ifeq ($(BOOTROM),1) + @echo "** BOOTROM support image ** config " ; + @echo "MV_FLAGS += -DMV_BOOTROM" >> include/config.mk; +ifeq ($(NBOOT),1) + @cp board/mv_feroceon/config/u-boot-sec64k-header-nand.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec64k-header.lds board/mv_feroceon/config/u-boot.lds; +endif +endif +#=================== +# Tiny Image support +#=================== +ifneq ($(TINY),) + @echo "MV_FLAGS += -DMV_TINY_IMAGE" >> include/config.mk; + @echo "MV_TINY_IMAGE=y" >> include/config.mk; +ifeq ($(TINY),256K_32K) + @echo "** TINY image BootSize=256K SEC=32K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec32k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec32k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_32K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_256K" >> include/config.mk; +else +ifeq ($(TINY),256K_64K) + @echo "** TINY image BootSize=256K SEC=64K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec64k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec64k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_256K" >> include/config.mk; +else +ifeq ($(TINY),512K_64K) + @echo "** TINY image BootSize=512K SEC=64K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec64k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec64k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K" >> include/config.mk; +else +ifeq ($(TINY),4M_128K) + @echo "** TINY image BootSize=4M SEC=128K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec128k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec128k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_4M" >> include/config.mk; +else +ifeq ($(TINY),8M_128K) + @echo "** TINY image BootSize=8M SEC=128K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec128k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec128k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_8M" >> include/config.mk; +else +ifeq ($(TINY),16M_64K) + @echo "** TINY image BootSize=16M SEC=64K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec64k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec64k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_64K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; +else +ifeq ($(TINY),16M_128K) + @echo "** TINY image BootSize=16M SEC=128K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec128k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec128k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_128K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_16M" >> include/config.mk; +else +ifeq ($(TINY),256K_4K) + @echo "** TINY image BootSize=256K SEC=4K" ; +ifeq ($(BOOTROM),1) + @cp board/mv_feroceon/config/u-boot-sec4k-header-tiny.lds board/mv_feroceon/config/u-boot.lds; +else + @cp board/mv_feroceon/config/u-boot-sec4k-tiny.lds board/mv_feroceon/config/u-boot.lds; +endif + @echo "MV_IMAGE_FLAGS = -DMV_SEC_4K" >> include/config.mk; + @echo "MV_IMAGE_FLAGS += -DMV_BOOTSIZE_256K" >> include/config.mk; +else + @make mrproper; + @echo "" ; + @echo "** ERROR : Illegal TINY image configuration" ; + @echo "" ; + @echo "Legal values for TINY are :" ; + @echo "" ; + @echo "512K_64K, 16M_64K, 16M_128K, 256K_32K or 256K_4K" ; + @echo "" ; +endif +endif +endif +endif +endif +endif +endif +endif +endif +#============================= +# Summary of compilation flags +#============================= + @echo -e "CPPFLAGS += \044(MV_IMAGE_FLAGS) \044(MV_FLAGS)" >> include/config.mk; + +######################################################################### +## END of Marvell Feroceon based Socs +######################################################################### DB64360_config: unconfig @./mkconfig DB64360 ppc 74xx_7xx db64360 Marvell @@ -1840,10 +3202,13 @@ clobber: clean | xargs -0 rm -f rm -f $(OBJS) *.bak tags TAGS rm -fr *.*~ + rm -f nboot nboot.dis nboot.map rm -f u-boot u-boot.map u-boot.hex $(ALL) + rm -f u-boot-${MV_OUTPUT} rm -f tools/crc32.c tools/environment.c tools/env/crc32.c rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c rm -f include/asm/proc include/asm/arch include/asm + rm -fR images/* mrproper \ distclean: clobber unconfig diff --git a/ReleaseNotes.txt b/ReleaseNotes.txt new file mode 100644 index 0000000..305dc8d --- /dev/null +++ b/ReleaseNotes.txt @@ -0,0 +1,507 @@ +11-Nov-2009 + +Release notes for MV88F6281A/MV88F6192A/MV88F6180A/MV88F6280A/MV88F6282A U-Boot, release: 3.4.25 +================================================================================================= + +Table of Contents +----------------- +1. Contents of Release +2. Supported boards/CPU's/ +3. How to build and burn U-Boot. +4. Changes from Previous Releases +5. Known Issues +6. Disclaimer + + + +1. Contents of Release (n) +========================== + + Included in current release: + + -) U-Boot source code patch (for u-boot-1.1.4) version 3.4.25 + + -) Support + - Little/Big endian + - Uart 0 + - Auto detect of PEX 0 + - Reset. + - RTC. + - Gigabit Ethernet ports. + Port 0 and 1 in RGMII mode + - XOR. + - SPI Flash + - NAND Flash + - JFFS over SPI or NAND + - SATA IDE and SATA port multiplier + - EXT2, FAT and FAT32 file systems + - Exceptions + - USB flash drive support + - MMC/SDIO support + + + +2. Supported boards/CPU's +============================ + + This U-Boot version supports the following boards: + + Boards + ====== + DB-88F6281A-BP + DB-88F6192A-BP + RD-88F6281A + RD-88F6192A + DB-88F6180A-BP + DB-88F6281A-SHEEVA_PLUG + DB-88F6280A-BP + DB-88F6282A-BP + +3. How to build and Burn U-Boot +=============================== + + Building U-Boot + =============== + + -) Download U-Boot release 1.1.4 from ftp://ftp.denx.de/pub/u-boot/. + + -) Update the U-Boot 1.1.4 release by copying the patch of this release. + + -) Update the U-Boot Makefile to point to the cross compiler in your host + machine, arm-none-linux-gnueabi cross compiler. + + -) Build the U-Boot binaries as follows: + + + -) For DB-88F6281-BP LE + > make mrproper + -) NAND + > make db88f6281abp_config NBOOT=1 LE=1 + -) SPI + > make db88f6281abp_config SPIBOOT=1 LE=1 + -) SPI with NAND support + > make db88f6281abp_config SPIBOOT=1 LE=1 NAND=1 + > make -s + + -) For DB-88F6192A-BP LE + > make mrproper + -) NAND + > make db88f6192abp_config NBOOT=1 LE=1 + -) SPI + > make db88f6192abp_config SPIBOOT=1 LE=1 + -) SPI with NAND support + > make db88f6192abp_config SPIBOOT=1 LE=1 NAND=1 + > make -s + + -) For RD-88F6281A LE + > make mrproper + -) NAND + > make rd88f6281a_config NBOOT=1 LE=1 + -) SPI + > make rd88f6281a_config SPIBOOT=1 LE=1 + -) SPI with NAND support + > make rd88f6281a_config SPIBOOT=1 LE=1 NAND=1 + > make -s + + -) For RD-88F6192A LE + > make mrproper + -) SPI + > make rd88f6192a_config SPIBOOT=1 LE=1 + > make -s + + -) For DB-88F6180-BP LE + > make mrproper + -) NAND + > make db88f6180abp_config NBOOT=1 LE=1 + -) SPI + > make db88f6180abp_config SPIBOOT=1 LE=1 + -) SPI with NAND support + > make db88f6180abp_config SPIBOOT=1 LE=1 NAND=1 + > make -s + + -) For SHEEVA PLUG LE + > make mrproper + -) NAND + > make rd88f6281Sheevaplug_config NBOOT=1 LE=1 + > make -s + + -) For DB-88F6280-BP LE + > make mrproper + -) NAND + > make db88f6280abp_config NBOOT=1 LE=1 + -) SPI + > make db88f6280abp_config SPIBOOT=1 LE=1 + -) SPI with NAND support + > make db88f6280abp_config SPIBOOT=1 LE=1 NAND=1 + > make -s + + -) For DB-88F6282-BP LE + > make mrproper + -) NAND + > make db88f6282abp_config NBOOT=1 LE=1 + -) SPI + > make db88f6282abp_config SPIBOOT=1 LE=1 + -) SPI with NAND support + > make db88f6282abp_config SPIBOOT=1 LE=1 NAND=1 + > make -s + +* For BE use BE=1 + + -) The BootRom header files are located in the source root directory: + -> dramregs_400rd_A.txt + -> dramregs_400db_A.txt + -> dramregs_200rd_A.txt + -> dramregs_200db_A.txt + -> dramregs_200db619x_A.txt + -> dramregs_200db6280_A.txt + + The files have predefined register settings for the different SDRAM configurations and required errata. + The matching header file is appended to the U-boot image during the make process according to the device + and board type, using the doimage utility which is located in the /tools directory. The output file to be + burnt on boot ROM depends on the make parameters: + -> NBOOT=1 : u-boot-__nand.bin + -> SPIBOOT=1 : u-boot-__flash.bin + + The file u-boot-__uart.bin is used for debug purposes for booting the + U-boot image through the UART port. + + Burning U-Boot + ============== + + If burning the new U-Boot image to an board the already runs a previous U-Boot image the following sequence + can be used to load the image using tftp to the board and burn it: + 1. Start a tftp server on the host PC, whose directory is set to point to the directory contaning the + new U-Boot bin image. + 2. Connect an Ethernet cable to the RJ-45 connector of the board. + 3. Configure the U-Boot environment parameters using the following commands: + > setenv serverip xx.xx.xx.xx (xx.xx.xx.xx should be the IP address of the PC runing the tftp server) + > setenv ipaddr yy.yy.yy.yy (yy.yy.yy.yy should be some IP address with the same subnet as the server) + 4. run the bubt command to load and burn the U-Boot image: + > bubt u-boot-__.bin + 5. Once the image is loaded the user is asked whether the environment parameters should be overwritten or not + , and answering y or n to thios question will start the burn process. + 6. Once the burn is complete the board can be restarted, and the new U-Boot image will be run. + + *** When upgrading U-boot from an older revision than 3.4.10, then after step 6 is done and U-boot 3.4.10 is up and running + need to repeat steps 3-6 again on the same image of U-boot 3.4.10 (and up) and re-burn it. The reason is that from U-boot + 3.4.10 and on NAND ECC uses 4-bit for the U-boot image and environment in the NAND, and when using an older U-boot to burn + it, it is written using 1-bit ECC, which is not correct. Using the newly burnt U-boot 3.4.10 (and on) to burn the image + again will use 4-bit ECC. + + In case the original U-Boot image was damaged, or when whishing to burn a different boot device than the current one, + the U-Boot command cannot be used, and a debugger is required to load the U-Boot ELF image into the SDRAM, using the + following procedure: + 1. Connect a debugger (Marvell uses a Lauterbach debugger, so the supplied scripts are written for this type of debugger) + to the debugger port of the board. + 2. From the file menue of the debugger SW choose the "run batch file" option and load the cmm file suiting the system: + - kw_dimm400.cmm for 88F6281 running at frequencies above 200MHz. + - kw_dimm200.cmm for all other options. + 3. From the file menue of the debugger SW choose the "load" option and load the U-Boot ELF file (The one without any extension). + 4. Once the loading is done change the following using the debugger SW: + - CPU PC to 0x670000. + - Configure the required MPPs to either NAND or SPI according to the required boot method using the debugger SW command line: + + For NAND boot: + - D.S SD:0xD0010000 %LE %LONG 0x01111111 + - D.S SD:0xD0010008 %LE %LONG 0x551111 + + For SPI boot: + - For DB-6180, DB-6280 and RD-6192: + + D.S SD:0xD0010000 %LE %LONG 0x01112222 + For all other boards: + + D.S SD:0xD0010000 %LE %LONG 0x21112220 + - D.S SD:0xD0010008 %LE %LONG 0x551111 + 5. Start the CPU by pressing "Go" in the debugger SW, and the loaded U-Boot image will boot the board, and now the new image can + be burnt to the required boot device using the bubt command. + +4. Recovery and Upgrade of Linux Image using USB Flash Drive +============================================================ + + 4.1 Requirements: + ----------------- + - UBOOT + - Flash drive + - Kernel compiled with ram_disk support. + - Static mapping (Kernel) or dynamic mapping (Uboot) of your MTD flash partitions. + + 4.2 Introduction: + ----------------- + Today, in order to “burn†a new file system we need to have NFS server with TFTP server, + this way is too complex and takes long time for setting up and configuring, and usually requires additional hardware. + In order to simplify the process UBOOT contains USB recovery feature (the older tftp method is also supported in case recovery is + executed and no flash drive is inserted), it enables you to put “flashware†image on USB, Load the image from the UBOOT level + and boot Linux. + + 4.3 Recovery Process: + --------------------- + 1. Power on + 2. If flash drive is inserted into the USB connector the UBOOT searches for flashware.img file (On either FAT or ext2 FS). + 3. If flashware.img exists the UBOOT will load the file to RAM starting from $loadaddr ( 0x2000000 ) + 4. When finished loading the image to RAM the UBOOT will invoke new bootcmd (Based on the image parameters, the below line is an example): + setenv bootargs $(console) root=/dev/ram0 rootfstype=squashfs initrd=0x2200000,0x626d64c ramdisk_size=100789 recovery=usb ser + verip=10.4.50.5; bootm 0x2000000; + + * The USB flash drive should contain recovery image – squashfs and the file system image. + For example: + - flashware.img (30M) – basic squashfs rootfs + - ubuntu_9.0.4_jffs2 – (140M) – your SW image. + + You can add more files as needed + + 4.4 How to create the recovery image? + ------------------------------------- + create basic squashfs from your minimal root file system (Ubuntu, RedHat, etc) with mkfs.squashfs + Change the init scripts of the filesystem to mount the flash drive and flash_erase, nand_write your SW image. + Reboot – the UBOOT will load the default bootcmd. + + +5. Changes from Previous Releases +================================= + + U-boot 3.4.25 + ============= + -) Fixed in mv_main.c the initialization of nandEnvBase in order to solve a probel caused to the console variable. + + U-boot 3.4.24 + ============= + -) Fixed in mv_main.c the initialization of nandEnvBase from "" assignment of the env variable which caused wrong display of "" in the mmcinit command to strcpy. + -) Fixed nand mark bad function in nand_base.c to support non sector aligned addresses. + -) Changed device number 1155 to 6282 + -) Fixed in nand_base.c the string assignments to nandEcc parameter which caused it to overflow into other strings. + + + U-boot 3.4.23 + ============= + -) excluded RD-6281 from audio shut down in mv_main.c. + -) rolled back the fix in armlinux.c which was made in 3.4.22 (returned to previous state). + + + U-boot 3.4.22 + ============= + -) Fixed network name assignment for recovery on the RD-6281 in mv_main.c and armlinux.c in order to fix problem in port assignment in Linux when performing recovery. + -) Added support for 88F6280 device. + -) Added support for 88F1155 device. + + U-boot 3.4.21 + ============= + -) Added a HUB port reset in usb.c prior to first descriptor fetch in order to solve problem for certain flash drives. + + U-boot 3.4.20 + ============= + -) Override USB low speed devices connected to a USB hub since we do not know how to handle them. + -) Aligned stack pointer to 8 bytes. + -) Added the switchRegRead/switchRegWrite commands to support also indirect phy access to switches. + + U-boot 3.4.19 + ============= + -) Added SDIO MMC support. + -) Added FAT32 support. + -) Updated NAND stack: + -) Added support for NAND bad block skipping for bubt and environment commands. + -) Fixed NAND ECC RS calculation algorithm. + -) Added NAND write verification. + -) Added "nandEnvBase" variable that holds the offset of the environment start in the nand flash to be used by the bootcmd for Linux + in case the NAND contains bad blocks and the environment is relocated to a different block. + -) Added support for NAND devices with pages larger than 2048 bytes, and updated nand stack in nand_base to support automatic identification and usage + of parameters for large page NAND devices. + -) Fixed endianess issue in nand_base.c nand read and nand verify for BE operation. + -) Added NAND I/F register values to the board structures in mvBoardEnvSpec.c in order to configure the NAND interface parameters + (in mvBoardEnvInit()) correctly for each board. + -) Fixed dos_part code to support unpartitioned USB drives. + + U-boot 3.4.18 + ============= + -) Fixed RD-6281 Fan and HDD power enable functions to access correct entry in the TWSI expander struct. + + U-boot 3.4.17 + ============= + -) Enabled P2DWr bit in register 0x1404 in bootrom header files for 400Mhz configurations. + -) Changed switch driver to get the single chip or multi chip device from switch structure in boardEnvSpec.c + -) Added diagnostic tests under /diag directory. Compiled when adding DIAG=1 during make configuration. + -) Updated SSCG configuration register setting according to FE-MISC-90. + -) Improved HDD detection. Fixed mv_ide.c. + -) Unified sources with other Feroceon core device streams. + -) Fixed NAND flash ECC algorithm for 1bit ECC. + -) Added pcieTune environment variable, which when set to "yes" performs tuning of the pci-e buffers. + -) Added ethact, ethaddr and eth1addr parameters in the bootargs variable when doing recovery in order to pass Linux the I/F + from which recovery takes place, and the MAC of the ports. + -) Improved nand read performance when accessing aligned offset and size by using 4 byte bursts instead of 1 byte accesses. + -) When initializing the 6161 GbE switch changed the write to the RGMII register to a RMW operation as required. + -) Removed WA for erratum GL-CPU-70. + -) Fixed the commands sp, me, se + -) Improved NAND ECC correction routine for faster operation when using 4-bit ECC. + -) Changed SPI access code for environment operations to use indirect SPI access, in order to have enough CS de-select timing. + -) Updating L2 configuration registers (0x20134 and 0x20138) in the bootrom header files. + -) Updated mv_ide.c file to support UDMA mode for drives that do not support UDMA mode 5. + + U-boot 3.4.16 + ============= + -) Updated timing parameter in SATA initialization. + -) Fixed MPP definition for Sheeva plug board. + -) Added MII module support. + -) Fixed nand_base.c to support OOB for smaller sized nand devices. + -) Added SheevaPlug recovery boot command setting + + + U-boot 3.4.15 + ============= + -) Improved the RS nand ECC calculation to speed things up. + -) Updated SDRAM parameters in bootrom header files. (reg 0x1404 [27:24] ; reg 0x140c [10:9]) + -) Added WA for the RD-6281 board erratum for the swapped MDI polarity of the switch connector. + + + U-boot 3.4.14 + ============= + -) Updated USB PHY Rx Control Register 0x50430 initialization according to lates guidelines For EL15, EL16, and EL 17. + -) Added FTDLL update to bootrom header file for 619x devices, which adds a new header file for the DB-88f619x-A-BP called dramregs_200db619x_A.txt + + + U-boot 3.4.13 + ============= + -) Added support for USB host to be able to load files from a DOK (FS support for FAT and EXT2). The new commands are "usb" + , "fatls", "fatload", "ext2ls", "ext2load". + -) Recovery process now tries by default to recover from FAT DOK -> EXT2 DOK -> network. + -) Removed from bootrom header files initialization for CPU registers 0x20134 and 0x20138 due to an Erratum that was fixed. + -) Patched the ext2fs.c driver to support large nodes and improved reading speed. + -) Added auto detection of TCLK for 88F6281 device which supports 166/200MHz, and updated the SatR command to support TCLK configuration. + + + U-boot 3.4.12 + ============= + -) Fixed udelay() function which previously didn't operate correctly and didn't do any delays for vlaues <1000us, and + didn't do correct delays for values >1000us. This may have influenced any function that used the udelay() function. + + + U-boot 3.4.11 + ============= + -) Fixed a bug in the NAND ECC calculation when using 1bit ECC which caused a page to be marked bad. + -) Changed the "nandEcc" environment variable to accept "1bit" or "4bit" (previously "RS"). + -) Set the default value for the NAND ECC environment to be 1bit (when it is not set) regardless of + the NAND size. + -) When GMII module is used ports 0 & 1 are configured to GMII mode. + -) Fixed a bug in the imm/imd I2C access commands which occured when accessing EPROM of more than 256 bytes. + + + U-boot 3.4.10 + ============= + -) increased the recovery file maximum load size from 32MB to infinite. + -) NAND ECC UBoot and environment use Reed-Solomon whenever the page size is 2048 bytes or more, + and the rest of NAND is defined by the environment variable "nandEcc" which can either be "RS" + or "1bit". If the variable is not defined then the default for a page size below 2048 is 1bit + and for 2048 or more RS. + -) Stack is cacheable for monitor extension mode + -) Added environment variable "nandEccAcc", which when set to "yes" together with "enaMonExt" + accelerates the NAND access and ECC calculation by using cacheable execution. + -) Fixed mvBoardMppMuxSet() setting values accodring to modules, and MPP settings for the audio and + TDM modules. + -) Work around in jump.s for the bug of the PEX wrong device ID for 619x. + + + U-boot 3.4.9 + ============ + -) Fixed MPP definitions and board structs in mvBoardEnvSpec. + -) Fixed bug in the parsing of the MTU parameter passed to Linux, and added a default value of 1500. + -) Fixed doimage.c to support 64 bit Linux host (previouse version caused segmentation fault). + + + U-boot 3.4.8 + ============ + -) Added support for PEX/PCI SATA controller on DB-6180-A-BP. + -) Added Lauterbach cmm files for loading ELF image. + + + U-boot 3.4.7 + ============ + -) Updated SDRAM ODT configuration in the BootRom header files to latest design guide recommendations. + -) Added support DB-88F6180A-BP. + -) Added support for customer board addition to the U-Boot tree (DB_CUSTOMER define) + -) Fixed MPP definitions for SPI + NAND support. + + + U-boot 3.4.6 + ============ + -) Changed the default boot environment for phonetools parameters to fxs:fxs. + -) Added support for NAND flash when booting from SPI. + + + U-boot 3.4.5 + ============ + -) Created separate header files for the bootrom for 400MHz RD and DB and updated SDRAM register values. + -) Initialized the SSCG configuration register. + -) moved Switch drivers to the USP directory. + -) Added WA for Erratum FE-MISC-70 + + + U-boot 3.4.4 + ============ + -) updated SATA PHY values to the latest recommendations. + -) In the RD-6281A enabled the HDD power and fan power on start. + -) Added support for RD-88F6192A board. + + + U-boot 3.4.3 + ============ + -) Added support for RD-88F6281A. + -) Fixed mv_egiga.c mvEgigaHalt() function which caused memory leakage due to unreleased buffers. + -) Removed doimage.c error message during the make process. + -) REmoved 4bit Reed-Solomon ECC from NAND driver due to significant slow down it caused. + + + U-boot 3.4.2 + ============ + -) Fixed bug in Reed-Solomon algorithm when doing "nand erase clean" command. + + U-boot 3.4.1 + ============ + -) Added support for 88F6192-A0 & 88F6281-A0 + -) Removed support for 88F6192-Z0 & 88F6281-Z0 + -) Changed Linux bootcmd to boot from 0x2000000 + -) Added support for NAND flash when booting from SPI. + -) Added the doimage and bootrom header addition into the make process. + -) Added Reed-Solomon ECC support for large page NAND. + + + U-boot 3.1.9 + ============ + -) Remove mvPci.c from Makfile + -) Add setting for both RGMII delay option in Marvell PHY 1116. + -) Fix MPP output voltage setting when working in RGMII mode. + -) Fix Marvell switch 6165 SMI address to 0x0. + -) Fix CFG_HZ to 1000, cause for overflow in calculation of timeout. + -) Change the definition of Marvell READ_TIMER in interrupts.c to return the value in 1mSec granularity. + -) Remove gateway IP and net mask from CFG_BOOTARGS_END. + -) Fix PCI-Express configuration of root complex or end point. + -) Enable silent mode in compilation only. + -) Code cleanup. + + U-boot 3.1.6 + ============ + -) Fix calculation of week day in integrated RTC driver. + -) Fix MPP output drive for 1.8V interfaces. + -) Add support for RGMII module detection in DB-88F6192-BP. + -) Add synchronise function for bridge reorder. + -) Add HDD power control for RD-6192. + -) Add mainlineLinux environment variable. + -) Add vxworks_en environment variable for vxWorks boot over U-boot. + -) Change mvPhoneConfig second interface default to "FXO". + -) Add 88E6165/61 SMI timeout and busy polling. + -) Add big endian support. + -) Fix ide read/write in case of size parameter equal 0. + -) Code cleanup. + + + +6. Known issues +=============== + + -) DRAM is fixed size and timing parameters in the image header. + -) SATA controller 6042 not supported (Hangs board). + -) When performing "nand erase clean" the OOB clean marker isn't compliant with JFFS2 definitions. + + +7. Disclaimer +============= +This document provides preliminary information about the products described, and such information should not be used for purpose of final design. Visit the Marvell® web site at www.marvell.com for the latest information on Marvell products. + +No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell makes no commitment either to update or to keep current the information contained in this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. The user should contact Marvell to obtain the latest specifications before finalizing a product design. Marvell assumes no responsibility, either for use of these products or for any infringements of patents and trademarks, or other rights of third parties resulting from its use. No license is granted under any patents, patent rights, or trademarks of Marvell. These products may include one or more optional functions. The user has the choice of implementing any particular optional function. Should the user choose to implement any of these optional functions, it is possible that the use could be subject to third party intellectual property rights. Marvell recommends that the user investigate whether third party intellectual property rights are relevant to the intended use of these products and obtain licenses as appropriate under relevant intellectual property rights. +Marvell comprises Marvell Technology Group Ltd. (MTGL) and its subsidiaries, Marvell International Ltd. (MIL), Marvell Semiconductor, Inc. (MSI), Marvell Asia Pte Ltd. (MAPL), Marvell Japan K.K. (MJKK), Marvell Semiconductor Israel Ltd. (MSIL), SysKonnect GmbH, and Radlan Computer Communications, Ltd. +Export Controls. With respect to any of Marvell’s Information, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) in the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. +Copyright © 2004. Marvell. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, and GalNet are registered trademarks of Marvell. Discovery, Fastwriter, GalTis, Horizon, Libertas, Link Street, NetGX, PHY Advantage, Prestera, Raising The Technology Bar, UniMAC, Virtual Cable Tester, and Yukon are trademarks of Marvell. All other trademarks are the property of their respective owners. diff --git a/System.map b/System.map new file mode 100644 index 0000000..722150f --- /dev/null +++ b/System.map @@ -0,0 +1,1786 @@ +00600000 T _start +00600020 t _undefined_instruction +00600024 t _software_interrupt +00600028 t _prefetch_abort +0060002c t _data_abort +00600030 t _not_used +00600034 t _irq +00600038 t _fiq +00600040 T _TEXT_BASE +00600044 T _armboot_start +00600048 T _bss_start +0060004c T _bss_end +00600050 t reset +00600064 t relocate +00600084 t copy_loop +00600094 t stack_setup +006000a0 t clear_bss +006000ac t clbss_l +006000c0 t _start_armboot +006000c4 t cpu_init_crit +006000e0 t cpu_926 +006000f0 t cpu_946 +006000fc t cpu_continue +00600130 t kw_a1 +00600140 T _dcache_index_max +00600144 T _dcache_index_inc +00600148 T _dcache_set_max +0060014c T _dcache_set_index +00600150 T cpu_dcache_flush_all +00600164 t Lnext_set_inv +00600168 t Lnext_index_inv +0060018c T cpu_icache_flush_invalidate_all +006001a0 t undefined_instruction +00600200 t software_interrupt +00600260 t prefetch_abort +006002c0 t data_abort +00600320 t not_used +00600380 t irq +006003e0 t fiq +00600460 t jumpStart +00600460 T lowlevel_init +006004b4 t done +006004c8 T _i2cInit +00600500 t _twsiDelay +00600504 t _twsiDelayLoop +00600510 T _i2cRead +0060052c t loop_1 +00600544 t loop_1_timeout +00600548 t loop_2 +00600560 t loop_2_timeout +00600564 t loop_3 +0060057c t loop_3_timeout +006005a4 t loop_4 +006005b8 t loop_5 +006005c8 t testStatus +006005ec t great_than_256 +00600618 t loop_6_1 +00600628 t loop_7_1 +00600648 t after_offset +00600664 t loop_6 +00600674 t loop_7 +006006b4 t loop_9 +006006c4 t loop_8 +006006d4 t loop_10 +00600710 t loop_11 +00600720 t loop_12 +0060074c t loop_14 +0060075c t loop_15 +006007a4 t loop_16 +006007b4 t exit_i2cRead +006007cc t flash_in_which_sec +0060084c t checksum8 +00600878 T bfGetWolStatus +006009d8 T bfTestWol +00600b50 T do_rcvr +00600b68 T do_satr +00600fe0 T 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+00670030 b Count.5267 +00670034 B sampleAtResetTargetArray +00670038 b accessProtReg.4033 +0067003c b mvFlashInfo +0067477c b sFlashBanksNum +00674780 B g_stack_cachable +00674800 B request_q +00674900 B response_q +00674908 b ide_dev_desc +00675608 b command_completed +0067560c b completion_type +00675610 B sataAdapters +00677e20 B prd_table +00677e40 B hdd_found +00677e44 b ide_detected +00677e48 b ide_initiated +00678000 b tmp_string +00678064 b tmp_string1 +006780c8 B ethPortCtrl +006780d0 B ethDescInSram +006780d4 B ethDescSwCoher +006780d8 B mvTsuCtrl +006780e8 B mvTsuPortCtrl +00678180 b bfWolPatternString +00678200 b timestamp +00678208 b lastdec +00678210 b mem_malloc_brk +00678214 b mem_malloc_start +00678218 b mem_malloc_end +0067821c B monitor_flash_len +00678220 B ext2fs_root +00678224 B indir1_block +00678228 B indir1_size +0067822c B indir2_block +00678230 B indir2_size +00678234 B ext2fs_file +00678238 B symlinknest +0067823c b part_info +0067828c b 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NetBootFileSize +0067a7e6 B BootFile +0067a868 b TftpState +0067a86c b tftp_filename +0067a870 b TftpBlock +0067a874 b TftpServerPort +0067a878 b TftpOurPort +0067a87c b default_filename +0067a88c b TftpTimeoutCount +0067a890 b TftpBlockWrap +0067a894 b TftpBlockWrapOffset +0067a898 b TftpLastBlock +0067a89c B BootpTry +0067a8a0 B BootpID +0067a8a4 B RarpTry +0067a8a8 b eth_current +0067a8ac b eth_devices +0067a8b0 b first_failed.2996 +0067a8b4 B peerTID +0067a8b8 B myTID +0067a8bc B imagePtr +0067a8c0 B rcvr_state +0067a8c4 B packetNum +0067a8c8 B flash_info +0067c704 B console_buffer +0067cb04 B header +0067cb44 B extraBootArgs +0067cc0c B devices +0067cc14 b current_dev +0067cc18 b current_partnum +0067cc19 b last_partition +0067cc29 b last_parts +0067ce2c B mtdids +0067ce34 b initialized.3307 +0067ce38 b last_ids +0067ceb8 b base_address +0067cebc B mm_last_addr +0067cec0 B mm_last_size +0067cec4 B dp_last_addr +0067cec8 B dp_last_size +0067cecc b tmp_buf.2582 +0067d0cc b tmp_buf +0067d4cc b ctrlc_disabled +0067d4d0 b ctrlc_was_pressed +0067d4d4 B devlist +0067d4d8 B stdio_devices +0067d4e4 b top_pad +0067d4e8 b n_mmaps_max +0067d4ec b current_mallinfo +0067d514 b max_sbrked_mem +0067d518 b max_total_mem +0067d51c b local.2656 +0067d532 b map +0067d634 b top_vars +0067d638 b flag_repeat +0067d63c b do_repeat +0067d640 b the_command.2683 +0067da40 b buf.3134 +0067da68 B last_return_code +0067da6c b ifs +0067da70 B nesting_level +0067da74 b asynch_allowed +0067da78 b usb_dev +0068b378 b usb_hub_index +0068b37c b hub_dev +0068b47c b dev_index +0068b480 b setup_packet +0068b488 b hubIndex +0068b48c b running +0068b490 B usb_started +0068b498 b usb_dev_desc +0068b6a0 b usb_ccb +0068b730 b usb_stor_buf +0068b930 b usb_max_devs +0068b934 b usb_stor +0068ba38 B ___strtok +0068ba3c b fixed_mem +0068cacc b fixed_lock +0068cad0 b fixed_built +0068cad4 b fixed_bl +0068cad8 b fixed_tl +0068cadc b fixed_bd +0068cae0 b fixed_td +0068cae4 B egiga_init +0068cae8 b mmc_dev +0068cb50 b resp.2791 +0068cb60 b is_sdhc +0068cb68 b mmc_csd +0068cb80 b rca +0068cb84 b mmc_ready +0068cb88 b mmc_buf +0068cd88 b uartBase +0068cd90 b uart_off +0068cd94 b params +0068cd98 B super +0068cde4 b stream +0068ce18 b part_offset +0068ce1c b cur_dev +0068ce20 B get_vfatname_block +0069ce20 B do_fat_read_block +006ace20 B get_dentfromdir_block +006bce20 b current_part +006bce40 b ntds.2884 +006bce60 b qh.2882 +006bcea0 b td.2883 +006bcf20 b hccr +006bcf24 b hcor +006bcf40 b qh_list +006bcf70 b rootdev +006bcf74 b portreset +006bcf80 A _end diff --git a/UART_boot_file.zip b/UART_boot_file.zip new file mode 100644 index 0000000..7a7e469 Binary files /dev/null and b/UART_boot_file.zip differ diff --git a/board/AtmarkTechno/suzaku/Makefile b/board/AtmarkTechno/suzaku/Makefile deleted file mode 100644 index 7a17067..0000000 --- a/board/AtmarkTechno/suzaku/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/AtmarkTechno/suzaku/config.mk b/board/AtmarkTechno/suzaku/config.mk deleted file mode 100644 index 7bbf2b1..0000000 --- a/board/AtmarkTechno/suzaku/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2004 Atmark Techno, Inc. -# -# Yasushi SHOJI -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x80F00000 - -PLATFORM_CPPFLAGS += -mno-xl-soft-mul -PLATFORM_CPPFLAGS += -mno-xl-soft-div -PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/AtmarkTechno/suzaku/flash.c b/board/AtmarkTechno/suzaku/flash.c deleted file mode 100644 index 49a0673..0000000 --- a/board/AtmarkTechno/suzaku/flash.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -unsigned long flash_init(void) -{ - return 0; -} - -void flash_print_info(flash_info_t *info) -{ -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - return 0; -} - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - return 0; -} diff --git a/board/AtmarkTechno/suzaku/suzaku.c b/board/AtmarkTechno/suzaku/suzaku.c deleted file mode 100644 index afe124a..0000000 --- a/board/AtmarkTechno/suzaku/suzaku.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This is a board specific file. It's OK to include board specific - * header files */ -#include - -void do_reset(void) -{ - *((unsigned long *)(MICROBLAZE_SYSREG_BASE_ADDR)) = MICROBLAZE_SYSREG_RECONFIGURE; -} diff --git a/board/AtmarkTechno/suzaku/u-boot.lds b/board/AtmarkTechno/suzaku/u-boot.lds deleted file mode 100644 index 00a8ef7..0000000 --- a/board/AtmarkTechno/suzaku/u-boot.lds +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(microblaze) -ENTRY(_start) - -SECTIONS -{ - .text ALIGN(0x4): - { - __text_start = .; - cpu/microblaze/start.o (.text) - *(.text) - __text_end = .; - } - - .rodata ALIGN(0x4): - { - __rodata_start = .; - *(.rodata) - __rodata_end = .; - } - - .data ALIGN(0x4): - { - __data_start = .; - *(.data) - __data_end = .; - } - - .u_boot_cmd ALIGN(0x4): - { - . = .; - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - - .bss ALIGN(0x4): - { - __bss_start = .; - *(.bss) - __bss_start = .; - } -} diff --git a/board/LEOX/elpt860/Makefile b/board/LEOX/elpt860/Makefile deleted file mode 100644 index 3e73163..0000000 --- a/board/LEOX/elpt860/Makefile +++ /dev/null @@ -1,48 +0,0 @@ - -####################################################################### -# -# Copyright (C) 2000, 2001, 2002, 2003 -# The LEOX team , http://www.leox.org -# -# LEOX.org is about the development of free hardware and software resources -# for system on chip. -# -# Description: U-Boot port on the LEOX's ELPT860 CPU board -# ~~~~~~~~~~~ -# -####################################################################### -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -####################################################################### - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/LEOX/elpt860/README.LEOX b/board/LEOX/elpt860/README.LEOX deleted file mode 100644 index 9052b09..0000000 --- a/board/LEOX/elpt860/README.LEOX +++ /dev/null @@ -1,424 +0,0 @@ -============================================================================= - - U-Boot port on the LEOX's ELPT860 CPU board - ------------------------------------------- - -LEOX.org is about the development of free hardware and software resources - for system on chip. - -For more information, contact The LEOX team - -References: -~~~~~~~~~~ - 1) Get the last stable release from denx.de: - o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2 - 2) Get the current CVS snapshot: - o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login - o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot - -============================================================================= - -The ELPT860 CPU board has the following features: - -Processor: - MPC860T @ 50MHz - - PowerPC Core - - 65 MIPS - - Caches: D->4KB, I->4KB - - CPM: 4 SCCs, 2 SMCs - - Ethernet 10/100 - - SPI, I2C, PCMCIA, Parallel - -CPU board: - DRAM: 16 MB - - FLASH: 512 KB + (2 * 4 MB) - - NVRAM: 128 KB - - 1 Serial link - - 2 Ethernet 10 BaseT Channels - -On power-up the processor jumps to the address of 0x02000100 - -Thus, U-Boot is configured to reside in flash starting at the address of -0x02001000. The environment space is located in NVRAM separately from -U-Boot, at the address of 0x03000000. - -============================================================================= - - U-Boot test results - -============================================================================= - - -################################################## -# Operation on the serial console (SMC1) -############################## - -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) - -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present - *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** -Board: ### No HW ID - assuming ELPT860 -DRAM: 16 MB -FLASH: 512 kB -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET - -Type "run nfsboot" to mount root filesystem over NFS - -Hit any key to stop autoboot: 0 -LEOX_elpt860: help -askenv - get environment variables from stdin -autoscr - run script from memory -base - print or set address offset -bdinfo - print Board Info structure -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -cmp - memory compare -coninfo - print console devices and informations -cp - memory copy -crc32 - checksum calculation -echo - echo args to console -erase - erase FLASH memory -flinfo - print FLASH memory information -go - start application at address 'addr' -help - print online help -iminfo - print header information for application image -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loop - infinite loop on address range -md - memory display -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nm - memory modify (constant address) -printenv- print environment variables -protect - enable or disable FLASH write protection -rarpboot- boot image via network using RARP/TFTP protocol -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -sleep - delay execution for some time -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -version - print monitor version -? - alias for 'help' - -################################################## -# Environment Variables (CFG_ENV_IS_IN_NVRAM) -############################## - -LEOX_elpt860: printenv -bootdelay=5 -loads_echo=1 -baudrate=9600 -stdin=serial -stdout=serial -stderr=serial -ethaddr=00:03:ca:00:64:df -ipaddr=192.168.0.30 -netmask=255.255.255.0 -serverip=192.168.0.1 -nfsserverip=192.168.0.1 -preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo -gatewayip=192.168.0.1 -ramargs=setenv bootargs root=/dev/ram rw -rootargs=setenv rootpath /tftp/${ipaddr} -nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${nfsserverip}:${rootpath} -addip=setenv bootargs ${bootargs} ip=${ipaddr}:${nfsserverip}:${gatewayip}:${netmask}:${hostname}:eth0: -ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm -nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm -bootcmd=run ramboot -clocks_in_mhz=1 - -Environment size: 730/16380 bytes - -################################################## -# Flash Memory Information -############################## - -LEOX_elpt860: flinfo - -Bank # 1: AMD AM29F040 (4 Mbits) - Size: 512 KB in 8 Sectors - Sector Start Addresses: - 02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000 - 02050000 02060000 02070000 - -################################################## -# Board Information Structure -############################## - -LEOX_elpt860: bdinfo -memstart = 0x00000000 -memsize = 0x01000000 -flashstart = 0x02000000 -flashsize = 0x00080000 -flashoffset = 0x00030000 -sramstart = 0x00000000 -sramsize = 0x00000000 -immr_base = 0xFF000000 -bootflags = 0x00000001 -intfreq = 50 MHz -busfreq = 50 MHz -ethaddr = 00:03:ca:00:64:df -IP addr = 192.168.0.30 -baudrate = 9600 bps - -################################################## -# Image Download and run over serial port -# hello_world (S-Record image) -# ===> 1) Enter "loads" command into U-Boot monitor -# ===> 2) From TeraTerm's bar menu, Select 'File/Send file...' -# Then select 'hello_world.srec' with the file browser -############################## - -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) - -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present - *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** -Board: ### No HW ID - assuming ELPT860 -DRAM: 16 MB -FLASH: 512 kB -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET - -Type "run nfsboot" to mount root filesystem over NFS - -Hit any key to stop autoboot: 0 -LEOX_elpt860: loads -## Ready for S-Record download ... -S804040004F3050154000501709905014C000501388D -## First Load Addr = 0x00040000 -## Last Load Addr = 0x0005018B -## Total Size = 0x0001018C = 65932 Bytes -## Start Addr = 0x00040004 -LEOX_elpt860: go 40004 This is a test !!! -## Starting application at 0x00040004 ... -Hello World -argc = 6 -argv[0] = "40004" -argv[1] = "This" -argv[2] = "is" -argv[3] = "a" -argv[4] = "test" -argv[5] = "!!!" -argv[6] = "" -Hit any key to exit ... - -## Application terminated, rc = 0x0 - -################################################## -# Image download and run over ethernet interface -# Linux-2.4.4 (uImage) + Root filesystem mounted over NFS -############################## - -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) - -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present - *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** -Board: ### No HW ID - assuming ELPT860 -DRAM: 16 MB -FLASH: 512 kB -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET - -Type "run nfsboot" to mount root filesystem over NFS - -Hit any key to stop autoboot: 0 -LEOX_elpt860: run nfsboot -ARP broadcast 1 -TFTP from server 192.168.0.1; our IP address is 192.168.0.30 -Filename '/home/leox/uImage'. -Load address: 0x400000 -Loading: ################################################################# - ############################# -done -Bytes transferred = 477294 (7486e hex) -## Booting image at 00400000 ... - Image Name: Linux-2.4.4 - Image Type: PowerPC Linux Kernel Image (gzip compressed) - Data Size: 477230 Bytes = 466 kB = 0 MB - Load Address: 00000000 - Entry Point: 00000000 - Verifying Checksum ... OK - Uncompressing Kernel Image ... OK -Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002 -On node 0 totalpages: 4096 -zone(0): 4096 pages. -zone(1): 0 pages. -zone(2): 0 pages. -Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.1:/tftp/192.168.0.30 ip=192.168.0.30:192.168.0.1:192.168.0.1:255.255.255.0::eth0: -rtsched version <20010618.1050.24> -Decrementer Frequency: 3125000 -Warning: real time clock seems stuck! -Calibrating delay loop... 49.76 BogoMIPS -Memory: 14720k available (928k kernel code, 384k data, 44k init, 0k highmem) -Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes) -Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) -Page-cache hash table entries: 4096 (order: 2, 16384 bytes) -Inode-cache hash table entries: 1024 (order: 1, 8192 bytes) -POSIX conformance testing by UNIFIX -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Starting kswapd v1.8 -CPM UART driver version 0.03 -ttyS0 on SMC1 at 0x0280, BRG1 -block: queued sectors max/low 9701kB/3233kB, 64 slots per queue -RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize -eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP -IP: routing cache hash table of 512 buckets, 4Kbytes -TCP: Hash tables configured (established 1024 bind 1024) -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -Looking up port of RPC 100003/2 on 192.168.0.1 -Looking up port of RPC 100005/2 on 192.168.0.1 -VFS: Mounted root (nfs filesystem). -Freeing unused kernel memory: 44k init -INIT: version 2.78 booting - Welcome to DENX Embedded Linux Environment - Press 'I' to enter interactive startup. -Mounting proc filesystem: [ OK ] -Configuring kernel parameters: [ OK ] -Cannot access the Hardware Clock via any known method. -Use the --debug option to see the details of our search for an access method. -Setting clock : Wed Dec 31 19:00:11 EST 1969 [ OK ] -Activating swap partitions: [ OK ] -Setting hostname 192.168.0.30: [ OK ] -Finding module dependencies: -[ OK ] -Checking filesystems -Checking all file systems. -[ OK ] -Mounting local filesystems: [ OK ] -Enabling swap space: [ OK ] -INIT: Entering runlevel: 3 -Entering non-interactive startup -Starting system logger: [ OK ] -Starting kernel logger: [ OK ] -Starting xinetd: [ OK ] - -192 login: root -Last login: Wed Dec 31 19:00:41 on ttyS0 -bash-2.04# - -################################################## -# Image download and run over ethernet interface -# Linux-2.4.4 + Root filesystem mounted from RAM (pMulti) -############################## - -U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) - -CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present - *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** -Board: ### No HW ID - assuming ELPT860 -DRAM: 16 MB -FLASH: 512 kB -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET - -Type "run nfsboot" to mount root filesystem over NFS - -Hit any key to stop autoboot: 0 -LEOX_elpt860: run ramboot -ARP broadcast 1 -TFTP from server 192.168.0.1; our IP address is 192.168.0.30 -Filename '/home/leox/pMulti'. -Load address: 0x400000 -Loading: ################################################################# - ################################################################# - ################################################################# - ################################################################# - ################################################################# - ######################################################## -done -Bytes transferred = 1947816 (1db8a8 hex) -## Booting image at 00400000 ... - Image Name: linux-2.4.4-2002-03-21 Multiboot - Image Type: PowerPC Linux Multi-File Image (gzip compressed) - Data Size: 1947752 Bytes = 1902 kB = 1 MB - Load Address: 00000000 - Entry Point: 00000000 - Contents: - Image 0: 477230 Bytes = 466 kB = 0 MB - Image 1: 1470508 Bytes = 1436 kB = 1 MB - Verifying Checksum ... OK - Uncompressing Multi-File Image ... OK - Loading Ramdisk to 00e44000, end 00fab02c ... OK -Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002 -On node 0 totalpages: 4096 -zone(0): 4096 pages. -zone(1): 0 pages. -zone(2): 0 pages. -Kernel command line: root=/dev/ram rw -rtsched version <20010618.1050.24> -Decrementer Frequency: 3125000 -Warning: real time clock seems stuck! -Calibrating delay loop... 49.76 BogoMIPS -Memory: 13280k available (928k kernel code, 384k data, 44k init, 0k highmem) -Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes) -Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) -Page-cache hash table entries: 4096 (order: 2, 16384 bytes) -Inode-cache hash table entries: 1024 (order: 1, 8192 bytes) -POSIX conformance testing by UNIFIX -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Starting kswapd v1.8 -CPM UART driver version 0.03 -ttyS0 on SMC1 at 0x0280, BRG1 -block: queued sectors max/low 8741kB/2913kB, 64 slots per queue -RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize -eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df -RAMDISK: Compressed image found at block 0 -Freeing initrd memory: 1436k freed -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP -IP: routing cache hash table of 512 buckets, 4Kbytes -TCP: Hash tables configured (established 1024 bind 1024) -IP-Config: Incomplete network configuration information. -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -VFS: Mounted root (ext2 filesystem). -Freeing unused kernel memory: 44k iné -init started: BusyBox v0.60.2 (2002.07.01-12:06+0000) multi-call Configuring hostname -Configuring lo... -Configuring eth0... -Configuring Gateway... - -Please press Enter to activate this console. - -ELPT860 login: root -Password: -Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz) - - a8888b. - d888888b. - 8P"YP"Y88 - _ _ 8|o||o|88 - | | |_| 8' .88 - | | _ ____ _ _ _ _ 8`._.' Y8. - | | | | _ \| | | |\ \/ / d/ `8b. - | |___ | | | | | |_| |/ \ .dP . Y8b. - |_____||_|_| |_|\____|\_/\_/ d8:' " `::88b. - d8" `Y88b - :8P ' :888 - 8a. : _a88P - ._/"Yaa_ : .| 88P| - \ YP" `| 8P `. - / \._____.d| .' - `--..__)888888P`._.' -login[21]: root login on `ttyS0' - - - -BusyBox v0.60.3 (2002.07.20-10:39+0000) Built-in shell (ash) -Enter 'help' for a list of built-in commands. - -root@ELPT860:~ # diff --git a/board/LEOX/elpt860/config.mk b/board/LEOX/elpt860/config.mk deleted file mode 100644 index defc360..0000000 --- a/board/LEOX/elpt860/config.mk +++ /dev/null @@ -1,36 +0,0 @@ -####################################################################### -# -# Copyright (C) 2000, 2001, 2002, 2003 -# The LEOX team , http://www.leox.org -# -# LEOX.org is about the development of free hardware and software resources -# for system on chip. -# -# Description: U-Boot port on the LEOX's ELPT860 CPU board -# ~~~~~~~~~~~ -# -####################################################################### -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -####################################################################### - -# -# ELPT860 board -# - -TEXT_BASE = 0x02000000 -#TEXT_BASE = 0x00FB0000 diff --git a/board/LEOX/elpt860/elpt860.c b/board/LEOX/elpt860/elpt860.c deleted file mode 100644 index 775db73..0000000 --- a/board/LEOX/elpt860/elpt860.c +++ /dev/null @@ -1,348 +0,0 @@ -/* -**===================================================================== -** -** Copyright (C) 2000, 2001, 2002, 2003 -** The LEOX team , http://www.leox.org -** -** LEOX.org is about the development of free hardware and software resources -** for system on chip. -** -** Description: U-Boot port on the LEOX's ELPT860 CPU board -** ~~~~~~~~~~~ -** -**===================================================================== -** -** This program is free software; you can redistribute it and/or -** modify it under the terms of the GNU General Public License as -** published by the Free Software Foundation; either version 2 of -** the License, or (at your option) any later version. -** -** This program is distributed in the hope that it will be useful, -** but WITHOUT ANY WARRANTY; without even the implied warranty of -** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -** GNU General Public License for more details. -** -** You should have received a copy of the GNU General Public License -** along with this program; if not, write to the Free Software -** Foundation, Inc., 59 Temple Place, Suite 330, Boston, -** MA 02111-1307 USA -** -**===================================================================== -*/ - -/* -** Note 1: In this file, you have to provide the following functions: -** ------ -** int board_early_init_f(void) -** int checkboard(void) -** long int initdram(int board_type) -** called from 'board_init_f()' into 'common/board.c' -** -** void reset_phy(void) -** called from 'board_init_r()' into 'common/board.c' -*/ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint init_sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, - 0xFFFFFC04, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */ - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, - 0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */ - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34, - 0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */ -}; - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, - 0xFF0FFC00, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, - 0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00, - 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, - 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00, - 0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */ - _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00, - 0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04, - 0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, - 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_, - 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */ -}; - -/* ------------------------------------------------------------------------- */ - -#define CFG_PC4 0x0800 - -#define CFG_DS1 CFG_PC4 - -/* - * Very early board init code (fpga boot, etc.) - */ -int board_early_init_f (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - /* - * Light up the red led on ELPT860 pcb (DS1) (PCDAT) - */ - immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */ - immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */ - immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */ - - return (0); /* success */ -} - -/* - * Check Board Identity: - * - * Test ELPT860 ID string - * - * Return 1 if no second DRAM bank, otherwise returns 0 - */ - -int checkboard (void) -{ - char *s = getenv ("serial#"); - - if (!s || strncmp (s, "ELPT860", 7)) - printf ("### No HW ID - assuming ELPT860\n"); - - return (0); /* success */ -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size_b0 = 0; - - /* - * This sequence initializes SDRAM chips on ELPT860 board - */ - upmconfig (UPMA, (uint *) init_sdram_table, - sizeof (init_sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = 0x18002111; - - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */ - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; - - /* - * The following value is used as an address (i.e. opcode) for - * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If - * the port size is 32bit the SDRAM does NOT "see" the lower two - * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for - * MICRON SDRAMs: - * -> 0 00 010 0 010 - * | | | | +- Burst Length = 4 - * | | | +----- Burst Type = Sequential - * | | +------- CAS Latency = 2 - * | +----------- Operating Mode = Standard - * +-------------- Write Burst Mode = Programmed Burst Length - */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, - SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, - SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; - /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - - size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); - /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if (size_b0 < 0x02000000) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - { - unsigned long reg; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - udelay (10000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int -dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#define CFG_PA1 0x4000 -#define CFG_PA2 0x2000 - -#define CFG_LBKs (CFG_PA2 | CFG_PA1) - -void reset_phy (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - /* - * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect - * and no AUI loopback - */ - immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */ - immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */ - immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */ -} diff --git a/board/LEOX/elpt860/flash.c b/board/LEOX/elpt860/flash.c deleted file mode 100644 index c1b3b85..0000000 --- a/board/LEOX/elpt860/flash.c +++ /dev/null @@ -1,615 +0,0 @@ -/* -**===================================================================== -** -** Copyright (C) 2000, 2001, 2002, 2003 -** The LEOX team , http://www.leox.org -** -** LEOX.org is about the development of free hardware and software resources -** for system on chip. -** -** Description: U-Boot port on the LEOX's ELPT860 CPU board -** ~~~~~~~~~~~ -** -**===================================================================== -** -** This program is free software; you can redistribute it and/or -** modify it under the terms of the GNU General Public License as -** published by the Free Software Foundation; either version 2 of -** the License, or (at your option) any later version. -** -** This program is distributed in the hope that it will be useful, -** but WITHOUT ANY WARRANTY; without even the implied warranty of -** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -** GNU General Public License for more details. -** -** You should have received a copy of the GNU General Public License -** along with this program; if not, write to the Free Software -** Foundation, Inc., 59 Temple Place, Suite 330, Boston, -** MA 02111-1307 USA -** -**===================================================================== -*/ - -/* -** Note 1: In this file, you have to provide the following variable: -** ------ -** flash_info_t flash_info[CFG_MAX_FLASH_BANKS] -** 'flash_info_t' structure is defined into 'include/flash.h' -** and defined as extern into 'common/cmd_flash.c' -** -** Note 2: In this file, you have to provide the following functions: -** ------ -** unsigned long flash_init(void) -** called from 'board_init_r()' into 'common/board.c' -** -** void flash_print_info(flash_info_t *info) -** called from 'do_flinfo()' into 'common/cmd_flash.c' -** -** int flash_erase(flash_info_t *info, -** int s_first, -** int s_last) -** called from 'do_flerase()' & 'flash_sect_erase()' into 'common/cmd_flash.c' -** -** int write_buff (flash_info_t *info, -** uchar *src, -** ulong addr, -** ulong cnt) -** called from 'flash_write()' into 'common/cmd_flash.c' -*/ - -#include -#include - - -#ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Internal Functions - */ -static void flash_get_offsets (ulong base, flash_info_t *info); -static ulong flash_get_size (volatile unsigned char *addr, flash_info_t *info); - -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int write_byte (flash_info_t *info, ulong dest, uchar data); - -/*----------------------------------------------------------------------- - */ - -unsigned long -flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE, - &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void -flash_get_offsets (ulong base, - flash_info_t *info) -{ - int i; - -#define SECTOR_64KB 0x00010000 - - /* set up sector start adress table */ - for (i = 0; i < info->sector_count; i++) - { - info->start[i] = base + (i * SECTOR_64KB); - } -} - -/*----------------------------------------------------------------------- - */ -void -flash_print_info (flash_info_t *info) -{ - int i; - - if ( info->flash_id == FLASH_UNKNOWN ) - { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ( info->flash_id & FLASH_VENDMASK ) - { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_STM: printf ("STM (Thomson) "); break; - default: printf ("Unknown Vendor "); break; - } - - switch ( info->flash_id & FLASH_TYPEMASK ) - { - case FLASH_AM040: printf ("AM29F040 (4 Mbits)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) - { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong -flash_get_size (volatile unsigned char *addr, - flash_info_t *info) -{ - short i; - uchar value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x90; - - value = addr[0]; - - switch ( value ) - { - /* case AMD_MANUFACT: */ - case 0x01: - info->flash_id = FLASH_MAN_AMD; - break; - /* case FUJ_MANUFACT: */ - case 0x04: - info->flash_id = FLASH_MAN_FUJ; - break; - /* case STM_MANUFACT: */ - case 0x20: - info->flash_id = FLASH_MAN_STM; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch ( value ) - { - case STM_ID_F040B: - case AMD_ID_F040B: - info->flash_id += FLASH_AM040; /* 4 Mbits = 512k * 8 */ - info->sector_count = 8; - info->size = 0x00080000; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start adress table */ - for (i = 0; i < info->sector_count; i++) - { - info->start[i] = base + (i * 0x00010000); - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) - { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if ( info->flash_id != FLASH_UNKNOWN ) - { - addr = (volatile unsigned char *)info->start[0]; - - *addr = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int -flash_erase (flash_info_t *info, - int s_first, - int s_last) -{ - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ( (s_first < 0) || (s_first > s_last) ) - { - if ( info->flash_id == FLASH_UNKNOWN ) - { - printf ("- missing\n"); - } - else - { - printf ("- no sectors to erase\n"); - } - return ( 1 ); - } - - if ( (info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP) ) - { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return ( 1 ); - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) - { - if ( info->protect[sect] ) - { - prot++; - } - } - - if ( prot ) - { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } - else - { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) - { - if (info->protect[sect] == 0) /* not protected */ - { - addr = (volatile unsigned char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if ( flag ) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if ( l_sect < 0 ) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - while ( (addr[0] & 0x80) != 0x80 ) - { - if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT ) - { - printf ("Timeout\n"); - return ( 1 ); - } - /* show that we're waiting */ - if ( (now - last) > 1000 ) /* every second */ - { - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf (" done\n"); - - return ( 0 ); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int -write_buff (flash_info_t *info, - uchar *src, - ulong addr, - ulong cnt) -{ - ulong cp, wp, data; - uchar bdata; - int i, l, rc; - - if ( (info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 ) - { - /* Width of the data bus: 8 bits */ - - wp = addr; - - while ( cnt ) - { - bdata = *src++; - - if ( (rc = write_byte(info, wp, bdata)) != 0 ) - { - return (rc); - } - - ++wp; - --cnt; - } - - return ( 0 ); - } - else - { - /* Width of the data bus: 32 bits */ - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ( (l = addr - wp) != 0 ) - { - data = 0; - for (i=0, cp=wp; i0; ++i) - { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) - { - data = (data << 8) | (*(uchar *)cp); - } - - if ( (rc = write_word(info, wp, data)) != 0 ) - { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while ( cnt >= 4 ) - { - data = 0; - for (i=0; i<4; ++i) - { - data = (data << 8) | *src++; - } - if ( (rc = write_word(info, wp, data)) != 0 ) - { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if ( cnt == 0 ) - { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) - { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) - { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); - } -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_word (flash_info_t *info, - ulong dest, - ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ( (*((vu_long *)dest) & data) != data ) - { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if ( flag ) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) ) - { - if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) - { - return (1); - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_byte (flash_info_t *info, - ulong dest, - uchar data) -{ - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ( (*((volatile unsigned char *)dest) & data) != data ) - { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((volatile unsigned char *)dest) = data; - - /* re-enable interrupts if necessary */ - if ( flag ) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) ) - { - if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) - { - return (1); - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds deleted file mode 100644 index b09fc33..0000000 --- a/board/LEOX/elpt860/u-boot.lds +++ /dev/null @@ -1,154 +0,0 @@ -/* -**===================================================================== -** -** Copyright (C) 2000, 2001, 2002, 2003 -** The LEOX team , http://www.leox.org -** -** LEOX.org is about the development of free hardware and software resources -** for system on chip. -** -** Description: U-Boot port on the LEOX's ELPT860 CPU board -** ~~~~~~~~~~~ -** -**===================================================================== -** -** This program is free software; you can redistribute it and/or -** modify it under the terms of the GNU General Public License as -** published by the Free Software Foundation; either version 2 of -** the License, or (at your option) any later version. -** -** This program is distributed in the hope that it will be useful, -** but WITHOUT ANY WARRANTY; without even the implied warranty of -** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -** GNU General Public License for more details. -** -** You should have received a copy of the GNU General Public License -** along with this program; if not, write to the Free Software -** Foundation, Inc., 59 Temple Place, Suite 330, Boston, -** MA 02111-1307 USA -** -**===================================================================== -*/ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_generic/string.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/extable.o (.text) - lib_ppc/time.o (.text) - lib_ppc/ticks.o (.text) - - . = env_offset; - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug deleted file mode 100644 index 6f5af91..0000000 --- a/board/LEOX/elpt860/u-boot.lds.debug +++ /dev/null @@ -1,141 +0,0 @@ -/* -**===================================================================== -** -** Copyright (C) 2000, 2001, 2002, 2003 -** The LEOX team , http://www.leox.org -** -** LEOX.org is about the development of free hardware and software resources -** for system on chip. -** -** Description: U-Boot port on the LEOX's ELPT860 CPU board -** ~~~~~~~~~~~ -** -**===================================================================== -** -** This program is free software; you can redistribute it and/or -** modify it under the terms of the GNU General Public License as -** published by the Free Software Foundation; either version 2 of -** the License, or (at your option) any later version. -** -** This program is distributed in the hope that it will be useful, -** but WITHOUT ANY WARRANTY; without even the implied warranty of -** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -** GNU General Public License for more details. -** -** You should have received a copy of the GNU General Public License -** along with this program; if not, write to the Free Software -** Foundation, Inc., 59 Temple Place, Suite 330, Boston, -** MA 02111-1307 USA -** -**===================================================================== -*/ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c deleted file mode 100644 index 0934e1b..0000000 --- a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2002 - * Hyperion Entertainment, ThomasF@hyperion-entertainment.com - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "articiaS.h" -#include "memio.h" -#include "via686.h" - -__asm(" .globl send_kb \n - send_kb: \n - lis r9, 0xfe00 \n - \n - li r4, 0x10 # retries \n - mtctr r4 \n - \n - idle: \n - lbz r4, 0x64(r9) \n - andi. r4, r4, 0x02 \n - bne idle \n - \n - ready: \n - stb r3, 0x60(r9) \n - \n - check: \n - lbz r4, 0x64(r9) \n - andi. r4, r4, 0x01 \n - beq check \n - \n - lbz r4, 0x60(r9) \n - cmpwi r4, 0xfa \n - beq done \n - \n - bdnz idle \n - \n - li r3, 0 \n - blr \n - \n - done: \n - li r3, 1 \n - blr \n - \n - .globl test_kb \n - test_kb: \n - mflr r10 \n - li r3, 0xed \n - bl send_kb \n - li r3, 0x01 \n - bl send_kb \n - mtlr r10 \n - blr \n -"); - - -int checkboard (void) -{ - printf ("Board: AmigaOneG3SE\n"); - return 0; -} - -long initdram (int board_type) -{ - return articiaS_ram_init (); -} - - -void after_reloc (ulong dest_addr, gd_t *gd) -{ -/* HJF: DECLARE_GLOBAL_DATA_PTR; */ - - board_init_r (gd, dest_addr); -} - - -int misc_init_r (void) -{ - extern pci_dev_t video_dev; - extern void drv_video_init (void); - - if (video_dev != ~0) - drv_video_init (); - - return (0); -} - - -void pci_init_board (void) -{ -#ifndef CONFIG_RAMBOOT - articiaS_pci_init (); -#endif -} diff --git a/board/MAI/AmigaOneG3SE/Makefile b/board/MAI/AmigaOneG3SE/Makefile deleted file mode 100644 index b1247fe..0000000 --- a/board/MAI/AmigaOneG3SE/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -COBJS = $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \ - via686.o i8259.o ../bios_emulator/x86interface.o \ - ../bios_emulator/bios.o ../bios_emulator/glue.o \ - interrupts.o ps2kbd.o video.o usb_uhci.o enet.o \ - ../menu/cmd_menu.o cmd_boota.o nvram.o - -AOBJS = board_asm_init.o memio.o - -OBJS = $(COBJS) $(AOBJS) - -EMUDIR = ../bios_emulator/scitech/src/x86emu/ -EMUOBJ = $(EMUDIR)decode.o $(EMUDIR)ops2.o $(EMUDIR)fpu.o $(EMUDIR)prim_ops.o \ - $(EMUDIR)ops.o $(EMUDIR)sys.o -EMUSRC = $(EMUOBJ:.o=.c) - -$(LIB): .depend $(OBJS) $(EMUSRC) - make libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE) - -rm $(LIB) - $(AR) crv $@ $(OBJS) $(EMUOBJ) - - -######################################################################### - -.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/MAI/AmigaOneG3SE/articiaS.c b/board/MAI/AmigaOneG3SE/articiaS.c deleted file mode 100644 index a4dad64..0000000 --- a/board/MAI/AmigaOneG3SE/articiaS.c +++ /dev/null @@ -1,705 +0,0 @@ -/* - * (C) Copyright 2002 - * Hyperion Entertainment, ThomasF@hyperion-entertainment.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "memio.h" -#include "articiaS.h" -#include "smbus.h" -#include "via686.h" - -#undef DEBUG - -struct dimm_bank { - uint8 used; /* Bank is populated */ - uint32 rows; /* Number of row addresses */ - uint32 columns; /* Number of column addresses */ - uint8 registered; /* SIMM is registered */ - uint8 ecc; /* SIMM has ecc */ - uint8 burst_len; /* Supported burst lengths */ - uint32 cas_lat; /* Supported CAS latencies */ - uint32 cas_used; /* CAS to use (not set by user) */ - uint32 trcd; /* RAS to CAS latency */ - uint32 trp; /* Precharge latency */ - uint32 tclk_hi; /* SDRAM cycle time (highest CAS latency) */ - uint32 tclk_2hi; /* SDRAM second highest CAS latency */ - uint32 size; /* Size of bank in bytes */ - uint8 auto_refresh; /* Module supports auto refresh */ - uint32 refresh_time; /* Refresh time (in ns) */ -}; - - -/* -** Based in part on the evb64260 code -*/ - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NS10to10PS (unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - - -long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks) -{ - DECLARE_GLOBAL_DATA_PTR; - int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR; - uint32 busclock = gd->bus_clk; - uint32 memclock = busclock; - uint32 tmemclock = 1000000000 / (memclock / 100); - uint32 datawidth; - - if (sm_get_data (rom, dimm_address) == 0) { - /* Nothing in slot, make both banks empty */ - debug ("Slot %d: vacant\n", dimmNum); - banks[0].used = 0; - banks[1].used = 0; - return 0; - } - - if (rom[2] != 0x04) { - debug ("Slot %d: No SDRAM\n", dimmNum); - banks[0].used = 0; - banks[1].used = 0; - return 0; - } - - /* Determine number of banks/rows */ - if (rom[5] == 1) { - banks[0].used = 1; - banks[1].used = 0; - } else { - banks[0].used = 1; - banks[1].used = 1; - } - - /* Determine number of row addresses */ - if (rom[3] & 0xf0) { - /* Different banks sizes */ - banks[0].rows = rom[3] & 0x0f; - banks[1].rows = (rom[3] & 0xf0) >> 4; - } else { - /* Equal sized banks */ - banks[0].rows = rom[3] & 0x0f; - banks[1].rows = banks[0].rows; - } - - /* Determine number of column addresses */ - if (rom[4] & 0xf0) { - /* Different bank sizes */ - banks[0].columns = rom[4] & 0x0f; - banks[1].columns = (rom[4] & 0xf0) >> 4; - } else { - banks[0].columns = rom[4] & 0x0f; - banks[1].columns = banks[0].columns; - } - - /* Check Jedec revision, and modify row/column accordingly */ - if (rom[62] > 0x10) { - if (banks[0].rows <= 3) - banks[0].rows += 15; - if (banks[1].rows <= 3) - banks[1].rows += 15; - if (banks[0].columns <= 3) - banks[0].columns += 15; - if (banks[0].columns <= 3) - banks[0].columns += 15; - } - - /* Check registered/unregisterd */ - if (rom[21] & 0x12) { - banks[0].registered = 1; - banks[1].registered = 1; - } else { - banks[0].registered = 0; - banks[1].registered = 0; - } - -#ifdef CONFIG_ECC - /* Check parity/ECC */ - banks[0].ecc = (rom[11] == 0x02); - banks[1].ecc = (rom[11] == 0x02); -#endif - - /* Find burst lengths supported */ - banks[0].burst_len = rom[16] & 0x8f; - banks[1].burst_len = rom[16] & 0x8f; - - /* Find possible cas latencies */ - banks[0].cas_lat = rom[18] & 0x7F; - banks[1].cas_lat = rom[18] & 0x7F; - - /* RAS/CAS latency */ - banks[0].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock; - banks[1].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock; - - /* Precharge latency */ - banks[0].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock; - banks[1].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock; - - /* highest CAS latency */ - banks[0].tclk_hi = NS10to10PS (rom[9]); - banks[1].tclk_hi = NS10to10PS (rom[9]); - - /* second highest CAS latency */ - banks[0].tclk_2hi = NS10to10PS (rom[23]); - banks[1].tclk_2hi = NS10to10PS (rom[23]); - - /* bank sizes */ - datawidth = rom[13] & 0x7f; - banks[0].size = - (1L << (banks[0].rows + banks[0].columns)) * - /* FIXME datawidth */ 8 * rom[17]; - if (rom[13] & 0x80) - banks[1].size = 2 * banks[0].size; - else - banks[1].size = (1L << (banks[1].rows + banks[1].columns)) * - /* FIXME datawidth */ 8 * rom[17]; - - /* Refresh */ - if (rom[12] & 0x80) { - banks[0].auto_refresh = 1; - banks[1].auto_refresh = 1; - } else { - banks[0].auto_refresh = 0; - banks[1].auto_refresh = 0; - } - - switch (rom[12] & 0x7f) { - case 0: - banks[0].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock; - banks[1].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock; - break; - case 1: - banks[0].refresh_time = (390600 + (tmemclock - 1)) / tmemclock; - banks[1].refresh_time = (390600 + (tmemclock - 1)) / tmemclock; - break; - case 2: - banks[0].refresh_time = (781200 + (tmemclock - 1)) / tmemclock; - banks[1].refresh_time = (781200 + (tmemclock - 1)) / tmemclock; - break; - case 3: - banks[0].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock; - banks[1].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock; - break; - case 4: - banks[0].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock; - banks[1].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock; - break; - case 5: - banks[0].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock; - banks[1].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock; - break; - default: - banks[0].refresh_time = 0x100; /* Default of Articia S */ - banks[1].refresh_time = 0x100; - break; - } - -#ifdef DEBUG - printf ("\nInformation for SIMM bank %ld:\n", dimmNum); - printf ("Number of banks: %ld\n", banks[0].used + banks[1].used); - printf ("Number of row addresses: %ld\n", banks[0].rows); - printf ("Number of coumns addresses: %ld\n", banks[0].columns); - printf ("SIMM is %sregistered\n", - banks[0].registered == 0 ? "not " : ""); -#ifdef CONFIG_ECC - printf ("SIMM %s ECC\n", - banks[0].ecc == 1 ? "supports" : "doesn't support"); -#endif - printf ("Supported burst lenghts: %s %s %s %s %s\n", - banks[0].burst_len & 0x08 ? "8" : " ", - banks[0].burst_len & 0x04 ? "4" : " ", - banks[0].burst_len & 0x02 ? "2" : " ", - banks[0].burst_len & 0x01 ? "1" : " ", - banks[0].burst_len & 0x80 ? "PAGE" : " "); - printf ("Supported CAS latencies: %s %s %s\n", - banks[0].cas_lat & 0x04 ? "CAS 3" : " ", - banks[0].cas_lat & 0x02 ? "CAS 2" : " ", - banks[0].cas_lat & 0x01 ? "CAS 1" : " "); - printf ("RAS to CAS latency: %ld\n", banks[0].trcd); - printf ("Precharge latency: %ld\n", banks[0].trp); - printf ("SDRAM highest CAS latency: %ld\n", banks[0].tclk_hi); - printf ("SDRAM 2nd highest CAS latency: %ld\n", banks[0].tclk_2hi); - printf ("SDRAM data width: %ld\n", datawidth); - printf ("Auto Refresh %ssupported\n", - banks[0].auto_refresh ? "" : "not "); - printf ("Refresh time: %ld clocks\n", banks[0].refresh_time); - if (banks[0].used) - printf ("Bank 0 size: %ld MB\n", banks[0].size / 1024 / 1024); - if (banks[1].used) - printf ("Bank 1 size: %ld MB\n", banks[1].size / 1024 / 1024); - - printf ("\n"); -#endif - - sm_term (); - return 1; -} - -void select_cas (struct dimm_bank *banks, uint8 fast) -{ - if (!banks[0].used) { - banks[0].cas_used = 0; - banks[0].cas_used = 0; - return; - } - - if (fast) { - /* Search for fast CAS */ - uint32 i; - uint32 c = 0x01; - - for (i = 1; i < 5; i++) { - if (banks[0].cas_lat & c) { - banks[0].cas_used = i; - banks[1].cas_used = i; - debug ("Using CAS %d (fast)\n", i); - return; - } - c <<= 1; - } - - /* Default to CAS 3 */ - banks[0].cas_used = 3; - banks[1].cas_used = 3; - debug ("Using CAS 3 (fast)\n"); - - return; - } else { - /* Search for slow cas */ - uint32 i; - uint32 c = 0x08; - - for (i = 4; i > 1; i--) { - if (banks[0].cas_lat & c) { - banks[0].cas_used = i; - banks[1].cas_used = i; - debug ("Using CAS %d (slow)\n", i); - return; - } - c >>= 1; - } - - /* Default to CAS 3 */ - banks[0].cas_used = 3; - banks[1].cas_used = 3; - debug ("Using CAS 3 (slow)\n"); - - return; - } - - banks[0].cas_used = 3; - banks[1].cas_used = 3; - debug ("Using CAS 3\n"); - - return; -} - -uint32 get_reg_setting (uint32 banks, uint32 rows, uint32 columns, uint32 size) -{ - uint32 i; - - struct RowColumnSize { - uint32 banks; - uint32 rows; - uint32 columns; - uint32 size; - uint32 register_value; - }; - - struct RowColumnSize rcs_map[] = { - /* Sbk Radr Cadr MB Value */ - {1, 11, 8, 8, 0x00840f00}, - {1, 11, 9, 16, 0x00925f00}, - {1, 11, 10, 32, 0x00a64f00}, - {2, 12, 8, 32, 0x00c55f00}, - {2, 12, 9, 64, 0x00d66f00}, - {2, 12, 10, 128, 0x00e77f00}, - {2, 12, 11, 256, 0x00ff8f00}, - {2, 13, 11, 512, 0x00ff9f00}, - {0, 0, 0, 0, 0x00000000} - }; - - - i = 0; - - while (rcs_map[i].banks != 0) { - if (rows == rcs_map[i].rows - && columns == rcs_map[i].columns - && (size / 1024 / 1024) == rcs_map[i].size) - return rcs_map[i].register_value; - - i++; - } - - return 0; -} - -uint32 burst_to_len (uint32 support) -{ - if (support & 0x80) - return 0x7; - else if (support & 0x8) - return 0x3; - else if (support & 0x4) - return 0x2; - else if (support & 0x2) - return 0x1; - else if (support & 0x1) - return 0x0; - - return 0; -} - -long articiaS_ram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - register uint32 i; - register uint32 value1; - register uint32 value2; - uint8 rom[128]; - uint32 burst_len; - uint32 burst_support; - uint32 total_ram = 0; - - struct dimm_bank banks[4]; /* FIXME: Move to initram */ - uint32 busclock = gd->bus_clk; - uint32 memclock = busclock; - uint32 reg32; - uint32 refresh_clocks; - uint8 auto_refresh; - - memset (banks, 0, sizeof (struct dimm_bank) * 4); - - detect_sdram (rom, 0, &banks[0]); - detect_sdram (rom, 1, &banks[2]); - - for (i = 0; i < 4; i++) { - total_ram = total_ram + (banks[i].used * banks[i].size); - } - - pci_write_cfg_long (0, 0, GLOBALINFO0, 0x117430c0); - pci_write_cfg_long (0, 0, HBUSACR0, 0x1f0100b0); - pci_write_cfg_long (0, 0, SRAM_CR, 0x00f12000); /* Note: Might also try 0x00f10000 (original: 0x00f12000) */ - pci_write_cfg_byte (0, 0, DRAM_RAS_CTL0, 0x3f); - pci_write_cfg_byte (0, 0, DRAM_RAS_CTL1, 0x00); /* was: 0x04); */ - pci_write_cfg_word (0, 0, DRAM_ECC0, 0x2020); /* was: 0x2400); No ECC yet */ - - /* FIXME: Move this stuff to seperate function, like setup_dimm_bank */ - if (banks[0].used) { - value1 = get_reg_setting (banks[0].used + banks[1].used, - banks[0].rows, banks[0].columns, - banks[0].size); - } else { - value1 = 0; - } - - if (banks[1].used) { - value2 = get_reg_setting (banks[0].used + banks[1].used, - banks[1].rows, banks[1].columns, - banks[1].size); - } else { - value2 = 0; - } - - pci_write_cfg_long (0, 0, DIMM0_B0_SCR0, value1); - pci_write_cfg_long (0, 0, DIMM0_B1_SCR0, value2); - - debug ("DIMM0_B0_SCR0 = 0x%08x\n", value1); - debug ("DIMM0_B1_SCR0 = 0x%08x\n", value2); - - if (banks[2].used) { - value1 = get_reg_setting (banks[2].used + banks[3].used, - banks[2].rows, banks[2].columns, - banks[2].size); - } else { - value1 = 0; - } - - if (banks[3].used) { - value2 = get_reg_setting (banks[2].used + banks[3].used, - banks[3].rows, banks[3].columns, - banks[3].size); - } else { - value2 = 0; - } - - pci_write_cfg_long (0, 0, DIMM1_B2_SCR0, value1); - pci_write_cfg_long (0, 0, DIMM1_B3_SCR0, value2); - - debug ("DIMM0_B2_SCR0 = 0x%08x\n", value1); - debug ("DIMM0_B3_SCR0 = 0x%08x\n", value2); - - pci_write_cfg_long (0, 0, DIMM2_B4_SCR0, 0); - pci_write_cfg_long (0, 0, DIMM2_B5_SCR0, 0); - pci_write_cfg_long (0, 0, DIMM3_B6_SCR0, 0); - pci_write_cfg_long (0, 0, DIMM3_B7_SCR0, 0); - - /* Determine timing */ - select_cas (&banks[0], 0); - select_cas (&banks[2], 0); - - /* FIXME: What about write recovery */ - /* Auto refresh Precharge */ -#if 0 - reg32 = (0x3 << 13) | (0x7 << 10) | ((banks[0].trp - 2) << 8) | - /* Write recovery CAS Latency */ - (0x1 << 6) | (banks[0].cas_used << 4) | - /* RAS/CAS latency */ - ((banks[0].trcd - 1) << 0); - - reg32 |= ((0x3 << 13) | (0x7 << 10) | ((banks[2].trp - 2) << 8) | - (0x1 << 6) | (banks[2].cas_used << 4) | - ((banks[2].trcd - 1) << 0)) << 16; -#else - if (100000000 == gd->bus_clk) - reg32 = 0x71737173; - else - reg32 = 0x69736973; -#endif - pci_write_cfg_long (0, 0, DIMM0_TCR0, reg32); - debug ("DIMM0_TCR0 = 0x%08x\n", reg32); - - /* Write default in DIMM2/3 (not used on A1) */ - pci_write_cfg_long (0, 0, DIMM2_TCR0, 0x7d737d73); - - - /* Determine buffered/unbuffered mode for each SIMM. Uses first bank as reference (second, if present, uses the same) */ - reg32 = pci_read_cfg_long (0, 0, DRAM_GCR0); - reg32 &= 0xFF00FFFF; - -#if 0 - if (banks[0].used && banks[0].registered) - reg32 |= 0x1 << 16; - - if (banks[2].used && banks[2].registered) - reg32 |= 0x1 << 18; -#else - if (banks[0].registered || banks[2].registered) - reg32 |= 0x55 << 16; -#endif - pci_write_cfg_long (0, 0, DRAM_GCR0, reg32); - debug ("DRAM_GCR0 = 0x%08x\n", reg32); - - /* Determine refresh */ - refresh_clocks = 0xffffffff; - auto_refresh = 1; - - for (i = 0; i < 4; i++) { - if (banks[i].used) { - if (banks[i].auto_refresh == 0) - auto_refresh = 0; - if (banks[i].refresh_time < refresh_clocks) - refresh_clocks = banks[i].refresh_time; - } - } - - -#if 1 - /* It seems this is suggested by the ArticiaS data book */ - if (100000000 == gd->bus_clk) - refresh_clocks = 1561; - else - refresh_clocks = 2083; -#endif - - - debug ("Refresh set to %ld clocks, auto refresh %s\n", - refresh_clocks, auto_refresh ? "on" : "off"); - - pci_write_cfg_long (0, 0, DRAM_REFRESH0, - (1 << 16) | (1 << 15) | (auto_refresh << 12) | - (refresh_clocks)); - debug ("DRAM_REFRESH0 = 0x%08x\n", - (1 << 16) | (1 << 15) | (auto_refresh << 12) | - (refresh_clocks)); - -/* pci_write_cfg_long(0, 0, DRAM_REFRESH0, 0x00019400); */ - - /* Set mode registers */ - /* FIXME: For now, set same burst len for all modules. Dunno if that's necessary */ - /* Find a common burst len */ - burst_support = 0xff; - - if (banks[0].used) - burst_support = banks[0].burst_len; - if (banks[1].used) - burst_support = banks[1].burst_len; - if (banks[2].used) - burst_support = banks[2].burst_len; - if (banks[3].used) - burst_support = banks[3].burst_len; - - /* - ** Mode register: - ** Bits Use - ** 0-2 Burst len - ** 3 Burst type (0 = sequential, 1 = interleave) - ** 4-6 CAS latency - ** 7-8 Operation mode (0 = default, all others invalid) - ** 9 Write burst - ** 10-11 Reserved - ** - ** Mode register burst table: - ** A2 A1 A0 lenght - ** 0 0 0 1 - ** 0 0 1 2 - ** 0 1 0 4 - ** 0 1 1 8 - ** 1 0 0 invalid - ** 1 0 1 invalid - ** 1 1 0 invalid - ** 1 1 1 page (only valid for non-interleaved) - */ - - burst_len = burst_to_len (burst_support); - burst_len = 2; /* FIXME */ - - if (banks[0].used) { - pci_write_cfg_word (0, 0, DRAM_PCR0, - 0x8000 | burst_len | (banks[0].cas_used << 4)); - debug ("Mode bank 0: 0x%08x\n", - 0x8000 | burst_len | (banks[0].cas_used << 4)); - } else { - /* Seems to be needed to disable the bank */ - pci_write_cfg_word (0, 0, DRAM_PCR0, 0x0000 | 0x032); - } - - if (banks[1].used) { - pci_write_cfg_word (0, 0, DRAM_PCR0, - 0x9000 | burst_len | (banks[1].cas_used << 4)); - debug ("Mode bank 1: 0x%08x\n", - 0x8000 | burst_len | (banks[1].cas_used << 4)); - } else { - /* Seems to be needed to disable the bank */ - pci_write_cfg_word (0, 0, DRAM_PCR0, 0x1000 | 0x032); - } - - - if (banks[2].used) { - pci_write_cfg_word (0, 0, DRAM_PCR0, - 0xa000 | burst_len | (banks[2].cas_used << 4)); - debug ("Mode bank 2: 0x%08x\n", - 0x8000 | burst_len | (banks[2].cas_used << 4)); - } else { - /* Seems to be needed to disable the bank */ - pci_write_cfg_word (0, 0, DRAM_PCR0, 0x2000 | 0x032); - } - - - if (banks[3].used) { - pci_write_cfg_word (0, 0, DRAM_PCR0, - 0xb000 | burst_len | (banks[3].cas_used << 4)); - debug ("Mode bank 3: 0x%08x\n", - 0x8000 | burst_len | (banks[3].cas_used << 4)); - } else { - /* Seems to be needed to disable the bank */ - pci_write_cfg_word (0, 0, DRAM_PCR0, 0x3000 | 0x032); - } - - - pci_write_cfg_word (0, 0, 0xba, 0x00); - - return total_ram; -} - -extern int drv_isa_kbd_init (void); - -int last_stage_init (void) -{ - drv_isa_kbd_init (); - return 0; -} - -int overwrite_console (void) -{ - return (0); -} - -#define in_8 read_byte -#define out_8 write_byte - -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - - asm volatile ("mfmsr %0":"=r" (msr):); - - return msr; -} - -static __inline__ void set_msr (unsigned long msr) -{ - asm volatile ("mtmsr %0"::"r" (msr)); -} - -int board_early_init_f (void) -{ - unsigned char c_value = 0; - unsigned long msr; - - /* Basic init of PS/2 keyboard (needed for some reason)... */ - /* Ripped from John's code */ - while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0); - out_8 ((unsigned char *) 0xfe000064, 0xaa); - while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0); - c_value = in_8 ((unsigned char *) 0xfe000060); - while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0); - out_8 ((unsigned char *) 0xfe000064, 0xab); - while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0); - c_value = in_8 ((unsigned char *) 0xfe000060); - while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0); - out_8 ((unsigned char *) 0xfe000064, 0xae); -/* while ((in_8((unsigned char *)0xfe000064) & 0x01) == 0); */ -/* c_value = in_8((unsigned char *)0xfe000060); */ - - /* Enable FPU */ - msr = get_msr (); - set_msr (msr | MSR_FP); - - via_calibrate_bus_freq (); - - return 0; -} diff --git a/board/MAI/AmigaOneG3SE/articiaS.h b/board/MAI/AmigaOneG3SE/articiaS.h deleted file mode 100644 index ce20d03..0000000 --- a/board/MAI/AmigaOneG3SE/articiaS.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef ARTICIAS_H -#define ARTICIAS_H - -#include "short_types.h" -#include - -#define REG_GROUP 0xF0 - -/* ArticiaS registers */ -#define GLOBALINFO0 0x50 -#define GLOBALINFO1 0x51 -#define GLOBALINFO2 0x52 -#define GLOBALINFO3 0x53 -#define GLOBALCTL0 0x54 -#define GLOBALCTL1 0x55 -#define NVRAMCTL 0x56 -#define PCI1ACR0 0x58 -#define PCI1ACR1 0x59 -#define PCI1ACR2 0x5a -#define PCI1ACR3 0x5b -#define HBUSACR0 0x5c -#define HBUSACR1 0x5d -#define HBUSACR2 0x5e -#define HBUSACR3 0x5f -#define HOSTINT0 0x68 -#define HOSTINT1 0x69 -#define HOSTINT2 0x6a -#define HOSTINT3 0x6b -#define HOSTRBCR 0x70 -#define XDBCR 0x74 - -#define LBSBCR2 0xd2 - - -/* Memory controller */ - -#define DIMM0_B0_SCR0 0x90 -#define DIMM0_B1_SCR0 0x94 -#define DIMM1_B2_SCR0 0x98 -#define DIMM1_B3_SCR0 0x9c -#define DIMM2_B4_SCR0 0xa0 -#define DIMM2_B5_SCR0 0xa4 -#define DIMM3_B6_SCR0 0xa8 -#define DIMM3_B7_SCR0 0xac - -#define DIMM0_TCR0 0xb0 -#define DIMM1_TCR0 0xb2 -#define DIMM2_TCR0 0xb4 -#define DIMM3_TCR0 0xb6 - -#define DRAM_REFRESH0 0xb8 -#define DRAM_GCR0 0xc0 -#define DRAM_PCR0 0xc6 -#define DRAM_ECC0 0xc4 -#define SRAM_CR 0xc8 -#define DRAM_RAS_CTL0 0xcc -#define DRAM_RAS_CTL1 0xcd - -/* Bits for REG_GROUP */ -#define REG_GROUP_MULTI (1<<1) -#define REG_GROUP_SPECIAL (1<<3) -#define REG_GROUP_DIAG (0x1<<4) -#define REG_GROUP_POWER (0x2<<4) - - -#define GLOBALINFO0_BO (1<<7) - - -#define GLOBALINFO2_B1ARBITER (1<<6) - - -#define HBUSACR0_CPUAPC (1<<0) -#define HBUSACR0_NUMREQ_2 (0<<1) -#define HBUSACR0_NUMREQ_3 (1<<1) -#define HBUSACR0_NUMREQ_4 (2<<1) -#define HBUSACR0_NUMREQ_MASK (7<<1) -#define HBUSACR0_RAW (1<<6) -#define HBUSACR0_WAIT (1<<7) -#define HBUSACR0_RESERVED (0x30) - - -#define HBUSACR2_BURST (1<<0) -#define HBUSACR2_LAT (1<<1) - - -#define HBUSACR3_LMWC_SM (1<<0) -#define HBUSACR3_LMWC_PCI1 (1<<1) -#define HBUSACR3_LMWC_PCI0 (1<<2) -#define HBUSACR3_PMWC_PCI1 (1<<3) -#define HBUSACR3_PMWC_PCI0 (1<<4) -#define HBUSACR3_FKH (1<<5) -#define HBUSACR3_92H_EN (1<<6) -#define HBUSACR3_60H_64H_EN (1<<7) - - -#define HOSTRBCR_PREFETCH (1<<4) - - -#define XDBCR_HWTOXD (1<<0) -#define XDBCR_KBTOXD (1<<1) -#define XDBCR_RTCTOXD (1<<2) -#define XDBCR_SCALE_1_1 (0x0<<3) -#define XDBCR_SCALE_2_2 (0x1<<3) -#define XDBCR_SCALE_3_2 (0x2<<3) -#define XDBCR_SCALE_4_4 (0x3<<3) -#define XDBCR_SCALE_5_8 (0x4<<3) -#define XDBCR_SCALE_6_8 (0x5<<3) -#define XDBCR_SCALE_8_8 (0x6<<3) -#define XDBCR_SCALE_0_16 (0x7<<3) -#define XDBCR_XDPROM (1<<7) - - -#define LBSBCR2_1_RWAC (1<<2) - - -/* PCI controller */ -#define ARTICIAS_PCI_CFGADDR 0xfec00cf8 -#define ARTICIAS_PCI_CFGDATA 0xfee00cfc - -#define ARTICIAS_PCI_BUS 0x80000000 -#define ARTICIAS_PCI_MAXSIZE 0x7cffffff -#define ARTICIAS_PCI_PHYS 0x80000000 - -#define ARTICIAS_SYS_BUS 0x00000000 -#define ARTICIAS_SYS_MAXSIZE 0x7fffffff -#define ARTICIAS_SYS_PHYS 0x00000000 - -#define ARTICIAS_PCIIO_BUS 0x00800000 -#define ARTICIAS_PCIIO_MAXSIZE 0x003fffff -#define ARTICIAS_PCIIO_PHYS 0xfe800000 - -#define ARTICIAS_ISAIO_BUS 0x00002000 -#define ARTICIAS_ISAIO_MAXSIZE 0x0000d000 -#define ARTICIAS_ISAIO_PHYS 0xfe002000 - - -/* Prototypes */ -long articiaS_ram_init(void); -void articiaS_pci_init(void); - - -#endif diff --git a/board/MAI/AmigaOneG3SE/articiaS_pci.c b/board/MAI/AmigaOneG3SE/articiaS_pci.c deleted file mode 100644 index d2e9f29..0000000 --- a/board/MAI/AmigaOneG3SE/articiaS_pci.c +++ /dev/null @@ -1,576 +0,0 @@ -/* - * (C) Copyright 2002 - * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "memio.h" -#include "articiaS.h" - -#undef ARTICIA_PCI_DEBUG - -#ifdef ARTICIA_PCI_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -struct pci_controller articiaS_hose; - -long irq_alloc(long wanted); - -static pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index); -static int articiaS_init_vga(void); -static void pci_cfgfunc_dummy(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table); -unsigned char pci_irq_alloc(void); - -extern void via_cfgfunc_via686(struct pci_controller * host, pci_dev_t dev, struct pci_config_table *table); -extern void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table); -extern void via_init_irq_routing(uint8 []); -extern void via_init_afterscan(void); - -#define cfgfunc_via686 1 -#define cfgfunc_dummy 2 -#define cfgfunc_ide_init 3 - -static struct pci_config_table config_table[] = -{ - { - 0x1106, PCI_ANY_ID, PCI_CLASS_BRIDGE_ISA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - (void *)cfgfunc_via686, {0, 0, 0} - }, - { - 0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,4, - (void *)cfgfunc_dummy, {0,0,0} - }, - { - 0x1106, 0x3068, PCI_ANY_ID, 0, 7, PCI_ANY_ID, - (void *)cfgfunc_dummy, {0,0,0} - }, - { - 0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,1, - (void *)cfgfunc_ide_init, {0,0,0} - }, - { - 0, - } -}; - - -void pci_cfgfunc_dummy(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table) -{ - - -} - -unsigned long irq_penalties[16] = -{ - 1000, /* 0:timer */ - 1000, /* 1:keyboard */ - 1000, /* 2:cascade */ - 50, /* 3:serial (COM2) */ - 50, /* 4:serial (COM1) */ - 4, /* 5:USB2 */ - 100, /* 6:floppy */ - 3, /* 7:parallel */ - 50, /* 8:AC97/MC97 */ - 0, /* 9: */ - 3, /* 10:: */ - 0, /* 11: */ - 3, /* 12: USB1 */ - 0, /* 13: */ - 100, /* 14: ide0 */ - 100, /* 15: ide1 */ -}; - - -/* - * The following defines a hard-coded interrupt mapping for the - * know devices on the board. - * If a device isn't found here, assumed to be a device that's - * plugged into a PCI or AGP slot - * NOTE: This table is machine dependant. - */ - -struct pci_irq_fixup_table -{ - uint8 bus; /* Bus number */ - uint8 device; /* Device number */ - uint8 func; /* Function number */ - uint8 interrupt; /* Interrupt to use (0xff to disable) */ -}; - -struct pci_irq_fixup_table fixuptab [] = -{ - { 0, 0, 0, 0xff}, /* Articia S host bridge */ - { 0, 1, 0, 0xff}, /* Articia S AGP bridge */ -/* { 0, 6, 0, 0x05}, /###* 3COM ethernet */ - { 0, 7, 0, 0xff}, /* VIA southbridge */ - { 0, 7, 1, 0x0e}, /* IDE controller in legacy mode */ -/* { 0, 7, 2, 0x05}, /###* First USB controller */ -/* { 0, 7, 3, 0x0c}, /###* Second USB controller (shares interrupt with ethernet) */ - { 0, 7, 4, 0xff}, /* ACPI Power Management */ -/* { 0, 7, 5, 0x08}, /###* AC97 */ -/* { 0, 7, 6, 0x08}, /###* MC97 */ - { 0xff, 0xff, 0xff, 0xff} -}; - - -/* - * This table maps IRQ's to PCI interrupts - */ - -uint8 pci_intmap[4] = {0, 0, 0, 0}; - -/* - * Map PCI slots to interrupt routings - * This table lists the device number assigned to a card inserted - * into the slot, along with a permutation for the slot's IRQ routing. - * NOTE: This table is machine dependant. - */ - -struct pci_slot_irq_routing -{ - uint8 bus; - uint8 device; - - uint8 ints[4]; -}; - -struct pci_slot_irq_routing amigaone_pci_routing[] = -{ - {0, 8, {0, 1, 2, 3}}, /* Slot 1 (left of riser slot) */ - {0, 9, {1, 2, 3, 0}}, /* Slot 2 (middle slot) */ - {0, 10, {2, 3, 0, 1}}, /* Slot 3 (leftmost slot) */ - {1, 0, {1, 0, 2, 3}}, /* AGP slot (only IRQA and IRQB) */ - {1, 1, {1, 2, 3, 0}}, /* PCI slot on AGP bus */ - {0, 6, {3, 3, 3, 3}}, /* On board ethernet */ - {0, 7, {0, 1, 2, 3}}, /* Southbridge */ - {0xff, 0, {0, 0, 0, 0}} -}; - -void articiaS_pci_irq_init(void) -{ - char *s; - - s = getenv("pci_irqa"); - if (s) - pci_intmap[0] = simple_strtoul (s, NULL, 10); - else - pci_intmap[0] = pci_irq_alloc(); - - s = getenv("pci_irqb"); - if (s) - pci_intmap[1] = simple_strtoul (s, NULL, 10); - else - pci_intmap[1] = pci_irq_alloc(); - - s = getenv("pci_irqc"); - if (s) - pci_intmap[2] = simple_strtoul (s, NULL, 10); - else - pci_intmap[2] = pci_irq_alloc(); - - s = getenv("pci_irqd"); - if (s) - pci_intmap[3] = simple_strtoul (s, NULL, 10); - else - pci_intmap[3] = pci_irq_alloc(); -} - - -unsigned char pci_irq_alloc(void) -{ - int i; - int interrupt = 10; - unsigned long min_penalty = 1000; - - /* Search for the minimal penalty, favoring interrupts at the end */ - for (i = 0; i < 16; i++) - { - if (irq_penalties[i] <= min_penalty) - { - interrupt = i; - min_penalty = irq_penalties[i]; - } - } - - PRINTF("pci_irq_alloc: Minimal penalty is %ld for %d\n", min_penalty, interrupt); - - irq_penalties[interrupt]++; - - return interrupt; -} - - -void articiaS_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - int8 bus, device, func, pin, line; - int i; - - bus = PCI_BUS(dev); - device = PCI_DEV(dev); - func = PCI_FUNC(dev); - - PRINTF("Fixup irq of %d:%d.%d\n", bus, device, func); - - /* Search for the device in the table */ - for (i = 0; fixuptab[i].bus != 0xff; i++) - { - if (bus == fixuptab[i].bus && device == fixuptab[i].device && func == fixuptab[i].func) - { - /* If the device needs an interrupt, write it */ - if (fixuptab[i].interrupt != 0xff) - { - PRINTF("Assigning IRQ %d (fixed)\n", fixuptab[i].interrupt); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, fixuptab[i].interrupt); - } - else - { - /* Otherwise, see if it wants an interrupt, and disable it if needed */ - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); - if (pin) - { - PRINTF("Disabling IRQ\n"); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0xff); - } - } - - return; - } - } - - /* If we get here, we have another PCI device in a slot... find the appropriate IRQ */ - - /* Find matching pin */ - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); - pin--; - - /* Search for it's map */ - for (i = 0; amigaone_pci_routing[i].bus != 0xff; i++) - { - if (bus == amigaone_pci_routing[i].bus && device == amigaone_pci_routing[i].device) - { - line = pci_intmap[amigaone_pci_routing[i].ints[pin]]; - PRINTF("Assigning IRQ %d (pin %d)\n", line, pin); - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, line); - return; - } - } - - PRINTF("Unkonwn PCI device found\n"); -} - -void articiaS_pci_init (void) -{ - int i; - char *s; - - PRINTF("atriciaS_pci_init\n"); - - /* Why aren't these relocated?? */ - for (i=0; config_table[i].config_device; i++) - { - switch((int)config_table[i].config_device) - { - case cfgfunc_via686: config_table[i].config_device = via_cfgfunc_via686; break; - case cfgfunc_dummy: config_table[i].config_device = pci_cfgfunc_dummy; break; - case cfgfunc_ide_init: config_table[i].config_device = via_cfgfunc_ide_init; break; - default: PRINTF("Error: Unknown constant\n"); - } - } - - articiaS_hose.first_busno = 0; - articiaS_hose.last_busno = 0xff; - articiaS_hose.config_table = config_table; - articiaS_hose.fixup_irq = articiaS_pci_fixup_irq; - - articiaS_pci_irq_init(); - - /* System memory */ - pci_set_region(articiaS_hose.regions + 0, - ARTICIAS_SYS_BUS, - ARTICIAS_SYS_PHYS, - ARTICIAS_SYS_MAXSIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region(articiaS_hose.regions + 1, - ARTICIAS_PCI_BUS, - ARTICIAS_PCI_PHYS, - ARTICIAS_PCI_MAXSIZE, - PCI_REGION_MEM); - - /* PCI io space */ - pci_set_region(articiaS_hose.regions + 2, - ARTICIAS_PCIIO_BUS, - ARTICIAS_PCIIO_PHYS, - ARTICIAS_PCIIO_MAXSIZE, - PCI_REGION_IO); - - /* PCI/ISA io space */ - pci_set_region(articiaS_hose.regions + 3, - ARTICIAS_ISAIO_BUS, - ARTICIAS_ISAIO_PHYS, - ARTICIAS_ISAIO_MAXSIZE, - PCI_REGION_IO); - - - articiaS_hose.region_count = 4; - - pci_setup_indirect(&articiaS_hose, ARTICIAS_PCI_CFGADDR, ARTICIAS_PCI_CFGDATA); - PRINTF("Registering articia hose...\n"); - pci_register_hose(&articiaS_hose); - PRINTF("Enabling AGP...\n"); - pci_write_config_byte(PCI_BDF(0,0,0), 0x58, 0x01); - PRINTF("Scanning bus...\n"); - articiaS_hose.last_busno = pci_hose_scan(&articiaS_hose); - - via_init_irq_routing(pci_intmap); - - PRINTF("After-Scan results:\n"); - PRINTF("Bus range: %d - %d\n", articiaS_hose.first_busno , articiaS_hose.last_busno); - - via_init_afterscan(); - - pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF); - - s = getenv("as_irq"); - if (s) - { - pci_write_config_byte(PCI_BDF(0,0,0), PCI_INTERRUPT_LINE, simple_strtoul (s, NULL, 10)); - } - - s = getenv("x86_run_bios"); - if (!s || (s && strcmp(s, "on")==0)) - { - if (articiaS_init_vga() == -1) - { - /* If the VGA didn't init and we have stdout set to VGA, reset to serial */ -/* s = getenv("stdout"); */ -/* if (s && strcmp(s, "vga") == 0) */ -/* { */ -/* setenv("stdout", "serial"); */ -/* } */ - } - } - pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF); - -} - -pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index) -{ - unsigned int sub_bus, found_multi=0; - unsigned short vendor, class; - unsigned char header_type; - pci_dev_t dev; - u8 c1, c2; - - sub_bus = bus; - - for (dev = PCI_BDF(bus,0,0); - dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); - dev += PCI_BDF(0,0,1)) - { - if ( dev == PCI_BDF(hose->first_busno,0,0) ) - continue; - - if (PCI_FUNC(dev) && !found_multi) - continue; - - pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); - - pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); - - if (vendor != 0xffff && vendor != 0x0000) - { - - if (!PCI_FUNC(dev)) - found_multi = header_type & 0x80; - pci_hose_read_config_byte(hose, dev, 0x0B, &c1); - pci_hose_read_config_byte(hose, dev, 0x0A, &c2); - class = c1<<8 | c2; - /*printf("At %02x:%02x:%02x: class %x\n", */ - /* PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), class); */ - if (class == find_class) - { - if (index == 0) - return dev; - else index--; - } - } - } - - return ~0; -} - - -/* - * For a given bus number, find the bridge on this hose that provides this - * bus number. The function scans for bridges and peeks config space offset - * 0x19 (PCI_SECONDARY_BUS). - */ -pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr) -{ - pci_dev_t dev; - int bus; - unsigned int found_multi=0; - unsigned char header_type; - unsigned short vendor; - unsigned char secondary_bus; - - if (hose == NULL) hose = &articiaS_hose; - - if (busnr < hose->first_busno || busnr > hose->last_busno) return PCI_ANY_ID; /* Not in range */ - - /* - * The bridge must be on a lower bus number - */ - for (bus = hose->first_busno; bus < busnr; bus++) - { - for (dev = PCI_BDF(bus,0,0); - dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); - dev += PCI_BDF(0,0,1)) - { - if ( dev == PCI_BDF(hose->first_busno,0,0) ) - continue; - - if (PCI_FUNC(dev) && !found_multi) - continue; - - pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); - - pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); - - if (vendor != 0xffff && vendor != 0x0000) - { - - if (!PCI_FUNC(dev)) - found_multi = header_type & 0x80; - if (header_type == 1) /* Bridge device header */ - { - pci_hose_read_config_byte(hose, dev, PCI_SECONDARY_BUS, &secondary_bus); - if ((int)secondary_bus == busnr) return dev; - } - - } - } - } - return PCI_ANY_ID; -} - -static short classes[] = -{ - PCI_CLASS_DISPLAY_VGA, - PCI_CLASS_DISPLAY_XGA, - PCI_CLASS_DISPLAY_3D, - PCI_CLASS_DISPLAY_OTHER, - ~0 -}; - -extern int execute_bios(pci_dev_t gr_dev, void *); - -pci_dev_t video_dev; - -int articiaS_init_vga (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - extern void shutdown_bios(void); - pci_dev_t dev = ~0; - int busnr = 0; - int classnr = 0; - - video_dev = PCI_ANY_ID; - - printf("VGA: "); - - PRINTF("Trying to initialize x86 VGA Card(s)\n"); - - while (dev == ~0) - { - PRINTF("Searching for class 0x%x on bus %d\n", classes[classnr], busnr); - /* Find the first of this class on this bus */ - dev = pci_hose_find_class(&articiaS_hose, busnr, classes[classnr], 0); - if (dev != ~0) - { - PRINTF("Found VGA Card at %02x:%02x:%02x\n", PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); - break; - } - busnr++; - if (busnr > articiaS_hose.last_busno) - { - busnr = 0; - classnr ++; - if (classes[classnr] == ~0) - { - printf("NOT PRESENT\n"); - return -1; - } - } - } - - /* - * If we get here we have found the first graphics card. - * If the bus number is not 0, then it is probably behind a bridge, and the - * bridge needs to be told to forward VGA access. - */ - - if (PCI_BUS(dev) != 0) - { - pci_dev_t bridge; - PRINTF("Behind bridge, looking for bridge\n"); - bridge = pci_find_bridge_for_bus(&articiaS_hose, PCI_BUS(dev)); - if (dev != PCI_ANY_ID) - { - unsigned char agp_control_0; - PRINTF("Got the bridge at %02x:%02x:%02x\n", - PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge)); - pci_hose_read_config_byte(&articiaS_hose, bridge, 0x3E, &agp_control_0); - agp_control_0 |= 0x18; - pci_hose_write_config_byte(&articiaS_hose, bridge, 0x3E, agp_control_0); - PRINTF("Configured for VGA forwarding\n"); - } - } - - /* - * Now try to run the bios - */ - PRINTF("Trying to run bios now\n"); - if (execute_bios(dev, gd->relocaddr)) - { - printf("OK\n"); - video_dev = dev; - } - else - { - printf("ERROR\n"); - } - - PRINTF("Done scanning.\n"); - - shutdown_bios(); - - if (dev == PCI_ANY_ID) return -1; - else return 0; - -} diff --git a/board/MAI/AmigaOneG3SE/board_asm_init.S b/board/MAI/AmigaOneG3SE/board_asm_init.S deleted file mode 100644 index 086b19c..0000000 --- a/board/MAI/AmigaOneG3SE/board_asm_init.S +++ /dev/null @@ -1,156 +0,0 @@ -#include "macros.h" - - -#define GLOBALINFO0 0x50 -#define GLOBALINFO0_BO (1<<7) -#define GLOBALINFO2_B1ARBITER (1<<6) -#define HBUSACR0 0x5c -#define HBUSACR2_BURST (1<<0) -#define HBUSACR2_LAT (1<<1) - -#define RECEIVER_HOLDING 0 -#define TRANSMITTER_HOLDING 0 -#define INTERRUPT_ENABLE 1 -#define INTERRUPT_STATUS 2 -#define FIFO_CONTROL 2 -#define LINE_CONTROL 3 -#define MODEM_CONTROL 4 -#define LINE_STATUS 5 -#define MODEM_STATUS 6 -#define SCRATCH_PAD 7 - -#define DIVISOR_LATCH_LSB 0 -#define DIVISOR_LATCH_MSB 1 -#define PRESCALER_DIVISION 5 - -#define UART(x) (0x3f8+(x)) - -#define GLOBALINFO0 0x50 -#define GLOBALINFO0_BO (1<<7) -#define GLOBALINFO2_B1ARBITER (1<<6) -#define HBUSACR0 0x5c -#define HBUSACR2_BURST (1<<0) -#define HBUSACR2_LAT (1<<1) - -#define SUPERIO_1 ((7 << 3) | (0)) -#define SUPERIO_2 ((7 << 3) | (1)) - - .globl board_asm_init - -board_asm_init: - mflr r29 - /* Set 'Must-set' register */ - li r3, 0 - li r4, 0 - li r5, 0x5e - bl pci_read_cfg_byte - ori r3, r3, (1<<1) - xori r6, r3, (1<<1) - li r3, 0 - bl pci_write_cfg_byte - - li r3, 0 - li r5, 0x52 - bl pci_read_cfg_byte - ori r6, r3, (1<<6) - li r3, 0 - bl pci_write_cfg_byte - - li r3, 0 - li r4, 0x08 - li r5, 0xd2 - bl pci_read_cfg_byte - ori r6, r3, (1<<2) - li r3, 0 - bl pci_write_cfg_byte - - - /* Do PCI reset */ -/* li r3, 0 - li r4, 0x38 - li r5, 0x47 - bl pci_read_cfg_byte - ori r6, r3, 0x01 - li r3, 0 - li r4, 0x38 - li r5, 0x47 - bl pci_write_cfg_byte*/ - - - /* Enable NVRAM for environment */ - li r3, 0 - li r4, 0 - li r5, 0x56 - li r6, 0x0B - bl pci_write_cfg_byte - - - /* Init Super-I/O chips */ - - siowb 0x40, 0x08 - siowb 0x41, 0x01 - siowb 0x45, 0x80 - siowb 0x46, 0x60 - siowb 0x47, 0x20 - siowb 0x48, 0x01 - siowb 0x4a, 0xc4 - siowb 0x50, 0x0e - siowb 0x51, 0x76 - siowb 0x52, 0x34 - siowb 0x54, 0x00 - siowb 0x55, 0x90 - siowb 0x56, 0x99 - siowb 0x57, 0x90 - siowb 0x85, 0x01 - - /* Enable configuration mode for SuperIO */ - li r3, 0 - li r4, (7<<3) - li r5, 0x85 - bl pci_read_cfg_byte - ori r6, r3, 0x02 - mr r31, r6 - li r3,0 - bl pci_write_cfg_byte - - /* COM1 as 3f8 */ - outb 0x3f0, 0xe7 - outb 0x3f1, 0xfe - - /* COM2 as 2f8 */ - outb 0x3f0, 0xe8 - outb 0x3f1, 0xeb - - /* Enable */ - outb 0x3f0, 0xe2 - inb r3, 0x3f1 - ori r3, r3, 0x0c - outb 0x3f0, 0xe2 - outbr 0x3f1, r3 - - /* Disable configuration mode */ - li r3, 0 - li r4, (7<<3) - li r5, 0x85 - mr r6, r31 - bl pci_write_cfg_byte - - /* Set line control */ - outb UART(LINE_CONTROL), 0x83 - outb UART(DIVISOR_LATCH_LSB), 0x0c - outb UART(DIVISOR_LATCH_MSB), 0x00 - outb UART(LINE_CONTROL), 0x3 - - mtlr r29 - blr - - - .globl new_reset - .globl new_reset_end -new_reset: - li r0, 0x100 - oris r0, r0, 0xFFF0 - mtlr r0 - blr - -new_reset_end: diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c deleted file mode 100644 index 3e2835a..0000000 --- a/board/MAI/AmigaOneG3SE/cmd_boota.c +++ /dev/null @@ -1,129 +0,0 @@ -#include -#include -#include "../disk/part_amiga.h" -#include - - -#undef BOOTA_DEBUG - -#ifdef BOOTA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -struct block_header { - u32 id; - u32 summed_longs; - s32 chk_sum; -}; - -extern block_dev_desc_t *ide_get_dev (int dev); -extern struct bootcode_block *get_bootcode (block_dev_desc_t * dev_desc); -extern int sum_block (struct block_header *header); - -struct bootcode_block bblk; - -int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - unsigned char *load_address = (unsigned char *) CFG_LOAD_ADDR; - unsigned char *base_address; - unsigned long offset; - - unsigned long part_number = 0; - block_dev_desc_t *boot_disk; - char *s; - struct bootcode_block *boot_code; - - /* Get parameters */ - - switch (argc) { - case 2: - load_address = (unsigned char *) simple_strtol (argv[1], NULL, 16); - part_number = 0; - break; - case 3: - load_address = (unsigned char *) simple_strtol (argv[1], NULL, 16); - part_number = simple_strtol (argv[2], NULL, 16); - break; - } - - base_address = load_address; - - PRINTF ("Loading boot code from disk %d to %p\n", part_number, - load_address); - - /* Find the appropriate disk device */ - boot_disk = ide_get_dev (part_number); - if (!boot_disk) { - PRINTF ("Unknown disk %d\n", part_number); - return 1; - } - - /* Find the bootcode block */ - boot_code = get_bootcode (boot_disk); - if (!boot_code) { - PRINTF ("Not a bootable disk %d\n", part_number); - return 1; - } - - /* Only use the offset from the first block */ - offset = boot_code->load_data[0]; - memcpy (load_address, &boot_code->load_data[1], 122 * 4); - load_address += 122 * 4; - - /* Setup for the loop */ - bblk.next = boot_code->next; - boot_code = &bblk; - - /* Scan the chain, and copy the loader succesively into the destination area */ - while (0xffffffff != boot_code->next) { - PRINTF ("Loading block %d\n", boot_code->next); - - /* Load block */ - if (1 != - boot_disk->block_read (boot_disk->dev, boot_code->next, 1, - (ulong *) & bblk)) { - PRINTF ("Read error\n"); - return 1; - } - - /* check sum */ - if (sum_block ((struct block_header *) (ulong *) & bblk) != 0) { - PRINTF ("Checksum error\n"); - return 1; - } - - /* Ok, concatenate it to the already loaded code */ - memcpy (load_address, boot_code->load_data, 123 * 4); - load_address += 123 * 4; - } - - printf ("Bootcode loaded to %p (size %d)\n", base_address, - load_address - base_address); - printf ("Entry point at %p\n", base_address + offset); - - flush_cache (base_address, load_address - base_address); - - - s = getenv ("autostart"); - if (s && strcmp (s, "yes") == 0) { - DECLARE_GLOBAL_DATA_PTR; - - void (*boot) (bd_t *, char *, block_dev_desc_t *); - char *args; - - boot = (void (*)(bd_t *, char *, block_dev_desc_t *)) (base_address + offset); - boot (gd->bd, getenv ("amiga_bootargs"), boot_disk); - } - - - return 0; -} -#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP) -U_BOOT_CMD( - boota, 3, 1, do_boota, - "boota - boot an Amiga kernel\n", - "address disk" -); -#endif /* _CMD_BOOTA_H */ diff --git a/board/MAI/AmigaOneG3SE/config.mk b/board/MAI/AmigaOneG3SE/config.mk deleted file mode 100644 index 930a793..0000000 --- a/board/MAI/AmigaOneG3SE/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# AmigaOneG3SE boards -# - -X86EMU = -I../bios_emulator/scitech/include -I../bios_emulator/scitech/src/x86emu - -TEXT_BASE = 0xfff00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -Wa,-mregnames -DEASTEREGG $(X86EMU) -Dprintk=printf #-DDEBUG diff --git a/board/MAI/AmigaOneG3SE/enet.c b/board/MAI/AmigaOneG3SE/enet.c deleted file mode 100644 index d4be889..0000000 --- a/board/MAI/AmigaOneG3SE/enet.c +++ /dev/null @@ -1,884 +0,0 @@ -/* - * (C) Copyright 2002 - * Adam Kowalczyk, ACK Software Controls Inc. akowalczyk@cogeco.ca - * - * Some portions taken from 3c59x.c Written 1996-1999 by Donald Becker. - * - * Outline of the program based on eepro100.c which is - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include "articiaS.h" -#include "memio.h" - -/* 3Com Ethernet PCI definitions*/ - -/* #define PCI_VENDOR_ID_3COM 0x10B7 */ -#define PCI_DEVICE_ID_3COM_3C905C 0x9200 - -/* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */ - -#define TotalReset (0<<11) -#define SelectWindow (1<<11) -#define StartCoax (2<<11) -#define RxDisable (3<<11) -#define RxEnable (4<<11) -#define RxReset (5<<11) -#define UpStall (6<<11) -#define UpUnstall (6<<11)+1 -#define DownStall (6<<11)+2 -#define DownUnstall (6<<11)+3 -#define RxDiscard (8<<11) -#define TxEnable (9<<11) -#define TxDisable (10<<11) -#define TxReset (11<<11) -#define FakeIntr (12<<11) -#define AckIntr (13<<11) -#define SetIntrEnb (14<<11) -#define SetStatusEnb (15<<11) -#define SetRxFilter (16<<11) -#define SetRxThreshold (17<<11) -#define SetTxThreshold (18<<11) -#define SetTxStart (19<<11) -#define StartDMAUp (20<<11) -#define StartDMADown (20<<11)+1 -#define StatsEnable (21<<11) -#define StatsDisable (22<<11) -#define StopCoax (23<<11) -#define SetFilterBit (25<<11) - -/* The SetRxFilter command accepts the following classes */ - -#define RxStation 1 -#define RxMulticast 2 -#define RxBroadcast 4 -#define RxProm 8 - -/* 3Com status word defnitions */ - -#define IntLatch 0x0001 -#define HostError 0x0002 -#define TxComplete 0x0004 -#define TxAvailable 0x0008 -#define RxComplete 0x0010 -#define RxEarly 0x0020 -#define IntReq 0x0040 -#define StatsFull 0x0080 -#define DMADone (1<<8) -#define DownComplete (1<<9) -#define UpComplete (1<<10) -#define DMAInProgress (1<<11) /* DMA controller is still busy.*/ -#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/ - -/* Polling Registers */ - -#define DnPoll 0x2d -#define UpPoll 0x3d - -/* Register window 0 offets */ - -#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */ -#define Wn0EepromData 12 /* Window 0: EEPROM results register. */ -#define IntrStatus 0x0E /* Valid in all windows. */ - -/* Register window 0 EEPROM bits */ - -#define EEPROM_Read 0x80 -#define EEPROM_WRITE 0x40 -#define EEPROM_ERASE 0xC0 -#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */ -#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */ - -/* EEPROM locations. */ - -#define PhysAddr01 0 -#define PhysAddr23 1 -#define PhysAddr45 2 -#define ModelID 3 -#define EtherLink3ID 7 -#define IFXcvrIO 8 -#define IRQLine 9 -#define NodeAddr01 10 -#define NodeAddr23 11 -#define NodeAddr45 12 -#define DriverTune 13 -#define Checksum 15 - -/* Register window 1 offsets, the window used in normal operation */ - -#define TX_FIFO 0x10 -#define RX_FIFO 0x10 -#define RxErrors 0x14 -#define RxStatus 0x18 -#define Timer 0x1A -#define TxStatus 0x1B -#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */ - -/* Register Window 2 */ - -#define Wn2_ResetOptions 12 - -/* Register Window 3: MAC/config bits */ - -#define Wn3_Config 0 /* Internal Configuration */ -#define Wn3_MAC_Ctrl 6 -#define Wn3_Options 8 - -#define BFEXT(value, offset, bitcount) \ - ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1)) - -#define BFINS(lhs, rhs, offset, bitcount) \ - (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ - (((rhs) & ((1 << (bitcount)) - 1)) << (offset))) - -#define RAM_SIZE(v) BFEXT(v, 0, 3) -#define RAM_WIDTH(v) BFEXT(v, 3, 1) -#define RAM_SPEED(v) BFEXT(v, 4, 2) -#define ROM_SIZE(v) BFEXT(v, 6, 2) -#define RAM_SPLIT(v) BFEXT(v, 16, 2) -#define XCVR(v) BFEXT(v, 20, 4) -#define AUTOSELECT(v) BFEXT(v, 24, 1) - -/* Register Window 4: Xcvr/media bits */ - -#define Wn4_FIFODiag 4 -#define Wn4_NetDiag 6 -#define Wn4_PhysicalMgmt 8 -#define Wn4_Media 10 - -#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */ -#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */ -#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */ -#define Media_LnkBeat 0x0800 - -/* Register Window 7: Bus Master control */ - -#define Wn7_MasterAddr 0 -#define Wn7_MasterLen 6 -#define Wn7_MasterStatus 12 - -/* Boomerang bus master control registers. */ - -#define PktStatus 0x20 -#define DownListPtr 0x24 -#define FragAddr 0x28 -#define FragLen 0x2c -#define TxFreeThreshold 0x2f -#define UpPktStatus 0x30 -#define UpListPtr 0x38 - -/* The Rx and Tx descriptor lists. */ - -#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ -#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */ - -struct rx_desc_3com { - u32 next; /* Last entry points to 0 */ - u32 status; /* FSH -> Frame Start Header */ - u32 addr; /* Up to 63 addr/len pairs possible */ - u32 length; /* Set LAST_FRAG to indicate last pair */ -}; - -/* Values for the Rx status entry. */ - -#define RxDComplete 0x00008000 -#define RxDError 0x4000 -#define IPChksumErr (1<<25) -#define TCPChksumErr (1<<26) -#define UDPChksumErr (1<<27) -#define IPChksumValid (1<<29) -#define TCPChksumValid (1<<30) -#define UDPChksumValid (1<<31) - -struct tx_desc_3com { - u32 next; /* Last entry points to 0 */ - u32 status; /* bits 0:12 length, others see below */ - u32 addr; - u32 length; -}; - -/* Values for the Tx status entry. */ - -#define CRCDisable 0x2000 -#define TxDComplete 0x8000 -#define AddIPChksum 0x02000000 -#define AddTCPChksum 0x04000000 -#define AddUDPChksum 0x08000000 -#define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */ - -/* XCVR Types */ - -#define XCVR_10baseT 0 -#define XCVR_AUI 1 -#define XCVR_10baseTOnly 2 -#define XCVR_10base2 3 -#define XCVR_100baseTx 4 -#define XCVR_100baseFx 5 -#define XCVR_MII 6 -#define XCVR_NWAY 8 -#define XCVR_ExtMII 9 -#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */ - -struct descriptor { /* A generic descriptor. */ - u32 next; /* Last entry points to 0 */ - u32 status; /* FSH -> Frame Start Header */ - u32 addr; /* Up to 63 addr/len pairs possible */ - u32 length; /* Set LAST_FRAG to indicate last pair */ -}; - -/* Misc. definitions */ - -#define NUM_RX_DESC PKTBUFSRX * 10 -#define NUM_TX_DESC 1 /* Number of TX descriptors */ - -#define TOUT_LOOP 1000000 - -#define ETH_ALEN 6 - -#define EL3WINDOW(dev, win_num) ETH_OUTW(dev, SelectWindow + (win_num), EL3_CMD) -#define EL3_CMD 0x0e -#define EL3_STATUS 0x0e - - -#undef ETH_DEBUG - -#ifdef ETH_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - - -static struct rx_desc_3com *rx_ring; /* RX descriptor ring */ -static struct tx_desc_3com *tx_ring; /* TX descriptor ring */ -static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN]; /* storage for the incoming messages */ -static int rx_next = 0; /* RX descriptor ring pointer */ -static int tx_next = 0; /* TX descriptor ring pointer */ -static int tx_threshold; - -static void init_rx_ring(struct eth_device* dev); -static void purge_tx_ring(struct eth_device* dev); - -static void read_hw_addr(struct eth_device* dev, bd_t * bis); - -static int eth_3com_init(struct eth_device* dev, bd_t *bis); -static int eth_3com_send(struct eth_device* dev, volatile void *packet, int length); -static int eth_3com_recv(struct eth_device* dev); -static void eth_3com_halt(struct eth_device* dev); - -#define io_to_phys(a) pci_io_to_phys((pci_dev_t)dev->priv, a) -#define phys_to_io(a) pci_phys_to_io((pci_dev_t)dev->priv, a) -#define mem_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) -#define phys_to_mem(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) - -static inline int ETH_INL(struct eth_device* dev, u_long addr) -{ - __asm volatile ("eieio"); - return le32_to_cpu(*(volatile u32 *)io_to_phys(addr + dev->iobase)); -} - -static inline int ETH_INW(struct eth_device* dev, u_long addr) -{ - __asm volatile ("eieio"); - return le16_to_cpu(*(volatile u16 *)io_to_phys(addr + dev->iobase)); -} - -static inline int ETH_INB(struct eth_device* dev, u_long addr) -{ - __asm volatile ("eieio"); - return *(volatile u8 *)io_to_phys(addr + dev->iobase); -} - -static inline void ETH_OUTB(struct eth_device* dev, int command, u_long addr) -{ - *(volatile u8 *)io_to_phys(addr + dev->iobase) = command; - __asm volatile ("eieio"); -} - -static inline void ETH_OUTW(struct eth_device* dev, int command, u_long addr) -{ - *(volatile u16 *)io_to_phys(addr + dev->iobase) = cpu_to_le16(command); - __asm volatile ("eieio"); -} - -static inline void ETH_OUTL(struct eth_device* dev, int command, u_long addr) -{ - *(volatile u32 *)io_to_phys(addr + dev->iobase) = cpu_to_le32(command); - __asm volatile ("eieio"); -} - -static inline int ETH_STATUS(struct eth_device* dev) -{ - __asm volatile ("eieio"); - return le16_to_cpu(*(volatile u16 *)io_to_phys(EL3_STATUS + dev->iobase)); -} - -static inline void ETH_CMD(struct eth_device* dev, int command) -{ - *(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command); - __asm volatile ("eieio"); -} - -/* Command register is always in the same spot in all the register windows */ -/* This function issues a command and waits for it so complete by checking the CmdInProgress bit */ - -static int issue_and_wait(struct eth_device* dev, int command) -{ - - int i, status; - - ETH_CMD(dev, command); - for (i = 0; i < 2000; i++) { - status = ETH_STATUS(dev); - /*printf ("Issue: status 0x%4x.\n", status); */ - if (!(status & CmdInProgress)) - return 1; - } - - /* OK, that didn't work. Do it the slow way. One second */ - for (i = 0; i < 100000; i++) { - status = ETH_STATUS(dev); - /*printf ("Issue: status 0x%4x.\n", status); */ - return 1; - udelay(10); - } - PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) ); - return 0; -} - -/* Determine network media type and set up 3com accordingly */ -/* I think I'm going to start with something known first like 10baseT */ - -static int auto_negotiate(struct eth_device* dev) -{ - int i; - - EL3WINDOW(dev, 1); - - /* Wait for Auto negotiation to complete */ - for (i = 0; i <= 1000; i++) - { - if (ETH_INW(dev, 2) & 0x04) - break; - udelay(100); - - if (i == 1000) - { - PRINTF("Error: Auto negotiation failed\n"); - return 0; - } - } - - - return 1; -} - -void eth_interrupt(struct eth_device *dev) -{ - u16 status = ETH_STATUS(dev); - - printf("eth0: status = 0x%04x\n", status); - - if (!(status & IntLatch)) - return; - - if (status & (1<<6)) - { - ETH_CMD(dev, AckIntr | (1<<6)); - printf("Acknowledged Interrupt command\n"); - } - - if (status & DownComplete) - { - ETH_CMD(dev, AckIntr | DownComplete); - printf("Acknowledged DownComplete\n"); - } - - if (status & UpComplete) - { - ETH_CMD(dev, AckIntr | UpComplete); - printf("Acknowledged UpComplete\n"); - } - - ETH_CMD(dev, AckIntr | IntLatch); - printf("Acknowledged IntLatch\n"); -} - -int eth_3com_initialize(bd_t *bis) -{ - u32 eth_iobase = 0, status; - int card_number = 0, ret; - struct eth_device* dev; - pci_dev_t devno; - char *s; - - s = getenv("3com_base"); - - /* Find ethernet controller on the PCI bus */ - - if ((devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0)) < 0) - { - PRINTF("Error: Cannot find the ethernet device on the PCI bus\n"); - goto Done; - } - - if (s) - { - unsigned long base = atoi(s); - pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, base | 0x01); - } - - ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, ð_iobase); - eth_iobase &= ~0xf; - - PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase); - - pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - /* Check if I/O accesses and Bus Mastering are enabled */ - - ret = pci_read_config_dword(devno, PCI_COMMAND, &status); - - if (!(status & PCI_COMMAND_IO)) - { - printf("Error: Cannot enable IO access.\n"); - goto Done; - } - - if (!(status & PCI_COMMAND_MEMORY)) - { - printf("Error: Cannot enable MEMORY access.\n"); - goto Done; - } - - if (!(status & PCI_COMMAND_MASTER)) - { - printf("Error: Cannot enable Bus Mastering.\n"); - goto Done; - } - - dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */ - - sprintf(dev->name, "3Com 3c920c#%d", card_number); - dev->iobase = eth_iobase; - dev->priv = (void*) devno; - dev->init = eth_3com_init; - dev->halt = eth_3com_halt; - dev->send = eth_3com_send; - dev->recv = eth_3com_recv; - - eth_register(dev); - -/* { */ -/* char interrupt; */ -/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */ -/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */ - -/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */ -/* irq_install_handler(interrupt, eth_interrupt, dev); */ -/* } */ - - card_number++; - - /* Set the latency timer for value */ - s = getenv("3com_latency"); - if (s) - { - ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, (unsigned char)atoi(s)); - } - else ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x0a); - - read_hw_addr(dev, bis); /* get the MAC address from Window 2*/ - - /* Reset the ethernet controller */ - - PRINTF ("Issuing reset command....\n"); - if (!issue_and_wait(dev, TotalReset)) - { - printf("Error: Cannot reset ethernet controller.\n"); - goto Done; - } - else - PRINTF ("Ethernet controller reset.\n"); - - /* allocate memory for rx and tx rings */ - - if(!(rx_ring = memalign(sizeof(struct rx_desc_3com) * NUM_RX_DESC, 16))) - { - PRINTF ("Cannot allocate memory for RX_RING.....\n"); - goto Done; - } - - if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16))) - { - PRINTF ("Cannot allocate memory for TX_RING.....\n"); - goto Done; - } - -Done: - return status; -} - - -static int eth_3com_init(struct eth_device* dev, bd_t *bis) -{ - int i, status = 0; - int tx_cur, loop; - u16 status_enable, intr_enable; - struct descriptor *ias_cmd; - - /* Determine what type of network the machine is connected to */ - /* presently drops the connect to 10Mbps */ - - if (!auto_negotiate(dev)) - { - printf("Error: Cannot determine network media.\n"); - goto Done; - } - - issue_and_wait(dev, TxReset); - issue_and_wait(dev, RxReset|0x04); - - /* Switch to register set 7 for normal use. */ - EL3WINDOW(dev, 7); - - /* Initialize Rx and Tx rings */ - - init_rx_ring(dev); - purge_tx_ring(dev); - - ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm); - - issue_and_wait(dev,SetTxStart|0x07ff); - - /* Below sets which indication bits to be seen. */ - - status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6); - ETH_CMD(dev, status_enable); - - /* Below sets no bits are to cause an interrupt since this is just polling */ - - intr_enable = SetIntrEnb; -/* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */ - ETH_CMD(dev, intr_enable); - ETH_OUTB(dev, 127, UpPoll); - - /* Ack all pending events, and set active indicator mask */ - - ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq); - ETH_CMD(dev, intr_enable); - - /* Tell the adapter where the RX ring is located */ - - issue_and_wait(dev,UpStall); /* Stall and set the UplistPtr */ - ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr); - ETH_CMD(dev, RxEnable); /* Enable the receiver. */ - issue_and_wait(dev,UpUnstall); - - /* Send the Individual Address Setup frame */ - - tx_cur = tx_next; - tx_next = ((tx_next+1) % NUM_TX_DESC); - - ias_cmd = (struct descriptor *)&tx_ring[tx_cur]; - ias_cmd->status = cpu_to_le32(1<<31); /* set DnIndicate bit. */ - ias_cmd->next = 0; - ias_cmd->addr = cpu_to_le32((u32)&bis->bi_enetaddr[0]); - ias_cmd->length = cpu_to_le32(6 | LAST_FRAG); - - /* Tell the adapter where the TX ring is located */ - - ETH_CMD(dev, TxEnable); /* Enable transmitter. */ - issue_and_wait(dev, DownStall); /* Stall and set the DownListPtr. */ - ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr); - issue_and_wait(dev, DownUnstall); - for (i=0; !(ETH_STATUS(dev) & DownComplete); i++) - { - if (i >= TOUT_LOOP) - { - PRINTF("TX Ring status (Init): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status)); - PRINTF("ETH_STATUS: 0x%x\n", ETH_STATUS(dev)); - goto Done; - } - } - if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */ - { - ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */ - issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */ - ETH_OUTL(dev, 0, DownListPtr); - issue_and_wait(dev, DownUnstall); - } - status = 1; - -Done: - return status; -} - -int eth_3com_send(struct eth_device* dev, volatile void *packet, int length) -{ - int i, status = 0; - int tx_cur; - - if (length <= 0) - { - PRINTF("eth: bad packet size: %d\n", length); - goto Done; - } - - tx_cur = tx_next; - tx_next = (tx_next+1) % NUM_TX_DESC; - - tx_ring[tx_cur].status = cpu_to_le32(1<<31); /* set DnIndicate bit */ - tx_ring[tx_cur].next = 0; - tx_ring[tx_cur].addr = cpu_to_le32(((u32) packet)); - tx_ring[tx_cur].length = cpu_to_le32(length | LAST_FRAG); - - /* Send the packet */ - - issue_and_wait(dev, DownStall); /* stall and set the DownListPtr */ - ETH_OUTL(dev, (u32) &tx_ring[tx_cur], DownListPtr); - issue_and_wait(dev, DownUnstall); - - for (i=0; !(ETH_STATUS(dev) & DownComplete); i++) - { - if (i >= TOUT_LOOP) - { - PRINTF("TX Ring status (send): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status)); - goto Done; - } - } - if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */ - { - ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */ - issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */ - ETH_OUTL(dev, 0, DownListPtr); - issue_and_wait(dev, DownUnstall); - } - status=1; - Done: - return status; -} - -void PrintPacket (uchar *packet, int length) -{ -int loop; -uchar *ptr; - - printf ("Printing packet of length %x.\n\n", length); - ptr = packet; - for (loop = 1; loop <= length; loop++) - { - printf ("%2x ", *ptr++); - if ((loop % 40)== 0) - printf ("\n"); - } -} - -int eth_3com_recv(struct eth_device* dev) -{ - u16 stat = 0; - u32 status; - int rx_prev, length = 0; - - while (!(ETH_STATUS(dev) & UpComplete)) /* wait on receipt of packet */ - ; - - status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */ - - while (status & (1<<15)) - { - /* A packet has been received */ - - if (status & (1<<15)) - { - /* A valid frame received */ - - length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */ - - /* Pass the packet up to the protocol layers */ - - NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length); - rx_ring[rx_next].status = 0; /* clear the status word */ - ETH_CMD(dev, AckIntr | UpComplete); - issue_and_wait(dev, UpUnstall); - } - else - if (stat & HostError) - { - /* There was an error */ - - printf("Rx error status: 0x%4x\n", stat); - init_rx_ring(dev); - goto Done; - } - - rx_prev = rx_next; - rx_next = (rx_next + 1) % NUM_RX_DESC; - stat = ETH_STATUS(dev); /* register status */ - status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */ - } - -Done: - return length; -} - -void eth_3com_halt(struct eth_device* dev) -{ - if (!(dev->iobase)) - { - goto Done; - } - - issue_and_wait(dev, DownStall); /* shut down transmit and receive */ - issue_and_wait(dev, UpStall); - issue_and_wait(dev, RxDisable); - issue_and_wait(dev, TxDisable); - -/* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */ -/* free(rx_ring); */ - -Done: - return; -} - -static void init_rx_ring(struct eth_device* dev) -{ - int i; - - PRINTF("Initializing rx_ring. rx_buffer = %p\n", rx_buffer); - issue_and_wait(dev, UpStall); - - for (i = 0; i < NUM_RX_DESC; i++) - { - rx_ring[i].next = cpu_to_le32(((u32) &rx_ring[(i+1) % NUM_RX_DESC])); - rx_ring[i].status = 0; - rx_ring[i].addr = cpu_to_le32(((u32) &rx_buffer[i][0])); - rx_ring[i].length = cpu_to_le32(PKTSIZE_ALIGN | LAST_FRAG); - } - rx_next = 0; -} - -static void purge_tx_ring(struct eth_device* dev) -{ - int i; - - PRINTF("Purging tx_ring.\n"); - - tx_next = 0; - - for (i = 0; i < NUM_TX_DESC; i++) - { - tx_ring[i].next = 0; - tx_ring[i].status = 0; - tx_ring[i].addr = 0; - tx_ring[i].length = 0; - } -} - -static void read_hw_addr(struct eth_device* dev, bd_t *bis) -{ - u8 hw_addr[ETH_ALEN]; - unsigned int eeprom[0x40]; - unsigned int checksum = 0; - int i, j, timer; - - /* Read the station address from the EEPROM. */ - - EL3WINDOW(dev, 0); - for (i = 0; i < 0x40; i++) - { - ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd); - /* Pause for at least 162 us. for the read to take place. */ - for (timer = 10; timer >= 0; timer--) - { - udelay(162); - if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0) - break; - } - eeprom[i] = ETH_INW(dev, Wn0EepromData); - } - - /* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */ - - for (i = 0; i < 0x21; i++) - checksum ^= eeprom[i]; - checksum = (checksum ^ (checksum >> 8)) & 0xff; - - if (checksum != 0xbb) - printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum); - - for (i = 0, j = 0; i < 3; i++) - { - hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff); - hw_addr[j++] = (u8)(eeprom[i+10] & 0xff); - } - - /* MAC Address is in window 2, write value from EEPROM to window 2 */ - - EL3WINDOW(dev, 2); - for (i = 0; i < 6; i++) - ETH_OUTB(dev, hw_addr[i], i); - - for (j = 0; j < ETH_ALEN; j+=2) - { - hw_addr[j] = (u8)(ETH_INW(dev, j) & 0xff); - hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff); - } - - for (i=0;ibi_enetaddr[i]) - { -/* printf("Warning: HW address don't match:\n"); */ -/* printf("Address in 3Com Window 2 is " */ -/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ -/* hw_addr[0], hw_addr[1], hw_addr[2], */ -/* hw_addr[3], hw_addr[4], hw_addr[5]); */ -/* printf("Address used by U-Boot is " */ -/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ -/* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */ -/* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */ -/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */ -/* goto Done; */ - char buffer[256]; - if (bis->bi_enetaddr[0] == 0 && bis->bi_enetaddr[1] == 0 && - bis->bi_enetaddr[2] == 0 && bis->bi_enetaddr[3] == 0 && - bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0) - { - - sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X", - hw_addr[0], hw_addr[1], hw_addr[2], - hw_addr[3], hw_addr[4], hw_addr[5]); - setenv("ethaddr", buffer); - } - } - } - - for(i=0; ienetaddr[i] = hw_addr[i]; - -Done: - return; -} diff --git a/board/MAI/AmigaOneG3SE/flash.c b/board/MAI/AmigaOneG3SE/flash.c deleted file mode 100644 index 409b955..0000000 --- a/board/MAI/AmigaOneG3SE/flash.c +++ /dev/null @@ -1,35 +0,0 @@ -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -unsigned long flash_init(void) -{ - int i; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) - { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = 0; - flash_info[i].size = 0; - } - - - return 1; -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - return 1; -} - -void flash_print_info(flash_info_t *info) -{ - printf("No flashrom installed\n"); -} - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - return 0; -} diff --git a/board/MAI/AmigaOneG3SE/flash_new.c b/board/MAI/AmigaOneG3SE/flash_new.c deleted file mode 100644 index d46bf46..0000000 --- a/board/MAI/AmigaOneG3SE/flash_new.c +++ /dev/null @@ -1,651 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "memio.h" - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -static ulong flash_get_size (ulong addr, flash_info_t *info); -static int flash_get_offsets (ulong base, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_reset (ulong addr); - -int flash_xd_nest; - -static void flash_to_xd(void) -{ - unsigned char x; - - flash_xd_nest ++; - - if (flash_xd_nest == 1) - { - DEBUGF("Flash on XD\n"); - x = pci_read_cfg_byte(0, 0, 0x74); - pci_write_cfg_byte(0, 0, 0x74, x|1); - } -} - -static void flash_to_mem(void) -{ - unsigned char x; - - flash_xd_nest --; - - if (flash_xd_nest == 0) - { - DEBUGF("Flash on memory bus\n"); - x = pci_read_cfg_byte(0, 0, 0x74); - pci_write_cfg_byte(0, 0, 0x74, x&0xFE); - } -} - -unsigned long flash_init_old(void) -{ - int i; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) - { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = 0; - flash_info[i].size = 0; - } - - - return 1; -} - -unsigned long flash_init (void) -{ - unsigned int i; - unsigned long flash_size = 0; - - flash_xd_nest = 0; - - flash_to_xd(); - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE && \ - CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - } else { - puts ("Warning: the BOOT Flash is not initialised !"); - } - - flash_to_mem(); - - return flash_size; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (ulong addr, flash_info_t *info) -{ - short i; - uchar value; - uchar *x = (uchar *)addr; - - flash_to_xd(); - - /* Write auto select command: read Manufacturer ID */ - x[0x0555] = 0xAA; - __asm volatile ("sync\n eieio"); - x[0x02AA] = 0x55; - __asm volatile ("sync\n eieio"); - x[0x0555] = 0x90; - __asm volatile ("sync\n eieio"); - - value = x[0]; - __asm volatile ("sync\n eieio"); - - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value); - - switch (value | (value << 16)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - flash_reset (addr); - return 0; - } - - value = x[1]; - __asm volatile ("sync\n eieio"); - - DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value); - - switch (value) { - case AMD_ID_F040B: - DEBUGF("Am29F040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - case AMD_ID_LV040B: - DEBUGF("Am29LV040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - case AMD_ID_LV400T: - DEBUGF("Am29LV400T\n"); - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - DEBUGF("Am29LV400B\n"); - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - DEBUGF("Am29LV800T\n"); - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - DEBUGF("Am29LV400B\n"); - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - DEBUGF("Am29LV160T\n"); - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - DEBUGF("Am29LV160B\n"); - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV320T: - DEBUGF("Am29LV320T\n"); - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 - /* Has the same ID as AMD_ID_LV320T, to be fixed */ - case AMD_ID_LV320B: - DEBUGF("Am29LV320B\n"); - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case AMD_ID_LV033C: - DEBUGF("Am29LV033C\n"); - info->flash_id += FLASH_AM033C; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16Mb */ - - case STM_ID_F040B: - DEBUGF("M29F040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - default: - info->flash_id = FLASH_UNKNOWN; - flash_reset (addr); - flash_to_mem(); - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - if (! flash_get_offsets (addr, info)) { - flash_reset (addr); - flash_to_mem(); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - value = in8(info->start[i] + 2); - iobarrier_rw(); - info->protect[i] = (value & 1) != 0; - } - - /* - * Reset bank to read mode - */ - flash_reset (addr); - - flash_to_mem(); - - return (info->size); -} - -static int flash_get_offsets (ulong base, flash_info_t *info) -{ - unsigned int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + i * info->size / - info->sector_count; - } - break; - default: - return 0; - } - - return 1; -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile ulong addr = info->start[0]; - int flag, prot, sect, l_sect; - ulong start, now, last; - - flash_to_xd(); - - if (s_first < 0 || s_first > s_last) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - flash_to_mem(); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - flash_to_mem(); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0x80); - iobarrier_rw(); - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = info->start[sect]; - out8(addr, 0x30); - iobarrier_rw(); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = info->start[l_sect]; - - DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT); - - while ((in8(addr) & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - flash_reset (info->start[0]); - flash_to_mem(); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - iobarrier_rw(); - } - -DONE: - /* reset to read mode */ - flash_reset (info->start[0]); - flash_to_mem(); - - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - flash_to_xd(); - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - flash_to_mem(); - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - flash_to_mem(); - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - flash_to_mem(); - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - - flash_to_mem(); - return (write_word(info, wp, data)); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile ulong addr = info->start[0]; - ulong start; - int i; - - flash_to_xd(); - - /* Check if Flash is (sufficiently) erased */ - if ((in32(dest) & data) != data) { - flash_to_mem(); - return (2); - } - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *)&data; - int flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0xA0); - iobarrier_rw(); - out8(dest+i, data_ch[i]); - iobarrier_rw(); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flash_reset (addr); - flash_to_mem(); - return (1); - } - iobarrier_rw(); - } - } - - flash_reset (addr); - flash_to_mem(); - return (0); -} - -/* - * Reset bank to read mode - */ -static void flash_reset (ulong addr) -{ - flash_to_xd(); - out8(addr, 0xF0); /* reset bank */ - iobarrier_rw(); - flash_to_mem(); -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_STM: printf ("SGS THOMSON "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size % 0x100000 == 0) { - printf (" Size: %ld MB in %d Sectors\n", - info->size / 0x100000, info->sector_count); - } else if (info->size % 0x400 == 0) { - printf (" Size: %ld KB in %d Sectors\n", - info->size / 0x400, info->sector_count); - } else { - printf (" Size: %ld B in %d Sectors\n", - info->size, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} diff --git a/board/MAI/AmigaOneG3SE/i8259.c b/board/MAI/AmigaOneG3SE/i8259.c deleted file mode 100644 index 34f489f..0000000 --- a/board/MAI/AmigaOneG3SE/i8259.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * (C) Copyright 2002 - * John W. Linville, linville@tuxdriver.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "i8259.h" - -#undef IRQ_DEBUG - -#ifdef IRQ_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -static inline unsigned char read_byte(volatile unsigned char* from) -{ - int x; - asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from)); - return (unsigned char)x; -} - -static inline void write_byte(volatile unsigned char *to, int x) -{ - asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x)); -} - -static inline unsigned long read_long_little(volatile unsigned long *from) -{ - unsigned long x; - asm volatile ("lwbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m"(*from)); - return (unsigned long)x; -} - -#ifdef out8 -#undef out8 -#endif - -#ifdef in8 -#undef in8 -#endif - -#define out8(addr, byte) write_byte(0xFE000000 | addr, byte) -#define in8(addr) read_byte(0xFE000000 | addr) - -/* - * This contains the irq mask for both 8259A irq controllers, - */ -static char cached_imr[2] = {0xff, 0xff}; - -#define cached_imr1 (cached_imr[0]) -#define cached_imr2 (cached_imr[1]) - -void i8259_init(void) -{ - char dummy; - PRINTF("Initializing Interrupt controller\n"); - /* init master interrupt controller */ - out8(0x20, 0x11); /* 0x19); /###* Start init sequence */ - out8(0x21, 0x00); /* Vector base */ - out8(0x21, 0x04); /* edge tiggered, Cascade (slave) on IRQ2 */ - out8(0x21, 0x11); /* was: 0x01); /###* Select 8086 mode */ - - /* init slave interrupt controller */ - out8(0xA0, 0x11); /* 0x19); /###* Start init sequence */ - out8(0xA1, 0x08); /* Vector base */ - out8(0xA1, 0x02); /* edge triggered, Cascade (slave) on IRQ2 */ - out8(0xA1, 0x11); /* was: 0x01); /###* Select 8086 mode */ - - /* always read ISR */ - out8(0x20, 0x0B); - dummy = in8(ISR_1); - out8(0xA0, 0x0B); - dummy = in8(ISR_2); - -/* out8(0x43, 0x30); */ -/* out8(0x40, 0); */ -/* out8(0x40, 0); */ -/* out8(0x43, 0x70); */ -/* out8(0x41, 0); */ -/* out8(0x41, 0); */ -/* out8(0x43, 0xb0); */ -/* out8(0x42, 0); */ -/* out8(0x42, 0); */ - - /* Mask all interrupts */ - out8(IMR_2, cached_imr2); - out8(IMR_1, cached_imr1); - - i8259_unmask_irq(2); -#if 0 - { - int i; - for (i=0; i<16; i++) - { - i8259_unmask_irq(i); - } - } -#endif -} - -static volatile char *pci_intack = (void *)0xFEF00000; - -int i8259_irq(void) -{ - int irq; - - irq = read_long_little(pci_intack) & 0xff; - if (irq==7) { - /* - * This may be a spurious interrupt. - * - * Read the interrupt status register (ISR). If the most - * significant bit is not set then there is no valid - * interrupt. - */ - if(~in8(0x20)&0x80) { - irq = -1; - } - } - - return irq; -} -int i8259_get_irq(struct pt_regs *regs) -{ - unsigned char irq; - - /* - * Perform an interrupt acknowledge cycle on controller 1 - */ - out8(OCW3_1, 0x0C); /* prepare for poll */ - irq = in8(IPL_1) & 7; - if (irq == 2) { - /* - * Interrupt is cascaded so perform interrupt - * acknowledge on controller 2 - */ - out8(OCW3_2, 0x0C); /* prepare for poll */ - irq = (in8(IPL_2) & 7) + 8; - if (irq == 15) { - /* - * This may be a spurious interrupt - * - * Read the interrupt status register. If the most - * significant bit is not set then there is no valid - * interrupt - */ - out8(OCW3_2, 0x0b); - if (~(in8(ISR_2) & 0x80)) { - return -1; - } - } - } else if (irq == 7) { - /* - * This may be a spurious interrupt - * - * Read the interrupt status register. If the most - * significant bit is not set then there is no valid - * interrupt - */ - out8(OCW3_1, 0x0b); - if (~(in8(ISR_1) & 0x80)) { - return -1; - } - } - return irq; -} - -/* - * Careful! The 8259A is a fragile beast, it pretty - * much _has_ to be done exactly like this (mask it - * first, _then_ send the EOI, and the order of EOI - * to the two 8259s is important! - */ -void i8259_mask_and_ack(int irq) -{ - if (irq > 7) { - cached_imr2 |= (1 << (irq - 8)); - in8(IMR_2); /* DUMMY */ - out8(IMR_2, cached_imr2); - out8(OCW2_2, 0x20); /* Non-specific EOI */ - out8(OCW2_1, 0x20); /* Non-specific EOI to cascade */ - } else { - cached_imr1 |= (1 << irq); - in8(IMR_1); /* DUMMY */ - out8(IMR_1, cached_imr1); - out8(OCW2_1, 0x20); /* Non-specific EOI */ - } -} - -void i8259_mask_irq(int irq) -{ - if (irq & 8) { - cached_imr2 |= (1 << (irq & 7)); - out8(IMR_2, cached_imr2); - } else { - cached_imr1 |= (1 << irq); - out8(IMR_1, cached_imr1); - } -} - -void i8259_unmask_irq(int irq) -{ - if (irq & 8) { - cached_imr2 &= ~(1 << (irq & 7)); - out8(IMR_2, cached_imr2); - } else { - cached_imr1 &= ~(1 << irq); - out8(IMR_1, cached_imr1); - } -} diff --git a/board/MAI/AmigaOneG3SE/i8259.h b/board/MAI/AmigaOneG3SE/i8259.h deleted file mode 100644 index 05c4052..0000000 --- a/board/MAI/AmigaOneG3SE/i8259.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002 - * John W. Linville, linville@tuxdriver.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define ICW1_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1 -#define ICW1_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1 -#define ICW2_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2 -#define ICW2_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2 -#define ICW3_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3 -#define ICW3_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3 -#define ICW4_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4 -#define ICW4_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4 -#define OCW1_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1 -#define OCW1_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1 -#define OCW2_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2 -#define OCW2_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2 -#define OCW3_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3 -#define OCW3_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3 - -#define IMR_1 OCW1_1 -#define IMR_2 OCW1_2 - -#define ISR_1 ICW1_1 -#define ISR_2 ICW1_2 - -#define IPL_1 ICW1_1 -#define IPL_2 ICW1_2 - -extern void i8259_init(void); - -extern int i8259_get_irq(struct pt_regs *regs); - -extern void i8259_mask_and_ack(int irq); - -extern void i8259_mask_irq(int irq); - -extern void i8259_unmask_irq(int irq); diff --git a/board/MAI/AmigaOneG3SE/interrupts.c b/board/MAI/AmigaOneG3SE/interrupts.c deleted file mode 100644 index 5b314a8..0000000 --- a/board/MAI/AmigaOneG3SE/interrupts.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * (C) Copyright 2002 - * John W. Linville - * - * Copied and modified from original code by Josh Huber. Original - * copyright notice preserved below. - * - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * interrupts.c - just enough support for the decrementer/timer - */ - -#include -#include -#include -#include "i8259.h" - -#undef DEBUG -#ifdef DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif -#define NR_IRQS 16 - -void irq_alloc_init(void); -long irq_alloc(long wanted); - -/****************************************************************************/ - -unsigned decrementer_count; /* count value for 1e6/HZ microseconds */ - -struct irq_action { - interrupt_handler_t *handler; - void *arg; - ulong count; -}; - -static struct irq_action irq_handlers[NR_IRQS]; - -/****************************************************************************/ - -static __inline__ unsigned long -get_msr(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void -set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -static __inline__ unsigned long -get_dec(void) -{ - unsigned long val; - - asm volatile("mfdec %0" : "=r" (val) :); - return val; -} - - -static __inline__ void -set_dec(unsigned long val) -{ - asm volatile("mtdec %0" : : "r" (val)); -} - - -void -enable_interrupts(void) -{ - set_msr (get_msr() | MSR_EE); -} - -/* returns flag if MSR_EE was set before */ -int -disable_interrupts(void) -{ - ulong msr; - - msr = get_msr(); - set_msr (msr & ~MSR_EE); - return ((msr & MSR_EE) != 0); -} - -/****************************************************************************/ - -int interrupt_init (void) -{ - extern void new_reset(void); - extern void new_reset_end(void); -#ifdef DEBUG - puts("interrupt_init: setting decrementer_count\n"); -#endif - decrementer_count = get_tbclk() / CFG_HZ; - -#ifdef DEBUG - puts("interrupt_init: setting actual decremter\n"); -#endif - set_dec (get_tbclk() / CFG_HZ); - -#ifdef DEBUG - puts("interrupt_init: clearing external interrupt table\n"); -#endif - /* clear external interrupt table here */ - memset(irq_handlers, 0, sizeof(irq_handlers)); - -#ifdef DEBUG - puts("interrupt_init: initializing interrupt controller\n"); -#endif - i8259_init(); - -#ifdef DEBUG - puts("Copying reset trampoline\n"); -#endif - /* WARNING: Assmues that the first megabyte is CACHEINHIBIT! */ - memcpy((void *)0x100, new_reset, new_reset_end - new_reset); - -#ifdef DEBUG - PRINTF("interrupt_init: enabling interrupts (msr = %08x)\n", - get_msr()); -#endif - set_msr (get_msr() | MSR_EE); - -#ifdef DEBUG - PRINTF("interrupt_init: done. (msr = %08x)\n", get_msr()); -#endif - -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void -external_interrupt(struct pt_regs *regs) -{ - extern int i8259_irq(void); - - int irq, unmask = 1; - - irq = i8259_irq(); /*i8259_get_irq(regs); */ -/* printf("irq = %d, handler at %p ack=%d\n", irq, irq_handlers[irq].handler, *(volatile unsigned char *)0xFEF00000); */ - i8259_mask_and_ack(irq); - - if (irq_handlers[irq].handler != NULL) - (*irq_handlers[irq].handler)(irq_handlers[irq].arg); - else { - PRINTF ("\nBogus External Interrupt IRQ %d\n", irq); - /* - * turn off the bogus interrupt, otherwise it - * might repeat forever - */ - unmask = 0; - } - - if (unmask) i8259_unmask_irq(irq); -} - -volatile ulong timestamp = 0; - -/* - * timer_interrupt - gets called when the decrementer overflows, - * with interrupts disabled. - * Trivial implementation - no need to be really accurate. - */ -void -timer_interrupt(struct pt_regs *regs) -{ - set_dec(decrementer_count); - timestamp++; -} - -/****************************************************************************/ - -void -reset_timer(void) -{ - timestamp = 0; -} - -ulong -get_timer(ulong base) -{ - return (timestamp - base); -} - -void -set_timer(ulong t) -{ - timestamp = t; -} - -/****************************************************************************/ - -/* - * Install and free a interrupt handler. - */ - -void -irq_install_handler(int irq, interrupt_handler_t *handler, void *arg) -{ - if (irq < 0 || irq >= NR_IRQS) { - PRINTF("irq_install_handler: bad irq number %d\n", irq); - return; - } - - if (irq_handlers[irq].handler != NULL) - PRINTF("irq_install_handler: 0x%08lx replacing 0x%08lx\n", - (ulong)handler, (ulong)irq_handlers[irq].handler); - - irq_handlers[irq].handler = handler; - irq_handlers[irq].arg = arg; - - i8259_unmask_irq(irq); -} - -void -irq_free_handler(int irq) -{ - if (irq < 0 || irq >= NR_IRQS) { - PRINTF("irq_free_handler: bad irq number %d\n", irq); - return; - } - - i8259_mask_irq(irq); - - irq_handlers[irq].handler = NULL; - irq_handlers[irq].arg = NULL; -} - -/****************************************************************************/ - -void -do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - puts("IRQ related functions are unimplemented currently.\n"); -} diff --git a/board/MAI/AmigaOneG3SE/macros.h b/board/MAI/AmigaOneG3SE/macros.h deleted file mode 100644 index 6020d7e..0000000 --- a/board/MAI/AmigaOneG3SE/macros.h +++ /dev/null @@ -1,84 +0,0 @@ - -#ifndef _MACROS_H -#define _MACROS_H - - /* - ** Load a long integer into a register - */ - .macro liw reg, value - lis \reg, \value@h - ori \reg, \reg, \value@l - .endm - - - /* - ** Generate config_addr request - ** This macro expects the values in registers: - ** r3 - bus - ** r4 - devfn - ** r5 - offset - */ - .macro config_addr - rlwinm r9, r5, 24, 0, 6 - rlwinm r8, r4, 16, 0, 31 - rlwinm r7, r3, 8, 0, 31 - or r9, r8, r9 - or r9, r7, r9 - ori r9, r9, 0x80 - liw r10, 0xfec00cf8 - stw r9, 0(r10) - eieio - sync - .endm - - - /* - ** Generate config_data address - */ - .macro config_data mask - andi. r9, r5, \mask - addi r9, r9, 0xcfc - oris r9, r9, 0xfee0 - .endm - - - /* - ** Write a byte value to an output port - */ - .macro outb port, value - lis r2, 0xfe00 - li r0, \value - stb r0, \port(r2) - .endm - - - /* - ** Write a register byte value to an output port - */ - .macro outbr port, value - lis r2, 0xfe00 - stb \value, \port(r2) - .endm - - - /* - ** Read a byte value from a port into a specified register - */ - .macro inb reg, port - lis r2, 0xfe00 - lbz \reg, \port(r2) - .endm - - - /* - ** Write a byte to the SuperIO config area - */ - .macro siowb offset, value - li r3, 0 - li r4, (7<<3) - li r5, \offset - li r6, \value - bl pci_write_cfg_byte - .endm - -#endif diff --git a/board/MAI/AmigaOneG3SE/memio.S b/board/MAI/AmigaOneG3SE/memio.S deleted file mode 100644 index 980d343..0000000 --- a/board/MAI/AmigaOneG3SE/memio.S +++ /dev/null @@ -1,67 +0,0 @@ -#include "macros.h" - - - .globl pci_read_cfg_byte - -pci_read_cfg_byte: - config_addr - config_data 3 - eieio - sync - lbz r3, 0(r9) - blr - - - .globl pci_write_cfg_byte - -pci_write_cfg_byte: - config_addr - config_data 3 - stb r6, 0(r9) - eieio - sync - blr - - - .globl pci_read_cfg_word - -pci_read_cfg_word: - config_addr - config_data 2 - lhbrx r3, 0, r9 - eieio - sync - blr - - - .globl pci_write_cfg_word - -pci_write_cfg_word: - config_addr - config_data 2 - sthbrx r6, 0, r9 - eieio - sync - blr - - - .globl pci_read_cfg_long - -pci_read_cfg_long: - config_addr - config_data 0 - lwbrx r3, 0, r9 - eieio - sync - blr - - - .globl pci_write_cfg_long - -pci_write_cfg_long: - config_addr - config_data 0 - stwbrx r6, 0, r9 - eieio - sync - blr diff --git a/board/MAI/AmigaOneG3SE/memio.h b/board/MAI/AmigaOneG3SE/memio.h deleted file mode 100644 index f5ce303..0000000 --- a/board/MAI/AmigaOneG3SE/memio.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Memory mapped IO - * - * (C) Copyright 2002 - * Hyperion Entertainment, ThomasF@hyperion-entertainment.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * You may also use this under a BSD license. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - */ - -#ifndef _MEMIO_H -#define _MEMIO_H - -#include "short_types.h" - -#define IOBASE 0xFE000000 - -#define in_byte(from) read_byte( (uint8 *)(IOBASE | (from))) -#define in_word(from) read_word_little((uint16 *)(IOBASE | (from))) -#define in_long(from) read_long_little((uint32 *)(IOBASE | (from))) -#define out_byte(to, val) write_byte((uint8 *)(IOBASE | (to)), val) -#define out_word(to, val) write_word_little((uint16 *)(IOBASE | (to)), val) -#define out_long(to, val) write_long_little((uint32 *)(IOBASE | (to)), val) - - -static inline uint8 read_byte(volatile uint8 *from) -{ - int x; - asm volatile ("lbz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from)); - return (uint8)x; -} - - -static inline void write_byte(volatile uint8 *to, uint8 x) -{ - asm volatile ("stb %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x)); -} - -static inline uint16 read_word_little(volatile uint16 *from) -{ - int x; - asm volatile ("lhbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m" (*from)); - return (uint16)x; -} - -static inline uint16 read_word_big(volatile uint16 *from) -{ - int x; - asm volatile ("lhz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from)); - return (uint16)x; -} - -static inline void write_word_little(volatile uint16 *to, int x) -{ - asm volatile ("sthbrx %1,0,%2\n eieio\n sync" : "=m" (*to) : "r" (x), "r" (to)); -} - -static inline void write_word_big(volatile uint16 *to, int x) -{ - asm volatile ("sth %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x)); -} - -static inline uint32 read_long_little(volatile uint32 *from) -{ - unsigned long x; - asm volatile ("lwbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m"(*from)); - return (uint32)x; -} - -static inline uint32 read_long_big(volatile uint32 *from) -{ - unsigned long x; - asm volatile ("lwz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from)); - return (uint32)x; -} - -static inline void write_long_little(volatile uint32 *to, uint32 x) -{ - asm volatile ("stwbrx %1,0,%2\n eieio\n sync" : "=m" (*to) : "r" (x), "r" (to)); -} - -static inline void write_long_big(volatile uint32 *to, uint32 x) -{ - asm volatile ("stw %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x)); -} - -#define CONFIG_ADDR(bus, devfn, offset) \ - write_long_big((uint32 *)0xFEC00CF8, \ - ((offset & 0xFC)<<24) | (devfn << 16) \ - | (bus<<8) | 0x80); -#define CONFIG_DATA(offset,mask) ((void *)(0xFEE00CFC+(offset & mask))) - - -uint8 pci_read_cfg_byte(int32 bus, int32 devfn, int32 offset); -void pci_write_cfg_byte(int32 bus, int32 devfn, int32 offset, uint8 x); -uint16 pci_read_cfg_word(int32 bus, int32 devfn, int32 offset); -void pci_write_cfg_word(int32 bus, int32 devfn, int32 offset, uint16 x); -uint32 pci_read_cfg_long(int32 bus, int32 devfn, int32 offset); -void pci_write_cfg_long(int32 bus, int32 devfn, int32 offset, uint32 x); - - -#endif diff --git a/board/MAI/AmigaOneG3SE/memory_dump b/board/MAI/AmigaOneG3SE/memory_dump deleted file mode 100644 index 65e7936..0000000 --- a/board/MAI/AmigaOneG3SE/memory_dump +++ /dev/null @@ -1,30 +0,0 @@ -64 MB: -0x00: 80 08 04 0c 09 01 40 00 01 a0 60 00 80 08 00 01 -0x10: 8f 04 04 01 01 00 06 a0 60 00 00 14 10 14 2d 10 -0x20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00 -0x30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 f2 -0x40: 7f 61 00 00 00 00 00 00 46 04 00 ff ff ff ff ff -0x50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff -0x60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff -0x70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff 64 f4 - -512 MB: -0x00: 80 08 04 0d 0a 02 40 00 01 75 54 00 82 08 00 01 -0x10: 8f 04 04 01 01 00 0f 00 00 00 00 14 0f 14 2d 40 -0x20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 -0x30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 d2 -0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 fd - -256 MB: -0x00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 -0x10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2d 20 -0x20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 -0x30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 b0 -0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 f6 - diff --git a/board/MAI/AmigaOneG3SE/nvram.c b/board/MAI/AmigaOneG3SE/nvram.c deleted file mode 100644 index d37eec1..0000000 --- a/board/MAI/AmigaOneG3SE/nvram.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2002 - * Thomas Frieden, Hyperion Entertainment - * ThomasF@hyperion-entertainment.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "memio.h" - -void enable_nvram(void) -{ - pci_write_cfg_byte(0, 0, 0x56, 0x0b); -} - -void disable_nvram(void) -{ - pci_write_cfg_byte(0, 0, 0x56, 0x0); -} diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.c b/board/MAI/AmigaOneG3SE/ps2kbd.c deleted file mode 100644 index cf4f4d0..0000000 --- a/board/MAI/AmigaOneG3SE/ps2kbd.c +++ /dev/null @@ -1,690 +0,0 @@ -/* - * (C) Copyright 2002 - * John W. Linville, linville@tuxdriver.com - * - * Modified from code for support of MIP405 and PIP405 boards. Previous - * copyright follows. - * - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - * Source partly derived from: - * linux/drivers/char/pc_keyb.c - * - * - */ -#include -#include -#include -#include "ps2kbd.h" - - -unsigned char kbd_read_status(void); -unsigned char kbd_read_input(void); -void kbd_send_data(unsigned char data); -void i8259_mask_irq(unsigned int irq); -void i8259_unmask_irq(unsigned int irq); - -/* used only by send_data - set by keyboard_interrupt */ - - -#undef KBG_DEBUG - -#ifdef KBG_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -#define KBD_STAT_KOBF 0x01 -#define KBD_STAT_IBF 0x02 -#define KBD_STAT_SYS 0x04 -#define KBD_STAT_CD 0x08 -#define KBD_STAT_LOCK 0x10 -#define KBD_STAT_MOBF 0x20 -#define KBD_STAT_TI_OUT 0x40 -#define KBD_STAT_PARERR 0x80 - -#define KBD_INIT_TIMEOUT 2000 /* Timeout in ms for initializing the keyboard */ -#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */ -#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */ -/* - * Keyboard Controller Commands - */ - -#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ -#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ -#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ -#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ -#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ -#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ -#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ -#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ -#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ -#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ -#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if - initiated by the auxiliary device */ -#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ - -/* - * Keyboard Commands - */ - -#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ -#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ -#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ -#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */ -#define KBD_CMD_RESET 0xFF /* Reset */ - -/* - * Keyboard Replies - */ - -#define KBD_REPLY_POR 0xAA /* Power on reset */ -#define KBD_REPLY_ACK 0xFA /* Command ACK */ -#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ - -/* - * Status Register Bits - */ - -#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ -#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ -#define KBD_STAT_SELFTEST 0x04 /* Self test successful */ -#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ -#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ -#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ -#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ -#define KBD_STAT_PERR 0x80 /* Parity error */ - -#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF) - -/* - * Controller Mode Register Bits - */ - -#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ -#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ -#define KBD_MODE_SYS 0x04 /* The system flag (?) */ -#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ -#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ -#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ -#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ -#define KBD_MODE_RFU 0x80 - - -#define KDB_DATA_PORT 0x60 -#define KDB_COMMAND_PORT 0x64 - -#define LED_SCR 0x01 /* scroll lock led */ -#define LED_CAP 0x04 /* caps lock led */ -#define LED_NUM 0x02 /* num lock led */ - -#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ - - -static volatile char kbd_buffer[KBD_BUFFER_LEN]; -static volatile int in_pointer = 0; -static volatile int out_pointer = 0; - - -static unsigned char num_lock = 0; -static unsigned char caps_lock = 0; -static unsigned char scroll_lock = 0; -static unsigned char shift = 0; -static unsigned char ctrl = 0; -static unsigned char alt = 0; -static unsigned char e0 = 0; -static unsigned char leds = 0; - -#define DEVNAME "ps2kbd" - -/* Simple translation table for the keys */ - -static unsigned char kbd_plain_xlate[] = { - 0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */ - 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */ - 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ - 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ - '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ - '\r',0xff,0xff - }; - -static unsigned char kbd_shift_xlate[] = { - 0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */ - 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */ - 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */ - 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ - 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ - '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ - '\r',0xff,0xff - }; - -static unsigned char kbd_ctrl_xlate[] = { - 0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */ - 0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */ - 0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */ - 0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ - 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ - '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ - '\r',0xff,0xff - }; - -/****************************************************************** - * Init - ******************************************************************/ - -int isa_kbd_init(void) -{ - char* result; - result=kbd_initialize(); - if (result != NULL) - { - result = kbd_initialize(); - } - if(result==NULL) { - printf("AT Keyboard initialized\n"); - irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL); - return (1); - } - else { - printf("%s\n",result); - return (-1); - } -} - -#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE -extern int overwrite_console (void); -#else -int overwrite_console (void) -{ - return (0); -} -#endif - -int drv_isa_kbd_init (void) -{ - int error; - device_t kbddev ; - char *stdinname = getenv ("stdin"); - - if(isa_kbd_init()==-1) - return -1; - memset (&kbddev, 0, sizeof(kbddev)); - strcpy(kbddev.name, DEVNAME); - kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbddev.putc = NULL ; - kbddev.puts = NULL ; - kbddev.getc = kbd_getc ; - kbddev.tstc = kbd_testc ; - - error = device_register (&kbddev); - if(error==0) { - /* check if this is the standard input device */ - if(strcmp(stdinname,DEVNAME)==0) { - /* reassign the console */ - if(overwrite_console()) { - return 1; - } - error=console_assign(stdin,DEVNAME); - if(error==0) - return 1; - else - return error; - } - return 1; - } - return error; -} - -/****************************************************************** - * Queue handling - ******************************************************************/ -/* puts character in the queue and sets up the in and out pointer */ -void kbd_put_queue(char data) -{ - if((in_pointer+1)==KBD_BUFFER_LEN) { - if(out_pointer==0) { - return; /* buffer full */ - } else{ - in_pointer=0; - } - } else { - if((in_pointer+1)==out_pointer) - return; /* buffer full */ - in_pointer++; - } - kbd_buffer[in_pointer]=data; - return; -} - -/* test if a character is in the queue */ -int kbd_testc(void) -{ - if(in_pointer==out_pointer) - return(0); /* no data */ - else - return(1); -} -/* gets the character from the queue */ -int kbd_getc(void) -{ - char c; - - while(in_pointer==out_pointer); - if((out_pointer+1)==KBD_BUFFER_LEN) - out_pointer=0; - else - out_pointer++; - c=kbd_buffer[out_pointer]; - return (int)c; - -} - - -/* set LEDs */ - -void kbd_set_leds(void) -{ - if(caps_lock==0) - leds&=~LED_CAP; /* switch caps_lock off */ - else - leds|=LED_CAP; /* switch on LED */ - if(num_lock==0) - leds&=~LED_NUM; /* switch LED off */ - else - leds|=LED_NUM; /* switch on LED */ - if(scroll_lock==0) - leds&=~LED_SCR; /* switch LED off */ - else - leds|=LED_SCR; /* switch on LED */ - kbd_send_data(KBD_CMD_SET_LEDS); - kbd_send_data(leds); -} - - -void handle_keyboard_event(unsigned char scancode) -{ - unsigned char keycode; - - /* Convert scancode to keycode */ - PRINTF("scancode %x\n",scancode); - if(scancode==0xe0) { - e0=1; /* special charakters */ - return; - } - if(e0==1) { - e0=0; /* delete flag */ - if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */ - ((scancode&0x7F)==0x1D)|| /* the right alt key */ - ((scancode&0x7F)==0x35)|| /* the right '/' key */ - ((scancode&0x7F)==0x1C)|| /* the right enter key */ - ((scancode)==0x48)|| /* arrow up */ - ((scancode)==0x50)|| /* arrow down */ - ((scancode)==0x4b)|| /* arrow left */ - ((scancode)==0x4d))) /* arrow right */ - /* we swallow unknown e0 codes */ - return; - } - /* special cntrl keys */ - switch(scancode) - { - case 0x48: - kbd_put_queue(27); - kbd_put_queue(91); - kbd_put_queue('A'); - return; - case 0x50: - kbd_put_queue(27); - kbd_put_queue(91); - kbd_put_queue('B'); - return; - case 0x4b: - kbd_put_queue(27); - kbd_put_queue(91); - kbd_put_queue('D'); - return; - case 0x4D: - kbd_put_queue(27); - kbd_put_queue(91); - kbd_put_queue('C'); - return; - case 0x58: /* F12 key */ - if (ctrl == 1) - { - extern int console_changed; - setenv("stdin", DEVNAME); - setenv("stdout", "vga"); - console_changed = 1; - } - return; - case 0x2A: - case 0x36: /* shift pressed */ - shift=1; - return; /* do nothing else */ - case 0xAA: - case 0xB6: /* shift released */ - shift=0; - return; /* do nothing else */ - case 0x38: /* alt pressed */ - alt=1; - return; /* do nothing else */ - case 0xB8: /* alt released */ - alt=0; - return; /* do nothing else */ - case 0x1d: /* ctrl pressed */ - ctrl=1; - return; /* do nothing else */ - case 0x9d: /* ctrl released */ - ctrl=0; - return; /* do nothing else */ - case 0x46: /* scrollock pressed */ - scroll_lock=~scroll_lock; - kbd_set_leds(); - return; /* do nothing else */ - case 0x3A: /* capslock pressed */ - caps_lock=~caps_lock; - kbd_set_leds(); - return; - case 0x45: /* numlock pressed */ - num_lock=~num_lock; - kbd_set_leds(); - return; - case 0xC6: /* scroll lock released */ - case 0xC5: /* num lock released */ - case 0xBA: /* caps lock released */ - return; /* just swallow */ - } - if((scancode&0x80)==0x80) /* key released */ - return; - /* now, decide which table we need */ - if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */ - PRINTF("unkown scancode %X\n",scancode); - return; /* swallow it */ - } - /* setup plain code first */ - keycode=kbd_plain_xlate[scancode]; - if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */ - if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ - PRINTF("unkown caps-locked scancode %X\n",scancode); - return; /* swallow it */ - } - keycode=kbd_shift_xlate[scancode]; - if(keycode<'A') { /* we only want the alphas capital */ - keycode=kbd_plain_xlate[scancode]; - } - } - if(shift==1) { /* shift overwrites caps_lock */ - if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ - PRINTF("unkown shifted scancode %X\n",scancode); - return; /* swallow it */ - } - keycode=kbd_shift_xlate[scancode]; - } - if(ctrl==1) { /* ctrl overwrites caps_lock and shift */ - if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */ - PRINTF("unkown ctrl scancode %X\n",scancode); - return; /* swallow it */ - } - keycode=kbd_ctrl_xlate[scancode]; - } - /* check if valid keycode */ - if(keycode==0xff) { - PRINTF("unkown scancode %X\n",scancode); - return; /* swallow unknown codes */ - } - - kbd_put_queue(keycode); - PRINTF("%x\n",keycode); -} - -/* - * This reads the keyboard status port, and does the - * appropriate action. - * - */ -unsigned char handle_kbd_event(void) -{ - unsigned char status = kbd_read_status(); - unsigned int work = 10000; - - while ((--work > 0) && (status & KBD_STAT_OBF)) { - unsigned char scancode; - - scancode = kbd_read_input(); - - /* Error bytes must be ignored to make the - Synaptics touchpads compaq use work */ - /* Ignore error bytes */ - if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) - { - if (status & KBD_STAT_MOUSE_OBF) - ; /* not supported: handle_mouse_event(scancode); */ - else - handle_keyboard_event(scancode); - } - status = kbd_read_status(); - } - if (!work) - PRINTF("pc_keyb: controller jammed (0x%02X).\n", status); - return status; -} - - -/****************************************************************************** - * Lowlevel Part of keyboard section - */ -unsigned char kbd_read_status(void) -{ - return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT)); -} - -unsigned char kbd_read_input(void) -{ - return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT)); -} - -void kbd_write_command(unsigned char cmd) -{ - out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd); -} - -void kbd_write_output(unsigned char data) -{ - out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data); -} - -int kbd_read_data(void) -{ - int val; - unsigned char status; - - val=-1; - status = kbd_read_status(); - if (status & KBD_STAT_OBF) { - val = kbd_read_input(); - if (status & (KBD_STAT_GTO | KBD_STAT_PERR)) - val = -2; - } - return val; -} - -int kbd_wait_for_input(void) -{ - unsigned long timeout; - int val; - - timeout = KBD_TIMEOUT; - val=kbd_read_data(); - while(val < 0) - { - if(timeout--==0) - return -1; - udelay(1000); - val=kbd_read_data(); - } - return val; -} - - -int kb_wait(void) -{ - unsigned long timeout = KBC_TIMEOUT * 10; - - do { - unsigned char status = handle_kbd_event(); - if (!(status & KBD_STAT_IBF)) - return 0; /* ok */ - udelay(1000); - timeout--; - } while (timeout); - return 1; -} - -void kbd_write_command_w(int data) -{ - if(kb_wait()) - PRINTF("timeout in kbd_write_command_w\n"); - kbd_write_command(data); -} - -void kbd_write_output_w(int data) -{ - if(kb_wait()) - PRINTF("timeout in kbd_write_output_w\n"); - kbd_write_output(data); -} - -void kbd_send_data(unsigned char data) -{ - unsigned char status; - i8259_mask_irq(KBD_INTERRUPT); /* disable interrupt */ - kbd_write_output_w(data); - status = kbd_wait_for_input(); - if (status == KBD_REPLY_ACK) - i8259_unmask_irq(KBD_INTERRUPT); /* enable interrupt */ -} - - -char * kbd_initialize(void) -{ - int status; - - in_pointer = 0; /* delete in Buffer */ - out_pointer = 0; - /* - * Test the keyboard interface. - * This seems to be the only way to get it going. - * If the test is successful a x55 is placed in the input buffer. - */ - kbd_write_command_w(KBD_CCMD_SELF_TEST); - if (kbd_wait_for_input() != 0x55) - return "Kbd: failed self test"; - /* - * Perform a keyboard interface test. This causes the controller - * to test the keyboard clock and data lines. The results of the - * test are placed in the input buffer. - */ - kbd_write_command_w(KBD_CCMD_KBD_TEST); - if (kbd_wait_for_input() != 0x00) - return "Kbd: interface failed self test"; - /* - * Enable the keyboard by allowing the keyboard clock to run. - */ - kbd_write_command_w(KBD_CCMD_KBD_ENABLE); - status = kbd_wait_for_input(); - /* - * Reset keyboard. If the read times out - * then the assumption is that no keyboard is - * plugged into the machine. - * This defaults the keyboard to scan-code set 2. - * - * Set up to try again if the keyboard asks for RESEND. - */ - do { - kbd_write_output_w(KBD_CMD_RESET); - status = kbd_wait_for_input(); - if (status == KBD_REPLY_ACK) - break; - if (status != KBD_REPLY_RESEND) - { - PRINTF("status: %X\n",status); - return "Kbd: reset failed, no ACK"; - } - } while (1); - if (kbd_wait_for_input() != KBD_REPLY_POR) - return "Kbd: reset failed, no POR"; - - /* - * Set keyboard controller mode. During this, the keyboard should be - * in the disabled state. - * - * Set up to try again if the keyboard asks for RESEND. - */ - do { - kbd_write_output_w(KBD_CMD_DISABLE); - status = kbd_wait_for_input(); - if (status == KBD_REPLY_ACK) - break; - if (status != KBD_REPLY_RESEND) - return "Kbd: disable keyboard: no ACK"; - } while (1); - - kbd_write_command_w(KBD_CCMD_WRITE_MODE); - kbd_write_output_w(KBD_MODE_KBD_INT - | KBD_MODE_SYS - | KBD_MODE_DISABLE_MOUSE - | KBD_MODE_KCC); - - /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */ - kbd_write_command_w(KBD_CCMD_READ_MODE); - if (!(kbd_wait_for_input() & KBD_MODE_KCC)) { - /* - * If the controller does not support conversion, - * Set the keyboard to scan-code set 1. - */ - kbd_write_output_w(0xF0); - kbd_wait_for_input(); - kbd_write_output_w(0x01); - kbd_wait_for_input(); - } - kbd_write_output_w(KBD_CMD_ENABLE); - if (kbd_wait_for_input() != KBD_REPLY_ACK) - return "Kbd: enable keyboard: no ACK"; - - /* - * Finally, set the typematic rate to maximum. - */ - kbd_write_output_w(KBD_CMD_SET_RATE); - if (kbd_wait_for_input() != KBD_REPLY_ACK) - return "Kbd: Set rate: no ACK"; - kbd_write_output_w(0x00); - if (kbd_wait_for_input() != KBD_REPLY_ACK) - return "Kbd: Set rate: no ACK"; - return NULL; -} - -void kbd_interrupt(void) -{ - handle_kbd_event(); -} diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.h b/board/MAI/AmigaOneG3SE/ps2kbd.h deleted file mode 100644 index fc5c422..0000000 --- a/board/MAI/AmigaOneG3SE/ps2kbd.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2002 - * John W. Linville, linville@tuxdriver.com - * - * Modified from code for support of MIP405 and PIP405 boards. Previous - * copyright follows. - * - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _KBD_H_ -#define _KBD_H_ - -extern int kbd_testc(void); -extern int kbd_getc(void); -extern void kbd_interrupt(void); -extern char *kbd_initialize(void); - -unsigned char kbd_is_init(void); -#define KBD_INTERRUPT 1 -#endif diff --git a/board/MAI/AmigaOneG3SE/serial.c b/board/MAI/AmigaOneG3SE/serial.c deleted file mode 100644 index e83fb46..0000000 --- a/board/MAI/AmigaOneG3SE/serial.c +++ /dev/null @@ -1,247 +0,0 @@ -#include -#include -#include "short_types.h" -#include "memio.h" -#include "articiaS.h" - -#ifndef CFG_NS16550 -static uint32 ComPort1; - -uint16 SerialEcho = 1; - - -#define RECEIVER_HOLDING 0 -#define TRANSMITTER_HOLDING 0 -#define INTERRUPT_ENABLE 1 -#define INTERRUPT_STATUS 2 -#define FIFO_CONTROL 2 -#define LINE_CONTROL 3 -#define MODEM_CONTROL 4 -#define LINE_STATUS 5 -#define MODEM_STATUS 6 -#define SCRATCH_PAD 7 - -#define DIVISOR_LATCH_LSB 0 -#define DIVISOR_LATCH_MSB 1 -#define PRESCALER_DIVISION 5 - -#define COM_WRITE_BYTE(reg, byte) out_byte((ComPort1+reg), byte) -#define COM_READ_BYTE(reg) in_byte((ComPort1+reg)) - -static int serial_init_done = 0; - -void serial_init (void) -{ -#if 0 - uint32 clock_divisor = 115200 / baudrate; - uint8 cfg; - uint8 a; - uint16 devfn = 7 << 3; - - if (serial_init_done) - return; - - /* Enter configuration mode */ - cfg = pci_read_cfg_byte (0, devfn, 0x85); - pci_write_cfg_byte (0, devfn, 0x85, cfg | 0x02); - - /* Set serial port COM1 as 3F8 */ - out_byte (0x3F0, 0xE7); - out_byte (0x3f1, 0xfe); - - /* Set serial port COM2 as 2F8 */ - out_byte (0x3f0, 0xe8); - out_byte (0x3f1, 0xeb); - - /* Enable */ - out_byte (0x3f0, 0xe2); - a = in_byte (0x3f1); - a |= 0xc; - out_byte (0x3f0, 0xe2); - out_byte (0x3f1, a); - - /* Reset the configuration mode */ - pci_write_cfg_byte (0, devfn, 0x85, cfg); -#endif - - ComPort1 = 0x3F8; - - /* Disable interrupts */ - COM_WRITE_BYTE (INTERRUPT_ENABLE, 0x00); - - /* Set baud rate */ - /* COM_WRITE_BYTE(LINE_CONTROL, 0x83); */ - /* COM_WRITE_BYTE(DIVISOR_LATCH_LSB, (uint8)(clock_divisor & 0xFF)); */ - /* COM_WRITE_BYTE(DIVISOR_LATCH_MSB, (uint8)(clock_divisor >> 8)); */ - /* __asm("eieio"); */ - - /* Set 8-N-1 */ - COM_WRITE_BYTE (LINE_CONTROL, 0x03); - __asm ("eieio"); - - /* Disable FIFO */ - COM_WRITE_BYTE (MODEM_CONTROL, 0x03); - COM_WRITE_BYTE (FIFO_CONTROL, 0x07); - - __asm ("eieio"); - serial_init_done = 1; -} - -extern int console_changed; - -void serial_putc (const char sendme) -{ - if (sendme == '\n') { - while ((in_byte (0x3FD) & 0x40) == 0); - out_byte (0x3f8, 0x0D); - } - - while ((in_byte (0x3FD) & 0x40) == 0); - out_byte (0x3f8, sendme); -} - -int serial_getc (void) -{ -#if 0 - uint8 c; - - for (;;) { - uint8 x = in_byte (0x3FD); - - if (x & 0x01) - break; - - if (x & 0x0C) - out_byte (0x3fd, 0x0c); - } - - c = in_byte (0x3F8); - - return c; -#else - while ((in_byte (0x3FD) & 0x01) == 0) { - if (console_changed != 0) { - printf ("Console changed\n"); - console_changed = 0; - return 0; - } - } - return in_byte (0x3F8); -#endif -} - -int serial_tstc (void) -{ - return (in_byte (0x03FD) & 0x01) != 0; -} - -void serial_debug_putc (int c) -{ - serial_puts ("DBG"); - serial_putc (c); - serial_putc (0x0d); - serial_putc (0x0A); -} - -#else - -const NS16550_t Com0 = (NS16550_t) CFG_NS16550_COM1; -const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2; - -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - uint32 clock_divisor = 115200 / gd->baudrate; - - NS16550_init (Com0, clock_divisor); - /* NS16550_reinit(Com1, clock_divisor); */ - /* serial_puts("COM1: 3F8h initalized"); */ - - return (0); -} - -#if 0 -void serial_putc (const char c) -{ - NS16550_putc (Com0, c); - if (c == '\n') - NS16550_putc (Com0, 0x0D); -} - -int serial_getc (void) -{ - return (int) NS16550_getc (Com0); -} - -int serial_tstc (void) -{ - return NS16550_tstc (Com0); -} -#else -void serial_putc (const char sendme) -{ - if (sendme == '\n') { - while ((in_byte (0x3FD) & 0x40) == 0); - out_byte (0x3f8, 0x0D); - } - - while ((in_byte (0x3FD) & 0x40) == 0); - out_byte (0x3f8, sendme); -} - - -extern int console_changed; - -int serial_getc (void) -{ -#if 0 - uint8 c; - - for (;;) { - uint8 x = in_byte (0x3FD); - - if (x & 0x01) - break; - - if (x & 0x0C) - out_byte (0x3fd, 0x0c); - } - - c = in_byte (0x3F8); - - return c; -#else - while ((in_byte (0x3FD) & 0x01) == 0) { - if (console_changed != 0) { - console_changed = 0; - return 0; - } - } - - return in_byte (0x3F8); -#endif -} - -int serial_tstc (void) -{ - return (in_byte (0x03FD) & 0x01) != 0; -} -#endif - -#endif - -void serial_puts (const char *string) -{ - while (*string) - serial_putc (*string++); -} - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - uint32 clock_divisor = 115200 / gd->baudrate; - - NS16550_init (Com0, clock_divisor); -} diff --git a/board/MAI/AmigaOneG3SE/short_types.h b/board/MAI/AmigaOneG3SE/short_types.h deleted file mode 100644 index 1840d28..0000000 --- a/board/MAI/AmigaOneG3SE/short_types.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * short type names - * - * (C) Copyright 2002 - * Hyperion Entertainment, ThomasF@hyperion-entertainment.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SHORT_TYPES_H -#define _SHORT_TYPES_H - -typedef unsigned long uint32; -typedef long int32; -typedef unsigned short uint16; -typedef short int16; -typedef unsigned char uint8; -typedef signed char int8; - -#endif diff --git a/board/MAI/AmigaOneG3SE/smbus.c b/board/MAI/AmigaOneG3SE/smbus.c deleted file mode 100644 index de13977..0000000 --- a/board/MAI/AmigaOneG3SE/smbus.c +++ /dev/null @@ -1,206 +0,0 @@ -#include "memio.h" -#include "articiaS.h" - -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef TRUE -#define TRUE 1 -#endif - - -void sm_write_mode(void) -{ - out_byte(0xA539, 0x00); - out_byte(0xA53A, 0x03); -} - -void sm_read_mode(void) -{ - out_byte(0xA53A, 0x02); - out_byte(0xA539, 0x02); -} - -void sm_write_byte(uint8 writeme) -{ - int i; - int level; - - out_byte(0xA539, 0x00); - - level = 0; - - for (i=0; i<8; i++) - { - if ((writeme & 0x80) == (level<<7)) - { - /* Bit did not change, rewrite strobe */ - out_byte(0xA539, level | 0x02); - out_byte(0xA539, level); - } - else - { - /* Bit changed, set bit, then strobe */ - level = (writeme & 0x80) >> 7; - out_byte(0xA539, level); - out_byte(0xA539, level | 0x02); - out_byte(0xA539, level); - } - writeme <<= 1; - } - out_byte(0xA539, 0x00); -} - -uint8 sm_read_byte(void) -{ - uint8 retme, r; - int i; - - retme = 0; - for (i=0; i<8; i++) - { - retme <<= 1; - out_byte(0xA539, 0x00); - out_byte(0xA539, 0x02); - r = in_byte(0xA538) & 0x01; - retme |= r; - } - - return retme; -} - -int sm_get_ack(void) -{ - uint8 r; - r = in_byte(0xA538); - if ((r&0x01) == 0) return TRUE; - else return FALSE; -} - -void sm_write_ack(void) -{ - out_byte(0xA539, 0x00); - out_byte(0xA539, 0x02); - out_byte(0xA539, 0x00); -} - -void sm_write_nack(void) -{ - out_byte(0xA539, 0x01); - out_byte(0xA539, 0x03); - out_byte(0xA539, 0x01); -} - -void sm_send_start(void) -{ - out_byte(0xA539, 0x03); - out_byte(0xA539, 0x02); -} - -void sm_send_stop(void) -{ - out_byte(0xA539, 0x02); - out_byte(0xA539, 0x03); -} - -int sm_read_byte_from_device(uint8 addr, uint8 reg, uint8 *storage) -{ - /* S Addr Wr */ - sm_write_mode(); - sm_send_start(); - sm_write_byte((addr<<1)); - - /* [A] */ - sm_read_mode(); - if (sm_get_ack() == FALSE) return FALSE; - - /* Comm */ - sm_write_mode(); - sm_write_byte(reg); - - /* [A] */ - sm_read_mode(); - if (sm_get_ack() == FALSE) return FALSE; - - /* S Addr Rd */ - sm_write_mode(); - sm_send_start(); - sm_write_byte((addr<<1)|1); - - /* [A] */ - sm_read_mode(); - if (sm_get_ack() == FALSE) return FALSE; - - /* [Data] */ - *storage = sm_read_byte(); - - /* NA */ - sm_write_mode(); - sm_write_nack(); - sm_send_stop(); - - return TRUE; -} - -void sm_init(void) -{ - /* Switch to PMC mode */ - pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER)); - - /* Set GPIO Base */ - pci_write_cfg_long(0, 0, 0x40, 0xa500); - - /* Enable GPIO */ - pci_write_cfg_byte(0, 0, 0x44, 0x11); - - /* Set both GPIO 0 and 1 as output */ - out_byte(0xA53A, 0x03); -} - - -void sm_term(void) -{ - /* Switch to normal mode */ - pci_write_cfg_byte(0, 0, REG_GROUP, 0); -} - - -int sm_get_data(uint8 *DataArray, int dimm_socket) -{ - int j; - -#if 0 - /* Switch to PMC mode */ - pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER)); - - /* Set GPIO Base */ - pci_write_cfg_long(0, 0, 0x40, 0xa500); - - /* Enable GPIO */ - pci_write_cfg_byte(0, 0, 0x44, 0x11); - - /* Set both GPIO 0 and 1 as output */ - out_byte(0xA53A, 0x03); -#endif - - sm_init(); - /* Start reading the rom */ - - j = 0; - - do - { - if (sm_read_byte_from_device(dimm_socket, (uint8)j, DataArray) == FALSE) - { - sm_term(); - return FALSE; - } - - DataArray++; - j++; - } while (j < 128); - - sm_term(); - return TRUE; -} diff --git a/board/MAI/AmigaOneG3SE/smbus.h b/board/MAI/AmigaOneG3SE/smbus.h deleted file mode 100644 index beeb6a0..0000000 --- a/board/MAI/AmigaOneG3SE/smbus.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _SMBUS_H_ -#define _SMBUS_H_ - -#include "short_types.h" - -#define SM_DIMM0_ADDR 0x51 -#define SM_DIMM1_ADDR 0x52 - -void sm_write_mode(void); -void sm_read_mode(void); -void sm_write_byte(uint8 writeme); -uint8 sm_read_byte(void); -int sm_get_ack(void); -void sm_write_ack(void); -void sm_write_nack(void); -void sm_send_start(void); -void sm_send_stop(void); -int sm_read_byte_from_device(uint8 addr, uint8 reg, uint8 *storage); -int sm_get_data(uint8 *DataArray, int dimm_socket); -void sm_init(void); -void sm_term(void); -#endif diff --git a/board/MAI/AmigaOneG3SE/start.txt b/board/MAI/AmigaOneG3SE/start.txt deleted file mode 100644 index e421462..0000000 --- a/board/MAI/AmigaOneG3SE/start.txt +++ /dev/null @@ -1,198 +0,0 @@ - - /*------------------------------------------------------*/ - /* TERON Articia / SDRAM Init */ - /*------------------------------------------------------*/ - -* XD_CTL = 0x81000000 (0x74) - -* HBUS_ACC_CTL_0 &= 0xFFFFFDFF (0x5c) - /* host bus access ctl reg 2(5e) */ - /* set - CPU read from memory data one clock after data is latched */ - -* GLOBL_INFO_0 |= 0x00004000 (0x50) - /* global info register 2 (52), AGP/PCI bus 1 arbiter is addressed in Articia S */ - - PCI_1_SB_CONFIG_0 |= 0x00000400 (0x80d0) - /* PCI1 side band config reg 2 (d2), enable read acces while write buffer not empty */ - - MEM_RAS_CTL_0 |= 0x3f000000 (0xcc) - &= 0x3fffffff - /* RAS park control reg 0(cc), park access enable is set */ - - HOST_RDBUF_CTL |= 0x10000000 (0x70) - &= 0x10ffffff - /* host read buffer control reg, enable prefetch for CPU read from DRAM control */ - - HBUS_ACC_CTL_0 |= 0x0100001f (0x5c) - &= 0xf1ffffff - /* host bus access control register, enable CPU address bus pipe control */ - /* two outstanding requests, *** changed to 2 from 3 */ - /* enable line merge write control for CPU write to system memory, PCI 1 */ - /* and PCI 0 bus memory; enable page merge write control for write to */ - /* PCI bus 0 & bus 1 memory */ - - SRAM_CTL |= 0x00004000 (0xc8) - &= 0xffbff7ff - /* DRAM detail timing control register 1 (ca), bit 3 set to 0 */ - /* DRAM start access latency control - wait for one clock */ - /* ff9f changed to ffbf */ - - DIM0_TIM_CTL_0 = 0x737d737d (0xc9) - /* DRAM timing control for dimm0 & dimm1; set wait one clock */ - /* cycle for next data access */ - - DIM2_TIM_CTL_0 = 0x737d737d (0xca) - /* DRAM timing control for dimm2 & dimm3; set wait one clock */ - /* cycle for next data access */ - - DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB (0x90) - /* set dimm0 bank0 for 128 MB */ - - DIM0_BNK1_CTL_0 = BNK1_RAM_SIZ_128MB (0x94) - /* set dimm0 for bank1 */ - - DIM0_TIM_CTL_0 = 0xf3bf0000 (0xc9) - /* dimm0 timing control register; RAS - CAS latency - 4 clock */ - /* CAS access latency - 3 wait; pre-charge latency - 3 wait */ - /* pre-charge command period control - 5 clock; wait one clock */ - /* cycle for next data access; read to write access latency control */ - /* - 2 clock cycles */ - - DRAM_GBL_CTL_0 |= 0x00000100 (0xc0) - &= 0xffff01ff - /* memory global control register - support buffer sdram on bank 0 */ - - DRAM_ECC_CTL_0 |= 0x00260000 (0xc4) - &= 0xff26ffff - /* enable ECC; enable read, modify, write control */ - - DRAM_REF_CTL_0 = DRAM_REF_DATA (0xb8) - /* set DRAM refresh parameters *** changed to 00940100 */ - - nop - nop - nop - nop - nop - - DRAM_ECC_CTL_0 |= 0x20243280 (0xc4) - /* turn off ecc */ - /* for SDRAM bank 0 */ - - DRAM_ECC_CTL_0 |= 0x20243290 (0xc4) ? - /* for SDRAM bank 1 */ - - -/* Additional Stuff...*/ - - GLOBL_CTRL |= 0x20000b00 (0x54) - - PCI_0_SB_CONFIG |= 0x04100007 (0xd0) - /* PCI 0 Side band config reg*/ - - 0x8000083c |= 0x00080000 - /* Disable VGA decode on PCI Bus 1 */ - - -/*End Additional Stuff..*/ - - /*--------------------------------------------------------------*/ - /* TERON serial port initialization code */ - /*--------------------------------------------------------------*/ - - 0x84380080 |= 0x00030000 - /* enable super IO configuration VIA chip Register 85 */ - /* Enable super I/O config mode */ - - 0xfe0003f0 = 0xe2 - bl delay1 - - 0xfe0003f1 = 0x0f - bl delay1 - /* enable com1 & com2, parallel port disabled */ - - 0xfe0003f0 = 0xe7 - bl delay1 - /* let's make com1 base as 0x3f8 */ - - 0xfe0003f1 = 0xfe - bl delay1 - - 0xfe0003f0 = 0xe8 - bl delay1 - /* let's make com2 base as 0x2f8 */ - - 0xfe0003f1 = 0xbe - - 0x84380080 &= 0xfffdffff - /* closing super IO configuration VIA chip Register 85 */ - - -/* -------------------------------*/ - - 0xfe0003fb = 0x83 - bl delay1 - /*latch enable word length -8 bit */ /* set mslab bit */ - 0xfe0003f8 = 0x0c - bl delay1 - /* set baud rate lsb for 9600 baud */ - 0xfe0003f9 = 0x0 - bl delay1 - /* set baud rate msb for 9600 baud */ - 0xfe0003fb = 0x03 - bl delay1 - /* reset mslab */ - - /*--------------------------------------------------------------*/ - /* END TERON Serial Port Initialization Code */ - /*--------------------------------------------------------------*/ - - - /*--------------------------------------------------------------*/ - /* END TERON Articia / SDRAM Initialization code */ - /*--------------------------------------------------------------*/ - -Proposed from Documentation: - -write dmem 0xfec00cf8 0x50000080 -write dmem 0xfee00cfc 0xc0305411 - - Writes to index 0x50-0x53. - 0x50: Global Information Register 0 - 0xC0 = Little Endian CPU, Sequential order Burst - 0x51: Global Information Register 1 - Read only, 0x30 = Provides PowerPC and X86 support - 0x52: Global Information Register 2 - 0x05 = 64/128 bit CPU bus support - 0x53: Global Information Register 3 - 0x80 = PCI Bus 0 grant active time is 1 clock after REQ# deasserted - -write dmem 0xfec00cf8 0x5c000080 -write dmem 0xfee00cfc 0xb300011F - -write dmem 0xfec00cf8 0xc8000080 -write dmem 0xfee00cfc 0x0020f100 - -write dmem 0xfec00cf8 0x90000080 -write dmem 0xfee00cfc 0x007fe700 - -write dmem 0xfec00cf8 0x9400080 -write dmem 0xfee00cfc 0x007fe700 - -write dmem 0xfec00cf8 0xb0000080 -write dmem 0xfee00cfc 0x737d737d - -write dmem 0xfec00cf8 0xb4000080 -write dmem 0xfee00cfc 0x737d737d - -write dmem 0xfec00cf8 0xc0000080 -write dmem 0xfee00cfc 0x40005500 - -write dmem 0xfec00cf8 0xb8000080 -write dmem 0xfee00cfc 0x00940100 - -write dmem 0xfec00cf8 0xc4000080 -write dmem 0xfee00cfc 0x00003280 - -write dmem 0xfec00cf8 0xc4000080 -write dmem 0xfee00cfc 0x00003290 diff --git a/board/MAI/AmigaOneG3SE/todo.txt b/board/MAI/AmigaOneG3SE/todo.txt deleted file mode 100644 index df25e3d..0000000 --- a/board/MAI/AmigaOneG3SE/todo.txt +++ /dev/null @@ -1,3 +0,0 @@ -- Init interrupt controller -- init sdram -- init ide controller \ No newline at end of file diff --git a/board/MAI/AmigaOneG3SE/u-boot.lds b/board/MAI/AmigaOneG3SE/u-boot.lds deleted file mode 100644 index b36b3cb..0000000 --- a/board/MAI/AmigaOneG3SE/u-boot.lds +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * u-boot.lds - linker script for U-Boot on the AmigaOneG3SE Board. - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/74xx_7xx/start.o (.text) -/* store the environment in a seperate sector in the boot flash */ -/* . = env_offset; */ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = ALIGN(4) /*.*/ ; - PROVIDE (end = ALIGN(4) /*.*/); -} diff --git a/board/MAI/AmigaOneG3SE/usb_uhci.c b/board/MAI/AmigaOneG3SE/usb_uhci.c deleted file mode 100644 index 14e8043..0000000 --- a/board/MAI/AmigaOneG3SE/usb_uhci.c +++ /dev/null @@ -1,1178 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Note: Part of this code has been derived from linux - * - */ - -/********************************************************************** - * How it works: - * ------------- - * The framelist / Transfer descriptor / Queue Heads are similar like - * in the linux usb_uhci.c. - * - * During initialization, the following skeleton is allocated in init_skel: - * - * framespecific | common chain - * - * framelist[] - * [ 0 ]-----> TD ---------\ - * [ 1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL - * ... TD ---------/ - * [1023]-----> TD --------/ - * - * ^^ ^^ ^^ ^^ ^^ - * 7 TDs for 1 TD for Start of Start of End Chain - * INT (2-128ms) 1ms-INT CTRL Chain BULK Chain - * - * - * Since this is a bootloader, the isochronous transfer descriptor have been removed. - * - * Interrupt Transfers. - * -------------------- - * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They - * will be inserted after the appropriate (depending the interval setting) skeleton TD. - * If an interrupt has been detected the dev->irqhandler is called. The status and number - * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the - * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned, - * the interrupt TD will be reactivated. - * - * Control Transfers - * ----------------- - * Control Transfers are issued by filling the tmp_td with the appropriate data and connect - * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued, - * the programm has to wait for completion. This does not allows asynchronous data transfer. - * - * Bulk Transfers - * -------------- - * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect - * them to the qh_bulk queue header. Before other control/bulk transfers can be issued, - * the programm has to wait for completion. This does not allows asynchronous data transfer. - * - * - */ - -#include -#include - -#ifdef CONFIG_USB_UHCI - -#include -#include "usb_uhci.h" - -#define USB_MAX_TEMP_TD 128 /* number of temporary TDs for bulk and control transfers */ -#define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */ - - -/*#define USB_UHCI_DEBUG */ - -#ifdef USB_UHCI_DEBUG -#define USB_UHCI_PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define USB_UHCI_PRINTF(fmt,args...) -#endif - - -static int irqvec = -1; /* irq vector, if -1 uhci is stopped / reseted */ -unsigned int usb_base_addr; /* base address */ - -static uhci_td_t td_int[8]; /* Interrupt Transfer descriptors */ -static uhci_qh_t qh_cntrl; /* control Queue Head */ -static uhci_qh_t qh_bulk; /* bulk Queue Head */ -static uhci_qh_t qh_end; /* end Queue Head */ -static uhci_td_t td_last; /* last TD (linked with end chain) */ - -/* temporary tds */ -static uhci_td_t tmp_td[USB_MAX_TEMP_TD]; /* temporary bulk/control td's */ -static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD]; /* temporary interrupt td's */ - -static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */ - -static struct virt_root_hub rh; /* struct for root hub */ - -/********************************************************************** - * some forward decleration - */ -int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len,struct devrequest *setup); - -/* fill a td with the approproiate data. Link, status, info and buffer - * are used by the USB controller itselfes, dev is used to identify the - * "connected" device - */ -void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status, - unsigned long info, unsigned long buffer, unsigned long dev) -{ - td->link=swap_32(link); - td->status=swap_32(status); - td->info=swap_32(info); - td->buffer=swap_32(buffer); - td->dev_ptr=dev; -} - -/* fill a qh with the approproiate data. Head and element are used by the USB controller - * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh. - * Please note, that after completion of the td chain, the entry element is removed / - * marked invalid by the USB controller. - */ -void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element) -{ - qh->head=swap_32(head); - qh->element=swap_32(element); - qh->dev_ptr=0L; -} - -/* get the status of a td->status - */ -unsigned long usb_uhci_td_stat(unsigned long status) -{ - unsigned long result=0; - result |= (status & TD_CTRL_NAK) ? USB_ST_NAK_REC : 0; - result |= (status & TD_CTRL_STALLED) ? USB_ST_STALLED : 0; - result |= (status & TD_CTRL_DBUFERR) ? USB_ST_BUF_ERR : 0; - result |= (status & TD_CTRL_BABBLE) ? USB_ST_BABBLE_DET : 0; - result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0; - result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0; - result |= (status & TD_CTRL_ACTIVE) ? USB_ST_NOT_PROC : 0; - return result; -} - -/* get the status and the transfered len of a td chain. - * called from the completion handler - */ -int usb_get_td_status(uhci_td_t *td,struct usb_device *dev) -{ - unsigned long temp,info; - unsigned long stat; - uhci_td_t *mytd=td; - - if(dev->devnum==rh.devnum) - return 0; - dev->act_len=0; - stat=0; - do { - temp=swap_32((unsigned long)mytd->status); - stat=usb_uhci_td_stat(temp); - info=swap_32((unsigned long)mytd->info); - if(((info & 0xff)!= USB_PID_SETUP) && - (((info >> 21) & 0x7ff)!= 0x7ff) && - (temp & 0x7FF)!=0x7ff) - { /* if not setup and not null data pack */ - dev->act_len+=(temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */ - } - if(stat) { /* status no ok */ - dev->status=stat; - return -1; - } - temp=swap_32((unsigned long)mytd->link); - mytd=(uhci_td_t *)(temp & 0xfffffff0); - }while((temp & 0x1)==0); /* process all TDs */ - dev->status=stat; - return 0; /* Ok */ -} - - -/*------------------------------------------------------------------- - * LOW LEVEL STUFF - * assembles QHs und TDs for control, bulk and iso - *-------------------------------------------------------------------*/ - -/* Submits a control message. That is a Setup, Data and Status transfer. - * Routine does not wait for completion. - */ -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len,struct devrequest *setup) -{ - unsigned long destination, status; - int maxsze = usb_maxpacket(dev, pipe); - unsigned long dataptr; - int len; - int pktsze; - int i=0; - - if (!maxsze) { - USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe); - return -1; - } - if(((pipe>>8)&0x7f)==rh.devnum) { - /* this is the root hub -> redirect it */ - return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup); - } - USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze); - /* The "pipe" thing contains the destination in bits 8--18 */ - destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */ - /* 3 errors */ - status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); - /* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */ - /* Build the TD for the control request, try forever, 8 bytes of data */ - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev); -#if 0 - { - char *sp=(char *)setup; - printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe, - sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]); - } -#endif - dataptr = (unsigned long)buffer; - len=transfer_len; - - /* If direction is "send", change the frame from SETUP (0x2D) - to OUT (0xE1). Else change it from SETUP to IN (0x69). */ - destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN); - while (len > 0) { - /* data stage */ - pktsze = len; - i++; - if (pktsze > maxsze) - pktsze = maxsze; - destination ^= 1 << TD_TOKEN_TOGGLE; /* toggle DATA0/1 */ - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */ - tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); - - dataptr += pktsze; - len -= pktsze; - } - - /* Build the final TD for control status */ - /* It's only IN if the pipe is out AND we aren't expecting data */ - - destination &= ~UHCI_PID; - if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0)) - destination |= USB_PID_IN; - else - destination |= USB_PID_OUT; - destination |= 1 << TD_TOKEN_TOGGLE; /* End in Data1 */ - i++; - status &=~TD_CTRL_SPD; - /* no limit on errors on final packet , 0 bytes of data */ - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev); - tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); /* queue status td */ - /* usb_show_td(i+1);*/ - USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i); - /* first mark the control QH element terminated */ - qh_cntrl.element=0xffffffffL; - /* set qh active */ - qh_cntrl.dev_ptr=(unsigned long)dev; - /* fill in tmp_td_chain */ - qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]); - return 0; -} - -/*------------------------------------------------------------------- - * Prepare TDs for bulk transfers. - */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len) -{ - unsigned long destination, status,info; - unsigned long dataptr; - int maxsze = usb_maxpacket(dev, pipe); - int len; - int i=0; - - if(transfer_len < 0) { - printf("Negative transfer length in submit_bulk\n"); - return -1; - } - if (!maxsze) - return -1; - /* The "pipe" thing contains the destination in bits 8--18. */ - destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe); - /* 3 errors */ - status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); - /* ((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */ - /* Build the TDs for the bulk request */ - len = transfer_len; - dataptr = (unsigned long)buffer; - do { - int pktsze = len; - if (pktsze > maxsze) - pktsze = maxsze; - /* pktsze bytes of data */ - info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) | - (usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE); - - if((len-pktsze)==0) - status |= TD_CTRL_IOC; /* last one generates INT */ - - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */ - if(i>0) - tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); - i++; - dataptr += pktsze; - len -= pktsze; - usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)); - } while (len > 0); - /* first mark the bulk QH element terminated */ - qh_bulk.element=0xffffffffL; - /* set qh active */ - qh_bulk.dev_ptr=(unsigned long)dev; - /* fill in tmp_td_chain */ - qh_bulk.element=swap_32((unsigned long)&tmp_td[0]); - return 0; -} - - -/* search a free interrupt td - */ -uhci_td_t *uhci_alloc_int_td(void) -{ - int i; - for(i=0;i free TD */ - return &tmp_int_td[i]; - } - return NULL; -} - -#if 0 -void uhci_show_temp_int_td(void) -{ - int i; - for(i=0;i free TD */ - printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr); - } - printf("all others temp_tds are free\n"); -} -#endif -/*------------------------------------------------------------------- - * submits USB interrupt (ie. polling ;-) - */ -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval) -{ - int nint, n; - unsigned long status, destination; - unsigned long info,tmp; - uhci_td_t *mytd; - if (interval < 0 || interval >= 256) - return -1; - - if (interval == 0) - nint = 0; - else { - for (nint = 0, n = 1; nint <= 8; nint++, n += n) /* round interval down to 2^n */ - { - if(interval < n) { - interval = n / 2; - break; - } - } - nint--; - } - - USB_UHCI_PRINTF("Rounded interval to %i, chain %i\n", interval, nint); - mytd=uhci_alloc_int_td(); - if(mytd==NULL) { - printf("No free INT TDs found\n"); - return -1; - } - status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27); -/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27); -*/ - - destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21); - - info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE); - tmp = swap_32(td_int[nint].link); - usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev); - /* Link it */ - tmp = swap_32((unsigned long)mytd); - td_int[nint].link=tmp; - - usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)); - - return 0; -} - -/********************************************************************** - * Low Level functions - */ - - -void reset_hc(void) -{ - - /* Global reset for 100ms */ - out16r( usb_base_addr + USBPORTSC1,0x0204); - out16r( usb_base_addr + USBPORTSC2,0x0204); - out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS); - /* Turn off all interrupts */ - out16r(usb_base_addr + USBINTR,0); - wait_ms(50); - out16r( usb_base_addr + USBCMD,0); - wait_ms(10); -} - -void start_hc(void) -{ - int timeout = 1000; - - while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) { - if (!--timeout) { - printf("USBCMD_HCRESET timed out!\n"); - break; - } - } - /* Turn on all interrupts */ - out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP); - /* Start at frame 0 */ - out16r(usb_base_addr + USBFRNUM,0); - /* set Framebuffer base address */ - out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist); - /* Run and mark it configured with a 64-byte max packet */ - out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP); -} - -/* Initialize the skeleton - */ -void usb_init_skel(void) -{ - unsigned long temp; - int n; - - for(n=0;nstatus & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ - qh_cntrl.dev_ptr=0; - } - } - /* now process the bulk */ - if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */ - { - dev=(struct usb_device *)qh_bulk.dev_ptr; - usb_get_td_status(&tmp_td[0],dev); /* update status */ - if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ - qh_bulk.dev_ptr=0; - } - } -} - -/* check the interrupt chain, ubdate the status of the appropriate device, - * call the appropriate irqhandler and reactivate the TD if the irqhandler - * returns with 1 - */ -void usb_check_int_chain(void) -{ - int i,res; - unsigned long link,status; - struct usb_device *dev; - uhci_td_t *td,*prevtd; - - for(i=0;i<8;i++) { - prevtd=&td_int[i]; /* the first previous td is the skeleton td */ - link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */ - td=(uhci_td_t *)link; /* assign it */ - /* all interrupt TDs are finally linked to the td_int[0]. - * so we process all until we find the td_int[0]. - * if int0 chain points to a QH, we're also done - */ - while(((i>0) && (link != (unsigned long)&td_int[0])) || - ((i==0) && !(swap_32(td->link) & UHCI_PTR_QH))) - { - /* check if a device is assigned with this td */ - status=swap_32(td->status); - if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) { - /* td is not active and a device is assigned -> call irqhandler */ - dev=(struct usb_device *)td->dev_ptr; - dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */ - dev->irq_status=usb_uhci_td_stat(status); /* get status */ - res=dev->irq_handle(dev); /* call irqhandler */ - if(res==1) { - /* reactivate */ - status|=TD_CTRL_ACTIVE; - td->status=swap_32(status); - prevtd=td; /* previous td = this td */ - } - else { - prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */ - /* remove device pointer */ - td->dev_ptr=0L; - } - } /* if we call the irq handler */ - link=swap_32(td->link) & 0xfffffff0; /* next in chain */ - td=(uhci_td_t *)link; /* assign it */ - } /* process all td in this int chain */ - } /* next interrupt chain */ -} - - -/* usb interrupt service routine. - */ -void handle_usb_interrupt(void) -{ - unsigned short status; - - /* - * Read the interrupt status, and write it back to clear the - * interrupt cause - */ - - status = in16r(usb_base_addr + USBSTS); - - if (!status) /* shared interrupt, not mine */ - return; - if (status != 1) { - /* remove host controller halted state */ - if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) { - out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD)); - } - } - usb_check_int_chain(); /* call interrupt handlers for int tds */ - usb_check_skel(); /* call completion handler for common transfer routines */ - out16r(usb_base_addr+USBSTS,status); -} - - -/* init uhci - */ -int usb_lowlevel_init(void) -{ - unsigned char temp; - int busdevfunc; -/* - * HJF - configure IRQ and base from variables optionally. - */ - char *s; - - - busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */ - if(busdevfunc==-1) { - printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID); - return -1; - } - -#if 1 - s = getenv("usb_irq"); - if (s) - { - temp = atoi(s); - pci_write_config_byte(busdevfunc, PCI_INTERRUPT_LINE, temp); - } - else -#endif - pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp); - - s = getenv("usb_base"); - if (s) - { - unsigned long temp2; - temp2 = atoi(s); - pci_write_config_dword(busdevfunc, PCI_BASE_ADDRESS_4, temp2|0x01); - } - - irqvec = temp; - irq_free_handler(irqvec); - USB_UHCI_PRINTF("Interrupt Line = %d\n",irqvec); - pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp); - USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp); - pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr); - USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr); - usb_base_addr&=0xFFFFFFF0; - usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS; - rh.devnum = 0; - usb_init_skel(); - reset_hc(); - start_hc(); - irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL); - irq_install_handler(0, (interrupt_handler_t *)handle_usb_interrupt, NULL); - - return 0; -} - -/* stop uhci - */ -int usb_lowlevel_stop(void) -{ - if(irqvec==-1) - return 1; - irq_free_handler(irqvec); - irq_free_handler(0); - reset_hc(); - irqvec=-1; - return 0; -} - -/******************************************************************************************* - * Virtual Root Hub - * Since the uhci does not have a real HUB, we simulate one ;-) - */ -#undef USB_RH_DEBUG - -#ifdef USB_RH_DEBUG -#define USB_RH_PRINTF(fmt,args...) printf (fmt ,##args) -static void usb_display_wValue(unsigned short wValue,unsigned short wIndex); -static void usb_display_Req(unsigned short req); -#else -#define USB_RH_PRINTF(fmt,args...) -static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {} -static void usb_display_Req(unsigned short req) {} -#endif - -static unsigned char root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x00, /* __u16 bcdUSB; v1.0 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x01, /* __u8 iManufacturer; */ - 0x00, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static unsigned char root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - - -static unsigned char root_hub_hub_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x29, /* __u8 bDescriptorType; Hub-descriptor */ - 0x02, /* __u8 bNbrPorts; */ - 0x00, /* __u16 wHubCharacteristics; */ - 0x00, - 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ - 0x00, /* __u8 bHubContrCurrent; 0 mA */ - 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ - 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'U', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - - -/* - * Root Hub Control Pipe (interrupt Pipes are not supported) - */ - - -int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd) -{ - void *data = buffer; - int leni = transfer_len; - int len = 0; - int status = 0; - int stat = 0; - int i; - - unsigned short cstatus; - - unsigned short bmRType_bReq; - unsigned short wValue; - unsigned short wIndex; - unsigned short wLength; - - if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { - printf("Root-Hub submit IRQ: NOT implemented\n"); -#if 0 - uhci->rh.urb = urb; - uhci->rh.send = 1; - uhci->rh.interval = urb->interval; - rh_init_int_timer (urb); -#endif - return 0; - } - bmRType_bReq = cmd->requesttype | cmd->request << 8; - wValue = swap_16(cmd->value); - wIndex = swap_16(cmd->index); - wLength = swap_16(cmd->length); - usb_display_Req(bmRType_bReq); - for (i = 0; i < 8; i++) - rh.c_p_r[i] = 0; - USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n", - dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(unsigned short *) data = swap_16(1); - len=2; - break; - case RH_GET_STATUS | RH_INTERFACE: - *(unsigned short *) data = swap_16(0); - len=2; - break; - case RH_GET_STATUS | RH_ENDPOINT: - *(unsigned short *) data = swap_16(0); - len=2; - break; - case RH_GET_STATUS | RH_CLASS: - *(unsigned long *) data = swap_32(0); - len=4; - break; /* hub power ** */ - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - - status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1)); - cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) | - ((status & USBPORTSC_PEC) >> (3 - 1)) | - (rh.c_p_r[wIndex - 1] << (0 + 4)); - status = (status & USBPORTSC_CCS) | - ((status & USBPORTSC_PE) >> (2 - 1)) | - ((status & USBPORTSC_SUSP) >> (12 - 2)) | - ((status & USBPORTSC_PR) >> (9 - 4)) | - (1 << 8) | /* power on ** */ - ((status & USBPORTSC_LSDA) << (-8 + 9)); - - *(unsigned short *) data = swap_16(status); - *(unsigned short *) (data + 2) = swap_16(cstatus); - len=4; - break; - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): - len=0; - break; - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case (RH_C_HUB_OVER_CURRENT): - len=0; /* hub power over current ** */ - break; - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - usb_display_wValue(wValue,wIndex); - switch (wValue) { - case (RH_PORT_ENABLE): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) & ~USBPORTSC_PE; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_SUSPEND): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) & ~USBPORTSC_SUSP; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_POWER): - len=0; /* port power ** */ - break; - case (RH_C_PORT_CONNECTION): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_CSC; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_C_PORT_ENABLE): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_PEC; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_C_PORT_SUSPEND): -/*** WR_RH_PORTSTAT(RH_PS_PSSC); */ - len=0; - break; - case (RH_C_PORT_OVER_CURRENT): - len=0; - break; - case (RH_C_PORT_RESET): - rh.c_p_r[wIndex - 1] = 0; - len=0; - break; - } - break; - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - usb_display_wValue(wValue,wIndex); - switch (wValue) { - case (RH_PORT_SUSPEND): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_SUSP; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_RESET): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_PR; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - wait_ms(10); - status = (status & 0xfff5) & ~USBPORTSC_PR; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - udelay(10); - status = (status & 0xfff5) | USBPORTSC_PE; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - wait_ms(10); - status = (status & 0xfff5) | 0xa; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_POWER): - len=0; /* port power ** */ - break; - case (RH_PORT_ENABLE): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_PE; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - } - break; - - case RH_SET_ADDRESS: - rh.devnum = wValue; - len=0; - break; - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - i=sizeof(root_hub_config_des); - status=i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_dev_des, len); - break; - case (0x02): /* configuration descriptor */ - i=sizeof(root_hub_config_des); - status=i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_config_des, len); - break; - case (0x03): /*string descriptors */ - if(wValue==0x0300) { - i=sizeof(root_hub_str_index0); - status = i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_str_index0, len); - break; - } - if(wValue==0x0301) { - i=sizeof(root_hub_str_index1); - status = i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_str_index1, len); - break; - } - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - root_hub_hub_des[2] = 2; - i=sizeof(root_hub_hub_des); - status= i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_hub_des, len); - break; - case RH_GET_CONFIGURATION: - *(unsigned char *) data = 0x01; - len = 1; - break; - case RH_SET_CONFIGURATION: - len=0; - break; - default: - stat = USB_ST_STALLED; - } - USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat, - in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2)); - dev->act_len=len; - dev->status=stat; - return stat; - -} - -/******************************************************************************** - * Some Debug Routines - */ - -#ifdef USB_RH_DEBUG - -static void usb_display_Req(unsigned short req) -{ - USB_RH_PRINTF("- Root-Hub Request: "); - switch (req) { - case RH_GET_STATUS: - USB_RH_PRINTF("Get Status "); - break; - case RH_GET_STATUS | RH_INTERFACE: - USB_RH_PRINTF("Get Status Interface "); - break; - case RH_GET_STATUS | RH_ENDPOINT: - USB_RH_PRINTF("Get Status Endpoint "); - break; - case RH_GET_STATUS | RH_CLASS: - USB_RH_PRINTF("Get Status Class"); - break; /* hub power ** */ - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - USB_RH_PRINTF("Get Status Class Others"); - break; - case RH_CLEAR_FEATURE | RH_ENDPOINT: - USB_RH_PRINTF("Clear Feature Endpoint "); - break; - case RH_CLEAR_FEATURE | RH_CLASS: - USB_RH_PRINTF("Clear Feature Class "); - break; - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - USB_RH_PRINTF("Clear Feature Other Class "); - break; - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - USB_RH_PRINTF("Set Feature Other Class "); - break; - case RH_SET_ADDRESS: - USB_RH_PRINTF("Set Address "); - break; - case RH_GET_DESCRIPTOR: - USB_RH_PRINTF("Get Descriptor "); - break; - case RH_GET_DESCRIPTOR | RH_CLASS: - USB_RH_PRINTF("Get Descriptor Class "); - break; - case RH_GET_CONFIGURATION: - USB_RH_PRINTF("Get Configuration "); - break; - case RH_SET_CONFIGURATION: - USB_RH_PRINTF("Get Configuration "); - break; - default: - USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req); - } - USB_RH_PRINTF("\n"); - -} - -static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) -{ - switch (wValue) { - case (RH_PORT_ENABLE): - USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex); - break; - case (RH_PORT_SUSPEND): - USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex); - break; - case (RH_PORT_POWER): - USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex); - break; - case (RH_C_PORT_CONNECTION): - USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex); - break; - case (RH_C_PORT_ENABLE): - USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex); - break; - case (RH_C_PORT_SUSPEND): - USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex); - break; - case (RH_C_PORT_OVER_CURRENT): - USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex); - break; - case (RH_C_PORT_RESET): - USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex); - break; - default: - USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex); - break; - } -} - -#endif - - -#ifdef USB_UHCI_DEBUG - -static int usb_display_td(uhci_td_t *td) -{ - unsigned long tmp; - int valid; - - printf("TD at %p:\n",td); - - tmp=swap_32(td->link); - printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0, - ((tmp & 0x4)==0x4) ? "Depth" : "Breath", - ((tmp & 0x2)==0x2) ? "QH" : "TD", - ((tmp & 0x1)==0x1) ? "invalid" : "valid"); - valid=((tmp & 0x1)==0x0); - tmp=swap_32(td->status); - printf(" %s %ld Errors %s %s %s \n %s %s %s %s %s %s\n Len 0x%lX\n", - (((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable", - ((tmp>>28)&0x3), - (((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed", - (((tmp>>25)&0x1)==0x1) ? "ISO " : "", - (((tmp>>24)&0x1)==0x1) ? "IOC " : "", - (((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ", - (((tmp>>22)&0x1)==0x1) ? "Stalled" : "", - (((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "", - (((tmp>>20)&0x1)==0x1) ? "Babble" : "", - (((tmp>>19)&0x1)==0x1) ? "NAK" : "", - (((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "", - (tmp&0x7ff)); - tmp=swap_32(td->info); - printf(" MaxLen 0x%lX\n",((tmp>>21)&0x7FF)); - printf(" %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "", - ((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF); - tmp=swap_32(td->buffer); - printf(" Buffer 0x%08lX\n",tmp); - printf(" DEV %08lX\n",td->dev_ptr); - return valid; -} - - -void usb_show_td(int max) -{ - int i; - if(max>0) { - for(i=0;i: */ -#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ -#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ -#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ -#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ -#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ -#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ -#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ -#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ -#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ -#define TD_CTRL_NAK (1 << 19) /* NAK Received */ -#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ -#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ -#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */ - -#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ - TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF) - -#define TD_TOKEN_TOGGLE 19 - -/* ------------------------------------------------------------------------------------ - Virtual Root HUB - ------------------------------------------------------------------------------------ */ -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -/* Our Vendor Specific feature */ -#define RH_REMOVE_EP 0x00 - - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* Transfer descriptor structure */ -typedef struct { - unsigned long link; /* next td/qh (LE)*/ - unsigned long status; /* status of the td */ - unsigned long info; /* Max Lenght / Endpoint / device address and PID */ - unsigned long buffer; /* pointer to data buffer (LE) */ - unsigned long dev_ptr; /* pointer to the assigned device (BE) */ - unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */ -} uhci_td_t, *puhci_td_t; - -/* Queue Header structure */ -typedef struct { - unsigned long head; /* Next QH (LE)*/ - unsigned long element; /* Queue element pointer (LE) */ - unsigned long res[5]; /* reserved */ - unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */ -} uhci_qh_t, *puhci_qh_t; - -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - int numports; /* number of ports */ - int c_p_r[8]; /* C_PORT_RESET */ -}; - - -#endif /* _USB_UHCI_H_ */ diff --git a/board/MAI/AmigaOneG3SE/via686.c b/board/MAI/AmigaOneG3SE/via686.c deleted file mode 100644 index c797e47..0000000 --- a/board/MAI/AmigaOneG3SE/via686.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * (C) Copyright 2002 - * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include "memio.h" -#include "articiaS.h" -#include "via686.h" -#include "i8259.h" - -#undef VIA_DEBUG - -#ifdef VIA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - - -/* Setup the ISA-to-PCI host bridge */ -void via_isa_init(pci_dev_t dev, struct pci_config_table *table) -{ - char regval; - if (PCI_FUNC(dev) == 0) - { - PRINTF("... PCI-to-ISA bridge, dev=0x%X\n", dev); - - /* Enable I/O Recovery time */ - pci_write_config_byte(dev, 0x40, 0x08); - - /* Enable ISA refresh */ - pci_write_config_byte(dev, 0x41, 0x41); /* was 01 */ - - /* Enable ISA line buffer */ - pci_write_config_byte(dev, 0x45, 0x80); - - /* Gate INTR, and flush line buffer */ - pci_write_config_byte(dev, 0x46, 0x60); - - /* Enable EISA ports 4D0/4D1. Do we need this ? */ - pci_write_config_byte(dev, 0x47, 0xe6); /* was 20 */ - - /* 512 K PCI Decode */ - pci_write_config_byte(dev, 0x48, 0x01); - - /* Wait for PGNT before grant to ISA Master/DMA */ - /* ports 0-FF to SDBus */ - /* IRQ 14 and 15 for ide 0/1 */ - pci_write_config_byte(dev, 0x4a, 0x04); /* Was c4 */ - - /* Plug'n'Play */ - /* Parallel DRQ 3, Floppy DRQ 2 (default) */ - pci_write_config_byte(dev, 0x50, 0x0e); - - /* IRQ Routing for Floppy and Parallel port */ - /* IRQ 6 for floppy, IRQ 7 for parallel port */ - pci_write_config_byte(dev, 0x51, 0x76); - - /* IRQ Routing for serial ports (take IRQ 3 and 4) */ - pci_write_config_byte(dev, 0x52, 0x34); - - /* All IRQ's level triggered. */ - pci_write_config_byte(dev, 0x54, 0x00); - - /* PCI IRQ's all at IRQ 9 */ - pci_write_config_byte(dev, 0x55, 0x90); - pci_write_config_byte(dev, 0x56, 0x99); - pci_write_config_byte(dev, 0x57, 0x90); - - /* Enable Keyboard */ - pci_read_config_byte(dev, 0x5A, ®val); - regval |= 0x01; - pci_write_config_byte(dev, 0x5A, regval); - - pci_write_config_byte(dev, 0x80, 0); - pci_write_config_byte(dev, 0x85, 0x01); - -/* pci_write_config_byte(dev, 0x77, 0x00); */ - } -} - -/* - * Initialize PNP irq routing - */ - -void via_init_irq_routing(uint8 irq_map[]) -{ - char *s; - uint8 level_edge_bits = 0xf; - - /* Set irq routings */ - pci_write_cfg_byte(0, 7<<3, 0x55, irq_map[0]<<4); - pci_write_cfg_byte(0, 7<<3, 0x56, irq_map[1] | irq_map[2]<<4); - pci_write_cfg_byte(0, 7<<3, 0x57, irq_map[3]<<4); - - /* - * Gather level/edge bits - * Default is to assume level triggered - */ - - s = getenv("pci_irqa_select"); - if (s && strcmp(s, "level") == 0) - level_edge_bits &= ~0x01; - - s = getenv("pci_irqb_select"); - if (s && strcmp(s, "level") == 0) - level_edge_bits &= ~0x02; - - s = getenv("pci_irqc_select"); - if (s && strcmp(s, "level") == 0) - level_edge_bits &= ~0x04; - - s = getenv("pci_irqd_select"); - if (s && strcmp(s, "level") == 0) - level_edge_bits &= ~0x08; - - PRINTF("IRQ map\n"); - PRINTF("%d: %s\n", irq_map[0], level_edge_bits&0x1 ? "edge" : "level"); - PRINTF("%d: %s\n", irq_map[1], level_edge_bits&0x2 ? "edge" : "level"); - PRINTF("%d: %s\n", irq_map[2], level_edge_bits&0x4 ? "edge" : "level"); - PRINTF("%d: %s\n", irq_map[3], level_edge_bits&0x8 ? "edge" : "level"); - pci_write_cfg_byte(0, 7<<3, 0x54, level_edge_bits); - - PRINTF("%02x %02x %02x %02x\n", pci_read_cfg_byte(0, 7<<3, 0x54), - pci_read_cfg_byte(0, 7<<3, 0x55), pci_read_cfg_byte(0, 7<<3, 0x56), - pci_read_cfg_byte(0, 7<<3, 0x57)); -} - - -/* Setup the IDE controller. This doesn't seem to work yet. I/O to an IDE controller port */ -/* always return the last character output on the serial port (!) */ -/* This function is called by the pnp-library when it encounters 0:7:1 */ -void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table) -{ - PRINTF("... IDE controller, dev=0x%X\n", dev); - - /* Enable both IDE channels. */ - pci_write_config_byte(dev, 0x40, 0x03); - /* udelay(10000); */ - /* udelay(10000); */ - - /* Enable IO Space */ - pci_write_config_word(dev, 0x04, 0x03); - - /* Set to compatibility mode */ - pci_write_config_byte(dev, 0x09, 0x8A); /* WAS: 0x8f); */ - - /* Set to legacy interrupt mode */ - pci_write_config_byte(dev, 0x3d, 0x00); /* WAS: 0x01); */ - -} - - -/* Set the base address of the floppy controller to 0x3F0 */ -void via_fdc_init(pci_dev_t dev) -{ - unsigned char c; - /* Enable Configuration mode */ - pci_read_config_byte(dev, 0x85, &c); - c |= 0x02; - pci_write_config_byte(dev, 0x85, c); - - /* Set floppy controller port to 0x3F0. */ - SIO_WRITE_CONFIG(0xE3, (0x3F<<2)); - - /* Enable floppy controller */ - SIO_READ_CONFIG(0xE2, c); - c |= 0x10; - SIO_WRITE_CONFIG(0xE2, c); - - /* Switch of configuration mode */ - pci_read_config_byte(dev, 0x85, &c); - c &= ~0x02; - pci_write_config_byte(dev, 0x85, c); -} - -/* Init function 0 of the via southbridge. Called by the pnp-library */ -void via_cfgfunc_via686(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table) -{ - if (PCI_FUNC(dev) == 0) - { - /* FIXME: Try to generate a PCI reset */ - /* unsigned char c; */ - /* pci_read_config_byte(dev, 0x47, &c); */ - /* pci_write_config_byte(dev, 0x47, c | 0x01); */ - - via_isa_init(dev, table); - via_fdc_init(dev); - } -} - -__asm (" .globl via_calibrate_time_base \n" - "via_calibrate_time_base: \n" - " lis 9, 0xfe00 \n" - " li 0, 0x00 \n" - " mttbu 0 \n" - " mttbl 0 \n" - "ctb_loop: \n" - " lbz 0, 0x61(9) \n" - " eieio \n" - " andi. 0, 0, 0x20 \n" - " beq ctb_loop \n" - "ctb_done: \n" - " mftb 3 \n" - " blr"); - -extern unsigned long via_calibrate_time_base(void); - -void via_calibrate_bus_freq(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned long tb; - - /* This is 20 microseconds */ - #define CALIBRATE_TIME 28636 - - - /* Enable the timer (and disable speaker) */ - unsigned char c; - c = in_byte(0x61); - out_byte(0x61, ((c & ~0x02) | 0x01)); - - /* Set timer 2 to low/high writing */ - out_byte(0x43, 0xb0); - out_byte(0x42, CALIBRATE_TIME & 0xff); - out_byte(0x42, CALIBRATE_TIME >>8); - - /* Read the time base */ - tb = via_calibrate_time_base(); - - if (tb >= 700000) - gd->bus_clk = 133333333; - else - gd->bus_clk = 100000000; - -} - - -void ide_led(uchar led, uchar status) -{ -/* unsigned char c = in_byte(0x92); */ - -/* if (!status) */ -/* out_byte(0x92, c | 0xC0); */ -/* else */ -/* out_byte(0x92, c & ~0xC0); */ -} - - -void via_init_afterscan(void) -{ - /* Modify IDE controller setup */ - pci_write_cfg_byte(0, 7<<3|1, PCI_LATENCY_TIMER, 0x20); - pci_write_cfg_byte(0, 7<<3|1, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER); - pci_write_cfg_byte(0, 7<<3|1, PCI_INTERRUPT_LINE, 0xff); - pci_write_cfg_byte(0, 7<<3|1, 0x40, 0x0b); /* FIXME: Might depend on drives connected */ - pci_write_cfg_byte(0, 7<<3|1, 0x41, 0x42); /* FIXME: Might depend on drives connected */ - pci_write_cfg_byte(0, 7<<3|1, 0x43, 0x05); - pci_write_cfg_byte(0, 7<<3|1, 0x44, 0x18); - pci_write_cfg_byte(0, 7<<3|1, 0x45, 0x10); - pci_write_cfg_byte(0, 7<<3|1, 0x4e, 0x22); /* FIXME: Not documented, but set in PC bios */ - pci_write_cfg_byte(0, 7<<3|1, 0x4f, 0x20); /* FIXME: Not documented */ - - /* Modify some values in the USB controller */ - pci_write_cfg_byte(0, 7<<3|2, 0x05, 0x17); - pci_write_cfg_byte(0, 7<<3|2, 0x06, 0x01); - pci_write_cfg_byte(0, 7<<3|2, 0x41, 0x12); - pci_write_cfg_byte(0, 7<<3|2, 0x42, 0x03); - pci_write_cfg_byte(0, 7<<3|2, PCI_LATENCY_TIMER, 0x40); - - pci_write_cfg_byte(0, 7<<3|3, 0x05, 0x17); - pci_write_cfg_byte(0, 7<<3|3, 0x06, 0x01); - pci_write_cfg_byte(0, 7<<3|3, 0x41, 0x12); - pci_write_cfg_byte(0, 7<<3|3, 0x42, 0x03); - pci_write_cfg_byte(0, 7<<3|3, PCI_LATENCY_TIMER, 0x40); - - -} diff --git a/board/MAI/AmigaOneG3SE/via686.h b/board/MAI/AmigaOneG3SE/via686.h deleted file mode 100644 index 2a06a05..0000000 --- a/board/MAI/AmigaOneG3SE/via686.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef VIA686_H_ -#define VIA686_H_ - - -#define CMOS_ADDR 0x70 -#define CMOS_DATA 0x71 - -#define I8259_MASTER_CONTROL 0x20 -#define I8259_MASTER_MASK 0x21 - -#define I8259_SLAVE_CONTROL 0xA0 -#define I8259_SLAVE_MASK 0xA1 - -#define SIO_CONFIG_ADDR 0x3F0 -#define SIO_CONFIG_DATA 0x3F1 - -#define SIO_WRITE_CONFIG(addr, byte) \ - out_byte(SIO_CONFIG_ADDR, addr); \ - out_byte(SIO_CONFIG_DATA, byte); - -#define SIO_READ_CONFIG(addr, byte) \ - out_byte(SIO_CONFIG_ADDR, addr); \ - byte = in_byte(SIO_CONFIG_DATA); - -void via_init(void); - -void via_calibrate_bus_freq(void); - -#endif diff --git a/board/MAI/AmigaOneG3SE/video.c b/board/MAI/AmigaOneG3SE/video.c deleted file mode 100644 index 36e3c62..0000000 --- a/board/MAI/AmigaOneG3SE/video.c +++ /dev/null @@ -1,539 +0,0 @@ -/* - * (C) Copyright 2002 - * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "memio.h" -#include - -unsigned char *cursor_position; -unsigned int cursor_row; -unsigned int cursor_col; - -unsigned char current_attr; - -unsigned int video_numrows = 25; -unsigned int video_numcols = 80; -unsigned int video_scrolls = 0; - -#define VIDEO_BASE (unsigned char *)0xFD0B8000 -#define VIDEO_ROWS video_numrows -#define VIDEO_COLS video_numcols -#define VIDEO_PITCH (2 * video_numcols) -#define VIDEO_SIZE (video_numrows * video_numcols * 2) -#define VIDEO_NAME "vga" - -void video_test(void); -void video_putc(char ch); -void video_puts(char *string); -void video_scroll(int rows); -void video_banner(void); -int video_init(void); -int video_start(void); -int video_rows(void); -int video_cols(void); - -char *prompt_string = "=>"; - -void video_set_color(unsigned char attr) -{ - unsigned char *fb = (unsigned char *)VIDEO_BASE; - int i; - - current_attr = video_get_attr(); - - for (i=0; i VIDEO_COLS-1) - { - cursor_row++; - cursor_col=0; - } - } - - if (cursor_row > VIDEO_ROWS-1) - video_scroll(1); - video_set_cursor(cursor_row, cursor_col); -} - -void video_scroll(int rows) -{ - unsigned short clear = ((unsigned short)current_attr) | (' '<<8); - unsigned short* addr16 = &((unsigned short *)VIDEO_BASE)[(VIDEO_ROWS-rows)*VIDEO_COLS]; - int i; - char *s; - - s = getenv("vga_askscroll"); - video_scrolls += rows; - - if (video_scrolls >= video_numrows) - { - if (s && strcmp(s, "yes")) - { - while (-1 == tstc()); - } - - video_scrolls = 0; - } - - - memcpy(VIDEO_BASE, VIDEO_BASE+rows*(VIDEO_COLS*2), (VIDEO_ROWS-rows)*(VIDEO_COLS*2)); - for (i = 0 ; i < rows * VIDEO_COLS ; i++) - addr16[i] = clear; - cursor_row-=rows; - cursor_col=0; -} - -void video_puts(char *string) -{ - while (*string) - { - video_putc(*string); - string++; - } -} - -int video_start(void) -{ - return 0; -} - -unsigned char video_single_box[] = -{ - 218, 196, 191, - 179, 179, - 192, 196, 217 -}; - -unsigned char video_double_box[] = -{ - 201, 205, 187, - 186, 186, - 200, 205, 188 -}; - -unsigned char video_single_title[] = -{ - 195, 196, 180, 180, 195 -}; - -unsigned char video_double_title[] = -{ - 204, 205, 185, 181, 198 -}; - -#define SINGLE_BOX 0 -#define DOUBLE_BOX 1 - -unsigned char *video_addr(int x, int y) -{ - return VIDEO_BASE + 2*(VIDEO_COLS*y) + 2*x; -} - -void video_bios_print_string(char *s, int x, int y, int attr, int count) -{ - int cattr = current_attr; - if (attr != -1) current_attr = attr; - video_set_cursor(x,y); - while (count) - { - char c = *s++; - if (attr == -1) current_attr = *s++; - video_putc(c); - count--; - } -} - -void video_draw_box(int style, int attr, char *title, int separate, int x, int y, int w, int h) -{ - unsigned char *fb, *fb2; - unsigned char *st = (style == SINGLE_BOX)?video_single_box : video_double_box; - unsigned char *ti = (style == SINGLE_BOX)?video_single_title : video_double_title; - int i; - - fb = video_addr(x,y); - *(fb) = st[0]; - *(fb+1) = attr; - fb += 2; - - fb2 = video_addr(x,y+h-1); - *(fb2) = st[5]; - *(fb2+1) = attr; - fb2 += 2; - - for (i=0; i 0) *fb = clearchar; - fb ++; - *save ++ = *fb; - if (clearattr > 0) *fb = clearattr; - } - fb = fbb + 2*VIDEO_COLS; - } -} - -void video_restore_rect(int x, int y, int w, int h, void *save_area) -{ - unsigned char *save = (unsigned char *)save_area; - unsigned char *fb = video_addr(x,y); - int i,j; - for (i=0; ibd->bi_memsize/(1024*1024)); - printf("FSB: %ld MHz\n", gd->bd->bi_busfreq/1000000); - - printf("\n---- Disk summary ----\n"); - for (i = 0; i < maxdev; i++) - { - ide = ide_get_dev(i); - printf("Device %d: ", i); - dev_print(ide); - } - -/* - video_draw_box(SINGLE_BOX, 0x0F, "Test 1", 0, 0,18, 72, 4); - video_draw_box(DOUBLE_BOX, 0x0F, "Test 2", 1, 4,10, 50, 6); - video_draw_box(DOUBLE_BOX, 0x0F, "Test 3", 0, 40, 3, 20, 5); - - video_draw_text(1, 4, 0x2F, "Highlighted options"); - video_draw_text(1, 5, 0x0F, "Non-selected option"); - video_draw_text(1, 6, 0x07, "disabled option"); -*/ -#ifdef EASTEREGG - } -#endif -} diff --git a/board/MAI/bios_emulator/bios.c b/board/MAI/bios_emulator/bios.c deleted file mode 100644 index d51eb64..0000000 --- a/board/MAI/bios_emulator/bios.c +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Mostly done after the Scitech Bios emulation - * Written by Hans-Jörg Frieden - * Hyperion Entertainment - */ -#include "x86emu.h" -#include "glue.h" - -#undef DEBUG -#ifdef DEBUG -#define PRINTF(fmt, args...) printf(fmt, ## args) -#else -#define PRINTF(fmt, args...) -#endif - -#define BIOS_SEG 0xFFF0 -#define PCIBIOS_SUCCESSFUL 0 -#define PCIBIOS_DEVICE_NOT_FOUND 0x86 - -typedef unsigned char UBYTE; -typedef unsigned short UWORD; -typedef unsigned long ULONG; - -typedef char BYTE; -typedef short WORT; -typedef long LONG; - -static inline UBYTE read_byte(volatile UBYTE* from) -{ - int x; - asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from)); - return (UBYTE)x; -} - -static inline void write_byte(volatile UBYTE *to, int x) -{ - asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x)); -} - -static inline UWORD read_word_little(volatile UWORD *from) -{ - int x; - asm volatile ("lhbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m" (*from)); - return (UWORD)x; -} - -static inline UWORD read_word_big(volatile UWORD *from) -{ - int x; - asm volatile ("lhz %0,%1\n eieio" : "=r" (x) : "m" (*from)); - return (UWORD)x; -} - -static inline void write_word_little(volatile UWORD *to, int x) -{ - asm volatile ("sthbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); -} - -static inline void write_word_big(volatile UWORD *to, int x) -{ - asm volatile ("sth %1,%0\n eieio" : "=m" (*to) : "r" (x)); -} - -static inline ULONG read_long_little(volatile ULONG *from) -{ - unsigned long x; - asm volatile ("lwbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m"(*from)); - return (ULONG)x; -} - -static inline ULONG read_long_big(volatile ULONG *from) -{ - unsigned long x; - asm volatile ("lwz %0,%1\n eieio" : "=r" (x) : "m" (*from)); - return (ULONG)x; -} - -static inline void write_long_little(volatile ULONG *to, ULONG x) -{ - asm volatile ("stwbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); -} - -static inline void write_long_big(volatile ULONG *to, ULONG x) -{ - asm volatile ("stw %1,%0\n eieio" : "=m" (*to) : "r" (x)); -} - -#define port_to_mem(from) (0xFE000000|(from)) -#define in_byte(from) read_byte( (UBYTE *)port_to_mem(from)) -#define in_word(from) read_word_little((UWORD *)port_to_mem(from)) -#define in_long(from) read_long_little((ULONG *)port_to_mem(from)) -#define out_byte(to, val) write_byte((UBYTE *)port_to_mem(to), val) -#define out_word(to, val) write_word_little((UWORD *)port_to_mem(to), val) -#define out_long(to, val) write_long_little((ULONG *)port_to_mem(to), val) - -static void X86API undefined_intr(int intno) -{ - extern u16 A1_rdw(u32 addr); - if (A1_rdw(intno * 4 + 2) == BIOS_SEG) - { - PRINTF("Undefined interrupt %xh called AX = %xh, BX = %xh, CX = %xh, DX = %xh\n", - intno, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); - X86EMU_halt_sys(); - } - else - { - PRINTF("Calling interrupt %xh, AL=%xh, AH=%xh\n", intno, M.x86.R_AL, M.x86.R_AH); - X86EMU_prepareForInt(intno); - } -} - -static void X86API int42(int intno); -static void X86API int15(int intno); - -static void X86API int10(int intno) -{ - if (A1_rdw(intno*4+2) == BIOS_SEG) - int42(intno); - else - { - PRINTF("int10: branching to %04X:%04X, AL=%xh, AH=%xh\n", A1_rdw(intno*4+2), A1_rdw(intno*4), - M.x86.R_AL, M.x86.R_AH); - X86EMU_prepareForInt(intno); - } -} - -static void X86API int1A(int intno) -{ - int device; - - switch(M.x86.R_AX) - { - case 0xB101: /* PCI Bios Present? */ - M.x86.R_AL = 0x00; - M.x86.R_EDX = 0x20494350; - M.x86.R_BX = 0x0210; - M.x86.R_CL = 3; - CLEAR_FLAG(F_CF); - break; - case 0xB102: /* Find device */ - device = mypci_find_device(M.x86.R_DX, M.x86.R_CX, M.x86.R_SI); - if (device != -1) - { - M.x86.R_AH = PCIBIOS_SUCCESSFUL; - M.x86.R_BH = mypci_bus(device); - M.x86.R_BL = mypci_devfn(device); - } - else - { - M.x86.R_AH = PCIBIOS_DEVICE_NOT_FOUND; - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); - break; - case 0xB103: /* Find PCI class code */ - M.x86.R_AH = PCIBIOS_DEVICE_NOT_FOUND; - /*printf("Find by class not yet implmented"); */ - CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); - break; - case 0xB108: /* read config byte */ - M.x86.R_CL = mypci_read_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI); - M.x86.R_AH = PCIBIOS_SUCCESSFUL; - CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); - /*printf("read_config_byte %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ - /* M.x86.R_CL); */ - break; - case 0xB109: /* read config word */ - M.x86.R_CX = mypci_read_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI); - M.x86.R_AH = PCIBIOS_SUCCESSFUL; - CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); - /*printf("read_config_word %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ - /* M.x86.R_CX); */ - break; - case 0xB10A: /* read config dword */ - M.x86.R_ECX = mypci_read_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI); - M.x86.R_AH = PCIBIOS_SUCCESSFUL; - CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); - /*printf("read_config_long %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ - /* M.x86.R_ECX); */ - break; - case 0xB10B: /* write config byte */ - mypci_write_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CL); - M.x86.R_AH = PCIBIOS_SUCCESSFUL; - CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); - /*printf("write_config_byte %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ - /* M.x86.R_CL); */ - break; - case 0xB10C: /* write config word */ - mypci_write_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CX); - M.x86.R_AH = PCIBIOS_SUCCESSFUL; - CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); - /*printf("write_config_word %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ - /* M.x86.R_CX); */ - break; - case 0xB10D: /* write config dword */ - mypci_write_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_ECX); - M.x86.R_AH = PCIBIOS_SUCCESSFUL; - CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); - /*printf("write_config_long %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ - /* M.x86.R_ECX); */ - break; - default: - PRINTF("BIOS int %xh: Unknown function AX=%04xh\n", intno, M.x86.R_AX); - - } -} - -void bios_init(void) -{ - int i; - X86EMU_intrFuncs bios_intr_tab[256]; - - for (i=0; i<256; i++) - { - write_long_little(M.mem_base+i*4, BIOS_SEG<<16); - bios_intr_tab[i] = undefined_intr; - } - - bios_intr_tab[0x10] = int10; - bios_intr_tab[0x1A] = int1A; - bios_intr_tab[0x42] = int42; - bios_intr_tab[0x15] = int15; - - bios_intr_tab[0x6D] = int42; - - X86EMU_setupIntrFuncs(bios_intr_tab); - video_init(); -} - -unsigned char setup_40x25[] = -{ - 0x38, 0x28, 0x2d, 0x0a, 0x1f, 6, 0x19, - 0x1c, 2, 7, 6, 7, 0, 0, 0, 0 -}; - -unsigned char setup_80x25[] = -{ - 0x71, 0x50, 0x5a, 0x0a, 0x1f, 6, 0x19, - 0x1c, 2, 7, 6, 7, 0, 0, 0, 0 -}; - -unsigned char setup_graphics[] = -{ - 0x38, 0x28, 0x20, 0x0a, 0x7f, 6, 0x64, - 0x70, 2, 1, 6, 7, 0, 0, 0, 0 -}; - -unsigned char setup_bw[] = -{ - 0x61, 0x50, 0x52, 0x0f, 0x19, 6, 0x19, - 0x19, 2, 0x0d, 0x0b, 0x0c, 0, 0, 0, 0 -}; - -unsigned char * setup_modes[] = -{ - setup_40x25, /* mode 0: 40x25 bw text */ - setup_40x25, /* mode 1: 40x25 col text */ - setup_80x25, /* mode 2: 80x25 bw text */ - setup_80x25, /* mode 3: 80x25 col text */ - setup_graphics, /* mode 4: 320x200 col graphics */ - setup_graphics, /* mode 5: 320x200 bw graphics */ - setup_graphics, /* mode 6: 640x200 bw graphics */ - setup_bw /* mode 7: 80x25 mono text */ -}; - -unsigned int setup_cols[] = -{ - 40, 40, 80, 80, 40, 40, 80, 80 -}; - -unsigned char setup_modesets[] = -{ - 0x2C, 0x28, 0x2D, 0x29, 0x2A, 0x2E, 0x1E, 0x29 -}; - -unsigned int setup_bufsize[] = -{ - 2048, 2048, 4096, 2096, 16384, 16384, 16384, 4096 -}; - -void bios_set_mode(int mode) -{ - int i; - unsigned char mode_set = setup_modesets[mode]; /* Control register value */ - unsigned char *setup_regs = setup_modes[mode]; /* Register 3D4 Array */ - - /* Switch video off */ - out_byte(0x3D8, mode_set & 0x37); - - /* Set up parameters at 3D4h */ - for (i=0; i<16; i++) - { - out_byte(0x3D4, (unsigned char)i); - out_byte(0x3D5, *setup_regs); - setup_regs++; - } - - /* Enable video */ - out_byte(0x3D8, mode_set); - - /* Set overscan */ - if (mode == 6) out_byte(0x3D9, 0x3F); - else out_byte(0x3D9, 0x30); -} - -static void bios_print_string(void) -{ - extern void video_bios_print_string(char *string, int x, int y, int attr, int count); - char *s = (char *)(M.x86.R_ES<<4) + M.x86.R_BP; - int attr; - if (M.x86.R_AL & 0x02) attr = - 1; - else attr = M.x86.R_BL; - video_bios_print_string(s, M.x86.R_DH, M.x86.R_DL, attr, M.x86.R_CX); -} - -static void X86API int42(int intno) -{ - switch (M.x86.R_AH) - { - case 0x00: - bios_set_mode(M.x86.R_AL); - break; - case 0x13: - bios_print_string(); - break; - default: - PRINTF("Warning: VIDEO BIOS interrupt %xh unimplemented function %xh, AL = %xh\n", - intno, M.x86.R_AH, M.x86.R_AL); - } -} - -static void X86API int15(int intno) -{ - PRINTF("Called interrupt 15h: AX = %xh, BX = %xh, CX = %xh, DX = %xh\n", - M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); -} diff --git a/board/MAI/bios_emulator/glue.c b/board/MAI/bios_emulator/glue.c deleted file mode 100644 index b380f0d..0000000 --- a/board/MAI/bios_emulator/glue.c +++ /dev/null @@ -1,515 +0,0 @@ -#include -#include -#include <74xx_7xx.h> - - -#ifdef DEBUG -#undef DEBUG -#endif - -#ifdef DEBUG -#define PRINTF(format, args...) _printf(format , ## args) -#else -#define PRINTF(format, argc...) -#endif - -static pci_dev_t to_pci(int bus, int devfn) -{ - return PCI_BDF(bus, (devfn>>3), devfn&3); -} - -int mypci_find_device(int vendor, int product, int index) -{ - return pci_find_device(vendor, product, index); -} - -int mypci_bus(int device) -{ - return PCI_BUS(device); -} - -int mypci_devfn(int device) -{ - return (PCI_DEV(device)<<3) | PCI_FUNC(device); -} - - -#define mypci_read_func(type, size) \ -type mypci_read_cfg_##size##(int bus, int devfn, int offset) \ -{ \ - type c; \ - pci_read_config_##size##(to_pci(bus, devfn), offset, &c); \ - return c; \ -} - -#define mypci_write_func(type, size) \ -void mypci_write_cfg_##size##(int bus, int devfn, int offset, int value) \ -{ \ - pci_write_config_##size##(to_pci(bus, devfn), offset, value); \ -} - -mypci_read_func(u8,byte); -mypci_read_func(u16,word); - -mypci_write_func(u8,byte); -mypci_write_func(u16,word); - -u32 mypci_read_cfg_long(int bus, int devfn, int offset) -{ - u32 c; - pci_read_config_dword(to_pci(bus, devfn), offset, &c); - return c; -} - -void mypci_write_cfg_long(int bus, int devfn, int offset, int value) -{ - pci_write_config_dword(to_pci(bus, devfn), offset, value); -} - -void _printf(const char *fmt, ...) -{ - va_list args; - char buf[CFG_PBSIZE]; - - va_start(args, fmt); - (void)vsprintf(buf, fmt, args); - va_end(args); - - printf(buf); -} - -char *_getenv(char *name) -{ - return getenv(name); -} - -unsigned long get_bar_size(pci_dev_t dev, int offset) -{ - u32 bar_back, bar_value; - - /* Save old BAR value */ - pci_read_config_dword(dev, offset, &bar_back); - - /* Write all 1's. */ - pci_write_config_dword(dev, offset, ~0); - - /* Now read back the relevant bits */ - pci_read_config_dword(dev, offset, &bar_value); - - /* Restore original value */ - pci_write_config_dword(dev, offset, bar_back); - - if (bar_value == 0) return 0xFFFFFFFF; /* This BAR is disabled */ - - if ((bar_value & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) - { - /* This is a memory space BAR. Mask it out so we get the size of it */ - return ~(bar_value & PCI_BASE_ADDRESS_MEM_MASK) + 1; - } - - /* Not suitable */ - return 0xFFFFFFFF; -} - -void enable_compatibility_hole(void) -{ - u8 cfg; - pci_dev_t art = PCI_BDF(0,0,0); - - pci_read_config_byte(art, 0x54, &cfg); - /* cfg |= 0x08; */ - cfg |= 0x20; - pci_write_config_byte(art, 0x54, cfg); -} - -void disable_compatibility_hole(void) -{ - u8 cfg; - pci_dev_t art = PCI_BDF(0,0,0); - - pci_read_config_byte(art, 0x54, &cfg); - /* cfg &= ~0x08; */ - cfg &= ~0x20; - pci_write_config_byte(art, 0x54, cfg); -} - -void map_rom(pci_dev_t dev, u32 address) -{ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, address|PCI_ROM_ADDRESS_ENABLE); -} - -void unmap_rom(pci_dev_t dev) -{ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0); -} - -void bat_map(u8 batnum, u32 address, u32 length) -{ - u32 temp = address; - address &= 0xFFFE0000; - temp &= 0x0001FFFF; - length = (length - 1 ) >> 17; - length <<= 2; - - switch (batnum) - { - case 0: - __asm volatile ("mtdbatu 0, %0" : : "r" (address | length | 3)); - __asm volatile ("mtdbatl 0, %0" : : "r" (address | 0x22)); - break; - case 1: - __asm volatile ("mtdbatu 1, %0" : : "r" (address | length | 3)); - __asm volatile ("mtdbatl 1, %0" : : "r" (address | 0x22)); - break; - case 2: - __asm volatile ("mtdbatu 2, %0" : : "r" (address | length | 3)); - __asm volatile ("mtdbatl 2, %0" : : "r" (address | 0x22)); - break; - case 3: - __asm volatile ("mtdbatu 3, %0" : : "r" (address | length | 3)); - __asm volatile ("mtdbatl 3, %0" : : "r" (address | 0x22)); - break; - } -} - -int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size); - -int attempt_map_rom(pci_dev_t dev, void *copy_address) -{ - u32 rom_size = 0; - u32 rom_address = 0; - u32 bar_size = 0; - u32 bar_backup = 0; - int i,j; - void *image = 0; - u32 image_size = 0; - int did_correct = 0; - u32 prefetch_addr = 0; - u32 prefetch_size = 0; - u32 prefetch_idx = 0; - - /* Get the size of the expansion rom */ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0xFFFFFFFF); - pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_size); - if ((rom_size & 0x01) == 0) - { - PRINTF("No ROM\n"); - return 0; - } - - rom_size &= 0xFFFFF800; - rom_size = (~rom_size)+1; - - PRINTF("ROM Size is %dK\n", rom_size/1024); - - /* - * Try to find a place for the ROM. We always attempt to use - * one of the card's bases for this, as this will be in any - * bridge's resource range as well as being free of conflicts - * with other cards. In a graphics card it is very unlikely - * that there won't be any base address that is large enough to - * hold the rom. - * - * FIXME: To work around this, theoretically the largest base - * could be used if none is found in the loop below. - */ - - for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4) - { - bar_size = get_bar_size(dev, i); - PRINTF("PCI_BASE_ADDRESS_%d is %dK large\n", - (i - PCI_BASE_ADDRESS_0)/4, - bar_size/1024); - if (bar_size != 0xFFFFFFFF && bar_size >= rom_size) - { - PRINTF("Found a match for rom size\n"); - pci_read_config_dword(dev, i, &rom_address); - rom_address &= 0xFFFFFFF0; - if (rom_address != 0 && rom_address != 0xFFFFFFF0) break; - } - } - - if (rom_address == 0 || rom_address == 0xFFFFFFF0) - { - PRINTF("No suitable rom address found\n"); - return 0; - } - - /* Disable the BAR */ - pci_read_config_dword(dev, i, &bar_backup); - pci_write_config_dword(dev, i, 0); - - /* Map ROM */ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address | PCI_ROM_ADDRESS_ENABLE); - - /* Copy the rom to a place in the emulator space */ - PRINTF("Claiming BAT 2\n"); - bat_map(2, rom_address, rom_size); - /* show_bat_mapping(); */ - - if (0 == find_image(rom_address, rom_size, &image, &image_size)) - { - PRINTF("No x86 BIOS image found\n"); - return 0; - } - - PRINTF("Copying %ld bytes from 0x%lx to 0x%lx\n", (long)image_size, (long)image, (long)copy_address); - - /* memcpy(copy_address, rom_address, rom_size); */ - { - unsigned char *from = (unsigned char *)image; /* rom_address; */ - unsigned char *to = (unsigned char *)copy_address; - for (j=0; j>16, (prefetch_addr+prefetch_size)>>16); */ -/* pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, (prefetch_addr>>16)); */ -/* pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, (prefetch_addr+prefetch_size)>>16); */ - } - - pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, 0x1000); - pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, 0x0000); - - pci_write_config_byte(bridge, 0xD0, 0x0A); - pci_write_config_byte(bridge, 0xD3, 0x04); - - /* - * Set the interrupt pin to 0 - */ -#if 0 - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0); - pci_write_config_byte(dev, PCI_INTERRUPT_PIN, 0); -#endif - pci_write_config_byte(bridge, PCI_INTERRUPT_LINE, 0); - pci_write_config_byte(bridge, PCI_INTERRUPT_PIN, 0); - - } - } - - /* Finally, enable the card's IO and memory response */ - pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0); - pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0); - - return 1; -} - -int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size) -{ - int i = 0; - unsigned char *rom = (unsigned char *)rom_address; - /* if (*rom != 0x55 || *(rom+1) != 0xAA) return 0; /* No bios rom this is, yes. */ */ - - for (;;) - { - unsigned short pci_data_offset = *(rom+0x18) + 256 * *(rom+0x19); - unsigned short pci_image_length = (*(rom+pci_data_offset+0x10) + 256 * *(rom+pci_data_offset+0x11)) * 512; - unsigned char pci_image_type = *(rom+pci_data_offset+0x14); - if (*rom != 0x55 || *(rom+1) != 0xAA) - { - PRINTF("Invalid header this is\n"); - return 0; - } - PRINTF("Image %i: Type %d (%s)\n", i++, pci_image_type, - pci_image_type==0 ? "x86" : - pci_image_type==1 ? "OpenFirmware" : - "Unknown"); - if (pci_image_type == 0) - { - *image = rom; - *image_size = pci_image_length; - return 1; - } - - if (*(rom+pci_data_offset+0x15) & 0x80) - { - PRINTF("LAST image encountered, no image found\n"); - return 0; - } - - rom += pci_image_length; - } -} - -void show_bat_mapping(void) -{ - u32 dbat0u, dbat0l, ibat0u, ibat0l; - u32 dbat1u, dbat1l, ibat1u, ibat1l; - u32 dbat2u, dbat2l, ibat2u, ibat2l; - u32 dbat3u, dbat3l, ibat3u, ibat3l; - u32 msr, hid0, l2cr_reg; - - __asm volatile ("mfdbatu %0,0" : "=r" (dbat0u)); - __asm volatile ("mfdbatl %0,0" : "=r" (dbat0l)); - __asm volatile ("mfibatu %0,0" : "=r" (ibat0u)); - __asm volatile ("mfibatl %0,0" : "=r" (ibat0l)); - - __asm volatile ("mfdbatu %0,1" : "=r" (dbat1u)); - __asm volatile ("mfdbatl %0,1" : "=r" (dbat1l)); - __asm volatile ("mfibatu %0,1" : "=r" (ibat1u)); - __asm volatile ("mfibatl %0,1" : "=r" (ibat1l)); - - __asm volatile ("mfdbatu %0,2" : "=r" (dbat2u)); - __asm volatile ("mfdbatl %0,2" : "=r" (dbat2l)); - __asm volatile ("mfibatu %0,2" : "=r" (ibat2u)); - __asm volatile ("mfibatl %0,2" : "=r" (ibat2l)); - - __asm volatile ("mfdbatu %0,3" : "=r" (dbat3u)); - __asm volatile ("mfdbatl %0,3" : "=r" (dbat3l)); - __asm volatile ("mfibatu %0,3" : "=r" (ibat3u)); - __asm volatile ("mfibatl %0,3" : "=r" (ibat3l)); - - __asm volatile ("mfmsr %0" : "=r" (msr)); - __asm volatile ("mfspr %0,1008": "=r" (hid0)); - __asm volatile ("mfspr %0,1017": "=r" (l2cr_reg)); - - printf("dbat0u: %08x dbat0l: %08x ibat0u: %08x ibat0l: %08x\n", - dbat0u, dbat0l, ibat0u, ibat0l); - printf("dbat1u: %08x dbat1l: %08x ibat1u: %08x ibat1l: %08x\n", - dbat1u, dbat1l, ibat1u, ibat1l); - printf("dbat2u: %08x dbat2l: %08x ibat2u: %08x ibat2l: %08x\n", - dbat2u, dbat2l, ibat2u, ibat2l); - printf("dbat3u: %08x dbat3l: %08x ibat3u: %08x ibat3l: %08x\n", - dbat3u, dbat3l, ibat3u, ibat3l); - - printf("\nMSR: %08x HID0: %08x L2CR: %08x \n", msr,hid0, l2cr_reg); -} - - -void remove_init_data(void) -{ - char *s; - - /* Invalidate and disable data cache */ - invalidate_l1_data_cache(); - dcache_disable(); - - s = getenv("x86_cache"); - - if (!s) - { - icache_enable(); - dcache_enable(); - } - else if (s) - { - if (strcmp(s, "dcache")==0) - { - dcache_enable(); - } - else if (strcmp(s, "icache") == 0) - { - icache_enable(); - } - else if (strcmp(s, "on")== 0 || strcmp(s, "both") == 0) - { - dcache_enable(); - icache_enable(); - } - } - - /* show_bat_mapping();*/ -} diff --git a/board/MAI/bios_emulator/glue.h b/board/MAI/bios_emulator/glue.h deleted file mode 100644 index 585efe1..0000000 --- a/board/MAI/bios_emulator/glue.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef GLUE_H -#define GLUE_H - -typedef unsigned int pci_dev_t; - -int mypci_find_device(int vendor, int product, int index); -int mypci_bus(int device); -int mypci_devfn(int device); -unsigned long get_bar_size(pci_dev_t dev, int offset); - -u8 mypci_read_cfg_byte(int bus, int devfn, int offset); -u16 mypci_read_cfg_word(int bus, int devfn, int offset); -u32 mypci_read_cfg_long(int bus, int devfn, int offset); - -void mypci_write_cfg_byte(int bus, int devfn, int offset, u8 value); -void mypci_write_cfg_word(int bus, int devfn, int offset, u16 value); -void mypci_write_cfg_long(int bus, int devfn, int offset, u32 value); - -void _printf(const char *fmt, ...); -char *_getenv(char *name); - -void *malloc(size_t size); -void memset(void *addr, int value, size_t size); -void memcpy(void *to, void *from, size_t numbytes); -int strcmp(char *, char *); - -void enable_compatibility_hole(void); -void disable_compatibility_hole(void); - -void map_rom(pci_dev_t dev, unsigned long address); -void unmap_rom(pci_dev_t dev); -int attempt_map_rom(pci_dev_t dev, void *copy_address); - -#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ -#define PCI_BASE_ADDRESS_SPACE_IO 0x01 -#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 -#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) - -#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ -#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ -#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ -#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ -#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ -#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ -#define PCI_BUS(d) (((d) >> 16) & 0xff) -#define PCI_DEV(d) (((d) >> 11) & 0x1f) -#define PCI_FUNC(d) (((d) >> 8) & 0x7) -#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8) - -#define PCI_ANY_ID (~0) -#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ -#define PCI_ROM_ADDRESS_ENABLE 0x01 - -#define OFF(addr) ((addr) & 0xFFFF) -#define SEG(addr) (((addr)>>4) &0xF000) - -#endif diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake deleted file mode 100755 index 4d6ccb3..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp deleted file mode 100755 index d372949..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo deleted file mode 100755 index 6f65d41..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm deleted file mode 100755 index 7de5030..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep b/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep deleted file mode 100755 index 5451b22..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm deleted file mode 100755 index fbd3352..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm deleted file mode 100755 index dd14a7a..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans b/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans deleted file mode 100755 index a1aea4f..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake deleted file mode 100755 index f198f29..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm deleted file mode 100755 index e312a0b..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm deleted file mode 100755 index 9fe81a3..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/trans b/board/MAI/bios_emulator/scitech/bin-linux/libc/trans deleted file mode 100755 index e536c04..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/libc/trans and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat deleted file mode 100755 index 776d138..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat +++ /dev/null @@ -1,28 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 3.1. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC3;%BC3_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC3;%BC3_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC3_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC3.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_SNAP= -PATH %SCITECH_BIN%;%BC3_PATH%\BIN;%DEFPATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC3_PATH%\BIN\turboc.cfg -echo -L%LIB% >> %BC3_PATH%\BIN\turboc.cfg -echo -L%LIB% > %BC3_PATH%\BIN\tlink.cfg - -echo Borland C++ 3.1 DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat deleted file mode 100755 index d2939f4..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC4;%BC4_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC4;%BC4_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_VXD= -SET USE_TNT= -SET USE_BC5= -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC4 -PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto createfiles -call win32sdk.bat borland - -:createfiles -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg - -echo Borland C++ 4.5 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat deleted file mode 100755 index 246517d..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat +++ /dev/null @@ -1,32 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 4.5 in 16 bit mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC4;%BC4_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC4;%BC4_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_BC5= -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC4 -PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC4_PATH%\BIN\turboc.cfg -echo -L%LIB% >> %BC4_PATH%\BIN\turboc.cfg -echo -L%LIB% > %BC4_PATH%\BIN\tlink.cfg - -echo Borland C++ 4.5 16 bit DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat deleted file mode 100755 index cbb2c79..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat +++ /dev/null @@ -1,33 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 4.5 in 32 bit mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC4;%BC4_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC4;%BC4_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_TNT= -SET USE_BC5= -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC4 -PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg - -echo Borland C++ 4.5 32 bit DOS compilation configuration set up (DPMI32). diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat b/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat deleted file mode 100755 index 14d7c05..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat +++ /dev/null @@ -1,32 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BC4;%BC4_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BC4;%BC4_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_TNT= -SET USE_BC5= -SET WIN32_GUI= -SET USE_SNAP=1 -SET BC_LIBBASE=BC4 -PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg - -echo Borland C++ 4.5 Snap compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat deleted file mode 100755 index 50bd3cb..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat +++ /dev/null @@ -1,46 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 4.5 in 32 bit mode with Phar Lap TNT - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC4;%BC4_PATH%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC4;%BC4_PATH%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_TNT=1 -SET USE_BC5= -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC4 -PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH% - -REM If you set the following to a 1, a TNT DosStyle app will be created. -REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* -REM run under real DOS when using our libraries, since we require access -REM to functions that the Win32 API does not support (such as direct access -REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps -REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't -REM work too well). -REM -REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, -REM and hence will never be able to run under Win95 or WinNT, only DOS. - -SET DOSSTYLE= - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg - -echo Borland C++ 4.5 32 bit DOS compilation configuration set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat deleted file mode 100755 index 4b59fa4..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat +++ /dev/null @@ -1,32 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows VxD mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BC4;%BC4_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BC4;%BC4_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD=1 -SET USE_TNT= -SET USE_BC5= -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC4 -PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg - -echo Borland C++ 4.5 32-bit VxD compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat b/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat deleted file mode 100755 index 4d799b4..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat +++ /dev/null @@ -1,32 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 4.5 in 16 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BC4;%BC4_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BC4;%BC4_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK -SET USE_DPMI16= -SET USE_WIN16=1 -SET USE_WIN32= -SET USE_VXD= -SET USE_BC5= -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC4 -PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC4_PATH%\BIN\turboc.cfg -echo -L%LIB% >> %BC4_PATH%\BIN\turboc.cfg -echo -L%LIB% > %BC4_PATH%\BIN\tlink.cfg - -echo Borland C++ 4.5 16 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat deleted file mode 100755 index a6c199f..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC4;%BC4_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC4;%BC4_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_VXD= -SET USE_TNT= -SET USE_BC5= -SET WIN32_GUI=1 -SET USE_SNAP= -SET BC_LIBBASE=BC4 -PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto createfiles -call win32sdk.bat borland - -:createfiles -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg - -echo Borland C++ 4.5 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat deleted file mode 100755 index 6a0fde2..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat +++ /dev/null @@ -1,40 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET C_INCLUDE=%BC5_PATH%\INCLUDE -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto createfiles -call win32sdk.bat borland - -:createfiles -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg - -echo Borland C++ 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat deleted file mode 100755 index 23b5038..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 5.0 in 16 bit mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC5;%BC5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC5;%BC5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC5_PATH%\BIN\turboc.cfg -echo -L%LIB% >> %BC5_PATH%\BIN\turboc.cfg -echo -L%LIB% > %BC5_PATH%\BIN\tlink.cfg - -echo Borland C++ 5.0 16 bit DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat deleted file mode 100755 index 0521f93..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat +++ /dev/null @@ -1,35 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 5.0 in 32 bit mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC5;%BC5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC5;%BC5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg - -echo Borland C++ 5.0 32 bit DOS compilation configuration set up (DPMI32). diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat b/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat deleted file mode 100755 index e3241ff..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat +++ /dev/null @@ -1,35 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 5.0 in 32 bit mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\SMX32\BC5;%BC5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\SMX32\BC5;%BC5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32=1 -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg - -echo Borland C++ 5.0 32 bit SMX compilation configuration set up (SMX32). diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat b/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat deleted file mode 100755 index ab3acd2..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BC5;%BC5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BC5;%BC5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP=1 -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg - -echo Borland C++ 5.0 Snap compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat deleted file mode 100755 index 4dcc372..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat +++ /dev/null @@ -1,48 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 5.0 in 32 bit mode with Phar Lap TNT - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC5;%BC5_PATH%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC5;%BC5_PATH%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_TNT=1 -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH% - -REM If you set the following to a 1, a TNT DosStyle app will be created. -REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* -REM run under real DOS when using our libraries, since we require access -REM to functions that the Win32 API does not support (such as direct access -REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps -REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't -REM work too well). -REM -REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, -REM and hence will never be able to run under Win95 or WinNT, only DOS. - -SET DOSSTYLE= - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg - -echo Borland C++ 5.0 32 bit DOS compilation configuration set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat deleted file mode 100755 index 2356911..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BC5;%BC5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BC5;%BC5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD=1 -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg - -echo Borland C++ 5.0 32 bit Windows (VxD) compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat b/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat deleted file mode 100755 index cd79d86..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat +++ /dev/null @@ -1,34 +0,0 @@ - @echo off -REM Setup for compiling with Borland C++ 5.0 in 16 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BC5;%BC5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BC5;%BC5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK -SET USE_DPMI16= -SET USE_WIN16=1 -SET USE_WIN32= -SET USE_VXD= -SET USE_BC5=1 -SET USE_SMX32= -SET USE_SMX16= -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC5_PATH%\BIN\turboc.cfg -echo -L%LIB% >> %BC5_PATH%\BIN\turboc.cfg -echo -L%LIB% > %BC5_PATH%\BIN\tlink.cfg - -echo Borland C++ 5.0 16 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat deleted file mode 100755 index 8b8cec9..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat +++ /dev/null @@ -1,40 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET C_INCLUDE=%BC5_PATH%\INCLUDE -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI=1 -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto createfiles -call win32sdk.bat borland - -:createfiles -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg - -echo Borland C++ 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat b/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat deleted file mode 100755 index ebfeb2e..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI=1 -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg - -echo Borland C++ 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat deleted file mode 100755 index 6e09428..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat +++ /dev/null @@ -1,40 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET C_INCLUDE=%BCB5_PATH%\INCLUDE -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto createfiles -call win32sdk.bat borland - -:createfiles -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg - -echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat deleted file mode 100755 index aa13e7d..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ Builder 5.0 in 16 bit mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BCB5;%BCB5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BCB5;%BCB5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BCB5_PATH%\BIN\turboc.cfg -echo -L%LIB% >> %BCB5_PATH%\BIN\turboc.cfg -echo -L%LIB% > %BCB5_PATH%\BIN\tlink.cfg - -echo Borland C++ Builder 5.0 16 bit DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat deleted file mode 100755 index d0017d4..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat +++ /dev/null @@ -1,35 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BCB5;%BCB5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BCB5;%BCB5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg - -echo Borland C++ Builder 5.0 32 bit DOS compilation configuration set up (DPMI32). diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat deleted file mode 100755 index 2b969a9..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat +++ /dev/null @@ -1,35 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\SMX32\BCB5;%BCB5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\SMX32\BCB5;%BCB5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32=1 -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg - -echo Borland C++ Builder 5.0 32 bit SMX compilation configuration set up (SMX32). diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat deleted file mode 100755 index d7b8ff2..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BCB5;%BCB5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BCB5;%BCB5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP=1 -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg - -echo Borland C++ Builder 5.0 Snap compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat deleted file mode 100755 index 1de3601..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat +++ /dev/null @@ -1,48 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode with Phar Lap TNT - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BCB5;%BCB5_PATH%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BCB5;%BCB5_PATH%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_DPMI16= -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD= -SET USE_TNT=1 -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH% - -REM If you set the following to a 1, a TNT DosStyle app will be created. -REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* -REM run under real DOS when using our libraries, since we require access -REM to functions that the Win32 API does not support (such as direct access -REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps -REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't -REM work too well). -REM -REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, -REM and hence will never be able to run under Win95 or WinNT, only DOS. - -SET DOSSTYLE= - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg - -echo Borland C++ Builder 5.0 32 bit DOS compilation configuration set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat deleted file mode 100755 index 28de58c..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BCB5;%BCB5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BCB5;%BCB5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_VXD=1 -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg - -echo Borland C++ Builder 5.0 32 bit Windows (VxD) compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat deleted file mode 100755 index c30d004..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat +++ /dev/null @@ -1,34 +0,0 @@ - @echo off -REM Setup for compiling with Borland C++ Builder 5.0 in 16 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BCB5;%BCB5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BCB5;%BCB5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK -SET USE_DPMI16= -SET USE_WIN16=1 -SET USE_WIN32= -SET USE_VXD= -SET USE_BC5=1 -SET USE_SMX32= -SET USE_SMX16= -SET WIN32_GUI= -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BCB5_PATH%\BIN\turboc.cfg -echo -L%LIB% >> %BCB5_PATH%\BIN\turboc.cfg -echo -L%LIB% > %BCB5_PATH%\BIN\tlink.cfg - -echo Borland C++ Builder 5.0 16 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat deleted file mode 100755 index 18760e1..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat +++ /dev/null @@ -1,40 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET C_INCLUDE=%BCB5_PATH%\INCLUDE -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI=1 -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto createfiles -call win32sdk.bat borland - -:createfiles -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg - -echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat deleted file mode 100755 index 198c1a2..0000000 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_VXD= -SET USE_TNT= -SET USE_SMX32= -SET USE_SMX16= -SET USE_BC5=1 -SET WIN32_GUI=1 -SET USE_SNAP= -SET BC_LIBBASE=BC5 -PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% - -REM: Create Borland compile/link configuration scripts -echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg -echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg - -echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/build b/board/MAI/bios_emulator/scitech/bin/build deleted file mode 100755 index ff1973d..0000000 --- a/board/MAI/bios_emulator/scitech/bin/build +++ /dev/null @@ -1,22 +0,0 @@ -#! /bin/sh - -if [ $# -lt 1 ] || ( [ "$1" != gcc-linux ] && [ "$1" != qnx4 ] ) ; then - echo Usage: $0 compiler_name [DMAKE commands] - echo - echo Current compilers: - echo " gcc-linux - GNU C/C++ 2.7 or higher, 32 bit" - echo " qnx4 - Watcom C/C++ 10.6 or higher, 32 bit" - exit 1 -fi - -unset DBG OPT OPT_SIZE BUILD_DLL IMPORT_DLL FPU CHECKS BETA -. ${1}.sh - -shift -dmake $* && exit 0 - -echo ************************************************* -echo * An error occurred while building the library. * -echo ************************************************* -exit 1 - diff --git a/board/MAI/bios_emulator/scitech/bin/build.bat b/board/MAI/bios_emulator/scitech/bin/build.bat deleted file mode 100755 index ee29093..0000000 --- a/board/MAI/bios_emulator/scitech/bin/build.bat +++ /dev/null @@ -1,4 +0,0 @@ -@echo off -rem Disable checked build and build release code -set CHECKED= -call build_it.bat %1 %2 %3 %4 %5 %6 %7 %8 %9 diff --git a/board/MAI/bios_emulator/scitech/bin/build_db.bat b/board/MAI/bios_emulator/scitech/bin/build_db.bat deleted file mode 100755 index 2b32529..0000000 --- a/board/MAI/bios_emulator/scitech/bin/build_db.bat +++ /dev/null @@ -1,4 +0,0 @@ -@echo off -rem Enable checked build and build debug code -set CHECKED=1 -call build_it.bat %1 %2 %3 %4 %5 %6 %7 %8 %9 diff --git a/board/MAI/bios_emulator/scitech/bin/build_it.bat b/board/MAI/bios_emulator/scitech/bin/build_it.bat deleted file mode 100755 index 5a619b4..0000000 --- a/board/MAI/bios_emulator/scitech/bin/build_it.bat +++ /dev/null @@ -1,432 +0,0 @@ -@echo off -rem Generic batch file to build a version of the library. This batch file -rem assumes that the correct batch files exist to setup the appropriate -rem compilation environments, and that the DMAKE.EXE program is available -rem somewhere on the path. -rem -rem Builds as release or debug depending on the value of the CHECKED -rem environment variable. - -rem Unset all environment variables that change the compile process -set DBG= -set OPT= -set OPT_SIZE= -set BUILD_DLL= -set IMPORT_DLL= -set FPU= -set CHECKS= -set BETA= - -if %1==bc31-d16 goto bc31-d16 -if %1==bc45-d16 goto bc45-d16 -if %1==bc45-d32 goto bc45-d32 -if %1==bc45-tnt goto bc45-tnt -if %1==bc45-w16 goto bc45-w16 -if %1==bc45-w32 goto bc45-w32 -if %1==bc45-c32 goto bc45-c32 -if %1==bc45-vxd goto bc45-vxd -if %1==bc45-snp goto bc45-snp -if %1==bc50-d16 goto bc50-d16 -if %1==bc50-d32 goto bc50-d32 -if %1==bc50-tnt goto bc50-tnt -if %1==bc50-w16 goto bc50-w16 -if %1==bc50-w32 goto bc50-w32 -if %1==bc50-c32 goto bc50-c32 -if %1==bc50-vxd goto bc50-vxd -if %1==bc50-snp goto bc50-snp -if %1==gcc2-d32 goto gcc2-d32 -if %1==gcc2-w32 goto gcc2-w32 -if %1==gcc2-c32 goto gcc2-c32 -if %1==gcc2-linux goto gcc2-linux -if %1==vc40-d16 goto vc40-d16 -if %1==vc40-tnt goto vc40-tnt -if %1==vc40-w16 goto vc40-w16 -if %1==vc40-w32 goto vc40-w32 -if %1==vc40-c32 goto vc40-c32 -if %1==vc40-drv9x goto vc40-drv9x -if %1==vc40-drvnt goto vc40-drvnt -if %1==vc40-rtt goto vc40-rtt -if %1==vc40-snp goto vc40-snp -if %1==vc50-d16 goto vc50-d16 -if %1==vc50-tnt goto vc50-tnt -if %1==vc50-w16 goto vc50-w16 -if %1==vc50-w32 goto vc50-w32 -if %1==vc50-c32 goto vc50-c32 -if %1==vc50-drv9x goto vc50-drv9x -if %1==vc50-drvnt goto vc50-drvnt -if %1==vc50-rtt goto vc50-rtt -if %1==vc50-snp goto vc50-snp -if %1==vc60-d16 goto vc60-d16 -if %1==vc60-tnt goto vc60-tnt -if %1==vc60-w16 goto vc60-w16 -if %1==vc60-w32 goto vc60-w32 -if %1==vc60-c32 goto vc60-c32 -if %1==vc60-drv9x goto vc60-drv9x -if %1==vc60-drvnt goto vc60-drvnt -if %1==vc60-drvw2k goto vc60-drvw2k -if %1==vc60-rtt goto vc60-rtt -if %1==vc60-snp goto vc60-snp -if %1==wc10ad16 goto wc10ad16 -if %1==wc10ad32 goto wc10ad32 -if %1==wc10atnt goto wc10atnt -if %1==wc10aw16 goto wc10aw16 -if %1==wc10aw32 goto wc10aw32 -if %1==wc10ac32 goto wc10ac32 -if %1==wc10ao32 goto wc10ao32 -if %1==wc10ap32 goto wc10ap32 -if %1==wc10asnp goto wc10asnp -if %1==wc10-d16 goto wc10-d16 -if %1==wc10-d32 goto wc10-d32 -if %1==wc10-tnt goto wc10-tnt -if %1==wc10-w16 goto wc10-w16 -if %1==wc10-w32 goto wc10-w32 -if %1==wc10-c32 goto wc10-c32 -if %1==wc10-o32 goto wc10-o32 -if %1==wc10-p32 goto wc10-p32 -if %1==wc10-snp goto wc10-snp -if %1==wc11-d16 goto wc11-d16 -if %1==wc11-d32 goto wc11-d32 -if %1==wc11-tnt goto wc11-tnt -if %1==wc11-w16 goto wc11-w16 -if %1==wc11-w32 goto wc11-w32 -if %1==wc11-c32 goto wc11-c32 -if %1==wc11-o32 goto wc11-o32 -if %1==wc11-p32 goto wc11-p32 -if %1==wc11-snp goto wc11-snp - -echo Usage: BUILD 'compiler_name' [DMAKE commands] -echo. -echo Where 'compiler_name' is of the form comp-os, where -echo 'comp' defines the compiler and 'os' defines the OS environment. -echo For instance 'bc50-w32' is for Borland C++ 5.0 for Win32. -echo The value of 'comp' can be any of the following: -echo. -echo bc45 - Borland C++ 4.5x -echo bc50 - Borland C++ 5.x -echo vc40 - Visual C++ 4.x -echo vc50 - Visual C++ 5.x -echo vc60 - Visual C++ 6.x -echo wc10 - Watcom C++ 10.6 -echo wc11 - Watcom C++ 11.0 -echo gcc2 - GNU C/C++ 2.9x -echo. -echo The value of 'os' can be one of the following: -echo. -echo d16 - 16-bit DOS -echo d32 - 32-bit DOS -echo w16 - 16-bit Windows GUI mode -echo c32 - 32-bit Windows console mode -echo w32 - 32-bit Windows GUI mode -echo o16 - 16-bit OS/2 console mode -echo o32 - 32-bit OS/2 console mode -echo p32 - 32-bit OS/2 Presentation Manager -echo snp - 32-bit SciTech Snap application -echo linux - 32-bit Linux application -goto end - -rem ------------------------------------------------------------------------- -rem Setup for the specified compiler - -:bc31-d16 -call bc31-d16.bat -goto compileit - -:bc45-d16 -call bc45-d16.bat -goto compileit - -:bc45-d32 -call bc45-d32.bat -goto compileit - -:bc45-tnt -call bc45-tnt.bat -goto compileit - -:bc45-w16 -call bc45-w16.bat -goto compileit - -:bc45-w32 -call bc45-w32.bat -goto compileit - -:bc45-c32 -call bc45-c32.bat -goto compileit - -:bc45-vxd -call bc45-vxd.bat -goto compileit - -:bc50-d16 -call bc50-d16.bat -goto compileit - -:bc50-d32 -call bc50-d32.bat -goto compileit - -:bc50-tnt -call bc50-tnt.bat -goto compileit - -:bc50-w16 -call bc50-w16.bat -goto compileit - -:bc50-w32 -call bc50-w32.bat -goto compileit - -:bc50-c32 -call bc50-c32.bat -goto compileit - -:bc50-vxd -call bc50-vxd.bat -goto compileit - -:gcc2-d32 -call gcc2-d32.bat -goto compileit - -:gcc2-w32 -call gcc2-w32.bat -goto compileit - -:gcc2-c32 -call gcc2-c32.bat -goto compileit - -:gcc2-linux -call gcc2-linux.bat -goto compileit - -:sc70-d16 -call sc70-d16.bat -goto compileit - -:sc70-w16 -call sc70-w16.bat -goto compileit - -:sc70-tnt -call sc70-tnt.bat -goto compileit - -:sc70-w32 -call sc70-w32.bat -goto compileit - -:sc70-c32 -call sc70-c32.bat -goto compileit - -:vc40-d16 -call vc40-d16.bat -goto compileit - -:vc40-tnt -call vc40-tnt.bat -goto compileit - -:vc40-w16 -call vc40-w16.bat -goto compileit - -:vc40-w32 -call vc40-w32.bat -goto compileit - -:vc40-c32 -call vc40-c32.bat -goto compileit - -:vc40-drv9x -call vc40-drv9x.bat -goto compileit - -:vc40-drvnt -call vc40-drvnt.bat -goto compileit - -:vc40-rtt -call vc40-rtt.bat -goto compileit - -:vc50-d16 -call vc50-d16.bat -goto compileit - -:vc50-tnt -call vc50-tnt.bat -goto compileit - -:vc50-w16 -call vc50-w16.bat -goto compileit - -:vc50-w32 -call vc50-w32.bat -goto compileit - -:vc50-c32 -call vc50-c32.bat -goto compileit - -:vc50-drv9x -call vc50-drv9x.bat -goto compileit - -:vc50-drvnt -call vc50-drvnt.bat -goto compileit - -:vc50-rtt -call vc50-rtt.bat -goto compileit - -:vc60-d16 -call vc60-d16.bat -goto compileit - -:vc60-tnt -call vc60-tnt.bat -goto compileit - -:vc60-w16 -call vc60-w16.bat -goto compileit - -:vc60-w32 -call vc60-w32.bat -goto compileit - -:vc60-c32 -call vc60-c32.bat -goto compileit - -:vc60-drv9x -call vc60-drv9x.bat -goto compileit - -:vc60-drvnt -call vc60-drvnt.bat -goto compileit - -:vc60-drvw2k -call vc60-drvw2k.bat -goto compileit - -:vc60-rtt -call vc60-rtt.bat -goto compileit - -:wc10ad16 -call wc10ad16.bat -goto compileit - -:wc10ad32 -call wc10ad32.bat -goto compileit - -:wc10atnt -call wc10atnt.bat -goto compileit - -:wc10aw16 -call wc10aw16.bat -goto compileit - -:wc10aw32 -call wc10aw32.bat -goto compileit - -:wc10ac32 -call wc10ac32.bat -goto compileit - -:wc10ao32 -call wc10ao32.bat -goto compileit - -:wc10ap32 -call wc10ap32.bat -goto compileit - -:wc10-d16 -call wc10-d16.bat -goto compileit - -:wc10-d32 -call wc10-d32.bat -goto compileit - -:wc10-tnt -call wc10-tnt.bat -goto compileit - -:wc10-w16 -call wc10-w16.bat -goto compileit - -:wc10-w32 -call wc10-w32.bat -goto compileit - -:wc10-c32 -call wc10-c32.bat -goto compileit - -:wc10-o32 -call wc10-o32.bat -goto compileit - -:wc10-p32 -call wc10-p32.bat -goto compileit - -:wc11-d16 -call wc11-d16.bat -goto compileit - -:wc11-d32 -call wc11-d32.bat -goto compileit - -:wc11-tnt -call wc11-tnt.bat -goto compileit - -:wc11-w16 -call wc11-w16.bat -goto compileit - -:wc11-w32 -call wc11-w32.bat -goto compileit - -:wc11-c32 -call wc11-c32.bat -goto compileit - -:wc11-o32 -call wc11-o32.bat -goto compileit - -:wc11-p32 -call wc11-p32.bat -goto compileit - -:compileit -k_rm -f *.lib *.a -dmake %2 %3 %4 %5 %6 %7 %8 %9 -if errorlevel 1 goto errorend -goto end - -:errorend -echo ************************************************* -echo * An error occurred while building the library. * -echo ************************************************* -:end diff --git a/board/MAI/bios_emulator/scitech/bin/cddrv.bat b/board/MAI/bios_emulator/scitech/bin/cddrv.bat deleted file mode 100755 index b64f4d7..0000000 --- a/board/MAI/bios_emulator/scitech/bin/cddrv.bat +++ /dev/null @@ -1,6 +0,0 @@ -@echo off -%1 -cd %3 -%4 %5 %6 %7 %8 %9 -%2 - diff --git a/board/MAI/bios_emulator/scitech/bin/cdit b/board/MAI/bios_emulator/scitech/bin/cdit deleted file mode 100755 index b22023d..0000000 --- a/board/MAI/bios_emulator/scitech/bin/cdit +++ /dev/null @@ -1,10 +0,0 @@ -#! /bin/sh - -cd $1 -PROG=$2 -shift 2 -rm -f *.lib *.a -$PROG $* -RET=$? -cd .. -exit $RET diff --git a/board/MAI/bios_emulator/scitech/bin/cdit.bat b/board/MAI/bios_emulator/scitech/bin/cdit.bat deleted file mode 100755 index 950b648..0000000 --- a/board/MAI/bios_emulator/scitech/bin/cdit.bat +++ /dev/null @@ -1,5 +0,0 @@ -@echo off -cd %1 -k_rm -f *.lib *.a -shift 1 -%1 %2 %3 %4 %5 %6 %7 %8 %9 diff --git a/board/MAI/bios_emulator/scitech/bin/djgpp.env b/board/MAI/bios_emulator/scitech/bin/djgpp.env deleted file mode 100644 index 5a2c3d8..0000000 --- a/board/MAI/bios_emulator/scitech/bin/djgpp.env +++ /dev/null @@ -1,46 +0,0 @@ -#= Don't edit this line unless you move djgpp.env outside -#= of the djgpp installation directory. If you do move -#= it, set DJDIR to the directory you installed DJGPP in. -#= -DJDIR=%:/>DJGPP% - -+USER=dosuser -+TMPDIR=%DJDIR%/tmp -+EMU387=%DJDIR%/bin/emu387.dxe -+LFN=y - -[bison] -BISON_HAIRY=%DJDIR%/lib/bison.hai -BISON_SIMPLE=%DJDIR%/lib/bison.sim - -[cpp] -CPLUS_INCLUDE_PATH=%/>;CPLUS_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/lang/cxx;%DJDIR%/include;%DJDIR%/contrib/grx20/include -C_INCLUDE_PATH=%/>;C_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/include;%DJDIR%/contrib/grx20/include -OBJCPLUS_INCLUDE_PATH=%/>;OBJCPLUS_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc -OBJC_INCLUDE_PATH=%/>;OBJC_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc - -[gcc] -COMPILER_PATH=%/>;COMPILER_PATH%%DJDIR%/bin -LIBRARY_PATH=%/>;LIBRARY_PATH%%DJDIR%/lib;%DJDIR%/contrib/grx20/lib;%SCITECH%/lib/release/dos32/dj2 - -[info] -INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info -INFO_COLORS=0x1f.0x31 - -[emacs] -INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info - -[less] -LESSBINFMT=*k<%X> -LESSCHARDEF=8bcccbcc12bc5b95.b127.b -LESS=%LESS% -h5$y5$Dd2.0$Du14.0$Ds4.7$Dk9.0$ - -[locate] -+LOCATE_PATH=%DJDIR%/lib/locatedb.dat - -[ls] -+LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: -[dir] -+LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: -[vdir] -+LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: diff --git a/board/MAI/bios_emulator/scitech/bin/djgpp_db.env b/board/MAI/bios_emulator/scitech/bin/djgpp_db.env deleted file mode 100644 index 9b792c9..0000000 --- a/board/MAI/bios_emulator/scitech/bin/djgpp_db.env +++ /dev/null @@ -1,46 +0,0 @@ -#= Don't edit this line unless you move djgpp.env outside -#= of the djgpp installation directory. If you do move -#= it, set DJDIR to the directory you installed DJGPP in. -#= -DJDIR=%:/>DJGPP% - -+USER=dosuser -+TMPDIR=%DJDIR%/tmp -+EMU387=%DJDIR%/bin/emu387.dxe -+LFN=y - -[bison] -BISON_HAIRY=%DJDIR%/lib/bison.hai -BISON_SIMPLE=%DJDIR%/lib/bison.sim - -[cpp] -CPLUS_INCLUDE_PATH=%/>;CPLUS_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/lang/cxx;%DJDIR%/include;%DJDIR%/contrib/grx20/include -C_INCLUDE_PATH=%/>;C_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/include;%DJDIR%/contrib/grx20/include -OBJCPLUS_INCLUDE_PATH=%/>;OBJCPLUS_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc -OBJC_INCLUDE_PATH=%/>;OBJC_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc - -[gcc] -COMPILER_PATH=%/>;COMPILER_PATH%%DJDIR%/bin -LIBRARY_PATH=%/>;LIBRARY_PATH%%DJDIR%/lib;%DJDIR%/contrib/grx20/lib;%SCITECH%/lib/debug/dos32/dj2 - -[info] -INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info -INFO_COLORS=0x1f.0x31 - -[emacs] -INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info - -[less] -LESSBINFMT=*k<%X> -LESSCHARDEF=8bcccbcc12bc5b95.b127.b -LESS=%LESS% -h5$y5$Dd2.0$Du14.0$Ds4.7$Dk9.0$ - -[locate] -+LOCATE_PATH=%DJDIR%/lib/locatedb.dat - -[ls] -+LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: -[dir] -+LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: -[vdir] -+LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: diff --git a/board/MAI/bios_emulator/scitech/bin/findint3.bat b/board/MAI/bios_emulator/scitech/bin/findint3.bat deleted file mode 100755 index 2e1506c..0000000 --- a/board/MAI/bios_emulator/scitech/bin/findint3.bat +++ /dev/null @@ -1 +0,0 @@ -perl c:\scitech\src\perl\findint3.per diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh b/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh deleted file mode 100755 index 61ffd93..0000000 --- a/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh +++ /dev/null @@ -1,16 +0,0 @@ -#! /bin/sh - -# Setup for compiling with GCC/G++ for BeOS - -if [ "$CHECKED" = "1" ]; then - echo Checked debug build enabled. -else - echo Release build enabled. -fi - -export MAKESTARTUP=$SCITECH/makedefs/gcc_beos.mk -export INCLUDE="-Iinclude -I$SCITECH/include -I$PRIVATE/include" -export USE_X11=0 -export USE_BEOS=1 - -echo GCC BeOS console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh b/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh deleted file mode 100755 index 3816a5d..0000000 --- a/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh +++ /dev/null @@ -1,16 +0,0 @@ -#! /bin/sh - -# Setup for compiling with GCC/G++ for FreeBSD - -if [ "$CHECKED" = "1" ]; then - echo Checked debug build enabled. -else - echo Release build enabled. -fi - -export MAKESTARTUP=$SCITECH/makedefs/gcc_freebsd.mk -export INCLUDE="-Iinclude -I$SCITECH/include -I$PRIVATE/include" -export USE_X11=1 -export USE_FREEBSD=1 - -echo GCC FreeBSD console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh b/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh deleted file mode 100755 index 27a4c49..0000000 --- a/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh +++ /dev/null @@ -1,19 +0,0 @@ -#! /bin/sh - -# Setup for compiling with GCC/G++ for Linux - -if [ "$CHECKED" = "1" ]; then - echo Checked debug build enabled. -else - echo Release build enabled. -fi - -export MAKESTARTUP=$SCITECH/makedefs/gcc_linux.mk -export INCLUDE="include;$SCITECH/include;$PRIVATE/include" -export USE_LINUX=1 - -if [ "x$LIBC" = x ]; then - echo "GCC Linux console compilation environment set up (glib)" -else - echo "GCC Linux console compilation environment set up (libc5)" -fi diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat deleted file mode 100755 index 13c4783..0000000 --- a/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat +++ /dev/null @@ -1,26 +0,0 @@ -@echo off -REM Setup for compiling with GNU C compiler - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2 -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2 -echo Checked debug build enabled. -goto setvars - -:setvars -set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include -set MAKESTARTUP=%SCITECH%\makedefs\gcc_win32.mk -set MAKE_MODE= -set USE_WIN16= -set USE_WIN32=1 -set WIN32_GUI= -set USE_SNAP= -set GCC_LIBBASE=gcc2 -PATH %SCITECH_BIN%;%GCC2_PATH%\NATIVE\BIN;%DEFPATH% - -echo GCC 2.9.x 32-bit Win32 console compilation environment set up - diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat deleted file mode 100755 index 97cb8bd..0000000 --- a/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat +++ /dev/null @@ -1,28 +0,0 @@ -@echo off -REM Setup for compiling with DJGPP 2.02 - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\release\dos32\dj2 -%SCITECH%\bin-dos\k_cp %SCITECH%\BIN\DJGPP.ENV %DJ_PATH%\DJGPP.ENV -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\debug\dos32\dj2 -%SCITECH%\bin-dos\k_cp %SCITECH%\BIN\DJGPP_DB.ENV %DJ_PATH%\DJGPP.ENV -echo Checked debug build enabled. -goto setvars - -:setvars -set DJGPP=%DJ_PATH%\DJGPP.ENV -set INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%DJ_PATH%\INCLUDE; -set MAKESTARTUP=%SCITECH%\MAKEDEFS\DJ32.MK -set USE_WIN16= -set USE_WIN32= -set WIN32_GUI= -set USE_SNAP= -set DJ_LIBBASE=dj2 -PATH %SCITECH_BIN%;%DJ_PATH%\BIN;%DEFPATH% - -echo DJGPP 2.02 32-bit DOS compilation environment set up (DPMI). - diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat deleted file mode 100755 index ceb2ab8..0000000 --- a/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat +++ /dev/null @@ -1,26 +0,0 @@ -@echo off -REM Setup for compiling with GNU C cross-compiler - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2 -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2 -echo Checked debug build enabled. -goto setvars - -:setvars -set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include -set MAKESTARTUP=%SCITECH%\MAKEDEFS\gcc_linux.mk -set MAKE_MODE=UNIX -set USE_WIN16= -set USE_WIN32= -set WIN32_GUI= -set USE_SNAP= -set GCC_LIBBASE=gcc2 -PATH %SCITECH_BIN%;%GCC2_PATH%\cross-linux\i386-redhat-linux\BIN;%DEFPATH% - -echo GCC 2.9.x 32-bit Linux console cross compilation environment set up - diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat deleted file mode 100755 index bdb31aa..0000000 --- a/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat +++ /dev/null @@ -1,26 +0,0 @@ -@echo off -REM Setup for compiling with GNU C compiler - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2 -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2 -echo Checked debug build enabled. -goto setvars - -:setvars -set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include -set MAKESTARTUP=%SCITECH%\makedefs\gcc_win32.mk -set MAKE_MODE= -set USE_WIN16= -set USE_WIN32=1 -set WIN32_GUI=1 -set USE_SNAP= -set GCC_LIBBASE=gcc2 -PATH %SCITECH_BIN%;%GCC2_PATH%\NATIVE\BIN;%DEFPATH% - -echo GCC 2.9.x 32-bit Win32 GUI compilation environment set up - diff --git a/board/MAI/bios_emulator/scitech/bin/makelib.bat b/board/MAI/bios_emulator/scitech/bin/makelib.bat deleted file mode 100755 index 6316734..0000000 --- a/board/MAI/bios_emulator/scitech/bin/makelib.bat +++ /dev/null @@ -1,97 +0,0 @@ -call wc11-d32.bat - -cd c:\private\src\license -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\pm -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\console -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\nucleus -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\zlib -dmake clean -dmake depend -dmake -u install - -cd c:\private\src\graphics\ref2d -dmake clean -dmake depend -dmake -u install -cd c:\private\src\drvlib -dmake clean -dmake depend -dmake -u install - -call wc11-w32.bat - -cd c:\private\src\license -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\pm -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\console -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\nucleus -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\zlib -dmake clean -dmake depend -dmake -u install - -cd c:\private\src\graphics\ref2d -dmake clean -dmake depend -dmake -u install -cd c:\private\src\drvlib -dmake clean -dmake depend -dmake -u install - -call wc10-d32.bat - -cd c:\private\src\license -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\pm -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\console -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\nucleus -dmake clean -dmake depend -dmake -u install -cd c:\scitech\src\zlib -dmake clean -dmake depend -dmake -u install - -cd c:\private\src\graphics\ref2d -dmake clean -dmake depend -dmake -u install -cd c:\private\src\drvlib -dmake clean -dmake depend -dmake -u install - -cd \private\src\graphics\drivers diff --git a/board/MAI/bios_emulator/scitech/bin/meltobjs.sh b/board/MAI/bios_emulator/scitech/bin/meltobjs.sh deleted file mode 100755 index fd1804b..0000000 --- a/board/MAI/bios_emulator/scitech/bin/meltobjs.sh +++ /dev/null @@ -1,23 +0,0 @@ -#! /bin/sh -# -# This script generates a single object file from a set of libraries (*.a files) -# Usage: meltobjs.sh target.o library1.a library2.a ... -# -# (C) SciTech Software, Inc. 1998 -# - -TMPDIR=/tmp/melt$$ -TARGET=$1 -TARGETDIR=$PWD -shift -mkdir $TMPDIR - -cd $TMPDIR - -for a in $* -do - ar x $a -done -ld -r -o $TARGETDIR/$TARGET *.o - -rm -fr $TMPDIR \ No newline at end of file diff --git a/board/MAI/bios_emulator/scitech/bin/ntddk.bat b/board/MAI/bios_emulator/scitech/bin/ntddk.bat deleted file mode 100755 index 07c0d78..0000000 --- a/board/MAI/bios_emulator/scitech/bin/ntddk.bat +++ /dev/null @@ -1,42 +0,0 @@ -@echo off -REM: Set up environment variables for Microsoft Windows NT DDK development. -REM: Note that we have hard coded this for Windows NT i386 development. - -SET USE_NTDRV=1 -SET USE_W2KDRV= -SET BASEDIR=%NT_DDKROOT% -SET PATH=%BASEDIR%\bin;%PATH% -SET NTMAKEENV=%BASEDIR%\inc -SET BUILD_MAKE_PROGRAM=nmake.exe -SET BUILD_DEFAULT=-ei -nmake -i -SET BUILD_DEFAULT_TARGETS=-386 -SET _OBJ_DIR=obj -SET NEW_CRTS=1 -SET _NTROOT=%BASEDIR% -SET INCLUDE=%BASEDIR%\inc;%INCLUDE% - -if .%CHECKED%==.1 goto checked - -REM: set up an NT free build environment -SET DDKBUILDENV=free -SET C_DEFINES=-D_IDWBUILD -SET NTDBGFILES=1 -SET NTDEBUG= -SET NTDEBUGTYPE= -SET MSC_OPTIMIZATION= -set LIB=%BASEDIR%\lib\i386\free;%SCITECH_LIB%\LIB\RELEASE\NTDRV\VC6;%MSVCDir%\LIB;. - -goto done - -:checked - -REM: set up an NT checked build environment -SET DDKBUILDENV=checked -SET C_DEFINES=-D_IDWBUILD -DRDRDBG -DSRVDBG -SET NTDBGFILES= -SET NTDEBUG=ntsd -SET NTDEBUGTYPE=both -SET MSC_OPTIMIZATION=/Od /Oi -set LIB=%BASEDIR%\lib\i386\free;%SCITECH_LIB%\LIB\DEBUG\NTDRV\VC6;%MSVCDir%\LIB;. - -:done diff --git a/board/MAI/bios_emulator/scitech/bin/qnx4.sh b/board/MAI/bios_emulator/scitech/bin/qnx4.sh deleted file mode 100755 index 843c4d9..0000000 --- a/board/MAI/bios_emulator/scitech/bin/qnx4.sh +++ /dev/null @@ -1,18 +0,0 @@ -#! /bin/sh - -# Setup for compiling with Watcom C/C++ for QNX4 - -if [ "$CHECKED" = "1" ]; then - echo Checked debug build enabled. -else - echo Release build enabled. -fi - -export MAKESTARTUP=$SCITECH/makedefs/qnx4.mk -export INCLUDE="-I$SCITECH/include -I$PRIVATE/include -I/usr/include" -export USE_QNX=1 -export USE_QNX4=1 -export WC_LIBBASE=wc10 - -echo Qnx 4 console compilation environment set up - diff --git a/board/MAI/bios_emulator/scitech/bin/qnxnto.sh b/board/MAI/bios_emulator/scitech/bin/qnxnto.sh deleted file mode 100755 index c114f9e..0000000 --- a/board/MAI/bios_emulator/scitech/bin/qnxnto.sh +++ /dev/null @@ -1,21 +0,0 @@ -#! /bin/sh - -# Setup for compiling with Watcom C/C++ for QNX Neutrino - -if [ "$CHECKED" = "1" ]; then - echo Checked debug build enabled. -else - echo Release build enabled. -fi - -if [ X$GCC_PATH = "X" ]; then - export GCC_PATH=/usr/gcc/bin -fi - -export MAKESTARTUP=$SCITECH/makedefs/qnxnto.mk -export INCLUDE="-I$SCITECH/include -I$PRIVATE/include -I/usr/nto/include" -export USE_BIOS=1 # VBIOS lib is tiny under Neutrino, always include it -export USE_QNX=1 -export USE_QNXNTO=1 - -echo Qnx Neutrino console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh deleted file mode 100755 index 0a272d6..0000000 --- a/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh +++ /dev/null @@ -1,42 +0,0 @@ -#! /bin/sh - -# BeOS VERSION -# Set the place where SciTech Software is installed, and where each -# of the supported compilers is installed. These environment variables -# are used by the batch files in the SCITECH\BIN directory. -# -# Modify the as appropriate for your compiler configuration (you should -# only need to change things in this batch file). -# -# This version is for a normal BeOS installation. - -# The SCITECH variable points to where batch files, makefile startups, -# include files and source files will be found when compiling. - -export SCITECH=$MGL_ROOT - -# The SCITECH_LIB variable points to where the SciTech libraries live -# for installation and linking. This allows you to have the source and -# include files on local machines for compiling and have the libraries -# located on a common network machine (for network builds). - -export SCITECH_LIB=$SCITECH - -# The PRIVATE variable points to where private source files reside that -# do not live in the public source tree - -export PRIVATE=$HOME/private - -# The following define the locations of all the compilers that you may -# be using. Change them to reflect where you have installed your -# compilers. - -export GCC_PATH=/boot/develop/tools/gnupro/bin - -# Add the Scitech bin path to the current PATH -export PATH=$SCITECH/bin:$SCITECH/bin-beos:$PATH -#if [ "x$LIBC" = x ]; then -# export PATH=$PATH:$SCITECH/bin-beos/glibc -#else -# export PATH=$PATH:$SCITECH/bin-beos/libc -#fi diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh deleted file mode 100755 index c920748..0000000 --- a/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh +++ /dev/null @@ -1,37 +0,0 @@ -#! /bin/sh - -# LINUX VERSION -# Set the place where SciTech Software is installed, and where each -# of the supported compilers is installed. These environment variables -# are used by the batch files in the SCITECH\BIN directory. -# -# Modify the as appropriate for your compiler configuration (you should -# only need to change things in this batch file). -# -# This version is for a normal Linux installation. - -# The SCITECH variable points to where batch files, makefile startups, -# include files and source files will be found when compiling. - -export SCITECH=$MGL_ROOT - -# The SCITECH_LIB variable points to where the SciTech libraries live -# for installation and linking. This allows you to have the source and -# include files on local machines for compiling and have the libraries -# located on a common network machine (for network builds). - -export SCITECH_LIB=$SCITECH - -# The PRIVATE variable points to where private source files reside that -# do not live in the public source tree - -export PRIVATE=$HOME/private - -# The following define the locations of all the compilers that you may -# be using. Change them to reflect where you have installed your -# compilers. - -export GCC_PATH=/usr/bin - -# Add the Scitech bin path to the current PATH -export PATH=$SCITECH/bin:$SCITECH/bin-freebsd:$PATH diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh deleted file mode 100755 index 35cbf1d..0000000 --- a/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh +++ /dev/null @@ -1,43 +0,0 @@ -#! /bin/sh - -# LINUX VERSION -# Set the place where SciTech Software is installed, and where each -# of the supported compilers is installed. These environment variables -# are used by the batch files in the SCITECH\BIN directory. -# -# Modify the as appropriate for your compiler configuration (you should -# only need to change things in this batch file). -# -# This version is for a normal Linux installation. - -# The SCITECH variable points to where batch files, makefile startups, -# include files and source files will be found when compiling. - -export SCITECH=$MGL_ROOT - -# The SCITECH_LIB variable points to where the SciTech libraries live -# for installation and linking. This allows you to have the source and -# include files on local machines for compiling and have the libraries -# located on a common network machine (for network builds). - -export SCITECH_LIB=$SCITECH - -# The PRIVATE variable points to where private source files reside that -# do not live in the public source tree - -export PRIVATE=$HOME/private - -# The following define the locations of all the compilers that you may -# be using. Change them to reflect where you have installed your -# compilers. - -export GCC_PATH=/usr/bin -export TEMP=/tmp TMP=/tmp - -# Add the Scitech bin path to the current PATH -export PATH=$SCITECH/bin:$SCITECH/bin-linux:$PATH -if [ "x$LIBC" = x ]; then - export PATH=$SCITECH/bin-linux/glibc:$PATH -else - export PATH=$SCITECH/bin-linux/libc:$PATH -fi diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh deleted file mode 100755 index 1d73109..0000000 --- a/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh +++ /dev/null @@ -1,37 +0,0 @@ -#! /bin/sh - -# QNX 4 VERSION -# Set the place where SciTech Software is installed, and where each -# of the supported compilers is installed. These environment variables -# are used by the batch files in the SCITECH\BIN directory. -# -# Modify the as appropriate for your compiler configuration (you should -# only need to change things in this batch file). -# -# This version is for a normal Linux installation. - -# The SCITECH variable points to where batch files, makefile startups, -# include files and source files will be found when compiling. - -export SCITECH=$MGL_ROOT - -# The SCITECH_LIB variable points to where the SciTech libraries live -# for installation and linking. This allows you to have the source and -# include files on local machines for compiling and have the libraries -# located on a common network machine (for network builds). - -export SCITECH_LIB=$SCITECH - -# The PRIVATE variable points to where private source files reside that -# do not live in the public source tree - -export PRIVATE=$HOME/private - -# The following define the locations of all the compilers that you may -# be using. Change them to reflect where you have installed your -# compilers. - -export WC10_PATH=/usr/watcom/10.6/usr - -# Add the Scitech bin path to the current PATH -export PATH=$SCITECH/bin:$SCITECH/bin-qnx:$PATH diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars.bat b/board/MAI/bios_emulator/scitech/bin/set-vars.bat deleted file mode 100755 index 2a2101d..0000000 --- a/board/MAI/bios_emulator/scitech/bin/set-vars.bat +++ /dev/null @@ -1,110 +0,0 @@ -@echo off -REM:========================================================================= -REM: Master batch file to set up all necessary environment variables for -REM: the SciTech makefile utilities. This batch file should be executed -REM: *first* before any other batch files when you start a command shell. -REM: You should not need to modify any batch files except this one to -REM: configure the makefile utilities. -REM:========================================================================= - -REM: Set the place where SciTech Software is installed, and where each -REM: of the supported compilers is installed. These environment variables -REM: are used by the batch files in the SCITECH\BIN directory. -REM: -REM: Modify the as appropriate for your compiler configuration (you should -REM: only need to change things in this batch file). -REM: -REM: This version is for a normal MSDOS installation. - -REM: The SCITECH variable points to where batch files, makefile startups, -REM: include files and source files will be found when compiling. - -SET SCITECH=c:\scitech - -REM: The SCITECH_LIB variable points to where the SciTech libraries live -REM: for installation and linking. This allows you to have the source and -REM: include files on local machines for compiling and have the libraries -REM: located on a common network machine (for network builds). - -SET SCITECH_LIB=%SCITECH% - -REM: The PRIVATE variable points to where private source files reside that -REM: do not live in the public source tree - -SET PRIVATE=c:\private - -REM: The following sets up the path to the SciTech command line utilities -REM: for the development operating system. We select either DOS hosted -REM: tools or Win32 hosted tools depending on whether you are running -REM: on NT or not. Windows 9x users can use the Win32 hosted tools but -REM: they run slower, but you will have long filenames if you do this. - -IF .%OS%==.Windows_NT goto Win32_path -IF NOT .%WINDIR%==. goto Win32_path -SET SCITECH_BIN=%SCITECH%\bin;%SCITECH%\bin-dos -goto path_set - -REM: The following sets up the path to the SciTech command line utilities -REM: for the development operating system. This version uses the Win32 -REM: hosted tools by default, so you can use long filenames. - -:Win32_path -SET SCITECH_BIN=%SCITECH%\bin;%SCITECH%\bin-win32 - -:path_set - -REM: Set the TMP variable for dmake if this is not already set - -SET TMP=%SCITECH% - -REM: Set the following environment variable to use the Netwide Assembler -REM: (NASM) provided with the MGL tools to build all assembler modules. -REM: If you have Turbo Assembler 4.0 or later and you wish to use it, -REM: you can use it by removing the following line. - -SET USE_NASM=1 - -REM: The following is used to set up DDK directories for device driver -REM: development. They can safely be ignored unless you are using the -REM: SciTech makefile utilities to build device drivers. - -SET DDKDRIVE=c: -SET MSSDK=c:\c\win32sdk -SET W95_DDKROOT=c:\c\95ddk -SET W98_DDKROOT=c:\c\98ddk -SET NT_DDKROOT=c:\c\ntddk -SET W2K_DDKROOT=c:\c\2000ddk -SET MASM_ROOT=c:\c\masm611 -SET VTOOLSD=c:\c\vtd95 -SET SOFTICE_PATH=c:\c\sint - -REM: The following define the locations of all the compilers that you may -REM: be using. Change them to reflect where you have installed your -REM: compilers. - -SET BC3_PATH=c:\c\bc3 -SET BC4_PATH=c:\c\bc45 -SET BC5_PATH=c:\c\bc50 -SET BCB5_PATH=c:\c\bcb50 -SET VC_PATH=c:\c\msvc -SET VC4_PATH=c:\c\vc42 -SET VC5_PATH=c:\c\vc50 -SET VC6_PATH=c:\c\vc60 -SET SC70_PATH=c:\c\sc75 -SET WC10A_PATH=c:\c\wc10a -SET WC10_PATH=c:\c\wc10 -SET WC11_PATH=c:\c\wc11 -SET TNT_PATH=c:\c\tnt -SET DJ_PATH=c:\c\djgpp -SET GCC2_PATH=c:\unix\usr - -REM: The following define the locations of the IDE and compiler path -REM: tools for Visual C++. If you do a standard installation, you wont -REM: need to change this. If however you did a custom install and changed -REM: the paths to these directory, you will need to modify this to suit. - -SET VC5_MSDevDir=%VC5_PATH%\sharedide -SET VC5_MSVCDir=%VC5_PATH%\vc -SET VC6_MSDevDir=%VC6_PATH%\common\msdev98 -SET VC6_MSVCDir=%VC6_PATH%\vc98 - diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat deleted file mode 100755 index 71f7d8e..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat +++ /dev/null @@ -1,36 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 4.2 32 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC4_PATH% -set C_INCLUDE=%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -set INIT=%VC4_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32=1 -SET WIN32_GUI= -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=VC4 -PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto done -call win32sdk.bat - -:done -echo Visual C++ 4.2 32 bit Windows compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat deleted file mode 100755 index 9817493..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat +++ /dev/null @@ -1,27 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 1.52c 16 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC4;%VC_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC4;%VC_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC_PATH% -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; -set INIT=%VC_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=VC4 -PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% - -echo Visual C++ 1.52c 16 DOS bit compilation environment set up. - diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat deleted file mode 100755 index 62e3521..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat +++ /dev/null @@ -1,21 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 4.2 32 bit edition - -REM: First setup for Win32 console development -call vc40-c32.bat > NUL - -REM: Extra stuff to set up for Windows 9x DDK development -set MASTER_MAKE=1 -set DDKROOT=%W95_DDKROOT% -set SDKROOT=%MSSDK% -set C16_ROOT=%VC_PATH% -set C32_ROOT=%VC4_PATH% - -if .%CHECKED%==.1 goto checked_build -echo Release build enabled. -goto done -:checked_build -echo Checked debug build enabled. -goto done -:done -echo Visual C++ 4.2 Windows 9x driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat deleted file mode 100755 index 83b6780..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat +++ /dev/null @@ -1,18 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 4.2 32 bit edition - -REM: First setup for Win32 console development (with Platform SDK) -call vc40-c32.bat sdk > NUL - -REM: Extra stuff to set up for Windows NT DDK development -SET BASEDIR=%NT_DDKROOT% -SET PATH=%NT_DDKROOT%\bin;%PATH% - -if .%CHECKED%==.1 goto checked_build -echo Release build enabled. -goto done -:checked_build -echo Checked debug build enabled. -goto done -:done -echo Visual C++ 4.2 Windows NT driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat deleted file mode 100755 index 7997044..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat +++ /dev/null @@ -1,31 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 4.2 32 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC4_PATH% -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE -set INIT=%VC4_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32= -SET WIN32_GUI= -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP=1 -SET VC_LIBBASE=VC4 -PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -echo Visual C++ 4.2 Snap compilation environment set up - diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat deleted file mode 100755 index b0fc936..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat +++ /dev/null @@ -1,42 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 4.2 32 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\COFFLIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\COFFLIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC4_PATH% -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; -set INIT=%VC4_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_TNT= -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=VC4 -PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -REM If you set the following to a 1, a TNT DosStyle app will be created. -REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* -REM run under real DOS when using our libraries, since we require access -REM to functions that the Win32 API does not support (such as direct access -REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps -REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't -REM work too well). -REM -REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, -REM and hence will never be able to run under Win95 or WinNT, only DOS. - -SET DOSSTYLE= - -echo Visual C++ 4.2 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat deleted file mode 100755 index 2849a20..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat +++ /dev/null @@ -1,26 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 1.52c 16 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC4;%VC_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC4;%VC_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC_PATH% -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; -set INIT=%VC_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK -SET USE_WIN16=1 -SET USE_WIN32= -SET VC_LIBBASE=VC4 -SET USE_RTTARGET= -SET USE_SNAP= -PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% - -echo Visual C++ 1.52c 16 bit Windows compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat deleted file mode 100755 index d93a624..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 4.2 32 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC4_PATH% -set C_INCLUDE=%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -set INIT=%VC4_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32=1 -SET WIN32_GUI=1 -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=VC4 -PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto done -call win32sdk.bat - -:done -echo Visual C++ 4.2 32 bit Windows compilation environment set up - diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat deleted file mode 100755 index a420a54..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat +++ /dev/null @@ -1,20 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 4.2 32 bit edition - -SET LIB=%VC4_PATH%\LIB;. -SET TOOLROOTDIR=%VC4_PATH% -SET INCLUDE=\xc\include;%VC4_PATH%\INCLUDE -SET INIT=%VC4_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32=1 -SET WIN32_GUI=1 -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=VC4 -PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%DEFPATH% - -echo Visual C++ 4.2 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat deleted file mode 100755 index 62d27b9..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat +++ /dev/null @@ -1,39 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 5.0 32 bit edition - -SET MSDevDir=%VC5_MSDevDir% -SET MSVCDir=%VC5_MSVCDir% - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%MSVCDir% -set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE; -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -set INIT=%MSVCDir% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32=1 -SET WIN32_GUI= -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc5 -PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto done -call win32sdk.bat - -:done -echo Visual C++ 5.0 32-bit Windows console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat deleted file mode 100755 index c789c50..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat +++ /dev/null @@ -1,26 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 1.52c 16 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC5;%VC_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC5;%VC_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC_PATH% -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; -set INIT=%VC_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc5 -PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% - -echo Visual C++ 1.52c 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat deleted file mode 100755 index 27a4a14..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat +++ /dev/null @@ -1,21 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 6.0 32 bit edition - -REM: First setup for Win32 console development -call vc60-c32.bat > NUL - -REM: Extra stuff to set up for Windows 9x DDK development -set MASTER_MAKE=1 -set DDKROOT=%W95_DDKROOT% -set SDKROOT=%MSSDK% -set C16_ROOT=%VC_PATH% -set C32_ROOT=%VC6_PATH% - -if .%CHECKED%==.1 goto checked_build -echo Release build enabled. -goto done -:checked_build -echo Checked debug build enabled. -goto done -:done -echo Visual C++ 6.0 Windows 9x driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat deleted file mode 100755 index 17b2f25..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat +++ /dev/null @@ -1,17 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 6.0 32 bit edition - -REM: First setup for Win32 console development (with Platform SDK) -call vc60-c32.bat sdk > NUL - -REM: Now setup stuff for the NT DDK build environment -call ntddk.bat - -if .%CHECKED%==.1 goto checked_build -echo Release build enabled. -goto done -:checked_build -echo Checked debug build enabled. -goto done -:done -echo Visual C++ 6.0 Windows NT driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat deleted file mode 100755 index afb2fb1..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat +++ /dev/null @@ -1,30 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 5.0 32 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC5_PATH%\VC -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC5_PATH%\VC\INCLUDE;%TNT_PATH%\INCLUDE; -set INIT=%VC5_PATH%\VC -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32= -SET WIN32_GUI= -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET=1 -SET USE_SNAP= -SET VC_LIBBASE=vc5 -PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -echo Visual C++ 5.0 RTTarget-32 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat deleted file mode 100755 index 22d2e13..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat +++ /dev/null @@ -1,33 +0,0 @@ -@echo off REM Setup environment variables for Visual C++ 5.0 32 bit -edition - -SET MSDevDir=%VC5_MSDevDir% -SET MSVCDir=%VC5_MSVCDir% - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%MSVCDir% -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE -set INIT=%MSVCDir% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32= -SET WIN32_GUI= -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP=1 -SET VC_LIBBASE=vc5 -PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -echo Visual C++ 5.0 Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat deleted file mode 100755 index 6b09199..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat +++ /dev/null @@ -1,42 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 5.0 32 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\COFFLIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\COFFLIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC5_PATH%\VC -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC5_PATH%\VC\INCLUDE;%TNT_PATH%\INCLUDE; -set INIT=%VC5_PATH%\VC -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_TNT= -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc5 -PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -REM If you set the following to a 1, a TNT DosStyle app will be created. -REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* -REM run under real DOS when using our libraries, since we require access -REM to functions that the Win32 API does not support (such as direct access -REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps -REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't -REM work too well). -REM -REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, -REM and hence will never be able to run under Win95 or WinNT, only DOS. - -SET DOSSTYLE= - -echo Visual C++ 5.0 32-bit compilation environment set up (with TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat deleted file mode 100755 index 52ab495..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat +++ /dev/null @@ -1,27 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 1.52c 16 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC5;%VC_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC5;%VC_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC_PATH% -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; -set INIT=%VC_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK -SET USE_WIN16=1 -SET USE_WIN32= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc5 -PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% - -echo Visual C++ 1.52c 16-bit Windows compilation environment set up. - diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat deleted file mode 100755 index 07bc5e5..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat +++ /dev/null @@ -1,39 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 5.0 32 bit edition - -SET MSDevDir=%VC5_MSDevDir% -SET MSVCDir=%VC5_MSVCDir% - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%MSVCDir% -set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE; -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -set INIT=%MSVCDir% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32=1 -SET WIN32_GUI=1 -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc5 -PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto done -call win32sdk.bat - -:done -echo Visual C++ 5.0 32-bit Windows console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat deleted file mode 100755 index fe286bd..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat +++ /dev/null @@ -1,20 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 5.0 32 bit edition - -SET LIB=%VC5_PATH%\VC\LIB;. -SET TOOLROOTDIR=%VC5_PATH%\VC -SET INCLUDE=\xc\include;%VC5_PATH%\VC\INCLUDE -SET INIT=%VC5_PATH%\VC -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32=1 -SET WIN32_GUI=1 -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc5 -PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%DEFPATH% - -echo Visual C++ 5.0 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat deleted file mode 100755 index e98417d..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat +++ /dev/null @@ -1,39 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 6.0 32 bit edition - -SET MSDevDir=%VC6_MSDevDir% -SET MSVCDir=%VC6_MSVCDir% - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%MSVCDir% -set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -set INIT=%MSVCDir% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32=1 -SET WIN32_GUI= -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc6 -PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto done -call win32sdk.bat - -:done -echo Visual C++ 6.0 32-bit Windows console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat deleted file mode 100755 index 10855e0..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat +++ /dev/null @@ -1,26 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 1.52c 16 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC6;%VC_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC6;%VC_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC_PATH% -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; -set INIT=%VC_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc6 -PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% - -echo Visual C++ 1.52c 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat deleted file mode 100755 index 27a4a14..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat +++ /dev/null @@ -1,21 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 6.0 32 bit edition - -REM: First setup for Win32 console development -call vc60-c32.bat > NUL - -REM: Extra stuff to set up for Windows 9x DDK development -set MASTER_MAKE=1 -set DDKROOT=%W95_DDKROOT% -set SDKROOT=%MSSDK% -set C16_ROOT=%VC_PATH% -set C32_ROOT=%VC6_PATH% - -if .%CHECKED%==.1 goto checked_build -echo Release build enabled. -goto done -:checked_build -echo Checked debug build enabled. -goto done -:done -echo Visual C++ 6.0 Windows 9x driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat deleted file mode 100755 index 17b2f25..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat +++ /dev/null @@ -1,17 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 6.0 32 bit edition - -REM: First setup for Win32 console development (with Platform SDK) -call vc60-c32.bat sdk > NUL - -REM: Now setup stuff for the NT DDK build environment -call ntddk.bat - -if .%CHECKED%==.1 goto checked_build -echo Release build enabled. -goto done -:checked_build -echo Checked debug build enabled. -goto done -:done -echo Visual C++ 6.0 Windows NT driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat deleted file mode 100755 index f304293..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat +++ /dev/null @@ -1,17 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 6.0 32 bit edition - -REM: First setup for Win32 console development (with Platform SDK) -call vc60-c32.bat sdk > NUL - -REM: Now setup stuff for the NT DDK build environment -call w2kddk.bat - -if .%CHECKED%==.1 goto checked_build -echo Release build enabled. -goto done -:checked_build -echo Checked debug build enabled. -goto done -:done -echo Visual C++ 6.0 Windows Windows 2000 driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat deleted file mode 100755 index 5348ef9..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat +++ /dev/null @@ -1,33 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 6.0 32 bit edition - -SET MSDevDir=%VC6_MSDevDir% -SET MSVCDir=%VC6_MSVCDir% - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%MSVCDir% -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE -set INIT=%MSVCDir% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32= -SET WIN32_GUI= -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP=1 -SET VC_LIBBASE=vc6 -PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -echo Visual C++ 6.0 Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat deleted file mode 100755 index 1d8b5e3..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat +++ /dev/null @@ -1,42 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 6.0 32 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC6;%VC6_PATH%\VC98\LIB;%TNT_PATH%\COFFLIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC6;%VC6_PATH%\VC98\LIB;%TNT_PATH%\COFFLIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC6_PATH%\VC98 -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC6_PATH%\VC98\INCLUDE;%TNT_PATH%\INCLUDE; -set INIT=%VC6_PATH%\VC98 -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_TNT= -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc6 PATH -%SCITECH_BIN%;%VC6_PATH%\VC98\BIN;%VC6_PATH%\COMMON\MSDEV98\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -REM If you set the following to a 1, a TNT DosStyle app will be created. -REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* -REM run under real DOS when using our libraries, since we require access -REM to functions that the Win32 API does not support (such as direct access -REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps -REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't -REM work too well). -REM -REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, -REM and hence will never be able to run under Win95 or WinNT, only DOS. - -SET DOSSTYLE= - -echo Visual C++ 6.0 32-bit compilation environment set up (with TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat deleted file mode 100755 index 70175c3..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat +++ /dev/null @@ -1,27 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 1.52c 16 bit edition - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC6;%VC_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC6;%VC_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%VC_PATH% -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; -set INIT=%VC_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK -SET USE_WIN16=1 -SET USE_WIN32= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc6 -PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% - -echo Visual C++ 1.52c 16-bit Windows compilation environment set up. - diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat deleted file mode 100755 index 2f8e7ab..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat +++ /dev/null @@ -1,39 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 6.0 32 bit edition - -SET MSDevDir=%VC6_MSDevDir% -SET MSVCDir=%VC6_MSVCDir% - -if .%CHECKED%==.1 goto checked_build -set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -set TOOLROOTDIR=%MSVCDir% -set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE -set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -set INIT=%MSVCDir% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32=1 -SET WIN32_GUI=1 -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc6 -PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto done -call win32sdk.bat - -:done -echo Visual C++ 6.0 32-bit Windows compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat deleted file mode 100755 index 57b23d2..0000000 --- a/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat +++ /dev/null @@ -1,20 +0,0 @@ -@echo off -REM Setup environment variables for Visual C++ 6.0 32 bit edition - -SET LIB=%VC6_PATH%\VC98\LIB;. -SET TOOLROOTDIR=%VC6_PATH%\VC98 -SET INCLUDE=\xc\include;%VC6_PATH%\VC98\INCLUDE; -SET INIT=%VC6_PATH%\VC98 -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK -SET USE_TNT= -SET USE_WIN16= -SET USE_WIN32=1 -SET WIN32_GUI=1 -SET USE_VXD= -SET USE_NTDRV= -SET USE_RTTARGET= -SET USE_SNAP= -SET VC_LIBBASE=vc6 -PATH %SCITECH_BIN%;%VC6_PATH%\VC98\BIN;%VC6_PATH%\COMMON\MSDEV98\BIN;%DEFPATH% - -echo Visual C++ 6.0 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/w2kddk.bat b/board/MAI/bios_emulator/scitech/bin/w2kddk.bat deleted file mode 100755 index 92858d1..0000000 --- a/board/MAI/bios_emulator/scitech/bin/w2kddk.bat +++ /dev/null @@ -1,42 +0,0 @@ -@echo off -REM: Set up environment variables for Microsoft Windows NT DDK development. -REM: Note that we have hard coded this for Windows NT i386 development. - -SET USE_NTDRV=1 -SET USE_W2KDRV=1 -SET BASEDIR=%W2K_DDKROOT% -SET PATH=%BASEDIR%\bin;%PATH% -SET NTMAKEENV=%BASEDIR%\inc -SET BUILD_MAKE_PROGRAM=nmake.exe -SET BUILD_DEFAULT=-ei -nmake -i -SET BUILD_DEFAULT_TARGETS=-386 -SET _OBJ_DIR=obj -SET NEW_CRTS=1 -SET _NTROOT=%BASEDIR% -SET INCLUDE=%BASEDIR%\inc;%BASEDIR%\inc\ddk;%INCLUDE% - -if .%CHECKED%==.1 goto checked - -REM: set up an NT free build environment -SET DDKBUILDENV=free -SET C_DEFINES=-D_IDWBUILD -SET NTDBGFILES=1 -SET NTDEBUG= -SET NTDEBUGTYPE= -SET MSC_OPTIMIZATION= -set LIB=%BASEDIR%\libfre\i386;%SCITECH_LIB%\LIB\RELEASE\W2KDRV\VC6;%MSVCDir%\LIB;. - -goto done - -:checked - -REM: set up an NT checked build environment -SET DDKBUILDENV=checked -SET C_DEFINES=-D_IDWBUILD -DRDRDBG -DSRVDBG -SET NTDBGFILES= -SET NTDEBUG=ntsd -SET NTDEBUGTYPE=both -SET MSC_OPTIMIZATION=/Od /Oi -set LIB=%BASEDIR%\libchk\i386;%SCITECH_LIB%\LIB\DEBUG\W2KDRV\VC6;%MSVCDir%\LIB;. - -:done diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat deleted file mode 100755 index 2d738f3..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT; -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_WIN386= -SET WIN32_GUI= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC10 -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.6 Win32 console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat deleted file mode 100755 index 5c53a90..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat +++ /dev/null @@ -1,30 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (DOS4GW) - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC10;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC10;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\WIN; -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC10 -SET EDPATH=%WC10_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.6 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat deleted file mode 100755 index a5c7210..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (DOS4GW) - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H; -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC10 -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.6 32-bit DOS compilation environment set up (DOS4GW) - diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat deleted file mode 100755 index 579dece..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat +++ /dev/null @@ -1,31 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 16-bit OS/2 mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\lib\release\os216\wc10;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\lib\debug\os216\wc10;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\eddat -SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216=1 -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=wc10 -SET EDPATH=%WC10_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.6 16-bit OS/2 compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat deleted file mode 100755 index 3404b42..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat +++ /dev/null @@ -1,31 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 32-bit OS/2 mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\eddat -SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232=1 -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=wc10 -SET EDPATH=%WC10_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.6 32-bit OS/2 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat deleted file mode 100755 index 57057de..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat +++ /dev/null @@ -1,31 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 32-bit OS/2 mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\eddat -SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232=1 -SET USE_OS2GUI=1 -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=wc10 -SET EDPATH=%WC10_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.6 32-bit OS/2 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat b/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat deleted file mode 100755 index 46f8659..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (QNX 4) - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\QNX4\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\QNX;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\QNX4\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\QNX;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\QH; -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4=1 -SET WC_LIBBASE=WC10 -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.6 32-bit QNX compilation environment set up - diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat b/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat deleted file mode 100755 index 1fde624..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET WIN32_GUI= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP=1 -SET USE_QNX4= -SET WC_LIBBASE=WC10 -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.6 Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat b/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat deleted file mode 100755 index d12f042..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat +++ /dev/null @@ -1,46 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode with Phar Lap TNT - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT;%TNT_PATH%\INCLUDE -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT=1 -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC10 -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -REM If you set the following to a 1, a TNT DosStyle app will be created. -REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* -REM run under real DOS when using our libraries, since we require access -REM to functions that the Win32 API does not support (such as direct access -REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps -REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't -REM work too well). -REM -REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, -REM and hence will never be able to run under Win95 or WinNT, only DOS. - -SET DOSSTYLE=1 - -echo Watcom C/C++ 10.6 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat deleted file mode 100755 index e8ba871..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat +++ /dev/null @@ -1,32 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 16 bit Windows mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC10;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC10;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\WIN; -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK -SET USE_WIN16=1 -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC10 -SET EDPATH=%WC10_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.6 16-bit Windows compilation environment set up. - diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat deleted file mode 100755 index 839bdde..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT; -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_WIN386= -SET WIN32_GUI=1 -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC10 -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.6 Win32 GUI compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat b/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat deleted file mode 100755 index fc783d8..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat +++ /dev/null @@ -1,24 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode - -SET LIB=%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. -SET EDPATH=%WC10_PATH%\EDDAT -SET INCLUDE=%WC10_PATH%\H;%WC10_PATH%\H\NT; -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_WIN386= -SET WIN32_GUI=1 -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC10 -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.6 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat deleted file mode 100755 index 6e0c24d..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat +++ /dev/null @@ -1,33 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10A_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT; -SET WATCOM=%WC10A_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_WIN386= -SET WIN32_GUI= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET WC_LIBBASE=WC10A -PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.0a Win32 console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat b/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat deleted file mode 100755 index f9ecb67..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat +++ /dev/null @@ -1,29 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode (DOS4GW) - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC10A;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC10A;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10A_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\WIN; -SET WATCOM=%WC10A_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET WC_LIBBASE=WC10A -SET EDPATH=%WC10A_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.0a 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat deleted file mode 100755 index d52b79a..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat +++ /dev/null @@ -1,32 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode (DOS4GW) - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10A_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H; -SET WATCOM=%WC10A_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET WC_LIBBASE=WC10A -PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.0a 32-bit DOS compilation environment set up (DOS4GW) diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat b/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat deleted file mode 100755 index ba7351d..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat +++ /dev/null @@ -1,30 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.0a in 16-bit OS/2 mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\lib\release\os216\wc10;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\lib\debug\os216\wc10;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10A_PATH%\eddat -SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10A_PATH%\h\os2;%WC10A_PATH%\h -SET WATCOM=%WC10A_PATH% -SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216=1 -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET WC_LIBBASE=wc10 -SET EDPATH=%WC10A_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.0a 16-bit OS/2 compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat deleted file mode 100755 index f3caa59..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat +++ /dev/null @@ -1,30 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.0a in 32-bit OS/2 mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10AA_PATH%\eddat -SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10AA_PATH%\h\os2;%WC10AA_PATH%\h -SET WATCOM=%WC10AA_PATH% -SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232=1 -SET USE_OS2GUI= -SET USE_SNAP= -SET WC_LIBBASE=WC10A -SET EDPATH=%WC10AA_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC10AA_PATH%\BINNT;%WC10AA6_PATH%\BINB;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.0a 32-bit OS/2 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat deleted file mode 100755 index 8d21c62..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat +++ /dev/null @@ -1,30 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.0a in 32-bit OS/2 mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10_PATH%\eddat -SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h -SET WATCOM=%WC10_PATH% -SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232=1 -SET USE_OS2GUI=1 -SET USE_SNAP= -SET WC_LIBBASE=WC10A -SET EDPATH=%WC10_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINB;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.0a 32-bit OS/2 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat b/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat deleted file mode 100755 index 28f857c..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat +++ /dev/null @@ -1,33 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10A_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE -SET WATCOM=%WC10A_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_WIN386= -SET WIN32_GUI= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP=1 -SET WC_LIBBASE=WC10A -PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.0a Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat b/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat deleted file mode 100755 index a2b3219..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat +++ /dev/null @@ -1,45 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode with Phar Lap TNT - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10A_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT;%TNT_PATH%\INCLUDE -SET WATCOM=%WC10A_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT=1 -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET WC_LIBBASE=WC10A -PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% - -REM If you set the following to a 1, a TNT DosStyle app will be created. -REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* -REM run under real DOS when using our libraries, since we require access -REM to functions that the Win32 API does not support (such as direct access -REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps -REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't -REM work too well). -REM -REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, -REM and hence will never be able to run under Win95 or WinNT, only DOS. - -SET DOSSTYLE=1 - -echo Watcom C/C++ 10.0a 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat b/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat deleted file mode 100755 index 94011cc..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat +++ /dev/null @@ -1,31 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.0a in 16 bit Windows mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC10A;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC10A;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10A_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\WIN; -SET WATCOM=%WC10A_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK -SET USE_WIN16=1 -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET WC_LIBBASE=WC10A -SET EDPATH=%WC10A_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.0a 16-bit Windows compilation environment set up. - diff --git a/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat b/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat deleted file mode 100755 index 1e14dbc..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat +++ /dev/null @@ -1,33 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC10A_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT; -SET WATCOM=%WC10A_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_WIN386= -SET WIN32_GUI=1 -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET WC_LIBBASE=WC10A -PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 10.0a Win32 GUI compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat deleted file mode 100755 index e753129..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat +++ /dev/null @@ -1,40 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\EDDAT -SET C_INCLUDE=%WC11_PATH%\H;%WC11_PATH%\H\NT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_WIN386= -SET WIN32_GUI= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC11 -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto done -call win32sdk.bat - -:done -echo Watcom C/C++ 11.0 Win32 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat deleted file mode 100755 index 4338ada..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat +++ /dev/null @@ -1,30 +0,0 @@ -@echo off -REM SETup for compiling with Watcom C/C++ 11.0 in 16 bit mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC11;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC11;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\WIN; -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK -SET USE_WIN16= -SET USE_WIN32= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC11 -SET EDPATH=%WC11_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 11.0 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat deleted file mode 100755 index e5a54d4..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat +++ /dev/null @@ -1,33 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode (DOS4GW) - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H; -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC11 -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 11.0 32-bit DOS compilation environment set up (DOS4GW). diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat deleted file mode 100755 index d46754a..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat +++ /dev/null @@ -1,31 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 11.0 in 16-bit OS/2 mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\lib\release\os216\wc11;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\lib\debug\os216\wc11;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\eddat -SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216=1 -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=wc11 -SET EDPATH=%WC11_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 11.0 16-bit OS/2 compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat deleted file mode 100755 index 37f5dc7..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat +++ /dev/null @@ -1,31 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 11.0 in 32-bit OS/2 mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\lib\release\os232\wc11;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\lib\debug\os232\wc11;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\eddat -SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232=1 -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=wc11 -SET EDPATH=%WC11_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 11.0 32-bit OS/2 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat deleted file mode 100755 index 348cbbd..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat +++ /dev/null @@ -1,31 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 11.0 in 32-bit OS/2 mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\lib\release\os232\wc11;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\lib\debug\os232\wc11;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\eddat -SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232=1 -SET USE_OS2GUI=1 -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=wc11 -SET EDPATH=%WC11_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 11.0 32-bit OS/2 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat b/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat deleted file mode 100755 index 1fd60fe..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode (QNX 4) - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\QNX4\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\QNX;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\QNX4\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\QNX;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\QH; -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4=1 -SET WC_LIBBASE=WC11 -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 11.0 32-bit QNX compilation environment set up - diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat b/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat deleted file mode 100755 index 6d2ac57..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET WIN32_GUI= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP=1 -SET USE_QNX4= -SET WC_LIBBASE=WC11 -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 11.0 Snap compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat b/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat deleted file mode 100755 index 44dbf24..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat +++ /dev/null @@ -1,46 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode with Phar Lap TNT - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\NT;%TNT_PATH%\INCLUDE -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT=1 -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC11 -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -REM If you set the following to a 1, a TNT DosStyle app will be created. -REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* -REM run under real DOS when using our libraries, since we require access -REM to functions that the Win32 API does not support (such as direct access -REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps -REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't -REM work too well). -REM -REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, -REM and hence will never be able to run under Win95 or WinNT, only DOS. - -SET DOSSTYLE=1 - -echo Watcom C/C++ 11.0 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat deleted file mode 100755 index e65c70e..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat +++ /dev/null @@ -1,31 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 11.0 in 16 bit Windows mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC11;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC11;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\WIN; -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK -SET USE_WIN16=1 -SET USE_WIN32= -SET USE_WIN386= -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC11 -SET EDPATH=%WC11_PATH%\EDDAT -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 11.0 16-bit Windows compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat deleted file mode 100755 index 764cdbd..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat +++ /dev/null @@ -1,40 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\EDDAT -SET C_INCLUDE=%WC11_PATH%\H;%WC11_PATH%\H\NT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_WIN386= -SET WIN32_GUI=1 -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC11 -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -REM: Enable Win32 SDK if desired (sdk on command line) -if NOT .%1%==.sdk goto done -call win32sdk.bat - -:done -echo Watcom C/C++ 11.0 Win32 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat b/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat deleted file mode 100755 index c2569a3..0000000 --- a/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat +++ /dev/null @@ -1,34 +0,0 @@ -@echo off -REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode - -if .%CHECKED%==.1 goto checked_build -SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. -echo Release build enabled. -goto setvars - -:checked_build -SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. -echo Checked debug build enabled. -goto setvars - -:setvars -SET EDPATH=%WC11_PATH%\EDDAT -SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\NT; -SET WATCOM=%WC11_PATH% -SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK -SET USE_TNT= -SET USE_X32= -SET USE_X32VM= -SET USE_WIN16= -SET USE_WIN32=1 -SET USE_WIN386= -SET WIN32_GUI=1 -SET USE_OS216= -SET USE_OS232= -SET USE_OS2GUI= -SET USE_SNAP= -SET USE_QNX4= -SET WC_LIBBASE=WC11 -PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% - -echo Watcom C/C++ 11.0 Win32 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/win32sdk.bat b/board/MAI/bios_emulator/scitech/bin/win32sdk.bat deleted file mode 100755 index 3c7f017..0000000 --- a/board/MAI/bios_emulator/scitech/bin/win32sdk.bat +++ /dev/null @@ -1,20 +0,0 @@ -@echo off -REM: Set up environment variables for Microsoft Platform SDK development -REM: Note that we have hard coded this for Windows NT i386 development. - -SET MSTOOLS=%MSSDK% -SET DXSDKROOT=%MSTOOLS% -SET INETSDK=%MSTOOLS% -SET BKOFFICE=%MSTOOLS% -SET BASEMAKE=%BKOFFICE%\INCLUDE\BKOffice.Mak -SET INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%MSTOOLS%\INCLUDE;%C_INCLUDE% -if .%1%==.borland goto borland -SET LIB=%MSTOOLS%\LIB;%LIB% -goto notborland -:borland -SET LIB=%MSTOOLS%\LIB\BORLAND;%LIB% -:notborland -SET PATH=%MSTOOLS%\Bin\;%MSTOOLS%\Bin\WinNT;%PATH% -SET CPU=i386 - -echo Microsoft Platform SDK support enbabled. diff --git a/board/MAI/bios_emulator/scitech/include/biosemu.h b/board/MAI/bios_emulator/scitech/include/biosemu.h deleted file mode 100644 index 82c33a7..0000000 --- a/board/MAI/bios_emulator/scitech/include/biosemu.h +++ /dev/null @@ -1,154 +0,0 @@ -/**************************************************************************** -* -* BIOS emulator and interface -* to Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Header file for the real mode x86 BIOS emulator, which is -* used to warmboot any number of VGA compatible PCI/AGP -* controllers under any OS, on any processor family that -* supports PCI. We also allow the user application to call -* real mode BIOS functions and Int 10h functions (including -* the VESA BIOS). -* -****************************************************************************/ - -#ifndef __BIOSEMU_H -#define __BIOSEMU_H - -#include "x86emu.h" -#include "pmapi.h" -#include "pcilib.h" - -/*---------------------- Macros and type definitions ----------------------*/ - -#pragma pack(1) - -/**************************************************************************** -REMARKS: -Data structure used to describe the details specific to a particular VGA -controller. This information is used to allow the VGA controller to be -swapped on the fly within the BIOS emulator. - -HEADER: -biosemu.h - -MEMBERS: -pciInfo - PCI device information block for the controller -BIOSImage - Pointer to a read/write copy of the BIOS image -BIOSImageLen - Length of the BIOS image -LowMem - Copy of key low memory areas -****************************************************************************/ -typedef struct { - PCIDeviceInfo *pciInfo; - void *BIOSImage; - ulong BIOSImageLen; - uchar LowMem[1536]; - } BE_VGAInfo; - -/**************************************************************************** -REMARKS: -Data structure used to describe the details for the BIOS emulator system -environment as used by the X86 emulator library. - -HEADER: -biosemu.h - -MEMBERS: -vgaInfo - VGA BIOS information structure -biosmem_base - Base of the BIOS image -biosmem_limit - Limit of the BIOS image -busmem_base - Base of the VGA bus memory -****************************************************************************/ -typedef struct { - BE_VGAInfo vgaInfo; - ulong biosmem_base; - ulong biosmem_limit; - ulong busmem_base; - } BE_sysEnv; - -/**************************************************************************** -REMARKS: -Structure defining all the BIOS Emulator API functions as exported from -the Binary Portable DLL. -{secret} -****************************************************************************/ -typedef struct { - ulong dwSize; - ibool (PMAPIP BE_init)(u32 debugFlags,int memSize,BE_VGAInfo *info); - void (PMAPIP BE_setVGA)(BE_VGAInfo *info); - void (PMAPIP BE_getVGA)(BE_VGAInfo *info); - void * (PMAPIP BE_mapRealPointer)(uint r_seg,uint r_off); - void * (PMAPIP BE_getVESABuf)(uint *len,uint *rseg,uint *roff); - void (PMAPIP BE_callRealMode)(uint seg,uint off,RMREGS *regs,RMSREGS *sregs); - int (PMAPIP BE_int86)(int intno,RMREGS *in,RMREGS *out); - int (PMAPIP BE_int86x)(int intno,RMREGS *in,RMREGS *out,RMSREGS *sregs); - void * reserved1; - void (PMAPIP BE_exit)(void); - } BE_exports; - -/**************************************************************************** -REMARKS: -Function pointer type for the Binary Portable DLL initialisation entry point. -{secret} -****************************************************************************/ -typedef BE_exports * (PMAPIP BE_initLibrary_t)(PM_imports *PMImp); - -#pragma pack() - -/*---------------------------- Global variables ---------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -/* {secret} Global BIOS emulator system environment */ -extern BE_sysEnv _BE_env; - -/*-------------------------- Function Prototypes --------------------------*/ - -/* BIOS emulator library entry points */ - -ibool PMAPI BE_init(u32 debugFlags,int memSize,BE_VGAInfo *info); -void PMAPI BE_setVGA(BE_VGAInfo *info); -void PMAPI BE_getVGA(BE_VGAInfo *info); -void PMAPI BE_setDebugFlags(u32 debugFlags); -void * PMAPI BE_mapRealPointer(uint r_seg,uint r_off); -void * PMAPI BE_getVESABuf(uint *len,uint *rseg,uint *roff); -void PMAPI BE_callRealMode(uint seg,uint off,RMREGS *regs,RMSREGS *sregs); -int PMAPI BE_int86(int intno,RMREGS *in,RMREGS *out); -int PMAPI BE_int86x(int intno,RMREGS *in,RMREGS *out,RMSREGS *sregs); -void PMAPI BE_exit(void); - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __BIOSEMU_H */ diff --git a/board/MAI/bios_emulator/scitech/include/event.h b/board/MAI/bios_emulator/scitech/include/event.h deleted file mode 100644 index beeac87..0000000 --- a/board/MAI/bios_emulator/scitech/include/event.h +++ /dev/null @@ -1,696 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Header file for the SciTech cross platform event library -* -****************************************************************************/ - -#ifndef __EVENT_H -#define __EVENT_H - -#include "scitech.h" - -/*---------------------- Macros and type definitions ----------------------*/ - -#pragma pack(1) - -/* 'C' calling conventions always */ - -#define EVTAPI _ASMAPI -#define EVTAPIP _ASMAPIP - -/* Event message masks for keyDown events */ - -#define EVT_ASCIIMASK 0x00FF /* ASCII code of key pressed */ -#define EVT_SCANMASK 0xFF00 /* Scan code of key pressed */ -#define EVT_COUNTMASK 0x7FFF0000L /* Count for KEYREPEAT's */ - -/* Macros to extract values from the message fields */ - -#define EVT_asciiCode(m) ( (uchar) (m & EVT_ASCIIMASK) ) -#define EVT_scanCode(m) ( (uchar) ( (m & EVT_SCANMASK) >> 8 ) ) -#define EVT_repeatCount(m) ( (short) ( (m & EVT_COUNTMASK) >> 16 ) ) - -/**************************************************************************** -REMARKS: -Defines the set of ASCII codes reported by the event library functions -in the message field. Use the EVT_asciiCode macro to extract the code -from the event structure. - -HEADER: -event.h -****************************************************************************/ -typedef enum { - ASCII_ctrlA = 0x01, - ASCII_ctrlB = 0x02, - ASCII_ctrlC = 0x03, - ASCII_ctrlD = 0x04, - ASCII_ctrlE = 0x05, - ASCII_ctrlF = 0x06, - ASCII_ctrlG = 0x07, - ASCII_backspace = 0x08, - ASCII_ctrlH = 0x08, - ASCII_tab = 0x09, - ASCII_ctrlI = 0x09, - ASCII_ctrlJ = 0x0A, - ASCII_ctrlK = 0x0B, - ASCII_ctrlL = 0x0C, - ASCII_enter = 0x0D, - ASCII_ctrlM = 0x0D, - ASCII_ctrlN = 0x0E, - ASCII_ctrlO = 0x0F, - ASCII_ctrlP = 0x10, - ASCII_ctrlQ = 0x11, - ASCII_ctrlR = 0x12, - ASCII_ctrlS = 0x13, - ASCII_ctrlT = 0x14, - ASCII_ctrlU = 0x15, - ASCII_ctrlV = 0x16, - ASCII_ctrlW = 0x17, - ASCII_ctrlX = 0x18, - ASCII_ctrlY = 0x19, - ASCII_ctrlZ = 0x1A, - ASCII_esc = 0x1B, - ASCII_space = 0x20, - ASCII_exclamation = 0x21, /* ! */ - ASCII_quote = 0x22, /* " */ - ASCII_pound = 0x23, /* # */ - ASCII_dollar = 0x24, /* $ */ - ASCII_percent = 0x25, /* % */ - ASCII_ampersand = 0x26, /* & */ - ASCII_apostrophe = 0x27, /* ' */ - ASCII_leftBrace = 0x28, /* ( */ - ASCII_rightBrace = 0x29, /* ) */ - ASCII_times = 0x2A, /* * */ - ASCII_plus = 0x2B, /* + */ - ASCII_comma = 0x2C, /* , */ - ASCII_minus = 0x2D, /* - */ - ASCII_period = 0x2E, /* . */ - ASCII_divide = 0x2F, /* / */ - ASCII_0 = 0x30, - ASCII_1 = 0x31, - ASCII_2 = 0x32, - ASCII_3 = 0x33, - ASCII_4 = 0x34, - ASCII_5 = 0x35, - ASCII_6 = 0x36, - ASCII_7 = 0x37, - ASCII_8 = 0x38, - ASCII_9 = 0x39, - ASCII_colon = 0x3A, /* : */ - ASCII_semicolon = 0x3B, /* ; */ - ASCII_lessThan = 0x3C, /* < */ - ASCII_equals = 0x3D, /* = */ - ASCII_greaterThan = 0x3E, /* > */ - ASCII_question = 0x3F, /* ? */ - ASCII_at = 0x40, /* @ */ - ASCII_A = 0x41, - ASCII_B = 0x42, - ASCII_C = 0x43, - ASCII_D = 0x44, - ASCII_E = 0x45, - ASCII_F = 0x46, - ASCII_G = 0x47, - ASCII_H = 0x48, - ASCII_I = 0x49, - ASCII_J = 0x4A, - ASCII_K = 0x4B, - ASCII_L = 0x4C, - ASCII_M = 0x4D, - ASCII_N = 0x4E, - ASCII_O = 0x4F, - ASCII_P = 0x50, - ASCII_Q = 0x51, - ASCII_R = 0x52, - ASCII_S = 0x53, - ASCII_T = 0x54, - ASCII_U = 0x55, - ASCII_V = 0x56, - ASCII_W = 0x57, - ASCII_X = 0x58, - ASCII_Y = 0x59, - ASCII_Z = 0x5A, - ASCII_leftSquareBrace = 0x5B, /* [ */ - ASCII_backSlash = 0x5C, /* \ */ - ASCII_rightSquareBrace = 0x5D, /* ] */ - ASCII_caret = 0x5E, /* ^ */ - ASCII_underscore = 0x5F, /* _ */ - ASCII_leftApostrophe = 0x60, /* ` */ - ASCII_a = 0x61, - ASCII_b = 0x62, - ASCII_c = 0x63, - ASCII_d = 0x64, - ASCII_e = 0x65, - ASCII_f = 0x66, - ASCII_g = 0x67, - ASCII_h = 0x68, - ASCII_i = 0x69, - ASCII_j = 0x6A, - ASCII_k = 0x6B, - ASCII_l = 0x6C, - ASCII_m = 0x6D, - ASCII_n = 0x6E, - ASCII_o = 0x6F, - ASCII_p = 0x70, - ASCII_q = 0x71, - ASCII_r = 0x72, - ASCII_s = 0x73, - ASCII_t = 0x74, - ASCII_u = 0x75, - ASCII_v = 0x76, - ASCII_w = 0x77, - ASCII_x = 0x78, - ASCII_y = 0x79, - ASCII_z = 0x7A, - ASCII_leftCurlyBrace = 0x7B, /* { */ - ASCII_verticalBar = 0x7C, /* | */ - ASCII_rightCurlyBrace = 0x7D, /* } */ - ASCII_tilde = 0x7E /* ~ */ - } EVT_asciiCodesType; - -/**************************************************************************** -REMARKS: -Defines the set of scan codes reported by the event library functions -in the message field. Use the EVT_scanCode macro to extract the code -from the event structure. Note that the scan codes reported will be the -same across all keyboards (assuming the placement of keys on a 101 key US -keyboard), but the translated ASCII values may be different depending on -the country code pages in use. - -NOTE: Scan codes in the event library are not really hardware scan codes, - but rather virtual scan codes as generated by a low level keyboard - interface driver. All virtual codes begin with scan code 0x60 and - range up from there. - -HEADER: -event.h -****************************************************************************/ -typedef enum { - KB_padEnter = 0x60, /* Keypad keys */ - KB_padMinus = 0x4A, - KB_padPlus = 0x4E, - KB_padTimes = 0x37, - KB_padDivide = 0x61, - KB_padLeft = 0x62, - KB_padRight = 0x63, - KB_padUp = 0x64, - KB_padDown = 0x65, - KB_padInsert = 0x66, - KB_padDelete = 0x67, - KB_padHome = 0x68, - KB_padEnd = 0x69, - KB_padPageUp = 0x6A, - KB_padPageDown = 0x6B, - KB_padCenter = 0x4C, - KB_F1 = 0x3B, /* Function keys */ - KB_F2 = 0x3C, - KB_F3 = 0x3D, - KB_F4 = 0x3E, - KB_F5 = 0x3F, - KB_F6 = 0x40, - KB_F7 = 0x41, - KB_F8 = 0x42, - KB_F9 = 0x43, - KB_F10 = 0x44, - KB_F11 = 0x57, - KB_F12 = 0x58, - KB_left = 0x4B, /* Cursor control keys */ - KB_right = 0x4D, - KB_up = 0x48, - KB_down = 0x50, - KB_insert = 0x52, - KB_delete = 0x53, - KB_home = 0x47, - KB_end = 0x4F, - KB_pageUp = 0x49, - KB_pageDown = 0x51, - KB_capsLock = 0x3A, - KB_numLock = 0x45, - KB_scrollLock = 0x46, - KB_leftShift = 0x2A, - KB_rightShift = 0x36, - KB_leftCtrl = 0x1D, - KB_rightCtrl = 0x6C, - KB_leftAlt = 0x38, - KB_rightAlt = 0x6D, - KB_leftWindows = 0x5B, - KB_rightWindows = 0x5C, - KB_menu = 0x5D, - KB_sysReq = 0x54, - KB_esc = 0x01, /* Normal keyboard keys */ - KB_1 = 0x02, - KB_2 = 0x03, - KB_3 = 0x04, - KB_4 = 0x05, - KB_5 = 0x06, - KB_6 = 0x07, - KB_7 = 0x08, - KB_8 = 0x09, - KB_9 = 0x0A, - KB_0 = 0x0B, - KB_minus = 0x0C, - KB_equals = 0x0D, - KB_backSlash = 0x2B, - KB_backspace = 0x0E, - KB_tab = 0x0F, - KB_Q = 0x10, - KB_W = 0x11, - KB_E = 0x12, - KB_R = 0x13, - KB_T = 0x14, - KB_Y = 0x15, - KB_U = 0x16, - KB_I = 0x17, - KB_O = 0x18, - KB_P = 0x19, - KB_leftSquareBrace = 0x1A, - KB_rightSquareBrace = 0x1B, - KB_enter = 0x1C, - KB_A = 0x1E, - KB_S = 0x1F, - KB_D = 0x20, - KB_F = 0x21, - KB_G = 0x22, - KB_H = 0x23, - KB_J = 0x24, - KB_K = 0x25, - KB_L = 0x26, - KB_semicolon = 0x27, - KB_apostrophe = 0x28, - KB_Z = 0x2C, - KB_X = 0x2D, - KB_C = 0x2E, - KB_V = 0x2F, - KB_B = 0x30, - KB_N = 0x31, - KB_M = 0x32, - KB_comma = 0x33, - KB_period = 0x34, - KB_divide = 0x35, - KB_space = 0x39, - KB_tilde = 0x29 - } EVT_scanCodesType; - -/**************************************************************************** -REMARKS: -Defines the mask for the joystick axes that are present - -HEADER: -event.h - -MEMBERS: -EVT_JOY_AXIS_X1 - Joystick 1, X axis is present -EVT_JOY_AXIS_Y1 - Joystick 1, Y axis is present -EVT_JOY_AXIS_X2 - Joystick 2, X axis is present -EVT_JOY_AXIS_Y2 - Joystick 2, Y axis is present -EVT_JOY_AXIS_ALL - Mask for all axes -****************************************************************************/ -typedef enum { - EVT_JOY_AXIS_X1 = 0x00000001, - EVT_JOY_AXIS_Y1 = 0x00000002, - EVT_JOY_AXIS_X2 = 0x00000004, - EVT_JOY_AXIS_Y2 = 0x00000008, - EVT_JOY_AXIS_ALL = 0x0000000F - } EVT_eventJoyAxisType; - -/**************************************************************************** -REMARKS: -Defines the event message masks for joystick events - -HEADER: -event.h - -MEMBERS: -EVT_JOY1_BUTTONA - Joystick 1, button A is down -EVT_JOY1_BUTTONB - Joystick 1, button B is down -EVT_JOY2_BUTTONA - Joystick 2, button A is down -EVT_JOY2_BUTTONB - Joystick 2, button B is down -****************************************************************************/ -typedef enum { - EVT_JOY1_BUTTONA = 0x00000001, - EVT_JOY1_BUTTONB = 0x00000002, - EVT_JOY2_BUTTONA = 0x00000004, - EVT_JOY2_BUTTONB = 0x00000008 - } EVT_eventJoyMaskType; - -/**************************************************************************** -REMARKS: -Defines the event message masks for mouse events - -HEADER: -event.h - -MEMBERS: -EVT_LEFTBMASK - Left button is held down -EVT_RIGHTBMASK - Right button is held down -EVT_MIDDLEBMASK - Middle button is held down -EVT_BOTHBMASK - Both left and right held down together -EVT_ALLBMASK - All buttons pressed -EVT_DBLCLICK - Set if mouse down event was a double click -****************************************************************************/ -typedef enum { - EVT_LEFTBMASK = 0x00000001, - EVT_RIGHTBMASK = 0x00000002, - EVT_MIDDLEBMASK = 0x00000004, - EVT_BOTHBMASK = 0x00000007, - EVT_ALLBMASK = 0x00000007, - EVT_DBLCLICK = 0x00010000 - } EVT_eventMouseMaskType; - -/**************************************************************************** -REMARKS: -Defines the event modifier masks. These are the masks used to extract -the modifier information from the modifiers field of the event_t structure. -Note that the values in the modifiers field represent the values of these -modifier keys at the time the event occurred, not the time you decided -to process the event. - -HEADER: -event.h - -MEMBERS: -EVT_LEFTBUT - Set if left mouse button was down -EVT_RIGHTBUT - Set if right mouse button was down -EVT_MIDDLEBUT - Set if the middle button was down -EVT_RIGHTSHIFT - Set if right shift was down -EVT_LEFTSHIFT - Set if left shift was down -EVT_RIGHTCTRL - Set if right ctrl key was down -EVT_RIGHTALT - Set if right alt key was down -EVT_LEFTCTRL - Set if left ctrl key was down -EVT_LEFTALT - Set if left alt key was down -EVT_SHIFTKEY - Mask for any shift key down -EVT_CTRLSTATE - Set if ctrl key was down -EVT_ALTSTATE - Set if alt key was down -EVT_CAPSLOCK - Caps lock is active -EVT_NUMLOCK - Num lock is active -EVT_SCROLLLOCK - Scroll lock is active -****************************************************************************/ -typedef enum { - EVT_LEFTBUT = 0x00000001, - EVT_RIGHTBUT = 0x00000002, - EVT_MIDDLEBUT = 0x00000004, - EVT_RIGHTSHIFT = 0x00000008, - EVT_LEFTSHIFT = 0x00000010, - EVT_RIGHTCTRL = 0x00000020, - EVT_RIGHTALT = 0x00000040, - EVT_LEFTCTRL = 0x00000080, - EVT_LEFTALT = 0x00000100, - EVT_SHIFTKEY = 0x00000018, - EVT_CTRLSTATE = 0x000000A0, - EVT_ALTSTATE = 0x00000140, - EVT_SCROLLLOCK = 0x00000200, - EVT_NUMLOCK = 0x00000400, - EVT_CAPSLOCK = 0x00000800 - } EVT_eventModMaskType; - -/**************************************************************************** -REMARKS: -Defines the event codes returned in the event_t structures what field. Note -that these are defined as a set of mutually exlusive bit fields, so you -can test for multiple event types using the combined event masks defined -in the EVT_eventMaskType enumeration. - -HEADER: -event.h - -MEMBERS: -EVT_NULLEVT - A null event -EVT_KEYDOWN - Key down event -EVT_KEYREPEAT - Key repeat event -EVT_KEYUP - Key up event -EVT_MOUSEDOWN - Mouse down event -EVT_MOUSEAUTO - Mouse down autorepeat event -EVT_MOUSEUP - Mouse up event -EVT_MOUSEMOVE - Mouse movement event -EVT_JOYCLICK - Joystick button state change event -EVT_JOYMOVE - Joystick movement event -EVT_USEREVT - First user event -****************************************************************************/ -typedef enum { - EVT_NULLEVT = 0x00000000, - EVT_KEYDOWN = 0x00000001, - EVT_KEYREPEAT = 0x00000002, - EVT_KEYUP = 0x00000004, - EVT_MOUSEDOWN = 0x00000008, - EVT_MOUSEAUTO = 0x00000010, - EVT_MOUSEUP = 0x00000020, - EVT_MOUSEMOVE = 0x00000040, - EVT_JOYCLICK = 0x00000080, - EVT_JOYMOVE = 0x00000100, - EVT_USEREVT = 0x00000200 - } EVT_eventType; - -/**************************************************************************** -REMARKS: -Defines the event code masks you can use to test for multiple types of -events, since the event codes are mutually exlusive bit fields. - -HEADER: -event.h - -MEMBERS: -EVT_KEYEVT - Mask for any key event -EVT_MOUSEEVT - Mask for any mouse event -EVT_MOUSECLICK - Mask for any mouse click event -EVT_JOYEVT - Mask for any joystick event -EVT_EVERYEVT - Mask for any event -****************************************************************************/ -typedef enum { - EVT_KEYEVT = (EVT_KEYDOWN | EVT_KEYREPEAT | EVT_KEYUP), - EVT_MOUSEEVT = (EVT_MOUSEDOWN | EVT_MOUSEAUTO | EVT_MOUSEUP | EVT_MOUSEMOVE), - EVT_MOUSECLICK = (EVT_MOUSEDOWN | EVT_MOUSEUP), - EVT_JOYEVT = (EVT_JOYCLICK | EVT_JOYMOVE), - EVT_EVERYEVT = 0x7FFFFFFF - } EVT_eventMaskType; - -/**************************************************************************** -REMARKS: -Structure describing the information contained in an event extracted from -the event queue. - -HEADER: -event.h - -MEMBERS: -which - Window identifier for message for use by high level window manager - code (i.e. MegaVision GUI or Windows API). -what - Type of event that occurred. Will be one of the values defined by - the EVT_eventType enumeration. -when - Time that the event occurred in milliseconds since startup -where_x - X coordinate of the mouse cursor location at the time of the event - (in screen coordinates). For joystick events this represents - the position of the first joystick X axis. -where_y - Y coordinate of the mouse cursor location at the time of the event - (in screen coordinates). For joystick events this represents - the position of the first joystick Y axis. -relative_x - Relative movement of the mouse cursor in the X direction (in - units of mickeys, or 1/200th of an inch). For joystick events - this represents the position of the second joystick X axis. -relative_y - Relative movement of the mouse cursor in the Y direction (in - units of mickeys, or 1/200th of an inch). For joystick events - this represents the position of the second joystick Y axis. -message - Event specific message for the event. For use events this can be - any user specific information. For keyboard events this contains - the ASCII code in bits 0-7, the keyboard scan code in bits 8-15 and - the character repeat count in bits 16-30. You can use the - EVT_asciiCode, EVT_scanCode and EVT_repeatCount macros to extract - this information from the message field. For mouse events this - contains information about which button was pressed, and will be a - combination of the flags defined by the EVT_eventMouseMaskType - enumeration. For joystick events, this conatins information - about which buttons were pressed, and will be a combination of - the flags defined by the EVT_eventJoyMaskType enumeration. -modifiers - Contains additional information about the state of the keyboard - shift modifiers (Ctrl, Alt and Shift keys) when the event - occurred. For mouse events it will also contain the state of - the mouse buttons. Will be a combination of the values defined - by the EVT_eventModMaskType enumeration. -next - Internal use; do not use. -prev - Internal use; do not use. -****************************************************************************/ -typedef struct { - ulong which; - ulong what; - ulong when; - int where_x; - int where_y; - int relative_x; - int relative_y; - ulong message; - ulong modifiers; - int next; - int prev; - } event_t; - -/**************************************************************************** -REMARKS: -Structure describing an entry in the code page table. A table of translation -codes for scan codes to ASCII codes is provided in this table to be used -by the keyboard event libraries. On some OS'es the keyboard translation is -handled by the OS, but for DOS and embedded systems you must register a -different code page translation table if you want to support keyboards -other than the US English keyboard (the default). - -NOTE: Entries in code page tables *must* be in ascending order for the - scan codes as we do a binary search on the tables for the ASCII - code equivalents. - -HEADER: -event.h - -MEMBERS: -scanCode - Scan code to translate (really the virtual scan code). -asciiCode - ASCII code for this scan code. -****************************************************************************/ -typedef struct { - uchar scanCode; - uchar asciiCode; - } codepage_entry_t; - -/**************************************************************************** -REMARKS: -Structure describing a complete code page translation table. The table -contains translation tables for normal keys, shifted keys and ctrl keys. -The Ctrl key always has precedence over the shift table, and the shift -table is used when the shift key is down or the CAPSLOCK key is down. - -HEADER: -event.h - -MEMBERS: -name - Name of the code page table (ie: "US English") -normal - Code page for translating normal keys -normalLen - Length of normal translation table -caps - Code page for translating keys when CAPSLOCK is down -capsLen - Length of CAPSLOCK translation table -shift - Code page for shifted keys (ie: shift key is held down) -shiftLen - Length of shifted translation table -shiftCaps - Code page for shifted keys when CAPSLOCK is down -shiftCapsLen - Length of shifted CAPSLOCK translation table -ctrl - Code page for ctrl'ed keys (ie: ctrl key is held down) -ctrlLen - Length of ctrl'ed translation table -numPad - Code page for NUMLOCK'ed keypad keys -numPadLen - Length of NUMLOCK'ed translation table -****************************************************************************/ -typedef struct { - char name[20]; - codepage_entry_t *normal; - int normalLen; - codepage_entry_t *caps; - int capsLen; - codepage_entry_t *shift; - int shiftLen; - codepage_entry_t *shiftCaps; - int shiftCapsLen; - codepage_entry_t *ctrl; - int ctrlLen; - codepage_entry_t *numPad; - int numPadLen; - } codepage_t; - -/* {secret} */ -typedef ibool (EVTAPIP _EVT_userEventFilter)(event_t *evt); -/* {secret} */ -typedef void (EVTAPIP _EVT_mouseMoveHandler)(int x,int y); -/* {secret} */ -typedef void (EVTAPIP _EVT_heartBeatCallback)(void *params); - -/* Macro to find the size of a static array */ - -#define EVT_ARR_SIZE(a) (sizeof(a)/sizeof((a)[0])) - -#pragma pack() - -/*--------------------------- Global variables ----------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -/* Standard code page tables */ - -extern codepage_t _CP_US_English; - -/*------------------------- Function Prototypes ---------------------------*/ - -/* Public API functions for user applications */ - -ibool EVTAPI EVT_getNext(event_t *evt,ulong mask); -ibool EVTAPI EVT_peekNext(event_t *evt,ulong mask); -ibool EVTAPI EVT_post(ulong which,ulong what,ulong message,ulong modifiers); -void EVTAPI EVT_flush(ulong mask); -void EVTAPI EVT_halt(event_t *evt,ulong mask); -ibool EVTAPI EVT_isKeyDown(uchar scanCode); -void EVTAPI EVT_setMousePos(int x,int y); -void EVTAPI EVT_getMousePos(int *x,int *y); - -/* Function to enable/disable updating of keyboard LED status indicators */ - -void EVTAPI EVT_allowLEDS(ibool enable); - -/* Function to install a custom keyboard code page. Default is US English */ - -codepage_t *EVTAPI EVT_getCodePage(void); -void EVTAPI EVT_setCodePage(codepage_t *page); - -/* Functions for fine grained joystick calibration */ - -void EVTAPI EVT_pollJoystick(void); -int EVTAPI EVT_joyIsPresent(void); -void EVTAPI EVT_joySetUpperLeft(void); -void EVTAPI EVT_joySetLowerRight(void); -void EVTAPI EVT_joySetCenter(void); - -/* Install user supplied event filter callback */ - -void EVTAPI EVT_setUserEventFilter(_EVT_userEventFilter filter); - -/* Install user supplied event heartbeat callback function */ - -void EVTAPI EVT_setHeartBeatCallback(_EVT_heartBeatCallback callback,void *params); -void EVTAPI EVT_getHeartBeatCallback(_EVT_heartBeatCallback *callback,void **params); - -/* Internal functions to initialise and kill the event manager. MGL - * applications should never call these functions directly as the MGL - * libraries do it for you. - */ - -/* {secret} */ -void EVTAPI EVT_init(_EVT_mouseMoveHandler mouseMove); -/* {secret} */ -void EVTAPI EVT_setMouseRange(int xRes,int yRes); -/* {secret} */ -void EVTAPI EVT_suspend(void); -/* {secret} */ -void EVTAPI EVT_resume(void); -/* {secret} */ -void EVTAPI EVT_exit(void); - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif /* __cplusplus */ - -#endif /* __EVENT_H */ diff --git a/board/MAI/bios_emulator/scitech/include/mtrr.h b/board/MAI/bios_emulator/scitech/include/mtrr.h deleted file mode 100644 index b29812c..0000000 --- a/board/MAI/bios_emulator/scitech/include/mtrr.h +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Include file defining the external ring 0 helper functions -* needed by the MTRR module. These functions may be included -* directly for native ring 0 device drivers, or they may -* be calls down to a ring 0 helper device driver where -* appropriate (or the entire MTRR module may be located in -* the device driver if the device driver is 32-bit). -* -****************************************************************************/ - -#ifndef __MTRR_H -#define __MTRR_H - -#include "scitech.h" - -/*--------------------------- Function Prototypes -------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -/* Internal functions (requires ring 0 access or helper functions!) */ - -void MTRR_init(void); -int MTRR_enableWriteCombine(ulong base,ulong size,uint type); - -/* External assembler helper functions */ - -ibool _ASMAPI _MTRR_isRing0(void); -ulong _ASMAPI _MTRR_disableInt(void); -void _ASMAPI _MTRR_restoreInt(ulong flags); -ulong _ASMAPI _MTRR_saveCR4(void); -void _ASMAPI _MTRR_restoreCR4(ulong cr4Val); -uchar _ASMAPI _MTRR_getCx86(uchar reg); -void _ASMAPI _MTRR_setCx86(uchar reg,uchar data); -#ifdef __16BIT__ -void _ASMAPI _MTRR_readMSR(ulong reg, ulong far *eax, ulong far *edx); -#else -void _ASMAPI _MTRR_readMSR(ulong reg, ulong *eax, ulong *edx); -#endif -void _ASMAPI _MTRR_writeMSR(ulong reg, ulong eax, ulong edx); - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __MTRR_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pcilib.h b/board/MAI/bios_emulator/scitech/include/pcilib.h deleted file mode 100644 index 238f8ef..0000000 --- a/board/MAI/bios_emulator/scitech/include/pcilib.h +++ /dev/null @@ -1,413 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Header file for interface routines to the PCI bus. -* -****************************************************************************/ - -#ifndef __PCILIB_H -#define __PCILIB_H - -#include "scitech.h" - -/*---------------------- Macros and type definitions ----------------------*/ - -#pragma pack(1) - -/* Defines for PCIDeviceInfo.HeaderType */ - -typedef enum { - PCI_deviceType = 0x00, - PCI_bridgeType = 0x01, - PCI_cardBusBridgeType = 0x02, - PCI_multiFunctionType = 0x80 - } PCIHeaderTypeFlags; - -/* Defines for PCIDeviceInfo.Command */ - -typedef enum { - PCI_enableIOSpace = 0x0001, - PCI_enableMemorySpace = 0x0002, - PCI_enableBusMaster = 0x0004, - PCI_enableSpecialCylces = 0x0008, - PCI_enableWriteAndInvalidate = 0x0010, - PCI_enableVGACompatiblePalette = 0x0020, - PCI_enableParity = 0x0040, - PCI_enableWaitCycle = 0x0080, - PCI_enableSerr = 0x0100, - PCI_enableFastBackToBack = 0x0200 - } PCICommandFlags; - -/* Defines for PCIDeviceInfo.Status */ - -typedef enum { - PCI_statusCapabilitiesList = 0x0010, - PCI_status66MhzCapable = 0x0020, - PCI_statusUDFSupported = 0x0040, - PCI_statusFastBackToBack = 0x0080, - PCI_statusDataParityDetected = 0x0100, - PCI_statusDevSel = 0x0600, - PCI_statusSignaledTargetAbort = 0x0800, - PCI_statusRecievedTargetAbort = 0x1000, - PCI_statusRecievedMasterAbort = 0x2000, - PCI_statusSignaledSystemError = 0x4000, - PCI_statusDetectedParityError = 0x8000 - } PCIStatusFlags; - -/* PCI capability IDs */ - -typedef enum { - PCI_capsPowerManagement = 0x01, - PCI_capsAGP = 0x02, - PCI_capsMSI = 0x05 - } PCICapsType; - -/* PCI AGP rate definitions */ - -typedef enum { - PCI_AGPRate1X = 0x1, - PCI_AGPRate2X = 0x2, - PCI_AGPRate4X = 0x4 - } PCIAGPRateType; - -/* NOTE: We define all bitfield's as uint's, specifically so that the IBM - * Visual Age C++ compiler does not complain. We need them to be - * 32-bits wide, and this is the width of an unsigned integer, but - * we can't use a ulong to make this explicit or we get errors. - */ - -/* Structure defining a PCI slot identifier */ - -typedef union { - struct { - uint Zero:2; - uint Register:6; - uint Function:3; - uint Device:5; - uint Bus:8; - uint Reserved:7; - uint Enable:1; - } p; - ulong i; - } PCIslot; - -/* Structure defining the regular (type 0) PCI configuration register - * layout. We use this in a union below so we can describe all types of - * PCI configuration spaces with a single structure. - */ - -typedef struct { - ulong BaseAddress10; - ulong BaseAddress14; - ulong BaseAddress18; - ulong BaseAddress1C; - ulong BaseAddress20; - ulong BaseAddress24; - ulong CardbusCISPointer; - ushort SubSystemVendorID; - ushort SubSystemID; - ulong ROMBaseAddress; - uchar CapabilitiesPointer; - uchar reserved1; - uchar reserved2; - uchar reserved3; - ulong reserved4; - uchar InterruptLine; - uchar InterruptPin; - uchar MinimumGrant; - uchar MaximumLatency; - - /* These are not in the actual config space, but we enumerate them */ - ulong BaseAddress10Len; - ulong BaseAddress14Len; - ulong BaseAddress18Len; - ulong BaseAddress1CLen; - ulong BaseAddress20Len; - ulong BaseAddress24Len; - ulong ROMBaseAddressLen; - } PCIType0Info; - -/* Structure defining PCI to PCI bridge (type 1) PCI configuration register - * layout. We use this in a union below so we can describe all types of - * PCI configuration spaces with a single structure. - */ - -typedef struct { - ulong BaseAddress10; - ulong BaseAddress14; - uchar PrimaryBusNumber; - uchar SecondayBusNumber; - uchar SubordinateBusNumber; - uchar SecondaryLatencyTimer; - uchar IOBase; - uchar IOLimit; - ushort SecondaryStatus; - ushort MemoryBase; - ushort MemoryLimit; - ushort PrefetchableMemoryBase; - ushort PrefetchableMemoryLimit; - ulong PrefetchableBaseHi; - ulong PrefetchableLimitHi; - ushort IOBaseHi; - ushort IOLimitHi; - uchar CapabilitiesPointer; - uchar reserved1; - uchar reserved2; - uchar reserved3; - ulong ROMBaseAddress; - uchar InterruptLine; - uchar InterruptPin; - ushort BridgeControl; - } PCIType1Info; - -/* PCI to CardBus bridge (type 2) configuration information */ -typedef struct { - ulong SocketRegistersBaseAddress; - uchar CapabilitiesPointer; - uchar reserved1; - ushort SecondaryStatus; - uchar PrimaryBus; - uchar SecondaryBus; - uchar SubordinateBus; - uchar SecondaryLatency; - struct { - ulong Base; - ulong Limit; - } Range[4]; - uchar InterruptLine; - uchar InterruptPin; - ushort BridgeControl; - } PCIType2Info; - -/* Structure defining the PCI configuration space information for a - * single PCI device on the PCI bus. We enumerate all this information - * for all PCI devices on the bus. - */ - -typedef struct { - ulong dwSize; - PCIslot slot; - ulong mech1; - ushort VendorID; - ushort DeviceID; - ushort Command; - ushort Status; - uchar RevID; - uchar Interface; - uchar SubClass; - uchar BaseClass; - uchar CacheLineSize; - uchar LatencyTimer; - uchar HeaderType; - uchar BIST; - union { - PCIType0Info type0; - PCIType1Info type1; - PCIType2Info type2; - } u; - } PCIDeviceInfo; - -/* PCI Capability header structure. All PCI capabilities have the - * following header. - * - * capsID is used to identify the type of the structure as define above. - * - * next is the offset in PCI configuration space (0x40-0xFC) of the - * next capability structure in the list, or 0x00 if there are no more - * entries. - */ - -typedef struct { - uchar capsID; - uchar next; - } PCICapsHeader; - -/* Structure defining the PCI AGP status register contents */ - -typedef struct { - uint rate:3; - uint rsvd1:1; - uint fastWrite:1; - uint fourGB:1; - uint rsvd2:3; - uint sideBandAddressing:1; - uint rsvd3:14; - uint requestQueueDepthMaximum:8; - } PCIAGPStatus; - -/* Structure defining the PCI AGP command register contents */ - -typedef struct { - uint rate:3; - uint rsvd1:1; - uint fastWriteEnable:1; - uint fourGBEnable:1; - uint rsvd2:2; - uint AGPEnable:1; - uint SBAEnable:1; - uint rsvd3:14; - uint requestQueueDepth:8; - } PCIAGPCommand; - -/* AGP Capability structure */ - -typedef struct { - PCICapsHeader h; - ushort majMin; - PCIAGPStatus AGPStatus; - PCIAGPCommand AGPCommand; - } PCIAGPCapability; - -/* Structure for obtaining the PCI IRQ routing information */ - -typedef struct { - uchar bus; - uchar device; - uchar linkA; - ushort mapA; - uchar linkB; - ushort mapB; - uchar linkC; - ushort mapC; - uchar linkD; - ushort mapD; - uchar slot; - uchar reserved; - } PCIRouteInfo; - -typedef struct { - ushort BufferSize; - PCIRouteInfo *DataBuffer; - } PCIRoutingOptionsBuffer; - -#define NUM_PCI_REG (sizeof(PCIDeviceInfo) / 4) - 10 -#define PCI_BRIDGE_CLASS 0x06 -#define PCI_HOST_BRIDGE_SUBCLASS 0x00 -#define PCI_EARLY_VGA_CLASS 0x00 -#define PCI_EARLY_VGA_SUBCLASS 0x01 -#define PCI_DISPLAY_CLASS 0x03 -#define PCI_DISPLAY_VGA_SUBCLASS 0x00 -#define PCI_DISPLAY_XGA_SUBCLASS 0x01 -#define PCI_DISPLAY_OTHER_SUBCLASS 0x80 -#define PCI_MM_CLASS 0x04 -#define PCI_AUDIO_SUBCLASS 0x01 - -/* Macros to detect specific classes of devices */ - -#define PCI_IS_3DLABS_NONVGA_CLASS(pci) \ - (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_OTHER_SUBCLASS) \ - && ((pci)->VendorID == 0x3D3D || (pci)->VendorID == 0x104C)) - -#define PCI_IS_DISPLAY_CLASS(pci) \ - (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_VGA_SUBCLASS) \ - || ((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_XGA_SUBCLASS) \ - || ((pci)->BaseClass == PCI_EARLY_VGA_CLASS && (pci)->SubClass == PCI_EARLY_VGA_SUBCLASS) \ - || PCI_IS_3DLABS_NONVGA_CLASS(pci)) - -/* Function codes to pass to PCI_accessReg */ - -#define PCI_READ_BYTE 0 -#define PCI_READ_WORD 1 -#define PCI_READ_DWORD 2 -#define PCI_WRITE_BYTE 3 -#define PCI_WRITE_WORD 4 -#define PCI_WRITE_DWORD 5 - -/* Macros to read/write PCI registers. These assume a global PCI array - * of device information. - */ - -#define PCI_readPCIRegB(index,device) \ - PCI_accessReg(index,0,0,&PCI[DeviceIndex[device]]) - -#define PCI_readPCIRegW(index,device) \ - PCI_accessReg(index,0,1,&PCI[DeviceIndex[device]]) - -#define PCI_readPCIRegL(index,device) \ - PCI_accessReg(index,0,2,&PCI[DeviceIndex[device]]) - -#define PCI_writePCIRegB(index,value,device) \ - PCI_accessReg(index,value,3,&PCI[DeviceIndex[device]]) - -#define PCI_writePCIRegW(index,value,device) \ - PCI_accessReg(index,value,4,&PCI[DeviceIndex[device]]) - -#define PCI_writePCIRegL(index,value,device) \ - PCI_accessReg(index,value,5,&PCI[DeviceIndex[device]]) - -#pragma pack() - -/*-------------------------- Function Prototypes --------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -/* Function to determine the number of PCI devices in the system */ - -int _ASMAPI PCI_getNumDevices(void); - -/* Function to enumerate all device on the PCI bus */ - -int _ASMAPI PCI_enumerate(PCIDeviceInfo info[]); - -/* Function to access PCI configuration registers */ - -ulong _ASMAPI PCI_accessReg(int index,ulong value,int func,PCIDeviceInfo *info); - -/* Function to get PCI IRQ routing options for a card */ - -int _ASMAPI PCI_getIRQRoutingOptions(int numDevices,PCIRouteInfo *buffer); - -/* Function to re-route the PCI IRQ setting for a device */ - -ibool _ASMAPI PCI_setHardwareIRQ(PCIDeviceInfo *info,uint intPin,uint IRQ); - -/* Function to generate a special cyle on the specified PCI bus */ - -void _ASMAPI PCI_generateSpecialCyle(uint bus,ulong specialCycleData); - -/* Function to determine the size of a PCI base address register */ - -ulong _ASMAPI PCI_findBARSize(int bar,PCIDeviceInfo *pci); - -/* Function to read a block of PCI configuration space registers */ - -void _ASMAPI PCI_readRegBlock(PCIDeviceInfo *info,int index,void *dst,int count); - -/* Function to write a block of PCI configuration space registers */ - -void _ASMAPI PCI_writeRegBlock(PCIDeviceInfo *info,int index,void *src,int count); - -/* Function to return the 32-bit PCI BIOS entry point */ - -ulong _ASMAPI PCIBIOS_getEntry(void); - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __PCILIB_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pm_help.h b/board/MAI/bios_emulator/scitech/include/pm_help.h deleted file mode 100644 index 536a2ba..0000000 --- a/board/MAI/bios_emulator/scitech/include/pm_help.h +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Win32, OS/2 -* -* Description: Include file for the SciTech Portability Manager 32-bit -* helper VxD for Windows 9x for and the 16-bit ring 0 -* helper device driver for OS/2. -* -* This file documents all the public services used by the -* SciTech Portability Manager library and SciTech Nucleus -* loader library. -* -****************************************************************************/ - -#ifndef __PMHELP_H -#define __PMHELP_H - -/* Include version information */ - -#include "sdd/sddver.h" -#define PMHELP_Major SDD_RELEASE_MAJOR -#define PMHELP_Minor SDD_RELEASE_MINOR -#define PMHELP_VERSION ((PMHELP_Major << 8) | PMHELP_Minor) - -#ifdef __OS2__ - -/**************************************************************************** -* Public OS/2 Support functions -****************************************************************************/ - -#include "scitech.h" -#include "nucleus/graphics.h" - -/* Name of device driver */ - -#define PMHELP_NAME (PSZ)"sddhelp$" - -/* Main IOCTL function to talk to device driver */ - -#define PMHELP_IOCTL 0x0080 - -/* Macro definition for defining IOCTL function control codes for the SDDHELP - * device driver for OS/2. Similar to that used for the DOS/Win32 version. - */ - -#define PMHELP_CTL_CODE(name,value) \ - PMHELP_##name = value - -typedef enum { - /* Version function used by all drivers */ - PMHELP_CTL_CODE(GETVER ,0x0001), - PMHELP_CTL_CODE(MAPPHYS ,0x0002), - PMHELP_CTL_CODE(ALLOCLOCKED ,0x0003), - PMHELP_CTL_CODE(FREELOCKED ,0x0004), - PMHELP_CTL_CODE(GETGDT32 ,0x0005), - PMHELP_CTL_CODE(MALLOCSHARED ,0x0007), - PMHELP_CTL_CODE(FREESHARED ,0x0008), - PMHELP_CTL_CODE(MAPTOPROCESS ,0x0009), - PMHELP_CTL_CODE(FREEPHYS ,0x000A), - PMHELP_CTL_CODE(FLUSHTLB ,0x000B), - PMHELP_CTL_CODE(SAVECR4 ,0x000C), - PMHELP_CTL_CODE(RESTORECR4 ,0x000D), - PMHELP_CTL_CODE(READMSR ,0x000E), - PMHELP_CTL_CODE(WRITEMSR ,0x000F), - PMHELP_CTL_CODE(GETPHYSICALADDR ,0x0010), - PMHELP_CTL_CODE(GETPHYSICALADDRRANGE ,0x0011), - PMHELP_CTL_CODE(LOCKPAGES ,0x0012), - PMHELP_CTL_CODE(UNLOCKPAGES ,0x0013), - PMHELP_CTL_CODE(GETSHAREDEXP ,0x0042), - PMHELP_CTL_CODE(SETSHAREDEXP ,0x0043), - PMHELP_CTL_CODE(GETSTACKSWITCHRTN ,0x0044), - PMHELP_CTL_CODE(GETBUILDNO ,0x0050), - } PMHELP_ctlCodes; - -#else - -/**************************************************************************** -* Public DOS/Windows Support functions -****************************************************************************/ - -#ifdef DEVICE_MAIN -#include -#define PMHELP_Init_Order (VDD_INIT_ORDER-1) -#define RETURN_LONGS(n) *p->dioc_bytesret = (n) * sizeof(ulong) -#endif /* DEVICE_MAIN */ -#include "scitech.h" -#include "nucleus/graphics.h" - -/* We connect to the SDDHELP.VXD module if it is staticly loaded (as part - * of SciTech Display Doctor), otherwise we dynamically load the PMHELP.VXD - * public helper VxD. - */ - -#define PMHELP_DeviceID 0x0000 -#define SDDHELP_DeviceID 0x3DF8 -#define VXDLDR_DeviceID 0x0027 -#define SDDHELP_MODULE "SDDHELP" -#define SDDHELP_NAME "SDDHELP.VXD" -#define PMHELP_MODULE "PMHELP" -#define PMHELP_NAME "PMHELP.VXD" -#define PMHELP_DDBNAME "pmhelp " -#define SDDHELP_MODULE_PATH "\\\\.\\" SDDHELP_MODULE -#define PMHELP_MODULE_PATH "\\\\.\\" PMHELP_MODULE -#define PMHELP_VXD_PATH "\\\\.\\" PMHELP_NAME - -/* Macro definition for defining IOCTL function control codes for the PMHELP - * device drivers for Windows 9x and NT. This macro is basically derived from - * the CTL_CODE macro in the Windows 2000 DDK, but we hard code it here to - * avoid having to #include any of the Windows 2000 DDK header files. We also - * define both a 16-bit and 32-bit version of the control code within the same - * macro to simplify future additions. - * - * Essentially the Win32 macro would normally expand to the following: - * - * CTL_CODE(FILE_DEVICE_VIDEO,0x800+value,METHOD_BUFFERED,FILE_ANY_ACCESS) - */ - -#define PMHELP_CTL_CODE(name,value) \ - PMHELP_##name = value, \ - PMHELP_##name##32 = ((0x23 << 16) | (0 << 14) | ((0x800+value) << 2) | (0)) - -typedef enum { - /* Include all the control codes. We keep them in a separate header - * file so we can include them in multiple places to make this - * more versatile. - */ - #include "pm_wctl.h" - } PMHELP_ctlCodes; - -/* For real mode VxD calls, we put the function number into the high - * order word of EAX, and a value of 0x4FFF in AX. This allows our - * VxD handler which is set up to handle Int 10's to recognise a native - * PMHELP API call from a real mode DOS program. - */ - -#ifdef REALMODE -#define API_NUM(num) (((ulong)(num) << 16) | 0x4FFF) -#else -#define API_NUM(num) (num) -#endif - -#endif /* !__OS2__ */ - -#endif /* __PMHELP_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pm_wctl.h b/board/MAI/bios_emulator/scitech/include/pm_wctl.h deleted file mode 100644 index 20aa15e..0000000 --- a/board/MAI/bios_emulator/scitech/include/pm_wctl.h +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Win32, OS/2 -* -* Description: Header file to define all the control codes for the DOS -* and Win32 device driver API's for calling from ring 3 -* into the ring 0 device drivers. -* -****************************************************************************/ - -/* Version function used by all drivers */ -PMHELP_CTL_CODE(GETVER ,0x0000), - -/* Functions used by obsolete 16-bit DOS TSR */ -PMHELP_CTL_CODE(RDREGB ,0x0003), -PMHELP_CTL_CODE(WRREGB ,0x0004), -PMHELP_CTL_CODE(RDREGW ,0x0005), -PMHELP_CTL_CODE(WRREGW ,0x0006), -PMHELP_CTL_CODE(RDREGL ,0x0008), -PMHELP_CTL_CODE(WRREGL ,0x0009), - -/* Functions used by obsolete WinDirect */ -PMHELP_CTL_CODE(MAPPHYS ,0x000F), -PMHELP_CTL_CODE(GETVESABUF ,0x0013), - -/* Functions used by PM library */ -PMHELP_CTL_CODE(DPMIINT86 ,0x0014), -PMHELP_CTL_CODE(INT86 ,0x0015), -PMHELP_CTL_CODE(INT86X ,0x0016), -PMHELP_CTL_CODE(CALLREALMODE ,0x0017), -PMHELP_CTL_CODE(ALLOCLOCKED ,0x0018), -PMHELP_CTL_CODE(FREELOCKED ,0x0019), -PMHELP_CTL_CODE(ENABLELFBCOMB ,0x001A), -PMHELP_CTL_CODE(GETPHYSICALADDR ,0x001B), -PMHELP_CTL_CODE(MALLOCSHARED ,0x001D), -PMHELP_CTL_CODE(FREESHARED ,0x001F), -PMHELP_CTL_CODE(LOCKDATAPAGES ,0x0020), -PMHELP_CTL_CODE(UNLOCKDATAPAGES ,0x0021), -PMHELP_CTL_CODE(LOCKCODEPAGES ,0x0022), -PMHELP_CTL_CODE(UNLOCKCODEPAGES ,0x0023), -PMHELP_CTL_CODE(GETCALLGATE ,0x0024), -PMHELP_CTL_CODE(SETCNTPATH ,0x0025), -PMHELP_CTL_CODE(GETPDB ,0x0026), -PMHELP_CTL_CODE(FLUSHTLB ,0x0027), -PMHELP_CTL_CODE(GETPHYSICALADDRRANGE ,0x0028), -PMHELP_CTL_CODE(ALLOCPAGE ,0x0029), -PMHELP_CTL_CODE(FREEPAGE ,0x002A), -PMHELP_CTL_CODE(ENABLERING3IOPL ,0x002B), -PMHELP_CTL_CODE(DISABLERING3IOPL ,0x002C), -PMHELP_CTL_CODE(GASETLOCALPATH ,0x002D), -PMHELP_CTL_CODE(GAGETEXPORTS ,0x002E), -PMHELP_CTL_CODE(GATHUNK ,0x002F), -PMHELP_CTL_CODE(SETNUCLEUSPATH ,0x0030), diff --git a/board/MAI/bios_emulator/scitech/include/pmapi.h b/board/MAI/bios_emulator/scitech/include/pmapi.h deleted file mode 100644 index 7ddace7..0000000 --- a/board/MAI/bios_emulator/scitech/include/pmapi.h +++ /dev/null @@ -1,1148 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Header file for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#ifndef __PMAPI_H -#define __PMAPI_H - -#include "scitech.h" -#include "pcilib.h" -#include "ztimerc.h" -#if !defined(__WIN32_VXD__) && !defined(__OS2_VDD__) && !defined(__NT_DRIVER__) -#include -#include -#endif - -/*--------------------------- Macros and Typedefs -------------------------*/ - -/* You will need to define one of the following before you compile this - * library for it to work correctly with the DOS extender that you are - * using when compiling for extended DOS: - * - * TNT - Phar Lap TNT DOS Extender - * DOS4GW - Rational DOS/4GW, DOS/4GW Pro, Causeway and PMODE/W - * DJGPP - DJGPP port of GNU C++ - * - * If none is specified, we will automatically determine which operating - * system is being targetted and the following will be defined (provided by - * scitech.h header file): - * - * __MSDOS16__ - Default for 16 bit MSDOS mode - * __MSDOS32__ - Default for 32 bit MSDOS - * __WINDOWS16__ - Default for 16 bit Windows - * __WINDOWS32__ - Default for 32 bit Windows - * - * One of the following will be defined automatically for you to select - * which memory model is in effect: - * - * REALMODE - 16 bit real mode (large memory model) - * PM286 - 16 protected mode (large memory model) - * PM386 - 32 protected mode (flat memory model) - */ - -#if defined(__UNIX__) && !defined(_MAX_PATH) -#define _MAX_PATH 256 -#endif - -#if defined(TNT) || defined(DOSX) || defined(X32VM) || defined(DPMI32) \ - || defined(DOS4GW) || defined(DJGPP) || defined(__WINDOWS32__) \ - || defined(__MSDOS32__) || defined(__UNIX__) || defined(__WIN32_VXD__) \ - || defined(__32BIT__) || defined(__SMX32__) || defined(__RTTARGET__) -#define PM386 -#elif defined(DPMI16) || defined(__WINDOWS16__) -#define PM286 -#else -#define REALMODE -#endif - -#pragma pack(1) - -/* Provide the typedefs for the PM_int386 functions, which issue native - * interrupts in real or protected mode and can pass extended registers - * around. - */ - -struct _PMDWORDREGS { - ulong eax,ebx,ecx,edx,esi,edi,cflag; - }; - -struct _PMWORDREGS { - ushort ax,ax_hi; - ushort bx,bx_hi; - ushort cx,cx_hi; - ushort dx,dx_hi; - ushort si,si_hi; - ushort di,di_hi; - ushort cflag,cflag_hi; - }; - -struct _PMBYTEREGS { - uchar al, ah; ushort ax_hi; - uchar bl, bh; ushort bx_hi; - uchar cl, ch; ushort cx_hi; - uchar dl, dh; ushort dx_hi; - }; - -typedef union { - struct _PMDWORDREGS e; - struct _PMWORDREGS x; - struct _PMBYTEREGS h; - } PMREGS; - -typedef struct { - ushort es; - ushort cs; - ushort ss; - ushort ds; - ushort fs; - ushort gs; - } PMSREGS; - -/* Provide definitions for the real mode register structures passed to - * the PM_int86() and PM_int86x() routines. Note that we provide our own - * functions to do this for 16-bit code that calls the PM_int386 functions. - */ - -typedef PMREGS RMREGS; -typedef PMSREGS RMSREGS; - -typedef struct { - long edi; - long esi; - long ebp; - long reserved; - long ebx; - long edx; - long ecx; - long eax; - short flags; - short es,ds,fs,gs,ip,cs,sp,ss; - } DPMI_regs; - -#ifdef __MSDOS__ -/* Register structure passed to PM_VxDCall function */ -typedef struct { - ulong eax; - ulong ebx; - ulong ecx; - ulong edx; - ulong esi; - ulong edi; - ushort ds,es; - } VXD_regs; -#endif - -#define PM_MAX_DRIVE 3 -#define PM_MAX_PATH 256 -#define PM_FILE_INVALID (void*)0xFFFFFFFF - -/* Structure for generic directory traversal and management. Also the same - * values are passed to PM_setFileAttr to change the file attributes. - */ - -typedef struct { - ulong dwSize; - ulong attrib; - ulong sizeLo; - ulong sizeHi; - char name[PM_MAX_PATH]; - } PM_findData; - -/* Macro to compute the byte offset of a field in a structure of type type */ - -#define PM_FIELD_OFFSET(type,field) ((long)&(((type*)0)->field)) - -/* Marcto to compute the address of the base of the structure given its type, - * and an address of a field within the structure. - */ - -#define PM_CONTAINING_RECORD(address, type, field) \ - ((type*)( \ - (char*)(address) - \ - (char*)(&((type*)0)->field))) - -/* Flags stored in the PM_findData structure, and also values passed to - * PM_setFileAttr to change the file attributes. - */ - -#define PM_FILE_NORMAL 0x00000000 -#define PM_FILE_READONLY 0x00000001 -#define PM_FILE_DIRECTORY 0x00000002 -#define PM_FILE_ARCHIVE 0x00000004 -#define PM_FILE_HIDDEN 0x00000008 -#define PM_FILE_SYSTEM 0x00000010 - -/* Flags returned by the PM_splitpath function */ - -#define PM_HAS_WILDCARDS 0x01 -#define PM_HAS_EXTENSION 0x02 -#define PM_HAS_FILENAME 0x04 -#define PM_HAS_DIRECTORY 0x08 -#define PM_HAS_DRIVE 0x10 - -/* Structure passed to the PM_setFileTime functions */ -typedef struct { - short sec; /* Seconds */ - short min; /* Minutes */ - short hour; /* Hour (0--23) */ - short day; /* Day of month (1--31) */ - short mon; /* Month (0--11) */ - short year; /* Year (calendar year minus 1900) */ - } PM_time; - -/* Define a macro for creating physical base addresses from segment:offset */ - -#define MK_PHYS(s,o) (((ulong)(s) << 4) + (ulong)(o)) - -/* Define the different types of modes supported. This is a global variable - * that can be used to determine the type at runtime which will contain - * one of these values. - */ - -typedef enum { - PM_realMode, - PM_286, - PM_386 - } PM_mode_enum; - -/* Define types passed to PM_enableWriteCombine */ - -#define PM_MTRR_UNCACHABLE 0 -#define PM_MTRR_WRCOMB 1 -#define PM_MTRR_WRTHROUGH 4 -#define PM_MTRR_WRPROT 5 -#define PM_MTRR_WRBACK 6 -#define PM_MTRR_MAX 6 - -/* Error codes returned by PM_enableWriteCombine */ - -#define PM_MTRR_ERR_OK 0 -#define PM_MTRR_NOT_SUPPORTED -1 -#define PM_MTRR_ERR_PARAMS -2 -#define PM_MTRR_ERR_NOT_4KB_ALIGNED -3 -#define PM_MTRR_ERR_BELOW_1MB -4 -#define PM_MTRR_ERR_NOT_ALIGNED -5 -#define PM_MTRR_ERR_OVERLAP -6 -#define PM_MTRR_ERR_TYPE_MISMATCH -7 -#define PM_MTRR_ERR_NONE_FREE -8 -#define PM_MTRR_ERR_NOWRCOMB -9 -#define PM_MTRR_ERR_NO_OS_SUPPORT -10 - -/* Values passed to the PM_DMACProgram function */ - -#define PM_DMA_READ_ONESHOT 0x44 /* One-shot DMA read */ -#define PM_DMA_WRITE_ONESHOT 0x48 /* One-shot DMA write */ -#define PM_DMA_READ_AUTOINIT 0x54 /* Auto-init DMA read */ -#define PM_DMA_WRITE_AUTOINIT 0x58 /* Auto-init DMA write */ - -/* Flags passed to suspend application callback */ - -#define PM_DEACTIVATE 1 -#define PM_REACTIVATE 2 - -/* Return codes that the application can return from the suspend application - * callback registered with the PM library. See the MGL documentation for - * more details. - */ -#define PM_SUSPEND_APP 0 -#define PM_NO_SUSPEND_APP 1 - -/**************************************************************************** -REMARKS: -This enumeration defines the type values passed to the PM_agpReservePhysical -function, to define how the physical memory mapping should be handled. - -The PM_agpUncached type indicates that the memory should be allocated as -uncached memory. - -The PM_agpWriteCombine type indicates that write combining should be enabled -for physical memory mapping. This is used for framebuffer write combing and -speeds up direct framebuffer writes to the memory. - -The PM_agpIntelDCACHE type indicates that memory should come from the Intel -i81x Display Cache (or DCACHE) memory pool. This flag is specific to the -Intel i810 and i815 controllers, and should not be passed for any other -controller type. - -HEADER: -pmapi.h - -MEMBERS: -PM_agpUncached - Indicates that the memory should be uncached -PM_agpWriteCombine - Indicates that the memory should be write combined -PM_agpIntelDCACHE - Indicates that the memory should come from DCACHE pool -****************************************************************************/ -typedef enum { - PM_agpUncached, - PM_agpWriteCombine, - PM_agpIntelDCACHE - } PM_agpMemoryType; - -/* Defines the size of an system memory page */ - -#define PM_PAGE_SIZE 4096 - -/* Type definition for a physical memory address */ - -typedef unsigned long PM_physAddr; - -/* Define a bad physical address returned by map physical functions */ - -#define PM_BAD_PHYS_ADDRESS 0xFFFFFFFF - -/* Type definition for the 12-byte lock handle for locking linear memory */ - -typedef struct { - ulong h[3]; - } PM_lockHandle; - -/* 'C' calling conventions always */ - -#define PMAPI _ASMAPI -#define PMAPIP _ASMAPIP - -/* Internal typedef to override DPMI_int86 handler */ - -typedef ibool (PMAPIP DPMI_handler_t)(DPMI_regs *regs); -void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler); - -/* Type definitions for a window handle for console modes */ - -#if defined(__DRIVER__) || defined(__WIN32_VXD__) || defined(__NT_DRIVER__) -typedef void *PM_HWND; /* Pointer for portable drivers */ -typedef void *PM_MODULE; /* Module handle for portable drivers */ -#elif defined(__WINDOWS__) -#ifdef DECLARE_HANDLE -typedef HWND PM_HWND; /* Real window handle */ -typedef HINSTANCE PM_MODULE; /* Win32 DLL handle */ -#else -typedef void *PM_HWND; /* Place holder if windows.h not included */ -typedef void *PM_MODULE; /* Place holder if windows.h not included */ -#endif -#elif defined(__USE_X11__) -typedef struct { - Window *window; - Display *display; - } PM_HWND; /* X11 window handle */ -#elif defined(__OS2__) -typedef void *PM_HWND; -typedef void *PM_MODULE; -#elif defined(__LINUX__) -typedef int PM_HWND; /* Console id for fullscreen Linux */ -typedef void *PM_MODULE; -#elif defined(__QNX__) -typedef int PM_HWND; /* Console id for fullscreen QNX */ -typedef void *PM_MODULE; -#elif defined(__RTTARGET__) -typedef int PM_HWND; /* Placeholder for RTTarget-32 */ -typedef void *PM_MODULE; -#elif defined(__REALDOS__) -typedef int PM_HWND; /* Placeholder for fullscreen DOS */ -typedef void *PM_MODULE; /* Placeholder for fullscreen DOS */ -#elif defined(__SMX32__) -typedef int PM_HWND; /* Placeholder for fullscreen SMX */ -typedef void *PM_MODULE; -#elif defined(__SNAP__) -typedef void *PM_HWND; -typedef void *PM_MODULE; -#else -#error PM library not ported to this platform yet! -#endif - -/* Type definition for code pointers */ - -typedef void (*__codePtr)(); - -/* Type definition for a C based interrupt handler */ - -typedef void (PMAPIP PM_intHandler)(void); -typedef ibool (PMAPIP PM_irqHandler)(void); - -/* Hardware IRQ handle used to save and restore the hardware IRQ */ - -typedef void *PM_IRQHandle; - -/* Type definition for the fatal cleanup handler */ - -typedef void (PMAPIP PM_fatalCleanupHandler)(void); - -/* Type defifinition for save state callback function */ - -typedef int (PMAPIP PM_saveState_cb)(int flags); - -/* Type definintion for enum write combined callback function */ - -typedef void (PMAPIP PM_enumWriteCombine_t)(ulong base,ulong length,uint type); - -/* Structure defining all the PM API functions as exported to - * the binary portable DLL's. - */ - -typedef struct { - ulong dwSize; - int (PMAPIP PM_getModeType)(void); - void * (PMAPIP PM_getBIOSPointer)(void); - void * (PMAPIP PM_getA0000Pointer)(void); - void * (PMAPIP PM_mapPhysicalAddr)(ulong base,ulong limit,ibool isCached); - void * (PMAPIP PM_mallocShared)(long size); - void * reserved1; - void (PMAPIP PM_freeShared)(void *ptr); - void * (PMAPIP PM_mapToProcess)(void *linear,ulong limit); - void * (PMAPIP PM_mapRealPointer)(uint r_seg,uint r_off); - void * (PMAPIP PM_allocRealSeg)(uint size,uint *r_seg,uint *r_off); - void (PMAPIP PM_freeRealSeg)(void *mem); - void * (PMAPIP PM_allocLockedMem)(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg); - void (PMAPIP PM_freeLockedMem)(void *p,uint size,ibool contiguous); - void (PMAPIP PM_callRealMode)(uint seg,uint off, RMREGS *regs,RMSREGS *sregs); - int (PMAPIP PM_int86)(int intno, RMREGS *in, RMREGS *out); - int (PMAPIP PM_int86x)(int intno, RMREGS *in, RMREGS *out,RMSREGS *sregs); - void (PMAPIP DPMI_int86)(int intno, DPMI_regs *regs); - void (PMAPIP PM_availableMemory)(ulong *physical,ulong *total); - void * (PMAPIP PM_getVESABuf)(uint *len,uint *rseg,uint *roff); - long (PMAPIP PM_getOSType)(void); - void (PMAPIP PM_fatalError)(const char *msg); - void (PMAPIP PM_setBankA)(int bank); - void (PMAPIP PM_setBankAB)(int bank); - void (PMAPIP PM_setCRTStart)(int x,int y,int waitVRT); - char * (PMAPIP PM_getCurrentPath)(char *path,int maxLen); - const char * (PMAPIP PM_getVBEAFPath)(void); - const char * (PMAPIP PM_getNucleusPath)(void); - const char * (PMAPIP PM_getNucleusConfigPath)(void); - const char * (PMAPIP PM_getUniqueID)(void); - const char * (PMAPIP PM_getMachineName)(void); - ibool (PMAPIP VF_available)(void); - void * (PMAPIP VF_init)(ulong baseAddr,int bankSize,int codeLen,void *bankFunc); - void (PMAPIP VF_exit)(void); - PM_HWND (PMAPIP PM_openConsole)(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen); - int (PMAPIP PM_getConsoleStateSize)(void); - void (PMAPIP PM_saveConsoleState)(void *stateBuf,PM_HWND hwndConsole); - void (PMAPIP PM_restoreConsoleState)(const void *stateBuf,PM_HWND hwndConsole); - void (PMAPIP PM_closeConsole)(PM_HWND hwndConsole); - void (PMAPIP PM_setOSCursorLocation)(int x,int y); - void (PMAPIP PM_setOSScreenWidth)(int width,int height); - int (PMAPIP PM_enableWriteCombine)(ulong base,ulong length,uint type); - void (PMAPIP PM_backslash)(char *filename); - int (PMAPIP PM_lockDataPages)(void *p,uint len,PM_lockHandle *lockHandle); - int (PMAPIP PM_unlockDataPages)(void *p,uint len,PM_lockHandle *lockHandle); - int (PMAPIP PM_lockCodePages)(__codePtr p,uint len,PM_lockHandle *lockHandle); - int (PMAPIP PM_unlockCodePages)(__codePtr p,uint len,PM_lockHandle *lockHandle); - ibool (PMAPIP PM_setRealTimeClockHandler)(PM_intHandler ih,int frequency); - void (PMAPIP PM_setRealTimeClockFrequency)(int frequency); - void (PMAPIP PM_restoreRealTimeClockHandler)(void); - ibool (PMAPIP PM_doBIOSPOST)(ushort axVal,ulong BIOSPhysAddr,void *BIOSPtr,ulong BIOSLen); - char (PMAPIP PM_getBootDrive)(void); - void (PMAPIP PM_freePhysicalAddr)(void *ptr,ulong limit); - uchar (PMAPIP PM_inpb)(int port); - ushort (PMAPIP PM_inpw)(int port); - ulong (PMAPIP PM_inpd)(int port); - void (PMAPIP PM_outpb)(int port,uchar val); - void (PMAPIP PM_outpw)(int port,ushort val); - void (PMAPIP PM_outpd)(int port,ulong val); - void * reserved2; - void (PMAPIP PM_setSuspendAppCallback)(PM_saveState_cb saveState); - ibool (PMAPIP PM_haveBIOSAccess)(void); - int (PMAPIP PM_kbhit)(void); - int (PMAPIP PM_getch)(void); - ibool (PMAPIP PM_findBPD)(const char *dllname,char *bpdpath); - ulong (PMAPIP PM_getPhysicalAddr)(void *p); - void (PMAPIP PM_sleep)(ulong milliseconds); - int (PMAPIP PM_getCOMPort)(int port); - int (PMAPIP PM_getLPTPort)(int port); - PM_MODULE (PMAPIP PM_loadLibrary)(const char *szDLLName); - void * (PMAPIP PM_getProcAddress)(PM_MODULE hModule,const char *szProcName); - void (PMAPIP PM_freeLibrary)(PM_MODULE hModule); - int (PMAPIP PCI_enumerate)(PCIDeviceInfo info[]); - ulong (PMAPIP PCI_accessReg)(int index,ulong value,int func,PCIDeviceInfo *info); - ibool (PMAPIP PCI_setHardwareIRQ)(PCIDeviceInfo *info,uint intPin,uint IRQ); - void (PMAPIP PCI_generateSpecialCyle)(uint bus,ulong specialCycleData); - void * reserved3; - ulong (PMAPIP PCIBIOS_getEntry)(void); - uint (PMAPIP CPU_getProcessorType)(void); - ibool (PMAPIP CPU_haveMMX)(void); - ibool (PMAPIP CPU_have3DNow)(void); - ibool (PMAPIP CPU_haveSSE)(void); - ibool (PMAPIP CPU_haveRDTSC)(void); - ulong (PMAPIP CPU_getProcessorSpeed)(ibool accurate); - void (PMAPIP ZTimerInit)(void); - void (PMAPIP LZTimerOn)(void); - ulong (PMAPIP LZTimerLap)(void); - void (PMAPIP LZTimerOff)(void); - ulong (PMAPIP LZTimerCount)(void); - void (PMAPIP LZTimerOnExt)(LZTimerObject *tm); - ulong (PMAPIP LZTimerLapExt)(LZTimerObject *tm); - void (PMAPIP LZTimerOffExt)(LZTimerObject *tm); - ulong (PMAPIP LZTimerCountExt)(LZTimerObject *tm); - void (PMAPIP ULZTimerOn)(void); - ulong (PMAPIP ULZTimerLap)(void); - void (PMAPIP ULZTimerOff)(void); - ulong (PMAPIP ULZTimerCount)(void); - ulong (PMAPIP ULZReadTime)(void); - ulong (PMAPIP ULZElapsedTime)(ulong start,ulong finish); - void (PMAPIP ULZTimerResolution)(ulong *resolution); - void * (PMAPIP PM_findFirstFile)(const char *filename,PM_findData *findData); - ibool (PMAPIP PM_findNextFile)(void *handle,PM_findData *findData); - void (PMAPIP PM_findClose)(void *handle); - void (PMAPIP PM_makepath)(char *p,const char *drive,const char *dir,const char *name,const char *ext); - int (PMAPIP PM_splitpath)(const char *fn,char *drive,char *dir,char *name,char *ext); - ibool (PMAPIP PM_driveValid)(char drive); - void (PMAPIP PM_getdcwd)(int drive,char *dir,int len); - void (PMAPIP PM_setFileAttr)(const char *filename,uint attrib); - ibool (PMAPIP PM_mkdir)(const char *filename); - ibool (PMAPIP PM_rmdir)(const char *filename); - uint (PMAPIP PM_getFileAttr)(const char *filename); - ibool (PMAPIP PM_getFileTime)(const char *filename,ibool gmtTime,PM_time *time); - ibool (PMAPIP PM_setFileTime)(const char *filename,ibool gmtTime,PM_time *time); - char * (PMAPIP CPU_getProcessorName)(void); - int (PMAPIP PM_getVGAStateSize)(void); - void (PMAPIP PM_saveVGAState)(void *stateBuf); - void (PMAPIP PM_restoreVGAState)(const void *stateBuf); - void (PMAPIP PM_vgaBlankDisplay)(void); - void (PMAPIP PM_vgaUnblankDisplay)(void); - void (PMAPIP PM_blockUntilTimeout)(ulong milliseconds); - void (PMAPIP _PM_add64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); - void (PMAPIP _PM_sub64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); - void (PMAPIP _PM_mul64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); - void (PMAPIP _PM_div64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); - void (PMAPIP _PM_shr64)(u32 a_low,s32 a_high,s32 shift,__i64 *result); - void (PMAPIP _PM_sar64)(u32 a_low,s32 a_high,s32 shift,__i64 *result); - void (PMAPIP _PM_shl64)(u32 a_low,s32 a_high,s32 shift,__i64 *result); - void (PMAPIP _PM_neg64)(u32 a_low,s32 a_high,__i64 *result); - ulong (PMAPIP PCI_findBARSize)(int bar,PCIDeviceInfo *pci); - void (PMAPIP PCI_readRegBlock)(PCIDeviceInfo *info,int index,void *dst,int count); - void (PMAPIP PCI_writeRegBlock)(PCIDeviceInfo *info,int index,void *src,int count); - void (PMAPIP PM_flushTLB)(void); - void (PMAPIP PM_useLocalMalloc)(void * (*malloc)(size_t size),void * (*calloc)(size_t nelem,size_t size),void * (*realloc)(void *ptr,size_t size),void (*free)(void *p)); - void * (PMAPIP PM_malloc)(size_t size); - void * (PMAPIP PM_calloc)(size_t nelem,size_t size); - void * (PMAPIP PM_realloc)(void *ptr,size_t size); - void (PMAPIP PM_free)(void *p); - ibool (PMAPIP PM_getPhysicalAddrRange)(void *p,ulong length,ulong *physAddress); - void * (PMAPIP PM_allocPage)(ibool locked); - void (PMAPIP PM_freePage)(void *p); - ulong (PMAPIP PM_agpInit)(void); - void (PMAPIP PM_agpExit)(void); - ibool (PMAPIP PM_agpReservePhysical)(ulong numPages,int type,void **physContext,PM_physAddr *physAddr); - ibool (PMAPIP PM_agpReleasePhysical)(void *physContext); - ibool (PMAPIP PM_agpCommitPhysical)(void *physContext,ulong numPages,ulong startOffset,PM_physAddr *physAddr); - ibool (PMAPIP PM_agpFreePhysical)(void *physContext,ulong numPages,ulong startOffset); - int (PMAPIP PCI_getNumDevices)(void); - void (PMAPIP PM_setLocalBPDPath)(const char *path); - void * (PMAPIP PM_loadDirectDraw)(int device); - void (PMAPIP PM_unloadDirectDraw)(int device); - PM_HWND (PMAPIP PM_getDirectDrawWindow)(void); - void (PMAPIP PM_doSuspendApp)(void); - } PM_imports; - -#pragma pack() - -/*---------------------------- Global variables ---------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -#ifdef __WIN32_VXD__ -#define VESA_BUF_SIZE 1024 -extern uchar *_PM_rmBufAddr; -#endif - -/* {secret} Pointer to global exports structure. - * Should not be used by application programs. - */ -extern PM_imports _VARAPI _PM_imports; - -/* {secret} */ -extern void * (*__PM_malloc)(size_t size); -/* {secret} */ -extern void * (*__PM_calloc)(size_t nelem,size_t size); -/* {secret} */ -extern void * (*__PM_realloc)(void *ptr,size_t size); -/* {secret} */ -extern void (*__PM_free)(void *p); - -/*--------------------------- Function Prototypes -------------------------*/ - -/* Routine to initialise the host side PM library. Note used from DLL's */ - -void PMAPI PM_init(void); - -/* Routine to return either PM_realMode, PM_286 or PM_386 */ - -int PMAPI PM_getModeType(void); - -/* Routine to return a selector to the BIOS data area at segment 0x40 */ - -void * PMAPI PM_getBIOSPointer(void); - -/* Routine to return a linear pointer to the VGA frame buffer memory */ - -void * PMAPI PM_getA0000Pointer(void); - -/* Routines to map/free physical memory into the current DS segment. In - * some environments (32-bit DOS is one), after the mapping has been - * allocated, it cannot be freed. Hence you should only allocate the - * mapping once and cache the value for use by other parts of your - * application. If the mapping cannot be createed, this function will - * return a NULL pointer. - * - * This routine will also work for memory addresses below 1Mb, but the - * mapped address cannot cross the 1Mb boundary. - */ - -void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached); -void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit); - -/* Routine to determine the physical address of a linear address. It is - * up to the caller to ensure the entire address range for a linear - * block of memory is page aligned if that is required. - */ - -ulong PMAPI PM_getPhysicalAddr(void *p); -ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress); - -/* Routines for memory allocation. By default these functions use the regular - * C runtime library malloc/free functions, but you can use the - * PM_useLocalMalloc function to override the default memory allocator with - * your own memory allocator. This will ensure that all memory allocation - * used by SciTech products will use your overridden memory allocator - * functions. - * - * Note that BPD files automatically map the C runtime library - * malloc/calloc/realloc/free calls from inside the BPD to the PM library - * versions by default. - */ - -void PMAPI PM_useLocalMalloc(void * (*malloc)(size_t size),void * (*calloc)(size_t nelem,size_t size),void * (*realloc)(void *ptr,size_t size),void (*free)(void *p)); -void * PMAPI PM_malloc(size_t size); -void * PMAPI PM_calloc(size_t nelem,size_t size); -void * PMAPI PM_realloc(void *ptr,size_t size); -void PMAPI PM_free(void *p); - -/* Routine to allocate a memory block in the global shared region that - * is common to all tasks and accessible from ring 0 code. - */ - -void * PMAPI PM_mallocShared(long size); - -/* Routine to free the allocated shared memory block */ - -void PMAPI PM_freeShared(void *ptr); - -/* Attach a previously allocated linear mapping to a new process */ - -void * PMAPI PM_mapToProcess(void *linear,ulong limit); - -/* Macros to extract byte, word and long values from a char pointer */ - -#define PM_getByte(p) *((volatile uchar*)(p)) -#define PM_getWord(p) *((volatile ushort*)(p)) -#define PM_getLong(p) *((volatile ulong*)(p)) -#define PM_setByte(p,v) PM_getByte(p) = (v) -#define PM_setWord(p,v) PM_getWord(p) = (v) -#define PM_setLong(p,v) PM_getLong(p) = (v) - -/* Routine for accessing a low 1Mb memory block. You dont need to free this - * pointer, but in 16 bit protected mode the selector allocated will be - * re-used the next time this routine is called. - */ - -void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off); - -/* Routine to allocate a block of conventional memory below the 1Mb - * limit so that it can be accessed from real mode. Ensure that you free - * the segment when you are done with it. - * - * This routine returns a selector and offset to the segment that has been - * allocated, and also returns the real mode segment and offset which can - * be passed to real mode routines. Will return 0 if memory could not be - * allocated. - * - * Please note that with some DOS extenders, memory allocated with the - * following function cannot be freed, hence it will be allocated for the - * life of your program. Thus if you need to call a bunch of different - * real-mode routines in your program, allocate a single large buffer at - * program startup that can be re-used throughout the program execution. - */ - -void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off); -void PMAPI PM_freeRealSeg(void *mem); - -/* Routine to allocate a block of locked memory, and return both the - * linear and physical addresses of the memory. You should always - * allocate locked memory blocks in page sized chunks (ie: 4K on IA32). - * If the memory is not contiguous, you will need to use the - * PM_getPhysicalAddr function to get the physical address of linear - * pages within the memory block (the returned physical address will be - * for the first address in the memory block only). - */ - -void * PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg); -void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous); - -/* Routine to allocate and free paged sized blocks of shared memory. - * Addressable from all processes, but not from a ring 0 context - * under OS/2. Note that under OS/2 PM_mapSharedPages must be called - * to map the memory blocks into the shared memory address space - * of each connecting process. - */ - -void * PMAPI PM_allocPage(ibool locked); -void PMAPI PM_freePage(void *p); -#ifdef __OS2__ -void PMAPI PM_mapSharedPages(void); -#endif - -/* Routine to return true if we have access to the BIOS on the host OS */ - -ibool PMAPI PM_haveBIOSAccess(void); - -/* Routine to call a real mode assembly language procedure. Register - * values are passed in and out in the 'regs' and 'sregs' structures. We - * do not provide any method of copying data from the protected mode stack - * to the real mode stack, so if you need to pass data to real mode, you will - * need to write a real mode assembly language hook to recieve the values - * in registers, and to pass the data through a real mode block allocated - * with the PM_allocRealSeg() routine. - */ - -void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *regs,RMSREGS *sregs); - -/* Routines to generate real mode interrupts using the same interface that - * is used by int86() and int86x() in realmode. This routine is need to - * call certain BIOS and DOS functions that are not supported by some - * DOS extenders. No translation is done on any of the register values, - * so they must be correctly set up and translated by the calling program. - * - * Normally the DOS extenders will allow you to use the normal int86() - * function directly and will pass on unhandled calls to real mode to be - * handled by the real mode handler. However calls to int86x() with real - * mode segment values to be loaded will cause a GPF if used with the - * standard int86x(), so you should use these routines if you know you - * want to call a real mode handler. - */ - -int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out); -int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out,RMSREGS *sregs); - -/* Routine to generate a real mode interrupt. This is identical to the - * above function, but takes a DPMI_regs structure for the registers - * which has a lot more information. It is only available from 32-bit - * protected mode. - */ - -void PMAPI DPMI_int86(int intno, DPMI_regs *regs); - -/* Function to return the amount of available physical and total memory. - * The results of this function are *only* valid before you have made any - * calls to malloc() and free(). If you need to keep track of exactly how - * much memory is currently allocated, you need to call this function to - * get the total amount of memory available and then keep track of - * the available memory every time you call malloc() and free(). - */ - -void PMAPI PM_availableMemory(ulong *physical,ulong *total); - -/* Return the address of a global VESA real mode transfer buffer for use - * by applications. - */ - -void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff); - -/* Handle fatal error conditions */ - -void PMAPI PM_fatalError(const char *msg); - -/* Function to set a cleanup error handler called when PM_fatalError - * is called. This allows us to the console back into a normal state - * if we get a failure from deep inside a BPD file. This function is - * not exported to BPD files, and is only used by code compiled for the - * OS. - */ - -void PMAPI PM_setFatalErrorCleanup(PM_fatalCleanupHandler cleanup); - -/* Return the OS type flag as defined in */ - -long PMAPI PM_getOSType(void); - -/* Functions to set a VBE bank via an Int 10h */ - -void PMAPI PM_setBankA(int bank); -void PMAPI PM_setBankAB(int bank); -void PMAPI PM_setCRTStart(int x,int y,int waitVRT); - -/* Return the current working directory */ - -char * PMAPI PM_getCurrentPath(char *path,int maxLen); - -/* Return paths to the VBE/AF and Nucleus directories */ - -const char * PMAPI PM_getVBEAFPath(void); -const char * PMAPI PM_getNucleusPath(void); -const char * PMAPI PM_getNucleusConfigPath(void); - -/* Find the path to a binary portable DLL */ - -void PMAPI PM_setLocalBPDPath(const char *path); -ibool PMAPI PM_findBPD(const char *dllname,char *bpdpath); - -/* Returns the drive letter of the boot drive for DOS, OS/2 and Windows */ - -char PMAPI PM_getBootDrive(void); - -/* Return a network unique machine identifier as a string */ - -const char * PMAPI PM_getUniqueID(void); - -/* Return the network machine name as a string */ - -const char * PMAPI PM_getMachineName(void); - -/* Functions to install and remove the virtual linear framebuffer - * emulation code. For unsupported DOS extenders and when running under - * a DPMI host like Windows or OS/2, this function will return a NULL. - */ - -ibool PMAPI VF_available(void); -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc); -void PMAPI VF_exit(void); - -/* Functions to wait for a keypress and read a key for command line - * environments such as DOS, Win32 console and Unix. - */ - -int PMAPI PM_kbhit(void); -int PMAPI PM_getch(void); - -/* Functions to create either a fullscreen or windowed console on the - * desktop, and to allow the resolution of fullscreen consoles to be - * changed on the fly without closing the console. For non-windowed - * environments (such as a Linux or OS/2 fullscreen console), these - * functions enable console graphics mode and restore console text mode. - * - * The suspend application callback is used to allow the application to - * save the state of the fullscreen console mode to allow temporary - * switching to another console or back to the regular GUI desktop. It - * is also called to restore the fullscreen graphics state after the - * fullscreen console regains the focus. - * - * The device parameter allows for the console to be opened on a different - * display controllers (0 is always the primary controller). - */ - -PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen); -int PMAPI PM_getConsoleStateSize(void); -void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole); -void PMAPI PM_setSuspendAppCallback(PM_saveState_cb saveState); -void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole); -void PMAPI PM_closeConsole(PM_HWND hwndConsole); - -/* Functions to modify OS console information */ - -void PMAPI PM_setOSCursorLocation(int x,int y); -void PMAPI PM_setOSScreenWidth(int width,int height); - -/* Function to emable Intel PPro/PII write combining */ - -int PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type); -int PMAPI PM_enumWriteCombine(PM_enumWriteCombine_t callback); - -/* Function to add a path separator to the end of a filename (if not present) */ - -void PMAPI PM_backslash(char *filename); - -/* Routines to lock and unlock regions of memory under a virtual memory - * environment. These routines _must_ be used to lock all hardware - * and mouse interrupt handlers installed, _AND_ any global data that - * these handler manipulate, so that they will always be present in memory - * to handle the incoming interrupts. - * - * Note that it is important to call the correct routine depending on - * whether the area being locked is code or data, so that under 32 bit - * PM we will get the selector value correct. - */ - -int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lockHandle); -int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lockHandle); -int PMAPI PM_lockCodePages(__codePtr p,uint len,PM_lockHandle *lockHandle); -int PMAPI PM_unlockCodePages(__codePtr p,uint len,PM_lockHandle *lockHandle); - -/* Routines to install and remove Real Time Clock interrupt handlers. The - * frequency of the real time clock can be changed by calling - * PM_setRealTimeClockFrequeny, and the value can be any power of 2 value - * from 2Hz to 8192Hz. - * - * Note that you _must_ lock the memory containing the interrupt - * handlers with the PM_lockPages() function otherwise you may encounter - * problems in virtual memory environments. - * - * NOTE: User space versions of the PM library should fail these functions. - */ - -ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih,int frequency); -void PMAPI PM_setRealTimeClockFrequency(int frequency); -void PMAPI PM_restoreRealTimeClockHandler(void); - -/* Routines to install and remove hardware interrupt handlers. - * - * Note that you _must_ lock the memory containing the interrupt - * handlers with the PM_lockPages() function otherwise you may encounter - * problems in virtual memory environments. - * - * NOTE: User space versions of the PM library should fail these functions. - */ - -PM_IRQHandle PMAPI PM_setIRQHandler(int IRQ,PM_irqHandler ih); -void PMAPI PM_restoreIRQHandler(PM_IRQHandle irqHandle); - -/* Functions to program DMA using the legacy ISA DMA controller */ - -void PMAPI PM_DMACEnable(int channel); -void PMAPI PM_DMACDisable(int channel); -void PMAPI PM_DMACProgram(int channel,int mode,ulong bufferPhys,int count); -ulong PMAPI PM_DMACPosition(int channel); - -/* Function to post secondary graphics controllers using the BIOS */ - -ibool PMAPI PM_doBIOSPOST(ushort axVal,ulong BIOSPhysAddr,void *mappedBIOS,ulong BIOSLen); - -/* Function to init the AGP functions and return the AGP aperture size in MB */ - -ulong PMAPI PM_agpInit(void); -void PMAPI PM_agpExit(void); - -/* Functions to reserve and release physical AGP memory ranges */ - -ibool PMAPI PM_agpReservePhysical(ulong numPages,int type,void **physContext,PM_physAddr *physAddr); -ibool PMAPI PM_agpReleasePhysical(void *physContext); - -/* Functions to commit and free physical AGP memory ranges */ - -ibool PMAPI PM_agpCommitPhysical(void *physContext,ulong numPages,ulong startOffset,PM_physAddr *physAddr); -ibool PMAPI PM_agpFreePhysical(void *physContext,ulong numPages,ulong startOffset); - -/* Functions to do I/O port manipulation directly from C code. These - * functions are portable and will work on any processor architecture - * to access I/O space registers on PCI devices. - */ - -uchar PMAPI PM_inpb(int port); -ushort PMAPI PM_inpw(int port); -ulong PMAPI PM_inpd(int port); -void PMAPI PM_outpb(int port,uchar val); -void PMAPI PM_outpw(int port,ushort val); -void PMAPI PM_outpd(int port,ulong val); - -/* Functions to determine the I/O port locations for COM and LPT ports. - * The functions are zero based, so for COM1 or LPT1 pass in a value of 0, - * for COM2 or LPT2 pass in a value of 1 etc. - */ - -int PMAPI PM_getCOMPort(int port); -int PMAPI PM_getLPTPort(int port); - -/* Internal functions that need prototypes */ - -void PMAPI _PM_getRMvect(int intno, long *realisr); -void PMAPI _PM_setRMvect(int intno, long realisr); -void PMAPI _PM_freeMemoryMappings(void); - -/* Function to override the default debug log file location */ - -void PMAPI PM_setDebugLog(const char *logFilePath); - -/* Function to put the process to sleep for the specified milliseconds */ - -void PMAPI PM_sleep(ulong milliseconds); - -/* Function to block until 'milliseconds' have passed since last call */ - -void PMAPI PM_blockUntilTimeout(ulong milliseconds); - -/* Functions for directory traversal and management */ - -void * PMAPI PM_findFirstFile(const char *filename,PM_findData *findData); -ibool PMAPI PM_findNextFile(void *handle,PM_findData *findData); -void PMAPI PM_findClose(void *handle); -void PMAPI PM_makepath(char *p,const char *drive,const char *dir,const char *name,const char *ext); -int PMAPI PM_splitpath(const char *fn,char *drive,char *dir,char *name,char *ext); -ibool PMAPI PM_driveValid(char drive); -void PMAPI PM_getdcwd(int drive,char *dir,int len); -uint PMAPI PM_getFileAttr(const char *filename); -void PMAPI PM_setFileAttr(const char *filename,uint attrib); -ibool PMAPI PM_getFileTime(const char *filename,ibool gmTime,PM_time *time); -ibool PMAPI PM_setFileTime(const char *filename,ibool gmTime,PM_time *time); -ibool PMAPI PM_mkdir(const char *filename); -ibool PMAPI PM_rmdir(const char *filename); - -/* Functions to handle loading OS specific shared libraries */ - -PM_MODULE PMAPI PM_loadLibrary(const char *szDLLName); -void * PMAPI PM_getProcAddress(PM_MODULE hModule,const char *szProcName); -void PMAPI PM_freeLibrary(PM_MODULE hModule); - -/* Functions and macros for 64-bit arithmetic */ - -void PMAPI _PM_add64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); -void PMAPI _PM_sub64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); -void PMAPI _PM_mul64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); -void PMAPI _PM_div64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); -void PMAPI _PM_shr64(u32 a_low,s32 a_high,s32 shift,__i64 *result); -void PMAPI _PM_sar64(u32 a_low,s32 a_high,s32 shift,__i64 *result); -void PMAPI _PM_shl64(u32 a_low,s32 a_high,s32 shift,__i64 *result); -void PMAPI _PM_neg64(u32 a_low,s32 a_high,__i64 *result); -#ifdef __NATIVE_INT64__ -#define PM_add64(r,a,b) (r) = (a) + (b) -#define PM_add64_32(r,a,b) (r) = (a) + (b) -#define PM_sub64(r,a,b) (r) = (a) - (b) -#define PM_sub64_32(r,a,b) (r) = (a) - (b) -#define PM_mul64(r,a,b) (r) = (a) * (b) -#define PM_mul64_32(r,a,b) (r) = (a) * (b) -#define PM_div64(r,a,b) (r) = (a) / (b) -#define PM_div64_32(r,a,b) (r) = (a) / (b) -#define PM_shr64(r,a,s) (r) = (a) >> (s) -#define PM_sar64(r,a,s) (r) = ((s64)(a)) >> (s) -#define PM_shl64(r,a,s) (r) = (u64)(a) << (s) -#define PM_neg64(r,a,s) (r) = -(a) -#define PM_not64(r,a,s) (r) = ~(a) -#define PM_eq64(a,b) (a) == (b) -#define PM_gt64(a,b) (a) > (b) -#define PM_lt64(a,b) (a) < (b) -#define PM_geq64(a,b) (a) >= (b) -#define PM_leq64(a,b) (a) <= (b) -#define PM_64to32(a) (u32)(a) -#define PM_64tos32(a) (s32)(a) -#define PM_set64(a,b,c) (a) = ((u64)(b) << 32) + (c) -#define PM_set64_32(a,b) (a) = (b) -#else -#define PM_add64(r,a,b) _PM_add64((a).low,(a).high,(b).low,(b).high,&(r)) -#define PM_add64_32(r,a,b) _PM_add64((a).low,(a).high,b,0,&(r)) -#define PM_sub64(r,a,b) _PM_sub64((a).low,(a).high,(b).low,(b).high,&(r)) -#define PM_sub64_32(r,a,b) _PM_sub64((a).low,(a).high,b,0,&(r)) -#define PM_mul64(r,a,b) _PM_mul64((a).low,(a).high,(b).low,(b).high,&(r)) -#define PM_mul64_32(r,a,b) _PM_mul64((a).low,(a).high,b,0,&(r)) -#define PM_div64(r,a,b) _PM_div64((a).low,(a).high,(b).low,(b).high,&(r)) -#define PM_div64_32(r,a,b) _PM_div64((a).low,(a).high,b,0,&(r)) -#define PM_shr64(r,a,s) _PM_shr64((a).low,(a).high,s,&(r)) -#define PM_sar64(r,a,s) _PM_sar64((a).low,(a).high,s,&(r)) -#define PM_shl64(r,a,s) _PM_shl64((a).low,(a).high,s,&(r)) -#define PM_neg64(r,a,s) _PM_neg64((a).low,(a).high,&(r)) -#define PM_not64(r,a,s) (r).low = ~(a).low, (r).high = ~(a).high -#define PM_eq64(a,b) ((a).low == (b).low && (a).high == (b).high) -#define PM_gt64(a,b) (((a).high > (b).high) || ((a).high == (b).high && (a).low > (b).low)) -#define PM_lt64(a,b) (((a).high < (b).high) || ((a).high == (b).high && (a).low < (b).low)) -#define PM_geq64(a,b) (PM_eq64(a,b) || PM_gt64(a,b)) -#define PM_leq64(a,b) (PM_eq64(a,b) || PM_lt64(a,b)) -#define PM_64to32(a) (u32)(a.low) -#define PM_64tos32(a) ((a).high < 0) ? -(a).low : (a).low) -#define PM_set64(a,b,c) (a).high = (b), (a).low = (c) -#define PM_set64_32(a,b) (a).high = 0, (a).low = (b) -#endif - -/* Function to enable IOPL access if required */ - -int PMAPI PM_setIOPL(int iopl); - -/* Function to flush the TLB and CPU caches */ - -void PMAPI PM_flushTLB(void); - -/* DOS specific fucntions */ - -#ifdef __MSDOS__ -uint PMAPI PMHELP_getVersion(void); -void PMAPI PM_VxDCall(VXD_regs *regs); -#endif - -/* Functions to save and restore the VGA hardware state */ - -int PMAPI PM_getVGAStateSize(void); -void PMAPI PM_saveVGAState(void *stateBuf); -void PMAPI PM_restoreVGAState(const void *stateBuf); -void PMAPI PM_vgaBlankDisplay(void); -void PMAPI PM_vgaUnblankDisplay(void); - -/* Functions to load and unload DirectDraw libraries. Only used on - * Windows platforms. - */ - -void * PMAPI PM_loadDirectDraw(int device); -void PMAPI PM_unloadDirectDraw(int device); -PM_HWND PMAPI PM_getDirectDrawWindow(void); -void PMAPI PM_doSuspendApp(void); - -/* Functions to install, start, stop and remove NT services. Valid only - * for Win32 apps running on Windows NT. - */ - -#ifdef __WINDOWS32__ -ulong PMAPI PM_installService(const char *szDriverName,const char *szServiceName,const char *szLoadGroup,ulong dwServiceType); -ulong PMAPI PM_startService(const char *szServiceName); -ulong PMAPI PM_stopService(const char *szServiceName); -ulong PMAPI PM_removeService(const char *szServiceName); -#endif - -/* Routines to generate native interrupts (ie: protected mode interrupts - * for protected mode apps) using an interface the same as that use by - * int86() and int86x() in realmode. These routines are required because - * many 32 bit compilers use different register structures and different - * functions causing major portability headaches. Thus we provide our - * own and solve it all in one fell swoop, and we also get a routine to - * put stuff into 32 bit registers from real mode ;-) - */ - -void PMAPI PM_segread(PMSREGS *sregs); -int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out); -int PMAPI PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs); - -/* Call the X86 emulator or the real BIOS in our test harness */ - -#if defined(TEST_HARNESS) && !defined(PMLIB) -#define PM_mapRealPointer(r_seg,r_off) _PM_imports.PM_mapRealPointer(r_seg,r_off) -#define PM_getVESABuf(len,rseg,roff) _PM_imports.PM_getVESABuf(len,rseg,roff) -#define PM_callRealMode(seg,off,regs,sregs) _PM_imports.PM_callRealMode(seg,off,regs,sregs) -#define PM_int86(intno,in,out) _PM_imports.PM_int86(intno,in,out) -#define PM_int86x(intno,in,out,sregs) _PM_imports.PM_int86x(intno,in,out,sregs) -#endif - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -/* Include OS extensions for interrupt handling */ - -#if defined(__REALDOS__) || defined(__SMX32__) -#include "pmint.h" -#endif - -#endif /* __PMAPI_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pmimp.h b/board/MAI/bios_emulator/scitech/include/pmimp.h deleted file mode 100644 index 817f5e6..0000000 --- a/board/MAI/bios_emulator/scitech/include/pmimp.h +++ /dev/null @@ -1,193 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Header file declaring all the PM imports structure for the -* current version of the PM library. Included in all code -* that needs to pass the PM imports to BPD files. -* -****************************************************************************/ - -PM_imports _VARAPI _PM_imports = { - sizeof(PM_imports), - PM_getModeType, - PM_getBIOSPointer, - PM_getA0000Pointer, - PM_mapPhysicalAddr, - PM_mallocShared, - NULL, - PM_freeShared, - PM_mapToProcess, - PM_mapRealPointer, - PM_allocRealSeg, - PM_freeRealSeg, - PM_allocLockedMem, - PM_freeLockedMem, - PM_callRealMode, - PM_int86, - PM_int86x, - DPMI_int86, - PM_availableMemory, - PM_getVESABuf, - PM_getOSType, - PM_fatalError, - PM_setBankA, - PM_setBankAB, - PM_setCRTStart, - PM_getCurrentPath, - PM_getVBEAFPath, - PM_getNucleusPath, - PM_getNucleusConfigPath, - PM_getUniqueID, - PM_getMachineName, - VF_available, - VF_init, - VF_exit, - PM_openConsole, - PM_getConsoleStateSize, - PM_saveConsoleState, - PM_restoreConsoleState, - PM_closeConsole, - PM_setOSCursorLocation, - PM_setOSScreenWidth, - PM_enableWriteCombine, - PM_backslash, - PM_lockDataPages, - PM_unlockDataPages, - PM_lockCodePages, - PM_unlockCodePages, - PM_setRealTimeClockHandler, - PM_setRealTimeClockFrequency, - PM_restoreRealTimeClockHandler, - PM_doBIOSPOST, - PM_getBootDrive, - PM_freePhysicalAddr, - PM_inpb, - PM_inpw, - PM_inpd, - PM_outpb, - PM_outpw, - PM_outpd, - NULL, - PM_setSuspendAppCallback, - PM_haveBIOSAccess, - PM_kbhit, - PM_getch, - PM_findBPD, - PM_getPhysicalAddr, - PM_sleep, - PM_getCOMPort, - PM_getLPTPort, - PM_loadLibrary, - PM_getProcAddress, - PM_freeLibrary, - PCI_enumerate, - PCI_accessReg, - PCI_setHardwareIRQ, - PCI_generateSpecialCyle, - NULL, - PCIBIOS_getEntry, - CPU_getProcessorType, - CPU_haveMMX, - CPU_have3DNow, - CPU_haveSSE, - CPU_haveRDTSC, - CPU_getProcessorSpeed, - ZTimerInit, - LZTimerOn, - LZTimerLap, - LZTimerOff, - LZTimerCount, - LZTimerOnExt, - LZTimerLapExt, - LZTimerOffExt, - LZTimerCountExt, - ULZTimerOn, - ULZTimerLap, - ULZTimerOff, - ULZTimerCount, - ULZReadTime, - ULZElapsedTime, - ULZTimerResolution, - PM_findFirstFile, - PM_findNextFile, - PM_findClose, - PM_makepath, - PM_splitpath, - PM_driveValid, - PM_getdcwd, - PM_setFileAttr, - PM_mkdir, - PM_rmdir, - PM_getFileAttr, - PM_getFileTime, - PM_setFileTime, - CPU_getProcessorName, - PM_getVGAStateSize, - PM_saveVGAState, - PM_restoreVGAState, - PM_vgaBlankDisplay, - PM_vgaUnblankDisplay, - PM_blockUntilTimeout, - _PM_add64, - _PM_sub64, - _PM_mul64, - _PM_div64, - _PM_shr64, - _PM_sar64, - _PM_shl64, - _PM_neg64, - PCI_findBARSize, - PCI_readRegBlock, - PCI_writeRegBlock, - PM_flushTLB, - PM_useLocalMalloc, - PM_malloc, - PM_calloc, - PM_realloc, - PM_free, - PM_getPhysicalAddrRange, - PM_allocPage, - PM_freePage, - PM_agpInit, - PM_agpExit, - PM_agpReservePhysical, - PM_agpReleasePhysical, - PM_agpCommitPhysical, - PM_agpFreePhysical, - PCI_getNumDevices, - PM_setLocalBPDPath, -#ifdef __WINDOWS32__ - PM_loadDirectDraw, - PM_unloadDirectDraw, - PM_getDirectDrawWindow, - PM_doSuspendApp, -#else - NULL, - NULL, - NULL, - NULL, -#endif - }; diff --git a/board/MAI/bios_emulator/scitech/include/pmint.h b/board/MAI/bios_emulator/scitech/include/pmint.h deleted file mode 100644 index 7d76dad..0000000 --- a/board/MAI/bios_emulator/scitech/include/pmint.h +++ /dev/null @@ -1,211 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Real mode and 16/32 bit Protected Mode -* -* Description: Header file for the interrupt handling extensions to the OS -* Portability Manager Library. These extensions includes -* simplified interrupt handling, allowing all common interrupt -* handlers to be hooked and handled directly with normal C -* functions, both in 16 bit and 32 bit modes. Note however that -* simplified handling does not mean slow performance! All low -* level interrupt handling is done efficiently in assembler -* for speed (well actually necessary to insulate the -* application from the lack of far pointers in 32 bit PM). The -* interrupt handlers currently supported are: -* -* Mouse (0x33 callback) -* Timer Tick (0x8) -* Keyboard (0x9 and 0x15) -* Control C/Break (0x23/0x1B) -* Critical Error (0x24) -* -****************************************************************************/ - -#ifndef __PMINT_H -#define __PMINT_H - -/*--------------------------- Macros and Typedefs -------------------------*/ - -#ifdef __SMX32__ -/* PC interrupts (Ensure consistent with pme.inc) */ -#define PM_IRQ0 0x40 -#define PM_IRQ1 (PM_IRQ0+1) -#define PM_IRQ6 (PM_IRQ0+6) -#define PM_IRQ14 (PM_IRQ0+14) -#endif - -/* Define the different types of interrupt handlers that we support */ - -typedef uint (PMAPIP PM_criticalHandler)(uint axValue,uint diValue); -typedef void (PMAPIP PM_breakHandler)(uint breakHit); -typedef short (PMAPIP PM_key15Handler)(short scanCode); -typedef void (PMAPIP PM_mouseHandler)(uint event, uint butstate,int x,int y,int mickeyX,int mickeyY); - -/* Create a type for representing far pointers in both 16 and 32 bit - * protected mode. - */ - -#ifdef PM386 -typedef struct { - long off; - short sel; - } PMFARPTR; -#define PMNULL {0,0} -#else -typedef void *PMFARPTR; -#define PMNULL NULL -#endif - -/*--------------------------- Function Prototypes -------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -/* Routine to load save default data segment selector value into a code - * segment variable, and another to load the value into the DS register. - */ - -void PMAPI PM_loadDS(void); -void PMAPI PM_saveDS(void); - -/* Routine to install a mouse interrupt handling routine. The - * mouse handler routine is a normal C function, and the PM library - * will take care of passing the correct parameters to the function, - * and switching to a local stack. - * - * Note that you _must_ lock the memory containing the mouse interrupt - * handler with the PM_lockPages() function otherwise you may encounter - * problems in virtual memory environments. - */ - -int PMAPI PM_setMouseHandler(int mask,PM_mouseHandler mh); -void PMAPI PM_restoreMouseHandler(void); - -/* Routine to reset the mouse driver, and re-install the current - * mouse interrupt handler if one was currently installed (since the - * mouse reset will automatically remove this handler. - */ - -void PMAPI PM_resetMouseDriver(int hardReset); - -/* Routine to reset the mouse driver, and re-install the current - * mouse interrupt handler if one was currently installed (since the - * mouse reset will automatically remove this handler. - */ - -void PMAPI PM_resetMouseDriver(int hardReset); - -/* Routines to install and remove timer interrupt handlers. - * - * Note that you _must_ lock the memory containing the interrupt - * handlers with the PM_lockPages() function otherwise you may encounter - * problems in virtual memory environments. - */ - -void PMAPI PM_setTimerHandler(PM_intHandler ih); -void PMAPI PM_chainPrevTimer(void); -void PMAPI PM_restoreTimerHandler(void); - -/* Routines to install and keyboard interrupt handlers. - * - * Note that you _must_ lock the memory containing the interrupt - * handlers with the PM_lockPages() function otherwise you may encounter - * problems in virtual memory environments. - */ - -void PMAPI PM_setKeyHandler(PM_intHandler ih); -void PMAPI PM_chainPrevKey(void); -void PMAPI PM_restoreKeyHandler(void); - -/* Routines to hook and unhook the alternate Int 15h keyboard intercept - * callout routine. Your event handler will need to return the following: - * - * scanCode - Let the BIOS process scan code (chains to previous handler) - * 0 - You have processed the scan code so flush from BIOS - * - * Note that this is not available under all DOS extenders, but does - * work under real mode, DOS4GW and X32-VM. It does not work under the - * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know! - */ - -void PMAPI PM_setKey15Handler(PM_key15Handler ih); -void PMAPI PM_restoreKey15Handler(void); - -/* Routines to install and remove the control c/break interrupt handlers. - * Interrupt handling is performed by the PM/Pro library, and you can call - * the supplied routines to test the status of the Ctrl-C and Ctrl-Break - * flags. If you pass the value TRUE for 'clearFlag' to these routines, - * the internal flags will be reset in order to catch another Ctrl-C or - * Ctrl-Break interrupt. - */ - -void PMAPI PM_installBreakHandler(void); -int PMAPI PM_ctrlCHit(int clearFlag); -int PMAPI PM_ctrlBreakHit(int clearFlag); -void PMAPI PM_restoreBreakHandler(void); - -/* Routine to install an alternate break handler that will call your - * code directly. This is not available under all DOS extenders, but does - * work under real mode, DOS4GW and X32-VM. It does not work under the - * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know! - * - * Note that you should either install one or the other, but not both! - */ - -void PMAPI PM_installAltBreakHandler(PM_breakHandler bh); - -/* Routines to install and remove the critical error handler. The interrupt - * is handled by the PM/Pro library, and the operation will always be failed. - * You can check the status of the critical error handler with the - * appropriate function. If you pass the value TRUE for 'clearFlag', the - * internal flag will be reset ready to catch another critical error. - */ - -void PMAPI PM_installCriticalHandler(void); -int PMAPI PM_criticalError(int *axValue, int *diValue, int clearFlag); -void PMAPI PM_restoreCriticalHandler(void); - -/* Routine to install an alternate critical handler that will call your - * code directly. This is not available under all DOS extenders, but does - * work under real mode, DOS4GW and X32-VM. It does not work under the - * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know! - * - * Note that you should either install one or the other, but not both! - */ - -void PMAPI PM_installAltCriticalHandler(PM_criticalHandler); - -/* Functions to manage protected mode only interrupt handlers */ - -void PMAPI PM_getPMvect(int intno, PMFARPTR *isr); -void PMAPI PM_setPMvect(int intno, PM_intHandler ih); -void PMAPI PM_restorePMvect(int intno, PMFARPTR isr); - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __PMINT_H */ diff --git a/board/MAI/bios_emulator/scitech/include/scitech.h b/board/MAI/bios_emulator/scitech/include/scitech.h deleted file mode 100644 index 8d5eee9..0000000 --- a/board/MAI/bios_emulator/scitech/include/scitech.h +++ /dev/null @@ -1,712 +0,0 @@ -/**************************************************************************** -* -* SciTech Multi-platform Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: any -* -* Description: General header file for operating system portable code. -* -****************************************************************************/ - -#ifndef __SCITECH_H -#define __SCITECH_H - -/* We have the following defines to identify the compilation environment: - * - * __16BIT__ Compiling for 16 bit code (any environment) - * __32BIT__ Compiling for 32 bit code (any environment) - * __MSDOS__ Compiling for MS-DOS (includes __WINDOWS16__, __WIN386__) - * __REALDOS__ Compiling for MS-DOS (excludes __WINDOWS16__) - * __MSDOS16__ Compiling for 16 bit MS-DOS - * __MSDOS32__ Compiling for 32 bit MS-DOS - * __WINDOWS__ Compiling for Windows - * __WINDOWS16__ Compiling for 16 bit Windows (__MSDOS__ also defined) - * __WINDOWS32__ Compiling for 32 bit Windows - * __WIN32_VXD__ Compiling for a 32-bit C based VxD - * __NT_DRIVER__ Compiling for a 32-bit C based NT device driver - * __OS2__ Compiling for OS/2 - * __OS2_16__ Compiling for 16 bit OS/2 - * __OS2_32__ Compiling for 32 bit OS/2 - * __UNIX__ Compiling for Unix - * __QNX__ Compiling for the QNX realtime OS (Unix compatible) - * __LINUX__ Compiling for the Linux OS (Unix compatible) - * __FREEBSD__ Compiling for the FreeBSD OS (Unix compatible) - * __BEOS__ Compiling for the BeOS (Unix compatible) - * __SMX32__ Compiling for the SMX 32-bit Real Time OS - * __ENEA_OSE__ Compiling for the OSE embedded OS - * __RTTARGET__ Compiling for the RTTarget 32-bit embedded OS - * __MACOS__ Compiling for the MacOS platform (PowerPC) - * __DRIVER__ Compiling for a 32-bit binary compatible driver - * __CONSOLE__ Compiling for a fullscreen OS console mode - * __SNAP__ Compiling as a Snap executeable or dynamic library - * - * __INTEL__ Compiling for Intel CPU's - * __ALPHA__ Compiling for DEC Alpha CPU's - * __MIPS__ Compiling for MIPS CPU's - * __PPC__ Compiling for PowerPC CPU's - * __MC68K__ Compiling for Motorola 680x0 - * - * __BIG_ENDIAN__ Compiling for a big endian processor - * - */ - -#ifdef __SC__ -#if __INTSIZE == 4 -#define __SC386__ -#endif -#endif - -/* Determine some things that are compiler specific */ - -#ifdef __GNUC__ -#ifdef __cplusplus -/* G++ currently fucks this up! */ -#define __cdecl -#define __stdcall -#else -#undef __cdecl -#undef __stdcall -#define __cdecl __attribute__ ((cdecl)) -#define __stdcall __attribute__ ((stdcall)) -#endif -#define __FLAT__ /* GCC is always 32 bit flat model */ -#define __HAS_BOOL__ /* Latest GNU C++ has ibool type */ -#define __HAS_LONG_LONG__ /* GNU C supports long long type */ -#include /* Bring in for definition of NULL */ -#endif - -#ifdef __BORLANDC__ -#if (__BORLANDC__ >= 0x500) || defined(CLASSLIB_DEFS_H) -#define __HAS_BOOL__ /* Borland C++ 5.0 defines ibool type */ -#endif -#if (__BORLANDC__ >= 0x502) && !defined(VTOOLSD) && !defined(__SMX32__) -#define __HAS_INT64__ /* Borland C++ 5.02 supports __int64 type */ -#endif -#endif - -#if defined(_MSC_VER) && !defined(__SC__) && !defined(VTOOLSD) && !defined(__SMX32__) -#define __HAS_INT64__ /* Visual C++ supports __int64 type */ -#endif - -#if defined(__WATCOMC__) && (__WATCOMC__ >= 1100) && !defined(VTOOLSD) && !defined(__SMX32__) -#define __HAS_INT64__ /* Watcom C++ 11.0 supports __int64 type */ -#endif - -/*--------------------------------------------------------------------------- - * Determine the compile time environment. This must be done for each - * supported platform so that we can determine at compile time the target - * environment, hopefully without requiring #define's from the user. - *-------------------------------------------------------------------------*/ - -/* 32-bit binary compatible driver. Compiled as Win32, but as OS neutral */ -#ifdef __DRIVER__ -#ifndef __32BIT__ -#define __32BIT__ -#endif -#undef __WINDOWS__ -#undef _WIN32 -#undef __WIN32__ -#undef __NT__ - -/* 32-bit Snap exe or dll. Compiled as Win32, but as OS neutral */ -#elif defined(__SNAP__) -#ifndef __32BIT__ -#define __32BIT__ -#endif -#undef __WINDOWS__ -#undef _WIN32 -#undef __WIN32__ -#undef __NT__ - -/* 32-bit Windows VxD compile environment */ -#elif defined(__vtoolsd_h_) || defined(VTOOLSD) -#include -#define __WIN32_VXD__ -#ifndef __32BIT__ -#define __32BIT__ -#endif -#define _MAX_PATH 256 -#undef __WINDOWS32__ - -/* 32-bit Windows NT driver compile environment: TODO!! */ -#elif defined(__NT_DRIVER__) -#include "ntdriver.h" -#ifndef __32BIT__ -#define __32BIT__ -#endif -#define _MAX_PATH 256 -#undef __WINDOWS32__ - -/* 32-bit SMX compile environment */ -#elif defined(__SMX32__) -#ifndef __MSDOS__ -#define __MSDOS__ -#endif -#ifndef __32BIT__ -#define __32BIT__ -#endif -#ifndef __CONSOLE__ -#define __CONSOLE__ -#endif - -/* 32-bit Enea OSE environment */ -#elif defined(__ENEA_OSE__) -#ifndef __32BIT__ -#define __32BIT__ -#endif -#ifndef __CONSOLE__ -#define __CONSOLE__ -#endif - -/* 32-bit RTTarget-32 environment */ -#elif defined(__RTTARGET__) -#ifndef __32BIT__ -#define __32BIT__ -#endif -#ifndef __CONSOLE__ -#define __CONSOLE__ -#endif - -/* 32-bit extended DOS compile environment */ -#elif defined(__MSDOS__) || defined(__MSDOS32__) || defined(__DOS__) || defined(__DPMI32__) || (defined(M_I86) && (!defined(__SC386__) && !defined(M_I386))) || defined(TNT) -#ifndef __MSDOS__ -#define __MSDOS__ -#endif -#if defined(__MSDOS32__) || defined(__386__) || defined(__FLAT__) || defined(__NT__) || defined(__SC386__) -#ifndef __MSDOS32__ -#define __MSDOS32__ -#endif -#ifndef __32BIT__ -#define __32BIT__ -#endif -#ifndef __REALDOS__ -#define __REALDOS__ -#endif -#ifndef __CONSOLE__ -#define __CONSOLE__ -#endif - -/* 16-bit Windows compile environment */ -#elif (defined(_Windows) || defined(_WINDOWS)) && !defined(__DPMI16__) -#ifndef __16BIT__ -#define __16BIT__ -#endif -#ifndef __WINDOWS16__ -#define __WINDOWS16__ -#endif -#ifndef __WINDOWS__ -#define __WINDOWS__ -#endif -#ifndef __MSDOS__ -#define __MSDOS__ -#endif - -/* 16-bit DOS compile environment */ -#else -#ifndef __16BIT__ -#define __16BIT__ -#endif -#ifndef __MSDOS16__ -#define __MSDOS16__ -#endif -#ifndef __REALDOS__ -#define __REALDOS__ -#endif -#ifndef __CONSOLE__ -#define __CONSOLE__ -#endif -#endif - -/* 32-bit Windows compile environment */ -#elif defined(WIN32) || defined(_WIN32) || defined(__WIN32__) || defined(__NT__) -#ifndef __32BIT__ -#define __32BIT__ -#endif -#ifndef __WINDOWS32__ -#define __WINDOWS32__ -#endif -#ifndef _WIN32 -#define _WIN32 /* Microsoft Win32 SDK headers use _WIN32 */ -#endif -#ifndef WIN32 -#define WIN32 /* OpenGL headers use WIN32 */ -#endif -#ifndef __WINDOWS__ -#define __WINDOWS__ -#endif - -/* 32-bit OS/2 VDD compile environment */ -/* We're assuming (for now) that CL386 must be used */ -#elif defined(MSDOS) && defined(M_I386) -/* fixes necessary to compile with CL386 */ -#define __cdecl _cdecl -typedef unsigned int size_t; - -#include - -/* This should probably be somewhere else... */ -/* Inline eligible functions (we have no CRT libs for CL386) */ -#pragma intrinsic (strcpy, strcmp, strlen, strcat) -#pragma intrinsic (memcmp, memcpy, memset) - -#define __OS2_VDD__ -#ifndef __32BIT__ -#define __32BIT__ -#endif -#define CCHMAXPATH 256 -#define _MAX_PATH 256 -#ifndef __OS2__ -#define __OS2__ -#endif -#ifndef __OS2_32__ -#define __OS2_32__ -#endif - -/* 16-bit OS/2 compile environment */ -#elif defined(__OS2_16__) -#ifndef __OS2__ -#define __OS2__ -#endif -#ifndef __16BIT__ -#define __16BIT__ -#endif -#ifndef __OS2_PM__ -#ifndef __CONSOLE__ -#define __CONSOLE__ -#endif -#endif - -/* 32-bit OS/2 compile environment */ -#elif defined(__OS2__) || defined(__OS2_32__) -#ifndef __OS2__ -#define __OS2__ -#endif -#ifndef __OS2_32__ -#define __OS2_32__ -#endif -#ifndef __32BIT__ -#define __32BIT__ -#endif -#ifndef __OS2_PM__ -#ifndef __CONSOLE__ -#define __CONSOLE__ -#endif -#endif - -/* 32-bit QNX compile environment */ -#elif defined(__QNX__) -#ifndef __32BIT__ -#define __32BIT__ -#endif -#ifndef __UNIX__ -#define __UNIX__ -#endif -#ifdef __GNUC__ -#define stricmp strcasecmp -#endif -#if !defined(__PHOTON__) && !defined(__X11__) -#ifndef __CONSOLE__ -#define __CONSOLE__ -#endif -#endif - -/* 32-bit Linux compile environment */ -#elif defined(__LINUX__) || defined(linux) -#ifndef __LINUX__ -#define __LINUX__ -#endif -#ifndef __32BIT__ -#define __32BIT__ -#endif -#ifndef __UNIX__ -#define __UNIX__ -#endif -#ifdef __GNUC__ -#define stricmp strcasecmp -#endif -#ifndef __X11__ -#ifndef __CONSOLE__ -#define __CONSOLE__ -#endif -#endif - -/* 32-bit FreeBSD compile environment */ -#elif defined(__FREEBSD__) -#ifndef __FREEBSD__ -#define __FREEBSD__ -#endif -#ifndef __32BIT__ -#define __32BIT__ -#endif -#ifndef __UNIX__ -#define __UNIX__ -#endif -#ifdef __GNUC__ -#define stricmp strcasecmp -#endif -#ifndef __X11__ -#ifndef __CONSOLE__ -#define __CONSOLE__ -#endif -#endif - -/* 32-bit BeOS compile environment */ -#elif defined(__BEOS__) -#ifndef __32BIT__ -#define __32BIT__ -#endif -#ifndef __UNIX__ -#define __UNIX__ -#endif -#ifdef __GNUC__ -#define stricmp strcasecmp -#endif - -/* Unsupported OS! */ -#else -#error This platform is not currently supported! -#endif - -/* Determine the CPU type that we are compiling for */ - -#if defined(__M_ALPHA) || defined(__ALPHA_) || defined(__ALPHA) || defined(__alpha) -#ifndef __ALPHA__ -#define __ALPHA__ -#endif -#elif defined(__M_PPC) || defined(__POWERC) -#ifndef __PPC__ -#define __PPC__ -#endif -#elif defined(__M_MRX000) -#ifndef __MIPS__ -#define __MIPS__ -#endif -#else -#ifndef __INTEL__ -#define __INTEL__ /* Assume Intel if nothing found */ -#endif -#endif - -/* We have the following defines to define the calling conventions for - * publicly accesible functions: - * - * _PUBAPI - Compiler default calling conventions for all public 'C' functions - * _ASMAPI - Calling conventions for all public assembler functions - * _VARAPI - Modifiers for variables; Watcom C++ mangles C++ globals - * _STDCALL - Win32 __stdcall where possible, __cdecl if not supported - */ - -#if defined(_MSC_VER) && defined(_WIN32) && !defined(__SC__) -#define __PASCAL __stdcall -#else -#define __PASCAL __pascal -#endif - -#if defined(NO_STDCALL) -#define _STDCALL __cdecl -#else -#define _STDCALL __stdcall -#endif - -#ifdef __WATCOMC__ -#if (__WATCOMC__ >= 1050) -#define _VARAPI __cdecl -#else -#define _VARAPI -#endif -#else -#define _VARAPI -#endif - -#if defined(__IBMC__) || defined(__IBMCPP__) -#define PTR_DECL_IN_FRONT -#endif - -/* Define the calling conventions for all public functions. For simplicity - * we define all public functions as __cdecl calling conventions, so that - * they are the same across all compilers and runtime DLL's. - */ - -#define _PUBAPI __cdecl -#define _ASMAPI __cdecl - -/* Determine the syntax for declaring a function pointer with a - * calling conventions override. Most compilers require the calling - * convention to be declared in front of the '*', but others require - * it to be declared after the '*'. We handle both in here depending - * on what the compiler requires. - */ - -#ifdef PTR_DECL_IN_FRONT -#define _PUBAPIP * _PUBAPI -#define _ASMAPIP * _ASMAPI -#else -#define _PUBAPIP _PUBAPI * -#define _ASMAPIP _ASMAPI * -#endif - -/* Useful macros */ - -#define PRIVATE static -#define PUBLIC - -/* This HAS to be 0L for 16-bit real mode code to work!!! */ - -#ifndef NULL -# define _NULL 0L -# define NULL _NULL -#endif - -#ifndef MAX -# define MAX(a,b) ( ((a) > (b)) ? (a) : (b)) -#endif -#ifndef MIN -# define MIN(a,b) ( ((a) < (b)) ? (a) : (b)) -#endif -#ifndef ABS -# define ABS(a) ((a) >= 0 ? (a) : -(a)) -#endif -#ifndef SIGN -# define SIGN(a) ((a) > 0 ? 1 : -1) -#endif - -/* General typedefs */ - -#ifndef __GENDEFS -#define __GENDEFS -#if defined(__BEOS__) -#include -#else -#ifdef __LINUX__ -#include -#ifdef __STRICT_ANSI__ -typedef unsigned short ushort; -typedef unsigned long ulong; -typedef unsigned int uint; -#endif -#ifdef __KERNEL__ -#define __GENDEFS_2 -#endif -#else -#if !(defined(__QNXNTO__) && defined(GENERAL_STRUCT)) -typedef unsigned short ushort; -typedef unsigned long ulong; -#endif -typedef unsigned int uint; -#endif -typedef unsigned char uchar; -#endif -typedef int ibool; /* Integer boolean type */ -#ifdef USE_BOOL /* Only for older code */ -#ifndef __cplusplus -#define bool ibool /* Standard C */ -#else -#ifndef __HAS_BOOL__ -#define bool ibool /* Older C++ compilers */ -#endif -#endif /* __cplusplus */ -#endif /* USE_BOOL */ -#endif /* __GENDEFS */ - -/* More general typedefs compatible with Linux kernel code */ - -#ifndef __GENDEFS_2 -#define __GENDEFS_2 -typedef char s8; -typedef unsigned char u8; -typedef short s16; -typedef unsigned short u16; -#ifdef __16BIT__ -typedef long s32; -typedef unsigned long u32; -#else -typedef int s32; -typedef unsigned int u32; -#endif -typedef struct { - u32 low; - s32 high; - } __i64; -#ifdef __HAS_LONG_LONG__ -#define __NATIVE_INT64__ -typedef long long s64; -typedef unsigned long long u64; -#elif defined(__HAS_INT64__) && !defined(__16BIT__) -#define __NATIVE_INT64__ -typedef __int64 s64; -typedef unsigned __int64 u64; -#else -typedef __i64 s64; -typedef __i64 u64; -#endif -#endif - -/* Boolean truth values */ - -#undef false -#undef true -#undef NO -#undef YES -#undef FALSE -#undef TRUE -#define false 0 -#define true 1 -#define NO 0 -#define YES 1 -#define FALSE 0 -#define TRUE 1 - -/* Inline debugger interrupts for Watcom C++ and Borland C++ */ - -#ifdef __WATCOMC__ -void DebugInt(void); -#pragma aux DebugInt = \ - "int 3"; -void DebugVxD(void); -#pragma aux DebugVxD = \ - "int 1"; -#elif defined(__BORLANDC__) -#define DebugInt() __emit__(0xCC) -#define DebugVxD() {__emit__(0xCD); __emit__(0x01);} -#elif defined(_MSC_VER) -#define DebugInt() _asm int 0x3 -#define DebugVxD() _asm int 0x1 -#elif defined(__GNUC__) -#define DebugInt() asm volatile ("int $0x3") -#define DebugVxD() asm volatile ("int $0x1") -#else -void _ASMAPI DebugInt(void); -void _ASMAPI DebugVxD(void); -#endif - -/* Macros to break once and never break again */ - -#define DebugIntOnce() \ -{ \ - static ibool firstTime = true; \ - if (firstTime) { \ - firstTime = false; \ - DebugInt(); \ - } \ -} - -#define DebugVxDOnce() \ -{ \ - static ibool firstTime = true; \ - if (firstTime) { \ - firstTime = false; \ - DebugVxD(); \ - } \ -} - -/* Macros for linux string compatibility functions */ - -#ifdef __LINUX__ -#define stricmp strcasecmp -#define strnicmp strncasecmp -#endif - -/* Macros for NT driver string compatibility functions */ - -#ifdef __NT_DRIVER__ -#define stricmp _stricmp -#define strnicmp _strnicmp -#endif - -/* Get rid of some helaciously annoying Visual C++ warnings! */ - -#if defined(_MSC_VER) && !defined(__MWERKS__) && !defined(__SC__) -#pragma warning(disable:4761) /* integral size mismatch in argument; conversion supplied */ -#pragma warning(disable:4244) /* conversion from 'unsigned short ' to 'unsigned char ', possible loss of data */ -#pragma warning(disable:4018) /* '<' : signed/unsigned mismatch */ -#pragma warning(disable:4305) /* 'initializing' : truncation from 'const double' to 'float' */ -#endif - -/*--------------------------------------------------------------------------- - * Set of debugging macros used by the libraries. If the debug flag is - * set, they are turned on depending on the setting of the flag. User code - * can override the default functions called when a check fails, and the - * MGL does this so it can restore the system from graphics mode to display - * an error message. These functions also log information to the - * scitech.log file in the root directory of the hard drive when problems - * show up. - * - * If you set the value of CHECKED to be 2, it will also enable code to - * insert hard coded debugger interrupt into the source code at the line of - * code where the check fail. This is useful if you run the code under a - * debugger as it will break inside the debugger before exiting with a - * failure condition. - * - * Also for code compiled to run under Windows, we also call the - * OutputDebugString function to send the message to the system debugger - * such as Soft-ICE or WDEB386. Hence if you get any non-fatal warnings you - * will see those on the debugger terminal as well as in the log file. - *-------------------------------------------------------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -extern void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line); -void _CHK_defaultFail(int fatal,const char *msg,const char *cond,const char *file,int line); - -#ifdef CHECKED -# define CHK(x) x -#if CHECKED > 1 -# define CHECK(p) \ - ((p) ? (void)0 : DebugInt(), \ - _CHK_fail(1,"Check failed: '%s', file %s, line %d\n", \ - #p, __FILE__, __LINE__)) -# define WARN(p) \ - ((p) ? (void)0 : DebugInt(), \ - _CHK_fail(0,"Warning: '%s', file %s, line %d\n", \ - #p, __FILE__, __LINE__)) -#else -# define CHECK(p) \ - ((p) ? (void)0 : \ - _CHK_fail(1,"Check failed: '%s', file %s, line %d\n", \ - #p, __FILE__, __LINE__)) -# define WARN(p) \ - ((p) ? (void)0 : \ - _CHK_fail(0,"Warning: '%s', file %s, line %d\n", \ - #p, __FILE__, __LINE__)) -#endif -# define LOGFATAL(msg) \ - _CHK_fail(1,"Fatal error: '%s', file %s, line %d\n", \ - msg, __FILE__, __LINE__) -# define LOGWARN(msg) \ - _CHK_fail(0,"Warning: '%s', file %s, line %d\n", \ - msg, __FILE__, __LINE__) -#else -# define CHK(x) -# define CHECK(p) ((void)0) -# define WARN(p) ((void)0) -# define LOGFATAL(msg) ((void)0) -# define LOGWARN(msg) ((void)0) -#endif - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __SCITECH_H */ diff --git a/board/MAI/bios_emulator/scitech/include/scitech.mac b/board/MAI/bios_emulator/scitech/include/scitech.mac deleted file mode 100644 index 27a2fc0..0000000 --- a/board/MAI/bios_emulator/scitech/include/scitech.mac +++ /dev/null @@ -1,1321 +0,0 @@ -;**************************************************************************** -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: NetWide Assembler (NASM) or Turbo Assembler (TASM) -;* Environment: Any Intel Environment -;* -;* Description: Macros to provide memory model independant assembly language -;* module for C programming. Supports the large and flat memory -;* models. -;* -;* The defines that you should use when assembling modules that -;* use this macro package are: -;* -;* __LARGE__ Assemble for 16-bit large model -;* __FLAT__ Assemble for 32-bit FLAT memory model -;* __NOU__ No underscore for all external C labels -;* __NOU_VAR__ No underscore for global variables only -;* -;* The default settings are for 16-bit large memory model with -;* leading underscores for symbol names. -;* -;* The main intent of the macro file is to enable programmers -;* to write _one_ set of source that can be assembled to run -;* in either 16 bit real and protected modes or 32 bit -;* protected mode without the need to riddle the code with -;* 'if flatmodel' style conditional assembly (it is still there -;* but nicely hidden by a macro layer that enhances the -;* readability and understandability of the resulting code). -;* -;**************************************************************************** - -; Include the appropriate version in here depending on the assembler. NASM -; appears to always try and parse code, even if it is in a non-compiling -; block of a ifdef expression, and hence crashes if we include the TASM -; macro package in the same header file. Hence we split the macros up into -; two separate header files. - -ifdef __NASM_MAJOR__ - -;============================================================================ -; Macro package when compiling with NASM. -;============================================================================ - -; Turn off underscores for globals if disabled for all externals - -%ifdef __NOU__ -%define __NOU_VAR__ -%endif - -; Define the __WINDOWS__ symbol if we are compiling for any Windows -; environment - -%ifdef __WINDOWS16__ -%define __WINDOWS__ 1 -%endif -%ifdef __WINDOWS32__ -%define __WINDOWS__ 1 -%define __WINDOWS32_386__ 1 -%endif - -; Macros for accessing 'generic' registers - -%ifdef __FLAT__ -%idefine _ax eax -%idefine _bx ebx -%idefine _cx ecx -%idefine _dx edx -%idefine _si esi -%idefine _di edi -%idefine _bp ebp -%idefine _sp esp -%idefine _es -%idefine UCHAR BYTE ; Size of a character -%idefine USHORT WORD ; Size of a short -%idefine UINT DWORD ; Size of an integer -%idefine ULONG DWORD ; Size of a long -%idefine BOOL DWORD ; Size of a boolean -%idefine DPTR DWORD ; Size of a data pointer -%idefine FDPTR FWORD ; Size of a far data pointer -%idefine NDPTR DWORD ; Size of a near data pointer -%idefine CPTR DWORD ; Size of a code pointer -%idefine FCPTR FWORD ; Size of a far code pointer -%idefine NCPTR DWORD ; Size of a near code pointer -%idefine FPTR NEAR ; Distance for function pointers -%idefine DUINT dd ; Declare a integer variable -%idefine intsize 4 -%idefine flatmodel 1 -%else -%idefine _ax ax -%idefine _bx bx -%idefine _cx cx -%idefine _dx dx -%idefine _si si -%idefine _di di -%idefine _bp bp -%idefine _sp sp -%idefine _es es: -%idefine UCHAR BYTE ; Size of a character -%idefine USHORT WORD ; Size of a short -%idefine UINT WORD ; Size of an integer -%idefine ULONG DWORD ; Size of a long -%idefine BOOL WORD ; Size of a boolean -%idefine DPTR DWORD ; Size of a data pointer -%idefine FDPTR DWORD ; Size of a far data pointer -%idefine NDPTR WORD ; Size of a near data pointer -%idefine CPTR DWORD ; Size of a code pointer -%idefine FCPTR DWORD ; Size of a far code pointer -%idefine NCPTR WORD ; Size of a near code pointer -%idefine FPTR FAR ; Distance for function pointers -%idefine DUINT dw ; Declare a integer variable -%idefine intsize 2 -%endif -%idefine invert ~ -%idefine offset -%idefine use_nasm - -; Convert all jumps to near jumps, since NASM does not so this automatically - -%idefine jo jo near -%idefine jno jno near -%idefine jz jz near -%idefine jnz jnz near -%idefine je je near -%idefine jne jne near -%idefine jb jb near -%idefine jbe jbe near -%idefine ja ja near -%idefine jae jae near -%idefine jl jl near -%idefine jle jle near -%idefine jg jg near -%idefine jge jge near -%idefine jc jc near -%idefine jnc jnc near -%idefine js js near -%idefine jns jns near - -%ifdef DOUBLE -%idefine REAL QWORD -%idefine DREAL dq -%else -%idefine REAL DWORD -%idefine DREAL dd -%endif - -; Boolean truth values (same as those in debug.h) - -%idefine False 0 -%idefine True 1 -%idefine No 0 -%idefine Yes 1 -%idefine Yes 1 - -; Macro to be invoked at the start of all modules to set up segments for -; later use. Does nothing for NASM. - -%imacro header 1 -%endmacro - -; Macro to begin a data segment - -%imacro begdataseg 1 -%ifdef __GNUC__ -segment .data public class=DATA use32 flat -%else -%ifdef flatmodel -segment _DATA public align=4 class=DATA use32 flat -%else -segment _DATA public align=4 class=DATA use16 -%endif -%endif -%endmacro - -; Macro to end a data segment - -%imacro enddataseg 1 -%endmacro - -; Macro to begin a code segment - -%imacro begcodeseg 1 -%ifdef __PIC__ -%ifdef __LINUX__ - extern _GLOBAL_OFFSET_TABLE_ -%else - extern __GLOBAL_OFFSET_TABLE_ -%endif -%endif -%ifdef __GNUC__ -segment .text public class=CODE use32 flat -%else -%ifdef flatmodel -segment _TEXT public align=16 class=CODE use32 flat -%else -segment %1_TEXT public align=16 class=CODE use16 -%endif -%endif -%endmacro - -; Macro to begin a near code segment - -%imacro begcodeseg_near 0 -%ifdef __GNUC__ -segment .text public class=CODE use32 flat -%else -%ifdef flatmodel -segment _TEXT public align=16 class=CODE use32 flat -%else -segment _TEXT public align=16 class=CODE use16 -%endif -%endif -%endmacro - -; Macro to end a code segment - -%imacro endcodeseg 1 -%endmacro - -; Macro to end a near code segment - -%imacro endcodeseg_near 0 -%endmacro - -; Macro for an extern C symbol. If the C compiler requires leading -; underscores, then the underscores are added to the symbol names, otherwise -; they are left off. The symbol name is referenced in the assembler code -; using the non-underscored symbol name. - -%imacro cextern 2 -%ifdef __NOU_VAR__ -extern %1 -%else -extern _%1 -%define %1 _%1 -%endif -%endmacro - -%imacro cexternfunc 2 -%ifdef __NOU__ -extern %1 -%else -extern _%1 -%define %1 _%1 -%endif -%endmacro - -; Macro for a public C symbol. If the C compiler requires leading -; underscores, then the underscores are added to the symbol names, otherwise -; they are left off. The symbol name is referenced in the assembler code -; using the non-underscored symbol name. - -%imacro cpublic 1 -%ifdef __NOU_VAR__ -global %1 -%1: -%else -global _%1 -_%1: -%define %1 _%1 -%endif -%endmacro - -; Macro for an global C symbol. If the C compiler requires leading -; underscores, then the underscores are added to the symbol names, otherwise -; they are left off. The symbol name is referenced in the assembler code -; using the non-underscored symbol name. - -%imacro cglobal 1 -%ifdef __NOU_VAR__ -global %1 -%else -global _%1 -%define %1 _%1 -%endif -%endmacro - -; Macro for an global C function symbol. If the C compiler requires leading -; underscores, then the underscores are added to the symbol names, otherwise -; they are left off. The symbol name is referenced in the assembler code -; using the non-underscored symbol name. - -%imacro cglobalfunc 1 -%ifdef __PIC__ -global %1:function -%else -%ifdef __NOU__ -global %1 -%else -global _%1 -%define %1 _%1 -%endif -%endif -%endmacro - -; Macro to start a C callable function. This will be a far function for -; 16-bit code, and a near function for 32-bit code. - -%imacro cprocstatic 1 -%push cproc -%1: -%ifdef flatmodel -%stacksize flat -%define ret retn -%else -%stacksize large -%define ret retf -%endif -%assign %$localsize 0 -%endmacro - -%imacro cprocstart 1 -%push cproc - cglobalfunc %1 -%1: -%ifdef flatmodel -%stacksize flat -%define ret retn -%else -%stacksize large -%define ret retf -%endif -%assign %$localsize 0 -%endmacro - -; This macro sets up a procedure to be exported from a 16 bit DLL. Since the -; calling conventions are always _far _pascal for 16 bit DLL's, we actually -; rename this routine with an extra underscore with 'C' calling conventions -; and a small DLL stub will be provided by the high level code to call the -; assembler routine. - -%imacro cprocstartdll16 1 -%ifdef __WINDOWS16__ -cprocstart _%1 -%else -cprocstart %1 -%endif -%endmacro - -; Macro to start a C callable near function. - -%imacro cprocnear 1 -%push cproc - cglobalfunc %1 -%1: -%define ret retn -%ifdef flatmodel -%stacksize flat -%else -%stacksize small -%endif -%assign %$localsize 0 -%endmacro - -; Macro to start a C callable far function. - -%imacro cprocfar 1 -%push cproc - cglobalfunc %1 -%1: -%define ret retf -%ifdef flatmodel -%stacksize flat -%else -%stacksize large -%endif -%assign %$localsize 0 -%endmacro - -; Macro to end a C function - -%imacro cprocend 0 -%pop -%endmacro - -; Macros for entering and exiting C callable functions. Note that we must -; always save and restore the SI and DI registers for C functions, and for -; 32 bit C functions we also need to save and restore EBX and clear the -; direction flag. - -%imacro enter_c 0 - push _bp - mov _bp,_sp -%ifnidn %$localsize,0 - sub _sp,%$localsize -%endif -%ifdef flatmodel - push ebx -%endif - push _si - push _di -%endmacro - -%imacro leave_c 0 - pop _di - pop _si -%ifdef flatmodel - pop ebx - cld -%endif -%ifnidn %$localsize,0 - mov _sp,_bp -%endif - pop _bp -%endmacro - -%imacro use_ebx 0 -%ifdef flatmodel - push ebx -%endif -%endmacro - -%imacro unuse_ebx 0 -%ifdef flatmodel - pop ebx -%endif -%endmacro - -; Macros for saving and restoring the value of DS,ES,FS,GS when it is to -; be used in assembly routines. This evaluates to nothing in the flat memory -; model, but is saves and restores DS in the large memory model. - -%imacro use_ds 0 -%ifndef flatmodel - push ds -%endif -%endmacro - -%imacro unuse_ds 0 -%ifndef flatmodel - pop ds -%endif -%endmacro - -%imacro use_es 0 -%ifndef flatmodel - push es -%endif -%endmacro - -%imacro unuse_es 0 -%ifndef flatmodel - pop es -%endif -%endmacro - -; Macros for loading the address of a data pointer into a segment and -; index register pair. The %imacro explicitly loads DS or ES in the 16 bit -; memory model, or it simply loads the offset into the register in the flat -; memory model since DS and ES always point to all addressable memory. You -; must use the correct _REG (ie: _BX) %imacros for documentation purposes. - -%imacro _lds 2 -%ifdef flatmodel - mov %1,%2 -%else - lds %1,%2 -%endif -%endmacro - -%imacro _les 2 -%ifdef flatmodel - mov %1,%2 -%else - les %1,%2 -%endif -%endmacro - -; Macros for adding and subtracting a value from registers. Two value are -; provided, one for 16 bit modes and another for 32 bit modes (the extended -; register is used in 32 bit modes). - -%imacro _add 3 -%ifdef flatmodel - add e%1, %3 -%else - add %1, %2 -%endif -%endmacro - -%imacro _sub 3 -%ifdef flatmodel - sub e%1, %3 -%else - sub %1, %2 -%endif -%endmacro - -; Macro to clear the high order word for the 32 bit extended registers. -; This is used to convert an unsigned 16 bit value to an unsigned 32 bit -; value, and will evaluate to nothing in 16 bit modes. - -%imacro clrhi 1 -%ifdef flatmodel - movzx e%1,%1 -%endif -%endmacro - -%imacro sgnhi 1 -%ifdef flatmodel - movsx e%1,%1 -%endif -%endmacro - -; Macro to load an extended register with an integer value in either mode - -%imacro loadint 2 -%ifdef flatmodel - mov e%1,%2 -%else - xor e%1,e%1 - mov %1,%2 -%endif -%endmacro - -; Macros to load and store integer values with string instructions - -%imacro LODSINT 0 -%ifdef flatmodel - lodsd -%else - lodsw -%endif -%endmacro - -%imacro STOSINT 0 -%ifdef flatmodel - stosd -%else - stosw -%endif -%endmacro - -; Macros to provide resb, resw, resd compatibility with NASM - -%imacro dclb 1 -times %1 db 0 -%endmacro - -%imacro dclw 1 -times %1 dw 0 -%endmacro - -%imacro dcld 1 -times %1 dd 0 -%endmacro - -; Macro to get the addres of the GOT for Linux/FreeBSD shared -; libraries into the EBX register. - -%imacro get_GOT 1 - call %%getgot -%%getgot: pop %1 - add %1,_GLOBAL_OFFSET_TABLE_+$$-%%getgot wrt ..gotpc -%endmacro - -; Macro to get the address of a *local* variable that is global to -; a single module in a manner that will work correctly when compiled -; into a Linux shared library. Note that this will *not* work for -; variables that are defined as global to all modules. For that -; use the LEA_G macro - -%macro LEA_L 2 -%ifdef __PIC__ - get_GOT %1 - lea %1,[%1+%2 wrt ..gotoff] -%else - lea %1,[%2] -%endif -%endmacro - -; Same macro as above but for global variables public to *all* -; modules. - -%macro LEA_G 2 -%ifdef __PIC__ - get_GOT %1 - mov %1,[%1+%2 wrt ..got] -%else - lea %1,[%2] -%endif -%endmacro - -; macros to declare assembler function stubs for function structures - -%imacro BEGIN_STUBS_DEF 2 -begdataseg _STUBS -%ifdef __NOU_VAR__ -extern %1 -%define STUBS_START %1 -%else -extern _%1 -%define STUBS_START _%1 -%endif -enddataseg _STUBS -begcodeseg _STUBS -%assign off %2 -%endmacro - -%imacro DECLARE_STUB 1 -%ifdef __PIC__ - global %1:function -%1: - get_GOT eax - mov eax,[eax+STUBS_START wrt ..got] - jmp [eax+off] -%else -%ifdef __NOU__ - global %1 -%1: -%else - global _%1 -_%1: -%endif - jmp [DWORD STUBS_START+off] -%endif -%assign off off+4 -%endmacro - -%imacro SKIP_STUB 1 -%assign off off+4 -%endmacro - -%imacro DECLARE_STDCALL 2 -%ifdef STDCALL_MANGLE - global _%1@%2 -_%1@%2: -%else -%ifdef STDCALL_USCORE - global _%1 -_%1: -%else - global %1 -%1: -%endif -%endif - jmp [DWORD STUBS_START+off] -%assign off off+4 -%endmacro - -%imacro END_STUBS_DEF 0 -endcodeseg _STUBS -%endmacro - -; macros to declare assembler import stubs for binary loadable drivers - -%imacro BEGIN_IMPORTS_DEF 1 -BEGIN_STUBS_DEF %1,4 -%endmacro - -%imacro DECLARE_IMP 2 -DECLARE_STUB %1 -%endmacro - -%imacro SKIP_IMP 2 -SKIP_STUB %1 -%endmacro - -%imacro SKIP_IMP2 1 -DECLARE_STUB %1 -%endmacro - -%imacro SKIP_IMP3 1 -SKIP_STUB %1 -%endmacro - -%imacro END_IMPORTS_DEF 0 -END_STUBS_DEF -%endmacro - -else ; __NASM_MAJOR__ - -;============================================================================ -; Macro package when compiling with TASM. -;============================================================================ - -; Turn off underscores for globals if disabled for all externals - -ifdef __NOU__ -__NOU_VAR__ = 1 -endif - -; Define the __WINDOWS__ symbol if we are compiling for any Windows -; environment - -ifdef __WINDOWS16__ -__WINDOWS__ = 1 -endif -ifdef __WINDOWS32__ -__WINDOWS__ = 1 -__WINDOWS32_386__ = 1 -endif -ifdef __WIN386__ -__WINDOWS__ = 1 -__WINDOWS32_386__ = 1 -endif -ifdef __VXD__ -__WINDOWS__ = 1 -__WINDOWS32_386__ = 1 - MASM - .386 - NO_SEGMENTS = 1 - include vmm.inc ; IGNORE DEPEND - include vsegment.inc ; IGNORE DEPEND - IDEAL -endif - -; Macros for accessing 'generic' registers - -ifdef __FLAT__ - _ax EQU eax ; EAX is used for accumulator - _bx EQU ebx ; EBX is used for accumulator - _cx EQU ecx ; ECX is used for looping - _dx EQU edx ; EDX is used for data register - _si EQU esi ; ESI is the source index register - _di EQU edi ; EDI is the destination index register - _bp EQU ebp ; EBP is used for base pointer register - _sp EQU esp ; ESP is used for stack pointer register - _es EQU ; ES and DS are the same in 32 bit PM - typedef UCHAR BYTE ; Size of a character - typedef USHORT WORD ; Size of a short - typedef UINT DWORD ; Size of an integer - typedef ULONG DWORD ; Size of a long - typedef BOOL DWORD ; Size of a boolean - typedef DPTR DWORD ; Size of a data pointer - typedef FDPTR FWORD ; Size of a far data pointer - typedef NDPTR DWORD ; Size of a near data pointer - typedef CPTR DWORD ; Size of a code pointer - typedef FCPTR FWORD ; Size of a far code pointer - typedef NCPTR DWORD ; Size of a near code pointer - typedef DUINT DWORD ; Declare a integer variable - FPTR EQU NEAR ; Distance for function pointers - intsize = 4 ; Size of an integer - flatmodel = 1 ; This is a flat memory model - P386 ; Turn on 386 code generation - MODEL FLAT ; Set up for 32 bit simplified FLAT model -else - _ax EQU ax ; AX is used for accumulator - _bx EQU bx ; BX is used for accumulator - _cx EQU cx ; CX is used for looping - _dx EQU dx ; DX is used for data register - _si EQU si ; SI is the source index register - _di EQU di ; DI is the destination index register - _bp EQU bp ; BP is used for base pointer register - _sp EQU sp ; SP is used for stack pointer register - _es EQU es: ; ES is used for segment override - typedef UCHAR BYTE ; Size of a character - typedef USHORT WORD ; Size of a short - typedef UINT WORD ; Size of an integer - typedef ULONG DWORD ; Size of a long - typedef BOOL WORD ; Size of a boolean - typedef DPTR DWORD ; Size of a data pointer - typedef FDPTR DWORD ; Size of a far data pointer - typedef NDPTR WORD ; Size of a near data pointer - typedef CPTR DWORD ; Size of a code pointer - typedef FCPTR DWORD ; Size of a far code pointer - typedef NCPTR WORD ; Size of a near code pointer - typedef DUINT WORD ; Declare a integer variable - FPTR EQU FAR ; Distance for function pointers - intsize = 2 ; Size of an integer - P386 ; Turn on 386 code generation -endif - invert EQU not - -; Provide a typedef for real floating point numbers - -ifdef DOUBLE -typedef REAL QWORD -typedef DREAL QWORD -else -typedef REAL DWORD -typedef DREAL DWORD -endif - -; Macros to access the floating point stack registers to convert them -; from NASM style to TASM style - -st0 EQU st(0) -st1 EQU st(1) -st2 EQU st(2) -st3 EQU st(3) -st4 EQU st(4) -st5 EQU st(5) -st6 EQU st(6) -st7 EQU st(7) -st8 EQU st(8) - -; Boolean truth values (same as those in debug.h) - -ifndef __VXD__ -False = 0 -True = 1 -No = 0 -Yes = 1 -Yes = 1 -endif - -; Macros for the _DATA data segment. This segment contains initialised data. - -MACRO begdataseg name -ifdef __VXD__ - MASM -VXD_LOCKED_DATA_SEG - IDEAL -else -ifdef flatmodel - DATASEG -else -SEGMENT _DATA DWORD PUBLIC USE16 'DATA' -endif -endif -ENDM - -MACRO enddataseg name -ifdef __VXD__ - MASM -VXD_LOCKED_DATA_ENDS - IDEAL -else -ifndef flatmodel -ENDS _DATA -endif -endif -ENDM - -; Macro for the main code segment. - -MACRO begcodeseg name -ifdef __VXD__ - MASM -VXD_LOCKED_CODE_SEG - IDEAL -else -ifdef flatmodel - CODESEG - ASSUME CS:FLAT,DS:FLAT,SS:FLAT -else -SEGMENT &name&_TEXT PARA PUBLIC USE16 'CODE' - ASSUME CS:&name&_TEXT,DS:_DATA -endif -endif -ENDM - -; Macro for a near code segment - -MACRO begcodeseg_near -ifdef flatmodel - CODESEG - ASSUME CS:FLAT,DS:FLAT,SS:FLAT -else -SEGMENT _TEXT PARA PUBLIC USE16 'CODE' - ASSUME CS:_TEXT,DS:_DATA -endif -ENDM - -MACRO endcodeseg name -ifdef __VXD__ - MASM -VXD_LOCKED_CODE_ENDS - IDEAL -else -ifndef flatmodel -ENDS &name&_TEXT -endif -endif -ENDM - -MACRO endcodeseg_near -ifndef flatmodel -ENDS _TEXT -endif -ENDM - -; Macro to be invoked at the start of all modules to set up segments for -; later use. - -MACRO header name -begdataseg name -enddataseg name -ENDM - -; Macro for an extern C symbol. If the C compiler requires leading -; underscores, then the underscores are added to the symbol names, otherwise -; they are left off. The symbol name is referenced in the assembler code -; using the non-underscored symbol name. - -MACRO cextern name,size -ifdef __NOU_VAR__ - EXTRN name:size -else - EXTRN _&name&:size -name EQU _&name& -endif -ENDM - -MACRO cexternfunc name,size -ifdef __NOU__ - EXTRN name:size -else - EXTRN _&name&:size -name EQU _&name& -endif -ENDM - -MACRO stdexternfunc name,num_args,size -ifdef STDCALL_MANGLE - EXTRN _&name&@&num_args&:size -name EQU _&name&@&num_args -else - EXTRN name:size -endif -ENDM - -; Macro for a public C symbol. If the C compiler requires leading -; underscores, then the underscores are added to the symbol names, otherwise -; they are left off. The symbol name is referenced in the assembler code -; using the non-underscored symbol name. - -MACRO cpublic name -ifdef __NOU_VAR__ -name: - PUBLIC name -else -_&name&: - PUBLIC _&name& -name EQU _&name& -endif -ENDM - -; Macro for an global C symbol. If the C compiler requires leading -; underscores, then the underscores are added to the symbol names, otherwise -; they are left off. The symbol name is referenced in the assembler code -; using the non-underscored symbol name. - -MACRO cglobal name -ifdef __NOU_VAR__ - PUBLIC name -else - PUBLIC _&name& -name EQU _&name& -endif -ENDM - -; Macro for an global C function symbol. If the C compiler requires leading -; underscores, then the underscores are added to the symbol names, otherwise -; they are left off. The symbol name is referenced in the assembler code -; using the non-underscored symbol name. - -MACRO cglobalfunc name -ifdef __NOU__ - PUBLIC name -else - PUBLIC _&name& -name EQU _&name& -endif -ENDM - -; Macro to start a C callable function. This will be a far function for -; 16-bit code, and a near function for 32-bit code. - -MACRO cprocstatic name ; Set up model independant private proc -ifdef flatmodel -PROC name NEAR -else -PROC name FAR -endif -LocalSize = 0 -ENDM - -MACRO cprocstart name ; Set up model independant proc -ifdef flatmodel -ifdef __NOU__ -PROC name NEAR -else -PROC _&name& NEAR -endif -else -ifdef __NOU__ -PROC name FAR -else -PROC _&name& FAR -endif -endif -LocalSize = 0 - cglobalfunc name -ENDM - -MACRO cprocnear name ; Set up near proc -ifdef __NOU__ -PROC name NEAR -else -PROC _&name& NEAR -endif -LocalSize = 0 - cglobalfunc name -ENDM - -MACRO cprocfar name ; Set up far proc -ifdef __NOU__ -PROC name FAR -else -PROC _&name& FAR -endif -LocalSize = 0 - cglobalfunc name -ENDM - -MACRO cprocend ; End procedure macro -ENDP -ENDM - -; This macro sets up a procedure to be exported from a 16 bit DLL. Since the -; calling conventions are always _far _pascal for 16 bit DLL's, we actually -; rename this routine with an extra underscore with 'C' calling conventions -; and a small DLL stub will be provided by the high level code to call the -; assembler routine. - -MACRO cprocstartdll16 name -ifdef __WINDOWS16__ -cprocstart _&name& -else -cprocstart name -endif -ENDM - -; Macros for entering and exiting C callable functions. Note that we must -; always save and restore the SI and DI registers for C functions, and for -; 32 bit C functions we also need to save and restore EBX and clear the -; direction flag. - -MACRO save_c_regs -ifdef flatmodel - push ebx -endif - push _si - push _di -ENDM - -MACRO enter_c - push _bp - mov _bp,_sp - IFDIFI ,<0> - sub _sp,LocalSize - ENDIF - save_c_regs -ENDM - -MACRO restore_c_regs - pop _di - pop _si -ifdef flatmodel - pop ebx -endif -ENDM - -MACRO leave_c - restore_c_regs - cld - IFDIFI ,<0> - mov _sp,_bp - ENDIF - pop _bp -ENDM - -MACRO use_ebx -ifdef flatmodel - push ebx -endif -ENDM - -MACRO unuse_ebx -ifdef flatmodel - pop ebx -endif -ENDM - -; Macros for saving and restoring the value of DS,ES,FS,GS when it is to -; be used in assembly routines. This evaluates to nothing in the flat memory -; model, but is saves and restores DS in the large memory model. - -MACRO use_ds -ifndef flatmodel - push ds -endif -ENDM - -MACRO unuse_ds -ifndef flatmodel - pop ds -endif -ENDM - -MACRO use_es -ifndef flatmodel - push es -endif -ENDM - -MACRO unuse_es -ifndef flatmodel - pop es -endif -ENDM - -; Macros for loading the address of a data pointer into a segment and -; index register pair. The macro explicitly loads DS or ES in the 16 bit -; memory model, or it simply loads the offset into the register in the flat -; memory model since DS and ES always point to all addressable memory. You -; must use the correct _REG (ie: _BX) macros for documentation purposes. - -MACRO _lds reg, addr -ifdef flatmodel - mov reg,addr -else - lds reg,addr -endif -ENDM - -MACRO _les reg, addr -ifdef flatmodel - mov reg,addr -else - les reg,addr -endif -ENDM - -; Macros for adding and subtracting a value from registers. Two value are -; provided, one for 16 bit modes and another for 32 bit modes (the extended -; register is used in 32 bit modes). - -MACRO _add reg, val16, val32 -ifdef flatmodel - add e®&, val32 -else - add reg, val16 -endif -ENDM - -MACRO _sub reg, val16, val32 -ifdef flatmodel - sub e®&, val32 -else - sub reg, val16 -endif -ENDM - -; Macro to clear the high order word for the 32 bit extended registers. -; This is used to convert an unsigned 16 bit value to an unsigned 32 bit -; value, and will evaluate to nothing in 16 bit modes. - -MACRO clrhi reg -ifdef flatmodel - movzx e®&,reg -endif -ENDM - -MACRO sgnhi reg -ifdef flatmodel - movsx e®&,reg -endif -ENDM - -; Macro to load an extended register with an integer value in either mode - -MACRO loadint reg,val -ifdef flatmodel - mov e®&,val -else - xor e®&,e®& - mov reg,val -endif -ENDM - -; Macros to load and store integer values with string instructions - -MACRO LODSINT -ifdef flatmodel - lodsd -else - lodsw -endif -ENDM - -MACRO STOSINT -ifdef flatmodel - stosd -else - stosw -endif -ENDM - -; Macros to provide resb, resw, resd compatibility with NASM - -MACRO dclb count -db count dup (0) -ENDM - -MACRO dclw count -dw count dup (0) -ENDM - -MACRO dcld count -dd count dup (0) -ENDM - -; Macros to provide resb, resw, resd compatibility with NASM - -MACRO resb count -db count dup (?) -ENDM - -MACRO resw count -dw count dup (?) -ENDM - -MACRO resd count -dd count dup (?) -ENDM - -; Macros to declare assembler stubs for function structures - -MACRO BEGIN_STUBS_DEF name, firstOffset -begdataseg _STUBS -ifdef __NOU_VAR__ - EXTRN name:DWORD -STUBS_START = name -else - EXTRN _&name&:DWORD -name EQU _&name& -STUBS_START = _&name -endif -enddataseg _STUBS -begcodeseg _STUBS -off = firstOffset -ENDM - -MACRO DECLARE_STUB name -ifdef __NOU__ -name: - PUBLIC name -else -_&name: - PUBLIC _&name -endif - jmp [DWORD STUBS_START+off] -off = off + 4 -ENDM - -MACRO SKIP_STUB name -off = off + 4 -ENDM - -MACRO DECLARE_STDCALL name,num_args -ifdef STDCALL_MANGLE -_&name&@&num_args&: - PUBLIC _&name&@&num_args& -else -name: - PUBLIC name -endif - jmp [DWORD STUBS_START+off] -off = off + 4 -ENDM - -MACRO END_STUBS_DEF -endcodeseg _STUBS -ENDM - -MACRO BEGIN_IMPORTS_DEF name -BEGIN_STUBS_DEF name,4 -ENDM - -ifndef LOCAL_DECLARE_IMP -MACRO DECLARE_IMP name, numArgs -DECLARE_STUB name -ENDM - -MACRO SKIP_IMP name -SKIP_STUB name -ENDM - -MACRO SKIP_IMP2 name, numArgs -DECLARE_STUB name -ENDM - -MACRO SKIP_IMP3 name -SKIP_STUB name -ENDM -endif - -MACRO END_IMPORTS_DEF -END_STUBS_DEF -ENDM - -MACRO LEA_L reg,name - lea reg,[name] -ENDM - -MACRO LEA_G reg,name - lea reg,[name] -ENDM - -endif - diff --git a/board/MAI/bios_emulator/scitech/include/x86emu.h b/board/MAI/bios_emulator/scitech/include/x86emu.h deleted file mode 100644 index 1d87d4e..0000000 --- a/board/MAI/bios_emulator/scitech/include/x86emu.h +++ /dev/null @@ -1,194 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Header file for public specific functions. -* Any application linking against us should only -* include this header -* -****************************************************************************/ - -#ifndef __X86EMU_X86EMU_H -#define __X86EMU_X86EMU_H - -#ifdef SCITECH -#include "scitech.h" -#define X86API _ASMAPI -#define X86APIP _ASMAPIP -typedef int X86EMU_pioAddr; -#else -#include "x86emu/types.h" -#define X86API -#define X86APIP * -#endif -#include "x86emu/regs.h" - -/*---------------------- Macros and type definitions ----------------------*/ - -#pragma pack(1) - -/**************************************************************************** -REMARKS: -Data structure containing ponters to programmed I/O functions used by the -emulator. This is used so that the user program can hook all programmed -I/O for the emulator to handled as necessary by the user program. By -default the emulator contains simple functions that do not do access the -hardware in any way. To allow the emualtor access the hardware, you will -need to override the programmed I/O functions using the X86EMU_setupPioFuncs -function. - -HEADER: -x86emu.h - -MEMBERS: -inb - Function to read a byte from an I/O port -inw - Function to read a word from an I/O port -inl - Function to read a dword from an I/O port -outb - Function to write a byte to an I/O port -outw - Function to write a word to an I/O port -outl - Function to write a dword to an I/O port -****************************************************************************/ -typedef struct { - u8 (X86APIP inb)(X86EMU_pioAddr addr); - u16 (X86APIP inw)(X86EMU_pioAddr addr); - u32 (X86APIP inl)(X86EMU_pioAddr addr); - void (X86APIP outb)(X86EMU_pioAddr addr, u8 val); - void (X86APIP outw)(X86EMU_pioAddr addr, u16 val); - void (X86APIP outl)(X86EMU_pioAddr addr, u32 val); - } X86EMU_pioFuncs; - -/**************************************************************************** -REMARKS: -Data structure containing ponters to memory access functions used by the -emulator. This is used so that the user program can hook all memory -access functions as necessary for the emulator. By default the emulator -contains simple functions that only access the internal memory of the -emulator. If you need specialised functions to handle access to different -types of memory (ie: hardware framebuffer accesses and BIOS memory access -etc), you will need to override this using the X86EMU_setupMemFuncs -function. - -HEADER: -x86emu.h - -MEMBERS: -rdb - Function to read a byte from an address -rdw - Function to read a word from an address -rdl - Function to read a dword from an address -wrb - Function to write a byte to an address -wrw - Function to write a word to an address -wrl - Function to write a dword to an address -****************************************************************************/ -typedef struct { - u8 (X86APIP rdb)(u32 addr); - u16 (X86APIP rdw)(u32 addr); - u32 (X86APIP rdl)(u32 addr); - void (X86APIP wrb)(u32 addr, u8 val); - void (X86APIP wrw)(u32 addr, u16 val); - void (X86APIP wrl)(u32 addr, u32 val); - } X86EMU_memFuncs; - -/**************************************************************************** - Here are the default memory read and write - function in case they are needed as fallbacks. -***************************************************************************/ -extern u8 X86API rdb(u32 addr); -extern u16 X86API rdw(u32 addr); -extern u32 X86API rdl(u32 addr); -extern void X86API wrb(u32 addr, u8 val); -extern void X86API wrw(u32 addr, u16 val); -extern void X86API wrl(u32 addr, u32 val); - -#pragma pack() - -/*--------------------- type definitions -----------------------------------*/ - -typedef void (X86APIP X86EMU_intrFuncs)(int num); -extern X86EMU_intrFuncs _X86EMU_intrTab[256]; - -/*-------------------------- Function Prototypes --------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); -void X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs); -void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); -void X86EMU_prepareForInt(int num); - -/* decode.c */ - -void X86EMU_exec(void); -void X86EMU_halt_sys(void); - -#ifdef DEBUG -#define HALT_SYS() \ - printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ - X86EMU_halt_sys() -#else -#define HALT_SYS() X86EMU_halt_sys() -#endif - -/* Debug options */ - -#define DEBUG_DECODE_F 0x0001 /* print decoded instruction */ -#define DEBUG_TRACE_F 0x0002 /* dump regs before/after execution */ -#define DEBUG_STEP_F 0x0004 -#define DEBUG_DISASSEMBLE_F 0x0008 -#define DEBUG_BREAK_F 0x0010 -#define DEBUG_SVC_F 0x0020 -#define DEBUG_SAVE_CS_IP 0x0040 -#define DEBUG_FS_F 0x0080 -#define DEBUG_PROC_F 0x0100 -#define DEBUG_SYSINT_F 0x0200 /* bios system interrupts. */ -#define DEBUG_TRACECALL_F 0x0400 -#define DEBUG_INSTRUMENT_F 0x0800 -#define DEBUG_MEM_TRACE_F 0x1000 -#define DEBUG_IO_TRACE_F 0x2000 -#define DEBUG_TRACECALL_REGS_F 0x4000 -#define DEBUG_DECODE_NOPRINT_F 0x8000 -#define DEBUG_EXIT 0x10000 -#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) - -void X86EMU_trace_regs(void); -void X86EMU_trace_xregs(void); -void X86EMU_dump_memory(u16 seg, u16 off, u32 amt); -int X86EMU_trace_on(void); -int X86EMU_trace_off(void); - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __X86EMU_X86EMU_H */ diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h b/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h deleted file mode 100644 index 777b03c..0000000 --- a/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Header file for FPU register definitions. -* -****************************************************************************/ - -#ifndef __X86EMU_FPU_REGS_H -#define __X86EMU_FPU_REGS_H - -#ifdef X86_FPU_SUPPORT - -#pragma pack(1) - -/* Basic 8087 register can hold any of the following values: */ - -union x86_fpu_reg_u { - s8 tenbytes[10]; - double dval; - float fval; - s16 sval; - s32 lval; - }; - -struct x86_fpu_reg { - union x86_fpu_reg_u reg; - char tag; - }; - -/* - * Since we are not going to worry about the problems of aliasing - * registers, every time a register is modified, its result type is - * set in the tag fields for that register. If some operation - * attempts to access the type in a way inconsistent with its current - * storage format, then we flag the operation. If common, we'll - * attempt the conversion. - */ - -#define X86_FPU_VALID 0x80 -#define X86_FPU_REGTYP(r) ((r) & 0x7F) - -#define X86_FPU_WORD 0x0 -#define X86_FPU_SHORT 0x1 -#define X86_FPU_LONG 0x2 -#define X86_FPU_FLOAT 0x3 -#define X86_FPU_DOUBLE 0x4 -#define X86_FPU_LDBL 0x5 -#define X86_FPU_BSD 0x6 - -#define X86_FPU_STKTOP 0 - -struct x86_fpu_registers { - struct x86_fpu_reg x86_fpu_stack[8]; - int x86_fpu_flags; - int x86_fpu_config; /* rounding modes, etc. */ - short x86_fpu_tos, x86_fpu_bos; - }; - -#pragma pack() - -/* - * There are two versions of the following macro. - * - * One version is for opcode D9, for which there are more than 32 - * instructions encoded in the second byte of the opcode. - * - * The other version, deals with all the other 7 i87 opcodes, for - * which there are only 32 strings needed to describe the - * instructions. - */ - -#endif /* X86_FPU_SUPPORT */ - -#ifdef DEBUG -# define DECODE_PRINTINSTR32(t,mod,rh,rl) \ - DECODE_PRINTF(t[(mod<<3)+(rh)]); -# define DECODE_PRINTINSTR256(t,mod,rh,rl) \ - DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]); -#else -# define DECODE_PRINTINSTR32(t,mod,rh,rl) -# define DECODE_PRINTINSTR256(t,mod,rh,rl) -#endif - -#endif /* __X86EMU_FPU_REGS_H */ diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/regs.h b/board/MAI/bios_emulator/scitech/include/x86emu/regs.h deleted file mode 100644 index a12017b..0000000 --- a/board/MAI/bios_emulator/scitech/include/x86emu/regs.h +++ /dev/null @@ -1,331 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Header file for x86 register definitions. -* -****************************************************************************/ - -#ifndef __X86EMU_REGS_H -#define __X86EMU_REGS_H - -/*---------------------- Macros and type definitions ----------------------*/ - -#pragma pack(1) - -/* - * General EAX, EBX, ECX, EDX type registers. Note that for - * portability, and speed, the issue of byte swapping is not addressed - * in the registers. All registers are stored in the default format - * available on the host machine. The only critical issue is that the - * registers should line up EXACTLY in the same manner as they do in - * the 386. That is: - * - * EAX & 0xff === AL - * EAX & 0xffff == AX - * - * etc. The result is that alot of the calculations can then be - * done using the native instruction set fully. - */ - -#ifdef __BIG_ENDIAN__ - -typedef struct { - u32 e_reg; - } I32_reg_t; - -typedef struct { - u16 filler0, x_reg; - } I16_reg_t; - -typedef struct { - u8 filler0, filler1, h_reg, l_reg; - } I8_reg_t; - -#else /* !__BIG_ENDIAN__ */ - -typedef struct { - u32 e_reg; - } I32_reg_t; - -typedef struct { - u16 x_reg; - } I16_reg_t; - -typedef struct { - u8 l_reg, h_reg; - } I8_reg_t; - -#endif /* BIG_ENDIAN */ - -typedef union { - I32_reg_t I32_reg; - I16_reg_t I16_reg; - I8_reg_t I8_reg; - } i386_general_register; - -struct i386_general_regs { - i386_general_register A, B, C, D; - }; - -typedef struct i386_general_regs Gen_reg_t; - -struct i386_special_regs { - i386_general_register SP, BP, SI, DI, IP; - u32 FLAGS; - }; - -/* - * Segment registers here represent the 16 bit quantities - * CS, DS, ES, SS. - */ - -struct i386_segment_regs { - u16 CS, DS, SS, ES, FS, GS; - }; - -/* 8 bit registers */ -#define R_AH gen.A.I8_reg.h_reg -#define R_AL gen.A.I8_reg.l_reg -#define R_BH gen.B.I8_reg.h_reg -#define R_BL gen.B.I8_reg.l_reg -#define R_CH gen.C.I8_reg.h_reg -#define R_CL gen.C.I8_reg.l_reg -#define R_DH gen.D.I8_reg.h_reg -#define R_DL gen.D.I8_reg.l_reg - -/* 16 bit registers */ -#define R_AX gen.A.I16_reg.x_reg -#define R_BX gen.B.I16_reg.x_reg -#define R_CX gen.C.I16_reg.x_reg -#define R_DX gen.D.I16_reg.x_reg - -/* 32 bit extended registers */ -#define R_EAX gen.A.I32_reg.e_reg -#define R_EBX gen.B.I32_reg.e_reg -#define R_ECX gen.C.I32_reg.e_reg -#define R_EDX gen.D.I32_reg.e_reg - -/* special registers */ -#define R_SP spc.SP.I16_reg.x_reg -#define R_BP spc.BP.I16_reg.x_reg -#define R_SI spc.SI.I16_reg.x_reg -#define R_DI spc.DI.I16_reg.x_reg -#define R_IP spc.IP.I16_reg.x_reg -#define R_FLG spc.FLAGS - -/* special registers */ -#define R_SP spc.SP.I16_reg.x_reg -#define R_BP spc.BP.I16_reg.x_reg -#define R_SI spc.SI.I16_reg.x_reg -#define R_DI spc.DI.I16_reg.x_reg -#define R_IP spc.IP.I16_reg.x_reg -#define R_FLG spc.FLAGS - -/* special registers */ -#define R_ESP spc.SP.I32_reg.e_reg -#define R_EBP spc.BP.I32_reg.e_reg -#define R_ESI spc.SI.I32_reg.e_reg -#define R_EDI spc.DI.I32_reg.e_reg -#define R_EIP spc.IP.I32_reg.e_reg -#define R_EFLG spc.FLAGS - -/* segment registers */ -#define R_CS seg.CS -#define R_DS seg.DS -#define R_SS seg.SS -#define R_ES seg.ES -#define R_FS seg.FS -#define R_GS seg.GS - -/* flag conditions */ -#define FB_CF 0x0001 /* CARRY flag */ -#define FB_PF 0x0004 /* PARITY flag */ -#define FB_AF 0x0010 /* AUX flag */ -#define FB_ZF 0x0040 /* ZERO flag */ -#define FB_SF 0x0080 /* SIGN flag */ -#define FB_TF 0x0100 /* TRAP flag */ -#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ -#define FB_DF 0x0400 /* DIR flag */ -#define FB_OF 0x0800 /* OVERFLOW flag */ - -/* 80286 and above always have bit#1 set */ -#define F_ALWAYS_ON (0x0002) /* flag bits always on */ - -/* - * Define a mask for only those flag bits we will ever pass back - * (via PUSHF) - */ -#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) - -/* following bits masked in to a 16bit quantity */ - -#define F_CF 0x0001 /* CARRY flag */ -#define F_PF 0x0004 /* PARITY flag */ -#define F_AF 0x0010 /* AUX flag */ -#define F_ZF 0x0040 /* ZERO flag */ -#define F_SF 0x0080 /* SIGN flag */ -#define F_TF 0x0100 /* TRAP flag */ -#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ -#define F_DF 0x0400 /* DIR flag */ -#define F_OF 0x0800 /* OVERFLOW flag */ - -#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) -#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) -#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) -#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) -#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) - -#define CONDITIONAL_SET_FLAG(COND,FLAG) \ - if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) - -#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ -#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ -#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ - -#define F_ALL_CALC 0xff0000 /* All have been calced */ - -/* - * Emulator machine state. - * Segment usage control. - */ -#define SYSMODE_SEG_DS_SS 0x00000001 -#define SYSMODE_SEGOVR_CS 0x00000002 -#define SYSMODE_SEGOVR_DS 0x00000004 -#define SYSMODE_SEGOVR_ES 0x00000008 -#define SYSMODE_SEGOVR_FS 0x00000010 -#define SYSMODE_SEGOVR_GS 0x00000020 -#define SYSMODE_SEGOVR_SS 0x00000040 -#define SYSMODE_PREFIX_REPE 0x00000080 -#define SYSMODE_PREFIX_REPNE 0x00000100 -#define SYSMODE_PREFIX_DATA 0x00000200 -#define SYSMODE_PREFIX_ADDR 0x00000400 -#define SYSMODE_INTR_PENDING 0x10000000 -#define SYSMODE_EXTRN_INTR 0x20000000 -#define SYSMODE_HALTED 0x40000000 - -#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ - SYSMODE_SEGOVR_CS | \ - SYSMODE_SEGOVR_DS | \ - SYSMODE_SEGOVR_ES | \ - SYSMODE_SEGOVR_FS | \ - SYSMODE_SEGOVR_GS | \ - SYSMODE_SEGOVR_SS) -#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ - SYSMODE_SEGOVR_CS | \ - SYSMODE_SEGOVR_DS | \ - SYSMODE_SEGOVR_ES | \ - SYSMODE_SEGOVR_FS | \ - SYSMODE_SEGOVR_GS | \ - SYSMODE_SEGOVR_SS | \ - SYSMODE_PREFIX_DATA | \ - SYSMODE_PREFIX_ADDR) - -#define INTR_SYNCH 0x1 -#define INTR_ASYNCH 0x2 -#define INTR_HALTED 0x4 - -typedef struct { - struct i386_general_regs gen; - struct i386_special_regs spc; - struct i386_segment_regs seg; - /* - * MODE contains information on: - * REPE prefix 2 bits repe,repne - * SEGMENT overrides 5 bits normal,DS,SS,CS,ES - * Delayed flag set 3 bits (zero, signed, parity) - * reserved 6 bits - * interrupt # 8 bits instruction raised interrupt - * BIOS video segregs 4 bits - * Interrupt Pending 1 bits - * Extern interrupt 1 bits - * Halted 1 bits - */ - long mode; - u8 intno; - volatile int intr; /* mask of pending interrupts */ - int debug; -#ifdef DEBUG - int check; - u16 saved_ip; - u16 saved_cs; - int enc_pos; - int enc_str_pos; - char decode_buf[32]; /* encoded byte stream */ - char decoded_buf[256]; /* disassembled strings */ -#endif - } X86EMU_regs; - -/**************************************************************************** -REMARKS: -Structure maintaining the emulator machine state. - -MEMBERS: -x86 - X86 registers -mem_base - Base real mode memory for the emulator -mem_size - Size of the real mode memory block for the emulator -****************************************************************************/ -typedef struct { - X86EMU_regs x86; - unsigned long mem_base; - unsigned long mem_size; - void* private; - } X86EMU_sysEnv; - -#pragma pack() - -/*----------------------------- Global Variables --------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -/* Global emulator machine state. - * - * We keep it global to avoid pointer dereferences in the code for speed. - */ - -extern X86EMU_sysEnv _X86EMU_env; -#define M _X86EMU_env - -/*-------------------------- Function Prototypes --------------------------*/ - -/* Function to log information at runtime */ - -/*void printk(const char *fmt, ...); */ - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __X86EMU_REGS_H */ diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/types.h b/board/MAI/bios_emulator/scitech/include/x86emu/types.h deleted file mode 100644 index 0a17c54..0000000 --- a/board/MAI/bios_emulator/scitech/include/x86emu/types.h +++ /dev/null @@ -1,70 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Header file for x86 emulator type definitions. -* -****************************************************************************/ - -#ifndef __X86EMU_TYPES_H -#define __X86EMU_TYPES_H - -#include - -/*---------------------- Macros and type definitions ----------------------*/ - -/* Currently only for Linux/32bit */ -#if defined(__GNUC__) && !defined(NO_LONG_LONG) -#define __HAS_LONG_LONG__ -#endif - -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned int u32; -#ifdef __HAS_LONG_LONG__ -typedef unsigned long long u64; -#endif - -typedef char s8; -typedef short s16; -typedef long s32; -#ifdef __HAS_LONG_LONG__ -typedef long long s64; -#endif - -/*typedef unsigned int uint;*/ -typedef int sint; - -typedef u16 X86EMU_pioAddr; - -#endif /* __X86EMU_TYPES_H */ diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc.so/readme.txt deleted file mode 100644 index 0d87eff..0000000 --- a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc.so/readme.txt +++ /dev/null @@ -1 +0,0 @@ -This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt deleted file mode 100644 index 0d87eff..0000000 --- a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt +++ /dev/null @@ -1 +0,0 @@ -This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc.so/readme.txt deleted file mode 100644 index 0d87eff..0000000 --- a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc.so/readme.txt +++ /dev/null @@ -1 +0,0 @@ -This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt deleted file mode 100644 index 0d87eff..0000000 --- a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt +++ /dev/null @@ -1 +0,0 @@ -This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc.so/readme.txt deleted file mode 100644 index 0d87eff..0000000 --- a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc.so/readme.txt +++ /dev/null @@ -1 +0,0 @@ -This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt deleted file mode 100644 index 0d87eff..0000000 --- a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt +++ /dev/null @@ -1 +0,0 @@ -This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc.so/readme.txt deleted file mode 100644 index 0d87eff..0000000 --- a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc.so/readme.txt +++ /dev/null @@ -1 +0,0 @@ -This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt deleted file mode 100644 index 0d87eff..0000000 --- a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt +++ /dev/null @@ -1 +0,0 @@ -This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc16.mk b/board/MAI/bios_emulator/scitech/makedefs/bc16.mk deleted file mode 100644 index aa4fe76..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/bc16.mk +++ /dev/null @@ -1,137 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Borland C++ 4.x 16 bit version. Supports 16 bit DOS, -# DPMI16 DOS extender and 16 bit Windows development. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : USE_WIN16 USE_BC5 BC_LIBBASE USE_WIN95 - -# Default commands for compiling, assembling linking and archiving - CC := bcc - CFLAGS := -ml -H=bcc.sym -i60 -d -dc -4 -f287 -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx -.ELSE - AS := tasm -.ENDIF - ASFLAGS := /t /mx /m /iINCLUDE /iINCLUDE /i$(SCITECH)\INCLUDE - LD := bclink tlink.exe - LDFLAGS := -c - RC := brc - RCFLAGS := -.IF $(USE_BC5) -.IF $(USE_WIN95) - WIN_VERSION := -V4.0 -.ENDIF -.ENDIF - LIBR := tlib - LIBFLAGS := /C /P32 - ILIB := implib - ILIBFLAGS := -c - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -v - LDFLAGS += -v - ASFLAGS += /zi - LIBFLAGS += /P128 -.ELSE - LDFLAGS += -x - ASFLAGS += /q -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += -O2 -k- -.ELIF $(OPT_SIZE) - CFLAGS += -O1 -k- -.END - -# Optionally turn on direct i387 FPU instructions - -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -DFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -DBETA -.END - -# Optionally compile as Win16 -.IF $(USE_WIN16) -.IF $(BUILD_DLL) - CFLAGS += -WD -Fs- -DBUILD_DLL - ASFLAGS += -DBUILD_DLL -.ELSE - CFLAGS += -W -Fs- -.ENDIF - DEF_LIBS := import.lib mathwl.lib cwl.lib - DX_ASFLAGS += -D__WINDOWS16__ - LIB_OS = WIN16 -.ELSE - USE_REALDOS := 1 - DEF_LIBS := mathl.lib fp87.lib cl.lib - LIB_OS = DOS16 -.END - -# Place to look for PMODE library files - -.IF $(USE_DPMI16) -PMLIB := dpmi16\pm.lib -.ELSE -PMLIB := pm.lib -.END - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Define which file contains our rules - - RULES_MAK := bc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc3.mk b/board/MAI/bios_emulator/scitech/makedefs/bc3.mk deleted file mode 100644 index 133d80e..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/bc3.mk +++ /dev/null @@ -1,102 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Borland C++ 3.1 version. Supports 16 bit DOS development. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Default commands for compiling, assembling linking and archiving - CC := bcc - CFLAGS := -ml -H=bcc.sym -i60 -d -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx -.ELSE - AS := tasm -.ENDIF - ASFLAGS := /t /mx /m /iINCLUDE /i$(SCITECH)\INCLUDE - LD := bclink tlink.exe - LDFLAGS := -c - LIB := tlib - LIBFLAGS := /C - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -v - LDFLAGS += -v - ASFLAGS += /zi - LIBFLAGS += /P128 -.ELSE - LDFLAGS += -x - ASFLAGS += /q -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += -3 -O2 -.ELIF $(OPT_SIZE) - CFLAGS += -3 -O1 -.END - -# Optionally turn on direct i387 FPU instructions - -.IF $(FPU) - CFLAGS += -f287 -DFPU387 - ASFLAGS += -DFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -DBETA -.END - USE_REALDOS := 1 - -# Define the default libraries to link with - DEF_LIBS := mathl.lib cl.lib - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_DEST := $(LIB_BASE_DIR)\dos16\bc3 - -# Define which file contains our rules - - RULES_MAK := bc3.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc32.mk b/board/MAI/bios_emulator/scitech/makedefs/bc32.mk deleted file mode 100644 index 246de1d..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/bc32.mk +++ /dev/null @@ -1,201 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Borland C++ 4.0 32 bit version. Supports Borland's DOS Power -# Pack DPMI32 DOS extender, Phar Lap's TNT DOS Extender and -# 32 bit Windows development. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : USE_SMX32 USE_TNT USE_WIN32 USE_BC5 USE_VXD BC_LIBBASE -.IMPORT .IGNORE : VTOOLSD - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# Default commands for compiling, assembling linking and archiving - CC := bcc32 -.IF $(USE_VXD) - CFLAGS := -4 -i60 -d -w-stu -.ELSE - CFLAGS := -4 -H=bcc32.sym -i60 -d -w-stu -.ENDIF -.IF $(USE_NASM) - AS := nasm - ASFLAGS := -t -f obj -d__FLAT__ -iINCLUDE -i$(SCITECH)\INCLUDE -.ELSE -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx -.ELSE - AS := tasm -.ENDIF - ASFLAGS := /t /mx /m /w-res /w-mcp /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE -.ENDIF - LD := bclink tlink32.exe - LDFLAGS := -c - RC := brc32 -.IF $(USE_BC5) - WIN_VERSION := -V4.0 - RCFLAGS := -32 -.ELSE - RCFLAGS := -w32 -.ENDIF - LIB := tlib - LIBFLAGS := /C - ILIB := implib - ILIBFLAGS := -c - INTEL_X86 := 1 - NMSYM := $(SOFTICE_PATH)\nmsym.exe - NMSYMFLAGS := /TRANSLATE:source,package,always /PROMPT /SOURCE:$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\win32 - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -v - LDFLAGS += -v - LIBFLAGS += /P256 -.IF $(USE_NASM) - ASFLAGS += -F borland -g -.ELSE - ASFLAGS += /zi -.ENDIF -.ELSE - LDFLAGS += -x - LIBFLAGS += /P128 -.IF $(USE_NASM) - ASFLAGS += -F null -.ELSE - ASFLAGS += /q -.ENDIF -.END - -# Optionally disable nagging warnings if MAX_WARN is not on -.IF $(MAX_WARN) -.ELSE - CFLAGS += -w-aus -w-par -w-hid -w-pia -.ENDIF - -# Optionally turn on optimisations (-5 -O2 breaks BC++ 4.0-4.5 sometimes) -.IF $(OPT) - CFLAGS += -5 -O2 -k- -.ELIF $(OPT_SIZE) - CFLAGS += -5 -O1 -k- -.END - -# Optionally turn on direct i387 FPU instructions -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -dBETA -.END - -# Optionally use Phar Lap's TNT DOS Extender, otherwise use the DOS Power Pack -.IF $(USE_TNT) - CFLAGS += -D__MSDOS__ - DX_CFLAGS += -DTNT - DX_ASFLAGS += -dTNT - LIB_OS = DOS32 - DEF_LIBS := import32.lib cw32.lib dosx32.lib tntapi.lib -.ELIF $(USE_VXD) - LDFLAGS += -n -P- -x - CFLAGS += -RT- -x- -Oi -VC -I$(VTOOLSD)\INCLUDE -DIS_32 -DWANTVXDWRAPS -DVTOOLSD -DWIN40 -DWIN40_OR_LATER -DDEFSEG=1 -zC_LTEXT -zALCODE -zR_LDATA -zTLCODE - DEF_LIBS := $(VTOOLSD)\lib\cfbc440d.lib $(VTOOLSD)\lib\wr0bc440.lib $(VTOOLSD)\lib\wr1bc440.lib $(VTOOLSD)\lib\wr2bc440.lib $(VTOOLSD)\lib\wr3bc440.lib $(VTOOLSD)\lib\rtbc440d.lib - DX_ASFLAGS += -d__VXD__ -d__BORLANDC__=1 -I$(VTOOLSD)\INCLUDE -I$(VTOOLSD)\LIB\INCLUDE - LIB_OS = VXD -.ELIF $(USE_WIN32) -.IF $(WIN32_GUI) -.ELSE - CFLAGS += -D__CONSOLE__ -.ENDIF -.IF $(BUILD_DLL) - CFLAGS += -WD -DBUILD_DLL - ASFLAGS += -dBUILD_DLL -.ELSE - CFLAGS += -W -WM -.ENDIF -.IF $(USE_BC5) -.ELSE - CFLAGS += -D_WIN32 -.ENDIF - DEF_LIBS := import32.lib cw32mt.lib - DX_ASFLAGS += -d__WINDOWS32__ - LIB_OS = WIN32 -.ELIF $(USE_SMX32) - CFLAGS += -D__SMX32__ -DPME32 - DX_CFLAGS += - DX_ASFLAGS += -d__SMX32__ -dDPMI32 -dPME32 - USE_REALDOS := 1 - LIB_OS = SMX32 - DEF_LIBS := cw32mt.lib -.ELSE - USE_DPMI32 := 1 - CFLAGS += -D__MSDOS__ - DX_CFLAGS += -WX -DDPMI32 - DX_ASFLAGS += -dDPMI32 - USE_REALDOS := 1 - LIB_OS = DOS32 - DEF_LIBS := -.END - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Place to look for PMODE library files - -.IF $(USE_TNT) -PMLIB := $(LIB_BASE)\tnt\pm.lib -.ELIF $(USE_DPMI32) -PMLIB := $(LIB_BASE)\dpmi32\pm.lib -.ELSE -PMLIB := $(LIB_BASE)\pm.lib -.END - -# Define which file contains our rules - - RULES_MAK := bc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk b/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk deleted file mode 100644 index 23aeb7c..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk +++ /dev/null @@ -1,137 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Borland C++ 2.0 32-bit OS/2 version. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : USE_OS2GUI BC_LIBBASE - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# Default commands for compiling, assembling linking and archiving - CC := bcc - CFLAGS := -w- -4 -H=bcc32.sym -i60 -d -.IF $(USE_NASM) - AS := nasm - ASFLAGS := -t -f obj -d__FLAT__ -iINCLUDE -i$(SCITECH)\INCLUDE -.ELSE - AS := tasm - ASFLAGS := /t /mx /m /D__FLAT__ /D__OS2__ /iINCLUDE /i$(SCITECH)\INCLUDE -.ENDIF - LD := bclink tlink.exe - LDFLAGS := -c - RC := brcc - RCFLAGS := - LIB := tlib - LIBFLAGS := /C /P32 - ILIB := implib - ILIBFLAGS := -c -.IF $(USE_OS2GUI) - CFLAGS += -D__OS2_PM__ -.ENDIF - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -v - LDFLAGS += -v - LIBFLAGS += /P128 -.IF $(USE_NASM) - ASFLAGS += -F borland -.ELSE - ASFLAGS += /zi -.ENDIF -.ELSE - LDFLAGS += -x -.IF $(USE_NASM) - ASFLAGS += -F null -.ELSE - ASFLAGS += /q -.ENDIF -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += -5 -O2 -k- -.ELIF $(OPT_SIZE) - CFLAGS += -5 -O1 -k- -.END - -# Optionally turn on direct i387 FPU instructions -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -dBETA -.END - -# Optionally use Phar Lap's TNT DOS Extender, otherwise use the DOS Power Pack -.IF $(BUILD_DLL) - CFLAGS += -sd -sm -DBUILD_DLL - ASFLAGS += -dBUILD_DLL -.ELSE - CFLAGS += -sm -.ENDIF - DEF_LIBS := os2.lib c2mt.lib - DX_ASFLAGS += -d__OS2__ - LIB_OS = os232 - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Place to look for PMODE library files - -.IF $(USE_OS2GUI) -DEF_LIBS += pm_pm.lib -.ELSE -DEF_LIBS += pm.lib -.ENDIF - -# Define which file contains our rules - - RULES_MAK := bcos2.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/cl16.mk b/board/MAI/bios_emulator/scitech/makedefs/cl16.mk deleted file mode 100644 index 0f29a15..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/cl16.mk +++ /dev/null @@ -1,132 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Microsoft C 6.0 16 bit version. Supports 16 bit -# OS/2 development. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : VC_LIBBASE -.IMPORT .IGNORE : USE_MASM - -# Default commands for compiling, assembling linking and archiving - CC := cl # C-compiler and flags - CFLAGS := /w /Gs - ASFLAGS := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx # Assembler and flags -.ELIF $(USE_MASM) - AS := masm # Assembler and flags - ASFLAGS := /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE -.ELSE - AS := tasm # Assembler and flags -.ENDIF - LD := cl # Loader and flags - LDFLAGS = $(CFLAGS) - RC := rc # WIndows resource compiler - RCFLAGS := - LIB := lib # Librarian - LIBFLAGS := /NOI /NOE - ILIB := implib # Import librarian - ILIBFLAGS := /noignorecase - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += /Zi # Turn on debugging for C compiler - ASFLAGS += /zi # Turn on debugging for assembler -.ELSE - ASFLAGS += /q # Suppress object records not needed for linking -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += /Ox -.END - -# Optionally turn on direct i387 FPU instructions - -.IF $(FPU) - CFLAGS += /FPi87 /DFPU387 - ASFLAGS += /DFPU387 /DFPU_REG_RTN -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += /DBETA - ASFLAGS += /DBETA -.END - -# Use a larger stack during linking if requested ???? How the fuck do you -# specify linker options on the CL command line????? - -.IF $(STKSIZE) -.ENDIF - -# Optionally compile for 16 bit Windows -.IF $(USE_WIN16) -.IF $(BUILD_DLL) - CFLAGS += /GD /Alfw /DBUILD_DLL - ASFLAGS += -DBUILD_DLL -.ELSE - CFLAGS += /GA /AL -.ENDIF - DX_ASFLAGS += -D__WINDOWS16__ - LIB_OS = WIN16 -.ELSE - USE_REALDOS := 1 - CFLAGS += /AL - LIB_OS = DOS16 -.END - -# Place to look for PMODE library files - -PMLIB := pm.lib - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Define which file contains our rules - - RULES_MAK := cl16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/cl386.mk b/board/MAI/bios_emulator/scitech/makedefs/cl386.mk deleted file mode 100644 index 52157f9..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/cl386.mk +++ /dev/null @@ -1,120 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Microsoft 386 C 6.0 32 bit. Supports 32 bit -# OS/2 development. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : CL_LIBBASE USE_VDD -.IMPORT .IGNORE : USE_MASM - -# Default commands for compiling, assembling linking and archiving - CC := cl386 # C-compiler and flags - # NB: The -Zf flag is ABSOLUTELY NECESSARY to compile IBM's OS/2 headers. - # It isn't documented anywhere but obviously adds support for 48-bit - # far pointers (ie. _far is valid in 32-bit code). Great. - CFLAGS := -G3s -Zf -D__386__ - ASFLAGS := /t /mx /m /oi /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx # Assembler and flags -.ELIF $(USE_MASM) - AS := masm # Assembler and flags - ASFLAGS := /t /mx /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE -.ELSE - AS := tasm # Assembler and flags -.ENDIF - LD := link386 # Linker and flags - LDFLAGS = $(CFLAGS) - RC := rc # Windows resource compiler - RCFLAGS := - LIB := lib # Librarian - LIBFLAGS := /NOI /NOE - ILIB := implib # Import librarian - ILIBFLAGS := /noignorecase - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -Zi # Turn on debugging for C compiler - ASFLAGS += /zi # Turn on debugging for assembler -.ELSE - ASFLAGS += /q # Suppress object records not needed for linking -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += /Ox -.END - -# Optionally turn on direct i387 FPU instructions - -.IF $(FPU) - CFLAGS += /FPi87 /DFPU387 - ASFLAGS += /DFPU387 /DFPU_REG_RTN -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += /DBETA - ASFLAGS += /DBETA -.END - -# Use a larger stack during linking if requested ???? How the fuck do you -# specify linker options on the CL command line????? - -.IF $(STKSIZE) -.ENDIF - -# Place to look for PMODE library files - -PMLIB := pm.lib - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_OS = os232 - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(CL_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Define which file contains our rules - - RULES_MAK := cl386.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/common.mk b/board/MAI/bios_emulator/scitech/makedefs/common.mk deleted file mode 100644 index d337152..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/common.mk +++ /dev/null @@ -1,180 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Common makefile targets used by all SciTech Software -# makefiles. This file includes targets for cleaning the -# current directory, and maintaining the source files with -# RCS. -# -############################################################################# - -# Override global OpenGL includes when compiling against MGL version - -.IF $(USE_MGL_OPENGL) -.IF $(UNIX_HOST) -CFLAGS += -I$(SCITECH)/include/mglgl -DEPEND_INC += $(SCITECH)/include/mglgl -.ELSE -CFLAGS += -I$(SCITECH)\include\mglgl -DEPEND_INC += $(SCITECH)\include/mglgl -.ENDIF -.ENDIF - -# Define where to install all compiled DLL files - -.IF $(UNIX_HOST) -.IF $(CHECKED) -DLL_DEST := $(SCITECH_LIB)/redist/debug -.ELSE -DLL_DEST := $(SCITECH_LIB)/redist/release -.ENDIF -.ELSE -.IF $(CHECKED) -DLL_DEST := $(SCITECH_LIB)\redist\debug -.ELSE -DLL_DEST := $(SCITECH_LIB)\redist\release -.ENDIF -.ENDIF - -# Target to build the library and DLL file if specified - -.IF $(LIBFILE) - -lib: $(LIBFILE) - -.IF $(DLLFILE) - -# Build and install a DLL file, or simply build import library and install - -.IF $(BUILD_DLL) - -$(DLLFILE): $(OBJECTS) -$(LIBFILE): $(DLLFILE) -install: $(LIBFILE) $(DLLFILE) - $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) - $(INSTALL) $(DLLFILE) $(DLL_DEST) -.IF $(USE_SOFTICE) - $(INSTALL) $(DLLFILE:s/.dll/.nms) $(DLL_DEST) -.ENDIF -.ELSE - -$(LIBFILE): $(DLL_DEST)\$(DLLFILE) -install: $(LIBFILE) - $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) - -.ENDIF -.ELSE - -.IF $(BUILD_DLL) - -# Build and install a Unix shared library - -$(LIBFILE): $(OBJECTS) -install: $(LIBFILE) - $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) - $(INSTALL) $(LIBFILE) $(DLL_DEST)/$(LIBFILE).$(VERSION) - -.ELSE - -# Build and install a normal library file - -.IF $(USE_DLL) -.ELSE -$(LIBFILE): $(OBJECTS) -install: $(LIBFILE) - $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) -.ENDIF -.ENDIF -.ENDIF -.ENDIF - -# Build and install a VxD file, including debug information - -.IF $(VXDFILE) -$(VXDFILE:s/.vxd/.dll): $(OBJECTS) -$(VXDFILE): $(VXDFILE:s/.vxd/.dll) -install: $(VXDFILE) - $(INSTALL) $(VXDFILE) $(DLL_DEST) -.IF $(DBG) - $(INSTALL) $(VXDFILE:s/.vxd/.nms) $(DLL_DEST) -.ENDIF -.ENDIF - -# Clean up directory removing all files not needed to make the library. - -__CLEAN_FILES := *.obj *.o *.sym *.bak *.tdk *.swp *.map *.err *.csm *.lib *.aps *.nms *.sys -__CLEAN_FILES += *.~* *.td *.tr *.tr? *.td? *.rws *.res *.exp *.ilk *.pdb *.pch *.a bcc32.* -__CLEAN_FILES += $(LIBCLEAN) -__CLEANEXE_FILES := $(__CLEAN_FILES) *$E *.drv *.rex *.dll *.vxd *.nms *.pel *.smf *.so.* - -.PHONY clean: - @$(RM) -f -S $(mktmp $(__CLEAN_FILES:t"\n")) - -.PHONY cleanexe: - @$(RM) -f -S $(mktmp $(__CLEANEXE_FILES:t"\n")) - -# Define the source directories to find common files - -.IF $(NO_SCITECH_COMMON) -.ELSE -.SOURCE: $(SCITECH)/src/common -.ENDIF - -# Create the include file dependencies using the MKUTIL makedep program if -# the list of dependent object files is defined - -.IF $(DEPEND_OBJ) -depend: - @$(RM) -f makefile.dep -.IF $(DEPEND_SRC) -.IF $(DEPEND_INC) - @makedep -amakefile.dep -r -s -I@$(mktmp $(DEPEND_INC:s/\/\\)) -S@$(mktmp $(DEPEND_SRC:s/\/\\);$(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) -.ELSE - @makedep -amakefile.dep -r -s -S@$(mktmp $(DEPEND_SRC:s/\/\\);$(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) -.ENDIF -.ELSE -.IF $(DEPEND_INC) - @makedep -amakefile.dep -r -s -I@$(mktmp $(DEPEND_INC:s/\/\\)) -S@$(mktmp $(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) -.ELSE - @makedep -amakefile.dep -r -s -S@$(mktmp $(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) -.ENDIF -.ENDIF - @$(ECHO) Object file dependency information generated. -.ENDIF - -# Set up for compiling Snap executeables and dynamic link libraries - -.IF $(USE_SNAP) -#CFLAGS += -I$(PRIVATE)\include\drvlib -I$(SCITECH)\include\drvlib -D__SNAP__ -CFLAGS += -D__SNAP__ -ASFLAGS += -d__SNAP__ -#EXELIBS += snap$L -.ENDIF - -# Include rule definitions for the compiler - -.INCLUDE: "$(SCITECH)/makedefs/rules/$(RULES_MAK)" - -# Include file dependencies - -.INCLUDE .IGNORE: "makefile.dep" diff --git a/board/MAI/bios_emulator/scitech/makedefs/emx.mk b/board/MAI/bios_emulator/scitech/makedefs/emx.mk deleted file mode 100644 index f569790..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/emx.mk +++ /dev/null @@ -1,194 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# OS/2 version for EMX/GNU C/C++. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Disable warnings for macros redefined here that were given -# on the command line. -__.SILENT := $(.SILENT) -.SILENT := yes - -# Import enivornment variables that we use common to all compilers -.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB -.IMPORT .IGNORE : DBG OPT OPT_SIZE CRTDLL SHW BETA CHECKED NO_EXCEPT NO_RTTI -.IMPORT .IGNORE : FULLSCREEN SHOW_ARGS - TMPDIR := $(TEMP) - -# Standard file suffix definitions - L := .lib # Libraries - E := .exe # Executables - O := .obj # Objects - A := .asm # Assembler sources - S := .s # GNU assembler sources - P := .cpp # C++ sources - -# File prefix/suffix definitions. The following prefixes are defined, and are -# used primarily to abstract between the Unix style libXX.a naming convention -# and the DOS/Windows/OS2 naming convention of XX.lib. - LP := # LP - Library file prefix (name of file on disk) - LL := -l # Library link prefix (name of library on link command line) - LE := # Library link suffix (extension of library on link command line) - -# Import enivornment variables that we use -.IMPORT .IGNORE : EMX_LIBBASE USE_OS232 USE_OS2GUI - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# DMAKE uses this recipe to remove intermediate targets -.REMOVE :; $(RM) -f $< - -# Turn warnings back to previous setting. -.SILENT := $(__.SILENT) - -# We dont use TABS in our makefiles -.NOTABS := yes - -# Default commands for compiling, assembling linking and archiving. - CC := gcc - CFLAGS := -Zmt -Zomf -Wall -I. -I$(INCLUDE) - CXX := gcc -x c++ -fno-exceptions -fno-rtti -.IF $(USE_NASM) - AS := nasm - ASFLAGS := -t -f obj -F null -d__FLAT__ -d__NOU__ -iINCLUDE -i$(SCITECH)\INCLUDE -.ELSE - AS := tasm # Assembler and flags - ASFLAGS := /t /mx /m /oi /D__FLAT__ /D__NOU__ /iINCLUDE /i$(SCITECH)\INCLUDE -.ENDIF - LD := gcc - LDXX := gcc -x c++ - LDFLAGS := -L. -Zomf -Zmt - LIB := emxomfar - LIBFLAGS := -p32 rcv - - YACC := bison -y - LEX := flex - SED := sed - -# Optionally turn off exceptions and RTTI for C++ code -.IF $(NO_EXCEPT) - CXX += -fno-exceptions -.ENDIF -.IF $(NO_RTTI) - CXX += -fno-rtti -.ENDIF - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -g -.ELSE -# Without -s, emx always runs LINK386 with the /DEBUG option - CFLAGS += -s - LDFLAGS += -s -# NASM does not support debugging information yet - ASFLAGS += -.ENDIF - -# Optionally turn on optimisations -.IF $(OPT_MAX) - CFLAGS += -O6 -.ELIF $(OPT) - CFLAGS += -O3 -fomit-frame-pointer -.ELIF $(OPT_SIZE) - CFLAGS += -Os -.ENDIF - -# Optionally turn on direct i387 FPU instructions -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -dBETA -.ENDIF - -# Disable standard C runtime library -.IF $(NO_RUNTIME) -CFLAGS += -fno-builtin -nostdinc -.ENDIF - -# Link against EMX DLLs (CRTDLL=1) or link with static C runtime libraries -.IF $(CRTDLL) - LDFLAGS += -Zcrtdll -.ELSE - CFLAGS += -Zsys - LDFLAGS += -Zsys -.ENDIF - -# Target environment dependant flags - CFLAGS += -D__OS2_32__ - CFLAGS += -D__OS2__ - ASFLAGS += -d__OS2__ - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)/lib/release -.ENDIF - -# Define where to install library files - LIB_DEST := $(LIB_BASE_DIR)\OS232\$(EMX_LIBBASE) - LDFLAGS += -L$(LIB_DEST) - -# Build 32-bit OS/2 apps -.IF $(BUILD_DLL) - CFLAGS += -Zdll -DBUILD_DLL - LDFLAGS += -Zdll - ASFLAGS += -dBUILD_DLL -.ELSE -.IF $(USE_OS2GUI) - CFLAGS += -D__OS2_PM__ - LDFLAGS += -Zlinker /PMTYPE:PM -.ELSE -.IF $(FULLSCREEN) - LDFLAGS += -Zlinker /PMTYPE:NOVIO -.ELSE - LDFLAGS += -Zlinker /PMTYPE:VIO -.ENDIF -.ENDIF -.ENDIF - -# Place to look for PMODE library files - -PMLIB := -lpm - -# Define which file contains our rules - - RULES_MAK := emx.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk deleted file mode 100644 index 0d62fdf..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk +++ /dev/null @@ -1,161 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# BeOS version for GNU C/C++. -# -############################################################################# - -# Disable warnings for macros redefined here that were given -# on the command line. -__.SILENT := $(.SILENT) -.SILENT := yes - -# Import enivornment variables that we use common to all compilers -.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB -.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_X11 USE_LINUX -.IMPORT .IGNORE : USE_EGCS USE_PGCC STATIC_LIBS LIBC - TMPDIR := $(TEMP) - -# Standard file suffix definitions -# -# NOTE: BeOS does not require any extenion for executeable files, but you -# can use an extension if you wish. We use the .x extension for building -# executeable files so that we can use implicit rules to make the -# makefiles simpler and more portable between systems. When you install -# the files to a local bin directory, you will probably want to remove -# the .x extension. - L := .a # Libraries - E := .x # Executables - O := .o # Objects - A := .asm # Assembler sources - S := .s # GNU assembler sources - P := .cpp # C++ sources - -# File prefix/suffix definitions. The following prefixes are defined, and are -# used primarily to abstract between the Unix style libXX.a naming convention -# and the DOS/Windows/OS2 naming convention of XX.lib. - LP := lib # LP - Library file prefix (name of file on disk) - LL := -l # Library link prefix (name of library on link command line) - LE := # Library link suffix (extension of library on link command line) - -# We use the Unix shell at all times - SHELLFLAGS := -c - -# Definition of $(MAKE) macro for recursive makes. - MAKE = $(MAKECMD) $(MFLAGS) - -# Macro to install a library file - INSTALL := cp - -# DMAKE uses this recipe to remove intermediate targets -.REMOVE :; $(RM) -f $< - -# Turn warnings back to previous setting. -.SILENT := $(__.SILENT) - -# We dont use TABS in our makefiles -.NOTABS := yes - -# Define that we are compiling for BeOS - USE_BEOS := 1 - -# Default commands for compiling, assembling linking and archiving. - CC := gcc - CFLAGS := -Wall -I. -Iinclude $(INCLUDE) - CXX := g++ - AS := nasm - ASFLAGS := -f elf -d__FLAT__ -iinclude -i$(SCITECH)/include -d__NOU__ - LD := gcc - LDFLAGS := -L. - LIB := ar - LIBFLAGS := rcs - -# Link to static libraries if requested -.IF $(STATIC_LIBS) - LDFLAGS += -static -.ENDIF - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -g -.ELSE -# NASM does not support debugging information yet - ASFLAGS += -.ENDIF - -# Optionally turn on optimisations -.IF $(OPT_MAX) - CFLAGS += -O6 -.ELIF $(OPT) - CFLAGS += -O2 -.ELIF $(OPT_SIZE) - CFLAGS += -O1 -.ENDIF - -# Optionally turn on direct i387 FPU instructions -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -dBETA -.ENDIF - -# Disable standard C runtime library - -.IF $(NO_RUNTIME) -CFLAGS += -fno-builtin -nostdinc -.ENDIF - -# Target environment dependant flags - CFLAGS += -D__BEOS__ - ASFLAGS += -d__BEOS__ -d__UNIX__ - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)/lib/release -.ENDIF - -# Define where to install library files -LIB_DEST := $(LIB_BASE_DIR)/beos/gcc -LDFLAGS += -L$(LIB_DEST) - -# Place to look for PMODE library files - -PMLIB := -lpm - -# Define which file contains our rules - - RULES_MAK := gcc_beos.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk deleted file mode 100644 index 65589c8..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk +++ /dev/null @@ -1,112 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# DJGPP V2 port of GNU C/C++ to DOS with DPMI only. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Override some file suffix definitions - L := .a # Libraries - O := .o # Objects - -# Override the file prefix/suffix definitions for library naming. - LP := lib # LP - Library file prefix (name of file on disk) - LL := -l # Library link prefix (name of library on link command line) - LE := # Library link suffix (extension of library on link command line) - -# Import enivornment variables that we use -.IMPORT .IGNORE : DJ_LIBBASE - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# Default commands for compiling, assembling linking and archiving - CC := gcc # C-compiler and flags - CFLAGS := -Wall - AS := nasm - ASFLAGS := -t -f coff -F null -d__FLAT__ -d__GNUC__ -dSTDCALL_USCORE -iINCLUDE -i$(SCITECH)\INCLUDE - LD := dj_ld # Loader and flags - LDFLAGS := - LIB := ar # Librarian - LIBFLAGS := rs - USE_NASM := 1 - USE_GCC := 1 - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -g # Turn on debugging for C compiler -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += -O2 -.ELIF $(OPT_SIZE) - CFLAGS += -O1 -.END - -# Optionally turn on direct i387 FPU instructions - -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -dBETA -.END - -# DOS extender dependant flags - DX_CFLAGS += - DX_ASFLAGS += -dDJGPP - USE_REALDOS := 1 - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_DEST := $(LIB_BASE_DIR)\DOS32\$(DJ_LIBBASE) - -# Place to look for PMODE library files - -PMLIB := -lpm - -# Define which file contains our rules - - RULES_MAK := dj32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk deleted file mode 100644 index 0cb4b85..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk +++ /dev/null @@ -1,174 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Linux version for GNU C/C++. -# -############################################################################# - -# Disable warnings for macros redefined here that were given -# on the command line. -__.SILENT := $(.SILENT) -.SILENT := yes - -# Import enivornment variables that we use common to all compilers -.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB -.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_X11 USE_FREEBSD -.IMPORT .IGNORE : USE_EGCS USE_PGCC STATIC_LIBS - TMPDIR := $(TEMP) - -# Standard file suffix definitions -# -# NOTE: Linux does not require any extenion for executeable files, but you -# can use an extension if you wish. We use the .x extension for building -# executeable files so that we can use implicit rules to make the -# makefiles simpler and more portable between systems. When you install -# the files to a local bin directory, you will probably want to remove -# the .x extension. - L := .a # Libraries - E := .x # Executables - O := .o # Objects - A := .asm # Assembler sources - S := .s # GNU assembler sources - P := .cpp # C++ sources - -# File prefix/suffix definitions. The following prefixes are defined, and are -# used primarily to abstract between the Unix style libXX.a naming convention -# and the DOS/Windows/OS2 naming convention of XX.lib. - LP := lib # LP - Library file prefix (name of file on disk) - LL := -l # Library link prefix (name of library on link command line) - LE := # Library link suffix (extension of library on link command line) - -# We use the Unix shell at all times - SHELL := /bin/sh - SHELLFLAGS := -c - -# Definition of $(MAKE) macro for recursive makes. - MAKE = $(MAKECMD) $(MFLAGS) - -# Macro to install a library file - INSTALL := cp - -# DMAKE uses this recipe to remove intermediate targets -.REMOVE :; $(RM) -f $< - -# Turn warnings back to previous setting. -.SILENT := $(__.SILENT) - -# We dont use TABS in our makefiles -.NOTABS := yes - -# Define that we are compiling for FreeBSD - USE_LINUX := 1 - -# Default commands for compiling, assembling linking and archiving. -.IF $(USE_EGCS) - CC := egcs -.ELIF $(USE_PGCC) - CC := pgcc -.ELSE - CC := gcc -.ENDIF - CFLAGS := -Wall -I. -Iinclude $(INCLUDE) - CXX := g++ - AS := nasm -# TODO: On earlier versions of FreeBSD (<3.0) a.out is used instead of ELF - ASFLAGS := -f elf -d__FLAT__ -iinclude -i$(SCITECH)/include -d__NOU__ - LD := g++ - LDFLAGS := -L. - LIB := ar - LIBFLAGS := rcs - -# Link to static libraries if requested -.IF $(STATIC_LIBS) - LDFLAGS += -static -.ENDIF - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -g -.ELSE -# NASM does not support debugging information yet - ASFLAGS += -.ENDIF - -# Optionally turn on optimisations -.IF $(OPT_MAX) - CFLAGS += -O6 -.ELIF $(OPT) - CFLAGS += -O2 -.ELIF $(OPT_SIZE) - CFLAGS += -O1 -.ENDIF - -# Optionally turn on direct i387 FPU instructions -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -dBETA -.ENDIF - -# Disable standard C runtime library - -.IF $(NO_RUNTIME) -CFLAGS += -fno-builtin -nostdinc -.ENDIF - -# Compile flag for whether to build X11 or non-X11 lib -.IF $(USE_X11) - CFLAGS += -D__X11__ -.ENDIF - -# Target environment dependant flags - CFLAGS += -D__FREEBSD__ - ASFLAGS += -d__FREEBSD__ -d__UNIX__ - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)/lib/release -.ENDIF - -# Define where to install library files - LIB_DEST := $(LIB_BASE_DIR)/freebsd/gcc - LDFLAGS += -L$(LIB_DEST) - -# Place to look for PMODE library files - -PMLIB := -lpm - -# Define which file contains our rules - - RULES_MAK := gcc_freebsd.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk deleted file mode 100644 index 72c4ced..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk +++ /dev/null @@ -1,180 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Linux version for GNU C/C++. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)/makedefs/startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : GCC2_LIBBASE - -# Override some file suffix definitions - L := .a # Libraries - O := .o # Objects - -# Override the file prefix/suffix definitions for library naming. - LP := lib # LP - Library file prefix (name of file on disk) - LL := -l # Library link prefix (name of library on link command line) - LE := # Library link suffix (extension of library on link command line) - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# Define that we are compiling for Linux - USE_LINUX := 1 - -# Default commands for compiling, assembling linking and archiving. - CC := gcc - CFLAGS := -Wall -I. -Iinclude -I$(SCITECH:s,\,/)/include -I$(PRIVATE:s,\,/)/include - SHOW_CFLAGS := -c - CXX := g++ - AS := nasm - ASFLAGS := -t -f elf -d__FLAT__ -d__GNUC__ -iinclude -i$(SCITECH)/include -d__NOU__ - SHOW_ASFLAGS := -f elf - LD := gcc - LDXX := g++ - LDFLAGS := -L. - LIB := ar - LIBFLAGS := rcs - YACC := bison -y - LEX := flex - SED := sed - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -g - SHOW_CFLAGS += -g -.ELSE -# NASM does not support debugging information yet - ASFLAGS += -.ENDIF - -# Optionally turn on optimisations -.IF $(OPT_MAX) - CFLAGS += -O6 - SHOW_CFLAGS += -O6 -.ELIF $(OPT) - CFLAGS += -O2 - SHOW_CFLAGS += -O2 -.ELIF $(OPT_SIZE) - CFLAGS += -O1 - SHOW_CFLAGS += -O1 -.ENDIF - -# Optionally turn on direct i387 FPU instructions -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - SHOW_CFLAGS += -DBETA - ASFLAGS += -dBETA - SHOW_ASFLAGS += -dBETA -.ENDIF - -# Disable standard C runtime library - -.IF $(NO_RUNTIME) -CFLAGS += -fno-builtin -nostdinc -.ENDIF - -# Compile flag for whether to build X11 or non-X11 lib -.IF $(USE_X11) - CFLAGS += -D__X11__ -.ENDIF - -# Target environment dependant flags - CFLAGS += -D__LINUX__ - ASFLAGS += -d__LINUX__ -d__UNIX__ - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug -CFLAGS += -DCHECKED=1 -SHOW_CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)/lib/release -.ENDIF - -# Define where to install library files -.IF $(LIBC) - LIB_DEST_SHARED := $(LIB_BASE_DIR)/linux/gcc/libc.so - LIB_DEST_STATIC := $(LIB_BASE_DIR)/linux/gcc/libc -.ELSE - LIB_DEST_SHARED := $(LIB_BASE_DIR)/linux/gcc/glibc.so - LIB_DEST_STATIC := $(LIB_BASE_DIR)/linux/gcc/glibc -.ENDIF - -# Link to static libraries if requested -.IF $(STATIC_LIBS_ALL) - LDFLAGS += -static - STATIC_LIBS := 1 -.ENDIF - -# Link to static libraries if requested -.IF $(STATIC_LIBS) - LDFLAGS += -L$(LIB_DEST_STATIC) -.ELSE - LDFLAGS += -L$(LIB_DEST_SHARED) -L$(LIB_DEST_STATIC) -.ENDIF - -# Optionally enable some dynamic libraries to be built -.IF $(BUILD_DLL) -.IF $(VERSIONMAJ) -.ELSE - VERSIONMAJ := 5 - VERSIONMIN := 0 -.ENDIF - VERSION := $(VERSIONMAJ).$(VERSIONMIN) - LIB := gcc -shared - LIBFLAGS := - L := .so - CFLAGS += -fPIC - SHOW_CFLAGS += -fPIC - ASFLAGS += -D__PIC__ - SHOW_ASFLAGS += -D__PIC__ - LIB_DEST := $(LIB_DEST_SHARED) -.ELSE - LIB_DEST := $(LIB_DEST_STATIC) -.ENDIF - -# Place to look for PMODE library files - -PMLIB := -lpm - -# Define which file contains our rules - - RULES_MAK := gcc_linux.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk deleted file mode 100644 index 21ccf97..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk +++ /dev/null @@ -1,135 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Cygwin port of GNU C/C++ to Win32. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : GCC2_LIBBASE - -# Override some file suffix definitions - L := .a # Libraries - O := .o # Objects - -# Override the file prefix/suffix definitions for library naming. - LP := lib # LP - Library file prefix (name of file on disk) - LL := -l # Library link prefix (name of library on link command line) - LE := # Library link suffix (extension of library on link command line) - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# Default commands for compiling, assembling linking and archiving - CC := gcc # C-compiler and flags - CFLAGS := -Wall -I. -Iinclude -I$(SCITECH:s,\,/)/include -I$(PRIVATE:s,\,/)/include - SHOW_CFLAGS := -c - CXX := g++ - AS := nasm - ASFLAGS := -t -f coff -F null -d__FLAT__ -d__GNUC__ -dSTDCALL_USCORE -iINCLUDE -i$(SCITECH)\INCLUDE - SHOW_ASFLAGS := -f coff - LD := gcc # Loader and flags - LDXX := g++ -.IF $(WIN32_GUI) - LDFLAGS := -L. -mwindows -e _mainCRTStartup -.ELSE - LDFLAGS := -L. -.ENDIF - RC := windres - RCFLAGS := -O coff - LIB := ar # Librarian - LIBFLAGS := rcs - YACC := bison -y - LEX := flex - SED := sed - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -g - SHOW_CFLAGS += -g -.ELSE -# NASM does not support debugging information yet - ASFLAGS += -.ENDIF - -# Optionally turn on optimisations -.IF $(OPT_MAX) - CFLAGS += -O6 - SHOW_CFLAGS += -O6 -.ELIF $(OPT) - CFLAGS += -O2 - SHOW_CFLAGS += -O2 -.ELIF $(OPT_SIZE) - CFLAGS += -O1 - SHOW_CFLAGS += -O1 -.ENDIF - -# Optionally turn on direct i387 FPU instructions - -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - SHOW_CFLAGS += -DBETA - ASFLAGS += -dBETA - SHOW_ASFLAGS += -dBETA -.ENDIF - -# DOS extender dependant flags - DX_CFLAGS += - DX_ASFLAGS += -dGCC_WIN32 - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -SHOW_CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_DEST := $(LIB_BASE_DIR)\WIN32\$(GCC2_LIBBASE) - LDFLAGS += -L$(LIB_DEST) - -# Place to look for PMODE library files - -PMLIB := -lpm - -# Define which file contains our rules - - RULES_MAK := gcc_win32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/hc32.mk b/board/MAI/bios_emulator/scitech/makedefs/hc32.mk deleted file mode 100644 index f0b065a..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/hc32.mk +++ /dev/null @@ -1,113 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Metaware High C/C++ 3.21 32 bit version. Supports Phar Lap's -# TNT DOS Extender. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# Default commands for compiling, assembling linking and archiving - CC := hc386 # C-compiler and flags - CFLAGS := -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx # Assembler and flags -.ELSE - AS := tasm # Assembler and flags -.ENDIF - ASFLAGS := /t /mx /m /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE - LD := hc386 - LDFLAGS = $(CFLAGS) - LIB := 386lib # TNT 386|lib Librarian - LIBFLAGS := -TC - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -g # Turn on debugging for C compiler - ASFLAGS += /zi # Turn on debugging for assembler -.ELSE - ASFLAGS += /q # Suppress object records not needed for linking -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += -586 -O -.ELIF $(OPT_SIZE) - CFLAGS += -586 -O1 -.ELSE - CFLAGS += -O0 -.END - -# Optionally turn on direct i387 FPU instructions - -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -DFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -DBETA -.END - -# DOS extender dependant flags - USE_TNT := 1 - USE_REALDOS := 1 - DX_CFLAGS += -DTNT - DX_ASFLAGS += -DTNT - LDFLAGS += -LH:\TNT\LIB - -# Place to look for PMODE library files - -PMLIB := tnt\pm.lib - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\DOS32\HC - LIB_DEST := $(LIB_BASE) - -# Define which file contains our rules - - RULES_MAK := hc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj b/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj deleted file mode 100644 index edd8809..0000000 Binary files a/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/makedefs/qnx4.mk b/board/MAI/bios_emulator/scitech/makedefs/qnx4.mk deleted file mode 100644 index f583af3..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/qnx4.mk +++ /dev/null @@ -1,164 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# QNX version for Watcom C. -# -############################################################################# - -# Disable warnings for macros redefined here that were given -# on the command line. -__.SILENT := $(.SILENT) -.SILENT := yes - -# Import enivornment variables that we use common to all compilers -.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB -.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_QNX USE_QNX4 -.IMPORT .IGNORE : USE_PHOTON USE_X11 USE_BIOS SHOW_ARGS MAX_WARN WC_LIBBASE - TMPDIR := $(TEMP) - -# Standard file suffix definitions -# -# NOTE: Qnx does not require any extension for executeable files, but you -# can use an extension if you wish. We use the .x extension for building -# executeable files so that we can use implicit rules to make the -# makefiles simpler and more portable between systems. When you install -# the files to a local bin directory, you will probably want to remove -# the .x extension. - L := .a # Libraries - E := .exe # Executables - O := .o # Objects - A := .asm # Assembler sources - S := .s # GNU assembler sources - P := .cpp # C++ sources - -# File prefix/suffix definitions. The following prefixes are defined, and are -# used primarily to abstract between the Unix style libXX.a naming convention -# and the DOS/Windows/OS2 naming convention of XX.lib. - LP := lib # LP - Library file prefix (name of file on disk) - LL := -l # Library link prefix (name of library on link command line) - LE := # Library link suffix (extension of library on link command line) - -# We use the Unix shell at all times - SHELL := /bin/sh - SHELLFLAGS := -c - -# Definition of $(MAKE) macro for recursive makes. - MAKE = $(MAKECMD) $(MFLAGS) - -# Macro to install a library file - INSTALL := cp - -# DMAKE uses this recipe to remove intermediate targets -.REMOVE :; $(RM) -f $< - -# Turn warnings back to previous setting. -.SILENT := $(__.SILENT) - -# We dont use TABS in our makefiles -.NOTABS := yes - -# Define that we are compiling for QNX - USE_QNX := 1 - -# Default commands for compiling, assembling linking and archiving. - CC := wcc386 - CFLAGS := -I. -Iinclude $(INCLUDE) - CXX := wpp386 - AS := nasm - ASFLAGS := -t -f obj -d__FLAT__ -dSTDCALL_MANGLE -iinclude -i$(SCITECH)/include - LD := cc - LDFLAGS := -L. - LIB := ar - LIBFLAGS := rc - -# Set the compiler warning level -.IF $(MAX_WARN) - CFLAGS += -w4 -.ELSE - CFLAGS += -w1 -.ENDIF - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -d2 - LDFLAGS += -g2 -.ELSE -# NASM does not support debugging information yet - ASFLAGS += -.ENDIF - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += -onatx-5r-fp5 -.ELIF $(OPT_SIZE) - CFLAGS += -onaslmr-5r-fp5 -.ELIF $(NOOPT) - CFLAGS += -od-5r -.END - -# Compile flag for whether to build photon or non-photon lib -.IF $(USE_PHOTON) - CFLAGS += -D__PHOTON__ -.ENDIF - -# Compile flag for whether to build X11 or non-X11 lib -.IF $(USE_X11) - CFLAGS += -D__X11__ -.ENDIF - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -dBETA -.ENDIF - -# Target environment dependant flags - CFLAGS += -D__QNX__ -D__UNIX__ - ASFLAGS += -d__QNX__ -d__UNIX__ - -# Define the base directory for library files - -.IF $(CHECKED) - LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug - CFLAGS += -DCHECKED=1 -.ELSE - LIB_BASE_DIR := $(SCITECH_LIB)/lib/release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)/qnx4/$(WC_LIBBASE) - LIB_DEST := $(LIB_BASE) - LDFLAGS += -L$(LIB_DEST) - -# Place to look for PMODE library files - -PMLIB := -lpm - -# Define which file contains our rules - - RULES_MAK := qnx4.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/qnxnto.mk b/board/MAI/bios_emulator/scitech/makedefs/qnxnto.mk deleted file mode 100644 index 5168ed2..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/qnxnto.mk +++ /dev/null @@ -1,157 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# QNX Neutrino version for GNU C/C++ -# -############################################################################# - -# Disable warnings for macros redefined here that were given -# on the command line. -__.SILENT := $(.SILENT) -.SILENT := yes - -# Import enivornment variables that we use common to all compilers -.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB -.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_QNX USE_QNXNTO -.IMPORT .IGNORE : USE_EGCS USE_PHOTON USE_X11 USE_BIOS - TMPDIR := $(TEMP) - -# Standard file suffix definitions -# -# NOTE: Qnx does not require any extension for executeable files, but you -# can use an extension if you wish. We use the .x extension for building -# executeable files so that we can use implicit rules to make the -# makefiles simpler and more portable between systems. When you install -# the files to a local bin directory, you will probably want to remove -# the .x extension. - L := .a # Libraries - E := .x # Executables - O := .o # Objects - A := .asm # Assembler sources - S := .s # GNU assembler sources - P := .cpp # C++ sources - -# File prefix/suffix definitions. The following prefixes are defined, and are -# used primarily to abstract between the Unix style libXX.a naming convention -# and the DOS/Windows/OS2 naming convention of XX.lib. - LP := lib # LP - Library file prefix (name of file on disk) - LL := -l # Library link prefix (name of library on link command line) - LE := # Library link suffix (extension of library on link command line) - -# We use the Unix shell at all times - SHELL := /bin/sh - SHELLFLAGS := -c - -# Definition of $(MAKE) macro for recursive makes. - MAKE = $(MAKECMD) $(MFLAGS) - -# Macro to install a library file - INSTALL := cp - -# DMAKE uses this recipe to remove intermediate targets -.REMOVE :; $(RM) -f $< - -# Turn warnings back to previous setting. -.SILENT := $(__.SILENT) - -# We dont use TABS in our makefiles -.NOTABS := yes - -# Define that we are compiling for QNX - USE_QNX := 1 - -# Default commands for compiling, assembling linking and archiving. - CC := qcc - CFLAGS := -Vgcc_ntox86 -I. -Iinclude $(INCLUDE) - CPPFLAGS := -Vgcc_ntox86 -I. -Iinclude $(INCLUDE) - CXX := QCC - AS := nasm - ASFLAGS := -t -f elf -d__FLAT__ -d__GNUC__ -dSTDCALL_MANGLE -iinclude -i$(SCITECH)/include -d__NOU__ - LD := qcc - LDFLAGS := -Vgcc_ntox86 -L. -lm - LIB := ar - LIBFLAGS := rc - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -g2 - LDFLAGS += -g2 -.ELSE -# NASM does not support debugging information yet - ASFLAGS += -.ENDIF - -# Optionally turn on optimisations -.IF $(OPT_MAX) - CFLAGS += -Ot -.ELIF $(OPT) - CFLAGS += -O -.ELIF $(OPT_SIZE) - CFLAGS += -Os -.ENDIF - -# Compile flag for whether to build photon or non-photon lib -.IF $(USE_PHOTON) - CFLAGS += -D__PHOTON__ -.ENDIF - -# Compile flag for whether to build X11 or non-X11 lib -.IF $(USE_X11) - CFLAGS += -D__X11__ -.ENDIF - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -dBETA -.ENDIF - -# Target environment dependant flags - CFLAGS += -D__QNX__ -D__UNIX__ - ASFLAGS += -d__QNX__ -d__UNIX__ - -# Define the base directory for library files - -.IF $(CHECKED) - LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug - CFLAGS += -DCHECKED=1 -.ELSE - LIB_BASE_DIR := $(SCITECH_LIB)/lib/release -.ENDIF - -# Define where to install library files - LIB_DEST := $(LIB_BASE_DIR)/qnxnto - LDFLAGS += -L$(LIB_DEST) - -# Place to look for PMODE library files - -PMLIB := -lpm - -# Define which file contains our rules - - RULES_MAK := qnxnto.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bc16.mk deleted file mode 100644 index 67ae910..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/bc16.mk +++ /dev/null @@ -1,69 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $< -%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $< -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building a DLL using a response file -%$D: ; $(LD) $(mktmp $(LDFLAGS) -C -Twd c0dl.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(EXELIBS)\n$*.def) - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ $? -.ELIF $(IMPORT_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ $? -.ELSE -%$L: ; - @$(RM) $@ - $(LIBR) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n) -.ENDIF - -# Implicit rule for building an executable file using response file -.IF $(USE_WIN16) -%$E: ; $(LD) $(mktmp $(LDFLAGS) -C -Twe $(WIN_VERSION) c0wl.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(EXELIBS)\n$*.def) -.ELSE -%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tde c0l.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(PMLIB) $(DEF_LIBS) $(EXELIBS)) -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bc3.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bc3.mk deleted file mode 100644 index d4d071c..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/bc3.mk +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) @$(mktmp $(CFLAGS)) -c $< -%$O: %$P ; $(CC) @$(mktmp $(CFLAGS)) -c $< -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\) - -# Implicit rule for building a library file using response file -%$L: ; - @$(RM) $@ - $(LIBR) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n) - -# Implicit rule for building an executable file using response file -%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tde c0l.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(EXELIBS)) diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bc32.mk deleted file mode 100644 index e3ce25b..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/bc32.mk +++ /dev/null @@ -1,151 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -.IF $(USE_VXD) - -# Implicit rule generation to build VxD's - -%$O: %.c ; - $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) - @$(VTOOLSD)\bin\segalias.exe -p $(VTOOLSD)\include\default.seg $@ - -%$O: %$P ; - $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) - @$(VTOOLSD)\bin\segalias.exe -p $(VTOOLSD)\include\default.seg $@ - -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) - -%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+")\n) - -%.dll: ; - @$(CP) $(mktmp EXPORTS\n_The_DDB @1) $*.def - tlink32.exe @$(mktmp $(LDFLAGS) -Tpd $(VTOOLSD:s/\/\\)\lib\icrtbc4.obj+\n$(&:s/\/\\)\n$*.dll\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS:s/\/\\)\n$*.def) - @$(RM) -S $(mktmp $*.def) - -%.vxd: %.dll ; - @$(CP) $(mktmp DYNAMIC\nATTRIB ICODE INIT\nATTRIB LCODE LOCKED\nATTRIB PCODE PAGEABLE\nATTRIB SCODE STATIC\nATTRIB DBOCODE DEBUG\nMERGE ICODE INITDAT0 INITDATA) $*.pel - @$(VTOOLSD)\bin\vxdver.exe $*.vrc $*.res - @$(VTOOLSD)\bin\pele.exe -d -s $*.smf -c $*.pel -o $@ -k 400 $*.dll - @$(VTOOLSD)\bin\sethdr.exe -n $* -x $@ -r $*.res -.IF $(DBG) - $(NMSYM) /TRANS:source,package /SOURCE:$(VXDSOURCE) $*.smf -.ENDIF - @$(RM) -S $(mktmp $*.pel) - -.ELSE - -# Implicit generation rules for making object files, libraries and exe's - -%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) -%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) -.IF $(USE_NASM) -%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ELSE -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ENDIF - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building a DLL using a response file -.IF $(IMPORT_DLL) -.ELSE -.IF $(NO_RUNTIME) -%$D: ; $(LD) $(mktmp $(LDFLAGS) -Tpd -aa $(&:s/\/\\)\n$@\n$*.map\n$(EXELIBS)\n$*.def) -.ELSE -%$D: ; - makedef $(@:b) - $(LD) $(mktmp $(LDFLAGS) -Tpd -aa c0d32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) -.IF $(DBG) -.IF $(USE_SOFTICE) - $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ - tdstrp32 $@ -.ENDIF -.ENDIF -.ENDIF -.ENDIF - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ $? -.ELIF $(IMPORT_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ $? -.ELSE -%$L: ; - @$(RM) $@ - $(LIB) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n) -.ENDIF - -# Implicit rule for building an executable file using response file - -.IF $(USE_WIN32) -.IF $(WIN32_GUI) -%$E: ; - $(LD) $(mktmp $(LDFLAGS) -Tpe -aa $(WIN_VERSION) c0w32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) -.IF $(DBG) -.IF $(USE_SOFTICE) - $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ - tdstrp32 $@ -.ENDIF -.ENDIF -.ELSE -%$E: ; - $(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) -.IF $(USE_SOFTICE) - $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ - tdstrp32 $@ -.ENDIF -.ENDIF -.ELIF $(USE_TNT) -%$E: ; - @$(CP) $(mktmp stub 'gotnt.exe') $*.def - @$(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) -.IF $(DOSSTYLE) - @markphar $@ -.ENDIF - @$(RM) -S $(mktmp $*.def) -.ELIF $(USE_SMX32) -%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) -.ELSE -%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def) -.END - -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bcos2.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bcos2.mk deleted file mode 100644 index f473fec..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/bcos2.mk +++ /dev/null @@ -1,70 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) -%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\) -.IF $(USE_NASM) -%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ELSE -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ENDIF - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building a DLL using a response file -%$D: ; - makedef $(@:b) - $(LD) $(mktmp $(LDFLAGS) -Tod -aa c02d.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(EXELIBS)\n$*.def) - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ $? -.ELIF $(IMPORT_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ $? -.ELSE -%$L: ; - @$(RM) $@ - $(LIB) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n) -.ENDIF - -# Implicit rule for building an executable file using response file - -.IF $(USE_OS2GUI) -%$E: ; $(LD) $(mktmp $(LDFLAGS) -Toe -aa c02.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(EXELIBS)\n$*.def) -.ELSE -%$E: ; $(LD) $(mktmp $(LDFLAGS) -Toe -ap c02.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(EXELIBS)\n$*.def) -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/cl16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/cl16.mk deleted file mode 100644 index 6489a3e..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/cl16.mk +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) /nologo $(CFLAGS) /c $< -%$O: %$P ; $(CC) /nologo $(CFLAGS) /c $< -%$O: %$A ; $(AS) $(ASFLAGS) $< $* NUL NUL - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building a DLL using a response file -#%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS:s/\/\\) -e$@\n$(&:t"\n":s/\/\\)\n$(EXELIBS)) -#%$D: ; $(LD) $(LDFLAGS) /Fe$@ $& $(EXELIBS) -%$D: ; link @default.rsp - - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? -.ELIF $(IMPORT_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? -.ELSE -%$L: ; $(LIB) /nologo $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+") &\n,,\n) -.ENDIF - -# Implicit rule for building an executable file using response file -.IF $(USE_WIN16) -#%$E: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) -%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) -.ELSE -%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(PMLIB) $(EXELIBS)) -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/cl386.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/cl386.mk deleted file mode 100644 index f50b274..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/cl386.mk +++ /dev/null @@ -1,69 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) -nologo $(CFLAGS) -c $< -%$O: %$P ; $(CC) -nologo $(CFLAGS) -c $< -%$O: %$A ; $(AS) $(ASFLAGS) $< $* NUL NUL - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building a DLL using a response file -#%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS:s/\/\\) -e$@\n$(&:t"\n":s/\/\\)\n$(EXELIBS)) -#%$D: ; $(LD) $(LDFLAGS) /Fe$@ $& $(EXELIBS) -%$D: ; link386 @default.rsp - -# Implicit rule for building a device driver using a response file -%.SYS: ; link386 @default.rsp - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? -.ELIF $(IMPORT_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? -.ELSE -%$L: ; $(LIB) /nologo $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+") &\n,,\n) -.ENDIF - -# Implicit rule for building an executable file using response file -.IF $(USE_WIN16) -#%$E: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) -%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) -.ELSE -%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(PMLIB) $(EXELIBS)) -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/dj32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/dj32.mk deleted file mode 100644 index 9f917bb..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/dj32.mk +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\) -c) $(<:s,/,\) -%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\) -c) $(<:s,/,\) -%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) - -# Implicit rule for building a library file using response file -%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp $(&:s/\/\\)\n) - -# Implicit rule for building an executable file using response file -%$E: ; $(LD) $(LDFLAGS) $@ @$(mktmp $(&:s/\/\\) $(EXELIBS) $(PMLIB) -lstdcxx -lm) diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/emx.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/emx.mk deleted file mode 100644 index 26d223a..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/emx.mk +++ /dev/null @@ -1,91 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -# OS/2 version for EMX/GNU C/C++. -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; -.IF $(SHOW_ARGS) - $(CC) -c $(CFLAGS) $(<:s,\,/) -.ELSE - @echo $(CC) -c $(<:s,\,/) - @$(CC) -c $(CFLAGS) $(<:s,\,/) -.ENDIF - -%$O: %$P ; -.IF $(SHOW_ARGS) - $(CXX) -c $(CFLAGS) $(<:s,\,/) -.ELSE - @echo $(CXX) -c $(<:s,\,/) - @$(CXX) -c $(CFLAGS) $(<:s,\,/) -.ENDIF - -%$O: %$A ; -.IF $(USE_NASM) -.IF $(SHOW_ARGS) - $(AS) -o $@ $(ASFLAGS) $(<:s,\,/) -.ELSE - @echo $(AS) $(<:s,\,/) - @$(AS) @$(mktmp -o $@ $(ASFLAGS)) $(<:s,\,/) -.ENDIF -.ELSE -.IF $(SHOW_ARGS) - - $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ELSE - @echo $(AS) $(<:s,/,\) - $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ENDIF -.ENDIF - -# Implicit rule for building a library file using response file -%$L: ; -.IF $(SHOW_ARGS) - $(LIB) $(LIBFLAGS) $@ $(&:s,\,/) -.ELSE - @echo $(LIB) $@ - @$(LIB) $(LIBFLAGS) $@ @$(mktmp $(?:t"\n")) -.ENDIF - -# Implicit rule for building an executable file using response file -%$E: ; -.IF $(SHOW_ARGS) - $(LD) $(LDFLAGS) -o $@ $(&:s,\,/) $(EXELIBS) $(PMLIB) -lgpp -lstdcpp -.ELSE - @echo $(LD) $@ - @$(LD) $(LDFLAGS) -o $@ $(&:s,\,/) $(EXELIBS) $(PMLIB) -lgpp -lstdcpp -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_beos.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_beos.mk deleted file mode 100644 index 681b698..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_beos.mk +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files from source files -%$O: %.c ; $(CC) $(CFLAGS) -c $< -%$O: %$P ; $(CXX) $(CFLAGS) -c $< -%$O: %$A ; $(AS) $(ASFLAGS) $< - -# Implicit rule for building a library file -%$L: ; $(LIB) $(LIBFLAGS) $@ $& - -# Implicit rule for building an executable file -%$E: ; $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_freebsd.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_freebsd.mk deleted file mode 100644 index 9b4d236..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_freebsd.mk +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files from source files -%$O: %.c ; $(CC) $(CFLAGS) -c $< -%$O: %$P ; $(CXX) $(CFLAGS) -c $< -%$O: %$A ; $(AS) -o $@ $(ASFLAGS) $< - -# Implicit rule for building a library file -%$L: ; $(LIB) $(LIBFLAGS) $@ $& - -# Implicit rule for building an executable file -%$E: ; $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_linux.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_linux.mk deleted file mode 100644 index 5f91fe5..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_linux.mk +++ /dev/null @@ -1,93 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -.IF $(USE_CXX_LINKER) -LD := $(LDXX) -.ENDIF - -# Implicit generation rules for making object files from source files -%$O: %.c ; -.IF $(SHOW_ARGS) - $(CC) -c $(CFLAGS) $< -.ELSE - @$(ECHO) $(CC) $(SHOW_CFLAGS) $< - @$(CC) -c $(CFLAGS) $< -.ENDIF - -%$O: %$P ; -.IF $(SHOW_ARGS) - $(CXX) -c $(CFLAGS) $< -.ELSE - @$(ECHO) $(CXX) $(SHOW_CFLAGS) $< - @$(CXX) -c $(CFLAGS) $< -.ENDIF - -%$O: %$A ; -.IF $(SHOW_ARGS) - $(AS) -o $@ $(ASFLAGS) $< -.ELSE - @$(ECHO) $(AS) $(SHOW_ASFLAGS) $< - @$(AS) @$(mktmp -o $@ $(ASFLAGS)) $< -.ENDIF - -# Implicit rule for building a library file -.IF $(BUILD_DLL) -%$L: ; -.IF $(SHOW_ARGS) - $(LIB) $(LIBFLAGS) -Wl,-soname,$@.$(VERSIONMAJ) -o $@ $& $(LIBS) -.ELSE - @$(ECHO) $(LIB) $@ - @$(LIB) $(LIBFLAGS) -Wl,-soname,$@.$(VERSIONMAJ) -o $@ $& $(LIBS) -.ENDIF -.ELSE -%$L: ; -.IF $(SHOW_ARGS) - $(LIB) $(LIBFLAGS) $@ $& -.ELSE - @$(ECHO) $(LIB) $@ - @$(LIB) $(LIBFLAGS) $@ $& -.ENDIF -.ENDIF - -# Implicit rule for building an executable file -%$E: ; -.IF $(SHOW_ARGS) - $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm -.ELSE - @$(ECHO) ld $@ - @$(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_win32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_win32.mk deleted file mode 100644 index 485d166..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_win32.mk +++ /dev/null @@ -1,90 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -.IF $(USE_CXX_LINKER) -LD := $(LDXX) -.ENDIF - -# Implicit generation rules for making object files from source files -%$O: %.c ; -.IF $(SHOW_ARGS) - $(CC) -c $(CFLAGS:s/\/\\) $(<:s,/,\) -.ELSE - @$(ECHO) $(CC) $(SHOW_CFLAGS:s/\/\\) $(<:s,/,\) - @$(CC) -c $(CFLAGS:s/\/\\) $(<:s,/,\) -.ENDIF - -%$O: %$P ; -.IF $(SHOW_ARGS) - $(CXX) -c $(CFLAGS:s/\/\\) $(<:s,/,\) -.ELSE - @$(ECHO) $(CXX) $(SHOW_CFLAGS:s/\/\\) $(<:s,/,\) - @$(CXX) -c $(CFLAGS:s/\/\\) $(<:s,/,\) -.ENDIF - -%$O: %$A ; -.IF $(SHOW_ARGS) - $(AS) -o $(ASFLAGS:s/\/\\) $(<:s,/,\) -.ELSE - @$(ECHO) $(AS) $(SHOW_ASFLAGS:s/\/\\) $(<:s,/,\) - @$(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ENDIF - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $< $(RCFLAGS) -o $@ - -# Implicit rule for building a DLL -# TODO! -#%$D: ; +rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) - -# Implicit rule for building a library file -%$L: ; -.IF $(SHOW_ARGS) - $(LIB) $(LIBFLAGS) $@ $& -.ELSE - @$(ECHO) $(LIB) $@ - @$(LIB) $(LIBFLAGS) $@ @$(mktmp $(&:s/\/\\)\n) -.ENDIF - -# Implicit rule for building an executable file -%$E: ; -.IF $(SHOW_ARGS) - $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm -.ELSE - @$(ECHO) ld $@ - @$(LD) $(LDFLAGS) -o $@ @$(mktmp $(&:s/\/\\) $(EXELIBS) $(PMLIB) -lm) -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/hc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/hc32.mk deleted file mode 100644 index 011e9ab..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/hc32.mk +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) $(CFLAGS) -c $< -%$O: %$P ; $(CC) $(CFLAGS) -c $< -.IF $(USE_NASM) -%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ELSE -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ENDIF - -# Implicit rule for building a library file using response file -%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp,$*.rsp -R $?) - -# Implicit rule for building an executable file using response file -%$E: ; $(LD) $(LDFLAGS) -o $@ @$(mktmp $(&:s/\/\\) $(PMLIB) $(EXELIBS) -ldosx32.lib) diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/qnx4.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/qnx4.mk deleted file mode 100644 index 55dc035..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/qnx4.mk +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Whether to link in real VBIOS library, or just the stub library - -.IF $(USE_BIOS) -VBIOSLIB := -lvbios.lib -.ELSE -VBIOSLIB := -lvbstubs.lib -.END - -# Require special privledges for Nucleus programs (requires root access) - -.IF $(USE_NUCLEUS) -LDFLAGS += -T1 -.ENDIF - -# Implicit generation rules for making object files from source files -%$O: %.c ; -.IF $(SHOW_ARGS) - $(CC) $(CFLAGS) $< -.ELSE - @echo $(CC) -c $< - +@$(CC) $(CFLAGS) $< > /dev/null -.ENDIF - -%$O: %$P ; -.IF $(SHOW_ARGS) - $(CXX) $(CFLAGS) $< -.ELSE - @echo $(CXX) -c $< - +@$(CXX) $(CFLAGS) $< > /dev/null -.ENDIF - -%$O: %$A ; -.IF $(SHOW_ARGS) - $(AS) -o $@ $(ASFLAGS) $< -.ELSE - @echo $(AS) $< - @$(AS) -o $@ $(ASFLAGS) $< -.ENDIF - -# Implicit rule for building a library file -%$L: ; -.IF $(SHOW_ARGS) - $(LIB) $(LIBFLAGS) -q $@ $& -.ELSE - @echo $(LIB) $@ - +@$(LIB) $(LIBFLAGS) -q $@ $& > /dev/null -.ENDIF - - -# Implicit rule for building an executable file -%$E: ; -.IF $(SHOW_ARGS) - $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) $(VBIOSLIB) -.ELSE - @echo wlink $@ - +@$(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) $(VBIOSLIB) > /dev/null -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/qnxnto.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/qnxnto.mk deleted file mode 100644 index c43ad1f..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/qnxnto.mk +++ /dev/null @@ -1,55 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Whether to link in real VBIOS library, or just the stub library - -.IF $(USE_BIOS) -VBIOSLIB := -lvbios -.ELSE -VBIOSLIB := -lvbstubs -.END - -# Implicit generation rules for making object files from source files -%$O: %.c ; $(CC) $(CFLAGS) -c $< -%$O: %$P ; $(CXX) $(CPPFLAGS) -c $< -%$O: %$A ; $(AS) -o $@ $(ASFLAGS) $< - -# Implicit rule for building a library file -%$L: ; $(LIB) $(LIBFLAGS) $@ $& - -# Implicit rule for building an executable file -%$E: ; $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) $(VBIOSLIB) diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk deleted file mode 100644 index b33bcd8..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk +++ /dev/null @@ -1,63 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) $(CFLAGS) -c $< -%$O: %$P ; $(CC) $(CFLAGS) -c $< -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\) - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building a DLL using a response file -%$D: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(EXELIBS)) - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? -.ELIF $(IMPORT_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? -.ELSE -%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+")\n) -.ENDIF - -# Implicit rule for building an executable file using response file -.IF $(USE_WIN16) -%$E: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(EXELIBS)) -.ELSE -%$E: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(PMLIB) $(EXELIBS)) -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk deleted file mode 100644 index 2231906..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk +++ /dev/null @@ -1,69 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) $(CFLAGS) -c $< -%$O: %$P ; $(CC) $(CFLAGS) -c $< -.IF $(USE_NASM) -%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ELSE -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ENDIF - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building a DLL using a response file -%$D: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(EXELIBS) kernel32.lib user32.lib gdi32.lib winmm.lib comdlg32.lib advapi32.lib) - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? -.ELIF $(IMPORT_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? -.ELSE -%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+")\n) -.ENDIF - -# Implicit rule for building an executable file using response file -.IF $(USE_TNT) -%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(PMLIB) $(EXELIBS)) -.ELIF $(USE_WIN32) -%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(EXELIBS) kernel32.lib user32.lib gdi32.lib winmm.lib comdlg32.lib advapi32.lib) -.ELSE -%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(PMLIB) $(EXELIBS)) -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk deleted file mode 100644 index 1a20319..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk +++ /dev/null @@ -1,82 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) -%$O: %$P ; $(CPP) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) -.IF $(USE_NASM) -%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ELSE -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ENDIF - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building help files -%.hlp: %.ipf; $(IPFC) $(IPFCFLAGS) $< - -# Implicit rule for building a DLL using a response file -.IF $(USE_OS2GUI) -%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) -.ELSE -%$D: ; $(LD) /nofree /nol @$(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) -.ENDIF - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? -.ELIF $(IMPORT_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? -.ELSE -%$L: ; $(LIB) $(LIBFLAGS) @$(mktmp $@-+$(?:t"&\n-+":s/\/\\);) -.ENDIF - -# Implicit rule for building an executable file using response file -.IF $(USE_OS2GUI) -%$E: ; - rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) -.IF $(LXLITE) - lxlite $@ -.ENDIF -.ELSE -%$E: ; - rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n\n) -.IF $(LXLITE) - lxlite $@ -.ENDIF -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk deleted file mode 100644 index 2b41801..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk +++ /dev/null @@ -1,79 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) -%$O: %$P ; $(CPP) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) -.IF $(USE_NASM) -%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ELSE -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ENDIF - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building a DLL using a response file -.IF $(USE_OS2GUI) -%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) -.ELSE -%$D: ; $(LD) /nofree /nol @$(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) -.ENDIF - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) /out:$@ $? -.ELIF $(IMPORT_DLL) -%$L: ; $(ILIB) $(ILIBFLAGS) /out:$@ $? -.ELSE -%$L: ; $(LIB) $(LIBFLAGS) /nowarn:86 /out:$@ @$(mktmp $(?:t"\n":s/\/\\)) -.ENDIF - -# Implicit rule for building an executable file using response file -.IF $(USE_OS2GUI) -%$E: ; - rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) -.IF $(LXLITE) - lxlite $@ -.ENDIF -.ELSE -%$E: ; - rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n\n) -.IF $(LXLITE) - lxlite $@ -.ENDIF -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk deleted file mode 100644 index 6ffc270..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk +++ /dev/null @@ -1,70 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) /nologo $(CFLAGS) /c $< -%$O: %$P ; $(CC) /nologo $(CFLAGS) /c $< -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\) - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building a DLL using a response file -%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) -e$@\n$(&:t"\n":s/\/\\)\n$(EXELIBS)) - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ $? -.ELIF $(IMPORT_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ $? -.ELSE -%$L: ; - @$(RM) $@ - $(LIB) $@ /nologo $(LIBFLAGS) @$(mktmp +$(&:t" &\n+") &\n,\n) -.ENDIF - -# Implicit rule for building an executable file using response file -.IF $(USE_WIN16) -%$E: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) -#%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) -.ELSE -%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(PMLIB) $(EXELIBS)) -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk deleted file mode 100644 index 97f1a0c..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk +++ /dev/null @@ -1,122 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Turn on pre-compiled headers as neccessary -.IF $(PRECOMP_HDR) - CFLAGS += -YX"$(PRECOMP_HDR)" -.ENDIF - -# Turn on runtime type information as necessary -.IF $(USE_RTTI) - CFLAGS += /GR -.ENDIF - -# Turn on C++ exception handling as necessary -.IF $(USE_CPPEXCEPT) - CFLAGS += /GX -.ENDIF - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) /nologo @$(mktmp $(CFLAGS:s/\/\\)) /c $(<:s,/,\) -%$O: %$P ; $(CC) /nologo @$(mktmp $(CFLAGS:s/\/\\)) /c $(<:s,/,\) -.IF $(USE_NASM) -%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ELSE -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ENDIF - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rules for building NT device drivers - -%.sys: ; - $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) -.IF $(DBG) -.IF $(USE_SOFTICE) - $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ -.ENDIF -.ENDIF - -# Implicit rule for building a DLL using a response file -.IF $(IMPORT_DLL) -.ELSE -.IF $(NO_RUNTIME) -%$D: ; $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) -.ELSE -%$D: ; - makedef -v $* - $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) -.IF $(DBG) -.IF $(USE_SOFTICE) - $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ -.ENDIF -.ENDIF -.ENDIF -.ENDIF - -# Implicit rule for building a library file using response file. Note that -# we use a special .VCD file that contains the EXPORT definitions for the -# Microsoft compiler, since the LIB utility automatically adds leading -# underscores to exported functions. -.IF $(IMPORT_DLL) -%$L: ; - makedef -v $(?:b) - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) /DEF:$(?:b).def /OUT:$@ -.ELSE -%$L: ; - @$(RM) $@ - $(LIB) $(LIBFLAGS) /out:$@ @$(mktmp $(&:t"\n")\n) -.ENDIF - -# Implicit rule for building an executable file using response file -.IF $(USE_WIN32) -%$E: ; - $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) -.IF $(DBG) -.IF $(USE_SOFTICE) - $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ -.ENDIF -.ENDIF -.ELSE -%$E: ; - @$(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) -.IF $(DOSSTYLE) - @markphar $@ -.ENDIF -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk deleted file mode 100644 index d1ca917..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk +++ /dev/null @@ -1,79 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Implicit generation rules for making object files -%$O: %.c ; $(CC) @$(mktmp $(CFLAGS)) $< -%$O: %$P ; $(CPP) @$(mktmp $(CFLAGS)) $< -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\) - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ +$? -.ELIF $(IMPORT_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ +$? -.ELSE -%$L: ; - @$(RM) $@ - $(LIB) $(LIBFLAGS) $@ @$(mktmp,$*.rsp +$(&:t"\n+":s/\/\\)\n) -.ENDIF - -# Implicit rule for building an executable file using response file -.IF $(USE_WIN16) -.IF $(BUILD_DLL) -%$E: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet SYS windows_dll\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk - rclink $(LD) $(RC) $@ $*.lnk - @$(RM) -S $(mktmp $*.lnk) -.ELSE -%$E: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet SYS windows\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk - rclink $(LD) $(RC) $@ $*.lnk - @$(RM) -S $(mktmp $*.lnk) -.ENDIF -.ELSE -%$E: ; - @trimlib $(mktmp OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB) $(EXELIBS:t",")) $*.lnk - $(LD) $(LDFLAGS) @$*.lnk - @$(RM) -S $(mktmp $*.lnk) -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk deleted file mode 100644 index 39b8819..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk +++ /dev/null @@ -1,264 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Rules makefile definitions, which define the rules used to -# build targets. We include them here at the end of the -# makefile so the generic project makefiles can override -# certain things with macros (such as linking C++ programs -# differently). -# -############################################################################# - -# Take out PMLIB if we don't need to link with it - -.IF $(NO_PMLIB) -PMLIB := -.ENDIF - -# Use a larger stack during linking if requested, or use a default stack -# of 200k. The usual default stack provided by Watcom C++ is *way* to small -# for real 32 bit code development. We also need a *huge* stack for OpenGL -# software rendering also! -.IF $(USE_QNX4) - # Not necessary for QNX code. -.ELSE -.IF $(STKSIZE) - LDFLAGS += OP STACK=$(STKSIZE) -.ELSE - LDFLAGS += OP STACK=204800 -.ENDIF -.ENDIF - -# Turn on runtime type information as necessary -.IF $(USE_RTTI) - CPFLAGS += -xr -.ENDIF - -# Optionally turn on pre-compiled headers -.IF $(PRECOMP_HDR) - CFLAGS += -fhq -.ENDIF - -.IF $(USE_QNX) -# Whether to link in real VBIOS library, or just the stub library -.IF $(USE_BIOS) -VBIOSLIB := vbios.lib, -.ELSE -VBIOSLIB := vbstubs.lib, -.END -# Require special privledges for Nucleus programs (requires root access) -.IF $(USE_NUCLEUS) -LDFLAGS += OP PRIV=1 -.ENDIF -.ENDIF - -# Implicit generation rules for making object files -.IF $(WC_LIBBASE) == WC10A -%$O: %.c ; $(CC) $(CFLAGS) $(<:s,/,\) -%$O: %$P ; $(CPP) $(CFLAGS) $(<:s,/,\) -.ELSE -%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) -%$O: %$P ; $(CPP) @$(mktmp $(CPFLAGS:s/\/\\) $(CFLAGS:s/\/\\)) $(<:s,/,\) -.ENDIF -.IF $(USE_NASM) -%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ELSE -%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) -.ENDIF - -# Implit rule to compile .S assembler files. The first version -# uses GAS directly and the second uses a pre-processor to -# produce NASM code. - -.IF $(USE_GAS) -.IF $(WC_LIBBASE) == WC11 -%$O: %$S ; $(GAS) -c @$(mktmp $(GAS_FLAGS:s/\/\\)) $(<:s,/,\) -.ELSE -# Black magic to build asm sources with Watcom 10.6 (requires sed) -%$O: %$S ; - $(GAS) -c @$(mktmp $(GAS_FLAGS:s/\/\\)) $(<:s,/,\) - wdisasm \\ -a $(*:s,/,\).o > $(*:s,/,\).lst - sed -e "s/\.text/_TEXT/; s/\.data/_DATA/; s/\.bss/_BSS/; s/\.386/\.586/; s/lar *ecx,cx/lar ecx,ecx/" $(*:s,/,\).lst > $(*:s,/,\).asm - wasm \\ $(WFLAGS) -zq -fr=nul -fp3 -fo=$@ $(*:s,/,\).asm - $(RM) -S $(mktmp $(*:s,/,\).o) - $(RM) -S $(mktmp $(*:s,/,\).lst) - $(RM) -S $(mktmp $(*:s,/,\).asm) -.ENDIF -.ELSE -%$O: %$S ; - @gcpp -DNASM_ASSEMBLER -D__WATCOMC__ -EP $(<:s,/,\) > $(*:s,/,\).asm - nasm @$(mktmp -f obj -o $@) $(*:s,/,\).asm - @$(RM) -S $(mktmp $(*:s,/,\).asm) -.ENDIF - -# Special target to build dllstart.asm using Borland TASM -dllstart.obj: dllstart.asm - $(DLL_TASM) @$(mktmp /t /mx /m /D__FLAT__ /i$(SCITECH)\INCLUDE /q) $(PRIVATE)\src\common\dllstart.asm - -# Implicit rule for building resource files -%$R: %.rc ; $(RC) $(RCFLAGS) -r $< - -# Implicit rule for building a DLL using a response file -.IF $(IMPORT_DLL) -.ELSE -.IF $(USE_OS232) -%$D: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2 dll\nN $@\nF $(&:t",\n":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk - rclink $(LD) $(RC) $@ $*.lnk -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.ELIF $(USE_WIN32) -%$D: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt_dll\nN $@\nF $(&:t",\n":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk - rclink $(LD) $(RC) $@ $*.lnk -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.ELSE -%$D: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet SYS win386\nN $*.rex\nF $(&:t",\n":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk - rclink $(LD) $(RC) $@ $*.lnk - wbind $* -d -q -n -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.ENDIF -.ENDIF - -# Implicit rule for building a library file using response file -.IF $(BUILD_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ +$? -.ELIF $(IMPORT_DLL) -%$L: ; - @$(RM) $@ - $(ILIB) $(ILIBFLAGS) $@ +$? -.ELSE -%$L: ; - @$(RM) $@ - $(LIB) $(LIBFLAGS) $@ @$(mktmp,$*.rsp +$(&:t"\n+":s/\/\\)\n) -.ENDIF - -# Implicit rule for building an executable file using response file -.IF $(USE_X32) -%$E: ; - @trimlib $(mktmp OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk - $(LD) $(LDFLAGS) @$*.lnk - x32fix $@ -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.ELIF $(USE_OS232) -.IF $(USE_OS2GUI) -%$E: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2_pm\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk - rclink $(LD) $(RC) $@ $*.lnk -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.IF $(LXLITE) - lxlite $@ -.ENDIF -.ELSE -%$E: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk - rclink $(LD) $(RC) $@ $*.lnk -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.IF $(LXLITE) - lxlite $@ -.ENDIF -.ENDIF -.ELIF $(USE_SNAP) -%$E: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(DEFLIBS)$(EXELIBS:t",")) $*.lnk - rclink $(LD) $(RC) $@ $*.lnk -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.ELIF $(USE_WIN32) -.IF $(WIN32_GUI) -%$E: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet SYS win95\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk - rclink $(LD) $(RC) $@ $*.lnk -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.ELSE -%$E: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk - rclink $(LD) $(RC) $@ $*.lnk -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.ENDIF -.ELIF $(USE_WIN386) -%$E: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet SYS win386\nN $*.rex\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk - rclink $(LD) wbind $*.rex $*.lnk -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.ELIF $(USE_TNT) -%$E: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR dosx32.lib,tntapi.lib,$(PMLIB)$(EXELIBS:t",")) $*.lnk - $(LD) @$*.lnk -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.IF $(DOSSTYLE) - @markphar $@ -.ENDIF -.ELIF $(USE_QNX4) -%$E: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(VBIOSLIB)$(EXELIBS:t",")) $*.lnk - @+if exist $*.exe attrib -s $*.exe > NUL - $(LD) @$*.lnk - @attrib +s $*.exe -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.ELSE -%$E: ; - @trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk - $(LD) @$*.lnk -.IF $(LEAVE_LINKFILE) -.ELSE - @$(RM) -S $(mktmp *.lnk) -.ENDIF -.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/sc16.mk b/board/MAI/bios_emulator/scitech/makedefs/sc16.mk deleted file mode 100644 index 099ad45..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/sc16.mk +++ /dev/null @@ -1,128 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Symantec C++ 6.x/7.x 16 bit version. Supports 16 bit DOS -# and 16 bit Windows development. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : SC_LIBBASE - -# Default commands for compiling, assembling linking and archiving - CC := sc # C-compiler and flags - CFLAGS := -ml -Jm -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx # Assembler and flags -.ELSE - AS := tasm # Assembler and flags -.ENDIF - ASFLAGS := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE - LD := sc # Loader and flags - LDFLAGS = $(CFLAGS) - RC := rcc # WIndows resource compiler - RCFLAGS := # Mark as Win32 compatible resources - LIB := lib # Librarian - LIBFLAGS := /N /B - ILIB := implib # Import librarian - ILIBFLAGS := - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -g # Turn on debugging for C compiler -.ELSE - ASFLAGS += /q # Suppress object records not needed for linking -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += -5 -o+all -.ELIF $(OPT_SIZE) - CFLAGS += -5 -o+space -.END - -# Optionally turn on direct i387 FPU instructions - -.IF $(FPU) - CFLAGS += -ff -DFPU387 - ASFLAGS += -DFPU387 -DFPU_REG_RTN -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -DBETA -.END - -# User a larger stack if requested - -.IF $(STKSIZE) - LDFLAGS += =$(STKSIZE) -.ENDIF - -# Optionally compile for 16 bit Windows -.IF $(USE_WIN16) -.IF $(BUILD_DLL) - CFLAGS += -WD -DBUILD_DLL - ASFLAGS += -DBUILD_DLL -.ELSE - CFLAGS += -WA -.ENDIF - DX_ASFLAGS += -D__WINDOWS16__ - LIB_OS = WIN16 -.ELSE - USE_REALDOS := 1 - LIB_OS = DOS16 -.END - -# Place to look for PMODE library files - -PMLIB := pm.lib - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(SC_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Define which file contains our rules - - RULES_MAK := sc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/sc32.mk b/board/MAI/bios_emulator/scitech/makedefs/sc32.mk deleted file mode 100644 index 9ca7570..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/sc32.mk +++ /dev/null @@ -1,178 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Symantec C++ 6.x/7.x 32 bit version. Supports the DOSX -# extender, FlashTek X32 and Phar Lap's TNT DOS Extender -# and 32 bit Windows development. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : USE_TNT USE_X32 USE_X32VM SC_LIBBASE - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# Default commands for compiling, assembling linking and archiving - CC := sc # C-compiler and flags - CFLAGS := -Jm -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx # Assembler and flags -.ELSE - AS := tasm # Assembler and flags -.ENDIF -.IF $(USE_WIN32) - ASFLAGS := /t /mx /m /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE -.ELSE - ASFLAGS := /t /mx /m /DES_NOT_DS /D__COMM__ /i$(SCITECH)\INCLUDE -.ENDIF - LD := sc # Loader and flags - LD_FLAGS = - RC := rcc # WIndows resource compiler - RCFLAGS := -32 # Mark as Win32 compatible resources - LIB := lib # Librarian - LIBFLAGS := /N /B - ILIB := implib # Import librarian - ILIBFLAGS := - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -g # Turn on debugging for C compiler (FlashView) -.IF $(USE_TNT) - LDFLAGS += -fullsym # Turn on debugging for TNT 386link linker -.END -.IF $(USE_X32) or $(USE_X32VM) - LDFLAGS += -L/map # Turn on debugging for FlashView debugger -.END -.ELSE - ASFLAGS += /q # Suppress object records not needed for linking -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += -5 -o+all -.ELIF $(OPT_SIZE) - CFLAGS += -5 -o+space -.END - -# Optionally turn on direct i387 FPU instructions - -.IF $(FPU) - CFLAGS += -ff -DFPU387 - ASFLAGS += -DFPU387 -DFPU_REG_RTN -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -DBETA -.END - -# User a larger stack if requested - -.IF $(STKSIZE) - LDFLAGS += =$(STKSIZE) -.ENDIF - -.IF $(USE_TNT) # Use Phar Lap's TNT DOS Extender - CFLAGS += -mp - DX_CFLAGS += -DTNT - ASFLAGS += /D__FLAT__ - DX_ASFLAGS += -DTNT - LD := 386link - LDFLAGS += @sc32.dos -exe $@ - LIB_OS = DOS32 -.ELIF $(USE_X32VM) # Use FlashTek X-32VM DOS extender - CFLAGS += -mx - DX_CFLAGS += -DX32VM - ASFLAGS += /D__X386__ - DX_ASFLAGS += -DX32VM - LD := sc - LDFLAGS += $(CFLAGS) x32v.lib - LIB_OS = DOS32 -.ELIF $(USE_X32) # Use FlashTek X-32 DOS extender - CFLAGS += -mx - DX_CFLAGS += -DX32VM - ASFLAGS += /D__X386__ - DX_ASFLAGS += -DX32VM - LD := sc - LDFLAGS += $(CFLAGS) x32.lib - LIB_OS = DOS32 -.ELIF $(USE_WIN32) # Build 32 bit Windows NT app -.IF $(BUILD_DLL) - CFLAGS += -WD -mn - ASFLAGS += -DBUILD_DLL -.ELSE - CFLAGS += -WA -mn -.ENDIF - DX_ASFLAGS += -D__WINDOWS32__ - LIB_OS = WIN32 -.ELSE # Use default Symantec DOSX extender - USE_DOSX := 1 - USE_REALDOS := 1 - CFLAGS += -mx - DX_CFLAGS += -DDOSX - ASFLAGS += /D__X386__ - DX_ASFLAGS += -DDOSX - LD := sc - LDFLAGS += $(CFLAGS) - LIB_OS = DOS32 -.END - -# Place to look for PMODE library files - -.IF $(USE_TNT) -PMLIB := tnt\pm.lib -.ELIF $(USE_X32) -PMLIB := x32\pm.lib -.ELSE -PMLIB := dosx\pm.lib -.END - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(SC_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Define which file contains our rules - - RULES_MAK := sc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/startup.mk b/board/MAI/bios_emulator/scitech/makedefs/startup.mk deleted file mode 100644 index d8b2ba2..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/startup.mk +++ /dev/null @@ -1,161 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Common startup script that defines all variables common to -# all startup scripts. These define the DMAKE runtime -# environment and the values are dependant on the version of -# DMAKE in use. -# -############################################################################# - -# Disable warnings for macros redefined here that were given -# on the command line. -__.SILENT := $(.SILENT) -.SILENT := yes - -# Import enivornment variables that we use common to all compilers -.IMPORT .IGNORE : TEMP SHELL COMSPEC INCLUDE LIB SCITECH PRIVATE SCITECH_LIB -.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA USE_WIN32 FPU BUILD_DLL BUILD_FOR_DLL -.IMPORT .IGNORE : IMPORT_DLL USE_TASMX WIN32_GUI USE_WIN16 USE_NASM CHECKED -.IMPORT .IGNORE : OS2_SHELL SOFTICE_PATH MAX_WARN USE_SOFTICE USE_TASM32 -.IMPORT .IGNORE : DLL_START_TASM USE_SNAP USE_X11 USE_LINUX STATIC_LIBS LIBC -.IMPORT .IGNORE : SHOW_ARGS BOOT_STRAP_DMAKE - TMPDIR := $(TEMP) - -# Determine if the host machine is a Windows/DOS or Unix box -.IF $(COMSPEC) - WIN32_HOST := 1 -.ELSE - USE_NASM := 1 - UNIX_HOST := 1 -.ENDIF - -# Setup to either user NASM or TASM as the assembler -.IF $(USE_NASM) -.ELSE - USE_TASM := 1 -.ENDIF - -.IF $(UNIX_HOST) -# Standard file suffix definitions -# -# NOTE: Linux/Unix does not require any extenion for executeable files, but you -# can use an extension if you wish. We use the .exe extension for building -# executeable files so that we can use implicit rules to make the -# makefiles simpler and more portable between systems (exe also makes it -# easier for cross-compile/debugging situations). When you install -# the files to a local bin directory, you will probably want to remove -# the .exe extension. - L := .a # Libraries - E := .exe # Executables for glibc - O := .o # Objects - A := .asm # Assembler sources - S := .s # GNU assembler sources - P := .cpp # C++ sources - -# File prefix/suffix definitions. The following prefixes are defined, and are -# used primarily to abstract between the Unix style libXX.a naming convention -# and the DOS/Windows/OS2 naming convention of XX.lib. - LP := lib # LP - Library file prefix (name of file on disk) - LL := -l # Library link prefix (name of library on link command line) - LE := # Library link suffix (extension of library on link command line) - -# We use the Unix shell at all times - SHELL := /bin/sh - SHELLFLAGS := -c - -.ELSE -# Standard file DOS/Win/OS2 suffix definitions - L := .lib # Libraries -.IF $(USE_SNAP) - E := .sxe # Snap Executables - D := .sll # Snap Dynamic Link Library file -.ELSE - E := .exe # Executables - D := .dll # Dynamic Link Library file -.ENDIF - O := .obj # Objects - A := .asm # Assembler sources - P := .cpp # C++ sources - R := .res # Compiled resource file - S := .s # Assyntax.h style assembler - -# File prefix/suffix definitions. The following prefixes are defined, and are -# used primarily to abstract between the Unix style libXX.a naming convention -# and the DOS/Windows/OS2 naming convention of XX.lib. - LP := # LP - Library file prefix (name of file on disk) - LL := # Library link prefix (name of library on link command line) - LE := .lib # Library link suffix (extension of library on link command line) - -# We use the DOS/Win/OS2 style shell at all times - SHELL := $(COMSPEC) - GROUPSHELL := $(SHELL) - SHELLFLAGS := $(SWITCHAR)c - GROUPFLAGS := $(SHELLFLAGS) - SHELLMETAS := *"?<> -.IF $(OS2_SHELL) - GROUPSUFFIX := .cmd -.ELSE - GROUPSUFFIX := .bat -.ENDIF - DIRSEPSTR := \\ - DIVFILE = $(TMPFILE:s,/,\) - -.ENDIF - -# Standard Unix style shell commands. Since these do not exist on -# regular DOS/Win/OS2 installations we use our own '' versions -# instead. To boostrtap a new OS you may wish to use the regular -# unix versions. - -.IF $(BOOT_STRAP_DMAKE) - CP := cp - MD := mkdir - RM := rm - ECHO := echo -.ELSE - CP := k_cp - MD := k_md - RM := k_rm - ECHO := k_echo -.ENDIF - -# Definition of $(MAKE) macro for recursive makes. - MAKE = $(MAKECMD) $(MFLAGS) - -# Macro to install a library file - INSTALL := $(CP) - -# DMAKE uses this recipe to remove intermediate targets -.REMOVE :; $(RM) -f $< - -# Turn warnings back to previous setting. -.SILENT := $(__.SILENT) - -# We dont use TABS in our makefiles -.NOTABS := yes diff --git a/board/MAI/bios_emulator/scitech/makedefs/va32.mk b/board/MAI/bios_emulator/scitech/makedefs/va32.mk deleted file mode 100644 index fbca523..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/va32.mk +++ /dev/null @@ -1,163 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# IBM VisualAge C++ 3.0 OS/2 32-bit version. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : VA_LIBBASE USE_OS232 USE_OS2GUI FULLSCREEN NOOPT MAX_WARN - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# Default commands for compiling, assembling linking and archiving - CC := icc - CPP := icc - CFLAGS := /Q /G5 /Gl+ /Fi /Si /J- /Ss+ /Sp1 /Gm+ /I. -.IF $(USE_NASM) - AS := nasm - ASFLAGS := -t -f obj -F null -d__FLAT__ -dSTDCALL_MANGLE -d__NOU_VAR__ -iINCLUDE -i$(SCITECH)\INCLUDE -.ELSE -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx -.ELSE - AS := tasm -.ENDIF - ASFLAGS := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE -.ENDIF - LD := ilink - LDFLAGS = /noi /exepack:2 /packcode /packdata /align:32 /map /noe - RC := rc - RCFLAGS := -n -x2 - LIB := ilib - LIBFLAGS := /nologo - ILIB := implib - ILIBFLAGS := /nologo - IPFC := ipfc - IPFCFLAGS := - IBMCOBJ := 1 - -# Set the compiler warning level -.IF $(MAX_WARN) - CFLAGS += /W3 -.ELSE - CFLAGS += /W1 -.ENDIF - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += /Ti - LDFLAGS += /DE -.ELSE -.IF $(USE_TASM) - ASFLAGS += /q -.ENDIF -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += /Gfi /O /Oi -.ELIF $(OPT_SIZE) - CFLAGS += /Gfi /O /Oc -.ELIF $(NOOPT) - CFLAGS += /O- -.END - -# Optionally turn on direct i387 FPU instructions optimised for Pentium -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -dBETA -.END - -# Build 32-bit OS/2 apps -.IF $(BUILD_DLL) - CFLAGS += /Ge- /DBUILD_DLL - LDFLAGS += /DLL /NOE - ASFLAGS += -dBUILD_DLL -.ELSE -.IF $(USE_OS2GUI) - CFLAGS += -D__OS2_PM__ - LDFLAGS += /PMTYPE:PM -.ELSE -.IF $(FULLSCREEN) - LDFLAGS += /PMTYPE:NOVIO -.ELSE - LDFLAGS += /PMTYPE:VIO -.ENDIF -.ENDIF -.ENDIF - DX_ASFLAGS += -d__OS2__ - LIB_OS = os232 - -# Place to look for PMODE library files - -.IF $(USE_OS2GUI) -.IF $(USE_SDDPMDLL) -#Note: This is OK for now but might need to be changed if the GUI PM library -# were really different -PMLIB := sddpmlib.lib -.ELSE -PMLIB := pm_pm.lib -.ENDIF -.ELSE -.IF $(USE_SDDPMDLL) -PMLIB := sddpmlib.lib -.ELSE -PMLIB := pm.lib -.ENDIF -.ENDIF - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += /DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VA_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Define which file contains our rules - - RULES_MAK := va32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/va365.mk b/board/MAI/bios_emulator/scitech/makedefs/va365.mk deleted file mode 100644 index 3a2eccb..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/va365.mk +++ /dev/null @@ -1,151 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# IBM VisualAge C++ 3.65 OS/2 32-bit version. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : VA_LIBBASE USE_OS232 USE_OS2GUI FULLSCREEN NOOPT MAX_WARN - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# Default commands for compiling, assembling linking and archiving - CC := icc - CPP := icc - CFLAGS := /Q /G5l /Fi /Si /J- /Ss+ /Sp1 /Gm+ /I. -.IF $(USE_NASM) - AS := nasm - ASFLAGS := -t -f obj -F null -d__FLAT__ -dSTDCALL_MANGLE -d__NOU_VAR__ -iINCLUDE -i$(SCITECH)\INCLUDE -.ELSE -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx -.ELSE - AS := tasm -.ENDIF - ASFLAGS := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE -.ENDIF - LD := ilink - LDFLAGS = /noi /exepack /packcode /packdata /align:32 /map /noe - RC := rc - RCFLAGS := /nologo - LIB := ilib - LIBFLAGS := /nologo - ILIB := implib - ILIBFLAGS := /nologo - IBMCOBJ := 1 - -# Set the compiler warning level -.IF $(MAX_WARN) - CFLAGS += /W3 -.ELSE - CFLAGS += /W1 -.ENDIF - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += /Ti - LDFLAGS += /DE -.ELSE -.IF $(USE_TASM) - ASFLAGS += /q -.ENDIF -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += /Gfi /O /Oi -.ELIF $(OPT_SIZE) - CFLAGS += /Gfi /O /Oc -.ELIF $(NOOPT) - CFLAGS += /O- -.END - -# Optionally turn on direct i387 FPU instructions optimised for Pentium -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -dBETA -.END - -# Build 32-bit OS/2 apps -.IF $(BUILD_DLL) - CFLAGS += /Gme- /DBUILD_DLL - LDFLAGS += /DLL /NOE - ASFLAGS += -dBUILD_DLL -.ELSE -.IF $(USE_OS2GUI) - CFLAGS += -D__OS2_PM__ - LDFLAGS += /PMTYPE:PM -.ELSE -.IF $(FULLSCREEN) - LDFLAGS += /PMTYPE:NOVIO -.ELSE - LDFLAGS += /PMTYPE:VIO -.ENDIF -.ENDIF -.ENDIF - DX_ASFLAGS += -d__OS2__ - LIB_OS = os232 - -# Place to look for PMODE library files - -.IF $(USE_OS2GUI) -PMLIB := pm_pm.lib -.ELSE -PMLIB := pm.lib -.ENDIF - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += /DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VA_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Define which file contains our rules - - RULES_MAK := va365.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/vc16.mk b/board/MAI/bios_emulator/scitech/makedefs/vc16.mk deleted file mode 100644 index 913bf9c..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/vc16.mk +++ /dev/null @@ -1,128 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Microsoft Visual C++ 1.x 16 bit version. Supports 16 bit -# DOS and Windows development. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : VC_LIBBASE - -# Default commands for compiling, assembling linking and archiving - CC := cl # C-compiler and flags - CFLAGS := /YX /w /G3 /Gs -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx # Assembler and flags -.ELSE - AS := tasm # Assembler and flags -.ENDIF - ASFLAGS := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE - LD := cl # Loader and flags - LDFLAGS = $(CFLAGS) - RC := rc # WIndows resource compiler - RCFLAGS := - LIB := lib # Librarian - LIBFLAGS := /NOI /NOE - ILIB := implib # Import librarian - ILIBFLAGS := /noignorecase - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += /Yd /Zi # Turn on debugging for C compiler - ASFLAGS += /zi # Turn on debugging for assembler -.ELSE - ASFLAGS += /q # Suppress object records not needed for linking -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += /Ox -.END - -# Optionally turn on direct i387 FPU instructions - -.IF $(FPU) - CFLAGS += /FPi87 /DFPU387 - ASFLAGS += /DFPU387 /DFPU_REG_RTN -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += /DBETA - ASFLAGS += /DBETA -.END - -# Use a larger stack during linking if requested ???? How the fuck do you -# specify linker options on the CL command line????? - -.IF $(STKSIZE) -.ENDIF - -# Optionally compile for 16 bit Windows -.IF $(USE_WIN16) -.IF $(BUILD_DLL) - CFLAGS += /GD /Alfw /DBUILD_DLL - ASFLAGS += -DBUILD_DLL -.ELSE - CFLAGS += /GA /AL -.ENDIF - DX_ASFLAGS += -D__WINDOWS16__ - LIB_OS = WIN16 -.ELSE - USE_REALDOS := 1 - CFLAGS += /AL - LIB_OS = DOS16 -.END - -# Place to look for PMODE library files - -PMLIB := pm.lib - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Define which file contains our rules - - RULES_MAK := vc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/vc32.mk b/board/MAI/bios_emulator/scitech/makedefs/vc32.mk deleted file mode 100644 index 11c9071..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/vc32.mk +++ /dev/null @@ -1,226 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Microsoft Visual C++ 2.x 32 bit version. Supports Phar Lap -# TNT DOS Extender and 32 bit Windows development. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : TNT_PATH VC_LIBBASE DOSSTYLE USE_TNT USE_RTTARGET MSVCDIR -.IMPORT .IGNORE : USE_VXD USE_NTDRV USE_W2KDRV NT_DDKROOT USE_RTTI USE_CPPEXCEPT - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# Default commands for compiling, assembling linking and archiving - CC := cl # C-compiler and flags - CFLAGS := -.IF $(USE_NASM) - AS := nasm - ASFLAGS := -t -f win32 -F null -d__FLAT__ -dSTDCALL_MANGLE -iINCLUDE -i$(SCITECH)\INCLUDE -.ELSE -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx # Assembler and flags -.ELSE - AS := tasm # Assembler and flags -.ENDIF - ASFLAGS := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /iINCLUDE /i$(SCITECH)\INCLUDE -.ENDIF - LD := cl -.IF $(USE_WIN32) - LDFLAGS = $(CFLAGS) -.IF $(USE_NTDRV) - LDENDFLAGS = -link /INCREMENTAL:NO /DRIVER /SUBSYSTEM:NATIVE,4.00 /VERSION:4.00 /MACHINE:I386 /NODEFAULTLIB /DEBUGTYPE:CV /PDB:NONE /ALIGN:0x20 /BASE:0x10000 /ENTRY:DriverEntry@8 - #/MERGE:_page=page /MERGE:_text=.text /MERGE:.rdata=.text -.ELIF $(WIN32_GUI) - LDENDFLAGS = -link /INCREMENTAL:NO /DEF:$(@:b).def /SUBSYSTEM:WINDOWS /MACHINE:I386 /DEBUGTYPE:CV /PDB:NONE -.ELSE - LDENDFLAGS = -link /INCREMENTAL:NO /SUBSYSTEM:CONSOLE /MACHINE:I386 /DEBUGTYPE:CV /PDB:NONE -.ENDIF -.ELSE - LDFLAGS = $(CFLAGS) - LDENDFLAGS := -link -stub:$(TNT_PATH:s/\/\\)\\bin\\gotnt.exe /PDB:NONE -.ENDIF - RC := rc # Watcom resource compiler - RCFLAGS := # Mark as Win32 compatible resources - LIB := lib # Librarian - LIBFLAGS := - ILIB := lib # Import librarian - ILIBFLAGS := /MACHINE:IX86 - INTEL_X86 := 1 - NMSYM := $(SOFTICE_PATH)\nmsym.exe -.IF $(USE_NTDRV) - NMSYMFLAGS := /TRANSLATE:source,package,always /PROMPT /SOURCE:$(MSVCDIR)\crt\src\intel;$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\ntdrv -.ELSE - NMSYMFLAGS := /TRANSLATE:source,package,always /PROMPT /SOURCE:$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\win32 -.ENDIF - -# Set the compiler warning level -.IF $(MAX_WARN) - CFLAGS += -W3 -.ELSE - CFLAGS += -W1 -.ENDIF - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += /Yd /Zi # Turn on debugging for C compiler -.IF $(USE_TASM) - ASFLAGS += /zi # Turn on debugging for assembler -.ENDIF -.ELSE -.IF $(USE_TASM) - ASFLAGS += /q # Suppress object records not needed for linking -.ENDIF -.END - -# Optionally turn on optimisations -.IF $(VC_LIBBASE) == vc5 -.IF $(OPT) - CFLAGS += /G6 /O2 /Ox /Oi- -.ELIF $(OPT_SIZE) - CFLAGS += /G6 /O1 -.END -.ELSE -.IF $(OPT) - CFLAGS += /G5 /O2 /Ox -.ELIF $(OPT_SIZE) - CFLAGS += /G5 /O1 -.END -.ENDIF - -# Optionally turn on direct i387 FPU instructions - -.IF $(FPU) - CFLAGS += /DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += /DBETA - ASFLAGS += -dBETA -.END - -# Use a larger stack during linking if requested, or use a default stack -# of 50k. The usual default stack provided by Visual C++ is *way* to small -# for real 32 bit code development. - -.IF $(USE_WIN32) - # Not necessary for Win32 code. -.ELSE -.IF $(STKSIZE) - LDENDFLAGS += /STACK:$(STKSIZE) -.ELSE - LDENDFLAGS += /STACK:51200 -.ENDIF -.ENDIF - -# DOS extender dependant flags -.IF $(USE_NTDRV) # Build 32 bit Windows NT driver - CFLAGS += /LD /Zl /Gy /Gz /GF /D__NT_DRIVER__ /D_X86_=1 /Di386=1 -.IF $(DBG) - CFLAGS += /QIf -.ENDIF - ASFLAGS += - DEF_LIBS := int64.lib ntoskrnl.lib hal.lib - DX_ASFLAGS += -d__NT_DRIVER__ -.IF $(USE_W2KDRV) # Build 32 bit Windows 2000 driver - LIB_OS = W2KDRV -.ELSE - LIB_OS = NTDRV -.ENDIF -.ELIF $(USE_WIN32) # Build 32 bit Windows NT app -.IF $(WIN32_GUI) -.ELSE - CFLAGS += -D__CONSOLE__ -.ENDIF -.IF $(BUILD_DLL) - CFLAGS += /MT /LD /DBUILD_DLL - ASFLAGS += -dBUILD_DLL -.IF $(NO_RUNTIME) - LDENDFLAGS += /NODEFAULTLIB - CFLAGS += /Zl - DEF_LIBS := -.ELSE - DEF_LIBS := kernel32.lib user32.lib gdi32.lib advapi32.lib shell32.lib winmm.lib comdlg32.lib comctl32.lib ole32.lib oleaut32.lib version.lib winspool.lib uuid.lib odbc32.lib odbccp32.lib wsock32.lib rpcrt4.lib -.ENDIF -.ELSE - CFLAGS += /MT - DEF_LIBS := kernel32.lib user32.lib gdi32.lib advapi32.lib shell32.lib winmm.lib comdlg32.lib comctl32.lib ole32.lib oleaut32.lib version.lib winspool.lib uuid.lib odbc32.lib odbccp32.lib wsock32.lib rpcrt4.lib -.ENDIF - DX_ASFLAGS += -d__WINDOWS32__ - LIB_OS = WIN32 -.ELIF $(USE_RTTARGET) - CFLAGS += -D__RTTARGET__ - DX_CFLAGS += - DX_ASFLAGS += -d__RTTARGET__ - USE_REALDOS := - LIB_OS = RTT32 - DEF_LIBS := cw32mt.lib -.ELSE - USE_TNT := 1 - USE_REALDOS := 1 - CFLAGS += /MT /D__MSDOS32__ - DX_CFLAGS += -DTNT - DX_ASFLAGS += -dTNT - LIB_OS = DOS32 - DEF_LIBS := dosx32.lib tntapi.lib -.ENDIF - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += /DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Place to look for PMODE library files - -.IF $(USE_TNT) -PMLIB := $(LIB_BASE:s/\/\\)\\tnt\\pm.lib -.ELSE -PMLIB := $(LIB_BASE:s/\/\\)\\pm.lib -.ENDIF - -# Define which file contains our rules - - RULES_MAK := vc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/wc16.mk b/board/MAI/bios_emulator/scitech/makedefs/wc16.mk deleted file mode 100644 index e316f4c..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/wc16.mk +++ /dev/null @@ -1,141 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Watcom C++ 10.x 16 bit version. Supports 16-bit DOS, -# 16-bit Windows development and 16-bit OS/2 development. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : WC_LIBBASE USE_WIN16 USE_OS216 USE_OS2GUI - -# Default commands for compiling, assembling linking and archiving - CC := wcc # C-compiler and flags - CPP := wpp # C++-compiler and flags - CFLAGS := -ml-zq-j-w2-s-fh -fhq -.IF $(USE_TASM32) - AS := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx # Assembler and flags -.ELSE - AS := tasm # Assembler and flags -.ENDIF - AS := tasm # Assembler and flags - ASFLAGS := /t /mx /m /D__LARGE__ /iINCLUDE /i$(SCITECH)\INCLUDE - LD := wlink # Loader and flags - LDFLAGS = - RC := wrc # Watcom resource compiler - RCFLAGS := /bt=windows - LIB := wlib # Librarian - LIBFLAGS := -q - ILIB := wlib # Import librarian - ILIBFLAGS := -c - -# Optionally turn on debugging information -.IF $(DBG) - CFLAGS += -d2 # Turn on debugging for C compiler - LIBFLAGS += -p=128 # Larger page size for libraries with debug info! - ASFLAGS += /zi # Turn on debugging for assembler - LDFLAGS += D A # Turn on debugging for linker -.ELSE - ASFLAGS += /q # Suppress object records not needed for linking -.END - -# Optionally turn on optimisations -.IF $(OPT) - CFLAGS += -onatx-5 -.ELIF $(OPT_SIZE) - CFLAGS += -onaslmr-5 -.END - -# Optionally turn on direct i387 FPU instructions optimised for Pentium - -.IF $(FPU) - CFLAGS += -fpi87-fp5-DFPU387 - ASFLAGS += -DFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -DBETA -.END - -# Use a larger stack during linking if requested - -.IF $(STKSIZE) - LDFLAGS += OP STACK=$(STKSIZE) -.ENDIF - -.IF $(USE_OS216) -.IF $(BUILD_DLL) - CFLAGS += -bd-bt=os2-DBUILD_DLL - ASFLAGS += -DBUILD_DLL -.ELSE - CFLAGS += -bt=os2 -.ENDIF - DX_ASFLAGS += -D__OS216__ - LIB_OS = os216 -.ELIF $(USE_WIN16) -.IF $(BUILD_DLL) - CFLAGS += -bd-bt=windows-D_WINDOWS-DBUILD_DLL - ASFLAGS += -DBUILD_DLL -.ELSE - CFLAGS += -bt=windows-D_WINDOWS -.ENDIF - DX_ASFLAGS += -D__WINDOWS16__ - LIB_OS = WIN16 -.ELSE - USE_REALDOS := 1 - LIB_OS = DOS16 -.END - -# Place to look for PMODE library files - -PMLIB := pm.lib, - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(WC_LIBBASE) - LIB_DEST := $(LIB_BASE) - -# Define which file contains our rules - - RULES_MAK := wc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/wc32.mk b/board/MAI/bios_emulator/scitech/makedefs/wc32.mk deleted file mode 100644 index e5175ca..0000000 --- a/board/MAI/bios_emulator/scitech/makedefs/wc32.mk +++ /dev/null @@ -1,353 +0,0 @@ -############################################################################# -# -# SciTech Multi-platform Graphics Library -# -# ======================================================================== -# -# The contents of this file are subject to the SciTech MGL Public -# License Version 1.0 (the "License"); you may not use this file -# except in compliance with the License. You may obtain a copy of -# the License at http://www.scitechsoft.com/mgl-license.txt -# -# Software distributed under the License is distributed on an -# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -# implied. See the License for the specific language governing -# rights and limitations under the License. -# -# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -# -# The Initial Developer of the Original Code is SciTech Software, Inc. -# All Rights Reserved. -# -# ======================================================================== -# -# Descripton: Generic DMAKE startup makefile definitions file. Assumes -# that the SCITECH environment variable has been set to point -# to where all our stuff is installed. You should not need -# to change anything in this file. -# -# Watcom C++ 10.x 32 bit version. Supports Rational's DOS4GW -# DOS Extender, PMODE/W, Causeway, FlashTek's X32-VM, -# Phar Lap's TNT DOS Extender, 32-bit Windows development and -# 32-bit OS/2 development. -# -############################################################################# - -# Include standard startup script definitions -.IMPORT: SCITECH -.INCLUDE: "$(SCITECH)\makedefs\startup.mk" - -# Import enivornment variables that we use -.IMPORT .IGNORE : USE_TNT USE_X32 USE_X32VM USE_PMODEW STKCALL USE_CAUSEWAY -.IMPORT .IGNORE : USE_WIN386 USE_OS232 USE_OS2GUI WC_LIBBASE NOOPT DOSSTYLE -.IMPORT .IGNORE : OS2_SHELL USE_CODEVIEW USE_DOS32A USE_QNX4 LEAVE_LINKFILE - -# We are compiling for a 32 bit envionment - _32BIT_ := 1 - -# Setup special environment for QNX 4 (Unix'ish) -.IF $(USE_QNX4) - USE_QNX := 1 - L := .a # Libraries - LP := lib # LP - Library file prefix (name of file on disk) - LL := lib # Library link prefix (name of library on link command line) - LE := .a # Library link suffix (extension of library on link command line) -.ENDIF - -# Default commands for compiling, assembling linking and archiving - CC := wcc386 - CPP := wpp386 - CFLAGS := -zq-j-s-fpi87 -.IF $(USE_NASM) - AS := nasm - ASFLAGS := -t -f obj -d__FLAT__ -dSTDCALL_MANGLE -iINCLUDE -i$(SCITECH)\INCLUDE -.ELSE -.IF $(USE_TASM32) - AS := tasm32 - DLL_TASM := tasm32 -.ELIF $(USE_TASMX) - AS := tasmx - DLL_TASM := tasmx -.ELSE - AS := tasm - DLL_TASM := tasm -.ENDIF - ASFLAGS := /t /mx /m /w-res /w-mcp /D__FLAT__ /DSTDCALL_MANGLE /iINCLUDE /i$(SCITECH)\INCLUDE - GAS := gcc - GAS_FLAGS := -D__WATCOMC__ -D__SW_3S -D__SW_S -U__GNUC__ -UDJGPP -U__unix__ -Wall -I. -I$(SCITECH)\include -x assembler-with-cpp -.ENDIF - LD := wlink - LDFLAGS = -.IF $(USE_OS232) - RC := rc -.ELSE - RC := wrc -.ENDIF -.IF $(USE_WIN32) - RCFLAGS := -q /bt=nt -.ELIF $(USE_OS232) -.IF $(USE_OS2GUI) - CFLAGS += -D__OS2_PM__ -.ENDIF -.ELSE - RCFLAGS := -q -.ENDIF - LIB := wlib - LIBFLAGS := -q - ILIB := wlib - ILIBFLAGS := -c - INTEL_X86 := 1 - -# Set the compiler warning level -.IF $(MAX_WARN) - CFLAGS += -w4 -.ELSE - CFLAGS += -w1 -.ENDIF - -# Optionally turn on debugging information (Codeview format) -.IF $(DBG) -.IF $(USE_WIN32) -.IF $(USE_CODEVIEW) - CFLAGS += -d2 -hc - LDFLAGS += D CODEVIEW OPT CVPACK -.ELSE - CFLAGS += -d2 - LDFLAGS += D A -.ENDIF -.ELSE - CFLAGS += -d2 - LDFLAGS += D A -.ENDIF - LIBFLAGS += -p=768 -.IF $(USE_NASM) - ASFLAGS += -F borland -g -.ELSE -.IF $(USE_TASM32) - ASFLAGS += /q # TASM32 fucks up Watcom C++ debug info -.ELIF $(OS2_SHELL) - ASFLAGS += /q # TASM for OS/2 fucks up Watcom C++ debug info -.ELSE - ASFLAGS += /zi -.ENDIF -.ENDIF -.ELSE -.IF $(USE_NASM) - ASFLAGS += -F null -.ELSE - ASFLAGS += /q -.ENDIF -.END - -# Optionally turn on optimisations (with or without stack conventions) -.IF $(STKCALL) -.IF $(OPT) - CFLAGS += -onatx-5s-fp5 -.ELIF $(OPT_SIZE) - CFLAGS += -onaslmr-5s-fp5 -.ELIF $(NOOPT) - CFLAGS += -od-5s -.ELSE - CFLAGS += -3s -.END -.ELSE -.IF $(OPT) - CFLAGS += -onatx-5r-fp5 -.ELIF $(OPT_SIZE) - CFLAGS += -onaslmr-5r-fp5 -.ELIF $(NOOPT) - CFLAGS += -od-5r -.END -.END - -# Optionally turn on direct i387 FPU instructions optimised for Pentium -.IF $(FPU) - CFLAGS += -DFPU387 - ASFLAGS += -dFPU387 -.END - -# Optionally compile a beta release version of a product -.IF $(BETA) - CFLAGS += -DBETA - ASFLAGS += -dBETA -.END - -.IF $(USE_TNT) # Use Phar Lap's TNT DOS Extender - CFLAGS += -bt=nt -DTNT - ASFLAGS += -dTNT - LDFLAGS += SYS NT OP STUB=GOTNT.EXE - LIB_OS = DOS32 -.ELIF $(USE_X32VM) # Use FlashTek X-32VM DOS extender - CFLAGS += -bt=dos - LDFLAGS += SYS X32RV - DX_CFLAGS += -DX32VM - DX_ASFLAGS += -dX32VM - LIB_OS = DOS32 -.ELIF $(USE_X32) # Use FlashTek X-32 DOS extender - CFLAGS += -bt=dos - LDFLAGS += SYS X32R - DX_CFLAGS += -DX32VM - DX_ASFLAGS += -dX32VM - LIB_OS = DOS32 -.ELIF $(USE_QNX4) # Build QNX 4 app - CFLAGS += -bt=qnx386 - LDFLAGS += SYS QNX386FLAT OP CASEEXACT OP OFFSET=40k OP STACK=32k - CFLAGS += -D__QNX__ -D__UNIX__ - ASFLAGS += -d__QNX__ -d__UNIX__ - LIB_OS = QNX4 -.ELIF $(USE_OS232) -.IF $(BUILD_DLL) - CFLAGS += -bm-bd-bt=os2-sg-DBUILD_DLL - ASFLAGS += -dBUILD_DLL -.ELSE - CFLAGS += -bm-bt=os2-sg -.ENDIF - DX_ASFLAGS += -d__OS2__ - LIB_OS = os232 -.ELIF $(USE_SNAP) # Build 32 bit Snap app -.IF $(BUILD_DLL) - CFLAGS += -bm-bd-bt=nt-DBUILD_DLL - ASFLAGS += -dBUILD_DLL -.ELSE - CFLAGS += -bm-bt=nt-D_WIN32 -.ENDIF - LDFLAGS += OP nodefaultlibs -.IF $(STKCALL) - DEFLIBS := clib3s.lib,math3s.lib,noemu387.lib, -.ELSE - DEFLIBS := clib3r.lib,math3r.lib,noemu387.lib, -.ENDIF - LIB_OS = SNAP -.ELIF $(USE_WIN32) # Build 32 bit Windows NT app -.IF $(WIN32_GUI) -.ELSE - CFLAGS += -D__CONSOLE__ -.ENDIF -.IF $(BUILD_DLL) - CFLAGS += -bm-bd-bt=nt-sg-DBUILD_DLL -D_WIN32 - ASFLAGS += -dBUILD_DLL -.ELSE - CFLAGS += -bm-bt=nt-sg-D_WIN32 -.ENDIF - DX_ASFLAGS += -d__WINDOWS32__ - LIB_OS = WIN32 - DEFLIBS := kernel32.lib,user32.lib,gdi32.lib,advapi32.lib,shell32.lib,winmm.lib,comdlg32.lib,comctl32.lib,ole32.lib,oleaut32.lib,version.lib,winspool.lib,uuid.lib,wsock32.lib,rpcrt4.lib, -.ELIF $(USE_WIN386) # Build 32 bit Win386 extended app -.IF $(BUILD_DLL) - CFLAGS += -bd-bt=windows-DBUILD_DLL - ASFLAGS += -dBUILD_DLL -.ELSE - CFLAGS += -bt=windows -.ENDIF - DX_ASFLAGS += -d__WIN386__ - LIB_OS = WIN386 -.ELIF $(USE_PMODEW) # PMODE/W - CFLAGS += -bt=dos - USE_DOS4GW := 1 - USE_REALDOS := 1 - LDFLAGS += SYS PMODEW - DX_CFLAGS += -DDOS4GW - DX_ASFLAGS += -dDOS4GW - LIB_OS = DOS32 -.ELIF $(USE_CAUSEWAY) # Causeway - CFLAGS += -bt=dos - USE_DOS4GW := 1 - USE_REALDOS := 1 - LDFLAGS += SYS CAUSEWAY - DX_CFLAGS += -DDOS4GW - DX_ASFLAGS += -dDOS4GW - LIB_OS = DOS32 -.ELIF $(USE_DOS32A) # DOS32/A - CFLAGS += -bt=dos - USE_DOS4GW := 1 - USE_REALDOS := 1 - LDFLAGS += SYS DOS32A - DX_CFLAGS += -DDOS4GW - DX_ASFLAGS += -dDOS4GW - LIB_OS = DOS32 -.ELSE # Use DOS4GW - CFLAGS += -bt=dos - USE_DOS4GW := 1 - USE_REALDOS := 1 - LDFLAGS += SYS DOS4G - DX_CFLAGS += -DDOS4GW - DX_ASFLAGS += -dDOS4GW - LIB_OS = DOS32 -.END - -# Disable linking to default C runtime library and PM library - -.IF $(NO_RUNTIME) -LDFLAGS += OP nodefaultlibs -DEFLIBS := -.ELSE - -# Place to look for PM library files - -.IF $(USE_SNAP) # Build 32 bit Snap app or dll -PMLIB := -.ELIF $(USE_WIN32) -.IF $(STKCALL) -PMLIB := spm.lib, -.ELSE -PMLIB := pm.lib, -.ENDIF -.ELIF $(USE_OS232) -.IF $(STKCALL) -.IF $(USE_OS2GUI) -PMLIB := spm_pm.lib, -.ELSE -PMLIB := spm.lib, -.ENDIF -.ELSE -.IF $(USE_OS2GUI) -PMLIB := pm_pm.lib, -.ELSE -PMLIB := pm.lib, -.ENDIF -.ENDIF -.ELIF $(USE_QNX4) -.IF $(STKCALL) -PMLIB := libspm.a, -.ELSE -PMLIB := libpm.a, -.ENDIF -.ELIF $(USE_TNT) -.IF $(STKCALL) -PMLIB := tnt\spm.lib, -.ELSE -PMLIB := tnt\pm.lib, -.ENDIF -.ELIF $(USE_X32) -.IF $(STKCALL) -PMLIB := x32\spm.lib, -.ELSE -PMLIB := x32\pm.lib, -.ENDIF -.ELSE -.IF $(STKCALL) -PMLIB := dos4gw\spm.lib, -.ELSE -PMLIB := dos4gw\pm.lib, -.ENDIF -.ENDIF -.ENDIF - -# Define the base directory for library files - -.IF $(CHECKED) -LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug -CFLAGS += -DCHECKED=1 -.ELSE -LIB_BASE_DIR := $(SCITECH_LIB)\lib\release -.ENDIF - -# Define where to install library files - LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(WC_LIBBASE) - LIB_DEST := $(LIB_BASE) - - LDFLAGS += op map - -# Define which file contains our rules - - RULES_MAK := wc32.mk diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/besys.c b/board/MAI/bios_emulator/scitech/src/biosemu/besys.c deleted file mode 100644 index 1512ce9..0000000 --- a/board/MAI/bios_emulator/scitech/src/biosemu/besys.c +++ /dev/null @@ -1,408 +0,0 @@ -/**************************************************************************** -* -* BIOS emulator and interface -* to Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: This file includes BIOS emulator I/O and memory access -* functions. -* -****************************************************************************/ - -#include "biosemui.h" - -/*------------------------------- Macros ----------------------------------*/ - -/* Macros to read and write values to x86 bus memory. Replace these as - * necessary if you need to do something special to access memory over - * the bus on a particular processor family. - */ - -#define readb(base,off) *((u8*)((u32)(base) + (off))) -#define readw(base,off) *((u16*)((u32)(base) + (off))) -#define readl(base,off) *((u32*)((u32)(base) + (off))) -#define writeb(v,base,off) *((u8*)((u32)(base) + (off))) = (v) -#define writew(v,base,off) *((u16*)((u32)(base) + (off))) = (v) -#define writel(v,base,off) *((u32*)((u32)(base) + (off))) = (v) - -/*----------------------------- Implementation ----------------------------*/ - -#ifdef DEBUG -# define DEBUG_MEM() (M.x86.debug & DEBUG_MEM_TRACE_F) -#else -# define DEBUG_MEM() -#endif - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read - -RETURNS: -Byte value read from emulator memory. - -REMARKS: -Reads a byte value from the emulator memory. We have three distinct memory -regions that are handled differently, which this function handles. -****************************************************************************/ -u8 X86API BE_rdb( - u32 addr) -{ - u8 val = 0; - - if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { - val = *(u8*)(_BE_env.biosmem_base + addr - 0xC0000); - } - else if (addr >= 0xA0000 && addr <= 0xFFFFF) { - val = readb(_BE_env.busmem_base, addr - 0xA0000); - } - else if (addr > M.mem_size - 1) { -DB( printk("mem_read: address %#lx out of range!\n", addr);) - HALT_SYS(); - } - else { - val = *(u8*)(M.mem_base + addr); - } -DB( if (DEBUG_MEM()) - printk("%#08x 1 -> %#x\n", addr, val);) - return val; -} - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read - -RETURNS: -Word value read from emulator memory. - -REMARKS: -Reads a word value from the emulator memory. We have three distinct memory -regions that are handled differently, which this function handles. -****************************************************************************/ -u16 X86API BE_rdw( - u32 addr) -{ - u16 val = 0; - - if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { -#ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - addr -= 0xC0000; - val = ( *(u8*)(_BE_env.biosmem_base + addr) | - (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8)); - } - else -#endif - val = *(u16*)(_BE_env.biosmem_base + addr - 0xC0000); - } - else if (addr >= 0xA0000 && addr <= 0xFFFFF) { -#ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - addr -= 0xA0000; - val = ( readb(_BE_env.busmem_base, addr) | - (readb(_BE_env.busmem_base, addr + 1) << 8)); - } - else -#endif - val = readw(_BE_env.busmem_base, addr - 0xA0000); - } - else if (addr > M.mem_size - 2) { -DB( printk("mem_read: address %#lx out of range!\n", addr);) - HALT_SYS(); - } - else { -#ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - val = ( *(u8*)(M.mem_base + addr) | - (*(u8*)(M.mem_base + addr + 1) << 8)); - } - else -#endif - val = *(u16*)(M.mem_base + addr); - } -DB( if (DEBUG_MEM()) - printk("%#08x 2 -> %#x\n", addr, val);) - return val; -} - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read - -RETURNS: -Long value read from emulator memory. - -REMARKS: -Reads a long value from the emulator memory. We have three distinct memory -regions that are handled differently, which this function handles. -****************************************************************************/ -u32 X86API BE_rdl( - u32 addr) -{ - u32 val = 0; - - if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { -#ifdef __BIG_ENDIAN__ - if (addr & 0x3) { - addr -= 0xC0000; - val = ( *(u8*)(_BE_env.biosmem_base + addr + 0) | - (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8) | - (*(u8*)(_BE_env.biosmem_base + addr + 2) << 16) | - (*(u8*)(_BE_env.biosmem_base + addr + 3) << 24)); - } - else -#endif - val = *(u32*)(_BE_env.biosmem_base + addr - 0xC0000); - } - else if (addr >= 0xA0000 && addr <= 0xFFFFF) { -#ifdef __BIG_ENDIAN__ - if (addr & 0x3) { - addr -= 0xA0000; - val = ( readb(_BE_env.busmem_base, addr) | - (readb(_BE_env.busmem_base, addr + 1) << 8) | - (readb(_BE_env.busmem_base, addr + 2) << 16) | - (readb(_BE_env.busmem_base, addr + 3) << 24)); - } - else -#endif - val = readl(_BE_env.busmem_base, addr - 0xA0000); - } - else if (addr > M.mem_size - 4) { -DB( printk("mem_read: address %#lx out of range!\n", addr);) - HALT_SYS(); - } - else { -#ifdef __BIG_ENDIAN__ - if (addr & 0x3) { - val = ( *(u8*)(M.mem_base + addr + 0) | - (*(u8*)(M.mem_base + addr + 1) << 8) | - (*(u8*)(M.mem_base + addr + 2) << 16) | - (*(u8*)(M.mem_base + addr + 3) << 24)); - } - else -#endif - val = *(u32*)(M.mem_base + addr); - } -DB( if (DEBUG_MEM()) - printk("%#08x 4 -> %#x\n", addr, val);) - return val; -} - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read -val - Value to store - -REMARKS: -Writes a byte value to emulator memory. We have three distinct memory -regions that are handled differently, which this function handles. -****************************************************************************/ -void X86API BE_wrb( - u32 addr, - u8 val) -{ -DB( if (DEBUG_MEM()) - printk("%#08x 1 <- %#x\n", addr, val);) - if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { - *(u8*)(_BE_env.biosmem_base + addr - 0xC0000) = val; - } - else if (addr >= 0xA0000 && addr <= 0xFFFFF) { - writeb(val, _BE_env.busmem_base, addr - 0xA0000); - } - else if (addr > M.mem_size-1) { -DB( printk("mem_write: address %#lx out of range!\n", addr);) - HALT_SYS(); - } - else { - *(u8*)(M.mem_base + addr) = val; - } -} - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read -val - Value to store - -REMARKS: -Writes a word value to emulator memory. We have three distinct memory -regions that are handled differently, which this function handles. -****************************************************************************/ -void X86API BE_wrw( - u32 addr, - u16 val) -{ -DB( if (DEBUG_MEM()) - printk("%#08x 2 <- %#x\n", addr, val);) - if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { -#ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - addr -= 0xC0000; - *(u8*)(_BE_env.biosmem_base + addr + 0) = (val >> 0) & 0xff; - *(u8*)(_BE_env.biosmem_base + addr + 1) = (val >> 8) & 0xff; - } - else -#endif - *(u16*)(_BE_env.biosmem_base + addr - 0xC0000) = val; - } - else if (addr >= 0xA0000 && addr <= 0xFFFFF) { -#ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - addr -= 0xA0000; - writeb(val >> 0, _BE_env.busmem_base, addr); - writeb(val >> 8, _BE_env.busmem_base, addr + 1); - } - else -#endif - writew(val, _BE_env.busmem_base, addr - 0xA0000); - } - else if (addr > M.mem_size-2) { -DB( printk("mem_write: address %#lx out of range!\n", addr);) - HALT_SYS(); - } - else { -#ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; - *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; - } - else -#endif - *(u16*)(M.mem_base + addr) = val; - } -} - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read -val - Value to store - -REMARKS: -Writes a long value to emulator memory. We have three distinct memory -regions that are handled differently, which this function handles. -****************************************************************************/ -void X86API BE_wrl( - u32 addr, - u32 val) -{ -DB( if (DEBUG_MEM()) - printk("%#08x 4 <- %#x\n", addr, val);) - if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { -#ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - addr -= 0xC0000; - *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; - *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; - *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; - *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; - } - else -#endif - *(u32*)(M.mem_base + addr - 0xC0000) = val; - } - else if (addr >= 0xA0000 && addr <= 0xFFFFF) { -#ifdef __BIG_ENDIAN__ - if (addr & 0x3) { - addr -= 0xA0000; - writeb(val >> 0, _BE_env.busmem_base, addr); - writeb(val >> 8, _BE_env.busmem_base, addr + 1); - writeb(val >> 16, _BE_env.busmem_base, addr + 1); - writeb(val >> 24, _BE_env.busmem_base, addr + 1); - } - else -#endif - writel(val, _BE_env.busmem_base, addr - 0xA0000); - } - else if (addr > M.mem_size-4) { -DB( printk("mem_write: address %#lx out of range!\n", addr);) - HALT_SYS(); - } - else { -#ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; - *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; - *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; - *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; - } - else -#endif - *(u32*)(M.mem_base + addr) = val; - } -} - -/* Debug functions to do ISA/PCI bus port I/O */ - -#ifdef DEBUG -#define DEBUG_IO() (M.x86.debug & DEBUG_IO_TRACE_F) - -u8 X86API BE_inb(int port) -{ - u8 val = PM_inpb(port); - if (DEBUG_IO()) - printk("%04X:%04X: inb.%04X -> %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); - return val; -} - -u16 X86API BE_inw(int port) -{ - u16 val = PM_inpw(port); - if (DEBUG_IO()) - printk("%04X:%04X: inw.%04X -> %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); - return val; -} - -u32 X86API BE_inl(int port) -{ - u32 val = PM_inpd(port); - if (DEBUG_IO()) - printk("%04X:%04X: inl.%04X -> %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); - return val; -} - -void X86API BE_outb(int port, u8 val) -{ - if (DEBUG_IO()) - printk("%04X:%04X: outb.%04X <- %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); - PM_outpb(port,val); -} - -void X86API BE_outw(int port, u16 val) -{ - if (DEBUG_IO()) - printk("%04X:%04X: outw.%04X <- %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); - PM_outpw(port,val); -} - -void X86API BE_outl(int port, u32 val) -{ - if (DEBUG_IO()) - printk("%04X:%04X: outl.%04X <- %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); - PM_outpd(port,val); -} -#endif diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/bios.c b/board/MAI/bios_emulator/scitech/src/biosemu/bios.c deleted file mode 100644 index c0f4a4b..0000000 --- a/board/MAI/bios_emulator/scitech/src/biosemu/bios.c +++ /dev/null @@ -1,250 +0,0 @@ -/**************************************************************************** -* -* BIOS emulator and interface -* to Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Module implementing the BIOS specific functions. -* -****************************************************************************/ - -#include "biosemui.h" - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -PARAMETERS: -intno - Interrupt number being serviced - -REMARKS: -Handler for undefined interrupts. -****************************************************************************/ -static void X86API undefined_intr( - int intno) -{ - if (BE_rdw(intno * 4 + 2) == BIOS_SEG) - printk("biosEmu: undefined interrupt %xh called!\n",intno); - else - X86EMU_prepareForInt(intno); -} - -/**************************************************************************** -PARAMETERS: -intno - Interrupt number being serviced - -REMARKS: -This function handles the default system BIOS Int 10h (the default is stored -in the Int 42h vector by the system BIOS at bootup). We only need to handle -a small number of special functions used by the BIOS during POST time. -****************************************************************************/ -static void X86API int42( - int intno) -{ - if (M.x86.R_AH == 0x12 && M.x86.R_BL == 0x32) { - if (M.x86.R_AL == 0) { - /* Enable CPU accesses to video memory */ - PM_outpb(0x3c2, PM_inpb(0x3cc) | (u8)0x02); - return; - } - else if (M.x86.R_AL == 1) { - /* Disable CPU accesses to video memory */ - PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8)~0x02); - return; - } -#ifdef DEBUG - else { - printk("biosEmu/bios.int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n",M.x86.R_AL); - } -#endif - } -#ifdef DEBUG - else { - printk("biosEmu/bios.int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n",M.x86.R_AH, M.x86.R_AL, M.x86.R_BL); - } -#endif -} - -/**************************************************************************** -PARAMETERS: -intno - Interrupt number being serviced - -REMARKS: -This function handles the default system BIOS Int 10h. If the POST code -has not yet re-vectored the Int 10h BIOS interrupt vector, we handle this -by simply calling the int42 interrupt handler above. Very early in the -BIOS POST process, the vector gets replaced and we simply let the real -mode interrupt handler process the interrupt. -****************************************************************************/ -static void X86API int10( - int intno) -{ - if (BE_rdw(intno * 4 + 2) == BIOS_SEG) - int42(intno); - else - X86EMU_prepareForInt(intno); -} - -/* Result codes returned by the PCI BIOS */ - -#define SUCCESSFUL 0x00 -#define FUNC_NOT_SUPPORT 0x81 -#define BAD_VENDOR_ID 0x83 -#define DEVICE_NOT_FOUND 0x86 -#define BAD_REGISTER_NUMBER 0x87 -#define SET_FAILED 0x88 -#define BUFFER_TOO_SMALL 0x89 - -/**************************************************************************** -PARAMETERS: -intno - Interrupt number being serviced - -REMARKS: -This function handles the default Int 1Ah interrupt handler for the real -mode code, which provides support for the PCI BIOS functions. Since we only -want to allow the real mode BIOS code *only* see the PCI config space for -its own device, we only return information for the specific PCI config -space that we have passed in to the init function. This solves problems -when using the BIOS to warm boot a secondary adapter when there is an -identical adapter before it on the bus (some BIOS'es get confused in this -case). -****************************************************************************/ -static void X86API int1A( - unused) -{ - u16 pciSlot; - - /* Fail if no PCI device information has been registered */ - if (!_BE_env.vgaInfo.pciInfo) - return; - pciSlot = (u16)(_BE_env.vgaInfo.pciInfo->slot.i >> 8); - switch (M.x86.R_AX) { - case 0xB101: /* PCI bios present? */ - M.x86.R_AL = 0x00; /* no config space/special cycle generation support */ - M.x86.R_EDX = 0x20494350; /* " ICP" */ - M.x86.R_BX = 0x0210; /* Version 2.10 */ - M.x86.R_CL = 0; /* Max bus number in system */ - CLEAR_FLAG(F_CF); - break; - case 0xB102: /* Find PCI device */ - M.x86.R_AH = DEVICE_NOT_FOUND; - if (M.x86.R_DX == _BE_env.vgaInfo.pciInfo->VendorID && - M.x86.R_CX == _BE_env.vgaInfo.pciInfo->DeviceID && - M.x86.R_SI == 0) { - M.x86.R_AH = SUCCESSFUL; - M.x86.R_BX = pciSlot; - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB103: /* Find PCI class code */ - M.x86.R_AH = DEVICE_NOT_FOUND; - if (M.x86.R_CL == _BE_env.vgaInfo.pciInfo->Interface && - M.x86.R_CH == _BE_env.vgaInfo.pciInfo->SubClass && - (u8)(M.x86.R_ECX >> 16) == _BE_env.vgaInfo.pciInfo->BaseClass) { - M.x86.R_AH = SUCCESSFUL; - M.x86.R_BX = pciSlot; - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB108: /* Read configuration byte */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - M.x86.R_CL = (u8)PCI_accessReg(M.x86.R_DI,0,PCI_READ_BYTE,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB109: /* Read configuration word */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - M.x86.R_CX = (u16)PCI_accessReg(M.x86.R_DI,0,PCI_READ_WORD,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB10A: /* Read configuration dword */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - M.x86.R_ECX = (u32)PCI_accessReg(M.x86.R_DI,0,PCI_READ_DWORD,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB10B: /* Write configuration byte */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - PCI_accessReg(M.x86.R_DI,M.x86.R_CL,PCI_WRITE_BYTE,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB10C: /* Write configuration word */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - PCI_accessReg(M.x86.R_DI,M.x86.R_CX,PCI_WRITE_WORD,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - case 0xB10D: /* Write configuration dword */ - M.x86.R_AH = BAD_REGISTER_NUMBER; - if (M.x86.R_BX == pciSlot) { - M.x86.R_AH = SUCCESSFUL; - PCI_accessReg(M.x86.R_DI,M.x86.R_ECX,PCI_WRITE_DWORD,_BE_env.vgaInfo.pciInfo); - } - CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); - break; - default: - printk("biosEmu/bios.int1a: unknown function AX=%#04x\n", M.x86.R_AX); - } -} - -/**************************************************************************** -REMARKS: -This function initialises the BIOS emulation functions for the specific -PCI display device. We insulate the real mode BIOS from any other devices -on the bus, so that it will work correctly thinking that it is the only -device present on the bus (ie: avoiding any adapters present in from of -the device we are trying to control). -****************************************************************************/ -void _BE_bios_init( - u32 *intrTab) -{ - int i; - X86EMU_intrFuncs bios_intr_tab[256]; - - for (i = 0; i < 256; ++i) { - intrTab[i] = BIOS_SEG << 16; - bios_intr_tab[i] = undefined_intr; - } - bios_intr_tab[0x10] = int10; - bios_intr_tab[0x1A] = int1A; - bios_intr_tab[0x42] = int42; - X86EMU_setupIntrFuncs(bios_intr_tab); -} diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c b/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c deleted file mode 100644 index 0052709..0000000 --- a/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c +++ /dev/null @@ -1,445 +0,0 @@ -/**************************************************************************** -* -* BIOS emulator and interface -* to Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Module implementing the system specific functions. This -* module is always compiled and linked in the OS depedent -* libraries, and never in a binary portable driver. -* -****************************************************************************/ - -#include "biosemui.h" -#include -#include - -/*------------------------- Global Variables ------------------------------*/ - -BE_sysEnv _BE_env; -#ifdef __DRIVER__ -PM_imports _VARAPI _PM_imports; -#endif -static X86EMU_memFuncs _BE_mem = { - BE_rdb, - BE_rdw, - BE_rdl, - BE_wrb, - BE_wrw, - BE_wrl, - }; -#ifdef DEBUG -static X86EMU_pioFuncs _BE_pio = { - BE_inb, - BE_inw, - BE_inl, - BE_outb, - BE_outw, - BE_outl, - }; -#else -static X86EMU_pioFuncs _BE_pio = { - (void*)PM_inpb, - (void*)PM_inpw, - (void*)PM_inpd, - (void*)PM_outpb, - (void*)PM_outpw, - (void*)PM_outpd, - }; -#endif - -/*-------------------------- Implementation -------------------------------*/ - -#define OFF(addr) (u16)(((addr) >> 0) & 0xffff) -#define SEG(addr) (u16)(((addr) >> 4) & 0xf000) - -/**************************************************************************** -PARAMETERS: -debugFlags - Flags to enable debugging options (debug builds only) -memSize - Amount of memory to allocate for real mode machine -info - Pointer to default VGA device information - -REMARKS: -This functions initialises the BElib, and uses the passed in -BIOS image as the BIOS that is used and emulated at 0xC0000. -****************************************************************************/ -ibool PMAPI BE_init( - u32 debugFlags, - int memSize, - BE_VGAInfo *info) -{ -#ifndef __DRIVER__ - PM_init(); -#endif - memset(&M,0,sizeof(M)); - if (memSize < 20480) - PM_fatalError("Emulator requires at least 20Kb of memory!\n"); - if ((M.mem_base = (unsigned long)malloc(memSize)) == NULL) - PM_fatalError("Out of memory!"); - M.mem_size = memSize; - _BE_env.busmem_base = (ulong)PM_mapPhysicalAddr(0xA0000,0x5FFFF,true); - M.x86.debug = debugFlags; - _BE_bios_init((u32*)info->LowMem); - X86EMU_setupMemFuncs(&_BE_mem); - X86EMU_setupPioFuncs(&_BE_pio); - BE_setVGA(info); - return true; -} - -/**************************************************************************** -PARAMETERS: -debugFlags - Flags to enable debugging options (debug builds only) - -REMARKS: -This function allows the application to enable logging and debug flags -on a function call basis, so we can specifically enable logging only -for specific functions that are causing problems in debug mode. -****************************************************************************/ -void PMAPI BE_setDebugFlags( - u32 debugFlags) -{ - M.x86.debug = debugFlags; -} - -/**************************************************************************** -PARAMETERS: -info - Pointer to VGA device information to make current - -REMARKS: -This function sets the VGA BIOS functions in the emulator to point to the -specific VGA BIOS in use. This includes swapping the BIOS interrupt -vectors, BIOS image and BIOS data area to the new BIOS. This allows the -real mode BIOS to be swapped without resetting the entire emulator. -****************************************************************************/ -void PMAPI BE_setVGA( - BE_VGAInfo *info) -{ - _BE_env.vgaInfo.pciInfo = info->pciInfo; - _BE_env.vgaInfo.BIOSImage = info->BIOSImage; - if (info->BIOSImage) { - _BE_env.biosmem_base = (ulong)info->BIOSImage; - _BE_env.biosmem_limit = 0xC0000 + info->BIOSImageLen-1; - } - else { - _BE_env.biosmem_base = _BE_env.busmem_base + 0x20000; - _BE_env.biosmem_limit = 0xC7FFF; - } - if (*((u32*)info->LowMem) == 0) - _BE_bios_init((u32*)info->LowMem); - memcpy((u8*)M.mem_base,info->LowMem,sizeof(info->LowMem)); -} - -/**************************************************************************** -PARAMETERS: -info - Pointer to VGA device information to retrieve current - -REMARKS: -This function returns the VGA BIOS functions currently active in the -emulator, so they can be restored at a later date. -****************************************************************************/ -void PMAPI BE_getVGA( - BE_VGAInfo *info) -{ - info->pciInfo = _BE_env.vgaInfo.pciInfo; - info->BIOSImage = _BE_env.vgaInfo.BIOSImage; - memcpy(info->LowMem,(u8*)M.mem_base,sizeof(info->LowMem)); -} - -/**************************************************************************** -PARAMETERS: -r_seg - Segment for pointer to convert -r_off - Offset for pointer to convert - -REMARKS: -This function maps a real mode pointer in the emulator memory to a protected -mode pointer that can be used to directly access the memory. - -NOTE: The memory is *always* in little endian format, son on non-x86 - systems you will need to do endian translations to access this - memory. -****************************************************************************/ -void * PMAPI BE_mapRealPointer( - uint r_seg, - uint r_off) -{ - u32 addr = ((u32)r_seg << 4) + r_off; - - if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { - return (void*)(_BE_env.biosmem_base + addr - 0xC0000); - } - else if (addr >= 0xA0000 && addr <= 0xFFFFF) { - return (void*)(_BE_env.busmem_base + addr - 0xA0000); - } - return (void*)(M.mem_base + addr); -} - -/**************************************************************************** -PARAMETERS: -len - Return the length of the VESA buffer -rseg - Place to store VESA buffer segment -roff - Place to store VESA buffer offset - -REMARKS: -This function returns the address of the VESA transfer buffer in real -mode emulator memory. The VESA transfer buffer is always 1024 bytes long, -and located at 15Kb into the start of the real mode memory (16Kb is where -we put the real mode code we execute for issuing interrupts). - -NOTE: The memory is *always* in little endian format, son on non-x86 - systems you will need to do endian translations to access this - memory. -****************************************************************************/ -void * PMAPI BE_getVESABuf( - uint *len, - uint *rseg, - uint *roff) -{ - *len = 1024; - *rseg = SEG(0x03C00); - *roff = OFF(0x03C00); - return (void*)(M.mem_base + ((u32)*rseg << 4) + *roff); -} - -/**************************************************************************** -REMARKS: -Cleans up and exits the emulator. -****************************************************************************/ -void PMAPI BE_exit(void) -{ - free((void*)M.mem_base); - PM_freePhysicalAddr((void*)_BE_env.busmem_base,0x5FFFF); -} - -/**************************************************************************** -PARAMETERS: -seg - Segment of code to call -off - Offset of code to call -regs - Real mode registers to load -sregs - Real mode segment registers to load - -REMARKS: -This functions calls a real mode far function at the specified address, -and loads all the x86 registers from the passed in registers structure. -On exit the registers returned from the call are returned in the same -structures. -****************************************************************************/ -void PMAPI BE_callRealMode( - uint seg, - uint off, - RMREGS *regs, - RMSREGS *sregs) -{ - M.x86.R_EAX = regs->e.eax; - M.x86.R_EBX = regs->e.ebx; - M.x86.R_ECX = regs->e.ecx; - M.x86.R_EDX = regs->e.edx; - M.x86.R_ESI = regs->e.esi; - M.x86.R_EDI = regs->e.edi; - M.x86.R_DS = sregs->ds; - M.x86.R_ES = sregs->es; - M.x86.R_FS = sregs->fs; - M.x86.R_GS = sregs->gs; - M.x86.R_CS = (u16)seg; - M.x86.R_IP = (u16)off; - M.x86.R_SS = SEG(M.mem_size - 1); - M.x86.R_SP = OFF(M.mem_size - 1); - X86EMU_exec(); - regs->e.cflag = M.x86.R_EFLG & F_CF; - regs->e.eax = M.x86.R_EAX; - regs->e.ebx = M.x86.R_EBX; - regs->e.ecx = M.x86.R_ECX; - regs->e.edx = M.x86.R_EDX; - regs->e.esi = M.x86.R_ESI; - regs->e.edi = M.x86.R_EDI; - sregs->ds = M.x86.R_DS; - sregs->es = M.x86.R_ES; - sregs->fs = M.x86.R_FS; - sregs->gs = M.x86.R_GS; -} - -/**************************************************************************** -PARAMETERS: -intno - Interrupt number to execute -in - Real mode registers to load -out - Place to store resulting real mode registers - -REMARKS: -This functions calls a real mode interrupt function at the specified address, -and loads all the x86 registers from the passed in registers structure. -On exit the registers returned from the call are returned in out stucture. -****************************************************************************/ -int PMAPI BE_int86( - int intno, - RMREGS *in, - RMREGS *out) -{ - M.x86.R_EAX = in->e.eax; - M.x86.R_EBX = in->e.ebx; - M.x86.R_ECX = in->e.ecx; - M.x86.R_EDX = in->e.edx; - M.x86.R_ESI = in->e.esi; - M.x86.R_EDI = in->e.edi; - ((u8*)M.mem_base)[0x4000] = 0xCD; - ((u8*)M.mem_base)[0x4001] = (u8)intno; - ((u8*)M.mem_base)[0x4002] = 0xC3; - M.x86.R_CS = SEG(0x04000); - M.x86.R_IP = OFF(0x04000); - M.x86.R_SS = SEG(M.mem_size - 1); - M.x86.R_SP = OFF(M.mem_size - 1); - X86EMU_exec(); - out->e.cflag = M.x86.R_EFLG & F_CF; - out->e.eax = M.x86.R_EAX; - out->e.ebx = M.x86.R_EBX; - out->e.ecx = M.x86.R_ECX; - out->e.edx = M.x86.R_EDX; - out->e.esi = M.x86.R_ESI; - out->e.edi = M.x86.R_EDI; - return out->x.ax; -} - -/**************************************************************************** -PARAMETERS: -intno - Interrupt number to execute -in - Real mode registers to load -out - Place to store resulting real mode registers -sregs - Real mode segment registers to load - -REMARKS: -This functions calls a real mode interrupt function at the specified address, -and loads all the x86 registers from the passed in registers structure. -On exit the registers returned from the call are returned in out stucture. -****************************************************************************/ -int PMAPI BE_int86x( - int intno, - RMREGS *in, - RMREGS *out, - RMSREGS *sregs) -{ - M.x86.R_EAX = in->e.eax; - M.x86.R_EBX = in->e.ebx; - M.x86.R_ECX = in->e.ecx; - M.x86.R_EDX = in->e.edx; - M.x86.R_ESI = in->e.esi; - M.x86.R_EDI = in->e.edi; - M.x86.R_DS = sregs->ds; - M.x86.R_ES = sregs->es; - M.x86.R_FS = sregs->fs; - M.x86.R_GS = sregs->gs; - ((u8*)M.mem_base)[0x4000] = 0xCD; - ((u8*)M.mem_base)[0x4001] = (u8)intno; - ((u8*)M.mem_base)[0x4002] = 0xC3; - M.x86.R_CS = SEG(0x04000); - M.x86.R_IP = OFF(0x04000); - M.x86.R_SS = SEG(M.mem_size - 1); - M.x86.R_SP = OFF(M.mem_size - 1); - X86EMU_exec(); - out->e.cflag = M.x86.R_EFLG & F_CF; - out->e.eax = M.x86.R_EAX; - out->e.ebx = M.x86.R_EBX; - out->e.ecx = M.x86.R_ECX; - out->e.edx = M.x86.R_EDX; - out->e.esi = M.x86.R_ESI; - out->e.edi = M.x86.R_EDI; - sregs->ds = M.x86.R_DS; - sregs->es = M.x86.R_ES; - sregs->fs = M.x86.R_FS; - sregs->gs = M.x86.R_GS; - return out->x.ax; -} - -#ifdef __DRIVER__ - -/**************************************************************************** -REMARKS: -Empty log function for binary portable DLL. The BPD is compiled without -debug information, so very little is logged anyway so it is simpler this -way. -****************************************************************************/ -void printk(const char *msg, ...) -{ -} - -/**************************************************************************** -REMARKS: -Fatal error handler called when a non-imported function is called by the -driver. We leave this to a runtime error so that older applications and -shell drivers will work with newer bpd drivers provided no newer functions -are required by the driver itself. If they are, the application or shell -driver needs to be recompiled. -****************************************************************************/ -static void _PM_fatalErrorHandler(void) -{ - PM_fatalError("Unsupported PM_imports import function called! Please re-compile!\n"); -} - -/**************************************************************************** -PARAMETERS: -beImp - BE library imports -beImp - Generic emulator imports - -RETURNS: -Pointer to exported function list - -REMARKS: -This function initialises the BIOS emulator library and returns the list of -loader library exported functions. -{secret} -****************************************************************************/ -BE_exports * _CEXPORT BE_initLibrary( - PM_imports *pmImp) -{ - static BE_exports _BE_exports = { - sizeof(BE_exports), - BE_init, - BE_setVGA, - BE_getVGA, - BE_mapRealPointer, - BE_getVESABuf, - BE_callRealMode, - BE_int86, - BE_int86x, - NULL, - BE_exit, - }; - int i,max; - ulong *p; - - /* Initialize all default imports to point to fatal error handler */ - /* for upwards compatibility. */ - max = sizeof(_PM_imports)/sizeof(BE_initLibrary_t); - for (i = 0,p = (ulong*)&_PM_imports; i < max; i++) - *p++ = (ulong)_PM_fatalErrorHandler; - - /* Now copy all our imported functions */ - memcpy(&_PM_imports,pmImp,MIN(sizeof(_PM_imports),pmImp->dwSize)); - return &_BE_exports; -} - -#endif /* __DRIVER__ */ diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h b/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h deleted file mode 100644 index 23edebc..0000000 --- a/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** -* -* BIOS emulator and interface -* to Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Internal header file for the BIOS emulator library. -* -****************************************************************************/ - -#ifndef __BIOSEMUI_H -#define __BIOSEMUI_H - -#include - -/*---------------------- Macros and type definitions ----------------------*/ - -#ifdef DEBUG -#define DB(x) x -#else -#define DB(x) -#endif - -#define BIOS_SEG 0xfff0 - -#define M _X86EMU_env - -/*-------------------------- Function Prototypes --------------------------*/ - -/* bios.c */ - -void _BE_bios_init(u32 *intrTab); -void _BE_setup_funcs(void); - -/* besys.c */ - -u8 X86API BE_rdb(u32 addr); -u16 X86API BE_rdw(u32 addr); -u32 X86API BE_rdl(u32 addr); -void X86API BE_wrb(u32 addr,u8 val); -void X86API BE_wrw(u32 addr,u16 val); -void X86API BE_wrl(u32 addr,u32 val); -#ifdef DEBUG -u8 X86API BE_inb(int port); -u16 X86API BE_inw(int port); -u32 X86API BE_inl(int port); -void X86API BE_outb(int port, u8 val); -void X86API BE_outw(int port, u16 val); -void X86API BE_outl(int port, u32 val); -#endif - -#endif /* __BIOSEMUI_H */ diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/makefile b/board/MAI/bios_emulator/scitech/src/biosemu/makefile deleted file mode 100644 index 80730b2..0000000 --- a/board/MAI/bios_emulator/scitech/src/biosemu/makefile +++ /dev/null @@ -1,99 +0,0 @@ -############################################################################# -# -# BIOS emulator and interface -# to Realmode X86 Emulator Library -# -# Copyright (C) 1996-1999 SciTech Software, Inc. -# -# ======================================================================== -# -# Permission to use, copy, modify, distribute, and sell this software and -# its documentation for any purpose is hereby granted without fee, -# provided that the above copyright notice appear in all copies and that -# both that copyright notice and this permission notice appear in -# supporting documentation, and that the name of the authors not be used -# in advertising or publicity pertaining to distribution of the software -# without specific, written prior permission. The authors makes no -# representations about the suitability of this software for any purpose. -# It is provided "as is" without express or implied warranty. -# -# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -# PERFORMANCE OF THIS SOFTWARE. -# -# ======================================================================== -# -# Descripton: Generic makefile for the x86emu library. Requires -# the SciTech Software makefile definitions package to be -# installed, which uses the DMAKE make program. -# -############################################################################# - -.IMPORT .IGNORE: DEBUG - -#---------------------------------------------------------------------------- -# Define the lists of object files -#---------------------------------------------------------------------------- - -DLL_OBJS = dllstart$O _pm_imp$O -BIOS_OBJS = biosemu$O bios$O besys$O -X86_OBJS = sys$O decode$O ops$O ops2$O prim_ops$O fpu$O debug$O -CFLAGS += -DSCITECH -I$(SCITECH)\src\x86emu - -.IF $(BUILD_DLL) - -CFLAGS += -I$(PRIVATE)\include\drvlib -I$(SCITECH)\include\drvlib -D__DRIVER__ -ASFLAGS += -d__DRIVER__ -EXELIBS = drvlib$L - -.ELSE - -.IF $(DEBUG) -CFLAGS += -DDEBUG -.ENDIF -OBJECTS = $(BIOS_OBJS) $(X86_OBJS) -LIBCLEAN = *.dll *.lib *.a -LIBFILE = $(LP)biosemu$L - -.ENDIF - -#---------------------------------------------------------------------------- -# Sample test programs -#---------------------------------------------------------------------------- - -all: $(LIBFILE) warmboot$E - -warmboot$E: warmboot$O $(LIBFILE) - -#---------------------------------------------------------------------------- -# Target to build the Binary Portable DLL target -#---------------------------------------------------------------------------- - -biosemu.dll: $(DLL_OBJS) $(BIOS_OBJS) $(X86_OBJS) - -#---------------------------------------------------------------------------- -# Target to build all Intel binary drivers -#---------------------------------------------------------------------------- - -.PHONY mkdrv: - @build wc11-w32 biosemu.dll -u BUILD_DLL=1 NO_RUNTIME=1 OPT=1 - @$(CP) biosemu.dll $(PRIVATE)\nucleus\graphics\biosemu.bpd - @dmake cleanexe - -.PHONY db: - @build wc11-w32 biosemu.dll BUILD_DLL=1 NO_RUNTIME=1 OPT=1 - @$(CP) biosemu.dll $(PRIVATE)\nucleus\graphics\biosemu.bpd - -#---------------------------------------------------------------------------- -# Define the list of object files to create dependency information for -#---------------------------------------------------------------------------- - -DEPEND_OBJ = warmboot$O $(BIOS_OBJS) $(X86_OBJS) $(DLL_OBJS) -DEPEND_SRC = $(SCITECH)/src/x86emu;$(PRIVATE)/src/common -.SOURCE: $(SCITECH)/src/x86emu $(PRIVATE)/src/common - -.INCLUDE: "$(SCITECH)/makedefs/common.mk" diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross b/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross deleted file mode 100644 index 9141003..0000000 --- a/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross +++ /dev/null @@ -1,10 +0,0 @@ -CC = ppc-elf32-gcc -AR = ppc-elf32-ar - -CFLAGS = -D__DRIVER__ -I../../include -DDEBUG -I. - -BIOS_OBJS = biosemu.o bios.o besys.o -X86_OBJS = sys.o decode.o ops.o prim_ops.o fpu.o debug.o - -libbios.a: $(BIOS_OBJS) - $(AR) rcs libbios.a $(BIOS_OBJS) \ No newline at end of file diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c b/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c deleted file mode 100644 index 98d5fb8..0000000 --- a/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c +++ /dev/null @@ -1,569 +0,0 @@ -/**************************************************************************** -* -* BIOS emulator and interface -* to Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Module to implement warm booting of all PCI/AGP controllers -* on the bus. We use the x86 real mode emulator to run the -* BIOS on the primary and secondary controllers to bring -* the cards up. -* -****************************************************************************/ - -#include -#include -#include -#include -#include "biosemu.h" -#ifndef _MAX_PATH -#define _MAX_PATH 256 -#endif - -/*------------------------- Global Variables ------------------------------*/ - -static PCIDeviceInfo PCI[MAX_PCI_DEVICES]; -static int NumPCI = -1; -static int BridgeIndex[MAX_PCI_DEVICES] = {0}; -static int NumBridges; -static PCIBridgeInfo *AGPBridge = NULL; -static int DeviceIndex[MAX_PCI_DEVICES] = {0}; -static int NumDevices; -static u32 debugFlags = 0; -static BE_VGAInfo VGAInfo[MAX_PCI_DEVICES] = {{0}}; -static ibool useV86 = false; -static ibool forcePost = false; - -/* Length of the BIOS image */ - -#define MAX_BIOSLEN (64 * 1024L) -#define FINAL_BIOSLEN (32 * 1024L) - -/* Macro to determine if the VGA is enabled and responding */ - -#define VGA_NOT_ACTIVE() (forcePost || (PM_inpb(0x3CC) == 0xFF) || ((PM_inpb(0x3CC) & 0x2) == 0)) - -#define ENABLE_DEVICE(device) \ - PCI_writePCIRegB(0x4,PCI[DeviceIndex[device]].Command | 0x7,device) - -#define DISABLE_DEVICE(device) \ - PCI_writePCIRegB(0x4,0,device) - -/* Macros to enable and disable AGP VGA resources */ - -#define ENABLE_AGP_VGA() \ - PCI_accessReg(0x3E,AGPBridge->BridgeControl | 0x8,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge) - -#define DISABLE_AGP_VGA() \ - PCI_accessReg(0x3E,AGPBridge->BridgeControl & ~0x8,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge) - -#define RESTORE_AGP_VGA() \ - PCI_accessReg(0x3E,AGPBridge->BridgeControl,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge) - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -RETURNS: -The address to use to map the secondary BIOS (PCI/AGP devices) - -REMARKS: -Searches all the PCI base address registers for the device looking for a -memory mapping that is large enough to hold our ROM BIOS. We usually end up -finding the framebuffer mapping (usually BAR 0x10), and we use this mapping -to map the BIOS for the device into. We use a mapping that is already -assigned to the device to ensure the memory range will be passed through -by any PCI->PCI or AGP->PCI bridge that may be present. - -NOTE: Usually this function is only used for AGP devices, but it may be - used for PCI devices that have already been POST'ed and the BIOS - ROM base address has been zero'ed out. -****************************************************************************/ -static ulong PCI_findBIOSAddr( - int device) -{ - ulong base,size; - int bar; - - for (bar = 0x10; bar <= 0x14; bar++) { - base = PCI_readPCIRegL(bar,device) & ~0xFF; - if (!(base & 0x1)) { - PCI_writePCIRegL(bar,0xFFFFFFFF,device); - size = PCI_readPCIRegL(bar,device) & ~0xFF; - size = ~size+1; - PCI_writePCIRegL(bar,0,device); - if (size >= MAX_BIOSLEN) - return base; - } - } - return 0; -} - -/**************************************************************************** -REMARKS: -Re-writes the PCI base address registers for the secondary PCI controller -with the values from our initial PCI bus enumeration. This fixes up the -values after we have POST'ed the secondary display controller BIOS, which -may have incorrectly re-programmed the base registers the same as the -primary display controller (the case for identical S3 cards). -****************************************************************************/ -static void _PCI_fixupSecondaryBARs(void) -{ - int i; - - for (i = 0; i < NumDevices; i++) { - PCI_writePCIRegL(0x10,PCI[DeviceIndex[i]].BaseAddress10,i); - PCI_writePCIRegL(0x14,PCI[DeviceIndex[i]].BaseAddress14,i); - PCI_writePCIRegL(0x18,PCI[DeviceIndex[i]].BaseAddress18,i); - PCI_writePCIRegL(0x1C,PCI[DeviceIndex[i]].BaseAddress1C,i); - PCI_writePCIRegL(0x20,PCI[DeviceIndex[i]].BaseAddress20,i); - PCI_writePCIRegL(0x24,PCI[DeviceIndex[i]].BaseAddress24,i); - } -} - -/**************************************************************************** -RETURNS: -True if successfully initialised, false if not. - -REMARKS: -This function executes the BIOS POST code on the controller. We assume that -at this stage the controller has its I/O and memory space enabled and -that all other controllers are in a disabled state. -****************************************************************************/ -static void PCI_doBIOSPOST( - int device, - ulong BIOSPhysAddr, - void *mappedBIOS, - ulong BIOSLen) -{ - RMREGS regs; - RMSREGS sregs; - - /* Determine the value to store in AX for BIOS POST */ - regs.x.ax = (u16)(PCI[DeviceIndex[device]].slot.i >> 8); - if (useV86) { - /* Post the BIOS using the PM functions (ie: v86 mode on Linux) */ - if (!PM_doBIOSPOST(regs.x.ax,BIOSPhysAddr,mappedBIOS,BIOSLen)) { - /* If the PM function fails, this probably means are we are on */ - /* DOS and can't re-map the real mode 0xC0000 region. In thise */ - /* case if the device is the primary, we can use the real */ - /* BIOS at 0xC0000 directly. */ - if (device == 0) - PM_doBIOSPOST(regs.x.ax,0xC0000,mappedBIOS,BIOSLen); - } - } - else { - /* Setup the X86 emulator for the VGA BIOS */ - BE_setVGA(&VGAInfo[device]); - - /* Execute the BIOS POST code */ - BE_callRealMode(0xC000,0x0003,®s,&sregs); - - /* Cleanup and exit */ - BE_getVGA(&VGAInfo[device]); - } -} - -/**************************************************************************** -RETURNS: -True if successfully initialised, false if not. - -REMARKS: -Loads and POST's the secondary controllers BIOS, directly from the BIOS -image we can extract over the PCI bus. -****************************************************************************/ -static ibool PCI_postControllers(void) -{ - int device; - ulong BIOSImageLen,mappedBIOSPhys; - uchar *mappedBIOS,*copyOfBIOS; - char filename[_MAX_PATH]; - FILE *f; - - /* Disable the primary display controller and AGP VGA pass-through */ - DISABLE_DEVICE(0); - if (AGPBridge) - DISABLE_AGP_VGA(); - - /* Now POST all the secondary controllers */ - for (device = 0; device < NumDevices; device++) { - /* Skip the device if it is not enabled (probably an ISA device) */ - if (DeviceIndex[device] == -1) - continue; - - /* Enable secondary display controller. If the secondary controller */ - /* is on the AGP bus, then enable VGA resources for the AGP device. */ - ENABLE_DEVICE(device); - if (AGPBridge && AGPBridge->SecondayBusNumber == PCI[DeviceIndex[device]].slot.p.Bus) - ENABLE_AGP_VGA(); - - /* Check if the controller has already been POST'ed */ - if (VGA_NOT_ACTIVE()) { - /* Find a viable place to map the secondary PCI BIOS image and map it */ - printk("Device %d not enabled, so attempting warm boot it\n", device); - - /* For AGP devices (and PCI devices that do have the ROM base */ - /* address zero'ed out) we have to map the BIOS to a location */ - /* that is passed by the AGP bridge to the bus. Some AGP devices */ - /* have the ROM base address already set up for us, and some */ - /* do not (we map to one of the existing BAR locations in */ - /* this case). */ - mappedBIOS = NULL; - if (PCI[DeviceIndex[device]].ROMBaseAddress != 0) - mappedBIOSPhys = PCI[DeviceIndex[device]].ROMBaseAddress & ~0xF; - else - mappedBIOSPhys = PCI_findBIOSAddr(device); - printk("Mapping BIOS image to 0x%08X\n", mappedBIOSPhys); - mappedBIOS = PM_mapPhysicalAddr(mappedBIOSPhys,MAX_BIOSLEN-1,false); - PCI_writePCIRegL(0x30,mappedBIOSPhys | 0x1,device); - BIOSImageLen = mappedBIOS[2] * 512; - if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) - return false; - memcpy(copyOfBIOS,mappedBIOS,BIOSImageLen); - PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1); - - /* Allocate memory to store copy of BIOS from secondary controllers */ - VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]]; - VGAInfo[device].BIOSImage = copyOfBIOS; - VGAInfo[device].BIOSImageLen = BIOSImageLen; - - /* Restore device mappings */ - PCI_writePCIRegL(0x30,PCI[DeviceIndex[device]].ROMBaseAddress,device); - PCI_writePCIRegL(0x10,PCI[DeviceIndex[device]].BaseAddress10,device); - PCI_writePCIRegL(0x14,PCI[DeviceIndex[device]].BaseAddress14,device); - - /* Now execute the BIOS POST for the device */ - if (copyOfBIOS[0] == 0x55 && copyOfBIOS[1] == 0xAA) { - printk("Executing BIOS POST for controller.\n"); - PCI_doBIOSPOST(device,mappedBIOSPhys,copyOfBIOS,BIOSImageLen); - } - - /* Reset the size of the BIOS image to the final size */ - VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN; - - /* Save the BIOS and interrupt vector information to disk */ - sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device); - if ((f = fopen(filename,"wb")) != NULL) { - fwrite(copyOfBIOS,1,FINAL_BIOSLEN,f); - fwrite(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f); - fclose(f); - } - } - else { - /* Allocate memory to store copy of BIOS from secondary controllers */ - if ((copyOfBIOS = malloc(FINAL_BIOSLEN)) == NULL) - return false; - VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]]; - VGAInfo[device].BIOSImage = copyOfBIOS; - VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN; - - /* Load the BIOS and interrupt vector information from disk */ - sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device); - if ((f = fopen(filename,"rb")) != NULL) { - fread(copyOfBIOS,1,FINAL_BIOSLEN,f); - fread(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f); - fclose(f); - } - } - - /* Fix up all the secondary PCI base address registers */ - /* (restores them all from the values we read previously) */ - _PCI_fixupSecondaryBARs(); - - /* Disable the secondary controller and AGP VGA pass-through */ - DISABLE_DEVICE(device); - if (AGPBridge) - DISABLE_AGP_VGA(); - } - - /* Reenable primary display controller and reset AGP bridge control */ - if (AGPBridge) - RESTORE_AGP_VGA(); - ENABLE_DEVICE(0); - - /* Free physical BIOS image mapping */ - PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1); - - /* Restore the X86 emulator BIOS info to primary controller */ - if (!useV86) - BE_setVGA(&VGAInfo[0]); - return true; -} - -/**************************************************************************** -REMARKS: -Enumerates the PCI bus and dumps the PCI configuration information to the -log file. -****************************************************************************/ -static void EnumeratePCI(void) -{ - int i,index; - PCIBridgeInfo *info; - - printk("Displaying enumeration of PCI bus (%d devices, %d display devices)\n", - NumPCI, NumDevices); - for (index = 0; index < NumDevices; index++) - printk(" Display device %d is PCI device %d\n",index,DeviceIndex[index]); - printk("\n"); - printk("Bus Slot Fnc DeviceID SubSystem Rev Class IRQ Int Cmd\n"); - for (i = 0; i < NumPCI; i++) { - printk("%2d %2d %2d %04X:%04X %04X:%04X %02X %02X:%02X %02X %02X %04X ", - PCI[i].slot.p.Bus, - PCI[i].slot.p.Device, - PCI[i].slot.p.Function, - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].SubSystemVendorID, - PCI[i].SubSystemID, - PCI[i].RevID, - PCI[i].BaseClass, - PCI[i].SubClass, - PCI[i].InterruptLine, - PCI[i].InterruptPin, - PCI[i].Command); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printk("<- %d\n", index); - else - printk("\n"); - } - printk("\n"); - printk("DeviceID Stat Ifc Cch Lat Hdr BIST\n"); - for (i = 0; i < NumPCI; i++) { - printk("%04X:%04X %04X %02X %02X %02X %02X %02X ", - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].Status, - PCI[i].Interface, - PCI[i].CacheLineSize, - PCI[i].LatencyTimer, - PCI[i].HeaderType, - PCI[i].BIST); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printk("<- %d\n", index); - else - printk("\n"); - } - printk("\n"); - printk("DeviceID Base10h Base14h Base18h Base1Ch Base20h Base24h ROMBase\n"); - for (i = 0; i < NumPCI; i++) { - printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ", - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].BaseAddress10, - PCI[i].BaseAddress14, - PCI[i].BaseAddress18, - PCI[i].BaseAddress1C, - PCI[i].BaseAddress20, - PCI[i].BaseAddress24, - PCI[i].ROMBaseAddress); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printk("<- %d\n", index); - else - printk("\n"); - } - printk("\n"); - printk("DeviceID BAR10Len BAR14Len BAR18Len BAR1CLen BAR20Len BAR24Len ROMLen\n"); - for (i = 0; i < NumPCI; i++) { - printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ", - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].BaseAddress10Len, - PCI[i].BaseAddress14Len, - PCI[i].BaseAddress18Len, - PCI[i].BaseAddress1CLen, - PCI[i].BaseAddress20Len, - PCI[i].BaseAddress24Len, - PCI[i].ROMBaseAddressLen); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printk("<- %d\n", index); - else - printk("\n"); - } - printk("\n"); - printk("Displaying enumeration of %d bridge devices\n",NumBridges); - printk("\n"); - printk("DeviceID P# S# B# IOB IOL MemBase MemLimit PreBase PreLimit Ctrl\n"); - for (i = 0; i < NumBridges; i++) { - info = (PCIBridgeInfo*)&PCI[BridgeIndex[i]]; - printk("%04X:%04X %02X %02X %02X %04X %04X %08X %08X %08X %08X %04X\n", - info->VendorID, - info->DeviceID, - info->PrimaryBusNumber, - info->SecondayBusNumber, - info->SubordinateBusNumber, - ((u16)info->IOBase << 8) & 0xF000, - info->IOLimit ? - ((u16)info->IOLimit << 8) | 0xFFF : 0, - ((u32)info->MemoryBase << 16) & 0xFFF00000, - info->MemoryLimit ? - ((u32)info->MemoryLimit << 16) | 0xFFFFF : 0, - ((u32)info->PrefetchableMemoryBase << 16) & 0xFFF00000, - info->PrefetchableMemoryLimit ? - ((u32)info->PrefetchableMemoryLimit << 16) | 0xFFFFF : 0, - info->BridgeControl); - } - printk("\n"); -} - -/**************************************************************************** -RETURNS: -Number of display devices found. - -REMARKS: -This function enumerates the number of available display devices on the -PCI bus, and returns the number found. -****************************************************************************/ -static int PCI_enumerateDevices(void) -{ - int i,j; - PCIBridgeInfo *info; - - /* If this is the first time we have been called, enumerate all */ - /* devices on the PCI bus. */ - if (NumPCI == -1) { - for (i = 0; i < MAX_PCI_DEVICES; i++) - PCI[i].dwSize = sizeof(PCI[i]); - if ((NumPCI = PCI_enumerate(PCI,MAX_PCI_DEVICES)) == 0) - return -1; - - /* Build a list of all PCI bridge devices */ - for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) { - if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) { - if (NumBridges < MAX_PCI_DEVICES) - BridgeIndex[NumBridges++] = i; - } - } - - /* Now build a list of all display class devices */ - for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) { - if (PCI_IS_DISPLAY_CLASS(&PCI[i])) { - if ((PCI[i].Command & 0x3) == 0x3) { - DeviceIndex[0] = i; - } - else { - if (NumDevices < MAX_PCI_DEVICES) - DeviceIndex[NumDevices++] = i; - } - if (PCI[i].slot.p.Bus != 0) { - /* This device is on a different bus than the primary */ - /* PCI bus, so it is probably an AGP device. Find the */ - /* AGP bus device that controls that bus so we can */ - /* control it. */ - for (j = 0; j < NumBridges; j++) { - info = (PCIBridgeInfo*)&PCI[BridgeIndex[j]]; - if (info->SecondayBusNumber == PCI[i].slot.p.Bus) { - AGPBridge = info; - break; - } - } - } - } - } - - /* Enumerate all PCI and bridge devices to log file */ - EnumeratePCI(); - } - return NumDevices; -} - -FILE *logfile; - -void printk(const char *fmt, ...) -{ - va_list argptr; - va_start(argptr, fmt); - vfprintf(logfile, fmt, argptr); - fflush(logfile); - va_end(argptr); -} - -int main(int argc,char *argv[]) -{ - while (argc > 1) { - if (stricmp(argv[1],"-usev86") == 0) { - useV86 = true; - } - else if (stricmp(argv[1],"-force") == 0) { - forcePost = true; - } -#ifdef DEBUG - else if (stricmp(argv[1],"-decode") == 0) { - debugFlags |= DEBUG_DECODE_F; - } - else if (stricmp(argv[1],"-iotrace") == 0) { - debugFlags |= DEBUG_IO_TRACE_F; - } -#endif - else { - printf("Usage: warmboot [-usev86] [-force] [-decode] [-iotrace]\n"); - exit(-1); - } - argc--; - argv++; - } - if ((logfile = fopen("warmboot.log","w")) == NULL) - exit(1); - - PM_init(); - if (!useV86) { - /* Initialise the x86 BIOS emulator */ - BE_init(false,debugFlags,65536,&VGAInfo[0]); - } - - /* Enumerate all devices (which POST's them at the same time) */ - if (PCI_enumerateDevices() < 1) { - printk("No PCI display devices found!\n"); - return -1; - } - - /* Post all the display controller BIOS'es */ - PCI_postControllers(); - - /* Cleanup and exit the emulator */ - if (!useV86) - BE_exit(); - fclose(logfile); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm deleted file mode 100644 index 61a9024..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm +++ /dev/null @@ -1,51 +0,0 @@ -;**************************************************************************** -;* -;* SciTech Nucleus Audio Architecture -;* -;* Copyright (C) 1991-1998 SciTech Software, Inc. -;* All rights reserved. -;* -;* ====================================================================== -;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -;* | | -;* |This copyrighted computer code contains proprietary technology | -;* |owned by SciTech Software, Inc., located at 505 Wall Street, | -;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -;* | | -;* |The contents of this file are subject to the SciTech Nucleus | -;* |License; you may *not* use this file or related software except in | -;* |compliance with the License. You may obtain a copy of the License | -;* |at http://www.scitechsoft.com/nucleus-license.txt | -;* | | -;* |Software distributed under the License is distributed on an | -;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -;* |implied. See the License for the specific language governing | -;* |rights and limitations under the License. | -;* | | -;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -;* ====================================================================== -;* -;* Language: TASM 4.0 or NASM -;* Environment: IBM PC 32 bit Protected Mode. -;* -;* Description: Module to implement the import stubs for all the Nucleus -;* Audio API functions for Intel binary compatible drivers. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -BEGIN_IMPORTS_DEF _AA_exports -SKIP_IMP AA_status ; Implemented in C code -SKIP_IMP AA_errorMsg ; Implemented in C code -SKIP_IMP AA_getDaysLeft ; Implemented in C code -SKIP_IMP AA_registerLicense ; Implemented in C code -SKIP_IMP AA_enumerateDevices ; Implemented in C code -SKIP_IMP AA_loadDriver ; Implemented in C code -DECLARE_IMP AA_unloadDriver -DECLARE_IMP AA_saveOptions -END_IMPORTS_DEF - - END diff --git a/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm deleted file mode 100644 index 5317600..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm +++ /dev/null @@ -1,136 +0,0 @@ -;**************************************************************************** -;* -;* SciTech Nucleus Graphics Architecture -;* -;* Copyright (C) 1991-1998 SciTech Software, Inc. -;* All rights reserved. -;* -;* ====================================================================== -;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -;* | | -;* |This copyrighted computer code contains proprietary technology | -;* |owned by SciTech Software, Inc., located at 505 Wall Street, | -;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -;* | | -;* |The contents of this file are subject to the SciTech Nucleus | -;* |License; you may *not* use this file or related software except in | -;* |compliance with the License. You may obtain a copy of the License | -;* |at http://www.scitechsoft.com/nucleus-license.txt | -;* | | -;* |Software distributed under the License is distributed on an | -;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -;* |implied. See the License for the specific language governing | -;* |rights and limitations under the License. | -;* | | -;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -;* ====================================================================== -;* -;* Language: TASM 4.0 or NASM -;* Environment: IBM PC 32 bit Protected Mode. -;* -;* Description: Module to implement the import stubs for all the Nucleus -;* Graphics API functions for Intel binary compatible drivers. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -BEGIN_IMPORTS_DEF __GA_exports -SKIP_IMP GA_status,0 ; Implemented in C code -SKIP_IMP GA_errorMsg,1 ; Implemented in C code -SKIP_IMP GA_getDaysLeft,1 ; Implemented in C code -SKIP_IMP GA_registerLicense,2 ; Implemented in C code -SKIP_IMP GA_enumerateDevices,1 ; Implemented in C code -SKIP_IMP GA_loadDriver,2 ; Implemented in C code -DECLARE_IMP GA_setActiveDevice,1 -SKIP_IMP GA_reserved1,0 ; Implemented in C code -DECLARE_IMP GA_unloadDriver,1 -DECLARE_IMP REF2D_loadDriver,6 -DECLARE_IMP REF2D_unloadDriver,2 -DECLARE_IMP GA_loadRef2d,5 -DECLARE_IMP GA_unloadRef2d,1 -DECLARE_IMP GA_softStereoInit,1 -DECLARE_IMP GA_softStereoOn,0 -DECLARE_IMP GA_softStereoScheduleFlip,2 -DECLARE_IMP GA_softStereoGetFlipStatus,0 -DECLARE_IMP GA_softStereoWaitTillFlipped,0 -DECLARE_IMP GA_softStereoOff,0 -DECLARE_IMP GA_softStereoExit,0 -DECLARE_IMP GA_saveModeProfile,2 -DECLARE_IMP GA_saveOptions,2 -DECLARE_IMP GA_saveCRTCTimings,1 -DECLARE_IMP GA_restoreCRTCTimings,1 -DECLARE_IMP DDC_init,1 -DECLARE_IMP DDC_readEDID,5 -DECLARE_IMP EDID_parse,3 -DECLARE_IMP MCS_begin,1 -DECLARE_IMP MCS_getCapabilitiesString,2 -DECLARE_IMP MCS_isControlSupported,1 -DECLARE_IMP MCS_enableControl,2 -DECLARE_IMP MCS_getControlMax,2 -DECLARE_IMP MCS_getControlValue,2 -DECLARE_IMP MCS_getControlValues,3 -DECLARE_IMP MCS_setControlValue,2 -DECLARE_IMP MCS_setControlValues,3 -DECLARE_IMP MCS_resetControl,1 -DECLARE_IMP MCS_saveCurrentSettings,0 -DECLARE_IMP MCS_getTimingReport,3 -DECLARE_IMP MCS_getSelfTestReport,3 -DECLARE_IMP MCS_end,0 -SKIP_IMP GA_loadInGUI,1 ; Implemented in C code -DECLARE_IMP DDC_writeEDID,6 -DECLARE_IMP GA_useDoubleScan,1 -DECLARE_IMP GA_getMaxRefreshRate,4 -DECLARE_IMP GA_computeCRTCTimings,6 -DECLARE_IMP GA_addMode,5 -DECLARE_IMP GA_addRefresh,5 -DECLARE_IMP GA_delMode,5 -DECLARE_IMP N_getLogName,0 -SKIP_IMP2 N_log -DECLARE_IMP MDBX_getErrCode,0 -DECLARE_IMP MDBX_getErrorMsg,0 -DECLARE_IMP MDBX_open,1 -DECLARE_IMP MDBX_close,0 -DECLARE_IMP MDBX_first,1 -DECLARE_IMP MDBX_last,1 -DECLARE_IMP MDBX_next,1 -DECLARE_IMP MDBX_prev,1 -DECLARE_IMP MDBX_insert,1 -DECLARE_IMP MDBX_update,1 -DECLARE_IMP MDBX_flush,0 -DECLARE_IMP MDBX_importINF,2 -SKIP_IMP GA_getGlobalOptions,2 ; Implemented in C code -DECLARE_IMP GA_setGlobalOptions,1 -DECLARE_IMP GA_saveGlobalOptions,1 -DECLARE_IMP GA_getInternalName,1 -DECLARE_IMP GA_getNucleusConfigPath,0 -DECLARE_IMP GA_getFakePCIID,0 -SKIP_IMP GA_loadLibrary,3 ; Implemented in C code -SKIP_IMP GA_isOEMVersion,1 ; Implemented in C code -DECLARE_IMP GA_isLiteVersion,1 -DECLARE_IMP GA_getDisplaySerialNo,1 -DECLARE_IMP GA_getDisplayUserName,1 -SKIP_IMP GA_getCurrentDriver,1 ; Implemented in C code -SKIP_IMP GA_getCurrentRef2d,1 ; Implemented in C code -SKIP_IMP GA_getLicensedDevices,1 ; Implemented in C code -DECLARE_IMP DDC_initExt,2 -DECLARE_IMP MCS_beginExt,2 -DECLARE_IMP GA_loadRegionMgr,3 -DECLARE_IMP GA_unloadRegionMgr,1 -DECLARE_IMP GA_getProcAddress,2 -DECLARE_IMP GA_enableVBEMode,5 -DECLARE_IMP GA_disableVBEMode,5 -DECLARE_IMP GA_loadModeProfile,2 -DECLARE_IMP GA_getCRTCTimings,4 -DECLARE_IMP GA_setCRTCTimings,4 -DECLARE_IMP GA_setDefaultRefresh,6 -DECLARE_IMP GA_saveMonitorInfo,2 -DECLARE_IMP GA_detectPnPMonitor,3 -SKIP_IMP3 GA_queryFunctions -SKIP_IMP3 REF2D_queryFunctions -END_IMPORTS_DEF - - END - diff --git a/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm b/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm deleted file mode 100644 index 0194a62..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm +++ /dev/null @@ -1,248 +0,0 @@ -;**************************************************************************** -;* -;* SciTech Nucleus Graphics Architecture -;* -;* Copyright (C) 1991-1998 SciTech Software, Inc. -;* All rights reserved. -;* -;* ====================================================================== -;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -;* | | -;* |This copyrighted computer code contains proprietary technology | -;* |owned by SciTech Software, Inc., located at 505 Wall Street, | -;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -;* | | -;* |The contents of this file are subject to the SciTech Nucleus | -;* |License; you may *not* use this file or related software except in | -;* |compliance with the License. You may obtain a copy of the License | -;* |at http://www.scitechsoft.com/nucleus-license.txt | -;* | | -;* |Software distributed under the License is distributed on an | -;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -;* |implied. See the License for the specific language governing | -;* |rights and limitations under the License. | -;* | | -;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -;* ====================================================================== -;* -;* Language: 80386 Assembler, NASM or TASM -;* Environment: IBM PC 32 bit Protected Mode. -;* -;* Description: Assembly support functions for the Nucleus library for -;* the high resolution timing support functions provided by -;* the Intel Pentium and compatible processors. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _gatimer - -begcodeseg _gatimer - -ifdef USE_NASM -%macro mCPU_ID 0 -db 00Fh,0A2h -%endmacro -else -MACRO mCPU_ID -db 00Fh,0A2h -ENDM -endif - -ifdef USE_NASM -%macro mRDTSC 0 -db 00Fh,031h -%endmacro -else -MACRO mRDTSC -db 00Fh,031h -ENDM -endif - -;---------------------------------------------------------------------------- -; bool _GA_haveCPUID(void) -;---------------------------------------------------------------------------- -; Determines if we have support for the CPUID instruction. -;---------------------------------------------------------------------------- -cprocstart _GA_haveCPUID - - enter_c - pushfd ; Get original EFLAGS - pop eax - mov ecx, eax - xor eax, 200000h ; Flip ID bit in EFLAGS - push eax ; Save new EFLAGS value on stack - popfd ; Replace current EFLAGS value - pushfd ; Get new EFLAGS - pop eax ; Store new EFLAGS in EAX - xor eax, ecx ; Can not toggle ID bit, - jnz @@1 ; Processor=80486 - mov eax,0 ; We dont have CPUID support - jmp @@Done -@@1: mov eax,1 ; We have CPUID support -@@Done: leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; uint _GA_getCPUIDFeatures(void) -;---------------------------------------------------------------------------- -; Determines the CPU type using the CPUID instruction. -;---------------------------------------------------------------------------- -cprocstart _GA_getCPUIDFeatures - - enter_c - - xor eax, eax ; Set up for CPUID instruction - mCPU_ID ; Get and save vendor ID - cmp eax, 1 ; Make sure 1 is valid input for CPUID - jl @@Fail ; We dont have the CPUID instruction - xor eax, eax - inc eax - mCPU_ID ; Get family/model/stepping/features - mov eax, edx -@@Done: leave_c - ret - -@@Fail: xor eax,eax - jmp @@Done - -cprocend - -;---------------------------------------------------------------------------- -; void _GA_readTimeStamp(GA_largeInteger *time) -;---------------------------------------------------------------------------- -; Reads the time stamp counter and returns the 64-bit result. -;---------------------------------------------------------------------------- -cprocstart _GA_readTimeStamp - - mRDTSC - mov ecx,[esp+4] ; Access directly without stack frame - mov [ecx],eax - mov [ecx+4],edx - ret - -cprocend - -;---------------------------------------------------------------------------- -; N_uint32 GA_TimerDifference(GA_largeInteger *a,GA_largeInteger *b) -;---------------------------------------------------------------------------- -; Computes the difference between two 64-bit numbers (a-b) -;---------------------------------------------------------------------------- -cprocstart GA_TimerDifference - - ARG a:DPTR, b:DPTR, t:DPTR - - enter_c - - mov ecx,[a] - mov eax,[ecx] ; EAX := b.low - mov ecx,[b] - sub eax,[ecx] - mov edx,eax ; EDX := low difference - mov ecx,[a] - mov eax,[ecx+4] ; ECX := b.high - mov ecx,[b] - sbb eax,[ecx+4] ; EAX := high difference - mov eax,edx ; Return low part - - leave_c - ret - -cprocend - -; Macro to delay briefly to ensure that enough time has elapsed between -; successive I/O accesses so that the device being accessed can respond -; to both accesses even on a very fast PC. - -ifdef USE_NASM -%macro DELAY_TIMER 0 - jmp short $+2 - jmp short $+2 - jmp short $+2 -%endmacro -else -macro DELAY_TIMER - jmp short $+2 - jmp short $+2 - jmp short $+2 -endm -endif - -;---------------------------------------------------------------------------- -; void _OS_delay8253(N_uint32 microSeconds); -;---------------------------------------------------------------------------- -; Delays for the specified number of microseconds, by directly programming -; the 8253 timer chips. -;---------------------------------------------------------------------------- -cprocstart _OS_delay8253 - - ARG microSec:UINT - - enter_c - -; Start timer 2 counting - - mov _ax,[microSec] ; EAX := count in microseconds - mov ecx,1196 - mul ecx - mov ecx,1000 - div ecx - mov ecx,eax ; ECX := count in timer ticks - in al,61h - or al,1 - out 61h,al - -; Set the timer 2 count to 0 again to start the timing interval. - - mov al,10110100b ; set up to load initial (timer 2) - out 43h,al ; timer count - DELAY_TIMER - sub al,al - out 42h,al ; load count lsb - DELAY_TIMER - out 42h,al ; load count msb - xor di,di ; Allow max 64K loop iterations - -@@LoopStart: - dec di ; This is a guard against the possibility that - jz @@LoopEnd ; someone eg. stopped the timer behind our back. - ; After 64K iterations we bail out no matter what - ; (and hope it wasn't too soon) - mov al,00000000b ; latch timer 0 - out 43h,al - DELAY_TIMER - in al,42h ; least significant byte - DELAY_TIMER - mov ah,al - in al,42h ; most significant byte - xchg ah,al - neg ax ; Convert from countdown remaining - ; to elapsed count - cmp ax,cx ; Has delay expired? - jb @@LoopStart ; No, so loop till done - -; Stop timer 2 from counting -@@LoopEnd: - in al,61H - and al,0FEh - out 61H,al - -; Some programs have a problem if we change the control port; better change it -; to something they expect (mode 3 - square wave generator)... - mov al,0B6h - out 43h,al - - leave_c - ret - -cprocend - -endcodeseg _gatimer - - END - diff --git a/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm deleted file mode 100644 index d4b1179..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm +++ /dev/null @@ -1,195 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* Copyright (C) 1991-1998 SciTech Software, Inc. -;* All rights reserved. -;* -;* ====================================================================== -;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -;* | | -;* |This copyrighted computer code contains proprietary technology | -;* |owned by SciTech Software, Inc., located at 505 Wall Street, | -;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -;* | | -;* |The contents of this file are subject to the SciTech Nucleus | -;* |License; you may *not* use this file or related software except in | -;* |compliance with the License. You may obtain a copy of the License | -;* |at http://www.scitechsoft.com/nucleus-license.txt | -;* | | -;* |Software distributed under the License is distributed on an | -;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -;* |implied. See the License for the specific language governing | -;* |rights and limitations under the License. | -;* | | -;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -;* ====================================================================== -;* -;* Language: TASM 4.0 or NASM -;* Environment: IBM PC 32 bit Protected Mode. -;* -;* Description: Module to implement the import stubs for all the PM -;* API functions for Intel binary portable drivers. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -BEGIN_IMPORTS_DEF _PM_imports -DECLARE_IMP PM_getModeType,0 -DECLARE_IMP PM_getBIOSPointer,0 -DECLARE_IMP PM_getA0000Pointer,0 -DECLARE_IMP PM_mapPhysicalAddr,0 -DECLARE_IMP PM_mallocShared,0 -SKIP_IMP _PM_reserved1,0 -DECLARE_IMP PM_freeShared,0 -DECLARE_IMP PM_mapToProcess,0 -DECLARE_IMP PM_mapRealPointer,0 -DECLARE_IMP PM_allocRealSeg,0 -DECLARE_IMP PM_freeRealSeg,0 -DECLARE_IMP PM_allocLockedMem,0 -DECLARE_IMP PM_freeLockedMem,0 -DECLARE_IMP PM_callRealMode,0 -DECLARE_IMP PM_int86,0 -DECLARE_IMP PM_int86x,0 -DECLARE_IMP DPMI_int86,0 -DECLARE_IMP PM_availableMemory,0 -DECLARE_IMP PM_getVESABuf,0 -DECLARE_IMP PM_getOSType,0 -DECLARE_IMP PM_fatalError,0 -DECLARE_IMP PM_setBankA,0 -DECLARE_IMP PM_setBankAB,0 -DECLARE_IMP PM_setCRTStart,0 -DECLARE_IMP PM_getCurrentPat,0 -DECLARE_IMP PM_getVBEAFPath,0 -DECLARE_IMP PM_getNucleusPath,0 -DECLARE_IMP PM_getNucleusConfigPath,0 -DECLARE_IMP PM_getUniqueID,0 -DECLARE_IMP PM_getMachineName,0 -DECLARE_IMP VF_available,0 -DECLARE_IMP VF_init,0 -DECLARE_IMP VF_exit,0 -DECLARE_IMP PM_openConsole,0 -DECLARE_IMP PM_getConsoleStateSize,0 -DECLARE_IMP PM_saveConsoleState,0 -DECLARE_IMP PM_restoreConsoleState,0 -DECLARE_IMP PM_closeConsole,0 -DECLARE_IMP PM_setOSCursorLocation,0 -DECLARE_IMP PM_setOSScreenWidth,0 -DECLARE_IMP PM_enableWriteCombine,0 -DECLARE_IMP PM_backslash,0 -DECLARE_IMP PM_lockDataPages,0 -DECLARE_IMP PM_unlockDataPages,0 -DECLARE_IMP PM_lockCodePages,0 -DECLARE_IMP PM_unlockCodePages,0 -DECLARE_IMP PM_setRealTimeClockHandler,0 -DECLARE_IMP PM_setRealTimeClockFrequency,0 -DECLARE_IMP PM_restoreRealTimeClockHandler,0 -DECLARE_IMP PM_doBIOSPOST,0 -DECLARE_IMP PM_getBootDrive,0 -DECLARE_IMP PM_freePhysicalAddr,0 -DECLARE_IMP PM_inpb,0 -DECLARE_IMP PM_inpw,0 -DECLARE_IMP PM_inpd,0 -DECLARE_IMP PM_outpb,0 -DECLARE_IMP PM_outpw,0 -DECLARE_IMP PM_outpd,0 -SKIP_IMP _PM_reserved2,0 -DECLARE_IMP PM_setSuspendAppCallback,0 -DECLARE_IMP PM_haveBIOSAccess,0 -DECLARE_IMP PM_kbhit,0 -DECLARE_IMP PM_getch,0 -DECLARE_IMP PM_findBPD,0 -DECLARE_IMP PM_getPhysicalAddr,0 -DECLARE_IMP PM_sleep,0 -DECLARE_IMP PM_getCOMPort,0 -DECLARE_IMP PM_getLPTPort,0 -DECLARE_IMP PM_loadLibrary,0 -DECLARE_IMP PM_getProcAddress,0 -DECLARE_IMP PM_freeLibrary,0 -DECLARE_IMP PCI_enumerate,0 -DECLARE_IMP PCI_accessReg,0 -DECLARE_IMP PCI_setHardwareIRQ,0 -DECLARE_IMP PCI_generateSpecialCyle,0 -SKIP_IMP _PM_reserved3,0 -DECLARE_IMP PCIBIOS_getEntry,0 -DECLARE_IMP CPU_getProcessorType,0 -DECLARE_IMP CPU_haveMMX,0 -DECLARE_IMP CPU_have3DNow,0 -DECLARE_IMP CPU_haveSSE,0 -DECLARE_IMP CPU_haveRDTSC,0 -DECLARE_IMP CPU_getProcessorSpeed,0 -DECLARE_IMP ZTimerInit,0 -DECLARE_IMP LZTimerOn,0 -DECLARE_IMP LZTimerLap,0 -DECLARE_IMP LZTimerOff,0 -DECLARE_IMP LZTimerCount,0 -DECLARE_IMP LZTimerOnExt,0 -DECLARE_IMP LZTimerLapExt,0 -DECLARE_IMP LZTimerOffExt,0 -DECLARE_IMP LZTimerCountExt,0 -DECLARE_IMP ULZTimerOn,0 -DECLARE_IMP ULZTimerLap,0 -DECLARE_IMP ULZTimerOff,0 -DECLARE_IMP ULZTimerCount,0 -DECLARE_IMP ULZReadTime,0 -DECLARE_IMP ULZElapsedTime,0 -DECLARE_IMP ULZTimerResolution,0 -DECLARE_IMP PM_findFirstFile,0 -DECLARE_IMP PM_findNextFile,0 -DECLARE_IMP PM_findClose,0 -DECLARE_IMP PM_makepath,0 -DECLARE_IMP PM_splitpath,0 -DECLARE_IMP PM_driveValid,0 -DECLARE_IMP PM_getdcwd,0 -DECLARE_IMP PM_setFileAttr,0 -DECLARE_IMP PM_mkdir,0 -DECLARE_IMP PM_rmdir,0 -DECLARE_IMP PM_getFileAttr,0 -DECLARE_IMP PM_getFileTime,0 -DECLARE_IMP PM_setFileTime,0 -DECLARE_IMP CPU_getProcessorName,0 -DECLARE_IMP PM_getVGAStateSize,0 -DECLARE_IMP PM_saveVGAState,0 -DECLARE_IMP PM_restoreVGAState,0 -DECLARE_IMP PM_vgaBlankDisplay,0 -DECLARE_IMP PM_vgaUnblankDisplay,0 -DECLARE_IMP PM_blockUntilTimeout,0 -DECLARE_IMP _PM_add64,0 -DECLARE_IMP _PM_sub64,0 -DECLARE_IMP _PM_mul64,0 -DECLARE_IMP _PM_div64,0 -DECLARE_IMP _PM_shr64,0 -DECLARE_IMP _PM_sar64,0 -DECLARE_IMP _PM_shl64,0 -DECLARE_IMP _PM_neg64,0 -DECLARE_IMP PCI_findBARSize,0 -DECLARE_IMP PCI_readRegBlock,0 -DECLARE_IMP PCI_writeRegBlock,0 -DECLARE_IMP PM_flushTLB,0 -DECLARE_IMP PM_useLocalMalloc,0 -DECLARE_IMP PM_malloc,0 -DECLARE_IMP PM_calloc,0 -DECLARE_IMP PM_realloc,0 -DECLARE_IMP PM_free,0 -DECLARE_IMP PM_getPhysicalAddrRange,0 -DECLARE_IMP PM_allocPage,0 -DECLARE_IMP PM_freePage,0 -DECLARE_IMP PM_agpInit,0 -DECLARE_IMP PM_agpExit,0 -DECLARE_IMP PM_agpReservePhysical,0 -DECLARE_IMP PM_agpReleasePhysical,0 -DECLARE_IMP PM_agpCommitPhysical,0 -DECLARE_IMP PM_agpFreePhysical,0 -DECLARE_IMP PCI_getNumDevices,0 -DECLARE_IMP PM_setLocalBPDPath,0 -DECLARE_IMP PM_loadDirectDraw,0 -DECLARE_IMP PM_unloadDirectDraw,0 -DECLARE_IMP PM_getDirectDrawWindow,0 -DECLARE_IMP PM_doSuspendApp,0 -END_IMPORTS_DEF - - END - diff --git a/board/MAI/bios_emulator/scitech/src/common/aabeos.c b/board/MAI/bios_emulator/scitech/src/common/aabeos.c deleted file mode 100644 index ad5698a..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/aabeos.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Linux -* -* Description: OS specific Nucleus Graphics Architecture services for -* the Linux operating system. -* -****************************************************************************/ - -#include "nucleus/graphics.h" -#include - -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -GA_sharedInfo * NAPI GA_getSharedInfo( - int device) -{ - (void)device; - return NULL; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp) -{ - (void)gaExp; - return false; -} - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - haveRDTSC = true; - return true; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else { - struct timeval t; - gettimeofday(&t, NULL); - value->low = t.tv_sec*1000000 + t.tv_usec; - value->high = 0; - } -} diff --git a/board/MAI/bios_emulator/scitech/src/common/aados.c b/board/MAI/bios_emulator/scitech/src/common/aados.c deleted file mode 100644 index 342d2f3..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/aados.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: MSDOS -* -* Description: OS specific Nucleus Graphics Architecture services for -* the MSDOS operating system. -* -****************************************************************************/ - -#include "pm_help.h" -#include "pmapi.h" -#include -#include -#include - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the DOS -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - return true; - return false; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - _GA_readTimeStamp(value); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/aalib.c b/board/MAI/bios_emulator/scitech/src/common/aalib.c deleted file mode 100644 index 5003b22..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/aalib.c +++ /dev/null @@ -1,225 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Audio Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Any 32-bit protected mode environment -* -* Description: C module for the Graphics Accelerator Driver API. Uses -* the SciTech PM library for interfacing with DOS -* extender specific functions. -* -****************************************************************************/ - -#include "nucleus/audio.h" -#ifdef __WIN32_VXD__ -#include "sdd/sddhelp.h" -#else -#include -#include -#endif - -/*---------------------------- Global Variables ---------------------------*/ - -#ifdef TEST_HARNESS -extern PM_imports _VARAPI _PM_imports; -#else -AA_exports _VARAPI _AA_exports; -static int loaded = false; -static PE_MODULE *hModBPD = NULL; - -#ifdef __DRIVER__ -extern PM_imports _PM_imports; -#else -#include "pmimp.h" -#endif - -static N_imports _N_imports = { - sizeof(N_imports), - _OS_delay, - }; - -#ifdef __DRIVER__ -extern AA_imports _AA_imports; -#else -static AA_imports _AA_imports = { - sizeof(AA_imports), - }; -#endif -#endif - -/*----------------------------- Implementation ----------------------------*/ - -#define DLL_NAME "audio.bpd" - -#ifndef TEST_HARNESS -/**************************************************************************** -REMARKS: -Fatal error handler for non-exported AA_exports. -****************************************************************************/ -static void _AA_fatalErrorHandler(void) -{ - PM_fatalError("Unsupported Nucleus export function called! Please upgrade your copy of Nucleus!\n"); -} - -/**************************************************************************** -REMARKS: -Loads the Nucleus binary portable DLL into memory and initilises it. -****************************************************************************/ -static ibool LoadDriver(void) -{ - AA_initLibrary_t AA_initLibrary; - AA_exports *aaExp; - char filename[PM_MAX_PATH]; - char bpdpath[PM_MAX_PATH]; - int i,max; - ulong *p; - - /* Check if we have already loaded the driver */ - if (loaded) - return true; - PM_init(); - _AA_exports.dwSize = sizeof(_AA_exports); - - /* Open the BPD file */ - if (!PM_findBPD(DLL_NAME,bpdpath)) - return false; - strcpy(filename,bpdpath); - strcat(filename,DLL_NAME); - if ((hModBPD = PE_loadLibrary(filename,false)) == NULL) - return false; - if ((AA_initLibrary = (AA_initLibrary_t)PE_getProcAddress(hModBPD,"_AA_initLibrary")) == NULL) - return false; - bpdpath[strlen(bpdpath)-1] = 0; - if (strcmp(bpdpath,PM_getNucleusPath()) == 0) - strcpy(bpdpath,PM_getNucleusConfigPath()); - else { - PM_backslash(bpdpath); - strcat(bpdpath,"config"); - } - if ((aaExp = AA_initLibrary(bpdpath,filename,&_PM_imports,&_N_imports,&_AA_imports)) == NULL) - PM_fatalError("AA_initLibrary failed!\n"); - - /* Initialize all default imports to point to fatal error handler - * for upwards compatibility, and copy the exported functions. - */ - max = sizeof(_AA_exports)/sizeof(AA_initLibrary_t); - for (i = 0,p = (ulong*)&_AA_exports; i < max; i++) - *p++ = (ulong)_AA_fatalErrorHandler; - memcpy(&_AA_exports,aaExp,MIN(sizeof(_AA_exports),aaExp->dwSize)); - loaded = true; - return true; -} - -/* The following are stub entry points that the application calls to - * initialise the Nucleus loader library, and we use this to load our - * driver DLL from disk and initialise the library using it. - */ - -/* {secret} */ -int NAPI AA_status(void) -{ - if (!loaded) - return nDriverNotFound; - return _AA_exports.AA_status(); -} - -/* {secret} */ -const char * NAPI AA_errorMsg( - N_int32 status) -{ - if (!loaded) - return "Unable to load Nucleus device driver!"; - return _AA_exports.AA_errorMsg(status); -} - -/* {secret} */ -int NAPI AA_getDaysLeft(void) -{ - if (!LoadDriver()) - return -1; - return _AA_exports.AA_getDaysLeft(); -} - -/* {secret} */ -int NAPI AA_registerLicense(uchar *license) -{ - if (!LoadDriver()) - return 0; - return _AA_exports.AA_registerLicense(license); -} - -/* {secret} */ -int NAPI AA_enumerateDevices(void) -{ - if (!LoadDriver()) - return 0; - return _AA_exports.AA_enumerateDevices(); -} - -/* {secret} */ -AA_devCtx * NAPI AA_loadDriver(N_int32 deviceIndex) -{ - if (!LoadDriver()) - return NULL; - return _AA_exports.AA_loadDriver(deviceIndex); -} -#endif - -typedef struct { - N_uint32 low; - N_uint32 high; - } AA_largeInteger; - -void NAPI _OS_delay8253(N_uint32 microSeconds); -ibool NAPI _GA_haveCPUID(void); -uint NAPI _GA_getCPUIDFeatures(void); -void NAPI _GA_readTimeStamp(AA_largeInteger *time); -#define CPU_HaveRDTSC 0x00000010 - -/**************************************************************************** -REMARKS: -This function delays for the specified number of microseconds -****************************************************************************/ -void NAPI _OS_delay( - N_uint32 microSeconds) -{ - static ibool inited = false; - LZTimerObject tm; - - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { - if (!inited) { - ZTimerInit(); - inited = true; - } - LZTimerOnExt(&tm); - while (LZTimerLapExt(&tm) < microSeconds) - ; - LZTimerOnExt(&tm); - } - else - _OS_delay8253(microSeconds); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/aalinux.c b/board/MAI/bios_emulator/scitech/src/common/aalinux.c deleted file mode 100644 index d3d468e..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/aalinux.c +++ /dev/null @@ -1,94 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Linux -* -* Description: OS specific Nucleus Graphics Architecture services for -* the Linux operating system. -* -****************************************************************************/ - -#include "nucleus/graphics.h" -#include - -/*---------------------------- Global Variables ---------------------------*/ - -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -GA_sharedInfo * NAPI GA_getSharedInfo( - int device) -{ - (void)device; - return NULL; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp) -{ - (void)gaExp; - return false; -} - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - haveRDTSC = true; - return true; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else { - struct timeval t; - gettimeofday(&t, NULL); - value->low = t.tv_sec*1000000 + t.tv_usec; - value->high = 0; - } -} diff --git a/board/MAI/bios_emulator/scitech/src/common/aaos2.c b/board/MAI/bios_emulator/scitech/src/common/aaos2.c deleted file mode 100644 index 0ec8c9f..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/aaos2.c +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: OS/2 32-bit -* -* Description: OS specific Nucleus Graphics Architecture services for -* the OS/2 operating system environments. -* -****************************************************************************/ - -#include "pm_help.h" -#define INCL_DOSERRORS -#define INCL_DOS -#define INCL_SUB -#define INCL_VIO -#define INCL_KBD -#include - -/*---------------------------- Global Variables ---------------------------*/ - -static HFILE hSDDHelp; -static ulong outLen; /* Must not cross 64Kb boundary! */ -static ulong result; /* Must not cross 64Kb boundary! */ -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -REMARKS: -This function returns a pointer to the common graphics driver loaded in the -helper VxD. The memory for the VxD is shared between all processes via -the VxD, so that the VxD, 16-bit code and 32-bit code all see the same -state when accessing the graphics binary portable driver. -****************************************************************************/ -GA_sharedInfo * NAPI GA_getSharedInfo( - int device) -{ - /* Initialise the PM library and connect to our runtime DLL's */ - PM_init(); - - /* Open our helper device driver */ - if (DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0, - FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, - NULL)) - PM_fatalError("Unable to open SDDHELP$ helper device driver!"); - outLen = sizeof(result); - DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,PMHELP_GETSHAREDINFO, - NULL, 0, NULL, - &result, outLen, &outLen); - DosClose(hSDDHelp); - if (result) { - /* We have found the shared Nucleus packet. Because not all processes - * map to SDDPMI.DLL, we need to ensure that we connect to this - * DLL so that it gets mapped into our address space (that is - * where the shared Nucleus packet is located). Simply doing a - * DosLoadModule on it is enough for this. - */ - HMODULE hModSDDPMI; - char buf[80]; - DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"SDDPMI.DLL",&hModSDDPMI); - } - return (GA_sharedInfo*)result; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp) -{ - (void)gaExp; - return false; -} - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - haveRDTSC = true; - return true; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else - DosTmrQueryTime((QWORD*)value); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/aaqnx.c b/board/MAI/bios_emulator/scitech/src/common/aaqnx.c deleted file mode 100644 index 13531be..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/aaqnx.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: QNX -* -* Description: OS specific Nucleus Graphics Architecture services for -* the QNX operating system. -* -****************************************************************************/ - -#include "nucleus/graphics.h" -#include - -/*---------------------------- Global Variables ---------------------------*/ - -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -GA_sharedInfo * NAPI GA_getSharedInfo( - int device) -{ - (void)device; - return NULL; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp) -{ - (void)gaExp; - return false; -} - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - haveRDTSC = true; - return true; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else { - struct timespec ts; - - clock_gettime(CLOCK_REALTIME, &ts); - value->low = (ts.tv_nsec / 1000 + ts.tv_sec * 1000000); - value->high = 0; - } -} diff --git a/board/MAI/bios_emulator/scitech/src/common/aartt.c b/board/MAI/bios_emulator/scitech/src/common/aartt.c deleted file mode 100644 index 1a5a67a..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/aartt.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: RTTarget-32 -* -* Description: OS specific Nucleus Graphics Architecture services for -* the RTTarget-32 operating system environments. -* -****************************************************************************/ - -#include "nucleus/graphics.h" - -/*------------------------- Global Variables ------------------------------*/ - -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -GA_sharedInfo * NAPI GA_getSharedInfo( - int device) -{ - (void)device; - return NULL; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp) -{ - (void)gaExp; - return false; -} - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { - haveRDTSC = true; - return true; - } - return false; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/aasmx.c b/board/MAI/bios_emulator/scitech/src/common/aasmx.c deleted file mode 100644 index 163060f..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/aasmx.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: smx32 -* -* Description: OS specific Nucleus Graphics Architecture services for -* the smx32 platform -- no vxD support. -* -****************************************************************************/ - -#include "pmapi.h" -#include "nucleus/graphics.h" - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -GA_sharedInfo * NAPI GA_getSharedInfo( - int device) -{ - (void)device; - return NULL; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp) -{ - (void)gaExp; - return false; -} - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - return true; - return false; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - _GA_readTimeStamp(value); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/aavxd.c b/board/MAI/bios_emulator/scitech/src/common/aavxd.c deleted file mode 100644 index 221b02b..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/aavxd.c +++ /dev/null @@ -1,90 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Win32 VxD -* -* Description: OS specific Nucleus Graphics Architecture services for -* the Win32 VxD's. -* -****************************************************************************/ - -#include "sdd/sddhelp.h" - -/*------------------------- Global Variables ------------------------------*/ - -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -REMARKS: -Return the internal shared info structure. -****************************************************************************/ -GA_sharedInfo * NAPI GA_getSharedInfo( - int device) -{ - static GA_sharedInfo shared = {0,-1}; - return &shared; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp) -{ - (void)gaExp; - return false; -} - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { - haveRDTSC = true; - } - return true; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else - VTD_Get_Real_Time(&value->high,&value->low); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/aawin32.c b/board/MAI/bios_emulator/scitech/src/common/aawin32.c deleted file mode 100644 index 541df4a..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/aawin32.c +++ /dev/null @@ -1,264 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Win32 -* -* Description: OS specific Nucleus Graphics Architecture services for -* the Win32 operating system environments. -* -****************************************************************************/ - -#include "pm_help.h" -#include "pmapi.h" -#include -#include -#include -#define STRICT -#define WIN32_LEAN_AND_MEAN -#include - -/*------------------------- Global Variables ------------------------------*/ - -#if GA_MAX_DEVICES > 4 -#error GA_MAX_DEVICES has changed! -#endif - -static ibool haveRDTSC; -static GA_largeInteger countFreq; -static GA_loadDriver_t ORG_GA_loadDriver; -extern HANDLE _PM_hDevice; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -DESCRIPTION: -Get the current graphics driver imports from the VxD - -REMARKS: -This function returns a pointer to the common graphics driver loaded in the -helper VxD. The memory for the VxD is shared between all processes via -the VxD, so that the VxD, 16-bit code and 32-bit code all see the same -state when accessing the graphics binary portable driver. -****************************************************************************/ -GA_sharedInfo * NAPI GA_getSharedInfo( - int device) -{ - DWORD inBuf[1]; /* Buffer to send data to VxD */ - DWORD outBuf[2]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - PM_init(); - inBuf[0] = device; - if (DeviceIoControl(_PM_hDevice, PMHELP_GETSHAREDINFO32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) { - return (GA_sharedInfo*)outBuf[0]; - } - return NULL; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp) -{ - (void)gaExp; - return false; -} - -/**************************************************************************** -REMARKS: -This function initialises the software stereo module by either calling -the Nucleus libraries directly, or calling into the VxD if we are running -on the shared Nucleus libraries loaded by the Windows VxD. -****************************************************************************/ -static ibool NAPI _GA_softStereoInit( - GA_devCtx *dc) -{ - if (_PM_hDevice) { - DWORD inBuf[1]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - inBuf[0] = (ulong)dc; - if (DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOINIT32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) { - return outBuf[0]; - } - } - return false; -} - -/**************************************************************************** -REMARKS: -This function turns on software stereo mode, either directly or via the VxD. -****************************************************************************/ -static void NAPI _GA_softStereoOn(void) -{ - if (_PM_hDevice) { - DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOON32, NULL, 0, - NULL, 0, NULL, NULL); - } -} - -/**************************************************************************** -REMARKS: -This function schedules a software stereo mode page flip, either directly -or via the VxD. -****************************************************************************/ -static void NAPI _GA_softStereoScheduleFlip( - N_uint32 leftAddr, - N_uint32 rightAddr) -{ - if (_PM_hDevice) { - DWORD inBuf[2]; /* Buffer to send data to VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - inBuf[0] = (ulong)leftAddr; - inBuf[1] = (ulong)rightAddr; - DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOFLIP32, inBuf, sizeof(inBuf), - NULL, 0, &count, NULL); - } -} - -/**************************************************************************** -REMARKS: -This function turns off software stereo mode, either directly or via the VxD. -****************************************************************************/ -static N_int32 NAPI _GA_softStereoGetFlipStatus(void) -{ - if (_PM_hDevice) { - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOFLIPSTATUS32, NULL, 0, - outBuf, sizeof(outBuf), &count, NULL)) { - return outBuf[0]; - } - } - return 0; -} - -/**************************************************************************** -REMARKS: -This function turns off software stereo mode, either directly or via the VxD. -****************************************************************************/ -static void NAPI _GA_softStereoWaitTillFlipped(void) -{ - while (!_GA_softStereoGetFlipStatus()) - ; -} - -/**************************************************************************** -REMARKS: -This function turns off software stereo mode, either directly or via the VxD. -****************************************************************************/ -static void NAPI _GA_softStereoOff(void) -{ - if (_PM_hDevice) { - DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOOFF32, NULL, 0, - NULL, 0, NULL, NULL); - } -} - -/**************************************************************************** -REMARKS: -This function disable the software stereo handler, either directly or via -the VxD. -****************************************************************************/ -static void NAPI _GA_softStereoExit(void) -{ - if (_PM_hDevice) { - DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOEXIT32, NULL, 0, - NULL, 0, NULL, NULL); - } -} - -/**************************************************************************** -REMARKS: -We hook this function in here so that we can avoid the memory detect and -other destructive sequences in the drivers if we are loading the driver -from a Win32 application (our display drivers in contrast load them inside -the VxD directly, but the control panel applets use this function). -****************************************************************************/ -static GA_devCtx * NAPI _GA_loadDriver( - N_int32 deviceIndex, - N_int32 shared) -{ - GA_devCtx *dc; - DWORD inBuf[1]; - DWORD outBuf[1]; - N_int32 totalMemory = 0,oldIOPL; - - if (deviceIndex >= GA_MAX_DEVICES) - PM_fatalError("DeviceIndex too large in GA_loadDriver!"); - PM_init(); - inBuf[0] = deviceIndex; - if (DeviceIoControl(_PM_hDevice, PMHELP_GETMEMSIZE32, - inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), NULL, NULL)) - totalMemory = outBuf[0]; - if (totalMemory == 0) - totalMemory = 8192; - _GA_exports.GA_forceMemSize(totalMemory,shared); - oldIOPL = PM_setIOPL(3); - dc = ORG_GA_loadDriver(deviceIndex,shared); - PM_setIOPL(oldIOPL); - return dc; -} - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { - haveRDTSC = true; - return true; - } - else if (QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq)) { - haveRDTSC = false; - return true; - } - return false; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else - QueryPerformanceCounter((LARGE_INTEGER*)value); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/agplib.c b/board/MAI/bios_emulator/scitech/src/common/agplib.c deleted file mode 100644 index 476eedc..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/agplib.c +++ /dev/null @@ -1,219 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Any 32-bit protected mode environment -* -* Description: C module for the Graphics Accelerator Driver API. Uses -* the SciTech PM library for interfacing with DOS -* extender specific functions. -* -****************************************************************************/ - -#include "nucleus/graphics.h" -#include "nucleus/agp.h" - -/*---------------------------- Global Variables ---------------------------*/ - -#ifndef DEBUG_AGP_DRIVER -static AGP_exports _AGP_exports; -static int loaded = false; -static PE_MODULE *hModBPD = NULL; - -static N_imports _N_imports = { - sizeof(N_imports), - _OS_delay, - }; - -static AGP_imports _AGP_imports = { - sizeof(AGP_imports), - }; -#endif - -#include "pmimp.h" - -/*----------------------------- Implementation ----------------------------*/ - -#define DLL_NAME "agp.bpd" - -#ifndef DEBUG_AGP_DRIVER -/**************************************************************************** -REMARKS: -Fatal error handler for non-exported GA_exports. -****************************************************************************/ -static void _AGP_fatalErrorHandler(void) -{ - PM_fatalError("Unsupported AGP export function called! Please upgrade your copy of AGP!\n"); -} - -/**************************************************************************** -PARAMETERS: -shared - True to load the driver into shared memory. - -REMARKS: -Loads the Nucleus binary portable DLL into memory and initilises it. -****************************************************************************/ -static ibool LoadDriver(void) -{ - AGP_initLibrary_t AGP_initLibrary; - AGP_exports *agpExp; - char filename[PM_MAX_PATH]; - char bpdpath[PM_MAX_PATH]; - int i,max; - ulong *p; - - /* Check if we have already loaded the driver */ - if (loaded) - return true; - PM_init(); - - /* Open the BPD file */ - if (!PM_findBPD(DLL_NAME,bpdpath)) - return false; - strcpy(filename,bpdpath); - strcat(filename,DLL_NAME); - if ((hModBPD = PE_loadLibrary(filename,false)) == NULL) - return false; - if ((AGP_initLibrary = (AGP_initLibrary_t)PE_getProcAddress(hModBPD,"_AGP_initLibrary")) == NULL) - return false; - bpdpath[strlen(bpdpath)-1] = 0; - if (strcmp(bpdpath,PM_getNucleusPath()) == 0) - strcpy(bpdpath,PM_getNucleusConfigPath()); - else { - PM_backslash(bpdpath); - strcat(bpdpath,"config"); - } - if ((agpExp = AGP_initLibrary(bpdpath,filename,GA_getSystemPMImports(),&_N_imports,&_AGP_imports)) == NULL) - PM_fatalError("AGP_initLibrary failed!\n"); - _AGP_exports.dwSize = sizeof(_AGP_exports); - max = sizeof(_AGP_exports)/sizeof(AGP_initLibrary_t); - for (i = 0,p = (ulong*)&_AGP_exports; i < max; i++) - *p++ = (ulong)_AGP_fatalErrorHandler; - memcpy(&_AGP_exports,agpExp,MIN(sizeof(_AGP_exports),agpExp->dwSize)); - loaded = true; - return true; -} - -/* The following are stub entry points that the application calls to - * initialise the Nucleus loader library, and we use this to load our - * driver DLL from disk and initialise the library using it. - */ - -/* {secret} */ -int NAPI AGP_status(void) -{ - if (!loaded) - return nDriverNotFound; - return _AGP_exports.AGP_status(); -} - -/* {secret} */ -const char * NAPI AGP_errorMsg( - N_int32 status) -{ - if (!loaded) - return "Unable to load Nucleus device driver!"; - return _AGP_exports.AGP_errorMsg(status); -} - -/* {secret} */ -AGP_devCtx * NAPI AGP_loadDriver(N_int32 deviceIndex) -{ - if (!LoadDriver()) - return NULL; - return _AGP_exports.AGP_loadDriver(deviceIndex); -} - -/* {secret} */ -void NAPI AGP_unloadDriver( - AGP_devCtx *dc) -{ - if (loaded) - _AGP_exports.AGP_unloadDriver(dc); -} - -/* {secret} */ -void NAPI AGP_getGlobalOptions( - AGP_globalOptions *options) -{ - if (LoadDriver()) - _AGP_exports.AGP_getGlobalOptions(options); -} - -/* {secret} */ -void NAPI AGP_setGlobalOptions( - AGP_globalOptions *options) -{ - if (LoadDriver()) - _AGP_exports.AGP_setGlobalOptions(options); -} - -/* {secret} */ -void NAPI AGP_saveGlobalOptions( - AGP_globalOptions *options) -{ - if (loaded) - _AGP_exports.AGP_saveGlobalOptions(options); -} -#endif - -/* {secret} */ -void NAPI _OS_delay8253(N_uint32 microSeconds); - -/**************************************************************************** -REMARKS: -This function delays for the specified number of microseconds -****************************************************************************/ -void NAPI _OS_delay( - N_uint32 microSeconds) -{ - static ibool inited = false; - static ibool haveRDTSC; - LZTimerObject tm; - - if (!inited) { -#ifndef __WIN32_VXD__ - /* This has been causing problems in VxD's for some reason, so for now */ - /* we avoid using it. */ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { - ZTimerInit(); - haveRDTSC = true; - } - else -#endif - haveRDTSC = false; - inited = true; - } - if (haveRDTSC) { - LZTimerOnExt(&tm); - while (LZTimerLapExt(&tm) < microSeconds) - ; - LZTimerOnExt(&tm); - } - else - _OS_delay8253(microSeconds); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/center.c b/board/MAI/bios_emulator/scitech/src/common/center.c deleted file mode 100644 index 68e17c2..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/center.c +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** -* -* Display Doctor Windows Interface Code -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code is a proprietary trade secret of | -* |SciTech Software, Inc., located at 505 Wall Street, Chico, CA 95928 | -* |USA (www.scitechsoft.com). ANY UNAUTHORIZED POSSESSION, USE, | -* |VIEWING, COPYING, MODIFICATION OR DISSEMINATION OF THIS CODE IS | -* |STRICTLY PROHIBITED BY LAW. Unless you have current, express | -* |written authorization from SciTech to possess or use this code, you | -* |may be subject to civil and/or criminal penalties. | -* | | -* |If you received this code in error or you would like to report | -* |improper use, please immediately contact SciTech Software, Inc. at | -* |530-894-8400. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: C++ 3.0 -* Environment: Win16 -* -* Description: Dialog driven configuration program for UniVBE and -* WinDirect Professional products. -* -****************************************************************************/ - -#include "center.h" - -/*------------------------------ Implementation ---------------------------*/ - -void _EXPORT CenterWindow(HWND hWndCenter, HWND parent, BOOL repaint) -/**************************************************************************** -* -* Function: CenterWindow -* Parameters: hWndCenter - Window to center -* parent - Handle for parent window -* repaint - true if window should be re-painted -* -* Description: Centers the specified window within the bounds of the -* specified parent window. If the parent window is NULL, then -* we center it using the Desktop window. -* -****************************************************************************/ -{ - HWND hWndParent = (parent ? parent : GetDesktopWindow()); - RECT RectParent; - RECT RectCenter; - int CenterX,CenterY,Height,Width; - - GetWindowRect(hWndParent, &RectParent); - GetWindowRect(hWndCenter, &RectCenter); - - Width = (RectCenter.right - RectCenter.left); - Height = (RectCenter.bottom - RectCenter.top); - CenterX = ((RectParent.right - RectParent.left) - Width) / 2; - CenterY = ((RectParent.bottom - RectParent.top) - Height) / 2; - - if ((CenterX < 0) || (CenterY < 0)) { - /* The Center Window is smaller than the parent window. */ - if (hWndParent != GetDesktopWindow()) { - /* If the parent window is not the desktop use the desktop size. */ - CenterX = (GetSystemMetrics(SM_CXSCREEN) - Width) / 2; - CenterY = (GetSystemMetrics(SM_CYSCREEN) - Height) / 2; - } - CenterX = (CenterX < 0) ? 0: CenterX; - CenterY = (CenterY < 0) ? 0: CenterY; - } - else { - CenterX += RectParent.left; - CenterY += RectParent.top; - } - - /* Copy the values into RectCenter */ - RectCenter.left = CenterX; - RectCenter.right = CenterX + Width; - RectCenter.top = CenterY; - RectCenter.bottom = CenterY + Height; - - /* Move the window to the new location */ - MoveWindow(hWndCenter, RectCenter.left, RectCenter.top, - (RectCenter.right - RectCenter.left), - (RectCenter.bottom - RectCenter.top), repaint); -} - -void _EXPORT CenterLogo(HWND hWndLogo, HWND hWndParent, int CenterY) -/**************************************************************************** -* -* Function: CenterLogo -* Parameters: hWndLogo - Window to center -* hWndParent - Handle for parent window -* CenterY - Top coordinate for logo -* -* Description: Centers the specified window within the bounds of the -* specified parent window in the horizontal direction only. -* -****************************************************************************/ -{ - RECT RectParent; - RECT RectCenter; - int CenterX,Height,Width; - - GetWindowRect(hWndParent, &RectParent); - GetWindowRect(hWndLogo, &RectCenter); - Width = (RectCenter.right - RectCenter.left); - Height = (RectCenter.bottom - RectCenter.top); - CenterX = ((RectParent.right - RectParent.left) - Width) / 2; - - /* Copy the values into RectCenter */ - RectCenter.left = CenterX; - RectCenter.right = CenterX + Width; - RectCenter.top = CenterY; - RectCenter.bottom = CenterY + Height; - - /* Move the window to the new location */ - MoveWindow(hWndLogo, RectCenter.left, RectCenter.top, - (RectCenter.right - RectCenter.left), - (RectCenter.bottom - RectCenter.top), false); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/cmdline.c b/board/MAI/bios_emulator/scitech/src/common/cmdline.c deleted file mode 100644 index 531e5e1..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/cmdline.c +++ /dev/null @@ -1,428 +0,0 @@ -/**************************************************************************** -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: any -* -* Description: This module contains code to parse the command line, -* extracting options and parameters in standard System V -* style. -* -****************************************************************************/ - -#include -#include -#include -#include "cmdline.h" - -/*------------------------- Global variables ------------------------------*/ - -int nextargv = 1; /* Index into argv array */ -char *nextchar = NULL; /* Pointer to next character */ - -/*-------------------------- Implementation -------------------------------*/ - -#define IS_SWITCH_CHAR(c) ((c) == '-') -#define IS_NOT_SWITCH_CHAR(c) ((c) != '-') - -/**************************************************************************** -DESCRIPTION: -Parse the command line for specific options - -HEADER: -cmdline.h - -PARAMETERS: -argc - Value passed to program through argc variable -argv - Pointer to the argv array passed to the program -format - A string representing the expected format of the command line -argument - Pointer to optional argument on command line - -RETURNS: -Character code representing the next option parsed from the command line by -getcmdopt. Returns ALLDONE (-1) when there are no more parameters to be parsed -on the command line, PARAMETER (-2) when the argument being parsed is a -parameter and not an option switch and lastly INVALID (-3) if an error -occured while parsing the command line. - -REMARKS: -Function to parse the command line option switches in UNIX System V style. -When getcmdopt is called, it returns the character code of the next valid -option that is parsed from the command line as specified by the Format -string. The format string should be in the following form: - - "abcd:e:f:" - -where a,b and c represent single switch style options and the character -code returned by getcmdopt is the only value returned. Also d, e and f -represent options that expect arguments immediately after them on the -command line. The argument that follows the option on the command line is -returned via a reference in the pointer argument. Thus a valid command line -for this format string might be: - - myprogram -adlines -b -f format infile outfile - -where a and b will be returned as single character options with no argument, -while d is returned with the argument lines and f is returned with the -argument format. - -When getcmdopt returns with PARAMETER (we attempted to parse a paramter, not -an option), the global variable NextArgv will hold an index in the argv -array to the argument on the command line AFTER the options, ie in the -above example the string 'infile'. If the parameter is successfully used, -NextArgv should be incremented and getcmdopt can be called again to parse any -more options. Thus you can also have options interspersed throught the -command line. eg: - - myprogram -adlines infile -b outfile -f format - -can be made to be a valid form of the above command line. -****************************************************************************/ -int getcmdopt( - int argc, - char **argv, - char *format, - char **argument) -{ - char ch; - char *formatchar; - - if (argc > nextargv) { - if (nextchar == NULL) { - nextchar = argv[nextargv]; /* Index next argument */ - if (nextchar == NULL) { - nextargv++; - return ALLDONE; /* No more options */ - } - if (IS_NOT_SWITCH_CHAR(*nextchar)) { - nextchar = NULL; - return PARAMETER; /* We have a parameter */ - } - nextchar++; /* Move past switch operator */ - if (IS_SWITCH_CHAR(*nextchar)) { - nextchar = NULL; - return INVALID; /* Ignore rest of line */ - } - } - if ((ch = *(nextchar++)) == 0) { - nextchar = NULL; - return INVALID; /* No options on line */ - } - - if (ch == ':' || (formatchar = strchr(format, ch)) == NULL) - return INVALID; - - if (*(++formatchar) == ':') { /* Expect an argument after option */ - nextargv++; - if (*nextchar == 0) { - if (argc <= nextargv) - return INVALID; - nextchar = argv[nextargv++]; - } - *argument = nextchar; - nextchar = NULL; - } - else { /* We have a switch style option */ - if (*nextchar == 0) { - nextargv++; - nextchar = NULL; - } - *argument = NULL; - } - return ch; /* return the option specifier */ - } - nextchar = NULL; - nextargv++; - return ALLDONE; /* no arguments on command line */ -} - -/**************************************************************************** -PARAMETERS: -optarr - Description for the option we are parsing -argument - String to parse - -RETURNS: -INVALID on error, ALLDONE on success. - -REMARKS: -Parses the argument string depending on the type of argument that is -expected, filling in the argument for that option. Note that to parse a -string, we simply return a pointer to argument. -****************************************************************************/ -static int parse_option( - Option *optarr, - char *argument) -{ - int num_read; - - switch ((int)(optarr->type)) { - case OPT_INTEGER: - num_read = sscanf(argument,"%d",(int*)optarr->arg); - break; - case OPT_HEX: - num_read = sscanf(argument,"%x",(int*)optarr->arg); - break; - case OPT_OCTAL: - num_read = sscanf(argument,"%o",(int*)optarr->arg); - break; - case OPT_UNSIGNED: - num_read = sscanf(argument,"%u",(uint*)optarr->arg); - break; - case OPT_LINTEGER: - num_read = sscanf(argument,"%ld",(long*)optarr->arg); - break; - case OPT_LHEX: - num_read = sscanf(argument,"%lx",(long*)optarr->arg); - break; - case OPT_LOCTAL: - num_read = sscanf(argument,"%lo",(long*)optarr->arg); - break; - case OPT_LUNSIGNED: - num_read = sscanf(argument,"%lu",(ulong*)optarr->arg); - break; - case OPT_FLOAT: - num_read = sscanf(argument,"%f",(float*)optarr->arg); - break; - case OPT_DOUBLE: - num_read = sscanf(argument,"%lf",(double*)optarr->arg); - break; - case OPT_LDOUBLE: - num_read = sscanf(argument,"%Lf",(long double*)optarr->arg); - break; - case OPT_STRING: - num_read = 1; /* This always works */ - *((char**)optarr->arg) = argument; - break; - default: - return INVALID; - } - - if (num_read == 0) - return INVALID; - else - return ALLDONE; -} - -/**************************************************************************** -HEADER: -cmdline.h - -PARAMETERS: -argc - Number of arguments on command line -argv - Array of command line arguments -num_opt - Number of options in option array -optarr - Array to specify how to parse the command line -do_param - Routine to handle a command line parameter - -RETURNS: -ALLDONE, INVALID or HELP - -REMARKS: -Function to parse the command line according to a table of options. This -routine calls getcmdopt above to parse each individual option and attempts -to parse each option into a variable of the specified type. The routine -can parse integers and long integers in either decimal, octal, hexadecimal -notation, unsigned integers and unsigned longs, strings and option switches. -Option switches are simply boolean variables that get turned on if the -switch was parsed. - -Parameters are extracted from the command line by calling a user supplied -routine do_param() to handle each parameter as it is encountered. The -routine do_param() should accept a pointer to the parameter on the command -line and an integer representing how many parameters have been encountered -(ie: 1 if this is the first parameter, 10 if it is the 10th etc), and return -ALLDONE upon successfully parsing it or INVALID if the parameter was invalid. - -We return either ALLDONE if all the options were successfully parsed, -INVALID if an invalid option was encountered or HELP if any of -h, -H or --? were present on the command line. -****************************************************************************/ -int getargs( - int argc, - char *argv[], - int num_opt, - Option optarr[], - int (*do_param)( - char *param, - int num)) -{ - int i,opt; - char *argument; - int param_num = 1; - char cmdstr[MAXARG*2 + 4]; - - /* Build the command string from the array of options */ - - strcpy(cmdstr,"hH?"); - for (i = 0,opt = 3; i < num_opt; i++,opt++) { - cmdstr[opt] = optarr[i].opt; - if (optarr[i].type != OPT_SWITCH) { - cmdstr[++opt] = ':'; - } - } - cmdstr[opt] = '\0'; - - for (;;) { - opt = getcmdopt(argc,argv,cmdstr,&argument); - switch (opt) { - case 'H': - case 'h': - case '?': - return HELP; - case ALLDONE: - return ALLDONE; - case INVALID: - return INVALID; - case PARAMETER: - if (do_param == NULL) - return INVALID; - if (do_param(argv[nextargv],param_num) == INVALID) - return INVALID; - nextargv++; - param_num++; - break; - default: - - /* Search for the option in the option array. We are - * guaranteed to find it. - */ - - for (i = 0; i < num_opt; i++) { - if (optarr[i].opt == opt) - break; - } - if (optarr[i].type == OPT_SWITCH) - *((ibool*)optarr[i].arg) = true; - else { - if (parse_option(&optarr[i],argument) == INVALID) - return INVALID; - } - break; - } - } -} - -/**************************************************************************** -HEADER: -cmdline.h - -PARAMETERS: -num_opt - Number of options in the table -optarr - Table of option descriptions - -REMARKS: -Prints the description of each option in a standard format to the standard -output device. The description for each option is obtained from the table -of options. -****************************************************************************/ -void print_desc( - int num_opt, - Option optarr[]) -{ - int i; - - for (i = 0; i < num_opt; i++) { - if (optarr[i].type == OPT_SWITCH) - printf(" -%c %s\n",optarr[i].opt,optarr[i].desc); - else - printf(" -%c %s\n",optarr[i].opt,optarr[i].desc); - } -} - -/**************************************************************************** -HEADER: -cmdline.h - -PARAMETERS: -moduleName - Module name for program -cmdLine - Command line to parse -pargc - Pointer to 'argc' parameter -pargv - Pointer to 'argv' parameter -maxArgc - Maximum argv array index - -REMARKS: -Parses a command line from a single string into the C style 'argc' and -'argv' format. Most useful for Windows programs where the command line -is passed in verbatim. -****************************************************************************/ -int parse_commandline( - char *moduleName, - char *cmdLine, - int *pargc, - char *argv[], - int maxArgv) -{ - static char str[512]; - static char filename[260]; - char *prevWord = NULL; - ibool inQuote = FALSE; - ibool noStrip = FALSE; - int argc; - - argc = 0; - strcpy(filename,moduleName); - argv[argc++] = filename; - cmdLine = strncpy(str, cmdLine, sizeof(str)-1); - while (*cmdLine) { - switch (*cmdLine) { - case '"' : - if (prevWord != NULL) { - if (inQuote) { - if (!noStrip) - *cmdLine = '\0'; - argv [argc++] = prevWord; - prevWord = NULL; - } - else - noStrip = TRUE; - } - inQuote = !inQuote; - break; - case ' ' : - case '\t' : - if (!inQuote) { - if (prevWord != NULL) { - *cmdLine = '\0'; - argv [argc++] = prevWord; - prevWord = NULL; - noStrip = FALSE; - } - } - break; - default : - if (prevWord == NULL) - prevWord = cmdLine; - break; - } - if (argc >= maxArgv - 1) - break; - cmdLine++; - } - - if ((prevWord != NULL || (inQuote && prevWord != NULL)) && argc < maxArgv - 1) { - *cmdLine = '\0'; - argv [argc++] = prevWord; - } - argv[argc] = NULL; - - /* Return updated parameters */ - return (*pargc = argc); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/gabeos.c b/board/MAI/bios_emulator/scitech/src/common/gabeos.c deleted file mode 100644 index a934bd1..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/gabeos.c +++ /dev/null @@ -1,146 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Linux -* -* Description: OS specific Nucleus Graphics Architecture services for -* the Linux operating system. -* -****************************************************************************/ - -#include "nucleus/graphics.h" -#include - -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -PARAMETERS: -path - Local path to the Nucleus driver files. - -REMARKS: -This function is used by the application program to override the location -of the Nucleus driver files that are loaded. Normally the loader code -will look in the system Nucleus directories first, then in the 'drivers' -directory relative to the current working directory, and finally relative -to the MGL_ROOT environment variable. -****************************************************************************/ -void NAPI GA_setLocalPath( - const char *path) -{ - PM_setLocalBPDPath(path); -} - -/**************************************************************************** -RETURNS: -Pointer to the system wide PM library imports, or the internal version if none - -REMARKS: -In order to support deploying new Nucleus drivers that may require updated -PM library functions, we check here to see if there is a system wide version -of the PM functions available. If so we return those functions for use with -the system wide Nucleus drivers, otherwise the compiled in version of the PM -library is used with the application local version of Nucleus. -****************************************************************************/ -PM_imports * NAPI GA_getSystemPMImports(void) -{ - /* TODO: We may very well want to provide a system shared library */ - /* that eports the PM functions required by the Nucleus library */ - /* for BeOS here. That will eliminate fatal errors loading new */ - /* drivers on BeOS! */ - return &_PM_imports; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp, - ibool shared) -{ - (void)gaExp; - (void)shared; - return false; -} - -#ifndef TEST_HARNESS -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI GA_queryFunctions( - GA_devCtx *dc, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.GA_queryFunctions(dc,id,funcs); -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI REF2D_queryFunctions( - REF2D_driver *ref2d, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); -} -#endif - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - haveRDTSC = true; - return true; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else { - struct timeval t; - gettimeofday(&t, NULL); - value->low = t.tv_sec*1000000 + t.tv_usec; - value->high = 0; - } -} diff --git a/board/MAI/bios_emulator/scitech/src/common/gados.c b/board/MAI/bios_emulator/scitech/src/common/gados.c deleted file mode 100644 index d2be776..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/gados.c +++ /dev/null @@ -1,135 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: MSDOS -* -* Description: OS specific Nucleus Graphics Architecture services for -* the MSDOS operating system. -* -****************************************************************************/ - -#include "pm_help.h" -#include "pmapi.h" -#include -#include -#include - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -PARAMETERS: -path - Local path to the Nucleus driver files. - -REMARKS: -This function is used by the application program to override the location -of the Nucleus driver files that are loaded. Normally the loader code -will look in the system Nucleus directories first, then in the 'drivers' -directory relative to the current working directory, and finally relative -to the MGL_ROOT environment variable. -****************************************************************************/ -void NAPI GA_setLocalPath( - const char *path) -{ - PM_setLocalBPDPath(path); -} - -/**************************************************************************** -RETURNS: -Pointer to the system wide PM library imports, or the internal version if none - -REMARKS: -Nothing to do here for DOS. Basically since DOS has no system wide shared -library mechanism we are essentially screwed if the binary API changes. -By default for 32-bit DOS apps the local Nucleus drivers should always be -used in preference to the system wide Nucleus drivers. -****************************************************************************/ -PM_imports * NAPI GA_getSystemPMImports(void) -{ - return &_PM_imports; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp, - ibool shared) -{ - (void)gaExp; - (void)shared; - return false; -} - -#if !defined(TEST_HARNESS) && !defined(VBETEST) -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI GA_queryFunctions( - GA_devCtx *dc, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.GA_queryFunctions(dc,id,funcs); -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI REF2D_queryFunctions( - REF2D_driver *ref2d, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); -} -#endif - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the DOS -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - return true; - return false; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - _GA_readTimeStamp(value); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/galib.c b/board/MAI/bios_emulator/scitech/src/common/galib.c deleted file mode 100644 index f2eacc3..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/galib.c +++ /dev/null @@ -1,268 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Any 32-bit protected mode environment -* -* Description: C module for the Graphics Accelerator Driver API. Uses -* the SciTech PM library for interfacing with DOS -* extender specific functions. -* -****************************************************************************/ - -#include "nucleus/graphics.h" -#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) -#include "sdd/sddhelp.h" -#else -#include -#include -#endif - -/*---------------------------- Global Variables ---------------------------*/ - -#ifndef TEST_HARNESS -GA_exports _VARAPI __GA_exports; -static int loaded = false; -static PE_MODULE *hModBPD = NULL; - -static N_imports _N_imports = { - sizeof(N_imports), - _OS_delay, - }; - -static GA_imports _GA_imports = { - sizeof(GA_imports), - GA_getSharedInfo, - GA_TimerInit, - GA_TimerRead, - GA_TimerDifference, - }; -#endif - -/*----------------------------- Implementation ----------------------------*/ - -#define DLL_NAME "graphics.bpd" - -/**************************************************************************** -REMARKS: -This function is no longer used but we must implement it and return NULL -for compatibility with older binary drivers. -****************************************************************************/ -GA_sharedInfo * NAPI GA_getSharedInfo( - int device) -{ - return NULL; -} - -#ifndef TEST_HARNESS -/**************************************************************************** -REMARKS: -Fatal error handler for non-exported GA_exports. -****************************************************************************/ -static void _GA_fatalErrorHandler(void) -{ - PM_fatalError("Unsupported Nucleus export function called! Please upgrade your copy of Nucleus!\n"); -} - -/**************************************************************************** -PARAMETERS: -shared - True to load the driver into shared memory. - -REMARKS: -Loads the Nucleus binary portable DLL into memory and initilises it. -****************************************************************************/ -static ibool LoadDriver( - ibool shared) -{ - GA_initLibrary_t GA_initLibrary; - GA_exports *gaExp; - char filename[PM_MAX_PATH]; - char bpdpath[PM_MAX_PATH]; - int i,max; - ulong *p; - - /* Check if we have already loaded the driver */ - if (loaded) - return true; - PM_init(); - - /* First try to see if we can find the system wide shared exports - * if they are available. Under OS/2 this connects to our global - * shared Nucleus loader in SDDPMI.DLL. - */ - __GA_exports.dwSize = sizeof(__GA_exports); - if (GA_getSharedExports(&__GA_exports,shared)) - return loaded = true; - - /* Open the BPD file */ - if (!PM_findBPD(DLL_NAME,bpdpath)) - return false; - strcpy(filename,bpdpath); - strcat(filename,DLL_NAME); - if ((hModBPD = PE_loadLibrary(filename,shared)) == NULL) - return false; - if ((GA_initLibrary = (GA_initLibrary_t)PE_getProcAddress(hModBPD,"_GA_initLibrary")) == NULL) - return false; - bpdpath[strlen(bpdpath)-1] = 0; - if (strcmp(bpdpath,PM_getNucleusPath()) == 0) - strcpy(bpdpath,PM_getNucleusConfigPath()); - else { - PM_backslash(bpdpath); - strcat(bpdpath,"config"); - } - if ((gaExp = GA_initLibrary(shared,bpdpath,filename,GA_getSystemPMImports(),&_N_imports,&_GA_imports)) == NULL) - PM_fatalError("GA_initLibrary failed!\n"); - - /* Initialize all default imports to point to fatal error handler - * for upwards compatibility, and copy the exported functions. - */ - max = sizeof(__GA_exports)/sizeof(GA_initLibrary_t); - for (i = 0,p = (ulong*)&__GA_exports; i < max; i++) - *p++ = (ulong)_GA_fatalErrorHandler; - memcpy(&__GA_exports,gaExp,MIN(sizeof(__GA_exports),gaExp->dwSize)); - loaded = true; - return true; -} - -/* The following are stub entry points that the application calls to - * initialise the Nucleus loader library, and we use this to load our - * driver DLL from disk and initialise the library using it. - */ - -/* {secret} */ -int NAPI GA_status(void) -{ - if (!loaded) - return nDriverNotFound; - return __GA_exports.GA_status(); -} - -/* {secret} */ -const char * NAPI GA_errorMsg( - N_int32 status) -{ - if (!loaded) - return "Unable to load Nucleus device driver!"; - return __GA_exports.GA_errorMsg(status); -} - -/* {secret} */ -int NAPI GA_getDaysLeft(N_int32 shared) -{ - if (!LoadDriver(shared)) - return -1; - return __GA_exports.GA_getDaysLeft(shared); -} - -/* {secret} */ -int NAPI GA_registerLicense(uchar *license,N_int32 shared) -{ - if (!LoadDriver(shared)) - return 0; - return __GA_exports.GA_registerLicense(license,shared); -} - -/* {secret} */ -ibool NAPI GA_loadInGUI(N_int32 shared) -{ - if (!LoadDriver(shared)) - return false; - return __GA_exports.GA_loadInGUI(shared); -} - -/* {secret} */ -int NAPI GA_enumerateDevices(N_int32 shared) -{ - if (!LoadDriver(shared)) - return 0; - return __GA_exports.GA_enumerateDevices(shared); -} - -/* {secret} */ -GA_devCtx * NAPI GA_loadDriver(N_int32 deviceIndex,N_int32 shared) -{ - if (!LoadDriver(shared)) - return NULL; - return __GA_exports.GA_loadDriver(deviceIndex,shared); -} - -/* {secret} */ -void NAPI GA_getGlobalOptions( - GA_globalOptions *options, - ibool shared) -{ - if (LoadDriver(shared)) - __GA_exports.GA_getGlobalOptions(options,shared); -} - -/* {secret} */ -PE_MODULE * NAPI GA_loadLibrary( - const char *szBPDName, - ulong *size, - ibool shared) -{ - if (!LoadDriver(shared)) - return NULL; - return __GA_exports.GA_loadLibrary(szBPDName,size,shared); -} - -/* {secret} */ -GA_devCtx * NAPI GA_getCurrentDriver( - N_int32 deviceIndex) -{ - /* Bail for older drivers that didn't export this function! */ - if (!__GA_exports.GA_getCurrentDriver) - return NULL; - return __GA_exports.GA_getCurrentDriver(deviceIndex); -} - -/* {secret} */ -REF2D_driver * NAPI GA_getCurrentRef2d( - N_int32 deviceIndex) -{ - /* Bail for older drivers that didn't export this function! */ - if (!__GA_exports.GA_getCurrentRef2d) - return NULL; - return __GA_exports.GA_getCurrentRef2d(deviceIndex); -} - -/* {secret} */ -int NAPI GA_isOEMVersion(ibool shared) -{ - if (!LoadDriver(shared)) - return 0; - return __GA_exports.GA_isOEMVersion(shared); -} - -/* {secret} */ -N_uint32 * NAPI GA_getLicensedDevices(ibool shared) -{ - if (!LoadDriver(shared)) - return 0; - return __GA_exports.GA_getLicensedDevices(shared); -} -#endif diff --git a/board/MAI/bios_emulator/scitech/src/common/galinux.c b/board/MAI/bios_emulator/scitech/src/common/galinux.c deleted file mode 100644 index 47e4e85..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/galinux.c +++ /dev/null @@ -1,148 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Linux -* -* Description: OS specific Nucleus Graphics Architecture services for -* the Linux operating system. -* -****************************************************************************/ - -#include "nucleus/graphics.h" -#include - -/*---------------------------- Global Variables ---------------------------*/ - -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -PARAMETERS: -path - Local path to the Nucleus driver files. - -REMARKS: -This function is used by the application program to override the location -of the Nucleus driver files that are loaded. Normally the loader code -will look in the system Nucleus directories first, then in the 'drivers' -directory relative to the current working directory, and finally relative -to the MGL_ROOT environment variable. -****************************************************************************/ -void NAPI GA_setLocalPath( - const char *path) -{ - PM_setLocalBPDPath(path); -} - -/**************************************************************************** -RETURNS: -Pointer to the system wide PM library imports, or the internal version if none - -REMARKS: -In order to support deploying new Nucleus drivers that may require updated -PM library functions, we check here to see if there is a system wide version -of the PM functions available. If so we return those functions for use with -the system wide Nucleus drivers, otherwise the compiled in version of the PM -library is used with the application local version of Nucleus. -****************************************************************************/ -PM_imports * NAPI GA_getSystemPMImports(void) -{ - /* TODO: We may very well want to provide a system shared library */ - /* that eports the PM functions required by the Nucleus library */ - /* for Linux here. That will eliminate fatal errors loading new */ - /* drivers on Linux! */ - return &_PM_imports; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp, - ibool shared) -{ - (void)gaExp; - (void)shared; - return false; -} - -#ifndef TEST_HARNESS -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI GA_queryFunctions( - GA_devCtx *dc, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.GA_queryFunctions(dc,id,funcs); -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI REF2D_queryFunctions( - REF2D_driver *ref2d, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); -} -#endif - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - haveRDTSC = true; - return true; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else { - struct timeval t; - gettimeofday(&t, NULL); - value->low = t.tv_sec*1000000 + t.tv_usec; - value->high = 0; - } -} diff --git a/board/MAI/bios_emulator/scitech/src/common/gantdrv.c b/board/MAI/bios_emulator/scitech/src/common/gantdrv.c deleted file mode 100644 index 050f737..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/gantdrv.c +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: NT device driver -* -* Description: OS specific Nucleus Graphics Architecture services for -* the NT device drivers. -* -****************************************************************************/ - -#include "sdd/sddhelp.h" - -/*------------------------- Global Variables ------------------------------*/ - -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -PARAMETERS: -path - Local path to the Nucleus driver files. - -REMARKS: -This function is used by the application program to override the location -of the Nucleus driver files that are loaded. Normally the loader code -will look in the system Nucleus directories first, then in the 'drivers' -directory relative to the current working directory, and finally relative -to the MGL_ROOT environment variable. -****************************************************************************/ -void NAPI GA_setLocalPath( - const char *path) -{ - PM_setLocalBPDPath(path); -} - -/**************************************************************************** -RETURNS: -Pointer to the system wide PM library imports, or the internal version if none - -REMARKS: -Nothing special for this OS. -****************************************************************************/ -PM_imports * NAPI GA_getSystemPMImports(void) -{ - return &_PM_imports; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp, - ibool shared) -{ - (void)gaExp; - (void)shared; - return false; -} - -#ifndef TEST_HARNESS -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI GA_queryFunctions( - GA_devCtx *dc, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.GA_queryFunctions(dc,id,funcs); -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI REF2D_queryFunctions( - REF2D_driver *ref2d, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); -} -#endif - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { - haveRDTSC = true; - } - return true; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else - KeQuerySystemTime((LARGE_INTEGER*)value); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/gaos2.c b/board/MAI/bios_emulator/scitech/src/common/gaos2.c deleted file mode 100644 index 26e6503..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/gaos2.c +++ /dev/null @@ -1,248 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: OS/2 32-bit -* -* Description: OS specific Nucleus Graphics Architecture services for -* the OS/2 operating system environments. -* -****************************************************************************/ - -#include "pm_help.h" -#define INCL_DOSERRORS -#define INCL_DOS -#define INCL_SUB -#define INCL_VIO -#define INCL_KBD -#include - -/*--------------------------- Global variables ----------------------------*/ - -static ibool haveRDTSC = false; -static ulong parms[3]; /* Must not cross 64Kb boundary! */ -static ulong result[4]; /* Must not cross 64Kb boundary! */ - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -PARAMETERS: -func - Helper device driver function to call - -RETURNS: -First return value from the device driver in parmsOut[0] - -REMARKS: -Function to open our helper device driver, call it and close the file -handle. Note that we have to open the device driver for every call because -of two problems: - - 1. We cannot open a single file handle in a DLL that is shared amongst - programs, since every process must have it's own open file handle. - - 2. For some reason there appears to be a limit of about 12 open file - handles on a device driver in the system. Hence when we open more - than about 12 file handles things start to go very strange. - -Hence we simply open the file handle every time that we need to call the -device driver to work around these problems. -****************************************************************************/ -static ulong CallSDDHelp( - int func) -{ - static ulong inLen; /* Must not cross 64Kb boundary! */ - static ulong outLen; /* Must not cross 64Kb boundary! */ - HFILE hSDDHelp; - - /* If this code in here fails, we are screwed! Many of our drivers - * use this code and don't have a C library, so we simply assume we - * can't fail here. - */ - DosOpen(PMHELP_NAME,&hSDDHelp,&result[0],0,0, - FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, - NULL); - DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,func, - &parms, inLen = sizeof(parms), &inLen, - &result, outLen = sizeof(result), &outLen); - DosClose(hSDDHelp); - return result[0]; -} - -/**************************************************************************** -PARAMETERS: -path - Local path to the Nucleus driver files. - -REMARKS: -This function is used by the application program to override the location -of the Nucleus driver files that are loaded. Normally the loader code -will look in the system Nucleus directories first, then in the 'drivers' -directory relative to the current working directory, and finally relative -to the MGL_ROOT environment variable. -****************************************************************************/ -void NAPI GA_setLocalPath( - const char *path) -{ - PM_setLocalBPDPath(path); -} - -/**************************************************************************** -RETURNS: -Pointer to the system wide PM library imports, or the internal version if none - -REMARKS: -For OS/2 we don't need to do anything special because Nucleus is always -loaded via the shared SDDPMI driver when SDD is loaded so we don't need -a system wide PM library imports function. -****************************************************************************/ -PM_imports * NAPI GA_getSystemPMImports(void) -{ - return &_PM_imports; -} - -/**************************************************************************** -PARAMETERS: -gaExp - Place to store the exported functions -shared - True if connecting to the shared, global Nucleus driver - -REMARKS: -For OS/2 if SDD is loaded we *always* connect to the shared Nucleus functions -contained within the SDDPMI driver. This allows the Nucleus functions contained -within this driver to be utilised by all Nucleus apps in the system and -maintains a consistent state between versions. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp, - ibool shared) -{ - /* In test harness mode, we need to load a local copy of Nucleus */ -#if !defined (TEST_HARNESS) || defined (DEBUG_SDDPMI) - HMODULE hModSDDPMI; - char buf[80]; - GA_exports *exp; - - /* Initialise the PM library and connect to our runtime DLL's */ - PM_init(); - if (CallSDDHelp(PMHELP_GETSHAREDEXP) != 0) { - /* We have found the shared Nucleus exports. Because not all processes - * map to SDDPMI.DLL, we need to ensure that we connect to this - * DLL so that it gets mapped into our address space (that is - * where the shared Nucleus loader code is located). Simply doing a - * DosLoadModule on it is enough for this. - */ - DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"SDDPMI.DLL",&hModSDDPMI); - exp = (GA_exports*)result[0]; - memcpy(gaExp,exp,MIN(gaExp->dwSize,exp->dwSize)); - return true; - } -#endif - (void)shared; - return false; -} - -#ifndef TEST_HARNESS -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI GA_queryFunctions( - GA_devCtx *dc, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.GA_queryFunctions(dc,id,funcs); -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI REF2D_queryFunctions( - REF2D_driver *ref2d, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); -} -#endif - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - haveRDTSC = true; - return true; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else - DosTmrQueryTime((QWORD*)value); -} - -/**************************************************************************** -REMARKS: -On OS/2, we need special memory allocation functions if we build SDDPMI in -test harness mode. But if we build GATest etc. in test mode, we want to use -the normal C runtime functions, so route them back here. -****************************************************************************/ - -#if defined (TEST_HARNESS) && !defined (DEBUG_SDDPMI) - -/* Undefine these macros first or we'll recurse to hell! */ -#undef malloc -#undef calloc -#undef realloc -#undef free - -void *SDDPMI_malloc(size_t size) { - return malloc(size); -} - -void *SDDPMI_calloc(size_t num, size_t size) { - return calloc(num, size); -} - -void SDDPMI_free(void *ptr) { - free(ptr); -} - -void *SDDPMI_realloc(void *ptr, size_t size) { - return realloc(ptr, size); -} - -#endif diff --git a/board/MAI/bios_emulator/scitech/src/common/gaqnx.c b/board/MAI/bios_emulator/scitech/src/common/gaqnx.c deleted file mode 100644 index 525d662..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/gaqnx.c +++ /dev/null @@ -1,149 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: QNX -* -* Description: OS specific Nucleus Graphics Architecture services for -* the QNX operating system. -* -****************************************************************************/ - -#include "nucleus/graphics.h" -#include - -/*---------------------------- Global Variables ---------------------------*/ - -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -PARAMETERS: -path - Local path to the Nucleus driver files. - -REMARKS: -This function is used by the application program to override the location -of the Nucleus driver files that are loaded. Normally the loader code -will look in the system Nucleus directories first, then in the 'drivers' -directory relative to the current working directory, and finally relative -to the MGL_ROOT environment variable. -****************************************************************************/ -void NAPI GA_setLocalPath( - const char *path) -{ - PM_setLocalBPDPath(path); -} - -/**************************************************************************** -RETURNS: -Pointer to the system wide PM library imports, or the internal version if none - -REMARKS: -In order to support deploying new Nucleus drivers that may require updated -PM library functions, we check here to see if there is a system wide version -of the PM functions available. If so we return those functions for use with -the system wide Nucleus drivers, otherwise the compiled in version of the PM -library is used with the application local version of Nucleus. -****************************************************************************/ -PM_imports * NAPI GA_getSystemPMImports(void) -{ - /* TODO: We may very well want to provide a system shared library */ - /* that eports the PM functions required by the Nucleus library */ - /* for QNX here. That will eliminate fatal errors loading new */ - /* drivers on QNX! */ - return &_PM_imports; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp, - ibool shared) -{ - (void)gaExp; - (void)shared; - return false; -} - -#ifndef TEST_HARNESS -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI GA_queryFunctions( - GA_devCtx *dc, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.GA_queryFunctions(dc,id,funcs); -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI REF2D_queryFunctions( - REF2D_driver *ref2d, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); -} -#endif - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - haveRDTSC = true; - return true; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else { - struct timespec ts; - - clock_gettime(CLOCK_REALTIME, &ts); - value->low = (ts.tv_nsec / 1000 + ts.tv_sec * 1000000); - value->high = 0; - } -} diff --git a/board/MAI/bios_emulator/scitech/src/common/gartt.c b/board/MAI/bios_emulator/scitech/src/common/gartt.c deleted file mode 100644 index 3a41f59..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/gartt.c +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: RTTarget-32 -* -* Description: OS specific Nucleus Graphics Architecture services for -* the RTTarget-32 operating system environments. -* -****************************************************************************/ - -#include "nucleus/graphics.h" - -/*------------------------- Global Variables ------------------------------*/ - -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -PARAMETERS: -path - Local path to the Nucleus driver files. - -REMARKS: -This function is used by the application program to override the location -of the Nucleus driver files that are loaded. Normally the loader code -will look in the system Nucleus directories first, then in the 'drivers' -directory relative to the current working directory, and finally relative -to the MGL_ROOT environment variable. -****************************************************************************/ -void NAPI GA_setLocalPath( - const char *path) -{ - PM_setLocalBPDPath(path); -} - -/**************************************************************************** -RETURNS: -Pointer to the system wide PM library imports, or the internal version if none - -REMARKS: -In order to support deploying new Nucleus drivers that may require updated -PM library functions, we check here to see if there is a system wide version -of the PM functions available. If so we return those functions for use with -the system wide Nucleus drivers, otherwise the compiled in version of the PM -library is used with the application local version of Nucleus. -****************************************************************************/ -PM_imports * NAPI GA_getSystemPMImports(void) -{ - return &_PM_imports; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp, - ibool shared) -{ - (void)gaExp; - (void)shared; - return false; -} - -#ifndef TEST_HARNESS -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI GA_queryFunctions( - GA_devCtx *dc, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.GA_queryFunctions(dc,id,funcs); -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI REF2D_queryFunctions( - REF2D_driver *ref2d, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); -} -#endif - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { - haveRDTSC = true; - return true; - } - return false; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/gasmx.c b/board/MAI/bios_emulator/scitech/src/common/gasmx.c deleted file mode 100644 index ae31941..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/gasmx.c +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: smx32 -* -* Description: OS specific Nucleus Graphics Architecture services for -* the smx32 platform -- no vxD support. -* -****************************************************************************/ - -#include "pmapi.h" -#include "nucleus/graphics.h" - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -PARAMETERS: -path - Local path to the Nucleus driver files. - -REMARKS: -This function is used by the application program to override the location -of the Nucleus driver files that are loaded. Normally the loader code -will look in the system Nucleus directories first, then in the 'drivers' -directory relative to the current working directory, and finally relative -to the MGL_ROOT environment variable. -****************************************************************************/ -void NAPI GA_setLocalPath( - const char *path) -{ - PM_setLocalBPDPath(path); -} - -/**************************************************************************** -RETURNS: -Pointer to the system wide PM library imports, or the internal version if none - -REMARKS: -In order to support deploying new Nucleus drivers that may require updated -PM library functions, we check here to see if there is a system wide version -of the PM functions available. If so we return those functions for use with -the system wide Nucleus drivers, otherwise the compiled in version of the PM -library is used with the application local version of Nucleus. -****************************************************************************/ -PM_imports * NAPI GA_getSystemPMImports(void) -{ - return &_PM_imports; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp, - ibool shared) -{ - (void)gaExp; - (void)shared; - return false; -} - -#ifndef TEST_HARNESS -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI GA_queryFunctions( - GA_devCtx *dc, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.GA_queryFunctions(dc,id,funcs); -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI REF2D_queryFunctions( - REF2D_driver *ref2d, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); -} -#endif - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) - return true; - return false; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - _GA_readTimeStamp(value); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/gavxd.c b/board/MAI/bios_emulator/scitech/src/common/gavxd.c deleted file mode 100644 index fc8ba8d..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/gavxd.c +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Win32 VxD -* -* Description: OS specific Nucleus Graphics Architecture services for -* the Win32 VxD's. -* -****************************************************************************/ - -#include "sdd/sddhelp.h" - -/*------------------------- Global Variables ------------------------------*/ - -static ibool haveRDTSC; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -PARAMETERS: -path - Local path to the Nucleus driver files. - -REMARKS: -This function is used by the application program to override the location -of the Nucleus driver files that are loaded. Normally the loader code -will look in the system Nucleus directories first, then in the 'drivers' -directory relative to the current working directory, and finally relative -to the MGL_ROOT environment variable. -****************************************************************************/ -void NAPI GA_setLocalPath( - const char *path) -{ - PM_setLocalBPDPath(path); -} - -/**************************************************************************** -RETURNS: -Pointer to the system wide PM library imports, or the internal version if none - -REMARKS: -Nothing special for this OS. -****************************************************************************/ -PM_imports * NAPI GA_getSystemPMImports(void) -{ - return &_PM_imports; -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp, - ibool shared) -{ - (void)gaExp; - (void)shared; - return false; -} - -#ifndef TEST_HARNESS -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI GA_queryFunctions( - GA_devCtx *dc, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.GA_queryFunctions(dc,id,funcs); -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI REF2D_queryFunctions( - REF2D_driver *ref2d, - N_uint32 id, - void _FAR_ *funcs) -{ - return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); -} -#endif - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { - haveRDTSC = true; - } - return true; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else - VTD_Get_Real_Time(&value->high,&value->low); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/gawin32.c b/board/MAI/bios_emulator/scitech/src/common/gawin32.c deleted file mode 100644 index 6944334..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/gawin32.c +++ /dev/null @@ -1,255 +0,0 @@ -/**************************************************************************** -* -* SciTech Nucleus Graphics Architecture -* -* Copyright (C) 1991-1998 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code contains proprietary technology | -* |owned by SciTech Software, Inc., located at 505 Wall Street, | -* |Chico, CA 95928 USA (http://www.scitechsoft.com). | -* | | -* |The contents of this file are subject to the SciTech Nucleus | -* |License; you may *not* use this file or related software except in | -* |compliance with the License. You may obtain a copy of the License | -* |at http://www.scitechsoft.com/nucleus-license.txt | -* | | -* |Software distributed under the License is distributed on an | -* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | -* |implied. See the License for the specific language governing | -* |rights and limitations under the License. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Win32 -* -* Description: OS specific Nucleus Graphics Architecture services for -* the Win32 operating system environments. -* -****************************************************************************/ - -#include "pm_help.h" -#include "pmapi.h" -#include -#include -#include -#define STRICT -#define WIN32_LEAN_AND_MEAN -#include - -/*------------------------- Global Variables ------------------------------*/ - -#define DLL_NAME "nga_w32.dll" - -extern HANDLE _PM_hDevice; -static HMODULE hModDLL = NULL; -static ibool useRing0Driver = false; -static ibool haveRDTSC; -static GA_largeInteger countFreq; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -REMARKS: -Loads the shared "nga_w32.dll" library from disk and connects to it. This -library is *always* located in the same directory as the Nucleus -graphics.bpd file. -****************************************************************************/ -static ibool LoadSharedDLL(void) -{ - char filename[PM_MAX_PATH]; - char bpdpath[PM_MAX_PATH]; - - /* Check if we have already loaded the DLL */ - if (hModDLL) - return true; - PM_init(); - - /* Open the DLL file */ - if (!PM_findBPD(DLL_NAME,bpdpath)) - return false; - strcpy(filename,bpdpath); - strcat(filename,DLL_NAME); - if ((hModDLL = LoadLibrary(filename)) == NULL) - return false; - return true; -} - -/**************************************************************************** -PARAMETERS: -path - Local path to the Nucleus driver files. - -REMARKS: -This function is used by the application program to override the location -of the Nucleus driver files that are loaded. Normally the loader code -will look in the system Nucleus directories first, then in the 'drivers' -directory relative to the current working directory, and finally relative -to the MGL_ROOT environment variable. - -Note that for Win32 we also call into the loaded PMHELP device driver -as necessary to change the local Nucleus path for system wide Nucleus -drivers. -****************************************************************************/ -void NAPI GA_setLocalPath( - const char *path) -{ - DWORD inBuf[1]; - DWORD outBuf[1],outCnt; - - PM_setLocalBPDPath(path); - if (_PM_hDevice != INVALID_HANDLE_VALUE) { - inBuf[0] = (DWORD)path; - DeviceIoControl(_PM_hDevice, PMHELP_GASETLOCALPATH32, - inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &outCnt, NULL); - } -} - -/**************************************************************************** -RETURNS: -Pointer to the system wide PM library imports, or the internal version if none - -REMARKS: -In order to support deploying new Nucleus drivers that may require updated -PM library functions, we check here to see if there is a system wide version -of the PM functions available. If so we return those functions for use with -the system wide Nucleus drivers, otherwise the compiled in version of the PM -library is used with the application local version of Nucleus. -****************************************************************************/ -PM_imports * NAPI GA_getSystemPMImports(void) -{ - PM_imports * pmImp; - PM_imports * (NAPIP _GA_getSystemPMImports)(void); - - if (LoadSharedDLL()) { - /* Note that Visual C++ build DLL's with only a single underscore in front - * of the exported name while Watcom C provides two of them. We check for - * both to allow working with either compiled DLL. - */ - if ((_GA_getSystemPMImports = (void*)GetProcAddress(hModDLL,"_GA_getSystemPMImports")) != NULL) { - if ((_GA_getSystemPMImports = (void*)GetProcAddress(hModDLL,"__GA_getSystemPMImports")) != NULL) { - pmImp = _GA_getSystemPMImports(); - memcpy(&_PM_imports,pmImp,MIN(_PM_imports.dwSize,pmImp->dwSize)); - return pmImp; - } - } - } - return &_PM_imports; -} - -/**************************************************************************** -PARAMETERS: -gaExp - Place to store the exported functions -shared - True if connecting to the shared, global Nucleus driver - -REMARKS: -For Win32 if we are connecting to the shared, global Nucleus driver (loaded -at ring 0) then we need to load a special nga_w32.dll library which contains -thunks to call down into the Ring 0 device driver as necessary. If we are -connecting to the application local Nucleus drivers (ie: Nucleus on DirectDraw -emulation layer) then we do nothing here. -****************************************************************************/ -ibool NAPI GA_getSharedExports( - GA_exports *gaExp, - ibool shared) -{ - GA_exports * exp; - GA_exports * (NAPIP _GA_getSystemGAExports)(void); - - useRing0Driver = false; - if (shared) { - if (!LoadSharedDLL()) - PM_fatalError("Unable to load " DLL_NAME "!"); - if ((_GA_getSystemGAExports = (void*)GetProcAddress(hModDLL,"_GA_getSystemGAExports")) == NULL) - if ((_GA_getSystemGAExports = (void*)GetProcAddress(hModDLL,"__GA_getSystemGAExports")) == NULL) - PM_fatalError("Unable to load " DLL_NAME "!"); - exp = _GA_getSystemGAExports(); - memcpy(gaExp,exp,MIN(gaExp->dwSize,exp->dwSize)); - useRing0Driver = true; - return true; - } - return false; -} - -#ifndef TEST_HARNESS -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI GA_queryFunctions( - GA_devCtx *dc, - N_uint32 id, - void _FAR_ *funcs) -{ - static ibool (NAPIP _GA_queryFunctions)(GA_devCtx *dc,N_uint32 id,void _FAR_ *funcs) = NULL; - - if (useRing0Driver) { - /* Call the version in nga_w32.dll if it is loaded */ - if (!_GA_queryFunctions) { - if ((_GA_queryFunctions = (void*)GetProcAddress(hModDLL,"_GA_queryFunctions")) == NULL) - if ((_GA_queryFunctions = (void*)GetProcAddress(hModDLL,"__GA_queryFunctions")) == NULL) - PM_fatalError("Unable to get exports from " DLL_NAME "!"); - } - return _GA_queryFunctions(dc,id,funcs); - } - return __GA_exports.GA_queryFunctions(dc,id,funcs); -} - -/**************************************************************************** -REMARKS: -Nothing special for this OS -****************************************************************************/ -ibool NAPI REF2D_queryFunctions( - REF2D_driver *ref2d, - N_uint32 id, - void _FAR_ *funcs) -{ - static ibool (NAPIP _REF2D_queryFunctions)(REF2D_driver *ref2d,N_uint32 id,void _FAR_ *funcs) = NULL; - - if (useRing0Driver) { - /* Call the version in nga_w32.dll if it is loaded */ - if (!_REF2D_queryFunctions) { - if ((_REF2D_queryFunctions = (void*)GetProcAddress(hModDLL,"_REF2D_queryFunctions")) == NULL) - if ((_REF2D_queryFunctions = (void*)GetProcAddress(hModDLL,"__REF2D_queryFunctions")) == NULL) - PM_fatalError("Unable to get exports from " DLL_NAME "!"); - } - return _REF2D_queryFunctions(ref2d,id,funcs); - } - return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); -} -#endif - -/**************************************************************************** -REMARKS: -This function initialises the high precision timing functions for the -Nucleus loader library. -****************************************************************************/ -ibool NAPI GA_TimerInit(void) -{ - if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { - haveRDTSC = true; - return true; - } - else if (QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq)) { - haveRDTSC = false; - return true; - } - return false; -} - -/**************************************************************************** -REMARKS: -This function reads the high resolution timer. -****************************************************************************/ -void NAPI GA_TimerRead( - GA_largeInteger *value) -{ - if (haveRDTSC) - _GA_readTimeStamp(value); - else - QueryPerformanceCounter((LARGE_INTEGER*)value); -} diff --git a/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c b/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c deleted file mode 100644 index 1d547e9..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c +++ /dev/null @@ -1,436 +0,0 @@ -/**************************************************************************** -* -* VESA Generalized Timing Formula (GTF) -* Version 1.1 -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Developed by: SciTech Software, Inc. -* -* Language: ANSI C -* Environment: Any. -* -* Description: C module for generating GTF compatible timings given a set -* of input requirements. Translated from the original GTF -* 1.14 spreadsheet definition. -* -* Compile with #define TESTING to build a command line test -* program. -* -* NOTE: The code in here has been written for clarity and -* to follow the original GTF spec as closely as -* possible. -* -****************************************************************************/ - -#include "gtf.h" -#ifndef __WIN32_VXD__ -#include -#include -#include -#include -#include -#endif - -/*------------------------- Global Variables ------------------------------*/ - -static GTF_constants GC = { - 1.8, /* Margin size as percentage of display */ - 8, /* Character cell granularity */ - 1, /* Minimum front porch in lines/chars */ - 3, /* Width of V sync in lines */ - 8, /* Width of H sync as percent of total */ - 550, /* Minimum vertical sync + back porch (us) */ - 600, /* Blanking formula gradient */ - 40, /* Blanking formula offset */ - 128, /* Blanking formula scaling factor */ - 20, /* Blanking formula scaling factor weight */ - }; - -/*-------------------------- Implementation -------------------------------*/ - -#ifdef __WIN32_VXD__ -/* These functions are not supported in a VxD, so we stub them out so this - * module will at least compile. Calling the functions in here will do - * something wierd! - */ -double sqrt(double x) -{ return x; } - -double floor(double x) -{ return x; } - -double pow(double x,double y) -{ return x*y; } -#endif - -static double round(double v) -{ - return floor(v + 0.5); -} - -static void GetInternalConstants(GTF_constants *c) -/**************************************************************************** -* -* Function: GetInternalConstants -* Parameters: c - Place to store the internal constants -* -* Description: Calculates the rounded, internal set of GTF constants. -* These constants are different to the real GTF constants -* that can be set up for the monitor. The calculations to -* get these real constants are defined in the 'Work Area' -* after the constants are defined in the Excel spreadsheet. -* -****************************************************************************/ -{ - c->margin = GC.margin; - c->cellGran = round(GC.cellGran); - c->minPorch = round(GC.minPorch); - c->vSyncRqd = round(GC.vSyncRqd); - c->hSync = GC.hSync; - c->minVSyncBP = GC.minVSyncBP; - if (GC.k == 0) - c->k = 0.001; - else - c->k = GC.k; - c->m = (c->k / 256) * GC.m; - c->c = (GC.c - GC.j) * (c->k / 256) + GC.j; - c->j = GC.j; -} - -void GTF_calcTimings(double hPixels,double vLines,double freq, - int type,ibool wantMargins,ibool wantInterlace,GTF_timings *t) -/**************************************************************************** -* -* Function: GTF_calcTimings -* Parameters: hPixels - X resolution -* vLines - Y resolution -* freq - Frequency (Hz, KHz or MHz depending on type) -* type - 1 - vertical, 2 - horizontal, 3 - dot clock -* margins - True if margins should be generated -* interlace - True if interlaced timings to be generated -* t - Place to store the resulting timings -* -* Description: Calculates a set of GTF timing parameters given a specified -* resolution and vertical frequency. The horizontal frequency -* and dot clock will be automatically generated by this -* routines. -* -* For interlaced modes the CRTC parameters are calculated for -* a single field, so will be half what would be used in -* a non-interlaced mode. -* -****************************************************************************/ -{ - double interlace,vFieldRate,hPeriod; - double topMarginLines,botMarginLines; - double leftMarginPixels,rightMarginPixels; - double hPeriodEst,vSyncBP,vBackPorch; - double vTotalLines,vFieldRateEst; - double hTotalPixels,hTotalActivePixels,hBlankPixels; - double idealDutyCycle,hSyncWidth,hSyncBP,hBackPorch; - double idealHPeriod; - double vFreq,hFreq,dotClock; - GTF_constants c; - - /* Get rounded GTF constants used for internal calculations */ - GetInternalConstants(&c); - - /* Move input parameters into appropriate variables */ - vFreq = hFreq = dotClock = freq; - - /* Round pixels to character cell granularity */ - hPixels = round(hPixels / c.cellGran) * c.cellGran; - - /* For interlaced mode halve the vertical parameters, and double - * the required field refresh rate. - */ - vFieldRate = vFreq; - interlace = 0; - if (wantInterlace) - dotClock *= 2; - - /* Determine the lines for margins */ - if (wantMargins) { - topMarginLines = round(c.margin / 100 * vLines); - botMarginLines = round(c.margin / 100 * vLines); - } - else { - topMarginLines = 0; - botMarginLines = 0; - } - - if (type != GTF_lockPF) { - if (type == GTF_lockVF) { - /* Estimate the horizontal period */ - hPeriodEst = ((1/vFieldRate) - (c.minVSyncBP/1000000)) / - (vLines + (2*topMarginLines) + c.minPorch + interlace) * 1000000; - - /* Find the number of lines in vSync + back porch */ - vSyncBP = round(c.minVSyncBP / hPeriodEst); - } - else if (type == GTF_lockHF) { - /* Find the number of lines in vSync + back porch */ - vSyncBP = round((c.minVSyncBP * hFreq) / 1000); - } - - /* Find the number of lines in the V back porch alone */ - vBackPorch = vSyncBP - c.vSyncRqd; - - /* Find the total number of lines in the vertical period */ - vTotalLines = vLines + topMarginLines + botMarginLines + vSyncBP - + interlace + c.minPorch; - - if (type == GTF_lockVF) { - /* Estimate the vertical frequency */ - vFieldRateEst = 1000000 / (hPeriodEst * vTotalLines); - - /* Find the actual horizontal period */ - hPeriod = (hPeriodEst * vFieldRateEst) / vFieldRate; - - /* Find the actual vertical field frequency */ - vFieldRate = 1000000 / (hPeriod * vTotalLines); - } - else if (type == GTF_lockHF) { - /* Find the actual vertical field frequency */ - vFieldRate = (hFreq / vTotalLines) * 1000; - } - } - - /* Find the number of pixels in the left and right margins */ - if (wantMargins) { - leftMarginPixels = round(hPixels * c.margin) / (100 * c.cellGran); - rightMarginPixels = round(hPixels * c.margin) / (100 * c.cellGran); - } - else { - leftMarginPixels = 0; - rightMarginPixels = 0; - } - - /* Find the total number of active pixels in image + margins */ - hTotalActivePixels = hPixels + leftMarginPixels + rightMarginPixels; - - if (type == GTF_lockVF) { - /* Find the ideal blanking duty cycle */ - idealDutyCycle = c.c - ((c.m * hPeriod) / 1000); - } - else if (type == GTF_lockHF) { - /* Find the ideal blanking duty cycle */ - idealDutyCycle = c.c - (c.m / hFreq); - } - else if (type == GTF_lockPF) { - /* Find ideal horizontal period from blanking duty cycle formula */ - idealHPeriod = (((c.c - 100) + (sqrt((pow(100-c.c,2)) + - (0.4 * c.m * (hTotalActivePixels + rightMarginPixels + - leftMarginPixels) / dotClock)))) / (2 * c.m)) * 1000; - - /* Find the ideal blanking duty cycle */ - idealDutyCycle = c.c - ((c.m * idealHPeriod) / 1000); - } - - /* Find the number of pixels in blanking time */ - hBlankPixels = round((hTotalActivePixels * idealDutyCycle) / - ((100 - idealDutyCycle) * c.cellGran)) * c.cellGran; - - /* Find the total number of pixels */ - hTotalPixels = hTotalActivePixels + hBlankPixels; - - /* Find the horizontal back porch */ - hBackPorch = round((hBlankPixels / 2) / c.cellGran) * c.cellGran; - - /* Find the horizontal sync width */ - hSyncWidth = round(((c.hSync/100) * hTotalPixels) / c.cellGran) * c.cellGran; - - /* Find the horizontal sync + back porch */ - hSyncBP = hBackPorch + hSyncWidth; - - if (type == GTF_lockPF) { - /* Find the horizontal frequency */ - hFreq = (dotClock / hTotalPixels) * 1000; - - /* Find the number of lines in vSync + back porch */ - vSyncBP = round((c.minVSyncBP * hFreq) / 1000); - - /* Find the number of lines in the V back porch alone */ - vBackPorch = vSyncBP - c.vSyncRqd; - - /* Find the total number of lines in the vertical period */ - vTotalLines = vLines + topMarginLines + botMarginLines + vSyncBP - + interlace + c.minPorch; - - /* Find the actual vertical field frequency */ - vFieldRate = (hFreq / vTotalLines) * 1000; - } - else { - if (type == GTF_lockVF) { - /* Find the horizontal frequency */ - hFreq = 1000 / hPeriod; - } - else if (type == GTF_lockHF) { - /* Find the horizontal frequency */ - hPeriod = 1000 / hFreq; - } - - /* Find the pixel clock frequency */ - dotClock = hTotalPixels / hPeriod; - } - - /* Return the computed frequencies */ - t->vFreq = vFieldRate; - t->hFreq = hFreq; - t->dotClock = dotClock; - - /* Determine the vertical timing parameters */ - t->h.hTotal = (int)hTotalPixels; - t->h.hDisp = (int)hTotalActivePixels; - t->h.hSyncStart = t->h.hTotal - (int)hSyncBP; - t->h.hSyncEnd = t->h.hTotal - (int)hBackPorch; - t->h.hFrontPorch = t->h.hSyncStart - t->h.hDisp; - t->h.hSyncWidth = (int)hSyncWidth; - t->h.hBackPorch = (int)hBackPorch; - - /* Determine the vertical timing parameters */ - t->v.vTotal = (int)vTotalLines; - t->v.vDisp = (int)vLines; - t->v.vSyncStart = t->v.vTotal - (int)vSyncBP; - t->v.vSyncEnd = t->v.vTotal - (int)vBackPorch; - t->v.vFrontPorch = t->v.vSyncStart - t->v.vDisp; - t->v.vSyncWidth = (int)c.vSyncRqd; - t->v.vBackPorch = (int)vBackPorch; - if (wantInterlace) { - /* Halve the timings for interlaced modes */ - t->v.vTotal /= 2; - t->v.vDisp /= 2; - t->v.vSyncStart /= 2; - t->v.vSyncEnd /= 2; - t->v.vFrontPorch /= 2; - t->v.vSyncWidth /= 2; - t->v.vBackPorch /= 2; - t->dotClock /= 2; - } - - /* Mark as GTF timing using the sync polarities */ - t->interlace = (wantInterlace) ? 'I' : 'N'; - t->hSyncPol = '-'; - t->vSyncPol = '+'; -} - -void GTF_getConstants(GTF_constants *constants) -{ *constants = GC; } - -void GTF_setConstants(GTF_constants *constants) -{ GC = *constants; } - -#ifdef TESTING_GTF - -void main(int argc,char *argv[]) -{ - FILE *f; - double xPixels,yPixels,freq; - ibool interlace; - GTF_timings t; - - if (argc != 5 && argc != 6) { - printf("Usage: GTFCALC [[Hz] [KHz] [MHz]] [I]\n"); - printf("\n"); - printf("where is the horizontal resolution of the mode, is the\n"); - printf("vertical resolution of the mode. The value will be the frequency to\n"); - printf("drive the calculations, and will be either the vertical frequency (in Hz)\n"); - printf("the horizontal frequency (in KHz) or the dot clock (in MHz). To generate\n"); - printf("timings for an interlaced mode, add 'I' to the end of the command line.\n"); - printf("\n"); - printf("For example to generate timings for 640x480 at 60Hz vertical:\n"); - printf("\n"); - printf(" GTFCALC 640 480 60 Hz\n"); - printf("\n"); - printf("For example to generate timings for 640x480 at 31.5KHz horizontal:\n"); - printf("\n"); - printf(" GTFCALC 640 480 31.5 KHz\n"); - printf("\n"); - printf("For example to generate timings for 640x480 with a 25.175Mhz dot clock:\n"); - printf("\n"); - printf(" GTFCALC 640 480 25.175 MHz\n"); - printf("\n"); - printf("GTFCALC will print a summary of the results found, and dump the CRTC\n"); - printf("values to the UVCONFIG.CRT file in the format used by SciTech Display Doctor.\n"); - exit(1); - } - - /* Get values from command line */ - xPixels = atof(argv[1]); - yPixels = atof(argv[2]); - freq = atof(argv[3]); - interlace = ((argc == 6) && (argv[5][0] == 'I')); - - /* Compute the CRTC timings */ - if (toupper(argv[4][0]) == 'H') - GTF_calcTimings(xPixels,yPixels,freq,GTF_lockVF,false,interlace,&t); - else if (toupper(argv[4][0]) == 'K') - GTF_calcTimings(xPixels,yPixels,freq,GTF_lockHF,false,interlace,&t); - else if (toupper(argv[4][0]) == 'M') - GTF_calcTimings(xPixels,yPixels,freq,GTF_lockPF,false,interlace,&t); - else { - printf("Unknown command line!\n"); - exit(1); - } - - /* Dump summary info to standard output */ - printf("CRTC values for %.0fx%.0f @ %.2f %s\n", xPixels, yPixels, freq, argv[4]); - printf("\n"); - printf(" hTotal = %-4d vTotal = %-4d\n", - t.h.hTotal, t.v.vTotal); - printf(" hDisp = %-4d vDisp = %-4d\n", - t.h.hDisp, t.v.vDisp); - printf(" hSyncStart = %-4d vSyncStart = %-4d\n", - t.h.hSyncStart, t.v.vSyncStart); - printf(" hSyncEnd = %-4d vSyncEnd = %-4d\n", - t.h.hSyncEnd, t.v.vSyncEnd); - printf(" hFrontPorch = %-4d vFrontPorch = %-4d\n", - t.h.hFrontPorch, t.v.vFrontPorch); - printf(" hSyncWidth = %-4d vSyncWidth = %-4d\n", - t.h.hSyncWidth, t.v.vSyncWidth); - printf(" hBackPorch = %-4d vBackPorch = %-4d\n", - t.h.hBackPorch, t.v.vBackPorch); - printf("\n"); - printf(" Interlaced = %s\n", (t.interlace == 'I') ? "Yes" : "No"); - printf(" H sync pol = %c\n", t.hSyncPol); - printf(" V sync pol = %c\n", t.vSyncPol); - printf("\n"); - printf(" Vert freq = %.2f Hz\n", t.vFreq); - printf(" Horiz freq = %.2f KHz\n", t.hFreq); - printf(" Dot Clock = %.2f Mhz\n", t.dotClock); - - /* Dump to file in format used by SciTech Display Doctor */ - if ((f = fopen("UVCONFIG.CRT","w")) != NULL) { - fprintf(f, "[%.0f %.0f]\n", xPixels, yPixels); - fprintf(f, "%d %d %d %d '%c' %s\n", - t.h.hTotal, t.h.hDisp, - t.h.hSyncStart, t.h.hSyncEnd, - t.hSyncPol, (t.interlace == 'I') ? "I" : "NI"); - fprintf(f, "%d %d %d %d '%c'\n", - t.v.vTotal, t.v.vDisp, - t.v.vSyncStart, t.v.vSyncEnd, - t.vSyncPol); - fprintf(f, "%.2f\n", t.dotClock); - fclose(f); - } -} - -#endif /* TESTING */ diff --git a/board/MAI/bios_emulator/scitech/src/common/libcimp.c b/board/MAI/bios_emulator/scitech/src/common/libcimp.c deleted file mode 100644 index ab73ad5..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/libcimp.c +++ /dev/null @@ -1,827 +0,0 @@ -/**************************************************************************** -* -* SciTech MGL Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Module to implement a the OS specific side of the Binary -* Portable DLL C runtime library. The functions in here -* are imported into the Binary Portable DLL's to implement -* OS specific services. -* -****************************************************************************/ - -#include "pmapi.h" -#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) -#include "drvlib/peloader.h" -#include "drvlib/attrib.h" -#include "drvlib/libc/init.h" -#define __BUILDING_PE_LOADER__ -#include "drvlib/libc/file.h" -#if defined(__WIN32_VXD__) -#include "vxdfile.h" -#endif -#else -#include -#include -#include -#include -#include -#include -#include -#if defined(__GNUC__) || defined(__UNIX__) -#include -#include -#include -#else -#include -#endif -#include "drvlib/attrib.h" -#include "drvlib/libc/init.h" -#define __BUILDING_PE_LOADER__ -#include "drvlib/libc/file.h" -#if defined(__WINDOWS__) || defined(TNT) || defined(__RTTARGET__) -#define WIN32_LEAN_AND_MEAN -#define STRICT -#include -#endif -#ifdef __MSDOS__ -#include -#endif -#ifdef __OS2__ -#define INCL_DOS -#define INCL_DOSERRORS -#define INCL_SUB -#include -#endif -#endif - -/* No text or binary modes for Unix */ - -#ifndef O_BINARY -#define O_BINARY 0 -#define O_TEXT 0 -#endif - -/*--------------------------- Global variables ----------------------------*/ - -#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) -#define MAX_FILES 16 -static FILE *openHandles[MAX_FILES] = {NULL}; -#endif - -/* stub functions */ -void _CDECL stub_abort(void); -int _CDECL stub_atexit(void (*)(void)); -void * _CDECL stub_calloc(size_t _nelem, size_t _size); -void _CDECL stub_exit(int _status); -void _CDECL stub_free(void *_ptr); -char * _CDECL stub_getenv(const char *_name); -void * _CDECL stub_malloc(size_t _size); -void * _CDECL stub_realloc(void *_ptr, size_t _size); -int _CDECL stub_system(const char *_s); -int _CDECL stub_putenv(const char *_val); - -/* stub functions */ -int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode); -int _CDECL stub_access(const char *_path, int _amode); -int _CDECL stub_close(int _fildes); -off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence); -size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte); -int _CDECL stub_unlink(const char *_path); -size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte); -int _CDECL stub_isatty(int _fildes); - -/* stub functions */ -int _CDECL stub_remove(const char *_filename); -int _CDECL stub_rename(const char *_old, const char *_new); - -/* stub functions */ -time_t _CDECL stub_time(time_t *_tod); - -/* stub functions */ -int _CDECL stub_raise(int); -void * _CDECL stub_signal(int, void *); - -/* functions */ -#define stub_OS_setfileattr _OS_setfileattr -#define stub_OS_getcurrentdate _OS_getcurrentdate - -LIBC_imports _VARAPI ___imports = { - sizeof(LIBC_imports), - - /* exports */ - stub_abort, - stub_atexit, - stub_calloc, - stub_exit, - stub_free, - stub_getenv, - stub_malloc, - stub_realloc, - stub_system, - stub_putenv, - - /* exports */ - stub_open, - stub_access, - stub_close, - stub_lseek, - stub_read, - stub_unlink, - stub_write, - stub_isatty, - - /* exports */ - stub_remove, - stub_rename, - - /* functions */ - stub_raise, - stub_signal, - - /* exports */ - stub_time, - - /* exports */ - stub_OS_setfileattr, - stub_OS_getcurrentdate, - }; - -/*---------------------- Stub function implementation ---------------------*/ - -/* stub functions */ -void _CDECL stub_abort(void) -{ -#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__) - abort(); -#endif -} - -int _CDECL stub_atexit(void (*func)(void)) -{ -#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__) - return atexit((void(*)(void))func); -#else - return -1; -#endif -} - -void * _CDECL stub_calloc(size_t _nelem, size_t _size) -{ return __PM_calloc(_nelem,_size); } - -void _CDECL stub_exit(int _status) -{ -#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__) - exit(_status); -#endif -} - -void _CDECL stub_free(void *_ptr) -{ __PM_free(_ptr); } - -char * _CDECL stub_getenv(const char *_name) -{ -#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__) - return NULL; -#else - return getenv(_name); -#endif -} - -void * _CDECL stub_malloc(size_t _size) -{ return __PM_malloc(_size); } - -void * _CDECL stub_realloc(void *_ptr, size_t _size) -{ return __PM_realloc(_ptr,_size); } - -int _CDECL stub_system(const char *_s) -{ -#if defined(__WINDOWS__) || defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__) || defined(__RTTARGET__) - (void)_s; - return -1; -#else - return system(_s); -#endif -} - -int _CDECL stub_putenv(const char *_val) -{ -#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__) - return -1; -#else - return putenv((char*)_val); -#endif -} - -time_t _CDECL stub_time(time_t *_tod) -{ -#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__) - return 0; -#else - return time(_tod); -#endif -} - -#if defined(__MSDOS__) - -#if defined(TNT) && defined(_MSC_VER) - -void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) -{ SetFileAttributes((LPSTR)filename, (DWORD)attrib); } - -#else - -void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) -{ _dos_setfileattr(filename,attrib); } - -#endif - -#elif defined(__WIN32_VXD__) - -#define USE_LOCAL_FILEIO -#define USE_LOCAL_GETDATE - -/* stub functions */ -int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) -{ - char mode[10]; - int i; - - /* Find an empty file handle to use */ - for (i = 3; i < MAX_FILES; i++) { - if (!openHandles[i]) - break; - } - if (openHandles[i]) - return -1; - - /* Find the open flags to use */ - if (_oflag & ___O_TRUNC) - strcpy(mode,"w"); - else if (_oflag & ___O_CREAT) - strcpy(mode,"a"); - else - strcpy(mode,"r"); - if (_oflag & ___O_BINARY) - strcat(mode,"b"); - if (_oflag & ___O_TEXT) - strcat(mode,"t"); - - /* Open the file and store the file handle */ - if ((openHandles[i] = fopen(_path,mode)) == NULL) - return -1; - return i; -} - -int _CDECL stub_access(const char *_path, int _amode) -{ return -1; } - -int _CDECL stub_close(int _fildes) -{ - if (_fildes >= 3 && openHandles[_fildes]) { - fclose(openHandles[_fildes]); - openHandles[_fildes] = NULL; - } - return 0; -} - -off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) -{ - if (_fildes >= 3) { - fseek(openHandles[_fildes],_offset,_whence); - return ftell(openHandles[_fildes]); - } - return 0; -} - -size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) -{ - if (_fildes >= 3) - return fread(_buf,1,_nbyte,openHandles[_fildes]); - return 0; -} - -int _CDECL stub_unlink(const char *_path) -{ - WORD error; - - if (initComplete) { - if (R0_DeleteFile((char*)_path,0,&error)) - return 0; - return -1; - } - else - return i_remove(_path); -} - -size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) -{ - if (_fildes >= 3) - return fwrite(_buf,1,_nbyte,openHandles[_fildes]); - return _nbyte; -} - -int _CDECL stub_isatty(int _fildes) -{ return 0; } - -/* stub functions */ -int _CDECL stub_remove(const char *_filename) -{ return stub_unlink(_filename); } - -int _CDECL stub_rename(const char *_old, const char *_new) -{ return -1; } - -void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) -{ - WORD error; - if (initComplete) - R0_SetFileAttributes((char*)filename,attrib,&error); -} - -/* Return the current date in days since 1/1/1980 */ -ulong _CDECL _OS_getcurrentdate(void) -{ - DWORD date; - VTD_Get_Date_And_Time(&date); - return date; -} - -#elif defined(__NT_DRIVER__) - -#define USE_LOCAL_FILEIO -#define USE_LOCAL_GETDATE - -/* stub functions */ -int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) -{ - char mode[10]; - int i; - - /* Find an empty file handle to use */ - for (i = 3; i < MAX_FILES; i++) { - if (!openHandles[i]) - break; - } - if (openHandles[i]) - return -1; - - /* Find the open flags to use */ - if (_oflag & ___O_TRUNC) - strcpy(mode,"w"); - else if (_oflag & ___O_CREAT) - strcpy(mode,"a"); - else - strcpy(mode,"r"); - if (_oflag & ___O_BINARY) - strcat(mode,"b"); - if (_oflag & ___O_TEXT) - strcat(mode,"t"); - - /* Open the file and store the file handle */ - if ((openHandles[i] = fopen(_path,mode)) == NULL) - return -1; - return i; -} - -int _CDECL stub_close(int _fildes) -{ - if (_fildes >= 3 && openHandles[_fildes]) { - fclose(openHandles[_fildes]); - openHandles[_fildes] = NULL; - } - return 0; -} - -off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) -{ - if (_fildes >= 3) { - fseek(openHandles[_fildes],_offset,_whence); - return ftell(openHandles[_fildes]); - } - return 0; -} - -size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) -{ - if (_fildes >= 3) - return fread(_buf,1,_nbyte,openHandles[_fildes]); - return 0; -} - -size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) -{ - if (_fildes >= 3) - return fwrite(_buf,1,_nbyte,openHandles[_fildes]); - return _nbyte; -} - -int _CDECL stub_access(const char *_path, int _amode) -{ return -1; } - -int _CDECL stub_isatty(int _fildes) -{ return 0; } - -int _CDECL stub_unlink(const char *_path) -{ - /* TODO: Implement this! */ - return -1; -} - -/* stub functions */ -int _CDECL stub_remove(const char *_filename) -{ return stub_unlink(_filename); } - -int _CDECL stub_rename(const char *_old, const char *_new) -{ - /* TODO: Implement this! */ - return -1; -} - -void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) -{ - uint _attr = 0; - if (attrib & __A_RDONLY) - _attr |= FILE_ATTRIBUTE_READONLY; - if (attrib & __A_HIDDEN) - _attr |= FILE_ATTRIBUTE_HIDDEN; - if (attrib & __A_SYSTEM) - _attr |= FILE_ATTRIBUTE_SYSTEM; - PM_setFileAttr(filename,_attr); -} - -/* Return the current date in days since 1/1/1980 */ -ulong _CDECL _OS_getcurrentdate(void) -{ - TIME_FIELDS tm; - _int64 count,count_1_1_1980; - - tm.Year = 1980; - tm.Month = 1; - tm.Day = 1; - tm.Hour = 0; - tm.Minute = 0; - tm.Second = 0; - tm.Milliseconds = 0; - tm.Weekday = 0; - RtlTimeFieldsToTime(&tm,(PLARGE_INTEGER)&count_1_1_1980); - KeQuerySystemTime((PLARGE_INTEGER)&count); - return (ulong)( (count - count_1_1_1980) / ((_int64)24 * (_int64)3600 * (_int64)10000000) ); -} - -#elif defined(__WINDOWS32__) || defined(__RTTARGET__) - -void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) -{ SetFileAttributes((LPSTR)filename, (DWORD)attrib); } - -#elif defined(__OS2__) - -#define USE_LOCAL_FILEIO - -#ifndef W_OK -#define W_OK 0x02 -#endif - -void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) -{ - FILESTATUS3 s; - if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s))) - return; - s.attrFile = attrib; - DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s),0L); -} - -/* stub functions */ - -#define BUF_SIZE 4096 - -/* Note: the implementation of the standard Unix-ish handle-based I/O isn't - * complete - but that wasn't the intent either. Note also that we - * don't presently support text file I/O, so all text files end - * up in Unix format (and are not translated!). - */ -int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) -{ - HFILE handle; - ULONG error, actiontaken, openflag, openmode; - char path[PM_MAX_PATH]; - - /* Determine open flags */ - if (_oflag & ___O_CREAT) { - if (_oflag & ___O_EXCL) - openflag = OPEN_ACTION_FAIL_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; - else if (_oflag & ___O_TRUNC) - openflag = OPEN_ACTION_REPLACE_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; - else - openflag = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; - } - else if (_oflag & ___O_TRUNC) - openflag = OPEN_ACTION_REPLACE_IF_EXISTS; - else - openflag = OPEN_ACTION_OPEN_IF_EXISTS; - - /* Determine open mode flags */ - if (_oflag & ___O_RDONLY) - openmode = OPEN_ACCESS_READONLY | OPEN_SHARE_DENYNONE; - else if (_oflag & ___O_WRONLY) - openmode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_DENYWRITE; - else - openmode = OPEN_ACCESS_READWRITE | OPEN_SHARE_DENYWRITE; - - /* Copy the path to a variable on the stack. We need to do this - * for OS/2 as when the drivers are loaded into shared kernel - * memory, we can't pass an address from that memory range to - * this function. - */ - strcpy(path,_path); - if (DosOpen(path, &handle, &actiontaken, 0, FILE_NORMAL, - openflag, openmode, NULL) != NO_ERROR) - return -1; - - /* Handle append mode of operation */ - if (_oflag & ___O_APPEND) { - if (DosSetFilePtr(handle, 0, FILE_END, &error) != NO_ERROR) - return -1; - } - return handle; -} - -int _CDECL stub_access(const char *_path, int _amode) -{ - char path[PM_MAX_PATH]; - FILESTATUS fs; - - /* Copy the path to a variable on the stack. We need to do this - * for OS/2 as when the drivers are loaded into shared kernel - * memory, we can't pass an address from that memory range to - * this function. - */ - strcpy(path,_path); - if (DosQueryPathInfo(path, FIL_STANDARD, &fs, sizeof(fs)) != NO_ERROR) - return -1; - if ((_amode & W_OK) && (fs.attrFile & FILE_READONLY)) - return -1; - return 0; -} - -int _CDECL stub_close(int _fildes) -{ - if (DosClose(_fildes) != NO_ERROR) - return -1; - return 0; -} - -off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) -{ - ULONG cbActual, origin; - - switch (_whence) { - case SEEK_CUR: - origin = FILE_CURRENT; - break; - case SEEK_END: - origin = FILE_END; - break; - default: - origin = FILE_BEGIN; - } - if (DosSetFilePtr(_fildes, _offset, origin, &cbActual) != NO_ERROR) - return -1; - return cbActual; -} - -size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) -{ - ULONG cbActual = 0,cbRead; - uchar *p = _buf; - uchar file_io_buf[BUF_SIZE]; - - /* We need to perform the physical read in chunks into a - * a temporary static buffer, since the buffer passed in may be - * in kernel space and will cause DosRead to bail internally. - */ - while (_nbyte > BUF_SIZE) { - if (DosRead(_fildes, file_io_buf, BUF_SIZE, &cbRead) != NO_ERROR) - return -1; - cbActual += cbRead; - memcpy(p,file_io_buf,BUF_SIZE); - p += BUF_SIZE; - _nbyte -= BUF_SIZE; - } - if (_nbyte) { - if (DosRead(_fildes, file_io_buf, _nbyte, &cbRead) != NO_ERROR) - return -1; - cbActual += cbRead; - memcpy(p,file_io_buf,_nbyte); - } - return cbActual; -} - -size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) -{ - ULONG cbActual = 0,cbWrite; - uchar *p = (PVOID)_buf; - uchar file_io_buf[BUF_SIZE]; - - /* We need to perform the physical write in chunks from a - * a temporary static buffer, since the buffer passed in may be - * in kernel space and will cause DosWrite to bail internally. - */ - while (_nbyte > BUF_SIZE) { - memcpy(file_io_buf,p,BUF_SIZE); - if (DosWrite(_fildes, file_io_buf, BUF_SIZE, &cbWrite) != NO_ERROR) - return -1; - cbActual += cbWrite; - p += BUF_SIZE; - _nbyte -= BUF_SIZE; - } - if (_nbyte) { - memcpy(file_io_buf,p,_nbyte); - if (DosWrite(_fildes, file_io_buf, _nbyte, &cbWrite) != NO_ERROR) - return -1; - cbActual += cbWrite; - } - return cbActual; -} - -int _CDECL stub_unlink(const char *_path) -{ - char path[PM_MAX_PATH]; - - /* Copy the path to a variable on the stack. We need to do this - * for OS/2 as when the drivers are loaded into shared kernel - * memory, we can't pass an address from that memory range to - * this function. - */ - strcpy(path,_path); - if (DosDelete(path) != NO_ERROR) - return -1; - return 0; -} - -int _CDECL stub_isatty(int _fildes) -{ - ULONG htype, flags; - - if (DosQueryHType(_fildes, &htype, &flags) != NO_ERROR) - return 0; - return ((htype & 0xFF) == HANDTYPE_DEVICE); -} - -/* stub functions */ -int _CDECL stub_remove(const char *_path) -{ - char path[PM_MAX_PATH]; - - /* Copy the path to a variable on the stack. We need to do this - * for OS/2 as when the drivers are loaded into shared kernel - * memory, we can't pass an address from that memory range to - * this function. - */ - strcpy(path,_path); - if (DosDelete(path) != NO_ERROR) - return -1; - return 0; -} - -int _CDECL stub_rename(const char *_old, const char *_new) -{ - char old[PM_MAX_PATH]; - char new[PM_MAX_PATH]; - - /* Copy the path to a variable on the stack. We need to do this - * for OS/2 as when the drivers are loaded into shared kernel - * memory, we can't pass an address from that memory range to - * this function. - */ - strcpy(old,_old); - strcpy(new,_new); - if (DosMove(old, new) != NO_ERROR) - return -1; - return 0; -} - -#else - -void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) -{ /* Unable to set hidden, system attributes on Unix. */ } - -#endif - -#ifndef USE_LOCAL_FILEIO - -/* stub functions */ -int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) -{ - int oflag_tab[] = { - ___O_RDONLY, O_RDONLY, - ___O_WRONLY, O_WRONLY, - ___O_RDWR, O_RDWR, - ___O_BINARY, O_BINARY, - ___O_TEXT, O_TEXT, - ___O_CREAT, O_CREAT, - ___O_EXCL, O_EXCL, - ___O_TRUNC, O_TRUNC, - ___O_APPEND, O_APPEND, - }; - int i,oflag = 0; - - /* Translate the oflag's to the OS dependent versions */ - for (i = 0; i < sizeof(oflag_tab) / sizeof(int); i += 2) { - if (_oflag & oflag_tab[i]) - oflag |= oflag_tab[i+1]; - } - return open(_path,oflag,_mode); -} - -int _CDECL stub_access(const char *_path, int _amode) -{ return access(_path,_amode); } - -int _CDECL stub_close(int _fildes) -{ return close(_fildes); } - -off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) -{ return lseek(_fildes,_offset,_whence); } - -size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) -{ return read(_fildes,_buf,_nbyte); } - -int _CDECL stub_unlink(const char *_path) -{ return unlink(_path); } - -size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) -{ return write(_fildes,_buf,_nbyte); } - -int _CDECL stub_isatty(int _fildes) -{ return isatty(_fildes); } - -/* stub functions */ -int _CDECL stub_remove(const char *_filename) -{ return remove(_filename); } - -int _CDECL stub_rename(const char *_old, const char *_new) -{ return rename(_old,_new); } - -#endif - -#ifndef USE_LOCAL_GETDATE - -/* Return the current date in days since 1/1/1980 */ -ulong _CDECL _OS_getcurrentdate(void) -{ - struct tm refTime; - refTime.tm_year = 80; - refTime.tm_mon = 0; - refTime.tm_mday = 1; - refTime.tm_hour = 0; - refTime.tm_min = 0; - refTime.tm_sec = 0; - refTime.tm_isdst = -1; - return (time(NULL) - mktime(&refTime)) / (24 * 3600L); -} - -#endif - -int _CDECL stub_raise(int sig) -{ -#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__) - return -1; -#else - return raise(sig); -#endif -} - -#ifdef __WINDOWS32__ -typedef void (*__code_ptr)(int); -#else -typedef void (*__code_ptr)(); -#endif - -void * _CDECL stub_signal(int sig, void *handler) -{ -#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__) - return NULL; -#else - return (void*)signal(sig,(__code_ptr)handler); -#endif -} diff --git a/board/MAI/bios_emulator/scitech/src/common/makefile b/board/MAI/bios_emulator/scitech/src/common/makefile deleted file mode 100644 index 5aac038..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/makefile +++ /dev/null @@ -1,18 +0,0 @@ -############################################################################# -# -# Copyright (C) 1996 SciTech Software. -# All rights reserved. -# -# Descripton: Makefile for UniVBE(tm), UniPOWER(tm), UVBELib(tm) and -# DPMSLib library files. Requires Borland C++ 4.52 to build -# some components. -# -# $Date: 2002/10/02 15:35:20 $ $Author: hfrieden $ -# -############################################################################# - -CFLAGS += -DTESTING_GTF - -gtfcalc$E: gtfcalc$O - -.INCLUDE: "$(SCITECH)/makedefs/common.mk" diff --git a/board/MAI/bios_emulator/scitech/src/common/peloader.c b/board/MAI/bios_emulator/scitech/src/common/peloader.c deleted file mode 100644 index a134bb0..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/peloader.c +++ /dev/null @@ -1,586 +0,0 @@ -/**************************************************************************** -* -* SciTech MGL Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Module to implement a simple Portable Binary DLL loader -* library. This library can be used to load PE DLL's under -* any Intel based OS, provided the DLL's do not have any -* imports in the import table. -* -* NOTE: This loader module expects the DLL's to be built with -* Watcom C++ and may produce unexpected results with -* DLL's linked by another compiler. -* -****************************************************************************/ - -#include "drvlib/peloader.h" -#include "pmapi.h" -#include "drvlib/os/os.h" -#include "drvlib/libc/init.h" -#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) -#define WIN32_LEAN_AND_MEAN -#define STRICT -#include -#endif -#include "drvlib/pe.h" - -/*--------------------------- Global variables ----------------------------*/ - -static int result = PE_ok; - -/*------------------------- Implementation --------------------------------*/ - -/**************************************************************************** -PARAMETERS: -f - Handle to open file to read driver from -startOffset - Offset to the start of the driver within the file - -RETURNS: -Handle to loaded PE DLL, or NULL on failure. - -REMARKS: -This function loads a Portable Binary DLL library from disk, relocates -the code and returns a handle to the loaded library. This function is the -same as the regular PE_loadLibrary except that it take a handle to an -open file and an offset within that file for the DLL to load. -****************************************************************************/ -static int PE_readHeader( - FILE *f, - long startOffset, - FILE_HDR *filehdr, - OPTIONAL_HDR *opthdr) -{ - EXE_HDR exehdr; - ulong offset,signature; - - /* Read the EXE header and check for valid header signature */ - result = PE_invalidDLLImage; - fseek(f, startOffset, SEEK_SET); - if (fread(&exehdr, 1, sizeof(exehdr), f) != sizeof(exehdr)) - return false; - if (exehdr.signature != 0x5A4D) - return false; - - /* Now seek to the start of the PE header defined at offset 0x3C - * in the MS-DOS EXE header, and read the signature and check it. - */ - fseek(f, startOffset+0x3C, SEEK_SET); - if (fread(&offset, 1, sizeof(offset), f) != sizeof(offset)) - return false; - fseek(f, startOffset+offset, SEEK_SET); - if (fread(&signature, 1, sizeof(signature), f) != sizeof(signature)) - return false; - if (signature != 0x00004550) - return false; - - /* Now read the PE file header and check that it is correct */ - if (fread(filehdr, 1, sizeof(*filehdr), f) != sizeof(*filehdr)) - return false; - if (filehdr->Machine != IMAGE_FILE_MACHINE_I386) - return false; - if (!(filehdr->Characteristics & IMAGE_FILE_32BIT_MACHINE)) - return false; - if (!(filehdr->Characteristics & IMAGE_FILE_DLL)) - return false; - if (fread(opthdr, 1, sizeof(*opthdr), f) != sizeof(*opthdr)) - return false; - if (opthdr->Magic != 0x10B) - return false; - - /* Success, so return true! */ - return true; -} - -/**************************************************************************** -PARAMETERS: -f - Handle to open file to read driver from -startOffset - Offset to the start of the driver within the file - -RETURNS: -Size of the DLL file on disk, or -1 on error - -REMARKS: -This function scans the headers for a Portable Binary DLL to determine the -length of the DLL file on disk. -{secret} -****************************************************************************/ -ulong PEAPI PE_getFileSize( - FILE *f, - ulong startOffset) -{ - FILE_HDR filehdr; - OPTIONAL_HDR opthdr; - SECTION_HDR secthdr; - ulong size; - int i; - - /* Read the PE file headers from disk */ - if (!PE_readHeader(f,startOffset,&filehdr,&opthdr)) - return 0xFFFFFFFF; - - /* Scan all the section headers summing up the total size */ - size = opthdr.SizeOfHeaders; - for (i = 0; i < filehdr.NumberOfSections; i++) { - if (fread(§hdr, 1, sizeof(secthdr), f) != sizeof(secthdr)) - return 0xFFFFFFFF; - size += secthdr.SizeOfRawData; - } - return size; -} - -/**************************************************************************** -DESCRIPTION: -Loads a Portable Binary DLL into memory from an open file - -HEADER: -peloader.h - -PARAMETERS: -f - Handle to open file to read driver from -startOffset - Offset to the start of the driver within the file -size - Place to store the size of the driver loaded -shared - True to load module into shared memory - -RETURNS: -Handle to loaded PE DLL, or NULL on failure. - -REMARKS: -This function loads a Portable Binary DLL library from disk, relocates -the code and returns a handle to the loaded library. This function is the -same as the regular PE_loadLibrary except that it take a handle to an -open file and an offset within that file for the DLL to load. - -SEE ALSO: -PE_loadLibrary, PE_getProcAddress, PE_freeLibrary -****************************************************************************/ -PE_MODULE * PEAPI PE_loadLibraryExt( - FILE *f, - ulong startOffset, - ulong *size, - ibool shared) -{ - FILE_HDR filehdr; - OPTIONAL_HDR opthdr; - SECTION_HDR secthdr; - ulong offset,pageOffset; - ulong text_off,text_addr,text_size; - ulong data_off,data_addr,data_size,data_end; - ulong export_off,export_addr,export_size,export_end; - ulong reloc_off,reloc_size; - ulong image_size; - int i,delta,numFixups; - ushort relocType,*fixup; - PE_MODULE *hMod = NULL; - void *reloc = NULL; - BASE_RELOCATION *baseReloc; - InitLibC_t InitLibC; - - /* Read the PE file headers from disk */ - if (!PE_readHeader(f,startOffset,&filehdr,&opthdr)) - return NULL; - - /* Scan all the section headers and find the necessary sections */ - text_off = data_off = reloc_off = export_off = 0; - text_addr = text_size = 0; - data_addr = data_size = data_end = 0; - export_addr = export_size = export_end = 0; - reloc_size = 0; - for (i = 0; i < filehdr.NumberOfSections; i++) { - if (fread(§hdr, 1, sizeof(secthdr), f) != sizeof(secthdr)) - goto Error; - if (strcmp(secthdr.Name, ".edata") == 0 || strcmp(secthdr.Name, ".rdata") == 0) { - /* Exports section */ - export_off = secthdr.PointerToRawData; - export_addr = secthdr.VirtualAddress; - export_size = secthdr.SizeOfRawData; - export_end = export_addr + export_size; - } - else if (strcmp(secthdr.Name, ".idata") == 0) { - /* Imports section, ignore */ - } - else if (strcmp(secthdr.Name, ".reloc") == 0) { - /* Relocations section */ - reloc_off = secthdr.PointerToRawData; - reloc_size = secthdr.SizeOfRawData; - } - else if (!text_off && secthdr.Characteristics & IMAGE_SCN_CNT_CODE) { - /* Code section */ - text_off = secthdr.PointerToRawData; - text_addr = secthdr.VirtualAddress; - text_size = secthdr.SizeOfRawData; - } - else if (!data_off && secthdr.Characteristics & IMAGE_SCN_CNT_INITIALIZED_DATA) { - /* Data section */ - data_off = secthdr.PointerToRawData; - data_addr = secthdr.VirtualAddress; - data_size = secthdr.SizeOfRawData; - data_end = data_addr + data_size; - } - } - - /* Check to make sure that we have all the sections we need */ - if (!text_off || !data_off || !export_off || !reloc_off) { - result = PE_invalidDLLImage; - goto Error; - } - - /* Find the size of the image to load allocate memory for it */ - image_size = MAX(export_end,data_end) - text_addr; - *size = sizeof(PE_MODULE) + image_size + 4096; - if (shared) - hMod = PM_mallocShared(*size); - else - hMod = PM_malloc(*size); - reloc = PM_malloc(reloc_size); - if (!hMod || !reloc) { - result = PE_outOfMemory; - goto Error; - } - - hMod->text = (uchar*)ROUND_4K((ulong)hMod + sizeof(PE_MODULE)); - hMod->data = (uchar*)((ulong)hMod->text + (data_addr - text_addr)); - hMod->export = (uchar*)((ulong)hMod->text + (export_addr - text_addr)); - hMod->textBase = text_addr; - hMod->dataBase = data_addr; - hMod->exportBase = export_addr; - hMod->exportDir = opthdr.DataDirectory[0].RelVirtualAddress - export_addr; - hMod->shared = shared; - - /* Now read the section images from disk */ - result = PE_invalidDLLImage; - fseek(f, startOffset+text_off, SEEK_SET); - if (fread(hMod->text, 1, text_size, f) != text_size) - goto Error; - fseek(f, startOffset+data_off, SEEK_SET); - if (fread(hMod->data, 1, data_size, f) != data_size) - goto Error; - fseek(f, startOffset+export_off, SEEK_SET); - if (fread(hMod->export, 1, export_size, f) != export_size) - goto Error; - fseek(f, startOffset+reloc_off, SEEK_SET); - if (fread(reloc, 1, reloc_size, f) != reloc_size) - goto Error; - - /* Now perform relocations on all sections in the image */ - delta = (ulong)hMod->text - opthdr.ImageBase - text_addr; - baseReloc = (BASE_RELOCATION*)reloc; - for (;;) { - /* Check for termination condition */ - if (!baseReloc->PageRVA || !baseReloc->BlockSize) - break; - - /* Do fixups */ - pageOffset = baseReloc->PageRVA - hMod->textBase; - numFixups = (baseReloc->BlockSize - sizeof(BASE_RELOCATION)) / sizeof(ushort); - fixup = (ushort*)(baseReloc + 1); - for (i = 0; i < numFixups; i++) { - relocType = *fixup >> 12; - if (relocType) { - offset = pageOffset + (*fixup & 0x0FFF); - *(ulong*)(hMod->text + offset) += delta; - } - fixup++; - } - - /* Move to next relocation block */ - baseReloc = (BASE_RELOCATION*)((ulong)baseReloc + baseReloc->BlockSize); - } - - /* Initialise the C runtime library for the loaded DLL */ - result = PE_unableToInitLibC; - if ((InitLibC = (InitLibC_t)PE_getProcAddress(hMod,"_InitLibC")) == NULL) - goto Error; - if (!InitLibC(&___imports,PM_getOSType())) - goto Error; - - /* Clean up, close the file and return the loaded module handle */ - PM_free(reloc); - result = PE_ok; - return hMod; - -Error: - if (shared) - PM_freeShared(hMod); - else - PM_free(hMod); - PM_free(reloc); - return NULL; -} - -/**************************************************************************** -DESCRIPTION: -Loads a Portable Binary DLL into memory - -HEADER: -peloader.h - -PARAMETERS: -szDLLName - Name of the PE DLL library to load -shared - True to load module into shared memory - -RETURNS: -Handle to loaded PE DLL, or NULL on failure. - -REMARKS: -This function loads a Portable Binary DLL library from disk, relocates -the code and returns a handle to the loaded library. This function -will only work on DLL's that do not have any imports, since we don't -resolve import dependencies in this function. - -SEE ALSO: -PE_getProcAddress, PE_freeLibrary -****************************************************************************/ -PE_MODULE * PEAPI PE_loadLibrary( - const char *szDLLName, - ibool shared) -{ - PE_MODULE *hMod; - -#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) - if (!shared) { - PM_MODULE hInst; - InitLibC_t InitLibC; - - /* For Win32 if are building checked libraries for debugging, we use - * the real Win32 DLL functions so that we can debug the resulting DLL - * files with the Win32 debuggers. Note that we can't do this if - * we need to load the files into a shared memory context. - */ - if ((hInst = PM_loadLibrary(szDLLName)) == NULL) { - result = PE_fileNotFound; - return NULL; - } - - /* Initialise the C runtime library for the loaded DLL */ - result = PE_unableToInitLibC; - if ((InitLibC = (void*)PM_getProcAddress(hInst,"_InitLibC")) == NULL) - return NULL; - if (!InitLibC(&___imports,PM_getOSType())) - return NULL; - - /* Allocate the PE_MODULE structure */ - if ((hMod = PM_malloc(sizeof(*hMod))) == NULL) - return NULL; - hMod->text = (void*)hInst; - hMod->shared = -1; - - /* DLL loaded successfully so return module handle */ - result = PE_ok; - return hMod; - } - else -#endif - { - FILE *f; - ulong size; - - /* Attempt to open the file on disk */ - if (shared < 0) - shared = 0; - if ((f = fopen(szDLLName,"rb")) == NULL) { - result = PE_fileNotFound; - return NULL; - } - hMod = PE_loadLibraryExt(f,0,&size,shared); - fclose(f); - return hMod; - } -} - -/**************************************************************************** -DESCRIPTION: -Loads a Portable Binary DLL into memory - -HEADER: -peloader.h - -PARAMETERS: -szDLLName - Name of the PE DLL library to load -shared - True to load module into shared memory - -RETURNS: -Handle to loaded PE DLL, or NULL on failure. - -REMARKS: -This function is the same as the regular PE_loadLibrary function, except -that it looks for the drivers in the MGL_ROOT/drivers directory or a -/drivers directory relative to the current directory. - -SEE ALSO: -PE_loadLibraryMGL, PE_getProcAddress, PE_freeLibrary -****************************************************************************/ -PE_MODULE * PEAPI PE_loadLibraryMGL( - const char *szDLLName, - ibool shared) -{ -#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) - PE_MODULE *hMod; -#endif - char path[256] = ""; - - /* We look in the 'drivers' directory, optionally under the MGL_ROOT - * environment variable directory. - */ -#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) - if (getenv("MGL_ROOT")) { - strcpy(path,getenv("MGL_ROOT")); - PM_backslash(path); - } - strcat(path,"drivers"); - PM_backslash(path); - strcat(path,szDLLName); - if ((hMod = PE_loadLibrary(path,shared)) != NULL) - return hMod; -#endif - strcpy(path,"drivers"); - PM_backslash(path); - strcat(path,szDLLName); - return PE_loadLibrary(path,shared); -} - -/**************************************************************************** -DESCRIPTION: -Gets a function address from a Portable Binary DLL - -HEADER: -peloader.h - -PARAMETERS: -hModule - Handle to a loaded PE DLL library -szProcName - Name of the function to get the address of - -RETURNS: -Pointer to the function, or NULL on failure. - -REMARKS: -This function searches for the named, exported function in a loaded PE -DLL library, and returns the address of the function. If the function is -not found in the library, this function return NULL. - -SEE ALSO: -PE_loadLibrary, PE_freeLibrary -****************************************************************************/ -void * PEAPI PE_getProcAddress( - PE_MODULE *hModule, - const char *szProcName) -{ -#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) - if (hModule->shared == -1) - return (void*)PM_getProcAddress(hModule->text,szProcName); - else -#endif - { - uint i; - EXPORT_DIRECTORY *exports; - ulong funcOffset; - ulong *AddressTable; - ulong *NameTable; - ushort *OrdinalTable; - char *name; - - /* Find the address of the export tables from the export section */ - if (!hModule) - return NULL; - exports = (EXPORT_DIRECTORY*)(hModule->export + hModule->exportDir); - AddressTable = (ulong*)(hModule->export + exports->AddressTableRVA - hModule->exportBase); - NameTable = (ulong*)(hModule->export + exports->NameTableRVA - hModule->exportBase); - OrdinalTable = (ushort*)(hModule->export + exports->OrdinalTableRVA - hModule->exportBase); - - /* Search the export name table to find the function name */ - for (i = 0; i < exports->NumberOfNamePointers; i++) { - name = (char*)(hModule->export + NameTable[i] - hModule->exportBase); - if (strcmp(name,szProcName) == 0) - break; - } - if (i == exports->NumberOfNamePointers) - return NULL; - funcOffset = AddressTable[OrdinalTable[i]]; - if (!funcOffset) - return NULL; - return (void*)(hModule->text + funcOffset - hModule->textBase); - } -} - -/**************************************************************************** -DESCRIPTION: -Frees a loaded Portable Binary DLL - -HEADER: -peloader.h - -PARAMETERS: -hModule - Handle to a loaded PE DLL library to free - -REMARKS: -This function frees a loaded PE DLL library from memory. - -SEE ALSO: -PE_getProcAddress, PE_loadLibrary -****************************************************************************/ -void PEAPI PE_freeLibrary( - PE_MODULE *hModule) -{ - TerminateLibC_t TerminateLibC; - -#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) - if (hModule->shared == -1) { - /* Run the C runtime library exit code on module unload */ - if ((TerminateLibC = (TerminateLibC_t)PM_getProcAddress(hModule->text,"_TerminateLibC")) != NULL) - TerminateLibC(); - PM_freeLibrary(hModule->text); - PM_free(hModule); - } - else -#endif - { - if (hModule) { - /* Run the C runtime library exit code on module unload */ - if ((TerminateLibC = (TerminateLibC_t)PE_getProcAddress(hModule,"_TerminateLibC")) != NULL) - TerminateLibC(); - if (hModule->shared) - PM_freeShared(hModule); - else - PM_free(hModule); - } - } -} - -/**************************************************************************** -DESCRIPTION: -Returns the error code for the last operation - -HEADER: -peloader.h - -RETURNS: -Error code for the last operation. - -SEE ALSO: -PE_getProcAddress, PE_loadLibrary -****************************************************************************/ -int PEAPI PE_getError(void) -{ - return result; -} diff --git a/board/MAI/bios_emulator/scitech/src/common/vesavbe.c b/board/MAI/bios_emulator/scitech/src/common/vesavbe.c deleted file mode 100644 index a669e5c..0000000 --- a/board/MAI/bios_emulator/scitech/src/common/vesavbe.c +++ /dev/null @@ -1,1214 +0,0 @@ -/**************************************************************************** -* -* The SuperVGA Kit - UniVBE Software Development Kit -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: IBM PC Real Mode and 16/32 bit Protected Mode. -* -* Description: Module to implement a C callable interface to the standard -* VESA VBE routines. You should rip out this module and use it -* directly in your own applications, or you can use the -* high level SDK functions. -* -* MUST be compiled in the LARGE or FLAT models. -* -****************************************************************************/ - -#include -#include -#include -#include "vesavbe.h" -#include "pmapi.h" -#include "drvlib/os/os.h" - -/*---------------------------- Global Variables ---------------------------*/ - -#define VBE_SUCCESS 0x004F -#define MAX_LIN_PTRS 10 - -static uint VESABuf_len = 1024;/* Length of the VESABuf buffer */ -static ibool haveRiva128; /* True if we have a Riva128 */ -static VBE_state defState = {0}; /* Default state buffer */ -static VBE_state *state = &defState; /* Pointer to current buffer */ -static int VBE_shared = 0; -#ifndef REALMODE -static char localBuf[512]; /* Global PM string translate buf */ -#define MAX_LOCAL_BUF &localBuf[511] -#endif - -/*----------------------------- Implementation ----------------------------*/ - -/* static function in WinDirect for passing 32-bit registers to BIOS */ -int PMAPI WD_int386(int intno, RMREGS *in, RMREGS *out); - -void VBEAPI VBE_init(void) -/**************************************************************************** -* -* Function: VBE_init -* -* Description: Initialises the VBE transfer buffer in real mode DC.memory. -* This routine is called by the VESAVBE module every time -* it needs to use the transfer buffer, so we simply allocate -* it once and then return. -* -****************************************************************************/ -{ - if (!state->VESABuf_ptr) { - /* Allocate a global buffer for communicating with the VESA VBE */ - if ((state->VESABuf_ptr = PM_getVESABuf(&VESABuf_len, &state->VESABuf_rseg, &state->VESABuf_roff)) == NULL) - PM_fatalError("VESAVBE.C: Real mode memory allocation failed!"); - } -} - -void * VBEAPI VBE_getRMBuf(uint *len,uint *rseg,uint *roff) -/**************************************************************************** -* -* Function: VBE_getRMBuf -* -* Description: This function returns the location and length of the real -* mode memory buffer for calling real mode functions. -* -****************************************************************************/ -{ - *len = VESABuf_len; - *rseg = state->VESABuf_rseg; - *roff = state->VESABuf_roff; - return state->VESABuf_ptr; -} - -void VBEAPI VBE_setStateBuffer(VBE_state *s) -/**************************************************************************** -* -* Function: VBE_setStateBuffer -* -* Description: This functions sets the internal state buffer for the -* VBE module to the passed in buffer. By default the internal -* global buffer is used, but you must use separate buffers -* for each device in a multi-controller environment. -* -****************************************************************************/ -{ - state = s; -} - -void VBEAPI VBE_callESDI(RMREGS *regs, void *buffer, int size) -/**************************************************************************** -* -* Function: VBE_callESDI -* Parameters: regs - Registers to load when calling VBE -* buffer - Buffer to copy VBE info block to -* size - Size of buffer to fill -* -* Description: Calls the VESA VBE and passes in a buffer for the VBE to -* store information in, which is then copied into the users -* buffer space. This works in protected mode as the buffer -* passed to the VESA VBE is allocated in conventional -* memory, and is then copied into the users memory block. -* -****************************************************************************/ -{ - RMSREGS sregs; - - if (!state->VESABuf_ptr) - PM_fatalError("You *MUST* call VBE_init() before you can call the VESAVBE.C module!"); - sregs.es = (ushort)state->VESABuf_rseg; - regs->x.di = (ushort)state->VESABuf_roff; - memcpy(state->VESABuf_ptr, buffer, size); - PM_int86x(0x10, regs, regs, &sregs); - memcpy(buffer, state->VESABuf_ptr, size); -} - -#ifndef REALMODE -static char *VBE_copyStrToLocal(char *p,char *realPtr,char *max) -/**************************************************************************** -* -* Function: VBE_copyStrToLocal -* Parameters: p - Flat model buffer to copy to -* realPtr - Real mode pointer to copy -* Returns: Pointer to the next byte after string -* -* Description: Copies the string from the real mode location pointed to -* by 'realPtr' into the flat model buffer pointed to by -* 'p'. We return a pointer to the next byte past the copied -* string. -* -****************************************************************************/ -{ - uchar *v; - - v = PM_mapRealPointer((uint)((ulong)realPtr >> 16), (uint)((ulong)realPtr & 0xFFFF)); - while (*v != 0 && p < max) - *p++ = *v++; - *p++ = 0; - return p; -} - -static void VBE_copyShortToLocal(ushort *p,ushort *realPtr) -/**************************************************************************** -* -* Function: VBE_copyShortToLocal -* Parameters: p - Flat model buffer to copy to -* realPtr - Real mode pointer to copy -* -* Description: Copies the mode table from real mode memory to the flat -* model buffer. -* -****************************************************************************/ -{ - ushort *v; - - v = PM_mapRealPointer((uint)((ulong)realPtr >> 16),(uint)((ulong)realPtr & 0xFFFF)); - while (*v != 0xFFFF) - *p++ = *v++; - *p = 0xFFFF; -} -#endif - -int VBEAPI VBE_detectEXT(VBE_vgaInfo *vgaInfo,ibool forceUniVBE) -/**************************************************************************** -* -* Function: VBE_detect -* Parameters: vgaInfo - Place to store the VGA information block -* Returns: VBE version number, or 0 if not detected. -* -* Description: Detects if a VESA VBE is out there and functioning -* correctly. If we detect a VBE interface we return the -* VGAInfoBlock returned by the VBE and the VBE version number. -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F00; /* Get SuperVGA information */ - if (forceUniVBE) { - regs.x.bx = 0x1234; - regs.x.cx = 0x4321; - } - else { - regs.x.bx = 0; - regs.x.cx = 0; - } - strncpy(vgaInfo->VESASignature,"VBE2",4); - VBE_callESDI(®s, vgaInfo, sizeof(*vgaInfo)); - if (regs.x.ax != VBE_SUCCESS) - return 0; - if (strncmp(vgaInfo->VESASignature,"VESA",4) != 0) - return 0; - - /* Check for bogus BIOSes that return a VBE version number that is - * not correct, and fix it up. We also check the OemVendorNamePtr for a - * valid value, and if it is invalid then we also reset to VBE 1.2. - */ - if (vgaInfo->VESAVersion >= 0x200 && vgaInfo->OemVendorNamePtr == 0) - vgaInfo->VESAVersion = 0x102; -#ifndef REALMODE - /* Relocate all the indirect information (mode tables, OEM strings - * etc) from the low 1Mb memory region into a static buffer in - * our default data segment. We do this to insulate the application - * from mapping the strings from real mode to protected mode. - */ - { - char *p,*p2; - p2 = VBE_copyStrToLocal(localBuf,vgaInfo->OemStringPtr,MAX_LOCAL_BUF); - vgaInfo->OemStringPtr = localBuf; - if (vgaInfo->VESAVersion >= 0x200) { - p = VBE_copyStrToLocal(p2,vgaInfo->OemVendorNamePtr,MAX_LOCAL_BUF); - vgaInfo->OemVendorNamePtr = p2; - p2 = VBE_copyStrToLocal(p,vgaInfo->OemProductNamePtr,MAX_LOCAL_BUF); - vgaInfo->OemProductNamePtr = p; - p = VBE_copyStrToLocal(p2,vgaInfo->OemProductRevPtr,MAX_LOCAL_BUF); - vgaInfo->OemProductRevPtr = p2; - VBE_copyShortToLocal((ushort*)p,vgaInfo->VideoModePtr); - vgaInfo->VideoModePtr = (ushort*)p; - } - else { - VBE_copyShortToLocal((ushort*)p2,vgaInfo->VideoModePtr); - vgaInfo->VideoModePtr = (ushort*)p2; - } - } -#endif - state->VBEMemory = vgaInfo->TotalMemory * 64; - - /* Check for Riva128 based cards since they have broken triple buffering - * and stereo support. - */ - haveRiva128 = false; - if (vgaInfo->VESAVersion >= 0x300 && - (strstr(vgaInfo->OemStringPtr,"NVidia") != NULL || - strstr(vgaInfo->OemStringPtr,"Riva") != NULL)) { - haveRiva128 = true; - } - - /* Check for Matrox G400 cards which claim to be VBE 3.0 - * compliant yet they don't implement the refresh rate control - * functions. - */ - if (vgaInfo->VESAVersion >= 0x300 && (strcmp(vgaInfo->OemProductNamePtr,"Matrox G400") == 0)) - vgaInfo->VESAVersion = 0x200; - return (state->VBEVersion = vgaInfo->VESAVersion); -} - -int VBEAPI VBE_detect(VBE_vgaInfo *vgaInfo) -/**************************************************************************** -* -* Function: VBE_detect -* Parameters: vgaInfo - Place to store the VGA information block -* Returns: VBE version number, or 0 if not detected. -* -* Description: Detects if a VESA VBE is out there and functioning -* correctly. If we detect a VBE interface we return the -* VGAInfoBlock returned by the VBE and the VBE version number. -* -****************************************************************************/ -{ - return VBE_detectEXT(vgaInfo,false); -} - -ibool VBEAPI VBE_getModeInfo(int mode,VBE_modeInfo *modeInfo) -/**************************************************************************** -* -* Function: VBE_getModeInfo -* Parameters: mode - VBE mode to get information for -* modeInfo - Place to store VBE mode information -* Returns: True on success, false if function failed. -* -* Description: Obtains information about a specific video mode from the -* VBE. You should use this function to find the video mode -* you wish to set, as the new VBE 2.0 mode numbers may be -* completely arbitrary. -* -****************************************************************************/ -{ - RMREGS regs; - int bits; - - regs.x.ax = 0x4F01; /* Get mode information */ - regs.x.cx = (ushort)mode; - VBE_callESDI(®s, modeInfo, sizeof(*modeInfo)); - if (regs.x.ax != VBE_SUCCESS) - return false; - if ((modeInfo->ModeAttributes & vbeMdAvailable) == 0) - return false; - - /* Map out triple buffer and stereo flags for NVidia Riva128 - * chips. - */ - if (haveRiva128) { - modeInfo->ModeAttributes &= ~vbeMdTripleBuf; - modeInfo->ModeAttributes &= ~vbeMdStereo; - } - - /* Support old style RGB definitions for VBE 1.1 BIOSes */ - bits = modeInfo->BitsPerPixel; - if (modeInfo->MemoryModel == vbeMemPK && bits > 8) { - modeInfo->MemoryModel = vbeMemRGB; - switch (bits) { - case 15: - modeInfo->RedMaskSize = 5; - modeInfo->RedFieldPosition = 10; - modeInfo->GreenMaskSize = 5; - modeInfo->GreenFieldPosition = 5; - modeInfo->BlueMaskSize = 5; - modeInfo->BlueFieldPosition = 0; - modeInfo->RsvdMaskSize = 1; - modeInfo->RsvdFieldPosition = 15; - break; - case 16: - modeInfo->RedMaskSize = 5; - modeInfo->RedFieldPosition = 11; - modeInfo->GreenMaskSize = 5; - modeInfo->GreenFieldPosition = 5; - modeInfo->BlueMaskSize = 5; - modeInfo->BlueFieldPosition = 0; - modeInfo->RsvdMaskSize = 0; - modeInfo->RsvdFieldPosition = 0; - break; - case 24: - modeInfo->RedMaskSize = 8; - modeInfo->RedFieldPosition = 16; - modeInfo->GreenMaskSize = 8; - modeInfo->GreenFieldPosition = 8; - modeInfo->BlueMaskSize = 8; - modeInfo->BlueFieldPosition = 0; - modeInfo->RsvdMaskSize = 0; - modeInfo->RsvdFieldPosition = 0; - break; - } - } - - /* Convert the 32k direct color modes of VBE 1.2+ BIOSes to - * be recognised as 15 bits per pixel modes. - */ - if (bits == 16 && modeInfo->RsvdMaskSize == 1) - modeInfo->BitsPerPixel = 15; - - /* Fix up bogus BIOS'es that report incorrect reserved pixel masks - * for 32K color modes. Quite a number of BIOS'es have this problem, - * and this affects our OS/2 drivers in VBE fallback mode. - */ - if (bits == 15 && (modeInfo->RsvdMaskSize != 1 || modeInfo->RsvdFieldPosition != 15)) { - modeInfo->RsvdMaskSize = 1; - modeInfo->RsvdFieldPosition = 15; - } - return true; -} - -long VBEAPI VBE_getPageSize(VBE_modeInfo *mi) -/**************************************************************************** -* -* Function: VBE_getPageSize -* Parameters: mi - Pointer to mode information block -* Returns: Caculated page size in bytes rounded to correct boundary -* -* Description: Computes the page size in bytes for the specified mode -* information block, rounded up to the appropriate boundary -* (8k, 16k, 32k or 64k). Pages >= 64k in size are always -* rounded to the nearest 64k boundary (so the start of a -* page is always bank aligned). -* -****************************************************************************/ -{ - long size; - - size = (long)mi->BytesPerScanLine * (long)mi->YResolution; - if (mi->BitsPerPixel == 4) { - /* We have a 16 color video mode, so round up the page size to - * 8k, 16k, 32k or 64k boundaries depending on how large it is. - */ - - size = (size + 0x1FFFL) & 0xFFFFE000L; - if (size != 0x2000) { - size = (size + 0x3FFFL) & 0xFFFFC000L; - if (size != 0x4000) { - size = (size + 0x7FFFL) & 0xFFFF8000L; - if (size != 0x8000) - size = (size + 0xFFFFL) & 0xFFFF0000L; - } - } - } - else size = (size + 0xFFFFL) & 0xFFFF0000L; - return size; -} - -ibool VBEAPI VBE_setVideoModeExt(int mode,VBE_CRTCInfo *crtc) -/**************************************************************************** -* -* Function: VBE_setVideoModeExt -* Parameters: mode - SuperVGA video mode to set. -* Returns: True if the mode was set, false if not. -* -* Description: Attempts to set the specified video mode. This version -* includes support for the VBE/Core 3.0 refresh rate control -* mechanism. -* -****************************************************************************/ -{ - RMREGS regs; - - if (state->VBEVersion < 0x200 && mode < 0x100) { - /* Some VBE implementations barf terribly if you try to set non-VBE - * video modes with the VBE set mode call. VBE 2.0 implementations - * must be able to handle this. - */ - regs.h.al = (ushort)mode; - regs.h.ah = 0; - PM_int86(0x10,®s,®s); - } - else { - if (state->VBEVersion < 0x300 && (mode & vbeRefreshCtrl)) - return false; - regs.x.ax = 0x4F02; - regs.x.bx = (ushort)mode; - if ((mode & vbeRefreshCtrl) && crtc) - VBE_callESDI(®s, crtc, sizeof(*crtc)); - else - PM_int86(0x10,®s,®s); - if (regs.x.ax != VBE_SUCCESS) - return false; - } - return true; -} - -ibool VBEAPI VBE_setVideoMode(int mode) -/**************************************************************************** -* -* Function: VBE_setVideoMode -* Parameters: mode - SuperVGA video mode to set. -* Returns: True if the mode was set, false if not. -* -* Description: Attempts to set the specified video mode. -* -****************************************************************************/ -{ - return VBE_setVideoModeExt(mode,NULL); -} - -int VBEAPI VBE_getVideoMode(void) -/**************************************************************************** -* -* Function: VBE_getVideoMode -* Returns: Current video mode -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F03; - PM_int86(0x10,®s,®s); - if (regs.x.ax != VBE_SUCCESS) - return -1; - return regs.x.bx; -} - -ibool VBEAPI VBE_setBank(int window,int bank) -/**************************************************************************** -* -* Function: VBE_setBank -* Parameters: window - Window to set -* bank - Bank number to set window to -* Returns: True on success, false on failure. -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F05; - regs.h.bh = 0; - regs.h.bl = window; - regs.x.dx = bank; - PM_int86(0x10,®s,®s); - return regs.x.ax == VBE_SUCCESS; -} - -int VBEAPI VBE_getBank(int window) -/**************************************************************************** -* -* Function: VBE_setBank -* Parameters: window - Window to read -* Returns: Bank number for the window (-1 on failure) -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F05; - regs.h.bh = 1; - regs.h.bl = window; - PM_int86(0x10,®s,®s); - if (regs.x.ax != VBE_SUCCESS) - return -1; - return regs.x.dx; -} - -ibool VBEAPI VBE_setPixelsPerLine(int pixelsPerLine,int *newBytes, - int *newPixels,int *maxScanlines) -/**************************************************************************** -* -* Function: VBE_setPixelsPerLine -* Parameters: pixelsPerLine - Pixels per scanline -* newBytes - Storage for bytes per line value set -* newPixels - Storage for pixels per line value set -* maxScanLines - Storage for maximum number of scanlines -* Returns: True on success, false on failure -* -* Description: Sets the scanline length for the video mode to the specified -* number of pixels per scanline. If you need more granularity -* in TrueColor modes, use the VBE_setBytesPerLine routine -* (only valid for VBE 2.0). -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F06; - regs.h.bl = 0; - regs.x.cx = pixelsPerLine; - PM_int86(0x10,®s,®s); - *newBytes = regs.x.bx; - *newPixels = regs.x.cx; - *maxScanlines = regs.x.dx; - return regs.x.ax == VBE_SUCCESS; -} - -ibool VBEAPI VBE_setBytesPerLine(int bytesPerLine,int *newBytes, - int *newPixels,int *maxScanlines) -/**************************************************************************** -* -* Function: VBE_setBytesPerLine -* Parameters: pixelsPerLine - Pixels per scanline -* newBytes - Storage for bytes per line value set -* newPixels - Storage for pixels per line value set -* maxScanLines - Storage for maximum number of scanlines -* Returns: True on success, false on failure -* -* Description: Sets the scanline length for the video mode to the specified -* number of bytes per scanline (valid for VBE 2.0 only). -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F06; - regs.h.bl = 2; - regs.x.cx = bytesPerLine; - PM_int86(0x10,®s,®s); - *newBytes = regs.x.bx; - *newPixels = regs.x.cx; - *maxScanlines = regs.x.dx; - return regs.x.ax == VBE_SUCCESS; -} - -ibool VBEAPI VBE_getScanlineLength(int *bytesPerLine,int *pixelsPerLine, - int *maxScanlines) -/**************************************************************************** -* -* Function: VBE_getScanlineLength -* Parameters: bytesPerLine - Storage for bytes per scanline -* pixelsPerLine - Storage for pixels per scanline -* maxScanLines - Storage for maximum number of scanlines -* Returns: True on success, false on failure -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F06; - regs.h.bl = 1; - PM_int86(0x10,®s,®s); - *bytesPerLine = regs.x.bx; - *pixelsPerLine = regs.x.cx; - *maxScanlines = regs.x.dx; - return regs.x.ax == VBE_SUCCESS; -} - -ibool VBEAPI VBE_getMaxScanlineLength(int *maxBytes,int *maxPixels) -/**************************************************************************** -* -* Function: VBE_getMaxScanlineLength -* Parameters: maxBytes - Maximum scanline width in bytes -* maxPixels - Maximum scanline width in pixels -* Returns: True if successful, false if function failed -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F06; - regs.h.bl = 3; - PM_int86(0x10,®s,®s); - *maxBytes = regs.x.bx; - *maxPixels = regs.x.cx; - return regs.x.ax == VBE_SUCCESS; -} - -ibool VBEAPI VBE_setDisplayStart(int x,int y,ibool waitVRT) -/**************************************************************************** -* -* Function: VBE_setDisplayStart -* Parameters: x,y - Position of the first pixel to display -* waitVRT - True to wait for retrace, false if not -* Returns: True if function was successful. -* -* Description: Sets the new starting display position to implement -* hardware scrolling. -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F07; - if (waitVRT) - regs.x.bx = 0x80; - else regs.x.bx = 0x00; - regs.x.cx = x; - regs.x.dx = y; - PM_int86(0x10,®s,®s); - return regs.x.ax == VBE_SUCCESS; -} - -ibool VBEAPI VBE_getDisplayStart(int *x,int *y) -/**************************************************************************** -* -* Function: VBE_getDisplayStart -* Parameters: x,y - Place to store starting address value -* Returns: True if function was successful. -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F07; - regs.x.bx = 0x01; - PM_int86(0x10,®s,®s); - *x = regs.x.cx; - *y = regs.x.dx; - return regs.x.ax == VBE_SUCCESS; -} - -ibool VBEAPI VBE_setDisplayStartAlt(ulong startAddr,ibool waitVRT) -/**************************************************************************** -* -* Function: VBE_setDisplayStartAlt -* Parameters: startAddr - 32-bit starting address in display memory -* waitVRT - True to wait for vertical retrace, false if not -* Returns: True if function was successful, false if not supported. -* -* Description: Sets the new starting display position to the specified -* 32-bit display start address. Note that this function is -* different the the version above, since it takes a 32-bit -* byte offset in video memory as the starting address which -* gives the programmer maximum control over the stat address. -* -* NOTE: Requires VBE/Core 3.0 -* -****************************************************************************/ -{ - RMREGS regs; - - if (state->VBEVersion >= 0x300) { - regs.x.ax = 0x4F07; - regs.x.bx = waitVRT ? 0x82 : 0x02; - regs.e.ecx = startAddr; - PM_int86(0x10,®s,®s); - return regs.x.ax == VBE_SUCCESS; - } - return false; -} - -int VBEAPI VBE_getDisplayStartStatus(void) -/**************************************************************************** -* -* Function: VBE_getDisplayStartStatus -* Returns: 0 if last flip not occurred, 1 if already flipped -* -1 if not supported -* -* Description: Returns the status of the previous display start request. -* If this function is supported the programmer can implement -* hardware triple buffering using this function. -* -* NOTE: Requires VBE/Core 3.0 -* -****************************************************************************/ -{ - RMREGS regs; - - if (state->VBEVersion >= 0x300) { - regs.x.ax = 0x4F07; - regs.x.bx = 0x0004; - PM_int86(0x10,®s,®s); - if (regs.x.ax == VBE_SUCCESS) - return (regs.x.cx != 0); - } - return -1; -} - -ibool VBEAPI VBE_enableStereoMode(void) -/**************************************************************************** -* -* Function: VBE_enableStereoMode -* Returns: True if stereo mode enabled, false if not supported. -* -* Description: Puts the system into hardware stereo mode for LC shutter -* glasses, where the display swaps between two display start -* addresses every vertical retrace. -* -* NOTE: Requires VBE/Core 3.0 -* -****************************************************************************/ -{ - RMREGS regs; - - if (state->VBEVersion >= 0x300) { - regs.x.ax = 0x4F07; - regs.x.bx = 0x0005; - PM_int86(0x10,®s,®s); - return regs.x.ax == VBE_SUCCESS; - } - return false; -} - -ibool VBEAPI VBE_disableStereoMode(void) -/**************************************************************************** -* -* Function: VBE_disableStereoMode -* Returns: True if stereo mode disabled, false if not supported. -* -* Description: Puts the system back into normal, non-stereo display mode -* after having stereo mode enabled. -* -* NOTE: Requires VBE/Core 3.0 -* -****************************************************************************/ -{ - RMREGS regs; - - if (state->VBEVersion >= 0x300) { - regs.x.ax = 0x4F07; - regs.x.bx = 0x0006; - PM_int86(0x10,®s,®s); - return regs.x.ax == VBE_SUCCESS; - } - return false; -} - -ibool VBEAPI VBE_setStereoDisplayStart(ulong leftAddr,ulong rightAddr, - ibool waitVRT) -/**************************************************************************** -* -* Function: VBE_setStereoDisplayStart -* Parameters: leftAddr - 32-bit start address for left image -* rightAddr - 32-bit start address for right image -* waitVRT - True to wait for vertical retrace, false if not -* Returns: True if function was successful, false if not supported. -* -* Description: Sets the new starting display position to the specified -* 32-bit display start address. Note that this function is -* different the the version above, since it takes a 32-bit -* byte offset in video memory as the starting address which -* gives the programmer maximum control over the stat address. -* -* NOTE: Requires VBE/Core 3.0 -* -****************************************************************************/ -{ - RMREGS regs; - - if (state->VBEVersion >= 0x300) { - regs.x.ax = 0x4F07; - regs.x.bx = waitVRT ? 0x83 : 0x03; - regs.e.ecx = leftAddr; - regs.e.edx = rightAddr; - PM_int86(0x10,®s,®s); - return regs.x.ax == VBE_SUCCESS; - } - return false; -} - -ulong VBEAPI VBE_getClosestClock(ushort mode,ulong pixelClock) -/**************************************************************************** -* -* Function: VBE_getClosestClock -* Parameters: mode - VBE mode to be used (include vbeLinearBuffer) -* pixelClock - Desired pixel clock -* Returns: Closest pixel clock to desired clock (-1 if not supported) -* -* Description: Calls the VBE/Core 3.0 interface to determine the closest -* pixel clock to the requested value. The BIOS will always -* search for a pixel clock that is no more than 1% below the -* requested clock or somewhere higher than the clock. If the -* clock is higher note that it may well be many Mhz higher -* that requested and the application will have to check that -* the returned value is suitable for it's needs. This function -* returns the actual pixel clock that will be programmed by -* the hardware. -* -* Note that if the pixel clock will be used with a linear -* framebuffer mode, make sure you pass in the linear -* framebuffer flag to this function. -* -* NOTE: Requires VBE/Core 3.0 -* -****************************************************************************/ -{ - RMREGS regs; - - if (state->VBEVersion >= 0x300) { - regs.x.ax = 0x4F0B; - regs.h.bl = 0x00; - regs.e.ecx = pixelClock; - regs.x.dx = mode; - PM_int86(0x10,®s,®s); - if (regs.x.ax == VBE_SUCCESS) - return regs.e.ecx; - } - return -1; -} - -ibool VBEAPI VBE_setDACWidth(int width) -/**************************************************************************** -* -* Function: VBE_setDACWidth -* Parameters: width - Width to set the DAC to -* Returns: True on success, false on failure -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F08; - regs.h.bl = 0x00; - regs.h.bh = width; - PM_int86(0x10,®s,®s); - return regs.x.ax == VBE_SUCCESS; -} - -int VBEAPI VBE_getDACWidth(void) -/**************************************************************************** -* -* Function: VBE_getDACWidth -* Returns: Current width of the palette DAC -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F08; - regs.h.bl = 0x01; - PM_int86(0x10,®s,®s); - if (regs.x.ax != VBE_SUCCESS) - return -1; - return regs.h.bh; -} - -ibool VBEAPI VBE_setPalette(int start,int num,VBE_palette *pal,ibool waitVRT) -/**************************************************************************** -* -* Function: VBE_setPalette -* Parameters: start - Starting palette index to program -* num - Number of palette indexes to program -* pal - Palette buffer containing values -* waitVRT - Wait for vertical retrace flag -* Returns: True on success, false on failure -* -* Description: Sets a block of palette registers by calling the VBE 2.0 -* BIOS. This function will fail on VBE 1.2 implementations. -* -****************************************************************************/ -{ - RMREGS regs; - - regs.x.ax = 0x4F09; - regs.h.bl = waitVRT ? 0x80 : 0x00; - regs.x.cx = num; - regs.x.dx = start; - VBE_callESDI(®s, pal, sizeof(VBE_palette) * num); - return regs.x.ax == VBE_SUCCESS; -} - -void * VBEAPI VBE_getBankedPointer(VBE_modeInfo *modeInfo) -/**************************************************************************** -* -* Function: VBE_getBankedPointer -* Parameters: modeInfo - Mode info block for video mode -* Returns: Selector to the linear framebuffer (0 on failure) -* -* Description: Returns a near pointer to the VGA framebuffer area. -* -****************************************************************************/ -{ - /* We just map the pointer every time, since the pointer will always - * be in real mode memory, so we wont actually be mapping any real - * memory. - * - * NOTE: We cannot currently map a near pointer to the banked frame - * buffer for Watcom Win386, so we create a 16:16 far pointer to - * the video memory. All the assembler code will render to the - * video memory by loading the selector rather than using a - * near pointer. - */ - ulong seg = (ushort)modeInfo->WinASegment; - if (seg != 0) { - if (seg == 0xA000) - return (void*)PM_getA0000Pointer(); - else - return (void*)PM_mapPhysicalAddr(seg << 4,0xFFFF,true); - } - return NULL; -} - -#ifndef REALMODE - -void * VBEAPI VBE_getLinearPointer(VBE_modeInfo *modeInfo) -/**************************************************************************** -* -* Function: VBE_getLinearPointer -* Parameters: modeInfo - Mode info block for video mode -* Returns: Selector to the linear framebuffer (0 on failure) -* -* Description: Returns a near pointer to the linear framebuffer for the video -* mode. -* -****************************************************************************/ -{ - static ulong physPtr[MAX_LIN_PTRS] = {0}; - static void *linPtr[MAX_LIN_PTRS] = {0}; - static int numPtrs = 0; - int i; - - /* Search for an already mapped pointer */ - for (i = 0; i < numPtrs; i++) { - if (physPtr[i] == modeInfo->PhysBasePtr) - return linPtr[i]; - } - if (numPtrs < MAX_LIN_PTRS) { - physPtr[numPtrs] = modeInfo->PhysBasePtr; - linPtr[numPtrs] = PM_mapPhysicalAddr(modeInfo->PhysBasePtr,(state->VBEMemory * 1024L)-1,true); - return linPtr[numPtrs++]; - } - return NULL; -} - -static void InitPMCode(void) -/**************************************************************************** -* -* Function: InitPMCode - 32 bit protected mode version -* -* Description: Finds the address of and relocates the protected mode -* code block from the VBE 2.0 into a local memory block. The -* memory block is allocated with malloc() and must be freed -* with VBE_freePMCode() after graphics processing is complete. -* -* Note that this buffer _must_ be recopied after each mode set, -* as the routines will change depending on the underlying -* video mode. -* -****************************************************************************/ -{ - RMREGS regs; - RMSREGS sregs; - uchar *code; - int pmLen; - - if (!state->pmInfo && state->VBEVersion >= 0x200) { - regs.x.ax = 0x4F0A; - regs.x.bx = 0; - PM_int86x(0x10,®s,®s,&sregs); - if (regs.x.ax != VBE_SUCCESS) - return; - if (VBE_shared) - state->pmInfo = PM_mallocShared(regs.x.cx); - else - state->pmInfo = PM_malloc(regs.x.cx); - if (state->pmInfo == NULL) - return; - state->pmInfo32 = state->pmInfo; - pmLen = regs.x.cx; - - /* Relocate the block into our local data segment */ - code = PM_mapRealPointer(sregs.es,regs.x.di); - memcpy(state->pmInfo,code,pmLen); - - /* Now do a sanity check on the information we recieve to ensure - * that is is correct. Some BIOS return totally bogus information - * in here (Matrox is one)! Under DOS this works OK, but under OS/2 - * we are screwed. - */ - if (state->pmInfo->setWindow >= pmLen || - state->pmInfo->setDisplayStart >= pmLen || - state->pmInfo->setPalette >= pmLen || - state->pmInfo->IOPrivInfo >= pmLen) { - if (VBE_shared) - PM_freeShared(state->pmInfo); - else - PM_free(state->pmInfo); - state->pmInfo32 = state->pmInfo = NULL; - return; - } - - /* Read the IO priveledge info and determine if we need to - * pass a selector to MMIO registers to the bank switch code. - * Since we no longer support selector allocation, we no longer - * support this mechanism so we disable the protected mode - * interface in this case. - */ - if (state->pmInfo->IOPrivInfo && !state->MMIOSel) { - ushort *p = (ushort*)((uchar*)state->pmInfo + state->pmInfo->IOPrivInfo); - while (*p != 0xFFFF) - p++; - p++; - if (*p != 0xFFFF) - VBE_freePMCode(); - } - } -} - -void * VBEAPI VBE_getSetBank(void) -/**************************************************************************** -* -* Function: VBE_getSetBank -* Returns: Pointer to the 32 VBE 2.0 bit bank switching routine. -* -****************************************************************************/ -{ - if (state->VBEVersion >= 0x200) { - InitPMCode(); - if (state->pmInfo) - return (uchar*)state->pmInfo + state->pmInfo->setWindow; - } - return NULL; -} - -void * VBEAPI VBE_getSetDisplayStart(void) -/**************************************************************************** -* -* Function: VBE_getSetDisplayStart -* Returns: Pointer to the 32 VBE 2.0 bit CRT start address routine. -* -****************************************************************************/ -{ - if (state->VBEVersion >= 0x200) { - InitPMCode(); - if (state->pmInfo) - return (uchar*)state->pmInfo + state->pmInfo->setDisplayStart; - } - return NULL; -} - -void * VBEAPI VBE_getSetPalette(void) -/**************************************************************************** -* -* Function: VBE_getSetPalette -* Returns: Pointer to the 32 VBE 2.0 bit palette programming routine. -* -****************************************************************************/ -{ - if (state->VBEVersion >= 0x200) { - InitPMCode(); - if (state->pmInfo) - return (uchar*)state->pmInfo + state->pmInfo->setPalette; - } - return NULL; -} - -void VBEAPI VBE_freePMCode(void) -/**************************************************************************** -* -* Function: VBE_freePMCode -* -* Description: This routine frees the protected mode code blocks that -* we copied from the VBE 2.0 interface. This routine must -* be after you have finished graphics processing to free up -* the memory occupied by the routines. This is necessary -* because the PM info memory block must be re-copied after -* every video mode set from the VBE 2.0 implementation. -* -****************************************************************************/ -{ - if (state->pmInfo) { - if (VBE_shared) - PM_freeShared(state->pmInfo); - else - PM_free(state->pmInfo); - state->pmInfo = NULL; - state->pmInfo32 = NULL; - } -} - -void VBEAPI VBE_sharePMCode(void) -/**************************************************************************** -* -* Function: VBE_sharePMCode -* -* Description: Enables internal sharing of the PM code buffer for OS/2. -* -****************************************************************************/ -{ - VBE_shared = true; -} - -/* Set of code stubs used to build the final bank switch code */ - -#define VBE20_adjustOffset 7 - -static uchar VBE20A_bankFunc32_Start[] = { - 0x53,0x51, /* push ebx,ecx */ - 0x8B,0xD0, /* mov edx,eax */ - 0x33,0xDB, /* xor ebx,ebx */ - 0xB1,0x00, /* mov cl,0 */ - 0xD2,0xE2, /* shl dl,cl */ - }; - -static uchar VBE20_bankFunc32_End[] = { - 0x59,0x5B, /* pop ecx,ebx */ - }; - -static uchar bankFunc32[100]; - -#define copy(p,b,a) memcpy(b,a,sizeof(a)); (p) = (b) + sizeof(a) - -ibool VBEAPI VBE_getBankFunc32(int *codeLen,void **bankFunc,int dualBanks, - int bankAdjust) -/**************************************************************************** -* -* Function: VBE_getBankFunc32 -* Parameters: codeLen - Place to store length of code -* bankFunc - Place to store pointer to bank switch code -* dualBanks - True if dual banks are in effect -* bankAdjust - Bank shift adjustment factor -* Returns: True on success, false if not compatible. -* -* Description: Creates a local 32 bit bank switch function from the -* VBE 2.0 bank switch code that is compatible with the -* virtual flat framebuffer devices (does not have a return -* instruction at the end and takes the bank number in EAX -* not EDX). Note that this 32 bit code cannot include int 10h -* instructions, so we can only do this if we have VBE 2.0 -* or later. -* -* Note that we need to know the length of the 32 bit -* bank switch function, which the standard VBE 2.0 spec -* does not provide. In order to support this we have -* extended the VBE 2.0 state->pmInfo structure in UniVBE 5.2 in a -* way to support this, and we hope that this will become -* a VBE 2.0 ammendment. -* -* Note also that we cannot run the linear framebuffer -* emulation code with bank switching routines that require -* a selector to the memory mapped registers passed in ES. -* -****************************************************************************/ -{ - int len; - uchar *code; - uchar *p; - - InitPMCode(); - if (state->VBEVersion >= 0x200 && state->pmInfo32 && !state->MMIOSel) { - code = (uchar*)state->pmInfo32 + state->pmInfo32->setWindow; - if (state->pmInfo32->extensionSig == VBE20_EXT_SIG) - len = state->pmInfo32->setWindowLen-1; - else { - /* We are running on a system without the UniVBE 5.2 extension. - * We do as best we can by scanning through the code for the - * ret function to determine the length. This is not foolproof, - * but is the best we can do. - */ - p = code; - while (*p != 0xC3) - p++; - len = p - code; - } - if ((len + sizeof(VBE20A_bankFunc32_Start) + sizeof(VBE20_bankFunc32_End)) > sizeof(bankFunc32)) - PM_fatalError("32-bit bank switch function too long!"); - copy(p,bankFunc32,VBE20A_bankFunc32_Start); - memcpy(p,code,len); - p += len; - copy(p,p,VBE20_bankFunc32_End); - *codeLen = p - bankFunc32; - bankFunc32[VBE20_adjustOffset] = (uchar)bankAdjust; - *bankFunc = bankFunc32; - return true; - } - return false; -} - -#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c deleted file mode 100644 index cb3afe2..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** -* -* Description: Module to implement OS specific services to measure the -* CPU frequency. -* -****************************************************************************/ - -#include - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Increase the thread priority to maximum, if possible. -****************************************************************************/ -static int SetMaxThreadPriority(void) -{ - thread_id thid = find_thread(NULL); - thread_info tinfo; - get_thread_info(thid, &tinfo); - set_thread_priority(thid, B_REAL_TIME_PRIORITY); - return tinfo.priority; -} - -/**************************************************************************** -REMARKS: -Restore the original thread priority. -****************************************************************************/ -static void RestoreThreadPriority( - int priority) -{ - thread_id thid = find_thread(NULL); - set_thread_priority(thid, priority); -} - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - /* TODO: Return the frequency of the counter in here. You should try to */ - /* normalise this value to be around 100,000 ticks per second. */ - freq->low = 1000000; - freq->high = 0; -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. - -TODO: Implement this to read the counter. It should be done as a macro - for accuracy. -****************************************************************************/ -#define GetCounter(t) { *((bigtime_t*) t) = system_time(); } diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/event.c b/board/MAI/bios_emulator/scitech/src/pm/beos/event.c deleted file mode 100644 index 93c6c0a..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/beos/event.c +++ /dev/null @@ -1,199 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: BeOS -* -* Description: BeOS implementation for the SciTech cross platform -* event library. -* -****************************************************************************/ - -/*---------------------------- Global Variables ---------------------------*/ - -static ushort keyUpMsg[256] = {0};/* Table of key up messages */ -static int rangeX,rangeY; /* Range of mouse coordinates */ - -/*---------------------------- Implementation -----------------------------*/ - -/* These are not used under non-DOS systems */ -#define _EVT_disableInt() 1 -#define _EVT_restoreInt(flags) - -/**************************************************************************** -PARAMETERS: -scanCode - Scan code to test - -REMARKS: -This macro determines if a specified key is currently down at the -time that the call is made. -****************************************************************************/ -#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) - -/**************************************************************************** -REMARKS: -This function is used to return the number of ticks since system -startup in milliseconds. This should be the same value that is placed into -the time stamp fields of events, and is used to implement auto mouse down -events. -****************************************************************************/ -ulong _EVT_getTicks(void) -{ - /* TODO: Implement this for your OS! */ -} - -/**************************************************************************** -REMARKS: -Pumps all messages in the application message queue into our event queue. -****************************************************************************/ -static void _EVT_pumpMessages(void) -{ - /* TODO: The purpose of this function is to read all keyboard and mouse */ - /* events from the OS specific event queue, translate them and post */ - /* them into the SciTech event queue. */ - /* */ - /* NOTE: There are a couple of important things that this function must */ - /* take care of: */ - /* */ - /* 1. Support for KEYDOWN, KEYREPEAT and KEYUP is required. */ - /* */ - /* 2. Support for reading hardware scan code as well as ASCII */ - /* translated values is required. Games use the scan codes rather */ - /* than ASCII values. Scan codes go into the high order byte of the */ - /* keyboard message field. */ - /* */ - /* 3. Support for at least reading mouse motion data (mickeys) from the */ - /* mouse is required. Using the mickey values, we can then translate */ - /* to mouse cursor coordinates scaled to the range of the current */ - /* graphics display mode. Mouse values are scaled based on the */ - /* global 'rangeX' and 'rangeY'. */ - /* */ - /* 4. Support for a timestamp for the events is required, which is */ - /* defined as the number of milliseconds since some event (usually */ - /* system startup). This is the timestamp when the event occurred */ - /* (ie: at interrupt time) not when it was stuff into the SciTech */ - /* event queue. */ - /* */ - /* 5. Support for mouse double click events. If the OS has a native */ - /* mechanism to determine this, it should be used. Otherwise the */ - /* time stamp information will be used by the generic event code */ - /* to generate double click events. */ -} - -/**************************************************************************** -REMARKS: -This macro/function is used to converts the scan codes reported by the -keyboard to our event libraries normalised format. We only have one scan -code for the 'A' key, and use shift modifiers to determine if it is a -Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, -but the OS gives us 'cooked' scan codes, we have to translate them back -to the raw format. -****************************************************************************/ -#define _EVT_maskKeyCode(evt) - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _EVT_abort() -{ - EVT_exit(); - PM_fatalError("Unhandled exception!"); -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -void EVTAPI EVT_init( - _EVT_mouseMoveHandler mouseMove) -{ - /* Initialise the event queue */ - _mouseMove = mouseMove; - initEventQueue(); - memset(keyUpMsg,0,sizeof(keyUpMsg)); - - /* TODO: Do any OS specific initialisation here */ - - /* Catch program termination signals so we can clean up properly */ - signal(SIGABRT, _EVT_abort); - signal(SIGFPE, _EVT_abort); - signal(SIGINT, _EVT_abort); -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - rangeX = xRes; - rangeY = yRes; -} - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVT_resume(void) -{ - /* Do nothing for non DOS systems */ -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVT_suspend(void) -{ - /* Do nothing for non DOS systems */ -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVT_exit(void) -{ - /* Restore signal handlers */ - signal(SIGABRT, SIG_DFL); - signal(SIGFPE, SIG_DFL); - signal(SIGINT, SIG_DFL); - - /* TODO: Do any OS specific cleanup in here */ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h deleted file mode 100644 index 043d73e..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h +++ /dev/null @@ -1,32 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: BeOS -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ - -/* This is where you include OS specific headers for the event handling */ -/* library. */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c b/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c deleted file mode 100644 index 2dcb1b8..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c +++ /dev/null @@ -1,539 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: BeOS -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include -#include -#include - -/* TODO: Include any BeOS specific headers here! */ - -/*--------------------------- Global variables ----------------------------*/ - -static void (PMAPIP fatalErrorCleanup)(void) = NULL; - -/*----------------------------- Implementation ----------------------------*/ - -void PMAPI PM_init(void) -{ - /* TODO: Do any initialisation in here. This includes getting IOPL */ - /* access for the process calling PM_init. This will get called */ - /* more than once. */ - - /* TODO: If you support the supplied MTRR register stuff (you need to */ - /* be at ring 0 for this!), you should initialise it in here. */ - -/* MTRR_init(); */ -} - -long PMAPI PM_getOSType(void) -{ return _OS_BEOS; } - -int PMAPI PM_getModeType(void) -{ return PM_386; } - -void PMAPI PM_backslash(char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '/') { - s[pos] = '/'; - s[pos+1] = '\0'; - } -} - -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -void PMAPI PM_fatalError(const char *msg) -{ - /* TODO: If you are running in a GUI environment without a console, */ - /* this needs to be changed to bring up a fatal error message */ - /* box and terminate the program. */ - if (fatalErrorCleanup) - fatalErrorCleanup(); - fprintf(stderr,"%s\n", msg); - exit(1); -} - -void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) -{ - /* No BIOS access for the BeOS */ - return NULL; -} - -int PMAPI PM_kbhit(void) -{ - /* TODO: This function checks if a key is available to be read. This */ - /* should be implemented, but is mostly used by the test programs */ - /* these days. */ - return true; -} - -int PMAPI PM_getch(void) -{ - /* TODO: This returns the ASCII code of the key pressed. This */ - /* should be implemented, but is mostly used by the test programs */ - /* these days. */ - return 0xD; -} - -int PMAPI PM_openConsole(void) -{ - /* TODO: Opens up a fullscreen console for graphics output. If your */ - /* console does not have graphics/text modes, this can be left */ - /* empty. The main purpose of this is to disable console switching */ - /* when in graphics modes if you can switch away from fullscreen */ - /* consoles (if you want to allow switching, this can be done */ - /* elsewhere with a full save/restore state of the graphics mode). */ - return 0; -} - -int PMAPI PM_getConsoleStateSize(void) -{ - /* TODO: Returns the size of the console state buffer used to save the */ - /* state of the console before going into graphics mode. This is */ - /* used to restore the console back to normal when we are done. */ - return 1; -} - -void PMAPI PM_saveConsoleState(void *stateBuf,int console_id) -{ - /* TODO: Saves the state of the console into the state buffer. This is */ - /* used to restore the console back to normal when we are done. */ - /* We will always restore 80x25 text mode after being in graphics */ - /* mode, so if restoring text mode is all you need to do this can */ - /* be left empty. */ -} - -void PMAPI PM_restoreConsoleState(const void *stateBuf,int console_id) -{ - /* TODO: Restore the state of the console from the state buffer. This is */ - /* used to restore the console back to normal when we are done. */ - /* We will always restore 80x25 text mode after being in graphics */ - /* mode, so if restoring text mode is all you need to do this can */ - /* be left empty. */ -} - -void PMAPI PM_closeConsole(int console_id) -{ - /* TODO: Close the console when we are done, going back to text mode. */ -} - -void PM_setOSCursorLocation(int x,int y) -{ - /* TODO: Set the OS console cursor location to the new value. This is */ - /* generally used for new OS ports (used mostly for DOS). */ -} - -void PM_setOSScreenWidth(int width,int height) -{ - /* TODO: Set the OS console screen width. This is generally unused for */ - /* new OS ports. */ -} - -ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency) -{ - /* TODO: Install a real time clock interrupt handler. Normally this */ - /* will not be supported from most OS'es in user land, so an */ - /* alternative mechanism is needed to enable software stereo. */ - /* Hence leave this unimplemented unless you have a high priority */ - /* mechanism to call the 32-bit callback when the real time clock */ - /* interrupt fires. */ - return false; -} - -void PMAPI PM_setRealTimeClockFrequency(int frequency) -{ - /* TODO: Set the real time clock interrupt frequency. Used for stereo */ - /* LC shutter glasses when doing software stereo. Usually sets */ - /* the frequency to around 2048 Hz. */ -} - -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - /* TODO: Restores the real time clock handler. */ -} - -char * PMAPI PM_getCurrentPath( - char *path, - int maxLen) -{ - return getcwd(path,maxLen); -} - -char PMAPI PM_getBootDrive(void) -{ return '/'; } - -const char * PMAPI PM_getVBEAFPath(void) -{ return PM_getNucleusConfigPath(); } - -const char * PMAPI PM_getNucleusPath(void) -{ - char *env = getenv("NUCLEUS_PATH"); - return env ? env : "/usr/lib/nucleus"; -} - -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[256]; - strcpy(path,PM_getNucleusPath()); - PM_backslash(path); - strcat(path,"config"); - return path; -} - -const char * PMAPI PM_getUniqueID(void) -{ - /* TODO: Return a unique ID for the machine. If a unique ID is not */ - /* available, return the machine name. */ - static char buf[128]; - gethostname(buf, 128); - return buf; -} - -const char * PMAPI PM_getMachineName(void) -{ - /* TODO: Return the network machine name for the machine. */ - static char buf[128]; - gethostname(buf, 128); - return buf; -} - -void * PMAPI PM_getBIOSPointer(void) -{ - /* No BIOS access on the BeOS */ - return NULL; -} - -void * PMAPI PM_getA0000Pointer(void) -{ - static void *bankPtr; - if (!bankPtr) - bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); - return bankPtr; -} - -void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) -{ - /* TODO: This function maps a physical memory address to a linear */ - /* address in the address space of the calling process. */ - - /* NOTE: This function *must* be able to handle any phsyical base */ - /* address, and hence you will have to handle rounding of */ - /* the physical base address to a page boundary (ie: 4Kb on */ - /* x86 CPU's) to be able to properly map in the memory */ - /* region. */ - - /* NOTE: If possible the isCached bit should be used to ensure that */ - /* the PCD (Page Cache Disable) and PWT (Page Write Through) */ - /* bits are set to disable caching for a memory mapping used */ - /* for MMIO register access. We also disable caching using */ - /* the MTRR registers for Pentium Pro and later chipsets so if */ - /* MTRR support is enabled for your OS then you can safely ignore */ - /* the isCached flag and always enable caching in the page */ - /* tables. */ - return NULL; -} - -void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) -{ - /* TODO: This function will free a physical memory mapping previously */ - /* allocated with PM_mapPhysicalAddr() if at all possible. If */ - /* you can't free physical memory mappings, simply do nothing. */ -} - -ulong PMAPI PM_getPhysicalAddr(void *p) -{ - /* TODO: This function should find the physical address of a linear */ - /* address. */ - return 0xFFFFFFFFUL; -} - -void PMAPI PM_sleep(ulong milliseconds) -{ - /* TODO: Put the process to sleep for milliseconds */ -} - -int PMAPI PM_getCOMPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - } - return 0; -} - -int PMAPI PM_getLPTPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -void * PMAPI PM_mallocShared(long size) -{ - /* TODO: This is used to allocate memory that is shared between process */ - /* that all access the common Nucleus drivers via a common display */ - /* driver DLL. If your OS does not support shared memory (or if */ - /* the display driver does not need to allocate shared memory */ - /* for each process address space), this should just call PM_malloc. */ - return PM_malloc(size); -} - -void PMAPI PM_freeShared(void *ptr) -{ - /* TODO: Free the shared memory block. This will be called in the context */ - /* of the original calling process that allocated the shared */ - /* memory with PM_mallocShared. Simply call free if you do not */ - /* need this. */ - PM_free(ptr); -} - -void * PMAPI PM_mapToProcess(void *base,ulong limit) -{ - /* TODO: This function is used to map a physical memory mapping */ - /* previously allocated with PM_mapPhysicalAddr into the */ - /* address space of the calling process. If the memory mapping */ - /* allocated by PM_mapPhysicalAddr is global to all processes, */ - /* simply return the pointer. */ - return base; -} - -void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) -{ - /* No BIOS access on the BeOS */ - return NULL; -} - -void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) -{ - /* No BIOS access on the BeOS */ - return NULL; -} - -void PMAPI PM_freeRealSeg(void *mem) -{ - /* No BIOS access on the BeOS */ -} - -void PMAPI DPMI_int86(int intno, DPMI_regs *regs) -{ - /* No BIOS access on the BeOS */ -} - -int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) -{ - /* No BIOS access on the BeOS */ - return 0; -} - -int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, - RMSREGS *sregs) -{ - /* No BIOS access on the BeOS */ - return 0; -} - -void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, - RMSREGS *sregs) -{ - /* No BIOS access on the BeOS */ -} - -void PMAPI PM_availableMemory(ulong *physical,ulong *total) -{ - /* TODO: Report the amount of available memory, both the amount of */ - /* physical memory left and the amount of virtual memory left. */ - /* If the OS does not provide these services, report 0's. */ - *physical = *total = 0; -} - -void * PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg) -{ - /* TODO: Allocate a block of locked, physical memory of the specified */ - /* size. This is used for bus master operations. If this is not */ - /* supported by the OS, return NULL and bus mastering will not */ - /* be used. */ - return NULL; -} - -void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) -{ - /* TODO: Free a memory block allocated with PM_allocLockedMem. */ -} - -void PMAPI PM_setBankA(int bank) -{ - /* No BIOS access on the BeOS */ -} - -void PMAPI PM_setBankAB(int bank) -{ - /* No BIOS access on the BeOS */ -} - -void PMAPI PM_setCRTStart(int x,int y,int waitVRT) -{ - /* No BIOS access on the BeOS */ -} - -ibool PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type) -{ - /* TODO: This function should enable Pentium Pro and Pentium II MTRR */ - /* write combining for the passed in physical memory base address */ - /* and length. Normally this is done via calls to an OS specific */ - /* device driver as this can only be done at ring 0. */ - /* */ - /* NOTE: This is a *very* important function to implement! If you do */ - /* not implement, graphics performance on the latest Intel chips */ - /* will be severly impaired. For sample code that can be used */ - /* directly in a ring 0 device driver, see the MSDOS implementation */ - /* which includes assembler code to do this directly (if the */ - /* program is running at ring 0). */ - return false; -} - -ibool PMAPI PM_doBIOSPOST(ushort axVal,ulong BIOSPhysAddr,void *mappedBIOS) -{ - /* TODO: This function is used to run the BIOS POST code on a secondary */ - /* controller to initialise it for use. This is not necessary */ - /* for multi-controller operation, but it will make it a lot */ - /* more convenicent for end users (otherwise they have to boot */ - /* the system once with the secondary controller as primary, and */ - /* then boot with both controllers installed). */ - /* */ - /* Even if you don't support full BIOS access, it would be */ - /* adviseable to be able to POST the secondary controllers in the */ - /* system using this function as a minimum requirement. Some */ - /* graphics hardware has registers that contain values that only */ - /* the BIOS knows about, which makes bring up a card from cold */ - /* reset difficult if the BIOS has not POST'ed it. */ - return false; -} - -/**************************************************************************** -REMARKS: -Function to find the first file matching a search criteria in a directory. -****************************************************************************/ -ulong PMAPI PM_findFirstFile( - const char *filename, - PM_findData *findData) -{ - (void)filename; - (void)findData; - return PM_FILE_INVALID; -} - -/**************************************************************************** -REMARKS: -Function to find the next file matching a search criteria in a directory. -****************************************************************************/ -ibool PMAPI PM_findNextFile( - ulong handle, - PM_findData *findData) -{ - (void)handle; - (void)findData; - return false; -} - -/**************************************************************************** -REMARKS: -Function to close the find process -****************************************************************************/ -void PMAPI PM_findClose( - ulong handle) -{ - (void)handle; -} - -/**************************************************************************** -REMARKS: -Function to determine if a drive is a valid drive or not. Under Unix this -function will return false for anything except a value of 3 (considered -the root drive, and equivalent to C: for non-Unix systems). The drive -numbering is: - - 1 - Drive A: - 2 - Drive B: - 3 - Drive C: - etc - -****************************************************************************/ -ibool PMAPI PM_driveValid( - char drive) -{ - if (drive == 3) - return true; - return false; -} - -/**************************************************************************** -REMARKS: -Function to get the current working directory for the specififed drive. -Under Unix this will always return the current working directory regardless -of what the value of 'drive' is. -****************************************************************************/ -void PMAPI PM_getdcwd( - int drive, - char *dir, - int len) -{ - (void)drive; - getcwd(dir,len); -} - -/**************************************************************************** -REMARKS: -Function to change the file attributes for a specific file. -****************************************************************************/ -void PMAPI PM_setFileAttr( - const char *filename, - uint attrib) -{ - /* TODO: Set the file attributes for a file */ - (void)filename; - (void)attrib; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c deleted file mode 100644 index 579ef2c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Dummy module; no virtual framebuffer for this OS -* -****************************************************************************/ - -#include "pmapi.h" - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -{ - baseAddr = baseAddr; - bankSize = bankSize; - codeLen = codeLen; - bankFunc = bankFunc; - return NULL; -} - -void PMAPI VF_exit(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c deleted file mode 100644 index a528b73..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** -* -* Description: OS specific implementation for the Zen Timer functions. -* -****************************************************************************/ - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -void _ZTimerInit(void) -{ - /* TODO: Do any specific internal initialisation in here */ -} - -/**************************************************************************** -REMARKS: -Start the Zen Timer counting. -****************************************************************************/ -static void _LZTimerOn( - LZTimerObject *tm) -{ - /* TODO: Start the Zen Timer counting. This should be a macro if */ - /* possible. */ -} - -/**************************************************************************** -REMARKS: -Compute the lap time since the timer was started. -****************************************************************************/ -static ulong _LZTimerLap( - LZTimerObject *tm) -{ - /* TODO: Compute the lap time between the current time and when the */ - /* timer was started. */ - return 0; -} - -/**************************************************************************** -REMARKS: -Stop the Zen Timer counting. -****************************************************************************/ -static void _LZTimerOff( - LZTimerObject *tm) -{ - /* TODO: Stop the timer counting. Should be a macro if possible. */ -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time in microseconds between start and end timings. -****************************************************************************/ -static ulong _LZTimerCount( - LZTimerObject *tm) -{ - /* TODO: Compute the elapsed time and return it. Always microseconds. */ - return 0; -} - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as microseconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION 1 - -/**************************************************************************** -REMARKS: -Read the Long Period timer from the OS -****************************************************************************/ -static ulong _ULZReadTime(void) -{ - /* TODO: Read the long period timer from the OS. The resolution of this */ - /* timer should be around 1/20 of a second for timing long */ - /* periods if possible. */ -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong _ULZElapsedTime(ulong start,ulong finish) -{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c b/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c deleted file mode 100644 index 9aa8714..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c +++ /dev/null @@ -1,285 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Keyboard translation code pages for US English keyboards. -* -****************************************************************************/ - -#include "event.h" - -/*--------------------------- Global variables ----------------------------*/ - -/* This table is used for all normal key translations, and is the fallback - * table if the key is not found in any of the other translation tables. - * If the code is not found in this table, the ASCII code is set to 0 to - * indicate that there is no ASCII code equivalent for this key. - */ -static codepage_entry_t US_normal[] = { - {0x01, 0x1B}, - {0x02, '1'}, - {0x03, '2'}, - {0x04, '3'}, - {0x05, '4'}, - {0x06, '5'}, - {0x07, '6'}, - {0x08, '7'}, - {0x09, '8'}, - {0x0A, '9'}, - {0x0B, '0'}, - {0x0C, '-'}, - {0x0D, '='}, - {0x0E, 0x08}, - {0x0F, 0x09}, - {0x10, 'q'}, - {0x11, 'w'}, - {0x12, 'e'}, - {0x13, 'r'}, - {0x14, 't'}, - {0x15, 'y'}, - {0x16, 'u'}, - {0x17, 'i'}, - {0x18, 'o'}, - {0x19, 'p'}, - {0x1A, '['}, - {0x1B, ']'}, - {0x1C, 0x0D}, - {0x1E, 'a'}, - {0x1F, 's'}, - {0x20, 'd'}, - {0x21, 'f'}, - {0x22, 'g'}, - {0x23, 'h'}, - {0x24, 'j'}, - {0x25, 'k'}, - {0x26, 'l'}, - {0x27, ';'}, - {0x28, '\''}, - {0x29, '`'}, - {0x2B, '\\'}, - {0x2C, 'z'}, - {0x2D, 'x'}, - {0x2E, 'c'}, - {0x2F, 'v'}, - {0x30, 'b'}, - {0x31, 'n'}, - {0x32, 'm'}, - {0x33, ','}, - {0x34, '.'}, - {0x35, '/'}, - {0x37, '*'}, /* Keypad */ - {0x39, ' '}, - {0x4A, '-'}, /* Keypad */ - {0x4E, '+'}, /* Keypad */ - {0x60, 0x0D}, /* Keypad */ - {0x61, '/'}, /* Keypad */ - }; - -/* This table is used for when CAPSLOCK is active and the shift or ctrl - * keys are not down. If the code is not found in this table, the normal - * table above is then searched. - */ -static codepage_entry_t US_caps[] = { - {0x10, 'Q'}, - {0x11, 'W'}, - {0x12, 'E'}, - {0x13, 'R'}, - {0x14, 'T'}, - {0x15, 'Y'}, - {0x16, 'U'}, - {0x17, 'I'}, - {0x18, 'O'}, - {0x19, 'P'}, - {0x1E, 'A'}, - {0x1F, 'S'}, - {0x20, 'D'}, - {0x21, 'F'}, - {0x22, 'G'}, - {0x23, 'H'}, - {0x24, 'J'}, - {0x25, 'K'}, - {0x26, 'L'}, - {0x2C, 'Z'}, - {0x2D, 'X'}, - {0x2E, 'C'}, - {0x2F, 'V'}, - {0x30, 'B'}, - {0x31, 'N'}, - {0x32, 'M'}, - }; - -/* This table is used for when shift key is down, but the ctrl key is not - * down and CAPSLOCK is not active. If the code is not found in this table, - * the normal table above is then searched. - */ -static codepage_entry_t US_shift[] = { - {0x02, '!'}, - {0x03, '@'}, - {0x04, '#'}, - {0x05, '$'}, - {0x06, '%'}, - {0x07, '^'}, - {0x08, '&'}, - {0x09, '*'}, - {0x0A, '('}, - {0x0B, ')'}, - {0x0C, '_'}, - {0x0D, '+'}, - {0x10, 'Q'}, - {0x11, 'W'}, - {0x12, 'E'}, - {0x13, 'R'}, - {0x14, 'T'}, - {0x15, 'Y'}, - {0x16, 'U'}, - {0x17, 'I'}, - {0x18, 'O'}, - {0x19, 'P'}, - {0x1A, '{'}, - {0x1B, '}'}, - {0x1E, 'A'}, - {0x1F, 'S'}, - {0x20, 'D'}, - {0x21, 'F'}, - {0x22, 'G'}, - {0x23, 'H'}, - {0x24, 'J'}, - {0x25, 'K'}, - {0x26, 'L'}, - {0x27, ':'}, - {0x28, '"'}, - {0x29, '~'}, - {0x2B, '|'}, - {0x2C, 'Z'}, - {0x2D, 'X'}, - {0x2E, 'C'}, - {0x2F, 'V'}, - {0x30, 'B'}, - {0x31, 'N'}, - {0x32, 'M'}, - {0x33, '<'}, - {0x34, '>'}, - {0x35, '?'}, - }; - -/* This table is used for when CAPSLOCK is active and the shift key is - * down, but the ctrl key is not. If the code is not found in this table, - * the shift table above is then searched. - */ -static codepage_entry_t US_shiftCaps[] = { - {0x10, 'q'}, - {0x11, 'w'}, - {0x12, 'e'}, - {0x13, 'r'}, - {0x14, 't'}, - {0x15, 'y'}, - {0x16, 'u'}, - {0x17, 'i'}, - {0x18, 'o'}, - {0x19, 'p'}, - {0x1E, 'a'}, - {0x1F, 's'}, - {0x20, 'd'}, - {0x21, 'f'}, - {0x22, 'g'}, - {0x23, 'h'}, - {0x24, 'j'}, - {0x25, 'k'}, - {0x26, 'l'}, - {0x2C, 'z'}, - {0x2D, 'x'}, - {0x2E, 'c'}, - {0x2F, 'v'}, - {0x30, 'b'}, - {0x31, 'n'}, - {0x32, 'm'}, - }; - -/* This table is used for all key translations when the ctrl key is down, - * regardless of the state of the shift key and CAPSLOCK. If the code is - * not found in this table, the ASCII code is set to 0 to indicate that - * there is no ASCII code equivalent for this key. - */ -static codepage_entry_t US_ctrl[] = { - {0x01, 0x1B}, - {0x06, 0x1E}, - {0x0C, 0x1F}, - {0x0E, 0x7F}, - {0x10, 0x11}, - {0x11, 0x17}, - {0x12, 0x05}, - {0x13, 0x12}, - {0x14, 0x14}, - {0x15, 0x19}, - {0x16, 0x16}, - {0x17, 0x09}, - {0x18, 0x0F}, - {0x19, 0x10}, - {0x1A, 0x1B}, - {0x1B, 0x1D}, - {0x1C, 0x0A}, - {0x1E, 0x01}, - {0x1F, 0x13}, - {0x20, 0x04}, - {0x21, 0x06}, - {0x22, 0x07}, - {0x23, 0x08}, - {0x24, 0x0A}, - {0x25, 0x0B}, - {0x26, 0x0C}, - {0x2B, 0x1C}, - {0x2C, 0x1A}, - {0x2D, 0x18}, - {0x2E, 0x03}, - {0x2F, 0x16}, - {0x30, 0x02}, - {0x31, 0x0E}, - {0x32, 0x0D}, - {0x39, ' '}, - }; - -static codepage_entry_t US_numPad[] = { - {0x4C, '5'}, - {0x62, '4'}, - {0x63, '6'}, - {0x64, '8'}, - {0x65, '2'}, - {0x66, '0'}, - {0x67, '.'}, - {0x68, '7'}, - {0x69, '1'}, - {0x6A, '9'}, - {0x6B, '3'}, - }; - -codepage_t _CP_US_English = { - "US English", - US_normal, EVT_ARR_SIZE(US_normal), - US_caps, EVT_ARR_SIZE(US_caps), - US_shift, EVT_ARR_SIZE(US_shift), - US_shiftCaps, EVT_ARR_SIZE(US_shiftCaps), - US_ctrl, EVT_ARR_SIZE(US_ctrl), - US_numPad, EVT_ARR_SIZE(US_numPad), - }; diff --git a/board/MAI/bios_emulator/scitech/src/pm/common.c b/board/MAI/bios_emulator/scitech/src/pm/common.c deleted file mode 100644 index d5a8e8f..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common.c +++ /dev/null @@ -1,480 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Module containing code common to all platforms. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#if defined(__WIN32_VXD__) || defined(__OS2_VDD__) || defined(__NT_DRIVER__) -#include "sdd/sddhelp.h" -#else -#include -#include -#include -#endif - -/*---------------------------- Global variables ---------------------------*/ - -/* {secret} */ -long _VARAPI ___drv_os_type = _OS_UNSUPPORTED; -static char localBPDPath[PM_MAX_PATH] = ""; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -PARAMETERS: -path - Local path to the Nucleus BPD driver files. - -REMARKS: -This function is used by the application program to override the location -of the Nucleus driver files that are loaded. Normally the loader code -will look in the system Nucleus directories first, then in the 'drivers' -directory relative to the current working directory, and finally relative -to the MGL_ROOT environment variable. By default the local BPD path is -always set to the current directory if not initialised. -****************************************************************************/ -void PMAPI PM_setLocalBPDPath( - const char *path) -{ - PM_init(); - strncpy(localBPDPath,path,sizeof(localBPDPath)); - localBPDPath[sizeof(localBPDPath)-1] = 0; -} - -/**************************************************************************** -PARAMETERS: -bpdpath - Place to store the actual path to the file -cachedpath - Place to store the cached BPD driver path -trypath - Path to try to find the BPD file in -subpath - Optional sub path to append to trypath -dllname - Name of the Binary Portable DLL to load - -RETURNS: -True if found, false if not. - -REMARKS: -Trys the specified path to see if the BPD file can be found or not. If so, -the path used is returned in bpdpath and cachedpath. -****************************************************************************/ -static ibool TryPath( - char *bpdpath, - char *cachedpath, - const char *trypath, - const char *subpath, - const char *dllname) -{ - char filename[256]; - FILE *f; - - strcpy(bpdpath, trypath); - PM_backslash(bpdpath); - strcat(bpdpath,subpath); - PM_backslash(bpdpath); - strcpy(filename,bpdpath); - strcat(filename,dllname); - if ((f = fopen(filename,"rb")) == NULL) - return false; - if (cachedpath) - strcpy(cachedpath,bpdpath); - fclose(f); - return true; -} - -/**************************************************************************** -RETURNS: -True if local override enabled, false if not. - -REMARKS: -Tests to see if the local override option is enabled, and if so it will -look for the Nucleus drivers in the local application directories in -preference to the Nucleus system directories. -****************************************************************************/ -static ibool GetLocalOverride(void) -{ - char filename[256]; - FILE *f; - static ibool local_override = -1; - - if (local_override == -1) { - local_override = false; - strcpy(filename,PM_getNucleusPath()); - PM_backslash(filename); - strcat(filename,"graphics.ini"); - if ((f = fopen(filename,"r")) != NULL) { - while (!feof(f) && fgets(filename,sizeof(filename),f)) { - if (strnicmp(filename,"uselocal",8) == 0) { - local_override = ((*(filename+9) - '0') == 1); - break; - } - } - fclose(f); - } - } - return local_override; -} - -/**************************************************************************** -DESCRIPTION: -Sets the location of the debug log file. - -HEADER: -pmapi.h - -PARAMETERS: -dllname - Name of the Binary Portable DLL to load -bpdpath - Place to store the actual path to the file - -RETURNS: -True if found, false if not. - -REMARKS: -Finds the location of a specific Binary Portable DLL, by searching all -the standard SciTech Nucleus driver locations. -****************************************************************************/ -ibool PMAPI PM_findBPD( - const char *dllname, - char *bpdpath) -{ - static char cachedpath[PM_MAX_PATH] = ""; - - /* On the first call determine the path to the Nucleus drivers */ - if (cachedpath[0] == 0) { - /* First try in the global system Nucleus driver path if - * the local override setting is not enabled. - */ - PM_init(); - if (!GetLocalOverride()) { - if (TryPath(bpdpath,cachedpath,PM_getNucleusPath(),"",dllname)) - return true; - } - - /* Next try in the local application directory if available */ - if (localBPDPath[0] != 0) { - if (TryPath(bpdpath,cachedpath,localBPDPath,"",dllname)) - return true; - } - else { -#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) - char *mgl_root; - if ((mgl_root = getenv("MGL_ROOT")) != NULL) { - if (TryPath(bpdpath,cachedpath,mgl_root,"drivers",dllname)) - return true; - } -#endif - PM_getCurrentPath(bpdpath,PM_MAX_PATH); - if (TryPath(bpdpath,cachedpath,bpdpath,"drivers",dllname)) - return true; - } - - /* Finally try in the global system path again so that we - * will still find the drivers in the global system path if - * the local override option is on, but the application does - * not have any local override drivers. - */ - if (TryPath(bpdpath,cachedpath,PM_getNucleusPath(),"",dllname)) - return true; - - /* Whoops, we can't find the BPD file! */ - return false; - } - - /* Always try in the previously discovered path */ - return TryPath(bpdpath,NULL,cachedpath,"",dllname); -} - -/**************************************************************************** -REMARKS: -Copies a string into another, and returns dest + strlen(src). -****************************************************************************/ -static char *_stpcpy( - char *_dest, - const char *_src) -{ - if (!_dest || !_src) - return 0; - while ((*_dest++ = *_src++) != 0) - ; - return --_dest; -} - -/**************************************************************************** -REMARKS: -Copies a string into another, stopping at the maximum length. The string -is properly terminated (unlike strncpy). -****************************************************************************/ -static void safe_strncpy( - char *dst, - const char *src, - unsigned maxlen) -{ - if (dst) { - if(strlen(src) >= maxlen) { - strncpy(dst, src, maxlen); - dst[maxlen] = 0; - } - else - strcpy(dst, src); - } -} - -/**************************************************************************** -REMARKS: -Determins if the dot separator is present in the string. -****************************************************************************/ -static int findDot( - char *p) -{ - if (*(p-1) == '.') - p--; - switch (*--p) { - case ':': - if (*(p-2) != '\0') - break; - case '/': - case '\\': - case '\0': - return true; - } - return false; -} - -/**************************************************************************** -DESCRIPTION: -Make a full pathname from split components. - -HEADER: -pmapi.h - -PARAMETERS: -path - Place to store full path -drive - Drive component for path -dir - Directory component for path -name - Filename component for path -ext - Extension component for path - -REMARKS: -Function to make a full pathname from split components. Under Unix the -drive component will usually be empty. If the drive, dir, name, or ext -parameters are null or empty, they are not inserted in the path string. -Otherwise, if the drive doesn't end with a colon, one is inserted in the -path. If the dir doesn't end in a slash, one is inserted in the path. -If the ext doesn't start with a dot, one is inserted in the path. - -The maximum sizes for the path string is given by the constant PM_MAX_PATH, -which includes space for the null-terminator. - -SEE ALSO: -PM_splitPath -****************************************************************************/ -void PMAPI PM_makepath( - char *path, - const char *drive, - const char *dir, - const char *name, - const char *ext) -{ - if (drive && *drive) { - *path++ = *drive; - *path++ = ':'; - } - if (dir && *dir) { - path = _stpcpy(path,dir); - if (*(path-1) != '\\' && *(path-1) != '/') -#ifdef __UNIX__ - *path++ = '/'; -#else - *path++ = '\\'; -#endif - } - if (name) - path = _stpcpy(path,name); - if (ext && *ext) { - if (*ext != '.') - *path++ = '.'; - path = _stpcpy(path,ext); - } - *path = 0; -} - -/**************************************************************************** -DESCRIPTION: -Split a full pathname into components. - -HEADER: -pmapi.h - -PARAMETERS: -path - Full path to split -drive - Drive component for path -dir - Directory component for path -name - Filename component for path -ext - Extension component for path - -RETURNS: -Flags indicating what components were parsed. - -REMARKS: -Function to split a full pathmame into separate components in the form - - X:\DIR\SUBDIR\NAME.EXT - -and splits path into its four components. It then stores those components -in the strings pointed to by drive, dir, name and ext. (Each component is -required but can be a NULL, which means the corresponding component will be -parsed but not stored). - -The maximum sizes for these strings are given by the constants PM_MAX_DRIVE -and PM_MAX_PATH. PM_MAX_DRIVE is always 4, and PM_MAX_PATH is usually at -least 256 characters. Under Unix the dir, name and ext components may be -up to the full path in length. - -SEE ALSO: -PM_makePath -****************************************************************************/ -int PMAPI PM_splitpath( - const char *path, - char *drive, - char *dir, - char *name, - char *ext) -{ - char *p; - int temp,ret; - char buf[PM_MAX_PATH+2]; - - /* Set all string to default value zero */ - ret = 0; - if (drive) *drive = 0; - if (dir) *dir = 0; - if (name) *name = 0; - if (ext) *ext = 0; - - /* Copy filename into template up to PM_MAX_PATH characters */ - p = buf; - if ((temp = strlen(path)) > PM_MAX_PATH) - temp = PM_MAX_PATH; - *p++ = 0; - strncpy(p, path, temp); - *(p += temp) = 0; - - /* Split the filename and fill corresponding nonzero pointers */ - temp = 0; - for (;;) { - switch (*--p) { - case '.': - if (!temp && (*(p+1) == '\0')) - temp = findDot(p); - if ((!temp) && ((ret & PM_HAS_EXTENSION) == 0)) { - ret |= PM_HAS_EXTENSION; - safe_strncpy(ext, p, PM_MAX_PATH - 1); - *p = 0; - } - continue; - case ':': - if (p != &buf[2]) - continue; - case '\0': - if (temp) { - if (*++p) - ret |= PM_HAS_DIRECTORY; - safe_strncpy(dir, p, PM_MAX_PATH - 1); - *p-- = 0; - break; - } - case '/': - case '\\': - if (!temp) { - temp++; - if (*++p) - ret |= PM_HAS_FILENAME; - safe_strncpy(name, p, PM_MAX_PATH - 1); - *p-- = 0; - if (*p == 0 || (*p == ':' && p == &buf[2])) - break; - } - continue; - case '*': - case '?': - if (!temp) - ret |= PM_HAS_WILDCARDS; - default: - continue; - } - break; - } - if (*p == ':') { - if (buf[1]) - ret |= PM_HAS_DRIVE; - safe_strncpy(drive, &buf[1], PM_MAX_DRIVE - 1); - } - return ret; -} - -/**************************************************************************** -DESCRIPTION: -Block until a specific time has elapsed since the last call - -HEADER: -pmapi.h - -PARAMETERS: -milliseconds - Number of milliseconds for delay - -REMARKS: -This function will block the calling thread or process until the specified -number of milliseconds have passed since the /last/ call to this function. -The first time this function is called, it will return immediately. On -subsquent calls it will block until the specified time has elapsed, or it -will return immediately if the time has already elapsed. - -This function is useful to provide constant time functionality in a -program, such as a frame rate limiter for graphics applications etc. - -SEE ALSO: -PM_sleep -****************************************************************************/ -void PMAPI PM_blockUntilTimeout( - ulong milliseconds) -{ - ulong microseconds = milliseconds * 1000L,msDelay; - static LZTimerObject tm; - static ibool firstTime = true; - - if (firstTime) { - firstTime = false; - LZTimerOnExt(&tm); - } - else { - if ((msDelay = (microseconds - LZTimerLapExt(&tm)) / 1000L) > 0) - PM_sleep(msDelay); - while (LZTimerLapExt(&tm) < microseconds) - ; - LZTimerOffExt(&tm); - LZTimerOnExt(&tm); - } -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm deleted file mode 100644 index 60ebed7..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm +++ /dev/null @@ -1,600 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: NASM or TASM Assembler -;* Environment: Intel 32 bit Protected Mode. -;* -;* Description: Code to determine the Intel processor type. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" - -header _cpuinfo - -begdataseg _cpuinfo ; Start of data segment - -cache_id db "01234567890123456" -intel_id db "GenuineIntel" ; Intel vendor ID -cyrix_id db "CyrixInstead" ; Cyrix vendor ID -amd_id db "AuthenticAMD" ; AMD vendor ID -idt_id db "CentaurHauls" ; IDT vendor ID - -CPU_IDT EQU 01000h ; Flag for IDT processors -CPU_Cyrix EQU 02000h ; Flag for Cyrix processors -CPU_AMD EQU 04000h ; Flag for AMD processors -CPU_Intel EQU 08000h ; Flag for Intel processors - -enddataseg _cpuinfo - -begcodeseg _cpuinfo ; Start of code segment - -ifdef USE_NASM -%macro mCPU_ID 0 -db 00Fh,0A2h -%endmacro -else -MACRO mCPU_ID -db 00Fh,0A2h -ENDM -endif - -ifdef USE_NASM -%macro mRDTSC 0 -db 00Fh,031h -%endmacro -else -MACRO mRDTSC -db 00Fh,031h -ENDM -endif - -;---------------------------------------------------------------------------- -; bool _CPU_check80386(void) -;---------------------------------------------------------------------------- -; Determines if we have an i386 processor. -;---------------------------------------------------------------------------- -cprocstart _CPU_check80386 - - enter_c - - xor edx,edx ; EDX = 0, not an 80386 - mov bx, sp -ifdef USE_NASM - and sp, ~3 -else - and sp, not 3 -endif - pushfd ; Push original EFLAGS - pop eax ; Get original EFLAGS - mov ecx, eax ; Save original EFLAGS - xor eax, 40000h ; Flip AC bit in EFLAGS - push eax ; Save new EFLAGS value on - ; stack - popfd ; Replace current EFLAGS value - pushfd ; Get new EFLAGS - pop eax ; Store new EFLAGS in EAX - xor eax, ecx ; Can't toggle AC bit, - ; processor=80386 - jnz @@Done ; Jump if not an 80386 processor - inc edx ; We have an 80386 - -@@Done: push ecx - popfd - mov sp, bx - mov eax, edx - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; bool _CPU_check80486(void) -;---------------------------------------------------------------------------- -; Determines if we have an i486 processor. -;---------------------------------------------------------------------------- -cprocstart _CPU_check80486 - - enter_c - -; Distinguish between the i486 and Pentium by the ability to set the ID flag -; in the EFLAGS register. If the ID flag is set, then we can use the CPUID -; instruction to determine the final version of the chip. Otherwise we -; simply have an 80486. - -; Distinguish between the i486 and Pentium by the ability to set the ID flag -; in the EFLAGS register. If the ID flag is set, then we can use the CPUID -; instruction to determine the final version of the chip. Otherwise we -; simply have an 80486. - - pushfd ; Get original EFLAGS - pop eax - mov ecx, eax - xor eax, 200000h ; Flip ID bit in EFLAGS - push eax ; Save new EFLAGS value on stack - popfd ; Replace current EFLAGS value - pushfd ; Get new EFLAGS - pop eax ; Store new EFLAGS in EAX - xor eax, ecx ; Can not toggle ID bit, - jnz @@1 ; Processor=80486 - mov eax,1 ; We dont have a Pentium - jmp @@Done -@@1: mov eax,0 ; We have Pentium or later -@@Done: leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; bool _CPU_checkClone(void) -;---------------------------------------------------------------------------- -; Checks if the i386 or i486 processor is a clone or genuine Intel. -;---------------------------------------------------------------------------- -cprocstart _CPU_checkClone - - enter_c - - mov ax,5555h ; Check to make sure this is a 32-bit processor - xor dx,dx - mov cx,2h - div cx ; Perform Division - clc - jnz @@NoClone - jmp @@Clone -@@NoClone: - stc -@@Clone: - pushfd - pop eax ; Get the flags - and eax,1 - xor eax,1 ; EAX=0 is probably Intel, EAX=1 is a Clone - - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; bool _CPU_haveCPUID(void) -;---------------------------------------------------------------------------- -; Determines if we have support for the CPUID instruction. -;---------------------------------------------------------------------------- -cprocstart _CPU_haveCPUID - - enter_c - -ifdef flatmodel - pushfd ; Get original EFLAGS - pop eax - mov ecx, eax - xor eax, 200000h ; Flip ID bit in EFLAGS - push eax ; Save new EFLAGS value on stack - popfd ; Replace current EFLAGS value - pushfd ; Get new EFLAGS - pop eax ; Store new EFLAGS in EAX - xor eax, ecx ; Can not toggle ID bit, - jnz @@1 ; Processor=80486 - mov eax,0 ; We dont have CPUID support - jmp @@Done -@@1: mov eax,1 ; We have CPUID support -else - mov eax,0 ; CPUID requires 32-bit pmode -endif -@@Done: leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; uint _CPU_checkCPUID(void) -;---------------------------------------------------------------------------- -; Determines the CPU type using the CPUID instruction. -;---------------------------------------------------------------------------- -cprocstart _CPU_checkCPUID - - enter_c - - xor eax, eax ; Set up for CPUID instruction - mCPU_ID ; Get and save vendor ID - cmp eax, 1 ; Make sure 1 is valid input for CPUID - jl @@Fail ; We dont have the CPUID instruction - xor eax,eax ; Assume vendor is unknown - -; Check for GenuineIntel processors - - LEA_L esi,intel_id - cmp [DWORD esi], ebx - jne @@NotIntel - cmp [DWORD esi+4], edx - jne @@NotIntel - cmp [DWORD esi+8], ecx - jne @@NotIntel - mov eax,CPU_Intel ; Flag that we have GenuineIntel - jmp @@FoundVendor - -; Check for CyrixInstead processors - -@@NotIntel: - LEA_L esi,cyrix_id - cmp [DWORD esi], ebx - jne @@NotCyrix - cmp [DWORD esi+4], edx - jne @@NotCyrix - cmp [DWORD esi+8], ecx - jne @@NotCyrix - mov eax,CPU_Cyrix ; Flag that we have CyrixInstead - jmp @@FoundVendor - -; Check for AuthenticAMD processors - -@@NotCyrix: - LEA_L esi,amd_id - cmp [DWORD esi], ebx - jne @@NotAMD - cmp [DWORD esi+4], edx - jne @@NotAMD - cmp [DWORD esi+8], ecx - jne @@NotAMD - mov eax,CPU_AMD ; Flag that we have AuthenticAMD - jmp @@FoundVendor - -; Check for CentaurHauls processors - -@@NotAMD: - LEA_L esi,idt_id - cmp [DWORD esi], ebx - jne @@NotIDT - cmp [DWORD esi+4], edx - jne @@NotIDT - cmp [DWORD esi+8], ecx - jne @@NotIDT - mov eax,CPU_IDT ; Flag that we have AuthenticIDT - jmp @@FoundVendor - -@@NotIDT: - -@@FoundVendor: - push eax - xor eax, eax - inc eax - mCPU_ID ; Get family/model/stepping/features - and eax, 0F00h - shr eax, 8 ; Isolate family - and eax, 0Fh - pop ecx - or eax,ecx ; Combine in the clone flag -@@Done: leave_c - ret - -@@Fail: xor eax,eax - jmp @@Done - -cprocend - -;---------------------------------------------------------------------------- -; uint _CPU_getCPUIDModel(void) -;---------------------------------------------------------------------------- -; Determines the CPU type using the CPUID instruction. -;---------------------------------------------------------------------------- -cprocstart _CPU_getCPUIDModel - - enter_c - - xor eax, eax ; Set up for CPUID instruction - mCPU_ID ; Get and save vendor ID - cmp eax, 1 ; Make sure 1 is valid input for CPUID - jl @@Fail ; We dont have the CPUID instruction - xor eax, eax - inc eax - mCPU_ID ; Get family/model/stepping/features - and eax, 0F0h - shr eax, 4 ; Isolate model -@@Done: leave_c - ret - -@@Fail: xor eax,eax - jmp @@Done - -cprocend - -;---------------------------------------------------------------------------- -; uint _CPU_getCPUIDStepping(void) -;---------------------------------------------------------------------------- -; Determines the CPU type using the CPUID instruction. -;---------------------------------------------------------------------------- -cprocstart _CPU_getCPUIDStepping - - enter_c - - xor eax, eax ; Set up for CPUID instruction - mCPU_ID ; Get and save vendor ID - cmp eax, 1 ; Make sure 1 is valid input for CPUID - jl @@Fail ; We dont have the CPUID instruction - xor eax, eax - inc eax - mCPU_ID ; Get family/model/stepping/features - and eax, 00Fh ; Isolate stepping -@@Done: leave_c - ret - -@@Fail: xor eax,eax - jmp @@Done - -cprocend - -;---------------------------------------------------------------------------- -; uint _CPU_getCPUIDFeatures(void) -;---------------------------------------------------------------------------- -; Determines the CPU type using the CPUID instruction. -;---------------------------------------------------------------------------- -cprocstart _CPU_getCPUIDFeatures - - enter_c - - xor eax, eax ; Set up for CPUID instruction - mCPU_ID ; Get and save vendor ID - cmp eax, 1 ; Make sure 1 is valid input for CPUID - jl @@Fail ; We dont have the CPUID instruction - xor eax, eax - inc eax - mCPU_ID ; Get family/model/stepping/features - mov eax, edx -@@Done: leave_c - ret - -@@Fail: xor eax,eax - jmp @@Done - -cprocend - -;---------------------------------------------------------------------------- -; uint _CPU_getCacheSize(void) -;---------------------------------------------------------------------------- -; Determines the CPU cache size for Intel processors -;---------------------------------------------------------------------------- -cprocstart _CPU_getCacheSize - - enter_c - xor eax, eax ; Set up for CPUID instruction - mCPU_ID ; Get and save vendor ID - cmp eax,2 ; Make sure 2 is valid input for CPUID - jl @@Fail ; We dont have the CPUID instruction - mov eax,2 - mCPU_ID ; Get cache descriptors - LEA_L esi,cache_id ; Get address of cache ID (-fPIC aware) - shr eax,8 - mov [esi+0],eax - mov [esi+3],ebx - mov [esi+7],ecx - mov [esi+11],edx - xor eax,eax - LEA_L esi,cache_id ; Get address of cache ID (-fPIC aware) - mov edi,15 -@@ScanLoop: - cmp [BYTE esi],41h - mov eax,128 - je @@Done - cmp [BYTE esi],42h - mov eax,256 - je @@Done - cmp [BYTE esi],43h - mov eax,512 - je @@Done - cmp [BYTE esi],44h - mov eax,1024 - je @@Done - cmp [BYTE esi],45h - mov eax,2048 - je @@Done - inc esi - dec edi - jnz @@ScanLoop - -@@Done: leave_c - ret - -@@Fail: xor eax,eax - jmp @@Done - -cprocend - -;---------------------------------------------------------------------------- -; uint _CPU_have3DNow(void) -;---------------------------------------------------------------------------- -; Determines the CPU type using the CPUID instruction. -;---------------------------------------------------------------------------- -cprocstart _CPU_have3DNow - - enter_c - - mov eax,80000000h ; Query for extended functions - mCPU_ID ; Get extended function limit - cmp eax,80000001h - jbe @@Fail ; Nope, we dont have function 800000001h - mov eax,80000001h ; Setup extended function 800000001h - mCPU_ID ; and get the information - test edx,80000000h ; Bit 31 is set if 3DNow! present - jz @@Fail ; Nope, we dont have 3DNow support - mov eax,1 ; Yep, we have 3DNow! support! -@@Done: leave_c - ret - -@@Fail: xor eax,eax - jmp @@Done - -cprocend - -;---------------------------------------------------------------------------- -; ulong _CPU_quickRDTSC(void) -;---------------------------------------------------------------------------- -; Reads the time stamp counter and returns the low order 32-bits -;---------------------------------------------------------------------------- -cprocstart _CPU_quickRDTSC - - mRDTSC - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _CPU_runBSFLoop(ulong interations) -;---------------------------------------------------------------------------- -; Runs a loop of BSF instructions for the specified number of iterations -;---------------------------------------------------------------------------- -cprocstart _CPU_runBSFLoop - - ARG iterations:ULONG - - push _bp - mov _bp,_sp - push _bx - - mov edx,[iterations] - mov eax,80000000h - mov ebx,edx - - ALIGN 4 - -@@loop: bsf ecx,eax - dec ebx - jnz @@loop - - pop _bx - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _CPU_readTimeStamp(CPU_largeInteger *time); -;---------------------------------------------------------------------------- -; Reads the time stamp counter and returns the 64-bit result. -;---------------------------------------------------------------------------- -cprocstart _CPU_readTimeStamp - - mRDTSC - mov ecx,[esp+4] ; Access directly without stack frame - mov [ecx],eax - mov [ecx+4],edx - ret - -cprocend - -;---------------------------------------------------------------------------- -; ulong _CPU_diffTime64(CPU_largeInteger *t1,CPU_largeInteger *t2,CPU_largeInteger *t) -;---------------------------------------------------------------------------- -; Computes the difference between two 64-bit numbers. -;---------------------------------------------------------------------------- -cprocstart _CPU_diffTime64 - - ARG t1:DPTR, t2:DPTR, t:DPTR - - enter_c - - mov ecx,[t2] - mov eax,[ecx] ; EAX := t2.low - mov ecx,[t1] - sub eax,[ecx] - mov edx,eax ; EDX := low difference - mov ecx,[t2] - mov eax,[ecx+4] ; ECX := t2.high - mov ecx,[t1] - sbb eax,[ecx+4] ; EAX := high difference - - mov ebx,[t] ; Store the result - mov [ebx],edx ; Store low part - mov [ebx+4],eax ; Store high part - mov eax,edx ; Return low part -ifndef flatmodel - shld edx,eax,16 ; Return in DX:AX -endif - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; ulong _CPU_calcMicroSec(CPU_largeInteger *count,ulong freq); -;---------------------------------------------------------------------------- -; Computes the value in microseconds for the elapsed time with maximum -; precision. The formula we use is: -; -; us = (((diff * 0x100000) / freq) * 1000000) / 0x100000) -; -; The power of two multiple before the first divide allows us to scale the -; 64-bit difference using simple shifts, and then the divide brings the -; final result into the range to fit into a 32-bit integer. -;---------------------------------------------------------------------------- -cprocstart _CPU_calcMicroSec - - ARG count:DPTR, freq:ULONG - - enter_c - - mov ecx,[count] - mov eax,[ecx] ; EAX := low part - mov edx,[ecx+4] ; EDX := high part - shld edx,eax,20 - shl eax,20 ; diff * 0x100000 - div [DWORD freq] ; (diff * 0x100000) / freq - mov ecx,1000000 - xor edx,edx - mul ecx ; ((diff * 0x100000) / freq) * 1000000) - shrd eax,edx,20 ; ((diff * 0x100000) / freq) * 1000000) / 0x100000 -ifndef flatmodel - shld edx,eax,16 ; Return in DX:AX -endif - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; ulong _CPU_mulDiv(ulong a,ulong b,ulong c); -;---------------------------------------------------------------------------- -; Computes the following with 64-bit integer precision: -; -; result = (a * b) / c -; -;---------------------------------------------------------------------------- -cprocstart _CPU_mulDiv - - ARG a:ULONG, b:ULONG, c:ULONG - - enter_c - mov eax,[a] - imul [ULONG b] - idiv [ULONG c] -ifndef flatmodel - shld edx,eax,16 ; Return in DX:AX -endif - leave_c - ret - -cprocend - -endcodeseg _cpuinfo - - END diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm deleted file mode 100644 index 2b6e1e8..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm +++ /dev/null @@ -1,246 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: 16/32 bit Ring 0 device driver -;* -;* Description: Assembler support routines for ISA DMA controller. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _dma ; Set up memory model - -begdataseg _dma ; Start of data segment - -cpublic _PM_DMADataStart - -; DMA register I/O addresses for channels 0-7 (except 4) - -DMAC_page db 087h,083h,081h,082h, -1,08Bh,089h,08Ah -DMAC_addr db 000h,002h,004h,006h, -1,0C4h,0C8h,0CCh -DMAC_cnt db 001h,003h,005h,007h, -1,0C6h,0CAh,0CEh -DMAC_mask db 00Ah,00Ah,00Ah,00Ah, -1,0D4h,0D4h,0D4h -DMAC_mode db 00Bh,00Bh,00Bh,00Bh, -1,0D6h,0D6h,0D6h -DMAC_FF db 00Ch,00Ch,00Ch,00Ch, -1,0D8h,0D8h,0D8h - -cpublic _PM_DMADataEnd - -enddataseg _dma - -begcodeseg _dma ; Start of code segment - -ifdef flatmodel - -cpublic _PM_DMACodeStart - -;---------------------------------------------------------------------------- -; void PM_DMACDisable(int channel); -;---------------------------------------------------------------------------- -; Masks DMA channel, inhibiting DMA transfers -;---------------------------------------------------------------------------- -cprocstart PM_DMACDisable - - ARG channel:UINT - - push ebp - mov ebp,esp - mov ecx,[channel] ; ECX indexes DMAC register tables - mov dh,0 ; DH = 0 for DMAC register port access - mov al,cl - and al,11b - or al,100b ; AL = (channel & 3) | "set mask bit" - mov dl,[DMAC_mask+ecx] - out dx,al - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_DMACEnable(int channel); -;---------------------------------------------------------------------------- -; Unmasks DMA channel, enabling DMA transfers -;---------------------------------------------------------------------------- -cprocstart PM_DMACEnable - - ARG channel:UINT - - push ebp - mov ebp,esp - mov ecx,[channel] ; ECX indexes DMAC register tables - mov dh,0 ; DH = 0 for DMAC register port access - mov al,cl - and al,11b ; AL = (channel & 3), "set mask bit"=0 - mov dl,[DMAC_mask+ecx] - out dx,al - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_DMACProgram(int channel,int mode,ulong bufferPhys,int count); -;---------------------------------------------------------------------------- -; Purpose: Program DMA controller to perform transfer from first 16MB -; based on previously selected mode and channel. DMA transfer may be enabled -; by subsequent call to PM_DMACEnable. -; -; Entry: channel - DMA channel in use (0-7) -; mode - Selected DMAMODE type for transfer -; buffer - 32-bit physical address of DMA buffer -; count - DMA byte count (1-65536 bytes) -;---------------------------------------------------------------------------- -cprocstart PM_DMACProgram - - ARG channel:UINT, mode:UINT, bufferPhys:ULONG, count:UINT - - enter_c - pushfd - cli ; Disable interrupts - -; Mask DMA channel to disable it - - mov ebx,[channel] ; EBX indexes DMAC register tables - mov dh,0 ; DH = 0 for DMAC register port access - mov al,bl - and al,11b - or al,100b ; AL = (channel & 3) | "set mask bit" - mov dl,[DMAC_mask+ebx] - out dx,al - -; Generate IOW to clear FF toggle state - - mov al,0 - mov dl,[DMAC_FF+ebx] - out dx,al - -; Compute buffer address to program - - mov eax,[bufferPhys] ; AX := DMA address offset - mov ecx,eax - shr ecx,16 ; CL := bufferPhys >> 16 (DMA page) - mov esi,[count] ; ESI = # of bytes to transfer - cmp ebx,4 ; 16-bit channel? - jb @@WriteDMAC ; No, program DMAC - shr eax,1 ; Yes, convert address and count - shr esi,1 ; to 16-bit, 128K/page format - -; Set the DMA address word (bits 0-15) - -@@WriteDMAC: - mov dl,[DMAC_addr+ebx] - out dx,al - mov al,ah - out dx,al - -; Set DMA transfer count - - mov eax,esi - dec eax ; ESI = # of bytes to transfer - 1 - mov dl,[DMAC_cnt+ebx] - out dx,al - mov al,ah - out dx,al - -; Set DMA page byte (bits 16-23) - - mov al,cl - mov dl,[DMAC_page+ebx] - out dx,al - -; Set the DMA channel mode - - mov al,bl - and al,11b - or al,[BYTE mode] ; EAX = (channel & 3) | mode - mov dl,[DMAC_mode+ebx] - out dx,al - - pop eax ; SMP safe interrupt state restore! - test eax,200h - jz @@1 - sti -@@1: leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; ulong PMAPI PM_DMACPosition(int channel); -;---------------------------------------------------------------------------- -; Returns the current position in a dma transfer. Interrupts should be -; disabled before calling this function. -;---------------------------------------------------------------------------- -cprocstart PM_DMACPosition - - ARG channel:UINT - - enter_c - mov ecx,[channel] ; ECX indexes DMAC register tables - mov dh,0 ; DH = 0 for DMAC register port access - -; Generate IOW to clear FF toggle state - - mov al,0 - mov dl,[DMAC_FF+ebx] - out dx,al - xor eax,eax - xor ecx,ecx - -; Now read the current position for the channel - -@@ReadLoop: - mov dl,[DMAC_cnt+ebx] - out dx,al - in al,dx - mov cl,al - in al,dx - mov ch,al ; ECX := first count read - in al,dx - mov ah,al - in al,dx - xchg al,ah ; EAX := second count read - sub ecx,eax - cmp ecx,40h - jg @@ReadLoop - cmp ebx,4 ; 16-bit channel? - jb @@Exit ; No, we are done - shl eax,1 ; Yes, adjust to byte address - -@@Exit: leave_c - ret - -cprocend - - -cpublic _PM_DMACodeEnd - -endif - -endcodeseg _dma - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm deleted file mode 100644 index fdec1b5..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm +++ /dev/null @@ -1,309 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: NASM or TASM Assembler -;* Environment: Intel 32 bit Protected Mode. -;* -;* Description: Code for 64-bit arhithmetic -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" - -header _int64 - -begcodeseg _int64 ; Start of code segment - -a_low EQU 04h ; Access a_low directly on stack -a_high EQU 08h ; Access a_high directly on stack -b_low EQU 0Ch ; Access b_low directly on stack -shift EQU 0Ch ; Access shift directly on stack -result_2 EQU 0Ch ; Access result directly on stack -b_high EQU 10h ; Access b_high directly on stack -result_3 EQU 10h ; Access result directly on stack -result_4 EQU 14h ; Access result directly on stack - -;---------------------------------------------------------------------------- -; void _PM_add64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result); -;---------------------------------------------------------------------------- -; Adds two 64-bit numbers. -;---------------------------------------------------------------------------- -cprocstart _PM_add64 - - mov eax,[esp+a_low] - add eax,[esp+b_low] - mov edx,[esp+a_high] - adc edx,[esp+b_high] - mov ecx,[esp+result_4] - mov [ecx],eax - mov [ecx+4],edx - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _PM_sub64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result); -;---------------------------------------------------------------------------- -; Subtracts two 64-bit numbers. -;---------------------------------------------------------------------------- -cprocstart _PM_sub64 - - mov eax,[esp+a_low] - sub eax,[esp+b_low] - mov edx,[esp+a_high] - sbb edx,[esp+b_high] - mov ecx,[esp+result_4] - mov [ecx],eax - mov [ecx+4],edx - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _PM_mul64(u32 a_high,u32 a_low,u32 b_high,u32 b_low,__u64 *result); -;---------------------------------------------------------------------------- -; Multiples two 64-bit numbers. -;---------------------------------------------------------------------------- -cprocstart _PM_mul64 - - mov eax,[esp+a_high] - mov ecx,[esp+b_high] - or ecx,eax - mov ecx,[esp+b_low] - jnz @@FullMultiply - mov eax,[esp+a_low] ; EDX:EAX = b.low * a.low - mul ecx - mov ecx,[esp+result_4] - mov [ecx],eax - mov [ecx+4],edx - ret - -@@FullMultiply: - push ebx - mul ecx ; EDX:EAX = a.high * b.low - mov ebx,eax - mov eax,[esp+a_low+4] - mul [DWORD esp+b_high+4] ; EDX:EAX = b.high * a.low - add ebx,eax - mov eax,[esp+a_low+4] - mul ecx ; EDX:EAX = a.low * b.low - add edx,ebx - pop ebx - mov ecx,[esp+result_4] - mov [ecx],eax - mov [ecx+4],edx - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _PM_div64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result); -;---------------------------------------------------------------------------- -; Divides two 64-bit numbers. -;---------------------------------------------------------------------------- -cprocstart _PM_div64 - - push edi - push esi - push ebx - xor edi,edi - mov eax,[esp+a_high+0Ch] - or eax,eax - jns @@ANotNeg - -; Dividend is negative, so negate it and save result for later - - inc edi - mov edx,[esp+a_low+0Ch] - neg eax - neg edx - sbb eax,0 - mov [esp+a_high+0Ch],eax - mov [esp+a_low+0Ch],edx - -@@ANotNeg: - mov eax,[esp+b_high+0Ch] - or eax,eax - jns @@BNotNeg - -; Divisor is negative, so negate it and save result for later - - inc edi - mov edx,[esp+b_low+0Ch] - neg eax - neg edx - sbb eax,0 - mov [esp+b_high+0Ch],eax - mov [esp+b_low+0Ch],edx - -@@BNotNeg: - or eax,eax - jnz @@BHighNotZero - -; b.high is zero, so handle this faster - - mov ecx,[esp+b_low+0Ch] - mov eax,[esp+a_high+0Ch] - xor edx,edx - div ecx - mov ebx,eax - mov eax,[esp+a_low+0Ch] - div ecx - mov edx,ebx - jmp @@BHighZero - -@@BHighNotZero: - mov ebx,eax - mov ecx,[esp+b_low+0Ch] - mov edx,[esp+a_high+0Ch] - mov eax,[esp+a_low+0Ch] - -; Shift values right until b.high becomes zero - -@@ShiftLoop: - shr ebx,1 - rcr ecx,1 - shr edx,1 - rcr eax,1 - or ebx,ebx - jnz @@ShiftLoop - -; Now complete the divide process - - div ecx - mov esi,eax - mul [DWORD esp+b_high+0Ch] - mov ecx,eax - mov eax,[esp+b_low+0Ch] - mul esi - add edx,ecx - jb @@8 - cmp edx,[esp+a_high+0Ch] - ja @@8 - jb @@9 - cmp eax,[esp+a_low+0Ch] - jbe @@9 -@@8: dec esi -@@9: xor edx,edx - mov eax,esi - -@@BHighZero: - dec edi - jnz @@Done - -; The result needs to be negated as either a or b was negative - - neg edx - neg eax - sbb edx,0 - -@@Done: pop ebx - pop esi - pop edi - mov ecx,[esp+result_4] - mov [ecx],eax - mov [ecx+4],edx - ret - -cprocend - -;---------------------------------------------------------------------------- -; __i64 _PM_shr64(u32 a_low,s32 a_high,s32 shift,__u64 *result); -;---------------------------------------------------------------------------- -; Shift a 64-bit number right -;---------------------------------------------------------------------------- -cprocstart _PM_shr64 - - mov eax,[esp+a_low] - mov edx,[esp+a_high] - mov cl,[esp+shift] - shrd edx,eax,cl - mov ecx,[esp+result_3] - mov [ecx],eax - mov [ecx+4],edx - ret - -cprocend - -;---------------------------------------------------------------------------- -; __i64 _PM_sar64(u32 a_low,s32 a_high,s32 shift,__u64 *result); -;---------------------------------------------------------------------------- -; Shift a 64-bit number right (signed) -;---------------------------------------------------------------------------- -cprocstart _PM_sar64 - - mov eax,[esp+a_low] - mov edx,[esp+a_high] - mov cl,[esp+shift] - sar edx,cl - rcr eax,cl - mov ecx,[esp+result_3] - mov [ecx],eax - mov [ecx+4],edx - ret - -cprocend - -;---------------------------------------------------------------------------- -; __i64 _PM_shl64(u32 a_low,s32 a_high,s32 shift,__u64 *result); -;---------------------------------------------------------------------------- -; Shift a 64-bit number left -;---------------------------------------------------------------------------- -cprocstart _PM_shl64 - - mov eax,[esp+a_low] - mov edx,[esp+a_high] - mov cl,[esp+shift] - shld edx,eax,cl - mov ecx,[esp+result_3] - mov [ecx],eax - mov [ecx+4],edx - ret - -cprocend - -;---------------------------------------------------------------------------- -; __i64 _PM_neg64(u32 a_low,s32 a_high,__u64 *result); -;---------------------------------------------------------------------------- -; Shift a 64-bit number left -;---------------------------------------------------------------------------- -cprocstart _PM_neg64 - - mov eax,[esp+a_low] - mov edx,[esp+a_high] - neg eax - neg edx - sbb eax,0 - mov ecx,[esp+result_2] - mov [ecx],eax - mov [ecx+4],edx - ret - -cprocend - - -endcodeseg _int64 - - END diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm deleted file mode 100644 index 0ff1ecf..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm +++ /dev/null @@ -1,230 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler -;* Environment: Intel x86, any OS -;* -;* Description: Assembly language support routines for reading analogue -;* joysticks. -;* -;**************************************************************************** - - ideal - -include "scitech.mac" ; Memory model macros - -ifdef flatmodel - -header _joy ; Set up memory model - -begcodeseg _joy ; Start of code segment - -;---------------------------------------------------------------------------- -; initTimer -;---------------------------------------------------------------------------- -; Sets up 8253 timer 2 (PC speaker) to start timing, but not produce output. -;---------------------------------------------------------------------------- -cprocstatic initTimer - -; Start timer 2 counting - - in al,61h - and al,0FDh ; Disable speaker output (just in case) - or al,1 - out 61h,al - -; Set the timer 2 count to 0 again to start the timing interval. - - mov al,10110100b ; set up to load initial (timer 2) - out 43h,al ; timer count - sub al,al - out 42h,al ; load count lsb - out 42h,al ; load count msb - ret - -cprocend - -;---------------------------------------------------------------------------- -; readTimer2 -;---------------------------------------------------------------------------- -; Reads the number of ticks from the 8253 timer chip using channel 2 (PC -; speaker). This is non-destructive and does not screw up other libraries. -;---------------------------------------------------------------------------- -cprocstatic readTimer - - xor al,al ; Latch timer 0 command - out 43h,al ; Latch timer - in al,42h ; least significant byte - mov ah,al - in al,42h ; most significant byte - xchg ah,al - and eax,0FFFFh - ret - -cprocend - -;---------------------------------------------------------------------------- -; exitTimer -;---------------------------------------------------------------------------- -; Stops the 8253 timer 2 (PC speaker) counting -;---------------------------------------------------------------------------- -cprocstatic exitTimer - -; Stop timer 2 from counting - - push eax - in al,61h - and al,0FEh - out 61h,al - -; Some programs have a problem if we change the control port; better change it -; to something they expect (mode 3 - square wave generator)... - mov al,0B6h - out 43h,al - - pop eax - ret - -cprocend - -;---------------------------------------------------------------------------- -; int _EVT_readJoyAxis(int jmask,int *axis); -;---------------------------------------------------------------------------- -; Function to poll the joystick to read the current axis positions. -;---------------------------------------------------------------------------- -cprocstart _EVT_readJoyAxis - - ARG jmask:UINT, axis:DPTR - - LOCAL firstTick:UINT, lastTick:UINT, totalTicks:UINT = LocalSize - - enter_c - - mov ebx,[jmask] - mov edi,[axis] - mov ecx,(1193180/100) - and ebx,01111b ; Mask out supported axes - mov dx,201h ; DX := joystick I/O port - call initTimer ; Start timer 2 counting - call readTimer ; Returns counter in EAX - mov [lastTick],eax - -@@WaitStable: - in al,dx - and al,bl ; Wait for the axes in question to be - jz @@Stable ; done reading... - call readTimer ; Returns counter in EAX - xchg eax,[lastTick] - cmp eax,[lastTick] - jb @@1 - sub eax,[lastTick] -@@1: add [totalTicks],eax - cmp [totalTicks],ecx ; Check for timeout - jae @@Stable - jmp @@WaitStable - -@@Stable: - mov al,0FFh - out dx,al ; Start joystick reading - call initTimer ; Start timer 2 counting - call readTimer ; Returns counter in EAX - mov [firstTick],eax ; Store initial count - mov [lastTick],eax - mov [DWORD totalTicks],0 - cli - -@@PollLoop: - in al,dx ; Read Joystick port - not al - and al,bl ; Mask off channels we don't want to read - jnz @@AxisFlipped ; See if any of the channels flipped - call readTimer ; Returns counter in EAX - xchg eax,[lastTick] - cmp eax,[lastTick] - jb @@2 - sub eax,[lastTick] -@@2: add [totalTicks],eax - cmp [totalTicks],ecx ; Check for timeout - jae @@TimedOut - jmp @@PollLoop - -@@AxisFlipped: - xor esi,esi - mov ah,1 - test al,ah - jnz @@StoreCount ; Joystick 1, X axis flipped - add esi,4 - mov ah,2 - test al,ah - jnz @@StoreCount ; Joystick 1, Y axis flipped - add esi,4 - mov ah,4 - test al,ah - jnz @@StoreCount ; Joystick 2, X axis flipped - add esi,4 ; Joystick 2, Y axis flipped - mov ah,8 - -@@StoreCount: - or bh,ah ; Indicate this axis is active - xor bl,ah ; Unmark the channels that just tripped - call readTimer ; Returns counter in EAX - xchg eax,[lastTick] - cmp eax,[lastTick] - jb @@3 - sub eax,[lastTick] -@@3: add [totalTicks],eax - mov eax,[totalTicks] - mov [edi+esi],eax ; Record the time this channel flipped - cmp bl,0 ; If there are more channels to read, - jne @@PollLoop ; keep looping - -@@TimedOut: - sti - call exitTimer ; Stop timer 2 counting - movzx eax,bh ; Return the mask of working axes - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; int _EVT_readJoyButtons(void); -;---------------------------------------------------------------------------- -; Function to poll the current joystick buttons -;---------------------------------------------------------------------------- -cprocstart _EVT_readJoyButtons - - mov dx,0201h - in al,dx - shr al,4 - not al - and eax,0Fh - ret - -cprocend - -endcodeseg _joy - -endif - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm deleted file mode 100644 index 1e0a696..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm +++ /dev/null @@ -1,272 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: 16/32 bit Ring 0 device driver -;* -;* Description: Assembler support routines for the Memory Type Range Register -;* (MTRR) module. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _mtrr ; Set up memory model - -begdataseg _mtrr - -ifdef DOS4GW - cextern _PM_haveCauseWay,UINT -endif - -enddataseg _mtrr - -begcodeseg _mtrr ; Start of code segment - -P586 - -;---------------------------------------------------------------------------- -; ibool _MTRR_isRing0(void); -;---------------------------------------------------------------------------- -; Checks to see if we are running at ring 0. This check is only relevant -; for 32-bit DOS4GW and compatible programs. If we are not running under -; DOS4GW, then we simply assume we are a ring 0 device driver. -;---------------------------------------------------------------------------- -cprocnear _MTRR_isRing0 - -; Are we running under CauseWay? - -ifdef DOS4GW - enter_c - mov ax,cs - and eax,3 - xor eax,3 - jnz @@Exit - -; CauseWay runs the apps at ring 3, but implements support for specific -; ring 0 instructions that we need to get stuff done under real DOS. - - mov eax,1 - cmp [UINT _PM_haveCauseWay],0 - jnz @@Exit -@@Fail: xor eax,eax -@@Exit: leave_c - ret -else -ifdef __SMX32__ - mov eax,1 ; SMX is ring 0! - ret -else -ifdef __VXD__ - mov eax,1 ; VxD is ring 0! - ret -else -ifdef __NT_DRIVER__ - mov eax,1 ; NT/W2K is ring 0! - ret -else -else - xor eax,eax ; Assume ring 3 for 32-bit DOS - ret -endif -endif -endif -endif - -cprocend - -;---------------------------------------------------------------------------- -; ulong _MTRR_disableInt(void); -;---------------------------------------------------------------------------- -; Return processor interrupt status and disable interrupts. -;---------------------------------------------------------------------------- -cprocstart _MTRR_disableInt - - pushfd ; Put flag word on stack - cli ; Disable interrupts! - pop eax ; deposit flag word in return register - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _MTRR_restoreInt(ulong ps); -;---------------------------------------------------------------------------- -; Restore processor interrupt status. -;---------------------------------------------------------------------------- -cprocstart _MTRR_restoreInt - - ARG ps:ULONG - - push ebp - mov ebp,esp ; Set up stack frame - mov ecx,[ps] - test ecx,200h ; SMP safe interrupt flag restore! - jz @@1 - sti -@@1: pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; ulong _MTRR_saveCR4(void); -;---------------------------------------------------------------------------- -; Save the value of CR4 and clear the Page Global Enable (bit 7). We also -; disable and flush the caches. -;---------------------------------------------------------------------------- -cprocstart _MTRR_saveCR4 - - enter_c - -; Save value of CR4 and clear Page Global Enable (bit 7) - - mov ebx,cr4 - mov eax,ebx - and al,7Fh - mov cr4,eax - -; Disable and flush caches - - mov eax,cr0 - or eax,40000000h - wbinvd - mov cr0,eax - wbinvd - -; Return value from CR4 - - mov eax,ebx - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _MTRR_restoreCR4(ulong cr4Val) -;---------------------------------------------------------------------------- -; Save the value of CR4 and clear the Page Global Enable (bit 7). We also -; disable and flush the caches. -;---------------------------------------------------------------------------- -cprocstart _MTRR_restoreCR4 - - ARG cr4Val:ULONG - - enter_c - -; Enable caches - - mov eax,cr0 - and eax,0BFFFFFFFh - mov cr0,eax - mov eax,[cr4Val] - mov cr4,eax - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; uchar _MTRR_getCx86(uchar reg); -;---------------------------------------------------------------------------- -; Read a Cyrix CPU indexed register -;---------------------------------------------------------------------------- -cprocstart _MTRR_getCx86 - - ARG reg:UCHAR - - enter_c - mov al,[reg] - out 22h,al - in al,23h - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; uchar _MTRR_setCx86(uchar reg,uchar val); -;---------------------------------------------------------------------------- -; Write a Cyrix CPU indexed register -;---------------------------------------------------------------------------- -cprocstart _MTRR_setCx86 - - ARG reg:UCHAR, val:UCHAR - - enter_c - mov al,[reg] - out 22h,al - mov al,[val] - out 23h,al - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _MTRR_readMSR(uong reg, ulong FAR *eax, ulong FAR *edx); -;---------------------------------------------------------------------------- -; Writes the specific Machine Status Register used on the newer Intel -; Pentium Pro and Pentium II motherboards. -;---------------------------------------------------------------------------- -cprocnear _MTRR_readMSR - - ARG reg:ULONG, v_eax:DPTR, v_edx:DPTR - - enter_c - mov ecx,[reg] - rdmsr - mov ebx,[v_eax] - mov [ebx],eax - mov ebx,[v_edx] - mov [ebx],edx - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _MTRR_writeMSR(uong reg, ulong eax, ulong edx); -;---------------------------------------------------------------------------- -; Writes the specific Machine Status Register used on the newer Intel -; Pentium Pro and Pentium II motherboards. -;---------------------------------------------------------------------------- -cprocnear _MTRR_writeMSR - - ARG reg:ULONG, v_eax:ULONG, v_edx:ULONG - - enter_c - mov ecx,[reg] - mov eax,[v_eax] - mov edx,[v_edx] - wrmsr - leave_c - ret - -cprocend - -endcodeseg _mtrr - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm deleted file mode 100644 index 5b8dbcc..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm +++ /dev/null @@ -1,358 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: Any -;* -;* Description: Helper assembler functions for PCI access module. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _pcilib - -begcodeseg _pcilib - -ifdef flatmodel - -;---------------------------------------------------------------------------- -; uchar _ASMAPI _BIOS32_service( -; ulong service, -; ulong func, -; ulong *physBase, -; ulong *length, -; ulong *serviceOffset, -; PCIBIOS_entry entry); -;---------------------------------------------------------------------------- -; Call the BIOS32 services directory -;---------------------------------------------------------------------------- -cprocstart _BIOS32_service - - ARG service:ULONG, func:ULONG, physBase:DPTR, len:DPTR, off:DPTR, entry:QWORD - - enter_c - mov eax,[service] - mov ebx,[func] -ifdef USE_NASM - call far dword [entry] -else - call [FWORD entry] -endif - mov esi,[physBase] - mov [esi],ebx - mov esi,[len] - mov [esi],ecx - mov esi,[off] - mov [esi],edx - leave_c - ret - -cprocend - -endif - -;---------------------------------------------------------------------------- -; ushort _ASMAPI _PCIBIOS_isPresent(ulong i_eax,ulong *o_edx,ushort *oeax, -; uchar *o_cl,PCIBIOS_entry entry) -;---------------------------------------------------------------------------- -; Call the PCI BIOS to determine if it is present. -;---------------------------------------------------------------------------- -cprocstart _PCIBIOS_isPresent - - ARG i_eax:ULONG, o_edx:DPTR, oeax:DPTR, o_cl:DPTR, entry:QWORD - - enter_c - mov eax,[i_eax] -ifdef flatmodel -ifdef USE_NASM - call far dword [entry] -else - call [FWORD entry] -endif -else - int 1Ah -endif - _les _si,[o_edx] - mov [_ES _si],edx - _les _si,[oeax] - mov [_ES _si],ax - _les _si,[o_cl] - mov [_ES _si],cl - mov ax,bx - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; ulong _PCIBIOS_service(ulong r_eax,ulong r_ebx,ulong r_edi,ulong r_ecx, -; PCIBIOS_entry entry) -;---------------------------------------------------------------------------- -; Call the PCI BIOS services, either via the 32-bit protected mode entry -; point or via the Int 1Ah 16-bit interrupt. -;---------------------------------------------------------------------------- -cprocstart _PCIBIOS_service - - ARG r_eax:ULONG, r_ebx:ULONG, r_edi:ULONG, r_ecx:ULONG, entry:QWORD - - enter_c - mov eax,[r_eax] - mov ebx,[r_ebx] - mov edi,[r_edi] - mov ecx,[r_ecx] -ifdef flatmodel -ifdef USE_NASM - call far dword [entry] -else - call [FWORD entry] -endif -else - int 1Ah -endif - mov eax,ecx -ifndef flatmodel - shld edx,eax,16 ; Return result in DX:AX -endif - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; int _PCIBIOS_getRouting(PCIRoutingOptionsBuffer *buf,PCIBIOS_entry entry); -;---------------------------------------------------------------------------- -; Get the routing options for PCI devices -;---------------------------------------------------------------------------- -cprocstart _PCIBIOS_getRouting - - ARG buf:DPTR, entry:QWORD - - enter_c - mov eax,0B10Eh - mov bx,0 - _les _di,[buf] -ifdef flatmodel -ifdef USE_NASM - call far dword [entry] -else - call [FWORD entry] -endif -else - int 1Ah -endif - movzx eax,ah - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; ibool _PCIBIOS_setIRQ(int busDev,int intPin,int IRQ,PCIBIOS_entry entry); -;---------------------------------------------------------------------------- -; Change the IRQ routing for the PCI device -;---------------------------------------------------------------------------- -cprocstart _PCIBIOS_setIRQ - - ARG busDev:UINT, intPin:UINT, IRQ:UINT, entry:QWORD - - enter_c - mov eax,0B10Fh - mov bx,[USHORT busDev] - mov cl,[BYTE intPin] - mov ch,[BYTE IRQ] -ifdef flatmodel -ifdef USE_NASM - call far dword [entry] -else - call [FWORD entry] -endif -else - int 1Ah -endif - mov eax,1 - jnc @@1 - xor eax,eax ; Function failed! -@@1: leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; ulong _PCIBIOS_specialCycle(int bus,ulong data,PCIBIOS_entry entry); -;---------------------------------------------------------------------------- -; Generate a special cycle via the PCI BIOS. -;---------------------------------------------------------------------------- -cprocstart _PCIBIOS_specialCycle - - ARG bus:UINT, data:ULONG, entry:QWORD - - enter_c - mov eax,0B106h - mov bh,[BYTE bus] - mov ecx,[data] -ifdef flatmodel -ifdef USE_NASM - call far dword [entry] -else - call [FWORD entry] -endif -else - int 1Ah -endif - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; ushort _PCI_getCS(void) -;---------------------------------------------------------------------------- -cprocstart _PCI_getCS - - mov ax,cs - ret - -cprocend - -;---------------------------------------------------------------------------- -; int PM_inpb(int port) -;---------------------------------------------------------------------------- -; Reads a byte from the specified port -;---------------------------------------------------------------------------- -cprocstart PM_inpb - - ARG port:UINT - - push _bp - mov _bp,_sp - xor _ax,_ax - mov _dx,[port] - in al,dx - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; int PM_inpw(int port) -;---------------------------------------------------------------------------- -; Reads a word from the specified port -;---------------------------------------------------------------------------- -cprocstart PM_inpw - - ARG port:UINT - - push _bp - mov _bp,_sp - xor _ax,_ax - mov _dx,[port] - in ax,dx - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; ulong PM_inpd(int port) -;---------------------------------------------------------------------------- -; Reads a word from the specified port -;---------------------------------------------------------------------------- -cprocstart PM_inpd - - ARG port:UINT - - push _bp - mov _bp,_sp - mov _dx,[port] - in eax,dx -ifndef flatmodel - shld edx,eax,16 ; DX:AX = result -endif - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_outpb(int port,int value) -;---------------------------------------------------------------------------- -; Write a byte to the specified port. -;---------------------------------------------------------------------------- -cprocstart PM_outpb - - ARG port:UINT, value:UINT - - push _bp - mov _bp,_sp - mov _dx,[port] - mov _ax,[value] - out dx,al - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_outpw(int port,int value) -;---------------------------------------------------------------------------- -; Write a word to the specified port. -;---------------------------------------------------------------------------- -cprocstart PM_outpw - - ARG port:UINT, value:UINT - - push _bp - mov _bp,_sp - mov _dx,[port] - mov _ax,[value] - out dx,ax - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_outpd(int port,ulong value) -;---------------------------------------------------------------------------- -; Write a word to the specified port. -;---------------------------------------------------------------------------- -cprocstart PM_outpd - - ARG port:UINT, value:ULONG - - push _bp - mov _bp,_sp - mov _dx,[port] - mov eax,[value] - out dx,eax - pop _bp - ret - -cprocend - -endcodeseg _pcilib - - END diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/agp.c b/board/MAI/bios_emulator/scitech/src/pm/common/agp.c deleted file mode 100644 index d53bc88..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/agp.c +++ /dev/null @@ -1,189 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Ring 0 device driver -* -* Description: Generic module to implement AGP support functions using the -* SciTech Nucleus AGP support drivers. If the OS provides -* native AGP support, this module should *NOT* be used. Instead -* wrappers should be placed around the OS support functions -* to implement this functionality. -* -****************************************************************************/ - -#include "pmapi.h" -#ifndef REALMODE -#include "nucleus/agp.h" - -/*--------------------------- Global variables ----------------------------*/ - -static AGP_devCtx *agp; -static AGP_driverFuncs driver; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -RETURNS: -Size of AGP aperture in MB on success, 0 on failure. - -REMARKS: -This function initialises the AGP driver in the system and returns the -size of the available AGP aperture in megabytes. -****************************************************************************/ -ulong PMAPI PM_agpInit(void) -{ - if ((agp = AGP_loadDriver(0)) == NULL) - return 0; - driver.dwSize = sizeof(driver); - if (!agp->QueryFunctions(AGP_GET_DRIVERFUNCS,&driver)) - return 0; - switch (driver.GetApertureSize()) { - case agpSize4MB: return 4; - case agpSize8MB: return 8; - case agpSize16MB: return 16; - case agpSize32MB: return 32; - case agpSize64MB: return 64; - case agpSize128MB: return 128; - case agpSize256MB: return 256; - case agpSize512MB: return 512; - case agpSize1GB: return 1024; - case agpSize2GB: return 2048; - } - return 0; -} - -/**************************************************************************** -REMARKS: -This function closes down the loaded AGP driver. -****************************************************************************/ -void PMAPI PM_agpExit(void) -{ - AGP_unloadDriver(agp); -} - -/**************************************************************************** -PARAMETERS: -numPages - Number of memory pages that should be reserved -type - Type of memory to allocate -physContext - Returns the physical context handle for the mapping -physAddr - Returns the physical address for the mapping - -RETURNS: -True on success, false on failure. - -REMARKS: -This function reserves a range of physical memory addresses on the system -bus which the AGP controller will respond to. If this function succeeds, -the AGP controller can respond to the reserved physical address range on -the bus. However you must first call AGP_commitPhysical to cause this memory -to actually be committed for use before it can be accessed. -****************************************************************************/ -ibool PMAPI PM_agpReservePhysical( - ulong numPages, - int type, - void **physContext, - PM_physAddr *physAddr) -{ - switch (type) { - case PM_agpUncached: - type = agpUncached; - break; - case PM_agpWriteCombine: - type = agpWriteCombine; - break; - case PM_agpIntelDCACHE: - type = agpIntelDCACHE; - break; - default: - return false; - } - return driver.ReservePhysical(numPages,type,physContext,physAddr) == nOK; -} - -/**************************************************************************** -PARAMETERS: -physContext - Physical AGP context to release - -RETURNS: -True on success, false on failure. - -REMARKS: -This function releases a range of physical memory addresses on the system -bus which the AGP controller will respond to. All committed memory for -the physical address range covered by the context will be released. -****************************************************************************/ -ibool PMAPI PM_agpReleasePhysical( - void *physContext) -{ - return driver.ReleasePhysical(physContext) == nOK; -} - -/**************************************************************************** -PARAMETERS: -physContext - Physical AGP context to commit memory for -numPages - Number of pages to be committed -startOffset - Offset in pages into the reserved physical context -physAddr - Returns the physical address of the committed memory - -RETURNS: -True on success, false on failure. - -REMARKS: -This function commits into the specified physical context that was previously -reserved by a call to ReservePhysical. You can use the startOffset and -numPages parameters to only commit portions of the reserved memory range at -a time. -****************************************************************************/ -ibool PMAPI PM_agpCommitPhysical( - void *physContext, - ulong numPages, - ulong startOffset, - PM_physAddr *physAddr) -{ - return driver.CommitPhysical(physContext,numPages,startOffset,physAddr) == nOK; -} - -/**************************************************************************** -PARAMETERS: -physContext - Physical AGP context to free memory for -numPages - Number of pages to be freed -startOffset - Offset in pages into the reserved physical context - -RETURNS: -True on success, false on failure. - -REMARKS: -This function frees memory previously committed by the CommitPhysical -function. Note that you can free a portion of a memory range that was -previously committed if you wish. -****************************************************************************/ -ibool PMAPI PM_agpFreePhysical( - void *physContext, - ulong numPages, - ulong startOffset) -{ - return driver.FreePhysical(physContext,numPages,startOffset) == nOK; -} - -#endif /* !REALMODE */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c b/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c deleted file mode 100644 index 36867bd..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c +++ /dev/null @@ -1,449 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Direct keyboard event handling module. This module contains -* code to process raw scan code information, convert it to -* virtual scan codes and do code page translation to ASCII -* for different international keyboard layouts. -* -****************************************************************************/ - -/*---------------------------- Implementation -----------------------------*/ - -/**************************************************************************** -PARAMETERS: -scanCode - Keyboard scan code to translate -table - Code page table to search -count - Number of entries in the code page table - -REMARKS: -This function translates the scan codes from keyboard scan codes to ASCII -codes using a binary search on the code page table. -****************************************************************************/ -static uchar translateScan( - uchar scanCode, - codepage_entry_t *table, - int count) -{ - codepage_entry_t *test; - int n,pivot,val; - - for (n = count; n > 0; ) { - pivot = n >> 1; - test = table + pivot; - val = scanCode - test->scanCode; - if (val < 0) - n = pivot; - else if (val == 0) - return test->asciiCode; - else { - table = test + 1; - n -= pivot + 1; - } - } - return 0; -} - -/**************************************************************************** -REMARKS: -This macro/function is used to converts the scan codes reported by the -keyboard to our event libraries normalised format. We only have one scan -code for the 'A' key, and use shift modifiers to determine if it is a -Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, -but the OS gives us 'cooked' scan codes, we have to translate them back -to the raw format. -{secret} -****************************************************************************/ -void _EVT_maskKeyCode( - event_t *evt) -{ - int ascii,scan = EVT_scanCode(evt->message); - - evt->message &= ~0xFF; - if (evt->modifiers & EVT_NUMLOCK) { - if ((ascii = translateScan(scan,EVT.codePage->numPad,EVT.codePage->numPadLen)) != 0) { - evt->message |= ascii; - return; - } - } - if (evt->modifiers & EVT_CTRLSTATE) { - evt->message |= translateScan(scan,EVT.codePage->ctrl,EVT.codePage->ctrlLen); - return; - } - if (evt->modifiers & EVT_CAPSLOCK) { - if (evt->modifiers & EVT_SHIFTKEY) { - if ((ascii = translateScan(scan,EVT.codePage->shiftCaps,EVT.codePage->shiftCapsLen)) != 0) { - evt->message |= ascii; - return; - } - } - else { - if ((ascii = translateScan(scan,EVT.codePage->caps,EVT.codePage->capsLen)) != 0) { - evt->message |= ascii; - return; - } - } - } - if (evt->modifiers & EVT_SHIFTKEY) { - if ((ascii = translateScan(scan,EVT.codePage->shift,EVT.codePage->shiftLen)) != 0) { - evt->message |= ascii; - return; - } - } - evt->message |= translateScan(scan,EVT.codePage->normal,EVT.codePage->normalLen); -} - -/**************************************************************************** -REMARKS: -Returns true if the key with the specified scan code is being held down. -****************************************************************************/ -static ibool _EVT_isKeyDown( - uchar scanCode) -{ - if (scanCode > 0x7F) - return false; - else - return EVT.keyTable[scanCode] != 0; -} - -/**************************************************************************** -PARAMETERS: -what - Event code -message - Event message (ASCII code and scan code) - -REMARKS: -Adds a new keyboard event to the event queue. This routine is called from -within the keyboard interrupt subroutine! - -NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, - and we leave them OFF the entire time. -****************************************************************************/ -static void addKeyEvent( - uint what, - uint message) -{ - event_t evt; - - if (EVT.count < EVENTQSIZE) { - /* Save information in event record */ - evt.when = _EVT_getTicks(); - evt.what = what; - evt.message = message | 0x10000UL; - evt.where_x = 0; - evt.where_y = 0; - evt.relative_x = 0; - evt.relative_y = 0; - evt.modifiers = EVT.keyModifiers; - if (evt.what == EVT_KEYREPEAT) { - if (EVT.oldKey != -1) - EVT.evtq[EVT.oldKey].message += 0x10000UL; - else { - EVT.oldKey = EVT.freeHead; - addEvent(&evt); /* Add to tail of event queue */ - } - } - else { -#ifdef __QNX__ - _EVT_maskKeyCode(&evt); -#endif - addEvent(&evt); /* Add to tail of event queue */ - } - EVT.oldMove = -1; - } -} - -/**************************************************************************** -REMARKS: -This function waits for the keyboard controller to set the ready-for-write -bit. -****************************************************************************/ -static int kbWaitForWriteReady(void) -{ - int timeout = 8192; - while ((timeout > 0) && (PM_inpb(0x64) & 0x02)) - timeout--; - return (timeout > 0); -} - -/**************************************************************************** -REMARKS: -This function waits for the keyboard controller to set the ready-for-read -bit. -****************************************************************************/ -static int kbWaitForReadReady(void) -{ - int timeout = 8192; - while ((timeout > 0) && (!(PM_inpb(0x64) & 0x01))) - timeout--; - return (timeout > 0); -} - -/**************************************************************************** -PARAMETERS: -data - Data to send to the keyboard - -REMARKS: -This function sends a data byte to the keyboard controller. -****************************************************************************/ -static int kbSendData( - uchar data) -{ - int resends = 4; - int timeout, temp; - - do { - if (!kbWaitForWriteReady()) - return 0; - PM_outpb(0x60,data); - timeout = 8192; - while (--timeout > 0) { - if (!kbWaitForReadReady()) - return 0; - temp = PM_inpb(0x60); - if (temp == 0xFA) - return 1; - if (temp == 0xFE) - break; - } - } while ((resends-- > 0) && (timeout > 0)); - return 0; -} - -/**************************************************************************** -PARAMETERS: -modifiers - Keyboard modifier flags - -REMARKS: -This function re-programs the LED's on the keyboard to the values stored -in the passed in modifier flags. If the 'allowLEDS' flag is false, this -function does nothing. -****************************************************************************/ -static void setLEDS( - uint modifiers) -{ - if (EVT.allowLEDS) { - if (!kbSendData(0xED) || !kbSendData((modifiers>>9) & 7)) { - kbSendData(0xF4); - } - } -} - -/**************************************************************************** -REMARKS: -Function to process raw scan codes read from the keyboard controller. - -NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, - and we leave them OFF the entire time. -{secret} -****************************************************************************/ -void processRawScanCode( - int scan) -{ - static int pauseLoop = 0; - static int extended = 0; - int what; - - if (pauseLoop) { - /* Skip scan codes until the pause key sequence has been read */ - pauseLoop--; - } - else if (scan == 0xE0) { - /* This signals the start of an extended scan code sequence */ - extended = 1; - } - else if (scan == 0xE1) { - /* The Pause key sends a strange scan code sequence, which is: - * - * E1 1D 52 E1 9D D2 - * - * However there is never any release code nor any auto-repeat for - * this key. For this reason we simply ignore the key and skip the - * next 5 scan codes read from the keyboard. - */ - pauseLoop = 5; - } - else { - /* Process the scan code normally (it may be an extended code - * however!). Bit 7 means key was released, and bits 0-6 are the - * scan code. - */ - what = (scan & 0x80) ? EVT_KEYUP : EVT_KEYDOWN; - scan &= 0x7F; - if (extended) { - extended = 0; - if (scan == 0x2A || scan == 0x36) { - /* Ignore these extended scan code sequences. These are - * used by the keyboard controller to wrap around certain - * key sequences for the keypad (and when NUMLOCK is down - * internally). - */ - return; - } - - /* Convert extended codes for key sequences that we map to - * virtual scan codes so the user can detect them in their - * code. - */ - switch (scan) { - case KB_leftCtrl: scan = KB_rightCtrl; break; - case KB_leftAlt: scan = KB_rightAlt; break; - case KB_divide: scan = KB_padDivide; break; - case KB_enter: scan = KB_padEnter; break; - case KB_padTimes: scan = KB_sysReq; break; - } - } - else { - /* Convert regular scan codes for key sequences that we map to - * virtual scan codes so the user can detect them in their - * code. - */ - switch (scan) { - case KB_left: scan = KB_padLeft; break; - case KB_right: scan = KB_padRight; break; - case KB_up: scan = KB_padUp; break; - case KB_down: scan = KB_padDown; break; - case KB_insert: scan = KB_padInsert; break; - case KB_delete: scan = KB_padDelete; break; - case KB_home: scan = KB_padHome; break; - case KB_end: scan = KB_padEnd; break; - case KB_pageUp: scan = KB_padPageUp; break; - case KB_pageDown: scan = KB_padPageDown; break; - } - } - - /* Determine if the key is an UP, DOWN or REPEAT and maintain the - * up/down status of all keys in our global key array. - */ - if (what == EVT_KEYDOWN) { - if (EVT.keyTable[scan]) - what = EVT_KEYREPEAT; - else - EVT.keyTable[scan] = scan; - } - else { - EVT.keyTable[scan] = 0; - } - - /* Handle shift key modifiers */ - if (what != EVT_KEYREPEAT) { - switch (scan) { - case KB_capsLock: - if (what == EVT_KEYDOWN) - EVT.keyModifiers ^= EVT_CAPSLOCK; - setLEDS(EVT.keyModifiers); - break; - case KB_numLock: - if (what == EVT_KEYDOWN) - EVT.keyModifiers ^= EVT_NUMLOCK; - setLEDS(EVT.keyModifiers); - break; - case KB_scrollLock: - if (what == EVT_KEYDOWN) - EVT.keyModifiers ^= EVT_SCROLLLOCK; - setLEDS(EVT.keyModifiers); - break; - case KB_leftShift: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_LEFTSHIFT; - else - EVT.keyModifiers |= EVT_LEFTSHIFT; - break; - case KB_rightShift: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_RIGHTSHIFT; - else - EVT.keyModifiers |= EVT_RIGHTSHIFT; - break; - case KB_leftCtrl: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_LEFTCTRL; - else - EVT.keyModifiers |= EVT_LEFTCTRL; - break; - case KB_rightCtrl: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_RIGHTCTRL; - else - EVT.keyModifiers |= EVT_RIGHTCTRL; - break; - case KB_leftAlt: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_LEFTALT; - else - EVT.keyModifiers |= EVT_LEFTALT; - break; - case KB_rightAlt: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_RIGHTALT; - else - EVT.keyModifiers |= EVT_RIGHTALT; - break; -#ifdef SUPPORT_CTRL_ALT_DEL - case KB_delete: - if ((EVT.keyModifiers & EVT_CTRLSTATE) && (EVT.keyModifiers & EVT_ALTSTATE)) - Reboot(); - break; -#endif - } - } - - /* Add the untranslated key code to the event queue. All - * translation to ASCII from the key codes occurs when the key - * is extracted from the queue, saving time in the low level - * interrupt handler. - */ - addKeyEvent(what,scan << 8); - } -} - -/**************************************************************************** -DESCRIPTION: -Enables/disables the update of the keyboard LED status indicators. - -HEADER: -event.h - -PARAMETERS: -enable - True to enable, false to disable - -REMARKS: -Enables the update of the keyboard LED status indicators. Sometimes it may -be convenient in the application to turn off the updating of the LED -status indicators (such as if a game is using the CAPSLOCK key for some -function). Passing in a value of FALSE to this function will turn off all -the LEDS, and stop updating them when the internal status changes (note -however that internally we still keep track of the toggle key status!). -****************************************************************************/ -void EVTAPI EVT_allowLEDS( - ibool enable) -{ - EVT.allowLEDS = true; - if (enable) - setLEDS(EVT.keyModifiers); - else - setLEDS(0); - EVT.allowLEDS = enable; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c b/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c deleted file mode 100644 index 83ef221..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c +++ /dev/null @@ -1,205 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Module for implementing the PM library overrideable memory -* allocator functions. -* -****************************************************************************/ - -#include "pmapi.h" - -/*--------------------------- Global variables ----------------------------*/ - -void * (*__PM_malloc)(size_t size) = malloc; -void * (*__PM_calloc)(size_t nelem,size_t size) = calloc; -void * (*__PM_realloc)(void *ptr,size_t size) = realloc; -void (*__PM_free)(void *p) = free; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -DESCRIPTION: -Use local memory allocation routines. - -HEADER: -pmapi.h - -PARAMETERS: -malloc - Pointer to new malloc routine to use -calloc - Pointer to new caalloc routine to use -realloc - Pointer to new realloc routine to use -free - Pointer to new free routine to use - -REMARKS: -Tells the PM library to use a set of user specified memory allocation -routines instead of using the normal malloc/calloc/realloc/free standard -C library functions. This is useful if you wish to use a third party -debugging malloc library or perhaps a set of faster memory allocation -functions with the PM library, or any apps that use the PM library (such as -the MGL). Once you have registered your memory allocation routines, all -calls to PM_malloc, PM_calloc, PM_realloc and PM_free will be revectored to -your local memory allocation routines. - -This is also useful if you need to keep track of just how much physical -memory your program has been using. You can use the PM_availableMemory -function to find out how much physical memory is available when the program -starts, and then you can use your own local memory allocation routines to -keep track of how much memory has been used and freed. - -NOTE: This function should be called right at the start of your application, - before you initialise any other components or libraries. - -NOTE: Code compiled into Binary Portable DLL's and Drivers automatically - end up calling these functions via the BPD C runtime library. - -SEE ALSO: -PM_malloc, PM_calloc, PM_realloc, PM_free, PM_availableMemory -****************************************************************************/ -void PMAPI PM_useLocalMalloc( - void * (*malloc)(size_t size), - void * (*calloc)(size_t nelem,size_t size), - void * (*realloc)(void *ptr,size_t size), - void (*free)(void *p)) -{ - __PM_malloc = malloc; - __PM_calloc = calloc; - __PM_realloc = realloc; - __PM_free = free; -} - -/**************************************************************************** -DESCRIPTION: -Allocate a block of memory. - -HEADER: -pmapi.h - -PARAMETERS: -size - Size of block to allocate in bytes - -RETURNS: -Pointer to allocated block, or NULL if out of memory. - -REMARKS: -Allocates a block of memory of length size. If you have changed the memory -allocation routines with the PM_useLocalMalloc function, then calls to this -function will actually make calls to the local memory allocation routines -that you have registered. - -SEE ALSO: -PM_calloc, PM_realloc, PM_free, PM_useLocalMalloc -****************************************************************************/ -void * PMAPI PM_malloc( - size_t size) -{ - return __PM_malloc(size); -} - -/**************************************************************************** -DESCRIPTION: -Allocate and clear a large memory block. - -HEADER: -pmapi.h - -PARAMETERS: -nelem - number of contiguous size-byte units to allocate -size - size of unit in bytes - -RETURNS: -Pointer to allocated memory if successful, NULL if out of memory. - -REMARKS: -Allocates a block of memory of length (size * nelem), and clears the -allocated area with zeros (0). If you have changed the memory allocation -routines with the PM_useLocalMalloc function, then calls to this function -will actually make calls to the local memory allocation routines that you -have registered. - -SEE ALSO: -PM_malloc, PM_realloc, PM_free, PM_useLocalMalloc -****************************************************************************/ -void * PMAPI PM_calloc( - size_t nelem, - size_t size) -{ - return __PM_calloc(nelem,size); -} - -/**************************************************************************** -DESCRIPTION: -Re-allocate a block of memory - -HEADER: -pmapi.h - -PARAMETERS: -ptr - Pointer to block to resize -size - size of unit in bytes - -RETURNS: -Pointer to allocated memory if successful, NULL if out of memory. - -REMARKS: -This function reallocates a block of memory that has been previously been -allocated to the new of size. The new size may be smaller or larger than -the original block of memory. If you have changed the memory allocation -routines with the PM_useLocalMalloc function, then calls to this function -will actually make calls to the local memory allocation routines that you -have registered. - -SEE ALSO: -PM_malloc, PM_calloc, PM_free, PM_useLocalMalloc -****************************************************************************/ -void * PMAPI PM_realloc( - void *ptr, - size_t size) -{ - return __PM_realloc(ptr,size); -} - -/**************************************************************************** -DESCRIPTION: -Frees a block of memory. - -HEADER: -pmapi.h - -PARAMETERS: -p - Pointer to memory block to free - -REMARKS: -Frees a block of memory previously allocated with either PM_malloc, -PM_calloc or PM_realloc. - -SEE ALSO: -PM_malloc, PM_calloc, PM_realloc, PM_useLocalMalloc -****************************************************************************/ -void PMAPI PM_free( - void *p) -{ - __PM_free(p); -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c b/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c deleted file mode 100644 index eed5f45..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c +++ /dev/null @@ -1,867 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Heavily based on code copyright (C) Richard Gooch -* -* Language: ANSI C -* Environment: 32-bit Ring 0 device driver -* -* Description: Generic Memory Type Range Register (MTRR) functions to -* manipulate the MTRR registers on supported CPU's. This code -* *must* run at ring 0, so you can't normally include this -* code directly in normal applications (the except is DOS4GW -* apps which run at ring 0 under real DOS). Thus this code -* will normally be compiled into a ring 0 device driver for -* the target operating system. -* -****************************************************************************/ - -#include "pmapi.h" -#include "ztimerc.h" -#include "mtrr.h" - -#ifndef REALMODE - -/*--------------------------- Global variables ----------------------------*/ - -/* Intel pre-defined MTRR registers */ - -#define NUM_FIXED_RANGES 88 -#define INTEL_cap_MSR 0x0FE -#define INTEL_defType_MSR 0x2FF -#define INTEL_fix64K_00000_MSR 0x250 -#define INTEL_fix16K_80000_MSR 0x258 -#define INTEL_fix16K_A0000_MSR 0x259 -#define INTEL_fix4K_C0000_MSR 0x268 -#define INTEL_fix4K_C8000_MSR 0x269 -#define INTEL_fix4K_D0000_MSR 0x26A -#define INTEL_fix4K_D8000_MSR 0x26B -#define INTEL_fix4K_E0000_MSR 0x26C -#define INTEL_fix4K_E8000_MSR 0x26D -#define INTEL_fix4K_F0000_MSR 0x26E -#define INTEL_fix4K_F8000_MSR 0x26F - -/* Macros to find the address of a paricular MSR register */ - -#define INTEL_physBase_MSR(reg) (0x200 + 2 * (reg)) -#define INTEL_physMask_MSR(reg) (0x200 + 2 * (reg) + 1) - -/* Cyrix CPU configuration register indexes */ -#define CX86_CCR0 0xC0 -#define CX86_CCR1 0xC1 -#define CX86_CCR2 0xC2 -#define CX86_CCR3 0xC3 -#define CX86_CCR4 0xE8 -#define CX86_CCR5 0xE9 -#define CX86_CCR6 0xEA -#define CX86_DIR0 0xFE -#define CX86_DIR1 0xFF -#define CX86_ARR_BASE 0xC4 -#define CX86_RCR_BASE 0xDC - -/* Structure to maintain machine state while updating MTRR registers */ - -typedef struct { - ulong flags; - ulong defTypeLo; - ulong defTypeHi; - ulong cr4Val; - ulong ccr3; - } MTRRContext; - -static int numMTRR = -1; -static int cpuFamily,cpuType,cpuStepping; -static void (*getMTRR)(uint reg,ulong *base,ulong *size,int *type) = NULL; -static void (*setMTRR)(uint reg,ulong base,ulong size,int type) = NULL; -static int (*getFreeRegion)(ulong base,ulong size) = NULL; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -RETURNS: -Returns non-zero if we have the write-combining memory type -****************************************************************************/ -static int MTRR_haveWriteCombine(void) -{ - ulong config,dummy; - - switch (cpuFamily) { - case CPU_AMD: - if (cpuType < CPU_AMDAthlon) { - /* AMD K6-2 stepping 8 and later support the MTRR registers. - * The earlier K6-2 steppings (300Mhz models) do not - * support MTRR's. - */ - if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8)) - return 0; - return 1; - } - /* Fall through for AMD Athlon which uses P6 style MTRR's */ - case CPU_Intel: - _MTRR_readMSR(INTEL_cap_MSR,&config,&dummy); - return (config & (1 << 10)); - case CPU_Cyrix: - /* Cyrix 6x86 and later support the MTRR registers */ - if (cpuType < CPU_Cyrix6x86) - return 0; - return 1; - } - return 0; -} - -/**************************************************************************** -PARAMETERS: -base - The starting physical base address of the region -size - The size in bytes of the region - -RETURNS: -The index of the region on success, else -1 on error. - -REMARKS: -Generic function to find the location of a free MTRR register to be used -for creating a new mapping. -****************************************************************************/ -static int GENERIC_getFreeRegion( - ulong base, - ulong size) -{ - int i,ltype; - ulong lbase,lsize; - - for (i = 0; i < numMTRR; i++) { - getMTRR(i,&lbase,&lsize,<ype); - if (lsize < 1) - return i; - } - (void)base; - (void)size; - return -1; -} - -/**************************************************************************** -PARAMETERS: -base - The starting physical base address of the region -size - The size in bytes of the region - -RETURNS: -The index of the region on success, else -1 on error. - -REMARKS: -Generic function to find the location of a free MTRR register to be used -for creating a new mapping. -****************************************************************************/ -static int AMDK6_getFreeRegion( - ulong base, - ulong size) -{ - int i,ltype; - ulong lbase,lsize; - - for (i = 0; i < numMTRR; i++) { - getMTRR(i,&lbase,&lsize,<ype); - if (lsize < 1) - return i; - } - (void)base; - (void)size; - return -1; -} - -/**************************************************************************** -PARAMETERS: -base - The starting physical base address of the region -size - The size in bytes of the region - -RETURNS: -The index of the region on success, else -1 on error. - -REMARKS: -Cyrix specific function to find the location of a free MTRR register to be -used for creating a new mapping. -****************************************************************************/ -static int CYRIX_getFreeRegion( - ulong base, - ulong size) -{ - int i,ltype; - ulong lbase, lsize; - - if (size > 0x2000000UL) { - /* If we are to set up a region >32M then look at ARR7 immediately */ - getMTRR(7,&lbase,&lsize,<ype); - if (lsize < 1) - return 7; - } - else { - /* Check ARR0-6 registers */ - for (i = 0; i < 7; i++) { - getMTRR(i,&lbase,&lsize,<ype); - if (lsize < 1) - return i; - } - /* Try ARR7 but its size must be at least 256K */ - getMTRR(7,&lbase,&lsize,<ype); - if ((lsize < 1) && (size >= 0x40000)) - return i; - } - (void)base; - return -1; -} - -/**************************************************************************** -PARAMETERS: -c - Place to store the machine context across the call - -REMARKS: -Puts the processor into a state where MTRRs can be safely updated -****************************************************************************/ -static void MTRR_beginUpdate( - MTRRContext *c) -{ - c->flags = _MTRR_disableInt(); - if (cpuFamily != CPU_AMD || (cpuFamily == CPU_AMD && cpuType >= CPU_AMDAthlon)) { - switch (cpuFamily) { - case CPU_Intel: - case CPU_AMD: - /* Disable MTRRs, and set the default type to uncached */ - c->cr4Val = _MTRR_saveCR4(); - _MTRR_readMSR(INTEL_defType_MSR,&c->defTypeLo,&c->defTypeHi); - _MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo & 0xF300UL,c->defTypeHi); - break; - case CPU_Cyrix: - c->ccr3 = _MTRR_getCx86(CX86_CCR3); - _MTRR_setCx86(CX86_CCR3, (uchar)((c->ccr3 & 0x0F) | 0x10)); - break; - } - } -} - -/**************************************************************************** -PARAMETERS: -c - Place to restore the machine context from - -REMARKS: -Restores the processor after updating any of the registers -****************************************************************************/ -static void MTRR_endUpdate( - MTRRContext *c) -{ - if (cpuFamily != CPU_AMD || (cpuFamily == CPU_AMD && cpuType >= CPU_AMDAthlon)) { - PM_flushTLB(); - switch (cpuFamily) { - case CPU_Intel: - case CPU_AMD: - _MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo,c->defTypeHi); - _MTRR_restoreCR4(c->cr4Val); - break; - case CPU_Cyrix: - _MTRR_setCx86(CX86_CCR3,(uchar)c->ccr3); - break; - } - } - - /* Re-enable interrupts (if enabled previously) */ - _MTRR_restoreInt(c->flags); -} - -/**************************************************************************** -PARAMETERS: -reg - MTRR register to read -base - Place to store the starting physical base address of the region -size - Place to store the size in bytes of the region -type - Place to store the type of the MTRR register - -REMARKS: -Intel specific function to read the value of a specific MTRR register. -****************************************************************************/ -static void INTEL_getMTRR( - uint reg, - ulong *base, - ulong *size, - int *type) -{ - ulong hi,maskLo,baseLo; - - _MTRR_readMSR(INTEL_physMask_MSR(reg),&maskLo,&hi); - if ((maskLo & 0x800) == 0) { - /* MTRR is disabled, so it is free */ - *base = 0; - *size = 0; - *type = 0; - return; - } - _MTRR_readMSR(INTEL_physBase_MSR(reg),&baseLo,&hi); - maskLo = (maskLo & 0xFFFFF000UL); - *size = ~(maskLo - 1); - *base = (baseLo & 0xFFFFF000UL); - *type = (baseLo & 0xFF); -} - -/**************************************************************************** -PARAMETERS: -reg - MTRR register to set -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -REMARKS: -Intel specific function to set the value of a specific MTRR register to -the passed in base, size and type. -****************************************************************************/ -static void INTEL_setMTRR( - uint reg, - ulong base, - ulong size, - int type) -{ - MTRRContext c; - - MTRR_beginUpdate(&c); - if (size == 0) { - /* The invalid bit is kept in the mask, so we simply clear the - * relevant mask register to disable a range. - */ - _MTRR_writeMSR(INTEL_physMask_MSR(reg),0,0); - } - else { - _MTRR_writeMSR(INTEL_physBase_MSR(reg),base | type,0); - _MTRR_writeMSR(INTEL_physMask_MSR(reg),~(size - 1) | 0x800,0); - } - MTRR_endUpdate(&c); -} - -/**************************************************************************** -REMARKS: -Disabled banked write combing for Intel processors. We always disable this -because it invariably causes problems with older hardware. -****************************************************************************/ -static void INTEL_disableBankedWriteCombine(void) -{ - MTRRContext c; - - MTRR_beginUpdate(&c); - _MTRR_writeMSR(INTEL_fix16K_A0000_MSR,0,0); - MTRR_endUpdate(&c); -} - -/**************************************************************************** -PARAMETERS: -reg - MTRR register to set -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -REMARKS: -Intel specific function to set the value of a specific MTRR register to -the passed in base, size and type. -****************************************************************************/ -static void AMD_getMTRR( - uint reg, - ulong *base, - ulong *size, - int *type) -{ - ulong low,high; - - /* Upper dword is region 1, lower is region 0 */ - _MTRR_readMSR(0xC0000085, &low, &high); - if (reg == 1) - low = high; - - /* Find the base and type for the region */ - *base = low & 0xFFFE0000; - *type = 0; - if (low & 1) - *type = PM_MTRR_UNCACHABLE; - if (low & 2) - *type = PM_MTRR_WRCOMB; - if ((low & 3) == 0) { - *size = 0; - return; - } - - /* This needs a little explaining. The size is stored as an - * inverted mask of bits of 128K granularity 15 bits long offset - * 2 bits - * - * So to get a size we do invert the mask and add 1 to the lowest - * mask bit (4 as its 2 bits in). This gives us a size we then shift - * to turn into 128K blocks - * - * eg 111 1111 1111 1100 is 512K - * - * invert 000 0000 0000 0011 - * +1 000 0000 0000 0100 - * *128K ... - */ - low = (~low) & 0x0FFFC; - *size = (low + 4) << 15; -} - -/**************************************************************************** -PARAMETERS: -reg - MTRR register to set -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -REMARKS: -Intel specific function to set the value of a specific MTRR register to -the passed in base, size and type. -****************************************************************************/ -static void AMD_setMTRR( - uint reg, - ulong base, - ulong size, - int type) -{ - ulong low,high,newVal; - MTRRContext c; - - MTRR_beginUpdate(&c); - _MTRR_readMSR(0xC0000085, &low, &high); - if (size == 0) { - /* Clear register to disable */ - if (reg) - high = 0; - else - low = 0; - } - else { - /* Set the register to the base (already shifted for us), the - * type (off by one) and an inverted bitmask of the size - * The size is the only odd bit. We are fed say 512K - * We invert this and we get 111 1111 1111 1011 but - * if you subtract one and invert you get the desired - * 111 1111 1111 1100 mask - */ - newVal = (((~(size-1)) >> 15) & 0x0001FFFC) | base | (type+1); - if (reg) - high = newVal; - else - low = newVal; - } - - /* The writeback rule is quite specific. See the manual. Its - * disable local interrupts, write back the cache, set the MTRR - */ - PM_flushTLB(); - _MTRR_writeMSR(0xC0000085, low, high); - MTRR_endUpdate(&c); -} - -/**************************************************************************** -PARAMETERS: -reg - MTRR register to set -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -REMARKS: -Intel specific function to set the value of a specific MTRR register to -the passed in base, size and type. -****************************************************************************/ -static void CYRIX_getMTRR( - uint reg, - ulong *base, - ulong *size, - int *type) -{ - MTRRContext c; - uchar arr = CX86_ARR_BASE + reg*3; - uchar rcr,shift; - - /* Save flags and disable interrupts */ - MTRR_beginUpdate(&c); - ((uchar*)base)[3] = _MTRR_getCx86(arr); - ((uchar*)base)[2] = _MTRR_getCx86((uchar)(arr+1)); - ((uchar*)base)[1] = _MTRR_getCx86((uchar)(arr+2)); - rcr = _MTRR_getCx86((uchar)(CX86_RCR_BASE + reg)); - MTRR_endUpdate(&c); - - /* Enable interrupts if it was enabled previously */ - shift = ((uchar*)base)[1] & 0x0f; - *base &= 0xFFFFF000UL; - - /* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7 - * Note: shift==0xF means 4G, this is unsupported. - */ - if (shift) - *size = (reg < 7 ? 0x800UL : 0x20000UL) << shift; - else - *size = 0; - - /* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */ - if (reg < 7) { - switch (rcr) { - case 1: *type = PM_MTRR_UNCACHABLE; break; - case 8: *type = PM_MTRR_WRBACK; break; - case 9: *type = PM_MTRR_WRCOMB; break; - case 24: - default: *type = PM_MTRR_WRTHROUGH; break; - } - } - else { - switch (rcr) { - case 0: *type = PM_MTRR_UNCACHABLE; break; - case 8: *type = PM_MTRR_WRCOMB; break; - case 9: *type = PM_MTRR_WRBACK; break; - case 25: - default: *type = PM_MTRR_WRTHROUGH; break; - } - } -} - -/**************************************************************************** -PARAMETERS: -reg - MTRR register to set -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -REMARKS: -Intel specific function to set the value of a specific MTRR register to -the passed in base, size and type. -****************************************************************************/ -static void CYRIX_setMTRR( - uint reg, - ulong base, - ulong size, - int type) -{ - MTRRContext c; - uchar arr = CX86_ARR_BASE + reg*3; - uchar arr_type,arr_size; - - /* Count down from 32M (ARR0-ARR6) or from 2G (ARR7) */ - size >>= (reg < 7 ? 12 : 18); - size &= 0x7FFF; /* Make sure arr_size <= 14 */ - for (arr_size = 0; size; arr_size++, size >>= 1) - ; - if (reg < 7) { - switch (type) { - case PM_MTRR_UNCACHABLE: arr_type = 1; break; - case PM_MTRR_WRCOMB: arr_type = 9; break; - case PM_MTRR_WRTHROUGH: arr_type = 24; break; - default: arr_type = 8; break; - } - } - else { - switch (type) { - case PM_MTRR_UNCACHABLE: arr_type = 0; break; - case PM_MTRR_WRCOMB: arr_type = 8; break; - case PM_MTRR_WRTHROUGH: arr_type = 25; break; - default: arr_type = 9; break; - } - } - MTRR_beginUpdate(&c); - _MTRR_setCx86((uchar)arr, ((uchar*)&base)[3]); - _MTRR_setCx86((uchar)(arr+1), ((uchar*)&base)[2]); - _MTRR_setCx86((uchar)(arr+2), (uchar)((((uchar*)&base)[1]) | arr_size)); - _MTRR_setCx86((uchar)(CX86_RCR_BASE + reg), (uchar)arr_type); - MTRR_endUpdate(&c); -} - -/**************************************************************************** -REMARKS: -On Cyrix 6x86(MX) and MII the ARR3 is special: it has connection -with the SMM (System Management Mode) mode. So we need the following: -Check whether SMI_LOCK (CCR3 bit 0) is set - if it is set, ARR3 cannot be changed (it cannot be changed until the - next processor reset) - if it is reset, then we can change it, set all the needed bits: - - disable access to SMM memory through ARR3 range (CCR1 bit 7 reset) - - disable access to SMM memory (CCR1 bit 2 reset) - - disable SMM mode (CCR1 bit 1 reset) - - disable write protection of ARR3 (CCR6 bit 1 reset) - - (maybe) disable ARR3 -Just to be sure, we enable ARR usage by the processor (CCR5 bit 5 set) -****************************************************************************/ -static void CYRIX_initARR(void) -{ - MTRRContext c; - uchar ccr[7]; - int ccrc[7] = { 0, 0, 0, 0, 0, 0, 0 }; - - /* Begin updating */ - MTRR_beginUpdate(&c); - - /* Save all CCRs locally */ - ccr[0] = _MTRR_getCx86(CX86_CCR0); - ccr[1] = _MTRR_getCx86(CX86_CCR1); - ccr[2] = _MTRR_getCx86(CX86_CCR2); - ccr[3] = (uchar)c.ccr3; - ccr[4] = _MTRR_getCx86(CX86_CCR4); - ccr[5] = _MTRR_getCx86(CX86_CCR5); - ccr[6] = _MTRR_getCx86(CX86_CCR6); - if (ccr[3] & 1) - ccrc[3] = 1; - else { - /* Disable SMM mode (bit 1), access to SMM memory (bit 2) and - * access to SMM memory through ARR3 (bit 7). - */ - if (ccr[6] & 0x02) { - ccr[6] &= 0xFD; - ccrc[6] = 1; /* Disable write protection of ARR3. */ - _MTRR_setCx86(CX86_CCR6,ccr[6]); - } - } - - /* If we changed CCR1 in memory, change it in the processor, too. */ - if (ccrc[1]) - _MTRR_setCx86(CX86_CCR1,ccr[1]); - - /* Enable ARR usage by the processor */ - if (!(ccr[5] & 0x20)) { - ccr[5] |= 0x20; - ccrc[5] = 1; - _MTRR_setCx86(CX86_CCR5,ccr[5]); - } - - /* We are finished updating */ - MTRR_endUpdate(&c); -} - -/**************************************************************************** -REMARKS: -Initialise the MTRR module, by detecting the processor type and determining -if the processor supports the MTRR functionality. -****************************************************************************/ -void MTRR_init(void) -{ - int i,cpu,ltype; - ulong eax,edx,lbase,lsize; - - /* Check that we have a compatible CPU */ - if (numMTRR == -1) { - numMTRR = 0; - if (!_MTRR_isRing0()) - return; - cpu = CPU_getProcessorType(); - cpuFamily = cpu & CPU_familyMask; - cpuType = cpu & CPU_mask; - cpuStepping = (cpu & CPU_steppingMask) >> CPU_steppingShift; - switch (cpuFamily) { - case CPU_Intel: - /* Intel Pentium Pro and later support the MTRR registers */ - if (cpuType < CPU_PentiumPro) - return; - _MTRR_readMSR(INTEL_cap_MSR,&eax,&edx); - numMTRR = eax & 0xFF; - getMTRR = INTEL_getMTRR; - setMTRR = INTEL_setMTRR; - getFreeRegion = GENERIC_getFreeRegion; - INTEL_disableBankedWriteCombine(); - break; - case CPU_AMD: - /* AMD K6-2 and later support the MTRR registers */ - if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8)) - return; - if (cpuType < CPU_AMDAthlon) { - numMTRR = 2; /* AMD CPU's have 2 MTRR's */ - getMTRR = AMD_getMTRR; - setMTRR = AMD_setMTRR; - getFreeRegion = AMDK6_getFreeRegion; - - /* For some reason some IBM systems with K6-2 processors - * have write combined enabled for the system BIOS - * region from 0xE0000 to 0xFFFFFF. We need *both* MTRR's - * for our own graphics drivers, so if we detect any - * regions below the 1Meg boundary, we remove them - * so we can use this MTRR register ourselves. - */ - for (i = 0; i < numMTRR; i++) { - getMTRR(i,&lbase,&lsize,<ype); - if (lbase < 0x100000) - setMTRR(i,0,0,0); - } - } - else { - /* AMD Athlon uses P6 style MTRR's */ - _MTRR_readMSR(INTEL_cap_MSR,&eax,&edx); - numMTRR = eax & 0xFF; - getMTRR = INTEL_getMTRR; - setMTRR = INTEL_setMTRR; - getFreeRegion = GENERIC_getFreeRegion; - INTEL_disableBankedWriteCombine(); - } - break; - case CPU_Cyrix: - /* Cyrix 6x86 and later support the MTRR registers */ - if (cpuType < CPU_Cyrix6x86 || cpuType >= CPU_CyrixMediaGX) - return; - numMTRR = 8; /* Cyrix CPU's have 8 ARR's */ - getMTRR = CYRIX_getMTRR; - setMTRR = CYRIX_setMTRR; - getFreeRegion = CYRIX_getFreeRegion; - CYRIX_initARR(); - break; - default: - return; - } - } -} - -/**************************************************************************** -PARAMETERS: -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -RETURNS: -Error code describing the result. - -REMARKS: -Function to enable write combining for the specified region of memory. -****************************************************************************/ -int MTRR_enableWriteCombine( - ulong base, - ulong size, - uint type) -{ - int i; - int ltype; - ulong lbase,lsize,last; - - /* Check that we have a CPU that supports MTRR's and type is valid */ - if (numMTRR <= 0) { - if (!_MTRR_isRing0()) - return PM_MTRR_ERR_NO_OS_SUPPORT; - return PM_MTRR_NOT_SUPPORTED; - } - if (type >= PM_MTRR_MAX) - return PM_MTRR_ERR_PARAMS; - - /* If the type is WC, check that this processor supports it */ - if (!MTRR_haveWriteCombine()) - return PM_MTRR_ERR_NOWRCOMB; - - /* Adjust the boundaries depending on the CPU type */ - switch (cpuFamily) { - case CPU_AMD: - if (cpuType < CPU_AMDAthlon) { - /* Apply the K6 block alignment and size rules. In order: - * o Uncached or gathering only - * o 128K or bigger block - * o Power of 2 block - * o base suitably aligned to the power - */ - if (type > PM_MTRR_WRCOMB && (size < (1 << 17) || (size & ~(size-1))-size || (base & (size-1)))) - return PM_MTRR_ERR_NOT_ALIGNED; - break; - } - /* Fall through for AMD Athlon which uses P6 style MTRR's */ - case CPU_Intel: - case CPU_Cyrix: - if ((base & 0xFFF) || (size & 0xFFF)) { - /* Base and size must be multiples of 4Kb */ - return PM_MTRR_ERR_NOT_4KB_ALIGNED; - } - if (base < 0x100000) { - /* Base must be >= 1Mb */ - return PM_MTRR_ERR_BELOW_1MB; - } - - /* Check upper bits of base and last are equal and lower bits - * are 0 for base and 1 for last - */ - last = base + size - 1; - for (lbase = base; !(lbase & 1) && (last & 1); lbase = lbase >> 1, last = last >> 1) - ; - if (lbase != last) { - /* Base is not aligned on the correct boundary */ - return PM_MTRR_ERR_NOT_ALIGNED; - } - break; - default: - return PM_MTRR_NOT_SUPPORTED; - } - - /* Search for existing MTRR */ - for (i = 0; i < numMTRR; ++i) { - getMTRR(i,&lbase,&lsize,<ype); - if (lbase == 0 && lsize == 0) - continue; - if (base > lbase + (lsize-1)) - continue; - if ((base < lbase) && (base+size-1 < lbase)) - continue; - - /* Check that we don't overlap an existing region */ - if (type != PM_MTRR_UNCACHABLE) { - if ((base < lbase) || (base+size-1 > lbase+lsize-1)) - return PM_MTRR_ERR_OVERLAP; - } - else if (base == lbase && size == lsize) { - /* The region already exists so leave it alone */ - return PM_MTRR_ERR_OK; - } - - /* New region is enclosed by an existing region, so only allow - * a new type to be created if we are setting a region to be - * uncacheable (such as MMIO registers within a framebuffer). - */ - if (ltype != (int)type) { - if (type == PM_MTRR_UNCACHABLE) - continue; - return PM_MTRR_ERR_TYPE_MISMATCH; - } - return PM_MTRR_ERR_OK; - } - - /* Search for an empty MTRR */ - if ((i = getFreeRegion(base,size)) < 0) - return PM_MTRR_ERR_NONE_FREE; - setMTRR(i,base,size,type); - return PM_MTRR_ERR_OK; -} - -/**************************************************************************** -PARAMETERS: -callback - Function to callback with write combine information - -REMARKS: -Function to enumerate all write combine regions currently enabled for the -processor. -****************************************************************************/ -int PMAPI PM_enumWriteCombine( - PM_enumWriteCombine_t callback) -{ - int i,ltype; - ulong lbase,lsize; - - /* Check that we have a CPU that supports MTRR's and type is valid */ - if (numMTRR <= 0) { - if (!_MTRR_isRing0()) - return PM_MTRR_ERR_NO_OS_SUPPORT; - return PM_MTRR_NOT_SUPPORTED; - } - - /* Enumerate all existing MTRR's */ - for (i = 0; i < numMTRR; ++i) { - getMTRR(i,&lbase,&lsize,<ype); - callback(lbase,lsize,ltype); - } - return PM_MTRR_ERR_OK; -} -#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c b/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c deleted file mode 100644 index 1d542fc..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c +++ /dev/null @@ -1,747 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Module for interfacing to the PCI bus and configuration -* space registers. -* -****************************************************************************/ - -#include "pmapi.h" -#include "pcilib.h" -#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) -#include -#endif - -/*---------------------- Macros and type definitions ----------------------*/ - -#pragma pack(1) - -/* Length of the memory mapping for the PCI BIOS */ - -#define BIOS_LIMIT (128 * 1024L - 1) - -/* Macros for accessing the PCI BIOS functions from 32-bit protected mode */ - -#define BIOS32_SIGNATURE (((ulong)'_' << 0) + ((ulong)'3' << 8) + ((ulong)'2' << 16) + ((ulong)'_' << 24)) -#define PCI_SIGNATURE (((ulong)'P' << 0) + ((ulong)'C' << 8) + ((ulong)'I' << 16) + ((ulong)' ' << 24)) -#define PCI_SERVICE (((ulong)'$' << 0) + ((ulong)'P' << 8) + ((ulong)'C' << 16) + ((ulong)'I' << 24)) -#define PCI_BIOS_PRESENT 0xB101 -#define FIND_PCI_DEVICE 0xB102 -#define FIND_PCI_CLASS 0xB103 -#define GENERATE_SPECIAL 0xB106 -#define READ_CONFIG_BYTE 0xB108 -#define READ_CONFIG_WORD 0xB109 -#define READ_CONFIG_DWORD 0xB10A -#define WRITE_CONFIG_BYTE 0xB10B -#define WRITE_CONFIG_WORD 0xB10C -#define WRITE_CONFIG_DWORD 0xB10D -#define GET_IRQ_ROUTING_OPT 0xB10E -#define SET_PCI_IRQ 0xB10F - -/* This is the standard structure used to identify the entry point to the - * BIOS32 Service Directory, as documented in PCI 2.1 BIOS Specicition. - */ - -typedef union { - struct { - ulong signature; /* _32_ */ - ulong entry; /* 32 bit physical address */ - uchar revision; /* Revision level, 0 */ - uchar length; /* Length in paragraphs should be 01 */ - uchar checksum; /* All bytes must add up to zero */ - uchar reserved[5]; /* Must be zero */ - } fields; - char chars[16]; - } PCI_bios32; - -/* Structure for a far pointer to call the PCI BIOS services with */ - -typedef struct { - ulong address; - ushort segment; - } PCIBIOS_entry; - -/* Macros to copy a structure that includes dwSize members */ - -#define COPY_STRUCTURE(d,s) memcpy(d,s,MIN((s)->dwSize,(d)->dwSize)) - -#pragma pack() - -/*--------------------------- Global variables ----------------------------*/ - -static uchar *BIOSImage = NULL; /* BIOS image mapping */ -static int PCIBIOSVersion = -1;/* PCI BIOS version */ -static PCIBIOS_entry PCIEntry; /* PCI services entry point */ -static ulong PCIPhysEntry = 0; /* Physical address */ - -/*----------------------------- Implementation ----------------------------*/ - -/* External assembler helper functions */ - -uchar _ASMAPI _BIOS32_service(ulong service,ulong function,ulong *physBase,ulong *length,ulong *serviceOffset,PCIBIOS_entry entry); -ushort _ASMAPI _PCIBIOS_isPresent(ulong i_eax,ulong *o_edx,ushort *o_ax,uchar *o_cl,PCIBIOS_entry entry); -ulong _ASMAPI _PCIBIOS_service(ulong r_eax,ulong r_ebx,ulong r_edi,ulong r_ecx,PCIBIOS_entry entry); -int _ASMAPI _PCIBIOS_getRouting(PCIRoutingOptionsBuffer *buf,PCIBIOS_entry entry); -ibool _ASMAPI _PCIBIOS_setIRQ(int busDev,int intPin,int IRQ,PCIBIOS_entry entry); -ulong _ASMAPI _PCIBIOS_specialCycle(int bus,ulong data,PCIBIOS_entry entry); -ushort _ASMAPI _PCI_getCS(void); - -/**************************************************************************** -REMARKS: -This functions returns the physical address of the PCI BIOS entry point. -****************************************************************************/ -ulong _ASMAPI PCIBIOS_getEntry(void) -{ return PCIPhysEntry; } - -/**************************************************************************** -PARAMETERS: -hwType - Place to store the PCI hardware access mechanism flags -lastBus - Place to store the index of the last PCI bus in the system - -RETURNS: -Version number of the PCI BIOS found. - -REMARKS: -This function determines if the PCI BIOS is present in the system, and if -so returns the information returned by the PCI BIOS detect function. -****************************************************************************/ -static int PCIBIOS_detect( - uchar *hwType, - uchar *lastBus) -{ - ulong signature; - ushort stat,version; - -#ifndef __16BIT__ - PCIBIOS_entry BIOSEntry = {0}; - uchar *BIOSEnd; - PCI_bios32 *BIOSDir; - ulong physBase,length,offset; - - /* Bail if we have already detected no BIOS is present */ - if (PCIBIOSVersion == 0) - return 0; - - /* First scan the memory from 0xE0000 to 0xFFFFF looking for the - * BIOS32 service directory, so we can determine if we can call it - * from 32-bit protected mode. - */ - if (PCIBIOSVersion == -1) { - PCIBIOSVersion = 0; - BIOSImage = PM_mapPhysicalAddr(0xE0000,BIOS_LIMIT,false); - if (!BIOSImage) - return 0; - BIOSEnd = BIOSImage + 0x20000; - for (BIOSDir = (PCI_bios32*)BIOSImage; BIOSDir < (PCI_bios32*)BIOSEnd; BIOSDir++) { - uchar sum; - int i,length; - - if (BIOSDir->fields.signature != BIOS32_SIGNATURE) - continue; - length = BIOSDir->fields.length * 16; - if (!length) - continue; - for (sum = i = 0; i < length ; i++) - sum += BIOSDir->chars[i]; - if (sum != 0) - continue; - BIOSEntry.address = (ulong)BIOSImage + (BIOSDir->fields.entry - 0xE0000); - BIOSEntry.segment = _PCI_getCS(); - break; - } - - /* If we found the BIOS32 directory, call it to get the address of the - * PCI services. - */ - if (BIOSEntry.address == 0) - return 0; - if (_BIOS32_service(PCI_SERVICE,0,&physBase,&length,&offset,BIOSEntry) != 0) - return 0; - PCIPhysEntry = physBase + offset; - PCIEntry.address = (ulong)BIOSImage + (PCIPhysEntry - 0xE0000); - PCIEntry.segment = _PCI_getCS(); - } -#endif - /* We found the BIOS entry, so now do the version check */ - version = _PCIBIOS_isPresent(PCI_BIOS_PRESENT,&signature,&stat,lastBus,PCIEntry); - if (version > 0 && ((stat >> 8) == 0) && signature == PCI_SIGNATURE) { - *hwType = stat & 0xFF; - return PCIBIOSVersion = version; - } - return 0; -} - -/**************************************************************************** -PARAMETERS: -info - Array of PCIDeviceInfo structures to check against -index - Index of the current device to check - -RETURNS: -True if the device is a duplicate, false if not. - -REMARKS: -This function goes through the list of all devices preceeding the newly -found device in the info structure, and checks that the device is not a -duplicate of a previous device. Some devices incorrectly enumerate -themselves at different function addresses so we check here to exclude -those cases. -****************************************************************************/ -static ibool CheckDuplicate( - PCIDeviceInfo *info, - PCIDeviceInfo *prev) -{ - /* Ignore devices with a vendor ID of 0 */ - if (info->VendorID == 0) - return true; - - /* NOTE: We only check against the current device on - * the bus to ensure that we do not exclude - * multiple controllers of the same device ID. - */ - if (info->slot.p.Bus == prev->slot.p.Bus && - info->slot.p.Device == prev->slot.p.Device && - info->DeviceID == prev->DeviceID) - return true; - return false; -} - -/**************************************************************************** -PARAMETERS: -info - Array of PCIDeviceInfo structures to fill in -maxDevices - Maximum number of of devices to enumerate into array - -RETURNS: -Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. - -REMARKS: -Function to enumerate all available devices on the PCI bus into an array -of configuration information blocks. -****************************************************************************/ -static int PCI_enumerateMech1( - PCIDeviceInfo info[]) -{ - int bus,device,function,i,numFound = 0; - ulong *lp,tmp; - PCIslot slot = {{0,0,0,0,0,0,1}}; - PCIDeviceInfo pci,prev = {0}; - - /* Try PCI access mechanism 1 */ - PM_outpb(0xCFB,0x01); - tmp = PM_inpd(0xCF8); - PM_outpd(0xCF8,slot.i); - if ((PM_inpd(0xCF8) == slot.i) && (PM_inpd(0xCFC) != 0xFFFFFFFFUL)) { - /* PCI access mechanism 1 - the preferred mechanism */ - for (bus = 0; bus < 8; bus++) { - slot.p.Bus = bus; - for (device = 0; device < 32; device++) { - slot.p.Device = device; - for (function = 0; function < 8; function++) { - slot.p.Function = function; - slot.p.Register = 0; - PM_outpd(0xCF8,slot.i); - if (PM_inpd(0xCFC) != 0xFFFFFFFFUL) { - memset(&pci,0,sizeof(pci)); - pci.dwSize = sizeof(pci); - pci.mech1 = 1; - pci.slot = slot; - lp = (ulong*)&(pci.VendorID); - for (i = 0; i < NUM_PCI_REG; i++, lp++) { - slot.p.Register = i; - PM_outpd(0xCF8,slot.i); - *lp = PM_inpd(0xCFC); - } - if (!CheckDuplicate(&pci,&prev)) { - if (info) - COPY_STRUCTURE(&info[numFound],&pci); - ++numFound; - } - prev = pci; - } - } - } - } - - /* Disable PCI config cycle on exit */ - PM_outpd(0xCF8,0); - return numFound; - } - PM_outpd(0xCF8,tmp); - - /* No hardware access mechanism 1 found */ - return 0; -} - -/**************************************************************************** -PARAMETERS: -info - Array of PCIDeviceInfo structures to fill in -maxDevices - Maximum number of of devices to enumerate into array - -RETURNS: -Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. - -REMARKS: -Function to enumerate all available devices on the PCI bus into an array -of configuration information blocks. -****************************************************************************/ -static int PCI_enumerateMech2( - PCIDeviceInfo info[]) -{ - int bus,device,function,i,numFound = 0; - ushort deviceIO; - ulong *lp; - PCIslot slot = {{0,0,0,0,0,0,1}}; - PCIDeviceInfo pci,prev = {0}; - - /* Try PCI access mechanism 2 */ - PM_outpb(0xCFB,0x00); - PM_outpb(0xCF8,0x00); - PM_outpb(0xCFA,0x00); - if (PM_inpb(0xCF8) == 0x00 && PM_inpb(0xCFB) == 0x00) { - /* PCI access mechanism 2 - the older mechanism for legacy busses */ - for (bus = 0; bus < 2; bus++) { - slot.p.Bus = bus; - PM_outpb(0xCFA,(uchar)bus); - for (device = 0; device < 16; device++) { - slot.p.Device = device; - deviceIO = 0xC000 + (device << 8); - for (function = 0; function < 8; function++) { - slot.p.Function = function; - slot.p.Register = 0; - PM_outpb(0xCF8,(uchar)((function << 1) | 0x10)); - if (PM_inpd(deviceIO) != 0xFFFFFFFFUL) { - memset(&pci,0,sizeof(pci)); - pci.dwSize = sizeof(pci); - pci.mech1 = 0; - pci.slot = slot; - lp = (ulong*)&(pci.VendorID); - for (i = 0; i < NUM_PCI_REG; i++, lp++) { - slot.p.Register = i; - *lp = PM_inpd(deviceIO + (i << 2)); - } - if (!CheckDuplicate(&pci,&prev)) { - if (info) - COPY_STRUCTURE(&info[numFound],&pci); - ++numFound; - } - prev = pci; - } - } - } - } - - /* Disable PCI config cycle on exit */ - PM_outpb(0xCF8,0); - return numFound; - } - - /* No hardware access mechanism 2 found */ - return 0; -} - -/**************************************************************************** -REMARKS: -This functions reads a configuration dword via the PCI BIOS. -****************************************************************************/ -static ulong PCIBIOS_readDWORD( - int index, - ulong slot) -{ - return (ulong)_PCIBIOS_service(READ_CONFIG_DWORD,slot >> 8,index,0,PCIEntry); -} - -/**************************************************************************** -PARAMETERS: -info - Array of PCIDeviceInfo structures to fill in -maxDevices - Maximum number of of devices to enumerate into array - -RETURNS: -Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. - -REMARKS: -Function to enumerate all available devices on the PCI bus into an array -of configuration information blocks. -****************************************************************************/ -static int PCI_enumerateBIOS( - PCIDeviceInfo info[]) -{ - uchar hwType,lastBus; - int bus,device,function,i,numFound = 0; - ulong *lp; - PCIslot slot = {{0,0,0,0,0,0,1}}; - PCIDeviceInfo pci,prev = {0}; - - if (PCIBIOS_detect(&hwType,&lastBus)) { - /* PCI BIOS access - the ultimate fallback */ - for (bus = 0; bus <= lastBus; bus++) { - slot.p.Bus = bus; - for (device = 0; device < 32; device++) { - slot.p.Device = device; - for (function = 0; function < 8; function++) { - slot.p.Function = function; - if (PCIBIOS_readDWORD(0,slot.i) != 0xFFFFFFFFUL) { - memset(&pci,0,sizeof(pci)); - pci.dwSize = sizeof(pci); - pci.mech1 = 2; - pci.slot = slot; - lp = (ulong*)&(pci.VendorID); - for (i = 0; i < NUM_PCI_REG; i++, lp++) - *lp = PCIBIOS_readDWORD(i << 2,slot.i); - if (!CheckDuplicate(&pci,&prev)) { - if (info) - COPY_STRUCTURE(&info[numFound],&pci); - ++numFound; - } - prev = pci; - } - } - } - } - } - - /* Return number of devices found */ - return numFound; -} - -/**************************************************************************** -PARAMETERS: -info - Array of PCIDeviceInfo structures to fill in -maxDevices - Maximum number of of devices to enumerate into array - -RETURNS: -Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. - -REMARKS: -Function to enumerate all available devices on the PCI bus into an array -of configuration information blocks. -****************************************************************************/ -int _ASMAPI PCI_enumerate( - PCIDeviceInfo info[]) -{ - int numFound; - - /* First try via the direct access mechanisms which are faster if we - * have them (nearly always). The BIOS is used as a fallback, and for - * stuff we can't do directly. - */ - if ((numFound = PCI_enumerateMech1(info)) == 0) { - if ((numFound = PCI_enumerateMech2(info)) == 0) { - if ((numFound = PCI_enumerateBIOS(info)) == 0) - return 0; - } - } - return numFound; -} - -/**************************************************************************** -PARAMETERS: -info - Array of PCIDeviceInfo structures to fill in -maxDevices - Maximum number of of devices to enumerate into array - -RETURNS: -Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. - -REMARKS: -Function to enumerate all available devices on the PCI bus into an array -of configuration information blocks. -****************************************************************************/ -int _ASMAPI PCI_getNumDevices(void) -{ - return PCI_enumerate(NULL); -} - -/**************************************************************************** -PARAMETERS: -bar - Base address to measure -pci - PCI device to access - -RETURNS: -Size of the PCI base address in bytes - -REMARKS: -This function measures the size of the PCI base address register in bytes, -by writing all F's to the register, and reading the value back. The size -of the base address is determines by the bits that are hardwired to zero's. -****************************************************************************/ -ulong _ASMAPI PCI_findBARSize( - int bar, - PCIDeviceInfo *pci) -{ - ulong base,size = 0; - - base = PCI_accessReg(bar,0,PCI_READ_DWORD,pci); - if (base && !(base & 0x1)) { - /* For some strange reason some devices don't properly decode - * their base address registers (Intel PCI/PCI bridges!), and - * we read completely bogus values. We check for that here - * and clear out those BAR's. - * - * We check for that here because at least the low 12 bits - * of the address range must be zeros, since the page size - * on IA32 processors is always 4Kb. - */ - if ((base & 0xFFF) == 0) { - PCI_accessReg(bar,0xFFFFFFFF,PCI_WRITE_DWORD,pci); - size = PCI_accessReg(bar,0,PCI_READ_DWORD,pci) & ~0xFF; - size = ~size+1; - PCI_accessReg(bar,base,PCI_WRITE_DWORD,pci); - } - } - pci->slot.p.Register = 0; - return size; -} - -/**************************************************************************** -PARAMETERS: -index - DWORD index of the register to access -value - Value to write to the register for write access -func - Function to implement - -RETURNS: -The value read from the register for read operations - -REMARKS: -The function code are defined as follows - -code - function -0 - Read BYTE -1 - Read WORD -2 - Read DWORD -3 - Write BYTE -4 - Write WORD -5 - Write DWORD -****************************************************************************/ -ulong _ASMAPI PCI_accessReg( - int index, - ulong value, - int func, - PCIDeviceInfo *info) -{ - int iobase; - - if (info->mech1 == 2) { - /* Use PCI BIOS access since we dont have direct hardware access */ - switch (func) { - case PCI_READ_BYTE: - return (uchar)_PCIBIOS_service(READ_CONFIG_BYTE,info->slot.i >> 8,index,0,PCIEntry); - case PCI_READ_WORD: - return (ushort)_PCIBIOS_service(READ_CONFIG_WORD,info->slot.i >> 8,index,0,PCIEntry); - case PCI_READ_DWORD: - return (ulong)_PCIBIOS_service(READ_CONFIG_DWORD,info->slot.i >> 8,index,0,PCIEntry); - case PCI_WRITE_BYTE: - _PCIBIOS_service(WRITE_CONFIG_BYTE,info->slot.i >> 8,index,value,PCIEntry); - break; - case PCI_WRITE_WORD: - _PCIBIOS_service(WRITE_CONFIG_WORD,info->slot.i >> 8,index,value,PCIEntry); - break; - case PCI_WRITE_DWORD: - _PCIBIOS_service(WRITE_CONFIG_DWORD,info->slot.i >> 8,index,value,PCIEntry); - break; - } - } - else { - /* Use direct hardware access mechanisms */ - if (info->mech1) { - /* PCI access mechanism 1 */ - iobase = 0xCFC + (index & 3); - info->slot.p.Register = index >> 2; - PM_outpd(0xCF8,info->slot.i); - } - else { - /* PCI access mechanism 2 */ - PM_outpb(0xCF8,(uchar)((info->slot.p.Function << 1) | 0x10)); - PM_outpb(0xCFA,(uchar)info->slot.p.Bus); - iobase = 0xC000 + (info->slot.p.Device << 8) + index; - } - switch (func) { - case PCI_READ_BYTE: - case PCI_READ_WORD: - case PCI_READ_DWORD: value = PM_inpd(iobase); break; - case PCI_WRITE_BYTE: PM_outpb(iobase,(uchar)value); break; - case PCI_WRITE_WORD: PM_outpw(iobase,(ushort)value); break; - case PCI_WRITE_DWORD: PM_outpd(iobase,(ulong)value); break; - } - PM_outpd(0xCF8,0); - } - return value; -} - -/**************************************************************************** -PARAMETERS: -numDevices - Number of devices to query info for - -RETURNS: -0 on success, -1 on error, number of devices to enumerate if numDevices = 0 - -REMARKS: -This function reads the PCI routing information. If you pass a value of -0 for numDevices, this function will return with the number of devices -needed in the routing buffer that will be filled in by the BIOS. -****************************************************************************/ -ibool _ASMAPI PCI_getIRQRoutingOptions( - int numDevices, - PCIRouteInfo *buffer) -{ - PCIRoutingOptionsBuffer buf; - int ret; - - if (PCIPhysEntry) { - buf.BufferSize = numDevices * sizeof(PCIRouteInfo); - buf.DataBuffer = buffer; - if ((ret = _PCIBIOS_getRouting(&buf,PCIEntry)) == 0x89) - return buf.BufferSize / sizeof(PCIRouteInfo); - if (ret != 0) - return -1; - return 0; - } - - /* We currently only support this via the PCI BIOS functions */ - return -1; -} - -/**************************************************************************** -PARAMETERS: -info - PCI device information for the specified device -intPin - Value to store in the PCI InterruptPin register -IRQ - New ISA IRQ to map the PCI interrupt to (0-15) - -RETURNS: -True on success, or false if this function failed. - -REMARKS: -This function changes the PCI IRQ routing for the specified device to the -desired PCI interrupt and the desired ISA bus compatible IRQ. This function -may not be supported by the PCI BIOS, in which case this function will -fail. -****************************************************************************/ -ibool _ASMAPI PCI_setHardwareIRQ( - PCIDeviceInfo *info, - uint intPin, - uint IRQ) -{ - if (PCIPhysEntry) { - if (_PCIBIOS_setIRQ(info->slot.i >> 8,intPin,IRQ,PCIEntry)) { - info->u.type0.InterruptPin = intPin; - info->u.type0.InterruptLine = IRQ; - return true; - } - return false; - } - - /* We currently only support this via the PCI BIOS functions */ - return false; -} - -/**************************************************************************** -PARAMETERS: -bus - Bus number to generate the special cycle for -specialCycleData - Data to send for the special cyle - -REMARKS: -This function generates a special cycle on the specified bus using with -the specified data. -****************************************************************************/ -void _ASMAPI PCI_generateSpecialCyle( - uint bus, - ulong specialCycleData) -{ - if (PCIPhysEntry) - _PCIBIOS_specialCycle(bus,specialCycleData,PCIEntry); - /* We currently only support this via the PCI BIOS functions */ -} - -/**************************************************************************** -PARAMETERS: -info - PCI device information block for device to access -index - Index of register to start reading from -dst - Place to store the values read from configuration space -count - Count of bytes to read from configuration space - -REMARKS: -This function is used to read a block of PCI configuration space registers -from the configuration space into the passed in data block. This function -will properly handle reading non-DWORD aligned data from the configuration -space correctly. -****************************************************************************/ -void _ASMAPI PCI_readRegBlock( - PCIDeviceInfo *info, - int index, - void *dst, - int count) -{ - uchar *pb; - ulong *pd; - int i; - int startCount = (index & 3); - int middleCount = (count - startCount) >> 2; - int endCount = count - middleCount * 4 - startCount; - - for (i = 0,pb = dst; i < startCount; i++, index++) { - *pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info); - } - for (i = 0,pd = (ulong*)pb; i < middleCount; i++, index += 4) { - *pd++ = (ulong)PCI_accessReg(index,0,PCI_READ_DWORD,info); - } - for (i = 0,pb = (uchar*)pd; i < endCount; i++, index++) { - *pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info); - } -} - -/**************************************************************************** -PARAMETERS: -info - PCI device information block for device to access -index - Index of register to start reading from -dst - Place to store the values read from configuration space -count - Count of bytes to read from configuration space - -REMARKS: -This function is used to write a block of PCI configuration space registers -to the configuration space from the passed in data block. This function -will properly handle writing non-DWORD aligned data to the configuration -space correctly. -****************************************************************************/ -void _ASMAPI PCI_writeRegBlock( - PCIDeviceInfo *info, - int index, - void *src, - int count) -{ - uchar *pb; - ulong *pd; - int i; - int startCount = (index & 3); - int middleCount = (count - startCount) >> 2; - int endCount = count - middleCount * 4 - startCount; - - for (i = 0,pb = src; i < startCount; i++, index++) { - PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info); - } - for (i = 0,pd = (ulong*)pb; i < middleCount; i++, index += 4) { - PCI_accessReg(index,*pd++,PCI_WRITE_DWORD,info); - } - for (i = 0,pb = (uchar*)pd; i < endCount; i++, index++) { - PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info); - } -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c b/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c deleted file mode 100644 index c3a66a7..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c +++ /dev/null @@ -1,306 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Module containing Unix I/O functions. -* -****************************************************************************/ - -#include "pmapi.h" -#include -#include -#include -#include -#include -#include - -/*----------------------------- Implementation ----------------------------*/ - -/* {secret} */ -typedef struct { - DIR *d; - char path[PM_MAX_PATH]; - char mask[PM_MAX_PATH]; - } PM_findHandle; - -/**************************************************************************** -REMARKS: -Internal function to convert the find data to the generic interface. -****************************************************************************/ -static void convertFindData( - PM_findData *findData, - struct dirent *blk, - const char *path) -{ - ulong dwSize = findData->dwSize; - struct stat st; - char filename[PM_MAX_PATH]; - - memset(findData,0,findData->dwSize); - findData->dwSize = dwSize; - strcpy(filename,path); - PM_backslash(filename); - strcat(filename,blk->d_name); - stat(filename,&st); - if (!(st.st_mode & S_IWRITE)) - findData->attrib |= PM_FILE_READONLY; - if (st.st_mode & S_IFDIR) - findData->attrib |= PM_FILE_DIRECTORY; - findData->sizeLo = st.st_size; - findData->sizeHi = 0; - strncpy(findData->name,blk->d_name,PM_MAX_PATH); - findData->name[PM_MAX_PATH-1] = 0; -} - -/**************************************************************************** -REMARKS: -Determines if a file name matches the passed in pattern. -****************************************************************************/ -static ibool filematch( - char *pattern, - char *dirpath, - struct dirent *dire) -{ - struct stat st; - int i = 0,j = 0,lastchar = '\0'; - char fullpath[PM_MAX_PATH]; - - strcpy(fullpath,dirpath); - PM_backslash(fullpath); - strcat(fullpath, dire->d_name); - if (stat(fullpath, &st) != 0) - return false; - for (; i < (int)strlen(dire->d_name) && j < (int)strlen(pattern); i++, j++) { - if (pattern[j] == '*' && lastchar != '\\') { - if (pattern[j+1] == '\0') - return true; - while (dire->d_name[i++] != pattern[j+1]) { - if (dire->d_name[i] == '\0') - return false; - } - i -= 2; - } - else if (dire->d_name[i] != pattern[j] && - !(pattern[j] == '?' && lastchar != '\\')) - return false; - lastchar = pattern[i]; - } - if (j == (int)strlen(pattern) && i == (int)strlen(dire->d_name)) - return true; - return false; -} - -/**************************************************************************** -REMARKS: -Function to find the first file matching a search criteria in a directory. -****************************************************************************/ -void * PMAPI PM_findFirstFile( - const char *filename, - PM_findData *findData) -{ - PM_findHandle *d; - struct dirent *dire; - char name[PM_MAX_PATH]; - char ext[PM_MAX_PATH]; - - if ((d = PM_malloc(sizeof(*d))) == NULL) - return PM_FILE_INVALID; - PM_splitpath(filename,NULL,d->path,name,ext); - strcpy(d->mask,name); - strcat(d->mask,ext); - if (strlen(d->path) == 0) - strcpy(d->path, "."); - if (d->path[strlen(d->path)-1] == '/') - d->path[strlen(d->path)-1] = 0; - if ((d->d = opendir(d->path)) != NULL) { - while ((dire = readdir(d->d)) != NULL) { - if (filematch(d->mask,d->path,dire)) { - convertFindData(findData,dire,d->path); - return d; - } - } - closedir(d->d); - } - PM_free(d); - return PM_FILE_INVALID; -} - -/**************************************************************************** -REMARKS: -Function to find the next file matching a search criteria in a directory. -****************************************************************************/ -ibool PMAPI PM_findNextFile( - void *handle, - PM_findData *findData) -{ - PM_findHandle *d = handle; - struct dirent *dire; - - while ((dire = readdir(d->d)) != NULL) { - if (filematch(d->mask,d->path,dire)) { - convertFindData(findData,dire,d->path); - return true; - } - } - return false; -} - -/**************************************************************************** -REMARKS: -Function to close the find process -****************************************************************************/ -void PMAPI PM_findClose( - void *handle) -{ - PM_findHandle *d = handle; - - closedir(d->d); - free(d); -} - -/**************************************************************************** -REMARKS: -Function to determine if a drive is a valid drive or not. Under Unix this -function will return false for anything except a value of 3 (considered -the root drive, and equivalent to C: for non-Unix systems). The drive -numbering is: - - 1 - Drive A: - 2 - Drive B: - 3 - Drive C: - etc - -****************************************************************************/ -ibool PMAPI PM_driveValid( - char drive) -{ - if (drive == 3) - return true; - return false; -} - -/**************************************************************************** -REMARKS: -Function to get the current working directory for the specififed drive. -Under Unix this will always return the current working directory regardless -of what the value of 'drive' is. -****************************************************************************/ -void PMAPI PM_getdcwd( - int drive, - char *dir, - int len) -{ - (void)drive; - getcwd(dir,len); -} - -/**************************************************************************** -REMARKS: -Function to change the file attributes for a specific file. -****************************************************************************/ -void PMAPI PM_setFileAttr( - const char *filename, - uint attrib) -{ - struct stat st; - mode_t mode; - - stat(filename,&st); - mode = st.st_mode; - if (attrib & PM_FILE_READONLY) - mode &= ~S_IWRITE; - else - mode |= S_IWRITE; - chmod(filename,mode); -} - -/**************************************************************************** -REMARKS: -Function to get the file attributes for a specific file. -****************************************************************************/ -uint PMAPI PM_getFileAttr( - const char *filename) -{ - struct stat st; - - stat(filename,&st); - if (st.st_mode & S_IWRITE) - return 0; - return PM_FILE_READONLY; -} - -/**************************************************************************** -REMARKS: -Function to create a directory. -****************************************************************************/ -ibool PMAPI PM_mkdir( - const char *filename) -{ - return mkdir(filename,0x1FF) == 0; -} - -/**************************************************************************** -REMARKS: -Function to remove a directory. -****************************************************************************/ -ibool PMAPI PM_rmdir( - const char *filename) -{ - return rmdir(filename) == 0; -} - -/**************************************************************************** -REMARKS: -Function to get the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_getFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* TODO: Implement this! */ - (void)filename; - (void)gmTime; - (void)time; - PM_fatalError("PM_getFileTime not implemented yet!"); - return false; -} - -/**************************************************************************** -REMARKS: -Function to set the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_setFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* TODO: Implement this! */ - (void)filename; - (void)gmTime; - (void)time; - PM_fatalError("PM_setFileTime not implemented yet!"); - return false; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c b/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c deleted file mode 100644 index 8056e9a..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c +++ /dev/null @@ -1,377 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Portions copyright (C) Josh Vanderhoof -* -* Language: ANSI C -* Environment: Any -* -* Description: Functions to save and restore the VGA hardware state. -* -****************************************************************************/ - -#include "pmapi.h" -#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) -#include "sdd/sddhelp.h" -#else -#include -#endif - -/*--------------------------- Global variables ----------------------------*/ - -/* VGA index register ports */ -#define CRT_I 0x3D4 /* CRT Controller Index */ -#define ATT_IW 0x3C0 /* Attribute Controller Index & Data */ -#define GRA_I 0x3CE /* Graphics Controller Index */ -#define SEQ_I 0x3C4 /* Sequencer Index */ - -/* VGA data register ports */ -#define CRT_D 0x3D5 /* CRT Controller Data Register */ -#define ATT_R 0x3C1 /* Attribute Controller Data Read Register */ -#define GRA_D 0x3CF /* Graphics Controller Data Register */ -#define SEQ_D 0x3C5 /* Sequencer Data Register */ -#define MIS_R 0x3CC /* Misc Output Read Register */ -#define MIS_W 0x3C2 /* Misc Output Write Register */ -#define IS1_R 0x3DA /* Input Status Register 1 */ -#define PEL_IW 0x3C8 /* PEL Write Index */ -#define PEL_IR 0x3C7 /* PEL Read Index */ -#define PEL_D 0x3C9 /* PEL Data Register */ - -/* standard VGA indexes max counts */ -#define CRT_C 24 /* 24 CRT Controller Registers */ -#define ATT_C 21 /* 21 Attribute Controller Registers */ -#define GRA_C 9 /* 9 Graphics Controller Registers */ -#define SEQ_C 5 /* 5 Sequencer Registers */ -#define MIS_C 1 /* 1 Misc Output Register */ -#define PAL_C 768 /* 768 Palette Registers */ -#define FONT_C 8192 /* Total size of character generator RAM */ - -/* VGA registers saving indexes */ -#define CRT 0 /* CRT Controller Registers start */ -#define ATT (CRT+CRT_C) /* Attribute Controller Registers start */ -#define GRA (ATT+ATT_C) /* Graphics Controller Registers start */ -#define SEQ (GRA+GRA_C) /* Sequencer Registers */ -#define MIS (SEQ+SEQ_C) /* General Registers */ -#define PAL (MIS+MIS_C) /* VGA Palette Registers */ -#define FONT (PAL+PAL_C) /* VGA font data */ - -/* Macros for port I/O with arguments reversed */ - -#define _port_out(v,p) PM_outpb(p,(uchar)(v)) -#define _port_in(p) PM_inpb(p) - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Returns the size of the VGA state buffer. -****************************************************************************/ -int PMAPI PM_getVGAStateSize(void) -{ - return CRT_C + ATT_C + GRA_C + SEQ_C + MIS_C + PAL_C + FONT_C; -} - -/**************************************************************************** -REMARKS: -Delay for a short period of time. -****************************************************************************/ -static void vga_delay(void) -{ - int i; - - /* For the loop here we program the POST register. The length of this - * delay is dependant only on ISA bus speed, but it is enough for - * what we need. - */ - for (i = 0; i <= 10; i++) - PM_outpb(0x80, 0); -} - -/**************************************************************************** -PARAMETERS: -port - I/O port to read value from -index - Port index to read - -RETURNS: -Byte read from 'port' register 'index'. -****************************************************************************/ -static ushort vga_rdinx( - ushort port, - ushort index) -{ - PM_outpb(port,(uchar)index); - return PM_inpb(port+1); -} - -/**************************************************************************** -PARAMETERS: -port - I/O port to write to -index - Port index to write -value - Byte to write to port - -REMARKS: -Writes a byte value to the 'port' register 'index'. -****************************************************************************/ -static void vga_wrinx( - ushort port, - ushort index, - ushort value) -{ - PM_outpb(port,(uchar)index); - PM_outpb(port+1,(uchar)value); -} - -/**************************************************************************** -REMARKS: -Save the color palette values -****************************************************************************/ -static void vga_savepalette( - uchar *pal) -{ - int i; - - _port_out(0, PEL_IR); - for (i = 0; i < 768; i++) { - vga_delay(); - *pal++ = _port_in(PEL_D); - } -} - -/**************************************************************************** -REMARKS: -Restore the color palette values -****************************************************************************/ -static void vga_restorepalette( - const uchar *pal) -{ - int i; - - /* restore saved palette */ - _port_out(0, PEL_IW); - for (i = 0; i < 768; i++) { - vga_delay(); - _port_out(*pal++, PEL_D); - } -} - -/**************************************************************************** -REMARKS: -Read the font data from the VGA character generator RAM -****************************************************************************/ -static void vga_saveFont( - uchar *data) -{ - uchar *A0000Ptr = PM_getA0000Pointer(); - uchar save[7]; - - /* Enable access to character generator RAM */ - save[0] = (uchar)vga_rdinx(SEQ_I,0x00); - save[1] = (uchar)vga_rdinx(SEQ_I,0x02); - save[2] = (uchar)vga_rdinx(SEQ_I,0x04); - save[3] = (uchar)vga_rdinx(SEQ_I,0x00); - save[4] = (uchar)vga_rdinx(GRA_I,0x04); - save[5] = (uchar)vga_rdinx(GRA_I,0x05); - save[6] = (uchar)vga_rdinx(GRA_I,0x06); - vga_wrinx(SEQ_I,0x00,0x01); - vga_wrinx(SEQ_I,0x02,0x04); - vga_wrinx(SEQ_I,0x04,0x07); - vga_wrinx(SEQ_I,0x00,0x03); - vga_wrinx(GRA_I,0x04,0x02); - vga_wrinx(GRA_I,0x05,0x00); - vga_wrinx(GRA_I,0x06,0x00); - - /* Copy character generator RAM */ - memcpy(data,A0000Ptr,FONT_C); - - /* Restore VGA state */ - vga_wrinx(SEQ_I,0x00,save[0]); - vga_wrinx(SEQ_I,0x02,save[1]); - vga_wrinx(SEQ_I,0x04,save[2]); - vga_wrinx(SEQ_I,0x00,save[3]); - vga_wrinx(GRA_I,0x04,save[4]); - vga_wrinx(GRA_I,0x05,save[5]); - vga_wrinx(GRA_I,0x06,save[6]); -} - -/**************************************************************************** -REMARKS: -Downloads the font data to the VGA character generator RAM -****************************************************************************/ -static void vga_restoreFont( - const uchar *data) -{ - uchar *A0000Ptr = PM_getA0000Pointer(); - - /* Enable access to character generator RAM */ - vga_wrinx(SEQ_I,0x00,0x01); - vga_wrinx(SEQ_I,0x02,0x04); - vga_wrinx(SEQ_I,0x04,0x07); - vga_wrinx(SEQ_I,0x00,0x03); - vga_wrinx(GRA_I,0x04,0x02); - vga_wrinx(GRA_I,0x05,0x00); - vga_wrinx(GRA_I,0x06,0x00); - - /* Copy font back to character generator RAM */ - memcpy(A0000Ptr,data,FONT_C); -} - -/**************************************************************************** -REMARKS: -Save the state of all VGA compatible registers -****************************************************************************/ -void PMAPI PM_saveVGAState( - void *stateBuf) -{ - uchar *regs = stateBuf; - int i; - - /* Save state of VGA registers */ - for (i = 0; i < CRT_C; i++) { - _port_out(i, CRT_I); - regs[CRT + i] = _port_in(CRT_D); - } - for (i = 0; i < ATT_C; i++) { - _port_in(IS1_R); - vga_delay(); - _port_out(i, ATT_IW); - vga_delay(); - regs[ATT + i] = _port_in(ATT_R); - vga_delay(); - } - for (i = 0; i < GRA_C; i++) { - _port_out(i, GRA_I); - regs[GRA + i] = _port_in(GRA_D); - } - for (i = 0; i < SEQ_C; i++) { - _port_out(i, SEQ_I); - regs[SEQ + i] = _port_in(SEQ_D); - } - regs[MIS] = _port_in(MIS_R); - - /* Save the VGA palette values */ - vga_savepalette(®s[PAL]); - - /* Save the VGA character generator RAM */ - vga_saveFont(®s[FONT]); - - /* Turn the VGA display back on */ - PM_vgaUnblankDisplay(); -} - -/**************************************************************************** -REMARKS: -Retore the state of all VGA compatible registers -****************************************************************************/ -void PMAPI PM_restoreVGAState( - const void *stateBuf) -{ - const uchar *regs = stateBuf; - int i; - - /* Blank the display before we start the restore */ - PM_vgaBlankDisplay(); - - /* Restore the VGA character generator RAM */ - vga_restoreFont(®s[FONT]); - - /* Restore the VGA palette values */ - vga_restorepalette(®s[PAL]); - - /* Restore the state of the VGA compatible registers */ - _port_out(regs[MIS], MIS_W); - - /* Delay to allow clock change to settle */ - for (i = 0; i < 10; i++) - vga_delay(); - - /* Synchronous reset on */ - _port_out(0x00,SEQ_I); - _port_out(0x01,SEQ_D); - - /* Write seqeuencer registers */ - _port_out(1, SEQ_I); - _port_out(regs[SEQ + 1] | 0x20, SEQ_D); - for (i = 2; i < SEQ_C; i++) { - _port_out(i, SEQ_I); - _port_out(regs[SEQ + i], SEQ_D); - } - - /* Synchronous reset off */ - _port_out(0x00,SEQ_I); - _port_out(0x03,SEQ_D); - - /* Deprotect CRT registers 0-7 and write CRTC */ - _port_out(0x11, CRT_I); - _port_out(_port_in(CRT_D) & 0x7F, CRT_D); - for (i = 0; i < CRT_C; i++) { - _port_out(i, CRT_I); - _port_out(regs[CRT + i], CRT_D); - } - for (i = 0; i < GRA_C; i++) { - _port_out(i, GRA_I); - _port_out(regs[GRA + i], GRA_D); - } - for (i = 0; i < ATT_C; i++) { - _port_in(IS1_R); /* reset flip-flop */ - vga_delay(); - _port_out(i, ATT_IW); - vga_delay(); - _port_out(regs[ATT + i], ATT_IW); - vga_delay(); - } - - /* Ensure the VGA screen is turned on */ - PM_vgaUnblankDisplay(); -} - -/**************************************************************************** -REMARKS: -Disables the VGA display for screen output making it blank. -****************************************************************************/ -void PMAPI PM_vgaBlankDisplay(void) -{ - /* Turn screen off */ - _port_out(0x01, SEQ_I); - _port_out(_port_in(SEQ_D) | 0x20, SEQ_D); - - /* Disable video output */ - _port_in(IS1_R); - vga_delay(); - _port_out(0x00, ATT_IW); -} - -/**************************************************************************** -REMARKS: -Enables the VGA display for screen output. -****************************************************************************/ -void PMAPI PM_vgaUnblankDisplay(void) -{ - /* Turn screen back on */ - _port_out(0x01, SEQ_I); - _port_out(_port_in(SEQ_D) & 0xDF, SEQ_D); - - /* Enable video output */ - _port_in(IS1_R); - vga_delay(); - _port_out(0x20, ATT_IW); -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c deleted file mode 100644 index ac62e81..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c +++ /dev/null @@ -1,808 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Main module to implement the Zen Timer support functions. -* -****************************************************************************/ - -#include "ztimer.h" -#include "pmapi.h" -#include "oshdr.h" -#if !defined(__WIN32_VXD__) && !defined(__OS2_VDD__) && !defined(__NT_DRIVER__) -#include -#include -#endif - -/*----------------------------- Implementation ----------------------------*/ - -/* External Intel assembler functions */ -#ifdef __INTEL__ -/* {secret} */ -ibool _ASMAPI _CPU_haveCPUID(void); -/* {secret} */ -ibool _ASMAPI _CPU_check80386(void); -/* {secret} */ -ibool _ASMAPI _CPU_check80486(void); -/* {secret} */ -uint _ASMAPI _CPU_checkCPUID(void); -/* {secret} */ -uint _ASMAPI _CPU_getCPUIDModel(void); -/* {secret} */ -uint _ASMAPI _CPU_getCPUIDStepping(void); -/* {secret} */ -uint _ASMAPI _CPU_getCPUIDFeatures(void); -/* {secret} */ -uint _ASMAPI _CPU_getCacheSize(void); -/* {secret} */ -uint _ASMAPI _CPU_have3DNow(void); -/* {secret} */ -ibool _ASMAPI _CPU_checkClone(void); -/* {secret} */ -void _ASMAPI _CPU_readTimeStamp(CPU_largeInteger *time); -/* {secret} */ -void _ASMAPI _CPU_runBSFLoop(ulong iterations); -/* {secret} */ -ulong _ASMAPI _CPU_mulDiv(ulong a,ulong b,ulong c); -/* {secret} */ -void ZTimerQuickInit(void); -#define CPU_HaveMMX 0x00800000 -#define CPU_HaveRDTSC 0x00000010 -#define CPU_HaveSSE 0x02000000 -#endif - -#if defined(__SMX32__) -#include "smx/cpuinfo.c" -#elif defined(__RTTARGET__) -#include "rttarget/cpuinfo.c" -#elif defined(__REALDOS__) -#include "dos/cpuinfo.c" -#elif defined(__NT_DRIVER__) -#include "ntdrv/cpuinfo.c" -#elif defined(__WIN32_VXD__) -#include "vxd/cpuinfo.c" -#elif defined(__WINDOWS32__) -#include "win32/cpuinfo.c" -#elif defined(__OS2_VDD__) -#include "vdd/cpuinfo.c" -#elif defined(__OS2__) -#include "os2/cpuinfo.c" -#elif defined(__LINUX__) -#include "linux/cpuinfo.c" -#elif defined(__QNX__) -#include "qnx/cpuinfo.c" -#elif defined(__BEOS__) -#include "beos/cpuinfo.c" -#else -#error CPU library not ported to this platform yet! -#endif - -/*------------------------ Public interface routines ----------------------*/ - -/**************************************************************************** -REMARKS: -Read an I/O port location. -****************************************************************************/ -static uchar rdinx( - int port, - int index) -{ - PM_outpb(port,(uchar)index); - return PM_inpb(port+1); -} - -/**************************************************************************** -REMARKS: -Write an I/O port location. -****************************************************************************/ -static void wrinx( - ushort port, - ushort index, - ushort value) -{ - PM_outpb(port,(uchar)index); - PM_outpb(port+1,(uchar)value); -} - -/**************************************************************************** -REMARKS: -Enables the Cyrix CPUID instruction to properly detect MediaGX and 6x86 -processors. -****************************************************************************/ -static void _CPU_enableCyrixCPUID(void) -{ - uchar ccr3; - - PM_init(); - ccr3 = rdinx(0x22,0xC3); - wrinx(0x22,0xC3,(uchar)(ccr3 | 0x10)); - wrinx(0x22,0xE8,(uchar)(rdinx(0x22,0xE8) | 0x80)); - wrinx(0x22,0xC3,ccr3); -} - -/**************************************************************************** -DESCRIPTION: -Returns the type of processor in the system. - -HEADER: -ztimer.h - -RETURNS: -Numerical identifier for the installed processor - -REMARKS: -Returns the type of processor in the system. Note that if the CPU is an -unknown Pentium family processor that we don't have an enumeration for, -the return value will be greater than or equal to the value of CPU_UnkPentium -(depending on the value returned by the CPUID instruction). - -SEE ALSO: -CPU_getProcessorSpeed, CPU_haveMMX, CPU_getProcessorName -****************************************************************************/ -uint ZAPI CPU_getProcessorType(void) -{ -#if defined(__INTEL__) - uint cpu,vendor,model,cacheSize; - static ibool firstTime = true; - - if (_CPU_haveCPUID()) { - cpu = _CPU_checkCPUID(); - vendor = cpu & ~CPU_mask; - if (vendor == CPU_Intel) { - /* Check for Intel processors */ - switch (cpu & CPU_mask) { - case 4: cpu = CPU_i486; break; - case 5: cpu = CPU_Pentium; break; - case 6: - if ((model = _CPU_getCPUIDModel()) == 1) - cpu = CPU_PentiumPro; - else if (model <= 6) { - cacheSize = _CPU_getCacheSize(); - if ((model == 5 && cacheSize == 0) || - (model == 5 && cacheSize == 256) || - (model == 6 && cacheSize == 128)) - cpu = CPU_Celeron; - else - cpu = CPU_PentiumII; - } - else if (model >= 7) { - /* Model 7 == Pentium III */ - /* Model 8 == Celeron/Pentium III Coppermine */ - cacheSize = _CPU_getCacheSize(); - if ((model == 8 && cacheSize == 128)) - cpu = CPU_Celeron; - else - cpu = CPU_PentiumIII; - } - break; - default: - cpu = CPU_UnkIntel; - } - } - else if (vendor == CPU_Cyrix) { - /* Check for Cyrix processors */ - switch (cpu & CPU_mask) { - case 4: - if ((model = _CPU_getCPUIDModel()) == 4) - cpu = CPU_CyrixMediaGX; - else - cpu = CPU_UnkCyrix; - break; - case 5: - if ((model = _CPU_getCPUIDModel()) == 2) - cpu = CPU_Cyrix6x86; - else if (model == 4) - cpu = CPU_CyrixMediaGXm; - else - cpu = CPU_UnkCyrix; - break; - case 6: - if ((model = _CPU_getCPUIDModel()) <= 1) - cpu = CPU_Cyrix6x86MX; - else - cpu = CPU_UnkCyrix; - break; - default: - cpu = CPU_UnkCyrix; - } - } - else if (vendor == CPU_AMD) { - /* Check for AMD processors */ - switch (cpu & CPU_mask) { - case 4: - if ((model = _CPU_getCPUIDModel()) == 0) - cpu = CPU_AMDAm5x86; - else - cpu = CPU_AMDAm486; - break; - case 5: - if ((model = _CPU_getCPUIDModel()) <= 3) - cpu = CPU_AMDK5; - else if (model <= 7) - cpu = CPU_AMDK6; - else if (model == 8) - cpu = CPU_AMDK6_2; - else if (model == 9) - cpu = CPU_AMDK6_III; - else if (model == 13) { - if (_CPU_getCPUIDStepping() <= 3) - cpu = CPU_AMDK6_IIIplus; - else - cpu = CPU_AMDK6_2plus; - } - else - cpu = CPU_UnkAMD; - break; - case 6: - if ((model = _CPU_getCPUIDModel()) == 3) - cpu = CPU_AMDDuron; - else - cpu = CPU_AMDAthlon; - break; - default: - cpu = CPU_UnkAMD; - } - } - else if (vendor == CPU_IDT) { - /* Check for IDT WinChip processors */ - switch (cpu & CPU_mask) { - case 5: - if ((model = _CPU_getCPUIDModel()) <= 4) - cpu = CPU_WinChipC6; - else if (model == 8) - cpu = CPU_WinChip2; - else - cpu = CPU_UnkIDT; - break; - default: - cpu = CPU_UnkIDT; - } - } - else { - /* Assume a Pentium compatible Intel clone */ - cpu = CPU_Pentium; - } - return cpu | vendor | (_CPU_getCPUIDStepping() << CPU_steppingShift); - } - else { - if (_CPU_check80386()) - cpu = CPU_i386; - else if (_CPU_check80486()) { - /* If we get here we may have a Cyrix processor so we can try - * enabling the CPUID instruction and trying again. - */ - if (firstTime) { - firstTime = false; - _CPU_enableCyrixCPUID(); - return CPU_getProcessorType(); - } - cpu = CPU_i486; - } - else - cpu = CPU_Pentium; - if (!_CPU_checkClone()) - return cpu | CPU_Intel; - return cpu; - } -#elif defined(__ALPHA__) - return CPU_Alpha; -#elif defined(__MIPS__) - return CPU_Mips; -#elif defined(__PPC__) - return CPU_PowerPC; -#endif -} - -/**************************************************************************** -DESCRIPTION: -Returns true if the processor supports Intel MMX extensions. - -HEADER: -ztimer.h - -RETURNS: -True if MMX is available, false if not. - -REMARKS: -This function determines if the processor supports the Intel MMX extended -instruction set. - -SEE ALSO: -CPU_getProcessorType, CPU_getProcessorSpeed, CPU_have3DNow, CPU_haveSSE, -CPU_getProcessorName -****************************************************************************/ -ibool ZAPI CPU_haveMMX(void) -{ -#ifdef __INTEL__ - if (_CPU_haveCPUID()) - return (_CPU_getCPUIDFeatures() & CPU_HaveMMX) != 0; - return false; -#else - return false; -#endif -} - -/**************************************************************************** -DESCRIPTION: -Returns true if the processor supports AMD 3DNow! extensions. - -HEADER: -ztimer.h - -RETURNS: -True if 3DNow! is available, false if not. - -REMARKS: -This function determines if the processor supports the AMD 3DNow! extended -instruction set. - -SEE ALSO: -CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_haveSSE, -CPU_getProcessorName -****************************************************************************/ -ibool ZAPI CPU_have3DNow(void) -{ -#ifdef __INTEL__ - if (_CPU_haveCPUID()) - return _CPU_have3DNow(); - return false; -#else - return false; -#endif -} - -/**************************************************************************** -DESCRIPTION: -Returns true if the processor supports Intel KNI extensions. - -HEADER: -ztimer.h - -RETURNS: -True if Intel KNI is available, false if not. - -REMARKS: -This function determines if the processor supports the Intel KNI extended -instruction set. - -SEE ALSO: -CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_have3DNow, -CPU_getProcessorName -****************************************************************************/ -ibool ZAPI CPU_haveSSE(void) -{ -#ifdef __INTEL__ - if (_CPU_haveCPUID()) - return (_CPU_getCPUIDFeatures() & CPU_HaveSSE) != 0; - return false; -#else - return false; -#endif -} - -/**************************************************************************** -RETURNS: -True if the RTSC instruction is available, false if not. - -REMARKS: -This function determines if the processor supports the Intel RDTSC -instruction, for high precision timing. If the processor is not an Intel or -Intel clone CPU, this function will always return false. - -DESCRIPTION: -Returns true if the processor supports RDTSC extensions. - -HEADER: -ztimer.h - -RETURNS: -True if RTSC is available, false if not. - -REMARKS: -This function determines if the processor supports the RDTSC instruction -for reading the processor time stamp counter. - -SEE ALSO: -CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_have3DNow, -CPU_getProcessorName -****************************************************************************/ -ibool ZAPI CPU_haveRDTSC(void) -{ -#ifdef __INTEL__ - if (_CPU_haveCPUID()) - return (_CPU_getCPUIDFeatures() & CPU_HaveRDTSC) != 0; - return false; -#else - return false; -#endif -} - -#ifdef __INTEL__ - -#define ITERATIONS 16000 -#define SAMPLINGS 2 -#define INNER_LOOPS 400 - -/**************************************************************************** -REMARKS: -If processor does not support time stamp reading, but is at least a 386 or -above, utilize method of timing a loop of BSF instructions which take a -known number of cycles to run on i386(tm), i486(tm), and Pentium(R) -processors. -****************************************************************************/ -static ulong GetBSFCpuSpeed( - ulong cycles) -{ - CPU_largeInteger t0,t1,count_freq; - ulong ticks; /* Microseconds elapsed during test */ - ulong current; /* Variable to store time elapsed */ - int i,j,iPriority; - ulong lowest = (ulong)-1; - - iPriority = SetMaxThreadPriority(); - GetCounterFrequency(&count_freq); - for (i = 0; i < SAMPLINGS; i++) { - GetCounter(&t0); - for (j = 0; j < INNER_LOOPS; j++) - _CPU_runBSFLoop(ITERATIONS); - GetCounter(&t1); - current = t1.low - t0.low; - if (current < lowest) - lowest = current; - } - RestoreThreadPriority(iPriority); - - /* Compute frequency */ - ticks = _CPU_mulDiv(lowest,1000000,count_freq.low); - if ((ticks % count_freq.low) > (count_freq.low/2)) - ticks++; /* Round up if necessary */ - if (ticks == 0) - return 0; - return ((cycles*INNER_LOOPS)/ticks); -} - -#define TOLERANCE 1 - -/**************************************************************************** -REMARKS: -On processors supporting the Read Time Stamp opcode, compare elapsed -time on the High-Resolution Counter with elapsed cycles on the Time -Stamp Register. - -The inner loop runs up to 20 times oruntil the average of the previous -three calculated frequencies is within 1 MHz of each of the individual -calculated frequencies. This resampling increases the accuracy of the -results since outside factors could affect this calculation. -****************************************************************************/ -static ulong GetRDTSCCpuSpeed( - ibool accurate) -{ - CPU_largeInteger t0,t1,s0,s1,count_freq; - u64 stamp0, stamp1, ticks0, ticks1; - u64 total_cycles, cycles, hz, freq; - u64 total_ticks, ticks; - int tries,iPriority; - ulong maxCount; - - PM_set64_32(total_cycles,0); - PM_set64_32(total_ticks,0); - maxCount = accurate ? 600000 : 30000; - iPriority = SetMaxThreadPriority(); - GetCounterFrequency(&count_freq); - PM_set64(freq,count_freq.high,count_freq.low); - for (tries = 0; tries < 3; tries++) { - /* Loop until 100 ticks have passed since last read of hi-res - * counter. This accounts for overhead later. - */ - GetCounter(&t0); - t1.low = t0.low; - t1.high = t0.high; - while ((t1.low - t0.low) < 100) { - GetCounter(&t1); - _CPU_readTimeStamp(&s0); - } - - /* Loop until 30000 ticks have passed since last read of hi-res counter. - * This allows for elapsed time for sampling. For a hi-res frequency - * of 1MHz, this is about 0.03 of a second. The frequency reported - * by the OS dependent code should be tuned to provide a good - * sample period depending on the accuracy of the OS timers (ie: - * if the accuracy is lower, lower the frequency to spend more time - * in the inner loop to get better accuracy). - */ - t0.low = t1.low; - t0.high = t1.high; - while ((t1.low - t0.low) < maxCount) { - GetCounter(&t1); - _CPU_readTimeStamp(&s1); - } - - /* Find the difference during the timing loop */ - PM_set64(stamp0,s0.high,s0.low); - PM_set64(stamp1,s1.high,s1.low); - PM_set64(ticks0,t0.high,t0.low); - PM_set64(ticks1,t1.high,t1.low); - PM_sub64(cycles,stamp1,stamp0); - PM_sub64(ticks,ticks1,ticks0); - - /* Sum up the results */ - PM_add64(total_ticks,total_ticks,ticks); - PM_add64(total_cycles,total_cycles,cycles); - } - RestoreThreadPriority(iPriority); - - /* Compute frequency in Hz */ - PM_mul64(hz,total_cycles,freq); - PM_div64(hz,hz,total_ticks); - return PM_64to32(hz); -} - -#endif /* __INTEL__ */ - -/**************************************************************************** -DESCRIPTION: -Returns the speed of the processor in MHz. - -HEADER: -ztimer.h - -PARAMETERS: -accurate - True of the speed should be measured accurately - -RETURNS: -Processor speed in MHz. - -REMARKS: -This function returns the speed of the CPU in MHz. Note that if the speed -cannot be determined, this function will return 0. - -If the accurate parameter is set to true, this function will spend longer -profiling the speed of the CPU, and will not round the CPU speed that is -reported. This is important for highly accurate timing using the Pentium -RDTSC instruction, but it does take a lot longer for the profiling to -produce accurate results. - -SEE ALSO: -CPU_getProcessorSpeedInHz, CPU_getProcessorType, CPU_haveMMX, -CPU_getProcessorName -****************************************************************************/ -ulong ZAPI CPU_getProcessorSpeed( - ibool accurate) -{ -#if defined(__INTEL__) - /* Number of cycles needed to execute a single BSF instruction on i386+ - * processors. - */ - ulong cpuSpeed; - uint i; - static ulong intel_cycles[] = { - 115,47,43, - }; - static ulong cyrix_cycles[] = { - 38,38,52,52, - }; - static ulong amd_cycles[] = { - 49, - }; - static ulong known_speeds[] = { - 1000,950,900,850,800,750,700,650,600,550,500,450,433,400,350, - 333,300,266,233,200,166,150,133,120,100,90,75,66,60,50,33,20,0, - }; - - if (CPU_haveRDTSC()) { - cpuSpeed = (GetRDTSCCpuSpeed(accurate) + 500000) / 1000000; - } - else { - int type = CPU_getProcessorType(); - int processor = type & CPU_mask; - int vendor = type & CPU_familyMask; - if (vendor == CPU_Intel) - cpuSpeed = GetBSFCpuSpeed(ITERATIONS * intel_cycles[processor - CPU_i386]); - else if (vendor == CPU_Cyrix) - cpuSpeed = GetBSFCpuSpeed(ITERATIONS * cyrix_cycles[processor - CPU_Cyrix6x86]); - else if (vendor == CPU_AMD) - cpuSpeed = GetBSFCpuSpeed(ITERATIONS * amd_cycles[0]); - else - return 0; - } - - /* Now normalise the results given known processors speeds, if the - * speed we measure is within 2MHz of the expected values - */ - if (!accurate) { - for (i = 0; known_speeds[i] != 0; i++) { - if (cpuSpeed >= (known_speeds[i]-3) && cpuSpeed <= (known_speeds[i]+3)) { - return known_speeds[i]; - } - } - } - return cpuSpeed; -#else - return 0; -#endif -} - -/**************************************************************************** -DESCRIPTION: -Returns the speed of the processor in Hz. - -HEADER: -ztimer.h - -RETURNS: -Accurate processor speed in Hz. - -REMARKS: -This function returns the accurate speed of the CPU in Hz. Note that if the -speed cannot be determined, this function will return 0. - -This function is similar to the CPU_getProcessorSpeed function, except that -it attempts to accurately measure the CPU speed in Hz. This is used -internally in the Zen Timer libraries to provide accurate real world timing -information. This is important for highly accurate timing using the Pentium -RDTSC instruction, but it does take a lot longer for the profiling to -produce accurate results. - -SEE ALSO: -CPU_getProcessorSpeed, CPU_getProcessorType, CPU_haveMMX, -CPU_getProcessorName -****************************************************************************/ -ulong ZAPI CPU_getProcessorSpeedInHZ( - ibool accurate) -{ -#if defined(__INTEL__) - if (CPU_haveRDTSC()) { - return GetRDTSCCpuSpeed(accurate); - } - return CPU_getProcessorSpeed(false) * 1000000; -#else - return 0; -#endif -} - -/**************************************************************************** -DESCRIPTION: -Returns a string defining the speed and name of the processor. - -HEADER: -ztimer.h - -RETURNS: -Processor name string. - -REMARKS: -This function returns an English string describing the speed and name of the -CPU. - -SEE ALSO: -CPU_getProcessorType, CPU_haveMMX, CPU_getProcessorName -****************************************************************************/ -char * ZAPI CPU_getProcessorName(void) -{ -#if defined(__INTEL__) - static int cpu,speed = -1; - static char name[80]; - - if (speed == -1) { - cpu = CPU_getProcessorType(); - speed = CPU_getProcessorSpeed(false); - } - sprintf(name,"%d MHz ", speed); - switch (cpu & CPU_mask) { - case CPU_i386: - strcat(name,"Intel i386 processor"); - break; - case CPU_i486: - strcat(name,"Intel i486 processor"); - break; - case CPU_Pentium: - strcat(name,"Intel Pentium processor"); - break; - case CPU_PentiumPro: - strcat(name,"Intel Pentium Pro processor"); - break; - case CPU_PentiumII: - strcat(name,"Intel Pentium II processor"); - break; - case CPU_Celeron: - strcat(name,"Intel Celeron processor"); - break; - case CPU_PentiumIII: - strcat(name,"Intel Pentium III processor"); - break; - case CPU_UnkIntel: - strcat(name,"Unknown Intel processor"); - break; - case CPU_Cyrix6x86: - strcat(name,"Cyrix 6x86 processor"); - break; - case CPU_Cyrix6x86MX: - strcat(name,"Cyrix 6x86MX processor"); - break; - case CPU_CyrixMediaGX: - strcat(name,"Cyrix MediaGX processor"); - break; - case CPU_CyrixMediaGXm: - strcat(name,"Cyrix MediaGXm processor"); - break; - case CPU_UnkCyrix: - strcat(name,"Unknown Cyrix processor"); - break; - case CPU_AMDAm486: - strcat(name,"AMD Am486 processor"); - break; - case CPU_AMDAm5x86: - strcat(name,"AMD Am5x86 processor"); - break; - case CPU_AMDK5: - strcat(name,"AMD K5 processor"); - break; - case CPU_AMDK6: - strcat(name,"AMD K6 processor"); - break; - case CPU_AMDK6_2: - strcat(name,"AMD K6-2 processor"); - break; - case CPU_AMDK6_III: - strcat(name,"AMD K6-III processor"); - break; - case CPU_AMDK6_2plus: - strcat(name,"AMD K6-2+ processor"); - break; - case CPU_AMDK6_IIIplus: - strcat(name,"AMD K6-III+ processor"); - break; - case CPU_UnkAMD: - strcat(name,"Unknown AMD processor"); - break; - case CPU_AMDAthlon: - strcat(name,"AMD Athlon processor"); - break; - case CPU_AMDDuron: - strcat(name,"AMD Duron processor"); - break; - case CPU_WinChipC6: - strcat(name,"IDT WinChip C6 processor"); - break; - case CPU_WinChip2: - strcat(name,"IDT WinChip 2 processor"); - break; - case CPU_UnkIDT: - strcat(name,"Unknown IDT processor"); - break; - default: - strcat(name,"Unknown processor"); - } - if (CPU_haveMMX()) - strcat(name," with MMX(R)"); - if (CPU_have3DNow()) - strcat(name,", 3DNow!(R)"); - if (CPU_haveSSE()) - strcat(name,", SSE(R)"); - return name; -#else - return "Unknown"; -#endif -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/debug.c b/board/MAI/bios_emulator/scitech/src/pm/debug.c deleted file mode 100644 index 751bf09..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/debug.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Main module containing debug checking features. -* -****************************************************************************/ - -#include "pmapi.h" -#ifdef __WIN32_VXD__ -#include "vxdfile.h" -#elif defined(__NT_DRIVER__) -#include "ntdriver.h" -#elif defined(__OS2_VDD__) -#include "vddfile.h" -#else -#include -#include -#include -#endif - -/*---------------------------- Global variables ---------------------------*/ - -/* {secret} */ -void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line) = _CHK_defaultFail; -static char logFile[256] = ""; - -/*----------------------------- Implementation ----------------------------*/ - -#ifdef CHECKED -void _CHK_defaultFail( - int fatal, - const char *msg, - const char *cond, - const char *file, - int line) -{ - FILE *f; - char buf[256]; - - if (logFile[0] == 0) { - strcpy(logFile,PM_getNucleusPath()); - PM_backslash(logFile); - strcat(logFile,"scitech.log"); - } - if ((f = fopen(logFile,"a+")) != NULL) { -#if defined(__WIN32_VXD__) || defined(__OS2_VDD__) || defined(__NT_DRIVER__) - sprintf(buf,msg,cond,file,line); - fwrite(buf,1,strlen(buf),f); -#else - fprintf(f,msg,cond,file,line); -#endif - fclose(f); - } - if (fatal) { - sprintf(buf,"Check failed: check '%s' for details", logFile); - PM_fatalError(buf); - } -} -#endif - -/**************************************************************************** -DESCRIPTION: -Sets the location of the debug log file. - -HEADER: -pmapi.h - -PARAMETERS: -logFilePath - Full file and path name to debug log file. - -REMARKS: -Sets the name and location of the debug log file. The debug log file is -created and written to when runtime checks, warnings and failure conditions -are logged to disk when code is compiled in CHECKED mode. By default the -log file is called 'scitech.log' and goes into the current SciTech Nucleus -path for the application. You can use this function to set the filename -and location of the debug log file to your own application specific -directory. -****************************************************************************/ -void PMAPI PM_setDebugLog( - const char *logFilePath) -{ - strcpy(logFile,logFilePath); -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm deleted file mode 100644 index 36dcaab..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm +++ /dev/null @@ -1,194 +0,0 @@ -;**************************************************************************** -;* -;* SciTech Multi-platform Graphics Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler -;* Environment: IBM PC (MS DOS) -;* -;* Description: Assembly language support routines for the event module. -;* -;**************************************************************************** - - ideal - -include "scitech.mac" ; Memory model macros - -ifdef flatmodel - -header _event ; Set up memory model - -begdataseg _event - - cextern _EVT_biosPtr,DPTR - -ifdef USE_NASM -%define KB_HEAD WORD esi+01Ah ; Keyboard buffer head in BIOS data area -%define KB_TAIL WORD esi+01Ch ; Keyboard buffer tail in BIOS data area -%define KB_START WORD esi+080h ; Start of keyboard buffer in BIOS data area -%define KB_END WORD esi+082h ; End of keyboard buffer in BIOS data area -else -KB_HEAD EQU WORD esi+01Ah ; Keyboard buffer head in BIOS data area -KB_TAIL EQU WORD esi+01Ch ; Keyboard buffer tail in BIOS data area -KB_START EQU WORD esi+080h ; Start of keyboard buffer in BIOS data area -KB_END EQU WORD esi+082h ; End of keyboard buffer in BIOS data area -endif - -enddataseg _event - -begcodeseg _event ; Start of code segment - - cpublic _EVT_codeStart - -;---------------------------------------------------------------------------- -; int _EVT_getKeyCode(void) -;---------------------------------------------------------------------------- -; Returns the key code for the next available key by extracting it from -; the BIOS keyboard buffer. -;---------------------------------------------------------------------------- -cprocstart _EVT_getKeyCode - - enter_c - - mov esi,[_EVT_biosPtr] - xor ebx,ebx - xor eax,eax - mov bx,[KB_HEAD] - cmp bx,[KB_TAIL] - jz @@Done - xor eax,eax - mov ax,[esi+ebx] ; EAX := character from keyboard buffer - inc _bx - inc _bx - cmp bx,[KB_END] ; Hit the end of the keyboard buffer? - jl @@1 - mov bx,[KB_START] -@@1: mov [KB_HEAD],bx ; Update keyboard buffer head pointer - -@@Done: leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _EVT_pumpMessages(void) -;---------------------------------------------------------------------------- -; This function would normally do nothing, however due to strange bugs -; in the Windows 3.1 and OS/2 DOS boxes, we don't get any hardware keyboard -; interrupts unless we periodically call the BIOS keyboard functions. Hence -; this function gets called every time that we check for events, and works -; around this problem (in essence it tells the DOS VDM to pump the -; keyboard events to our program ;-). -; -; Note that this bug is not present under Win 9x DOS boxes. -;---------------------------------------------------------------------------- -cprocstart _EVT_pumpMessages - - mov ah,11h ; Function - Check keyboard status - int 16h ; Call BIOS - - mov ax, 0Bh ; Reset Move Mouse - int 33h - ret - -cprocend - -;---------------------------------------------------------------------------- -; int _EVT_disableInt(void); -;---------------------------------------------------------------------------- -; Return processor interrupt status and disable interrupts. -;---------------------------------------------------------------------------- -cprocstart _EVT_disableInt - - pushf ; Put flag word on stack - cli ; Disable interrupts! - pop eax ; deposit flag word in return register - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _EVT_restoreInt(int ps); -;---------------------------------------------------------------------------- -; Restore processor interrupt status. -;---------------------------------------------------------------------------- -cprocstart _EVT_restoreInt - - ARG ps:UINT - - push ebp - mov ebp,esp ; Set up stack frame - push [DWORD ps] - popf ; Restore processor status (and interrupts) - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; int EVT_rdinx(int port,int index) -;---------------------------------------------------------------------------- -; Reads an indexed register value from an I/O port. -;---------------------------------------------------------------------------- -cprocstart EVT_rdinx - - ARG port:UINT, index:UINT - - push ebp - mov ebp,esp - mov edx,[port] - mov al,[BYTE index] - out dx,al - inc dx - in al,dx - movzx eax,al - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void EVT_wrinx(int port,int index,int value) -;---------------------------------------------------------------------------- -; Writes an indexed register value to an I/O port. -;---------------------------------------------------------------------------- -cprocstart EVT_wrinx - - ARG port:UINT, index:UINT, value:UINT - - push ebp - mov ebp,esp - mov edx,[port] - mov al,[BYTE index] - mov ah,[BYTE value] - out dx,ax - pop ebp - ret - -cprocend - - cpublic _EVT_codeEnd - -endcodeseg _event - -endif - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm deleted file mode 100644 index a4a9c79..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm +++ /dev/null @@ -1,438 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: NASM or TASM Assembler -;* Environment: IBM PC (MS DOS) -;* -;* Description: Uses the 8253 timer and the BIOS time-of-day count to time -;* the performance of code that takes less than an hour to -;* execute. -;* -;* The routines in this package only works with interrupts -;* enabled, and in fact will explicitly turn interrupts on -;* in order to ensure we get accurate results from the timer. -;* -;* Externally 'C' callable routines: -;* -;* LZ_timerOn: Saves the BIOS time of day count and starts the -;* long period Zen Timer. -;* -;* LZ_timerLap: Latches the current count, and keeps the timer running -;* -;* LZ_timerOff: Stops the long-period Zen Timer and saves the timer -;* count and the BIOS time of day count. -;* -;* LZ_timerCount: Returns an unsigned long representing the timed count -;* in microseconds. If more than an hour passed during -;* the timing interval, LZ_timerCount will return the -;* value 0xFFFFFFFF (an invalid count). -;* -;* Note: If either more than an hour passes between calls to LZ_timerOn -;* and LZ_timerOff, an error is reported. For timing code that takes -;* more than a few minutes to execute, use the low resolution -;* Ultra Long Period Zen Timer code, which should be accurate -;* enough for most purposes. -;* -;* Note: Each block of code being timed should ideally be run several -;* times, with at least two similar readings required to -;* establish a true measurement, in order to eliminate any -;* variability caused by interrupts. -;* -;* Note: Interrupts must not be disabled for more than 54 ms at a -;* stretch during the timing interval. Because interrupts are -;* enabled, key, mice, and other devices that generate interrupts -;* should not be used during the timing interval. -;* -;* Note: Any extra code running off the timer interrupt (such as -;* some memory resident utilities) will increase the time -;* measured by the Zen Timer. -;* -;* Note: These routines can introduce inaccuracies of up to a few -;* tenths of a second into the system clock count for each -;* code section being timed. Consequently, it's a good idea to -;* reboot at the conclusion of timing sessions. (The -;* battery-backed clock, if any, is not affected by the Zen -;* timer.) -;* -;* All registers and all flags are preserved by all routines, except -;* interrupts which are always turned on -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" - -;**************************************************************************** -; -; Equates used by long period Zen Timer -; -;**************************************************************************** - -; Base address of 8253 timer chip - -BASE_8253 equ 40h - -; The address of the timer 0 count registers in the 8253 - -TIMER_0_8253 equ BASE_8253 + 0 - -; The address of the mode register in the 8253 - -MODE_8253 equ BASE_8253 + 3 - -; The address of the BIOS timer count variable in the BIOS data area. - -TIMER_COUNT equ 6Ch - -; Macro to delay briefly to ensure that enough time has elapsed between -; successive I/O accesses so that the device being accessed can respond -; to both accesses even on a very fast PC. - -ifdef USE_NASM -%macro DELAY 0 - jmp short $+2 - jmp short $+2 - jmp short $+2 -%endmacro -else -macro DELAY - jmp short $+2 - jmp short $+2 - jmp short $+2 -endm -endif - -header _lztimer - -begdataseg _lztimer - - cextern _ZTimerBIOSPtr,DPTR - -StartBIOSCount dd 0 ; Starting BIOS count dword -EndBIOSCount dd 0 ; Ending BIOS count dword -EndTimedCount dw 0 ; Timer 0 count at the end of timing period - -enddataseg _lztimer - -begcodeseg _lztimer ; Start of code segment - -;---------------------------------------------------------------------------- -; void LZ_timerOn(void); -;---------------------------------------------------------------------------- -; Starts the Long period Zen timer counting. -;---------------------------------------------------------------------------- -cprocstart LZ_timerOn - -; Set the timer 0 of the 8253 to mode 2 (divide-by-N), to cause -; linear counting rather than count-by-two counting. Also stops -; timer 0 until the timer count is loaded, except on PS/2 computers. - - mov al,00110100b ; mode 2 - out MODE_8253,al - -; Set the timer count to 0, so we know we won't get another timer -; interrupt right away. Note: this introduces an inaccuracy of up to 54 ms -; in the system clock count each time it is executed. - - DELAY - sub al,al - out TIMER_0_8253,al ; lsb - DELAY - out TIMER_0_8253,al ; msb - -; Store the timing start BIOS count - - use_es -ifdef flatmodel - mov ebx,[_ZTimerBIOSPtr] -else - les bx,[_ZTimerBIOSPtr] -endif - cli ; No interrupts while we grab the count - mov eax,[_ES _bx+TIMER_COUNT] - sti - mov [StartBIOSCount],eax - unuse_es - -; Set the timer count to 0 again to start the timing interval. - - mov al,00110100b ; set up to load initial - out MODE_8253,al ; timer count - DELAY - sub al,al - out TIMER_0_8253,al ; load count lsb - DELAY - out TIMER_0_8253,al ; load count msb - - ret - -cprocend - -;---------------------------------------------------------------------------- -; void LZ_timerOff(void); -;---------------------------------------------------------------------------- -; Stops the long period Zen timer and saves count. -;---------------------------------------------------------------------------- -cprocstart LZ_timerOff - -; Latch the timer count. - - mov al,00000000b ; latch timer 0 - out MODE_8253,al - cli ; Stop the BIOS count - -; Read the BIOS count. (Since interrupts are disabled, the BIOS -; count won't change). - - use_es -ifdef flatmodel - mov ebx,[_ZTimerBIOSPtr] -else - les bx,[_ZTimerBIOSPtr] -endif - mov eax,[_ES _bx+TIMER_COUNT] - mov [EndBIOSCount],eax - unuse_es - -; Read out the count we latched earlier. - - in al,TIMER_0_8253 ; least significant byte - DELAY - mov ah,al - in al,TIMER_0_8253 ; most significant byte - xchg ah,al - neg ax ; Convert from countdown remaining - ; to elapsed count - mov [EndTimedCount],ax - sti ; Let the BIOS count continue - - ret - -cprocend - -;---------------------------------------------------------------------------- -; unsigned long LZ_timerLap(void) -;---------------------------------------------------------------------------- -; Latches the current count and converts it to a microsecond timing value, -; but leaves the timer still running. We dont check for and overflow, -; where the time has gone over an hour in this routine, since we want it -; to execute as fast as possible. -;---------------------------------------------------------------------------- -cprocstart LZ_timerLap - - push ebx ; Save EBX for 32 bit code - -; Latch the timer count. - - mov al,00000000b ; latch timer 0 - out MODE_8253,al - cli ; Stop the BIOS count - -; Read the BIOS count. (Since interrupts are disabled, the BIOS -; count wont change). - - use_es -ifdef flatmodel - mov ebx,[_ZTimerBIOSPtr] -else - les bx,[_ZTimerBIOSPtr] -endif - mov eax,[_ES _bx+TIMER_COUNT] - mov [EndBIOSCount],eax - unuse_es - -; Read out the count we latched earlier. - - in al,TIMER_0_8253 ; least significant byte - DELAY - mov ah,al - in al,TIMER_0_8253 ; most significant byte - xchg ah,al - neg ax ; Convert from countdown remaining - ; to elapsed count - mov [EndTimedCount],ax - sti ; Let the BIOS count continue - -; See if a midnight boundary has passed and adjust the finishing BIOS -; count by the number of ticks in 24 hours. We wont be able to detect -; more than 24 hours, but at least we can time across a midnight -; boundary - - mov eax,[EndBIOSCount] ; Is end < start? - cmp eax,[StartBIOSCount] - jae @@CalcBIOSTime ; No, calculate the time taken - -; Adjust the finishing time by adding the number of ticks in 24 hours -; (1573040). - - add [DWORD EndBIOSCount],1800B0h - -; Convert the BIOS time to microseconds - -@@CalcBIOSTime: - mov ax,[WORD EndBIOSCount] - sub ax,[WORD StartBIOSCount] - mov dx,54925 ; Number of microseconds each - ; BIOS count represents. - mul dx - mov bx,ax ; set aside BIOS count in - mov cx,dx ; microseconds - -; Convert timer count to microseconds - - push _si - mov ax,[EndTimedCount] - mov si,8381 - mul si - mov si,10000 - div si ; * 0.8381 = * 8381 / 10000 - pop _si - -; Add the timer and BIOS counts together to get an overall time in -; microseconds. - - add ax,bx - adc cx,0 -ifdef flatmodel - shl ecx,16 - mov cx,ax - mov eax,ecx ; EAX := timer count -else - mov dx,cx -endif - pop ebx ; Restore EBX for 32 bit code - ret - -cprocend - -;---------------------------------------------------------------------------- -; unsigned long LZ_timerCount(void); -;---------------------------------------------------------------------------- -; Returns an unsigned long representing the net time in microseconds. -; -; If an hour has passed while timing, we return 0xFFFFFFFF as the count -; (which is not a possible count in itself). -;---------------------------------------------------------------------------- -cprocstart LZ_timerCount - - push ebx ; Save EBX for 32 bit code - -; See if a midnight boundary has passed and adjust the finishing BIOS -; count by the number of ticks in 24 hours. We wont be able to detect -; more than 24 hours, but at least we can time across a midnight -; boundary - - mov eax,[EndBIOSCount] ; Is end < start? - cmp eax,[StartBIOSCount] - jae @@CheckForHour ; No, check for hour passing - -; Adjust the finishing time by adding the number of ticks in 24 hours -; (1573040). - - add [DWORD EndBIOSCount],1800B0h - -; See if more than an hour passed during timing. If so, notify the user. - -@@CheckForHour: - mov ax,[WORD StartBIOSCount+2] - cmp ax,[WORD EndBIOSCount+2] - jz @@CalcBIOSTime ; Hour count didn't change, so - ; everything is fine - - inc ax - cmp ax,[WORD EndBIOSCount+2] - jnz @@TestTooLong ; Two hour boundaries passed, so the - ; results are no good - mov ax,[WORD EndBIOSCount] - cmp ax,[WORD StartBIOSCount] - jb @@CalcBIOSTime ; a single hour boundary passed. That's - ; OK, so long as the total time wasn't - ; more than an hour. - -; Over an hour elapsed passed during timing, which renders -; the results invalid. Notify the user. This misses the case where a -; multiple of 24 hours has passed, but we'll rely on the perspicacity of -; the user to detect that case :-). - -@@TestTooLong: -ifdef flatmodel - mov eax,0FFFFFFFFh -else - mov ax,0FFFFh - mov dx,0FFFFh -endif - jmp short @@Done - -; Convert the BIOS time to microseconds - -@@CalcBIOSTime: - mov ax,[WORD EndBIOSCount] - sub ax,[WORD StartBIOSCount] - mov dx,54925 ; Number of microseconds each - ; BIOS count represents. - mul dx - mov bx,ax ; set aside BIOS count in - mov cx,dx ; microseconds - -; Convert timer count to microseconds - - push _si - mov ax,[EndTimedCount] - mov si,8381 - mul si - mov si,10000 - div si ; * 0.8381 = * 8381 / 10000 - pop _si - -; Add the timer and BIOS counts together to get an overall time in -; microseconds. - - add ax,bx - adc cx,0 -ifdef flatmodel - shl ecx,16 - mov cx,ax - mov eax,ecx ; EAX := timer count -else - mov dx,cx -endif - -@@Done: pop ebx ; Restore EBX for 32 bit code - ret - -cprocend - -cprocstart LZ_disable - cli - ret -cprocend - -cprocstart LZ_enable - sti - ret -cprocend - -endcodeseg _lztimer - - END diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm deleted file mode 100644 index 42b5cf3..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm +++ /dev/null @@ -1,656 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: IBM PC Real mode and 16/32 bit protected mode -;* -;* Description: Low level assembly support for the PM library specific to -;* MSDOS. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _pmdos ; Set up memory model - -begdataseg _pmdos - -ifndef flatmodel - -struc rmregs_s -ax dw ? -ax_high dw ? -bx dw ? -bx_high dw ? -cx dw ? -cx_high dw ? -dx dw ? -dx_high dw ? -si dw ? -si_high dw ? -di dw ? -di_high dw ? -cflag dw ? -cflag_high dw ? -ends rmregs_s -RMREGS = (rmregs_s PTR es:bx) - -struc rmsregs_s -es dw ? -cs dw ? -ss dw ? -ds dw ? -ends rmsregs_s -RMSREGS = (rmsregs_s PTR es:bx) - -endif ; !flatmodel - -ifdef flatmodel - cextern _PM_savedDS,USHORT - cextern _PM_VXD_off,UINT - cextern _PM_VXD_sel,UINT -ifdef DOS4GW - cextern _PM_haveCauseWay,UINT -endif -endif -intel_id db "GenuineIntel" ; Intel vendor ID - -PMHELP_GETPDB EQU 0026h -PMHELP_FLUSHTLB EQU 0027h - -enddataseg _pmdos - -P586 - -begcodeseg _pmdos ; Start of code segment - -ifndef flatmodel - -;---------------------------------------------------------------------------- -; void PM_callRealMode(unsigned s,unsigned o, RMREGS *regs, -; RMSREGS *sregs) -;---------------------------------------------------------------------------- -; Calls a real mode procedure, loading the appropriate registers values -; from the passed in structures. Only the DS and ES register are loaded -; from the SREGS structure. -;---------------------------------------------------------------------------- -cprocstart PM_callRealMode - - ARG s:WORD, o:WORD, regs:DWORD, sregs:DWORD - - LOCAL addr:DWORD, bxVal:WORD, esVal:WORD, flags:WORD = LocalSize - - enter_c - push ds - push es - - mov ax,[o] ; Build the address to call in 'addr' - mov [WORD addr],ax - mov ax,[s] - mov [WORD addr+2],ax - - les bx,[sregs] - mov ax,[RMSREGS.ds] - mov ds,ax ; DS := passed in value - mov ax,[RMSREGS.es] - mov [esVal],ax - les bx,[regs] - mov ax,[RMREGS.bx] - mov [bxVal],ax - mov ax,[RMREGS.ax] ; AX := passed in value - mov cx,[RMREGS.cx] ; CX := passed in value - mov dx,[RMREGS.dx] ; DX := passed in value - mov si,[RMREGS.si] ; SI := passed in value - mov di,[RMREGS.di] ; DI := passed in value - push bp - push [esVal] - pop es ; ES := passed in value - mov bx,[bxVal] ; BX := passed in value - - call [addr] ; Call the specified routine - - pushf ; Save flags for later - pop [flags] - - pop bp - push es - pop [esVal] - push bx - pop [bxVal] - les bx,[sregs] - push ds - pop [RMSREGS.ds] ; Save value of DS - push [esVal] - pop [RMSREGS.es] ; Save value of ES - les bx,[regs] - mov [RMREGS.ax],ax ; Save value of AX - mov [RMREGS.cx],cx ; Save value of CX - mov [RMREGS.dx],dx ; Save value of DX - mov [RMREGS.si],si ; Save value of SI - mov [RMREGS.di],di ; Save value of DI - mov ax,[flags] ; Return flags - and ax,1h ; Isolate carry flag - mov [RMREGS.cflag],ax ; Save carry flag status - mov ax,[bxVal] - mov [RMREGS.bx],ax ; Save value of BX - - pop es - pop ds - leave_c - ret - -cprocend - -endif - -;---------------------------------------------------------------------------- -; void PM_segread(PMSREGS *sregs) -;---------------------------------------------------------------------------- -; Read the current value of all segment registers -;---------------------------------------------------------------------------- -cprocstartdll16 PM_segread - - ARG sregs:DPTR - - enter_c - - mov ax,es - _les _si,[sregs] - mov [_ES _si],ax - mov [_ES _si+2],cs - mov [_ES _si+4],ss - mov [_ES _si+6],ds - mov [_ES _si+8],fs - mov [_ES _si+10],gs - - leave_c - ret - -cprocend - -; Create a table of the 256 different interrupt calls that we can jump -; into - -ifdef USE_NASM - -%assign intno 0 - -intTable: -%rep 256 - db 0CDh - db intno -%assign intno intno + 1 - ret - nop -%endrep - -else - -intno = 0 - -intTable: - REPT 256 - db 0CDh - db intno -intno = intno + 1 - ret - nop - ENDM - -endif - -;---------------------------------------------------------------------------- -; _PM_genInt - Generate the appropriate interrupt -;---------------------------------------------------------------------------- -cprocnear _PM_genInt - - push _ax ; Save _ax - push _bx ; Save _bx -ifdef flatmodel - mov ebx,[UINT esp+12] ; EBX := interrupt number -else - mov bx,sp ; Make sure ESP is zeroed - mov bx,[UINT ss:bx+6] ; BX := interrupt number -endif - mov _ax,offset intTable ; Point to interrupt generation table - shl _bx,2 ; _BX := index into table - add _ax,_bx ; _AX := pointer to interrupt code -ifdef flatmodel - xchg eax,[esp+4] ; Restore eax, and set for int -else - mov bx,sp - xchg ax,[ss:bx+2] ; Restore ax, and set for int -endif - pop _bx ; restore _bx - ret - -cprocend - -;---------------------------------------------------------------------------- -; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) -;---------------------------------------------------------------------------- -; Issues a software interrupt in protected mode. This routine has been -; written to allow user programs to load CS and DS with different values -; other than the default. -;---------------------------------------------------------------------------- -cprocstartdll16 PM_int386x - - ARG intno:UINT, inptr:DPTR, outptr:DPTR, sregs:DPTR - - LOCAL flags:UINT, sv_ds:UINT, sv_esi:ULONG = LocalSize - - enter_c - push ds - push es ; Save segment registers - push fs - push gs - - _lds _si,[sregs] ; DS:_SI -> Load segment registers - mov es,[_si] - mov bx,[_si+6] - mov [sv_ds],_bx ; Save value of user DS on stack - mov fs,[_si+8] - mov gs,[_si+10] - - _lds _si,[inptr] ; Load CPU registers - mov eax,[_si] - mov ebx,[_si+4] - mov ecx,[_si+8] - mov edx,[_si+12] - mov edi,[_si+20] - mov esi,[_si+16] - - push ds ; Save value of DS - push _bp ; Some interrupts trash this! - clc ; Generate the interrupt - push [UINT intno] - mov ds,[WORD sv_ds] ; Set value of user's DS selector - call _PM_genInt - pop _bp ; Pop intno from stack (flags unchanged) - pop _bp ; Restore value of stack frame pointer - pop ds ; Restore value of DS - - pushf ; Save flags for later - pop [UINT flags] - push esi ; Save ESI for later - pop [DWORD sv_esi] - push ds ; Save DS for later - pop [UINT sv_ds] - - _lds _si,[outptr] ; Save CPU registers - mov [_si],eax - mov [_si+4],ebx - mov [_si+8],ecx - mov [_si+12],edx - push [DWORD sv_esi] - pop [DWORD _si+16] - mov [_si+20],edi - - mov _bx,[flags] ; Return flags - and ebx,1h ; Isolate carry flag - mov [_si+24],ebx ; Save carry flag status - - _lds _si,[sregs] ; Save segment registers - mov [_si],es - mov _bx,[sv_ds] - mov [_si+6],bx ; Get returned DS from stack - mov [_si+8],fs - mov [_si+10],gs - - pop gs ; Restore segment registers - pop fs - pop es - pop ds - leave_c - ret - -cprocend - -ifndef flatmodel -_PM_savedDS dw _DATA ; Saved value of DS -endif - -;---------------------------------------------------------------------------- -; void PM_saveDS(void) -;---------------------------------------------------------------------------- -; Save the value of DS into a section of the code segment, so that we can -; quickly load this value at a later date in the PM_loadDS() routine from -; inside interrupt handlers etc. The method to do this is different -; depending on the DOS extender being used. -;---------------------------------------------------------------------------- -cprocstartdll16 PM_saveDS - -ifdef flatmodel - mov [_PM_savedDS],ds ; Store away in data segment -endif - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_loadDS(void) -;---------------------------------------------------------------------------- -; Routine to load the DS register with the default value for the current -; DOS extender. Only the DS register is loaded, not the ES register, so -; if you wish to call C code, you will need to also load the ES register -; in 32 bit protected mode. -;---------------------------------------------------------------------------- -cprocstartdll16 PM_loadDS - - mov ds,[cs:_PM_savedDS] ; We can access the proper DS through CS - ret - -cprocend - -ifdef flatmodel - -;---------------------------------------------------------------------------- -; ibool DPMI_allocateCallback(void (*pmcode)(), void *rmregs, long *RMCB) -;---------------------------------------------------------------------------- -cprocstart _DPMI_allocateCallback - - ARG pmcode:CPTR, rmregs:DPTR, RMCB:DPTR - - enter_c - push ds - push es - - push cs - pop ds - mov esi,[pmcode] ; DS:ESI -> protected mode code to call - mov edi,[rmregs] ; ES:EDI -> real mode register buffer - mov ax,303h ; AX := allocate realmode callback function - int 31h - mov eax,0 ; Return failure! - jc @@Fail - - mov eax,[RMCB] - shl ecx,16 - mov cx,dx - mov [es:eax],ecx ; Return real mode address - mov eax,1 ; Return success! - -@@Fail: pop es - pop ds - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void DPMI_freeCallback(long RMCB) -;---------------------------------------------------------------------------- -cprocstart _DPMI_freeCallback - - ARG RMCB:ULONG - - enter_c - - mov cx,[WORD RMCB+2] - mov dx,[WORD RMCB] ; CX:DX := real mode callback - mov ax,304h - int 31h - - leave_c - ret - -cprocend - -endif - -; Macro to delay briefly to ensure that enough time has elapsed between -; successive I/O accesses so that the device being accessed can respond -; to both accesses even on a very fast PC. - -ifdef USE_NASM -%macro DELAY 0 - jmp short $+2 - jmp short $+2 - jmp short $+2 -%endmacro -%macro IODELAYN 1 -%rep %1 - DELAY -%endrep -%endmacro -else -macro DELAY - jmp short $+2 - jmp short $+2 - jmp short $+2 -endm -macro IODELAYN N - rept N - DELAY - endm -endm -endif - -;---------------------------------------------------------------------------- -; uchar _PM_readCMOS(int index) -;---------------------------------------------------------------------------- -; Read the value of a specific CMOS register. We do this with both -; normal interrupts and NMI disabled. -;---------------------------------------------------------------------------- -cprocstart _PM_readCMOS - - ARG index:UINT - - push _bp - mov _bp,_sp - pushfd - mov al,[BYTE index] - or al,80h ; Add disable NMI flag - cli - out 70h,al - IODELAYN 5 - in al,71h - mov ah,al - xor al,al - IODELAYN 5 - out 70h,al ; Re-enable NMI - sti - mov al,ah ; Return value in AL - popfd - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _PM_writeCMOS(int index,uchar value) -;---------------------------------------------------------------------------- -; Read the value of a specific CMOS register. We do this with both -; normal interrupts and NMI disabled. -;---------------------------------------------------------------------------- -cprocstart _PM_writeCMOS - - ARG index:UINT, value:UCHAR - - push _bp - mov _bp,_sp - pushfd - mov al,[BYTE index] - or al,80h ; Add disable NMI flag - cli - out 70h,al - IODELAYN 5 - mov al,[value] - out 71h,al - xor al,al - IODELAYN 5 - out 70h,al ; Re-enable NMI - sti - popfd - pop _bp - ret - -cprocend - -ifdef flatmodel - -;---------------------------------------------------------------------------- -; int _PM_pagingEnabled(void) -;---------------------------------------------------------------------------- -; Returns 1 if paging is enabled, 0 if not or -1 if not at ring 0 -;---------------------------------------------------------------------------- -cprocstart _PM_pagingEnabled - - mov eax,-1 -ifdef DOS4GW - mov cx,cs - and ecx,3 - jz @@Ring0 - cmp [UINT _PM_haveCauseWay],0 - jnz @@Ring0 - jmp @@Exit - -@@Ring0: - mov eax,cr0 ; Load CR0 - shr eax,31 ; Isolate paging enabled bit -endif -@@Exit: ret - -cprocend - -;---------------------------------------------------------------------------- -; _PM_getPDB - Return the Page Table Directory Base address -;---------------------------------------------------------------------------- -cprocstart _PM_getPDB - -ifdef DOS4GW - mov ax,cs - and eax,3 - jz @@Ring0 - cmp [UINT _PM_haveCauseWay],0 - jnz @@Ring0 -endif - -; Call VxD if running at ring 3 in a DOS box - - cmp [WORD _PM_VXD_sel],0 - jz @@Fail - mov eax,PMHELP_GETPDB -ifdef USE_NASM - call far dword [_PM_VXD_off] -else - call [FCPTR _PM_VXD_off] -endif - ret - -@@Ring0: -ifdef DOS4GW - mov eax,cr3 - and eax,0FFFFF000h - ret -endif -@@Fail: xor eax,eax - ret - -cprocend - -;---------------------------------------------------------------------------- -; PM_flushTLB - Flush the Translation Lookaside buffer -;---------------------------------------------------------------------------- -cprocstart PM_flushTLB - - mov ax,cs - and eax,3 - jz @@Ring0 -ifdef DOS4GW - cmp [UINT _PM_haveCauseWay],0 - jnz @@Ring0 -endif - -; Call VxD if running at ring 3 in a DOS box - - cmp [WORD _PM_VXD_sel],0 - jz @@Fail - mov eax,PMHELP_FLUSHTLB -ifdef USE_NASM - call far dword [_PM_VXD_off] -else - call [FCPTR _PM_VXD_off] -endif - ret - -@@Ring0: -ifdef DOS4GW - wbinvd ; Flush the CPU cache - mov eax,cr3 - mov cr3,eax ; Flush the TLB -endif -@@Fail: ret - -cprocend - -endif - -;---------------------------------------------------------------------------- -; void _PM_VxDCall(VXD_regs far *r,uint off,uint sel); -;---------------------------------------------------------------------------- -cprocstart _PM_VxDCall - - ARG r:DPTR, off:UINT, sel:UINT - - enter_c - -; Load all registers from the registers structure - - mov ebx,[r] - mov eax,[ebx+0] - mov ecx,[ebx+8] - mov edx,[ebx+12] - mov esi,[ebx+16] - mov edi,[ebx+20] - mov ebx,[ebx+4] ; Trashes BX structure pointer! - -; Call the VxD entry point (on stack) - -ifdef USE_NASM - call far dword [off] -else - call [FCPTR off] -endif - -; Save all registers back in the structure - - push ebx ; Push EBX onto stack for later - mov ebx,[r] - mov [ebx+0],eax - mov [ebx+8],ecx - mov [ebx+12],edx - mov [ebx+16],esi - mov [ebx+20],edi - pop [DWORD ebx+4] ; Save value of EBX from stack - - leave_c - ret - -cprocend - -endcodeseg _pmdos - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm deleted file mode 100644 index 5c741f3..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm +++ /dev/null @@ -1,1105 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: IBM PC Real mode and 16/32 bit protected mode -;* -;* Description: Low level assembly support for the PM library specific to -;* MSDOS interrupt handling. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _pmdos ; Set up memory model - -; Define the size of our local stacks. For real mode code they cant be -; that big, but for 32 bit protected mode code we can make them nice and -; large so that complex C functions can be used. - -ifdef flatmodel -MOUSE_STACK EQU 4096 -TIMER_STACK EQU 4096 -KEY_STACK EQU 1024 -INT10_STACK EQU 1024 -IRQ_STACK EQU 1024 -else -MOUSE_STACK EQU 1024 -TIMER_STACK EQU 512 -KEY_STACK EQU 256 -INT10_STACK EQU 256 -IRQ_STACK EQU 256 -endif - -ifdef USE_NASM - -; Macro to load DS and ES registers with correct value. - -%imacro LOAD_DS 0 -%ifdef flatmodel - mov ds,[cs:_PM_savedDS] - mov es,[cs:_PM_savedDS] -%else - push ax - mov ax,_DATA - mov ds,ax - pop ax -%endif -%endmacro - -; Note that interrupts we disable interrupts during the following stack -; %imacro for correct operation, but we do not enable them again. Normally -; these %imacros are used within interrupt handlers so interrupts should -; already be off. We turn them back on explicitly later if the user code -; needs them to be back on. - -; Macro to switch to a new local stack. - -%imacro NEWSTK 1 - cli - mov [seg_%1],ss - mov [ptr_%1],_sp - mov [TempSeg],ds - mov ss,[TempSeg] - mov _sp,offset %1 -%endmacro - -; %imacro to switch back to the old stack. - -%imacro RESTSTK 1 - cli - mov ss,[seg_%1] - mov _sp,[ptr_%1] -%endmacro - -; %imacro to swap the current stack with the one saved away. - -%imacro SWAPSTK 1 - cli - mov ax,ss - xchg ax,[seg_%1] - mov ss,ax - xchg _sp,[ptr_%1] -%endmacro - -else - -; Macro to load DS and ES registers with correct value. - -MACRO LOAD_DS -ifdef flatmodel - mov ds,[cs:_PM_savedDS] - mov es,[cs:_PM_savedDS] -else - push ax - mov ax,_DATA - mov ds,ax - pop ax -endif -ENDM - -; Note that interrupts we disable interrupts during the following stack -; macro for correct operation, but we do not enable them again. Normally -; these macros are used within interrupt handlers so interrupts should -; already be off. We turn them back on explicitly later if the user code -; needs them to be back on. - -; Macro to switch to a new local stack. - -MACRO NEWSTK stkname - cli - mov [seg_&stkname&],ss - mov [ptr_&stkname&],_sp - mov [TempSeg],ds - mov ss,[TempSeg] - mov _sp,offset stkname -ENDM - -; Macro to switch back to the old stack. - -MACRO RESTSTK stkname - cli - mov ss,[seg_&stkname&] - mov _sp,[ptr_&stkname&] -ENDM - -; Macro to swap the current stack with the one saved away. - -MACRO SWAPSTK stkname - cli - mov ax,ss - xchg ax,[seg_&stkname&] - mov ss,ax - xchg _sp,[ptr_&stkname&] -ENDM - -endif - -begdataseg _pmdos - -ifdef flatmodel - cextern _PM_savedDS,USHORT -endif - cextern _PM_critHandler,CPTR - cextern _PM_breakHandler,CPTR - cextern _PM_timerHandler,CPTR - cextern _PM_rtcHandler,CPTR - cextern _PM_keyHandler,CPTR - cextern _PM_key15Handler,CPTR - cextern _PM_mouseHandler,CPTR - cextern _PM_int10Handler,CPTR - - cextern _PM_ctrlCPtr,DPTR - cextern _PM_ctrlBPtr,DPTR - cextern _PM_critPtr,DPTR - - cextern _PM_prevTimer,FCPTR - cextern _PM_prevRTC,FCPTR - cextern _PM_prevKey,FCPTR - cextern _PM_prevKey15,FCPTR - cextern _PM_prevBreak,FCPTR - cextern _PM_prevCtrlC,FCPTR - cextern _PM_prevCritical,FCPTR - cextern _PM_prevRealTimer,ULONG - cextern _PM_prevRealRTC,ULONG - cextern _PM_prevRealKey,ULONG - cextern _PM_prevRealKey15,ULONG - cextern _PM_prevRealInt10,ULONG - -cpublic _PM_pmdosDataStart - -; Allocate space for all of the local stacks that we need. These stacks -; are not very large, but should be large enough for most purposes -; (generally you want to handle these interrupts quickly, simply storing -; the information for later and then returning). If you need bigger -; stacks then change the appropriate value in here. - - ALIGN 4 - dclb MOUSE_STACK ; Space for local stack (small) -MsStack: ; Stack starts at end! -ptr_MsStack DUINT 0 ; Place to store old stack offset -seg_MsStack dw 0 ; Place to store old stack segment - - ALIGN 4 - dclb INT10_STACK ; Space for local stack (small) -Int10Stack: ; Stack starts at end! -ptr_Int10Stack DUINT 0 ; Place to store old stack offset -seg_Int10Stack dw 0 ; Place to store old stack segment - - ALIGN 4 - dclb TIMER_STACK ; Space for local stack (small) -TmStack: ; Stack starts at end! -ptr_TmStack DUINT 0 ; Place to store old stack offset -seg_TmStack dw 0 ; Place to store old stack segment - - ALIGN 4 - dclb TIMER_STACK ; Space for local stack (small) -RtcStack: ; Stack starts at end! -ptr_RtcStack DUINT 0 ; Place to store old stack offset -seg_RtcStack dw 0 ; Place to store old stack segment -RtcInside dw 0 ; Are we still handling current interrupt - - ALIGN 4 - dclb KEY_STACK ; Space for local stack (small) -KyStack: ; Stack starts at end! -ptr_KyStack DUINT 0 ; Place to store old stack offset -seg_KyStack dw 0 ; Place to store old stack segment -KyInside dw 0 ; Are we still handling current interrupt - - ALIGN 4 - dclb KEY_STACK ; Space for local stack (small) -Ky15Stack: ; Stack starts at end! -ptr_Ky15Stack DUINT 0 ; Place to store old stack offset -seg_Ky15Stack dw 0 ; Place to store old stack segment - -TempSeg dw 0 ; Place to store stack segment - -cpublic _PM_pmdosDataEnd - -enddataseg _pmdos - -begcodeseg _pmdos ; Start of code segment - -cpublic _PM_pmdosCodeStart - -;---------------------------------------------------------------------------- -; PM_mouseISR - Mouse interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Interrupt subroutine called by the mouse driver upon interrupts, to -; dispatch control to high level C based subroutines. Interrupts are on -; when we call the user code. -; -; It is _extremely_ important to save the state of the extended registers -; as these may well be trashed by the routines called from here and not -; restored correctly by the mouse interface module. -; -; NOTE: This routine switches to a local stack before calling any C code, -; and hence is _not_ re-entrant. For mouse handlers this is not a -; problem, as the mouse driver arbitrates calls to the user mouse -; handler for us. -; -; Entry: AX - Condition mask giving reason for call -; BX - Mouse button state -; CX - Horizontal cursor coordinate -; DX - Vertical cursor coordinate -; SI - Horizontal mickey value -; DI - Vertical mickey value -; -;---------------------------------------------------------------------------- -ifdef DJGPP -cprocstart _PM_mouseISR -else -cprocfar _PM_mouseISR -endif - - push ds ; Save value of DS - push es - pushad ; Save _all_ extended registers - cld ; Clear direction flag - - LOAD_DS ; Load DS register - NEWSTK MsStack ; Switch to local stack - -; Call the installed high level C code routine - - clrhi dx ; Clear out high order values - clrhi cx - clrhi bx - clrhi ax - sgnhi si - sgnhi di - - push _di - push _si - push _dx - push _cx - push _bx - push _ax - sti ; Enable interrupts - call [CPTR _PM_mouseHandler] - _add sp,12,24 - - RESTSTK MsStack ; Restore previous stack - - popad ; Restore all extended registers - pop es - pop ds - ret ; We are done!! - -cprocend - -;---------------------------------------------------------------------------- -; PM_timerISR - Timer interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Hardware interrupt handler for the timer interrupt, to dispatch control -; to high level C based subroutines. We save the state of all registers -; in this routine, and switch to a local stack. Interrupts are *off* -; when we call the user code. -; -; NOTE: This routine switches to a local stack before calling any C code, -; and hence is _not_ re-entrant. Make sure your C code executes as -; quickly as possible, since a timer overrun will simply hang the -; system. -;---------------------------------------------------------------------------- -cprocfar _PM_timerISR - - push ds ; Save value of DS - push es - pushad ; Save _all_ extended registers - cld ; Clear direction flag - - LOAD_DS ; Load DS register - - NEWSTK TmStack ; Switch to local stack - call [CPTR _PM_timerHandler] - RESTSTK TmStack ; Restore previous stack - - popad ; Restore all extended registers - pop es - pop ds - iret ; Return from interrupt - -cprocend - -;---------------------------------------------------------------------------- -; PM_chainPrevTimer - Chain to previous timer interrupt and return -;---------------------------------------------------------------------------- -; Chains to the previous timer interrupt routine and returns control -; back to the high level interrupt handler. -;---------------------------------------------------------------------------- -cprocstart PM_chainPrevTimer - -ifdef TNT - push eax - push ebx - push ecx - pushfd ; Push flags on stack to simulate interrupt - mov ax,250Eh ; Call real mode procedure function - mov ebx,[_PM_prevRealTimer] - mov ecx,1 ; Copy real mode flags to real mode stack - int 21h ; Call the real mode code - popfd - pop ecx - pop ebx - pop eax - ret -else - SWAPSTK TmStack ; Swap back to previous stack - pushf ; Save state of interrupt flag - pushf ; Push flags on stack to simulate interrupt -ifdef USE_NASM - call far dword [_PM_prevTimer] -else - call [_PM_prevTimer] -endif - popf ; Restore state of interrupt flag - SWAPSTK TmStack ; Swap back to C stack again - ret -endif - -cprocend - -; Macro to delay briefly to ensure that enough time has elapsed between -; successive I/O accesses so that the device being accessed can respond -; to both accesses even on a very fast PC. - -ifdef USE_NASM -%macro DELAY 0 - jmp short $+2 - jmp short $+2 - jmp short $+2 -%endmacro -%macro IODELAYN 1 -%rep %1 - DELAY -%endrep -%endmacro -else -macro DELAY - jmp short $+2 - jmp short $+2 - jmp short $+2 -endm -macro IODELAYN N - rept N - DELAY - endm -endm -endif - -;---------------------------------------------------------------------------- -; PM_rtcISR - Real time clock interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Hardware interrupt handler for the timer interrupt, to dispatch control -; to high level C based subroutines. We save the state of all registers -; in this routine, and switch to a local stack. Interrupts are *off* -; when we call the user code. -; -; NOTE: This routine switches to a local stack before calling any C code, -; and hence is _not_ re-entrant. Make sure your C code executes as -; quickly as possible, since a timer overrun will simply hang the -; system. -;---------------------------------------------------------------------------- -cprocfar _PM_rtcISR - - push ds ; Save value of DS - push es - pushad ; Save _all_ extended registers - cld ; Clear direction flag - -; Clear priority interrupt controller and re-enable interrupts so we -; dont lock things up for long. - - mov al,20h - out 0A0h,al - out 020h,al - -; Clear real-time clock timeout - - in al,70h ; Read CMOS index register - push _ax ; and save for later - IODELAYN 3 - mov al,0Ch - out 70h,al - IODELAYN 5 - in al,71h - -; Call the C interrupt handler function - - LOAD_DS ; Load DS register - cmp [BYTE RtcInside],1 ; Check for mutual exclusion - je @@Exit - mov [BYTE RtcInside],1 - NEWSTK RtcStack ; Switch to local stack - sti ; Re-enable interrupts - call [CPTR _PM_rtcHandler] - RESTSTK RtcStack ; Restore previous stack - mov [BYTE RtcInside],0 - -@@Exit: pop _ax - out 70h,al ; Restore CMOS index register - popad ; Restore all extended registers - pop es - pop ds - iret ; Return from interrupt - -cprocend - -ifdef flatmodel -;---------------------------------------------------------------------------- -; PM_irqISRTemplate - Hardware interrupt handler IRQ template -;---------------------------------------------------------------------------- -; Hardware interrupt handler for any interrupt, to dispatch control -; to high level C based subroutines. We save the state of all registers -; in this routine, and switch to a local stack. Interrupts are *off* -; when we call the user code. -; -; NOTE: This routine switches to a local stack before calling any C code, -; and hence is _not_ re-entrant. Make sure your C code executes as -; quickly as possible. -;---------------------------------------------------------------------------- -cprocfar _PM_irqISRTemplate - - push ebx - mov ebx,0 ; Relocation adjustment factor - jmp __IRQEntry - -; Global variables stored in the IRQ thunk code segment - -_CHandler dd 0 ; Pointer to C interrupt handler -_PrevIRQ dd 0 ; Previous IRQ handler - dd 0 -_IRQ dd 0 ; IRQ we are hooked for -ptr_IRQStack DUINT 0 ; Place to store old stack offset -seg_IRQStack dw 0 ; Place to store old stack segment -_Inside db 0 ; Mutual exclusion flag - ALIGN 4 - dclb IRQ_STACK ; Space for local stack -_IRQStack: ; Stack starts at end! - -; Check for and reject spurious IRQ 7 signals - -__IRQEntry: - cmp [BYTE cs:ebx+_IRQ],7 ; Spurious IRQs occur only on IRQ 7 - jmp @@ValidIRQ - push eax - mov al,1011b ; OCW3: read ISR - out 20h,al ; (Intel Peripheral Components, 1991, - in al,20h ; p. 3-188) - shl al,1 ; Set C = bit 7 (IRQ 7) of ISR register - pop eax - jc @@ValidIRQ - iret ; Return from interrupt - -; Save all registers for duration of IRQ handler - -@@ValidIRQ: - push ds ; Save value of DS - push es - pushad ; Save _all_ extended registers - cld ; Clear direction flag - LOAD_DS ; Load DS register - -; Send an EOI to the PIC - - mov al,20h ; Send EOI to PIC - cmp [BYTE ebx+_IRQ],8 ; Clear PIC1 first if IRQ >= 8 - jb @@1 - out 0A0h,al -@@1: out 20h,al - -; Check for mutual exclusion - - cmp [BYTE ebx+_Inside],1 - je @@ChainOldHandler - mov [BYTE ebx+_Inside],1 - -; Call the C interrupt handler function - - mov [ebx+seg_IRQStack],ss ; Switch to local stack - mov [ebx+ptr_IRQStack],esp - mov [TempSeg],ds - mov ss,[TempSeg] - lea esp,[ebx+_IRQStack] - sti ; Re-enable interrupts - push ebx - call [DWORD ebx+_CHandler] - pop ebx - cli - mov ss,[ebx+seg_IRQStack] ; Restore previous stack - mov esp,[ebx+ptr_IRQStack] - or eax,eax - jz @@ChainOldHandler ; Chain if not handled for shared IRQ - -@@Exit: mov [BYTE ebx+_Inside],0 - popad ; Restore all extended registers - pop es - pop ds - pop ebx - iret ; Return from interrupt - -@@ChainOldHandler: - cmp [DWORD ebx+_PrevIRQ],0 - jz @@Exit - mov [BYTE ebx+_Inside],0 - mov eax,[DWORD ebx+_PrevIRQ] - mov ebx,[DWORD ebx+_PrevIRQ+4] - mov [DWORD _PrevIRQ],eax - mov [DWORD _PrevIRQ+4],ebx - popad ; Restore all extended registers - pop es - pop ds - pop ebx - jmp [cs:_PrevIRQ] ; Chain to previous IRQ handler - -cprocend -cpublic _PM_irqISRTemplateEnd -endif - -;---------------------------------------------------------------------------- -; PM_keyISR - keyboard interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Hardware interrupt handler for the keyboard interrupt, to dispatch control -; to high level C based subroutines. We save the state of all registers -; in this routine, and switch to a local stack. Interrupts are *off* -; when we call the user code. -; -; NOTE: This routine switches to a local stack before calling any C code, -; and hence is _not_ re-entrant. However we ensure within this routine -; mutual exclusion to the keyboard handling routine. -;---------------------------------------------------------------------------- -cprocfar _PM_keyISR - - push ds ; Save value of DS - push es - pushad ; Save _all_ extended registers - cld ; Clear direction flag - - LOAD_DS ; Load DS register - - cmp [BYTE KyInside],1 ; Check for mutual exclusion - je @@Reissued - - mov [BYTE KyInside],1 - NEWSTK KyStack ; Switch to local stack - call [CPTR _PM_keyHandler] ; Call C code - RESTSTK KyStack ; Restore previous stack - mov [BYTE KyInside],0 - -@@Exit: popad ; Restore all extended registers - pop es - pop ds - iret ; Return from interrupt - -; When the BIOS keyboard handler needs to change the SHIFT status lights -; on the keyboard, in the process of doing this the keyboard controller -; re-issues another interrupt, while the current handler is still executing. -; If we recieve another interrupt while still handling the current one, -; then simply chain directly to the previous handler. -; -; Note that for most DOS extenders, the real mode interrupt handler that we -; install takes care of this for us. - -@@Reissued: -ifdef TNT - push eax - push ebx - push ecx - pushfd ; Push flags on stack to simulate interrupt - mov ax,250Eh ; Call real mode procedure function - mov ebx,[_PM_prevRealKey] - mov ecx,1 ; Copy real mode flags to real mode stack - int 21h ; Call the real mode code - popfd - pop ecx - pop ebx - pop eax -else - pushf -ifdef USE_NASM - call far dword [_PM_prevKey] -else - call [_PM_prevKey] -endif -endif - jmp @@Exit - -cprocend - -;---------------------------------------------------------------------------- -; PM_chainPrevkey - Chain to previous key interrupt and return -;---------------------------------------------------------------------------- -; Chains to the previous key interrupt routine and returns control -; back to the high level interrupt handler. -;---------------------------------------------------------------------------- -cprocstart PM_chainPrevKey - -ifdef TNT - push eax - push ebx - push ecx - pushfd ; Push flags on stack to simulate interrupt - mov ax,250Eh ; Call real mode procedure function - mov ebx,[_PM_prevRealKey] - mov ecx,1 ; Copy real mode flags to real mode stack - int 21h ; Call the real mode code - popfd - pop ecx - pop ebx - pop eax - ret -else - -; YIKES! For some strange reason, when execution returns from the -; previous keyboard handler, interrupts are re-enabled!! Since we expect -; interrupts to remain off during the duration of our handler, this can -; cause havoc. However our stack macros always turn off interrupts, so they -; will be off when we exit this routine. Obviously there is a tiny weeny -; window when interrupts will be enabled, but there is nothing we can -; do about this. - - SWAPSTK KyStack ; Swap back to previous stack - pushf ; Push flags on stack to simulate interrupt -ifdef USE_NASM - call far dword [_PM_prevKey] -else - call [_PM_prevKey] -endif - SWAPSTK KyStack ; Swap back to C stack again - ret -endif - -cprocend - -;---------------------------------------------------------------------------- -; PM_key15ISR - Int 15h keyboard interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; This routine gets called if we have been called to handle the Int 15h -; keyboard interrupt callout from real mode. -; -; Entry: AX - Hardware scan code to process -; Exit: AX - Hardware scan code to process (0 to ignore) -;---------------------------------------------------------------------------- -cprocfar _PM_key15ISR - - push ds - push es - LOAD_DS - cmp ah,4Fh - jnz @@NotOurs ; Quit if not keyboard callout - - pushad - cld ; Clear direction flag - xor ah,ah ; AX := scan code - NEWSTK Ky15Stack ; Switch to local stack - push _ax - call [CPTR _PM_key15Handler] ; Call C code - _add sp,2,4 - RESTSTK Ky15Stack ; Restore previous stack - test ax,ax - jz @@1 - stc ; Set carry to process as normal - jmp @@2 -@@1: clc ; Clear carry to ignore scan code -@@2: popad - jmp @@Exit ; We are done - -@@NotOurs: -ifdef TNT - push eax - push ebx - push ecx - pushfd ; Push flags on stack to simulate interrupt - mov ax,250Eh ; Call real mode procedure function - mov ebx,[_PM_prevRealKey15] - mov ecx,1 ; Copy real mode flags to real mode stack - int 21h ; Call the real mode code - popfd - pop ecx - pop ebx - pop eax -else - pushf -ifdef USE_NASM - call far dword [_PM_prevKey15] -else - call [_PM_prevKey15] -endif -endif -@@Exit: pop es - pop ds -ifdef flatmodel - retf 4 -else - retf 2 -endif - -cprocend - -;---------------------------------------------------------------------------- -; PM_breakISR - Control Break interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Hardware interrupt handler for the Ctrl-Break interrupt. We simply set -; the Ctrl-Break flag to a 1 and leave (note that this is accessed through -; a far pointer, as it may well be located in conventional memory). -;---------------------------------------------------------------------------- -cprocfar _PM_breakISR - - sti - push ds ; Save value of DS - push es - push _bx - - LOAD_DS ; Load DS register -ifdef flatmodel - mov ebx,[_PM_ctrlBPtr] -else - les bx,[_PM_ctrlBPtr] -endif - mov [UINT _ES _bx],1 - -; Run alternate break handler code if installed - - cmp [CPTR _PM_breakHandler],0 - je @@Exit - - pushad - mov _ax,1 - push _ax - call [CPTR _PM_breakHandler] ; Call C code - pop _ax - popad - -@@Exit: pop _bx - pop es - pop ds - iret ; Return from interrupt - -cprocend - -;---------------------------------------------------------------------------- -; int PM_ctrlBreakHit(int clearFlag) -;---------------------------------------------------------------------------- -; Returns the current state of the Ctrl-Break flag and possibly clears it. -;---------------------------------------------------------------------------- -cprocstart PM_ctrlBreakHit - - ARG clearFlag:UINT - - enter_c - pushf ; Save interrupt status - push es -ifdef flatmodel - mov ebx,[_PM_ctrlBPtr] -else - les bx,[_PM_ctrlBPtr] -endif - cli ; No interrupts thanks! - mov _ax,[_ES _bx] - test [BYTE clearFlag],1 - jz @@Done - mov [UINT _ES _bx],0 - -@@Done: pop es - popf ; Restore interrupt status - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; PM_ctrlCISR - Control Break interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Hardware interrupt handler for the Ctrl-C interrupt. We simply set -; the Ctrl-C flag to a 1 and leave (note that this is accessed through -; a far pointer, as it may well be located in conventional memory). -;---------------------------------------------------------------------------- -cprocfar _PM_ctrlCISR - - sti - push ds ; Save value of DS - push es - push _bx - - LOAD_DS ; Load DS register -ifdef flatmodel - mov ebx,[_PM_ctrlCPtr] -else - les bx,[_PM_ctrlCPtr] -endif - mov [UINT _ES _bx],1 - -; Run alternate break handler code if installed - - cmp [CPTR _PM_breakHandler],0 - je @@Exit - - pushad - mov _ax,0 - push _ax - call [CPTR _PM_breakHandler] ; Call C code - pop _ax - popad - -@@Exit: pop _bx - pop es - pop ds - iret ; Return from interrupt - iretd - -cprocend - -;---------------------------------------------------------------------------- -; int PM_ctrlCHit(int clearFlag) -;---------------------------------------------------------------------------- -; Returns the current state of the Ctrl-C flag and possibly clears it. -;---------------------------------------------------------------------------- -cprocstart PM_ctrlCHit - - ARG clearFlag:UINT - - enter_c - pushf ; Save interrupt status - push es -ifdef flatmodel - mov ebx,[_PM_ctrlCPtr] -else - les bx,[_PM_ctrlCPtr] -endif - cli ; No interrupts thanks! - mov _ax,[_ES _bx] - test [BYTE clearFlag],1 - jz @@Done - mov [UINT _ES _bx],0 - -@@Done: - pop es - popf ; Restore interrupt status - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; PM_criticalISR - Control Error handler interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Interrupt handler for the MSDOS Critical Error interrupt, to dispatch -; control to high level C based subroutines. We save the state of all -; registers in this routine, and switch to a local stack. We also pass -; the values of the AX and DI registers to the as pointers, so that the -; values can be modified before returning to MSDOS. -;---------------------------------------------------------------------------- -cprocfar _PM_criticalISR - - sti - push ds ; Save value of DS - push es - push _bx ; Save register values changed - cld ; Clear direction flag - - LOAD_DS ; Load DS register -ifdef flatmodel - mov ebx,[_PM_critPtr] -else - les bx,[_PM_critPtr] -endif - mov [_ES _bx],ax - mov [_ES _bx+2],di - -; Run alternate critical handler code if installed - - cmp [CPTR _PM_critHandler],0 - je @@NoAltHandler - - pushad - push _di - push _ax - call [CPTR _PM_critHandler] ; Call C code - _add sp,4,8 - popad - - pop _bx - pop es - pop ds - iret ; Return from interrupt - -@@NoAltHandler: - mov ax,3 ; Tell MSDOS to fail the operation - pop _bx - pop es - pop ds - iret ; Return from interrupt - -cprocend - -;---------------------------------------------------------------------------- -; int PM_criticalError(int *axVal,int *diVal,int clearFlag) -;---------------------------------------------------------------------------- -; Returns the current state of the critical error flags, and the values that -; MSDOS passed in the AX and DI registers to our handler. -;---------------------------------------------------------------------------- -cprocstart PM_criticalError - - ARG axVal:DPTR, diVal:DPTR, clearFlag:UINT - - enter_c - pushf ; Save interrupt status - push es -ifdef flatmodel - mov ebx,[_PM_critPtr] -else - les bx,[_PM_critPtr] -endif - cli ; No interrupts thanks! - xor _ax,_ax - xor _di,_di - mov ax,[_ES _bx] - mov di,[_ES _bx+2] - test [BYTE clearFlag],1 - jz @@NoClear - mov [ULONG _ES _bx],0 -@@NoClear: - _les _bx,[axVal] - mov [_ES _bx],_ax - _les _bx,[diVal] - mov [_ES _bx],_di - pop es - popf ; Restore interrupt status - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_setMouseHandler(int mask, PM_mouseHandler mh) -;---------------------------------------------------------------------------- -cprocstart _PM_setMouseHandler - - ARG mouseMask:UINT - - enter_c - push es - - mov ax,0Ch ; AX := Function 12 - install interrupt sub - mov _cx,[mouseMask] ; CX := mouse mask - mov _dx,offset _PM_mouseISR - push cs - pop es ; ES:_DX -> mouse handler - int 33h ; Call mouse driver - - pop es - leave_c - ret - -cprocend - -ifdef flatmodel - -;---------------------------------------------------------------------------- -; void PM_mousePMCB(void) -;---------------------------------------------------------------------------- -; Mouse realmode callback routine. Upon entry to this routine, we recieve -; the following from the DPMI server: -; -; Entry: DS:_SI -> Real mode stack at time of call -; ES:_DI -> Real mode register data structure -; SS:_SP -> Locked protected mode stack to use -;---------------------------------------------------------------------------- -cprocfar _PM_mousePMCB - - pushad - mov eax,[es:_di+1Ch] ; Load register values from real mode - mov ebx,[es:_di+10h] - mov ecx,[es:_di+18h] - mov edx,[es:_di+14h] - mov esi,[es:_di+04h] - mov edi,[es:_di] - call _PM_mouseISR ; Call the mouse handler - popad - - mov ax,[ds:_si] - mov [es:_di+2Ah],ax ; Plug in return IP address - mov ax,[ds:_si+2] - mov [es:_di+2Ch],ax ; Plug in return CS value - add [WORD es:_di+2Eh],4 ; Remove return address from stack - iret ; Go back to real mode! - -cprocend - -;---------------------------------------------------------------------------- -; void PM_int10PMCB(void) -;---------------------------------------------------------------------------- -; int10 realmode callback routine. Upon entry to this routine, we recieve -; the following from the DPMI server: -; -; Entry: DS:ESI -> Real mode stack at time of call -; ES:EDI -> Real mode register data structure -; SS:ESP -> Locked protected mode stack to use -;---------------------------------------------------------------------------- -cprocfar _PM_int10PMCB - - pushad - push ds - push es - push fs - - pushfd - pop eax - mov [es:edi+20h],ax ; Save return flag status - mov ax,[ds:esi] - mov [es:edi+2Ah],ax ; Plug in return IP address - mov ax,[ds:esi+2] - mov [es:edi+2Ch],ax ; Plug in return CS value - add [WORD es:edi+2Eh],4 ; Remove return address from stack - -; Call the install int10 handler in protected mode. This function gets called -; with DS set to the current data selector, and ES:EDI pointing the the -; real mode DPMI register structure at the time of the interrupt. The -; handle must be written in assembler to be able to extract the real mode -; register values from the structure - - push es - pop fs ; FS:EDI -> real mode registers - LOAD_DS - NEWSTK Int10Stack ; Switch to local stack - - call [_PM_int10Handler] - - RESTSTK Int10Stack ; Restore previous stack - pop fs - pop es - pop ds - popad - iret ; Go back to real mode! - -cprocend - -endif - -cpublic _PM_pmdosCodeEnd - -endcodeseg _pmdos - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm deleted file mode 100644 index 34985a9..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm +++ /dev/null @@ -1,652 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Based on original code Copyright 1994 Otto Chrons -;* -;* Language: 80386 Assembler, TASM 4.0 or later -;* Environment: IBM PC 32 bit protected mode -;* -;* Description: Low level page fault handler for virtual linear framebuffers. -;* -;**************************************************************************** - - IDEAL - JUMPS - -include "scitech.mac" ; Memory model macros - -header _vflat ; Set up memory model - -VFLAT_START EQU 0F0000000h -VFLAT_END EQU 0F03FFFFFh -PAGE_PRESENT EQU 1 -PAGE_NOTPRESENT EQU 0 -PAGE_READ EQU 0 -PAGE_WRITE EQU 2 - -ifdef DOS4GW - -;---------------------------------------------------------------------------- -; DOS4G/W flat linear framebuffer emulation. -;---------------------------------------------------------------------------- - -begdataseg _vflat - -; Near pointers to the page directory base and our page tables. All of -; this memory is always located in the first Mb of DOS memory. - -PDBR dd 0 ; Page directory base register (CR3) -accessPageAddr dd 0 -accessPageTable dd 0 - -; CauseWay page directory & 1st page table linear addresses. - -CauseWayDIRLinear dd 0 -CauseWay1stLinear dd 0 - -; Place to store a copy of the original Page Table Directory before we -; intialised our virtual buffer code. - -pageDirectory: resd 1024 ; Saved page table directory - -ValidCS dw 0 ; Valid CS for page faults -Ring0CS dw 0 ; Our ring 0 code selector -LastPage dd 0 ; Last page we mapped in -BankFuncBuf: resb 101 ; Place to store bank switch code -BankFuncPtr dd offset BankFuncBuf - -INT14Gate: -INT14Offset dd 0 ; eip of original vector -INT14Selector dw 0 ; cs of original vector - - cextern _PM_savedDS,USHORT - cextern VF_haveCauseWay,BOOL - -enddataseg _vflat - -begcodeseg _vflat ; Start of code segment - - cextern VF_malloc,FPTR - -;---------------------------------------------------------------------------- -; PF_handler64k - Page fault handler for 64k banks -;---------------------------------------------------------------------------- -; The handler below is a 32 bit ring 0 page fault handler. It receives -; control immediately after any page fault or after an IRQ6 (hardware -; interrupt). This provides the fastest possible handling of page faults -; since it jump directly here. If this is a page fault, the number -; immediately on the stack will be an error code, at offset 4 will be -; the eip of the faulting instruction, at offset 8 will be the cs of the -; faulting instruction. If it is a hardware interrupt, it will not have -; the error code and the eflags will be at offset 8. -;---------------------------------------------------------------------------- -cprocfar PF_handler64k - -; Check if this is a processor exeception or a page fault - - push eax - mov ax,[cs:ValidCS] ; Use CS override to access data - cmp [ss:esp+12],ax ; Is this a page fault? - jne @@ToOldHandler ; Nope, jump to the previous handler - -; Get address of page fault and check if within our handlers range - - mov eax,cr2 ; EBX has page fault linear address - cmp eax,VFLAT_START ; Is the fault less than ours? - jb @@ToOldHandler ; Yep, go to previous handler - cmp eax,VFLAT_END ; Is the fault more than ours? - jae @@ToOldHandler ; Yep, go to previous handler - -; This is our page fault, so we need to handle it - - pushad - push ds - push es - mov ebx,eax ; EBX := page fault address - and ebx,invert 0FFFFh ; Mask to 64k bank boundary - mov ds,[cs:_PM_savedDS]; Load segment registers - mov es,[cs:_PM_savedDS] - -; Map in the page table for our virtual framebuffer area for modification - - mov edi,[PDBR] ; EDI points to page directory - mov edx,ebx ; EDX = linear address - shr edx,22 ; EDX = offset to page directory - mov edx,[edx*4+edi] ; EDX = physical page table address - mov eax,edx - mov edx,[accessPageTable] - or eax,7 - mov [edx],eax - mov eax,cr3 - mov cr3,eax ; Update page table cache - -; Mark all pages valid for the new page fault area - - mov esi,ebx ; ESI := linear address for page - shr esi,10 - and esi,0FFFh ; Offset into page table - add esi,[accessPageAddr] -ifdef USE_NASM -%assign off 0 -%rep 16 - or [DWORD esi+off],0000000001h ; Enable pages -%assign off off+4 -%endrep -else -off = 0 -REPT 16 - or [DWORD esi+off],0000000001h ; Enable pages -off = off+4 -ENDM -endif - -; Mark all pages invalid for the previously mapped area - - xchg esi,[LastPage] ; Save last page for next page fault - test esi,esi - jz @@DoneMapping ; Dont update if first time round -ifdef USE_NASM -%assign off 0 -%rep 16 - or [DWORD esi+off],0FFFFFFFEh ; Disable pages -%assign off off+4 -%endrep -else -off = 0 -REPT 16 - and [DWORD esi+off],0FFFFFFFEh ; Disable pages -off = off+4 -ENDM -endif - -@@DoneMapping: - mov eax,cr3 - mov cr3,eax ; Flush the TLB - -; Now program the new SuperVGA starting bank address - - mov eax,ebx ; EAX := page fault address - shr eax,16 - and eax,0FFh ; Mask to 0-255 - call [BankFuncPtr] ; Call the bank switch function - - pop es - pop ds - popad - pop eax - add esp,4 ; Pop the error code from stack - iretd ; Return to faulting instruction - -@@ToOldHandler: - pop eax -ifdef USE_NASM - jmp far dword [cs:INT14Gate]; Chain to previous handler -else - jmp [FWORD cs:INT14Gate]; Chain to previous handler -endif - -cprocend - -;---------------------------------------------------------------------------- -; PF_handler4k - Page fault handler for 4k banks -;---------------------------------------------------------------------------- -; The handler below is a 32 bit ring 0 page fault handler. It receives -; control immediately after any page fault or after an IRQ6 (hardware -; interrupt). This provides the fastest possible handling of page faults -; since it jump directly here. If this is a page fault, the number -; immediately on the stack will be an error code, at offset 4 will be -; the eip of the faulting instruction, at offset 8 will be the cs of the -; faulting instruction. If it is a hardware interrupt, it will not have -; the error code and the eflags will be at offset 8. -;---------------------------------------------------------------------------- -cprocfar PF_handler4k - -; Fill in when we have tested all the 64Kb code - -ifdef USE_NASM - jmp far dword [cs:INT14Gate]; Chain to previous handler -else - jmp [FWORD cs:INT14Gate]; Chain to previous handler -endif - -cprocend - -;---------------------------------------------------------------------------- -; void InstallFaultHandler(void *baseAddr,int bankSize) -;---------------------------------------------------------------------------- -; Installes the page fault handler directly int the interrupt descriptor -; table for maximum performance. This of course requires ring 0 access, -; but none of this stuff will run without ring 0! -;---------------------------------------------------------------------------- -cprocstart InstallFaultHandler - - ARG baseAddr:ULONG, bankSize:UINT - - enter_c - - mov [DWORD LastPage],0 ; No pages have been mapped - mov ax,cs - mov [ValidCS],ax ; Save CS value for page faults - -; Put address of our page fault handler into the IDT directly - - sub esp,6 ; Allocate space on stack -ifdef USE_NASM - sidt [ss:esp] ; Store pointer to IDT -else - sidt [FWORD ss:esp] ; Store pointer to IDT -endif - pop ax ; add esp,2 - pop eax ; Absolute address of IDT - add eax,14*8 ; Point to Int #14 - -; Note that Interrupt gates do not have the high and low word of the -; offset in adjacent words in memory, there are 4 bytes separating them. - - mov ecx,[eax] ; Get cs and low 16 bits of offset - mov edx,[eax+6] ; Get high 16 bits of offset in dx - shl edx,16 - mov dx,cx ; edx has offset - mov [INT14Offset],edx ; Save offset - shr ecx,16 - mov [INT14Selector],cx ; Save original cs - mov [eax+2],cs ; Install new cs - mov edx,offset PF_handler64k - cmp [UINT bankSize],4 - jne @@1 - mov edx,offset PF_handler4k -@@1: mov [eax],dx ; Install low word of offset - shr edx,16 - mov [eax+6],dx ; Install high word of offset - - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void RemoveFaultHandler(void) -;---------------------------------------------------------------------------- -; Closes down the virtual framebuffer services and restores the previous -; page fault handler. -;---------------------------------------------------------------------------- -cprocstart RemoveFaultHandler - - enter_c - -; Remove page fault handler from IDT - - sub esp,6 ; Allocate space on stack -ifdef USE_NASM - sidt [ss:esp] ; Store pointer to IDT -else - sidt [FWORD ss:esp] ; Store pointer to IDT -endif - - pop ax ; add esp,2 - pop eax ; Absolute address of IDT - add eax,14*8 ; Point to Int #14 - mov cx,[INT14Selector] - mov [eax+2],cx ; Restore original CS - mov edx,[INT14Offset] - mov [eax],dx ; Install low word of offset - shr edx,16 - mov [eax+6],dx ; Install high word of offset - - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void InstallBankFunc(int codeLen,void *bankFunc) -;---------------------------------------------------------------------------- -; Installs the bank switch function by relocating it into our data segment -; and making it into a callable function. We do it this way to make the -; code identical to the way that the VflatD devices work under Windows. -;---------------------------------------------------------------------------- -cprocstart InstallBankFunc - - ARG codeLen:UINT, bankFunc:DPTR - - enter_c - - mov esi,[bankFunc] ; Copy the code into buffer - mov edi,offset BankFuncBuf - mov ecx,[codeLen] - rep movsb - mov [BYTE edi],0C3h ; Terminate the function with a near ret - - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; int InitPaging(void) -;---------------------------------------------------------------------------- -; Initializes paging system. If paging is not enabled, builds a page table -; directory and page tables for physical memory -; -; Exit: 0 - Successful -; -1 - Couldn't initialize paging mechanism -;---------------------------------------------------------------------------- -cprocstart InitPaging - - push ebx - push ecx - push edx - push esi - push edi - -; Are we running under CauseWay? - - mov ax,0FFF9h - int 31h - jc @@NotCauseway - cmp ecx,"CAUS" - jnz @@NotCauseway - cmp edx,"EWAY" - jnz @@NotCauseway - - mov [BOOL VF_haveCauseWay],1 - mov [CauseWayDIRLinear],esi - mov [CauseWay1stLinear],edi - -; Check for DPMI - - mov ax,0ff00h - push es - int 31h - pop es - shr edi,2 - and edi,3 - cmp edi,2 - jz @@ErrExit ; Not supported under DPMI - - mov eax,[CauseWayDIRLinear] - jmp @@CopyCR3 - -@@NotCauseway: - mov ax,cs - test ax,3 ; Which ring are we running - jnz @@ErrExit ; Needs zero ring to access - ; page tables (CR3) - mov eax,cr0 ; Load CR0 - test eax,80000000h ; Is paging enabled? - jz @@ErrExit ; No, we must have paging! - - mov eax,cr3 ; Load directory address - and eax,0FFFFF000h - -@@CopyCR3: - mov [PDBR],eax ; Save it - mov esi,eax - mov edi,offset pageDirectory - mov ecx,1024 - cld - rep movsd ; Copy the original page table directory - cmp [DWORD accessPageAddr],0; Check if we have allocated page - jne @@HaveRealMem ; table already (we cant free it) - - mov eax,0100h ; DPMI DOS allocate - mov ebx,8192/16 - int 31h ; Allocate 8192 bytes - and eax,0FFFFh - shl eax,4 ; EAX points to newly allocated memory - add eax,4095 - and eax,0FFFFF000h ; Page align - mov [accessPageAddr],eax - -@@HaveRealMem: - mov eax,[accessPageAddr] ; EAX -> page table in 1st Mb - shr eax,12 - and eax,3FFh ; Page table offset - shl eax,2 - cmp [BOOL VF_haveCauseWay],0 - jz @@NotCW0 - mov ebx,[CauseWay1stLinear] - jmp @@Put1st - -@@NotCW0: - mov ebx,[PDBR] - mov ebx,[ebx] - and ebx,0FFFFF000h ; Page table for 1st megabyte - -@@Put1st: - add eax,ebx - mov [accessPageTable],eax - sub eax,eax ; No error - jmp @@Exit - -@@ErrExit: - mov eax,-1 - -@@Exit: pop edi - pop esi - pop edx - pop ecx - pop ebx - ret - -cprocend - -;---------------------------------------------------------------------------- -; void ClosePaging(void) -;---------------------------------------------------------------------------- -; Closes the paging system -;---------------------------------------------------------------------------- -cprocstart ClosePaging - - push eax - push ecx - push edx - push esi - push edi - - mov eax,[accessPageAddr] - call AccessPage ; Restore AccessPage mapping - mov edi,[PDBR] - mov esi,offset pageDirectory - mov ecx,1024 - cld - rep movsd ; Restore the original page table directory - -@@Exit: pop edi - pop esi - pop edx - pop ecx - pop eax - ret - -cprocend - -;---------------------------------------------------------------------------- -; long AccessPage(long phys) -;---------------------------------------------------------------------------- -; Maps a known page to given physical memory -; Entry: EAX - Physical memory -; Exit: EAX - Linear memory address of mapped phys mem -;---------------------------------------------------------------------------- -cprocstatic AccessPage - - push edx - mov edx,[accessPageTable] - or eax,7 - mov [edx],eax - mov eax,cr3 - mov cr3,eax ; Update page table cache - mov eax,[accessPageAddr] - pop edx - ret - -cprocend - -;---------------------------------------------------------------------------- -; long GetPhysicalAddress(long linear) -;---------------------------------------------------------------------------- -; Returns the physical address of linear address -; Entry: EAX - Linear address to convert -; Exit: EAX - Physical address -;---------------------------------------------------------------------------- -cprocstatic GetPhysicalAddress - - push ebx - push edx - mov edx,eax - shr edx,22 ; EDX is the directory offset - mov ebx,[PDBR] - mov edx,[edx*4+ebx] ; Load page table address - push eax - mov eax,edx - call AccessPage ; Access the page table - mov edx,eax - pop eax - shr eax,12 - and eax,03FFh ; EAX offset into page table - mov eax,[edx+eax*4] ; Load physical address - and eax,0FFFFF000h - pop edx - pop ebx - ret - -cprocend - -;---------------------------------------------------------------------------- -; void CreatePageTable(long pageDEntry) -;---------------------------------------------------------------------------- -; Creates a page table for specific address (4MB) -; Entry: EAX - Page directory entry (top 10-bits of address) -;---------------------------------------------------------------------------- -cprocstatic CreatePageTable - - push ebx - push ecx - push edx - push edi - mov ebx,eax ; Save address - mov eax,8192 - push eax - call VF_malloc ; Allocate page table directory - add esp,4 - add eax,0FFFh - and eax,0FFFFF000h ; Page align (4KB) - mov edi,eax ; Save page table linear address - sub eax,eax ; Fill with zero - mov ecx,1024 - cld - rep stosd ; Clear page table - sub edi,4096 - mov eax,edi - call GetPhysicalAddress - mov edx,[PDBR] - or eax,7 ; Present/write/user bit - mov [edx+ebx*4],eax ; Save physical address into page directory - mov eax,cr3 - mov cr3,eax ; Update page table cache - pop edi - pop edx - pop ecx - pop ebx - ret - -cprocend - -;---------------------------------------------------------------------------- -; void MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags); -;---------------------------------------------------------------------------- -; Maps physical memory into linear memory -; Entry: pAddr - Physical address -; lAddr - Linear address -; pages - Number of 4K pages to map -; flags - Page flags -; bit 0 = present -; bit 1 = Read(0)/Write(1) -;---------------------------------------------------------------------------- -cprocstart MapPhysical2Linear - - ARG pAddr:ULONG, lAddr:ULONG, pages:UINT, pflags:UINT - - enter_c - - and [ULONG pAddr],0FFFFF000h; Page boundary - and [ULONG lAddr],0FFFFF000h; Page boundary - mov ecx,[pflags] - and ecx,11b ; Just two bits - or ecx,100b ; Supervisor bit - mov [pflags],ecx - - mov edx,[lAddr] - shr edx,22 ; EDX = Directory - mov esi,[PDBR] - mov edi,[pages] ; EDI page count - mov ebx,[lAddr] - -@@CreateLoop: - mov ecx,[esi+edx*4] ; Load page table address - test ecx,1 ; Is it present? - jnz @@TableOK - mov eax,edx - call CreatePageTable ; Create a page table -@@TableOK: - mov eax,ebx - shr eax,12 - and eax,3FFh - sub eax,1024 - neg eax ; EAX = page count in this table - inc edx ; Next table - mov ebx,0 ; Next time we'll map 1K pages - sub edi,eax ; Subtract mapped pages from page count - jns @@CreateLoop ; Create more tables if necessary - - mov ecx,[pages] ; ECX = Page count - mov esi,[lAddr] - shr esi,12 ; Offset part isn't needed - mov edi,[pAddr] -@@MappingLoop: - mov eax,esi - shr eax,10 ; EAX = offset to page directory - mov ebx,[PDBR] - mov eax,[eax*4+ebx] ; EAX = page table address - call AccessPage - mov ebx,esi - and ebx,3FFh ; EBX = offset to page table - mov edx,edi - add edi,4096 ; Next physical address - inc esi ; Next linear page - or edx,[pflags] ; Update flags... - mov [eax+ebx*4],edx ; Store page table entry - loop @@MappingLoop - mov eax,cr3 - mov cr3,eax ; Update page table cache - - leave_c - ret - -cprocend - -endcodeseg _vflat - -endif - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c deleted file mode 100644 index ee117c7..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: DOS -* -* Description: MSDOS specific code for the CPU detection module. -* -****************************************************************************/ - -/*----------------------------- Implementation ----------------------------*/ - -/* External timing function */ - -void __ZTimerInit(void); - -/**************************************************************************** -REMARKS: -Do nothing for DOS because we don't have thread priorities. -****************************************************************************/ -#define SetMaxThreadPriority() 0 - -/**************************************************************************** -REMARKS: -Do nothing for DOS because we don't have thread priorities. -****************************************************************************/ -#define RestoreThreadPriority(i) (void)(i) - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - ulong resolution; - - __ZTimerInit(); - ULZTimerResolution(&resolution); - freq->low = (ulong)(10000000000.0 / resolution); - freq->high = 0; -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. -****************************************************************************/ -#define GetCounter(t) \ -{ \ - (t)->low = ULZReadTime() * 10000L; \ - (t)->high = 0; \ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/event.c b/board/MAI/bios_emulator/scitech/src/pm/dos/event.c deleted file mode 100644 index a969d11..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/event.c +++ /dev/null @@ -1,494 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit DOS -* -* Description: 32-bit DOS implementation for the SciTech cross platform -* event library. -* -****************************************************************************/ - -/*--------------------------- Global variables ----------------------------*/ - -ibool _VARAPI _EVT_useEvents = true; /* True to use event handling */ -ibool _VARAPI _EVT_installed = 0; /* Event handers installed? */ -uchar _VARAPI *_EVT_biosPtr = NULL; /* Pointer to the BIOS data area */ -static ibool haveMouse = false; /* True if we have a mouse */ - -/*---------------------------- Implementation -----------------------------*/ - -/* External assembler functions */ - -void EVTAPI _EVT_pollJoystick(void); -uint EVTAPI _EVT_disableInt(void); -uint EVTAPI _EVT_restoreInt(uint flags); -void EVTAPI _EVT_codeStart(void); -void EVTAPI _EVT_codeEnd(void); -void EVTAPI _EVT_cCodeStart(void); -void EVTAPI _EVT_cCodeEnd(void); -int EVTAPI _EVT_getKeyCode(void); -void EVTAPI _EVT_pumpMessages(void); -int EVTAPI EVT_rdinx(int port,int index); -void EVTAPI EVT_wrinx(int port,int index,int value); - -#ifdef NO_KEYBOARD_INTERRUPT -/**************************************************************************** -REMARKS: -This function is used to pump all keyboard messages from the BIOS keyboard -handler into our event queue. This can be used to avoid using the -installable keyboard handler if this is causing problems. -****************************************************************************/ -static void EVTAPI _EVT_pumpMessages(void) -{ - RMREGS regs; - uint key,ps; - - /* Since the keyboard ISR has not been installed if NO_IDE_BUG has - * been defined, we first check for any pending keyboard events - * here, and if there are some insert them into the event queue to - * be picked up later - what a kludge. - */ - while ((key = _EVT_getKeyCode()) != 0) { - ps = _EVT_disableInt(); - addKeyEvent(EVT_KEYDOWN, key); - _EVT_restoreInt(ps); - } - - regs.x.ax = 0x0B; /* Reset Move Mouse */ - PM_int86(0x33,®s,®s); -} -#endif - -/**************************************************************************** -REMARKS: -This function is used to return the number of ticks since system -startup in milliseconds. This should be the same value that is placed into -the time stamp fields of events, and is used to implement auto mouse down -events. -****************************************************************************/ -ulong _EVT_getTicks(void) -{ - return (ulong)PM_getLong(_EVT_biosPtr+0x6C) * 55UL; -} - -/**************************************************************************** -REMARKS: -Reboots the machine from DOS (warm boot) -****************************************************************************/ -static void Reboot(void) -{ - PMREGS regs; - PMSREGS sregs; - - ushort *rebootType = PM_mapRealPointer(0x40,0x72); - *rebootType = 0x1234; - PM_callRealMode(0xFFFF,0x0000,®s,&sregs); -} - -/**************************************************************************** -REMARKS: -Include generic raw scancode keyboard module. -****************************************************************************/ -#define SUPPORT_CTRL_ALT_DEL -#include "common/keyboard.c" - -/**************************************************************************** -REMARKS: -This function fools the DOS mouse driver into thinking that it is running -in graphics mode, rather than text mode so we always get virtual coordinates -correctly rather than character coordinates. -****************************************************************************/ -int _EVT_foolMouse(void) -{ - int oldmode = PM_getByte(_EVT_biosPtr+0x49); - PM_setByte(_EVT_biosPtr+0x49,0x10); - oldmode |= (EVT_rdinx(0x3C4,0x2) << 8); - return oldmode; -} - -/**************************************************************************** -REMARKS: -This function unfools the DOS mouse driver after we have finished calling it. -****************************************************************************/ -void _EVT_unfoolMouse( - int oldmode) -{ - PM_setByte(_EVT_biosPtr+0x49,oldmode); - - /* Some mouse drivers reset the plane mask register for VGA plane 4 - * modes, which screws up the display on some VGA compatible controllers - * in SuperVGA modes. We reset the value back again in here to solve - * the problem. - */ - EVT_wrinx(0x3C4,0x2,oldmode >> 8); -} - -/**************************************************************************** -REMARKS: -Determines if we have a mouse attached and functioning. -****************************************************************************/ -static ibool detectMouse(void) -{ - RMREGS regs; - RMSREGS sregs; - uchar *p; - ibool retval; - - regs.x.ax = 0x3533; /* Get interrupt vector 0x33 */ - PM_int86x(0x21,®s,®s,&sregs); - - /* Check that interrupt vector 0x33 is not a zero, and that the first - * instruction in the interrupt vector is not an IRET instruction - */ - p = PM_mapRealPointer(sregs.es, regs.x.bx); - retval = ((sregs.es != 0) || (regs.x.bx != 0)) && (PM_getByte(p) != 207); - return retval; -} - -/**************************************************************************** -PARAMETERS: -what - Event code -message - Event message -x,y - Mouse position at time of event -but_stat - Mouse button status at time of event - -REMARKS: -Adds a new mouse event to the event queue. This routine is called from within -the mouse interrupt subroutine, so it must be efficient. - -NOTE: Interrupts MUST be OFF while this routine is called to ensure we have - mutually exclusive access to our internal data structures for - interrupt driven systems (like under DOS). -****************************************************************************/ -static void addMouseEvent( - uint what, - uint message, - int x, - int y, - int mickeyX, - int mickeyY, - uint but_stat) -{ - event_t evt; - - if (EVT.count < EVENTQSIZE) { - /* Save information in event record. */ - evt.when = _EVT_getTicks(); - evt.what = what; - evt.message = message; - evt.modifiers = but_stat; - evt.where_x = x; /* Save mouse event position */ - evt.where_y = y; - evt.relative_x = mickeyX; - evt.relative_y = mickeyY; - evt.modifiers |= EVT.keyModifiers; - addEvent(&evt); /* Add to tail of event queue */ - } -} - -/**************************************************************************** -PARAMETERS: -mask - Event mask -butstate - Button state -x - Mouse x coordinate -y - Mouse y coordinate - -REMARKS: -Mouse event handling routine. This gets called when a mouse event occurs, -and we call the addMouseEvent() routine to add the appropriate mouse event -to the event queue. - -Note: Interrupts are ON when this routine is called by the mouse driver code. -****************************************************************************/ -static void EVTAPI mouseISR( - uint mask, - uint butstate, - int x, - int y, - int mickeyX, - int mickeyY) -{ - uint ps; - uint buttonMask; - - if (mask & 1) { - /* Save the current mouse coordinates */ - EVT.mx = x; EVT.my = y; - - /* If the last event was a movement event, then modify the last - * event rather than post a new one, so that the queue will not - * become saturated. Before we modify the data structures, we - * MUST ensure that interrupts are off. - */ - ps = _EVT_disableInt(); - if (EVT.oldMove != -1) { - EVT.evtq[EVT.oldMove].where_x = x; /* Modify existing one */ - EVT.evtq[EVT.oldMove].where_y = y; - EVT.evtq[EVT.oldMove].relative_x += mickeyX; - EVT.evtq[EVT.oldMove].relative_y += mickeyY; - } - else { - EVT.oldMove = EVT.freeHead; /* Save id of this move event */ - addMouseEvent(EVT_MOUSEMOVE,0,x,y,mickeyX,mickeyY,butstate); - } - _EVT_restoreInt(ps); - } - if (mask & 0x2A) { - ps = _EVT_disableInt(); - buttonMask = 0; - if (mask & 2) buttonMask |= EVT_LEFTBMASK; - if (mask & 8) buttonMask |= EVT_RIGHTBMASK; - if (mask & 32) buttonMask |= EVT_MIDDLEBMASK; - addMouseEvent(EVT_MOUSEDOWN,buttonMask,x,y,0,0,butstate); - EVT.oldMove = -1; - _EVT_restoreInt(ps); - } - if (mask & 0x54) { - ps = _EVT_disableInt(); - buttonMask = 0; - if (mask & 2) buttonMask |= EVT_LEFTBMASK; - if (mask & 8) buttonMask |= EVT_RIGHTBMASK; - if (mask & 32) buttonMask |= EVT_MIDDLEBMASK; - addMouseEvent(EVT_MOUSEUP,buttonMask,x,y,0,0,butstate); - EVT.oldMove = -1; - _EVT_restoreInt(ps); - } - EVT.oldKey = -1; -} - -/**************************************************************************** -REMARKS: -Keyboard interrupt handler function. - -NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, - and we leave them OFF the entire time. -****************************************************************************/ -static void EVTAPI keyboardISR(void) -{ - processRawScanCode(PM_inpb(0x60)); - PM_outpb(0x20,0x20); -} - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _EVT_abort() -{ - EVT_exit(); - PM_fatalError("Unhandled exception!"); -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -void EVTAPI EVT_init( - _EVT_mouseMoveHandler mouseMove) -{ - int i; - - PM_init(); - EVT.mouseMove = mouseMove; - _EVT_biosPtr = PM_getBIOSPointer(); - EVT_resume(); - - /* Grab all characters pending in the keyboard buffer and stuff - * them into our event buffer. This allows us to pick up any keypresses - * while the program is initialising. - */ - while ((i = _EVT_getKeyCode()) != 0) - addKeyEvent(EVT_KEYDOWN,i); -} - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVTAPI EVT_resume(void) -{ - static int locked = 0; - int stat; - uchar mods; - PM_lockHandle lh; /* Unused in DOS */ - - if (_EVT_useEvents) { - /* Initialise the event queue and enable our interrupt handlers */ - initEventQueue(); -#ifndef NO_KEYBOARD_INTERRUPT - PM_setKeyHandler(keyboardISR); -#endif -#ifndef NO_MOUSE_INTERRUPT - if ((haveMouse = detectMouse()) != 0) { - int oldmode = _EVT_foolMouse(); - PM_setMouseHandler(0xFFFF,mouseISR); - _EVT_unfoolMouse(oldmode); - } -#endif - - /* Read the keyboard modifier flags from the BIOS to get the - * correct initialisation state. The only state we care about is - * the correct toggle state flags such as SCROLLLOCK, NUMLOCK and - * CAPSLOCK. - */ - EVT.keyModifiers = 0; - mods = PM_getByte(_EVT_biosPtr+0x17); - if (mods & 0x10) - EVT.keyModifiers |= EVT_SCROLLLOCK; - if (mods & 0x20) - EVT.keyModifiers |= EVT_NUMLOCK; - if (mods & 0x40) - EVT.keyModifiers |= EVT_CAPSLOCK; - - /* Lock all of the code and data used by our protected mode interrupt - * handling routines, so that it will continue to work correctly - * under real mode. - */ - if (!locked) { - /* It is difficult to ensure that we lock our global data, so we - * do this by taking the address of a variable locking all data - * 2Kb on either side. This should properly cover the global data - * used by the module (the other alternative is to declare the - * variables in assembler, in which case we know it will be - * correct). - */ - stat = !PM_lockDataPages(&EVT,sizeof(EVT),&lh); - stat |= !PM_lockDataPages(&_EVT_biosPtr,sizeof(_EVT_biosPtr),&lh); - stat |= !PM_lockCodePages((__codePtr)_EVT_cCodeStart,(int)_EVT_cCodeEnd-(int)_EVT_cCodeStart,&lh); - stat |= !PM_lockCodePages((__codePtr)_EVT_codeStart,(int)_EVT_codeEnd-(int)_EVT_codeStart,&lh); - if (stat) { - PM_fatalError("Page locking services failed - interrupt handling not safe!"); - exit(1); - } - locked = 1; - } - - /* Catch program termination signals so we can clean up properly */ - signal(SIGABRT, _EVT_abort); - signal(SIGFPE, _EVT_abort); - signal(SIGINT, _EVT_abort); - _EVT_installed = true; - } -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - RMREGS regs; - - if (haveMouse) { - int oldmode = _EVT_foolMouse(); - PM_resetMouseDriver(1); - regs.x.ax = 7; /* Mouse function 7 - Set horizontal min and max */ - regs.x.cx = 0; - regs.x.dx = xRes; - PM_int86(0x33,®s,®s); - regs.x.ax = 8; /* Mouse function 8 - Set vertical min and max */ - regs.x.cx = 0; - regs.x.dx = yRes; - PM_int86(0x33,®s,®s); - _EVT_unfoolMouse(oldmode); - } -} - -/**************************************************************************** -REMARKS -Modifes the mouse coordinates as necessary if scaling to OS coordinates, -and sets the OS mouse cursor position. -****************************************************************************/ -void _EVT_setMousePos( - int *x, - int *y) -{ - RMREGS regs; - - if (haveMouse) { - int oldmode = _EVT_foolMouse(); - regs.x.ax = 4; /* Mouse function 4 - Set mouse position */ - regs.x.cx = *x; /* New horizontal coordinate */ - regs.x.dx = *y; /* New vertical coordinate */ - PM_int86(0x33,®s,®s); - _EVT_unfoolMouse(oldmode); - } -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVTAPI EVT_suspend(void) -{ - uchar mods; - - if (_EVT_installed) { - /* Restore the interrupt handlers */ - PM_restoreKeyHandler(); - if (haveMouse) - PM_restoreMouseHandler(); - signal(SIGABRT, SIG_DFL); - signal(SIGFPE, SIG_DFL); - signal(SIGINT, SIG_DFL); - - /* Set the keyboard modifier flags in the BIOS to our values */ - EVT_allowLEDS(true); - mods = PM_getByte(_EVT_biosPtr+0x17) & ~0x70; - if (EVT.keyModifiers & EVT_SCROLLLOCK) - mods |= 0x10; - if (EVT.keyModifiers & EVT_NUMLOCK) - mods |= 0x20; - if (EVT.keyModifiers & EVT_CAPSLOCK) - mods |= 0x40; - PM_setByte(_EVT_biosPtr+0x17,mods); - - /* Flag that we are no longer installed */ - _EVT_installed = false; - } -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVTAPI EVT_exit(void) -{ - EVT_suspend(); -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h deleted file mode 100644 index 35e8e00..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h +++ /dev/null @@ -1,29 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit DOS -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c b/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c deleted file mode 100644 index 2ad9e34..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c +++ /dev/null @@ -1,2243 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 16/32 bit DOS -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include "ztimerc.h" -#include "mtrr.h" -#include "pm_help.h" -#include -#include -#include -#include -#include -#ifdef __GNUC__ -#include -#include -#include -#else -#include -#endif -#ifdef __BORLANDC__ -#pragma warn -par -#endif - -/*--------------------------- Global variables ----------------------------*/ - -typedef struct { - int oldMode; - int old50Lines; - } DOS_stateBuf; - -#define MAX_RM_BLOCKS 10 - -static struct { - void *p; - uint tag; - } rmBlocks[MAX_RM_BLOCKS]; - -static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ -static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ -static uint VESABuf_rseg; /* Real mode segment of VESABuf */ -static uint VESABuf_roff; /* Real mode offset of VESABuf */ -static void (PMAPIP fatalErrorCleanup)(void) = NULL; -ushort _VARAPI _PM_savedDS = 0; -#ifdef DOS4GW -static ulong PDB = 0,*pPDB = NULL; -#endif -#ifndef REALMODE -static char VXD_name[] = PMHELP_NAME; -static char VXD_module[] = PMHELP_MODULE; -static char VXD_DDBName[] = PMHELP_DDBNAME; -static uint VXD_version = -1; -static uint VXD_loadOff = 0; -static uint VXD_loadSel = 0; -uint _VARAPI _PM_VXD_off = 0; -uint _VARAPI _PM_VXD_sel = 0; -int _VARAPI _PM_haveCauseWay = -1; - -/* Memory mapping cache */ - -#define MAX_MEMORY_MAPPINGS 100 -typedef struct { - ulong physical; - ulong linear; - ulong limit; - } mmapping; -static mmapping maps[MAX_MEMORY_MAPPINGS] = {0}; -static int numMaps = 0; - -/* Page sized block cache */ - -#define PAGES_PER_BLOCK 100 -#define FREELIST_NEXT(p) (*(void**)(p)) -typedef struct pageblock { - struct pageblock *next; - struct pageblock *prev; - void *freeListStart; - void *freeList; - void *freeListEnd; - int freeCount; - } pageblock; -static pageblock *pageBlocks = NULL; -#endif - -/* Start of all page tables in CauseWay */ - -#define CW_PAGE_TABLE_START (1024UL*4096UL*1023UL) - -/*----------------------------- Implementation ----------------------------*/ - -/* External assembler functions */ - -ulong _ASMAPI _PM_getPDB(void); -int _ASMAPI _PM_pagingEnabled(void); -void _ASMAPI _PM_VxDCall(VXD_regs *regs,uint off,uint sel); - -#ifndef REALMODE -/**************************************************************************** -REMARKS: -Exit function to unload the dynamically loaded VxD -****************************************************************************/ -static void UnloadVxD(void) -{ - PMSREGS sregs; - VXD_regs r; - - r.eax = 2; - r.ebx = 0; - r.edx = (uint)VXD_module; - PM_segread(&sregs); -#ifdef __16BIT__ - r.ds = ((ulong)VXD_module) >> 16; -#else - r.ds = sregs.ds; -#endif - r.es = sregs.es; - _PM_VxDCall(&r,VXD_loadOff,VXD_loadSel); -} - -/**************************************************************************** -REMARKS: -External function to call the PMHELP helper VxD. -****************************************************************************/ -void PMAPI PM_VxDCall( - VXD_regs *regs) -{ - if (_PM_VXD_sel != 0 || _PM_VXD_off != 0) - _PM_VxDCall(regs,_PM_VXD_off,_PM_VXD_sel); -} - -/**************************************************************************** -RETURNS: -BCD coded version number of the VxD, or 0 if not loaded (ie: 0x202 - 2.2) - -REMARKS: -This function gets the version number for the VxD that we have connected to. -****************************************************************************/ -uint PMAPI PMHELP_getVersion(void) -{ - VXD_regs r; - - /* Call the helper VxD to determine the version number */ - if (_PM_VXD_sel != 0 || _PM_VXD_off != 0) { - memset(&r,0,sizeof(r)); - r.eax = API_NUM(PMHELP_GETVER); - _PM_VxDCall(&r,_PM_VXD_off,_PM_VXD_sel); - return VXD_version = (uint)r.eax; - } - return VXD_version = 0; -} - -/**************************************************************************** -DESCRIPTION: -Connects to the helper VxD and returns the version number - -RETURNS: -True if the VxD was found and loaded, false otherwise. - -REMARKS: -This function connects to the VxD (loading it if it is dynamically loadable) -and returns the version number of the VxD. -****************************************************************************/ -static ibool PMHELP_connect(void) -{ - PMREGS regs; - PMSREGS sregs; - VXD_regs r; - - /* Bail early if we have alread connected */ - if (VXD_version != -1) - return VXD_version != 0; - - /* Get the static SDDHELP.VXD entry point if available */ - PM_segread(&sregs); - regs.x.ax = 0x1684; - regs.x.bx = SDDHELP_DeviceID; - regs.x.di = 0; - sregs.es = 0; - PM_int386x(0x2F,®s,®s,&sregs); - _PM_VXD_sel = sregs.es; - _PM_VXD_off = regs.x.di; - if (_PM_VXD_sel != 0 || _PM_VXD_off != 0) { - if (PMHELP_getVersion() >= PMHELP_VERSION) - return true; - } - - /* If we get here, then either SDDHELP.VXD is not loaded, or it is an - * earlier version. In this case try to dynamically load the PMHELP.VXD - * helper VxD instead. - */ - PM_segread(&sregs); - regs.x.ax = 0x1684; - regs.x.bx = VXDLDR_DeviceID; - regs.x.di = 0; - sregs.es = 0; - PM_int386x(0x2F,®s,®s,&sregs); - VXD_loadSel = sregs.es; - VXD_loadOff = regs.x.di; - if (VXD_loadSel == 0 && VXD_loadOff == 0) - return VXD_version = 0; - r.eax = 1; - r.ebx = 0; - r.edx = (uint)VXD_name; - PM_segread(&sregs); - r.ds = sregs.ds; - r.es = sregs.es; - _PM_VxDCall(&r,VXD_loadOff,VXD_loadSel); - if (r.eax != 0) - return VXD_version = 0; - - /* Get the dynamic VxD entry point so we can call it */ - atexit(UnloadVxD); - PM_segread(&sregs); - regs.x.ax = 0x1684; - regs.x.bx = 0; - regs.e.edi = (uint)VXD_DDBName; - PM_int386x(0x2F,®s,®s,&sregs); - _PM_VXD_sel = sregs.es; - _PM_VXD_off = regs.x.di; - if (_PM_VXD_sel == 0 && _PM_VXD_off == 0) - return VXD_version = 0; - if (PMHELP_getVersion() >= PMHELP_VERSION) - return true; - return VXD_version = 0; -} -#endif - -/**************************************************************************** -REMARKS: -Initialise the PM library. First we try to connect to a static SDDHELP.VXD -helper VxD, and check that it is a version we can use. If not we try to -dynamically load the PMHELP.VXD helper VxD -****************************************************************************/ -void PMAPI PM_init(void) -{ -#ifndef REALMODE - PMREGS regs; - - /* Check if we are running under CauseWay under real DOS */ - if (_PM_haveCauseWay == -1) { - /* Check if we are running under DPMI in which case we will not be - * able to use our special ring 0 CauseWay functions. - */ - _PM_haveCauseWay = false; - regs.x.ax = 0xFF00; - PM_int386(0x31,®s,®s); - if (regs.x.cflag || !(regs.e.edi & 8)) { - /* We are not under DPMI, so now check if CauseWay is active */ - regs.x.ax = 0xFFF9; - PM_int386(0x31,®s,®s); - if (!regs.x.cflag && regs.e.ecx == 0x43415553 && regs.e.edx == 0x45574159) - _PM_haveCauseWay = true; - } - - /* Now connect to PMHELP.VXD and initialise MTRR module */ - if (!PMHELP_connect()) - MTRR_init(); - } -#endif -} - -/**************************************************************************** -PARAMETERS: -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -RETURNS: -Error code describing the result. - -REMARKS: -Function to enable write combining for the specified region of memory. -****************************************************************************/ -int PMAPI PM_enableWriteCombine( - ulong base, - ulong size, - uint type) -{ -#ifndef REALMODE - VXD_regs regs; - - if (PMHELP_connect()) { - memset(®s,0,sizeof(regs)); - regs.eax = API_NUM(PMHELP_ENABLELFBCOMB); - regs.ebx = base; - regs.ecx = size; - regs.edx = type; - _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); - return regs.eax; - } - return MTRR_enableWriteCombine(base,size,type); -#else - return PM_MTRR_NOT_SUPPORTED; -#endif -} - -ibool PMAPI PM_haveBIOSAccess(void) -{ return true; } - -long PMAPI PM_getOSType(void) -{ return _OS_DOS; } - -int PMAPI PM_getModeType(void) -{ -#if defined(REALMODE) - return PM_realMode; -#elif defined(PM286) - return PM_286; -#elif defined(PM386) - return PM_386; -#endif -} - -void PMAPI PM_backslash(char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '\\') { - s[pos] = '\\'; - s[pos+1] = '\0'; - } -} - -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -void PMAPI PM_fatalError(const char *msg) -{ - if (fatalErrorCleanup) - fatalErrorCleanup(); - fprintf(stderr,"%s\n", msg); - exit(1); -} - -static void ExitVBEBuf(void) -{ - if (VESABuf_ptr) - PM_freeRealSeg(VESABuf_ptr); - VESABuf_ptr = 0; -} - -void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) -{ - if (!VESABuf_ptr) { - /* Allocate a global buffer for communicating with the VESA VBE */ - if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) - return NULL; - atexit(ExitVBEBuf); - } - *len = VESABuf_len; - *rseg = VESABuf_rseg; - *roff = VESABuf_roff; - return VESABuf_ptr; -} - -int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out) -{ - PMSREGS sregs; - PM_segread(&sregs); - return PM_int386x(intno,in,out,&sregs); -} - -/* Routines to set and get the real mode interrupt vectors, by making - * direct real mode calls to DOS and bypassing the DOS extenders API. - * This is the safest way to handle this, as some servers try to be - * smart about changing real mode vectors. - */ - -void PMAPI _PM_getRMvect(int intno, long *realisr) -{ - RMREGS regs; - RMSREGS sregs; - - PM_saveDS(); - regs.h.ah = 0x35; - regs.h.al = intno; - PM_int86x(0x21, ®s, ®s, &sregs); - *realisr = ((long)sregs.es << 16) | regs.x.bx; -} - -void PMAPI _PM_setRMvect(int intno, long realisr) -{ - RMREGS regs; - RMSREGS sregs; - - PM_saveDS(); - regs.h.ah = 0x25; - regs.h.al = intno; - sregs.ds = (int)(realisr >> 16); - regs.x.dx = (int)(realisr & 0xFFFF); - PM_int86x(0x21, ®s, ®s, &sregs); -} - -void PMAPI _PM_addRealModeBlock(void *mem,uint tag) -{ - int i; - - for (i = 0; i < MAX_RM_BLOCKS; i++) { - if (rmBlocks[i].p == NULL) { - rmBlocks[i].p = mem; - rmBlocks[i].tag = tag; - return; - } - } - PM_fatalError("To many real mode memory block allocations!"); -} - -uint PMAPI _PM_findRealModeBlock(void *mem) -{ - int i; - - for (i = 0; i < MAX_RM_BLOCKS; i++) { - if (rmBlocks[i].p == mem) - return rmBlocks[i].tag; - } - PM_fatalError("Could not find prior real mode memory block allocation!"); - return 0; -} - -char * PMAPI PM_getCurrentPath( - char *path, - int maxLen) -{ - return getcwd(path,maxLen); -} - -char PMAPI PM_getBootDrive(void) -{ return 'C'; } - -const char * PMAPI PM_getVBEAFPath(void) -{ return "c:\\"; } - -const char * PMAPI PM_getNucleusPath(void) -{ - static char path[256]; - char *env; - - if ((env = getenv("NUCLEUS_PATH")) != NULL) - return env; - if ((env = getenv("WINBOOTDIR")) != NULL) { - /* Running in a Windows 9x DOS box or DOS mode */ - strcpy(path,env); - strcat(path,"\\system\\nucleus"); - return path; - } - if ((env = getenv("SystemRoot")) != NULL) { - /* Running in an NT/2K DOS box */ - strcpy(path,env); - strcat(path,"\\system32\\nucleus"); - return path; - } - return "c:\\nucleus"; -} - -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[256]; - strcpy(path,PM_getNucleusPath()); - PM_backslash(path); - strcat(path,"config"); - return path; -} - -const char * PMAPI PM_getUniqueID(void) -{ return "DOS"; } - -const char * PMAPI PM_getMachineName(void) -{ return "DOS"; } - -int PMAPI PM_kbhit(void) -{ - return kbhit(); -} - -int PMAPI PM_getch(void) -{ - return getch(); -} - -PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen) -{ - /* Not used for DOS */ - (void)hwndUser; - (void)device; - (void)xRes; - (void)yRes; - (void)bpp; - (void)fullScreen; - return 0; -} - -int PMAPI PM_getConsoleStateSize(void) -{ - return sizeof(DOS_stateBuf); -} - -void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole) -{ - RMREGS regs; - DOS_stateBuf *sb = stateBuf; - - /* Save the old video mode state */ - regs.h.ah = 0x0F; - PM_int86(0x10,®s,®s); - sb->oldMode = regs.h.al & 0x7F; - sb->old50Lines = false; - if (sb->oldMode == 0x3) { - regs.x.ax = 0x1130; - regs.x.bx = 0; - regs.x.dx = 0; - PM_int86(0x10,®s,®s); - sb->old50Lines = (regs.h.dl == 42 || regs.h.dl == 49); - } - (void)hwndConsole; -} - -void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) -{ - /* Not used for DOS */ - (void)saveState; -} - -void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) -{ - RMREGS regs; - const DOS_stateBuf *sb = stateBuf; - - /* Retore 50 line mode if set */ - if (sb->old50Lines) { - regs.x.ax = 0x1112; - regs.x.bx = 0; - PM_int86(0x10,®s,®s); - } - (void)hwndConsole; -} - -void PMAPI PM_closeConsole(PM_HWND hwndConsole) -{ - /* Not used for DOS */ - (void)hwndConsole; -} - -void PMAPI PM_setOSCursorLocation(int x,int y) -{ - uchar *_biosPtr = PM_getBIOSPointer(); - PM_setByte(_biosPtr+0x50,x); - PM_setByte(_biosPtr+0x51,y); -} - -void PMAPI PM_setOSScreenWidth(int width,int height) -{ - uchar *_biosPtr = PM_getBIOSPointer(); - PM_setWord(_biosPtr+0x4A,width); - PM_setWord(_biosPtr+0x4C,width*2); - PM_setByte(_biosPtr+0x84,height-1); - if (height > 25) { - PM_setWord(_biosPtr+0x60,0x0607); - PM_setByte(_biosPtr+0x85,0x08); - } - else { - PM_setWord(_biosPtr+0x60,0x0D0E); - PM_setByte(_biosPtr+0x85,0x016); - } -} - -void * PMAPI PM_mallocShared(long size) -{ - return PM_malloc(size); -} - -void PMAPI PM_freeShared(void *ptr) -{ - PM_free(ptr); -} - -#define GetRMVect(intno,isr) *(isr) = ((ulong*)rmZeroPtr)[intno] -#define SetRMVect(intno,isr) ((ulong*)rmZeroPtr)[intno] = (isr) - -ibool PMAPI PM_doBIOSPOST( - ushort axVal, - ulong BIOSPhysAddr, - void *mappedBIOS, - ulong BIOSLen) -{ - static int firstTime = true; - static uchar *rmZeroPtr; - long Current10,Current6D,Current42; - RMREGS regs; - RMSREGS sregs; - - /* Create a zero memory mapping for us to use */ - if (firstTime) { - rmZeroPtr = PM_mapPhysicalAddr(0,0x7FFF,true); - firstTime = false; - } - - /* Remap the secondary BIOS to 0xC0000 physical */ - if (BIOSPhysAddr != 0xC0000L || BIOSLen > 32768) { - /* DOS cannot virtually remap the BIOS, so we can only work if all - * the secondary controllers are identical, and we then use the - * BIOS on the first controller for all the remaining controllers. - * - * For OS'es that do virtual memory, and remapping of 0xC0000 - * physical (perhaps a copy on write mapping) should be all that - * is needed. - */ - return false; - } - - /* Save current handlers of int 10h and 6Dh */ - GetRMVect(0x10,&Current10); - GetRMVect(0x6D,&Current6D); - - /* POST the secondary BIOS */ - GetRMVect(0x42,&Current42); - SetRMVect(0x10,Current42); /* Restore int 10h to STD-BIOS */ - regs.x.ax = axVal; - PM_callRealMode(0xC000,0x0003,®s,&sregs); - - /* Restore current handlers */ - SetRMVect(0x10,Current10); - SetRMVect(0x6D,Current6D); - - /* Second the primary BIOS mappin 1:1 for 0xC0000 physical */ - if (BIOSPhysAddr != 0xC0000L) { - /* DOS does not support this */ - (void)mappedBIOS; - } - return true; -} - -void PMAPI PM_sleep(ulong milliseconds) -{ - ulong microseconds = milliseconds * 1000L; - LZTimerObject tm; - - LZTimerOnExt(&tm); - while (LZTimerLapExt(&tm) < microseconds) - ; - LZTimerOffExt(&tm); -} - -int PMAPI PM_getCOMPort(int port) -{ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - } - return 0; -} - -int PMAPI PM_getLPTPort(int port) -{ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -PM_MODULE PMAPI PM_loadLibrary( - const char *szDLLName) -{ - (void)szDLLName; - return NULL; -} - -void * PMAPI PM_getProcAddress( - PM_MODULE hModule, - const char *szProcName) -{ - (void)hModule; - (void)szProcName; - return NULL; -} - -void PMAPI PM_freeLibrary( - PM_MODULE hModule) -{ - (void)hModule; -} - -int PMAPI PM_setIOPL( - int level) -{ - return level; -} - -/**************************************************************************** -REMARKS: -Internal function to convert the find data to the generic interface. -****************************************************************************/ -static void convertFindData( - PM_findData *findData, - struct find_t *blk) -{ - ulong dwSize = findData->dwSize; - - memset(findData,0,findData->dwSize); - findData->dwSize = dwSize; - if (blk->attrib & _A_RDONLY) - findData->attrib |= PM_FILE_READONLY; - if (blk->attrib & _A_SUBDIR) - findData->attrib |= PM_FILE_DIRECTORY; - if (blk->attrib & _A_ARCH) - findData->attrib |= PM_FILE_ARCHIVE; - if (blk->attrib & _A_HIDDEN) - findData->attrib |= PM_FILE_HIDDEN; - if (blk->attrib & _A_SYSTEM) - findData->attrib |= PM_FILE_SYSTEM; - findData->sizeLo = blk->size; - strncpy(findData->name,blk->name,PM_MAX_PATH); - findData->name[PM_MAX_PATH-1] = 0; -} - -#define FIND_MASK (_A_RDONLY | _A_ARCH | _A_SUBDIR | _A_HIDDEN | _A_SYSTEM) - -/**************************************************************************** -REMARKS: -Function to find the first file matching a search criteria in a directory. -****************************************************************************/ -void * PMAPI PM_findFirstFile( - const char *filename, - PM_findData *findData) -{ - struct find_t *blk; - - if ((blk = PM_malloc(sizeof(*blk))) == NULL) - return PM_FILE_INVALID; - if (_dos_findfirst((char*)filename,FIND_MASK,blk) == 0) { - convertFindData(findData,blk); - return blk; - } - return PM_FILE_INVALID; -} - -/**************************************************************************** -REMARKS: -Function to find the next file matching a search criteria in a directory. -****************************************************************************/ -ibool PMAPI PM_findNextFile( - void *handle, - PM_findData *findData) -{ - struct find_t *blk = handle; - - if (_dos_findnext(blk) == 0) { - convertFindData(findData,blk); - return true; - } - return false; -} - -/**************************************************************************** -REMARKS: -Function to close the find process -****************************************************************************/ -void PMAPI PM_findClose( - void *handle) -{ - PM_free(handle); -} - -/**************************************************************************** -REMARKS: -Function to determine if a drive is a valid drive or not. Under Unix this -function will return false for anything except a value of 3 (considered -the root drive, and equivalent to C: for non-Unix systems). The drive -numbering is: - - 1 - Drive A: - 2 - Drive B: - 3 - Drive C: - etc - -****************************************************************************/ -ibool PMAPI PM_driveValid( - char drive) -{ - RMREGS regs; - regs.h.dl = (uchar)(drive - 'A' + 1); - regs.h.ah = 0x36; /* Get disk information service */ - PM_int86(0x21,®s,®s); - return regs.x.ax != 0xFFFF; /* AX = 0xFFFF if disk is invalid */ -} - -/**************************************************************************** -REMARKS: -Function to get the current working directory for the specififed drive. -Under Unix this will always return the current working directory regardless -of what the value of 'drive' is. -****************************************************************************/ -void PMAPI PM_getdcwd( - int drive, - char *dir, - int len) -{ - uint oldDrive,maxDrives; - _dos_getdrive(&oldDrive); - _dos_setdrive(drive,&maxDrives); - getcwd(dir,len); - _dos_setdrive(oldDrive,&maxDrives); -} - -/**************************************************************************** -REMARKS: -Function to change the file attributes for a specific file. -****************************************************************************/ -void PMAPI PM_setFileAttr( - const char *filename, - uint attrib) -{ -#if defined(TNT) && defined(_MSC_VER) - DWORD attr = 0; - - if (attrib & PM_FILE_READONLY) - attr |= FILE_ATTRIBUTE_READONLY; - if (attrib & PM_FILE_ARCHIVE) - attr |= FILE_ATTRIBUTE_ARCHIVE; - if (attrib & PM_FILE_HIDDEN) - attr |= FILE_ATTRIBUTE_HIDDEN; - if (attrib & PM_FILE_SYSTEM) - attr |= FILE_ATTRIBUTE_SYSTEM; - SetFileAttributes((LPSTR)filename, attr); -#else - uint attr = 0; - - if (attrib & PM_FILE_READONLY) - attr |= _A_RDONLY; - if (attrib & PM_FILE_ARCHIVE) - attr |= _A_ARCH; - if (attrib & PM_FILE_HIDDEN) - attr |= _A_HIDDEN; - if (attrib & PM_FILE_SYSTEM) - attr |= _A_SYSTEM; - _dos_setfileattr(filename,attr); -#endif -} - -/**************************************************************************** -REMARKS: -Function to create a directory. -****************************************************************************/ -ibool PMAPI PM_mkdir( - const char *filename) -{ -#ifdef __GNUC__ - return mkdir(filename,S_IRUSR) == 0; -#else - return mkdir(filename) == 0; -#endif -} - -/**************************************************************************** -REMARKS: -Function to remove a directory. -****************************************************************************/ -ibool PMAPI PM_rmdir( - const char *filename) -{ - return rmdir(filename) == 0; -} - -/*-------------------------------------------------------------------------*/ -/* Generic DPMI routines common to 16/32 bit code */ -/*-------------------------------------------------------------------------*/ - -#ifndef REALMODE -ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit) -{ - PMREGS r; - int i; - ulong baseAddr,baseOfs,roundedLimit; - - /* We can't map memory below 1Mb, but the linear address are already - * mapped 1:1 for this memory anyway so we just return the base address. - */ - if (physAddr < 0x100000L) - return physAddr; - - /* Search table of existing mappings to see if we have already mapped - * a region of memory that will serve this purpose. We do this because - * DPMI 0.9 does not allow us to free physical memory mappings, and if - * the mappings get re-used in the program we want to avoid allocating - * more mappings than necessary. - */ - for (i = 0; i < numMaps; i++) { - if (maps[i].physical == physAddr && maps[i].limit == limit) - return maps[i].linear; - } - - /* Find a free slot in our physical memory mapping table */ - for (i = 0; i < numMaps; i++) { - if (maps[i].limit == 0) - break; - } - if (i == numMaps) { - i = numMaps++; - if (i == MAX_MEMORY_MAPPINGS) - return NULL; - } - - /* Round the physical address to a 4Kb boundary and the limit to a - * 4Kb-1 boundary before passing the values to DPMI as some extenders - * will fail the calls unless this is the case. If we round the - * physical address, then we also add an extra offset into the address - * that we return. - */ - baseOfs = physAddr & 4095; - baseAddr = physAddr & ~4095; - roundedLimit = ((limit+baseOfs+1+4095) & ~4095)-1; - r.x.ax = 0x800; - r.x.bx = baseAddr >> 16; - r.x.cx = baseAddr & 0xFFFF; - r.x.si = roundedLimit >> 16; - r.x.di = roundedLimit & 0xFFFF; - PM_int386(0x31, &r, &r); - if (r.x.cflag) - return 0xFFFFFFFFUL; - maps[i].physical = physAddr; - maps[i].limit = limit; - maps[i].linear = ((ulong)r.x.bx << 16) + r.x.cx + baseOfs; - return maps[i].linear; -} - -int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr) -{ - PMREGS r; - - r.x.ax = 7; /* DPMI set selector base address */ - r.x.bx = sel; - r.x.cx = linAddr >> 16; - r.x.dx = linAddr & 0xFFFF; - PM_int386(0x31, &r, &r); - if (r.x.cflag) - return 0; - return 1; -} - -ulong PMAPI DPMI_getSelectorBase(ushort sel) -{ - PMREGS r; - - r.x.ax = 6; /* DPMI get selector base address */ - r.x.bx = sel; - PM_int386(0x31, &r, &r); - return ((ulong)r.x.cx << 16) + r.x.dx; -} - -int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit) -{ - PMREGS r; - - r.x.ax = 8; /* DPMI set selector limit */ - r.x.bx = sel; - r.x.cx = limit >> 16; - r.x.dx = limit & 0xFFFF; - PM_int386(0x31, &r, &r); - if (r.x.cflag) - return 0; - return 1; -} - -uint PMAPI DPMI_createSelector(ulong base,ulong limit) -{ - uint sel; - PMREGS r; - - /* Allocate 1 descriptor */ - r.x.ax = 0; - r.x.cx = 1; - PM_int386(0x31, &r, &r); - if (r.x.cflag) return 0; - sel = r.x.ax; - - /* Set the descriptor access rights (for a 32 bit page granular - * segment). - */ - if (limit >= 0x10000L) { - r.x.ax = 9; - r.x.bx = sel; - r.x.cx = 0x40F3; - PM_int386(0x31, &r, &r); - } - - /* Map physical memory and create selector */ - if ((base = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFFUL) - return 0; - if (!DPMI_setSelectorBase(sel,base)) - return 0; - if (!DPMI_setSelectorLimit(sel,limit)) - return 0; - return sel; -} - -void PMAPI DPMI_freeSelector(uint sel) -{ - PMREGS r; - - r.x.ax = 1; - r.x.bx = sel; - PM_int386(0x31, &r, &r); -} - -int PMAPI DPMI_lockLinearPages(ulong linear,ulong len) -{ - PMREGS r; - - r.x.ax = 0x600; /* DPMI Lock Linear Region */ - r.x.bx = (linear >> 16); /* Linear address in BX:CX */ - r.x.cx = (linear & 0xFFFF); - r.x.si = (len >> 16); /* Length in SI:DI */ - r.x.di = (len & 0xFFFF); - PM_int386(0x31, &r, &r); - return (!r.x.cflag); -} - -int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len) -{ - PMREGS r; - - r.x.ax = 0x601; /* DPMI Unlock Linear Region */ - r.x.bx = (linear >> 16); /* Linear address in BX:CX */ - r.x.cx = (linear & 0xFFFF); - r.x.si = (len >> 16); /* Length in SI:DI */ - r.x.di = (len & 0xFFFF); - PM_int386(0x31, &r, &r); - return (!r.x.cflag); -} - -/**************************************************************************** -REMARKS: -Adjust the page table caching bits directly. Requires ring 0 access and -only works with DOS4GW and compatible extenders (CauseWay also works since -it has direct support for the ring 0 instructions we need from ring 3). Will -not work in a DOS box, but we call into the ring 0 helper VxD so we should -never get here in a DOS box anyway (assuming the VxD is present). If we -do get here and we are in windows, this code will be skipped. -****************************************************************************/ -static void PM_adjustPageTables( - ulong linear, - ulong limit, - ibool isCached) -{ -#ifdef DOS4GW - int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; - ulong andMask,orMask,pageTable,*pPageTable; - - andMask = ~0x18; - orMask = (isCached) ? 0x00 : 0x18; - if (_PM_pagingEnabled() == 1 && (PDB = _PM_getPDB()) != 0) { - if (_PM_haveCauseWay) { - /* CauseWay is a little different in the page table handling. - * The code that we use for DOS4G/W does not appear to work - * with CauseWay correctly as it does not appear to allow us - * to map the page tables directly. Instead we can directly - * access the page table entries in extended memory where - * CauseWay always locates them (starting at 1024*4096*1023) - */ - startPage = (linear >> 12); - endPage = ((linear+limit) >> 12); - pPageTable = (ulong*)CW_PAGE_TABLE_START; - for (iPage = startPage; iPage <= endPage; iPage++) - pPageTable[iPage] = (pPageTable[iPage] & andMask) | orMask; - } - else { - pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF); - if (pPDB) { - startPDB = (linear >> 22) & 0x3FF; - startPage = (linear >> 12) & 0x3FF; - endPDB = ((linear+limit) >> 22) & 0x3FF; - endPage = ((linear+limit) >> 12) & 0x3FF; - for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { - pageTable = pPDB[iPDB] & ~0xFFF; - pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF); - start = (iPDB == startPDB) ? startPage : 0; - end = (iPDB == endPDB) ? endPage : 0x3FF; - for (iPage = start; iPage <= end; iPage++) - pPageTable[iPage] = (pPageTable[iPage] & andMask) | orMask; - } - } - } - PM_flushTLB(); - } -#endif -} - -void * PMAPI DPMI_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) -{ - PMSREGS sregs; - ulong linAddr; - ulong DSBaseAddr; - - /* Get the base address for the default DS selector */ - PM_segread(&sregs); - DSBaseAddr = DPMI_getSelectorBase(sregs.ds); - if ((base < 0x100000) && (DSBaseAddr == 0)) { - /* DS is zero based, so we can directly access the first 1Mb of - * system memory (like under DOS4GW). - */ - return (void*)base; - } - - /* Map the memory to a linear address using DPMI function 0x800 */ - if ((linAddr = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFF) { - if (base >= 0x100000) - return NULL; - /* If the linear address mapping fails but we are trying to - * map an area in the first 1Mb of system memory, then we must - * be running under a Windows or OS/2 DOS box. Under these - * environments we can use the segment wrap around as a fallback - * measure, as this does work properly. - */ - linAddr = base; - } - - /* Now expand the default DS selector to 4Gb so we can access it */ - if (!DPMI_setSelectorLimit(sregs.ds,0xFFFFFFFFUL)) - return NULL; - - /* Finally enable caching for the page tables that we just mapped in, - * since DOS4GW and PMODE/W create the page table entries without - * caching enabled which hurts the performance of the linear framebuffer - * as it disables write combining on Pentium Pro and above processors. - * - * For those processors cache disabling is better handled through the - * MTRR registers anyway (we can write combine a region but disable - * caching) so that MMIO register regions do not screw up. - */ - if (DSBaseAddr == 0) - PM_adjustPageTables(linAddr,limit,isCached); - - /* Now return the base address of the memory into the default DS */ - return (void*)(linAddr - DSBaseAddr); -} - -#if defined(PM386) - -/* Some DOS extender implementations do not directly support calling a - * real mode procedure from protected mode. However we can simulate what - * we need temporarily hooking the INT 6Ah vector with a small real mode - * stub that will call our real mode code for us. - */ - -static uchar int6AHandler[] = { - 0x00,0x00,0x00,0x00, /* __PMODE_callReal variable */ - 0xFB, /* sti */ - 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PMODE_callReal] */ - 0xCF, /* iretf */ - }; -static uchar *crPtr = NULL; /* Pointer to of int 6A handler */ -static uint crRSeg,crROff; /* Real mode seg:offset of handler */ - -void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, - RMSREGS *sregs) -{ - uchar *p; - uint oldSeg,oldOff; - - if (!crPtr) { - /* Allocate and copy the memory block only once */ - crPtr = PM_allocRealSeg(sizeof(int6AHandler), &crRSeg, &crROff); - memcpy(crPtr,int6AHandler,sizeof(int6AHandler)); - } - PM_setWord(crPtr,off); /* Plug in address to call */ - PM_setWord(crPtr+2,seg); - p = PM_mapRealPointer(0,0x6A * 4); - oldOff = PM_getWord(p); /* Save old handler address */ - oldSeg = PM_getWord(p+2); - PM_setWord(p,crROff+4); /* Hook 6A handler */ - PM_setWord(p+2,crRSeg); - PM_int86x(0x6A, in, in, sregs); /* Call real mode code */ - PM_setWord(p,oldOff); /* Restore old handler */ - PM_setWord(p+2,oldSeg); -} - -#endif /* PM386 */ - -#endif /* !REALMODE */ - -/**************************************************************************** -REMARKS: -Allocates a block of locked, physically contiguous memory. The memory -may be required to be below the 16Meg boundary. -****************************************************************************/ -void * PMAPI PM_allocLockedMem( - uint size, - ulong *physAddr, - ibool contiguous, - ibool below16Meg) -{ - uchar *p,*roundedP; - uint r_seg,r_off; - uint roundedSize = (size + 4 + 0xFFF) & ~0xFFF; - PM_lockHandle lh; /* Unused in DOS */ -#ifndef REALMODE - VXD_regs regs; - - /* If we have connected to our helper VxD in a Windows DOS box, use the - * helper VxD services to allocate the memory that we need. - */ - if (VXD_version) { - memset(®s,0,sizeof(regs)); - regs.eax = API_NUM(PMHELP_ALLOCLOCKED); - regs.ebx = size; - regs.ecx = (ulong)physAddr; - regs.edx = contiguous | (below16Meg << 8); - _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); - return (void*)regs.eax; - } - - /* If the memory is not contiguous, we simply need to allocate it - * using regular memory allocation services, and lock it down - * in memory. - * - * For contiguous memory blocks, the only way to guarantee contiguous physical - * memory addresses under DOS is to allocate the memory below the - * 1Meg boundary as real mode memory. - * - * Note that we must page align the memory block, and we also must - * keep track of the non-aligned pointer so we can properly free - * it later. Hence we actually allocate 4 bytes more than the - * size rounded up to the next 4K boundary. - */ - if (!contiguous) - p = PM_malloc(roundedSize); - else -#endif - p = PM_allocRealSeg(roundedSize,&r_seg,&r_off); - if (p == NULL) - return NULL; - roundedP = (void*)(((ulong)p + 0xFFF) & ~0xFFF); - *((ulong*)(roundedP + size)) = (ulong)p; - PM_lockDataPages(roundedP,size,&lh); - if ((*physAddr = PM_getPhysicalAddr(roundedP)) == 0xFFFFFFFF) { - PM_freeLockedMem(roundedP,size,contiguous); - return NULL; - } - - /* Disable caching for the memory since it is probably a DMA buffer */ -#ifndef REALMODE - PM_adjustPageTables((ulong)roundedP,size-1,false); -#endif - return roundedP; -} - -/**************************************************************************** -REMARKS: -Free a block of locked memory. -****************************************************************************/ -void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) -{ -#ifndef REALMODE - VXD_regs regs; - PM_lockHandle lh; /* Unused in DOS */ - - if (!p) - return; - if (VXD_version) { - memset(®s,0,sizeof(regs)); - regs.eax = API_NUM(PMHELP_FREELOCKED); - regs.ebx = (ulong)p; - regs.ecx = size; - regs.edx = contiguous; - _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); - return; - } - PM_unlockDataPages(p,size,&lh); - if (!contiguous) - free(*((void**)((uchar*)p + size))); - else -#endif - PM_freeRealSeg(*((void**)((char*)p + size))); -} - -#ifndef REALMODE -/**************************************************************************** -REMARKS: -Allocates a new block of pages for the page block manager. -****************************************************************************/ -static pageblock *PM_addNewPageBlock(void) -{ - int i,size; - pageblock *newBlock; - char *p,*next; - - /* Allocate memory for the new page block, and add to head of list */ - size = PAGES_PER_BLOCK * PM_PAGE_SIZE + (PM_PAGE_SIZE-1) + sizeof(pageblock); - if ((newBlock = PM_malloc(size)) == NULL) - return NULL; - newBlock->prev = NULL; - newBlock->next = pageBlocks; - if (pageBlocks) - pageBlocks->prev = newBlock; - pageBlocks = newBlock; - - /* Initialise the page aligned free list for the page block */ - newBlock->freeCount = PAGES_PER_BLOCK; - newBlock->freeList = p = (char*)(((ulong)(newBlock + 1) + (PM_PAGE_SIZE-1)) & ~(PM_PAGE_SIZE-1)); - newBlock->freeListStart = newBlock->freeList; - newBlock->freeListEnd = p + (PAGES_PER_BLOCK-1) * PM_PAGE_SIZE; - for (i = 0; i < PAGES_PER_BLOCK; i++,p = next) - FREELIST_NEXT(p) = next = p + PM_PAGE_SIZE; - FREELIST_NEXT(p - PM_PAGE_SIZE) = NULL; - return newBlock; -} -#endif - -/**************************************************************************** -REMARKS: -Allocates a page aligned and page sized block of memory -****************************************************************************/ -void * PMAPI PM_allocPage( - ibool locked) -{ -#ifndef REALMODE - VXD_regs regs; - pageblock *block; - void *p; - PM_lockHandle lh; /* Unused in DOS */ - - /* Call the helper VxD for this service if we are running in a DOS box */ - if (VXD_version) { - memset(®s,0,sizeof(regs)); - regs.eax = API_NUM(PMHELP_ALLOCPAGE); - regs.ebx = locked; - _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); - return (void*)regs.eax; - } - - /* Scan the block list looking for any free blocks. Allocate a new - * page block if no free blocks are found. - */ - for (block = pageBlocks; block != NULL; block = block->next) { - if (block->freeCount) - break; - } - if (block == NULL && (block = PM_addNewPageBlock()) == NULL) - return NULL; - block->freeCount--; - p = block->freeList; - block->freeList = FREELIST_NEXT(p); - if (locked) - PM_lockDataPages(p,PM_PAGE_SIZE,&lh); - return p; -#else - return NULL; -#endif -} - -/**************************************************************************** -REMARKS: -Free a page aligned and page sized block of memory -****************************************************************************/ -void PMAPI PM_freePage( - void *p) -{ -#ifndef REALMODE - VXD_regs regs; - pageblock *block; - - /* Call the helper VxD for this service if we are running in a DOS box */ - if (VXD_version) { - memset(®s,0,sizeof(regs)); - regs.eax = API_NUM(PMHELP_FREEPAGE); - regs.ebx = (ulong)p; - _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); - return; - } - - /* First find the page block that this page belongs to */ - for (block = pageBlocks; block != NULL; block = block->next) { - if (p >= block->freeListStart && p <= block->freeListEnd) - break; - } - CHECK(block != NULL); - - /* Now free the block by adding it to the free list */ - FREELIST_NEXT(p) = block->freeList; - block->freeList = p; - if (++block->freeCount == PAGES_PER_BLOCK) { - /* If all pages in the page block are now free, free the entire - * page block itself. - */ - if (block == pageBlocks) { - /* Delete from head */ - pageBlocks = block->next; - if (block->next) - block->next->prev = NULL; - } - else { - /* Delete from middle of list */ - CHECK(block->prev != NULL); - block->prev->next = block->next; - if (block->next) - block->next->prev = block->prev; - } - PM_free(block); - } -#else - (void)p; -#endif -} - -/*-------------------------------------------------------------------------*/ -/* DOS Real Mode support. */ -/*-------------------------------------------------------------------------*/ - -#ifdef REALMODE - -#ifndef MK_FP -#define MK_FP(s,o) ( (void far *)( ((ulong)(s) << 16) + \ - (ulong)(o) )) -#endif - -void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) -{ return MK_FP(r_seg,r_off); } - -void * PMAPI PM_getBIOSPointer(void) -{ - return MK_FP(0x40,0); -} - -void * PMAPI PM_getA0000Pointer(void) -{ - return MK_FP(0xA000,0); -} - -void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) -{ - uint sel = base >> 4; - uint off = base & 0xF; - limit = limit; - return MK_FP(sel,off); -} - -void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) -{ ptr = ptr; } - -ulong PMAPI PM_getPhysicalAddr(void *p) -{ - return ((((ulong)p >> 16) << 4) + (ushort)p); -} - -ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) -{ return false; } - -void * PMAPI PM_mapToProcess(void *base,ulong limit) -{ return (void*)base; } - -void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) -{ - /* Call malloc() to allocate the memory for us */ - void *p = PM_malloc(size); - *r_seg = FP_SEG(p); - *r_off = FP_OFF(p); - return p; -} - -void PMAPI PM_freeRealSeg(void *mem) -{ - if (mem) PM_free(mem); -} - -int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) -{ - return PM_int386(intno,in,out); -} - -int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, - RMSREGS *sregs) -{ - return PM_int386x(intno,in,out,sregs); -} - -void PMAPI PM_availableMemory(ulong *physical,ulong *total) -{ - PMREGS regs; - - regs.h.ah = 0x48; - regs.x.bx = 0xFFFF; - PM_int86(0x21,®s,®s); - *physical = *total = regs.x.bx * 16UL; -} - -#endif - -/*-------------------------------------------------------------------------*/ -/* Phar Lap TNT DOS Extender support. */ -/*-------------------------------------------------------------------------*/ - -#ifdef TNT - -#include -#include -#include - -static uchar *zeroPtr = NULL; - -void * PMAPI PM_getBIOSPointer(void) -{ - if (!zeroPtr) - zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); - return (void*)(zeroPtr + 0x400); -} - -void * PMAPI PM_getA0000Pointer(void) -{ - static void *bankPtr; - if (!bankPtr) - bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); - return bankPtr; -} - -void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) -{ - CONFIG_INF config; - ULONG offset; - int err; - ulong baseAddr,baseOfs,newLimit; - VXD_regs regs; - - /* If we have connected to our helper VxD in a Windows DOS box, use - * the helper VxD services to map memory instead of the DPMI services. - * We do this because the helper VxD can properly disable caching - * where necessary, which we can only do directly here if we are - * running at ring 0 (ie: under real DOS). - */ - if (VXD_version == -1) - PM_init(); - if (VXD_version) { - memset(®s,0,sizeof(regs)); - regs.eax = API_NUM(PMHELP_MAPPHYS); - regs.ebx = base; - regs.ecx = limit; - regs.edx = isCached; - _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); - return (void*)regs.eax; - } - - /* Round the physical address to a 4Kb boundary and the limit to a - * 4Kb-1 boundary before passing the values to TNT. If we round the - * physical address, then we also add an extra offset into the address - * that we return. - */ - baseOfs = base & 4095; - baseAddr = base & ~4095; - newLimit = ((limit+baseOfs+1+4095) & ~4095)-1; - _dx_config_inf(&config, (UCHAR*)&config); - err = _dx_map_phys(config.c_ds_sel,baseAddr,(newLimit + 4095) / 4096,&offset); - if (err == 130) { - /* If the TNT function failed, we are running in a DPMI environment - * and this function does not work. However we know how to handle - * DPMI properly, so we use our generic DPMI functions to do - * what the TNT runtime libraries can't. - */ - return DPMI_mapPhysicalAddr(base,limit,isCached); - } - if (err == 0) - return (void*)(offset + baseOfs); - return NULL; -} - -void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) -{ -} - -ulong PMAPI PM_getPhysicalAddr(void *p) -{ return 0xFFFFFFFFUL; } - -ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) -{ return false; } - -void * PMAPI PM_mapToProcess(void *base,ulong limit) -{ return (void*)base; } - -void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) -{ - if (!zeroPtr) - zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF); - return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); -} - -void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) -{ - USHORT addr,t; - void *p; - - if (_dx_real_alloc((size + 0xF) >> 4,&addr,&t) != 0) - return 0; - *r_seg = addr; /* Real mode segment address */ - *r_off = 0; /* Real mode segment offset */ - p = PM_mapRealPointer(*r_seg,*r_off); - _PM_addRealModeBlock(p,addr); - return p; -} - -void PMAPI PM_freeRealSeg(void *mem) -{ - if (mem) _dx_real_free(_PM_findRealModeBlock(mem)); -} - -#define INDPMI(reg) rmregs.reg = regs->reg -#define OUTDPMI(reg) regs->reg = rmregs.reg - -void PMAPI DPMI_int86(int intno, DPMI_regs *regs) -{ - SWI_REGS rmregs; - - memset(&rmregs, 0, sizeof(rmregs)); - INDPMI(eax); INDPMI(ebx); INDPMI(ecx); INDPMI(edx); INDPMI(esi); INDPMI(edi); - - _dx_real_int(intno,&rmregs); - - OUTDPMI(eax); OUTDPMI(ebx); OUTDPMI(ecx); OUTDPMI(edx); OUTDPMI(esi); OUTDPMI(edi); - regs->flags = rmregs.flags; -} - -#define IN(reg) rmregs.reg = in->e.reg -#define OUT(reg) out->e.reg = rmregs.reg - -int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) -{ - SWI_REGS rmregs; - - memset(&rmregs, 0, sizeof(rmregs)); - IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); - - _dx_real_int(intno,&rmregs); - - OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); - out->x.cflag = rmregs.flags & 0x1; - return out->x.ax; -} - -int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, - RMSREGS *sregs) -{ - SWI_REGS rmregs; - - memset(&rmregs, 0, sizeof(rmregs)); - IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); - rmregs.es = sregs->es; - rmregs.ds = sregs->ds; - - _dx_real_int(intno,&rmregs); - - OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); - sregs->es = rmregs.es; - sregs->cs = rmregs.cs; - sregs->ss = rmregs.ss; - sregs->ds = rmregs.ds; - out->x.cflag = rmregs.flags & 0x1; - return out->x.ax; -} - -void PMAPI PM_availableMemory(ulong *physical,ulong *total) -{ - PMREGS r; - uint data[25]; - - r.x.ax = 0x2520; /* Get free memory info */ - r.x.bx = 0; - r.e.edx = (uint)data; - PM_int386(0x21, &r, &r); - *physical = data[21] * 4096; - *total = data[23] * 4096; -} - -#endif - -/*-------------------------------------------------------------------------*/ -/* Symantec C++ DOSX and FlashTek X-32/X-32VM support */ -/*-------------------------------------------------------------------------*/ - -#if defined(DOSX) || defined(X32VM) - -#ifdef X32VM -#include - -#define _x386_mk_protected_ptr(p) _x32_mk_protected_ptr((void*)p) -#define _x386_free_protected_ptr(p) _x32_free_protected_ptr(p) -#define _x386_zero_base_ptr _x32_zero_base_ptr -#else -extern void *_x386_zero_base_ptr; -#endif - -void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) -{ - return (void*)((ulong)_x386_zero_base_ptr + MK_PHYS(r_seg,r_off)); -} - -void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) -{ - PMREGS r; - - r.h.ah = 0x48; /* DOS function 48h - allocate mem */ - r.x.bx = (size + 0xF) >> 4; /* Number of paragraphs to allocate */ - PM_int386(0x21, &r, &r); /* Call DOS extender */ - if (r.x.cflag) - return 0; /* Could not allocate the memory */ - *r_seg = r.e.eax; - *r_off = 0; - return PM_mapRealPointer(*r_seg,*r_off); -} - -void PMAPI PM_freeRealSeg(void *mem) -{ - /* Cannot de-allocate this memory */ - mem = mem; -} - -#pragma pack(1) - -typedef struct { - ushort intno; - ushort ds; - ushort es; - ushort fs; - ushort gs; - ulong eax; - ulong edx; - } _RMREGS; - -#pragma pack() - -#define IN(reg) regs.e.reg = in->e.reg -#define OUT(reg) out->e.reg = regs.e.reg - -int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) -{ - _RMREGS rmregs; - PMREGS regs; - PMSREGS pmsregs; - - rmregs.intno = intno; - rmregs.eax = in->e.eax; - rmregs.edx = in->e.edx; - IN(ebx); IN(ecx); IN(esi); IN(edi); - regs.x.ax = 0x2511; - regs.e.edx = (uint)(&rmregs); - PM_segread(&pmsregs); - PM_int386x(0x21,®s,®s,&pmsregs); - - OUT(eax); OUT(ebx); OUT(ecx); OUT(esi); OUT(edi); - out->x.dx = rmregs.edx; - out->x.cflag = regs.x.cflag; - return out->x.ax; -} - -int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, RMSREGS *sregs) -{ - _RMREGS rmregs; - PMREGS regs; - PMSREGS pmsregs; - - rmregs.intno = intno; - rmregs.eax = in->e.eax; - rmregs.edx = in->e.edx; - rmregs.es = sregs->es; - rmregs.ds = sregs->ds; - IN(ebx); IN(ecx); IN(esi); IN(edi); - regs.x.ax = 0x2511; - regs.e.edx = (uint)(&rmregs); - PM_segread(&pmsregs); - PM_int386x(0x21,®s,®s,&pmsregs); - - OUT(eax); OUT(ebx); OUT(ecx); OUT(esi); OUT(edi); - sregs->es = rmregs.es; - sregs->ds = rmregs.ds; - out->x.dx = rmregs.edx; - out->x.cflag = regs.x.cflag; - return out->x.ax; -} - -void * PMAPI PM_getBIOSPointer(void) -{ - return (void*)((ulong)_x386_zero_base_ptr + 0x400); -} - -void * PMAPI PM_getA0000Pointer(void) -{ - return (void*)((ulong)_x386_zero_base_ptr + 0xA0000); -} - -void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) -{ - VXD_regs regs; - - /* If we have connected to our helper VxD in a Windows DOS box, use - * the helper VxD services to map memory instead of the DPMI services. - * We do this because the helper VxD can properly disable caching - * where necessary, which we can only do directly here if we are - * running at ring 0 (ie: under real DOS). - */ - if (VXD_version == -1) - PM_init(); - if (VXD_version) { - memset(®s,0,sizeof(regs)); - regs.eax = API_NUM(PMHELP_MAPPHYS); - regs.ebx = base; - regs.ecx = limit; - regs.edx = isCached; - _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); - return (void*)regs.eax; - } - - if (base > 0x100000) - return _x386_map_physical_address((void*)base,limit); - return (void*)((ulong)_x386_zero_base_ptr + base); -} - -void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) -{ - /* Mapping cannot be freed */ -} - -ulong PMAPI PM_getPhysicalAddr(void *p) -{ return 0xFFFFFFFFUL; } - -ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) -{ return false; } - -void * PMAPI PM_mapToProcess(void *base,ulong limit) -{ return (void*)base; } - -ulong _cdecl _X32_getPhysMem(void); - -void PMAPI PM_availableMemory(ulong *physical,ulong *total) -{ - PMREGS regs; - - /* Get total memory available, including virtual memory */ - regs.x.ax = 0x350B; - PM_int386(0x21,®s,®s); - *total = regs.e.eax; - - /* Get physical memory available */ - *physical = _X32_getPhysMem(); - if (*physical > *total) - *physical = *total; -} - -#endif - -/*-------------------------------------------------------------------------*/ -/* Borland's DPMI32, Watcom DOS4GW and DJGPP DPMI support routines */ -/*-------------------------------------------------------------------------*/ - -#if defined(DPMI32) || defined(DOS4GW) || defined(DJGPP) - -void * PMAPI PM_getBIOSPointer(void) -{ - return PM_mapPhysicalAddr(0x400,0xFFFF,true); -} - -void * PMAPI PM_getA0000Pointer(void) -{ - return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); -} - -void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) -{ - VXD_regs regs; - -#ifdef DJGPP - /* Enable near pointers for DJGPP V2 */ - __djgpp_nearptr_enable(); -#endif - /* If we have connected to our helper VxD in a Windows DOS box, use - * the helper VxD services to map memory instead of the DPMI services. - * We do this because the helper VxD can properly disable caching - * where necessary, which we can only do directly here if we are - * running at ring 0 (ie: under real DOS). - */ - if (VXD_version == -1) - PM_init(); - if (VXD_version) { - memset(®s,0,sizeof(regs)); - regs.eax = API_NUM(PMHELP_MAPPHYS); - regs.ebx = base; - regs.ecx = limit; - regs.edx = isCached; - _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); - return (void*)regs.eax; - } - return DPMI_mapPhysicalAddr(base,limit,isCached); -} - -void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) -{ - /* Mapping cannot be freed */ - (void)ptr; - (void)limit; -} - -ulong PMAPI PM_getPhysicalAddr(void *p) -{ - ulong physAddr; - if (!PM_getPhysicalAddrRange(p,1,&physAddr)) - return 0xFFFFFFFF; - return physAddr | ((ulong)p & 0xFFF); -} - -ibool PMAPI PM_getPhysicalAddrRange( - void *p, - ulong length, - ulong *physAddress) -{ - VXD_regs regs; - ulong pte; - PMSREGS sregs; - ulong DSBaseAddr; - - /* If we have connected to our helper VxD in a Windows DOS box, use the - * helper VxD services to find the physical address of an address. - */ - if (VXD_version) { - memset(®s,0,sizeof(regs)); - regs.eax = API_NUM(PMHELP_GETPHYSICALADDRRANGE); - regs.ebx = (ulong)p; - regs.ecx = (ulong)length; - regs.edx = (ulong)physAddress; - _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); - return regs.eax; - } - - /* Find base address for default DS selector */ - PM_segread(&sregs); - DSBaseAddr = DPMI_getSelectorBase(sregs.ds); - - /* Otherwise directly access the page tables to determine the - * physical memory address. Note that we touch the memory before - * calling, otherwise the memory may not be paged in correctly. - */ - pte = *((ulong*)p); -#ifdef DOS4GW - if (_PM_pagingEnabled() == 0) { - int count; - ulong linAddr = (ulong)p; - - /* When paging is disabled physical=linear */ - for (count = (length+0xFFF) >> 12; count > 0; count--) { - *physAddress++ = linAddr; - linAddr += 4096; - } - return true; - } - else if ((PDB = _PM_getPDB()) != 0 && DSBaseAddr == 0) { - int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; - ulong pageTable,*pPageTable,linAddr = (ulong)p; - ulong limit = length-1; - - pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF); - if (pPDB) { - startPDB = (linAddr >> 22) & 0x3FFL; - startPage = (linAddr >> 12) & 0x3FFL; - endPDB = ((linAddr+limit) >> 22) & 0x3FFL; - endPage = ((linAddr+limit) >> 12) & 0x3FFL; - for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { - pageTable = pPDB[iPDB] & ~0xFFFL; - pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF); - start = (iPDB == startPDB) ? startPage : 0; - end = (iPDB == endPDB) ? endPage : 0x3FFL; - for (iPage = start; iPage <= end; iPage++) - *physAddress++ = (pPageTable[iPage] & ~0xFFF); - } - return true; - } - } -#endif - return false; -} - -void * PMAPI PM_mapToProcess(void *base,ulong limit) -{ - (void)limit; - return (void*)base; -} - -void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) -{ - static uchar *zeroPtr = NULL; - - if (!zeroPtr) - zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); - return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); -} - -void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) -{ - PMREGS r; - void *p; - - r.x.ax = 0x100; /* DPMI allocate DOS memory */ - r.x.bx = (size + 0xF) >> 4; /* number of paragraphs */ - PM_int386(0x31, &r, &r); - if (r.x.cflag) - return NULL; /* DPMI call failed */ - *r_seg = r.x.ax; /* Real mode segment */ - *r_off = 0; - p = PM_mapRealPointer(*r_seg,*r_off); - _PM_addRealModeBlock(p,r.x.dx); - return p; -} - -void PMAPI PM_freeRealSeg(void *mem) -{ - PMREGS r; - - if (mem) { - r.x.ax = 0x101; /* DPMI free DOS memory */ - r.x.dx = _PM_findRealModeBlock(mem);/* DX := selector from 0x100 */ - PM_int386(0x31, &r, &r); - } -} - -static DPMI_handler_t DPMI_int10 = NULL; - -void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler) -{ - DPMI_int10 = handler; -} - -void PMAPI DPMI_int86(int intno, DPMI_regs *regs) -{ - PMREGS r; - PMSREGS sr; - - if (intno == 0x10 && DPMI_int10) { - if (DPMI_int10(regs)) - return; - } - PM_segread(&sr); - r.x.ax = 0x300; /* DPMI issue real interrupt */ - r.h.bl = intno; - r.h.bh = 0; - r.x.cx = 0; - sr.es = sr.ds; - r.e.edi = (uint)regs; - PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ -} - -#define IN(reg) rmregs.reg = in->e.reg -#define OUT(reg) out->e.reg = rmregs.reg - -int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) -{ - DPMI_regs rmregs; - - memset(&rmregs, 0, sizeof(rmregs)); - IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); - - DPMI_int86(intno,&rmregs); /* DPMI issue real interrupt */ - - OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); - out->x.cflag = rmregs.flags & 0x1; - return out->x.ax; -} - -int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, - RMSREGS *sregs) -{ - DPMI_regs rmregs; - - memset(&rmregs, 0, sizeof(rmregs)); - IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); - rmregs.es = sregs->es; - rmregs.ds = sregs->ds; - - DPMI_int86(intno,&rmregs); /* DPMI issue real interrupt */ - - OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); - sregs->es = rmregs.es; - sregs->cs = rmregs.cs; - sregs->ss = rmregs.ss; - sregs->ds = rmregs.ds; - out->x.cflag = rmregs.flags & 0x1; - return out->x.ax; -} - -#pragma pack(1) - -typedef struct { - uint LargestBlockAvail; - uint MaxUnlockedPage; - uint LargestLockablePage; - uint LinAddrSpace; - uint NumFreePagesAvail; - uint NumPhysicalPagesFree; - uint TotalPhysicalPages; - uint FreeLinAddrSpace; - uint SizeOfPageFile; - uint res[3]; - } MemInfo; - -#pragma pack() - -void PMAPI PM_availableMemory(ulong *physical,ulong *total) -{ - PMREGS r; - PMSREGS sr; - MemInfo memInfo; - - PM_segread(&sr); - r.x.ax = 0x500; /* DPMI get free memory info */ - sr.es = sr.ds; - r.e.edi = (uint)&memInfo; - PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ - *physical = memInfo.NumPhysicalPagesFree * 4096; - *total = memInfo.LargestBlockAvail; - if (*total < *physical) - *physical = *total; -} - -#endif - -#ifndef __16BIT__ - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display banks. -****************************************************************************/ -void PMAPI PM_setBankA( - int bank) -{ - DPMI_regs regs; - memset(®s, 0, sizeof(regs)); - regs.eax = 0x4F05; - regs.ebx = 0x0000; - regs.edx = bank; - DPMI_int86(0x10,®s); -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display banks. -****************************************************************************/ -void PMAPI PM_setBankAB( - int bank) -{ - DPMI_regs regs; - memset(®s, 0, sizeof(regs)); - regs.eax = 0x4F05; - regs.ebx = 0x0000; - regs.edx = bank; - DPMI_int86(0x10,®s); - regs.eax = 0x4F05; - regs.ebx = 0x0001; - regs.edx = bank; - DPMI_int86(0x10,®s); -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display start address. -****************************************************************************/ -void PMAPI PM_setCRTStart( - int x, - int y, - int waitVRT) -{ - DPMI_regs regs; - memset(®s, 0, sizeof(regs)); - regs.eax = 0x4F07; - regs.ebx = waitVRT; - regs.ecx = x; - regs.edx = y; - DPMI_int86(0x10,®s); -} - -#endif - -/**************************************************************************** -REMARKS: -Function to get the file attributes for a specific file. -****************************************************************************/ -uint PMAPI PM_getFileAttr( - const char *filename) -{ - /* TODO: Implement this! */ - return 0; -} - -/**************************************************************************** -REMARKS: -Function to get the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_getFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* TODO: Implement this! */ - return false; -} - -/**************************************************************************** -REMARKS: -Function to set the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_setFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* TODO: Implement this! */ - return false; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c b/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c deleted file mode 100644 index eecc2da..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c +++ /dev/null @@ -1,1637 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 16/32 bit DOS -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include -#include -#include -#include - -/*--------------------------- Global variables ----------------------------*/ - -#ifndef REALMODE -static int globalDataStart; -#endif - -PM_criticalHandler _VARAPI _PM_critHandler = NULL; -PM_breakHandler _VARAPI _PM_breakHandler = NULL; -PM_intHandler _VARAPI _PM_timerHandler = NULL; -PM_intHandler _VARAPI _PM_rtcHandler = NULL; -PM_intHandler _VARAPI _PM_keyHandler = NULL; -PM_key15Handler _VARAPI _PM_key15Handler = NULL; -PM_mouseHandler _VARAPI _PM_mouseHandler = NULL; -PM_intHandler _VARAPI _PM_int10Handler = NULL; -int _VARAPI _PM_mouseMask; - -uchar * _VARAPI _PM_ctrlCPtr; /* Location of Ctrl-C flag */ -uchar * _VARAPI _PM_ctrlBPtr; /* Location of Ctrl-Break flag */ -uchar * _VARAPI _PM_critPtr; /* Location of Critical error Bf*/ -PMFARPTR _VARAPI _PM_prevTimer = PMNULL; /* Previous timer handler */ -PMFARPTR _VARAPI _PM_prevRTC = PMNULL; /* Previous RTC handler */ -PMFARPTR _VARAPI _PM_prevKey = PMNULL; /* Previous key handler */ -PMFARPTR _VARAPI _PM_prevKey15 = PMNULL; /* Previous key15 handler */ -PMFARPTR _VARAPI _PM_prevBreak = PMNULL; /* Previous break handler */ -PMFARPTR _VARAPI _PM_prevCtrlC = PMNULL; /* Previous CtrlC handler */ -PMFARPTR _VARAPI _PM_prevCritical = PMNULL; /* Previous critical handler */ -long _VARAPI _PM_prevRealTimer; /* Previous real mode timer */ -long _VARAPI _PM_prevRealRTC; /* Previous real mode RTC */ -long _VARAPI _PM_prevRealKey; /* Previous real mode key */ -long _VARAPI _PM_prevRealKey15; /* Previous real mode key15 */ -long _VARAPI _PM_prevRealInt10; /* Previous real mode int 10h */ -static uchar _PM_oldCMOSRegA; /* CMOS register A contents */ -static uchar _PM_oldCMOSRegB; /* CMOS register B contents */ -static uchar _PM_oldRTCPIC2; /* Mask value for RTC IRQ8 */ - -/* Structure to maintain information about hardware interrupt handlers, - * include a copy of the hardware IRQ assembler thunk (one for each - * hooked interrupt handler). - */ - -typedef struct { - uchar IRQ; - uchar IRQVect; - uchar prevPIC; - uchar prevPIC2; - PMFARPTR prevHandler; - long prevRealhandler; - uchar thunk[1]; - /* IRQ assembler thunk follows ... */ - } _PM_IRQHandle; - -/*----------------------------- Implementation ----------------------------*/ - -/* Globals for locking interrupt handlers in _pmdos.asm */ - -#ifndef REALMODE -extern int _VARAPI _PM_pmdosDataStart; -extern int _VARAPI _PM_pmdosDataEnd; -extern int _VARAPI _PM_DMADataStart; -extern int _VARAPI _PM_DMADataEnd; -void _ASMAPI _PM_pmdosCodeStart(void); -void _ASMAPI _PM_pmdosCodeEnd(void); -void _ASMAPI _PM_DMACodeStart(void); -void _ASMAPI _PM_DMACodeEnd(void); -#endif - -/* Protected mode interrupt handlers, also called by PM callbacks below */ - -void _ASMAPI _PM_timerISR(void); -void _ASMAPI _PM_rtcISR(void); -void _ASMAPI _PM_irqISRTemplate(void); -void _ASMAPI _PM_irqISRTemplateEnd(void); -void _ASMAPI _PM_keyISR(void); -void _ASMAPI _PM_key15ISR(void); -void _ASMAPI _PM_breakISR(void); -void _ASMAPI _PM_ctrlCISR(void); -void _ASMAPI _PM_criticalISR(void); -void _ASMAPI _PM_mouseISR(void); -void _ASMAPI _PM_int10PMCB(void); - -/* Protected mode DPMI callback handlers */ - -void _ASMAPI _PM_mousePMCB(void); - -/* Routine to install a mouse handler function */ - -void _ASMAPI _PM_setMouseHandler(int mask); - -/* Routine to allocate DPMI real mode callback routines */ - -ibool _ASMAPI _DPMI_allocateCallback(void (_ASMAPI *pmcode)(),void *rmregs,long *RMCB); -void _ASMAPI _DPMI_freeCallback(long RMCB); - -/* DPMI helper functions in PMLITE.C */ - -ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit); -int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr); -ulong PMAPI DPMI_getSelectorBase(ushort sel); -int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit); -uint PMAPI DPMI_createSelector(ulong base,ulong limit); -void PMAPI DPMI_freeSelector(uint sel); -int PMAPI DPMI_lockLinearPages(ulong linear,ulong len); -int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len); - -/* Functions to read and write CMOS registers */ - -uchar PMAPI _PM_readCMOS(int index); -void PMAPI _PM_writeCMOS(int index,uchar value); - -/*-------------------------------------------------------------------------*/ -/* Generic routines common to all environments */ -/*-------------------------------------------------------------------------*/ - -void PMAPI PM_resetMouseDriver(int hardReset) -{ - RMREGS regs; - PM_mouseHandler oldHandler = _PM_mouseHandler; - - PM_restoreMouseHandler(); - regs.x.ax = hardReset ? 0 : 33; - PM_int86(0x33, ®s, ®s); - if (oldHandler) - PM_setMouseHandler(_PM_mouseMask, oldHandler); -} - -void PMAPI PM_setRealTimeClockFrequency(int frequency) -{ - static short convert[] = { - 8192, - 4096, - 2048, - 1024, - 512, - 256, - 128, - 64, - 32, - 16, - 8, - 4, - 2, - -1, - }; - int i; - - /* First clear any pending RTC timeout if not cleared */ - _PM_readCMOS(0x0C); - if (frequency == 0) { - /* Disable RTC timout */ - _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); - _PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F); - } - else { - /* Convert frequency value to RTC clock indexes */ - for (i = 0; convert[i] != -1; i++) { - if (convert[i] == frequency) - break; - } - - /* Set RTC timout value and enable timeout */ - _PM_writeCMOS(0x0A,0x20 | (i+3)); - _PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40); - } -} - -#ifndef REALMODE - -static void PMAPI lockPMHandlers(void) -{ - static int locked = 0; - int stat; - PM_lockHandle lh; /* Unused in DOS */ - - /* Lock all of the code and data used by our protected mode interrupt - * handling routines, so that it will continue to work correctly - * under real mode. - */ - if (!locked) { - PM_saveDS(); - stat = !PM_lockDataPages(&globalDataStart-2048,4096,&lh); - stat |= !PM_lockDataPages(&_PM_pmdosDataStart,(int)&_PM_pmdosDataEnd - (int)&_PM_pmdosDataStart,&lh); - stat |= !PM_lockCodePages((__codePtr)_PM_pmdosCodeStart,(int)_PM_pmdosCodeEnd-(int)_PM_pmdosCodeStart,&lh); - stat |= !PM_lockDataPages(&_PM_DMADataStart,(int)&_PM_DMADataEnd - (int)&_PM_DMADataStart,&lh); - stat |= !PM_lockCodePages((__codePtr)_PM_DMACodeStart,(int)_PM_DMACodeEnd-(int)_PM_DMACodeStart,&lh); - if (stat) { - printf("Page locking services failed - interrupt handling not safe!\n"); - exit(1); - } - locked = 1; - } -} - -#endif - -/*-------------------------------------------------------------------------*/ -/* DOS Real Mode support. */ -/*-------------------------------------------------------------------------*/ - -#ifdef REALMODE - -#ifndef MK_FP -#define MK_FP(s,o) ( (void far *)( ((ulong)(s) << 16) + \ - (ulong)(o) )) -#endif - -int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) -{ - PM_saveDS(); - _PM_mouseHandler = mh; - _PM_setMouseHandler(_PM_mouseMask = mask); - return 1; -} - -void PMAPI PM_restoreMouseHandler(void) -{ - union REGS regs; - - if (_PM_mouseHandler) { - regs.x.ax = 33; - int86(0x33, ®s, ®s); - _PM_mouseHandler = NULL; - } -} - -void PMAPI PM_setTimerHandler(PM_intHandler th) -{ - _PM_getRMvect(0x8, (long*)&_PM_prevTimer); - _PM_timerHandler = th; - _PM_setRMvect(0x8, (long)_PM_timerISR); -} - -void PMAPI PM_restoreTimerHandler(void) -{ - if (_PM_timerHandler) { - _PM_setRMvect(0x8, (long)_PM_prevTimer); - _PM_timerHandler = NULL; - } -} - -ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) -{ - /* Save the old CMOS real time clock values */ - _PM_oldCMOSRegA = _PM_readCMOS(0x0A); - _PM_oldCMOSRegB = _PM_readCMOS(0x0B); - - /* Set the real time clock interrupt handler */ - _PM_getRMvect(0x70, (long*)&_PM_prevRTC); - _PM_rtcHandler = th; - _PM_setRMvect(0x70, (long)_PM_rtcISR); - - /* Program the real time clock default frequency */ - PM_setRealTimeClockFrequency(frequency); - - /* Unmask IRQ8 in the PIC2 */ - _PM_oldRTCPIC2 = PM_inpb(0xA1); - PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); - return true; -} - -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - if (_PM_rtcHandler) { - /* Restore CMOS registers and mask RTC clock */ - _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); - _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); - PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); - - /* Restore the interrupt vector */ - _PM_setRMvect(0x70, (long)_PM_prevRTC); - _PM_rtcHandler = NULL; - } -} - -void PMAPI PM_setKeyHandler(PM_intHandler kh) -{ - _PM_getRMvect(0x9, (long*)&_PM_prevKey); - _PM_keyHandler = kh; - _PM_setRMvect(0x9, (long)_PM_keyISR); -} - -void PMAPI PM_restoreKeyHandler(void) -{ - if (_PM_keyHandler) { - _PM_setRMvect(0x9, (long)_PM_prevKey); - _PM_keyHandler = NULL; - } -} - -void PMAPI PM_setKey15Handler(PM_key15Handler kh) -{ - _PM_getRMvect(0x15, (long*)&_PM_prevKey15); - _PM_key15Handler = kh; - _PM_setRMvect(0x15, (long)_PM_key15ISR); -} - -void PMAPI PM_restoreKey15Handler(void) -{ - if (_PM_key15Handler) { - _PM_setRMvect(0x15, (long)_PM_prevKey15); - _PM_key15Handler = NULL; - } -} - -void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) -{ - static int ctrlCFlag,ctrlBFlag; - - _PM_ctrlCPtr = (uchar*)&ctrlCFlag; - _PM_ctrlBPtr = (uchar*)&ctrlBFlag; - _PM_getRMvect(0x1B, (long*)&_PM_prevBreak); - _PM_getRMvect(0x23, (long*)&_PM_prevCtrlC); - _PM_breakHandler = bh; - _PM_setRMvect(0x1B, (long)_PM_breakISR); - _PM_setRMvect(0x23, (long)_PM_ctrlCISR); -} - -void PMAPI PM_installBreakHandler(void) -{ - PM_installAltBreakHandler(NULL); -} - -void PMAPI PM_restoreBreakHandler(void) -{ - if (_PM_prevBreak) { - _PM_setRMvect(0x1B, (long)_PM_prevBreak); - _PM_setRMvect(0x23, (long)_PM_prevCtrlC); - _PM_prevBreak = NULL; - _PM_breakHandler = NULL; - } -} - -void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) -{ - static short critBuf[2]; - - _PM_critPtr = (uchar*)critBuf; - _PM_getRMvect(0x24, (long*)&_PM_prevCritical); - _PM_critHandler = ch; - _PM_setRMvect(0x24, (long)_PM_criticalISR); -} - -void PMAPI PM_installCriticalHandler(void) -{ - PM_installAltCriticalHandler(NULL); -} - -void PMAPI PM_restoreCriticalHandler(void) -{ - if (_PM_prevCritical) { - _PM_setRMvect(0x24, (long)_PM_prevCritical); - _PM_prevCritical = NULL; - _PM_critHandler = NULL; - } -} - -int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - p = p; len = len; /* Do nothing for real mode */ - return 1; -} - -int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - p = p; len = len; /* Do nothing for real mode */ - return 1; -} - -int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - p = p; len = len; /* Do nothing for real mode */ - return 1; -} - -int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - p = p; len = len; /* Do nothing for real mode */ - return 1; -} - -void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) -{ - long t; - _PM_getRMvect(intno,&t); - *isr = (void*)t; -} - -void PMAPI PM_setPMvect(int intno, PM_intHandler isr) -{ - PM_saveDS(); - _PM_setRMvect(intno,(long)isr); -} - -void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) -{ - _PM_setRMvect(intno,(long)isr); -} - -#endif - -/*-------------------------------------------------------------------------*/ -/* Phar Lap TNT DOS Extender support. */ -/*-------------------------------------------------------------------------*/ - -#ifdef TNT - -#include -#include -#include - -static long prevRealBreak; /* Previous real mode break handler */ -static long prevRealCtrlC; /* Previous real mode CtrlC handler */ -static long prevRealCritical; /* Prev real mode critical handler */ -static uchar *mousePtr; - -/* The following real mode routine is used to call a 32 bit protected - * mode FAR function from real mode. We use this for passing up control - * from the real mode mouse callback to our protected mode code. - */ - -static UCHAR realHandler[] = { /* Real mode code generic handler */ - 0x00,0x00,0x00,0x00, /* __PM_callProtp */ - 0x00,0x00, /* __PM_protCS */ - 0x00,0x00,0x00,0x00, /* __PM_protHandler */ - 0x66,0x60, /* pushad */ - 0x1E, /* push ds */ - 0x6A,0x00, /* push 0 */ - 0x6A,0x00, /* push 0 */ - 0x2E,0xFF,0x36,0x04,0x00, /* push [cs:__PM_protCS] */ - 0x66,0x2E,0xFF,0x36,0x06,0x00, /* push [cs:__PM_protHandler] */ - 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PM_callProtp] */ - 0x83,0xC4,0x0A, /* add sp,10 */ - 0x1F, /* pop ds */ - 0x66,0x61, /* popad */ - 0xCB, /* retf */ - }; - -/* The following functions installs the above realmode callback mechanism - * in real mode memory for calling the protected mode routine. - */ - -uchar * installCallback(void (PMAPI *pmCB)(),uint *rseg, uint *roff) -{ - CONFIG_INF config; - REALPTR realBufAdr,callProtp; - ULONG bufSize; - FARPTR protBufAdr; - uchar *p; - - /* Get address of real mode routine to call up to protected mode */ - _dx_rmlink_get(&callProtp, &realBufAdr, &bufSize, &protBufAdr); - _dx_config_inf(&config, (UCHAR*)&config); - - /* Fill in the values in the real mode code segment so that it will - * call the correct routine. - */ - *((REALPTR*)&realHandler[0]) = callProtp; - *((USHORT*)&realHandler[4]) = config.c_cs_sel; - *((ULONG*)&realHandler[6]) = (ULONG)pmCB; - - /* Copy the real mode handler to real mode memory */ - if ((p = PM_allocRealSeg(sizeof(realHandler),rseg,roff)) == NULL) - return NULL; - memcpy(p,realHandler,sizeof(realHandler)); - - /* Skip past global variabls in real mode code segment */ - *roff += 0x0A; - return p; -} - -int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) -{ - RMREGS regs; - RMSREGS sregs; - uint rseg,roff; - - lockPMHandlers(); /* Ensure our handlers are locked */ - - if ((mousePtr = installCallback(_PM_mouseISR, &rseg, &roff)) == NULL) - return 0; - _PM_mouseHandler = mh; - - /* Install the real mode mouse handler */ - sregs.es = rseg; - regs.x.dx = roff; - regs.x.cx = _PM_mouseMask = mask; - regs.x.ax = 0xC; - PM_int86x(0x33, ®s, ®s, &sregs); - return 1; -} - -void PMAPI PM_restoreMouseHandler(void) -{ - RMREGS regs; - - if (_PM_mouseHandler) { - regs.x.ax = 33; - PM_int86(0x33, ®s, ®s); - PM_freeRealSeg(mousePtr); - _PM_mouseHandler = NULL; - } -} - -void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) -{ - FARPTR ph; - - _dx_pmiv_get(intno, &ph); - isr->sel = FP_SEL(ph); - isr->off = FP_OFF(ph); -} - -void PMAPI PM_setPMvect(int intno, PM_intHandler isr) -{ - CONFIG_INF config; - FARPTR ph; - - PM_saveDS(); - _dx_config_inf(&config, (UCHAR*)&config); - FP_SET(ph,(uint)isr,config.c_cs_sel); - _dx_pmiv_set(intno,ph); -} - -void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) -{ - FARPTR ph; - - FP_SET(ph,isr.off,isr.sel); - _dx_pmiv_set(intno,ph); -} - -static void getISR(int intno, PMFARPTR *pmisr, long *realisr) -{ - PM_getPMvect(intno,pmisr); - _PM_getRMvect(intno, realisr); -} - -static void restoreISR(int intno, PMFARPTR pmisr, long realisr) -{ - _PM_setRMvect(intno,realisr); - PM_restorePMvect(intno,pmisr); -} - -static void setISR(int intno, void (PMAPI *isr)()) -{ - CONFIG_INF config; - FARPTR ph; - - lockPMHandlers(); /* Ensure our handlers are locked */ - - _dx_config_inf(&config, (UCHAR*)&config); - FP_SET(ph,(uint)isr,config.c_cs_sel); - _dx_apmiv_set(intno,ph); -} - -void PMAPI PM_setTimerHandler(PM_intHandler th) -{ - getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer); - _PM_timerHandler = th; - setISR(0x8, _PM_timerISR); -} - -void PMAPI PM_restoreTimerHandler(void) -{ - if (_PM_timerHandler) { - restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer); - _PM_timerHandler = NULL; - } -} - -ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) -{ - /* Save the old CMOS real time clock values */ - _PM_oldCMOSRegA = _PM_readCMOS(0x0A); - _PM_oldCMOSRegB = _PM_readCMOS(0x0B); - - /* Set the real time clock interrupt handler */ - getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); - _PM_rtcHandler = th; - setISR(0x70, _PM_rtcISR); - - /* Program the real time clock default frequency */ - PM_setRealTimeClockFrequency(frequency); - - /* Unmask IRQ8 in the PIC2 */ - _PM_oldRTCPIC2 = PM_inpb(0xA1); - PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); - return true; -} - -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - if (_PM_rtcHandler) { - /* Restore CMOS registers and mask RTC clock */ - _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); - _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); - PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); - - /* Restore the interrupt vector */ - restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); - _PM_rtcHandler = NULL; - } -} - -void PMAPI PM_setKeyHandler(PM_intHandler kh) -{ - getISR(0x9, &_PM_prevKey, &_PM_prevRealKey); - _PM_keyHandler = kh; - setISR(0x9, _PM_keyISR); -} - -void PMAPI PM_restoreKeyHandler(void) -{ - if (_PM_keyHandler) { - restoreISR(0x9, _PM_prevKey, _PM_prevRealKey); - _PM_keyHandler = NULL; - } -} - -void PMAPI PM_setKey15Handler(PM_key15Handler kh) -{ - getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); - _PM_key15Handler = kh; - setISR(0x15, _PM_key15ISR); -} - -void PMAPI PM_restoreKey15Handler(void) -{ - if (_PM_key15Handler) { - restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); - _PM_key15Handler = NULL; - } -} - -void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) -{ - static int ctrlCFlag,ctrlBFlag; - - _PM_ctrlCPtr = (uchar*)&ctrlCFlag; - _PM_ctrlBPtr = (uchar*)&ctrlBFlag; - getISR(0x1B, &_PM_prevBreak, &prevRealBreak); - getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); - _PM_breakHandler = bh; - setISR(0x1B, _PM_breakISR); - setISR(0x23, _PM_ctrlCISR); -} - -void PMAPI PM_installBreakHandler(void) -{ - PM_installAltBreakHandler(NULL); -} - -void PMAPI PM_restoreBreakHandler(void) -{ - if (_PM_prevBreak.sel) { - restoreISR(0x1B, _PM_prevBreak, prevRealBreak); - restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); - _PM_prevBreak.sel = 0; - _PM_breakHandler = NULL; - } -} - -void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) -{ - static short critBuf[2]; - - _PM_critPtr = (uchar*)critBuf; - getISR(0x24, &_PM_prevCritical, &prevRealCritical); - _PM_critHandler = ch; - setISR(0x24, _PM_criticalISR); -} - -void PMAPI PM_installCriticalHandler(void) -{ - PM_installAltCriticalHandler(NULL); -} - -void PMAPI PM_restoreCriticalHandler(void) -{ - if (_PM_prevCritical.sel) { - restoreISR(0x24, _PM_prevCritical, prevRealCritical); - _PM_prevCritical.sel = 0; - _PM_critHandler = NULL; - } -} - -int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - return (_dx_lock_pgsn(p,len) == 0); -} - -int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - return (_dx_ulock_pgsn(p,len) == 0); -} - -int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - CONFIG_INF config; - FARPTR fp; - - _dx_config_inf(&config, (UCHAR*)&config); - FP_SET(fp,p,config.c_cs_sel); - return (_dx_lock_pgs(fp,len) == 0); -} - -int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - CONFIG_INF config; - FARPTR fp; - - _dx_config_inf(&config, (UCHAR*)&config); - FP_SET(fp,p,config.c_cs_sel); - return (_dx_ulock_pgs(fp,len) == 0); -} - -#endif - -/*-------------------------------------------------------------------------*/ -/* Symantec C++ DOSX and FlashTek X-32/X-32VM support */ -/*-------------------------------------------------------------------------*/ - -#if defined(DOSX) || defined(X32VM) - -#ifdef X32VM -#include -#endif - -static long prevRealBreak; /* Previous real mode break handler */ -static long prevRealCtrlC; /* Previous real mode CtrlC handler */ -static long prevRealCritical; /* Prev real mode critical handler */ - -static uint mouseSel = 0,mouseOff; - -/* The following real mode routine is used to call a 32 bit protected - * mode FAR function from real mode. We use this for passing up control - * from the real mode mouse callback to our protected mode code. - */ - -static char realHandler[] = { /* Real mode code generic handler */ - 0x00,0x00,0x00,0x00, /* __PM_callProtp */ - 0x00,0x00, /* __PM_protCS */ - 0x00,0x00,0x00,0x00, /* __PM_protHandler */ - 0x1E, /* push ds */ - 0x6A,0x00, /* push 0 */ - 0x6A,0x00, /* push 0 */ - 0x2E,0xFF,0x36,0x04,0x00, /* push [cs:__PM_protCS] */ - 0x66,0x2E,0xFF,0x36,0x06,0x00, /* push [cs:__PM_protHandler] */ - 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PM_callProtp] */ - 0x83,0xC4,0x0A, /* add sp,10 */ - 0x1F, /* pop ds */ - 0xCB, /* retf */ - }; - -/* The following functions installs the above realmode callback mechanism - * in real mode memory for calling the protected mode routine. - */ - -int installCallback(void (PMAPI *pmCB)(),uint *psel, uint *poff, - uint *rseg, uint *roff) -{ - PMREGS regs; - PMSREGS sregs; - - regs.x.ax = 0x250D; - PM_segread(&sregs); - PM_int386x(0x21,®s,®s,&sregs); /* Get RM callback address */ - - /* Fill in the values in the real mode code segment so that it will - * call the correct routine. - */ - *((ulong*)&realHandler[0]) = regs.e.eax; - *((ushort*)&realHandler[4]) = sregs.cs; - *((ulong*)&realHandler[6]) = (ulong)pmCB; - - /* Copy the real mode handler to real mode memory (only allocate the - * buffer once since we cant dealloate it with X32). - */ - if (*psel == 0) { - if (!PM_allocRealSeg(sizeof(realHandler),psel,poff,rseg,roff)) - return 0; - } - PM_memcpyfn(*psel,*poff,realHandler,sizeof(realHandler)); - - /* Skip past global variables in real mode code segment */ - *roff += 0x0A; - return 1; -} - -int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) -{ - RMREGS regs; - RMSREGS sregs; - uint rseg,roff; - - lockPMHandlers(); /* Ensure our handlers are locked */ - - if (!installCallback(_PM_mouseISR, &mouseSel, &mouseOff, &rseg, &roff)) - return 0; - _PM_mouseHandler = mh; - - /* Install the real mode mouse handler */ - sregs.es = rseg; - regs.x.dx = roff; - regs.x.cx = _PM_mouseMask = mask; - regs.x.ax = 0xC; - PM_int86x(0x33, ®s, ®s, &sregs); - return 1; -} - -void PMAPI PM_restoreMouseHandler(void) -{ - RMREGS regs; - - if (_PM_mouseHandler) { - regs.x.ax = 33; - PM_int86(0x33, ®s, ®s); - _PM_mouseHandler = NULL; - } -} - -void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) -{ - PMREGS regs; - PMSREGS sregs; - - PM_segread(&sregs); - regs.x.ax = 0x2502; /* Get PM interrupt vector */ - regs.x.cx = intno; - PM_int386x(0x21, ®s, ®s, &sregs); - isr->sel = sregs.es; - isr->off = regs.e.ebx; -} - -void PMAPI PM_setPMvect(int intno, PM_intHandler isr) -{ - PMFARPTR pmisr; - PMSREGS sregs; - - PM_saveDS(); - PM_segread(&sregs); - pmisr.sel = sregs.cs; - pmisr.off = (uint)isr; - PM_restorePMvect(intno, pmisr); -} - -void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) -{ - PMREGS regs; - PMSREGS sregs; - - PM_segread(&sregs); - regs.x.ax = 0x2505; /* Set PM interrupt vector */ - regs.x.cx = intno; - sregs.ds = isr.sel; - regs.e.edx = isr.off; - PM_int386x(0x21, ®s, ®s, &sregs); -} - -static void getISR(int intno, PMFARPTR *pmisr, long *realisr) -{ - PM_getPMvect(intno,pmisr); - _PM_getRMvect(intno,realisr); -} - -static void restoreISR(int intno, PMFARPTR pmisr, long realisr) -{ - PMREGS regs; - PMSREGS sregs; - - PM_segread(&sregs); - regs.x.ax = 0x2507; /* Set real and PM vectors */ - regs.x.cx = intno; - sregs.ds = pmisr.sel; - regs.e.edx = pmisr.off; - regs.e.ebx = realisr; - PM_int386x(0x21, ®s, ®s, &sregs); -} - -static void setISR(int intno, void *isr) -{ - PMREGS regs; - PMSREGS sregs; - - lockPMHandlers(); /* Ensure our handlers are locked */ - - PM_segread(&sregs); - regs.x.ax = 0x2506; /* Hook real and protected vectors */ - regs.x.cx = intno; - sregs.ds = sregs.cs; - regs.e.edx = (uint)isr; - PM_int386x(0x21, ®s, ®s, &sregs); -} - -void PMAPI PM_setTimerHandler(PM_intHandler th) -{ - getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer); - _PM_timerHandler = th; - setISR(0x8, _PM_timerISR); -} - -void PMAPI PM_restoreTimerHandler(void) -{ - if (_PM_timerHandler) { - restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer); - _PM_timerHandler = NULL; - } -} - -ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) -{ - /* Save the old CMOS real time clock values */ - _PM_oldCMOSRegA = _PM_readCMOS(0x0A); - _PM_oldCMOSRegB = _PM_readCMOS(0x0B); - - /* Set the real time clock interrupt handler */ - getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); - _PM_rtcHandler = th; - setISR(0x70, _PM_rtcISR); - - /* Program the real time clock default frequency */ - PM_setRealTimeClockFrequency(frequency); - - /* Unmask IRQ8 in the PIC2 */ - _PM_oldRTCPIC2 = PM_inpb(0xA1); - PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); - return true; -} - -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - if (_PM_rtcHandler) { - /* Restore CMOS registers and mask RTC clock */ - _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); - _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); - PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); - - /* Restore the interrupt vector */ - restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); - _PM_rtcHandler = NULL; - } -} - -void PMAPI PM_setKeyHandler(PM_intHandler kh) -{ - getISR(0x9, &_PM_prevKey, &_PM_prevRealKey); - _PM_keyHandler = kh; - setISR(0x9, _PM_keyISR); -} - -void PMAPI PM_restoreKeyHandler(void) -{ - if (_PM_keyHandler) { - restoreISR(0x9, _PM_prevKey, _PM_prevRealKey); - _PM_keyHandler = NULL; - } -} - -void PMAPI PM_setKey15Handler(PM_key15Handler kh) -{ - getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); - _PM_key15Handler = kh; - setISR(0x15, _PM_key15ISR); -} - -void PMAPI PM_restoreKey15Handler(void) -{ - if (_PM_key15Handler) { - restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); - _PM_key15Handler = NULL; - } -} - -void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) -{ - static int ctrlCFlag,ctrlBFlag; - - _PM_ctrlCPtr = (uchar*)&ctrlCFlag; - _PM_ctrlBPtr = (uchar*)&ctrlBFlag; - getISR(0x1B, &_PM_prevBreak, &prevRealBreak); - getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); - _PM_breakHandler = bh; - setISR(0x1B, _PM_breakISR); - setISR(0x23, _PM_ctrlCISR); -} - -void PMAPI PM_installBreakHandler(void) -{ - PM_installAltBreakHandler(NULL); -} - -void PMAPI PM_restoreBreakHandler(void) -{ - if (_PM_prevBreak.sel) { - restoreISR(0x1B, _PM_prevBreak, prevRealBreak); - restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); - _PM_prevBreak.sel = 0; - _PM_breakHandler = NULL; - } -} - -void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) -{ - static short critBuf[2]; - - _PM_critPtr = (uchar*)critBuf; - getISR(0x24, &_PM_prevCritical, &prevRealCritical); - _PM_critHandler = ch; - setISR(0x24, _PM_criticalISR); -} - -void PMAPI PM_installCriticalHandler(void) -{ - PM_installAltCriticalHandler(NULL); -} - -void PMAPI PM_restoreCriticalHandler(void) -{ - if (_PM_prevCritical.sel) { - restoreISR(0x24, _PM_prevCritical, prevRealCritical); - _PM_prevCritical.sel = 0; - _PM_critHandler = NULL; - } -} - -int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - return (_x386_memlock(p,len) == 0); -} - -int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - return (_x386_memunlock(p,len) == 0); -} - -int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - return (_x386_memlock(p,len) == 0); -} - -int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - return (_x386_memunlock(p,len) == 0); -} - -#endif - -/*-------------------------------------------------------------------------*/ -/* Borland's DPMI32 DOS Power Pack Extender support. */ -/*-------------------------------------------------------------------------*/ - -#ifdef DPMI32 -#define GENERIC_DPMI32 /* Use generic 32 bit DPMI routines */ - -void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) -{ - PMREGS regs; - - regs.x.ax = 0x204; - regs.h.bl = intno; - PM_int386(0x31,®s,®s); - isr->sel = regs.x.cx; - isr->off = regs.e.edx; -} - -void PMAPI PM_setPMvect(int intno, PM_intHandler isr) -{ - PMSREGS sregs; - PMREGS regs; - - PM_saveDS(); - regs.x.ax = 0x205; /* Set protected mode vector */ - regs.h.bl = intno; - PM_segread(&sregs); - regs.x.cx = sregs.cs; - regs.e.edx = (uint)isr; - PM_int386(0x31,®s,®s); -} - -void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) -{ - PMREGS regs; - - regs.x.ax = 0x205; - regs.h.bl = intno; - regs.x.cx = isr.sel; - regs.e.edx = isr.off; - PM_int386(0x31,®s,®s); -} -#endif - -/*-------------------------------------------------------------------------*/ -/* Watcom C/C++ with Rational DOS/4GW support. */ -/*-------------------------------------------------------------------------*/ - -#ifdef DOS4GW -#define GENERIC_DPMI32 /* Use generic 32 bit DPMI routines */ - -#define MOUSE_SUPPORTED /* DOS4GW directly supports mouse */ - -/* We use the normal DOS services to save and restore interrupts handlers - * for Watcom C++, because using the direct DPMI functions does not - * appear to work properly. At least if we use the DPMI functions, we - * dont get the auto-passup feature that we need to correctly trap - * real and protected mode interrupts without installing Bi-model - * interrupt handlers. - */ - -void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) -{ - PMREGS regs; - PMSREGS sregs; - - PM_segread(&sregs); - regs.h.ah = 0x35; - regs.h.al = intno; - PM_int386x(0x21,®s,®s,&sregs); - isr->sel = sregs.es; - isr->off = regs.e.ebx; -} - -void PMAPI PM_setPMvect(int intno, PM_intHandler isr) -{ - PMREGS regs; - PMSREGS sregs; - - PM_saveDS(); - PM_segread(&sregs); - regs.h.ah = 0x25; - regs.h.al = intno; - sregs.ds = sregs.cs; - regs.e.edx = (uint)isr; - PM_int386x(0x21,®s,®s,&sregs); -} - -void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) -{ - PMREGS regs; - PMSREGS sregs; - - PM_segread(&sregs); - regs.h.ah = 0x25; - regs.h.al = intno; - sregs.ds = isr.sel; - regs.e.edx = isr.off; - PM_int386x(0x21,®s,®s,&sregs); -} - -int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) -{ - lockPMHandlers(); /* Ensure our handlers are locked */ - - _PM_mouseHandler = mh; - _PM_setMouseHandler(_PM_mouseMask = mask); - return 1; -} - -void PMAPI PM_restoreMouseHandler(void) -{ - PMREGS regs; - - if (_PM_mouseHandler) { - regs.x.ax = 33; - PM_int386(0x33, ®s, ®s); - _PM_mouseHandler = NULL; - } -} - -#endif - -/*-------------------------------------------------------------------------*/ -/* DJGPP port of GNU C++ support. */ -/*-------------------------------------------------------------------------*/ - -#ifdef DJGPP -#define GENERIC_DPMI32 /* Use generic 32 bit DPMI routines */ - -void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) -{ - PMREGS regs; - - regs.x.ax = 0x204; - regs.h.bl = intno; - PM_int386(0x31,®s,®s); - isr->sel = regs.x.cx; - isr->off = regs.e.edx; -} - -void PMAPI PM_setPMvect(int intno, PM_intHandler isr) -{ - PMSREGS sregs; - PMREGS regs; - - PM_saveDS(); - regs.x.ax = 0x205; /* Set protected mode vector */ - regs.h.bl = intno; - PM_segread(&sregs); - regs.x.cx = sregs.cs; - regs.e.edx = (uint)isr; - PM_int386(0x31,®s,®s); -} - -void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) -{ - PMREGS regs; - - regs.x.ax = 0x205; - regs.h.bl = intno; - regs.x.cx = isr.sel; - regs.e.edx = isr.off; - PM_int386(0x31,®s,®s); -} - -#endif - -/*-------------------------------------------------------------------------*/ -/* Generic 32 bit DPMI routines */ -/*-------------------------------------------------------------------------*/ - -#if defined(GENERIC_DPMI32) - -static long prevRealBreak; /* Previous real mode break handler */ -static long prevRealCtrlC; /* Previous real mode CtrlC handler */ -static long prevRealCritical; /* Prev real mode critical handler */ - -#ifndef MOUSE_SUPPORTED - -/* The following real mode routine is used to call a 32 bit protected - * mode FAR function from real mode. We use this for passing up control - * from the real mode mouse callback to our protected mode code. - */ - -static long mouseRMCB; /* Mouse real mode callback address */ -static uchar *mousePtr; -static char mouseRegs[0x32]; /* Real mode regs for mouse callback */ -static uchar mouseHandler[] = { - 0x00,0x00,0x00,0x00, /* _realRMCB */ - 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:_realRMCB] */ - 0xCB, /* retf */ - }; - -int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) -{ - RMREGS regs; - RMSREGS sregs; - uint rseg,roff; - - lockPMHandlers(); /* Ensure our handlers are locked */ - - /* Copy the real mode handler to real mode memory */ - if ((mousePtr = PM_allocRealSeg(sizeof(mouseHandler),&rseg,&roff)) == NULL) - return 0; - memcpy(mousePtr,mouseHandler,sizeof(mouseHandler)); - if (!_DPMI_allocateCallback(_PM_mousePMCB, mouseRegs, &mouseRMCB)) - PM_fatalError("Unable to allocate real mode callback!\n"); - PM_setLong(mousePtr,mouseRMCB); - - /* Install the real mode mouse handler */ - _PM_mouseHandler = mh; - sregs.es = rseg; - regs.x.dx = roff+4; - regs.x.cx = _PM_mouseMask = mask; - regs.x.ax = 0xC; - PM_int86x(0x33, ®s, ®s, &sregs); - return 1; -} - -void PMAPI PM_restoreMouseHandler(void) -{ - RMREGS regs; - - if (_PM_mouseHandler) { - regs.x.ax = 33; - PM_int86(0x33, ®s, ®s); - PM_freeRealSeg(mousePtr); - _DPMI_freeCallback(mouseRMCB); - _PM_mouseHandler = NULL; - } -} - -#endif - -static void getISR(int intno, PMFARPTR *pmisr, long *realisr) -{ - PM_getPMvect(intno,pmisr); - _PM_getRMvect(intno,realisr); -} - -static void restoreISR(int intno, PMFARPTR pmisr, long realisr) -{ - _PM_setRMvect(intno,realisr); - PM_restorePMvect(intno,pmisr); -} - -static void setISR(int intno, void (* PMAPI pmisr)()) -{ - lockPMHandlers(); /* Ensure our handlers are locked */ - PM_setPMvect(intno,pmisr); -} - -void PMAPI PM_setTimerHandler(PM_intHandler th) -{ - getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer); - _PM_timerHandler = th; - setISR(0x8, _PM_timerISR); -} - -void PMAPI PM_restoreTimerHandler(void) -{ - if (_PM_timerHandler) { - restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer); - _PM_timerHandler = NULL; - } -} - -ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) -{ - /* Save the old CMOS real time clock values */ - _PM_oldCMOSRegA = _PM_readCMOS(0x0A); - _PM_oldCMOSRegB = _PM_readCMOS(0x0B); - - /* Set the real time clock interrupt handler */ - getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); - _PM_rtcHandler = th; - setISR(0x70, _PM_rtcISR); - - /* Program the real time clock default frequency */ - PM_setRealTimeClockFrequency(frequency); - - /* Unmask IRQ8 in the PIC2 */ - _PM_oldRTCPIC2 = PM_inpb(0xA1); - PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); - return true; -} - -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - if (_PM_rtcHandler) { - /* Restore CMOS registers and mask RTC clock */ - _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); - _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); - PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); - - /* Restore the interrupt vector */ - restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); - _PM_rtcHandler = NULL; - } -} - -PM_IRQHandle PMAPI PM_setIRQHandler( - int IRQ, - PM_irqHandler ih) -{ - int thunkSize,PICmask,chainPrevious; - ulong offsetAdjust; - _PM_IRQHandle *handle; - - thunkSize = (ulong)_PM_irqISRTemplateEnd - (ulong)_PM_irqISRTemplate; - if ((handle = PM_malloc(sizeof(_PM_IRQHandle) + thunkSize)) == NULL) - return NULL; - handle->IRQ = IRQ; - handle->prevPIC = PM_inpb(0x21); - handle->prevPIC2 = PM_inpb(0xA1); - if (IRQ < 8) { - handle->IRQVect = (IRQ + 8); - PICmask = (1 << IRQ); - chainPrevious = ((handle->prevPIC & PICmask) == 0); - } - else { - handle->IRQVect = (0x60 + IRQ + 8); - PICmask = ((1 << IRQ) | 0x4); - chainPrevious = ((handle->prevPIC2 & (PICmask >> 8)) == 0); - } - - /* Copy and setup the assembler thunk */ - offsetAdjust = (ulong)handle->thunk - (ulong)_PM_irqISRTemplate; - memcpy(handle->thunk,_PM_irqISRTemplate,thunkSize); - *((ulong*)&handle->thunk[2]) = offsetAdjust; - *((ulong*)&handle->thunk[11+0]) = (ulong)ih; - if (chainPrevious) { - *((ulong*)&handle->thunk[11+4]) = handle->prevHandler.off; - *((ulong*)&handle->thunk[11+8]) = handle->prevHandler.sel; - } - else { - *((ulong*)&handle->thunk[11+4]) = 0; - *((ulong*)&handle->thunk[11+8]) = 0; - } - *((ulong*)&handle->thunk[11+12]) = IRQ; - - /* Set the real time clock interrupt handler */ - getISR(handle->IRQVect, &handle->prevHandler, &handle->prevRealhandler); - setISR(handle->IRQVect, (PM_intHandler)handle->thunk); - - /* Unmask the IRQ in the PIC */ - PM_outpb(0xA1,handle->prevPIC2 & ~(PICmask >> 8)); - PM_outpb(0x21,handle->prevPIC & ~PICmask); - return handle; -} - -void PMAPI PM_restoreIRQHandler( - PM_IRQHandle irqHandle) -{ - int PICmask; - _PM_IRQHandle *handle = irqHandle; - - /* Restore PIC mask for the interrupt */ - if (handle->IRQ < 8) - PICmask = (1 << handle->IRQ); - else - PICmask = ((1 << handle->IRQ) | 0x4); - PM_outpb(0xA1,(PM_inpb(0xA1) & ~(PICmask >> 8)) | (handle->prevPIC2 & (PICmask >> 8))); - PM_outpb(0x21,(PM_inpb(0x21) & ~PICmask) | (handle->prevPIC & PICmask)); - - /* Restore the interrupt vector */ - restoreISR(handle->IRQVect, handle->prevHandler, handle->prevRealhandler); - - /* Finally free the thunk */ - PM_free(handle); -} - -void PMAPI PM_setKeyHandler(PM_intHandler kh) -{ - getISR(0x9, &_PM_prevKey, &_PM_prevRealKey); - _PM_keyHandler = kh; - setISR(0x9, _PM_keyISR); -} - -void PMAPI PM_restoreKeyHandler(void) -{ - if (_PM_keyHandler) { - restoreISR(0x9, _PM_prevKey, _PM_prevRealKey); - _PM_keyHandler = NULL; - } -} - -void PMAPI PM_setKey15Handler(PM_key15Handler kh) -{ - getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); - _PM_key15Handler = kh; - setISR(0x15, _PM_key15ISR); -} - -void PMAPI PM_restoreKey15Handler(void) -{ - if (_PM_key15Handler) { - restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); - _PM_key15Handler = NULL; - } -} - -/* Real mode Ctrl-C and Ctrl-Break handler. This handler simply sets a - * flag in the real mode code segment and exit. We save the location - * of this flag in real mode memory so that both the real mode and - * protected mode code will be modifying the same flags. - */ - -#ifndef DOS4GW -static uchar ctrlHandler[] = { - 0x00,0x00,0x00,0x00, /* ctrlBFlag */ - 0x66,0x2E,0xC7,0x06,0x00,0x00, - 0x01,0x00,0x00,0x00, /* mov [cs:ctrlBFlag],1 */ - 0xCF, /* iretf */ - }; -#endif - -void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) -{ -#ifndef DOS4GW - uint rseg,roff; -#else - static int ctrlCFlag,ctrlBFlag; - - _PM_ctrlCPtr = (uchar*)&ctrlCFlag; - _PM_ctrlBPtr = (uchar*)&ctrlBFlag; -#endif - - getISR(0x1B, &_PM_prevBreak, &prevRealBreak); - getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); - _PM_breakHandler = bh; - setISR(0x1B, _PM_breakISR); - setISR(0x23, _PM_ctrlCISR); - -#ifndef DOS4GW - /* Hook the real mode vectors for these handlers, as these are not - * normally reflected by the DPMI server up to protected mode - */ - _PM_ctrlBPtr = PM_allocRealSeg(sizeof(ctrlHandler)*2, &rseg, &roff); - memcpy(_PM_ctrlBPtr,ctrlHandler,sizeof(ctrlHandler)); - memcpy(_PM_ctrlBPtr+sizeof(ctrlHandler),ctrlHandler,sizeof(ctrlHandler)); - _PM_ctrlCPtr = _PM_ctrlBPtr + sizeof(ctrlHandler); - _PM_setRMvect(0x1B,((long)rseg << 16) | (roff+4)); - _PM_setRMvect(0x23,((long)rseg << 16) | (roff+sizeof(ctrlHandler)+4)); -#endif -} - -void PMAPI PM_installBreakHandler(void) -{ - PM_installAltBreakHandler(NULL); -} - -void PMAPI PM_restoreBreakHandler(void) -{ - if (_PM_prevBreak.sel) { - restoreISR(0x1B, _PM_prevBreak, prevRealBreak); - restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); - _PM_prevBreak.sel = 0; - _PM_breakHandler = NULL; -#ifndef DOS4GW - PM_freeRealSeg(_PM_ctrlBPtr); -#endif - } -} - -/* Real mode Critical Error handler. This handler simply saves the AX and - * DI values in the real mode code segment and exits. We save the location - * of this flag in real mode memory so that both the real mode and - * protected mode code will be modifying the same flags. - */ - -#ifndef DOS4GW -static uchar criticalHandler[] = { - 0x00,0x00, /* axCode */ - 0x00,0x00, /* diCode */ - 0x2E,0xA3,0x00,0x00, /* mov [cs:axCode],ax */ - 0x2E,0x89,0x3E,0x02,0x00, /* mov [cs:diCode],di */ - 0xB8,0x03,0x00, /* mov ax,3 */ - 0xCF, /* iretf */ - }; -#endif - -void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) -{ -#ifndef DOS4GW - uint rseg,roff; -#else - static short critBuf[2]; - - _PM_critPtr = (uchar*)critBuf; -#endif - - getISR(0x24, &_PM_prevCritical, &prevRealCritical); - _PM_critHandler = ch; - setISR(0x24, _PM_criticalISR); - -#ifndef DOS4GW - /* Hook the real mode vector, as this is not normally reflected by the - * DPMI server up to protected mode. - */ - _PM_critPtr = PM_allocRealSeg(sizeof(criticalHandler)*2, &rseg, &roff); - memcpy(_PM_critPtr,criticalHandler,sizeof(criticalHandler)); - _PM_setRMvect(0x24,((long)rseg << 16) | (roff+4)); -#endif -} - -void PMAPI PM_installCriticalHandler(void) -{ - PM_installAltCriticalHandler(NULL); -} - -void PMAPI PM_restoreCriticalHandler(void) -{ - if (_PM_prevCritical.sel) { - restoreISR(0x24, _PM_prevCritical, prevRealCritical); - PM_freeRealSeg(_PM_critPtr); - _PM_prevCritical.sel = 0; - _PM_critHandler = NULL; - } -} - -int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - PMSREGS sregs; - PM_segread(&sregs); - return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); -} - -int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - PMSREGS sregs; - PM_segread(&sregs); - return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); -} - -int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - PMSREGS sregs; - PM_segread(&sregs); - return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.cs),len); -} - -int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - PMSREGS sregs; - PM_segread(&sregs); - return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.cs),len); -} - -#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c deleted file mode 100644 index c3e9b6c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c +++ /dev/null @@ -1,251 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit DOS -* -* Description: Main C module for the VFlat framebuffer routines. The page -* fault handler is always installed to handle up to a 4Mb -* framebuffer with a window size of 4Kb or 64Kb in size. -* -****************************************************************************/ - -#include "pmapi.h" -#include -#include - -/*-------------------------------------------------------------------------*/ -/* DOS4G/W, PMODE/W and CauseWay support. */ -/*-------------------------------------------------------------------------*/ - -#if defined(DOS4GW) - -#define VFLAT_START_ADDR 0xF0000000U -#define VFLAT_END_ADDR 0xF03FFFFFU -#define VFLAT_LIMIT (VFLAT_END_ADDR - VFLAT_START_ADDR) -#define PAGE_PRESENT 1 -#define PAGE_NOTPRESENT 0 -#define PAGE_READ 0 -#define PAGE_WRITE 2 - -PRIVATE ibool installed = false; -PRIVATE ibool haveDPMI = false; -PUBLIC ibool _ASMAPI VF_haveCauseWay = false; -PUBLIC uchar * _ASMAPI VF_zeroPtr = NULL; - -/* Low level assembler code */ - -int _ASMAPI InitPaging(void); -void _ASMAPI ClosePaging(void); -void _ASMAPI MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags); -void _ASMAPI InstallFaultHandler(ulong baseAddr,int bankSize); -void _ASMAPI RemoveFaultHandler(void); -void _ASMAPI InstallBankFunc(int codeLen,void *bankFunc); - -void * _ASMAPI VF_malloc(uint size) -{ return PM_malloc(size); } - -void _ASMAPI VF_free(void *p) -{ PM_free(p); } - -PRIVATE ibool CheckDPMI(void) -/**************************************************************************** -* -* Function: CheckDPMI -* Returns: True if we are running under DPMI -* -****************************************************************************/ -{ - PMREGS regs; - - if (haveDPMI) - return true; - - /* Check if we are running under DPMI in which case we will not be - * able to install our page fault handlers. We can however use the - * DVA.386 or VFLATD.386 virtual device drivers if they are present. - */ - regs.x.ax = 0xFF00; - PM_int386(0x31,®s,®s); - if (!regs.x.cflag && (regs.e.edi & 8)) - return (haveDPMI = true); - return false; -} - -ibool PMAPI VF_available(void) -/**************************************************************************** -* -* Function: VF_available -* Returns: True if virtual buffer is available, false if not. -* -****************************************************************************/ -{ - if (!VF_zeroPtr) - VF_zeroPtr = PM_mapPhysicalAddr(0,0xFFFFFFFF,true); - if (CheckDPMI()) - return false; - - /* Standard DOS4GW, PMODE/W and Causeway */ - if (InitPaging() == -1) - return false; - ClosePaging(); - return true; -} - -void * PMAPI InitDPMI(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -/**************************************************************************** -* -* Function: InitDOS4GW -* Parameters: baseAddr - Base address of framebuffer bank window -* bankSize - Physical size of banks in Kb (4 or 64) -* codeLen - Length of 32 bit bank switch function -* bankFunc - Pointer to protected mode bank function -* Returns: Near pointer to virtual framebuffer, or NULL on failure. -* -* Description: Installs the virtual linear framebuffer handling for -* DPMI environments. This requires the DVA.386 or VFLATD.386 -* virtual device drivers to be installed and functioning. -* -****************************************************************************/ -{ - (void)baseAddr; - (void)bankSize; - (void)codeLen; - (void)bankFunc; - return NULL; -} - -void * PMAPI InitDOS4GW(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -/**************************************************************************** -* -* Function: InitDOS4GW -* Parameters: baseAddr - Base address of framebuffer bank window -* bankSize - Physical size of banks in Kb (4 or 64) -* codeLen - Length of 32 bit bank switch function -* bankFunc - Pointer to protected mode bank function -* Returns: Near pointer to virtual framebuffer, or NULL on failure. -* -* Description: Installs the virtual linear framebuffer handling for -* the DOS4GW extender. -* -****************************************************************************/ -{ - int i; - - if (InitPaging() == -1) - return NULL; /* Cannot do hardware paging! */ - - /* Map 4MB of video memory into linear address space (read/write) */ - if (bankSize == 64) { - for (i = 0; i < 64; i++) { - MapPhysical2Linear(baseAddr,VFLAT_START_ADDR+(i<<16),16, - PAGE_WRITE | PAGE_NOTPRESENT); - } - } - else { - for (i = 0; i < 1024; i++) { - MapPhysical2Linear(baseAddr,VFLAT_START_ADDR+(i<<12),1, - PAGE_WRITE | PAGE_NOTPRESENT); - } - } - - /* Install our page fault handler and banks switch function */ - InstallFaultHandler(baseAddr,bankSize); - InstallBankFunc(codeLen,bankFunc); - installed = true; - return (void*)VFLAT_START_ADDR; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -/**************************************************************************** -* -* Function: VF_init -* Parameters: baseAddr - Base address of framebuffer bank window -* bankSize - Physical size of banks in Kb (4 or 64) -* codeLen - Length of 32 bit bank switch function -* bankFunc - Pointer to protected mode bank function -* Returns: Near pointer to virtual framebuffer, or NULL on failure. -* -* Description: Installs the virtual linear framebuffer handling. -* -****************************************************************************/ -{ - if (installed) - return (void*)VFLAT_START_ADDR; - if (codeLen > 100) - return NULL; /* Bank function is too large! */ - if (!VF_zeroPtr) - VF_zeroPtr = PM_mapPhysicalAddr(0,0xFFFFFFFF,true); - if (CheckDPMI()) - return InitDPMI(baseAddr,bankSize,codeLen,bankFunc); - return InitDOS4GW(baseAddr,bankSize,codeLen,bankFunc); -} - -void PMAPI VF_exit(void) -/**************************************************************************** -* -* Function: VF_exit -* -* Description: Closes down the virtual framebuffer services and -* restores the previous page fault handler. -* -****************************************************************************/ -{ - if (installed) { - if (haveDPMI) { - /* DPMI support */ - } - else { - /* Standard DOS4GW and PMODE/W support */ - RemoveFaultHandler(); - ClosePaging(); - } - installed = false; - } -} - -/*-------------------------------------------------------------------------*/ -/* Support mapped out for other compilers. */ -/*-------------------------------------------------------------------------*/ - -#else - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -{ - (void)baseAddr; - (void)bankSize; - (void)codeLen; - (void)bankFunc; - return NULL; -} - -void PMAPI VF_exit(void) -{ -} - -#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c deleted file mode 100644 index 53ab16c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: MSDOS -* -* Description: OS specific implementation for the Zen Timer functions. -* -****************************************************************************/ - - -/*---------------------------- Global variables ---------------------------*/ - -uchar * _VARAPI _ZTimerBIOSPtr; - -/*----------------------------- Implementation ----------------------------*/ - -/* External assembler functions */ - -void _ASMAPI LZ_timerOn(void); -ulong _ASMAPI LZ_timerLap(void); -void _ASMAPI LZ_timerOff(void); -ulong _ASMAPI LZ_timerCount(void); -void _ASMAPI LZ_disable(void); -void _ASMAPI LZ_enable(void); - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -void __ZTimerInit(void) -{ - _ZTimerBIOSPtr = PM_getBIOSPointer(); -} - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerOn(tm) LZ_timerOn() - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerLap(tm) LZ_timerLap() - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerOff(tm) LZ_timerOff() - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerCount(tm) LZ_timerCount() - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as microseconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION 54925 - -/**************************************************************************** -REMARKS: -Read the Long Period timer value from the BIOS timer tick. -****************************************************************************/ -static ulong __ULZReadTime(void) -{ - ulong ticks; - LZ_disable(); /* Turn of interrupts */ - ticks = PM_getLong(_ZTimerBIOSPtr+0x6C); - LZ_enable(); /* Turn on interrupts again */ - return ticks; -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong __ULZElapsedTime(ulong start,ulong finish) -{ - if (finish < start) - finish += 1573040L; /* Number of ticks in 24 hours */ - return finish - start; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/event.c b/board/MAI/bios_emulator/scitech/src/pm/event.c deleted file mode 100644 index b6f4586..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/event.c +++ /dev/null @@ -1,1115 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Main implementation for the SciTech cross platform event -* library. This module contains all the generic cross platform -* code, and pulls in modules specific to each target OS -* environment. -* -****************************************************************************/ - -#include "event.h" -#include "pmapi.h" -#include -#include -#include -#include -#include -#include "oshdr.h" - -/*--------------------------- Global variables ----------------------------*/ - -#define EVENTQSIZE 100 /* Number of events in event queue */ -#define JOY_NUM_AXES 4 /* Number of joystick axes supported */ - -static struct { - int mx,my; /* Current mouse position */ - int head; /* Head of event queue */ - int tail; /* Tail of event queue */ - int freeHead; /* Head of free list */ - int count; /* No. of items currently in queue */ - event_t evtq[EVENTQSIZE]; /* The queue structure itself */ - int oldMove; /* Previous movement event */ - int oldKey; /* Previous key repeat event */ - int oldJoyMove; /* Previous joystick movement event */ - int joyMask; /* Mask of joystick axes present */ - int joyMin[JOY_NUM_AXES]; - int joyCenter[JOY_NUM_AXES]; - int joyMax[JOY_NUM_AXES]; - int joyPrev[JOY_NUM_AXES]; - int joyButState; - ulong doubleClick; - ulong autoRepeat; - ulong autoDelay; - ulong autoTicks; - ulong doubleClickThresh; - ulong firstAuto; - int autoMouse_x; - int autoMouse_y; - event_t downMouse; - ulong keyModifiers; /* Current keyboard modifiers */ - uchar keyTable[128]; /* Table of key up/down flags */ - ibool allowLEDS; /* True if LEDS should change */ - _EVT_userEventFilter userEventCallback; - _EVT_mouseMoveHandler mouseMove; - _EVT_heartBeatCallback heartBeat; - void *heartBeatParams; - codepage_t *codePage; - } EVT; - -/*---------------------------- Implementation -----------------------------*/ - -#if defined(__REALDOS__) || defined(__SMX32__) -/* {secret} */ -void EVTAPI _EVT_cCodeStart(void) {} -#endif - -/* External assembler functions */ - -int EVTAPI _EVT_readJoyAxis(int mask,int *axis); -int EVTAPI _EVT_readJoyButtons(void); - -/* Forward declaration */ - -ulong _EVT_getTicks(void); - -/**************************************************************************** -PARAMETERS: -evt - Event to add to the event queue - -REMARKS: -Adds an event to the event queue by tacking it onto the tail of the event -queue. This routine assumes that at least one spot is available on the -freeList for the event to be inserted. - -NOTE: Interrupts MUST be OFF while this routine is called to ensure we have - mutually exclusive access to our internal data structures for - interrupt driven systems (like under DOS). -****************************************************************************/ -static void addEvent( - event_t *evt) -{ - int evtID; - - /* Check for mouse double click events */ - if (evt->what & EVT_MOUSEEVT) { - EVT.autoMouse_x = evt->where_x; - EVT.autoMouse_y = evt->where_y; - if ((evt->what & EVT_MOUSEDOWN) && !(evt->message & EVT_DBLCLICK)) { - /* Determine if the last mouse event was a double click event */ - uint diff_x = ABS(evt->where_x - EVT.downMouse.where_x); - uint diff_y = ABS(evt->where_y - EVT.downMouse.where_y); - if ((evt->message == EVT.downMouse.message) - && ((evt->when - EVT.downMouse.when) <= EVT.doubleClick) - && (diff_x <= EVT.doubleClickThresh) - && (diff_y <= EVT.doubleClickThresh)) { - evt->message |= EVT_DBLCLICK; - EVT.downMouse = *evt; - EVT.downMouse.when = 0; - } - else - EVT.downMouse = *evt; - EVT.autoTicks = _EVT_getTicks(); - } - else if (evt->what & EVT_MOUSEUP) { - EVT.downMouse.what = EVT_NULLEVT; - EVT.firstAuto = true; - } - } - - /* Call user supplied callback to modify the event if desired */ - if (EVT.userEventCallback) { - if (!EVT.userEventCallback(evt)) - return; - } - - /* Get spot to place the event from the free list */ - evtID = EVT.freeHead; - EVT.freeHead = EVT.evtq[EVT.freeHead].next; - - /* Add to the EVT.tail of the event queue */ - evt->next = -1; - evt->prev = EVT.tail; - if (EVT.tail != -1) - EVT.evtq[EVT.tail].next = evtID; - else - EVT.head = evtID; - EVT.tail = evtID; - EVT.evtq[evtID] = *evt; - EVT.count++; -} - -/**************************************************************************** -REMARKS: -Internal function to initialise the event queue to the empty state. -****************************************************************************/ -static void initEventQueue(void) -{ - int i; - - /* Build free list, and initialize global data structures */ - for (i = 0; i < EVENTQSIZE; i++) - EVT.evtq[i].next = i+1; - EVT.evtq[EVENTQSIZE-1].next = -1; /* Terminate list */ - EVT.count = EVT.freeHead = 0; - EVT.head = EVT.tail = -1; - EVT.oldMove = -1; - EVT.oldKey = -1; - EVT.oldJoyMove = -1; - EVT.joyButState = 0; - EVT.mx = EVT.my = 0; - EVT.keyModifiers = 0; - EVT.allowLEDS = true; - - /* Set default values for mouse double click and mouse auto events */ - EVT.doubleClick = 440; - EVT.autoRepeat = 55; - EVT.autoDelay = 330; - EVT.autoTicks = 0; - EVT.doubleClickThresh = 5; - EVT.firstAuto = true; - EVT.autoMouse_x = EVT.autoMouse_y = 0; - memset(&EVT.downMouse,0,sizeof(EVT.downMouse)); - - /* Setup default pointers for event library */ - EVT.userEventCallback = NULL; - EVT.codePage = &_CP_US_English; - - /* Initialise the joystick module and do basic calibration (which assumes - * the joystick is centered. - */ - EVT.joyMask = EVT_joyIsPresent(); -} - -#if defined(NEED_SCALE_JOY_AXIS) || !defined(USE_OS_JOYSTICK) -/**************************************************************************** -REMARKS: -This function scales a joystick axis value to normalised form. -****************************************************************************/ -static int scaleJoyAxis( - int raw, - int axis) -{ - int scaled,range; - - /* Make sure the joystick is calibrated properly */ - if (EVT.joyCenter[axis] - EVT.joyMin[axis] < 5) - return raw; - if (EVT.joyMax[axis] - EVT.joyCenter[axis] < 5) - return raw; - - /* Now scale the coordinates to -128 to 127 */ - raw -= EVT.joyCenter[axis]; - if (raw < 0) - range = EVT.joyCenter[axis]-EVT.joyMin[axis]; - else - range = EVT.joyMax[axis]-EVT.joyCenter[axis]; - scaled = (raw * 128) / range; - if (scaled < -128) - scaled = -128; - if (scaled > 127) - scaled = 127; - return scaled; -} -#endif - -#if defined(__SMX32__) -#include "smx/event.c" -#elif defined(__RTTARGET__) -#include "rttarget/event.c" -#elif defined(__REALDOS__) -#include "dos/event.c" -#elif defined(__WINDOWS32__) -#include "win32/event.c" -#elif defined(__OS2__) -#if defined(__OS2_PM__) -#include "os2pm/event.c" -#else -#include "os2/event.c" -#endif -#elif defined(__LINUX__) -#if defined(__USE_X11__) -#include "x11/event.c" -#else -#include "linux/event.c" -#endif -#elif defined(__QNX__) -#if defined(__USE_PHOTON__) -#include "photon/event.c" -#elif defined(__USE_X11__) -#include "x11/event.c" -#else -#include "qnx/event.c" -#endif -#elif defined(__BEOS__) -#include "beos/event.c" -#else -#error Event library not ported to this platform yet! -#endif - -/*------------------------ Public interface routines ----------------------*/ - -/* If USE_OS_JOYSTICK is defined, the OS specific libraries will implement - * the joystick code rather than using the generic OS portable version. - */ - -#ifndef USE_OS_JOYSTICK -/**************************************************************************** -DESCRIPTION: -Returns the mask indicating what joystick axes are attached. - -HEADER: -event.h - -REMARKS: -This function is used to detect the attached joysticks, and determine -what axes are present and functioning. This function will re-detect any -attached joysticks when it is called, so if the user forgot to attach -the joystick when the application started, you can call this function to -re-detect any newly attached joysticks. - -SEE ALSO: -EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent -****************************************************************************/ -int EVTAPI EVT_joyIsPresent(void) -{ - int mask,i; - - memset(EVT.joyMin,0,sizeof(EVT.joyMin)); - memset(EVT.joyCenter,0,sizeof(EVT.joyCenter)); - memset(EVT.joyMax,0,sizeof(EVT.joyMax)); - memset(EVT.joyPrev,0,sizeof(EVT.joyPrev)); - EVT.joyButState = 0; -#ifdef __LINUX__ - PM_init(); -#endif - mask = _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); - if (mask) { - for (i = 0; i < JOY_NUM_AXES; i++) - EVT.joyMax[i] = EVT.joyCenter[i]*2; - } - return mask; -} - -/**************************************************************************** -DESCRIPTION: -Polls the joystick for position and button information. - -HEADER: -event.h - -REMARKS: -This routine is used to poll analogue joysticks for button and position -information. It should be called once for each main loop of the user -application, just before processing all pending events via EVT_getNext. -All information polled from the joystick will be posted to the event -queue for later retrieval. - -Note: Most analogue joysticks will provide readings that change even - though the joystick has not moved. Hence if you call this routine - you will likely get an EVT_JOYMOVE event every time through your - event loop. - -SEE ALSO: -EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight, -EVT_joySetCenter, EVT_joyIsPresent -****************************************************************************/ -void EVTAPI EVT_pollJoystick(void) -{ - event_t evt; - int i,axis[JOY_NUM_AXES],newButState,mask,moved,ps; - - if (EVT.joyMask) { - /* Read joystick axes and post movement events if they have - * changed since the last time we polled. Until the events are - * actually flushed, we keep modifying the same joystick movement - * event, so you won't get multiple movement event - */ - mask = _EVT_readJoyAxis(EVT.joyMask,axis); - newButState = _EVT_readJoyButtons(); - moved = false; - for (i = 0; i < JOY_NUM_AXES; i++) { - if (mask & (EVT_JOY_AXIS_X1 << i)) - axis[i] = scaleJoyAxis(axis[i],i); - else - axis[i] = EVT.joyPrev[i]; - if (axis[i] != EVT.joyPrev[i]) - moved = true; - } - if (moved) { - memcpy(EVT.joyPrev,axis,sizeof(EVT.joyPrev)); - ps = _EVT_disableInt(); - if (EVT.oldJoyMove != -1) { - /* Modify the existing joystick movement event */ - EVT.evtq[EVT.oldJoyMove].message = newButState; - EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; - EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; - EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; - EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; - } - else if (EVT.count < EVENTQSIZE) { - /* Add a new joystick movement event */ - EVT.oldJoyMove = EVT.freeHead; - memset(&evt,0,sizeof(evt)); - evt.what = EVT_JOYMOVE; - evt.message = EVT.joyButState; - evt.where_x = EVT.joyPrev[0]; - evt.where_y = EVT.joyPrev[1]; - evt.relative_x = EVT.joyPrev[2]; - evt.relative_y = EVT.joyPrev[3]; - addEvent(&evt); - } - _EVT_restoreInt(ps); - } - - /* Read the joystick buttons, and post events to reflect the change - * in state for the joystick buttons. - */ - if (newButState != EVT.joyButState) { - if (EVT.count < EVENTQSIZE) { - /* Add a new joystick click event */ - ps = _EVT_disableInt(); - memset(&evt,0,sizeof(evt)); - evt.what = EVT_JOYCLICK; - evt.message = newButState; - EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; - EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; - EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; - EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; - addEvent(&evt); - _EVT_restoreInt(ps); - } - EVT.joyButState = newButState; - } - } -} - -/**************************************************************************** -DESCRIPTION: -Calibrates the joystick upper left position - -HEADER: -event.h - -REMARKS: -This function can be used to zero in on better joystick calibration factors, -which may work better than the default simplistic calibration (which assumes -the joystick is centered when the event library is initialised). -To use this function, ask the user to hold the stick in the upper left -position and then have them press a key or button. and then call this -function. This function will then read the joystick and update the -calibration factors. - -Usually, assuming that the stick was centered when the event library was -initialized, you really only need to call EVT_joySetLowerRight since the -upper left position is usually always 0,0 on most joysticks. However, the -safest procedure is to call all three calibration functions. - -SEE ALSO: -EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent -****************************************************************************/ -void EVTAPI EVT_joySetUpperLeft(void) -{ - _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMin); -} - -/**************************************************************************** -DESCRIPTION: -Calibrates the joystick lower right position - -HEADER: -event.h - -REMARKS: -This function can be used to zero in on better joystick calibration factors, -which may work better than the default simplistic calibration (which assumes -the joystick is centered when the event library is initialised). -To use this function, ask the user to hold the stick in the lower right -position and then have them press a key or button. and then call this -function. This function will then read the joystick and update the -calibration factors. - -Usually, assuming that the stick was centered when the event library was -initialized, you really only need to call EVT_joySetLowerRight since the -upper left position is usually always 0,0 on most joysticks. However, the -safest procedure is to call all three calibration functions. - -SEE ALSO: -EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent -****************************************************************************/ -void EVTAPI EVT_joySetLowerRight(void) -{ - _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMax); -} - -/**************************************************************************** -DESCRIPTION: -Calibrates the joystick center position - -HEADER: -event.h - -REMARKS: -This function can be used to zero in on better joystick calibration factors, -which may work better than the default simplistic calibration (which assumes -the joystick is centered when the event library is initialised). -To use this function, ask the user to hold the stick in the center -position and then have them press a key or button. and then call this -function. This function will then read the joystick and update the -calibration factors. - -Usually, assuming that the stick was centered when the event library was -initialized, you really only need to call EVT_joySetLowerRight since the -upper left position is usually always 0,0 on most joysticks. However, the -safest procedure is to call all three calibration functions. - -SEE ALSO: -EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter -****************************************************************************/ -void EVTAPI EVT_joySetCenter(void) -{ - _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); -} -#endif - -/**************************************************************************** -DESCRIPTION: -Posts a user defined event to the event queue - -HEADER: -event.h - -RETURNS: -True if event was posted, false if event queue is full. - -PARAMETERS: -what - Type code for message to post -message - Event specific message to post -modifiers - Event specific modifier flags to post - -REMARKS: -This routine is used to post user defined events to the event queue. - -SEE ALSO: -EVT_flush, EVT_getNext, EVT_peekNext, EVT_halt -****************************************************************************/ -ibool EVTAPI EVT_post( - ulong which, - ulong what, - ulong message, - ulong modifiers) -{ - event_t evt; - uint ps; - - if (EVT.count < EVENTQSIZE) { - /* Save information in event record */ - ps = _EVT_disableInt(); - evt.which = which; - evt.when = _EVT_getTicks(); - evt.what = what; - evt.message = message; - evt.modifiers = modifiers; - addEvent(&evt); /* Add to EVT.tail of event queue */ - _EVT_restoreInt(ps); - return true; - } - else - return false; -} - -/**************************************************************************** -DESCRIPTION: -Flushes all events of a specified type from the event queue. - -PARAMETERS: -mask - Mask specifying the types of events that should be removed - -HEADER: -event.h - -REMARKS: -Flushes (removes) all pending events of the specified type from the event -queue. You may combine the masks for different event types with a simple -logical OR. - -SEE ALSO: -EVT_getNext, EVT_halt, EVT_peekNext -****************************************************************************/ -void EVTAPI EVT_flush( - ulong mask) -{ - event_t evt; - - do { /* Flush all events */ - EVT_getNext(&evt,mask); - } while (evt.what != EVT_NULLEVT); -} - -/**************************************************************************** -DESCRIPTION: -Halts until and event of the specified type is recieved. - -HEADER: -event.h - -PARAMETERS: -evt - Pointer to -mask - Mask specifying the types of events that should be removed - -REMARKS: -This functions halts exceution until an event of the specified type is -recieved into the event queue. It does not flush the event queue of events -before performing the busy loop. However this function does throw away -any events other than the ones you have requested via the event mask, to -avoid the event queue filling up with unwanted events (like EVT_KEYUP or -EVT_MOUSEMOVE events). - -SEE ALSO: -EVT_getNext, EVT_flush, EVT_peekNext -****************************************************************************/ -void EVTAPI EVT_halt( - event_t *evt, - ulong mask) -{ - do { /* Wait for an event */ - if (mask & (EVT_JOYEVT)) - EVT_pollJoystick(); - EVT_getNext(evt,EVT_EVERYEVT); - } while (!(evt->what & mask)); -} - -/**************************************************************************** -DESCRIPTION: -Peeks at the next pending event in the event queue. - -HEADER: -event.h - -RETURNS: -True if an event is pending, false if not. - -PARAMETERS: -evt - Pointer to structure to return the event info in -mask - Mask specifying the types of events that should be removed - -REMARKS: -Peeks at the next pending event of the specified type in the event queue. The -mask parameter is used to specify the type of events to be peeked at, and -can be any logical combination of any of the flags defined by the -EVT_eventType enumeration. - -In contrast to EVT_getNext, the event is not removed from the event queue. -You may combine the masks for different event types with a simple logical OR. - -SEE ALSO: -EVT_flush, EVT_getNext, EVT_halt -****************************************************************************/ -ibool EVTAPI EVT_peekNext( - event_t *evt, - ulong mask) -{ - int evtID; - uint ps; - - if (EVT.heartBeat) - EVT.heartBeat(EVT.heartBeatParams); - _EVT_pumpMessages(); /* Pump all messages into queue */ - EVT.mouseMove(EVT.mx,EVT.my); /* Move the mouse cursor */ - evt->what = EVT_NULLEVT; /* Default to null event */ - if (EVT.count) { - /* It is possible that an event be posted while we are trying - * to access the event queue. This would create problems since - * we may end up with invalid data for our event queue pointers. To - * alleviate this, all interrupts are suspended while we manipulate - * our pointers. - */ - ps = _EVT_disableInt(); /* disable interrupts */ - for (evtID = EVT.head; evtID != -1; evtID = EVT.evtq[evtID].next) { - if (EVT.evtq[evtID].what & mask) - break; /* Found an event */ - } - if (evtID == -1) { - _EVT_restoreInt(ps); - return false; /* Event was not found */ - } - *evt = EVT.evtq[evtID]; /* Return the event */ - _EVT_restoreInt(ps); - if (evt->what & EVT_KEYEVT) - _EVT_maskKeyCode(evt); - } - return evt->what != EVT_NULLEVT; -} - -/**************************************************************************** -DESCRIPTION: -Retrieves the next pending event from the event queue. - -PARAMETERS: -evt - Pointer to structure to return the event info in -mask - Mask specifying the types of events that should be removed - -HEADER: -event.h - -RETURNS: -True if an event was pending, false if not. - -REMARKS: -Retrieves the next pending event from the event queue, and stores it in a -event_t structure. The mask parameter is used to specify the type of events -to be removed, and can be any logical combination of any of the flags defined -by the EVT_eventType enumeration. - -The what field of the event contains the event code of the event that was -extracted. All application specific events should begin with the EVT_USEREVT -code and build from there. Since the event code is stored in an integer, -there is a maximum of 32 different event codes that can be distinguished. -You can store extra information about the event in the message field to -distinguish between events of the same class (for instance the button used in -a EVT_MOUSEDOWN event). - -If an event of the specified type was not in the event queue, the what field -of the event will be set to NULLEVT, and the return value will return false. - -Note: You should /always/ use the EVT_EVERYEVT mask for extracting events - from your main event loop handler. Using a mask for only a specific - type of event for long periods of time will cause the event queue to - fill up with events of the type you are ignoring, eventually causing - the application to hang when the event queue becomes full. - -SEE ALSO: -EVT_flush, EVT_halt, EVT_peekNext -****************************************************************************/ -ibool EVTAPI EVT_getNext( - event_t *evt, - ulong mask) -{ - int evtID,next,prev; - uint ps; - - if (EVT.heartBeat) - EVT.heartBeat(EVT.heartBeatParams); - _EVT_pumpMessages(); /* Pump all messages into queue */ - EVT.mouseMove(EVT.mx,EVT.my); /* Move the mouse cursor */ - evt->what = EVT_NULLEVT; /* Default to null event */ - if (EVT.count) { - /* It is possible that an event be posted while we are trying - * to access the event queue. This would create problems since - * we may end up with invalid data for our event queue pointers. To - * alleviate this, all interrupts are suspended while we manipulate - * our pointers. - */ - ps = _EVT_disableInt(); /* disable interrupts */ - for (evtID = EVT.head; evtID != -1; evtID = EVT.evtq[evtID].next) { - if (EVT.evtq[evtID].what & mask) - break; /* Found an event */ - } - if (evtID == -1) { - _EVT_restoreInt(ps); - return false; /* Event was not found */ - } - next = EVT.evtq[evtID].next; - prev = EVT.evtq[evtID].prev; - if (prev != -1) - EVT.evtq[prev].next = next; - else - EVT.head = next; - if (next != -1) - EVT.evtq[next].prev = prev; - else - EVT.tail = prev; - *evt = EVT.evtq[evtID]; /* Return the event */ - EVT.evtq[evtID].next = EVT.freeHead; /* and return to free list */ - EVT.freeHead = evtID; - EVT.count--; - if (evt->what == EVT_MOUSEMOVE) - EVT.oldMove = -1; - if (evt->what == EVT_KEYREPEAT) - EVT.oldKey = -1; - if (evt->what == EVT_JOYMOVE) - EVT.oldJoyMove = -1; - _EVT_restoreInt(ps); /* enable interrupts */ - if (evt->what & EVT_KEYEVT) - _EVT_maskKeyCode(evt); - } - - /* If there is no event pending, check if we should generate an auto - * mouse down event if the mouse is still currently down. - */ - if (evt->what == EVT_NULLEVT && EVT.autoRepeat && (mask & EVT_MOUSEAUTO) && (EVT.downMouse.what & EVT_MOUSEDOWN)) { - ulong ticks = _EVT_getTicks(); - if ((ticks - EVT.autoTicks) >= (EVT.autoRepeat + (EVT.firstAuto ? EVT.autoDelay : 0))) { - evt->what = EVT_MOUSEAUTO; - evt->message = EVT.downMouse.message; - evt->modifiers = EVT.downMouse.modifiers; - evt->where_x = EVT.autoMouse_x; - evt->where_y = EVT.autoMouse_y; - evt->relative_x = 0; - evt->relative_y = 0; - EVT.autoTicks = evt->when = ticks; - EVT.firstAuto = false; - } - } - return evt->what != EVT_NULLEVT; -} - -/**************************************************************************** -DESCRIPTION: -Installs a user supplied event filter callback for event handling. - -HEADER: -event.h - -PARAMETERS: -userEventFilter - Address of user supplied event filter callback - -REMARKS: -This function allows the application programmer to install an event filter -callback for event handling. Once you install your callback, the MGL -event handling routines will call your callback with a pointer to the -new event that will be placed into the event queue. Your callback can the -modify the contents of the event before it is placed into the queue (for -instance adding custom information or perhaps high precision timing -information). - -If your callback returns FALSE, the event will be ignore and will not be -posted to the event queue. You should always return true from your event -callback unless you plan to use the events immediately that they are -recieved. - -Note: Your event callback may be called in response to a hardware - interrupt and will be executing in the context of the hardware - interrupt handler under MSDOS (ie: keyboard interrupt or mouse - interrupt). For this reason the code pages for the callback that - you register must be locked in memory with the PM_lockCodePages - function. You must also lock down any data pages that your function - needs to reference as well. - -Note: You can also use this filter callback to process events at the - time they are activated by the user (ie: when the user hits the - key or moves the mouse), but make sure your code runs as fast as - possible as it will be executing inside the context of an interrupt - handler on some systems. - -SEE ALSO: -EVT_getNext, EVT_peekNext -****************************************************************************/ -void EVTAPI EVT_setUserEventFilter( - _EVT_userEventFilter filter) -{ - EVT.userEventCallback = filter; -} - -/**************************************************************************** -DESCRIPTION: -Installs a user supplied event heartbeat callback function. - -HEADER: -event.h - -PARAMETERS: -callback - Address of user supplied event heartbeat callback -params - Parameters to pass to the event heartbeat function - -REMARKS: -This function allows the application programmer to install an event heatbeat -function that gets called every time that EVT_getNext or EVT_peekNext -is called. This is primarily useful for simulating text mode cursors inside -event handling code when running in graphics modes as opposed to hardware -text modes. - -SEE ALSO: -EVT_getNext, EVT_peekNext, EVT_getHeartBeatCallback -****************************************************************************/ -void EVTAPI EVT_setHeartBeatCallback( - _EVT_heartBeatCallback callback, - void *params) -{ - EVT.heartBeat = callback; - EVT.heartBeatParams = params; -} - - -/**************************************************************************** -DESCRIPTION: -Returns the current user supplied event heartbeat callback function. - -HEADER: -event.h - -PARAMETERS: -callback - Place to store the address of user supplied event heartbeat callback -params - Place to store the parameters to pass to the event heartbeat function - -REMARKS: -This function retrieves the current event heatbeat function that gets called -every time that EVT_getNext or EVT_peekNext is called. - -SEE ALSO: -EVT_getNext, EVT_peekNext, EVT_setHeartBeatCallback -****************************************************************************/ -void EVTAPI EVT_getHeartBeatCallback( - _EVT_heartBeatCallback *callback, - void **params) -{ - *callback = EVT.heartBeat; - *params = EVT.heartBeatParams; -} - -/**************************************************************************** -DESCRIPTION: -Determines if a specified key is currently down. - -PARAMETERS: -scanCode - Scan code to test - -RETURNS: -True of the specified key is currently held down. - -HEADER: -event.h - -REMARKS: -This function determines if a specified key is currently down at the -time that the call is made. You simply need to pass in the scan code of -the key that you wish to test, and the MGL will tell you if it is currently -down or not. The MGL does this by keeping track of the up and down state -of all the keys. -****************************************************************************/ -ibool EVTAPI EVT_isKeyDown( - uchar scanCode) -{ - return _EVT_isKeyDown(scanCode); -} - -/**************************************************************************** -DESCRIPTION: -Set the mouse position for the event module - -PARAMETERS: -x - X coordinate to move the mouse cursor position to -y - Y coordinate to move the mouse cursor position to - -HEADER: -event.h - -REMARKS: -This function moves the mouse cursor position for the event module to the -specified location. - -SEE ALSO: -EVT_getMousePos -****************************************************************************/ -void EVTAPI EVT_setMousePos( - int x, - int y) -{ - EVT.mx = x; - EVT.my = y; - _EVT_setMousePos(&EVT.mx,&EVT.my); - EVT.mouseMove(EVT.mx,EVT.my); -} - -/**************************************************************************** -DESCRIPTION: -Returns the current mouse cursor location. - -HEADER: -event.h - -PARAMETERS: -x - Place to store value for mouse x coordinate (screen coordinates) -y - Place to store value for mouse y coordinate (screen coordinates) - -REMARKS: -Obtains the current mouse cursor position in screen coordinates. Normally the -mouse cursor location is tracked using the mouse movement events that are -posted to the event queue when the mouse moves, however this routine -provides an alternative method of polling the mouse cursor location. - -SEE ALSO: -EVT_setMousePos -****************************************************************************/ -void EVTAPI EVT_getMousePos( - int *x, - int *y) -{ - *x = EVT.mx; - *y = EVT.my; -} - -/**************************************************************************** -DESCRIPTION: -Returns the currently active code page for translation of keyboard characters. - -HEADER: -event.h - -RETURNS: -Pointer to the currently active code page translation table. - -REMARKS: -This function is returns a pointer to the currently active code page -translation table. See EVT_setCodePage for more information. - -SEE ALSO: -EVT_setCodePage -****************************************************************************/ -codepage_t * EVTAPI EVT_getCodePage(void) -{ - return EVT.codePage; -} - -/**************************************************************************** -DESCRIPTION: -Sets the currently active code page for translation of keyboard characters. - -HEADER: -event.h - -PARAMETERS: -page - New code page to make active - -REMARKS: -This function is used to set a new code page translation table that is used -to translate virtual scan code values to ASCII characters for different -keyboard configurations. The default is usually US English, although if -possible the PM library will auto-detect the correct code page translation -for the target OS if OS services are available to determine what type of -keyboard is currently attached. - -SEE ALSO: -EVT_getCodePage -****************************************************************************/ -void EVTAPI EVT_setCodePage( - codepage_t *page) -{ - EVT.codePage = page; -} - -/* The following contains fake C prototypes and documentation for the - * macro functions in the event.h header file. These exist soley so - * that DocJet will correctly pull in the documentation for these functions. - */ -#ifdef INCLUDE_DOC_FUNCTIONS - -/**************************************************************************** -DESCRIPTION: -Macro to extract the ASCII code from a message. - -PARAMETERS: -message - Message to extract ASCII code from - -RETURNS: -ASCII code extracted from the message. - -HEADER: -event.h - -REMARKS: -Macro to extract the ASCII code from the message field of the event_t -structure. You pass the message field to the macro as the parameter and -the ASCII code is the result, for example: - - event_t EVT.myEvent; - uchar code; - code = EVT_asciiCode(EVT.myEvent.message); - -SEE ALSO: -EVT_scanCode, EVT_repeatCount -****************************************************************************/ -uchar EVT_asciiCode( - ulong message); - -/**************************************************************************** -DESCRIPTION: -Macro to extract the keyboard scan code from a message. - -HEADER: -event.h - -PARAMETERS: -message - Message to extract scan code from - -RETURNS: -Keyboard scan code extracted from the message. - -REMARKS: -Macro to extract the keyboard scan code from the message field of the event -structure. You pass the message field to the macro as the parameter and -the scan code is the result, for example: - - event_t EVT.myEvent; - uchar code; - code = EVT_scanCode(EVT.myEvent.message); - -NOTE: Scan codes in the event library are not really hardware scan codes, - but rather virtual scan codes as generated by a low level keyboard - interface driver. All virtual scan code values are defined by the - EVT_scanCodesType enumeration, and will be identical across all - supports OS'es and platforms. - -SEE ALSO: -EVT_asciiCode, EVT_repeatCount -****************************************************************************/ -uchar EVT_scanCode( - ulong message); - -/**************************************************************************** -DESCRIPTION: -Macro to extract the repeat count from a message. - -HEADER: -event.h - -PARAMETERS: -message - Message to extract repeat count from - -RETURNS: -Repeat count extracted from the message. - -REMARKS: -Macro to extract the repeat count from the message field of the event -structure. The repeat count is the number of times that the key repeated -before there was another keyboard event to be place in the queue, and -allows the event handling code to avoid keyboard buffer overflow -conditions when a single key is held down by the user. If you are processing -a key repeat code, you will probably want to check this field to see how -many key repeats you should process for this message. - -SEE ALSO: -EVT_asciiCode, EVT_repeatCount -****************************************************************************/ -short EVT_repeatCount( - ulong message); - -#endif /* DOC FUNCTIONS */ - -#if defined(__REALDOS__) || defined(__SMX32__) -/* {secret} */ -void EVTAPI _EVT_cCodeEnd(void) {} -#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c deleted file mode 100644 index e88d210..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Linux -* -* Description: Linux specific code for the CPU detection module. -* -****************************************************************************/ - -#include - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -TODO: We should implement this for Linux! -****************************************************************************/ -#define SetMaxThreadPriority() 0 - -/**************************************************************************** -REMARKS: -TODO: We should implement this for Linux! -****************************************************************************/ -#define RestoreThreadPriority(i) - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - freq->low = 1000000; - freq->high = 0; -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. -****************************************************************************/ -#define GetCounter(t) \ -{ \ - struct timeval tv; \ - gettimeofday(&tv,NULL); \ - (t)->low = tv.tv_sec*1000000 + tv.tv_usec; \ - (t)->high = 0; \ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/event.c b/board/MAI/bios_emulator/scitech/src/pm/linux/event.c deleted file mode 100644 index ce38732..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/linux/event.c +++ /dev/null @@ -1,1360 +0,0 @@ -/**************************************************************************** -* -* SciTech Multi-platform Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Linux -* -* Description: Linux fullscreen console implementation for the SciTech -* cross platform event library. -* Portions ripped straigth from the gpm source code for mouse -* handling. -* -****************************************************************************/ - -/*---------------------------- Global Variables ---------------------------*/ - -extern int _PM_console_fd; -static ushort keyUpMsg[256] = {0}; -static int _EVT_mouse_fd = 0; -static int range_x, range_y; -static int opt_baud = 1200, opt_sample = 100; -#ifdef USE_OS_JOYSTICK -static short *axis0 = NULL, *axis1 = NULL; -static uchar *buts0 = NULL, *buts1 = NULL; -static int joystick0_fd = 0, joystick1_fd = 0; -static int js_version = 0; -#endif - -/* This defines the supported mouse drivers */ - -typedef enum { - EVT_noMouse = -1, - EVT_microsoft = 0, - EVT_ps2, - EVT_mousesystems, - EVT_gpm, - EVT_MMseries, - EVT_logitech, - EVT_busmouse, - EVT_mouseman, - EVT_intellimouse, - EVT_intellimouse_ps2, - } mouse_drivers_t; - -static mouse_drivers_t mouse_driver = EVT_noMouse; -static char mouse_dev[20] = "/dev/mouse"; - -typedef struct { - char *name; - int flags; - void (*init)(void); - uchar proto[4]; - int packet_len; - int read; - } mouse_info; - -#define STD_FLG (CREAD | CLOCAL | HUPCL) - -static void _EVT_mouse_init(void); -static void _EVT_logitech_init(void); -static void _EVT_pnpmouse_init(void); - -mouse_info mouse_infos[] = { - {"Microsoft", CS7 | B1200 | STD_FLG, _EVT_mouse_init, {0x40, 0x40, 0x40, 0x00}, 3, 1}, - {"PS2", STD_FLG, NULL, {0xc0, 0x00, 0x00, 0x00}, 3, 1}, - {"MouseSystems", CS8 | CSTOPB | STD_FLG, _EVT_mouse_init, {0xf8, 0x80, 0x00, 0x00}, 5, 5}, - {"GPM", CS8 | CSTOPB | STD_FLG, NULL, {0xf8, 0x80, 0x00, 0x00}, 5, 5}, - {"MMSeries", CS8 | PARENB | PARODD | STD_FLG, _EVT_mouse_init, {0xe0, 0x80, 0x80, 0x00}, 3, 1}, - {"Logitech", CS8 | CSTOPB | STD_FLG, _EVT_logitech_init, {0xe0, 0x80, 0x80, 0x00}, 3, 3}, - {"BusMouse", STD_FLG, NULL, {0xf8, 0x80, 0x00, 0x00}, 3, 3}, - {"MouseMan", CS7 | STD_FLG, _EVT_mouse_init, {0x40, 0x40, 0x40, 0x00}, 3, 1}, - {"IntelliMouse", CS7 | STD_FLG, _EVT_pnpmouse_init, {0xc0, 0x40, 0xc0, 0x00}, 4, 1}, - {"IMPS2", CS7 | STD_FLG, NULL, {0xc0, 0x40, 0xc0, 0x00}, 4, 1}, /* ? */ - }; - -#define NB_MICE (sizeof(mouse_infos)/sizeof(mouse_info)) - -/* The name of the environment variables that are used to change the defaults above */ - -#define ENV_MOUSEDRV "MGL_MOUSEDRV" -#define ENV_MOUSEDEV "MGL_MOUSEDEV" -#define ENV_MOUSESPD "MGL_MOUSESPD" -#define ENV_JOYDEV0 "MGL_JOYDEV1" -#define ENV_JOYDEV1 "MGL_JOYDEV2" - -/* Scancode mappings on Linux for special keys */ - -typedef struct { - int scan; - int map; - } keymap; - -/* TODO: Fix this and set it up so we can do a binary search! */ - -keymap keymaps[] = { - {96, KB_padEnter}, - {74, KB_padMinus}, - {78, KB_padPlus}, - {55, KB_padTimes}, - {98, KB_padDivide}, - {71, KB_padHome}, - {72, KB_padUp}, - {73, KB_padPageUp}, - {75, KB_padLeft}, - {76, KB_padCenter}, - {77, KB_padRight}, - {79, KB_padEnd}, - {80, KB_padDown}, - {81, KB_padPageDown}, - {82, KB_padInsert}, - {83, KB_padDelete}, - {105,KB_left}, - {108,KB_down}, - {106,KB_right}, - {103,KB_up}, - {110,KB_insert}, - {102,KB_home}, - {104,KB_pageUp}, - {111,KB_delete}, - {107,KB_end}, - {109,KB_pageDown}, - {125,KB_leftWindows}, - {126,KB_rightWindows}, - {127,KB_menu}, - {100,KB_rightAlt}, - {97,KB_rightCtrl}, - }; - -/* And the keypad with num lock turned on (changes the ASCII code only) */ - -keymap keypad[] = { - {71, ASCII_7}, - {72, ASCII_8}, - {73, ASCII_9}, - {75, ASCII_4}, - {76, ASCII_5}, - {77, ASCII_6}, - {79, ASCII_1}, - {80, ASCII_2}, - {81, ASCII_3}, - {82, ASCII_0}, - {83, ASCII_period}, - }; - -#define NB_KEYMAPS (sizeof(keymaps)/sizeof(keymaps[0])) -#define NB_KEYPAD (sizeof(keypad)/sizeof(keypad[0])) - -typedef struct { - int sample; - char code[2]; - } sample_rate; - -sample_rate sampletab[]={ - { 0,"O"}, - { 15,"J"}, - { 27,"K"}, - { 42,"L"}, - { 60,"R"}, - { 85,"M"}, - {125,"Q"}, - {1E9,"N"}, - }; - -/* Number of keycodes to read at a time from the console */ - -#define KBDREADBUFFERSIZE 32 - -/*---------------------------- Implementation -----------------------------*/ - -/* These are not used under Linux */ -#define _EVT_disableInt() 1 -#define _EVT_restoreInt(flaps) - -/**************************************************************************** -PARAMETERS: -scanCode - Scan code to test - -REMARKS: -This macro determines if a specified key is currently down at the -time that the call is made. -****************************************************************************/ -#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) - -/**************************************************************************** -REMARKS: -This function is used to return the number of ticks since system -startup in milliseconds. This should be the same value that is placed into -the time stamp fields of events, and is used to implement auto mouse down -events. -****************************************************************************/ -ulong _EVT_getTicks(void) -{ - static uint starttime = 0; - struct timeval t; - - gettimeofday(&t, NULL); - if (starttime == 0) - starttime = t.tv_sec * 1000 + (t.tv_usec/1000); - return ((t.tv_sec * 1000 + (t.tv_usec/1000)) - starttime); -} - -/**************************************************************************** -REMARKS: -Small Unix function that checks for availability on a file using select() -****************************************************************************/ -static ibool dataReady( - int fd) -{ - static struct timeval t = { 0L, 0L }; - fd_set fds; - - FD_ZERO(&fds); - FD_SET(fd, &fds); - return select(fd+1, &fds, NULL, NULL, &t) > 0; -} - -/**************************************************************************** -REMARKS: -Reads mouse data according to the selected mouse driver. -****************************************************************************/ -static ibool readMouseData( - int *buttons, - int *dx, - int *dy) -{ - static uchar data[32],prev = 0; - int cnt = 0,ret; - mouse_info *drv; - - /* Read the first byte to check for the protocol */ - drv = &mouse_infos[mouse_driver]; - if (read(_EVT_mouse_fd, data, drv->read) != drv->read) { - perror("read"); - return false; - } - if ((data[0] & drv->proto[0]) != drv->proto[1]) - return false; - - /* Load a whole protocol packet */ - cnt += drv->read; - while (cnt < drv->packet_len) { - ret = read(_EVT_mouse_fd, data+cnt, drv->read); - if (ret == drv->read) - cnt += ret; - else { - perror("read"); - return false; - } - } - if ((data[1] & drv->proto[2]) != drv->proto[3]) - return false; - - /* Now decode the protocol packet */ - switch (mouse_driver) { - case EVT_microsoft: - if (data[0] == 0x40 && !(prev|data[1]|data[2])) - *buttons = 2; /* Third button on MS compatible mouse */ - else - *buttons= ((data[0] & 0x20) >> 3) | ((data[0] & 0x10) >> 4); - prev = *buttons; - *dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F)); - *dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F)); - break; - case EVT_ps2: - *buttons = !!(data[0]&1) * 4 + !!(data[0]&2) * 1 + !!(data[0]&4) * 2; - if (data[1] != 0) - *dx = (data[0] & 0x10) ? data[1]-256 : data[1]; - else - *dx = 0; - if (data[2] != 0) - *dy = -((data[0] & 0x20) ? data[2]-256 : data[2]); - else - *dy = 0; - break; - case EVT_mousesystems: case EVT_gpm: - *buttons = (~data[0]) & 0x07; - *dx = (char)(data[1]) + (char)(data[3]); - *dy = -((char)(data[2]) + (char)(data[4])); - break; - case EVT_logitech: - *buttons= data[0] & 0x07; - *dx = (data[0] & 0x10) ? data[1] : - data[1]; - *dy = (data[0] & 0x08) ? - data[2] : data[2]; - break; - case EVT_busmouse: - *buttons= (~data[0]) & 0x07; - *dx = (char)data[1]; - *dy = -(char)data[2]; - break; - case EVT_MMseries: - *buttons = data[0] & 0x07; - *dx = (data[0] & 0x10) ? data[1] : - data[1]; - *dy = (data[0] & 0x08) ? - data[2] : data[2]; - break; - case EVT_intellimouse: - *buttons = ((data[0] & 0x20) >> 3) /* left */ - | ((data[3] & 0x10) >> 3) /* middle */ - | ((data[0] & 0x10) >> 4); /* right */ - *dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F)); - *dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F)); - break; - case EVT_intellimouse_ps2: - *buttons = (data[0] & 0x04) >> 1 /* Middle */ - | (data[0] & 0x02) >> 1 /* Right */ - | (data[0] & 0x01) << 2; /* Left */ - *dx = (data[0] & 0x10) ? data[1]-256 : data[1]; - *dy = (data[0] & 0x20) ? -(data[2]-256) : -data[2]; - break; - case EVT_mouseman: { - static int getextra; - static uchar prev=0; - uchar b; - - /* The damned MouseMan has 3/4 bytes packets. The extra byte - * is only there if the middle button is active. - * I get the extra byte as a packet with magic numbers in it. - * and then switch to 4-byte mode. - */ - if (data[1] == 0xAA && data[2] == 0x55) { - /* Got unexpected fourth byte */ - if ((b = (*data>>4)) > 0x3) - return false; /* just a sanity check */ - *dx = *dy = 0; - drv->packet_len=4; - getextra=0; - } - else { - /* Got 3/4, as expected */ - /* Motion is independent of packetlen... */ - *dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F)); - *dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F)); - prev = ((data[0] & 0x20) >> 3) | ((data[0] & 0x10) >> 4); - if (drv->packet_len==4) - b = data[3]>>4; - } - if (drv->packet_len == 4) { - if (b == 0) { - drv->packet_len = 3; - getextra = 1; - } - else { - if (b & 0x2) - prev |= 2; - } - } - *buttons = prev; - - /* This "chord-middle" behaviour was reported by David A. van Leeuwen */ - if (((prev ^ *buttons) & 5) == 5) - *buttons = *buttons ? 2 : 0; - prev = *buttons; - break; - } - case EVT_noMouse: - return false; - break; - } - return true; -} - -/**************************************************************************** -REMARKS: -Map a keypress via the key mapping table -****************************************************************************/ -static int getKeyMapping( - keymap *tab, - int nb, - int key) -{ - int i; - - for(i = 0; i < nb; i++) { - if (tab[i].scan == key) - return tab[i].map; - } - return key; -} - -#ifdef USE_OS_JOYSTICK - -static char js0_axes = 0, js0_buttons = 0; -static char js1_axes = 0, js1_buttons = 0; -static char joystick0_dev[20] = "/dev/js0"; -static char joystick1_dev[20] = "/dev/js1"; - -/**************************************************************************** -REMARKS: -Create a joystick event from the joystick data -****************************************************************************/ -static void makeJoyEvent( - event_t *evt) -{ - evt->message = 0; - if (buts0 && axis0) { - if (buts0[0]) evt->message |= EVT_JOY1_BUTTONA; - if (buts0[1]) evt->message |= EVT_JOY1_BUTTONB; - evt->where_x = axis0[0]; - evt->where_y = axis0[1]; - } - else - evt->where_x = evt->where_y = 0; - if (buts1 && axis1) { - if (buts1[0]) evt->message |= EVT_JOY2_BUTTONA; - if (buts1[1]) evt->message |= EVT_JOY2_BUTTONB; - evt->where_x = axis1[0]; - evt->where_y = axis1[1]; - } - else - evt->where_x = evt->where_y = 0; -} - -/**************************************************************************** -REMARKS: -Read the joystick axis data -****************************************************************************/ -int EVTAPI _EVT_readJoyAxis( - int jmask, - int *axis) -{ - int mask = 0; - - if ((js_version & ~0xffff) == 0) { - /* Old 0.x driver */ - struct JS_DATA_TYPE js; - if (joystick0_fd && read(joystick0_fd, &js, JS_RETURN) == JS_RETURN) { - if (jmask & EVT_JOY_AXIS_X1) - axis[0] = js.x; - if (jmask & EVT_JOY_AXIS_Y1) - axis[1] = js.y; - mask |= EVT_JOY_AXIS_X1|EVT_JOY_AXIS_Y1; - } - if (joystick1_fd && read(joystick1_fd, &js, JS_RETURN) == JS_RETURN) { - if (jmask & EVT_JOY_AXIS_X2) - axis[2] = js.x; - if (jmask & EVT_JOY_AXIS_Y2) - axis[3] = js.y; - mask |= EVT_JOY_AXIS_X2|EVT_JOY_AXIS_Y2; - } - } - else { - if (axis0) { - if (jmask & EVT_JOY_AXIS_X1) - axis[0] = axis0[0]; - if (jmask & EVT_JOY_AXIS_Y1) - axis[1] = axis0[1]; - mask |= EVT_JOY_AXIS_X1 | EVT_JOY_AXIS_Y1; - } - if (axis1) { - if (jmask & EVT_JOY_AXIS_X2) - axis[2] = axis1[0]; - if (jmask & EVT_JOY_AXIS_Y2) - axis[3] = axis1[1]; - mask |= EVT_JOY_AXIS_X2 | EVT_JOY_AXIS_Y2; - } - } - return mask; -} - -/**************************************************************************** -REMARKS: -Read the joystick button data -****************************************************************************/ -int EVTAPI _EVT_readJoyButtons(void) -{ - int buts = 0; - - if ((js_version & ~0xffff) == 0) { - /* Old 0.x driver */ - struct JS_DATA_TYPE js; - if (joystick0_fd && read(joystick0_fd, &js, JS_RETURN) == JS_RETURN) - buts = js.buttons; - if (joystick1_fd && read(joystick1_fd, &js, JS_RETURN) == JS_RETURN) - buts |= js.buttons << 2; - } - else { - if (buts0) - buts |= EVT_JOY1_BUTTONA*buts0[0] + EVT_JOY1_BUTTONB*buts0[1]; - if (buts1) - buts |= EVT_JOY2_BUTTONA*buts1[0] + EVT_JOY2_BUTTONB*buts1[1]; - } - return buts; -} - -/**************************************************************************** -DESCRIPTION: -Returns the mask indicating what joystick axes are attached. - -HEADER: -event.h - -REMARKS: -This function is used to detect the attached joysticks, and determine -what axes are present and functioning. This function will re-detect any -attached joysticks when it is called, so if the user forgot to attach -the joystick when the application started, you can call this function to -re-detect any newly attached joysticks. - -SEE ALSO: -EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent -****************************************************************************/ -int EVTAPI EVT_joyIsPresent(void) -{ - static int mask = 0; - int i; - char *tmp, name0[128], name1[128]; - static ibool inited = false; - - if (inited) - return mask; - memset(EVT.joyMin,0,sizeof(EVT.joyMin)); - memset(EVT.joyCenter,0,sizeof(EVT.joyCenter)); - memset(EVT.joyMax,0,sizeof(EVT.joyMax)); - memset(EVT.joyPrev,0,sizeof(EVT.joyPrev)); - EVT.joyButState = 0; - if ((tmp = getenv(ENV_JOYDEV0)) != NULL) - strcpy(joystick0_dev,tmp); - if ((tmp = getenv(ENV_JOYDEV1)) != NULL) - strcpy(joystick1_dev,tmp); - if ((joystick0_fd = open(joystick0_dev, O_RDONLY)) < 0) - joystick0_fd = 0; - if ((joystick1_fd = open(joystick1_dev, O_RDONLY)) < 0) - joystick1_fd = 0; - if (!joystick0_fd && !joystick1_fd) /* No joysticks detected */ - return 0; - inited = true; - if (ioctl(joystick0_fd ? joystick0_fd : joystick1_fd, JSIOCGVERSION, &js_version) < 0) - return 0; - - /* Initialise joystick 0 */ - if (joystick0_fd) { - ioctl(joystick0_fd, JSIOCGNAME(sizeof(name0)), name0); - if (js_version & ~0xffff) { - struct js_event js; - - ioctl(joystick0_fd, JSIOCGAXES, &js0_axes); - ioctl(joystick0_fd, JSIOCGBUTTONS, &js0_buttons); - axis0 = PM_calloc((int)js0_axes, sizeof(short)); - buts0 = PM_malloc((int)js0_buttons); - /* Read the initial events */ - while(dataReady(joystick0_fd) - && read(joystick0_fd, &js, sizeof(struct js_event)) == sizeof(struct js_event) - && (js.type & JS_EVENT_INIT) - ) { - if (js.type & JS_EVENT_BUTTON) - buts0[js.number] = js.value; - else if (js.type & JS_EVENT_AXIS) - axis0[js.number] = scaleJoyAxis(js.value,js.number); - } - } - else { - js0_axes = 2; - js0_buttons = 2; - axis0 = PM_calloc((int)js0_axes, sizeof(short)); - buts0 = PM_malloc((int)js0_buttons); - } - } - - /* Initialise joystick 1 */ - if (joystick1_fd) { - ioctl(joystick1_fd, JSIOCGNAME(sizeof(name1)), name1); - if (js_version & ~0xffff) { - struct js_event js; - - ioctl(joystick1_fd, JSIOCGAXES, &js1_axes); - ioctl(joystick1_fd, JSIOCGBUTTONS, &js1_buttons); - axis1 = PM_calloc((int)js1_axes, sizeof(short)); - buts1 = PM_malloc((int)js1_buttons); - /* Read the initial events */ - while(dataReady(joystick1_fd) - && read(joystick1_fd, &js, sizeof(struct js_event))==sizeof(struct js_event) - && (js.type & JS_EVENT_INIT) - ) { - if (js.type & JS_EVENT_BUTTON) - buts1[js.number] = js.value; - else if (js.type & JS_EVENT_AXIS) - axis1[js.number] = scaleJoyAxis(js.value,js.number<<2); - } - } - else { - js1_axes = 2; - js1_buttons = 2; - axis1 = PM_calloc((int)js1_axes, sizeof(short)); - buts1 = PM_malloc((int)js1_buttons); - } - } - -#ifdef CHECKED - fprintf(stderr,"Using joystick driver version %d.%d.%d\n", - js_version >> 16, (js_version >> 8) & 0xff, js_version & 0xff); - if (joystick0_fd) - fprintf(stderr,"Joystick 1 (%s): %s\n", joystick0_dev, name0); - if (joystick1_fd) - fprintf(stderr,"Joystick 2 (%s): %s\n", joystick1_dev, name1); -#endif - mask = _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); - if (mask) { - for (i = 0; i < JOY_NUM_AXES; i++) - EVT.joyMax[i] = EVT.joyCenter[i]*2; - } - return mask; -} - -/**************************************************************************** -DESCRIPTION: -Polls the joystick for position and button information. - -HEADER: -event.h - -REMARKS: -This routine is used to poll analogue joysticks for button and position -information. It should be called once for each main loop of the user -application, just before processing all pending events via EVT_getNext. -All information polled from the joystick will be posted to the event -queue for later retrieval. - -Note: Most analogue joysticks will provide readings that change even - though the joystick has not moved. Hence if you call this routine - you will likely get an EVT_JOYMOVE event every time through your - event loop. - -SEE ALSO: -EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight, -EVT_joySetCenter, EVT_joyIsPresent -****************************************************************************/ -void EVTAPI EVT_pollJoystick(void) -{ - event_t evt; - int i,axis[JOY_NUM_AXES],newButState,mask,moved,ps; - - if ((js_version & ~0xFFFF) == 0 && EVT.joyMask) { - /* Read joystick axes and post movement events if they have - * changed since the last time we polled. Until the events are - * actually flushed, we keep modifying the same joystick movement - * event, so you won't get multiple movement event - */ - mask = _EVT_readJoyAxis(EVT.joyMask,axis); - newButState = _EVT_readJoyButtons(); - moved = false; - for (i = 0; i < JOY_NUM_AXES; i++) { - if (mask & (EVT_JOY_AXIS_X1 << i)) - axis[i] = scaleJoyAxis(axis[i],i); - else - axis[i] = EVT.joyPrev[i]; - if (axis[i] != EVT.joyPrev[i]) - moved = true; - } - if (moved) { - memcpy(EVT.joyPrev,axis,sizeof(EVT.joyPrev)); - ps = _EVT_disableInt(); - if (EVT.oldJoyMove != -1) { - /* Modify the existing joystick movement event */ - EVT.evtq[EVT.oldJoyMove].message = newButState; - EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; - EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; - EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; - EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; - } - else if (EVT.count < EVENTQSIZE) { - /* Add a new joystick movement event */ - EVT.oldJoyMove = EVT.freeHead; - memset(&evt,0,sizeof(evt)); - evt.what = EVT_JOYMOVE; - evt.message = EVT.joyButState; - evt.where_x = EVT.joyPrev[0]; - evt.where_y = EVT.joyPrev[1]; - evt.relative_x = EVT.joyPrev[2]; - evt.relative_y = EVT.joyPrev[3]; - addEvent(&evt); - } - _EVT_restoreInt(ps); - } - - /* Read the joystick buttons, and post events to reflect the change - * in state for the joystick buttons. - */ - if (newButState != EVT.joyButState) { - if (EVT.count < EVENTQSIZE) { - /* Add a new joystick movement event */ - ps = _EVT_disableInt(); - memset(&evt,0,sizeof(evt)); - evt.what = EVT_JOYCLICK; - evt.message = newButState; - EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; - EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; - EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; - EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; - addEvent(&evt); - _EVT_restoreInt(ps); - } - EVT.joyButState = newButState; - } - } -} - -/**************************************************************************** -DESCRIPTION: -Calibrates the joystick upper left position - -HEADER: -event.h - -REMARKS: -This function can be used to zero in on better joystick calibration factors, -which may work better than the default simplistic calibration (which assumes -the joystick is centered when the event library is initialised). -To use this function, ask the user to hold the stick in the upper left -position and then have them press a key or button. and then call this -function. This function will then read the joystick and update the -calibration factors. - -Usually, assuming that the stick was centered when the event library was -initialized, you really only need to call EVT_joySetLowerRight since the -upper left position is usually always 0,0 on most joysticks. However, the -safest procedure is to call all three calibration functions. - -SEE ALSO: -EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent -****************************************************************************/ -void EVTAPI EVT_joySetUpperLeft(void) -{ - _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMin); -} - -/**************************************************************************** -DESCRIPTION: -Calibrates the joystick lower right position - -HEADER: -event.h - -REMARKS: -This function can be used to zero in on better joystick calibration factors, -which may work better than the default simplistic calibration (which assumes -the joystick is centered when the event library is initialised). -To use this function, ask the user to hold the stick in the lower right -position and then have them press a key or button. and then call this -function. This function will then read the joystick and update the -calibration factors. - -Usually, assuming that the stick was centered when the event library was -initialized, you really only need to call EVT_joySetLowerRight since the -upper left position is usually always 0,0 on most joysticks. However, the -safest procedure is to call all three calibration functions. - -SEE ALSO: -EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent -****************************************************************************/ -void EVTAPI EVT_joySetLowerRight(void) -{ - _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMax); -} - -/**************************************************************************** -DESCRIPTION: -Calibrates the joystick center position - -HEADER: -event.h - -REMARKS: -This function can be used to zero in on better joystick calibration factors, -which may work better than the default simplistic calibration (which assumes -the joystick is centered when the event library is initialised). -To use this function, ask the user to hold the stick in the center -position and then have them press a key or button. and then call this -function. This function will then read the joystick and update the -calibration factors. - -Usually, assuming that the stick was centered when the event library was -initialized, you really only need to call EVT_joySetLowerRight since the -upper left position is usually always 0,0 on most joysticks. However, the -safest procedure is to call all three calibration functions. - -SEE ALSO: -EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter -****************************************************************************/ -void EVTAPI EVT_joySetCenter(void) -{ - _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); -} -#endif - -/**************************************************************************** -REMARKS: -Pumps all messages in the message queue from Linux into our event queue. -****************************************************************************/ -static void _EVT_pumpMessages(void) -{ - event_t evt; - int i,numkeys, c; - ibool release; - static struct kbentry ke; - static char buf[KBDREADBUFFERSIZE]; - static ushort repeatKey[128] = {0}; - - /* Poll keyboard events */ - while (dataReady(_PM_console_fd) && (numkeys = read(_PM_console_fd, buf, KBDREADBUFFERSIZE)) > 0) { - for (i = 0; i < numkeys; i++) { - c = buf[i]; - release = c & 0x80; - c &= 0x7F; - - /* TODO: This is wrong! We need this to be the time stamp at */ - /* ** interrupt ** time!! One solution would be to */ - /* put the keyboard and mouse polling loops into */ - /* a separate thread that can block on I/O to the */ - /* necessay file descriptor. */ - evt.when = _EVT_getTicks(); - - if (release) { - /* Key released */ - evt.what = EVT_KEYUP; - switch (c) { - case KB_leftShift: - _PM_modifiers &= ~EVT_LEFTSHIFT; - break; - case KB_rightShift: - _PM_modifiers &= ~EVT_RIGHTSHIFT; - break; - case 29: - _PM_modifiers &= ~(EVT_LEFTCTRL|EVT_CTRLSTATE); - break; - case 97: /* Control */ - _PM_modifiers &= ~EVT_CTRLSTATE; - break; - case 56: - _PM_modifiers &= ~(EVT_LEFTALT|EVT_ALTSTATE); - break; - case 100: - _PM_modifiers &= ~EVT_ALTSTATE; - break; - default: - } - evt.modifiers = _PM_modifiers; - evt.message = keyUpMsg[c]; - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - keyUpMsg[c] = 0; - repeatKey[c] = 0; - } - else { - /* Key pressed */ - evt.what = EVT_KEYDOWN; - switch (c) { - case KB_leftShift: - _PM_modifiers |= EVT_LEFTSHIFT; - break; - case KB_rightShift: - _PM_modifiers |= EVT_RIGHTSHIFT; - break; - case 29: - _PM_modifiers |= EVT_LEFTCTRL|EVT_CTRLSTATE; - break; - case 97: /* Control */ - _PM_modifiers |= EVT_CTRLSTATE; - break; - case 56: - _PM_modifiers |= EVT_LEFTALT|EVT_ALTSTATE; - break; - case 100: - _PM_modifiers |= EVT_ALTSTATE; - break; - case KB_capsLock: /* Caps Lock */ - _PM_leds ^= LED_CAP; - ioctl(_PM_console_fd, KDSETLED, _PM_leds); - break; - case KB_numLock: /* Num Lock */ - _PM_leds ^= LED_NUM; - ioctl(_PM_console_fd, KDSETLED, _PM_leds); - break; - case KB_scrollLock: /* Scroll Lock */ - _PM_leds ^= LED_SCR; - ioctl(_PM_console_fd, KDSETLED, _PM_leds); - break; - default: - } - evt.modifiers = _PM_modifiers; - if (keyUpMsg[c]) { - evt.what = EVT_KEYREPEAT; - evt.message = keyUpMsg[c] | (repeatKey[c]++ << 16); - } - else { - int asc; - - evt.message = getKeyMapping(keymaps, NB_KEYMAPS, c) << 8; - ke.kb_index = c; - ke.kb_table = 0; - if ((_PM_modifiers & EVT_SHIFTKEY) || (_PM_leds & LED_CAP)) - ke.kb_table |= K_SHIFTTAB; - if (_PM_modifiers & (EVT_LEFTALT | EVT_ALTSTATE)) - ke.kb_table |= K_ALTTAB; - if (ioctl(_PM_console_fd, KDGKBENT, (unsigned long)&ke)<0) - perror("ioctl(KDGKBENT)"); - if ((_PM_leds & LED_NUM) && (getKeyMapping(keypad, NB_KEYPAD, c)!=c)) { - asc = getKeyMapping(keypad, NB_KEYPAD, c); - } - else { - switch (c) { - case 14: - asc = ASCII_backspace; - break; - case 15: - asc = ASCII_tab; - break; - case 28: - case 96: - asc = ASCII_enter; - break; - case 1: - asc = ASCII_esc; - default: - asc = ke.kb_value & 0xFF; - if (asc < 0x1B) - asc = 0; - break; - } - } - if ((_PM_modifiers & (EVT_CTRLSTATE|EVT_LEFTCTRL)) && isalpha(asc)) - evt.message |= toupper(asc) - 'A' + 1; - else - evt.message |= asc; - keyUpMsg[c] = evt.message; - repeatKey[c]++; - } - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - } - } - - /* Poll mouse events */ - if (_EVT_mouse_fd) { - int dx, dy, buts; - static int oldbuts; - - while (dataReady(_EVT_mouse_fd)) { - if (readMouseData(&buts, &dx, &dy)) { - EVT.mx += dx; - EVT.my += dy; - if (EVT.mx < 0) EVT.mx = 0; - if (EVT.my < 0) EVT.my = 0; - if (EVT.mx > range_x) EVT.mx = range_x; - if (EVT.my > range_y) EVT.my = range_y; - evt.where_x = EVT.mx; - evt.where_y = EVT.my; - evt.relative_x = dx; - evt.relative_y = dy; - - /* TODO: This is wrong! We need this to be the time stamp at */ - /* ** interrupt ** time!! One solution would be to */ - /* put the keyboard and mouse polling loops into */ - /* a separate thread that can block on I/O to the */ - /* necessay file descriptor. */ - evt.when = _EVT_getTicks(); - evt.modifiers = _PM_modifiers; - if (buts & 4) - evt.modifiers |= EVT_LEFTBUT; - if (buts & 1) - evt.modifiers |= EVT_RIGHTBUT; - if (buts & 2) - evt.modifiers |= EVT_MIDDLEBUT; - - /* Left click events */ - if ((buts&4) != (oldbuts&4)) { - if (buts&4) - evt.what = EVT_MOUSEDOWN; - else - evt.what = EVT_MOUSEUP; - evt.message = EVT_LEFTBMASK; - EVT.oldMove = -1; - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - - /* Right click events */ - if ((buts&1) != (oldbuts&1)) { - if (buts&1) - evt.what = EVT_MOUSEDOWN; - else - evt.what = EVT_MOUSEUP; - evt.message = EVT_RIGHTBMASK; - EVT.oldMove = -1; - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - - /* Middle click events */ - if ((buts&2) != (oldbuts&2)) { - if (buts&2) - evt.what = EVT_MOUSEDOWN; - else - evt.what = EVT_MOUSEUP; - evt.message = EVT_MIDDLEBMASK; - EVT.oldMove = -1; - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - - /* Mouse movement event */ - if (dx || dy) { - evt.what = EVT_MOUSEMOVE; - evt.message = 0; - if (EVT.oldMove != -1) { - /* Modify existing movement event */ - EVT.evtq[EVT.oldMove].where_x = evt.where_x; - EVT.evtq[EVT.oldMove].where_y = evt.where_y; - } - else { - /* Save id of this movement event */ - EVT.oldMove = EVT.freeHead; - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - } - oldbuts = buts; - } - } - } - -#ifdef USE_OS_JOYSTICK - /* Poll joystick events using the 1.x joystick driver API in the 2.2 kernels */ - if (js_version & ~0xffff) { - static struct js_event js; - - /* Read joystick axis 0 */ - evt.when = 0; - evt.modifiers = _PM_modifiers; - if (joystick0_fd && dataReady(joystick0_fd) && - read(joystick0_fd, &js, sizeof(js)) == sizeof(js)) { - if (js.type & JS_EVENT_BUTTON) { - if (js.number < 2) { /* Only 2 buttons for now :( */ - buts0[js.number] = js.value; - evt.what = EVT_JOYCLICK; - makeJoyEvent(&evt); - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - } - else if (js.type & JS_EVENT_AXIS) { - axis0[js.number] = scaleJoyAxis(js.value,js.number); - evt.what = EVT_JOYMOVE; - if (EVT.oldJoyMove != -1) { - makeJoyEvent(&EVT.evtq[EVT.oldJoyMove]); - } - else if (EVT.count < EVENTQSIZE) { - EVT.oldJoyMove = EVT.freeHead; - makeJoyEvent(&evt); - addEvent(&evt); - } - } - } - - /* Read joystick axis 1 */ - if (joystick1_fd && dataReady(joystick1_fd) && - read(joystick1_fd, &js, sizeof(js))==sizeof(js)) { - if (js.type & JS_EVENT_BUTTON) { - if (js.number < 2) { /* Only 2 buttons for now :( */ - buts1[js.number] = js.value; - evt.what = EVT_JOYCLICK; - makeJoyEvent(&evt); - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - } - else if (js.type & JS_EVENT_AXIS) { - axis1[js.number] = scaleJoyAxis(js.value,js.number<<2); - evt.what = EVT_JOYMOVE; - if (EVT.oldJoyMove != -1) { - makeJoyEvent(&EVT.evtq[EVT.oldJoyMove]); - } - else if (EVT.count < EVENTQSIZE) { - EVT.oldJoyMove = EVT.freeHead; - makeJoyEvent(&evt); - addEvent(&evt); - } - } - } - } -#endif -} - -/**************************************************************************** -REMARKS: -This macro/function is used to converts the scan codes reported by the -keyboard to our event libraries normalised format. We only have one scan -code for the 'A' key, and use shift _PM_modifiers to determine if it is a -Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, -but the OS gives us 'cooked' scan codes, we have to translate them back -to the raw format. -****************************************************************************/ -#define _EVT_maskKeyCode(evt) - -/**************************************************************************** -REMARKS: -Set the speed of the serial port -****************************************************************************/ -static int setspeed( - int fd, - int old, - int new, - unsigned short flags) -{ - struct termios tty; - char *c; - - tcgetattr(fd, &tty); - tty.c_iflag = IGNBRK | IGNPAR; - tty.c_oflag = 0; - tty.c_lflag = 0; - tty.c_line = 0; - tty.c_cc[VTIME] = 0; - tty.c_cc[VMIN] = 1; - switch (old) { - case 9600: tty.c_cflag = flags | B9600; break; - case 4800: tty.c_cflag = flags | B4800; break; - case 2400: tty.c_cflag = flags | B2400; break; - case 1200: - default: tty.c_cflag = flags | B1200; break; - } - tcsetattr(fd, TCSAFLUSH, &tty); - switch (new) { - case 9600: c = "*q"; tty.c_cflag = flags | B9600; break; - case 4800: c = "*p"; tty.c_cflag = flags | B4800; break; - case 2400: c = "*o"; tty.c_cflag = flags | B2400; break; - case 1200: - default: c = "*n"; tty.c_cflag = flags | B1200; break; - } - write(fd, c, 2); - usleep(100000); - tcsetattr(fd, TCSAFLUSH, &tty); - return 0; -} - -/**************************************************************************** -REMARKS: -Generic mouse driver init code -****************************************************************************/ -static void _EVT_mouse_init(void) -{ - int i; - - /* Change from any available speed to the chosen one */ - for (i = 9600; i >= 1200; i /= 2) - setspeed(_EVT_mouse_fd, i, opt_baud, mouse_infos[mouse_driver].flags); -} - -/**************************************************************************** -REMARKS: -Logitech mouse driver init code -****************************************************************************/ -static void _EVT_logitech_init(void) -{ - int i; - struct stat buf; - int busmouse; - - /* is this a serial- or a bus- mouse? */ - if (fstat(_EVT_mouse_fd,&buf) == -1) - perror("fstat"); - i = MAJOR(buf.st_rdev); - if (stat("/dev/ttyS0",&buf) == -1) - perror("stat"); - busmouse=(i != MAJOR(buf.st_rdev)); - - /* Fix the howmany field, so that serial mice have 1, while busmice have 3 */ - mouse_infos[mouse_driver].read = busmouse ? 3 : 1; - - /* Change from any available speed to the chosen one */ - for (i = 9600; i >= 1200; i /= 2) - setspeed(_EVT_mouse_fd, i, opt_baud, mouse_infos[mouse_driver].flags); - - /* This stuff is peculiar of logitech mice, also for the serial ones */ - write(_EVT_mouse_fd, "S", 1); - setspeed(_EVT_mouse_fd, opt_baud, opt_baud,CS8 |PARENB |PARODD |CREAD |CLOCAL |HUPCL); - - /* Configure the sample rate */ - for (i = 0; opt_sample <= sampletab[i].sample; i++) - ; - write(_EVT_mouse_fd,sampletab[i].code,1); -} - -/**************************************************************************** -REMARKS: -Microsoft Intellimouse init code -****************************************************************************/ -static void _EVT_pnpmouse_init(void) -{ - struct termios tty; - - tcgetattr(_EVT_mouse_fd, &tty); - tty.c_iflag = IGNBRK | IGNPAR; - tty.c_oflag = 0; - tty.c_lflag = 0; - tty.c_line = 0; - tty.c_cc[VTIME] = 0; - tty.c_cc[VMIN] = 1; - tty.c_cflag = mouse_infos[mouse_driver].flags | B1200; - tcsetattr(_EVT_mouse_fd, TCSAFLUSH, &tty); /* set parameters */ -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -void EVTAPI EVT_init( - _EVT_mouseMoveHandler mouseMove) -{ - int i; - char *tmp; - - /* Initialise the event queue */ - EVT.mouseMove = mouseMove; - initEventQueue(); - for (i = 0; i < 256; i++) - keyUpMsg[i] = 0; - - /* Keyboard initialization */ - if (_PM_console_fd == -1) - PM_fatalError("You must first call PM_openConsole to use the EVT functions!"); - _PM_keyboard_rawmode(); - fcntl(_PM_console_fd,F_SETFL,fcntl(_PM_console_fd,F_GETFL) | O_NONBLOCK); - - /* Mouse initialization */ - if ((tmp = getenv(ENV_MOUSEDRV)) != NULL) { - for (i = 0; i < NB_MICE; i++) { - if (!strcasecmp(tmp, mouse_infos[i].name)) { - mouse_driver = i; - break; - } - } - if (i == NB_MICE) { - fprintf(stderr,"Unknown mouse driver: %s\n", tmp); - mouse_driver = EVT_noMouse; - _EVT_mouse_fd = 0; - } - } - if (mouse_driver != EVT_noMouse) { - if (mouse_driver == EVT_gpm) - strcpy(mouse_dev,"/dev/gpmdata"); - if ((tmp = getenv(ENV_MOUSEDEV)) != NULL) - strcpy(mouse_dev,tmp); -#ifdef CHECKED - fprintf(stderr,"Using the %s MGL mouse driver on %s.\n", mouse_infos[mouse_driver].name, mouse_dev); -#endif - if ((_EVT_mouse_fd = open(mouse_dev, O_RDWR)) < 0) { - perror("open"); - fprintf(stderr, "Unable to open mouse device %s, dropping mouse support.\n", mouse_dev); - sleep(1); - mouse_driver = EVT_noMouse; - _EVT_mouse_fd = 0; - } - else { - char c; - - /* Init and flush the mouse pending input queue */ - if (mouse_infos[mouse_driver].init) - mouse_infos[mouse_driver].init(); - while(dataReady(_EVT_mouse_fd) && read(_EVT_mouse_fd, &c, 1) == 1) - ; - } - } -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - range_x = xRes; - range_y = yRes; -} - -/**************************************************************************** -REMARKS -Modifes the mouse coordinates as necessary if scaling to OS coordinates, -and sets the OS mouse cursor position. -****************************************************************************/ -#define _EVT_setMousePos(x,y) - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVT_resume(void) -{ - /* Do nothing for Linux */ -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVT_suspend(void) -{ - /* Do nothing for Linux */ -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVT_exit(void) -{ - /* Restore signal handlers */ - _PM_restore_kb_mode(); - if (_EVT_mouse_fd) { - close(_EVT_mouse_fd); - _EVT_mouse_fd = 0; - } -#ifdef USE_OS_JOYSTICK - if (joystick0_fd) { - close(joystick0_fd); - free(axis0); - free(buts0); - joystick0_fd = 0; - } - if (joystick1_fd) { - close(joystick1_fd); - free(axis1); - free(buts1); - joystick1_fd = 0; - } -#endif -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga b/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga deleted file mode 100644 index c0358a0..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga +++ /dev/null @@ -1,1058 +0,0 @@ -/**************************************************************************** -* -* The SuperVGA Kit - UniVBE Software Development Kit -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: IBM PC (MS DOS) -* -* Description: Routines to provide a Linux event queue, which automatically -* handles keyboard and mouse events for the Linux compatability -* libraries. Based on the event handling code in the MGL. -* -****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "pm.h" -#include "vesavbe.h" -#include "wdirect.h" - -/*--------------------------- Global variables ----------------------------*/ - -#define EVENTQSIZE 100 /* Number of events in event queue */ - -static int head = -1; /* Head of event queue */ -static int tail = -1; /* Tail of event queue */ -static int freeHead = -1; /* Head of free list */ -static int count = 0; /* No. of items currently in queue */ -static WD_event evtq[EVENTQSIZE]; /* The queue structure itself */ -static int oldMove = -1; /* Previous movement event */ -static int oldKey = -1; /* Previous key repeat event */ -static int mx,my; /* Current mouse position */ -static int xRes,yRes; /* Screen resolution coordinates */ -static void *stateBuf; /* Pointer to console state buffer */ -static int conn; /* GPM file descriptor for mouse handling */ -static int tty_fd; /* File descriptor for /dev/console */ -extern int tty_vc; /* Virtual console ID, from the PM/Pro library */ -static ibool key_down[128]; /* State of all keyboard keys */ -static struct termios old_conf; /* Saved terminal configuration */ -static int oldkbmode; /* and previous keyboard mode */ -struct vt_mode oldvtmode; /* Old virtual terminal mode */ -static int old_flags; /* Old flags for fcntl */ -static ulong key_modifiers; /* Keyboard modifiers */ -static int forbid_vt_release=0;/* Flag to forbid release of VT */ -static int forbid_vt_acquire=0;/* Flag to forbid cature of VT */ -static int oldmode; /* Old SVGA mode saved for VT switch*/ -static int initmode; /* Initial text mode */ -static ibool installed = false; /* True if we are installed */ -static void (_ASMAPI *moveCursor)(int x,int y) = NULL; -static int (_ASMAPI *suspendAppCallback)(int flags) = NULL; - -#if 0 -/* Keyboard Translation table from scancodes to ASCII */ - -static uchar keyTable[128] = -"\0\0331234567890-=\010" -"\011qwertyuiop[]\015" -"\0asdfghjkl;'`\0\\" -"zxcvbnm,./\0*\0 \0" -"\0\0\0\0\0\0\0\0\0\0\0\0" /* Function keys */ -"789-456+1230.\0\0\0\0\0" /* Keypad keys */ -"\0\0\0\0\0\0\0\015\0/"; - -static uchar keyTableShifted[128] = -"\0\033!@#$%^&*()_+\010" -"\011QWERTYUIOP{}\015" -"\0ASDFGHJKL:\"~\0|" -"ZXCVBNM<>?\0*\0 \0" -"\0\0\0\0\0\0\0\0\0\0\0\0" /* Function keys */ -"789-456+1230.\0\0\0\0\0" /* Keypad keys */ -"\0\0\0\0\0\0\0\015\0/"; -#endif - -/* Macros to keep track of the CAPS and NUM lock states */ - -#define EVT_CAPSSTATE 0x0100 -#define EVT_NUMSTATE 0x0200 - -/* Helper macros for dealing with timers */ - -#define TICKS_TO_USEC(t) ((t)*65536.0/1.193180) -#define USEC_TO_TICKS(u) ((u)*1.193180/65536.0) - -/* Number of keycodes to read at a time from the console */ - -#define KBDREADBUFFERSIZE 32 - -/*---------------------------- Implementation -----------------------------*/ - -/**************************************************************************** -REMARKS: -Returns the current time stamp in units of 18.2 ticks per second. -****************************************************************************/ -static ulong getTimeStamp(void) -{ - return (ulong)(clock() / (CLOCKS_PER_SEC / 18.2)); -} - -/**************************************************************************** -PARAMETERS: -evt - Event to place onto event queue - -REMARKS: -Adds an event to the event queue by tacking it onto the tail of the event -queue. This routine assumes that at least one spot is available on the -freeList for the event to be inserted. -****************************************************************************/ -static void addEvent( - WD_event *evt) -{ - int evtID; - - /* Get spot to place the event from the free list */ - evtID = freeHead; - freeHead = evtq[freeHead].next; - - /* Add to the tail of the event queue */ - evt->next = -1; - evt->prev = tail; - if (tail != -1) - evtq[tail].next = evtID; - else - head = evtID; - tail = evtID; - evtq[evtID] = *evt; - count++; -} - -/**************************************************************************** -PARAMETERS: -what - Event code -message - Event message -modifiers - keyboard modifiers -x - Mouse X position at time of event -y - Mouse Y position at time of event -but_stat - Mouse button status at time of event - -REMARKS: -Adds a new mouse event to the event queue. This routine is called from -within the mouse interrupt subroutine, so it must be efficient. -****************************************************************************/ -static void addMouseEvent( - uint what, - uint message, - int x, - int y, - uint but_stat) -{ - WD_event evt; - - if (count < EVENTQSIZE) { - evt.what = what; - evt.when = getTimeStamp(); - evt.message = message; - evt.modifiers = but_stat | key_modifiers; - evt.where_x = x; - evt.where_y = y; - fprintf(stderr, "(%d,%d), buttons %ld\n", x,y, evt.modifiers); - addEvent(&evt); /* Add to tail of event queue */ - } -} - -/**************************************************************************** -PARAMETERS: -scancode - Raw keyboard scan code -modifiers - Keyboard modifiers flags - -REMARKS: -Converts the raw scan code into the appropriate ASCII code using the scan -code and the keyboard modifier flags. -****************************************************************************/ -static ulong getKeyMessage( - uint scancode, - ulong modifiers) -{ - ushort code = scancode << 8; - ushort ascii; - struct kbentry ke; - - ke.kb_index = scancode; - - /* Find the basic ASCII code for the scan code */ - if (modifiers & EVT_CAPSSTATE) { - if (modifiers & EVT_SHIFTKEY) - ke.kb_table = K_NORMTAB; - // ascii = tolower(keyTableShifted[scancode]); - else - ke.kb_table = K_SHIFTTAB; - // ascii = toupper(keyTable[scancode]); - } - else { - if (modifiers & EVT_SHIFTKEY) - ke.kb_table = K_SHIFTTAB; - // ascii = keyTableShifted[scancode]; - else - ke.kb_table = K_NORMTAB; - // ascii = keyTable[scancode]; - } - if(modifiers & EVT_ALTSTATE) - ke.kb_table |= K_ALTTAB; - - if (ioctl(tty_fd, KDGKBENT, (unsigned long)&ke)) { - fprintf(stderr, "KDGKBENT at index %d in table %d: ", - scancode, ke.kb_table); - return 0; - } - ascii = ke.kb_value; - - /* Add ASCII code if key is not alt'ed or ctrl'ed */ - if (!(modifiers & (EVT_ALTSTATE | EVT_CTRLSTATE))) - code |= ascii; - - return code; -} - -/**************************************************************************** -PARAMETERS: -what - Event code -scancode - Raw scancode of keyboard event to add - -REMARKS: -Adds a new keyboard event to the event queue. We only take KEYUP and -KEYDOWN event codes, however if a key is already down we convert the KEYDOWN -to a KEYREPEAT. -****************************************************************************/ -static void addKeyEvent( - uint what, - uint scancode) -{ - WD_event evt; - - if (count < EVENTQSIZE) { - evt.what = what; - evt.when = getTimeStamp(); - evt.message = getKeyMessage(scancode,key_modifiers) | 0x10000UL; - evt.where_x = evt.where_y = 0; - evt.modifiers = key_modifiers; - if (evt.what == EVT_KEYUP) - key_down[scancode] = false; - else if (evt.what == EVT_KEYDOWN) { - if (key_down[scancode]) { - if (oldKey != -1) { - evtq[oldKey].message += 0x10000UL; - } - else { - evt.what = EVT_KEYREPEAT; - oldKey = freeHead; - addEvent(&evt); - oldMove = -1; - } - return; - } - key_down[scancode] = true; - } - - addEvent(&evt); - oldMove = -1; - } -} - -/**************************************************************************** -PARAMETERS: -sig - Signal being sent to this signal handler - -REMARKS: -Signal handler for the timer. This routine takes care of periodically -posting timer events to the event queue. -****************************************************************************/ -void timerHandler( - int sig) -{ - WD_event evt; - - if (sig == SIGALRM) { - if (count < EVENTQSIZE) { - evt.when = getTimeStamp(); - evt.what = EVT_TIMERTICK; - evt.message = 0; - evt.where_x = evt.where_y = 0; - evt.modifiers = 0; - addEvent(&evt); - oldMove = -1; - oldKey = -1; - } - signal(SIGALRM, timerHandler); - } -} - -/**************************************************************************** -REMARKS: -Restore the terminal to normal operation on exit -****************************************************************************/ -static void restore_term(void) -{ - RMREGS regs; - - if (installed) { - /* Restore text mode and the state of the console */ - regs.x.ax = 0x3; - PM_int86(0x10,®s,®s); - PM_restoreConsoleState(stateBuf,tty_fd); - - /* Restore console to normal operation */ - ioctl(tty_fd, VT_SETMODE, &oldvtmode); - ioctl(tty_fd, KDSKBMODE, oldkbmode); - tcsetattr(tty_fd, TCSAFLUSH, &old_conf); - fcntl(tty_fd,F_SETFL,old_flags &= ~O_NONBLOCK); - PM_closeConsole(tty_fd); - - /* Close the mouse driver */ - close(conn); - - /* Flag that we are not no longer installed */ - installed = false; - } -} - -/**************************************************************************** -REMARKS: -Signal handler to capture forced program termination conditions so that -we can clean up properly. -****************************************************************************/ -static void exitHandler(int sig) -{ - exit(-1); -} - -/**************************************************************************** -REMARKS: -Sleep until the virtual terminal is active -****************************************************************************/ -void wait_vt_active(void) -{ - while (ioctl(tty_fd, VT_WAITACTIVE, tty_vc) < 0) { - if ((errno != EAGAIN) && (errno != EINTR)) { - perror("ioctl(VT_WAITACTIVE)"); - exit(1); - } - usleep(150000); - } -} - -/**************************************************************************** -REMARKS: -Signal handler called when our virtual terminal has been released and we are -losing the active focus. -****************************************************************************/ -static void release_vt_signal(int n) -{ - forbid_vt_acquire = 1; - if (forbid_vt_release) { - forbid_vt_acquire = 0; - ioctl(tty_fd, VT_RELDISP, 0); - return; - } - - // TODO: Call the user supplied suspendAppCallback and restore text - // mode (saving the existing mode so we can restore it). - // - // Also if the suspendAppCallback is NULL then we have to - // ignore the switch request! - if(suspendAppCallback){ - oldmode = VBE_getVideoMode(); - suspendAppCallback(true); - VBE_setVideoMode(initmode); - } - - ioctl(tty_fd, VT_RELDISP, 1); - forbid_vt_acquire = 0; - wait_vt_active(); -} - -/**************************************************************************** -REMARKS: -Signal handler called when our virtual terminal has been re-aquired and we -are now regaiing the active focus. -****************************************************************************/ -static void acquire_vt_signal(int n) -{ - forbid_vt_release = 1; - if (forbid_vt_acquire) { - forbid_vt_release = 0; - return; - } - - // TODO: Restore the old display mode, call the user suspendAppCallback - // and and we will be back in graphics mode. - - if(suspendAppCallback){ - VBE_setVideoMode(oldmode); - suspendAppCallback(false); - } - - ioctl(tty_fd, VT_RELDISP, VT_ACKACQ); - forbid_vt_release = 0; -} - -/**************************************************************************** -REMARKS: -Function to set the action for a specific signal to call our signal handler. -****************************************************************************/ -static void set_sigaction(int sig,void (*handler)(int)) -{ - struct sigaction siga; - - siga.sa_handler = handler; - siga.sa_flags = SA_RESTART; - memset(&(siga.sa_mask), 0, sizeof(sigset_t)); - sigaction(sig, &siga, NULL); -} - -/**************************************************************************** -REMARKS: -Function to take over control of VT switching so that we can capture -virtual terminal release and aquire signals, allowing us to properly -support VT switching while in graphics modes. -****************************************************************************/ -static void take_vt_control(void) -{ - struct vt_mode vtmode; - - ioctl(tty_fd, VT_GETMODE, &vtmode); - oldvtmode = vtmode; - vtmode.mode = VT_PROCESS; - vtmode.relsig = SIGUSR1; - vtmode.acqsig = SIGUSR2; - set_sigaction(SIGUSR1, release_vt_signal); - set_sigaction(SIGUSR2, acquire_vt_signal); - ioctl(tty_fd, VT_SETMODE, &oldvtmode); -} - -/**************************************************************************** -REMARKS: -Set the shift keyboard LED's based on the current keyboard modifiers flags. -****************************************************************************/ -static void updateLEDStatus(void) -{ - int state = 0; - if (key_modifiers & EVT_CAPSSTATE) - state |= LED_CAP; - if (key_modifiers & EVT_NUMSTATE) - state |= LED_NUM; - ioctl(tty_fd,KDSETLED,state); -} - -/**************************************************************************** -PARAMETERS: -scancode - Raw scan code to handle - -REMARKS: -Handles the shift key modifiers and keeps track of the shift key states -so that we can return the correct ASCII codes for the keyboard. -****************************************************************************/ -static void toggleModifiers( - int scancode) -{ - static int caps_down = 0,num_down = 0; - - if (scancode & 0x80) { - /* Handle key-release function */ - scancode &= 0x7F; - if (scancode == 0x2A || scancode == 0x36) - key_modifiers &= ~EVT_SHIFTKEY; - else if (scancode == 0x1D || scancode == 0x61) - key_modifiers &= ~EVT_CTRLSTATE; - else if (scancode == 0x38 || scancode == 0x64) - key_modifiers &= ~EVT_ALTSTATE; - else if (scancode == 0x3A) - caps_down = false; - else if (scancode == 0x45) - num_down = false; - } - else { - /* Handle key-down function */ - scancode &= 0x7F; - if (scancode == 0x2A || scancode == 0x36) - key_modifiers |= EVT_SHIFTKEY; - else if (scancode == 0x1D || scancode == 0x61) - key_modifiers |= EVT_CTRLSTATE; - else if (scancode == 0x38 || scancode == 0x64) - key_modifiers |= EVT_ALTSTATE; - else if (scancode == 0x3A) { - if (!caps_down) { - key_modifiers ^= EVT_CAPSSTATE; - updateLEDStatus(); - } - caps_down = true; - } - else if (scancode == 0x45) { - if (!num_down) { - key_modifiers ^= EVT_NUMSTATE; - updateLEDStatus(); - } - num_down = true; - } - } -} - -/*************************************************************************** -REMARKS: -Returns the number of bits that have changed from 0 to 1 -(a negative value means the number of bits that have changed from 1 to 0) - **************************************************************************/ -static int compareBits(short a, short b) -{ - int ret = 0; - if( (a&1) != (b&1) ) ret += (b&1) ? 1 : -1; - if( (a&2) != (b&2) ) ret += (b&2) ? 1 : -1; - if( (a&4) != (b&4) ) ret += (b&4) ? 1 : -1; - return ret; -} - -/*************************************************************************** -REMARKS: -Turns off all keyboard state because we can't rely on them anymore as soon -as we switch VT's -***************************************************************************/ -static void keyboard_clearstate(void) -{ - key_modifiers = 0; - memset(key_down, 0, sizeof(key_down)); -} - -/**************************************************************************** -REMARKS: -Pumps all events from the console event queue into the WinDirect event queue. -****************************************************************************/ -static void pumpEvents(void) -{ - static uchar buf[KBDREADBUFFERSIZE]; - static char data[5]; - static int old_buts, old_mx, old_my; - static struct timeval t; - fd_set fds; - int numkeys,i; - int dx, dy, buts; - - /* Read all pending keypresses from keyboard buffer and process */ - while ((numkeys = read(tty_fd, buf, KBDREADBUFFERSIZE)) > 0) { - for (i = 0; i < numkeys; i++) { - toggleModifiers(buf[i]); - if (key_modifiers & EVT_ALTSTATE){ - int fkey = 0; - - // Do VT switching here for Alt+Fx keypresses - switch(buf[i] & 0x7F){ - case 59 ... 68: /* F1 to F10 */ - fkey = (buf[i] & 0x7F) - 58; - break; - case 87: /* F11 */ - case 88: /* F12 */ - fkey = (buf[i] & 0x7F) - 76; - break; - } - if(fkey){ - struct vt_stat vts; - ioctl(tty_fd, VT_GETSTATE, &vts); - - if(fkey != vts.v_active){ - keyboard_clearstate(); - ioctl(tty_fd, VT_ACTIVATE, fkey); - } - } - } - - if (buf[i] & 0x80) - addKeyEvent(EVT_KEYUP,buf[i] & 0x7F); - else - addKeyEvent(EVT_KEYDOWN,buf[i] & 0x7F); - } - - // TODO: If we want to handle VC switching we will need to do it - // in here so that we can switch away from the VC and then - // switch back to it later. Right now VC switching is disabled - // and in order to enable it we need to save/restore the state - // of the graphics screen (using the suspendAppCallback and - // saving/restoring the state of the current display mode). - - } - - /* Read all pending mouse events and process them */ - if(conn > 0){ - FD_ZERO(&fds); - FD_SET(conn, &fds); - t.tv_sec = t.tv_usec = 0L; - while (select(conn+1, &fds, NULL, NULL, &t) > 0) { - if(read(conn, data, 5) == 5){ - buts = (~data[0]) & 0x07; - dx = (char)(data[1]) + (char)(data[3]); - dy = -((char)(data[2]) + (char)(data[4])); - - mx += dx; my += dy; - - if (dx || dy) - addMouseEvent(EVT_MOUSEMOVE, 0, mx, my, buts); - - if (buts != old_buts){ - int c = compareBits(buts,old_buts); - if(c>0) - addMouseEvent(EVT_MOUSEDOWN, 0, mx, my, buts); - else if(c<0) - addMouseEvent(EVT_MOUSEUP, 0, mx, my, buts); - } - old_mx = mx; old_my = my; - old_buts = buts; - FD_SET(conn, &fds); - t.tv_sec = t.tv_usec = 0L; - } - } - } -} - -/*------------------------ Public interface routines ----------------------*/ - -/**************************************************************************** -PARAMETERS: -which - Which code for event to post -what - Event code for event to post -message - Event message -modifiers - Shift key/mouse button modifiers - -RETURNS: -True if the event was posted, false if queue is full. - -REMARKS: -Posts an event to the event queue. This routine can be used to post any type -of event into the queue. -****************************************************************************/ -ibool _WDAPI WD_postEvent( - ulong which, - uint what, - ulong message, - ulong modifiers) -{ - WD_event evt; - - if (count < EVENTQSIZE) { - /* Save information in event record */ - evt.which = which; - evt.what = what; - evt.when = getTimeStamp(); - evt.message = message; - evt.modifiers = modifiers; - addEvent(&evt); /* Add to tail of event queue */ - return true; - } - else - return false; -} - -/**************************************************************************** -PARAMETERS: -mask - Event mask to use - -REMARKS: -Flushes all the event specified in 'mask' from the event queue. -****************************************************************************/ -void _WDAPI WD_flushEvent( - uint mask) -{ - WD_event evt; - - do { /* Flush all events */ - WD_getEvent(&evt,mask); - } while (evt.what != EVT_NULLEVT); -} - -/**************************************************************************** -PARAMETERS: -evt - Place to store event -mask - Event mask to use - -REMARKS: -Halts program execution until a specified event occurs. The event is -returned. All pending events not in the specified mask will be ignored and -removed from the queue. -****************************************************************************/ -void _WDAPI WD_haltEvent( - WD_event *evt, - uint mask) -{ - do { /* Wait for an event */ - WD_getEvent(evt,EVT_EVERYEVT); - } while (!(evt->what & mask)); -} - -/**************************************************************************** -PARAMETERS: -evt - Place to store event -mask - Event mask to use - -RETURNS: -True if an event was pending. - -REMARKS: -Retrieves the next pending event defined in 'mask' from the event queue. -The event queue is adjusted to reflect the new state after the event has -been removed. -****************************************************************************/ -ibool _WDAPI WD_getEvent( - WD_event *evt, - uint mask) -{ - int evtID,next,prev; - - pumpEvents(); - if (moveCursor) - moveCursor(mx,my); /* Move the mouse cursor */ - evt->what = EVT_NULLEVT; /* Default to null event */ - - if (count) { - for (evtID = head; evtID != -1; evtID = evtq[evtID].next) { - if (evtq[evtID].what & mask) - break; /* Found an event */ - } - if (evtID == -1) - return false; /* Event was not found */ - next = evtq[evtID].next; - prev = evtq[evtID].prev; - if (prev != -1) - evtq[prev].next = next; - else - head = next; - if (next != -1) - evtq[next].prev = prev; - else - tail = prev; - *evt = evtq[evtID]; /* Return the event */ - evtq[evtID].next = freeHead; /* and return to free list */ - freeHead = evtID; - count--; - if (evt->what == EVT_MOUSEMOVE) - oldMove = -1; - if (evt->what == EVT_KEYREPEAT) - oldKey = -1; - } - return evt->what != EVT_NULLEVT; -} - -/**************************************************************************** -PARAMETERS: -evt - Place to store event -mask - Event mask to use - -RETURNS: -True if an event is pending. - -REMARKS: -Peeks at the next pending event defined in 'mask' in the event queue. The -event is not removed from the event queue. -****************************************************************************/ -ibool _WDAPI WD_peekEvent( - WD_event *evt, - uint mask) -{ - int evtID; - - pumpEvents(); - if (moveCursor) - moveCursor(mx,my); /* Move the mouse cursor */ - evt->what = EVT_NULLEVT; /* Default to null event */ - - if (count) { - for (evtID = head; evtID != -1; evtID = evtq[evtID].next) { - if (evtq[evtID].what & mask) - break; /* Found an event */ - } - if (evtID == -1) - return false; /* Event was not found */ - - *evt = evtq[evtID]; /* Return the event */ - } - return evt->what != EVT_NULLEVT; -} - -/**************************************************************************** -PARAMETERS: -hwndMain - Handle to main window -_xRes - X resolution of graphics mode to be used -_yRes - Y resolulion of graphics mode to be used - -RETURNS: -Handle to the fullscreen event window if (we return hwndMain on Linux) - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling -ISR to be called whenever any button's are pressed or released. We also -build the free list of events in the event queue. -****************************************************************************/ -WD_HWND _WDAPI WD_startFullScreen( - WD_HWND hwndMain, - int _xRes, - int _yRes) -{ - int i; - struct termios conf; - if (!installed) { - Gpm_Connect gpm; - - /* Build free list, and initialise global data structures */ - for (i = 0; i < EVENTQSIZE; i++) - evtq[i].next = i+1; - evtq[EVENTQSIZE-1].next = -1; /* Terminate list */ - count = freeHead = 0; - head = tail = -1; - oldMove = -1; - oldKey = -1; - xRes = _xRes; - yRes = _yRes; - - /* Open the console device and initialise it for raw mode */ - tty_fd = PM_openConsole(); - - /* Wait until virtual terminal is active and take over control */ - wait_vt_active(); - take_vt_control(); - - /* Initialise keyboard handling to raw mode */ - if (ioctl(tty_fd, KDGKBMODE, &oldkbmode)) { - printf("WD_startFullScreen: cannot get keyboard mode.\n"); - exit(-1); - } - old_flags = fcntl(tty_fd,F_GETFL); - fcntl(tty_fd,F_SETFL,old_flags |= O_NONBLOCK); - tcgetattr(tty_fd, &conf); - old_conf = conf; - conf.c_lflag &= ~(ICANON | ECHO | ECHOE | ECHOK | ECHONL | NOFLSH | ISIG); - conf.c_iflag &= ~(ISTRIP | IGNCR | ICRNL | INLCR | BRKINT | PARMRK | INPCK | IUCLC | IXON | IXOFF); - conf.c_iflag |= (IGNBRK | IGNPAR); - conf.c_cc[VMIN] = 1; - conf.c_cc[VTIME] = 0; - conf.c_cc[VSUSP] = 0; - tcsetattr(tty_fd, TCSAFLUSH, &conf); - ioctl(tty_fd, KDSKBMODE, K_MEDIUMRAW); - - /* Clear the keyboard state information */ - memset(key_down, 0, sizeof(key_down)); - ioctl(tty_fd,KDSETLED,key_modifiers = 0); - - /* Initialize the mouse connection - The user *MUST* run gpm with the option -R for this to work (or have a MouseSystems mouse) - */ - if(Gpm_Open(&gpm,0) > 0){ /* GPM available */ - if ((conn = open(GPM_NODE_FIFO,O_RDONLY|O_SYNC)) < 0) - fprintf(stderr,"WD_startFullScreen: Can't open mouse connection.\n"); - }else{ - fprintf(stderr,"Warning: when not using gpm -R, only MouseSystems mice are currently supported.\n"); - if ((conn = open("/dev/mouse",O_RDONLY|O_SYNC)) < 0) - fprintf(stderr,"WD_startFullScreen: Can't open /dev/mouse.\n"); - } - Gpm_Close(); - - /* TODO: Scale the mouse coordinates to the specific resolution */ - - /* Save the state of the console */ - if ((stateBuf = malloc(PM_getConsoleStateSize())) == NULL) { - printf("Out of memory!\n"); - exit(-1); - } - PM_saveConsoleState(stateBuf,tty_fd); - initmode = VBE_getVideoMode(); - - /* Initialize the signal handler for timer events */ - signal(SIGALRM, timerHandler); - - /* Capture termination signals so we can clean up properly */ - signal(SIGTERM, exitHandler); - signal(SIGINT, exitHandler); - signal(SIGQUIT, exitHandler); - atexit(restore_term); - - /* Signal that we are installed */ - installed = true; - } - return hwndMain; -} - -/**************************************************************************** -REMARKS: -Lets the library know when fullscreen graphics mode has been initialized so -that we can properly scale the mouse driver coordinates. -****************************************************************************/ -void _WDAPI WD_inFullScreen(void) -{ - /* Nothing to do in here */ -} - -/**************************************************************************** -REMARKS: -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void _WDAPI WD_restoreGDI(void) -{ - restore_term(); -} - -/**************************************************************************** -PARAMETERS: -ticks - Number of ticks between timer tick messages - -RETURNS: -Previous value for the timer tick event spacing. - -REMARKS: -The event module will automatically generate periodic timer tick events for -you, with 'ticks' between each event posting. If you set the value of -'ticks' to 0, the timer tick events are turned off. -****************************************************************************/ -int _WDAPI WD_setTimerTick( - int ticks) -{ - int old; - struct itimerval tim; - long ms = TICKS_TO_USEC(ticks); - - getitimer(ITIMER_REAL, &tim); - old = USEC_TO_TICKS(tim.it_value.tv_sec*1000000.0 + tim.it_value.tv_usec); - tim.it_interval.tv_sec = ms / 1000000; - tim.it_interval.tv_usec = ms % 1000000; - setitimer(ITIMER_REAL, &tim, NULL); - return old; -} - -/**************************************************************************** -PARAMETERS: -saveState - Address of suspend app callback to register - -REMARKS: -Registers a user application supplied suspend application callback so that -we can properly handle virtual terminal switching. -****************************************************************************/ -void _WDAPI WD_setSuspendAppCallback( - int (_ASMAPI *saveState)(int flags)) -{ - suspendAppCallback = saveState; -} - -/**************************************************************************** -PARAMETERS: -x - New X coordinate to move the mouse cursor to -y - New Y coordinate to move the mouse cursor to - -REMARKS: -Moves to mouse cursor to the specified coordinate. -****************************************************************************/ -void _WDAPI WD_setMousePos( - int x, - int y) -{ - mx = x; - my = y; -} - -/**************************************************************************** -PARAMETERS: -x - Place to store X coordinate of mouse cursor -y - Place to store Y coordinate of mouse cursor - -REMARKS: -Reads the current mouse cursor location int *screen* coordinates. -****************************************************************************/ -void _WDAPI WD_getMousePos( - int *x, - int *y) -{ - *x = mx; - *y = my; -} - -/**************************************************************************** -PARAMETERS: -mcb - Address of mouse callback function - -REMARKS: -Registers an application supplied mouse callback function that is called -whenever the mouse cursor moves. -****************************************************************************/ -void _WDAPI WD_setMouseCallback( - void (_ASMAPI *mcb)(int x,int y)) -{ - moveCursor = mcb; -} - -/**************************************************************************** -PARAMETERS: -xRes - New X resolution of graphics mode -yRes - New Y resolution of graphics mode - -REMARKS: -This is called to inform the event handling code that the screen resolution -has changed so that the mouse coordinates can be scaled appropriately. -****************************************************************************/ -void _WDAPI WD_changeResolution( - int xRes, - int yRes) -{ - // Gpm_FitValues(xRes, yRes); // ?? -} - -/**************************************************************************** -PARAMETERS: -scancode - Scan code to check if a key is down - -REMARKS: -Determines if a particular key is down based on the scan code for the key. -****************************************************************************/ -ibool _WDAPI WD_isKeyDown( - uchar scancode) -{ - return key_down[scancode]; -} - -/**************************************************************************** -REMARKS: -Determines if the application needs to run in safe mode. Not necessary for -anything but broken Windows 95 display drivers so we return false for -Linux. -****************************************************************************/ -int _WDAPI WD_isSafeMode(void) -{ - return false; -} - - diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h deleted file mode 100644 index eadedfb..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h +++ /dev/null @@ -1,60 +0,0 @@ -/**************************************************************************** -* -* SciTech Multi-platform Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Linux -* -* Description: Include all the OS specific header files. -* -****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef USE_OS_JOYSTICK -#include -#endif -#include -#include -#include -#include -#include - -/* Internal global variables */ - -extern int _PM_console_fd,_PM_leds,_PM_modifiers; - -/* Internal function prototypes */ - -void _PM_restore_kb_mode(void); -void _PM_keyboard_rawmode(void); - -/* Linux needs the generic joystick scaling code */ - -#define NEED_SCALE_JOY_AXIS diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c b/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c deleted file mode 100644 index c12a835..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c +++ /dev/null @@ -1,1809 +0,0 @@ -;/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Portions copyright (C) Josh Vanderhoof -* -* Language: ANSI C -* Environment: Linux -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef ENABLE_MTRR -#include -#endif -#include -#ifdef __GLIBC__ -#include -#endif - -/*--------------------------- Global variables ----------------------------*/ - -#define REAL_MEM_BASE ((void *)0x10000) -#define REAL_MEM_SIZE 0x10000 -#define REAL_MEM_BLOCKS 0x100 -#define DEFAULT_VM86_FLAGS (IF_MASK | IOPL_MASK) -#define DEFAULT_STACK_SIZE 0x1000 -#define RETURN_TO_32_INT 255 - -/* Quick and dirty fix for vm86() syscall from lrmi 0.6 */ -static int -vm86(struct vm86_struct *vm) - { - int r; -#ifdef __PIC__ - asm volatile ( - "pushl %%ebx\n\t" - "movl %2, %%ebx\n\t" - "int $0x80\n\t" - "popl %%ebx" - : "=a" (r) - : "0" (113), "r" (vm)); -#else - asm volatile ( - "int $0x80" - : "=a" (r) - : "0" (113), "b" (vm)); -#endif - return r; - } - - -static struct { - int ready; - unsigned short ret_seg, ret_off; - unsigned short stack_seg, stack_off; - struct vm86_struct vm; - } context = {0}; - -struct mem_block { - unsigned int size : 20; - unsigned int free : 1; - }; - -static struct { - int ready; - int count; - struct mem_block blocks[REAL_MEM_BLOCKS]; - } mem_info = {0}; - -int _PM_console_fd = -1; -int _PM_leds = 0,_PM_modifiers = 0; -static ibool inited = false; -static int tty_vc = 0; -static int console_count = 0; -static int startup_vc; -static int fd_mem = 0; -static ibool in_raw_mode = false; -#ifdef ENABLE_MTRR -static int mtrr_fd; -#endif -static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ -static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ -static uint VESABuf_rseg; /* Real mode segment of VESABuf */ -static uint VESABuf_roff; /* Real mode offset of VESABuf */ -#ifdef TRACE_IO -static ulong traceAddr; -#endif - -static void (PMAPIP fatalErrorCleanup)(void) = NULL; - -/*----------------------------- Implementation ----------------------------*/ - -#ifdef TRACE_IO -extern void printk(char *msg,...); -#endif - -static inline void port_out(int value, int port) -{ -#ifdef TRACE_IO - printk("%04X:%04X: outb.%04X <- %02X\n", traceAddr >> 16, traceAddr & 0xFFFF, (ushort)port, (uchar)value); -#endif - asm volatile ("outb %0,%1" - ::"a" ((unsigned char) value), "d"((unsigned short) port)); -} - -static inline void port_outw(int value, int port) -{ -#ifdef TRACE_IO - printk("%04X:%04X: outw.%04X <- %04X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ushort)value); -#endif - asm volatile ("outw %0,%1" - ::"a" ((unsigned short) value), "d"((unsigned short) port)); -} - -static inline void port_outl(int value, int port) -{ -#ifdef TRACE_IO - printk("%04X:%04X: outl.%04X <- %08X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ulong)value); -#endif - asm volatile ("outl %0,%1" - ::"a" ((unsigned long) value), "d"((unsigned short) port)); -} - -static inline unsigned int port_in(int port) -{ - unsigned char value; - asm volatile ("inb %1,%0" - :"=a" ((unsigned char)value) - :"d"((unsigned short) port)); -#ifdef TRACE_IO - printk("%04X:%04X: inb.%04X -> %02X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (uchar)value); -#endif - return value; -} - -static inline unsigned int port_inw(int port) -{ - unsigned short value; - asm volatile ("inw %1,%0" - :"=a" ((unsigned short)value) - :"d"((unsigned short) port)); -#ifdef TRACE_IO - printk("%04X:%04X: inw.%04X -> %04X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ushort)value); -#endif - return value; -} - -static inline unsigned int port_inl(int port) -{ - unsigned long value; - asm volatile ("inl %1,%0" - :"=a" ((unsigned long)value) - :"d"((unsigned short) port)); -#ifdef TRACE_IO - printk("%04X:%04X: inl.%04X -> %08X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ulong)value); -#endif - return value; -} - -static int real_mem_init(void) -{ - void *m; - int fd_zero; - - if (mem_info.ready) - return 1; - - if ((fd_zero = open("/dev/zero", O_RDONLY)) == -1) - PM_fatalError("You must have root privledges to run this program!"); - if ((m = mmap((void *)REAL_MEM_BASE, REAL_MEM_SIZE, - PROT_READ | PROT_WRITE | PROT_EXEC, - MAP_FIXED | MAP_PRIVATE, fd_zero, 0)) == (void *)-1) { - close(fd_zero); - PM_fatalError("You must have root privledges to run this program!"); - } - mem_info.ready = 1; - mem_info.count = 1; - mem_info.blocks[0].size = REAL_MEM_SIZE; - mem_info.blocks[0].free = 1; - return 1; -} - -static void insert_block(int i) -{ - memmove( - mem_info.blocks + i + 1, - mem_info.blocks + i, - (mem_info.count - i) * sizeof(struct mem_block)); - mem_info.count++; -} - -static void delete_block(int i) -{ - mem_info.count--; - - memmove( - mem_info.blocks + i, - mem_info.blocks + i + 1, - (mem_info.count - i) * sizeof(struct mem_block)); -} - -static inline void set_bit(unsigned int bit, void *array) -{ - unsigned char *a = array; - a[bit / 8] |= (1 << (bit % 8)); -} - -static inline unsigned int get_int_seg(int i) -{ - return *(unsigned short *)(i * 4 + 2); -} - -static inline unsigned int get_int_off(int i) -{ - return *(unsigned short *)(i * 4); -} - -static inline void pushw(unsigned short i) -{ - struct vm86_regs *r = &context.vm.regs; - r->esp -= 2; - *(unsigned short *)(((unsigned int)r->ss << 4) + r->esp) = i; -} - -ibool PMAPI PM_haveBIOSAccess(void) -{ return true; } - -void PMAPI PM_init(void) -{ - void *m; - uint r_seg,r_off; - - if (inited) - return; - - /* Map the Interrupt Vectors (0x0 - 0x400) + BIOS data (0x400 - 0x502) - * and the physical framebuffer and ROM images from (0xa0000 - 0x100000) - */ - real_mem_init(); - if (!fd_mem && (fd_mem = open("/dev/mem", O_RDWR)) == -1) { - PM_fatalError("You must have root privileges to run this program!"); - } - if ((m = mmap((void *)0, 0x502, - PROT_READ | PROT_WRITE | PROT_EXEC, - MAP_FIXED | MAP_PRIVATE, fd_mem, 0)) == (void *)-1) { - PM_fatalError("You must have root privileges to run this program!"); - } - if ((m = mmap((void *)0xA0000, 0xC0000 - 0xA0000, - PROT_READ | PROT_WRITE, - MAP_FIXED | MAP_SHARED, fd_mem, 0xA0000)) == (void *)-1) { - PM_fatalError("You must have root privileges to run this program!"); - } - if ((m = mmap((void *)0xC0000, 0xD0000 - 0xC0000, - PROT_READ | PROT_WRITE | PROT_EXEC, - MAP_FIXED | MAP_PRIVATE, fd_mem, 0xC0000)) == (void *)-1) { - PM_fatalError("You must have root privileges to run this program!"); - } - if ((m = mmap((void *)0xD0000, 0x100000 - 0xD0000, - PROT_READ | PROT_WRITE, - MAP_FIXED | MAP_SHARED, fd_mem, 0xD0000)) == (void *)-1) { - PM_fatalError("You must have root privileges to run this program!"); - } - inited = 1; - - /* Allocate a stack */ - m = PM_allocRealSeg(DEFAULT_STACK_SIZE,&r_seg,&r_off); - context.stack_seg = r_seg; - context.stack_off = r_off+DEFAULT_STACK_SIZE; - - /* Allocate the return to 32 bit routine */ - m = PM_allocRealSeg(2,&r_seg,&r_off); - context.ret_seg = r_seg; - context.ret_off = r_off; - ((uchar*)m)[0] = 0xCD; /* int opcode */ - ((uchar*)m)[1] = RETURN_TO_32_INT; - memset(&context.vm, 0, sizeof(context.vm)); - - /* Enable kernel emulation of all ints except RETURN_TO_32_INT */ - memset(&context.vm.int_revectored, 0, sizeof(context.vm.int_revectored)); - set_bit(RETURN_TO_32_INT, &context.vm.int_revectored); - context.ready = 1; -#ifdef ENABLE_MTRR - mtrr_fd = open("/dev/cpu/mtrr", O_RDWR, 0); - if (mtrr_fd < 0) - mtrr_fd = open("/proc/mtrr", O_RDWR, 0); -#endif - /* Enable I/O permissions to directly access I/O ports. We break the - * allocation into two parts, one for the ports from 0-0x3FF and - * another for the remaining ports up to 0xFFFF. Standard Linux kernels - * only allow the first 0x400 ports to be enabled, so to enable all - * 65536 ports you need a patched kernel that will enable the full - * 8Kb I/O permissions bitmap. - */ -#ifndef TRACE_IO - ioperm(0x0,0x400,1); - ioperm(0x400,0x10000-0x400,1); -#endif - iopl(3); -} - -long PMAPI PM_getOSType(void) -{ return _OS_LINUX; } - -int PMAPI PM_getModeType(void) -{ return PM_386; } - -void PMAPI PM_backslash(char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '/') { - s[pos] = '/'; - s[pos+1] = '\0'; - } -} - -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -void PMAPI PM_fatalError(const char *msg) -{ - if (fatalErrorCleanup) - fatalErrorCleanup(); - fprintf(stderr,"%s\n", msg); - fflush(stderr); - exit(1); -} - -static void ExitVBEBuf(void) -{ - if (VESABuf_ptr) - PM_freeRealSeg(VESABuf_ptr); - VESABuf_ptr = 0; -} - -void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) -{ - if (!VESABuf_ptr) { - /* Allocate a global buffer for communicating with the VESA VBE */ - if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) - return NULL; - atexit(ExitVBEBuf); - } - *len = VESABuf_len; - *rseg = VESABuf_rseg; - *roff = VESABuf_roff; - return VESABuf_ptr; -} - -/* New raw console based getch and kbhit functions */ - -#define KB_CAPS LED_CAP /* 4 */ -#define KB_NUMLOCK LED_NUM /* 2 */ -#define KB_SCROLL LED_SCR /* 1 */ -#define KB_SHIFT 8 -#define KB_CONTROL 16 -#define KB_ALT 32 - -/* Structure used to save the keyboard mode to disk. We save it to disk - * so that we can properly restore the mode later if the program crashed. - */ - -typedef struct { - struct termios termios; - int kb_mode; - int leds; - int flags; - int startup_vc; - } keyboard_mode; - -/* Name of the file used to save keyboard mode information */ - -#define KBMODE_DAT "kbmode.dat" - -/**************************************************************************** -REMARKS: -Open the keyboard mode file on disk. -****************************************************************************/ -static FILE *open_kb_mode( - char *mode, - char *path) -{ - if (!PM_findBPD("graphics.bpd",path)) - return NULL; - PM_backslash(path); - strcat(path,KBMODE_DAT); - return fopen(path,mode); -} - -/**************************************************************************** -REMARKS: -Restore the keyboard to normal mode -****************************************************************************/ -void _PM_restore_kb_mode(void) -{ - FILE *kbmode; - keyboard_mode mode; - char path[PM_MAX_PATH]; - - if (_PM_console_fd != -1 && (kbmode = open_kb_mode("rb",path)) != NULL) { - if (fread(&mode,1,sizeof(mode),kbmode) == sizeof(mode)) { - if (mode.startup_vc > 0) - ioctl(_PM_console_fd, VT_ACTIVATE, mode.startup_vc); - ioctl(_PM_console_fd, KDSKBMODE, mode.kb_mode); - ioctl(_PM_console_fd, KDSETLED, mode.leds); - tcsetattr(_PM_console_fd, TCSAFLUSH, &mode.termios); - fcntl(_PM_console_fd,F_SETFL,mode.flags); - } - fclose(kbmode); - unlink(path); - in_raw_mode = false; - } -} - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _PM_abort( - int signo) -{ - char buf[80]; - - sprintf(buf,"Terminating on signal %d",signo); - _PM_restore_kb_mode(); - PM_fatalError(buf); -} - -/**************************************************************************** -REMARKS: -Put the keyboard into raw mode -****************************************************************************/ -void _PM_keyboard_rawmode(void) -{ - struct termios conf; - FILE *kbmode; - keyboard_mode mode; - char path[PM_MAX_PATH]; - int i; - static int sig_list[] = { - SIGHUP, - SIGINT, - SIGQUIT, - SIGILL, - SIGTRAP, - SIGABRT, - SIGIOT, - SIGBUS, - SIGFPE, - SIGKILL, - SIGSEGV, - SIGTERM, - }; - - if ((kbmode = open_kb_mode("rb",path)) == NULL) { - if ((kbmode = open_kb_mode("wb",path)) == NULL) - PM_fatalError("Unable to open kbmode.dat file for writing!"); - if (ioctl(_PM_console_fd, KDGKBMODE, &mode.kb_mode)) - perror("KDGKBMODE"); - ioctl(_PM_console_fd, KDGETLED, &mode.leds); - _PM_leds = mode.leds & 0xF; - _PM_modifiers = 0; - tcgetattr(_PM_console_fd, &mode.termios); - conf = mode.termios; - conf.c_lflag &= ~(ICANON | ECHO | ISIG); - conf.c_iflag &= ~(ISTRIP | IGNCR | ICRNL | INLCR | BRKINT | PARMRK | INPCK | IUCLC | IXON | IXOFF); - conf.c_iflag |= (IGNBRK | IGNPAR); - conf.c_cc[VMIN] = 1; - conf.c_cc[VTIME] = 0; - conf.c_cc[VSUSP] = 0; - tcsetattr(_PM_console_fd, TCSAFLUSH, &conf); - mode.flags = fcntl(_PM_console_fd,F_GETFL); - if (ioctl(_PM_console_fd, KDSKBMODE, K_MEDIUMRAW)) - perror("KDSKBMODE"); - atexit(_PM_restore_kb_mode); - for (i = 0; i < sizeof(sig_list)/sizeof(sig_list[0]); i++) - signal(sig_list[i], _PM_abort); - mode.startup_vc = startup_vc; - if (fwrite(&mode,1,sizeof(mode),kbmode) != sizeof(mode)) - PM_fatalError("Error writing kbmode.dat!"); - fclose(kbmode); - in_raw_mode = true; - } -} - -int PMAPI PM_kbhit(void) -{ - fd_set s; - struct timeval tv = { 0, 0 }; - - if (console_count == 0) - PM_fatalError("You *must* open a console before using PM_kbhit!"); - if (!in_raw_mode) - _PM_keyboard_rawmode(); - FD_ZERO(&s); - FD_SET(_PM_console_fd, &s); - return select(_PM_console_fd+1, &s, NULL, NULL, &tv) > 0; -} - -int PMAPI PM_getch(void) -{ - static uchar c; - int release; - static struct kbentry ke; - - if (console_count == 0) - PM_fatalError("You *must* open a console before using PM_getch!"); - if (!in_raw_mode) - _PM_keyboard_rawmode(); - while (read(_PM_console_fd, &c, 1) > 0) { - release = c & 0x80; - c &= 0x7F; - if (release) { - switch(c){ - case 42: case 54: /* Shift */ - _PM_modifiers &= ~KB_SHIFT; - break; - case 29: case 97: /* Control */ - _PM_modifiers &= ~KB_CONTROL; - break; - case 56: case 100: /* Alt / AltGr */ - _PM_modifiers &= ~KB_ALT; - break; - } - continue; - } - switch (c) { - case 42: case 54: /* Shift */ - _PM_modifiers |= KB_SHIFT; - break; - case 29: case 97: /* Control */ - _PM_modifiers |= KB_CONTROL; - break; - case 56: case 100: /* Alt / AltGr */ - _PM_modifiers |= KB_ALT; - break; - case 58: /* Caps Lock */ - _PM_modifiers ^= KB_CAPS; - ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7); - break; - case 69: /* Num Lock */ - _PM_modifiers ^= KB_NUMLOCK; - ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7); - break; - case 70: /* Scroll Lock */ - _PM_modifiers ^= KB_SCROLL; - ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7); - break; - case 28: - return 0x1C; - default: - ke.kb_index = c; - ke.kb_table = 0; - if ((_PM_modifiers & KB_SHIFT) || (_PM_modifiers & KB_CAPS)) - ke.kb_table |= K_SHIFTTAB; - if (_PM_modifiers & KB_ALT) - ke.kb_table |= K_ALTTAB; - ioctl(_PM_console_fd, KDGKBENT, (ulong)&ke); - c = ke.kb_value & 0xFF; - return c; - } - } - return 0; -} - -/**************************************************************************** -REMARKS: -Sleep until the virtual terminal is active -****************************************************************************/ -static void wait_vt_active( - int _PM_console_fd) -{ - while (ioctl(_PM_console_fd, VT_WAITACTIVE, tty_vc) < 0) { - if ((errno != EAGAIN) && (errno != EINTR)) { - perror("ioctl(VT_WAITACTIVE)"); - exit(1); - } - usleep(150000); - } -} - -/**************************************************************************** -REMARKS: -Checks the owner of the specified virtual console. -****************************************************************************/ -static int check_owner( - int vc) -{ - struct stat sbuf; - char fname[30]; - - sprintf(fname, "/dev/tty%d", vc); - if ((stat(fname, &sbuf) >= 0) && (getuid() == sbuf.st_uid)) - return 1; - printf("You must be the owner of the current console to use this program.\n"); - return 0; -} - -/**************************************************************************** -REMARKS: -Checks if the console is currently in graphics mode, and if so we forcibly -restore it back to text mode again. This handles the case when a Nucleus or -MGL program crashes and leaves the console in graphics mode. Running the -textmode utility (or any other Nucleus/MGL program) via a telnet session -into the machine will restore it back to normal. -****************************************************************************/ -static void restore_text_console( - int console_id) -{ - if (ioctl(console_id, KDSETMODE, KD_TEXT) < 0) - LOGWARN("ioctl(KDSETMODE) failed"); - _PM_restore_kb_mode(); -} - -/**************************************************************************** -REMARKS: -Opens up the console device for output by finding an appropriate virutal -console that we can run on. -****************************************************************************/ -PM_HWND PMAPI PM_openConsole( - PM_HWND hwndUser, - int device, - int xRes, - int yRes, - int bpp, - ibool fullScreen) -{ - struct vt_mode vtm; - struct vt_stat vts; - struct stat sbuf; - char fname[30]; - - /* Check if we have already opened the console */ - if (console_count++) - return _PM_console_fd; - - /* Now, it would be great if we could use /dev/tty and see what it is - * connected to. Alas, we cannot find out reliably what VC /dev/tty is - * bound to. Thus we parse stdin through stderr for a reliable VC. - */ - startup_vc = 0; - for (_PM_console_fd = 0; _PM_console_fd < 3; _PM_console_fd++) { - if (fstat(_PM_console_fd, &sbuf) < 0) - continue; - if (ioctl(_PM_console_fd, VT_GETMODE, &vtm) < 0) - continue; - if ((sbuf.st_rdev & 0xFF00) != 0x400) - continue; - if (!(sbuf.st_rdev & 0xFF)) - continue; - tty_vc = sbuf.st_rdev & 0xFF; - restore_text_console(_PM_console_fd); - return _PM_console_fd; - } - if ((_PM_console_fd = open("/dev/console", O_RDWR)) < 0) { - printf("open_dev_console: can't open /dev/console \n"); - exit(1); - } - if (ioctl(_PM_console_fd, VT_OPENQRY, &tty_vc) < 0) - goto Error; - if (tty_vc <= 0) - goto Error; - sprintf(fname, "/dev/tty%d", tty_vc); - close(_PM_console_fd); - - /* Change our control terminal */ - setsid(); - - /* We must use RDWR to allow for output... */ - if (((_PM_console_fd = open(fname, O_RDWR)) >= 0) && - (ioctl(_PM_console_fd, VT_GETSTATE, &vts) >= 0)) { - if (!check_owner(vts.v_active)) - goto Error; - restore_text_console(_PM_console_fd); - - /* Success, redirect all stdios */ - fflush(stdin); - fflush(stdout); - fflush(stderr); - close(0); - close(1); - close(2); - dup(_PM_console_fd); - dup(_PM_console_fd); - dup(_PM_console_fd); - - /* clear screen and switch to it */ - fwrite("\e[H\e[J", 6, 1, stderr); - fflush(stderr); - if (tty_vc != vts.v_active) { - startup_vc = vts.v_active; - ioctl(_PM_console_fd, VT_ACTIVATE, tty_vc); - wait_vt_active(_PM_console_fd); - } - } - return _PM_console_fd; - -Error: - if (_PM_console_fd > 2) - close(_PM_console_fd); - console_count = 0; - PM_fatalError( - "Not running in a graphics capable console,\n" - "and unable to find one.\n"); - return -1; -} - -#define FONT_C 0x10000 /* 64KB for font data */ - -/**************************************************************************** -REMARKS: -Returns the size of the console state buffer. -****************************************************************************/ -int PMAPI PM_getConsoleStateSize(void) -{ - if (!inited) - PM_init(); - return PM_getVGAStateSize() + FONT_C*2; -} - -/**************************************************************************** -REMARKS: -Save the state of the Linux console. -****************************************************************************/ -void PMAPI PM_saveConsoleState(void *stateBuf,int console_id) -{ - uchar *regs = stateBuf; - - /* Save the current console font */ - if (ioctl(console_id,GIO_FONT,®s[PM_getVGAStateSize()]) < 0) - perror("ioctl(GIO_FONT)"); - - /* Inform the Linux console that we are going into graphics mode */ - if (ioctl(console_id, KDSETMODE, KD_GRAPHICS) < 0) - perror("ioctl(KDSETMODE)"); - - /* Save state of VGA registers */ - PM_saveVGAState(stateBuf); -} - -void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) -{ - /* TODO: Implement support for allowing console switching! */ -} - -/**************************************************************************** -REMARKS: -Restore the state of the Linux console. -****************************************************************************/ -void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND console_id) -{ - const uchar *regs = stateBuf; - - /* Restore the state of the VGA compatible registers */ - PM_restoreVGAState(stateBuf); - - /* Inform the Linux console that we are back from graphics modes */ - if (ioctl(console_id, KDSETMODE, KD_TEXT) < 0) - LOGWARN("ioctl(KDSETMODE) failed"); - - /* Restore the old console font */ - if (ioctl(console_id,PIO_FONT,®s[PM_getVGAStateSize()]) < 0) - LOGWARN("ioctl(KDSETMODE) failed"); - - /* Coming back from graphics mode on Linux also restored the previous - * text mode console contents, so we need to clear the screen to get - * around this since the cursor does not get homed by our code. - */ - fflush(stdout); - fflush(stderr); - printf("\033[H\033[J"); - fflush(stdout); -} - -/**************************************************************************** -REMARKS: -Close the Linux console and put it back to normal. -****************************************************************************/ -void PMAPI PM_closeConsole(PM_HWND _PM_console_fd) -{ - /* Restore console to normal operation */ - if (--console_count == 0) { - /* Re-activate the original virtual console */ - if (startup_vc > 0) - ioctl(_PM_console_fd, VT_ACTIVATE, startup_vc); - - /* Close the console file descriptor */ - if (_PM_console_fd > 2) - close(_PM_console_fd); - _PM_console_fd = -1; - } -} - -void PM_setOSCursorLocation(int x,int y) -{ - /* Nothing to do in here */ -} - -/**************************************************************************** -REMARKS: -Set the screen width and height for the Linux console. -****************************************************************************/ -void PM_setOSScreenWidth(int width,int height) -{ - struct winsize ws; - struct vt_sizes vs; - - /* Resize the software terminal */ - ws.ws_col = width; - ws.ws_row = height; - ioctl(_PM_console_fd, TIOCSWINSZ, &ws); - - /* And the hardware */ - vs.v_rows = height; - vs.v_cols = width; - vs.v_scrollsize = 0; - ioctl(_PM_console_fd, VT_RESIZE, &vs); -} - -ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency) -{ - /* TODO: Implement this for Linux */ - return false; -} - -void PMAPI PM_setRealTimeClockFrequency(int frequency) -{ - /* TODO: Implement this for Linux */ -} - -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - /* TODO: Implement this for Linux */ -} - -char * PMAPI PM_getCurrentPath( - char *path, - int maxLen) -{ - return getcwd(path,maxLen); -} - -char PMAPI PM_getBootDrive(void) -{ return '/'; } - -const char * PMAPI PM_getVBEAFPath(void) -{ return PM_getNucleusConfigPath(); } - -const char * PMAPI PM_getNucleusPath(void) -{ - char *env = getenv("NUCLEUS_PATH"); - return env ? env : "/usr/lib/nucleus"; -} - -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[256]; - strcpy(path,PM_getNucleusPath()); - PM_backslash(path); - strcat(path,"config"); - return path; -} - -const char * PMAPI PM_getUniqueID(void) -{ - static char buf[128]; - gethostname(buf, 128); - return buf; -} - -const char * PMAPI PM_getMachineName(void) -{ - static char buf[128]; - gethostname(buf, 128); - return buf; -} - -void * PMAPI PM_getBIOSPointer(void) -{ - static uchar *zeroPtr = NULL; - if (!zeroPtr) - zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); - return (void*)(zeroPtr + 0x400); -} - -void * PMAPI PM_getA0000Pointer(void) -{ - /* PM_init maps in the 0xA0000 framebuffer region 1:1 with our - * address mapping, so we can return the address here. - */ - if (!inited) - PM_init(); - return (void*)(0xA0000); -} - -void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) -{ - uchar *p; - ulong baseAddr,baseOfs; - - if (!inited) - PM_init(); - if (base >= 0xA0000 && base < 0x100000) - return (void*)base; - if (!fd_mem && (fd_mem = open("/dev/mem", O_RDWR)) == -1) - return NULL; - - /* Round the physical address to a 4Kb boundary and the limit to a - * 4Kb-1 boundary before passing the values to mmap. If we round the - * physical address, then we also add an extra offset into the address - * that we return. - */ - baseOfs = base & 4095; - baseAddr = base & ~4095; - limit = ((limit+baseOfs+1+4095) & ~4095)-1; - if ((p = mmap(0, limit+1, - PROT_READ | PROT_WRITE, MAP_SHARED, - fd_mem, baseAddr)) == (void *)-1) - return NULL; - return (void*)(p+baseOfs); -} - -void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) -{ - if ((ulong)ptr >= 0x100000) - munmap(ptr,limit+1); -} - -ulong PMAPI PM_getPhysicalAddr(void *p) -{ - /* TODO: This function should find the physical address of a linear */ - /* address. */ - return 0xFFFFFFFFUL; -} - -ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) -{ - /* TODO: This function should find a range of physical addresses */ - /* for a linear address. */ - return false; -} - -void PMAPI PM_sleep(ulong milliseconds) -{ - /* TODO: Put the process to sleep for milliseconds */ -} - -int PMAPI PM_getCOMPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - } - return 0; -} - -int PMAPI PM_getLPTPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -void * PMAPI PM_mallocShared(long size) -{ - return PM_malloc(size); -} - -void PMAPI PM_freeShared(void *ptr) -{ - PM_free(ptr); -} - -void * PMAPI PM_mapToProcess(void *base,ulong limit) -{ return (void*)base; } - -void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) -{ - /* PM_init maps in the 0xA0000-0x100000 region 1:1 with our - * address mapping, as well as all memory blocks in a 1:1 address - * mapping so we can simply return the physical address in here. - */ - if (!inited) - PM_init(); - return (void*)MK_PHYS(r_seg,r_off); -} - -void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) -{ - int i; - char *r = (char *)REAL_MEM_BASE; - - if (!inited) - PM_init(); - if (!mem_info.ready) - return NULL; - if (mem_info.count == REAL_MEM_BLOCKS) - return NULL; - size = (size + 15) & ~15; - for (i = 0; i < mem_info.count; i++) { - if (mem_info.blocks[i].free && size < mem_info.blocks[i].size) { - insert_block(i); - mem_info.blocks[i].size = size; - mem_info.blocks[i].free = 0; - mem_info.blocks[i + 1].size -= size; - *r_seg = (uint)(r) >> 4; - *r_off = (uint)(r) & 0xF; - return (void *)r; - } - r += mem_info.blocks[i].size; - } - return NULL; -} - -void PMAPI PM_freeRealSeg(void *mem) -{ - int i; - char *r = (char *)REAL_MEM_BASE; - - if (!mem_info.ready) - return; - i = 0; - while (mem != (void *)r) { - r += mem_info.blocks[i].size; - i++; - if (i == mem_info.count) - return; - } - mem_info.blocks[i].free = 1; - if (i + 1 < mem_info.count && mem_info.blocks[i + 1].free) { - mem_info.blocks[i].size += mem_info.blocks[i + 1].size; - delete_block(i + 1); - } - if (i - 1 >= 0 && mem_info.blocks[i - 1].free) { - mem_info.blocks[i - 1].size += mem_info.blocks[i].size; - delete_block(i); - } -} - -#define DIRECTION_FLAG (1 << 10) - -static void em_ins(int size) -{ - unsigned int edx, edi; - - edx = context.vm.regs.edx & 0xffff; - edi = context.vm.regs.edi & 0xffff; - edi += (unsigned int)context.vm.regs.ds << 4; - if (context.vm.regs.eflags & DIRECTION_FLAG) { - if (size == 4) - asm volatile ("std; insl; cld" - : "=D" (edi) : "d" (edx), "0" (edi)); - else if (size == 2) - asm volatile ("std; insw; cld" - : "=D" (edi) : "d" (edx), "0" (edi)); - else - asm volatile ("std; insb; cld" - : "=D" (edi) : "d" (edx), "0" (edi)); - } - else { - if (size == 4) - asm volatile ("cld; insl" - : "=D" (edi) : "d" (edx), "0" (edi)); - else if (size == 2) - asm volatile ("cld; insw" - : "=D" (edi) : "d" (edx), "0" (edi)); - else - asm volatile ("cld; insb" - : "=D" (edi) : "d" (edx), "0" (edi)); - } - edi -= (unsigned int)context.vm.regs.ds << 4; - context.vm.regs.edi &= 0xffff0000; - context.vm.regs.edi |= edi & 0xffff; -} - -static void em_rep_ins(int size) -{ - unsigned int ecx, edx, edi; - - ecx = context.vm.regs.ecx & 0xffff; - edx = context.vm.regs.edx & 0xffff; - edi = context.vm.regs.edi & 0xffff; - edi += (unsigned int)context.vm.regs.ds << 4; - if (context.vm.regs.eflags & DIRECTION_FLAG) { - if (size == 4) - asm volatile ("std; rep; insl; cld" - : "=D" (edi), "=c" (ecx) - : "d" (edx), "0" (edi), "1" (ecx)); - else if (size == 2) - asm volatile ("std; rep; insw; cld" - : "=D" (edi), "=c" (ecx) - : "d" (edx), "0" (edi), "1" (ecx)); - else - asm volatile ("std; rep; insb; cld" - : "=D" (edi), "=c" (ecx) - : "d" (edx), "0" (edi), "1" (ecx)); - } - else { - if (size == 4) - asm volatile ("cld; rep; insl" - : "=D" (edi), "=c" (ecx) - : "d" (edx), "0" (edi), "1" (ecx)); - else if (size == 2) - asm volatile ("cld; rep; insw" - : "=D" (edi), "=c" (ecx) - : "d" (edx), "0" (edi), "1" (ecx)); - else - asm volatile ("cld; rep; insb" - : "=D" (edi), "=c" (ecx) - : "d" (edx), "0" (edi), "1" (ecx)); - } - - edi -= (unsigned int)context.vm.regs.ds << 4; - context.vm.regs.edi &= 0xffff0000; - context.vm.regs.edi |= edi & 0xffff; - context.vm.regs.ecx &= 0xffff0000; - context.vm.regs.ecx |= ecx & 0xffff; -} - -static void em_outs(int size) -{ - unsigned int edx, esi; - - edx = context.vm.regs.edx & 0xffff; - esi = context.vm.regs.esi & 0xffff; - esi += (unsigned int)context.vm.regs.ds << 4; - if (context.vm.regs.eflags & DIRECTION_FLAG) { - if (size == 4) - asm volatile ("std; outsl; cld" - : "=S" (esi) : "d" (edx), "0" (esi)); - else if (size == 2) - asm volatile ("std; outsw; cld" - : "=S" (esi) : "d" (edx), "0" (esi)); - else - asm volatile ("std; outsb; cld" - : "=S" (esi) : "d" (edx), "0" (esi)); - } - else { - if (size == 4) - asm volatile ("cld; outsl" - : "=S" (esi) : "d" (edx), "0" (esi)); - else if (size == 2) - asm volatile ("cld; outsw" - : "=S" (esi) : "d" (edx), "0" (esi)); - else - asm volatile ("cld; outsb" - : "=S" (esi) : "d" (edx), "0" (esi)); - } - - esi -= (unsigned int)context.vm.regs.ds << 4; - context.vm.regs.esi &= 0xffff0000; - context.vm.regs.esi |= esi & 0xffff; -} - -static void em_rep_outs(int size) -{ - unsigned int ecx, edx, esi; - - ecx = context.vm.regs.ecx & 0xffff; - edx = context.vm.regs.edx & 0xffff; - esi = context.vm.regs.esi & 0xffff; - esi += (unsigned int)context.vm.regs.ds << 4; - if (context.vm.regs.eflags & DIRECTION_FLAG) { - if (size == 4) - asm volatile ("std; rep; outsl; cld" - : "=S" (esi), "=c" (ecx) - : "d" (edx), "0" (esi), "1" (ecx)); - else if (size == 2) - asm volatile ("std; rep; outsw; cld" - : "=S" (esi), "=c" (ecx) - : "d" (edx), "0" (esi), "1" (ecx)); - else - asm volatile ("std; rep; outsb; cld" - : "=S" (esi), "=c" (ecx) - : "d" (edx), "0" (esi), "1" (ecx)); - } - else { - if (size == 4) - asm volatile ("cld; rep; outsl" - : "=S" (esi), "=c" (ecx) - : "d" (edx), "0" (esi), "1" (ecx)); - else if (size == 2) - asm volatile ("cld; rep; outsw" - : "=S" (esi), "=c" (ecx) - : "d" (edx), "0" (esi), "1" (ecx)); - else - asm volatile ("cld; rep; outsb" - : "=S" (esi), "=c" (ecx) - : "d" (edx), "0" (esi), "1" (ecx)); - } - - esi -= (unsigned int)context.vm.regs.ds << 4; - context.vm.regs.esi &= 0xffff0000; - context.vm.regs.esi |= esi & 0xffff; - context.vm.regs.ecx &= 0xffff0000; - context.vm.regs.ecx |= ecx & 0xffff; -} - -static int emulate(void) -{ - unsigned char *insn; - struct { - unsigned int size : 1; - unsigned int rep : 1; - } prefix = { 0, 0 }; - int i = 0; - - insn = (unsigned char *)((unsigned int)context.vm.regs.cs << 4); - insn += context.vm.regs.eip; - - while (1) { -#ifdef TRACE_IO - traceAddr = ((ulong)context.vm.regs.cs << 16) + context.vm.regs.eip + i; -#endif - if (insn[i] == 0x66) { - prefix.size = 1 - prefix.size; - i++; - } - else if (insn[i] == 0xf3) { - prefix.rep = 1; - i++; - } - else if (insn[i] == 0xf0 || insn[i] == 0xf2 - || insn[i] == 0x26 || insn[i] == 0x2e - || insn[i] == 0x36 || insn[i] == 0x3e - || insn[i] == 0x64 || insn[i] == 0x65 - || insn[i] == 0x67) { - /* these prefixes are just ignored */ - i++; - } - else if (insn[i] == 0x6c) { - if (prefix.rep) - em_rep_ins(1); - else - em_ins(1); - i++; - break; - } - else if (insn[i] == 0x6d) { - if (prefix.rep) { - if (prefix.size) - em_rep_ins(4); - else - em_rep_ins(2); - } - else { - if (prefix.size) - em_ins(4); - else - em_ins(2); - } - i++; - break; - } - else if (insn[i] == 0x6e) { - if (prefix.rep) - em_rep_outs(1); - else - em_outs(1); - i++; - break; - } - else if (insn[i] == 0x6f) { - if (prefix.rep) { - if (prefix.size) - em_rep_outs(4); - else - em_rep_outs(2); - } - else { - if (prefix.size) - em_outs(4); - else - em_outs(2); - } - i++; - break; - } - else if (insn[i] == 0xec) { - *((uchar*)&context.vm.regs.eax) = port_in(context.vm.regs.edx); - i++; - break; - } - else if (insn[i] == 0xed) { - if (prefix.size) - *((ulong*)&context.vm.regs.eax) = port_inl(context.vm.regs.edx); - else - *((ushort*)&context.vm.regs.eax) = port_inw(context.vm.regs.edx); - i++; - break; - } - else if (insn[i] == 0xee) { - port_out(context.vm.regs.eax,context.vm.regs.edx); - i++; - break; - } - else if (insn[i] == 0xef) { - if (prefix.size) - port_outl(context.vm.regs.eax,context.vm.regs.edx); - else - port_outw(context.vm.regs.eax,context.vm.regs.edx); - i++; - break; - } - else - return 0; - } - - context.vm.regs.eip += i; - return 1; -} - -static void debug_info(int vret) -{ - int i; - unsigned char *p; - - fputs("vm86() failed\n", stderr); - fprintf(stderr, "return = 0x%x\n", vret); - fprintf(stderr, "eax = 0x%08lx\n", context.vm.regs.eax); - fprintf(stderr, "ebx = 0x%08lx\n", context.vm.regs.ebx); - fprintf(stderr, "ecx = 0x%08lx\n", context.vm.regs.ecx); - fprintf(stderr, "edx = 0x%08lx\n", context.vm.regs.edx); - fprintf(stderr, "esi = 0x%08lx\n", context.vm.regs.esi); - fprintf(stderr, "edi = 0x%08lx\n", context.vm.regs.edi); - fprintf(stderr, "ebp = 0x%08lx\n", context.vm.regs.ebp); - fprintf(stderr, "eip = 0x%08lx\n", context.vm.regs.eip); - fprintf(stderr, "cs = 0x%04x\n", context.vm.regs.cs); - fprintf(stderr, "esp = 0x%08lx\n", context.vm.regs.esp); - fprintf(stderr, "ss = 0x%04x\n", context.vm.regs.ss); - fprintf(stderr, "ds = 0x%04x\n", context.vm.regs.ds); - fprintf(stderr, "es = 0x%04x\n", context.vm.regs.es); - fprintf(stderr, "fs = 0x%04x\n", context.vm.regs.fs); - fprintf(stderr, "gs = 0x%04x\n", context.vm.regs.gs); - fprintf(stderr, "eflags = 0x%08lx\n", context.vm.regs.eflags); - fputs("cs:ip = [ ", stderr); - p = (unsigned char *)((context.vm.regs.cs << 4) + (context.vm.regs.eip & 0xffff)); - for (i = 0; i < 16; ++i) - fprintf(stderr, "%02x ", (unsigned int)p[i]); - fputs("]\n", stderr); - fflush(stderr); -} - -static int run_vm86(void) -{ - unsigned int vret; - - for (;;) { - vret = vm86(&context.vm); - if (VM86_TYPE(vret) == VM86_INTx) { - unsigned int v = VM86_ARG(vret); - if (v == RETURN_TO_32_INT) - return 1; - pushw(context.vm.regs.eflags); - pushw(context.vm.regs.cs); - pushw(context.vm.regs.eip); - context.vm.regs.cs = get_int_seg(v); - context.vm.regs.eip = get_int_off(v); - context.vm.regs.eflags &= ~(VIF_MASK | TF_MASK); - continue; - } - if (VM86_TYPE(vret) != VM86_UNKNOWN) - break; - if (!emulate()) - break; - } - debug_info(vret); - return 0; -} - -#define IND(ereg) context.vm.regs.ereg = regs->ereg -#define OUTD(ereg) regs->ereg = context.vm.regs.ereg - -void PMAPI DPMI_int86(int intno, DPMI_regs *regs) -{ - if (!inited) - PM_init(); - memset(&context.vm.regs, 0, sizeof(context.vm.regs)); - IND(eax); IND(ebx); IND(ecx); IND(edx); IND(esi); IND(edi); - context.vm.regs.eflags = DEFAULT_VM86_FLAGS; - context.vm.regs.cs = get_int_seg(intno); - context.vm.regs.eip = get_int_off(intno); - context.vm.regs.ss = context.stack_seg; - context.vm.regs.esp = context.stack_off; - pushw(DEFAULT_VM86_FLAGS); - pushw(context.ret_seg); - pushw(context.ret_off); - run_vm86(); - OUTD(eax); OUTD(ebx); OUTD(ecx); OUTD(edx); OUTD(esi); OUTD(edi); - regs->flags = context.vm.regs.eflags; -} - -#define IN(ereg) context.vm.regs.ereg = in->e.ereg -#define OUT(ereg) out->e.ereg = context.vm.regs.ereg - -int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) -{ - if (!inited) - PM_init(); - memset(&context.vm.regs, 0, sizeof(context.vm.regs)); - IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); - context.vm.regs.eflags = DEFAULT_VM86_FLAGS; - context.vm.regs.cs = get_int_seg(intno); - context.vm.regs.eip = get_int_off(intno); - context.vm.regs.ss = context.stack_seg; - context.vm.regs.esp = context.stack_off; - pushw(DEFAULT_VM86_FLAGS); - pushw(context.ret_seg); - pushw(context.ret_off); - run_vm86(); - OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); - out->x.cflag = context.vm.regs.eflags & 1; - return out->x.ax; -} - -int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, - RMSREGS *sregs) -{ - if (!inited) - PM_init(); - if (intno == 0x21) { - time_t today = time(NULL); - struct tm *t; - t = localtime(&today); - out->x.cx = t->tm_year + 1900; - out->h.dh = t->tm_mon + 1; - out->h.dl = t->tm_mday; - } - else { - unsigned int seg, off; - seg = get_int_seg(intno); - off = get_int_off(intno); - memset(&context.vm.regs, 0, sizeof(context.vm.regs)); - IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); - context.vm.regs.eflags = DEFAULT_VM86_FLAGS; - context.vm.regs.cs = seg; - context.vm.regs.eip = off; - context.vm.regs.es = sregs->es; - context.vm.regs.ds = sregs->ds; - context.vm.regs.fs = sregs->fs; - context.vm.regs.gs = sregs->gs; - context.vm.regs.ss = context.stack_seg; - context.vm.regs.esp = context.stack_off; - pushw(DEFAULT_VM86_FLAGS); - pushw(context.ret_seg); - pushw(context.ret_off); - run_vm86(); - OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); - sregs->es = context.vm.regs.es; - sregs->ds = context.vm.regs.ds; - sregs->fs = context.vm.regs.fs; - sregs->gs = context.vm.regs.gs; - out->x.cflag = context.vm.regs.eflags & 1; - } - return out->e.eax; -} - -#define OUTR(ereg) in->e.ereg = context.vm.regs.ereg - -void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, - RMSREGS *sregs) -{ - if (!inited) - PM_init(); - memset(&context.vm.regs, 0, sizeof(context.vm.regs)); - IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); - context.vm.regs.eflags = DEFAULT_VM86_FLAGS; - context.vm.regs.cs = seg; - context.vm.regs.eip = off; - context.vm.regs.ss = context.stack_seg; - context.vm.regs.esp = context.stack_off; - context.vm.regs.es = sregs->es; - context.vm.regs.ds = sregs->ds; - context.vm.regs.fs = sregs->fs; - context.vm.regs.gs = sregs->gs; - pushw(DEFAULT_VM86_FLAGS); - pushw(context.ret_seg); - pushw(context.ret_off); - run_vm86(); - OUTR(eax); OUTR(ebx); OUTR(ecx); OUTR(edx); OUTR(esi); OUTR(edi); - sregs->es = context.vm.regs.es; - sregs->ds = context.vm.regs.ds; - sregs->fs = context.vm.regs.fs; - sregs->gs = context.vm.regs.gs; - in->x.cflag = context.vm.regs.eflags & 1; -} - -void PMAPI PM_availableMemory(ulong *physical,ulong *total) -{ - FILE *mem = fopen("/proc/meminfo","r"); - char buf[1024]; - - fgets(buf,1024,mem); - fgets(buf,1024,mem); - sscanf(buf,"Mem: %*d %*d %ld", physical); - fgets(buf,1024,mem); - sscanf(buf,"Swap: %*d %*d %ld", total); - fclose(mem); - *total += *physical; -} - -void * PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16M) -{ - /* TODO: Implement this for Linux */ - return NULL; -} - -void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) -{ - /* TODO: Implement this for Linux */ -} - -void * PMAPI PM_allocPage( - ibool locked) -{ - /* TODO: Implement this for Linux */ - return NULL; -} - -void PMAPI PM_freePage( - void *p) -{ - /* TODO: Implement this for Linux */ -} - -void PMAPI PM_setBankA(int bank) -{ - if (!inited) - PM_init(); - memset(&context.vm.regs, 0, sizeof(context.vm.regs)); - context.vm.regs.eax = 0x4F05; - context.vm.regs.ebx = 0x0000; - context.vm.regs.edx = bank; - context.vm.regs.eflags = DEFAULT_VM86_FLAGS; - context.vm.regs.cs = get_int_seg(0x10); - context.vm.regs.eip = get_int_off(0x10); - context.vm.regs.ss = context.stack_seg; - context.vm.regs.esp = context.stack_off; - pushw(DEFAULT_VM86_FLAGS); - pushw(context.ret_seg); - pushw(context.ret_off); - run_vm86(); -} - -void PMAPI PM_setBankAB(int bank) -{ - if (!inited) - PM_init(); - memset(&context.vm.regs, 0, sizeof(context.vm.regs)); - context.vm.regs.eax = 0x4F05; - context.vm.regs.ebx = 0x0000; - context.vm.regs.edx = bank; - context.vm.regs.eflags = DEFAULT_VM86_FLAGS; - context.vm.regs.cs = get_int_seg(0x10); - context.vm.regs.eip = get_int_off(0x10); - context.vm.regs.ss = context.stack_seg; - context.vm.regs.esp = context.stack_off; - pushw(DEFAULT_VM86_FLAGS); - pushw(context.ret_seg); - pushw(context.ret_off); - run_vm86(); - context.vm.regs.eax = 0x4F05; - context.vm.regs.ebx = 0x0001; - context.vm.regs.edx = bank; - context.vm.regs.eflags = DEFAULT_VM86_FLAGS; - context.vm.regs.cs = get_int_seg(0x10); - context.vm.regs.eip = get_int_off(0x10); - context.vm.regs.ss = context.stack_seg; - context.vm.regs.esp = context.stack_off; - pushw(DEFAULT_VM86_FLAGS); - pushw(context.ret_seg); - pushw(context.ret_off); - run_vm86(); -} - -void PMAPI PM_setCRTStart(int x,int y,int waitVRT) -{ - if (!inited) - PM_init(); - memset(&context.vm.regs, 0, sizeof(context.vm.regs)); - context.vm.regs.eax = 0x4F07; - context.vm.regs.ebx = waitVRT; - context.vm.regs.ecx = x; - context.vm.regs.edx = y; - context.vm.regs.eflags = DEFAULT_VM86_FLAGS; - context.vm.regs.cs = get_int_seg(0x10); - context.vm.regs.eip = get_int_off(0x10); - context.vm.regs.ss = context.stack_seg; - context.vm.regs.esp = context.stack_off; - pushw(DEFAULT_VM86_FLAGS); - pushw(context.ret_seg); - pushw(context.ret_off); - run_vm86(); -} - -int PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type) -{ -#ifdef ENABLE_MTRR - struct mtrr_sentry sentry; - - if (mtrr_fd < 0) - return PM_MTRR_ERR_NO_OS_SUPPORT; - sentry.base = base; - sentry.size = length; - sentry.type = type; - if (ioctl(mtrr_fd, MTRRIOC_ADD_ENTRY, &sentry) == -1) { - /* TODO: Need to decode MTRR error codes!! */ - return PM_MTRR_NOT_SUPPORTED; - } - return PM_MTRR_ERR_OK; -#else - return PM_MTRR_ERR_NO_OS_SUPPORT; -#endif -} - -/**************************************************************************** -PARAMETERS: -callback - Function to callback with write combine information - -REMARKS: -Function to enumerate all write combine regions currently enabled for the -processor. -****************************************************************************/ -int PMAPI PM_enumWriteCombine( - PM_enumWriteCombine_t callback) -{ -#ifdef ENABLE_MTRR - struct mtrr_gentry gentry; - - if (mtrr_fd < 0) - return PM_MTRR_ERR_NO_OS_SUPPORT; - - for (gentry.regnum = 0; ioctl (mtrr_fd, MTRRIOC_GET_ENTRY, &gentry) == 0; - ++gentry.regnum) { - if (gentry.size > 0) { - /* WARNING: This code assumes that the types in pmapi.h match the ones */ - /* in the Linux kernel (mtrr.h) */ - callback(gentry.base, gentry.size, gentry.type); - } - } - - return PM_MTRR_ERR_OK; -#else - return PM_MTRR_ERR_NO_OS_SUPPORT; -#endif -} - -ibool PMAPI PM_doBIOSPOST( - ushort axVal, - ulong BIOSPhysAddr, - void *copyOfBIOS, - ulong BIOSLen) -{ - char *bios_ptr = (char*)0xC0000; - char *old_bios; - ulong Current10, Current6D, *rvec = 0; - RMREGS regs; - RMSREGS sregs; - - /* The BIOS is mapped to 0xC0000 with a private memory mapping enabled - * which means we have a copy on write scheme. Hence we simply copy - * the secondary BIOS image over the top of the old one. - */ - if (!inited) - PM_init(); - if ((old_bios = PM_malloc(BIOSLen)) == NULL) - return false; - if (BIOSPhysAddr != 0xC0000) { - memcpy(old_bios,bios_ptr,BIOSLen); - memcpy(bios_ptr,copyOfBIOS,BIOSLen); - } - - /* The interrupt vectors should already be mmap()'ed from 0-0x400 in PM_init */ - Current10 = rvec[0x10]; - Current6D = rvec[0x6D]; - - /* POST the secondary BIOS */ - rvec[0x10] = rvec[0x42]; /* Restore int 10h to STD-BIOS */ - regs.x.ax = axVal; - PM_callRealMode(0xC000,0x0003,®s,&sregs); - - /* Restore interrupt vectors */ - rvec[0x10] = Current10; - rvec[0x6D] = Current6D; - - /* Restore original BIOS image */ - if (BIOSPhysAddr != 0xC0000) - memcpy(bios_ptr,old_bios,BIOSLen); - PM_free(old_bios); - return true; -} - -int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - p = p; len = len; - return 1; -} - -int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - p = p; len = len; - return 1; -} - -int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - p = p; len = len; - return 1; -} - -int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - p = p; len = len; - return 1; -} - -PM_MODULE PMAPI PM_loadLibrary( - const char *szDLLName) -{ - /* TODO: Implement this to load shared libraries! */ - (void)szDLLName; - return NULL; -} - -void * PMAPI PM_getProcAddress( - PM_MODULE hModule, - const char *szProcName) -{ - /* TODO: Implement this! */ - (void)hModule; - (void)szProcName; - return NULL; -} - -void PMAPI PM_freeLibrary( - PM_MODULE hModule) -{ - /* TODO: Implement this! */ - (void)hModule; -} - -int PMAPI PM_setIOPL( - int level) -{ - /* TODO: Move the IOPL switching into this function!! */ - return level; -} - -void PMAPI PM_flushTLB(void) -{ - /* Do nothing on Linux. */ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c deleted file mode 100644 index 579ef2c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Dummy module; no virtual framebuffer for this OS -* -****************************************************************************/ - -#include "pmapi.h" - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -{ - baseAddr = baseAddr; - bankSize = bankSize; - codeLen = codeLen; - bankFunc = bankFunc; - return NULL; -} - -void PMAPI VF_exit(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c deleted file mode 100644 index 1b9bae2..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Linux -* -* Description: Linux specific implementation for the Zen Timer functions. -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -void __ZTimerInit(void) -{ -} - -/**************************************************************************** -REMARKS: -Use the gettimeofday() function to get microsecond precision (probably less -though) -****************************************************************************/ -static inline ulong __ULZReadTime(void) -{ - struct timeval t; - gettimeofday(&t, NULL); - return t.tv_sec*1000000 + t.tv_usec; -} - -/**************************************************************************** -REMARKS: -Start the Zen Timer counting. -****************************************************************************/ -#define __LZTimerOn(tm) tm->start.low = __ULZReadTime() - -/**************************************************************************** -REMARKS: -Compute the lap time since the timer was started. -****************************************************************************/ -#define __LZTimerLap(tm) (__ULZReadTime() - tm->start.low) - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerOff(tm) tm->end.low = __ULZReadTime() - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerCount(tm) (tm->end.low - tm->start.low) - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as microseconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION 1 - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong __ULZElapsedTime(ulong start,ulong finish) -{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/makefile b/board/MAI/bios_emulator/scitech/src/pm/makefile deleted file mode 100644 index 265f0e3..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/makefile +++ /dev/null @@ -1,290 +0,0 @@ -############################################################################# -# -# Copyright (C) 1996 SciTech Software. -# All rights reserved. -# -# Descripton: Generic makefile for the PM library. Builds the library -# file and all test programs. -# -############################################################################# - -.IMPORT .IGNORE : DEBUG_AGP_DRIVER TEST_HARNESS DEBUG_SDDPMI - -#---------------------------------------------------------------------------- -# Add DOS extender dependant flags to command line -#---------------------------------------------------------------------------- - -CFLAGS += $(DX_CFLAGS) -ASFLAGS += $(DX_ASFLAGS) -NO_PMLIB := 1 - -#---------------------------------------------------------------------------- -# Include definitions specific for the target system -#---------------------------------------------------------------------------- - -.IF $(USE_VXD) - -# Building for Win32 VxD (minimal PM library implementation) - -LIBNAME = pm -OBJECTS = pm$O vflat$O ztimer$O cpuinfo$O mtrr$O fileio$O pcilib$O \ - agp$O malloc$O vgastate$O gavxd$O _pm$O _mtrr$O _cpuinfo$O \ - _int64$O _pcihelp$O -DEPEND_SRC := vxd;common;codepage;tests -.SOURCE: vxd common codepage tests - -.ELIF $(USE_NTDRV) - -# Building for NT device drivers (minimal PM library implementation) - -LIBNAME = pm -OBJECTS = pm$O vflat$O ztimer$O cpuinfo$O mtrr$O mem$O irq$O int86$O \ - stdio$O stdlib$O pcilib$O agp$O malloc$O vgastate$O gantdrv$O \ - _pm$O _mtrr$O _cpuinfo$O _int64$O _pcihelp$O _irq$O -DEPEND_SRC := ntdrv;common;codepage;tests -.SOURCE: ntdrv common codepage tests - -.ELIF $(USE_WIN32) - -# Building for Win32 - -CFLAGS += -DUSE_OS_JOYSTICK -LIBNAME = pm -OBJECTS = pm$O vflat$O event$O ddraw$O ztimer$O cpuinfo$O pcilib$O \ - agp$O malloc$O vgastate$O gawin32$O ntservc$O _joy$O _cpuinfo$O \ - _int64$O _pcihelp$O -DEPEND_SRC := win32;common;codepage;tests -.SOURCE: win32 common codepage tests - -.ELIF $(USE_OS232) - -# Building for OS/2 - -.IF $(USE_OS2GUI) -LIBNAME = pm_pm -.ELSE -LIBNAME = pm -.ENDIF -OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ - agp$O malloc$O vgastate$O gaos2$O _pmos2$O _joy$O _cpuinfo$O \ - _int64$O _pcihelp$O dossctl$O -DEPEND_SRC := os2;common;codepage;tests -.SOURCE: os2 common codepage tests - -.ELIF $(USE_QNX) - -# Building for QNX - -USE_BIOS := 1 -.IF $(USE_PHOTON) -LIBNAME = pm_ph -.ELIF $(USE_X11) -LIBNAME = pm_x11 -.ELSE -LIBNAME = pm -.ENDIF -OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ - agp$O malloc$O mtrrqnx$O unixio$O vgastate$O gaqnx$O _joy$O \ - _mtrrqnx$O _cpuinfo$O _int64$O _pcihelp$O -DEPEND_SRC := qnx;common;codepage;tests -.SOURCE: qnx common codepage tests - -# Indicate that this program uses Nucleus device drivers (so needs I/O access) -USE_NUCLEUS := 1 - -.ELIF $(USE_LINUX) - -# Building for Linux - -CFLAGS += -DENABLE_MTRR -DUSE_OS_JOYSTICK -.IF $(USE_X11) -LIBNAME = pm_x11 -.ELSE -LIBNAME = pm -.ENDIF -OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O pcilib$O \ - agp$O malloc$O unixio$O vgastate$O galinux$O _cpuinfo$O \ - _int64$O _pcihelp$O -DEPEND_SRC := linux;common;codepage;tests;x11 -.SOURCE: linux common codepage tests x11 - -# Building a shared library -.IF $(SOFILE) -LIB := ld -LIBFLAGS := -r -o -CFLAGS += -fPIC -.ENDIF - -.ELIF $(USE_BEOS) - -# Building for BeOS GUI - -LIBNAME = pm -OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O pcilib$O \ - agp$O malloc$O vgastate$O gabeos$O _joy$O _cpuinfo$O \ - _int64$O _pcihelp$O -DEPEND_SRC := beos;common;codepage;tests -.SOURCE: beos common codepage tests - -.ELIF $(USE_SMX32) - -# Building for SMX - -LIBNAME = pm -OBJECTS = pm$O pmsmx$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ - agp$O malloc$O vgastate$O gasmx$O _pm$O _pmsmx$O _mtrr$O _event$O \ - _joy$O _cpuinfo$O _int64$O _pcihelp$O _lztimer$O -DEPEND_SRC := smx;common;codepage;tests -.SOURCE: smx common codepage tests - -.ELIF $(USE_RTTARGET) - -# Building for RTTarget-32 - -LIBNAME = pm -OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ - agp$O malloc$O vgastate$O gartt$O _mtrr$O _joy$O _cpuinfo$O \ - _int64$O _pcihelp$O -DEPEND_SRC := rttarget;common;codepage;tests -.SOURCE: rttarget common codepage tests - -.ELSE - -# Building for MSDOS - -LIBNAME = pm -OBJECTS = pm$O pmdos$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O \ - agp$O malloc$O pcilib$O vgastate$O gados$O \ - _pm$O _pmdos$O _mtrr$O _vflat$O _event$O _joy$O _pcihelp$O \ - _cpuinfo$O _int64$O _lztimer$O _dma$O -DEPEND_SRC := dos;common;codepage;tests -.SOURCE: dos common codepage tests - -.ENDIF - -# Object modules for keyboard code pages - -OBJECTS += us_eng$O - -# Common object modules - -OBJECTS += common$O -.IF $(CHECKED) -OBJECTS += debug$O -.ENDIF - -# Nucleus loader library object modules. Note that when compiling a test harness -# library we need to exclude the Nucleus loader library. - -.IF $(TEST_HARNESS) -CFLAGS += -DTEST_HARNESS -DPMLIB -LIBNAME = pm_test -.ELSE -OBJECTS += galib$O _ga_imp$O -.ENDIF - -.IF $(DEBUG_SDDPMI) -CFLAGS += -DDEBUG_SDDPMI -.ENDIF - -# AGP library object modules - -.IF $(DEBUG_AGP_DRIVER) -CFLAGS += -DDEBUG_AGP_DRIVER -OBJECTS += agplib$O -.ELSE -OBJECTS += agplib$O peloader$O libcimp$O _gatimer$O -.ENDIF - -#---------------------------------------------------------------------------- -# Name of library and generic object files required to build it -#---------------------------------------------------------------------------- - -.IF $(STKCALL) -LIBFILE = s$(LP)$(LIBNAME)$L -.ELSE -LIBFILE = $(LP)$(LIBNAME)$L -.ENDIF -LIBCLEAN = *.lib *.a - -#---------------------------------------------------------------------------- -# Change destination for library file depending the extender being used. This -# is only necessary for DOS extender since the file go into a subdirectory -# in the normal library directory, one for each supported extender. Other -# OS'es put the file into the regular library directory, since there is -# only one per OS in this case. -#---------------------------------------------------------------------------- - -MK_PMODE = 1 - -.IF $(TEST_HARNESS) -LIB_DEST := $(LIB_BASE) -.ELIF $(USE_TNT) -LIB_DEST := $(LIB_BASE)\tnt -.ELIF $(USE_DOS4GW) -LIB_DEST := $(LIB_BASE)\dos4gw -.ELIF $(USE_X32) -LIB_DEST := $(LIB_BASE)\x32 -.ELIF $(USE_DPMI16) -LIB_DEST := $(LIB_BASE)\dpmi16 -.ELIF $(USE_DPMI32) -LIB_DEST := $(LIB_BASE)\dpmi32 -.ELIF $(USE_DOSX) -LIB_DEST := $(LIB_BASE)\dosx -.END - -#---------------------------------------------------------------------------- -# Names of all executable files built -#---------------------------------------------------------------------------- - -.IF $(USE_REALDOS) -EXEFILES = memtest$E biosptr$E video$E isvesa$E callreal$E \ - mouse$E tick$E key$E key15$E brk$E altbrk$E \ - critical$E altcrit$E vftest$E rtc$E getch$E \ - cpu$E timerc$E timercpp$E showpci$E uswc$E block$E -.ELSE -EXEFILES = memtest$E video$E isvesa$E callreal$E vftest$E getch$E \ - cpu$E timerc$E timercpp$E showpci$E uswc$E block$E \ - save$E restore$E -.ENDIF - -all: $(EXEFILES) - -$(EXEFILES): $(LIBFILE) - -memtest$E: memtest$O -biosptr$E: biosptr$O -video$E: video$O -isvesa$E: isvesa$O -mouse$E: mouse$O -tick$E: tick$O -key$E: key$O -key15$E: key15$O -brk$E: brk$O -altbrk$E: altbrk$O -critical$E: critical$O -altcrit$E: altcrit$O -callreal$E: callreal$O -vftest$E: vftest$O -rtc$E: rtc$O -getch$E: getch$O -cpu$E: cpu$O -timerc$E: timerc$O -timercpp$E: timercpp$O -showpci$E: showpci$O -uswc$E: uswc$O -block$E: block$O -save$E: save$O -restore$E: restore$O -test$E: test$O _test$O - -#---------------------------------------------------------------------------- -# Define the list of object files to create dependency information for -#---------------------------------------------------------------------------- - -DEPEND_OBJ := $(OBJECTS) memtest$O biosptr$O video$O isvesa$O mouse$O \ - tick$O key$O key$O brk$O altbrk$O critical$O altcrit$O \ - callreal$O vftest$O getch$O timercpp$O - -.INCLUDE: "$(SCITECH)/makedefs/common.mk" - diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm deleted file mode 100644 index 11824a0..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm +++ /dev/null @@ -1,288 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: 32-bit Windows NT device driver -;* -;* Description: Low level assembly support for the PM library specific to -;* Windows NT device drivers. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _irq ; Set up memory model - -begdataseg _irq - - cextern _PM_rtcHandler,CPTR - cextern _PM_prevRTC,FCPTR - -RtcInside dw 0 ; Are we still handling current interrupt -sidtBuf df 0 ; Buffer for sidt instruction - -enddataseg _irq - -begcodeseg _irq ; Start of code segment - -cpublic _PM_irqCodeStart - -; Macro to delay briefly to ensure that enough time has elapsed between -; successive I/O accesses so that the device being accessed can respond -; to both accesses even on a very fast PC. - -ifdef USE_NASM -%macro DELAY 0 - jmp short $+2 - jmp short $+2 - jmp short $+2 -%endmacro -%macro IODELAYN 1 -%rep %1 - DELAY -%endrep -%endmacro -else -macro DELAY - jmp short $+2 - jmp short $+2 - jmp short $+2 -endm -macro IODELAYN N - rept N - DELAY - endm -endm -endif - -;---------------------------------------------------------------------------- -; PM_rtcISR - Real time clock interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Hardware interrupt handler for the timer interrupt, to dispatch control -; to high level C based subroutines. We save the state of all registers -; in this routine, and switch to a local stack. Interrupts are *off* -; when we call the user code. -; -; NOTE: This routine switches to a local stack before calling any C code, -; and hence is _not_ re-entrant. Make sure your C code executes as -; quickly as possible, since a timer overrun will simply hang the -; system. -;---------------------------------------------------------------------------- -cprocfar _PM_rtcISR - -;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -; If we enable interrupts and call into any C based interrupt handling code, -; we need to setup a bunch of important information for the NT kernel. The -; code below takes care of this housekeeping for us (see Undocumented NT for -; details). If we don't do this housekeeping and interrupts are enabled, -; the kernel will become very unstable and crash within 10 seconds or so. -;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - - pushad - pushfd - push fs - - mov ebx,00000030h - mov fs,bx - sub esp,50h - mov ebp,esp - -; Setup the exception frame to NULL - - mov ebx,[DWORD cs:0FFDFF000h] - mov [DWORD ds:0FFDFF000h], 0FFFFFFFFh - mov [DWORD ebp],ebx - -; Save away the existing KSS ebp - - mov esi,[DWORD cs:0FFDFF124h] - mov ebx,[DWORD esi+00000128h] - mov [DWORD ebp+4h],ebx - mov [DWORD esi+00000128h],ebp - -; Save away the kernel time and the thread mode (kernel/user) - - mov edi,[DWORD esi+00000137h] - mov [DWORD ebp+8h],edi - -; Set the thread mode (kernel/user) based on the code selector - - mov ebx,[DWORD ebp+7Ch] - and ebx,01 - mov [BYTE esi+00000137h],bl - -;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -; End of special interrupt Prolog code -;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -; Clear priority interrupt controller and re-enable interrupts so we -; dont lock things up for long. - - mov al,20h - out 0A0h,al - out 020h,al - -; Clear real-time clock timeout - - in al,70h ; Read CMOS index register - push eax ; and save for later - IODELAYN 3 - mov al,0Ch - out 70h,al - IODELAYN 5 - in al,71h - -; Call the C interrupt handler function - - cmp [BYTE RtcInside],1 ; Check for mutual exclusion - je @@Exit - mov [BYTE RtcInside],1 - sti ; Enable interrupts - cld ; Clear direction flag for C code - call [CPTR _PM_rtcHandler] - cli ; Disable interrupts on exit! - mov [BYTE RtcInside],0 - -@@Exit: pop eax - out 70h,al ; Restore CMOS index register - -;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -; Start of special epilog code to restore stuff on exit from handler -;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -; Restore the KSS ebp - - mov esi,[DWORD cs:0FFDFF124h] - mov ebx,[DWORD ebp+4] - mov [DWORD esi+00000128h],ebx - -; Restore the exception frame - - mov ebx,[DWORD ebp] - mov [DWORD fs:00000000],ebx - -; Restore the thread mode - - mov ebx,[DWORD ebp+8h] - mov esi,[DWORD fs:00000124h] - mov [BYTE esi+00000137h],bl - add esp, 50h - pop fs - popfd - popad - -; Return from interrupt - - iret - -cprocend - -cpublic _PM_irqCodeEnd - -;---------------------------------------------------------------------------- -; void _PM_getISR(int irq,PMFARPTR *handler); -;---------------------------------------------------------------------------- -; Function to return the specific IRQ handler direct from the IDT. -;---------------------------------------------------------------------------- -cprocstart _PM_getISR - - ARG idtEntry:UINT, handler:DPTR - - enter_c 0 - mov ecx,[handler] ; Get address of handler to fill in - sidt [sidtBuf] ; Get IDTR register into sidtBuf - mov eax,[DWORD sidtBuf+2] ; Get address of IDT into EAX - mov ebx,[idtEntry] - lea eax,[eax+ebx*8] ; Get entry in the IDT - movzx edx,[WORD eax+6] ; Get high order 16-bits - shl edx,16 ; Move into top 16-bits of address - mov dx,[WORD eax] ; Get low order 16-bits - mov [DWORD ecx],edx ; Store linear address of handler - mov dx,[WORD eax+2] ; Get selector value - mov [WORD ecx+4],dx ; Store selector value - leave_c - ret - -cprocend _PM_getISR - -;---------------------------------------------------------------------------- -; void _PM_setISR(int irq,void *handler); -;---------------------------------------------------------------------------- -; Function to set the specific IRQ handler direct in the IDT. -;---------------------------------------------------------------------------- -cprocstart _PM_setISR - - ARG irq:UINT, handler:CPTR - - enter_c 0 - mov ecx,[handler] ; Get address of new handler - mov dx,cs ; Get selector for new handler - sidt [sidtBuf] ; Get IDTR register into sidtBuf - mov eax,[DWORD sidtBuf+2] ; Get address of IDT into EAX - mov ebx,[idtEntry] - lea eax,[eax+ebx*8] ; Get entry in the IDT - cli - mov [WORD eax+2],dx ; Store code segment selector - mov [WORD eax],cx ; Store low order bits of handler - shr ecx,16 - mov [WORD eax+6],cx ; Store high order bits of handler - sti - leave_c - ret - -cprocend _PM_setISR - -;---------------------------------------------------------------------------- -; void _PM_restoreISR(int irq,PMFARPTR *handler); -;---------------------------------------------------------------------------- -; Function to set the specific IRQ handler direct in the IDT. -;---------------------------------------------------------------------------- -cprocstart _PM_restoreISR - - ARG irq:UINT, handler:CPTR - - enter_c 0 - mov ecx,[handler] - mov dx,[WORD ecx+4] ; Get selector for old handler - mov ecx,[DWORD ecx] ; Get address of old handler - sidt [sidtBuf] ; Get IDTR register into sidtBuf - mov eax,[DWORD sidtBuf+2] ; Get address of IDT into EAX - mov ebx,[idtEntry] - lea eax,[eax+ebx*8] ; Get entry in the IDT - cli - mov [WORD eax+2],dx ; Store code segment selector - mov [WORD eax],cx ; Store low order bits of handler - shr ecx,16 - mov [WORD eax+6],cx ; Store high order bits of handler - sti - leave_c - ret - -cprocend _PM_restoreISR - -endcodeseg _irq - - END ; End of module - diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm deleted file mode 100644 index 6cb276d..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm +++ /dev/null @@ -1,281 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: 32-bit Windows NT device driver -;* -;* Description: Low level assembly support for the PM library specific to -;* Windows NT device drivers. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _pm ; Set up memory model - -P586 - -begdataseg - -; Watcom C++ externals required to link when compiling floating point -; C code. They are not actually used in the code because we compile with -; inline floating point instructions, however the compiler still generates -; the references in the object modules. - -__8087 dd 0 - PUBLIC __8087 -__imthread: -__fltused: -_fltused_ dd 0 - PUBLIC __imthread - PUBLIC _fltused_ - PUBLIC __fltused - -enddataseg - -begcodeseg _pm ; Start of code segment - -;---------------------------------------------------------------------------- -; void PM_segread(PMSREGS *sregs) -;---------------------------------------------------------------------------- -; Read the current value of all segment registers -;---------------------------------------------------------------------------- -cprocstart PM_segread - - ARG sregs:DPTR - - enter_c - - mov ax,es - _les _si,[sregs] - mov [_ES _si],ax - mov [_ES _si+2],cs - mov [_ES _si+4],ss - mov [_ES _si+6],ds - mov [_ES _si+8],fs - mov [_ES _si+10],gs - - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) -;---------------------------------------------------------------------------- -; Issues a software interrupt in protected mode. This routine has been -; written to allow user programs to load CS and DS with different values -; other than the default. -;---------------------------------------------------------------------------- -cprocstart PM_int386x - -; Not used for NT device drivers - - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_setBankA(int bank) -;---------------------------------------------------------------------------- -cprocstart PM_setBankA - -; Not used for NT device drivers - - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_setBankAB(int bank) -;---------------------------------------------------------------------------- -cprocstart PM_setBankAB - -; Not used for NT device drivers - - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_setCRTStart(int x,int y,int waitVRT) -;---------------------------------------------------------------------------- -cprocstart PM_setCRTStart - -; Not used for NT device drivers - - ret - -cprocend - -; Macro to delay briefly to ensure that enough time has elapsed between -; successive I/O accesses so that the device being accessed can respond -; to both accesses even on a very fast PC. - -ifdef USE_NASM -%macro DELAY 0 - jmp short $+2 - jmp short $+2 - jmp short $+2 -%endmacro -%macro IODELAYN 1 -%rep %1 - DELAY -%endrep -%endmacro -else -macro DELAY - jmp short $+2 - jmp short $+2 - jmp short $+2 -endm -macro IODELAYN N - rept N - DELAY - endm -endm -endif - -;---------------------------------------------------------------------------- -; uchar _PM_readCMOS(int index) -;---------------------------------------------------------------------------- -; Read the value of a specific CMOS register. We do this with both -; normal interrupts and NMI disabled. -;---------------------------------------------------------------------------- -cprocstart _PM_readCMOS - - ARG index:UINT - - push _bp - mov _bp,_sp - pushfd - mov al,[BYTE index] - or al,80h ; Add disable NMI flag - cli - out 70h,al - IODELAYN 5 - in al,71h - mov ah,al - xor al,al - IODELAYN 5 - out 70h,al ; Re-enable NMI - mov al,ah ; Return value in AL - popfd - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _PM_writeCMOS(int index,uchar value) -;---------------------------------------------------------------------------- -; Read the value of a specific CMOS register. We do this with both -; normal interrupts and NMI disabled. -;---------------------------------------------------------------------------- -cprocstart _PM_writeCMOS - - ARG index:UINT, value:UCHAR - - push _bp - mov _bp,_sp - pushfd - mov al,[BYTE index] - or al,80h ; Add disable NMI flag - cli - out 70h,al - IODELAYN 5 - mov al,[value] - out 71h,al - xor al,al - IODELAYN 5 - out 70h,al ; Re-enable NMI - popfd - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; double _ftol(double f) -;---------------------------------------------------------------------------- -; Calls to __ftol are generated by the Borland C++ compiler for code -; that needs to convert a floating point type to an integral type. -; -; Input: floating point number on the top of the '87. -; -; Output: a (signed or unsigned) long in EAX -; All other registers preserved. -;----------------------------------------------------------------------- -cprocstart _ftol - - LOCAL temp1:WORD, temp2:QWORD = LocalSize - - push ebp - mov ebp,esp - sub esp,LocalSize - - fstcw [temp1] ; save the control word - fwait - mov al,[BYTE temp1+1] - or [BYTE temp1+1],0Ch ; set rounding control to chop - fldcw [temp1] - fistp [temp2] ; convert to 64-bit integer - mov [BYTE temp1+1],al - fldcw [temp1] ; restore the control word - mov eax,[DWORD temp2] ; return LS 32 bits - mov edx,[DWORD temp2+4] ; MS 32 bits - - mov esp,ebp - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; _PM_getPDB - Return the Page Table Directory Base address -;---------------------------------------------------------------------------- -cprocstart _PM_getPDB - - mov eax,cr3 - and eax,0FFFFF000h - ret - -cprocend - -;---------------------------------------------------------------------------- -; Flush the Translation Lookaside buffer -;---------------------------------------------------------------------------- -cprocstart PM_flushTLB - - wbinvd ; Flush the CPU cache - mov eax,cr3 - mov cr3,eax ; Flush the TLB - ret - -cprocend - -endcodeseg _pm - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c deleted file mode 100644 index d15b07c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows VxD -* -* Description: VxD specific code for the CPU detection module. -* -****************************************************************************/ - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Do nothing for VxD's -****************************************************************************/ -#define SetMaxThreadPriority() 0 - -/**************************************************************************** -REMARKS: -Do nothing for VxD's -****************************************************************************/ -#define RestoreThreadPriority(i) (void)(i) - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - KeQueryPerformanceCounter((LARGE_INTEGER*)freq); -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. -****************************************************************************/ -#define GetCounter(t) \ -{ \ - LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL); \ - (t)->low = lt.LowPart; \ - (t)->high = lt.HighPart; \ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c deleted file mode 100644 index c82648b..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c +++ /dev/null @@ -1,251 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows NT device drivers. -* -* Description: Implementation for the real mode software interrupt -* handling functions. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include "sdd/sddhelp.h" -#include "mtrr.h" -#include "oshdr.h" - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -We do have limited BIOS access under Windows NT device drivers. -****************************************************************************/ -ibool PMAPI PM_haveBIOSAccess(void) -{ - /* Return false unless we have full buffer passing! */ - return false; -} - -/**************************************************************************** -PARAMETERS: -len - Place to store the length of the buffer -rseg - Place to store the real mode segment of the buffer -roff - Place to store the real mode offset of the buffer - -REMARKS: -This function returns the address and length of the global VESA transfer -buffer that is used for communicating with the VESA BIOS functions from -Win16 and Win32 programs under Windows. -****************************************************************************/ -void * PMAPI PM_getVESABuf( - uint *len, - uint *rseg, - uint *roff) -{ - /* No buffers supported under Windows NT (Windows XP has them however if */ - /* we ever decide to support this!) */ - return NULL; -} - -/**************************************************************************** -REMARKS: -Issue a protected mode software interrupt. -****************************************************************************/ -int PMAPI PM_int386( - int intno, - PMREGS *in, - PMREGS *out) -{ - PMSREGS sregs; - PM_segread(&sregs); - return PM_int386x(intno,in,out,&sregs); -} - -/**************************************************************************** -REMARKS: -Map a real mode pointer to a protected mode pointer. -****************************************************************************/ -void * PMAPI PM_mapRealPointer( - uint r_seg, - uint r_off) -{ - /* Not used for Windows NT drivers! */ - return NULL; -} - -/**************************************************************************** -REMARKS: -Allocate a block of real mode memory -****************************************************************************/ -void * PMAPI PM_allocRealSeg( - uint size, - uint *r_seg, - uint *r_off) -{ - /* Not supported in NT drivers */ - (void)size; - (void)r_seg; - (void)r_off; - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a block of real mode memory. -****************************************************************************/ -void PMAPI PM_freeRealSeg( - void *mem) -{ - /* Not supported in NT drivers */ - (void)mem; -} - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt (parameters in DPMI compatible structure) -****************************************************************************/ -void PMAPI DPMI_int86( - int intno, - DPMI_regs *regs) -{ - /* Not used in NT drivers */ -} - -/**************************************************************************** -REMARKS: -Call a V86 real mode function with the specified register values -loaded before the call. The call returns with a far ret. -****************************************************************************/ -void PMAPI PM_callRealMode( - uint seg, - uint off, - RMREGS *regs, - RMSREGS *sregs) -{ - /* TODO!! */ -#if 0 - CLIENT_STRUCT saveRegs; - - /* Bail if we do not have BIOS access (ie: the VxD was dynamically - * loaded, and not statically loaded. - */ - if (!_PM_haveBIOS) - return; - - TRACE("SDDHELP: Entering PM_callRealMode()\n"); - Begin_Nest_V86_Exec(); - LoadV86Registers(&saveRegs,regs,sregs); - Simulate_Far_Call(seg, off); - Resume_Exec(); - ReadV86Registers(&saveRegs,regs,sregs); - End_Nest_Exec(); - TRACE("SDDHELP: Exiting PM_callRealMode()\n"); -#endif -} - -/**************************************************************************** -REMARKS: -Issue a V86 real mode interrupt with the specified register values -loaded before the interrupt. -****************************************************************************/ -int PMAPI PM_int86( - int intno, - RMREGS *in, - RMREGS *out) -{ - /* TODO!! */ -#if 0 - RMSREGS sregs = {0}; - CLIENT_STRUCT saveRegs; - ushort oldDisable; - - /* Disable pass-up to our VxD handler so we directly call BIOS */ - TRACE("SDDHELP: Entering PM_int86()\n"); - if (disableTSRFlag) { - oldDisable = *disableTSRFlag; - *disableTSRFlag = 0; - } - Begin_Nest_V86_Exec(); - LoadV86Registers(&saveRegs,in,&sregs); - Exec_Int(intno); - ReadV86Registers(&saveRegs,out,&sregs); - End_Nest_Exec(); - - /* Re-enable pass-up to our VxD handler if previously enabled */ - if (disableTSRFlag) - *disableTSRFlag = oldDisable; - - TRACE("SDDHELP: Exiting PM_int86()\n"); -#else - *out = *in; -#endif - return out->x.ax; -} - -/**************************************************************************** -REMARKS: -Issue a V86 real mode interrupt with the specified register values -loaded before the interrupt. -****************************************************************************/ -int PMAPI PM_int86x( - int intno, - RMREGS *in, - RMREGS *out, - RMSREGS *sregs) -{ - /* TODO!! */ -#if 0 - CLIENT_STRUCT saveRegs; - ushort oldDisable; - - /* Bail if we do not have BIOS access (ie: the VxD was dynamically - * loaded, and not statically loaded. - */ - if (!_PM_haveBIOS) { - *out = *in; - return out->x.ax; - } - - /* Disable pass-up to our VxD handler so we directly call BIOS */ - TRACE("SDDHELP: Entering PM_int86x()\n"); - if (disableTSRFlag) { - oldDisable = *disableTSRFlag; - *disableTSRFlag = 0; - } - Begin_Nest_V86_Exec(); - LoadV86Registers(&saveRegs,in,sregs); - Exec_Int(intno); - ReadV86Registers(&saveRegs,out,sregs); - End_Nest_Exec(); - - /* Re-enable pass-up to our VxD handler if previously enabled */ - if (disableTSRFlag) - *disableTSRFlag = oldDisable; - - TRACE("SDDHELP: Exiting PM_int86x()\n"); -#else - *out = *in; -#endif - return out->x.ax; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c deleted file mode 100644 index 9cd5204..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows NT device drivers. -* -* Description: Implementation for the NT driver IRQ management functions -* for the PM library. -* -****************************************************************************/ - -#include "pmapi.h" -#include "pmint.h" -#include "drvlib/os/os.h" -#include "sdd/sddhelp.h" -#include "mtrr.h" -#include "oshdr.h" - -/*--------------------------- Global variables ----------------------------*/ - -static int globalDataStart; -static uchar _PM_oldCMOSRegA; -static uchar _PM_oldCMOSRegB; -static uchar _PM_oldRTCPIC2; -static ulong RTC_idtEntry; -PM_intHandler _PM_rtcHandler = NULL; -PMFARPTR _VARAPI _PM_prevRTC = PMNULL; - -/*----------------------------- Implementation ----------------------------*/ - -/* Functions to read and write CMOS registers */ - -uchar _ASMAPI _PM_readCMOS(int index); -void _ASMAPI _PM_writeCMOS(int index,uchar value); -void _ASMAPI _PM_rtcISR(void); -void _ASMAPI _PM_getISR(int irq,PMFARPTR *handler); -void _ASMAPI _PM_setISR(int irq,void *handler); -void _ASMAPI _PM_restoreISR(int irq,PMFARPTR *handler); -void _ASMAPI _PM_irqCodeStart(void); -void _ASMAPI _PM_irqCodeEnd(void); - -/**************************************************************************** -REMARKS: -Set the real time clock frequency (for stereo modes). -****************************************************************************/ -void PMAPI PM_setRealTimeClockFrequency( - int frequency) -{ - static short convert[] = { - 8192, - 4096, - 2048, - 1024, - 512, - 256, - 128, - 64, - 32, - 16, - 8, - 4, - 2, - -1, - }; - int i; - - /* First clear any pending RTC timeout if not cleared */ - _PM_readCMOS(0x0C); - if (frequency == 0) { - /* Disable RTC timout */ - _PM_writeCMOS(0x0A,(uchar)_PM_oldCMOSRegA); - _PM_writeCMOS(0x0B,(uchar)(_PM_oldCMOSRegB & 0x0F)); - } - else { - /* Convert frequency value to RTC clock indexes */ - for (i = 0; convert[i] != -1; i++) { - if (convert[i] == frequency) - break; - } - - /* Set RTC timout value and enable timeout */ - _PM_writeCMOS(0x0A,(uchar)(0x20 | (i+3))); - _PM_writeCMOS(0x0B,(uchar)((_PM_oldCMOSRegB & 0x0F) | 0x40)); - } -} - -ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) -{ - static ibool locked = false; - - /* Save the old CMOS real time clock values */ - _PM_oldCMOSRegA = _PM_readCMOS(0x0A); - _PM_oldCMOSRegB = _PM_readCMOS(0x0B); - - /* Install the interrupt handler */ - RTC_idtEntry = 0x38; - _PM_getISR(RTC_idtEntry, &_PM_prevRTC); - _PM_rtcHandler = th; - _PM_setISR(RTC_idtEntry, _PM_rtcISR); - - /* Program the real time clock default frequency */ - PM_setRealTimeClockFrequency(frequency); - - /* Unmask IRQ8 in the PIC2 */ - _PM_oldRTCPIC2 = PM_inpb(0xA1); - PM_outpb(0xA1,(uchar)(_PM_oldRTCPIC2 & 0xFE)); - return true; -} - -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - if (_PM_rtcHandler) { - /* Restore CMOS registers and mask RTC clock */ - _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); - _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); - PM_outpb(0xA1,(uchar)((PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE))); - - /* Restore the interrupt vector */ - _PM_restoreISR(RTC_idtEntry, &_PM_prevRTC); - _PM_rtcHandler = NULL; - } -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c deleted file mode 100644 index 3128c6a..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c +++ /dev/null @@ -1,518 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows NT device drivers. -* -* Description: Implementation for the NT driver memory management functions -* for the PM library. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include "sdd/sddhelp.h" -#include "mtrr.h" -#include "oshdr.h" - -/*--------------------------- Global variables ----------------------------*/ - -#define MAX_MEMORY_SHARED 100 -#define MAX_MEMORY_MAPPINGS 100 -#define MAX_MEMORY_LOCKED 100 - -typedef struct { - void *linear; - ulong length; - PMDL pMdl; - } memshared; - -typedef struct { - void *linear; - void *mmIoMapped; - ulong length; - PMDL pMdl; - } memlocked; - -typedef struct { - ulong physical; - ulong linear; - ulong length; - ibool isCached; - } mmapping; - -static int numMappings = 0; -static memshared shared[MAX_MEMORY_MAPPINGS] = {0}; -static mmapping maps[MAX_MEMORY_MAPPINGS]; -static memlocked locked[MAX_MEMORY_LOCKED]; - -/*----------------------------- Implementation ----------------------------*/ - -ulong PMAPI _PM_getPDB(void); - -/* Page table entry flags */ - -#define PAGE_FLAGS_PRESENT 0x00000001 -#define PAGE_FLAGS_WRITEABLE 0x00000002 -#define PAGE_FLAGS_USER 0x00000004 -#define PAGE_FLAGS_WRITE_THROUGH 0x00000008 -#define PAGE_FLAGS_CACHE_DISABLE 0x00000010 -#define PAGE_FLAGS_ACCESSED 0x00000020 -#define PAGE_FLAGS_DIRTY 0x00000040 -#define PAGE_FLAGS_4MB 0x00000080 - -/**************************************************************************** -PARAMETERS: -base - Physical base address of the memory to maps in -limit - Limit of physical memory to region to maps in - -RETURNS: -Linear address of the newly mapped memory. - -REMARKS: -Maps a physical memory range to a linear memory range. -****************************************************************************/ -static ulong _PM_mapPhysicalToLinear( - ulong base, - ulong limit, - ibool isCached) -{ - ulong length = limit+1; - PHYSICAL_ADDRESS paIoBase = {0}; - - /* NT loves large Ints */ - paIoBase = RtlConvertUlongToLargeInteger( base ); - - /* Map IO space into Kernel */ - if (isCached) - return (ULONG)MmMapIoSpace(paIoBase, length, MmCached ); - else - return (ULONG)MmMapIoSpace(paIoBase, length, MmNonCached ); -} - -/**************************************************************************** -REMARKS: -Adjust the page table caching bits directly. Requires ring 0 access and -only works with DOS4GW and compatible extenders (CauseWay also works since -it has direct support for the ring 0 instructions we need from ring 3). Will -not work in a DOS box, but we call into the ring 0 helper VxD so we should -never get here in a DOS box anyway (assuming the VxD is present). If we -do get here and we are in windows, this code will be skipped. -****************************************************************************/ -static void _PM_adjustPageTables( - ulong linear, - ulong limit, - ibool isGlobal, - ibool isCached) -{ - int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; - ulong pageTable,*pPDB,*pPageTable; - ulong mask = 0xFFFFFFFF; - ulong bits = 0x00000000; - - /* Enable user level access for page table entry */ - if (isGlobal) { - mask &= ~PAGE_FLAGS_USER; - bits |= PAGE_FLAGS_USER; - } - - /* Disable PCD bit if page table entry should be uncached */ - if (!isCached) { - mask &= ~(PAGE_FLAGS_CACHE_DISABLE | PAGE_FLAGS_WRITE_THROUGH); - bits |= (PAGE_FLAGS_CACHE_DISABLE | PAGE_FLAGS_WRITE_THROUGH); - } - - pPDB = (ulong*)_PM_mapPhysicalToLinear(_PM_getPDB(),0xFFF,true); - if (pPDB) { - startPDB = (linear >> 22) & 0x3FF; - startPage = (linear >> 12) & 0x3FF; - endPDB = ((linear+limit) >> 22) & 0x3FF; - endPage = ((linear+limit) >> 12) & 0x3FF; - for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { - /* Set the bits in the page directory entry - required as per */ - /* Pentium 4 manual. This also takes care of the 4MB page entries */ - pPDB[iPDB] = (pPDB[iPDB] & mask) | bits; - if (!(pPDB[iPDB] & PAGE_FLAGS_4MB)) { - /* If we are dealing with 4KB pages then we need to iterate */ - /* through each of the page table entries */ - pageTable = pPDB[iPDB] & ~0xFFF; - pPageTable = (ulong*)_PM_mapPhysicalToLinear(pageTable,0xFFF,true); - start = (iPDB == startPDB) ? startPage : 0; - end = (iPDB == endPDB) ? endPage : 0x3FF; - for (iPage = start; iPage <= end; iPage++) { - pPageTable[iPage] = (pPageTable[iPage] & mask) | bits; - } - MmUnmapIoSpace(pPageTable,0xFFF); - } - } - MmUnmapIoSpace(pPDB,0xFFF); - PM_flushTLB(); - } -} - -/**************************************************************************** -REMARKS: -Allocate a block of shared memory. For NT we allocate shared memory -as locked, global memory that is accessible from any memory context -(including interrupt time context), which allows us to load our important -data structure and code such that we can access it directly from a ring -0 interrupt context. -****************************************************************************/ -void * PMAPI PM_mallocShared( - long size) -{ - int i; - - /* First find a free slot in our shared memory table */ - for (i = 0; i < MAX_MEMORY_SHARED; i++) { - if (shared[i].linear == 0) - break; - } - if (i == MAX_MEMORY_SHARED) - return NULL; - - /* Allocate the paged pool */ - shared[i].linear = ExAllocatePool(PagedPool, size); - - /* Create a list to manage this allocation */ - shared[i].pMdl = IoAllocateMdl(shared[i].linear,size,FALSE,FALSE,(PIRP) NULL); - - /* Lock this allocation in memory */ - MmProbeAndLockPages(shared[i].pMdl,KernelMode,IoModifyAccess); - - /* Modify bits to grant user access */ - _PM_adjustPageTables((ulong)shared[i].linear, size, true, true); - return (void*)shared[i].linear; -} - -/**************************************************************************** -REMARKS: -Free a block of shared memory -****************************************************************************/ -void PMAPI PM_freeShared( - void *p) -{ - int i; - - /* Find a shared memory block in our table and free it */ - for (i = 0; i < MAX_MEMORY_SHARED; i++) { - if (shared[i].linear == p) { - /* Unlock what we locked */ - MmUnlockPages(shared[i].pMdl); - - /* Free our MDL */ - IoFreeMdl(shared[i].pMdl); - - /* Free our mem */ - ExFreePool(shared[i].linear); - - /* Flag that is entry is available */ - shared[i].linear = 0; - break; - } - } -} - -/**************************************************************************** -REMARKS: -Map a physical address to a linear address in the callers process. -****************************************************************************/ -void * PMAPI PM_mapPhysicalAddr( - ulong base, - ulong limit, - ibool isCached) -{ - ulong linear,length = limit+1; - int i; - - /* Search table of existing mappings to see if we have already mapped */ - /* a region of memory that will serve this purpose. */ - for (i = 0; i < numMappings; i++) { - if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached) { - _PM_adjustPageTables((ulong)maps[i].linear, maps[i].length, true, isCached); - return (void*)maps[i].linear; - } - } - if (numMappings == MAX_MEMORY_MAPPINGS) - return NULL; - - /* We did not find any previously mapped memory region, so maps it in. */ - if ((linear = _PM_mapPhysicalToLinear(base,limit,isCached)) == 0xFFFFFFFF) - return NULL; - maps[numMappings].physical = base; - maps[numMappings].length = length; - maps[numMappings].linear = linear; - maps[numMappings].isCached = isCached; - numMappings++; - - /* Grant user access to this I/O space */ - _PM_adjustPageTables((ulong)linear, length, true, isCached); - return (void*)linear; -} - -/**************************************************************************** -REMARKS: -Free a physical address mapping allocated by PM_mapPhysicalAddr. -****************************************************************************/ -void PMAPI PM_freePhysicalAddr( - void *ptr, - ulong limit) -{ - /* We don't free the memory mappings in here because we cache all */ - /* the memory mappings we create in the system for later use. */ -} - -/**************************************************************************** -REMARKS: -Called when the device driver unloads to free all the page table mappings! -****************************************************************************/ -void PMAPI _PM_freeMemoryMappings(void) -{ - int i; - - for (i = 0; i < numMappings; i++) - MmUnmapIoSpace((void *)maps[i].linear,maps[i].length); -} - -/**************************************************************************** -REMARKS: -Find the physical address of a linear memory address in current process. -****************************************************************************/ -ulong PMAPI PM_getPhysicalAddr( - void *p) -{ - PHYSICAL_ADDRESS paOurAddress; - - paOurAddress = MmGetPhysicalAddress(p); - return paOurAddress.LowPart; -} - -/**************************************************************************** -REMARKS: -Find the physical address of a linear memory address in current process. -****************************************************************************/ -ibool PMAPI PM_getPhysicalAddrRange( - void *p, - ulong length, - ulong *physAddress) -{ - int i; - ulong linear = (ulong)p & ~0xFFF; - - for (i = (length + 0xFFF) >> 12; i > 0; i--) { - if ((*physAddress++ = PM_getPhysicalAddr((void*)linear)) == 0xFFFFFFFF) - return false; - linear += 4096; - } - return true; -} - -/**************************************************************************** -REMARKS: -Allocates a block of locked physical memory. -****************************************************************************/ -void * PMAPI PM_allocLockedMem( - uint size, - ulong *physAddr, - ibool contiguous, - ibool below16M) -{ - int i; - PHYSICAL_ADDRESS paOurAddress; - - /* First find a free slot in our shared memory table */ - for (i = 0; i < MAX_MEMORY_LOCKED; i++) { - if (locked[i].linear == 0) - break; - } - if (i == MAX_MEMORY_LOCKED) - return NULL; - - /* HighestAcceptableAddress - Specifies the highest valid physical address */ - /* the driver can use. For example, if a device can only reference physical */ - /* memory in the lower 16MB, this value would be set to 0x00000000FFFFFF. */ - paOurAddress.HighPart = 0; - if (below16M) - paOurAddress.LowPart = 0x00FFFFFF; - else - paOurAddress.LowPart = 0xFFFFFFFF; - - if (contiguous) { - /* Allocate from the non-paged pool (unfortunately 4MB pages) */ - locked[i].linear = MmAllocateContiguousMemory(size, paOurAddress); - if (!locked[i].linear) - return NULL; - - /* Flag no MDL */ - locked[i].pMdl = NULL; - - /* Map the physical address for the memory so we can manage */ - /* the page tables in 4KB chunks mapped into user space. */ - - /* TODO: Map this with the physical address to the linear addresss */ - locked[i].mmIoMapped = locked[i].linear; - - /* Modify bits to grant user access, flag not cached */ - _PM_adjustPageTables((ulong)locked[i].mmIoMapped, size, true, false); - return (void*)locked[i].mmIoMapped; - } - else { - /* Allocate from the paged pool */ - locked[i].linear = ExAllocatePool(PagedPool, size); - if (!locked[i].linear) - return NULL; - - /* Create a list to manage this allocation */ - locked[i].pMdl = IoAllocateMdl(locked[i].linear,size,FALSE,FALSE,(PIRP) NULL); - - /* Lock this allocation in memory */ - MmProbeAndLockPages(locked[i].pMdl,KernelMode,IoModifyAccess); - - /* Modify bits to grant user access, flag not cached */ - _PM_adjustPageTables((ulong)locked[i].linear, size, true, false); - return (void*)locked[i].linear; - } -} - -/**************************************************************************** -REMARKS: -Frees a block of locked physical memory. -****************************************************************************/ -void PMAPI PM_freeLockedMem( - void *p, - uint size, - ibool contiguous) -{ - int i; - - /* Find a locked memory block in our table and free it */ - for (i = 0; i < MAX_MEMORY_LOCKED; i++) { - if (locked[i].linear == p) { - /* An Mdl indicates that we used the paged pool, and locked it, */ - /* so now we have to unlock, free the MDL, and free paged */ - if (locked[i].pMdl) { - /* Unlock what we locked and free the Mdl */ - MmUnlockPages(locked[i].pMdl); - IoFreeMdl(locked[i].pMdl); - ExFreePool(locked[i].linear); - } - else { - /* TODO: Free the mmIoMap mapping for the memory! */ - - /* Free non-paged pool */ - MmFreeContiguousMemory(locked[i].linear); - } - - /* Flag that is entry is available */ - locked[i].linear = 0; - break; - } - } -} - -/**************************************************************************** -REMARKS: -Allocates a page aligned and page sized block of memory -****************************************************************************/ -void * PMAPI PM_allocPage( - ibool locked) -{ - /* Allocate the memory from the non-paged pool if we want the memory */ - /* to be locked. */ - return ExAllocatePool( - locked ? NonPagedPoolCacheAligned : PagedPoolCacheAligned, - PAGE_SIZE); -} - -/**************************************************************************** -REMARKS: -Free a page aligned and page sized block of memory -****************************************************************************/ -void PMAPI PM_freePage( - void *p) -{ - if (p) ExFreePool(p); -} - -/**************************************************************************** -REMARKS: -Lock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_lockDataPages( - void *p, - uint len, - PM_lockHandle *lh) -{ - MDL *pMdl; - - /* Create a list to manage this allocation */ - if ((pMdl = IoAllocateMdl(p,len,FALSE,FALSE,(PIRP)NULL)) == NULL) - return false; - - /* Lock this allocation in memory */ - MmProbeAndLockPages(pMdl,KernelMode,IoModifyAccess); - *((PMDL*)(&lh->h)) = pMdl; - return true; -} - -/**************************************************************************** -REMARKS: -Unlock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_unlockDataPages( - void *p, - uint len, - PM_lockHandle *lh) -{ - if (p && lh) { - /* Unlock what we locked */ - MDL *pMdl = *((PMDL*)(&lh->h)); - MmUnlockPages(pMdl); - IoFreeMdl(pMdl); - } - return true; -} - -/**************************************************************************** -REMARKS: -Lock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_lockCodePages( - void (*p)(), - uint len, - PM_lockHandle *lh) -{ - return PM_lockDataPages((void*)p,len,lh); -} - -/**************************************************************************** -REMARKS: -Unlock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_unlockCodePages( - void (*p)(), - uint len, - PM_lockHandle *lh) -{ - return PM_unlockDataPages((void*)p,len,lh); -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h deleted file mode 100644 index 65b7bae..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows NT drivers -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ - -#ifndef __NTDRV_OSHDR_H -#define __NTDRV_OSHDR_H - -/*--------------------------- Macros and Typedefs -------------------------*/ - -/*---------------------------- Global variables ---------------------------*/ - -/*--------------------------- Function Prototypes -------------------------*/ - -/* Internal unicode string handling functions */ - -UNICODE_STRING * _PM_CStringToUnicodeString(const char *cstr); -void _PM_FreeUnicodeString(UNICODE_STRING *uniStr); - -#endif /* __NTDRV_OSHDR_H */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c deleted file mode 100644 index c660631..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c +++ /dev/null @@ -1,933 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows NT device drivers. -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include "sdd/sddhelp.h" -#include "mtrr.h" -#include "oshdr.h" - -/*--------------------------- Global variables ----------------------------*/ - -char _PM_cntPath[PM_MAX_PATH] = ""; -char _PM_nucleusPath[PM_MAX_PATH] = ""; -static void (PMAPIP fatalErrorCleanup)(void) = NULL; - -static char *szNTWindowsKey = "\\REGISTRY\\Machine\\Software\\Microsoft\\Windows NT\\CurrentVersion"; -static char *szNTSystemRoot = "SystemRoot"; -static char *szMachineNameKey = "\\REGISTRY\\Machine\\System\\CurrentControlSet\\control\\ComputerName\\ComputerName"; -static char *szMachineNameKeyNT = "\\REGISTRY\\Machine\\System\\CurrentControlSet\\control\\ComputerName\\ActiveComputerName"; -static char *szMachineName = "ComputerName"; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the PM library. -****************************************************************************/ -void PMAPI PM_init(void) -{ - /* Initialiase the MTRR module */ - MTRR_init(); -} - -/**************************************************************************** -REMARKS: -Return the operating system type identifier. -****************************************************************************/ -long PMAPI PM_getOSType(void) -{ - return _OS_WINNTDRV; -} - -/**************************************************************************** -REMARKS: -Return the runtime type identifier. -****************************************************************************/ -int PMAPI PM_getModeType(void) -{ - return PM_386; -} - -/**************************************************************************** -REMARKS: -Add a file directory separator to the end of the filename. -****************************************************************************/ -void PMAPI PM_backslash(char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '\\') { - s[pos] = '\\'; - s[pos+1] = '\0'; - } -} - -/**************************************************************************** -REMARKS: -Add a user defined PM_fatalError cleanup function. -****************************************************************************/ -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -/**************************************************************************** -REMARKS: -Handle fatal errors internally in the driver. -****************************************************************************/ -void PMAPI PM_fatalError( - const char *msg) -{ - ULONG BugCheckCode = 0; - ULONG MoreBugCheckData[4] = {0}; - char *p; - ULONG len; - - if (fatalErrorCleanup) - fatalErrorCleanup(); - -#ifdef DBG /* Send output to debugger, just return so as not to force a reboot */ -#pragma message("INFO: building for debug, PM_fatalError() re-routed") - DBGMSG2("SDDHELP> PM_fatalError(): ERROR: %s\n", msg); - return ; -#endif - /* KeBugCheckEx brings down the system in a controlled */ - /* manner when the caller discovers an unrecoverable */ - /* inconsistency that would corrupt the system if */ - /* the caller continued to run. */ - /* */ - /* hack - dump the first 20 chars in hex using the variables */ - /* provided - Each ULONG is equal to four characters... */ - for(len = 0; len < 20; len++) - if (msg[len] == (char)0) - break; - - /* This looks bad but it's quick and reliable... */ - p = (char *)&BugCheckCode; - if(len > 0) p[3] = msg[0]; - if(len > 1) p[2] = msg[1]; - if(len > 2) p[1] = msg[2]; - if(len > 3) p[0] = msg[3]; - - p = (char *)&MoreBugCheckData[0]; - if(len > 4) p[3] = msg[4]; - if(len > 5) p[2] = msg[5]; - if(len > 6) p[1] = msg[6]; - if(len > 7) p[0] = msg[7]; - - p = (char *)&MoreBugCheckData[1]; - if(len > 8) p[3] = msg[8]; - if(len > 9) p[2] = msg[9]; - if(len > 10) p[1] = msg[10]; - if(len > 11) p[0] = msg[11]; - - p = (char *)&MoreBugCheckData[2]; - if(len > 12) p[3] = msg[12]; - if(len > 13) p[2] = msg[13]; - if(len > 14) p[1] = msg[14]; - if(len > 15) p[0] = msg[15]; - - p = (char *)&MoreBugCheckData[3]; - if(len > 16) p[3] = msg[16]; - if(len > 17) p[2] = msg[17]; - if(len > 18) p[1] = msg[18]; - if(len > 19) p[0] = msg[19]; - - /* Halt the system! */ - KeBugCheckEx(BugCheckCode, MoreBugCheckData[0], MoreBugCheckData[1], MoreBugCheckData[2], MoreBugCheckData[3]); -} - -/**************************************************************************** -REMARKS: -Return the current operating system path or working directory. -****************************************************************************/ -char * PMAPI PM_getCurrentPath( - char *path, - int maxLen) -{ - strncpy(path,_PM_cntPath,maxLen); - path[maxLen-1] = 0; - return path; -} - -/**************************************************************************** -PARAMETERS: -szKey - Key to query (can contain version number formatting) -szValue - Value to get information for -value - Place to store the registry key data read -size - Size of the string buffer to read into - -RETURNS: -true if the key was found, false if not. -****************************************************************************/ -static ibool REG_queryString( - char *szKey, - const char *szValue, - char *value, - DWORD size) -{ - ibool status; - NTSTATUS rval; - ULONG length; - HANDLE Handle; - OBJECT_ATTRIBUTES keyAttributes; - UNICODE_STRING *uniKey = NULL; - UNICODE_STRING *uniValue = NULL; - PKEY_VALUE_FULL_INFORMATION fullInfo = NULL; - STRING stringdata; - UNICODE_STRING unidata; - - /* Convert strings to UniCode */ - status = false; - if ((uniKey = _PM_CStringToUnicodeString(szKey)) == NULL) - goto Exit; - if ((uniValue = _PM_CStringToUnicodeString(szValue)) == NULL) - goto Exit; - - /* Open the key */ - InitializeObjectAttributes( &keyAttributes, - uniKey, - OBJ_CASE_INSENSITIVE, - NULL, - NULL ); - rval = ZwOpenKey( &Handle, - KEY_ALL_ACCESS, - &keyAttributes ); - if (!NT_SUCCESS(rval)) - goto Exit; - - /* Query the value */ - length = sizeof (KEY_VALUE_FULL_INFORMATION) - + size * sizeof(WCHAR); - if ((fullInfo = ExAllocatePool (PagedPool, length)) == NULL) - goto Exit; - RtlZeroMemory(fullInfo, length); - rval = ZwQueryValueKey (Handle, - uniValue, - KeyValueFullInformation, - fullInfo, - length, - &length); - if (NT_SUCCESS (rval)) { - /* Create the UniCode string so we can convert it */ - unidata.Buffer = (PWCHAR)(((PCHAR)fullInfo) + fullInfo->DataOffset); - unidata.Length = (USHORT)fullInfo->DataLength; - unidata.MaximumLength = (USHORT)fullInfo->DataLength + sizeof(WCHAR); - - /* Convert unicode univalue to ansi string. */ - rval = RtlUnicodeStringToAnsiString(&stringdata, &unidata, TRUE); - if (NT_SUCCESS(rval)) { - strcpy(value,stringdata.Buffer); - status = true; - } - } - -Exit: - if (fullInfo) ExFreePool(fullInfo); - if (uniKey) _PM_FreeUnicodeString(uniKey); - if (uniValue) _PM_FreeUnicodeString(uniValue); - return status; -} - -/**************************************************************************** -REMARKS: -Return the drive letter for the boot drive. -****************************************************************************/ -char PMAPI PM_getBootDrive(void) -{ - char path[256]; - if (REG_queryString(szNTWindowsKey,szNTSystemRoot,path,sizeof(path))) - return 'c'; - return path[0]; -} - -/**************************************************************************** -REMARKS: -Return the path to the VBE/AF driver files. -****************************************************************************/ -const char * PMAPI PM_getVBEAFPath(void) -{ - return "c:\\"; -} - -/**************************************************************************** -REMARKS: -Return the path to the Nucleus driver files. -****************************************************************************/ -const char * PMAPI PM_getNucleusPath(void) -{ - static char path[256]; - - if (strlen(_PM_nucleusPath) > 0) { - strcpy(path,_PM_nucleusPath); - PM_backslash(path); - return path; - } - if (!REG_queryString(szNTWindowsKey,szNTSystemRoot,path,sizeof(path))) - strcpy(path,"c:\\winnt"); - PM_backslash(path); - strcat(path,"system32\\nucleus"); - return path; -} - -/**************************************************************************** -REMARKS: -Return the path to the Nucleus configuration files. -****************************************************************************/ -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[256]; - strcpy(path,PM_getNucleusPath()); - PM_backslash(path); - strcat(path,"config"); - return path; -} - -/**************************************************************************** -REMARKS: -Return a unique identifier for the machine if possible. -****************************************************************************/ -const char * PMAPI PM_getUniqueID(void) -{ - return PM_getMachineName(); -} - -/**************************************************************************** -REMARKS: -Get the name of the machine on the network. -****************************************************************************/ -const char * PMAPI PM_getMachineName(void) -{ - static char name[256]; - - if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name))) - return name; - if (REG_queryString(szMachineNameKeyNT,szMachineName,name,sizeof(name))) - return name; - return "Unknown"; -} - -/**************************************************************************** -REMARKS: -Check if a key has been pressed. -****************************************************************************/ -int PMAPI PM_kbhit(void) -{ - /* Not used in NT drivers */ - return true; -} - -/**************************************************************************** -REMARKS: -Wait for and return the next keypress. -****************************************************************************/ -int PMAPI PM_getch(void) -{ - /* Not used in NT drivers */ - return 0xD; -} - -/**************************************************************************** -REMARKS: -Open a console for output to the screen, creating the main event handling -window if necessary. -****************************************************************************/ -PM_HWND PMAPI PM_openConsole( - PM_HWND hwndUser, - int device, - int xRes, - int yRes, - int bpp, - ibool fullScreen) -{ - /* Not used in NT drivers */ - (void)hwndUser; - (void)device; - (void)xRes; - (void)yRes; - (void)bpp; - (void)fullScreen; - return NULL; -} - -/**************************************************************************** -REMARKS: -Find the size of the console state buffer. -****************************************************************************/ -int PMAPI PM_getConsoleStateSize(void) -{ - /* Not used in NT drivers */ - return 1; -} - -/**************************************************************************** -REMARKS: -Save the state of the console. -****************************************************************************/ -void PMAPI PM_saveConsoleState( - void *stateBuf, - PM_HWND hwndConsole) -{ - /* Not used in NT drivers */ - (void)stateBuf; - (void)hwndConsole; -} - -/**************************************************************************** -REMARKS: -Set the suspend application callback for the fullscreen console. -****************************************************************************/ -void PMAPI PM_setSuspendAppCallback( - PM_saveState_cb saveState) -{ - /* Not used in NT drivers */ - (void)saveState; -} - -/**************************************************************************** -REMARKS: -Restore the console state. -****************************************************************************/ -void PMAPI PM_restoreConsoleState( - const void *stateBuf, - PM_HWND hwndConsole) -{ - /* Not used in NT drivers */ - (void)stateBuf; - (void)hwndConsole; -} - -/**************************************************************************** -REMARKS: -Close the fullscreen console. -****************************************************************************/ -void PMAPI PM_closeConsole( - PM_HWND hwndConsole) -{ - /* Not used in NT drivers */ - (void)hwndConsole; -} - -/**************************************************************************** -REMARKS: -Set the location of the OS console cursor. -****************************************************************************/ -void PMAPI PM_setOSCursorLocation( - int x, - int y) -{ - /* Nothing to do for Windows */ - (void)x; - (void)y; -} - -/**************************************************************************** -REMARKS: -Set the width of the OS console. -****************************************************************************/ -void PMAPI PM_setOSScreenWidth( - int width, - int height) -{ - /* Nothing to do for Windows */ - (void)width; - (void)height; -} - -/**************************************************************************** -REMARKS: -Maps a shared memory block into process address space. Does nothing since -the memory blocks are already globally mapped into all processes. -****************************************************************************/ -void * PMAPI PM_mapToProcess( - void *base, - ulong limit) -{ - /* Not used anymore */ - (void)base; - (void)limit; - return NULL; -} - -/**************************************************************************** -REMARKS: -Execute the POST on the secondary BIOS for a controller. -****************************************************************************/ -ibool PMAPI PM_doBIOSPOST( - ushort axVal, - ulong BIOSPhysAddr, - void *mappedBIOS, - ulong BIOSLen) -{ - /* This may not be possible in NT and should be done by the OS anyway */ - (void)axVal; - (void)BIOSPhysAddr; - (void)mappedBIOS; - (void)BIOSLen; - return false; -} - -/**************************************************************************** -REMARKS: -Return a pointer to the real mode BIOS data area. -****************************************************************************/ -void * PMAPI PM_getBIOSPointer(void) -{ - /* Note that on NT this probably does not do what we expect! */ - return PM_mapPhysicalAddr(0x400, 0x1000, true); -} - -/**************************************************************************** -REMARKS: -Return a pointer to 0xA0000 physical VGA graphics framebuffer. -****************************************************************************/ -void * PMAPI PM_getA0000Pointer(void) -{ - return PM_mapPhysicalAddr(0xA0000,0xFFFF,false); -} - -/**************************************************************************** -REMARKS: -Sleep for the specified number of milliseconds. -****************************************************************************/ -void PMAPI PM_sleep( - ulong milliseconds) -{ - /* We never use this in NT drivers */ - (void)milliseconds; -} - -/**************************************************************************** -REMARKS: -Return the base I/O port for the specified COM port. -****************************************************************************/ -int PMAPI PM_getCOMPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - case 2: return 0x3E8; - case 3: return 0x2E8; - } - return 0; -} - -/**************************************************************************** -REMARKS: -Return the base I/O port for the specified LPT port. -****************************************************************************/ -int PMAPI PM_getLPTPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -/**************************************************************************** -REMARKS: -Returns available memory. Not possible under Windows. -****************************************************************************/ -void PMAPI PM_availableMemory( - ulong *physical, - ulong *total) -{ - *physical = *total = 0; -} - -/**************************************************************************** -REMARKS: -OS specific shared libraries not supported inside a VxD -****************************************************************************/ -PM_MODULE PMAPI PM_loadLibrary( - const char *szDLLName) -{ - /* Not used in NT drivers */ - (void)szDLLName; - return NULL; -} - -/**************************************************************************** -REMARKS: -OS specific shared libraries not supported inside a VxD -****************************************************************************/ -void * PMAPI PM_getProcAddress( - PM_MODULE hModule, - const char *szProcName) -{ - /* Not used in NT drivers */ - (void)hModule; - (void)szProcName; - return NULL; -} - -/**************************************************************************** -REMARKS: -OS specific shared libraries not supported inside a VxD -****************************************************************************/ -void PMAPI PM_freeLibrary( - PM_MODULE hModule) -{ - /* Not used in NT drivers */ - (void)hModule; -} - -/**************************************************************************** -REMARKS: -Function to find the first file matching a search criteria in a directory. -****************************************************************************/ -void *PMAPI PM_findFirstFile( - const char *filename, - PM_findData *findData) -{ - /* TODO: This function should start a directory enumeration search */ - /* given the filename (with wildcards). The data should be */ - /* converted and returned in the findData standard form. */ - (void)filename; - (void)findData; - return PM_FILE_INVALID; -} - -/**************************************************************************** -REMARKS: -Function to find the next file matching a search criteria in a directory. -****************************************************************************/ -ibool PMAPI PM_findNextFile( - void *handle, - PM_findData *findData) -{ - /* TODO: This function should find the next file in directory enumeration */ - /* search given the search criteria defined in the call to */ - /* PM_findFirstFile. The data should be converted and returned */ - /* in the findData standard form. */ - (void)handle; - (void)findData; - return false; -} - -/**************************************************************************** -REMARKS: -Function to close the find process -****************************************************************************/ -void PMAPI PM_findClose( - void *handle) -{ - /* TODO: This function should close the find process. This may do */ - /* nothing for some OS'es. */ - (void)handle; -} - -/**************************************************************************** -REMARKS: -Function to determine if a drive is a valid drive or not. Under Unix this -function will return false for anything except a value of 3 (considered -the root drive, and equivalent to C: for non-Unix systems). The drive -numbering is: - - 1 - Drive A: - 2 - Drive B: - 3 - Drive C: - etc - -****************************************************************************/ -ibool PMAPI PM_driveValid( - char drive) -{ - /* Not supported in NT drivers */ - (void)drive; - return false; -} - -/**************************************************************************** -REMARKS: -Function to get the current working directory for the specififed drive. -Under Unix this will always return the current working directory regardless -of what the value of 'drive' is. -****************************************************************************/ -void PMAPI PM_getdcwd( - int drive, - char *dir, - int len) -{ - /* Not supported in NT drivers */ - (void)drive; - (void)dir; - (void)len; -} - -/**************************************************************************** -PARAMETERS: -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -RETURNS: -Error code describing the result. - -REMARKS: -Function to enable write combining for the specified region of memory. -****************************************************************************/ -int PMAPI PM_enableWriteCombine( - ulong base, - ulong size, - uint type) -{ - return MTRR_enableWriteCombine(base,size,type); -} - -/**************************************************************************** -REMARKS: -Function to change the file attributes for a specific file. -****************************************************************************/ -void PMAPI PM_setFileAttr( - const char *filename, - uint attrib) -{ - NTSTATUS status; - ACCESS_MASK DesiredAccess = GENERIC_READ | GENERIC_WRITE; - OBJECT_ATTRIBUTES ObjectAttributes; - ULONG ShareAccess = FILE_SHARE_READ; - ULONG CreateDisposition = FILE_OPEN; - HANDLE FileHandle = NULL; - UNICODE_STRING *uniFile = NULL; - IO_STATUS_BLOCK IoStatusBlock; - FILE_BASIC_INFORMATION FileBasic; - char kernelFilename[PM_MAX_PATH+5]; - ULONG FileAttributes = 0; - - /* Convert file attribute flags */ - if (attrib & PM_FILE_READONLY) - FileAttributes |= FILE_ATTRIBUTE_READONLY; - if (attrib & PM_FILE_ARCHIVE) - FileAttributes |= FILE_ATTRIBUTE_ARCHIVE; - if (attrib & PM_FILE_HIDDEN) - FileAttributes |= FILE_ATTRIBUTE_HIDDEN; - if (attrib & PM_FILE_SYSTEM) - FileAttributes |= FILE_ATTRIBUTE_SYSTEM; - - /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */ - strcpy(kernelFilename, "\\??\\"); - strcat(kernelFilename, filename); - - /* Convert filename string to ansi string */ - if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL) - goto Exit; - - /* Must open a file to query it's attributes */ - InitializeObjectAttributes (&ObjectAttributes, - uniFile, - OBJ_CASE_INSENSITIVE, - NULL, - NULL ); - status = ZwCreateFile( &FileHandle, - DesiredAccess | SYNCHRONIZE, - &ObjectAttributes, - &IoStatusBlock, - NULL, /*AllocationSize OPTIONAL, */ - FILE_ATTRIBUTE_NORMAL, - ShareAccess, - CreateDisposition, - FILE_RANDOM_ACCESS, /*CreateOptions, */ - NULL, /*EaBuffer OPTIONAL, */ - 0 /*EaLength (required if EaBuffer) */ - ); - if (!NT_SUCCESS (status)) - goto Exit; - - /* Query timestamps */ - status = ZwQueryInformationFile(FileHandle, - &IoStatusBlock, - &FileBasic, - sizeof(FILE_BASIC_INFORMATION), - FileBasicInformation - ); - if (!NT_SUCCESS (status)) - goto Exit; - - /* Change the four bits we change */ - FileBasic.FileAttributes &= ~(FILE_ATTRIBUTE_READONLY | FILE_ATTRIBUTE_ARCHIVE - | FILE_ATTRIBUTE_HIDDEN | FILE_ATTRIBUTE_SYSTEM); - FileBasic.FileAttributes |= FileAttributes; - - /* Set timestamps */ - ZwSetInformationFile( FileHandle, - &IoStatusBlock, - &FileBasic, - sizeof(FILE_BASIC_INFORMATION), - FileBasicInformation - ); - -Exit: - if (FileHandle) ZwClose(FileHandle); - if (uniFile) _PM_FreeUnicodeString(uniFile); - return; -} - -/**************************************************************************** -REMARKS: -Function to get the file attributes for a specific file. -****************************************************************************/ -uint PMAPI PM_getFileAttr( - const char *filename) -{ - NTSTATUS status; - ACCESS_MASK DesiredAccess = GENERIC_READ | GENERIC_WRITE; - OBJECT_ATTRIBUTES ObjectAttributes; - ULONG ShareAccess = FILE_SHARE_READ; - ULONG CreateDisposition = FILE_OPEN; - HANDLE FileHandle = NULL; - UNICODE_STRING *uniFile = NULL; - IO_STATUS_BLOCK IoStatusBlock; - FILE_BASIC_INFORMATION FileBasic; - char kernelFilename[PM_MAX_PATH+5]; - ULONG FileAttributes = 0; - uint retval = 0; - - /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */ - strcpy(kernelFilename, "\\??\\"); - strcat(kernelFilename, filename); - - /* Convert filename string to ansi string */ - if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL) - goto Exit; - - /* Must open a file to query it's attributes */ - InitializeObjectAttributes (&ObjectAttributes, - uniFile, - OBJ_CASE_INSENSITIVE, - NULL, - NULL ); - status = ZwCreateFile( &FileHandle, - DesiredAccess | SYNCHRONIZE, - &ObjectAttributes, - &IoStatusBlock, - NULL, /*AllocationSize OPTIONAL, */ - FILE_ATTRIBUTE_NORMAL, - ShareAccess, - CreateDisposition, - FILE_RANDOM_ACCESS, /*CreateOptions, */ - NULL, /*EaBuffer OPTIONAL, */ - 0 /*EaLength (required if EaBuffer) */ - ); - if (!NT_SUCCESS (status)) - goto Exit; - - /* Query timestamps */ - status = ZwQueryInformationFile(FileHandle, - &IoStatusBlock, - &FileBasic, - sizeof(FILE_BASIC_INFORMATION), - FileBasicInformation - ); - if (!NT_SUCCESS (status)) - goto Exit; - - /* Translate the file attributes */ - if (FileBasic.FileAttributes & FILE_ATTRIBUTE_READONLY) - retval |= PM_FILE_READONLY; - if (FileBasic.FileAttributes & FILE_ATTRIBUTE_ARCHIVE) - retval |= PM_FILE_ARCHIVE; - if (FileBasic.FileAttributes & FILE_ATTRIBUTE_HIDDEN) - retval |= PM_FILE_HIDDEN; - if (FileBasic.FileAttributes & FILE_ATTRIBUTE_SYSTEM) - retval |= PM_FILE_SYSTEM; - -Exit: - if (FileHandle) ZwClose(FileHandle); - if (uniFile) _PM_FreeUnicodeString(uniFile); - return retval; -} - -/**************************************************************************** -REMARKS: -Function to create a directory. -****************************************************************************/ -ibool PMAPI PM_mkdir( - const char *filename) -{ - /* Not supported in NT drivers */ - (void)filename; - return false; -} - -/**************************************************************************** -REMARKS: -Function to remove a directory. -****************************************************************************/ -ibool PMAPI PM_rmdir( - const char *filename) -{ - /* Not supported in NT drivers */ - (void)filename; - return false; -} - -/**************************************************************************** -REMARKS: -Function to get the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_getFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* Not supported in NT drivers */ - (void)filename; - (void)gmTime; - (void)time; - return false; -} - -/**************************************************************************** -REMARKS: -Function to set the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_setFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* Not supported in NT drivers */ - (void)filename; - (void)gmTime; - (void)time; - return false; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c deleted file mode 100644 index 658f1c8..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c +++ /dev/null @@ -1,330 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows NT driver -* -* Description: C library compatible I/O functions for use within a Windows -* NT driver. -* -****************************************************************************/ - -#include "pmapi.h" -#include "oshdr.h" - -/*------------------------ Main Code Implementation -----------------------*/ - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C fopen function. -****************************************************************************/ -FILE * fopen( - const char *filename, - const char *mode) -{ - ACCESS_MASK DesiredAccess; /* for ZwCreateFile... */ - OBJECT_ATTRIBUTES ObjectAttributes; - ULONG ShareAccess; - ULONG CreateDisposition; - NTSTATUS status; - HANDLE FileHandle; - UNICODE_STRING *uniFile = NULL; - PWCHAR bufFile = NULL; - IO_STATUS_BLOCK IoStatusBlock; - FILE_STANDARD_INFORMATION FileInformation; - FILE_POSITION_INFORMATION FilePosition; - char kernelFilename[PM_MAX_PATH+5]; - FILE *f; - - /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */ - strcpy(kernelFilename, "\\??\\"); - strcat(kernelFilename, filename); - if ((f = PM_malloc(sizeof(FILE))) == NULL) - goto Error; - f->offset = 0; - f->text = (mode[1] == 't' || mode[2] == 't'); - f->writemode = (mode[0] == 'w') || (mode[0] == 'a'); - if (mode[0] == 'r') { - /* omode = OPEN_ACCESS_READONLY | OPEN_SHARE_COMPATIBLE; */ - /* action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_FAIL; */ - DesiredAccess = GENERIC_READ; - ShareAccess = FILE_SHARE_READ | FILE_SHARE_WRITE; - CreateDisposition = FILE_OPEN; - } - else if (mode[0] == 'w') { - /* omode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_COMPATIBLE; */ - /* action = ACTION_IFEXISTS_TRUNCATE | ACTION_IFNOTEXISTS_CREATE; */ - DesiredAccess = GENERIC_WRITE; - ShareAccess = FILE_SHARE_READ | FILE_SHARE_WRITE; - CreateDisposition = FILE_SUPERSEDE; - } - else { - /* omode = OPEN_ACCESS_READWRITE | OPEN_SHARE_COMPATIBLE; */ - /* action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_CREATE; */ - DesiredAccess = GENERIC_READ | GENERIC_WRITE; - ShareAccess = FILE_SHARE_READ; - CreateDisposition = FILE_OPEN_IF; - } - - /* Convert filename string to ansi string and then to UniCode string */ - if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL) - return NULL; - - /* Create the file */ - InitializeObjectAttributes (&ObjectAttributes, - uniFile, - OBJ_CASE_INSENSITIVE, - NULL, - NULL); - status = ZwCreateFile( &FileHandle, - DesiredAccess | SYNCHRONIZE, - &ObjectAttributes, - &IoStatusBlock, - NULL, /* AllocationSize OPTIONAL, */ - FILE_ATTRIBUTE_NORMAL, - ShareAccess, - CreateDisposition, - FILE_RANDOM_ACCESS, /* CreateOptions, */ - NULL, /* EaBuffer OPTIONAL, */ - 0 /* EaLength (required if EaBuffer) */ - ); - if (!NT_SUCCESS (status)) - goto Error; - f->handle = (int)FileHandle; - - /* Determine size of the file */ - status = ZwQueryInformationFile( FileHandle, - &IoStatusBlock, - &FileInformation, - sizeof(FILE_STANDARD_INFORMATION), - FileStandardInformation - ); - if (!NT_SUCCESS (status)) - goto Error; - f->filesize = FileInformation.EndOfFile.LowPart; - - /* Move to the end of the file if we are appending */ - if (mode[0] == 'a') { - FilePosition.CurrentByteOffset.HighPart = 0; - FilePosition.CurrentByteOffset.LowPart = f->filesize; - status = ZwSetInformationFile( FileHandle, - &IoStatusBlock, - &FilePosition, - sizeof(FILE_POSITION_INFORMATION), - FilePositionInformation - ); - if (!NT_SUCCESS (status)) - goto Error; - } - return f; - -Error: - if (f) PM_free(f); - if (uniFile) _PM_FreeUnicodeString(uniFile); - return NULL; -} - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C fread function. -****************************************************************************/ -size_t fread( - void *ptr, - size_t size, - size_t n, - FILE *f) -{ - NTSTATUS status; - IO_STATUS_BLOCK IoStatusBlock; - LARGE_INTEGER ByteOffset; - - /* Read any extra bytes from the file */ - ByteOffset.HighPart = 0; - ByteOffset.LowPart = f->offset; - status = ZwReadFile( (HANDLE)f->handle, - NULL, /*IN HANDLE Event OPTIONAL, */ - NULL, /* IN PIO_APC_ROUTINE ApcRoutine OPTIONAL, */ - NULL, /* IN PVOID ApcContext OPTIONAL, */ - &IoStatusBlock, - ptr, /* OUT PVOID Buffer, */ - size * n, /*IN ULONG Length, */ - &ByteOffset, /*OPTIONAL, */ - NULL /*IN PULONG Key OPTIONAL */ - ); - if (!NT_SUCCESS (status)) - return 0; - f->offset += IoStatusBlock.Information; - return IoStatusBlock.Information / size; -} - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C fwrite function. -****************************************************************************/ -size_t fwrite( - const void *ptr, - size_t size, - size_t n, - FILE *f) -{ - NTSTATUS status; - IO_STATUS_BLOCK IoStatusBlock; - LARGE_INTEGER ByteOffset; - - if (!f->writemode) - return 0; - ByteOffset.HighPart = 0; - ByteOffset.LowPart = f->offset; - status = ZwWriteFile( (HANDLE)f->handle, - NULL, /*IN HANDLE Event OPTIONAL, */ - NULL, /* IN PIO_APC_ROUTINE ApcRoutine OPTIONAL, */ - NULL, /* IN PVOID ApcContext OPTIONAL, */ - &IoStatusBlock, - (void*)ptr, /* OUT PVOID Buffer, */ - size * n, /*IN ULONG Length, */ - &ByteOffset, /*OPTIONAL, */ - NULL /*IN PULONG Key OPTIONAL */ - ); - if (!NT_SUCCESS (status)) - return 0; - f->offset += IoStatusBlock.Information; - if (f->offset > f->filesize) - f->filesize = f->offset; - return IoStatusBlock.Information / size; -} - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C fflush function. -****************************************************************************/ -int fflush( - FILE *f) -{ - /* Nothing to do here as we are not doing buffered I/O */ - (void)f; - return 0; -} - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C fseek function. -****************************************************************************/ -int fseek( - FILE *f, - long int offset, - int whence) -{ - NTSTATUS status; - FILE_POSITION_INFORMATION FilePosition; - IO_STATUS_BLOCK IoStatusBlock; - - if (whence == 0) - f->offset = offset; - else if (whence == 1) - f->offset += offset; - else if (whence == 2) - f->offset = f->filesize + offset; - FilePosition.CurrentByteOffset.HighPart = 0; - FilePosition.CurrentByteOffset.LowPart = f->offset; - status = ZwSetInformationFile( (HANDLE)f->handle, - &IoStatusBlock, - &FilePosition, - sizeof(FILE_POSITION_INFORMATION), - FilePositionInformation - ); - if (!NT_SUCCESS (status)) - return -1; - return 0; -} - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C ftell function. -****************************************************************************/ -long ftell( - FILE *f) -{ - return f->offset; -} - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C feof function. -****************************************************************************/ -int feof( - FILE *f) -{ - return (f->offset == f->filesize); -} - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C fgets function. -****************************************************************************/ -char *fgets( - char *s, - int n, - FILE *f) -{ - int len; - char *cs; - - /* Read the entire buffer into memory (our functions are unbuffered!) */ - if ((len = fread(s,1,n,f)) == 0) - return NULL; - - /* Search for '\n' or end of string */ - if (n > len) - n = len; - cs = s; - while (--n > 0) { - if (*cs == '\n') - break; - cs++; - } - *cs = '\0'; - return s; -} - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C fputs function. -****************************************************************************/ -int fputs( - const char *s, - FILE *f) -{ - return fwrite(s,1,strlen(s),f); -} - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C fclose function. -****************************************************************************/ -int fclose( - FILE *f) -{ - ZwClose((HANDLE)f->handle); - PM_free(f); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c deleted file mode 100644 index bbf0cbf..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows NT driver -* -* Description: C library compatible stdlib.h functions for use within a -* Windows NT driver. -* -****************************************************************************/ - -#include "pmapi.h" -#include "oshdr.h" - -/*------------------------ Main Code Implementation -----------------------*/ - -/**************************************************************************** -REMARKS: -PM_malloc override function for Nucleus drivers loaded in NT drivers's. -****************************************************************************/ -void * malloc( - size_t size) -{ - return PM_mallocShared(size); -} - -/**************************************************************************** -REMARKS: -calloc library function for Nucleus drivers loaded in NT drivers's. -****************************************************************************/ -void * calloc( - size_t nelem, - size_t size) -{ - void *p = PM_mallocShared(nelem * size); - if (p) - memset(p,0,nelem * size); - return p; -} - -/**************************************************************************** -REMARKS: -PM_realloc override function for Nucleus drivers loaded in VxD's. -****************************************************************************/ -void * realloc( - void *ptr, - size_t size) -{ - void *p = PM_mallocShared(size); - if (p) { - memcpy(p,ptr,size); - PM_freeShared(ptr); - } - return p; -} - -/**************************************************************************** -REMARKS: -PM_free override function for Nucleus drivers loaded in VxD's. -****************************************************************************/ -void free( - void *p) -{ - PM_freeShared(p); -} - -/**************************************************************************** -PARAMETERS: -cstr - C style ANSI string to convert - -RETURNS: -Pointer to the UniCode string structure or NULL on failure to allocate memory - -REMARKS: -Converts a C style string to a UniCode string structure that can be passed -directly to NT kernel functions. -****************************************************************************/ -UNICODE_STRING *_PM_CStringToUnicodeString( - const char *cstr) -{ - int length; - ANSI_STRING ansiStr; - UNICODE_STRING *uniStr; - - /* Allocate memory for the string structure */ - if ((uniStr = ExAllocatePool(NonPagedPool, sizeof(UNICODE_STRING))) == NULL) - return NULL; - - /* Allocate memory for the wide string itself */ - length = (strlen(cstr) * sizeof(WCHAR)) + sizeof(WCHAR); - if ((uniStr->Buffer = ExAllocatePool(NonPagedPool, length)) == NULL) { - ExFreePool(uniStr); - return NULL; - } - RtlZeroMemory(uniStr->Buffer, length); - uniStr->Length = 0; - uniStr->MaximumLength = (USHORT)length; - - /* Convert filename string to ansi string and then to UniCode string */ - RtlInitAnsiString(&ansiStr, cstr); - RtlAnsiStringToUnicodeString(uniStr, &ansiStr, FALSE); - return uniStr; -} - -/**************************************************************************** -PARAMETERS: -uniStr - UniCode string structure to free - -REMARKS: -Frees a string allocated by the above _PM_CStringToUnicodeString function. -****************************************************************************/ -void _PM_FreeUnicodeString( - UNICODE_STRING *uniStr) -{ - if (uniStr) { - ExFreePool(uniStr->Buffer); - ExFreePool(uniStr); - } -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c deleted file mode 100644 index 901ce1c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Dummy module; no virtual framebuffer for this OS -* -****************************************************************************/ - -#include "pmapi.h" - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -{ - return NULL; -} - -void PMAPI VF_exit(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c deleted file mode 100644 index f4c4bd4..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c +++ /dev/null @@ -1,123 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows VxD -* -* Description: OS specific implementation for the Zen Timer functions. -* -****************************************************************************/ - -/*---------------------------- Global variables ---------------------------*/ - -static CPU_largeInteger countFreq; -static ulong start,finish; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -static void __ZTimerInit(void) -{ - KeQueryPerformanceCounter((LARGE_INTEGER*)&countFreq); -} - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -static void __LZTimerOn( - LZTimerObject *tm) -{ - LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL); - tm->start.low = lt.LowPart; - tm->start.high = lt.HighPart; -} - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -static ulong __LZTimerLap( - LZTimerObject *tm) -{ - LARGE_INTEGER tmLap = KeQueryPerformanceCounter(NULL); - CPU_largeInteger tmCount; - - _CPU_diffTime64(&tm->start,(CPU_largeInteger*)&tmLap,&tmCount); - return _CPU_calcMicroSec(&tmCount,countFreq.low); -} - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -static void __LZTimerOff( - LZTimerObject *tm) -{ - LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL); - tm->end.low = lt.LowPart; - tm->end.high = lt.HighPart; -} - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -static ulong __LZTimerCount( - LZTimerObject *tm) -{ - CPU_largeInteger tmCount; - - _CPU_diffTime64(&tm->start,&tm->end,&tmCount); - return _CPU_calcMicroSec(&tmCount,countFreq.low); -} - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as microseconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION 1 - -/**************************************************************************** -REMARKS: -Read the Long Period timer value from the BIOS timer tick. -****************************************************************************/ -static ulong __ULZReadTime(void) -{ - LARGE_INTEGER count; - KeQuerySystemTime(&count); - return (ulong)(*((_int64*)&count) / 10); -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong __ULZElapsedTime(ulong start,ulong finish) -{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm b/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm deleted file mode 100644 index 761f0f4..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm +++ /dev/null @@ -1,180 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: OS/2 32 bit protected mode -;* -;* Description: Low level assembly support for the PM library specific -;* to OS/2 -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _pmos2 ; Set up memory model - -begdataseg _pmos2 - - cglobal _PM_ioentry - cglobal _PM_gdt -_PM_ioentry dd 0 ; Offset to call gate -_PM_gdt dw 0 ; Selector to call gate - -enddataseg _pmos2 - -begcodeseg _pmos2 ; Start of code segment - -;---------------------------------------------------------------------------- -; int PM_setIOPL(int iopl) -;---------------------------------------------------------------------------- -; Change the IOPL level for the 32-bit task. Returns the previous level -; so it can be restored for the task correctly. -;---------------------------------------------------------------------------- -cprocstart PM_setIOPL - - ARG iopl:UINT - - enter_c - pushfd ; Save the old EFLAGS for later - mov ecx,[iopl] ; ECX := IOPL level - xor ebx,ebx ; Change IOPL level function code (0) -ifdef USE_NASM - call far dword [_PM_ioentry] -else - call [FWORD _PM_ioentry] -endif - pop eax - and eax,0011000000000000b - shr eax,12 - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _PM_setGDTSelLimit(ushort selector, ulong limit); -;---------------------------------------------------------------------------- -; Change the GDT selector limit to given value. Used to change selector -; limits to address the entire system address space. -;---------------------------------------------------------------------------- -cprocstart _PM_setGDTSelLimit - - ARG selector:USHORT, limit:UINT - - enter_c - sub esp,20 ; Make room for selector data on stack - mov ecx,esp ; ECX := selector data structure - mov bx,[selector] ; Fill out the data structure - and bx,0FFF8h ; Kick out the LDT/GDT and DPL bits - mov [WORD ecx],bx - mov ebx,[limit] - mov [DWORD ecx+4],ebx - mov ebx,5 ; Set GDT selector limit function code -ifdef USE_NASM - call far dword [_PM_ioentry] -else - call [FWORD _PM_ioentry] -endif - add esp,20 - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; uchar _MTRR_getCx86(uchar reg); -;---------------------------------------------------------------------------- -; Read a Cyrix CPU indexed register -;---------------------------------------------------------------------------- -cprocstart _MTRR_getCx86 - - ARG reg:UCHAR - - enter_c - mov al,[reg] - out 22h,al - in al,23h - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; uchar _MTRR_setCx86(uchar reg,uchar val); -;---------------------------------------------------------------------------- -; Write a Cyrix CPU indexed register -;---------------------------------------------------------------------------- -cprocstart _MTRR_setCx86 - - ARG reg:UCHAR, val:UCHAR - - enter_c - mov al,[reg] - out 22h,al - mov al,[val] - out 23h,al - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; ulong _MTRR_disableInt(void); -;---------------------------------------------------------------------------- -; Return processor interrupt status and disable interrupts. -;---------------------------------------------------------------------------- -cprocstart _MTRR_disableInt - -; Do nothing! - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _MTRR_restoreInt(ulong ps); -;---------------------------------------------------------------------------- -; Restore processor interrupt status. -;---------------------------------------------------------------------------- -cprocstart _MTRR_restoreInt - -; Do nothing! - ret - -cprocend - -;---------------------------------------------------------------------------- -; void DebugInt(void) -;---------------------------------------------------------------------------- -cprocstart DebugInt - - int 3 - ret - -cprocend - -endcodeseg _pmos2 - - END ; End of module - diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c deleted file mode 100644 index 7de400d..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: OS/2 -* -* Description: OS/2 specific code for the CPU detection module. -* -****************************************************************************/ - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -TODO: This should be implemented for OS/2! -****************************************************************************/ -#define SetMaxThreadPriority() 0 - -/**************************************************************************** -REMARKS: -TODO: This should be implemented for OS/2! -****************************************************************************/ -#define RestoreThreadPriority(i) - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - freq->low = 100000; - freq->high = 0; -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. -****************************************************************************/ -#define GetCounter(t) \ -{ \ - ULONG count; \ - DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) ); \ - (t)->low = count * 100; \ - (t)->high = 0; \ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj b/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj deleted file mode 100644 index 5533346..0000000 Binary files a/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/event.c b/board/MAI/bios_emulator/scitech/src/pm/os2/event.c deleted file mode 100644 index 91cc19b..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/os2/event.c +++ /dev/null @@ -1,565 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: IBM PC (OS/2) -* -* Description: OS/2 implementation for the SciTech cross platform -* event library. -* -****************************************************************************/ - -/*---------------------------- Global Variables ---------------------------*/ - -/* Define generous keyboard monitor circular buffer size to minimize - * the danger of losing keystrokes - */ -#define KEYBUFSIZE (EVENTQSIZE + 10) - -static int oldMouseState; /* Old mouse state */ -static ulong oldKeyMessage; /* Old keyboard state */ -static ushort keyUpMsg[256] = {0}; /* Table of key up messages */ -static int rangeX,rangeY; /* Range of mouse coordinates */ -HMOU _EVT_hMouse; /* Handle to the mouse driver */ -HMONITOR _EVT_hKbdMon; /* Handle to the keyboard driver */ -TID kbdMonTID = 0; /* Keyboard monitor thread ID */ -HEV hevStart; /* Start event semaphore handle */ -BOOL bMonRunning; /* Flag set if monitor thread OK */ -HMTX hmtxKeyBuf; /* Mutex protecting key buffer */ -KEYPACKET keyMonPkts[KEYBUFSIZE]; /* Array of monitor key packets */ -int kpHead = 0; /* Key packet buffer head */ -int kpTail = 0; /* Key packet buffer tail */ - -/*---------------------------- Implementation -----------------------------*/ - -/* These are not used under OS/2 */ -#define _EVT_disableInt() 1 -#define _EVT_restoreInt(flags) - -/**************************************************************************** -PARAMETERS: -scanCode - Scan code to test - -REMARKS: -This macro determines if a specified key is currently down at the -time that the call is made. -****************************************************************************/ -#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) - -/**************************************************************************** -REMARKS: -This function is used to return the number of ticks since system -startup in milliseconds. This should be the same value that is placed into -the time stamp fields of events, and is used to implement auto mouse down -events. -****************************************************************************/ -ulong _EVT_getTicks(void) -{ - ULONG count; - DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) ); - return count; -} - -/**************************************************************************** -REMARKS: -Converts a mickey movement value to a pixel adjustment value. -****************************************************************************/ -static int MickeyToPixel( - int mickey) -{ - /* TODO: We can add some code in here to handle 'acceleration' for */ - /* the mouse cursor. For now just use the mickeys. */ - return mickey; -} - -/* Some useful defines any typedefs used in the keyboard handling */ -#define KEY_RELEASE 0x40 - -/**************************************************************************** -REMARKS: -Pumps all messages in the message queue from OS/2 into our event queue. -****************************************************************************/ -static void _EVT_pumpMessages(void) -{ - KBDINFO keyInfo; /* Must not cross a 64K boundary */ - KBDKEYINFO key; /* Must not cross a 64K boundary */ - MOUQUEINFO mqueue; /* Must not cross a 64K boundary */ - MOUEVENTINFO mouse; /* Must not cross a 64K boundary */ - ushort mWait; /* Must not cross a 64K boundary */ - KEYPACKET kp; /* Must not cross a 64K boundary */ - event_t evt; - int scan; - ibool noInput = TRUE; /* Flag to determine if any input was available */ - - /* First of all, check if we should do any session switch work */ - __PM_checkConsoleSwitch(); - - /* Pump all keyboard messages from our circular buffer */ - for (;;) { - /* Check that the monitor thread is still running */ - if (!bMonRunning) - PM_fatalError("Keyboard monitor thread died!"); - - /* Protect keypacket buffer with mutex */ - DosRequestMutexSem(hmtxKeyBuf, SEM_INDEFINITE_WAIT); - if (kpHead == kpTail) { - DosReleaseMutexSem(hmtxKeyBuf); - break; - } - - noInput = FALSE; - - /* Read packet from circular buffer and remove it */ - memcpy(&kp, &keyMonPkts[kpTail], sizeof(KEYPACKET)); - if (++kpTail == KEYBUFSIZE) - kpTail = 0; - DosReleaseMutexSem(hmtxKeyBuf); - - /* Compensate for the 0xE0 character */ - if (kp.XlatedScan && kp.XlatedChar == 0xE0) - kp.XlatedChar = 0; - - /* Determine type of keyboard event */ - memset(&evt,0,sizeof(evt)); - if (kp.KbdDDFlagWord & KEY_RELEASE) - evt.what = EVT_KEYUP; - else - evt.what = EVT_KEYDOWN; - - /* Convert keyboard codes */ - scan = kp.MonFlagWord >> 8; - if (evt.what == EVT_KEYUP) { - /* Get message for keyup code from table of cached down values */ - evt.message = keyUpMsg[scan]; - keyUpMsg[scan] = 0; - oldKeyMessage = -1; - } - else { - evt.message = ((ulong)scan << 8) | kp.XlatedChar; - if (evt.message == keyUpMsg[scan]) { - evt.what = EVT_KEYREPEAT; - evt.message |= 0x10000; - } - oldKeyMessage = evt.message & 0x0FFFF; - keyUpMsg[scan] = (ushort)evt.message; - } - - /* Convert shift state modifiers */ - if (kp.u.ShiftState & 0x0001) - evt.modifiers |= EVT_RIGHTSHIFT; - if (kp.u.ShiftState & 0x0002) - evt.modifiers |= EVT_LEFTSHIFT; - if (kp.u.ShiftState & 0x0100) - evt.modifiers |= EVT_LEFTCTRL; - if (kp.u.ShiftState & 0x0200) - evt.modifiers |= EVT_LEFTALT; - if (kp.u.ShiftState & 0x0400) - evt.modifiers |= EVT_RIGHTCTRL; - if (kp.u.ShiftState & 0x0800) - evt.modifiers |= EVT_RIGHTALT; - EVT.oldMove = -1; - - /* Add time stamp and add the event to the queue */ - evt.when = key.time; - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - - /* Don't just flush because that terminally confuses the monitor */ - do { - KbdCharIn(&key, IO_NOWAIT, 0); - } while (key.fbStatus & KBDTRF_FINAL_CHAR_IN); - - /* Pump all mouse messages */ - KbdGetStatus(&keyInfo,0); - /* Check return code - mouse may not be operational!! */ - if (MouGetNumQueEl(&mqueue,_EVT_hMouse) == NO_ERROR) { - while (mqueue.cEvents) { - while (mqueue.cEvents--) { - memset(&evt,0,sizeof(evt)); - mWait = MOU_NOWAIT; - MouReadEventQue(&mouse,&mWait,_EVT_hMouse); - - /* Update the mouse position. We get the mouse coordinates - * in mickeys so we have to translate these into pixels and - * move our mouse position. If we don't do this, OS/2 gives - * us the coordinates in character positions since it still - * thinks we are in text mode! - */ - EVT.mx += MickeyToPixel(mouse.col); - EVT.my += MickeyToPixel(mouse.row); - if (EVT.mx < 0) EVT.mx = 0; - if (EVT.my < 0) EVT.my = 0; - if (EVT.mx > rangeX) EVT.mx = rangeX; - if (EVT.my > rangeY) EVT.my = rangeY; - evt.where_x = EVT.mx; - evt.where_y = EVT.my; - evt.relative_x = mouse.col; - evt.relative_y = mouse.row; - evt.when = key.time; - if (mouse.fs & (MOUSE_BN1_DOWN | MOUSE_MOTION_WITH_BN1_DOWN)) - evt.modifiers |= EVT_LEFTBUT; - if (mouse.fs & (MOUSE_BN2_DOWN | MOUSE_MOTION_WITH_BN2_DOWN)) - evt.modifiers |= EVT_RIGHTBUT; - if (mouse.fs & (MOUSE_BN3_DOWN | MOUSE_MOTION_WITH_BN3_DOWN)) - evt.modifiers |= EVT_MIDDLEBUT; - if (keyInfo.fsState & 0x0001) - evt.modifiers |= EVT_RIGHTSHIFT; - if (keyInfo.fsState & 0x0002) - evt.modifiers |= EVT_LEFTSHIFT; - if (keyInfo.fsState & 0x0100) - evt.modifiers |= EVT_LEFTCTRL; - if (keyInfo.fsState & 0x0200) - evt.modifiers |= EVT_LEFTALT; - if (keyInfo.fsState & 0x0400) - evt.modifiers |= EVT_RIGHTCTRL; - if (keyInfo.fsState & 0x0800) - evt.modifiers |= EVT_RIGHTALT; - - /* Check for left mouse click events */ - /* 0x06 == (MOUSE_BN1_DOWN | MOUSE_MOTION_WITH_BN1_DOWN) */ - if (((mouse.fs & 0x0006) && !(oldMouseState & 0x0006)) - || (!(mouse.fs & 0x0006) && (oldMouseState & 0x0006))) { - if (mouse.fs & 0x0006) - evt.what = EVT_MOUSEDOWN; - else - evt.what = EVT_MOUSEUP; - evt.message = EVT_LEFTBMASK; - EVT.oldMove = -1; - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - - /* Check for right mouse click events */ - /* 0x0018 == (MOUSE_BN2_DOWN | MOUSE_MOTION_WITH_BN2_DOWN) */ - if (((mouse.fs & 0x0018) && !(oldMouseState & 0x0018)) - || (!(mouse.fs & 0x0018) && (oldMouseState & 0x0018))) { - if (mouse.fs & 0x0018) - evt.what = EVT_MOUSEDOWN; - else - evt.what = EVT_MOUSEUP; - evt.message = EVT_RIGHTBMASK; - EVT.oldMove = -1; - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - - /* Check for middle mouse click events */ - /* 0x0060 == (MOUSE_BN3_DOWN | MOUSE_MOTION_WITH_BN3_DOWN) */ - if (((mouse.fs & 0x0060) && !(oldMouseState & 0x0060)) - || (!(mouse.fs & 0x0060) && (oldMouseState & 0x0060))) { - if (mouse.fs & 0x0060) - evt.what = EVT_MOUSEDOWN; - else - evt.what = EVT_MOUSEUP; - evt.message = EVT_MIDDLEBMASK; - EVT.oldMove = -1; - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - - /* Check for mouse movement event */ - if (mouse.fs & 0x002B) { - evt.what = EVT_MOUSEMOVE; - if (EVT.oldMove != -1) { - EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one */ - EVT.evtq[EVT.oldMove].where_y = evt.where_y; - } - else { - EVT.oldMove = EVT.freeHead; /* Save id of this move event */ - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - } - - /* Save current mouse state */ - oldMouseState = mouse.fs; - } - MouGetNumQueEl(&mqueue,_EVT_hMouse); - } - noInput = FALSE; - } - - /* If there was no input available, give up the current timeslice - * Note: DosSleep(0) will effectively do nothing if no other thread is ready. Hence - * DosSleep(0) will still use 100% CPU _but_ should not interfere with other programs. - */ - if (noInput) - DosSleep(0); -} - -/**************************************************************************** -REMARKS: -This macro/function is used to converts the scan codes reported by the -keyboard to our event libraries normalised format. We only have one scan -code for the 'A' key, and use shift modifiers to determine if it is a -Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, -but the OS gives us 'cooked' scan codes, we have to translate them back -to the raw format. -****************************************************************************/ -#define _EVT_maskKeyCode(evt) - -/**************************************************************************** -REMARKS: -Keyboard monitor thread. Needed to catch both keyup and keydown events. -****************************************************************************/ -static void _kbdMonThread( - void *params) -{ - APIRET rc; - KEYPACKET kp; - USHORT count = sizeof(KEYPACKET); - MONBUF monInbuf; - MONBUF monOutbuf; - int kpNew; - - /* Raise thread priority for higher responsiveness */ - DosSetPriority(PRTYS_THREAD, PRTYC_TIMECRITICAL, 0, 0); - monInbuf.cb = sizeof(monInbuf) - sizeof(monInbuf.cb); - monOutbuf.cb = sizeof(monOutbuf) - sizeof(monOutbuf.cb); - bMonRunning = FALSE; - - /* Register the buffers to be used for monitoring for current session */ - if (DosMonReg(_EVT_hKbdMon, &monInbuf, (ULONG*)&monOutbuf,MONITOR_END, -1)) { - DosPostEventSem(hevStart); /* unblock the main thread */ - return; - } - - /* Unblock the main thread and tell it we're OK*/ - bMonRunning = TRUE; - DosPostEventSem(hevStart); - while (bMonRunning) { /* Start an endless loop */ - /* Read data from keyboard driver */ - rc = DosMonRead((PBYTE)&monInbuf, IO_WAIT, (PBYTE)&kp, (PUSHORT)&count); - if (rc) { -#ifdef CHECKED - if (bMonRunning) - printf("Error in DosMonRead, rc = %ld\n", rc); -#endif - bMonRunning = FALSE; - return; - } - - /* Pass FLUSH packets immediately */ - if (kp.MonFlagWord & 4) { -#ifdef CHECKED - printf("Flush packet!\n"); -#endif - DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count); - continue; - } - - /*TODO: to be removed */ - /* Skip extended scancodes & some others */ - if (((kp.MonFlagWord >> 8) == 0xE0) || ((kp.KbdDDFlagWord & 0x0F) == 0x0F)) { - DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count); - continue; - } - -/* printf("RawScan = %X, XlatedScan = %X, fbStatus = %X, KbdDDFlags = %X\n", */ -/* kp.MonFlagWord >> 8, kp.XlatedScan, kp.u.ShiftState, kp.KbdDDFlagWord); */ - - /* Protect access to buffer with mutex semaphore */ - rc = DosRequestMutexSem(hmtxKeyBuf, 1000); - if (rc) { -#ifdef CHECKED - printf("Can't get access to mutex, rc = %ld\n", rc); -#endif - bMonRunning = FALSE; - return; - } - - /* Store packet in circular buffer, drop it if it's full */ - kpNew = kpHead + 1; - if (kpNew == KEYBUFSIZE) - kpNew = 0; - if (kpNew != kpTail) { - memcpy(&keyMonPkts[kpHead], &kp, sizeof(KEYPACKET)); - /* TODO: fix this! */ - /* Convert break to make code */ - keyMonPkts[kpHead].MonFlagWord &= 0x7FFF; - kpHead = kpNew; - } - DosReleaseMutexSem(hmtxKeyBuf); - - /* Finally write the packet */ - rc = DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count); - if (rc) { -#ifdef CHECKED - if (bMonRunning) - printf("Error in DosMonWrite, rc = %ld\n", rc); -#endif - bMonRunning = FALSE; - return; - } - } - (void)params; -} - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _EVT_abort( - int signal) -{ - EVT_exit(); - PM_fatalError("Unhandled exception!"); -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -void EVTAPI EVT_init( - _EVT_mouseMoveHandler mouseMove) -{ - ushort stat; - - /* Initialise the event queue */ - PM_init(); - EVT.mouseMove = mouseMove; - initEventQueue(); - oldMouseState = 0; - oldKeyMessage = 0; - memset(keyUpMsg,0,sizeof(keyUpMsg)); - - /* Open the mouse driver, and set it up to report events in mickeys */ - MouOpen(NULL,&_EVT_hMouse); - stat = 0x7F; - MouSetEventMask(&stat,_EVT_hMouse); - stat = (MOU_NODRAW | MOU_MICKEYS) << 8; - MouSetDevStatus(&stat,_EVT_hMouse); - - /* Open the keyboard monitor */ - if (DosMonOpen((PSZ)"KBD$", &_EVT_hKbdMon)) - PM_fatalError("Unable to open keyboard monitor!"); - - /* Create event semaphore, the monitor will post it when it's initalized */ - if (DosCreateEventSem(NULL, &hevStart, 0, FALSE)) - PM_fatalError("Unable to create event semaphore!"); - - /* Create mutex semaphore protecting the keypacket buffer */ - if (DosCreateMutexSem(NULL, &hmtxKeyBuf, 0, FALSE)) - PM_fatalError("Unable to create mutex semaphore!"); - - /* Start keyboard monitor thread, use 32K stack */ - kbdMonTID = _beginthread(_kbdMonThread, NULL, 0x8000, NULL); - - /* Now block until the monitor thread is up and running */ - /* Give the thread one second */ - DosWaitEventSem(hevStart, 1000); - if (!bMonRunning) { /* Check the thread is OK */ - DosMonClose(_EVT_hKbdMon); - PM_fatalError("Keyboard monitor thread didn't initialize!"); - } - - /* Catch program termination signals so we can clean up properly */ - signal(SIGABRT, _EVT_abort); - signal(SIGFPE, _EVT_abort); - signal(SIGINT, _EVT_abort); -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - rangeX = xRes; - rangeY = yRes; -} - -/**************************************************************************** -REMARKS -Modifes the mouse coordinates as necessary if scaling to OS coordinates, -and sets the OS mouse cursor position. -****************************************************************************/ -#define _EVT_setMousePos(x,y) - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVT_resume(void) -{ - /* Do nothing for OS/2 */ -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVT_suspend(void) -{ - /* Do nothing for OS/2 */ -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVT_exit(void) -{ - APIRET rc; - - /* Restore signal handlers */ - signal(SIGABRT, SIG_DFL); - signal(SIGFPE, SIG_DFL); - signal(SIGINT, SIG_DFL); - - /* Close the mouse driver */ - MouClose(_EVT_hMouse); - - /* Stop the keyboard monitor thread and close the monitor */ - bMonRunning = FALSE; - rc = DosKillThread(kbdMonTID); -#ifdef CHECKED - if (rc) - printf("DosKillThread failed, rc = %ld\n", rc); -#endif - rc = DosMonClose(_EVT_hKbdMon); -#ifdef CHECKED - if (rc) { - printf("DosMonClose failed, rc = %ld\n", rc); - } -#endif - DosCloseEventSem(hevStart); - DosCloseMutexSem(hmtxKeyBuf); - KbdFlushBuffer(0); -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h b/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h deleted file mode 100644 index 28d39fb..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h +++ /dev/null @@ -1,165 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit OS/2 -* -* Description: Include file to include all OS/2 keyboard monitor stuff. -* -****************************************************************************/ - -/* Monitors stuff */ - -#define MONITOR_DEFAULT 0x0000 -#define MONITOR_BEGIN 1 -#define MONITOR_END 2 - -typedef SHANDLE HMONITOR; -typedef HMONITOR *PHMONITOR; - -typedef struct _KEYPACKET { - USHORT MonFlagWord; - UCHAR XlatedChar; - UCHAR XlatedScan; - UCHAR DBCSStatus; - UCHAR DBCSShift; - - union - { - USHORT ShiftState; - USHORT LayerIndex; - } u; - - ULONG Milliseconds; - USHORT KbdDDFlagWord; -} KEYPACKET; - -typedef struct _MLNPACKET { - USHORT MonFlagWord; - USHORT IOCTL; - USHORT CPId; - USHORT CPIndex; - ULONG Reserved; - USHORT KbdDDFlagWord; -} MLNPACKET; - -/* DBCSStatus */ - -#define SF_SHIFTS 1 /* If set to 1, shift status returned without a character */ -#define SF_NOTCHAR 2 /* 0 - Scan code is a character */ - /* 1 - Scan code is not a character; */ - /* instead it is an extended key code from the keyboard. */ -#define SF_IMMEDIATE 32 /* If set to 1, immediate conversion requested */ -#define SF_TYPEMASK 192 /* Has the following values: */ - /* 00 - Undefined */ - /* 01 - Final character; interim character flag is turned off */ - /* 10 - Interim character */ - /* 11 - Final character; interim character flag is turned on. */ -/* MonFlagWord */ - -#define MF_OPEN 1 /* open */ -#define MF_CLOSE 2 /* close */ -#define MF_FLUSH 4 /* is flush packet */ - -/* KbdDDFlagWord */ - -#define KF_NOTSQPACKET 1024 /* Don't put this packet in SQ buffer */ -#define KF_ACCENTEDKEY 512 /* Key was translated using previous accent. */ -#define KF_MULTIMAKE 256 /* Key was repeated make of a toggle key. */ -#define KF_SECONDARYKEY 128 /* Previous scan code was the E0 prefix code. */ -#define KF_KEYBREAK 64 /* This is the break of the key. */ -#define KF_KEYTYPEMASK 63 /* Isolates the Key Type field of DDFlags. */ -#define KF_UNDEFKEY 63 /* Key packet is undefined */ -#define KF_SYSREQKEY 23 /* This key packet is the SysReq key (4990) */ -#define KF_PRINTFLUSHKEY 22 /* This packet is Ct-Alt-PrtScr */ -#define KF_PSPRINTECHOKEY 21 /* This packet is Ctl-P */ -#define KF_PRINTECHOKEY 20 /* This packet is Ctl-PrtScr */ -#define KF_PRTSCRKEY 19 /* This packet is PrtScr */ -#define KF_PSBREAKKEY 18 /* This packet is Ctl-C */ -#define KF_BREAKKEY 17 /* This packet is Ctl-Break */ -#define KF_ACCENTKEY 16 /* This packet is an accent key */ -#define KF_XRORPNOT 13 /* This packet is a Read or Peek Notification Pct. */ -#define KF_MLNOTIFICATION 14 /* packet is a Multi-Layer NLS packet */ -#define KF_HOTKEYPACKET 12 /* This packet is the hot key. */ -#define KF_BADKEYCOMBO 11 /* Accent/char combo undefined, beep only. */ -#define KF_WAKEUPKEY 10 /* This packet is one following PAUSEKEY */ -#define KF_PSPAUSEKEY 9 /* This packet is Ctl-S */ -#define KF_PAUSEKEY 8 /* This packet is Ctl-Numlock or PAUSE */ -#define KF_SHIFTMASK 7 /* Key is a shift Key */ -#define KF_DUMPKEY 6 /* This packet is Ctl-Numlock-NumLock */ -#define KF_REBOOTKEY 5 /* This packet is Ctl-Alt-Del */ -#define KF_RESENDCODE 4 /* This packet is resend code from controller */ -#define KF_OVERRUNCODE 3 /* This packet is overrun code from controller */ -#define KF_SECPREFIXCODE 2 /* This packet is E0/E1 scan code */ -#define KF_ACKCODE 1 /* This packet is ack code from keyboard */ - - -typedef struct _MONBUF { - USHORT cb; - KEYPACKET Buffer; - BYTE Reserved[20]; -} MONBUF; - -#define RS_SYSREG 32768 /* Bit 15 SysReq key down */ -#define RS_CAPSLOCK 16384 /* Bit 14 Caps Lock key down */ -#define RS_NUMLOCK 8192 /* Bit 13 NumLock key down */ -#define RS_SCROLLLOCK 4096 /* Bit 12 Scroll Lock key down */ -#define RS_RALT 2048 /* Bit 11 Right Alt key down */ -#define RS_RCONTROL 1024 /* Bit 10 Right Ctrl key down */ -#define RS_LALT 512 /* Bit 9 Left Alt key down */ -#define RS_LCONTROL 256 /* Bit 8 Left Ctrl key down */ -#define RS_INSERT 128 /* Bit 7 Insert on */ -#define RS_CAPS 64 /* Bit 6 Caps Lock on */ -#define RS_NUM 32 /* Bit 5 NumLock on */ -#define RS_SCROLL 16 /* Bit 4 Scroll Lock on */ -#define RS_ALT 8 /* Bit 3 Either Alt key down */ -#define RS_CONTROL 4 /* Bit 2 Either Ctrl key down */ -#define RS_LSHIFT 2 /* Bit 1 Left Shift key down */ -#define RS_RSHIFT 1 /* Bit 0 Right Shift key down */ - - -#define CS_RCONTROL 91 /* Right Control */ -#define CS_LSHIFT 42 /* Left Shift */ -#define CS_RSHIFT 54 /* Right Shift */ -#define CS_LALT 56 /* Left Alt */ -#define CS_RALT 94 /* Right Alt */ - - -/* DosMon* prototypes */ -#ifdef __EMX__ - #define APIRET16 USHORT - #define APIENTRY16 -#else - #define DosMonOpen DOS16MONOPEN - #define DosMonClose DOS16MONCLOSE - #define DosMonReg DOS16MONREG - #define DosMonRead DOS16MONREAD - #define DosMonWrite DOS16MONWRITE - #define DosGetInfoSeg DOS16GETINFOSEG -#endif - -APIRET16 APIENTRY16 DosMonOpen (PSZ pszDevName, PHMONITOR phmon); -APIRET16 APIENTRY16 DosMonClose (HMONITOR hmon); -APIRET16 APIENTRY16 DosMonReg (HMONITOR hmon, MONBUF *pbInBuf, /*MONBUF*/ULONG *pbOutBuf, USHORT fPosition, USHORT usIndex); -APIRET16 APIENTRY16 DosMonRead (PBYTE pbInBuf, USHORT fWait, PBYTE pbDataBuf, PUSHORT pcbData); -APIRET16 APIENTRY16 DosMonWrite (PBYTE pbOutBuf, PBYTE pbDataBuf, USHORT cbData); diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h deleted file mode 100644 index e7aa1c6..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h +++ /dev/null @@ -1,41 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit OS/2 -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ - -#define INCL_DOSPROFILE -#define INCL_DOSERRORS -#define INCL_DOS -#define INCL_SUB -#define INCL_VIO -#define INCL_KBD -#include -#include -#include "os2/mon.h" - -void __PM_checkConsoleSwitch(void); diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c b/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c deleted file mode 100644 index 756eead..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c +++ /dev/null @@ -1,2008 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit OS/2 -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include "pm_help.h" -#include "mtrr.h" -#include -#include -#include -#include -#ifndef __EMX__ -#include -#endif -#define INCL_DOSERRORS -#define INCL_DOS -#define INCL_SUB -#define INCL_VIO -#define INCL_KBD -#include - -/* Semaphore for communication with our background daemon */ -#define SHAREDSEM ((PSZ)"\\SEM32\\SDD\\DAEMON") -#define DAEMON_NAME "SDDDAEMN.EXE" - -/*--------------------------- Global variables ----------------------------*/ - -/* Public structures used to communicate with VIDEOPMI for implementing - * the ability to call the real mode BIOS functions. - */ - -typedef struct _VIDEOMODEINFO { - ULONG miModeId; - USHORT usType; - USHORT usInt10ModeSet; - USHORT usXResolution; - USHORT usYResolution; - ULONG ulBufferAddress; - ULONG ulApertureSize; - BYTE bBitsPerPixel; - BYTE bBitPlanes; - BYTE bXCharSize; - BYTE bYCharSize; - USHORT usBytesPerScanLine; - USHORT usTextRows; - ULONG ulPageLength; - ULONG ulSaveSize; - BYTE bVrtRefresh; - BYTE bHrtRefresh; - BYTE bVrtPolPos; - BYTE bHrtPolPos; - CHAR bRedMaskSize; - CHAR bRedFieldPosition; - CHAR bGreenMaskSize; - CHAR bGreenFieldPosition; - CHAR bBlueMaskSize; - CHAR bBlueFieldPosition; - CHAR bRsvdMaskSize; - CHAR bRsvdFieldPosition; - ULONG ulColors; - ULONG ulReserved[3]; - } VIDEOMODEINFO, FAR *PVIDEOMODEINFO; - -typedef struct _ADAPTERINFO { - ULONG ulAdapterID; - CHAR szOEMString[128]; - CHAR szDACString[128]; - CHAR szRevision[128]; - ULONG ulTotalMemory; - ULONG ulMMIOBaseAddress; - ULONG ulPIOBaseAddress; - BYTE bBusType; - BYTE bEndian; - USHORT usDeviceBusID; - USHORT usVendorBusID; - USHORT SlotID; - } ADAPTERINFO, FAR *PADAPTERINFO; - -typedef struct _VIDEO_ADAPTER { - void *hvideo; - ADAPTERINFO Adapter; - VIDEOMODEINFO ModeInfo; - } VIDEO_ADAPTER, FAR *PVIDEO_ADAPTER; - -/* PMIREQUEST_SOFTWAREINT structures from OS/2 DDK */ - -typedef struct { - ULONG ulFlags; /* VDM initialization type */ -#define VDM_POSTLOAD 0x1 /* adapter just loaded, used internally for initialization */ -#define VDM_INITIALIZE 0x2 /* force initialization of a permanently open VDM, even if previously initialized */ -#define VDM_TERMINATE_POSTINITIALIZE 0x6 /*start VDM with initialization, but close it afterwards (includes VDM_INITIALIZE) */ -#define VDM_QUERY_CAPABILITY 0x10 /* query the current int 10 capability */ -#define VDM_FULL_VDM_CREATED 0x20 /* a full VDM is created */ -#define VDM_MINI_VDM_CREATED 0x40 /* a mini VDM is created */ -#define VDM_MINI_VDM_SUPPORTED 0x80 /* mini VDM support is available */ - PCHAR szName; /* VDM initialization program */ - PCHAR szArgs; /* VDM initialization arguments */ - }INITVDM; - -typedef struct { - BYTE bBufferType; -#define BUFFER_NONE 0 -#define INPUT_BUFFER 1 -#define OUTPUT_BUFFER 2 - BYTE bReserved; - BYTE bSelCRF; - BYTE bOffCRF; - PVOID pAddress; - ULONG ulSize; - } BUFFER, *PBUFFER; - -typedef struct vcrf_s { - ULONG reg_eax; - ULONG reg_ebx; - ULONG reg_ecx; - ULONG reg_edx; - ULONG reg_ebp; - ULONG reg_esi; - ULONG reg_edi; - ULONG reg_ds; - ULONG reg_es; - ULONG reg_fs; - ULONG reg_gs; - ULONG reg_cs; - ULONG reg_eip; - ULONG reg_eflag; - ULONG reg_ss; - ULONG reg_esp; - } VCRF; - -typedef struct { - ULONG ulBIOSIntNo; - VCRF aCRF; - BUFFER pB[2]; - } INTCRF; - -#define PMIREQUEST_LOADPMIFILE 21 -#define PMIREQUEST_IDENTIFYADAPTER 22 -#define PMIREQUEST_SOFTWAREINT 23 - -#ifdef PTR_DECL_IN_FRONT -#define EXPENTRYP * EXPENTRY -#else -#define EXPENTRYP EXPENTRY * -#endif - -/* Entry point to VIDEOPMI32Request. This may be overridden by external - * code that has already loaded VIDEOPMI to avoid loading it twice. - */ - -APIRET (EXPENTRYP PM_VIDEOPMI32Request)(PVIDEO_ADAPTER, ULONG, PVOID, PVOID) = NULL; -static ibool haveInt10 = -1; /* True if we have Int 10 support */ -static ibool useVPMI = true; /* False if VIDEOPMI unavailable */ -static VIDEO_ADAPTER Adapter; /* Video adapter for VIDEOPMI */ -static uchar RMBuf[1024]; /* Fake real mode transfer buffer */ -static uint VESABuf_len = 1024;/* Length of the VESABuf buffer */ -static void *VESABuf_ptr = NULL;/* Near pointer to VESABuf */ -static uint VESABuf_rseg; /* Real mode segment of VESABuf */ -static uint VESABuf_roff; /* Real mode offset of VESABuf */ -static uchar * lowMem = NULL; -static ibool isSessionSwitching = false; -static ulong parmsIn[4]; /* Must not cross 64Kb boundary! */ -static ulong parmsOut[4]; /* Must not cross 64Kb boundary! */ -extern ushort _PM_gdt; -static void (PMAPIP fatalErrorCleanup)(void) = NULL; - -/* DosSysCtl prototype. It is not declared in the headers but it is in the - * standard import libraries (DOSCALLS.876). Funny. - */ -APIRET APIENTRY DosSysCtl(ULONG ulFunction, PVOID pvData); - -/* This is the stack size for the threads that track the session switch event */ -#define SESSION_SWITCH_STACK_SIZE 32768 - -typedef struct { - VIOMODEINFO vmi; - USHORT CursorX; - USHORT CursorY; - UCHAR FrameBuffer[1]; - } CONSOLE_SAVE; - -typedef struct _SESWITCHREC { - /* The following variable is volatile because of PM_SUSPEND_APP */ - volatile int Flags; /* -1 or PM_DEACTIVATE or PM_REACTIVATE */ - PM_saveState_cb Callback; /* Save/restore context callback */ - HMTX Mutex; /* Exclusive access mutex */ - HEV Event; /* Posted after callback is called */ - } SESWITCHREC; - -/* Page sized block cache */ - -#define PAGES_PER_BLOCK 32 -#define PAGE_BLOCK_SIZE (PAGES_PER_BLOCK * PM_PAGE_SIZE + (PM_PAGE_SIZE-1) + sizeof(pageblock)) -#define FREELIST_NEXT(p) (*(void**)(p)) -typedef struct pageblock { - struct pageblock *next; - struct pageblock *prev; - void *freeListStart; - void *freeList; - void *freeListEnd; - int freeCount; - PM_lockHandle lockHandle; - } pageblock; - -static pageblock *pageBlocks = NULL; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -PARAMETERS: -func - Helper device driver function to call - -RETURNS: -First return value from the device driver in parmsOut[0] - -REMARKS: -Function to open our helper device driver, call it and close the file -handle. Note that we have to open the device driver for every call because -of two problems: - - 1. We cannot open a single file handle in a DLL that is shared amongst - programs, since every process must have it's own open file handle. - - 2. For some reason there appears to be a limit of about 12 open file - handles on a device driver in the system. Hence when we open more - than about 12 file handles things start to go very strange. - -Hence we simply open the file handle every time that we need to call the -device driver to work around these problems. -****************************************************************************/ -static ulong CallSDDHelp( - int func) -{ - static ulong inLen; /* Must not cross 64Kb boundary! */ - static ulong outLen; /* Must not cross 64Kb boundary! */ - HFILE hSDDHelp; - ULONG rc; - ulong result; - - if ((rc = DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0, - FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, - NULL)) != 0) { - if (rc == 4) { /* Did we run out of file handles? */ - ULONG ulNewFHs; - LONG lAddFHs = 5; - - if (DosSetRelMaxFH(&lAddFHs, &ulNewFHs) != 0) - PM_fatalError("Failed to raise the file handles limit!"); - else { - if ((rc = DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0, - FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, - NULL)) != 0) { - PM_fatalError("Unable to open SDDHELP$ helper device driver! (#2)"); - } - } - } - else - PM_fatalError("Unable to open SDDHELP$ helper device driver!"); - } - if (DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,func, - &parmsIn, inLen = sizeof(parmsIn), &inLen, - &parmsOut, outLen = sizeof(parmsOut), &outLen) != 0) - PM_fatalError("Failure calling SDDHELP$ helper device driver!"); - DosClose(hSDDHelp); - return parmsOut[0]; -} - -/**************************************************************************** -REMARKS: -Determine if we're running on a DBCS system. -****************************************************************************/ -ibool __IsDBCSSystem(void) -{ - CHAR achDBCSInfo[12]; - COUNTRYCODE ccStruct = {0, 0}; - - memset(achDBCSInfo, 0, 12); - - /* Get the DBCS vector - if it's not empty, we're on DBCS */ - DosQueryDBCSEnv(sizeof(achDBCSInfo), &ccStruct, achDBCSInfo); - if (achDBCSInfo[0] != 0) - return true; - else - return false; -} - -/**************************************************************************** -REMARKS: -Determine if PMSHELL is running - if it isn't, we can't use certain calls -****************************************************************************/ -ibool __isShellLoaded(void) -{ - PVOID ptr; - - if (DosGetNamedSharedMem(&ptr, (PSZ)"\\SHAREMEM\\PMGLOBAL.MEM", PAG_READ) == NO_ERROR) { - DosFreeMem(ptr); - return true; - } - return false; -} - -/**************************************************************************** -REMARKS: -Initialise the PM library and connect to our helper device driver. If we -cannot connect to our helper device driver, we bail out with an error -message. -****************************************************************************/ -void PMAPI PM_init(void) -{ - if (!lowMem) { - /* Obtain the 32->16 callgate from the device driver to enable IOPL */ - if ((_PM_gdt = CallSDDHelp(PMHELP_GETGDT32)) == 0) - PM_fatalError("Unable to obtain call gate selector!"); - - PM_setIOPL(3); - - /* Map the first Mb of physical memory into lowMem */ - if ((lowMem = PM_mapPhysicalAddr(0,0xFFFFF,true)) == NULL) - PM_fatalError("Unable to map first Mb physical memory!"); - - /* Initialise the MTRR interface functions */ - MTRR_init(); - } -} - -/**************************************************************************** -REMARKS: -Initialise the PM library for BIOS access via VIDEOPMI. This should work -with any GRADD driver, including SDD/2. -****************************************************************************/ -static ibool InitInt10(void) -{ - HMODULE hModGENPMI,hModSDDPMI,hModVideoPMI; - CHAR buf[80],path[_MAX_PATH]; - HEV hevDaemon = NULLHANDLE; - RESULTCODES resCodes; - - if (haveInt10 == -1) { - /* Connect to VIDEOPMI and get entry point. Note that we only - * do this if GENPMI or SDDPMI are already loaded, since we need - * a GRADD based driver for this to work. - */ - PM_init(); - haveInt10 = false; - if (DosQueryModuleHandle((PSZ)"GENPMI.DLL",&hModGENPMI) != 0) - hModGENPMI = NULLHANDLE; - if (DosQueryModuleHandle((PSZ)"SDDPMI.DLL",&hModSDDPMI) != 0) - hModSDDPMI = NULLHANDLE; - if (hModGENPMI || hModSDDPMI) { - if (DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"VIDEOPMI.DLL",&hModVideoPMI) == 0) { - if (DosQueryProcAddr(hModVideoPMI,0,(PSZ)"VIDEOPMI32Request",(void*)&PM_VIDEOPMI32Request) != 0) - PM_fatalError("Unable to get VIDEOPMI32Request entry point!"); - strcpy(path,"X:\\OS2\\SVGADATA.PMI"); - path[0] = PM_getBootDrive(); - if (PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_LOADPMIFILE,path,NULL) != 0) { - DosFreeModule(hModVideoPMI); - PM_VIDEOPMI32Request = NULL; - haveInt10 = false; - } - else { - /* Attempt to initialise the full VDM in the system. This will only - * work if VPRPMI.SYS is loaded, but it provides support for passing - * values in ES/DS/ESI/EDI between the BIOS which does not work with - * kernel VDM's in fixpacks earlier than FP15. FP15 and later and - * the new Warp 4.51 and Warp Server convenience packs should work - * fine with the kernel mini-VDM. - * - * Also the full VDM is the only solution for really old kernels - * (but GRADD won't run on them so this is superfluous ;-). - */ - INITVDM InitVDM = {VDM_INITIALIZE,NULL,NULL}; - PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&InitVDM,NULL); - haveInt10 = true; - } - } - } - else { - /* A GRADD driver isn't loaded, hence we can't use VIDEOPMI. But we will try - * to access the mini-VDM directly, first verifying that the support is - * available in the kernel (it should be for kernels that support GRADD). - * This may be needed in a command line boot or if non-GRADD driver is - * used (Matrox or classic VGA). - * Note: because of problems with mini-VDM support in the kernel, we have to - * spawn a daemon process that will do the actual mini-VDM access for us. - */ - /* Try to open shared semaphore to see if our daemon is already up */ - if (DosOpenEventSem(SHAREDSEM, &hevDaemon) == NO_ERROR) { - if (DosWaitEventSem(hevDaemon, 1) == NO_ERROR) { - /* If semaphore is posted, all is well */ - useVPMI = false; - haveInt10 = true; - } - } - else { - /* Create shared event semaphore */ - if (DosCreateEventSem(SHAREDSEM, &hevDaemon, DC_SEM_SHARED, FALSE) == NO_ERROR) { - PM_findBPD(DAEMON_NAME, path); - strcat(path, DAEMON_NAME); - if (DosExecPgm(buf, sizeof(buf), EXEC_BACKGROUND, (PSZ)DAEMON_NAME, - NULL, &resCodes, (PSZ)path) == NO_ERROR) { - /* The daemon was successfully spawned, now give it a sec to come up */ - if (DosWaitEventSem(hevDaemon, 2000) == NO_ERROR) { - /* It's up! */ - useVPMI = false; - haveInt10 = true; - } - } - } - } - } - } - return haveInt10; -} - -/**************************************************************************** -REMARKS: -We "probably" have BIOS access under OS/2 but we have to verify/initialize it -first. -****************************************************************************/ -ibool PMAPI PM_haveBIOSAccess(void) -{ - return InitInt10(); -} - -/**************************************************************************** -REMARKS: -Return the operating system type identifier. -****************************************************************************/ -long PMAPI PM_getOSType(void) -{ - return _OS_OS2; -} - -/**************************************************************************** -REMARKS: -Return the runtime type identifier. -****************************************************************************/ -int PMAPI PM_getModeType(void) -{ - return PM_386; -} - -/**************************************************************************** -REMARKS: -Add a file directory separator to the end of the filename. -****************************************************************************/ -void PMAPI PM_backslash( - char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '\\') { - s[pos] = '\\'; - s[pos+1] = '\0'; - } -} - -/**************************************************************************** -REMARKS: -Add a user defined PM_fatalError cleanup function. -****************************************************************************/ -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -/**************************************************************************** -REMARKS: -Report a fatal error condition and halt the program. -****************************************************************************/ -void PMAPI PM_fatalError( - const char *msg) -{ - /* Be prepare to be called recursively (failed to fail situation :-) */ - static int fatalErrorCount = 0; - if (fatalErrorCount++ == 0) { - if (fatalErrorCleanup) - fatalErrorCleanup(); - } - fprintf(stderr,"%s\n", msg); - exit(1); -} - -/**************************************************************************** -REMARKS: -Allocate the real mode VESA transfer buffer for communicating with the BIOS. -****************************************************************************/ -void * PMAPI PM_getVESABuf( - uint *len, - uint *rseg, - uint *roff) -{ - if (!VESABuf_ptr) { - /* Allocate a global buffer for communicating with the VESA VBE */ - if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) - return NULL; - } - *len = VESABuf_len; - *rseg = VESABuf_rseg; - *roff = VESABuf_roff; - return VESABuf_ptr; -} - -/**************************************************************************** -REMARKS: -Check if a key has been pressed. -****************************************************************************/ -int PMAPI PM_kbhit(void) -{ - KBDKEYINFO key; /* Must not cross a 64K boundary */ - - KbdPeek(&key, 0); - return (key.fbStatus & KBDTRF_FINAL_CHAR_IN); -} - -/**************************************************************************** -REMARKS: -Wait for and return the next keypress. -****************************************************************************/ -int PMAPI PM_getch(void) -{ - KBDKEYINFO key; /* Must not cross a 64K boundary */ - - KbdCharIn(&key,IO_WAIT,0); - return key.chChar; -} - -/**************************************************************************** -REMARKS: -Open a fullscreen console for output to the screen. This requires that -the application be a fullscreen VIO program. -****************************************************************************/ -PM_HWND PMAPI PM_openConsole( - PM_HWND hwndUser, - int device, - int xRes, - int yRes, - int bpp, - ibool fullScreen) -{ - (void)hwndUser; - (void)device; - (void)xRes; - (void)yRes; - (void)bpp; - (void)fullScreen; - return 0; -} - -/**************************************************************************** -REMARKS: -Find the size of the console state buffer. -****************************************************************************/ -int PMAPI PM_getConsoleStateSize(void) -{ - VIOMODEINFO vmi; - vmi.cb = sizeof (VIOMODEINFO); - VioGetMode (&vmi, (HVIO)0); - return sizeof (CONSOLE_SAVE) - 1 + vmi.col * vmi.row * 2; -} - -/**************************************************************************** -REMARKS: -Save the state of the console. -****************************************************************************/ -void PMAPI PM_saveConsoleState( - void *stateBuf, - PM_HWND hwndConsole) -{ - USHORT fblen; - CONSOLE_SAVE *cs = (CONSOLE_SAVE*)stateBuf; - VIOMODEINFO vmi; - - /* The reason for the VIOMODEINFO juggling is 16-bit code. Because the user - * allocates the state buffer, cd->vmi might be crossing the 64K boundary and - * the 16-bit API would fail. If we create another copy on stack, the compiler - * should ensure that the 64K boundary will not be crossed (it adjusts the stack - * if it should cross). - */ - vmi.cb = sizeof(VIOMODEINFO); - VioGetMode(&vmi,(HVIO)0); - memcpy(&cs->vmi, &vmi, sizeof(VIOMODEINFO)); - VioGetCurPos(&cs->CursorY, &cs->CursorX, (HVIO)0); - fblen = cs->vmi.col * cs->vmi.row * 2; - VioReadCellStr((PCH)cs->FrameBuffer, &fblen, 0, 0, (HVIO)0); -} - -/* Global variable to communicate between threads */ -static SESWITCHREC SesSwitchRec = { -1 }; - -/**************************************************************************** -REMARKS: -Called by external routines at least once per frame to check whenever a -session save/restore should be performed. Since we receive such notifications -asyncronously, we can't perform all required operations at that time. -****************************************************************************/ -void __PM_checkConsoleSwitch(void) -{ - int Flags, Mode; - PM_saveState_cb Callback; - - /* Quick optimized path for most common case */ - if (SesSwitchRec.Flags == -1) - return; - -again: - if (DosRequestMutexSem(SesSwitchRec.Mutex, 100)) - return; - Flags = SesSwitchRec.Flags; - Callback = SesSwitchRec.Callback; - SesSwitchRec.Flags = -1; - DosReleaseMutexSem(SesSwitchRec.Mutex); - - isSessionSwitching = true; /* Prevent VIO calls */ - Mode = Callback(Flags); - isSessionSwitching = false; - DosPostEventSem(SesSwitchRec.Event); - if (Flags == PM_DEACTIVATE && Mode == PM_SUSPEND_APP) - /* Suspend application until we switch back to our application */ - for (;;) { - DosSleep (500); - /* SesSwitchRec.Flags is volatile so optimizer - * won't load it into a register - */ - if (SesSwitchRec.Flags != -1) - goto again; - } -} - -/**************************************************************************** -REMARKS: -Waits until main thread processes the session switch event. -****************************************************************************/ -static void _PM_SessionSwitchEvent( - PM_saveState_cb saveState, - int flags) -{ - ULONG Count; - - if (DosRequestMutexSem(SesSwitchRec.Mutex, 10000)) - return; - - /* We're going to wait on that semaphore */ - DosResetEventSem(SesSwitchRec.Event, &Count); - SesSwitchRec.Callback = saveState; - SesSwitchRec.Flags = flags; - DosReleaseMutexSem(SesSwitchRec.Mutex); - - /* Now wait until all required operations are complete */ - DosWaitEventSem (SesSwitchRec.Event, 10000); -} - -/**************************************************************************** -REMARKS: -This is the thread responsible for tracking switches back to our -fullscreen session. -****************************************************************************/ -static void _PM_ConsoleSwitch( - PM_saveState_cb saveState) -{ - USHORT NotifyType; - - for (;;) { - if (VioModeWait(VMWR_POPUP, &NotifyType, 0) != 0) - break; - _PM_SessionSwitchEvent(saveState, PM_REACTIVATE); - } - VioModeUndo(UNDOI_RELEASEOWNER, UNDOK_ERRORCODE, (HVIO)0); -} - -/**************************************************************************** -REMARKS: -This is the thread responsible for tracking screen popups (usually fatal -error handler uses them). -****************************************************************************/ -static void _PM_ConsolePopup( - PM_saveState_cb saveState) -{ - USHORT NotifyType; - for (;;) { - if (VioSavRedrawWait(VSRWI_SAVEANDREDRAW, &NotifyType, 0) != 0) - break; - if (NotifyType == VSRWN_SAVE) - _PM_SessionSwitchEvent(saveState, PM_DEACTIVATE); - else if (NotifyType == VSRWN_REDRAW) - _PM_SessionSwitchEvent(saveState, PM_REACTIVATE); - } - VioSavRedrawUndo(UNDOI_RELEASEOWNER, UNDOK_ERRORCODE, (HVIO)0); -} - -/**************************************************************************** -REMARKS: -Set the suspend application callback for the fullscreen console. -****************************************************************************/ -void PMAPI PM_setSuspendAppCallback( - PM_saveState_cb saveState) -{ - /* If PM isn't loaded, this stuff will cause crashes! */ - if (__isShellLoaded()) { - if (saveState) { - /* Create the threads responsible for tracking console switches */ - SesSwitchRec.Flags = -1; - DosCreateMutexSem(NULL, &SesSwitchRec.Mutex, 0, FALSE); - DosCreateEventSem(NULL, &SesSwitchRec.Event, 0, FALSE); - _beginthread ((void(*)(void*))_PM_ConsoleSwitch,NULL,SESSION_SWITCH_STACK_SIZE, (void*)saveState); - _beginthread ((void(*)(void*))_PM_ConsolePopup,NULL,SESSION_SWITCH_STACK_SIZE, (void*)saveState); - } - else { - /* Kill the threads responsible for tracking console switches */ - VioModeUndo(UNDOI_RELEASEOWNER, UNDOK_TERMINATE, (HVIO)0); - VioSavRedrawUndo(UNDOI_RELEASEOWNER, UNDOK_TERMINATE, (HVIO)0); - DosCloseEventSem(SesSwitchRec.Event); - DosCloseMutexSem(SesSwitchRec.Mutex); - } - } -} - -/**************************************************************************** -REMARKS: -Restore the console state. -****************************************************************************/ -void PMAPI PM_restoreConsoleState( - const void *stateBuf, - PM_HWND hwndConsole) -{ - CONSOLE_SAVE *cs = (CONSOLE_SAVE *)stateBuf; - VIOMODEINFO vmi; - - if (!cs) - return; - - memcpy(&vmi, &cs->vmi, sizeof (VIOMODEINFO)); - VioSetMode(&vmi, (HVIO)0); - VioSetCurPos(cs->CursorY, cs->CursorX, (HVIO)0); - VioWrtCellStr((PCH)cs->FrameBuffer, cs->vmi.col * cs->vmi.row * 2,0, 0, (HVIO)0); -} - -/**************************************************************************** -REMARKS: -Close the fullscreen console. -****************************************************************************/ -void PMAPI PM_closeConsole( - PM_HWND hwndConsole) -{ - /* Kill the threads responsible for tracking console switches */ - PM_setSuspendAppCallback(NULL); - (void)hwndConsole; -} - -/**************************************************************************** -REMARKS: -Set the location of the OS console cursor. -****************************************************************************/ -void PM_setOSCursorLocation( - int x, - int y) -{ - /* If session switch is in progress, calling into VIO causes deadlocks! */ - /* Also this call to VIO screws up our console library on DBCS boxes... */ - if (!isSessionSwitching && !__IsDBCSSystem()) - VioSetCurPos(y,x,0); -} - -/**************************************************************************** -REMARKS: -Set the width of the OS console. -****************************************************************************/ -void PM_setOSScreenWidth( - int width, - int height) -{ - /* Nothing to do in here */ - (void)width; - (void)height; -} - -/**************************************************************************** -REMARKS: -Set the real time clock handler (used for software stereo modes). -****************************************************************************/ -ibool PMAPI PM_setRealTimeClockHandler( - PM_intHandler ih, - int frequency) -{ - /* TODO: Implement this! */ - (void)ih; - (void)frequency; - return false; -} - -/**************************************************************************** -REMARKS: -Set the real time clock frequency (for stereo modes). -****************************************************************************/ -void PMAPI PM_setRealTimeClockFrequency( - int frequency) -{ - /* TODO: Implement this! */ - (void)frequency; -} - -/**************************************************************************** -REMARKS: -Restore the original real time clock handler. -****************************************************************************/ -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - /* TODO: Implement this! */ -} - -/**************************************************************************** -REMARKS: -Return the current operating system path or working directory. -****************************************************************************/ -char * PMAPI PM_getCurrentPath( - char *path, - int maxLen) -{ - return getcwd(path,maxLen); -} - -/**************************************************************************** -REMARKS: -Return the drive letter for the boot drive. -****************************************************************************/ -char PMAPI PM_getBootDrive(void) -{ - ulong boot = 3; - DosQuerySysInfo(QSV_BOOT_DRIVE,QSV_BOOT_DRIVE,&boot,sizeof(boot)); - return (char)('a' + boot - 1); -} - -/**************************************************************************** -REMARKS: -Return the path to the VBE/AF driver files. -****************************************************************************/ -const char * PMAPI PM_getVBEAFPath(void) -{ - static char path[CCHMAXPATH]; - strcpy(path,"x:\\"); - path[0] = PM_getBootDrive(); - return path; -} - -/**************************************************************************** -REMARKS: -Return the path to the Nucleus driver files. -****************************************************************************/ -const char * PMAPI PM_getNucleusPath(void) -{ - static char path[CCHMAXPATH]; - if (getenv("NUCLEUS_PATH") != NULL) - return getenv("NUCLEUS_PATH"); - strcpy(path,"x:\\os2\\drivers"); - path[0] = PM_getBootDrive(); - PM_backslash(path); - strcat(path,"nucleus"); - return path; -} - -/**************************************************************************** -REMARKS: -Return the path to the Nucleus configuration files. -****************************************************************************/ -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[CCHMAXPATH]; - strcpy(path,PM_getNucleusPath()); - PM_backslash(path); - strcat(path,"config"); - return path; -} - -/**************************************************************************** -REMARKS: -Return a unique identifier for the machine if possible. -****************************************************************************/ -const char * PMAPI PM_getUniqueID(void) -{ - return PM_getMachineName(); -} - -/**************************************************************************** -REMARKS: -Get the name of the machine on the network. -****************************************************************************/ -const char * PMAPI PM_getMachineName(void) -{ - static char name[40],*env; - - if ((env = getenv("HOSTNAME")) != NULL) { - strncpy(name,env,sizeof(name)); - name[sizeof(name)-1] = 0; - return name; - } - return "OS2"; -} - -/**************************************************************************** -REMARKS: -Return a pointer to the real mode BIOS data area. -****************************************************************************/ -void * PMAPI PM_getBIOSPointer(void) -{ - PM_init(); - return lowMem + 0x400; -} - -/**************************************************************************** -REMARKS: -Return a pointer to 0xA0000 physical VGA graphics framebuffer. -****************************************************************************/ -void * PMAPI PM_getA0000Pointer(void) -{ - PM_init(); - return lowMem + 0xA0000; -} - -/**************************************************************************** -REMARKS: -Map a physical address to a linear address in the callers process. -****************************************************************************/ -void * PMAPI PM_mapPhysicalAddr( - ulong base, - ulong limit, - ibool isCached) -{ - ulong baseAddr,baseOfs,linear; - - /* Round the physical address to a 4Kb boundary and the limit to a - * 4Kb-1 boundary before passing the values to mmap. If we round the - * physical address, then we also add an extra offset into the address - * that we return. - */ - baseOfs = base & 4095; - baseAddr = base & ~4095; - limit = ((limit+baseOfs+1+4095) & ~4095)-1; - parmsIn[0] = baseAddr; - parmsIn[1] = limit; - parmsIn[2] = isCached; - if ((linear = CallSDDHelp(PMHELP_MAPPHYS)) == 0) - return NULL; - return (void*)(linear + baseOfs); -} - -/**************************************************************************** -REMARKS: -Free a physical address mapping allocated by PM_mapPhysicalAddr. -****************************************************************************/ -void PMAPI PM_freePhysicalAddr( - void *ptr, - ulong limit) -{ - parmsIn[0] = (ulong)ptr; - parmsIn[1] = limit; - CallSDDHelp(PMHELP_FREEPHYS); -} - -/**************************************************************************** -REMARKS: -Find the physical address of a linear memory address in current process. -****************************************************************************/ -ulong PMAPI PM_getPhysicalAddr( - void *p) -{ - parmsIn[0] = (ulong)p; - return CallSDDHelp(PMHELP_GETPHYSICALADDR); -} - -/**************************************************************************** -REMARKS: -Find the physical address of a linear memory address in current process. -****************************************************************************/ -ibool PMAPI PM_getPhysicalAddrRange( - void *p, - ulong length, - ulong *physAddress) -{ - parmsIn[0] = (ulong)p; - parmsIn[1] = (ulong)length; - parmsIn[2] = (ulong)physAddress; - return CallSDDHelp(PMHELP_GETPHYSICALADDRRANGE); -} - -/**************************************************************************** -REMARKS: -Sleep for the specified number of milliseconds. -****************************************************************************/ -void PMAPI PM_sleep( - ulong milliseconds) -{ - DosSleep(milliseconds); -} - -/**************************************************************************** -REMARKS: -Return the base I/O port for the specified COM port. -****************************************************************************/ -int PMAPI PM_getCOMPort( - int port) -{ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - } - return 0; -} - -/**************************************************************************** -REMARKS: -Return the base I/O port for the specified LPT port. -****************************************************************************/ -int PMAPI PM_getLPTPort( - int port) -{ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -/**************************************************************************** -REMARKS: -Allocate a block of shared memory. For Win9x we allocate shared memory -as locked, global memory that is accessible from any memory context -(including interrupt time context), which allows us to load our important -data structure and code such that we can access it directly from a ring -0 interrupt context. -****************************************************************************/ -void * PMAPI PM_mallocShared( - long size) -{ - parmsIn[0] = size; - return (void*)CallSDDHelp(PMHELP_MALLOCSHARED); -} - -/**************************************************************************** -REMARKS: -Free a block of shared memory. -****************************************************************************/ -void PMAPI PM_freeShared( - void *ptr) -{ - parmsIn[0] = (ulong)ptr; - CallSDDHelp(PMHELP_FREESHARED); -} - -/**************************************************************************** -REMARKS: -Map a linear memory address to the calling process address space. The -address will have been allocated in another process using the -PM_mapPhysicalAddr function. -****************************************************************************/ -void * PMAPI PM_mapToProcess( - void *base, - ulong limit) -{ - ulong baseAddr,baseOfs; - - /* Round the physical address to a 4Kb boundary and the limit to a - * 4Kb-1 boundary before passing the values to mmap. If we round the - * physical address, then we also add an extra offset into the address - * that we return. - */ - baseOfs = (ulong)base & 4095; - baseAddr = (ulong)base & ~4095; - limit = ((limit+baseOfs+1+4095) & ~4095)-1; - parmsIn[0] = (ulong)baseAddr; - parmsIn[1] = limit; - return (void*)(CallSDDHelp(PMHELP_MAPTOPROCESS)+baseOfs); -} - -/**************************************************************************** -REMARKS: -Map a real mode pointer to a protected mode pointer. -****************************************************************************/ -void * PMAPI PM_mapRealPointer( - uint r_seg, - uint r_off) -{ - if (r_seg == 0xFFFF) - return &RMBuf[r_off]; - return lowMem + MK_PHYS(r_seg,r_off); -} - -/**************************************************************************** -REMARKS: -Allocate a block of real mode memory -****************************************************************************/ -void * PMAPI PM_allocRealSeg( - uint size, - uint *r_seg, - uint *r_off) -{ - if (size > sizeof(RMBuf)) - return NULL; - *r_seg = 0xFFFF; - *r_off = 0x0000; - return &RMBuf; -} - -/**************************************************************************** -REMARKS: -Free a block of real mode memory. -****************************************************************************/ -void PMAPI PM_freeRealSeg( - void *mem) -{ - /* Nothing to do in here */ - (void)mem; -} - -#define INDPMI(reg) rmregs.aCRF.reg_##reg = regs->reg -#define OUTDPMI(reg) regs->reg = rmregs.aCRF.reg_##reg - -#define REG_OFFSET(field) (((ULONG)&(((VCRF*)0)->field)) / sizeof(ULONG)) - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt (parameters in DPMI compatible structure) -****************************************************************************/ -void PMAPI DPMI_int86( - int intno, - DPMI_regs *regs) -{ - INTCRF rmregs; - ulong eax = 0; - - if (!InitInt10()) - return; - memset(&rmregs, 0, sizeof(rmregs)); - rmregs.ulBIOSIntNo = intno; - INDPMI(eax); INDPMI(ebx); INDPMI(ecx); INDPMI(edx); INDPMI(esi); INDPMI(edi); - rmregs.aCRF.reg_ds = regs->ds; - rmregs.aCRF.reg_es = regs->es; - if (intno == 0x10) { - eax = rmregs.aCRF.reg_eax; - switch (eax & 0xFFFF) { - case 0x4F00: - /* We have to hack the way this function works, due to - * some bugs in the IBM mini-VDM BIOS support. Specifically - * we need to make the input buffer and output buffer the - * 'same' buffer, and that ES:SI points to the output - * buffer (ignored by the BIOS). The data will end up - * being returned in the input buffer, except for the - * first four bytes ('VESA') that will not be returned. - */ - rmregs.pB[0].bBufferType = INPUT_BUFFER; - rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); - rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); - rmregs.pB[0].pAddress = RMBuf; - rmregs.pB[0].ulSize = 4; - rmregs.pB[1].bBufferType = OUTPUT_BUFFER; - rmregs.pB[1].bSelCRF = REG_OFFSET(reg_es); - rmregs.pB[1].bOffCRF = REG_OFFSET(reg_esi); - rmregs.pB[1].pAddress = ((PBYTE)RMBuf)+4; - rmregs.pB[1].ulSize = 512-4; - break; - case 0x4F01: - rmregs.pB[0].bBufferType = OUTPUT_BUFFER; - rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); - rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); - rmregs.pB[0].pAddress = RMBuf; - rmregs.pB[0].ulSize = 256; - break; - case 0x4F02: - rmregs.pB[0].bBufferType = INPUT_BUFFER; - rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); - rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); - rmregs.pB[0].pAddress = RMBuf; - rmregs.pB[0].ulSize = 256; - break; - case 0x4F09: - rmregs.pB[0].bBufferType = INPUT_BUFFER; - rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); - rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); - rmregs.pB[0].pAddress = RMBuf; - rmregs.pB[0].ulSize = 1024; - break; - case 0x4F0A: - /* Due to bugs in the mini-VDM in OS/2, the 0x4F0A protected - * mode interface functions will not work (we never get any - * selectors returned), so we fail this function here. The - * rest of the VBE/Core driver will work properly if this - * function is failed, because the VBE 2.0 and 3.0 specs - * allow for this. - */ - regs->eax = 0x014F; - return; - } - } - if (useVPMI) - PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,NULL,&rmregs); - else { - DosSysCtl(6, &rmregs); - } - - OUTDPMI(eax); OUTDPMI(ebx); OUTDPMI(ecx); OUTDPMI(edx); OUTDPMI(esi); OUTDPMI(edi); - if (((regs->eax & 0xFFFF) == 0x004F) && ((eax & 0xFFFF) == 0x4F00)) { - /* Hack to fix up the missing 'VESA' string for mini-VDM */ - memcpy(RMBuf,"VESA",4); - } - regs->ds = rmregs.aCRF.reg_ds; - regs->es = rmregs.aCRF.reg_es; - regs->flags = rmregs.aCRF.reg_eflag; -} - -#define IN(reg) rmregs.reg = in->e.reg -#define OUT(reg) out->e.reg = rmregs.reg - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt. -****************************************************************************/ -int PMAPI PM_int86( - int intno, - RMREGS *in, - RMREGS *out) -{ - DPMI_regs rmregs; - - memset(&rmregs, 0, sizeof(rmregs)); - IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); - DPMI_int86(intno,&rmregs); - OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); - out->x.cflag = rmregs.flags & 0x1; - return out->x.ax; -} - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt. -****************************************************************************/ -int PMAPI PM_int86x( - int intno, - RMREGS *in, - RMREGS *out, - RMSREGS *sregs) -{ - DPMI_regs rmregs; - - memset(&rmregs, 0, sizeof(rmregs)); - IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); - rmregs.es = sregs->es; - rmregs.ds = sregs->ds; - DPMI_int86(intno,&rmregs); - OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); - sregs->es = rmregs.es; - sregs->cs = rmregs.cs; - sregs->ss = rmregs.ss; - sregs->ds = rmregs.ds; - out->x.cflag = rmregs.flags & 0x1; - return out->x.ax; -} - -/**************************************************************************** -REMARKS: -Call a real mode far function. -****************************************************************************/ -void PMAPI PM_callRealMode( - uint seg, - uint off, - RMREGS *in, - RMSREGS *sregs) -{ - PM_fatalError("PM_callRealMode not supported on OS/2!"); -} - -/**************************************************************************** -REMARKS: -Return the amount of available memory. -****************************************************************************/ -void PMAPI PM_availableMemory( - ulong *physical, - ulong *total) -{ - /* Unable to get reliable values from OS/2 for this */ - *physical = *total = 0; -} - -/**************************************************************************** -REMARKS: -Allocate a block of locked, physical memory for DMA operations. -****************************************************************************/ -void * PMAPI PM_allocLockedMem( - uint size, - ulong *physAddr, - ibool contiguous, - ibool below16M) -{ - parmsIn[0] = size; - parmsIn[1] = contiguous; - parmsIn[2] = below16M; - CallSDDHelp(PMHELP_ALLOCLOCKED); - *physAddr = parmsOut[1]; - return (void*)parmsOut[0]; -} - -/**************************************************************************** -REMARKS: -Free a block of locked physical memory. -****************************************************************************/ -void PMAPI PM_freeLockedMem( - void *p, - uint size, - ibool contiguous) -{ - parmsIn[0] = (ulong)p; - CallSDDHelp(PMHELP_FREELOCKED); -} - -/**************************************************************************** -REMARKS: -Allocates a new block of pages for the page block manager. -****************************************************************************/ -static pageblock *PM_addNewPageBlock(void) -{ - int i; - pageblock *newBlock; - char *p,*next; - - /* Allocate memory for the new page block, and add to head of list */ - if (DosAllocSharedMem((void**)&newBlock,NULL,PAGE_BLOCK_SIZE,OBJ_GETTABLE | PAG_READ | PAG_WRITE | PAG_COMMIT)) - return NULL; - if (!PM_lockDataPages(newBlock,PAGE_BLOCK_SIZE,&newBlock->lockHandle)) - return NULL; - newBlock->prev = NULL; - newBlock->next = pageBlocks; - if (pageBlocks) - pageBlocks->prev = newBlock; - pageBlocks = newBlock; - - /* Initialise the page aligned free list for the page block */ - newBlock->freeCount = PAGES_PER_BLOCK; - newBlock->freeList = p = (char*)(((ulong)(newBlock + 1) + (PM_PAGE_SIZE-1)) & ~(PM_PAGE_SIZE-1)); - newBlock->freeListStart = newBlock->freeList; - newBlock->freeListEnd = p + (PAGES_PER_BLOCK-1) * PM_PAGE_SIZE; - for (i = 0; i < PAGES_PER_BLOCK; i++,p = next) - FREELIST_NEXT(p) = next = p + PM_PAGE_SIZE; - FREELIST_NEXT(p - PM_PAGE_SIZE) = NULL; - return newBlock; -} - -/**************************************************************************** -REMARKS: -Allocates a page aligned and page sized block of memory -****************************************************************************/ -void * PMAPI PM_allocPage( - ibool locked) -{ - pageblock *block; - void *p; - - /* Scan the block list looking for any free blocks. Allocate a new - * page block if no free blocks are found. - */ - for (block = pageBlocks; block != NULL; block = block->next) { - if (block->freeCount) - break; - } - if (block == NULL && (block = PM_addNewPageBlock()) == NULL) - return NULL; - block->freeCount--; - p = block->freeList; - block->freeList = FREELIST_NEXT(p); - (void)locked; - return p; -} - -/**************************************************************************** -REMARKS: -Free a page aligned and page sized block of memory -****************************************************************************/ -void PMAPI PM_freePage( - void *p) -{ - pageblock *block; - - /* First find the page block that this page belongs to */ - for (block = pageBlocks; block != NULL; block = block->next) { - if (p >= block->freeListStart && p <= block->freeListEnd) - break; - } - CHECK(block != NULL); - - /* Now free the block by adding it to the free list */ - FREELIST_NEXT(p) = block->freeList; - block->freeList = p; - if (++block->freeCount == PAGES_PER_BLOCK) { - /* If all pages in the page block are now free, free the entire - * page block itself. - */ - if (block == pageBlocks) { - /* Delete from head */ - pageBlocks = block->next; - if (block->next) - block->next->prev = NULL; - } - else { - /* Delete from middle of list */ - CHECK(block->prev != NULL); - block->prev->next = block->next; - if (block->next) - block->next->prev = block->prev; - } - - /* Unlock the memory and free it */ - PM_unlockDataPages(block,PAGE_BLOCK_SIZE,&block->lockHandle); - DosFreeMem(block); - } -} - -/**************************************************************************** -REMARKS: -Map in all the shared memory blocks for managing the memory pages above. -****************************************************************************/ -void PMAPI PM_mapSharedPages(void) -{ - pageblock *block; - - /* Map all the page blocks above into the shared memory for process */ - for (block = pageBlocks; block != NULL; block = block->next) { - DosGetSharedMem(block, PAG_READ | PAG_WRITE); - } -} - -/**************************************************************************** -REMARKS: -Lock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_lockDataPages( - void *p, - uint len, - PM_lockHandle *lockHandle) -{ - parmsIn[0] = (ulong)p; - parmsIn[1] = len; - CallSDDHelp(PMHELP_LOCKPAGES); - lockHandle->h[0] = parmsOut[1]; - lockHandle->h[1] = parmsOut[2]; - lockHandle->h[2] = parmsOut[3]; - return parmsOut[0]; -} - -/**************************************************************************** -REMARKS: -Unlock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_unlockDataPages( - void *p, - uint len, - PM_lockHandle *lockHandle) -{ - parmsIn[0] = lockHandle->h[0]; - parmsIn[1] = lockHandle->h[1]; - parmsIn[2] = lockHandle->h[2]; - return CallSDDHelp(PMHELP_UNLOCKPAGES); -} - -/**************************************************************************** -REMARKS: -Lock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_lockCodePages( - void (*p)(), - uint len, - PM_lockHandle *lockHandle) -{ - parmsIn[0] = (ulong)p; - parmsIn[1] = len; - CallSDDHelp(PMHELP_LOCKPAGES); - lockHandle->h[0] = parmsOut[1]; - lockHandle->h[1] = parmsOut[2]; - lockHandle->h[2] = parmsOut[3]; - return parmsOut[0]; -} - -/**************************************************************************** -REMARKS: -Unlock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_unlockCodePages( - void (*p)(), - uint len, - PM_lockHandle *lockHandle) -{ - parmsIn[0] = lockHandle->h[0]; - parmsIn[1] = lockHandle->h[1]; - parmsIn[2] = lockHandle->h[2]; - return CallSDDHelp(PMHELP_UNLOCKPAGES); -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display banks. -****************************************************************************/ -void PMAPI PM_setBankA( - int bank) -{ - INTCRF rmregs; - - if (!InitInt10()) - return; - memset(&rmregs, 0, sizeof(rmregs)); - rmregs.ulBIOSIntNo = 0x10; - rmregs.aCRF.reg_eax = 0x4F05; - rmregs.aCRF.reg_ebx = 0x0000; - rmregs.aCRF.reg_edx = bank; - PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display banks. -****************************************************************************/ -void PMAPI PM_setBankAB( - int bank) -{ - INTCRF rmregs; - - if (!InitInt10()) - return; - memset(&rmregs, 0, sizeof(rmregs)); - rmregs.ulBIOSIntNo = 0x10; - rmregs.aCRF.reg_eax = 0x4F05; - rmregs.aCRF.reg_ebx = 0x0000; - rmregs.aCRF.reg_edx = bank; - PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); - rmregs.ulBIOSIntNo = 0x10; - rmregs.aCRF.reg_eax = 0x4F05; - rmregs.aCRF.reg_ebx = 0x0001; - rmregs.aCRF.reg_edx = bank; - PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display start address. -****************************************************************************/ -void PMAPI PM_setCRTStart( - int x, - int y, - int waitVRT) -{ - INTCRF rmregs; - - if (!InitInt10()) - return; - memset(&rmregs, 0, sizeof(rmregs)); - rmregs.ulBIOSIntNo = 0x10; - rmregs.aCRF.reg_eax = 0x4F07; - rmregs.aCRF.reg_ebx = waitVRT; - rmregs.aCRF.reg_ecx = x; - rmregs.aCRF.reg_edx = y; - PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); -} - -/**************************************************************************** -REMARKS: -Execute the POST on the secondary BIOS for a controller. -****************************************************************************/ -ibool PMAPI PM_doBIOSPOST( - ushort axVal, - ulong BIOSPhysAddr, - void *mappedBIOS, - ulong BIOSLen) -{ - (void)axVal; - (void)BIOSPhysAddr; - (void)mappedBIOS; - (void)BIOSLen; - return false; -} - -/**************************************************************************** -PARAMETERS: -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -RETURNS: -Error code describing the result. - -REMARKS: -Function to enable write combining for the specified region of memory. -****************************************************************************/ -int PMAPI PM_enableWriteCombine( - ulong base, - ulong size, - uint type) -{ - return MTRR_enableWriteCombine(base,size,type); -} - -/* TODO: Move the MTRR helper stuff into the call gate, or better yet */ -/* entirely into the ring 0 helper driver!! */ - -/* MTRR helper functions. To make it easier to implement the MTRR support - * under OS/2, we simply put our ring 0 helper functions into the - * helper device driver rather than the entire MTRR module. This makes - * it easier to maintain the MTRR support since we don't need to deal - * with 16-bit ring 0 code in the MTRR library. - */ - -/**************************************************************************** -REMARKS: -Flush the translation lookaside buffer. -****************************************************************************/ -void PMAPI PM_flushTLB(void) -{ - CallSDDHelp(PMHELP_FLUSHTLB); -} - -/**************************************************************************** -REMARKS: -Return true if ring 0 (or if we can call the helpers functions at ring 0) -****************************************************************************/ -ibool _ASMAPI _MTRR_isRing0(void) -{ - return true; -} - -/**************************************************************************** -REMARKS: -Read and return the value of the CR4 register -****************************************************************************/ -ulong _ASMAPI _MTRR_saveCR4(void) -{ - return CallSDDHelp(PMHELP_SAVECR4); -} - -/**************************************************************************** -REMARKS: -Restore the value of the CR4 register -****************************************************************************/ -void _ASMAPI _MTRR_restoreCR4(ulong cr4Val) -{ - parmsIn[0] = cr4Val; - CallSDDHelp(PMHELP_RESTORECR4); -} - -/**************************************************************************** -REMARKS: -Read a machine status register for the CPU. -****************************************************************************/ -void _ASMAPI _MTRR_readMSR( - ulong reg, - ulong *eax, - ulong *edx) -{ - parmsIn[0] = reg; - CallSDDHelp(PMHELP_READMSR); - *eax = parmsOut[0]; - *edx = parmsOut[1]; -} - -/**************************************************************************** -REMARKS: -Write a machine status register for the CPU. -****************************************************************************/ -void _ASMAPI _MTRR_writeMSR( - ulong reg, - ulong eax, - ulong edx) -{ - parmsIn[0] = reg; - parmsIn[1] = eax; - parmsIn[2] = edx; - CallSDDHelp(PMHELP_WRITEMSR); -} - -PM_MODULE PMAPI PM_loadLibrary( - const char *szDLLName) -{ - /* TODO: Implement this to load shared libraries! */ - (void)szDLLName; - return NULL; -} - -void * PMAPI PM_getProcAddress( - PM_MODULE hModule, - const char *szProcName) -{ - /* TODO: Implement this! */ - (void)hModule; - (void)szProcName; - return NULL; -} - -void PMAPI PM_freeLibrary( - PM_MODULE hModule) -{ - /* TODO: Implement this! */ - (void)hModule; -} - -/**************************************************************************** -REMARKS: -Internal function to convert the find data to the generic interface. -****************************************************************************/ -static void convertFindData( - PM_findData *findData, - FILEFINDBUF3 *blk) -{ - ulong dwSize = findData->dwSize; - - memset(findData,0,findData->dwSize); - findData->dwSize = dwSize; - if (blk->attrFile & FILE_READONLY) - findData->attrib |= PM_FILE_READONLY; - if (blk->attrFile & FILE_DIRECTORY) - findData->attrib |= PM_FILE_DIRECTORY; - if (blk->attrFile & FILE_ARCHIVED) - findData->attrib |= PM_FILE_ARCHIVE; - if (blk->attrFile & FILE_HIDDEN) - findData->attrib |= PM_FILE_HIDDEN; - if (blk->attrFile & FILE_SYSTEM) - findData->attrib |= PM_FILE_SYSTEM; - findData->sizeLo = blk->cbFile; - findData->sizeHi = 0; - strncpy(findData->name,blk->achName,PM_MAX_PATH); - findData->name[PM_MAX_PATH-1] = 0; -} - -#define FIND_MASK (FILE_ARCHIVED | FILE_DIRECTORY | FILE_SYSTEM | FILE_HIDDEN | FILE_READONLY) - -/**************************************************************************** -REMARKS: -Function to find the first file matching a search criteria in a directory. -****************************************************************************/ -void *PMAPI PM_findFirstFile( - const char *filename, - PM_findData *findData) -{ - FILEFINDBUF3 blk; - HDIR hdir = HDIR_CREATE; - ulong count = 1; - - if (DosFindFirst((PSZ)filename,&hdir,FIND_MASK,&blk,sizeof(blk),&count,FIL_STANDARD) == NO_ERROR) { - convertFindData(findData,&blk); - return (void*)hdir; - } - return PM_FILE_INVALID; -} - -/**************************************************************************** -REMARKS: -Function to find the next file matching a search criteria in a directory. -****************************************************************************/ -ibool PMAPI PM_findNextFile( - void *handle, - PM_findData *findData) -{ - FILEFINDBUF3 blk; - ulong count = 1; - - if (DosFindNext((HDIR)handle,&blk,sizeof(blk),&count) == NO_ERROR) { - convertFindData(findData,&blk); - return true; - } - return false; -} - -/**************************************************************************** -REMARKS: -Function to close the find process -****************************************************************************/ -void PMAPI PM_findClose( - void *handle) -{ - DosFindClose((HDIR)handle); -} - -/**************************************************************************** -REMARKS: -Function to determine if a drive is a valid drive or not. Under Unix this -function will return false for anything except a value of 3 (considered -the root drive, and equivalent to C: for non-Unix systems). The drive -numbering is: - - 0 - Current drive - 1 - Drive A: - 2 - Drive B: - 3 - Drive C: - etc - -****************************************************************************/ -ibool PMAPI PM_driveValid( - char drive) -{ - ulong cntDisk,cntDriveMap; - ibool valid; - - DosQueryCurrentDisk(&cntDisk,&cntDriveMap); - valid = (DosSetDefaultDisk(drive) == NO_ERROR); - DosSetDefaultDisk(cntDisk); - return valid; -} - -/**************************************************************************** -REMARKS: -Function to get the current working directory for the specififed drive. -Under Unix this will always return the current working directory regardless -of what the value of 'drive' is. -****************************************************************************/ -void PMAPI PM_getdcwd( - int drive, - char *dir, - int len) -{ - ulong length = len; - - DosQueryCurrentDir(drive, (PSZ)dir, &length); -} - -/**************************************************************************** -REMARKS: -Function to change the file attributes for a specific file. -****************************************************************************/ -void PMAPI PM_setFileAttr( - const char *filename, - uint attrib) -{ - FILESTATUS3 s; - - if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s))) - return; - s.attrFile = 0; - if (attrib & PM_FILE_READONLY) - s.attrFile |= FILE_READONLY; - if (attrib & PM_FILE_ARCHIVE) - s.attrFile |= FILE_ARCHIVED; - if (attrib & PM_FILE_HIDDEN) - s.attrFile |= FILE_HIDDEN; - if (attrib & PM_FILE_SYSTEM) - s.attrFile |= FILE_SYSTEM; - DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s),0L); -} - -/**************************************************************************** -REMARKS: -Function to get the file attributes for a specific file. -****************************************************************************/ -uint PMAPI PM_getFileAttr( - const char *filename) -{ - FILESTATUS3 fs3; - uint retval = 0; - - if (DosQueryPathInfo((PSZ)filename, FIL_STANDARD, &fs3, sizeof(FILESTATUS3))) - return 0; - if (fs3.attrFile & FILE_READONLY) - retval |= PM_FILE_READONLY; - if (fs3.attrFile & FILE_ARCHIVED) - retval |= PM_FILE_ARCHIVE; - if (fs3.attrFile & FILE_HIDDEN) - retval |= PM_FILE_HIDDEN; - if (fs3.attrFile & FILE_SYSTEM) - retval |= PM_FILE_SYSTEM; - return retval; -} - -/**************************************************************************** -REMARKS: -Function to create a directory. -****************************************************************************/ -ibool PMAPI PM_mkdir( - const char *filename) -{ - return DosCreateDir((PSZ)filename,NULL) == NO_ERROR; -} - -/**************************************************************************** -REMARKS: -Function to remove a directory. -****************************************************************************/ -ibool PMAPI PM_rmdir( - const char *filename) -{ - return DosDeleteDir((PSZ)filename) == NO_ERROR; -} - -/**************************************************************************** -REMARKS: -Function to get the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_getFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - FILESTATUS3 fs3; - struct tm tc; - struct tm *ret; - time_t tt; - - if (DosQueryPathInfo((PSZ)filename, FIL_STANDARD, &fs3, sizeof(FILESTATUS3))) - return false; - if (gmTime) { - tc.tm_year = fs3.fdateLastWrite.year + 80; - tc.tm_mon = fs3.fdateLastWrite.month - 1; - tc.tm_mday = fs3.fdateLastWrite.day; - tc.tm_hour = fs3.ftimeLastWrite.hours; - tc.tm_min = fs3.ftimeLastWrite.minutes; - tc.tm_sec = fs3.ftimeLastWrite.twosecs * 2; - if((tt = mktime(&tc)) == -1) - return false; - if(!(ret = gmtime(&tt))) - return false; - time->sec = ret->tm_sec; - time->day = ret->tm_mday; - time->mon = ret->tm_mon + 1; - time->year = ret->tm_year - 80; - time->min = ret->tm_min; - time->hour = ret->tm_hour; - } - else { - time->sec = fs3.ftimeLastWrite.twosecs * 2; - time->day = fs3.fdateLastWrite.day; - time->mon = fs3.fdateLastWrite.month; - time->year = fs3.fdateLastWrite.year; - time->min = fs3.ftimeLastWrite.minutes; - time->hour = fs3.ftimeLastWrite.hours; - } - return true; -} - -/**************************************************************************** -REMARKS: -Function to set the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_setFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - FILESTATUS3 fs3; - struct tm tc; - struct tm *ret; - time_t tt; - - if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&fs3,sizeof(fs3))) - return false; - if (gmTime) { - tc.tm_year = time->year + 80; - tc.tm_mon = time->mon - 1; - tc.tm_mday = time->day; - tc.tm_hour = time->hour; - tc.tm_min = time->min; - tc.tm_sec = time->sec; - if((tt = mktime(&tc)) == -1) - return false; - ret = localtime(&tt); - fs3.ftimeLastWrite.twosecs = ret->tm_sec / 2; - fs3.fdateLastWrite.day = ret->tm_mday; - fs3.fdateLastWrite.month = ret->tm_mon + 1; - fs3.fdateLastWrite.year = ret->tm_year - 80; - fs3.ftimeLastWrite.minutes = ret->tm_min; - fs3.ftimeLastWrite.hours = ret->tm_hour; - } - else { - fs3.ftimeLastWrite.twosecs = time->sec / 2; - fs3.fdateLastWrite.day = time->day; - fs3.fdateLastWrite.month = time->mon; - fs3.fdateLastWrite.year = time->year; - fs3.ftimeLastWrite.minutes = time->min; - fs3.ftimeLastWrite.hours = time->hour; - } - memcpy(&fs3.fdateLastAccess, &fs3.fdateLastWrite, sizeof(FDATE)); - memcpy(&fs3.fdateCreation, &fs3.fdateLastWrite, sizeof(FDATE)); - memcpy(&fs3.ftimeLastAccess, &fs3.ftimeLastWrite, sizeof(FTIME)); - memcpy(&fs3.ftimeCreation, &fs3.ftimeLastWrite, sizeof(FTIME)); - DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&fs3,sizeof(FILESTATUS3),0L); - return true; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c deleted file mode 100644 index 579ef2c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Dummy module; no virtual framebuffer for this OS -* -****************************************************************************/ - -#include "pmapi.h" - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -{ - baseAddr = baseAddr; - bankSize = bankSize; - codeLen = codeLen; - bankFunc = bankFunc; - return NULL; -} - -void PMAPI VF_exit(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c deleted file mode 100644 index 30ffe43..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: OS/2 -* -* Description: OS specific implementation for the Zen Timer functions. -* -****************************************************************************/ - -/*---------------------------- Global variables ---------------------------*/ - -static ulong frequency; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -void __ZTimerInit(void) -{ - DosTmrQueryFreq(&frequency); -} - -/**************************************************************************** -REMARKS: -Start the Zen Timer counting. -****************************************************************************/ -#define __LZTimerOn(tm) DosTmrQueryTime((QWORD*)&tm->start) - -/**************************************************************************** -REMARKS: -Compute the lap time since the timer was started. -****************************************************************************/ -static ulong __LZTimerLap( - LZTimerObject *tm) -{ - CPU_largeInteger tmLap,tmCount; - - DosTmrQueryTime((QWORD*)&tmLap); - _CPU_diffTime64(&tm->start,&tmLap,&tmCount); - return _CPU_calcMicroSec(&tmCount,frequency); -} - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerOff(tm) DosTmrQueryTime((QWORD*)&tm->end) - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -static ulong __LZTimerCount( - LZTimerObject *tm) -{ - CPU_largeInteger tmCount; - - _CPU_diffTime64(&tm->start,&tm->end,&tmCount); - return _CPU_calcMicroSec(&tmCount,frequency); -} - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as microseconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION 1000 - -/**************************************************************************** -REMARKS: -Read the Long Period timer value from the BIOS timer tick. -****************************************************************************/ -static ulong __ULZReadTime(void) -{ - ULONG count; - DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) ); - return count; -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong __ULZElapsedTime(ulong start,ulong finish) -{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c b/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c deleted file mode 100644 index 7af20a9..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c +++ /dev/null @@ -1,170 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: IBM PC (OS/2) -* -* Description: OS/2 implementation for the SciTech cross platform -* event library. -* -****************************************************************************/ - -/*---------------------------- Global Variables ---------------------------*/ - -static int oldMouseState; /* Old mouse state */ -static ulong oldKeyMessage; /* Old keyboard state */ -static ushort keyUpMsg[256] = {0};/* Table of key up messages */ -static int rangeX,rangeY; /* Range of mouse coordinates */ -HMOU _EVT_hMouse; /* Handle to the mouse driver */ - -/*---------------------------- Implementation -----------------------------*/ - -/* These are not used under OS/2 */ -#define _EVT_disableInt() 1 -#define _EVT_restoreInt(flags) - -/**************************************************************************** -PARAMETERS: -scanCode - Scan code to test - -REMARKS: -This macro determines if a specified key is currently down at the -time that the call is made. -****************************************************************************/ -#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) - -/**************************************************************************** -REMARKS: -Pumps all messages in the message queue from OS/2 into our event queue. -****************************************************************************/ -static void _EVT_pumpMessages(void) -{ - /* TODO: Implement this for OS/2 Presentation Manager apps! */ -} - -/**************************************************************************** -REMARKS: -This macro/function is used to converts the scan codes reported by the -keyboard to our event libraries normalised format. We only have one scan -code for the 'A' key, and use shift modifiers to determine if it is a -Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, -but the OS gives us 'cooked' scan codes, we have to translate them back -to the raw format. -****************************************************************************/ -#define _EVT_maskKeyCode(evt) - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _EVT_abort() -{ - EVT_exit(); - PM_fatalError("Unhandled exception!"); -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -void EVTAPI EVT_init( - _EVT_mouseMoveHandler mouseMove) -{ - /* Initialise the event queue */ - EVT.mouseMove = mouseMove; - initEventQueue(); - oldMouseState = 0; - oldKeyMessage = 0; - memset(keyUpMsg,0,sizeof(keyUpMsg)); - - /* TODO: OS/2 PM specific initialisation code! */ - - /* Catch program termination signals so we can clean up properly */ - signal(SIGABRT, _EVT_abort); - signal(SIGFPE, _EVT_abort); - signal(SIGINT, _EVT_abort); -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - rangeX = xRes; - rangeY = yRes; -} - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVT_resume(void) -{ - /* Do nothing for OS/2 */ -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVT_suspend(void) -{ - /* Do nothing for OS/2 */ -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVT_exit(void) -{ - /* Restore signal handlers */ - signal(SIGABRT, SIG_DFL); - signal(SIGFPE, SIG_DFL); - signal(SIGINT, SIG_DFL); - - /* TODO: OS/2 PM specific exit code */ -} - -/**************************************************************************** -REMARKS -Modifes the mouse coordinates as necessary if scaling to OS coordinates, -and sets the OS mouse cursor position. -****************************************************************************/ -#define _EVT_setMousePos(x,y) diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h deleted file mode 100644 index 0b69f82..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h +++ /dev/null @@ -1,36 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit OS/2 -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ - -#define INCL_DOSERRORS -#define INCL_DOS -#define INCL_SUB -#define INCL_VIO -#define INCL_KBD -#include diff --git a/board/MAI/bios_emulator/scitech/src/pm/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/oshdr.h deleted file mode 100644 index 404e5c9..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/oshdr.h +++ /dev/null @@ -1,70 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Header file to pull in OS specific headers for the target -* OS environment. -* -****************************************************************************/ - -#if defined(__SMX32__) -#include "smx/oshdr.h" -#elif defined(__RTTARGET__) -#include "rttarget/oshdr.h" -#elif defined(__REALDOS__) -#include "dos/oshdr.h" -#elif defined(__WIN32_VXD__) -#include "vxd/oshdr.h" -#elif defined(__NT_DRIVER__) -#include "ntdrv/oshdr.h" -#elif defined(__WINDOWS32__) -#include "win32/oshdr.h" -#elif defined(__OS2_VDD__) -#include "vxd/oshdr.h" -#elif defined(__OS2__) -#if defined(__OS2_PM__) -#include "os2pm/oshdr.h" -#else -#include "os2/oshdr.h" -#endif -#elif defined(__LINUX__) -#if defined(__USE_X11__) -#include "x11/oshdr.h" -#else -#include "linux/oshdr.h" -#endif -#elif defined(__QNX__) -#if defined(__USE_PHOTON__) -#include "photon/oshdr.h" -#elif defined(__USE_X11__) -#include "x11/oshdr.h" -#else -#include "qnx/oshdr.h" -#endif -#elif defined(__BEOS__) -#include "beos/oshdr.h" -#else -#error PM library not ported to this platform yet! -#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/photon/event.c b/board/MAI/bios_emulator/scitech/src/pm/photon/event.c deleted file mode 100644 index 581da16..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/photon/event.c +++ /dev/null @@ -1,268 +0,0 @@ -/**************************************************************************** -* -* SciTech Multi-platform Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: QNX Photon GUI -* -* Description: QNX fullscreen console implementation for the SciTech -* cross platform event library. -* -****************************************************************************/ - -/*--------------------------- Global variables ----------------------------*/ - -static ushort keyUpMsg[256] = {0};/* Table of key up messages */ - -/*---------------------------- Implementation -----------------------------*/ - -/* These are not used under Linux */ -#define _EVT_disableInt() 1 -#define _EVT_restoreInt(flags) - -/**************************************************************************** -PARAMETERS: -scanCode - Scan code to test - -REMARKS: -This macro determines if a specified key is currently down at the -time that the call is made. -****************************************************************************/ -static ibool _EVT_isKeyDown( - uchar scancode) -{ - return (KeyState[(scancode & 0xf8) >> 3] & (1 << (scancode & 0x7)) ? - true : false); -} - -/**************************************************************************** -REMARKS: -Retrieves all events from the mouse/keyboard event queue and stuffs them -into the MGL event queue for further processing. -****************************************************************************/ -static void _EVT_pumpMessages(void) -{ - int pid; - uint msg, but_stat, message; - uchar evt[sizeof (PhEvent_t) + 1024]; - PhEvent_t *event = (void *)evt; - PhKeyEvent_t *key; - PhPointerEvent_t *mouse; - static int extended; - event_t _evt; - - while (count < EVENTQSIZE) { - uint mods = 0, keyp = 0; - - pid = Creceive(0, &msg, sizeof (msg)); - - if (pid == -1) - return; - - if (PhEventRead(pid, event, sizeof (evt)) == Ph_EVENT_MSG) { - memset(&evt, 0, sizeof (evt)); - if (event->type == Ph_EV_KEY) { - key = PhGetData(event); - - if (key->key_flags & KEY_SCAN_VALID) { - keyp = key->key_scan; - if (key->key_flags & KEY_DOWN) - KeyState[(keyp & 0xf800) >> 11] - |= 1 << ((keyp & 0x700) >> 8); - else - KeyState[(keyp & 0xf800) >> 11] - &= ~(1 << ((keyp & 0x700) >> 8)); - } - if ((key->key_flags & KEY_SYM_VALID) || extended) - keyp |= key->key_sym; - - /* No way to tell left from right... */ - if (key->key_mods & KEYMOD_SHIFT) - mods = (EVT_LEFTSHIFT | EVT_RIGHTSHIFT); - if (key->key_mods & KEYMOD_CTRL) - mods |= (EVT_CTRLSTATE | EVT_LEFTCTRL); - if (key->key_mods & KEYMOD_ALT) - mods |= (EVT_ALTSTATE | EVT_LEFTALT); - - _evt.when = evt->timestamp; - if (key->key_flags & KEY_REPEAT) { - _evt.what = EVT_KEYREPEAT; - _evt.message = 0x10000; - } - else if (key->key_flags & KEY_DOWN) - _evt.what = EVT_KEYDOWN; - else - _evt.what = EVT_KEYUP; - _evt.modifiers = mods; - _evt.message |= keyp; - - addEvent(&_evt); - - switch(key->key_scan & 0xff00) { - case 0xe000: - extended = 1; - break; - case 0xe001: - extended = 2; - break; - default: - if (extended) - extended--; - } - } - else if (event->type & Ph_EV_PTR_ALL) { - but_stat = message = 0; - mouse = PhGetData(event); - - if (mouse->button_state & Ph_BUTTON_3) - but_stat = EVT_LEFTBUT; - if (mouse->buttons & Ph_BUTTON_3) - message = EVT_LEFTBMASK; - - if (mouse->button_state & Ph_BUTTON_1) - but_stat |= EVT_RIGHTBUT; - if (mouse->buttons & Ph_BUTTON_1) - message |= EVT_RIGHTBMASK; - - _evt.when = evt->timestamp; - if (event->type & Ph_EV_PTR_MOTION) { - _evt.what = EVT_MOUSEMOVE; - _evt.where_x = mouse->pos.x; - _evt.where_y = mouse->pos.y; - _evt.modifiers = but_stat; - addEvent(&_evt); - } - if (event->type & Ph_EV_BUT_PRESS) - _evt.what = EVT_MOUSEDOWN; - else - _evt.what = EVT_MOUSEUP; - _evt.where_x = mouse->pos.x; - _evt.where_y = mouse->pos.y; - _evt.modifiers = but_stat; - _evt.message = message; - addEvent(&_evt); - } - } - else - return; - } -} - -/**************************************************************************** -REMARKS: -This macro/function is used to converts the scan codes reported by the -keyboard to our event libraries normalised format. We only have one scan -code for the 'A' key, and use shift modifiers to determine if it is a -Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, -but the OS gives us 'cooked' scan codes, we have to translate them back -to the raw format. -****************************************************************************/ -#define _EVT_maskKeyCode(evt) - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _EVT_abort( - int signo) -{ - char buf[80]; - - EVT_exit(); - sprintf(buf,"Terminating on signal %d",signo); - PM_fatalError(buf); -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -void EVTAPI EVT_init( - _EVT_mouseMoveHandler mouseMove) -{ - int i; - - /* Initialise the event queue */ - _mouseMove = mouseMove; - initEventQueue(); - memset((void *)KeyState, 0, sizeof (KeyState)); - - /* Catch program termination signals so we can clean up properly */ - signal(SIGABRT, _EVT_abort); - signal(SIGFPE, _EVT_abort); - signal(SIGINT, _EVT_abort); -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - /* TODO: Need to call Input to change the coordinates that it returns */ - /* for mouse events!! */ -} - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVT_resume(void) -{ - /* Do nothing for Photon */ -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVT_suspend(void) -{ - /* Do nothing for Photon */ -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVT_exit(void) -{ - /* Restore signal handlers */ - signal(SIGABRT, SIG_DFL); - signal(SIGFPE, SIG_DFL); - signal(SIGINT, SIG_DFL); -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h deleted file mode 100644 index 3c72563..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h +++ /dev/null @@ -1,38 +0,0 @@ -/**************************************************************************** -* -* SciTech Multi-platform Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: QNX Photon GUI -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include diff --git a/board/MAI/bios_emulator/scitech/src/pm/pm.vpw b/board/MAI/bios_emulator/scitech/src/pm/pm.vpw deleted file mode 100644 index 26e68a7..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/pm.vpw +++ /dev/null @@ -1,43 +0,0 @@ -[Dependencies] -[CurrentProject] -curproj=pmlinux.vpj -[ProjectFiles] -pmcommon.vpj -pmdos.vpj -pmlinux.vpj -pmqnx.vpj -pmvxd.vpj -pmwin32.vpj -z_samples.vpj -..\a-global includes.vpj -[TreeExpansion] -"..\a-global includes.vpj" 0 -pmcommon.vpj 0 -pmdos.vpj 0 -pmlinux.vpj 0 -pmqnx.vpj 0 -pmvxd.vpj 0 -pmwin32.vpj 0 -z_samples.vpj 1 1 -[State] -SCREEN: 1280 1024 0 0 960 746 0 0 M 0 0 0 0 977 631 -CWD: C:\scitech\src\pm -FILEHIST: 9 -C:\scitech\makedefs\gcc_win32.mk -C:\scitech\bin\gcc2-w32.bat -C:\scitech\bin\gcc2-c32.bat -C:\scitech\bin\gcc2-linux.bat -C:\scitech\makedefs\gcc_linux.mk -C:\scitech\src\pm\linux\event.c -C:\scitech\src\pm\linux\oshdr.h -C:\scitech\src\pm\event.c -C:\scitech\src\pm\pmlinux.vpj -[ProjectDates] -pmcommon.vpj=20010517164335290 -pmdos.vpj=20010517164335290 -pmlinux.vpj=20010620175829812 -pmqnx.vpj=20010517164335290 -pmvxd.vpj=20010517164335306 -pmwin32.vpj=20010517164335306 -z_samples.vpj=20010517164335306 -..\a-global includes.vpj=20010517164334978 diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj deleted file mode 100644 index 48b872d..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj +++ /dev/null @@ -1,45 +0,0 @@ -[COMPILER] -version=5.0b -MACRO=\n -activeconfig=,wc10-d32 -FILTERNAME=Source Files\nInclude Files\nAssembler Files\nOther Files\n -FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n*.*\n -FILTERASSOCIATEFILETYPES=0 0 0 0 -FILTERAPPCOMMAND=\n\n\n\n -vcsproject=SCC:Perforce SCM://depot -vcslocalpath=SCC:Perforce SCM:c:\ -compile=concur|capture|hide|:Compile:&Compile, -make=concur|capture|hide|clear|saveall|:Build:&Build, -rebuild=concur|capture|hide|clear|saveall|:Rebuild:&Rebuild, -debug=concur|capture|hide|savenone|:Debug:&Debug, -execute=hide|savenone|:Execute:E&xecute, -user1=hide|:User 1:User 1, -user2=hide|:User 2:User 2, -workingdir=. -includedirs=%(SCITECH)\include;%(PRIVATE)\include -reffile= -[FILES] -common.c -cpuinfo.c -debug.c -event.c -makefile -oshdr.h -ztimer.c -..\common\agplib.c -codepage\us_eng.c -common\_cpuinfo.asm -common\_dma.asm -common\_int64.asm -common\_joy.asm -common\_mtrr.asm -common\_pcilib.asm -common\agp.c -common\keyboard.c -common\malloc.c -common\mtrr.c -common\pcilib.c -common\unixio.c -common\vgastate.c -[ASSOCIATION] -[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj deleted file mode 100644 index 1157513..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj +++ /dev/null @@ -1,41 +0,0 @@ -[SciTech] -compiler=wc10- -targetos=d32 -[COMPILER] -version=5.0b -MACRO=enable_current_compiler\n -activeconfig=,TEST_HARNESS=1 -FILTERNAME=Source Files\nInclude Files\nAssembler Files\n -FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n -FILTERASSOCIATEFILETYPES=0 0 0 -FILTERAPPCOMMAND=\n\n\n -vcsproject=SCC:Perforce SCM://depot -vcslocalpath=SCC:Perforce SCM:c:\ -compile=concur|capture|clear|:Compile:&Compile,dmake %n.obj -u %b -make=concur|capture|clear|saveall|:Build:&Build,dmake install %b -rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u %b -debug=concur|capture|hide|savenone|:Debug:&Debug, -execute=hide|savenone|nochangedir|:Execute:E&xecute, -user1=hide|:User 1:User 1, -user2=hide|:User 2:User 2, -usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe -workingdir=. -includedirs=%(SCITECH)\include;%(PRIVATE)\include -reffile= -[FILES] -dos\_event.asm -dos\_lztimer.asm -dos\_pm.asm -dos\_pmdos.asm -dos\_vflat.asm -dos\cpuinfo.c -dos\event.c -dos\oshdr.h -dos\pm.c -dos\pmdos.c -dos\vflat.c -dos\ztimer.c -[ASSOCIATION] -[CONFIGURATIONS] -config=,NORMAL_BUILD=1 -config=,TEST_HARNESS=1 diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj deleted file mode 100644 index 0bfbf84..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj +++ /dev/null @@ -1,35 +0,0 @@ -[SciTech] -compiler=gcc2- -targetos=linux -[COMPILER] -version=5.0b -MACRO=enable_current_compiler\n -FILTERNAME=Source Files\nInclude Files\nAssembler Files\n -FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n -FILTERASSOCIATEFILETYPES=0 0 0 -FILTERAPPCOMMAND=\n\n\n -vcsproject=SCC:Perforce SCM://depot -vcslocalpath=SCC:Perforce SCM:c:\ -activeconfig=,install BUILD_DLL=1 -compile=concur|capture|clear|:Compile:&Compile,dmake %n.o -u -make=concur|capture|clear|saveall|:Build:&Build,dmake %b -rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake -u %b -debug=concur|capture|hide|savenone|:Debug:&Debug, -execute=hide|savenone|nochangedir|:Execute:E&xecute, -user1=hide|:User 1:User 1, -user2=hide|:User 2:User 2, -usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe -workingdir=. -includedirs=%(SCITECH)\include;%(PRIVATE)\include -reffile= -[FILES] -linux\cpuinfo.c -linux\event.c -linux\oshdr.h -linux\pm.c -linux\vflat.c -linux\ztimer.c -[ASSOCIATION] -[CONFIGURATIONS] -config=,install BUILD_DLL=1 -config=,install diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj deleted file mode 100644 index 3ec35a7..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj +++ /dev/null @@ -1,39 +0,0 @@ -[SciTech] -compiler=vc60- -targetos=drvw2k -[COMPILER] -version=5.0b -MACRO=enable_current_compiler\n -activeconfig=,wc10-d32 -FILTERNAME=Source Files\nInclude Files\nAssembler Files\n -FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n -FILTERASSOCIATEFILETYPES=0 0 0 -FILTERAPPCOMMAND=\n\n\n -vcsproject=SCC:Perforce SCM://depot -vcslocalpath=SCC:Perforce SCM:c:\ -compile=concur|capture|:Compile:&Compile,dmake %n.obj -make=concur|capture|clear|saveall|:Build:&Build,dmake install -rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u -debug=concur|capture|hide|savenone|:Debug:&Debug, -execute=hide|savenone|nochangedir|:Execute:E&xecute, -user1=hide|:User 1:User 1, -user2=hide|:User 2:User 2, -usertool_clean_directory=concur|capture|hide|savenone|:Clean Directory:&Clean Directory,dmake cleanexe -workingdir=. -includedirs=%(SCITECH)\include;%(PRIVATE)\include -reffile= -[FILES] -..\..\include\ntdriver.h -ntdrv\_pm.asm -ntdrv\cpuinfo.c -ntdrv\int86.c -ntdrv\irq.c -ntdrv\mem.c -ntdrv\oshdr.h -ntdrv\pm.c -ntdrv\stdio.c -ntdrv\stdlib.c -ntdrv\vflat.c -ntdrv\ztimer.c -[ASSOCIATION] -[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj deleted file mode 100644 index d541702..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj +++ /dev/null @@ -1,35 +0,0 @@ -[SciTech] -compiler=wc10- -targetos=qnx -[COMPILER] -version=5.0b -MACRO=enable_current_compiler\n -activeconfig=,wc10-d32 -FILTERNAME=Source Files\nInclude Files\nAssembler Files\n -FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n -FILTERASSOCIATEFILETYPES=0 0 0 -FILTERAPPCOMMAND=\n\n\n -vcsproject=SCC:Perforce SCM://depot -vcslocalpath=SCC:Perforce SCM:c:\ -compile=concur|capture|clear|:Compile:&Compile,dmake %n.obj -make=concur|capture|clear|saveall|:Build:&Build,dmake install -rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u -debug=concur|capture|hide|savenone|:Debug:&Debug, -execute=hide|savenone|nochangedir|:Execute:E&xecute, -user1=hide|:User 1:User 1, -user2=hide|:User 2:User 2, -usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe -workingdir=. -includedirs=%(SCITECH)\include;%(PRIVATE)\include -reffile= -[FILES] -qnx\_mtrrqnx.asm -qnx\cpuinfo.c -qnx\event.c -qnx\mtrrqnx.c -qnx\oshdr.h -qnx\pm.c -qnx\vflat.c -qnx\ztimer.c -[ASSOCIATION] -[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj deleted file mode 100644 index 1fcf911..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj +++ /dev/null @@ -1,34 +0,0 @@ -[SciTech] -compiler=bc50- -targetos=vxd -[COMPILER] -version=5.0b -MACRO=enable_current_compiler\n -activeconfig=,wc10-d32 -FILTERNAME=Source Files\nInclude Files\nAssembler Files\n -FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n -FILTERASSOCIATEFILETYPES=0 0 0 -FILTERAPPCOMMAND=\n\n\n -vcsproject=SCC:Perforce SCM://depot -vcslocalpath=SCC:Perforce SCM:c:\ -compile=concur|capture|nochangedir|:Compile:&Compile,dmake %n.obj -make=concur|capture|clear|saveall|nochangedir|:Build:&Build,dmake install -rebuild=concur|capture|clear|saveall|nochangedir|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u -debug=concur|capture|hide|savenone|nochangedir|:Debug:&Debug, -execute=hide|savenone|nochangedir|:Execute:E&xecute, -user1=hide|:User 1:User 1, -user2=hide|:User 2:User 2, -usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:&Clean Directory,dmake cleanexe -workingdir=. -includedirs=%(SCITECH)\include;%(PRIVATE)\include -reffile= -[FILES] -vxd\_pm.asm -vxd\cpuinfo.c -vxd\fileio.c -vxd\oshdr.h -vxd\pm.c -vxd\vflat.c -vxd\ztimer.c -[ASSOCIATION] -[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj deleted file mode 100644 index ace6822..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj +++ /dev/null @@ -1,35 +0,0 @@ -[SciTech] -compiler=vc60- -targetos=c32 -[COMPILER] -version=5.0b -MACRO=enable_current_compiler\n -activeconfig=,wc10-d32 -FILTERNAME=Source Files\nInclude Files\nAssembler Files\n -FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n -FILTERASSOCIATEFILETYPES=0 0 0 -FILTERAPPCOMMAND=\n\n\n -vcsproject=SCC:Perforce SCM://depot -vcslocalpath=SCC:Perforce SCM:c:\ -compile=concur|capture|:Compile:&Compile,dmake %n.obj -make=concur|capture|clear|saveall|:Build:&Build,dmake install -rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u -debug=concur|capture|hide|savenone|:Debug:&Debug, -execute=hide|savenone|nochangedir|:Execute:E&xecute, -user1=hide|:User 1:User 1, -user2=hide|:User 2:User 2, -usertool_clean_directory=concur|capture|savenone|:Clean Directory:&Clean Directory,dmake cleanexe -workingdir=. -includedirs=%(SCITECH)\include;%(PRIVATE)\include -reffile= -[FILES] -win32\_pmwin32.asm -win32\cpuinfo.c -win32\ddraw.c -win32\event.c -win32\oshdr.h -win32\pm.c -win32\vflat.c -win32\ztimer.c -[ASSOCIATION] -[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm b/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm deleted file mode 100644 index 5a3fe10..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm +++ /dev/null @@ -1,226 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: NASM -;* Environment: QNX -;* -;* Description: Assembler support routines for the Memory Type Range Register -;* (MTRR) module for QNX. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _mtrrqnx ; Set up memory model - -begdataseg _mtrrqnx ; Start of code segment - -ifdef USE_NASM -%define R0_FLUSH_TLB 0 -%define R0_SAVE_CR4 1 -%define R0_RESTORE_CR4 2 -%define R0_READ_MSR 3 -%define R0_WRITE_MSR 4 -else -R0_FLUSH_TLB EQU 0 -R0_SAVE_CR4 EQU 1 -R0_RESTORE_CR4 EQU 2 -R0_READ_MSR EQU 3 -R0_WRITE_MSR EQU 4 -endif - -cpublic _PM_R0 -_PM_R0_service dd 0 -_PM_R0_reg dd 0 -_PM_R0_eax dd 0 -_PM_R0_edx dd 0 - -enddataseg _mtrrqnx ; Start of code segment - -begcodeseg _mtrrqnx ; Start of code segment - -P586 - -;---------------------------------------------------------------------------- -; ulong _MTRR_disableInt(void); -;---------------------------------------------------------------------------- -; Return processor interrupt status and disable interrupts. -;---------------------------------------------------------------------------- -cprocstart _MTRR_disableInt - - pushfd ; Put flag word on stack -; cli ; Disable interrupts! - pop eax ; deposit flag word in return register - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _MTRR_restoreInt(ulong ps); -;---------------------------------------------------------------------------- -; Restore processor interrupt status. -;---------------------------------------------------------------------------- -cprocstart _MTRR_restoreInt - - ARG ps:ULONG - - push ebp - mov ebp,esp ; Set up stack frame - push [ULONG ps] - popfd ; Restore processor status (and interrupts) - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; uchar _MTRR_getCx86(uchar reg); -;---------------------------------------------------------------------------- -; Read a Cyrix CPU indexed register -;---------------------------------------------------------------------------- -cprocstart _MTRR_getCx86 - - ARG reg:UCHAR - - enter_c - mov al,[reg] - out 22h,al - in al,23h - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; uchar _MTRR_setCx86(uchar reg,uchar val); -;---------------------------------------------------------------------------- -; Write a Cyrix CPU indexed register -;---------------------------------------------------------------------------- -cprocstart _MTRR_setCx86 - - ARG reg:UCHAR, val:UCHAR - - enter_c - mov al,[reg] - out 22h,al - mov al,[val] - out 23h,al - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; ulong _PM_ring0_isr(void); -;---------------------------------------------------------------------------- -; Ring 0 clock interrupt handler that we use to execute the MTRR support -; code. -;---------------------------------------------------------------------------- -cprocnear _PM_ring0_isr - -;-------------------------------------------------------- -; void PM_flushTLB(void); -;-------------------------------------------------------- - pushad - cmp [DWORD _PM_R0_service],R0_FLUSH_TLB - jne @@1 - wbinvd ; Flush the CPU cache - mov eax,cr3 - mov cr3,eax ; Flush the TLB - jmp @@Exit - -;-------------------------------------------------------- -; ulong _MTRR_saveCR4(void); -;-------------------------------------------------------- -@@1: cmp [DWORD _PM_R0_service],R0_SAVE_CR4 - jne @@2 - -; Save value of CR4 and clear Page Global Enable (bit 7) - - mov ebx,cr4 - mov eax,ebx - and al,7Fh - mov cr4,eax - -; Disable and flush caches - - mov eax,cr0 - or eax,40000000h - wbinvd - mov cr0,eax - wbinvd - -; Return value from CR4 - - mov [_PM_R0_reg],ebx - jmp @@Exit - -;-------------------------------------------------------- -; void _MTRR_restoreCR4(ulong cr4Val) -;-------------------------------------------------------- -@@2: cmp [DWORD _PM_R0_service],R0_RESTORE_CR4 - jne @@3 - - mov eax,cr0 - and eax,0BFFFFFFFh - mov cr0,eax - mov eax,[_PM_R0_reg] - mov cr4,eax - jmp @@Exit - -;-------------------------------------------------------- -; void _MTRR_readMSR(int reg, ulong FAR *eax, ulong FAR *edx); -;-------------------------------------------------------- -@@3: cmp [DWORD _PM_R0_service],R0_READ_MSR - jne @@4 - - mov ecx,[_PM_R0_reg] - rdmsr - mov [_PM_R0_eax],eax - mov [_PM_R0_edx],edx - jmp @@Exit - -;-------------------------------------------------------- -; void _MTRR_writeMSR(int reg, ulong eax, ulong edx); -;-------------------------------------------------------- -@@4: cmp [DWORD _PM_R0_service],R0_WRITE_MSR - jne @@Exit - - mov ecx,[_PM_R0_reg] - mov eax,[_PM_R0_eax] - mov edx,[_PM_R0_edx] - wrmsr - jmp @@Exit - -@@Exit: mov [DWORD _PM_R0_service],-1 - popad - mov eax,0 - retf - -cprocend - -endcodeseg _mtrrqnx - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c deleted file mode 100644 index a878254..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: QNX -* -* Description: QNX specific code for the CPU detection module. -* -****************************************************************************/ - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -TODO: We should implement this for QNX! -****************************************************************************/ -#define SetMaxThreadPriority() 0 - -/**************************************************************************** -REMARKS: -TODO: We should implement this for QNX! -****************************************************************************/ -#define RestoreThreadPriority(i) - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - freq->low = CLOCKS_PER_SEC * 1000; - freq->high = 0; -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. -****************************************************************************/ -#define GetCounter(t) \ -{ \ - (t)->low = clock() * 1000; \ - (t)->high = 0; \ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c deleted file mode 100644 index 45cd514..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c +++ /dev/null @@ -1,601 +0,0 @@ -/**************************************************************************** -* -* SciTech Multi-platform Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: QNX -* -* Description: QNX fullscreen console implementation for the SciTech -* cross platform event library. -* -****************************************************************************/ - -#include -#include - -/*--------------------------- Global variables ----------------------------*/ - -#ifndef __QNXNTO__ -static struct _mouse_ctrl *_PM_mouse_ctl; -static int _PM_keyboard_fd = -1; -/*static int _PM_modifiers, _PM_leds; */ -#else -static int kbd_fd = -1, mouse_fd = -1; -#endif -static int kill_pid = 0; -static ushort keyUpMsg[256] = {0};/* Table of key up messages */ -static int rangeX,rangeY; /* Range of mouse coordinates */ - -#define TIME_TO_MSEC(__t) ((__t).tv_nsec / 1000000 + (__t).tv_sec * 1000) - -#define LED_NUM 1 -#define LED_CAP 2 -#define LED_SCR 4 - -/* Scancode mappings on QNX for special keys */ - -typedef struct { - int scan; - int map; - } keymap; - -/* TODO: Fix this and set it up so we can do a binary search! */ - -keymap keymaps[] = { - {96, KB_padEnter}, - {74, KB_padMinus}, - {78, KB_padPlus}, - {55, KB_padTimes}, - {98, KB_padDivide}, - {71, KB_padHome}, - {72, KB_padUp}, - {73, KB_padPageUp}, - {75, KB_padLeft}, - {76, KB_padCenter}, - {77, KB_padRight}, - {79, KB_padEnd}, - {80, KB_padDown}, - {81, KB_padPageDown}, - {82, KB_padInsert}, - {83, KB_padDelete}, - {105,KB_left}, - {108,KB_down}, - {106,KB_right}, - {103,KB_up}, - {110,KB_insert}, - {102,KB_home}, - {104,KB_pageUp}, - {111,KB_delete}, - {107,KB_end}, - {109,KB_pageDown}, - {125,KB_leftWindows}, - {126,KB_rightWindows}, - {127,KB_menu}, - {100,KB_rightAlt}, - {97,KB_rightCtrl}, - }; - -/* And the keypad with num lock turned on (changes the ASCII code only) */ - -keymap keypad[] = { - {71, ASCII_7}, - {72, ASCII_8}, - {73, ASCII_9}, - {75, ASCII_4}, - {76, ASCII_5}, - {77, ASCII_6}, - {79, ASCII_1}, - {80, ASCII_2}, - {81, ASCII_3}, - {82, ASCII_0}, - {83, ASCII_period}, - }; - -#define NB_KEYMAPS (sizeof(keymaps)/sizeof(keymaps[0])) -#define NB_KEYPAD (sizeof(keypad)/sizeof(keypad[0])) - -/*---------------------------- Implementation -----------------------------*/ - -/**************************************************************************** -REMARKS: -Include generic raw scancode keyboard module. -****************************************************************************/ -#include "common/keyboard.c" - -/* These are not used under QNX */ -#define _EVT_disableInt() 1 -#define _EVT_restoreInt(flags) - -/**************************************************************************** -REMARKS: -This function is used to return the number of ticks since system -startup in milliseconds. This should be the same value that is placed into -the time stamp fields of events, and is used to implement auto mouse down -events. -****************************************************************************/ -ulong _EVT_getTicks(void) -{ - struct timespec t; - clock_gettime(CLOCK_REALTIME,&t); - return (t.tv_nsec / 1000000 + t.tv_sec * 1000); -} - -/**************************************************************************** -REMARKS: -Converts a mickey movement value to a pixel adjustment value. -****************************************************************************/ -static int MickeyToPixel( - int mickey) -{ - /* TODO: We can add some code in here to handle 'acceleration' for */ - /* the mouse cursor. For now just use the mickeys. */ - return mickey; -} - -#ifdef __QNXNTO__ -/**************************************************************************** -REMARKS: -Retrieves all events from the mouse/keyboard event queue and stuffs them -into the MGL event queue for further processing. -****************************************************************************/ -static void _EVT_pumpMessages(void) -{ - int rc1, rc2; - struct _keyboard_packet key; - struct _mouse_packet ms; - static long old_buttons = 0; - uint message = 0, but_stat = 0, mods = 0; - event_t evt; - - while (EVT.count < EVENTQSIZE) { - rc1 = read(kbd_fd, (void *)&key, sizeof(key)); - if (rc1 == -1) { - if (errno == EAGAIN) - rc1 = 0; - else { - perror("getEvents"); - PM_fatalError("Keyboard error"); - } - } - if (rc1 > 0) { - memset(&evt, 0, sizeof(evt)); - if (key.data.modifiers & KEYMOD_SHIFT) - mods |= EVT_LEFTSHIFT; - if (key.data.modifiers & KEYMOD_CTRL) - mods |= EVT_CTRLSTATE; - if (key.data.modifiers & KEYMOD_ALT) - mods |= EVT_ALTSTATE; - - /* Now store the keyboard event data */ - evt.when = TIME_TO_MSEC(key.time); - if (key.data.flags & KEY_SCAN_VALID) - evt.message |= (key.data.key_scan & 0x7F) << 8; - if ((key.data.flags & KEY_SYM_VALID) && - (((key.data.key_sym & 0xff00) == 0xf000 && - (key.data.key_sym & 0xff) < 0x20) || - key.data.key_sym < 0x80)) - evt.message |= (key.data.key_sym & 0xFF); - evt.modifiers = mods; - if (key.data.flags & KEY_DOWN) { - evt.what = EVT_KEYDOWN; - keyUpMsg[evt.message >> 8] = (ushort)evt.message; - } - else if (key.data.flags & KEY_REPEAT) { - evt.message |= 0x10000; - evt.what = EVT_KEYREPEAT; - } - else { - evt.what = EVT_KEYUP; - evt.message = keyUpMsg[evt.message >> 8]; - if (evt.message == 0) - continue; - keyUpMsg[evt.message >> 8] = 0; - } - - /* Now add the new event to the event queue */ - addEvent(&evt); - } - rc2 = read(mouse_fd, (void *)&ms, sizeof (ms)); - if (rc2 == -1) { - if (errno == EAGAIN) - rc2 = 0; - else { - perror("getEvents"); - PM_fatalError("Mouse error"); - } - } - if (rc2 > 0) { - memset(&evt, 0, sizeof(evt)); - ms.hdr.buttons &= - (_POINTER_BUTTON_LEFT | _POINTER_BUTTON_RIGHT); - if (ms.hdr.buttons & _POINTER_BUTTON_LEFT) - but_stat = EVT_LEFTBUT; - if ((ms.hdr.buttons & _POINTER_BUTTON_LEFT) != - (old_buttons & _POINTER_BUTTON_LEFT)) - message = EVT_LEFTBMASK; - if (ms.hdr.buttons & _POINTER_BUTTON_RIGHT) - but_stat |= EVT_RIGHTBUT; - if ((ms.hdr.buttons & _POINTER_BUTTON_RIGHT) != - (old_buttons & _POINTER_BUTTON_RIGHT)) - message |= EVT_RIGHTBMASK; - if (ms.dx || ms.dy) { - ms.dy = -ms.dy; - EVT.mx += MickeyToPixel(ms.dx); - EVT.my += MickeyToPixel(ms.dy); - if (EVT.mx < 0) EVT.mx = 0; - if (EVT.my < 0) EVT.my = 0; - if (EVT.mx > rangeX) EVT.mx = rangeX; - if (EVT.my > rangeY) EVT.my = rangeY; - evt.what = EVT_MOUSEMOVE; - evt.when = TIME_TO_MSEC(ms.hdr.time); - evt.where_x = EVT.mx; - evt.where_y = EVT.my; - evt.relative_x = ms.dx; - evt.relative_y = ms.dy; - evt.modifiers = but_stat; - addEvent(&evt); - } - evt.what = ms.hdr.buttons < old_buttons ? - EVT_MOUSEUP : EVT_MOUSEDOWN; - evt.when = TIME_TO_MSEC(ms.hdr.time); - evt.where_x = EVT.mx; - evt.where_y = EVT.my; - evt.relative_x = ms.dx; - evt.relative_y = ms.dy; - evt.modifiers = but_stat; - evt.message = message; - if (ms.hdr.buttons != old_buttons) { - addEvent(&evt); - old_buttons = ms.hdr.buttons; - } - } - if (rc1 + rc2 == 0) - break; - } -} -#else -/**************************************************************************** -REMARKS: -Retrieves all events from the mouse/keyboard event queue and stuffs them -into the MGL event queue for further processing. -****************************************************************************/ -static void _EVT_pumpMessages(void) -{ - struct mouse_event ev; - int rc; - static long old_buttons = 0; - uint message = 0, but_stat = 0; - event_t evt; - char buf[32]; - int numkeys, i; - - /* Poll keyboard events */ - while ((numkeys = read(_PM_keyboard_fd, buf, sizeof buf)) > 0) { - for (i = 0; i < numkeys; i++) { - processRawScanCode(buf[i]); - } - } - - if (_PM_mouse_ctl == NULL) - return; - - /* Gobble pending mouse events */ - while (EVT.count < EVENTQSIZE) { - rc = mouse_read(_PM_mouse_ctl, &ev, 1, 0, NULL); - if (rc == -1) { - perror("getEvents"); - PM_fatalError("Mouse error (Input terminated?)"); - } - if (rc == 0) - break; - - message = 0, but_stat = 0; - memset(&evt, 0, sizeof(evt)); - - ev.buttons &= (_MOUSE_LEFT | _MOUSE_RIGHT); - if (ev.buttons & _MOUSE_LEFT) - but_stat = EVT_LEFTBUT; - if ((ev.buttons & _MOUSE_LEFT) != (old_buttons & _MOUSE_LEFT)) - message = EVT_LEFTBMASK; - if (ev.buttons & _MOUSE_RIGHT) - but_stat |= EVT_RIGHTBUT; - if ((ev.buttons & _MOUSE_RIGHT) != (old_buttons & _MOUSE_RIGHT)) - message |= EVT_RIGHTBMASK; - if (ev.dx || ev.dy) { - ev.dy = -ev.dy; - EVT.mx += MickeyToPixel(ev.dx); - EVT.my += MickeyToPixel(ev.dy); - if (EVT.mx < 0) EVT.mx = 0; - if (EVT.my < 0) EVT.my = 0; - if (EVT.mx > rangeX) EVT.mx = rangeX; - if (EVT.my > rangeY) EVT.my = rangeY; - evt.what = EVT_MOUSEMOVE; - evt.when = ev.timestamp*100; - evt.where_x = EVT.mx; - evt.where_y = EVT.my; - evt.relative_x = ev.dx; - evt.relative_y = ev.dy; - evt.modifiers = but_stat; - addEvent(&evt); - } - evt.what = ev.buttons < old_buttons ? EVT_MOUSEUP : EVT_MOUSEDOWN; - evt.when = ev.timestamp*100; - evt.where_x = EVT.mx; - evt.where_y = EVT.my; - evt.relative_x = ev.dx; - evt.relative_y = ev.dy; - evt.modifiers = but_stat; - evt.message = message; - if (ev.buttons != old_buttons) { - addEvent(&evt); - old_buttons = ev.buttons; - } - } -} -#endif /* __QNXNTO__ */ - -/**************************************************************************** -REMARKS: -This macro/function is used to converts the scan codes reported by the -keyboard to our event libraries normalised format. We only have one scan -code for the 'A' key, and use shift modifiers to determine if it is a -Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, -but the OS gives us 'cooked' scan codes, we have to translate them back -to the raw format. -****************************************************************************/ -#define _EVT_maskKeyCode(evt) - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _EVT_abort( - int signo) -{ - char buf[80]; - - EVT_exit(); - sprintf(buf,"Terminating on signal %d",signo); - PM_fatalError(buf); -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -void EVTAPI EVT_init( - _EVT_mouseMoveHandler mouseMove) -{ - int i; - struct stat st; - char *iarg[16]; -#ifdef __QNXNTO__ - char buf[128]; - FILE *p; - int argno,len; -#endif - -#ifdef __QNXNTO__ - ThreadCtl(_NTO_TCTL_IO, 0); /* So joystick code won't blow up */ -#endif - - /* Initialise the event queue */ - EVT.mouseMove = mouseMove; - initEventQueue(); - memset(keyUpMsg,0,sizeof(keyUpMsg)); - -#ifdef __QNXNTO__ - /* - * User may already have input running with the right parameters. - * Thus they could start input at boot time, using the output of - * inputtrap, passing the the -r flag to make it run as a resource - * manager. - */ - if ((mouse_fd = open("/dev/mouse0", O_RDONLY | O_NONBLOCK)) < 0) { - /* Run inputtrap to get the args for input */ - if ((p = popen("inputtrap", "r")) == NULL) - PM_fatalError("Error running 'inputtrap'"); - fgets(buf, sizeof(buf), p); - pclose(p); - - /* Build the argument list */ - len = strlen(buf); - iarg[0] = buf; - for (i = 0, argno = 0; i < len && argno < 15;) { - if (argno == 1) { - /* - * Add flags to input's arg list. - * '-r' means run as resource - * manager, providing the /dev/mouse - * and /dev/keyboard interfaces. - * '-P' supresses the /dev/photon - * mechanism. - */ - iarg[argno++] = "-Pr"; - continue; - } - while (buf[i] == ' ') - i++; - if (buf[i] == '\0' || buf[i] == '\n') - break; - iarg[argno++] = &buf[i]; - while (buf[i] != ' ' - && buf[i] != '\0' && buf[i] != '\n') - i++; - buf[i++] = '\0'; - } - iarg[argno] = NULL; - - if ((kill_pid = spawnvp(P_NOWAITO, iarg[0], iarg)) == -1) { - perror("spawning input resmgr"); - PM_fatalError("Could not start input resmgr"); - } - for (i = 0; i < 10; i++) { - if (stat("/dev/mouse0", &st) == 0) - break; - sleep(1); - } - if ((mouse_fd = open("/dev/mouse0", O_RDONLY|O_NONBLOCK)) < 0) { - perror("/dev/mouse0"); - PM_fatalError("Could not open /dev/mouse0"); - } - } - if ((kbd_fd = open("/dev/keyboard0", O_RDONLY|O_NONBLOCK)) < 0) { - perror("/dev/keyboard0"); - PM_fatalError("Could not open /dev/keyboard0"); - } -#else - /* Connect to Input/Mouse for event handling */ - if (_PM_mouse_ctl == NULL) { - _PM_mouse_ctl = mouse_open(0, "/dev/mouse", 0); - - /* "Mouse" is not running; attempt to start it */ - if (_PM_mouse_ctl == NULL) { - iarg[0] = "mousetrap"; - iarg[1] = "start"; - iarg[2] = NULL; - if ((kill_pid = spawnvp(P_NOWAITO, iarg[0], (void*)iarg)) == -1) - perror("spawn (mousetrap)"); - else { - for (i = 0; i < 10; i++) { - if (stat("/dev/mouse", &st) == 0) - break; - sleep(1); - } - _PM_mouse_ctl = mouse_open(0, "/dev/mouse", 0); - } - } - } - if (_PM_keyboard_fd == -1) - _PM_keyboard_fd = open("/dev/kbd", O_RDONLY|O_NONBLOCK); -#endif - - /* Catch program termination signals so we can clean up properly */ - signal(SIGABRT, _EVT_abort); - signal(SIGFPE, _EVT_abort); - signal(SIGINT, _EVT_abort); -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - rangeX = xRes; - rangeY = yRes; -} - -/**************************************************************************** -REMARKS -Modifes the mouse coordinates as necessary if scaling to OS coordinates, -and sets the OS mouse cursor position. -****************************************************************************/ -#define _EVT_setMousePos(x,y) - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVT_resume(void) -{ - /* Do nothing for QNX */ -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVT_suspend(void) -{ - /* Do nothing for QNX */ -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVT_exit(void) -{ -#ifdef __QNXNTO__ - char c; - int flags; - - if (kbd_fd != -1) { - close(kbd_fd); - kbd_fd = -1; - } - if (mouse_fd != -1) { - close(mouse_fd); - mouse_fd = -1; - } -#endif - - /* Restore signal handlers */ - signal(SIGABRT, SIG_DFL); - signal(SIGFPE, SIG_DFL); - signal(SIGINT, SIG_DFL); - -#ifndef __QNXNTO__ - /* Kill the Input/Mouse driver if we have spawned it */ - if (_PM_mouse_ctl != NULL) { - struct _fd_entry fde; - uint pid = 0; - - /* Find out the pid of the mouse driver */ - if (kill_pid > 0) { - if (qnx_fd_query(0, - 0, _PM_mouse_ctl->fd, &fde) != -1) - pid = fde.pid; - } - mouse_close(_PM_mouse_ctl); - _PM_mouse_ctl = NULL; - - if (pid > 0) { - /* For some reasons the PID's are different under QNX4, - * so we use the old mechanism to kill the mouse server. - */ - kill(pid, SIGTERM); - kill_pid = 0; - } - } -#endif - if (kill_pid > 0) { - kill(kill_pid, SIGTERM); - kill_pid = 0; - } -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c deleted file mode 100644 index f960c75..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: QNX -* -* Description: MTRR helper functions module. To make it easier to implement -* the MTRR support under QNX, we simply put our ring 0 helper -* functions into stubs that run them at ring 0 using whatever -* mechanism is available. -* -****************************************************************************/ - -#include "pmapi.h" -#include -#include -#include -#ifdef __QNXNTO__ -#include -#include -#else -#include -#include -#endif - -/*--------------------------- Global variables ----------------------------*/ - -#define R0_FLUSH_TLB 0 -#define R0_SAVE_CR4 1 -#define R0_RESTORE_CR4 2 -#define R0_READ_MSR 3 -#define R0_WRITE_MSR 4 - -typedef struct { - int service; - int reg; - ulong eax; - ulong edx; - } R0_data; - -extern volatile R0_data _PM_R0; - -/*----------------------------- Implementation ----------------------------*/ - -#ifdef __QNXNTO__ -const struct sigevent * _ASMAPI _PM_ring0_isr(void *arg, int id); -#else -pid_t far _ASMAPI _PM_ring0_isr(); -#endif - -/**************************************************************************** -REMARKS: -Return true if ring 0 (or if we can call the helpers functions at ring 0) -****************************************************************************/ -ibool _ASMAPI _MTRR_isRing0(void) -{ -#ifdef __QNXNTO__ - return false; /* Not implemented yet! */ -#else - return true; -#endif -} - -/**************************************************************************** -REMARKS: -Function to execute a service at ring 0. This is done using the clock -interrupt handler since the code we attach to it will always run at ring 0. -****************************************************************************/ -static void CallRing0(void) -{ -#ifdef __QNXNTO__ - uint clock_intno = SYSPAGE_ENTRY(qtime)->intr; -#else - uint clock_intno = 0; /* clock irq */ -#endif - int intrid; - -#ifdef __QNXNTO__ - mlock((void*)&_PM_R0, sizeof(_PM_R0)); - ThreadCtl(_NTO_TCTL_IO, 0); -#endif -#ifdef __QNXNTO__ - if ((intrid = InterruptAttach(_NTO_INTR_CLASS_EXTERNAL | clock_intno, - _PM_ring0_isr, (void*)&_PM_R0, sizeof(_PM_R0), _NTO_INTR_FLAGS_END)) == -1) { -#else - if ((intrid = qnx_hint_attach(clock_intno, _PM_ring0_isr, FP_SEG(&_PM_R0))) == -1) { -#endif - perror("Attach"); - exit(-1); - } - while (_PM_R0.service != -1) - ; -#ifdef __QNXNTO__ - InterruptDetachId(intrid); -#else - qnx_hint_detach(intrid); -#endif -} - -/**************************************************************************** -REMARKS: -Flush the translation lookaside buffer. -****************************************************************************/ -void PMAPI PM_flushTLB(void) -{ - _PM_R0.service = R0_FLUSH_TLB; - CallRing0(); -} - -/**************************************************************************** -REMARKS: -Read and return the value of the CR4 register -****************************************************************************/ -ulong _ASMAPI _MTRR_saveCR4(void) -{ - _PM_R0.service = R0_SAVE_CR4; - CallRing0(); - return _PM_R0.reg; -} - -/**************************************************************************** -REMARKS: -Restore the value of the CR4 register -****************************************************************************/ -void _ASMAPI _MTRR_restoreCR4(ulong cr4Val) -{ - _PM_R0.service = R0_RESTORE_CR4; - _PM_R0.reg = cr4Val; - CallRing0(); -} - -/**************************************************************************** -REMARKS: -Read a machine status register for the CPU. -****************************************************************************/ -void _ASMAPI _MTRR_readMSR( - int reg, - ulong *eax, - ulong *edx) -{ - _PM_R0.service = R0_READ_MSR; - _PM_R0.reg = reg; - CallRing0(); - *eax = _PM_R0.eax; - *edx = _PM_R0.edx; -} - -/**************************************************************************** -REMARKS: -Write a machine status register for the CPU. -****************************************************************************/ -void _ASMAPI _MTRR_writeMSR( - int reg, - ulong eax, - ulong edx) -{ - _PM_R0.service = R0_WRITE_MSR; - _PM_R0.reg = reg; - _PM_R0.eax = eax; - _PM_R0.edx = edx; - CallRing0(); -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h deleted file mode 100644 index 0961193..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** -* -* SciTech Multi-platform Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: QNX -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ - -#include -#include -#include -#include -#ifndef __QNXNTO__ -#include -#include -#include -#include -#else -#include - -/* Things 'borrowed' from photon/keycodes.h */ - -/* - * Keyboard modifiers - */ -#define KEYMODBIT_SHIFT 0 -#define KEYMODBIT_CTRL 1 -#define KEYMODBIT_ALT 2 -#define KEYMODBIT_ALTGR 3 -#define KEYMODBIT_SHL3 4 -#define KEYMODBIT_MOD6 5 -#define KEYMODBIT_MOD7 6 -#define KEYMODBIT_MOD8 7 - -#define KEYMODBIT_SHIFT_LOCK 8 -#define KEYMODBIT_CTRL_LOCK 9 -#define KEYMODBIT_ALT_LOCK 10 -#define KEYMODBIT_ALTGR_LOCK 11 -#define KEYMODBIT_SHL3_LOCK 12 -#define KEYMODBIT_MOD6_LOCK 13 -#define KEYMODBIT_MOD7_LOCK 14 -#define KEYMODBIT_MOD8_LOCK 15 - -#define KEYMODBIT_CAPS_LOCK 16 -#define KEYMODBIT_NUM_LOCK 17 -#define KEYMODBIT_SCROLL_LOCK 18 - -#define KEYMOD_SHIFT (1 << KEYMODBIT_SHIFT) -#define KEYMOD_CTRL (1 << KEYMODBIT_CTRL) -#define KEYMOD_ALT (1 << KEYMODBIT_ALT) -#define KEYMOD_ALTGR (1 << KEYMODBIT_ALTGR) -#define KEYMOD_SHL3 (1 << KEYMODBIT_SHL3) -#define KEYMOD_MOD6 (1 << KEYMODBIT_MOD6) -#define KEYMOD_MOD7 (1 << KEYMODBIT_MOD7) -#define KEYMOD_MOD8 (1 << KEYMODBIT_MOD8) - -#define KEYMOD_SHIFT_LOCK (1 << KEYMODBIT_SHIFT_LOCK) -#define KEYMOD_CTRL_LOCK (1 << KEYMODBIT_CTRL_LOCK) -#define KEYMOD_ALT_LOCK (1 << KEYMODBIT_ALT_LOCK) -#define KEYMOD_ALTGR_LOCK (1 << KEYMODBIT_ALTGR_LOCK) -#define KEYMOD_SHL3_LOCK (1 << KEYMODBIT_SHL3_LOCK) -#define KEYMOD_MOD6_LOCK (1 << KEYMODBIT_MOD6_LOCK) -#define KEYMOD_MOD7_LOCK (1 << KEYMODBIT_MOD7_LOCK) -#define KEYMOD_MOD8_LOCK (1 << KEYMODBIT_MOD8_LOCK) - -#define KEYMOD_CAPS_LOCK (1 << KEYMODBIT_CAPS_LOCK) -#define KEYMOD_NUM_LOCK (1 << KEYMODBIT_NUM_LOCK) -#define KEYMOD_SCROLL_LOCK (1 << KEYMODBIT_SCROLL_LOCK) - -/* - * Keyboard flags - */ -#define KEY_DOWN 0x00000001 /* Key was pressed down */ -#define KEY_REPEAT 0x00000002 /* Key was repeated */ -#define KEY_SCAN_VALID 0x00000020 /* Scancode is valid */ -#define KEY_SYM_VALID 0x00000040 /* Key symbol is valid */ -#define KEY_CAP_VALID 0x00000080 /* Key cap is valid */ -#define KEY_DEAD 0x40000000 /* Key symbol is a DEAD key */ -#define KEY_OEM_CAP 0x80000000 /* Key cap is an OEM scan code from keyboard */ - -#endif /* __QNXNTO__ */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c deleted file mode 100644 index c993ee0..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c +++ /dev/null @@ -1,891 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: QNX -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include "mtrr.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "qnx/vbios.h" -#ifndef __QNXNTO__ -#include -#include -#include -#include -#else -#include -#include -#endif - -/*--------------------------- Global variables ----------------------------*/ - -static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ -static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ -static uint VESABuf_rseg; /* Real mode segment of VESABuf */ -static uint VESABuf_roff; /* Real mode offset of VESABuf */ -static VBIOSregs_t *VRegs = NULL; /* Pointer to VBIOS registers */ -static int raw_count = 0; -static struct _console_ctrl *cc = NULL; -static int console_count = 0; -static int rmbuf_inuse = 0; - -static void (PMAPIP fatalErrorCleanup)(void) = NULL; - -/*----------------------------- Implementation ----------------------------*/ - -void PMAPI PM_init(void) -{ - char *force; - - if (VRegs == NULL) { -#ifdef __QNXNTO__ - ThreadCtl(_NTO_TCTL_IO, 0); /* Get IO privilidge */ -#endif - force = getenv("VBIOS_METHOD"); - VRegs = VBIOSinit(force ? atoi(force) : 0); - } -#ifndef __QNXNTO__ - MTRR_init(); -#endif -} - -ibool PMAPI PM_haveBIOSAccess(void) -{ return VRegs != NULL; } - -long PMAPI PM_getOSType(void) -{ return _OS_QNX; } - -int PMAPI PM_getModeType(void) -{ return PM_386; } - -void PMAPI PM_backslash(char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '/') { - s[pos] = '/'; - s[pos+1] = '\0'; - } -} - -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -void PMAPI PM_fatalError(const char *msg) -{ - if (fatalErrorCleanup) - fatalErrorCleanup(); - fprintf(stderr,"%s\n", msg); - exit(1); -} - -static void ExitVBEBuf(void) -{ - if (VESABuf_ptr) - PM_freeRealSeg(VESABuf_ptr); - VESABuf_ptr = 0; -} - -void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) -{ - if (!VESABuf_ptr) { - /* Allocate a global buffer for communicating with the VESA VBE */ - if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) - return NULL; - atexit(ExitVBEBuf); - } - *len = VESABuf_len; - *rseg = VESABuf_rseg; - *roff = VESABuf_roff; - return VESABuf_ptr; -} - -static int term_raw(void) -{ - struct termios termios_p; - - if (raw_count++ > 0) - return 0; - - /* Go into "raw" input mode */ - if (tcgetattr(STDIN_FILENO, &termios_p)) - return -1; - - termios_p.c_cc[VMIN] = 1; - termios_p.c_cc[VTIME] = 0; - termios_p.c_lflag &= ~( ECHO|ICANON|ISIG|ECHOE|ECHOK|ECHONL); - tcsetattr(STDIN_FILENO, TCSADRAIN, &termios_p); - return 0; -} - -static void term_restore(void) -{ - struct termios termios_p; - - if (raw_count-- != 1) - return; - - tcgetattr(STDIN_FILENO, &termios_p); - termios_p.c_lflag |= (ECHO|ICANON|ISIG|ECHOE|ECHOK|ECHONL); - termios_p.c_oflag |= (OPOST); - tcsetattr(STDIN_FILENO, TCSADRAIN, &termios_p); -} - -int PMAPI PM_kbhit(void) -{ - int blocking, c; - - if (term_raw() == -1) - return 0; - - /* Go into non blocking mode */ - blocking = fcntl(STDIN_FILENO, F_GETFL) | O_NONBLOCK; - fcntl(STDIN_FILENO, F_SETFL, blocking); - c = getc(stdin); - - /* restore blocking mode */ - fcntl(STDIN_FILENO, F_SETFL, blocking & ~O_NONBLOCK); - term_restore(); - if (c != EOF) { - ungetc(c, stdin); - return c; - } - clearerr(stdin); - return 0; -} - -int PMAPI PM_getch(void) -{ - int c; - - if (term_raw() == -1) - return (0); - c = getc(stdin); -#if defined(__QNX__) && !defined(__QNXNTO__) - if (c == 0xA) - c = 0x0D; - else if (c == 0x7F) - c = 0x08; -#endif - term_restore(); - return c; -} - -PM_HWND PMAPI PM_openConsole( - PM_HWND hwndUser, - int device, - int xRes, - int yRes, - int bpp, - ibool fullScreen) -{ -#ifndef __QNXNTO__ - int fd; - - if (console_count++) - return 0; - if ((fd = open("/dev/con1", O_RDWR)) == -1) - return -1; - cc = console_open(fd, O_RDWR); - close(fd); - if (cc == NULL) - return -1; -#endif - return 1; -} - -int PMAPI PM_getConsoleStateSize(void) -{ - return PM_getVGAStateSize() + sizeof(int) * 3; -} - -void PMAPI PM_saveConsoleState(void *stateBuf,int console_id) -{ -#ifdef __QNXNTO__ - int fd; - int flags; - - if ((fd = open("/dev/con1", O_RDWR)) == -1) - return; - flags = _CONCTL_INVISIBLE_CHG | _CONCTL_INVISIBLE; - devctl(fd, DCMD_CHR_SERCTL, &flags, sizeof flags, 0); - close(fd); -#else - uchar *buf = &((uchar*)stateBuf)[PM_getVGAStateSize()]; - - /* Save QNX 4 console state */ - console_read(cc, -1, 0, NULL, 0, - (int *)buf+1, (int *)buf+2, NULL); - *(int *)buf = console_ctrl(cc, -1, - CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE, - CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE); - - /* Save state of VGA registers */ - PM_saveVGAState(stateBuf); -#endif -} - -void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) -{ - /* TODO: Implement support for console switching if possible */ -} - -void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) -{ -#ifdef __QNXNTO__ - int fd; - int flags; - - if ((fd = open("/dev/con1", O_RDWR)) == -1) - return; - flags = _CONCTL_INVISIBLE_CHG; - devctl(fd, DCMD_CHR_SERCTL, &flags, sizeof flags, 0); - close(fd); -#else - uchar *buf = &((uchar*)stateBuf)[PM_getVGAStateSize()]; - - /* Restore the state of the VGA compatible registers */ - PM_restoreVGAState(stateBuf); - - /* Restore QNX 4 console state */ - console_ctrl(cc, -1, *(int *)buf, - CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE); - console_write(cc, -1, 0, NULL, 0, - (int *)buf+1, (int *)buf+2, NULL); -#endif -} - -void PMAPI PM_closeConsole(PM_HWND hwndConsole) -{ -#ifndef __QNXNTO__ - if (--console_count == 0) { - console_close(cc); - cc = NULL; - } -#endif -} - -void PM_setOSCursorLocation(int x,int y) -{ - if (!cc) - return; -#ifndef __QNXNTO__ - console_write(cc, -1, 0, NULL, 0, &y, &x, NULL); -#endif -} - -void PM_setOSScreenWidth(int width,int height) -{ -} - -ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency) -{ - /* TODO: Implement this for QNX */ - return false; -} - -void PMAPI PM_setRealTimeClockFrequency(int frequency) -{ - /* TODO: Implement this for QNX */ -} - -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - /* TODO: Implement this for QNX */ -} - -char * PMAPI PM_getCurrentPath( - char *path, - int maxLen) -{ - return getcwd(path,maxLen); -} - -char PMAPI PM_getBootDrive(void) -{ return '/'; } - -const char * PMAPI PM_getVBEAFPath(void) -{ return PM_getNucleusConfigPath(); } - -const char * PMAPI PM_getNucleusPath(void) -{ - char *env = getenv("NUCLEUS_PATH"); -#ifdef __QNXNTO__ -#ifdef __X86__ - return env ? env : "/nto/scitech/x86/bin"; -#elif defined (__PPC__) - return env ? env : "/nto/scitech/ppcbe/bin"; -#elif defined (__MIPS__) -#ifdef __BIGENDIAN__ - return env ? env : "/nto/scitech/mipsbe/bin"; -#else - return env ? env : "/nto/scitech/mipsle/bin"; -#endif -#elif defined (__SH__) -#ifdef __BIGENDIAN__ - return env ? env : "/nto/scitech/shbe/bin"; -#else - return env ? env : "/nto/scitech/shle/bin"; -#endif -#elif defined (__ARM__) - return env ? env : "/nto/scitech/armle/bin"; -#endif -#else /* QNX 4 */ - return env ? env : "/qnx4/scitech/bin"; -#endif -} - -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[512]; - char *env; -#ifdef __QNXNTO__ - char temp[64]; - gethostname(temp, sizeof (temp)); - temp[sizeof (temp) - 1] = '\0'; /* Paranoid */ - sprintf(path,"/etc/config/scitech/%s/config", temp); -#else - sprintf(path,"/etc/config/scitech/%d/config", getnid()); -#endif - if ((env = getenv("NUCLEUS_PATH")) != NULL) { - strcpy(path,env); - PM_backslash(path); - strcat(path,"config"); - } - return path; -} - -const char * PMAPI PM_getUniqueID(void) -{ - static char buf[128]; -#ifdef __QNXNTO__ - gethostname(buf, sizeof (buf)); -#else - sprintf(buf,"node%d", getnid()); -#endif - return buf; -} - -const char * PMAPI PM_getMachineName(void) -{ - static char buf[128]; -#ifdef __QNXNTO__ - gethostname(buf, sizeof (buf)); -#else - sprintf(buf,"node%d", getnid()); -#endif - return buf; -} - -void * PMAPI PM_getBIOSPointer(void) -{ - return PM_mapRealPointer(0, 0x400); -} - -void * PMAPI PM_getA0000Pointer(void) -{ - static void *ptr = NULL; - void *freeptr; - unsigned offset, i, maplen; - - if (ptr != NULL) - return ptr; - - /* Some trickery is required to get the linear address 64K aligned */ - for (i = 0; i < 5; i++) { - ptr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); - offset = 0x10000 - ((unsigned)ptr % 0x10000); - if (!offset) - break; - munmap(ptr, 0x10000); - maplen = 0x10000 + offset; - freeptr = PM_mapPhysicalAddr(0xA0000-offset, maplen-1,true); - ptr = (void *)(offset + (unsigned)freeptr); - if (0x10000 - ((unsigned)ptr % 0x10000)) - break; - munmap(freeptr, maplen); - } - if (i == 5) { - printf("Could not get a 64K aligned linear address for A0000 region\n"); - exit(1); - } - return ptr; -} - -void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) -{ - uchar_t *p; - unsigned o; - unsigned prot = PROT_READ|PROT_WRITE|(isCached?0:PROT_NOCACHE); -#ifdef __PAGESIZE - int pagesize = __PAGESIZE; -#else - int pagesize = 4096; -#endif - int rounddown = base % pagesize; -#ifndef __QNXNTO__ - static int __VidFD = -1; -#endif - - if (rounddown) { - if (base < rounddown) - return NULL; - base -= rounddown; - limit += rounddown; - } - -#ifndef __QNXNTO__ - if (__VidFD < 0) { - if ((__VidFD = shm_open( "Physical", O_RDWR, 0777 )) == -1) { - perror( "Cannot open Physical memory" ); - exit(1); - } - } - o = base & 0xFFF; - limit = (limit + o + 0xFFF) & ~0xFFF; - if ((int)(p = mmap( 0, limit, prot, MAP_SHARED, - __VidFD, base )) == -1 ) { - return NULL; - } - p += o; -#else - if ((p = mmap(0, limit, prot, MAP_PHYS | MAP_SHARED, - NOFD, base)) == MAP_FAILED) { - return (void *)-1; - } -#endif - return (p + rounddown); -} - -void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) -{ - munmap(ptr,limit+1); -} - -ulong PMAPI PM_getPhysicalAddr(void *p) -{ - /* TODO: This function should find the physical address of a linear */ - /* address. */ - return 0xFFFFFFFFUL; -} - -ibool PMAPI PM_getPhysicalAddrRange( - void *p, - ulong length, - ulong *physAddress) -{ - /* TODO: Implement this! */ - return false; -} - -void PMAPI PM_sleep(ulong milliseconds) -{ - /* TODO: Put the process to sleep for milliseconds */ -} - -int PMAPI PM_getCOMPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - } - return 0; -} - -int PMAPI PM_getLPTPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -void * PMAPI PM_mallocShared(long size) -{ - return PM_malloc(size); -} - -void PMAPI PM_freeShared(void *ptr) -{ - PM_free(ptr); -} - -void * PMAPI PM_mapToProcess(void *base,ulong limit) -{ return (void*)base; } - -void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) -{ - void *p; - - PM_init(); - - if ((p = VBIOSgetmemptr(r_seg, r_off, VRegs)) == (void *)-1) - return NULL; - return p; -} - -void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) -{ - if (size > 1024) { - printf("PM_allocRealSeg: can't handle %d bytes\n", size); - return 0; - } - if (rmbuf_inuse != 0) { - printf("PM_allocRealSeg: transfer area already in use\n"); - return 0; - } - PM_init(); - rmbuf_inuse = 1; - *r_seg = VBIOS_TransBufVSeg(VRegs); - *r_off = VBIOS_TransBufVOff(VRegs); - return (void*)VBIOS_TransBufPtr(VRegs); -} - -void PMAPI PM_freeRealSeg(void *mem) -{ - if (rmbuf_inuse == 0) { - printf("PM_freeRealSeg: nothing was allocated\n"); - return; - } - rmbuf_inuse = 0; -} - -void PMAPI DPMI_int86(int intno, DPMI_regs *regs) -{ - PM_init(); - if (VRegs == NULL) - return; - - VRegs->l.eax = regs->eax; - VRegs->l.ebx = regs->ebx; - VRegs->l.ecx = regs->ecx; - VRegs->l.edx = regs->edx; - VRegs->l.esi = regs->esi; - VRegs->l.edi = regs->edi; - - VBIOSint(intno, VRegs, 1024); - - regs->eax = VRegs->l.eax; - regs->ebx = VRegs->l.ebx; - regs->ecx = VRegs->l.ecx; - regs->edx = VRegs->l.edx; - regs->esi = VRegs->l.esi; - regs->edi = VRegs->l.edi; - regs->flags = VRegs->w.flags & 0x1; -} - -int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) -{ - PM_init(); - if (VRegs == NULL) - return 0; - - VRegs->l.eax = in->e.eax; - VRegs->l.ebx = in->e.ebx; - VRegs->l.ecx = in->e.ecx; - VRegs->l.edx = in->e.edx; - VRegs->l.esi = in->e.esi; - VRegs->l.edi = in->e.edi; - - VBIOSint(intno, VRegs, 1024); - - out->e.eax = VRegs->l.eax; - out->e.ebx = VRegs->l.ebx; - out->e.ecx = VRegs->l.ecx; - out->e.edx = VRegs->l.edx; - out->e.esi = VRegs->l.esi; - out->e.edi = VRegs->l.edi; - out->x.cflag = VRegs->w.flags & 0x1; - - return out->x.ax; -} - -int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, - RMSREGS *sregs) -{ - PM_init(); - if (VRegs == NULL) - return 0; - - if (intno == 0x21) { - time_t today = time(NULL); - struct tm *t; - t = localtime(&today); - out->x.cx = t->tm_year + 1900; - out->h.dh = t->tm_mon + 1; - out->h.dl = t->tm_mday; - return 0; - } - else { - VRegs->l.eax = in->e.eax; - VRegs->l.ebx = in->e.ebx; - VRegs->l.ecx = in->e.ecx; - VRegs->l.edx = in->e.edx; - VRegs->l.esi = in->e.esi; - VRegs->l.edi = in->e.edi; - VRegs->w.es = sregs->es; - VRegs->w.ds = sregs->ds; - - VBIOSint(intno, VRegs, 1024); - - out->e.eax = VRegs->l.eax; - out->e.ebx = VRegs->l.ebx; - out->e.ecx = VRegs->l.ecx; - out->e.edx = VRegs->l.edx; - out->e.esi = VRegs->l.esi; - out->e.edi = VRegs->l.edi; - out->x.cflag = VRegs->w.flags & 0x1; - sregs->es = VRegs->w.es; - sregs->ds = VRegs->w.ds; - - return out->x.ax; - } -} - -void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, - RMSREGS *sregs) -{ - PM_init(); - if (VRegs == NULL) - return; - - VRegs->l.eax = in->e.eax; - VRegs->l.ebx = in->e.ebx; - VRegs->l.ecx = in->e.ecx; - VRegs->l.edx = in->e.edx; - VRegs->l.esi = in->e.esi; - VRegs->l.edi = in->e.edi; - VRegs->w.es = sregs->es; - VRegs->w.ds = sregs->ds; - - VBIOScall(seg, off, VRegs, 1024); - - in->e.eax = VRegs->l.eax; - in->e.ebx = VRegs->l.ebx; - in->e.ecx = VRegs->l.ecx; - in->e.edx = VRegs->l.edx; - in->e.esi = VRegs->l.esi; - in->e.edi = VRegs->l.edi; - in->x.cflag = VRegs->w.flags & 0x1; - sregs->es = VRegs->w.es; - sregs->ds = VRegs->w.ds; -} - -void PMAPI PM_availableMemory(ulong *physical,ulong *total) -{ -#ifndef __QNXNTO__ - *physical = *total = _memavl(); -#endif -} - -void * PMAPI PM_allocLockedMem( - uint size, - ulong *physAddr, - ibool contiguous, - ibool below16M) -{ - /* TODO: Implement this on QNX */ - return NULL; -} - -void PMAPI PM_freeLockedMem( - void *p, - uint size, - ibool contiguous) -{ - /* TODO: Implement this on QNX */ -} - -void * PMAPI PM_allocPage( - ibool locked) -{ - /* TODO: Implement this on QNX */ - return NULL; -} - -void PMAPI PM_freePage( - void *p) -{ - /* TODO: Implement this on QNX */ -} - -void PMAPI PM_setBankA(int bank) -{ - PM_init(); - if (VRegs == NULL) - return; - - VRegs->l.eax = 0x4F05; - VRegs->l.ebx = 0x0000; - VRegs->l.edx = bank; - VBIOSint(0x10, VRegs, 1024); -} - -void PMAPI PM_setBankAB(int bank) -{ - PM_init(); - if (VRegs == NULL) - return; - - VRegs->l.eax = 0x4F05; - VRegs->l.ebx = 0x0000; - VRegs->l.edx = bank; - VBIOSint(0x10, VRegs, 1024); - - VRegs->l.eax = 0x4F05; - VRegs->l.ebx = 0x0001; - VRegs->l.edx = bank; - VBIOSint(0x10, VRegs, 1024); -} - -void PMAPI PM_setCRTStart(int x,int y,int waitVRT) -{ - PM_init(); - if (VRegs == NULL) - return; - - VRegs->l.eax = 0x4F07; - VRegs->l.ebx = waitVRT; - VRegs->l.ecx = x; - VRegs->l.edx = y; - VBIOSint(0x10, VRegs, 1024); -} - -ibool PMAPI PM_doBIOSPOST( - ushort axVal, - ulong BIOSPhysAddr, - void *copyOfBIOS, - ulong BIOSLen) -{ - (void)axVal; - (void)BIOSPhysAddr; - (void)copyOfBIOS; - (void)BIOSLen; - return false; -} - -int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - p = p; len = len; - return 1; -} - -int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - p = p; len = len; - return 1; -} - -int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - p = p; len = len; - return 1; -} - -int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - p = p; len = len; - return 1; -} - -PM_MODULE PMAPI PM_loadLibrary( - const char *szDLLName) -{ - /* TODO: Implement this to load shared libraries! */ - (void)szDLLName; - return NULL; -} - -void * PMAPI PM_getProcAddress( - PM_MODULE hModule, - const char *szProcName) -{ - /* TODO: Implement this! */ - (void)hModule; - (void)szProcName; - return NULL; -} - -void PMAPI PM_freeLibrary( - PM_MODULE hModule) -{ - /* TODO: Implement this! */ - (void)hModule; -} - -int PMAPI PM_setIOPL( - int level) -{ - /* QNX handles IOPL selection at the program link level. */ - return level; -} - -/**************************************************************************** -PARAMETERS: -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -RETURNS: -Error code describing the result. - -REMARKS: -Function to enable write combining for the specified region of memory. -****************************************************************************/ -int PMAPI PM_enableWriteCombine( - ulong base, - ulong size, - uint type) -{ -#ifndef __QNXNTO__ - return MTRR_enableWriteCombine(base,size,type); -#else - return PM_MTRR_NOT_SUPPORTED; -#endif -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c deleted file mode 100644 index 579ef2c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Dummy module; no virtual framebuffer for this OS -* -****************************************************************************/ - -#include "pmapi.h" - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -{ - baseAddr = baseAddr; - bankSize = bankSize; - codeLen = codeLen; - bankFunc = bankFunc; - return NULL; -} - -void PMAPI VF_exit(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c deleted file mode 100644 index d274097..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: QNX -* -* Description: QNX specific implementation for the Zen Timer functions. -* -****************************************************************************/ - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -void __ZTimerInit(void) -{ -} - -/**************************************************************************** -REMARKS: -Use the gettimeofday() function to get microsecond precision (probably less -though) -****************************************************************************/ -static ulong __ULZReadTime(void) -{ - struct timespec ts; - clock_gettime(CLOCK_REALTIME, &ts); - return (ts.tv_nsec / 1000 + ts.tv_sec * 1000000); -} - -/**************************************************************************** -REMARKS: -Start the Zen Timer counting. -****************************************************************************/ -#define __LZTimerOn(tm) tm->start.low = __ULZReadTime() - -/**************************************************************************** -REMARKS: -Compute the lap time since the timer was started. -****************************************************************************/ -#define __LZTimerLap(tm) (__ULZReadTime() - tm->start.low) - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerOff(tm) tm->end.low = __ULZReadTime() - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerCount(tm) (tm->end.low - tm->start.low) - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as microseconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION 1 - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong __ULZElapsedTime(ulong start,ulong finish) -{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c deleted file mode 100644 index 4f32c3e..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c +++ /dev/null @@ -1,94 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: RTTarget-32 -* -* Description: Module to implement OS specific services to measure the -* CPU frequency. -* -****************************************************************************/ - -/*---------------------------- Global variables ---------------------------*/ - -static ibool havePerformanceCounter; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Increase the thread priority to maximum, if possible. -****************************************************************************/ -static int SetMaxThreadPriority(void) -{ - int oldPriority; - HANDLE hThread = GetCurrentThread(); - - oldPriority = GetThreadPriority(hThread); - if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) - SetThreadPriority(hThread, THREAD_PRIORITY_TIME_CRITICAL); - return oldPriority; -} - -/**************************************************************************** -REMARKS: -Restore the original thread priority. -****************************************************************************/ -static void RestoreThreadPriority( - int oldPriority) -{ - HANDLE hThread = GetCurrentThread(); - - if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) - SetThreadPriority(hThread, oldPriority); -} - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - if (!QueryPerformanceFrequency((LARGE_INTEGER*)freq)) { - havePerformanceCounter = false; - freq->low = 100000; - freq->high = 0; - } - else - havePerformanceCounter = true; -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. -****************************************************************************/ -#define GetCounter(t) \ -{ \ - if (havePerformanceCounter) \ - QueryPerformanceCounter((LARGE_INTEGER*)t); \ - else { \ - (t)->low = timeGetTime() * 100; \ - (t)->high = 0; \ - } \ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c deleted file mode 100644 index 962a14a..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c +++ /dev/null @@ -1,287 +0,0 @@ -/**************************************************************************** -* -* SciTech Multi-platform Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: RTTarget-32 -* -* Description: Win32 implementation for the SciTech cross platform -* event library. -* -****************************************************************************/ - -/*---------------------------- Global Variables ---------------------------*/ - -static ushort keyUpMsg[256] = {0}; /* Table of key up messages */ -static int rangeX,rangeY; /* Range of mouse coordinates */ - -/*---------------------------- Implementation -----------------------------*/ - -/* These are not used under Win32 */ -#define _EVT_disableInt() 1 -#define _EVT_restoreInt(flags) - -/**************************************************************************** -PARAMETERS: -scanCode - Scan code to test - -REMARKS: -This macro determines if a specified key is currently down at the -time that the call is made. -****************************************************************************/ -#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) - -/**************************************************************************** -REMARKS: -This function is used to return the number of ticks since system -startup in milliseconds. This should be the same value that is placed into -the time stamp fields of events, and is used to implement auto mouse down -events. -****************************************************************************/ -ulong _EVT_getTicks(void) -{ return timeGetTime(); } - -/**************************************************************************** -REMARKS: -Pumps all messages in the message queue from Win32 into our event queue. -****************************************************************************/ -void _EVT_pumpMessages(void) -{ - MSG msg; - MSG charMsg; - event_t evt; - - while (PeekMessage(&msg,NULL,0,0,PM_REMOVE)) { - memset(&evt,0,sizeof(evt)); - switch (msg.message) { - case WM_MOUSEMOVE: - evt.what = EVT_MOUSEMOVE; - break; - case WM_LBUTTONDBLCLK: - evt.what = EVT_MOUSEDOWN; - evt.message = EVT_LEFTBMASK | EVT_DBLCLICK; - break; - case WM_LBUTTONDOWN: - evt.what = EVT_MOUSEDOWN; - evt.message = EVT_LEFTBMASK; - break; - case WM_LBUTTONUP: - evt.what = EVT_MOUSEUP; - evt.message = EVT_LEFTBMASK; - break; - case WM_RBUTTONDBLCLK: - evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK; - evt.message = EVT_RIGHTBMASK; - break; - case WM_RBUTTONDOWN: - evt.what = EVT_MOUSEDOWN; - evt.message = EVT_RIGHTBMASK; - break; - case WM_RBUTTONUP: - evt.what = EVT_MOUSEUP; - evt.message = EVT_RIGHTBMASK; - break; - case WM_KEYDOWN: - case WM_SYSKEYDOWN: - if (HIWORD(msg.lParam) & KF_REPEAT) { - evt.what = EVT_KEYREPEAT; - } - else { - evt.what = EVT_KEYDOWN; - } - break; - case WM_KEYUP: - case WM_SYSKEYUP: - evt.what = EVT_KEYUP; - break; - } - - /* Convert mouse event modifier flags */ - if (evt.what & EVT_MOUSEEVT) { - evt.where_x = msg.pt.x; - evt.where_y = msg.pt.y; - if (evt.what == EVT_MOUSEMOVE) { - if (oldMove != -1) { - evtq[oldMove].where_x = evt.where_x;/* Modify existing one */ - evtq[oldMove].where_y = evt.where_y; - evt.what = 0; - } - else { - oldMove = freeHead; /* Save id of this move event */ - } - } - else - oldMove = -1; - if (msg.wParam & MK_LBUTTON) - evt.modifiers |= EVT_LEFTBUT; - if (msg.wParam & MK_RBUTTON) - evt.modifiers |= EVT_RIGHTBUT; - if (msg.wParam & MK_SHIFT) - evt.modifiers |= EVT_SHIFTKEY; - if (msg.wParam & MK_CONTROL) - evt.modifiers |= EVT_CTRLSTATE; - } - - /* Convert keyboard codes */ - TranslateMessage(&msg); - if (evt.what & EVT_KEYEVT) { - int scanCode = (msg.lParam >> 16) & 0xFF; - if (evt.what == EVT_KEYUP) { - /* Get message for keyup code from table of cached down values */ - evt.message = keyUpMsg[scanCode]; - keyUpMsg[scanCode] = 0; - } - else { - if (PeekMessage(&charMsg,NULL,WM_CHAR,WM_CHAR,PM_REMOVE)) - evt.message = charMsg.wParam; - if (PeekMessage(&charMsg,NULL,WM_SYSCHAR,WM_SYSCHAR,PM_REMOVE)) - evt.message = charMsg.wParam; - evt.message |= ((msg.lParam >> 8) & 0xFF00); - keyUpMsg[scanCode] = (ushort)evt.message; - } - if (evt.what == EVT_KEYREPEAT) - evt.message |= (msg.lParam << 16); - if (HIWORD(msg.lParam) & KF_ALTDOWN) - evt.modifiers |= EVT_ALTSTATE; - if (GetKeyState(VK_SHIFT) & 0x8000U) - evt.modifiers |= EVT_SHIFTKEY; - if (GetKeyState(VK_CONTROL) & 0x8000U) - evt.modifiers |= EVT_CTRLSTATE; - oldMove = -1; - } - - if (evt.what != 0) { - /* Add time stamp and add the event to the queue */ - evt.when = msg.time; - if (count < EVENTQSIZE) { - addEvent(&evt); - } - } - DispatchMessage(&msg); - } -} - -/**************************************************************************** -REMARKS: -This macro/function is used to converts the scan codes reported by the -keyboard to our event libraries normalised format. We only have one scan -code for the 'A' key, and use shift modifiers to determine if it is a -Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, -but the OS gives us 'cooked' scan codes, we have to translate them back -to the raw format. -****************************************************************************/ -#define _EVT_maskKeyCode(evt) - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _EVT_abort() -{ - EVT_exit(); - PM_fatalError("Unhandled exception!"); -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -void EVTAPI EVT_init( - _EVT_mouseMoveHandler mouseMove) -{ - /* Initialise the event queue */ - _mouseMove = mouseMove; - initEventQueue(); - memset(keyUpMsg,0,sizeof(keyUpMsg)); - - /* Catch program termination signals so we can clean up properly */ - signal(SIGABRT, _EVT_abort); - signal(SIGFPE, _EVT_abort); - signal(SIGINT, _EVT_abort); -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - rangeX = xRes; - rangeY = yRes; -} - -/**************************************************************************** -REMARKS -Modifes the mouse coordinates as necessary if scaling to OS coordinates, -and sets the OS mouse cursor position. -****************************************************************************/ -void _EVT_setMousePos( - int *x, - int *y) -{ - SetCursorPos(*x,*y); -} - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVT_resume(void) -{ - /* Do nothing for Win32 */ -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVT_suspend(void) -{ - /* Do nothing for Win32 */ -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVT_exit(void) -{ - /* Restore signal handlers */ - signal(SIGABRT, SIG_DFL); - signal(SIGFPE, SIG_DFL); - signal(SIGINT, SIG_DFL); -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h deleted file mode 100644 index 1352dad..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h +++ /dev/null @@ -1,34 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: RTTarget-32 -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ - -#define WIN32_LEAN_AND_MEAN -#define STRICT -#include -#include diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c deleted file mode 100644 index 47d7ed6..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c +++ /dev/null @@ -1,701 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: RTTarget-32 -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include -#include -#include -#define WIN32_LEAN_AND_MEAN -#define STRICT -#include -#include -#ifdef __BORLANDC__ -#pragma warn -par -#endif - -/*--------------------------- Global variables ----------------------------*/ - -static void (PMAPIP fatalErrorCleanup)(void) = NULL; - -/*----------------------------- Implementation ----------------------------*/ - -void MTRR_init(void); - -/**************************************************************************** -REMARKS: -Initialise the PM library. -****************************************************************************/ -void PMAPI PM_init(void) -{ - /* TODO: dO any special init code in here. */ - MTRR_init(); -} - -/**************************************************************************** -REMARKS: -Return the operating system type identifier. -****************************************************************************/ -long PMAPI PM_getOSType(void) -{ - return _OS_RTTARGET; -} - -/**************************************************************************** -REMARKS: -Return the runtime type identifier. -****************************************************************************/ -int PMAPI PM_getModeType(void) -{ - return PM_386; -} - -/**************************************************************************** -REMARKS: -Add a file directory separator to the end of the filename. -****************************************************************************/ -void PMAPI PM_backslash( - char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '\\') { - s[pos] = '\\'; - s[pos+1] = '\0'; - } -} - -/**************************************************************************** -REMARKS: -Add a user defined PM_fatalError cleanup function. -****************************************************************************/ -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -/**************************************************************************** -REMARKS: -Report a fatal error condition and halt the program. -****************************************************************************/ -void PMAPI PM_fatalError( - const char *msg) -{ - if (fatalErrorCleanup) - fatalErrorCleanup(); - /* TODO: Display a fatal error message and exit! */ -/* MessageBox(NULL,msg,"Fatal Error!", MB_ICONEXCLAMATION); */ - exit(1); -} - -/**************************************************************************** -REMARKS: -Allocate the real mode VESA transfer buffer for communicating with the BIOS. -****************************************************************************/ -void * PMAPI PM_getVESABuf( - uint *len, - uint *rseg, - uint *roff) -{ - /* No BIOS access for the RTTarget */ - return NULL; -} - -/**************************************************************************** -REMARKS: -Check if a key has been pressed. -****************************************************************************/ -int PMAPI PM_kbhit(void) -{ - /* TODO: Need to check if a key is waiting on the keyboard queue */ - return true; -} - -/**************************************************************************** -REMARKS: -Wait for and return the next keypress. -****************************************************************************/ -int PMAPI PM_getch(void) -{ - /* TODO: Need to obtain the next keypress, and block until one is hit */ - return 0xD; -} - -/**************************************************************************** -REMARKS: -Set the location of the OS console cursor. -****************************************************************************/ -void PM_setOSCursorLocation( - int x, - int y) -{ - /* Nothing to do for RTTarget-32 */ -} - -/**************************************************************************** -REMARKS: -Set the width of the OS console. -****************************************************************************/ -void PM_setOSScreenWidth( - int width, - int height) -{ - /* Nothing to do for RTTarget-32 */ -} - -/**************************************************************************** -REMARKS: -Set the real time clock handler (used for software stereo modes). -****************************************************************************/ -ibool PMAPI PM_setRealTimeClockHandler( - PM_intHandler ih, - int frequency) -{ - /* Not supported for RTTarget-32 */ - return false; -} - -/**************************************************************************** -REMARKS: -Set the real time clock frequency (for stereo modes). -****************************************************************************/ -void PMAPI PM_setRealTimeClockFrequency( - int frequency) -{ - /* Not supported under RTTarget-32 */ -} - -/**************************************************************************** -REMARKS: -Restore the original real time clock handler. -****************************************************************************/ -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - /* Not supported under RTTarget-32 */ -} - -/**************************************************************************** -REMARKS: -Return the current operating system path or working directory. -****************************************************************************/ -char * PMAPI PM_getCurrentPath( - char *path, - int maxLen) -{ - return getcwd(path,maxLen); -} - -/**************************************************************************** -REMARKS: -Return the drive letter for the boot drive. -****************************************************************************/ -char PMAPI PM_getBootDrive(void) -{ - return 'c'; -} - -/**************************************************************************** -REMARKS: -Return the path to the VBE/AF driver files. -****************************************************************************/ -const char * PMAPI PM_getVBEAFPath(void) -{ - return "c:\\"; -} - -/**************************************************************************** -REMARKS: -Return the path to the Nucleus driver files. -****************************************************************************/ -const char * PMAPI PM_getNucleusPath(void) -{ - /* TODO: Point this at the path when the Nucleus drivers will be found */ - return "c:\\nucleus"; -} - -/**************************************************************************** -REMARKS: -Return the path to the Nucleus configuration files. -****************************************************************************/ -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[256]; - strcpy(path,PM_getNucleusPath()); - PM_backslash(path); - strcat(path,"config"); - return path; -} - -/**************************************************************************** -REMARKS: -Return a unique identifier for the machine if possible. -****************************************************************************/ -const char * PMAPI PM_getUniqueID(void) -{ - return PM_getMachineName(); -} - -/**************************************************************************** -REMARKS: -Get the name of the machine on the network. -****************************************************************************/ -const char * PMAPI PM_getMachineName(void) -{ - /* Not necessary for RTTarget-32 */ - return "Unknown"; -} - -/**************************************************************************** -REMARKS: -Return a pointer to the real mode BIOS data area. -****************************************************************************/ -void * PMAPI PM_getBIOSPointer(void) -{ - /* Not used for RTTarget-32 */ - return NULL; -} - -/**************************************************************************** -REMARKS: -Return a pointer to 0xA0000 physical VGA graphics framebuffer. -****************************************************************************/ -void * PMAPI PM_getA0000Pointer(void) -{ - static void *bankPtr; - if (!bankPtr) - bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); - return bankPtr; -} - -/**************************************************************************** -REMARKS: -Map a physical address to a linear address in the callers process. -****************************************************************************/ -void * PMAPI PM_mapPhysicalAddr( - ulong base, - ulong limit, - ibool isCached) -{ - /* TODO: Map a physical memory address to a linear address */ - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a physical address mapping allocated by PM_mapPhysicalAddr. -****************************************************************************/ -void PMAPI PM_freePhysicalAddr( - void *ptr, - ulong limit) -{ - /* TODO: Free the physical address mapping */ -} - -ulong PMAPI PM_getPhysicalAddr(void *p) -{ - /* TODO: This function should find the physical address of a linear */ - /* address. */ - return 0xFFFFFFFFUL; -} - -void PMAPI PM_sleep(ulong milliseconds) -{ - Sleep(milliseconds); -} - -int PMAPI PM_getCOMPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - } - return 0; -} - -int PMAPI PM_getLPTPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -/**************************************************************************** -REMARKS: -Allocate a block of (unnamed) shared memory. -****************************************************************************/ -void * PMAPI PM_mallocShared( - long size) -{ - return PM_malloc(size); -} - -/**************************************************************************** -REMARKS: -Free a block of shared memory. -****************************************************************************/ -void PMAPI PM_freeShared( - void *ptr) -{ - PM_free(ptr); -} - -/**************************************************************************** -REMARKS: -Map a linear memory address to the calling process address space. The -address will have been allocated in another process using the -PM_mapPhysicalAddr function. -****************************************************************************/ -void * PMAPI PM_mapToProcess( - void *base, - ulong limit) -{ - return base; -} - -/**************************************************************************** -REMARKS: -Map a real mode pointer to a protected mode pointer. -****************************************************************************/ -void * PMAPI PM_mapRealPointer( - uint r_seg, - uint r_off) -{ - /* Not used for RTTarget-32 */ - return NULL; -} - -/**************************************************************************** -REMARKS: -Allocate a block of real mode memory -****************************************************************************/ -void * PMAPI PM_allocRealSeg( - uint size, - uint *r_seg, - uint *r_off) -{ - /* Not used for RTTarget-32 */ - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a block of real mode memory. -****************************************************************************/ -void PMAPI PM_freeRealSeg( - void *mem) -{ - /* Not used for RTTarget-32 */ -} - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt (parameters in DPMI compatible structure) -****************************************************************************/ -void PMAPI DPMI_int86( - int intno, - DPMI_regs *regs) -{ - /* Not used for RTTarget-32 */ -} - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt. -****************************************************************************/ -int PMAPI PM_int86( - int intno, - RMREGS *in, - RMREGS *out) -{ - /* Not used for RTTarget-32 */ - return 0; -} - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt. -****************************************************************************/ -int PMAPI PM_int86x( - int intno, - RMREGS *in, - RMREGS *out, - RMSREGS *sregs) -{ - /* Not used for RTTarget-32 */ - return 0; -} - -/**************************************************************************** -REMARKS: -Call a real mode far function. -****************************************************************************/ -void PMAPI PM_callRealMode( - uint seg, - uint off, - RMREGS *in, - RMSREGS *sregs) -{ - /* Not used for RTTarget-32 */ -} - -/**************************************************************************** -REMARKS: -Return the amount of available memory. -****************************************************************************/ -void PMAPI PM_availableMemory( - ulong *physical, - ulong *total) -{ - /* TODO: Figure out how to determine the available memory. Not entirely */ - /* critical so returning 0 is OK. */ - *physical = *total = 0; -} - -/**************************************************************************** -REMARKS: -Allocate a block of locked, physical memory for DMA operations. -****************************************************************************/ -void * PMAPI PM_allocLockedMem( - uint size, - ulong *physAddr, - ibool contiguous, - ibool below16M) -{ - /* TODO: Allocate a block of locked, phsyically contigous memory for DMA */ - return 0; -} - -/**************************************************************************** -REMARKS: -Free a block of locked physical memory. -****************************************************************************/ -void PMAPI PM_freeLockedMem( - void *p, - uint size, - - ibool contiguous) -{ - /* TODO: Free a locked memory buffer */ -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display banks. -****************************************************************************/ -void PMAPI PM_setBankA( - int bank) -{ - /* Not used for RTTarget-32 */ -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display banks. -****************************************************************************/ -void PMAPI PM_setBankAB( - int bank) -{ - /* Not used for RTTarget-32 */ -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display start address. -****************************************************************************/ -void PMAPI PM_setCRTStart( - int x, - int y, - int waitVRT) -{ - /* Not used for RTTarget-32 */ -} - -/**************************************************************************** -REMARKS: -Execute the POST on the secondary BIOS for a controller. -****************************************************************************/ -ibool PMAPI PM_doBIOSPOST( - ushort axVal, - ulong BIOSPhysAddr, - void *mappedBIOS) -{ - /* Not used for RTTarget-32 */ - return false; -} - -PM_MODULE PMAPI PM_loadLibrary( - const char *szDLLName) -{ - /* TODO: Implement this to load shared libraries! */ - (void)szDLLName; - return NULL; -} - -void * PMAPI PM_getProcAddress( - PM_MODULE hModule, - const char *szProcName) -{ - /* TODO: Implement this! */ - (void)hModule; - (void)szProcName; - return NULL; -} - -void PMAPI PM_freeLibrary( - PM_MODULE hModule) -{ - /* TODO: Implement this! */ - (void)hModule; -} - -/**************************************************************************** -REMARKS: -Function to find the first file matching a search criteria in a directory. -****************************************************************************/ -ulong PMAPI PM_findFirstFile( - const char *filename, - PM_findData *findData) -{ - /* TODO: This function should start a directory enumeration search */ - /* given the filename (with wildcards). The data should be */ - /* converted and returned in the findData standard form. */ - (void)filename; - (void)findData; - return PM_FILE_INVALID; -} - -/**************************************************************************** -REMARKS: -Function to find the next file matching a search criteria in a directory. -****************************************************************************/ -ibool PMAPI PM_findNextFile( - ulong handle, - PM_findData *findData) -{ - /* TODO: This function should find the next file in directory enumeration */ - /* search given the search criteria defined in the call to */ - /* PM_findFirstFile. The data should be converted and returned */ - /* in the findData standard form. */ - (void)handle; - (void)findData; - return false; -} - -/**************************************************************************** -REMARKS: -Function to close the find process -****************************************************************************/ -void PMAPI PM_findClose( - ulong handle) -{ - /* TODO: This function should close the find process. This may do */ - /* nothing for some OS'es. */ - (void)handle; -} - -/**************************************************************************** -REMARKS: -Function to determine if a drive is a valid drive or not. Under Unix this -function will return false for anything except a value of 3 (considered -the root drive, and equivalent to C: for non-Unix systems). The drive -numbering is: - - 1 - Drive A: - 2 - Drive B: - 3 - Drive C: - etc - -****************************************************************************/ -ibool PMAPI PM_driveValid( - char drive) -{ - if (drive == 3) - return true; - return false; -} - -/**************************************************************************** -REMARKS: -Function to get the current working directory for the specififed drive. -Under Unix this will always return the current working directory regardless -of what the value of 'drive' is. -****************************************************************************/ -void PMAPI PM_getdcwd( - int drive, - char *dir, - int len) -{ - (void)drive; - getcwd(dir,len); -} - -/**************************************************************************** -REMARKS: -Function to change the file attributes for a specific file. -****************************************************************************/ -void PMAPI PM_setFileAttr( - const char *filename, - uint attrib) -{ - /* TODO: Set the file attributes for a file */ - (void)filename; - (void)attrib; -} - -/**************************************************************************** -REMARKS: -Function to create a directory. -****************************************************************************/ -ibool PMAPI PM_mkdir( - const char *filename) -{ - return mkdir(filename) == 0; -} - -/**************************************************************************** -REMARKS: -Function to remove a directory. -****************************************************************************/ -ibool PMAPI PM_rmdir( - const char *filename) -{ - return rmdir(filename) == 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c deleted file mode 100644 index dd9dfe6..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c +++ /dev/null @@ -1,48 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: RTTarget-32 -* -* Description: Dummy module; no virtual framebuffer for this OS -* -****************************************************************************/ - -#include "pmapi.h" -#ifdef __BORLANDC__ -#pragma warn -par -#endif - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -{ - return NULL; -} - -void PMAPI VF_exit(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c deleted file mode 100644 index 80c184d..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: RTTarget-32 -* -* Description: OS specific implementation for the Zen Timer functions. -* -****************************************************************************/ - -/*---------------------------- Global variables ---------------------------*/ - -static CPU_largeInteger countFreq; -static ibool havePerformanceCounter; -static ulong start,finish; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -void __ZTimerInit(void) -{ -#ifdef NO_ASSEMBLER - havePerformanceCounter = false; -#else - havePerformanceCounter = QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq); -#endif -} - -/**************************************************************************** -REMARKS: -Start the Zen Timer counting. -****************************************************************************/ -static void __LZTimerOn( - LZTimerObject *tm) -{ - if (havePerformanceCounter) - QueryPerformanceCounter((LARGE_INTEGER*)&tm->start); - else - tm->start.low = timeGetTime(); -} - -/**************************************************************************** -REMARKS: -Compute the lap time since the timer was started. -****************************************************************************/ -static ulong __LZTimerLap( - LZTimerObject *tm) -{ - CPU_largeInteger tmLap,tmCount; - - if (havePerformanceCounter) { - QueryPerformanceCounter((LARGE_INTEGER*)&tmLap); - _CPU_diffTime64(&tm->start,&tmLap,&tmCount); - return _CPU_calcMicroSec(&tmCount,countFreq.low); - } - else { - tmLap.low = timeGetTime(); - return (tmLap.low - tm->start.low) * 1000L; - } -} - -/**************************************************************************** -REMARKS: -Stop the Zen Timer counting. -****************************************************************************/ -static void __LZTimerOff( - LZTimerObject *tm) -{ - if (havePerformanceCounter) - QueryPerformanceCounter((LARGE_INTEGER*)&tm->end); - else - tm->end.low = timeGetTime(); -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time in microseconds between start and end timings. -****************************************************************************/ -static ulong __LZTimerCount( - LZTimerObject *tm) -{ - CPU_largeInteger tmCount; - - if (havePerformanceCounter) { - _CPU_diffTime64(&tm->start,&tm->end,&tmCount); - return _CPU_calcMicroSec(&tmCount,countFreq.low); - } - else - return (tm->end.low - tm->start.low) * 1000L; -} - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as microseconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION 1000 - -/**************************************************************************** -REMARKS: -Read the Long Period timer from the OS -****************************************************************************/ -static ulong __ULZReadTime(void) -{ return timeGetTime(); } - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong __ULZElapsedTime(ulong start,ulong finish) -{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm deleted file mode 100644 index da62b1f..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm +++ /dev/null @@ -1,175 +0,0 @@ -;**************************************************************************** -;* -;* SciTech Multi-platform Graphics Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler -;* Environment: IBM PC (MS DOS) -;* -;* Description: Assembly language support routines for the event module. -;* -;**************************************************************************** - - ideal - -include "scitech.mac" ; Memory model macros - -ifdef flatmodel - -header _event ; Set up memory model - -begdataseg _event - - cextern _EVT_biosPtr,DPTR - - cpublic _EVT_dataStart - -ifdef USE_NASM -%define KB_HEAD WORD esi+01Ah ; Keyboard buffer head in BIOS data area -%define KB_TAIL WORD esi+01Ch ; Keyboard buffer tail in BIOS data area -%define KB_START WORD esi+080h ; Start of keyboard buffer in BIOS data area -%define KB_END WORD esi+082h ; End of keyboard buffer in BIOS data area -else -KB_HEAD EQU WORD esi+01Ah ; Keyboard buffer head in BIOS data area -KB_TAIL EQU WORD esi+01Ch ; Keyboard buffer tail in BIOS data area -KB_START EQU WORD esi+080h ; Start of keyboard buffer in BIOS data area -KB_END EQU WORD esi+082h ; End of keyboard buffer in BIOS data area -endif - - cpublic _EVT_dataEnd - -enddataseg _event - -begcodeseg _event ; Start of code segment - - cpublic _EVT_codeStart - -;---------------------------------------------------------------------------- -; int _EVT_getKeyCode(void) -;---------------------------------------------------------------------------- -; Returns the key code for the next available key by extracting it from -; the BIOS keyboard buffer. -;---------------------------------------------------------------------------- -cprocstart _EVT_getKeyCode - - enter_c - - mov esi,[_EVT_biosPtr] - xor ebx,ebx - xor eax,eax - mov bx,[KB_HEAD] - cmp bx,[KB_TAIL] - jz @@Done - xor eax,eax - mov ax,[esi+ebx] ; EAX := character from keyboard buffer - inc _bx - inc _bx - cmp bx,[KB_END] ; Hit the end of the keyboard buffer? - jl @@1 - mov bx,[KB_START] -@@1: mov [KB_HEAD],bx ; Update keyboard buffer head pointer - -@@Done: leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; int _EVT_disableInt(void); -;---------------------------------------------------------------------------- -; Return processor interrupt status and disable interrupts. -;---------------------------------------------------------------------------- -cprocstart _EVT_disableInt - - pushf ; Put flag word on stack - cli ; Disable interrupts! - pop eax ; deposit flag word in return register - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _EVT_restoreInt(int ps); -;---------------------------------------------------------------------------- -; Restore processor interrupt status. -;---------------------------------------------------------------------------- -cprocstart _EVT_restoreInt - - ARG ps:UINT - - push ebp - mov ebp,esp ; Set up stack frame - push [DWORD ps] - popf ; Restore processor status (and interrupts) - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; int EVT_rdinx(int port,int index) -;---------------------------------------------------------------------------- -; Reads an indexed register value from an I/O port. -;---------------------------------------------------------------------------- -cprocstart EVT_rdinx - - ARG port:UINT, index:UINT - - push ebp - mov ebp,esp - mov edx,[port] - mov al,[BYTE index] - out dx,al - inc dx - in al,dx - movzx eax,al - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void EVT_wrinx(int port,int index,int value) -;---------------------------------------------------------------------------- -; Writes an indexed register value to an I/O port. -;---------------------------------------------------------------------------- -cprocstart EVT_wrinx - - ARG port:UINT, index:UINT, value:UINT - - push ebp - mov ebp,esp - mov edx,[port] - mov al,[BYTE index] - mov ah,[BYTE value] - out dx,ax - pop ebp - ret - -cprocend - - cpublic _EVT_codeEnd - -endcodeseg _event - -endif - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm deleted file mode 100644 index 068eea6..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm +++ /dev/null @@ -1,58 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: NASM or TASM Assembler -;* Environment: smx 32 bit intel CPU -;* -;* Description: SMX does not support 486's, so this module is not necessary. -;* -;* All registers and all flags are preserved by all routines, except -;* interrupts which are always turned on -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" - -header _lztimer - -begdataseg _lztimer - -enddataseg _lztimer - -begcodeseg _lztimer ; Start of code segment - -cprocstart LZ_disable - cli - ret -cprocend - -cprocstart LZ_enable - sti - ret -cprocend - -endcodeseg _lztimer - - END diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm deleted file mode 100644 index 1c7cb21..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm +++ /dev/null @@ -1,448 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: 32-bit SMX embedded systems development -;* -;* Description: Low level assembly support for the PM library specific to -;* SMX. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _pm ; Set up memory model - -begdataseg _pm - - cextern _PM_savedDS,USHORT - -intel_id db "GenuineIntel" ; Intel vendor ID - -enddataseg _pm - -begcodeseg _pm ; Start of code segment - -;---------------------------------------------------------------------------- -; void PM_segread(PMSREGS *sregs) -;---------------------------------------------------------------------------- -; Read the current value of all segment registers -;---------------------------------------------------------------------------- -cprocstartdll16 PM_segread - - ARG sregs:DPTR - - enter_c - - mov ax,es - _les _si,[sregs] - mov [_ES _si],ax - mov [_ES _si+2],cs - mov [_ES _si+4],ss - mov [_ES _si+6],ds - mov [_ES _si+8],fs - mov [_ES _si+10],gs - - leave_c - ret - -cprocend - -; Create a table of the 256 different interrupt calls that we can jump -; into - -ifdef USE_NASM - -%assign intno 0 - -intTable: -%rep 256 - db 0CDh - db intno -%assign intno intno + 1 - ret - nop -%endrep - -else - -intno = 0 - -intTable: - REPT 256 - db 0CDh - db intno -intno = intno + 1 - ret - nop - ENDM - -endif - -;---------------------------------------------------------------------------- -; _PM_genInt - Generate the appropriate interrupt -;---------------------------------------------------------------------------- -cprocnear _PM_genInt - - push _ax ; Save _ax - push _bx ; Save _bx - mov ebx,[UINT esp+12] ; EBX := interrupt number - mov _ax,offset intTable ; Point to interrupt generation table - shl _bx,2 ; _BX := index into table - add _ax,_bx ; _AX := pointer to interrupt code - xchg eax,[esp+4] ; Restore eax, and set for int - pop _bx ; restore _bx - ret - -cprocend - -;---------------------------------------------------------------------------- -; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) -;---------------------------------------------------------------------------- -; Issues a software interrupt in protected mode. This routine has been -; written to allow user programs to load CS and DS with different values -; other than the default. -;---------------------------------------------------------------------------- -cprocstartdll16 PM_int386x - - ARG intno:UINT, inptr:DPTR, outptr:DPTR, sregs:DPTR - - LOCAL flags:UINT, sv_ds:UINT, sv_esi:ULONG = LocalSize - - enter_c - push ds - push es ; Save segment registers - push fs - push gs - - _lds _si,[sregs] ; DS:_SI -> Load segment registers - mov es,[_si] - mov bx,[_si+6] - mov [sv_ds],_bx ; Save value of user DS on stack - mov fs,[_si+8] - mov gs,[_si+10] - - _lds _si,[inptr] ; Load CPU registers - mov eax,[_si] - mov ebx,[_si+4] - mov ecx,[_si+8] - mov edx,[_si+12] - mov edi,[_si+20] - mov esi,[_si+16] - - push ds ; Save value of DS - push _bp ; Some interrupts trash this! - clc ; Generate the interrupt - push [UINT intno] - mov ds,[WORD sv_ds] ; Set value of user's DS selector - call _PM_genInt - pop _bp ; Pop intno from stack (flags unchanged) - pop _bp ; Restore value of stack frame pointer - pop ds ; Restore value of DS - - pushf ; Save flags for later - pop [UINT flags] - push esi ; Save ESI for later - pop [DWORD sv_esi] - push ds ; Save DS for later - pop [UINT sv_ds] - - _lds _si,[outptr] ; Save CPU registers - mov [_si],eax - mov [_si+4],ebx - mov [_si+8],ecx - mov [_si+12],edx - push [DWORD sv_esi] - pop [DWORD _si+16] - mov [_si+20],edi - - mov _bx,[flags] ; Return flags - and ebx,1h ; Isolate carry flag - mov [_si+24],ebx ; Save carry flag status - - _lds _si,[sregs] ; Save segment registers - mov [_si],es - mov _bx,[sv_ds] - mov [_si+6],bx ; Get returned DS from stack - mov [_si+8],fs - mov [_si+10],gs - - pop gs ; Restore segment registers - pop fs - pop es - pop ds - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_saveDS(void) -;---------------------------------------------------------------------------- -; Save the value of DS into a section of the code segment, so that we can -; quickly load this value at a later date in the PM_loadDS() routine from -; inside interrupt handlers etc. The method to do this is different -; depending on the DOS extender being used. -;---------------------------------------------------------------------------- -cprocstartdll16 PM_saveDS - - mov [_PM_savedDS],ds ; Store away in data segment - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_loadDS(void) -;---------------------------------------------------------------------------- -; Routine to load the DS register with the default value for the current -; DOS extender. Only the DS register is loaded, not the ES register, so -; if you wish to call C code, you will need to also load the ES register -; in 32 bit protected mode. -;---------------------------------------------------------------------------- -cprocstartdll16 PM_loadDS - - mov ds,[cs:_PM_savedDS] ; We can access the proper DS through CS - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_setBankA(int bank) -;---------------------------------------------------------------------------- -cprocstart PM_setBankA - - ARG bank:UINT - - push ebp - mov ebp,esp - push ebx - mov _bx,0 - mov _ax,4F05h - mov _dx,[bank] - int 10h - pop ebx - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_setBankAB(int bank) -;---------------------------------------------------------------------------- -cprocstart PM_setBankAB - - ARG bank:UINT - - push ebp - mov ebp,esp - push ebx - mov _bx,0 - mov _ax,4F05h - mov _dx,[bank] - int 10h - mov _bx,1 - mov _ax,4F05h - mov _dx,[bank] - int 10h - pop ebx - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_setCRTStart(int x,int y,int waitVRT) -;---------------------------------------------------------------------------- -cprocstart PM_setCRTStart - - ARG x:UINT, y:UINT, waitVRT:UINT - - push ebp - mov ebp,esp - push ebx - mov _bx,[waitVRT] - mov _cx,[x] - mov _dx,[y] - mov _ax,4F07h - int 10h - pop ebx - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; int _PM_inp(int port) -;---------------------------------------------------------------------------- -; Reads a byte from the specified port -;---------------------------------------------------------------------------- -cprocstart _PM_inp - - ARG port:UINT - - push _bp - mov _bp,_sp - xor _ax,_ax - mov _dx,[port] - in al,dx - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _PM_outp(int port,int value) -;---------------------------------------------------------------------------- -; Write a byte to the specified port. -;---------------------------------------------------------------------------- -cprocstart _PM_outp - - ARG port:UINT, value:UINT - - push _bp - mov _bp,_sp - mov _dx,[port] - mov _ax,[value] - out dx,al - pop _bp - ret - -cprocend - -; Macro to delay briefly to ensure that enough time has elapsed between -; successive I/O accesses so that the device being accessed can respond -; to both accesses even on a very fast PC. - -ifdef USE_NASM -%macro DELAY 0 - jmp short $+2 - jmp short $+2 - jmp short $+2 -%endmacro -%macro IODELAYN 1 -%rep %1 - DELAY -%endrep -%endmacro -else -macro DELAY - jmp short $+2 - jmp short $+2 - jmp short $+2 -endm -macro IODELAYN N - rept N - DELAY - endm -endm -endif - -;---------------------------------------------------------------------------- -; uchar _PM_readCMOS(int index) -;---------------------------------------------------------------------------- -; Read the value of a specific CMOS register. We do this with both -; normal interrupts and NMI disabled. -;---------------------------------------------------------------------------- -cprocstart _PM_readCMOS - - ARG index:UINT - - push _bp - mov _bp,_sp - pushfd - mov al,[BYTE index] - or al,80h ; Add disable NMI flag - cli - out 70h,al - IODELAYN 5 - in al,71h - mov ah,al - xor al,al - IODELAYN 5 - out 70h,al ; Re-enable NMI - sti - mov al,ah ; Return value in AL - popfd - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _PM_writeCMOS(int index,uchar value) -;---------------------------------------------------------------------------- -; Read the value of a specific CMOS register. We do this with both -; normal interrupts and NMI disabled. -;---------------------------------------------------------------------------- -cprocstart _PM_writeCMOS - - ARG index:UINT, value:UCHAR - - push _bp - mov _bp,_sp - pushfd - mov al,[BYTE index] - or al,80h ; Add disable NMI flag - cli - out 70h,al - IODELAYN 5 - mov al,[value] - out 71h,al - xor al,al - IODELAYN 5 - out 70h,al ; Re-enable NMI - sti - popfd - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; _PM_getPDB - Return the Page Table Directory Base address -;---------------------------------------------------------------------------- -cprocstart _PM_getPDB - - mov eax,cr3 - and eax,0FFFFF000h - ret - -cprocend - -;---------------------------------------------------------------------------- -; _PM_flushTLB - Flush the Translation Lookaside buffer -;---------------------------------------------------------------------------- -cprocstart PM_flushTLB - - wbinvd ; Flush the CPU cache - mov eax,cr3 - mov cr3,eax ; Flush the TLB - ret - -cprocend - -endcodeseg _pm - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm deleted file mode 100644 index 8352ce3..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm +++ /dev/null @@ -1,933 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: 32-bit SMX embedded systems development -;* -;* Description: Low level assembly support for the PM library specific to -;* SMX interrupt handling. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _pmsmx ; Set up memory model - -; Define the size of our local stacks. For real mode code they cant be -; that big, but for 32 bit protected mode code we can make them nice and -; large so that complex C functions can be used. - -MOUSE_STACK EQU 4096 -TIMER_STACK EQU 4096 -KEY_STACK EQU 1024 -INT10_STACK EQU 1024 - -ifdef USE_NASM - -; Macro to load DS and ES registers with correct value. - -%imacro LOAD_DS 0 - mov ds,[cs:_PM_savedDS] - mov es,[cs:_PM_savedDS] -%endmacro - -; Note that interrupts we disable interrupts during the following stack -; %imacro for correct operation, but we do not enable them again. Normally -; these %imacros are used within interrupt handlers so interrupts should -; already be off. We turn them back on explicitly later if the user code -; needs them to be back on. - -; Macro to switch to a new local stack. - -%imacro NEWSTK 1 - cli - mov [seg_%1],ss - mov [ptr_%1],_sp - mov [TempSeg],ds - mov ss,[TempSeg] - mov _sp,offset %1 -%endmacro - -; %imacro to switch back to the old stack. - -%imacro RESTSTK 1 - cli - mov ss,[seg_%1] - mov _sp,[ptr_%1] -%endmacro - -; %imacro to swap the current stack with the one saved away. - -%imacro SWAPSTK 1 - cli - mov ax,ss - xchg ax,[seg_%1] - mov ss,ax - xchg _sp,[ptr_%1] -%endmacro - -else - -; Macro to load DS and ES registers with correct value. - -MACRO LOAD_DS - mov ds,[cs:_PM_savedDS] - mov es,[cs:_PM_savedDS] -ENDM - -; Note that interrupts we disable interrupts during the following stack -; macro for correct operation, but we do not enable them again. Normally -; these macros are used within interrupt handlers so interrupts should -; already be off. We turn them back on explicitly later if the user code -; needs them to be back on. - -; Macro to switch to a new local stack. - -MACRO NEWSTK stkname - cli - mov [seg_&stkname&],ss - mov [ptr_&stkname&],_sp - mov [TempSeg],ds - mov ss,[TempSeg] - mov _sp,offset stkname -ENDM - -; Macro to switch back to the old stack. - -MACRO RESTSTK stkname - cli - mov ss,[seg_&stkname&] - mov _sp,[ptr_&stkname&] -ENDM - -; Macro to swap the current stack with the one saved away. - -MACRO SWAPSTK stkname - cli - mov ax,ss - xchg ax,[seg_&stkname&] - mov ss,ax - xchg _sp,[ptr_&stkname&] -ENDM - -endif - -begdataseg _pmsmx - - cextern _PM_savedDS,USHORT - cextern _PM_critHandler,CPTR - cextern _PM_breakHandler,CPTR - cextern _PM_timerHandler,CPTR - cextern _PM_rtcHandler,CPTR - cextern _PM_keyHandler,CPTR - cextern _PM_key15Handler,CPTR - cextern _PM_mouseHandler,CPTR - cextern _PM_int10Handler,CPTR - - cextern _PM_ctrlCPtr,DPTR - cextern _PM_ctrlBPtr,DPTR - cextern _PM_critPtr,DPTR - - cextern _PM_prevTimer,FCPTR - cextern _PM_prevRTC,FCPTR - cextern _PM_prevKey,FCPTR - cextern _PM_prevKey15,FCPTR - cextern _PM_prevBreak,FCPTR - cextern _PM_prevCtrlC,FCPTR - cextern _PM_prevCritical,FCPTR - cextern _PM_prevRealTimer,ULONG - cextern _PM_prevRealRTC,ULONG - cextern _PM_prevRealKey,ULONG - cextern _PM_prevRealKey15,ULONG - cextern _PM_prevRealInt10,ULONG - -cpublic _PM_pmsmxDataStart - -; Allocate space for all of the local stacks that we need. These stacks -; are not very large, but should be large enough for most purposes -; (generally you want to handle these interrupts quickly, simply storing -; the information for later and then returning). If you need bigger -; stacks then change the appropriate value in here. - - ALIGN 4 - dclb MOUSE_STACK ; Space for local stack (small) -MsStack: ; Stack starts at end! -ptr_MsStack DUINT 0 ; Place to store old stack offset -seg_MsStack dw 0 ; Place to store old stack segment - - ALIGN 4 - dclb INT10_STACK ; Space for local stack (small) -Int10Stack: ; Stack starts at end! -ptr_Int10Stack DUINT 0 ; Place to store old stack offset -seg_Int10Stack dw 0 ; Place to store old stack segment - - ALIGN 4 - dclb TIMER_STACK ; Space for local stack (small) -TmStack: ; Stack starts at end! -ptr_TmStack DUINT 0 ; Place to store old stack offset -seg_TmStack dw 0 ; Place to store old stack segment - - ALIGN 4 - dclb TIMER_STACK ; Space for local stack (small) -RtcStack: ; Stack starts at end! -ptr_RtcStack DUINT 0 ; Place to store old stack offset -seg_RtcStack dw 0 ; Place to store old stack segment -RtcInside dw 0 ; Are we still handling current interrupt - - ALIGN 4 - dclb KEY_STACK ; Space for local stack (small) -KyStack: ; Stack starts at end! -ptr_KyStack DUINT 0 ; Place to store old stack offset -seg_KyStack dw 0 ; Place to store old stack segment -KyInside dw 0 ; Are we still handling current interrupt - - ALIGN 4 - dclb KEY_STACK ; Space for local stack (small) -Ky15Stack: ; Stack starts at end! -ptr_Ky15Stack DUINT 0 ; Place to store old stack offset -seg_Ky15Stack dw 0 ; Place to store old stack segment - -TempSeg dw 0 ; Place to store stack segment - -cpublic _PM_pmsmxDataEnd - -enddataseg _pmsmx - -begcodeseg _pmsmx ; Start of code segment - -cpublic _PM_pmsmxCodeStart - -;---------------------------------------------------------------------------- -; PM_mouseISR - Mouse interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Interrupt subroutine called by the mouse driver upon interrupts, to -; dispatch control to high level C based subroutines. Interrupts are on -; when we call the user code. -; -; It is _extremely_ important to save the state of the extended registers -; as these may well be trashed by the routines called from here and not -; restored correctly by the mouse interface module. -; -; NOTE: This routine switches to a local stack before calling any C code, -; and hence is _not_ re-entrant. For mouse handlers this is not a -; problem, as the mouse driver arbitrates calls to the user mouse -; handler for us. -; -; Entry: AX - Condition mask giving reason for call -; BX - Mouse button state -; CX - Horizontal cursor coordinate -; DX - Vertical cursor coordinate -; SI - Horizontal mickey value -; DI - Vertical mickey value -; -;---------------------------------------------------------------------------- -cprocfar _PM_mouseISR - - push ds ; Save value of DS - push es - pushad ; Save _all_ extended registers - cld ; Clear direction flag - - LOAD_DS ; Load DS register - NEWSTK MsStack ; Switch to local stack - -; Call the installed high level C code routine - - clrhi dx ; Clear out high order values - clrhi cx - clrhi bx - clrhi ax - sgnhi si - sgnhi di - - push _di - push _si - push _dx - push _cx - push _bx - push _ax - sti ; Enable interrupts - call [CPTR _PM_mouseHandler] - _add sp,12,24 - - RESTSTK MsStack ; Restore previous stack - - popad ; Restore all extended registers - pop es - pop ds - ret ; We are done!! - -cprocend - -;---------------------------------------------------------------------------- -; PM_timerISR - Timer interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Hardware interrupt handler for the timer interrupt, to dispatch control -; to high level C based subroutines. We save the state of all registers -; in this routine, and switch to a local stack. Interrupts are *off* -; when we call the user code. -; -; NOTE: This routine switches to a local stack before calling any C code, -; and hence is _not_ re-entrant. Make sure your C code executes as -; quickly as possible, since a timer overrun will simply hang the -; system. -;---------------------------------------------------------------------------- -cprocfar _PM_timerISR - - push ds ; Save value of DS - push es - pushad ; Save _all_ extended registers - cld ; Clear direction flag - - LOAD_DS ; Load DS register - - NEWSTK TmStack ; Switch to local stack - call [CPTR _PM_timerHandler] - RESTSTK TmStack ; Restore previous stack - - popad ; Restore all extended registers - pop es - pop ds - iret ; Return from interrupt - -cprocend - -;---------------------------------------------------------------------------- -; PM_chainPrevTimer - Chain to previous timer interrupt and return -;---------------------------------------------------------------------------- -; Chains to the previous timer interrupt routine and returns control -; back to the high level interrupt handler. -;---------------------------------------------------------------------------- -cprocstart PM_chainPrevTimer - -ifdef TNT - push eax - push ebx - push ecx - pushfd ; Push flags on stack to simulate interrupt - mov ax,250Eh ; Call real mode procedure function - mov ebx,[_PM_prevRealTimer] - mov ecx,1 ; Copy real mode flags to real mode stack - int 21h ; Call the real mode code - popfd - pop ecx - pop ebx - pop eax - ret -else - SWAPSTK TmStack ; Swap back to previous stack - pushf ; Save state of interrupt flag - pushf ; Push flags on stack to simulate interrupt -ifdef USE_NASM - call far dword [_PM_prevTimer] -else - call [_PM_prevTimer] -endif - popf ; Restore state of interrupt flag - SWAPSTK TmStack ; Swap back to C stack again - ret -endif - -cprocend - -; Macro to delay briefly to ensure that enough time has elapsed between -; successive I/O accesses so that the device being accessed can respond -; to both accesses even on a very fast PC. - -ifdef USE_NASM -%macro DELAY 0 - jmp short $+2 - jmp short $+2 - jmp short $+2 -%endmacro -%macro IODELAYN 1 -%rep %1 - DELAY -%endrep -%endmacro -else -macro DELAY - jmp short $+2 - jmp short $+2 - jmp short $+2 -endm -macro IODELAYN N - rept N - DELAY - endm -endm -endif - -;---------------------------------------------------------------------------- -; PM_rtcISR - Real time clock interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Hardware interrupt handler for the timer interrupt, to dispatch control -; to high level C based subroutines. We save the state of all registers -; in this routine, and switch to a local stack. Interrupts are *off* -; when we call the user code. -; -; NOTE: This routine switches to a local stack before calling any C code, -; and hence is _not_ re-entrant. Make sure your C code executes as -; quickly as possible, since a timer overrun will simply hang the -; system. -;---------------------------------------------------------------------------- -cprocfar _PM_rtcISR - - push ds ; Save value of DS - push es - pushad ; Save _all_ extended registers - cld ; Clear direction flag - -; Clear priority interrupt controller and re-enable interrupts so we -; dont lock things up for long. - - mov al,20h - out 0A0h,al - out 020h,al - -; Clear real-time clock timeout - - in al,70h ; Read CMOS index register - push _ax ; and save for later - IODELAYN 3 - mov al,0Ch - out 70h,al - IODELAYN 5 - in al,71h - -; Call the C interrupt handler function - - LOAD_DS ; Load DS register - cmp [BYTE RtcInside],1 ; Check for mutual exclusion - je @@Exit - mov [BYTE RtcInside],1 - sti ; Re-enable interrupts - NEWSTK RtcStack ; Switch to local stack - call [CPTR _PM_rtcHandler] - RESTSTK RtcStack ; Restore previous stack - mov [BYTE RtcInside],0 - -@@Exit: pop _ax - out 70h,al ; Restore CMOS index register - popad ; Restore all extended registers - pop es - pop ds - iret ; Return from interrupt - -cprocend - -;---------------------------------------------------------------------------- -; PM_keyISR - keyboard interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Hardware interrupt handler for the keyboard interrupt, to dispatch control -; to high level C based subroutines. We save the state of all registers -; in this routine, and switch to a local stack. Interrupts are *off* -; when we call the user code. -; -; NOTE: This routine switches to a local stack before calling any C code, -; and hence is _not_ re-entrant. However we ensure within this routine -; mutual exclusion to the keyboard handling routine. -;---------------------------------------------------------------------------- -cprocfar _PM_keyISR - - push ds ; Save value of DS - push es - pushad ; Save _all_ extended registers - cld ; Clear direction flag - - LOAD_DS ; Load DS register - - cmp [BYTE KyInside],1 ; Check for mutual exclusion - je @@Reissued - - mov [BYTE KyInside],1 - NEWSTK KyStack ; Switch to local stack - call [CPTR _PM_keyHandler] ; Call C code - RESTSTK KyStack ; Restore previous stack - mov [BYTE KyInside],0 - -@@Exit: popad ; Restore all extended registers - pop es - pop ds - iret ; Return from interrupt - -; When the BIOS keyboard handler needs to change the SHIFT status lights -; on the keyboard, in the process of doing this the keyboard controller -; re-issues another interrupt, while the current handler is still executing. -; If we recieve another interrupt while still handling the current one, -; then simply chain directly to the previous handler. -; -; Note that for most DOS extenders, the real mode interrupt handler that we -; install takes care of this for us. - -@@Reissued: -ifdef TNT - push eax - push ebx - push ecx - pushfd ; Push flags on stack to simulate interrupt - mov ax,250Eh ; Call real mode procedure function - mov ebx,[_PM_prevRealKey] - mov ecx,1 ; Copy real mode flags to real mode stack - int 21h ; Call the real mode code - popfd - pop ecx - pop ebx - pop eax -else - pushf -ifdef USE_NASM - call far dword [_PM_prevKey] -else - call [_PM_prevKey] -endif -endif - jmp @@Exit - -cprocend - -;---------------------------------------------------------------------------- -; PM_chainPrevkey - Chain to previous key interrupt and return -;---------------------------------------------------------------------------- -; Chains to the previous key interrupt routine and returns control -; back to the high level interrupt handler. -;---------------------------------------------------------------------------- -cprocstart PM_chainPrevKey - -ifdef TNT - push eax - push ebx - push ecx - pushfd ; Push flags on stack to simulate interrupt - mov ax,250Eh ; Call real mode procedure function - mov ebx,[_PM_prevRealKey] - mov ecx,1 ; Copy real mode flags to real mode stack - int 21h ; Call the real mode code - popfd - pop ecx - pop ebx - pop eax - ret -else - -; YIKES! For some strange reason, when execution returns from the -; previous keyboard handler, interrupts are re-enabled!! Since we expect -; interrupts to remain off during the duration of our handler, this can -; cause havoc. However our stack macros always turn off interrupts, so they -; will be off when we exit this routine. Obviously there is a tiny weeny -; window when interrupts will be enabled, but there is nothing we can -; do about this. - - SWAPSTK KyStack ; Swap back to previous stack - pushf ; Push flags on stack to simulate interrupt -ifdef USE_NASM - call far dword [_PM_prevKey] -else - call [_PM_prevKey] -endif - SWAPSTK KyStack ; Swap back to C stack again - ret -endif - -cprocend - -;---------------------------------------------------------------------------- -; PM_key15ISR - Int 15h keyboard interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; This routine gets called if we have been called to handle the Int 15h -; keyboard interrupt callout from real mode. -; -; Entry: AX - Hardware scan code to process -; Exit: AX - Hardware scan code to process (0 to ignore) -;---------------------------------------------------------------------------- -cprocfar _PM_key15ISR - - push ds - push es - LOAD_DS - cmp ah,4Fh - jnz @@NotOurs ; Quit if not keyboard callout - - pushad - cld ; Clear direction flag - xor ah,ah ; AX := scan code - NEWSTK Ky15Stack ; Switch to local stack - push _ax - call [CPTR _PM_key15Handler] ; Call C code - _add sp,2,4 - RESTSTK Ky15Stack ; Restore previous stack - test ax,ax - jz @@1 - stc ; Set carry to process as normal - jmp @@2 -@@1: clc ; Clear carry to ignore scan code -@@2: popad - jmp @@Exit ; We are done - -@@NotOurs: -ifdef TNT - push eax - push ebx - push ecx - pushfd ; Push flags on stack to simulate interrupt - mov ax,250Eh ; Call real mode procedure function - mov ebx,[_PM_prevRealKey15] - mov ecx,1 ; Copy real mode flags to real mode stack - int 21h ; Call the real mode code - popfd - pop ecx - pop ebx - pop eax -else - pushf -ifdef USE_NASM - call far dword [_PM_prevKey15] -else - call [_PM_prevKey15] -endif -endif -@@Exit: pop es - pop ds - retf 4 - -cprocend - -;---------------------------------------------------------------------------- -; PM_breakISR - Control Break interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Hardware interrupt handler for the Ctrl-Break interrupt. We simply set -; the Ctrl-Break flag to a 1 and leave (note that this is accessed through -; a far pointer, as it may well be located in conventional memory). -;---------------------------------------------------------------------------- -cprocfar _PM_breakISR - - sti - push ds ; Save value of DS - push es - push _bx - - LOAD_DS ; Load DS register - mov ebx,[_PM_ctrlBPtr] - mov [UINT _ES _bx],1 - -; Run alternate break handler code if installed - - cmp [CPTR _PM_breakHandler],0 - je @@Exit - - pushad - mov _ax,1 - push _ax - call [CPTR _PM_breakHandler] ; Call C code - pop _ax - popad - -@@Exit: pop _bx - pop es - pop ds - iret ; Return from interrupt - -cprocend - -;---------------------------------------------------------------------------- -; int PM_ctrlBreakHit(int clearFlag) -;---------------------------------------------------------------------------- -; Returns the current state of the Ctrl-Break flag and possibly clears it. -;---------------------------------------------------------------------------- -cprocstart PM_ctrlBreakHit - - ARG clearFlag:UINT - - enter_c - pushf ; Save interrupt status - push es - mov ebx,[_PM_ctrlBPtr] - cli ; No interrupts thanks! - mov _ax,[_ES _bx] - test [BYTE clearFlag],1 - jz @@Done - mov [UINT _ES _bx],0 - -@@Done: pop es - popf ; Restore interrupt status - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; PM_ctrlCISR - Control Break interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Hardware interrupt handler for the Ctrl-C interrupt. We simply set -; the Ctrl-C flag to a 1 and leave (note that this is accessed through -; a far pointer, as it may well be located in conventional memory). -;---------------------------------------------------------------------------- -cprocfar _PM_ctrlCISR - - sti - push ds ; Save value of DS - push es - push _bx - - LOAD_DS ; Load DS register - mov ebx,[_PM_ctrlCPtr] - mov [UINT _ES _bx],1 - -; Run alternate break handler code if installed - - cmp [CPTR _PM_breakHandler],0 - je @@Exit - - pushad - mov _ax,0 - push _ax - call [CPTR _PM_breakHandler] ; Call C code - pop _ax - popad - -@@Exit: pop _bx - pop es - pop ds - iret ; Return from interrupt - iretd - -cprocend - -;---------------------------------------------------------------------------- -; int PM_ctrlCHit(int clearFlag) -;---------------------------------------------------------------------------- -; Returns the current state of the Ctrl-C flag and possibly clears it. -;---------------------------------------------------------------------------- -cprocstart PM_ctrlCHit - - ARG clearFlag:UINT - - enter_c - pushf ; Save interrupt status - push es - mov ebx,[_PM_ctrlCPtr] - cli ; No interrupts thanks! - mov _ax,[_ES _bx] - test [BYTE clearFlag],1 - jz @@Done - mov [UINT _ES _bx],0 - -@@Done: - pop es - popf ; Restore interrupt status - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; PM_criticalISR - Control Error handler interrupt subroutine dispatcher -;---------------------------------------------------------------------------- -; Interrupt handler for the MSDOS Critical Error interrupt, to dispatch -; control to high level C based subroutines. We save the state of all -; registers in this routine, and switch to a local stack. We also pass -; the values of the AX and DI registers to the as pointers, so that the -; values can be modified before returning to MSDOS. -;---------------------------------------------------------------------------- -cprocfar _PM_criticalISR - - sti - push ds ; Save value of DS - push es - push _bx ; Save register values changed - cld ; Clear direction flag - - LOAD_DS ; Load DS register - mov ebx,[_PM_critPtr] - mov [_ES _bx],ax - mov [_ES _bx+2],di - -; Run alternate critical handler code if installed - - cmp [CPTR _PM_critHandler],0 - je @@NoAltHandler - - pushad - push _di - push _ax - call [CPTR _PM_critHandler] ; Call C code - _add sp,4,8 - popad - - pop _bx - pop es - pop ds - iret ; Return from interrupt - -@@NoAltHandler: - mov ax,3 ; Tell MSDOS to fail the operation - pop _bx - pop es - pop ds - iret ; Return from interrupt - -cprocend - -;---------------------------------------------------------------------------- -; int PM_criticalError(int *axVal,int *diVal,int clearFlag) -;---------------------------------------------------------------------------- -; Returns the current state of the critical error flags, and the values that -; MSDOS passed in the AX and DI registers to our handler. -;---------------------------------------------------------------------------- -cprocstart PM_criticalError - - ARG axVal:DPTR, diVal:DPTR, clearFlag:UINT - - enter_c - pushf ; Save interrupt status - push es - mov ebx,[_PM_critPtr] - cli ; No interrupts thanks! - xor _ax,_ax - xor _di,_di - mov ax,[_ES _bx] - mov di,[_ES _bx+2] - test [BYTE clearFlag],1 - jz @@NoClear - mov [ULONG _ES _bx],0 -@@NoClear: - _les _bx,[axVal] - mov [_ES _bx],_ax - _les _bx,[diVal] - mov [_ES _bx],_di - pop es - popf ; Restore interrupt status - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_setMouseHandler(int mask, PM_mouseHandler mh) -;---------------------------------------------------------------------------- -cprocstart _PM_setMouseHandler - - ARG mouseMask:UINT - - enter_c - push es - - mov ax,0Ch ; AX := Function 12 - install interrupt sub - mov _cx,[mouseMask] ; CX := mouse mask - mov _dx,offset _PM_mouseISR - push cs - pop es ; ES:_DX -> mouse handler - int 33h ; Call mouse driver - - pop es - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_mousePMCB(void) -;---------------------------------------------------------------------------- -; Mouse realmode callback routine. Upon entry to this routine, we recieve -; the following from the DPMI server: -; -; Entry: DS:_SI -> Real mode stack at time of call -; ES:_DI -> Real mode register data structure -; SS:_SP -> Locked protected mode stack to use -;---------------------------------------------------------------------------- -cprocfar _PM_mousePMCB - - pushad - mov eax,[es:_di+1Ch] ; Load register values from real mode - mov ebx,[es:_di+10h] - mov ecx,[es:_di+18h] - mov edx,[es:_di+14h] - mov esi,[es:_di+04h] - mov edi,[es:_di] - call _PM_mouseISR ; Call the mouse handler - popad - - mov ax,[ds:_si] - mov [es:_di+2Ah],ax ; Plug in return IP address - mov ax,[ds:_si+2] - mov [es:_di+2Ch],ax ; Plug in return CS value - add [WORD es:_di+2Eh],4 ; Remove return address from stack - iret ; Go back to real mode! - -cprocend - -;---------------------------------------------------------------------------- -; void PM_int10PMCB(void) -;---------------------------------------------------------------------------- -; int10 realmode callback routine. Upon entry to this routine, we recieve -; the following from the DPMI server: -; -; Entry: DS:ESI -> Real mode stack at time of call -; ES:EDI -> Real mode register data structure -; SS:ESP -> Locked protected mode stack to use -;---------------------------------------------------------------------------- -cprocfar _PM_int10PMCB - - pushad - push ds - push es - push fs - - pushfd - pop eax - mov [es:edi+20h],ax ; Save return flag status - mov ax,[ds:esi] - mov [es:edi+2Ah],ax ; Plug in return IP address - mov ax,[ds:esi+2] - mov [es:edi+2Ch],ax ; Plug in return CS value - add [WORD es:edi+2Eh],4 ; Remove return address from stack - -; Call the install int10 handler in protected mode. This function gets called -; with DS set to the current data selector, and ES:EDI pointing the the -; real mode DPMI register structure at the time of the interrupt. The -; handle must be written in assembler to be able to extract the real mode -; register values from the structure - - push es - pop fs ; FS:EDI -> real mode registers - LOAD_DS - NEWSTK Int10Stack ; Switch to local stack - - call [_PM_int10Handler] - - RESTSTK Int10Stack ; Restore previous stack - pop fs - pop es - pop ds - popad - iret ; Go back to real mode! - -cprocend - -cpublic _PM_pmsmxCodeEnd - -endcodeseg _pmsmx - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm deleted file mode 100644 index 34985a9..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm +++ /dev/null @@ -1,652 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Based on original code Copyright 1994 Otto Chrons -;* -;* Language: 80386 Assembler, TASM 4.0 or later -;* Environment: IBM PC 32 bit protected mode -;* -;* Description: Low level page fault handler for virtual linear framebuffers. -;* -;**************************************************************************** - - IDEAL - JUMPS - -include "scitech.mac" ; Memory model macros - -header _vflat ; Set up memory model - -VFLAT_START EQU 0F0000000h -VFLAT_END EQU 0F03FFFFFh -PAGE_PRESENT EQU 1 -PAGE_NOTPRESENT EQU 0 -PAGE_READ EQU 0 -PAGE_WRITE EQU 2 - -ifdef DOS4GW - -;---------------------------------------------------------------------------- -; DOS4G/W flat linear framebuffer emulation. -;---------------------------------------------------------------------------- - -begdataseg _vflat - -; Near pointers to the page directory base and our page tables. All of -; this memory is always located in the first Mb of DOS memory. - -PDBR dd 0 ; Page directory base register (CR3) -accessPageAddr dd 0 -accessPageTable dd 0 - -; CauseWay page directory & 1st page table linear addresses. - -CauseWayDIRLinear dd 0 -CauseWay1stLinear dd 0 - -; Place to store a copy of the original Page Table Directory before we -; intialised our virtual buffer code. - -pageDirectory: resd 1024 ; Saved page table directory - -ValidCS dw 0 ; Valid CS for page faults -Ring0CS dw 0 ; Our ring 0 code selector -LastPage dd 0 ; Last page we mapped in -BankFuncBuf: resb 101 ; Place to store bank switch code -BankFuncPtr dd offset BankFuncBuf - -INT14Gate: -INT14Offset dd 0 ; eip of original vector -INT14Selector dw 0 ; cs of original vector - - cextern _PM_savedDS,USHORT - cextern VF_haveCauseWay,BOOL - -enddataseg _vflat - -begcodeseg _vflat ; Start of code segment - - cextern VF_malloc,FPTR - -;---------------------------------------------------------------------------- -; PF_handler64k - Page fault handler for 64k banks -;---------------------------------------------------------------------------- -; The handler below is a 32 bit ring 0 page fault handler. It receives -; control immediately after any page fault or after an IRQ6 (hardware -; interrupt). This provides the fastest possible handling of page faults -; since it jump directly here. If this is a page fault, the number -; immediately on the stack will be an error code, at offset 4 will be -; the eip of the faulting instruction, at offset 8 will be the cs of the -; faulting instruction. If it is a hardware interrupt, it will not have -; the error code and the eflags will be at offset 8. -;---------------------------------------------------------------------------- -cprocfar PF_handler64k - -; Check if this is a processor exeception or a page fault - - push eax - mov ax,[cs:ValidCS] ; Use CS override to access data - cmp [ss:esp+12],ax ; Is this a page fault? - jne @@ToOldHandler ; Nope, jump to the previous handler - -; Get address of page fault and check if within our handlers range - - mov eax,cr2 ; EBX has page fault linear address - cmp eax,VFLAT_START ; Is the fault less than ours? - jb @@ToOldHandler ; Yep, go to previous handler - cmp eax,VFLAT_END ; Is the fault more than ours? - jae @@ToOldHandler ; Yep, go to previous handler - -; This is our page fault, so we need to handle it - - pushad - push ds - push es - mov ebx,eax ; EBX := page fault address - and ebx,invert 0FFFFh ; Mask to 64k bank boundary - mov ds,[cs:_PM_savedDS]; Load segment registers - mov es,[cs:_PM_savedDS] - -; Map in the page table for our virtual framebuffer area for modification - - mov edi,[PDBR] ; EDI points to page directory - mov edx,ebx ; EDX = linear address - shr edx,22 ; EDX = offset to page directory - mov edx,[edx*4+edi] ; EDX = physical page table address - mov eax,edx - mov edx,[accessPageTable] - or eax,7 - mov [edx],eax - mov eax,cr3 - mov cr3,eax ; Update page table cache - -; Mark all pages valid for the new page fault area - - mov esi,ebx ; ESI := linear address for page - shr esi,10 - and esi,0FFFh ; Offset into page table - add esi,[accessPageAddr] -ifdef USE_NASM -%assign off 0 -%rep 16 - or [DWORD esi+off],0000000001h ; Enable pages -%assign off off+4 -%endrep -else -off = 0 -REPT 16 - or [DWORD esi+off],0000000001h ; Enable pages -off = off+4 -ENDM -endif - -; Mark all pages invalid for the previously mapped area - - xchg esi,[LastPage] ; Save last page for next page fault - test esi,esi - jz @@DoneMapping ; Dont update if first time round -ifdef USE_NASM -%assign off 0 -%rep 16 - or [DWORD esi+off],0FFFFFFFEh ; Disable pages -%assign off off+4 -%endrep -else -off = 0 -REPT 16 - and [DWORD esi+off],0FFFFFFFEh ; Disable pages -off = off+4 -ENDM -endif - -@@DoneMapping: - mov eax,cr3 - mov cr3,eax ; Flush the TLB - -; Now program the new SuperVGA starting bank address - - mov eax,ebx ; EAX := page fault address - shr eax,16 - and eax,0FFh ; Mask to 0-255 - call [BankFuncPtr] ; Call the bank switch function - - pop es - pop ds - popad - pop eax - add esp,4 ; Pop the error code from stack - iretd ; Return to faulting instruction - -@@ToOldHandler: - pop eax -ifdef USE_NASM - jmp far dword [cs:INT14Gate]; Chain to previous handler -else - jmp [FWORD cs:INT14Gate]; Chain to previous handler -endif - -cprocend - -;---------------------------------------------------------------------------- -; PF_handler4k - Page fault handler for 4k banks -;---------------------------------------------------------------------------- -; The handler below is a 32 bit ring 0 page fault handler. It receives -; control immediately after any page fault or after an IRQ6 (hardware -; interrupt). This provides the fastest possible handling of page faults -; since it jump directly here. If this is a page fault, the number -; immediately on the stack will be an error code, at offset 4 will be -; the eip of the faulting instruction, at offset 8 will be the cs of the -; faulting instruction. If it is a hardware interrupt, it will not have -; the error code and the eflags will be at offset 8. -;---------------------------------------------------------------------------- -cprocfar PF_handler4k - -; Fill in when we have tested all the 64Kb code - -ifdef USE_NASM - jmp far dword [cs:INT14Gate]; Chain to previous handler -else - jmp [FWORD cs:INT14Gate]; Chain to previous handler -endif - -cprocend - -;---------------------------------------------------------------------------- -; void InstallFaultHandler(void *baseAddr,int bankSize) -;---------------------------------------------------------------------------- -; Installes the page fault handler directly int the interrupt descriptor -; table for maximum performance. This of course requires ring 0 access, -; but none of this stuff will run without ring 0! -;---------------------------------------------------------------------------- -cprocstart InstallFaultHandler - - ARG baseAddr:ULONG, bankSize:UINT - - enter_c - - mov [DWORD LastPage],0 ; No pages have been mapped - mov ax,cs - mov [ValidCS],ax ; Save CS value for page faults - -; Put address of our page fault handler into the IDT directly - - sub esp,6 ; Allocate space on stack -ifdef USE_NASM - sidt [ss:esp] ; Store pointer to IDT -else - sidt [FWORD ss:esp] ; Store pointer to IDT -endif - pop ax ; add esp,2 - pop eax ; Absolute address of IDT - add eax,14*8 ; Point to Int #14 - -; Note that Interrupt gates do not have the high and low word of the -; offset in adjacent words in memory, there are 4 bytes separating them. - - mov ecx,[eax] ; Get cs and low 16 bits of offset - mov edx,[eax+6] ; Get high 16 bits of offset in dx - shl edx,16 - mov dx,cx ; edx has offset - mov [INT14Offset],edx ; Save offset - shr ecx,16 - mov [INT14Selector],cx ; Save original cs - mov [eax+2],cs ; Install new cs - mov edx,offset PF_handler64k - cmp [UINT bankSize],4 - jne @@1 - mov edx,offset PF_handler4k -@@1: mov [eax],dx ; Install low word of offset - shr edx,16 - mov [eax+6],dx ; Install high word of offset - - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void RemoveFaultHandler(void) -;---------------------------------------------------------------------------- -; Closes down the virtual framebuffer services and restores the previous -; page fault handler. -;---------------------------------------------------------------------------- -cprocstart RemoveFaultHandler - - enter_c - -; Remove page fault handler from IDT - - sub esp,6 ; Allocate space on stack -ifdef USE_NASM - sidt [ss:esp] ; Store pointer to IDT -else - sidt [FWORD ss:esp] ; Store pointer to IDT -endif - - pop ax ; add esp,2 - pop eax ; Absolute address of IDT - add eax,14*8 ; Point to Int #14 - mov cx,[INT14Selector] - mov [eax+2],cx ; Restore original CS - mov edx,[INT14Offset] - mov [eax],dx ; Install low word of offset - shr edx,16 - mov [eax+6],dx ; Install high word of offset - - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; void InstallBankFunc(int codeLen,void *bankFunc) -;---------------------------------------------------------------------------- -; Installs the bank switch function by relocating it into our data segment -; and making it into a callable function. We do it this way to make the -; code identical to the way that the VflatD devices work under Windows. -;---------------------------------------------------------------------------- -cprocstart InstallBankFunc - - ARG codeLen:UINT, bankFunc:DPTR - - enter_c - - mov esi,[bankFunc] ; Copy the code into buffer - mov edi,offset BankFuncBuf - mov ecx,[codeLen] - rep movsb - mov [BYTE edi],0C3h ; Terminate the function with a near ret - - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; int InitPaging(void) -;---------------------------------------------------------------------------- -; Initializes paging system. If paging is not enabled, builds a page table -; directory and page tables for physical memory -; -; Exit: 0 - Successful -; -1 - Couldn't initialize paging mechanism -;---------------------------------------------------------------------------- -cprocstart InitPaging - - push ebx - push ecx - push edx - push esi - push edi - -; Are we running under CauseWay? - - mov ax,0FFF9h - int 31h - jc @@NotCauseway - cmp ecx,"CAUS" - jnz @@NotCauseway - cmp edx,"EWAY" - jnz @@NotCauseway - - mov [BOOL VF_haveCauseWay],1 - mov [CauseWayDIRLinear],esi - mov [CauseWay1stLinear],edi - -; Check for DPMI - - mov ax,0ff00h - push es - int 31h - pop es - shr edi,2 - and edi,3 - cmp edi,2 - jz @@ErrExit ; Not supported under DPMI - - mov eax,[CauseWayDIRLinear] - jmp @@CopyCR3 - -@@NotCauseway: - mov ax,cs - test ax,3 ; Which ring are we running - jnz @@ErrExit ; Needs zero ring to access - ; page tables (CR3) - mov eax,cr0 ; Load CR0 - test eax,80000000h ; Is paging enabled? - jz @@ErrExit ; No, we must have paging! - - mov eax,cr3 ; Load directory address - and eax,0FFFFF000h - -@@CopyCR3: - mov [PDBR],eax ; Save it - mov esi,eax - mov edi,offset pageDirectory - mov ecx,1024 - cld - rep movsd ; Copy the original page table directory - cmp [DWORD accessPageAddr],0; Check if we have allocated page - jne @@HaveRealMem ; table already (we cant free it) - - mov eax,0100h ; DPMI DOS allocate - mov ebx,8192/16 - int 31h ; Allocate 8192 bytes - and eax,0FFFFh - shl eax,4 ; EAX points to newly allocated memory - add eax,4095 - and eax,0FFFFF000h ; Page align - mov [accessPageAddr],eax - -@@HaveRealMem: - mov eax,[accessPageAddr] ; EAX -> page table in 1st Mb - shr eax,12 - and eax,3FFh ; Page table offset - shl eax,2 - cmp [BOOL VF_haveCauseWay],0 - jz @@NotCW0 - mov ebx,[CauseWay1stLinear] - jmp @@Put1st - -@@NotCW0: - mov ebx,[PDBR] - mov ebx,[ebx] - and ebx,0FFFFF000h ; Page table for 1st megabyte - -@@Put1st: - add eax,ebx - mov [accessPageTable],eax - sub eax,eax ; No error - jmp @@Exit - -@@ErrExit: - mov eax,-1 - -@@Exit: pop edi - pop esi - pop edx - pop ecx - pop ebx - ret - -cprocend - -;---------------------------------------------------------------------------- -; void ClosePaging(void) -;---------------------------------------------------------------------------- -; Closes the paging system -;---------------------------------------------------------------------------- -cprocstart ClosePaging - - push eax - push ecx - push edx - push esi - push edi - - mov eax,[accessPageAddr] - call AccessPage ; Restore AccessPage mapping - mov edi,[PDBR] - mov esi,offset pageDirectory - mov ecx,1024 - cld - rep movsd ; Restore the original page table directory - -@@Exit: pop edi - pop esi - pop edx - pop ecx - pop eax - ret - -cprocend - -;---------------------------------------------------------------------------- -; long AccessPage(long phys) -;---------------------------------------------------------------------------- -; Maps a known page to given physical memory -; Entry: EAX - Physical memory -; Exit: EAX - Linear memory address of mapped phys mem -;---------------------------------------------------------------------------- -cprocstatic AccessPage - - push edx - mov edx,[accessPageTable] - or eax,7 - mov [edx],eax - mov eax,cr3 - mov cr3,eax ; Update page table cache - mov eax,[accessPageAddr] - pop edx - ret - -cprocend - -;---------------------------------------------------------------------------- -; long GetPhysicalAddress(long linear) -;---------------------------------------------------------------------------- -; Returns the physical address of linear address -; Entry: EAX - Linear address to convert -; Exit: EAX - Physical address -;---------------------------------------------------------------------------- -cprocstatic GetPhysicalAddress - - push ebx - push edx - mov edx,eax - shr edx,22 ; EDX is the directory offset - mov ebx,[PDBR] - mov edx,[edx*4+ebx] ; Load page table address - push eax - mov eax,edx - call AccessPage ; Access the page table - mov edx,eax - pop eax - shr eax,12 - and eax,03FFh ; EAX offset into page table - mov eax,[edx+eax*4] ; Load physical address - and eax,0FFFFF000h - pop edx - pop ebx - ret - -cprocend - -;---------------------------------------------------------------------------- -; void CreatePageTable(long pageDEntry) -;---------------------------------------------------------------------------- -; Creates a page table for specific address (4MB) -; Entry: EAX - Page directory entry (top 10-bits of address) -;---------------------------------------------------------------------------- -cprocstatic CreatePageTable - - push ebx - push ecx - push edx - push edi - mov ebx,eax ; Save address - mov eax,8192 - push eax - call VF_malloc ; Allocate page table directory - add esp,4 - add eax,0FFFh - and eax,0FFFFF000h ; Page align (4KB) - mov edi,eax ; Save page table linear address - sub eax,eax ; Fill with zero - mov ecx,1024 - cld - rep stosd ; Clear page table - sub edi,4096 - mov eax,edi - call GetPhysicalAddress - mov edx,[PDBR] - or eax,7 ; Present/write/user bit - mov [edx+ebx*4],eax ; Save physical address into page directory - mov eax,cr3 - mov cr3,eax ; Update page table cache - pop edi - pop edx - pop ecx - pop ebx - ret - -cprocend - -;---------------------------------------------------------------------------- -; void MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags); -;---------------------------------------------------------------------------- -; Maps physical memory into linear memory -; Entry: pAddr - Physical address -; lAddr - Linear address -; pages - Number of 4K pages to map -; flags - Page flags -; bit 0 = present -; bit 1 = Read(0)/Write(1) -;---------------------------------------------------------------------------- -cprocstart MapPhysical2Linear - - ARG pAddr:ULONG, lAddr:ULONG, pages:UINT, pflags:UINT - - enter_c - - and [ULONG pAddr],0FFFFF000h; Page boundary - and [ULONG lAddr],0FFFFF000h; Page boundary - mov ecx,[pflags] - and ecx,11b ; Just two bits - or ecx,100b ; Supervisor bit - mov [pflags],ecx - - mov edx,[lAddr] - shr edx,22 ; EDX = Directory - mov esi,[PDBR] - mov edi,[pages] ; EDI page count - mov ebx,[lAddr] - -@@CreateLoop: - mov ecx,[esi+edx*4] ; Load page table address - test ecx,1 ; Is it present? - jnz @@TableOK - mov eax,edx - call CreatePageTable ; Create a page table -@@TableOK: - mov eax,ebx - shr eax,12 - and eax,3FFh - sub eax,1024 - neg eax ; EAX = page count in this table - inc edx ; Next table - mov ebx,0 ; Next time we'll map 1K pages - sub edi,eax ; Subtract mapped pages from page count - jns @@CreateLoop ; Create more tables if necessary - - mov ecx,[pages] ; ECX = Page count - mov esi,[lAddr] - shr esi,12 ; Offset part isn't needed - mov edi,[pAddr] -@@MappingLoop: - mov eax,esi - shr eax,10 ; EAX = offset to page directory - mov ebx,[PDBR] - mov eax,[eax*4+ebx] ; EAX = page table address - call AccessPage - mov ebx,esi - and ebx,3FFh ; EBX = offset to page table - mov edx,edi - add edi,4096 ; Next physical address - inc esi ; Next linear page - or edx,[pflags] ; Update flags... - mov [eax+ebx*4],edx ; Store page table entry - loop @@MappingLoop - mov eax,cr3 - mov cr3,eax ; Update page table cache - - leave_c - ret - -cprocend - -endcodeseg _vflat - -endif - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c deleted file mode 100644 index 5447e57..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit SMX embedded systems development. -* -* Description: SMX specific code for the CPU detection module. -* -****************************************************************************/ - -/*----------------------------- Implementation ----------------------------*/ - -/* External timing function */ - -void __ZTimerInit(void); - -/**************************************************************************** -REMARKS: -Do nothing for DOS because we don't have thread priorities. -****************************************************************************/ -#define SetMaxThreadPriority() 0 - -/**************************************************************************** -REMARKS: -Do nothing for DOS because we don't have thread priorities. -****************************************************************************/ -#define RestoreThreadPriority(i) (void)(i) - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - ulong resolution; - - __ZTimerInit(); - ULZTimerResolution(&resolution); - freq->low = (ulong)(10000000000.0 / resolution); - freq->high = 0; -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. -****************************************************************************/ -#define GetCounter(t) \ -{ \ - (t)->low = ULZReadTime() * 10000L; \ - (t)->high = 0; \ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/event.c b/board/MAI/bios_emulator/scitech/src/pm/smx/event.c deleted file mode 100644 index 533c261..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/event.c +++ /dev/null @@ -1,368 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit SMX embedded systems development -* -* Description: 32-bit SMX implementation for the SciTech cross platform -* event library. -* -****************************************************************************/ - -#include "smx/ps2mouse.h" - -/*--------------------------- Global variables ----------------------------*/ - -ibool _VARAPI _EVT_useEvents = true; /* True to use event handling */ -ibool _VARAPI _EVT_installed = 0; /* Event handers installed? */ -uchar _VARAPI *_EVT_biosPtr = NULL; /* Pointer to the BIOS data area */ -static ibool haveMouse = false; /* True if we have a mouse */ - -/*---------------------------- Implementation -----------------------------*/ - -/* External assembler functions */ - -void EVTAPI _EVT_pollJoystick(void); -uint EVTAPI _EVT_disableInt(void); -uint EVTAPI _EVT_restoreInt(uint flags); -void EVTAPI _EVT_codeStart(void); -void EVTAPI _EVT_codeEnd(void); -void EVTAPI _EVT_cCodeStart(void); -void EVTAPI _EVT_cCodeEnd(void); -int EVTAPI _EVT_getKeyCode(void); -int EVTAPI EVT_rdinx(int port,int index); -void EVTAPI EVT_wrinx(int port,int index,int value); - -/**************************************************************************** -REMARKS: -Do nothing for DOS, because we are fully interrupt driven. -****************************************************************************/ -#define _EVT_pumpMessages() - -/**************************************************************************** -REMARKS: -This function is used to return the number of ticks since system -startup in milliseconds. This should be the same value that is placed into -the time stamp fields of events, and is used to implement auto mouse down -events. -****************************************************************************/ -ulong _EVT_getTicks(void) -{ - return (ulong)PM_getLong(_EVT_biosPtr+0x6C) * 55UL; -} - -/**************************************************************************** -REMARKS: -Include generic raw scancode keyboard module. -****************************************************************************/ -#include "common/keyboard.c" - -/**************************************************************************** -REMARKS: -Determines if we have a mouse attached and functioning. -****************************************************************************/ -static ibool detectMouse(void) -{ - return(ps2Query()); -} - -/**************************************************************************** -PARAMETERS: -what - Event code -message - Event message -x,y - Mouse position at time of event -but_stat - Mouse button status at time of event - -REMARKS: -Adds a new mouse event to the event queue. This routine is called from within -the mouse interrupt subroutine, so it must be efficient. - -NOTE: Interrupts MUST be OFF while this routine is called to ensure we have - mutually exclusive access to our internal data structures for - interrupt driven systems (like under DOS). -****************************************************************************/ -static void addMouseEvent( - uint what, - uint message, - int x, - int y, - int mickeyX, - int mickeyY, - uint but_stat) -{ - event_t evt; - - if (EVT.count < EVENTQSIZE) { - /* Save information in event record. */ - evt.when = _EVT_getTicks(); - evt.what = what; - evt.message = message; - evt.modifiers = but_stat; - evt.where_x = x; /* Save mouse event position */ - evt.where_y = y; - evt.relative_x = mickeyX; - evt.relative_y = mickeyY; - evt.modifiers |= EVT.keyModifiers; - addEvent(&evt); /* Add to tail of event queue */ - } -} - -/**************************************************************************** -PARAMETERS: -mask - Event mask -butstate - Button state -x - Mouse x coordinate -y - Mouse y coordinate - -REMARKS: -Mouse event handling routine. This gets called when a mouse event occurs, -and we call the addMouseEvent() routine to add the appropriate mouse event -to the event queue. - -Note: Interrupts are ON when this routine is called by the mouse driver code. -/*AM: NOTE: This function has not actually been ported from DOS yet and should not */ -/*AM: be installed until it is. */ -****************************************************************************/ -static void EVTAPI mouseISR( - uint mask, - uint butstate, - int x, - int y, - int mickeyX, - int mickeyY) -{ - RMREGS regs; - uint ps; - - if (mask & 1) { - /* Save the current mouse coordinates */ - EVT.mx = x; EVT.my = y; - - /* If the last event was a movement event, then modify the last - * event rather than post a new one, so that the queue will not - * become saturated. Before we modify the data structures, we - * MUST ensure that interrupts are off. - */ - ps = _EVT_disableInt(); - if (EVT.oldMove != -1) { - EVT.evtq[EVT.oldMove].where_x = x; /* Modify existing one */ - EVT.evtq[EVT.oldMove].where_y = y; - EVT.evtq[EVT.oldMove].relative_x += mickeyX; - EVT.evtq[EVT.oldMove].relative_y += mickeyY; - } - else { - EVT.oldMove = EVT.freeHead; /* Save id of this move event */ - addMouseEvent(EVT_MOUSEMOVE,0,x,y,mickeyX,mickeyY,butstate); - } - _EVT_restoreInt(ps); - } - if (mask & 0x2A) { - ps = _EVT_disableInt(); - addMouseEvent(EVT_MOUSEDOWN,mask >> 1,x,y,0,0,butstate); - EVT.oldMove = -1; - _EVT_restoreInt(ps); - } - if (mask & 0x54) { - ps = _EVT_disableInt(); - addMouseEvent(EVT_MOUSEUP,mask >> 2,x,y,0,0,butstate); - EVT.oldMove = -1; - _EVT_restoreInt(ps); - } - EVT.oldKey = -1; -} - -/**************************************************************************** -REMARKS: -Keyboard interrupt handler function. - -NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, - and we leave them OFF the entire time. This has been modified to work - in conjunction with smx keyboard handler. -****************************************************************************/ -static void EVTAPI keyboardISR(void) -{ - PM_chainPrevKey(); - processRawScanCode(PM_inpb(0x60)); - PM_outpb(0x20,0x20); -} - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _EVT_abort() -{ - EVT_exit(); - PM_fatalError("Unhandled exception!"); -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -void EVTAPI EVT_init( - _EVT_mouseMoveHandler mouseMove) -{ - int i; - - EVT.mouseMove = mouseMove; - _EVT_biosPtr = PM_getBIOSPointer(); - EVT_resume(); -} - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVTAPI EVT_resume(void) -{ - static int locked = 0; - int stat; - uchar mods; - PM_lockHandle lh; - - if (_EVT_useEvents) { - /* Initialise the event queue and enable our interrupt handlers */ - initEventQueue(); - PM_setKeyHandler(keyboardISR); - if ((haveMouse = detectMouse()) != 0) - PM_setMouseHandler(0xFFFF,mouseISR); - - /* Read the keyboard modifier flags from the BIOS to get the - * correct initialisation state. The only state we care about is - * the correct toggle state flags such as SCROLLLOCK, NUMLOCK and - * CAPSLOCK. - */ - EVT.keyModifiers = 0; - mods = PM_getByte(_EVT_biosPtr+0x17); - if (mods & 0x10) - EVT.keyModifiers |= EVT_SCROLLLOCK; - if (mods & 0x20) - EVT.keyModifiers |= EVT_NUMLOCK; - if (mods & 0x40) - EVT.keyModifiers |= EVT_CAPSLOCK; - - /* Lock all of the code and data used by our protected mode interrupt - * handling routines, so that it will continue to work correctly - * under real mode. - */ - if (!locked) { - /* It is difficult to ensure that we lock our global data, so we - * do this by taking the address of a variable locking all data - * 2Kb on either side. This should properly cover the global data - * used by the module (the other alternative is to declare the - * variables in assembler, in which case we know it will be - * correct). - */ - stat = !PM_lockDataPages(&EVT,sizeof(EVT),&lh); - stat |= !PM_lockDataPages(&_EVT_biosPtr,sizeof(_EVT_biosPtr),&lh); - stat |= !PM_lockCodePages((__codePtr)_EVT_cCodeStart,(int)_EVT_cCodeEnd-(int)_EVT_cCodeStart,&lh); - stat |= !PM_lockCodePages((__codePtr)_EVT_codeStart,(int)_EVT_codeEnd-(int)_EVT_codeStart,&lh); - if (stat) { - PM_fatalError("Page locking services failed - interrupt handling not safe!"); - exit(1); - } - locked = 1; - } - - _EVT_installed = true; - } -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - if (haveMouse) { - ps2MouseStop(); - ps2MouseStart( 0, xRes, 0, yRes, -1, -1, -1); - } -} - -/**************************************************************************** -REMARKS -Modifes the mouse coordinates as necessary if scaling to OS coordinates, -and sets the OS mouse cursor position. -****************************************************************************/ -void _EVT_setMousePos( - int *x, - int *y) -{ - if (haveMouse) - ps2MouseMove(*x, *y); -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVTAPI EVT_suspend(void) -{ - uchar mods; - - if (_EVT_installed) { - PM_restoreKeyHandler(); - if (haveMouse) - PM_restoreMouseHandler(); - - /* Set the keyboard modifier flags in the BIOS to our values */ - EVT_allowLEDS(true); - mods = PM_getByte(_EVT_biosPtr+0x17) & ~0x70; - if (EVT.keyModifiers & EVT_SCROLLLOCK) - mods |= 0x10; - if (EVT.keyModifiers & EVT_NUMLOCK) - mods |= 0x20; - if (EVT.keyModifiers & EVT_CAPSLOCK) - mods |= 0x40; - PM_setByte(_EVT_biosPtr+0x17,mods); - - /* Flag that we are no longer installed */ - _EVT_installed = false; - } -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVTAPI EVT_exit(void) -{ - EVT_suspend(); -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h deleted file mode 100644 index 3ff8daa..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h +++ /dev/null @@ -1,29 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit SMX embedded systems development. -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c b/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c deleted file mode 100644 index 99ee3d4..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c +++ /dev/null @@ -1,1187 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32 bit SMX embedded systems development. -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include "ztimerc.h" -#include "event.h" -#include "mtrr.h" -#include "pm_help.h" -#include -#include -#include -#include -#include -#ifdef __GNUC__ -#include -#include -#include -#else -#include -#endif -#ifdef __BORLANDC__ -#pragma warn -par -#endif - -/*--------------------------- Global variables ----------------------------*/ - -typedef struct { - int oldMode; - int old50Lines; - } DOS_stateBuf; - -#define MAX_RM_BLOCKS 10 - -static struct { - void *p; - uint tag; - } rmBlocks[MAX_RM_BLOCKS]; - -static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ -static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ -static uint VESABuf_rseg; /* Real mode segment of VESABuf */ -static uint VESABuf_roff; /* Real mode offset of VESABuf */ -static void (PMAPIP fatalErrorCleanup)(void) = NULL; -ushort _VARAPI _PM_savedDS = 0; -static ulong PDB = 0,*pPDB = NULL; -static uint VXD_version = -1; - -/*----------------------------- Implementation ----------------------------*/ - -ulong _ASMAPI _PM_getPDB(void); -void _ASMAPI _PM_VxDCall(VXD_regs *regs,uint off,uint sel); - -/**************************************************************************** -REMARKS: -External function to call the PMHELP helper VxD. -****************************************************************************/ -void PMAPI PM_VxDCall( - VXD_regs *regs) -{ -} - -/**************************************************************************** -RETURNS: -BCD coded version number of the VxD, or 0 if not loaded (ie: 0x202 - 2.2) - -REMARKS: -This function gets the version number for the VxD that we have connected to. -****************************************************************************/ -uint PMAPI PMHELP_getVersion(void) -{ - return VXD_version = 0; -} - -void PMAPI PM_init(void) -{ -#ifndef REALMODE - MTRR_init(); -#endif -} - -/**************************************************************************** -PARAMETERS: -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -RETURNS: -Error code describing the result. - -REMARKS: -Function to enable write combining for the specified region of memory. -****************************************************************************/ -int PMAPI PM_enableWriteCombine( - ulong base, - ulong size, - uint type) -{ -#ifndef REALMODE - return MTRR_enableWriteCombine(base,size,type); -#else - return PM_MTRR_NOT_SUPPORTED; -#endif -} - -ibool PMAPI PM_haveBIOSAccess(void) -{ return false; } - -long PMAPI PM_getOSType(void) -{ return _OS_SMX; } - -int PMAPI PM_getModeType(void) -{ return PM_386; } - -void PMAPI PM_backslash(char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '\\') { - s[pos] = '\\'; - s[pos+1] = '\0'; - } -} - -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -void MGLOutput(char *); - -void PMAPI PM_fatalError(const char *msg) -{ - if (fatalErrorCleanup) - fatalErrorCleanup(); - MGLOutput(msg); -/* No support for fprintf() under smx currently! */ -/* fprintf(stderr,"%s\n", msg); */ - exit(1); -} - -static void ExitVBEBuf(void) -{ - if (VESABuf_ptr) - PM_freeRealSeg(VESABuf_ptr); - VESABuf_ptr = 0; -} - -void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) -{ - if (!VESABuf_ptr) { - /* Allocate a global buffer for communicating with the VESA VBE */ - if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) - return NULL; - atexit(ExitVBEBuf); - } - *len = VESABuf_len; - *rseg = VESABuf_rseg; - *roff = VESABuf_roff; - return VESABuf_ptr; -} - -int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out) -{ - PMSREGS sregs; - PM_segread(&sregs); - return PM_int386x(intno,in,out,&sregs); -} - -/* Routines to set and get the real mode interrupt vectors, by making - * direct real mode calls to DOS and bypassing the DOS extenders API. - * This is the safest way to handle this, as some servers try to be - * smart about changing real mode vectors. - */ - -void PMAPI _PM_getRMvect(int intno, long *realisr) -{ - RMREGS regs; - RMSREGS sregs; - - PM_saveDS(); - regs.h.ah = 0x35; - regs.h.al = intno; - PM_int86x(0x21, ®s, ®s, &sregs); - *realisr = ((long)sregs.es << 16) | regs.x.bx; -} - -void PMAPI _PM_setRMvect(int intno, long realisr) -{ - RMREGS regs; - RMSREGS sregs; - - PM_saveDS(); - regs.h.ah = 0x25; - regs.h.al = intno; - sregs.ds = (int)(realisr >> 16); - regs.x.dx = (int)(realisr & 0xFFFF); - PM_int86x(0x21, ®s, ®s, &sregs); -} - -void PMAPI _PM_addRealModeBlock(void *mem,uint tag) -{ - int i; - - for (i = 0; i < MAX_RM_BLOCKS; i++) { - if (rmBlocks[i].p == NULL) { - rmBlocks[i].p = mem; - rmBlocks[i].tag = tag; - return; - } - } - PM_fatalError("To many real mode memory block allocations!"); -} - -uint PMAPI _PM_findRealModeBlock(void *mem) -{ - int i; - - for (i = 0; i < MAX_RM_BLOCKS; i++) { - if (rmBlocks[i].p == mem) - return rmBlocks[i].tag; - } - PM_fatalError("Could not find prior real mode memory block allocation!"); - return 0; -} - -char * PMAPI PM_getCurrentPath( - char *path, - int maxLen) -{ - return getcwd(path,maxLen); -} - -char PMAPI PM_getBootDrive(void) -{ return 'C'; } - -const char * PMAPI PM_getVBEAFPath(void) -{ return "c:\\"; } - -const char * PMAPI PM_getNucleusPath(void) -{ - static char path[256]; - char *env; - - if ((env = getenv("NUCLEUS_PATH")) != NULL) - return env; - return "c:\\nucleus"; -} - -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[256]; - strcpy(path,PM_getNucleusPath()); - PM_backslash(path); - strcat(path,"config"); - return path; -} - -const char * PMAPI PM_getUniqueID(void) -{ return "SMX"; } - -const char * PMAPI PM_getMachineName(void) -{ return "SMX"; } - -int PMAPI PM_kbhit(void) -{ - int hit; - event_t evt; - - hit = EVT_peekNext(&evt,EVT_KEYDOWN | EVT_KEYREPEAT); - EVT_flush(~(EVT_KEYDOWN | EVT_KEYREPEAT)); - return hit; -} - -int PMAPI PM_getch(void) -{ - event_t evt; - - EVT_halt(&evt,EVT_KEYDOWN); - return EVT_asciiCode(evt.message); -} - -PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen) -{ - /* Not used for SMX */ - (void)hwndUser; - (void)device; - (void)xRes; - (void)yRes; - (void)bpp; - (void)fullScreen; - return 0; -} - -int PMAPI PM_getConsoleStateSize(void) -{ - return sizeof(DOS_stateBuf); -} - -void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole) -{ - RMREGS regs; - DOS_stateBuf *sb = stateBuf; - - /* Save the old video mode state */ - regs.h.ah = 0x0F; - PM_int86(0x10,®s,®s); - sb->oldMode = regs.h.al & 0x7F; - sb->old50Lines = false; - if (sb->oldMode == 0x3) { - regs.x.ax = 0x1130; - regs.x.bx = 0; - regs.x.dx = 0; - PM_int86(0x10,®s,®s); - sb->old50Lines = (regs.h.dl == 42 || regs.h.dl == 49); - } - (void)hwndConsole; -} - -void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) -{ - /* Not used for SMX */ - (void)saveState; -} - -void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) -{ - RMREGS regs; - const DOS_stateBuf *sb = stateBuf; - - /* Retore 50 line mode if set */ - if (sb->old50Lines) { - regs.x.ax = 0x1112; - regs.x.bx = 0; - PM_int86(0x10,®s,®s); - } - (void)hwndConsole; -} - -void PMAPI PM_closeConsole(PM_HWND hwndConsole) -{ - /* Not used for SMX */ - (void)hwndConsole; -} - -void PMAPI PM_setOSCursorLocation(int x,int y) -{ - uchar *_biosPtr = PM_getBIOSPointer(); - PM_setByte(_biosPtr+0x50,x); - PM_setByte(_biosPtr+0x51,y); -} - -void PMAPI PM_setOSScreenWidth(int width,int height) -{ - uchar *_biosPtr = PM_getBIOSPointer(); - PM_setWord(_biosPtr+0x4A,width); - PM_setWord(_biosPtr+0x4C,width*2); - PM_setByte(_biosPtr+0x84,height-1); - if (height > 25) { - PM_setWord(_biosPtr+0x60,0x0607); - PM_setByte(_biosPtr+0x85,0x08); - } - else { - PM_setWord(_biosPtr+0x60,0x0D0E); - PM_setByte(_biosPtr+0x85,0x016); - } -} - -void * PMAPI PM_mallocShared(long size) -{ - return PM_malloc(size); -} - -void PMAPI PM_freeShared(void *ptr) -{ - PM_free(ptr); -} - -#define GetRMVect(intno,isr) *(isr) = ((ulong*)rmZeroPtr)[intno] -#define SetRMVect(intno,isr) ((ulong*)rmZeroPtr)[intno] = (isr) - -ibool PMAPI PM_doBIOSPOST( - ushort axVal, - ulong BIOSPhysAddr, - void *mappedBIOS, - ulong BIOSLen) -{ - static int firstTime = true; - static uchar *rmZeroPtr; - long Current10,Current6D,Current42; - RMREGS regs; - RMSREGS sregs; - - /* Create a zero memory mapping for us to use */ - if (firstTime) { - rmZeroPtr = PM_mapPhysicalAddr(0,0x7FFF,true); - firstTime = false; - } - - /* Remap the secondary BIOS to 0xC0000 physical */ - if (BIOSPhysAddr != 0xC0000L || BIOSLen > 32768) { - /* SMX cannot virtually remap the BIOS, so we can only work if all - * the secondary controllers are identical, and we then use the - * BIOS on the first controller for all the remaining controllers. - * - * For OS'es that do virtual memory, and remapping of 0xC0000 - * physical (perhaps a copy on write mapping) should be all that - * is needed. - */ - return false; - } - - /* Save current handlers of int 10h and 6Dh */ - GetRMVect(0x10,&Current10); - GetRMVect(0x6D,&Current6D); - - /* POST the secondary BIOS */ - GetRMVect(0x42,&Current42); - SetRMVect(0x10,Current42); /* Restore int 10h to STD-BIOS */ - regs.x.ax = axVal; - PM_callRealMode(0xC000,0x0003,®s,&sregs); - - /* Restore current handlers */ - SetRMVect(0x10,Current10); - SetRMVect(0x6D,Current6D); - - /* Second the primary BIOS mappin 1:1 for 0xC0000 physical */ - if (BIOSPhysAddr != 0xC0000L) { - /* SMX does not support this */ - (void)mappedBIOS; - } - return true; -} - -void PMAPI PM_sleep(ulong milliseconds) -{ - ulong microseconds = milliseconds * 1000L; - LZTimerObject tm; - - LZTimerOnExt(&tm); - while (LZTimerLapExt(&tm) < microseconds) - ; - LZTimerOffExt(&tm); -} - -int PMAPI PM_getCOMPort(int port) -{ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - } - return 0; -} - -int PMAPI PM_getLPTPort(int port) -{ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -PM_MODULE PMAPI PM_loadLibrary( - const char *szDLLName) -{ - (void)szDLLName; - return NULL; -} - -void * PMAPI PM_getProcAddress( - PM_MODULE hModule, - const char *szProcName) -{ - (void)hModule; - (void)szProcName; - return NULL; -} - -void PMAPI PM_freeLibrary( - PM_MODULE hModule) -{ - (void)hModule; -} - -int PMAPI PM_setIOPL( - int level) -{ - return level; -} - -/**************************************************************************** -REMARKS: -Internal function to convert the find data to the generic interface. -****************************************************************************/ -static void convertFindData( - PM_findData *findData, - struct find_t *blk) -{ - ulong dwSize = findData->dwSize; - - memset(findData,0,findData->dwSize); - findData->dwSize = dwSize; - if (blk->attrib & _A_RDONLY) - findData->attrib |= PM_FILE_READONLY; - if (blk->attrib & _A_SUBDIR) - findData->attrib |= PM_FILE_DIRECTORY; - if (blk->attrib & _A_ARCH) - findData->attrib |= PM_FILE_ARCHIVE; - if (blk->attrib & _A_HIDDEN) - findData->attrib |= PM_FILE_HIDDEN; - if (blk->attrib & _A_SYSTEM) - findData->attrib |= PM_FILE_SYSTEM; - findData->sizeLo = blk->size; - strncpy(findData->name,blk->name,PM_MAX_PATH); - findData->name[PM_MAX_PATH-1] = 0; -} - -#define FIND_MASK (_A_RDONLY | _A_ARCH | _A_SUBDIR | _A_HIDDEN | _A_SYSTEM) - -/**************************************************************************** -REMARKS: -Function to find the first file matching a search criteria in a directory. -****************************************************************************/ -void * PMAPI PM_findFirstFile( - const char *filename, - PM_findData *findData) -{ - struct find_t *blk; - - if ((blk = PM_malloc(sizeof(*blk))) == NULL) - return PM_FILE_INVALID; - if (_dos_findfirst((char*)filename,FIND_MASK,blk) == 0) { - convertFindData(findData,blk); - return blk; - } - return PM_FILE_INVALID; -} - -/**************************************************************************** -REMARKS: -Function to find the next file matching a search criteria in a directory. -****************************************************************************/ -ibool PMAPI PM_findNextFile( - void *handle, - PM_findData *findData) -{ - struct find_t *blk = handle; - - if (_dos_findnext(blk) == 0) { - convertFindData(findData,blk); - return true; - } - return false; -} - -/**************************************************************************** -REMARKS: -Function to close the find process -****************************************************************************/ -void PMAPI PM_findClose( - void *handle) -{ - PM_free(handle); -} - -/**************************************************************************** -REMARKS: -Function to determine if a drive is a valid drive or not. Under Unix this -function will return false for anything except a value of 3 (considered -the root drive, and equivalent to C: for non-Unix systems). The drive -numbering is: - - 1 - Drive A: - 2 - Drive B: - 3 - Drive C: - etc - -****************************************************************************/ -ibool PMAPI PM_driveValid( - char drive) -{ - RMREGS regs; - regs.h.dl = (uchar)(drive - 'A' + 1); - regs.h.ah = 0x36; /* Get disk information service */ - PM_int86(0x21,®s,®s); - return regs.x.ax != 0xFFFF; /* AX = 0xFFFF if disk is invalid */ -} - -/**************************************************************************** -REMARKS: -Function to get the current working directory for the specififed drive. -Under Unix this will always return the current working directory regardless -of what the value of 'drive' is. -****************************************************************************/ -void PMAPI PM_getdcwd( - int drive, - char *dir, - int len) -{ - uint oldDrive,maxDrives; - _dos_getdrive(&oldDrive); - _dos_setdrive(drive,&maxDrives); - getcwd(dir,len); - _dos_setdrive(oldDrive,&maxDrives); -} - -/**************************************************************************** -REMARKS: -Function to change the file attributes for a specific file. -****************************************************************************/ -void PMAPI PM_setFileAttr( - const char *filename, - uint attrib) -{ -#if defined(TNT) && defined(_MSC_VER) - DWORD attr = 0; - - if (attrib & PM_FILE_READONLY) - attr |= FILE_ATTRIBUTE_READONLY; - if (attrib & PM_FILE_ARCHIVE) - attr |= FILE_ATTRIBUTE_ARCHIVE; - if (attrib & PM_FILE_HIDDEN) - attr |= FILE_ATTRIBUTE_HIDDEN; - if (attrib & PM_FILE_SYSTEM) - attr |= FILE_ATTRIBUTE_SYSTEM; - SetFileAttributes((LPSTR)filename, attr); -#else - uint attr = 0; - - if (attrib & PM_FILE_READONLY) - attr |= _A_RDONLY; - if (attrib & PM_FILE_ARCHIVE) - attr |= _A_ARCH; - if (attrib & PM_FILE_HIDDEN) - attr |= _A_HIDDEN; - if (attrib & PM_FILE_SYSTEM) - attr |= _A_SYSTEM; - _dos_setfileattr(filename,attr); -#endif -} - -/**************************************************************************** -REMARKS: -Function to create a directory. -****************************************************************************/ -ibool PMAPI PM_mkdir( - const char *filename) -{ -#ifdef __GNUC__ - return mkdir(filename,S_IRUSR) == 0; -#else -/*AM: return mkdir(filename) == 0; */ - return(false); -#endif -} - -/**************************************************************************** -REMARKS: -Function to remove a directory. -****************************************************************************/ -ibool PMAPI PM_rmdir( - const char *filename) -{ -/*AM: return rmdir(filename) == 0; */ - return(false); -} - -/**************************************************************************** -REMARKS: -Allocates a block of locked, physically contiguous memory. The memory -may be required to be below the 16Meg boundary. -****************************************************************************/ -void * PMAPI PM_allocLockedMem( - uint size, - ulong *physAddr, - ibool contiguous, - ibool below16M) -{ - void *p; - uint r_seg,r_off; - PM_lockHandle lh; - - /* Under DOS the only way to know the physical memory address is to - * allocate the memory below the 1Meg boundary as real mode memory. - * We also allocate 4095 bytes more memory than we need, so we can - * properly page align the start of the memory block for DMA operations. - */ - if (size > 4096) - return NULL; - if ((p = PM_allocRealSeg((size + 0xFFF) & ~0xFFF,&r_seg,&r_off)) == NULL) - return NULL; - *physAddr = ((r_seg << 4) + r_off + 0xFFF) & ~0xFFF; - PM_lockDataPages(p,size*2,&lh); - return p; -} - -void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) -{ - (void)size; - PM_freeRealSeg(p); -} - -/*-------------------------------------------------------------------------*/ -/* Generic DPMI routines common to 16/32 bit code */ -/*-------------------------------------------------------------------------*/ - -ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit) -{ - PMREGS r; - ulong physOfs; - - if (physAddr < 0x100000L) { - /* We can't map memory below 1Mb, but the linear address are already - * mapped 1:1 for this memory anyway so we just return the base address. - */ - return physAddr; - } - - /* Round the physical address to a 4Kb boundary and the limit to a - * 4Kb-1 boundary before passing the values to DPMI as some extenders - * will fail the calls unless this is the case. If we round the - * physical address, then we also add an extra offset into the address - * that we return. - */ - physOfs = physAddr & 4095; - physAddr = physAddr & ~4095; - limit = ((limit+physOfs+1+4095) & ~4095)-1; - - r.x.ax = 0x800; /* DPMI map physical to linear */ - r.x.bx = physAddr >> 16; - r.x.cx = physAddr & 0xFFFF; - r.x.si = limit >> 16; - r.x.di = limit & 0xFFFF; - PM_int386(0x31, &r, &r); - if (r.x.cflag) - return 0xFFFFFFFFUL; - return ((ulong)r.x.bx << 16) + r.x.cx + physOfs; -} - -int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr) -{ - PMREGS r; - - r.x.ax = 7; /* DPMI set selector base address */ - r.x.bx = sel; - r.x.cx = linAddr >> 16; - r.x.dx = linAddr & 0xFFFF; - PM_int386(0x31, &r, &r); - if (r.x.cflag) - return 0; - return 1; -} - -ulong PMAPI DPMI_getSelectorBase(ushort sel) -{ - PMREGS r; - - r.x.ax = 6; /* DPMI get selector base address */ - r.x.bx = sel; - PM_int386(0x31, &r, &r); - return ((ulong)r.x.cx << 16) + r.x.dx; -} - -int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit) -{ - PMREGS r; - - r.x.ax = 8; /* DPMI set selector limit */ - r.x.bx = sel; - r.x.cx = limit >> 16; - r.x.dx = limit & 0xFFFF; - PM_int386(0x31, &r, &r); - if (r.x.cflag) - return 0; - return 1; -} - -uint PMAPI DPMI_createSelector(ulong base,ulong limit) -{ - uint sel; - PMREGS r; - - /* Allocate 1 descriptor */ - r.x.ax = 0; - r.x.cx = 1; - PM_int386(0x31, &r, &r); - if (r.x.cflag) return 0; - sel = r.x.ax; - - /* Set the descriptor access rights (for a 32 bit page granular - * segment, ring 0). - */ - r.x.ax = 9; - r.x.bx = sel; - r.x.cx = 0x4093; - PM_int386(0x31, &r, &r); - - /* Map physical memory and create selector */ - if ((base = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFFUL) - return 0; - if (!DPMI_setSelectorBase(sel,base)) - return 0; - if (!DPMI_setSelectorLimit(sel,limit)) - return 0; - return sel; -} - -void PMAPI DPMI_freeSelector(uint sel) -{ - PMREGS r; - - r.x.ax = 1; - r.x.bx = sel; - PM_int386(0x31, &r, &r); -} - -int PMAPI DPMI_lockLinearPages(ulong linear,ulong len) -{ - PMREGS r; - - r.x.ax = 0x600; /* DPMI Lock Linear Region */ - r.x.bx = (linear >> 16); /* Linear address in BX:CX */ - r.x.cx = (linear & 0xFFFF); - r.x.si = (len >> 16); /* Length in SI:DI */ - r.x.di = (len & 0xFFFF); - PM_int386(0x31, &r, &r); - return (!r.x.cflag); -} - -int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len) -{ - PMREGS r; - - r.x.ax = 0x601; /* DPMI Unlock Linear Region */ - r.x.bx = (linear >> 16); /* Linear address in BX:CX */ - r.x.cx = (linear & 0xFFFF); - r.x.si = (len >> 16); /* Length in SI:DI */ - r.x.di = (len & 0xFFFF); - PM_int386(0x31, &r, &r); - return (!r.x.cflag); -} - -void * PMAPI DPMI_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) -{ - PMSREGS sregs; - ulong linAddr; - ulong DSBaseAddr; - - /* Get the base address for the default DS selector */ - PM_segread(&sregs); - DSBaseAddr = DPMI_getSelectorBase(sregs.ds); - if ((base < 0x100000) && (DSBaseAddr == 0)) { - /* DS is zero based, so we can directly access the first 1Mb of - * system memory (like under DOS4GW). - */ - return (void*)base; - } - - /* Map the memory to a linear address using DPMI function 0x800 */ - if ((linAddr = DPMI_mapPhysicalToLinear(base,limit)) == 0) { - if (base >= 0x100000) - return NULL; - /* If the linear address mapping fails but we are trying to - * map an area in the first 1Mb of system memory, then we must - * be running under a Windows or OS/2 DOS box. Under these - * environments we can use the segment wrap around as a fallback - * measure, as this does work properly. - */ - linAddr = base; - } - - /* Now expand the default DS selector to 4Gb so we can access it */ - if (!DPMI_setSelectorLimit(sregs.ds,0xFFFFFFFFUL)) - return NULL; - - /* Finally enable caching for the page tables that we just mapped in, - * since DOS4GW and PMODE/W create the page table entries without - * caching enabled which hurts the performance of the linear framebuffer - * as it disables write combining on Pentium Pro and above processors. - * - * For those processors cache disabling is better handled through the - * MTRR registers anyway (we can write combine a region but disable - * caching) so that MMIO register regions do not screw up. - */ - if (isCached) { - if ((PDB = _PM_getPDB()) != 0 && DSBaseAddr == 0) { - int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; - ulong pageTable,*pPageTable; - if (!pPDB) { - if (PDB >= 0x100000) - pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF); - else - pPDB = (ulong*)PDB; - } - if (pPDB) { - startPDB = (linAddr >> 22) & 0x3FF; - startPage = (linAddr >> 12) & 0x3FF; - endPDB = ((linAddr+limit) >> 22) & 0x3FF; - endPage = ((linAddr+limit) >> 12) & 0x3FF; - for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { - pageTable = pPDB[iPDB] & ~0xFFF; - if (pageTable >= 0x100000) - pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF); - else - pPageTable = (ulong*)pageTable; - start = (iPDB == startPDB) ? startPage : 0; - end = (iPDB == endPDB) ? endPage : 0x3FF; - for (iPage = start; iPage <= end; iPage++) - pPageTable[iPage] &= ~0x18; - } - } - } - } - - /* Now return the base address of the memory into the default DS */ - return (void*)(linAddr - DSBaseAddr); -} - -/* Some DOS extender implementations do not directly support calling a - * real mode procedure from protected mode. However we can simulate what - * we need temporarily hooking the INT 6Ah vector with a small real mode - * stub that will call our real mode code for us. - */ - -static uchar int6AHandler[] = { - 0x00,0x00,0x00,0x00, /* __PMODE_callReal variable */ - 0xFB, /* sti */ - 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PMODE_callReal] */ - 0xCF, /* iretf */ - }; -static uchar *crPtr = NULL; /* Pointer to of int 6A handler */ -static uint crRSeg,crROff; /* Real mode seg:offset of handler */ - -void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, - RMSREGS *sregs) -{ - uchar *p; - uint oldSeg,oldOff; - - if (!crPtr) { - /* Allocate and copy the memory block only once */ - crPtr = PM_allocRealSeg(sizeof(int6AHandler), &crRSeg, &crROff); - memcpy(crPtr,int6AHandler,sizeof(int6AHandler)); - } - PM_setWord(crPtr,off); /* Plug in address to call */ - PM_setWord(crPtr+2,seg); - p = PM_mapRealPointer(0,0x6A * 4); - oldOff = PM_getWord(p); /* Save old handler address */ - oldSeg = PM_getWord(p+2); - PM_setWord(p,crROff+4); /* Hook 6A handler */ - PM_setWord(p+2,crRSeg); - PM_int86x(0x6A, in, in, sregs); /* Call real mode code */ - PM_setWord(p,oldOff); /* Restore old handler */ - PM_setWord(p+2,oldSeg); -} - -void * PMAPI PM_getBIOSPointer(void) -{ return PM_mapPhysicalAddr(0x400,0xFFFF,true); } - -void * PMAPI PM_getA0000Pointer(void) -{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); } - -void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) -{ return DPMI_mapPhysicalAddr(base,limit,isCached); } - -void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) -{ - /* Mapping cannot be free */ -} - -ulong PMAPI PM_getPhysicalAddr(void *p) -{ - /* TODO: This function should find the physical address of a linear */ - /* address. */ - (void)p; - return 0xFFFFFFFFUL; -} - -void * PMAPI PM_mapToProcess(void *base,ulong limit) -{ - (void)limit; - return (void*)base; -} - -void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) -{ - static uchar *zeroPtr = NULL; - - if (!zeroPtr) - zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); - return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); -} - -void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) -{ - PMREGS r; - void *p; - - r.x.ax = 0x100; /* DPMI allocate DOS memory */ - r.x.bx = (size + 0xF) >> 4; /* number of paragraphs */ - PM_int386(0x31, &r, &r); - if (r.x.cflag) - return NULL; /* DPMI call failed */ - *r_seg = r.x.ax; /* Real mode segment */ - *r_off = 0; - p = PM_mapRealPointer(*r_seg,*r_off); - _PM_addRealModeBlock(p,r.x.dx); - return p; -} - -void PMAPI PM_freeRealSeg(void *mem) -{ - PMREGS r; - - r.x.ax = 0x101; /* DPMI free DOS memory */ - r.x.dx = _PM_findRealModeBlock(mem);/* DX := selector from 0x100 */ - PM_int386(0x31, &r, &r); -} - -static DPMI_handler_t DPMI_int10 = NULL; - -void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler) -{ - DPMI_int10 = handler; -} - -void PMAPI DPMI_int86(int intno, DPMI_regs *regs) -{ - PMREGS r; - PMSREGS sr; - - if (intno == 0x10 && DPMI_int10) { - if (DPMI_int10(regs)) - return; - } - PM_segread(&sr); - r.x.ax = 0x300; /* DPMI issue real interrupt */ - r.h.bl = intno; - r.h.bh = 0; - r.x.cx = 0; - sr.es = sr.ds; - r.e.edi = (uint)regs; - PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ -} - -#define IN(reg) rmregs.reg = in->e.reg -#define OUT(reg) out->e.reg = rmregs.reg - -int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) -{ - DPMI_regs rmregs; - - memset(&rmregs, 0, sizeof(rmregs)); - IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); - -/* These real mode ints may cause crashes. */ -/*AM: DPMI_int86(intno,&rmregs); /###* DPMI issue real interrupt */ - - OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); - out->x.cflag = rmregs.flags & 0x1; - return out->x.ax; -} - -int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, - RMSREGS *sregs) -{ - DPMI_regs rmregs; - - memset(&rmregs, 0, sizeof(rmregs)); - IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); - rmregs.es = sregs->es; - rmregs.ds = sregs->ds; - -/*AM: DPMI_int86(intno,&rmregs); /###* DPMI issue real interrupt */ - - OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); - sregs->es = rmregs.es; - sregs->cs = rmregs.cs; - sregs->ss = rmregs.ss; - sregs->ds = rmregs.ds; - out->x.cflag = rmregs.flags & 0x1; - return out->x.ax; -} - -#pragma pack(1) - -typedef struct { - uint LargestBlockAvail; - uint MaxUnlockedPage; - uint LargestLockablePage; - uint LinAddrSpace; - uint NumFreePagesAvail; - uint NumPhysicalPagesFree; - uint TotalPhysicalPages; - uint FreeLinAddrSpace; - uint SizeOfPageFile; - uint res[3]; - } MemInfo; - -#pragma pack() - -void PMAPI PM_availableMemory(ulong *physical,ulong *total) -{ - PMREGS r; - PMSREGS sr; - MemInfo memInfo; - - PM_segread(&sr); - r.x.ax = 0x500; /* DPMI get free memory info */ - sr.es = sr.ds; - r.e.edi = (uint)&memInfo; - PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ - *physical = memInfo.NumPhysicalPagesFree * 4096; - *total = memInfo.LargestBlockAvail; - if (*total < *physical) - *physical = *total; -} - -/**************************************************************************** -REMARKS: -Function to get the file attributes for a specific file. -****************************************************************************/ -uint PMAPI PM_getFileAttr( - const char *filename) -{ - /* TODO: Implement this! */ - return 0; -} - -/**************************************************************************** -REMARKS: -Function to get the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_getFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* TODO: Implement this! */ - return false; -} - -/**************************************************************************** -REMARKS: -Function to set the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_setFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* TODO: Implement this! */ - return false; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c b/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c deleted file mode 100644 index 98e31bc..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c +++ /dev/null @@ -1,471 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit SMX embedded systems development -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include -#include -#include -#include -#include "smx/ps2mouse.h" - -/*--------------------------- Global variables ----------------------------*/ - -static int globalDataStart; - -PM_criticalHandler _VARAPI _PM_critHandler = NULL; -PM_breakHandler _VARAPI _PM_breakHandler = NULL; -PM_intHandler _VARAPI _PM_timerHandler = NULL; -PM_intHandler _VARAPI _PM_rtcHandler = NULL; -PM_intHandler _VARAPI _PM_keyHandler = NULL; -PM_key15Handler _VARAPI _PM_key15Handler = NULL; -PM_mouseHandler _VARAPI _PM_mouseHandler = NULL; -PM_intHandler _VARAPI _PM_int10Handler = NULL; -int _VARAPI _PM_mouseMask; - -uchar * _VARAPI _PM_ctrlCPtr; /* Location of Ctrl-C flag */ -uchar * _VARAPI _PM_ctrlBPtr; /* Location of Ctrl-Break flag */ -uchar * _VARAPI _PM_critPtr; /* Location of Critical error Bf*/ -PMFARPTR _VARAPI _PM_prevTimer = PMNULL; /* Previous timer handler */ -PMFARPTR _VARAPI _PM_prevRTC = PMNULL; /* Previous RTC handler */ -PMFARPTR _VARAPI _PM_prevKey = PMNULL; /* Previous key handler */ -PMFARPTR _VARAPI _PM_prevKey15 = PMNULL; /* Previous key15 handler */ -PMFARPTR _VARAPI _PM_prevBreak = PMNULL; /* Previous break handler */ -PMFARPTR _VARAPI _PM_prevCtrlC = PMNULL; /* Previous CtrlC handler */ -PMFARPTR _VARAPI _PM_prevCritical = PMNULL; /* Previous critical handler */ -long _VARAPI _PM_prevRealTimer; /* Previous real mode timer */ -long _VARAPI _PM_prevRealRTC; /* Previous real mode RTC */ -long _VARAPI _PM_prevRealKey; /* Previous real mode key */ -long _VARAPI _PM_prevRealKey15; /* Previous real mode key15 */ -long _VARAPI _PM_prevRealInt10; /* Previous real mode int 10h */ -static uchar _PM_oldCMOSRegA; /* CMOS register A contents */ -static uchar _PM_oldCMOSRegB; /* CMOS register B contents */ -static uchar _PM_oldRTCPIC2; /* Mask value for RTC IRQ8 */ - -/*----------------------------- Implementation ----------------------------*/ - -/* Globals for locking interrupt handlers in _pmsmx.asm */ - -extern int _ASMAPI _PM_pmsmxDataStart; -extern int _ASMAPI _PM_pmsmxDataEnd; -void _ASMAPI _PM_pmsmxCodeStart(void); -void _ASMAPI _PM_pmsmxCodeEnd(void); - -/* Protected mode interrupt handlers, also called by PM callbacks below */ - -void _ASMAPI _PM_timerISR(void); -void _ASMAPI _PM_rtcISR(void); -void _ASMAPI _PM_keyISR(void); -void _ASMAPI _PM_key15ISR(void); -void _ASMAPI _PM_breakISR(void); -void _ASMAPI _PM_ctrlCISR(void); -void _ASMAPI _PM_criticalISR(void); -void _ASMAPI _PM_mouseISR(void); -void _ASMAPI _PM_int10PMCB(void); - -/* Protected mode DPMI callback handlers */ - -void _ASMAPI _PM_mousePMCB(void); - -/* Routine to install a mouse handler function */ - -void _ASMAPI _PM_setMouseHandler(int mask); - -/* Routine to allocate DPMI real mode callback routines */ - -void _ASMAPI _DPMI_allocateCallback(void (_ASMAPI *pmcode)(),void *rmregs,long *RMCB); -void _ASMAPI _DPMI_freeCallback(long RMCB); - -/* DPMI helper functions in PMLITE.C */ - -ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit); -int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr); -ulong PMAPI DPMI_getSelectorBase(ushort sel); -int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit); -uint PMAPI DPMI_createSelector(ulong base,ulong limit); -void PMAPI DPMI_freeSelector(uint sel); -int PMAPI DPMI_lockLinearPages(ulong linear,ulong len); -int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len); - -/* Functions to read and write CMOS registers */ - -uchar PMAPI _PM_readCMOS(int index); -void PMAPI _PM_writeCMOS(int index,uchar value); - -/*-------------------------------------------------------------------------*/ -/* Generic routines common to all environments */ -/*-------------------------------------------------------------------------*/ - -void PMAPI PM_resetMouseDriver(int hardReset) -{ - ps2MouseReset(); -} - -void PMAPI PM_setRealTimeClockFrequency(int frequency) -{ - static short convert[] = { - 8192, - 4096, - 2048, - 1024, - 512, - 256, - 128, - 64, - 32, - 16, - 8, - 4, - 2, - -1, - }; - int i; - - /* First clear any pending RTC timeout if not cleared */ - _PM_readCMOS(0x0C); - if (frequency == 0) { - /* Disable RTC timout */ - _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); - _PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F); - } - else { - /* Convert frequency value to RTC clock indexes */ - for (i = 0; convert[i] != -1; i++) { - if (convert[i] == frequency) - break; - } - - /* Set RTC timout value and enable timeout */ - _PM_writeCMOS(0x0A,(_PM_oldCMOSRegA & 0xF0) | (i+3)); - _PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40); - } -} - -static void PMAPI lockPMHandlers(void) -{ - static int locked = 0; - int stat = 0; - PM_lockHandle lh; - - /* Lock all of the code and data used by our protected mode interrupt - * handling routines, so that it will continue to work correctly - * under real mode. - */ - if (!locked) { - PM_saveDS(); - stat = !PM_lockDataPages(&globalDataStart-2048,4096,&lh); - stat |= !PM_lockDataPages(&_PM_pmsmxDataStart,(int)&_PM_pmsmxDataEnd - (int)&_PM_pmsmxDataStart,&lh); - stat |= !PM_lockCodePages((__codePtr)_PM_pmsmxCodeStart,(int)_PM_pmsmxCodeEnd-(int)_PM_pmsmxCodeStart,&lh); - if (stat) { - printf("Page locking services failed - interrupt handling not safe!\n"); - exit(1); - } - locked = 1; - } -} - -void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) -{ - PMREGS regs; - - regs.x.ax = 0x204; - regs.h.bl = intno; - PM_int386(0x31,®s,®s); - isr->sel = regs.x.cx; - isr->off = regs.e.edx; -} - -void PMAPI PM_setPMvect(int intno, PM_intHandler isr) -{ - PMSREGS sregs; - PMREGS regs; - - PM_saveDS(); - regs.x.ax = 0x205; /* Set protected mode vector */ - regs.h.bl = intno; - PM_segread(&sregs); - regs.x.cx = sregs.cs; - regs.e.edx = (uint)isr; - PM_int386(0x31,®s,®s); -} - -void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) -{ - PMREGS regs; - - regs.x.ax = 0x205; - regs.h.bl = intno; - regs.x.cx = isr.sel; - regs.e.edx = isr.off; - PM_int386(0x31,®s,®s); -} - -static long prevRealBreak; /* Previous real mode break handler */ -static long prevRealCtrlC; /* Previous real mode CtrlC handler */ -static long prevRealCritical; /* Prev real mode critical handler */ - -int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) -{ - lockPMHandlers(); /* Ensure our handlers are locked */ - - _PM_mouseHandler = mh; - return 0; -} - -void PMAPI PM_restoreMouseHandler(void) -{ - if (_PM_mouseHandler) - _PM_mouseHandler = NULL; -} - -static void getISR(int intno, PMFARPTR *pmisr, long *realisr) -{ - PM_getPMvect(intno,pmisr); -} - -static void restoreISR(int intno, PMFARPTR pmisr, long realisr) -{ - PM_restorePMvect(intno,pmisr); -} - -static void setISR(int intno, void (* PMAPI pmisr)()) -{ - lockPMHandlers(); /* Ensure our handlers are locked */ - PM_setPMvect(intno,pmisr); -} - -void PMAPI PM_setTimerHandler(PM_intHandler th) -{ - getISR(PM_IRQ0, &_PM_prevTimer, &_PM_prevRealTimer); - _PM_timerHandler = th; - setISR(PM_IRQ0, _PM_timerISR); -} - -void PMAPI PM_restoreTimerHandler(void) -{ - if (_PM_timerHandler) { - restoreISR(PM_IRQ0, _PM_prevTimer, _PM_prevRealTimer); - _PM_timerHandler = NULL; - } -} - -ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) -{ - /* Save the old CMOS real time clock values */ - _PM_oldCMOSRegA = _PM_readCMOS(0x0A); - _PM_oldCMOSRegB = _PM_readCMOS(0x0B); - - /* Set the real time clock interrupt handler */ - getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); - _PM_rtcHandler = th; - setISR(0x70, _PM_rtcISR); - - /* Program the real time clock default frequency */ - PM_setRealTimeClockFrequency(frequency); - - /* Unmask IRQ8 in the PIC2 */ - _PM_oldRTCPIC2 = PM_inpb(0xA1); - PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); - return true; -} - -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - if (_PM_rtcHandler) { - /* Restore CMOS registers and mask RTC clock */ - _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); - _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); - PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); - - /* Restore the interrupt vector */ - restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); - _PM_rtcHandler = NULL; - } -} - -void PMAPI PM_setKeyHandler(PM_intHandler kh) -{ - getISR(PM_IRQ1, &_PM_prevKey, &_PM_prevRealKey); - _PM_keyHandler = kh; - setISR(PM_IRQ1, _PM_keyISR); -} - -void PMAPI PM_restoreKeyHandler(void) -{ - if (_PM_keyHandler) { - restoreISR(PM_IRQ1, _PM_prevKey, _PM_prevRealKey); - _PM_keyHandler = NULL; - } -} - -void PMAPI PM_setKey15Handler(PM_key15Handler kh) -{ - getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); - _PM_key15Handler = kh; - setISR(0x15, _PM_key15ISR); -} - -void PMAPI PM_restoreKey15Handler(void) -{ - if (_PM_key15Handler) { - restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); - _PM_key15Handler = NULL; - } -} - -/* Real mode Ctrl-C and Ctrl-Break handler. This handler simply sets a - * flag in the real mode code segment and exit. We save the location - * of this flag in real mode memory so that both the real mode and - * protected mode code will be modifying the same flags. - */ - -static uchar ctrlHandler[] = { - 0x00,0x00,0x00,0x00, /* ctrlBFlag */ - 0x66,0x2E,0xC7,0x06,0x00,0x00, - 0x01,0x00,0x00,0x00, /* mov [cs:ctrlBFlag],1 */ - 0xCF, /* iretf */ - }; - -void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) -{ - uint rseg,roff; - - getISR(0x1B, &_PM_prevBreak, &prevRealBreak); - getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); - _PM_breakHandler = bh; - setISR(0x1B, _PM_breakISR); - setISR(0x23, _PM_ctrlCISR); - - /* Hook the real mode vectors for these handlers, as these are not - * normally reflected by the DPMI server up to protected mode - */ - _PM_ctrlBPtr = PM_allocRealSeg(sizeof(ctrlHandler)*2, &rseg, &roff); - memcpy(_PM_ctrlBPtr,ctrlHandler,sizeof(ctrlHandler)); - memcpy(_PM_ctrlBPtr+sizeof(ctrlHandler),ctrlHandler,sizeof(ctrlHandler)); - _PM_ctrlCPtr = _PM_ctrlBPtr + sizeof(ctrlHandler); - _PM_setRMvect(0x1B,((long)rseg << 16) | (roff+4)); - _PM_setRMvect(0x23,((long)rseg << 16) | (roff+sizeof(ctrlHandler)+4)); -} - -void PMAPI PM_installBreakHandler(void) -{ - PM_installAltBreakHandler(NULL); -} - -void PMAPI PM_restoreBreakHandler(void) -{ - if (_PM_prevBreak.sel) { - restoreISR(0x1B, _PM_prevBreak, prevRealBreak); - restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); - _PM_prevBreak.sel = 0; - _PM_breakHandler = NULL; - PM_freeRealSeg(_PM_ctrlBPtr); - } -} - -/* Real mode Critical Error handler. This handler simply saves the AX and - * DI values in the real mode code segment and exits. We save the location - * of this flag in real mode memory so that both the real mode and - * protected mode code will be modifying the same flags. - */ - -static uchar criticalHandler[] = { - 0x00,0x00, /* axCode */ - 0x00,0x00, /* diCode */ - 0x2E,0xA3,0x00,0x00, /* mov [cs:axCode],ax */ - 0x2E,0x89,0x3E,0x02,0x00, /* mov [cs:diCode],di */ - 0xB8,0x03,0x00, /* mov ax,3 */ - 0xCF, /* iretf */ - }; - -void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) -{ - uint rseg,roff; - - getISR(0x24, &_PM_prevCritical, &prevRealCritical); - _PM_critHandler = ch; - setISR(0x24, _PM_criticalISR); - - /* Hook the real mode vector, as this is not normally reflected by the - * DPMI server up to protected mode. - */ - _PM_critPtr = PM_allocRealSeg(sizeof(criticalHandler)*2, &rseg, &roff); - memcpy(_PM_critPtr,criticalHandler,sizeof(criticalHandler)); - _PM_setRMvect(0x24,((long)rseg << 16) | (roff+4)); -} - -void PMAPI PM_installCriticalHandler(void) -{ - PM_installAltCriticalHandler(NULL); -} - -void PMAPI PM_restoreCriticalHandler(void) -{ - if (_PM_prevCritical.sel) { - restoreISR(0x24, _PM_prevCritical, prevRealCritical); - PM_freeRealSeg(_PM_critPtr); - _PM_prevCritical.sel = 0; - _PM_critHandler = NULL; - } -} - -int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - PMSREGS sregs; - PM_segread(&sregs); - return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); -} - -int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - PMSREGS sregs; - PM_segread(&sregs); - return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); -} - -int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - PMSREGS sregs; - PM_segread(&sregs); -/*AM: causes minor glitch with */ -/*AM: older versions pmEasy which don't allow DPMI 06 on */ -/*AM: Code selector 0x0C -- assume base is 0 which it should be. */ - return DPMI_lockLinearPages((uint)p,len); -} - -int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - PMSREGS sregs; - PM_segread(&sregs); - return DPMI_unlockLinearPages((uint)p,len); -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c deleted file mode 100644 index 579ef2c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Dummy module; no virtual framebuffer for this OS -* -****************************************************************************/ - -#include "pmapi.h" - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -{ - baseAddr = baseAddr; - bankSize = bankSize; - codeLen = codeLen; - bankFunc = bankFunc; - return NULL; -} - -void PMAPI VF_exit(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c deleted file mode 100644 index 7941192..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit SMX embedded systems development -* -* Description: OS specific implementation for the Zen Timer functions. -* LZTimer not supported for smx (as needed for i486 processors), only -* ULZTimer is supported at this time. -* -****************************************************************************/ - -/*---------------------------- Global smx variables -----------------------*/ - -extern ulong _cdecl etime; /* elapsed time */ -extern ulong _cdecl xticks_per_second(void); - -/*----------------------------- Implementation ----------------------------*/ - -/* External assembler functions */ - -void _ASMAPI LZ_disable(void); -void _ASMAPI LZ_enable(void); - - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -void __ZTimerInit(void) -{ -} - -ulong reterr(void) -{ - PM_fatalError("Zen Timer not supported for smx."); - return(0); -} - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerOn(tm) PM_fatalError("Zen Timer not supported for smx.") - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerLap(tm) reterr() - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerOff(tm) PM_fatalError("Zen Timer not supported for smx.") - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerCount(tm) reterr() - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as seconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION (ulong)(1000000/xticks_per_second()) - -/**************************************************************************** -REMARKS: -Read the Long Period timer value from the smx timer tick. -****************************************************************************/ -static ulong __ULZReadTime(void) -{ - ulong ticks; - LZ_disable(); /* Turn of interrupts */ - ticks = etime; - LZ_enable(); /* Turn on interrupts again */ - return ticks; -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong __ULZElapsedTime(ulong start,ulong finish) -{ - if (finish < start) - finish += xticks_per_second() * 3600 *24; /* Number of ticks in 24 hours */ - return finish - start; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c deleted file mode 100644 index 0615e90..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** -* -* Description: Module to implement OS specific services to measure the -* CPU frequency. -* -****************************************************************************/ - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Increase the thread priority to maximum, if possible. -****************************************************************************/ -static int SetMaxThreadPriority(void) -{ - /* TODO: If you have thread priorities, increase it to maximum for the */ - /* thread for timing the CPU frequency. */ - return oldPriority; -} - -/**************************************************************************** -REMARKS: -Restore the original thread priority. -****************************************************************************/ -static void RestoreThreadPriority( - int priority) -{ - /* TODO: Restore the original thread priority on exit. */ -} - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - /* TODO: Return the frequency of the counter in here. You should try to */ - /* normalise this value to be around 100,000 ticks per second. */ - freq->low = 0; - freq->high = 0; -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. - -TODO: Implement this to read the counter. It should be done as a macro - for accuracy. -****************************************************************************/ -#define GetCounter(t) \ -{ \ - (t)->low = 0; \ - (t)->high = 0; \ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/event.c b/board/MAI/bios_emulator/scitech/src/pm/stub/event.c deleted file mode 100644 index 204c492..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/stub/event.c +++ /dev/null @@ -1,199 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** -* -* Description: **** implementation for the SciTech cross platform -* event library. -* -****************************************************************************/ - -/*---------------------------- Global Variables ---------------------------*/ - -static ushort keyUpMsg[256] = {0};/* Table of key up messages */ -static int rangeX,rangeY; /* Range of mouse coordinates */ - -/*---------------------------- Implementation -----------------------------*/ - -/* These are not used under non-DOS systems */ -#define _EVT_disableInt() 1 -#define _EVT_restoreInt(flags) - -/**************************************************************************** -PARAMETERS: -scanCode - Scan code to test - -REMARKS: -This macro determines if a specified key is currently down at the -time that the call is made. -****************************************************************************/ -#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) - -/**************************************************************************** -REMARKS: -This function is used to return the number of ticks since system -startup in milliseconds. This should be the same value that is placed into -the time stamp fields of events, and is used to implement auto mouse down -events. -****************************************************************************/ -ulong _EVT_getTicks(void) -{ - /* TODO: Implement this for your OS! */ -} - -/**************************************************************************** -REMARKS: -Pumps all messages in the application message queue into our event queue. -****************************************************************************/ -static void _EVT_pumpMessages(void) -{ - /* TODO: The purpose of this function is to read all keyboard and mouse */ - /* events from the OS specific event queue, translate them and post */ - /* them into the SciTech event queue. */ - /* */ - /* NOTE: There are a couple of important things that this function must */ - /* take care of: */ - /* */ - /* 1. Support for KEYDOWN, KEYREPEAT and KEYUP is required. */ - /* */ - /* 2. Support for reading hardware scan code as well as ASCII */ - /* translated values is required. Games use the scan codes rather */ - /* than ASCII values. Scan codes go into the high order byte of the */ - /* keyboard message field. */ - /* */ - /* 3. Support for at least reading mouse motion data (mickeys) from the */ - /* mouse is required. Using the mickey values, we can then translate */ - /* to mouse cursor coordinates scaled to the range of the current */ - /* graphics display mode. Mouse values are scaled based on the */ - /* global 'rangeX' and 'rangeY'. */ - /* */ - /* 4. Support for a timestamp for the events is required, which is */ - /* defined as the number of milliseconds since some event (usually */ - /* system startup). This is the timestamp when the event occurred */ - /* (ie: at interrupt time) not when it was stuff into the SciTech */ - /* event queue. */ - /* */ - /* 5. Support for mouse double click events. If the OS has a native */ - /* mechanism to determine this, it should be used. Otherwise the */ - /* time stamp information will be used by the generic event code */ - /* to generate double click events. */ -} - -/**************************************************************************** -REMARKS: -This macro/function is used to converts the scan codes reported by the -keyboard to our event libraries normalised format. We only have one scan -code for the 'A' key, and use shift modifiers to determine if it is a -Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, -but the OS gives us 'cooked' scan codes, we have to translate them back -to the raw format. -****************************************************************************/ -#define _EVT_maskKeyCode(evt) - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _EVT_abort() -{ - EVT_exit(); - PM_fatalError("Unhandled exception!"); -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -void EVTAPI EVT_init( - _EVT_mouseMoveHandler mouseMove) -{ - /* Initialise the event queue */ - _mouseMove = mouseMove; - initEventQueue(); - memset(keyUpMsg,0,sizeof(keyUpMsg)); - - /* TODO: Do any OS specific initialisation here */ - - /* Catch program termination signals so we can clean up properly */ - signal(SIGABRT, _EVT_abort); - signal(SIGFPE, _EVT_abort); - signal(SIGINT, _EVT_abort); -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - rangeX = xRes; - rangeY = yRes; -} - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVT_resume(void) -{ - /* Do nothing for non DOS systems */ -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVT_suspend(void) -{ - /* Do nothing for non DOS systems */ -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVT_exit(void) -{ - /* Restore signal handlers */ - signal(SIGABRT, SIG_DFL); - signal(SIGFPE, SIG_DFL); - signal(SIGINT, SIG_DFL); - - /* TODO: Do any OS specific cleanup in here */ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h deleted file mode 100644 index 1395cbc..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h +++ /dev/null @@ -1,33 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: BeOS -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ - -/* TODO: This is where you include OS specific headers for the event handling */ -/* library. You may leave this empty if you have no OS specific headers */ -/* to include. */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c b/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c deleted file mode 100644 index 5f278c3..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c +++ /dev/null @@ -1,980 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include -#include -#include - -/* TODO: Include any OS specific headers here! */ - -/*--------------------------- Global variables ----------------------------*/ - -/* TODO: If you support access to the BIOS, the following VESABuf globals */ -/* keep track of a single VESA transfer buffer. If you don't support */ -/* access to the BIOS, remove these variables. */ - -static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ -static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ -static uint VESABuf_rseg; /* Real mode segment of VESABuf */ -static uint VESABuf_roff; /* Real mode offset of VESABuf */ - -static void (PMAPIP fatalErrorCleanup)(void) = NULL; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the PM library. -****************************************************************************/ -void PMAPI PM_init(void) -{ - /* TODO: Do any initialisation in here. This includes getting IOPL */ - /* access for the process calling PM_init. This will get called */ - /* more than once. */ - - /* TODO: If you support the supplied MTRR register stuff (you need to */ - /* be at ring 0 for this!), you should initialise it in here. */ - -/* MTRR_init(); */ -} - -/**************************************************************************** -REMARKS: -Return the operating system type identifier. -****************************************************************************/ -long PMAPI PM_getOSType(void) -{ - /* TODO: Change this to return the define for your OS from drvlib/os.h */ - return _OS_MYOS; -} - -/**************************************************************************** -REMARKS: -Return the runtime type identifier (always PM_386 for protected mode) -****************************************************************************/ -int PMAPI PM_getModeType(void) -{ return PM_386; } - -/**************************************************************************** -REMARKS: -Add a file directory separator to the end of the filename. -****************************************************************************/ -void PMAPI PM_backslash( - char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '/') { - s[pos] = '/'; - s[pos+1] = '\0'; - } -} - -/**************************************************************************** -REMARKS: -Add a user defined PM_fatalError cleanup function. -****************************************************************************/ -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -/**************************************************************************** -REMARKS: -Report a fatal error condition and halt the program. -****************************************************************************/ -void PMAPI PM_fatalError( - const char *msg) -{ - /* TODO: If you are running in a GUI environment without a console, */ - /* this needs to be changed to bring up a fatal error message */ - /* box and terminate the program. */ - if (fatalErrorCleanup) - fatalErrorCleanup(); - fprintf(stderr,"%s\n", msg); - exit(1); -} - -/**************************************************************************** -REMARKS: -Exit handler to kill the VESA transfer buffer. -****************************************************************************/ -static void ExitVBEBuf(void) -{ - /* TODO: If you do not have BIOS access, remove this function. */ - if (VESABuf_ptr) - PM_freeRealSeg(VESABuf_ptr); - VESABuf_ptr = 0; -} - -/**************************************************************************** -REMARKS: -Allocate the real mode VESA transfer buffer for communicating with the BIOS. -****************************************************************************/ -void * PMAPI PM_getVESABuf( - uint *len, - uint *rseg, - uint *roff) -{ - /* TODO: If you do not have BIOS access, simply delete the guts of */ - /* this function and return NULL. */ - if (!VESABuf_ptr) { - /* Allocate a global buffer for communicating with the VESA VBE */ - if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) - return NULL; - atexit(ExitVBEBuf); - } - *len = VESABuf_len; - *rseg = VESABuf_rseg; - *roff = VESABuf_roff; - return VESABuf_ptr; -} - -/**************************************************************************** -REMARKS: -Check if a key has been pressed. -****************************************************************************/ -int PMAPI PM_kbhit(void) -{ - /* TODO: This function checks if a key is available to be read. This */ - /* should be implemented, but is mostly used by the test programs */ - /* these days. */ - return true; -} - -/**************************************************************************** -REMARKS: -Wait for and return the next keypress. -****************************************************************************/ -int PMAPI PM_getch(void) -{ - /* TODO: This returns the ASCII code of the key pressed. This */ - /* should be implemented, but is mostly used by the test programs */ - /* these days. */ - return 0xD; -} - -/**************************************************************************** -REMARKS: -Open a fullscreen console mode for output. -****************************************************************************/ -int PMAPI PM_openConsole(void) -{ - /* TODO: Opens up a fullscreen console for graphics output. If your */ - /* console does not have graphics/text modes, this can be left */ - /* empty. The main purpose of this is to disable console switching */ - /* when in graphics modes if you can switch away from fullscreen */ - /* consoles (if you want to allow switching, this can be done */ - /* elsewhere with a full save/restore state of the graphics mode). */ - return 0; -} - -/**************************************************************************** -REMARKS: -Return the size of the state buffer used to save the console state. -****************************************************************************/ -int PMAPI PM_getConsoleStateSize(void) -{ - /* TODO: Returns the size of the console state buffer used to save the */ - /* state of the console before going into graphics mode. This is */ - /* used to restore the console back to normal when we are done. */ - return 1; -} - -/**************************************************************************** -REMARKS: -Save the state of the console into the state buffer. -****************************************************************************/ -void PMAPI PM_saveConsoleState( - void *stateBuf, - int console_id) -{ - /* TODO: Saves the state of the console into the state buffer. This is */ - /* used to restore the console back to normal when we are done. */ - /* We will always restore 80x25 text mode after being in graphics */ - /* mode, so if restoring text mode is all you need to do this can */ - /* be left empty. */ -} - -/**************************************************************************** -REMARKS: -Restore the state of the console from the state buffer. -****************************************************************************/ -void PMAPI PM_restoreConsoleState( - const void *stateBuf, - int console_id) -{ - /* TODO: Restore the state of the console from the state buffer. This is */ - /* used to restore the console back to normal when we are done. */ - /* We will always restore 80x25 text mode after being in graphics */ - /* mode, so if restoring text mode is all you need to do this can */ - /* be left empty. */ -} - -/**************************************************************************** -REMARKS: -Close the console and return to non-fullscreen console mode. -****************************************************************************/ -void PMAPI PM_closeConsole( - int console_id) -{ - /* TODO: Close the console when we are done, going back to text mode. */ -} - -/**************************************************************************** -REMARKS: -Set the location of the OS console cursor. -****************************************************************************/ -void PM_setOSCursorLocation( - int x, - int y) -{ - /* TODO: Set the OS console cursor location to the new value. This is */ - /* generally used for new OS ports (used mostly for DOS). */ -} - -/**************************************************************************** -REMARKS: -Set the width of the OS console. -****************************************************************************/ -void PM_setOSScreenWidth( - int width, - int height) -{ - /* TODO: Set the OS console screen width. This is generally unused for */ - /* new OS ports. */ -} - -/**************************************************************************** -REMARKS: -Set the real time clock handler (used for software stereo modes). -****************************************************************************/ -ibool PMAPI PM_setRealTimeClockHandler( - PM_intHandler ih, - int frequency) -{ - /* TODO: Install a real time clock interrupt handler. Normally this */ - /* will not be supported from most OS'es in user land, so an */ - /* alternative mechanism is needed to enable software stereo. */ - /* Hence leave this unimplemented unless you have a high priority */ - /* mechanism to call the 32-bit callback when the real time clock */ - /* interrupt fires. */ - return false; -} - -/**************************************************************************** -REMARKS: -Set the real time clock frequency (for stereo modes). -****************************************************************************/ -void PMAPI PM_setRealTimeClockFrequency( - int frequency) -{ - /* TODO: Set the real time clock interrupt frequency. Used for stereo */ - /* LC shutter glasses when doing software stereo. Usually sets */ - /* the frequency to around 2048 Hz. */ -} - -/**************************************************************************** -REMARKS: -Restore the original real time clock handler. -****************************************************************************/ -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - /* TODO: Restores the real time clock handler. */ -} - -/**************************************************************************** -REMARKS: -Return the current operating system path or working directory. -****************************************************************************/ -char * PMAPI PM_getCurrentPath( - char *path, - int maxLen) -{ - return getcwd(path,maxLen); -} - -/**************************************************************************** -REMARKS: -Return the drive letter for the boot drive. -****************************************************************************/ -char PMAPI PM_getBootDrive(void) -{ - /* TODO: Return the boot drive letter for the OS. Normally this is 'c' */ - /* for DOS based OS'es and '/' for Unices. */ - return '/'; -} - -/**************************************************************************** -REMARKS: -Return the path to the VBE/AF driver files (legacy and not used). -****************************************************************************/ -const char * PMAPI PM_getVBEAFPath(void) -{ - return PM_getNucleusConfigPath(); -} - -/**************************************************************************** -REMARKS: -Return the path to the Nucleus driver files. -****************************************************************************/ -const char * PMAPI PM_getNucleusPath(void) -{ - /* TODO: Change this to the default path to Nucleus driver files. The */ - /* following is the default for Unices. */ - char *env = getenv("NUCLEUS_PATH"); - return env ? env : "/usr/lib/nucleus"; -} - -/**************************************************************************** -REMARKS: -Return the path to the Nucleus configuration files. -****************************************************************************/ -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[256]; - strcpy(path,PM_getNucleusPath()); - PM_backslash(path); - strcat(path,"config"); - return path; -} - -/**************************************************************************** -REMARKS: -Return a unique identifier for the machine if possible. -****************************************************************************/ -const char * PMAPI PM_getUniqueID(void) -{ - /* TODO: Return a unique ID for the machine. If a unique ID is not */ - /* available, return the machine name. */ - static char buf[128]; - gethostname(buf, 128); - return buf; -} - -/**************************************************************************** -REMARKS: -Get the name of the machine on the network. -****************************************************************************/ -const char * PMAPI PM_getMachineName(void) -{ - /* TODO: Return the network machine name for the machine. */ - static char buf[128]; - gethostname(buf, 128); - return buf; -} - -/**************************************************************************** -REMARKS: -Return a pointer to the real mode BIOS data area. -****************************************************************************/ -void * PMAPI PM_getBIOSPointer(void) -{ - /* TODO: This returns a pointer to the real mode BIOS data area. If you */ - /* do not support BIOS access, you can simply return NULL here. */ - if (!zeroPtr) - zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); - return (void*)(zeroPtr + 0x400); -} - -/**************************************************************************** -REMARKS: -Return a pointer to 0xA0000 physical VGA graphics framebuffer. -****************************************************************************/ -void * PMAPI PM_getA0000Pointer(void) -{ - static void *bankPtr; - if (!bankPtr) - bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); - return bankPtr; -} - -/**************************************************************************** -REMARKS: -Map a physical address to a linear address in the callers process. -****************************************************************************/ -void * PMAPI PM_mapPhysicalAddr( - ulong base, - ulong limit, - ibool isCached) -{ - /* TODO: This function maps a physical memory address to a linear */ - /* address in the address space of the calling process. */ - - /* NOTE: This function *must* be able to handle any phsyical base */ - /* address, and hence you will have to handle rounding of */ - /* the physical base address to a page boundary (ie: 4Kb on */ - /* x86 CPU's) to be able to properly map in the memory */ - /* region. */ - - /* NOTE: If possible the isCached bit should be used to ensure that */ - /* the PCD (Page Cache Disable) and PWT (Page Write Through) */ - /* bits are set to disable caching for a memory mapping used */ - /* for MMIO register access. We also disable caching using */ - /* the MTRR registers for Pentium Pro and later chipsets so if */ - /* MTRR support is enabled for your OS then you can safely ignore */ - /* the isCached flag and always enable caching in the page */ - /* tables. */ - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a physical address mapping allocated by PM_mapPhysicalAddr. -****************************************************************************/ -void PMAPI PM_freePhysicalAddr( - void *ptr, - ulong limit) -{ - /* TODO: This function will free a physical memory mapping previously */ - /* allocated with PM_mapPhysicalAddr() if at all possible. If */ - /* you can't free physical memory mappings, simply do nothing. */ -} - -/**************************************************************************** -REMARKS: -Find the physical address of a linear memory address in current process. -****************************************************************************/ -ulong PMAPI PM_getPhysicalAddr(void *p) -{ - /* TODO: This function should find the physical address of a linear */ - /* address. */ - return 0xFFFFFFFFUL; -} - -void PMAPI PM_sleep(ulong milliseconds) -{ - /* TODO: Put the process to sleep for milliseconds */ -} - -int PMAPI PM_getCOMPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - } - return 0; -} - -int PMAPI PM_getLPTPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -/**************************************************************************** -REMARKS: -Allocate a block of (unnamed) shared memory. -****************************************************************************/ -void * PMAPI PM_mallocShared( - long size) -{ - /* TODO: This is used to allocate memory that is shared between process */ - /* that all access the common Nucleus drivers via a common display */ - /* driver DLL. If your OS does not support shared memory (or if */ - /* the display driver does not need to allocate shared memory */ - /* for each process address space), this should just call PM_malloc. */ - return PM_malloc(size); -} - -/**************************************************************************** -REMARKS: -Free a block of shared memory. -****************************************************************************/ -void PMAPI PM_freeShared( - void *ptr) -{ - /* TODO: Free the shared memory block. This will be called in the context */ - /* of the original calling process that allocated the shared */ - /* memory with PM_mallocShared. Simply call PM_free if you do not */ - /* need this. */ - PM_free(ptr); -} - -/**************************************************************************** -REMARKS: -Map a linear memory address to the calling process address space. The -address will have been allocated in another process using the -PM_mapPhysicalAddr function. -****************************************************************************/ -void * PMAPI PM_mapToProcess( - void *base, - ulong limit) -{ - /* TODO: This function is used to map a physical memory mapping */ - /* previously allocated with PM_mapPhysicalAddr into the */ - /* address space of the calling process. If the memory mapping */ - /* allocated by PM_mapPhysicalAddr is global to all processes, */ - /* simply return the pointer. */ - - /* NOTE: This function must also handle rounding to page boundaries, */ - /* since this function is used to map in shared memory buffers */ - /* allocated with PM_mapPhysicalAddr(). Hence if you aligned */ - /* the physical address above, then you also need to do it here. */ - return base; -} - -/**************************************************************************** -REMARKS: -Map a real mode pointer to a protected mode pointer. -****************************************************************************/ -void * PMAPI PM_mapRealPointer( - uint r_seg, - uint r_off) -{ - /* TODO: This function maps a real mode memory pointer into the */ - /* calling processes address space as a 32-bit near pointer. If */ - /* you do not support BIOS access, simply return NULL here. */ - if (!zeroPtr) - zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF); - return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); -} - -/**************************************************************************** -REMARKS: -Allocate a block of real mode memory -****************************************************************************/ -void * PMAPI PM_allocRealSeg( - uint size, - uint *r_seg, - uint *r_off) -{ - /* TODO: This function allocates a block of real mode memory for the */ - /* calling process used to communicate with real mode BIOS */ - /* functions. If you do not support BIOS access, simply return */ - /* NULL here. */ - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a block of real mode memory. -****************************************************************************/ -void PMAPI PM_freeRealSeg( - void *mem) -{ - /* TODO: Frees a previously allocated real mode memory block. If you */ - /* do not support BIOS access, this function should be empty. */ -} - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt (parameters in DPMI compatible structure) -****************************************************************************/ -void PMAPI DPMI_int86( - int intno, - DPMI_regs *regs) -{ - /* TODO: This function calls the real mode BIOS using the passed in */ - /* register structure. If you do not support real mode BIOS */ - /* access, this function should be empty. */ -} - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt. -****************************************************************************/ -int PMAPI PM_int86( - int intno, - RMREGS *in, - RMREGS *out) -{ - /* TODO: This function calls the real mode BIOS using the passed in */ - /* register structure. If you do not support real mode BIOS */ - /* access, this function should return 0. */ - return 0; -} - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt. -****************************************************************************/ -int PMAPI PM_int86x( - int intno, - RMREGS *in, - RMREGS *out, - RMSREGS *sregs) -{ - /* TODO: This function calls the real mode BIOS using the passed in */ - /* register structure. If you do not support real mode BIOS */ - /* access, this function should return 0. */ - return 0; -} - -/**************************************************************************** -REMARKS: -Call a real mode far function. -****************************************************************************/ -void PMAPI PM_callRealMode( - uint seg, - uint off, - RMREGS *in, - RMSREGS *sregs) -{ - /* TODO: This function calls a real mode far function with a far call. */ - /* If you do not support BIOS access, this function should be */ - /* empty. */ -} - -/**************************************************************************** -REMARKS: -Return the amount of available memory. -****************************************************************************/ -void PMAPI PM_availableMemory( - ulong *physical, - ulong *total) -{ - /* TODO: Report the amount of available memory, both the amount of */ - /* physical memory left and the amount of virtual memory left. */ - /* If the OS does not provide these services, report 0's. */ - *physical = *total = 0; -} - -/**************************************************************************** -REMARKS: -Allocate a block of locked, physical memory for DMA operations. -****************************************************************************/ -void * PMAPI PM_allocLockedMem( - uint size, - ulong *physAddr, - ibool contiguous, - ibool below16M) -{ - /* TODO: Allocate a block of locked, physical memory of the specified */ - /* size. This is used for bus master operations. If this is not */ - /* supported by the OS, return NULL and bus mastering will not */ - /* be used. */ - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a block of locked physical memory. -****************************************************************************/ -void PMAPI PM_freeLockedMem( - void *p, - uint size, - ibool contiguous) -{ - /* TODO: Free a memory block allocated with PM_allocLockedMem. */ -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display banks. -****************************************************************************/ -void PMAPI PM_setBankA( - int bank) -{ - RMREGS regs; - - /* TODO: This does a bank switch function by calling the real mode */ - /* VESA BIOS. If you do not support BIOS access, this function should */ - /* be empty. */ - regs.x.ax = 0x4F05; - regs.x.bx = 0x0000; - regs.x.dx = bank; - PM_int86(0x10,®s,®s); -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display banks. -****************************************************************************/ -void PMAPI PM_setBankAB( - int bank) -{ - RMREGS regs; - - /* TODO: This does a bank switch function by calling the real mode */ - /* VESA BIOS. If you do not support BIOS access, this function should */ - /* be empty. */ - regs.x.ax = 0x4F05; - regs.x.bx = 0x0000; - regs.x.dx = bank; - PM_int86(0x10,®s,®s); - regs.x.ax = 0x4F05; - regs.x.bx = 0x0001; - regs.x.dx = bank; - PM_int86(0x10,®s,®s); -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display start address. -****************************************************************************/ -void PMAPI PM_setCRTStart( - int x, - int y, - int waitVRT) -{ - RMREGS regs; - - /* TODO: This changes the display start address by calling the real mode */ - /* VESA BIOS. If you do not support BIOS access, this function */ - /* should be empty. */ - regs.x.ax = 0x4F07; - regs.x.bx = waitVRT; - regs.x.cx = x; - regs.x.dx = y; - PM_int86(0x10,®s,®s); -} - -/**************************************************************************** -REMARKS: -Enable write combining for the memory region. -****************************************************************************/ -ibool PMAPI PM_enableWriteCombine( - ulong base, - ulong length, - uint type) -{ - /* TODO: This function should enable Pentium Pro and Pentium II MTRR */ - /* write combining for the passed in physical memory base address */ - /* and length. Normally this is done via calls to an OS specific */ - /* device driver as this can only be done at ring 0. */ - /* */ - /* NOTE: This is a *very* important function to implement! If you do */ - /* not implement, graphics performance on the latest Intel chips */ - /* will be severly impaired. For sample code that can be used */ - /* directly in a ring 0 device driver, see the MSDOS implementation */ - /* which includes assembler code to do this directly (if the */ - /* program is running at ring 0). */ - return false; -} - -/**************************************************************************** -REMARKS: -Execute the POST on the secondary BIOS for a controller. -****************************************************************************/ -ibool PMAPI PM_doBIOSPOST( - ushort axVal, - ulong BIOSPhysAddr, - void *mappedBIOS) -{ - /* TODO: This function is used to run the BIOS POST code on a secondary */ - /* controller to initialise it for use. This is not necessary */ - /* for multi-controller operation, but it will make it a lot */ - /* more convenicent for end users (otherwise they have to boot */ - /* the system once with the secondary controller as primary, and */ - /* then boot with both controllers installed). */ - /* */ - /* Even if you don't support full BIOS access, it would be */ - /* adviseable to be able to POST the secondary controllers in the */ - /* system using this function as a minimum requirement. Some */ - /* graphics hardware has registers that contain values that only */ - /* the BIOS knows about, which makes bring up a card from cold */ - /* reset difficult if the BIOS has not POST'ed it. */ - return false; -} - -/**************************************************************************** -REMARKS: -Load an OS specific shared library or DLL. If the OS does not support -shared libraries, simply return NULL. -****************************************************************************/ -PM_MODULE PMAPI PM_loadLibrary( - const char *szDLLName) -{ - /* TODO: This function should load a native shared library from disk */ - /* given the path to the library. */ - (void)szDLLName; - return NULL; -} - -/**************************************************************************** -REMARKS: -Get the address of a named procedure from a shared library. -****************************************************************************/ -void * PMAPI PM_getProcAddress( - PM_MODULE hModule, - const char *szProcName) -{ - /* TODO: This function should return the address of a named procedure */ - /* from a native shared library. */ - (void)hModule; - (void)szProcName; - return NULL; -} - -/**************************************************************************** -REMARKS: -Unload a shared library. -****************************************************************************/ -void PMAPI PM_freeLibrary( - PM_MODULE hModule) -{ - /* TODO: This function free a previously loaded native shared library. */ - (void)hModule; -} - -/**************************************************************************** -REMARKS: -Enable requested I/O privledge level (usually only to set to a value of -3, and then restore it back again). If the OS is protected this function -must be implemented in order to enable I/O port access for ring 3 -applications. The function should return the IOPL level active before -the switch occurred so it can be properly restored. -****************************************************************************/ -int PMAPI PM_setIOPL( - int level) -{ - /* TODO: This function should enable IOPL for the task (if IOPL is */ - /* not always enabled for the app through some other means). */ - return level; -} - -/**************************************************************************** -REMARKS: -Function to find the first file matching a search criteria in a directory. -****************************************************************************/ -void *PMAPI PM_findFirstFile( - const char *filename, - PM_findData *findData) -{ - /* TODO: This function should start a directory enumeration search */ - /* given the filename (with wildcards). The data should be */ - /* converted and returned in the findData standard form. */ - (void)filename; - (void)findData; - return PM_FILE_INVALID; -} - -/**************************************************************************** -REMARKS: -Function to find the next file matching a search criteria in a directory. -****************************************************************************/ -ibool PMAPI PM_findNextFile( - void *handle, - PM_findData *findData) -{ - /* TODO: This function should find the next file in directory enumeration */ - /* search given the search criteria defined in the call to */ - /* PM_findFirstFile. The data should be converted and returned */ - /* in the findData standard form. */ - (void)handle; - (void)findData; - return false; -} - -/**************************************************************************** -REMARKS: -Function to close the find process -****************************************************************************/ -void PMAPI PM_findClose( - void *handle) -{ - /* TODO: This function should close the find process. This may do */ - /* nothing for some OS'es. */ - (void)handle; -} - -/**************************************************************************** -REMARKS: -Function to determine if a drive is a valid drive or not. Under Unix this -function will return false for anything except a value of 3 (considered -the root drive, and equivalent to C: for non-Unix systems). The drive -numbering is: - - 1 - Drive A: - 2 - Drive B: - 3 - Drive C: - etc - -****************************************************************************/ -ibool PMAPI PM_driveValid( - char drive) -{ - if (drive == 3) - return true; - return false; -} - -/**************************************************************************** -REMARKS: -Function to get the current working directory for the specififed drive. -Under Unix this will always return the current working directory regardless -of what the value of 'drive' is. -****************************************************************************/ -void PMAPI PM_getdcwd( - int drive, - char *dir, - int len) -{ - (void)drive; - getcwd(dir,len); -} - -/**************************************************************************** -REMARKS: -Function to change the file attributes for a specific file. -****************************************************************************/ -void PMAPI PM_setFileAttr( - const char *filename, - uint attrib) -{ - /* TODO: Set the file attributes for a file */ - (void)filename; - (void)attrib; -} - -/**************************************************************************** -REMARKS: -Function to create a directory. -****************************************************************************/ -ibool PMAPI PM_mkdir( - const char *filename) -{ - return mkdir(filename) == 0; -} - -/**************************************************************************** -REMARKS: -Function to remove a directory. -****************************************************************************/ -ibool PMAPI PM_rmdir( - const char *filename) -{ - return rmdir(filename) == 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c deleted file mode 100644 index 579ef2c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Dummy module; no virtual framebuffer for this OS -* -****************************************************************************/ - -#include "pmapi.h" - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -{ - baseAddr = baseAddr; - bankSize = bankSize; - codeLen = codeLen; - bankFunc = bankFunc; - return NULL; -} - -void PMAPI VF_exit(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c deleted file mode 100644 index 820e292..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** -* -* Description: OS specific implementation for the Zen Timer functions. -* -****************************************************************************/ - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -void __ZTimerInit(void) -{ - /* TODO: Do any specific internal initialisation in here */ -} - -/**************************************************************************** -REMARKS: -Start the Zen Timer counting. -****************************************************************************/ -static void __LZTimerOn( - LZTimerObject *tm) -{ - /* TODO: Start the Zen Timer counting. This should be a macro if */ - /* possible. */ -} - -/**************************************************************************** -REMARKS: -Compute the lap time since the timer was started. -****************************************************************************/ -static ulong __LZTimerLap( - LZTimerObject *tm) -{ - /* TODO: Compute the lap time between the current time and when the */ - /* timer was started. */ - return 0; -} - -/**************************************************************************** -REMARKS: -Stop the Zen Timer counting. -****************************************************************************/ -static void __LZTimerOff( - LZTimerObject *tm) -{ - /* TODO: Stop the timer counting. Should be a macro if possible. */ -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time in microseconds between start and end timings. -****************************************************************************/ -static ulong __LZTimerCount( - LZTimerObject *tm) -{ - /* TODO: Compute the elapsed time and return it. Always microseconds. */ - return 0; -} - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as microseconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION 1 - -/**************************************************************************** -REMARKS: -Read the Long Period timer from the OS -****************************************************************************/ -static ulong __ULZReadTime(void) -{ - /* TODO: Read the long period timer from the OS. The resolution of this */ - /* timer should be around 1/20 of a second for timing long */ - /* periods if possible. */ -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong __ULZElapsedTime(ulong start,ulong finish) -{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c b/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c deleted file mode 100644 index ba90262..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c +++ /dev/null @@ -1,90 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to install a C based -* control C/break interrupt handler. Note that this -* alternate version does not work with all extenders. -* -* Functions tested: PM_installAltBreakHandler() -* PM_restoreBreakHandler() -* -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -volatile int breakHit = false; -volatile int ctrlCHit = false; - -#pragma off (check_stack) /* No stack checking under Watcom */ - -void PMAPI breakHandler(uint bHit) -{ - if (bHit) - breakHit = true; - else - ctrlCHit = true; -} - -int main(void) -{ - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - PM_installAltBreakHandler(breakHandler); - printf("Control C/Break interrupt handler installed\n"); - while (1) { - if (ctrlCHit) { - printf("Code termimated with Ctrl-C.\n"); - break; - } - if (breakHit) { - printf("Code termimated with Ctrl-Break.\n"); - break; - } - if (PM_kbhit() && PM_getch() == 0x1B) { - printf("No break code detected!\n"); - break; - } - printf("Hit Ctrl-C or Ctrl-Break to exit!\n"); - } - - PM_restoreBreakHandler(); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c b/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c deleted file mode 100644 index e137307..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c +++ /dev/null @@ -1,85 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to install a C based -* critical error handler. -* -* Functions tested: PM_installCriticalHandler() -* PM_criticalError() -* PM_restoreCriticalHandler() -* -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -volatile uint criticalError = false; -volatile uint axValue; -volatile uint diValue; - -#pragma off (check_stack) /* No stack checking under Watcom */ - -uint PMAPI criticalHandler(uint axVal,uint diVal) -{ - criticalError = true; - axValue = axVal; - diValue = diVal; - return 3; /* Tell MS-DOS to fail the operation */ -} - -int main(void) -{ - FILE *f; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - PM_installAltCriticalHandler(criticalHandler); - printf("Critical Error handler installed - trying to read from A: drive...\n"); - f = fopen("a:\bog.bog","rb"); - if (f) fclose(f); - if (criticalError) { - printf("Critical error occured on INT 21h function %02X!\n", - axValue >> 8); - } - else - printf("Critical error was not caught!\n"); - PM_restoreCriticalHandler(); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c b/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c deleted file mode 100644 index 5fa3382..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to manipulate the -* BIOS data area from protected mode using the PM -* library. Compile and link with the appropriate command -* line for your DOS extender. -* -* Functions tested: PM_getBIOSSelector() -* PM_getLong() -* PM_getByte() -* PM_getWord() -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -/* Macros to obtain values from the BIOS data area */ - -#define TICKS() PM_getLong(bios+0x6C) -#define KB_STAT PM_getByte(bios+0x17) -#define KB_HEAD PM_getWord(bios+0x1A) -#define KB_TAIL PM_getWord(bios+0x1C) - -/* Macros for working with the keyboard buffer */ - -#define KB_HIT() (KB_HEAD != KB_TAIL) -#define CTRL() (KB_STAT & 4) -#define SHIFT() (KB_STAT & 2) -#define ESC 0x1B - -/* Selector for BIOS data area */ - -uchar *bios; - -int main(void) -{ - int c,done = 0; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - bios = PM_getBIOSPointer(); - printf("Hit any key to test, Ctrl-Shift-Esc to quit\n"); - while (!done) { - if (KB_HIT()) { - c = PM_getch(); - if (c == 0) PM_getch(); - printf("TIME=%-8lX ST=%02X CHAR=%02X ", TICKS(), KB_STAT, c); - printf("\n"); - if ((c == ESC) && SHIFT() && CTRL())/* Ctrl-Shift-Esc */ - break; - } - } - - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/block.c b/board/MAI/bios_emulator/scitech/src/pm/tests/block.c deleted file mode 100644 index 15d503c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/block.c +++ /dev/null @@ -1,69 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Test program for the PM_blockUntilTimeout function. -* -****************************************************************************/ - -#include -#include "pmapi.h" - -#define DELAY_MSECS 1100 -#define LOOPS 5 - -/*-------------------------- Implementation -------------------------------*/ - -/* The following routine takes a long count in microseconds and outputs - * a string representing the count in seconds. It could be modified to - * return a pointer to a static string representing the count rather - * than printing it out. - */ - -void ReportTime(ulong count) -{ - ulong secs; - - secs = count / 1000000L; - count = count - secs * 1000000L; - printf("Time taken: %lu.%06lu seconds\n",secs,count); -} - -int main(void) -{ - int i; - - printf("Detecting processor information ..."); - fflush(stdout); - printf("\n\n%s\n", CPU_getProcessorName()); - ZTimerInit(); - LZTimerOn(); - for (i = 0; i < LOOPS; i++) { - PM_blockUntilTimeout(DELAY_MSECS); - ReportTime(LZTimerLap()); - } - LZTimerOff(); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c b/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c deleted file mode 100644 index 10b6446..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c +++ /dev/null @@ -1,78 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to install a C based -* control C/break interrupt handler. -* -* Functions tested: PM_installBreakHandler() -* PM_ctrlCHit() -* PM_ctrlBreakHit() -* PM_restoreBreakHandler() -* -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -int main(void) -{ - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - PM_installBreakHandler(); - printf("Control C/Break interrupt handler installed\n"); - while (1) { - if (PM_ctrlCHit(1)) { - printf("Code termimated with Ctrl-C.\n"); - break; - } - if (PM_ctrlBreakHit(1)) { - printf("Code termimated with Ctrl-Break.\n"); - break; - } - if (PM_kbhit() && PM_getch() == 0x1B) { - printf("No break code detected!\n"); - break; - } - printf("Hit Ctrl-C or Ctrl-Break to exit!\n"); - } - - PM_restoreBreakHandler(); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c b/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c deleted file mode 100644 index 4d37cab..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to call a real mode -* procedure. We simply copy a terribly simple assembly -* language routine into a real mode block that we allocate, -* and then attempt to call the routine and verify that it -* was successful. -* -* Functions tested: PM_allocRealSeg() -* PM_freeRealSeg() -* PM_callRealMode() -* -****************************************************************************/ - -#include -#include -#include -#include "pmapi.h" - -/* Block of real mode code we will eventually call */ - -static unsigned char realModeCode[] = { - 0x93, /* xchg ax,bx */ - 0x87, 0xCA, /* xchg cx,dx */ - 0xCB /* retf */ - }; - -int main(void) -{ - RMREGS regs; - RMSREGS sregs; - uchar *p; - unsigned r_seg,r_off; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - /* Allocate a the block of real mode memory */ - if ((p = PM_allocRealSeg(sizeof(realModeCode), &r_seg, &r_off)) == NULL) { - printf("Unable to allocate real mode memory!\n"); - exit(1); - } - - /* Copy the real mode code */ - memcpy(p,realModeCode,sizeof(realModeCode)); - - /* Now call the real mode code */ - regs.x.ax = 1; - regs.x.bx = 2; - regs.x.cx = 3; - regs.x.dx = 4; - regs.x.si = 5; - regs.x.di = 6; - sregs.es = 7; - sregs.ds = 8; - PM_callRealMode(r_seg,r_off,®s,&sregs); - if (regs.x.ax != 2 || regs.x.bx != 1 || regs.x.cx != 4 || regs.x.dx != 3 - || regs.x.si != 5 || regs.x.di != 6 || sregs.es != 7 - || sregs.ds != 8) { - printf("Real mode call failed!\n"); - printf("\n"); - printf("ax = %04X, bx = %04X, cx = %04X, dx = %04X\n", - regs.x.ax,regs.x.bx,regs.x.cx,regs.x.dx); - printf("si = %04X, di = %04X, es = %04X, ds = %04X\n", - regs.x.si,regs.x.di,sregs.es,sregs.ds); - } - else - printf("Real mode call succeeded!\n"); - - /* Free the memory we allocated */ - PM_freeRealSeg(p); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c b/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c deleted file mode 100644 index 5933ac9..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Main module for building checked builds of products with -* assertions and trace code. -* -****************************************************************************/ - -#include "scitech.h" -#include -#include -#include -#ifdef __WINDOWS__ -#define WIN32_LEAN_AND_MEAN -#define STRICT -#include -#endif - -#ifdef CHECKED - -/*---------------------------- Global variables ---------------------------*/ - -#define LOGFILE "\\scitech.log" - -void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line) = _CHK_defaultFail; - -/*---------------------------- Implementation -----------------------------*/ - -/**************************************************************************** -DESCRIPTION: -Handles fatal error and warning conditions for checked builds. - -HEADER: -scitech.h - -REMARKS: -This function is called whenever an inline check or warning fails in any -of the SciTech runtime libraries. Warning conditions simply cause the -condition to be logged to the log file and send to the system debugger -under Window. Fatal error conditions do all of the above, and then -terminate the program with a fatal error conditions. - -This handler may be overriden by the user code if necessary to replace it -with a different handler (the MGL for instance overrides this and replaces -it with a handler that does an MGL_exit() before terminating the application -so that it will clean up correctly. -****************************************************************************/ -void _CHK_defaultFail( - int fatal, - const char *msg, - const char *cond, - const char *file, - int line) -{ - char buf[256]; - FILE *log = fopen(LOGFILE, "at+"); - - sprintf(buf,msg,cond,file,line); - if (log) { - fputs(buf,log); - fflush(log); - fclose(log); -#ifdef __WINDOWS__ - OutputDebugStr(buf); -#endif - } - if (fatal) { -#ifdef __WINDOWS__ - MessageBox(NULL, buf,"Fatal Error!",MB_ICONEXCLAMATION); -#else - fputs(buf,stderr); -#endif - exit(-1); - } -} - -#endif /* CHECKED */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c b/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c deleted file mode 100644 index 30e5dd3..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c +++ /dev/null @@ -1,46 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Test program for the CPU detection code. -* -****************************************************************************/ - -#include "ztimer.h" -#include "pmapi.h" -#include -#include - -/*----------------------------- Implementation ----------------------------*/ - -int main(void) -{ - printf("Detecting processor information ..."); - fflush(stdout); - printf("\n\n%s\n", CPU_getProcessorName()); - if (CPU_haveRDTSC()) - printf("\nProcessor supports Read Time Stamp Counter performance timer.\n"); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c b/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c deleted file mode 100644 index 60f1251..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c +++ /dev/null @@ -1,70 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to install a C based -* critical error handler. -* -* Functions tested: PM_installAltCriticalHandler() -* PM_restoreCriticalHandler() -* -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -int main(void) -{ - FILE *f; - int axcode,dicode; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - PM_installCriticalHandler(); - printf("Critical Error handler installed - trying to read from A: drive...\n"); - f = fopen("a:\bog.bog","rb"); - if (f) fclose(f); - if (PM_criticalError(&axcode,&dicode,1)) { - printf("Critical error occured on INT 21h function %02X!\n", - axcode >> 8); - } - else printf("Critical error was not caught!\n"); - PM_restoreCriticalHandler(); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c b/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c deleted file mode 100644 index 06c2180..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c +++ /dev/null @@ -1,501 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Test program to test out the cross platform event handling -* library. -* -****************************************************************************/ - -#include -#include -#include -#include "pmapi.h" -#include "event.h" - -/* Translation table for key codes */ - -typedef struct { - int code; - char *name; - } KeyEntry; - -KeyEntry ASCIICodes[] = { - {ASCII_ctrlA ,"ASCII_ctrlA"}, - {ASCII_ctrlB ,"ASCII_ctrlB"}, - {ASCII_ctrlC ,"ASCII_ctrlC"}, - {ASCII_ctrlD ,"ASCII_ctrlD"}, - {ASCII_ctrlE ,"ASCII_ctrlE"}, - {ASCII_ctrlF ,"ASCII_ctrlF"}, - {ASCII_ctrlG ,"ASCII_ctrlG"}, - {ASCII_backspace ,"ASCII_backspace"}, - {ASCII_ctrlH ,"ASCII_ctrlH"}, - {ASCII_tab ,"ASCII_tab"}, - {ASCII_ctrlI ,"ASCII_ctrlI"}, - {ASCII_ctrlJ ,"ASCII_ctrlJ"}, - {ASCII_ctrlK ,"ASCII_ctrlK"}, - {ASCII_ctrlL ,"ASCII_ctrlL"}, - {ASCII_enter ,"ASCII_enter"}, - {ASCII_ctrlM ,"ASCII_ctrlM"}, - {ASCII_ctrlN ,"ASCII_ctrlN"}, - {ASCII_ctrlO ,"ASCII_ctrlO"}, - {ASCII_ctrlP ,"ASCII_ctrlP"}, - {ASCII_ctrlQ ,"ASCII_ctrlQ"}, - {ASCII_ctrlR ,"ASCII_ctrlR"}, - {ASCII_ctrlS ,"ASCII_ctrlS"}, - {ASCII_ctrlT ,"ASCII_ctrlT"}, - {ASCII_ctrlU ,"ASCII_ctrlU"}, - {ASCII_ctrlV ,"ASCII_ctrlV"}, - {ASCII_ctrlW ,"ASCII_ctrlW"}, - {ASCII_ctrlX ,"ASCII_ctrlX"}, - {ASCII_ctrlY ,"ASCII_ctrlY"}, - {ASCII_ctrlZ ,"ASCII_ctrlZ"}, - {ASCII_esc ,"ASCII_esc"}, - {ASCII_space ,"ASCII_space"}, - {ASCII_exclamation ,"ASCII_exclamation"}, - {ASCII_quote ,"ASCII_quote"}, - {ASCII_pound ,"ASCII_pound"}, - {ASCII_dollar ,"ASCII_dollar"}, - {ASCII_percent ,"ASCII_percent"}, - {ASCII_ampersand ,"ASCII_ampersand"}, - {ASCII_apostrophe ,"ASCII_apostrophe"}, - {ASCII_leftBrace ,"ASCII_leftBrace"}, - {ASCII_rightBrace ,"ASCII_rightBrace"}, - {ASCII_times ,"ASCII_times"}, - {ASCII_plus ,"ASCII_plus"}, - {ASCII_comma ,"ASCII_comma"}, - {ASCII_minus ,"ASCII_minus"}, - {ASCII_period ,"ASCII_period"}, - {ASCII_divide ,"ASCII_divide"}, - {ASCII_0 ,"ASCII_0"}, - {ASCII_1 ,"ASCII_1"}, - {ASCII_2 ,"ASCII_2"}, - {ASCII_3 ,"ASCII_3"}, - {ASCII_4 ,"ASCII_4"}, - {ASCII_5 ,"ASCII_5"}, - {ASCII_6 ,"ASCII_6"}, - {ASCII_7 ,"ASCII_7"}, - {ASCII_8 ,"ASCII_8"}, - {ASCII_9 ,"ASCII_9"}, - {ASCII_colon ,"ASCII_colon"}, - {ASCII_semicolon ,"ASCII_semicolon"}, - {ASCII_lessThan ,"ASCII_lessThan"}, - {ASCII_equals ,"ASCII_equals"}, - {ASCII_greaterThan ,"ASCII_greaterThan"}, - {ASCII_question ,"ASCII_question"}, - {ASCII_at ,"ASCII_at"}, - {ASCII_A ,"ASCII_A"}, - {ASCII_B ,"ASCII_B"}, - {ASCII_C ,"ASCII_C"}, - {ASCII_D ,"ASCII_D"}, - {ASCII_E ,"ASCII_E"}, - {ASCII_F ,"ASCII_F"}, - {ASCII_G ,"ASCII_G"}, - {ASCII_H ,"ASCII_H"}, - {ASCII_I ,"ASCII_I"}, - {ASCII_J ,"ASCII_J"}, - {ASCII_K ,"ASCII_K"}, - {ASCII_L ,"ASCII_L"}, - {ASCII_M ,"ASCII_M"}, - {ASCII_N ,"ASCII_N"}, - {ASCII_O ,"ASCII_O"}, - {ASCII_P ,"ASCII_P"}, - {ASCII_Q ,"ASCII_Q"}, - {ASCII_R ,"ASCII_R"}, - {ASCII_S ,"ASCII_S"}, - {ASCII_T ,"ASCII_T"}, - {ASCII_U ,"ASCII_U"}, - {ASCII_V ,"ASCII_V"}, - {ASCII_W ,"ASCII_W"}, - {ASCII_X ,"ASCII_X"}, - {ASCII_Y ,"ASCII_Y"}, - {ASCII_Z ,"ASCII_Z"}, - {ASCII_leftSquareBrace ,"ASCII_leftSquareBrace"}, - {ASCII_backSlash ,"ASCII_backSlash"}, - {ASCII_rightSquareBrace ,"ASCII_rightSquareBrace"}, - {ASCII_caret ,"ASCII_caret"}, - {ASCII_underscore ,"ASCII_underscore"}, - {ASCII_leftApostrophe ,"ASCII_leftApostrophe"}, - {ASCII_a ,"ASCII_a"}, - {ASCII_b ,"ASCII_b"}, - {ASCII_c ,"ASCII_c"}, - {ASCII_d ,"ASCII_d"}, - {ASCII_e ,"ASCII_e"}, - {ASCII_f ,"ASCII_f"}, - {ASCII_g ,"ASCII_g"}, - {ASCII_h ,"ASCII_h"}, - {ASCII_i ,"ASCII_i"}, - {ASCII_j ,"ASCII_j"}, - {ASCII_k ,"ASCII_k"}, - {ASCII_l ,"ASCII_l"}, - {ASCII_m ,"ASCII_m"}, - {ASCII_n ,"ASCII_n"}, - {ASCII_o ,"ASCII_o"}, - {ASCII_p ,"ASCII_p"}, - {ASCII_q ,"ASCII_q"}, - {ASCII_r ,"ASCII_r"}, - {ASCII_s ,"ASCII_s"}, - {ASCII_t ,"ASCII_t"}, - {ASCII_u ,"ASCII_u"}, - {ASCII_v ,"ASCII_v"}, - {ASCII_w ,"ASCII_w"}, - {ASCII_x ,"ASCII_x"}, - {ASCII_y ,"ASCII_y"}, - {ASCII_z ,"ASCII_z"}, - {ASCII_leftCurlyBrace ,"ASCII_leftCurlyBrace"}, - {ASCII_verticalBar ,"ASCII_verticalBar"}, - {ASCII_rightCurlyBrace ,"ASCII_rightCurlyBrace"}, - {ASCII_tilde ,"ASCII_tilde"}, - {0 ,"ASCII_unknown"}, - }; - -KeyEntry ScanCodes[] = { - {KB_padEnter ,"KB_padEnter"}, - {KB_padMinus ,"KB_padMinus"}, - {KB_padPlus ,"KB_padPlus"}, - {KB_padTimes ,"KB_padTimes"}, - {KB_padDivide ,"KB_padDivide"}, - {KB_padLeft ,"KB_padLeft"}, - {KB_padRight ,"KB_padRight"}, - {KB_padUp ,"KB_padUp"}, - {KB_padDown ,"KB_padDown"}, - {KB_padInsert ,"KB_padInsert"}, - {KB_padDelete ,"KB_padDelete"}, - {KB_padHome ,"KB_padHome"}, - {KB_padEnd ,"KB_padEnd"}, - {KB_padPageUp ,"KB_padPageUp"}, - {KB_padPageDown ,"KB_padPageDown"}, - {KB_padCenter ,"KB_padCenter"}, - {KB_F1 ,"KB_F1"}, - {KB_F2 ,"KB_F2"}, - {KB_F3 ,"KB_F3"}, - {KB_F4 ,"KB_F4"}, - {KB_F5 ,"KB_F5"}, - {KB_F6 ,"KB_F6"}, - {KB_F7 ,"KB_F7"}, - {KB_F8 ,"KB_F8"}, - {KB_F9 ,"KB_F9"}, - {KB_F10 ,"KB_F10"}, - {KB_F11 ,"KB_F11"}, - {KB_F12 ,"KB_F12"}, - {KB_left ,"KB_left"}, - {KB_right ,"KB_right"}, - {KB_up ,"KB_up"}, - {KB_down ,"KB_down"}, - {KB_insert ,"KB_insert"}, - {KB_delete ,"KB_delete"}, - {KB_home ,"KB_home"}, - {KB_end ,"KB_end"}, - {KB_pageUp ,"KB_pageUp"}, - {KB_pageDown ,"KB_pageDown"}, - {KB_capsLock ,"KB_capsLock"}, - {KB_numLock ,"KB_numLock"}, - {KB_scrollLock ,"KB_scrollLock"}, - {KB_leftShift ,"KB_leftShift"}, - {KB_rightShift ,"KB_rightShift"}, - {KB_leftCtrl ,"KB_leftCtrl"}, - {KB_rightCtrl ,"KB_rightCtrl"}, - {KB_leftAlt ,"KB_leftAlt"}, - {KB_rightAlt ,"KB_rightAlt"}, - {KB_leftWindows ,"KB_leftWindows"}, - {KB_rightWindows ,"KB_rightWindows"}, - {KB_menu ,"KB_menu"}, - {KB_sysReq ,"KB_sysReq"}, - {KB_esc ,"KB_esc"}, - {KB_1 ,"KB_1"}, - {KB_2 ,"KB_2"}, - {KB_3 ,"KB_3"}, - {KB_4 ,"KB_4"}, - {KB_5 ,"KB_5"}, - {KB_6 ,"KB_6"}, - {KB_7 ,"KB_7"}, - {KB_8 ,"KB_8"}, - {KB_9 ,"KB_9"}, - {KB_0 ,"KB_0"}, - {KB_minus ,"KB_minus"}, - {KB_equals ,"KB_equals"}, - {KB_backSlash ,"KB_backSlash"}, - {KB_backspace ,"KB_backspace"}, - {KB_tab ,"KB_tab"}, - {KB_Q ,"KB_Q"}, - {KB_W ,"KB_W"}, - {KB_E ,"KB_E"}, - {KB_R ,"KB_R"}, - {KB_T ,"KB_T"}, - {KB_Y ,"KB_Y"}, - {KB_U ,"KB_U"}, - {KB_I ,"KB_I"}, - {KB_O ,"KB_O"}, - {KB_P ,"KB_P"}, - {KB_leftSquareBrace ,"KB_leftSquareBrace"}, - {KB_rightSquareBrace ,"KB_rightSquareBrace"}, - {KB_enter ,"KB_enter"}, - {KB_A ,"KB_A"}, - {KB_S ,"KB_S"}, - {KB_D ,"KB_D"}, - {KB_F ,"KB_F"}, - {KB_G ,"KB_G"}, - {KB_H ,"KB_H"}, - {KB_J ,"KB_J"}, - {KB_K ,"KB_K"}, - {KB_L ,"KB_L"}, - {KB_semicolon ,"KB_semicolon"}, - {KB_apostrophe ,"KB_apostrophe"}, - {KB_Z ,"KB_Z"}, - {KB_X ,"KB_X"}, - {KB_C ,"KB_C"}, - {KB_V ,"KB_V"}, - {KB_B ,"KB_B"}, - {KB_N ,"KB_N"}, - {KB_M ,"KB_M"}, - {KB_comma ,"KB_comma"}, - {KB_period ,"KB_period"}, - {KB_divide ,"KB_divide"}, - {KB_space ,"KB_space"}, - {KB_tilde ,"KB_tilde"}, - {0 ,"KB_unknown"}, - }; - -/**************************************************************************** -PARAMETERS: -x - X coordinate of the mouse cursor position (screen coordinates) -y - Y coordinate of the mouse cursor position (screen coordinates) - -REMARKS: -This gets called periodically to move the mouse. It will get called when -the mouse may not have actually moved, so check if it has before redrawing -it. -****************************************************************************/ -void EVTAPI moveMouse( - int x, - int y) -{ -} - -/**************************************************************************** -PARAMETERS: -code - Code to translate -keys - Table of translation key values to look up - -REMARKS: -Simple function to look up the printable name for the keyboard code. -****************************************************************************/ -KeyEntry *FindKey( - int code, - KeyEntry *keys) -{ - KeyEntry *key; - - for (key = keys; key->code != 0; key++) { - if (key->code == code) - break; - } - return key; -} - -/**************************************************************************** -PARAMETERS: -evt - Event to display modifiers for - -REMARKS: -Function to display shift modifiers flags -****************************************************************************/ -void DisplayModifiers( - event_t *evt) -{ - if (evt->modifiers & EVT_LEFTBUT) - printf(", LBUT"); - if (evt->modifiers & EVT_RIGHTBUT) - printf(", RBUT"); - if (evt->modifiers & EVT_MIDDLEBUT) - printf(", MBUT"); - if (evt->modifiers & EVT_SHIFTKEY) { - if (evt->modifiers & EVT_LEFTSHIFT) - printf(", LSHIFT"); - if (evt->modifiers & EVT_RIGHTSHIFT) - printf(", RSHIFT"); - } - if (evt->modifiers & EVT_CTRLSTATE) { - if (evt->modifiers & EVT_LEFTCTRL) - printf(", LCTRL"); - if (evt->modifiers & EVT_RIGHTCTRL) - printf(", RCTRL"); - } - if (evt->modifiers & EVT_ALTSTATE) { - if (evt->modifiers & EVT_LEFTALT) - printf(", LALT"); - if (evt->modifiers & EVT_RIGHTALT) - printf(", RALT"); - } -} - -/**************************************************************************** -PARAMETERS: -msg - Message to display for type of event -evt - Event to display - -REMARKS: -Function to display the status of the keyboard event to the screen. -****************************************************************************/ -void DisplayKey( - char *msg, - event_t *evt) -{ - KeyEntry *ascii,*scan; - char ch = EVT_asciiCode(evt->message); - - ascii = FindKey(ch,ASCIICodes); - scan = FindKey(EVT_scanCode(evt->message),ScanCodes); - printf("%s: 0x%04X -> %s, %s, '%c'", - msg, (int)evt->message & 0xFFFF, scan->name, ascii->name, isprint(ch) ? ch : ' '); - DisplayModifiers(evt); - printf("\n"); -} - -/**************************************************************************** -PARAMETERS: -msg - Message to display for type of event -evt - Event to display - -REMARKS: -Function to display the status of the mouse event to the screen. -****************************************************************************/ -void DisplayMouse( - char *msg, - event_t *evt) -{ - printf("%s: ", msg); - if (evt->message & EVT_LEFTBMASK) - printf("LEFT "); - if (evt->message & EVT_RIGHTBMASK) - printf("RIGHT "); - if (evt->message & EVT_MIDDLEBMASK) - printf("MIDDLE "); - printf("abs(%d,%d), rel(%d,%d)", evt->where_x, evt->where_y, evt->relative_x, evt->relative_y); - DisplayModifiers(evt); - if (evt->message & EVT_DBLCLICK) - printf(", DBLCLICK"); - printf("\n"); -} - -/**************************************************************************** -PARAMETERS: -msg - Message to display for type of event -evt - Event to display - -REMARKS: -Function to display the status of the joystick event to the screen. -****************************************************************************/ -void DisplayJoy( - char *msg, - event_t *evt) -{ - printf("%s: Joy1(%4d,%4d,%c%c), Joy2(%4d,%4d,%c%c)\n", msg, - evt->where_x,evt->where_y, - (evt->message & EVT_JOY1_BUTTONA) ? 'A' : 'a', - (evt->message & EVT_JOY1_BUTTONB) ? 'B' : 'b', - evt->relative_x,evt->relative_y, - (evt->message & EVT_JOY2_BUTTONA) ? 'A' : 'a', - (evt->message & EVT_JOY2_BUTTONB) ? 'B' : 'b'); -} - -/**************************************************************************** -REMARKS: -Joystick calibration routine -****************************************************************************/ -void CalibrateJoy(void) -{ - event_t evt; - if(EVT_joyIsPresent()){ - printf("Joystick Calibration\nMove the joystick to the upper left corner and press any button.\n"); - EVT_halt(&evt, EVT_JOYCLICK); - EVT_halt(&evt, EVT_JOYCLICK); - EVT_joySetUpperLeft(); - printf("Move the joystick to the lower right corner and press any button.\n"); - EVT_halt(&evt, EVT_JOYCLICK); - EVT_halt(&evt, EVT_JOYCLICK); - EVT_joySetLowerRight(); - printf("Move the joystick to center position and press any button.\n"); - EVT_halt(&evt, EVT_JOYCLICK); - EVT_halt(&evt, EVT_JOYCLICK); - EVT_joySetCenter(); - printf("Joystick calibrated\n"); - } -} - -/**************************************************************************** -REMARKS: -Main program entry point -****************************************************************************/ -int main(void) -{ - event_t evt; - ibool done = false; - PM_HWND hwndConsole; - - hwndConsole = PM_openConsole(0,0,0,0,0,true); - EVT_init(&moveMouse); - EVT_setMouseRange(1024,768); - CalibrateJoy(); - do { - EVT_pollJoystick(); - if (EVT_getNext(&evt,EVT_EVERYEVT)) { - switch (evt.what) { - case EVT_KEYDOWN: - DisplayKey("EVT_KEYDOWN ", &evt); - if (EVT_scanCode(evt.message) == KB_esc) - done = true; - break; - case EVT_KEYREPEAT: - DisplayKey("EVT_KEYREPEAT", &evt); - break; - case EVT_KEYUP: - DisplayKey("EVT_KEYUP ", &evt); - break; - case EVT_MOUSEDOWN: - DisplayMouse("EVT_MOUSEDOWN", &evt); - break; - case EVT_MOUSEAUTO: - DisplayMouse("EVT_MOUSEAUTO", &evt); - break; - case EVT_MOUSEUP: - DisplayMouse("EVT_MOUSEUP ", &evt); - break; - case EVT_MOUSEMOVE: - DisplayMouse("EVT_MOUSEMOVE", &evt); - break; - case EVT_JOYCLICK: - DisplayJoy("EVT_JOYCLICK ", &evt); - break; - case EVT_JOYMOVE: - DisplayJoy("EVT_JOYMOVE ", &evt); - break; - } - } - } while (!done); - EVT_exit(); - PM_closeConsole(hwndConsole); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c b/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c deleted file mode 100644 index 67ad245..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to allocate real mode -* memory and to call real mode interrupt handlers such as -* the VESA VBE BIOS from protected mode. Compile and link -* with the appropriate command line for your DOS extender. -* -* Functions tested: PM_getVESABuf() -* PM_mapRealPointer() -* PM_int86x() -* -****************************************************************************/ - -#include -#include -#include -#include "pmapi.h" - -/* SuperVGA information block */ - -#pragma pack(1) - -typedef struct { - char VESASignature[4]; /* 'VESA' 4 byte signature */ - short VESAVersion; /* VBE version number */ - ulong OEMStringPtr; /* Far pointer to OEM string */ - ulong Capabilities; /* Capabilities of video card */ - ulong VideoModePtr; /* Far pointer to supported modes */ - short TotalMemory; /* Number of 64kb memory blocks */ - char reserved[236]; /* Pad to 256 byte block size */ - } VgaInfoBlock; - -#pragma pack() - -int main(void) -{ - RMREGS regs; - RMSREGS sregs; - VgaInfoBlock vgaInfo; - ushort *mode; - uint vgLen; - uchar *vgPtr; - unsigned r_vgseg,r_vgoff; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - /* Allocate a 256 byte block of real memory for communicating with - * the VESA BIOS. - */ - if ((vgPtr = PM_getVESABuf(&vgLen,&r_vgseg,&r_vgoff)) == NULL) { - printf("Unable to allocate VESA memory buffer!\n"); - exit(1); - } - - /* Call the VESA VBE to see if it is out there */ - regs.x.ax = 0x4F00; - regs.x.di = r_vgoff; - sregs.es = r_vgseg; - memcpy(vgPtr,"VBE2",4); - PM_int86x(0x10, ®s, ®s, &sregs); - memcpy(&vgaInfo,vgPtr,sizeof(VgaInfoBlock)); - if (regs.x.ax == 0x4F && strncmp(vgaInfo.VESASignature,"VESA",4) == 0) { - printf("VESA VBE version %d.%d BIOS detected\n\n", - vgaInfo.VESAVersion >> 8, vgaInfo.VESAVersion & 0xF); - printf("Available video modes:\n"); - mode = PM_mapRealPointer(vgaInfo.VideoModePtr >> 16, vgaInfo.VideoModePtr & 0xFFFF); - while (*mode != 0xFFFF) { - printf(" %04hXh (%08X)\n", *mode, (int)mode); - mode++; - } - } - else - printf("VESA VBE not found\n"); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/key.c b/board/MAI/bios_emulator/scitech/src/pm/tests/key.c deleted file mode 100644 index dba8885..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/key.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to install a C based -* keyboard interrupt handler. -* -* Functions tested: PM_setKeyHandler() -* PM_chainPrevKey() -* PM_restoreKeyHandler() -* -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -volatile long count = 0; - -#pragma off (check_stack) /* No stack checking under Watcom */ - -void PMAPI keyHandler(void) -{ - count++; - PM_chainPrevKey(); /* Chain to previous handler */ -} - -int main(void) -{ - int ch; - PM_lockHandle lh; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - /* Install our timer handler and lock handler pages in memory. It is - * difficult to get the size of a function in C, but we know our - * function is well less than 100 bytes (and an entire 4k page will - * need to be locked by the server anyway). - */ - PM_lockCodePages((__codePtr)keyHandler,100,&lh); - PM_lockDataPages((void*)&count,sizeof(count),&lh); - PM_installBreakHandler(); /* We *DONT* want Ctrl-Breaks! */ - PM_setKeyHandler(keyHandler); - printf("Keyboard interrupt handler installed - Type some characters and\n"); - printf("hit ESC to exit\n"); - while ((ch = PM_getch()) != 0x1B) { - printf("%c", ch); - fflush(stdout); - } - - PM_restoreKeyHandler(); - PM_restoreBreakHandler(); - PM_unlockDataPages((void*)&count,sizeof(count),&lh); - PM_unlockCodePages((__codePtr)keyHandler,100,&lh); - printf("\n\nKeyboard handler was called %ld times\n", count); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c b/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c deleted file mode 100644 index b0b94be..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to install a C based -* keyboard Int 15h interrupt handler. This is an alternate -* way to intercept scancodes from the keyboard by hooking -* the Int 15h keyboard intercept callout. -* -* Functions tested: PM_setKey15Handler() -* PM_restoreKey15Handler() -* -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -volatile long count = 0; -volatile short lastScanCode = 0; - -#pragma off (check_stack) /* No stack checking under Watcom */ - -short PMAPI keyHandler(short scanCode) -{ - count++; - lastScanCode = scanCode; - return scanCode; /* Let BIOS process as normal */ -} - -int main(void) -{ - int ch; - PM_lockHandle lh; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - /* Install our timer handler and lock handler pages in memory. It is - * difficult to get the size of a function in C, but we know our - * function is well less than 100 bytes (and an entire 4k page will - * need to be locked by the server anyway). - */ - PM_lockCodePages((__codePtr)keyHandler,100,&lh); - PM_lockDataPages((void*)&count,sizeof(count),&lh); - PM_installBreakHandler(); /* We *DONT* want Ctrl-Break's! */ - PM_setKey15Handler(keyHandler); - printf("Keyboard interrupt handler installed - Type some characters and\n"); - printf("hit ESC to exit\n"); - while ((ch = PM_getch()) != 0x1B) { - printf("%c", ch); - fflush(stdout); - } - - PM_restoreKey15Handler(); - PM_restoreBreakHandler(); - PM_unlockDataPages((void*)&count,sizeof(count),&lh); - PM_unlockCodePages((__codePtr)keyHandler,100,&lh); - printf("\n\nKeyboard handler was called %ld times\n", count); - printf("Last scan code %04X\n", lastScanCode); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c b/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c deleted file mode 100644 index a2c655b..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to determine just how much memory can be -* allocated with the compiler in use. Compile and link -* with the appropriate command line for your DOS extender. -* -* Functions tested: PM_malloc() -* PM_availableMemory() -* -* -****************************************************************************/ - -#include -#include -#include -#include -#include "pmapi.h" - -#ifdef __16BIT__ -#define MAXALLOC 64 -#else -#define MAXALLOC 2000 -#endif - -int main(void) -{ - int i; - ulong allocs; - ulong physical,total; - char *p,*pa[MAXALLOC]; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - printf("Memory available at start:\n"); - PM_availableMemory(&physical,&total); - printf(" Physical memory: %ld Kb\n", physical / 1024); - printf(" Total (including virtual): %ld Kb\n", total / 1024); - printf("\n"); - for (allocs = i = 0; i < MAXALLOC; i++) { - if ((pa[i] = PM_malloc(10*1024)) != 0) { /* in 10k blocks */ - p = pa[allocs]; - memset(p, 0, 10*1024); /* touch every byte */ - *p = 'x'; /* do something, anything with */ - p[1023] = 'y'; /* the allocated memory */ - allocs++; - printf("Allocated %lu bytes\r", 10*(allocs << 10)); - } - else break; - if (PM_kbhit() && (PM_getch() == 0x1B)) - break; - } - - printf("\n\nAllocated total of %lu bytes\n", 10 * (allocs << 10)); - - printf("\nMemory available at end:\n"); - PM_availableMemory(&physical,&total); - printf(" Physical memory: %ld Kb\n", physical / 1024); - printf(" Total (including virtual): %ld Kb\n", total / 1024); - - for (i = allocs-1; i >= 0; i--) - PM_free(pa[i]); - - printf("\nMemory available after freeing all blocks (note that under protected mode\n"); - printf("this will most likely not be correct after freeing blocks):\n\n"); - PM_availableMemory(&physical,&total); - printf(" Physical memory: %ld Kb\n", physical / 1024); - printf(" Total (including virtual): %ld Kb\n", total / 1024); - - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c b/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c deleted file mode 100644 index 2765a0d..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to install an assembly -* language mouse interrupt handler. We use assembly language -* as it must be a far function and should swap to a local -* 32 bit stack if it is going to call any C based code (which -* we do in this example). -* -* Functions tested: PM_installMouseHandler() -* PM_int86() -* -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -volatile long count = 0; - -#pragma off (check_stack) /* No stack checking under Watcom */ - -void PMAPI mouseHandler( - uint mask, - uint butstate, - int x, - int y, - int mickeyX, - int mickeyY) -{ - mask = mask; /* We dont use any of the parameters */ - butstate = butstate; - x = x; - y = y; - mickeyX = mickeyX; - mickeyY = mickeyY; - count++; -} - -int main(void) -{ - RMREGS regs; - PM_lockHandle lh; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - regs.x.ax = 33; /* Mouse function 33 - Software reset */ - PM_int86(0x33,®s,®s); - if (regs.x.bx == 0) { - printf("No mouse installed.\n"); - exit(1); - } - - /* Install our mouse handler and lock handler pages in memory. It is - * difficult to get the size of a function in C, but we know our - * function is well less than 100 bytes (and an entire 4k page will - * need to be locked by the server anyway). - */ - PM_lockCodePages((__codePtr)mouseHandler,100,&lh); - PM_lockDataPages((void*)&count,sizeof(count),&lh); - if (!PM_setMouseHandler(0xFFFF, mouseHandler)) { - printf("Unable to install mouse handler!\n"); - exit(1); - } - printf("Mouse handler installed - Hit any key to exit\n"); - PM_getch(); - - PM_restoreMouseHandler(); - PM_unlockDataPages((void*)&count,sizeof(count),&lh); - PM_unlockCodePages((__codePtr)mouseHandler,100,&lh); - printf("Mouse handler was called %ld times\n", count); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c b/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c deleted file mode 100644 index e00be75..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Linux/QNX -* -* Description: Program to restore the console state state from a previously -* saved state if the program crashed while the console -* was in graphics mode. -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -void setVideoMode(int mode) -{ - RMREGS r; - - r.x.ax = mode; - PM_int86(0x10, &r, &r); -} - -int main(void) -{ - PM_HWND hwndConsole; - ulong stateSize; - void *stateBuf; - FILE *f; - - /* Write the saved console state buffer to disk */ - if ((f = fopen("/etc/pmsave.dat","rb")) == NULL) { - printf("Unable to open /etc/pmsave.dat for reading!\n"); - return -1; - } - fread(&stateSize,1,sizeof(stateSize),f); - if (stateSize != PM_getConsoleStateSize()) { - printf("Size mismatch in /etc/pmsave.dat!\n"); - return -1; - } - if ((stateBuf = PM_malloc(stateSize)) == NULL) { - printf("Unable to allocate console state buffer!\n"); - return -1; - } - fread(stateBuf,1,stateSize,f); - fclose(f); - - /* Open the console */ - hwndConsole = PM_openConsole(0,0,0,0,0,true); - - /* Forcibly set 80x25 text mode using the BIOS */ - setVideoMode(0x3); - - /* Restore the previous console state */ - PM_restoreConsoleState(stateBuf,0); - PM_closeConsole(hwndConsole); - PM_free(stateBuf); - printf("Console state successfully restored from /etc/pmsave.dat\n"); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c deleted file mode 100644 index acef922..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to install a C based -* Real Time Clock interrupt handler. -* -* Functions tested: PM_setRealTimeClockHandler() -* PM_restoreRealTimeClockHandler() -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -volatile long count = 0; - -#pragma off (check_stack) /* No stack checking under Watcom */ - -void PMAPI RTCHandler(void) -{ - count++; -} - -int main(void) -{ - long oldCount; - PM_lockHandle lh; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - /* Install our timer handler and lock handler pages in memory. It is - * difficult to get the size of a function in C, but we know our - * function is well less than 100 bytes (and an entire 4k page will - * need to be locked by the server anyway). - */ - PM_lockCodePages((__codePtr)RTCHandler,100,&lh); - PM_lockDataPages((void*)&count,sizeof(count),&lh); - PM_installBreakHandler(); /* We *DONT* want Ctrl-Breaks! */ - PM_setRealTimeClockHandler(RTCHandler,128); - printf("RealTimeClock interrupt handler installed - Hit ESC to exit\n"); - oldCount = count; - while (1) { - if (PM_kbhit() && (PM_getch() == 0x1B)) - break; - if (count != oldCount) { - printf("Tick, Tock: %ld\n", count); - oldCount = count; - } - } - - PM_restoreRealTimeClockHandler(); - PM_restoreBreakHandler(); - PM_unlockDataPages((void*)&count,sizeof(count),&lh); - PM_unlockCodePages((__codePtr)RTCHandler,100,&lh); - printf("RealTimeClock handler was called %ld times\n", count); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/save.c b/board/MAI/bios_emulator/scitech/src/pm/tests/save.c deleted file mode 100644 index f732456..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/save.c +++ /dev/null @@ -1,69 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Linux/QNX -* -* Description: Program to save the console state state so that it can -* be later restored if the program crashed while the console -* was in graphics mode. -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -int main(void) -{ - PM_HWND hwndConsole; - ulong stateSize; - void *stateBuf; - FILE *f; - - /* Allocate a buffer to save console state and save the state */ - hwndConsole = PM_openConsole(0,0,0,0,0,true); - stateSize = PM_getConsoleStateSize(); - if ((stateBuf = PM_malloc(stateSize)) == NULL) { - PM_closeConsole(hwndConsole); - printf("Unable to allocate console state buffer!\n"); - return -1; - } - PM_saveConsoleState(stateBuf,0); - - /* Restore the console state on exit */ - PM_restoreConsoleState(stateBuf,0); - PM_closeConsole(hwndConsole); - - /* Write the saved console state buffer to disk */ - if ((f = fopen("/etc/pmsave.dat","wb")) == NULL) - printf("Unable to open /etc/pmsave/dat for writing!\n"); - else { - fwrite(&stateSize,1,sizeof(stateSize),f); - fwrite(stateBuf,1,stateSize,f); - fclose(f); - printf("Console state successfully saved to /etc/pmsave.dat\n"); - } - PM_free(stateBuf); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c b/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c deleted file mode 100644 index be275e1..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c +++ /dev/null @@ -1,253 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to test the PCI library functions. -* -****************************************************************************/ - -#include "pmapi.h" -#include "pcilib.h" -#include -#include -#include -#include - -/*------------------------- Global Variables ------------------------------*/ - -static int NumPCI = -1; -static PCIDeviceInfo *PCI; -static int *BridgeIndex; -static int *DeviceIndex; -static int NumBridges; -static PCIDeviceInfo *AGPBridge = NULL; -static int NumDevices; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -REMARKS: -Enumerates the PCI bus and dumps the PCI configuration information to the -log file. -****************************************************************************/ -static void EnumeratePCI(void) -{ - int i,index; - PCIDeviceInfo *info; - - printf("Displaying enumeration of PCI bus (%d devices, %d display devices)\n", - NumPCI, NumDevices); - for (index = 0; index < NumDevices; index++) - printf(" Display device %d is PCI device %d\n",index,DeviceIndex[index]); - printf("\n"); - printf("Bus Slot Fnc DeviceID SubSystem Rev Class IRQ Int Cmd\n"); - for (i = 0; i < NumPCI; i++) { - printf("%2d %2d %2d %04X:%04X %04X:%04X %02X %02X:%02X %02X %02X %04X ", - PCI[i].slot.p.Bus, - PCI[i].slot.p.Device, - PCI[i].slot.p.Function, - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].u.type0.SubSystemVendorID, - PCI[i].u.type0.SubSystemID, - PCI[i].RevID, - PCI[i].BaseClass, - PCI[i].SubClass, - PCI[i].u.type0.InterruptLine, - PCI[i].u.type0.InterruptPin, - PCI[i].Command); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printf("<- %d\n", index); - else - printf("\n"); - } - printf("\n"); - printf("DeviceID Stat Ifc Cch Lat Hdr BIST\n"); - for (i = 0; i < NumPCI; i++) { - printf("%04X:%04X %04X %02X %02X %02X %02X %02X ", - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].Status, - PCI[i].Interface, - PCI[i].CacheLineSize, - PCI[i].LatencyTimer, - PCI[i].HeaderType, - PCI[i].BIST); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printf("<- %d\n", index); - else - printf("\n"); - } - printf("\n"); - printf("DeviceID Base10h Base14h Base18h Base1Ch Base20h Base24h ROMBase\n"); - for (i = 0; i < NumPCI; i++) { - printf("%04X:%04X %08lX %08lX %08lX %08lX %08lX %08lX %08lX ", - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].u.type0.BaseAddress10, - PCI[i].u.type0.BaseAddress14, - PCI[i].u.type0.BaseAddress18, - PCI[i].u.type0.BaseAddress1C, - PCI[i].u.type0.BaseAddress20, - PCI[i].u.type0.BaseAddress24, - PCI[i].u.type0.ROMBaseAddress); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printf("<- %d\n", index); - else - printf("\n"); - } - printf("\n"); - printf("DeviceID BAR10Len BAR14Len BAR18Len BAR1CLen BAR20Len BAR24Len ROMLen\n"); - for (i = 0; i < NumPCI; i++) { - printf("%04X:%04X %08lX %08lX %08lX %08lX %08lX %08lX %08lX ", - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].u.type0.BaseAddress10Len, - PCI[i].u.type0.BaseAddress14Len, - PCI[i].u.type0.BaseAddress18Len, - PCI[i].u.type0.BaseAddress1CLen, - PCI[i].u.type0.BaseAddress20Len, - PCI[i].u.type0.BaseAddress24Len, - PCI[i].u.type0.ROMBaseAddressLen); - for (index = 0; index < NumDevices; index++) { - if (DeviceIndex[index] == i) - break; - } - if (index < NumDevices) - printf("<- %d\n", index); - else - printf("\n"); - } - printf("\n"); - printf("Displaying enumeration of %d bridge devices\n",NumBridges); - printf("\n"); - printf("DeviceID P# S# B# IOB IOL MemBase MemLimit PreBase PreLimit Ctrl\n"); - for (i = 0; i < NumBridges; i++) { - info = (PCIDeviceInfo*)&PCI[BridgeIndex[i]]; - printf("%04X:%04X %02X %02X %02X %04X %04X %08X %08X %08X %08X %04X\n", - info->VendorID, - info->DeviceID, - info->u.type1.PrimaryBusNumber, - info->u.type1.SecondayBusNumber, - info->u.type1.SubordinateBusNumber, - ((u16)info->u.type1.IOBase << 8) & 0xF000, - info->u.type1.IOLimit ? - ((u16)info->u.type1.IOLimit << 8) | 0xFFF : 0, - ((u32)info->u.type1.MemoryBase << 16) & 0xFFF00000, - info->u.type1.MemoryLimit ? - ((u32)info->u.type1.MemoryLimit << 16) | 0xFFFFF : 0, - ((u32)info->u.type1.PrefetchableMemoryBase << 16) & 0xFFF00000, - info->u.type1.PrefetchableMemoryLimit ? - ((u32)info->u.type1.PrefetchableMemoryLimit << 16) | 0xFFFFF : 0, - info->u.type1.BridgeControl); - } - printf("\n"); -} - -/**************************************************************************** -RETURNS: -Number of display devices found. - -REMARKS: -This function enumerates the number of available display devices on the -PCI bus, and returns the number found. -****************************************************************************/ -static int PCI_enumerateDevices(void) -{ - int i,j; - PCIDeviceInfo *info; - - /* If this is the first time we have been called, enumerate all */ - /* devices on the PCI bus. */ - if (NumPCI == -1) { - if ((NumPCI = PCI_getNumDevices()) == 0) - return -1; - PCI = malloc(NumPCI * sizeof(PCI[0])); - BridgeIndex = malloc(NumPCI * sizeof(BridgeIndex[0])); - DeviceIndex = malloc(NumPCI * sizeof(DeviceIndex[0])); - if (!PCI || !BridgeIndex || !DeviceIndex) - return -1; - for (i = 0; i < NumPCI; i++) - PCI[i].dwSize = sizeof(PCI[i]); - if (PCI_enumerate(PCI) == 0) - return -1; - - /* Build a list of all PCI bridge devices */ - for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) { - if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) - BridgeIndex[NumBridges++] = i; - } - - /* Now build a list of all display class devices */ - for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) { - if (PCI_IS_DISPLAY_CLASS(&PCI[i])) { - if ((PCI[i].Command & 0x3) == 0x3) - DeviceIndex[0] = i; - else - DeviceIndex[NumDevices++] = i; - if (PCI[i].slot.p.Bus != 0) { - /* This device is on a different bus than the primary */ - /* PCI bus, so it is probably an AGP device. Find the */ - /* AGP bus device that controls that bus so we can */ - /* control it. */ - for (j = 0; j < NumBridges; j++) { - info = (PCIDeviceInfo*)&PCI[BridgeIndex[j]]; - if (info->u.type1.SecondayBusNumber == PCI[i].slot.p.Bus) { - AGPBridge = info; - break; - } - } - } - } - } - - /* Enumerate all PCI and bridge devices to standard output */ - EnumeratePCI(); - } - return NumDevices; -} - -int main(void) -{ - /* Enumerate all PCI devices */ - PM_init(); - if (PCI_enumerateDevices() < 1) { - printf("No PCI display devices found!\n"); - return -1; - } - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c b/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c deleted file mode 100644 index 378725e..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c +++ /dev/null @@ -1,94 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to install a C based -* timer interrupt handler. -* -* Functions tested: PM_setTimerHandler() -* PM_chainPrevTimer(); -* PM_restoreTimerHandler() -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -volatile long count = 0; - -#pragma off (check_stack) /* No stack checking under Watcom */ - -void PMAPI timerHandler(void) -{ - PM_chainPrevTimer(); /* Chain to previous handler */ - count++; -} - -int main(void) -{ - long oldCount; - PM_lockHandle lh; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - /* Install our timer handler and lock handler pages in memory. It is - * difficult to get the size of a function in C, but we know our - * function is well less than 100 bytes (and an entire 4k page will - * need to be locked by the server anyway). - */ - PM_lockCodePages((__codePtr)timerHandler,100,&lh); - PM_lockDataPages((void*)&count,sizeof(count),&lh); - PM_installBreakHandler(); /* We *DONT* want Ctrl-Breaks! */ - PM_setTimerHandler(timerHandler); - printf("Timer interrupt handler installed - Hit ESC to exit\n"); - oldCount = count; - while (1) { - if (PM_kbhit() && (PM_getch() == 0x1B)) - break; - if (count != oldCount) { - printf("Tick, Tock: %ld\n", count); - oldCount = count; - } - } - - PM_restoreTimerHandler(); - PM_restoreBreakHandler(); - PM_unlockDataPages((void*)&count,sizeof(count),&lh); - PM_unlockCodePages((__codePtr)timerHandler,100,&lh); - printf("Timer handler was called %ld times\n", count); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c deleted file mode 100644 index 7fa77b7..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Test program for the Zen Timer Library. -* -****************************************************************************/ - -#include -#include "pmapi.h" -#include "ztimer.h" - -#define DELAY_SECS 10 - -/*-------------------------- Implementation -------------------------------*/ - -/* The following routine takes a long count in microseconds and outputs - * a string representing the count in seconds. It could be modified to - * return a pointer to a static string representing the count rather - * than printing it out. - */ - -void ReportTime(ulong count) -{ - ulong secs; - - secs = count / 1000000L; - count = count - secs * 1000000L; - printf("Time taken: %lu.%06lu seconds\n",secs,count); -} - -int i,j; /* NON register variables! */ - -int main(void) -{ -#ifdef LONG_TEST - ulong start,finish; -#endif - - printf("Processor type: %d %ld MHz\n", CPU_getProcessorType(), CPU_getProcessorSpeed(true)); - - ZTimerInit(); - - /* Test the long period Zen Timer (we don't check for overflow coz - * it would take tooooo long!) - */ - - LZTimerOn(); - for (j = 0; j < 10; j++) - for (i = 0; i < 20000; i++) - i = i; - LZTimerOff(); - ReportTime(LZTimerCount()); - - /* Test the ultra long period Zen Timer */ -#ifdef LONG_TEST - start = ULZReadTime(); - delay(DELAY_SECS * 1000); - finish = ULZReadTime(); - printf("Delay of %d secs took %d 1/10ths of a second\n", - DELAY_SECS,ULZElapsedTime(start,finish)); -#endif - - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp b/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp deleted file mode 100644 index 1258a4b..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: C++ 3.0 -* Environment: Any -* -* Description: Test program for the Zen Timer Library C++ interface. -* -****************************************************************************/ - -#include -#include "pmapi.h" -#include "ztimer.h" - -/*-------------------------- Implementation -------------------------------*/ - -int i,j,k; /* NON register variables! */ - -void dummy() {} - -int main(void) -{ - LZTimer ltimer; - ULZTimer ultimer; - - ZTimerInit(); - - /* Test the long period Zen Timer (we don't check for overflow coz - * it would take tooooo long!) - */ - - cout << endl; - ultimer.restart(); - ltimer.start(); - for (j = 0; j < 10; j++) - for (i = 0; i < 20000; i++) - dummy(); - ltimer.stop(); - ultimer.stop(); - cout << "LCount: " << ltimer.count() << endl; - cout << "Time: " << ltimer << " secs\n"; - cout << "ULCount: " << ultimer.count() << endl; - cout << "ULTime: " << ultimer << " secs\n"; - - cout << endl << "Timing ... \n"; - ultimer.restart(); - ltimer.restart(); - for (j = 0; j < 200; j++) - for (i = 0; i < 20000; i++) - dummy(); - ltimer.stop(); - ultimer.stop(); - cout << "LCount: " << ltimer.count() << endl; - cout << "Time: " << ltimer << " secs\n"; - cout << "ULCount: " << ultimer.count() << endl; - cout << "ULTime: " << ultimer << " secs\n"; - - /* Test the lap function of the long period Zen Timer */ - - cout << endl << "Timing ... \n"; - ultimer.restart(); - ltimer.restart(); - for (j = 0; j < 20; j++) { - for (k = 0; k < 10; k++) - for (i = 0; i < 20000; i++) - dummy(); - cout << "lap: " << ltimer.lap() << endl; - } - ltimer.stop(); - ultimer.stop(); - cout << "LCount: " << ltimer.count() << endl; - cout << "Time: " << ltimer << " secs\n"; - cout << "ULCount: " << ultimer.count() << endl; - cout << "ULTime: " << ultimer << " secs\n"; - -#ifdef LONG_TEST - /* Test the ultra long period Zen Timer */ - - ultimer.start(); - delay(DELAY_SECS * 1000); - ultimer.stop(); - cout << "Delay of " << DELAY_SECS << " secs took " << ultimer.count() - << " 1/10ths of a second\n"; - cout << "Time: " << ultimer << " secs\n"; -#endif - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c deleted file mode 100644 index f0c7bd6..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c +++ /dev/null @@ -1,311 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: any -* -* Description: Simple test program to test the write combine functions. -* -* Note that this program should never be used in a production -* environment, because write combining needs to be handled -* with more intimate knowledge of the display hardware than -* you can obtain by simply examining the PCI configuration -* space. -* -****************************************************************************/ - -#include "pmapi.h" -#include "pcilib.h" -#include -#include -#include -#include - -/*------------------------- Global Variables ------------------------------*/ - -static int NumPCI = -1; -static PCIDeviceInfo *PCI; -static int *BridgeIndex; -static int *DeviceIndex; -static int NumBridges; -static PCIDeviceInfo *AGPBridge = NULL; -static int NumDevices; - -/*-------------------------- Implementation -------------------------------*/ - -/**************************************************************************** -RETURNS: -Number of display devices found. - -REMARKS: -This function enumerates the number of available display devices on the -PCI bus, and returns the number found. -****************************************************************************/ -static int PCI_enumerateDevices(void) -{ - int i,j; - PCIDeviceInfo *info; - - /* If this is the first time we have been called, enumerate all */ - /* devices on the PCI bus. */ - if (NumPCI == -1) { - if ((NumPCI = PCI_getNumDevices()) == 0) - return -1; - PCI = malloc(NumPCI * sizeof(PCI[0])); - BridgeIndex = malloc(NumPCI * sizeof(BridgeIndex[0])); - DeviceIndex = malloc(NumPCI * sizeof(DeviceIndex[0])); - if (!PCI || !BridgeIndex || !DeviceIndex) - return -1; - for (i = 0; i < NumPCI; i++) - PCI[i].dwSize = sizeof(PCI[i]); - if (PCI_enumerate(PCI) == 0) - return -1; - - /* Build a list of all PCI bridge devices */ - for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) { - if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) - BridgeIndex[NumBridges++] = i; - } - - /* Now build a list of all display class devices */ - for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) { - if (PCI_IS_DISPLAY_CLASS(&PCI[i])) { - if ((PCI[i].Command & 0x3) == 0x3) - DeviceIndex[0] = i; - else - DeviceIndex[NumDevices++] = i; - if (PCI[i].slot.p.Bus != 0) { - /* This device is on a different bus than the primary */ - /* PCI bus, so it is probably an AGP device. Find the */ - /* AGP bus device that controls that bus so we can */ - /* control it. */ - for (j = 0; j < NumBridges; j++) { - info = (PCIDeviceInfo*)&PCI[BridgeIndex[j]]; - if (info->u.type1.SecondayBusNumber == PCI[i].slot.p.Bus) { - AGPBridge = info; - break; - } - } - } - } - } - } - return NumDevices; -} - -/**************************************************************************** -REMARKS: -Enumerates useful information about attached display devices. -****************************************************************************/ -static void ShowDisplayDevices(void) -{ - int i,index; - - printf("Displaying enumeration of %d PCI display devices\n", NumDevices); - printf("\n"); - printf("DeviceID SubSystem Base10h (length ) Base14h (length )\n"); - for (index = 0; index < NumDevices; index++) { - i = DeviceIndex[index]; - printf("%04X:%04X %04X:%04X %08lX (%6ld KB) %08lX (%6ld KB)\n", - PCI[i].VendorID, - PCI[i].DeviceID, - PCI[i].u.type0.SubSystemVendorID, - PCI[i].u.type0.SubSystemID, - PCI[i].u.type0.BaseAddress10, - PCI[i].u.type0.BaseAddress10Len / 1024, - PCI[i].u.type0.BaseAddress14, - PCI[i].u.type0.BaseAddress14Len / 1024); - } - printf("\n"); -} - -/**************************************************************************** -REMARKS: -Dumps the value for a write combine region to the display. -****************************************************************************/ -static char *DecodeWCType( - uint type) -{ - static char *names[] = { - "UNCACHABLE", - "WRCOMB", - "UNKNOWN", - "UNKNOWN", - "WRTHROUGH", - "WRPROT", - "WRBACK", - }; - if (type <= PM_MTRR_MAX) - return names[type]; - return "UNKNOWN"; -} - -/**************************************************************************** -REMARKS: -Dumps the value for a write combine region to the display. -****************************************************************************/ -static void PMAPI EnumWriteCombine( - ulong base, - ulong length, - uint type) -{ - printf("%08lX %-10ld %s\n", base, length / 1024, DecodeWCType(type)); -} - -/**************************************************************************** -PARAMETERS: -err - Error to log - -REMARKS: -Function to log an error message if the MTRR write combining attempt failed. -****************************************************************************/ -static void LogMTRRError( - int err) -{ - if (err == PM_MTRR_ERR_OK) - return; - switch (err) { - case PM_MTRR_NOT_SUPPORTED: - printf("Failed: MTRR is not supported by host CPU\n"); - break; - case PM_MTRR_ERR_PARAMS: - printf("Failed: Invalid parameters passed to PM_enableWriteCombined!\n"); - break; - case PM_MTRR_ERR_NOT_4KB_ALIGNED: - printf("Failed: Address is not 4Kb aligned!\n"); - break; - case PM_MTRR_ERR_BELOW_1MB: - printf("Failed: Addresses below 1Mb cannot be write combined!\n"); - break; - case PM_MTRR_ERR_NOT_ALIGNED: - printf("Failed: Address is not correctly aligned for processor!\n"); - break; - case PM_MTRR_ERR_OVERLAP: - printf("Failed: Address overlaps an existing region!\n"); - break; - case PM_MTRR_ERR_TYPE_MISMATCH: - printf("Failed: Adress is contained with existing region, but type is different!\n"); - break; - case PM_MTRR_ERR_NONE_FREE: - printf("Failed: Out of MTRR registers!\n"); - break; - case PM_MTRR_ERR_NOWRCOMB: - printf("Failed: This processor does not support write combining!\n"); - break; - case PM_MTRR_ERR_NO_OS_SUPPORT: - printf("Failed: MTRR is not supported by host OS\n"); - break; - default: - printf("Failed: UNKNOWN ERROR!\n"); - break; - } - exit(-1); -} - -/**************************************************************************** -REMARKS: -Shows all write combine regions. -****************************************************************************/ -static void ShowWriteCombine(void) -{ - printf("Base Length(KB) Type\n"); - LogMTRRError(PM_enumWriteCombine(EnumWriteCombine)); - printf("\n"); -} - -/**************************************************************************** -REMARKS: -Dumps the value for a write combine region to the display. -****************************************************************************/ -static void EnableWriteCombine(void) -{ - int i,index; - - for (index = 0; index < NumDevices; index++) { - i = DeviceIndex[index]; - if (PCI[i].u.type0.BaseAddress10 & 0x8) { - LogMTRRError(PM_enableWriteCombine( - PCI[i].u.type0.BaseAddress10 & 0xFFFFFFF0, - PCI[i].u.type0.BaseAddress10Len, - PM_MTRR_WRCOMB)); - } - if (PCI[i].u.type0.BaseAddress14 & 0x8) { - LogMTRRError(PM_enableWriteCombine( - PCI[i].u.type0.BaseAddress14 & 0xFFFFFFF0, - PCI[i].u.type0.BaseAddress14Len, - PM_MTRR_WRCOMB)); - } - } - printf("\n"); - ShowDisplayDevices(); - ShowWriteCombine(); -} - -/**************************************************************************** -REMARKS: -Dumps the value for a write combine region to the display. -****************************************************************************/ -static void DisableWriteCombine(void) -{ - int i,index; - - for (index = 0; index < NumDevices; index++) { - i = DeviceIndex[index]; - if (PCI[i].u.type0.BaseAddress10 & 0x8) { - LogMTRRError(PM_enableWriteCombine( - PCI[i].u.type0.BaseAddress10 & 0xFFFFFFF0, - PCI[i].u.type0.BaseAddress10Len, - PM_MTRR_UNCACHABLE)); - } - if (PCI[i].u.type0.BaseAddress14 & 0x8) { - LogMTRRError(PM_enableWriteCombine( - PCI[i].u.type0.BaseAddress14 & 0xFFFFFFF0, - PCI[i].u.type0.BaseAddress14Len, - PM_MTRR_UNCACHABLE)); - } - } - printf("\n"); - ShowDisplayDevices(); - ShowWriteCombine(); -} - -int main(int argc,char *argv[]) -{ - PM_init(); - if (PCI_enumerateDevices() < 1) { - printf("No PCI display devices found!\n"); - return -1; - } - if (argc < 2) { - printf("usage: uswc [-show -on -off]\n\n"); - ShowDisplayDevices(); - return -1; - } - if (stricmp(argv[1],"-show") == 0) - ShowWriteCombine(); - else if (stricmp(argv[1],"-on") == 0) - EnableWriteCombine(); - else if (stricmp(argv[1],"-off") == 0) - DisableWriteCombine(); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c b/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c deleted file mode 100644 index b7e3bb7..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c +++ /dev/null @@ -1,78 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Filename: $Workfile$ -* Version: $Revision: 1.1 $ -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to test the VFlat virtual framebuffer functions. -* -* Functions tested: VF_available() -* VF_init() -* VF_exit() -* -* $Date: 2002/10/02 15:35:21 $ $Author: hfrieden $ -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -uchar code[] = { - 0xC3, /* ret */ - }; - -int main(void) -{ - void *vfBuffer; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - if (!VF_available()) { - printf("Virtual Linear Framebuffer not available.\n"); - exit(1); - } - - vfBuffer = VF_init(0xA0000,64,sizeof(code),code); - if (!vfBuffer) { - printf("Failure to initialise Virtual Linear Framebuffer!\n"); - exit(1); - } - VF_exit(); - printf("Virtual Linear Framebuffer set up successfully!\n"); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/video.c b/board/MAI/bios_emulator/scitech/src/pm/tests/video.c deleted file mode 100644 index 92adcdd..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/tests/video.c +++ /dev/null @@ -1,199 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: any -* -* Description: Test program to check the ability to generate real mode -* interrupts and to be able to obtain direct access to the -* video memory from protected mode. Compile and link with -* the appropriate command line for your DOS extender. -* -* Functions tested: PM_getBIOSSelector() -* PM_mapPhysicalAddr() -* PM_int86() -* -****************************************************************************/ - -#include -#include -#include "pmapi.h" - -uchar *bios; /* Pointer to BIOS data area */ -uchar *videoPtr; /* Pointer to VGA framebuffer */ -void *stateBuf; /* Console state save buffer */ - -/* Routine to return the current video mode number */ - -int getVideoMode(void) -{ - return PM_getByte(bios+0x49); -} - -/* Routine to set a specified video mode */ - -void setVideoMode(int mode) -{ - RMREGS r; - - r.x.ax = mode; - PM_int86(0x10, &r, &r); -} - -/* Routine to clear a rectangular region on the display by calling the - * video BIOS. - */ - -void clearScreen(int startx, int starty, int endx, int endy, unsigned char attr) -{ - RMREGS r; - - r.x.ax = 0x0600; - r.h.bh = attr; - r.h.cl = startx; - r.h.ch = starty; - r.h.dl = endx; - r.h.dh = endy; - PM_int86(0x10, &r, &r); -} - -/* Routine to fill a rectangular region on the display using direct - * video writes. - */ - -#define SCREEN(x,y) (videoPtr + ((y) * 160) + ((x) << 1)) - -void fill(int startx, int starty, int endx, int endy, unsigned char c, - unsigned char attr) -{ - unsigned char *v; - int x,y; - - for (y = starty; y <= endy; y++) { - v = SCREEN(startx,y); - for (x = startx; x <= endx; x++) { - *v++ = c; - *v++ = attr; - } - } -} - -/* Routine to display a single character using direct video writes */ - -void writeChar(int x, int y, unsigned char c, unsigned char attr) -{ - unsigned char *v = SCREEN(x,y); - *v++ = c; - *v = attr; -} - -/* Routine to draw a border around a rectangular area using direct video - * writes. - */ - -static unsigned char border_chars[] = { - 186, 205, 201, 187, 200, 188 /* double box chars */ - }; - -void border(int startx, int starty, int endx, int endy, unsigned char attr) -{ - unsigned char *v; - unsigned char *b; - int i; - - b = border_chars; - - for (i = starty+1; i < endy; i++) { - writeChar(startx, i, *b, attr); - writeChar(endx, i, *b, attr); - } - b++; - for (i = startx+1, v = SCREEN(startx+1, starty); i < endx; i++) { - *v++ = *b; - *v++ = attr; - } - for (i = startx+1, v = SCREEN(startx+1, endy); i < endx; i++) { - *v++ = *b; - *v++ = attr; - } - b++; - writeChar(startx, starty, *b++, attr); - writeChar(endx, starty, *b++, attr); - writeChar(startx, endy, *b++, attr); - writeChar(endx, endy, *b++, attr); -} - -int main(void) -{ - int orgMode; - PM_HWND hwndConsole; - - printf("Program running in "); - switch (PM_getModeType()) { - case PM_realMode: - printf("real mode.\n\n"); - break; - case PM_286: - printf("16 bit protected mode.\n\n"); - break; - case PM_386: - printf("32 bit protected mode.\n\n"); - break; - } - - hwndConsole = PM_openConsole(0,0,0,0,0,true); - printf("Hit any key to start 80x25 text mode and perform some direct video output.\n"); - PM_getch(); - - /* Allocate a buffer to save console state and save the state */ - if ((stateBuf = PM_malloc(PM_getConsoleStateSize())) == NULL) { - printf("Unable to allocate console state buffer!\n"); - exit(1); - } - PM_saveConsoleState(stateBuf,0); - bios = PM_getBIOSPointer(); - orgMode = getVideoMode(); - setVideoMode(0x3); - if ((videoPtr = PM_mapPhysicalAddr(0xB8000,0xFFFF,true)) == NULL) { - printf("Unable to obtain pointer to framebuffer!\n"); - exit(1); - } - - /* Draw some text on the screen */ - fill(0, 0, 79, 24, 176, 0x1E); - border(0, 0, 79, 24, 0x1F); - PM_getch(); - clearScreen(0, 0, 79, 24, 0x7); - - /* Restore the console state on exit */ - PM_restoreConsoleState(stateBuf,0); - PM_free(stateBuf); - PM_closeConsole(hwndConsole); - - /* Display useful status information */ - printf("\n"); - printf("Original Video Mode = %02X\n", orgMode); - printf("BIOS Pointer = %08X\n", (int)bios); - printf("Video Memory = %08X\n", (int)videoPtr); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c deleted file mode 100644 index 3460b72..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit OS/2 VDD -* -* Description: VDD specific code for the CPU detection module. -* -****************************************************************************/ - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Do nothing for VDD's -****************************************************************************/ -#define SetMaxThreadPriority() 0 - -/**************************************************************************** -REMARKS: -Do nothing for VDD's -****************************************************************************/ -#define RestoreThreadPriority(i) (void)(i) - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - freq->low = 100000; - freq->high = 0; -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. -****************************************************************************/ -#define GetCounter(t) \ -{ \ - ULONG count; \ - count = VDHQuerySysValue(0, VDHGSV_MSECSBOOT); \ - (t)->low = count * 100; \ - (t)->high = 0; \ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c deleted file mode 100644 index 93742de..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c +++ /dev/null @@ -1,359 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit OS/2 VDD -* -* Description: C library compatible I/O functions for use within a VDD. -* -****************************************************************************/ - -#include "pmapi.h" -#include "vddfile.h" - -/*------------------------ Main Code Implementation -----------------------*/ - -#define EOF -1 - -/* NB: none of the file VDHs are available during the DOS session */ -/* initialzation context! */ - -/* Macros for Open/Close APIs to allow using this module in both VDDs and */ -/* normal OS/2 applications. Unfortunately VDHRead/Write/Seek don't map to */ -/* their Dos* counterparts so cleanly. */ -#ifdef __OS2_VDD__ -#define _OS2Open VDHOpen -#define _OS2Close VDHClose -#else -#define _OS2Open DosOpen -#define _OS2Close DosClose -#endif - -/**************************************************************************** -REMARKS: -VDD implementation of the ANSI C fopen function. -****************************************************************************/ -FILE * fopen( - const char *filename, - const char *mode) -{ - FILE *f = PM_malloc(sizeof(FILE)); - long oldpos; - ULONG rc, ulAction; - ULONG omode, oflags; - - if (f != NULL) { - f->offset = 0; - f->text = (mode[1] == 't' || mode[2] == 't'); - f->writemode = (mode[0] == 'w') || (mode[0] == 'a'); - f->unputc = EOF; - f->endp = f->buf + sizeof(f->buf); - f->curp = f->startp = f->buf; - - if (mode[0] == 'r') { - #ifdef __OS2_VDD__ - omode = VDHOPEN_ACCESS_READONLY | VDHOPEN_SHARE_DENYNONE; - oflags = VDHOPEN_ACTION_OPEN_IF_EXISTS | VDHOPEN_ACTION_FAIL_IF_NEW; - #else - omode = OPEN_ACCESS_READONLY | OPEN_SHARE_DENYNONE; - oflags = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_FAIL_IF_NEW; - #endif - } - else if (mode[0] == 'w') { - #ifdef __OS2_VDD__ - omode = VDHOPEN_ACCESS_WRITEONLY | VDHOPEN_SHARE_DENYWRITE; - oflags = VDHOPEN_ACTION_REPLACE_IF_EXISTS | VDHOPEN_ACTION_CREATE_IF_NEW; - #else - omode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_DENYWRITE; - oflags = OPEN_ACTION_REPLACE_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; - #endif - } - else { - #ifdef __OS2_VDD__ - omode = VDHOPEN_ACCESS_READWRITE | VDHOPEN_SHARE_DENYWRITE; - oflags = VDHOPEN_ACTION_OPEN_IF_EXISTS | VDHOPEN_ACTION_CREATE_IF_NEW; - #else - omode = OPEN_ACCESS_READWRITE | OPEN_SHARE_DENYWRITE; - oflags = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; - #endif - } - rc = _OS2Open((PSZ)filename, (PHFILE)&f->handle, &ulAction, 0, VDHOPEN_FILE_NORMAL, oflags, omode, NULL); - if (rc != 0) { - PM_free(f); - return NULL; - } - - #ifdef __OS2_VDD__ - f->filesize = VDHSeek((HFILE)f->handle, 0, VDHSK_END_OF_FILE); - #else - rc = DosSetFilePtr((HFILE)f->handle, 0, FILE_END, &f->filesize); - #endif - - if (mode[0] == 'a') - fseek(f,0,2); - } - return f; -} - -/**************************************************************************** -REMARKS: -VDD implementation of the ANSI C fread function. Note that unlike Windows VxDs, -OS/2 VDDs are not limited to 64K reads or writes. -****************************************************************************/ -size_t fread( - void *ptr, - size_t size, - size_t n, - FILE *f) -{ - char *buf = ptr; - int bytes,readbytes,totalbytes = 0; - - /* First copy any data already read into our buffer */ - if ((bytes = (f->curp - f->startp)) > 0) { - memcpy(buf,f->curp,bytes); - f->startp = f->curp = f->buf; - buf += bytes; - totalbytes += bytes; - bytes = (size * n) - bytes; - } - else - bytes = size * n; - if (bytes) { - #ifdef __OS2_VDD__ - readbytes = VDHRead((HFILE)f->handle, buf, bytes); - #else - DosRead((HFILE)f->handle, buf, bytes, &readbytes); - #endif - totalbytes += readbytes; - f->offset += readbytes; - } - return totalbytes / size; -} - -/**************************************************************************** -REMARKS: -VDD implementation of the ANSI C fwrite function. -****************************************************************************/ -size_t fwrite( - void *ptr, - size_t size, - size_t n, - FILE *f) -{ - char *buf = ptr; - int bytes,writtenbytes,totalbytes = 0; - - /* Flush anything already in the buffer */ - if (!f->writemode) - return 0; - fflush(f); - bytes = size * n; - #ifdef __OS2_VDD__ - writtenbytes = VDHWrite((HFILE)f->handle, buf, bytes); - #else - DosWrite((HFILE)f->handle, buf, bytes, &writtenbytes); - #endif - totalbytes += writtenbytes; - f->offset += writtenbytes; - if (f->offset > f->filesize) - f->filesize = f->offset; - return totalbytes / size; -} - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C fflush function. -****************************************************************************/ -int fflush( - FILE *f) -{ - ULONG bytes; - - /* First copy any data already written into our buffer */ - if (f->writemode && (bytes = (f->curp - f->startp)) > 0) { - #ifdef __OS2_VDD__ - bytes = VDHWrite((HFILE)f->handle, f->startp, bytes); - #else - DosWrite((HFILE)f->handle, f->startp, bytes, &bytes); - #endif - f->offset += bytes; - if (f->offset > f->filesize) - f->filesize = f->offset; - f->startp = f->curp = f->buf; - } - return 0; -} - -/**************************************************************************** -REMARKS: -VDD implementation of the ANSI C fseek function. -****************************************************************************/ -int fseek( - FILE *f, - long int offset, - int whence) -{ - fflush(f); - - if (whence == 0) - f->offset = offset; - else if (whence == 1) - f->offset += offset; - else if (whence == 2) - f->offset = f->filesize + offset; - - #ifdef __OS2_VDD__ - VDHSeek((HFILE)f->handle, f->offset, VDHSK_ABSOLUTE); - #else - DosSetFilePtr((HFILE)f->handle, f->offset, FILE_BEGIN, NULL); - #endif - - return 0; -} - -/**************************************************************************** -REMARKS: -VDD implementation of the ANSI C ftell function. -****************************************************************************/ -long ftell( - FILE *f) -{ - long offset; - - offset = (f->curp - f->startp); - offset += f->offset; - return offset; -} - -/**************************************************************************** -REMARKS: -VDD implementation of the ANSI C feof function. -****************************************************************************/ -int feof( - FILE *f) -{ - return (f->offset == f->filesize); -} - -/**************************************************************************** -REMARKS: -Read a single character from the input file buffer, including translation -of the character in text transation modes. -****************************************************************************/ -static int __getc( - FILE *f) -{ - int c; - - if (f->unputc != EOF) { - c = f->unputc; - f->unputc = EOF; - } - else { - if (f->startp == f->curp) { - int bytes = fread(f->buf,1,sizeof(f->buf),f); - if (bytes == 0) - return EOF; - f->curp = f->startp + bytes; - } - c = *f->startp++; - if (f->text && c == '\r') { - int nc = __getc(f); - if (nc != '\n') - f->unputc = nc; - } - } - return c; -} - -/**************************************************************************** -REMARKS: -Write a single character from to input buffer, including translation of the -character in text transation modes. -****************************************************************************/ -static int __putc(int c,FILE *f) -{ - int count = 1; - if (f->text && c == '\n') { - __putc('\r',f); - count = 2; - } - if (f->curp == f->endp) - fflush(f); - *f->curp++ = c; - return count; -} - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C fgets function. -****************************************************************************/ -char *fgets( - char *s, - int n, - FILE *f) -{ - int c = 0; - char *cs; - - cs = s; - while (--n > 0 && (c = __getc(f)) != EOF) { - *cs++ = c; - if (c == '\n') - break; - } - if (c == EOF && cs == s) - return NULL; - *cs = '\0'; - return s; -} - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C fputs function. -****************************************************************************/ -int fputs( - const char *s, - FILE *f) -{ - int r = 0; - int c; - - while ((c = *s++) != 0) - r = __putc(c, f); - return r; -} - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C fclose function. -****************************************************************************/ -int fclose( - FILE *f) -{ - fflush(f); - _OS2Close((HFILE)f->handle); - PM_free(f); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h deleted file mode 100644 index 03286bd..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h +++ /dev/null @@ -1,29 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit OS/2 VDD -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c deleted file mode 100644 index 6688bab..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c +++ /dev/null @@ -1,1050 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit OS/2 VDD -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include "sdd/sddhelp.h" -#include "mtrr.h" - -#define TRACE(a) - -/*--------------------------- Global variables ----------------------------*/ - -#define MAX_MEMORY_SHARED 100 -#define MAX_MEMORY_MAPPINGS 100 - -/* TODO: I think the global and linear members will be the same, but not sure yet. */ -typedef struct { - void *linear; - ulong global; - ulong length; - int npages; - } memshared; - -typedef struct { - ulong physical; - ulong linear; - ulong length; - int npages; - ibool isCached; - } mmapping; - -static int numMappings = 0; -static memshared shared[MAX_MEMORY_MAPPINGS] = {0}; -static mmapping maps[MAX_MEMORY_MAPPINGS]; -ibool _PM_haveBIOS = TRUE; -char _PM_cntPath[PM_MAX_PATH] = ""; /* there just isn't any */ -uchar *_PM_rmBufAddr = NULL; -ushort _VARAPI PM_savedDS = 0; /* why can't I use the underscore prefix? */ - -HVDHSEM hevFarCallRet = NULL; -HVDHSEM hevIRet = NULL; -HHOOK hhookUserReturnHook = NULL; -HHOOK hhookUserIRetHook = NULL; - -static void (PMAPIP fatalErrorCleanup)(void) = NULL; - -/*----------------------------- Implementation ----------------------------*/ - -/* Functions to read and write CMOS registers */ - -ulong PMAPI _PM_getPDB(void); -uchar PMAPI _PM_readCMOS(int index); -void PMAPI _PM_writeCMOS(int index,uchar value); - -VOID HOOKENTRY UserReturnHook(PVOID pRefData, PCRF pcrf); -VOID HOOKENTRY UserIRetHook(PVOID pRefData, PCRF pcrf); - -void PMAPI PM_init(void) -{ - MTRR_init(); - - /* Initialize VDD-specific data */ - /* Note: PM_init must be (obviously) called in VDM task context! */ - VDHCreateSem(&hevFarCallRet, VDH_EVENTSEM); - VDHCreateSem(&hevIRet, VDH_EVENTSEM); - hhookUserReturnHook = VDHAllocHook(VDH_RETURN_HOOK, (PFNARM)UserReturnHook, 0); - hhookUserIRetHook = VDHAllocHook(VDH_RETURN_HOOK, (PFNARM)UserIRetHook, 0); - - if ((hevIRet == NULL) || (hevFarCallRet == NULL) || - (hhookUserReturnHook == NULL) || (hhookUserIRetHook == NULL)) { - /* something failed, we can't go on */ - /* TODO: take some action here! */ - } -} - -/* Do some cleaning up */ -void PMAPI PM_exit(void) -{ - /* Note: Hooks allocated during or after VDM creation are deallocated automatically */ - if (hevIRet != NULL) - VDHDestroySem(hevIRet); - - if (hevFarCallRet != NULL) - VDHDestroySem(hevFarCallRet); -} - -ibool PMAPI PM_haveBIOSAccess(void) -{ return _PM_haveBIOS; } - -long PMAPI PM_getOSType(void) -{ return /*_OS_OS2VDD*/ _OS_OS2; } /*FIX!! */ - -int PMAPI PM_getModeType(void) -{ return PM_386; } - -void PMAPI PM_backslash(char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '\\') { - s[pos] = '\\'; - s[pos+1] = '\0'; - } -} - -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -void PMAPI PM_fatalError(const char *msg) -{ - if (fatalErrorCleanup) - fatalErrorCleanup(); -/* Fatal_Error_Handler(msg,0); TODO: implement somehow! */ -} - -/**************************************************************************** -PARAMETERS: -len - Place to store the length of the buffer -rseg - Place to store the real mode segment of the buffer -roff - Place to store the real mode offset of the buffer - -REMARKS: -This function returns the address and length of the global VESA transfer -buffer. -****************************************************************************/ -void * PMAPI PM_getVESABuf( - uint *len, - uint *rseg, - uint *roff) -{ - if (_PM_rmBufAddr) { - *len = 0; /*VESA_BUF_SIZE; */ - *rseg = (ulong)(_PM_rmBufAddr) >> 4; - *roff = (ulong)(_PM_rmBufAddr) & 0xF; - return _PM_rmBufAddr; - } - return NULL; -} - -int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out) -{ - /* Unused in VDDs */ - return 0; -} - -char * PMAPI PM_getCurrentPath(char *path,int maxLen) -{ - strncpy(path, _PM_cntPath, maxLen); - path[maxLen - 1] = 0; - return path; -} - -char PMAPI PM_getBootDrive(void) -{ - ulong boot = 3; - boot = VDHQuerySysValue(0, VDHGSV_BOOTDRV); - return (char)('a' + boot - 1); -} - -const char * PMAPI PM_getVBEAFPath(void) -{ - static char path[CCHMAXPATH]; - strcpy(path,"x:\\"); - path[0] = PM_getBootDrive(); - return path; -} - -const char * PMAPI PM_getNucleusPath(void) -{ - static char path[CCHMAXPATH]; - strcpy(path,"x:\\os2\\drivers"); - path[0] = PM_getBootDrive(); - PM_backslash(path); - strcat(path,"nucleus"); - return path; -} - -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[256]; - strcpy(path,PM_getNucleusPath()); - PM_backslash(path); - strcat(path,"config"); - return path; -} - -const char * PMAPI PM_getUniqueID(void) -{ return PM_getMachineName(); } - -const char * PMAPI PM_getMachineName(void) -{ - return "Unknown"; -} - -int PMAPI PM_kbhit(void) -{ return 1; } - -int PMAPI PM_getch(void) -{ return 0; } - -PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen) -{ - /* Unused in VDDs */ - return NULL; -} - -int PMAPI PM_getConsoleStateSize(void) -{ - /* Unused in VDDs */ - return 1; -} - -void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole) -{ - /* Unused in VDDs */ -} - -void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) -{ - /* Unused in VDDs */ -} - -void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) -{ - /* Unused in VDDs */ -} - -void PMAPI PM_closeConsole(PM_HWND hwndConsole) -{ - /* Unused in VDDs */ -} - -void PMAPI PM_setOSCursorLocation(int x,int y) -{ - uchar *_biosPtr = PM_getBIOSPointer(); - PM_setByte(_biosPtr+0x50,x); - PM_setByte(_biosPtr+0x51,y); -} - -void PMAPI PM_setOSScreenWidth(int width,int height) -{ - uchar *_biosPtr = PM_getBIOSPointer(); - PM_setByte(_biosPtr+0x4A,width); - PM_setByte(_biosPtr+0x84,height-1); -} - -/**************************************************************************** -REMARKS: -Allocate a block of shared memory. For OS/2 VDD we allocate shared memory -as locked, global memory that is accessible from any memory context -(including interrupt time context), which allows us to load our important -data structure and code such that we can access it directly from a ring -0 interrupt context. -****************************************************************************/ -void * PMAPI PM_mallocShared(long size) -{ - ULONG nPages = (size + 0xFFF) >> 12; - int i; - - /* First find a free slot in our shared memory table */ - for (i = 0; i < MAX_MEMORY_SHARED; i++) { - if (shared[i].linear == 0) - break; - } - if (i < MAX_MEMORY_SHARED) { - shared[i].linear = VDHAllocPages(NULL, nPages, VDHAP_SYSTEM | VDHAP_FIXED); - shared[i].npages = nPages; - shared[i].global = (ULONG)shared[i].linear; - return (void*)shared[i].global; - } - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a block of shared memory -****************************************************************************/ -void PMAPI PM_freeShared(void *p) -{ - int i; - - /* Find a shared memory block in our table and free it */ - for (i = 0; i < MAX_MEMORY_SHARED; i++) { - if (shared[i].global == (ulong)p) { - VDHFreePages(shared[i].linear); - shared[i].linear = 0; - break; - } - } -} - -void * PMAPI PM_mapToProcess(void *base,ulong limit) -{ return (void*)base; } - -ibool PMAPI PM_doBIOSPOST( - ushort axVal, - ulong BIOSPhysAddr, - void *mappedBIOS, - ulong BIOSLen) -{ - /* TODO: Figure out how to do this */ - return false; -} - -void * PMAPI PM_getBIOSPointer(void) -{ return (void*)0x400; } - -void * PMAPI PM_getA0000Pointer(void) -{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); } - -/**************************************************************************** -PARAMETERS: -base - Physical base address of the memory to maps in -limit - Limit of physical memory to region to maps in - -RETURNS: -Linear address of the newly mapped memory. - -REMARKS: -Maps a physical memory range to a linear memory range. -****************************************************************************/ -ulong MapPhysicalToLinear( - ulong base, - ulong limit, - int *npages) -{ - ulong linear,length = limit+1; - int i,ppage,flags; -#if 0 - ppage = base >> 12; - *npages = (length + (base & 0xFFF) + 4095) >> 12; - flags = PR_FIXED | PR_STATIC; - if (base == 0xA0000) { - /* We require the linear address to be aligned to a 64Kb boundary - * for mapping the banked framebuffer (so we can do efficient - * carry checking for bank changes in the assembler code). The only - * way to ensure this is to force the linear address to be aligned - * to a 4Mb boundary. - */ - flags |= PR_4MEG; - } - if ((linear = (ulong)PageReserve(PR_SYSTEM,*npages,flags)) == (ulong)-1) - return 0; - if (!PageCommitPhys(linear >> 12,*npages,ppage,PC_INCR | PC_USER | PC_WRITEABLE)) - return 0; -#endif - return linear + (base & 0xFFF); -} - -/**************************************************************************** -PARAMETERS: -base - Physical base address of the memory to map in -limit - Limit of physical memory to region to map in -isCached - True if the memory should be cached, false if not - -RETURNS: -Linear address of the newly mapped memory. - -REMARKS: -This function maps physical memory to linear memory, which can then be used -to create a selector or used directly from 32-bit protected mode programs. -This is better than DPMI 0x800, since it allows you to maps physical -memory below 1Mb, which gets this memory out of the way of the Windows VxD's -sticky paws. - -NOTE: If the memory is not expected to be cached, this function will - directly re-program the PCD (Page Cache Disable) bit in the - page tables. There does not appear to be a mechanism in the VMM - to control this bit via the regular interface. -****************************************************************************/ -void * PMAPI PM_mapPhysicalAddr( - ulong base, - ulong limit, - ibool isCached) -{ - ulong linear,length = limit+1; - int i,npages; - ulong PDB,*pPDB; - - /* Search table of existing mappings to see if we have already mapped - * a region of memory that will serve this purpose. - */ - for (i = 0; i < numMappings; i++) { - if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached) - return (void*)maps[i].linear; - } - if (numMappings == MAX_MEMORY_MAPPINGS) - return NULL; - - /* We did not find any previously mapped memory region, so map it in. - * Note that we do not use MapPhysToLinear, since this function appears - * to have problems mapping memory in the 1Mb physical address space. - * Hence we use PageReserve and PageCommitPhys. - */ - if ((linear = MapPhysicalToLinear(base,limit,&npages)) == 0) - return NULL; - maps[numMappings].physical = base; - maps[numMappings].length = length; - maps[numMappings].linear = linear; - maps[numMappings].npages = npages; - maps[numMappings].isCached = isCached; - numMappings++; - -#if 0 - /* Finally disable caching where necessary */ - if (!isCached && (PDB = _PM_getPDB()) != 0) { - int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; - ulong pageTable,*pPageTable; - - if (PDB >= 0x100000) - pPDB = (ulong*)MapPhysicalToLinear(PDB,0xFFF,&npages); - else - pPDB = (ulong*)PDB; - if (pPDB) { - startPDB = (linear >> 22) & 0x3FF; - startPage = (linear >> 12) & 0x3FF; - endPDB = ((linear+limit) >> 22) & 0x3FF; - endPage = ((linear+limit) >> 12) & 0x3FF; - for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { - pageTable = pPDB[iPDB] & ~0xFFF; - if (pageTable >= 0x100000) - pPageTable = (ulong*)MapPhysicalToLinear(pageTable,0xFFF,&npages); - else - pPageTable = (ulong*)pageTable; - start = (iPDB == startPDB) ? startPage : 0; - end = (iPDB == endPDB) ? endPage : 0x3FF; - for (iPage = start; iPage <= end; iPage++) - pPageTable[iPage] |= 0x10; - PageFree((ulong)pPageTable,PR_STATIC); - } - PageFree((ulong)pPDB,PR_STATIC); - } - } -#endif - return (void*)linear; -} - -void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) -{ - /* We never free the mappings */ -} - -void PMAPI PM_sleep(ulong milliseconds) -{ - /* We never sleep in a VDD */ -} - -int PMAPI PM_getCOMPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - } - return 0; -} - -int PMAPI PM_getLPTPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -ulong PMAPI PM_getPhysicalAddr(void *p) -{ - /* TODO: This function should find the physical address of a linear */ - /* address. */ - return 0xFFFFFFFFUL; -} - -void PMAPI _PM_freeMemoryMappings(void) -{ - int i; -/* for (i = 0; i < numMappings; i++) */ -/* PageFree(maps[i].linear,PR_STATIC); */ -} - -void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) -{ return (void*)MK_PHYS(r_seg,r_off); } - -void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) -{ return NULL; } - -void PMAPI PM_freeRealSeg(void *mem) -{ } - -void PMAPI DPMI_int86(int intno, DPMI_regs *regs) -{ - /* Unsed in VDDs */ -} - -/**************************************************************************** -REMARKS: -Load the V86 registers in the client state, and save the original state -before loading the registers. -****************************************************************************/ -static void LoadV86Registers( - PCRF saveRegs, - RMREGS *in, - RMSREGS *sregs) -{ - PCRF pcrf; /* current client register frame */ - - /* get pointer to registers */ - pcrf = (PCRF)VDHQuerySysValue(CURRENT_VDM, VDHLSV_PCRF); - - /* Note: We could do VDHPushRegs instead but this should be safer as it */ - /* doesn't rely on the VDM session having enough free stack space. */ - *saveRegs = *pcrf; /* save all registers */ - - pcrf->crf_eax = in->e.eax; /* load new values */ - pcrf->crf_ebx = in->e.ebx; - pcrf->crf_ecx = in->e.ecx; - pcrf->crf_edx = in->e.edx; - pcrf->crf_esi = in->e.esi; - pcrf->crf_edi = in->e.edi; - pcrf->crf_es = sregs->es; - pcrf->crf_ds = sregs->ds; - -} - -/**************************************************************************** -REMARKS: -Read the V86 registers from the client state and restore the original state. -****************************************************************************/ -static void ReadV86Registers( - PCRF saveRegs, - RMREGS *out, - RMSREGS *sregs) -{ - PCRF pcrf; /* current client register frame */ - - /* get pointer to registers */ - pcrf = (PCRF)VDHQuerySysValue(CURRENT_VDM, VDHLSV_PCRF); - - /* read new register values */ - out->e.eax = pcrf->crf_eax; - out->e.ebx = pcrf->crf_ebx; - out->e.ecx = pcrf->crf_ecx; - out->e.edx = pcrf->crf_edx; - out->e.esi = pcrf->crf_esi; - out->e.edi = pcrf->crf_edi; - sregs->es = pcrf->crf_es; - sregs->ds = pcrf->crf_ds; - - /* restore original client registers */ - *pcrf = *saveRegs; -} - -/**************************************************************************** -REMARKS: Used for far calls into V86 code -****************************************************************************/ -VOID HOOKENTRY UserReturnHook( - PVOID pRefData, - PCRF pcrf ) -{ - VDHPostEventSem(hevFarCallRet); -} - -/**************************************************************************** -REMARKS: Used for calling BIOS interrupts -****************************************************************************/ -VOID HOOKENTRY UserIRetHook( - PVOID pRefData, - PCRF pcrf ) -{ - VDHPostEventSem(hevIRet); -} - -/**************************************************************************** -REMARKS: -Call a V86 real mode function with the specified register values -loaded before the call. The call returns with a far ret. -Must be called from within a DOS session context! -****************************************************************************/ -void PMAPI PM_callRealMode( - uint seg, - uint off, - RMREGS *regs, - RMSREGS *sregs) -{ - CRF saveRegs; - FPFN fnAddress; - ULONG rc; - - TRACE("SDDHELP: Entering PM_callRealMode()\n"); - LoadV86Registers(SSToDS(&saveRegs),regs,sregs); - - /* set up return hook for call */ - rc = VDHArmReturnHook(hhookUserReturnHook, VDHARH_CSEIP_HOOK); - - VDHResetEventSem(hevFarCallRet); - - /* the address is a 16:32 pointer */ - OFFSETOF32(fnAddress) = off; - SEGMENTOF32(fnAddress) = seg; - rc = VDHPushFarCall(fnAddress); - VDHYield(0); - - /* wait until the V86 call returns - our return hook posts the semaphore */ - rc = VDHWaitEventSem(hevFarCallRet, SEM_INDEFINITE_WAIT); - - ReadV86Registers(SSToDS(&saveRegs),regs,sregs); - TRACE("SDDHELP: Exiting PM_callRealMode()\n"); -} - -/**************************************************************************** -REMARKS: -Issue a V86 real mode interrupt with the specified register values -loaded before the interrupt. -Must be called from within a DOS session context! -****************************************************************************/ -int PMAPI PM_int86( - int intno, - RMREGS *in, - RMREGS *out) -{ - RMSREGS sregs = {0}; - CRF saveRegs; - ushort oldDisable; - ULONG rc; - - memset(SSToDS(&sregs), 0, sizeof(sregs)); - -#if 0 /* do we need this?? */ - /* Disable pass-up to our VDD handler so we directly call BIOS */ - TRACE("SDDHELP: Entering PM_int86()\n"); - if (disableTSRFlag) { - oldDisable = *disableTSRFlag; - *disableTSRFlag = 0; - } -#endif - - LoadV86Registers(SSToDS(&saveRegs), in, SSToDS(&sregs)); - - VDHResetEventSem(hevIRet); - rc = VDHPushInt(intno); - - /* set up return hook for interrupt */ - rc = VDHArmReturnHook(hhookUserIRetHook, VDHARH_NORMAL_IRET); - - VDHYield(0); - - /* wait until the V86 IRETs - our return hook posts the semaphore */ - rc = VDHWaitEventSem(hevIRet, 5000); /*SEM_INDEFINITE_WAIT); */ - - ReadV86Registers(SSToDS(&saveRegs), out, SSToDS(&sregs)); - -#if 0 - /* Re-enable pass-up to our VDD handler if previously enabled */ - if (disableTSRFlag) - *disableTSRFlag = oldDisable; -#endif - - TRACE("SDDHELP: Exiting PM_int86()\n"); - return out->x.ax; - -} - -/**************************************************************************** -REMARKS: -Issue a V86 real mode interrupt with the specified register values -loaded before the interrupt. -****************************************************************************/ -int PMAPI PM_int86x( - int intno, - RMREGS *in, - RMREGS *out, - RMSREGS *sregs) -{ - CRF saveRegs; - ushort oldDisable; - ULONG rc; - -#if 0 - /* Disable pass-up to our VxD handler so we directly call BIOS */ - TRACE("SDDHELP: Entering PM_int86x()\n"); - if (disableTSRFlag) { - oldDisable = *disableTSRFlag; - *disableTSRFlag = 0; - } -#endif - LoadV86Registers(SSToDS(&saveRegs), in, sregs); - - VDHResetEventSem(hevIRet); - rc = VDHPushInt(intno); - - /* set up return hook for interrupt */ - rc = VDHArmReturnHook(hhookUserIRetHook, VDHARH_NORMAL_IRET); - - VDHYield(0); - - /* wait until the V86 IRETs - our return hook posts the semaphore */ - rc = VDHWaitEventSem(hevIRet, 5000); /*SEM_INDEFINITE_WAIT); */ - - ReadV86Registers(SSToDS(&saveRegs), out, sregs); - -#if 0 - /* Re-enable pass-up to our VxD handler if previously enabled */ - if (disableTSRFlag) - *disableTSRFlag = oldDisable; -#endif - - TRACE("SDDHELP: Exiting PM_int86x()\n"); - return out->x.ax; -} - -void PMAPI PM_availableMemory(ulong *physical,ulong *total) -{ *physical = *total = 0; } - -/**************************************************************************** -REMARKS: -Allocates a block of locked physical memory. -****************************************************************************/ -void * PMAPI PM_allocLockedMem( - uint size, - ulong *physAddr, - ibool contiguous, - ibool below16M) -{ - ULONG flags = VDHAP_SYSTEM; - ULONG nPages = (size + 0xFFF) >> 12; - - flags |= (physAddr != NULL) ? VDHAP_PHYSICAL : VDHAP_FIXED; - - return VDHAllocPages(physAddr, nPages, VDHAP_SYSTEM | VDHAP_PHYSICAL); -} - -/**************************************************************************** -REMARKS: -Frees a block of locked physical memory. -****************************************************************************/ -void PMAPI PM_freeLockedMem( - void *p, - uint size, - ibool contiguous) -{ - if (p) - VDHFreePages((PVOID)p); -} - -/**************************************************************************** -REMARKS: -Lock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - ULONG lockHandle; - - /* TODO: the lock handle is essential for the unlock operation!! */ - lockHandle = VDHLockMem(p, len, 0, (PVOID)VDHLM_NO_ADDR, NULL); - - if (lockHandle != NULL) - return 0; - else - return 1; -} - -/**************************************************************************** -REMARKS: -Unlock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - /* TODO: implement - use a table of lock handles? */ - /* VDHUnlockPages(lockHandle); */ - return 0; -} - -/**************************************************************************** -REMARKS: -Lock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - return PM_lockDataPages((void*)p,len,lh); -} - -/**************************************************************************** -REMARKS: -Unlock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - return PM_unlockDataPages((void*)p,len,lh); -} - -/**************************************************************************** -REMARKS: -OS specific shared libraries not supported inside a VDD -****************************************************************************/ -PM_MODULE PMAPI PM_loadLibrary( - const char *szDLLName) -{ - (void)szDLLName; - return NULL; -} - -/**************************************************************************** -REMARKS: -OS specific shared libraries not supported inside a VDD -****************************************************************************/ -void * PMAPI PM_getProcAddress( - PM_MODULE hModule, - const char *szProcName) -{ - (void)hModule; - (void)szProcName; - return NULL; -} - -/**************************************************************************** -REMARKS: -OS specific shared libraries not supported inside a VDD -****************************************************************************/ -void PMAPI PM_freeLibrary( - PM_MODULE hModule) -{ - (void)hModule; -} - -/**************************************************************************** -REMARKS: -Function to find the first file matching a search criteria in a directory. -****************************************************************************/ -void *PMAPI PM_findFirstFile( - const char *filename, - PM_findData *findData) -{ - /* TODO: This function should start a directory enumeration search */ - /* given the filename (with wildcards). The data should be */ - /* converted and returned in the findData standard form. */ - (void)filename; - (void)findData; - return PM_FILE_INVALID; -} - -/**************************************************************************** -REMARKS: -Function to find the next file matching a search criteria in a directory. -****************************************************************************/ -ibool PMAPI PM_findNextFile( - void *handle, - PM_findData *findData) -{ - /* TODO: This function should find the next file in directory enumeration */ - /* search given the search criteria defined in the call to */ - /* PM_findFirstFile. The data should be converted and returned */ - /* in the findData standard form. */ - (void)handle; - (void)findData; - return false; -} - -/**************************************************************************** -REMARKS: -Function to close the find process -****************************************************************************/ -void PMAPI PM_findClose( - void *handle) -{ - /* TODO: This function should close the find process. This may do */ - /* nothing for some OS'es. */ - (void)handle; -} - -/**************************************************************************** -REMARKS: -Function to determine if a drive is a valid drive or not. Under Unix this -function will return false for anything except a value of 3 (considered -the root drive, and equivalent to C: for non-Unix systems). The drive -numbering is: - - 1 - Drive A: - 2 - Drive B: - 3 - Drive C: - etc - -****************************************************************************/ -ibool PMAPI PM_driveValid( - char drive) -{ - /* Not applicable in a VDD */ - (void)drive; - return false; -} - -/**************************************************************************** -REMARKS: -Function to get the current working directory for the specififed drive. -Under Unix this will always return the current working directory regardless -of what the value of 'drive' is. -****************************************************************************/ -void PMAPI PM_getdcwd( - int drive, - char *dir, - int len) -{ - /* Not applicable in a VDD */ - (void)drive; - (void)dir; - (void)len; -} - -/**************************************************************************** -PARAMETERS: -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -RETURNS: -Error code describing the result. - -REMARKS: -Function to enable write combining for the specified region of memory. -****************************************************************************/ -int PMAPI PM_enableWriteCombine( - ulong base, - ulong size, - uint type) -{ - return MTRR_enableWriteCombine(base,size,type); -} - -/**************************************************************************** -REMARKS: -Function to change the file attributes for a specific file. -****************************************************************************/ -void PMAPI PM_setFileAttr( - const char *filename, - uint attrib) -{ - /* TODO: Implement this ? */ - (void)filename; - (void)attrib; - PM_fatalError("PM_setFileAttr not implemented!"); -} - -/**************************************************************************** -REMARKS: -Function to get the file attributes for a specific file. -****************************************************************************/ -uint PMAPI PM_getFileAttr( - const char *filename) -{ - /* TODO: Implement this ? */ - (void)filename; - PM_fatalError("PM_getFileAttr not implemented!"); - return 0; -} - -/**************************************************************************** -REMARKS: -Function to create a directory. -****************************************************************************/ -ibool PMAPI PM_mkdir( - const char *filename) -{ - /* TODO: Implement this ? */ - (void)filename; - PM_fatalError("PM_mkdir not implemented!"); - return false; -} - -/**************************************************************************** -REMARKS: -Function to remove a directory. -****************************************************************************/ -ibool PMAPI PM_rmdir( - const char *filename) -{ - /* TODO: Implement this ? */ - (void)filename; - PM_fatalError("PM_rmdir not implemented!"); - return false; -} - -/**************************************************************************** -REMARKS: -Function to get the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_getFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* TODO: Implement this ? */ - (void)filename; - (void)gmTime; - (void)time; - PM_fatalError("PM_getFileTime not implemented!"); - return false; -} - -/**************************************************************************** -REMARKS: -Function to set the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_setFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* TODO: Implement this ? */ - (void)filename; - (void)gmTime; - (void)time; - PM_fatalError("PM_setFileTime not implemented!"); - return false; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c deleted file mode 100644 index 2163928..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Dummy module; no virtual framebuffer for this OS -* -****************************************************************************/ - -#include "pmapi.h" - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -{ - return NULL; -} - -void PMAPI VF_exit(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c deleted file mode 100644 index 631f655..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit OS/2 VDD -* -* Description: OS specific implementation for the Zen Timer functions. -* -****************************************************************************/ - -/*---------------------------- Global variables ---------------------------*/ - -static ulong frequency = 1193180; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -#define __ZTimerInit() - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerOn(tm) VTD_Get_Real_Time(&tm->start.high,&tm->start.low) - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -static ulong __LZTimerLap( - LZTimerObject *tm) -{ - CPU_largeInteger lap,count; - VTD_Get_Real_Time(&lap.high,&lap.low); - _CPU_diffTime64(&tm->start,&lap,&count); - return _CPU_calcMicroSec(&count,frequency); -} - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerOff(tm) VTD_Get_Real_Time(&tm->end.high,&tm->end.low) - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -static ulong __LZTimerCount( - LZTimerObject *tm) -{ - CPU_largeInteger tmCount; - _CPU_diffTime64(&tm->start,&tm->end,&tmCount); - return _CPU_calcMicroSec(&tmCount,frequency); -} - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as microseconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION 1000 - -/**************************************************************************** -REMARKS: -Read the Long Period timer value from the BIOS timer tick. -****************************************************************************/ -static ulong __ULZReadTime(void) -{ - return VDHQuerySysValue(0, VDHGSV_MSECSBOOT); -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong __ULZElapsedTime(ulong start,ulong finish) -{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm deleted file mode 100644 index 64a7cec..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm +++ /dev/null @@ -1,299 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: 32-bit Windows VxD -;* -;* Description: Low level assembly support for the PM library specific to -;* Windows VxDs. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _pm ; Set up memory model - -begdataseg _pm - - cextern _PM_savedDS,USHORT - -enddataseg _pm - -P586 - -begcodeseg _pm ; Start of code segment - -;---------------------------------------------------------------------------- -; void PM_segread(PMSREGS *sregs) -;---------------------------------------------------------------------------- -; Read the current value of all segment registers -;---------------------------------------------------------------------------- -cprocstart PM_segread - - ARG sregs:DPTR - - enter_c - - mov ax,es - _les _si,[sregs] - mov [_ES _si],ax - mov [_ES _si+2],cs - mov [_ES _si+4],ss - mov [_ES _si+6],ds - mov [_ES _si+8],fs - mov [_ES _si+10],gs - - leave_c - ret - -cprocend - -;---------------------------------------------------------------------------- -; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) -;---------------------------------------------------------------------------- -; Issues a software interrupt in protected mode. This routine has been -; written to allow user programs to load CS and DS with different values -; other than the default. -;---------------------------------------------------------------------------- -cprocstart PM_int386x - -; Not used for VxDs - - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_saveDS(void) -;---------------------------------------------------------------------------- -; Save the value of DS into a section of the code segment, so that we can -; quickly load this value at a later date in the PM_loadDS() routine from -; inside interrupt handlers etc. The method to do this is different -; depending on the DOS extender being used. -;---------------------------------------------------------------------------- -cprocstart PM_saveDS - - mov [_PM_savedDS],ds ; Store away in data segment - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_loadDS(void) -;---------------------------------------------------------------------------- -; Routine to load the DS register with the default value for the current -; DOS extender. Only the DS register is loaded, not the ES register, so -; if you wish to call C code, you will need to also load the ES register -; in 32 bit protected mode. -;---------------------------------------------------------------------------- -cprocstart PM_loadDS - - mov ds,[cs:_PM_savedDS] ; We can access the proper DS through CS - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_setBankA(int bank) -;---------------------------------------------------------------------------- -cprocstart PM_setBankA - -; Not used for VxDs - - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_setBankAB(int bank) -;---------------------------------------------------------------------------- -cprocstart PM_setBankAB - -; Not used for VxDs - - ret - -cprocend - -;---------------------------------------------------------------------------- -; void PM_setCRTStart(int x,int y,int waitVRT) -;---------------------------------------------------------------------------- -cprocstart PM_setCRTStart - -; Not used for VxDs - - ret - -cprocend - -; Macro to delay briefly to ensure that enough time has elapsed between -; successive I/O accesses so that the device being accessed can respond -; to both accesses even on a very fast PC. - -ifdef USE_NASM -%macro DELAY 0 - jmp short $+2 - jmp short $+2 - jmp short $+2 -%endmacro -%macro IODELAYN 1 -%rep %1 - DELAY -%endrep -%endmacro -else -macro DELAY - jmp short $+2 - jmp short $+2 - jmp short $+2 -endm -macro IODELAYN N - rept N - DELAY - endm -endm -endif - -;---------------------------------------------------------------------------- -; uchar _PM_readCMOS(int index) -;---------------------------------------------------------------------------- -; Read the value of a specific CMOS register. We do this with both -; normal interrupts and NMI disabled. -;---------------------------------------------------------------------------- -cprocstart _PM_readCMOS - - ARG index:UINT - - push _bp - mov _bp,_sp - pushfd - mov al,[BYTE index] - or al,80h ; Add disable NMI flag - cli - out 70h,al - IODELAYN 5 - in al,71h - mov ah,al - xor al,al - IODELAYN 5 - out 70h,al ; Re-enable NMI - mov al,ah ; Return value in AL - popfd - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; void _PM_writeCMOS(int index,uchar value) -;---------------------------------------------------------------------------- -; Read the value of a specific CMOS register. We do this with both -; normal interrupts and NMI disabled. -;---------------------------------------------------------------------------- -cprocstart _PM_writeCMOS - - ARG index:UINT, value:UCHAR - - push _bp - mov _bp,_sp - pushfd - mov al,[BYTE index] - or al,80h ; Add disable NMI flag - cli - out 70h,al - IODELAYN 5 - mov al,[value] - out 71h,al - xor al,al - IODELAYN 5 - out 70h,al ; Re-enable NMI - popfd - pop _bp - ret - -cprocend - -;---------------------------------------------------------------------------- -; double _ftol(double f) -;---------------------------------------------------------------------------- -; Calls to __ftol are generated by the Borland C++ compiler for code -; that needs to convert a floating point type to an integral type. -; -; Input: floating point number on the top of the '87. -; -; Output: a (signed or unsigned) long in EAX -; All other registers preserved. -;----------------------------------------------------------------------- -cprocstart _ftol - - LOCAL temp1:WORD, temp2:QWORD = LocalSize - - push ebp - mov ebp,esp - sub esp,LocalSize - - fstcw [temp1] ; save the control word - fwait - mov al,[BYTE temp1+1] - or [BYTE temp1+1],0Ch ; set rounding control to chop - fldcw [temp1] - fistp [temp2] ; convert to 64-bit integer - mov [BYTE temp1+1],al - fldcw [temp1] ; restore the control word - mov eax,[DWORD temp2] ; return LS 32 bits - mov edx,[DWORD temp2+4] ; MS 32 bits - - mov esp,ebp - pop ebp - ret - -cprocend - -;---------------------------------------------------------------------------- -; _PM_getPDB - Return the Page Table Directory Base address -;---------------------------------------------------------------------------- -cprocstart _PM_getPDB - - mov eax,cr3 - and eax,0FFFFF000h - ret - -cprocend - -;---------------------------------------------------------------------------- -; Flush the Translation Lookaside buffer -;---------------------------------------------------------------------------- -cprocstart PM_flushTLB - - wbinvd ; Flush the CPU cache - mov eax,cr3 - mov cr3,eax ; Flush the TLB - ret - -cprocend - -endcodeseg _pm - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c deleted file mode 100644 index 3c7eaae..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows VxD -* -* Description: VxD specific code for the CPU detection module. -* -****************************************************************************/ - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Do nothing for VxD's -****************************************************************************/ -#define SetMaxThreadPriority() 0 - -/**************************************************************************** -REMARKS: -Do nothing for VxD's -****************************************************************************/ -#define RestoreThreadPriority(i) (void)(i) - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - freq->low = 1193180; - freq->high = 0; -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. -****************************************************************************/ -#define GetCounter(t) \ -{ \ - CPU_largeInteger count; \ - VTD_Get_Real_Time(&count.high,&count.low); \ - (t)->low = count.low; \ - (t)->high = count.high; \ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c deleted file mode 100644 index 3c6ce99..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c +++ /dev/null @@ -1,304 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows VxD -* -* Description: C library compatible I/O functions for use within a VxD. -* -****************************************************************************/ - -#include "pmapi.h" -#include "vxdfile.h" - -/*------------------------ Main Code Implementation -----------------------*/ - -#define EOF -1 - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C fopen function. -****************************************************************************/ -FILE * fopen( - const char *filename, - const char *mode) -{ - FILE *f = PM_malloc(sizeof(FILE)); - long oldpos; - - if (f) { - f->offset = 0; - f->text = (mode[1] == 't' || mode[2] == 't'); - f->writemode = (mode[0] == 'w') || (mode[0] == 'a'); - if (initComplete) { - WORD omode,error; - BYTE action; - - if (mode[0] == 'r') { - omode = OPEN_ACCESS_READONLY | OPEN_SHARE_COMPATIBLE; - action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_FAIL; - } - else if (mode[0] == 'w') { - omode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_COMPATIBLE; - action = ACTION_IFEXISTS_TRUNCATE | ACTION_IFNOTEXISTS_CREATE; - } - else { - omode = OPEN_ACCESS_READWRITE | OPEN_SHARE_COMPATIBLE; - action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_CREATE; - } - f->handle = (int)R0_OpenCreateFile(false,(char*)filename,omode,ATTR_NORMAL,action,0,&error,&action); - if (f->handle == 0) { - PM_free(f); - return NULL; - } - f->filesize = R0_GetFileSize((HANDLE)f->handle,&error); - if (mode[0] == 'a') - fseek(f,0,2); - } - else { - int oflag,pmode; - - if (mode[0] == 'r') { - pmode = _S_IREAD; - oflag = _O_RDONLY; - } - else if (mode[0] == 'w') { - pmode = _S_IWRITE; - oflag = _O_WRONLY | _O_CREAT | _O_TRUNC; - } - else { - pmode = _S_IWRITE; - oflag = _O_RDWR | _O_CREAT | _O_APPEND; - } - if (f->text) - oflag |= _O_TEXT; - else - oflag |= _O_BINARY; - if ((f->handle = i_open(filename,oflag,pmode)) == -1) { - PM_free(f); - return NULL; - } - oldpos = i_lseek(f->handle,0,1); - f->filesize = i_lseek(f->handle,0,2); - i_lseek(f->handle,oldpos,0); - } - } - return f; -} - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C fread function. Note that the VxD file I/O -functions are layered on DOS, so can only read up to 64K at a time. Since -we are expected to handle much larger chunks than this, we handle larger -blocks automatically in here. -****************************************************************************/ -size_t fread( - void *ptr, - size_t size, - size_t n, - FILE *f) -{ - char *buf = ptr; - WORD error; - int bytes = size * n; - int readbytes,totalbytes = 0; - - while (bytes > 0x10000) { - if (initComplete) { - readbytes = R0_ReadFile(false,(HANDLE)f->handle,buf,0x8000,f->offset,&error); - readbytes += R0_ReadFile(false,(HANDLE)f->handle,buf+0x8000,0x8000,f->offset+0x8000,&error); - } - else { - readbytes = i_read(f->handle,buf,0x8000); - readbytes += i_read(f->handle,buf+0x8000,0x8000); - } - totalbytes += readbytes; - f->offset += readbytes; - buf += 0x10000; - bytes -= 0x10000; - } - if (bytes) { - if (initComplete) - readbytes = R0_ReadFile(false,(HANDLE)f->handle,buf,bytes,f->offset,&error); - else - readbytes = i_read(f->handle,buf,bytes); - totalbytes += readbytes; - f->offset += readbytes; - } - return totalbytes / size; -} - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C fwrite function. Note that the VxD file I/O -functions are layered on DOS, so can only read up to 64K at a time. Since -we are expected to handle much larger chunks than this, we handle larger -blocks automatically in here. -****************************************************************************/ -size_t fwrite( - const void *ptr, - size_t size, - size_t n, - FILE *f) -{ - const char *buf = ptr; - WORD error; - int bytes = size * n; - int writtenbytes,totalbytes = 0; - - if (!f->writemode) - return 0; - while (bytes > 0x10000) { - if (initComplete) { - writtenbytes = R0_WriteFile(false,(HANDLE)f->handle,buf,0x8000,f->offset,&error); - writtenbytes += R0_WriteFile(false,(HANDLE)f->handle,buf+0x8000,0x8000,f->offset+0x8000,&error); - } - else { - writtenbytes = i_write(f->handle,buf,0x8000); - writtenbytes += i_write(f->handle,buf+0x8000,0x8000); - } - totalbytes += writtenbytes; - f->offset += writtenbytes; - buf += 0x10000; - bytes -= 0x10000; - } - if (initComplete) - writtenbytes = R0_WriteFile(false,(HANDLE)f->handle,buf,bytes,f->offset,&error); - else - writtenbytes = i_write(f->handle,buf,bytes); - totalbytes += writtenbytes; - f->offset += writtenbytes; - if (f->offset > f->filesize) - f->filesize = f->offset; - return totalbytes / size; -} - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C fflush function. -****************************************************************************/ -int fflush( - FILE *f) -{ - /* Nothing to do since we are not doing buffered file I/O */ - (void)f; - return 0; -} - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C fseek function. -****************************************************************************/ -int fseek( - FILE *f, - long int offset, - int whence) -{ - if (whence == 0) - f->offset = offset; - else if (whence == 1) - f->offset += offset; - else if (whence == 2) - f->offset = f->filesize + offset; - if (!initComplete) - i_lseek(f->handle,f->offset,0); - return 0; -} - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C ftell function. -****************************************************************************/ -long ftell( - FILE *f) -{ - return f->offset; -} - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C feof function. -****************************************************************************/ -int feof( - FILE *f) -{ - return (f->offset == f->filesize); -} - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C fgets function. -****************************************************************************/ -char *fgets( - char *s, - int n, - FILE *f) -{ - int len; - char *cs; - - /* Read the entire buffer into memory (our functions are unbuffered!) */ - if ((len = fread(s,1,n,f)) == 0) - return NULL; - - /* Search for '\n' or end of string */ - if (n > len) - n = len; - cs = s; - while (--n > 0) { - if (*cs == '\n') - break; - cs++; - } - *cs = '\0'; - return s; -} - -/**************************************************************************** -REMARKS: -NT driver implementation of the ANSI C fputs function. -****************************************************************************/ -int fputs( - const char *s, - FILE *f) -{ - return fwrite(s,1,strlen(s),f); -} - -/**************************************************************************** -REMARKS: -VxD implementation of the ANSI C fclose function. -****************************************************************************/ -int fclose( - FILE *f) -{ - WORD error; - - if (initComplete) - R0_CloseFile((HANDLE)f->handle,&error); - else - i_close(f->handle); - PM_free(f); - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h deleted file mode 100644 index 7efc0f9..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h +++ /dev/null @@ -1,29 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows VxD -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c deleted file mode 100644 index 4cb7f19..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c +++ /dev/null @@ -1,1359 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows VxD -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#include "pmapi.h" -#include "drvlib/os/os.h" -#include "sdd/sddhelp.h" -#include "mtrr.h" - -/*--------------------------- Global variables ----------------------------*/ - -#define MAX_MEMORY_SHARED 100 -#define MAX_MEMORY_MAPPINGS 100 - -typedef struct { - void *linear; - ulong global; - ulong length; - int npages; - } memshared; - -typedef struct { - ulong physical; - ulong linear; - ulong length; - int npages; - ibool isCached; - } mmapping; - -static int numMappings = 0; -static memshared shared[MAX_MEMORY_MAPPINGS] = {0}; -static mmapping maps[MAX_MEMORY_MAPPINGS]; -extern ibool _PM_haveBIOS; -char _PM_cntPath[PM_MAX_PATH] = ""; -char _PM_nucleusPath[PM_MAX_PATH] = ""; -uchar *_PM_rmBufAddr = NULL; -ushort _VARAPI _PM_savedDS = 0; -static uchar _PM_oldCMOSRegA; -static uchar _PM_oldCMOSRegB; -PM_intHandler _PM_rtcHandler = NULL; -IRQHANDLE RTCIRQHandle = 0; -VPICD_HWInt_THUNK RTCInt_Thunk; - -static char *szWindowsKey = "Software\\Microsoft\\Windows\\CurrentVersion"; -static char *szSystemRoot = "SystemRoot"; -static char *szMachineNameKey = "System\\CurrentControlSet\\control\\ComputerName\\ComputerName"; -static char *szMachineName = "ComputerName"; -static void (PMAPIP fatalErrorCleanup)(void) = NULL; - -/*----------------------------- Implementation ----------------------------*/ - -/* Functions to read and write CMOS registers */ - -ulong PMAPI _PM_getPDB(void); -uchar PMAPI _PM_readCMOS(int index); -void PMAPI _PM_writeCMOS(int index,uchar value); - -/**************************************************************************** -REMARKS: -PM_malloc override function for Nucleus drivers loaded in VxD's. -****************************************************************************/ -void * VXD_malloc( - size_t size) -{ - return PM_mallocShared(size); -} - -/**************************************************************************** -REMARKS: -PM_calloc override function for Nucleus drivers loaded in VxD's. -****************************************************************************/ -void * VXD_calloc( - size_t nelem, - size_t size) -{ - void *p = PM_mallocShared(nelem * size); - if (p) - memset(p,0,nelem * size); - return p; -} - -/**************************************************************************** -REMARKS: -PM_realloc override function for Nucleus drivers loaded in VxD's. -****************************************************************************/ -void * VXD_realloc( - void *ptr, - size_t size) -{ - void *p = PM_mallocShared(size); - if (p) { - memcpy(p,ptr,size); - PM_freeShared(ptr); - } - return p; -} - -/**************************************************************************** -REMARKS: -PM_free override function for Nucleus drivers loaded in VxD's. -****************************************************************************/ -void VXD_free( - void *p) -{ - PM_freeShared(p); -} - -/**************************************************************************** -REMARKS: -Initialise the PM library. -****************************************************************************/ -void PMAPI PM_init(void) -{ - /* Override the default memory allocators for all Nucleus drivers - * loaded in SDDHELP/PMHELP. We do this so that we can ensure all memory - * dynamically allocated by Nucleus drivers and internal C runtime - * library functions are shared memory blocks that all processes - * connecting to SDDHELP can see. - */ - PM_useLocalMalloc(VXD_malloc,VXD_calloc,VXD_realloc,VXD_free); - - /* Initialiase the MTRR module */ - MTRR_init(); -} - -ibool PMAPI PM_haveBIOSAccess(void) -{ return _PM_haveBIOS; } - -long PMAPI PM_getOSType(void) -{ return _OS_WIN32VXD; } - -int PMAPI PM_getModeType(void) -{ return PM_386; } - -void PMAPI PM_backslash(char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '\\') { - s[pos] = '\\'; - s[pos+1] = '\0'; - } -} - -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -void PMAPI PM_fatalError(const char *msg) -{ - if (fatalErrorCleanup) - fatalErrorCleanup(); - Fatal_Error_Handler(msg,0); -} - -/**************************************************************************** -PARAMETERS: -len - Place to store the length of the buffer -rseg - Place to store the real mode segment of the buffer -roff - Place to store the real mode offset of the buffer - -REMARKS: -This function returns the address and length of the global VESA transfer -buffer that is used for communicating with the VESA BIOS functions from -Win16 and Win32 programs under Windows. -****************************************************************************/ -void * PMAPI PM_getVESABuf( - uint *len, - uint *rseg, - uint *roff) -{ - /* If the VxD is dynamically loaded we will not have a real mode - * transfer buffer to return, so we fail the call. - */ - if (_PM_rmBufAddr) { - *len = VESA_BUF_SIZE; - *rseg = (ulong)(_PM_rmBufAddr) >> 4; - *roff = (ulong)(_PM_rmBufAddr) & 0xF; - return _PM_rmBufAddr; - } - return NULL; -} - -int PMAPI PM_int386( - int intno, - PMREGS *in, - PMREGS *out) -{ - /* Unused in VxDs */ - return 0; -} - -void PMAPI _PM_getRMvect( - int intno, - long *realisr) -{ - WORD seg; - DWORD off; - - Get_V86_Int_Vector(intno,&seg,&off); - *realisr = ((long)seg << 16) | (off & 0xFFFF); -} - -void PMAPI _PM_setRMvect( - int intno, - long realisr) -{ - Set_V86_Int_Vector(intno,realisr >> 16,realisr & 0xFFFF); -} - -char * PMAPI PM_getCurrentPath( - char *path, - int maxLen) -{ - strncpy(path,_PM_cntPath,maxLen); - path[maxLen-1] = 0; - return path; -} - -char PMAPI PM_getBootDrive(void) -{ return 'c'; } - -const char * PMAPI PM_getVBEAFPath(void) -{ return "c:\\"; } - -/**************************************************************************** -PARAMETERS: -szKey - Key to query (can contain version number formatting) -szValue - Value to get information for -value - Place to store the registry key data read -size - Size of the string buffer to read into - -RETURNS: -true if the key was found, false if not. -****************************************************************************/ -static ibool REG_queryString( - char *szKey, - char *szValue, - char *value, - ulong size) -{ - HKEY hKey; - ulong type; - ibool status = false; - - memset(value,0,sizeof(value)); - if (RegOpenKey(HKEY_LOCAL_MACHINE,szKey,&hKey) == ERROR_SUCCESS) { - if (RegQueryValueEx(hKey,(PCHAR)szValue,(ulong*)NULL,(ulong*)&type,value,(ulong*)&size) == ERROR_SUCCESS) - status = true; - RegCloseKey(hKey); - } - return status; -} - -const char * PMAPI PM_getNucleusPath(void) -{ - static char path[256]; - - if (strlen(_PM_nucleusPath) > 0) { - strcpy(path,_PM_nucleusPath); - PM_backslash(path); - return path; - } - if (!REG_queryString(szWindowsKey,szSystemRoot,path,sizeof(path))) - strcpy(path,"c:\\windows"); - PM_backslash(path); - strcat(path,"system\\nucleus"); - return path; -} - -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[256]; - strcpy(path,PM_getNucleusPath()); - PM_backslash(path); - strcat(path,"config"); - return path; -} - -const char * PMAPI PM_getUniqueID(void) -{ return PM_getMachineName(); } - -const char * PMAPI PM_getMachineName(void) -{ - static char name[256]; - if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name))) - return name; - return "Unknown"; -} - -int PMAPI PM_kbhit(void) -{ return 1; } - -int PMAPI PM_getch(void) -{ return 0; } - -PM_HWND PMAPI PM_openConsole( - PM_HWND hwndUser, - int device, - int xRes, - int yRes, - int bpp, - ibool fullScreen) -{ - /* Unused in VxDs */ - return NULL; -} - -int PMAPI PM_getConsoleStateSize(void) -{ - /* Unused in VxDs */ - return 1; -} - -void PMAPI PM_saveConsoleState( - void *stateBuf, - PM_HWND hwndConsole) -{ - /* Unused in VxDs */ -} - -void PMAPI PM_setSuspendAppCallback( - int (_ASMAPIP saveState)( - int flags)) -{ - /* Unused in VxDs */ -} - -void PMAPI PM_restoreConsoleState( - const void *stateBuf, - PM_HWND hwndConsole) -{ - /* Unused in VxDs */ -} - -void PMAPI PM_closeConsole( - PM_HWND hwndConsole) -{ - /* Unused in VxDs */ -} - -void PM_setOSCursorLocation( - int x, - int y) -{ - uchar *_biosPtr = PM_getBIOSPointer(); - PM_setByte(_biosPtr+0x50,x); - PM_setByte(_biosPtr+0x51,y); -} - -void PM_setOSScreenWidth( - int width, - int height) -{ - uchar *_biosPtr = PM_getBIOSPointer(); - PM_setByte(_biosPtr+0x4A,width); - PM_setByte(_biosPtr+0x84,height-1); -} - -/**************************************************************************** -REMARKS: -Allocate a block of shared memory. For Win9x we allocate shared memory -as locked, global memory that is accessible from any memory context -(including interrupt time context), which allows us to load our important -data structure and code such that we can access it directly from a ring -0 interrupt context. -****************************************************************************/ -void * PMAPI PM_mallocShared( - long size) -{ - MEMHANDLE hMem; - DWORD pgNum,nPages = (size + 0xFFF) >> 12; - int i; - - /* First find a free slot in our shared memory table */ - for (i = 0; i < MAX_MEMORY_SHARED; i++) { - if (shared[i].linear == 0) - break; - } - if (i < MAX_MEMORY_SHARED) { - PageAllocate(nPages,PG_SYS,0,0,0,0,NULL,0,&hMem,&shared[i].linear); - shared[i].npages = nPages; - pgNum = (ulong)shared[i].linear >> 12; - shared[i].global = LinPageLock(pgNum,nPages,PAGEMAPGLOBAL); - return (void*)shared[i].global; - } - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a block of shared memory -****************************************************************************/ -void PMAPI PM_freeShared(void *p) -{ - int i; - - /* Find a shared memory block in our table and free it */ - for (i = 0; i < MAX_MEMORY_SHARED; i++) { - if (shared[i].global == (ulong)p) { - LinPageUnLock(shared[i].global >> 12,shared[i].npages,PAGEMAPGLOBAL); - PageFree((ulong)shared[i].linear,0); - shared[i].linear = 0; - break; - } - } -} - -/**************************************************************************** -REMARKS: -Maps a shared memory block into process address space. Does nothing since -the memory blocks are already globally7 mapped into all processes. -****************************************************************************/ -void * PMAPI PM_mapToProcess( - void *base, - ulong limit) -{ - return (void*)base; -} - -ibool PMAPI PM_doBIOSPOST( - ushort axVal, - ulong BIOSPhysAddr, - void *mappedBIOS, - ulong BIOSLen) -{ - /* TODO: Figure out how to do this */ - return false; -} - -void * PMAPI PM_getBIOSPointer(void) -{ return (void*)0x400; } - -void * PMAPI PM_getA0000Pointer(void) -{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); } - -/**************************************************************************** -PARAMETERS: -base - Physical base address of the memory to maps in -limit - Limit of physical memory to region to maps in - -RETURNS: -Linear address of the newly mapped memory. - -REMARKS: -Maps a physical memory range to a linear memory range. -****************************************************************************/ -ulong _PM_mapPhysicalToLinear( - ulong base, - ulong limit, - int *npages) -{ - ulong linear,length = limit+1; - int i,ppage,flags; - - if (base < 0x100000) { - /* Windows 9x is zero based for the first meg of memory */ - return base; - } - ppage = base >> 12; - *npages = (length + (base & 0xFFF) + 4095) >> 12; - flags = PR_FIXED | PR_STATIC; - if (base == 0xA0000) { - /* We require the linear address to be aligned to a 64Kb boundary - * for mapping the banked framebuffer (so we can do efficient - * carry checking for bank changes in the assembler code). The only - * way to ensure this is to force the linear address to be aligned - * to a 4Mb boundary. - */ - flags |= PR_4MEG; - } - if ((linear = (ulong)PageReserve(PR_SYSTEM,*npages,flags)) == (ulong)-1) - return 0xFFFFFFFF; - if (!PageCommitPhys(linear >> 12,*npages,ppage,PC_INCR | PC_USER | PC_WRITEABLE)) - return 0xFFFFFFFF; - return linear + (base & 0xFFF); -} - -/* Page table flags */ - -#define PAGE_FLAGS_PRESENT 0x00000001 -#define PAGE_FLAGS_WRITEABLE 0x00000002 -#define PAGE_FLAGS_USER 0x00000004 -#define PAGE_FLAGS_WRITE_THROUGH 0x00000008 -#define PAGE_FLAGS_CACHE_DISABLE 0x00000010 -#define PAGE_FLAGS_ACCESSED 0x00000020 -#define PAGE_FLAGS_DIRTY 0x00000040 -#define PAGE_FLAGS_4MB 0x00000080 - -/**************************************************************************** -PARAMETERS: -base - Physical base address of the memory to maps in -limit - Limit of physical memory to region to maps in -isCached - True if the memory should be cached, false if not - -RETURNS: -Linear address of the newly mapped memory. - -REMARKS: -This function maps physical memory to linear memory, which can then be used -to create a selector or used directly from 32-bit protected mode programs. -This is better than DPMI 0x800, since it allows you to maps physical -memory below 1Mb, which gets this memory out of the way of the Windows VDD's -sticky paws. - -NOTE: If the memory is not expected to be cached, this function will - directly re-program the PCD (Page Cache Disable) bit in the - page tables. There does not appear to be a mechanism in the VMM - to control this bit via the regular interface. -****************************************************************************/ -void * PMAPI PM_mapPhysicalAddr( - ulong base, - ulong limit, - ibool isCached) -{ - ulong linear,length = limit+1; - int i,npages; - ulong PDB,*pPDB; - - /* Search table of existing mappings to see if we have already mapped - * a region of memory that will serve this purpose. - */ - for (i = 0; i < numMappings; i++) { - if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached) - return (void*)maps[i].linear; - } - if (numMappings == MAX_MEMORY_MAPPINGS) - return NULL; - - /* We did not find any previously mapped memory region, so maps it in. - * Note that we do not use MapPhysToLinear, since this function appears - * to have problems mapping memory in the 1Mb physical address space. - * Hence we use PageReserve and PageCommitPhys. - */ - if ((linear = _PM_mapPhysicalToLinear(base,limit,&npages)) == 0xFFFFFFFF) - return NULL; - maps[numMappings].physical = base; - maps[numMappings].length = length; - maps[numMappings].linear = linear; - maps[numMappings].npages = npages; - maps[numMappings].isCached = isCached; - numMappings++; - - /* Finally disable caching where necessary */ - if (!isCached && (PDB = _PM_getPDB()) != 0) { - int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; - ulong pageTable,*pPageTable; - pPDB = (ulong*)_PM_mapPhysicalToLinear(PDB,0xFFF,&npages); - if (pPDB) { - startPDB = (linear >> 22) & 0x3FF; - startPage = (linear >> 12) & 0x3FF; - endPDB = ((linear+limit) >> 22) & 0x3FF; - endPage = ((linear+limit) >> 12) & 0x3FF; - for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { - /* Set the bits in the page directory entry - required as per */ - /* Pentium 4 manual. This also takes care of the 4MB page entries */ - pPDB[iPDB] = pPDB[iPDB] |= (PAGE_FLAGS_WRITE_THROUGH | PAGE_FLAGS_CACHE_DISABLE); - if (!(pPDB[iPDB] & PAGE_FLAGS_4MB)) { - /* If we are dealing with 4KB pages then we need to iterate */ - /* through each of the page table entries */ - pageTable = pPDB[iPDB] & ~0xFFF; - pPageTable = (ulong*)_PM_mapPhysicalToLinear(pageTable,0xFFF,&npages); - start = (iPDB == startPDB) ? startPage : 0; - end = (iPDB == endPDB) ? endPage : 0x3FF; - for (iPage = start; iPage <= end; iPage++) - pPageTable[iPage] |= (PAGE_FLAGS_WRITE_THROUGH | PAGE_FLAGS_CACHE_DISABLE); - PageFree((ulong)pPageTable,PR_STATIC); - } - } - PageFree((ulong)pPDB,PR_STATIC); - PM_flushTLB(); - } - } - return (void*)linear; -} - -void PMAPI PM_freePhysicalAddr( - void *ptr, - ulong limit) -{ - /* We never free the mappings */ -} - -void PMAPI PM_sleep(ulong milliseconds) -{ - /* We never sleep in a VxD */ -} - -int PMAPI PM_getCOMPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - case 2: return 0x3E8; - case 3: return 0x2E8; - } - return 0; -} - -int PMAPI PM_getLPTPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -ulong PMAPI PM_getPhysicalAddr( - void *p) -{ - DWORD pte; - - /* Touch the memory before calling CopyPageTable. For some reason */ - /* we need to do this on Windows 9x, otherwise the memory may not */ - /* be paged in correctly. Of course if the passed in pointer is */ - /* invalid, this function will fault, but we shouldn't be passed bogus */ - /* pointers anyway ;-) */ - pte = *((ulong*)p); - - /* Return assembled address value only if VMM service succeeds */ - if (CopyPageTable(((DWORD)p) >> 12, 1, (PVOID*)&pte, 0)) - return (pte & ~0xFFF) | (((DWORD)p) & 0xFFF); - - /* Return failure to the caller! */ - return 0xFFFFFFFFUL; -} - -ibool PMAPI PM_getPhysicalAddrRange( - void *p, - ulong length, - ulong *physAddress) -{ - int i; - ulong linear = (ulong)p & ~0xFFF; - - for (i = (length + 0xFFF) >> 12; i > 0; i--) { - if ((*physAddress++ = PM_getPhysicalAddr((void*)linear)) == 0xFFFFFFFF) - return false; - linear += 4096; - } - return true; -} - -void PMAPI _PM_freeMemoryMappings(void) -{ - int i; - for (i = 0; i < numMappings; i++) - PageFree(maps[i].linear,PR_STATIC); -} - -void * PMAPI PM_mapRealPointer( - uint r_seg, - uint r_off) -{ - return (void*)MK_PHYS(r_seg,r_off); -} - -void * PMAPI PM_allocRealSeg( - uint size, - uint *r_seg, - uint *r_off) -{ - return NULL; -} - -void PMAPI PM_freeRealSeg( - void *mem) -{ -} - -void PMAPI DPMI_int86( - int intno, - DPMI_regs *regs) -{ - /* Unsed in VxD's */ -} - -/**************************************************************************** -REMARKS: -Load the V86 registers in the client state, and save the original state -before loading the registers. -****************************************************************************/ -static void LoadV86Registers( - CLIENT_STRUCT *saveRegs, - RMREGS *in, - RMSREGS *sregs) -{ - CLIENT_STRUCT newRegs; - - Save_Client_State(saveRegs); - newRegs = *saveRegs; - newRegs.CRS.Client_EAX = in->e.eax; - newRegs.CRS.Client_EBX = in->e.ebx; - newRegs.CRS.Client_ECX = in->e.ecx; - newRegs.CRS.Client_EDX = in->e.edx; - newRegs.CRS.Client_ESI = in->e.esi; - newRegs.CRS.Client_EDI = in->e.edi; - newRegs.CRS.Client_ES = sregs->es; - newRegs.CRS.Client_DS = sregs->ds; - Restore_Client_State(&newRegs); -} - -/**************************************************************************** -REMARKS: -Read the V86 registers from the client state and restore the original state. -****************************************************************************/ -static void ReadV86Registers( - CLIENT_STRUCT *saveRegs, - RMREGS *out, - RMSREGS *sregs) -{ - CLIENT_STRUCT newRegs; - - Save_Client_State(&newRegs); - out->e.eax = newRegs.CRS.Client_EAX; - out->e.ebx = newRegs.CRS.Client_EBX; - out->e.ecx = newRegs.CRS.Client_ECX; - out->e.edx = newRegs.CRS.Client_EDX; - out->e.esi = newRegs.CRS.Client_ESI; - out->e.edi = newRegs.CRS.Client_EDI; - sregs->es = newRegs.CRS.Client_ES; - sregs->ds = newRegs.CRS.Client_DS; - Restore_Client_State(saveRegs); -} - -/**************************************************************************** -REMARKS: -Call a V86 real mode function with the specified register values -loaded before the call. The call returns with a far ret. -****************************************************************************/ -void PMAPI PM_callRealMode( - uint seg, - uint off, - RMREGS *regs, - RMSREGS *sregs) -{ - CLIENT_STRUCT saveRegs; - - /* Bail if we do not have BIOS access (ie: the VxD was dynamically - * loaded, and not statically loaded. - */ - if (!_PM_haveBIOS) - return; - - _TRACE("SDDHELP: Entering PM_callRealMode()\n"); - Begin_Nest_V86_Exec(); - LoadV86Registers(&saveRegs,regs,sregs); - Simulate_Far_Call(seg, off); - Resume_Exec(); - ReadV86Registers(&saveRegs,regs,sregs); - End_Nest_Exec(); - _TRACE("SDDHELP: Exiting PM_callRealMode()\n"); -} - -/**************************************************************************** -REMARKS: -Issue a V86 real mode interrupt with the specified register values -loaded before the interrupt. -****************************************************************************/ -int PMAPI PM_int86( - int intno, - RMREGS *in, - RMREGS *out) -{ - RMSREGS sregs = {0}; - CLIENT_STRUCT saveRegs; - ushort oldDisable; - - /* Bail if we do not have BIOS access (ie: the VxD was dynamically - * loaded, and not statically loaded. - */ - if (!_PM_haveBIOS) { - *out = *in; - return out->x.ax; - } - - /* Disable pass-up to our VxD handler so we directly call BIOS */ - _TRACE("SDDHELP: Entering PM_int86()\n"); - if (disableTSRFlag) { - oldDisable = *disableTSRFlag; - *disableTSRFlag = 0; - } - Begin_Nest_V86_Exec(); - LoadV86Registers(&saveRegs,in,&sregs); - Exec_Int(intno); - ReadV86Registers(&saveRegs,out,&sregs); - End_Nest_Exec(); - - /* Re-enable pass-up to our VxD handler if previously enabled */ - if (disableTSRFlag) - *disableTSRFlag = oldDisable; - - _TRACE("SDDHELP: Exiting PM_int86()\n"); - return out->x.ax; -} - -/**************************************************************************** -REMARKS: -Issue a V86 real mode interrupt with the specified register values -loaded before the interrupt. -****************************************************************************/ -int PMAPI PM_int86x( - int intno, - RMREGS *in, - RMREGS *out, - RMSREGS *sregs) -{ - CLIENT_STRUCT saveRegs; - ushort oldDisable; - - /* Bail if we do not have BIOS access (ie: the VxD was dynamically - * loaded, and not statically loaded. - */ - if (!_PM_haveBIOS) { - *out = *in; - return out->x.ax; - } - - /* Disable pass-up to our VxD handler so we directly call BIOS */ - _TRACE("SDDHELP: Entering PM_int86x()\n"); - if (disableTSRFlag) { - oldDisable = *disableTSRFlag; - *disableTSRFlag = 0; - } - Begin_Nest_V86_Exec(); - LoadV86Registers(&saveRegs,in,sregs); - Exec_Int(intno); - ReadV86Registers(&saveRegs,out,sregs); - End_Nest_Exec(); - - /* Re-enable pass-up to our VxD handler if previously enabled */ - if (disableTSRFlag) - *disableTSRFlag = oldDisable; - - _TRACE("SDDHELP: Exiting PM_int86x()\n"); - return out->x.ax; -} - -/**************************************************************************** -REMARKS: -Returns available memory. Not possible under Windows. -****************************************************************************/ -void PMAPI PM_availableMemory( - ulong *physical, - ulong *total) -{ - *physical = *total = 0; -} - -/**************************************************************************** -REMARKS: -Allocates a block of locked physical memory. -****************************************************************************/ -void * PMAPI PM_allocLockedMem( - uint size, - ulong *physAddr, - ibool contiguous, - ibool below16M) -{ - MEMHANDLE hMem; - DWORD nPages = (size + 0xFFF) >> 12; - DWORD flags = PAGEFIXED | PAGEUSEALIGN | (contiguous ? PAGECONTIG : 0); - DWORD maxPhys = below16M ? 0x00FFFFFF : 0xFFFFFFFF; - void *p; - - /* TODO: This may need to be modified if the memory needs to be globally */ - /* accessible. Check how we implemented PM_mallocShared() as we */ - /* may need to do something similar in here. */ - PageAllocate(nPages,PG_SYS,0,0,0,maxPhys,physAddr,flags,&hMem,&p); - - /* TODO: We may need to modify the memory blocks to disable caching via */ - /* the page tables (PCD|PWT) since DMA memory blocks *cannot* be */ - /* cached! */ - return p; -} - -/**************************************************************************** -REMARKS: -Frees a block of locked physical memory. -****************************************************************************/ -void PMAPI PM_freeLockedMem( - void *p, - uint size, - ibool contiguous) -{ - if (p) - PageFree((ulong)p,0); -} - -/**************************************************************************** -REMARKS: -Allocates a page aligned and page sized block of memory -****************************************************************************/ -void * PMAPI PM_allocPage( - ibool locked) -{ - MEMHANDLE hMem; - void *p; - - /* TODO: This will need to be modified if the memory needs to be globally */ - /* accessible. Check how we implemented PM_mallocShared() as we */ - /* may need to do something similar in here. */ - PageAllocate(1,PG_SYS,0,0,0,0,0,PAGEFIXED,&hMem,&p); - return p; -} - -/**************************************************************************** -REMARKS: -Free a page aligned and page sized block of memory -****************************************************************************/ -void PMAPI PM_freePage( - void *p) -{ - if (p) - PageFree((ulong)p,0); -} - -/**************************************************************************** -REMARKS: -Lock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_lockDataPages( - void *p, - uint len, - PM_lockHandle *lh) -{ - DWORD pgNum = (ulong)p >> 12; - DWORD nPages = (len + (ulong)p - (pgNum << 12) + 0xFFF) >> 12; - return LinPageLock(pgNum,nPages,0); -} - -/**************************************************************************** -REMARKS: -Unlock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_unlockDataPages( - void *p, - uint len, - PM_lockHandle *lh) -{ - DWORD pgNum = (ulong)p >> 12; - DWORD nPages = (len + (ulong)p - (pgNum << 12) + 0xFFF) >> 12; - return LinPageUnLock(pgNum,nPages,0); -} - -/**************************************************************************** -REMARKS: -Lock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_lockCodePages( - void (*p)(), - uint len, - PM_lockHandle *lh) -{ - return PM_lockDataPages((void*)p,len,lh); -} - -/**************************************************************************** -REMARKS: -Unlock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_unlockCodePages( - void (*p)(), - uint len, - PM_lockHandle *lh) -{ - return PM_unlockDataPages((void*)p,len,lh); -} - -/**************************************************************************** -REMARKS: -Set the real time clock frequency (for stereo modes). -****************************************************************************/ -void PMAPI PM_setRealTimeClockFrequency( - int frequency) -{ - static short convert[] = { - 8192, - 4096, - 2048, - 1024, - 512, - 256, - 128, - 64, - 32, - 16, - 8, - 4, - 2, - -1, - }; - int i; - - /* First clear any pending RTC timeout if not cleared */ - _PM_readCMOS(0x0C); - if (frequency == 0) { - /* Disable RTC timout */ - _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); - _PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F); - } - else { - /* Convert frequency value to RTC clock indexes */ - for (i = 0; convert[i] != -1; i++) { - if (convert[i] == frequency) - break; - } - - /* Set RTC timout value and enable timeout */ - _PM_writeCMOS(0x0A,0x20 | (i+3)); - _PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40); - } -} - -/**************************************************************************** -REMARKS: -Real time clock interrupt handler, which calls the user registered C code. -****************************************************************************/ -static BOOL __stdcall RTCInt_Handler( - VMHANDLE hVM, - IRQHANDLE hIRQ) -{ - static char inside = 0; - - /* Clear priority interrupt controller and re-enable interrupts so we - * dont lock things up for long. - */ - VPICD_Phys_EOI(hIRQ); - - /* Clear real-time clock timeout */ - _PM_readCMOS(0x0C); - - /* Now call the C based interrupt handler (but check for mutual - * exclusion since we may still be servicing an old interrupt when a - * new one comes along; if that happens we ignore the old one). - */ - if (!inside) { - inside = 1; - enable(); - _PM_rtcHandler(); - inside = 0; - } - return TRUE; -} - -/**************************************************************************** -REMARKS: -Set the real time clock handler (used for software stereo modes). -****************************************************************************/ -ibool PMAPI PM_setRealTimeClockHandler( - PM_intHandler ih, - int frequency) -{ - struct VPICD_IRQ_Descriptor IRQdesc; - - /* Save the old CMOS real time clock values */ - _PM_oldCMOSRegA = _PM_readCMOS(0x0A); - _PM_oldCMOSRegB = _PM_readCMOS(0x0B); - - /* Set the real time clock interrupt handler */ - CHECK(ih != NULL); - _PM_rtcHandler = ih; - IRQdesc.VID_IRQ_Number = 0x8; - IRQdesc.VID_Options = 0; - IRQdesc.VID_Hw_Int_Proc = (DWORD)VPICD_Thunk_HWInt(RTCInt_Handler, &RTCInt_Thunk); - IRQdesc.VID_EOI_Proc = 0; - IRQdesc.VID_Virt_Int_Proc = 0; - IRQdesc.VID_Mask_Change_Proc= 0; - IRQdesc.VID_IRET_Proc = 0; - IRQdesc.VID_IRET_Time_Out = 500; - if ((RTCIRQHandle = VPICD_Virtualize_IRQ(&IRQdesc)) == 0) - return false; - - /* Program the real time clock default frequency */ - PM_setRealTimeClockFrequency(frequency); - - /* Unmask IRQ8 in the PIC */ - VPICD_Physically_Unmask(RTCIRQHandle); - return true; -} - -/**************************************************************************** -REMARKS: -Restore the original real time clock handler. -****************************************************************************/ -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - if (RTCIRQHandle) { - /* Restore CMOS registers and mask RTC clock */ - _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); - _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); - - /* Restore the interrupt vector */ - VPICD_Set_Auto_Masking(RTCIRQHandle); - VPICD_Force_Default_Behavior(RTCIRQHandle); - RTCIRQHandle = 0; - } -} - -/**************************************************************************** -REMARKS: -OS specific shared libraries not supported inside a VxD -****************************************************************************/ -PM_MODULE PMAPI PM_loadLibrary( - const char *szDLLName) -{ - (void)szDLLName; - return NULL; -} - -/**************************************************************************** -REMARKS: -OS specific shared libraries not supported inside a VxD -****************************************************************************/ -void * PMAPI PM_getProcAddress( - PM_MODULE hModule, - const char *szProcName) -{ - (void)hModule; - (void)szProcName; - return NULL; -} - -/**************************************************************************** -REMARKS: -OS specific shared libraries not supported inside a VxD -****************************************************************************/ -void PMAPI PM_freeLibrary( - PM_MODULE hModule) -{ - (void)hModule; -} - -/**************************************************************************** -REMARKS: -Function to find the first file matching a search criteria in a directory. -****************************************************************************/ -void *PMAPI PM_findFirstFile( - const char *filename, - PM_findData *findData) -{ - /* TODO: This function should start a directory enumeration search */ - /* given the filename (with wildcards). The data should be */ - /* converted and returned in the findData standard form. */ - (void)filename; - (void)findData; - return PM_FILE_INVALID; -} - -/**************************************************************************** -REMARKS: -Function to find the next file matching a search criteria in a directory. -****************************************************************************/ -ibool PMAPI PM_findNextFile( - void *handle, - PM_findData *findData) -{ - /* TODO: This function should find the next file in directory enumeration */ - /* search given the search criteria defined in the call to */ - /* PM_findFirstFile. The data should be converted and returned */ - /* in the findData standard form. */ - (void)handle; - (void)findData; - return false; -} - -/**************************************************************************** -REMARKS: -Function to close the find process -****************************************************************************/ -void PMAPI PM_findClose( - void *handle) -{ - /* TODO: This function should close the find process. This may do */ - /* nothing for some OS'es. */ - (void)handle; -} - -/**************************************************************************** -REMARKS: -Function to determine if a drive is a valid drive or not. Under Unix this -function will return false for anything except a value of 3 (considered -the root drive, and equivalent to C: for non-Unix systems). The drive -numbering is: - - 1 - Drive A: - 2 - Drive B: - 3 - Drive C: - etc - -****************************************************************************/ -ibool PMAPI PM_driveValid( - char drive) -{ - /* Not supported in a VxD */ - (void)drive; - return false; -} - -/**************************************************************************** -REMARKS: -Function to get the current working directory for the specififed drive. -Under Unix this will always return the current working directory regardless -of what the value of 'drive' is. -****************************************************************************/ -void PMAPI PM_getdcwd( - int drive, - char *dir, - int len) -{ - /* Not supported in a VxD */ - (void)drive; - (void)dir; - (void)len; -} - -/**************************************************************************** -PARAMETERS: -base - The starting physical base address of the region -size - The size in bytes of the region -type - Type to place into the MTRR register - -RETURNS: -Error code describing the result. - -REMARKS: -Function to enable write combining for the specified region of memory. -****************************************************************************/ -int PMAPI PM_enableWriteCombine( - ulong base, - ulong size, - uint type) -{ - return MTRR_enableWriteCombine(base,size,type); -} - -/**************************************************************************** -REMARKS: -Function to change the file attributes for a specific file. -****************************************************************************/ -void PMAPI PM_setFileAttr( - const char *filename, - uint attrib) -{ - /* TODO: Implement this */ - (void)filename; - (void)attrib; - PM_fatalError("PM_setFileAttr not implemented yet!"); -} - -/**************************************************************************** -REMARKS: -Function to get the file attributes for a specific file. -****************************************************************************/ -uint PMAPI PM_getFileAttr( - const char *filename) -{ - /* TODO: Implement this */ - (void)filename; - PM_fatalError("PM_getFileAttr not implemented yet!"); - return 0; -} - -/**************************************************************************** -REMARKS: -Function to create a directory. -****************************************************************************/ -ibool PMAPI PM_mkdir( - const char *filename) -{ - /* TODO: Implement this */ - (void)filename; - PM_fatalError("PM_mkdir not implemented yet!"); - return false; -} - -/**************************************************************************** -REMARKS: -Function to remove a directory. -****************************************************************************/ -ibool PMAPI PM_rmdir( - const char *filename) -{ - /* TODO: Implement this */ - (void)filename; - PM_fatalError("PM_rmdir not implemented yet!"); - return false; -} - -/**************************************************************************** -REMARKS: -Function to get the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_getFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* TODO: Implement this! */ - (void)filename; - (void)gmTime; - (void)time; - PM_fatalError("PM_getFileTime not implemented yet!"); - return false; -} - -/**************************************************************************** -REMARKS: -Function to set the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_setFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - /* TODO: Implement this! */ - (void)filename; - (void)gmTime; - (void)time; - PM_fatalError("PM_setFileTime not implemented yet!"); - return false; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c deleted file mode 100644 index 901ce1c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Dummy module; no virtual framebuffer for this OS -* -****************************************************************************/ - -#include "pmapi.h" - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) -{ - return NULL; -} - -void PMAPI VF_exit(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c deleted file mode 100644 index 76df48c..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: 32-bit Windows VxD -* -* Description: OS specific implementation for the Zen Timer functions. -* -****************************************************************************/ - -/*---------------------------- Global variables ---------------------------*/ - -static ulong frequency = 1193180; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -#define __ZTimerInit() - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerOn(tm) VTD_Get_Real_Time(&tm->start.high,&tm->start.low) - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -static ulong __LZTimerLap( - LZTimerObject *tm) -{ - CPU_largeInteger lap,count; - VTD_Get_Real_Time(&lap.high,&lap.low); - _CPU_diffTime64(&tm->start,&lap,&count); - return _CPU_calcMicroSec(&count,frequency); -} - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -#define __LZTimerOff(tm) VTD_Get_Real_Time(&tm->end.high,&tm->end.low) - -/**************************************************************************** -REMARKS: -Call the assembler Zen Timer functions to do the timing. -****************************************************************************/ -static ulong __LZTimerCount( - LZTimerObject *tm) -{ - CPU_largeInteger tmCount; - _CPU_diffTime64(&tm->start,&tm->end,&tmCount); - return _CPU_calcMicroSec(&tmCount,frequency); -} - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as microseconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION 1000 - -/**************************************************************************** -REMARKS: -Read the Long Period timer value from the BIOS timer tick. -****************************************************************************/ -static ulong __ULZReadTime(void) -{ - CPU_largeInteger count; - VTD_Get_Real_Time(&count.high,&count.low); - return (count.low * 1000.0 / frequency); -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong __ULZElapsedTime(ulong start,ulong finish) -{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm b/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm deleted file mode 100644 index 7c242b5..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm +++ /dev/null @@ -1,78 +0,0 @@ -;**************************************************************************** -;* -;* SciTech OS Portability Manager Library -;* -;* ======================================================================== -;* -;* The contents of this file are subject to the SciTech MGL Public -;* License Version 1.0 (the "License"); you may not use this file -;* except in compliance with the License. You may obtain a copy of -;* the License at http://www.scitechsoft.com/mgl-license.txt -;* -;* Software distributed under the License is distributed on an -;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -;* implied. See the License for the specific language governing -;* rights and limitations under the License. -;* -;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -;* -;* The Initial Developer of the Original Code is SciTech Software, Inc. -;* All Rights Reserved. -;* -;* ======================================================================== -;* -;* Language: 80386 Assembler, TASM 4.0 or NASM -;* Environment: Win32 -;* -;* Description: Low level assembly support for the PM library specific -;* to Windows. -;* -;**************************************************************************** - - IDEAL - -include "scitech.mac" ; Memory model macros - -header _pmwin32 ; Set up memory model - -begdataseg _pmwin32 - - cglobal _PM_ioentry - cglobal _PM_gdt -_PM_ioentry dd 0 ; Offset to call gate -_PM_gdt dw 0 ; Selector to call gate - -enddataseg _pmwin32 - -begcodeseg _pmwin32 ; Start of code segment - -;---------------------------------------------------------------------------- -; int PM_setIOPL(int iopl) -;---------------------------------------------------------------------------- -; Change the IOPL level for the 32-bit task. Returns the previous level -; so it can be restored for the task correctly. -;---------------------------------------------------------------------------- -cprocstart _PM_setIOPLViaCallGate - - ARG iopl:UINT - - enter_c - pushfd ; Save the old EFLAGS for later - mov ecx,[iopl] ; ECX := IOPL level - xor ebx,ebx ; Change IOPL level function code -ifdef USE_NASM - call far dword [_PM_ioentry] -else - call [FWORD _PM_ioentry] -endif - pop eax - and eax,0011000000000000b - shr eax,12 - leave_c - ret - -cprocend - -endcodeseg _pmwin32 - - END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c deleted file mode 100644 index 7da9752..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c +++ /dev/null @@ -1,94 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Win32 -* -* Description: Module to implement OS specific services to measure the -* CPU frequency. -* -****************************************************************************/ - -/*---------------------------- Global variables ---------------------------*/ - -static ibool havePerformanceCounter; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Increase the thread priority to maximum, if possible. -****************************************************************************/ -static int SetMaxThreadPriority(void) -{ - int oldPriority; - HANDLE hThread = GetCurrentThread(); - - oldPriority = GetThreadPriority(hThread); - if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) - SetThreadPriority(hThread, THREAD_PRIORITY_TIME_CRITICAL); - return oldPriority; -} - -/**************************************************************************** -REMARKS: -Restore the original thread priority. -****************************************************************************/ -static void RestoreThreadPriority( - int oldPriority) -{ - HANDLE hThread = GetCurrentThread(); - - if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) - SetThreadPriority(hThread, oldPriority); -} - -/**************************************************************************** -REMARKS: -Initialise the counter and return the frequency of the counter. -****************************************************************************/ -static void GetCounterFrequency( - CPU_largeInteger *freq) -{ - if (!QueryPerformanceFrequency((LARGE_INTEGER*)freq)) { - havePerformanceCounter = false; - freq->low = 100000; - freq->high = 0; - } - else - havePerformanceCounter = true; -} - -/**************************************************************************** -REMARKS: -Read the counter and return the counter value. -****************************************************************************/ -#define GetCounter(t) \ -{ \ - if (havePerformanceCounter) \ - QueryPerformanceCounter((LARGE_INTEGER*)t); \ - else { \ - (t)->low = timeGetTime() * 100; \ - (t)->high = 0; \ - } \ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c deleted file mode 100644 index d6c3f60..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c +++ /dev/null @@ -1,582 +0,0 @@ -/**************************************************************************** -* -* SciTech Multi-platform Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Win32 -* -* Description: Win32 implementation for the SciTech cross platform -* event library. -* -****************************************************************************/ - -#include "event.h" -#include "pmapi.h" -#include "win32/oshdr.h" -#include "nucleus/graphics.h" - -/*---------------------------- Global Variables ---------------------------*/ - -/* Publicly accessible variables */ - -int _PM_deskX,_PM_deskY;/* Desktop dimentions */ -HWND _PM_hwndConsole; /* Window handle for console */ -#ifdef __INTEL__ -uint _PM_cw_default; /* Default FPU control word */ -#endif - -/* Private internal variables */ - -static HINSTANCE hInstApp = NULL;/* Application instance handle */ -static HWND hwndUser = NULL;/* User window handle */ -static HINSTANCE hInstDD = NULL; /* Handle to DirectDraw DLL */ -static LPDIRECTDRAW lpDD = NULL; /* DirectDraw object */ -static LONG oldWndStyle; /* Info about old user window */ -static LONG oldExWndStyle; /* Info about old user window */ -static int oldWinPosX; /* Old window position X coordinate */ -static int oldWinPosY; /* Old window pisition Y coordinate */ -static int oldWinSizeX; /* Old window size X */ -static int oldWinSizeY; /* Old window size Y */ -static WNDPROC oldWinProc = NULL; -static PM_saveState_cb suspendApp = NULL; -static ibool waitActive = false; -static ibool isFullScreen = false; -static ibool backInGDI = false; - -/* Internal strings */ - -static char *szWinClassName = "SciTechDirectDrawWindow"; -static char *szAutoPlayKey = "Software\\Microsoft\\Windows\\CurrentVersion\\Policies\\Explorer"; -static char *szAutoPlayValue = "NoDriveTypeAutoRun"; - -/* Dynalinks to DirectDraw functions */ - -static HRESULT (WINAPI *pDirectDrawCreate)(GUID FAR *lpGUID, LPDIRECTDRAW FAR *lplpDD, IUnknown FAR *pUnkOuter); - -/*---------------------------- Implementation -----------------------------*/ - -/**************************************************************************** -REMARKS: -Temporarily disables AutoPlay operation while we are running in fullscreen -graphics modes. -****************************************************************************/ -static void DisableAutoPlay(void) -{ - DWORD dwAutoPlay,dwSize = sizeof(dwAutoPlay); - HKEY hKey; - - if (RegOpenKeyEx(HKEY_CURRENT_USER,szAutoPlayKey,0,KEY_EXECUTE | KEY_WRITE,&hKey) == ERROR_SUCCESS) { - RegQueryValueEx(hKey,szAutoPlayValue,NULL,NULL,(void*)&dwAutoPlay,&dwSize); - dwAutoPlay |= AUTOPLAY_DRIVE_CDROM; - RegSetValueEx(hKey,szAutoPlayValue,0,REG_DWORD,(void*)&dwAutoPlay,dwSize); - RegCloseKey(hKey); - } -} - -/**************************************************************************** -REMARKS: -Re-enables AutoPlay operation when we return to regular GDI mode. -****************************************************************************/ -static void RestoreAutoPlay(void) -{ - DWORD dwAutoPlay,dwSize = sizeof(dwAutoPlay); - HKEY hKey; - - if (RegOpenKeyEx(HKEY_CURRENT_USER,szAutoPlayKey,0,KEY_EXECUTE | KEY_WRITE,&hKey) == ERROR_SUCCESS) { - RegQueryValueEx(hKey,szAutoPlayValue,NULL,NULL,(void*)&dwAutoPlay,&dwSize); - dwAutoPlay &= ~AUTOPLAY_DRIVE_CDROM; - RegSetValueEx(hKey,szAutoPlayValue,0,REG_DWORD,(void*)&dwAutoPlay,dwSize); - RegCloseKey(hKey); - } -} - -/**************************************************************************** -REMARKS: -Suspends the application by switching back to the GDI desktop, allowing -normal application code to be processed, and then waiting for the -application activate command to bring us back to fullscreen mode with our -window minimised. -****************************************************************************/ -static void LeaveFullScreen(void) -{ - int retCode = PM_SUSPEND_APP; - - if (backInGDI) - return; - if (suspendApp) - retCode = suspendApp(PM_DEACTIVATE); - RestoreAutoPlay(); - backInGDI = true; - - /* Now process messages normally until we are re-activated */ - waitActive = true; - if (retCode != PM_NO_SUSPEND_APP) { - while (waitActive) { - _EVT_pumpMessages(); - Sleep(200); - } - } -} - -/**************************************************************************** -REMARKS: -Reactivate all the surfaces for DirectDraw and set the system back up for -fullscreen rendering. -****************************************************************************/ -static void RestoreFullScreen(void) -{ - static ibool firstTime = true; - - if (firstTime) { - /* Clear the message queue while waiting for the surfaces to be - * restored. - */ - firstTime = false; - while (1) { - /* Continue looping until out application has been restored - * and we have reset the display mode. - */ - _EVT_pumpMessages(); - if (GetActiveWindow() == _PM_hwndConsole) { - if (suspendApp) - suspendApp(PM_REACTIVATE); - DisableAutoPlay(); - backInGDI = false; - waitActive = false; - firstTime = true; - return; - } - Sleep(200); - } - } -} - -/**************************************************************************** -REMARKS: -This function suspends the application by switching back to the GDI desktop, -allowing normal application code to be processed and then waiting for the -application activate command to bring us back to fullscreen mode with our -window minimised. - -This version only gets called if we have not captured the screen switch in -our activate message loops and will occur if the DirectDraw drivers lose a -surface for some reason while rendering. This should not normally happen, -but it is included just to be sure (it can happen on WinNT/2000 if the user -hits the Ctrl-Alt-Del key combination). Note that this code will always -spin loop, and we cannot disable the spin looping from this version (ie: -if the user hits Ctrl-Alt-Del under WinNT/2000 the application main loop -will cease to be executed until the user switches back to the application). -****************************************************************************/ -void PMAPI PM_doSuspendApp(void) -{ - static ibool firstTime = true; - - /* Call system DLL version if found */ - if (_PM_imports.PM_doSuspendApp != PM_doSuspendApp) { - _PM_imports.PM_doSuspendApp(); - return; - } - - if (firstTime) { - if (suspendApp) - suspendApp(PM_DEACTIVATE); - RestoreAutoPlay(); - firstTime = false; - backInGDI = true; - } - RestoreFullScreen(); - firstTime = true; -} - -/**************************************************************************** -REMARKS: -Main Window proc for the full screen DirectDraw Window that we create while -running in full screen mode. Here we capture all mouse and keyboard events -for the window and plug them into our event queue. -****************************************************************************/ -static LONG CALLBACK PM_winProc( - HWND hwnd, - UINT msg, - WPARAM wParam, - LONG lParam) -{ - switch (msg) { - case WM_SYSCHAR: - /* Stop Alt-Space from pausing our application */ - return 0; - case WM_KEYDOWN: - case WM_SYSKEYDOWN: - if (HIWORD(lParam) & KF_REPEAT) { - if (msg == WM_SYSKEYDOWN) - return 0; - break; - } - /* Fall through for keydown events */ - case WM_KEYUP: - case WM_SYSKEYUP: - if (msg == WM_SYSKEYDOWN || msg == WM_SYSKEYUP) { - if ((HIWORD(lParam) & KF_ALTDOWN) && wParam == VK_RETURN) - break; - /* We ignore the remainder of the system keys to stop the - * system menu from being activated from the keyboard and pausing - * our app while fullscreen (ie: pressing the Alt key). - */ - return 0; - } - break; - case WM_SYSCOMMAND: - switch (wParam & ~0x0F) { - case SC_SCREENSAVE: - case SC_MONITORPOWER: - /* Ignore screensaver requests in fullscreen modes */ - return 0; - } - break; - case WM_SIZE: - if (waitActive && backInGDI && (wParam != SIZE_MINIMIZED)) { - /* Start the re-activation process */ - PostMessage(hwnd,WM_DO_SUSPEND_APP,WM_PM_RESTORE_FULLSCREEN,0); - } - else if (!waitActive && isFullScreen && !backInGDI && (wParam == SIZE_MINIMIZED)) { - /* Start the de-activation process */ - PostMessage(hwnd,WM_DO_SUSPEND_APP,WM_PM_LEAVE_FULLSCREEN,0); - } - break; - case WM_DO_SUSPEND_APP: - switch (wParam) { - case WM_PM_RESTORE_FULLSCREEN: - RestoreFullScreen(); - break; - case WM_PM_LEAVE_FULLSCREEN: - LeaveFullScreen(); - break; - } - return 0; - } - if (oldWinProc) - return oldWinProc(hwnd,msg,wParam,lParam); - return DefWindowProc(hwnd,msg,wParam,lParam); -} - -/**************************************************************************** -PARAMETERS: -hwnd - User window to convert -width - Window of the fullscreen window -height - Height of the fullscreen window - -RETURNS: -Handle to converted fullscreen Window. - -REMARKS: -This function takes the original user window handle and modifies the size, -position and attributes for the window to convert it into a fullscreen -window that we can use. -****************************************************************************/ -static PM_HWND _PM_convertUserWindow( - HWND hwnd, - int width, - int height) -{ - RECT window; - - GetWindowRect(hwnd,&window); - oldWinPosX = window.left; - oldWinPosY = window.top; - oldWinSizeX = window.right - window.left; - oldWinSizeY = window.bottom - window.top; - oldWndStyle = SetWindowLong(hwnd,GWL_STYLE,WS_POPUP | WS_SYSMENU); - oldExWndStyle = SetWindowLong(hwnd,GWL_EXSTYLE,WS_EX_APPWINDOW); - ShowWindow(hwnd,SW_SHOW); - MoveWindow(hwnd,0,0,width,height,TRUE); - SetWindowPos(hwnd,HWND_TOPMOST,0,0,0,0,SWP_NOMOVE | SWP_NOSIZE); - oldWinProc = (WNDPROC)SetWindowLong(hwnd,GWL_WNDPROC, (LPARAM)PM_winProc); - return hwnd; -} - -/**************************************************************************** -PARAMETERS: -hwnd - User window to restore - -REMARKS: -This function restores the original attributes of the user window and put's -it back into it's original state before it was converted to a fullscreen -window. -****************************************************************************/ -static void _PM_restoreUserWindow( - HWND hwnd) -{ - SetWindowLong(hwnd,GWL_WNDPROC, (LPARAM)oldWinProc); - SetWindowLong(hwnd,GWL_EXSTYLE,oldExWndStyle); - SetWindowLong(hwnd,GWL_STYLE,oldWndStyle); - SetWindowPos(hwnd,HWND_NOTOPMOST,0,0,0,0,SWP_NOMOVE | SWP_NOSIZE); - ShowWindow(hwnd,SW_SHOW); - MoveWindow(hwnd,oldWinPosX,oldWinPosY,oldWinSizeX,oldWinSizeY,TRUE); - oldWinProc = NULL; -} - -/**************************************************************************** -PARAMETERS: -device - Index of the device to load DirectDraw for (0 for primary) - -REMARKS: -Attempts to dynamically load the DirectDraw DLL's and create the DirectDraw -objects that we need. -****************************************************************************/ -void * PMAPI PM_loadDirectDraw( - int device) -{ - HDC hdc; - int bits; - - /* Call system DLL version if found */ - if (_PM_imports.PM_loadDirectDraw != PM_loadDirectDraw) - return _PM_imports.PM_loadDirectDraw(device); - - /* TODO: Handle multi-monitor!! */ - if (device != 0) - return NULL; - - /* Load the DirectDraw DLL if not presently loaded */ - GET_DEFAULT_CW(); - if (!hInstDD) { - hdc = GetDC(NULL); - bits = GetDeviceCaps(hdc,BITSPIXEL); - ReleaseDC(NULL,hdc); - if (bits < 8) - return NULL; - if ((hInstDD = LoadLibrary("ddraw.dll")) == NULL) - return NULL; - pDirectDrawCreate = (void*)GetProcAddress(hInstDD,"DirectDrawCreate"); - if (!pDirectDrawCreate) - return NULL; - } - - /* Create the DirectDraw object */ - if (!lpDD && pDirectDrawCreate(NULL, &lpDD, NULL) != DD_OK) { - lpDD = NULL; - return NULL; - } - RESET_DEFAULT_CW(); - return lpDD; -} - -/**************************************************************************** -PARAMETERS: -device - Index of the device to unload DirectDraw for (0 for primary) - -REMARKS: -Frees any DirectDraw objects for the device. We never actually explicitly -unload the ddraw.dll library, since unloading and reloading it is -unnecessary since we only want to unload it when the application exits and -that happens automatically. -****************************************************************************/ -void PMAPI PM_unloadDirectDraw( - int device) -{ - /* Call system DLL version if found */ - if (_PM_imports.PM_unloadDirectDraw != PM_unloadDirectDraw) { - _PM_imports.PM_unloadDirectDraw(device); - return; - } - if (lpDD) { - IDirectDraw_Release(lpDD); - lpDD = NULL; - } - (void)device; -} - -/**************************************************************************** -REMARKS: -Open a console for output to the screen, creating the main event handling -window if necessary. -****************************************************************************/ -PM_HWND PMAPI PM_openConsole( - PM_HWND hWndUser, - int device, - int xRes, - int yRes, - int bpp, - ibool fullScreen) -{ - WNDCLASS cls; - static ibool classRegistered = false; - - /* Call system DLL version if found */ - GA_getSystemPMImports(); - if (_PM_imports.PM_openConsole != PM_openConsole) { - if (fullScreen) { - _PM_deskX = xRes; - _PM_deskY = yRes; - } - return _PM_imports.PM_openConsole(hWndUser,device,xRes,yRes,bpp,fullScreen); - } - - /* Create the fullscreen window if necessary */ - hwndUser = hWndUser; - if (fullScreen) { - if (!classRegistered) { - /* Create a Window class for the fullscreen window in here, since - * we need to register one that will do all our event handling for - * us. - */ - hInstApp = GetModuleHandle(NULL); - cls.hCursor = LoadCursor(NULL,IDC_ARROW); - cls.hIcon = LoadIcon(hInstApp,MAKEINTRESOURCE(1)); - cls.lpszMenuName = NULL; - cls.lpszClassName = szWinClassName; - cls.hbrBackground = GetStockObject(BLACK_BRUSH); - cls.hInstance = hInstApp; - cls.style = CS_DBLCLKS; - cls.lpfnWndProc = PM_winProc; - cls.cbWndExtra = 0; - cls.cbClsExtra = 0; - if (!RegisterClass(&cls)) - return NULL; - classRegistered = true; - } - _PM_deskX = xRes; - _PM_deskY = yRes; - if (!hwndUser) { - char windowTitle[80]; - if (LoadString(hInstApp,1,windowTitle,sizeof(windowTitle)) == 0) - strcpy(windowTitle,"MGL Fullscreen Application"); - _PM_hwndConsole = CreateWindowEx(WS_EX_APPWINDOW,szWinClassName, - windowTitle,WS_POPUP | WS_SYSMENU,0,0,xRes,yRes, - NULL,NULL,hInstApp,NULL); - } - else { - _PM_hwndConsole = _PM_convertUserWindow(hwndUser,xRes,yRes); - } - ShowCursor(false); - isFullScreen = true; - } - else { - _PM_hwndConsole = hwndUser; - isFullScreen = false; - } - SetFocus(_PM_hwndConsole); - SetForegroundWindow(_PM_hwndConsole); - DisableAutoPlay(); - (void)bpp; - return _PM_hwndConsole; -} - -/**************************************************************************** -REMARKS: -Find the size of the console state buffer. -****************************************************************************/ -int PMAPI PM_getConsoleStateSize(void) -{ - /* Call system DLL version if found */ - if (_PM_imports.PM_getConsoleStateSize != PM_getConsoleStateSize) - return _PM_imports.PM_getConsoleStateSize(); - - /* Not used in Windows */ - return 1; -} - -/**************************************************************************** -REMARKS: -Save the state of the console. -****************************************************************************/ -void PMAPI PM_saveConsoleState( - void *stateBuf, - PM_HWND hwndConsole) -{ - /* Call system DLL version if found */ - if (_PM_imports.PM_saveConsoleState != PM_saveConsoleState) { - _PM_imports.PM_saveConsoleState(stateBuf,hwndConsole); - return; - } - - /* Not used in Windows */ - (void)stateBuf; - (void)hwndConsole; -} - -/**************************************************************************** -REMARKS: -Set the suspend application callback for the fullscreen console. -****************************************************************************/ -void PMAPI PM_setSuspendAppCallback( - PM_saveState_cb saveState) -{ - /* Call system DLL version if found */ - if (_PM_imports.PM_setSuspendAppCallback != PM_setSuspendAppCallback) { - _PM_imports.PM_setSuspendAppCallback(saveState); - return; - } - suspendApp = saveState; -} - -/**************************************************************************** -REMARKS: -Restore the console state. -****************************************************************************/ -void PMAPI PM_restoreConsoleState( - const void *stateBuf, - PM_HWND hwndConsole) -{ - /* Call system DLL version if found */ - if (_PM_imports.PM_restoreConsoleState != PM_restoreConsoleState) { - _PM_imports.PM_restoreConsoleState(stateBuf,hwndConsole); - return; - } - - /* Not used in Windows */ - (void)stateBuf; - (void)hwndConsole; -} - -/**************************************************************************** -REMARKS: -Close the fullscreen console. -****************************************************************************/ -void PMAPI PM_closeConsole( - PM_HWND hwndConsole) -{ - /* Call system DLL version if found */ - if (_PM_imports.PM_closeConsole != PM_closeConsole) { - _PM_imports.PM_closeConsole(hwndConsole); - return; - } - ShowCursor(true); - RestoreAutoPlay(); - if (hwndUser) - _PM_restoreUserWindow(hwndConsole); - else - DestroyWindow(hwndConsole); - hwndUser = NULL; - _PM_hwndConsole = NULL; -} - -/**************************************************************************** -REMARKS: -Return the DirectDraw window handle used by the application. -****************************************************************************/ -PM_HWND PMAPI PM_getDirectDrawWindow(void) -{ - /* Call system DLL version if found */ - if (_PM_imports.PM_getDirectDrawWindow != PM_getDirectDrawWindow) - return _PM_imports.PM_getDirectDrawWindow(); - return _PM_hwndConsole; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/event.c b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c deleted file mode 100644 index 86448e3..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/win32/event.c +++ /dev/null @@ -1,459 +0,0 @@ -/**************************************************************************** -* -* SciTech Multi-platform Graphics Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Win32 -* -* Description: Win32 implementation for the SciTech cross platform -* event library. -* -****************************************************************************/ - -/*---------------------------- Global Variables ---------------------------*/ - -static ushort keyUpMsg[256] = {0}; /* Table of key up messages */ -static int rangeX,rangeY; /* Range of mouse coordinates */ - -/*---------------------------- Implementation -----------------------------*/ - -/* These are not used under Win32 */ -#define _EVT_disableInt() 1 -#define _EVT_restoreInt(flags) (void)(flags) - -/**************************************************************************** -PARAMETERS: -scanCode - Scan code to test - -REMARKS: -This macro determines if a specified key is currently down at the -time that the call is made. -****************************************************************************/ -#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) - -/**************************************************************************** -REMARKS: -This function is used to return the number of ticks since system -startup in milliseconds. This should be the same value that is placed into -the time stamp fields of events, and is used to implement auto mouse down -events. -****************************************************************************/ -ulong _EVT_getTicks(void) -{ return timeGetTime(); } - -/**************************************************************************** -REMARKS: -Pumps all messages in the message queue from Win32 into our event queue. -****************************************************************************/ -void _EVT_pumpMessages(void) -{ - MSG msg; - MSG charMsg; - event_t evt; - - /* TODO: Add support for DirectInput! We can't support relative mouse */ - /* movement motion counters without DirectInput ;-(. */ - while (PeekMessage(&msg,NULL,0,0,PM_REMOVE)) { - memset(&evt,0,sizeof(evt)); - switch (msg.message) { - case WM_MOUSEMOVE: - evt.what = EVT_MOUSEMOVE; - break; - case WM_LBUTTONDBLCLK: - evt.what = EVT_MOUSEDOWN; - evt.message = EVT_LEFTBMASK | EVT_DBLCLICK; - break; - case WM_LBUTTONDOWN: - evt.what = EVT_MOUSEDOWN; - evt.message = EVT_LEFTBMASK; - break; - case WM_LBUTTONUP: - evt.what = EVT_MOUSEUP; - evt.message = EVT_LEFTBMASK; - break; - case WM_RBUTTONDBLCLK: - evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK; - evt.message = EVT_RIGHTBMASK; - break; - case WM_RBUTTONDOWN: - evt.what = EVT_MOUSEDOWN; - evt.message = EVT_RIGHTBMASK; - break; - case WM_RBUTTONUP: - evt.what = EVT_MOUSEUP; - evt.message = EVT_RIGHTBMASK; - break; - case WM_MBUTTONDBLCLK: - evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK; - evt.message = EVT_MIDDLEBMASK; - break; - case WM_MBUTTONDOWN: - evt.what = EVT_MOUSEDOWN; - evt.message = EVT_MIDDLEBMASK; - break; - case WM_MBUTTONUP: - evt.what = EVT_MOUSEUP; - evt.message = EVT_MIDDLEBMASK; - break; - case WM_KEYDOWN: - case WM_SYSKEYDOWN: - if (HIWORD(msg.lParam) & KF_REPEAT) { - evt.what = EVT_KEYREPEAT; - } - else { - evt.what = EVT_KEYDOWN; - } - break; - case WM_KEYUP: - case WM_SYSKEYUP: - evt.what = EVT_KEYUP; - break; - } - - /* Convert mouse event modifier flags */ - if (evt.what & EVT_MOUSEEVT) { - if (_PM_deskX) { - evt.where_x = ((long)msg.pt.x * rangeX) / _PM_deskX; - evt.where_y = ((long)msg.pt.y * rangeY) / _PM_deskY; - } - else { - ScreenToClient(_PM_hwndConsole, &msg.pt); - evt.where_x = msg.pt.x; - evt.where_y = msg.pt.y; - } - if (evt.what == EVT_MOUSEMOVE) { - /* Save the current mouse position */ - EVT.mx = evt.where_x; - EVT.my = evt.where_y; - if (EVT.oldMove != -1) { - EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one */ - EVT.evtq[EVT.oldMove].where_y = evt.where_y; -/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; // TODO! */ -/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; // TODO! */ - evt.what = 0; - } - else { - EVT.oldMove = EVT.freeHead; /* Save id of this move event */ -/* evt.relative_x = mickeyX; // TODO! */ -/* evt.relative_y = mickeyY; // TODO! */ - } - } - else - EVT.oldMove = -1; - if (msg.wParam & MK_LBUTTON) - evt.modifiers |= EVT_LEFTBUT; - if (msg.wParam & MK_RBUTTON) - evt.modifiers |= EVT_RIGHTBUT; - if (msg.wParam & MK_MBUTTON) - evt.modifiers |= EVT_MIDDLEBUT; - if (msg.wParam & MK_SHIFT) - evt.modifiers |= EVT_SHIFTKEY; - if (msg.wParam & MK_CONTROL) - evt.modifiers |= EVT_CTRLSTATE; - } - - /* Convert keyboard codes */ - TranslateMessage(&msg); - if (evt.what & EVT_KEYEVT) { - int scanCode = (msg.lParam >> 16) & 0xFF; - if (evt.what == EVT_KEYUP) { - /* Get message for keyup code from table of cached down values */ - evt.message = keyUpMsg[scanCode]; - keyUpMsg[scanCode] = 0; - } - else { - if (PeekMessage(&charMsg,NULL,WM_CHAR,WM_CHAR,PM_REMOVE)) - evt.message = charMsg.wParam; - if (PeekMessage(&charMsg,NULL,WM_SYSCHAR,WM_SYSCHAR,PM_REMOVE)) - evt.message = charMsg.wParam; - evt.message |= ((msg.lParam >> 8) & 0xFF00); - keyUpMsg[scanCode] = (ushort)evt.message; - } - if (evt.what == EVT_KEYREPEAT) - evt.message |= (msg.lParam << 16); - if (HIWORD(msg.lParam) & KF_ALTDOWN) - evt.modifiers |= EVT_ALTSTATE; - if (GetKeyState(VK_SHIFT) & 0x8000U) - evt.modifiers |= EVT_SHIFTKEY; - if (GetKeyState(VK_CONTROL) & 0x8000U) - evt.modifiers |= EVT_CTRLSTATE; - EVT.oldMove = -1; - } - - if (evt.what != 0) { - /* Add time stamp and add the event to the queue */ - evt.when = msg.time; - if (EVT.count < EVENTQSIZE) - addEvent(&evt); - } - DispatchMessage(&msg); - } -} - -/**************************************************************************** -REMARKS: -This macro/function is used to converts the scan codes reported by the -keyboard to our event libraries normalised format. We only have one scan -code for the 'A' key, and use shift modifiers to determine if it is a -Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, -but the OS gives us 'cooked' scan codes, we have to translate them back -to the raw format. -****************************************************************************/ -#define _EVT_maskKeyCode(evt) - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _EVT_abort( - int signal) -{ - (void)signal; - EVT_exit(); - PM_fatalError("Unhandled exception!"); -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -void EVTAPI EVT_init( - _EVT_mouseMoveHandler mouseMove) -{ - /* Initialise the event queue */ - EVT.mouseMove = mouseMove; - initEventQueue(); - memset(keyUpMsg,0,sizeof(keyUpMsg)); - - /* Catch program termination signals so we can clean up properly */ - signal(SIGABRT, _EVT_abort); - signal(SIGFPE, _EVT_abort); - signal(SIGINT, _EVT_abort); -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - rangeX = xRes; - rangeY = yRes; -} - -/**************************************************************************** -REMARKS -Modifes the mouse coordinates as necessary if scaling to OS coordinates, -and sets the OS mouse cursor position. -****************************************************************************/ -void _EVT_setMousePos( - int *x, - int *y) -{ - /* Scale coordinates up to desktop coordinates first */ - int scaledX = (*x * _PM_deskX) / rangeX; - int scaledY = (*y * _PM_deskY) / rangeY; - - /* Scale coordinates back to screen coordinates again */ - *x = (scaledX * rangeX) / _PM_deskX; - *y = (scaledY * rangeY) / _PM_deskY; - SetCursorPos(scaledX,scaledY); -} - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVT_resume(void) -{ - /* Do nothing for Win32 */ -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVT_suspend(void) -{ - /* Do nothing for Win32 */ -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVT_exit(void) -{ - /* Restore signal handlers */ - signal(SIGABRT, SIG_DFL); - signal(SIGFPE, SIG_DFL); - signal(SIGINT, SIG_DFL); -} - -/**************************************************************************** -DESCRIPTION: -Returns the mask indicating what joystick axes are attached. - -HEADER: -event.h - -REMARKS: -This function is used to detect the attached joysticks, and determine -what axes are present and functioning. This function will re-detect any -attached joysticks when it is called, so if the user forgot to attach -the joystick when the application started, you can call this function to -re-detect any newly attached joysticks. - -SEE ALSO: -EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent -****************************************************************************/ -int EVTAPI EVT_joyIsPresent(void) -{ - /* TODO: Implement joystick code based on DirectX! */ - return 0; -} - -/**************************************************************************** -DESCRIPTION: -Polls the joystick for position and button information. - -HEADER: -event.h - -REMARKS: -This routine is used to poll analogue joysticks for button and position -information. It should be called once for each main loop of the user -application, just before processing all pending events via EVT_getNext. -All information polled from the joystick will be posted to the event -queue for later retrieval. - -Note: Most analogue joysticks will provide readings that change even - though the joystick has not moved. Hence if you call this routine - you will likely get an EVT_JOYMOVE event every time through your - event loop. - -SEE ALSO: -EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight, -EVT_joySetCenter, EVT_joyIsPresent -****************************************************************************/ -void EVTAPI EVT_pollJoystick(void) -{ -} - -/**************************************************************************** -DESCRIPTION: -Calibrates the joystick upper left position - -HEADER: -event.h - -REMARKS: -This function can be used to zero in on better joystick calibration factors, -which may work better than the default simplistic calibration (which assumes -the joystick is centered when the event library is initialised). -To use this function, ask the user to hold the stick in the upper left -position and then have them press a key or button. and then call this -function. This function will then read the joystick and update the -calibration factors. - -Usually, assuming that the stick was centered when the event library was -initialized, you really only need to call EVT_joySetLowerRight since the -upper left position is usually always 0,0 on most joysticks. However, the -safest procedure is to call all three calibration functions. - -SEE ALSO: -EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent -****************************************************************************/ -void EVTAPI EVT_joySetUpperLeft(void) -{ -} - -/**************************************************************************** -DESCRIPTION: -Calibrates the joystick lower right position - -HEADER: -event.h - -REMARKS: -This function can be used to zero in on better joystick calibration factors, -which may work better than the default simplistic calibration (which assumes -the joystick is centered when the event library is initialised). -To use this function, ask the user to hold the stick in the lower right -position and then have them press a key or button. and then call this -function. This function will then read the joystick and update the -calibration factors. - -Usually, assuming that the stick was centered when the event library was -initialized, you really only need to call EVT_joySetLowerRight since the -upper left position is usually always 0,0 on most joysticks. However, the -safest procedure is to call all three calibration functions. - -SEE ALSO: -EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent -****************************************************************************/ -void EVTAPI EVT_joySetLowerRight(void) -{ -} - -/**************************************************************************** -DESCRIPTION: -Calibrates the joystick center position - -HEADER: -event.h - -REMARKS: -This function can be used to zero in on better joystick calibration factors, -which may work better than the default simplistic calibration (which assumes -the joystick is centered when the event library is initialised). -To use this function, ask the user to hold the stick in the center -position and then have them press a key or button. and then call this -function. This function will then read the joystick and update the -calibration factors. - -Usually, assuming that the stick was centered when the event library was -initialized, you really only need to call EVT_joySetLowerRight since the -upper left position is usually always 0,0 on most joysticks. However, the -safest procedure is to call all three calibration functions. - -SEE ALSO: -EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter -****************************************************************************/ -void EVTAPI EVT_joySetCenter(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c deleted file mode 100644 index 59d9aa0..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c +++ /dev/null @@ -1,258 +0,0 @@ -/**************************************************************************** -* -* SciTech Display Doctor -* -* Copyright (C) 1991-2001 SciTech Software, Inc. -* All rights reserved. -* -* ====================================================================== -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* | | -* |This copyrighted computer code is a proprietary trade secret of | -* |SciTech Software, Inc., located at 505 Wall Street, Chico, CA 95928 | -* |USA (www.scitechsoft.com). ANY UNAUTHORIZED POSSESSION, USE, | -* |VIEWING, COPYING, MODIFICATION OR DISSEMINATION OF THIS CODE IS | -* |STRICTLY PROHIBITED BY LAW. Unless you have current, express | -* |written authorization from SciTech to possess or use this code, you | -* |may be subject to civil and/or criminal penalties. | -* | | -* |If you received this code in error or you would like to report | -* |improper use, please immediately contact SciTech Software, Inc. at | -* |530-894-8400. | -* | | -* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| -* ====================================================================== -* -* Language: ANSI C -* Environment: Windows NT, Windows 2K or Windows XP. -* -* Description: Main module to do the installation of the SDD and GLDirect -* device driver components under Windows NT/2K/XP. -* -****************************************************************************/ - -#include "pmapi.h" -#include "win32/oshdr.h" - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -PARAMETERS: -szDriverName - Actual name of the driver to install in the system -szServiceName - Name of the service to create -szLoadGroup - Load group for the driver (NULL for normal drivers) -dwServiceType - Service type to create - -RETURNS: -True on success, false on failure. - -REMARKS: -This function does all the work to install the driver into the system. -The driver is not however activated; for that you must use the Start_SddFilt -function. -****************************************************************************/ -ulong PMAPI PM_installService( - const char *szDriverName, - const char *szServiceName, - const char *szLoadGroup, - ulong dwServiceType) -{ - SC_HANDLE scmHandle; - SC_HANDLE driverHandle; - char szDriverPath[MAX_PATH]; - HKEY key; - char keyPath[MAX_PATH]; - ulong status; - - /* Obtain a handle to the service control manager requesting all access */ - if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) - return GetLastError(); - - /* Find the path to the driver in system directory */ - GetSystemDirectory(szDriverPath, sizeof(szDriverPath)); - strcat(szDriverPath, "\\drivers\\"); - strcat(szDriverPath, szDriverName); - - /* Create the service with the Service Control Manager. */ - driverHandle = CreateService(scmHandle, - szServiceName, - szServiceName, - SERVICE_ALL_ACCESS, - dwServiceType, - SERVICE_BOOT_START, - SERVICE_ERROR_NORMAL, - szDriverPath, - szLoadGroup, - NULL, - NULL, - NULL, - NULL); - - /* Check to see if the driver could actually be installed. */ - if (!driverHandle) { - status = GetLastError(); - CloseServiceHandle(scmHandle); - return status; - } - - /* Get a handle to the key for driver so that it can be altered in the */ - /* next step. */ - strcpy(keyPath, "SYSTEM\\CurrentControlSet\\Services\\"); - strcat(keyPath, szServiceName); - if ((status = RegOpenKeyEx(HKEY_LOCAL_MACHINE,keyPath,0,KEY_ALL_ACCESS,&key)) != ERROR_SUCCESS) { - /* A problem has occured. Delete the service so that it is not installed. */ - status = GetLastError(); - DeleteService(driverHandle); - CloseServiceHandle(driverHandle); - CloseServiceHandle(scmHandle); - return status; - } - - /* Delete the ImagePath value in the newly created key so that the */ - /* system looks for the driver in the normal location. */ - if ((status = RegDeleteValue(key, "ImagePath")) != ERROR_SUCCESS) { - /* A problem has occurred. Delete the service so that it is not */ - /* installed and will not try to start. */ - RegCloseKey(key); - DeleteService(driverHandle); - CloseServiceHandle(driverHandle); - CloseServiceHandle(scmHandle); - return status; - } - - /* Clean up and exit */ - RegCloseKey(key); - CloseServiceHandle(driverHandle); - CloseServiceHandle(scmHandle); - return ERROR_SUCCESS; -} - -/**************************************************************************** -PARAMETERS: -szServiceName - Name of the service to start - -RETURNS: -True on success, false on failure. - -REMARKS: -This function is used to start the specified service and make it active. -****************************************************************************/ -ulong PMAPI PM_startService( - const char *szServiceName) -{ - SC_HANDLE scmHandle; - SC_HANDLE driverHandle; - SERVICE_STATUS serviceStatus; - ulong status; - - /* Obtain a handle to the service control manager requesting all access */ - if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) - return GetLastError(); - - /* Open the service with the Service Control Manager. */ - if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) { - status = GetLastError(); - CloseServiceHandle(scmHandle); - return status; - } - - /* Start the service */ - if (!StartService(driverHandle,0,NULL)) { - status = GetLastError(); - CloseServiceHandle(driverHandle); - CloseServiceHandle(scmHandle); - return status; - } - - /* Query the service to make sure it is there */ - if (!QueryServiceStatus(driverHandle,&serviceStatus)) { - status = GetLastError(); - CloseServiceHandle(driverHandle); - CloseServiceHandle(scmHandle); - return status; - } - CloseServiceHandle(driverHandle); - CloseServiceHandle(scmHandle); - return ERROR_SUCCESS; -} - -/**************************************************************************** -PARAMETERS: -szServiceName - Name of the service to stop - -RETURNS: -True on success, false on failure. - -REMARKS: -This function is used to stop the specified service and disable it. -****************************************************************************/ -ulong PMAPI PM_stopService( - const char *szServiceName) -{ - SC_HANDLE scmHandle; - SC_HANDLE driverHandle; - SERVICE_STATUS serviceStatus; - ulong status; - - /* Obtain a handle to the service control manager requesting all access */ - if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) - return GetLastError(); - - /* Open the service with the Service Control Manager. */ - if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) { - status = GetLastError(); - CloseServiceHandle(scmHandle); - return status; - } - - /* Stop the service from running */ - if (!ControlService(driverHandle, SERVICE_CONTROL_STOP, &serviceStatus)) { - status = GetLastError(); - CloseServiceHandle(driverHandle); - CloseServiceHandle(scmHandle); - return status; - } - CloseServiceHandle(driverHandle); - CloseServiceHandle(scmHandle); - return ERROR_SUCCESS; -} - -/**************************************************************************** -PARAMETERS: -szServiceName - Name of the service to remove - -RETURNS: -True on success, false on failure. - -REMARKS: -This function is used to remove a service completely from the system. -****************************************************************************/ -ulong PMAPI PM_removeService( - const char *szServiceName) -{ - SC_HANDLE scmHandle; - SC_HANDLE driverHandle; - ulong status; - - /* Obtain a handle to the service control manager requesting all access */ - if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) - return GetLastError(); - - /* Open the service with the Service Control Manager. */ - if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) { - status = GetLastError(); - CloseServiceHandle(scmHandle); - return status; - } - - /* Remove the service */ - if (!DeleteService(driverHandle)) { - status = GetLastError(); - CloseServiceHandle(driverHandle); - CloseServiceHandle(scmHandle); - return status; - } - CloseServiceHandle(driverHandle); - CloseServiceHandle(scmHandle); - return ERROR_SUCCESS; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h deleted file mode 100644 index 0c59e90..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Win32 -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ - -#define WIN32_LEAN_AND_MEAN -#define STRICT -#include -#include -#include -#define NONAMELESSUNION -#include "pm/ddraw.h" - -/* Macros to save and restore the default control word. Windows 9x has - * some bugs in it such that calls to load any DLL's which load 16-bit - * DLL's cause the floating point control word to get trashed. We fix - * this by saving and restoring the control word across problematic - * calls. - */ - -#if defined(__INTEL__) -#define GET_DEFAULT_CW() \ -{ \ - if (_PM_cw_default == 0) \ - _PM_cw_default = _control87(0,0); \ -} -#define RESET_DEFAULT_CW() \ - _control87(_PM_cw_default,0xFFFFFFFF) -#else -#define GET_DEFAULT_CW() -#define RESET_DEFAULT_CW() -#endif - -/* Custom window messages */ - -#define WM_DO_SUSPEND_APP WM_USER -#define WM_PM_LEAVE_FULLSCREEN 0 -#define WM_PM_RESTORE_FULLSCREEN 1 - -/* Macro for disabling AutoPlay on a use system */ - -#define AUTOPLAY_DRIVE_CDROM 0x20 - -/*--------------------------- Global Variables ----------------------------*/ - -#ifdef __INTEL__ -extern uint _PM_cw_default; /* Default FPU control word */ -#endif -extern int _PM_deskX,_PM_deskY; /* Desktop dimensions */ -extern HWND _PM_hwndConsole; /* Window handle for console */ - -/*-------------------------- Internal Functions ---------------------------*/ - -void _EVT_pumpMessages(void); diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c b/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c deleted file mode 100644 index 1ffdbcc..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c +++ /dev/null @@ -1,1459 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Win32 -* -* Description: Implementation for the OS Portability Manager Library, which -* contains functions to implement OS specific services in a -* generic, cross platform API. Porting the OS Portability -* Manager library is the first step to porting any SciTech -* products to a new platform. -* -****************************************************************************/ - -#define WIN32_LEAN_AND_MEAN -#define STRICT -#include -#include -#include -#include -#include -#include -#include "pmapi.h" -#include "drvlib/os/os.h" -#include "pm_help.h" - -/*--------------------------- Global variables ----------------------------*/ - -ibool _PM_haveWinNT; /* True if we are running on NT */ -static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ -static void *VESABuf_ptr = NULL;/* Near pointer to VESABuf */ -static uint VESABuf_rseg; /* Real mode segment of VESABuf */ -static uint VESABuf_roff; /* Real mode offset of VESABuf */ -HANDLE _PM_hDevice = NULL; /* Handle to Win32 VxD */ -static ibool inited = false; /* Flags if we are initialised */ -static void (PMAPIP fatalErrorCleanup)(void) = NULL; - -static char *szMachineNameKey = "System\\CurrentControlSet\\control\\ComputerName\\ComputerName"; -static char *szMachineNameKeyNT = "System\\CurrentControlSet\\control\\ComputerName\\ActiveComputerName"; -static char *szMachineName = "ComputerName"; - -/*----------------------------- Implementation ----------------------------*/ - -/* Macro to check for a valid, loaded version of PMHELP. We check this - * on demand when we need these services rather than when PM_init() is - * called because if we are running on DirectDraw we don't need PMHELP.VXD. - */ - -#define CHECK_FOR_PMHELP() \ -{ \ - if (_PM_hDevice == INVALID_HANDLE_VALUE) \ - if (_PM_haveWinNT) \ - PM_fatalError("Unable to connect to PMHELP.SYS or SDDHELP.SYS!"); \ - else \ - PM_fatalError("Unable to connect to PMHELP.VXD or SDDHELP.VXD!"); \ -} - -/**************************************************************************** -REMARKS: -Initialise the PM library and connect to our helper device driver. If we -cannot connect to our helper device driver, we bail out with an error -message. Our Windows 9x VxD is dynamically loadable, so it can be loaded -after the system has started. -****************************************************************************/ -void PMAPI PM_init(void) -{ - DWORD inBuf[1]; /* Buffer to receive data from VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - char cntPath[PM_MAX_PATH]; - char *env; - - /* Create a file handle for the static VxD if possible, otherwise - * dynamically load the PMHELP helper VxD. Note that if an old version - * of SDD is loaded, we use the PMHELP VxD instead. - */ - if (!inited) { - /* Determine if we are running under Windows NT or not and - * set the global OS type variable. - */ - _PM_haveWinNT = false; - if ((GetVersion() & 0x80000000UL) == 0) - _PM_haveWinNT = true; - ___drv_os_type = (_PM_haveWinNT) ? _OS_WINNT : _OS_WIN95; - - /* Now try to connect to SDDHELP.VXD or SDDHELP.SYS */ - _PM_hDevice = CreateFile(SDDHELP_MODULE_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0); - if (_PM_hDevice != INVALID_HANDLE_VALUE) { - if (!DeviceIoControl(_PM_hDevice, PMHELP_GETVER32, NULL, 0, - outBuf, sizeof(outBuf), &count, NULL) || outBuf[0] < PMHELP_VERSION) { - /* Old version of SDDHELP loaded, so use PMHELP instead */ - CloseHandle(_PM_hDevice); - _PM_hDevice = INVALID_HANDLE_VALUE; - } - } - if (_PM_hDevice == INVALID_HANDLE_VALUE) { - /* First try to see if there is a currently loaded PMHELP driver. - * This is usually the case when we are running under Windows NT/2K. - */ - _PM_hDevice = CreateFile(PMHELP_MODULE_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0); - if (_PM_hDevice == INVALID_HANDLE_VALUE) { - /* The driver was not staticly loaded, so try creating a file handle - * to a dynamic version of the VxD if possible. Note that on WinNT/2K we - * cannot support dynamically loading the drivers. - */ - _PM_hDevice = CreateFile(PMHELP_VXD_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0); - } - } - if (_PM_hDevice != INVALID_HANDLE_VALUE) { - /* Call the driver to determine the version number */ - if (!DeviceIoControl(_PM_hDevice, PMHELP_GETVER32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL) || outBuf[0] < PMHELP_VERSION) { - if (_PM_haveWinNT) - PM_fatalError("Older version of PMHELP.SYS found!"); - else - PM_fatalError("Older version of PMHELP.VXD found!"); - } - - /* Now set the current path inside the VxD so it knows what the - * current directory is for loading Nucleus drivers. - */ - inBuf[0] = (ulong)PM_getCurrentPath(cntPath,sizeof(cntPath)); - if (!DeviceIoControl(_PM_hDevice, PMHELP_SETCNTPATH32, inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &count, NULL)) - PM_fatalError("Unable to set VxD current path!"); - - /* Now pass down the NUCLEUS_PATH environment variable to the device - * driver so it can use this value if it is found. - */ - if ((env = getenv("NUCLEUS_PATH")) != NULL) { - inBuf[0] = (ulong)env; - if (!DeviceIoControl(_PM_hDevice, PMHELP_SETNUCLEUSPATH32, inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &count, NULL)) - PM_fatalError("Unable to set VxD Nucleus path!"); - } - - /* Enable IOPL for ring-3 code by default if driver is present */ - if (_PM_haveWinNT) - PM_setIOPL(3); - } - - /* Indicate that we have been initialised */ - inited = true; - } -} - -/**************************************************************************** -REMARKS: -We do have BIOS access under Windows 9x, but not under Windows NT. -****************************************************************************/ -int PMAPI PM_setIOPL( - int iopl) -{ - DWORD inBuf[1]; /* Buffer to receive data from VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - static int cntIOPL = 0; - int oldIOPL = cntIOPL; - - /* Enable I/O by adjusting the I/O permissions map on Windows NT */ - if (_PM_haveWinNT) { - CHECK_FOR_PMHELP(); - if (iopl == 3) - DeviceIoControl(_PM_hDevice, PMHELP_ENABLERING3IOPL, inBuf, sizeof(inBuf),outBuf, sizeof(outBuf), &count, NULL); - else - DeviceIoControl(_PM_hDevice, PMHELP_DISABLERING3IOPL, inBuf, sizeof(inBuf),outBuf, sizeof(outBuf), &count, NULL); - cntIOPL = iopl; - return oldIOPL; - } - - /* We always have IOPL on Windows 9x */ - return 3; -} - -/**************************************************************************** -REMARKS: -We do have BIOS access under Windows 9x, but not under Windows NT. -****************************************************************************/ -ibool PMAPI PM_haveBIOSAccess(void) -{ - if (PM_getOSType() == _OS_WINNT) - return false; - else - return _PM_hDevice != INVALID_HANDLE_VALUE; -} - -/**************************************************************************** -REMARKS: -Return the operating system type identifier. -****************************************************************************/ -long PMAPI PM_getOSType(void) -{ - if ((GetVersion() & 0x80000000UL) == 0) - return ___drv_os_type = _OS_WINNT; - else - return ___drv_os_type = _OS_WIN95; -} - -/**************************************************************************** -REMARKS: -Return the runtime type identifier. -****************************************************************************/ -int PMAPI PM_getModeType(void) -{ - return PM_386; -} - -/**************************************************************************** -REMARKS: -Add a file directory separator to the end of the filename. -****************************************************************************/ -void PMAPI PM_backslash( - char *s) -{ - uint pos = strlen(s); - if (s[pos-1] != '\\') { - s[pos] = '\\'; - s[pos+1] = '\0'; - } -} - -/**************************************************************************** -REMARKS: -Add a user defined PM_fatalError cleanup function. -****************************************************************************/ -void PMAPI PM_setFatalErrorCleanup( - void (PMAPIP cleanup)(void)) -{ - fatalErrorCleanup = cleanup; -} - -/**************************************************************************** -REMARKS: -Report a fatal error condition and halt the program. -****************************************************************************/ -void PMAPI PM_fatalError( - const char *msg) -{ - if (fatalErrorCleanup) - fatalErrorCleanup(); - MessageBox(NULL,msg,"Fatal Error!", MB_ICONEXCLAMATION); - exit(1); -} - -/**************************************************************************** -REMARKS: -Allocate the real mode VESA transfer buffer for communicating with the BIOS. -****************************************************************************/ -void * PMAPI PM_getVESABuf( - uint *len, - uint *rseg, - uint *roff) -{ - DWORD outBuf[4]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - /* We require the helper VxD to be loaded staticly in order to support - * the VESA transfer buffer. We do not support dynamically allocating - * real mode memory buffers from Win32 programs (we need a 16-bit DLL - * for this, and Windows 9x becomes very unstable if you free the - * memory blocks out of order). - */ - if (!inited) - PM_init(); - if (!VESABuf_ptr) { - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_GETVESABUF32, NULL, 0, - outBuf, sizeof(outBuf), &count, NULL)) { - if (!outBuf[0]) - return NULL; - VESABuf_ptr = (void*)outBuf[0]; - VESABuf_len = outBuf[1]; - VESABuf_rseg = outBuf[2]; - VESABuf_roff = outBuf[3]; - } - } - *len = VESABuf_len; - *rseg = VESABuf_rseg; - *roff = VESABuf_roff; - return VESABuf_ptr; -} - -/**************************************************************************** -REMARKS: -Check if a key has been pressed. -****************************************************************************/ -int PMAPI PM_kbhit(void) -{ - /* Not used in Windows */ - return true; -} - -/**************************************************************************** -REMARKS: -Wait for and return the next keypress. -****************************************************************************/ -int PMAPI PM_getch(void) -{ - /* Not used in Windows */ - return 0xD; -} - -/**************************************************************************** -REMARKS: -Set the location of the OS console cursor. -****************************************************************************/ -void PM_setOSCursorLocation( - int x, - int y) -{ - /* Nothing to do for Windows */ - (void)x; - (void)y; -} - -/**************************************************************************** -REMARKS: -Set the width of the OS console. -****************************************************************************/ -void PM_setOSScreenWidth( - int width, - int height) -{ - /* Nothing to do for Windows */ - (void)width; - (void)height; -} - -/**************************************************************************** -REMARKS: -Set the real time clock handler (used for software stereo modes). -****************************************************************************/ -ibool PMAPI PM_setRealTimeClockHandler( - PM_intHandler ih, - int frequency) -{ - /* We do not support this from Win32 programs. Rather the VxD handles - * this stuff it will take care of hooking the stereo flip functions at - * the VxD level. - */ - (void)ih; - (void)frequency; - return false; -} - -/**************************************************************************** -REMARKS: -Set the real time clock frequency (for stereo modes). -****************************************************************************/ -void PMAPI PM_setRealTimeClockFrequency( - int frequency) -{ - /* Not supported under Win32 */ - (void)frequency; -} - -/**************************************************************************** -REMARKS: -Restore the original real time clock handler. -****************************************************************************/ -void PMAPI PM_restoreRealTimeClockHandler(void) -{ - /* Not supported under Win32 */ -} - -/**************************************************************************** -REMARKS: -Return the current operating system path or working directory. -****************************************************************************/ -char * PMAPI PM_getCurrentPath( - char *path, - int maxLen) -{ - return getcwd(path,maxLen); -} - -/**************************************************************************** -REMARKS: -Query a string from the registry (extended version). -****************************************************************************/ -static ibool REG_queryStringEx( - HKEY hKey, - const char *szValue, - char *value, - ulong size) -{ - DWORD type; - - if (RegQueryValueEx(hKey,(PCHAR)szValue,(PDWORD)NULL,(PDWORD)&type,(LPBYTE)value,(PDWORD)&size) == ERROR_SUCCESS) - return true; - return false; -} - -/**************************************************************************** -REMARKS: -Query a string from the registry. -****************************************************************************/ -static ibool REG_queryString( - const char *szKey, - const char *szValue, - char *value, - DWORD size) -{ - HKEY hKey; - ibool status = false; - - memset(value,0,sizeof(value)); - if (RegOpenKey(HKEY_LOCAL_MACHINE,szKey,&hKey) == ERROR_SUCCESS) { - status = REG_queryStringEx(hKey,szValue,value,size); - RegCloseKey(hKey); - } - return status; -} - -/**************************************************************************** -REMARKS: -Return the drive letter for the boot drive. -****************************************************************************/ -char PMAPI PM_getBootDrive(void) -{ - static char path[256]; - GetSystemDirectory(path,sizeof(path)); - return path[0]; -} - -/**************************************************************************** -REMARKS: -Return the path to the VBE/AF driver files. -****************************************************************************/ -const char * PMAPI PM_getVBEAFPath(void) -{ - return "c:\\"; -} - -/**************************************************************************** -REMARKS: -Return the path to the Nucleus driver files. -****************************************************************************/ -const char * PMAPI PM_getNucleusPath(void) -{ - static char path[256]; - char *env; - - if ((env = getenv("NUCLEUS_PATH")) != NULL) - return env; - GetSystemDirectory(path,sizeof(path)); - strcat(path,"\\nucleus"); - return path; -} - -/**************************************************************************** -REMARKS: -Return the path to the Nucleus configuration files. -****************************************************************************/ -const char * PMAPI PM_getNucleusConfigPath(void) -{ - static char path[256]; - strcpy(path,PM_getNucleusPath()); - PM_backslash(path); - strcat(path,"config"); - return path; -} - -/**************************************************************************** -REMARKS: -Return a unique identifier for the machine if possible. -****************************************************************************/ -const char * PMAPI PM_getUniqueID(void) -{ - return PM_getMachineName(); -} - -/**************************************************************************** -REMARKS: -Get the name of the machine on the network. -****************************************************************************/ -const char * PMAPI PM_getMachineName(void) -{ - static char name[256]; - - if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name))) - return name; - if (REG_queryString(szMachineNameKeyNT,szMachineName,name,sizeof(name))) - return name; - return "Unknown"; -} - -/**************************************************************************** -REMARKS: -Return a pointer to the real mode BIOS data area. -****************************************************************************/ -void * PMAPI PM_getBIOSPointer(void) -{ - if (_PM_haveWinNT) { - /* On Windows NT we have to map it physically directly */ - return PM_mapPhysicalAddr(0x400, 0x1000, true); - } - else { - /* For Windows 9x we can access this memory directly */ - return (void*)0x400; - } -} - -/**************************************************************************** -REMARKS: -Return a pointer to 0xA0000 physical VGA graphics framebuffer. -****************************************************************************/ -void * PMAPI PM_getA0000Pointer(void) -{ - if (_PM_haveWinNT) { - /* On Windows NT we have to map it physically directly */ - return PM_mapPhysicalAddr(0xA0000, 0x0FFFF, false); - } - else { - /* Always use the 0xA0000 linear address so that we will use - * whatever page table mappings are set up for us (ie: for virtual - * bank switching. - */ - return (void*)0xA0000; - } -} - -/**************************************************************************** -REMARKS: -Map a physical address to a linear address in the callers process. -****************************************************************************/ -void * PMAPI PM_mapPhysicalAddr( - ulong base, - ulong limit, - ibool isCached) -{ - DWORD inBuf[3]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = base; - inBuf[1] = limit; - inBuf[2] = isCached; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_MAPPHYS32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return (void*)outBuf[0]; - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a physical address mapping allocated by PM_mapPhysicalAddr. -****************************************************************************/ -void PMAPI PM_freePhysicalAddr( - void *ptr, - ulong limit) -{ - /* We never free the mappings under Win32 (the VxD tracks them and - * reissues the same mappings until the system is rebooted). - */ - (void)ptr; - (void)limit; -} - -/**************************************************************************** -REMARKS: -Find the physical address of a linear memory address in current process. -****************************************************************************/ -ulong PMAPI PM_getPhysicalAddr( - void *p) -{ - DWORD inBuf[1]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = (ulong)p; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_GETPHYSICALADDR32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return outBuf[0]; - return 0xFFFFFFFFUL; -} - -/**************************************************************************** -REMARKS: -Find the physical address of a linear memory address in current process. -****************************************************************************/ -ibool PMAPI PM_getPhysicalAddrRange( - void *p, - ulong length, - ulong *physAddress) -{ - DWORD inBuf[3]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = (ulong)p; - inBuf[1] = (ulong)length; - inBuf[2] = (ulong)physAddress; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_GETPHYSICALADDRRANGE32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return outBuf[0]; - return false; -} - -/**************************************************************************** -REMARKS: -Sleep for the specified number of milliseconds. -****************************************************************************/ -void PMAPI PM_sleep( - ulong milliseconds) -{ - Sleep(milliseconds); -} - -/**************************************************************************** -REMARKS: -Return the base I/O port for the specified COM port. -****************************************************************************/ -int PMAPI PM_getCOMPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3F8; - case 1: return 0x2F8; - case 2: return 0x3E8; - case 3: return 0x2E8; - } - return 0; -} - -/**************************************************************************** -REMARKS: -Return the base I/O port for the specified LPT port. -****************************************************************************/ -int PMAPI PM_getLPTPort(int port) -{ - /* TODO: Re-code this to determine real values using the Plug and Play */ - /* manager for the OS. */ - switch (port) { - case 0: return 0x3BC; - case 1: return 0x378; - case 2: return 0x278; - } - return 0; -} - -/**************************************************************************** -REMARKS: -Allocate a block of shared memory. For Win9x we allocate shared memory -as locked, global memory that is accessible from any memory context -(including interrupt time context), which allows us to load our important -data structure and code such that we can access it directly from a ring -0 interrupt context. -****************************************************************************/ -void * PMAPI PM_mallocShared( - long size) -{ - DWORD inBuf[1]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - inBuf[0] = size; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_MALLOCSHARED32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return (void*)outBuf[0]; - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a block of shared memory. -****************************************************************************/ -void PMAPI PM_freeShared( - void *ptr) -{ - DWORD inBuf[1]; /* Buffer to send data to VxD */ - - inBuf[0] = (ulong)ptr; - CHECK_FOR_PMHELP(); - DeviceIoControl(_PM_hDevice, PMHELP_FREESHARED32, inBuf, sizeof(inBuf), NULL, 0, NULL, NULL); -} - -/**************************************************************************** -REMARKS: -Map a linear memory address to the calling process address space. The -address will have been allocated in another process using the -PM_mapPhysicalAddr function. -****************************************************************************/ -void * PMAPI PM_mapToProcess( - void *base, - ulong limit) -{ - (void)base; - (void)limit; - return base; -} - -/**************************************************************************** -REMARKS: -Map a real mode pointer to a protected mode pointer. -****************************************************************************/ -void * PMAPI PM_mapRealPointer( - uint r_seg, - uint r_off) -{ - return (void*)(MK_PHYS(r_seg,r_off)); -} - -/**************************************************************************** -REMARKS: -Allocate a block of real mode memory -****************************************************************************/ -void * PMAPI PM_allocRealSeg( - uint size, - uint *r_seg, - uint *r_off) -{ - /* We do not support dynamically allocating real mode memory buffers - * from Win32 programs (we need a 16-bit DLL for this, and Windows - * 9x becomes very unstable if you free the memory blocks out of order). - */ - (void)size; - (void)r_seg; - (void)r_off; - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a block of real mode memory. -****************************************************************************/ -void PMAPI PM_freeRealSeg( - void *mem) -{ - /* Not supported in Windows */ - (void)mem; -} - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt (parameters in DPMI compatible structure) -****************************************************************************/ -void PMAPI DPMI_int86( - int intno, - DPMI_regs *regs) -{ - DWORD inBuf[2]; /* Buffer to send data to VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = intno; - inBuf[1] = (ulong)regs; - CHECK_FOR_PMHELP(); - DeviceIoControl(_PM_hDevice, PMHELP_DPMIINT8632, inBuf, sizeof(inBuf), - NULL, 0, &count, NULL); -} - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt. -****************************************************************************/ -int PMAPI PM_int86( - int intno, - RMREGS *in, - RMREGS *out) -{ - DWORD inBuf[3]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = intno; - inBuf[1] = (ulong)in; - inBuf[2] = (ulong)out; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_INT8632, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return outBuf[0]; - return 0; -} - -/**************************************************************************** -REMARKS: -Issue a real mode interrupt. -****************************************************************************/ -int PMAPI PM_int86x( - int intno, - RMREGS *in, - RMREGS *out, - RMSREGS *sregs) -{ - DWORD inBuf[4]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = intno; - inBuf[1] = (ulong)in; - inBuf[2] = (ulong)out; - inBuf[3] = (ulong)sregs; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_INT86X32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return outBuf[0]; - return 0; -} - -/**************************************************************************** -REMARKS: -Call a real mode far function. -****************************************************************************/ -void PMAPI PM_callRealMode( - uint seg, - uint off, - RMREGS *in, - RMSREGS *sregs) -{ - DWORD inBuf[4]; /* Buffer to send data to VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = seg; - inBuf[1] = off; - inBuf[2] = (ulong)in; - inBuf[3] = (ulong)sregs; - CHECK_FOR_PMHELP(); - DeviceIoControl(_PM_hDevice, PMHELP_CALLREALMODE32, inBuf, sizeof(inBuf), - NULL, 0, &count, NULL); -} - -/**************************************************************************** -REMARKS: -Return the amount of available memory. -****************************************************************************/ -void PMAPI PM_availableMemory( - ulong *physical, - ulong *total) -{ - /* We don't support this under Win32 at the moment */ - *physical = *total = 0; -} - -/**************************************************************************** -REMARKS: -Allocate a block of locked, physical memory for DMA operations. -****************************************************************************/ -void * PMAPI PM_allocLockedMem( - uint size, - ulong *physAddr, - ibool contiguous, - ibool below16M) -{ - DWORD inBuf[4]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = size; - inBuf[1] = (ulong)physAddr; - inBuf[2] = (ulong)contiguous; - inBuf[3] = (ulong)below16M; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_ALLOCLOCKED32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return (void*)outBuf[0]; - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a block of locked physical memory. -****************************************************************************/ -void PMAPI PM_freeLockedMem( - void *p, - uint size, - ibool contiguous) -{ - DWORD inBuf[3]; /* Buffer to send data to VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = (ulong)p; - inBuf[1] = size; - inBuf[2] = contiguous; - CHECK_FOR_PMHELP(); - DeviceIoControl(_PM_hDevice, PMHELP_FREELOCKED32, inBuf, sizeof(inBuf), - NULL, 0, &count, NULL); -} - -/**************************************************************************** -REMARKS: -Allocates a page aligned and page sized block of memory -****************************************************************************/ -void * PMAPI PM_allocPage( - ibool locked) -{ - DWORD inBuf[2]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = locked; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_ALLOCPAGE32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return (void*)outBuf[0]; - return NULL; -} - -/**************************************************************************** -REMARKS: -Free a page aligned and page sized block of memory -****************************************************************************/ -void PMAPI PM_freePage( - void *p) -{ - DWORD inBuf[1]; /* Buffer to send data to VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = (ulong)p; - CHECK_FOR_PMHELP(); - DeviceIoControl(_PM_hDevice, PMHELP_FREEPAGE32, inBuf, sizeof(inBuf), - NULL, 0, &count, NULL); -} - -/**************************************************************************** -REMARKS: -Lock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - DWORD inBuf[2]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - inBuf[0] = (ulong)p; - inBuf[1] = len; - inBuf[2] = (ulong)lh; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_LOCKDATAPAGES32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return outBuf[0]; - return 0; -} - -/**************************************************************************** -REMARKS: -Unlock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) -{ - DWORD inBuf[2]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - inBuf[0] = (ulong)p; - inBuf[1] = len; - inBuf[2] = (ulong)lh; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_UNLOCKDATAPAGES32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return outBuf[0]; - return 0; -} - -/**************************************************************************** -REMARKS: -Lock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - DWORD inBuf[2]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - inBuf[0] = (ulong)p; - inBuf[1] = len; - inBuf[2] = (ulong)lh; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_LOCKCODEPAGES32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return outBuf[0]; - return 0; -} - -/**************************************************************************** -REMARKS: -Unlock linear memory so it won't be paged. -****************************************************************************/ -int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) -{ - DWORD inBuf[2]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - inBuf[0] = (ulong)p; - inBuf[1] = len; - inBuf[2] = (ulong)lh; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_UNLOCKCODEPAGES32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return outBuf[0]; - return 0; -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display banks. -****************************************************************************/ -void PMAPI PM_setBankA( - int bank) -{ - RMREGS regs; - regs.x.ax = 0x4F05; - regs.x.bx = 0x0000; - regs.x.dx = bank; - PM_int86(0x10,®s,®s); -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display banks. -****************************************************************************/ -void PMAPI PM_setBankAB( - int bank) -{ - RMREGS regs; - regs.x.ax = 0x4F05; - regs.x.bx = 0x0000; - regs.x.dx = bank; - PM_int86(0x10,®s,®s); - regs.x.ax = 0x4F05; - regs.x.bx = 0x0001; - regs.x.dx = bank; - PM_int86(0x10,®s,®s); -} - -/**************************************************************************** -REMARKS: -Call the VBE/Core software interrupt to change display start address. -****************************************************************************/ -void PMAPI PM_setCRTStart( - int x, - int y, - int waitVRT) -{ - RMREGS regs; - regs.x.ax = 0x4F07; - regs.x.bx = waitVRT; - regs.x.cx = x; - regs.x.dx = y; - PM_int86(0x10,®s,®s); -} - -/**************************************************************************** -REMARKS: -Enable write combining for the memory region. -****************************************************************************/ -ibool PMAPI PM_enableWriteCombine( - ulong base, - ulong length, - uint type) -{ - DWORD inBuf[3]; /* Buffer to send data to VxD */ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - if (!inited) - PM_init(); - inBuf[0] = base; - inBuf[1] = length; - inBuf[2] = type; - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_ENABLELFBCOMB32, inBuf, sizeof(inBuf), - outBuf, sizeof(outBuf), &count, NULL)) - return outBuf[0]; - return false; -} - -/**************************************************************************** -REMARKS: -Get the page directory base register value -****************************************************************************/ -ulong PMAPI _PM_getPDB(void) -{ - DWORD outBuf[1]; /* Buffer to receive data from VxD */ - DWORD count; /* Count of bytes returned from VxD */ - - CHECK_FOR_PMHELP(); - if (DeviceIoControl(_PM_hDevice, PMHELP_GETPDB32, NULL, 0, - outBuf, sizeof(outBuf), &count, NULL)) - return outBuf[0]; - return 0; -} - -/**************************************************************************** -REMARKS: -Flush the translation lookaside buffer. -****************************************************************************/ -void PMAPI PM_flushTLB(void) -{ - CHECK_FOR_PMHELP(); - DeviceIoControl(_PM_hDevice, PMHELP_FLUSHTLB32, NULL, 0, NULL, 0, NULL, NULL); -} - -/**************************************************************************** -REMARKS: -Execute the POST on the secondary BIOS for a controller. -****************************************************************************/ -ibool PMAPI PM_doBIOSPOST( - ushort axVal, - ulong BIOSPhysAddr, - void *mappedBIOS, - ulong BIOSLen) -{ - /* This is never done by Win32 programs, but rather done by the VxD - * when the system boots. - */ - (void)axVal; - (void)BIOSPhysAddr; - (void)mappedBIOS; - (void)BIOSLen; - return false; -} - -/**************************************************************************** -REMARKS: -Load an OS specific shared library or DLL. If the OS does not support -shared libraries, simply return NULL. -****************************************************************************/ -PM_MODULE PMAPI PM_loadLibrary( - const char *szDLLName) -{ - return (PM_MODULE)LoadLibrary(szDLLName); -} - -/**************************************************************************** -REMARKS: -Get the address of a named procedure from a shared library. -****************************************************************************/ -void * PMAPI PM_getProcAddress( - PM_MODULE hModule, - const char *szProcName) -{ - return (void*)GetProcAddress((HINSTANCE)hModule,szProcName); -} - -/**************************************************************************** -REMARKS: -Unload a shared library. -****************************************************************************/ -void PMAPI PM_freeLibrary( - PM_MODULE hModule) -{ - FreeLibrary((HINSTANCE)hModule); -} - -/**************************************************************************** -REMARKS: -Internal function to convert the find data to the generic interface. -****************************************************************************/ -static void convertFindData( - PM_findData *findData, - WIN32_FIND_DATA *blk) -{ - ulong dwSize = findData->dwSize; - - memset(findData,0,findData->dwSize); - findData->dwSize = dwSize; - if (blk->dwFileAttributes & FILE_ATTRIBUTE_READONLY) - findData->attrib |= PM_FILE_READONLY; - if (blk->dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) - findData->attrib |= PM_FILE_DIRECTORY; - if (blk->dwFileAttributes & FILE_ATTRIBUTE_ARCHIVE) - findData->attrib |= PM_FILE_ARCHIVE; - if (blk->dwFileAttributes & FILE_ATTRIBUTE_HIDDEN) - findData->attrib |= PM_FILE_HIDDEN; - if (blk->dwFileAttributes & FILE_ATTRIBUTE_SYSTEM) - findData->attrib |= PM_FILE_SYSTEM; - findData->sizeLo = blk->nFileSizeLow; - findData->sizeHi = blk->nFileSizeHigh; - strncpy(findData->name,blk->cFileName,PM_MAX_PATH); - findData->name[PM_MAX_PATH-1] = 0; -} - -/**************************************************************************** -REMARKS: -Function to find the first file matching a search criteria in a directory. -****************************************************************************/ -void *PMAPI PM_findFirstFile( - const char *filename, - PM_findData *findData) -{ - WIN32_FIND_DATA blk; - HANDLE hfile; - - if ((hfile = FindFirstFile(filename,&blk)) != INVALID_HANDLE_VALUE) { - convertFindData(findData,&blk); - return (void*)hfile; - } - return PM_FILE_INVALID; -} - -/**************************************************************************** -REMARKS: -Function to find the next file matching a search criteria in a directory. -****************************************************************************/ -ibool PMAPI PM_findNextFile( - void *handle, - PM_findData *findData) -{ - WIN32_FIND_DATA blk; - - if (FindNextFile((HANDLE)handle,&blk)) { - convertFindData(findData,&blk); - return true; - } - return false; -} - -/**************************************************************************** -REMARKS: -Function to close the find process -****************************************************************************/ -void PMAPI PM_findClose( - void *handle) -{ - FindClose((HANDLE)handle); -} - -/**************************************************************************** -REMARKS: -Function to determine if a drive is a valid drive or not. Under Unix this -function will return false for anything except a value of 3 (considered -the root drive, and equivalent to C: for non-Unix systems). The drive -numbering is: - - 1 - Drive A: - 2 - Drive B: - 3 - Drive C: - etc - -****************************************************************************/ -ibool PMAPI PM_driveValid( - char drive) -{ - char buf[5]; - int type; - - sprintf(buf,"%c:\\", drive); - return ((type = GetDriveType(buf)) != 0 && type != 1); -} - -/**************************************************************************** -REMARKS: -Function to get the current working directory for the specififed drive. -Under Unix this will always return the current working directory regardless -of what the value of 'drive' is. -****************************************************************************/ -void PMAPI PM_getdcwd( - int drive, - char *dir, - int len) -{ - /* NT stores the current directory for drive N in the magic environment */ - /* variable =N: so we simply look for that environment variable. */ - char envname[4]; - - envname[0] = '='; - envname[1] = drive - 1 + 'A'; - envname[2] = ':'; - envname[3] = '\0'; - if (GetEnvironmentVariable(envname,dir,len) == 0) { - /* The current directory or the drive has not been set yet, so */ - /* simply set it to the root. */ - dir[0] = envname[1]; - dir[1] = ':'; - dir[2] = '\\'; - dir[3] = '\0'; - SetEnvironmentVariable(envname,dir); - } -} - -/**************************************************************************** -REMARKS: -Function to change the file attributes for a specific file. -****************************************************************************/ -void PMAPI PM_setFileAttr( - const char *filename, - uint attrib) -{ - DWORD attr = 0; - - if (attrib & PM_FILE_READONLY) - attr |= FILE_ATTRIBUTE_READONLY; - if (attrib & PM_FILE_ARCHIVE) - attr |= FILE_ATTRIBUTE_ARCHIVE; - if (attrib & PM_FILE_HIDDEN) - attr |= FILE_ATTRIBUTE_HIDDEN; - if (attrib & PM_FILE_SYSTEM) - attr |= FILE_ATTRIBUTE_SYSTEM; - SetFileAttributes((LPSTR)filename, attr); -} - -/**************************************************************************** -REMARKS: -Function to get the file attributes for a specific file. -****************************************************************************/ -uint PMAPI PM_getFileAttr( - const char *filename) -{ - DWORD attr = GetFileAttributes(filename); - uint attrib = 0; - - if (attr & FILE_ATTRIBUTE_READONLY) - attrib |= PM_FILE_READONLY; - if (attr & FILE_ATTRIBUTE_ARCHIVE) - attrib |= PM_FILE_ARCHIVE; - if (attr & FILE_ATTRIBUTE_HIDDEN) - attrib |= PM_FILE_HIDDEN; - if (attr & FILE_ATTRIBUTE_SYSTEM) - attrib |= PM_FILE_SYSTEM; - return attrib; -} - -/**************************************************************************** -REMARKS: -Function to create a directory. -****************************************************************************/ -ibool PMAPI PM_mkdir( - const char *filename) -{ - return CreateDirectory(filename,NULL); -} - -/**************************************************************************** -REMARKS: -Function to remove a directory. -****************************************************************************/ -ibool PMAPI PM_rmdir( - const char *filename) -{ - return RemoveDirectory(filename); -} - -/**************************************************************************** -REMARKS: -Function to get the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_getFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - HFILE f; - OFSTRUCT of; - FILETIME utcTime,localTime; - SYSTEMTIME sysTime; - ibool status = false; - - of.cBytes = sizeof(of); - if ((f = OpenFile(filename,&of,OF_READ)) == HFILE_ERROR) - return false; - if (!GetFileTime((HANDLE)f,NULL,NULL,&utcTime)) - goto Exit; - if (!gmTime) { - if (!FileTimeToLocalFileTime(&utcTime,&localTime)) - goto Exit; - } - else - localTime = utcTime; - if (!FileTimeToSystemTime(&localTime,&sysTime)) - goto Exit; - time->year = sysTime.wYear; - time->mon = sysTime.wMonth-1; - time->day = sysTime.wYear; - time->hour = sysTime.wHour; - time->min = sysTime.wMinute; - time->sec = sysTime.wSecond; - status = true; - -Exit: - CloseHandle((HANDLE)f); - return status; -} - -/**************************************************************************** -REMARKS: -Function to set the file time and date for a specific file. -****************************************************************************/ -ibool PMAPI PM_setFileTime( - const char *filename, - ibool gmTime, - PM_time *time) -{ - HFILE f; - OFSTRUCT of; - FILETIME utcTime,localTime; - SYSTEMTIME sysTime; - ibool status = false; - - of.cBytes = sizeof(of); - if ((f = OpenFile(filename,&of,OF_WRITE)) == HFILE_ERROR) - return false; - sysTime.wYear = time->year; - sysTime.wMonth = time->mon+1; - sysTime.wYear = time->day; - sysTime.wHour = time->hour; - sysTime.wMinute = time->min; - sysTime.wSecond = time->sec; - if (!SystemTimeToFileTime(&sysTime,&localTime)) - goto Exit; - if (!gmTime) { - if (!LocalFileTimeToFileTime(&localTime,&utcTime)) - goto Exit; - } - else - utcTime = localTime; - if (!SetFileTime((HANDLE)f,NULL,NULL,&utcTime)) - goto Exit; - status = true; - -Exit: - CloseHandle((HANDLE)f); - return status; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c deleted file mode 100644 index 70491cd..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Dummy module; no virtual framebuffer for this OS -* -****************************************************************************/ - -#include "pmapi.h" - -ibool PMAPI VF_available(void) -{ - return false; -} - -void * PMAPI VF_init( - ulong baseAddr, - int bankSize, - int codeLen, - void *bankFunc) -{ - (void)baseAddr; - (void)bankSize; - (void)codeLen; - (void)bankFunc; - return NULL; -} - -void PMAPI VF_exit(void) -{ -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c deleted file mode 100644 index 5a901a4..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************** -* -* Ultra Long Period Timer -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Win32 -* -* Description: OS specific implementation for the Zen Timer functions. -* -****************************************************************************/ - -/*---------------------------- Global variables ---------------------------*/ - -static CPU_largeInteger countFreq; -static ibool havePerformanceCounter; -static ulong start,finish; - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Initialise the Zen Timer module internals. -****************************************************************************/ -void __ZTimerInit(void) -{ -#ifdef NO_ASSEMBLER - havePerformanceCounter = false; -#else - havePerformanceCounter = QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq); -#endif -} - -/**************************************************************************** -REMARKS: -Start the Zen Timer counting. -****************************************************************************/ -static void __LZTimerOn( - LZTimerObject *tm) -{ - if (havePerformanceCounter) - QueryPerformanceCounter((LARGE_INTEGER*)&tm->start); - else - tm->start.low = timeGetTime(); -} - -/**************************************************************************** -REMARKS: -Compute the lap time since the timer was started. -****************************************************************************/ -static ulong __LZTimerLap( - LZTimerObject *tm) -{ - CPU_largeInteger tmLap,tmCount; - - if (havePerformanceCounter) { - QueryPerformanceCounter((LARGE_INTEGER*)&tmLap); - _CPU_diffTime64(&tm->start,&tmLap,&tmCount); - return _CPU_calcMicroSec(&tmCount,countFreq.low); - } - else { - tmLap.low = timeGetTime(); - return (tmLap.low - tm->start.low) * 1000L; - } -} - -/**************************************************************************** -REMARKS: -Stop the Zen Timer counting. -****************************************************************************/ -static void __LZTimerOff( - LZTimerObject *tm) -{ - if (havePerformanceCounter) - QueryPerformanceCounter((LARGE_INTEGER*)&tm->end); - else - tm->end.low = timeGetTime(); -} - -/**************************************************************************** -REMARKS: -Compute the elapsed time in microseconds between start and end timings. -****************************************************************************/ -static ulong __LZTimerCount( - LZTimerObject *tm) -{ - CPU_largeInteger tmCount; - - if (havePerformanceCounter) { - _CPU_diffTime64(&tm->start,&tm->end,&tmCount); - return _CPU_calcMicroSec(&tmCount,countFreq.low); - } - else - return (tm->end.low - tm->start.low) * 1000L; -} - -/**************************************************************************** -REMARKS: -Define the resolution of the long period timer as microseconds per timer tick. -****************************************************************************/ -#define ULZTIMER_RESOLUTION 1000 - -/**************************************************************************** -REMARKS: -Read the Long Period timer from the OS -****************************************************************************/ -static ulong __ULZReadTime(void) -{ return timeGetTime(); } - -/**************************************************************************** -REMARKS: -Compute the elapsed time from the BIOS timer tick. Note that we check to see -whether a midnight boundary has passed, and if so adjust the finish time to -account for this. We cannot detect if more that one midnight boundary has -passed, so if this happens we will be generating erronous results. -****************************************************************************/ -ulong __ULZElapsedTime(ulong start,ulong finish) -{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/x11/event.c b/board/MAI/bios_emulator/scitech/src/pm/x11/event.c deleted file mode 100644 index b34bfac..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/x11/event.c +++ /dev/null @@ -1,307 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Unix / X11 -* -* Description: X11 event queue implementation for the MGL. -* This can be used both for windowed and fullscreen (DGA) modes. -* -****************************************************************************/ - -/*---------------------------- Global Variables ---------------------------*/ - -static ushort keyUpMsg[256] = {0};/* Table of key up messages */ -static int rangeX,rangeY; /* Range of mouse coordinates */ - -static Display *_EVT_dpy; -static Window _EVT_win; - -typedef struct { - int keycode; - int scancode; -} xkeymap; - -xkeymap xkeymaps[] = { - { 9, KB_esc}, - {24, KB_Q}, - {25, KB_W}, - {26, KB_E}, - {27, KB_R}, - {28, KB_T}, - {29, KB_Y}, - {30, KB_U}, - {31, KB_I}, - {32, KB_O}, - {33, KB_P}, -}; - -/*---------------------------- Implementation -----------------------------*/ - -/* These are not used under non-DOS systems */ -#define _EVT_disableInt() 1 -#define _EVT_restoreInt(flags) - -/**************************************************************************** -PARAMETERS: -scanCode - Scan code to test - -REMARKS: -This macro determines if a specified key is currently down at the -time that the call is made. -****************************************************************************/ -#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) - -/**************************************************************************** -REMARKS: -This function is used to return the number of ticks since system -startup in milliseconds. This should be the same value that is placed into -the time stamp fields of events, and is used to implement auto mouse down -events. -****************************************************************************/ -ulong _EVT_getTicks(void) -{ - static unsigned starttime = 0; - struct timeval t; - - gettimeofday(&t, NULL); - if (starttime == 0) - starttime = t.tv_sec * 1000 + (t.tv_usec/1000); - return ((t.tv_sec * 1000 + (t.tv_usec/1000)) - starttime); -} - -static int getScancode(int keycode) -{ - return keycode-8; -} - -/**************************************************************************** -REMARKS: -Pumps all messages in the application message queue into our event queue. -****************************************************************************/ -#ifdef X11_CORE -static void _EVT_pumpX11Messages(void) -#else -static void _EVT_pumpMessages(void) -#endif -{ - /* TODO: The purpose of this function is to read all keyboard and mouse */ - /* events from the OS specific event queue, translate them and post */ - /* them into the SciTech event queue. */ - event_t evt; - XEvent ev; - static int old_mx = 0, old_my = 0, buts = 0, c; - char buf[2]; - - while (XPending(_EVT_dpy) && XNextEvent(_EVT_dpy,&ev)) { - evt.when = _MGL_getTicks(); - - switch(ev.type){ - case KeyPress: - c = getScancode(ev.xkey.keycode); - evt.what = EVT_KEYDOWN; - evt.message = c << 8; - XLookupString(&ev.xkey, buf, 2, NULL, NULL); - evt.message |= buf[0]; - break; - case KeyRelease: - c = getScancode(ev.xkey.keycode); - evt.what = EVT_KEYUP; - evt.message = keyUpMsg[c]; - if(count < EVENTQSIZE) - addEvent(&evt); - keyUpMsg[c] = 0; - repeatKey[c] = 0; - break; - case ButtonPress: - evt.what = EVT_MOUSEDOWN; - if(ev.xbutton.button == 1){ - buts |= EVT_LEFTBUT; - evt.message = EVT_LEFTBMASK; - }else if(ev.xbutton.button == 2){ - buts |= EVT_MIDDLEBUT; - evt.message = EVT_MIDDLEBMASK; - }else if(ev.xbutton.button == 3){ - buts |= EVT_RIGHTBUT; - evt.message = EVT_RIGHTBMASK; - } - evt.modifiers = modifiers | buts; - - break; - case ButtonRelease: - evt.what = EVT_MOUSEUP; - if(ev.xbutton.button == 1){ - buts &= ~EVT_LEFTBUT; - evt.message = EVT_LEFTBMASK; - }else if(ev.xbutton.button == 2){ - buts &= ~EVT_MIDDLEBUT; - evt.message = EVT_MIDDLEBMASK; - }else if(ev.xbutton.button == 3){ - buts &= ~EVT_RIGHTBUT; - evt.message = EVT_RIGHTBMASK; - } - evt.modifiers = modifiers | buts; - - break; - case MotionNotify: - evt.what = EVT_MOUSEMOVE; - evt.where_x = ev.xmotion.x; - evt.where_y = ev.xmotion.y; - evt.relative_x = evt.where_x - old_mx; - evt.relative_y = evt.where_y - old_my; - old_mx = evt.where_x; - old_my = evt.where_y; - break; - } - if (count < EVENTQSIZE) - addEvent(&evt); - } - -} - -/**************************************************************************** -REMARKS: -This macro/function is used to converts the scan codes reported by the -keyboard to our event libraries normalised format. We only have one scan -code for the 'A' key, and use shift modifiers to determine if it is a -Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, -but the OS gives us 'cooked' scan codes, we have to translate them back -to the raw format. -****************************************************************************/ -#define _EVT_maskKeyCode(evt) - -/**************************************************************************** -REMARKS: -Safely abort the event module upon catching a fatal error. -****************************************************************************/ -void _EVT_abort() -{ - EVT_exit(); - PM_fatalError("Unhandled exception!"); -} - -/**************************************************************************** -PARAMETERS: -mouseMove - Callback function to call wheneve the mouse needs to be moved - -REMARKS: -Initiliase the event handling module. Here we install our mouse handling ISR -to be called whenever any button's are pressed or released. We also build -the free list of events in the event queue. - -We use handler number 2 of the mouse libraries interrupt handlers for our -event handling routines. -****************************************************************************/ -#ifdef X11_CORE -void EVTAPI EVT_initX11( -#else -void EVTAPI EVT_init( -#endif - _EVT_mouseMoveHandler mouseMove) -{ - int result, i,j,k; - XDeviceInfoPtr list,slist; - - /* Initialise the event queue */ - _mouseMove = mouseMove; - initEventQueue(); - memset(keyUpMsg,0,sizeof(keyUpMsg)); - - - /* query server for input extensions */ - result =XQueryExtension(_EVT_dpy,"XInputExtension",&i,&j,&k); - if(!result) { - fprintf(stderr,"Your server doesn't support XInput Extensions\n"); - fprintf(stderr,"X11 Joystick disabled\n"); - } - list = XListInputDevices(_EVT_dpy,&result); - if (!list) { - fprintf(stderr,"No extended input devices found !!\n"); - fprintf(stderr,"X11 Joystick disabled\n"); - } - - - /* Catch program termination signals so we can clean up properly */ - signal(SIGABRT, _EVT_abort); - signal(SIGFPE, _EVT_abort); - signal(SIGINT, _EVT_abort); -} - -/**************************************************************************** -REMARKS -Changes the range of coordinates returned by the mouse functions to the -specified range of values. This is used when changing between graphics -modes set the range of mouse coordinates for the new display mode. -****************************************************************************/ -void EVTAPI EVT_setMouseRange( - int xRes, - int yRes) -{ - rangeX = xRes; - rangeY = yRes; -} - -/**************************************************************************** -REMARKS: -Initiailises the internal event handling modules. The EVT_suspend function -can be called to suspend event handling (such as when shelling out to DOS), -and this function can be used to resume it again later. -****************************************************************************/ -void EVT_resume(void) -{ - /* Do nothing for non DOS systems */ -} - -/**************************************************************************** -REMARKS -Suspends all of our event handling operations. This is also used to -de-install the event handling code. -****************************************************************************/ -void EVT_suspend(void) -{ - /* Do nothing for non DOS systems */ -} - -/**************************************************************************** -REMARKS -Exits the event module for program terminatation. -****************************************************************************/ -void EVT_exit(void) -{ - /* Restore signal handlers */ - signal(SIGABRT, SIG_DFL); - signal(SIGFPE, SIG_DFL); - signal(SIGINT, SIG_DFL); - - /* TODO: Do any OS specific cleanup in here */ -} - -/**************************************************************************** -REMARKS -Sets the current X11 display -****************************************************************************/ -void EVT_setX11Display(Display *dpy, Window win) -{ - _EVT_dpy = dpy; - _EVT_win = win; -} diff --git a/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h deleted file mode 100644 index 45d7451..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h +++ /dev/null @@ -1,38 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: BeOS -* -* Description: Include file to include all OS specific header files. -* -****************************************************************************/ - -#include -#include -#include -#include -#ifdef USE_OS_JOYSTICK -#include -#include -#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj b/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj deleted file mode 100644 index 0c6c80f..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj +++ /dev/null @@ -1,74 +0,0 @@ -[SciTech] -compiler=wc10- -targetos=d32 -[COMPILER] -version=5.0b -MACRO=enable_current_compiler\n -activeconfig=,getch.exe -FILTERNAME=Source Files\n -FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n -FILTERASSOCIATEFILETYPES=0 -FILTERAPPCOMMAND=\n -vcsproject=SCC:Perforce SCM://depot -vcslocalpath=SCC:Perforce SCM:c:\ -compile=concur|capture|:Compile:&Compile,dmake %n.obj -make=concur|capture|clear|saveall|:Build:&Build,dmake %b -rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake -u %b -debug=concur|capture|savenone|nochangedir|:Debug:&Debug,wdn %b -execute=hide|savenone|nochangedir|:Execute:E&xecute, -user1=hide|nochangedir|:User 1:User 1, -user2=hide|nochangedir|:User 2:User 2, -usertool_build_all=concur|capture|clear|savenone|:Build All:Build All,dmake all -usertool_rebuild_all=concur|capture|clear|savenone|:Rebuild All:Rebuild All,dmake -u all -usertool_clean_directory=concur|capture|savenone|:Clean Directory:&Clean Directory,dmake cleanexe -workingdir=. -includedirs=%(SCITECH)\include;%(PRIVATE)\include -reffile= -[FILES] -tests\altbrk.c -tests\altcrit.c -tests\biosptr.c -tests\block.c -tests\brk.c -tests\callreal.c -tests\checks.c -tests\cpu.c -tests\critical.c -tests\getch.c -tests\isvesa.c -tests\key.c -tests\key15.c -tests\memtest.c -tests\mouse.c -tests\rtc.c -tests\showpci.c -tests\tick.c -tests\timerc.c -tests\timercpp.cpp -tests\uswc.c -tests\vftest.c -tests\video.c -[ASSOCIATION] -[CONFIGURATIONS] -config=,altbrk.exe -config=,altcrit.exe -config=,biosptr.exe -config=,block.exe -config=,brk.exe -config=,callreal.exe -config=,cpu.exe -config=,critical.exe -config=,getch.exe -config=,isvesa.exe -config=,key.exe -config=,key15.exe -config=,memtest.exe -config=,mouse.exe -config=,rtc.exe -config=,showpci.exe -config=,tick.exe -config=,timerc.exe -config=,timercpp.exe -config=,uswc.exe -config=,vftest.exe -config=,video.exe diff --git a/board/MAI/bios_emulator/scitech/src/pm/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/ztimer.c deleted file mode 100644 index 5acf7b1..0000000 --- a/board/MAI/bios_emulator/scitech/src/pm/ztimer.c +++ /dev/null @@ -1,516 +0,0 @@ -/**************************************************************************** -* -* SciTech OS Portability Manager Library -* -* ======================================================================== -* -* The contents of this file are subject to the SciTech MGL Public -* License Version 1.0 (the "License"); you may not use this file -* except in compliance with the License. You may obtain a copy of -* the License at http://www.scitechsoft.com/mgl-license.txt -* -* Software distributed under the License is distributed on an -* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or -* implied. See the License for the specific language governing -* rights and limitations under the License. -* -* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. -* -* The Initial Developer of the Original Code is SciTech Software, Inc. -* All Rights Reserved. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* -* Description: Module to implement high precision timing on each OS. -* -****************************************************************************/ - -#include "ztimer.h" -#include "pmapi.h" -#include "oshdr.h" - -/*---------------------------- Global variables ---------------------------*/ - -static LZTimerObject LZTimer; -static ulong start,finish; -#ifdef __INTEL__ -static long cpuSpeed = -1; -static ibool haveRDTSC = false; -#endif - -/*----------------------------- Implementation ----------------------------*/ - -/* External Intel assembler functions */ -#ifdef __INTEL__ -/* {secret} */ -void _ASMAPI _CPU_readTimeStamp(CPU_largeInteger *time); -/* {secret} */ -ulong _ASMAPI _CPU_diffTime64(CPU_largeInteger *t1,CPU_largeInteger *t2,CPU_largeInteger *t); -/* {secret} */ -ulong _ASMAPI _CPU_calcMicroSec(CPU_largeInteger *count,ulong freq); -#endif - -#if defined(__SMX32__) -#include "smx/ztimer.c" -#elif defined(__RTTARGET__) -#include "rttarget/ztimer.c" -#elif defined(__REALDOS__) -#include "dos/ztimer.c" -#elif defined(__NT_DRIVER__) -#include "ntdrv/ztimer.c" -#elif defined(__WIN32_VXD__) -#include "vxd/ztimer.c" -#elif defined(__WINDOWS32__) -#include "win32/ztimer.c" -#elif defined(__OS2_VDD__) -#include "vdd/ztimer.c" -#elif defined(__OS2__) -#include "os2/ztimer.c" -#elif defined(__LINUX__) -#include "linux/ztimer.c" -#elif defined(__QNX__) -#include "qnx/ztimer.c" -#elif defined(__BEOS__) -#include "beos/ztimer.c" -#else -#error Timer library not ported to this platform yet! -#endif - -/*------------------------ Public interface routines ----------------------*/ - -/**************************************************************************** -DESCRIPTION: -Initializes the Zen Timer library (extended) - -PARAMETERS: -accurate - True of the speed should be measured accurately - -HEADER: -ztimer.h - -REMARKS: -This function initializes the Zen Timer library, and /must/ be called before -any of the remaining Zen Timer library functions are called. The accurate -parameter is used to determine whether highly accurate timing should be -used or not. If high accuracy is needed, more time is spent profiling the -actual speed of the CPU so that we can obtain highly accurate timing -results, but the time spent in the initialisation routine will be -significantly longer (on the order of 5 seconds). -****************************************************************************/ -void ZAPI ZTimerInitExt( - ibool accurate) -{ - if (cpuSpeed == -1) { - __ZTimerInit(); -#ifdef __INTEL__ - cpuSpeed = CPU_getProcessorSpeedInHZ(accurate); - haveRDTSC = CPU_haveRDTSC() && (cpuSpeed > 0); -#endif - } -} - -/**************************************************************************** -DESCRIPTION: -Initializes the Zen Timer library. - -HEADER: -ztimer.h - -REMARKS: -This function initializes the Zen Timer library, and /must/ be called before -any of the remaining Zen Timer library functions are called. -****************************************************************************/ -void ZAPI ZTimerInit(void) -{ - ZTimerInitExt(false); -} - -/**************************************************************************** -DESCRIPTION: -Starts the Long Period Zen Timer counting. - -HEADER: -ztimer.h - -PARAMETERS: -tm - Timer object to start timing with - -REMARKS: -Starts the Long Period Zen Timer counting. Once you have started the timer, -you can stop it with LZTimerOff or you can latch the current count with -LZTimerLap. - -The Long Period Zen Timer uses a number of different high precision timing -mechanisms to obtain microsecond accurate timings results whenever possible. -The following different techniques are used depending on the operating -system, runtime environment and CPU on the target machine. If the target -system has a Pentium CPU installed which supports the Read Time Stamp -Counter instruction (RDTSC), the Zen Timer library will use this to -obtain the maximum timing precision available. - -Under 32-bit Windows, if the Pentium RDTSC instruction is not available, we -first try to use the Win32 QueryPerformanceCounter API, and if that is not -available we fall back on the timeGetTime API which is always supported. - -Under 32-bit DOS, if the Pentium RDTSC instruction is not available, we -then do all timing using the old style 8253 timer chip. The 8253 timer -routines provide highly accurate timings results in pure DOS mode, however -in a DOS box under Windows or other Operating Systems the virtualization -of the timer can produce inaccurate results. - -Note: Because the Long Period Zen Timer stores the results in a 32-bit - unsigned integer, you can only time periods of up to 2^32 microseconds, - or about 1hr 20mins. For timing longer periods use the Ultra Long - Period Zen Timer. - -SEE ALSO: -LZTimerOff, LZTimerLap, LZTimerCount -****************************************************************************/ -void ZAPI LZTimerOnExt( - LZTimerObject *tm) -{ -#ifdef __INTEL__ - if (haveRDTSC) { - _CPU_readTimeStamp(&tm->start); - } - else -#endif - __LZTimerOn(tm); -} - -/**************************************************************************** -DESCRIPTION: -Returns the current count for the Long Period Zen Timer and keeps it -running. - -HEADER: -ztimer.h - -PARAMETERS: -tm - Timer object to do lap timing with - -RETURNS: -Count that has elapsed in microseconds. - -REMARKS: -Returns the current count that has elapsed since the last call to -LZTimerOn in microseconds. The time continues to run after this function is -called so you can call this function repeatedly. - -SEE ALSO: -LZTimerOn, LZTimerOff, LZTimerCount -****************************************************************************/ -ulong ZAPI LZTimerLapExt( - LZTimerObject *tm) -{ -#ifdef __INTEL__ - CPU_largeInteger tmLap,tmCount; - - if (haveRDTSC) { - _CPU_readTimeStamp(&tmLap); - _CPU_diffTime64(&tm->start,&tmLap,&tmCount); - return _CPU_calcMicroSec(&tmCount,cpuSpeed); - } - else -#endif - return __LZTimerLap(tm); -} - -/**************************************************************************** -DESCRIPTION: -Stops the Long Period Zen Timer counting. - -HEADER: -ztimer.h - -PARAMETERS: -tm - Timer object to stop timing with - -REMARKS: -Stops the Long Period Zen Timer counting and latches the count. Once you -have stopped the timer you can read the count with LZTimerCount. If you need -highly accurate timing, you should use the on and off functions rather than -the lap function since the lap function does not subtract the overhead of -the function calls from the timed count. - -SEE ALSO: -LZTimerOn, LZTimerLap, LZTimerCount -****************************************************************************/ -void ZAPI LZTimerOffExt( - LZTimerObject *tm) -{ -#ifdef __INTEL__ - if (haveRDTSC) { - _CPU_readTimeStamp(&tm->end); - } - else -#endif - __LZTimerOff(tm); -} - -/**************************************************************************** -DESCRIPTION: -Returns the current count for the Long Period Zen Timer. - -HEADER: -ztimer.h - -PARAMETERS: -tm - Timer object to compute the elapsed time with. - -RETURNS: -Count that has elapsed in microseconds. - -REMARKS: -Returns the current count that has elapsed between calls to -LZTimerOn and LZTimerOff in microseconds. - -SEE ALSO: -LZTimerOn, LZTimerOff, LZTimerLap -****************************************************************************/ -ulong ZAPI LZTimerCountExt( - LZTimerObject *tm) -{ -#ifdef __INTEL__ - CPU_largeInteger tmCount; - - if (haveRDTSC) { - _CPU_diffTime64(&tm->start,&tm->end,&tmCount); - return _CPU_calcMicroSec(&tmCount,cpuSpeed); - } - else -#endif - return __LZTimerCount(tm); -} - -/**************************************************************************** -DESCRIPTION: -Starts the Long Period Zen Timer counting. - -HEADER: -ztimer.h - -REMARKS: -Obsolete function. You should use the LZTimerOnExt function instead -which allows for multiple timers running at the same time. -****************************************************************************/ -void ZAPI LZTimerOn(void) -{ LZTimerOnExt(&LZTimer); } - -/**************************************************************************** -DESCRIPTION: -Returns the current count for the Long Period Zen Timer and keeps it -running. - -HEADER: -ztimer.h - -RETURNS: -Count that has elapsed in microseconds. - -REMARKS: -Obsolete function. You should use the LZTimerLapExt function instead -which allows for multiple timers running at the same time. -****************************************************************************/ -ulong ZAPI LZTimerLap(void) -{ return LZTimerLapExt(&LZTimer); } - -/**************************************************************************** -DESCRIPTION: -Stops the Long Period Zen Timer counting. - -HEADER: -ztimer.h - -REMARKS: -Obsolete function. You should use the LZTimerOffExt function instead -which allows for multiple timers running at the same time. -****************************************************************************/ -void ZAPI LZTimerOff(void) -{ LZTimerOffExt(&LZTimer); } - -/**************************************************************************** -DESCRIPTION: -Returns the current count for the Long Period Zen Timer. - -HEADER: -ztimer.h - -RETURNS: -Count that has elapsed in microseconds. - -REMARKS: -Obsolete function. You should use the LZTimerCountExt function instead -which allows for multiple timers running at the same time. -****************************************************************************/ -ulong ZAPI LZTimerCount(void) -{ return LZTimerCountExt(&LZTimer); } - -/**************************************************************************** -DESCRIPTION: -Starts the Ultra Long Period Zen Timer counting. - -HEADER: -ztimer.h - -REMARKS: -Starts the Ultra Long Period Zen Timer counting. Once you have started the -timer, you can stop it with ULZTimerOff or you can latch the current count -with ULZTimerLap. - -The Ultra Long Period Zen Timer uses the available operating system services -to obtain accurate timings results with as much precision as the operating -system provides, but with enough granularity to time longer periods of -time than the Long Period Zen Timer. Note that the resolution of the timer -ticks is not constant between different platforms, and you should use the -ULZTimerResolution function to determine the number of seconds in a single -tick of the timer, and use this to convert the timer counts to seconds. - -Under 32-bit Windows, we use the timeGetTime function which provides a -resolution of 1 millisecond (0.001 of a second). Given that the timer -count is returned as an unsigned 32-bit integer, this we can time intervals -that are a maximum of 2^32 milliseconds in length (or about 1,200 hours or -50 days!). - -Under 32-bit DOS, we use the system timer tick which runs at 18.2 times per -second. Given that the timer count is returned as an unsigned 32-bit integer, -this we can time intervals that are a maximum of 2^32 * (1/18.2) in length -(or about 65,550 hours or 2731 days!). - -SEE ALSO: -ULZTimerOff, ULZTimerLap, ULZTimerCount, ULZElapsedTime, ULZReadTime -****************************************************************************/ -void ZAPI ULZTimerOn(void) -{ start = __ULZReadTime(); } - -/**************************************************************************** -DESCRIPTION: -Returns the current count for the Ultra Long Period Zen Timer and keeps it -running. - -HEADER: -ztimer.h - -RETURNS: -Count that has elapsed in resolution counts. - -REMARKS: -Returns the current count that has elapsed since the last call to -ULZTimerOn in microseconds. The time continues to run after this function is -called so you can call this function repeatedly. - -SEE ALSO: -ULZTimerOn, ULZTimerOff, ULZTimerCount -****************************************************************************/ -ulong ZAPI ULZTimerLap(void) -{ return (__ULZReadTime() - start); } - -/**************************************************************************** -DESCRIPTION: -Stops the Long Period Zen Timer counting. - -HEADER: -ztimer.h - -REMARKS: -Stops the Ultra Long Period Zen Timer counting and latches the count. Once -you have stopped the timer you can read the count with ULZTimerCount. - -SEE ALSO: -ULZTimerOn, ULZTimerLap, ULZTimerCount -****************************************************************************/ -void ZAPI ULZTimerOff(void) -{ finish = __ULZReadTime(); } - -/**************************************************************************** -DESCRIPTION: -Returns the current count for the Ultra Long Period Zen Timer. - -HEADER: -ztimer.h - -RETURNS: -Count that has elapsed in resolution counts. - -REMARKS: -Returns the current count that has elapsed between calls to -ULZTimerOn and ULZTimerOff in resolution counts. - -SEE ALSO: -ULZTimerOn, ULZTimerOff, ULZTimerLap, ULZTimerResolution -****************************************************************************/ -ulong ZAPI ULZTimerCount(void) -{ return (finish - start); } - -/**************************************************************************** -DESCRIPTION: -Reads the current time from the Ultra Long Period Zen Timer. - -HEADER: -ztimer.h - -RETURNS: -Current timer value in resolution counts. - -REMARKS: -Reads the current Ultra Long Period Zen Timer and returns it’s current -count. You can use the ULZElapsedTime function to find the elapsed time -between two timer count readings. - -SEE ALSO: -ULZElapsedTime, ULZTimerResolution -****************************************************************************/ -ulong ZAPI ULZReadTime(void) -{ return __ULZReadTime(); } - -/**************************************************************************** -DESCRIPTION: -Compute the elapsed time between two timer counts. - -HEADER: -ztimer.h - -PARAMETERS: -start - Starting time for elapsed count -finish - Ending time for elapsed count - -RETURNS: -Elapsed timer in resolution counts. - -REMARKS: -Returns the elapsed time for the Ultra Long Period Zen Timer in units of the -timers resolution (1/18th of a second under DOS). This function correctly -computes the difference even if a midnight boundary has been crossed -during the timing period. - -SEE ALSO: -ULZReadTime, ULZTimerResolution -****************************************************************************/ -ulong ZAPI ULZElapsedTime( - ulong start, - ulong finish) -{ return __ULZElapsedTime(start,finish); } - -/**************************************************************************** -DESCRIPTION: -Returns the resolution of the Ultra Long Period Zen Timer. - -HEADER: -ztimer.h - -PARAMETERS: -resolution - Place to store the timer in microseconds per timer count. - -REMARKS: -Returns the resolution of the Ultra Long Period Zen Timer as a 32-bit -integer value measured in microseconds per timer count. - -SEE ALSO: -ULZReadTime, ULZElapsedTime, ULZTimerCount -****************************************************************************/ -void ZAPI ULZTimerResolution( - ulong *resolution) -{ *resolution = ULZTIMER_RESOLUTION; } diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h b/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h deleted file mode 100644 index 77c545a..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h +++ /dev/null @@ -1,450 +0,0 @@ -/* $XConsortium: AsmMacros.h /main/13 1996/10/25 11:33:12 kaleb $ */ -/* - * (c) Copyright 1993,1994 by David Wexelblat - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * DAVID WEXELBLAT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Except as contained in this notice, the name of David Wexelblat shall not be - * used in advertising or otherwise to promote the sale, use or other dealings - * in this Software without prior written authorization from David Wexelblat. - * - */ -/* - * Copyright 1997 - * Digital Equipment Corporation. All rights reserved. - * This software is furnished under license and may be used and copied only in - * accordance with the following terms and conditions. Subject to these - * conditions, you may download, copy, install, use, modify and distribute - * this software in source and/or binary form. No title or ownership is - * transferred hereby. - * - * 1) Any source code used, modified or distributed must reproduce and retain - * this copyright notice and list of conditions as they appear in the source - * file. - * - * 2) No right is granted to use any trade name, trademark, or logo of Digital - * Equipment Corporation. Neither the "Digital Equipment Corporation" name - * nor any trademark or logo of Digital Equipment Corporation may be used - * to endorse or promote products derived from this software without the - * prior written permission of Digital Equipment Corporation. - * - * 3) This software is provided "AS-IS" and any express or implied warranties, - * including but not limited to, any implied warranties of merchantability, - * fitness for a particular purpose, or non-infringement are disclaimed. In - * no event shall DIGITAL be liable for any damages whatsoever, and in - * particular, DIGITAL shall not be liable for special, indirect, - * consequential, or incidental damages or damages for - * lost profits, loss of revenue or loss of use, whether such damages arise - * in contract, - * negligence, tort, under statute, in equity, at law or otherwise, even if - * advised of the possibility of such damage. - * - */ - -/* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/AsmMacros.h,v 3.14 1999/09/25 14:36:58 dawes Exp $ */ - -#if defined(__GNUC__) -#if defined(linux) && (defined(__alpha__) || defined(__ia64__)) -#undef inb -#define inb _inb -#undef inw -#define inw _inw -#undef inl -#define inl _inl -#undef outb -#define outb(p,v) _outb((v),(p)) -#undef outw -#define outw(p,v) _outw((v),(p)) -#undef outl -#define outl(p,v) _outl((v),(p)) -#else -#if defined(__sparc__) -#ifndef ASI_PL -#define ASI_PL 0x88 -#endif - -static __inline__ void -outb(port, val) -unsigned long port; -char val; -{ - __asm__ __volatile__("stba %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); -} - -static __inline__ void -outw(port, val) -unsigned long port; -char val; -{ - __asm__ __volatile__("stha %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); -} - -static __inline__ void -outl(port, val) -unsigned long port; -char val; -{ - __asm__ __volatile__("sta %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); -} - -static __inline__ unsigned int -inb(port) -unsigned long port; -{ - unsigned char ret; - __asm__ __volatile__("lduba [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); - return ret; -} - -static __inline__ unsigned int -inw(port) -unsigned long port; -{ - unsigned char ret; - __asm__ __volatile__("lduha [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); - return ret; -} - -static __inline__ unsigned int -inl(port) -unsigned long port; -{ - unsigned char ret; - __asm__ __volatile__("lda [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); - return ret; -} -#else -#ifdef __arm32__ -unsigned int IOPortBase; /* Memory mapped I/O port area */ - -static __inline__ void -outb(port, val) - short port; - char val; -{ - if ((unsigned short)port >= 0x400) return; - - *(volatile unsigned char*)(((unsigned short)(port))+IOPortBase) = val; -} - -static __inline__ void -outw(port, val) - short port; - short val; -{ - if ((unsigned short)port >= 0x400) return; - - *(volatile unsigned short*)(((unsigned short)(port))+IOPortBase) = val; -} - -static __inline__ void -outl(port, val) - short port; - int val; -{ - if ((unsigned short)port >= 0x400) return; - - *(volatile unsigned long*)(((unsigned short)(port))+IOPortBase) = val; -} - -static __inline__ unsigned int -inb(port) - short port; -{ - if ((unsigned short)port >= 0x400) return((unsigned int)-1); - - return(*(volatile unsigned char*)(((unsigned short)(port))+IOPortBase)); -} - -static __inline__ unsigned int -inw(port) - short port; -{ - if ((unsigned short)port >= 0x400) return((unsigned int)-1); - - return(*(volatile unsigned short*)(((unsigned short)(port))+IOPortBase)); -} - -static __inline__ unsigned int -inl(port) - short port; -{ - if ((unsigned short)port >= 0x400) return((unsigned int)-1); - - return(*(volatile unsigned long*)(((unsigned short)(port))+IOPortBase)); -} -#else /* __arm32__ */ -#if defined(Lynx) && defined(__powerpc__) -extern unsigned char *ioBase; - -static volatile void -eieio() -{ - __asm__ __volatile__ ("eieio"); -} - -static void -outb(port, value) -short port; -unsigned char value; -{ - *(uchar *)(ioBase + port) = value; eieio(); -} - -static void -outw(port, value) -short port; -unsigned short value; -{ - *(unsigned short *)(ioBase + port) = value; eieio(); -} - -static void -outl(port, value) -short port; -unsigned long value; -{ - *(unsigned long *)(ioBase + port) = value; eieio(); -} - -static unsigned char -inb(port) -short port; -{ - unsigned char val; - - val = *((unsigned char *)(ioBase + port)); eieio(); - return(val); -} - -static unsigned short -inw(port) -short port; -{ - unsigned short val; - - val = *((unsigned short *)(ioBase + port)); eieio(); - return(val); -} - -static unsigned long -inl(port) -short port; -{ - unsigned long val; - - val = *((unsigned long *)(ioBase + port)); eieio(); - return(val); -} - -#else -#if defined(__FreeBSD__) && defined(__alpha__) - -#include - -extern void outb(u_int32_t port, u_int8_t val); -extern void outw(u_int32_t port, u_int16_t val); -extern void outl(u_int32_t port, u_int32_t val); -extern u_int8_t inb(u_int32_t port); -extern u_int16_t inw(u_int32_t port); -extern u_int32_t inl(u_int32_t port); - -#else -#ifdef GCCUSESGAS -static __inline__ void -outb(port, val) -short port; -char val; -{ - __asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port)); -} - -static __inline__ void -outw(port, val) -short port; -short val; -{ - __asm__ __volatile__("outw %0,%1" : :"a" (val), "d" (port)); -} - -static __inline__ void -outl(port, val) -short port; -unsigned int val; -{ - __asm__ __volatile__("outl %0,%1" : :"a" (val), "d" (port)); -} - -static __inline__ unsigned int -inb(port) -short port; -{ - unsigned char ret; - __asm__ __volatile__("inb %1,%0" : - "=a" (ret) : - "d" (port)); - return ret; -} - -static __inline__ unsigned int -inw(port) -short port; -{ - unsigned short ret; - __asm__ __volatile__("inw %1,%0" : - "=a" (ret) : - "d" (port)); - return ret; -} - -static __inline__ unsigned int -inl(port) -short port; -{ - unsigned int ret; - __asm__ __volatile__("inl %1,%0" : - "=a" (ret) : - "d" (port)); - return ret; -} - -#else /* GCCUSESGAS */ - -static __inline__ void -outb(port, val) - short port; - char val; -{ - __asm__ __volatile__("out%B0 (%1)" : :"a" (val), "d" (port)); -} - -static __inline__ void -outw(port, val) - short port; - short val; -{ - __asm__ __volatile__("out%W0 (%1)" : :"a" (val), "d" (port)); -} - -static __inline__ void -outl(port, val) - short port; - unsigned int val; -{ - __asm__ __volatile__("out%L0 (%1)" : :"a" (val), "d" (port)); -} - -static __inline__ unsigned int -inb(port) - short port; -{ - unsigned int ret; - __asm__ __volatile__("in%B0 (%1)" : - "=a" (ret) : - "d" (port)); - return ret; -} - -static __inline__ unsigned int -inw(port) - short port; -{ - unsigned int ret; - __asm__ __volatile__("in%W0 (%1)" : - "=a" (ret) : - "d" (port)); - return ret; -} - -static __inline__ unsigned int -inl(port) - short port; -{ - unsigned int ret; - __asm__ __volatile__("in%L0 (%1)" : - "=a" (ret) : - "d" (port)); - return ret; -} - -#endif /* GCCUSESGAS */ -#endif /* Lynx && __powerpc__ */ -#endif /* arm32 */ -#endif /* linux && __sparc__ */ -#endif /* linux && __alpha__ */ -#endif /* __FreeBSD__ && __alpha__ */ - -#if defined(linux) || defined(__arm32__) || (defined(Lynx) && defined(__powerpc__)) - -#define intr_disable() -#define intr_enable() - -#else - -static __inline__ void -intr_disable() -{ - __asm__ __volatile__("cli"); -} - -static __inline__ void -intr_enable() -{ - __asm__ __volatile__("sti"); -} - -#endif /* else !linux && !__arm32__ */ - -#else /* __GNUC__ */ - -#if defined(_MINIX) && defined(_ACK) - -/* inb, outb, inw and outw are defined in the library */ -/* ... but I've no idea if the same is true for inl & outl */ - -u8_t inb(U16_t); -void outb(U16_t, U8_t); -u16_t inw(U16_t); -void outw(U16_t, U16_t); -u32_t inl(U16_t); -void outl(U16_t, U32_t); - -#else /* not _MINIX and _ACK */ - -# if defined(__STDC__) && (__STDC__ == 1) -# ifndef NCR -# define asm __asm -# endif -# endif -# ifdef SVR4 -# include -# ifndef __USLC__ -# define __USLC__ -# endif -# endif -#ifndef SCO325 -# include -#else -# include "../common/scoasm.h" -#endif -#define intr_disable() asm("cli") -#define intr_enable() asm("sti") - -#endif /* _MINIX and _ACK */ -#endif /* __GNUC__ */ diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/README b/board/MAI/bios_emulator/scitech/src/v86bios/README deleted file mode 100644 index cb65674..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/README +++ /dev/null @@ -1,32 +0,0 @@ - -This is a preliminary version of a VGA softbooter for LINUX. - -It makes use of the of the vm86() call and is therefore only -usable on ix86 systems. -There are plans to port this program to use a x86 emulator -like x86emu. Also it may be ported to other operating systems. - -So far it has been tested on a small number of cards. It might -well be that it will fail on your card. - -If you need to make modifications to the programs to be able -to boot your card please let the author know. - -So far there is no command line interface. All options need -to be hardcoded. You can do this by editing debug.h. You can -turn on a bunch of debug output. Other options allow you to -boot the primary card (CONFIG_ACTIVE_DEVICE), save the bios -to a file (SAVE_BIOS), and map the original system bios -(MAP_SYS_BIOS). - -The author wants to thank - Hans Lermen (dosemu) - and - Kendall Bennett (x86emu) -for their support. - -Parts of the code - especially in v86.c and io.c - are based on code -taken from dosemu. Parts of the code in int.c are based on code taken -from x86emu - -Egbert Eich. diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr b/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr deleted file mode 100644 index 9d2a80d..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr +++ /dev/null @@ -1,15 +0,0 @@ -/.*\(0x3da.*/||/.*\(0x3ba.*/ { - if (v_3da != 1) print "_v_retrace_"; - v_3da = 1; - next; - } -/.*\(0x42.*/||/.*\(0x43.*/ { - if (v_4x != 1) print "_timer_"; - v_4x = 1; - next; -} -{ - print; - v_3da = 0; - v_4x = 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c b/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c deleted file mode 100644 index 6b12dff..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c +++ /dev/null @@ -1,415 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(__alpha__) || defined (__ia64__) -#include -#elif defined(HAVE_SYS_PERM) -#include -#endif -#include "debug.h" -#include "v86bios.h" -#include "pci.h" -#include "AsmMacros.h" - -#define SIZE 0x100000 -#define VRAM_START 0xA0000 -#define VRAM_SIZE 0x1FFFF -#define V_BIOS_SIZE 0x1FFFF -#define BIOS_START 0x7C00 /* default BIOS entry */ -#define BIOS_MEM 0x600 - -CARD8 code[] = { 0xcd, 0x10, 0xf4 }; -struct config Config; - -static int map(void); -static void unmap(void); -static void runBIOS(int argc, char **argv); -static int map_vram(void); -static void unmap_vram(void); -static int copy_vbios(memType base); -static int copy_sys_bios(void); -static CARD32 setup_int_vect(void); -static void update_bios_vars(void); -static int chksum(CARD8 *start); -static void setup_bios_regs(i86biosRegsPtr regs, int argc, char **argv); -static void print_regs(i86biosRegsPtr regs); -void dprint(unsigned long start, unsigned long size); - -void loadCodeToMem(unsigned char *ptr, CARD8 *code); - -static int vram_mapped = 0; -static char* bios_var; - - -int -main(int argc,char **argv) -{ - CARD32 vbios_base; - - Config.PrintPort = PRINT_PORT; - Config.IoStatistics = IO_STATISTICS; - Config.PrintIrq = PRINT_IRQ; - Config.PrintPci = PRINT_PCI; - Config.ShowAllDev = SHOW_ALL_DEV; - Config.PrintIp = PRINT_IP; - Config.SaveBios = SAVE_BIOS; - Config.Trace = TRACE; - Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY; - Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE; - Config.MapSysBios = MAP_SYS_BIOS; - Config.Resort = RESORT; - Config.FixRom = FIX_ROM; - Config.NoConsole = NO_CONSOLE; - Config.Verbose = VERBOSE; - - if (!map()) - exit(1); - if (!copy_sys_bios()) - exit(1); - if (!(vbios_base = setup_int_vect())) - exit(1); - if (!map_vram()) - exit(1); - if (!copy_vbios(vbios_base)) - exit(1); - - iopl(3); - setup_io(); - runBIOS(argc,argv); - update_bios_vars(); - unmap_vram(); - iopl(0); - unmap(); - printf("done !\n"); - exit (1); -} - -int -map(void) -{ - void* mem; - - mem = mmap(0, (size_t)SIZE, - PROT_EXEC | PROT_READ | PROT_WRITE, - MAP_FIXED | MAP_PRIVATE | MAP_ANON, - -1, 0 ); - if (mem != 0) { - perror("anonymous map"); - return (0); - } - memset(mem,0,SIZE); - - loadCodeToMem((unsigned char *) BIOS_START, code); - return (1); -} - -static int -copy_sys_bios(void) -{ -#define SYS_BIOS 0xF0000 - int mem_fd; - - if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { - perror("opening memory"); - return (0); - } - - if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS) - goto Error; - if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF) - goto Error; - - close(mem_fd); - return (1); - -Error: - perror("sys_bios"); - close(mem_fd); - return (0); -} - -static int -map_vram(void) -{ - int mem_fd; - -#ifdef __ia64__ - if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) -#else - if ((mem_fd = open(MEM_FILE,O_RDWR))<0) -#endif - { - perror("opening memory"); - return 0; - } - -#ifndef __alpha__ - if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE, - PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, - mem_fd, VRAM_START) == (void *) -1) -#else - if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */ - if (!_bus_base_sparse()) sparse_shift = 0; - if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift), - PROT_READ | PROT_WRITE, - MAP_SHARED, - mem_fd, (VRAM_START << sparse_shift) - | _bus_base_sparse())) == (void *) -1) -#endif - { - perror("mmap error in map_hardware_ram"); - close(mem_fd); - return (0); - } - vram_mapped = 1; - close(mem_fd); - return (1); -} - -static int -copy_vbios(memType v_base) -{ - int mem_fd; - unsigned char *tmp; - int size; - - if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { - perror("opening memory"); - return (0); - } - - if (lseek(mem_fd,(off_t) v_base, SEEK_SET) != (off_t) v_base) { - fprintf(stderr,"Cannot lseek\n"); - goto Error; - } - tmp = (unsigned char *)malloc(3); - if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) { - fprintf(stderr,"Cannot read\n"); - goto Error; - } - if (lseek(mem_fd,(off_t) v_base,SEEK_SET) != (off_t) v_base) - goto Error; - - if (*tmp != 0x55 || *(tmp+1) != 0xAA ) { - fprintf(stderr,"No bios found at: 0x%lx\n",v_base); - goto Error; - } -#ifdef DEBUG - dprint((unsigned long)tmp,0x100); -#endif - size = *(tmp+2) * 512; - - if (read(mem_fd, (char *)v_base, (size_t) size) != (size_t) size) { - fprintf(stderr,"Cannot read\n"); - goto Error; - } - free(tmp); - close(mem_fd); - if (!chksum((CARD8*)v_base)) - return (0); - - return (1); - -Error: - perror("v_bios"); - close(mem_fd); - return (0); -} - -static void -unmap(void) -{ - munmap(0,SIZE); -} - -static void -unmap_vram(void) -{ - if (!vram_mapped) return; - - munmap((void*)VRAM_START,VRAM_SIZE); - vram_mapped = 0; -} - -static void -runBIOS(int argc, char ** argv) -{ - i86biosRegs bRegs; -#ifdef V86BIOS_DEBUG - printf("starting BIOS\n"); -#endif - setup_bios_regs(&bRegs, argc, argv); - do_x86(BIOS_START,&bRegs); - print_regs(&bRegs); -#ifdef V86BIOS_DEBUG - printf("done\n"); -#endif -} - -static CARD32 -setup_int_vect(void) -{ - int mem_fd; - CARD32 vbase; - void *map; - - if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { - perror("opening memory"); - return (0); - } - - if ((map = mmap((void *) 0, (size_t) 0x2000, - PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, - mem_fd, 0)) == (void *)-1) { - perror("mmap error in map_hardware_ram"); - close(mem_fd); - return (0); - } - - close(mem_fd); - memcpy(0,map,BIOS_MEM); - munmap(map,0x2000); - /* - * create a backup copy of the bios variables to write back the - * modified values - */ - bios_var = (char *)malloc(BIOS_MEM); - memcpy(bios_var,0,BIOS_MEM); - - vbase = (*((CARD16*)(0x10 << 2) + 1)) << 4; - fprintf(stderr,"vbase: 0x%x\n",vbase); - return vbase; -} - -static void -update_bios_vars(void) -{ - int mem_fd; - void *map; - memType i; - -#ifdef __ia64__ - if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) -#else - if ((mem_fd = open(MEM_FILE,O_RDWR))<0) -#endif - { - perror("opening memory"); - return; - } - - if ((map = mmap((void *) 0, (size_t) 0x2000, - PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, - mem_fd, 0)) == (void *)-1) { - perror("mmap error in map_hardware_ram"); - close(mem_fd); - return; - } - - for (i = 0; i < BIOS_MEM; i++) { - if (bios_var[i] != *(CARD8*)i) - *((CARD8*)map + i) = *(CARD8*)i; - } - - munmap(map,0x2000); - close(mem_fd); -} - - -static void -setup_bios_regs(i86biosRegsPtr regs, int argc, char **argv) -{ - int c; - - regs->ax = 0; - regs->bx = 0; - regs->cx = 0; - regs->dx = 0; - regs->es = 0; - regs->di = 0; - opterr = 0; - while ((c = getopt(argc,argv,"a:b:c:d:e:i:")) != EOF) { - switch (c) { - case 'a': - regs->ax = strtol(optarg,NULL,0); - break; - case 'b': - regs->bx = strtol(optarg,NULL,0); - break; - case 'c': - regs->cx = strtol(optarg,NULL,0); - break; - case 'd': - regs->dx = strtol(optarg,NULL,0); - break; - case 'e': - regs->es = strtol(optarg,NULL,0); - break; - case 'i': - regs->di = strtol(optarg,NULL,0); - break; - } - } -} - - -static int -chksum(CARD8 *start) -{ - CARD16 size; - CARD8 val = 0; - int i; - - size = *(start+2) * 512; - for (i = 0; iax, - (CARD16)regs->bx,(CARD16)regs->cx,(CARD16)regs->dx, - (CARD16)regs->es,(CARD16)regs->di); -} - -void -loadCodeToMem(unsigned char *ptr, CARD8 code[]) -{ - int i; - CARD8 val; - - for ( i=0;;i++) { - val = code[i]; - *ptr++ = val; - if (val == 0xf4) break; - } - return; -} - -void -dprint(unsigned long start, unsigned long size) -{ - int i,j; - char *c = (char *)start; - - for (j = 0; j < (size >> 4); j++) { - printf ("\n0x%lx: ",(unsigned long)c); - for (i = 0; i<16; i++) - printf("%x ",(unsigned char) (*(c++))); - } - printf("\n"); -} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/command.c b/board/MAI/bios_emulator/scitech/src/v86bios/command.c deleted file mode 100644 index e2bce6d..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/command.c +++ /dev/null @@ -1,38 +0,0 @@ -#include -#include -#include -#include - -#define PROMPT ">" - - -void -getline(char *buf,int *num,int max_num) -{ - static int line_len = 0; - static char *line = NULL; - static char *line_pointer = NULL; - static int len = 0; - int tmp_len; - char *buff; - - if (len <= 0) { - buff = readline(PROMPT); - add_history(buff); - - if ((tmp_len = strlen(buff)) > line_len) { - free(line); - line = malloc(tmp_len); - line_len = tmp_len; - } - sprintf(line,"%s\n",buff); - free(buff); - line_pointer = line; - len = strlen(line); - } - - *num = max_num > len? len : max_num; - strncpy(buf,line_pointer,*num); - line_pointer = line_pointer + *num; - len = len - *num; -} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/console.c b/board/MAI/bios_emulator/scitech/src/v86bios/console.c deleted file mode 100644 index 5e9c924..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/console.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 1999 Egbert Eich - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of the authors not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. The authors makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#include -#include -#include -#include -#include -#include -#include "debug.h" -#include "v86bios.h" - -console -open_console(void) -{ - int fd; - int VTno; - char VTname[11]; - console Con = {-1,-1}; - struct vt_stat vts; - - if (NO_CONSOLE) - return Con; - - if ((fd = open("/dev/tty0",O_WRONLY,0)) < 0) - return Con; - - if ((ioctl(fd, VT_OPENQRY, &VTno) < 0) || (VTno == -1)) { - fprintf(stderr,"cannot get a vt\n"); - return Con; - } - - close(fd); - sprintf(VTname,"/dev/tty%i",VTno); - - if ((fd = open(VTname, O_RDWR|O_NDELAY, 0)) < 0) { - fprintf(stderr,"cannot open console\n"); - return Con; - } - - if (ioctl(fd, VT_GETSTATE, &vts) == 0) - Con.vt = vts.v_active; - - if (ioctl(fd, VT_ACTIVATE, VTno) != 0) { - fprintf(stderr,"cannot activate console\n"); - close(fd); - return Con; - } - if (ioctl(fd, VT_WAITACTIVE, VTno) != 0) { - fprintf(stderr,"wait for active console failed\n"); - close(fd); - return Con; - } -#if 0 - if (ioctl(fd, KDSETMODE, KD_GRAPHICS) < 0) { - close(fd); - return Con; - } -#endif - Con.fd = fd; - return Con; -} - -void -close_console(console Con) -{ - if (Con.fd == -1) - return; - -#if 0 - ioctl(Con.fd, KDSETMODE, KD_TEXT); -#endif - if (Con.vt >=0) - ioctl(Con.fd, VT_ACTIVATE, Con.vt); - - close(Con.fd); -} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/debug.h b/board/MAI/bios_emulator/scitech/src/v86bios/debug.h deleted file mode 100644 index c5c906b..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/debug.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 1999 Egbert Eich - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of the authors not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. The authors makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -/*#define V86BIOS_DEBUG */ - -/* - * uncomment the following if needed - * should be command line options - */ - -#define PRINT_PORT 0 -#define IO_STATISTICS 0 -#define PRINT_IRQ 0 -#define PRINT_PCI 1 -#define PRINT_IP 0 /* print IP address with PIO information */ -#define TRACE 0 /* turn on debugger in x86emu */ - /* requires x86emu compiled with -DDEBUG */ - -/* - * these should not be here. - * Should be converted to command line options. - */ -#define CONFIG_ACTIVE_ONLY 0 -#define CONFIG_ACTIVE_DEVICE 1 -#define SAVE_BIOS 0 -#define MAP_SYS_BIOS 1 -#define RESORT 1 -#define FIX_ROM 0 -#define NO_CONSOLE 0 -#define SHOW_ALL_DEV 0 -#define VERBOSE 0 - -/*#define V_BIOS 0xe0000 */ -/*#define V_BIOS 0xe4000 */ - - -#if (PRINT_IO == 1) && (PRINT_PORT == 0) -# define PRINT_IO 0 -#endif -#if (IO_STATISTICS == 1) && (PRINT_PORT == 0) -# define IO_STATISTICS 0 -#endif diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards b/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards deleted file mode 100644 index 943d44e..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards +++ /dev/null @@ -1,76 +0,0 @@ -What I had to do to make cards happy: - -1. Tseng ET4000 W32P -This card wants to call the original system BIOS video routines. -It sets the int 0x42 vector to F000:F065, the entry point to the -system bios video routines. -CAVE: don't catch int 0x42 and use the vbios int 0x10 routines. -At early stage during initialization they call int 0x42. This -causes an infinite loop. - -2. ATi Mach64 Rage IIc AGP -This card does similar things like the Tseng ET4000 W32P. -However it doesn't have the problem with the ininite loop. - -3. Elsa Victory II-A16 AGP Banshee -This card is very clever: It knows it is an AGP card. Therefore -it knows it is behind a PCI-PCI bridge. It also knows that noone -else is behind this bridge. Therefore it start reprogramming the -bridge! For this it assumes the AGP bridge is on bus 1. - -4. Elsa Gloria Synergy 8 ViVo AGP PM2 -This card likes to see a complete interrupt vector table. If -we fill this table with 0 the VBIOS detects this and quits -initialization. - -5. Dimond Viper 330 AGP NVIDIA Riva 128. -This card has a similar problem like the Elsa Gloria. It wants -to read the system BIOS date at 0xffffd. - -6. Matrox Mystique PCI -This card reads the IO port 0x62. If it doesn't like what it sees -it loops forever. To keep the card happy put 0xfc into 0xffffe. -This location holds the system model id. 0xfc means IBM-AT. - One can make an interesting observation: this card likes to know -with whom it has to share the system. Therefore it accesses PCI -config space of all the other cards. It does this bypassing the -PCI BIOS by reading the PCI access ports directly. - -7. Matrox G100 AGP -This card has the same problem as the Mystique. - -Apperantly this works now. However not all combinations of cards are -checked, yet. - -Further notes: -the IO register 0x42-0x43 as well as 0x61-0x63 are of special interest -for many graphic cards. They should be emulated. -The so called "Industry Standard BIOS Entry Points" to int 0x42 (0xFF065) -and to int 0x1a (0xFFE6E) should be filled with useful code. This code -needs to return as if it was called as int. -The subvendor ID PCI registers might cause problems. On some chipsets -they are programmed in a non-obivous non-PCI conformant way. -V_Bioses are seen to modify the following int: -0x10 (default video), 0x1f(font table), 0x42(copy of default video), -0x43 (??), 0x6d (copy of default video - same as 0x10?) - -TODO: -Int 0x6d needs to be done. -All interrupts where there is no default industry standard entry point -should point to an unused location in the 0xF000 segmant (possibly -0xF0000). This way they could be trapped. A trap handler for -a. int 0x42 and int 0x1a needs to be implemented. -The default "industry entry point" for video and PCI (0xFFE6E) should -also be implemented. (any others?) They should either be routed to -int 0x42(0x6d?) (video) and 0x1A (PCI) or some other interrupts to -trap them. Mapping of system bios might not be a good idea. Maybe -the system bios area should just be filled with "hlt" to trap any -access there. -Handling of timer IO registers 0x42, 0x43 and IO registers 0x61, 0x62. - -Find documentation: -- on interrupt vector table -- on industry standard entry points to the system bios -- on IO registers 0x61 and 0x62 - - diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/hexdump b/board/MAI/bios_emulator/scitech/src/v86bios/hexdump deleted file mode 100644 index 4f359e5..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/hexdump +++ /dev/null @@ -1,3 +0,0 @@ -"%06.6_ax " 16/1 "%02x " -" " 16/1 "%_p" -"\n" diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/int.c b/board/MAI/bios_emulator/scitech/src/v86bios/int.c deleted file mode 100644 index 3504c6c..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/int.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright 1999 Egbert Eich - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of the authors not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. The authors makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#include "debug.h" -#if defined(__alpha__) || defined (__ia64__) -#include -#endif - -#include "v86bios.h" -#include "AsmMacros.h" -#include "pci.h" - -static int int1A_handler(struct regs86 *regs); -static int int42_handler(int num, struct regs86 *regs); - -int -int_handler(int num, struct regs86 *regs) -{ - switch (num) { - case 0x10: - case 0x42: - return (int42_handler(num,regs)); - case 0x1A: - return (int1A_handler(regs)); - default: - return 0; - } - return 0; -} - -static int -int42_handler(int num,struct regs86 *regs) -{ - unsigned char c; - CARD32 val; - - i_printf("int 0x%x: ax:0x%lx bx:0x%lx cx:0x%lx dx:0x%lx\n",num, - regs->eax,regs->ebx, regs->ecx, regs->edx); - - /* - * video bios has modified these - - * leave it to the video bios to do this - */ - - val = getIntVect(num); - if (val != 0xF000F065) - return 0; - - if ((regs->ebx & 0xff) == 0x32) { - switch (regs->eax & 0xFFFF) { - case 0x1200: - i_printf("enabling video\n"); - c = inb(0x3cc); - c |= 0x02; - outb(0x3c2,c); - return 1; - case 0x1201: - i_printf("disabling video\n"); - c = inb(0x3cc); - c &= ~0x02; - outb(0x3c2,c); - return 1; - default: - } - } - if (num == 0x42) - return 1; - else - return 0; -} - -#define SUCCESSFUL 0x00 -#define DEVICE_NOT_FOUND 0x86 -#define BAD_REGISTER_NUMBER 0x87 - -static int -int1A_handler(struct regs86 *regs) -{ - CARD32 Slot; - PciStructPtr pPci; - - if (! CurrentPci) return 0; /* oops */ - - i_printf("int 0x1a: ax=0x%lx bx=0x%lx cx=0x%lx dx=0x%lx di=0x%lx" - " si=0x%lx\n", regs->eax,regs->ebx,regs->ecx,regs->edx, - regs->edi,regs->esi); - switch (regs->eax & 0xFFFF) { - case 0xb101: - regs->eax &= 0xFF00; /* no config space/special cycle support */ - regs->edx = 0x20494350; /* " ICP" */ - regs->ebx = 0x0210; /* Version 2.10 */ - regs->ecx &= 0xFF00; - regs->ecx |= (pciMaxBus & 0xFF); /* Max bus number in system */ - regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ - i_printf("ax=0x%lx dx=0x%lx bx=0x%lx cx=0x%lx flags=0x%lx\n", - regs->eax,regs->edx,regs->ebx,regs->ecx,regs->eflags); - return 1; - case 0xb102: - if (((regs->edx & 0xFFFF) == CurrentPci->VendorID) && - ((regs->ecx & 0xFFFF) == CurrentPci->DeviceID) && - (regs->esi == 0)) { - regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); - regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ - regs->ebx = pciSlotBX(CurrentPci); - } - else if (Config.ShowAllDev && - (pPci = findPciDevice(regs->edx,regs->ecx,regs->esi)) != NULL) { - regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); - regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ - regs->ebx = pciSlotBX(pPci); - } else { - regs->eax = (regs->eax & 0x00FF) | (DEVICE_NOT_FOUND << 8); - regs->eflags |= ((unsigned long)0x01); /* set carry flag */ - } - i_printf("ax=0x%lx bx=0x%lx flags=0x%lx\n", - regs->eax,regs->ebx,regs->eflags); - return 1; - case 0xb103: - if (((regs->ecx & 0xFF) == CurrentPci->Interface) && - (((regs->ecx & 0xFF00) >> 8) == CurrentPci->SubClass) && - (((regs->ecx & 0xFFFF0000) >> 16) == CurrentPci->BaseClass) && - ((regs->esi & 0xff) == 0)) { - regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); - regs->ebx = pciSlotBX(CurrentPci); - regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ - } - else if (Config.ShowAllDev - && (pPci = findPciClass(regs->ecx & 0xFF, (regs->ecx & 0xff00) >> 8, - (regs->ecx & 0xffff0000) >> 16, regs->esi)) != NULL) { - regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); - regs->ebx = pciSlotBX(pPci); - regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ - } else { - regs->eax = (regs->eax & 0x00FF) | (DEVICE_NOT_FOUND << 8); - regs->eflags |= ((unsigned long)0x01); /* set carry flag */ - } - i_printf("ax=0x%lx flags=0x%lx\n",regs->eax,regs->eflags); - return 1; - case 0xb108: - i_printf("Slot=0x%x\n",CurrentPci->Slot.l); - if ((Slot = findPci(regs->ebx))) { - regs->ecx &= 0xFFFFFF00; - regs->ecx |= PciRead8(regs->edi,Slot); - regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); - regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ - } else { - regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); - regs->eflags |= ((unsigned long)0x01); /* set carry flag */ - } - i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n", - regs->eax,regs->ecx,regs->eflags); - return 1; - case 0xb109: - i_printf("Slot=0x%x\n",CurrentPci->Slot.l); - if ((Slot = findPci(regs->ebx))) { - regs->ecx &= 0xFFFF0000; - regs->ecx |= PciRead16(regs->edi,Slot); - regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); - regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ - } else { - regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); - regs->eflags |= ((unsigned long)0x01); /* set carry flag */ - } - i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n", - regs->eax,regs->ecx,regs->eflags); - return 1; - case 0xb10a: - i_printf("Slot=0x%x\n",CurrentPci->Slot.l); - if ((Slot = findPci(regs->ebx))) { - regs->ecx &= 0; - regs->ecx |= PciRead32(regs->edi,Slot); - regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); - regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ - } else { - regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); - regs->eflags |= ((unsigned long)0x01); /* set carry flag */ - } - i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n", - regs->eax,regs->ecx,regs->eflags); - return 1; - case 0xb10b: - i_printf("Slot=0x%x\n",CurrentPci->Slot.l); - if ((Slot = findPci(regs->ebx))) { - PciWrite8(regs->edi,(CARD8)regs->ecx,Slot); - regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); - regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ - } else { - regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); - regs->eflags |= ((unsigned long)0x01); /* set carry flag */ - } - i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags); - return 1; - case 0xb10c: - i_printf("Slot=0x%x\n",CurrentPci->Slot.l); - if ((Slot = findPci(regs->ebx))) { - PciWrite16(regs->edi,(CARD16)regs->ecx,Slot); - regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); - regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ - } else { - regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); - regs->eflags |= ((unsigned long)0x01); /* set carry flag */ - } - i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags); - return 1; - case 0xb10d: - i_printf("Slot=0x%x\n",CurrentPci->Slot.l); - if ((Slot = findPci(regs->ebx))) { - PciWrite32(regs->edi,(CARD32)regs->ecx,Slot); - regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); - regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ - } else { - regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); - regs->eflags |= ((unsigned long)0x01); /* set carry flag */ - } - i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags); - return 1; - default: - return 0; - } -} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/io.c b/board/MAI/bios_emulator/scitech/src/v86bios/io.c deleted file mode 100644 index f35b43e..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/io.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright 1999 Egbert Eich - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of the authors not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. The authors makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#include "debug.h" - -#include -#if defined(__alpha__) || defined (__ia64__) -#include -#endif -#include "AsmMacros.h" -#include "v86bios.h" -#include "pci.h" - -int r_inb = 0, r_inw = 0, r_inl = 0, r_outb = 0, r_outw = 0, r_outl = 0; -int in_b = 0, in_w = 0, in_l = 0, out_b = 0, out_w = 0, out_l = 0; - - -int -port_rep_inb(CARD16 port, CARD8 *base, int d_f, CARD32 count) -{ - register int inc = d_f ? -1 : 1; - CARD8 *dst = base; - - p_printf(" rep_insb(%#x) %d bytes at %p %s", - port, count, base, d_f?"up":"down"); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - - r_inb++; - while (count--) { - *dst = inb(port); - dst += inc; - } - return (dst-base); -} - -int -port_rep_inw(CARD16 port, CARD16 *base, int d_f, CARD32 count) -{ - register int inc = d_f ? -1 : 1; - CARD16 *dst = base; - - p_printf(" rep_insw(%#x) %d bytes at %p %s", - port, count, base, d_f?"up":"down"); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - - r_inw++; - while (count--) { - *dst = inw(port); - dst += inc; - } - return (dst-base); -} - -int -port_rep_inl(CARD16 port, CARD32 *base, int d_f, CARD32 count) -{ - register int inc = d_f ? -1 : 1; - CARD32 *dst = base; - - p_printf(" rep_insl(%#x) %d bytes at %p %s", - port, count, base, d_f?"up":"down"); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - - r_inl++; - while (count--) { - *dst = inl(port); - dst += inc; - } - return (dst-base); -} - -int -port_rep_outb(CARD16 port, CARD8 *base, int d_f, CARD32 count) -{ - register int inc = d_f ? -1 : 1; - CARD8 *dst = base; - - p_printf(" rep_outb(%#x) %d bytes at %p %s", - port, count, base, d_f?"up":"down"); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - - r_outb++; - while (count--) { - outb(port,*dst); - dst += inc; - } - return (dst-base); -} - -int -port_rep_outw(CARD16 port, CARD16 *base, int d_f, CARD32 count) -{ - register int inc = d_f ? -1 : 1; - CARD16 *dst = base; - - p_printf(" rep_outw(%#x) %d bytes at %p %s", - port, count, base, d_f?"up":"down"); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - - r_outw++; - while (count--) { - outw(port,*dst); - dst += inc; - } - return (dst-base); -} - -int -port_rep_outl(CARD16 port, CARD32 *base, int d_f, CARD32 count) -{ - register int inc = d_f ? -1 : 1; - CARD32 *dst = base; - - p_printf(" rep_outl(%#x) %d bytes at %p %s", - port, count, base, d_f?"up":"down"); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - - r_outl++; - while (count--) { - outl(port,*dst); - dst += inc; - } - return (dst-base); -} - -CARD8 -p_inb(CARD16 port) -{ - CARD8 val = 0; - in_b++; - val = inb(port); - p_printf(" inb(%#x) = %2.2x",port,val); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - - return val; -} - -CARD16 -p_inw(CARD16 port) -{ - CARD16 val = 0; - in_w++; - val = inw(port); - p_printf(" inw(%#x) = %4.4x",port,val); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - - return val; -} - -CARD32 -p_inl(CARD16 port) -{ - CARD32 val = 0; - in_l++; -#ifdef NEED_PCI_IO - if (cfg1in(port,&val)) - return val; - else -#endif - val = inl(port); - p_printf(" inl(%#x) = %8.8x",port,val); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - - return val; -} - -void -p_outb(CARD16 port, CARD8 val) -{ - out_b++; - p_printf(" outb(%#x, %2.2x)",port,val); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - - outb(port,val); -} - -void -p_outw(CARD16 port, CARD16 val) -{ - out_w++; - p_printf(" outw(%#x, %4.4x)",port,val); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - - outw(port,val); -} - -void -p_outl(CARD16 port, CARD32 val) -{ - out_l++; - p_printf(" outl(%#x, %8.8x)",port,val); - if (Config.PrintIp) - p_printf(" %x\n",getIP()); - else p_printf("\n"); - -#ifdef NEED_PCI_IO - if (cfg1out(port,val)) - return; -#endif - outl(port,val); -} - -void -io_statistics(void) -{ - p_printf("rep: inb: %i, inw: %i, inl: %i, outb: %i, outw: %i, outl: %i\n", - r_inb,r_inw,r_inl,r_outb,r_outw,r_outl); - p_printf("inb: %i, inw: %i, inl: %i, outb: %i, outw: %i, outl: %i\n", - in_b,in_w,in_l,out_b,out_w,out_l); -} - -void -clear_stat(void) -{ - r_inb = r_inw = r_inl = r_outb = r_outw = r_outl = 0; - in_b = in_w = in_l = out_b = out_w = out_l = 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/lex.l b/board/MAI/bios_emulator/scitech/src/v86bios/lex.l deleted file mode 100644 index 3a3391c..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/lex.l +++ /dev/null @@ -1,79 +0,0 @@ -%{ -#include "parser.h" - -#include -#include - - void getline(char *buf,int *num,int max_num); - -#define YY_INPUT(buf,result,max_size) {\ - getline(buf,&result,max_size);\ - } - - void - yyerror (char *s) - { - printf ("%s\n", s); - } - -%} - -DIGIT [0-9a-fA-F] - -%% - -"0x"?{DIGIT}+ { yylval = strtol(yytext,NULL,0); return TOK_NUM; } -"ax" { return TOK_REG_AX; } -"bx" { return TOK_REG_BX; } -"cx" { return TOK_REG_CX; } -"dx" { return TOK_REG_DX; } -"di" { return TOK_REG_SI; } -"si" { return TOK_REG_DI; } -"ds" { return TOK_SEG_DS; } -"es" { return TOK_SEG_ES; } -":" { return TOK_SEP;} -"$"{DIGIT}{1,2} { yylval = strtol(yytext+1,NULL,0); return TOK_VAR; } -"$mem" { return TOK_VAR_MEM; } -[ \t]+ -"#".*[\n] { return TOK_END; } -"boot" { return TOK_COMMAND_BOOT; } -"do" { return TOK_COMMAND_EXEC; } -"\"".*"\"" { yylval = (unsigned long) yytext; return TOK_STRING; } -"byte" { return TOK_BYTE; } -"word" { return TOK_WORD; } -"long" { return TOK_LONG; } -"setmem" { return TOK_COMMAND_MEMSET; } -"dumpmem" { return TOK_COMMAND_MEMDUMP; } -"quit" { return TOK_COMMAND_QUIT; } -"\n" { return TOK_END; } -"select" { return TOK_SELECT; } -"isa" { return TOK_ISA; } -"pci" { return TOK_PCI; } -"pport" { return TOK_PRINT_PORT; } -"iostat" { return TOK_IOSTAT; } -"pirq" { return TOK_PRINT_IRQ; } -"ppci" { return TOK_PPCI; } -"pip" { return TOK_PIP; } -"trace" { return TOK_TRACE; } -"on" { return TOK_ON; } -"off" { return TOK_OFF; } -"verbose" { return TOK_VERBOSE; } -"log" { return TOK_LOG; } -"print" { return TOK_STDOUT; } -"clstat" { return TOK_CLSTAT; } -"hlt" { return TOK_HLT; } -"del" { return TOK_DEL; } -"ioperm" { return TOK_IOPERM; } -"lpci" { return TOK_DUMP_PCI; } -"bootbios" { return TOK_BOOT_BIOS; } -"?" { return '?'; } -. { return TOK_ERROR; } - -%% - - - - - - - diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/main.c b/board/MAI/bios_emulator/scitech/src/v86bios/main.c deleted file mode 100644 index 15f9115..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/main.c +++ /dev/null @@ -1,616 +0,0 @@ -/* - * Copyright 1999 Egbert Eich - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of the authors not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. The authors makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#define DELETE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(__alpha__) || defined (__ia64__) -#include -#elif defined(HAVE_SYS_PERM) -#include -#endif -#include "debug.h" -#include "v86bios.h" -#include "pci.h" -#include "AsmMacros.h" - -#define SIZE 0x100000 -#define VRAM_START 0xA0000 -#define VRAM_SIZE 0x1FFFF -#define V_BIOS_SIZE 0x1FFFF -#define BIOS_START 0x7C00 /* default BIOS entry */ - -/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0, 0xf4 }; */ -#define VB_X(x) (V_BIOS >> x) & 0xFF -CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xf4 }; -/*CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xb8, 0x03, 0x00, */ -/*0xcd, 0x10, 0xf4 }; */ -/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0 ,0xf4 }; */ - -static void sig_handler(int); -static int map(void); -static void unmap(void); -static void bootBIOS(CARD16 ax); -static int map_vram(void); -static void unmap_vram(void); -static int copy_vbios(void); -static int copy_sys_bios(void); -static void save_bios_to_file(void); -static int setup_system_bios(void); -static void setup_int_vect(void); -static int chksum(CARD8 *start); -static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax); - -void loadCodeToMem(unsigned char *ptr, CARD8 *code); -void dprint(unsigned long start, unsigned long size); - -static int vram_mapped = 0; -static CARD8 save_msr; -static CARD8 save_pos102; -static CARD8 save_vse; -static CARD8 save_46e8; -console Console; -struct config Config; - - -int -main(void) -{ - int Active_is_Pci = 0; -#ifdef DELETE - Config.PrintPort = PRINT_PORT; - Config.IoStatistics = IO_STATISTICS; - Config.PrintIrq = PRINT_IRQ; - Config.PrintPci = PRINT_PCI; - Config.ShowAllDev = SHOW_ALL_DEV; - Config.PrintIp = PRINT_IP; - Config.SaveBios = SAVE_BIOS; - Config.Trace = TRACE; - Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY; - Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE; - Config.MapSysBios = MAP_SYS_BIOS; - Config.Resort = RESORT; - Config.FixRom = FIX_ROM; - Config.NoConsole = NO_CONSOLE; - Config.Verbose = VERBOSE; - - if (!map()) - exit(1); - - if (!setup_system_bios()) - exit(1); - - iopl(3); - setup_io(); - - scan_pci(); - if (!CurrentPci && !Config.ConfigActiveDevice && !Config.ConfigActiveOnly) - exit (1); -#endif - Console = open_console(); - - if (Config.ConfigActiveOnly) { - CARD16 ax; - int activePci = 0; - int error = 0; - - while (CurrentPci) { - if (CurrentPci->active) { - activePci = 1; - if (!(mapPciRom(NULL) && chksum((CARD8*)V_BIOS))) - error = 1; - break; - } - CurrentPci = CurrentPci->next; - } - ax = ((CARD16)(CurrentPci->bus) << 8) - | (CurrentPci->dev << 3) | (CurrentPci->func & 0x7); - P_printf("ax: 0x%x\n",ax); - setup_int_vect(); - if (!error && (activePci || copy_vbios())) { - - if (Config.SaveBios) save_bios_to_file(); - if (map_vram()) { - printf("initializing ISA\n"); - bootBIOS(0); - } - } - unmap_vram(); - sleep(1); - } else { - /* disable primary card */ - save_msr = inb(0x3CC); - save_vse = inb(0x3C3); - save_46e8 = inb(0x46e8); - save_pos102 = inb(0x102); - - signal(2,sig_handler); - signal(11,sig_handler); - - outb(0x3C2,~(CARD8)0x03 & save_msr); - outb(0x3C3,~(CARD8)0x01 & save_vse); - outb(0x46e8, ~(CARD8)0x08 & save_46e8); - outb(0x102, ~(CARD8)0x01 & save_pos102); - - pciVideoDisable(); - - while (CurrentPci) { - CARD16 ax; - - if (CurrentPci->active) { - Active_is_Pci = 1; - if (!Config.ConfigActiveDevice) { - CurrentPci = CurrentPci->next; - continue; - } - } - - EnableCurrent(); - - if (CurrentPci->active) { - outb(0x102, save_pos102); - outb(0x46e8, save_46e8); - outb(0x3C3, save_vse); - outb(0x3C2, save_msr); - } - - /* clear interrupt vectors */ - setup_int_vect(); - - ax = ((CARD16)(CurrentPci->bus) << 8) - | (CurrentPci->dev << 3) | (CurrentPci->func & 0x7); - P_printf("ax: 0x%x\n",ax); - - if (!((mapPciRom(NULL) && chksum((CARD8*)V_BIOS)) - || (CurrentPci->active && copy_vbios()))) { - CurrentPci = CurrentPci->next; - continue; - } - if (!map_vram()) { - CurrentPci = CurrentPci->next; - continue; - } - if (Config.SaveBios) save_bios_to_file(); - printf("initializing PCI bus: %i dev: %i func: %i\n",CurrentPci->bus, - CurrentPci->dev,CurrentPci->func); - bootBIOS(ax); - unmap_vram(); - - CurrentPci = CurrentPci->next; - } - - /* We have an ISA device - configure if requested */ - if (!Active_is_Pci && Config.ConfigActiveDevice) { - pciVideoDisable(); - - outb(0x102, save_pos102); - outb(0x46e8, save_46e8); - outb(0x3C3, save_vse); - outb(0x3C2, save_msr); - - setup_int_vect(); - if (copy_vbios()) { - - if (Config.SaveBios) save_bios_to_file(); - if (map_vram()) { - printf("initializing ISA\n"); - bootBIOS(0); - } - } - - unmap_vram(); - sleep(1); - } - - pciVideoRestore(); - - outb(0x102, save_pos102); - outb(0x46e8, save_46e8); - outb(0x3C3, save_vse); - outb(0x3C2, save_msr); - } - - close_console(Console); -#ifdef DELETE - iopl(0); - unmap(); - - printf("done !\n"); -#endif - if (Config.IoStatistics) - io_statistics(); -#ifdef DELETE - exit(0); -#endif -} - -int -map(void) -{ - void* mem; - - mem = mmap(0, (size_t)SIZE, - PROT_EXEC | PROT_READ | PROT_WRITE, - MAP_FIXED | MAP_PRIVATE | MAP_ANON, - -1, 0 ); - if (mem != 0) { - perror("anonymous map"); - return (0); - } - memset(mem,0,SIZE); - - loadCodeToMem((unsigned char *) BIOS_START, code); - return (1); -} - -static void -unmap(void) -{ - munmap(0,SIZE); -} - -static void -bootBIOS(CARD16 ax) -{ - i86biosRegs bRegs; -#ifdef V86BIOS_DEBUG - printf("starting BIOS\n"); -#endif - setup_bios_regs(&bRegs, ax); - do_x86(BIOS_START,&bRegs); -#ifdef V86BIOS_DEBUG - printf("done\n"); -#endif -} - -static int -map_vram(void) -{ - int mem_fd; - -#ifdef __ia64__ - if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) -#else - if ((mem_fd = open(MEM_FILE,O_RDWR))<0) -#endif - { - perror("opening memory"); - return 0; - } - -#ifndef __alpha__ - if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE, - PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, - mem_fd, VRAM_START) == (void *) -1) -#else - if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */ - if (!_bus_base_sparse()) sparse_shift = 0; - if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift), - PROT_READ | PROT_WRITE, - MAP_SHARED, - mem_fd, (VRAM_START << sparse_shift) - | _bus_base_sparse())) == (void *) -1) -#endif - { - perror("mmap error in map_hardware_ram"); - close(mem_fd); - return (0); - } - vram_mapped = 1; - close(mem_fd); - return (1); -} - -static void -unmap_vram(void) -{ - if (!vram_mapped) return; - - munmap((void*)VRAM_START,VRAM_SIZE); - vram_mapped = 0; -} - -static int -copy_vbios(void) -{ - int mem_fd; - unsigned char *tmp; - int size; - - if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { - perror("opening memory"); - return (0); - } - - if (lseek(mem_fd,(off_t) V_BIOS, SEEK_SET) != (off_t) V_BIOS) { - fprintf(stderr,"Cannot lseek\n"); - goto Error; - } - tmp = (unsigned char *)malloc(3); - if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) { - fprintf(stderr,"Cannot read\n"); - goto Error; - } - if (lseek(mem_fd,(off_t) V_BIOS,SEEK_SET) != (off_t) V_BIOS) - goto Error; - - if (*tmp != 0x55 || *(tmp+1) != 0xAA ) { -#ifdef DEBUG - dprint((unsigned long)tmp,0x100); -#endif - fprintf(stderr,"No bios found at: 0x%x\n",V_BIOS); - goto Error; - } - size = *(tmp+2) * 512; - - if (read(mem_fd, (char *)V_BIOS, (size_t) size) != (size_t) size) { - fprintf(stderr,"Cannot read\n"); - goto Error; - } - free(tmp); - close(mem_fd); - if (!chksum((CARD8)V_BIOS)) - return (0); - - return (1); - -Error: - perror("v_bios"); - close(mem_fd); - return (0); -} - -static int -copy_sys_bios(void) -{ -#define SYS_BIOS 0xF0000 - int mem_fd; - - if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { - perror("opening memory"); - return (0); - } - - if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS) - goto Error; - if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF) - goto Error; - - close(mem_fd); - return (1); - -Error: - perror("sys_bios"); - close(mem_fd); - return (0); -} - -void -loadCodeToMem(unsigned char *ptr, CARD8 code[]) -{ - int i; - CARD8 val; - - for ( i=0;;i++) { - val = code[i]; - *ptr++ = val; - if (val == 0xf4) break; - } - return; -} - -void -dprint(unsigned long start, unsigned long size) -{ - int i,j; - char *c = (char *)start; - - for (j = 0; j < (size >> 4); j++) { - char *d = c; - printf("\n0x%lx: ",(unsigned long)c); - for (i = 0; i<16; i++) - printf("%2.2x ",(unsigned char) (*(c++))); - c = d; - for (i = 0; i<16; i++) { - printf("%c",((((CARD8)(*c)) > 32) && (((CARD8)(*c)) < 128)) ? - (unsigned char) (*(c)): '.'); - c++; - } - } - printf("\n"); -} - -static void -save_bios_to_file(void) -{ - static int num = 0; - int size, count; - char file_name[256]; - int fd; - - sprintf(file_name,"bios_%i.fil",num); - if ((fd = open(file_name,O_WRONLY | O_CREAT | O_TRUNC,00644)) == -1) - return; - size = (*(unsigned char*)(V_BIOS + 2)) * 512; -#ifdef V86BIOS_DEBUG - dprint(V_BIOS,20); -#endif - if ((count = write(fd,(void *)(V_BIOS),size)) != size) - fprintf(stderr,"only saved %i of %i bytes\n",size,count); - num++; -} - -static void -sig_handler(int unused) -{ - fflush(stdout); - fflush(stderr); - - /* put system back in a save state */ - unmap_vram(); - pciVideoRestore(); - outb(0x102, save_pos102); - outb(0x46e8, save_46e8); - outb(0x3C3, save_vse); - outb(0x3C2, save_msr); - - close_console(Console); - iopl(0); - unmap(); - - exit(1); -} - -/* - * For initialization we just pass ax to the BIOS. - * PCI BIOSes need this. All other register are set 0. - */ -static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax) -{ - regs->ax = ax; - regs->bx = 0; - regs->cx = 0; - regs->dx = 0; - regs->es = 0; - regs->di = 0; -} - -/* - * here we are really paranoid about faking a "real" - * BIOS. Most of this information was pulled from - * dosem. - */ -static void -setup_int_vect(void) -{ - const CARD16 cs = 0x0000; - const CARD16 ip = 0x0; - int i; - - /* let the int vects point to the SYS_BIOS seg */ - for (i=0; i<0x80; i++) { - ((CARD16*)0)[i<<1] = ip; - ((CARD16*)0)[(i<<1)+1] = cs; - } - /* video interrupts default location */ - ((CARD16*)0)[(0x42<<1)+1] = 0xf000; - ((CARD16*)0)[0x42<<1] = 0xf065; - ((CARD16*)0)[(0x10<<1)+1] = 0xf000; - ((CARD16*)0)[0x10<<1] = 0xf065; - /* video param table default location (int 1d) */ - ((CARD16*)0)[(0x1d<<1)+1] = 0xf000; - ((CARD16*)0)[0x1d<<1] = 0xf0A4; - /* font tables default location (int 1F) */ - ((CARD16*)0)[(0x1f<<1)+1] = 0xf000; - ((CARD16*)0)[0x1f<<1] = 0xfa6e; - - /* int 11 default location */ - ((CARD16*)0)[(0x11<1)+1] = 0xf000; - ((CARD16*)0)[0x11<<1] = 0xf84d; - /* int 12 default location */ - ((CARD16*)0)[(0x12<<1)+1] = 0xf000; - ((CARD16*)0)[0x12<<1] = 0xf841; - /* int 15 default location */ - ((CARD16*)0)[(0x15<<1)+1] = 0xf000; - ((CARD16*)0)[0x15<<1] = 0xf859; - /* int 1A default location */ - ((CARD16*)0)[(0x1a<<1)+1] = 0xf000; - ((CARD16*)0)[0x1a<<1] = 0xff6e; - /* int 05 default location */ - ((CARD16*)0)[(0x05<<1)+1] = 0xf000; - ((CARD16*)0)[0x05<<1] = 0xff54; - /* int 08 default location */ - ((CARD16*)0)[(0x8<<1)+1] = 0xf000; - ((CARD16*)0)[0x8<<1] = 0xfea5; - /* int 13 default location (fdd) */ - ((CARD16*)0)[(0x13<<1)+1] = 0xf000; - ((CARD16*)0)[0x13<<1] = 0xec59; - /* int 0E default location */ - ((CARD16*)0)[(0xe<<1)+1] = 0xf000; - ((CARD16*)0)[0xe<<1] = 0xef57; - /* int 17 default location */ - ((CARD16*)0)[(0x17<<1)+1] = 0xf000; - ((CARD16*)0)[0x17<<1] = 0xefd2; - /* fdd table default location (int 1e) */ - ((CARD16*)0)[(0x1e<<1)+1] = 0xf000; - ((CARD16*)0)[0x1e<<1] = 0xefc7; -} - -static int -setup_system_bios(void) -{ - char *date = "06/01/99"; - char *eisa_ident = "PCI/ISA"; - -#if MAP_SYS_BIOS - if (!copy_sys_bios()) return 0; - return 1; -#endif -/* memset((void *)0xF0000,0xf4,0xfff7); */ - - /* - * we trap the "industry standard entry points" to the BIOS - * and all other locations by filling them with "hlt" - * TODO: implement hlt-handler for these - */ - memset((void *)0xF0000,0xf4,0x10000); - - /* - * TODO: we should copy the fdd table (0xfec59-0xfec5b) - * the video parameter table (0xf0ac-0xf0fb) - * and the font tables (0xfa6e-0xfe6d) - * from the original bios here - */ - - /* set bios date */ - strcpy((char *)0xFFFF5,date); - /* set up eisa ident string */ - strcpy((char *)0xFFFD9,eisa_ident); - /* write system model id for IBM-AT */ - ((char *)0)[0xFFFFE] = 0xfc; - - return 1; -} - -static int -chksum(CARD8 *start) -{ - CARD16 size; - CARD8 val = 0; - int i; - - size = *(start+2) * 512; - for (i = 0; i= 0xA0000 && addr <= 0xBFFFF) { - addr -= 0xA0000; - shift = (addr & 0x3) * 8; - result = *(vuip) ((unsigned long)vram_map + (addr << sparse_shift)); - result >>= shift; - return 0xffUL & result; - } else -#endif - return rdb(addr); -} - -CARD16 -mem_rw(CARD32 addr) -{ - unsigned long result, shift; -#if 1 - if (addr >= 0xA0000 && addr <= 0xBFFFF) { - addr -= 0xA0000; - shift = (addr & 0x2) * 8; - result = *(vuip)((unsigned long)vram_map+(addr<>= shift; - return 0xffffUL & result; - } else -#endif - return rdw(addr); -} - -CARD32 -mem_rl(CARD32 addr) -{ - unsigned long result; -#if 1 - if (addr >= 0xA0000 && addr <= 0xBFFFF) { - addr -= 0xA0000; - result = *(vuip)((unsigned long)vram_map+(addr<= 0xA0000 && addr <= 0xBFFFF) { - addr -= 0xA0000; - *(vuip) ((unsigned long)vram_map + (addr << sparse_shift)) = b * 0x01010101; - mem_barrier(); - } else -#endif - wrb(addr,val); -} - -void -mem_ww(CARD32 addr, CARD16 val) -{ - unsigned int w = val & 0xffffU; -#if 1 - if (addr >= 0xA0000 && addr <= 0xBFFFF) { - addr -= 0xA0000; - *(vuip)((unsigned long)vram_map+(addr<= 0xA0000 && addr <= 0xBFFFF) { - addr -= 0xA0000; - *(vuip)((unsigned long)vram_map+(addr< -#include -#include "v86bios.h" -#include "pci.h" - -#define YYSTYPE unsigned long - -#define MAX_VAR 0x20 - - CARD32 var[MAX_VAR]; - CARD32 var_mem; - - -i86biosRegs regs = { 00 }; - -enum mem_type { BYTE, WORD, LONG, STRING }; -union mem_val { - CARD32 integer; - char *ptr; -} rec; - -struct mem { - enum mem_type type; - union mem_val val; - struct mem *next; -}; - - -struct device Device = {FALSE,NONE,{0}}; - -extern void yyerror(char *s); -extern int yylex( void ); - -static void boot(void); -static void dump_mem(CARD32 addr, int len); -static void exec_int(int num); -static void *add_to_list(enum mem_type type, union mem_val *rec, void *next); -static void do_list(struct mem *list, memType addr); -static char * normalize_string(char *ptr); -%} - -%token TOK_NUM -%token TOK_REG_AX -%token TOK_REG_BX -%token TOK_REG_CX -%token TOK_REG_DX -%token TOK_REG_DI -%token TOK_REG_SI -%token TOK_SEG_DS -%token TOK_SEG_ES -%token TOK_SEP -%token TOK_VAR -%token TOK_VAR_MEM -%token TOK_COMMAND_BOOT -%token TOK_COMMAND_EXEC -%token TOK_SELECT -%token TOK_STRING -%token TOK_MODIFIER_BYTE -%token TOK_MODIFIER_WORD -%token TOK_MODIFIER_LONG -%token TOK_MODIFIER_MEMSET -%token TOK_COMMAND_MEMSET -%token TOK_COMMAND_MEMDUMP -%token TOK_COMMAND_QUIT -%token TOK_ERROR -%token TOK_END -%token TOK_ISA -%token TOK_PCI -%token TOK_BYTE -%token TOK_WORD -%token TOK_LONG -%token TOK_PRINT_PORT -%token TOK_IOSTAT -%token TOK_PRINT_IRQ -%token TOK_PPCI -%token TOK_PIP -%token TOK_TRACE -%token TOK_ON -%token TOK_OFF -%token TOK_VERBOSE -%token TOK_LOG -%token TOK_LOGOFF -%token TOK_CLSTAT -%token TOK_STDOUT -%token TOK_HLT -%token TOK_DEL -%token TOK_IOPERM -%token TOK_DUMP_PCI -%token TOK_BOOT_BIOS -%% -input: | input line -line: end | com_reg | com_var | com_select - | com_boot | com_memset | com_memdump | com_quit - | com_exec | hlp | config | verbose | logging | print | clstat - | com_hlt | ioperm | list_pci | boot_bios - | error end { printf("unknown command\n"); } -; -end: TOK_END -; -com_reg: reg_off val end { *(CARD16*)$1 = $2 & 0xffff; } - | reg_seg TOK_SEP reg_off val end { - *(CARD16*)$1 = ($4 & 0xf0000) >> 4; - *(CARD16*)$3 = ($4 & 0x0ffff); - } - | reg_off '?' end { printf("0x%x\n",*(CARD16*)$1);} - | reg_seg TOK_SEP reg_off '?' end - { printf("0x%x:0x%x\n",*(CARD16*)$1, - *(CARD16*)$3); } -; -register_read: reg_seg TOK_SEP reg_off { $$ = (((*(CARD16*)$1) << 4) - | ((*(CARD16*)$3) & 0xffff)); - } - | reg_off { $$ = ((*(CARD16*)$1) & 0xffff); } -; -reg_off: TOK_REG_AX { $$ = (unsigned long)&(regs.ax); } - | TOK_REG_BX { $$ = (unsigned long)&(regs.bx); } - | TOK_REG_CX { $$ = (unsigned long)&(regs.cx); } - | TOK_REG_DX { $$ = (unsigned long)&(regs.dx); } - | TOK_REG_DI { $$ = (unsigned long)&(regs.di); } - | TOK_REG_SI { $$ = (unsigned long)&(regs.si); } -; -reg_seg: TOK_SEG_DS { $$ = (unsigned long)&(regs.ds); } - | TOK_SEG_ES { $$ = (unsigned long)&(regs.es); } -; -com_var: TOK_VAR_MEM '?' end { printf("var mem: 0x%x\n",var_mem); } - | TOK_VAR '?' end { if ($1 < MAX_VAR) - printf("var[%i]: 0x%x\n",(int)$1,var[$1]); - else - printf("var index %i out of range\n",(int)$1); } - | TOK_VAR_MEM val end { var_mem = $2; } - | TOK_VAR val end { if ($1 <= MAX_VAR) - var[$1] = $2; - else - printf("var index %i out of range\n",(int)$1); } - | TOK_VAR error end { printf("$i val\n"); } - | TOK_VAR_MEM error end { printf("$i val\n"); } -; -com_boot: TOK_COMMAND_BOOT end { boot(); } - TOK_COMMAND_BOOT error end { boot(); } -; -com_select: TOK_SELECT TOK_ISA end { Device.booted = FALSE; - Device.type = ISA; - CurrentPci = NULL; } - | TOK_SELECT TOK_PCI val TOK_SEP val TOK_SEP val end - { Device.booted = FALSE; - Device.type = PCI; - Device.loc.pci.bus = $3; - Device.loc.pci.dev = $5; - Device.loc.pci.func = $7; } - | TOK_SELECT '?' end - { switch (Device.type) { - case ISA: - printf("isa\n"); - break; - case PCI: - printf("pci: %x:%x:%x\n",Device.loc.pci.bus, - Device.loc.pci.dev, - Device.loc.pci.func); - break; - default: - printf("no device selected\n"); - break; - } - } - | TOK_SELECT error end { printf("select ? | isa " - "| pci:bus:dev:func\n"); } -; -com_quit: TOK_COMMAND_QUIT end { return 0; } - | TOK_COMMAND_QUIT error end { logoff(); return 0; } -; -com_exec: TOK_COMMAND_EXEC end { exec_int(0x10); } - | TOK_COMMAND_EXEC val end { exec_int($2); } - | TOK_COMMAND_EXEC error end { exec_int(0x10); } -; -com_memdump: TOK_COMMAND_MEMDUMP val val end { dump_mem($2,$3); } - | TOK_COMMAND_MEMDUMP error end { printf("memdump start len\n"); } - - -; -com_memset: TOK_COMMAND_MEMSET val list end { do_list((struct mem*)$3,$2);} - | TOK_COMMAND_MEMSET error end { printf("setmem addr [byte val] " - "[word val] [long val] " - "[\"string\"]\n"); } -; -list: { $$ = 0; } - | TOK_BYTE val list { rec.integer = $2; - $$ = (unsigned long)add_to_list(BYTE,&rec,(void*)$3); } - | TOK_WORD val list { rec.integer = $2; - $$ = (unsigned long) add_to_list(WORD,&rec,(void*)$3); } - | TOK_LONG val list { rec.integer = $2; - $$ = (unsigned long) add_to_list(LONG,&rec,(void*)$3); } - | TOK_STRING list { rec.ptr = (void*)$1; - $$ = (unsigned long) add_to_list(STRING,&rec,(void*)$2); } -; -val: TOK_VAR { if ($1 > MAX_VAR) { - printf("variable index out of range\n"); - $$=0; - } else - $$ = var[$1]; } - | TOK_NUM { $$ = $1; } - | register_read -; -bool: TOK_ON { $$ = 1; } - | TOK_OFF { $$ = 0; } -; -config: TOK_PRINT_PORT bool end { Config.PrintPort = $2; } - | TOK_PRINT_PORT '?' end { printf("print port %s\n", - Config.PrintPort?"on":"off"); } - | TOK_PRINT_PORT error end { printf("pport on | off | ?\n") } - | TOK_PRINT_IRQ bool end { Config.PrintIrq = $2; } - | TOK_PRINT_IRQ '?' end { printf("print irq %s\n", - Config.PrintIrq?"on":"off"); } - | TOK_PRINT_IRQ error end { printf("pirq on | off | ?\n") } - | TOK_PPCI bool end { Config.PrintPci = $2; } - | TOK_PPCI '?' end { printf("print PCI %s\n", - Config.PrintPci?"on":"off"); } - | TOK_PPCI error end { printf("ppci on | off | ?\n") } - | TOK_PIP bool end { Config.PrintIp = $2; } - | TOK_PIP '?' end { printf("printip %s\n", - Config.PrintIp?"on":"off"); } - | TOK_PIP error end { printf("pip on | off | ?\n") } - | TOK_IOSTAT bool end { Config.IoStatistics = $2; } - | TOK_IOSTAT '?' end { printf("io statistics %s\n", - Config.IoStatistics?"on":"off"); } - | TOK_IOSTAT error end { printf("iostat on | off | ?\n") } - | TOK_TRACE bool end { Config.Trace = $2; } - | TOK_TRACE '?' end { printf("trace %s\n", - Config.Trace ?"on":"off"); } - | TOK_TRACE error end { printf("trace on | off | ?\n") } -; -verbose: TOK_VERBOSE val end { Config.Verbose = $2; } - | TOK_VERBOSE '?' end { printf("verbose: %i\n", - Config.Verbose); } - | TOK_VERBOSE error end { printf("verbose val | ?\n"); } -; -logging: TOK_LOG TOK_STRING end { logon(normalize_string((char*)$2)); } - | TOK_LOG '?' end { if (logging) printf("logfile: %s\n", - logfile); - else printf("no logging\n?"); } - | TOK_LOG TOK_OFF end { logoff(); } - | TOK_LOG error end { printf("log \"\" | ? |" - " off\n"); } -; -clstat: TOK_CLSTAT end { clear_stat(); } - | TOK_CLSTAT error end { printf("clstat\n"); } -; -print: TOK_STDOUT bool end { nostdout = !$2; } - | TOK_STDOUT '?' end { printf("print %s\n",nostdout ? - "no":"yes"); } - | TOK_STDOUT error end { printf("print on | off\n"); } -; -com_hlt: TOK_HLT val end { add_hlt($2); } - | TOK_HLT TOK_DEL val end { del_hlt($3); } - | TOK_HLT TOK_DEL end { del_hlt(21); } - | TOK_HLT '?' end { list_hlt(); } - | TOK_HLT error end { printf( - "hlt val | del [val] | ?\n"); } -; -ioperm: TOK_IOPERM val val val end { int i,max; - if ($2 >= 0) { - max = $2 + $3 - 1; - if (max > IOPERM_BITS) - max = IOPERM_BITS; - for (i = $2;i <= max; i++) - ioperm_list[i] - = $4>0 ? 1 : 0; - } - } - | TOK_IOPERM '?' end { int i,start; - for (i=0; i <= IOPERM_BITS; i++) { - if (ioperm_list[i]) { - start = i; - for (; i <= IOPERM_BITS; i++) - if (!ioperm_list[i]) { - printf("ioperm on in " - "0x%x+0x%x\n", start,i-start); - break; - } - } - } - } - | TOK_IOPERM error end { printf("ioperm start len val\n"); } -; -list_pci: TOK_DUMP_PCI end { list_pci(); } - | TOK_DUMP_PCI error end { list_pci(); } -; -boot_bios: TOK_BOOT_BIOS '?' end { if (!BootBios) printf("No Boot BIOS\n"); - else printf("BootBIOS from: %i:%i:%i\n", - BootBios->bus, BootBios->dev, - BootBios->func); } - | TOK_BOOT_BIOS error end { printf ("bootbios bus:dev:num\n"); } -; -hlp: '?' { printf("Command list:\n"); - printf(" select isa | pci bus:dev:func\n"); - printf(" boot\n"); - printf(" seg:reg val | reg val \n"); - printf(" $x val | $mem val\n"); - printf(" setmem addr list; addr := val\n"); - printf(" dumpmem addr len; addr,len := val\n"); - printf(" do [val]\n"); - printf(" quit\n"); - printf(" ?\n"); - printf(" seg := ds | es;" - " reg := ax | bx | cx | dx | si \n"); - printf(" val := var | | seg:reg | seg\n"); - printf(" var := $x | $mem; x := 0..20\n"); - printf(" list := byte val | word val | long val " - "| \"string\"\n"); - printf(" pport on | off | ?\n"); - printf(" ppci on | off | ?\n"); - printf(" pirq on | off | ?\n"); - printf(" pip on | off | ?\n"); - printf(" trace on | off | ?\n"); - printf(" iostat on | off | ?\n"); - printf(" verbose val\n"); - printf(" log \"\" | off | ?\n"); - printf(" print on | off\n"); - printf(" hlt val | del [val] | ?\n"); - printf(" clstat\n"); - printf(" lpci\n"); - printf ("bootbios ?\n"); -} -; - -%% - -static void -dump_mem(CARD32 addr, int len) -{ - dprint(addr,len); -} - -static void -exec_int(int num) -{ - if (num == 0x10) { /* video interrupt */ - if (Device.type == NONE) { - CurrentPci = PciList; - while (CurrentPci) { - if (CurrentPci->active) - break; - CurrentPci = CurrentPci->next; - } - if (!CurrentPci) - Device.type = ISA; - else { - Device.type = PCI; - Device.loc.pci.dev = CurrentPci->dev; - Device.loc.pci.bus = CurrentPci->bus; - Device.loc.pci.func = CurrentPci->func; - } - } - if (Device.type != ISA) { - if (!Device.booted) { - if (!CurrentPci || (Device.type == PCI - && (!CurrentPci->active - && (Device.loc.pci.dev != CurrentPci->dev - || Device.loc.pci.bus != CurrentPci->bus - || Device.loc.pci.func != CurrentPci->func)))) { - printf("boot the device fist\n"); - return; - } - } - } else - CurrentPci = NULL; - } else { - Device.booted = FALSE; /* we need this for sanity! */ - } - - runINT(num,®s); -} - -static void -boot(void) -{ - if (Device.type == NONE) { - printf("select a device fist\n"); - return; - } - - call_boot(&Device); -} - -static void * -add_to_list(enum mem_type type, union mem_val *rec, void *next) -{ - struct mem *mem_rec = (struct mem *) malloc(sizeof(mem_rec)); - - mem_rec->type = type; - mem_rec->next = next; - - switch (type) { - case BYTE: - case WORD: - case LONG: - mem_rec->val.integer = rec->integer; - break; - case STRING: - mem_rec->val.ptr = normalize_string(rec->ptr); - break; - } - return mem_rec; -} - -static int -validRange(int addr,int len) -{ - int end = addr + len; - - if (addr < 0x1000 || end > 0xc0000) - return 0; - return 1; -} - -static void -do_list(struct mem *list, memType addr) -{ - struct mem *prev; - int len; - - while (list) { - switch (list->type) { - case BYTE: - if (!validRange(addr,1)) goto error; - *(CARD8*)addr = list->val.integer; - addr =+ 1; - break; - case WORD: - if (!validRange(addr,2)) goto error; - *(CARD16*)addr = list->val.integer; - addr =+ 2; - break; - case LONG: - if (!validRange(addr,4)) goto error; - *(CARD32*)addr = list->val.integer; - addr =+ 4; - break; - case STRING: - len = strlen((char*)list->val.ptr); - if (!validRange(addr,len)) goto error; - memcpy((CARD8*)addr,(void*)list->val.ptr,len); - addr =+ len; - free(list->val.ptr); - break; - } - prev = list; - list = list->next; - free(prev); - continue; - error: - printf("address out of range\n"); - while (list) { - prev = list; - list = list->next; - free(prev); - } - break; - } -} - -static char * -normalize_string(char *ptr) -{ - int i = 0, j = 0, c = 0, esc= 0; - int size; - char *mem_ptr; - - size = strlen(ptr); - mem_ptr = malloc(size); - while (1) { - switch (*(ptr + i)) { - case '\\': - if (esc) { - *(mem_ptr + j++) = *(ptr + i); - esc = 0; - } else - esc = 1; - break; - case '\"': - if (esc) { - *(mem_ptr + j++) = *(ptr + i); - esc = 0; - } else - c++; - break; - default: - *(mem_ptr + j++) = *(ptr + i); - break; - } - if (c > 1) { - *(mem_ptr + j) = '\0'; - break; - } - i++; - } - return mem_ptr; -} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/pci.c b/board/MAI/bios_emulator/scitech/src/v86bios/pci.c deleted file mode 100644 index b58a571..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/pci.c +++ /dev/null @@ -1,902 +0,0 @@ -/* - * Copyright 1999 Egbert Eich - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of the authors not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. The authors makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#include "debug.h" -#include -#include -#include -#include -#include -#include -#include -#include -#if defined (__alpha__) || defined (__ia64__) -#include -#endif -#include "AsmMacros.h" - -#include "pci.h" - -/* - * I'm rather simple mindend - therefore I do a poor man's - * pci scan without all the fancy stuff that is done in - * scanpci. However that's all we need. - */ - -PciStructPtr PciStruct = NULL; -PciBusPtr PciBuses = NULL; -PciStructPtr CurrentPci = NULL; -PciStructPtr PciList = NULL; -PciStructPtr BootBios = NULL; -int pciMaxBus = 0; - -static CARD32 PciCfg1Addr; - -static void readConfigSpaceCfg1(CARD32 bus, CARD32 dev, CARD32 func, - CARD32 *reg); -static int checkSlotCfg1(CARD32 bus, CARD32 dev, CARD32 func); -static int checkSlotCfg2(CARD32 bus, int dev); -static void readConfigSpaceCfg2(CARD32 bus, int dev, CARD32 *reg); -static CARD8 interpretConfigSpace(CARD32 *reg, int busidx, - CARD8 dev, CARD8 func); -static CARD32 findBIOSMap(PciStructPtr pciP, CARD32 *biosSize); -static void restoreMem(PciStructPtr pciP); - - -#ifdef __alpha__ -#define PCI_BUS_FROM_TAG(tag) (((tag) & 0x00ff0000) >> 16) -#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00) >> 8) - -#include - -CARD32 -axpPciCfgRead(CARD32 tag) -{ - int bus, dfn; - CARD32 val = 0xffffffff; - - bus = PCI_BUS_FROM_TAG(tag); - dfn = PCI_DFN_FROM_TAG(tag); - - syscall(__NR_pciconfig_read, bus, dfn, tag & 0xff, 4, &val); - return(val); -} - -void -axpPciCfgWrite(CARD32 tag, CARD32 val) -{ - int bus, dfn; - - bus = PCI_BUS_FROM_TAG(tag); - dfn = PCI_DFN_FROM_TAG(tag); - - syscall(__NR_pciconfig_write, bus, dfn, tag & 0xff, 4, &val); -} - -static CARD32 (*readPci)(CARD32 reg) = axpPciCfgRead; -static void (*writePci)(CARD32 reg, CARD32 val) = axpPciCfgWrite; -#else -static CARD32 readPciCfg1(CARD32 reg); -static void writePciCfg1(CARD32 reg, CARD32 val); -static CARD32 readPciCfg2(CARD32 reg); -static void writePciCfg2(CARD32 reg, CARD32 val); - -static CARD32 (*readPci)(CARD32 reg) = readPciCfg1; -static void (*writePci)(CARD32 reg, CARD32 val) = writePciCfg1; -#endif - -#if defined(__alpha__) || defined(__sparc__) -#define PCI_EN 0x00000000 -#else -#define PCI_EN 0x80000000 -#endif - - -static int numbus; -static int hostbridges = 1; -static unsigned long pciMinMemReg = ~0; - - -void -scan_pci(void) -{ - unsigned short configtype; - - CARD32 reg[64]; - int busidx; - CARD8 cardnum; - CARD8 func; - int idx; - - int i; - PciStructPtr pci1; - PciBusPtr pci_b1,pci_b2; - -#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc__) || defined(__ia64__) - configtype = 1; -#else - CARD8 tmp1, tmp2; - CARD32 tmp32_1, tmp32_2; - outb(PCI_MODE2_ENABLE_REG, 0x00); - outb(PCI_MODE2_FORWARD_REG, 0x00); - tmp1 = inb(PCI_MODE2_ENABLE_REG); - tmp2 = inb(PCI_MODE2_FORWARD_REG); - if ((tmp1 == 0x00) && (tmp2 == 0x00)) { - configtype = 2; - readPci = readPciCfg2; - writePci = writePciCfg2; - P_printf("PCI says configuration type 2\n"); - } else { - tmp32_1 = inl(PCI_MODE1_ADDRESS_REG); - outl(PCI_MODE1_ADDRESS_REG, PCI_EN); - tmp32_2 = inl(PCI_MODE1_ADDRESS_REG); - outl(PCI_MODE1_ADDRESS_REG, tmp32_1); - if (tmp32_2 == PCI_EN) { - configtype = 1; - P_printf("PCI says configuration type 1\n"); - } else { - P_printf("No PCI !\n"); - return; - } - } -#endif - - if (configtype == 1) { - P_printf("PCI probing configuration type 1\n"); - busidx = 0; - numbus = 1; - idx = 0; - do { - P_printf("\nProbing for devices on PCI bus %d:\n", busidx); - for (cardnum = 0; cardnum < MAX_DEV_PER_VENDOR_CFG1; cardnum++) { - func = 0; - do { - /* loop over the different functions, if present */ - if (!checkSlotCfg1(busidx,cardnum,func)) - break; - readConfigSpaceCfg1(busidx,cardnum,func,reg); - - func = interpretConfigSpace(reg,busidx, - cardnum,func); - - if (idx++ > MAX_PCI_DEVICES) - continue; - } while (func < 8); - } - } while (++busidx < PCI_MAXBUS); -#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc__) || defined(__ia64__) - /* don't use outl() ;-) */ -#else - outl(PCI_MODE1_ADDRESS_REG, 0); -#endif - } else { - int slot; - - P_printf("PCI probing configuration type 2\n"); - busidx = 0; - numbus = 1; - idx = 0; - do { - for (slot=0xc0; slot<0xd0; i++) { - if (!checkSlotCfg2(busidx,slot)) - break; - readConfigSpaceCfg2(busidx,slot,reg); - - interpretConfigSpace(reg,busidx, - slot,0); - if (idx++ > MAX_PCI_DEVICES) - continue; - } - } while (++busidx < PCI_MAXBUS); - } - - - pciMaxBus = numbus - 1; - P_printf("Number of buses in system: %i\n",pciMaxBus + 1); - P_printf("Min PCI mem address: 0x%lx\n",pciMinMemReg); - - /* link buses */ - pci_b1 = PciBuses; - while (pci_b1) { - pci_b2 = PciBuses; - pci_b1->pBus = NULL; - while (pci_b2) { - if (pci_b1->primary == pci_b2->secondary) - pci_b1->pBus = pci_b2; - pci_b2 = pci_b2->next; - } - pci_b1 = pci_b1->next; - } - pci1 = PciStruct; - while (pci1) { - pci_b2 = PciBuses; - pci1->pBus = NULL; - while (pci_b2) { - if (pci1->bus == pci_b2->secondary) - pci1->pBus = pci_b2; - pci_b2 = pci_b2->next; - } - pci1 = pci1->next; - } - if (RESORT) { - PciStructPtr tmp = PciStruct, tmp1; - PciStruct = NULL; - while (tmp) { - tmp1 = tmp->next; - tmp->next = PciStruct; - PciStruct = tmp; - tmp = tmp1; - } - } - PciList = CurrentPci = PciStruct; -} - -#ifndef __alpha__ -static CARD32 -readPciCfg1(CARD32 reg) -{ - CARD32 val; - - outl(PCI_MODE1_ADDRESS_REG, reg); - val = inl(PCI_MODE1_DATA_REG); - outl(PCI_MODE1_ADDRESS_REG, 0); - P_printf("reading: 0x%x from 0x%x\n",val,reg); - return val; -} - -static void -writePciCfg1(CARD32 reg, CARD32 val) -{ - P_printf("writing: 0x%x to 0x%x\n",val,reg); - outl(PCI_MODE1_ADDRESS_REG, reg); - outl(PCI_MODE1_DATA_REG,val); - outl(PCI_MODE1_ADDRESS_REG, 0); -} - -static CARD32 -readPciCfg2(CARD32 reg) -{ - CARD32 val; - CARD8 bus = (reg >> 16) & 0xff; - CARD8 dev = (reg >> 11) & 0x1f; - CARD8 num = reg & 0xff; - - outb(PCI_MODE2_ENABLE_REG, 0xF1); - outb(PCI_MODE2_FORWARD_REG, bus); - val = inl((dev << 8) + num); - outb(PCI_MODE2_ENABLE_REG, 0x00); - P_printf("reading: 0x%x from 0x%x\n",val,reg); - return val; -} - -static void -writePciCfg2(CARD32 reg, CARD32 val) -{ - CARD8 bus = (reg >> 16) & 0xff; - CARD8 dev = (reg >> 11) & 0x1f; - CARD8 num = reg & 0xff; - - P_printf("writing: 0x%x to 0x%x\n",val,reg); - outb(PCI_MODE2_ENABLE_REG, 0xF1); - outb(PCI_MODE2_FORWARD_REG, bus); - outl((dev << 8) + num,val); - outb(PCI_MODE2_ENABLE_REG, 0x00); -} -#endif - -void -pciVideoDisable(void) -{ - /* disable VGA routing on bridges */ - PciBusPtr pbp = PciBuses; - PciStructPtr pcp = PciStruct; - - while (pbp) { - writePci(pbp->Slot.l | 0x3c, pbp->bctl & ~(CARD32)(8<<16)); - pbp = pbp->next; - } - /* disable display devices */ - while (pcp) { - writePci(pcp->Slot.l | 0x04, pcp->cmd_st & ~(CARD32)3); - writePci(pcp->Slot.l | 0x30, pcp->RomBase & ~(CARD32)1); - pcp = pcp->next; - } -} - -void -pciVideoRestore(void) -{ - /* disable VGA routing on bridges */ - PciBusPtr pbp = PciBuses; - PciStructPtr pcp = PciStruct; - - while (pbp) { - writePci(pbp->Slot.l | 0x3c, pbp->bctl); - pbp = pbp->next; - } - /* disable display devices */ - while (pcp) { - writePci(pcp->Slot.l | 0x04, pcp->cmd_st); - writePci(pcp->Slot.l | 0x30, pcp->RomBase); - pcp = pcp->next; - } -} - -void -EnableCurrent() -{ - PciBusPtr pbp; - PciStructPtr pcp = CurrentPci; - - pciVideoDisable(); - - pbp = pcp->pBus; - while (pbp) { /* enable bridges */ - writePci(pbp->Slot.l | 0x3c, pbp->bctl | (CARD32)(8<<16)); - pbp = pbp->pBus; - } - writePci(pcp->Slot.l | 0x04, pcp->cmd_st | (CARD32)3); - writePci(pcp->Slot.l | 0x30, pcp->RomBase | (CARD32)1); -} - -CARD8 -PciRead8(int offset, CARD32 Slot) -{ - int shift = offset & 0x3; - offset = offset & 0xFC; - return ((readPci(Slot | offset) >> (shift << 3)) & 0xff); -} - -CARD16 -PciRead16(int offset, CARD32 Slot) -{ - int shift = offset & 0x2; - offset = offset & 0xFC; - return ((readPci(Slot | offset) >> (shift << 3)) & 0xffff); -} - -CARD32 -PciRead32(int offset, CARD32 Slot) -{ - offset = offset & 0xFC; - return (readPci(Slot | offset)); -} - -void -PciWrite8(int offset, CARD8 byte, CARD32 Slot) -{ - CARD32 val; - int shift = offset & 0x3; - offset = offset & 0xFC; - val = readPci(Slot | offset); - val &= ~(CARD32)(0xff << (shift << 3)); - val |= byte << (shift << 3); - writePci(Slot | offset, val); -} - -void -PciWrite16(int offset, CARD16 word, CARD32 Slot) -{ - CARD32 val; - int shift = offset & 0x2; - offset = offset & 0xFC; - val = readPci(Slot | offset); - val &= ~(CARD32)(0xffff << (shift << 3)); - val |= word << (shift << 3); - writePci(Slot | offset, val); -} - -void -PciWrite32(int offset, CARD32 lg, CARD32 Slot) -{ - offset = offset & 0xFC; - writePci(Slot | offset, lg); -} - -int -mapPciRom(PciStructPtr pciP) -{ - unsigned long RomBase = 0; - int mem_fd; - unsigned char *mem, *ptr; - unsigned char *scratch = NULL; - int length = 0; - CARD32 biosSize = 0x1000000; - CARD32 enablePci; - - if (!pciP) - pciP = CurrentPci; - - if (FIX_ROM) { - RomBase = findBIOSMap(pciP, &biosSize); - if (!RomBase) { - fprintf(stderr,"Cannot remap BIOS of %i:%i:%i " - "- trying preset address\n",pciP->bus,pciP->dev, - pciP->func); - RomBase = pciP->RomBase & ~(CARD32)0xFF; - } - } else { - RomBase = pciP->RomBase & ~(CARD32)0xFF; - if (~RomBase + 1 < biosSize || !RomBase) - RomBase = findBIOSMap(pciP, &biosSize); - } - - P_printf("RomBase: 0x%lx\n",RomBase); - - if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { - perror("opening memory"); - restoreMem(pciP); - return (0); - } - - PciWrite32(0x30,RomBase | 1,pciP->Slot.l); - -#ifdef __alpha__ - mem = ptr = (unsigned char *)mmap(0, biosSize, PROT_READ, - MAP_SHARED, mem_fd, RomBase | _bus_base()); -#else - mem = ptr = (unsigned char *)mmap(0, biosSize, PROT_READ, - MAP_SHARED, mem_fd, RomBase); -#endif - if (pciP != CurrentPci) { - enablePci = PciRead32(0x4,pciP->Slot.l); - PciWrite32(0x4,enablePci | 0x2,pciP->Slot.l); - } - -#ifdef PRINT_PCI - dprint((unsigned long)ptr,0x30); -#endif - while ( *ptr == 0x55 && *(ptr+1) == 0xAA) { - unsigned short data_off = *(ptr+0x18) | (*(ptr+0x19)<< 8); - unsigned char *data = ptr + data_off; - unsigned char type; - int i; - - if (*data!='P' || *(data+1)!='C' || *(data+2)!='I' || *(data+3)!='R') { - break; - } - type = *(data + 0x14); - P_printf("data segment in BIOS: 0x%x, type: 0x%x ",data_off,type); - - if (type != 0) { /* not PC-AT image: find next one */ - unsigned int image_length; - unsigned char indicator = *(data + 0x15); - if (indicator & 0x80) /* last image */ - break; - image_length = (*(data + 0x10) - | (*(data + 0x11) << 8)) << 9; - P_printf("data image length: 0x%x, ind: 0x%x\n", - image_length,indicator); - ptr = ptr + image_length; - continue; - } - /* OK, we have a PC Image */ - length = (*(ptr + 2) << 9); - P_printf("BIOS length: 0x%x\n",length); - scratch = (unsigned char *)malloc(length); - /* don't use memcpy() here: Reading from bus! */ - for (i=0;iSlot.l); - - /* unmap/close/disable PCI bios mem */ - munmap(mem, biosSize); - close(mem_fd); - /* disable and restore mapping */ - writePci(pciP->Slot.l | 0x30, pciP->RomBase & ~(CARD32)1); - - if (scratch && length) { - memcpy((unsigned char *)V_BIOS, scratch, length); - free(scratch); - } - - restoreMem(pciP); - return length; -} - -CARD32 -findPci(CARD16 slotBX) -{ - CARD32 slot = slotBX << 8; - - if (slot == (CurrentPci->Slot.l & ~PCI_EN)) - return (CurrentPci->Slot.l | PCI_EN); - else { -#if !SHOW_ALL_DEV - PciBusPtr pBus = CurrentPci->pBus; - while (pBus) { - /* fprintf(stderr,"slot: 0x%x bridge: 0x%x\n",slot, pBus->Slot.l); */ - if (slot == (pBus->Slot.l & ~PCI_EN)) - return pBus->Slot.l | PCI_EN; - pBus = pBus->next; - } -#else - PciStructPtr pPci = PciStruct; - while (pPci) { - /*fprintf(stderr,"slot: 0x%x bridge: 0x%x\n",slot, pPci->Slot.l); */ - if (slot == (pPci->Slot.l & ~PCI_EN)) - return pPci->Slot.l | PCI_EN; - pPci = pPci->next; - } -#endif - } - return 0; -} - -CARD16 -pciSlotBX(PciStructPtr pPci) -{ - return (CARD16)((pPci->Slot.l >> 8) & 0xFFFF); -} - -PciStructPtr -findPciDevice(CARD16 vendorID, CARD16 deviceID, char n) -{ - PciStructPtr pPci = CurrentPci; - n++; - - while (pPci) { - if ((pPci->VendorID == vendorID) && (pPci->DeviceID == deviceID)) { - if (!(--n)) break; - } - pPci = pPci->next; - } - return pPci; -} - -PciStructPtr -findPciClass(CARD8 intf, CARD8 subClass, CARD16 class, char n) -{ - PciStructPtr pPci = CurrentPci; - n++; - - while (pPci) { - if ((pPci->Interface == intf) && (pPci->SubClass == subClass) - && (pPci->BaseClass == class)) { - if (!(--n)) break; - } - pPci = pPci->next; - } - return pPci; -} - -static void -readConfigSpaceCfg1(CARD32 bus, CARD32 dev, CARD32 func, CARD32 *reg) -{ - CARD32 config_cmd = PCI_EN | (bus<<16) | - (dev<<11) | (func<<8); - int i; - - for (i = 0; i<64;i+=4) { -#ifdef __alpha__ - reg[i] = axpPciCfgRead(config_cmd | i); -#else - outl(PCI_MODE1_ADDRESS_REG, config_cmd | i); - reg[i] = inl(PCI_MODE1_DATA_REG); -#endif - -#ifdef V86BIOS_DEBUG - P_printf("0x%lx\n",reg[i]); -#endif - } -} - -static int -checkSlotCfg1(CARD32 bus, CARD32 dev, CARD32 func) -{ - CARD32 config_cmd = PCI_EN | (bus<<16) | - (dev<<11) | (func<<8); - CARD32 reg; -#ifdef __alpha__ - reg = axpPciCfgRead(config_cmd); -#else - outl(PCI_MODE1_ADDRESS_REG, config_cmd); - reg = inl(PCI_MODE1_DATA_REG); -#endif - if (reg != 0xFFFFFFFF) - return 1; - else - return 0; -} - -static int -checkSlotCfg2(CARD32 bus, int dev) -{ - CARD32 val; - - outb(PCI_MODE2_ENABLE_REG, 0xF1); - outb(PCI_MODE2_FORWARD_REG, bus); - val = inl(dev << 8); - outb(PCI_MODE2_FORWARD_REG, 0x00); - outb(PCI_MODE2_ENABLE_REG, 0x00); - if (val == 0xFFFFFFFF) - return 0; - if (val == 0xF0F0F0F0) - return 0; - return 1; -} - -static void -readConfigSpaceCfg2(CARD32 bus, int dev, CARD32 *reg) -{ - int i; - - outb(PCI_MODE2_ENABLE_REG, 0xF1); - outb(PCI_MODE2_FORWARD_REG, bus); - for (i = 0; i<64;i+=4) { - reg[i] = inl((dev << 8) + i); -#ifdef V86BIOS_DEBUG - P_printf("0x%lx\n",reg[i]); -#endif - } - outb(PCI_MODE2_ENABLE_REG, 0x00); -} - -static CARD8 -interpretConfigSpace(CARD32 *reg, int busidx, CARD8 dev, CARD8 func) -{ - CARD32 config_cmd; - CARD16 vendor, device; - CARD8 baseclass, subclass; - CARD8 primary, secondary; - CARD8 header, interface; - int i; - - config_cmd = PCI_EN | busidx<<16 | - (dev<<11) | (func<<8); - - for (i = 0x10; i < 0x28; i+=4) { - if (IS_MEM32(reg[i])) - if ((reg[i] & 0xFFFFFFF0) < pciMinMemReg) - pciMinMemReg = (reg[i] & 0xFFFFFFF0); -#ifdef __alpha__ - if (IS_MEM64(reg[i])) { - unsigned long addr = reg[i] | - (unsigned long)(reg[i+4]) << 32; - if ((addr & ~0xfL) < pciMinMemReg) - pciMinMemReg = (addr & ~0xfL); - i+=4; - } -#endif - } - vendor = reg[0] & 0xFFFF; - device = reg[0] >> 16; - P_printf("bus: %i card: %i func %i reg0: 0x%x ", busidx,dev,func,reg[0]); - baseclass = reg[8] >> 24; - subclass = (reg[8] >> 16) & 0xFF; - interface = (reg[8] >> 8) & 0xFF; - - header = (reg[0x0c] >> 16) & 0xff; - P_printf("bc 0x%x, sub 0x%x, if 0x%x, hdr 0x%x\n", - baseclass,subclass,interface,header); - if (BRIDGE_CLASS(baseclass)) { - if (BRIDGE_PCI_CLASS(subclass)) { - PciBusPtr pbp = malloc(sizeof(PciBusRec)); - P_printf("Pci-Pci Bridge found; "); - primary = reg[0x18] & 0xFF; - secondary = (reg[0x18] >> 8) & 0xFF; - P_printf("primary: 0x%x secondary: 0x%x\n", - primary,secondary); - pbp->bctl = reg[0x3c]; - pbp->primary = primary; - pbp->secondary = secondary; - pbp->Slot.l = config_cmd; - pbp->next = PciBuses; - PciBuses = pbp; - numbus++; - } else if (BRIDGE_HOST_CLASS(subclass) - && (hostbridges++ > 1)) { - numbus++; - } - } else if (VIDEO_CLASS(baseclass,subclass)) { - PciStructPtr pcp = malloc(sizeof(PciStructRec)); - P_printf("Display adapter found\n"); - pcp->RomBase = reg[0x30]; - pcp->cmd_st = reg[4]; - pcp->active = (reg[4] & 0x03) == 3 ? 1 : 0; - pcp->VendorID = vendor; - pcp->DeviceID = device; - pcp->Interface = interface; - pcp->BaseClass = baseclass; - pcp->SubClass = subclass; - pcp->Slot.l = config_cmd; - pcp->bus = busidx; - pcp->dev = dev; - pcp->func = func; - pcp->next = PciStruct; - PciStruct = pcp; - } - if ((func == 0) - && ((header & PCI_MULTIFUNC_DEV) == 0)) - func = 8; - else - func++; - return func; -} - -static CARD32 remapMEM_val; -static int remapMEM_num; - -static int /* map it on some other video device */ -remapMem(PciStructPtr pciP, int num, CARD32 size) -{ - PciStructPtr pciPtr = PciStruct; - int i; - CARD32 org; - CARD32 val; - CARD32 size_n; - - org = PciRead32(num + 0x10,pciP->Slot.l); - - while (pciPtr) { - for (i = 0; i < 20; i=i+4) { - - val = PciRead32(i + 0x10,pciPtr->Slot.l); - /* don't map it on itself */ - if ((org & 0xfffffff0) == (val & 0xfffffff0)) - continue; - if (val && !(val & 1)) - PciWrite32(i + 0x10,0xffffffff,pciPtr->Slot.l); - else - continue; - size_n = PciRead32(i + 0x10,pciPtr->Slot.l); - PciWrite32(i + 0x10,val,pciPtr->Slot.l); - size_n = ~(CARD32)(size_n & 0xfffffff0) + 1; - - if (size_n >= size) { - PciWrite32(num + 0x10,val,pciP->Slot.l); - return 1; - } - } - pciPtr = pciPtr->next; - } - /* last resort: try to go below lowest PCI mem address */ - val = ((pciMinMemReg & ~(CARD32)(size - 1)) - size); - if (val > 0x7fffffff) { - PciWrite32(num + 0x10,val, pciP->Slot.l); - return 1; - } - - return 0; -} - -static void -restoreMem(PciStructPtr pciP) -{ - if (remapMEM_val == 0) return; - PciWrite32(remapMEM_num + 0x10,remapMEM_val,pciP->Slot.l); - return; -} - -static CARD32 -findBIOSMap(PciStructPtr pciP, CARD32 *biosSize) -{ - PciStructPtr pciPtr = PciStruct; - int i; - CARD32 val; - CARD32 size; - - PciWrite32(0x30,0xffffffff,pciP->Slot.l); - *biosSize = PciRead32(0x30,pciP->Slot.l); - P_printf("bios size: 0x%x\n",*biosSize); - PciWrite32(0x30,pciP->RomBase,pciP->Slot.l); - *biosSize = ~(*biosSize & 0xFFFFFF00) + 1; - P_printf("bios size masked: 0x%x\n",*biosSize); - if (*biosSize > (1024 * 1024 * 16)) { - *biosSize = 1024 * 1024 * 16; - P_printf("fixing broken BIOS size: 0x%x\n",*biosSize); - } - while (pciPtr) { - if (pciPtr->bus != pciP->bus) { - pciPtr = pciPtr->next; - continue; - } - for (i = 0; i < 20; i=i+4) { - - val = PciRead32(i + 0x10,pciPtr->Slot.l); - if (!(val & 1)) - - PciWrite32(i + 0x10,0xffffffff,pciPtr->Slot.l); - else - continue; - size = PciRead32(i + 0x10,pciPtr->Slot.l); - PciWrite32(i + 0x10,val,pciPtr->Slot.l); - size = ~(CARD32)(size & 0xFFFFFFF0) + 1; -#ifdef V86_BIOS_DEBUG - P_printf("size: 0x%x\n",size); -#endif - if (size >= *biosSize) { - if (pciP == pciPtr) { /* if same device remap ram*/ - if (!(remapMem(pciP,i,size))) - continue; - remapMEM_val = val; - remapMEM_num = i; - } else { - remapMEM_val = 0; - } - return val & 0xFFFFFF00; - } - } - pciPtr = pciPtr->next; - } - remapMEM_val = 0; - /* very last resort */ - if (pciP->bus == 0 && (pciMinMemReg > *biosSize)) - return (pciMinMemReg - size) & ~(size - 1); - - return 0; -} - -int -cfg1out(CARD16 addr, CARD32 val) -{ - if (addr == 0xCF8) { - PciCfg1Addr = val; - return 1; - } else if (addr == 0xCFC) { - writePci(PciCfg1Addr, val); - return 1; - } - return 0; -} - -int -cfg1in(CARD16 addr, CARD32 *val) -{ - if (addr == 0xCF8) { - *val = PciCfg1Addr; - return 1; - } else if (addr == 0xCFC) { - *val = readPci(PciCfg1Addr); - return 1; - } - return 0; -} - -void -list_pci(void) -{ - PciStructPtr pci = PciList; - - while (pci) { - printf("[0x%x:0x%x:0x%x] vendor: 0x%4.4x dev: 0x%4.4x class: 0x%4.4x" - " subclass: 0x%4.4x\n",pci->bus,pci->dev,pci->func, - pci->VendorID,pci->DeviceID,pci->BaseClass,pci->SubClass); - pci = pci->next; - } -} - -PciStructPtr -findPciByIDs(int bus, int dev, int func) -{ - PciStructPtr pciP = PciList; - - while (pciP) { - if (pciP->bus == bus && pciP->dev == dev && pciP->func == func) - return pciP; - pciP = pciP->next; - } - return NULL; -} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/pci.h b/board/MAI/bios_emulator/scitech/src/v86bios/pci.h deleted file mode 100644 index 58ad522..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/pci.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright 1999 Egbert Eich - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of the authors not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. The authors makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#include "v86bios.h" - -#ifndef V86_PCI_H -#define V86_PCI_H - -typedef union { - struct { - unsigned int zero:2; - unsigned int reg:6; - unsigned int func:3; - unsigned int dev:5; - unsigned int bus:8; - unsigned int reserved:7; - unsigned int enable:1; - } pci; - CARD32 l; -} PciSlot; - -typedef struct pciBusRec { - CARD8 primary; - CARD8 secondary; - CARD32 bctl; - PciSlot Slot; - struct pciBusRec *next; - struct pciBusRec *pBus; -} PciBusRec, *PciBusPtr; - -typedef struct pciStructRec { - CARD16 VendorID; - CARD16 DeviceID; - CARD8 Interface; - CARD8 BaseClass; - CARD8 SubClass; - CARD32 RomBase; - CARD32 bus; - CARD8 dev; - CARD8 func; - CARD32 cmd_st; - int active; - PciSlot Slot; - struct pciStructRec *next; - PciBusPtr pBus; -} PciStructRec , *PciStructPtr; - - -extern PciStructPtr CurrentPci; -extern PciStructPtr PciList; -extern PciStructPtr BootBios; -extern int pciMaxBus; - -extern CARD32 findPci(CARD16 slotBX); -extern CARD16 pciSlotBX(PciStructPtr); -PciStructPtr findPciDevice(CARD16 vendorID, CARD16 deviceID, char n); -PciStructPtr findPciClass(CARD8 intf, CARD8 subClass, CARD16 class, char n); - -extern CARD8 PciRead8(int offset, CARD32 slot); -extern CARD16 PciRead16(int offset, CARD32 slot); -extern CARD32 PciRead32(int offset, CARD32 slot); - -extern void PciWrite8(int offset,CARD8 byte, CARD32 slot); -extern void PciWrite16(int offset,CARD16 word, CARD32 slot); -extern void PciWrite32(int offset,CARD32 lg, CARD32 slot); - -extern void scan_pci(void); -extern void pciVideoDisable(void); -extern void pciVideoRestore(void); -extern void EnableCurrent(void); -extern int mapPciRom(PciStructPtr pciP); -extern int cfg1out(CARD16 addr, CARD32 val); -extern int cfg1in(CARD16 addr, CARD32 *val); -extern void list_pci(void); -extern PciStructPtr findPciByIDs(int bus, int dev, int func); - -#define PCI_MODE2_ENABLE_REG 0xCF8 -#define PCI_MODE2_FORWARD_REG 0xCFA -#define PCI_MODE1_ADDRESS_REG 0xCF8 -#define PCI_MODE1_DATA_REG 0xCFC -#if defined(__alpha__) || defined(__sparc__) -#define PCI_EN 0x00000000 -#else -#define PCI_EN 0x80000000 -#endif -#define MAX_DEV_PER_VENDOR_CFG1 32 -#define BRIDGE_CLASS(x) (x == 0x06) -#define BRIDGE_PCI_CLASS(x) (x == 0x04) -#define BRIDGE_HOST_CLASS(x) (x == 0x00) -#define PCI_CLASS_PREHISTORIC 0x00 -#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 -#define PCI_CLASS_DISPLAY 0x03 -#define PCI_SUBCLASS_DISPLAY_VGA 0x00 -#define PCI_SUBCLASS_DISPLAY_XGA 0x01 -#define PCI_SUBCLASS_DISPLAY_MISC 0x80 -#define VIDEO_CLASS(b,s) \ - (((b) == PCI_CLASS_PREHISTORIC && (s) == PCI_SUBCLASS_PREHISTORIC_VGA) || \ - ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_VGA) ||\ - ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_XGA) ||\ - ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_MISC)) -#define PCI_MULTIFUNC_DEV 0x80 -#define MAX_PCI_DEVICES 64 -#define PCI_MAXBUS 16 -#define PCI_IS_MEM 0x00000001 -#define MAX_PCI_ROM_SIZE (1024 * 1024 * 16) - -#define IS_MEM32(x) ((x & 0x7) == 0 && x != 0) -#define IS_MEM64(x) ((x & 0x7) == 0x4) -#endif diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86.c b/board/MAI/bios_emulator/scitech/src/v86bios/v86.c deleted file mode 100644 index 4deed04..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/v86.c +++ /dev/null @@ -1,562 +0,0 @@ -/* - * Copyright 1999 Egbert Eich - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of the authors not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. The authors makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ - -#include "debug.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include "v86bios.h" -#include "AsmMacros.h" - -struct vm86_struct vm86s; - -static int vm86_GP_fault(void); -static int vm86_do_int(int num); -static void dump_code(void); -static void dump_registers(void); -static void stack_trace(void); -static int vm86_rep(struct vm86_struct *ptr); - -#define CPU_REG(x) (vm86s.regs.##x) -#define CPU_REG_LW(reg) (*((CARD16 *)&CPU_REG(reg))) -#define CPU_REG_HW(reg) (*((CARD16 *)&CPU_REG(reg) + 1)) -#define CPU_REG_LB(reg) (*(CARD8 *)&CPU_REG(e##reg)) -#define SEG_ADR(type, seg, reg) type((CPU_REG_LW(seg) << 4) \ - + CPU_REG_LW(e##reg)) -#define DF (1 << 10) - -struct pio P; - - -void -setup_io(void) -{ - if (!Config.PrintPort && !Config.IoStatistics) { - P.inb = (CARD8(*)(CARD16))inb; - P.inw = (CARD16(*)(CARD16))inw; - P.inl = (CARD32(*)(CARD16))inl; - P.outb = (void(*)(CARD16,CARD8))outb; - P.outw = (void(*)(CARD16,CARD16))outw; - P.outl = (void(*)(CARD16,CARD32))outl; - } else { - P.inb = p_inb; - P.inw = p_inw; - P.inl = p_inl; - P.outb = p_outb; - P.outw = p_outw; - P.outl = p_outl; - } -} - - -static void -setup_vm86(unsigned long bios_start, i86biosRegsPtr regs) -{ - CARD32 eip; - CARD16 cs; - - vm86s.flags = VM86_SCREEN_BITMAP; - vm86s.flags = 0; - vm86s.screen_bitmap = 0; - vm86s.cpu_type = CPU_586; - memset(&vm86s.int_revectored, 0xff,sizeof(vm86s.int_revectored)) ; - memset(&vm86s.int21_revectored, 0xff,sizeof(vm86s.int21_revectored)) ; - - eip = bios_start & 0xFFFF; - cs = (bios_start & 0xFF0000) >> 4; - - CPU_REG(eax) = regs->ax; - CPU_REG(ebx) = regs->bx; - CPU_REG(ecx) = regs->cx; - CPU_REG(edx) = regs->dx; - CPU_REG(esi) = 0; - CPU_REG(edi) = regs->di; - CPU_REG(ebp) = 0; - CPU_REG(eip) = eip; - CPU_REG(cs) = cs; - CPU_REG(esp) = 0x100; - CPU_REG(ss) = 0x30; /* This is the standard pc bios stack */ - CPU_REG(es) = regs->es; - CPU_REG(ds) = 0x40; /* standard pc ds */ - CPU_REG(fs) = 0; - CPU_REG(gs) = 0; - CPU_REG(eflags) |= (VIF_MASK | VIP_MASK); -} - -void -collect_bios_regs(i86biosRegsPtr regs) -{ - regs->ax = CPU_REG(eax); - regs->bx = CPU_REG(ebx); - regs->cx = CPU_REG(ecx); - regs->dx = CPU_REG(edx); - regs->es = CPU_REG(es); - regs->ds = CPU_REG(ds); - regs->di = CPU_REG(edi); - regs->si = CPU_REG(esi); -} - -static int -do_vm86(void) -{ - int retval; - -#ifdef V86BIOS_DEBUG - dump_registers(); -#endif -/* retval = SYS_vm86old(&vm86s); */ -/* retval = syscall(SYS_vm86old,&vm86s); */ - - retval = vm86_rep(&vm86s); - - switch (VM86_TYPE(retval)) { - case VM86_UNKNOWN: - if (!vm86_GP_fault()) return 0; - break; - case VM86_STI: - fprintf(stderr,"vm86_sti :-((\n"); - stack_trace(); - dump_code(); - return 0; - case VM86_INTx: - if (!vm86_do_int(VM86_ARG(retval))) { - fprintf(stderr,"\nUnknown vm86_int: %X\n\n",VM86_ARG(retval)); - dump_registers(); - return 0; - } - /* I'm not sure yet what to do if we can handle ints */ - break; - case VM86_SIGNAL: - fprintf(stderr,"received signal\n"); - return 0; - default: - fprintf(stderr,"unknown type(0x%x)=0x%x\n", - VM86_ARG(retval),VM86_TYPE(retval)); - dump_registers(); - dump_code(); - stack_trace(); - return 0; - } - - return 1; -} - -static jmp_buf x86_esc; -static void -vmexit(int unused) -{ - longjmp(x86_esc,1); -} - -void -do_x86(unsigned long bios_start, i86biosRegsPtr regs) -{ - static void (*org_handler)(int); - - setup_vm86(bios_start, regs); - if (setjmp(x86_esc) == 0) { - org_handler = signal(2,vmexit); - while(do_vm86()) {}; - signal(2,org_handler); - collect_bios_regs(regs); - } else { - signal(2,org_handler); - printf("interrupted at 0x%x\n",((CARD16)CPU_REG(cs)) << 4 - | (CARD16)CPU_REG(eip)); - } -} - -/* get the linear address */ -#define LIN_PREF_SI ((pref_seg << 4) + CPU_REG_LW(esi)) - -#define LWECX (prefix66 ^ prefix67 ? CPU_REG(ecx) : CPU_REG_LW(ecx)) - -static int -vm86_GP_fault(void) -{ - unsigned char *csp, *lina; - CARD32 org_eip; - int pref_seg; - int done,is_rep,prefix66,prefix67; - - - csp = lina = SEG_ADR((unsigned char *), cs, ip); -#ifdef V86BIOS_DEBUG - printf("exception: \n"); - dump_code(); -#endif - - is_rep = 0; - prefix66 = prefix67 = 0; - pref_seg = -1; - - /* eat up prefixes */ - done = 0; - do { - switch (*(csp++)) { - case 0x66: /* operand prefix */ prefix66=1; break; - case 0x67: /* address prefix */ prefix67=1; break; - case 0x2e: /* CS */ pref_seg=CPU_REG(cs); break; - case 0x3e: /* DS */ pref_seg=CPU_REG(ds); break; - case 0x26: /* ES */ pref_seg=CPU_REG(es); break; - case 0x36: /* SS */ pref_seg=CPU_REG(ss); break; - case 0x65: /* GS */ pref_seg=CPU_REG(gs); break; - case 0x64: /* FS */ pref_seg=CPU_REG(fs); break; - case 0xf2: /* repnz */ - case 0xf3: /* rep */ is_rep=1; break; - default: done=1; - } - } while (!done); - csp--; /* oops one too many */ - org_eip = CPU_REG(eip); - CPU_REG_LW(eip) += (csp - lina); - - switch (*csp) { - - case 0x6c: /* insb */ - /* NOTE: ES can't be overwritten; prefixes 66,67 should use esi,edi,ecx - * but is anyone using extended regs in real mode? */ - /* WARNING: no test for DI wrapping! */ - CPU_REG_LW(edi) += port_rep_inb(CPU_REG_LW(edx), - SEG_ADR((CARD8 *),es,di), - CPU_REG_LW(eflags)&DF, - (is_rep? LWECX:1)); - if (is_rep) LWECX = 0; - CPU_REG_LW(eip)++; - break; - - case 0x6d: /* (rep) insw / insd */ - /* NOTE: ES can't be overwritten */ - /* WARNING: no test for _DI wrapping! */ - if (prefix66) { - CPU_REG_LW(edi) += port_rep_inl(CPU_REG_LW(edx), - SEG_ADR((CARD32 *),es,di), - CPU_REG_LW(eflags)&DF, - (is_rep? LWECX:1)); - } - else { - CPU_REG_LW(edi) += port_rep_inw(CPU_REG_LW(edx), - SEG_ADR((CARD16 *),es,di), - CPU_REG_LW(eflags)&DF, - (is_rep? LWECX:1)); - } - if (is_rep) LWECX = 0; - CPU_REG_LW(eip)++; - break; - - case 0x6e: /* (rep) outsb */ - if (pref_seg < 0) pref_seg = CPU_REG_LW(ds); - /* WARNING: no test for _SI wrapping! */ - CPU_REG_LW(esi) += port_rep_outb(CPU_REG_LW(edx),(CARD8*)LIN_PREF_SI, - CPU_REG_LW(eflags)&DF, - (is_rep? LWECX:1)); - if (is_rep) LWECX = 0; - CPU_REG_LW(eip)++; - break; - - case 0x6f: /* (rep) outsw / outsd */ - if (pref_seg < 0) pref_seg = CPU_REG_LW(ds); - /* WARNING: no test for _SI wrapping! */ - if (prefix66) { - CPU_REG_LW(esi) += port_rep_outl(CPU_REG_LW(edx), - (CARD32 *)LIN_PREF_SI, - CPU_REG_LW(eflags)&DF, - (is_rep? LWECX:1)); - } - else { - CPU_REG_LW(esi) += port_rep_outw(CPU_REG_LW(edx), - (CARD16 *)LIN_PREF_SI, - CPU_REG_LW(eflags)&DF, - (is_rep? LWECX:1)); - } - if (is_rep) LWECX = 0; - CPU_REG_LW(eip)++; - break; - - case 0xe5: /* inw xx, inl xx */ - if (prefix66) CPU_REG(eax) = P.inl((int) csp[1]); - else CPU_REG_LW(eax) = P.inw((int) csp[1]); - CPU_REG_LW(eip) += 2; - break; - case 0xe4: /* inb xx */ - CPU_REG_LW(eax) &= ~(CARD32)0xff; - CPU_REG_LB(ax) |= P.inb((int) csp[1]); - CPU_REG_LW(eip) += 2; - break; - case 0xed: /* inw dx, inl dx */ - if (prefix66) CPU_REG(eax) = P.inl(CPU_REG_LW(edx)); - else CPU_REG_LW(eax) = P.inw(CPU_REG_LW(edx)); - CPU_REG_LW(eip) += 1; - break; - case 0xec: /* inb dx */ - CPU_REG_LW(eax) &= ~(CARD32)0xff; - CPU_REG_LB(ax) |= P.inb(CPU_REG_LW(edx)); - CPU_REG_LW(eip) += 1; - break; - - case 0xe7: /* outw xx */ - if (prefix66) P.outl((int)csp[1], CPU_REG(eax)); - else P.outw((int)csp[1], CPU_REG_LW(eax)); - CPU_REG_LW(eip) += 2; - break; - case 0xe6: /* outb xx */ - P.outb((int) csp[1], CPU_REG_LB(ax)); - CPU_REG_LW(eip) += 2; - break; - case 0xef: /* outw dx */ - if (prefix66) P.outl(CPU_REG_LW(edx), CPU_REG(eax)); - else P.outw(CPU_REG_LW(edx), CPU_REG_LW(eax)); - CPU_REG_LW(eip) += 1; - break; - case 0xee: /* outb dx */ - P.outb(CPU_REG_LW(edx), CPU_REG_LB(ax)); - CPU_REG_LW(eip) += 1; - break; - - case 0xf4: -#ifdef V86BIOS_DEBUG - printf("hlt at %p\n", lina); -#endif - return 0; - - case 0x0f: - fprintf(stderr,"CPU 0x0f Trap at eip=0x%lx\n",CPU_REG(eip)); - goto op0ferr; - break; - - case 0xf0: /* lock */ - default: - fprintf(stderr,"unknown reason for exception\n"); - dump_registers(); - stack_trace(); - op0ferr: - dump_code(); - fprintf(stderr,"cannot continue\n"); - return 0; - } /* end of switch() */ - return 1; -} - -static int -vm86_do_int(int num) -{ - int val; - struct regs86 regs; - - i_printf("int 0x%x received: ax:0x%lx",num,CPU_REG(eax)); - if (Config.PrintIp) - i_printf(" at: 0x%x\n",getIP()); - else - i_printf("\n"); - - /* try to run bios interrupt */ - - /* if not installed fall back */ -#define COPY(x) regs.##x = CPU_REG(x) -#define COPY_R(x) CPU_REG(x) = regs.##x - - COPY(eax); - COPY(ebx); - COPY(ecx); - COPY(edx); - COPY(esi); - COPY(edi); - COPY(ebp); - COPY(eip); - COPY(esp); - COPY(cs); - COPY(ss); - COPY(ds); - COPY(es); - COPY(fs); - COPY(gs); - COPY(eflags); - - if (!(val = int_handler(num,®s))) - if (!(val = run_bios_int(num,®s))) - return val; - - COPY_R(eax); - COPY_R(ebx); - COPY_R(ecx); - COPY_R(edx); - COPY_R(esi); - COPY_R(edi); - COPY_R(ebp); - COPY_R(eip); - COPY_R(esp); - COPY_R(cs); - COPY_R(ss); - COPY_R(ds); - COPY_R(es); - COPY_R(fs); - COPY_R(gs); - COPY_R(eflags); - - return val; -#undef COPY -#undef COPY_R -} - -static void -dump_code(void) -{ - int i; - unsigned char *lina = SEG_ADR((unsigned char *), cs, ip); - - fprintf(stderr,"code at 0x%8.8x: ",(CARD32)lina); - for (i=0; i<0x10; i++) - fprintf(stderr,"%2.2x ",*(lina + i)); - fprintf(stderr,"\n "); - for (; i<0x20; i++) - fprintf(stderr,"%2.2x ",*(lina + i)); - fprintf(stderr,"\n"); -} - -#define PRINT(x) fprintf(stderr,#x":%4.4x ",CPU_REG_LW(x)) -#define PRINT_FLAGS(x) fprintf(stderr,#x":%8.8x ",CPU_REG_LW(x)) -static void -dump_registers(void) -{ - PRINT(eip); - PRINT(eax); - PRINT(ebx); - PRINT(ecx); - PRINT(edx); - PRINT(esi); - PRINT(edi); - PRINT(ebp); - fprintf(stderr,"\n"); - PRINT(esp); - PRINT(cs); - PRINT(ss); - PRINT(es); - PRINT(ds); - PRINT(fs); - PRINT(gs); - PRINT_FLAGS(eflags); - fprintf(stderr,"\n"); -} - -static void -stack_trace(void) -{ - int i; - unsigned char *stack = SEG_ADR((unsigned char *), ss, sp); - - fprintf(stderr,"stack at 0x%8.8lx:\n",(unsigned long)stack); - for (i=0; i < 0x10; i++) - fprintf(stderr,"%2.2x ",*(stack + i)); - fprintf(stderr,"\n"); - -} - -static int -vm86_rep(struct vm86_struct *ptr) -{ - - int __res; - - __asm__ __volatile__("int $0x80\n" - :"=a" (__res):"a" ((int)113), - "b" ((struct vm86_struct *)ptr)); - - if ((__res) < 0) { - errno = -__res; - __res=-1; - } - else errno = 0; - return __res; -} - -#define pushw(base, ptr, val) \ -__asm__ __volatile__( \ - "decw %w0\n\t" \ - "movb %h2,(%1,%0)\n\t" \ - "decw %w0\n\t" \ - "movb %b2,(%1,%0)" \ - : "=r" (ptr) \ - : "r" (base), "q" (val), "0" (ptr)) - -int -run_bios_int(int num, struct regs86 *regs) -{ - CARD16 *ssp; - CARD32 sp; - CARD32 eflags; - -#ifdef V86BIOS_DEBUG - static int firsttime = 1; -#endif - /* check if bios vector is initialized */ - if (((CARD16*)0)[(num<<1)+1] == 0x0000) { /* SYS_BIOS_SEG ?*/ -#ifdef V86BIOS_DEBUG - i_printf("card BIOS not loaded\n"); -#endif - return 0; - } - -#ifdef V86BIOS_DEBUG - if (firsttime) { - dprint(0,0x3D0); - firsttime = 0; - } -#endif - - i_printf("calling card BIOS at: "); - ssp = (CARD16*)(CPU_REG(ss)<<4); - sp = (CARD32) CPU_REG_LW(esp); - - eflags = regs->eflags; - eflags = ((eflags & VIF_MASK) != 0) - ? (eflags | IF_MASK) : (eflags & ~(CARD32) IF_MASK); - pushw(ssp, sp, eflags); - pushw(ssp, sp, regs->cs); - pushw(ssp, sp, (CARD16)regs->eip); - regs->esp -= 6; - regs->cs = ((CARD16 *) 0)[(num << 1) + 1]; - regs->eip = (regs->eip & 0xFFFF0000) | ((CARD16 *) 0)[num << 1]; - i_printf("0x%x:%lx\n",regs->cs,regs->eip); -#ifdef V86BIOS_DEBUG - dump_code(); -#endif - regs->eflags = regs->eflags - & ~(VIF_MASK | TF_MASK | IF_MASK | NT_MASK); - return 1; -} - -CARD32 -getIntVect(int num) -{ - return ((CARD32*)0)[num]; -} - -CARD32 -getIP(void) -{ - return (CPU_REG(cs) << 4) + CPU_REG(eip); -} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c deleted file mode 100644 index 101c1f2..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c +++ /dev/null @@ -1,933 +0,0 @@ -/* - * Copyright 1999 Egbert Eich - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of the authors not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. The authors makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#define DELETE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(__alpha__) || defined (__ia64__) -#include -#elif defined(HAVE_SYS_PERM) -#include -#endif -#include "debug.h" -#include "v86bios.h" -#include "pci.h" -#include "AsmMacros.h" - -#define SIZE 0x100000 -#define VRAM_START 0xA0000 -#define VRAM_SIZE 0x1FFFF -#define V_BIOS_SIZE 0x1FFFF -#define BIOS_START 0x7C00 /* default BIOS entry */ -#define BIOS_MEM 0x600 - -/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0, 0xf4 }; */ -#define VB_X(x) (V_BIOS >> x) & 0xFF -CARD8 code[] = { 6, 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xf4 }; -/*CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xb8, 0x03, 0x00, */ -/*0xcd, 0x10, 0xf4 }; */ -/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0 ,0xf4 }; */ - -int ioperm_list[IOPERM_BITS] = {0,}; - -static void sig_handler(int); -static int map(void); -static void unmap(void); -static void bootBIOS(CARD16 ax); -static int map_vram(void); -static void unmap_vram(void); -static int copy_vbios(memType v_base); -static int copy_sys_bios(void); -static void save_bios_to_file(void); -static int setup_system_bios(void); -static CARD32 setup_int_vect(void); -#ifdef __ia32__ -static CARD32 setup_primary_int_vect(void); -#endif -static int chksum(CARD8 *start); -static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax); -static void print_regs(i86biosRegsPtr regs); -static void print_usage(void); -static void set_hlt(Bool set); -static void set_ioperm(void); - -extern void yyparse(); - -void loadCodeToMem(unsigned char *ptr, CARD8 *code); -void dprint(unsigned long start, unsigned long size); - -static int vram_mapped = 0; -static char* bios_var = NULL; -static CARD8 save_msr; -static CARD8 save_pos102; -static CARD8 save_vse; -static CARD8 save_46e8; -static haltpoints hltp[20] = { {0, 0}, }; - -console Console = {-1,-1}; -struct config Config; - -int main(int argc,char **argv) -{ - int c; - - Config.PrintPort = PRINT_PORT; - Config.IoStatistics = IO_STATISTICS; - Config.PrintIrq = PRINT_IRQ; - Config.PrintPci = PRINT_PCI; - Config.ShowAllDev = SHOW_ALL_DEV; - Config.PrintIp = PRINT_IP; - Config.SaveBios = SAVE_BIOS; - Config.Trace = TRACE; - Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY; /* boot */ - Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE; /* boot */ - Config.MapSysBios = MAP_SYS_BIOS; - Config.Resort = RESORT; /* boot */ - Config.FixRom = FIX_ROM; - Config.NoConsole = NO_CONSOLE; - Config.BootOnly = FALSE; - Config.Verbose = VERBOSE; - - opterr = 0; - while ((c = getopt(argc,argv,"psicaPStAdbrfnv:?")) != EOF) { - switch(c) { - case 'p': - Config.PrintPort = TRUE; - break; - case 's': - Config.IoStatistics = TRUE; - break; - case 'i': - Config.PrintIrq = TRUE; - break; - case 'c': - Config.PrintPci = TRUE; - break; - case 'a': - Config.ShowAllDev = TRUE; - break; - case 'P': - Config.PrintIp = TRUE; - break; - case 'S': - Config.SaveBios = TRUE; - break; - case 't': - Config.Trace = TRUE; - break; - case 'A': - Config.ConfigActiveOnly = TRUE; - break; - case 'd': - Config.ConfigActiveDevice = TRUE; - break; - case 'b': - Config.MapSysBios = TRUE; - break; - case 'r': - Config.Resort = TRUE; - break; - case 'f': - Config.FixRom = TRUE; - break; - case 'n': - Config.NoConsole = TRUE; - break; - case 'v': - Config.Verbose = strtol(optarg,NULL,0); - break; - case '?': - print_usage(); - break; - default: - break; - } - } - - - if (!map()) - exit(1); - - if (!setup_system_bios()) - exit(1); - - iopl(3); - - scan_pci(); - - save_msr = inb(0x3CC); - save_vse = inb(0x3C3); - save_46e8 = inb(0x46e8); - save_pos102 = inb(0x102); - - if (Config.BootOnly) { - - if (!CurrentPci && !Config.ConfigActiveDevice - && !Config.ConfigActiveOnly) { - iopl(0); - unmap(); - exit (1); - } - call_boot(NULL); - } else { - using_history(); - yyparse(); - } - - unmap(); - - pciVideoRestore(); - - outb(0x102, save_pos102); - outb(0x46e8, save_46e8); - outb(0x3C3, save_vse); - outb(0x3C2, save_msr); - - iopl(0); - - close_console(Console); - - exit(0); -} - - -void -call_boot(struct device *dev) -{ - int Active_is_Pci = 0; - CARD32 vbios_base; - - CurrentPci = PciList; - Console = open_console(); - - set_ioperm(); - - - signal(2,sig_handler); - signal(11,sig_handler); - - /* disable primary card */ - pciVideoRestore(); /* reset PCI state to see primary card */ - outb(0x3C2,~(CARD8)0x03 & save_msr); - outb(0x3C3,~(CARD8)0x01 & save_vse); - outb(0x46e8, ~(CARD8)0x08 & save_46e8); - outb(0x102, ~(CARD8)0x01 & save_pos102); - - pciVideoDisable(); - - while (CurrentPci) { - CARD16 ax; - - if (CurrentPci->active) { - Active_is_Pci = 1; - if (!Config.ConfigActiveDevice && !dev) { - CurrentPci = CurrentPci->next; - continue; - } - } else if (Config.ConfigActiveOnly && !dev) { - CurrentPci = CurrentPci->next; - continue; - } - if (dev && ((dev->type != PCI) - || (dev->type == PCI - && (dev->loc.pci.dev != CurrentPci->dev - || dev->loc.pci.bus != CurrentPci->bus - || dev->loc.pci.func != CurrentPci->func)))) { - CurrentPci = CurrentPci->next; - continue; - } - - EnableCurrent(); - - if (CurrentPci->active) { - outb(0x102, save_pos102); - outb(0x46e8, save_46e8); - outb(0x3C3, save_vse); - outb(0x3C2, save_msr); - } - - /* clear interrupt vectors */ -#ifdef __ia32__ - vbios_base = CurrentPci->active ? setup_primary_int_vect() - : setup_int_vect(); -#else - vbios_base = setup_int_vect(); -#endif - ax = ((CARD16)(CurrentPci->bus) << 8) - | (CurrentPci->dev << 3) | (CurrentPci->func & 0x7); - if (Config.Verbose > 1) P_printf("ax: 0x%x\n",ax); - - BootBios = findPciByIDs(CurrentPci->bus,CurrentPci->dev, - CurrentPci->func); - if (!((mapPciRom(BootBios) && chksum((CARD8*)V_BIOS)) - || (CurrentPci->active && copy_vbios(vbios_base)))) { - CurrentPci = CurrentPci->next; - continue; - } - if (!map_vram()) { - CurrentPci = CurrentPci->next; - continue; - } - if (Config.SaveBios) save_bios_to_file(); - printf("initializing PCI bus: %i dev: %i func: %i\n",CurrentPci->bus, - CurrentPci->dev,CurrentPci->func); - bootBIOS(ax); - unmap_vram(); - - if (CurrentPci->active) - close_console(Console); - - if (dev) return; - - CurrentPci = CurrentPci->next; - } - - /* We have an ISA device - configure if requested */ - if (!Active_is_Pci /* no isa card in system! */ - && ((!dev && (Config.ConfigActiveDevice || Config.ConfigActiveOnly)) - || (dev && dev->type == ISA))) { - - pciVideoDisable(); - - if (!dev || dev->type == ISA) { - outb(0x102, save_pos102); - outb(0x46e8, save_46e8); - outb(0x3C3, save_vse); - outb(0x3C2, save_msr); - -#ifdef __ia32__ - vbios_base = setup_primary_int_vect(); -#else - vbios_base = setup_int_vect(); -#endif - if (copy_vbios(vbios_base)) { - - if (Config.SaveBios) save_bios_to_file(); - if (map_vram()) { - printf("initializing ISA bus\n"); - bootBIOS(0); - } - } - - unmap_vram(); - sleep(1); - close_console(Console); - } - } - - -} - -int -map(void) -{ - void* mem; - mem = mmap(0, (size_t)SIZE, - PROT_EXEC | PROT_READ | PROT_WRITE, - MAP_FIXED | MAP_PRIVATE | MAP_ANON, - -1, 0 ); - if (mem != 0) { - perror("anonymous map"); - return (0); - } - memset(mem,0,SIZE); - - return (1); -} - -static void -unmap(void) -{ - munmap(0,SIZE); -} - -static void -bootBIOS(CARD16 ax) -{ - i86biosRegs bRegs; -#ifdef V86BIOS_DEBUG - printf("starting BIOS\n"); -#endif - setup_io(); - setup_bios_regs(&bRegs, ax); - loadCodeToMem((unsigned char *) BIOS_START, code); - do_x86(BIOS_START,&bRegs); -#ifdef V86BIOS_DEBUG - printf("done\n"); -#endif -} - -static int -map_vram(void) -{ - int mem_fd; - -#ifdef __ia64__ - if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) -#else - if ((mem_fd = open(MEM_FILE,O_RDWR))<0) -#endif - { - perror("opening memory"); - return 0; - } - -#ifdef __alpha__ - if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */ - if (!_bus_base_sparse()) sparse_shift = 0; - if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift), - PROT_READ | PROT_WRITE, - MAP_SHARED, - mem_fd, (VRAM_START << sparse_shift) - | _bus_base_sparse())) == (void *) -1) -#else - if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE, - PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, - mem_fd, VRAM_START) == (void *) -1) -#endif - { - perror("mmap error in map_hardware_ram (1)"); - close(mem_fd); - return (0); - } - vram_mapped = 1; - close(mem_fd); - return (1); -} - -static void -unmap_vram(void) -{ - if (!vram_mapped) return; - - munmap((void*)VRAM_START,VRAM_SIZE); - vram_mapped = 0; -} - -static int -copy_vbios(memType v_base) -{ - int mem_fd; - unsigned char *tmp; - int size; - - if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { - perror("opening memory"); - return (0); - } - - if (lseek(mem_fd,(off_t) v_base, SEEK_SET) != (off_t) v_base) { - fprintf(stderr,"Cannot lseek\n"); - goto Error; - } - tmp = (unsigned char *)malloc(3); - if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) { - fprintf(stderr,"Cannot read\n"); - goto Error; - } - if (lseek(mem_fd,(off_t) v_base,SEEK_SET) != (off_t) v_base) - goto Error; - - if (*tmp != 0x55 || *(tmp+1) != 0xAA ) { - fprintf(stderr,"No bios found at: 0x%lx\n",v_base); - goto Error; - } -#ifdef DEBUG - dprint((unsigned long)tmp,0x100); -#endif - size = *(tmp+2) * 512; - - if (read(mem_fd, (char *)v_base, (size_t) size) != (size_t) size) { - fprintf(stderr,"Cannot read\n"); - goto Error; - } - free(tmp); - close(mem_fd); - if (!chksum((CARD8*)v_base)) - return (0); - - return (1); - -Error: - perror("v_bios"); - close(mem_fd); - return (0); -} - -static int -copy_sys_bios(void) -{ -#define SYS_BIOS 0xF0000 - int mem_fd; - - if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { - perror("opening memory"); - return (0); - } - - if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS) - goto Error; - if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF) - goto Error; - - close(mem_fd); - return (1); - -Error: - perror("sys_bios"); - close(mem_fd); - return (0); -} - -void -loadCodeToMem(unsigned char *ptr, CARD8 code[]) -{ - int i; - CARD8 val; - int size = code[0]; - - for ( i=1;i<=size;i++) { - val = code[i]; - *ptr++ = val; - } - return; -} - -void -dprint(unsigned long start, unsigned long size) -{ - int i,j; - char *c = (char *)start; - - for (j = 0; j < (size >> 4); j++) { - char *d = c; - printf("\n0x%lx: ",(unsigned long)c); - for (i = 0; i<16; i++) - printf("%2.2x ",(unsigned char) (*(c++))); - c = d; - for (i = 0; i<16; i++) { - printf("%c",((((CARD8)(*c)) > 32) && (((CARD8)(*c)) < 128)) ? - (unsigned char) (*(c)): '.'); - c++; - } - } - printf("\n"); -} - -static void -save_bios_to_file(void) -{ - static int num = 0; - int size, count; - char file_name[256]; - int fd; - - sprintf(file_name,"bios_%i.fil",num); - if ((fd = open(file_name,O_WRONLY | O_CREAT | O_TRUNC,00644)) == -1) - return; - size = (*(unsigned char*)(V_BIOS + 2)) * 512; -#ifdef V86BIOS_DEBUG - dprint(V_BIOS,20); -#endif - if ((count = write(fd,(void *)(V_BIOS),size)) != size) - fprintf(stderr,"only saved %i of %i bytes\n",size,count); - num++; -} - -static void -sig_handler(int unused) -{ - fflush(stdout); - fflush(stderr); - - /* put system back in a save state */ - unmap_vram(); - pciVideoRestore(); - outb(0x102, save_pos102); - outb(0x46e8, save_46e8); - outb(0x3C3, save_vse); - outb(0x3C2, save_msr); - - close_console(Console); - iopl(0); - unmap(); - - exit(1); -} - -/* - * For initialization we just pass ax to the BIOS. - * PCI BIOSes need this. All other register are set 0. - */ -static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax) -{ - regs->ax = ax; - regs->bx = 0; - regs->cx = 0; - regs->dx = 0; - regs->es = 0; - regs->ds = 0x40; /* standard pc ds */ - regs->si = 0; - regs->di = 0; -} - -/* - * here we are really paranoid about faking a "real" - * BIOS. Most of this information was pulled from - * dosem. - */ - -#ifdef __ia32__ -static CARD32 -setup_primary_int_vect(void) -{ - int mem_fd; - CARD32 vbase; - void *map; - - if ((mem_fd = open(MEM_FILE,O_RDWR))<0) - { - perror("opening memory"); - return (0); - } - - if ((map = mmap((void *) 0, (size_t) 0x2000, - PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, - mem_fd, 0)) == (void *)-1) { - perror("mmap error in map_hardware_ram (2)"); - close(mem_fd); - return (0); - } - - close(mem_fd); - memcpy(0,map,BIOS_MEM); - munmap(map,0x2000); - /* - * create a backup copy of the bios variables to write back the - * modified values - */ - if (!bios_var) - bios_var = (char *)malloc(BIOS_MEM); - memcpy(bios_var,0,BIOS_MEM); - - vbase = (*((CARD16*)(0x10 << 2) + 1)) << 4; - if (Config.Verbose > 0) printf("vbase: 0x%x\n",vbase); - return vbase; -} -#endif - -static CARD32 -setup_int_vect(void) -{ - const CARD16 cs = 0x0; - const CARD16 ip = 0x0; - int i; - - /* let the int vects point to the SYS_BIOS seg */ - for (i=0; i<0x80; i++) { - ((CARD16*)0)[i<<1] = ip; - ((CARD16*)0)[(i<<1)+1] = cs; - } - /* video interrupts default location */ - ((CARD16*)0)[(0x42<<1)+1] = 0xf000; - ((CARD16*)0)[0x42<<1] = 0xf065; - ((CARD16*)0)[(0x10<<1)+1] = 0xf000; - ((CARD16*)0)[0x10<<1] = 0xf065; - /* video param table default location (int 1d) */ - ((CARD16*)0)[(0x1d<<1)+1] = 0xf000; - ((CARD16*)0)[0x1d<<1] = 0xf0A4; - /* font tables default location (int 1F) */ - ((CARD16*)0)[(0x1f<<1)+1] = 0xf000; - ((CARD16*)0)[0x1f<<1] = 0xfa6e; - - /* int 11 default location */ - ((CARD16*)0)[(0x11<<1)+1] = 0xf000; - ((CARD16*)0)[0x11<<1] = 0xf84d; - /* int 12 default location */ - ((CARD16*)0)[(0x12<<1)+1] = 0xf000; - ((CARD16*)0)[0x12<<1] = 0xf841; - /* int 15 default location */ - ((CARD16*)0)[(0x15<<1)+1] = 0xf000; - ((CARD16*)0)[0x15<<1] = 0xf859; - /* int 1A default location */ - ((CARD16*)0)[(0x1a<<1)+1] = 0xf000; - ((CARD16*)0)[0x1a<<1] = 0xff6e; - /* int 05 default location */ - ((CARD16*)0)[(0x05<<1)+1] = 0xf000; - ((CARD16*)0)[0x05<<1] = 0xff54; - /* int 08 default location */ - ((CARD16*)0)[(0x8<<1)+1] = 0xf000; - ((CARD16*)0)[0x8<<1] = 0xfea5; - /* int 13 default location (fdd) */ - ((CARD16*)0)[(0x13<<1)+1] = 0xf000; - ((CARD16*)0)[0x13<<1] = 0xec59; - /* int 0E default location */ - ((CARD16*)0)[(0xe<<1)+1] = 0xf000; - ((CARD16*)0)[0xe<<1] = 0xef57; - /* int 17 default location */ - ((CARD16*)0)[(0x17<<1)+1] = 0xf000; - ((CARD16*)0)[0x17<<1] = 0xefd2; - /* fdd table default location (int 1e) */ - ((CARD16*)0)[(0x1e<<1)+1] = 0xf000; - ((CARD16*)0)[0x1e<<1] = 0xefc7; - return V_BIOS; -} - -static int -setup_system_bios(void) -{ - char *date = "06/01/99"; - char *eisa_ident = "PCI/ISA"; - - if (Config.MapSysBios) { - - if (!copy_sys_bios()) return 0; - return 1; - - } else { - -/* memset((void *)0xF0000,0xf4,0xfff7); */ - - /* - * we trap the "industry standard entry points" to the BIOS - * and all other locations by filling them with "hlt" - * TODO: implement hlt-handler for these - */ - memset((void *)0xF0000,0xf4,0x10000); - - /* - * TODO: we should copy the fdd table (0xfec59-0xfec5b) - * the video parameter table (0xf0ac-0xf0fb) - * and the font tables (0xfa6e-0xfe6d) - * from the original bios here - */ - - /* set bios date */ - strcpy((char *)0xFFFF5,date); - /* set up eisa ident string */ - strcpy((char *)0xFFFD9,eisa_ident); - /* write system model id for IBM-AT */ - ((char *)0)[0xFFFFE] = 0xfc; - - return 1; - } - -} - -static void -update_bios_vars(void) -{ - int mem_fd; - void *map; - memType i; - -#ifdef __ia64__ - if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) -#else - if ((mem_fd = open(MEM_FILE,O_RDWR))<0) -#endif - { - perror("opening memory"); - return; - } - - if ((map = mmap((void *) 0, (size_t) 0x2000, - PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, - mem_fd, 0)) == (void *)-1) { - perror("mmap error in map_hardware_ram (3)"); - close(mem_fd); - return; - } - - for (i = 0; i < BIOS_MEM; i++) { - if (bios_var[i] != *(CARD8*)i) - *((CARD8*)map + i) = *(CARD8*)i; - } - - munmap(map,0x2000); - close(mem_fd); -} - -static int -chksum(CARD8 *start) -{ - CARD16 size; - CARD8 val = 0; - int i; - - size = *(start+2) * 512; - for (i = 0; iactive)) || !isVideo) { - CARD32 vbios_base; - -#ifdef __ia32__ - if (!(vbios_base = setup_primary_int_vect())) -#else - if (!(vbios_base = setup_int_vect())) -#endif - return; - if (!copy_vbios(vbios_base)) - return; - } - - if (!map_vram()) - return; - -#ifdef V86BIOS_DEBUG - printf("starting BIOS\n"); -#endif - loadCodeToMem((unsigned char *) BIOS_START, code_int); - setup_io(); - print_regs(Regs); - set_ioperm(); - set_hlt(TRUE); - do_x86(BIOS_START,Regs); - set_hlt(FALSE); - print_regs(Regs); - -#ifdef V86BIOS_DEBUG - printf("done\n"); -#endif - - if ((isVideo && (!CurrentPci || CurrentPci->active)) || !isVideo) - update_bios_vars(); -} - -static void -print_regs(i86biosRegsPtr regs) -{ - printf("ax=%x bx=%x cx=%x dx=%x ds=%x es=%x di=%x si=%x\n", - (CARD16)regs->ax,(CARD16)regs->bx,(CARD16)regs->cx,(CARD16)regs->dx, - (CARD16)regs->ds,(CARD16)regs->es,(CARD16)regs->di, - (CARD16)regs->si); -} - -static void -print_usage(void) -{ -} - -void -add_hlt(unsigned long val) -{ - int i; - - if (val < BIOS_MEM || (val > VRAM_START && val < (VRAM_START + VRAM_SIZE)) - || val >= SIZE) { - printf("address out of range\n"); - return; - } - - for (i=0; i<20; i++) { - if (hltp[i].address == 0) { - hltp[i].address = (void*)val; - break; - } - } - if (i == 20) printf("no more hltpoints available\n"); -} - -void -del_hlt(int val) -{ - if (val == 21) { /* delete all */ - int i; - printf("clearing all hltpoints\n"); - for (i=0; i <20; i++) - hltp[i].address = NULL; - } else if (val >= 0 && val <20) - hltp[val].address = NULL; - else printf("hltpoint %i out of range: valid range 0-19\n",val); -} - -void -list_hlt() -{ - int i; - for (i=0; i<20; i++) - if (hltp[i].address) - printf("hltpoint[%i]: 0x%lx\n",i,(unsigned long)hltp[i].address); -} - -static void -set_hlt(Bool set) -{ - int i; - for (i=0; i<20; i++) - if (hltp[i].address) { - if (set) { - hltp[i].orgval = *(CARD8*)hltp[i].address; - *(CARD8*)hltp[i].address = 0xf4; - } else - *(CARD8*)hltp[i].address = hltp[i].orgval; - } -} - -static void -set_ioperm(void) -{ - int i, start; - - ioperm(0,IOPERM_BITS,0); - - for (i = 0; i < IOPERM_BITS;i++) - if (ioperm_list[i]) { - start = i; - for (;i < IOPERM_BITS; i++) { - if (!ioperm_list[i]) { - ioperm(start,i - start, 1); - break; - } - } - } -} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h deleted file mode 100644 index a8f3f8e..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 1999 Egbert Eich - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of the authors not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. The authors makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#ifndef V86_BIOS_H -#define V86_BIOS_H - -#if defined (__i386__) || defined (__i486__) || defined (__i586__) || defined (__i686__) || defined (__k6__) -# ifndef __ia32__ -# define __ia32__ -# endif -#endif - -#include - -#define p_printf(f,a...) do {if (Config.PrintPort) lprintf(f,##a);} \ - while(0) -#define i_printf(f,a...) do {if (Config.PrintIrq) lprintf(f,##a);} \ - while(0) -#define P_printf(f,a...) do {if (Config.PrintPci) lprintf(f,##a);} \ - while(0) - -typedef unsigned char CARD8; -typedef unsigned short CARD16; -typedef unsigned int CARD32; -#if defined (__alpha__) || defined (__ia64__) -typedef unsigned long memType; -#else -typedef unsigned int memType; -#endif - -typedef int Bool; - -#define FALSE 0 -#define TRUE 1 - -struct config { - Bool PrintPort; - Bool IoStatistics; - Bool PrintIrq; - Bool PrintPci; - Bool ShowAllDev; - Bool PrintIp; - Bool SaveBios; - Bool Trace; - Bool ConfigActiveOnly; - Bool ConfigActiveDevice; - Bool MapSysBios; - Bool Resort; - Bool FixRom; - Bool NoConsole; - Bool BootOnly; - int Verbose; -}; - -struct pio { - CARD8 (*inb)(CARD16); - CARD16 (*inw)(CARD16); - CARD32 (*inl)(CARD16); - void (*outb)(CARD16,CARD8); - void (*outw)(CARD16,CARD16); - void (*outl)(CARD16,CARD32); -}; - -struct regs86 { - long ebx; - long ecx; - long edx; - long esi; - long edi; - long ebp; - long eax; - long eip; - long esp; - unsigned short cs; - unsigned short ss; - unsigned short es; - unsigned short ds; - unsigned short fs; - unsigned short gs; - long eflags; -}; - -typedef struct { - CARD32 ax; - CARD32 bx; - CARD32 cx; - CARD32 dx; - CARD32 cs; - CARD32 es; - CARD32 ds; - CARD32 si; - CARD32 di; -} i86biosRegs, *i86biosRegsPtr; - -typedef struct { - int fd; - int vt; -} console; - -typedef struct { - void* address; - CARD8 orgval; -} haltpoints; - -enum dev_type { NONE, ISA, PCI }; -struct device { - Bool booted; - enum dev_type type; - union { - int none; - struct pci { - int bus; - int dev; - int func; - } pci; - } loc; -}; - -extern struct device Device; - -#ifdef __alpha__ -unsigned long _bus_base(void); -extern void* vram_map; -extern int sparse_shift; -#endif - -extern struct pio P; -extern struct config Config; -#define IOPERM_BITS 1024 -extern int ioperm_list[IOPERM_BITS]; - -extern void setup_io(void); -extern void do_x86(unsigned long bios_start,i86biosRegsPtr regs); -extern int run_bios_int(int num, struct regs86 *regs); -extern CARD32 getIntVect(int num); -CARD32 getIP(void); - -extern void call_boot(struct device *dev); -extern void runINT(int num,i86biosRegsPtr Regs); -extern void add_hlt(unsigned long addr); -extern void del_hlt(int addr); -extern void list_hlt(); - -extern int port_rep_inb(CARD16 port, CARD8 *base, int d_f, CARD32 count); -extern int port_rep_inw(CARD16 port, CARD16 *base, int d_f, CARD32 count); -extern int port_rep_inl(CARD16 port, CARD32 *base, int d_f, CARD32 count); -extern int port_rep_outb(CARD16 port, CARD8 *base, int d_f, CARD32 count); -extern int port_rep_outw(CARD16 port, CARD16 *base, int d_f, CARD32 count); -extern int port_rep_outl(CARD16 port, CARD32 *base, int d_f, CARD32 count); -extern CARD8 p_inb(CARD16 port); -extern CARD16 p_inw(CARD16 port); -extern CARD32 p_inl(CARD16 port); -extern void p_outb(CARD16 port, CARD8 val); -extern void p_outw(CARD16 port, CARD16 val); -extern void p_outl(CARD16 port, CARD32 val); -#ifdef __alpha__ -extern CARD8 a_inb(CARD16 port); -extern CARD16 a_inw(CARD16 port); -extern void a_outb(CARD16 port, CARD8 val); -extern void a_outw(CARD16 port, CARD16 val); -#endif -#ifdef __alpha__ -CARD8 mem_rb(CARD32 addr); -CARD16 mem_rw(CARD32 addr); -CARD32 mem_rl(CARD32 addr); -void mem_wb(CARD32 addr, CARD8 val); -void mem_ww(CARD32 addr, CARD16 val); -void mem_wl(CARD32 addr, CARD32 val); -#endif -extern void io_statistics(void); -extern void clear_stat(void); -extern int int_handler(int num, struct regs86 *regs); - -extern console open_console(void); -extern void close_console(console); - -extern void dprint(unsigned long start, unsigned long size); - -extern Bool logging; -extern Bool nostdout; -extern char* logfile; -extern void logon(void* ptr); -extern void logoff(); -extern void lprintf(const char *f, ...); - -#define MEM_FILE "/dev/mem" -#define DEFAULT_V_BIOS 0xc0000 -#ifndef V_BIOS -#define V_BIOS DEFAULT_V_BIOS -#endif - -#ifdef __alpha__ -#define NEED_PCI_IO -#endif - -#endif diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/working_cards b/board/MAI/bios_emulator/scitech/src/v86bios/working_cards deleted file mode 100644 index 7753f24..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/working_cards +++ /dev/null @@ -1,7 +0,0 @@ -David Monro: Trident TGUI 9440 - Virge/VX (Diamond Stealth 3D 3400) - Riva TNT (Diamond Viper V550) no vbios? -Jarno Paananen : Guillemot Maxigamer Xentor 32 - (NVIDIA TNT2 Ultra) - Creative Graphics Blaster Exxtreme - (Permedia 2) diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c b/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c deleted file mode 100644 index b5c99d7..0000000 --- a/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright 1999 Egbert Eich - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of the authors not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. The authors makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - */ -#include "debug.h" - -#define IF_MASK 0x00000200 -#define VIF_MASK 0x00080000 /* virtual interrupt flag */ -#define VIP_MASK 0x00100000 /* virtual interrupt pending */ - -#include -#include -#include -/*#include */ -#include -#include -#include -#include -#ifdef __alpha__ -#include -#endif -#include -#include -#include "AsmMacros.h" -#include "v86bios.h" -# define DEBUG -#include "x86emu.h" -#undef DEBUG - -#define M _X86EMU_env -#define CPU_REG(reg) M.x86.R_##reg - -struct pio P; - -void -setup_io(void) -{ - if (!Config.PrintPort && !Config.IoStatistics) { - -#if defined (__i386__) - P.inb = (u8(*)(u16))inb; - P.inw = (u16(*)(u16))inw; - P.outb = (void(*)(u16,u8))outb; - P.outw = (void(*)(u16,u16))outw; -#else - P.inb = p_inb; - P.inw = p_inw; - P.outb = p_outb; - P.outw = p_outw; -#endif -#if defined (__i386__) && ! defined(NEED_PCI_IO) - P.inl = (u32(*)(u16))inl; - P.outl = (void(*)(u16,u32))outl; -#else - P.inl = p_inl; - P.outl = p_outl; -#endif - } else { - P.inb = p_inb; - P.inw = p_inw; - P.inl = p_inl; - P.outb = p_outb; - P.outw = p_outw; - P.outl = p_outl; - } -} - -void -x86emu_do_int(int num) -{ - struct regs86 regs; - - i_printf("int 0x%x received: ax:0x%x",num,CPU_REG(AX)); - if (Config.PrintIp) - i_printf(" at: 0x%x\n",getIP()); - else - i_printf("\n"); - - /* try to run bios interrupt */ - - /* if not installed fall back */ -#define COPY(x,y) regs.y = M.x86.x -#define COPY_R(x,y) M.x86.x = regs.y - - COPY(R_EAX,eax); - COPY(R_EBX,ebx); - COPY(R_ECX,ecx); - COPY(R_EDX,edx); - COPY(R_ESI,esi); - COPY(R_EDI,edi); - COPY(R_EBP,ebp); - COPY(R_EIP,eip); - COPY(R_ESP,esp); - COPY(R_CS,cs); - COPY(R_SS,ss); - COPY(R_DS,ds); - COPY(R_ES,es); - COPY(R_FS,fs); - COPY(R_GS,gs); - COPY(R_EFLG,eflags); - - if (!(int_handler(num,®s))) { - if (!run_bios_int(num,®s)) - goto unknown_int; - else - return; - } - - COPY_R(R_EAX,eax); - COPY_R(R_EBX,ebx); - COPY_R(R_ECX,ecx); - COPY_R(R_EDX,edx); - COPY_R(R_ESI,esi); - COPY_R(R_EDI,edi); - COPY_R(R_EBP,ebp); - COPY_R(R_EIP,eip); - COPY_R(R_ESP,esp); - COPY_R(R_CS,cs); - COPY_R(R_SS,ss); - COPY_R(R_DS,ds); - COPY_R(R_ES,es); - COPY_R(R_FS,fs); - COPY_R(R_GS,gs); - COPY_R(R_EFLG,eflags); - return; - - unknown_int: - fprintf(stderr,"\nUnknown vm86_int: %X\n\n",num); - X86EMU_halt_sys(); - return; - -#undef COPY -#undef COPY_R -} - -void -setup_x86emu(unsigned long bios_start, i86biosRegsPtr regs) -{ - int i; - CARD32 eip; - CARD16 cs; - X86EMU_intrFuncs intFuncs[256]; - - X86EMU_pioFuncs pioFuncs = { - (u8(*)(u16))P.inb, - (u16(*)(u16))P.inw, - (u32(*)(u16))P.inl, - (void(*)(u16,u8))P.outb, - (void(*)(u16,u16))P.outw, - (void(*)(u16,u32))P.outl - }; -#ifdef __alpha__ - X86EMU_memFuncs memFuncs = { - (u8(*)(u32))mem_rb, - (u16(*)(u32))mem_rw, - (u32(*)(u32))mem_rl, - (void(*)(u32,u8))mem_wb, - (void(*)(u32,u16))mem_ww, - (void(*)(u32,u32))mem_wl - }; -#endif - M.mem_base = 0; - M.mem_size = 1024*1024 + 1024; - /* M.x86.debug = DEBUG_DISASSEMBLE_F | DEBUG_TRACE_F | DEBUG_DECODE_F; */ - /* M.x86.debug |= DEBUG_DECODE_F | DEBUG_TRACE_F; */ -/* - * For single step tracing compile x86emu with option -DDEBUG - */ - M.x86.debug = 0; - if (Config.PrintIp) - M.x86.debug = DEBUG_SAVE_CS_IP; - - if (Config.Trace) - X86EMU_trace_on(); - - X86EMU_setupPioFuncs(&pioFuncs); -#ifdef __alpha__ - X86EMU_setupMemFuncs(&memFuncs); -#endif - for (i=0;i<256;i++) - intFuncs[i] = x86emu_do_int; - X86EMU_setupIntrFuncs(intFuncs); - - eip = bios_start & 0xFFFF; - cs = (bios_start & 0xFF0000) >> 4; - - CPU_REG(EAX) = regs->ax; - CPU_REG(EBX) = regs->bx; - CPU_REG(ECX) = regs->cx; - CPU_REG(EDX) = regs->dx; - CPU_REG(ESI) = regs->si; - CPU_REG(EDI) = regs->di; - CPU_REG(EBP) = 0; - CPU_REG(EIP) = eip; - CPU_REG(CS) = cs; - CPU_REG(SP) = 0x100; - CPU_REG(SS) = 0x30; /* This is the standard pc bios stack */ - CPU_REG(ES) = regs->es; - CPU_REG(DS) = regs->ds; - CPU_REG(FS) = 0; - CPU_REG(GS) = 0; - CPU_REG(EFLG) |= (VIF_MASK | VIP_MASK | IF_MASK | 0x2); -} - -void -collect_bios_regs(i86biosRegsPtr regs) -{ - regs->ax = CPU_REG(EAX); - regs->bx = CPU_REG(EBX); - regs->cx = CPU_REG(ECX); - regs->dx = CPU_REG(EDX); - regs->es = CPU_REG(ES); - regs->ds = CPU_REG(DS); - regs->di = CPU_REG(EDI); - regs->si = CPU_REG(ESI); -} - -static void -do_x86emu(void) -{ - X86EMU_exec(); -} - -static jmp_buf x86_esc; -static void -vmexit(int unused) -{ - longjmp(x86_esc,1); -} - -void -do_x86(unsigned long bios_start, i86biosRegsPtr regs) -{ - static void (*org_handler)(int); - - setup_x86emu(bios_start,regs); - if (setjmp(x86_esc) == 0) { - org_handler = signal(2,vmexit); - do_x86emu(); - signal(2,org_handler); - collect_bios_regs(regs); - } else { - signal(2,org_handler); - printf("interrupted at 0x%x\n",((CARD16)CPU_REG(CS)) << 4 - | (CARD16)CPU_REG(EIP)); - } -} - -int -run_bios_int(int num, struct regs86 *regs) -{ -#ifdef V86BIOS_DEBUG - static int firsttime = 1; -#endif - /* check if bios vector is initialized */ - if (((CARD16*)0)[(num<<1)+1] == 0x0000) { /* SYS_BIOS_SEG ?*/ -#ifdef V86BIOS_DEBUG - i_printf("card BIOS not loaded\n"); -#endif - return 0; - } - -#ifdef V86BIOS_DEBUG - if (firsttime) { - dprint(0,0x3D0); - firsttime = 0; - } -#endif - - i_printf("calling card BIOS at: "); - i_printf("0x%x:%x\n",((CARD16 *) 0)[(num << 1) + 1], - (CARD32)((CARD16 *) 0)[num << 1]); - X86EMU_prepareForInt(num); - - return 1; -} - -CARD32 -getIntVect(int num) -{ - return ((CARD32*)0)[num]; -} -#if 0 -void -printk(const char *fmt, ...) -{ - va_list argptr; - va_start(argptr, fmt); - vfprintf(stdout, fmt, argptr); - fflush(stdout); - va_end(argptr); -} -#endif - -CARD32 -getIP(void) -{ - return (M.x86.saved_cs << 4) + M.x86.saved_ip; -} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE b/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE deleted file mode 100644 index a3ede4a..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE +++ /dev/null @@ -1,17 +0,0 @@ - License information - ------------------- - -The x86emu library is under a BSD style license, comaptible -with the XFree86 and X licenses used by XFree86. The -original x86emu libraries were under the GNU General Public -License. Due to license incompatibilities between the GPL -and the XFree86 license, the original authors of the code -decided to allow a license change. If you have submitted -code to the original x86emu project, and you don't agree -with the license change, please contact us and let you -know. Your code will be removed to comply with your wishes. - -If you have any questions about this, please send email to -x86emu@linuxlabs.com or KendallB@scitechsoft.com for -clarification. - diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/debug.c b/board/MAI/bios_emulator/scitech/src/x86emu/debug.c deleted file mode 100644 index 235e6ac..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/debug.c +++ /dev/null @@ -1,443 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: This file contains the code to handle debugging of the -* emulator. -* -****************************************************************************/ - -#include "x86emu/x86emui.h" -#include -#include - -/*----------------------------- Implementation ----------------------------*/ - -#ifdef DEBUG - -static void print_encoded_bytes (u16 s, u16 o); -static void print_decoded_instruction (void); -static int parse_line (char *s, int *ps, int *n); - -/* should look something like debug's output. */ -void X86EMU_trace_regs (void) -{ - if (DEBUG_TRACE()) { - x86emu_dump_regs(); - } - if (DEBUG_DECODE() && ! DEBUG_DECODE_NOPRINT()) { - printk("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); - print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); - print_decoded_instruction(); - } -} - -void X86EMU_trace_xregs (void) -{ - if (DEBUG_TRACE()) { - x86emu_dump_xregs(); - } -} - -void x86emu_just_disassemble (void) -{ - /* - * This routine called if the flag DEBUG_DISASSEMBLE is set kind - * of a hack! - */ - printk("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); - print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); - print_decoded_instruction(); -} - -static void disassemble_forward (u16 seg, u16 off, int n) -{ - X86EMU_sysEnv tregs; - int i; - u8 op1; - /* - * hack, hack, hack. What we do is use the exact machinery set up - * for execution, except that now there is an additional state - * flag associated with the "execution", and we are using a copy - * of the register struct. All the major opcodes, once fully - * decoded, have the following two steps: TRACE_REGS(r,m); - * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to - * the preprocessor. The TRACE_REGS macro expands to: - * - * if (debug&DEBUG_DISASSEMBLE) - * {just_disassemble(); goto EndOfInstruction;} - * if (debug&DEBUG_TRACE) trace_regs(r,m); - * - * ...... and at the last line of the routine. - * - * EndOfInstruction: end_instr(); - * - * Up to the point where TRACE_REG is expanded, NO modifications - * are done to any register EXCEPT the IP register, for fetch and - * decoding purposes. - * - * This was done for an entirely different reason, but makes a - * nice way to get the system to help debug codes. - */ - tregs = M; - tregs.x86.R_IP = off; - tregs.x86.R_CS = seg; - - /* reset the decoding buffers */ - tregs.x86.enc_str_pos = 0; - tregs.x86.enc_pos = 0; - - /* turn on the "disassemble only, no execute" flag */ - tregs.x86.debug |= DEBUG_DISASSEMBLE_F; - - /* DUMP NEXT n instructions to screen in straight_line fashion */ - /* - * This looks like the regular instruction fetch stream, except - * that when this occurs, each fetched opcode, upon seeing the - * DEBUG_DISASSEMBLE flag set, exits immediately after decoding - * the instruction. XXX --- CHECK THAT MEM IS NOT AFFECTED!!! - * Note the use of a copy of the register structure... - */ - for (i=0; i 256) return; - seg = fetch_data_word_abs(0,iv*4); - off = fetch_data_word_abs(0,iv*4+2); - printk("%04x:%04x ", seg, off); -} - -void X86EMU_dump_memory (u16 seg, u16 off, u32 amt) -{ - u32 start = off & 0xfffffff0; - u32 end = (off+16) & 0xfffffff0; - u32 i; - u32 current; - - current = start; - while (end <= off + amt) { - printk("%04x:%04x ", seg, start); - for (i=start; i< off; i++) - printk(" "); - for ( ; i< end; i++) - printk("%02x ", fetch_data_byte_abs(seg,i)); - printk("\n"); - start = end; - end = start + 16; - } -} - -void x86emu_single_step (void) -{ - char s[1024]; - int ps[10]; - int ntok; - int cmd; - int done; - int segment; - int offset; - static int breakpoint; - static int noDecode = 1; - - char *p; - - if (DEBUG_BREAK()) { - if (M.x86.saved_ip != breakpoint) { - return; - } else { - M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; - M.x86.debug |= DEBUG_TRACE_F; - M.x86.debug &= ~DEBUG_BREAK_F; - print_decoded_instruction (); - X86EMU_trace_regs(); - } - } - - done=0; - offset = M.x86.saved_ip; - while (!done) { - printk("-"); - /*p = fgets(s, 1023, stdin); */ - cons_gets(s); - cmd = parse_line(s, ps, &ntok); - switch(cmd) { - case 'u': - disassemble_forward(M.x86.saved_cs,(u16)offset,10); - break; - case 'd': - if (ntok == 2) { - segment = M.x86.saved_cs; - offset = ps[1]; - X86EMU_dump_memory(segment,(u16)offset,16); - offset += 16; - } else if (ntok == 3) { - segment = ps[1]; - offset = ps[2]; - X86EMU_dump_memory(segment,(u16)offset,16); - offset += 16; - } else { - segment = M.x86.saved_cs; - X86EMU_dump_memory(segment,(u16)offset,16); - offset += 16; - } - break; - case 'c': - M.x86.debug ^= DEBUG_TRACECALL_F; - break; - case 's': - M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; - break; - case 'r': - X86EMU_trace_regs(); - break; - case 'x': - X86EMU_trace_xregs(); - break; - case 'g': - if (ntok == 2) { - breakpoint = ps[1]; - printk("breakpoint set to 0x%X\n", breakpoint); - if (noDecode) { - M.x86.debug |= DEBUG_DECODE_NOPRINT_F; - } else { - M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; - } - M.x86.debug &= ~DEBUG_TRACE_F; - M.x86.debug |= DEBUG_BREAK_F; - done = 1; - } - break; - case 'q': - M.x86.debug |= DEBUG_EXIT; - return; - case 'P': - noDecode = (noDecode)?0:1; - printk("Toggled decoding to %s\n",(noDecode)?"FALSE":"TRUE"); - break; - case 't': - case 0: - done = 1; - break; - } - } -} - -int X86EMU_trace_on(void) -{ - return M.x86.debug |= DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F; -} - -int X86EMU_trace_off(void) -{ - return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F); -} - -static int parse_line (char *s, int *ps, int *n) -{ - int cmd; - - *n = 0; - while(*s == ' ' || *s == '\t') s++; - ps[*n] = *s; - switch (*s) { - case '\n': - *n += 1; - return 0; - default: - cmd = *s; - *n += 1; - } - - while (1) { - while (*s != ' ' && *s != '\t' && *s != '\n') s++; - - if (*s == '\n') - return cmd; - - while(*s == ' ' || *s == '\t') s++; - - ps[*n]=atoi(s); - /*sscanf(s,"%x",&ps[*n]); */ - *n += 1; - } -} - -#endif /* DEBUG */ - -void x86emu_dump_stack(void) -{ - int i; - printk("Stack: "); - for (i = 0; i<16; i++) - { - u8 x = fetch_data_byte_abs(M.x86.R_SS, M.x86.R_SP + i); - printk("%02x ", (int)x); - } - printk("\n"); -} - -void x86emu_dump_regs (void) -{ - printk("\tAX=%04x ", M.x86.R_AX ); - printk("BX=%04x ", M.x86.R_BX ); - printk("CX=%04x ", M.x86.R_CX ); - printk("DX=%04x ", M.x86.R_DX ); - printk("SP=%04x ", M.x86.R_SP ); - printk("BP=%04x ", M.x86.R_BP ); - printk("SI=%04x ", M.x86.R_SI ); - printk("DI=%04x\n", M.x86.R_DI ); - printk("\tDS=%04x ", M.x86.R_DS ); - printk("ES=%04x ", M.x86.R_ES ); - printk("SS=%04x ", M.x86.R_SS ); - printk("CS=%04x ", M.x86.R_CS ); - printk("IP=%04x ", M.x86.R_IP ); - if (ACCESS_FLAG(F_OF)) printk("OV "); /* CHECKED... */ - else printk("NV "); - if (ACCESS_FLAG(F_DF)) printk("DN "); - else printk("UP "); - if (ACCESS_FLAG(F_IF)) printk("EI "); - else printk("DI "); - if (ACCESS_FLAG(F_SF)) printk("NG "); - else printk("PL "); - if (ACCESS_FLAG(F_ZF)) printk("ZR "); - else printk("NZ "); - if (ACCESS_FLAG(F_AF)) printk("AC "); - else printk("NA "); - if (ACCESS_FLAG(F_PF)) printk("PE "); - else printk("PO "); - if (ACCESS_FLAG(F_CF)) printk("CY "); - else printk("NC "); - printk("\n"); - /*x86emu_dump_stack(); */ -} - -void x86emu_dump_xregs (void) -{ - printk("\tEAX=%08x ", M.x86.R_EAX ); - printk("EBX=%08x ", M.x86.R_EBX ); - printk("ECX=%08x ", M.x86.R_ECX ); - printk("EDX=%08x \n", M.x86.R_EDX ); - printk("\tESP=%08x ", M.x86.R_ESP ); - printk("EBP=%08x ", M.x86.R_EBP ); - printk("ESI=%08x ", M.x86.R_ESI ); - printk("EDI=%08x\n", M.x86.R_EDI ); - printk("\tDS=%04x ", M.x86.R_DS ); - printk("ES=%04x ", M.x86.R_ES ); - printk("SS=%04x ", M.x86.R_SS ); - printk("CS=%04x ", M.x86.R_CS ); - printk("EIP=%08x\n\t", M.x86.R_EIP ); - if (ACCESS_FLAG(F_OF)) printk("OV "); /* CHECKED... */ - else printk("NV "); - if (ACCESS_FLAG(F_DF)) printk("DN "); - else printk("UP "); - if (ACCESS_FLAG(F_IF)) printk("EI "); - else printk("DI "); - if (ACCESS_FLAG(F_SF)) printk("NG "); - else printk("PL "); - if (ACCESS_FLAG(F_ZF)) printk("ZR "); - else printk("NZ "); - if (ACCESS_FLAG(F_AF)) printk("AC "); - else printk("NA "); - if (ACCESS_FLAG(F_PF)) printk("PE "); - else printk("PO "); - if (ACCESS_FLAG(F_CF)) printk("CY "); - else printk("NC "); - printk("\n"); -} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/decode.c b/board/MAI/bios_emulator/scitech/src/x86emu/decode.c deleted file mode 100644 index 832b1f5..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/decode.c +++ /dev/null @@ -1,970 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: This file includes subroutines which are related to -* instruction decoding and accessess of immediate data via IP. etc. -* -****************************************************************************/ - -#include "x86emu/x86emui.h" - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -REMARKS: -Handles any pending asychronous interrupts. -****************************************************************************/ -static void x86emu_intr_handle(void) -{ - u8 intno; - - if (M.x86.intr & INTR_SYNCH) { - intno = M.x86.intno; - if (_X86EMU_intrTab[intno]) { - (*_X86EMU_intrTab[intno])(intno); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(intno * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(intno * 4); - M.x86.intr = 0; - } - } -} - -/**************************************************************************** -PARAMETERS: -intrnum - Interrupt number to raise - -REMARKS: -Raise the specified interrupt to be handled before the execution of the -next instruction. -****************************************************************************/ -void x86emu_intr_raise( - u8 intrnum) -{ - M.x86.intno = intrnum; - M.x86.intr |= INTR_SYNCH; -} - -/**************************************************************************** -REMARKS: -Main execution loop for the emulator. We return from here when the system -halts, which is normally caused by a stack fault when we return from the -original real mode call. -****************************************************************************/ -void X86EMU_exec(void) -{ - u8 op1; - - M.x86.intr = 0; - DB(x86emu_end_instr();) - - for (;;) { - DB(if (CHECK_IP_FETCH()) x86emu_check_ip_access();) - /* If debugging, save the IP and CS values. */ - SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); - INC_DECODED_INST_LEN(1); - if (M.x86.intr) { - if (M.x86.intr & INTR_HALTED) { - DB( printk("halted\n"); X86EMU_trace_regs();) - return; - } - if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || - !ACCESS_FLAG(F_IF)) { - x86emu_intr_handle(); - } - } - op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); - (*x86emu_optab[op1])(op1); - if (M.x86.debug & DEBUG_EXIT) { - M.x86.debug &= ~DEBUG_EXIT; - return; - } - } -} - -/**************************************************************************** -REMARKS: -Halts the system by setting the halted system flag. -****************************************************************************/ -void X86EMU_halt_sys(void) -{ - M.x86.intr |= INTR_HALTED; -} - -/**************************************************************************** -PARAMETERS: -mod - Mod value from decoded byte -regh - Reg h value from decoded byte -regl - Reg l value from decoded byte - -REMARKS: -Raise the specified interrupt to be handled before the execution of the -next instruction. - -NOTE: Do not inline this function, as (*sys_rdb) is already inline! -****************************************************************************/ -void fetch_decode_modrm( - int *mod, - int *regh, - int *regl) -{ - int fetched; - -DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) - fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); - INC_DECODED_INST_LEN(1); - *mod = (fetched >> 6) & 0x03; - *regh = (fetched >> 3) & 0x07; - *regl = (fetched >> 0) & 0x07; -} - -/**************************************************************************** -RETURNS: -Immediate byte value read from instruction queue - -REMARKS: -This function returns the immediate byte from the instruction queue, and -moves the instruction pointer to the next value. - -NOTE: Do not inline this function, as (*sys_rdb) is already inline! -****************************************************************************/ -u8 fetch_byte_imm(void) -{ - u8 fetched; - -DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) - fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); - INC_DECODED_INST_LEN(1); - return fetched; -} - -/**************************************************************************** -RETURNS: -Immediate word value read from instruction queue - -REMARKS: -This function returns the immediate byte from the instruction queue, and -moves the instruction pointer to the next value. - -NOTE: Do not inline this function, as (*sys_rdw) is already inline! -****************************************************************************/ -u16 fetch_word_imm(void) -{ - u16 fetched; - -DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) - fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); - M.x86.R_IP += 2; - INC_DECODED_INST_LEN(2); - return fetched; -} - -/**************************************************************************** -RETURNS: -Immediate lone value read from instruction queue - -REMARKS: -This function returns the immediate byte from the instruction queue, and -moves the instruction pointer to the next value. - -NOTE: Do not inline this function, as (*sys_rdw) is already inline! -****************************************************************************/ -u32 fetch_long_imm(void) -{ - u32 fetched; - -DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) - fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); - M.x86.R_IP += 4; - INC_DECODED_INST_LEN(4); - return fetched; -} - -/**************************************************************************** -RETURNS: -Value of the default data segment - -REMARKS: -Inline function that returns the default data segment for the current -instruction. - -On the x86 processor, the default segment is not always DS if there is -no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to -addresses relative to SS (ie: on the stack). So, at the minimum, all -decodings of addressing modes would have to set/clear a bit describing -whether the access is relative to DS or SS. That is the function of the -cpu-state-varible M.x86.mode. There are several potential states: - - repe prefix seen (handled elsewhere) - repne prefix seen (ditto) - - cs segment override - ds segment override - es segment override - fs segment override - gs segment override - ss segment override - - ds/ss select (in absense of override) - -Each of the above 7 items are handled with a bit in the mode field. -****************************************************************************/ -_INLINE u32 get_data_segment(void) -{ -#define GET_SEGMENT(segment) - switch (M.x86.mode & SYSMODE_SEGMASK) { - case 0: /* default case: use ds register */ - case SYSMODE_SEGOVR_DS: - case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: - return M.x86.R_DS; - case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ - return M.x86.R_SS; - case SYSMODE_SEGOVR_CS: - case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: - return M.x86.R_CS; - case SYSMODE_SEGOVR_ES: - case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: - return M.x86.R_ES; - case SYSMODE_SEGOVR_FS: - case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: - return M.x86.R_FS; - case SYSMODE_SEGOVR_GS: - case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: - return M.x86.R_GS; - case SYSMODE_SEGOVR_SS: - case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: - return M.x86.R_SS; - default: -#ifdef DEBUG - printk("error: should not happen: multiple overrides.\n"); -#endif - HALT_SYS(); - return 0; - } -} - -/**************************************************************************** -PARAMETERS: -offset - Offset to load data from - -RETURNS: -Byte value read from the absolute memory location. - -NOTE: Do not inline this function as (*sys_rdX) is already inline! -****************************************************************************/ -u8 fetch_data_byte( - uint offset) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); -#endif - return (*sys_rdb)((get_data_segment() << 4) + offset); -} - -/**************************************************************************** -PARAMETERS: -offset - Offset to load data from - -RETURNS: -Word value read from the absolute memory location. - -NOTE: Do not inline this function as (*sys_rdX) is already inline! -****************************************************************************/ -u16 fetch_data_word( - uint offset) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); -#endif - return (*sys_rdw)((get_data_segment() << 4) + offset); -} - -/**************************************************************************** -PARAMETERS: -offset - Offset to load data from - -RETURNS: -Long value read from the absolute memory location. - -NOTE: Do not inline this function as (*sys_rdX) is already inline! -****************************************************************************/ -u32 fetch_data_long( - uint offset) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); -#endif - return (*sys_rdl)((get_data_segment() << 4) + offset); -} - -/**************************************************************************** -PARAMETERS: -segment - Segment to load data from -offset - Offset to load data from - -RETURNS: -Byte value read from the absolute memory location. - -NOTE: Do not inline this function as (*sys_rdX) is already inline! -****************************************************************************/ -u8 fetch_data_byte_abs( - uint segment, - uint offset) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); -#endif - return (*sys_rdb)(((u32)segment << 4) + offset); -} - -/**************************************************************************** -PARAMETERS: -segment - Segment to load data from -offset - Offset to load data from - -RETURNS: -Word value read from the absolute memory location. - -NOTE: Do not inline this function as (*sys_rdX) is already inline! -****************************************************************************/ -u16 fetch_data_word_abs( - uint segment, - uint offset) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); -#endif - return (*sys_rdw)(((u32)segment << 4) + offset); -} - -/**************************************************************************** -PARAMETERS: -segment - Segment to load data from -offset - Offset to load data from - -RETURNS: -Long value read from the absolute memory location. - -NOTE: Do not inline this function as (*sys_rdX) is already inline! -****************************************************************************/ -u32 fetch_data_long_abs( - uint segment, - uint offset) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); -#endif - return (*sys_rdl)(((u32)segment << 4) + offset); -} - -/**************************************************************************** -PARAMETERS: -offset - Offset to store data at -val - Value to store - -REMARKS: -Writes a word value to an segmented memory location. The segment used is -the current 'default' segment, which may have been overridden. - -NOTE: Do not inline this function as (*sys_wrX) is already inline! -****************************************************************************/ -void store_data_byte( - uint offset, - u8 val) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); -#endif - (*sys_wrb)((get_data_segment() << 4) + offset, val); -} - -/**************************************************************************** -PARAMETERS: -offset - Offset to store data at -val - Value to store - -REMARKS: -Writes a word value to an segmented memory location. The segment used is -the current 'default' segment, which may have been overridden. - -NOTE: Do not inline this function as (*sys_wrX) is already inline! -****************************************************************************/ -void store_data_word( - uint offset, - u16 val) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); -#endif - (*sys_wrw)((get_data_segment() << 4) + offset, val); -} - -/**************************************************************************** -PARAMETERS: -offset - Offset to store data at -val - Value to store - -REMARKS: -Writes a long value to an segmented memory location. The segment used is -the current 'default' segment, which may have been overridden. - -NOTE: Do not inline this function as (*sys_wrX) is already inline! -****************************************************************************/ -void store_data_long( - uint offset, - u32 val) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); -#endif - (*sys_wrl)((get_data_segment() << 4) + offset, val); -} - -/**************************************************************************** -PARAMETERS: -segment - Segment to store data at -offset - Offset to store data at -val - Value to store - -REMARKS: -Writes a byte value to an absolute memory location. - -NOTE: Do not inline this function as (*sys_wrX) is already inline! -****************************************************************************/ -void store_data_byte_abs( - uint segment, - uint offset, - u8 val) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); -#endif - (*sys_wrb)(((u32)segment << 4) + offset, val); -} - -/**************************************************************************** -PARAMETERS: -segment - Segment to store data at -offset - Offset to store data at -val - Value to store - -REMARKS: -Writes a word value to an absolute memory location. - -NOTE: Do not inline this function as (*sys_wrX) is already inline! -****************************************************************************/ -void store_data_word_abs( - uint segment, - uint offset, - u16 val) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); -#endif - (*sys_wrw)(((u32)segment << 4) + offset, val); -} - -/**************************************************************************** -PARAMETERS: -segment - Segment to store data at -offset - Offset to store data at -val - Value to store - -REMARKS: -Writes a long value to an absolute memory location. - -NOTE: Do not inline this function as (*sys_wrX) is already inline! -****************************************************************************/ -void store_data_long_abs( - uint segment, - uint offset, - u32 val) -{ -#ifdef DEBUG - if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); -#endif - (*sys_wrl)(((u32)segment << 4) + offset, val); -} - -/**************************************************************************** -PARAMETERS: -reg - Register to decode - -RETURNS: -Pointer to the appropriate register - -REMARKS: -Return a pointer to the register given by the R/RM field of the -modrm byte, for byte operands. Also enables the decoding of instructions. -****************************************************************************/ -u8* decode_rm_byte_register( - int reg) -{ - switch (reg) { - case 0: - DECODE_PRINTF("AL"); - return &M.x86.R_AL; - case 1: - DECODE_PRINTF("CL"); - return &M.x86.R_CL; - case 2: - DECODE_PRINTF("DL"); - return &M.x86.R_DL; - case 3: - DECODE_PRINTF("BL"); - return &M.x86.R_BL; - case 4: - DECODE_PRINTF("AH"); - return &M.x86.R_AH; - case 5: - DECODE_PRINTF("CH"); - return &M.x86.R_CH; - case 6: - DECODE_PRINTF("DH"); - return &M.x86.R_DH; - case 7: - DECODE_PRINTF("BH"); - return &M.x86.R_BH; - } - HALT_SYS(); - return NULL; /* NOT REACHED OR REACHED ON ERROR */ -} - -/**************************************************************************** -PARAMETERS: -reg - Register to decode - -RETURNS: -Pointer to the appropriate register - -REMARKS: -Return a pointer to the register given by the R/RM field of the -modrm byte, for word operands. Also enables the decoding of instructions. -****************************************************************************/ -u16* decode_rm_word_register( - int reg) -{ - switch (reg) { - case 0: - DECODE_PRINTF("AX"); - return &M.x86.R_AX; - case 1: - DECODE_PRINTF("CX"); - return &M.x86.R_CX; - case 2: - DECODE_PRINTF("DX"); - return &M.x86.R_DX; - case 3: - DECODE_PRINTF("BX"); - return &M.x86.R_BX; - case 4: - DECODE_PRINTF("SP"); - return &M.x86.R_SP; - case 5: - DECODE_PRINTF("BP"); - return &M.x86.R_BP; - case 6: - DECODE_PRINTF("SI"); - return &M.x86.R_SI; - case 7: - DECODE_PRINTF("DI"); - return &M.x86.R_DI; - } - HALT_SYS(); - return NULL; /* NOTREACHED OR REACHED ON ERROR */ -} - -/**************************************************************************** -PARAMETERS: -reg - Register to decode - -RETURNS: -Pointer to the appropriate register - -REMARKS: -Return a pointer to the register given by the R/RM field of the -modrm byte, for dword operands. Also enables the decoding of instructions. -****************************************************************************/ -u32* decode_rm_long_register( - int reg) -{ - switch (reg) { - case 0: - DECODE_PRINTF("EAX"); - return &M.x86.R_EAX; - case 1: - DECODE_PRINTF("ECX"); - return &M.x86.R_ECX; - case 2: - DECODE_PRINTF("EDX"); - return &M.x86.R_EDX; - case 3: - DECODE_PRINTF("EBX"); - return &M.x86.R_EBX; - case 4: - DECODE_PRINTF("ESP"); - return &M.x86.R_ESP; - case 5: - DECODE_PRINTF("EBP"); - return &M.x86.R_EBP; - case 6: - DECODE_PRINTF("ESI"); - return &M.x86.R_ESI; - case 7: - DECODE_PRINTF("EDI"); - return &M.x86.R_EDI; - } - HALT_SYS(); - return NULL; /* NOTREACHED OR REACHED ON ERROR */ -} - -/**************************************************************************** -PARAMETERS: -reg - Register to decode - -RETURNS: -Pointer to the appropriate register - -REMARKS: -Return a pointer to the register given by the R/RM field of the -modrm byte, for word operands, modified from above for the weirdo -special case of segreg operands. Also enables the decoding of instructions. -****************************************************************************/ -u16* decode_rm_seg_register( - int reg) -{ - switch (reg) { - case 0: - DECODE_PRINTF("ES"); - return &M.x86.R_ES; - case 1: - DECODE_PRINTF("CS"); - return &M.x86.R_CS; - case 2: - DECODE_PRINTF("SS"); - return &M.x86.R_SS; - case 3: - DECODE_PRINTF("DS"); - return &M.x86.R_DS; - case 4: - case 5: - case 6: - case 7: - DECODE_PRINTF("ILLEGAL SEGREG"); - break; - } - HALT_SYS(); - return NULL; /* NOT REACHED OR REACHED ON ERROR */ -} - -/**************************************************************************** -PARAMETERS: -rm - RM value to decode - -RETURNS: -Offset in memory for the address decoding - -REMARKS: -Return the offset given by mod=00 addressing. Also enables the -decoding of instructions. - -NOTE: The code which specifies the corresponding segment (ds vs ss) - below in the case of [BP+..]. The assumption here is that at the - point that this subroutine is called, the bit corresponding to - SYSMODE_SEG_DS_SS will be zero. After every instruction - except the segment override instructions, this bit (as well - as any bits indicating segment overrides) will be clear. So - if a SS access is needed, set this bit. Otherwise, DS access - occurs (unless any of the segment override bits are set). -****************************************************************************/ -unsigned decode_rm00_address( - int rm) -{ - unsigned offset; - - if (M.x86.mode & SYSMODE_PREFIX_ADDR) - { - switch (rm) { - case 0: - DECODE_PRINTF("[EAX]"); - return M.x86.R_EAX; - case 1: - DECODE_PRINTF("[ECX]"); - return M.x86.R_ECX; - case 2: - DECODE_PRINTF("[EDX]"); -/* M.x86.mode |= SYSMODE_SEG_DS_SS; */ - return M.x86.R_EDX; - case 3: - DECODE_PRINTF("[EBX]"); -/* M.x86.mode |= SYSMODE_SEG_DS_SS; */ - return M.x86.R_EBX; - case 4: - printk("Unsupported SIB encoding\n"); - HALT_SYS(); - return 0; - case 5: - offset = fetch_long_imm(); - DECODE_PRINTF2("[%08x]", offset); - return offset; - case 6: - DECODE_PRINTF("[ESI]"); - return M.x86.R_ESI; - case 7: - DECODE_PRINTF("[EDI]"); - return M.x86.R_EDI; - } - } - else - { - switch (rm) { - case 0: - DECODE_PRINTF("[BX+SI]"); - return M.x86.R_BX + M.x86.R_SI; - case 1: - DECODE_PRINTF("[BX+DI]"); - return M.x86.R_BX + M.x86.R_DI; - case 2: - DECODE_PRINTF("[BP+SI]"); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + M.x86.R_SI; - case 3: - DECODE_PRINTF("[BP+DI]"); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + M.x86.R_DI; - case 4: - DECODE_PRINTF("[SI]"); - return M.x86.R_SI; - case 5: - DECODE_PRINTF("[DI]"); - return M.x86.R_DI; - case 6: - offset = fetch_word_imm(); - DECODE_PRINTF2("[%04x]", offset); - return offset; - case 7: - DECODE_PRINTF("[BX]"); - return M.x86.R_BX; - } - } - HALT_SYS(); - return 0; -} - -/**************************************************************************** -PARAMETERS: -rm - RM value to decode - -RETURNS: -Offset in memory for the address decoding - -REMARKS: -Return the offset given by mod=01 addressing. Also enables the -decoding of instructions. -****************************************************************************/ -unsigned decode_rm01_address( - int rm) -{ - int displacement = (s8)fetch_byte_imm(); - if (M.x86.mode & SYSMODE_PREFIX_ADDR) - { - switch (rm) - { - case 0: - DECODE_PRINTF2("%d[EAX}", displacement); - return M.x86.R_EAX + displacement; - case 1: - DECODE_PRINTF2("%d[ECX]", displacement); - return M.x86.R_ECX + displacement; - case 2: - DECODE_PRINTF2("%d[EDX]", displacement); - return M.x86.R_EDX + displacement; - case 3: - DECODE_PRINTF2("%d[EBX]", displacement); - return M.x86.R_EBX + displacement; - case 4: - printk("Unsupported SIB addressing mode\n"); - HALT_SYS(); - return 0; - case 5: - DECODE_PRINTF2("%d[EBP]", displacement); - return M.x86.R_EBP + displacement; - case 6: - DECODE_PRINTF2("%d[ESI]", displacement); - return M.x86.R_ESI + displacement; - case 7: - DECODE_PRINTF2("%d[EDI]", displacement); - return M.x86.R_EDI + displacement; - } - } - else - { - switch (rm) { - case 0: - DECODE_PRINTF2("%d[BX+SI]", displacement); - return M.x86.R_BX + M.x86.R_SI + displacement; - case 1: - DECODE_PRINTF2("%d[BX+DI]", displacement); - return M.x86.R_BX + M.x86.R_DI + displacement; - case 2: - DECODE_PRINTF2("%d[BP+SI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + M.x86.R_SI + displacement; - case 3: - DECODE_PRINTF2("%d[BP+DI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + M.x86.R_DI + displacement; - case 4: - DECODE_PRINTF2("%d[SI]", displacement); - return M.x86.R_SI + displacement; - case 5: - DECODE_PRINTF2("%d[DI]", displacement); - return M.x86.R_DI + displacement; - case 6: - DECODE_PRINTF2("%d[BP]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return M.x86.R_BP + displacement; - case 7: - DECODE_PRINTF2("%d[BX]", displacement); - return M.x86.R_BX + displacement; - } - HALT_SYS(); - } - return 0; /* SHOULD NOT HAPPEN */ -} - -/**************************************************************************** -PARAMETERS: -rm - RM value to decode - -RETURNS: -Offset in memory for the address decoding - -REMARKS: -Return the offset given by mod=10 addressing. Also enables the -decoding of instructions. -****************************************************************************/ -unsigned decode_rm10_address( - int rm) -{ - if (M.x86.mode & SYSMODE_PREFIX_ADDR) - { - int displacement = (s32)fetch_long_imm(); - switch (rm) - { - case 0: - DECODE_PRINTF2("%d[EAX}", displacement); - return M.x86.R_EAX + displacement; - case 1: - DECODE_PRINTF2("%d[ECX]", displacement); - return M.x86.R_ECX + displacement; - case 2: - DECODE_PRINTF2("%d[EDX]", displacement); - return M.x86.R_EDX + displacement; - case 3: - DECODE_PRINTF2("%d[EBX]", displacement); - return M.x86.R_EBX + displacement; - case 4: - printk("Unsupported SIB addressing mode\n"); - HALT_SYS(); - return 0; - case 5: - DECODE_PRINTF2("%d[EBP]", displacement); - return M.x86.R_EBP + displacement; - case 6: - DECODE_PRINTF2("%d[ESI]", displacement); - return M.x86.R_ESI + displacement; - case 7: - DECODE_PRINTF2("%d[EDI]", displacement); - return M.x86.R_EDI + displacement; - } - } - else - { - int displacement = (s16)fetch_word_imm(); - switch (rm) { - case 0: - DECODE_PRINTF2("%d[BX+SI]", displacement); - return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; - case 1: - DECODE_PRINTF2("%d[BX+DI]", displacement); - return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; - case 2: - DECODE_PRINTF2("%d[BP+SI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; - case 3: - DECODE_PRINTF2("%d[BP+DI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; - case 4: - DECODE_PRINTF2("%d[SI]", displacement); - return (M.x86.R_SI + displacement) & 0xffff; - case 5: - DECODE_PRINTF2("%d[DI]", displacement); - return (M.x86.R_DI + displacement) & 0xffff; - case 6: - DECODE_PRINTF2("%d[BP]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + displacement) & 0xffff; - case 7: - DECODE_PRINTF2("%d[BX]", displacement); - return (M.x86.R_BX + displacement) & 0xffff; - } - } - HALT_SYS(); - return 0; - /*NOTREACHED */ -} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c b/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c deleted file mode 100644 index 7f7c345..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c +++ /dev/null @@ -1,945 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: This file contains the code to implement the decoding and -* emulation of the FPU instructions. -* -****************************************************************************/ - -#include "x86emu/x86emui.h" - -/*----------------------------- Implementation ----------------------------*/ - -/* opcode=0xd8 */ -void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("ESC D8\n"); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR_NO_TRACE(); -} - -#ifdef DEBUG - -static char *x86emu_fpu_op_d9_tab[] = { - "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", - "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", - - "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", - "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", - - "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", - "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", -}; - -static char *x86emu_fpu_op_d9_tab1[] = { - "FLD\t", "FLD\t", "FLD\t", "FLD\t", - "FLD\t", "FLD\t", "FLD\t", "FLD\t", - - "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", - "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", - - "FNOP", "ESC_D9", "ESC_D9", "ESC_D9", - "ESC_D9", "ESC_D9", "ESC_D9", "ESC_D9", - - "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", - "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", - - "FCHS", "FABS", "ESC_D9", "ESC_D9", - "FTST", "FXAM", "ESC_D9", "ESC_D9", - - "FLD1", "FLDL2T", "FLDL2E", "FLDPI", - "FLDLG2", "FLDLN2", "FLDZ", "ESC_D9", - - "F2XM1", "FYL2X", "FPTAN", "FPATAN", - "FXTRACT", "ESC_D9", "FDECSTP", "FINCSTP", - - "FPREM", "FYL2XP1", "FSQRT", "ESC_D9", - "FRNDINT", "FSCALE", "ESC_D9", "ESC_D9", -}; - -#endif /* DEBUG */ - -/* opcode=0xd9 */ -void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - u8 stkelem; - - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (mod != 3) { - DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); - } else { - DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]); - } -#endif - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - if (rh < 4) { - DECODE_PRINTF2("ST(%d)\n", stkelem); - } else { - DECODE_PRINTF("\n"); - } - break; - } -#ifdef X86EMU_FPU_PRESENT - /* execute */ - switch (mod) { - case 3: - switch (rh) { - case 0: - x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem); - break; - case 1: - x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem); - break; - case 2: - switch (rl) { - case 0: - x86emu_fpu_R_nop(); - break; - default: - x86emu_fpu_illegal(); - break; - } - case 3: - x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem); - break; - case 4: - switch (rl) { - case 0: - x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP); - break; - default: - /* 2,3,6,7 */ - x86emu_fpu_illegal(); - break; - } - break; - - case 5: - switch (rl) { - case 0: - x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP); - break; - case 6: - x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP); - break; - default: - /* 7 */ - x86emu_fpu_illegal(); - break; - } - break; - - case 6: - switch (rl) { - case 0: - x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_illegal(); - break; - case 6: - x86emu_fpu_R_decstp(); - break; - case 7: - x86emu_fpu_R_incstp(); - break; - } - break; - - case 7: - switch (rl) { - case 0: - x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_illegal(); - break; - case 4: - x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP); - break; - case 6: - case 7: - default: - x86emu_fpu_illegal(); - break; - } - break; - - default: - switch (rh) { - case 0: - x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset); - break; - case 3: - x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset); - break; - case 4: - x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset); - break; - case 5: - x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset); - break; - case 6: - x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset); - break; - case 7: - x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset); - break; - } - } - } -#endif /* X86EMU_FPU_PRESENT */ - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR_NO_TRACE(); -} - -#ifdef DEBUG - -char *x86emu_fpu_op_da_tab[] = { - "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", - "FICOMP\tDWORD PTR ", - "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", - "FIDIVR\tDWORD PTR ", - - "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", - "FICOMP\tDWORD PTR ", - "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", - "FIDIVR\tDWORD PTR ", - - "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", - "FICOMP\tDWORD PTR ", - "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", - "FIDIVR\tDWORD PTR ", - - "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", - "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", -}; - -#endif /* DEBUG */ - -/* opcode=0xda */ -void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - u8 stkelem; - - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); - DECODE_PRINTINSTR32(x86emu_fpu_op_da_tab, mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; - } -#ifdef X86EMU_FPU_PRESENT - switch (mod) { - case 3: - x86emu_fpu_illegal(); - break; - default: - switch (rh) { - case 0: - x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset); - break; - case 1: - x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset); - break; - case 2: - x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset); - break; - case 3: - x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset); - break; - case 4: - x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset); - break; - case 5: - x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset); - break; - case 6: - x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset); - break; - case 7: - x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset); - break; - } - } -#endif - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR_NO_TRACE(); -} - -#ifdef DEBUG - -char *x86emu_fpu_op_db_tab[] = { - "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", - "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", - - "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", - "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", - - "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", - "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", -}; - -#endif /* DEBUG */ - -/* opcode=0xdb */ -void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (mod != 3) { - DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); - } else if (rh == 4) { /* === 11 10 0 nnn */ - switch (rl) { - case 0: - DECODE_PRINTF("FENI\n"); - break; - case 1: - DECODE_PRINTF("FDISI\n"); - break; - case 2: - DECODE_PRINTF("FCLEX\n"); - break; - case 3: - DECODE_PRINTF("FINIT\n"); - break; - } - } else { - DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); - } -#endif /* DEBUG */ - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - break; - case 1: - destoffset = decode_rm01_address(rl); - break; - case 2: - destoffset = decode_rm10_address(rl); - break; - case 3: /* register to register */ - break; - } -#ifdef X86EMU_FPU_PRESENT - /* execute */ - switch (mod) { - case 3: - switch (rh) { - case 4: - switch (rl) { - case 0: - x86emu_fpu_R_feni(); - break; - case 1: - x86emu_fpu_R_fdisi(); - break; - case 2: - x86emu_fpu_R_fclex(); - break; - case 3: - x86emu_fpu_R_finit(); - break; - default: - x86emu_fpu_illegal(); - break; - } - break; - default: - x86emu_fpu_illegal(); - break; - } - break; - default: - switch (rh) { - case 0: - x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset); - break; - case 3: - x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset); - break; - case 4: - x86emu_fpu_illegal(); - break; - case 5: - x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset); - break; - case 6: - x86emu_fpu_illegal(); - break; - case 7: - x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset); - break; - } - } -#endif - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR_NO_TRACE(); -} - -#ifdef DEBUG -char *x86emu_fpu_op_dc_tab[] = { - "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", - "FCOMP\tQWORD PTR ", - "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", - "FDIVR\tQWORD PTR ", - - "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", - "FCOMP\tQWORD PTR ", - "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", - "FDIVR\tQWORD PTR ", - - "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", - "FCOMP\tQWORD PTR ", - "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", - "FDIVR\tQWORD PTR ", - - "FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t", - "FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t", -}; -#endif /* DEBUG */ - -/* opcode=0xdc */ -void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - u8 stkelem; - - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); - DECODE_PRINTINSTR32(x86emu_fpu_op_dc_tab, mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; - } -#ifdef X86EMU_FPU_PRESENT - /* execute */ - switch (mod) { - case 3: - switch (rh) { - case 0: - x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP); - break; - case 6: - x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP); - break; - case 7: - x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP); - break; - } - break; - default: - switch (rh) { - case 0: - x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset); - break; - case 1: - x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset); - break; - case 2: - x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset); - break; - case 3: - x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset); - break; - case 4: - x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset); - break; - case 5: - x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset); - break; - case 6: - x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset); - break; - case 7: - x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset); - break; - } - } -#endif - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR_NO_TRACE(); -} - -#ifdef DEBUG - -static char *x86emu_fpu_op_dd_tab[] = { - "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", - "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", - - "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", - "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", - - "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", - "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", - - "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", - "ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,", -}; - -#endif /* DEBUG */ - -/* opcode=0xdd */ -void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - u8 stkelem; - - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); - DECODE_PRINTINSTR32(x86emu_fpu_op_dd_tab, mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; - } -#ifdef X86EMU_FPU_PRESENT - switch (mod) { - case 3: - switch (rh) { - case 0: - x86emu_fpu_R_ffree(stkelem); - break; - case 1: - x86emu_fpu_R_fxch(stkelem); - break; - case 2: - x86emu_fpu_R_fst(stkelem); /* register version */ - break; - case 3: - x86emu_fpu_R_fstp(stkelem); /* register version */ - break; - default: - x86emu_fpu_illegal(); - break; - } - break; - default: - switch (rh) { - case 0: - x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset); - break; - case 3: - x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset); - break; - case 4: - x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset); - break; - case 5: - x86emu_fpu_illegal(); - break; - case 6: - x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset); - break; - case 7: - x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset); - break; - } - } -#endif - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR_NO_TRACE(); -} - -#ifdef DEBUG - -static char *x86emu_fpu_op_de_tab[] = -{ - "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", - "FICOMP\tWORD PTR ", - "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", - "FIDIVR\tWORD PTR ", - - "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", - "FICOMP\tWORD PTR ", - "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", - "FIDIVR\tWORD PTR ", - - "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", - "FICOMP\tWORD PTR ", - "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", - "FIDIVR\tWORD PTR ", - - "FADDP\t", "FMULP\t", "FCOMP\t", "FCOMPP\t", - "FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t", -}; - -#endif /* DEBUG */ - -/* opcode=0xde */ -void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - u8 stkelem; - - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); - DECODE_PRINTINSTR32(x86emu_fpu_op_de_tab, mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; - } -#ifdef X86EMU_FPU_PRESENT - switch (mod) { - case 3: - switch (rh) { - case 0: - x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); - break; - case 3: - if (stkelem == 1) - x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP); - else - x86emu_fpu_illegal(); - break; - case 4: - x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP); - break; - case 6: - x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP); - break; - case 7: - x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP); - break; - } - break; - default: - switch (rh) { - case 0: - x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset); - break; - case 1: - x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset); - break; - case 2: - x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset); - break; - case 3: - x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset); - break; - case 4: - x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset); - break; - case 5: - x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset); - break; - case 6: - x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset); - break; - case 7: - x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset); - break; - } - } -#endif - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR_NO_TRACE(); -} - -#ifdef DEBUG - -static char *x86emu_fpu_op_df_tab[] = { - /* mod == 00 */ - "FILD\tWORD PTR ", "ESC_DF\t39\n", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", - "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", - "FISTP\tQWORD PTR ", - - /* mod == 01 */ - "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", - "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", - "FISTP\tQWORD PTR ", - - /* mod == 10 */ - "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", - "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", - "FISTP\tQWORD PTR ", - - /* mod == 11 */ - "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", - "ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F," -}; - -#endif /* DEBUG */ - -/* opcode=0xdf */ -void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - u8 stkelem; - - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); - DECODE_PRINTINSTR32(x86emu_fpu_op_df_tab, mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d)\n", stkelem); - break; - } -#ifdef X86EMU_FPU_PRESENT - switch (mod) { - case 3: - switch (rh) { - case 0: - x86emu_fpu_R_ffree(stkelem); - break; - case 1: - x86emu_fpu_R_fxch(stkelem); - break; - case 2: - x86emu_fpu_R_fst(stkelem); /* register version */ - break; - case 3: - x86emu_fpu_R_fstp(stkelem); /* register version */ - break; - default: - x86emu_fpu_illegal(); - break; - } - break; - default: - switch (rh) { - case 0: - x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset); - break; - case 3: - x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset); - break; - case 4: - x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset); - break; - case 5: - x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset); - break; - case 6: - x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset); - break; - case 7: - x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset); - break; - } - } -#endif - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR_NO_TRACE(); -} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile b/board/MAI/bios_emulator/scitech/src/x86emu/makefile deleted file mode 100644 index 8ce2e9e..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/makefile +++ /dev/null @@ -1,63 +0,0 @@ -############################################################################# -# -# Realmode X86 Emulator Library -# -# Copyright (C) 1996-1999 SciTech Software, Inc. -# -# ======================================================================== -# -# Permission to use, copy, modify, distribute, and sell this software and -# its documentation for any purpose is hereby granted without fee, -# provided that the above copyright notice appear in all copies and that -# both that copyright notice and this permission notice appear in -# supporting documentation, and that the name of the authors not be used -# in advertising or publicity pertaining to distribution of the software -# without specific, written prior permission. The authors makes no -# representations about the suitability of this software for any purpose. -# It is provided "as is" without express or implied warranty. -# -# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -# PERFORMANCE OF THIS SOFTWARE. -# -# ======================================================================== -# -# Descripton: Generic makefile for the x86emu library. Requires -# the SciTech Software makefile definitions package to be -# installed, which uses the DMAKE make program. -# -############################################################################# - -.IMPORT .IGNORE: DEBUG - -#---------------------------------------------------------------------------- -# Define the lists of object files -#---------------------------------------------------------------------------- - -OBJECTS = sys$O decode$O ops$O ops2$O prim_ops$O fpu$O debug$O -CFLAGS += -DSCITECH -.IF $(DEBUG) -CFLAGS += -DDEBUG -.ENDIF -LIBCLEAN = *.dll *.lib *.a -LIBFILE = $(LP)x86emu$L - -#---------------------------------------------------------------------------- -# Sample test programs -#---------------------------------------------------------------------------- - -all: $(LIBFILE) - -validate$E: validate$O $(LIBFILE) - -#---------------------------------------------------------------------------- -# Define the list of object files to create dependency information for -#---------------------------------------------------------------------------- - -DEPEND_OBJ = validate$O $(OBJECTS) - -.INCLUDE: "$(SCITECH)/makedefs/common.mk" diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross deleted file mode 100644 index 0bce9a9..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross +++ /dev/null @@ -1,82 +0,0 @@ -############################################################################# -# -# Realmode X86 Emulator Library -# -# Copyright (C) 1996-1999 SciTech Software, Inc. -# -# ======================================================================== -# -# Permission to use, copy, modify, distribute, and sell this software and -# its documentation for any purpose is hereby granted without fee, -# provided that the above copyright notice appear in all copies and that -# both that copyright notice and this permission notice appear in -# supporting documentation, and that the name of the authors not be used -# in advertising or publicity pertaining to distribution of the software -# without specific, written prior permission. The authors makes no -# representations about the suitability of this software for any purpose. -# It is provided "as is" without express or implied warranty. -# -# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -# PERFORMANCE OF THIS SOFTWARE. -# -# ======================================================================== -# -# Descripton: Linux specific makefile for the x86emu library. -# -############################################################################# - -CC = $(CROSS_COMPILE)gcc -AR = $(CROSS_COMPILE)ar - -TARGETLIB = libx86emu.a -TARGETDEBUGLIB =libx86emud.a - -OBJS=\ -decode.o \ -fpu.o \ -ops.o \ -ops2.o \ -prim_ops.o \ -sys.o - -DEBUGOBJS=debug.d \ - decode.d \ - fpu.d \ - ops.d \ - ops2.d \ - prim_ops.d \ - sys.d - -.SUFFIXES: .d - -all: $(TARGETLIB) $(TARGETDEBUGLIB) - -$(TARGETLIB): $(OBJS) - $(AR) rv $(TARGETLIB) $(OBJS) - -$(TARGETDEBUGLIB): $(DEBUGOBJS) - $(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS) - -INCS = -I. -Ix86emu -I../../include -CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char -fomit-frame-pointer -fPIC -ffixed-r14 -meabi -CDEBUGFLAGS = -DDEBUG - -.c.o: - $(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c - -.c.d: - $(CC) -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c - -.cpp.o: - $(CC) -c $(CFLAGS) $(INCS) $*.cpp - -clean: - rm -f *.a *.o *.d - -validate: validate.o libx86emu.a - $(CC) -o validate validate.o -lx86emu -L. diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux deleted file mode 100644 index f74b88d..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux +++ /dev/null @@ -1,81 +0,0 @@ -############################################################################# -# -# Realmode X86 Emulator Library -# -# Copyright (C) 1996-1999 SciTech Software, Inc. -# -# ======================================================================== -# -# Permission to use, copy, modify, distribute, and sell this software and -# its documentation for any purpose is hereby granted without fee, -# provided that the above copyright notice appear in all copies and that -# both that copyright notice and this permission notice appear in -# supporting documentation, and that the name of the authors not be used -# in advertising or publicity pertaining to distribution of the software -# without specific, written prior permission. The authors makes no -# representations about the suitability of this software for any purpose. -# It is provided "as is" without express or implied warranty. -# -# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -# PERFORMANCE OF THIS SOFTWARE. -# -# ======================================================================== -# -# Descripton: Linux specific makefile for the x86emu library. -# -############################################################################# - -TARGETLIB = libx86emu.a -TARGETDEBUGLIB =libx86emud.a - -OBJS=\ -decode.o \ -fpu.o \ -ops.o \ -ops2.o \ -prim_ops.o \ -pregs.o \ -sys.o - -DEBUGOBJS=debug.d \ - decode.d \ - fpu.d \ - ops.d \ - ops2.d \ - prim_ops.d \ - pregs.d \ - sys.d - -.SUFFIXES: .d - -all: $(TARGETLIB) $(TARGETDEBUGLIB) - -$(TARGETLIB): $(OBJS) - ar rv $(TARGETLIB) $(OBJS) - -$(TARGETDEBUGLIB): $(DEBUGOBJS) - ar rv $(TARGETDEBUGLIB) $(DEBUGOBJS) - -INCS = -I. -Ix86emu -I../../include -CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -CDEBUGFLAGS = -DDEBUG - -.c.o: - gcc -g -O -Wall -c $(CFLAGS) $(INCS) $*.c - -.c.d: - gcc -g -O -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c - -.cpp.o: - gcc -c $(CFLAGS) $(INCS) $*.cpp - -clean: - rm -f *.a *.o *.d - -validate: validate.o libx86emu.a - gcc -o validate validate.o -lx86emu -L. diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot deleted file mode 100644 index af9ae1f..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot +++ /dev/null @@ -1,80 +0,0 @@ -############################################################################# -# -# Realmode X86 Emulator Library -# -# Copyright (C) 1996-1999 SciTech Software, Inc. -# -# ======================================================================== -# -# Permission to use, copy, modify, distribute, and sell this software and -# its documentation for any purpose is hereby granted without fee, -# provided that the above copyright notice appear in all copies and that -# both that copyright notice and this permission notice appear in -# supporting documentation, and that the name of the authors not be used -# in advertising or publicity pertaining to distribution of the software -# without specific, written prior permission. The authors makes no -# representations about the suitability of this software for any purpose. -# It is provided "as is" without express or implied warranty. -# -# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -# PERFORMANCE OF THIS SOFTWARE. -# -# ======================================================================== -# -# Descripton: Linux specific makefile for the x86emu library. -# -############################################################################# -CC = $(CROSS_COMPILE)gcc -AR = $(CROSS_COMPILE)ar -TARGETLIB = libx86emu.a -TARGETDEBUGLIB =libx86emud.a - -OBJS=\ -decode.o \ -fpu.o \ -ops.o \ -ops2.o \ -prim_ops.o \ -sys.o - -DEBUGOBJS=debug.d \ - decode.d \ - fpu.d \ - ops.d \ - ops2.d \ - prim_ops.d \ - sys.d - -.SUFFIXES: .d - -all: $(TARGETLIB) $(TARGETDEBUGLIB) - -$(TARGETLIB): $(OBJS) - $(AR) rv $(TARGETLIB) $(OBJS) - -$(TARGETDEBUGLIB): $(DEBUGOBJS) - $(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS) - -INCS = -I. -Ix86emu -I../../include -CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char -fomit-frame-pointer -fPIC -ffixed-r14 -meabi -CDEBUGFLAGS = -DDEBUG - -.c.o: - $(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c - -.c.d: - $(CC) -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c - -.cpp.o: - $(CC) -c $(CFLAGS) $(INCS) $*.cpp - -clean: - rm -f *.a *.o *.d - -validate: validate.o libx86emu.a - $(CC) -o validate validate.o -lx86emu -L. diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/ops.c b/board/MAI/bios_emulator/scitech/src/x86emu/ops.c deleted file mode 100644 index 2d4f93e..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/ops.c +++ /dev/null @@ -1,11701 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: This file includes subroutines to implement the decoding -* and emulation of all the x86 processor instructions. -* -* There are approximately 250 subroutines in here, which correspond -* to the 256 byte-"opcodes" found on the 8086. The table which -* dispatches this is found in the files optab.[ch]. -* -* Each opcode proc has a comment preceeding it which gives it's table -* address. Several opcodes are missing (undefined) in the table. -* -* Each proc includes information for decoding (DECODE_PRINTF and -* DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc -* functions (START_OF_INSTR, END_OF_INSTR). -* -* Many of the procedures are *VERY* similar in coding. This has -* allowed for a very large amount of code to be generated in a fairly -* short amount of time (i.e. cut, paste, and modify). The result is -* that much of the code below could have been folded into subroutines -* for a large reduction in size of this file. The downside would be -* that there would be a penalty in execution speed. The file could -* also have been *MUCH* larger by inlining certain functions which -* were called. This could have resulted even faster execution. The -* prime directive I used to decide whether to inline the code or to -* modularize it, was basically: 1) no unnecessary subroutine calls, -* 2) no routines more than about 200 lines in size, and 3) modularize -* any code that I might not get right the first time. The fetch_* -* subroutines fall into the latter category. The The decode_* fall -* into the second category. The coding of the "switch(mod){ .... }" -* in many of the subroutines below falls into the first category. -* Especially, the coding of {add,and,or,sub,...}_{byte,word} -* subroutines are an especially glaring case of the third guideline. -* Since so much of the code is cloned from other modules (compare -* opcode #00 to opcode #01), making the basic operations subroutine -* calls is especially important; otherwise mistakes in coding an -* "add" would represent a nightmare in maintenance. -* -****************************************************************************/ - -#include "x86emu/x86emui.h" - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -PARAMETERS: -op1 - Instruction op code - -REMARKS: -Handles illegal opcodes. -****************************************************************************/ -void x86emuOp_illegal_op( - u8 op1) -{ - START_OF_INSTR(); - DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); - TRACE_REGS(); - printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-1,op1); - HALT_SYS(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x00 -****************************************************************************/ -void x86emuOp_add_byte_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - u8 *destreg, *srcreg; - u8 destval; - - START_OF_INSTR(); - DECODE_PRINTF("ADD\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = add_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = add_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = add_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x01 -****************************************************************************/ -void x86emuOp_add_word_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("ADD\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = add_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = add_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = add_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = add_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = add_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = add_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x02 -****************************************************************************/ -void x86emuOp_add_byte_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint srcoffset; - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("ADD\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_byte(*destreg, srcval); - break; - case 1: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_byte(*destreg, srcval); - break; - case 2: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_byte(*destreg, srcval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x03 -****************************************************************************/ -void x86emuOp_add_word_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("ADD\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_word(*destreg, srcval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_word(*destreg, srcval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_word(*destreg, srcval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = add_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x04 -****************************************************************************/ -void x86emuOp_add_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("ADD\tAL,"); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - M.x86.R_AL = add_byte(M.x86.R_AL, srcval); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x05 -****************************************************************************/ -void x86emuOp_add_word_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("ADD\tEAX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("ADD\tAX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = add_long(M.x86.R_EAX, srcval); - } else { - M.x86.R_AX = add_word(M.x86.R_AX, (u16)srcval); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x06 -****************************************************************************/ -void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("PUSH\tES\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_ES); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x07 -****************************************************************************/ -void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("POP\tES\n"); - TRACE_AND_STEP(); - M.x86.R_ES = pop_word(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x08 -****************************************************************************/ -void x86emuOp_or_byte_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint destoffset; - u8 destval; - - START_OF_INSTR(); - DECODE_PRINTF("OR\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = or_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = or_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = or_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x09 -****************************************************************************/ -void x86emuOp_or_word_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("OR\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = or_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = or_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = or_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = or_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = or_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = or_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0a -****************************************************************************/ -void x86emuOp_or_byte_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint srcoffset; - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("OR\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_byte(*destreg, srcval); - break; - case 1: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_byte(*destreg, srcval); - break; - case 2: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_byte(*destreg, srcval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0b -****************************************************************************/ -void x86emuOp_or_word_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("OR\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_word(*destreg, srcval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_word(*destreg, srcval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_word(*destreg, srcval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = or_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0c -****************************************************************************/ -void x86emuOp_or_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("OR\tAL,"); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - M.x86.R_AL = or_byte(M.x86.R_AL, srcval); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0d -****************************************************************************/ -void x86emuOp_or_word_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("OR\tEAX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("OR\tAX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = or_long(M.x86.R_EAX, srcval); - } else { - M.x86.R_AX = or_word(M.x86.R_AX, (u16)srcval); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0e -****************************************************************************/ -void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("PUSH\tCS\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f. Escape for two-byte opcode (286 or better) -****************************************************************************/ -void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1)) -{ - u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); - INC_DECODED_INST_LEN(1); - (*x86emu_optab2[op2])(op2); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x10 -****************************************************************************/ -void x86emuOp_adc_byte_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint destoffset; - u8 destval; - - START_OF_INSTR(); - DECODE_PRINTF("ADC\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = adc_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = adc_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = adc_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x11 -****************************************************************************/ -void x86emuOp_adc_word_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("ADC\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = adc_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = adc_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = adc_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = adc_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = adc_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = adc_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x12 -****************************************************************************/ -void x86emuOp_adc_byte_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint srcoffset; - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("ADC\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_byte(*destreg, srcval); - break; - case 1: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_byte(*destreg, srcval); - break; - case 2: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_byte(*destreg, srcval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x13 -****************************************************************************/ -void x86emuOp_adc_word_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("ADC\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_word(*destreg, srcval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_word(*destreg, srcval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_word(*destreg, srcval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = adc_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x14 -****************************************************************************/ -void x86emuOp_adc_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("ADC\tAL,"); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - M.x86.R_AL = adc_byte(M.x86.R_AL, srcval); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x15 -****************************************************************************/ -void x86emuOp_adc_word_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("ADC\tEAX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("ADC\tAX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = adc_long(M.x86.R_EAX, srcval); - } else { - M.x86.R_AX = adc_word(M.x86.R_AX, (u16)srcval); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x16 -****************************************************************************/ -void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("PUSH\tSS\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_SS); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x17 -****************************************************************************/ -void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("POP\tSS\n"); - TRACE_AND_STEP(); - M.x86.R_SS = pop_word(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x18 -****************************************************************************/ -void x86emuOp_sbb_byte_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint destoffset; - u8 destval; - - START_OF_INSTR(); - DECODE_PRINTF("SBB\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sbb_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sbb_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sbb_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x19 -****************************************************************************/ -void x86emuOp_sbb_word_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("SBB\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sbb_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sbb_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sbb_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sbb_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sbb_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sbb_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x1a -****************************************************************************/ -void x86emuOp_sbb_byte_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint srcoffset; - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("SBB\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_byte(*destreg, srcval); - break; - case 1: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_byte(*destreg, srcval); - break; - case 2: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_byte(*destreg, srcval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x1b -****************************************************************************/ -void x86emuOp_sbb_word_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("SBB\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_word(*destreg, srcval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_word(*destreg, srcval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_word(*destreg, srcval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sbb_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x1c -****************************************************************************/ -void x86emuOp_sbb_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("SBB\tAL,"); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - M.x86.R_AL = sbb_byte(M.x86.R_AL, srcval); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x1d -****************************************************************************/ -void x86emuOp_sbb_word_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("SBB\tEAX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("SBB\tAX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = sbb_long(M.x86.R_EAX, srcval); - } else { - M.x86.R_AX = sbb_word(M.x86.R_AX, (u16)srcval); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x1e -****************************************************************************/ -void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("PUSH\tDS\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_DS); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x1f -****************************************************************************/ -void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("POP\tDS\n"); - TRACE_AND_STEP(); - M.x86.R_DS = pop_word(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x20 -****************************************************************************/ -void x86emuOp_and_byte_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint destoffset; - u8 destval; - - START_OF_INSTR(); - DECODE_PRINTF("AND\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = and_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = and_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = and_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x21 -****************************************************************************/ -void x86emuOp_and_word_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("AND\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = and_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = and_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = and_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = and_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = and_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = and_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x22 -****************************************************************************/ -void x86emuOp_and_byte_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint srcoffset; - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("AND\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_byte(*destreg, srcval); - break; - case 1: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_byte(*destreg, srcval); - break; - case 2: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_byte(*destreg, srcval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x23 -****************************************************************************/ -void x86emuOp_and_word_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("AND\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_word(*destreg, srcval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_long(*destreg, srcval); - break; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_word(*destreg, srcval); - break; - } - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_word(*destreg, srcval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = and_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x24 -****************************************************************************/ -void x86emuOp_and_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("AND\tAL,"); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - M.x86.R_AL = and_byte(M.x86.R_AL, srcval); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x25 -****************************************************************************/ -void x86emuOp_and_word_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("AND\tEAX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("AND\tAX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = and_long(M.x86.R_EAX, srcval); - } else { - M.x86.R_AX = and_word(M.x86.R_AX, (u16)srcval); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x26 -****************************************************************************/ -void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("ES:\n"); - TRACE_AND_STEP(); - M.x86.mode |= SYSMODE_SEGOVR_ES; - /* - * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 - * opcode subroutines we do not want to do this. - */ - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x27 -****************************************************************************/ -void x86emuOp_daa(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("DAA\n"); - TRACE_AND_STEP(); - M.x86.R_AL = daa_byte(M.x86.R_AL); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x28 -****************************************************************************/ -void x86emuOp_sub_byte_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint destoffset; - u8 destval; - - START_OF_INSTR(); - DECODE_PRINTF("SUB\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sub_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sub_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sub_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x29 -****************************************************************************/ -void x86emuOp_sub_word_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("SUB\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sub_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sub_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sub_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sub_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sub_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = sub_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x2a -****************************************************************************/ -void x86emuOp_sub_byte_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint srcoffset; - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("SUB\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_byte(*destreg, srcval); - break; - case 1: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_byte(*destreg, srcval); - break; - case 2: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_byte(*destreg, srcval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x2b -****************************************************************************/ -void x86emuOp_sub_word_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("SUB\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_word(*destreg, srcval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_word(*destreg, srcval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_word(*destreg, srcval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = sub_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x2c -****************************************************************************/ -void x86emuOp_sub_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("SUB\tAL,"); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - M.x86.R_AL = sub_byte(M.x86.R_AL, srcval); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x2d -****************************************************************************/ -void x86emuOp_sub_word_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("SUB\tEAX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("SUB\tAX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = sub_long(M.x86.R_EAX, srcval); - } else { - M.x86.R_AX = sub_word(M.x86.R_AX, (u16)srcval); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x2e -****************************************************************************/ -void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("CS:\n"); - TRACE_AND_STEP(); - M.x86.mode |= SYSMODE_SEGOVR_CS; - /* note no DECODE_CLEAR_SEGOVR here. */ - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x2f -****************************************************************************/ -void x86emuOp_das(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("DAS\n"); - TRACE_AND_STEP(); - M.x86.R_AL = das_byte(M.x86.R_AL); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x30 -****************************************************************************/ -void x86emuOp_xor_byte_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint destoffset; - u8 destval; - - START_OF_INSTR(); - DECODE_PRINTF("XOR\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = xor_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = xor_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = xor_byte(destval, *srcreg); - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x31 -****************************************************************************/ -void x86emuOp_xor_word_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("XOR\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = xor_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = xor_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = xor_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = xor_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = xor_long(destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = xor_word(destval, *srcreg); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x32 -****************************************************************************/ -void x86emuOp_xor_byte_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint srcoffset; - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("XOR\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_byte(*destreg, srcval); - break; - case 1: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_byte(*destreg, srcval); - break; - case 2: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_byte(*destreg, srcval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x33 -****************************************************************************/ -void x86emuOp_xor_word_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("XOR\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_word(*destreg, srcval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_word(*destreg, srcval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_word(*destreg, srcval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = xor_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x34 -****************************************************************************/ -void x86emuOp_xor_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("XOR\tAL,"); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - M.x86.R_AL = xor_byte(M.x86.R_AL, srcval); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x35 -****************************************************************************/ -void x86emuOp_xor_word_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("XOR\tEAX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("XOR\tAX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = xor_long(M.x86.R_EAX, srcval); - } else { - M.x86.R_AX = xor_word(M.x86.R_AX, (u16)srcval); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x36 -****************************************************************************/ -void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("SS:\n"); - TRACE_AND_STEP(); - M.x86.mode |= SYSMODE_SEGOVR_SS; - /* no DECODE_CLEAR_SEGOVR ! */ - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x37 -****************************************************************************/ -void x86emuOp_aaa(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("AAA\n"); - TRACE_AND_STEP(); - M.x86.R_AX = aaa_word(M.x86.R_AX); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x38 -****************************************************************************/ -void x86emuOp_cmp_byte_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - u8 *destreg, *srcreg; - u8 destval; - - START_OF_INSTR(); - DECODE_PRINTF("CMP\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_byte(destval, *srcreg); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_byte(destval, *srcreg); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_byte(destval, *srcreg); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x39 -****************************************************************************/ -void x86emuOp_cmp_word_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("CMP\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_long(destval, *srcreg); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_word(destval, *srcreg); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_long(destval, *srcreg); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_word(destval, *srcreg); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_long(destval, *srcreg); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_word(destval, *srcreg); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x3a -****************************************************************************/ -void x86emuOp_cmp_byte_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint srcoffset; - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("CMP\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_byte(*destreg, srcval); - break; - case 1: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_byte(*destreg, srcval); - break; - case 2: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_byte(*destreg, srcval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x3b -****************************************************************************/ -void x86emuOp_cmp_word_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("CMP\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_word(*destreg, srcval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_word(*destreg, srcval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_word(*destreg, srcval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - cmp_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x3c -****************************************************************************/ -void x86emuOp_cmp_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("CMP\tAL,"); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - cmp_byte(M.x86.R_AL, srcval); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x3d -****************************************************************************/ -void x86emuOp_cmp_word_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CMP\tEAX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("CMP\tAX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - cmp_long(M.x86.R_EAX, srcval); - } else { - cmp_word(M.x86.R_AX, (u16)srcval); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x3e -****************************************************************************/ -void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("DS:\n"); - TRACE_AND_STEP(); - M.x86.mode |= SYSMODE_SEGOVR_DS; - /* NO DECODE_CLEAR_SEGOVR! */ - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x3f -****************************************************************************/ -void x86emuOp_aas(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("AAS\n"); - TRACE_AND_STEP(); - M.x86.R_AX = aas_word(M.x86.R_AX); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x40 -****************************************************************************/ -void x86emuOp_inc_AX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tEAX\n"); - } else { - DECODE_PRINTF("INC\tAX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = inc_long(M.x86.R_EAX); - } else { - M.x86.R_AX = inc_word(M.x86.R_AX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x41 -****************************************************************************/ -void x86emuOp_inc_CX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tECX\n"); - } else { - DECODE_PRINTF("INC\tCX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ECX = inc_long(M.x86.R_ECX); - } else { - M.x86.R_CX = inc_word(M.x86.R_CX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x42 -****************************************************************************/ -void x86emuOp_inc_DX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tEDX\n"); - } else { - DECODE_PRINTF("INC\tDX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDX = inc_long(M.x86.R_EDX); - } else { - M.x86.R_DX = inc_word(M.x86.R_DX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x43 -****************************************************************************/ -void x86emuOp_inc_BX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tEBX\n"); - } else { - DECODE_PRINTF("INC\tBX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EBX = inc_long(M.x86.R_EBX); - } else { - M.x86.R_BX = inc_word(M.x86.R_BX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x44 -****************************************************************************/ -void x86emuOp_inc_SP(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tESP\n"); - } else { - DECODE_PRINTF("INC\tSP\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ESP = inc_long(M.x86.R_ESP); - } else { - M.x86.R_SP = inc_word(M.x86.R_SP); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x45 -****************************************************************************/ -void x86emuOp_inc_BP(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tEBP\n"); - } else { - DECODE_PRINTF("INC\tBP\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EBP = inc_long(M.x86.R_EBP); - } else { - M.x86.R_BP = inc_word(M.x86.R_BP); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x46 -****************************************************************************/ -void x86emuOp_inc_SI(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tESI\n"); - } else { - DECODE_PRINTF("INC\tSI\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ESI = inc_long(M.x86.R_ESI); - } else { - M.x86.R_SI = inc_word(M.x86.R_SI); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x47 -****************************************************************************/ -void x86emuOp_inc_DI(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tEDI\n"); - } else { - DECODE_PRINTF("INC\tDI\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDI = inc_long(M.x86.R_EDI); - } else { - M.x86.R_DI = inc_word(M.x86.R_DI); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x48 -****************************************************************************/ -void x86emuOp_dec_AX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tEAX\n"); - } else { - DECODE_PRINTF("DEC\tAX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = dec_long(M.x86.R_EAX); - } else { - M.x86.R_AX = dec_word(M.x86.R_AX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x49 -****************************************************************************/ -void x86emuOp_dec_CX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tECX\n"); - } else { - DECODE_PRINTF("DEC\tCX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ECX = dec_long(M.x86.R_ECX); - } else { - M.x86.R_CX = dec_word(M.x86.R_CX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x4a -****************************************************************************/ -void x86emuOp_dec_DX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tEDX\n"); - } else { - DECODE_PRINTF("DEC\tDX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDX = dec_long(M.x86.R_EDX); - } else { - M.x86.R_DX = dec_word(M.x86.R_DX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x4b -****************************************************************************/ -void x86emuOp_dec_BX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tEBX\n"); - } else { - DECODE_PRINTF("DEC\tBX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EBX = dec_long(M.x86.R_EBX); - } else { - M.x86.R_BX = dec_word(M.x86.R_BX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x4c -****************************************************************************/ -void x86emuOp_dec_SP(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tESP\n"); - } else { - DECODE_PRINTF("DEC\tSP\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ESP = dec_long(M.x86.R_ESP); - } else { - M.x86.R_SP = dec_word(M.x86.R_SP); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x4d -****************************************************************************/ -void x86emuOp_dec_BP(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tEBP\n"); - } else { - DECODE_PRINTF("DEC\tBP\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EBP = dec_long(M.x86.R_EBP); - } else { - M.x86.R_BP = dec_word(M.x86.R_BP); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x4e -****************************************************************************/ -void x86emuOp_dec_SI(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tESI\n"); - } else { - DECODE_PRINTF("DEC\tSI\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ESI = dec_long(M.x86.R_ESI); - } else { - M.x86.R_SI = dec_word(M.x86.R_SI); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x4f -****************************************************************************/ -void x86emuOp_dec_DI(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tEDI\n"); - } else { - DECODE_PRINTF("DEC\tDI\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDI = dec_long(M.x86.R_EDI); - } else { - M.x86.R_DI = dec_word(M.x86.R_DI); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x50 -****************************************************************************/ -void x86emuOp_push_AX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSH\tEAX\n"); - } else { - DECODE_PRINTF("PUSH\tAX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_EAX); - } else { - push_word(M.x86.R_AX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x51 -****************************************************************************/ -void x86emuOp_push_CX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSH\tECX\n"); - } else { - DECODE_PRINTF("PUSH\tCX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_ECX); - } else { - push_word(M.x86.R_CX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x52 -****************************************************************************/ -void x86emuOp_push_DX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSH\tEDX\n"); - } else { - DECODE_PRINTF("PUSH\tDX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_EDX); - } else { - push_word(M.x86.R_DX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x53 -****************************************************************************/ -void x86emuOp_push_BX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSH\tEBX\n"); - } else { - DECODE_PRINTF("PUSH\tBX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_EBX); - } else { - push_word(M.x86.R_BX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x54 -****************************************************************************/ -void x86emuOp_push_SP(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSH\tESP\n"); - } else { - DECODE_PRINTF("PUSH\tSP\n"); - } - TRACE_AND_STEP(); - /* Always push (E)SP, since we are emulating an i386 and above - * processor. This is necessary as some BIOS'es use this to check - * what type of processor is in the system. - */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_ESP); - } else { - push_word((u16)(M.x86.R_SP)); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x55 -****************************************************************************/ -void x86emuOp_push_BP(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSH\tEBP\n"); - } else { - DECODE_PRINTF("PUSH\tBP\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_EBP); - } else { - push_word(M.x86.R_BP); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x56 -****************************************************************************/ -void x86emuOp_push_SI(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSH\tESI\n"); - } else { - DECODE_PRINTF("PUSH\tSI\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_ESI); - } else { - push_word(M.x86.R_SI); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x57 -****************************************************************************/ -void x86emuOp_push_DI(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSH\tEDI\n"); - } else { - DECODE_PRINTF("PUSH\tDI\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_EDI); - } else { - push_word(M.x86.R_DI); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x58 -****************************************************************************/ -void x86emuOp_pop_AX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POP\tEAX\n"); - } else { - DECODE_PRINTF("POP\tAX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = pop_long(); - } else { - M.x86.R_AX = pop_word(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x59 -****************************************************************************/ -void x86emuOp_pop_CX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POP\tECX\n"); - } else { - DECODE_PRINTF("POP\tCX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ECX = pop_long(); - } else { - M.x86.R_CX = pop_word(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x5a -****************************************************************************/ -void x86emuOp_pop_DX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POP\tEDX\n"); - } else { - DECODE_PRINTF("POP\tDX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDX = pop_long(); - } else { - M.x86.R_DX = pop_word(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x5b -****************************************************************************/ -void x86emuOp_pop_BX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POP\tEBX\n"); - } else { - DECODE_PRINTF("POP\tBX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EBX = pop_long(); - } else { - M.x86.R_BX = pop_word(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x5c -****************************************************************************/ -void x86emuOp_pop_SP(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POP\tESP\n"); - } else { - DECODE_PRINTF("POP\tSP\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ESP = pop_long(); - } else { - M.x86.R_SP = pop_word(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x5d -****************************************************************************/ -void x86emuOp_pop_BP(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POP\tEBP\n"); - } else { - DECODE_PRINTF("POP\tBP\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EBP = pop_long(); - } else { - M.x86.R_BP = pop_word(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x5e -****************************************************************************/ -void x86emuOp_pop_SI(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POP\tESI\n"); - } else { - DECODE_PRINTF("POP\tSI\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ESI = pop_long(); - } else { - M.x86.R_SI = pop_word(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x5f -****************************************************************************/ -void x86emuOp_pop_DI(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POP\tEDI\n"); - } else { - DECODE_PRINTF("POP\tDI\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDI = pop_long(); - } else { - M.x86.R_DI = pop_word(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x60 -****************************************************************************/ -void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSHAD\n"); - } else { - DECODE_PRINTF("PUSHA\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 old_sp = M.x86.R_ESP; - - push_long(M.x86.R_EAX); - push_long(M.x86.R_ECX); - push_long(M.x86.R_EDX); - push_long(M.x86.R_EBX); - push_long(old_sp); - push_long(M.x86.R_EBP); - push_long(M.x86.R_ESI); - push_long(M.x86.R_EDI); - } else { - u16 old_sp = M.x86.R_SP; - - push_word(M.x86.R_AX); - push_word(M.x86.R_CX); - push_word(M.x86.R_DX); - push_word(M.x86.R_BX); - push_word(old_sp); - push_word(M.x86.R_BP); - push_word(M.x86.R_SI); - push_word(M.x86.R_DI); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x61 -****************************************************************************/ -void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POPAD\n"); - } else { - DECODE_PRINTF("POPA\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDI = pop_long(); - M.x86.R_ESI = pop_long(); - M.x86.R_EBP = pop_long(); - M.x86.R_ESP += 4; /* skip ESP */ - M.x86.R_EBX = pop_long(); - M.x86.R_EDX = pop_long(); - M.x86.R_ECX = pop_long(); - M.x86.R_EAX = pop_long(); - } else { - M.x86.R_DI = pop_word(); - M.x86.R_SI = pop_word(); - M.x86.R_BP = pop_word(); - M.x86.R_SP += 2; /* skip SP */ - M.x86.R_BX = pop_word(); - M.x86.R_DX = pop_word(); - M.x86.R_CX = pop_word(); - M.x86.R_AX = pop_word(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ -/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ - -/**************************************************************************** -REMARKS: -Handles opcode 0x64 -****************************************************************************/ -void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("FS:\n"); - TRACE_AND_STEP(); - M.x86.mode |= SYSMODE_SEGOVR_FS; - /* - * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 - * opcode subroutines we do not want to do this. - */ - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x65 -****************************************************************************/ -void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("GS:\n"); - TRACE_AND_STEP(); - M.x86.mode |= SYSMODE_SEGOVR_GS; - /* - * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 - * opcode subroutines we do not want to do this. - */ - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x66 - prefix for 32-bit register -****************************************************************************/ -void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("DATA:\n"); - TRACE_AND_STEP(); - M.x86.mode |= SYSMODE_PREFIX_DATA; - /* note no DECODE_CLEAR_SEGOVR here. */ - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x67 - prefix for 32-bit address -****************************************************************************/ -void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("ADDR:\n"); - TRACE_AND_STEP(); - M.x86.mode |= SYSMODE_PREFIX_ADDR; - /* note no DECODE_CLEAR_SEGOVR here. */ - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x68 -****************************************************************************/ -void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 imm; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - imm = fetch_long_imm(); - } else { - imm = fetch_word_imm(); - } - DECODE_PRINTF2("PUSH\t%x\n", imm); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(imm); - } else { - push_word((u16)imm); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x69 -****************************************************************************/ -void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("IMUL\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - res = (s16)*srcreg * (s16)imm; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x6a -****************************************************************************/ -void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) -{ - s16 imm; - - START_OF_INSTR(); - imm = (s8)fetch_byte_imm(); - DECODE_PRINTF2("PUSH\t%d\n", imm); - TRACE_AND_STEP(); - push_word(imm); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x6b -****************************************************************************/ -void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint srcoffset; - s8 imm; - - START_OF_INSTR(); - DECODE_PRINTF("IMUL\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - res = (s16)*srcreg * (s16)imm; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x6c -****************************************************************************/ -void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("INSB\n"); - ins(1); - TRACE_AND_STEP(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x6d -****************************************************************************/ -void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INSD\n"); - ins(4); - } else { - DECODE_PRINTF("INSW\n"); - ins(2); - } - TRACE_AND_STEP(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x6e -****************************************************************************/ -void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("OUTSB\n"); - outs(1); - TRACE_AND_STEP(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x6f -****************************************************************************/ -void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("OUTSD\n"); - outs(4); - } else { - DECODE_PRINTF("OUTSW\n"); - outs(2); - } - TRACE_AND_STEP(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x70 -****************************************************************************/ -void x86emuOp_jump_near_O(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if overflow flag is set */ - START_OF_INSTR(); - DECODE_PRINTF("JO\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (ACCESS_FLAG(F_OF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x71 -****************************************************************************/ -void x86emuOp_jump_near_NO(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if overflow is not set */ - START_OF_INSTR(); - DECODE_PRINTF("JNO\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (!ACCESS_FLAG(F_OF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x72 -****************************************************************************/ -void x86emuOp_jump_near_B(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if carry flag is set. */ - START_OF_INSTR(); - DECODE_PRINTF("JB\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (ACCESS_FLAG(F_CF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x73 -****************************************************************************/ -void x86emuOp_jump_near_NB(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if carry flag is clear. */ - START_OF_INSTR(); - DECODE_PRINTF("JNB\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (!ACCESS_FLAG(F_CF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x74 -****************************************************************************/ -void x86emuOp_jump_near_Z(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if zero flag is set. */ - START_OF_INSTR(); - DECODE_PRINTF("JZ\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (ACCESS_FLAG(F_ZF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x75 -****************************************************************************/ -void x86emuOp_jump_near_NZ(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if zero flag is clear. */ - START_OF_INSTR(); - DECODE_PRINTF("JNZ\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (!ACCESS_FLAG(F_ZF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x76 -****************************************************************************/ -void x86emuOp_jump_near_BE(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if carry flag is set or if the zero - flag is set. */ - START_OF_INSTR(); - DECODE_PRINTF("JBE\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x77 -****************************************************************************/ -void x86emuOp_jump_near_NBE(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if carry flag is clear and if the zero - flag is clear */ - START_OF_INSTR(); - DECODE_PRINTF("JNBE\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (!(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF))) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x78 -****************************************************************************/ -void x86emuOp_jump_near_S(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if sign flag is set */ - START_OF_INSTR(); - DECODE_PRINTF("JS\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (ACCESS_FLAG(F_SF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x79 -****************************************************************************/ -void x86emuOp_jump_near_NS(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if sign flag is clear */ - START_OF_INSTR(); - DECODE_PRINTF("JNS\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (!ACCESS_FLAG(F_SF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x7a -****************************************************************************/ -void x86emuOp_jump_near_P(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if parity flag is set (even parity) */ - START_OF_INSTR(); - DECODE_PRINTF("JP\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (ACCESS_FLAG(F_PF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x7b -****************************************************************************/ -void x86emuOp_jump_near_NP(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - - /* jump to byte offset if parity flag is clear (odd parity) */ - START_OF_INSTR(); - DECODE_PRINTF("JNP\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (!ACCESS_FLAG(F_PF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x7c -****************************************************************************/ -void x86emuOp_jump_near_L(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - int sf, of; - - /* jump to byte offset if sign flag not equal to overflow flag. */ - START_OF_INSTR(); - DECODE_PRINTF("JL\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - sf = ACCESS_FLAG(F_SF) != 0; - of = ACCESS_FLAG(F_OF) != 0; - if (sf ^ of) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x7d -****************************************************************************/ -void x86emuOp_jump_near_NL(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - int sf, of; - - /* jump to byte offset if sign flag not equal to overflow flag. */ - START_OF_INSTR(); - DECODE_PRINTF("JNL\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - sf = ACCESS_FLAG(F_SF) != 0; - of = ACCESS_FLAG(F_OF) != 0; - /* note: inverse of above, but using == instead of xor. */ - if (sf == of) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x7e -****************************************************************************/ -void x86emuOp_jump_near_LE(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - int sf, of; - - /* jump to byte offset if sign flag not equal to overflow flag - or the zero flag is set */ - START_OF_INSTR(); - DECODE_PRINTF("JLE\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - sf = ACCESS_FLAG(F_SF) != 0; - of = ACCESS_FLAG(F_OF) != 0; - if ((sf ^ of) || ACCESS_FLAG(F_ZF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x7f -****************************************************************************/ -void x86emuOp_jump_near_NLE(u8 X86EMU_UNUSED(op1)) -{ - s8 offset; - u16 target; - int sf, of; - - /* jump to byte offset if sign flag equal to overflow flag. - and the zero flag is clear */ - START_OF_INSTR(); - DECODE_PRINTF("JNLE\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + (s16)offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - sf = ACCESS_FLAG(F_SF) != 0; - of = ACCESS_FLAG(F_OF) != 0; - if ((sf == of) && !ACCESS_FLAG(F_ZF)) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -static u8 (*opc80_byte_operation[])(u8 d, u8 s) = -{ - add_byte, /* 00 */ - or_byte, /* 01 */ - adc_byte, /* 02 */ - sbb_byte, /* 03 */ - and_byte, /* 04 */ - sub_byte, /* 05 */ - xor_byte, /* 06 */ - cmp_byte, /* 07 */ -}; - -/**************************************************************************** -REMARKS: -Handles opcode 0x80 -****************************************************************************/ -void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg; - uint destoffset; - u8 imm; - u8 destval; - - /* - * Weirdo special case instruction format. Part of the opcode - * held below in "RH". Doubly nested case would result, except - * that the decoded instruction - */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } - } -#endif - /* know operation, decode the mod byte to find the addressing - mode. */ - switch (mod) { - case 0: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc80_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - break; - case 1: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc80_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - break; - case 2: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc80_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc80_byte_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -static u16 (*opc81_word_operation[])(u16 d, u16 s) = -{ - add_word, /*00 */ - or_word, /*01 */ - adc_word, /*02 */ - sbb_word, /*03 */ - and_word, /*04 */ - sub_word, /*05 */ - xor_word, /*06 */ - cmp_word, /*07 */ -}; - -static u32 (*opc81_long_operation[])(u32 d, u32 s) = -{ - add_long, /*00 */ - or_long, /*01 */ - adc_long, /*02 */ - sbb_long, /*03 */ - and_long, /*04 */ - sub_long, /*05 */ - xor_long, /*06 */ - cmp_long, /*07 */ -}; - -/**************************************************************************** -REMARKS: -Handles opcode 0x81 -****************************************************************************/ -void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - /* - * Weirdo special case instruction format. Part of the opcode - * held below in "RH". Doubly nested case would result, except - * that the decoded instruction - */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } - } -#endif - /* - * Know operation, decode the mod byte to find the addressing - * mode. - */ - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc81_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc81_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc81_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc81_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc81_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc81_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 destval,imm; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc81_long_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } else { - u16 *destreg; - u16 destval,imm; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc81_word_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -static u8 (*opc82_byte_operation[])(u8 s, u8 d) = -{ - add_byte, /*00 */ - or_byte, /*01 */ /*YYY UNUSED ???? */ - adc_byte, /*02 */ - sbb_byte, /*03 */ - and_byte, /*04 */ /*YYY UNUSED ???? */ - sub_byte, /*05 */ - xor_byte, /*06 */ /*YYY UNUSED ???? */ - cmp_byte, /*07 */ -}; - -/**************************************************************************** -REMARKS: -Handles opcode 0x82 -****************************************************************************/ -void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg; - uint destoffset; - u8 imm; - u8 destval; - - /* - * Weirdo special case instruction format. Part of the opcode - * held below in "RH". Doubly nested case would result, except - * that the decoded instruction Similar to opcode 81, except that - * the immediate byte is sign extended to a word length. - */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } - } -#endif - /* know operation, decode the mod byte to find the addressing - mode. */ - switch (mod) { - case 0: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm00_address(rl); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc82_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - break; - case 1: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm01_address(rl); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc82_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - break; - case 2: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm10_address(rl); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc82_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc82_byte_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -static u16 (*opc83_word_operation[])(u16 s, u16 d) = -{ - add_word, /*00 */ - or_word, /*01 */ /*YYY UNUSED ???? */ - adc_word, /*02 */ - sbb_word, /*03 */ - and_word, /*04 */ /*YYY UNUSED ???? */ - sub_word, /*05 */ - xor_word, /*06 */ /*YYY UNUSED ???? */ - cmp_word, /*07 */ -}; - -static u32 (*opc83_long_operation[])(u32 s, u32 d) = -{ - add_long, /*00 */ - or_long, /*01 */ /*YYY UNUSED ???? */ - adc_long, /*02 */ - sbb_long, /*03 */ - and_long, /*04 */ /*YYY UNUSED ???? */ - sub_long, /*05 */ - xor_long, /*06 */ /*YYY UNUSED ???? */ - cmp_long, /*07 */ -}; - -/**************************************************************************** -REMARKS: -Handles opcode 0x83 -****************************************************************************/ -void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - /* - * Weirdo special case instruction format. Part of the opcode - * held below in "RH". Doubly nested case would result, except - * that the decoded instruction Similar to opcode 81, except that - * the immediate byte is sign extended to a word length. - */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } - } -#endif - /* know operation, decode the mod byte to find the addressing - mode. */ - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm00_address(rl); - destval = fetch_data_long(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc83_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm00_address(rl); - destval = fetch_data_word(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc83_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm01_address(rl); - destval = fetch_data_long(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc83_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm01_address(rl); - destval = fetch_data_word(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc83_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm10_address(rl); - destval = fetch_data_long(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc83_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm10_address(rl); - destval = fetch_data_word(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc83_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 destval,imm; - - destreg = DECODE_RM_LONG_REGISTER(rl); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc83_long_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } else { - u16 *destreg; - u16 destval,imm; - - destreg = DECODE_RM_WORD_REGISTER(rl); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*opc83_word_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x84 -****************************************************************************/ -void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint destoffset; - u8 destval; - - START_OF_INSTR(); - DECODE_PRINTF("TEST\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(destval, *srcreg); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(destval, *srcreg); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(destval, *srcreg); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(*destreg, *srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x85 -****************************************************************************/ -void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("TEST\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(destval, *srcreg); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(destval, *srcreg); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(destval, *srcreg); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(destval, *srcreg); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(destval, *srcreg); - } else { - u16 destval; - u16 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(destval, *srcreg); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(*destreg, *srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x86 -****************************************************************************/ -void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint destoffset; - u8 destval; - u8 tmp; - - START_OF_INSTR(); - DECODE_PRINTF("XCHG\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_byte(destoffset, destval); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_byte(destoffset, destval); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x87 -****************************************************************************/ -void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("XCHG\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - u32 destval,tmp; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_long(destoffset, destval); - } else { - u16 *srcreg; - u16 destval,tmp; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - u32 destval,tmp; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_long(destoffset, destval); - } else { - u16 *srcreg; - u16 destval,tmp; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - u32 destval,tmp; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_long(destoffset, destval); - } else { - u16 *srcreg; - u16 destval,tmp; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 tmp; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; - } else { - u16 *destreg,*srcreg; - u16 tmp; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x88 -****************************************************************************/ -void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_byte(destoffset, *srcreg); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_byte(destoffset, *srcreg); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_byte(destoffset, *srcreg); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x89 -****************************************************************************/ -void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_long(destoffset, *srcreg); - } else { - u16 *srcreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_word(destoffset, *srcreg); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_long(destoffset, *srcreg); - } else { - u16 *srcreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_word(destoffset, *srcreg); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_long(destoffset, *srcreg); - } else { - u16 *srcreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_word(destoffset, *srcreg); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x8a -****************************************************************************/ -void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg, *srcreg; - uint srcoffset; - u8 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 1: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 2: - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x8b -****************************************************************************/ -void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg, *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg, *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x8c -****************************************************************************/ -void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u16 *destreg, *srcreg; - uint destoffset; - u16 destval; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = *srcreg; - store_data_word(destoffset, destval); - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = *srcreg; - store_data_word(destoffset, destval); - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = *srcreg; - store_data_word(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x8d -****************************************************************************/ -void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u16 *srcreg; - uint destoffset; - -/* - * TODO: Need to handle address size prefix! - * - * lea eax,[eax+ebx*2] ?? - */ - - START_OF_INSTR(); - DECODE_PRINTF("LEA\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *srcreg = (u16)destoffset; - break; - case 1: - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *srcreg = (u16)destoffset; - break; - case 2: - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *srcreg = (u16)destoffset; - break; - case 3: /* register to register */ - /* undefined. Do nothing. */ - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x8e -****************************************************************************/ -void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u16 *destreg, *srcreg; - uint srcoffset; - u16 srcval; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 1: - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 2: - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 3: /* register to register */ - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - break; - } - /* - * Clean up, and reset all the R_xSP pointers to the correct - * locations. This is about 3x too much overhead (doing all the - * segreg ptrs when only one is needed, but this instruction - * *cannot* be that common, and this isn't too much work anyway. - */ - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x8f -****************************************************************************/ -void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("POP\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); - HALT_SYS(); - } - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_long(); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_word(); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_long(); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_word(); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_long(); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_word(); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = pop_long(); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = pop_word(); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x90 -****************************************************************************/ -void x86emuOp_nop(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("NOP\n"); - TRACE_AND_STEP(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x91 -****************************************************************************/ -void x86emuOp_xchg_word_AX_CX(u8 X86EMU_UNUSED(op1)) -{ - u32 tmp; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("XCHG\tEAX,ECX\n"); - } else { - DECODE_PRINTF("XCHG\tAX,CX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - tmp = M.x86.R_EAX; - M.x86.R_EAX = M.x86.R_ECX; - M.x86.R_ECX = tmp; - } else { - tmp = M.x86.R_AX; - M.x86.R_AX = M.x86.R_CX; - M.x86.R_CX = (u16)tmp; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x92 -****************************************************************************/ -void x86emuOp_xchg_word_AX_DX(u8 X86EMU_UNUSED(op1)) -{ - u32 tmp; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("XCHG\tEAX,EDX\n"); - } else { - DECODE_PRINTF("XCHG\tAX,DX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - tmp = M.x86.R_EAX; - M.x86.R_EAX = M.x86.R_EDX; - M.x86.R_EDX = tmp; - } else { - tmp = M.x86.R_AX; - M.x86.R_AX = M.x86.R_DX; - M.x86.R_DX = (u16)tmp; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x93 -****************************************************************************/ -void x86emuOp_xchg_word_AX_BX(u8 X86EMU_UNUSED(op1)) -{ - u32 tmp; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("XCHG\tEAX,EBX\n"); - } else { - DECODE_PRINTF("XCHG\tAX,BX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - tmp = M.x86.R_EAX; - M.x86.R_EAX = M.x86.R_EBX; - M.x86.R_EBX = tmp; - } else { - tmp = M.x86.R_AX; - M.x86.R_AX = M.x86.R_BX; - M.x86.R_BX = (u16)tmp; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x94 -****************************************************************************/ -void x86emuOp_xchg_word_AX_SP(u8 X86EMU_UNUSED(op1)) -{ - u32 tmp; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("XCHG\tEAX,ESP\n"); - } else { - DECODE_PRINTF("XCHG\tAX,SP\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - tmp = M.x86.R_EAX; - M.x86.R_EAX = M.x86.R_ESP; - M.x86.R_ESP = tmp; - } else { - tmp = M.x86.R_AX; - M.x86.R_AX = M.x86.R_SP; - M.x86.R_SP = (u16)tmp; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x95 -****************************************************************************/ -void x86emuOp_xchg_word_AX_BP(u8 X86EMU_UNUSED(op1)) -{ - u32 tmp; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("XCHG\tEAX,EBP\n"); - } else { - DECODE_PRINTF("XCHG\tAX,BP\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - tmp = M.x86.R_EAX; - M.x86.R_EAX = M.x86.R_EBP; - M.x86.R_EBP = tmp; - } else { - tmp = M.x86.R_AX; - M.x86.R_AX = M.x86.R_BP; - M.x86.R_BP = (u16)tmp; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x96 -****************************************************************************/ -void x86emuOp_xchg_word_AX_SI(u8 X86EMU_UNUSED(op1)) -{ - u32 tmp; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("XCHG\tEAX,ESI\n"); - } else { - DECODE_PRINTF("XCHG\tAX,SI\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - tmp = M.x86.R_EAX; - M.x86.R_EAX = M.x86.R_ESI; - M.x86.R_ESI = tmp; - } else { - tmp = M.x86.R_AX; - M.x86.R_AX = M.x86.R_SI; - M.x86.R_SI = (u16)tmp; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x97 -****************************************************************************/ -void x86emuOp_xchg_word_AX_DI(u8 X86EMU_UNUSED(op1)) -{ - u32 tmp; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("XCHG\tEAX,EDI\n"); - } else { - DECODE_PRINTF("XCHG\tAX,DI\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - tmp = M.x86.R_EAX; - M.x86.R_EAX = M.x86.R_EDI; - M.x86.R_EDI = tmp; - } else { - tmp = M.x86.R_AX; - M.x86.R_AX = M.x86.R_DI; - M.x86.R_DI = (u16)tmp; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x98 -****************************************************************************/ -void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CWDE\n"); - } else { - DECODE_PRINTF("CBW\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - if (M.x86.R_AX & 0x8000) { - M.x86.R_EAX |= 0xffff0000; - } else { - M.x86.R_EAX &= 0x0000ffff; - } - } else { - if (M.x86.R_AL & 0x80) { - M.x86.R_AH = 0xff; - } else { - M.x86.R_AH = 0x0; - } - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x99 -****************************************************************************/ -void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CDQ\n"); - } else { - DECODE_PRINTF("CWD\n"); - } - DECODE_PRINTF("CWD\n"); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - if (M.x86.R_EAX & 0x80000000) { - M.x86.R_EDX = 0xffffffff; - } else { - M.x86.R_EDX = 0x0; - } - } else { - if (M.x86.R_AX & 0x8000) { - M.x86.R_DX = 0xffff; - } else { - M.x86.R_DX = 0x0; - } - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x9a -****************************************************************************/ -void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) -{ - u16 farseg, faroff; - - START_OF_INSTR(); - DECODE_PRINTF("CALL\t"); - faroff = fetch_word_imm(); - farseg = fetch_word_imm(); - DECODE_PRINTF2("%04x:", farseg); - DECODE_PRINTF2("%04x\n", faroff); - CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); - - /* XXX - * - * Hooked interrupt vectors calling into our "BIOS" will cause - * problems unless all intersegment stuff is checked for BIOS - * access. Check needed here. For moment, let it alone. - */ - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - M.x86.R_CS = farseg; - push_word(M.x86.R_IP); - M.x86.R_IP = faroff; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x9b -****************************************************************************/ -void x86emuOp_wait(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("WAIT"); - TRACE_AND_STEP(); - /* NADA. */ - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x9c -****************************************************************************/ -void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) -{ - u32 flags; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSHFD\n"); - } else { - DECODE_PRINTF("PUSHF\n"); - } - TRACE_AND_STEP(); - - /* clear out *all* bits not representing flags, and turn on real bits */ - flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(flags); - } else { - push_word((u16)flags); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x9d -****************************************************************************/ -void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POPFD\n"); - } else { - DECODE_PRINTF("POPF\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EFLG = pop_long(); - } else { - M.x86.R_FLG = pop_word(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x9e -****************************************************************************/ -void x86emuOp_sahf(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("SAHF\n"); - TRACE_AND_STEP(); - /* clear the lower bits of the flag register */ - M.x86.R_FLG &= 0xffffff00; - /* or in the AH register into the flags register */ - M.x86.R_FLG |= M.x86.R_AH; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x9f -****************************************************************************/ -void x86emuOp_lahf(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("LAHF\n"); - TRACE_AND_STEP(); - M.x86.R_AH = (u8)(M.x86.R_FLG & 0xff); - /*undocumented TC++ behavior??? Nope. It's documented, but - you have too look real hard to notice it. */ - M.x86.R_AH |= 0x2; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xa0 -****************************************************************************/ -void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1)) -{ - u16 offset; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\tAL,"); - offset = fetch_word_imm(); - DECODE_PRINTF2("[%04x]\n", offset); - TRACE_AND_STEP(); - M.x86.R_AL = fetch_data_byte(offset); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xa1 -****************************************************************************/ -void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) -{ - u16 offset; - - START_OF_INSTR(); - offset = fetch_word_imm(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); - } else { - DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = fetch_data_long(offset); - } else { - M.x86.R_AX = fetch_data_word(offset); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xa2 -****************************************************************************/ -void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u16 offset; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\t"); - offset = fetch_word_imm(); - DECODE_PRINTF2("[%04x],AL\n", offset); - TRACE_AND_STEP(); - store_data_byte(offset, M.x86.R_AL); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xa3 -****************************************************************************/ -void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u16 offset; - - START_OF_INSTR(); - offset = fetch_word_imm(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); - } else { - DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - store_data_long(offset, M.x86.R_EAX); - } else { - store_data_word(offset, M.x86.R_AX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xa4 -****************************************************************************/ -void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) -{ - u8 val; - u32 count; - int inc; - - START_OF_INSTR(); - DECODE_PRINTF("MOVS\tBYTE\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; - else - inc = 1; - TRACE_AND_STEP(); - count = 1; - if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); - } - while (count--) { - val = fetch_data_byte(M.x86.R_SI); - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); - M.x86.R_SI += inc; - M.x86.R_DI += inc; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xa5 -****************************************************************************/ -void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) -{ - u32 val; - int inc; - u32 count; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOVS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; - } else { - DECODE_PRINTF("MOVS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; - } - TRACE_AND_STEP(); - count = 1; - if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); - } - while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long(M.x86.R_SI); - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); - } else { - val = fetch_data_word(M.x86.R_SI); - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); - } - M.x86.R_SI += inc; - M.x86.R_DI += inc; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xa6 -****************************************************************************/ -void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) -{ - s8 val1, val2; - int inc; - - START_OF_INSTR(); - DECODE_PRINTF("CMPS\tBYTE\n"); - TRACE_AND_STEP(); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; - else - inc = 1; - - if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - val1 = fetch_data_byte(M.x86.R_SI); - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(val1, val2); - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; - } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - val1 = fetch_data_byte(M.x86.R_SI); - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(val1, val2); - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; - } else { - val1 = fetch_data_byte(M.x86.R_SI); - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(val1, val2); - M.x86.R_SI += inc; - M.x86.R_DI += inc; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xa7 -****************************************************************************/ -void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) -{ - u32 val1,val2; - int inc; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CMPS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; - } else { - DECODE_PRINTF("CMPS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val1 = fetch_data_long(M.x86.R_SI); - val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(val1, val2); - } else { - val1 = fetch_data_word(M.x86.R_SI); - val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word((u16)val1, (u16)val2); - } - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; - } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val1 = fetch_data_long(M.x86.R_SI); - val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(val1, val2); - } else { - val1 = fetch_data_word(M.x86.R_SI); - val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word((u16)val1, (u16)val2); - } - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; - } else { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val1 = fetch_data_long(M.x86.R_SI); - val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(val1, val2); - } else { - val1 = fetch_data_word(M.x86.R_SI); - val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word((u16)val1, (u16)val2); - } - M.x86.R_SI += inc; - M.x86.R_DI += inc; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xa8 -****************************************************************************/ -void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - int imm; - - START_OF_INSTR(); - DECODE_PRINTF("TEST\tAL,"); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%04x\n", imm); - TRACE_AND_STEP(); - test_byte(M.x86.R_AL, (u8)imm); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xa9 -****************************************************************************/ -void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("TEST\tEAX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("TEST\tAX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - test_long(M.x86.R_EAX, srcval); - } else { - test_word(M.x86.R_AX, (u16)srcval); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xaa -****************************************************************************/ -void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) -{ - int inc; - - START_OF_INSTR(); - DECODE_PRINTF("STOS\tBYTE\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; - else - inc = 1; - TRACE_AND_STEP(); - if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); - } else { - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); - M.x86.R_DI += inc; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xab -****************************************************************************/ -void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) -{ - int inc; - u32 count; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("STOS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; - } else { - DECODE_PRINTF("STOS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; - } - TRACE_AND_STEP(); - count = 1; - if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); - } - while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); - } else { - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); - } - M.x86.R_DI += inc; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xac -****************************************************************************/ -void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) -{ - int inc; - - START_OF_INSTR(); - DECODE_PRINTF("LODS\tBYTE\n"); - TRACE_AND_STEP(); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; - else - inc = 1; - if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - M.x86.R_AL = fetch_data_byte(M.x86.R_SI); - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); - } else { - M.x86.R_AL = fetch_data_byte(M.x86.R_SI); - M.x86.R_SI += inc; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xad -****************************************************************************/ -void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) -{ - int inc; - u32 count; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("LODS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; - } else { - DECODE_PRINTF("LODS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; - } - TRACE_AND_STEP(); - count = 1; - if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); - } - while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = fetch_data_long(M.x86.R_SI); - } else { - M.x86.R_AX = fetch_data_word(M.x86.R_SI); - } - M.x86.R_SI += inc; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xae -****************************************************************************/ -void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) -{ - s8 val2; - int inc; - - START_OF_INSTR(); - DECODE_PRINTF("SCAS\tBYTE\n"); - TRACE_AND_STEP(); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; - else - inc = 1; - if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; - } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; - } else { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - M.x86.R_DI += inc; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xaf -****************************************************************************/ -void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) -{ - int inc; - u32 val; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("SCAS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; - } else { - DECODE_PRINTF("SCAS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; - } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; - } else { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - M.x86.R_DI += inc; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xb0 -****************************************************************************/ -void x86emuOp_mov_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 imm; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\tAL,"); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - M.x86.R_AL = imm; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xb1 -****************************************************************************/ -void x86emuOp_mov_byte_CL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 imm; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\tCL,"); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - M.x86.R_CL = imm; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xb2 -****************************************************************************/ -void x86emuOp_mov_byte_DL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 imm; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\tDL,"); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - M.x86.R_DL = imm; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xb3 -****************************************************************************/ -void x86emuOp_mov_byte_BL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 imm; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\tBL,"); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - M.x86.R_BL = imm; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xb4 -****************************************************************************/ -void x86emuOp_mov_byte_AH_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 imm; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\tAH,"); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - M.x86.R_AH = imm; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xb5 -****************************************************************************/ -void x86emuOp_mov_byte_CH_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 imm; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\tCH,"); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - M.x86.R_CH = imm; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xb6 -****************************************************************************/ -void x86emuOp_mov_byte_DH_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 imm; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\tDH,"); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - M.x86.R_DH = imm; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xb7 -****************************************************************************/ -void x86emuOp_mov_byte_BH_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 imm; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\tBH,"); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - M.x86.R_BH = imm; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xb8 -****************************************************************************/ -void x86emuOp_mov_word_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOV\tEAX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("MOV\tAX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = srcval; - } else { - M.x86.R_AX = (u16)srcval; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xb9 -****************************************************************************/ -void x86emuOp_mov_word_CX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOV\tECX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("MOV\tCX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ECX = srcval; - } else { - M.x86.R_CX = (u16)srcval; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xba -****************************************************************************/ -void x86emuOp_mov_word_DX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOV\tEDX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("MOV\tDX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDX = srcval; - } else { - M.x86.R_DX = (u16)srcval; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xbb -****************************************************************************/ -void x86emuOp_mov_word_BX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOV\tEBX,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("MOV\tBX,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EBX = srcval; - } else { - M.x86.R_BX = (u16)srcval; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xbc -****************************************************************************/ -void x86emuOp_mov_word_SP_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOV\tESP,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("MOV\tSP,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ESP = srcval; - } else { - M.x86.R_SP = (u16)srcval; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xbd -****************************************************************************/ -void x86emuOp_mov_word_BP_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOV\tEBP,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("MOV\tBP,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EBP = srcval; - } else { - M.x86.R_BP = (u16)srcval; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xbe -****************************************************************************/ -void x86emuOp_mov_word_SI_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOV\tESI,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("MOV\tSI,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ESI = srcval; - } else { - M.x86.R_SI = (u16)srcval; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xbf -****************************************************************************/ -void x86emuOp_mov_word_DI_IMM(u8 X86EMU_UNUSED(op1)) -{ - u32 srcval; - - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOV\tEDI,"); - srcval = fetch_long_imm(); - } else { - DECODE_PRINTF("MOV\tDI,"); - srcval = fetch_word_imm(); - } - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDI = srcval; - } else { - M.x86.R_DI = (u16)srcval; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/* used by opcodes c0, d0, and d2. */ -static u8(*opcD0_byte_operation[])(u8 d, u8 s) = -{ - rol_byte, - ror_byte, - rcl_byte, - rcr_byte, - shl_byte, - shr_byte, - shl_byte, /* sal_byte === shl_byte by definition */ - sar_byte, -}; - -/**************************************************************************** -REMARKS: -Handles opcode 0xc0 -****************************************************************************/ -void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg; - uint destoffset; - u8 destval; - u8 amt; - - /* - * Yet another weirdo special case instruction format. Part of - * the opcode held below in "RH". Doubly nested case would - * result, except that the decoded instruction - */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } - } -#endif - /* know operation, decode the mod byte to find the addressing - mode. */ - switch (mod) { - case 0: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm00_address(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - break; - case 1: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm01_address(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - break; - case 2: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm10_address(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, amt); - *destreg = destval; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/* used by opcodes c1, d1, and d3. */ -static u16(*opcD1_word_operation[])(u16 s, u8 d) = -{ - rol_word, - ror_word, - rcl_word, - rcr_word, - shl_word, - shr_word, - shl_word, /* sal_byte === shl_byte by definition */ - sar_word, -}; - -/* used by opcodes c1, d1, and d3. */ -static u32 (*opcD1_long_operation[])(u32 s, u8 d) = -{ - rol_long, - ror_long, - rcl_long, - rcr_long, - shl_long, - shr_long, - shl_long, /* sal_byte === shl_byte by definition */ - sar_long, -}; - -/**************************************************************************** -REMARKS: -Handles opcode 0xc1 -****************************************************************************/ -void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - u8 amt; - - /* - * Yet another weirdo special case instruction format. Part of - * the opcode held below in "RH". Doubly nested case would - * result, except that the decoded instruction - */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } - } -#endif - /* know operation, decode the mod byte to find the addressing - mode. */ - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm00_address(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm00_address(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm01_address(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm01_address(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm10_address(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm10_address(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xc2 -****************************************************************************/ -void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1)) -{ - u16 imm; - - START_OF_INSTR(); - DECODE_PRINTF("RET\t"); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); - TRACE_AND_STEP(); - M.x86.R_IP = pop_word(); - M.x86.R_SP += imm; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xc3 -****************************************************************************/ -void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("RET\n"); - RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); - TRACE_AND_STEP(); - M.x86.R_IP = pop_word(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xc4 -****************************************************************************/ -void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rh, rl; - u16 *dstreg; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("LES\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_ES = fetch_data_word(srcoffset + 2); - break; - case 1: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_ES = fetch_data_word(srcoffset + 2); - break; - case 2: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_ES = fetch_data_word(srcoffset + 2); - break; - case 3: /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xc5 -****************************************************************************/ -void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rh, rl; - u16 *dstreg; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("LDS\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_DS = fetch_data_word(srcoffset + 2); - break; - case 1: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_DS = fetch_data_word(srcoffset + 2); - break; - case 2: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_DS = fetch_data_word(srcoffset + 2); - break; - case 3: /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xc6 -****************************************************************************/ -void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg; - uint destoffset; - u8 imm; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); - HALT_SYS(); - } - switch (mod) { - case 0: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm00_address(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - store_data_byte(destoffset, imm); - break; - case 1: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm01_address(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - store_data_byte(destoffset, imm); - break; - case 2: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm10_address(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - store_data_byte(destoffset, imm); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xc7 -****************************************************************************/ -void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("MOV\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); - HALT_SYS(); - } - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm00_address(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_long(destoffset, imm); - } else { - u16 imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm00_address(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_word(destoffset, imm); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm01_address(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_long(destoffset, imm); - } else { - u16 imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm01_address(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_word(destoffset, imm); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm10_address(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_long(destoffset, imm); - } else { - u16 imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm10_address(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_word(destoffset, imm); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; - } else { - u16 *destreg; - u16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xc8 -****************************************************************************/ -void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) -{ - u16 local,frame_pointer; - u8 nesting; - int i; - - START_OF_INSTR(); - local = fetch_word_imm(); - nesting = fetch_byte_imm(); - DECODE_PRINTF2("ENTER %x\n", local); - DECODE_PRINTF2(",%x\n", nesting); - TRACE_AND_STEP(); - push_word(M.x86.R_BP); - frame_pointer = M.x86.R_SP; - if (nesting > 0) { - for (i = 1; i < nesting; i++) { - M.x86.R_BP -= 2; - push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); - } - push_word(frame_pointer); - } - M.x86.R_BP = frame_pointer; - M.x86.R_SP = (u16)(M.x86.R_SP - local); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xc9 -****************************************************************************/ -void x86emuOp_leave(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("LEAVE\n"); - TRACE_AND_STEP(); - M.x86.R_SP = M.x86.R_BP; - M.x86.R_BP = pop_word(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xca -****************************************************************************/ -void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1)) -{ - u16 imm; - - START_OF_INSTR(); - DECODE_PRINTF("RETF\t"); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); - TRACE_AND_STEP(); - M.x86.R_IP = pop_word(); - M.x86.R_CS = pop_word(); - M.x86.R_SP += imm; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xcb -****************************************************************************/ -void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("RETF\n"); - RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); - TRACE_AND_STEP(); - M.x86.R_IP = pop_word(); - M.x86.R_CS = pop_word(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xcc -****************************************************************************/ -void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) -{ - u16 tmp; - - START_OF_INSTR(); - DECODE_PRINTF("INT 3\n"); - tmp = (u16) mem_access_word(3 * 4 + 2); - /* access the segment register */ - TRACE_AND_STEP(); - if (_X86EMU_intrTab[3]) { - (*_X86EMU_intrTab[3])(3); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(3 * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(3 * 4); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xcd -****************************************************************************/ -void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) -{ - u16 tmp; - u8 intnum; - - START_OF_INSTR(); - DECODE_PRINTF("INT\t"); - intnum = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", intnum); - tmp = mem_access_word(intnum * 4 + 2); - TRACE_AND_STEP(); - if (_X86EMU_intrTab[intnum]) { - (*_X86EMU_intrTab[intnum])(intnum); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(intnum * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(intnum * 4); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xce -****************************************************************************/ -void x86emuOp_into(u8 X86EMU_UNUSED(op1)) -{ - u16 tmp; - - START_OF_INSTR(); - DECODE_PRINTF("INTO\n"); - TRACE_AND_STEP(); - if (ACCESS_FLAG(F_OF)) { - tmp = mem_access_word(4 * 4 + 2); - if (_X86EMU_intrTab[4]) { - (*_X86EMU_intrTab[4])(4); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(4 * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(4 * 4); - } - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xcf -****************************************************************************/ -void x86emuOp_iret(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("IRET\n"); - - TRACE_AND_STEP(); - - M.x86.R_IP = pop_word(); - M.x86.R_CS = pop_word(); - M.x86.R_FLG = pop_word(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xd0 -****************************************************************************/ -void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg; - uint destoffset; - u8 destval; - - /* - * Yet another weirdo special case instruction format. Part of - * the opcode held below in "RH". Doubly nested case would - * result, except that the decoded instruction - */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } - } -#endif - /* know operation, decode the mod byte to find the addressing - mode. */ - switch (mod) { - case 0: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, 1); - store_data_byte(destoffset, destval); - break; - case 1: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, 1); - store_data_byte(destoffset, destval); - break; - case 2: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, 1); - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, 1); - *destreg = destval; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xd1 -****************************************************************************/ -void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - /* - * Yet another weirdo special case instruction format. Part of - * the opcode held below in "RH". Doubly nested case would - * result, except that the decoded instruction - */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } - } -#endif - /* know operation, decode the mod byte to find the addressing - mode. */ - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, 1); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, 1); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, 1); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, 1); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, 1); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, 1); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (*destreg, 1); - *destreg = destval; - } else { - u16 destval; - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (*destreg, 1); - *destreg = destval; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xd2 -****************************************************************************/ -void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg; - uint destoffset; - u8 destval; - u8 amt; - - /* - * Yet another weirdo special case instruction format. Part of - * the opcode held below in "RH". Doubly nested case would - * result, except that the decoded instruction - */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } - } -#endif - /* know operation, decode the mod byte to find the addressing - mode. */ - amt = M.x86.R_CL; - switch (mod) { - case 0: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - break; - case 1: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - break; - case 2: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, amt); - *destreg = destval; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xd3 -****************************************************************************/ -void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - u8 amt; - - /* - * Yet another weirdo special case instruction format. Part of - * the opcode held below in "RH". Doubly nested case would - * result, except that the decoded instruction - */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } - } -#endif - /* know operation, decode the mod byte to find the addressing - mode. */ - amt = M.x86.R_CL; - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xd4 -****************************************************************************/ -void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) -{ - u8 a; - - START_OF_INSTR(); - DECODE_PRINTF("AAM\n"); - a = fetch_byte_imm(); /* this is a stupid encoding. */ - if (a != 10) { - DECODE_PRINTF("ERROR DECODING AAM\n"); - TRACE_REGS(); - HALT_SYS(); - } - TRACE_AND_STEP(); - /* note the type change here --- returning AL and AH in AX. */ - M.x86.R_AX = aam_word(M.x86.R_AL); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xd5 -****************************************************************************/ -void x86emuOp_aad(u8 X86EMU_UNUSED(op1)) -{ - u8 a; - - START_OF_INSTR(); - DECODE_PRINTF("AAD\n"); - a = fetch_byte_imm(); - TRACE_AND_STEP(); - M.x86.R_AX = aad_word(M.x86.R_AX); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/* opcode 0xd6 ILLEGAL OPCODE */ - -/**************************************************************************** -REMARKS: -Handles opcode 0xd7 -****************************************************************************/ -void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) -{ - u16 addr; - - START_OF_INSTR(); - DECODE_PRINTF("XLAT\n"); - TRACE_AND_STEP(); - addr = (u16)(M.x86.R_BX + (u8)M.x86.R_AL); - M.x86.R_AL = fetch_data_byte(addr); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/* instuctions D8 .. DF are in i87_ops.c */ - -/**************************************************************************** -REMARKS: -Handles opcode 0xe0 -****************************************************************************/ -void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) -{ - s16 ip; - - START_OF_INSTR(); - DECODE_PRINTF("LOOPNE\t"); - ip = (s8) fetch_byte_imm(); - ip += (s16) M.x86.R_IP; - DECODE_PRINTF2("%04x\n", ip); - TRACE_AND_STEP(); - M.x86.R_CX -= 1; - if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ - M.x86.R_IP = ip; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xe1 -****************************************************************************/ -void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) -{ - s16 ip; - - START_OF_INSTR(); - DECODE_PRINTF("LOOPE\t"); - ip = (s8) fetch_byte_imm(); - ip += (s16) M.x86.R_IP; - DECODE_PRINTF2("%04x\n", ip); - TRACE_AND_STEP(); - M.x86.R_CX -= 1; - if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ - M.x86.R_IP = ip; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xe2 -****************************************************************************/ -void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) -{ - s16 ip; - - START_OF_INSTR(); - DECODE_PRINTF("LOOP\t"); - ip = (s8) fetch_byte_imm(); - ip += (s16) M.x86.R_IP; - DECODE_PRINTF2("%04x\n", ip); - TRACE_AND_STEP(); - M.x86.R_CX -= 1; - if (M.x86.R_CX != 0) - M.x86.R_IP = ip; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xe3 -****************************************************************************/ -void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) -{ - u16 target; - s8 offset; - - /* jump to byte offset if overflow flag is set */ - START_OF_INSTR(); - DECODE_PRINTF("JCXZ\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - if (M.x86.R_CX == 0) - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xe4 -****************************************************************************/ -void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 port; - - START_OF_INSTR(); - DECODE_PRINTF("IN\t"); - port = (u8) fetch_byte_imm(); - DECODE_PRINTF2("%x,AL\n", port); - TRACE_AND_STEP(); - M.x86.R_AL = (*sys_inb)(port); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xe5 -****************************************************************************/ -void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) -{ - u8 port; - - START_OF_INSTR(); - DECODE_PRINTF("IN\t"); - port = (u8) fetch_byte_imm(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("EAX,%x\n", port); - } else { - DECODE_PRINTF2("AX,%x\n", port); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = (*sys_inl)(port); - } else { - M.x86.R_AX = (*sys_inw)(port); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xe6 -****************************************************************************/ -void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1)) -{ - u8 port; - - START_OF_INSTR(); - DECODE_PRINTF("OUT\t"); - port = (u8) fetch_byte_imm(); - DECODE_PRINTF2("%x,AL\n", port); - TRACE_AND_STEP(); - (*sys_outb)(port, M.x86.R_AL); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xe7 -****************************************************************************/ -void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) -{ - u8 port; - - START_OF_INSTR(); - DECODE_PRINTF("OUT\t"); - port = (u8) fetch_byte_imm(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("%x,EAX\n", port); - } else { - DECODE_PRINTF2("%x,AX\n", port); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - (*sys_outl)(port, M.x86.R_EAX); - } else { - (*sys_outw)(port, M.x86.R_AX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xe8 -****************************************************************************/ -void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) -{ - s16 ip; - - START_OF_INSTR(); - DECODE_PRINTF("CALL\t"); - ip = (s16) fetch_word_imm(); - ip += (s16) M.x86.R_IP; /* CHECK SIGN */ - DECODE_PRINTF2("%04x\n", ip); - CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, ""); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = ip; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xe9 -****************************************************************************/ -void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) -{ - int ip; - - START_OF_INSTR(); - DECODE_PRINTF("JMP\t"); - ip = (s16)fetch_word_imm(); - ip += (s16)M.x86.R_IP; - DECODE_PRINTF2("%04x\n", ip); - TRACE_AND_STEP(); - M.x86.R_IP = (u16)ip; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xea -****************************************************************************/ -void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) -{ - u16 cs, ip; - - START_OF_INSTR(); - DECODE_PRINTF("JMP\tFAR "); - ip = fetch_word_imm(); - cs = fetch_word_imm(); - DECODE_PRINTF2("%04x:", cs); - DECODE_PRINTF2("%04x\n", ip); - TRACE_AND_STEP(); - M.x86.R_IP = ip; - M.x86.R_CS = cs; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xeb -****************************************************************************/ -void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1)) -{ - u16 target; - s8 offset; - - START_OF_INSTR(); - DECODE_PRINTF("JMP\t"); - offset = (s8)fetch_byte_imm(); - target = (u16)(M.x86.R_IP + offset); - DECODE_PRINTF2("%x\n", target); - TRACE_AND_STEP(); - M.x86.R_IP = target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xec -****************************************************************************/ -void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("IN\tAL,DX\n"); - TRACE_AND_STEP(); - M.x86.R_AL = (*sys_inb)(M.x86.R_DX); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xed -****************************************************************************/ -void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("IN\tEAX,DX\n"); - } else { - DECODE_PRINTF("IN\tAX,DX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); - } else { - M.x86.R_AX = (*sys_inw)(M.x86.R_DX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xee -****************************************************************************/ -void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("OUT\tDX,AL\n"); - TRACE_AND_STEP(); - (*sys_outb)(M.x86.R_DX, M.x86.R_AL); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xef -****************************************************************************/ -void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("OUT\tDX,EAX\n"); - } else { - DECODE_PRINTF("OUT\tDX,AX\n"); - } - TRACE_AND_STEP(); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); - } else { - (*sys_outw)(M.x86.R_DX, M.x86.R_AX); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xf0 -****************************************************************************/ -void x86emuOp_lock(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("LOCK:\n"); - TRACE_AND_STEP(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/*opcode 0xf1 ILLEGAL OPERATION */ - -/**************************************************************************** -REMARKS: -Handles opcode 0xf2 -****************************************************************************/ -void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("REPNE\n"); - TRACE_AND_STEP(); - M.x86.mode |= SYSMODE_PREFIX_REPNE; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xf3 -****************************************************************************/ -void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("REPE\n"); - TRACE_AND_STEP(); - M.x86.mode |= SYSMODE_PREFIX_REPE; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xf4 -****************************************************************************/ -void x86emuOp_halt(u8 X86EMU_UNUSED(op1)) -{ - START_OF_INSTR(); - DECODE_PRINTF("HALT\n"); - TRACE_AND_STEP(); - HALT_SYS(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xf5 -****************************************************************************/ -void x86emuOp_cmc(u8 X86EMU_UNUSED(op1)) -{ - /* complement the carry flag. */ - START_OF_INSTR(); - DECODE_PRINTF("CMC\n"); - TRACE_AND_STEP(); - TOGGLE_FLAG(F_CF); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xf6 -****************************************************************************/ -void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - u8 *destreg; - uint destoffset; - u8 destval, srcval; - - /* long, drawn out code follows. Double switch for a total - of 32 cases. */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: /* mod=00 */ - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF("TEST\tBYTE PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - test_byte(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("NOT\tBYTE PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = not_byte(destval); - store_data_byte(destoffset, destval); - break; - case 3: - DECODE_PRINTF("NEG\tBYTE PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = neg_byte(destval); - store_data_byte(destoffset, destval); - break; - case 4: - DECODE_PRINTF("MUL\tBYTE PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - mul_byte(destval); - break; - case 5: - DECODE_PRINTF("IMUL\tBYTE PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - imul_byte(destval); - break; - case 6: - DECODE_PRINTF("DIV\tBYTE PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - div_byte(destval); - break; - case 7: - DECODE_PRINTF("IDIV\tBYTE PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - idiv_byte(destval); - break; - } - break; /* end mod==00 */ - case 1: /* mod=01 */ - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF("TEST\tBYTE PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - test_byte(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("NOT\tBYTE PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = not_byte(destval); - store_data_byte(destoffset, destval); - break; - case 3: - DECODE_PRINTF("NEG\tBYTE PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = neg_byte(destval); - store_data_byte(destoffset, destval); - break; - case 4: - DECODE_PRINTF("MUL\tBYTE PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - mul_byte(destval); - break; - case 5: - DECODE_PRINTF("IMUL\tBYTE PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - imul_byte(destval); - break; - case 6: - DECODE_PRINTF("DIV\tBYTE PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - div_byte(destval); - break; - case 7: - DECODE_PRINTF("IDIV\tBYTE PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - idiv_byte(destval); - break; - } - break; /* end mod==01 */ - case 2: /* mod=10 */ - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF("TEST\tBYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - test_byte(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("NOT\tBYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = not_byte(destval); - store_data_byte(destoffset, destval); - break; - case 3: - DECODE_PRINTF("NEG\tBYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = neg_byte(destval); - store_data_byte(destoffset, destval); - break; - case 4: - DECODE_PRINTF("MUL\tBYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - mul_byte(destval); - break; - case 5: - DECODE_PRINTF("IMUL\tBYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - imul_byte(destval); - break; - case 6: - DECODE_PRINTF("DIV\tBYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - div_byte(destval); - break; - case 7: - DECODE_PRINTF("IDIV\tBYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - idiv_byte(destval); - break; - } - break; /* end mod==10 */ - case 3: /* mod=11 */ - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF("TEST\t"); - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - TRACE_AND_STEP(); - test_byte(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("NOT\t"); - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_byte(*destreg); - break; - case 3: - DECODE_PRINTF("NEG\t"); - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_byte(*destreg); - break; - case 4: - DECODE_PRINTF("MUL\t"); - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_byte(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("IMUL\t"); - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_byte(*destreg); - break; - case 6: - DECODE_PRINTF("DIV\t"); - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_byte(*destreg); - break; - case 7: - DECODE_PRINTF("IDIV\t"); - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_byte(*destreg); - break; - } - break; /* end mod==11 */ - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xf7 -****************************************************************************/ -void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rl, rh; - uint destoffset; - - /* long, drawn out code follows. Double switch for a total - of 32 cases. */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: /* mod=00 */ - switch (rh) { - case 0: /* test word imm */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,srcval; - - DECODE_PRINTF("TEST\tDWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - test_long(destval, srcval); - } else { - u16 destval,srcval; - - DECODE_PRINTF("TEST\tWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - test_word(destval, srcval); - } - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); - HALT_SYS(); - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("NOT\tDWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = not_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("NOT\tWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = not_word(destval); - store_data_word(destoffset, destval); - } - break; - case 3: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("NEG\tDWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = neg_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("NEG\tWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = neg_word(destval); - store_data_word(destoffset, destval); - } - break; - case 4: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("MUL\tDWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - mul_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("MUL\tWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - mul_word(destval); - } - break; - case 5: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("IMUL\tDWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - imul_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("IMUL\tWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - imul_word(destval); - } - break; - case 6: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DIV\tDWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - div_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("DIV\tWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - div_word(destval); - } - break; - case 7: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("IDIV\tDWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - idiv_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("IDIV\tWORD PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - idiv_word(destval); - } - break; - } - break; /* end mod==00 */ - case 1: /* mod=01 */ - switch (rh) { - case 0: /* test word imm */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,srcval; - - DECODE_PRINTF("TEST\tDWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - test_long(destval, srcval); - } else { - u16 destval,srcval; - - DECODE_PRINTF("TEST\tWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - test_word(destval, srcval); - } - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("NOT\tDWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = not_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("NOT\tWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = not_word(destval); - store_data_word(destoffset, destval); - } - break; - case 3: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("NEG\tDWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = neg_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("NEG\tWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = neg_word(destval); - store_data_word(destoffset, destval); - } - break; - case 4: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("MUL\tDWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - mul_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("MUL\tWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - mul_word(destval); - } - break; - case 5: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("IMUL\tDWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - imul_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("IMUL\tWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - imul_word(destval); - } - break; - case 6: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DIV\tDWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - div_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("DIV\tWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - div_word(destval); - } - break; - case 7: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("IDIV\tDWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - idiv_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("IDIV\tWORD PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - idiv_word(destval); - } - break; - } - break; /* end mod==01 */ - case 2: /* mod=10 */ - switch (rh) { - case 0: /* test word imm */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,srcval; - - DECODE_PRINTF("TEST\tDWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - test_long(destval, srcval); - } else { - u16 destval,srcval; - - DECODE_PRINTF("TEST\tWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - test_word(destval, srcval); - } - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("NOT\tDWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = not_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("NOT\tWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = not_word(destval); - store_data_word(destoffset, destval); - } - break; - case 3: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("NEG\tDWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = neg_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("NEG\tWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = neg_word(destval); - store_data_word(destoffset, destval); - } - break; - case 4: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("MUL\tDWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - mul_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("MUL\tWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - mul_word(destval); - } - break; - case 5: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("IMUL\tDWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - imul_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("IMUL\tWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - imul_word(destval); - } - break; - case 6: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DIV\tDWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - div_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("DIV\tWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - div_word(destval); - } - break; - case 7: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("IDIV\tDWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - idiv_long(destval); - } else { - u16 destval; - - DECODE_PRINTF("IDIV\tWORD PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - idiv_word(destval); - } - break; - } - break; /* end mod==10 */ - case 3: /* mod=11 */ - switch (rh) { - case 0: /* test word imm */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - DECODE_PRINTF("TEST\t"); - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_long(*destreg, srcval); - } else { - u16 *destreg; - u16 srcval; - - DECODE_PRINTF("TEST\t"); - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_word(*destreg, srcval); - } - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - DECODE_PRINTF("NOT\t"); - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_long(*destreg); - } else { - u16 *destreg; - - DECODE_PRINTF("NOT\t"); - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_word(*destreg); - } - break; - case 3: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - DECODE_PRINTF("NEG\t"); - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_long(*destreg); - } else { - u16 *destreg; - - DECODE_PRINTF("NEG\t"); - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_word(*destreg); - } - break; - case 4: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - DECODE_PRINTF("MUL\t"); - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_long(*destreg); /*!!! */ - } else { - u16 *destreg; - - DECODE_PRINTF("MUL\t"); - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_word(*destreg); /*!!! */ - } - break; - case 5: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - DECODE_PRINTF("IMUL\t"); - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_long(*destreg); - } else { - u16 *destreg; - - DECODE_PRINTF("IMUL\t"); - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_word(*destreg); - } - break; - case 6: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - DECODE_PRINTF("DIV\t"); - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_long(*destreg); - } else { - u16 *destreg; - - DECODE_PRINTF("DIV\t"); - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_word(*destreg); - } - break; - case 7: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - DECODE_PRINTF("IDIV\t"); - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_long(*destreg); - } else { - u16 *destreg; - - DECODE_PRINTF("IDIV\t"); - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_word(*destreg); - } - break; - } - break; /* end mod==11 */ - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xf8 -****************************************************************************/ -void x86emuOp_clc(u8 X86EMU_UNUSED(op1)) -{ - /* clear the carry flag. */ - START_OF_INSTR(); - DECODE_PRINTF("CLC\n"); - TRACE_AND_STEP(); - CLEAR_FLAG(F_CF); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xf9 -****************************************************************************/ -void x86emuOp_stc(u8 X86EMU_UNUSED(op1)) -{ - /* set the carry flag. */ - START_OF_INSTR(); - DECODE_PRINTF("STC\n"); - TRACE_AND_STEP(); - SET_FLAG(F_CF); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xfa -****************************************************************************/ -void x86emuOp_cli(u8 X86EMU_UNUSED(op1)) -{ - /* clear interrupts. */ - START_OF_INSTR(); - DECODE_PRINTF("CLI\n"); - TRACE_AND_STEP(); - CLEAR_FLAG(F_IF); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xfb -****************************************************************************/ -void x86emuOp_sti(u8 X86EMU_UNUSED(op1)) -{ - /* enable interrupts. */ - START_OF_INSTR(); - DECODE_PRINTF("STI\n"); - TRACE_AND_STEP(); - SET_FLAG(F_IF); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xfc -****************************************************************************/ -void x86emuOp_cld(u8 X86EMU_UNUSED(op1)) -{ - /* clear interrupts. */ - START_OF_INSTR(); - DECODE_PRINTF("CLD\n"); - TRACE_AND_STEP(); - CLEAR_FLAG(F_DF); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xfd -****************************************************************************/ -void x86emuOp_std(u8 X86EMU_UNUSED(op1)) -{ - /* clear interrupts. */ - START_OF_INSTR(); - DECODE_PRINTF("STD\n"); - TRACE_AND_STEP(); - SET_FLAG(F_DF); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xfe -****************************************************************************/ -void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rh, rl; - u8 destval; - uint destoffset; - u8 *destreg; - - /* Yet another special case instruction. */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("INC\t"); - break; - case 1: - DECODE_PRINTF("DEC\t"); - break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); - HALT_SYS(); - break; - } - } -#endif - switch (mod) { - case 0: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - switch (rh) { - case 0: /* inc word ptr ... */ - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = inc_byte(destval); - store_data_byte(destoffset, destval); - break; - case 1: /* dec word ptr ... */ - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = dec_byte(destval); - store_data_byte(destoffset, destval); - break; - } - break; - case 1: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - switch (rh) { - case 0: - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = inc_byte(destval); - store_data_byte(destoffset, destval); - break; - case 1: - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = dec_byte(destval); - store_data_byte(destoffset, destval); - break; - } - break; - case 2: - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - switch (rh) { - case 0: - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = inc_byte(destval); - store_data_byte(destoffset, destval); - break; - case 1: - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = dec_byte(destval); - store_data_byte(destoffset, destval); - break; - } - break; - case 3: - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - switch (rh) { - case 0: - TRACE_AND_STEP(); - *destreg = inc_byte(*destreg); - break; - case 1: - TRACE_AND_STEP(); - *destreg = dec_byte(*destreg); - break; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0xff -****************************************************************************/ -void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) -{ - int mod, rh, rl; - uint destoffset = 0; - u16 *destreg; - u16 destval,destval2; - - /* Yet another special case instruction. */ - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG - if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tDWORD PTR "); - } else { - DECODE_PRINTF("INC\tWORD PTR "); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tDWORD PTR "); - } else { - DECODE_PRINTF("DEC\tWORD PTR "); - } - break; - case 2: - DECODE_PRINTF("CALL\t "); - break; - case 3: - DECODE_PRINTF("CALL\tFAR "); - break; - case 4: - DECODE_PRINTF("JMP\t"); - break; - case 5: - DECODE_PRINTF("JMP\tFAR "); - break; - case 6: - DECODE_PRINTF("PUSH\t"); - break; - case 7: - DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); - HALT_SYS(); - break; - } - } -#endif - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - switch (rh) { - case 0: /* inc word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = inc_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = inc_word(destval); - store_data_word(destoffset, destval); - } - break; - case 1: /* dec word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = dec_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = dec_word(destval); - store_data_word(destoffset, destval); - } - break; - case 2: /* call word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 3: /* call far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - M.x86.R_CS = destval2; - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 4: /* jmp word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - break; - case 5: /* jmp far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - M.x86.R_CS = destval2; - break; - case 6: /* push word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - push_long(destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(destval); - } - break; - } - break; - case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = inc_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = inc_word(destval); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = dec_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = dec_word(destval); - store_data_word(destoffset, destval); - } - break; - case 2: /* call word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 3: /* call far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - M.x86.R_CS = destval2; - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 4: /* jmp word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - break; - case 5: /* jmp far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - M.x86.R_CS = destval2; - break; - case 6: /* push word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - push_long(destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(destval); - } - break; - } - break; - case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = inc_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = inc_word(destval); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = dec_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = dec_word(destval); - store_data_word(destoffset, destval); - } - break; - case 2: /* call word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 3: /* call far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - M.x86.R_CS = destval2; - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 4: /* jmp word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - break; - case 5: /* jmp far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - M.x86.R_CS = destval2; - break; - case 6: /* push word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - push_long(destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(destval); - } - break; - } - break; - case 3: - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = inc_long(*destreg); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = inc_word(*destreg); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = dec_long(*destreg); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = dec_word(*destreg); - } - break; - case 2: /* call word ptr ... */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = *destreg; - break; - case 3: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); - TRACE_AND_STEP(); - HALT_SYS(); - break; - - case 4: /* jmp ... */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - M.x86.R_IP = (u16) (*destreg); - break; - case 5: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); - TRACE_AND_STEP(); - HALT_SYS(); - break; - case 6: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_long(*destreg); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(*destreg); - } - break; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/*************************************************************************** - * Single byte operation code table: - **************************************************************************/ -void (*x86emu_optab[256])(u8) = -{ -/* 0x00 */ x86emuOp_add_byte_RM_R, -/* 0x01 */ x86emuOp_add_word_RM_R, -/* 0x02 */ x86emuOp_add_byte_R_RM, -/* 0x03 */ x86emuOp_add_word_R_RM, -/* 0x04 */ x86emuOp_add_byte_AL_IMM, -/* 0x05 */ x86emuOp_add_word_AX_IMM, -/* 0x06 */ x86emuOp_push_ES, -/* 0x07 */ x86emuOp_pop_ES, - -/* 0x08 */ x86emuOp_or_byte_RM_R, -/* 0x09 */ x86emuOp_or_word_RM_R, -/* 0x0a */ x86emuOp_or_byte_R_RM, -/* 0x0b */ x86emuOp_or_word_R_RM, -/* 0x0c */ x86emuOp_or_byte_AL_IMM, -/* 0x0d */ x86emuOp_or_word_AX_IMM, -/* 0x0e */ x86emuOp_push_CS, -/* 0x0f */ x86emuOp_two_byte, - -/* 0x10 */ x86emuOp_adc_byte_RM_R, -/* 0x11 */ x86emuOp_adc_word_RM_R, -/* 0x12 */ x86emuOp_adc_byte_R_RM, -/* 0x13 */ x86emuOp_adc_word_R_RM, -/* 0x14 */ x86emuOp_adc_byte_AL_IMM, -/* 0x15 */ x86emuOp_adc_word_AX_IMM, -/* 0x16 */ x86emuOp_push_SS, -/* 0x17 */ x86emuOp_pop_SS, - -/* 0x18 */ x86emuOp_sbb_byte_RM_R, -/* 0x19 */ x86emuOp_sbb_word_RM_R, -/* 0x1a */ x86emuOp_sbb_byte_R_RM, -/* 0x1b */ x86emuOp_sbb_word_R_RM, -/* 0x1c */ x86emuOp_sbb_byte_AL_IMM, -/* 0x1d */ x86emuOp_sbb_word_AX_IMM, -/* 0x1e */ x86emuOp_push_DS, -/* 0x1f */ x86emuOp_pop_DS, - -/* 0x20 */ x86emuOp_and_byte_RM_R, -/* 0x21 */ x86emuOp_and_word_RM_R, -/* 0x22 */ x86emuOp_and_byte_R_RM, -/* 0x23 */ x86emuOp_and_word_R_RM, -/* 0x24 */ x86emuOp_and_byte_AL_IMM, -/* 0x25 */ x86emuOp_and_word_AX_IMM, -/* 0x26 */ x86emuOp_segovr_ES, -/* 0x27 */ x86emuOp_daa, - -/* 0x28 */ x86emuOp_sub_byte_RM_R, -/* 0x29 */ x86emuOp_sub_word_RM_R, -/* 0x2a */ x86emuOp_sub_byte_R_RM, -/* 0x2b */ x86emuOp_sub_word_R_RM, -/* 0x2c */ x86emuOp_sub_byte_AL_IMM, -/* 0x2d */ x86emuOp_sub_word_AX_IMM, -/* 0x2e */ x86emuOp_segovr_CS, -/* 0x2f */ x86emuOp_das, - -/* 0x30 */ x86emuOp_xor_byte_RM_R, -/* 0x31 */ x86emuOp_xor_word_RM_R, -/* 0x32 */ x86emuOp_xor_byte_R_RM, -/* 0x33 */ x86emuOp_xor_word_R_RM, -/* 0x34 */ x86emuOp_xor_byte_AL_IMM, -/* 0x35 */ x86emuOp_xor_word_AX_IMM, -/* 0x36 */ x86emuOp_segovr_SS, -/* 0x37 */ x86emuOp_aaa, - -/* 0x38 */ x86emuOp_cmp_byte_RM_R, -/* 0x39 */ x86emuOp_cmp_word_RM_R, -/* 0x3a */ x86emuOp_cmp_byte_R_RM, -/* 0x3b */ x86emuOp_cmp_word_R_RM, -/* 0x3c */ x86emuOp_cmp_byte_AL_IMM, -/* 0x3d */ x86emuOp_cmp_word_AX_IMM, -/* 0x3e */ x86emuOp_segovr_DS, -/* 0x3f */ x86emuOp_aas, - -/* 0x40 */ x86emuOp_inc_AX, -/* 0x41 */ x86emuOp_inc_CX, -/* 0x42 */ x86emuOp_inc_DX, -/* 0x43 */ x86emuOp_inc_BX, -/* 0x44 */ x86emuOp_inc_SP, -/* 0x45 */ x86emuOp_inc_BP, -/* 0x46 */ x86emuOp_inc_SI, -/* 0x47 */ x86emuOp_inc_DI, - -/* 0x48 */ x86emuOp_dec_AX, -/* 0x49 */ x86emuOp_dec_CX, -/* 0x4a */ x86emuOp_dec_DX, -/* 0x4b */ x86emuOp_dec_BX, -/* 0x4c */ x86emuOp_dec_SP, -/* 0x4d */ x86emuOp_dec_BP, -/* 0x4e */ x86emuOp_dec_SI, -/* 0x4f */ x86emuOp_dec_DI, - -/* 0x50 */ x86emuOp_push_AX, -/* 0x51 */ x86emuOp_push_CX, -/* 0x52 */ x86emuOp_push_DX, -/* 0x53 */ x86emuOp_push_BX, -/* 0x54 */ x86emuOp_push_SP, -/* 0x55 */ x86emuOp_push_BP, -/* 0x56 */ x86emuOp_push_SI, -/* 0x57 */ x86emuOp_push_DI, - -/* 0x58 */ x86emuOp_pop_AX, -/* 0x59 */ x86emuOp_pop_CX, -/* 0x5a */ x86emuOp_pop_DX, -/* 0x5b */ x86emuOp_pop_BX, -/* 0x5c */ x86emuOp_pop_SP, -/* 0x5d */ x86emuOp_pop_BP, -/* 0x5e */ x86emuOp_pop_SI, -/* 0x5f */ x86emuOp_pop_DI, - -/* 0x60 */ x86emuOp_push_all, -/* 0x61 */ x86emuOp_pop_all, -/* 0x62 */ x86emuOp_illegal_op, /* bound */ -/* 0x63 */ x86emuOp_illegal_op, /* arpl */ -/* 0x64 */ x86emuOp_segovr_FS, -/* 0x65 */ x86emuOp_segovr_GS, -/* 0x66 */ x86emuOp_prefix_data, -/* 0x67 */ x86emuOp_prefix_addr, - -/* 0x68 */ x86emuOp_push_word_IMM, -/* 0x69 */ x86emuOp_imul_word_IMM, -/* 0x6a */ x86emuOp_push_byte_IMM, -/* 0x6b */ x86emuOp_imul_byte_IMM, -/* 0x6c */ x86emuOp_ins_byte, -/* 0x6d */ x86emuOp_ins_word, -/* 0x6e */ x86emuOp_outs_byte, -/* 0x6f */ x86emuOp_outs_word, - -/* 0x70 */ x86emuOp_jump_near_O, -/* 0x71 */ x86emuOp_jump_near_NO, -/* 0x72 */ x86emuOp_jump_near_B, -/* 0x73 */ x86emuOp_jump_near_NB, -/* 0x74 */ x86emuOp_jump_near_Z, -/* 0x75 */ x86emuOp_jump_near_NZ, -/* 0x76 */ x86emuOp_jump_near_BE, -/* 0x77 */ x86emuOp_jump_near_NBE, - -/* 0x78 */ x86emuOp_jump_near_S, -/* 0x79 */ x86emuOp_jump_near_NS, -/* 0x7a */ x86emuOp_jump_near_P, -/* 0x7b */ x86emuOp_jump_near_NP, -/* 0x7c */ x86emuOp_jump_near_L, -/* 0x7d */ x86emuOp_jump_near_NL, -/* 0x7e */ x86emuOp_jump_near_LE, -/* 0x7f */ x86emuOp_jump_near_NLE, - -/* 0x80 */ x86emuOp_opc80_byte_RM_IMM, -/* 0x81 */ x86emuOp_opc81_word_RM_IMM, -/* 0x82 */ x86emuOp_opc82_byte_RM_IMM, -/* 0x83 */ x86emuOp_opc83_word_RM_IMM, -/* 0x84 */ x86emuOp_test_byte_RM_R, -/* 0x85 */ x86emuOp_test_word_RM_R, -/* 0x86 */ x86emuOp_xchg_byte_RM_R, -/* 0x87 */ x86emuOp_xchg_word_RM_R, - -/* 0x88 */ x86emuOp_mov_byte_RM_R, -/* 0x89 */ x86emuOp_mov_word_RM_R, -/* 0x8a */ x86emuOp_mov_byte_R_RM, -/* 0x8b */ x86emuOp_mov_word_R_RM, -/* 0x8c */ x86emuOp_mov_word_RM_SR, -/* 0x8d */ x86emuOp_lea_word_R_M, -/* 0x8e */ x86emuOp_mov_word_SR_RM, -/* 0x8f */ x86emuOp_pop_RM, - -/* 0x90 */ x86emuOp_nop, -/* 0x91 */ x86emuOp_xchg_word_AX_CX, -/* 0x92 */ x86emuOp_xchg_word_AX_DX, -/* 0x93 */ x86emuOp_xchg_word_AX_BX, -/* 0x94 */ x86emuOp_xchg_word_AX_SP, -/* 0x95 */ x86emuOp_xchg_word_AX_BP, -/* 0x96 */ x86emuOp_xchg_word_AX_SI, -/* 0x97 */ x86emuOp_xchg_word_AX_DI, - -/* 0x98 */ x86emuOp_cbw, -/* 0x99 */ x86emuOp_cwd, -/* 0x9a */ x86emuOp_call_far_IMM, -/* 0x9b */ x86emuOp_wait, -/* 0x9c */ x86emuOp_pushf_word, -/* 0x9d */ x86emuOp_popf_word, -/* 0x9e */ x86emuOp_sahf, -/* 0x9f */ x86emuOp_lahf, - -/* 0xa0 */ x86emuOp_mov_AL_M_IMM, -/* 0xa1 */ x86emuOp_mov_AX_M_IMM, -/* 0xa2 */ x86emuOp_mov_M_AL_IMM, -/* 0xa3 */ x86emuOp_mov_M_AX_IMM, -/* 0xa4 */ x86emuOp_movs_byte, -/* 0xa5 */ x86emuOp_movs_word, -/* 0xa6 */ x86emuOp_cmps_byte, -/* 0xa7 */ x86emuOp_cmps_word, -/* 0xa8 */ x86emuOp_test_AL_IMM, -/* 0xa9 */ x86emuOp_test_AX_IMM, -/* 0xaa */ x86emuOp_stos_byte, -/* 0xab */ x86emuOp_stos_word, -/* 0xac */ x86emuOp_lods_byte, -/* 0xad */ x86emuOp_lods_word, -/* 0xac */ x86emuOp_scas_byte, -/* 0xad */ x86emuOp_scas_word, - - -/* 0xb0 */ x86emuOp_mov_byte_AL_IMM, -/* 0xb1 */ x86emuOp_mov_byte_CL_IMM, -/* 0xb2 */ x86emuOp_mov_byte_DL_IMM, -/* 0xb3 */ x86emuOp_mov_byte_BL_IMM, -/* 0xb4 */ x86emuOp_mov_byte_AH_IMM, -/* 0xb5 */ x86emuOp_mov_byte_CH_IMM, -/* 0xb6 */ x86emuOp_mov_byte_DH_IMM, -/* 0xb7 */ x86emuOp_mov_byte_BH_IMM, - -/* 0xb8 */ x86emuOp_mov_word_AX_IMM, -/* 0xb9 */ x86emuOp_mov_word_CX_IMM, -/* 0xba */ x86emuOp_mov_word_DX_IMM, -/* 0xbb */ x86emuOp_mov_word_BX_IMM, -/* 0xbc */ x86emuOp_mov_word_SP_IMM, -/* 0xbd */ x86emuOp_mov_word_BP_IMM, -/* 0xbe */ x86emuOp_mov_word_SI_IMM, -/* 0xbf */ x86emuOp_mov_word_DI_IMM, - -/* 0xc0 */ x86emuOp_opcC0_byte_RM_MEM, -/* 0xc1 */ x86emuOp_opcC1_word_RM_MEM, -/* 0xc2 */ x86emuOp_ret_near_IMM, -/* 0xc3 */ x86emuOp_ret_near, -/* 0xc4 */ x86emuOp_les_R_IMM, -/* 0xc5 */ x86emuOp_lds_R_IMM, -/* 0xc6 */ x86emuOp_mov_byte_RM_IMM, -/* 0xc7 */ x86emuOp_mov_word_RM_IMM, -/* 0xc8 */ x86emuOp_enter, -/* 0xc9 */ x86emuOp_leave, -/* 0xca */ x86emuOp_ret_far_IMM, -/* 0xcb */ x86emuOp_ret_far, -/* 0xcc */ x86emuOp_int3, -/* 0xcd */ x86emuOp_int_IMM, -/* 0xce */ x86emuOp_into, -/* 0xcf */ x86emuOp_iret, - -/* 0xd0 */ x86emuOp_opcD0_byte_RM_1, -/* 0xd1 */ x86emuOp_opcD1_word_RM_1, -/* 0xd2 */ x86emuOp_opcD2_byte_RM_CL, -/* 0xd3 */ x86emuOp_opcD3_word_RM_CL, -/* 0xd4 */ x86emuOp_aam, -/* 0xd5 */ x86emuOp_aad, -/* 0xd6 */ x86emuOp_illegal_op, /* Undocumented SETALC instruction */ -/* 0xd7 */ x86emuOp_xlat, -/* 0xd8 */ x86emuOp_esc_coprocess_d8, -/* 0xd9 */ x86emuOp_esc_coprocess_d9, -/* 0xda */ x86emuOp_esc_coprocess_da, -/* 0xdb */ x86emuOp_esc_coprocess_db, -/* 0xdc */ x86emuOp_esc_coprocess_dc, -/* 0xdd */ x86emuOp_esc_coprocess_dd, -/* 0xde */ x86emuOp_esc_coprocess_de, -/* 0xdf */ x86emuOp_esc_coprocess_df, - -/* 0xe0 */ x86emuOp_loopne, -/* 0xe1 */ x86emuOp_loope, -/* 0xe2 */ x86emuOp_loop, -/* 0xe3 */ x86emuOp_jcxz, -/* 0xe4 */ x86emuOp_in_byte_AL_IMM, -/* 0xe5 */ x86emuOp_in_word_AX_IMM, -/* 0xe6 */ x86emuOp_out_byte_IMM_AL, -/* 0xe7 */ x86emuOp_out_word_IMM_AX, - -/* 0xe8 */ x86emuOp_call_near_IMM, -/* 0xe9 */ x86emuOp_jump_near_IMM, -/* 0xea */ x86emuOp_jump_far_IMM, -/* 0xeb */ x86emuOp_jump_byte_IMM, -/* 0xec */ x86emuOp_in_byte_AL_DX, -/* 0xed */ x86emuOp_in_word_AX_DX, -/* 0xee */ x86emuOp_out_byte_DX_AL, -/* 0xef */ x86emuOp_out_word_DX_AX, - -/* 0xf0 */ x86emuOp_lock, -/* 0xf1 */ x86emuOp_illegal_op, -/* 0xf2 */ x86emuOp_repne, -/* 0xf3 */ x86emuOp_repe, -/* 0xf4 */ x86emuOp_halt, -/* 0xf5 */ x86emuOp_cmc, -/* 0xf6 */ x86emuOp_opcF6_byte_RM, -/* 0xf7 */ x86emuOp_opcF7_word_RM, - -/* 0xf8 */ x86emuOp_clc, -/* 0xf9 */ x86emuOp_stc, -/* 0xfa */ x86emuOp_cli, -/* 0xfb */ x86emuOp_sti, -/* 0xfc */ x86emuOp_cld, -/* 0xfd */ x86emuOp_std, -/* 0xfe */ x86emuOp_opcFE_byte_RM, -/* 0xff */ x86emuOp_opcFF_word_RM, -}; - -void tables_relocate(unsigned int offset) -{ - int i; - for (i=0; i<8; i++) - { - opc80_byte_operation[i] -= offset; - opc81_word_operation[i] -= offset; - opc81_long_operation[i] -= offset; - - opc82_byte_operation[i] -= offset; - opc83_word_operation[i] -= offset; - opc83_long_operation[i] -= offset; - - opcD0_byte_operation[i] -= offset; - opcD1_word_operation[i] -= offset; - opcD1_long_operation[i] -= offset; - } -} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c b/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c deleted file mode 100644 index d381307..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c +++ /dev/null @@ -1,2800 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: This file includes subroutines to implement the decoding -* and emulation of all the x86 extended two-byte processor -* instructions. -* -****************************************************************************/ - -#include "x86emu/x86emui.h" - -/*----------------------------- Implementation ----------------------------*/ - -/**************************************************************************** -PARAMETERS: -op1 - Instruction op code - -REMARKS: -Handles illegal opcodes. -****************************************************************************/ -void x86emuOp2_illegal_op( - u8 op2) -{ - START_OF_INSTR(); - DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); - TRACE_REGS(); - printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-2,op2); - HALT_SYS(); - END_OF_INSTR(); -} - -#define xorl(a,b) ((a) && !(b)) || (!(a) && (b)) - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0x80-0x8F -****************************************************************************/ -void x86emuOp2_long_jump(u8 op2) -{ - s32 target; - char *name = 0; - int cond = 0; - - /* conditional jump to word offset. */ - START_OF_INSTR(); - switch (op2) { - case 0x80: - name = "JO\t"; - cond = ACCESS_FLAG(F_OF); - break; - case 0x81: - name = "JNO\t"; - cond = !ACCESS_FLAG(F_OF); - break; - case 0x82: - name = "JB\t"; - cond = ACCESS_FLAG(F_CF); - break; - case 0x83: - name = "JNB\t"; - cond = !ACCESS_FLAG(F_CF); - break; - case 0x84: - name = "JZ\t"; - cond = ACCESS_FLAG(F_ZF); - break; - case 0x85: - name = "JNZ\t"; - cond = !ACCESS_FLAG(F_ZF); - break; - case 0x86: - name = "JBE\t"; - cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); - break; - case 0x87: - name = "JNBE\t"; - cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); - break; - case 0x88: - name = "JS\t"; - cond = ACCESS_FLAG(F_SF); - break; - case 0x89: - name = "JNS\t"; - cond = !ACCESS_FLAG(F_SF); - break; - case 0x8a: - name = "JP\t"; - cond = ACCESS_FLAG(F_PF); - break; - case 0x8b: - name = "JNP\t"; - cond = !ACCESS_FLAG(F_PF); - break; - case 0x8c: - name = "JL\t"; - cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; - case 0x8d: - name = "JNL\t"; - cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; - case 0x8e: - name = "JLE\t"; - cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; - case 0x8f: - name = "JNLE\t"; - cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; - } - DECODE_PRINTF(name); - target = (s16) fetch_word_imm(); - target += (s16) M.x86.R_IP; - DECODE_PRINTF2("%04x\n", target); - TRACE_AND_STEP(); - if (cond) - M.x86.R_IP = (u16)target; - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0x90-0x9F -****************************************************************************/ -void x86emuOp2_set_byte(u8 op2) -{ - int mod, rl, rh; - uint destoffset; - u8 *destreg; - char *name = 0; - int cond = 0; - - START_OF_INSTR(); - switch (op2) { - case 0x90: - name = "SETO\t"; - cond = ACCESS_FLAG(F_OF); - break; - case 0x91: - name = "SETNO\t"; - cond = !ACCESS_FLAG(F_OF); - break; - case 0x92: - name = "SETB\t"; - cond = ACCESS_FLAG(F_CF); - break; - case 0x93: - name = "SETNB\t"; - cond = !ACCESS_FLAG(F_CF); - break; - case 0x94: - name = "SETZ\t"; - cond = ACCESS_FLAG(F_ZF); - break; - case 0x95: - name = "SETNZ\t"; - cond = !ACCESS_FLAG(F_ZF); - break; - case 0x96: - name = "SETBE\t"; - cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); - break; - case 0x97: - name = "SETNBE\t"; - cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); - break; - case 0x98: - name = "SETS\t"; - cond = ACCESS_FLAG(F_SF); - break; - case 0x99: - name = "SETNS\t"; - cond = !ACCESS_FLAG(F_SF); - break; - case 0x9a: - name = "SETP\t"; - cond = ACCESS_FLAG(F_PF); - break; - case 0x9b: - name = "SETNP\t"; - cond = !ACCESS_FLAG(F_PF); - break; - case 0x9c: - name = "SETL\t"; - cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; - case 0x9d: - name = "SETNL\t"; - cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; - case 0x9e: - name = "SETLE\t"; - cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; - case 0x9f: - name = "SETNLE\t"; - cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; - } - DECODE_PRINTF(name); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destoffset = decode_rm00_address(rl); - TRACE_AND_STEP(); - store_data_byte(destoffset, cond ? 0x01 : 0x00); - break; - case 1: - destoffset = decode_rm01_address(rl); - TRACE_AND_STEP(); - store_data_byte(destoffset, cond ? 0x01 : 0x00); - break; - case 2: - destoffset = decode_rm10_address(rl); - TRACE_AND_STEP(); - store_data_byte(destoffset, cond ? 0x01 : 0x00); - break; - case 3: /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - TRACE_AND_STEP(); - *destreg = cond ? 0x01 : 0x00; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xa0 -****************************************************************************/ -void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2)) -{ - START_OF_INSTR(); - DECODE_PRINTF("PUSH\tFS\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_FS); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xa1 -****************************************************************************/ -void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2)) -{ - START_OF_INSTR(); - DECODE_PRINTF("POP\tFS\n"); - TRACE_AND_STEP(); - M.x86.R_FS = pop_word(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xa3 -****************************************************************************/ -void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - int bit,disp; - - START_OF_INSTR(); - DECODE_PRINTF("BT\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval; - u32 *shiftreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } else { - u16 srcval; - u16 *shiftreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval; - u32 *shiftreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } else { - u16 srcval; - u16 *shiftreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval; - u32 *shiftreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } else { - u16 srcval; - u16 *shiftreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); - } else { - u16 *srcreg,*shiftreg; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xa4 -****************************************************************************/ -void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint destoffset; - u8 shift; - - START_OF_INSTR(); - DECODE_PRINTF("SHLD\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shld_long(*destreg,*shiftreg,shift); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shld_word(*destreg,*shiftreg,shift); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xa5 -****************************************************************************/ -void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("SHLD\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xa8 -****************************************************************************/ -void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2)) -{ - START_OF_INSTR(); - DECODE_PRINTF("PUSH\tGS\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_GS); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xa9 -****************************************************************************/ -void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2)) -{ - START_OF_INSTR(); - DECODE_PRINTF("POP\tGS\n"); - TRACE_AND_STEP(); - M.x86.R_GS = pop_word(); - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xaa -****************************************************************************/ -void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - int bit,disp; - - START_OF_INSTR(); - DECODE_PRINTF("BTS\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval | mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, srcval | mask); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval | mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, srcval | mask); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval | mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, srcval | mask); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg |= mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg |= mask; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xac -****************************************************************************/ -void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint destoffset; - u8 shift; - - START_OF_INSTR(); - DECODE_PRINTF("SHLD\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shrd_long(*destreg,*shiftreg,shift); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shrd_word(*destreg,*shiftreg,shift); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xad -****************************************************************************/ -void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint destoffset; - - START_OF_INSTR(); - DECODE_PRINTF("SHLD\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - destoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xaf -****************************************************************************/ -void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("IMUL\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_long(srcoffset); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - TRACE_AND_STEP(); - res = (s16)*destreg * (s16)srcval; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_long(srcoffset); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - TRACE_AND_STEP(); - res = (s16)*destreg * (s16)srcval; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_long(srcoffset); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - TRACE_AND_STEP(); - res = (s16)*destreg * (s16)srcval; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - res = (s16)*destreg * (s16)*srcreg; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xb2 -****************************************************************************/ -void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) -{ - int mod, rh, rl; - u16 *dstreg; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("LSS\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_SS = fetch_data_word(srcoffset + 2); - break; - case 1: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_SS = fetch_data_word(srcoffset + 2); - break; - case 2: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_SS = fetch_data_word(srcoffset + 2); - break; - case 3: /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xb3 -****************************************************************************/ -void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - int bit,disp; - - START_OF_INSTR(); - DECODE_PRINTF("BTR\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval & ~mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval & ~mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval & ~mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg &= ~mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg &= ~mask; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xb4 -****************************************************************************/ -void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) -{ - int mod, rh, rl; - u16 *dstreg; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("LFS\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_FS = fetch_data_word(srcoffset + 2); - break; - case 1: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_FS = fetch_data_word(srcoffset + 2); - break; - case 2: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_FS = fetch_data_word(srcoffset + 2); - break; - case 3: /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xb5 -****************************************************************************/ -void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) -{ - int mod, rh, rl; - u16 *dstreg; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("LGS\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_GS = fetch_data_word(srcoffset + 2); - break; - case 1: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_GS = fetch_data_word(srcoffset + 2); - break; - case 2: - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_GS = fetch_data_word(srcoffset + 2); - break; - case 3: /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xb6 -****************************************************************************/ -void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("MOVZX\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xb7 -****************************************************************************/ -void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - u32 *destreg; - u32 srcval; - u16 *srcreg; - - START_OF_INSTR(); - DECODE_PRINTF("MOVZX\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 1: - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 2: - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 3: /* register to register */ - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xba -****************************************************************************/ -void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - int bit; - - START_OF_INSTR(); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (rh) { - case 3: - DECODE_PRINTF("BT\t"); - break; - case 4: - DECODE_PRINTF("BTS\t"); - break; - case 5: - DECODE_PRINTF("BTR\t"); - break; - case 6: - DECODE_PRINTF("BTC\t"); - break; - default: - DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); - TRACE_REGS(); - printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", - M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); - HALT_SYS(); - } - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, mask; - u8 shift; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - TRACE_AND_STEP(); - bit = shift & 0x1F; - srcval = fetch_data_long(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 4: - store_data_long(srcoffset, srcval | mask); - break; - case 5: - store_data_long(srcoffset, srcval & ~mask); - break; - case 6: - store_data_long(srcoffset, srcval ^ mask); - break; - default: - break; - } - } else { - u16 srcval, mask; - u8 shift; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - TRACE_AND_STEP(); - bit = shift & 0xF; - srcval = fetch_data_word(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 4: - store_data_word(srcoffset, srcval | mask); - break; - case 5: - store_data_word(srcoffset, srcval & ~mask); - break; - case 6: - store_data_word(srcoffset, srcval ^ mask); - break; - default: - break; - } - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, mask; - u8 shift; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - TRACE_AND_STEP(); - bit = shift & 0x1F; - srcval = fetch_data_long(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 4: - store_data_long(srcoffset, srcval | mask); - break; - case 5: - store_data_long(srcoffset, srcval & ~mask); - break; - case 6: - store_data_long(srcoffset, srcval ^ mask); - break; - default: - break; - } - } else { - u16 srcval, mask; - u8 shift; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - TRACE_AND_STEP(); - bit = shift & 0xF; - srcval = fetch_data_word(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 4: - store_data_word(srcoffset, srcval | mask); - break; - case 5: - store_data_word(srcoffset, srcval & ~mask); - break; - case 6: - store_data_word(srcoffset, srcval ^ mask); - break; - default: - break; - } - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, mask; - u8 shift; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - TRACE_AND_STEP(); - bit = shift & 0x1F; - srcval = fetch_data_long(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 4: - store_data_long(srcoffset, srcval | mask); - break; - case 5: - store_data_long(srcoffset, srcval & ~mask); - break; - case 6: - store_data_long(srcoffset, srcval ^ mask); - break; - default: - break; - } - } else { - u16 srcval, mask; - u8 shift; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - TRACE_AND_STEP(); - bit = shift & 0xF; - srcval = fetch_data_word(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 4: - store_data_word(srcoffset, srcval | mask); - break; - case 5: - store_data_word(srcoffset, srcval & ~mask); - break; - case 6: - store_data_word(srcoffset, srcval ^ mask); - break; - default: - break; - } - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - u32 mask; - u8 shift; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - TRACE_AND_STEP(); - bit = shift & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - switch (rh) { - case 4: - *srcreg |= mask; - break; - case 5: - *srcreg &= ~mask; - break; - case 6: - *srcreg ^= mask; - break; - default: - break; - } - } else { - u16 *srcreg; - u16 mask; - u8 shift; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - TRACE_AND_STEP(); - bit = shift & 0xF; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - switch (rh) { - case 4: - *srcreg |= mask; - break; - case 5: - *srcreg &= ~mask; - break; - case 6: - *srcreg ^= mask; - break; - default: - break; - } - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xbb -****************************************************************************/ -void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - int bit,disp; - - START_OF_INSTR(); - DECODE_PRINTF("BTC\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval ^ mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval ^ mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval ^ mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg ^= mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg ^= mask; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xbc -****************************************************************************/ -void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("BSF\n"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch(mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg, *dstreg; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) - if ((*srcreg >> *dstreg) & 1) break; - } else { - u16 *srcreg, *dstreg; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) - if ((*srcreg >> *dstreg) & 1) break; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xbd -****************************************************************************/ -void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("BSF\n"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch(mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - srcoffset = decode_rm00_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - srcoffset = decode_rm01_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - srcoffset = decode_rm10_address(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg, *dstreg; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) - if ((*srcreg >> *dstreg) & 1) break; - } else { - u16 *srcreg, *dstreg; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) - if ((*srcreg >> *dstreg) & 1) break; - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xbe -****************************************************************************/ -void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - - START_OF_INSTR(); - DECODE_PRINTF("MOVSX\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = (s32)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = (s16)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = (s32)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = (s16)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - break; - case 2: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = (s32)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = (s16)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - break; - case 3: /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s32)((s8)*srcreg); - } else { - u16 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s16)((s8)*srcreg); - } - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/**************************************************************************** -REMARKS: -Handles opcode 0x0f,0xbf -****************************************************************************/ -void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) -{ - int mod, rl, rh; - uint srcoffset; - u32 *destreg; - u32 srcval; - u16 *srcreg; - - START_OF_INSTR(); - DECODE_PRINTF("MOVSX\t"); - FETCH_DECODE_MODRM(mod, rh, rl); - switch (mod) { - case 0: - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm00_address(rl); - srcval = (s32)((s16)fetch_data_word(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 1: - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm01_address(rl); - srcval = (s32)((s16)fetch_data_word(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 2: - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rm10_address(rl); - srcval = (s32)((s16)fetch_data_word(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - break; - case 3: /* register to register */ - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s32)((s16)*srcreg); - break; - } - DECODE_CLEAR_SEGOVR(); - END_OF_INSTR(); -} - -/*************************************************************************** - * Double byte operation code table: - **************************************************************************/ -void (*x86emu_optab2[256])(u8) = -{ -/* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ -/* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ -/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ -/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ -/* 0x04 */ x86emuOp2_illegal_op, -/* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ -/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ -/* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ -/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ -/* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ -/* 0x0a */ x86emuOp2_illegal_op, -/* 0x0b */ x86emuOp2_illegal_op, -/* 0x0c */ x86emuOp2_illegal_op, -/* 0x0d */ x86emuOp2_illegal_op, -/* 0x0e */ x86emuOp2_illegal_op, -/* 0x0f */ x86emuOp2_illegal_op, - -/* 0x10 */ x86emuOp2_illegal_op, -/* 0x11 */ x86emuOp2_illegal_op, -/* 0x12 */ x86emuOp2_illegal_op, -/* 0x13 */ x86emuOp2_illegal_op, -/* 0x14 */ x86emuOp2_illegal_op, -/* 0x15 */ x86emuOp2_illegal_op, -/* 0x16 */ x86emuOp2_illegal_op, -/* 0x17 */ x86emuOp2_illegal_op, -/* 0x18 */ x86emuOp2_illegal_op, -/* 0x19 */ x86emuOp2_illegal_op, -/* 0x1a */ x86emuOp2_illegal_op, -/* 0x1b */ x86emuOp2_illegal_op, -/* 0x1c */ x86emuOp2_illegal_op, -/* 0x1d */ x86emuOp2_illegal_op, -/* 0x1e */ x86emuOp2_illegal_op, -/* 0x1f */ x86emuOp2_illegal_op, - -/* 0x20 */ x86emuOp2_illegal_op, /* mov reg32,creg (ring 0 PM) */ -/* 0x21 */ x86emuOp2_illegal_op, /* mov reg32,dreg (ring 0 PM) */ -/* 0x22 */ x86emuOp2_illegal_op, /* mov creg,reg32 (ring 0 PM) */ -/* 0x23 */ x86emuOp2_illegal_op, /* mov dreg,reg32 (ring 0 PM) */ -/* 0x24 */ x86emuOp2_illegal_op, /* mov reg32,treg (ring 0 PM) */ -/* 0x25 */ x86emuOp2_illegal_op, -/* 0x26 */ x86emuOp2_illegal_op, /* mov treg,reg32 (ring 0 PM) */ -/* 0x27 */ x86emuOp2_illegal_op, -/* 0x28 */ x86emuOp2_illegal_op, -/* 0x29 */ x86emuOp2_illegal_op, -/* 0x2a */ x86emuOp2_illegal_op, -/* 0x2b */ x86emuOp2_illegal_op, -/* 0x2c */ x86emuOp2_illegal_op, -/* 0x2d */ x86emuOp2_illegal_op, -/* 0x2e */ x86emuOp2_illegal_op, -/* 0x2f */ x86emuOp2_illegal_op, - -/* 0x30 */ x86emuOp2_illegal_op, -/* 0x31 */ x86emuOp2_illegal_op, -/* 0x32 */ x86emuOp2_illegal_op, -/* 0x33 */ x86emuOp2_illegal_op, -/* 0x34 */ x86emuOp2_illegal_op, -/* 0x35 */ x86emuOp2_illegal_op, -/* 0x36 */ x86emuOp2_illegal_op, -/* 0x37 */ x86emuOp2_illegal_op, -/* 0x38 */ x86emuOp2_illegal_op, -/* 0x39 */ x86emuOp2_illegal_op, -/* 0x3a */ x86emuOp2_illegal_op, -/* 0x3b */ x86emuOp2_illegal_op, -/* 0x3c */ x86emuOp2_illegal_op, -/* 0x3d */ x86emuOp2_illegal_op, -/* 0x3e */ x86emuOp2_illegal_op, -/* 0x3f */ x86emuOp2_illegal_op, - -/* 0x40 */ x86emuOp2_illegal_op, -/* 0x41 */ x86emuOp2_illegal_op, -/* 0x42 */ x86emuOp2_illegal_op, -/* 0x43 */ x86emuOp2_illegal_op, -/* 0x44 */ x86emuOp2_illegal_op, -/* 0x45 */ x86emuOp2_illegal_op, -/* 0x46 */ x86emuOp2_illegal_op, -/* 0x47 */ x86emuOp2_illegal_op, -/* 0x48 */ x86emuOp2_illegal_op, -/* 0x49 */ x86emuOp2_illegal_op, -/* 0x4a */ x86emuOp2_illegal_op, -/* 0x4b */ x86emuOp2_illegal_op, -/* 0x4c */ x86emuOp2_illegal_op, -/* 0x4d */ x86emuOp2_illegal_op, -/* 0x4e */ x86emuOp2_illegal_op, -/* 0x4f */ x86emuOp2_illegal_op, - -/* 0x50 */ x86emuOp2_illegal_op, -/* 0x51 */ x86emuOp2_illegal_op, -/* 0x52 */ x86emuOp2_illegal_op, -/* 0x53 */ x86emuOp2_illegal_op, -/* 0x54 */ x86emuOp2_illegal_op, -/* 0x55 */ x86emuOp2_illegal_op, -/* 0x56 */ x86emuOp2_illegal_op, -/* 0x57 */ x86emuOp2_illegal_op, -/* 0x58 */ x86emuOp2_illegal_op, -/* 0x59 */ x86emuOp2_illegal_op, -/* 0x5a */ x86emuOp2_illegal_op, -/* 0x5b */ x86emuOp2_illegal_op, -/* 0x5c */ x86emuOp2_illegal_op, -/* 0x5d */ x86emuOp2_illegal_op, -/* 0x5e */ x86emuOp2_illegal_op, -/* 0x5f */ x86emuOp2_illegal_op, - -/* 0x60 */ x86emuOp2_illegal_op, -/* 0x61 */ x86emuOp2_illegal_op, -/* 0x62 */ x86emuOp2_illegal_op, -/* 0x63 */ x86emuOp2_illegal_op, -/* 0x64 */ x86emuOp2_illegal_op, -/* 0x65 */ x86emuOp2_illegal_op, -/* 0x66 */ x86emuOp2_illegal_op, -/* 0x67 */ x86emuOp2_illegal_op, -/* 0x68 */ x86emuOp2_illegal_op, -/* 0x69 */ x86emuOp2_illegal_op, -/* 0x6a */ x86emuOp2_illegal_op, -/* 0x6b */ x86emuOp2_illegal_op, -/* 0x6c */ x86emuOp2_illegal_op, -/* 0x6d */ x86emuOp2_illegal_op, -/* 0x6e */ x86emuOp2_illegal_op, -/* 0x6f */ x86emuOp2_illegal_op, - -/* 0x70 */ x86emuOp2_illegal_op, -/* 0x71 */ x86emuOp2_illegal_op, -/* 0x72 */ x86emuOp2_illegal_op, -/* 0x73 */ x86emuOp2_illegal_op, -/* 0x74 */ x86emuOp2_illegal_op, -/* 0x75 */ x86emuOp2_illegal_op, -/* 0x76 */ x86emuOp2_illegal_op, -/* 0x77 */ x86emuOp2_illegal_op, -/* 0x78 */ x86emuOp2_illegal_op, -/* 0x79 */ x86emuOp2_illegal_op, -/* 0x7a */ x86emuOp2_illegal_op, -/* 0x7b */ x86emuOp2_illegal_op, -/* 0x7c */ x86emuOp2_illegal_op, -/* 0x7d */ x86emuOp2_illegal_op, -/* 0x7e */ x86emuOp2_illegal_op, -/* 0x7f */ x86emuOp2_illegal_op, - -/* 0x80 */ x86emuOp2_long_jump, -/* 0x81 */ x86emuOp2_long_jump, -/* 0x82 */ x86emuOp2_long_jump, -/* 0x83 */ x86emuOp2_long_jump, -/* 0x84 */ x86emuOp2_long_jump, -/* 0x85 */ x86emuOp2_long_jump, -/* 0x86 */ x86emuOp2_long_jump, -/* 0x87 */ x86emuOp2_long_jump, -/* 0x88 */ x86emuOp2_long_jump, -/* 0x89 */ x86emuOp2_long_jump, -/* 0x8a */ x86emuOp2_long_jump, -/* 0x8b */ x86emuOp2_long_jump, -/* 0x8c */ x86emuOp2_long_jump, -/* 0x8d */ x86emuOp2_long_jump, -/* 0x8e */ x86emuOp2_long_jump, -/* 0x8f */ x86emuOp2_long_jump, - -/* 0x90 */ x86emuOp2_set_byte, -/* 0x91 */ x86emuOp2_set_byte, -/* 0x92 */ x86emuOp2_set_byte, -/* 0x93 */ x86emuOp2_set_byte, -/* 0x94 */ x86emuOp2_set_byte, -/* 0x95 */ x86emuOp2_set_byte, -/* 0x96 */ x86emuOp2_set_byte, -/* 0x97 */ x86emuOp2_set_byte, -/* 0x98 */ x86emuOp2_set_byte, -/* 0x99 */ x86emuOp2_set_byte, -/* 0x9a */ x86emuOp2_set_byte, -/* 0x9b */ x86emuOp2_set_byte, -/* 0x9c */ x86emuOp2_set_byte, -/* 0x9d */ x86emuOp2_set_byte, -/* 0x9e */ x86emuOp2_set_byte, -/* 0x9f */ x86emuOp2_set_byte, - -/* 0xa0 */ x86emuOp2_push_FS, -/* 0xa1 */ x86emuOp2_pop_FS, -/* 0xa2 */ x86emuOp2_illegal_op, -/* 0xa3 */ x86emuOp2_bt_R, -/* 0xa4 */ x86emuOp2_shld_IMM, -/* 0xa5 */ x86emuOp2_shld_CL, -/* 0xa6 */ x86emuOp2_illegal_op, -/* 0xa7 */ x86emuOp2_illegal_op, -/* 0xa8 */ x86emuOp2_push_GS, -/* 0xa9 */ x86emuOp2_pop_GS, -/* 0xaa */ x86emuOp2_illegal_op, -/* 0xab */ x86emuOp2_bt_R, -/* 0xac */ x86emuOp2_shrd_IMM, -/* 0xad */ x86emuOp2_shrd_CL, -/* 0xae */ x86emuOp2_illegal_op, -/* 0xaf */ x86emuOp2_imul_R_RM, - -/* 0xb0 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ -/* 0xb1 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ -/* 0xb2 */ x86emuOp2_lss_R_IMM, -/* 0xb3 */ x86emuOp2_btr_R, -/* 0xb4 */ x86emuOp2_lfs_R_IMM, -/* 0xb5 */ x86emuOp2_lgs_R_IMM, -/* 0xb6 */ x86emuOp2_movzx_byte_R_RM, -/* 0xb7 */ x86emuOp2_movzx_word_R_RM, -/* 0xb8 */ x86emuOp2_illegal_op, -/* 0xb9 */ x86emuOp2_illegal_op, -/* 0xba */ x86emuOp2_btX_I, -/* 0xbb */ x86emuOp2_btc_R, -/* 0xbc */ x86emuOp2_bsf, -/* 0xbd */ x86emuOp2_bsr, -/* 0xbe */ x86emuOp2_movsx_byte_R_RM, -/* 0xbf */ x86emuOp2_movsx_word_R_RM, - -/* 0xc0 */ x86emuOp2_illegal_op, /* TODO: xadd */ -/* 0xc1 */ x86emuOp2_illegal_op, /* TODO: xadd */ -/* 0xc2 */ x86emuOp2_illegal_op, -/* 0xc3 */ x86emuOp2_illegal_op, -/* 0xc4 */ x86emuOp2_illegal_op, -/* 0xc5 */ x86emuOp2_illegal_op, -/* 0xc6 */ x86emuOp2_illegal_op, -/* 0xc7 */ x86emuOp2_illegal_op, -/* 0xc8 */ x86emuOp2_illegal_op, /* TODO: bswap */ -/* 0xc9 */ x86emuOp2_illegal_op, /* TODO: bswap */ -/* 0xca */ x86emuOp2_illegal_op, /* TODO: bswap */ -/* 0xcb */ x86emuOp2_illegal_op, /* TODO: bswap */ -/* 0xcc */ x86emuOp2_illegal_op, /* TODO: bswap */ -/* 0xcd */ x86emuOp2_illegal_op, /* TODO: bswap */ -/* 0xce */ x86emuOp2_illegal_op, /* TODO: bswap */ -/* 0xcf */ x86emuOp2_illegal_op, /* TODO: bswap */ - -/* 0xd0 */ x86emuOp2_illegal_op, -/* 0xd1 */ x86emuOp2_illegal_op, -/* 0xd2 */ x86emuOp2_illegal_op, -/* 0xd3 */ x86emuOp2_illegal_op, -/* 0xd4 */ x86emuOp2_illegal_op, -/* 0xd5 */ x86emuOp2_illegal_op, -/* 0xd6 */ x86emuOp2_illegal_op, -/* 0xd7 */ x86emuOp2_illegal_op, -/* 0xd8 */ x86emuOp2_illegal_op, -/* 0xd9 */ x86emuOp2_illegal_op, -/* 0xda */ x86emuOp2_illegal_op, -/* 0xdb */ x86emuOp2_illegal_op, -/* 0xdc */ x86emuOp2_illegal_op, -/* 0xdd */ x86emuOp2_illegal_op, -/* 0xde */ x86emuOp2_illegal_op, -/* 0xdf */ x86emuOp2_illegal_op, - -/* 0xe0 */ x86emuOp2_illegal_op, -/* 0xe1 */ x86emuOp2_illegal_op, -/* 0xe2 */ x86emuOp2_illegal_op, -/* 0xe3 */ x86emuOp2_illegal_op, -/* 0xe4 */ x86emuOp2_illegal_op, -/* 0xe5 */ x86emuOp2_illegal_op, -/* 0xe6 */ x86emuOp2_illegal_op, -/* 0xe7 */ x86emuOp2_illegal_op, -/* 0xe8 */ x86emuOp2_illegal_op, -/* 0xe9 */ x86emuOp2_illegal_op, -/* 0xea */ x86emuOp2_illegal_op, -/* 0xeb */ x86emuOp2_illegal_op, -/* 0xec */ x86emuOp2_illegal_op, -/* 0xed */ x86emuOp2_illegal_op, -/* 0xee */ x86emuOp2_illegal_op, -/* 0xef */ x86emuOp2_illegal_op, - -/* 0xf0 */ x86emuOp2_illegal_op, -/* 0xf1 */ x86emuOp2_illegal_op, -/* 0xf2 */ x86emuOp2_illegal_op, -/* 0xf3 */ x86emuOp2_illegal_op, -/* 0xf4 */ x86emuOp2_illegal_op, -/* 0xf5 */ x86emuOp2_illegal_op, -/* 0xf6 */ x86emuOp2_illegal_op, -/* 0xf7 */ x86emuOp2_illegal_op, -/* 0xf8 */ x86emuOp2_illegal_op, -/* 0xf9 */ x86emuOp2_illegal_op, -/* 0xfa */ x86emuOp2_illegal_op, -/* 0xfb */ x86emuOp2_illegal_op, -/* 0xfc */ x86emuOp2_illegal_op, -/* 0xfd */ x86emuOp2_illegal_op, -/* 0xfe */ x86emuOp2_illegal_op, -/* 0xff */ x86emuOp2_illegal_op, -}; diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c b/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c deleted file mode 100644 index 72b1bf2..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c +++ /dev/null @@ -1,2914 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: This file contains the code to implement the primitive -* machine operations used by the emulation code in ops.c -* -* Carry Chain Calculation -* -* This represents a somewhat expensive calculation which is -* apparently required to emulate the setting of the OF and AF flag. -* The latter is not so important, but the former is. The overflow -* flag is the XOR of the top two bits of the carry chain for an -* addition (similar for subtraction). Since we do not want to -* simulate the addition in a bitwise manner, we try to calculate the -* carry chain given the two operands and the result. -* -* So, given the following table, which represents the addition of two -* bits, we can derive a formula for the carry chain. -* -* a b cin r cout -* 0 0 0 0 0 -* 0 0 1 1 0 -* 0 1 0 1 0 -* 0 1 1 0 1 -* 1 0 0 1 0 -* 1 0 1 0 1 -* 1 1 0 0 1 -* 1 1 1 1 1 -* -* Construction of table for cout: -* -* ab -* r \ 00 01 11 10 -* |------------------ -* 0 | 0 1 1 1 -* 1 | 0 0 1 0 -* -* By inspection, one gets: cc = ab + r'(a + b) -* -* That represents alot of operations, but NO CHOICE.... -* -* Borrow Chain Calculation. -* -* The following table represents the subtraction of two bits, from -* which we can derive a formula for the borrow chain. -* -* a b bin r bout -* 0 0 0 0 0 -* 0 0 1 1 1 -* 0 1 0 1 1 -* 0 1 1 0 1 -* 1 0 0 1 0 -* 1 0 1 0 0 -* 1 1 0 0 0 -* 1 1 1 1 1 -* -* Construction of table for cout: -* -* ab -* r \ 00 01 11 10 -* |------------------ -* 0 | 0 1 0 0 -* 1 | 1 1 1 0 -* -* By inspection, one gets: bc = a'b + r(a' + b) -* -****************************************************************************/ - -#define PRIM_OPS_NO_REDEFINE_ASM -#include "x86emu/x86emui.h" - -/*------------------------- Global Variables ------------------------------*/ - -#ifndef __HAVE_INLINE_ASSEMBLER__ - -static u32 x86emu_parity_tab[8] = -{ - 0x96696996, - 0x69969669, - 0x69969669, - 0x96696996, - 0x69969669, - 0x96696996, - 0x96696996, - 0x69969669, -}; - -#endif - -#define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) -#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) - -/*----------------------------- Implementation ----------------------------*/ - -#ifndef __HAVE_INLINE_ASSEMBLER__ - -/**************************************************************************** -REMARKS: -Implements the AAA instruction and side effects. -****************************************************************************/ -u16 aaa_word(u16 d) -{ - u16 res; - if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { - d += 0x6; - d += 0x100; - SET_FLAG(F_AF); - SET_FLAG(F_CF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - } - res = (u16)(d & 0xFF0F); - CLEAR_FLAG(F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the AAA instruction and side effects. -****************************************************************************/ -u16 aas_word(u16 d) -{ - u16 res; - if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { - d -= 0x6; - d -= 0x100; - SET_FLAG(F_AF); - SET_FLAG(F_CF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - } - res = (u16)(d & 0xFF0F); - CLEAR_FLAG(F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the AAD instruction and side effects. -****************************************************************************/ -u16 aad_word(u16 d) -{ - u16 l; - u8 hb, lb; - - hb = (u8)((d >> 8) & 0xff); - lb = (u8)((d & 0xff)); - l = (u16)((lb + 10 * hb) & 0xFF); - - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - CLEAR_FLAG(F_OF); - CONDITIONAL_SET_FLAG(l & 0x80, F_SF); - CONDITIONAL_SET_FLAG(l == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); - return l; -} - -/**************************************************************************** -REMARKS: -Implements the AAM instruction and side effects. -****************************************************************************/ -u16 aam_word(u8 d) -{ - u16 h, l; - - h = (u16)(d / 10); - l = (u16)(d % 10); - l |= (u16)(h << 8); - - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - CLEAR_FLAG(F_OF); - CONDITIONAL_SET_FLAG(l & 0x80, F_SF); - CONDITIONAL_SET_FLAG(l == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); - return l; -} - -/**************************************************************************** -REMARKS: -Implements the ADC instruction and side effects. -****************************************************************************/ -u8 adc_byte(u8 d, u8 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 cc; - - if (ACCESS_FLAG(F_CF)) - res = 1 + d + s; - else - res = d + s; - - CONDITIONAL_SET_FLAG(res & 0x100, F_CF); - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the carry chain SEE NOTE AT TOP. */ - cc = (s & d) | ((~res) & (s | d)); - CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); - CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the ADC instruction and side effects. -****************************************************************************/ -u16 adc_word(u16 d, u16 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 cc; - - if (ACCESS_FLAG(F_CF)) - res = 1 + d + s; - else - res = d + s; - - CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the carry chain SEE NOTE AT TOP. */ - cc = (s & d) | ((~res) & (s | d)); - CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); - CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the ADC instruction and side effects. -****************************************************************************/ -u32 adc_long(u32 d, u32 s) -{ - register u32 lo; /* all operands in native machine order */ - register u32 hi; - register u32 res; - register u32 cc; - - if (ACCESS_FLAG(F_CF)) { - lo = 1 + (d & 0xFFFF) + (s & 0xFFFF); - res = 1 + d + s; - } - else { - lo = (d & 0xFFFF) + (s & 0xFFFF); - res = d + s; - } - hi = (lo >> 16) + (d >> 16) + (s >> 16); - - CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the carry chain SEE NOTE AT TOP. */ - cc = (s & d) | ((~res) & (s | d)); - CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); - CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the ADD instruction and side effects. -****************************************************************************/ -u8 add_byte(u8 d, u8 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 cc; - - res = d + s; - CONDITIONAL_SET_FLAG(res & 0x100, F_CF); - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the carry chain SEE NOTE AT TOP. */ - cc = (s & d) | ((~res) & (s | d)); - CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); - CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the ADD instruction and side effects. -****************************************************************************/ -u16 add_word(u16 d, u16 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 cc; - - res = d + s; - CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the carry chain SEE NOTE AT TOP. */ - cc = (s & d) | ((~res) & (s | d)); - CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); - CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the ADD instruction and side effects. -****************************************************************************/ -u32 add_long(u32 d, u32 s) -{ - register u32 lo; /* all operands in native machine order */ - register u32 hi; - register u32 res; - register u32 cc; - - lo = (d & 0xFFFF) + (s & 0xFFFF); - res = d + s; - hi = (lo >> 16) + (d >> 16) + (s >> 16); - - CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the carry chain SEE NOTE AT TOP. */ - cc = (s & d) | ((~res) & (s | d)); - CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); - CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); - - return res; -} - -/**************************************************************************** -REMARKS: -Implements the AND instruction and side effects. -****************************************************************************/ -u8 and_byte(u8 d, u8 s) -{ - register u8 res; /* all operands in native machine order */ - - res = d & s; - - /* set the flags */ - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res), F_PF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the AND instruction and side effects. -****************************************************************************/ -u16 and_word(u16 d, u16 s) -{ - register u16 res; /* all operands in native machine order */ - - res = d & s; - - /* set the flags */ - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the AND instruction and side effects. -****************************************************************************/ -u32 and_long(u32 d, u32 s) -{ - register u32 res; /* all operands in native machine order */ - - res = d & s; - - /* set the flags */ - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the CMP instruction and side effects. -****************************************************************************/ -u8 cmp_byte(u8 d, u8 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - res = d - s; - CLEAR_FLAG(F_CF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return d; -} - -/**************************************************************************** -REMARKS: -Implements the CMP instruction and side effects. -****************************************************************************/ -u16 cmp_word(u16 d, u16 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - res = d - s; - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return d; -} - -/**************************************************************************** -REMARKS: -Implements the CMP instruction and side effects. -****************************************************************************/ -u32 cmp_long(u32 d, u32 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - res = d - s; - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return d; -} - -/**************************************************************************** -REMARKS: -Implements the DAA instruction and side effects. -****************************************************************************/ -u8 daa_byte(u8 d) -{ - u32 res = d; - if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { - res += 6; - SET_FLAG(F_AF); - } - if (res > 0x9F || ACCESS_FLAG(F_CF)) { - res += 0x60; - SET_FLAG(F_CF); - } - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG((res & 0xFF) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the DAS instruction and side effects. -****************************************************************************/ -u8 das_byte(u8 d) -{ - if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { - d -= 6; - SET_FLAG(F_AF); - } - if (d > 0x9F || ACCESS_FLAG(F_CF)) { - d -= 0x60; - SET_FLAG(F_CF); - } - CONDITIONAL_SET_FLAG(d & 0x80, F_SF); - CONDITIONAL_SET_FLAG(d == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(d & 0xff), F_PF); - return d; -} - -/**************************************************************************** -REMARKS: -Implements the DEC instruction and side effects. -****************************************************************************/ -u8 dec_byte(u8 d) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - res = d - 1; - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - /* based on sub_byte, uses s==1. */ - bc = (res & (~d | 1)) | (~d & 1); - /* carry flag unchanged */ - CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the DEC instruction and side effects. -****************************************************************************/ -u16 dec_word(u16 d) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - res = d - 1; - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - /* based on the sub_byte routine, with s==1 */ - bc = (res & (~d | 1)) | (~d & 1); - /* carry flag unchanged */ - CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the DEC instruction and side effects. -****************************************************************************/ -u32 dec_long(u32 d) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - res = d - 1; - - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | 1)) | (~d & 1); - /* carry flag unchanged */ - CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the INC instruction and side effects. -****************************************************************************/ -u8 inc_byte(u8 d) -{ - register u32 res; /* all operands in native machine order */ - register u32 cc; - - res = d + 1; - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the carry chain SEE NOTE AT TOP. */ - cc = ((1 & d) | (~res)) & (1 | d); - CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); - CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the INC instruction and side effects. -****************************************************************************/ -u16 inc_word(u16 d) -{ - register u32 res; /* all operands in native machine order */ - register u32 cc; - - res = d + 1; - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the carry chain SEE NOTE AT TOP. */ - cc = (1 & d) | ((~res) & (1 | d)); - CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); - CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the INC instruction and side effects. -****************************************************************************/ -u32 inc_long(u32 d) -{ - register u32 res; /* all operands in native machine order */ - register u32 cc; - - res = d + 1; - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the carry chain SEE NOTE AT TOP. */ - cc = (1 & d) | ((~res) & (1 | d)); - CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); - CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the OR instruction and side effects. -****************************************************************************/ -u8 or_byte(u8 d, u8 s) -{ - register u8 res; /* all operands in native machine order */ - - res = d | s; - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res), F_PF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the OR instruction and side effects. -****************************************************************************/ -u16 or_word(u16 d, u16 s) -{ - register u16 res; /* all operands in native machine order */ - - res = d | s; - /* set the carry flag to be bit 8 */ - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the OR instruction and side effects. -****************************************************************************/ -u32 or_long(u32 d, u32 s) -{ - register u32 res; /* all operands in native machine order */ - - res = d | s; - - /* set the carry flag to be bit 8 */ - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the OR instruction and side effects. -****************************************************************************/ -u8 neg_byte(u8 s) -{ - register u8 res; - register u8 bc; - - CONDITIONAL_SET_FLAG(s != 0, F_CF); - res = (u8)-s; - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res), F_PF); - /* calculate the borrow chain --- modified such that d=0. - substitutiing d=0 into bc= res&(~d|s)|(~d&s); - (the one used for sub) and simplifying, since ~d=0xff..., - ~d|s == 0xffff..., and res&0xfff... == res. Similarly - ~d&s == s. So the simplified result is: */ - bc = res | s; - CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the OR instruction and side effects. -****************************************************************************/ -u16 neg_word(u16 s) -{ - register u16 res; - register u16 bc; - - CONDITIONAL_SET_FLAG(s != 0, F_CF); - res = (u16)-s; - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain --- modified such that d=0. - substitutiing d=0 into bc= res&(~d|s)|(~d&s); - (the one used for sub) and simplifying, since ~d=0xff..., - ~d|s == 0xffff..., and res&0xfff... == res. Similarly - ~d&s == s. So the simplified result is: */ - bc = res | s; - CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the OR instruction and side effects. -****************************************************************************/ -u32 neg_long(u32 s) -{ - register u32 res; - register u32 bc; - - CONDITIONAL_SET_FLAG(s != 0, F_CF); - res = (u32)-s; - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain --- modified such that d=0. - substitutiing d=0 into bc= res&(~d|s)|(~d&s); - (the one used for sub) and simplifying, since ~d=0xff..., - ~d|s == 0xffff..., and res&0xfff... == res. Similarly - ~d&s == s. So the simplified result is: */ - bc = res | s; - CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the NOT instruction and side effects. -****************************************************************************/ -u8 not_byte(u8 s) -{ - return ~s; -} - -/**************************************************************************** -REMARKS: -Implements the NOT instruction and side effects. -****************************************************************************/ -u16 not_word(u16 s) -{ - return ~s; -} - -/**************************************************************************** -REMARKS: -Implements the NOT instruction and side effects. -****************************************************************************/ -u32 not_long(u32 s) -{ - return ~s; -} - -/**************************************************************************** -REMARKS: -Implements the RCL instruction and side effects. -****************************************************************************/ -u8 rcl_byte(u8 d, u8 s) -{ - register unsigned int res, cnt, mask, cf; - - /* s is the rotate distance. It varies from 0 - 8. */ - /* have - - CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 - - want to rotate through the carry by "s" bits. We could - loop, but that's inefficient. So the width is 9, - and we split into three parts: - - The new carry flag (was B_n) - the stuff in B_n-1 .. B_0 - the stuff in B_7 .. B_n+1 - - The new rotate is done mod 9, and given this, - for a rotation of n bits (mod 9) the new carry flag is - then located n bits from the MSB. The low part is - then shifted up cnt bits, and the high part is or'd - in. Using CAPS for new values, and lowercase for the - original values, this can be expressed as: - - IF n > 0 - 1) CF <- b_(8-n) - 2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 - 3) B_(n-1) <- cf - 4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) - */ - res = d; - if ((cnt = s % 9) != 0) { - /* extract the new CARRY FLAG. */ - /* CF <- b_(8-n) */ - cf = (d >> (8 - cnt)) & 0x1; - - /* get the low stuff which rotated - into the range B_7 .. B_cnt */ - /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ - /* note that the right hand side done by the mask */ - res = (d << cnt) & 0xff; - - /* now the high stuff which rotated around - into the positions B_cnt-2 .. B_0 */ - /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ - /* shift it downward, 7-(n-2) = 9-n positions. - and mask off the result before or'ing in. - */ - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (9 - cnt)) & mask; - - /* if the carry flag was set, or it in. */ - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - /* B_(n-1) <- cf */ - res |= 1 << (cnt - 1); - } - /* set the new carry flag, based on the variable "cf" */ - CONDITIONAL_SET_FLAG(cf, F_CF); - /* OVERFLOW is set *IFF* cnt==1, then it is the - xor of CF and the most significant bit. Blecck. */ - /* parenthesized this expression since it appears to - be causing OF to be misset */ - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), - F_OF); - - } - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the RCL instruction and side effects. -****************************************************************************/ -u16 rcl_word(u16 d, u8 s) -{ - register unsigned int res, cnt, mask, cf; - - res = d; - if ((cnt = s % 17) != 0) { - cf = (d >> (16 - cnt)) & 0x1; - res = (d << cnt) & 0xffff; - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (17 - cnt)) & mask; - if (ACCESS_FLAG(F_CF)) { - res |= 1 << (cnt - 1); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), - F_OF); - } - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the RCL instruction and side effects. -****************************************************************************/ -u32 rcl_long(u32 d, u8 s) -{ - register u32 res, cnt, mask, cf; - - res = d; - if ((cnt = s % 33) != 0) { - cf = (d >> (32 - cnt)) & 0x1; - res = (d << cnt) & 0xffffffff; - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (33 - cnt)) & mask; - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - res |= 1 << (cnt - 1); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), - F_OF); - } - return res; -} - -/**************************************************************************** -REMARKS: -Implements the RCR instruction and side effects. -****************************************************************************/ -u8 rcr_byte(u8 d, u8 s) -{ - u32 res, cnt; - u32 mask, cf, ocf = 0; - - /* rotate right through carry */ - /* - s is the rotate distance. It varies from 0 - 8. - d is the byte object rotated. - - have - - CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 - - The new rotate is done mod 9, and given this, - for a rotation of n bits (mod 9) the new carry flag is - then located n bits from the LSB. The low part is - then shifted up cnt bits, and the high part is or'd - in. Using CAPS for new values, and lowercase for the - original values, this can be expressed as: - - IF n > 0 - 1) CF <- b_(n-1) - 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) - 3) B_(8-n) <- cf - 4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) - */ - res = d; - if ((cnt = s % 9) != 0) { - /* extract the new CARRY FLAG. */ - /* CF <- b_(n-1) */ - if (cnt == 1) { - cf = d & 0x1; - /* note hackery here. Access_flag(..) evaluates to either - 0 if flag not set - non-zero if flag is set. - doing access_flag(..) != 0 casts that into either - 0..1 in any representation of the flags register - (i.e. packed bit array or unpacked.) - */ - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - - /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ - /* note that the right hand side done by the mask - This is effectively done by shifting the - object to the right. The result must be masked, - in case the object came in and was treated - as a negative number. Needed??? */ - - mask = (1 << (8 - cnt)) - 1; - res = (d >> cnt) & mask; - - /* now the high stuff which rotated around - into the positions B_cnt-2 .. B_0 */ - /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ - /* shift it downward, 7-(n-2) = 9-n positions. - and mask off the result before or'ing in. - */ - res |= (d << (9 - cnt)); - - /* if the carry flag was set, or it in. */ - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - /* B_(8-n) <- cf */ - res |= 1 << (8 - cnt); - } - /* set the new carry flag, based on the variable "cf" */ - CONDITIONAL_SET_FLAG(cf, F_CF); - /* OVERFLOW is set *IFF* cnt==1, then it is the - xor of CF and the most significant bit. Blecck. */ - /* parenthesized... */ - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), - F_OF); - } - } - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the RCR instruction and side effects. -****************************************************************************/ -u16 rcr_word(u16 d, u8 s) -{ - u32 res, cnt; - u32 mask, cf, ocf = 0; - - /* rotate right through carry */ - res = d; - if ((cnt = s % 17) != 0) { - if (cnt == 1) { - cf = d & 0x1; - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - mask = (1 << (16 - cnt)) - 1; - res = (d >> cnt) & mask; - res |= (d << (17 - cnt)); - if (ACCESS_FLAG(F_CF)) { - res |= 1 << (16 - cnt); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), - F_OF); - } - } - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the RCR instruction and side effects. -****************************************************************************/ -u32 rcr_long(u32 d, u8 s) -{ - u32 res, cnt; - u32 mask, cf, ocf = 0; - - /* rotate right through carry */ - res = d; - if ((cnt = s % 33) != 0) { - if (cnt == 1) { - cf = d & 0x1; - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - mask = (1 << (32 - cnt)) - 1; - res = (d >> cnt) & mask; - if (cnt != 1) - res |= (d << (33 - cnt)); - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - res |= 1 << (32 - cnt); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), - F_OF); - } - } - return res; -} - -/**************************************************************************** -REMARKS: -Implements the ROL instruction and side effects. -****************************************************************************/ -u8 rol_byte(u8 d, u8 s) -{ - register unsigned int res, cnt, mask; - - /* rotate left */ - /* - s is the rotate distance. It varies from 0 - 8. - d is the byte object rotated. - - have - - CF B_7 ... B_0 - - The new rotate is done mod 8. - Much simpler than the "rcl" or "rcr" operations. - - IF n > 0 - 1) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) - 2) B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) - */ - res = d; - if ((cnt = s % 8) != 0) { - /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ - res = (d << cnt); - - /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ - mask = (1 << cnt) - 1; - res |= (d >> (8 - cnt)) & mask; - - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - /* OVERFLOW is set *IFF* s==1, then it is the - xor of CF and the most significant bit. Blecck. */ - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 6) & 0x2)), - F_OF); - } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - } - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the ROL instruction and side effects. -****************************************************************************/ -u16 rol_word(u16 d, u8 s) -{ - register unsigned int res, cnt, mask; - - res = d; - if ((cnt = s % 16) != 0) { - res = (d << cnt); - mask = (1 << cnt) - 1; - res |= (d >> (16 - cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 14) & 0x2)), - F_OF); - } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - } - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the ROL instruction and side effects. -****************************************************************************/ -u32 rol_long(u32 d, u8 s) -{ - register u32 res, cnt, mask; - - res = d; - if ((cnt = s % 32) != 0) { - res = (d << cnt); - mask = (1 << cnt) - 1; - res |= (d >> (32 - cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 30) & 0x2)), - F_OF); - } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - } - return res; -} - -/**************************************************************************** -REMARKS: -Implements the ROR instruction and side effects. -****************************************************************************/ -u8 ror_byte(u8 d, u8 s) -{ - register unsigned int res, cnt, mask; - - /* rotate right */ - /* - s is the rotate distance. It varies from 0 - 8. - d is the byte object rotated. - - have - - B_7 ... B_0 - - The rotate is done mod 8. - - IF n > 0 - 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) - 2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) - */ - res = d; - if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ - /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ - res = (d << (8 - cnt)); - - /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ - mask = (1 << (8 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80, F_CF); - /* OVERFLOW is set *IFF* s==1, then it is the - xor of the two most significant bits. Blecck. */ - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); - } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80, F_CF); - } - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the ROR instruction and side effects. -****************************************************************************/ -u16 ror_word(u16 d, u8 s) -{ - register unsigned int res, cnt, mask; - - res = d; - if ((cnt = s % 16) != 0) { - res = (d << (16 - cnt)); - mask = (1 << (16 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); - } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); - } - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the ROR instruction and side effects. -****************************************************************************/ -u32 ror_long(u32 d, u8 s) -{ - register u32 res, cnt, mask; - - res = d; - if ((cnt = s % 32) != 0) { - res = (d << (32 - cnt)); - mask = (1 << (32 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); - } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); - } - return res; -} - -/**************************************************************************** -REMARKS: -Implements the SHL instruction and side effects. -****************************************************************************/ -u8 shl_byte(u8 d, u8 s) -{ - unsigned int cnt, res, cf; - - if (s < 8) { - cnt = s % 8; - - /* last bit shifted out goes into carry flag */ - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (8 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else { - res = (u8) d; - } - - if (cnt == 1) { - /* Needs simplification. */ - CONDITIONAL_SET_FLAG( - (((res & 0x80) == 0x80) ^ - (ACCESS_FLAG(F_CF) != 0)), - /* was (M.x86.R_FLG&F_CF)==F_CF)), */ - F_OF); - } else { - CLEAR_FLAG(F_OF); - } - } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); - } - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the SHL instruction and side effects. -****************************************************************************/ -u16 shl_word(u16 d, u8 s) -{ - unsigned int cnt, res, cf; - - if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else { - res = (u16) d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG( - (((res & 0x8000) == 0x8000) ^ - (ACCESS_FLAG(F_CF) != 0)), - F_OF); - } else { - CLEAR_FLAG(F_OF); - } - } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); - } - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the SHL instruction and side effects. -****************************************************************************/ -u32 shl_long(u32 d, u8 s) -{ - unsigned int cnt, res, cf; - - if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } - } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); - } - return res; -} - -/**************************************************************************** -REMARKS: -Implements the SHR instruction and side effects. -****************************************************************************/ -u8 shr_byte(u8 d, u8 s) -{ - unsigned int cnt, res, cf; - - if (s < 8) { - cnt = s % 8; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else { - res = (u8) d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); - } else { - CLEAR_FLAG(F_OF); - } - } else { - res = 0; - CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); - } - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the SHR instruction and side effects. -****************************************************************************/ -u16 shr_word(u16 d, u8 s) -{ - unsigned int cnt, res, cf; - - if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else { - res = d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); - } else { - CLEAR_FLAG(F_OF); - } - } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the SHR instruction and side effects. -****************************************************************************/ -u32 shr_long(u32 d, u8 s) -{ - unsigned int cnt, res, cf; - - if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); - } else { - CLEAR_FLAG(F_OF); - } - } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } - return res; -} - -/**************************************************************************** -REMARKS: -Implements the SAR instruction and side effects. -****************************************************************************/ -u8 sar_byte(u8 d, u8 s) -{ - unsigned int cnt, res, cf, mask, sf; - - res = d; - sf = d & 0x80; - cnt = s % 8; - if (cnt > 0 && cnt < 8) { - mask = (1 << (8 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - } else if (cnt >= 8) { - if (sf) { - res = 0xff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } - } - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the SAR instruction and side effects. -****************************************************************************/ -u16 sar_word(u16 d, u8 s) -{ - unsigned int cnt, res, cf, mask, sf; - - sf = d & 0x8000; - cnt = s % 16; - res = d; - if (cnt > 0 && cnt < 16) { - mask = (1 << (16 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else if (cnt >= 16) { - if (sf) { - res = 0xffff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } - } - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the SAR instruction and side effects. -****************************************************************************/ -u32 sar_long(u32 d, u8 s) -{ - u32 cnt, res, cf, mask, sf; - - sf = d & 0x80000000; - cnt = s % 32; - res = d; - if (cnt > 0 && cnt < 32) { - mask = (1 << (32 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else if (cnt >= 32) { - if (sf) { - res = 0xffffffff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } - } - return res; -} - -/**************************************************************************** -REMARKS: -Implements the SHLD instruction and side effects. -****************************************************************************/ -u16 shld_word (u16 d, u16 fill, u8 s) -{ - unsigned int cnt, res, cf; - - if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - res = (d << cnt) | (fill >> (16-cnt)); - cf = d & (1 << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } - } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); - } - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the SHLD instruction and side effects. -****************************************************************************/ -u32 shld_long (u32 d, u32 fill, u8 s) -{ - unsigned int cnt, res, cf; - - if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - res = (d << cnt) | (fill >> (32-cnt)); - cf = d & (1 << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } - } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); - } - return res; -} - -/**************************************************************************** -REMARKS: -Implements the SHRD instruction and side effects. -****************************************************************************/ -u16 shrd_word (u16 d, u16 fill, u8 s) -{ - unsigned int cnt, res, cf; - - if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) | (fill << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else { - res = d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); - } else { - CLEAR_FLAG(F_OF); - } - } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the SHRD instruction and side effects. -****************************************************************************/ -u32 shrd_long (u32 d, u32 fill, u8 s) -{ - unsigned int cnt, res, cf; - - if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) | (fill << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); - } else { - CLEAR_FLAG(F_OF); - } - } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } - return res; -} - -/**************************************************************************** -REMARKS: -Implements the SBB instruction and side effects. -****************************************************************************/ -u8 sbb_byte(u8 d, u8 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - if (ACCESS_FLAG(F_CF)) - res = d - s - 1; - else - res = d - s; - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the SBB instruction and side effects. -****************************************************************************/ -u16 sbb_word(u16 d, u16 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - if (ACCESS_FLAG(F_CF)) - res = d - s - 1; - else - res = d - s; - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the SBB instruction and side effects. -****************************************************************************/ -u32 sbb_long(u32 d, u32 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - if (ACCESS_FLAG(F_CF)) - res = d - s - 1; - else - res = d - s; - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the SUB instruction and side effects. -****************************************************************************/ -u8 sub_byte(u8 d, u8 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - res = d - s; - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return (u8)res; -} - -/**************************************************************************** -REMARKS: -Implements the SUB instruction and side effects. -****************************************************************************/ -u16 sub_word(u16 d, u16 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - res = d - s; - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return (u16)res; -} - -/**************************************************************************** -REMARKS: -Implements the SUB instruction and side effects. -****************************************************************************/ -u32 sub_long(u32 d, u32 s) -{ - register u32 res; /* all operands in native machine order */ - register u32 bc; - - res = d - s; - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - - /* calculate the borrow chain. See note at top */ - bc = (res & (~d | s)) | (~d & s); - CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); - CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); - CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the TEST instruction and side effects. -****************************************************************************/ -void test_byte(u8 d, u8 s) -{ - register u32 res; /* all operands in native machine order */ - - res = d & s; - - CLEAR_FLAG(F_OF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - /* AF == dont care */ - CLEAR_FLAG(F_CF); -} - -/**************************************************************************** -REMARKS: -Implements the TEST instruction and side effects. -****************************************************************************/ -void test_word(u16 d, u16 s) -{ - register u32 res; /* all operands in native machine order */ - - res = d & s; - - CLEAR_FLAG(F_OF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - /* AF == dont care */ - CLEAR_FLAG(F_CF); -} - -/**************************************************************************** -REMARKS: -Implements the TEST instruction and side effects. -****************************************************************************/ -void test_long(u32 d, u32 s) -{ - register u32 res; /* all operands in native machine order */ - - res = d & s; - - CLEAR_FLAG(F_OF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - /* AF == dont care */ - CLEAR_FLAG(F_CF); -} - -/**************************************************************************** -REMARKS: -Implements the XOR instruction and side effects. -****************************************************************************/ -u8 xor_byte(u8 d, u8 s) -{ - register u8 res; /* all operands in native machine order */ - - res = d ^ s; - CLEAR_FLAG(F_OF); - CONDITIONAL_SET_FLAG(res & 0x80, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res), F_PF); - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the XOR instruction and side effects. -****************************************************************************/ -u16 xor_word(u16 d, u16 s) -{ - register u16 res; /* all operands in native machine order */ - - res = d ^ s; - CLEAR_FLAG(F_OF); - CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the XOR instruction and side effects. -****************************************************************************/ -u32 xor_long(u32 d, u32 s) -{ - register u32 res; /* all operands in native machine order */ - - res = d ^ s; - CLEAR_FLAG(F_OF); - CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); - CONDITIONAL_SET_FLAG(res == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - return res; -} - -/**************************************************************************** -REMARKS: -Implements the IMUL instruction and side effects. -****************************************************************************/ -void imul_byte(u8 s) -{ - s16 res = (s16)((s8)M.x86.R_AL * (s8)s); - - M.x86.R_AX = res; - if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) || - ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } -} - -/**************************************************************************** -REMARKS: -Implements the IMUL instruction and side effects. -****************************************************************************/ -void imul_word(u16 s) -{ - s32 res = (s16)M.x86.R_AX * (s16)s; - - M.x86.R_AX = (u16)res; - M.x86.R_DX = (u16)(res >> 16); - if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x00) || - ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } -} - -/**************************************************************************** -REMARKS: -Implements the IMUL instruction and side effects. -****************************************************************************/ -void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) -{ -#ifdef __HAS_LONG_LONG__ - s64 res = (s32)d * (s32)s; - - *res_lo = (u32)res; - *res_hi = (u32)(res >> 32); -#else - u32 d_lo,d_hi,d_sign; - u32 s_lo,s_hi,s_sign; - u32 rlo_lo,rlo_hi,rhi_lo; - - if ((d_sign = d & 0x80000000) != 0) - d = -d; - d_lo = d & 0xFFFF; - d_hi = d >> 16; - if ((s_sign = s & 0x80000000) != 0) - s = -s; - s_lo = s & 0xFFFF; - s_hi = s >> 16; - rlo_lo = d_lo * s_lo; - rlo_hi = (d_hi * s_lo + d_lo * s_hi) + (rlo_lo >> 16); - rhi_lo = d_hi * s_hi + (rlo_hi >> 16); - *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF); - *res_hi = rhi_lo; - if (d_sign != s_sign) { - d = ~*res_lo; - s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); - *res_lo = ~*res_lo+1; - *res_hi = ~*res_hi+(s >> 16); - } -#endif -} - -/**************************************************************************** -REMARKS: -Implements the IMUL instruction and side effects. -****************************************************************************/ -void imul_long(u32 s) -{ - imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); - if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00) || - ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } -} - -/**************************************************************************** -REMARKS: -Implements the MUL instruction and side effects. -****************************************************************************/ -void mul_byte(u8 s) -{ - u16 res = (u16)(M.x86.R_AL * s); - - M.x86.R_AX = res; - if (M.x86.R_AH == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } -} - -/**************************************************************************** -REMARKS: -Implements the MUL instruction and side effects. -****************************************************************************/ -void mul_word(u16 s) -{ - u32 res = M.x86.R_AX * s; - - M.x86.R_AX = (u16)res; - M.x86.R_DX = (u16)(res >> 16); - if (M.x86.R_DX == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } -} - -/**************************************************************************** -REMARKS: -Implements the MUL instruction and side effects. -****************************************************************************/ -void mul_long(u32 s) -{ -#ifdef __HAS_LONG_LONG__ - u64 res = (u32)M.x86.R_EAX * (u32)s; - - M.x86.R_EAX = (u32)res; - M.x86.R_EDX = (u32)(res >> 32); -#else - u32 a,a_lo,a_hi; - u32 s_lo,s_hi; - u32 rlo_lo,rlo_hi,rhi_lo; - - a = M.x86.R_EAX; - a_lo = a & 0xFFFF; - a_hi = a >> 16; - s_lo = s & 0xFFFF; - s_hi = s >> 16; - rlo_lo = a_lo * s_lo; - rlo_hi = (a_hi * s_lo + a_lo * s_hi) + (rlo_lo >> 16); - rhi_lo = a_hi * s_hi + (rlo_hi >> 16); - M.x86.R_EAX = (rlo_hi << 16) | (rlo_lo & 0xFFFF); - M.x86.R_EDX = rhi_lo; -#endif - - if (M.x86.R_EDX == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } -} - -/**************************************************************************** -REMARKS: -Implements the IDIV instruction and side effects. -****************************************************************************/ -void idiv_byte(u8 s) -{ - s32 dvd, div, mod; - - dvd = (s16)M.x86.R_AX; - if (s == 0) { - x86emu_intr_raise(0); - return; - } - div = dvd / (s8)s; - mod = dvd % (s8)s; - if (abs(div) > 0x7f) { - x86emu_intr_raise(0); - return; - } - M.x86.R_AL = (s8) div; - M.x86.R_AH = (s8) mod; -} - -/**************************************************************************** -REMARKS: -Implements the IDIV instruction and side effects. -****************************************************************************/ -void idiv_word(u16 s) -{ - s32 dvd, div, mod; - - dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX; - if (s == 0) { - x86emu_intr_raise(0); - return; - } - div = dvd / (s16)s; - mod = dvd % (s16)s; - if (abs(div) > 0x7fff) { - x86emu_intr_raise(0); - return; - } - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_SF); - CONDITIONAL_SET_FLAG(div == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); - - M.x86.R_AX = (u16)div; - M.x86.R_DX = (u16)mod; -} - -/**************************************************************************** -REMARKS: -Implements the IDIV instruction and side effects. -****************************************************************************/ -void idiv_long(u32 s) -{ -#ifdef __HAS_LONG_LONG__ - s64 dvd, div, mod; - - dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX; - if (s == 0) { - x86emu_intr_raise(0); - return; - } - div = dvd / (s32)s; - mod = dvd % (s32)s; - if (abs(div) > 0x7fffffff) { - x86emu_intr_raise(0); - return; - } -#else - s32 div = 0, mod; - s32 h_dvd = M.x86.R_EDX; - u32 l_dvd = M.x86.R_EAX; - u32 abs_s = s & 0x7FFFFFFF; - u32 abs_h_dvd = h_dvd & 0x7FFFFFFF; - u32 h_s = abs_s >> 1; - u32 l_s = abs_s << 31; - int counter = 31; - int carry; - - if (s == 0) { - x86emu_intr_raise(0); - return; - } - do { - div <<= 1; - carry = (l_dvd >= l_s) ? 0 : 1; - - if (abs_h_dvd < (h_s + carry)) { - h_s >>= 1; - l_s = abs_s << (--counter); - continue; - } else { - abs_h_dvd -= (h_s + carry); - l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) - : (l_dvd - l_s); - h_s >>= 1; - l_s = abs_s << (--counter); - div |= 1; - continue; - } - - } while (counter > -1); - /* overflow */ - if (abs_h_dvd || (l_dvd > abs_s)) { - x86emu_intr_raise(0); - return; - } - /* sign */ - div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000)); - mod = l_dvd; - -#endif - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_ZF); - CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); - - M.x86.R_EAX = (u32)div; - M.x86.R_EDX = (u32)mod; -} - -/**************************************************************************** -REMARKS: -Implements the DIV instruction and side effects. -****************************************************************************/ -void div_byte(u8 s) -{ - u32 dvd, div, mod; - - dvd = M.x86.R_AX; - if (s == 0) { - x86emu_intr_raise(0); - return; - } - div = dvd / (u8)s; - mod = dvd % (u8)s; - if (abs(div) > 0xff) { - x86emu_intr_raise(0); - return; - } - M.x86.R_AL = (u8)div; - M.x86.R_AH = (u8)mod; -} - -/**************************************************************************** -REMARKS: -Implements the DIV instruction and side effects. -****************************************************************************/ -void div_word(u16 s) -{ - u32 dvd, div, mod; - - dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX; - if (s == 0) { - x86emu_intr_raise(0); - return; - } - div = dvd / (u16)s; - mod = dvd % (u16)s; - if (abs(div) > 0xffff) { - x86emu_intr_raise(0); - return; - } - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_SF); - CONDITIONAL_SET_FLAG(div == 0, F_ZF); - CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); - - M.x86.R_AX = (u16)div; - M.x86.R_DX = (u16)mod; -} - -/**************************************************************************** -REMARKS: -Implements the DIV instruction and side effects. -****************************************************************************/ -void div_long(u32 s) -{ -#ifdef __HAS_LONG_LONG__ - u64 dvd, div, mod; - - dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX; - if (s == 0) { - x86emu_intr_raise(0); - return; - } - div = dvd / (u32)s; - mod = dvd % (u32)s; - if (abs(div) > 0xffffffff) { - x86emu_intr_raise(0); - return; - } -#else - s32 div = 0, mod; - s32 h_dvd = M.x86.R_EDX; - u32 l_dvd = M.x86.R_EAX; - - u32 h_s = s; - u32 l_s = 0; - int counter = 32; - int carry; - - if (s == 0) { - x86emu_intr_raise(0); - return; - } - do { - div <<= 1; - carry = (l_dvd >= l_s) ? 0 : 1; - - if (h_dvd < (h_s + carry)) { - h_s >>= 1; - l_s = s << (--counter); - continue; - } else { - h_dvd -= (h_s + carry); - l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) - : (l_dvd - l_s); - h_s >>= 1; - l_s = s << (--counter); - div |= 1; - continue; - } - - } while (counter > -1); - /* overflow */ - if (h_dvd || (l_dvd > s)) { - x86emu_intr_raise(0); - return; - } - mod = l_dvd; -#endif - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_ZF); - CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); - - M.x86.R_EAX = (u32)div; - M.x86.R_EDX = (u32)mod; -} - -#endif /* __HAVE_INLINE_ASSEMBLER__ */ - -/**************************************************************************** -REMARKS: -Implements the IN string instruction and side effects. -****************************************************************************/ -void ins(int size) -{ - int inc = size; - - if (ACCESS_FLAG(F_DF)) { - inc = -size; - } - if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* in until CX is ZERO. */ - u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? - M.x86.R_ECX : M.x86.R_CX); - switch (size) { - case 1: - while (count--) { - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, - (*sys_inb)(M.x86.R_DX)); - M.x86.R_DI += inc; - } - break; - - case 2: - while (count--) { - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, - (*sys_inw)(M.x86.R_DX)); - M.x86.R_DI += inc; - } - break; - case 4: - while (count--) { - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, - (*sys_inl)(M.x86.R_DX)); - M.x86.R_DI += inc; - break; - } - } - M.x86.R_CX = 0; - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ECX = 0; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); - } else { - switch (size) { - case 1: - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, - (*sys_inb)(M.x86.R_DX)); - break; - case 2: - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, - (*sys_inw)(M.x86.R_DX)); - break; - case 4: - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, - (*sys_inl)(M.x86.R_DX)); - break; - } - M.x86.R_DI += inc; - } -} - -/**************************************************************************** -REMARKS: -Implements the OUT string instruction and side effects. -****************************************************************************/ -void outs(int size) -{ - int inc = size; - - if (ACCESS_FLAG(F_DF)) { - inc = -size; - } - if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* out until CX is ZERO. */ - u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? - M.x86.R_ECX : M.x86.R_CX); - switch (size) { - case 1: - while (count--) { - (*sys_outb)(M.x86.R_DX, - fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); - M.x86.R_SI += inc; - } - break; - - case 2: - while (count--) { - (*sys_outw)(M.x86.R_DX, - fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); - M.x86.R_SI += inc; - } - break; - case 4: - while (count--) { - (*sys_outl)(M.x86.R_DX, - fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); - M.x86.R_SI += inc; - break; - } - } - M.x86.R_CX = 0; - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ECX = 0; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); - } else { - switch (size) { - case 1: - (*sys_outb)(M.x86.R_DX, - fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); - break; - case 2: - (*sys_outw)(M.x86.R_DX, - fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); - break; - case 4: - (*sys_outl)(M.x86.R_DX, - fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); - break; - } - M.x86.R_SI += inc; - } -} - -/**************************************************************************** -PARAMETERS: -addr - Address to fetch word from - -REMARKS: -Fetches a word from emulator memory using an absolute address. -****************************************************************************/ -u16 mem_access_word(int addr) -{ -DB( if (CHECK_MEM_ACCESS()) - x86emu_check_mem_access(addr);) - return (*sys_rdw)(addr); -} - -/**************************************************************************** -REMARKS: -Pushes a word onto the stack. - -NOTE: Do not inline this, as (*sys_wrX) is already inline! -****************************************************************************/ -void push_word(u16 w) -{ -DB( if (CHECK_SP_ACCESS()) - x86emu_check_sp_access();) - M.x86.R_SP -= 2; - (*sys_wrw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); -} - -/**************************************************************************** -REMARKS: -Pushes a long onto the stack. - -NOTE: Do not inline this, as (*sys_wrX) is already inline! -****************************************************************************/ -void push_long(u32 w) -{ -DB( if (CHECK_SP_ACCESS()) - x86emu_check_sp_access();) - M.x86.R_SP -= 4; - (*sys_wrl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); -} - -/**************************************************************************** -REMARKS: -Pops a word from the stack. - -NOTE: Do not inline this, as (*sys_rdX) is already inline! -****************************************************************************/ -u16 pop_word(void) -{ - register u16 res; - -DB( if (CHECK_SP_ACCESS()) - x86emu_check_sp_access();) - res = (*sys_rdw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); - M.x86.R_SP += 2; - return res; -} - -/**************************************************************************** -REMARKS: -Pops a long from the stack. - -NOTE: Do not inline this, as (*sys_rdX) is already inline! -****************************************************************************/ -u32 pop_long(void) -{ - register u32 res; - -DB( if (CHECK_SP_ACCESS()) - x86emu_check_sp_access();) - res = (*sys_rdl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); - M.x86.R_SP += 4; - return res; -} - -#ifdef __HAVE_INLINE_ASSEMBLER__ - -u16 aaa_word (u16 d) -{ return aaa_word_asm(&M.x86.R_EFLG,d); } - -u16 aas_word (u16 d) -{ return aas_word_asm(&M.x86.R_EFLG,d); } - -u16 aad_word (u16 d) -{ return aad_word_asm(&M.x86.R_EFLG,d); } - -u16 aam_word (u8 d) -{ return aam_word_asm(&M.x86.R_EFLG,d); } - -u8 adc_byte (u8 d, u8 s) -{ return adc_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 adc_word (u16 d, u16 s) -{ return adc_word_asm(&M.x86.R_EFLG,d,s); } - -u32 adc_long (u32 d, u32 s) -{ return adc_long_asm(&M.x86.R_EFLG,d,s); } - -u8 add_byte (u8 d, u8 s) -{ return add_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 add_word (u16 d, u16 s) -{ return add_word_asm(&M.x86.R_EFLG,d,s); } - -u32 add_long (u32 d, u32 s) -{ return add_long_asm(&M.x86.R_EFLG,d,s); } - -u8 and_byte (u8 d, u8 s) -{ return and_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 and_word (u16 d, u16 s) -{ return and_word_asm(&M.x86.R_EFLG,d,s); } - -u32 and_long (u32 d, u32 s) -{ return and_long_asm(&M.x86.R_EFLG,d,s); } - -u8 cmp_byte (u8 d, u8 s) -{ return cmp_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 cmp_word (u16 d, u16 s) -{ return cmp_word_asm(&M.x86.R_EFLG,d,s); } - -u32 cmp_long (u32 d, u32 s) -{ return cmp_long_asm(&M.x86.R_EFLG,d,s); } - -u8 daa_byte (u8 d) -{ return daa_byte_asm(&M.x86.R_EFLG,d); } - -u8 das_byte (u8 d) -{ return das_byte_asm(&M.x86.R_EFLG,d); } - -u8 dec_byte (u8 d) -{ return dec_byte_asm(&M.x86.R_EFLG,d); } - -u16 dec_word (u16 d) -{ return dec_word_asm(&M.x86.R_EFLG,d); } - -u32 dec_long (u32 d) -{ return dec_long_asm(&M.x86.R_EFLG,d); } - -u8 inc_byte (u8 d) -{ return inc_byte_asm(&M.x86.R_EFLG,d); } - -u16 inc_word (u16 d) -{ return inc_word_asm(&M.x86.R_EFLG,d); } - -u32 inc_long (u32 d) -{ return inc_long_asm(&M.x86.R_EFLG,d); } - -u8 or_byte (u8 d, u8 s) -{ return or_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 or_word (u16 d, u16 s) -{ return or_word_asm(&M.x86.R_EFLG,d,s); } - -u32 or_long (u32 d, u32 s) -{ return or_long_asm(&M.x86.R_EFLG,d,s); } - -u8 neg_byte (u8 s) -{ return neg_byte_asm(&M.x86.R_EFLG,s); } - -u16 neg_word (u16 s) -{ return neg_word_asm(&M.x86.R_EFLG,s); } - -u32 neg_long (u32 s) -{ return neg_long_asm(&M.x86.R_EFLG,s); } - -u8 not_byte (u8 s) -{ return not_byte_asm(&M.x86.R_EFLG,s); } - -u16 not_word (u16 s) -{ return not_word_asm(&M.x86.R_EFLG,s); } - -u32 not_long (u32 s) -{ return not_long_asm(&M.x86.R_EFLG,s); } - -u8 rcl_byte (u8 d, u8 s) -{ return rcl_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 rcl_word (u16 d, u8 s) -{ return rcl_word_asm(&M.x86.R_EFLG,d,s); } - -u32 rcl_long (u32 d, u8 s) -{ return rcl_long_asm(&M.x86.R_EFLG,d,s); } - -u8 rcr_byte (u8 d, u8 s) -{ return rcr_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 rcr_word (u16 d, u8 s) -{ return rcr_word_asm(&M.x86.R_EFLG,d,s); } - -u32 rcr_long (u32 d, u8 s) -{ return rcr_long_asm(&M.x86.R_EFLG,d,s); } - -u8 rol_byte (u8 d, u8 s) -{ return rol_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 rol_word (u16 d, u8 s) -{ return rol_word_asm(&M.x86.R_EFLG,d,s); } - -u32 rol_long (u32 d, u8 s) -{ return rol_long_asm(&M.x86.R_EFLG,d,s); } - -u8 ror_byte (u8 d, u8 s) -{ return ror_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 ror_word (u16 d, u8 s) -{ return ror_word_asm(&M.x86.R_EFLG,d,s); } - -u32 ror_long (u32 d, u8 s) -{ return ror_long_asm(&M.x86.R_EFLG,d,s); } - -u8 shl_byte (u8 d, u8 s) -{ return shl_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 shl_word (u16 d, u8 s) -{ return shl_word_asm(&M.x86.R_EFLG,d,s); } - -u32 shl_long (u32 d, u8 s) -{ return shl_long_asm(&M.x86.R_EFLG,d,s); } - -u8 shr_byte (u8 d, u8 s) -{ return shr_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 shr_word (u16 d, u8 s) -{ return shr_word_asm(&M.x86.R_EFLG,d,s); } - -u32 shr_long (u32 d, u8 s) -{ return shr_long_asm(&M.x86.R_EFLG,d,s); } - -u8 sar_byte (u8 d, u8 s) -{ return sar_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 sar_word (u16 d, u8 s) -{ return sar_word_asm(&M.x86.R_EFLG,d,s); } - -u32 sar_long (u32 d, u8 s) -{ return sar_long_asm(&M.x86.R_EFLG,d,s); } - -u16 shld_word (u16 d, u16 fill, u8 s) -{ return shld_word_asm(&M.x86.R_EFLG,d,fill,s); } - -u32 shld_long (u32 d, u32 fill, u8 s) -{ return shld_long_asm(&M.x86.R_EFLG,d,fill,s); } - -u16 shrd_word (u16 d, u16 fill, u8 s) -{ return shrd_word_asm(&M.x86.R_EFLG,d,fill,s); } - -u32 shrd_long (u32 d, u32 fill, u8 s) -{ return shrd_long_asm(&M.x86.R_EFLG,d,fill,s); } - -u8 sbb_byte (u8 d, u8 s) -{ return sbb_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 sbb_word (u16 d, u16 s) -{ return sbb_word_asm(&M.x86.R_EFLG,d,s); } - -u32 sbb_long (u32 d, u32 s) -{ return sbb_long_asm(&M.x86.R_EFLG,d,s); } - -u8 sub_byte (u8 d, u8 s) -{ return sub_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 sub_word (u16 d, u16 s) -{ return sub_word_asm(&M.x86.R_EFLG,d,s); } - -u32 sub_long (u32 d, u32 s) -{ return sub_long_asm(&M.x86.R_EFLG,d,s); } - -void test_byte (u8 d, u8 s) -{ test_byte_asm(&M.x86.R_EFLG,d,s); } - -void test_word (u16 d, u16 s) -{ test_word_asm(&M.x86.R_EFLG,d,s); } - -void test_long (u32 d, u32 s) -{ test_long_asm(&M.x86.R_EFLG,d,s); } - -u8 xor_byte (u8 d, u8 s) -{ return xor_byte_asm(&M.x86.R_EFLG,d,s); } - -u16 xor_word (u16 d, u16 s) -{ return xor_word_asm(&M.x86.R_EFLG,d,s); } - -u32 xor_long (u32 d, u32 s) -{ return xor_long_asm(&M.x86.R_EFLG,d,s); } - -void imul_byte (u8 s) -{ imul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s); } - -void imul_word (u16 s) -{ imul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s); } - -void imul_long (u32 s) -{ imul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); } - -void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) -{ imul_long_asm(&M.x86.R_EFLG,res_lo,res_hi,d,s); } - -void mul_byte (u8 s) -{ mul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s); } - -void mul_word (u16 s) -{ mul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s); } - -void mul_long (u32 s) -{ mul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); } - -void idiv_byte (u8 s) -{ idiv_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s); } - -void idiv_word (u16 s) -{ idiv_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s); } - -void idiv_long (u32 s) -{ idiv_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s); } - -void div_byte (u8 s) -{ div_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s); } - -void div_word (u16 s) -{ div_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s); } - -void div_long (u32 s) -{ div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s); } - -#endif diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/sys.c b/board/MAI/bios_emulator/scitech/src/x86emu/sys.c deleted file mode 100644 index afe58f8..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/sys.c +++ /dev/null @@ -1,658 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: This file includes subroutines which are related to -* programmed I/O and memory access. Included in this module -* are default functions with limited usefulness. For real -* uses these functions will most likely be overriden by the -* user library. -* -****************************************************************************/ - -#include "x86emu.h" -#include "x86emu/regs.h" -#include "x86emu/debug.h" -#include "x86emu/prim_ops.h" -#include - -/*------------------------- Global Variables ------------------------------*/ - -X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ -X86EMU_intrFuncs _X86EMU_intrTab[256]; - -/*----------------------------- Implementation ----------------------------*/ -#ifdef __alpha__ -/* to cope with broken egcs-1.1.2 :-(((( */ - -/* - * inline functions to do unaligned accesses - * from linux/include/asm-alpha/unaligned.h - */ - -/* - * EGCS 1.1 knows about arbitrary unaligned loads. Define some - * packed structures to talk about such things with. - */ - -#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 -struct __una_u64 { unsigned long x __attribute__((packed)); }; -struct __una_u32 { unsigned int x __attribute__((packed)); }; -struct __una_u16 { unsigned short x __attribute__((packed)); }; -#endif - -static __inline__ unsigned long ldq_u(unsigned long * r11) -{ -#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 - const struct __una_u64 *ptr = (const struct __una_u64 *) r11; - return ptr->x; -#else - unsigned long r1,r2; - __asm__("ldq_u %0,%3\n\t" - "ldq_u %1,%4\n\t" - "extql %0,%2,%0\n\t" - "extqh %1,%2,%1" - :"=&r" (r1), "=&r" (r2) - :"r" (r11), - "m" (*r11), - "m" (*(const unsigned long *)(7+(char *) r11))); - return r1 | r2; -#endif -} - -static __inline__ unsigned long ldl_u(unsigned int * r11) -{ -#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 - const struct __una_u32 *ptr = (const struct __una_u32 *) r11; - return ptr->x; -#else - unsigned long r1,r2; - __asm__("ldq_u %0,%3\n\t" - "ldq_u %1,%4\n\t" - "extll %0,%2,%0\n\t" - "extlh %1,%2,%1" - :"=&r" (r1), "=&r" (r2) - :"r" (r11), - "m" (*r11), - "m" (*(const unsigned long *)(3+(char *) r11))); - return r1 | r2; -#endif -} - -static __inline__ unsigned long ldw_u(unsigned short * r11) -{ -#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 - const struct __una_u16 *ptr = (const struct __una_u16 *) r11; - return ptr->x; -#else - unsigned long r1,r2; - __asm__("ldq_u %0,%3\n\t" - "ldq_u %1,%4\n\t" - "extwl %0,%2,%0\n\t" - "extwh %1,%2,%1" - :"=&r" (r1), "=&r" (r2) - :"r" (r11), - "m" (*r11), - "m" (*(const unsigned long *)(1+(char *) r11))); - return r1 | r2; -#endif -} - -/* - * Elemental unaligned stores - */ - -static __inline__ void stq_u(unsigned long r5, unsigned long * r11) -{ -#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 - struct __una_u64 *ptr = (struct __una_u64 *) r11; - ptr->x = r5; -#else - unsigned long r1,r2,r3,r4; - - __asm__("ldq_u %3,%1\n\t" - "ldq_u %2,%0\n\t" - "insqh %6,%7,%5\n\t" - "insql %6,%7,%4\n\t" - "mskqh %3,%7,%3\n\t" - "mskql %2,%7,%2\n\t" - "bis %3,%5,%3\n\t" - "bis %2,%4,%2\n\t" - "stq_u %3,%1\n\t" - "stq_u %2,%0" - :"=m" (*r11), - "=m" (*(unsigned long *)(7+(char *) r11)), - "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) - :"r" (r5), "r" (r11)); -#endif -} - -static __inline__ void stl_u(unsigned long r5, unsigned int * r11) -{ -#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 - struct __una_u32 *ptr = (struct __una_u32 *) r11; - ptr->x = r5; -#else - unsigned long r1,r2,r3,r4; - - __asm__("ldq_u %3,%1\n\t" - "ldq_u %2,%0\n\t" - "inslh %6,%7,%5\n\t" - "insll %6,%7,%4\n\t" - "msklh %3,%7,%3\n\t" - "mskll %2,%7,%2\n\t" - "bis %3,%5,%3\n\t" - "bis %2,%4,%2\n\t" - "stq_u %3,%1\n\t" - "stq_u %2,%0" - :"=m" (*r11), - "=m" (*(unsigned long *)(3+(char *) r11)), - "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) - :"r" (r5), "r" (r11)); -#endif -} - -static __inline__ void stw_u(unsigned long r5, unsigned short * r11) -{ -#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 - struct __una_u16 *ptr = (struct __una_u16 *) r11; - ptr->x = r5; -#else - unsigned long r1,r2,r3,r4; - - __asm__("ldq_u %3,%1\n\t" - "ldq_u %2,%0\n\t" - "inswh %6,%7,%5\n\t" - "inswl %6,%7,%4\n\t" - "mskwh %3,%7,%3\n\t" - "mskwl %2,%7,%2\n\t" - "bis %3,%5,%3\n\t" - "bis %2,%4,%2\n\t" - "stq_u %3,%1\n\t" - "stq_u %2,%0" - :"=m" (*r11), - "=m" (*(unsigned long *)(1+(char *) r11)), - "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) - :"r" (r5), "r" (r11)); -#endif -} - -#elif defined (__ia64__) -/* - * EGCS 1.1 knows about arbitrary unaligned loads. Define some - * packed structures to talk about such things with. - */ -struct __una_u64 { unsigned long x __attribute__((packed)); }; -struct __una_u32 { unsigned int x __attribute__((packed)); }; -struct __una_u16 { unsigned short x __attribute__((packed)); }; - -static __inline__ unsigned long -__uldq (const unsigned long * r11) -{ - const struct __una_u64 *ptr = (const struct __una_u64 *) r11; - return ptr->x; -} - -static __inline__ unsigned long -uldl (const unsigned int * r11) -{ - const struct __una_u32 *ptr = (const struct __una_u32 *) r11; - return ptr->x; -} - -static __inline__ unsigned long -uldw (const unsigned short * r11) -{ - const struct __una_u16 *ptr = (const struct __una_u16 *) r11; - return ptr->x; -} - -static __inline__ void -ustq (unsigned long r5, unsigned long * r11) -{ - struct __una_u64 *ptr = (struct __una_u64 *) r11; - ptr->x = r5; -} - -static __inline__ void -ustl (unsigned long r5, unsigned int * r11) -{ - struct __una_u32 *ptr = (struct __una_u32 *) r11; - ptr->x = r5; -} - -static __inline__ void -ustw (unsigned long r5, unsigned short * r11) -{ - struct __una_u16 *ptr = (struct __una_u16 *) r11; - ptr->x = r5; -} - -#endif - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read - -RETURNS: -Byte value read from emulator memory. - -REMARKS: -Reads a byte value from the emulator memory. -****************************************************************************/ -u8 X86API rdb( - u32 addr) -{ - u8 val; - - if (addr > M.mem_size - 1) { - DB(printk("mem_read: address %#lx out of range!\n", addr);) - HALT_SYS(); - } - val = *(u8*)(M.mem_base + addr); -DB( if (DEBUG_MEM_TRACE()) - printk("%#08x 1 -> %#x\n", addr, val);) - return val; -} - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read - -RETURNS: -Word value read from emulator memory. - -REMARKS: -Reads a word value from the emulator memory. -****************************************************************************/ -u16 X86API rdw( - u32 addr) -{ - u16 val = 0; - - if (addr > M.mem_size - 2) { - DB(printk("mem_read: address %#lx out of range!\n", addr);) - HALT_SYS(); - } -#ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - val = (*(u8*)(M.mem_base + addr) | - (*(u8*)(M.mem_base + addr + 1) << 8)); - } - else -#endif -#ifdef __alpha__ - val = ldw_u((u16*)(M.mem_base + addr)); -#elif defined (__ia64__) - val = uldw((u16*)(M.mem_base + addr)); -#else - val = *(u16*)(M.mem_base + addr); -#endif - DB( if (DEBUG_MEM_TRACE()) - printk("%#08x 2 -> %#x\n", addr, val);) - return val; -} - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read - -RETURNS: -Long value read from emulator memory. -REMARKS: -Reads a long value from the emulator memory. -****************************************************************************/ -u32 X86API rdl( - u32 addr) -{ - u32 val = 0; - - if (addr > M.mem_size - 4) { - DB(printk("mem_read: address %#lx out of range!\n", addr);) - HALT_SYS(); - } -#ifdef __BIG_ENDIAN__ - if (addr & 0x3) { - val = (*(u8*)(M.mem_base + addr + 0) | - (*(u8*)(M.mem_base + addr + 1) << 8) | - (*(u8*)(M.mem_base + addr + 2) << 16) | - (*(u8*)(M.mem_base + addr + 3) << 24)); - } - else -#endif -#ifdef __alpha__ - val = ldl_u((u32*)(M.mem_base + addr)); -#elif defined (__ia64__) - val = uldl((u32*)(M.mem_base + addr)); -#else - val = *(u32*)(M.mem_base + addr); -#endif -DB( if (DEBUG_MEM_TRACE()) - printk("%#08x 4 -> %#x\n", addr, val);) - return val; -} - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read -val - Value to store - -REMARKS: -Writes a byte value to emulator memory. -****************************************************************************/ -void X86API wrb( - u32 addr, - u8 val) -{ -DB( if (DEBUG_MEM_TRACE()) - printk("%#08x 1 <- %#x\n", addr, val);) - if (addr > M.mem_size - 1) { - DB(printk("mem_write: address %#lx out of range!\n", addr);) - HALT_SYS(); - } - *(u8*)(M.mem_base + addr) = val; -} - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read -val - Value to store - -REMARKS: -Writes a word value to emulator memory. -****************************************************************************/ -void X86API wrw( - u32 addr, - u16 val) -{ -DB( if (DEBUG_MEM_TRACE()) - printk("%#08x 2 <- %#x\n", addr, val);) - if (addr > M.mem_size - 2) { - DB(printk("mem_write: address %#lx out of range!\n", addr);) - HALT_SYS(); - } -#ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; - *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; - } - else -#endif -#ifdef __alpha__ - stw_u(val,(u16*)(M.mem_base + addr)); -#elif defined (__ia64__) - ustw(val,(u16*)(M.mem_base + addr)); -#else - *(u16*)(M.mem_base + addr) = val; -#endif -} - -/**************************************************************************** -PARAMETERS: -addr - Emulator memory address to read -val - Value to store - -REMARKS: -Writes a long value to emulator memory. -****************************************************************************/ -void X86API wrl( - u32 addr, - u32 val) -{ -DB( if (DEBUG_MEM_TRACE()) - printk("%#08x 4 <- %#x\n", addr, val);) - if (addr > M.mem_size - 4) { - DB(printk("mem_write: address %#lx out of range!\n", addr);) - HALT_SYS(); - } -#ifdef __BIG_ENDIAN__ - if (addr & 0x1) { - *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; - *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; - *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; - *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; - } - else -#endif -#ifdef __alpha__ - stl_u(val,(u32*)(M.mem_base + addr)); -#elif defined (__ia64__) - ustl(val,(u32*)(M.mem_base + addr)); -#else - *(u32*)(M.mem_base + addr) = val; -#endif -} - -/**************************************************************************** -PARAMETERS: -addr - PIO address to read -RETURN: -0 -REMARKS: -Default PIO byte read function. Doesn't perform real inb. -****************************************************************************/ -static u8 X86API p_inb( - X86EMU_pioAddr addr) -{ -DB( if (DEBUG_IO_TRACE()) - printk("inb %#04x \n", addr);) - return 0; -} - -/**************************************************************************** -PARAMETERS: -addr - PIO address to read -RETURN: -0 -REMARKS: -Default PIO word read function. Doesn't perform real inw. -****************************************************************************/ -static u16 X86API p_inw( - X86EMU_pioAddr addr) -{ -DB( if (DEBUG_IO_TRACE()) - printk("inw %#04x \n", addr);) - return 0; -} - -/**************************************************************************** -PARAMETERS: -addr - PIO address to read -RETURN: -0 -REMARKS: -Default PIO long read function. Doesn't perform real inl. -****************************************************************************/ -static u32 X86API p_inl( - X86EMU_pioAddr addr) -{ -DB( if (DEBUG_IO_TRACE()) - printk("inl %#04x \n", addr);) - return 0; -} - -/**************************************************************************** -PARAMETERS: -addr - PIO address to write -val - Value to store -REMARKS: -Default PIO byte write function. Doesn't perform real outb. -****************************************************************************/ -static void X86API p_outb( - X86EMU_pioAddr addr, - u8 val) -{ -DB( if (DEBUG_IO_TRACE()) - printk("outb %#02x -> %#04x \n", val, addr);) - return; -} - -/**************************************************************************** -PARAMETERS: -addr - PIO address to write -val - Value to store -REMARKS: -Default PIO word write function. Doesn't perform real outw. -****************************************************************************/ -static void X86API p_outw( - X86EMU_pioAddr addr, - u16 val) -{ -DB( if (DEBUG_IO_TRACE()) - printk("outw %#04x -> %#04x \n", val, addr);) - return; -} - -/**************************************************************************** -PARAMETERS: -addr - PIO address to write -val - Value to store -REMARKS: -Default PIO ;ong write function. Doesn't perform real outl. -****************************************************************************/ -static void X86API p_outl( - X86EMU_pioAddr addr, - u32 val) -{ -DB( if (DEBUG_IO_TRACE()) - printk("outl %#08x -> %#04x \n", val, addr);) - return; -} - -/*------------------------- Global Variables ------------------------------*/ - -u8 (X86APIP sys_rdb)(u32 addr) = rdb; -u16 (X86APIP sys_rdw)(u32 addr) = rdw; -u32 (X86APIP sys_rdl)(u32 addr) = rdl; -void (X86APIP sys_wrb)(u32 addr,u8 val) = wrb; -void (X86APIP sys_wrw)(u32 addr,u16 val) = wrw; -void (X86APIP sys_wrl)(u32 addr,u32 val) = wrl; -u8 (X86APIP sys_inb)(X86EMU_pioAddr addr) = p_inb; -u16 (X86APIP sys_inw)(X86EMU_pioAddr addr) = p_inw; -u32 (X86APIP sys_inl)(X86EMU_pioAddr addr) = p_inl; -void (X86APIP sys_outb)(X86EMU_pioAddr addr, u8 val) = p_outb; -void (X86APIP sys_outw)(X86EMU_pioAddr addr, u16 val) = p_outw; -void (X86APIP sys_outl)(X86EMU_pioAddr addr, u32 val) = p_outl; - -/*----------------------------- Setup -------------------------------------*/ - -/**************************************************************************** -PARAMETERS: -funcs - New memory function pointers to make active - -REMARKS: -This function is used to set the pointers to functions which access -memory space, allowing the user application to override these functions -and hook them out as necessary for their application. -****************************************************************************/ -void X86EMU_setupMemFuncs( - X86EMU_memFuncs *funcs) -{ - sys_rdb = funcs->rdb; - sys_rdw = funcs->rdw; - sys_rdl = funcs->rdl; - sys_wrb = funcs->wrb; - sys_wrw = funcs->wrw; - sys_wrl = funcs->wrl; -} - -/**************************************************************************** -PARAMETERS: -funcs - New programmed I/O function pointers to make active - -REMARKS: -This function is used to set the pointers to functions which access -I/O space, allowing the user application to override these functions -and hook them out as necessary for their application. -****************************************************************************/ -void X86EMU_setupPioFuncs( - X86EMU_pioFuncs *funcs) -{ - sys_inb = funcs->inb; - sys_inw = funcs->inw; - sys_inl = funcs->inl; - sys_outb = funcs->outb; - sys_outw = funcs->outw; - sys_outl = funcs->outl; -} - -/**************************************************************************** -PARAMETERS: -funcs - New interrupt vector table to make active - -REMARKS: -This function is used to set the pointers to functions which handle -interrupt processing in the emulator, allowing the user application to -hook interrupts as necessary for their application. Any interrupts that -are not hooked by the user application, and reflected and handled internally -in the emulator via the interrupt vector table. This allows the application -to get control when the code being emulated executes specific software -interrupts. -****************************************************************************/ -void X86EMU_setupIntrFuncs( - X86EMU_intrFuncs funcs[]) -{ - int i; - - for (i=0; i < 256; i++) - _X86EMU_intrTab[i] = NULL; - if (funcs) { - for (i = 0; i < 256; i++) - _X86EMU_intrTab[i] = funcs[i]; - } -} - -/**************************************************************************** -PARAMETERS: -int - New software interrupt to prepare for - -REMARKS: -This function is used to set up the emulator state to exceute a software -interrupt. This can be used by the user application code to allow an -interrupt to be hooked, examined and then reflected back to the emulator -so that the code in the emulator will continue processing the software -interrupt as per normal. This essentially allows system code to actively -hook and handle certain software interrupts as necessary. -****************************************************************************/ -void X86EMU_prepareForInt( - int num) -{ - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(num * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(num * 4); - M.x86.intr = 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/validate.c b/board/MAI/bios_emulator/scitech/src/x86emu/validate.c deleted file mode 100644 index c951301..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/validate.c +++ /dev/null @@ -1,765 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: Watcom C 10.6 or later -* Environment: 32-bit DOS -* Developer: Kendall Bennett -* -* Description: Program to validate the x86 emulator library for -* correctness. We run the emulator primitive operations -* functions against the real x86 CPU, and compare the result -* and flags to ensure correctness. -* -* We use inline assembler to compile and build this program. -* -****************************************************************************/ - -#include -#include -#include -#include -#include "x86emu.h" -#include "x86emu/prim_asm.h" - -/*-------------------------- Implementation -------------------------------*/ - -#define true 1 -#define false 0 - -#define ALL_FLAGS (F_CF | F_PF | F_AF | F_ZF | F_SF | F_OF) - -#define VAL_START_BINARY(parm_type,res_type,dmax,smax,dincr,sincr) \ -{ \ - parm_type d,s; \ - res_type r,r_asm; \ - ulong flags,inflags; \ - int f,failed = false; \ - char buf1[80],buf2[80]; \ - for (d = 0; d < dmax; d += dincr) { \ - for (s = 0; s < smax; s += sincr) { \ - M.x86.R_EFLG = inflags = flags = def_flags; \ - for (f = 0; f < 2; f++) { - -#define VAL_TEST_BINARY(name) \ - r_asm = name##_asm(&flags,d,s); \ - r = name(d,s); \ - if (r != r_asm || M.x86.R_EFLG != flags) \ - failed = true; \ - if (failed || trace) { - -#define VAL_TEST_BINARY_VOID(name) \ - name##_asm(&flags,d,s); \ - name(d,s); \ - r = r_asm = 0; \ - if (M.x86.R_EFLG != flags) \ - failed = true; \ - if (failed || trace) { - -#define VAL_FAIL_BYTE_BYTE_BINARY(name) \ - if (failed) \ - printk("fail\n"); \ - printk("0x%02X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ - r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%02X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ - r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); - -#define VAL_FAIL_WORD_WORD_BINARY(name) \ - if (failed) \ - printk("fail\n"); \ - printk("0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ - r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ - r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); - -#define VAL_FAIL_LONG_LONG_BINARY(name) \ - if (failed) \ - printk("fail\n"); \ - printk("0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ - r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ - r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); - -#define VAL_END_BINARY() \ - } \ - M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (!failed) \ - printk("passed\n"); \ -} - -#define VAL_BYTE_BYTE_BINARY(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_BINARY(u8,u8,0xFF,0xFF,1,1) \ - VAL_TEST_BINARY(name) \ - VAL_FAIL_BYTE_BYTE_BINARY(name) \ - VAL_END_BINARY() - -#define VAL_WORD_WORD_BINARY(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_BINARY(u16,u16,0xFF00,0xFF00,0x100,0x100) \ - VAL_TEST_BINARY(name) \ - VAL_FAIL_WORD_WORD_BINARY(name) \ - VAL_END_BINARY() - -#define VAL_LONG_LONG_BINARY(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_BINARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000) \ - VAL_TEST_BINARY(name) \ - VAL_FAIL_LONG_LONG_BINARY(name) \ - VAL_END_BINARY() - -#define VAL_VOID_BYTE_BINARY(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_BINARY(u8,u8,0xFF,0xFF,1,1) \ - VAL_TEST_BINARY_VOID(name) \ - VAL_FAIL_BYTE_BYTE_BINARY(name) \ - VAL_END_BINARY() - -#define VAL_VOID_WORD_BINARY(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_BINARY(u16,u16,0xFF00,0xFF00,0x100,0x100) \ - VAL_TEST_BINARY_VOID(name) \ - VAL_FAIL_WORD_WORD_BINARY(name) \ - VAL_END_BINARY() - -#define VAL_VOID_LONG_BINARY(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_BINARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000) \ - VAL_TEST_BINARY_VOID(name) \ - VAL_FAIL_LONG_LONG_BINARY(name) \ - VAL_END_BINARY() - -#define VAL_BYTE_ROTATE(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_BINARY(u8,u8,0xFF,8,1,1) \ - VAL_TEST_BINARY(name) \ - VAL_FAIL_BYTE_BYTE_BINARY(name) \ - VAL_END_BINARY() - -#define VAL_WORD_ROTATE(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_BINARY(u16,u16,0xFF00,16,0x100,1) \ - VAL_TEST_BINARY(name) \ - VAL_FAIL_WORD_WORD_BINARY(name) \ - VAL_END_BINARY() - -#define VAL_LONG_ROTATE(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_BINARY(u32,u32,0xFF000000,32,0x1000000,1) \ - VAL_TEST_BINARY(name) \ - VAL_FAIL_LONG_LONG_BINARY(name) \ - VAL_END_BINARY() - -#define VAL_START_TERNARY(parm_type,res_type,dmax,smax,dincr,sincr,maxshift)\ -{ \ - parm_type d,s; \ - res_type r,r_asm; \ - u8 shift; \ - u32 flags,inflags; \ - int f,failed = false; \ - char buf1[80],buf2[80]; \ - for (d = 0; d < dmax; d += dincr) { \ - for (s = 0; s < smax; s += sincr) { \ - for (shift = 0; shift < maxshift; shift += 1) { \ - M.x86.R_EFLG = inflags = flags = def_flags; \ - for (f = 0; f < 2; f++) { - -#define VAL_TEST_TERNARY(name) \ - r_asm = name##_asm(&flags,d,s,shift); \ - r = name(d,s,shift); \ - if (r != r_asm || M.x86.R_EFLG != flags) \ - failed = true; \ - if (failed || trace) { - -#define VAL_FAIL_WORD_WORD_TERNARY(name) \ - if (failed) \ - printk("fail\n"); \ - printk("0x%04X = %-15s(0x%04X,0x%04X,%d), flags = %s -> %s\n", \ - r, #name, d, s, shift, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%04X = %-15s(0x%04X,0x%04X,%d), flags = %s -> %s\n", \ - r_asm, #name"_asm", d, s, shift, print_flags(buf1,inflags), print_flags(buf2,flags)); - -#define VAL_FAIL_LONG_LONG_TERNARY(name) \ - if (failed) \ - printk("fail\n"); \ - printk("0x%08X = %-15s(0x%08X,0x%08X,%d), flags = %s -> %s\n", \ - r, #name, d, s, shift, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%08X = %-15s(0x%08X,0x%08X,%d), flags = %s -> %s\n", \ - r_asm, #name"_asm", d, s, shift, print_flags(buf1,inflags), print_flags(buf2,flags)); - -#define VAL_END_TERNARY() \ - } \ - M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (!failed) \ - printk("passed\n"); \ -} - -#define VAL_WORD_ROTATE_DBL(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_TERNARY(u16,u16,0xFF00,0xFF00,0x100,0x100,16) \ - VAL_TEST_TERNARY(name) \ - VAL_FAIL_WORD_WORD_TERNARY(name) \ - VAL_END_TERNARY() - -#define VAL_LONG_ROTATE_DBL(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_TERNARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000,32) \ - VAL_TEST_TERNARY(name) \ - VAL_FAIL_LONG_LONG_TERNARY(name) \ - VAL_END_TERNARY() - -#define VAL_START_UNARY(parm_type,max,incr) \ -{ \ - parm_type d,r,r_asm; \ - u32 flags,inflags; \ - int f,failed = false; \ - char buf1[80],buf2[80]; \ - for (d = 0; d < max; d += incr) { \ - M.x86.R_EFLG = inflags = flags = def_flags; \ - for (f = 0; f < 2; f++) { - -#define VAL_TEST_UNARY(name) \ - r_asm = name##_asm(&flags,d); \ - r = name(d); \ - if (r != r_asm || M.x86.R_EFLG != flags) { \ - failed = true; - -#define VAL_FAIL_BYTE_UNARY(name) \ - printk("fail\n"); \ - printk("0x%02X = %-15s(0x%02X), flags = %s -> %s\n", \ - r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%02X = %-15s(0x%02X), flags = %s -> %s\n", \ - r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); - -#define VAL_FAIL_WORD_UNARY(name) \ - printk("fail\n"); \ - printk("0x%04X = %-15s(0x%04X), flags = %s -> %s\n", \ - r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%04X = %-15s(0x%04X), flags = %s -> %s\n", \ - r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); - -#define VAL_FAIL_LONG_UNARY(name) \ - printk("fail\n"); \ - printk("0x%08X = %-15s(0x%08X), flags = %s -> %s\n", \ - r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%08X = %-15s(0x%08X), flags = %s -> %s\n", \ - r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); - -#define VAL_END_UNARY() \ - } \ - M.x86.R_EFLG = inflags = flags = def_flags | ALL_FLAGS; \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (!failed) \ - printk("passed\n"); \ -} - -#define VAL_BYTE_UNARY(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_UNARY(u8,0xFF,0x1) \ - VAL_TEST_UNARY(name) \ - VAL_FAIL_BYTE_UNARY(name) \ - VAL_END_UNARY() - -#define VAL_WORD_UNARY(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_UNARY(u16,0xFF00,0x100) \ - VAL_TEST_UNARY(name) \ - VAL_FAIL_WORD_UNARY(name) \ - VAL_END_UNARY() - -#define VAL_WORD_BYTE_UNARY(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_UNARY(u16,0xFF,0x1) \ - VAL_TEST_UNARY(name) \ - VAL_FAIL_WORD_UNARY(name) \ - VAL_END_UNARY() - -#define VAL_LONG_UNARY(name) \ - printk("Validating %s ... ", #name); \ - VAL_START_UNARY(u32,0xFF000000,0x1000000) \ - VAL_TEST_UNARY(name) \ - VAL_FAIL_LONG_UNARY(name) \ - VAL_END_UNARY() - -#define VAL_BYTE_MUL(name) \ - printk("Validating %s ... ", #name); \ -{ \ - u8 d,s; \ - u16 r,r_asm; \ - u32 flags,inflags; \ - int f,failed = false; \ - char buf1[80],buf2[80]; \ - for (d = 0; d < 0xFF; d += 1) { \ - for (s = 0; s < 0xFF; s += 1) { \ - M.x86.R_EFLG = inflags = flags = def_flags; \ - for (f = 0; f < 2; f++) { \ - name##_asm(&flags,&r_asm,d,s); \ - M.x86.R_AL = d; \ - name(s); \ - r = M.x86.R_AX; \ - if (r != r_asm || M.x86.R_EFLG != flags) \ - failed = true; \ - if (failed || trace) { \ - if (failed) \ - printk("fail\n"); \ - printk("0x%04X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ - r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%04X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ - r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ - } \ - M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (!failed) \ - printk("passed\n"); \ -} - -#define VAL_WORD_MUL(name) \ - printk("Validating %s ... ", #name); \ -{ \ - u16 d,s; \ - u16 r_lo,r_asm_lo; \ - u16 r_hi,r_asm_hi; \ - u32 flags,inflags; \ - int f,failed = false; \ - char buf1[80],buf2[80]; \ - for (d = 0; d < 0xFF00; d += 0x100) { \ - for (s = 0; s < 0xFF00; s += 0x100) { \ - M.x86.R_EFLG = inflags = flags = def_flags; \ - for (f = 0; f < 2; f++) { \ - name##_asm(&flags,&r_asm_lo,&r_asm_hi,d,s); \ - M.x86.R_AX = d; \ - name(s); \ - r_lo = M.x86.R_AX; \ - r_hi = M.x86.R_DX; \ - if (r_lo != r_asm_lo || r_hi != r_asm_hi || M.x86.R_EFLG != flags)\ - failed = true; \ - if (failed || trace) { \ - if (failed) \ - printk("fail\n"); \ - printk("0x%04X:0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ - r_hi,r_lo, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%04X:0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ - r_asm_hi,r_asm_lo, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ - } \ - M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (!failed) \ - printk("passed\n"); \ -} - -#define VAL_LONG_MUL(name) \ - printk("Validating %s ... ", #name); \ -{ \ - u32 d,s; \ - u32 r_lo,r_asm_lo; \ - u32 r_hi,r_asm_hi; \ - u32 flags,inflags; \ - int f,failed = false; \ - char buf1[80],buf2[80]; \ - for (d = 0; d < 0xFF000000; d += 0x1000000) { \ - for (s = 0; s < 0xFF000000; s += 0x1000000) { \ - M.x86.R_EFLG = inflags = flags = def_flags; \ - for (f = 0; f < 2; f++) { \ - name##_asm(&flags,&r_asm_lo,&r_asm_hi,d,s); \ - M.x86.R_EAX = d; \ - name(s); \ - r_lo = M.x86.R_EAX; \ - r_hi = M.x86.R_EDX; \ - if (r_lo != r_asm_lo || r_hi != r_asm_hi || M.x86.R_EFLG != flags)\ - failed = true; \ - if (failed || trace) { \ - if (failed) \ - printk("fail\n"); \ - printk("0x%08X:0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ - r_hi,r_lo, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%08X:0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ - r_asm_hi,r_asm_lo, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ - } \ - M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (!failed) \ - printk("passed\n"); \ -} - -#define VAL_BYTE_DIV(name) \ - printk("Validating %s ... ", #name); \ -{ \ - u16 d,s; \ - u8 r_quot,r_rem,r_asm_quot,r_asm_rem; \ - u32 flags,inflags; \ - int f,failed = false; \ - char buf1[80],buf2[80]; \ - for (d = 0; d < 0xFF00; d += 0x100) { \ - for (s = 1; s < 0xFF; s += 1) { \ - M.x86.R_EFLG = inflags = flags = def_flags; \ - for (f = 0; f < 2; f++) { \ - M.x86.intr = 0; \ - M.x86.R_AX = d; \ - name(s); \ - r_quot = M.x86.R_AL; \ - r_rem = M.x86.R_AH; \ - if (M.x86.intr & INTR_SYNCH) \ - continue; \ - name##_asm(&flags,&r_asm_quot,&r_asm_rem,d,s); \ - if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ - failed = true; \ - if (failed || trace) { \ - if (failed) \ - printk("fail\n"); \ - printk("0x%02X:0x%02X = %-15s(0x%04X,0x%02X), flags = %s -> %s\n", \ - r_quot, r_rem, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%02X:0x%02X = %-15s(0x%04X,0x%02X), flags = %s -> %s\n", \ - r_asm_quot, r_asm_rem, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ - } \ - M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (!failed) \ - printk("passed\n"); \ -} - -#define VAL_WORD_DIV(name) \ - printk("Validating %s ... ", #name); \ -{ \ - u32 d,s; \ - u16 r_quot,r_rem,r_asm_quot,r_asm_rem; \ - u32 flags,inflags; \ - int f,failed = false; \ - char buf1[80],buf2[80]; \ - for (d = 0; d < 0xFF000000; d += 0x1000000) { \ - for (s = 0x100; s < 0xFF00; s += 0x100) { \ - M.x86.R_EFLG = inflags = flags = def_flags; \ - for (f = 0; f < 2; f++) { \ - M.x86.intr = 0; \ - M.x86.R_AX = d & 0xFFFF; \ - M.x86.R_DX = d >> 16; \ - name(s); \ - r_quot = M.x86.R_AX; \ - r_rem = M.x86.R_DX; \ - if (M.x86.intr & INTR_SYNCH) \ - continue; \ - name##_asm(&flags,&r_asm_quot,&r_asm_rem,d & 0xFFFF,d >> 16,s);\ - if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ - failed = true; \ - if (failed || trace) { \ - if (failed) \ - printk("fail\n"); \ - printk("0x%04X:0x%04X = %-15s(0x%08X,0x%04X), flags = %s -> %s\n", \ - r_quot, r_rem, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%04X:0x%04X = %-15s(0x%08X,0x%04X), flags = %s -> %s\n", \ - r_asm_quot, r_asm_rem, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ - } \ - M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (!failed) \ - printk("passed\n"); \ -} - -#define VAL_LONG_DIV(name) \ - printk("Validating %s ... ", #name); \ -{ \ - u32 d,s; \ - u32 r_quot,r_rem,r_asm_quot,r_asm_rem; \ - u32 flags,inflags; \ - int f,failed = false; \ - char buf1[80],buf2[80]; \ - for (d = 0; d < 0xFF000000; d += 0x1000000) { \ - for (s = 0x100; s < 0xFF00; s += 0x100) { \ - M.x86.R_EFLG = inflags = flags = def_flags; \ - for (f = 0; f < 2; f++) { \ - M.x86.intr = 0; \ - M.x86.R_EAX = d; \ - M.x86.R_EDX = 0; \ - name(s); \ - r_quot = M.x86.R_EAX; \ - r_rem = M.x86.R_EDX; \ - if (M.x86.intr & INTR_SYNCH) \ - continue; \ - name##_asm(&flags,&r_asm_quot,&r_asm_rem,d,0,s); \ - if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ - failed = true; \ - if (failed || trace) { \ - if (failed) \ - printk("fail\n"); \ - printk("0x%08X:0x%08X = %-15s(0x%08X:0x%08X,0x%08X), flags = %s -> %s\n", \ - r_quot, r_rem, #name, 0, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ - printk("0x%08X:0x%08X = %-15s(0x%08X:0x%08X,0x%08X), flags = %s -> %s\n", \ - r_asm_quot, r_asm_rem, #name"_asm", 0, d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ - } \ - M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (failed) \ - break; \ - } \ - if (!failed) \ - printk("passed\n"); \ -} - -void printk(const char *fmt, ...) -{ - va_list argptr; - va_start(argptr, fmt); - vfprintf(stdout, fmt, argptr); - fflush(stdout); - va_end(argptr); -} - -char * print_flags(char *buf,ulong flags) -{ - char *separator = ""; - - buf[0] = 0; - if (flags & F_CF) { - strcat(buf,separator); - strcat(buf,"CF"); - separator = ","; - } - if (flags & F_PF) { - strcat(buf,separator); - strcat(buf,"PF"); - separator = ","; - } - if (flags & F_AF) { - strcat(buf,separator); - strcat(buf,"AF"); - separator = ","; - } - if (flags & F_ZF) { - strcat(buf,separator); - strcat(buf,"ZF"); - separator = ","; - } - if (flags & F_SF) { - strcat(buf,separator); - strcat(buf,"SF"); - separator = ","; - } - if (flags & F_OF) { - strcat(buf,separator); - strcat(buf,"OF"); - separator = ","; - } - if (separator[0] == 0) - strcpy(buf,"None"); - return buf; -} - -int main(int argc) -{ - ulong def_flags; - int trace = false; - - if (argc > 1) - trace = true; - memset(&M, 0, sizeof(M)); - def_flags = get_flags_asm() & ~ALL_FLAGS; - - VAL_WORD_UNARY(aaa_word); - VAL_WORD_UNARY(aas_word); - - VAL_WORD_UNARY(aad_word); - VAL_WORD_UNARY(aam_word); - - VAL_BYTE_BYTE_BINARY(adc_byte); - VAL_WORD_WORD_BINARY(adc_word); - VAL_LONG_LONG_BINARY(adc_long); - - VAL_BYTE_BYTE_BINARY(add_byte); - VAL_WORD_WORD_BINARY(add_word); - VAL_LONG_LONG_BINARY(add_long); - - VAL_BYTE_BYTE_BINARY(and_byte); - VAL_WORD_WORD_BINARY(and_word); - VAL_LONG_LONG_BINARY(and_long); - - VAL_BYTE_BYTE_BINARY(cmp_byte); - VAL_WORD_WORD_BINARY(cmp_word); - VAL_LONG_LONG_BINARY(cmp_long); - - VAL_BYTE_UNARY(daa_byte); - VAL_BYTE_UNARY(das_byte); /* Fails for 0x9A (out of range anyway) */ - - VAL_BYTE_UNARY(dec_byte); - VAL_WORD_UNARY(dec_word); - VAL_LONG_UNARY(dec_long); - - VAL_BYTE_UNARY(inc_byte); - VAL_WORD_UNARY(inc_word); - VAL_LONG_UNARY(inc_long); - - VAL_BYTE_BYTE_BINARY(or_byte); - VAL_WORD_WORD_BINARY(or_word); - VAL_LONG_LONG_BINARY(or_long); - - VAL_BYTE_UNARY(neg_byte); - VAL_WORD_UNARY(neg_word); - VAL_LONG_UNARY(neg_long); - - VAL_BYTE_UNARY(not_byte); - VAL_WORD_UNARY(not_word); - VAL_LONG_UNARY(not_long); - - VAL_BYTE_ROTATE(rcl_byte); - VAL_WORD_ROTATE(rcl_word); - VAL_LONG_ROTATE(rcl_long); - - VAL_BYTE_ROTATE(rcr_byte); - VAL_WORD_ROTATE(rcr_word); - VAL_LONG_ROTATE(rcr_long); - - VAL_BYTE_ROTATE(rol_byte); - VAL_WORD_ROTATE(rol_word); - VAL_LONG_ROTATE(rol_long); - - VAL_BYTE_ROTATE(ror_byte); - VAL_WORD_ROTATE(ror_word); - VAL_LONG_ROTATE(ror_long); - - VAL_BYTE_ROTATE(shl_byte); - VAL_WORD_ROTATE(shl_word); - VAL_LONG_ROTATE(shl_long); - - VAL_BYTE_ROTATE(shr_byte); - VAL_WORD_ROTATE(shr_word); - VAL_LONG_ROTATE(shr_long); - - VAL_BYTE_ROTATE(sar_byte); - VAL_WORD_ROTATE(sar_word); - VAL_LONG_ROTATE(sar_long); - - VAL_WORD_ROTATE_DBL(shld_word); - VAL_LONG_ROTATE_DBL(shld_long); - - VAL_WORD_ROTATE_DBL(shrd_word); - VAL_LONG_ROTATE_DBL(shrd_long); - - VAL_BYTE_BYTE_BINARY(sbb_byte); - VAL_WORD_WORD_BINARY(sbb_word); - VAL_LONG_LONG_BINARY(sbb_long); - - VAL_BYTE_BYTE_BINARY(sub_byte); - VAL_WORD_WORD_BINARY(sub_word); - VAL_LONG_LONG_BINARY(sub_long); - - VAL_BYTE_BYTE_BINARY(xor_byte); - VAL_WORD_WORD_BINARY(xor_word); - VAL_LONG_LONG_BINARY(xor_long); - - VAL_VOID_BYTE_BINARY(test_byte); - VAL_VOID_WORD_BINARY(test_word); - VAL_VOID_LONG_BINARY(test_long); - - VAL_BYTE_MUL(imul_byte); - VAL_WORD_MUL(imul_word); - VAL_LONG_MUL(imul_long); - - VAL_BYTE_MUL(mul_byte); - VAL_WORD_MUL(mul_word); - VAL_LONG_MUL(mul_long); - - VAL_BYTE_DIV(idiv_byte); - VAL_WORD_DIV(idiv_word); - VAL_LONG_DIV(idiv_long); - - VAL_BYTE_DIV(div_byte); - VAL_WORD_DIV(div_word); - VAL_LONG_DIV(div_long); - - return 0; -} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h deleted file mode 100644 index 9a4a096..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h +++ /dev/null @@ -1,210 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Header file for debug definitions. -* -****************************************************************************/ - -#ifndef __X86EMU_DEBUG_H -#define __X86EMU_DEBUG_H - -/*---------------------- Macros and type definitions ----------------------*/ - -/* checks to be enabled for "runtime" */ - -#define CHECK_IP_FETCH_F 0x1 -#define CHECK_SP_ACCESS_F 0x2 -#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ -#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ - -#ifdef DEBUG -# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) -# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) -# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) -# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) -#else -# define CHECK_IP_FETCH() -# define CHECK_SP_ACCESS() -# define CHECK_MEM_ACCESS() -# define CHECK_DATA_ACCESS() -#endif - -#ifdef DEBUG -# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) -# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) -# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) -# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) -# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) -# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) -# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) -# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_CS_IP) - -# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) -# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) -# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) -# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) -# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) -# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) -# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) -# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) -# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) -#else -# define DEBUG_INSTRUMENT() 0 -# define DEBUG_DECODE() 0 -# define DEBUG_TRACE() 0 -# define DEBUG_STEP() 0 -# define DEBUG_DISASSEMBLE() 0 -# define DEBUG_BREAK() 0 -# define DEBUG_SVC() 0 -# define DEBUG_SAVE_IP_CS() 0 -# define DEBUG_FS() 0 -# define DEBUG_PROC() 0 -# define DEBUG_SYSINT() 0 -# define DEBUG_TRACECALL() 0 -# define DEBUG_TRACECALLREGS() 0 -# define DEBUG_SYS() 0 -# define DEBUG_MEM_TRACE() 0 -# define DEBUG_IO_TRACE() 0 -# define DEBUG_DECODE_NOPRINT() 0 -#endif - -#ifdef DEBUG - -# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ - x86emu_decode_printf(x) -# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ - x86emu_decode_printf2(x,y) - -/* - * The following allow us to look at the bytes of an instruction. The - * first INCR_INSTRN_LEN, is called everytime bytes are consumed in - * the decoding process. The SAVE_IP_CS is called initially when the - * major opcode of the instruction is accessed. - */ -#define INC_DECODED_INST_LEN(x) \ - if (DEBUG_DECODE()) \ - x86emu_inc_decoded_inst_len(x) - -#define SAVE_IP_CS(x,y) \ - if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ - | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ - M.x86.saved_cs = x; \ - M.x86.saved_ip = y; \ - } -#else -# define INC_DECODED_INST_LEN(x) -# define DECODE_PRINTF(x) -# define DECODE_PRINTF2(x,y) -# define SAVE_IP_CS(x,y) -#endif - -#ifdef DEBUG -#define TRACE_REGS() \ - if (DEBUG_DISASSEMBLE()) { \ - x86emu_just_disassemble(); \ - goto EndOfTheInstructionProcedure; \ - } \ - if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() -#else -# define TRACE_REGS() -#endif - -#ifdef DEBUG -# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() -#else -# define SINGLE_STEP() -#endif - -#define TRACE_AND_STEP() \ - TRACE_REGS(); \ - SINGLE_STEP() - -#ifdef DEBUG -# define START_OF_INSTR() -# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); -# define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); -#else -# define START_OF_INSTR() -# define END_OF_INSTR() -# define END_OF_INSTR_NO_TRACE() -#endif - -#ifdef DEBUG -# define CALL_TRACE(u,v,w,x,s) \ - if (DEBUG_TRACECALLREGS()) \ - x86emu_dump_regs(); \ - if (DEBUG_TRACECALL()) \ - printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); -# define RETURN_TRACE(n,u,v) \ - if (DEBUG_TRACECALLREGS()) \ - x86emu_dump_regs(); \ - if (DEBUG_TRACECALL()) \ - printk("%04x:%04x: %s\n",u,v,n); -#else -# define CALL_TRACE(u,v,w,x,s) -# define RETURN_TRACE(n,u,v) -#endif - -#ifdef DEBUG -#define DB(x) x -#else -#define DB(x) -#endif - -/*-------------------------- Function Prototypes --------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -extern void x86emu_inc_decoded_inst_len (int x); -extern void x86emu_decode_printf (char *x); -extern void x86emu_decode_printf2 (char *x, int y); -extern void x86emu_just_disassemble (void); -extern void x86emu_single_step (void); -extern void x86emu_end_instr (void); -extern void x86emu_dump_regs (void); -extern void x86emu_dump_xregs (void); -extern void x86emu_print_int_vect (u16 iv); -extern void x86emu_instrument_instruction (void); -extern void x86emu_check_ip_access (void); -extern void x86emu_check_sp_access (void); -extern void x86emu_check_mem_access (u32 p); -extern void x86emu_check_data_access (uint s, uint o); - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __X86EMU_DEBUG_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h deleted file mode 100644 index 321a345..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Header file for instruction decoding logic. -* -****************************************************************************/ - -#ifndef __X86EMU_DECODE_H -#define __X86EMU_DECODE_H - -/*---------------------- Macros and type definitions ----------------------*/ - -/* Instruction Decoding Stuff */ - -#define FETCH_DECODE_MODRM(mod,rh,rl) fetch_decode_modrm(&mod,&rh,&rl) -#define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) -#define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) -#define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) -#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK - -/*-------------------------- Function Prototypes --------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -void x86emu_intr_raise (u8 type); -void fetch_decode_modrm (int *mod,int *regh,int *regl); -u8 fetch_byte_imm (void); -u16 fetch_word_imm (void); -u32 fetch_long_imm (void); -u8 fetch_data_byte (uint offset); -u8 fetch_data_byte_abs (uint segment, uint offset); -u16 fetch_data_word (uint offset); -u16 fetch_data_word_abs (uint segment, uint offset); -u32 fetch_data_long (uint offset); -u32 fetch_data_long_abs (uint segment, uint offset); -void store_data_byte (uint offset, u8 val); -void store_data_byte_abs (uint segment, uint offset, u8 val); -void store_data_word (uint offset, u16 val); -void store_data_word_abs (uint segment, uint offset, u16 val); -void store_data_long (uint offset, u32 val); -void store_data_long_abs (uint segment, uint offset, u32 val); -u8* decode_rm_byte_register(int reg); -u16* decode_rm_word_register(int reg); -u32* decode_rm_long_register(int reg); -u16* decode_rm_seg_register(int reg); -unsigned decode_rm00_address(int rm); -unsigned decode_rm01_address(int rm); -unsigned decode_rm10_address(int rm); - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __X86EMU_DECODE_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h deleted file mode 100644 index 5fb2714..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h +++ /dev/null @@ -1,61 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Header file for FPU instruction decoding. -* -****************************************************************************/ - -#ifndef __X86EMU_FPU_H -#define __X86EMU_FPU_H - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -/* these have to be defined, whether 8087 support compiled in or not. */ - -extern void x86emuOp_esc_coprocess_d8 (u8 op1); -extern void x86emuOp_esc_coprocess_d9 (u8 op1); -extern void x86emuOp_esc_coprocess_da (u8 op1); -extern void x86emuOp_esc_coprocess_db (u8 op1); -extern void x86emuOp_esc_coprocess_dc (u8 op1); -extern void x86emuOp_esc_coprocess_dd (u8 op1); -extern void x86emuOp_esc_coprocess_de (u8 op1); -extern void x86emuOp_esc_coprocess_df (u8 op1); - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __X86EMU_FPU_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h deleted file mode 100644 index 65ea676..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h +++ /dev/null @@ -1,45 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Header file for operand decoding functions. -* -****************************************************************************/ - -#ifndef __X86EMU_OPS_H -#define __X86EMU_OPS_H - -extern void (*x86emu_optab[0x100])(u8 op1); -extern void (*x86emu_optab2[0x100])(u8 op2); - -#endif /* __X86EMU_OPS_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h deleted file mode 100644 index e023cf8..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h +++ /dev/null @@ -1,970 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: Watcom C++ 10.6 or later -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Inline assembler versions of the primitive operand -* functions for faster performance. At the moment this is -* x86 inline assembler, but these functions could be replaced -* with native inline assembler for each supported processor -* platform. -* -****************************************************************************/ - -#ifndef __X86EMU_PRIM_ASM_H -#define __X86EMU_PRIM_ASM_H - -#ifdef __WATCOMC__ - -#ifndef VALIDATE -#define __HAVE_INLINE_ASSEMBLER__ -#endif - -u32 get_flags_asm(void); -#pragma aux get_flags_asm = \ - "pushf" \ - "pop eax" \ - value [eax] \ - modify exact [eax]; - -u16 aaa_word_asm(u32 *flags,u16 d); -#pragma aux aaa_word_asm = \ - "push [edi]" \ - "popf" \ - "aaa" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aas_word_asm(u32 *flags,u16 d); -#pragma aux aas_word_asm = \ - "push [edi]" \ - "popf" \ - "aas" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aad_word_asm(u32 *flags,u16 d); -#pragma aux aad_word_asm = \ - "push [edi]" \ - "popf" \ - "aad" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aam_word_asm(u32 *flags,u8 d); -#pragma aux aam_word_asm = \ - "push [edi]" \ - "popf" \ - "aam" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [ax] \ - modify exact [ax]; - -u8 adc_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux adc_byte_asm = \ - "push [edi]" \ - "popf" \ - "adc al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 adc_word_asm(u32 *flags,u16 d, u16 s); -#pragma aux adc_word_asm = \ - "push [edi]" \ - "popf" \ - "adc ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 adc_long_asm(u32 *flags,u32 d, u32 s); -#pragma aux adc_long_asm = \ - "push [edi]" \ - "popf" \ - "adc eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 add_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux add_byte_asm = \ - "push [edi]" \ - "popf" \ - "add al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 add_word_asm(u32 *flags,u16 d, u16 s); -#pragma aux add_word_asm = \ - "push [edi]" \ - "popf" \ - "add ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 add_long_asm(u32 *flags,u32 d, u32 s); -#pragma aux add_long_asm = \ - "push [edi]" \ - "popf" \ - "add eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 and_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux and_byte_asm = \ - "push [edi]" \ - "popf" \ - "and al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 and_word_asm(u32 *flags,u16 d, u16 s); -#pragma aux and_word_asm = \ - "push [edi]" \ - "popf" \ - "and ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 and_long_asm(u32 *flags,u32 d, u32 s); -#pragma aux and_long_asm = \ - "push [edi]" \ - "popf" \ - "and eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 cmp_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux cmp_byte_asm = \ - "push [edi]" \ - "popf" \ - "cmp al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 cmp_word_asm(u32 *flags,u16 d, u16 s); -#pragma aux cmp_word_asm = \ - "push [edi]" \ - "popf" \ - "cmp ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 cmp_long_asm(u32 *flags,u32 d, u32 s); -#pragma aux cmp_long_asm = \ - "push [edi]" \ - "popf" \ - "cmp eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 daa_byte_asm(u32 *flags,u8 d); -#pragma aux daa_byte_asm = \ - "push [edi]" \ - "popf" \ - "daa" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u8 das_byte_asm(u32 *flags,u8 d); -#pragma aux das_byte_asm = \ - "push [edi]" \ - "popf" \ - "das" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u8 dec_byte_asm(u32 *flags,u8 d); -#pragma aux dec_byte_asm = \ - "push [edi]" \ - "popf" \ - "dec al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 dec_word_asm(u32 *flags,u16 d); -#pragma aux dec_word_asm = \ - "push [edi]" \ - "popf" \ - "dec ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 dec_long_asm(u32 *flags,u32 d); -#pragma aux dec_long_asm = \ - "push [edi]" \ - "popf" \ - "dec eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 inc_byte_asm(u32 *flags,u8 d); -#pragma aux inc_byte_asm = \ - "push [edi]" \ - "popf" \ - "inc al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 inc_word_asm(u32 *flags,u16 d); -#pragma aux inc_word_asm = \ - "push [edi]" \ - "popf" \ - "inc ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 inc_long_asm(u32 *flags,u32 d); -#pragma aux inc_long_asm = \ - "push [edi]" \ - "popf" \ - "inc eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 or_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux or_byte_asm = \ - "push [edi]" \ - "popf" \ - "or al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 or_word_asm(u32 *flags,u16 d, u16 s); -#pragma aux or_word_asm = \ - "push [edi]" \ - "popf" \ - "or ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 or_long_asm(u32 *flags,u32 d, u32 s); -#pragma aux or_long_asm = \ - "push [edi]" \ - "popf" \ - "or eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 neg_byte_asm(u32 *flags,u8 d); -#pragma aux neg_byte_asm = \ - "push [edi]" \ - "popf" \ - "neg al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 neg_word_asm(u32 *flags,u16 d); -#pragma aux neg_word_asm = \ - "push [edi]" \ - "popf" \ - "neg ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 neg_long_asm(u32 *flags,u32 d); -#pragma aux neg_long_asm = \ - "push [edi]" \ - "popf" \ - "neg eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 not_byte_asm(u32 *flags,u8 d); -#pragma aux not_byte_asm = \ - "push [edi]" \ - "popf" \ - "not al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 not_word_asm(u32 *flags,u16 d); -#pragma aux not_word_asm = \ - "push [edi]" \ - "popf" \ - "not ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 not_long_asm(u32 *flags,u32 d); -#pragma aux not_long_asm = \ - "push [edi]" \ - "popf" \ - "not eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 rcl_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux rcl_byte_asm = \ - "push [edi]" \ - "popf" \ - "rcl al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rcl_word_asm(u32 *flags,u16 d, u8 s); -#pragma aux rcl_word_asm = \ - "push [edi]" \ - "popf" \ - "rcl ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rcl_long_asm(u32 *flags,u32 d, u8 s); -#pragma aux rcl_long_asm = \ - "push [edi]" \ - "popf" \ - "rcl eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 rcr_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux rcr_byte_asm = \ - "push [edi]" \ - "popf" \ - "rcr al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rcr_word_asm(u32 *flags,u16 d, u8 s); -#pragma aux rcr_word_asm = \ - "push [edi]" \ - "popf" \ - "rcr ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rcr_long_asm(u32 *flags,u32 d, u8 s); -#pragma aux rcr_long_asm = \ - "push [edi]" \ - "popf" \ - "rcr eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 rol_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux rol_byte_asm = \ - "push [edi]" \ - "popf" \ - "rol al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rol_word_asm(u32 *flags,u16 d, u8 s); -#pragma aux rol_word_asm = \ - "push [edi]" \ - "popf" \ - "rol ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rol_long_asm(u32 *flags,u32 d, u8 s); -#pragma aux rol_long_asm = \ - "push [edi]" \ - "popf" \ - "rol eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 ror_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux ror_byte_asm = \ - "push [edi]" \ - "popf" \ - "ror al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 ror_word_asm(u32 *flags,u16 d, u8 s); -#pragma aux ror_word_asm = \ - "push [edi]" \ - "popf" \ - "ror ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 ror_long_asm(u32 *flags,u32 d, u8 s); -#pragma aux ror_long_asm = \ - "push [edi]" \ - "popf" \ - "ror eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 shl_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux shl_byte_asm = \ - "push [edi]" \ - "popf" \ - "shl al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 shl_word_asm(u32 *flags,u16 d, u8 s); -#pragma aux shl_word_asm = \ - "push [edi]" \ - "popf" \ - "shl ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 shl_long_asm(u32 *flags,u32 d, u8 s); -#pragma aux shl_long_asm = \ - "push [edi]" \ - "popf" \ - "shl eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 shr_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux shr_byte_asm = \ - "push [edi]" \ - "popf" \ - "shr al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 shr_word_asm(u32 *flags,u16 d, u8 s); -#pragma aux shr_word_asm = \ - "push [edi]" \ - "popf" \ - "shr ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 shr_long_asm(u32 *flags,u32 d, u8 s); -#pragma aux shr_long_asm = \ - "push [edi]" \ - "popf" \ - "shr eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 sar_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux sar_byte_asm = \ - "push [edi]" \ - "popf" \ - "sar al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 sar_word_asm(u32 *flags,u16 d, u8 s); -#pragma aux sar_word_asm = \ - "push [edi]" \ - "popf" \ - "sar ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 sar_long_asm(u32 *flags,u32 d, u8 s); -#pragma aux sar_long_asm = \ - "push [edi]" \ - "popf" \ - "sar eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u16 shld_word_asm(u32 *flags,u16 d, u16 fill, u8 s); -#pragma aux shld_word_asm = \ - "push [edi]" \ - "popf" \ - "shld ax,dx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [dx] [cl] \ - value [ax] \ - modify exact [ax dx cl]; - -u32 shld_long_asm(u32 *flags,u32 d, u32 fill, u8 s); -#pragma aux shld_long_asm = \ - "push [edi]" \ - "popf" \ - "shld eax,edx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [edx] [cl] \ - value [eax] \ - modify exact [eax edx cl]; - -u16 shrd_word_asm(u32 *flags,u16 d, u16 fill, u8 s); -#pragma aux shrd_word_asm = \ - "push [edi]" \ - "popf" \ - "shrd ax,dx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [dx] [cl] \ - value [ax] \ - modify exact [ax dx cl]; - -u32 shrd_long_asm(u32 *flags,u32 d, u32 fill, u8 s); -#pragma aux shrd_long_asm = \ - "push [edi]" \ - "popf" \ - "shrd eax,edx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [edx] [cl] \ - value [eax] \ - modify exact [eax edx cl]; - -u8 sbb_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux sbb_byte_asm = \ - "push [edi]" \ - "popf" \ - "sbb al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 sbb_word_asm(u32 *flags,u16 d, u16 s); -#pragma aux sbb_word_asm = \ - "push [edi]" \ - "popf" \ - "sbb ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 sbb_long_asm(u32 *flags,u32 d, u32 s); -#pragma aux sbb_long_asm = \ - "push [edi]" \ - "popf" \ - "sbb eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 sub_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux sub_byte_asm = \ - "push [edi]" \ - "popf" \ - "sub al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 sub_word_asm(u32 *flags,u16 d, u16 s); -#pragma aux sub_word_asm = \ - "push [edi]" \ - "popf" \ - "sub ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 sub_long_asm(u32 *flags,u32 d, u32 s); -#pragma aux sub_long_asm = \ - "push [edi]" \ - "popf" \ - "sub eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -void test_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux test_byte_asm = \ - "push [edi]" \ - "popf" \ - "test al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - modify exact [al bl]; - -void test_word_asm(u32 *flags,u16 d, u16 s); -#pragma aux test_word_asm = \ - "push [edi]" \ - "popf" \ - "test ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - modify exact [ax bx]; - -void test_long_asm(u32 *flags,u32 d, u32 s); -#pragma aux test_long_asm = \ - "push [edi]" \ - "popf" \ - "test eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - modify exact [eax ebx]; - -u8 xor_byte_asm(u32 *flags,u8 d, u8 s); -#pragma aux xor_byte_asm = \ - "push [edi]" \ - "popf" \ - "xor al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 xor_word_asm(u32 *flags,u16 d, u16 s); -#pragma aux xor_word_asm = \ - "push [edi]" \ - "popf" \ - "xor ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 xor_long_asm(u32 *flags,u32 d, u32 s); -#pragma aux xor_long_asm = \ - "push [edi]" \ - "popf" \ - "xor eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -void imul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); -#pragma aux imul_byte_asm = \ - "push [edi]" \ - "popf" \ - "imul bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - parm [edi] [esi] [al] [bl] \ - modify exact [esi ax bl]; - -void imul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); -#pragma aux imul_word_asm = \ - "push [edi]" \ - "popf" \ - "imul bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [bx]\ - modify exact [esi edi ax bx dx]; - -void imul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); -#pragma aux imul_long_asm = \ - "push [edi]" \ - "popf" \ - "imul ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [ebx] \ - modify exact [esi edi eax ebx edx]; - -void mul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); -#pragma aux mul_byte_asm = \ - "push [edi]" \ - "popf" \ - "mul bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - parm [edi] [esi] [al] [bl] \ - modify exact [esi ax bl]; - -void mul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); -#pragma aux mul_word_asm = \ - "push [edi]" \ - "popf" \ - "mul bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [bx]\ - modify exact [esi edi ax bx dx]; - -void mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); -#pragma aux mul_long_asm = \ - "push [edi]" \ - "popf" \ - "mul ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [ebx] \ - modify exact [esi edi eax ebx edx]; - -void idiv_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); -#pragma aux idiv_byte_asm = \ - "push [edi]" \ - "popf" \ - "idiv bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],al" \ - "mov [ecx],ah" \ - parm [edi] [esi] [ecx] [ax] [bl]\ - modify exact [esi edi ax bl]; - -void idiv_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); -#pragma aux idiv_word_asm = \ - "push [edi]" \ - "popf" \ - "idiv bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [dx] [bx]\ - modify exact [esi edi ax dx bx]; - -void idiv_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); -#pragma aux idiv_long_asm = \ - "push [edi]" \ - "popf" \ - "idiv ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ - modify exact [esi edi eax edx ebx]; - -void div_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); -#pragma aux div_byte_asm = \ - "push [edi]" \ - "popf" \ - "div bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],al" \ - "mov [ecx],ah" \ - parm [edi] [esi] [ecx] [ax] [bl]\ - modify exact [esi edi ax bl]; - -void div_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); -#pragma aux div_word_asm = \ - "push [edi]" \ - "popf" \ - "div bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [dx] [bx]\ - modify exact [esi edi ax dx bx]; - -void div_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); -#pragma aux div_long_asm = \ - "push [edi]" \ - "popf" \ - "div ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ - modify exact [esi edi eax edx ebx]; - -#endif - -#endif /* __X86EMU_PRIM_ASM_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h deleted file mode 100644 index 1633fe1..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h +++ /dev/null @@ -1,231 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Header file for primitive operation functions. -* -****************************************************************************/ - -#ifndef __X86EMU_PRIM_OPS_H -#define __X86EMU_PRIM_OPS_H - -#include "x86emu/prim_asm.h" - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -u16 aaa_word (u16 d); -u16 aas_word (u16 d); -u16 aad_word (u16 d); -u16 aam_word (u8 d); -u8 adc_byte (u8 d, u8 s); -u16 adc_word (u16 d, u16 s); -u32 adc_long (u32 d, u32 s); -u8 add_byte (u8 d, u8 s); -u16 add_word (u16 d, u16 s); -u32 add_long (u32 d, u32 s); -u8 and_byte (u8 d, u8 s); -u16 and_word (u16 d, u16 s); -u32 and_long (u32 d, u32 s); -u8 cmp_byte (u8 d, u8 s); -u16 cmp_word (u16 d, u16 s); -u32 cmp_long (u32 d, u32 s); -u8 daa_byte (u8 d); -u8 das_byte (u8 d); -u8 dec_byte (u8 d); -u16 dec_word (u16 d); -u32 dec_long (u32 d); -u8 inc_byte (u8 d); -u16 inc_word (u16 d); -u32 inc_long (u32 d); -u8 or_byte (u8 d, u8 s); -u16 or_word (u16 d, u16 s); -u32 or_long (u32 d, u32 s); -u8 neg_byte (u8 s); -u16 neg_word (u16 s); -u32 neg_long (u32 s); -u8 not_byte (u8 s); -u16 not_word (u16 s); -u32 not_long (u32 s); -u8 rcl_byte (u8 d, u8 s); -u16 rcl_word (u16 d, u8 s); -u32 rcl_long (u32 d, u8 s); -u8 rcr_byte (u8 d, u8 s); -u16 rcr_word (u16 d, u8 s); -u32 rcr_long (u32 d, u8 s); -u8 rol_byte (u8 d, u8 s); -u16 rol_word (u16 d, u8 s); -u32 rol_long (u32 d, u8 s); -u8 ror_byte (u8 d, u8 s); -u16 ror_word (u16 d, u8 s); -u32 ror_long (u32 d, u8 s); -u8 shl_byte (u8 d, u8 s); -u16 shl_word (u16 d, u8 s); -u32 shl_long (u32 d, u8 s); -u8 shr_byte (u8 d, u8 s); -u16 shr_word (u16 d, u8 s); -u32 shr_long (u32 d, u8 s); -u8 sar_byte (u8 d, u8 s); -u16 sar_word (u16 d, u8 s); -u32 sar_long (u32 d, u8 s); -u16 shld_word (u16 d, u16 fill, u8 s); -u32 shld_long (u32 d, u32 fill, u8 s); -u16 shrd_word (u16 d, u16 fill, u8 s); -u32 shrd_long (u32 d, u32 fill, u8 s); -u8 sbb_byte (u8 d, u8 s); -u16 sbb_word (u16 d, u16 s); -u32 sbb_long (u32 d, u32 s); -u8 sub_byte (u8 d, u8 s); -u16 sub_word (u16 d, u16 s); -u32 sub_long (u32 d, u32 s); -void test_byte (u8 d, u8 s); -void test_word (u16 d, u16 s); -void test_long (u32 d, u32 s); -u8 xor_byte (u8 d, u8 s); -u16 xor_word (u16 d, u16 s); -u32 xor_long (u32 d, u32 s); -void imul_byte (u8 s); -void imul_word (u16 s); -void imul_long (u32 s); -void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s); -void mul_byte (u8 s); -void mul_word (u16 s); -void mul_long (u32 s); -void idiv_byte (u8 s); -void idiv_word (u16 s); -void idiv_long (u32 s); -void div_byte (u8 s); -void div_word (u16 s); -void div_long (u32 s); -void ins (int size); -void outs (int size); -u16 mem_access_word (int addr); -void push_word (u16 w); -void push_long (u32 w); -u16 pop_word (void); -u32 pop_long (void); - -#if defined(__HAVE_INLINE_ASSEMBLER__) && !defined(PRIM_OPS_NO_REDEFINE_ASM) - -#define aaa_word(d) aaa_word_asm(&M.x86.R_EFLG,d) -#define aas_word(d) aas_word_asm(&M.x86.R_EFLG,d) -#define aad_word(d) aad_word_asm(&M.x86.R_EFLG,d) -#define aam_word(d) aam_word_asm(&M.x86.R_EFLG,d) -#define adc_byte(d,s) adc_byte_asm(&M.x86.R_EFLG,d,s) -#define adc_word(d,s) adc_word_asm(&M.x86.R_EFLG,d,s) -#define adc_long(d,s) adc_long_asm(&M.x86.R_EFLG,d,s) -#define add_byte(d,s) add_byte_asm(&M.x86.R_EFLG,d,s) -#define add_word(d,s) add_word_asm(&M.x86.R_EFLG,d,s) -#define add_long(d,s) add_long_asm(&M.x86.R_EFLG,d,s) -#define and_byte(d,s) and_byte_asm(&M.x86.R_EFLG,d,s) -#define and_word(d,s) and_word_asm(&M.x86.R_EFLG,d,s) -#define and_long(d,s) and_long_asm(&M.x86.R_EFLG,d,s) -#define cmp_byte(d,s) cmp_byte_asm(&M.x86.R_EFLG,d,s) -#define cmp_word(d,s) cmp_word_asm(&M.x86.R_EFLG,d,s) -#define cmp_long(d,s) cmp_long_asm(&M.x86.R_EFLG,d,s) -#define daa_byte(d) daa_byte_asm(&M.x86.R_EFLG,d) -#define das_byte(d) das_byte_asm(&M.x86.R_EFLG,d) -#define dec_byte(d) dec_byte_asm(&M.x86.R_EFLG,d) -#define dec_word(d) dec_word_asm(&M.x86.R_EFLG,d) -#define dec_long(d) dec_long_asm(&M.x86.R_EFLG,d) -#define inc_byte(d) inc_byte_asm(&M.x86.R_EFLG,d) -#define inc_word(d) inc_word_asm(&M.x86.R_EFLG,d) -#define inc_long(d) inc_long_asm(&M.x86.R_EFLG,d) -#define or_byte(d,s) or_byte_asm(&M.x86.R_EFLG,d,s) -#define or_word(d,s) or_word_asm(&M.x86.R_EFLG,d,s) -#define or_long(d,s) or_long_asm(&M.x86.R_EFLG,d,s) -#define neg_byte(s) neg_byte_asm(&M.x86.R_EFLG,s) -#define neg_word(s) neg_word_asm(&M.x86.R_EFLG,s) -#define neg_long(s) neg_long_asm(&M.x86.R_EFLG,s) -#define not_byte(s) not_byte_asm(&M.x86.R_EFLG,s) -#define not_word(s) not_word_asm(&M.x86.R_EFLG,s) -#define not_long(s) not_long_asm(&M.x86.R_EFLG,s) -#define rcl_byte(d,s) rcl_byte_asm(&M.x86.R_EFLG,d,s) -#define rcl_word(d,s) rcl_word_asm(&M.x86.R_EFLG,d,s) -#define rcl_long(d,s) rcl_long_asm(&M.x86.R_EFLG,d,s) -#define rcr_byte(d,s) rcr_byte_asm(&M.x86.R_EFLG,d,s) -#define rcr_word(d,s) rcr_word_asm(&M.x86.R_EFLG,d,s) -#define rcr_long(d,s) rcr_long_asm(&M.x86.R_EFLG,d,s) -#define rol_byte(d,s) rol_byte_asm(&M.x86.R_EFLG,d,s) -#define rol_word(d,s) rol_word_asm(&M.x86.R_EFLG,d,s) -#define rol_long(d,s) rol_long_asm(&M.x86.R_EFLG,d,s) -#define ror_byte(d,s) ror_byte_asm(&M.x86.R_EFLG,d,s) -#define ror_word(d,s) ror_word_asm(&M.x86.R_EFLG,d,s) -#define ror_long(d,s) ror_long_asm(&M.x86.R_EFLG,d,s) -#define shl_byte(d,s) shl_byte_asm(&M.x86.R_EFLG,d,s) -#define shl_word(d,s) shl_word_asm(&M.x86.R_EFLG,d,s) -#define shl_long(d,s) shl_long_asm(&M.x86.R_EFLG,d,s) -#define shr_byte(d,s) shr_byte_asm(&M.x86.R_EFLG,d,s) -#define shr_word(d,s) shr_word_asm(&M.x86.R_EFLG,d,s) -#define shr_long(d,s) shr_long_asm(&M.x86.R_EFLG,d,s) -#define sar_byte(d,s) sar_byte_asm(&M.x86.R_EFLG,d,s) -#define sar_word(d,s) sar_word_asm(&M.x86.R_EFLG,d,s) -#define sar_long(d,s) sar_long_asm(&M.x86.R_EFLG,d,s) -#define shld_word(d,fill,s) shld_word_asm(&M.x86.R_EFLG,d,fill,s) -#define shld_long(d,fill,s) shld_long_asm(&M.x86.R_EFLG,d,fill,s) -#define shrd_word(d,fill,s) shrd_word_asm(&M.x86.R_EFLG,d,fill,s) -#define shrd_long(d,fill,s) shrd_long_asm(&M.x86.R_EFLG,d,fill,s) -#define sbb_byte(d,s) sbb_byte_asm(&M.x86.R_EFLG,d,s) -#define sbb_word(d,s) sbb_word_asm(&M.x86.R_EFLG,d,s) -#define sbb_long(d,s) sbb_long_asm(&M.x86.R_EFLG,d,s) -#define sub_byte(d,s) sub_byte_asm(&M.x86.R_EFLG,d,s) -#define sub_word(d,s) sub_word_asm(&M.x86.R_EFLG,d,s) -#define sub_long(d,s) sub_long_asm(&M.x86.R_EFLG,d,s) -#define test_byte(d,s) test_byte_asm(&M.x86.R_EFLG,d,s) -#define test_word(d,s) test_word_asm(&M.x86.R_EFLG,d,s) -#define test_long(d,s) test_long_asm(&M.x86.R_EFLG,d,s) -#define xor_byte(d,s) xor_byte_asm(&M.x86.R_EFLG,d,s) -#define xor_word(d,s) xor_word_asm(&M.x86.R_EFLG,d,s) -#define xor_long(d,s) xor_long_asm(&M.x86.R_EFLG,d,s) -#define imul_byte(s) imul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s) -#define imul_word(s) imul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s) -#define imul_long(s) imul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s) -#define imul_long_direct(res_lo,res_hi,d,s) imul_long_asm(&M.x86.R_EFLG,res_lo,res_hi,d,s) -#define mul_byte(s) mul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s) -#define mul_word(s) mul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s) -#define mul_long(s) mul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s) -#define idiv_byte(s) idiv_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s) -#define idiv_word(s) idiv_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s) -#define idiv_long(s) idiv_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s) -#define div_byte(s) div_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s) -#define div_word(s) div_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s) -#define div_long(s) div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s) - -#endif - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __X86EMU_PRIM_OPS_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h deleted file mode 100644 index bff4903..0000000 --- a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h +++ /dev/null @@ -1,98 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Header file for system specific functions. These functions -* are always compiled and linked in the OS depedent libraries, -* and never in a binary portable driver. -* -****************************************************************************/ - -#ifndef __X86EMU_X86EMUI_H -#define __X86EMU_X86EMUI_H - -/* If we are compiling in C++ mode, we can compile some functions as - * inline to increase performance (however the code size increases quite - * dramatically in this case). - */ - -#if defined(__cplusplus) && !defined(_NO_INLINE) -#define _INLINE inline -#else -#define _INLINE static -#endif - -/* Get rid of unused parameters in C++ compilation mode */ - -#ifdef __cplusplus -#define X86EMU_UNUSED(v) -#else -#define X86EMU_UNUSED(v) v -#endif - -#include "x86emu.h" -#include "x86emu/regs.h" -#include "x86emu/debug.h" -#include "x86emu/decode.h" -#include "x86emu/ops.h" -#include "x86emu/prim_ops.h" -#include "x86emu/fpu.h" -#include "x86emu/fpu_regs.h" -#include -#include - -/*--------------------------- Inline Functions ----------------------------*/ - -#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ -#endif - -extern u8 (X86APIP sys_rdb)(u32 addr); -extern u16 (X86APIP sys_rdw)(u32 addr); -extern u32 (X86APIP sys_rdl)(u32 addr); -extern void (X86APIP sys_wrb)(u32 addr,u8 val); -extern void (X86APIP sys_wrw)(u32 addr,u16 val); -extern void (X86APIP sys_wrl)(u32 addr,u32 val); - -extern u8 (X86APIP sys_inb)(X86EMU_pioAddr addr); -extern u16 (X86APIP sys_inw)(X86EMU_pioAddr addr); -extern u32 (X86APIP sys_inl)(X86EMU_pioAddr addr); -extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,u8 val); -extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val); -extern void (X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val); - -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ -#endif - -#endif /* __X86EMU_X86EMUI_H */ diff --git a/board/MAI/bios_emulator/x86interface.c b/board/MAI/bios_emulator/x86interface.c deleted file mode 100644 index 909cb3c..0000000 --- a/board/MAI/bios_emulator/x86interface.c +++ /dev/null @@ -1,814 +0,0 @@ -#include "x86emu.h" -#include "glue.h" - - -/* - * This isn't nice, but there are a lot of incompatibilities in the U-Boot and scitech include - * files that this is the only really workable solution. - * Might be cleaned out later. - */ - -#ifdef DEBUG -#undef DEBUG -#endif - -#undef IO_LOGGING -#undef MEM_LOGGING - -#ifdef IO_LOGGING -#define LOGIO(port, format, args...) if (dolog(port)) _printf(format , ## args) -#else -#define LOGIO(port, format, args...) -#endif - -#ifdef MEM_LOGGIN -#define LOGMEM(format, args...) _printf(format , ## args) -#else -#define LOGMEM(format, args...) -#endif - -#ifdef DEBUG -#define PRINTF(format, args...) _printf(format , ## args) -#else -#define PRINTF(format, argc...) -#endif - -typedef unsigned char UBYTE; -typedef unsigned short UWORD; -typedef unsigned long ULONG; - -typedef char BYTE; -typedef short WORT; -typedef long LONG; - -#define EMULATOR_MEM_SIZE (1024*1024) -#define EMULATOR_BIOS_OFFSET 0xC0000 -#define EMULATOR_STRAP_OFFSET 0x30000 -#define EMULATOR_STACK_OFFSET 0x20000 -#define EMULATOR_LOGO_OFFSET 0x40000 /* If you change this, change the strap code, too */ -#define VIDEO_BASE (void *)0xFD0B8000 - -extern char *getenv(char *); -extern int tstc(void); -extern int getc(void); -extern unsigned char video_get_attr(void); - -int atoi(char *string) -{ - int res = 0; - while (*string>='0' && *string <='9') - { - res *= 10; - res += *string-'0'; - string++; - } - - return res; -} - -void cons_gets(char *buffer) -{ - int i = 0; - char c = 0; - - buffer[0] = 0; - if (getenv("x86_runthru")) return; /*FIXME: */ - while (c != 0x0D && c != 0x0A) - { - while (!tstc()); - c = getc(); - if (c>=32 && c < 127) - { - buffer[i] = c; - i++; - buffer[i] = 0; - putc(c); - } - else - { - if (c == 0x08) - { - if (i>0) i--; - buffer[i] = 0; - } - } - } - buffer[i] = '\n'; - buffer[i+1] = 0; -} - -char *bios_date = "08/14/02"; -UBYTE model = 0xFC; -UBYTE submodel = 0x00; - -static inline UBYTE read_byte(volatile UBYTE* from) -{ - int x; - asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from)); - return (UBYTE)x; -} - -static inline void write_byte(volatile UBYTE *to, int x) -{ - asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x)); -} - -static inline UWORD read_word_little(volatile UWORD *from) -{ - int x; - asm volatile ("lhbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m" (*from)); - return (UWORD)x; -} - -static inline UWORD read_word_big(volatile UWORD *from) -{ - int x; - asm volatile ("lhz %0,%1\n eieio" : "=r" (x) : "m" (*from)); - return (UWORD)x; -} - -static inline void write_word_little(volatile UWORD *to, int x) -{ - asm volatile ("sthbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); -} - -static inline void write_word_big(volatile UWORD *to, int x) -{ - asm volatile ("sth %1,%0\n eieio" : "=m" (*to) : "r" (x)); -} - -static inline ULONG read_long_little(volatile ULONG *from) -{ - unsigned long x; - asm volatile ("lwbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m"(*from)); - return (ULONG)x; -} - -static inline ULONG read_long_big(volatile ULONG *from) -{ - unsigned long x; - asm volatile ("lwz %0,%1\n eieio" : "=r" (x) : "m" (*from)); - return (ULONG)x; -} - -static inline void write_long_little(volatile ULONG *to, ULONG x) -{ - asm volatile ("stwbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); -} - -static inline void write_long_big(volatile ULONG *to, ULONG x) -{ - asm volatile ("stw %1,%0\n eieio" : "=m" (*to) : "r" (x)); -} - -static int log_init = 0; -static int log_do = 0; -static int log_low = 0; - -int dolog(int port) -{ - if (log_init && log_do) - { - if (log_low && port > 0x400) return 0; - return 1; - } - - if (!log_init) - { - log_init = 1; - log_do = (getenv("x86_logio") != (char *)0); - log_low = (getenv("x86_loglow") != (char *)0); - if (log_do) - { - if (log_low && port > 0x400) return 0; - return 1; - } - } - return 0; -} - -/* Converts an emulator address to a physical address. */ -/* Handles all special cases (bios date, model etc), and might need work */ -u32 memaddr(u32 addr) -{ -/* if (addr >= 0xF0000 && addr < 0xFFFFF) printf("WARNING: Segment F access (0x%x)\n", addr); */ -/* printf("MemAddr=%p\n", addr); */ - if (addr >= 0xA0000 && addr < 0xC0000) - return 0xFD000000 + addr; - else if (addr >= 0xFFFF5 && addr < 0xFFFFE) - { - return (u32)bios_date+addr-0xFFFF5; - } - else if (addr == 0xFFFFE) - return (u32)&model; - else if (addr == 0xFFFFF) - return (u32)&submodel; - else if (addr >= 0x80000000) - { - /*printf("Warning: High memory access at 0x%x\n", addr); */ - return addr; - } - else - return (u32)M.mem_base+addr; -} - -u8 A1_rdb(u32 addr) -{ - u8 a = read_byte((UBYTE *)memaddr(addr)); - LOGMEM("rdb: %x -> %x\n", addr, a); - return a; -} - -u16 A1_rdw(u32 addr) -{ - u16 a = read_word_little((UWORD *)memaddr(addr)); - LOGMEM("rdw: %x -> %x\n", addr, a); - return a; -} - -u32 A1_rdl(u32 addr) -{ - u32 a = read_long_little((ULONG *)memaddr(addr)); - LOGMEM("rdl: %x -> %x\n", addr, a); - return a; -} - -void A1_wrb(u32 addr, u8 val) -{ - LOGMEM("wrb: %x <- %x\n", addr, val); - write_byte((UBYTE *)memaddr(addr), val); -} - -void A1_wrw(u32 addr, u16 val) -{ - LOGMEM("wrw: %x <- %x\n", addr, val); - write_word_little((UWORD *)memaddr(addr), val); -} - -void A1_wrl(u32 addr, u32 val) -{ - LOGMEM("wrl: %x <- %x\n", addr, val); - write_long_little((ULONG *)memaddr(addr), val); -} - -X86EMU_memFuncs _A1_mem = -{ - A1_rdb, - A1_rdw, - A1_rdl, - A1_wrb, - A1_wrw, - A1_wrl, -}; - -#define ARTICIAS_PCI_CFGADDR 0xfec00cf8 -#define ARTICIAS_PCI_CFGDATA 0xfee00cfc -#define IOBASE 0xFE000000 - -#define in_byte(from) read_byte( (UBYTE *)port_to_mem(from)) -#define in_word(from) read_word_little((UWORD *)port_to_mem(from)) -#define in_long(from) read_long_little((ULONG *)port_to_mem(from)) -#define out_byte(to, val) write_byte((UBYTE *)port_to_mem(to), val) -#define out_word(to, val) write_word_little((UWORD *)port_to_mem(to), val) -#define out_long(to, val) write_long_little((ULONG *)port_to_mem(to), val) - -u32 port_to_mem(int port) -{ - if (port >= 0xCFC && port <= 0xCFF) return 0xFEE00000+port; - else if (port >= 0xCF8 && port <= 0xCFB) return 0xFEC00000+port; - else return IOBASE + port; -} - -u8 A1_inb(int port) -{ - u8 a; - /*if (port == 0x3BA) return 0; */ - a = in_byte(port); - LOGIO(port, "inb: %Xh -> %d (%Xh)\n", port, a, a); - return a; -} - -u16 A1_inw(int port) -{ - u16 a = in_word(port); - LOGIO(port, "inw: %Xh -> %d (%Xh)\n", port, a, a); - return a; -} - -u32 A1_inl(int port) -{ - u32 a = in_long(port); - LOGIO(port, "inl: %Xh -> %d (%Xh)\n", port, a, a); - return a; -} - -void A1_outb(int port, u8 val) -{ - LOGIO(port, "outb: %Xh <- %d (%Xh)\n", port, val, val); -/* if (port == 0xCF8) port = 0xCFB; - else if (port == 0xCF9) port = 0xCFA; - else if (port == 0xCFA) port = 0xCF9; - else if (port == 0xCFB) port = 0xCF8;*/ - out_byte(port, val); -} - -void A1_outw(int port, u16 val) -{ - LOGIO(port, "outw: %Xh <- %d (%Xh)\n", port, val, val); - out_word(port, val); -} - -void A1_outl(int port, u32 val) -{ - LOGIO(port, "outl: %Xh <- %d (%Xh)\n", port, val, val); - out_long(port, val); -} - -X86EMU_pioFuncs _A1_pio = -{ - A1_inb, - A1_inw, - A1_inl, - A1_outb, - A1_outw, - A1_outl, -}; - -static int reloced_ops = 0; - -void reloc_ops(void *reloc_addr) -{ - extern void (*x86emu_optab[256])(u8); - extern void (*x86emu_optab2[256])(u8); - extern void tables_relocate(unsigned int offset); - int i; - unsigned long delta; - if (reloced_ops == 1) return; - reloced_ops = 1; - - delta = TEXT_BASE - (unsigned long)reloc_addr; - - for (i=0; i<256; i++) - { - x86emu_optab[i] -= delta; - x86emu_optab2[i] -= delta; - } - - _A1_mem.rdb = A1_rdb; - _A1_mem.rdw = A1_rdw; - _A1_mem.rdl = A1_rdl; - _A1_mem.wrb = A1_wrb; - _A1_mem.wrw = A1_wrw; - _A1_mem.wrl = A1_wrl; - - _A1_pio.inb = A1_inb; - _A1_pio.inw = A1_inw; - _A1_pio.inl = A1_inl; - _A1_pio.outb = A1_outb; - _A1_pio.outw = A1_outw; - _A1_pio.outl = A1_outl; - - tables_relocate(delta); - -} - - -#define ANY_KEY(text) \ - printf(text); \ - while (!tstc()); - - -unsigned char more_strap[] = { - 0xb4, 0x0, 0xb0, 0x2, 0xcd, 0x10, -}; -#define MORE_STRAP_BYTES 6 /* Additional bytes of strap code */ - - -unsigned char *done_msg="VGA Initialized\0"; - -int execute_bios(pci_dev_t gr_dev, void *reloc_addr) -{ - extern void bios_init(void); - extern void remove_init_data(void); - extern int video_rows(void); - extern int video_cols(void); - extern int video_size(int, int); - u8 *strap; - unsigned char *logo; - u8 cfg; - int i; - char c; - char *s; -#ifdef EASTEREGG - int easteregg_active = 0; -#endif - char *pal_reset; - u8 *fb; - unsigned char *msg; - unsigned char current_attr; - - PRINTF("Trying to remove init data\n"); - remove_init_data(); - PRINTF("Removed init data from cache, now in RAM\n"); - - reloc_ops(reloc_addr); - PRINTF("Attempting to run emulator on %02x:%02x:%02x\n", - PCI_BUS(gr_dev), PCI_DEV(gr_dev), PCI_FUNC(gr_dev)); - - /* Enable compatibility hole for emulator access to frame buffer */ - PRINTF("Enabling compatibility hole\n"); - enable_compatibility_hole(); - - /* Allocate memory */ - /* FIXME: We shouldn't use this much memory really. */ - memset(&M, 0, sizeof(X86EMU_sysEnv)); - M.mem_base = malloc(EMULATOR_MEM_SIZE); - M.mem_size = EMULATOR_MEM_SIZE; - - if (!M.mem_base) - { - PRINTF("Unable to allocate one megabyte for emulator\n"); - return 0; - } - - if (attempt_map_rom(gr_dev, M.mem_base + EMULATOR_BIOS_OFFSET) == 0) - { - PRINTF("Error mapping rom. Emulation terminated\n"); - return 0; - } - -#if 1 /*def DEBUG*/ - s = getenv("x86_ask_start"); - if (s) - { - printf("Press 'q' to skip initialization, 'd' for dry init\n'i' for i/o session"); - while (!tstc()); - c = getc(); - if (c == 'q') return 0; - if (c == 'd') - { - extern void bios_set_mode(int mode); - bios_set_mode(0x03); - return 0; - } - if (c == 'i') do_inout(); - } - - -#endif - -#ifdef EASTEREGG -/* if (tstc()) - { - if (getc() == 'c') - { - easteregg_active = 1; - } - } -*/ - if (getenv("easteregg")) - { - easteregg_active = 1; - } - - if (easteregg_active) - { - /* Yay! */ - setenv("x86_mode", "1"); - setenv("vga_fg_color", "11"); - setenv("vga_bg_color", "1"); - easteregg_active = 1; - } -#endif - - strap = (u8*)M.mem_base + EMULATOR_STRAP_OFFSET; - - { - char *m = getenv("x86_mode"); - if (m) - { - more_strap[3] = atoi(m); - if (more_strap[3] == 1) video_size(40, 25); - else video_size(80, 25); - } - } - - /* - * Poke the strap routine. This might need a bit of extending - * if there is a mode switch involved, i.e. we want to int10 - * afterwards to set a different graphics mode, or alternatively - * there might be a different start address requirement if the - * ROM doesn't have an x86 image in its first image. - */ - - PRINTF("Poking strap...\n"); - - /* FAR CALL c000:0003 */ - *strap++ = 0x9A; *strap++ = 0x03; *strap++ = 0x00; - *strap++ = 0x00; *strap++ = 0xC0; - -#if 1 - /* insert additional strap code */ - for (i=0; i < MORE_STRAP_BYTES; i++) - { - *strap++ = more_strap[i]; - } -#endif - /* HALT */ - *strap++ = 0xF4; - - PRINTF("Setting up logo data\n"); - logo = (unsigned char *)M.mem_base + EMULATOR_LOGO_OFFSET; - for (i=0; i<16; i++) - { - *logo++ = 0xFF; - } - - /* - * Setup the init parameters. - * Per PCI specs, AH must contain the bus and AL - * must contain the devfn, encoded as (dev<<3)|fn - */ - - /* Execution starts here */ - M.x86.R_CS = SEG(EMULATOR_STRAP_OFFSET); - M.x86.R_IP = OFF(EMULATOR_STRAP_OFFSET); - - /* Stack at top of ram */ - M.x86.R_SS = SEG(EMULATOR_STACK_OFFSET); - M.x86.R_SP = OFF(EMULATOR_STACK_OFFSET); - - /* Input parameters */ - M.x86.R_AH = PCI_BUS(gr_dev); - M.x86.R_AL = (PCI_DEV(gr_dev)<<3) | PCI_FUNC(gr_dev); - - /* Set the I/O and memory access functions */ - X86EMU_setupMemFuncs(&_A1_mem); - X86EMU_setupPioFuncs(&_A1_pio); - - /* Enable timer 2 */ - cfg = in_byte(0x61); /* Get Misc control */ - cfg |= 0x01; /* Enable timer 2 */ - out_byte(0x61, cfg); /* output again */ - - /* Set up the timers */ - out_byte(0x43, 0x54); - out_byte(0x41, 0x18); - - out_byte(0x43, 0x36); - out_byte(0x40, 0x00); - out_byte(0x40, 0x00); - - out_byte(0x43, 0xb6); - out_byte(0x42, 0x31); - out_byte(0x42, 0x13); - - /* Init the "BIOS". */ - bios_init(); - - /* Video Card Reset */ - out_byte(0x3D8, 0); - out_byte(0x3B8, 1); - (void)in_byte(0x3BA); - (void)in_byte(0x3DA); - out_byte(0x3C0, 0); - out_byte(0x61, 0xFC); - -#ifdef DEBUG - s = _getenv("x86_singlestep"); - if (s && strcmp(s, "on")==0) - { - PRINTF("Enabling single stepping for debug\n"); - X86EMU_trace_on(); - } -#endif - - /* Ready set go... */ - PRINTF("Running emulator\n"); - X86EMU_exec(); - PRINTF("Done running emulator\n"); - -/* FIXME: Remove me */ - pal_reset = getenv("x86_palette_reset"); - if (pal_reset && strcmp(pal_reset, "on") == 0) - { - PRINTF("Palette reset\n"); - /*(void)in_byte(0x3da); */ - /*out_byte(0x3c0, 0); */ - - out_byte(0x3C8, 0); - out_byte(0x3C9, 0); - out_byte(0x3C9, 0); - out_byte(0x3C9, 0); - for (i=0; i<254; i++) - { - out_byte(0x3C9, 63); - out_byte(0x3C9, 63); - out_byte(0x3C9, 63); - } - - out_byte(0x3c0, 0x20); - } -/* FIXME: remove me */ -#ifdef EASTEREGG - if (easteregg_active) - { - extern void video_easteregg(void); - video_easteregg(); - } -#endif -/* - current_attr = video_get_attr(); - fb = (u8 *)VIDEO_BASE; - for (i=0; i -#include - -int do_menu( cmd_tbl_t *cmdtp, /*bd_t *bd,*/ int flag, int argc, char *argv[] ) -{ -/* printf("\n"); */ - return 0; -} - -#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP) -U_BOOT_CMD( - menu, 1, 1, do_menu, - "menu - display BIOS setup menu\n", - "" -); -#endif diff --git a/board/MAI/menu/menu.c b/board/MAI/menu/menu.c deleted file mode 100644 index c0c63a8..0000000 --- a/board/MAI/menu/menu.c +++ /dev/null @@ -1,66 +0,0 @@ -#include "menu.h" - -#define SINGLE_BOX 0 -#define DOUBLE_BOX 1 - -void video_draw_box(int style, int attr, char *title, int separate, int x, int y, int w, int h); -void video_draw_text(int x, int y, int attr, char *text); -void video_save_rect(int x, int y, int w, int h, void *save_area, int clearchar, int clearattr); -void video_restore_rect(int x, int y, int w, int h, void *save_area); -int video_rows(void); -int video_cols(void); - -#define MAX_MENU_OPTIONS 200 - -typedef struct -{ - int used; /* flag if this entry is used */ - int entry_x; /* Character column of the menu entry */ - int entry_y; /* Character line of the entry */ - int option_x; /* Character colum of the option (entry is same) */ -} option_data_t; - -option_data_t odata[MAX_MENU_OPTIONS]; - -int normal_attr = 0x0F; -int select_attr = 0x2F; -int disabled_attr = 0x07; - -menu_t *root_menu; - -int menu_init (menu_t *root) -{ - char *s; - int i; - - s = getenv("menu_normal"); - if (s) normal_attr = atoi(s); - - s = getenv("menu_select"); - if (s) select_attr = atoi(s); - - s = getenv("menu_disabled"); - if (s) disabled_attr = atoi(s); - - for (i=0; iused = 0; -} - -void menu_layout (menu_t *menu) -{ diff --git a/board/MAI/menu/menu.h b/board/MAI/menu/menu.h deleted file mode 100644 index 8aebb7d..0000000 --- a/board/MAI/menu/menu.h +++ /dev/null @@ -1,174 +0,0 @@ -#ifndef MENU_H -#define MENU_H - -/* A single menu */ -typedef void (*menu_finish_callback)(struct menu_s *menu); - -typedef struct menu_s -{ - char *name; /* Menu name */ - int num_options; /* Number of options in this menu */ - int flags; /* Various flags - see below */ - int option_align; /* Aligns options to a field width of this much characters if != 0 */ - - struct menu_option_s **options; /* Pointer to this menu's options */ - menu_finish_callback callback; /* Called when the menu closes */ -} menu_t; - -/* - * type: Type of the option (see below) - * name: Name to display for this option - * help: Optional help string - * id : optional id number - * sys : pointer for system-specific data, init to NULL and don't touch - */ - -#define OPTION_PREAMBLE \ - int type; \ - char *name; \ - char *help; \ - int id; \ - void *sys; \ - - -/* - * Menu option types. - * There are a number of different layouts for menu options depending - * on their types. Currently there are the following possibilities: - * - * Submenu: - * This entry links to a new menu. - * - * Boolean: - * A simple on/off toggle entry. Booleans can be either yes/no, 0/1 or on/off. - * Optionally, this entry can enable/disable a set of other options. An example would - * be to enable/disable on-board USB, and if enabled give access to further options like - * irq settings, base address etc. - * - * Text: - * A single line/limited number of characters text entry box. Text can be restricted - * to a certain charset (digits/hex digits/all/custom). Result is also available as an - * int if numeric. - * - * Selection: - * One-of-many type of selection entry. User may choose on of a set of strings, which - * maps to a specific value for the variable. - * - * Routine: - * Selecting this calls an entry-specific routine. This can be used for saving contents etc. - * - * Custom: - * Display and behaviour of this entry is defined by a set of callbacks. - */ - -#define MENU_SUBMENU_TYPE 0 -typedef struct menu_submenu_s -{ - OPTION_PREAMBLE - - menu_t * submenu; /* Pointer to the submenu */ -} menu_submenu_t; - -#define MENU_BOOLEAN_TYPE 1 -typedef struct menu_boolean_s -{ - OPTION_PREAMBLE - - char *variable; /* Name of the variable to getenv()/setenv() */ - int subtype; /* Subtype (on/off, 0/1, yes/no, enable/disable), see below */ - int mutex; /* Bit mask of options to enable/disable. Bit 0 is the option - immediately following this one, bit 1 is the next one etc. - bit 7 = 0 means to disable when this option is off, - bit 7 = 1 means to disable when this option is on. - An option is disabled when the type field's upper bit is set */ -} menu_boolean_t; - -/* BOOLEAN Menu flags */ -#define MENU_BOOLEAN_ONOFF 0x01 -#define MENU_BOOLEAN_01 0x02 -#define MENU_BOOLEAN_YESNO 0x03 -#define MENU_BOOLEAN_ENDIS 0x04 -#define MENU_BOOLEAN_TYPE_MASK 0x07 - - -#define MENU_TEXT_TYPE 2 -typedef struct menu_text_s -{ - OPTION_PREAMBLE - - char *variable; /* Name of the variable to getenv()/setenv() */ - int maxchars; /* Max number of characters */ - char *charset; /* Optional charset to use */ - int flags; /* Flags - see below */ -} menu_text_t; - -/* TEXT entry menu flags */ -#define MENU_TEXT_NUMERIC 0x01 -#define MENU_TEXT_HEXADECIMAL 0x02 -#define MENU_TEXT_FREE 0x03 -#define MENU_TEXT_TYPE_MASK 0x07 - - -#define MENU_SELECTION_TYPE 3 -typedef struct menu_select_option_s -{ - char *map_from; /* Map this variable contents ... */ - char *map_to; /* ... to this menu text and vice versa */ -} menu_select_option_t; - -typedef struct menu_select_s -{ - OPTION_PREAMBLE - - int num_options; /* Number of mappings */ - menu_select_option_t **options; - /* Option list array */ -} menu_select_t; - - -#define MENU_ROUTINE_TYPE 4 -typedef void (*menu_routine_callback)(struct menu_routine_s *); - -typedef struct menu_routine_s -{ - OPTION_PREAMBLE - menu_routine_callback callback; - /* routine to be called */ - void *user_data; /* User data, don't care for system */ -} menu_routine_t; - - -#define MENU_CUSTOM_TYPE 5 -typedef void (*menu_custom_draw)(struct menu_custom_s *); -typedef void (*menu_custom_key)(struct menu_custom_s *, int); - -typedef struct menu_custom_s -{ - OPTION_PREAMBLE - menu_custom_draw drawfunc; - menu_custom_key keyfunc; - void *user_data; -} menu_custom_t; - -/* - * The menu option superstructure - */ -typedef struct menu_option_s -{ - union - { - menu_submenu_t m_sub_menu; - menu_boolean_t m_boolean; - menu_text_t m_text; - menu_select_t m_select; - menu_routine_t m_routine; - }; -} menu_option_t; - -/* Init the menu system. Returns <0 on error */ -int menu_init(menu_t *root); - -/* Execute a single menu. Returns <0 on error */ -int menu_do(menu_t *menu); - -#endif diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt deleted file mode 100644 index 391d49a..0000000 --- a/board/Marvell/common/bootseq.txt +++ /dev/null @@ -1,94 +0,0 @@ -(cpu/mpc7xxx/start.S) - -start: - b boot_cold - -start_warm: - b boot_warm - - -boot_cold: -boot_warm: - clear bats - init l2 (if enabled) - init altivec (if enabled) - invalidate l2 (if enabled) - setup bats (from defines in config_EVB) - enable_addr_trans: (if MMU enabled) - enable MSR_IR and MSR_DR - jump to in_flash - -in_flash: - enable l1 dcache - gal_low_init: (board/evb64260/sdram_init.S) - config SDRAM (CFG, TIMING, DECODE) - init scratch regs (810 + 814) - - detect DIMM0 (bank 0 only) - config SDRAM_PARA0 to 256/512Mbit - bl sdram_op_mode - detect bank0 width - write scratch reg 810 - config SDRAM_PARA0 with results - config SDRAM_PARA1 with results - - detect DIMM1 (bank 2 only) - config SDRAM_PARA2 to 256/512Mbit - detect bank2 width - write scratch reg 814 - config SDRAM_PARA2 with results - config SDRAM_PARA3 with results - - setup device bus timings/width - setup boot device timings/width - - setup CPU_CONF (0x0) - setup cpu master control register 0x160 - setup PCI0 TIMEOUT - setup PCI1 TIMEOUT - setup PCI0 BAR - setup PCI1 BAR - - setup MPP control 0-3 - setup GPP level control - setup Serial ports multiplex - - setup stack pointer (r1) - setup GOT - call cpu_init_f - debug leds - board_init_f: (common/board.c) - board_early_init_f: - remap gt regs? - map PCI mem/io - map device space - clear out interupts - init_timebase - env_init - serial_init - console_init_f - display_options - initdram: (board/evb64260/evb64260.c) - detect memory - for each bank: - dram_size() - setup PCI slave memory mappings - setup SCS - setup monitor - alloc board info struct - init bd struct - relocate_code: (cpu/mpc7xxx/start.S) - copy,got,clearbss - board_init_r(bd, dest_addr) (common/board.c) - setup bd function pointers - trap_init - flash_init: (board/evb64260/flash.c) - setup bd flash info - cpu_init_r: (cpu/mpc7xxx/cpu_init.c) - nothing - mem_malloc_init - malloc_bin_reloc - spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) - env_relocated - misc_init_r(bd): (board/evb64260/evb64260.c) - mpsc_init2 diff --git a/board/Marvell/common/ecctest.c b/board/Marvell/common/ecctest.c deleted file mode 100644 index e22b113..0000000 --- a/board/Marvell/common/ecctest.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2001 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifdef ECC_TEST -static inline void ecc_off (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000; -} - -static inline void ecc_on (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000; -} - -static int putshex (const char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) { - printf ("%02x", buf[i]); - } - return 0; -} - -static int char_memcpy (void *d, const void *s, int len) -{ - int i; - char *cd = d; - const char *cs = s; - - for (i = 0; i < len; i++) { - *(cd++) = *(cs++); - } - return 0; -} - -static int memory_test (char *buf) -{ - const char src[][16] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}, - {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, - 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}, - {0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, - 0x04, 0x04, 0x04, 0x04, 0x04, 0x04}, - {0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, - 0x08, 0x08, 0x08, 0x08, 0x08, 0x08}, - {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, - {0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x20, 0x20}, - {0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, - 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}, - {0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80}, - {0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, - 0x55, 0x55, 0x55, 0x55, 0x55, 0x55}, - {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}, - {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }; - const int foo[] = { 0 }; - int i, j, a; - - printf ("\ntest @ %d %p\n", foo[0], buf); - for (i = 0; i < 12; i++) { - for (a = 0; a < 8; a++) { - const char *s = src[i] + a; - int align = (unsigned) (s) & 0x7; - - /* ecc_off(); */ - memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - /* ecc_off(); */ - char_memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - } - } - - return 0; -} -#endif diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c deleted file mode 100644 index a8add85..0000000 --- a/board/Marvell/common/flash.c +++ /dev/null @@ -1,1072 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * flash.c - flash support for the 512k, 8bit boot flash - and the 8MB 32bit extra flash on the DB64360 - * most of this file was based on the existing U-Boot - * flash drivers. - * - * written or collected and sometimes rewritten by - * Ingo Assmus - * - */ - -#include -#include -#include "../include/mv_gen_reg.h" -#include "../include/memory.h" -#include "intel_flash.h" - -#define FLASH_ROM 0xFFFD /* unknown flash type */ -#define FLASH_RAM 0xFFFE /* unknown flash type */ -#define FLASH_MAN_UNKNOWN 0xFFFF0000 - -/* #define DEBUG */ - -/* Intel flash commands */ -int flash_erase_intel (flash_info_t * info, int s_first, int s_last); -int write_word_intel (bank_addr_t addr, bank_word_t value); - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (int portwidth, vu_long * addr, - flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned int i; - unsigned long size_b0 = 0, size_b1 = 0; - unsigned long base, flash_size; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* the boot flash */ - base = CFG_FLASH_BASE; - size_b0 = - flash_get_size (CFG_BOOT_FLASH_WIDTH, (vu_long *) base, - &flash_info[0]); - - printf ("[%ldkB@%lx] ", size_b0 / 1024, base); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20); - } - - base = memoryGetDeviceBaseAddress (CFG_EXTRA_FLASH_DEVICE); -/* base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/ - for (i = 1; i < CFG_MAX_FLASH_BANKS; i++) { - unsigned long size = - flash_get_size (CFG_EXTRA_FLASH_WIDTH, - (vu_long *) base, &flash_info[i]); - - printf ("[%ldMB@%lx] ", size >> 20, base); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - if (i == 1) { - printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b1, size_b1 << 20); - } - break; - } - size_b1 += size; - base += size; - } - - flash_size = size_b0 + size_b1; - return flash_size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - int sector_size; - - if (!info->sector_count) - return; - - /* set up sector start address table */ - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - case FLASH_28F128J3A: - case FLASH_28F640J3A: - case FLASH_RAM: - /* this chip has uniformly spaced sectors */ - sector_size = info->size / info->sector_count; - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sector_size); - break; - default: - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A (64 Mbit)\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A (128 Mbit)\n"); - break; - case FLASH_ROM: - printf ("ROM\n"); - break; - case FLASH_RAM: - printf ("RAM\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if ((info->size >> 20) > 0) { - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - } else { - printf (" Size: %ld kB in %d Sectors\n", - info->size >> 10, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static inline void flash_cmd (int width, volatile unsigned char *addr, - int offset, unsigned char cmd) -{ - /* supports 1x8, 1x16, and 2x16 */ - /* 2x8 and 4x8 are not supported */ - if (width == 4) { - /* assuming chips are in 16 bit mode */ - /* 2x16 */ - unsigned long cmd32 = (cmd << 16) | cmd; - - *(volatile unsigned long *) (addr + offset * 2) = cmd32; - } else { - /* 1x16 or 1x8 */ - *(volatile unsigned char *) (addr + offset) = cmd; - } -} - -static ulong -flash_get_size (int portwidth, vu_long * addr, flash_info_t * info) -{ - short i; - volatile unsigned char *caddr = (unsigned char *) addr; - volatile unsigned short *saddr = (unsigned short *) addr; - volatile unsigned long *laddr = (unsigned long *) addr; - char old[2], save; - ulong id = 0, manu = 0, base = (ulong) addr; - -#ifdef DEBUG - printf ("%s: enter\n", __FUNCTION__); -#endif - info->portwidth = portwidth; - - save = *caddr; - - flash_cmd (portwidth, caddr, 0, 0xf0); - flash_cmd (portwidth, caddr, 0, 0xf0); - - udelay (10); - - old[0] = caddr[0]; - old[1] = caddr[1]; - - - if (old[0] != 0xf0) { - flash_cmd (portwidth, caddr, 0, 0xf0); - flash_cmd (portwidth, caddr, 0, 0xf0); - - udelay (10); - - if (*caddr == 0xf0) { - /* this area is ROM */ - *caddr = save; - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets (base, info); - return info->size; - } - } else { - *caddr = 0; - - udelay (10); - - if (*caddr == 0) { - /* this area is RAM */ - *caddr = save; - info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets (base, info); - return info->size; - } - flash_cmd (portwidth, caddr, 0, 0xf0); - - udelay (10); - } - - /* Write auto select command: read Manufacturer ID */ - flash_cmd (portwidth, caddr, 0x555, 0xAA); - flash_cmd (portwidth, caddr, 0x2AA, 0x55); - flash_cmd (portwidth, caddr, 0x555, 0x90); - - udelay (10); - - if ((caddr[0] == old[0]) && (caddr[1] == old[1])) { - - /* this area is ROM */ - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets (base, info); - return info->size; -#ifdef DEBUG - } else { - printf ("%px%d: %02x:%02x -> %02x:%02x\n", - caddr, portwidth, old[0], old[1], caddr[0], caddr[1]); -#endif - } - - switch (portwidth) { - case 1: - manu = caddr[0]; - manu |= manu << 16; - id = caddr[1]; - break; - case 2: - manu = saddr[0]; - manu |= manu << 16; - id = saddr[1]; - id |= id << 16; - break; - case 4: - manu = laddr[0]; - id = laddr[1]; - break; - } - -#ifdef DEBUG - flash_cmd (portwidth, caddr, 0, 0xf0); - - printf ("\n%08lx:%08lx:%08lx\n", base, manu, id); - printf ("%08lx %08lx %08lx %08lx\n", - laddr[0], laddr[1], laddr[2], laddr[3]); -#endif - - switch (manu) { - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - flash_cmd (portwidth, caddr, 0, 0xf0); - - printf ("Unknown Mfr [%08lx]:%08lx\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - switch (id) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth = 1; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth = 1; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth = 1; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth = 1; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth = 1; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth = 1; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth = 1; - break; /* => 512 kB */ - - case INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 128 * 1024 * 64; /* 128kbytes x 64 blocks */ - info->chipwidth = 2; - if (portwidth == 4) - info->size *= 2; /* 2x16 */ - break; - - case INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 128 * 1024 * 128; /* 128kbytes x 128 blocks */ - info->chipwidth = 2; - if (portwidth == 4) - info->size *= 2; /* 2x16 */ - break; - - default: - flash_cmd (portwidth, caddr, 0, 0xf0); - - printf ("Unknown id %lx:[%lx]\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->chipwidth = 1; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets (base, info); - - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0)=0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *) (info->start[i]); - saddr = (volatile unsigned short *) (info->start[i]); - laddr = (volatile unsigned long *) (info->start[i]); - if (portwidth == 1) - info->protect[i] = caddr[2] & 1; - else if (portwidth == 2) - info->protect[i] = saddr[2] & 1; - else - info->protect[i] = laddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *) info->start[0]; - - flash_cmd (portwidth, caddr, 0, 0xF0); /* reset bank */ - } - - return (info->size); -} - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile unsigned char *addr = (uchar *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - -/* modified to support 2x16 Intel flash */ -/* Note that the code will not exit on a flash erasure error or timeout */ -/* but will print and error message and continue processing sectors */ -/* until they are all erased. */ -/* 10-16-2002 P. Marchese */ - ulong mask; - int timeout; - - if (info->portwidth == 4) -/* { - printf ("- Warning: erasing of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); - return 1; - }*/ - { - /* make sure it's Intel flash */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - /* yup! it's an Intel flash */ - /* is it 16-bits wide? */ - if (info->chipwidth == 2) { - /* yup! it's 16-bits wide */ - /* are there any sectors to process? */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("Error: There are no sectors to erase\n"); - printf ("Either sector %d is less than zero\n", s_first); - printf ("or sector %d is greater than sector %d\n", s_first, s_last); - return 1; - } - /* check for protected sectors */ - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) - if (info->protect[sect]) - prot++; - /* if variable "prot" is nonzero, there are protected sectors */ - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - /* Clear the status register */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_CLR_STAT); - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - /* is the sector unprotected? */ - if (info->protect[sect] == 0) { /* not protected */ - /* issue the single block erase command, 0x20 */ - flash_cmd (info->portwidth, - (volatile unsigned - char *) info-> - start[sect], 0, - CHIP_CMD_ERASE1); - /* issue the erase confirm command, 0xD0 */ - flash_cmd (info->portwidth, - (volatile unsigned - char *) info-> - start[sect], 0, - CHIP_CMD_ERASE2); - l_sect = sect; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - /* poll for erasure completion */ - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, - addr, 0, - CHIP_CMD_RD_STAT); - /* setup the status register mask */ - mask = CHIP_STAT_RDY | - (CHIP_STAT_RDY << 16); - /* init. the timeout counter */ - start = get_timer (0); - /* keep looping while the flash is not ready */ - /* exit the loop by timing out or the flash */ - /* becomes ready again */ - timeout = 0; - while ((* - (volatile unsigned - long *) info-> - start[sect] & mask) != - mask) { - /* has the timeout limit been reached? */ - if (get_timer (start) - > - CFG_FLASH_ERASE_TOUT) - { - /* timeout limit reached */ - printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]); - printf ("Continuing with next sector\n"); - timeout = 1; - goto timed_out_error; - } - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info-> - portwidth, - addr, 0, - CHIP_CMD_RD_STAT); - } - /* did we timeout? */ - timed_out_error:if (timeout == 0) - { - /* didn't timeout, so check the status register */ - /* create the status mask to check for errors */ - mask = CHIP_STAT_ECLBS; - mask = mask | (mask << - 16); - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info-> - portwidth, - addr, 0, - CHIP_CMD_RD_STAT); - /* are there any errors? */ - if ((* - (volatile - unsigned long *) - info-> - start[sect] & - mask) != 0) { - /* We got an erasure error */ - printf ("Flash erasure error at address 0x%08lx\n", info->start[sect]); - printf ("Continuing with next sector\n"); - /* reset the flash */ - flash_cmd - (info-> - portwidth, - addr, - 0, - CHIP_CMD_RST); - } - } - /* erasure completed without errors */ - /* reset the flash */ - flash_cmd (info->portwidth, - addr, 0, - CHIP_CMD_RST); - } /* end if not protected */ - } /* end for loop */ - printf ("Flash erasure done\n"); - return 0; - } else { - /* The Intel flash is not 16-bit wide */ - /* print and error message and return */ - /* NOTE: you can add routines here to handle other size flash */ - printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8); - printf ("The erasure code only handles Intel 16-bit wide flash memory\n"); - return 1; - } - } else { - /* Not Intel flash so return an error as a write timeout */ - /* NOTE: if it's another type flash, stick its routine here */ - printf ("Error: The flash device is not Intel type\n"); - printf ("The erasure code only supports Intel flash in a 32-bit port width\n"); - return 1; - } - } - - /* end 32-bit wide flash code */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) - return 1; /* Rom can not be erased */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { /* RAM just copy 0s to RAM */ - for (sect = s_first; sect <= s_last; sect++) { - int sector_size = info->size / info->sector_count; - - addr = (uchar *) (info->start[sect]); - memset ((void *) addr, 0, sector_size); - } - return 0; - } - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { /* Intel works spezial */ - return flash_erase_intel (info, - (unsigned short) s_first, - (unsigned short) s_last); - } -#if 0 - if ((info->flash_id == FLASH_UNKNOWN) || /* Flash is unknown to PPCBoot */ - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } -#endif - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - flash_cmd (info->portwidth, addr, 0x555, 0xAA); /* start erase routine */ - flash_cmd (info->portwidth, addr, 0x2AA, 0x55); - flash_cmd (info->portwidth, addr, 0x555, 0x80); - flash_cmd (info->portwidth, addr, 0x555, 0xAA); - flash_cmd (info->portwidth, addr, 0x2AA, 0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (uchar *) (info->start[sect]); - flash_cmd (info->portwidth, addr, 0, 0x30); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile unsigned char *) (info->start[l_sect]); - /* broken for 2x16: TODO */ - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned char *) info->start[0]; - flash_cmd (info->portwidth, addr, 0, 0xf0); - flash_cmd (info->portwidth, addr, 0, 0xf0); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -/* broken for 2x16: TODO */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - -/* Commented out since the below code should work for 32-bit(2x 16 flash) */ -/* 10-16-2002 P. Marchese */ -/* if(info->portwidth==4) return 1; */ -/* if(info->portwidth==4) { - printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); - return 1; - }*/ - - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) - return 0; - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - memcpy ((void *) addr, src, cnt); - return 0; - } - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -/* broken for 2x16: TODO */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile unsigned char *addr = (uchar *) (info->start[0]); - ulong start; - int flag, i; - ulong mask; - -/* modified so that it handles 32-bit(2x16 Intel flash programming */ -/* 10-16-2002 P. Marchese */ - - if (info->portwidth == 4) -/* { - printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); - return 1; - }*/ - { - /* make sure it's Intel flash */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - /* yup! it's an Intel flash */ - /* is it 16-bits wide? */ - if (info->chipwidth == 2) { - /* yup! it's 16-bits wide */ - /* so we know how to program it */ - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - /* Clear the status register */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_CLR_STAT); - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* 1st cycle of word/byte program */ - /* write 0x40 to the location to program */ - flash_cmd (info->portwidth, (uchar *) dest, 0, - CHIP_CMD_PROG); - /* 2nd cycle of word/byte program */ - /* write the data to the destination address */ - *(ulong *) dest = data; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - /* setup the status register mask */ - mask = CHIP_STAT_RDY | (CHIP_STAT_RDY << 16); - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - /* init. the timeout counter */ - start = get_timer (0); - /* keep looping while the flash is not ready */ - /* exit the loop by timing out or the flash */ - /* becomes ready again */ -/* 11-13-2002 Paul Marchese */ -/* modified while loop conditional statement */ -/* because we were always timing out. */ -/* there is a type mismatch, "addr[0]" */ -/* returns a byte but "mask" is a 32-bit value */ - while ((*(volatile unsigned long *) info-> - start[0] & mask) != mask) -/* original code */ -/* while (addr[0] & mask) != mask) */ - { - /* has the timeout limit been reached? */ - if (get_timer (start) > - CFG_FLASH_WRITE_TOUT) { - /* timeout limit reached */ - printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data); - /* reset the flash */ - flash_cmd (info->portwidth, - addr, 0, - CHIP_CMD_RST); - return (1); - } - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - } - /* flash is ready, so check the status */ - /* create the status mask to check for errors */ - mask = CHIP_STAT_DPS | CHIP_STAT_VPPS | - CHIP_STAT_PSLBS; - mask = mask | (mask << 16); - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - /* are there any errors? */ - if ((addr[0] & mask) != 0) { - /* We got a one of the following errors: */ - /* Voltage range, Device protect, or programming */ - /* return the error as a device timeout */ - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - printf ("Flash programming error at address 0x%08lx\n", dest); - printf ("Flash status register contains 0x%08lx\n", (unsigned long) addr[0]); - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - return 1; - } - /* write completed without errors */ - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - return 0; - } else { - /* it's not 16-bits wide, so return an error as a write timeout */ - /* NOTE: you can add routines here to handle other size flash */ - printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8); - printf ("The write code only handles Intel 16-bit wide flash memory\n"); - return 1; - } - } else { - /* not Intel flash so return an error as a write timeout */ - /* NOTE: if it's another type flash, stick its routine here */ - printf ("Error: The flash device is not Intel type\n"); - printf ("The code only supports Intel flash in a 32-bit port width\n"); - return 1; - } - } - - /* end of 32-bit flash code */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) - return 1; - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - *(unsigned long *) dest = data; - return 0; - } - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - unsigned short low = data & 0xffff; - unsigned short hi = (data >> 16) & 0xffff; - int ret = write_word_intel ((bank_addr_t) dest, hi); - - if (!ret) - ret = write_word_intel ((bank_addr_t) (dest + 2), - low); - - return ret; - } - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* first, perform an unlock bypass command to speed up flash writes */ - addr[0x555] = 0xAA; - addr[0x2AA] = 0x55; - addr[0x555] = 0x20; - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *) &data; - - addr[0] = 0xA0; - *(((char *) dest) + i) = data_ch[i]; - udelay (10); /* XXX */ - } - - /* we're done, now do an unlock bypass reset */ - addr[0] = 0x90; - addr[0] = 0x00; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c deleted file mode 100644 index 32b2b30..0000000 --- a/board/Marvell/common/i2c.c +++ /dev/null @@ -1,532 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for the DB64360 board by Ingo.Assmus@keymile.com - * extra improvments by Brain Waite - */ -#include -#include -#include -#include "../include/mv_gen_reg.h" -#include "../include/core.h" - -#define MAX_I2C_RETRYS 10 -#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */ -#undef DEBUG_I2C -/*#define DEBUG_I2C*/ - -#ifdef DEBUG_I2C -#define DP(x) x -#else -#define DP(x) -#endif - -/* Assuming that there is only one master on the bus (us) */ - -static void i2c_init (int speed, int slaveaddr) -{ - unsigned int n, m, freq, margin, power; - unsigned int actualN = 0, actualM = 0; - unsigned int control, status; - unsigned int minMargin = 0xffffffff; - unsigned int tclk = CFG_TCLK; - unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ - - DP (puts ("i2c_init\n")); -/* gtI2cMasterInit */ - for (n = 0; n < 8; n++) { - for (m = 0; m < 16; m++) { - power = 2 << n; /* power = 2^(n+1) */ - freq = tclk / (10 * (m + 1) * power); - if (i2cFreq > freq) - margin = i2cFreq - freq; - else - margin = freq - i2cFreq; - if (margin < minMargin) { - minMargin = margin; - actualN = n; - actualM = m; - } - } - } - - DP (puts ("setup i2c bus\n")); - - /* Setup bus */ -/* gtI2cReset */ - GT_REG_WRITE (I2C_SOFT_RESET, 0); - - DP (puts ("udelay...\n")); - - udelay (I2C_DELAY); - - DP (puts ("set baudrate\n")); - - GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); - GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); - - udelay (I2C_DELAY * 10); - - DP (puts ("read control, baudrate\n")); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - GT_REG_READ (I2C_CONTROL, &control); -} - -static uchar i2c_start (void) -{ /* DB64360 checked -> ok */ - unsigned int control, status; - int count = 0; - - DP (puts ("i2c_start\n")); - - /* Set the start bit */ - -/* gtI2cGenerateStartBit() */ - - GT_REG_READ (I2C_CONTROL, &control); - control |= (0x1 << 5); /* generate the I2C_START_BIT */ - GT_REG_WRITE (I2C_CONTROL, control); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - - count = 0; - while ((status & 0xff) != 0x08) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - return (0); -} - -static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit) -{ - unsigned int status, data, bits = 7; - int count = 0; - - DP (puts ("i2c_select_device\n")); - - /* Output slave address */ - - if (ten_bit) { - bits = 10; - } - - data = (dev_addr << 1); - /* set the read bit */ - data |= read; - GT_REG_WRITE (I2C_DATA, data); - /* assert the address */ - RESET_REG_BITS (I2C_CONTROL, BIT3); - - udelay (I2C_DELAY); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count = 0; - while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - if (bits == 10) { - printf ("10 bit I2C addressing not yet implemented\n"); - return (0xff); - } - - return (0); -} - -static uchar i2c_get_data (uchar * return_data, int len) -{ - - unsigned int data, status = 0; - int count = 0; - - DP (puts ("i2c_get_data\n")); - - while (len) { - - /* Get and return the data */ - - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - - udelay (I2C_DELAY * 5); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x50) { - udelay (I2C_DELAY); - if (count > 2) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return 0; - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_READ (I2C_DATA, &data); - len--; - *return_data = (uchar) data; - return_data++; - } - RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3); - while ((status & 0xff) != 0x58) { - udelay (I2C_DELAY); - if (count > 200) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */ - - return (0); -} - -static uchar i2c_write_data (unsigned int *data, int len) -{ - unsigned int status; - int count = 0; - unsigned int temp; - unsigned int *temp_ptr = data; - - DP (puts ("i2c_write_data\n")); - - while (len) { - temp = (unsigned int) (*temp_ptr); - GT_REG_WRITE (I2C_DATA, temp); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - - udelay (I2C_DELAY); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } -/* 11-14-2002 Paul Marchese */ -/* Can't have the write issuing a stop command */ -/* it's wrong to have a stop bit in read stream or write stream */ -/* since we don't know if it's really the end of the command */ -/* or whether we have just send the device address + offset */ -/* we will push issuing the stop command off to the original */ -/* calling function */ - /* set the interrupt bit in the control register */ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 3)); - udelay (I2C_DELAY * 10); - return (0); -} - -/* 11-14-2002 Paul Marchese */ -/* created this function to get the i2c_write() */ -/* function working properly. */ -/* function to write bytes out on the i2c bus */ -/* this is identical to the function i2c_write_data() */ -/* except that it requires a buffer that is an */ -/* unsigned character array. You can't use */ -/* i2c_write_data() to send an array of unsigned characters */ -/* since the byte of interest ends up on the wrong end of the bus */ -/* aah, the joys of big endian versus little endian! */ -/* */ -/* returns 0 = success */ -/* anything other than zero is failure */ -static uchar i2c_write_byte (unsigned char *data, int len) -{ - unsigned int status; - int count = 0; - unsigned int temp; - unsigned char *temp_ptr = data; - - DP (puts ("i2c_write_byte\n")); - - while (len) { - /* Set and assert the data */ - temp = *temp_ptr; - GT_REG_WRITE (I2C_DATA, temp); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - - udelay (I2C_DELAY); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } -/* Can't have the write issuing a stop command */ -/* it's wrong to have a stop bit in read stream or write stream */ -/* since we don't know if it's really the end of the command */ -/* or whether we have just send the device address + offset */ -/* we will push issuing the stop command off to the original */ -/* calling function */ -/* GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4)); - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */ - /* set the interrupt bit in the control register */ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 3)); - udelay (I2C_DELAY * 10); - - return (0); -} - -static uchar -i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit, - int alen) -{ - uchar status; - unsigned int table[2]; - -/* initialize the table of address offset bytes */ -/* utilized for 2 byte address offsets */ -/* NOTE: the order is high byte first! */ - table[1] = offset & 0xff; /* low byte */ - table[0] = offset / 0x100; /* high byte */ - - DP (puts ("i2c_set_dev_offset\n")); - - status = i2c_select_device (dev_addr, 0, ten_bit); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to select device setting offset: 0x%02x\n", - status); -#endif - return status; - } -/* check the address offset length */ - if (alen == 0) - /* no address offset */ - return (0); - else if (alen == 1) { - /* 1 byte address offset */ - status = i2c_write_data (&offset, 1); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else if (alen == 2) { - /* 2 bytes address offset */ - status = i2c_write_data (table, 2); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else { - /* address offset unknown or not supported */ - printf ("Address length offset %d is not supported\n", alen); - return 1; - } - return 0; /* sucessful completion */ -} - -uchar -i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; - - DP (puts ("i2c_read\n")); - - i2c_init (i2cFreq, 0); /* set the i2c frequency */ - - status = i2c_start (); - - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction start failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - i2c_init (i2cFreq, 0); /* set the i2c frequency again */ - - status = i2c_start (); - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction restart failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_select_device (dev_addr, 1, 0); /* send the slave address */ - if (status) { -#ifdef DEBUG_I2C - printf ("Address not acknowledged: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_get_data (data, len); - if (status) { -#ifdef DEBUG_I2C - printf ("Data not recieved: 0x%02x\n", status); -#endif - return status; - } - - return 0; -} - -/* 11-14-2002 Paul Marchese */ -/* Function to set the I2C stop bit */ -void i2c_stop (void) -{ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); -} - -/* 11-14-2002 Paul Marchese */ -/* I2C write function */ -/* dev_addr = device address */ -/* offset = address offset */ -/* alen = length in bytes of the address offset */ -/* data = pointer to buffer to read data into */ -/* len = # of bytes to read */ -/* */ -/* returns 0 = succesful */ -/* anything but zero is failure */ -uchar -i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; - - DP (puts ("i2c_write\n")); - - i2c_init (i2cFreq, 0); /* set the i2c frequency */ - - status = i2c_start (); /* send a start bit */ - - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction start failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - - status = i2c_write_byte (data, len); /* write the data */ - if (status) { -#ifdef DEBUG_I2C - printf ("Data not written: 0x%02x\n", status); -#endif - return status; - } - /* issue a stop bit */ - i2c_stop (); - return 0; -} - -/* 11-14-2002 Paul Marchese */ -/* function to determine if an I2C device is present */ -/* chip = device address of chip to check for */ -/* */ -/* returns 0 = sucessful, the device exists */ -/* anything other than zero is failure, no device */ -int i2c_probe (uchar chip) -{ - - /* We are just looking for an back. */ - /* To see if the device/chip is there */ - -#ifdef DEBUG_I2C - unsigned int i2c_status; -#endif - uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; - - DP (puts ("i2c_probe\n")); - - i2c_init (i2cFreq, 0); /* set the i2c frequency */ - - status = i2c_start (); /* send a start bit */ - - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction start failed: 0x%02x\n", status); -#endif - return (int) status; - } - - status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address: 0x%02x\n", status); -#endif - return (int) status; - } -#ifdef DEBUG_I2C - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status); - printf ("address %#x returned %#x\n", chip, i2c_status); -#endif - /* issue a stop bit */ - i2c_stop (); - return 0; /* successful completion */ -} diff --git a/board/Marvell/common/i2c.h b/board/Marvell/common/i2c.h deleted file mode 100644 index b669ff0..0000000 --- a/board/Marvell/common/i2c.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for the DB64360 board by Ingo.Assmus@keymile.com - */ - -#ifndef __I2C_H__ -#define __I2C_H__ - -/* function declarations */ -uchar i2c_read(uchar, unsigned int, int, uchar*, int); - -#endif diff --git a/board/Marvell/common/intel_flash.c b/board/Marvell/common/intel_flash.c deleted file mode 100644 index d26f883..0000000 --- a/board/Marvell/common/intel_flash.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for the marvell db64360 eval board by - * Ingo Assmus - */ - -#include -#include -#include "../include/mv_gen_reg.h" -#include "../include/memory.h" -#include "intel_flash.h" - - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -static void bank_reset (flash_info_t * info, int sect) -{ - bank_addr_t addrw, eaddrw; - - addrw = (bank_addr_t) info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD (addrw); - - while (addrw < eaddrw) { -#ifdef FLASH_DEBUG - printf (" writing reset cmd to addr 0x%08lx\n", - (unsigned long) addrw); -#endif - *addrw = BANK_CMD_RST; - addrw++; - } -} - -static void bank_erase_init (flash_info_t * info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int flag; - -#ifdef FLASH_DEBUG - printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG); - printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1); - printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2); - printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT); - printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST); - printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY); - printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR); -#endif - - saddrw = (bank_addr_t) info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD (saddrw); - -#ifdef FLASH_DEBUG - printf ("erasing sector %d, start addr = 0x%08lx " - "(bank next word addr = 0x%08lx)\n", sect, - (unsigned long) saddrw, (unsigned long) eaddrw); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts (); - - for (addrw = saddrw; addrw < eaddrw; addrw++) { -#ifdef FLASH_DEBUG - printf (" writing erase cmd to addr 0x%08lx\n", - (unsigned long) addrw); -#endif - *addrw = BANK_CMD_ERASE1; - *addrw = BANK_CMD_ERASE2; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); -} - -static int bank_erase_poll (flash_info_t * info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int sectdone, haderr; - - saddrw = (bank_addr_t) info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD (saddrw); - - sectdone = 1; - haderr = 0; - - for (addrw = saddrw; addrw < eaddrw; addrw++) { - bank_word_t stat = *addrw; - -#ifdef FLASH_DEBUG - printf (" checking status at addr " - "0x%08x [0x%08x]\n", (unsigned long) addrw, stat); -#endif - if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY) - sectdone = 0; - else if ((stat & BANK_STAT_ERR) != 0) { - printf (" failed on sector %d " - "(stat = 0x%08x) at " - "address 0x%p\n", sect, stat, addrw); - *addrw = BANK_CMD_CLR_STAT; - haderr = 1; - } - } - - if (haderr) - return (-1); - else - return (sectdone); -} - -int write_word_intel (bank_addr_t addr, bank_word_t value) -{ - bank_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = BANK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); - - if ((stat & BANK_STAT_ERR) != 0) { - printf ("flash program failed (stat = 0x%08lx) " - "at address 0x%08lx\n", (ulong) stat, (ulong) addr); - *addr = BANK_CMD_CLR_STAT; - retval = 3; - } - - done: - /* reset to read mode */ - *addr = BANK_CMD_RST; - - return (retval); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase_intel (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - -#ifdef FLASH_DEBUG - printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info (info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - bank_erase_init (info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer (start); - - do { - now = get_timer (start); - - if (now - estart > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - break; - } -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = bank_erase_poll (info, sect); - - if (sectdone < 0) { - haderr = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) - printf (" failed\n"); - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - bank_reset (info, sect); - } - } - return haderr; -} diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h deleted file mode 100644 index 666a4cd..0000000 --- a/board/Marvell/common/intel_flash.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for the marvell db64360 eval board by - * Ingo Assmus - */ - -/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ - -/* - * acceptable chips types are: - * - * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A - */ - -/* register addresses, valid only following an CHIP_CMD_RD_ID command */ -#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */ -#define CHIP_ADDR_REG_DEV 0x000001 /* device id */ -#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */ -#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */ - -/* Commands */ -#define CHIP_CMD_RST 0xFF /* reset flash */ -#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */ -#define CHIP_CMD_RD_STAT 0x70 /* read the status register */ -#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */ -#define CHIP_CMD_PROG 0x40 /* program word command */ -#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */ -#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */ -#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ -#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */ -#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ -#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ -#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ - -/* status register bits */ -#define CHIP_STAT_DPS 0x02 /* Device Protect Status */ -#define CHIP_STAT_VPPS 0x08 /* VPP Status */ -#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ -#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ -#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */ -#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ - -#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \ - CHIP_STAT_ECLBS | CHIP_STAT_PSLBS) - -/* ID and Lock Configuration */ -#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ -#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define CHIP_RD_ID_DEV CFG_FLASH_ID - -/* dimensions */ -#define CHIP_WIDTH 2 /* chips are in 16 bit mode */ -#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */ -#define CHIP_NBLOCKS 128 -#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */ -#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS) - -/********************** DEFINES for Hymod Flash ******************************/ - -/* - * The hymod board has 2 x 28F320J5 chips running in - * 16 bit mode, for a 32 bit wide bank. - */ - -typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */ -typedef volatile bank_word_t *bank_addr_t; -typedef unsigned long bank_size_t; /* want this big - >= 32 bit */ - -#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */ -#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */ - -#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH) -#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT) -#define BANK_NBLOCKS CHIP_NBLOCKS -#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH) -#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH) - -#define MAX_BANKS 1 /* only one bank possible */ - -/* align bank addresses and sizes to bank word boundaries */ -#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_WIDTH - 1))) -#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \ - (bank_size_t)(s) + (BANK_WIDTH - 1))) - -/* align bank addresses and sizes to bank block boundaries */ -#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_BLKSZ - 1))) -#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \ - (bank_size_t)(s) + (BANK_BLKSZ - 1))) - -/* align bank addresses and sizes to bank boundaries */ -#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_SIZE - 1))) -#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \ - (bank_size_t)(s) + (BANK_SIZE - 1))) - -/* add an offset to a bank address */ -#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \ - (bank_size_t)(o)) - -/* get base address of bank b, given flash base address a */ -#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - (bank_size_t)(b) * BANK_SIZE) - -/* adjust a bank address to start of next word, block or bank */ -#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ - BANK_WIDTH) -#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ - BANK_BLKSZ) -#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - BANK_SIZE) - -/* get bank address of chip register r given a bank base address a */ -#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - ((bank_size_t)(r) << BANK_WSHIFT)) - -/* make a bank address for each chip register address */ - -#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN) -#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV) -#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM) -#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b)) - -/* - * replicate a chip cmd/stat/rd value into each byte position within a word - * so that multiple chips are accessed in a single word i/o operation - * - * this must be as wide as the bank_word_t type, and take into account the - * chip width and bank layout - */ - -#define BANK_FILL_WORD(o) ((bank_word_t)(o)) - -/* make a bank word value for each chip cmd/stat/rd value */ - -/* Commands */ -#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST) -#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID) -#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT) -#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT) -#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1) -#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2) -#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG) -#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK) -#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK) -#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR) -#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS) -#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS) -#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS) -#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS) -#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS) -#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS) -#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY) - -#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR) - -/* ID and Lock Configuration */ -#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK) -#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN) -#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV) diff --git a/board/Marvell/common/memory.c b/board/Marvell/common/memory.c deleted file mode 100644 index 45353af..0000000 --- a/board/Marvell/common/memory.c +++ /dev/null @@ -1,1390 +0,0 @@ -/* - * Copyright - Galileo technology. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * written or collected and sometimes rewritten by - * Ingo Assmus - * - */ - - -#include -#include "../include/core.h" -#include "../include/memory.h" - -/******************************************************************************* -* memoryGetBankBaseAddress - Returns the base address of a memory bank. -* DESCRIPTION: -* This function returns the base address of one of the SDRAM’s memory -* banks. There are 4 memory banks and each one represents one DIMM side. -* INPUT: -* MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit Memory bank base address. -*******************************************************************************/ -static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank) -{ - switch (bank) { - case BANK0: - return SCS_0_LOW_DECODE_ADDRESS; - case BANK1: - return SCS_1_LOW_DECODE_ADDRESS; - case BANK2: - return SCS_2_LOW_DECODE_ADDRESS; - case BANK3: - return SCS_3_LOW_DECODE_ADDRESS; - - } - return SCS_0_LOW_DECODE_ADDRESS; /* default value */ -} - -unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank) -{ - unsigned int base; - unsigned int regOffset = memoryGetBankRegOffset (bank); - - GT_REG_READ (regOffset, &base); - base = base << 16; /* MV6436x */ - return base; -} - -/******************************************************************************* -* memoryGetDeviceBaseAddress - Returns the base address of a device. -* DESCRIPTION: -* This function returns the base address of a device on the system. There -* are 5 possible devices (0 - 4 and one boot device) as defined in -* gtMemory.h. Each of the device parameters is maped to one of the CS -* (Devices chip selects) base address register. -* INPUT: -* device - Selects one of the five devices as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit Device base address. -* -*******************************************************************************/ -static unsigned int memoryGetDeviceRegOffset (DEVICE device) -{ - switch (device) { - case DEVICE0: - return CS_0_LOW_DECODE_ADDRESS; - case DEVICE1: - return CS_1_LOW_DECODE_ADDRESS; - case DEVICE2: - return CS_2_LOW_DECODE_ADDRESS; - case DEVICE3: - return CS_3_LOW_DECODE_ADDRESS; - case BOOT_DEVICE: - return BOOTCS_LOW_DECODE_ADDRESS; - } - return CS_0_LOW_DECODE_ADDRESS; /* default value */ -} - -unsigned int memoryGetDeviceBaseAddress (DEVICE device) -{ - unsigned int regBase; - unsigned int regOffset = memoryGetDeviceRegOffset (device); - - GT_REG_READ (regOffset, ®Base); - - regBase = regBase << 16; /* MV6436x */ - return regBase; -} - -/******************************************************************************* -* MemoryGetPciBaseAddr - Returns the base address of a PCI window. -* DESCRIPTION: -* This function returns the base address of a PCI window. There are 5 -* possible PCI windows (memory 0 - 3 and one for I/O) for each PCI -* interface as defined in gtMemory.h, used by the CPU's address decoding -* mechanism. -* New in MV6436x -* INPUT: -* pciWindow - Selects one of the PCI windows as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit PCI window base address. -*******************************************************************************/ -unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow) -{ - unsigned int baseAddrReg, base; - - switch (pciWindow) { - case PCI_0_IO: - baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */ - break; - case PCI_0_MEM0: - baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */ - break; - case PCI_0_MEM1: - baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */ - break; - case PCI_0_MEM2: - baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */ - break; - case PCI_0_MEM3: - baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */ - break; -#ifdef INCLUDE_PCI_1 - case PCI_1_IO: - baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */ - break; - case PCI_1_MEM0: - baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */ - break; - case PCI_1_MEM1: - baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */ - break; - case PCI_1_MEM2: - baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */ - break; - case PCI_1_MEM3: - baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */ - break; -#endif /* INCLUDE_PCI_1 */ - default: - return 0xffffffff; - } - GT_REG_READ (baseAddrReg, &base); - return (base << 16); -} - -/******************************************************************************* -* memoryGetBankSize - Returns the size of a memory bank. -* DESCRIPTION: -* This function returns the size of memory bank as described in -* 'gtMemoryGetBankBaseAddress' function. -* INPUT: -* bank - Selects one of the four banks as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit size memory bank size or 0 for a closed or non populated bank. -* -*******************************************************************************/ -unsigned int memoryGetBankSize (MEMORY_BANK bank) -{ - unsigned int sizeReg, size; - MEMORY_WINDOW window; - - switch (bank) { - case BANK0: - sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /* CS_0_SIZE; */ - window = CS_0_WINDOW; - break; - case BANK1: - sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /* CS_1_SIZE; */ - window = CS_1_WINDOW; - break; - case BANK2: - sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /* CS_2_SIZE; */ - window = CS_2_WINDOW; - break; - case BANK3: - sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /* CS_3_SIZE; */ - window = CS_3_WINDOW; - break; - default: - return 0; - break; - } - /* If the window is closed, a size of 0 is returned */ - if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED) - return 0; - GT_REG_READ (sizeReg, &size); - size = ((size << 16) | 0xffff) + 1; - return size; -} - -/******************************************************************************* -* memoryGetDeviceSize - Returns the size of a device memory space. -* DESCRIPTION: -* This function returns the memory space size of a given device. -* INPUT: -* device - Selects one of the five devices as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit size of a device memory space. -*******************************************************************************/ -unsigned int memoryGetDeviceSize (DEVICE device) -{ - unsigned int sizeReg, size; - MEMORY_WINDOW window; - - switch (device) { - case DEVICE0: - sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */ - window = DEVCS_0_WINDOW; - break; - case DEVICE1: - sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */ - window = DEVCS_1_WINDOW; - break; - case DEVICE2: - sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */ - window = DEVCS_2_WINDOW; - break; - case DEVICE3: - sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */ - window = DEVCS_3_WINDOW; - break; - case BOOT_DEVICE: - sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */ - window = BOOT_CS_WINDOW; - break; - default: - return 0; - break; - } - /* If the window is closed, a size of 0 is returned */ - if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED) - return 0; - GT_REG_READ (sizeReg, &size); - size = ((size << 16) | 0xffff) + 1; - return size; -} - -/******************************************************************************* -* MemoryGetPciWindowSize - Returns the size of a PCI memory window. -* DESCRIPTION: -* This function returns the size of a PCI window. -* INPUT: -* pciWindow - Selects one of the PCI memory windows as defined in -* Memory.h. -* OUTPUT: -* None. -* RETURN: -* 32 bit size of a PCI memory window. -*******************************************************************************/ -unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow) -{ - unsigned int sizeReg, size; - - switch (pciWindow) { - case PCI_0_IO: - sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */ - break; - case PCI_0_MEM0: - sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */ - break; - case PCI_0_MEM1: - sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */ - break; - case PCI_0_MEM2: - sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */ - break; - case PCI_0_MEM3: - sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */ - break; -#ifdef INCLUDE_PCI_1 - case PCI_1_IO: - sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */ - break; - case PCI_1_MEM0: - sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */ - break; - case PCI_1_MEM1: - sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */ - break; - case PCI_1_MEM2: - sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */ - break; - case PCI_1_MEM3: - sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */ - break; -#endif /* INCLUDE_PCI_1 */ - default: - return 0x0; - } - /* If the memory window is disabled, retrun size = 0 */ - if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow) - == MEM_WINDOW_DISABLED) - return 0; - GT_REG_READ (sizeReg, &size); - size = ((size << 16) | 0xffff) + 1; - return size; -} - -/******************************************************************************* -* memoryGetDeviceWidth - Returns the width of a given device. -* DESCRIPTION: -* The MV's device interface supports up to 32 Bit wide devices. A device -* can have a 1, 2, 4 or 8 Bytes data width. This function returns the -* width of a device as defined by the user or the operating system. -* INPUT: -* device - Selects one of the five devices as defined in Memory.h. -* OUTPUT: -* None. -* RETURN: -* Device width in Bytes (1,2,4 or 8), 0 if error had occurred. -*******************************************************************************/ -unsigned int memoryGetDeviceWidth (DEVICE device) -{ - unsigned int width; - unsigned int regValue; - - GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, ®Value); - width = (regValue & (BIT20 | BIT21)) >> 20; - return (BIT0 << width); -} - -/******************************************************************************* -* memoryMapBank - Set new base address and size for one of the memory -* banks. -* -* DESCRIPTION: -* The CPU interface address decoding map consists of 21 address windows -* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each -* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte -* space. Each address window is defined by two registers - base and size. -* The CPU address is compared with the values in the various CPU windows -* until a match is found and the address is than targeted to that window. -* This function sets new base and size for one the memory banks -* (CS0 - CS3). It is the programmer`s responsibility to make sure that -* there are no conflicts with other memory spaces. When two memory spaces -* overlap, the MV’s behavior is not defined .If a bank needs to be closed, -* set the ’bankLength’ parameter size to 0x0. -* -* INPUT: -* bank - One of the memory banks (CS0-CS3) as defined in gtMemory.h. -* bankBase - The memory bank base address. -* bankLength - The memory bank size. This function will decrement the -* 'bankLength' parameter by one and then check if the size is -* valid. A valid size must be programed from LSB to MSB as -* sequence of ‘1’s followed by sequence of ‘0’s. -* To close a memory window simply set the size to 0. -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* OUTPUT: -* None. -* RETURN: -* False for invalid size, true otherwise. -* -* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!! -* -*******************************************************************************/ - -bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase, - unsigned int bankLength) -{ - unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift; - -/* PCI_INTERNAL_BAR pciBAR; */ - - switch (bank) { - case BANK0: - baseReg = SCS_0_LOW_DECODE_ADDRESS; /*CS_0_BASE_ADDR; */ - sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /*CS_0_SIZE; */ -/* pciBAR = PCI_CS0_BAR; */ - break; - case BANK1: - baseReg = SCS_1_LOW_DECODE_ADDRESS; /*CS_1_BASE_ADDR; */ - sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /*CS_1_SIZE; */ - /* pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */ - break; - case BANK2: - baseReg = SCS_2_LOW_DECODE_ADDRESS; /*CS_2_BASE_ADDR; */ - sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /*CS_2_SIZE; */ -/* pciBAR = PCI_CS2_BAR;*/ - break; - case BANK3: - baseReg = SCS_3_LOW_DECODE_ADDRESS; /*CS_3_BASE_ADDR; */ - sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /*CS_3_SIZE; */ -/* pciBAR = PCI_CS3_BAR; */ - break; - default: - return false; - } - /* If the size is 0, the window will be disabled */ - if (bankLength == 0) { - MemoryDisableWindow (CS_0_WINDOW << bank); - /* Disable the BAR from the PCI slave side */ -/* gtPci0DisableInternalBAR(pciBAR); */ -/* gtPci1DisableInternalBAR(pciBAR); */ - return true; - } - /* The base address must be aligned to the size */ - if ((bankBase % bankLength) != 0) { - return false; - } - if (bankLength >= MINIMUM_MEM_BANK_SIZE) { - newBase = bankBase >> 16; - newSize = bankLength >> 16; - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - temp = newSize - 1; - for (rShift = 0; rShift < 16; rShift++) { - temp = temp >> rShift; - if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ - /* or the size is not valid */ - if (temp > 0x0) - return false; - else - break; - } - } -#ifdef DEBUG - { - unsigned int oldBase, oldSize; - - GT_REG_READ (baseReg, &oldBase); - GT_REG_READ (sizeReg + 8, &oldSize); - - printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n", - bank, oldBase, oldSize, newBase, newSize); - } -#endif - /* writing the new values */ - GT_REG_WRITE (baseReg, newBase); - GT_REG_WRITE (sizeReg, newSize - 1); - /* Enable back the window */ - MemoryEnableWindow (CS_0_WINDOW << bank); - /* Enable the BAR from the PCI slave side */ -/* gtPci0EnableInternalBAR(pciBAR); */ -/* gtPci1EnableInternalBAR(pciBAR); */ - return true; - } - return false; -} - - -/******************************************************************************* -* memoryMapDeviceSpace - Set new base address and size for one of the device -* windows. -* -* DESCRIPTION: -* The CPU interface address decoding map consists of 21 address windows -* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each -* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte -* space. Each address window is defined by two registers - base and size. -* The CPU address is compared with the values in the various CPU windows -* until a match is found and the address is than targeted to that window. -* This function sets new base and size for one the device windows -* (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure -* that there are no conflicts with other memory spaces. When two memory -* spaces overlap, the MV’s behavior is not defined .If a device window -* needs to be closed, set the 'deviceLength' parameter size to 0x0. -* -* INPUT: -* device - One of the device windows (DEV_CS0-DEV_CS3) as -* defined in gtMemory.h. -* deviceBase - The device window base address. -* deviceLength - The device window size. This function will decrement -* the 'deviceLength' parameter by one and then -* check if the size is valid. A valid size must be -* programed from LSB to MSB as sequence of ‘1’s -* followed by sequence of ‘0’s. -* To close a memory window simply set the size to 0. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* -* OUTPUT: -* None. -* -* RETURN: -* False for invalid size, true otherwise. -* -* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!! -* -*******************************************************************************/ - -bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase, - unsigned int deviceLength) -{ - unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift; - -/* PCI_INTERNAL_BAR pciBAR;*/ - - switch (device) { - case DEVICE0: - baseReg = CS_0_LOW_DECODE_ADDRESS; /*DEV_CS0_BASE_ADDR; */ - sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */ -/* pciBAR = PCI_DEV_CS0_BAR; */ - break; - case DEVICE1: - baseReg = CS_1_LOW_DECODE_ADDRESS; /*DEV_CS1_BASE_ADDR; */ - sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */ -/* pciBAR = PCI_DEV_CS1_BAR; */ - break; - case DEVICE2: - baseReg = CS_2_LOW_DECODE_ADDRESS; /*DEV_CS2_BASE_ADDR; */ - sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */ -/* pciBAR = PCI_DEV_CS2_BAR; */ - break; - case DEVICE3: - baseReg = CS_3_LOW_DECODE_ADDRESS; /*DEV_CS3_BASE_ADDR; */ - sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */ -/* pciBAR = PCI_DEV_CS3_BAR; */ - break; - case BOOT_DEVICE: - baseReg = BOOTCS_LOW_DECODE_ADDRESS; /*BOOTCS_BASE_ADDR; */ - sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */ -/* pciBAR = PCI_BOOT_CS_BAR; */ - break; - default: - return false; - } - if (deviceLength == 0) { - MemoryDisableWindow (DEVCS_0_WINDOW << device); - /* Disable the BAR from the PCI slave side */ -/* gtPci0DisableInternalBAR(pciBAR); */ -/* gtPci1DisableInternalBAR(pciBAR); */ - return true; - } - /* The base address must be aligned to the size */ - if ((deviceBase % deviceLength) != 0) { - return false; - } - if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) { - newBase = deviceBase >> 16; - newSize = deviceLength >> 16; - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - temp = newSize - 1; - for (rShift = 0; rShift < 16; rShift++) { - temp = temp >> rShift; - if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ - /* or the size is not valid */ - if (temp > 0x0) - return false; - else - break; - } - } - /* writing the new values */ - GT_REG_WRITE (baseReg, newBase); - GT_REG_WRITE (sizeReg, newSize - 1); - MemoryEnableWindow (DEVCS_0_WINDOW << device); - /* Enable the BAR from the PCI slave side */ -/* gtPci0EnableInternalBAR(pciBAR); */ -/* gtPci1EnableInternalBAR(pciBAR); */ - return true; - } - return false; -} - -/******************************************************************************* -* MemorySetPciWindow - Set new base address and size for one of the PCI -* windows. -* -* DESCRIPTION: -* The CPU interface address decoding map consists of 21 address windows -* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each -* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte -* space. Each address window is defined by two registers - base and size. -* The CPU address is compared with the values in the various CPU windows -* until a match is found and the address is than targeted to that window. -* This function sets new base and size for one the PCI windows -* (PCI memory0/1/2..). It is the programmer`s responsibility to make sure -* that there are no conflicts with other memory spaces. When two memory -* spaces overlap, the MV’s behavior is not defined .If a PCI window -* needs to be closed, set the 'pciWindowSize' parameter size to 0x0. -* -* INPUT: -* pciWindow - One of the PCI windows as defined in gtMemory.h. -* pciWindowBase - The PCI window base address. -* pciWindowSize - The PCI window size. This function will decrement the -* 'pciWindowSize' parameter by one and then check if the -* size is valid. A valid size must be programed from LSB -* to MSB as sequence of ‘1’s followed by sequence of ‘0’s. -* To close a memory window simply set the size to 0. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* -* OUTPUT: -* None. -* -* RETURN: -* False for invalid size, true otherwise. -* -*******************************************************************************/ -bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase, - unsigned int pciWindowSize) -{ - unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift; - - switch (pciWindow) { - case PCI_0_IO: - baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */ - sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */ - break; - case PCI_0_MEM0: - baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */ - sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */ - break; - case PCI_0_MEM1: - baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */ - sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */ - break; - case PCI_0_MEM2: - baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */ - sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */ - break; - case PCI_0_MEM3: - baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */ - sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */ - break; -#ifdef INCLUDE_PCI_1 - case PCI_1_IO: - baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */ - sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */ - break; - case PCI_1_MEM0: - baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */ - sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */ - break; - case PCI_1_MEM1: - baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */ - sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */ - break; - case PCI_1_MEM2: - baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */ - sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */ - break; - case PCI_1_MEM3: - baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */ - sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */ - break; -#endif /* INCLUDE_PCI_1 */ - default: - return false; - } - if (pciWindowSize == 0) { - MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow); - return true; - } - /* The base address must be aligned to the size */ - if ((pciWindowBase % pciWindowSize) != 0) { - return false; - } - if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) { - pciWindowBase >>= 16; - pciWindowSize >>= 16; - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - temp = pciWindowSize - 1; - for (rShift = 0; rShift < 16; rShift++) { - temp = temp >> rShift; - if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ - /* or the size is not valid */ - if (temp > 0x0) - return false; - else - break; - } - } - GT_REG_WRITE (sizeReg, pciWindowSize - 1); - GT_REG_READ (baseAddrReg, ¤tLow); - pciWindowBase = - (pciWindowBase & 0xfffff) | (currentLow & 0xfff00000); - GT_REG_WRITE (baseAddrReg, pciWindowBase); - MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow); - return true; - } - return false; -} - -/******************************************************************************* -* memoryMapInternalRegistersSpace - Sets new base address for the internal -* registers memory space. -* -* DESCRIPTION: -* This function set new base address for the internal register’s memory -* space (the size is fixed and cannot be modified). The function does not -* handle overlapping with other memory spaces, it is the programer's -* responsibility to ensure that overlapping does not occur. -* When two memory spaces overlap, the MV’s behavior is not defined. -* -* INPUT: -* internalRegBase - new base address for the internal register’s memory -* space. -* -* OUTPUT: -* None. -* -* RETURN: -* true on success, false on failure -* -*******************************************************************************/ -/******************************************************************** -* memoryMapInternalRegistersSpace - Sets new base address for the internals -* registers. -* -* INPUTS: unsigned int internalRegBase - The new base address. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapInternalRegistersSpace (unsigned int internalRegBase) -{ - unsigned int currentValue; - unsigned int internalValue = internalRegBase; - - internalRegBase = (internalRegBase >> 16); - GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue); - internalRegBase = (currentValue & 0xff000000) | internalRegBase; - GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase); - /* initializing also the global variable 'internalRegBaseAddr' */ -/* gtInternalRegBaseAddr = internalValue; */ - INTERNAL_REG_BASE_ADDR = internalValue; - return true; -} - -/******************************************************************************* -* memoryGetInternalRegistersSpace - Returns the internal registers Base -* address. -* -* DESCRIPTION: -* This function returns the base address of the internal register’s -* memory space . -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* 32 bit base address of the internal register’s memory space. -* -*******************************************************************************/ -unsigned int memoryGetInternalRegistersSpace (void) -{ - unsigned int currentValue = 0; - - GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue); - return ((currentValue & 0x000fffff) << 16); -} - -/******************************************************************************* -* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address. -* -* DESCRIPTION: -* The Atlantis incorporate integrated 2Mbit SRAM for general use. This -* funcnion return the SRAM's base address. -* INPUT: -* None. -* OUTPUT: -* None. -* RETURN: -* 32 bit SRAM's base address. -* -*******************************************************************************/ -unsigned int memoryGetInternalSramBaseAddr (void) -{ - return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16); -} - -/******************************************************************************* -* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address. -* -* DESCRIPTION: -* The Atlantis incorporate integrated 2Mbit SRAM for general use. This -* function sets a new base address to the SRAM . -* INPUT: -* sramBaseAddress - The SRAM's base address. -* OUTPUT: -* None. -* RETURN: -* None. -* -*******************************************************************************/ -void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress) -{ - GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16); -} - -/******************************************************************************* -* memorySetProtectRegion - Set protection mode for one of the 8 regions. -* -* DESCRIPTION: -* The CPU interface supports configurable access protection. This includes -* up to eight address ranges defined to a different protection type : -* whether the address range is cacheable or not, whether it is writable or -* not , and whether it is accessible or not. A Low and High registers -* define each window while the minimum address range of each window is -* 1Mbyte. An address driven by the CPU, in addition to the address -* decoding and remapping process, is compared against the eight Access -* Protection Low/High registers , if an address matches one of the windows -* , the MV device checks the transaction type against the protection bits -* defined in CPU Access Protection register, to determine if the access is -* allowed. This function set a protection mode to one of the 8 possible -* regions. -* NOTE: -* The CPU address windows are restricted to a size of 2 power n and the -* start address must be aligned to the window size. For example, if using -* a 16 MB window, the start address bits [23:0] must be 0.The MV's -* internal registers space is not protected, even if the access protection -* windows contain this space. -* -* INPUT: -* region - selects which region to be configured. The values defined in -* gtMemory.h: -* -* - MEM_REGION0 -* - MEM_REGION1 -* - etc. -* -* memAccess - Allows or forbids access (read or write ) to the region. The -* values defined in gtMemory.h: -* -* - MEM_ACCESS_ALLOWED -* - MEM_ACCESS_FORBIDEN -* -* memWrite - CPU write protection to the region. The values defined in -* gtMemory.h: -* -* - MEM_WRITE_ALLOWED -* - MEM_WRITE_FORBIDEN -* -* cacheProtection - Defines whether caching the region is allowed or not. -* The values defined in gtMemory.h: -* -* - MEM_CACHE_ALLOWED -* - MEM_CACHE_FORBIDEN -* -* baseAddress - the region's base Address. -* regionSize - The region's size. This function will decrement the -* 'regionSize' parameter by one and then check if the size -* is valid. A valid size must be programed from LSB to MSB -* as sequence of ‘1’s followed by sequence of ‘0’s. -* To close a memory window simply set the size to 0. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* -* OUTPUT: -* None. -* -* RETURN: -* False for invalid size, true otherwise. -* -*******************************************************************************/ -bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window, - MEMORY_ACCESS memAccess, - MEMORY_ACCESS_WRITE memWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, unsigned int size) -{ - unsigned int dataForReg, temp, rShift; - - if (size == 0) { - GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window), - 0x0); - return true; - } - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size >= MINIMUM_ACCESS_WIN_SIZE) { - baseAddress = ((baseAddress >> 16) & 0xfffff); - dataForReg = baseAddress | ((memAccess << 20) & BIT20) | - ((memWrite << 21) & BIT21) | ((cacheProtection << 22) - & BIT22) | BIT31; - GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window, - dataForReg); - size >>= 16; - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - temp = size - 1; - for (rShift = 0; rShift < 16; rShift++) { - temp = temp >> rShift; - if ((temp & 0x1) == 0) { /* Either we got to the last '1' */ - /* or the size is not valid */ - if (temp > 0x0) - return false; - else - break; - } - } - GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window), - size - 1); - return true; - } - return false; -} - -/******************************************************************************* -* gtMemoryDisableProtectRegion - Disable a protected window. -* -* DESCRIPTION: -* This function disable a protected window set by -* 'gtMemorySetProtectRegion' function. -* -* INPUT: -* window - one of the 4 windows ( defined in gtMemory.h ). -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window) -{ - RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)), - BIT31); -} - -/******************************************************************************* -* memorySetPciRemapValue - Set a remap value to a PCI memory space target. -* -* DESCRIPTION: -* In addition to the address decoding mechanism, the CPU has an address -* remapping mechanism to be used by every PCI decoding window. Each PCI -* window can be remaped to a desired address target according to the remap -* value within the remap register. The address remapping is useful when a -* CPU address range must be reallocated to a different location on the -* PCI bus. Also, it enables CPU access to a PCI agent located above the -* 4Gbyte space. On system boot, each of the PCI memory spaces is maped to -* a defualt value (see CPU interface section in the MV spec for the -* default values). The remap mechanism does not always produce the desired -* address on the PCI bus because of the remap mechanism way of working -* (to fully understand why, please see the 'Address Remapping' section in -* the MV's spec). Therefor, this function sets a desired remap value to -* one of the PCI memory windows and return the effective address that -* should be used when exiting the PCI memory window. You should ALWAYS use -* the returned value by this function when remapping a PCI window and -* exiting it. If for example the base address of PCI0 memory 0 is -* 0x90000000, the size is 0x03ffffff and the remap value is 0x11000000, -* the function will return the value of 0x91000000 that MUST -* be used to exit this memory window in order to achive the deisred -* remapping. -* -* INPUT: -* memoryWindow - One of the PCI memory windows as defined in Memory.h -* remapValueLow - The low remap value. -* remapValueHigh - The high remap value. -* OUTPUT: -* None. -* -* RETURN: -* The effective base address to exit the PCI, or 0xffffffff if one of the -* parameters is erroneous or the effective base address is higher the top -* decode value. -* -*******************************************************************************/ -unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow, - unsigned int remapValueHigh, - unsigned int remapValueLow) -{ - unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0; - unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0; - unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh; - - /* Initializing the base and size variables of the PCI - memory windows */ - switch (memoryWindow) { - case PCI_0_IO: - pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR; - pciMemWindowSizeReg = PCI_0_IO_SIZE; - remapRegLow = PCI_0_IO_ADDR_REMAP; - remapRegHigh = PCI_0_IO_ADDR_REMAP; - break; - case PCI_0_MEM0: - pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR; - pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE; - remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP; - remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP; - break; - case PCI_0_MEM1: - pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR; - pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE; - remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP; - remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP; - break; - case PCI_0_MEM2: - pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR; - pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE; - remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP; - remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP; - break; - case PCI_0_MEM3: - pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR; - pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE; - remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP; - remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP; - break; -#ifdef INCLUDE_PCI_1 - case PCI_1_IO: - pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR; - pciMemWindowSizeReg = PCI_1_IO_SIZE; - remapRegLow = PCI_1_IO_ADDR_REMAP; - remapRegHigh = PCI_1_IO_ADDR_REMAP; - break; - case PCI_1_MEM0: - pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR; - pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE; - remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP; - remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP; - break; - case PCI_1_MEM1: - pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR; - pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE; - remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP; - remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP; - break; - case PCI_1_MEM2: - pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR; - pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE; - remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP; - remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP; - break; - case PCI_1_MEM3: - pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR; - pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE; - remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP; - remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP; - break; -#endif /* INCLUDE_PCI_1 */ - default: - /* Retrun an invalid effective base address */ - return 0xffffffff; - } - /* Writing the remap value to the remap regisers */ - GT_REG_WRITE (remapRegHigh, remapValueHigh); - GT_REG_WRITE (remapRegLow, remapValueLow >> 16); - /* Reading the values from the base address and size registers */ - baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff; - windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff; - /* Start calculating the effective Base Address */ - effectiveBaseAddress = baseAddrValue << 16; - /* The effective base address will be combined from the chopped (if any) - remap value (according to the size value and remap mechanism) and the - window's base address */ - effectiveBaseAddress |= - (((windowSizeValue << 16) | 0xffff) & remapValueLow); - /* If the effectiveBaseAddress exceed the window boundaries return an - invalid value. */ - if (effectiveBaseAddress > - ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff))) - return 0xffffffff; - return effectiveBaseAddress; -} - -/******************************************************************** -* memorySetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency. -* -* -* Inputs: SNOOP_REGION region - One of the four regions. -* SNOOP_TYPE snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* unsigned int baseAddress - Base Address of this region. -* unsigned int topAddress - Top Address of this region. -* Returns: false if one of the parameters is wrong and true else -*********************************************************************/ -/* evb6260 code */ -#if 0 -bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, - MEMORY_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) ) - return false; - snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region; - snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region; - if(regionLength == 0) /* closing the region */ - { - GT_REG_WRITE(snoopXbaseAddress,0x0000ffff); - GT_REG_WRITE(snoopXtopAddress,0); - return true; - } - baseAddress = baseAddress & 0xffff0000; - data = (baseAddress >> 16) | snoopType << 16; - GT_REG_WRITE(snoopXbaseAddress,data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1); - return true; -} -#endif - -/******************************************************************** -* memoryRemapAddress - This fubction used for address remapping. -* -* -* Inputs: regOffset: remap register -* remapValue : -* Returns: false if one of the parameters is erroneous,true otherwise. -* -* Not needed function To_do !!!! -*********************************************************************/ -bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue) -{ - unsigned int valueForReg; - - valueForReg = (remapValue & 0xfff00000) >> 20; - GT_REG_WRITE (remapReg, valueForReg); - return true; -} - -/******************************************************************************* -* memoryGetDeviceParam - Extract the device parameters from the device bank -* parameters register. -* -* DESCRIPTION: -* To allow interfacing with very slow devices and fast synchronous SRAMs, -* each device can be programed to different timing parameters. Each bank -* has its own parameters register. Bank width can be programmed to 8, 16, -* or 32-bits. Bank timing parameters can be programmed to support -* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O -* Controllers). The MV allows you to set timing parameters and width for -* each device through parameters register . -* This function extracts the parameters described from the Device Bank -* parameters register and fills the given 'deviceParam' (defined in -* gtMemory.h) structure with the read data. -* -* INPUT: -* deviceParam - pointer to a structure DEVICE_PARAM (defined in -* Memory.h).For details about each structure field please -* see the device timing parameter section in the MV -* datasheet. -* deviceNum - Select on of the five device banks (defined in -* Memory.h) : -* -* - DEVICE0 -* - DEVICE1 -* - DEVICE2 -* - etc. -* -* OUTPUT: -* None. -* -* RETURN: -* false if one of the parameters is erroneous,true otherwise. -* -*******************************************************************************/ -/******************************************************************** -* memoryGetDeviceParam - This function used for getting device parameters from -* DEVICE BANK PARAMETERS REGISTER -* -* -* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK -* PARAMETERS REGISTER -* - deviceNum : number of device -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ - -bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum) -{ - unsigned int valueOfReg; - unsigned int calcData; - - if (deviceNum > 4) - return false; - GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg); - calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19); - deviceParam->turnOff = calcData; /* Turn Off */ - - calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19); - deviceParam->acc2First = calcData; /* Access To First */ - - calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20); - deviceParam->acc2Next = calcData; /* Access To Next */ - - calcData = - ((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22); - deviceParam->ale2Wr = calcData; /* Ale To Write */ - - calcData = ((0x1c000 & valueOfReg) >> 14) + - ((BIT26 & valueOfReg) >> 23); - deviceParam->wrLow = calcData; /* Write Active */ - - calcData = ((0xe0000 & valueOfReg) >> 17) + - ((BIT27 & valueOfReg) >> 24); - deviceParam->wrHigh = calcData; /* Write High */ - - calcData = ((0x300000 & valueOfReg) >> 20); - deviceParam->deviceWidth = (BIT0 << calcData); /* In bytes */ - calcData = ((0x30000000 & valueOfReg) >> 28); - deviceParam->badrSkew = calcData; /* Cycles gap between BAdr - toggle to read data sample. */ - calcData = ((0x40000000 & valueOfReg) >> 30); - deviceParam->DPEn = calcData; /* Data Parity enable */ - return true; -} - -/******************************************************************************* -* memorySetDeviceParam - Set new parameters for a device. -* -* -* DESCRIPTION: -* To allow interfacing with very slow devices and fast synchronous SRAMs, -* each device can be programed to different timing parameters. Each bank -* has its own parameters register. Bank width can be programmed to 8, 16, -* or 32-bits. Bank timing parameters can be programmed to support -* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O -* Controllers). The MV allows you to set timing parameters and width for -* each device through parameters register. This function set new -* parameters to a device Bank from the delivered structure 'deviceParam' -* (defined in gtMemory.h). The structure must be initialized with data -* prior to the use of these function. -* -* INPUT: -* deviceParam - pointer to a structure DEVICE_PARAM (defined in -* Memory.h).For details about each structure field please -* see the device timing parameter section in the MV -* datasheet. -* deviceNum - Select on of the five device banks (defined in -* Memory.h) : -* -* - DEVICE0 -* - DEVICE1 -* - DEVICE2 -* - etc. -* -* OUTPUT: -* None. -* -* RETURN: -* false if one of the parameters is erroneous,true otherwise. -* -*******************************************************************************/ -/******************************************************************** -* memorySetDeviceParam - This function used for setting device parameters to -* DEVICE BANK PARAMETERS REGISTER -* -* -* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK -* PARAMETERS REGISTER -* - deviceNum : number of device -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ -bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum) -{ - unsigned int valueForReg; - - if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) || - (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) || - (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) || - (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) { - return false; - } - valueForReg = (((deviceParam->turnOff) & 0x7) | - (((deviceParam->turnOff) & 0x8) << 19) | - (((deviceParam->acc2First) & 0xf) << 3) | - (((deviceParam->acc2First) & 0x10) << 19) | - (((deviceParam->acc2Next) & 0xf) << 7) | - (((deviceParam->acc2Next) & 0x10) << 20) | - (((deviceParam->ale2Wr) & 0x7) << 11) | - (((deviceParam->ale2Wr) & 0xf) << 22) | - (((deviceParam->wrLow) & 0x7) << 14) | - (((deviceParam->wrLow) & 0xf) << 23) | - (((deviceParam->wrHigh) & 0x7) << 17) | - (((deviceParam->wrHigh) & 0xf) << 24) | - (((deviceParam->badrSkew) & 0x3) << 28) | - (((deviceParam->DPEn) & 0x1) << 30)); - - /* insert the device width: */ - switch (deviceParam->deviceWidth) { - case 1: - valueForReg = valueForReg | _8BIT; - break; - case 2: - valueForReg = valueForReg | _16BIT; - break; - case 4: - valueForReg = valueForReg | _32BIT; - break; - default: - valueForReg = valueForReg | _8BIT; - break; - } - GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg); - return true; -} - -/******************************************************************************* -* MemoryDisableWindow - Disable a memory space by the disable bit. -* DESCRIPTION: -* This function disables one of the 21 availiable windows dedicated for -* the CPU decoding mechanism. Its possible to combine several windows with -* the OR command. -* INPUT: -* window - One or more of the memory windows (defined in gtMemory.h). -* OUTPUT: -* None. -* RETURN: -* None. -*******************************************************************************/ -void MemoryDisableWindow (MEMORY_WINDOW window) -{ - SET_REG_BITS (BASE_ADDR_ENABLE, window); -} - -/******************************************************************************* -* MemoryEnableWindow - Enable a memory space that was disabled by -* 'MemoryDisableWindow'. -* DESCRIPTION: -* This function enables one of the 21 availiable windows dedicated for the -* CPU decoding mechanism. Its possible to combine several windows with the -* OR command. -* INPUT: -* window - One or more of the memory windows (defined in gtMemory.h). -* OUTPUT: -* None. -* RETURN: -* None. -*******************************************************************************/ -void MemoryEnableWindow (MEMORY_WINDOW window) -{ - RESET_REG_BITS (BASE_ADDR_ENABLE, window); -} - -/******************************************************************************* -* MemoryGetMemWindowStatus - This function check whether the memory window is -* disabled or not. -* DESCRIPTION: -* This function checks if the given memory window is closed . -* INPUT: -* window - One or more of the memory windows (defined in gtMemory.h). -* OUTPUT: -* None. -* RETURN: -* True for a closed window, false otherwise . -*******************************************************************************/ -MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window) -{ - if (GTREGREAD (BASE_ADDR_ENABLE) & window) - return MEM_WINDOW_DISABLED; - return MEM_WINDOW_ENABLED; -} diff --git a/board/Marvell/common/misc.S b/board/Marvell/common/misc.S deleted file mode 100644 index 41c3a95..0000000 --- a/board/Marvell/common/misc.S +++ /dev/null @@ -1,235 +0,0 @@ -#include -#include <74xx_7xx.h> -#include "version.h" - -#include -#include - -#include -#include - -#include "../include/mv_gen_reg.h" - -#ifdef CONFIG_ECC - /* Galileo specific asm code for initializing ECC */ - .globl board_relocate_rom -board_relocate_rom: - mflr r7 - /* update the location of the GT registers */ - lis r11, CFG_GT_REGS@h - /* if we're using ECC, we must use the DMA engine to copy ourselves */ - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - - mtlr r7 - blr - - .globl board_init_ecc -board_init_ecc: - mflr r7 - /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ - - /* now that we're running from ram, init the rest of main memory - * for ECC use */ - lis r8, CFG_MONITOR_LEN@h - ori r8, r8, CFG_MONITOR_LEN@l - - divw r3, r10, r8 - - /* set up the counter, and init the starting address */ - mtctr r3 - li r12, 0 - - /* bytes per transfer */ - mr r5, r8 -about_to_init_ecc: -1: mr r3, r12 - mr r4, r12 - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - add r12, r12, r8 - bdnz 1b - - mtlr r7 - blr - - /* r3: dest addr - * r4: source addr - * r5: byte count - * r11: gt regbase - * trashes: r6, r5 - */ -start_idma_transfer_0: - /* set the byte count, including the OWN bit */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_BYTE_COUNT - stwbrx r5, 0, (r6) - - /* set the source address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS - stwbrx r4, 0, (r6) - - /* set the dest address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS - stwbrx r3, 0, (r6) - - /* set the next record pointer */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0NEXT_RECORD_POINTER - stwbrx r5, 0, (r6) - - /* set the low control register */ - /* bit 9 is NON chained mode, bit 31 is new style descriptors. - bit 12 is channel enable */ - ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) - /* 15 shifted by 16 (oris) == bit 31 */ - oris r5, r5, (1 << 15) - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr - - /* this waits for the bytecount to return to zero, indicating - * that the trasfer is complete */ -wait_for_idma_0: - mr r5, r11 - lis r6, 0xff - ori r6, r6, 0xffff - ori r5, r5, CHANNEL0_DMA_BYTE_COUNT -1: lwbrx r4, 0, (r5) - and. r4, r4, r6 - bne 1b - - blr - - /* this turns off channel 0 of the idma engine */ -stop_idma_engine_0: - /* shut off the DMA engine */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr -#endif - -#ifdef CFG_BOARD_ASM_INIT - /* NOTE: trashes r3-r7 */ - .globl board_asm_init -board_asm_init: - /* just move the GT registers to where they belong */ - lis r3, CFG_DFL_GT_REGS@h - ori r3, r3, CFG_DFL_GT_REGS@l - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l - li r5, INTERNAL_SPACE_DECODE - - /* test to see if we've already moved */ - lwbrx r6, r5, r4 - andi. r6, r6, 0xffff - /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */ -/* rlwinm r7, r4, 8, 16, 31 - rlwinm r7, r4, 12, 16, 31 */ /* original */ - rlwinm r7, r4, 16, 16, 31 - /* -----------------------------------------------------*/ - cmp cr0, r7, r6 - beqlr - - /* nope, have to move the registers */ - lwbrx r6, r5, r3 - andis. r6, r6, 0xffff - or r6, r6, r7 - stwbrx r6, r5, r3 - - /* now, poll for the change */ -1: lwbrx r7, r5, r4 - cmp cr0, r7, r6 - bne 1b - - /* done! */ - blr -#endif - -/* For use of the debug LEDs */ - .global led_on0_relocated -led_on0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC80 - ori r18, r18, 0x8000 - stw r21, 0x0(r18) -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off0_relocated -led_off0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC81 - ori r18, r18, 0x4000 - stw r21, 0x0(r18) -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on0 -led_on0: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0x8000 - stw r18, 0x0(r18) - sync - blr - - .global led_off0 -led_off0: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x4000 - stw r18, 0x0(r18) - sync - blr - - .global led_on1 -led_on1: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0xc000 - stw r18, 0x0(r18) - sync - blr - - .global led_off1 -led_off1: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x8000 - stw r18, 0x0(r18) - sync - blr - - .global led_on2 -led_on2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x0000 - stw r18, 0x0(r18) - sync - blr - - .global led_off2 -led_off2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0xc000 - stw r18, 0x0(r18) - sync - blr diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c deleted file mode 100644 index 475445b..0000000 --- a/board/Marvell/common/ns16550.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * COM1 NS16550 support - * originally from linux source (arch/ppc/boot/ns16550.c) - * modified to use CFG_ISA_MEM and new defines - * - * further modified by Josh Huber to support - * the DUART on the Galileo Eval board. (db64360) - */ - -#include -#include "ns16550.h" - -#ifdef ZUMA_NTL -/* no 16550 device */ -#else -const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0), - (NS16550_t) (CFG_DUART_IO + 0x20) -}; - -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) -{ - volatile struct NS16550 *com_port; - - com_port = (struct NS16550 *) COM_PORTS[chan]; - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - - /* Clear & enable FIFOs */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; - return (com_port); -} - -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor) -{ - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ - - /* Clear & enable FIFOs */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; -} - -void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c) -{ - while ((com_port->lsr & LSR_THRE) == 0); - com_port->thr = c; -} - -unsigned char NS16550_getc (volatile struct NS16550 *com_port) -{ - while ((com_port->lsr & LSR_DR) == 0); - return (com_port->rbr); -} - -int NS16550_tstc (volatile struct NS16550 *com_port) -{ - return ((com_port->lsr & LSR_DR) != 0); -} -#endif diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h deleted file mode 100644 index f2ed2ab..0000000 --- a/board/Marvell/common/ns16550.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * NS16550 Serial Port - * originally from linux source (arch/ppc/boot/ns16550.h) - * modified slightly to - * have addresses as offsets from CFG_ISA_BASE - * added a few more definitions - * added prototypes for ns16550.c - * reduced no of com ports to 2 - * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - * - * further modified to support the DUART in the Galileo eval board - * modifications (c) Josh Huber , Mission Critical Linux, Inc. - */ - -#ifndef __NS16550_H__ -#define __NS16550_H__ - -/* the padding is necessary because on the galileo board the UART is - wired in with the 3 address lines shifted over by 2 bits */ -struct NS16550 -{ - unsigned char rbr; /* 0 = 0-3*/ - int pad1:24; - - unsigned char ier; /* 1 = 4-7*/ - int pad2:24; - - unsigned char fcr; /* 2 = 8-b*/ - int pad3:24; - - unsigned char lcr; /* 3 = c-f*/ - int pad4:24; - - unsigned char mcr; /* 4 = 10-13*/ - int pad5:24; - - unsigned char lsr; /* 5 = 14-17*/ - int pad6:24; - - unsigned char msr; /* 6 =18-1b*/ - int pad7:24; - - unsigned char scr; /* 7 =1c-1f*/ - int pad8:24; -} __attribute__ ((packed)); - -/* aliases */ -#define thr rbr -#define iir fcr -#define dll rbr -#define dlm ier - -#define FCR_FIFO_EN 0x01 /*fifo enable*/ -#define FCR_RXSR 0x02 /*reciever soft reset*/ -#define FCR_TXSR 0x04 /*transmitter soft reset*/ - - -#define MCR_DTR 0x01 -#define MCR_RTS 0x02 -#define MCR_DMA_EN 0x04 -#define MCR_TX_DFR 0x08 - - -#define LCR_WLS_MSK 0x03 /* character length slect mask*/ -#define LCR_WLS_5 0x00 /* 5 bit character length */ -#define LCR_WLS_6 0x01 /* 6 bit character length */ -#define LCR_WLS_7 0x02 /* 7 bit character length */ -#define LCR_WLS_8 0x03 /* 8 bit character length */ -#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define LCR_PEN 0x08 /* Parity eneble*/ -#define LCR_EPS 0x10 /* Even Parity Select*/ -#define LCR_STKP 0x20 /* Stick Parity*/ -#define LCR_SBRK 0x40 /* Set Break*/ -#define LCR_BKSE 0x80 /* Bank select enable*/ - -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -/* useful defaults for LCR*/ -#define LCR_8N1 0x03 - - -#define COM1 0x03F8 -#define COM2 0x02F8 - -volatile struct NS16550 * NS16550_init(int chan, int baud_divisor); -void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c); -unsigned char NS16550_getc(volatile struct NS16550 *com_port); -int NS16550_tstc(volatile struct NS16550 *com_port); -void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor); - -typedef struct NS16550 *NS16550_t; - -extern const NS16550_t COM_PORTS[]; - -#endif diff --git a/board/Marvell/common/ppc_error_no.h b/board/Marvell/common/ppc_error_no.h deleted file mode 100644 index 53687c8..0000000 --- a/board/Marvell/common/ppc_error_no.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus - */ -#ifndef _MV_PPC_ERRNO_H -#define _MV_PPC_ERRNO_H - -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Arg list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ -#define EDEADLK 35 /* Resource deadlock would occur */ -#define ENAMETOOLONG 36 /* File name too long */ -#define ENOLCK 37 /* No record locks available */ -#define ENOSYS 38 /* Function not implemented */ -#define ENOTEMPTY 39 /* Directory not empty */ -#define ELOOP 40 /* Too many symbolic links encountered */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define ENOMSG 42 /* No message of desired type */ -#define EIDRM 43 /* Identifier removed */ -#define ECHRNG 44 /* Channel number out of range */ -#define EL2NSYNC 45 /* Level 2 not synchronized */ -#define EL3HLT 46 /* Level 3 halted */ -#define EL3RST 47 /* Level 3 reset */ -#define ELNRNG 48 /* Link number out of range */ -#define EUNATCH 49 /* Protocol driver not attached */ -#define ENOCSI 50 /* No CSI structure available */ -#define EL2HLT 51 /* Level 2 halted */ -#define EBADE 52 /* Invalid exchange */ -#define EBADR 53 /* Invalid request descriptor */ -#define EXFULL 54 /* Exchange full */ -#define ENOANO 55 /* No anode */ -#define EBADRQC 56 /* Invalid request code */ -#define EBADSLT 57 /* Invalid slot */ -#define EDEADLOCK 58 /* File locking deadlock error */ -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EMULTIHOP 72 /* Multihop attempted */ -#define EDOTDOT 73 /* RFS specific error */ -#define EBADMSG 74 /* Not a data message */ -#define EOVERFLOW 75 /* Value too large for defined data type */ -#define ENOTUNIQ 76 /* Name not unique on network */ -#define EBADFD 77 /* File descriptor in bad state */ -#define EREMCHG 78 /* Remote address changed */ -#define ELIBACC 79 /* Can not access a needed shared library */ -#define ELIBBAD 80 /* Accessing a corrupted shared library */ -#define ELIBSCN 81 /* .lib section in a.out corrupted */ -#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 83 /* Cannot exec a shared library directly */ -#define EILSEQ 84 /* Illegal byte sequence */ -#define ERESTART 85 /* Interrupted system call should be restarted */ -#define ESTRPIPE 86 /* Streams pipe error */ -#define EUSERS 87 /* Too many users */ -#define ENOTSOCK 88 /* Socket operation on non-socket */ -#define EDESTADDRREQ 89 /* Destination address required */ -#define EMSGSIZE 90 /* Message too long */ -#define EPROTOTYPE 91 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 92 /* Protocol not available */ -#define EPROTONOSUPPORT 93 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 96 /* Protocol family not supported */ -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#define EADDRINUSE 98 /* Address already in use */ -#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ -#define ENETDOWN 100 /* Network is down */ -#define ENETUNREACH 101 /* Network is unreachable */ -#define ENETRESET 102 /* Network dropped connection because of reset */ -#define ECONNABORTED 103 /* Software caused connection abort */ -#define ECONNRESET 104 /* Connection reset by peer */ -#define ENOBUFS 105 /* No buffer space available */ -#define EISCONN 106 /* Transport endpoint is already connected */ -#define ENOTCONN 107 /* Transport endpoint is not connected */ -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 109 /* Too many references: cannot splice */ -#define ETIMEDOUT 110 /* Connection timed out */ -#define ECONNREFUSED 111 /* Connection refused */ -#define EHOSTDOWN 112 /* Host is down */ -#define EHOSTUNREACH 113 /* No route to host */ -#define EALREADY 114 /* Operation already in progress */ -#define EINPROGRESS 115 /* Operation now in progress */ -#define ESTALE 116 /* Stale NFS file handle */ -#define EUCLEAN 117 /* Structure needs cleaning */ -#define ENOTNAM 118 /* Not a XENIX named type file */ -#define ENAVAIL 119 /* No XENIX semaphores available */ -#define EISNAM 120 /* Is a named type file */ -#define EREMOTEIO 121 /* Remote I/O error */ -#define EDQUOT 122 /* Quota exceeded */ - -#define ENOMEDIUM 123 /* No medium found */ -#define EMEDIUMTYPE 124 /* Wrong medium type */ - -/* Should never be seen by user programs */ -#define ERESTARTSYS 512 -#define ERESTARTNOINTR 513 -#define ERESTARTNOHAND 514 /* restart if no handler.. */ -#define ENOIOCTLCMD 515 /* No ioctl command */ - -#define _LAST_ERRNO 515 - -#endif diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c deleted file mode 100644 index 9d0d213..0000000 --- a/board/Marvell/common/serial.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * serial.c - serial support for the gal ev board - */ - -/* supports both the 16650 duart and the MPSC */ - -#include -#include -#include "../include/memory.h" -#include "serial.h" - -#ifdef CONFIG_DB64360 -#include "../db64360/mpsc.h" -#endif - -#ifdef CONFIG_DB64460 -#include "../db64460/mpsc.h" -#endif - -#include "ns16550.h" - -#ifdef CONFIG_MPSC - - -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) - int clock_divisor = 230400 / gd->baudrate; -#endif - - mpsc_init (gd->baudrate); - - /* init the DUART chans so that KGDB in the kernel can use them */ -#ifdef CFG_INIT_CHAN1 - NS16550_reinit (COM_PORTS[0], clock_divisor); -#endif -#ifdef CFG_INIT_CHAN2 - NS16550_reinit (COM_PORTS[1], clock_divisor); -#endif - return (0); -} - -void serial_putc (const char c) -{ - if (c == '\n') - mpsc_putchar ('\r'); - - mpsc_putchar (c); -} - -int serial_getc (void) -{ - return mpsc_getchar (); -} - -int serial_tstc (void) -{ - return mpsc_test_char (); -} - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); -} - -#else /* ! CONFIG_MPSC */ - -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = 230400 / gd->baudrate; - -#ifdef CFG_INIT_CHAN1 - (void) NS16550_init (0, clock_divisor); -#endif -#ifdef CFG_INIT_CHAN2 - (void) NS16550_init (1, clock_divisor); -#endif - return (0); -} - -void serial_putc (const char c) -{ - if (c == '\n') - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r'); - - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c); -} - -int serial_getc (void) -{ - return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]); -} - -int serial_tstc (void) -{ - return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]); -} - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = 230400 / gd->baudrate; - -#ifdef CFG_INIT_CHAN1 - NS16550_reinit (COM_PORTS[0], clock_divisor); -#endif -#ifdef CFG_INIT_CHAN2 - NS16550_reinit (COM_PORTS[1], clock_divisor); -#endif -} - -#endif /* CONFIG_MPSC */ - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -void kgdb_serial_init (void) -{ -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif /* CFG_CMD_KGDB */ diff --git a/board/Marvell/common/serial.h b/board/Marvell/common/serial.h deleted file mode 100644 index c7fc8c1..0000000 --- a/board/Marvell/common/serial.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/Marvell/db64360/64360.h b/board/Marvell/db64360/64360.h deleted file mode 100644 index a65e23b..0000000 --- a/board/Marvell/db64360/64360.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * main board support/init for the Galileo Eval board DB64360. - */ - -#ifndef __64360_H__ -#define __64360_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_SINGLE_CPU (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64360_H__ */ diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile deleted file mode 100644 index 768ccdd..0000000 --- a/board/Marvell/db64360/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -SOBJS = ../common/misc.o - -OBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ - mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ - sdram_init.o ../common/intel_flash.o - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/Marvell/db64360/config.mk b/board/Marvell/db64360/config.mk deleted file mode 100644 index 0e42b48..0000000 --- a/board/Marvell/db64360/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# EVB64360 boards -# - -TEXT_BASE = 0xfff00000 diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c deleted file mode 100644 index a2ab2d7..0000000 --- a/board/Marvell/db64360/db64360.c +++ /dev/null @@ -1,936 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com - */ - -/* - * db64360.c - main board support/init for the Galileo Eval board. - */ - -#include -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64360.h" -#include "mv_regs.h" - -#undef DEBUG -/*#define DEBUG */ - -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -extern void flush_data_cache (void); -extern void invalidate_l1_instruction_cache (void); - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; -int display_mem_map (void); - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void my_remap_gt_regs (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - -/* original ppcboot 1.1.6 source - - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -original ppcboot 1.1.6 source end */ - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); -} - -#ifdef CONFIG_PCI - -static void gt_pci_config (void) -{ - unsigned int stat; - unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ - - /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's - * config registers by writing ones to the bus and device. - * We then update the Virtual register with the correct value for the bus and device. - */ - if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - - GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); - - } - if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); - } - - /* Enable master */ - PCI_MASTER_ENABLE (0, SELF); - PCI_MASTER_ENABLE (1, SELF); - - /* Enable PCI0/1 Mem0 and IO 0 disable all others */ - GT_REG_READ (BASE_ADDR_ENABLE, &stat); - stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 - << - 18); - stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); - GT_REG_WRITE (BASE_ADDR_ENABLE, stat); - - /* ronen- add write to pci remap registers for 64460. - in 64360 when writing to pci base go and overide remap automaticaly, - in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); - - /* PCI interface settings */ - /* Timeout set to retry forever */ - GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); - GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); - - /* ronen - enable only CS0 and Internal reg!! */ - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - -/*ronen update the pci internal registers base address.*/ -#ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) - pciWriteConfigReg (stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CFG_GT_REGS); -#endif - -} -#endif - -/* Setup CPU interface paramaters */ -static void gt_cpu_config (void) -{ - cpu_t cpu = get_cpu_type (); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD (CPU_CONFIGURATION); - - /* set the SINGLE_CPU bit see MV64360 P.399 */ -#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ - tmp |= CPU_CONF_SINGLE_CPU; -#endif - - tmp &= ~CPU_CONF_AACK_DELAY_2; - - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - - tmp |= CPU_CONF_PIPELINE; - - GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ - - /* CPU master control register */ - tmp = GTREGREAD (CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command (603e, 750) - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - uchar sram_boot = 0; - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); - - /* No PCI in first release of Port To_do: enable it. */ -#ifdef CONFIG_PCI - gt_pci_config (); -#endif - /* mask all external interrupt sources */ - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - /* new in MV6436x */ - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); - /* --------------------- */ - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - /* does not exist in MV6436x - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - --------------------- */ - - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM ???? - * 1 - RTC ???? - * 2 - UART ???? - * 3 - Flash checked 32Bit Intel Strata - * boot - BootCS checked 8Bit 29LV040B - * - * Zuma - * 0 - Flash - * boot - BootCS - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) - sram_boot = 1; - if (!sram_boot) - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - - memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); - - - /* configure device timing */ -#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */ - if (!sram_boot) - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); -#endif - -#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */ - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); -#endif -#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */ - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); -#endif - -#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CFG_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ -#endif - - - gt_cpu_config (); - - /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); - - GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); - DEBUG_LED0_ON (); - DEBUG_LED1_ON (); - DEBUG_LED2_ON (); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r () -{ - icache_enable (); -#ifdef CFG_L2 - l2cache_enable (); -#endif -#ifdef CONFIG_MPSC - - mpsc_sdma_init (); - mpsc_init2 (); -#endif - -#if 0 - /* disable the dcache and MMU */ - dcache_lock (); -#endif - return 0; -} - -void after_reloc (ulong dest_addr, gd_t * gd) -{ - /* check to see if we booted from the sram. If so, move things - * back to the way they should be. (we're running from main - * memory at this point now */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) { - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M); - } - display_mem_map (); - /* now, jump to the main ppcboot board init code */ - board_init_r (gd, dest_addr); - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * right now, assume borad type. (there is just one...after all) - */ - -int checkboard (void) -{ - int l_type = 0; - - printf ("BOARD: %s\n", CFG_BOARD_NAME); - return (l_type); -} - -/* utility functions */ -void debug_led (int led, int mode) -{ - volatile int *addr = 0; - int dummy; - - if (mode == 1) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x08000); - break; - - case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x0c000); - break; - - case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x10000); - break; - } - } else if (mode == 0) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x14000); - break; - - case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x18000); - break; - - case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x1c000); - break; - } - } - - dummy = *addr; -} - -int display_mem_map (void) -{ - int i, j; - unsigned int base, size, width; - - /* SDRAM */ - printf ("SD (DDR) RAM\n"); - for (i = 0; i <= BANK3; i++) { - base = memoryGetBankBaseAddress (i); - size = memoryGetBankSize (i); - if (size != 0) { - printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", - i, base, size >> 20); - } - } - - /* CPU's PCI windows */ - for (i = 0; i <= PCI_HOST1; i++) { - printf ("\nCPU's PCI %d windows\n", i); - base = pciGetSpaceBase (i, PCI_IO); - size = pciGetSpaceSize (i, PCI_IO); - printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, - size >> 20); - for (j = 0; - j <= - PCI_REGION0 - /*ronen currently only first PCI MEM is used 3 */ ; - j++) { - base = pciGetSpaceBase (i, j); - size = pciGetSpaceSize (i, j); - printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); - } - } - - /* Devices */ - printf ("\nDEVICES\n"); - for (i = 0; i <= DEVICE3; i++) { - base = memoryGetDeviceBaseAddress (i); - size = memoryGetDeviceSize (i); - width = memoryGetDeviceWidth (i) * 8; - printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); - if (i == 0) - printf ("\t- EXT SRAM (actual - 1M)\n"); - else if (i == 1) - printf ("\t- RTC\n"); - else if (i == 2) - printf ("\t- UART\n"); - else - printf ("\t- LARGE FLASH\n"); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize (BOOT_DEVICE); - width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; - printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n", - base, size >> 20, width); - return (0); -} - -/* DRAM check routines copied from gw8260 */ - -#if defined (CFG_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CFG_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CFG_DRAM_TEST_DATA */ - -#if defined (CFG_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CFG_DRAM_TEST_ADDRESS */ - -#if defined (CFG_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CFG_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - char *s; - int rundata, runaddress, runwalk; - - s = getenv ("testdramdata"); - rundata = (s && (*s == 'y')) ? 1 : 0; - s = getenv ("testdramaddress"); - runaddress = (s && (*s == 'y')) ? 1 : 0; - s = getenv ("testdramwalk"); - runwalk = (s && (*s == 'y')) ? 1 : 0; - -/* rundata = 1; */ -/* runaddress = 0; */ -/* runwalk = 0; */ - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); - } -#ifdef CFG_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CFG_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CFG_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed\n"); - } - return 0; - -} -#endif /* CFG_DRAM_TEST */ - -/* ronen - the below functions are used by the bootm function */ -/* - we map the base register to fbe00000 (same mapping as in the LSP) */ -/* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ -void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | - new_loc | - (INTERNAL_SPACE_DECODE))))) - != temp); - -} - -void board_prebootm_init () -{ - -/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ - GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); - -/* Stop GigE Rx DMA engines */ - GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); - GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); -/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */ - -/* Relocate MV64360 internal regs */ - my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM); - - icache_disable (); - invalidate_l1_instruction_cache (); - flush_data_cache (); - dcache_disable (); -} diff --git a/board/Marvell/db64360/eth.h b/board/Marvell/db64360/eth.h deleted file mode 100644 index aab32d2..0000000 --- a/board/Marvell/db64360/eth.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __EVB64360_ETH_H__ -#define __EVB64360_ETH_H__ - -#include -#include -#include -#include - - -int db64360_eth0_poll(void); -int db64360_eth0_transmit(unsigned int s, volatile char *p); -void db64360_eth0_disable(void); -bool network_start(bd_t *bis); - - -#endif /* __EVB64360_ETH_H__ */ diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c deleted file mode 100644 index ccb3adc..0000000 --- a/board/Marvell/db64360/mpsc.c +++ /dev/null @@ -1,1019 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - -/* - * mpsc.c - driver for console over the MPSC. - */ - - -#include -#include -#include - -#include -#include "mpsc.h" - -#include "mv_regs.h" - -#include "../include/memory.h" - -/* Define this if you wish to use the MPSC as a register based UART. - * This will force the serial port to not use the SDMA engine at all. - */ -#undef CONFIG_MPSC_DEBUG_PORT - - -int (*mpsc_putchar) (char ch) = mpsc_putchar_early; -char (*mpsc_getchar) (void) = mpsc_getchar_debug; -int (*mpsc_test_char) (void) = mpsc_test_char_debug; - - -static volatile unsigned int *rx_desc_base = NULL; -static unsigned int rx_desc_index = 0; -static volatile unsigned int *tx_desc_base = NULL; -static unsigned int tx_desc_index = 0; - -/* local function declarations */ -static int galmpsc_connect (int channel, int connect); -static int galmpsc_route_rx_clock (int channel, int brg); -static int galmpsc_route_tx_clock (int channel, int brg); -static int galmpsc_write_config_regs (int mpsc, int mode); -static int galmpsc_config_channel_regs (int mpsc); -static int galmpsc_set_char_length (int mpsc, int value); -static int galmpsc_set_stop_bit_length (int mpsc, int value); -static int galmpsc_set_parity (int mpsc, int value); -static int galmpsc_enter_hunt (int mpsc); -static int galmpsc_set_brkcnt (int mpsc, int value); -static int galmpsc_set_tcschar (int mpsc, int value); -static int galmpsc_set_snoop (int mpsc, int value); -static int galmpsc_shutdown (int mpsc); - -static int galsdma_set_RFT (int channel); -static int galsdma_set_SFM (int channel); -static int galsdma_set_rxle (int channel); -static int galsdma_set_txle (int channel); -static int galsdma_set_burstsize (int channel, unsigned int value); -static int galsdma_set_RC (int channel, unsigned int value); - -static int galbrg_set_CDV (int channel, int value); -static int galbrg_enable (int channel); -static int galbrg_disable (int channel); -static int galbrg_set_clksrc (int channel, int value); -static int galbrg_set_CUV (int channel, int value); - -static void galsdma_enable_rx (void); -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, - unsigned int size); - - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - -#ifdef CONFIG_MPSC_DEBUG_PORT -static void mpsc_debug_init (void) -{ - - volatile unsigned int temp; - - /* Clear the CFR (CHR4) */ - /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&". Assuming "= &" - -REG_GAP)); - temp &= 0xffffff00; - temp |= BIT29; - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); - temp |= (BIT12 | BIT15); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set int mask */ - temp = GTREGREAD (GALMPSC_0_INT_MASK); - temp |= BIT6; - GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); -} -#endif - -char mpsc_getchar_debug (void) -{ - volatile int temp; - volatile unsigned int cause; - - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - while ((cause & BIT6) == 0) { - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - } - - temp = GTREGREAD (GALMPSC_CHANNELREG_10 + - (CHANNEL * GALMPSC_REG_GAP)); - /* By writing 1's to the set bits, the register is cleared */ - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), - temp); - GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); - return (temp >> 16) & 0xff; -} - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int mpsc_putchar_early (char ch) -{ - DECLARE_GLOBAL_DATA_PTR; - int mpsc = CHANNEL; - int temp = - GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - galmpsc_set_tcschar (mpsc, ch); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), - temp | 0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay (MAGIC_FACTOR / gd->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int mpsc_putchar_sdma (char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset ((void *) p, 0, 8 * sizeof (unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int) ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int) &p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int) &p[0]; - p[11] = (unsigned int) &p[12]; -#endif - - FLUSH_DCACHE (&p[0], &p[8]); - - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE (&p[1], &p[2]); - - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[1], &p[2]); - } - return 0; -} - -char mpsc_getchar_sdma (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP)); - temp |= (1 << 23); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP), temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - - -int mpsc_test_char_debug (void) -{ - if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) - return 0; - else { - return 1; - } -} - - -int mpsc_test_char_sdma (void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[1], &p[2]); - - if (p[1] & DESC_OWNER_BIT) - return 0; - else - return 1; -} - -int mpsc_init (int baud) -{ - /* BRG CONFIG */ - galbrg_set_baudrate (CHANNEL, baud); - galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ - galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ - galbrg_enable (CHANNEL); /* Enable BRG */ - - /* Set up clock routing */ - galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ - - galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ - galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ - - /* reset MPSC state */ - galmpsc_shutdown (CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle (CHANNEL); - galsdma_set_rxle (CHANNEL); - galsdma_set_RC (CHANNEL, 0xf); - galsdma_set_SFM (CHANNEL); - galsdma_set_RFT (CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs (CHANNEL); - galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - -#ifdef CONFIG_MPSC_DEBUG_PORT - mpsc_debug_init (); -#endif - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - - -void mpsc_sdma_init (void) -{ -/* Setup SDMA channel0 SDMA_CONFIG_REG*/ - GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); - -/* Enable MPSC-Window0 for DRAM Bank0 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_0_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK0)) != true) - printf ("%s: SDMA_Window0 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window1 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_1_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window1 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window2 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_2_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window2 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window3 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_3_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window3 memory setup failed !!! \n", - __FUNCTION__); - -/* Setup MPSC0 access mode Window0 full access */ - GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC1 access mode Window1 full access */ - GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); - -/* no high address remap*/ - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); - -/* clear interrupt cause register for MPSC (fault register)*/ - GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); -} - - -void mpsc_init2 (void) -{ - int i; - -#ifndef CONFIG_MPSC_DEBUG_PORT - mpsc_putchar = mpsc_putchar_sdma; - mpsc_getchar = mpsc_getchar_sdma; - mpsc_test_char = mpsc_test_char_sdma; -#endif - /* RX descriptors */ - rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset ((void *) rx_desc_base, 0, - (RX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ - rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ - rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i * 8] = 0x00100000; - } - rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; - - FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset ((void *) tx_desc_base, 0, - (TX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 3] = - (unsigned int) &tx_desc_base[i * 8 + 4]; - tx_desc_base[i * 8 + 2] = - (unsigned int) &tx_desc_base[(i + 1) * 8]; - tx_desc_base[i * 8 + 1] = - DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i * 8] = 0x00010001; - } - tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; - - FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); - - udelay (100); - - galsdma_enable_rx (); - - return; -} - -int galbrg_set_baudrate (int channel, int rate) -{ - DECLARE_GLOBAL_DATA_PTR; - int clock; - - galbrg_disable (channel); /*ok */ - -#ifdef ZUMA_NTL - /* from tclk */ - clock = (CFG_TCLK / (16 * rate)) - 1; -#else - clock = (CFG_TCLK / (16 * rate)) - 1; -#endif - - galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ - - galbrg_enable (channel); - - gd->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int galbrg_set_CDV (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_enable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x00010000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_disable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFEFFFF; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_set_clksrc (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ - temp |= (value << 18); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - return 0; -} - -static int galbrg_set_CUV (int channel, int value) -{ - /* set CountUpValue */ - GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int galbrg_reset (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int galsdma_set_RFT (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_SFM (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_rxle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_txle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_RC (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_burstsize (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int galmpsc_connect (int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int galmpsc_route_rx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_RxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_route_tx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_TxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_write_config_regs (int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int galmpsc_config_channel_regs (int mpsc) -{ - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt (mpsc, 0x3); - galmpsc_set_tcschar (mpsc, 0xab); - - return 0; -} - -static int galmpsc_set_brkcnt (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_tcschar (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_char_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_stop_bit_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFBFFF; - temp |= (value << 14); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_parity (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_enter_hunt (int mpsc) -{ - int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= 0x80000000; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & - MPSC_ENTER_HUNT) { - udelay (1); - } - return 0; -} - - -static int galmpsc_shutdown (int mpsc) -{ - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - GT_REG_WRITE (GALSDMA_0_COM_REG, 0); - GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); - - udelay (100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); - - udelay (100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); - - udelay (100); - - return 0; -} - -static void galsdma_enable_rx (void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt (CHANNEL); -} - -static int galmpsc_set_snoop (int mpsc, int value) -{ - int reg = - mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : - MPSC_0_ADDRESS_CONTROL_LOW; - int temp = GTREGREAD (reg); - - if (value) - temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); - else - temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); - GT_REG_WRITE (reg, temp); - return 0; -} - -/******************************************************************************* -* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map. -* -* DESCRIPTION: -* the MV64360 SDMA has its own address decoding map that is de-coupled -* from the CPU interface address decoding windows. The SDMA channels -* share four address windows. Each region can be individually configured -* by this function by associating it to a target interface and setting -* base and size values. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* The size must be a series of 1s followed by a series of zeros -* -* OUTPUT: -* None. -* -* RETURN: -* True for success, false otherwise. -* -*******************************************************************************/ - -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, unsigned int size) -{ - unsigned int temp; - - if (size == 0) { - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - return true; - } - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size < 0x10000) { - return false; - } - - /* Align size and base to 64K */ - baseAddress &= 0xffff0000; - size &= 0xffff0000; - temp = size >> 16; - - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - while ((temp > 0) && (temp & 0x1)) { - temp = temp >> 1; - } - - if (temp != 0) { - GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8), - (size - 1) & 0xffff0000); - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - } else { - /* An invalid size was specified */ - return false; - } - return true; -} diff --git a/board/Marvell/db64360/mpsc.h b/board/Marvell/db64360/mpsc.h deleted file mode 100644 index f95f8c0..0000000 --- a/board/Marvell/db64360/mpsc.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include "../include/mv_gen_reg.h" - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_sdma_init(void); -void mpsc_init2(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -char mpsc_getchar_debug(void); -int mpsc_test_char_debug(void); - -int mpsc_test_char_sdma(void); - -extern int (*mpsc_putchar)(char ch); -extern char (*mpsc_getchar)(void); -extern int (*mpsc_test_char)(void); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER_BIT 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ -#define GALMPSC_0_INT_CAUSE 0xb804 -#define GALMPSC_0_INT_MASK 0xb884 - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c deleted file mode 100644 index 3c5dee7..0000000 --- a/board/Marvell/db64360/mv_eth.c +++ /dev/null @@ -1,3183 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mv_eth.c - header file for the polled mode GT ethernet driver - */ -#include -#include -#include - -#include "mv_eth.h" - -/* enable Debug outputs */ - -#undef DEBUG_MV_ETH - -#ifdef DEBUG_MV_ETH -#define DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#undef MV64360_CHECKSUM_OFFLOAD -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - -/* Definition for configuring driver */ -/* #define UPDATE_STATS_BY_SOFTWARE */ -#undef MV64360_RX_QUEUE_FILL_ON_TASK - - -/* Constants */ -#define MAGIC_ETH_RUNNING 8031971 -#define MV64360_INTERNAL_SRAM_SIZE _256K -#define EXTRA_BYTES 32 -#define WRAP ETH_HLEN + 2 + 4 + 16 -#define BUFFER_MTU dev->mtu + WRAP -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#ifdef MV64360_RX_FILL_ON_TASK -#define INT_CAUSE_MASK_ALL 0x00000000 -#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL -#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT -#endif - -/* Read/Write to/from MV64360 internal registers */ -#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) -#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) -#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) -#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) - -/* Static function declarations */ -static int mv64360_eth_real_open (struct eth_device *eth); -static int mv64360_eth_real_stop (struct eth_device *eth); -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device - *dev); -static void eth_port_init_mac_tables (ETH_PORT eth_port_num); -static void mv64360_eth_update_stat (struct eth_device *dev); -bool db64360_eth_start (struct eth_device *eth); -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset); -int mv64360_eth_receive (struct eth_device *dev); - -int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length); - -#ifndef UPDATE_STATS_BY_SOFTWARE -static void mv64360_eth_print_stat (struct eth_device *dev); -#endif -/* Processes a received packet */ -extern void NetReceive (volatile uchar *, int); - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/************************************************* - *Helper functions - used inside the driver only * - *************************************************/ -#ifdef DEBUG_MV_ETH -void print_globals (struct eth_device *dev) -{ - printf ("Ethernet PRINT_Globals-Debug function\n"); - printf ("Base Address for ETH_PORT_INFO: %08x\n", - (unsigned int) dev->priv); - printf ("Base Address for mv64360_eth_priv: %08x\n", - (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> - port_private)); - - printf ("GT Internal Base Address: %08x\n", - INTERNAL_REG_BASE_ADDR); - printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE); - printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE); - printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_rx_buffer_base[0], - (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32); - printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_tx_buffer_base[0], - (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32); -} -#endif - -#define my_cpu_to_le32(x) my_le32_to_cpu((x)) - -unsigned long my_le32_to_cpu (unsigned long x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); -} - - -/********************************************************************** - * mv64360_eth_print_phy_status - * - * Prints gigabit ethenret phy status - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_phy_status (struct eth_device *dev) -{ - struct mv64360_eth_priv *port_private; - unsigned int port_num; - ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; - unsigned int port_status, phy_reg_data; - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("Ethernet port changed link status to DOWN\n"); - } else { - port_status = - MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - printf ("Ethernet status port %d: Link up", port_num); - printf (", %s", - (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); - if (port_status & BIT4) - printf (", Speed 1 Gbps"); - else - printf (", %s", - (port_status & BIT5) ? "Speed 100 Mbps" : - "Speed 10 Mbps"); - printf ("\n"); - } -} - -/********************************************************************** - * u-boot entry functions for mv64360_eth - * - **********************************************************************/ -int db64360_eth_probe (struct eth_device *dev) -{ - return ((int) db64360_eth_start (dev)); -} - -int db64360_eth_poll (struct eth_device *dev) -{ - return mv64360_eth_receive (dev); -} - -int db64360_eth_transmit (struct eth_device *dev, volatile void *packet, - int length) -{ - mv64360_eth_xmit (dev, packet, length); - return 0; -} - -void db64360_eth_disable (struct eth_device *dev) -{ - mv64360_eth_stop (dev); -} - - -void mv6436x_eth_initialize (bd_t * bis) -{ - struct eth_device *dev; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - int devnum, x, temp; - char *s, *e, buf[64]; - - for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { - dev = calloc (sizeof (*dev), 1); - if (!dev) { - printf ("%s: mv_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than NAMESIZE (16) */ - sprintf (dev->name, "mv_enet%d", devnum); - -#ifdef DEBUG - printf ("Initializing %s\n", dev->name); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_r (s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - /* ronen - set the MAC addr in the HW */ - eth_port_uc_addr_set (devnum, dev->enetaddr, 0); - - dev->init = (void *) db64360_eth_probe; - dev->halt = (void *) ethernet_phy_reset; - dev->send = (void *) db64360_eth_transmit; - dev->recv = (void *) db64360_eth_poll; - - ethernet_private = calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *) ethernet_private; - - if (!ethernet_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Private Device Structure"); - free (dev); - return; - } - /* start with an zeroed ETH_PORT_INFO */ - memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - /* set pointer to memory for stats data structure etc... */ - port_private = calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; - if (!port_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Port Private Device Structure"); - - free (ethernet_private); - free (dev); - return; - } - - port_private->stats = - calloc (sizeof (struct net_device_stats), 1); - if (!port_private->stats) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Net stat Structure"); - - free (port_private); - free (ethernet_private); - free (dev); - return; - } - memset (ethernet_private->port_private, 0, - sizeof (struct mv64360_eth_priv)); - switch (devnum) { - case 0: - ethernet_private->port_num = ETH_0; - break; - case 1: - ethernet_private->port_num = ETH_1; - break; - case 2: - ethernet_private->port_num = ETH_2; - break; - default: - printf ("Invalid device number %d\n", devnum); - break; - }; - - port_private->port_num = devnum; - /* - * Read MIB counter on the GT in order to reset them, - * then zero all the stats fields in memory - */ - mv64360_eth_update_stat (dev); - memset (port_private->stats, 0, - sizeof (struct net_device_stats)); - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_r (s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - DP (printf ("Allocating descriptor and buffer rings\n")); - - ethernet_private->p_rx_desc_area_base[0] = - (ETH_RX_DESC *) memalign (16, - RX_DESC_ALIGNED_SIZE * - MV64360_RX_QUEUE_SIZE + 1); - ethernet_private->p_tx_desc_area_base[0] = - (ETH_TX_DESC *) memalign (16, - TX_DESC_ALIGNED_SIZE * - MV64360_TX_QUEUE_SIZE + 1); - - ethernet_private->p_rx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - ethernet_private->p_tx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - -#ifdef DEBUG_MV_ETH - /* DEBUG OUTPUT prints adresses of globals */ - print_globals (dev); -#endif - eth_register (dev); - - } - DP (printf ("%s: exit\n", __FUNCTION__)); - -} - -/********************************************************************** - * mv64360_eth_open - * - * This function is called when openning the network device. The function - * should initialize all the hardware, initialize cyclic Rx/Tx - * descriptors chain and buffers and allocate an IRQ to the network - * device. - * - * Input : a pointer to the network device structure - * / / ronen - changed the output to match net/eth.c needs - * Output : nonzero of success , zero if fails. - * under construction - **********************************************************************/ - -int mv64360_eth_open (struct eth_device *dev) -{ - return (mv64360_eth_real_open (dev)); -} - -/* Helper function for mv64360_eth_open */ -static int mv64360_eth_real_open (struct eth_device *dev) -{ - - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - u32 port_status, phy_reg_data; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - /* ronen - when we update the MAC env params we only update dev->enetaddr - see ./net/eth.c eth_set_enetaddr() */ - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Clear the ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - - /* Unmask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL); - - /* Unmask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL_EXT); - - /* Set phy address of the port */ - ethernet_private->port_phy_addr = 0x8 + port_num; - - /* Activate the DMA channels etc */ - eth_port_init (ethernet_private); - - - /* "Allocate" setup TX rings */ - - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - unsigned int size; - - port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE; - size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ - ethernet_private->tx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_tx_desc_area_base[queue], - 0, ethernet_private->tx_desc_area_size[queue]); - - /* initialize tx desc ring with low level driver */ - if (ether_init_tx_desc_ring - (ethernet_private, ETH_Q0, - port_private->tx_ring_size[queue], - MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_tx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_tx_buffer_base[queue]) == false) - printf ("### Error initializing TX Ring\n"); - } - - /* "Allocate" setup RX rings */ - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - unsigned int size; - - /* Meantime RX Ring are fixed - but must be configurable by user */ - port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE; - size = (port_private->rx_ring_size[queue] * - RX_DESC_ALIGNED_SIZE); - ethernet_private->rx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_rx_desc_area_base[queue], - 0, ethernet_private->rx_desc_area_size[queue]); - if ((ether_init_rx_desc_ring - (ethernet_private, ETH_Q0, - port_private->rx_ring_size[queue], - MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_rx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_rx_buffer_base[queue])) == false) - printf ("### Error initializing RX Ring\n"); - } - - eth_port_start (ethernet_private); - - /* Set maximum receive buffer to 9700 bytes */ - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num), - (0x5 << 17) | - (MV_REG_READ - (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num)) - & 0xfff1ffff)); - - /* - * Set ethernet MTU for leaky bucket mechanism to 0 - this will - * disable the leaky bucket mechanism . - */ - - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - /* Reset PHY */ - if ((ethernet_phy_reset (port_num)) != true) { - printf ("$$ Warnning: No link on port %d \n", - port_num); - return 0; - } else { - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("### Error: Phy is not active\n"); - return 0; - } - } - } else { - mv64360_eth_print_phy_status (dev); - } - port_private->eth_running = MAGIC_ETH_RUNNING; - return 1; -} - - -static int mv64360_eth_free_tx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_TX_DESC *p_tx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop Tx Queues */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free TX rings */ - DP (printf ("Clearing previously allocated TX queues... ")); - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - /* Free on TX rings */ - for (p_tx_curr_desc = - ethernet_private->p_tx_desc_area_base[queue]; - ((unsigned int) p_tx_curr_desc <= (unsigned int) - ethernet_private->p_tx_desc_area_base[queue] + - ethernet_private->tx_desc_area_size[queue]); - p_tx_curr_desc = - (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + - TX_DESC_ALIGNED_SIZE)) { - /* this is inside for loop */ - if (p_tx_curr_desc->return_info != 0) { - p_tx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -static int mv64360_eth_free_rx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_RX_DESC *p_rx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free RX rings */ - DP (printf ("Clearing previously allocated RX queues... ")); - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - /* Free preallocated skb's on RX rings */ - for (p_rx_curr_desc = - ethernet_private->p_rx_desc_area_base[queue]; - (((unsigned int) p_rx_curr_desc < - ((unsigned int) ethernet_private-> - p_rx_desc_area_base[queue] + - ethernet_private->rx_desc_area_size[queue]))); - p_rx_curr_desc = - (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + - RX_DESC_ALIGNED_SIZE)) { - if (p_rx_curr_desc->return_info != 0) { - p_rx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -/********************************************************************** - * mv64360_eth_stop - * - * This function is used when closing the network device. - * It updates the hardware, - * release all memory that holds buffers and descriptors and release the IRQ. - * Input : a pointer to the device structure - * Output : zero if success , nonzero if fails - *********************************************************************/ - -int mv64360_eth_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Disable all gigE address decoder */ - MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); - DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); - mv64360_eth_real_stop (dev); - - return 0; -}; - -/* Helper function for mv64360_eth_stop */ - -static int mv64360_eth_real_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - mv64360_eth_free_tx_rings (dev); - mv64360_eth_free_rx_rings (dev); - - eth_port_reset (ethernet_private->port_num); - /* Disable ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - /* Mask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0); - /* Mask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); - MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH, - BIT0 << port_num); - /* Print Network statistics */ -#ifndef UPDATE_STATS_BY_SOFTWARE - /* - * Print statistics (only if ethernet is running), - * then zero all the stats fields in memory - */ - if (port_private->eth_running == MAGIC_ETH_RUNNING) { - port_private->eth_running = 0; - mv64360_eth_print_stat (dev); - } - memset (port_private->stats, 0, sizeof (struct net_device_stats)); -#endif - DP (printf ("\nEthernet stopped ... \n")); - return 0; -} - - -/********************************************************************** - * mv64360_eth_start_xmit - * - * This function is queues a packet in the Tx descriptor for - * required port. - * - * Input : skb - a pointer to socket buffer - * dev - a pointer to the required port - * - * Output : zero upon success - **********************************************************************/ - -int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, - int dataSize) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - PKT_INFO pkt_info; - ETH_FUNC_RET_STATUS status; - struct net_device_stats *stats; - ETH_FUNC_RET_STATUS release_result; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - stats = port_private->stats; - - /* Update packet info data structure */ - pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ - pkt_info.byte_cnt = dataSize; - pkt_info.buf_ptr = (unsigned int) dataPtr; - - status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); - if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { - printf ("Error on transmitting packet .."); - if (status == ETH_QUEUE_FULL) - printf ("ETH Queue is full. \n"); - if (status == ETH_QUEUE_LAST_RESOURCE) - printf ("ETH Queue: using last available resource. \n"); - goto error; - } - - /* Update statistics and start of transmittion time */ - stats->tx_bytes += dataSize; - stats->tx_packets++; - - /* Check if packet(s) is(are) transmitted correctly (release everything) */ - do { - release_result = - eth_tx_return_desc (ethernet_private, ETH_Q0, - &pkt_info); - switch (release_result) { - case ETH_OK: - DP (printf ("descriptor released\n")); - if (pkt_info.cmd_sts & BIT0) { - printf ("Error in TX\n"); - stats->tx_errors++; - - } - break; - case ETH_RETRY: - DP (printf ("transmission still in process\n")); - break; - - case ETH_ERROR: - printf ("routine can not access Tx desc ring\n"); - break; - - case ETH_END_OF_JOB: - DP (printf ("the routine has nothing to release\n")); - break; - default: /* should not happen */ - break; - } - } while (release_result == ETH_OK); - - - return 0; /* success */ - error: - return 1; /* Failed - higher layers will free the skb */ -} - -/********************************************************************** - * mv64360_eth_receive - * - * This function is forward packets that are received from the port's - * queues toward kernel core or FastRoute them to another interface. - * - * Input : dev - a pointer to the required interface - * max - maximum number to receive (0 means unlimted) - * - * Output : number of served packets - **********************************************************************/ - -int mv64360_eth_receive (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - PKT_INFO pkt_info; - struct net_device_stats *stats; - - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - stats = port_private->stats; - - while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == - ETH_OK)) { - -#ifdef DEBUG_MV_ETH - if (pkt_info.byte_cnt != 0) { - printf ("%s: Received %d byte Packet @ 0x%x\n", - __FUNCTION__, pkt_info.byte_cnt, - pkt_info.buf_ptr); - } -#endif - /* Update statistics. Note byte count includes 4 byte CRC count */ - stats->rx_packets++; - stats->rx_bytes += pkt_info.byte_cnt; - - /* - * In case received a packet without first / last bits on OR the error - * summary bit is on, the packets needs to be dropeed. - */ - if (((pkt_info. - cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != - (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) - || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { - stats->rx_dropped++; - - printf ("Received packet spread on multiple descriptors\n"); - - /* Is this caused by an error ? */ - if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { - stats->rx_errors++; - } - - /* free these descriptors again without forwarding them to the higher layers */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - /* /free these descriptors again */ - } else { - -/* !!! call higher layer processing */ -#ifdef DEBUG_MV_ETH - printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); -#endif - /* let the upper layer handle the packet */ - NetReceive ((uchar *) pkt_info.buf_ptr, - (int) pkt_info.byte_cnt); - -/* **************************************************************** */ -/* free descriptor */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - DP (printf - ("RX: pkt_info.buf_ptr = %x\n", - pkt_info.buf_ptr)); - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - -/* **************************************************************** */ - - } - } - mv64360_eth_get_stats (dev); /* update statistics */ - return 1; -} - -/********************************************************************** - * mv64360_eth_get_stats - * - * Returns a pointer to the interface statistics. - * - * Input : dev - a pointer to the required interface - * - * Output : a pointer to the interface's statistics - **********************************************************************/ - -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - mv64360_eth_update_stat (dev); - - return port_private->stats; -} - - -/********************************************************************** - * mv64360_eth_update_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_update_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - unsigned int port_num; - volatile unsigned int dummy; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - stats = port_private->stats; - - /* These are false updates */ - stats->rx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_RECEIVED); - stats->tx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_SENT); - stats->rx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); - /* - * Ideally this should be as follows - - * - * stats->rx_bytes += stats->rx_bytes + - * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , - * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); - * - * But the unsigned long in PowerPC and MIPS are 32bit. So the next read - * is just a dummy read for proper work of the GigE port - */ - dummy = eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); - stats->tx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_LOW); - dummy = eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_HIGH); - stats->rx_errors += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MAC_RECEIVE_ERROR); - - /* Rx dropped is for received packet with CRC error */ - stats->rx_dropped += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_BAD_CRC_EVENT); - stats->multicast += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MULTICAST_FRAMES_RECEIVED); - stats->collisions += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_COLLISION) + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_LATE_COLLISION); - /* detailed rx errors */ - stats->rx_length_errors += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_UNDERSIZE_RECEIVED) - + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_OVERSIZE_RECEIVED); - /* detailed tx errors */ -} - -#ifndef UPDATE_STATS_BY_SOFTWARE -/********************************************************************** - * mv64360_eth_print_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - stats = port_private->stats; - - /* These are false updates */ - printf ("\n### Network statistics: ###\n"); - printf ("--------------------------\n"); - printf (" Packets received: %ld\n", stats->rx_packets); - printf (" Packets send: %ld\n", stats->tx_packets); - printf (" Received bytes: %ld\n", stats->rx_bytes); - printf (" Send bytes: %ld\n", stats->tx_bytes); - if (stats->rx_errors != 0) - printf (" Rx Errors: %ld\n", - stats->rx_errors); - if (stats->rx_dropped != 0) - printf (" Rx dropped (CRC Errors): %ld\n", - stats->rx_dropped); - if (stats->multicast != 0) - printf (" Rx mulicast frames: %ld\n", - stats->multicast); - if (stats->collisions != 0) - printf (" No. of collisions: %ld\n", - stats->collisions); - if (stats->rx_length_errors != 0) - printf (" Rx length errors: %ld\n", - stats->rx_length_errors); -} -#endif - -/************************************************************************** - *network_start - Network Kick Off Routine UBoot - *Inputs : - *Outputs : - **************************************************************************/ - -bool db64360_eth_start (struct eth_device *dev) -{ - return (mv64360_eth_open (dev)); /* calls real open */ -} - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* - * based on Linux code - * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -/******************************************************************************** - * Marvell's Gigabit Ethernet controller low level driver - * - * DESCRIPTION: - * This file introduce low level API to Marvell's Gigabit Ethernet - * controller. This Gigabit Ethernet Controller driver API controls - * 1) Operations (i.e. port init, start, reset etc'). - * 2) Data flow (i.e. port send, receive etc'). - * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO - * struct. - * This struct includes user configuration information as well as - * driver internal data needed for its operations. - * - * Supported Features: - * - This low level driver is OS independent. Allocating memory for - * the descriptor rings and buffers are not within the scope of - * this driver. - * - The user is free from Rx/Tx queue managing. - * - This low level driver introduce functionality API that enable - * the to operate Marvell's Gigabit Ethernet Controller in a - * convenient way. - * - Simple Gigabit Ethernet port operation API. - * - Simple Gigabit Ethernet port data flow API. - * - Data flow and operation API support per queue functionality. - * - Support cached descriptors for better performance. - * - Enable access to all four DRAM banks and internal SRAM memory - * spaces. - * - PHY access and control API. - * - Port control register configuration API. - * - Full control over Unicast and Multicast MAC configurations. - * - * Operation flow: - * - * Initialization phase - * This phase complete the initialization of the ETH_PORT_INFO - * struct. - * User information regarding port configuration has to be set - * prior to calling the port initialization routine. For example, - * the user has to assign the port_phy_addr field which is board - * depended parameter. - * In this phase any port Tx/Rx activity is halted, MIB counters - * are cleared, PHY address is set according to user parameter and - * access to DRAM and internal SRAM memory spaces. - * - * Driver ring initialization - * Allocating memory for the descriptor rings and buffers is not - * within the scope of this driver. Thus, the user is required to - * allocate memory for the descriptors ring and buffers. Those - * memory parameters are used by the Rx and Tx ring initialization - * routines in order to curve the descriptor linked list in a form - * of a ring. - * Note: Pay special attention to alignment issues when using - * cached descriptors/buffers. In this phase the driver store - * information in the ETH_PORT_INFO struct regarding each queue - * ring. - * - * Driver start - * This phase prepares the Ethernet port for Rx and Tx activity. - * It uses the information stored in the ETH_PORT_INFO struct to - * initialize the various port registers. - * - * Data flow: - * All packet references to/from the driver are done using PKT_INFO - * struct. - * This struct is a unified struct used with Rx and Tx operations. - * This way the user is not required to be familiar with neither - * Tx nor Rx descriptors structures. - * The driver's descriptors rings are management by indexes. - * Those indexes controls the ring resources and used to indicate - * a SW resource error: - * 'current' - * This index points to the current available resource for use. For - * example in Rx process this index will point to the descriptor - * that will be passed to the user upon calling the receive routine. - * In Tx process, this index will point to the descriptor - * that will be assigned with the user packet info and transmitted. - * 'used' - * This index points to the descriptor that need to restore its - * resources. For example in Rx process, using the Rx buffer return - * API will attach the buffer returned in packet info to the - * descriptor pointed by 'used'. In Tx process, using the Tx - * descriptor return will merely return the user packet info with - * the command status of the transmitted buffer pointed by the - * 'used' index. Nevertheless, it is essential to use this routine - * to update the 'used' index. - * 'first' - * This index supports Tx Scatter-Gather. It points to the first - * descriptor of a packet assembled of multiple buffers. For example - * when in middle of Such packet we have a Tx resource error the - * 'curr' index get the value of 'first' to indicate that the ring - * returned to its state before trying to transmit this packet. - * - * Receive operation: - * The eth_port_receive API set the packet information struct, - * passed by the caller, with received information from the - * 'current' SDMA descriptor. - * It is the user responsibility to return this resource back - * to the Rx descriptor ring to enable the reuse of this source. - * Return Rx resource is done using the eth_rx_return_buff API. - * - * Transmit operation: - * The eth_port_send API supports Scatter-Gather which enables to - * send a packet spanned over multiple buffers. This means that - * for each packet info structure given by the user and put into - * the Tx descriptors ring, will be transmitted only if the 'LAST' - * bit will be set in the packet info command status field. This - * API also consider restriction regarding buffer alignments and - * sizes. - * The user must return a Tx resource after ensuring the buffer - * has been transmitted to enable the Tx ring indexes to update. - * - * BOARD LAYOUT - * This device is on-board. No jumper diagram is necessary. - * - * EXTERNAL INTERFACE - * - * Prior to calling the initialization routine eth_port_init() the user - * must set the following fields under ETH_PORT_INFO struct: - * port_num User Ethernet port number. - * port_phy_addr User PHY address of Ethernet port. - * port_mac_addr[6] User defined port MAC address. - * port_config User port configuration value. - * port_config_extend User port config extend value. - * port_sdma_config User port SDMA config value. - * port_serial_control User port serial control value. - * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. - * *port_private User scratch pad for user specific data structures. - * - * This driver introduce a set of default values: - * PORT_CONFIG_VALUE Default port configuration value - * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value - * PORT_SDMA_CONFIG_VALUE Default sdma control value - * PORT_SERIAL_CONTROL_VALUE Default port serial control value - * - * This driver data flow is done using the PKT_INFO struct which is - * a unified struct for Rx and Tx operations: - * byte_cnt Tx/Rx descriptor buffer byte count. - * l4i_chk CPU provided TCP Checksum. For Tx operation only. - * cmd_sts Tx/Rx descriptor command status. - * buf_ptr Tx/Rx descriptor buffer pointer. - * return_info Tx/Rx user resource return information. - * - * - * EXTERNAL SUPPORT REQUIREMENTS - * - * This driver requires the following external support: - * - * D_CACHE_FLUSH_LINE (address, address offset) - * - * This macro applies assembly code to flush and invalidate cache - * line. - * address - address base. - * address offset - address offset - * - * - * CPU_PIPE_FLUSH - * - * This macro applies assembly code to flush the CPU pipeline. - * - *******************************************************************************/ -/* includes */ - -/* defines */ -/* SDMA command macros */ -#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) - -#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ - (1 << (8 + tx_queue))) - -#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) - -#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) - -#define CURR_RFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) - -#define CURR_RFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_RFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) - -#define USED_RFD_SET(p_used_desc, queue)\ -(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) - - -#define CURR_TFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) - -#define CURR_TFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_TFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) - -#define USED_TFD_SET(p_used_desc, queue) \ - (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) - -#define FIRST_TFD_GET(p_first_desc, queue) \ - ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) - -#define FIRST_TFD_SET(p_first_desc, queue) \ - (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) - - -/* Macros that save access to desc in order to find next desc pointer */ -#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) - -#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) - -#define LINK_UP_TIMEOUT 100000 -#define PHY_BUSY_TIMEOUT 10000000 - -/* locals */ - -/* PHY routines */ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); -static int ethernet_phy_get (ETH_PORT eth_port_num); - -/* Ethernet Port routines */ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param); -static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, - ETH_QUEUE queue, int option); -#if 0 /* FIXME */ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option); -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option); -#endif - -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count); - -void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); - - -typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; -u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_BASE_ADDR); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_BASE_ADDR); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_BASE_ADDR); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_dram_bank_size (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_SIZE); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_SIZE); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_SIZE); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_SIZE); - result += 1; - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_internal_sram_base (void) -{ - u32 result; - - result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -/******************************************************************************* -* eth_port_init - Initialize the Ethernet port driver -* -* DESCRIPTION: -* This function prepares the ethernet port to start its activity: -* 1) Completes the ethernet port driver struct initialization toward port -* start routine. -* 2) Resets the device to a quiescent state in case of warm reboot. -* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -* 4) Clean MAC tables. The reset status of those tables is unknown. -* 5) Set PHY address. -* Note: Call this routine prior to eth_port_start routine and after setting -* user values in the user fields of Ethernet port control struct (i.e. -* port_phy_addr). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* See description. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - ETH_WIN_PARAM win_param; - - p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; - p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; - p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; - p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; - - p_eth_port_ctrl->port_rx_queue_command = 0; - p_eth_port_ctrl->port_tx_queue_command = 0; - - /* Zero out SW structs */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->rx_resource_err[queue] = false; - } - - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->tx_resource_err[queue] = false; - } - - eth_port_reset (p_eth_port_ctrl->port_num); - - /* Set access parameters for DRAM bank 0 */ - win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); - win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 1 */ - win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); - win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 2 */ - win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); - win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 3 */ - win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); - win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for Internal SRAM */ - win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ - win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ - win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; - win_param.high_addr = 0; - win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ - win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */ - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - eth_port_init_mac_tables (p_eth_port_ctrl->port_num); - - ethernet_phy_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_phy_addr); - - return; - -} - -/******************************************************************************* -* eth_port_start - Start the Ethernet port activity. -* -* DESCRIPTION: -* This routine prepares the Ethernet port for Rx and Tx activity: -* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -* has been initialized a descriptor's ring (using ether_init_tx_desc_ring -* for Tx and ether_init_rx_desc_ring for Rx) -* 2. Initialize and enable the Ethernet configuration port by writing to -* the port's configuration and command registers. -* 3. Initialize and enable the SDMA by writing to the SDMA's -* configuration and command registers. -* After completing these steps, the ethernet port SDMA can starts to -* perform Rx and Tx activities. -* -* Note: Each Rx and Tx queue descriptor's list must be initialized prior -* to calling this function (use ether_init_tx_desc_ring for Tx queues and -* ether_init_rx_desc_ring for Rx queues). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* Ethernet port is ready to receive and transmit. -* -* RETURN: -* false if the port PHY is not up. -* true otherwise. -* -*******************************************************************************/ -static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - volatile ETH_TX_DESC *p_tx_curr_desc; - volatile ETH_RX_DESC *p_rx_curr_desc; - unsigned int phy_reg_data; - ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; - - - /* Assignment of Tx CTRP of given queue */ - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_GET (p_tx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_tx_curr_desc)); - - } - - /* Assignment of Rx CRDP of given queue */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_GET (p_rx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_rx_curr_desc)); - - if (p_rx_curr_desc != NULL) - /* Add the assigned Ethernet address to the port's address table */ - eth_port_uc_addr_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_mac_addr, - queue); - } - - /* Assign port configuration and command. */ - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_config); - - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - p_eth_port_ctrl->port_config_extend); - - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - p_eth_port_ctrl->port_serial_control); - - MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - ETH_SERIAL_PORT_ENABLE); - - /* Assign port SDMA configuration */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_sdma_config); - - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT - (eth_port_num), 0x3fffffff); - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG - (eth_port_num), 0x03fffcff); - /* Turn off the port/queue bandwidth limitation */ - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); - - /* Enable port Rx. */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), - p_eth_port_ctrl->port_rx_queue_command); - - /* Check if link is up */ - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (!(phy_reg_data & 0x20)) - return false; - - return true; -} - -/******************************************************************************* -* eth_port_uc_addr_set - This function Set the port Unicast address. -* -* DESCRIPTION: -* This function Set the port Ethernet MAC address. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. -* -* OUTPUT: -* Set MAC address low and high registers. also calls eth_port_uc_addr() -* To set the unicast table with the proper information. -* -* RETURN: -* N/A. -* -*******************************************************************************/ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, ETH_QUEUE queue) -{ - unsigned int mac_h; - unsigned int mac_l; - - mac_l = (p_addr[4] << 8) | (p_addr[5]); - mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | - (p_addr[2] << 8) | (p_addr[3] << 0); - - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); - - /* Accept frames of this address */ - eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); - - return; -} - -/******************************************************************************* -* eth_port_uc_addr - This function Set the port unicast address table -* -* DESCRIPTION: -* This function locates the proper entry in the Unicast table for the -* specified MAC nibble and sets its properties according to function -* parameters. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* This function add/removes MAC addresses from the port unicast address -* table. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_uc_addr (ETH_PORT eth_port_num, - unsigned char uc_nibble, - ETH_QUEUE queue, int option) -{ - unsigned int unicast_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the Unicast table entry */ - uc_nibble = (0xf & uc_nibble); - tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ - reg_offset = uc_nibble % 4; /* Entry offset within the above register */ - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified unicast DA table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - - break; - - default: - return false; - } - return true; -} - -#if 0 /* FIXME */ -/******************************************************************************* -* eth_port_mc_addr - Multicast address settings. -* -* DESCRIPTION: -* This API controls the MV device MAC multicast support. -* The MV device supports multicast using two tables: -* 1) Special Multicast Table for MAC addresses of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* In this case, the function calls eth_port_smc_addr() routine to set the -* Special Multicast Table. -* 2) Other Multicast Table for multicast of another type. A CRC-8bit -* is used as an index to the Other Multicast Table entries in the -* DA-Filter table. -* In this case, the function calculates the CRC-8bit value and calls -* eth_port_omc_addr() routine to set the Other Multicast Table. -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if add_address_table_entry( ) failed. -* -*******************************************************************************/ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, int option) -{ - unsigned int mac_h; - unsigned int mac_l; - unsigned char crc_result = 0; - int mac_array[48]; - int crc[8]; - int i; - - - if ((p_addr[0] == 0x01) && - (p_addr[1] == 0x00) && - (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) - - eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); - else { - /* Calculate CRC-8 out of the given address */ - mac_h = (p_addr[0] << 8) | (p_addr[1]); - mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | - (p_addr[4] << 8) | (p_addr[5] << 0); - - for (i = 0; i < 32; i++) - mac_array[i] = (mac_l >> i) & 0x1; - for (i = 32; i < 48; i++) - mac_array[i] = (mac_h >> (i - 32)) & 0x1; - - - crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ - mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ - mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ - mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ - mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ - mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[0]; - - crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ - mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ - mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ - mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ - mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ - mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ - mac_array[0]; - - crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ - mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ - mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ - mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ - mac_array[2] ^ mac_array[1] ^ mac_array[0]; - - crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ - mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ - mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ - mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ - mac_array[2] ^ mac_array[1]; - - crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ - mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ - mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ - mac_array[2]; - - crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ - mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ - mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ - mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ - mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ - mac_array[3]; - - crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ - mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ - mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ - mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[6] ^ mac_array[5] ^ mac_array[4]; - - crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ - mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ - mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ - mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ - mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[5]; - - for (i = 0; i < 8; i++) - crc_result = crc_result | (crc[i] << i); - - eth_port_omc_addr (eth_port_num, crc_result, queue, option); - } - return; -} - -/******************************************************************************* -* eth_port_smc_addr - Special Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device special MAC multicast support. -* The Special Multicast Table for MAC addresses supports MAC of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* This function set the Special Multicast Table appropriate entry -* according to the argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option) -{ - unsigned int smc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the SMC table entry */ - tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ - reg_offset = mc_byte % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - default: - return false; - } - return true; -} - -/******************************************************************************* -* eth_port_omc_addr - Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device Other MAC multicast support. -* The Other Multicast Table is used for multicast of another type. -* A CRC-8bit is used as an index to the Other Multicast Table entries -* in the DA-Filter table. -* The function gets the CRC-8bit value from the calling routine and -* set the Other Multicast Table appropriate entry according to the -* CRC-8 argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option) -{ - unsigned int omc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the OMC table entry */ - tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ - reg_offset = crc8 % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - default: - return false; - } - return true; -} -#endif - -/******************************************************************************* -* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -* -* DESCRIPTION: -* Go through all the DA filter tables (Unicast, Special Multicast & Other -* Multicast) and set each entry to 0. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Multicast and Unicast packets are rejected. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init_mac_tables (ETH_PORT eth_port_num) -{ - int table_index; - - /* Clear DA filter unicast table (Ex_dFUT) */ - for (table_index = 0; table_index <= 0xC; table_index += 4) - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) + table_index), 0); - - for (table_index = 0; table_index <= 0xFC; table_index += 4) { - /* Clear DA filter special multicast table (Ex_dFSMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - /* Clear DA filter other multicast table (Ex_dFOMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - } -} - -/******************************************************************************* -* eth_clear_mib_counters - Clear all MIB counters -* -* DESCRIPTION: -* This function clears all MIB counters of a specific ethernet port. -* A read from the MIB counter will reset the counter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* After reading all MIB counters, the counters resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -static void eth_clear_mib_counters (ETH_PORT eth_port_num) -{ - int i; - unsigned int dummy; - - /* Perform dummy reads from MIB counters */ - for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) - dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); - - return; -} - -/******************************************************************************* -* eth_read_mib_counter - Read a MIB counter -* -* DESCRIPTION: -* This function reads a MIB counter of a specific ethernet port. -* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the -* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH -* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and -* ETH_MIB_GOOD_OCTETS_SENT_HIGH -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). -* -* OUTPUT: -* After reading the MIB counter, the counter resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset) -{ - return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num) - + mib_offset)); -} - -/******************************************************************************* -* ethernet_phy_set - Set the ethernet port PHY address. -* -* DESCRIPTION: -* This routine set the ethernet port PHY address according to given -* parameter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Set PHY Address Register with given PHY address parameter. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - reg_data &= ~(0x1F << (5 * eth_port_num)); - reg_data |= (phy_addr << (5 * eth_port_num)); - - MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data); - - return; -} - -/******************************************************************************* - * ethernet_phy_get - Get the ethernet port PHY address. - * - * DESCRIPTION: - * This routine returns the given ethernet port PHY address. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * PHY address. - * - *******************************************************************************/ -static int ethernet_phy_get (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - return ((reg_data >> (5 * eth_port_num)) & 0x1f); -} - -/******************************************************************************* - * ethernet_phy_reset - Reset Ethernet port PHY. - * - * DESCRIPTION: - * This routine utilize the SMI interface to reset the ethernet port PHY. - * The routine waits until the link is up again or link up is timeout. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * The ethernet port PHY renew its link. - * - * RETURN: - * None. - * -*******************************************************************************/ -static bool ethernet_phy_reset (ETH_PORT eth_port_num) -{ - unsigned int time_out = 50; - unsigned int phy_reg_data; - - /* Reset the PHY */ - eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); - phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ - eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); - - /* Poll on the PHY LINK */ - do { - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (time_out-- == 0) - return false; - } - while (!(phy_reg_data & 0x20)); - - return true; -} - -/******************************************************************************* - * eth_port_reset - Reset Ethernet port - * - * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and - * clearing the MIB counters. The Receiver and the Transmit unit are in - * idle state after this command is performed and the port is disabled. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * Channel activity is halted. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_port_reset (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - /* Stop Tx port activity. Check port Tx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Tx activity to terminate. */ - do { - /* Check port cause register that all Tx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Stop Rx port activity. Check port Rx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Rx activity to terminate. */ - do { - /* Check port cause register that all Rx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - - /* Clear all MIB counters */ - eth_clear_mib_counters (eth_port_num); - - /* Reset the Enable bit in the Configuration Register */ - reg_data = - MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG - (eth_port_num)); - reg_data &= ~ETH_SERIAL_PORT_ENABLE; - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - reg_data); - - return; -} - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_set_config_reg - Set specified bits in configuration register. - * - * DESCRIPTION: - * This function sets specified bits in the given ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are set in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_set_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = - MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num)); - eth_config_reg |= value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* FIXME */ -/******************************************************************************* - * ethernet_reset_config_reg - Reset specified bits in configuration register. - * - * DESCRIPTION: - * This function resets specified bits in the given Ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are reset in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_reset_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - eth_config_reg &= ~value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_get_config_reg - Get the port configuration register - * - * DESCRIPTION: - * This function returns the configuration register value of the given - * ethernet port. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * Port configuration register value. - * - *******************************************************************************/ -static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - return eth_config_reg; -} - -#endif - -/******************************************************************************* - * eth_port_read_smi_reg - Read PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform PHY register read. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int *value Register value buffer. - * - * OUTPUT: - * Write the value of a specified PHY register into given buffer. - * - * RETURN: - * false if the PHY is busy or read data is not in valid state. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); -/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ -#define PHY_UPDATE_TIMEOUT 10000 - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return true; -} - -/******************************************************************************* - * eth_port_write_smi_reg - Write to PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform writes to PHY registers. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int value Register value. - * - * OUTPUT: - * Write the given value to the specified PHY register. - * - * RETURN: - * false if the PHY is busy. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return true; -} - -/******************************************************************************* - * eth_set_access_control - Config address decode parameters for Ethernet unit - * - * DESCRIPTION: - * This function configures the address decode parameters for the Gigabit - * Ethernet Controller according the given parameters struct. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * ETH_WIN_PARAM *param Address decode parameter struct. - * - * OUTPUT: - * An access window is opened using the given access parameters. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param) -{ - unsigned int access_prot_reg; - - /* Set access control register */ - access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG - (eth_port_num)); - access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ - access_prot_reg |= (param->access_ctrl << (param->win * 2)); - MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num), - access_prot_reg); - - /* Set window Size reg (SR) */ - MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 + - (ETH_SIZE_REG_GAP * param->win)), - (((param->size / 0x10000) - 1) << 16)); - - /* Set window Base address reg (BA) */ - MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), - (param->target | param->attributes | param->base_addr)); - /* High address remap reg (HARR) */ - if (param->win < 4) - MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 + - (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), - param->high_addr); - - /* Base address enable reg (BARER) */ - if (param->enable == 1) - MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); - else - MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); -} - -/******************************************************************************* - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Rx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer - * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. - * unsigned int rx_buff_base_addr Rx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Rx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr) -{ - ETH_RX_DESC *p_rx_desc; - ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ - unsigned int buffer_addr; - int ix; /* a counter */ - - - p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; - p_rx_prev_desc = p_rx_desc; - buffer_addr = rx_buff_base_addr; - - /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (rx_buff_base_addr & 0xF) - return false; - - /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) - return false; - - /* Rx buffers must be 64-bit aligned. */ - if ((rx_buff_base_addr + rx_buff_size) & 0x7) - return false; - - /* initialize the Rx descriptors ring */ - for (ix = 0; ix < rx_desc_num; ix++) { - p_rx_desc->buf_size = rx_buff_size; - p_rx_desc->byte_cnt = 0x0000; - p_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - p_rx_desc->next_desc_ptr = - ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; - p_rx_desc->buf_ptr = buffer_addr; - p_rx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_rx_desc, 0); - buffer_addr += rx_buff_size; - p_rx_prev_desc = p_rx_desc; - p_rx_desc = (ETH_RX_DESC *) - ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); - } - - /* Closing Rx descriptors ring */ - p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); - D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); - - /* Save Rx desc pointer to driver struct. */ - CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - - p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = - (ETH_RX_DESC *) rx_desc_base_addr; - p_eth_port_ctrl->rx_desc_area_size[rx_queue] = - rx_desc_num * RX_DESC_ALIGNED_SIZE; - - p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); - - return true; -} - -/******************************************************************************* - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Tx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer - * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. - * unsigned int tx_buff_base_addr Tx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Tx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr) -{ - - ETH_TX_DESC *p_tx_desc; - ETH_TX_DESC *p_tx_prev_desc; - unsigned int buffer_addr; - int ix; /* a counter */ - - - /* save the first desc pointer to link with the last descriptor */ - p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; - p_tx_prev_desc = p_tx_desc; - buffer_addr = tx_buff_base_addr; - - /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (tx_buff_base_addr & 0xF) - return false; - - /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((tx_buff_size > TX_BUFFER_MAX_SIZE) - || (tx_buff_size < TX_BUFFER_MIN_SIZE)) - return false; - - /* Initialize the Tx descriptors ring */ - for (ix = 0; ix < tx_desc_num; ix++) { - p_tx_desc->byte_cnt = 0x0000; - p_tx_desc->l4i_chk = 0x0000; - p_tx_desc->cmd_sts = 0x00000000; - p_tx_desc->next_desc_ptr = - ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; - - p_tx_desc->buf_ptr = buffer_addr; - p_tx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_tx_desc, 0); - buffer_addr += tx_buff_size; - p_tx_prev_desc = p_tx_desc; - p_tx_desc = (ETH_TX_DESC *) - ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); - - } - /* Closing Tx descriptors ring */ - p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; - D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); - /* Set Tx desc pointer in driver struct. */ - CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - - /* Init Tx ring base and size parameters */ - p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = - (ETH_TX_DESC *) tx_desc_base_addr; - p_eth_port_ctrl->tx_desc_area_size[tx_queue] = - (tx_desc_num * TX_DESC_ALIGNED_SIZE); - - /* Add the queue to the list of Tx queues of this port */ - p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); - - return true; -} - -/******************************************************************************* - * eth_port_send - Send an Ethernet packet - * - * DESCRIPTION: - * This routine send a given packet described by p_pktinfo parameter. It - * supports transmitting of a packet spaned over multiple buffers. The - * routine updates 'curr' and 'first' indexes according to the packet - * segment passed to the routine. In case the packet segment is first, - * the 'first' index is update. In any case, the 'curr' index is updated. - * If the routine get into Tx resource error it assigns 'curr' index as - * 'first'. This way the function can abort Tx process of multiple - * descriptors per packet. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'curr' and 'first' indexes are updated. - * - * RETURN: - * ETH_QUEUE_FULL in case of Tx resource error. - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_first; - volatile ETH_TX_DESC *p_tx_desc_curr; - volatile ETH_TX_DESC *p_tx_next_desc_curr; - volatile ETH_TX_DESC *p_tx_desc_used; - unsigned int command_status; - - /* Do not process Tx ring in case of Tx ring resource error */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - return ETH_QUEUE_FULL; - - /* Get the Tx Desc ring indexes */ - CURR_TFD_GET (p_tx_desc_curr, tx_queue); - USED_TFD_GET (p_tx_desc_used, tx_queue); - - if (p_tx_desc_curr == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); - command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; - - if (command_status & (ETH_TX_FIRST_DESC)) { - /* Update first desc */ - FIRST_TFD_SET (p_tx_desc_curr, tx_queue); - p_tx_desc_first = p_tx_desc_curr; - } else { - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - command_status |= ETH_BUFFER_OWNED_BY_DMA; - } - - /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ - /* boundary. We use the memory allocated for Tx descriptor. This memory */ - /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ - if (p_pkt_info->byte_cnt <= 8) { - printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ - return ETH_ERROR; - - p_tx_desc_curr->buf_ptr = - (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; - eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, - p_pkt_info->byte_cnt); - } else - p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; - - p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; - p_tx_desc_curr->return_info = p_pkt_info->return_info; - - if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { - /* Set last desc with DMA ownership and interrupt enable. */ - p_tx_desc_curr->cmd_sts = command_status | - ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; - - if (p_tx_desc_curr != p_tx_desc_first) - p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; - - /* Flush CPU pipe */ - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); - CPU_PIPE_FLUSH; - - /* Apply send command */ - ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); - - /* Finish Tx packet. Update first desc in case of Tx resource error */ - p_tx_desc_first = p_tx_next_desc_curr; - FIRST_TFD_SET (p_tx_desc_first, tx_queue); - - } else { - p_tx_desc_curr->cmd_sts = command_status; - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - } - - /* Check for ring index overlap in the Tx desc ring */ - if (p_tx_next_desc_curr == p_tx_desc_used) { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_desc_first, tx_queue); - - p_eth_port_ctrl->tx_resource_err[tx_queue] = true; - return ETH_QUEUE_LAST_RESOURCE; - } else { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); - return ETH_OK; - } -} - -/******************************************************************************* - * eth_tx_return_desc - Free all used Tx descriptors - * - * DESCRIPTION: - * This routine returns the transmitted packet information to the caller. - * It uses the 'first' index to support Tx desc return in case a transmit - * of a packet spanned over multiple buffer still in process. - * In case the Tx queue was in "resource error" condition, where there are - * no available Tx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'first' and 'used' indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_RETRY in case there is transmission in process. - * ETH_END_OF_JOB if the routine has nothing to release. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_used = NULL; - volatile ETH_TX_DESC *p_tx_desc_first = NULL; - unsigned int command_status; - - - /* Get the Tx Desc ring indexes */ - USED_TFD_GET (p_tx_desc_used, tx_queue); - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - - - /* Sanity check */ - if (p_tx_desc_used == NULL) - return ETH_ERROR; - - command_status = p_tx_desc_used->cmd_sts; - - /* Still transmitting... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_RETRY; - } - - /* Stop release. About to overlap the current available Tx descriptor */ - if ((p_tx_desc_used == p_tx_desc_first) && - (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_END_OF_JOB; - } - - /* Pass the packet information to the caller */ - p_pkt_info->cmd_sts = command_status; - p_pkt_info->return_info = p_tx_desc_used->return_info; - p_tx_desc_used->return_info = 0; - - /* Update the next descriptor to release. */ - USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); - - /* Any Tx return cancels the Tx resource error status */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - p_eth_port_ctrl->tx_resource_err[tx_queue] = false; - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - - return ETH_OK; - -} - -/******************************************************************************* - * eth_port_receive - Get received information from Rx ring. - * - * DESCRIPTION: - * This routine returns the received data to the caller. There is no - * data copying during routine operation. All information is returned - * using pointer to packet information struct passed from the caller. - * If the routine exhausts Rx ring resources then the resource error flag - * is set. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Rx ring current and used indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_QUEUE_FULL if Rx ring resources are exhausted. - * ETH_END_OF_JOB if there is no received data. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_rx_curr_desc; - volatile ETH_RX_DESC *p_rx_next_curr_desc; - volatile ETH_RX_DESC *p_rx_used_desc; - unsigned int command_status; - - /* Do not process Rx ring in case of Rx ring resource error */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { - printf ("\nRx Queue is full ...\n"); - return ETH_QUEUE_FULL; - } - - /* Get the Rx Desc ring 'curr and 'used' indexes */ - CURR_RFD_GET (p_rx_curr_desc, rx_queue); - USED_RFD_GET (p_rx_used_desc, rx_queue); - - /* Sanity check */ - if (p_rx_curr_desc == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); - command_status = p_rx_curr_desc->cmd_sts; - - /* Nothing to receive... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); -/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ - return ETH_END_OF_JOB; - } - - p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; - p_pkt_info->cmd_sts = command_status; - p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; - p_pkt_info->return_info = p_rx_curr_desc->return_info; - p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ - - /* Clean the return info field to indicate that the packet has been */ - /* moved to the upper layers */ - p_rx_curr_desc->return_info = 0; - - /* Update 'curr' in data structure */ - CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); - - /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ - if (p_rx_next_curr_desc == p_rx_used_desc) - p_eth_port_ctrl->rx_resource_err[rx_queue] = true; - - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); - CPU_PIPE_FLUSH; - return ETH_OK; -} - -/******************************************************************************* - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. - * - * DESCRIPTION: - * This routine returns a Rx buffer back to the Rx ring. It retrieves the - * next 'used' descriptor and attached the returned buffer to it. - * In case the Rx ring was in "resource error" condition, where there are - * no available Rx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info Information on the returned buffer. - * - * OUTPUT: - * New available Rx resource in Rx descriptor ring. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ - - /* Get 'used' Rx descriptor */ - USED_RFD_GET (p_used_rx_desc, rx_queue); - - /* Sanity check */ - if (p_used_rx_desc == NULL) - return ETH_ERROR; - - p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; - p_used_rx_desc->return_info = p_pkt_info->return_info; - p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; - p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */ - - /* Flush the write pipe */ - CPU_PIPE_FLUSH; - - /* Return the descriptor to DMA ownership */ - p_used_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - - /* Flush descriptor and CPU pipe */ - D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); - CPU_PIPE_FLUSH; - - /* Move the used descriptor pointer to the next descriptor */ - USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); - - /* Any Rx return cancels the Rx resource error status */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) - p_eth_port_ctrl->rx_resource_err[rx_queue] = false; - - return ETH_OK; -} - -/******************************************************************************* - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path - * - * DESCRIPTION: - * This routine sets the RX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the tClk of the MV-643xx chip - * , and the required delay of the interrupt in usec. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in usec - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set RX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - ((coal & 0x3fff) << 8) | - (MV_REG_READ - (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num)) - & 0xffc000ff)); - return coal; -} - -#endif -/******************************************************************************* - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path - * - * DESCRIPTION: - * This routine sets the TX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the t_cLK frequency of the - * MV-643xx chip and the required delay in the interrupt in uSec - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in uSeconds - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set TX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), - coal << 4); - return coal; -} -#endif - -/******************************************************************************* - * eth_b_copy - Copy bytes from source to destination - * - * DESCRIPTION: - * This function supports the eight bytes limitation on Tx buffer size. - * The routine will zero eight bytes starting from the destination address - * followed by copying bytes from the source address to the destination. - * - * INPUT: - * unsigned int src_addr 32 bit source address. - * unsigned int dst_addr 32 bit destination address. - * int byte_count Number of bytes to copy. - * - * OUTPUT: - * See description. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count) -{ - /* Zero the dst_addr area */ - *(unsigned int *) dst_addr = 0x0; - - while (byte_count != 0) { - *(char *) dst_addr = *(char *) src_addr; - dst_addr++; - src_addr++; - byte_count--; - } -} diff --git a/board/Marvell/db64360/mv_eth.h b/board/Marvell/db64360/mv_eth.h deleted file mode 100644 index 943d30b..0000000 --- a/board/Marvell/db64360/mv_eth.h +++ /dev/null @@ -1,844 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mv_eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __DB64360_ETH_H__ -#define __DB64360_ETH_H__ - -#include -#include -#include -#include -#include -#include "mv_regs.h" -#include "../common/ppc_error_no.h" - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ -#ifndef MAX_SKB_FRAGS -#define MAX_SKB_FRAGS 0 -#endif - -/* Port attributes */ -/*#define MAX_RX_QUEUE_NUM 8*/ -/*#define MAX_TX_QUEUE_NUM 8*/ -#define MAX_RX_QUEUE_NUM 1 -#define MAX_TX_QUEUE_NUM 1 - - -/* Use one TX queue and one RX queue */ -#define MV64360_TX_QUEUE_NUM 1 -#define MV64360_RX_QUEUE_NUM 1 - -/* - * Number of RX / TX descriptors on RX / TX rings. - * Note that allocating RX descriptors is done by allocating the RX - * ring AND a preallocated RX buffers (skb's) for each descriptor. - * The TX descriptors only allocates the TX descriptors ring, - * with no pre allocated TX buffers (skb's are allocated by higher layers. - */ - -/* Default TX ring size is 10 descriptors */ -#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE -#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE -#else -#define MV64360_TX_QUEUE_SIZE 4 -#endif - -/* Default RX ring size is 4 descriptors */ -#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE -#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE -#else -#define MV64360_RX_QUEUE_SIZE 4 -#endif - -#ifdef CONFIG_RX_BUFFER_SIZE -#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE -#else -#define MV64360_RX_BUFFER_SIZE 1600 -#endif - -#ifdef CONFIG_TX_BUFFER_SIZE -#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE -#else -#define MV64360_TX_BUFFER_SIZE 1600 -#endif - - -/* - * Network device statistics. Akin to the 2.0 ether stats but - * with byte counters. - */ - -struct net_device_stats -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; -}; - - -/* Private data structure used for ethernet device */ -struct mv64360_eth_priv { - unsigned int port_num; - struct net_device_stats *stats; - -/* to buffer area aligned */ - char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ - char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ - - /* Size of Tx Ring per queue */ - unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; - - - /* Size of Rx Ring per queue */ - unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; - - /* Magic Number for Ethernet running */ - unsigned int eth_running; - -}; - - -int mv64360_eth_init (struct eth_device *dev); -int mv64360_eth_stop (struct eth_device *dev); -int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length); -/* return db64360_eth0_poll(); */ - -int mv64360_eth_open (struct eth_device *dev); - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - - -/******************************************************************************** - * Header File for : MV-643xx network interface header - * - * DESCRIPTION: - * This header file contains macros typedefs and function declaration for - * the Marvell Gig Bit Ethernet Controller. - * - * DEPENDENCIES: - * None. - * - *******************************************************************************/ - - -#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY -#ifdef CONFIG_MV64360_SRAM_CACHEABLE -/* In case SRAM is cacheable but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case SRAM is cache coherent or non-cacheable */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif -#else -#ifdef CONFIG_NOT_COHERENT_CACHE -/* In case of descriptors on DDR but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case of descriptors on DDR and cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif /* CONFIG_NOT_COHERENT_CACHE */ -#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ - - -#define CPU_PIPE_FLUSH \ -{ \ - __asm__ __volatile__ ("eieio"); \ -} - - -/* defines */ - -/* Default port configuration value */ -#define PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -/* Default port extend configuration value */ -#define PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - - -/* Default sdma control value */ -#ifdef CONFIG_NOT_COHERENT_CACHE -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_16_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_16_64BIT; -#else -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT; -#endif - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ETTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_1552BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; - -#define RX_BUFFER_MAX_SIZE 0xFFFF -#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ - -#define RX_BUFFER_MIN_SIZE 0x8 -#define TX_BUFFER_MIN_SIZE 0x8 - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ - -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 - -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define RX_DESC_ALIGNED_SIZE 0x20 -#define TX_DESC_ALIGNED_SIZE 0x20 - -/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -#define TX_BUF_OFFSET_IN_DESC 0x18 -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Gap define */ -#define ETH_BAR_GAP 0x8 -#define ETH_SIZE_REG_GAP 0x8 -#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define ETH_PORT_ACCESS_CTRL_GAP 0x4 - -/* Gigabit Ethernet Unit Global Registers */ - -/* MIB Counters register definitions */ -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 -#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc -#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 -#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c -#define ETH_MIB_FRAMES_64_OCTETS 0x20 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c -#define ETH_MIB_GOOD_FRAMES_SENT 0x40 -#define ETH_MIB_EXCESSIVE_COLLISION 0x44 -#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 -#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 -#define ETH_MIB_FC_SENT 0x54 -#define ETH_MIB_GOOD_FC_RECEIVED 0x58 -#define ETH_MIB_BAD_FC_RECEIVED 0x5c -#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 -#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 -#define ETH_MIB_OVERSIZE_RECEIVED 0x68 -#define ETH_MIB_JABBER_RECEIVED 0x6c -#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 -#define ETH_MIB_BAD_CRC_EVENT 0x74 -#define ETH_MIB_COLLISION 0x78 -#define ETH_MIB_LATE_COLLISION 0x7c - -/* Port serial status reg (PSR) */ -#define ETH_INTERFACE_GMII_MII 0 -#define ETH_INTERFACE_PCM BIT0 -#define ETH_LINK_IS_DOWN 0 -#define ETH_LINK_IS_UP BIT1 -#define ETH_PORT_AT_HALF_DUPLEX 0 -#define ETH_PORT_AT_FULL_DUPLEX BIT2 -#define ETH_RX_FLOW_CTRL_DISABLED 0 -#define ETH_RX_FLOW_CTRL_ENBALED BIT3 -#define ETH_GMII_SPEED_100_10 0 -#define ETH_GMII_SPEED_1000 BIT4 -#define ETH_MII_SPEED_10 0 -#define ETH_MII_SPEED_100 BIT5 -#define ETH_NO_TX 0 -#define ETH_TX_IN_PROGRESS BIT7 -#define ETH_BYPASS_NO_ACTIVE 0 -#define ETH_BYPASS_ACTIVE BIT8 -#define ETH_PORT_NOT_AT_PARTITION_STATE 0 -#define ETH_PORT_AT_PARTITION_STATE BIT9 -#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 -#define ETH_PORT_TX_FIFO_EMPTY BIT10 - - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define ETH_UNICAST_NORMAL_MODE 0 -#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 -#define ETH_DEFAULT_RX_QUEUE_0 0 -#define ETH_DEFAULT_RX_QUEUE_1 BIT1 -#define ETH_DEFAULT_RX_QUEUE_2 BIT2 -#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_4 BIT3 -#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) -#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) -#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 -#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 -#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 -#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 -#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) -#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) -#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 -#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 -#define ETH_RECEIVE_BC_IF_IP 0 -#define ETH_REJECT_BC_IF_IP BIT8 -#define ETH_RECEIVE_BC_IF_ARP 0 -#define ETH_REJECT_BC_IF_ARP BIT9 -#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 -#define ETH_CAPTURE_TCP_FRAMES_DIS 0 -#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 -#define ETH_CAPTURE_UDP_FRAMES_DIS 0 -#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 -#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 -#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 -#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 -#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 -#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) -#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) -#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 -#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 -#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 -#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 -#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) -#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) -#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 -#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 -#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 -#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 -#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) -#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) - - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define ETH_CLASSIFY_EN BIT0 -#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 -#define ETH_PARTITION_DISABLE 0 -#define ETH_PARTITION_ENABLE BIT2 - - -/* Tx/Rx queue command reg (RQCR/TQCR)*/ -#define ETH_QUEUE_0_ENABLE BIT0 -#define ETH_QUEUE_1_ENABLE BIT1 -#define ETH_QUEUE_2_ENABLE BIT2 -#define ETH_QUEUE_3_ENABLE BIT3 -#define ETH_QUEUE_4_ENABLE BIT4 -#define ETH_QUEUE_5_ENABLE BIT5 -#define ETH_QUEUE_6_ENABLE BIT6 -#define ETH_QUEUE_7_ENABLE BIT7 -#define ETH_QUEUE_0_DISABLE BIT8 -#define ETH_QUEUE_1_DISABLE BIT9 -#define ETH_QUEUE_2_DISABLE BIT10 -#define ETH_QUEUE_3_DISABLE BIT11 -#define ETH_QUEUE_4_DISABLE BIT12 -#define ETH_QUEUE_5_DISABLE BIT13 -#define ETH_QUEUE_6_DISABLE BIT14 -#define ETH_QUEUE_7_DISABLE BIT15 - - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define ETH_RIFB BIT0 -#define ETH_RX_BURST_SIZE_1_64BIT 0 -#define ETH_RX_BURST_SIZE_2_64BIT BIT1 -#define ETH_RX_BURST_SIZE_4_64BIT BIT2 -#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) -#define ETH_RX_BURST_SIZE_16_64BIT BIT3 -#define ETH_BLM_RX_NO_SWAP BIT4 -#define ETH_BLM_RX_BYTE_SWAP 0 -#define ETH_BLM_TX_NO_SWAP BIT5 -#define ETH_BLM_TX_BYTE_SWAP 0 -#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 -#define ETH_DESCRIPTORS_NO_SWAP 0 -#define ETH_TX_BURST_SIZE_1_64BIT 0 -#define ETH_TX_BURST_SIZE_2_64BIT BIT22 -#define ETH_TX_BURST_SIZE_4_64BIT BIT23 -#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) -#define ETH_TX_BURST_SIZE_16_64BIT BIT24 - - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define ETH_SERIAL_PORT_DISABLE 0 -#define ETH_SERIAL_PORT_ENABLE BIT0 -#define ETH_FORCE_LINK_PASS BIT1 -#define ETH_DO_NOT_FORCE_LINK_PASS 0 -#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 -#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 -#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 -#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 -#define ETH_ADV_NO_FLOW_CTRL 0 -#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 -#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 -#define ETH_FORCE_BP_MODE_NO_JAM 0 -#define ETH_FORCE_BP_MODE_JAM_TX BIT7 -#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 -#define ETH_FORCE_LINK_FAIL 0 -#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 -#define ETH_RETRANSMIT_16_ETTEMPTS 0 -#define ETH_RETRANSMIT_FOREVER BIT11 -#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 -#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 -#define ETH_DTE_ADV_0 0 -#define ETH_DTE_ADV_1 BIT14 -#define ETH_DISABLE_AUTO_NEG_BYPASS 0 -#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 -#define ETH_AUTO_NEG_NO_CHANGE 0 -#define ETH_RESTART_AUTO_NEG BIT16 -#define ETH_MAX_RX_PACKET_1518BYTE 0 -#define ETH_MAX_RX_PACKET_1522BYTE BIT17 -#define ETH_MAX_RX_PACKET_1552BYTE BIT18 -#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) -#define ETH_MAX_RX_PACKET_9192BYTE BIT19 -#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) -#define ETH_SET_EXT_LOOPBACK BIT20 -#define ETH_CLR_EXT_LOOPBACK 0 -#define ETH_SET_FULL_DUPLEX_MODE BIT21 -#define ETH_SET_HALF_DUPLEX_MODE 0 -#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 -#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define ETH_SET_GMII_SPEED_TO_10_100 0 -#define ETH_SET_GMII_SPEED_TO_1000 BIT23 -#define ETH_SET_MII_SPEED_TO_10 0 -#define ETH_SET_MII_SPEED_TO_100 BIT24 - - -/* SMI reg */ -#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ -#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ -#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ -#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ - -/* SDMA command status fields macros */ - -/* Tx & Rx descriptors status */ -#define ETH_ERROR_SUMMARY (BIT0) - -/* Tx & Rx descriptors command */ -#define ETH_BUFFER_OWNED_BY_DMA (BIT31) - -/* Tx descriptors status */ -#define ETH_LC_ERROR (0 ) -#define ETH_UR_ERROR (BIT1 ) -#define ETH_RL_ERROR (BIT2 ) -#define ETH_LLC_SNAP_FORMAT (BIT9 ) - -/* Rx descriptors status */ -#define ETH_CRC_ERROR (0 ) -#define ETH_OVERRUN_ERROR (BIT1 ) -#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) -#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) -#define ETH_VLAN_TAGGED (BIT19) -#define ETH_BPDU_FRAME (BIT20) -#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) -#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) -#define ETH_OTHER_FRAME_TYPE (BIT22) -#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) -#define ETH_FRAME_TYPE_IP_V_4 (BIT24) -#define ETH_FRAME_HEADER_OK (BIT25) -#define ETH_RX_LAST_DESC (BIT26) -#define ETH_RX_FIRST_DESC (BIT27) -#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) -#define ETH_RX_ENABLE_INTERRUPT (BIT29) -#define ETH_LAYER_4_CHECKSUM_OK (BIT30) - -/* Rx descriptors byte count */ -#define ETH_FRAME_FRAGMENTED (BIT2) - -/* Tx descriptors command */ -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) -#define ETH_FRAME_SET_TO_VLAN (BIT15) -#define ETH_TCP_FRAME (0 ) -#define ETH_UDP_FRAME (BIT16) -#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) -#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) -#define ETH_ZERO_PADDING (BIT19) -#define ETH_TX_LAST_DESC (BIT20) -#define ETH_TX_FIRST_DESC (BIT21) -#define ETH_GEN_CRC (BIT22) -#define ETH_TX_ENABLE_INTERRUPT (BIT23) -#define ETH_AUTO_MODE (BIT30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attributes */ -#define EBAR_ATTR_DRAM_CS0 0x00000E00 -#define EBAR_ATTR_DRAM_CS1 0x00000D00 -#define EBAR_ATTR_DRAM_CS2 0x00000B00 -#define EBAR_ATTR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 -#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 -#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 -#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 -#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 - -/* CPU 60x bus or internal SRAM interface */ -#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define EBAR_ATTR_CBS_SRAM 0x00000000 -#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY BIT0 -#define EWIN_ACCESS_FULL (BIT1 | BIT0) -#define EWIN0_ACCESS_MASK 0x0003 -#define EWIN1_ACCESS_MASK 0x000C -#define EWIN2_ACCESS_MASK 0x0030 -#define EWIN3_ACCESS_MASK 0x00C0 - -/* typedefs */ - -typedef enum _eth_port -{ - ETH_0 = 0, - ETH_1 = 1, - ETH_2 = 2 -}ETH_PORT; - -typedef enum _eth_func_ret_status -{ - ETH_OK, /* Returned as expected. */ - ETH_ERROR, /* Fundamental error. */ - ETH_RETRY, /* Could not process request. Try later. */ - ETH_END_OF_JOB, /* Ring has nothing to process. */ - ETH_QUEUE_FULL, /* Ring resource error. */ - ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ -}ETH_FUNC_RET_STATUS; - -typedef enum _eth_queue -{ - ETH_Q0 = 0, - ETH_Q1 = 1, - ETH_Q2 = 2, - ETH_Q3 = 3, - ETH_Q4 = 4, - ETH_Q5 = 5, - ETH_Q6 = 6, - ETH_Q7 = 7 -} ETH_QUEUE; - -typedef enum _addr_win -{ - ETH_WIN0, - ETH_WIN1, - ETH_WIN2, - ETH_WIN3, - ETH_WIN4, - ETH_WIN5 -} ETH_ADDR_WIN; - -typedef enum _eth_target -{ - ETH_TARGET_DRAM , - ETH_TARGET_DEVICE, - ETH_TARGET_CBS , - ETH_TARGET_PCI0 , - ETH_TARGET_PCI1 -}ETH_TARGET; - -typedef struct _eth_rx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short buf_size ; /* Buffer size */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_RX_DESC; - - -typedef struct _eth_tx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_TX_DESC; - -/* Unified struct for Rx and Tx operations. The user is not required to */ -/* be familier with neither Tx nor Rx descriptors. */ -typedef struct _pkt_info -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} PKT_INFO; - - -typedef struct _eth_win_param -{ - ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ - ETH_TARGET target; /* System targets. See ETH_TARGET enum */ - unsigned short attributes; /* BAR attributes. See above macros. */ - unsigned int base_addr; /* Window base address in unsigned int form */ - unsigned int high_addr; /* Window high address in unsigned int form */ - unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ - bool enable; /* Enable/disable access to the window. */ - unsigned short access_ctrl; /* Access ctrl register. see above macros */ -} ETH_WIN_PARAM; - - -/* Ethernet port specific infomation */ - -typedef struct _eth_port_ctrl -{ - ETH_PORT port_num; /* User Ethernet port number */ - int port_phy_addr; /* User phy address of Ethrnet port */ - unsigned char port_mac_addr[6]; /* User defined port MAC address. */ - unsigned int port_config; /* User port configuration value */ - unsigned int port_config_extend; /* User port config extend value */ - unsigned int port_sdma_config; /* User port SDMA config value */ - unsigned int port_serial_control; /* User port serial control value */ - unsigned int port_tx_queue_command; /* Port active Tx queues summary */ - unsigned int port_rx_queue_command; /* Port active Rx queues summary */ - - /* User function to cast virtual address to CPU bus address */ - unsigned int (*port_virt_to_phys)(unsigned int addr); - /* User scratch pad for user specific data structures */ - void *port_private; - - bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ - bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ - - /* Tx/Rx rings managment indexes fields. For driver use */ - - /* Next available Rx resource */ - volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; - /* Returning Rx resource */ - volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; - - /* Next available Tx resource */ - volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; - /* Returning Tx resource */ - volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; - /* An extra Tx index to support transmit of multiple buffers per packet */ - volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; - - /* Tx/Rx rings size and base variables fields. For driver use */ - - volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; - unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; - char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; - - volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; - unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; - char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; - -} ETH_PORT_INFO; - - -/* ethernet.h API list */ - -/* Port operation control routines */ -static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); -static void eth_port_reset(ETH_PORT eth_port_num); -static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); - - -/* Port MAC address routines */ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue); -#if 0 /* FIXME */ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, - int option); -#endif - -/* PHY and MIB routines */ -static bool ethernet_phy_reset(ETH_PORT eth_port_num); - -static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int value); - -static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int* value); - -static void eth_clear_mib_counters(ETH_PORT eth_port_num); - -/* Port data flow control routines */ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); - - -static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr); - -static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr); - -#endif /* MV64360_ETH_ */ diff --git a/board/Marvell/db64360/mv_regs.h b/board/Marvell/db64360/mv_regs.h deleted file mode 100644 index 0d6370b..0000000 --- a/board/Marvell/db64360/mv_regs.h +++ /dev/null @@ -1,1124 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/******************************************************************************** -* gt64360r.h - GT-64360 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_regsh -#define __INCmv_regsh - -#define MV64360 - -/* Supported by the Atlantis */ -#define MV64360_INCLUDE_PCI_1 -#define MV64360_INCLUDE_PCI_0_ARBITER -#define MV64360_INCLUDE_PCI_1_ARBITER -#define MV64360_INCLUDE_SNOOP_SUPPORT -#define MV64360_INCLUDE_P2P -#define MV64360_INCLUDE_ETH_PORT_2 -#define MV64360_INCLUDE_CPU_MAPPING -#define MV64360_INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64360_CS_0_BASE_ADDR 0x008 -#define MV64360_CS_0_SIZE 0x010 -#define MV64360_CS_1_BASE_ADDR 0x208 -#define MV64360_CS_1_SIZE 0x210 -#define MV64360_CS_2_BASE_ADDR 0x018 -#define MV64360_CS_2_SIZE 0x020 -#define MV64360_CS_3_BASE_ADDR 0x218 -#define MV64360_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64360_PCI_0_IO_BASE_ADDR 0x048 -#define MV64360_PCI_0_IO_SIZE 0x050 -#define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64360_PCI_0_MEMORY0_SIZE 0x060 -#define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64360_PCI_0_MEMORY1_SIZE 0x088 -#define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64360_PCI_0_MEMORY2_SIZE 0x260 -#define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64360_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64360_PCI_1_IO_BASE_ADDR 0x090 -#define MV64360_PCI_1_IO_SIZE 0x098 -#define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64360_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64360_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64360_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64360_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64360_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64360_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64360_CPU_CONFIG 0x000 -#define MV64360_CPU_MODE 0x120 -#define MV64360_CPU_MASTER_CONTROL 0x160 -#define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64360_SMP_WHO_AM_I 0x200 -#define MV64360_SMP_CPU0_DOORBELL 0x214 -#define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64360_SMP_CPU1_DOORBELL 0x224 -#define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64360_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64360_SMP_SEMAPHOR0 0x244 -#define MV64360_SMP_SEMAPHOR1 0x24c -#define MV64360_SMP_SEMAPHOR2 0x254 -#define MV64360_SMP_SEMAPHOR3 0x25c -#define MV64360_SMP_SEMAPHOR4 0x264 -#define MV64360_SMP_SEMAPHOR5 0x26c -#define MV64360_SMP_SEMAPHOR6 0x274 -#define MV64360_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64360_CPU_ERROR_ADDR_LOW 0x070 -#define MV64360_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64360_CPU_ERROR_DATA_LOW 0x128 -#define MV64360_CPU_ERROR_DATA_HIGH 0x130 -#define MV64360_CPU_ERROR_PARITY 0x138 -#define MV64360_CPU_ERROR_CAUSE 0x140 -#define MV64360_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64360_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64360_SRAM_CONFIG 0x380 -#define MV64360_SRAM_TEST_MODE 0X3F4 -#define MV64360_SRAM_ERROR_CAUSE 0x388 -#define MV64360_SRAM_ERROR_ADDR 0x390 -#define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64360_SRAM_ERROR_DATA_LOW 0x398 -#define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64360_SDRAM_CONFIG 0x1400 -#define MV64360_D_UNIT_CONTROL_LOW 0x1404 -#define MV64360_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64360_SDRAM_ADDR_CONTROL 0x1410 -#define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64360_SDRAM_OPERATION 0x1418 -#define MV64360_SDRAM_MODE 0x141c -#define MV64360_EXTENDED_DRAM_MODE 0x1420 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64360_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64360_SDRAM_ERROR_ADDR 0x1450 -#define MV64360_SDRAM_RECEIVED_ECC 0x1448 -#define MV64360_SDRAM_CALCULATED_ECC 0x144c -#define MV64360_SDRAM_ECC_CONTROL 0x1454 -#define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64360_DFCDL_CONFIG0 0x1480 -#define MV64360_DFCDL_CONFIG1 0x1484 -#define MV64360_DLL_WRITE 0x1488 -#define MV64360_DLL_READ 0x148c -#define MV64360_SRAM_ADDR 0x1490 -#define MV64360_SRAM_DATA0 0x1494 -#define MV64360_SRAM_DATA1 0x1498 -#define MV64360_SRAM_DATA2 0x149c -#define MV64360_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64360_DUNIT_DEBUG_LOW 0x1460 -#define MV64360_DUNIT_DEBUG_HIGH 0x1464 -#define MV64360_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64360_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64360_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64360_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64360_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64360_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64360_DEVICE_ERROR_ADDR 0x4d8 -#define MV64360_DEVICE_ERROR_DATA 0x4dc -#define MV64360_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64360_DEVICE_DEBUG_LOW 0x4e4 -#define MV64360_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64360_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64360_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64360_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64360_PCI_0_COMMAND 0xc00 -#define MV64360_PCI_1_COMMAND 0xc80 -#define MV64360_PCI_0_MODE 0xd00 -#define MV64360_PCI_1_MODE 0xd80 -#define MV64360_PCI_0_RETRY 0xc04 -#define MV64360_PCI_1_RETRY 0xc84 -#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64360_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64360_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64360_PCI_0_P2P_CONFIG 0x1d14 -#define MV64360_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64360_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64360_PCI_1_CONFIG_ADDR 0xc78 -#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64360_PCI_0_SERR_MASK 0xc28 -#define MV64360_PCI_1_SERR_MASK 0xca8 -#define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64360_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64360_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64360_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64360_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64360_PCI_0_ERROR_MASK 0x1d5c -#define MV64360_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64360_PCI_0_MMASK 0X1D24 -#define MV64360_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64360_PCI_STATUS_AND_COMMAND 0x004 -#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64360_PCI_VPD_ADDR 0x048 -#define MV64360_PCI_VPD_DATA 0x04c -#define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64360_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64360_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64360_PCI_X_COMMAND 0x060 -#define MV64360_PCI_X_STATUS 0x064 -#define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64360_ETH_PHY_ADDR_REG 0x2000 -#define MV64360_ETH_SMI_REG 0x2004 -#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64360_ETH_BAR_0 0x2200 -#define MV64360_ETH_BAR_1 0x2208 -#define MV64360_ETH_BAR_2 0x2210 -#define MV64360_ETH_BAR_3 0x2218 -#define MV64360_ETH_BAR_4 0x2220 -#define MV64360_ETH_BAR_5 0x2228 -#define MV64360_ETH_SIZE_REG_0 0x2204 -#define MV64360_ETH_SIZE_REG_1 0x220c -#define MV64360_ETH_SIZE_REG_2 0x2214 -#define MV64360_ETH_SIZE_REG_3 0x221c -#define MV64360_ETH_SIZE_REG_4 0x2224 -#define MV64360_ETH_SIZE_REG_5 0x222c -#define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64360_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64360_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64360_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64360_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64360_CUNIT_SIZE0 0xf204 -#define MV64360_CUNIT_SIZE1 0xf20c -#define MV64360_CUNIT_SIZE2 0xf214 -#define MV64360_CUNIT_SIZE3 0xf21c -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64360_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64360_CUNIT_CONFIG_REG 0xb40c -#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64360_CUNIT_DEBUG_LOW 0xf340 -#define MV64360_CUNIT_DEBUG_HIGH 0xf344 -#define MV64360_CUNIT_MMASK 0xf380 - - /* Cunit Base Address Enable Window Bits*/ -#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 -#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 -#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 -#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 - - /* MPSCs Clocks Routing Registers */ - -#define MV64360_MPSC_ROUTING_REG 0xb400 -#define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64360_SDMA_CAUSE_REG 0xb800 -#define MV64360_SDMA_MASK_REG 0xb880 - - -/****************************************/ -/* SDMA Address Space Targets */ -/****************************************/ - -#define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00 -#define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00 -#define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00 -#define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700 - -#define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01 -#define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01 -#define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01 -#define MV64360_SDMA_DEV_CS_3_TARGET 0x1701 - -#define MV64360_SDMA_BOOT_CS_TARGET 0x0f00 - -#define MV64360_SDMA_SRAM_TARGET 0x0003 -#define MV64360_SDMA_60X_BUS_TARGET 0x4003 - -#define MV64360_PCI_0_TARGET 0x0003 -#define MV64360_PCI_1_TARGET 0x0004 - - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* SDMA Window access protection */ -#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0 -#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1 -#define MV64360_SDMA_WIN_ACCESS_FULL 2 - -/* BRG Interrupts */ - -#define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) -#define MV64360_BRG_CAUSE_REG 0xb834 -#define MV64360_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_CONTROL 0x840 -#define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64360_DMA_CHANNEL1_CONTROL 0x844 -#define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64360_DMA_CHANNEL2_CONTROL 0x848 -#define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64360_DMA_CHANNEL3_CONTROL 0x84C -#define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64360_DMA_BASE_ADDR_REG0 0xa00 -#define MV64360_DMA_BASE_ADDR_REG1 0xa08 -#define MV64360_DMA_BASE_ADDR_REG2 0xa10 -#define MV64360_DMA_BASE_ADDR_REG3 0xa18 -#define MV64360_DMA_BASE_ADDR_REG4 0xa20 -#define MV64360_DMA_BASE_ADDR_REG5 0xa28 -#define MV64360_DMA_BASE_ADDR_REG6 0xa30 -#define MV64360_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64360_DMA_SIZE_REG0 0xa04 -#define MV64360_DMA_SIZE_REG1 0xa0c -#define MV64360_DMA_SIZE_REG2 0xa14 -#define MV64360_DMA_SIZE_REG3 0xa1c -#define MV64360_DMA_SIZE_REG4 0xa24 -#define MV64360_DMA_SIZE_REG5 0xa2c -#define MV64360_DMA_SIZE_REG6 0xa34 -#define MV64360_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64360_DMA_ARBITER_CONTROL 0x860 -#define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64360_DMA_ERROR_ADDR 0x8c8 -#define MV64360_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64360_DMA_DEBUG_LOW 0x8e0 -#define MV64360_DMA_DEBUG_HIGH 0x8e4 -#define MV64360_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64360_TIMER_COUNTER0 0x850 -#define MV64360_TIMER_COUNTER1 0x854 -#define MV64360_TIMER_COUNTER2 0x858 -#define MV64360_TIMER_COUNTER3 0x85C -#define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64360_WATCHDOG_CONFIG_REG 0xb410 -#define MV64360_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64360_I2C_SLAVE_ADDR 0xc000 -#define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64360_I2C_DATA 0xc004 -#define MV64360_I2C_CONTROL 0xc008 -#define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64360_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64360_GPP_IO_CONTROL 0xf100 -#define MV64360_GPP_LEVEL_CONTROL 0xf110 -#define MV64360_GPP_VALUE 0xf104 -#define MV64360_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64360_GPP_INTERRUPT_MASK0 0xf10c -#define MV64360_GPP_INTERRUPT_MASK1 0xf114 -#define MV64360_GPP_VALUE_SET 0xf118 -#define MV64360_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64360_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64360_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64360_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64360_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64360_MPP_CONTROL0 0xf000 -#define MV64360_MPP_CONTROL1 0xf004 -#define MV64360_MPP_CONTROL2 0xf008 -#define MV64360_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64360_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64360_SERIAL_INIT_CONTROL 0xf328 -#define MV64360_SERIAL_INIT_STATUS 0xf32c - - -#endif /* __INCgt64360rh */ diff --git a/board/Marvell/db64360/pci.c b/board/Marvell/db64360/pci.c deleted file mode 100644 index 5637284..0000000 --- a/board/Marvell/db64360/pci.c +++ /dev/null @@ -1,940 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* PCI.c - PCI functions */ - - -#include -#include - -#include "../include/pci.h" - -#undef DEBUG -#undef IDE_SET_NATIVE_MODE -static unsigned int local_buses[] = { 0, 0 }; - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { - {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, - {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, -}; - - -#ifdef DEBUG -static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; -static void gt_pci_bus_mode_display (PCI_HOST host) -{ - unsigned int mode; - - - mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; - switch (mode) { - case 0: - printf ("PCI %d bus mode: Conventional PCI\n", host); - break; - case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); - break; - case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); - break; - case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); - break; - default: - printf ("Unknown BUS %d\n", mode); - } -} -#endif - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_address_space_en[] = { - PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = 0; - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_WRITE (pci_configuration_data[host], data); -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, ®Base); - GT_REG_READ (regOffset + 8, ®End); - - if (regEnd <= regBase) - return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 16; - return regBase; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 16) & 0xffff; - high = ((bankBase + bankLength) >> 16) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xffff) << 16; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - return ((high & 0xffff) + 1) << 16; -} - - -/* ronen - 7/Dec/03*/ -/******************************************************************** -* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. -* Inputs: one of the PCI BAR -*********************************************************************/ -void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - /*ronen different function for 3rd bank. */ - unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; - - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + offset, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); - gtPciEnableInternalBAR (host, bank); -} - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData & regData); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum, unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE (pci_p2p_configuration[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), bus, - value); - } - return 0; -} - - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - /*ronen different function for 3rd bank. */ - unsigned int offset = - (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - - -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ -/* and is curently not called *. */ -#if 0 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - - {} -}; - -struct pci_controller pci0_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST0); -#endif - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci0_hose.last_busno = pci_hose_scan (&pci0_hose); - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); -#endif - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci1_hose.first_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - - pci1_hose.last_busno = pci_hose_scan (&pci1_hose); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -} diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c deleted file mode 100644 index d2635f8..0000000 --- a/board/Marvell/db64360/sdram_init.c +++ /dev/null @@ -1,1984 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************* - * adaption for the Marvell DB64360 Board - * Ingo Assmus (ingo.assmus@keymile.com) - ************************************************************************/ - - -/* sdram_init.c - automatic memory sizing */ - -#include -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include - -#include "eth.h" -#include "mpsc.h" -#include "../common/i2c.h" -#include "64360.h" -#include "mv_regs.h" - -#undef DEBUG -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -int set_dfcdlInit (void); /* setup delay line of Mv64360 */ -int mvDmaIsChannelActive (int); -int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); -int mvDmaTransfer (int, ulong, ulong, ulong, ulong); - -/* ------------------------------------------------------------------------- */ - -int -memory_map_bank (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ -#ifdef MAP_PCI - PCI_HOST host; -#endif - - -#ifdef DEBUG - if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf ("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank (bankNo, bankBase, bankLength); - -#ifdef MAP_PCI - for (host = PCI_HOST0; host <= PCI_HOST1; host++) { - const int features = - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | PCI_NO_SWAP; - - pciMapMemoryBank (host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures (host, bankNo, features, bankBase, - bankLength); - } -#endif - return 0; -} - -#define GB (1 << 30) - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; -} sdram_info_t; - -/* Typedefs for 'gtAuxilGetDIMMinfo' function */ - -typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE; - -typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, - SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, -} VOLTAGE_INTERFACE; - -typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 = - 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 = - 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR; -typedef enum _max_CL_supported_SD { SD_CL_1 = - 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, - SD_FAULT } MAX_CL_SUPPORTED_SD; - - -/* SDRAM/DDR information struct */ -typedef struct _gtMemoryDimmInfo { - MEMORY_TYPE memoryType; - unsigned int numOfRowAddresses; - unsigned int numOfColAddresses; - unsigned int numOfModuleBanks; - unsigned int dataWidth; - VOLTAGE_INTERFACE voltageInterface; - unsigned int errorCheckType; /* ECC , PARITY.. */ - unsigned int sdramWidth; /* 4,8,16 or 32 */ ; - unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ - unsigned int minClkDelay; - unsigned int burstLengthSupported; - unsigned int numOfBanksOnEachDevice; - unsigned int suportedCasLatencies; - unsigned int RefreshInterval; - unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ - unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ - MAX_CL_SUPPORTED_DDR maxClSupported_DDR; - MAX_CL_SUPPORTED_SD maxClSupported_SD; - unsigned int moduleBankDensity; - /* module attributes (true for yes) */ - bool bufferedAddrAndControlInputs; - bool registeredAddrAndControlInputs; - bool onCardPLL; - bool bufferedDQMBinputs; - bool registeredDQMBinputs; - bool differentialClockInput; - bool redundantRowAddressing; - - /* module general attributes */ - bool suportedAutoPreCharge; - bool suportedPreChargeAll; - bool suportedEarlyRasPreCharge; - bool suportedWrite1ReadBurst; - bool suported5PercentLowVCC; - bool suported5PercentUpperVCC; - /* module timing parameters */ - unsigned int minRasToCasDelay; - unsigned int minRowActiveRowActiveDelay; - unsigned int minRasPulseWidth; - unsigned int minRowPrechargeTime; /* measured in ns */ - - int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ - int addrAndCommandSetupTime; /* (measured in ns/100) */ - int dataInputSetupTime; /* LoP left of point (measured in ns) */ - int dataInputHoldTime; /* LoP left of point (measured in ns) */ -/* tAC times for highest 2nd and 3rd highest CAS Latency values */ - unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ - - /* Parameters calculated from - the extracted DIMM information */ - unsigned int size; - unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ - unsigned int numberOfDevices; - uchar drb_size; /* DRAM size in n*64Mbit */ - uchar slot; /* Slot Number this module is inserted in */ - uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ -#ifdef DEBUG - uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ - uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ - uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ - unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ - unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ - unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ - uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ - -#endif -} AUX_MEM_DIMM_INFO; - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NS10to10PS (unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ -static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned long spd_checksum; - -#ifdef ZUMA_NTL - /* zero all the values */ - memset (info, 0, sizeof (*info)); - -/* - if (!slot) { - info->slot = 0; - info->banks = 1; - info->registered = 0; - info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */ -/* info->tpar = 3; - info->tras_clocks = 5; - info->burst_len = 4; -*/ -#ifdef CONFIG_MV64360_ECC - /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ - dimmInfo->errorCheckType = 2; -/* info->ecc = 2;*/ -#endif -} - -return 0; - -#else - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; - -#ifdef DEBUG - unsigned int k; -#endif - unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; - int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; - uchar supp_cal, cal_val; - ulong memclk, tmemclk; - ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; - uchar data[128]; - - memclk = gd->bus_clk; - tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - - DP (puts ("before i2c read\n")); - - ret = i2c_read (addr, 0, 1, data, 128); - - DP (puts ("after i2c read\n")); - - /* zero all the values */ - memset (dimmInfo, 0, sizeof (*dimmInfo)); - - /* copy the SPD content 1:1 into the dimmInfo structure */ - for (i = 0; i <= 127; i++) { - dimmInfo->spd_raw_data[i] = data[i]; - } - - if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); - return 0; - } else - dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ - -#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT - - for (i = 0; i <= 127; i++) { - printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], - data[i]); - } - -#endif -#ifdef DEBUG -/* find Manufactura of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { - dimmInfo->manufactura[i] = data[64 + i]; - } - printf ("\nThis RAM-Module is produced by: %s\n", - dimmInfo->manufactura); - -/* find Manul-ID of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { - dimmInfo->modul_id[i] = data[73 + i]; - } - printf ("The Module-ID of this RAM-Module is: %s\n", - dimmInfo->modul_id); - -/* find Vendor-Data of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { - dimmInfo->vendor_data[i] = data[99 + i]; - } - printf ("Vendor Data of this RAM-Module is: %s\n", - dimmInfo->vendor_data); - -/* find modul_serial_no of Dimm Module */ - dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); - printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", - dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); - -/* find Manufac-Data of Dimm Module */ - dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); - printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ - -/* find modul_revision of Dimm Module */ - dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); - printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ - -/* find manufac_place of Dimm Module */ - dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); - printf ("manufac_place of this RAM-Module is: %d\n", - dimmInfo->manufac_place); - -#endif - -/*------------------------------------------------------------------------------------------------------------------------------*/ -/* calculate SPD checksum */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - spd_checksum = 0; - - for (i = 0; i <= 62; i++) { - spd_checksum += data[i]; - } - - if ((spd_checksum & 0xff) != data[63]) { - printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); - hang (); - } - - else - printf ("SPD Checksum ok!\n"); - - -/*------------------------------------------------------------------------------------------------------------------------------*/ - for (i = 2; i <= 35; i++) { - switch (i) { - case 2: /* Memory type (DDR / SDRAM) */ - dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; -#ifdef DEBUG - if (dimmInfo->memoryType == 0) - DP (printf - ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); - if (dimmInfo->memoryType == 1) - DP (printf - ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 3: /* Number Of Row Addresses */ - dimmInfo->numOfRowAddresses = data[i]; - DP (printf - ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 4: /* Number Of Column Addresses */ - dimmInfo->numOfColAddresses = data[i]; - DP (printf - ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 5: /* Number Of Module Banks */ - dimmInfo->numOfModuleBanks = data[i]; - DP (printf - ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 6: /* Data Width */ - dimmInfo->dataWidth = data[i]; - DP (printf - ("Module Data Width: %d\n", - dimmInfo->dataWidth)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 8: /* Voltage Interface */ - switch (data[i]) { - case 0x0: - dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); - break; - case 0x1: - dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); - break; - case 0x2: - dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); - break; - case 0x3: - dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); - break; - case 0x4: - dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); - break; - default: - dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); - break; - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 9: /* Minimum Cycle Time At Max CasLatancy */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = - rightOfPoint; - DP (printf - ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 10: /* Clock To Data Out */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOut_LoP = leftOfPoint; - dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - -/*#ifdef CONFIG_ECC */ - case 11: /* Error Check Type */ - dimmInfo->errorCheckType = data[i]; - DP (printf - ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); - break; -/* #endif */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 12: /* Refresh Interval */ - dimmInfo->RefreshInterval = data[i]; - DP (printf - ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 13: /* Sdram Width */ - dimmInfo->sdramWidth = data[i]; - DP (printf - ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 14: /* Error Check Data Width */ - dimmInfo->errorCheckDataWidth = data[i]; - DP (printf - ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 15: /* Minimum Clock Delay */ - dimmInfo->minClkDelay = data[i]; - DP (printf - ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 16: /* Burst Length Supported */ - /******-******-******-******* - * bit3 | bit2 | bit1 | bit0 * - *******-******-******-******* - burst length = * 8 | 4 | 2 | 1 * - ***************************** - - If for example bit0 and bit2 are set, the burst - length supported are 1 and 4. */ - - dimmInfo->burstLengthSupported = data[i]; -#ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); - if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); - if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); - if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); - if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 17: /* Number Of Banks On Each Device */ - dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf - ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 18: /* Suported Cas Latencies */ - - /* DDR: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - ********************************************************* - SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - dimmInfo->suportedCasLatencies = data[i]; -#ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); - if (dimmInfo->memoryType == 0) { /* SDRAM */ - for (k = 0; k <= 7; k++) { - if (dimmInfo-> - suportedCasLatencies & (1 << k)) - DP (printf - ("%d, ", - k + 1)); - } - - } else { /* DDR-RAM */ - - if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); - if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); - if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); - if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); - if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); - if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); - - } - DP (printf ("\n")); -#endif - /* Calculating MAX CAS latency */ - for (j = 7; j > 0; j--) { - if (((dimmInfo-> - suportedCasLatencies >> j) & 0x1) == - 1) { - switch (dimmInfo->memoryType) { - case DDR: - /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ - switch (j) { - case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3_5; - break; - case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3; - break; - case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2_5; - break; - case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2; - break; - case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_1_5; - break; - } - - /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy - lower then our SDRAM cycle count, we won't be able to support this CAL - and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - < - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - < - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - dimmInfo-> - maxClSupported_DDR - = - dimmInfo-> - maxClSupported_DDR - >> 1; - DP (printf - ("*** Change actual Cas Latencies cause of minimumCycleTime n")); - } - /* ronen - checkif the Dimm frequency compared to the Sysclock. */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - > - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - > - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - printf ("*********************************************************\n"); - printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); - printf ("*********************************************************\n"); - hang (); - } - - dimmInfo-> - maxCASlatencySupported_LoP - = - 1 + - (int) (5 * j / 10); - if (((5 * j) % 10) != 0) - dimmInfo-> - maxCASlatencySupported_RoP - = 5; - else - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - DP (printf - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP)); - break; - case SDRAM: - /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ - dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf - ("Max. Cas Latencies (SD): %d\n", - dimmInfo-> - maxClSupported_SD)); - dimmInfo-> - maxCASlatencySupported_LoP - = j; - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - DP (printf - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP)); - break; - } - break; - } - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); - dimmInfo->bufferedAddrAndControlInputs = - data[i] & BIT0; - dimmInfo->registeredAddrAndControlInputs = - (data[i] & BIT1) >> 1; - dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; - dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; - dimmInfo->registeredDQMBinputs = - (data[i] & BIT4) >> 4; - dimmInfo->differentialClockInput = - (data[i] & BIT5) >> 5; - dimmInfo->redundantRowAddressing = - (data[i] & BIT6) >> 6; -#ifdef DEBUG - if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); - else - DP (printf - (" - Buffered Address/Control Input: No \n")); - - if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); - else - DP (printf - (" - Registered Address/Control Input: No \n")); - - if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); - else - DP (printf - (" - On-Card PLL (clock): No \n")); - - if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); - else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); - - if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); - else - DP (printf - (" - Registered DQMB Inputs: No \n")); - - if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); - else - DP (printf - (" - Differential Clock Input: No \n")); - - if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); - else - DP (printf - (" - redundant Row Addressing: No \n")); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); - dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; - dimmInfo->suportedAutoPreCharge = - (data[i] & BIT1) >> 1; - dimmInfo->suportedPreChargeAll = - (data[i] & BIT2) >> 2; - dimmInfo->suportedWrite1ReadBurst = - (data[i] & BIT3) >> 3; - dimmInfo->suported5PercentLowVCC = - (data[i] & BIT4) >> 4; - dimmInfo->suported5PercentUpperVCC = - (data[i] & BIT5) >> 5; -#ifdef DEBUG - if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); - else - DP (printf - (" - Early Ras Precharge: No \n")); - - if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); - else - DP (printf - (" - AutoPreCharge: No \n")); - - if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); - else - DP (printf - (" - Precharge All: No \n")); - - if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); - else - DP (printf - (" - Write 1/ReadBurst: No \n")); - - if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); - else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); - - if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); - else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = - rightOfPoint; - DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = - rightOfPoint; - DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 27: /* Minimum Row Precharge Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ - trp_clocks = - (dimmInfo->minRowPrechargeTime + - (tmemclk - 1)) / tmemclk; - DP (printf - ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf - ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 28: /* Minimum Row Active to Row Active Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 29: /* Minimum Ras-To-Cas Delay */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 30: /* Minimum Ras Pulse Width */ - dimmInfo->minRasPulseWidth = data[i]; - tras_clocks = - (NSto10PS (data[i]) + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 31: /* Module Bank Density */ - dimmInfo->moduleBankDensity = data[i]; - DP (printf - ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); -#ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); - { - if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); - if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); - if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); - if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); - if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); - if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); - if ((dimmInfo->moduleBankDensity & 64) - || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); - hang (); - } - } - DP (printf ("\n")); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 32: /* Address And Command Setup Time (measured in ns/1000) */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 33: /* Address And Command Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 34: /* Data Input Setup Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 35: /* Data Input Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - } - } - /* calculating the sdram density */ - for (i = 0; - i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; - i++) { - density = density * 2; - } - dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * - dimmInfo->sdramWidth; - dimmInfo->numberOfDevices = - (dimmInfo->dataWidth / dimmInfo->sdramWidth) * - dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; - if ((dimmInfo->errorCheckType == 0x1) - || (dimmInfo->errorCheckType == 0x2) - || (dimmInfo->errorCheckType == 0x3)) { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - (dimmInfo->numberOfDevices - - /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */ - dimmInfo->numberOfDevices / 8); - } else { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - dimmInfo->numberOfDevices; - } - - /* compute the module DRB size */ - tmp = (1 << - (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); - tmp *= dimmInfo->numOfModuleBanks; - tmp *= dimmInfo->sdramWidth; - tmp = tmp >> 24; /* div by 0x4000000 (64M) */ - dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); - - /* try a CAS latency of 3 first... */ - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1; - - cal_val = 0; - if (supp_cal & 3) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 3; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 2; - } - - DP (printf ("cal_val = %d\n", cal_val)); - - /* bummer, did't work... */ - if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); - hang (); - return 0; - } - - return true; - -#endif -} - -/* sets up the GT properly with information passed in */ -int setup_sdram (AUX_MEM_DIMM_INFO * info) -{ - ulong tmp, check; - ulong tmp_sdram_mode = 0; /* 0x141c */ - ulong tmp_dunit_control_low = 0; /* 0x1404 */ - int i; - - /* added 8/21/2003 P. Marchese */ - unsigned int sdram_config_reg; - - /* added 10/10/2003 P. Marchese */ - ulong sdram_chip_size; - - /* sanity checking */ - if (!info->numOfModuleBanks) { - printf ("setup_sdram called with 0 banks\n"); - return 1; - } - - /* delay line */ - set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); - - /* set SDRAM mode NOP */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); - } - - /* SDRAM configuration */ -/* added 8/21/2003 P. Marchese */ -/* code allows usage of registered DIMMS */ - - /* figure out the memory refresh internal */ - switch (info->RefreshInterval) { - case 0x0: - case 0x80: /* refresh period is 15.625 usec */ - sdram_config_reg = - (unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ) - / (float) 1000000.0); - break; - case 0x1: - case 0x81: /* refresh period is 3.9 usec */ - sdram_config_reg = - (unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) / - (float) 1000000.0); - break; - case 0x2: - case 0x82: /* refresh period is 7.8 usec */ - sdram_config_reg = - (unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) / - (float) 1000000.0); - break; - case 0x3: - case 0x83: /* refresh period is 31.3 usec */ - sdram_config_reg = - (unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) / - (float) 1000000.0); - break; - case 0x4: - case 0x84: /* refresh period is 62.5 usec */ - sdram_config_reg = - (unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) / - (float) 1000000.0); - break; - case 0x5: - case 0x85: /* refresh period is 125 usec */ - sdram_config_reg = - (unsigned int) (((float) 125 * (float) CFG_BUS_HZ) / - (float) 1000000.0); - break; - default: /* refresh period undefined */ - printf ("DRAM refresh period is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - DP (printf ("calculated refresh interval %0x\n", sdram_config_reg)); - - /* make sure the refresh value is only 14 bits */ - if (sdram_config_reg > 0x1fff) - sdram_config_reg = 0x1fff; - DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg)); - - /* we want physical bank interleaving and */ - /* virtual bank interleaving enabled so do nothing */ - /* since these bits need to be zero to enable the interleaving */ - - /* registered DRAM ? */ - if (info->registeredAddrAndControlInputs == 1) { - /* it's registered DRAM, so set the reg. DRAM bit */ - sdram_config_reg = sdram_config_reg | BIT17; - DP (printf ("Enabling registered DRAM bit\n")); - } - /* turn on DRAM ECC? */ -#ifdef CONFIG_MV64360_ECC - if (info->errorCheckType == 0x2) { - /* DRAM has ECC, so turn it on */ - sdram_config_reg = sdram_config_reg | BIT18; - DP (printf ("Enabling ECC\n")); - } -#endif - /* set the data DQS pin configuration */ - switch (info->sdramWidth) { - case 0x4: /* memory is x4 */ - sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - DP (printf ("Data DQS pins set for 16 pins\n")); - break; - case 0x8: /* memory is x8 or x16 */ - case 0x10: - sdram_config_reg = sdram_config_reg | BIT21; - DP (printf ("Data DQS pins set for 8 pins\n")); - break; - case 0x20: /* memory is x32 */ - /* both bits are cleared for x32 so nothing to do */ - DP (printf ("Data DQS pins set for 2 pins\n")); - break; - default: /* memory width unsupported */ - printf ("DRAM chip width is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - - /* perform read buffer assignments */ - /* we are going to use the Power-up defaults */ - /* bit 26 = CPU = buffer 1 */ - /* bit 27 = PCI bus #0 = buffer 0 */ - /* bit 28 = PCI bus #1 = buffer 0 */ - /* bit 29 = MPSC = buffer 0 */ - /* bit 30 = IDMA = buffer 0 */ - /* bit 31 = Gigabit = buffer 0 */ - sdram_config_reg = sdram_config_reg | BIT26; - /* sdram_config_reg = sdram_config_reg | 0x58000000; */ - /* sdram_config_reg = sdram_config_reg & 0xffffff00; */ - - /* write the value into the SDRAM configuration register */ - GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - DP (printf - ("OOOOOOOOO sdram_conf 0x1400: %08x\n", - GTREGREAD (SDRAM_CONFIG))); - - /* SDRAM open pages control keep open as much as I can */ - GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf - ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); - else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); - - /* SDRAM set CAS Latency according to SPD information */ - switch (info->memoryType) { - case SDRAM: - printf ("### SD-RAM not supported !!!\n"); - printf ("Aborting!!!\n"); - hang (); - /* ToDo fill SD-RAM if needed !!!!! */ - break; - /* Calculate the settings for SDRAM mode and Dunit control low registers */ - /* Values set according to technical bulletin TB-92 rev. c */ - case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); - switch (info->maxClSupported_DDR) { - case DDR_CL_3: - tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x05110051; - else - tmp_dunit_control_low = 0x24110051; - DP (printf - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x2C1107F2; - else - tmp_dunit_control_low = 0x3C1107d2; - DP (printf - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } - break; - case DDR_CL_2_5: - tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x25110051; - else - tmp_dunit_control_low = 0x24110051; - DP (printf - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - printf ("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); - printf ("Aborting!!!\n"); - hang (); - } else - tmp_dunit_control_low = 0x1B1107d2; - DP (printf - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } - break; - case DDR_CL_2: - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x04110051; - else - tmp_dunit_control_low = 0x03110051; - DP (printf - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - printf ("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); - printf ("Aborting!!!\n"); - hang (); - } else - tmp_dunit_control_low = 0x3B1107d2; - DP (printf - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } - break; - case DDR_CL_1_5: - tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x24110051; - else - tmp_dunit_control_low = 0x23110051; - DP (printf - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - printf ("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); - printf ("Aborting!!!\n"); - hang (); - } else - tmp_dunit_control_low = 0x1A1107d2; - DP (printf - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } - break; - - default: - printf ("Max. CL is out of range %d\n", - info->maxClSupported_DDR); - hang (); - break; - } /* end DDR switch */ - break; - } /* end CL switch */ - - /* Write results of CL detection procedure */ - /* set SDRAM mode reg. 0x141c */ - GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); - } - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); - } - -/*------------------------------------------------------------------------------ */ - - /* bank parameters */ - /* SDRAM address decode register 0x1410 */ - /* program this with the default value */ - tmp = 0x02; /* power-up default address select decoding value */ - - DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); -/* figure out the DRAM chip size */ - sdram_chip_size = - (1 << (info->numOfRowAddresses + info->numOfColAddresses)); - sdram_chip_size *= info->sdramWidth; - sdram_chip_size *= 4; - DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size)); - /* divide sdram chip size by 64 Mbits */ - sdram_chip_size = sdram_chip_size / 0x4000000; - switch (sdram_chip_size) { - case 1: /* 64 Mbit */ - case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); - tmp |= (0x00 << 4); - break; - case 4: /* 256 Mbit */ - case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); - tmp |= (0x01 << 4); - break; - case 16: /* 1 Gbit */ - case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); - tmp |= (0x02 << 4); - break; - default: - printf ("Error in dram size calculation\n"); - printf ("RAM-Device_size is unsupported\n"); - hang (); - } - - /* SDRAM address control */ - GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - DP (printf - ("setting up sdram address control (0x1410) with: %08lx \n", - tmp)); - -/* ------------------------------------------------------------------------------ */ -/* same settings for registerd & non-registerd DDR SDRAM */ - DP (printf - ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x11511220)); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); - - -/* ------------------------------------------------------------------------------ */ - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIG); - - if (info->registeredAddrAndControlInputs - || info->registeredDQMBinputs) { - tmp |= (1 << 17); - DP (printf - ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", - info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); - } - - /* Use buffer 1 to return read data to the CPU - * Page 426 MV64360 */ - tmp |= (1 << 26); - DP (printf - ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf - ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); - - /* SDRAM timing To_do: */ -/* ------------------------------------------------------------------------------ */ - - DP (printf - ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0x9)); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9); - - DP (printf - ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a)); - GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - - DP (printf - indent: Standard input:1450: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". Assuming "= *" - - ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a)); - GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); - -/* ------------------------------------------------------------------------------ */ - - /* set the SDRAM configuration for each bank */ - -/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ - { - i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); - - /* set SDRAM mode */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - check = GTREGREAD (SDRAM_OPERATION); - DP (printf - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); - - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION, 0); - check = GTREGREAD (SDRAM_OPERATION); - DP (printf - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); - - /* unmap the bank */ - memory_map_bank (i, 0, 0); - } - - return 0; - -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -long int dram_size (long int *base, long int maxsize) -{ - volatile long int *addr, *b = base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); - cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr = cnt; /* write cnt to addr */ - *b = 0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr = save1; /* restore *addr */ - *b = save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - val = *addr; /* read *addr */ - - *addr = save1; - *b = save2; - - if (val != cnt) { - DP (printf - ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr)); - /* fix boundary condition.. STARTVAL means zero */ - if (cnt == STARTVAL / sizeof (long)) - cnt = 0; - return (cnt * sizeof (long)); - } - } - return maxsize; -} - -/* ------------------------------------------------------------------------- */ - -/* ppcboot interface function to SDRAM init - this is where all the - * controlling logic happens */ -long int initdram (int board_type) -{ - int s0 = 0, s1 = 0; - int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total, check; - AUX_MEM_DIMM_INFO dimmInfo1; - AUX_MEM_DIMM_INFO dimmInfo2; - int nhr, bank_no; - ulong dest, memSpaceAttr; - - /* first, use the SPD to get info about the SDRAM/ DDRRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0 () & (1 << 16); - - if (nhr) { - printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - s0 = check_dimm (0, &dimmInfo1); - - /* DIMM1 */ - s1 = check_dimm (1, &dimmInfo2); - - memory_map_bank (0, 0, 0); - memory_map_bank (1, 0, 0); - memory_map_bank (2, 0, 0); - memory_map_bank (3, 0, 0); - - /* ronen check correct set of DIMMS */ - if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) { - if (dimmInfo1.errorCheckType != - dimmInfo2.errorCheckType) - printf ("***WARNNING***!!!! different ECC support of the DIMMS\n"); - if (dimmInfo1.maxClSupported_DDR != - dimmInfo2.maxClSupported_DDR) - printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n"); - if (dimmInfo1.registeredAddrAndControlInputs != - dimmInfo2.registeredAddrAndControlInputs) - printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n"); - } - - if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) { - printf ("Setup for DIMM1 failed.\n"); - } - - if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) { - printf ("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0 (get_hid0 () | (1 << 16)); - } - /* next, size the SDRAM banks */ - - realsize = total = 0; - check = GB / 4; - if (dimmInfo1.numOfModuleBanks > 0) { - checkbank[0] = 1; - } - if (dimmInfo1.numOfModuleBanks > 1) { - checkbank[1] = 1; - } - if (dimmInfo1.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM1 has >2 banks\n"); - - printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks); - - if (dimmInfo2.numOfModuleBanks > 0) { - checkbank[2] = 1; - } - if (dimmInfo2.numOfModuleBanks > 1) { - checkbank[3] = 1; - } - if (dimmInfo2.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM2 has >2 banks\n"); - - printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); - - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (!checkbank[bank_no]) - continue; - - /* ronen - realsize = dram_size((long int *)total, check); */ - if (bank_no == 0 || bank_no == 1) { - if (checkbank[1] == 1) - realsize = dimmInfo1.size / 2; - else - realsize = dimmInfo1.size; - } - if (bank_no == 2 || bank_no == 3) { - if (checkbank[3] == 1) - realsize = dimmInfo2.size / 2; - else - realsize = dimmInfo2.size; - } - memory_map_bank (bank_no, total, realsize); - - /* ronen - initialize the DRAM for ECC */ -#ifdef CONFIG_MV64360_ECC - if ((dimmInfo1.errorCheckType != 0) && - ((dimmInfo2.errorCheckType != 0) - || (dimmInfo2.numOfModuleBanks == 0))) { - printf ("ECC Initialization of Bank %d:", bank_no); - memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8; - mvDmaSetMemorySpace (0, 0, memSpaceAttr, total, - realsize); - for (dest = total; dest < total + realsize; - dest += _8M) { - mvDmaTransfer (0, total, dest, _8M, - BIT8 /*DMA_DTL_128BYTES */ | - BIT3 /*DMA_HOLD_SOURCE_ADDR */ - | - BIT11 - /*DMA_BLOCK_TRANSFER_MODE */ ); - while (mvDmaIsChannelActive (0)); - } - printf (" PASS\n"); - } -#endif - - total += realsize; - } - - /* ronen- add DRAM conf prints */ - switch ((GTREGREAD (0x141c) >> 4) & 0x7) { - case 0x2: - printf ("CAS Latency = 2"); - break; - case 0x3: - printf ("CAS Latency = 3"); - break; - case 0x5: - printf ("CAS Latency = 1.5"); - break; - case 0x6: - printf ("CAS Latency = 2.5"); - break; - } - printf (" tRP = %d tRAS = %d tRCD=%d\n", - ((GTREGREAD (0x1408) >> 8) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 20) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 4) & 0xf) + 1); - -/* Setup Ethernet DMA Adress window to DRAM Area */ - if (total > _256M) - printf ("*** ONLY the first 256MB DRAM memory are used out of the "); - else - printf ("Total SDRAM memory is "); - /* (cause all the 4 BATS are taken) */ - return (total); -} - - -/* ronen- add Idma functions for usage of the ecc dram init. */ -/******************************************************************************* -* mvDmaIsChannelActive - Checks if a engine is busy. -********************************************************************************/ -int mvDmaIsChannelActive (int engine) -{ - ulong data; - - data = GTREGREAD (MV64360_DMA_CHANNEL0_CONTROL + 4 * engine); - if (data & BIT14 /*activity status */ ) { - return 1; - } - return 0; -} - -/******************************************************************************* -* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding -* map. -*******************************************************************************/ -int mvDmaSetMemorySpace (ulong memSpace, - ulong memSpaceTarget, - ulong memSpaceAttr, ulong baseAddress, ulong size) -{ - ulong temp; - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return 0; - } - if (size >= 0x10000 /*64K */ ) { - size &= 0xffff0000; - baseAddress = (baseAddress & 0xffff0000); - /* Set the new attributes */ - GT_REG_WRITE (MV64360_DMA_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64360_DMA_SIZE_REG0 + memSpace * 8), - (size - 1) & 0xffff0000); - temp = GTREGREAD (MV64360_DMA_BASE_ADDR_ENABLE_REG); - GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, - (temp & ~(BIT0 << memSpace))); - return 1; - } - return 0; -} - - -/******************************************************************************* -* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4 -* DMA channels. -********************************************************************************/ -int mvDmaTransfer (int engine, ulong sourceAddr, - ulong destAddr, ulong numOfBytes, ulong command) -{ - ulong engOffReg = 0; /* Engine Offset Register */ - - if (numOfBytes > 0xffff) { - command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ; - } - command = command | ((command >> 6) & 0x7); - engOffReg = engine * 4; - GT_REG_WRITE (MV64360_DMA_CHANNEL0_BYTE_COUNT + engOffReg, - numOfBytes); - GT_REG_WRITE (MV64360_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, - sourceAddr); - GT_REG_WRITE (MV64360_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, - destAddr); - command = - command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9 - /*DMA_NON_CHAIN_MODE */ ; - /* Activate DMA engine By writting to mvDmaControlRegister */ - GT_REG_WRITE (MV64360_DMA_CHANNEL0_CONTROL + engOffReg, command); - return 1; -} - -/**************************************************************************************** - * SDRAM INIT * - * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * - * This procedure fits only the Atlantis * - * * - ***************************************************************************************/ - - -/**************************************************************************************** - * DFCDL initialize MV643xx Design Considerations * - * * - ***************************************************************************************/ -int set_dfcdlInit (void) -{ - int i; - unsigned int dfcdl_word = 0x391; /* 0x14f; ronen new dfcdl */ - - for (i = 0; i < 64; i++) { - GT_REG_WRITE (SRAM_DATA0, dfcdl_word); -/* dfcdl_word += 0x41; - ronen new dfcdl */ - } - GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ - - return (0); -} diff --git a/board/Marvell/db64360/u-boot.lds b/board/Marvell/db64360/u-boot.lds deleted file mode 100644 index d89eb6c..0000000 --- a/board/Marvell/db64360/u-boot.lds +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/74xx_7xx/start.o (.text) - -/* store the environment in a seperate sector in the boot flash */ -/* . = env_offset; */ -/* common/environment.o(.text) */ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/Marvell/db64460/64460.h b/board/Marvell/db64460/64460.h deleted file mode 100644 index 8bb0ebf..0000000 --- a/board/Marvell/db64460/64460.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * main board support/init for the Galileo Eval board DB64460. - */ - -#ifndef __64460_H__ -#define __64460_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_SINGLE_CPU (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64460_H__ */ diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile deleted file mode 100644 index 768ccdd..0000000 --- a/board/Marvell/db64460/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -SOBJS = ../common/misc.o - -OBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ - mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ - sdram_init.o ../common/intel_flash.o - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/Marvell/db64460/config.mk b/board/Marvell/db64460/config.mk deleted file mode 100644 index 5a434d9..0000000 --- a/board/Marvell/db64460/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# EVB64460 boards -# - -TEXT_BASE = 0xfff00000 diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c deleted file mode 100644 index a4abf8d..0000000 --- a/board/Marvell/db64460/db64460.c +++ /dev/null @@ -1,936 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com - */ - -/* - * db64460.c - main board support/init for the Galileo Eval board. - */ - -#include -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64460.h" -#include "mv_regs.h" - -#undef DEBUG -/*#define DEBUG */ - -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -extern void flush_data_cache (void); -extern void invalidate_l1_instruction_cache (void); - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; -int display_mem_map (void); - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void my_remap_gt_regs (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - -/* original ppcboot 1.1.6 source - - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -original ppcboot 1.1.6 source end */ - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); -} - -#ifdef CONFIG_PCI - -static void gt_pci_config (void) -{ - unsigned int stat; - unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ - - /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's - * config registers by writing ones to the bus and device. - * We then update the Virtual register with the correct value for the bus and device. - */ - if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - - GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); - - } - if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); - } - - /* Enable master */ - PCI_MASTER_ENABLE (0, SELF); - PCI_MASTER_ENABLE (1, SELF); - - /* Enable PCI0/1 Mem0 and IO 0 disable all others */ - GT_REG_READ (BASE_ADDR_ENABLE, &stat); - stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 - << - 18); - stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); - GT_REG_WRITE (BASE_ADDR_ENABLE, stat); - - /* ronen- add write to pci remap registers for 64460. - in 64360 when writing to pci base go and overide remap automaticaly, - in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); - - /* PCI interface settings */ - /* Timeout set to retry forever */ - GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); - GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); - - /* ronen - enable only CS0 and Internal reg!! */ - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - -/*ronen update the pci internal registers base address.*/ -#ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) - pciWriteConfigReg (stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CFG_GT_REGS); -#endif - -} -#endif - -/* Setup CPU interface paramaters */ -static void gt_cpu_config (void) -{ - cpu_t cpu = get_cpu_type (); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD (CPU_CONFIGURATION); - - /* set the SINGLE_CPU bit see MV64460 P.399 */ -#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ - tmp |= CPU_CONF_SINGLE_CPU; -#endif - - tmp &= ~CPU_CONF_AACK_DELAY_2; - - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - - tmp |= CPU_CONF_PIPELINE; - - GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ - - /* CPU master control register */ - tmp = GTREGREAD (CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command (603e, 750) - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - uchar sram_boot = 0; - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); - - /* No PCI in first release of Port To_do: enable it. */ -#ifdef CONFIG_PCI - gt_pci_config (); -#endif - /* mask all external interrupt sources */ - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - /* new in MV6446x */ - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); - /* --------------------- */ - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - /* does not exist in MV6446x - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - --------------------- */ - - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM ???? - * 1 - RTC ???? - * 2 - UART ???? - * 3 - Flash checked 32Bit Intel Strata - * boot - BootCS checked 8Bit 29LV040B - * - * Zuma - * 0 - Flash - * boot - BootCS - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) - sram_boot = 1; - if (!sram_boot) - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - - memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); - - - /* configure device timing */ -#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */ - if (!sram_boot) - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); -#endif - -#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */ - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); -#endif -#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */ - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); -#endif - -#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CFG_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ -#endif - - - gt_cpu_config (); - - /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); - - GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); - DEBUG_LED0_ON (); - DEBUG_LED1_ON (); - DEBUG_LED2_ON (); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r () -{ - icache_enable (); -#ifdef CFG_L2 - l2cache_enable (); -#endif -#ifdef CONFIG_MPSC - - mpsc_sdma_init (); - mpsc_init2 (); -#endif - -#if 0 - /* disable the dcache and MMU */ - dcache_lock (); -#endif - return 0; -} - -void after_reloc (ulong dest_addr, gd_t * gd) -{ - /* check to see if we booted from the sram. If so, move things - * back to the way they should be. (we're running from main - * memory at this point now */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) { - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M); - } - display_mem_map (); - /* now, jump to the main ppcboot board init code */ - board_init_r (gd, dest_addr); - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * right now, assume borad type. (there is just one...after all) - */ - -int checkboard (void) -{ - int l_type = 0; - - printf ("BOARD: %s\n", CFG_BOARD_NAME); - return (l_type); -} - -/* utility functions */ -void debug_led (int led, int mode) -{ - volatile int *addr = 0; - int dummy; - - if (mode == 1) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x08000); - break; - - case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x0c000); - break; - - case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x10000); - break; - } - } else if (mode == 0) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x14000); - break; - - case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x18000); - break; - - case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | - 0x1c000); - break; - } - } - - dummy = *addr; -} - -int display_mem_map (void) -{ - int i, j; - unsigned int base, size, width; - - /* SDRAM */ - printf ("SD (DDR) RAM\n"); - for (i = 0; i <= BANK3; i++) { - base = memoryGetBankBaseAddress (i); - size = memoryGetBankSize (i); - if (size != 0) { - printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", - i, base, size >> 20); - } - } - - /* CPU's PCI windows */ - for (i = 0; i <= PCI_HOST1; i++) { - printf ("\nCPU's PCI %d windows\n", i); - base = pciGetSpaceBase (i, PCI_IO); - size = pciGetSpaceSize (i, PCI_IO); - printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, - size >> 20); - for (j = 0; - j <= - PCI_REGION0 - /*ronen currently only first PCI MEM is used 3 */ ; - j++) { - base = pciGetSpaceBase (i, j); - size = pciGetSpaceSize (i, j); - printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); - } - } - - /* Devices */ - printf ("\nDEVICES\n"); - for (i = 0; i <= DEVICE3; i++) { - base = memoryGetDeviceBaseAddress (i); - size = memoryGetDeviceSize (i); - width = memoryGetDeviceWidth (i) * 8; - printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); - if (i == 0) - printf ("\t- EXT SRAM (actual - 1M)\n"); - else if (i == 1) - printf ("\t- RTC\n"); - else if (i == 2) - printf ("\t- UART\n"); - else - printf ("\t- LARGE FLASH\n"); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize (BOOT_DEVICE); - width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; - printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n", - base, size >> 20, width); - return (0); -} - -/* DRAM check routines copied from gw8260 */ - -#if defined (CFG_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CFG_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CFG_DRAM_TEST_DATA */ - -#if defined (CFG_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CFG_DRAM_TEST_ADDRESS */ - -#if defined (CFG_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CFG_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - char *s; - int rundata, runaddress, runwalk; - - s = getenv ("testdramdata"); - rundata = (s && (*s == 'y')) ? 1 : 0; - s = getenv ("testdramaddress"); - runaddress = (s && (*s == 'y')) ? 1 : 0; - s = getenv ("testdramwalk"); - runwalk = (s && (*s == 'y')) ? 1 : 0; - -/* rundata = 1; */ -/* runaddress = 0; */ -/* runwalk = 0; */ - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); - } -#ifdef CFG_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CFG_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CFG_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed\n"); - } - return 0; - -} -#endif /* CFG_DRAM_TEST */ - -/* ronen - the below functions are used by the bootm function */ -/* - we map the base register to fbe00000 (same mapping as in the LSP) */ -/* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ -void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | - new_loc | - (INTERNAL_SPACE_DECODE))))) - != temp); - -} - -void board_prebootm_init () -{ - -/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ - GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); - -/* Stop GigE Rx DMA engines */ - GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); - GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); - GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); - -/* Relocate MV64460 internal regs */ - my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM); - - icache_disable (); - invalidate_l1_instruction_cache (); - flush_data_cache (); - dcache_disable (); -} diff --git a/board/Marvell/db64460/eth.h b/board/Marvell/db64460/eth.h deleted file mode 100644 index 6c3b2e0..0000000 --- a/board/Marvell/db64460/eth.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __EVB64460_ETH_H__ -#define __EVB64460_ETH_H__ - -#include -#include -#include -#include - -int db64460_eth0_poll(void); -int db64460_eth0_transmit(unsigned int s, volatile char *p); -void db64460_eth0_disable(void); -bool network_start(bd_t *bis); - -#endif /* __EVB64460_ETH_H__ */ diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c deleted file mode 100644 index 33fbc49..0000000 --- a/board/Marvell/db64460/mpsc.c +++ /dev/null @@ -1,1019 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************* - * changes for Marvell DB64460 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - -/* - * mpsc.c - driver for console over the MPSC. - */ - - -#include -#include -#include - -#include -#include "mpsc.h" - -#include "mv_regs.h" - -#include "../include/memory.h" - -/* Define this if you wish to use the MPSC as a register based UART. - * This will force the serial port to not use the SDMA engine at all. - */ -#undef CONFIG_MPSC_DEBUG_PORT - - -int (*mpsc_putchar) (char ch) = mpsc_putchar_early; -char (*mpsc_getchar) (void) = mpsc_getchar_debug; -int (*mpsc_test_char) (void) = mpsc_test_char_debug; - - -static volatile unsigned int *rx_desc_base = NULL; -static unsigned int rx_desc_index = 0; -static volatile unsigned int *tx_desc_base = NULL; -static unsigned int tx_desc_index = 0; - -/* local function declarations */ -static int galmpsc_connect (int channel, int connect); -static int galmpsc_route_rx_clock (int channel, int brg); -static int galmpsc_route_tx_clock (int channel, int brg); -static int galmpsc_write_config_regs (int mpsc, int mode); -static int galmpsc_config_channel_regs (int mpsc); -static int galmpsc_set_char_length (int mpsc, int value); -static int galmpsc_set_stop_bit_length (int mpsc, int value); -static int galmpsc_set_parity (int mpsc, int value); -static int galmpsc_enter_hunt (int mpsc); -static int galmpsc_set_brkcnt (int mpsc, int value); -static int galmpsc_set_tcschar (int mpsc, int value); -static int galmpsc_set_snoop (int mpsc, int value); -static int galmpsc_shutdown (int mpsc); - -static int galsdma_set_RFT (int channel); -static int galsdma_set_SFM (int channel); -static int galsdma_set_rxle (int channel); -static int galsdma_set_txle (int channel); -static int galsdma_set_burstsize (int channel, unsigned int value); -static int galsdma_set_RC (int channel, unsigned int value); - -static int galbrg_set_CDV (int channel, int value); -static int galbrg_enable (int channel); -static int galbrg_disable (int channel); -static int galbrg_set_clksrc (int channel, int value); -static int galbrg_set_CUV (int channel, int value); - -static void galsdma_enable_rx (void); -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, - unsigned int size); - - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - -#ifdef CONFIG_MPSC_DEBUG_PORT -static void mpsc_debug_init (void) -{ - - volatile unsigned int temp; - - /* Clear the CFR (CHR4) */ - /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&". Assuming "= &" - -REG_GAP)); - temp &= 0xffffff00; - temp |= BIT29; - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); - temp |= (BIT12 | BIT15); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set int mask */ - temp = GTREGREAD (GALMPSC_0_INT_MASK); - temp |= BIT6; - GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); -} -#endif - -char mpsc_getchar_debug (void) -{ - volatile int temp; - volatile unsigned int cause; - - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - while ((cause & BIT6) == 0) { - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - } - - temp = GTREGREAD (GALMPSC_CHANNELREG_10 + - (CHANNEL * GALMPSC_REG_GAP)); - /* By writing 1's to the set bits, the register is cleared */ - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), - temp); - GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); - return (temp >> 16) & 0xff; -} - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int mpsc_putchar_early (char ch) -{ - DECLARE_GLOBAL_DATA_PTR; - int mpsc = CHANNEL; - int temp = - GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - galmpsc_set_tcschar (mpsc, ch); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), - temp | 0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay (MAGIC_FACTOR / gd->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int mpsc_putchar_sdma (char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset ((void *) p, 0, 8 * sizeof (unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int) ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int) &p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int) &p[0]; - p[11] = (unsigned int) &p[12]; -#endif - - FLUSH_DCACHE (&p[0], &p[8]); - - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE (&p[1], &p[2]); - - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[1], &p[2]); - } - return 0; -} - -char mpsc_getchar_sdma (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP)); - temp |= (1 << 23); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP), temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - - -int mpsc_test_char_debug (void) -{ - if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) - return 0; - else { - return 1; - } -} - - -int mpsc_test_char_sdma (void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[1], &p[2]); - - if (p[1] & DESC_OWNER_BIT) - return 0; - else - return 1; -} - -int mpsc_init (int baud) -{ - /* BRG CONFIG */ - galbrg_set_baudrate (CHANNEL, baud); - galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ - galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ - galbrg_enable (CHANNEL); /* Enable BRG */ - - /* Set up clock routing */ - galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ - - galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ - galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ - - /* reset MPSC state */ - galmpsc_shutdown (CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle (CHANNEL); - galsdma_set_rxle (CHANNEL); - galsdma_set_RC (CHANNEL, 0xf); - galsdma_set_SFM (CHANNEL); - galsdma_set_RFT (CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs (CHANNEL); - galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - -#ifdef CONFIG_MPSC_DEBUG_PORT - mpsc_debug_init (); -#endif - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - - -void mpsc_sdma_init (void) -{ -/* Setup SDMA channel0 SDMA_CONFIG_REG*/ - GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); - -/* Enable MPSC-Window0 for DRAM Bank0 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_0_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK0)) != true) - printf ("%s: SDMA_Window0 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window1 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_1_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window1 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window2 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_2_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window2 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window3 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_3_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window3 memory setup failed !!! \n", - __FUNCTION__); - -/* Setup MPSC0 access mode Window0 full access */ - GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, - (MV64460_SDMA_WIN_ACCESS_FULL << - (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC1 access mode Window1 full access */ - GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, - (MV64460_SDMA_WIN_ACCESS_FULL << - (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); - -/* no high address remap*/ - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); - -/* clear interrupt cause register for MPSC (fault register)*/ - GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); -} - - -void mpsc_init2 (void) -{ - int i; - -#ifndef CONFIG_MPSC_DEBUG_PORT - mpsc_putchar = mpsc_putchar_sdma; - mpsc_getchar = mpsc_getchar_sdma; - mpsc_test_char = mpsc_test_char_sdma; -#endif - /* RX descriptors */ - rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset ((void *) rx_desc_base, 0, - (RX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ - rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ - rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i * 8] = 0x00100000; - } - rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; - - FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset ((void *) tx_desc_base, 0, - (TX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 3] = - (unsigned int) &tx_desc_base[i * 8 + 4]; - tx_desc_base[i * 8 + 2] = - (unsigned int) &tx_desc_base[(i + 1) * 8]; - tx_desc_base[i * 8 + 1] = - DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i * 8] = 0x00010001; - } - tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; - - FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); - - udelay (100); - - galsdma_enable_rx (); - - return; -} - -int galbrg_set_baudrate (int channel, int rate) -{ - DECLARE_GLOBAL_DATA_PTR; - int clock; - - galbrg_disable (channel); /*ok */ - -#ifdef ZUMA_NTL - /* from tclk */ - clock = (CFG_TCLK / (16 * rate)) - 1; -#else - clock = (CFG_TCLK / (16 * rate)) - 1; -#endif - - galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ - - galbrg_enable (channel); - - gd->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int galbrg_set_CDV (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_enable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x00010000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_disable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFEFFFF; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_set_clksrc (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ - temp |= (value << 18); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - return 0; -} - -static int galbrg_set_CUV (int channel, int value) -{ - /* set CountUpValue */ - GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int galbrg_reset (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int galsdma_set_RFT (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_SFM (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_rxle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_txle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_RC (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_burstsize (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int galmpsc_connect (int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int galmpsc_route_rx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_RxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_route_tx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_TxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_write_config_regs (int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int galmpsc_config_channel_regs (int mpsc) -{ - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt (mpsc, 0x3); - galmpsc_set_tcschar (mpsc, 0xab); - - return 0; -} - -static int galmpsc_set_brkcnt (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_tcschar (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_char_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_stop_bit_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFBFFF; - temp |= (value << 14); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_parity (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_enter_hunt (int mpsc) -{ - int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= 0x80000000; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & - MPSC_ENTER_HUNT) { - udelay (1); - } - return 0; -} - - -static int galmpsc_shutdown (int mpsc) -{ - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - GT_REG_WRITE (GALSDMA_0_COM_REG, 0); - GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); - - udelay (100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); - - udelay (100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); - - udelay (100); - - return 0; -} - -static void galsdma_enable_rx (void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt (CHANNEL); -} - -static int galmpsc_set_snoop (int mpsc, int value) -{ - int reg = - mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : - MPSC_0_ADDRESS_CONTROL_LOW; - int temp = GTREGREAD (reg); - - if (value) - temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); - else - temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); - GT_REG_WRITE (reg, temp); - return 0; -} - -/******************************************************************************* -* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map. -* -* DESCRIPTION: -* the MV64460 SDMA has its own address decoding map that is de-coupled -* from the CPU interface address decoding windows. The SDMA channels -* share four address windows. Each region can be individually configured -* by this function by associating it to a target interface and setting -* base and size values. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* The size must be a series of 1s followed by a series of zeros -* -* OUTPUT: -* None. -* -* RETURN: -* True for success, false otherwise. -* -*******************************************************************************/ - -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, unsigned int size) -{ - unsigned int temp; - - if (size == 0) { - GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - return true; - } - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size < 0x10000) { - return false; - } - - /* Align size and base to 64K */ - baseAddress &= 0xffff0000; - size &= 0xffff0000; - temp = size >> 16; - - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - while ((temp > 0) && (temp & 0x1)) { - temp = temp >> 1; - } - - if (temp != 0) { - GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8), - (size - 1) & 0xffff0000); - GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - } else { - /* An invalid size was specified */ - return false; - } - return true; -} diff --git a/board/Marvell/db64460/mpsc.h b/board/Marvell/db64460/mpsc.h deleted file mode 100644 index 3cc0c0f..0000000 --- a/board/Marvell/db64460/mpsc.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************* - * changes for Marvell DB64460 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include "../include/mv_gen_reg.h" - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_sdma_init(void); -void mpsc_init2(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -char mpsc_getchar_debug(void); -int mpsc_test_char_debug(void); - -int mpsc_test_char_sdma(void); - -extern int (*mpsc_putchar)(char ch); -extern char (*mpsc_getchar)(void); -extern int (*mpsc_test_char)(void); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER_BIT 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ -#define GALMPSC_0_INT_CAUSE 0xb804 -#define GALMPSC_0_INT_MASK 0xb884 - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c deleted file mode 100644 index ec5d581..0000000 --- a/board/Marvell/db64460/mv_eth.c +++ /dev/null @@ -1,3182 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mv_eth.c - header file for the polled mode GT ethernet driver - */ -#include -#include -#include - -#include "mv_eth.h" - -/* enable Debug outputs */ - -#undef DEBUG_MV_ETH - -#ifdef DEBUG_MV_ETH -#define DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#undef MV64460_CHECKSUM_OFFLOAD -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - -/* Definition for configuring driver */ -/* #define UPDATE_STATS_BY_SOFTWARE */ -#undef MV64460_RX_QUEUE_FILL_ON_TASK - - -/* Constants */ -#define MAGIC_ETH_RUNNING 8031971 -#define MV64460_INTERNAL_SRAM_SIZE _256K -#define EXTRA_BYTES 32 -#define WRAP ETH_HLEN + 2 + 4 + 16 -#define BUFFER_MTU dev->mtu + WRAP -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#ifdef MV64460_RX_FILL_ON_TASK -#define INT_CAUSE_MASK_ALL 0x00000000 -#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL -#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT -#endif - -/* Read/Write to/from MV64460 internal registers */ -#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) -#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) -#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) -#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) - -/* Static function declarations */ -static int mv64460_eth_real_open (struct eth_device *eth); -static int mv64460_eth_real_stop (struct eth_device *eth); -static struct net_device_stats *mv64460_eth_get_stats (struct eth_device - *dev); -static void eth_port_init_mac_tables (ETH_PORT eth_port_num); -static void mv64460_eth_update_stat (struct eth_device *dev); -bool db64460_eth_start (struct eth_device *eth); -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset); -int mv64460_eth_receive (struct eth_device *dev); - -int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length); - -#ifndef UPDATE_STATS_BY_SOFTWARE -static void mv64460_eth_print_stat (struct eth_device *dev); -#endif -/* Processes a received packet */ -extern void NetReceive (volatile uchar *, int); - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/************************************************* - *Helper functions - used inside the driver only * - *************************************************/ -#ifdef DEBUG_MV_ETH -void print_globals (struct eth_device *dev) -{ - printf ("Ethernet PRINT_Globals-Debug function\n"); - printf ("Base Address for ETH_PORT_INFO: %08x\n", - (unsigned int) dev->priv); - printf ("Base Address for mv64460_eth_priv: %08x\n", - (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> - port_private)); - - printf ("GT Internal Base Address: %08x\n", - INTERNAL_REG_BASE_ADDR); - printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE); - printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE); - printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_rx_buffer_base[0], - (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32); - printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_tx_buffer_base[0], - (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32); -} -#endif - -#define my_cpu_to_le32(x) my_le32_to_cpu((x)) - -unsigned long my_le32_to_cpu (unsigned long x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); -} - - -/********************************************************************** - * mv64460_eth_print_phy_status - * - * Prints gigabit ethenret phy status - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_print_phy_status (struct eth_device *dev) -{ - struct mv64460_eth_priv *port_private; - unsigned int port_num; - ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; - unsigned int port_status, phy_reg_data; - - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("Ethernet port changed link status to DOWN\n"); - } else { - port_status = - MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); - printf ("Ethernet status port %d: Link up", port_num); - printf (", %s", - (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); - if (port_status & BIT4) - printf (", Speed 1 Gbps"); - else - printf (", %s", - (port_status & BIT5) ? "Speed 100 Mbps" : - "Speed 10 Mbps"); - printf ("\n"); - } -} - -/********************************************************************** - * u-boot entry functions for mv64460_eth - * - **********************************************************************/ -int db64460_eth_probe (struct eth_device *dev) -{ - return ((int) db64460_eth_start (dev)); -} - -int db64460_eth_poll (struct eth_device *dev) -{ - return mv64460_eth_receive (dev); -} - -int db64460_eth_transmit (struct eth_device *dev, volatile void *packet, - int length) -{ - mv64460_eth_xmit (dev, packet, length); - return 0; -} - -void db64460_eth_disable (struct eth_device *dev) -{ - mv64460_eth_stop (dev); -} - - -void mv6446x_eth_initialize (bd_t * bis) -{ - struct eth_device *dev; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - int devnum, x, temp; - char *s, *e, buf[64]; - - for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { - dev = calloc (sizeof (*dev), 1); - if (!dev) { - printf ("%s: mv_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than NAMESIZE (16) */ - sprintf (dev->name, "mv_enet%d", devnum); - -#ifdef DEBUG - printf ("Initializing %s\n", dev->name); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_r (s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - /* ronen - set the MAC addr in the HW */ - eth_port_uc_addr_set (devnum, dev->enetaddr, 0); - - dev->init = (void *) db64460_eth_probe; - dev->halt = (void *) ethernet_phy_reset; - dev->send = (void *) db64460_eth_transmit; - dev->recv = (void *) db64460_eth_poll; - - ethernet_private = calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *)ethernet_private; - if (!ethernet_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Private Device Structure"); - free (dev); - return; - } - /* start with an zeroed ETH_PORT_INFO */ - memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - /* set pointer to memory for stats data structure etc... */ - port_private = calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; - if (!port_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Port Private Device Structure"); - - free (ethernet_private); - free (dev); - return; - } - - port_private->stats = - calloc (sizeof (struct net_device_stats), 1); - if (!port_private->stats) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Net stat Structure"); - - free (port_private); - free (ethernet_private); - free (dev); - return; - } - memset (ethernet_private->port_private, 0, - sizeof (struct mv64460_eth_priv)); - switch (devnum) { - case 0: - ethernet_private->port_num = ETH_0; - break; - case 1: - ethernet_private->port_num = ETH_1; - break; - case 2: - ethernet_private->port_num = ETH_2; - break; - default: - printf ("Invalid device number %d\n", devnum); - break; - }; - - port_private->port_num = devnum; - /* - * Read MIB counter on the GT in order to reset them, - * then zero all the stats fields in memory - */ - mv64460_eth_update_stat (dev); - memset (port_private->stats, 0, - sizeof (struct net_device_stats)); - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_r (s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - DP (printf ("Allocating descriptor and buffer rings\n")); - - ethernet_private->p_rx_desc_area_base[0] = - (ETH_RX_DESC *) memalign (16, - RX_DESC_ALIGNED_SIZE * - MV64460_RX_QUEUE_SIZE + 1); - ethernet_private->p_tx_desc_area_base[0] = - (ETH_TX_DESC *) memalign (16, - TX_DESC_ALIGNED_SIZE * - MV64460_TX_QUEUE_SIZE + 1); - - ethernet_private->p_rx_buffer_base[0] = - (char *) memalign (16, - MV64460_RX_QUEUE_SIZE * - MV64460_TX_BUFFER_SIZE + 1); - ethernet_private->p_tx_buffer_base[0] = - (char *) memalign (16, - MV64460_RX_QUEUE_SIZE * - MV64460_TX_BUFFER_SIZE + 1); - -#ifdef DEBUG_MV_ETH - /* DEBUG OUTPUT prints adresses of globals */ - print_globals (dev); -#endif - eth_register (dev); - - } - DP (printf ("%s: exit\n", __FUNCTION__)); - -} - -/********************************************************************** - * mv64460_eth_open - * - * This function is called when openning the network device. The function - * should initialize all the hardware, initialize cyclic Rx/Tx - * descriptors chain and buffers and allocate an IRQ to the network - * device. - * - * Input : a pointer to the network device structure - * / / ronen - changed the output to match net/eth.c needs - * Output : nonzero of success , zero if fails. - * under construction - **********************************************************************/ - -int mv64460_eth_open (struct eth_device *dev) -{ - return (mv64460_eth_real_open (dev)); -} - -/* Helper function for mv64460_eth_open */ -static int mv64460_eth_real_open (struct eth_device *dev) -{ - - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - u32 port_status, phy_reg_data; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - /* ronen - when we update the MAC env params we only update dev->enetaddr - see ./net/eth.c eth_set_enetaddr() */ - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Clear the ethernet port interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - - /* Unmask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL); - - /* Unmask phy and link status changes interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL_EXT); - - /* Set phy address of the port */ - ethernet_private->port_phy_addr = 0x8 + port_num; - - /* Activate the DMA channels etc */ - eth_port_init (ethernet_private); - - - /* "Allocate" setup TX rings */ - - for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { - unsigned int size; - - port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE; - size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ - ethernet_private->tx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_tx_desc_area_base[queue], - 0, ethernet_private->tx_desc_area_size[queue]); - - /* initialize tx desc ring with low level driver */ - if (ether_init_tx_desc_ring - (ethernet_private, ETH_Q0, - port_private->tx_ring_size[queue], - MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_tx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_tx_buffer_base[queue]) == false) - printf ("### Error initializing TX Ring\n"); - } - - /* "Allocate" setup RX rings */ - for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { - unsigned int size; - - /* Meantime RX Ring are fixed - but must be configurable by user */ - port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE; - size = (port_private->rx_ring_size[queue] * - RX_DESC_ALIGNED_SIZE); - ethernet_private->rx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_rx_desc_area_base[queue], - 0, ethernet_private->rx_desc_area_size[queue]); - if ((ether_init_rx_desc_ring - (ethernet_private, ETH_Q0, - port_private->rx_ring_size[queue], - MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_rx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_rx_buffer_base[queue])) == false) - printf ("### Error initializing RX Ring\n"); - } - - eth_port_start (ethernet_private); - - /* Set maximum receive buffer to 9700 bytes */ - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num), - (0x5 << 17) | - (MV_REG_READ - (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num)) - & 0xfff1ffff)); - - /* - * Set ethernet MTU for leaky bucket mechanism to 0 - this will - * disable the leaky bucket mechanism . - */ - - MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - /* Reset PHY */ - if ((ethernet_phy_reset (port_num)) != true) { - printf ("$$ Warnning: No link on port %d \n", - port_num); - return 0; - } else { - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("### Error: Phy is not active\n"); - return 0; - } - } - } else { - mv64460_eth_print_phy_status (dev); - } - port_private->eth_running = MAGIC_ETH_RUNNING; - return 1; -} - - -static int mv64460_eth_free_tx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - volatile ETH_TX_DESC *p_tx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop Tx Queues */ - MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free TX rings */ - DP (printf ("Clearing previously allocated TX queues... ")); - for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { - /* Free on TX rings */ - for (p_tx_curr_desc = - ethernet_private->p_tx_desc_area_base[queue]; - ((unsigned int) p_tx_curr_desc <= (unsigned int) - ethernet_private->p_tx_desc_area_base[queue] + - ethernet_private->tx_desc_area_size[queue]); - p_tx_curr_desc = - (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + - TX_DESC_ALIGNED_SIZE)) { - /* this is inside for loop */ - if (p_tx_curr_desc->return_info != 0) { - p_tx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -static int mv64460_eth_free_rx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - volatile ETH_RX_DESC *p_rx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - /* Stop RX Queues */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free RX rings */ - DP (printf ("Clearing previously allocated RX queues... ")); - for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { - /* Free preallocated skb's on RX rings */ - for (p_rx_curr_desc = - ethernet_private->p_rx_desc_area_base[queue]; - (((unsigned int) p_rx_curr_desc < - ((unsigned int) ethernet_private-> - p_rx_desc_area_base[queue] + - ethernet_private->rx_desc_area_size[queue]))); - p_rx_curr_desc = - (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + - RX_DESC_ALIGNED_SIZE)) { - if (p_rx_curr_desc->return_info != 0) { - p_rx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -/********************************************************************** - * mv64460_eth_stop - * - * This function is used when closing the network device. - * It updates the hardware, - * release all memory that holds buffers and descriptors and release the IRQ. - * Input : a pointer to the device structure - * Output : zero if success , nonzero if fails - *********************************************************************/ - -int mv64460_eth_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Disable all gigE address decoder */ - MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f); - DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); - mv64460_eth_real_stop (dev); - - return 0; -}; - -/* Helper function for mv64460_eth_stop */ - -static int mv64460_eth_real_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - mv64460_eth_free_tx_rings (dev); - mv64460_eth_free_rx_rings (dev); - - eth_port_reset (ethernet_private->port_num); - /* Disable ethernet port interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - /* Mask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0); - /* Mask phy and link status changes interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); - MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH, - BIT0 << port_num); - /* Print Network statistics */ -#ifndef UPDATE_STATS_BY_SOFTWARE - /* - * Print statistics (only if ethernet is running), - * then zero all the stats fields in memory - */ - if (port_private->eth_running == MAGIC_ETH_RUNNING) { - port_private->eth_running = 0; - mv64460_eth_print_stat (dev); - } - memset (port_private->stats, 0, sizeof (struct net_device_stats)); -#endif - DP (printf ("\nEthernet stopped ... \n")); - return 0; -} - - -/********************************************************************** - * mv64460_eth_start_xmit - * - * This function is queues a packet in the Tx descriptor for - * required port. - * - * Input : skb - a pointer to socket buffer - * dev - a pointer to the required port - * - * Output : zero upon success - **********************************************************************/ - -int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, - int dataSize) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - PKT_INFO pkt_info; - ETH_FUNC_RET_STATUS status; - struct net_device_stats *stats; - ETH_FUNC_RET_STATUS release_result; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - stats = port_private->stats; - - /* Update packet info data structure */ - pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ - pkt_info.byte_cnt = dataSize; - pkt_info.buf_ptr = (unsigned int) dataPtr; - - status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); - if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { - printf ("Error on transmitting packet .."); - if (status == ETH_QUEUE_FULL) - printf ("ETH Queue is full. \n"); - if (status == ETH_QUEUE_LAST_RESOURCE) - printf ("ETH Queue: using last available resource. \n"); - goto error; - } - - /* Update statistics and start of transmittion time */ - stats->tx_bytes += dataSize; - stats->tx_packets++; - - /* Check if packet(s) is(are) transmitted correctly (release everything) */ - do { - release_result = - eth_tx_return_desc (ethernet_private, ETH_Q0, - &pkt_info); - switch (release_result) { - case ETH_OK: - DP (printf ("descriptor released\n")); - if (pkt_info.cmd_sts & BIT0) { - printf ("Error in TX\n"); - stats->tx_errors++; - - } - break; - case ETH_RETRY: - DP (printf ("transmission still in process\n")); - break; - - case ETH_ERROR: - printf ("routine can not access Tx desc ring\n"); - break; - - case ETH_END_OF_JOB: - DP (printf ("the routine has nothing to release\n")); - break; - default: /* should not happen */ - break; - } - } while (release_result == ETH_OK); - - - return 0; /* success */ - error: - return 1; /* Failed - higher layers will free the skb */ -} - -/********************************************************************** - * mv64460_eth_receive - * - * This function is forward packets that are received from the port's - * queues toward kernel core or FastRoute them to another interface. - * - * Input : dev - a pointer to the required interface - * max - maximum number to receive (0 means unlimted) - * - * Output : number of served packets - **********************************************************************/ - -int mv64460_eth_receive (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - PKT_INFO pkt_info; - struct net_device_stats *stats; - - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - stats = port_private->stats; - - while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == - ETH_OK)) { - -#ifdef DEBUG_MV_ETH - if (pkt_info.byte_cnt != 0) { - printf ("%s: Received %d byte Packet @ 0x%x\n", - __FUNCTION__, pkt_info.byte_cnt, - pkt_info.buf_ptr); - } -#endif - /* Update statistics. Note byte count includes 4 byte CRC count */ - stats->rx_packets++; - stats->rx_bytes += pkt_info.byte_cnt; - - /* - * In case received a packet without first / last bits on OR the error - * summary bit is on, the packets needs to be dropeed. - */ - if (((pkt_info. - cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != - (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) - || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { - stats->rx_dropped++; - - printf ("Received packet spread on multiple descriptors\n"); - - /* Is this caused by an error ? */ - if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { - stats->rx_errors++; - } - - /* free these descriptors again without forwarding them to the higher layers */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - /* /free these descriptors again */ - } else { - -/* !!! call higher layer processing */ -#ifdef DEBUG_MV_ETH - printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); -#endif - /* let the upper layer handle the packet */ - NetReceive ((uchar *) pkt_info.buf_ptr, - (int) pkt_info.byte_cnt); - -/* **************************************************************** */ -/* free descriptor */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - DP (printf - ("RX: pkt_info.buf_ptr = %x\n", - pkt_info.buf_ptr)); - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - -/* **************************************************************** */ - - } - } - mv64460_eth_get_stats (dev); /* update statistics */ - return 1; -} - -/********************************************************************** - * mv64460_eth_get_stats - * - * Returns a pointer to the interface statistics. - * - * Input : dev - a pointer to the required interface - * - * Output : a pointer to the interface's statistics - **********************************************************************/ - -static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - mv64460_eth_update_stat (dev); - - return port_private->stats; -} - - -/********************************************************************** - * mv64460_eth_update_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_update_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - struct net_device_stats *stats; - unsigned int port_num; - volatile unsigned int dummy; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - stats = port_private->stats; - - /* These are false updates */ - stats->rx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_RECEIVED); - stats->tx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_SENT); - stats->rx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); - /* - * Ideally this should be as follows - - * - * stats->rx_bytes += stats->rx_bytes + - * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , - * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); - * - * But the unsigned long in PowerPC and MIPS are 32bit. So the next read - * is just a dummy read for proper work of the GigE port - */ - dummy = eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); - stats->tx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_LOW); - dummy = eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_HIGH); - stats->rx_errors += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MAC_RECEIVE_ERROR); - - /* Rx dropped is for received packet with CRC error */ - stats->rx_dropped += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_BAD_CRC_EVENT); - stats->multicast += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MULTICAST_FRAMES_RECEIVED); - stats->collisions += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_COLLISION) + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_LATE_COLLISION); - /* detailed rx errors */ - stats->rx_length_errors += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_UNDERSIZE_RECEIVED) - + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_OVERSIZE_RECEIVED); - /* detailed tx errors */ -} - -#ifndef UPDATE_STATS_BY_SOFTWARE -/********************************************************************** - * mv64460_eth_print_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_print_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - struct net_device_stats *stats; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - stats = port_private->stats; - - /* These are false updates */ - printf ("\n### Network statistics: ###\n"); - printf ("--------------------------\n"); - printf (" Packets received: %ld\n", stats->rx_packets); - printf (" Packets send: %ld\n", stats->tx_packets); - printf (" Received bytes: %ld\n", stats->rx_bytes); - printf (" Send bytes: %ld\n", stats->tx_bytes); - if (stats->rx_errors != 0) - printf (" Rx Errors: %ld\n", - stats->rx_errors); - if (stats->rx_dropped != 0) - printf (" Rx dropped (CRC Errors): %ld\n", - stats->rx_dropped); - if (stats->multicast != 0) - printf (" Rx mulicast frames: %ld\n", - stats->multicast); - if (stats->collisions != 0) - printf (" No. of collisions: %ld\n", - stats->collisions); - if (stats->rx_length_errors != 0) - printf (" Rx length errors: %ld\n", - stats->rx_length_errors); -} -#endif - -/************************************************************************** - *network_start - Network Kick Off Routine UBoot - *Inputs : - *Outputs : - **************************************************************************/ - -bool db64460_eth_start (struct eth_device *dev) -{ - return (mv64460_eth_open (dev)); /* calls real open */ -} - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* - * based on Linux code - * arch/ppc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -/******************************************************************************** - * Marvell's Gigabit Ethernet controller low level driver - * - * DESCRIPTION: - * This file introduce low level API to Marvell's Gigabit Ethernet - * controller. This Gigabit Ethernet Controller driver API controls - * 1) Operations (i.e. port init, start, reset etc'). - * 2) Data flow (i.e. port send, receive etc'). - * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO - * struct. - * This struct includes user configuration information as well as - * driver internal data needed for its operations. - * - * Supported Features: - * - This low level driver is OS independent. Allocating memory for - * the descriptor rings and buffers are not within the scope of - * this driver. - * - The user is free from Rx/Tx queue managing. - * - This low level driver introduce functionality API that enable - * the to operate Marvell's Gigabit Ethernet Controller in a - * convenient way. - * - Simple Gigabit Ethernet port operation API. - * - Simple Gigabit Ethernet port data flow API. - * - Data flow and operation API support per queue functionality. - * - Support cached descriptors for better performance. - * - Enable access to all four DRAM banks and internal SRAM memory - * spaces. - * - PHY access and control API. - * - Port control register configuration API. - * - Full control over Unicast and Multicast MAC configurations. - * - * Operation flow: - * - * Initialization phase - * This phase complete the initialization of the ETH_PORT_INFO - * struct. - * User information regarding port configuration has to be set - * prior to calling the port initialization routine. For example, - * the user has to assign the port_phy_addr field which is board - * depended parameter. - * In this phase any port Tx/Rx activity is halted, MIB counters - * are cleared, PHY address is set according to user parameter and - * access to DRAM and internal SRAM memory spaces. - * - * Driver ring initialization - * Allocating memory for the descriptor rings and buffers is not - * within the scope of this driver. Thus, the user is required to - * allocate memory for the descriptors ring and buffers. Those - * memory parameters are used by the Rx and Tx ring initialization - * routines in order to curve the descriptor linked list in a form - * of a ring. - * Note: Pay special attention to alignment issues when using - * cached descriptors/buffers. In this phase the driver store - * information in the ETH_PORT_INFO struct regarding each queue - * ring. - * - * Driver start - * This phase prepares the Ethernet port for Rx and Tx activity. - * It uses the information stored in the ETH_PORT_INFO struct to - * initialize the various port registers. - * - * Data flow: - * All packet references to/from the driver are done using PKT_INFO - * struct. - * This struct is a unified struct used with Rx and Tx operations. - * This way the user is not required to be familiar with neither - * Tx nor Rx descriptors structures. - * The driver's descriptors rings are management by indexes. - * Those indexes controls the ring resources and used to indicate - * a SW resource error: - * 'current' - * This index points to the current available resource for use. For - * example in Rx process this index will point to the descriptor - * that will be passed to the user upon calling the receive routine. - * In Tx process, this index will point to the descriptor - * that will be assigned with the user packet info and transmitted. - * 'used' - * This index points to the descriptor that need to restore its - * resources. For example in Rx process, using the Rx buffer return - * API will attach the buffer returned in packet info to the - * descriptor pointed by 'used'. In Tx process, using the Tx - * descriptor return will merely return the user packet info with - * the command status of the transmitted buffer pointed by the - * 'used' index. Nevertheless, it is essential to use this routine - * to update the 'used' index. - * 'first' - * This index supports Tx Scatter-Gather. It points to the first - * descriptor of a packet assembled of multiple buffers. For example - * when in middle of Such packet we have a Tx resource error the - * 'curr' index get the value of 'first' to indicate that the ring - * returned to its state before trying to transmit this packet. - * - * Receive operation: - * The eth_port_receive API set the packet information struct, - * passed by the caller, with received information from the - * 'current' SDMA descriptor. - * It is the user responsibility to return this resource back - * to the Rx descriptor ring to enable the reuse of this source. - * Return Rx resource is done using the eth_rx_return_buff API. - * - * Transmit operation: - * The eth_port_send API supports Scatter-Gather which enables to - * send a packet spanned over multiple buffers. This means that - * for each packet info structure given by the user and put into - * the Tx descriptors ring, will be transmitted only if the 'LAST' - * bit will be set in the packet info command status field. This - * API also consider restriction regarding buffer alignments and - * sizes. - * The user must return a Tx resource after ensuring the buffer - * has been transmitted to enable the Tx ring indexes to update. - * - * BOARD LAYOUT - * This device is on-board. No jumper diagram is necessary. - * - * EXTERNAL INTERFACE - * - * Prior to calling the initialization routine eth_port_init() the user - * must set the following fields under ETH_PORT_INFO struct: - * port_num User Ethernet port number. - * port_phy_addr User PHY address of Ethernet port. - * port_mac_addr[6] User defined port MAC address. - * port_config User port configuration value. - * port_config_extend User port config extend value. - * port_sdma_config User port SDMA config value. - * port_serial_control User port serial control value. - * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. - * *port_private User scratch pad for user specific data structures. - * - * This driver introduce a set of default values: - * PORT_CONFIG_VALUE Default port configuration value - * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value - * PORT_SDMA_CONFIG_VALUE Default sdma control value - * PORT_SERIAL_CONTROL_VALUE Default port serial control value - * - * This driver data flow is done using the PKT_INFO struct which is - * a unified struct for Rx and Tx operations: - * byte_cnt Tx/Rx descriptor buffer byte count. - * l4i_chk CPU provided TCP Checksum. For Tx operation only. - * cmd_sts Tx/Rx descriptor command status. - * buf_ptr Tx/Rx descriptor buffer pointer. - * return_info Tx/Rx user resource return information. - * - * - * EXTERNAL SUPPORT REQUIREMENTS - * - * This driver requires the following external support: - * - * D_CACHE_FLUSH_LINE (address, address offset) - * - * This macro applies assembly code to flush and invalidate cache - * line. - * address - address base. - * address offset - address offset - * - * - * CPU_PIPE_FLUSH - * - * This macro applies assembly code to flush the CPU pipeline. - * - *******************************************************************************/ -/* includes */ - -/* defines */ -/* SDMA command macros */ -#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) - -#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ - (1 << (8 + tx_queue))) - -#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) - -#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) - -#define CURR_RFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) - -#define CURR_RFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_RFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) - -#define USED_RFD_SET(p_used_desc, queue)\ -(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) - - -#define CURR_TFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) - -#define CURR_TFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_TFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) - -#define USED_TFD_SET(p_used_desc, queue) \ - (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) - -#define FIRST_TFD_GET(p_first_desc, queue) \ - ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) - -#define FIRST_TFD_SET(p_first_desc, queue) \ - (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) - - -/* Macros that save access to desc in order to find next desc pointer */ -#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) - -#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) - -#define LINK_UP_TIMEOUT 100000 -#define PHY_BUSY_TIMEOUT 10000000 - -/* locals */ - -/* PHY routines */ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); -static int ethernet_phy_get (ETH_PORT eth_port_num); - -/* Ethernet Port routines */ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param); -static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, - ETH_QUEUE queue, int option); -#if 0 /* FIXME */ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option); -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option); -#endif - -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count); - -void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); - - -typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; -u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64460_CS_0_BASE_ADDR); - if (bank == BANK1) - result = MV_REG_READ (MV64460_CS_1_BASE_ADDR); - if (bank == BANK2) - result = MV_REG_READ (MV64460_CS_2_BASE_ADDR); - if (bank == BANK3) - result = MV_REG_READ (MV64460_CS_3_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_dram_bank_size (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64460_CS_0_SIZE); - if (bank == BANK1) - result = MV_REG_READ (MV64460_CS_1_SIZE); - if (bank == BANK2) - result = MV_REG_READ (MV64460_CS_2_SIZE); - if (bank == BANK3) - result = MV_REG_READ (MV64460_CS_3_SIZE); - result += 1; - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_internal_sram_base (void) -{ - u32 result; - - result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -/******************************************************************************* -* eth_port_init - Initialize the Ethernet port driver -* -* DESCRIPTION: -* This function prepares the ethernet port to start its activity: -* 1) Completes the ethernet port driver struct initialization toward port -* start routine. -* 2) Resets the device to a quiescent state in case of warm reboot. -* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -* 4) Clean MAC tables. The reset status of those tables is unknown. -* 5) Set PHY address. -* Note: Call this routine prior to eth_port_start routine and after setting -* user values in the user fields of Ethernet port control struct (i.e. -* port_phy_addr). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* See description. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - ETH_WIN_PARAM win_param; - - p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; - p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; - p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; - p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; - - p_eth_port_ctrl->port_rx_queue_command = 0; - p_eth_port_ctrl->port_tx_queue_command = 0; - - /* Zero out SW structs */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->rx_resource_err[queue] = false; - } - - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->tx_resource_err[queue] = false; - } - - eth_port_reset (p_eth_port_ctrl->port_num); - - /* Set access parameters for DRAM bank 0 */ - win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); - win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 1 */ - win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); - win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 2 */ - win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); - win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 3 */ - win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); - win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for Internal SRAM */ - win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ - win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ - win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; - win_param.high_addr = 0; - win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ - win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */ - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - eth_port_init_mac_tables (p_eth_port_ctrl->port_num); - - ethernet_phy_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_phy_addr); - - return; - -} - -/******************************************************************************* -* eth_port_start - Start the Ethernet port activity. -* -* DESCRIPTION: -* This routine prepares the Ethernet port for Rx and Tx activity: -* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -* has been initialized a descriptor's ring (using ether_init_tx_desc_ring -* for Tx and ether_init_rx_desc_ring for Rx) -* 2. Initialize and enable the Ethernet configuration port by writing to -* the port's configuration and command registers. -* 3. Initialize and enable the SDMA by writing to the SDMA's -* configuration and command registers. -* After completing these steps, the ethernet port SDMA can starts to -* perform Rx and Tx activities. -* -* Note: Each Rx and Tx queue descriptor's list must be initialized prior -* to calling this function (use ether_init_tx_desc_ring for Tx queues and -* ether_init_rx_desc_ring for Rx queues). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* Ethernet port is ready to receive and transmit. -* -* RETURN: -* false if the port PHY is not up. -* true otherwise. -* -*******************************************************************************/ -static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - volatile ETH_TX_DESC *p_tx_curr_desc; - volatile ETH_RX_DESC *p_rx_curr_desc; - unsigned int phy_reg_data; - ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; - - - /* Assignment of Tx CTRP of given queue */ - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_GET (p_tx_curr_desc, queue); - MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_tx_curr_desc)); - - } - - /* Assignment of Rx CRDP of given queue */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_GET (p_rx_curr_desc, queue); - MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_rx_curr_desc)); - - if (p_rx_curr_desc != NULL) - /* Add the assigned Ethernet address to the port's address table */ - eth_port_uc_addr_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_mac_addr, - queue); - } - - /* Assign port configuration and command. */ - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_config); - - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - p_eth_port_ctrl->port_config_extend); - - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - p_eth_port_ctrl->port_serial_control); - - MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - ETH_SERIAL_PORT_ENABLE); - - /* Assign port SDMA configuration */ - MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_sdma_config); - - MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT - (eth_port_num), 0x3fffffff); - MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG - (eth_port_num), 0x03fffcff); - /* Turn off the port/queue bandwidth limitation */ - MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); - - /* Enable port Rx. */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), - p_eth_port_ctrl->port_rx_queue_command); - - /* Check if link is up */ - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (!(phy_reg_data & 0x20)) - return false; - - return true; -} - -/******************************************************************************* -* eth_port_uc_addr_set - This function Set the port Unicast address. -* -* DESCRIPTION: -* This function Set the port Ethernet MAC address. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. -* -* OUTPUT: -* Set MAC address low and high registers. also calls eth_port_uc_addr() -* To set the unicast table with the proper information. -* -* RETURN: -* N/A. -* -*******************************************************************************/ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, ETH_QUEUE queue) -{ - unsigned int mac_h; - unsigned int mac_l; - - mac_l = (p_addr[4] << 8) | (p_addr[5]); - mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | - (p_addr[2] << 8) | (p_addr[3] << 0); - - MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); - MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); - - /* Accept frames of this address */ - eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); - - return; -} - -/******************************************************************************* -* eth_port_uc_addr - This function Set the port unicast address table -* -* DESCRIPTION: -* This function locates the proper entry in the Unicast table for the -* specified MAC nibble and sets its properties according to function -* parameters. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* This function add/removes MAC addresses from the port unicast address -* table. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_uc_addr (ETH_PORT eth_port_num, - unsigned char uc_nibble, - ETH_QUEUE queue, int option) -{ - unsigned int unicast_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the Unicast table entry */ - uc_nibble = (0xf & uc_nibble); - tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ - reg_offset = uc_nibble % 4; /* Entry offset within the above register */ - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified unicast DA table entry */ - unicast_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - - break; - - default: - return false; - } - return true; -} - -#if 0 /* FIXME */ -/******************************************************************************* -* eth_port_mc_addr - Multicast address settings. -* -* DESCRIPTION: -* This API controls the MV device MAC multicast support. -* The MV device supports multicast using two tables: -* 1) Special Multicast Table for MAC addresses of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* In this case, the function calls eth_port_smc_addr() routine to set the -* Special Multicast Table. -* 2) Other Multicast Table for multicast of another type. A CRC-8bit -* is used as an index to the Other Multicast Table entries in the -* DA-Filter table. -* In this case, the function calculates the CRC-8bit value and calls -* eth_port_omc_addr() routine to set the Other Multicast Table. -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if add_address_table_entry( ) failed. -* -*******************************************************************************/ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, int option) -{ - unsigned int mac_h; - unsigned int mac_l; - unsigned char crc_result = 0; - int mac_array[48]; - int crc[8]; - int i; - - - if ((p_addr[0] == 0x01) && - (p_addr[1] == 0x00) && - (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) - - eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); - else { - /* Calculate CRC-8 out of the given address */ - mac_h = (p_addr[0] << 8) | (p_addr[1]); - mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | - (p_addr[4] << 8) | (p_addr[5] << 0); - - for (i = 0; i < 32; i++) - mac_array[i] = (mac_l >> i) & 0x1; - for (i = 32; i < 48; i++) - mac_array[i] = (mac_h >> (i - 32)) & 0x1; - - - crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ - mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ - mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ - mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ - mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ - mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[0]; - - crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ - mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ - mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ - mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ - mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ - mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ - mac_array[0]; - - crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ - mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ - mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ - mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ - mac_array[2] ^ mac_array[1] ^ mac_array[0]; - - crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ - mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ - mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ - mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ - mac_array[2] ^ mac_array[1]; - - crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ - mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ - mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ - mac_array[2]; - - crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ - mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ - mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ - mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ - mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ - mac_array[3]; - - crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ - mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ - mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ - mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[6] ^ mac_array[5] ^ mac_array[4]; - - crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ - mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ - mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ - mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ - mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[5]; - - for (i = 0; i < 8; i++) - crc_result = crc_result | (crc[i] << i); - - eth_port_omc_addr (eth_port_num, crc_result, queue, option); - } - return; -} - -/******************************************************************************* -* eth_port_smc_addr - Special Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device special MAC multicast support. -* The Special Multicast Table for MAC addresses supports MAC of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* This function set the Special Multicast Table appropriate entry -* according to the argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option) -{ - unsigned int smc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the SMC table entry */ - tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ - reg_offset = mc_byte % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - default: - return false; - } - return true; -} - -/******************************************************************************* -* eth_port_omc_addr - Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device Other MAC multicast support. -* The Other Multicast Table is used for multicast of another type. -* A CRC-8bit is used as an index to the Other Multicast Table entries -* in the DA-Filter table. -* The function gets the CRC-8bit value from the calling routine and -* set the Other Multicast Table appropriate entry according to the -* CRC-8 argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option) -{ - unsigned int omc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the OMC table entry */ - tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ - reg_offset = crc8 % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - default: - return false; - } - return true; -} -#endif - -/******************************************************************************* -* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -* -* DESCRIPTION: -* Go through all the DA filter tables (Unicast, Special Multicast & Other -* Multicast) and set each entry to 0. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Multicast and Unicast packets are rejected. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init_mac_tables (ETH_PORT eth_port_num) -{ - int table_index; - - /* Clear DA filter unicast table (Ex_dFUT) */ - for (table_index = 0; table_index <= 0xC; table_index += 4) - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) + table_index), 0); - - for (table_index = 0; table_index <= 0xFC; table_index += 4) { - /* Clear DA filter special multicast table (Ex_dFSMT) */ - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - /* Clear DA filter other multicast table (Ex_dFOMT) */ - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - } -} - -/******************************************************************************* -* eth_clear_mib_counters - Clear all MIB counters -* -* DESCRIPTION: -* This function clears all MIB counters of a specific ethernet port. -* A read from the MIB counter will reset the counter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* After reading all MIB counters, the counters resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -static void eth_clear_mib_counters (ETH_PORT eth_port_num) -{ - int i; - unsigned int dummy; - - /* Perform dummy reads from MIB counters */ - for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) - dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); - - return; -} - -/******************************************************************************* -* eth_read_mib_counter - Read a MIB counter -* -* DESCRIPTION: -* This function reads a MIB counter of a specific ethernet port. -* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the -* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH -* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and -* ETH_MIB_GOOD_OCTETS_SENT_HIGH -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). -* -* OUTPUT: -* After reading the MIB counter, the counter resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset) -{ - return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num) - + mib_offset)); -} - -/******************************************************************************* -* ethernet_phy_set - Set the ethernet port PHY address. -* -* DESCRIPTION: -* This routine set the ethernet port PHY address according to given -* parameter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Set PHY Address Register with given PHY address parameter. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); - - reg_data &= ~(0x1F << (5 * eth_port_num)); - reg_data |= (phy_addr << (5 * eth_port_num)); - - MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data); - - return; -} - -/******************************************************************************* - * ethernet_phy_get - Get the ethernet port PHY address. - * - * DESCRIPTION: - * This routine returns the given ethernet port PHY address. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * PHY address. - * - *******************************************************************************/ -static int ethernet_phy_get (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); - - return ((reg_data >> (5 * eth_port_num)) & 0x1f); -} - -/******************************************************************************* - * ethernet_phy_reset - Reset Ethernet port PHY. - * - * DESCRIPTION: - * This routine utilize the SMI interface to reset the ethernet port PHY. - * The routine waits until the link is up again or link up is timeout. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * The ethernet port PHY renew its link. - * - * RETURN: - * None. - * -*******************************************************************************/ -static bool ethernet_phy_reset (ETH_PORT eth_port_num) -{ - unsigned int time_out = 50; - unsigned int phy_reg_data; - - /* Reset the PHY */ - eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); - phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ - eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); - - /* Poll on the PHY LINK */ - do { - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (time_out-- == 0) - return false; - } - while (!(phy_reg_data & 0x20)); - - return true; -} - -/******************************************************************************* - * eth_port_reset - Reset Ethernet port - * - * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and - * clearing the MIB counters. The Receiver and the Transmit unit are in - * idle state after this command is performed and the port is disabled. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * Channel activity is halted. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_port_reset (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - /* Stop Tx port activity. Check port Tx activity. */ - reg_data = - MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Tx activity to terminate. */ - do { - /* Check port cause register that all Tx queues are stopped */ - reg_data = - MV_REG_READ - (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Stop Rx port activity. Check port Rx activity. */ - reg_data = - MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Rx activity to terminate. */ - do { - /* Check port cause register that all Rx queues are stopped */ - reg_data = - MV_REG_READ - (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - - /* Clear all MIB counters */ - eth_clear_mib_counters (eth_port_num); - - /* Reset the Enable bit in the Configuration Register */ - reg_data = - MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG - (eth_port_num)); - reg_data &= ~ETH_SERIAL_PORT_ENABLE; - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - reg_data); - - return; -} - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_set_config_reg - Set specified bits in configuration register. - * - * DESCRIPTION: - * This function sets specified bits in the given ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are set in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_set_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = - MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num)); - eth_config_reg |= value; - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* FIXME */ -/******************************************************************************* - * ethernet_reset_config_reg - Reset specified bits in configuration register. - * - * DESCRIPTION: - * This function resets specified bits in the given Ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are reset in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_reset_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - eth_config_reg &= ~value; - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_get_config_reg - Get the port configuration register - * - * DESCRIPTION: - * This function returns the configuration register value of the given - * ethernet port. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * Port configuration register value. - * - *******************************************************************************/ -static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - return eth_config_reg; -} - -#endif - -/******************************************************************************* - * eth_port_read_smi_reg - Read PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform PHY register read. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int *value Register value buffer. - * - * OUTPUT: - * Write the value of a specified PHY register into given buffer. - * - * RETURN: - * false if the PHY is busy or read data is not in valid state. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); -/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ -#define PHY_UPDATE_TIMEOUT 10000 - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return true; -} - -/******************************************************************************* - * eth_port_write_smi_reg - Write to PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform writes to PHY registers. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int value Register value. - * - * OUTPUT: - * Write the given value to the specified PHY register. - * - * RETURN: - * false if the PHY is busy. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return true; -} - -/******************************************************************************* - * eth_set_access_control - Config address decode parameters for Ethernet unit - * - * DESCRIPTION: - * This function configures the address decode parameters for the Gigabit - * Ethernet Controller according the given parameters struct. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * ETH_WIN_PARAM *param Address decode parameter struct. - * - * OUTPUT: - * An access window is opened using the given access parameters. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param) -{ - unsigned int access_prot_reg; - - /* Set access control register */ - access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG - (eth_port_num)); - access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ - access_prot_reg |= (param->access_ctrl << (param->win * 2)); - MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num), - access_prot_reg); - - /* Set window Size reg (SR) */ - MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 + - (ETH_SIZE_REG_GAP * param->win)), - (((param->size / 0x10000) - 1) << 16)); - - /* Set window Base address reg (BA) */ - MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), - (param->target | param->attributes | param->base_addr)); - /* High address remap reg (HARR) */ - if (param->win < 4) - MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 + - (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), - param->high_addr); - - /* Base address enable reg (BARER) */ - if (param->enable == 1) - MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); - else - MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); -} - -/******************************************************************************* - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Rx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer - * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. - * unsigned int rx_buff_base_addr Rx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Rx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr) -{ - ETH_RX_DESC *p_rx_desc; - ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ - unsigned int buffer_addr; - int ix; /* a counter */ - - - p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; - p_rx_prev_desc = p_rx_desc; - buffer_addr = rx_buff_base_addr; - - /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (rx_buff_base_addr & 0xF) - return false; - - /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) - return false; - - /* Rx buffers must be 64-bit aligned. */ - if ((rx_buff_base_addr + rx_buff_size) & 0x7) - return false; - - /* initialize the Rx descriptors ring */ - for (ix = 0; ix < rx_desc_num; ix++) { - p_rx_desc->buf_size = rx_buff_size; - p_rx_desc->byte_cnt = 0x0000; - p_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - p_rx_desc->next_desc_ptr = - ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; - p_rx_desc->buf_ptr = buffer_addr; - p_rx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_rx_desc, 0); - buffer_addr += rx_buff_size; - p_rx_prev_desc = p_rx_desc; - p_rx_desc = (ETH_RX_DESC *) - ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); - } - - /* Closing Rx descriptors ring */ - p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); - D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); - - /* Save Rx desc pointer to driver struct. */ - CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - - p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = - (ETH_RX_DESC *) rx_desc_base_addr; - p_eth_port_ctrl->rx_desc_area_size[rx_queue] = - rx_desc_num * RX_DESC_ALIGNED_SIZE; - - p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); - - return true; -} - -/******************************************************************************* - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Tx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer - * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. - * unsigned int tx_buff_base_addr Tx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Tx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr) -{ - - ETH_TX_DESC *p_tx_desc; - ETH_TX_DESC *p_tx_prev_desc; - unsigned int buffer_addr; - int ix; /* a counter */ - - - /* save the first desc pointer to link with the last descriptor */ - p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; - p_tx_prev_desc = p_tx_desc; - buffer_addr = tx_buff_base_addr; - - /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (tx_buff_base_addr & 0xF) - return false; - - /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((tx_buff_size > TX_BUFFER_MAX_SIZE) - || (tx_buff_size < TX_BUFFER_MIN_SIZE)) - return false; - - /* Initialize the Tx descriptors ring */ - for (ix = 0; ix < tx_desc_num; ix++) { - p_tx_desc->byte_cnt = 0x0000; - p_tx_desc->l4i_chk = 0x0000; - p_tx_desc->cmd_sts = 0x00000000; - p_tx_desc->next_desc_ptr = - ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; - - p_tx_desc->buf_ptr = buffer_addr; - p_tx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_tx_desc, 0); - buffer_addr += tx_buff_size; - p_tx_prev_desc = p_tx_desc; - p_tx_desc = (ETH_TX_DESC *) - ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); - - } - /* Closing Tx descriptors ring */ - p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; - D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); - /* Set Tx desc pointer in driver struct. */ - CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - - /* Init Tx ring base and size parameters */ - p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = - (ETH_TX_DESC *) tx_desc_base_addr; - p_eth_port_ctrl->tx_desc_area_size[tx_queue] = - (tx_desc_num * TX_DESC_ALIGNED_SIZE); - - /* Add the queue to the list of Tx queues of this port */ - p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); - - return true; -} - -/******************************************************************************* - * eth_port_send - Send an Ethernet packet - * - * DESCRIPTION: - * This routine send a given packet described by p_pktinfo parameter. It - * supports transmitting of a packet spaned over multiple buffers. The - * routine updates 'curr' and 'first' indexes according to the packet - * segment passed to the routine. In case the packet segment is first, - * the 'first' index is update. In any case, the 'curr' index is updated. - * If the routine get into Tx resource error it assigns 'curr' index as - * 'first'. This way the function can abort Tx process of multiple - * descriptors per packet. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'curr' and 'first' indexes are updated. - * - * RETURN: - * ETH_QUEUE_FULL in case of Tx resource error. - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_first; - volatile ETH_TX_DESC *p_tx_desc_curr; - volatile ETH_TX_DESC *p_tx_next_desc_curr; - volatile ETH_TX_DESC *p_tx_desc_used; - unsigned int command_status; - - /* Do not process Tx ring in case of Tx ring resource error */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - return ETH_QUEUE_FULL; - - /* Get the Tx Desc ring indexes */ - CURR_TFD_GET (p_tx_desc_curr, tx_queue); - USED_TFD_GET (p_tx_desc_used, tx_queue); - - if (p_tx_desc_curr == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); - command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; - - if (command_status & (ETH_TX_FIRST_DESC)) { - /* Update first desc */ - FIRST_TFD_SET (p_tx_desc_curr, tx_queue); - p_tx_desc_first = p_tx_desc_curr; - } else { - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - command_status |= ETH_BUFFER_OWNED_BY_DMA; - } - - /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ - /* boundary. We use the memory allocated for Tx descriptor. This memory */ - /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ - if (p_pkt_info->byte_cnt <= 8) { - printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ - return ETH_ERROR; - - p_tx_desc_curr->buf_ptr = - (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; - eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, - p_pkt_info->byte_cnt); - } else - p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; - - p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; - p_tx_desc_curr->return_info = p_pkt_info->return_info; - - if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { - /* Set last desc with DMA ownership and interrupt enable. */ - p_tx_desc_curr->cmd_sts = command_status | - ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; - - if (p_tx_desc_curr != p_tx_desc_first) - p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; - - /* Flush CPU pipe */ - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); - CPU_PIPE_FLUSH; - - /* Apply send command */ - ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); - - /* Finish Tx packet. Update first desc in case of Tx resource error */ - p_tx_desc_first = p_tx_next_desc_curr; - FIRST_TFD_SET (p_tx_desc_first, tx_queue); - - } else { - p_tx_desc_curr->cmd_sts = command_status; - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - } - - /* Check for ring index overlap in the Tx desc ring */ - if (p_tx_next_desc_curr == p_tx_desc_used) { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_desc_first, tx_queue); - - p_eth_port_ctrl->tx_resource_err[tx_queue] = true; - return ETH_QUEUE_LAST_RESOURCE; - } else { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); - return ETH_OK; - } -} - -/******************************************************************************* - * eth_tx_return_desc - Free all used Tx descriptors - * - * DESCRIPTION: - * This routine returns the transmitted packet information to the caller. - * It uses the 'first' index to support Tx desc return in case a transmit - * of a packet spanned over multiple buffer still in process. - * In case the Tx queue was in "resource error" condition, where there are - * no available Tx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'first' and 'used' indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_RETRY in case there is transmission in process. - * ETH_END_OF_JOB if the routine has nothing to release. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_used = NULL; - volatile ETH_TX_DESC *p_tx_desc_first = NULL; - unsigned int command_status; - - - /* Get the Tx Desc ring indexes */ - USED_TFD_GET (p_tx_desc_used, tx_queue); - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - - - /* Sanity check */ - if (p_tx_desc_used == NULL) - return ETH_ERROR; - - command_status = p_tx_desc_used->cmd_sts; - - /* Still transmitting... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_RETRY; - } - - /* Stop release. About to overlap the current available Tx descriptor */ - if ((p_tx_desc_used == p_tx_desc_first) && - (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_END_OF_JOB; - } - - /* Pass the packet information to the caller */ - p_pkt_info->cmd_sts = command_status; - p_pkt_info->return_info = p_tx_desc_used->return_info; - p_tx_desc_used->return_info = 0; - - /* Update the next descriptor to release. */ - USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); - - /* Any Tx return cancels the Tx resource error status */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - p_eth_port_ctrl->tx_resource_err[tx_queue] = false; - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - - return ETH_OK; - -} - -/******************************************************************************* - * eth_port_receive - Get received information from Rx ring. - * - * DESCRIPTION: - * This routine returns the received data to the caller. There is no - * data copying during routine operation. All information is returned - * using pointer to packet information struct passed from the caller. - * If the routine exhausts Rx ring resources then the resource error flag - * is set. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Rx ring current and used indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_QUEUE_FULL if Rx ring resources are exhausted. - * ETH_END_OF_JOB if there is no received data. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_rx_curr_desc; - volatile ETH_RX_DESC *p_rx_next_curr_desc; - volatile ETH_RX_DESC *p_rx_used_desc; - unsigned int command_status; - - /* Do not process Rx ring in case of Rx ring resource error */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { - printf ("\nRx Queue is full ...\n"); - return ETH_QUEUE_FULL; - } - - /* Get the Rx Desc ring 'curr and 'used' indexes */ - CURR_RFD_GET (p_rx_curr_desc, rx_queue); - USED_RFD_GET (p_rx_used_desc, rx_queue); - - /* Sanity check */ - if (p_rx_curr_desc == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); - command_status = p_rx_curr_desc->cmd_sts; - - /* Nothing to receive... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); -/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ - return ETH_END_OF_JOB; - } - - p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; - p_pkt_info->cmd_sts = command_status; - p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; - p_pkt_info->return_info = p_rx_curr_desc->return_info; - p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ - - /* Clean the return info field to indicate that the packet has been */ - /* moved to the upper layers */ - p_rx_curr_desc->return_info = 0; - - /* Update 'curr' in data structure */ - CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); - - /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ - if (p_rx_next_curr_desc == p_rx_used_desc) - p_eth_port_ctrl->rx_resource_err[rx_queue] = true; - - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); - CPU_PIPE_FLUSH; - return ETH_OK; -} - -/******************************************************************************* - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. - * - * DESCRIPTION: - * This routine returns a Rx buffer back to the Rx ring. It retrieves the - * next 'used' descriptor and attached the returned buffer to it. - * In case the Rx ring was in "resource error" condition, where there are - * no available Rx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info Information on the returned buffer. - * - * OUTPUT: - * New available Rx resource in Rx descriptor ring. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ - - /* Get 'used' Rx descriptor */ - USED_RFD_GET (p_used_rx_desc, rx_queue); - - /* Sanity check */ - if (p_used_rx_desc == NULL) - return ETH_ERROR; - - p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; - p_used_rx_desc->return_info = p_pkt_info->return_info; - p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; - p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */ - - /* Flush the write pipe */ - CPU_PIPE_FLUSH; - - /* Return the descriptor to DMA ownership */ - p_used_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - - /* Flush descriptor and CPU pipe */ - D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); - CPU_PIPE_FLUSH; - - /* Move the used descriptor pointer to the next descriptor */ - USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); - - /* Any Rx return cancels the Rx resource error status */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) - p_eth_port_ctrl->rx_resource_err[rx_queue] = false; - - return ETH_OK; -} - -/******************************************************************************* - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path - * - * DESCRIPTION: - * This routine sets the RX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the tClk of the MV-643xx chip - * , and the required delay of the interrupt in usec. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in usec - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set RX Coalescing mechanism */ - MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), - ((coal & 0x3fff) << 8) | - (MV_REG_READ - (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num)) - & 0xffc000ff)); - return coal; -} - -#endif -/******************************************************************************* - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path - * - * DESCRIPTION: - * This routine sets the TX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the t_cLK frequency of the - * MV-643xx chip and the required delay in the interrupt in uSec - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in uSeconds - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set TX Coalescing mechanism */ - MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), - coal << 4); - return coal; -} -#endif - -/******************************************************************************* - * eth_b_copy - Copy bytes from source to destination - * - * DESCRIPTION: - * This function supports the eight bytes limitation on Tx buffer size. - * The routine will zero eight bytes starting from the destination address - * followed by copying bytes from the source address to the destination. - * - * INPUT: - * unsigned int src_addr 32 bit source address. - * unsigned int dst_addr 32 bit destination address. - * int byte_count Number of bytes to copy. - * - * OUTPUT: - * See description. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count) -{ - /* Zero the dst_addr area */ - *(unsigned int *) dst_addr = 0x0; - - while (byte_count != 0) { - *(char *) dst_addr = *(char *) src_addr; - dst_addr++; - src_addr++; - byte_count--; - } -} diff --git a/board/Marvell/db64460/mv_eth.h b/board/Marvell/db64460/mv_eth.h deleted file mode 100644 index b4e498b..0000000 --- a/board/Marvell/db64460/mv_eth.h +++ /dev/null @@ -1,840 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mv_eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __DB64460_ETH_H__ -#define __DB64460_ETH_H__ - -#include -#include -#include -#include -#include -#include "mv_regs.h" -#include "../common/ppc_error_no.h" - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ -#ifndef MAX_SKB_FRAGS -#define MAX_SKB_FRAGS 0 -#endif - -/* Port attributes */ -/*#define MAX_RX_QUEUE_NUM 8*/ -/*#define MAX_TX_QUEUE_NUM 8*/ -#define MAX_RX_QUEUE_NUM 1 -#define MAX_TX_QUEUE_NUM 1 - - -/* Use one TX queue and one RX queue */ -#define MV64460_TX_QUEUE_NUM 1 -#define MV64460_RX_QUEUE_NUM 1 - -/* - * Number of RX / TX descriptors on RX / TX rings. - * Note that allocating RX descriptors is done by allocating the RX - * ring AND a preallocated RX buffers (skb's) for each descriptor. - * The TX descriptors only allocates the TX descriptors ring, - * with no pre allocated TX buffers (skb's are allocated by higher layers. - */ - -/* Default TX ring size is 10 descriptors */ -#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE -#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE -#else -#define MV64460_TX_QUEUE_SIZE 4 -#endif - -/* Default RX ring size is 4 descriptors */ -#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE -#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE -#else -#define MV64460_RX_QUEUE_SIZE 4 -#endif - -#ifdef CONFIG_RX_BUFFER_SIZE -#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE -#else -#define MV64460_RX_BUFFER_SIZE 1600 -#endif - -#ifdef CONFIG_TX_BUFFER_SIZE -#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE -#else -#define MV64460_TX_BUFFER_SIZE 1600 -#endif - -/* - * Network device statistics. Akin to the 2.0 ether stats but - * with byte counters. - */ - -struct net_device_stats -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; -}; - - -/* Private data structure used for ethernet device */ -struct mv64460_eth_priv { - unsigned int port_num; - struct net_device_stats *stats; - -/* to buffer area aligned */ - char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ - char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ - - /* Size of Tx Ring per queue */ - unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; - - - /* Size of Rx Ring per queue */ - unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; - - /* Magic Number for Ethernet running */ - unsigned int eth_running; - -}; - -int mv64460_eth_init (struct eth_device *dev); -int mv64460_eth_stop (struct eth_device *dev); -int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length); -/* return db64460_eth0_poll(); */ - -int mv64460_eth_open (struct eth_device *dev); - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - - -/******************************************************************************** - * Header File for : MV-643xx network interface header - * - * DESCRIPTION: - * This header file contains macros typedefs and function declaration for - * the Marvell Gig Bit Ethernet Controller. - * - * DEPENDENCIES: - * None. - * - *******************************************************************************/ - - -#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY -#ifdef CONFIG_MV64460_SRAM_CACHEABLE -/* In case SRAM is cacheable but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case SRAM is cache coherent or non-cacheable */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif -#else -#ifdef CONFIG_NOT_COHERENT_CACHE -/* In case of descriptors on DDR but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case of descriptors on DDR and cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif /* CONFIG_NOT_COHERENT_CACHE */ -#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ - - -#define CPU_PIPE_FLUSH \ -{ \ - __asm__ __volatile__ ("eieio"); \ -} - - -/* defines */ - -/* Default port configuration value */ -#define PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -/* Default port extend configuration value */ -#define PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - - -/* Default sdma control value */ -#ifdef CONFIG_NOT_COHERENT_CACHE -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_16_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_16_64BIT; -#else -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT; -#endif - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ETTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_1552BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; - -#define RX_BUFFER_MAX_SIZE 0xFFFF -#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ - -#define RX_BUFFER_MIN_SIZE 0x8 -#define TX_BUFFER_MIN_SIZE 0x8 - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ - -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 - -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define RX_DESC_ALIGNED_SIZE 0x20 -#define TX_DESC_ALIGNED_SIZE 0x20 - -/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -#define TX_BUF_OFFSET_IN_DESC 0x18 -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Gap define */ -#define ETH_BAR_GAP 0x8 -#define ETH_SIZE_REG_GAP 0x8 -#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define ETH_PORT_ACCESS_CTRL_GAP 0x4 - -/* Gigabit Ethernet Unit Global Registers */ - -/* MIB Counters register definitions */ -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 -#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc -#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 -#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c -#define ETH_MIB_FRAMES_64_OCTETS 0x20 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c -#define ETH_MIB_GOOD_FRAMES_SENT 0x40 -#define ETH_MIB_EXCESSIVE_COLLISION 0x44 -#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 -#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 -#define ETH_MIB_FC_SENT 0x54 -#define ETH_MIB_GOOD_FC_RECEIVED 0x58 -#define ETH_MIB_BAD_FC_RECEIVED 0x5c -#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 -#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 -#define ETH_MIB_OVERSIZE_RECEIVED 0x68 -#define ETH_MIB_JABBER_RECEIVED 0x6c -#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 -#define ETH_MIB_BAD_CRC_EVENT 0x74 -#define ETH_MIB_COLLISION 0x78 -#define ETH_MIB_LATE_COLLISION 0x7c - -/* Port serial status reg (PSR) */ -#define ETH_INTERFACE_GMII_MII 0 -#define ETH_INTERFACE_PCM BIT0 -#define ETH_LINK_IS_DOWN 0 -#define ETH_LINK_IS_UP BIT1 -#define ETH_PORT_AT_HALF_DUPLEX 0 -#define ETH_PORT_AT_FULL_DUPLEX BIT2 -#define ETH_RX_FLOW_CTRL_DISABLED 0 -#define ETH_RX_FLOW_CTRL_ENBALED BIT3 -#define ETH_GMII_SPEED_100_10 0 -#define ETH_GMII_SPEED_1000 BIT4 -#define ETH_MII_SPEED_10 0 -#define ETH_MII_SPEED_100 BIT5 -#define ETH_NO_TX 0 -#define ETH_TX_IN_PROGRESS BIT7 -#define ETH_BYPASS_NO_ACTIVE 0 -#define ETH_BYPASS_ACTIVE BIT8 -#define ETH_PORT_NOT_AT_PARTITION_STATE 0 -#define ETH_PORT_AT_PARTITION_STATE BIT9 -#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 -#define ETH_PORT_TX_FIFO_EMPTY BIT10 - - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define ETH_UNICAST_NORMAL_MODE 0 -#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 -#define ETH_DEFAULT_RX_QUEUE_0 0 -#define ETH_DEFAULT_RX_QUEUE_1 BIT1 -#define ETH_DEFAULT_RX_QUEUE_2 BIT2 -#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_4 BIT3 -#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) -#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) -#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 -#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 -#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 -#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 -#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) -#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) -#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 -#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 -#define ETH_RECEIVE_BC_IF_IP 0 -#define ETH_REJECT_BC_IF_IP BIT8 -#define ETH_RECEIVE_BC_IF_ARP 0 -#define ETH_REJECT_BC_IF_ARP BIT9 -#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 -#define ETH_CAPTURE_TCP_FRAMES_DIS 0 -#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 -#define ETH_CAPTURE_UDP_FRAMES_DIS 0 -#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 -#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 -#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 -#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 -#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 -#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) -#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) -#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 -#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 -#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 -#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 -#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) -#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) -#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 -#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 -#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 -#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 -#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) -#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) - - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define ETH_CLASSIFY_EN BIT0 -#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 -#define ETH_PARTITION_DISABLE 0 -#define ETH_PARTITION_ENABLE BIT2 - - -/* Tx/Rx queue command reg (RQCR/TQCR)*/ -#define ETH_QUEUE_0_ENABLE BIT0 -#define ETH_QUEUE_1_ENABLE BIT1 -#define ETH_QUEUE_2_ENABLE BIT2 -#define ETH_QUEUE_3_ENABLE BIT3 -#define ETH_QUEUE_4_ENABLE BIT4 -#define ETH_QUEUE_5_ENABLE BIT5 -#define ETH_QUEUE_6_ENABLE BIT6 -#define ETH_QUEUE_7_ENABLE BIT7 -#define ETH_QUEUE_0_DISABLE BIT8 -#define ETH_QUEUE_1_DISABLE BIT9 -#define ETH_QUEUE_2_DISABLE BIT10 -#define ETH_QUEUE_3_DISABLE BIT11 -#define ETH_QUEUE_4_DISABLE BIT12 -#define ETH_QUEUE_5_DISABLE BIT13 -#define ETH_QUEUE_6_DISABLE BIT14 -#define ETH_QUEUE_7_DISABLE BIT15 - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define ETH_RIFB BIT0 -#define ETH_RX_BURST_SIZE_1_64BIT 0 -#define ETH_RX_BURST_SIZE_2_64BIT BIT1 -#define ETH_RX_BURST_SIZE_4_64BIT BIT2 -#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) -#define ETH_RX_BURST_SIZE_16_64BIT BIT3 -#define ETH_BLM_RX_NO_SWAP BIT4 -#define ETH_BLM_RX_BYTE_SWAP 0 -#define ETH_BLM_TX_NO_SWAP BIT5 -#define ETH_BLM_TX_BYTE_SWAP 0 -#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 -#define ETH_DESCRIPTORS_NO_SWAP 0 -#define ETH_TX_BURST_SIZE_1_64BIT 0 -#define ETH_TX_BURST_SIZE_2_64BIT BIT22 -#define ETH_TX_BURST_SIZE_4_64BIT BIT23 -#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) -#define ETH_TX_BURST_SIZE_16_64BIT BIT24 - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define ETH_SERIAL_PORT_DISABLE 0 -#define ETH_SERIAL_PORT_ENABLE BIT0 -#define ETH_FORCE_LINK_PASS BIT1 -#define ETH_DO_NOT_FORCE_LINK_PASS 0 -#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 -#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 -#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 -#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 -#define ETH_ADV_NO_FLOW_CTRL 0 -#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 -#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 -#define ETH_FORCE_BP_MODE_NO_JAM 0 -#define ETH_FORCE_BP_MODE_JAM_TX BIT7 -#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 -#define ETH_FORCE_LINK_FAIL 0 -#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 -#define ETH_RETRANSMIT_16_ETTEMPTS 0 -#define ETH_RETRANSMIT_FOREVER BIT11 -#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 -#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 -#define ETH_DTE_ADV_0 0 -#define ETH_DTE_ADV_1 BIT14 -#define ETH_DISABLE_AUTO_NEG_BYPASS 0 -#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 -#define ETH_AUTO_NEG_NO_CHANGE 0 -#define ETH_RESTART_AUTO_NEG BIT16 -#define ETH_MAX_RX_PACKET_1518BYTE 0 -#define ETH_MAX_RX_PACKET_1522BYTE BIT17 -#define ETH_MAX_RX_PACKET_1552BYTE BIT18 -#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) -#define ETH_MAX_RX_PACKET_9192BYTE BIT19 -#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) -#define ETH_SET_EXT_LOOPBACK BIT20 -#define ETH_CLR_EXT_LOOPBACK 0 -#define ETH_SET_FULL_DUPLEX_MODE BIT21 -#define ETH_SET_HALF_DUPLEX_MODE 0 -#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 -#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define ETH_SET_GMII_SPEED_TO_10_100 0 -#define ETH_SET_GMII_SPEED_TO_1000 BIT23 -#define ETH_SET_MII_SPEED_TO_10 0 -#define ETH_SET_MII_SPEED_TO_100 BIT24 - - -/* SMI reg */ -#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ -#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ -#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ -#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ - -/* SDMA command status fields macros */ - -/* Tx & Rx descriptors status */ -#define ETH_ERROR_SUMMARY (BIT0) - -/* Tx & Rx descriptors command */ -#define ETH_BUFFER_OWNED_BY_DMA (BIT31) - -/* Tx descriptors status */ -#define ETH_LC_ERROR (0 ) -#define ETH_UR_ERROR (BIT1 ) -#define ETH_RL_ERROR (BIT2 ) -#define ETH_LLC_SNAP_FORMAT (BIT9 ) - -/* Rx descriptors status */ -#define ETH_CRC_ERROR (0 ) -#define ETH_OVERRUN_ERROR (BIT1 ) -#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) -#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) -#define ETH_VLAN_TAGGED (BIT19) -#define ETH_BPDU_FRAME (BIT20) -#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) -#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) -#define ETH_OTHER_FRAME_TYPE (BIT22) -#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) -#define ETH_FRAME_TYPE_IP_V_4 (BIT24) -#define ETH_FRAME_HEADER_OK (BIT25) -#define ETH_RX_LAST_DESC (BIT26) -#define ETH_RX_FIRST_DESC (BIT27) -#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) -#define ETH_RX_ENABLE_INTERRUPT (BIT29) -#define ETH_LAYER_4_CHECKSUM_OK (BIT30) - -/* Rx descriptors byte count */ -#define ETH_FRAME_FRAGMENTED (BIT2) - -/* Tx descriptors command */ -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) -#define ETH_FRAME_SET_TO_VLAN (BIT15) -#define ETH_TCP_FRAME (0 ) -#define ETH_UDP_FRAME (BIT16) -#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) -#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) -#define ETH_ZERO_PADDING (BIT19) -#define ETH_TX_LAST_DESC (BIT20) -#define ETH_TX_FIRST_DESC (BIT21) -#define ETH_GEN_CRC (BIT22) -#define ETH_TX_ENABLE_INTERRUPT (BIT23) -#define ETH_AUTO_MODE (BIT30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attributes */ -#define EBAR_ATTR_DRAM_CS0 0x00000E00 -#define EBAR_ATTR_DRAM_CS1 0x00000D00 -#define EBAR_ATTR_DRAM_CS2 0x00000B00 -#define EBAR_ATTR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 -#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 -#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 -#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 -#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 - -/* CPU 60x bus or internal SRAM interface */ -#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define EBAR_ATTR_CBS_SRAM 0x00000000 -#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY BIT0 -#define EWIN_ACCESS_FULL (BIT1 | BIT0) -#define EWIN0_ACCESS_MASK 0x0003 -#define EWIN1_ACCESS_MASK 0x000C -#define EWIN2_ACCESS_MASK 0x0030 -#define EWIN3_ACCESS_MASK 0x00C0 - -/* typedefs */ - -typedef enum _eth_port -{ - ETH_0 = 0, - ETH_1 = 1, - ETH_2 = 2 -}ETH_PORT; - -typedef enum _eth_func_ret_status -{ - ETH_OK, /* Returned as expected. */ - ETH_ERROR, /* Fundamental error. */ - ETH_RETRY, /* Could not process request. Try later. */ - ETH_END_OF_JOB, /* Ring has nothing to process. */ - ETH_QUEUE_FULL, /* Ring resource error. */ - ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ -}ETH_FUNC_RET_STATUS; - -typedef enum _eth_queue -{ - ETH_Q0 = 0, - ETH_Q1 = 1, - ETH_Q2 = 2, - ETH_Q3 = 3, - ETH_Q4 = 4, - ETH_Q5 = 5, - ETH_Q6 = 6, - ETH_Q7 = 7 -} ETH_QUEUE; - -typedef enum _addr_win -{ - ETH_WIN0, - ETH_WIN1, - ETH_WIN2, - ETH_WIN3, - ETH_WIN4, - ETH_WIN5 -} ETH_ADDR_WIN; - -typedef enum _eth_target -{ - ETH_TARGET_DRAM , - ETH_TARGET_DEVICE, - ETH_TARGET_CBS , - ETH_TARGET_PCI0 , - ETH_TARGET_PCI1 -}ETH_TARGET; - -typedef struct _eth_rx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short buf_size ; /* Buffer size */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_RX_DESC; - - -typedef struct _eth_tx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_TX_DESC; - -/* Unified struct for Rx and Tx operations. The user is not required to */ -/* be familier with neither Tx nor Rx descriptors. */ -typedef struct _pkt_info -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} PKT_INFO; - - -typedef struct _eth_win_param -{ - ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ - ETH_TARGET target; /* System targets. See ETH_TARGET enum */ - unsigned short attributes; /* BAR attributes. See above macros. */ - unsigned int base_addr; /* Window base address in unsigned int form */ - unsigned int high_addr; /* Window high address in unsigned int form */ - unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ - bool enable; /* Enable/disable access to the window. */ - unsigned short access_ctrl; /* Access ctrl register. see above macros */ -} ETH_WIN_PARAM; - - -/* Ethernet port specific infomation */ - -typedef struct _eth_port_ctrl -{ - ETH_PORT port_num; /* User Ethernet port number */ - int port_phy_addr; /* User phy address of Ethrnet port */ - unsigned char port_mac_addr[6]; /* User defined port MAC address. */ - unsigned int port_config; /* User port configuration value */ - unsigned int port_config_extend; /* User port config extend value */ - unsigned int port_sdma_config; /* User port SDMA config value */ - unsigned int port_serial_control; /* User port serial control value */ - unsigned int port_tx_queue_command; /* Port active Tx queues summary */ - unsigned int port_rx_queue_command; /* Port active Rx queues summary */ - - /* User function to cast virtual address to CPU bus address */ - unsigned int (*port_virt_to_phys)(unsigned int addr); - /* User scratch pad for user specific data structures */ - void *port_private; - - bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ - bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ - - /* Tx/Rx rings managment indexes fields. For driver use */ - - /* Next available Rx resource */ - volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; - /* Returning Rx resource */ - volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; - - /* Next available Tx resource */ - volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; - /* Returning Tx resource */ - volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; - /* An extra Tx index to support transmit of multiple buffers per packet */ - volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; - - /* Tx/Rx rings size and base variables fields. For driver use */ - - volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; - unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; - char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; - - volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; - unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; - char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; - -} ETH_PORT_INFO; - - -/* ethernet.h API list */ - -/* Port operation control routines */ -static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); -static void eth_port_reset(ETH_PORT eth_port_num); -static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); - - -/* Port MAC address routines */ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue); -#if 0 /* FIXME */ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, - int option); -#endif - -/* PHY and MIB routines */ -static bool ethernet_phy_reset(ETH_PORT eth_port_num); - -static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int value); - -static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int* value); - -static void eth_clear_mib_counters(ETH_PORT eth_port_num); - -/* Port data flow control routines */ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); - - -static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr); - -static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr); - -#endif /* MV64460_ETH_ */ diff --git a/board/Marvell/db64460/mv_regs.h b/board/Marvell/db64460/mv_regs.h deleted file mode 100644 index fb50bb6..0000000 --- a/board/Marvell/db64460/mv_regs.h +++ /dev/null @@ -1,1124 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/******************************************************************************** -* gt64460r.h - GT-64460 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_regsh -#define __INCmv_regsh - -#define MV64460 - -/* Supported by the Atlantis */ -#define MV64460_INCLUDE_PCI_1 -#define MV64460_INCLUDE_PCI_0_ARBITER -#define MV64460_INCLUDE_PCI_1_ARBITER -#define MV64460_INCLUDE_SNOOP_SUPPORT -#define MV64460_INCLUDE_P2P -#define MV64460_INCLUDE_ETH_PORT_2 -#define MV64460_INCLUDE_CPU_MAPPING -#define MV64460_INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64460_CS_0_BASE_ADDR 0x008 -#define MV64460_CS_0_SIZE 0x010 -#define MV64460_CS_1_BASE_ADDR 0x208 -#define MV64460_CS_1_SIZE 0x210 -#define MV64460_CS_2_BASE_ADDR 0x018 -#define MV64460_CS_2_SIZE 0x020 -#define MV64460_CS_3_BASE_ADDR 0x218 -#define MV64460_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64460_DEV_CS0_BASE_ADDR 0x028 -#define MV64460_DEV_CS0_SIZE 0x030 -#define MV64460_DEV_CS1_BASE_ADDR 0x228 -#define MV64460_DEV_CS1_SIZE 0x230 -#define MV64460_DEV_CS2_BASE_ADDR 0x248 -#define MV64460_DEV_CS2_SIZE 0x250 -#define MV64460_DEV_CS3_BASE_ADDR 0x038 -#define MV64460_DEV_CS3_SIZE 0x040 -#define MV64460_BOOTCS_BASE_ADDR 0x238 -#define MV64460_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64460_PCI_0_IO_BASE_ADDR 0x048 -#define MV64460_PCI_0_IO_SIZE 0x050 -#define MV64460_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64460_PCI_0_MEMORY0_SIZE 0x060 -#define MV64460_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64460_PCI_0_MEMORY1_SIZE 0x088 -#define MV64460_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64460_PCI_0_MEMORY2_SIZE 0x260 -#define MV64460_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64460_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64460_PCI_1_IO_BASE_ADDR 0x090 -#define MV64460_PCI_1_IO_SIZE 0x098 -#define MV64460_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64460_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64460_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64460_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64460_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64460_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64460_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64460_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64460_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64460_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64460_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64460_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64460_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64460_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64460_CPU_CONFIG 0x000 -#define MV64460_CPU_MODE 0x120 -#define MV64460_CPU_MASTER_CONTROL 0x160 -#define MV64460_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64460_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64460_SMP_WHO_AM_I 0x200 -#define MV64460_SMP_CPU0_DOORBELL 0x214 -#define MV64460_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64460_SMP_CPU1_DOORBELL 0x224 -#define MV64460_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64460_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64460_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64460_SMP_SEMAPHOR0 0x244 -#define MV64460_SMP_SEMAPHOR1 0x24c -#define MV64460_SMP_SEMAPHOR2 0x254 -#define MV64460_SMP_SEMAPHOR3 0x25c -#define MV64460_SMP_SEMAPHOR4 0x264 -#define MV64460_SMP_SEMAPHOR5 0x26c -#define MV64460_SMP_SEMAPHOR6 0x274 -#define MV64460_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64460_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64460_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64460_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64460_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64460_CPU_ERROR_ADDR_LOW 0x070 -#define MV64460_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64460_CPU_ERROR_DATA_LOW 0x128 -#define MV64460_CPU_ERROR_DATA_HIGH 0x130 -#define MV64460_CPU_ERROR_PARITY 0x138 -#define MV64460_CPU_ERROR_CAUSE 0x140 -#define MV64460_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64460_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64460_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64460_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64460_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64460_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64460_SRAM_CONFIG 0x380 -#define MV64460_SRAM_TEST_MODE 0X3F4 -#define MV64460_SRAM_ERROR_CAUSE 0x388 -#define MV64460_SRAM_ERROR_ADDR 0x390 -#define MV64460_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64460_SRAM_ERROR_DATA_LOW 0x398 -#define MV64460_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64460_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64460_SDRAM_CONFIG 0x1400 -#define MV64460_D_UNIT_CONTROL_LOW 0x1404 -#define MV64460_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64460_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64460_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64460_SDRAM_ADDR_CONTROL 0x1410 -#define MV64460_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64460_SDRAM_OPERATION 0x1418 -#define MV64460_SDRAM_MODE 0x141c -#define MV64460_EXTENDED_DRAM_MODE 0x1420 -#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64460_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64460_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64460_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64460_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64460_SDRAM_ERROR_ADDR 0x1450 -#define MV64460_SDRAM_RECEIVED_ECC 0x1448 -#define MV64460_SDRAM_CALCULATED_ECC 0x144c -#define MV64460_SDRAM_ECC_CONTROL 0x1454 -#define MV64460_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64460_DFCDL_CONFIG0 0x1480 -#define MV64460_DFCDL_CONFIG1 0x1484 -#define MV64460_DLL_WRITE 0x1488 -#define MV64460_DLL_READ 0x148c -#define MV64460_SRAM_ADDR 0x1490 -#define MV64460_SRAM_DATA0 0x1494 -#define MV64460_SRAM_DATA1 0x1498 -#define MV64460_SRAM_DATA2 0x149c -#define MV64460_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64460_DUNIT_DEBUG_LOW 0x1460 -#define MV64460_DUNIT_DEBUG_HIGH 0x1464 -#define MV64460_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64460_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64460_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64460_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64460_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64460_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64460_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64460_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64460_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64460_DEVICE_ERROR_ADDR 0x4d8 -#define MV64460_DEVICE_ERROR_DATA 0x4dc -#define MV64460_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64460_DEVICE_DEBUG_LOW 0x4e4 -#define MV64460_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64460_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64460_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64460_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64460_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64460_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64460_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64460_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64460_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64460_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64460_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64460_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64460_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64460_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64460_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64460_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64460_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64460_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64460_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64460_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64460_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64460_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64460_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64460_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64460_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64460_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64460_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64460_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64460_PCI_0_COMMAND 0xc00 -#define MV64460_PCI_1_COMMAND 0xc80 -#define MV64460_PCI_0_MODE 0xd00 -#define MV64460_PCI_1_MODE 0xd80 -#define MV64460_PCI_0_RETRY 0xc04 -#define MV64460_PCI_1_RETRY 0xc84 -#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64460_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64460_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64460_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64460_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64460_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64460_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64460_PCI_0_P2P_CONFIG 0x1d14 -#define MV64460_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64460_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64460_PCI_1_CONFIG_ADDR 0xc78 -#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64460_PCI_0_SERR_MASK 0xc28 -#define MV64460_PCI_1_SERR_MASK 0xca8 -#define MV64460_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64460_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64460_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64460_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64460_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64460_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64460_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64460_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64460_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64460_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64460_PCI_0_ERROR_MASK 0x1d5c -#define MV64460_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64460_PCI_0_MMASK 0X1D24 -#define MV64460_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64460_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64460_PCI_STATUS_AND_COMMAND 0x004 -#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64460_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64460_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64460_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64460_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64460_PCI_VPD_ADDR 0x048 -#define MV64460_PCI_VPD_DATA 0x04c -#define MV64460_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64460_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64460_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64460_PCI_X_COMMAND 0x060 -#define MV64460_PCI_X_STATUS 0x064 -#define MV64460_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64460_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64460_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64460_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64460_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64460_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64460_ETH_PHY_ADDR_REG 0x2000 -#define MV64460_ETH_SMI_REG 0x2004 -#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64460_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64460_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64460_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64460_ETH_BAR_0 0x2200 -#define MV64460_ETH_BAR_1 0x2208 -#define MV64460_ETH_BAR_2 0x2210 -#define MV64460_ETH_BAR_3 0x2218 -#define MV64460_ETH_BAR_4 0x2220 -#define MV64460_ETH_BAR_5 0x2228 -#define MV64460_ETH_SIZE_REG_0 0x2204 -#define MV64460_ETH_SIZE_REG_1 0x220c -#define MV64460_ETH_SIZE_REG_2 0x2214 -#define MV64460_ETH_SIZE_REG_3 0x221c -#define MV64460_ETH_SIZE_REG_4 0x2224 -#define MV64460_ETH_SIZE_REG_5 0x222c -#define MV64460_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64460_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64460_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64460_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64460_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64460_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64460_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64460_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64460_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64460_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64460_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64460_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64460_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64460_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64460_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64460_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64460_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64460_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64460_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64460_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64460_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64460_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64460_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64460_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64460_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64460_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64460_CUNIT_SIZE0 0xf204 -#define MV64460_CUNIT_SIZE1 0xf20c -#define MV64460_CUNIT_SIZE2 0xf214 -#define MV64460_CUNIT_SIZE3 0xf21c -#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64460_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64460_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64460_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64460_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64460_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64460_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64460_CUNIT_CONFIG_REG 0xb40c -#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64460_CUNIT_DEBUG_LOW 0xf340 -#define MV64460_CUNIT_DEBUG_HIGH 0xf344 -#define MV64460_CUNIT_MMASK 0xf380 - - /* Cunit Base Address Enable Window Bits*/ -#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 -#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 -#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 -#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 - - /* MPSCs Clocks Routing Registers */ - -#define MV64460_MPSC_ROUTING_REG 0xb400 -#define MV64460_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64460_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64460_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64460_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64460_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64460_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64460_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64460_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64460_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64460_SDMA_CAUSE_REG 0xb800 -#define MV64460_SDMA_MASK_REG 0xb880 - - -/****************************************/ -/* SDMA Address Space Targets */ -/****************************************/ - -#define MV64460_SDMA_DRAM_CS_0_TARGET 0x0e00 -#define MV64460_SDMA_DRAM_CS_1_TARGET 0x0d00 -#define MV64460_SDMA_DRAM_CS_2_TARGET 0x0b00 -#define MV64460_SDMA_DRAM_CS_3_TARGET 0x0700 - -#define MV64460_SDMA_DEV_CS_0_TARGET 0x1e01 -#define MV64460_SDMA_DEV_CS_1_TARGET 0x1d01 -#define MV64460_SDMA_DEV_CS_2_TARGET 0x1b01 -#define MV64460_SDMA_DEV_CS_3_TARGET 0x1701 - -#define MV64460_SDMA_BOOT_CS_TARGET 0x0f00 - -#define MV64460_SDMA_SRAM_TARGET 0x0003 -#define MV64460_SDMA_60X_BUS_TARGET 0x4003 - -#define MV64460_PCI_0_TARGET 0x0003 -#define MV64460_PCI_1_TARGET 0x0004 - - -/* Devices BAR and size registers */ - -#define MV64460_DEV_CS0_BASE_ADDR 0x028 -#define MV64460_DEV_CS0_SIZE 0x030 -#define MV64460_DEV_CS1_BASE_ADDR 0x228 -#define MV64460_DEV_CS1_SIZE 0x230 -#define MV64460_DEV_CS2_BASE_ADDR 0x248 -#define MV64460_DEV_CS2_SIZE 0x250 -#define MV64460_DEV_CS3_BASE_ADDR 0x038 -#define MV64460_DEV_CS3_SIZE 0x040 -#define MV64460_BOOTCS_BASE_ADDR 0x238 -#define MV64460_BOOTCS_SIZE 0x240 - -/* SDMA Window access protection */ -#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0 -#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1 -#define MV64460_SDMA_WIN_ACCESS_FULL 2 - -/* BRG Interrupts */ - -#define MV64460_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64460_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) -#define MV64460_BRG_CAUSE_REG 0xb834 -#define MV64460_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64460_DMA_CHANNEL0_CONTROL 0x840 -#define MV64460_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64460_DMA_CHANNEL1_CONTROL 0x844 -#define MV64460_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64460_DMA_CHANNEL2_CONTROL 0x848 -#define MV64460_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64460_DMA_CHANNEL3_CONTROL 0x84C -#define MV64460_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64460_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64460_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64460_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64460_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64460_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64460_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64460_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64460_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64460_DMA_BASE_ADDR_REG0 0xa00 -#define MV64460_DMA_BASE_ADDR_REG1 0xa08 -#define MV64460_DMA_BASE_ADDR_REG2 0xa10 -#define MV64460_DMA_BASE_ADDR_REG3 0xa18 -#define MV64460_DMA_BASE_ADDR_REG4 0xa20 -#define MV64460_DMA_BASE_ADDR_REG5 0xa28 -#define MV64460_DMA_BASE_ADDR_REG6 0xa30 -#define MV64460_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64460_DMA_SIZE_REG0 0xa04 -#define MV64460_DMA_SIZE_REG1 0xa0c -#define MV64460_DMA_SIZE_REG2 0xa14 -#define MV64460_DMA_SIZE_REG3 0xa1c -#define MV64460_DMA_SIZE_REG4 0xa24 -#define MV64460_DMA_SIZE_REG5 0xa2c -#define MV64460_DMA_SIZE_REG6 0xa34 -#define MV64460_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64460_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64460_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64460_DMA_ARBITER_CONTROL 0x860 -#define MV64460_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64460_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64460_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64460_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64460_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64460_DMA_ERROR_ADDR 0x8c8 -#define MV64460_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64460_DMA_DEBUG_LOW 0x8e0 -#define MV64460_DMA_DEBUG_HIGH 0x8e4 -#define MV64460_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64460_TIMER_COUNTER0 0x850 -#define MV64460_TIMER_COUNTER1 0x854 -#define MV64460_TIMER_COUNTER2 0x858 -#define MV64460_TIMER_COUNTER3 0x85C -#define MV64460_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64460_WATCHDOG_CONFIG_REG 0xb410 -#define MV64460_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64460_I2C_SLAVE_ADDR 0xc000 -#define MV64460_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64460_I2C_DATA 0xc004 -#define MV64460_I2C_CONTROL 0xc008 -#define MV64460_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64460_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64460_GPP_IO_CONTROL 0xf100 -#define MV64460_GPP_LEVEL_CONTROL 0xf110 -#define MV64460_GPP_VALUE 0xf104 -#define MV64460_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64460_GPP_INTERRUPT_MASK0 0xf10c -#define MV64460_GPP_INTERRUPT_MASK1 0xf114 -#define MV64460_GPP_VALUE_SET 0xf118 -#define MV64460_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64460_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64460_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64460_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64460_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64460_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64460_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64460_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64460_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64460_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64460_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64460_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64460_MPP_CONTROL0 0xf000 -#define MV64460_MPP_CONTROL1 0xf004 -#define MV64460_MPP_CONTROL2 0xf008 -#define MV64460_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64460_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64460_SERIAL_INIT_CONTROL 0xf328 -#define MV64460_SERIAL_INIT_STATUS 0xf32c - - -#endif /* __INCgt64460rh */ diff --git a/board/Marvell/db64460/pci.c b/board/Marvell/db64460/pci.c deleted file mode 100644 index 5637284..0000000 --- a/board/Marvell/db64460/pci.c +++ /dev/null @@ -1,940 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* PCI.c - PCI functions */ - - -#include -#include - -#include "../include/pci.h" - -#undef DEBUG -#undef IDE_SET_NATIVE_MODE -static unsigned int local_buses[] = { 0, 0 }; - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { - {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, - {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, -}; - - -#ifdef DEBUG -static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; -static void gt_pci_bus_mode_display (PCI_HOST host) -{ - unsigned int mode; - - - mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; - switch (mode) { - case 0: - printf ("PCI %d bus mode: Conventional PCI\n", host); - break; - case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); - break; - case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); - break; - case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); - break; - default: - printf ("Unknown BUS %d\n", mode); - } -} -#endif - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_address_space_en[] = { - PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = 0; - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_WRITE (pci_configuration_data[host], data); -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, ®Base); - GT_REG_READ (regOffset + 8, ®End); - - if (regEnd <= regBase) - return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 16; - return regBase; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 16) & 0xffff; - high = ((bankBase + bankLength) >> 16) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xffff) << 16; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - return ((high & 0xffff) + 1) << 16; -} - - -/* ronen - 7/Dec/03*/ -/******************************************************************** -* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. -* Inputs: one of the PCI BAR -*********************************************************************/ -void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - /*ronen different function for 3rd bank. */ - unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; - - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + offset, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); - gtPciEnableInternalBAR (host, bank); -} - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData & regData); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum, unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE (pci_p2p_configuration[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), bus, - value); - } - return 0; -} - - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - /*ronen different function for 3rd bank. */ - unsigned int offset = - (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - - -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ -/* and is curently not called *. */ -#if 0 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - - {} -}; - -struct pci_controller pci0_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST0); -#endif - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci0_hose.last_busno = pci_hose_scan (&pci0_hose); - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); -#endif - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci1_hose.first_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - - pci1_hose.last_busno = pci_hose_scan (&pci1_hose); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -} diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c deleted file mode 100644 index 8cfe84c..0000000 --- a/board/Marvell/db64460/sdram_init.c +++ /dev/null @@ -1,1985 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************* - * adaption for the Marvell DB64460 Board - * Ingo Assmus (ingo.assmus@keymile.com) - ************************************************************************/ - - -/* sdram_init.c - automatic memory sizing */ - -#include -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include - -#include "eth.h" -#include "mpsc.h" -#include "../common/i2c.h" -#include "64460.h" -#include "mv_regs.h" - -#undef DEBUG -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -int set_dfcdlInit (void); /* setup delay line of Mv64460 */ -int mvDmaIsChannelActive (int); -int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); -int mvDmaTransfer (int, ulong, ulong, ulong, ulong); - -/* ------------------------------------------------------------------------- */ - -int -memory_map_bank (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ -#ifdef MAP_PCI - PCI_HOST host; -#endif - - -#ifdef DEBUG - if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf ("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank (bankNo, bankBase, bankLength); - -#ifdef MAP_PCI - for (host = PCI_HOST0; host <= PCI_HOST1; host++) { - const int features = - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | PCI_NO_SWAP; - - pciMapMemoryBank (host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures (host, bankNo, features, bankBase, - bankLength); - } -#endif - return 0; -} - -#define GB (1 << 30) - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; -} sdram_info_t; - -/* Typedefs for 'gtAuxilGetDIMMinfo' function */ - -typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE; - -typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, - SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, -} VOLTAGE_INTERFACE; - -typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 = - 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 = - 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR; -typedef enum _max_CL_supported_SD { SD_CL_1 = - 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, - SD_FAULT } MAX_CL_SUPPORTED_SD; - - -/* SDRAM/DDR information struct */ -typedef struct _gtMemoryDimmInfo { - MEMORY_TYPE memoryType; - unsigned int numOfRowAddresses; - unsigned int numOfColAddresses; - unsigned int numOfModuleBanks; - unsigned int dataWidth; - VOLTAGE_INTERFACE voltageInterface; - unsigned int errorCheckType; /* ECC , PARITY.. */ - unsigned int sdramWidth; /* 4,8,16 or 32 */ ; - unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ - unsigned int minClkDelay; - unsigned int burstLengthSupported; - unsigned int numOfBanksOnEachDevice; - unsigned int suportedCasLatencies; - unsigned int RefreshInterval; - unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ - unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ - MAX_CL_SUPPORTED_DDR maxClSupported_DDR; - MAX_CL_SUPPORTED_SD maxClSupported_SD; - unsigned int moduleBankDensity; - /* module attributes (true for yes) */ - bool bufferedAddrAndControlInputs; - bool registeredAddrAndControlInputs; - bool onCardPLL; - bool bufferedDQMBinputs; - bool registeredDQMBinputs; - bool differentialClockInput; - bool redundantRowAddressing; - - /* module general attributes */ - bool suportedAutoPreCharge; - bool suportedPreChargeAll; - bool suportedEarlyRasPreCharge; - bool suportedWrite1ReadBurst; - bool suported5PercentLowVCC; - bool suported5PercentUpperVCC; - /* module timing parameters */ - unsigned int minRasToCasDelay; - unsigned int minRowActiveRowActiveDelay; - unsigned int minRasPulseWidth; - unsigned int minRowPrechargeTime; /* measured in ns */ - - int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ - int addrAndCommandSetupTime; /* (measured in ns/100) */ - int dataInputSetupTime; /* LoP left of point (measured in ns) */ - int dataInputHoldTime; /* LoP left of point (measured in ns) */ -/* tAC times for highest 2nd and 3rd highest CAS Latency values */ - unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ - - /* Parameters calculated from - the extracted DIMM information */ - unsigned int size; - unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ - unsigned int numberOfDevices; - uchar drb_size; /* DRAM size in n*64Mbit */ - uchar slot; /* Slot Number this module is inserted in */ - uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ -#ifdef DEBUG - uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ - uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ - uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ - unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ - unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ - unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ - uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ - -#endif -} AUX_MEM_DIMM_INFO; - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NS10to10PS (unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ -static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned long spd_checksum; - -#ifdef ZUMA_NTL - /* zero all the values */ - memset (info, 0, sizeof (*info)); - -/* - if (!slot) { - info->slot = 0; - info->banks = 1; - info->registered = 0; - info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */ -/* info->tpar = 3; - info->tras_clocks = 5; - info->burst_len = 4; -*/ -#ifdef CONFIG_MV64460_ECC - /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ - dimmInfo->errorCheckType = 2; -/* info->ecc = 2;*/ -#endif -} - -return 0; - -#else - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; - -#ifdef DEBUG - unsigned int k; -#endif - unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; - int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; - uchar supp_cal, cal_val; - ulong memclk, tmemclk; - ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; - uchar data[128]; - - memclk = gd->bus_clk; - tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - - DP (puts ("before i2c read\n")); - - ret = i2c_read (addr, 0, 1, data, 128); - - DP (puts ("after i2c read\n")); - - /* zero all the values */ - memset (dimmInfo, 0, sizeof (*dimmInfo)); - - /* copy the SPD content 1:1 into the dimmInfo structure */ - for (i = 0; i <= 127; i++) { - dimmInfo->spd_raw_data[i] = data[i]; - } - - if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); - return 0; - } else - dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ - -#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT - - for (i = 0; i <= 127; i++) { - printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], - data[i]); - } - -#endif -#ifdef DEBUG -/* find Manufactura of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { - dimmInfo->manufactura[i] = data[64 + i]; - } - printf ("\nThis RAM-Module is produced by: %s\n", - dimmInfo->manufactura); - -/* find Manul-ID of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { - dimmInfo->modul_id[i] = data[73 + i]; - } - printf ("The Module-ID of this RAM-Module is: %s\n", - dimmInfo->modul_id); - -/* find Vendor-Data of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { - dimmInfo->vendor_data[i] = data[99 + i]; - } - printf ("Vendor Data of this RAM-Module is: %s\n", - dimmInfo->vendor_data); - -/* find modul_serial_no of Dimm Module */ - dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); - printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", - dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); - -/* find Manufac-Data of Dimm Module */ - dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); - printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ - -/* find modul_revision of Dimm Module */ - dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); - printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ - -/* find manufac_place of Dimm Module */ - dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); - printf ("manufac_place of this RAM-Module is: %d\n", - dimmInfo->manufac_place); - -#endif - -/*------------------------------------------------------------------------------------------------------------------------------*/ -/* calculate SPD checksum */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - spd_checksum = 0; - - for (i = 0; i <= 62; i++) { - spd_checksum += data[i]; - } - - if ((spd_checksum & 0xff) != data[63]) { - printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); - hang (); - } - - else - printf ("SPD Checksum ok!\n"); - - -/*------------------------------------------------------------------------------------------------------------------------------*/ - for (i = 2; i <= 35; i++) { - switch (i) { - case 2: /* Memory type (DDR / SDRAM) */ - dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; -#ifdef DEBUG - if (dimmInfo->memoryType == 0) - DP (printf - ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); - if (dimmInfo->memoryType == 1) - DP (printf - ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 3: /* Number Of Row Addresses */ - dimmInfo->numOfRowAddresses = data[i]; - DP (printf - ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 4: /* Number Of Column Addresses */ - dimmInfo->numOfColAddresses = data[i]; - DP (printf - ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 5: /* Number Of Module Banks */ - dimmInfo->numOfModuleBanks = data[i]; - DP (printf - ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 6: /* Data Width */ - dimmInfo->dataWidth = data[i]; - DP (printf - ("Module Data Width: %d\n", - dimmInfo->dataWidth)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 8: /* Voltage Interface */ - switch (data[i]) { - case 0x0: - dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); - break; - case 0x1: - dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); - break; - case 0x2: - dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); - break; - case 0x3: - dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); - break; - case 0x4: - dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); - break; - default: - dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); - break; - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 9: /* Minimum Cycle Time At Max CasLatancy */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = - rightOfPoint; - DP (printf - ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 10: /* Clock To Data Out */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOut_LoP = leftOfPoint; - dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - -/*#ifdef CONFIG_ECC */ - case 11: /* Error Check Type */ - dimmInfo->errorCheckType = data[i]; - DP (printf - ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); - break; -/* #endif */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 12: /* Refresh Interval */ - dimmInfo->RefreshInterval = data[i]; - DP (printf - ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 13: /* Sdram Width */ - dimmInfo->sdramWidth = data[i]; - DP (printf - ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 14: /* Error Check Data Width */ - dimmInfo->errorCheckDataWidth = data[i]; - DP (printf - ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 15: /* Minimum Clock Delay */ - dimmInfo->minClkDelay = data[i]; - DP (printf - ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 16: /* Burst Length Supported */ - /******-******-******-******* - * bit3 | bit2 | bit1 | bit0 * - *******-******-******-******* - burst length = * 8 | 4 | 2 | 1 * - ***************************** - - If for example bit0 and bit2 are set, the burst - length supported are 1 and 4. */ - - dimmInfo->burstLengthSupported = data[i]; -#ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); - if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); - if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); - if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); - if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 17: /* Number Of Banks On Each Device */ - dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf - ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 18: /* Suported Cas Latencies */ - - /* DDR: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - ********************************************************* - SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - dimmInfo->suportedCasLatencies = data[i]; -#ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); - if (dimmInfo->memoryType == 0) { /* SDRAM */ - for (k = 0; k <= 7; k++) { - if (dimmInfo-> - suportedCasLatencies & (1 << k)) - DP (printf - ("%d, ", - k + 1)); - } - - } else { /* DDR-RAM */ - - if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); - if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); - if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); - if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); - if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); - if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); - - } - DP (printf ("\n")); -#endif - /* Calculating MAX CAS latency */ - for (j = 7; j > 0; j--) { - if (((dimmInfo-> - suportedCasLatencies >> j) & 0x1) == - 1) { - switch (dimmInfo->memoryType) { - case DDR: - /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ - switch (j) { - case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3_5; - break; - case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3; - break; - case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2_5; - break; - case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2; - break; - case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_1_5; - break; - } - - /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy - lower then our SDRAM cycle count, we won't be able to support this CAL - and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - < - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - < - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - dimmInfo-> - maxClSupported_DDR - = - dimmInfo-> - maxClSupported_DDR - >> 1; - DP (printf - ("*** Change actual Cas Latencies cause of minimumCycleTime n")); - } - /* ronen - checkif the Dimm frequency compared to the Sysclock. */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - > - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - > - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - printf ("*********************************************************\n"); - printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); - printf ("*********************************************************\n"); - hang (); - } - - dimmInfo-> - maxCASlatencySupported_LoP - = - 1 + - (int) (5 * j / 10); - if (((5 * j) % 10) != 0) - dimmInfo-> - maxCASlatencySupported_RoP - = 5; - else - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - DP (printf - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP)); - break; - case SDRAM: - /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ - dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf - ("Max. Cas Latencies (SD): %d\n", - dimmInfo-> - maxClSupported_SD)); - dimmInfo-> - maxCASlatencySupported_LoP - = j; - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - DP (printf - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP)); - break; - } - break; - } - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); - dimmInfo->bufferedAddrAndControlInputs = - data[i] & BIT0; - dimmInfo->registeredAddrAndControlInputs = - (data[i] & BIT1) >> 1; - dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; - dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; - dimmInfo->registeredDQMBinputs = - (data[i] & BIT4) >> 4; - dimmInfo->differentialClockInput = - (data[i] & BIT5) >> 5; - dimmInfo->redundantRowAddressing = - (data[i] & BIT6) >> 6; -#ifdef DEBUG - if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); - else - DP (printf - (" - Buffered Address/Control Input: No \n")); - - if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); - else - DP (printf - (" - Registered Address/Control Input: No \n")); - - if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); - else - DP (printf - (" - On-Card PLL (clock): No \n")); - - if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); - else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); - - if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); - else - DP (printf - (" - Registered DQMB Inputs: No \n")); - - if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); - else - DP (printf - (" - Differential Clock Input: No \n")); - - if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); - else - DP (printf - (" - redundant Row Addressing: No \n")); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); - dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; - dimmInfo->suportedAutoPreCharge = - (data[i] & BIT1) >> 1; - dimmInfo->suportedPreChargeAll = - (data[i] & BIT2) >> 2; - dimmInfo->suportedWrite1ReadBurst = - (data[i] & BIT3) >> 3; - dimmInfo->suported5PercentLowVCC = - (data[i] & BIT4) >> 4; - dimmInfo->suported5PercentUpperVCC = - (data[i] & BIT5) >> 5; -#ifdef DEBUG - if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); - else - DP (printf - (" - Early Ras Precharge: No \n")); - - if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); - else - DP (printf - (" - AutoPreCharge: No \n")); - - if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); - else - DP (printf - (" - Precharge All: No \n")); - - if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); - else - DP (printf - (" - Write 1/ReadBurst: No \n")); - - if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); - else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); - - if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); - else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = - rightOfPoint; - DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = - rightOfPoint; - DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 27: /* Minimum Row Precharge Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ - trp_clocks = - (dimmInfo->minRowPrechargeTime + - (tmemclk - 1)) / tmemclk; - DP (printf - ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf - ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 28: /* Minimum Row Active to Row Active Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 29: /* Minimum Ras-To-Cas Delay */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 30: /* Minimum Ras Pulse Width */ - dimmInfo->minRasPulseWidth = data[i]; - tras_clocks = - (NSto10PS (data[i]) + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 31: /* Module Bank Density */ - dimmInfo->moduleBankDensity = data[i]; - DP (printf - ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); -#ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); - { - if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); - if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); - if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); - if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); - if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); - if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); - if ((dimmInfo->moduleBankDensity & 64) - || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); - hang (); - } - } - DP (printf ("\n")); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 32: /* Address And Command Setup Time (measured in ns/1000) */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 33: /* Address And Command Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 34: /* Data Input Setup Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 35: /* Data Input Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - } - } - /* calculating the sdram density */ - for (i = 0; - i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; - i++) { - density = density * 2; - } - dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * - dimmInfo->sdramWidth; - dimmInfo->numberOfDevices = - (dimmInfo->dataWidth / dimmInfo->sdramWidth) * - dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; - if ((dimmInfo->errorCheckType == 0x1) - || (dimmInfo->errorCheckType == 0x2) - || (dimmInfo->errorCheckType == 0x3)) { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - (dimmInfo->numberOfDevices - - /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */ - dimmInfo->numberOfDevices / 8); - } else { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - dimmInfo->numberOfDevices; - } - - /* compute the module DRB size */ - tmp = (1 << - (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); - tmp *= dimmInfo->numOfModuleBanks; - tmp *= dimmInfo->sdramWidth; - tmp = tmp >> 24; /* div by 0x4000000 (64M) */ - dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); - - /* try a CAS latency of 3 first... */ - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1; - - cal_val = 0; - if (supp_cal & 3) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 3; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 2; - } - - DP (printf ("cal_val = %d\n", cal_val)); - - /* bummer, did't work... */ - if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); - hang (); - return 0; - } - - return true; -#endif -} - -/* sets up the GT properly with information passed in */ -int setup_sdram (AUX_MEM_DIMM_INFO * info) -{ - ulong tmp, check; - ulong tmp_sdram_mode = 0; /* 0x141c */ - ulong tmp_dunit_control_low = 0; /* 0x1404 */ - int i; - - /* added 8/21/2003 P. Marchese */ - unsigned int sdram_config_reg; - - /* added 10/10/2003 P. Marchese */ - ulong sdram_chip_size; - - /* sanity checking */ - if (!info->numOfModuleBanks) { - printf ("setup_sdram called with 0 banks\n"); - return 1; - } - - /* delay line */ - set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); - - /* set SDRAM mode NOP */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); - } - - /* SDRAM configuration */ -/* added 8/21/2003 P. Marchese */ -/* code allows usage of registered DIMMS */ - - /* figure out the memory refresh internal */ - switch (info->RefreshInterval) { - case 0x0: - case 0x80: /* refresh period is 15.625 usec */ - sdram_config_reg = - (unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ) - / (float) 1000000.0); - break; - case 0x1: - case 0x81: /* refresh period is 3.9 usec */ - sdram_config_reg = - (unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) / - (float) 1000000.0); - break; - case 0x2: - case 0x82: /* refresh period is 7.8 usec */ - sdram_config_reg = - (unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) / - (float) 1000000.0); - break; - case 0x3: - case 0x83: /* refresh period is 31.3 usec */ - sdram_config_reg = - (unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) / - (float) 1000000.0); - break; - case 0x4: - case 0x84: /* refresh period is 62.5 usec */ - sdram_config_reg = - (unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) / - (float) 1000000.0); - break; - case 0x5: - case 0x85: /* refresh period is 125 usec */ - sdram_config_reg = - (unsigned int) (((float) 125 * (float) CFG_BUS_HZ) / - (float) 1000000.0); - break; - default: /* refresh period undefined */ - printf ("DRAM refresh period is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - DP (printf ("calculated refresh interval %0x\n", sdram_config_reg)); - - /* make sure the refresh value is only 14 bits */ - if (sdram_config_reg > 0x1fff) - sdram_config_reg = 0x1fff; - DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg)); - - /* we want physical bank interleaving and */ - /* virtual bank interleaving enabled so do nothing */ - /* since these bits need to be zero to enable the interleaving */ - - /* registered DRAM ? */ - if (info->registeredAddrAndControlInputs == 1) { - /* it's registered DRAM, so set the reg. DRAM bit */ - sdram_config_reg = sdram_config_reg | BIT17; - DP (printf ("Enabling registered DRAM bit\n")); - } - /* turn on DRAM ECC? */ -#ifdef CONFIG_MV64460_ECC - if (info->errorCheckType == 0x2) { - /* DRAM has ECC, so turn it on */ - sdram_config_reg = sdram_config_reg | BIT18; - DP (printf ("Enabling ECC\n")); - } -#endif - /* set the data DQS pin configuration */ - switch (info->sdramWidth) { - case 0x4: /* memory is x4 */ - sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - DP (printf ("Data DQS pins set for 16 pins\n")); - break; - case 0x8: /* memory is x8 or x16 */ - case 0x10: - sdram_config_reg = sdram_config_reg | BIT21; - DP (printf ("Data DQS pins set for 8 pins\n")); - break; - case 0x20: /* memory is x32 */ - /* both bits are cleared for x32 so nothing to do */ - DP (printf ("Data DQS pins set for 2 pins\n")); - break; - default: /* memory width unsupported */ - printf ("DRAM chip width is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - - /*ronen db64460 */ - /* perform read buffer assignments */ - /* we are going to use the Power-up defaults */ - /* bit 27 = PCI bus #0 = buffer 0 */ - /* bit 28 = PCI bus #1 = buffer 0 */ - /* bit 29 = MPSC = buffer 0 */ - /* bit 30 = IDMA = buffer 0 */ - /* bit 31 = Gigabit = buffer 0 */ - sdram_config_reg = sdram_config_reg | 0x58000000; - sdram_config_reg = sdram_config_reg & 0xffffff00; - /* bit 14 FBSplit = FCRAM controller bsplit enable. */ - /* bit 15 vw = FCRAM Variable write length enable. */ - /* bit 16 DType = Dram Type (0 = FCRAM,1 = Standard) */ - sdram_config_reg = sdram_config_reg | BIT14 | BIT15; - - /* write the value into the SDRAM configuration register */ - GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG))); - - /* SDRAM open pages control keep open as much as I can */ - GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf - ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); - else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); - - /* SDRAM set CAS Latency according to SPD information */ - switch (info->memoryType) { - case SDRAM: - printf ("### SD-RAM not supported !!!\n"); - printf ("Aborting!!!\n"); - hang (); - /* ToDo fill SD-RAM if needed !!!!! */ - break; - /* Calculate the settings for SDRAM mode and Dunit control low registers */ - /* Values set according to technical bulletin TB-92 rev. c */ - case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); - /* ronen db64460 - change the tmp_dunit_control_low setting!!! */ - switch (info->maxClSupported_DDR) { - case DDR_CL_3: - tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x05110051; - else - tmp_dunit_control_low = 0x24110051; - DP (printf - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0xC5000540; - else - tmp_dunit_control_low = 0xC4000540; - DP (printf - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } - break; - case DDR_CL_2_5: - tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x25110051; - else - tmp_dunit_control_low = 0x24110051; - DP (printf - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0xC5000540; - /* printf("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ - /* printf("Aborting!!!\n");1 */ - /* hang();1 */ - } else - tmp_dunit_control_low = 0xC4000540; - DP (printf - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } - break; - case DDR_CL_2: - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x04110051; - else - tmp_dunit_control_low = 0x03110051; - DP (printf - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - /*printf("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ - /*printf("Aborting!!!\n");1 */ - /*hang();1 */ - tmp_dunit_control_low = 0xC4000540; - } else - tmp_dunit_control_low = 0xC3000540;; - DP (printf - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } - break; - case DDR_CL_1_5: - tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x24110051; - else - tmp_dunit_control_low = 0x23110051; - DP (printf - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - /*printf("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ - /*printf("Aborting!!!\n");1 */ - /*hang();1 */ - tmp_dunit_control_low = 0xC4000540; - } else - tmp_dunit_control_low = 0xC3000540; - DP (printf - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } - break; - - default: - printf ("Max. CL is out of range %d\n", - info->maxClSupported_DDR); - hang (); - break; - } /* end DDR switch */ - break; - } /* end CL switch */ - - /* Write results of CL detection procedure */ - /* set SDRAM mode reg. 0x141c */ - GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); - } - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); - } - -/*------------------------------------------------------------------------------ */ - - /* bank parameters */ - /* SDRAM address decode register 0x1410 */ - /* program this with the default value */ - tmp = 0x02; /* power-up default address select decoding value */ - - DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); -/* figure out the DRAM chip size */ - sdram_chip_size = - (1 << (info->numOfRowAddresses + info->numOfColAddresses)); - sdram_chip_size *= info->sdramWidth; - sdram_chip_size *= 4; - DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size)); - /* divide sdram chip size by 64 Mbits */ - sdram_chip_size = sdram_chip_size / 0x4000000; - switch (sdram_chip_size) { - case 1: /* 64 Mbit */ - case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); - tmp |= (0x00 << 4); - break; - case 4: /* 256 Mbit */ - case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); - tmp |= (0x01 << 4); - break; - case 16: /* 1 Gbit */ - case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); - tmp |= (0x02 << 4); - break; - default: - printf ("Error in dram size calculation\n"); - printf ("RAM-Device_size is unsupported\n"); - hang (); - } - - /* SDRAM address control */ - GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - DP (printf - ("setting up sdram address control (0x1410) with: %08lx \n", - tmp)); - -/* ------------------------------------------------------------------------------ */ -/* same settings for registerd & non-registerd DDR SDRAM */ - DP (printf - ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x01501220)); - /*ronen db64460 */ - GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220); - - -/* ------------------------------------------------------------------------------ */ - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIG); - - if (info->registeredAddrAndControlInputs - || info->registeredDQMBinputs) { - tmp |= (1 << 17); - DP (printf - ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", - info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); - } - - /* Use buffer 1 to return read data to the CPU - * Page 426 MV6indent: Standard input:1464: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -4460 */ - tmp |= (1 << 26); - DP (printf - ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf - ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); - - /* SDRAM timing To_do: */ -/* ------------------------------------------------------------------------------ */ - /* ronen db64460 */ - DP (printf - ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0xc)); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc); - - DP (printf - ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a)); - GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - - DP (printf - ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a)); - GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); - -/* ------------------------------------------------------------------------------ */ - - /* set the SDRAM configuration for each bank */ - -/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ - { - i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); - - /* set SDRAM mode */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - check = GTREGREAD (SDRAM_OPERATION); - DP (printf - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); - - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION, 0); - check = GTREGREAD (SDRAM_OPERATION); - DP (printf - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); - - /* unmap the bank */ - memory_map_bank (i, 0, 0); - } - - return 0; - -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -long int dram_size (long int *base, long int maxsize) -{ - volatile long int *addr, *b = base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); - cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr = cnt; /* write cnt to addr */ - *b = 0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr = save1; /* restore *addr */ - *b = save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - val = *addr; /* read *addr */ - - *addr = save1; - *b = save2; - - if (val != cnt) { - DP (printf - ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr)); - /* fix boundary condition.. STARTVAL means zero */ - if (cnt == STARTVAL / sizeof (long)) - cnt = 0; - return (cnt * sizeof (long)); - } - } - return maxsize; -} - -/* ------------------------------------------------------------------------- */ - -/* ppcboot interface function to SDRAM init - this is where all the - * controlling logic happens */ -long int initdram (int board_type) -{ - int s0 = 0, s1 = 0; - int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total, check; - AUX_MEM_DIMM_INFO dimmInfo1; - AUX_MEM_DIMM_INFO dimmInfo2; - int nhr, bank_no; - ulong dest, memSpaceAttr; - - /* first, use the SPD to get info about the SDRAM/ DDRRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0 () & (1 << 16); - - if (nhr) { - printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - s0 = check_dimm (0, &dimmInfo1); - - /* DIMM1 */ - s1 = check_dimm (1, &dimmInfo2); - - memory_map_bank (0, 0, 0); - memory_map_bank (1, 0, 0); - memory_map_bank (2, 0, 0); - memory_map_bank (3, 0, 0); - - /* ronen check correct set of DIMMS */ - if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) { - if (dimmInfo1.errorCheckType != - dimmInfo2.errorCheckType) - printf ("***WARNNING***!!!! different ECC support of the DIMMS\n"); - if (dimmInfo1.maxClSupported_DDR != - dimmInfo2.maxClSupported_DDR) - printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n"); - if (dimmInfo1.registeredAddrAndControlInputs != - dimmInfo2.registeredAddrAndControlInputs) - printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n"); - } - - if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) { - printf ("Setup for DIMM1 failed.\n"); - } - - if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) { - printf ("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0 (get_hid0 () | (1 << 16)); - } - /* next, size the SDRAM banks */ - - realsize = total = 0; - check = GB / 4; - if (dimmInfo1.numOfModuleBanks > 0) { - checkbank[0] = 1; - } - if (dimmInfo1.numOfModuleBanks > 1) { - checkbank[1] = 1; - } - if (dimmInfo1.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM1 has >2 banks\n"); - - printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks); - - if (dimmInfo2.numOfModuleBanks > 0) { - checkbank[2] = 1; - } - if (dimmInfo2.numOfModuleBanks > 1) { - checkbank[3] = 1; - } - if (dimmInfo2.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM2 has >2 banks\n"); - - printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); - - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (!checkbank[bank_no]) - continue; - - /* ronen - realsize = dram_size((long int *)total, check); */ - if (bank_no == 0 || bank_no == 1) { - if (checkbank[1] == 1) - realsize = dimmInfo1.size / 2; - else - realsize = dimmInfo1.size; - } - if (bank_no == 2 || bank_no == 3) { - if (checkbank[3] == 1) - realsize = dimmInfo2.size / 2; - else - realsize = dimmInfo2.size; - } - memory_map_bank (bank_no, total, realsize); - - /* ronen - initialize the DRAM for ECC */ -#ifdef CONFIG_MV64460_ECC - if ((dimmInfo1.errorCheckType != 0) && - ((dimmInfo2.errorCheckType != 0) - || (dimmInfo2.numOfModuleBanks == 0))) { - printf ("ECC Initialization of Bank %d:", bank_no); - memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8; - mvDmaSetMemorySpace (0, 0, memSpaceAttr, total, - realsize); - for (dest = total; dest < total + realsize; - dest += _8M) { - mvDmaTransfer (0, total, dest, _8M, - BIT8 /*DMA_DTL_128BYTES */ | - BIT3 /*DMA_HOLD_SOURCE_ADDR */ - | - BIT11 - /*DMA_BLOCK_TRANSFER_MODE */ ); - while (mvDmaIsChannelActive (0)); - } - printf (" PASS\n"); - } -#endif - - total += realsize; - } - - /* ronen */ - switch ((GTREGREAD (0x141c) >> 4) & 0x7) { - case 0x2: - printf ("CAS Latency = 2"); - break; - case 0x3: - printf ("CAS Latency = 3"); - break; - case 0x5: - printf ("CAS Latency = 1.5"); - break; - case 0x6: - printf ("CAS Latency = 2.5"); - break; - } - printf (" tRP = %d tRAS = %d tRCD=%d\n", - ((GTREGREAD (0x1408) >> 8) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 20) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 4) & 0xf) + 1); - -/* Setup Ethernet DMA Adress window to DRAM Area */ - if (total > _256M) - printf ("*** ONLY the first 256MB DRAM memory are used out of the "); - else - printf ("Total SDRAM memory is "); - /* (cause all the 4 BATS are taken) */ - return (total); -} - - -/* ronen- add Idma functions for usage of the ecc dram init. */ -/******************************************************************************* -* mvDmaIsChannelActive - Checks if a engine is busy. -********************************************************************************/ -int mvDmaIsChannelActive (int engine) -{ - ulong data; - - data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * engine); - if (data & BIT14 /*activity status */ ) { - return 1; - } - return 0; -} - -/******************************************************************************* -* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding -* map. -*******************************************************************************/ -int mvDmaSetMemorySpace (ulong memSpace, - ulong memSpaceTarget, - ulong memSpaceAttr, ulong baseAddress, ulong size) -{ - ulong temp; - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return 0; - } - if (size >= 0x10000 /*64K */ ) { - size &= 0xffff0000; - baseAddress = (baseAddress & 0xffff0000); - /* Set the new attributes */ - GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8), - (size - 1) & 0xffff0000); - temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG); - GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, - (temp & ~(BIT0 << memSpace))); - return 1; - } - return 0; -} - - -/******************************************************************************* -* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4 -* DMA channels. -********************************************************************************/ -int mvDmaTransfer (int engine, ulong sourceAddr, - ulong destAddr, ulong numOfBytes, ulong command) -{ - ulong engOffReg = 0; /* Engine Offset Register */ - - if (numOfBytes > 0xffff) { - command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ; - } - command = command | ((command >> 6) & 0x7); - engOffReg = engine * 4; - GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, - numOfBytes); - GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, - sourceAddr); - GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, - destAddr); - command = - command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9 - /*DMA_NON_CHAIN_MODE */ ; - /* Activate DMA engine By writting to mvDmaControlRegister */ - GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command); - return 1; -} - -/**************************************************************************************** - * SDRAM INIT * - * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * - * This procedure fits only the Atlantis * - * * - ***************************************************************************************/ - - -/**************************************************************************************** - * DFCDL initialize MV643xx Design Considerations * - * * - ***************************************************************************************/ -int set_dfcdlInit (void) -{ - /*ronen the dfcdl init are done by the I2C */ - return (0); -} diff --git a/board/Marvell/db64460/u-boot.lds b/board/Marvell/db64460/u-boot.lds deleted file mode 100644 index d89eb6c..0000000 --- a/board/Marvell/db64460/u-boot.lds +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/74xx_7xx/start.o (.text) - -/* store the environment in a seperate sector in the boot flash */ -/* . = env_offset; */ -/* common/environment.o(.text) */ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/Marvell/include/core.h b/board/Marvell/include/core.h deleted file mode 100644 index 081d5fd..0000000 --- a/board/Marvell/include/core.h +++ /dev/null @@ -1,238 +0,0 @@ -/* Core.h - Basic core logic functions and definitions */ - -/* Copyright Galileo Technology. */ - -/* -DESCRIPTION -This header file contains simple read/write macros for addressing -the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address -space). The macros take care of Big/Little endian conversions. -*/ - -#ifndef __INCcoreh -#define __INCcoreh - -#include "mv_gen_reg.h" - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/****************************************/ -/* GENERAL Definitions */ -/****************************************/ - -#define NO_BIT 0x00000000 -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -#define _1K 0x00000400 -#define _2K 0x00000800 -#define _4K 0x00001000 -#define _8K 0x00002000 -#define _16K 0x00004000 -#define _32K 0x00008000 -#define _64K 0x00010000 -#define _128K 0x00020000 -#define _256K 0x00040000 -#define _512K 0x00080000 - -#define _1M 0x00100000 -#define _2M 0x00200000 -#define _3M 0x00300000 -#define _4M 0x00400000 -#define _5M 0x00500000 -#define _6M 0x00600000 -#define _7M 0x00700000 -#define _8M 0x00800000 -#define _9M 0x00900000 -#define _10M 0x00a00000 -#define _11M 0x00b00000 -#define _12M 0x00c00000 -#define _13M 0x00d00000 -#define _14M 0x00e00000 -#define _15M 0x00f00000 -#define _16M 0x01000000 - -#define _32M 0x02000000 -#define _64M 0x04000000 -#define _128M 0x08000000 -#define _256M 0x10000000 -#define _512M 0x20000000 - -#define _1G 0x40000000 -#define _2G 0x80000000 - -typedef enum _bool{false,true} bool; - -/* Little to Big endian conversion macros */ - -#ifdef LE /* Little Endian */ -#define SHORT_SWAP(X) (X) -#define WORD_SWAP(X) (X) -#define LONG_SWAP(X) ((l64)(X)) - -#else /* Big Endian */ -#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8)) - -#define WORD_SWAP(X) (((X)&0xff)<<24)+ \ - (((X)&0xff00)<<8)+ \ - (((X)&0xff0000)>>8)+ \ - (((X)&0xff000000)>>24) - -#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \ - (((X)&0xff00ULL)<<40)+ \ - (((X)&0xff0000ULL)<<24)+ \ - (((X)&0xff000000ULL)<<8)+ \ - (((X)&0xff00000000ULL)>>8)+ \ - (((X)&0xff0000000000ULL)>>24)+ \ - (((X)&0xff000000000000ULL)>>40)+ \ - (((X)&0xff00000000000000ULL)>>56)) - -#endif - -#ifndef NULL -#define NULL 0 -#endif - -/* Those two definitions were defined to be compatible with MIPS */ -#define NONE_CACHEABLE 0x00000000 -#define CACHEABLE 0x00000000 - -/* 750 cache line */ -#define CACHE_LINE_SIZE 32 -#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1) -#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS) - -/* Read/Write to/from GT`s internal registers */ -#define GT_REG_READ(offset, pData) \ -*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) ) ; \ -*pData = WORD_SWAP(*pData) - -#define GTREGREAD(offset) \ - (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) )) - -#define GT_REG_WRITE(offset, data) \ -*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \ - WORD_SWAP(data) - -/* Write 32/16/8 bit */ -#define WRITE_CHAR(address, data) \ - *((unsigned char *)(address)) = data -#define WRITE_SHORT(address, data) \ - *((unsigned short *)(address)) = data -#define WRITE_WORD(address, data) \ - *((unsigned int *)(address)) = data - -#define GT_WRITE_CHAR(address, data) WRITE_CHAR(address, data) - -/* Write 32/16/8 bit NonCacheable */ -/* -#define GT_WRITE_CHAR(address, data) \ - (*((unsigned char *)NONE_CACHEABLE(address))) = data -#define GT_WRITE_SHORT(address, data) \ - (*((unsigned short *)NONE_CACHEABLE(address))) = data -#define GT_WRITE_WORD(address, data) \ - (*((unsigned int *)NONE_CACHEABLE(address))) = data -*/ - /*#define GT_WRITE_CHAR(address, data) ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */ - - /*#define GT_WRITE_SHORT(address, data) ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */ - - /*#define GT_WRITE_WORD(address, data) ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */ - - -/* Read 32/16/8 bits - returns data in variable. */ -#define READ_CHAR(address, pData) \ - *pData = *((volatile unsigned char *)(address)) - -#define READ_SHORT(address, pData) \ - *pData = *((volatile unsigned short *)(address)) - -#define READ_WORD(address, pData) \ - *pData = *((volatile unsigned int *)(address)) - -/* Read 32/16/8 bit - returns data direct. */ -#define READCHAR(address) \ - *((volatile unsigned char *)((address) | NONE_CACHEABLE)) - -#define READSHORT(address) \ - *((volatile unsigned short *)((address) | NONE_CACHEABLE)) - -#define READWORD(address) \ - *((volatile unsigned int *)((address) | NONE_CACHEABLE)) - -/* Those two Macros were defined to be compatible with MIPS */ -#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff) -#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE) - -/* SET_REG_BITS(regOffset,bits) - - gets register offset and bits: a 32bit value. It set to logic '1' in the - internal register the bits which given as an input example: - SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '1' in register 0x840 while the other bits stays as is. */ -#define SET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ - regOffset) |= (unsigned int)WORD_SWAP(bits) - -/* RESET_REG_BITS(regOffset,bits) - - gets register offset and bits: a 32bit value. It set to logic '0' in the - internal register the bits which given as an input example: - RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '0' in register 0x840 while the other bits stays as is. */ -#define RESET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \ - | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) ) -/* gets register offset and bits: a 32bit value. It set to logic '1' in the - internal register the bits which given as an input example: - GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '1' in register 0x840 while the other bits stays as is. */ - /*#define GT_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */ - /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */ -#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits) -/* gets register offset and bits: a 32bit value. It set to logic '0' in the - internal register the bits which given as an input example: - GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to - logic '0' in register 0x840 while the other bits stays as is. */ - /*#define GT_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */ -#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits) - - -#define DEBUG_LED0_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0) -#define DEBUG_LED1_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0) -#define DEBUG_LED2_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0) -#define DEBUG_LED0_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0) -#define DEBUG_LED1_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0) -#define DEBUG_LED2_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0) - -#endif /* __INCcoreh */ diff --git a/board/Marvell/include/memory.h b/board/Marvell/include/memory.h deleted file mode 100644 index 0947b6e..0000000 --- a/board/Marvell/include/memory.h +++ /dev/null @@ -1,173 +0,0 @@ -/* Memory.h - Memory mappings and remapping functions declarations */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCmemoryh -#define __INCmemoryh - -/* includes */ - -#include "core.h" - -/* defines */ - -#define DONT_MODIFY 0xffffffff -#define PARITY_SUPPORT 0x40000000 -#define MINIMUM_MEM_BANK_SIZE 0x10000 -#define MINIMUM_DEVICE_WINDOW_SIZE 0x10000 -#define MINIMUM_PCI_WINDOW_SIZE 0x10000 -#define MINIMUM_ACCESS_WIN_SIZE 0x10000 - -#define _8BIT 0x00000000 -#define _16BIT 0x00100000 -#define _32BIT 0x00200000 -#define _64BIT 0x00300000 - -/* typedefs */ - - typedef struct deviceParam -{ /* boundary values */ - unsigned int turnOff; /* 0x0 - 0xf */ - unsigned int acc2First; /* 0x0 - 0x1f */ - unsigned int acc2Next; /* 0x0 - 0x1f */ - unsigned int ale2Wr; /* 0x0 - 0xf */ - unsigned int wrLow; /* 0x0 - 0xf */ - unsigned int wrHigh; /* 0x0 - 0xf */ - unsigned int badrSkew; /* 0x0 - 0x2 */ - unsigned int DPEn; /* 0x0 - 0x1 */ - unsigned int deviceWidth; /* in Bytes */ -} DEVICE_PARAM; - - -typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK; -typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE; - -/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \ - MEM_REGION3,MEM_REGION4,MEM_REGION5, \ - MEM_REGION6,MEM_REGION7} \ - MEMORY_PROTECT_REGION;*/ -/* There are four possible windows that can be defined as protected */ -typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2, - MEM_WINDOW3 - } MEMORY_PROTECT_WINDOW; -/* When defining a protected window , this paramter indicates whether it - is accessible or not */ -typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \ - MEMORY_ACCESS; -typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \ - MEMORY_ACCESS_WRITE; -typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \ - MEMORY_CACHE_PROTECT; -typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \ - MEMORY_SNOOP_TYPE; -typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \ - MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \ - MEMORY_SNOOP_REGION; - -/* There are 21 memory windows dedicated for the varios interfaces (PCI, - devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's - address decoding mechanism. */ -typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1, - CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3, - DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5, - DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7, - BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9, - PCI_0_MEM0_WINDOW = BIT10, - PCI_0_MEM1_WINDOW = BIT11, - PCI_0_MEM2_WINDOW = BIT12, - PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14, - PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16, - PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18, - INTEGRATED_SRAM_WINDOW = BIT19, - INTERNAL_SPACE_WINDOW = BIT20, - ALL_WINDOWS = 0X1FFFFF - } MEMORY_WINDOW; - -typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED - } MEMORY_WINDOW_STATUS; - - -typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3 -#ifdef INCLUDE_PCI_1 - ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3 -#endif /* INCLUDE_PCI_1 */ - } PCI_MEM_WINDOW; - - -/* -------------------------------------------------------------------------------------------------*/ - -/* functions */ -unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank); -unsigned int memoryGetDeviceBaseAddress(DEVICE device); -/* New at MV6436x */ -unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow); -unsigned int memoryGetBankSize(MEMORY_BANK bank); -unsigned int memoryGetDeviceSize(DEVICE device); -unsigned int memoryGetDeviceWidth(DEVICE device); -/* New at MV6436x */ -unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow); - -/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/ -bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength); -/* Set a new base and size for one of the memory banks (CS0 - CS3) */ -bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase, - unsigned int bankSize); -bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength); - -/* Change the Internal Register Base Address to a new given Address. */ -bool memoryMapInternalRegistersSpace(unsigned int internalRegBase); -/* returns internal Register Space Base Address. */ -unsigned int memoryGetInternalRegistersSpace(void); - -/* Returns the integrated SRAM Base Address. */ -unsigned int memoryGetInternalSramBaseAddr(void); -/* -------------------------------------------------------------------------------------------------*/ - -/* Set new base address for the integrated SRAM. */ -void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress); -/* -------------------------------------------------------------------------------------------------*/ - -/* Delete a protection feature to a given space. */ -void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window); -/* -------------------------------------------------------------------------------------------------*/ - -/* Writes a new remap value to the remap register */ -unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow, - unsigned int remapValueHigh, - unsigned int remapValueLow); -/* -------------------------------------------------------------------------------------------------*/ - -/* Configurate the protection feature to a given space. */ -bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window, - MEMORY_ACCESS gtMemoryAccess, - MEMORY_ACCESS_WRITE gtMemoryWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int size); - -/* Configurate the protection feature to a given space. */ -/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, - MEMORY_ACCESS memoryAccess, - MEMORY_ACCESS_WRITE memoryWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int regionLength); */ -/* Configurate the snoop feature to a given space. */ -bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, - MEMORY_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); - -bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue); -bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); -bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); -/* Set a new base and size for one of the PCI windows. */ -bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase, - unsigned int pciWindowSize); - -/* Disable or enable one of the 21 windows dedicated for the CPU's - address decoding mechanism */ -void MemoryDisableWindow(MEMORY_WINDOW window); -void MemoryEnableWindow (MEMORY_WINDOW window); -MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window); -#endif /* __INCmemoryh */ diff --git a/board/Marvell/include/mv_gen_reg.h b/board/Marvell/include/mv_gen_reg.h deleted file mode 100644 index 5e4f076..0000000 --- a/board/Marvell/include/mv_gen_reg.h +++ /dev/null @@ -1,2288 +0,0 @@ -/* mv_gen_reg.h - Internal registers definition file */ -/* Copyright - Galileo technology. */ - - -/******************************************************************************* -* Copyright 2002, GALILEO TECHNOLOGY, LTD. * -* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -* * -* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI). * -******************************************************************************** -* mv_gen_reg.h - Marvell 64360 and 64460 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_gen_regh -#define __INCmv_gen_regh - - -/* Supported by the Atlantis */ -#define INCLUDE_PCI_1 -#define INCLUDE_PCI_0_ARBITER -#define INCLUDE_PCI_1_ARBITER -#define INCLUDE_SNOOP_SUPPORT -#define INCLUDE_P2P -#define INCLUDE_ETH_PORT_2 -#define INCLUDE_CPU_MAPPING -#define INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - - -/****************************************/ -/* Processor Address Space */ -/****************************************/ -/* DDR SDRAM BAR and size registers */ - -/* Sdram's BAR'S */ -#define SCS_0_LOW_DECODE_ADDRESS 0x008 -#define SCS_0_HIGH_DECODE_ADDRESS 0x010 -#define SCS_1_LOW_DECODE_ADDRESS 0x208 -#define SCS_1_HIGH_DECODE_ADDRESS 0x210 -#define SCS_2_LOW_DECODE_ADDRESS 0x018 -#define SCS_2_HIGH_DECODE_ADDRESS 0x020 -#define SCS_3_LOW_DECODE_ADDRESS 0x218 -#define SCS_3_HIGH_DECODE_ADDRESS 0x220 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -#define CS_0_BASE_ADDR SCS_0_LOW_DECODE_ADDRESS -#define CS_0_SIZE SCS_0_HIGH_DECODE_ADDRESS -#define CS_1_BASE_ADDR SCS_1_LOW_DECODE_ADDRESS -#define CS_1_SIZE SCS_1_HIGH_DECODE_ADDRESS -#define CS_2_BASE_ADDR SCS_2_LOW_DECODE_ADDRESS -#define CS_2_SIZE SCS_2_HIGH_DECODE_ADDRESS -#define CS_3_BASE_ADDR SCS_3_LOW_DECODE_ADDRESS -#define CS_3_SIZE SCS_3_HIGH_DECODE_ADDRESS - -/* Devices BAR'S */ -#define CS_0_LOW_DECODE_ADDRESS 0x028 -#define CS_0_HIGH_DECODE_ADDRESS 0x030 -#define CS_1_LOW_DECODE_ADDRESS 0x228 -#define CS_1_HIGH_DECODE_ADDRESS 0x230 -#define CS_2_LOW_DECODE_ADDRESS 0x248 -#define CS_2_HIGH_DECODE_ADDRESS 0x250 -#define CS_3_LOW_DECODE_ADDRESS 0x038 -#define CS_3_HIGH_DECODE_ADDRESS 0x040 -#define BOOTCS_LOW_DECODE_ADDRESS 0x238 -#define BOOTCS_HIGH_DECODE_ADDRESS 0x240 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -/* Devices BAR and size registers */ - -#define DEV_CS0_BASE_ADDR CS_0_LOW_DECODE_ADDRESS -#define DEV_CS0_SIZE CS_0_HIGH_DECODE_ADDRESS -#define DEV_CS1_BASE_ADDR CS_1_LOW_DECODE_ADDRESS -#define DEV_CS1_SIZE CS_1_HIGH_DECODE_ADDRESS -#define DEV_CS2_BASE_ADDR CS_2_LOW_DECODE_ADDRESS -#define DEV_CS2_SIZE CS_2_HIGH_DECODE_ADDRESS -#define DEV_CS3_BASE_ADDR CS_3_LOW_DECODE_ADDRESS -#define DEV_CS3_SIZE CS_3_HIGH_DECODE_ADDRESS -#define BOOTCS_BASE_ADDR BOOTCS_LOW_DECODE_ADDRESS -#define BOOTCS_SIZE BOOTCS_HIGH_DECODE_ADDRESS - -/* PCI 0 BAR and size registers old names of evb64260*/ - -#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 -#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 -#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 -#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 -#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 -#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 -#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 -#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 -#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 -#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -#define PCI_0_IO_BASE_ADDR 0x048 -#define PCI_0_IO_SIZE 0x050 -#define PCI_0_MEMORY0_BASE_ADDR 0x058 -#define PCI_0_MEMORY0_SIZE 0x060 -#define PCI_0_MEMORY1_BASE_ADDR 0x080 -#define PCI_0_MEMORY1_SIZE 0x088 -#define PCI_0_MEMORY2_BASE_ADDR 0x258 -#define PCI_0_MEMORY2_SIZE 0x260 -#define PCI_0_MEMORY3_BASE_ADDR 0x280 -#define PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers old names of evb64260*/ -#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 -#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 -#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 -#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 -#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 -#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 -#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 -#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 -#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 -#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -#define PCI_1_IO_BASE_ADDR 0x090 -#define PCI_1_IO_SIZE 0x098 -#define PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define PCI_1_MEMORY0_SIZE 0x0a8 -#define PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define PCI_1_MEMORY1_SIZE 0x0b8 -#define PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define PCI_1_MEMORY2_SIZE 0x2a8 -#define PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define PCI_1_MEMORY3_SIZE 0x2b8 - -/* internal registers space base address */ -#define INTERNAL_SPACE_DECODE 0x068 -#define INTERNAL_SPACE_BASE_ADDR INTERNAL_SPACE_DECODE - -/* SRAM base address */ -#define INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define BASE_ADDR_ENABLE 0x278 - - -#define CPU_0_LOW_DECODE_ADDRESS 0x290 -#define CPU_0_HIGH_DECODE_ADDRESS 0x298 -#define CPU_1_LOW_DECODE_ADDRESS 0x2c0 -#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ -/*****************************************************************************************/ - /* PCI 0 */ -/* old fashion evb 64260 */ -#define PCI_0I_O_ADDRESS_REMAP 0x0f0 -#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 -#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 -#define PCI_0MEMORY1_ADDRESS_REMAP 0x100 -#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 -#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 -#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 -#define PCI_0MEMORY3_ADDRESS_REMAP 0x300 -#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 - -#define PCI_0_IO_ADDR_REMAP PCI_0I_O_ADDRESS_REMAP -#define PCI_0_MEMORY0_LOW_ADDR_REMAP PCI_0MEMORY0_ADDRESS_REMAP -#define PCI_0_MEMORY0_HIGH_ADDR_REMAP PCI_0MEMORY0_HIGH_ADDRESS_REMAP -#define PCI_0_MEMORY1_LOW_ADDR_REMAP PCI_0MEMORY1_ADDRESS_REMAP -#define PCI_0_MEMORY1_HIGH_ADDR_REMAP PCI_0MEMORY1_HIGH_ADDRESS_REMAP -#define PCI_0_MEMORY2_LOW_ADDR_REMAP PCI_0MEMORY2_ADDRESS_REMAP -#define PCI_0_MEMORY2_HIGH_ADDR_REMAP PCI_0MEMORY2_HIGH_ADDRESS_REMAP -#define PCI_0_MEMORY3_LOW_ADDR_REMAP PCI_0MEMORY3_ADDRESS_REMAP -#define PCI_0_MEMORY3_HIGH_ADDR_REMAP PCI_0MEMORY3_HIGH_ADDRESS_REMAP - - /* PCI 1 */ -/* old fashion evb 64260 */ -#define PCI_1I_O_ADDRESS_REMAP 0x108 -#define PCI_1MEMORY0_ADDRESS_REMAP 0x110 -#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 -#define PCI_1MEMORY1_ADDRESS_REMAP 0x118 -#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 -#define PCI_1MEMORY2_ADDRESS_REMAP 0x310 -#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 -#define PCI_1MEMORY3_ADDRESS_REMAP 0x318 -#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 - -#define PCI_1_IO_ADDR_REMAP PCI_1I_O_ADDRESS_REMAP -#define PCI_1_MEMORY0_LOW_ADDR_REMAP PCI_1MEMORY0_ADDRESS_REMAP -#define PCI_1_MEMORY0_HIGH_ADDR_REMAP PCI_1MEMORY0_HIGH_ADDRESS_REMAP -#define PCI_1_MEMORY1_LOW_ADDR_REMAP PCI_1MEMORY1_ADDRESS_REMAP -#define PCI_1_MEMORY1_HIGH_ADDR_REMAP PCI_1MEMORY1_HIGH_ADDRESS_REMAP -#define PCI_1_MEMORY2_LOW_ADDR_REMAP PCI_1MEMORY2_ADDRESS_REMAP -#define PCI_1_MEMORY2_HIGH_ADDR_REMAP PCI_1MEMORY2_HIGH_ADDRESS_REMAP -#define PCI_1_MEMORY3_LOW_ADDR_REMAP PCI_1MEMORY3_ADDRESS_REMAP -#define PCI_1_MEMORY3_HIGH_ADDR_REMAP PCI_1MEMORY3_HIGH_ADDRESS_REMAP - -/* old fashion evb 64260 */ -#define CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define CPU_GE_HEADERS_RETARGET_BASE 0x3d8 - -/* MV64360 and MV64460 no changes needed*/ -/*****************************************************************************************/ - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ -/* CPU MASTER CONTROL REGISTER */ -#define CPU_CONFIGURATION 0x000 -#define CPU_MASTER_CONTROL 0x160 - -#define CPU_CONFIG 0x000 -#define CPU_MODE 0x120 -#define CPU_MASTER_CONTROL 0x160 -/* new in MV64360 and MV64460 */ -#define CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define SMP_WHO_AM_I 0x200 -#define SMP_CPU0_DOORBELL 0x214 -#define SMP_CPU0_DOORBELL_CLEAR 0x21C -#define SMP_CPU1_DOORBELL 0x224 -#define SMP_CPU1_DOORBELL_CLEAR 0x22C -#define SMP_CPU0_DOORBELL_MASK 0x234 -#define SMP_CPU1_DOORBELL_MASK 0x23C -#define SMP_SEMAPHOR0 0x244 -#define SMP_SEMAPHOR1 0x24c -#define SMP_SEMAPHOR2 0x254 -#define SMP_SEMAPHOR3 0x25c -#define SMP_SEMAPHOR4 0x264 -#define SMP_SEMAPHOR5 0x26c -#define SMP_SEMAPHOR6 0x274 -#define SMP_SEMAPHOR7 0x27c - - -/****************************************/ -/* CPU Sync Barrier */ -/****************************************/ -#define CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define CPU_LOW_PROTECT_ADDRESS_0 0x180 -#define CPU_HIGH_PROTECT_ADDRESS_0 0x188 -#define CPU_LOW_PROTECT_ADDRESS_1 0x190 -#define CPU_HIGH_PROTECT_ADDRESS_1 0x198 -#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0 -#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8 -#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0 -#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8 -/*#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0 -#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8 -#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0 -#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8 -#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0 -#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8 -#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0 -#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8 -*/ - -#define CPU_PROTECT_WINDOW_0_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_0 /* 0x180 */ -#define CPU_PROTECT_WINDOW_0_SIZE CPU_HIGH_PROTECT_ADDRESS_0 /* 0x188 */ -#define CPU_PROTECT_WINDOW_1_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_1 /* 0x190 */ -#define CPU_PROTECT_WINDOW_1_SIZE CPU_HIGH_PROTECT_ADDRESS_1 /* 0x198 */ -#define CPU_PROTECT_WINDOW_2_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_2 /*0x1a0 */ -#define CPU_PROTECT_WINDOW_2_SIZE CPU_HIGH_PROTECT_ADDRESS_2 /* 0x1a8 */ -#define CPU_PROTECT_WINDOW_3_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_3 /* 0x1b0 */ -#define CPU_PROTECT_WINDOW_3_SIZE CPU_HIGH_PROTECT_ADDRESS_3 /* 0x1b8 */ - - -/****************************************/ -/* Snoop Control */ -/****************************************/ - -/*#define SNOOP_BASE_ADDRESS_0 0x380 -#define SNOOP_TOP_ADDRESS_0 0x388 -#define SNOOP_BASE_ADDRESS_1 0x390 -#define SNOOP_TOP_ADDRESS_1 0x398 -#define SNOOP_BASE_ADDRESS_2 0x3a0 -#define SNOOP_TOP_ADDRESS_2 0x3a8 -#define SNOOP_BASE_ADDRESS_3 0x3b0 -#define SNOOP_TOP_ADDRESS_3 0x3b8 -*/ - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define SRAM_CONFIG 0x380 -#define SRAM_TEST_MODE 0x3F4 -#define SRAM_ERROR_CAUSE 0x388 -#define SRAM_ERROR_ADDR 0x390 -#define SRAM_ERROR_ADDR_HIGH 0x3F8 -#define SRAM_ERROR_DATA_LOW 0x398 -#define SRAM_ERROR_DATA_HIGH 0x3a0 -#define SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define CPU_ERROR_ADDRESS_LOW 0x070 -#define CPU_ERROR_ADDRESS_HIGH 0x078 -#define CPU_ERROR_DATA_LOW 0x128 -#define CPU_ERROR_DATA_HIGH 0x130 -#define CPU_ERROR_PARITY 0x138 -#define CPU_ERROR_CAUSE 0x140 -#define CPU_ERROR_MASK 0x148 - -#define CPU_ERROR_ADDR_LOW CPU_ERROR_ADDRESS_LOW /* 0x0701 */ -#define CPU_ERROR_ADDR_HIGH CPU_ERROR_ADDRESS_HIGH /* 0x0781 */ - -/****************************************/ -/* Pslave Debug */ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define X_0_ADDRESS 0x360 -#define X_0_COMMAND_ID 0x368 -#define X_1_ADDRESS 0x370 -#define X_1_COMMAND_ID 0x378 - /*#define WRITE_DATA_LOW 0x3c01 */ - /*#define WRITE_DATA_HIGH 0x3c81 */ - /*#define WRITE_BYTE_ENABLE 0x3e01 */ - /*#define READ_DATA_LOW 0x3d01 */ - /*#define READ_DATA_HIGH 0x3d81 */ - /*#define READ_ID 0x3e81 */ - -#define PUNIT_SLAVE_DEBUG_LOW X_0_ADDRESS /* 0x3601 */ -#define PUNIT_SLAVE_DEBUG_HIGH X_0_COMMAND_ID /* 0x3681 */ -#define PUNIT_MASTER_DEBUG_LOW X_1_ADDRESS /* 0x3701 */ -#define PUNIT_MASTER_DEBUG_HIGH X_1_COMMAND_ID /* 0x3781 */ -#define PUNIT_MMASK 0x3e4 - - -/****************************************/ -/* SDRAM and Device Address Space */ -/****************************************/ - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ -#define SDRAM_CONFIG 0x1400 /* MV64260 0x448 some changes*/ -#define D_UNIT_CONTROL_LOW 0x1404 /* NEW in MV64360 and MV64460 */ -#define D_UNIT_CONTROL_HIGH 0x1424 /* NEW in MV64360 and MV64460 */ -#define SDRAM_TIMING_CONTROL_LOW 0x1408 /* MV64260 0x4b4 new SDRAM TIMING REGISTER */ -#define SDRAM_TIMING_CONTROL_HIGH 0x140c /* MV64260 0x4b4 new SDRAM TIMING REGISTER */ -#define SDRAM_ADDR_CONTROL 0x1410 /* MV64260 0x47c some changes*/ -#define SDRAM_OPEN_PAGES_CONTROL 0x1414 /* NEW in MV64360 and MV64460 */ -#define SDRAM_OPERATION 0x1418 /* MV64260 0x474 some changes*/ -#define SDRAM_MODE 0x141c /* NEW in MV64360 and MV64460 */ -#define EXTENDED_DRAM_MODE 0x1420 /* NEW in MV64360 and MV64460 */ -#define SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 /* MV64260 0x4a8 NO changes*/ -#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 /* MV64260 0x4ac NO changes*/ -#define SDRAM_CROSS_BAR_TIMEOUT 0x1438 /* MV64260 0x4b0 NO changes*/ -#define SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 /* what is this ??? */ -#define SDRAM_DATA_PADS_CALIBRATION 0x14c4 /* what is this ??? */ -/****************************************/ -/* SDRAM Configuration MV64260 */ -/****************************************/ - /*#define SDRAM_CONFIGURATION 0x4481 */ - /*#define SDRAM_OPERATION_MODE 0x4741 */ - /*#define SDRAM_ADDRESS_DECODE 0x47c1 */ - /*#define SDRAM_UMA_CONTROL 0x4a4 eliminated in MV64360 and MV64460 */ - /*#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a81 */ - /*#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac1 */ - /*#define SDRAM_CROSS_BAR_TIMEOUT 0x4b01 */ - /*#define SDRAM_TIMING 0x4b41 */ - - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ -#define SDRAM_ERROR_DATA_LOW 0x1444 /* MV64260 0x484 NO changes*/ -#define SDRAM_ERROR_DATA_HIGH 0x1440 /* MV64260 0x480 NO changes*/ -#define SDRAM_ERROR_ADDR 0x1450 /* MV64260 0x490 NO changes*/ -#define SDRAM_RECEIVED_ECC 0x1448 /* MV64260 0x488 NO changes*/ -#define SDRAM_CALCULATED_ECC 0x144c /* MV64260 0x48c NO changes*/ -#define SDRAM_ECC_CONTROL 0x1454 /* MV64260 0x494 NO changes*/ -#define SDRAM_ECC_ERROR_COUNTER 0x1458 /* MV64260 0x498 NO changes*/ -#define SDRAM_MMASK 0x1B40 /* NEW Register in MV64360 and MV64460 DO NOT USE !!!*/ -/****************************************/ -/* SDRAM Error Report MV64260 */ -/****************************************/ - /*#define SDRAM_ERROR_DATA_LOW 0x4841 */ - /*#define SDRAM_ERROR_DATA_HIGH 0x4801 */ - /*#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x4901 */ - /*#define SDRAM_RECEIVED_ECC 0x4881 */ - /*#define SDRAM_CALCULATED_ECC 0x48c1 */ - /*#define SDRAM_ECC_CONTROL 0x4941 */ - /*#define SDRAM_ECC_ERROR_COUNTER 0x4981 */ - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ -#define DFCDL_CONFIG0 0x1480 -#define DFCDL_CONFIG1 0x1484 -#define DLL_WRITE 0x1488 -#define DLL_READ 0x148c -#define SRAM_ADDR 0x1490 -#define SRAM_DATA0 0x1494 -#define SRAM_DATA1 0x1498 -#define SRAM_DATA2 0x149c -#define DFCL_PROBE 0x14a0 - - -/****************************************/ -/* SDRAM Parameters only in MV64260 */ -/****************************************/ - - /*#define SDRAM_BANK0PARAMETERS 0x44C eliminated in MV64360 and MV64460 */ - /*#define SDRAM_BANK1PARAMETERS 0x450 eliminated in MV64360 and MV64460 */ - /*#define SDRAM_BANK2PARAMETERS 0x454 eliminated in MV64360 and MV64460 */ - /*#define SDRAM_BANK3PARAMETERS 0x458 eliminated in MV64360 and MV64460 */ - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define DUNIT_DEBUG_LOW 0x1460 -#define DUNIT_DEBUG_HIGH 0x1464 -#define DUNIT_MMASK 0x1b40 - -/****************************************/ -/* SDunit Debug (for internal use) */ -/****************************************/ - -#define X0_ADDRESS 0x500 -#define X0_COMMAND_AND_ID 0x504 -#define X0_WRITE_DATA_LOW 0x508 -#define X0_WRITE_DATA_HIGH 0x50c -#define X0_WRITE_BYTE_ENABLE 0x518 -#define X0_READ_DATA_LOW 0x510 -#define X0_READ_DATA_HIGH 0x514 -#define X0_READ_ID 0x51c -#define X1_ADDRESS 0x520 -#define X1_COMMAND_AND_ID 0x524 -#define X1_WRITE_DATA_LOW 0x528 -#define X1_WRITE_DATA_HIGH 0x52c -#define X1_WRITE_BYTE_ENABLE 0x538 -#define X1_READ_DATA_LOW 0x530 -#define X1_READ_DATA_HIGH 0x534 -#define X1_READ_ID 0x53c -#define X0_SNOOP_ADDRESS 0x540 -#define X0_SNOOP_COMMAND 0x544 -#define X1_SNOOP_ADDRESS 0x548 -#define X1_SNOOP_COMMAND 0x54c - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define DEVICE_BANK0PARAMETERS 0x45c -#define DEVICE_BANK1PARAMETERS 0x460 -#define DEVICE_BANK2PARAMETERS 0x464 -#define DEVICE_BANK3PARAMETERS 0x468 -#define DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define DEVICE_CONTROL 0x4c0 -#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define DEVICE_BANK0_PARAMETERS DEVICE_BANK0PARAMETERS /* 0x45c1 */ -#define DEVICE_BANK1_PARAMETERS DEVICE_BANK1PARAMETERS /* 0x4601 */ -#define DEVICE_BANK2_PARAMETERS DEVICE_BANK2PARAMETERS /* 0x4641 */ -#define DEVICE_BANK3_PARAMETERS DEVICE_BANK3PARAMETERS /* 0x4681 */ -/*#define DEVICE_BOOT_BANK_PARAMETERS 0x46c1 */ -#define DEVICE_INTERFACE_CONTROL DEVICE_CONTROL /* 0x4c01 */ -#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW DEVICE_CROSS_BAR_CONTROL_LOW /* 0x4c81 */ -#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH DEVICE_CROSS_BAR_CONTROL_HIGH /* 0x4cc1 */ -#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT DEVICE_CROSS_BAR_TIMEOUT /* 0x4c41 */ - - -/****************************************/ -/* Device Interrupt */ -/****************************************/ - -#define DEVICE_INTERRUPT_CAUSE 0x4d0 -#define DEVICE_INTERRUPT_MASK 0x4d4 -#define DEVICE_ERROR_ADDRESS 0x4d8 - /*#define DEVICE_INTERRUPT_CAUSE 0x4d01 */ - /*#define DEVICE_INTERRUPT_MASK 0x4d41 */ -#define DEVICE_ERROR_ADDR DEVICE_ERROR_ADDRESS /*0x4d81 */ -#define DEVICE_ERROR_DATA 0x4dc -#define DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define DEVICE_DEBUG_LOW 0x4e4 -#define DEVICE_DEBUG_HIGH 0x4e8 -#define RUNIT_MMASK 0x4f0 - -/****************************************/ -/* DMA Record */ -/****************************************/ - - /*#define CHANNEL4_DMA_BYTE_COUNT 0x9001 */ - /*#define CHANNEL5_DMA_BYTE_COUNT 0x9041 */ - /*#define CHANNEL6_DMA_BYTE_COUNT 0x9081 */ - /*#define CHANNEL7_DMA_BYTE_COUNT 0x90C1 */ - /*#define CHANNEL4_DMA_SOURCE_ADDRESS 0x9101 */ - /*#define CHANNEL5_DMA_SOURCE_ADDRESS 0x9141 */ - /*#define CHANNEL6_DMA_SOURCE_ADDRESS 0x9181 */ - /*#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C1 */ - /*#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x9201 */ - /*#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x9241 */ - /*#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x9281 */ - /*#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C1 */ - /*#define CHANNEL4NEXT_RECORD_POINTER 0x9301 */ - /*#define CHANNEL5NEXT_RECORD_POINTER 0x9341 */ - /*#define CHANNEL6NEXT_RECORD_POINTER 0x9381 */ - /*#define CHANNEL7NEXT_RECORD_POINTER 0x93C1 */ - /*#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x9701 */ - /*#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x9741 */ - /*#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x9781 */ - /*#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C1 */ - /*#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8901 */ - /*#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8941 */ - /*#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8981 */ - /*#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c1 */ - /*#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9901 */ - /*#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9941 */ - /*#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9981 */ - /*#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c1 */ - /*#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a01 */ - /*#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a41 */ - /*#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a81 */ - /*#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac1 */ - /*#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a01 */ - /*#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a41 */ - /*#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a81 */ - /*#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac1 */ - /*#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b01 */ - /*#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b41 */ - /*#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b81 */ - /*#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc1 */ - /*#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b01 */ - /*#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b41 */ - /*#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b81 */ - /*#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc1 */ - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define CHANNEL0CONTROL 0x840 -#define CHANNEL0CONTROL_HIGH 0x880 -#define CHANNEL1CONTROL 0x844 -#define CHANNEL1CONTROL_HIGH 0x884 -#define CHANNEL2CONTROL 0x848 -#define CHANNEL2CONTROL_HIGH 0x888 -#define CHANNEL3CONTROL 0x84C -#define CHANNEL3CONTROL_HIGH 0x88C - -#define DMA_CHANNEL0_CONTROL CHANNEL0CONTROL /*0x8401 */ -#define DMA_CHANNEL0_CONTROL_HIGH CHANNEL0CONTROL_HIGH /*0x8801 */ -#define DMA_CHANNEL1_CONTROL CHANNEL1CONTROL /* 0x8441 */ -#define DMA_CHANNEL1_CONTROL_HIGH CHANNEL1CONTROL_HIGH /*0x8841 */ -#define DMA_CHANNEL2_CONTROL CHANNEL2CONTROL /*0x8481 */ -#define DMA_CHANNEL2_CONTROL_HIGH CHANNEL2CONTROL_HIGH /*0x8881 */ -#define DMA_CHANNEL3_CONTROL CHANNEL3CONTROL /*0x84C1 */ -#define DMA_CHANNEL3_CONTROL_HIGH CHANNEL3CONTROL_HIGH /*0x88C1 */ - - /*#define CHANNEL4CONTROL 0x9401 */ - /*#define CHANNEL4CONTROL_HIGH 0x9801 */ - /*#define CHANNEL5CONTROL 0x9441 */ - /*#define CHANNEL5CONTROL_HIGH 0x9841 */ - /*#define CHANNEL6CONTROL 0x9481 */ - /*#define CHANNEL6CONTROL_HIGH 0x9881 */ - /*#define CHANNEL7CONTROL 0x94C1 */ - /*#define CHANNEL7CONTROL_HIGH 0x98C1 */ - - -/****************************************/ -/* DMA Arbiter */ -/****************************************/ - - /*#define ARBITER_CONTROL_0_3 0x8601 */ -#define ARBITER_CONTROL_4_7 0x960 -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define DMA_CHANNEL0_BYTE_COUNT CHANNEL0_DMA_BYTE_COUNT /*0x8001 */ -#define DMA_CHANNEL1_BYTE_COUNT CHANNEL1_DMA_BYTE_COUNT /*0x8041 */ -#define DMA_CHANNEL2_BYTE_COUNT CHANNEL2_DMA_BYTE_COUNT /*0x8081 */ -#define DMA_CHANNEL3_BYTE_COUNT CHANNEL3_DMA_BYTE_COUNT /*0x80C1 */ -#define DMA_CHANNEL0_SOURCE_ADDR CHANNEL0_DMA_SOURCE_ADDRESS /*0x8101 */ -#define DMA_CHANNEL1_SOURCE_ADDR CHANNEL1_DMA_SOURCE_ADDRESS /*0x8141 */ -#define DMA_CHANNEL2_SOURCE_ADDR CHANNEL2_DMA_SOURCE_ADDRESS /*0x8181 */ -#define DMA_CHANNEL3_SOURCE_ADDR CHANNEL3_DMA_SOURCE_ADDRESS /*0x81c1 */ -#define DMA_CHANNEL0_DESTINATION_ADDR CHANNEL0_DMA_DESTINATION_ADDRESS /*0x8201 */ -#define DMA_CHANNEL1_DESTINATION_ADDR CHANNEL1_DMA_DESTINATION_ADDRESS /*0x8241 */ -#define DMA_CHANNEL2_DESTINATION_ADDR CHANNEL2_DMA_DESTINATION_ADDRESS /*0x8281 */ -#define DMA_CHANNEL3_DESTINATION_ADDR CHANNEL3_DMA_DESTINATION_ADDRESS /*0x82C1 */ -#define DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER CHANNEL0NEXT_RECORD_POINTER /*0x8301 */ -#define DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER CHANNEL1NEXT_RECORD_POINTER /*0x8341 */ -#define DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER CHANNEL2NEXT_RECORD_POINTER /*0x8381 */ -#define DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER CHANNEL3NEXT_RECORD_POINTER /*0x83C1 */ -#define DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER CHANNEL0CURRENT_DESCRIPTOR_POINTER /*0x8701 */ -#define DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER CHANNEL1CURRENT_DESCRIPTOR_POINTER /*0x8741 */ -#define DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER CHANNEL2CURRENT_DESCRIPTOR_POINTER /*0x8781 */ -#define DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER CHANNEL3CURRENT_DESCRIPTOR_POINTER /*0x87C1 */ - -#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C -#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 -#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 -#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 -#define CHANNEL0NEXT_RECORD_POINTER 0x830 -#define CHANNEL1NEXT_RECORD_POINTER 0x834 -#define CHANNEL2NEXT_RECORD_POINTER 0x838 -#define CHANNEL3NEXT_RECORD_POINTER 0x83C -#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 -#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 -#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 -#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C -#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 -#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 -#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 -#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C -#define CHANNEL0_DMA_BYTE_COUNT 0x800 -#define CHANNEL1_DMA_BYTE_COUNT 0x804 -#define CHANNEL2_DMA_BYTE_COUNT 0x808 -#define CHANNEL3_DMA_BYTE_COUNT 0x80C - - /* IDMA Address Decoding Base Address Registers */ - -#define DMA_BASE_ADDR_REG0 0xa00 -#define DMA_BASE_ADDR_REG1 0xa08 -#define DMA_BASE_ADDR_REG2 0xa10 -#define DMA_BASE_ADDR_REG3 0xa18 -#define DMA_BASE_ADDR_REG4 0xa20 -#define DMA_BASE_ADDR_REG5 0xa28 -#define DMA_BASE_ADDR_REG6 0xa30 -#define DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define DMA_SIZE_REG0 0xa04 -#define DMA_SIZE_REG1 0xa0c -#define DMA_SIZE_REG2 0xa14 -#define DMA_SIZE_REG3 0xa1c -#define DMA_SIZE_REG4 0xa24 -#define DMA_SIZE_REG5 0xa2c -#define DMA_SIZE_REG6 0xa34 -#define DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define DMA_ARBITER_CONTROL 0x860 -#define DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - - /*#define CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e01 */ - /*#define CPU_IDMA_HEADERS_RETARGET_BASE 0x3e81 */ - -#define DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define DMA_HEADERS_RETARGET_BASE 0xa88 - -/****************************************/ -/* DMA Interrupt */ -/****************************************/ - -#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 -#define CHANELS0_3_INTERRUPT_MASK 0x8c4 -#define CHANELS0_3_ERROR_ADDRESS 0x8c8 -#define CHANELS0_3_ERROR_SELECT 0x8cc - /*#define CHANELS4_7_INTERRUPT_CAUSE 0x9c01 */ - /*#define CHANELS4_7_INTERRUPT_MASK 0x9c41 */ - /*#define CHANELS4_7_ERROR_ADDRESS 0x9c81 */ - /*#define CHANELS4_7_ERROR_SELECT 0x9cc1 */ - -#define DMA_INTERRUPT_CAUSE_REG CHANELS0_3_INTERRUPT_CAUSE /*0x8c01 */ -#define DMA_INTERRUPT_CAUSE_MASK CHANELS0_3_INTERRUPT_MASK /*0x8c41 */ -#define DMA_ERROR_ADDR CHANELS0_3_ERROR_ADDRESS /*0x8c81 */ -#define DMA_ERROR_SELECT CHANELS0_3_ERROR_SELECT /*0x8cc1 */ - - -/****************************************/ -/* DMA Debug (for internal use) */ -/****************************************/ - -#define DMA_X0_ADDRESS 0x8e0 -#define DMA_X0_COMMAND_AND_ID 0x8e4 - /*#define DMA_X0_WRITE_DATA_LOW 0x8e81 */ - /*#define DMA_X0_WRITE_DATA_HIGH 0x8ec1 */ - /*#define DMA_X0_WRITE_BYTE_ENABLE 0x8f81 */ - /*#define DMA_X0_READ_DATA_LOW 0x8f01 */ - /*#define DMA_X0_READ_DATA_HIGH 0x8f41 */ - /*#define DMA_X0_READ_ID 0x8fc1 */ - /*#define DMA_X1_ADDRESS 0x9e01 */ - /*#define DMA_X1_COMMAND_AND_ID 0x9e41 */ - /*#define DMA_X1_WRITE_DATA_LOW 0x9e81 */ - /*#define DMA_X1_WRITE_DATA_HIGH 0x9ec1 */ - /*#define DMA_X1_WRITE_BYTE_ENABLE 0x9f81 */ - /*#define DMA_X1_READ_DATA_LOW 0x9f01 */ - /*#define DMA_X1_READ_DATA_HIGH 0x9f41 */ - /*#define DMA_X1_READ_ID 0x9fc1 */ - - /* IDMA Debug Register ( for internal use ) */ - -#define DMA_DEBUG_LOW DMA_X0_ADDRESS /* 0x8e01 */ -#define DMA_DEBUG_HIGH DMA_X0_COMMAND_AND_ID /*0x8e41 */ -#define DMA_SPARE 0xA8C - - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define TIMER_COUNTER0 0x850 -#define TIMER_COUNTER1 0x854 -#define TIMER_COUNTER2 0x858 -#define TIMER_COUNTER3 0x85C -#define TIMER_COUNTER_0_3_CONTROL 0x864 -#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - /*#define TIMER_COUNTER4 0x9501 */ - /*#define TIMER_COUNTER5 0x9541 */ - /*#define TIMER_COUNTER6 0x9581 */ - /*#define TIMER_COUNTER7 0x95C1 */ - /*#define TIMER_COUNTER_4_7_CONTROL 0x9641 */ - /*#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x9681 */ - /*#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c1 */ - -/****************************************/ -/* PCI Slave Address Decoding */ -/****************************************/ -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ -#define PCI_0_CS_0_BANK_SIZE PCI_0SCS_0_BANK_SIZE /*0xc081 */ -#define PCI_1_CS_0_BANK_SIZE PCI_1SCS_0_BANK_SIZE /* 0xc881 */ -#define PCI_0_CS_1_BANK_SIZE PCI_0SCS_1_BANK_SIZE /*0xd081 */ -#define PCI_1_CS_1_BANK_SIZE PCI_1SCS_1_BANK_SIZE /* 0xd881 */ -#define PCI_0_CS_2_BANK_SIZE PCI_0SCS_2_BANK_SIZE /*0xc0c1 */ -#define PCI_1_CS_2_BANK_SIZE PCI_1SCS_2_BANK_SIZE /*0xc8c1 */ -#define PCI_0_CS_3_BANK_SIZE PCI_0SCS_3_BANK_SIZE /*0xd0c1 */ -#define PCI_1_CS_3_BANK_SIZE PCI_1SCS_3_BANK_SIZE /*0xd8c1 */ -#define PCI_0_DEVCS_0_BANK_SIZE PCI_0CS_0_BANK_SIZE /*0xc101 */ -#define PCI_1_DEVCS_0_BANK_SIZE PCI_1CS_0_BANK_SIZE /*0xc901 */ -#define PCI_0_DEVCS_1_BANK_SIZE PCI_0CS_1_BANK_SIZE /*0xd101 */ -#define PCI_1_DEVCS_1_BANK_SIZE PCI_1CS_1_BANK_SIZE /* 0xd901 */ -#define PCI_0_DEVCS_2_BANK_SIZE PCI_0CS_2_BANK_SIZE /* 0xd181 */ -#define PCI_1_DEVCS_2_BANK_SIZE PCI_1CS_2_BANK_SIZE /*0xd981 */ -#define PCI_0_DEVCS_3_BANK_SIZE PCI_0CS_3_BANK_SIZE /* 0xc141 */ -#define PCI_1_DEVCS_3_BANK_SIZE PCI_1CS_3_BANK_SIZE /*0xc941 */ -#define PCI_0_DEVCS_BOOT_BANK_SIZE PCI_0CS_BOOT_BANK_SIZE /*0xd141 */ -#define PCI_1_DEVCS_BOOT_BANK_SIZE PCI_1CS_BOOT_BANK_SIZE /* 0xd941 */ -#define PCI_0_P2P_MEM0_BAR_SIZE PCI_0P2P_MEM0_BAR_SIZE /*0xd1c1 */ -#define PCI_1_P2P_MEM0_BAR_SIZE PCI_1P2P_MEM0_BAR_SIZE /*0xd9c1 */ -#define PCI_0_P2P_MEM1_BAR_SIZE PCI_0P2P_MEM1_BAR_SIZE /*0xd201 */ -#define PCI_1_P2P_MEM1_BAR_SIZE PCI_1P2P_MEM1_BAR_SIZE /*0xda01 */ -#define PCI_0_P2P_I_O_BAR_SIZE PCI_0P2P_I_O_BAR_SIZE /*0xd241 */ -#define PCI_1_P2P_I_O_BAR_SIZE PCI_1P2P_I_O_BAR_SIZE /*0xda41 */ -#define PCI_0_CPU_BAR_SIZE PCI_0CPU_BAR_SIZE /*0xd281 */ -#define PCI_1_CPU_BAR_SIZE PCI_1CPU_BAR_SIZE /*0xda81 */ -#define PCI_0_INTERNAL_SRAM_BAR_SIZE PCI_0DAC_SCS_0_BANK_SIZE /*0xe001 */ -#define PCI_1_INTERNAL_SRAM_BAR_SIZE PCI_1DAC_SCS_0_BANK_SIZE /*0xe801 */ -#define PCI_0_EXPANSION_ROM_BAR_SIZE PCI_0EXPANSION_ROM_BAR_SIZE /*0xd2c1 */ -#define PCI_1_EXPANSION_ROM_BAR_SIZE PCI_1EXPANSION_ROM_BAR_SIZE /*0xd9c1 */ -#define PCI_0_BASE_ADDR_REG_ENABLE PCI_0BASE_ADDRESS_REGISTERS_ENABLE /*0xc3c1 */ -#define PCI_1_BASE_ADDR_REG_ENABLE PCI_1BASE_ADDRESS_REGISTERS_ENABLE /*0xcbc1 */ -#define PCI_0_CS_0_BASE_ADDR_REMAP PCI_0SCS_0_BASE_ADDRESS_REMAP /*0xc481 */ -#define PCI_1_CS_0_BASE_ADDR_REMAP PCI_1SCS_0_BASE_ADDRESS_REMAP /*0xcc81 */ -#define PCI_0_CS_1_BASE_ADDR_REMAP PCI_0SCS_1_BASE_ADDRESS_REMAP /*0xd481 */ -#define PCI_1_CS_1_BASE_ADDR_REMAP PCI_1SCS_1_BASE_ADDRESS_REMAP /*0xdc81 */ -#define PCI_0_CS_2_BASE_ADDR_REMAP PCI_0SCS_2_BASE_ADDRESS_REMAP /*0xc4c1 */ -#define PCI_1_CS_2_BASE_ADDR_REMAP PCI_1SCS_2_BASE_ADDRESS_REMAP /*0xccc1 */ -#define PCI_0_CS_3_BASE_ADDR_REMAP PCI_0SCS_3_BASE_ADDRESS_REMAP /*0xd4c1 */ -#define PCI_1_CS_3_BASE_ADDR_REMAP PCI_1SCS_3_BASE_ADDRESS_REMAP /* 0xdcc1 */ -#define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP -#define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP -#define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP -#define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP -#define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP -#define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP -#define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP -#define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP -#define PCI_0_DEVCS_0_BASE_ADDR_REMAP PCI_0CS_0_BASE_ADDRESS_REMAP /*0xc501 */ -#define PCI_1_DEVCS_0_BASE_ADDR_REMAP PCI_1CS_0_BASE_ADDRESS_REMAP /*0xcd01 */ -#define PCI_0_DEVCS_1_BASE_ADDR_REMAP PCI_0CS_1_BASE_ADDRESS_REMAP /*0xd501 */ -#define PCI_1_DEVCS_1_BASE_ADDR_REMAP PCI_1CS_1_BASE_ADDRESS_REMAP /*0xdd01 */ -#define PCI_0_DEVCS_2_BASE_ADDR_REMAP PCI_0CS_2_BASE_ADDRESS_REMAP /*0xd581 */ -#define PCI_1_DEVCS_2_BASE_ADDR_REMAP PCI_1CS_2_BASE_ADDRESS_REMAP /*0xdd81 */ -#define PCI_0_DEVCS_3_BASE_ADDR_REMAP PCI_0CS_3_BASE_ADDRESS_REMAP /*0xc541 */ -#define PCI_1_DEVCS_3_BASE_ADDR_REMAP PCI_1CS_3_BASE_ADDRESS_REMAP /*0xcd41 */ -#define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP /*0xd541 */ -#define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP /*0xdd41 */ -#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xd5c1 */ -#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xddc1 */ -#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xd601 */ -#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xde01 */ -#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xd641 */ -#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xde41 */ -#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xd681 */ -#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xde81 */ -#define PCI_0_P2P_I_O_BASE_ADDR_REMAP PCI_0P2P_I_O_BASE_ADDRESS_REMAP /*0xd6c1 */ -#define PCI_1_P2P_I_O_BASE_ADDR_REMAP PCI_1P2P_I_O_BASE_ADDRESS_REMAP /*0xdec 1 */ -#define PCI_0_CPU_BASE_ADDR_REMAP_LOW PCI_0CPU_BASE_ADDRESS_REMAP /*0xd701 */ -#define PCI_1_CPU_BASE_ADDR_REMAP_LOW PCI_1CPU_BASE_ADDRESS_REMAP /*0xdf01 */ -#define PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP /*0xf001 */ -#define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xf381 */ -#define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xfb81 */ -#define PCI_0_ADDR_DECODE_CONTROL PCI_0ADDRESS_DECODE_CONTROL /*0xd3c1 */ -#define PCI_1_ADDR_DECODE_CONTROL PCI_1ADDRESS_DECODE_CONTROL /*0xdbc1 */ -#define PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -#define PCI_0SCS_0_BANK_SIZE 0xc08 -#define PCI_1SCS_0_BANK_SIZE 0xc88 -#define PCI_0SCS_1_BANK_SIZE 0xd08 -#define PCI_1SCS_1_BANK_SIZE 0xd88 -#define PCI_0SCS_2_BANK_SIZE 0xc0c -#define PCI_1SCS_2_BANK_SIZE 0xc8c -#define PCI_0SCS_3_BANK_SIZE 0xd0c -#define PCI_1SCS_3_BANK_SIZE 0xd8c -#define PCI_0CS_0_BANK_SIZE 0xc10 -#define PCI_1CS_0_BANK_SIZE 0xc90 -#define PCI_0CS_1_BANK_SIZE 0xd10 -#define PCI_1CS_1_BANK_SIZE 0xd90 -#define PCI_0CS_2_BANK_SIZE 0xd18 -#define PCI_1CS_2_BANK_SIZE 0xd98 -#define PCI_0CS_3_BANK_SIZE 0xc14 -#define PCI_1CS_3_BANK_SIZE 0xc94 -#define PCI_0CS_BOOT_BANK_SIZE 0xd14 -#define PCI_1CS_BOOT_BANK_SIZE 0xd94 -#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c -#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c -#define PCI_0P2P_MEM1_BAR_SIZE 0xd20 -#define PCI_1P2P_MEM1_BAR_SIZE 0xda0 -#define PCI_0P2P_I_O_BAR_SIZE 0xd24 -#define PCI_1P2P_I_O_BAR_SIZE 0xda4 -#define PCI_0CPU_BAR_SIZE 0xd28 -#define PCI_1CPU_BAR_SIZE 0xda8 -#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 -#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 -#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 -#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 -#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 -#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 -#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c -#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c -#define PCI_0DAC_CS_0_BANK_SIZE 0xe10 -#define PCI_1DAC_CS_0_BANK_SIZE 0xe90 -#define PCI_0DAC_CS_1_BANK_SIZE 0xe14 -#define PCI_1DAC_CS_1_BANK_SIZE 0xe94 -#define PCI_0DAC_CS_2_BANK_SIZE 0xe18 -#define PCI_1DAC_CS_2_BANK_SIZE 0xe98 -#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c -#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c -#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 -#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 - -#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 -#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 -#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 -#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 -#define PCI_0DAC_CPU_BAR_SIZE 0xe2c -#define PCI_1DAC_CPU_BAR_SIZE 0xeac -#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c -#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac -#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c -#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc -#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 -#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 -#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 -#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 -#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c -#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc -#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c -#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc -#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 -#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 -#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 -#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 -#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 -#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 -#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 -#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 -#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 -#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 -#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c -#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec -#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 -#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 -#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 -#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 -#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 -#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 -#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 -#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 -#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c -#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c -#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 -#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 -#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 -#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 -#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 -#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 -#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c -#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c -#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 -#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 -#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 -#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 -#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 -#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 -#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c -#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc - -/****************************************/ -/* PCI Control */ -/****************************************/ - -#define PCI_0COMMAND 0xc00 -#define PCI_1COMMAND 0xc80 -#define PCI_0MODE 0xd00 -#define PCI_1MODE 0xd80 -#define PCI_0TIMEOUT_RETRY 0xc04 -#define PCI_1TIMEOUT_RETRY 0xc84 -#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 -#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 -#define MSI_0TRIGGER_TIMER 0xc38 -#define MSI_1TRIGGER_TIMER 0xcb8 -#define PCI_0ARBITER_CONTROL 0x1d00 -#define PCI_1ARBITER_CONTROL 0x1d80 -/* changing untill here */ -#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 -#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c -#define PCI_0CROSS_BAR_TIMEOUT 0x1d04 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c -#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 -#define PCI_0P2P_CONFIGURATION 0x1d14 -#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 -#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 -#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 -#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 -#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 -#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 -#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60 -#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 -#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 -#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70 -#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 -#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 -#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 -#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c -#define PCI_1CROSS_BAR_TIMEOUT 0x1d84 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c -#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 -#define PCI_1P2P_CONFIGURATION 0x1d94 -#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 -#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 -#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 -#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 -#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 -#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 -#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0 -#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 -#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 -#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0 -#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 -#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 - -/****************************************/ -/* PCI Snoop Control */ -/****************************************/ - -#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 -#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 -#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 -#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 -#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 -#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 -#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 -#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 -#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 -#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 -#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 -#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 -#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 -#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 -#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 -#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 -#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 -#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 -#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 -#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 -#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 -#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 -#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 -#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 - -/****************************************/ -/* PCI Configuration Address */ -/****************************************/ - -#define PCI_0CONFIGURATION_ADDRESS 0xcf8 -#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc -#define PCI_1CONFIGURATION_ADDRESS 0xc78 -#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c -#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 -#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 - -/****************************************/ -/* PCI Error Report */ -/****************************************/ - -#define PCI_0SERR_MASK 0xc28 -#define PCI_0ERROR_ADDRESS_LOW 0x1d40 -#define PCI_0ERROR_ADDRESS_HIGH 0x1d44 -#define PCI_0ERROR_DATA_LOW 0x1d48 -#define PCI_0ERROR_DATA_HIGH 0x1d4c -#define PCI_0ERROR_COMMAND 0x1d50 -#define PCI_0ERROR_CAUSE 0x1d58 -#define PCI_0ERROR_MASK 0x1d5c -#define PCI_1SERR_MASK 0xca8 -#define PCI_1ERROR_ADDRESS_LOW 0x1dc0 -#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 -#define PCI_1ERROR_DATA_LOW 0x1dc8 -#define PCI_1ERROR_DATA_HIGH 0x1dcc -#define PCI_1ERROR_COMMAND 0x1dd0 -#define PCI_1ERROR_CAUSE 0x1dd8 -#define PCI_1ERROR_MASK 0x1ddc - - -/****************************************/ -/* Lslave Debug (for internal use) */ -/****************************************/ - -#define L_SLAVE_X0_ADDRESS 0x1d20 -#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 -#define L_SLAVE_X1_ADDRESS 0x1d28 -#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c -#define L_SLAVE_WRITE_DATA_LOW 0x1d30 -#define L_SLAVE_WRITE_DATA_HIGH 0x1d34 -#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 -#define L_SLAVE_READ_DATA_LOW 0x1d38 -#define L_SLAVE_READ_DATA_HIGH 0x1d3c -#define L_SLAVE_READ_ID 0x1d64 - -/****************************************/ -/* PCI Configuration Function 0 */ -/****************************************/ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C -#define PCI_SCS_0_BASE_ADDRESS 0x010 -#define PCI_SCS_1_BASE_ADDRESS 0x014 -#define PCI_SCS_2_BASE_ADDRESS 0x018 -#define PCI_SCS_3_BASE_ADDRESS 0x01C -#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 -#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 -#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C -#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDRESS 0x048 -#define PCI_VPD_DATA 0x04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDRESS 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 - -/****************************************/ -/* PCI Configuration Function 1 */ -/****************************************/ - -#define PCI_CS_0_BASE_ADDRESS 0x110 -#define PCI_CS_1_BASE_ADDRESS 0x114 -#define PCI_CS_2_BASE_ADDRESS 0x118 -#define PCI_CS_3_BASE_ADDRESS 0x11c -#define PCI_BOOTCS_BASE_ADDRESS 0x120 - -/****************************************/ -/* PCI Configuration Function 2 */ -/****************************************/ - -#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 - /*#define PCI_P2P_MEM1_BASE_ADDRESS 0x2141 */ -#define PCI_P2P_I_O_BASE_ADDRESS 0x218 - /*#define PCI_CPU_BASE_ADDRESS 0x21c1 */ - -/****************************************/ -/* PCI Configuration Function 4 */ -/****************************************/ - -#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 -#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 -#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 -#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 - - -/****************************************/ -/* PCI Configuration Function 5 */ -/****************************************/ - -#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 -#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 -#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 -#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 - - -/****************************************/ -/* PCI Configuration Function 6 */ -/****************************************/ - -#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 -#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 -#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 -#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c -#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 -#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 - -/****************************************/ -/* PCI Configuration Function 7 */ -/****************************************/ - -#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 -#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c -#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 -#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 - -/****************************** MV64360 and MV64460 PCI ***************************/ -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define PCI_0_COMMAND 0xc00 -#define PCI_1_COMMAND 0xc80 -#define PCI_0_MODE 0xd00 -#define PCI_1_MODE 0xd80 -#define PCI_0_RETRY 0xc04 -#define PCI_1_RETRY 0xc84 -#define PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define PCI_0_ARBITER_CONTROL 0x1d00 -#define PCI_1_ARBITER_CONTROL 0x1d80 -#define PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define PCI_0_P2P_CONFIG 0x1d14 -#define PCI_1_P2P_CONFIG 0x1d94 - -#define PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define PCI_0_CONFIG_ADDR 0xcf8 -#define PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define PCI_1_CONFIG_ADDR 0xc78 -#define PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define PCI_0_SERR_MASK 0xc28 -#define PCI_1_SERR_MASK 0xca8 -#define PCI_0_ERROR_ADDR_LOW 0x1d40 -#define PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define PCI_0_ERROR_COMMAND 0x1d50 -#define PCI_1_ERROR_COMMAND 0x1dd0 -#define PCI_0_ERROR_CAUSE 0x1d58 -#define PCI_1_ERROR_CAUSE 0x1dd8 -#define PCI_0_ERROR_MASK 0x1d5c -#define PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define PCI_0_MMASK 0X1D24 -#define PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 - /*#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c1 */ -#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDR 0x048 -#define PCI_VPD_DATA 0x04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDR 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_X_COMMAND 0x060 -#define PCI_X_STATUS 0x064 -#define PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define PCI_CPU_BASE_ADDR_LOW 0x220 -#define PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define PCI_P2P_I_O_BASE_ADDR 0x420 -#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************** MV64360 and MV64460 PCI End ***************************/ -/****************************************/ -/* I20 Support registers */ -/****************************************/ - -#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 -#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 -#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 -#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C -#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 -#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 -#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C - -#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10 -#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14 -#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18 -#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C -#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28 -#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44 -#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C - - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - - -/****************************************/ -/* Communication Unit Registers */ -/****************************************/ -/* -#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200 -#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 -#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 -#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c -#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 -#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 -#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 -#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 -#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 -#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 -#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c -#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 -#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 -#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 -#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 -#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 -#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 -#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c -#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 -#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 -#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 - */ -#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 -#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 -#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 -#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c -#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 -#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 -#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0 -#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4 -#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 -#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc -#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 -#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 - /*#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf3201 */ -#define COMM_UNIT_ARBITER_CONTROL 0xf300 -#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 -#define COMM_UNIT_INTERRUPT_CAUSE 0xf310 -#define COMM_UNIT_INTERRUPT_MASK 0xf314 -#define COMM_UNIT_ERROR_ADDRESS 0xf314 -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - - /*#define SERIAL_INIT_LAST_DATA 0xf3241 */ - /*#define SERIAL_INIT_STATUS_AND_CONTROL 0xf3281 */ -#define SERIAL_INIT_LAST_DATA 0xf324 -#define SERIAL_INIT_CONTROL 0xf328 -#define SERIAL_INIT_STATUS 0xf32c - - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define ETH_PHY_ADDR_REG 0x2000 -#define ETH_SMI_REG 0x2004 -#define ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define ETH_UNIT_DEFAULTID_REG 0x200c -#define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define ETH_BAR_0 0x2200 -#define ETH_BAR_1 0x2208 -#define ETH_BAR_2 0x2210 -#define ETH_BAR_3 0x2218 -#define ETH_BAR_4 0x2220 -#define ETH_BAR_5 0x2228 -#define ETH_SIZE_REG_0 0x2204 -#define ETH_SIZE_REG_1 0x220c -#define ETH_SIZE_REG_2 0x2214 -#define ETH_SIZE_REG_3 0x221c -#define ETH_SIZE_REG_4 0x2224 -#define ETH_SIZE_REG_5 0x222c -#define ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define ETH_DSCP_3(port) (0x242c + (port<<10)) -#define ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/****************************************/ -/* Cunit Debug (for internal use) */ -/****************************************/ - -#define CUNIT_ADDRESS 0xf340 -#define CUNIT_COMMAND_AND_ID 0xf344 -#define CUNIT_WRITE_DATA_LOW 0xf348 -#define CUNIT_WRITE_DATA_HIGH 0xf34c -#define CUNIT_WRITE_BYTE_ENABLE 0xf358 -#define CUNIT_READ_DATA_LOW 0xf350 -#define CUNIT_READ_DATA_HIGH 0xf354 -#define CUNIT_READ_ID 0xf35c - -/****************************************/ -/* Fast Ethernet Unit Registers */ -/****************************************/ - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define ETH_PHY_ADDR_REG 0x2000 -#define ETH_SMI_REG 0x2004 -#define ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define ETH_UNIT_DEFAULTID_REG 0x200c -#define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define ETH_BAR_0 0x2200 -#define ETH_BAR_1 0x2208 -#define ETH_BAR_2 0x2210 -#define ETH_BAR_3 0x2218 -#define ETH_BAR_4 0x2220 -#define ETH_BAR_5 0x2228 -#define ETH_SIZE_REG_0 0x2204 -#define ETH_SIZE_REG_1 0x220c -#define ETH_SIZE_REG_2 0x2214 -#define ETH_SIZE_REG_3 0x221c -#define ETH_SIZE_REG_4 0x2224 -#define ETH_SIZE_REG_5 0x222c -#define ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define ETH_DSCP_3(port) (0x242c + (port<<10)) -#define ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - - -/* Ethernet GT64260 */ -/* -#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 -#define ETHERNET_SMI_REGISTER 0x2010 -*/ -/* Ethernet 0 */ -/* -#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 -#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 -#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 -#define ETHERNET0_PORT_STATUS_REGISTER 0x2418 -#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 -#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 -#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 -#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 -#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 -#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 -#define ETHERNET0_MIB_COUNTER_BASE 0x2500 -*/ -/* Ethernet 1 */ -/* -#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 -#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 -#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 -#define ETHERNET1_PORT_STATUS_REGISTER 0x2818 -#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 -#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 -#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 -#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 -#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 -#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 -#define ETHERNET1_MIB_COUNTER_BASE 0x2900 -*/ -/* Ethernet 2 */ -/* -#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 -#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 -#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 -#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 -#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 -#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 -#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 -#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 -#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 -#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 -#define ETHERNET2_MIB_COUNTER_BASE 0x2d00 -*/ - -/****************************************/ -/* SDMA Registers */ -/****************************************/ - -#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 -#define CHANNEL0_CONFIGURATION_REGISTER 0x4000 -#define CHANNEL0_COMMAND_REGISTER 0x4008 -#define CHANNEL0_RX_CMD_STATUS 0x4800 -#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 -#define CHANNEL0_RX_BUFFER_POINTER 0x4808 -#define CHANNEL0_RX_NEXT_POINTER 0x480c -#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 -#define CHANNEL0_TX_CMD_STATUS 0x4C00 -#define CHANNEL0_TX_PACKET_SIZE 0x4C04 -#define CHANNEL0_TX_BUFFER_POINTER 0x4C08 -#define CHANNEL0_TX_NEXT_POINTER 0x4C0c -#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 -#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 -/* -#define CHANNEL1_CONFIGURATION_REGISTER 0x5000 -#define CHANNEL1_COMMAND_REGISTER 0x5008 -#define CHANNEL1_RX_CMD_STATUS 0x5800 -#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804 -#define CHANNEL1_RX_BUFFER_POINTER 0x5808 -#define CHANNEL1_RX_NEXT_POINTER 0x580c -#define CHANNEL1_TX_CMD_STATUS 0x5C00 -#define CHANNEL1_TX_PACKET_SIZE 0x5C04 -#define CHANNEL1_TX_BUFFER_POINTER 0x5C08 -#define CHANNEL1_TX_NEXT_POINTER 0x5C0c -#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810 -#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10 -#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14 -#define CHANNEL2_CONFIGURATION_REGISTER 0x6000 -#define CHANNEL2_COMMAND_REGISTER 0x6008 -#define CHANNEL2_RX_CMD_STATUS 0x6800 -#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804 -#define CHANNEL2_RX_BUFFER_POINTER 0x6808 -#define CHANNEL2_RX_NEXT_POINTER 0x680c -#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL2_TX_CMD_STATUS 0x6C00 -#define CHANNEL2_TX_PACKET_SIZE 0x6C04 -#define CHANNEL2_TX_BUFFER_POINTER 0x6C08 -#define CHANNEL2_TX_NEXT_POINTER 0x6C0c -#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 -#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 -*/ -/* SDMA Interrupt */ -/* -#define SDMA_CAUSE 0xb820 -#define SDMA_MASK 0xb8a0 -*/ -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define SDMA_CAUSE_REG 0xb800 -#define SDMA_MASK_REG 0xb880 - -/****************************************/ -/* Baude Rate Generators Registers */ -/****************************************/ - -/* BRG 0 */ -#define BRG0_CONFIGURATION_REGISTER 0xb200 -#define BRG0_BAUDE_TUNING_REGISTER 0xb204 - -/* BRG 1 */ -#define BRG1_CONFIGURATION_REGISTER 0xb208 -#define BRG1_BAUDE_TUNING_REGISTER 0xb20c - -/* BRG 2 */ -#define BRG2_CONFIGURATION_REGISTER 0xb210 -#define BRG2_BAUDE_TUNING_REGISTER 0xb214 - -/* BRG Interrupts */ -#define BRG_CAUSE_REGISTER 0xb834 -#define BRG_MASK_REGISTER 0xb8b4 -#define BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3)) -#define BRG_CAUSE_REG BRG_CAUSE_REGISTER /*0xb8341 */ -#define BRG_MASK_REG BRG_MASK_REGISTER /*0xb8b41 */ - -/* MISC */ - -#define MAIN_ROUTING_REGISTER 0xb400 -#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 -#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 -#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ -#define WATCHDOG_CONFIGURATION_REGISTER 0xb410 -#define WATCHDOG_VALUE_REGISTER 0xb414 -#define WATCHDOG_CONFIG_REG WATCHDOG_CONFIGURATION_REGISTER /*0xb4101 */ -#define WATCHDOG_VALUE_REG WATCHDOG_VALUE_REGISTER /*0xb4141 */ - - -/****************************************/ -/* Flex TDM Registers */ -/****************************************/ - -/* FTDM Port */ - -#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 -#define FLEXTDM_RECEIVE_READ_POINTER 0xa804 -#define FLEXTDM_CONFIGURATION_REGISTER 0xa808 -#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c -#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 -#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 -#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 - -/* FTDM Interrupts */ - -#define FTDM_CAUSE_REGISTER 0xb830 -#define FTDM_MASK_REGISTER 0xb8b0 - - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define GPP_IO_CONTROL 0xf100 -#define GPP_LEVEL_CONTROL 0xf110 -#define GPP_VALUE 0xf104 -#define GPP_INTERRUPT_CAUSE 0xf108 -#define GPP_INTERRUPT_MASK 0xf10c -#define GPP_INTERRUPT_MASK0 GPP_INTERRUPT_MASK /* 0xf10c1 */ -#define GPP_INTERRUPT_MASK1 0xf114 -#define GPP_VALUE_SET 0xf118 -#define GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ -#define MPP_CONTROL0 0xf000 -#define MPP_CONTROL1 0xf004 -#define MPP_CONTROL2 0xf008 -#define MPP_CONTROL3 0xf00c -#define DEBUG_PORT_MULTIPLEX 0xf014 - /*#define SERIAL_PORT_MULTIPLEX 0xf0101 */ - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ -/****************************************/ -/* Interrupts (checked I.A. 14.10.02) */ -/****************************************/ - -#define LOW_INTERRUPT_CAUSE_REGISTER 0x004 /* gt64260: 0xc181 */ -#define HIGH_INTERRUPT_CAUSE_REGISTER 0x00c /* gt64260: 0xc681 */ -#define CPU_INTERRUPT_MASK_REGISTER_LOW 0x014 /* gt64260: 0xc1c1 */ -#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0x01c /* gt64260: 0xc6c1 */ -#define CPU_SELECT_CAUSE_REGISTER 0x024 /* gt64260: 0xc701 */ -#define CPU_INTERRUPT_1_MASK_REGISTER_LOW 0x034 /* new in the MV64360 and MV64460 */ -#define CPU_INTERRUPT_1_MASK_REGISTER_HIGH 0x03c /* new in the MV64360 and MV64460 */ -#define CPU_SELECT_1_CAUSE_REGISTER 0x044 /* new in the MV64360 and MV64460 */ -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x054 /* gt64260: 0xc241 */ -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x05c /* gt64260: 0xc641 */ -#define PCI_0SELECT_CAUSE 0x064 /* gt64260: 0xc741 */ -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x074 /* gt64260: 0xca41 */ -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x07c /* gt64260: 0xce41 */ -#define PCI_1SELECT_CAUSE 0x084 /* gt64260: 0xcf41 */ -/*#define CPU_INT_0_MASK 0xe60 signal is not multiplexed on MPP in the MV64360 and MV64460 */ -/*#define CPU_INT_1_MASK 0xe64 signal is not multiplexed on MPP in the MV64360 and MV64460 */ -/*#define CPU_INT_2_MASK 0xe68 signal is not multiplexed on MPP in the MV64360 and MV64460 */ -/*#define CPU_INT_3_MASK 0xe6c signal is not multiplexed on MPP in the MV64360 and MV64460 */ - -#define MAIN_INTERRUPT_CAUSE_LOW LOW_INTERRUPT_CAUSE_REGISTER /* 0x0041 */ -#define MAIN_INTERRUPT_CAUSE_HIGH HIGH_INTERRUPT_CAUSE_REGISTER /* 0x00c1 */ -#define CPU_INTERRUPT0_MASK_LOW CPU_INTERRUPT_MASK_REGISTER_LOW /* 0x0141 */ -#define CPU_INTERRUPT0_MASK_HIGH CPU_INTERRUPT_MASK_REGISTER_HIGH /*0x01c1 */ -#define CPU_INTERRUPT0_SELECT_CAUSE CPU_SELECT_CAUSE_REGISTER /* 0x0241 */ -#define CPU_INTERRUPT1_MASK_LOW CPU_INTERRUPT_1_MASK_REGISTER_LOW /* 0x0341 */ -#define CPU_INTERRUPT1_MASK_HIGH CPU_INTERRUPT_1_MASK_REGISTER_HIGH /* 0x03c1 */ -#define CPU_INTERRUPT1_SELECT_CAUSE CPU_SELECT_1_CAUSE_REGISTER /* 0x0441 */ -#define INTERRUPT0_MASK_0_LOW PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0541 */ -#define INTERRUPT0_MASK_0_HIGH PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x05c1 */ -#define INTERRUPT0_SELECT_CAUSE PCI_0SELECT_CAUSE /* 0x0641 */ -#define INTERRUPT1_MASK_0_LOW PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0741 */ -#define INTERRUPT1_MASK_0_HIGH PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x07c1 */ -#define INTERRUPT1_SELECT_CAUSE PCI_1SELECT_CAUSE /* 0x0841 */ - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define I2C_SLAVE_ADDRESS 0xc000 -#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 -#define I2C_DATA 0xc004 -#define I2C_CONTROL 0xc008 -#define I2C_STATUS_BAUDE_RATE 0xc00C -#define I2C_SOFT_RESET 0xc01c -#define I2C_SLAVE_ADDR I2C_SLAVE_ADDRESS /* 0xc0001 */ -#define I2C_EXTENDED_SLAVE_ADDR I2C_EXTENDED_SLAVE_ADDRESS /*0xc0101 */ - -/****************************************/ -/* MPSC Registers */ -/****************************************/ - - /* MPSCs Clocks Routing Registers */ - -#define MPSC_ROUTING_REG 0xb400 -#define MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - -/* MPSC0 */ - -#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 -#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 -#define MPSC0_PROTOCOL_CONFIGURATION 0x8008 -#define CHANNEL0_REGISTER1 0x800c -#define CHANNEL0_REGISTER2 0x8010 -#define CHANNEL0_REGISTER3 0x8014 -#define CHANNEL0_REGISTER4 0x8018 -#define CHANNEL0_REGISTER5 0x801c -#define CHANNEL0_REGISTER6 0x8020 -#define CHANNEL0_REGISTER7 0x8024 -#define CHANNEL0_REGISTER8 0x8028 -#define CHANNEL0_REGISTER9 0x802c -#define CHANNEL0_REGISTER10 0x8030 -#define CHANNEL0_REGISTER11 0x8034 - -/* MPSC1 */ - -#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840 -#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844 -#define MPSC1_PROTOCOL_CONFIGURATION 0x8848 -#define CHANNEL1_REGISTER1 0x884c -#define CHANNEL1_REGISTER2 0x8850 -#define CHANNEL1_REGISTER3 0x8854 -#define CHANNEL1_REGISTER4 0x8858 -#define CHANNEL1_REGISTER5 0x885c -#define CHANNEL1_REGISTER6 0x8860 -#define CHANNEL1_REGISTER7 0x8864 -#define CHANNEL1_REGISTER8 0x8868 -#define CHANNEL1_REGISTER9 0x886c -#define CHANNEL1_REGISTER10 0x8870 -#define CHANNEL1_REGISTER11 0x8874 - -/* MPSC2 */ - -#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040 -#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044 -#define MPSC2_PROTOCOL_CONFIGURATION 0x9048 -#define CHANNEL2_REGISTER1 0x904c -#define CHANNEL2_REGISTER2 0x9050 -#define CHANNEL2_REGISTER3 0x9054 -#define CHANNEL2_REGISTER4 0x9058 -#define CHANNEL2_REGISTER5 0x905c -#define CHANNEL2_REGISTER6 0x9060 -#define CHANNEL2_REGISTER7 0x9064 -#define CHANNEL2_REGISTER8 0x9068 -#define CHANNEL2_REGISTER9 0x906c -#define CHANNEL2_REGISTER10 0x9070 -#define CHANNEL2_REGISTER11 0x9074 - -/* MPSCs Interupts */ - -#define MPSC0_CAUSE 0xb824 -#define MPSC0_MASK 0xb8a4 -#define MPSC1_CAUSE 0xb828 -#define MPSC1_MASK 0xb8a8 -#define MPSC2_CAUSE 0xb82c -#define MPSC2_MASK 0xb8ac - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define CUNIT_BASE_ADDR_REG0 0xf200 -#define CUNIT_BASE_ADDR_REG1 0xf208 -#define CUNIT_BASE_ADDR_REG2 0xf210 -#define CUNIT_BASE_ADDR_REG3 0xf218 -#define CUNIT_SIZE0 0xf204 -#define CUNIT_SIZE1 0xf20c -#define CUNIT_SIZE2 0xf214 -#define CUNIT_SIZE3 0xf21c -#define CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define CUNIT_INTERRUPT_MASK_REG 0xf314 -#define CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define CUNIT_ARBITER_CONTROL_REG 0xf300 -#define CUNIT_CONFIG_REG 0xb40c -#define CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define CUNIT_DEBUG_LOW 0xf340 -#define CUNIT_DEBUG_HIGH 0xf344 -#define CUNIT_MMASK 0xf380 - -#endif /* __INCmv_gen_regh */ diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h deleted file mode 100644 index 167248d..0000000 --- a/board/Marvell/include/pci.h +++ /dev/null @@ -1,293 +0,0 @@ -/* PCI.h - PCI functions header file */ - -/* Copyright - Galileo technology. */ - -#ifndef __INCpcih -#define __INCpcih - -/* includes */ - -#include"core.h" -#include"memory.h" - -/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ -#define PCI_MAX_DEVICES 22 - - -/* Macros */ - -/* The next Macros configurate the initiator board (SELF) or any any agent on - the PCI to become: MASTER, response to MEMORY transactions , response to - IO transactions or TWO both MEMORY_IO transactions. Those configuration - are for both PCI0 and PCI1. */ - -#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \ - pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber)) - -#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \ - pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \ - PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \ - pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) - -#define MASTER_ENABLE BIT2 -#define MEMORY_ENABLE BIT1 -#define I_O_ENABLE BIT0 -#define SELF 32 - -/* Agent on the PCI bus may have up to 6 BARS. */ -#define BAR0 0x10 -#define BAR1 0x14 -#define BAR2 0x18 -#define BAR3 0x1c -#define BAR4 0x20 -#define BAR5 0x24 -#define BAR_SEL_MEM_IO BIT0 -#define BAR_MEM_TYPE_32_BIT NO_BIT -#define BAR_MEM_TYPE_BELOW_1M BIT1 -#define BAR_MEM_TYPE_64_BIT BIT2 -#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2) -#define BAR_MEM_TYPE_MASK (BIT1 | BIT2) -#define BAR_PREFETCHABLE BIT3 -#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3) - -/* Defines for the access regions. */ -#define PREFETCH_ENABLE BIT12 -#define PREFETCH_DISABLE NO_BIT -#define DELAYED_READ_ENABLE BIT13 -/* #define CACHING_ENABLE BIT14 */ -/* aggressive prefetch: PCI slave prefetch two burst in advance*/ -#define AGGRESSIVE_PREFETCH BIT16 -/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/ -#define READ_LINE_AGGRESSIVE_PREFETCH BIT17 -/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/ -#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18 -#define MAX_BURST_4 NO_BIT -#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */ -#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */ -#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */ -#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */ -#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */ -#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */ -#define PCI_ACCESS_PROTECT BIT28 -#define PCI_WRITE_PROTECT BIT29 - -/* typedefs */ - -typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5, - REGION6,REGION7} PCI_ACCESS_REGIONS; - -typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO; -typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK; - -typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB} - PCI_SNOOP_TYPE; -typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1, - PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} - PCI_SNOOP_REGION; - -typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST; -typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1, - PCI_REGION2,PCI_REGION3, - PCI_IO} - PCI_REGION; - -/*ronen 7/Dec/03 */ -typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR, - PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR, - PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR, - PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR, - PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR, - PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR, - PCI_LAST_BAR} PCI_INTERNAL_BAR; - -typedef struct pciBar { - unsigned int detectBase; - unsigned int base; - unsigned int size; - unsigned int type; -} PCI_BAR; - -typedef struct pciDevice { - PCI_HOST host; - char type[40]; - unsigned int deviceNum; - unsigned int venID; - unsigned int deviceID; - PCI_BAR bar[6]; -} PCI_DEVICE; - -typedef struct pciSelfBars { - unsigned int SCS0Base; - unsigned int SCS0Size; - unsigned int SCS1Base; - unsigned int SCS1Size; - unsigned int SCS2Base; - unsigned int SCS2Size; - unsigned int SCS3Base; - unsigned int SCS3Size; - unsigned int internalMemBase; - unsigned int internalIOBase; - unsigned int CS0Base; - unsigned int CS0Size; - unsigned int CS1Base; - unsigned int CS1Size; - unsigned int CS2Base; - unsigned int CS2Size; - unsigned int CS3Base; - unsigned int CS3Size; - unsigned int CSBootBase; - unsigned int CSBootSize; - unsigned int P2PMem0Base; - unsigned int P2PMem0Size; - unsigned int P2PMem1Base; - unsigned int P2PMem1Size; - unsigned int P2PIOBase; - unsigned int P2PIOSize; - unsigned int CPUBase; - unsigned int CPUSize; -} PCI_SELF_BARS; - -/* read/write configuration registers on local PCI bus. */ -void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data); -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum); - -/* read/write configuration registers on another PCI bus. */ -void pciOverBridgeWriteConfigReg(PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum,unsigned int data); -unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum); - -/* Performs full scane on both PCI and returns all detail possible on the - agents which exist on the bus. */ -void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect, - unsigned int numberOfElment); - -/* Master`s memory space */ -bool pciMapSpace(PCI_HOST host, PCI_REGION region, - unsigned int remapBase, - unsigned int deviceBase, - unsigned int deviceLength); -unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region); -unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region); - -/* Slave`s memory space */ -void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, - unsigned int pci0Dram0Base, unsigned int pci0Dram0Size); - -#if 0 /* GARBAGE routines - dont use till they get cleaned up */ -void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars); -void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars); -void pci0MapInternalRegSpace(unsigned int pci0InternalBase); -void pci1MapInternalRegSpace(unsigned int pci1InternalBase); -void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase); -void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase); -void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base, - unsigned int pci0Dev0Length); -void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base, - unsigned int pci1Dev0Length); -void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base, - unsigned int pci0Dev1Length); -void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base, - unsigned int pci1Dev1Length); -void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base, - unsigned int pci0Dev2Length); -void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base, - unsigned int pci1Dev2Length); -void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base, - unsigned int pci0Dev3Length); -void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base, - unsigned int pci1Dev3Length); -void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase, - unsigned int pci0DevBootLength); -void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase, - unsigned int pci1DevBootLength); -void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base, - unsigned int pci0P2pMem0Length); -void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base, - unsigned int pci1P2pMem0Length); -void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base, - unsigned int pci0P2pMem1Length); -void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base, - unsigned int pci1P2pMem1Length); -void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase, - unsigned int pci0P2pIoLength); -void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase, - unsigned int pci1P2pIoLength); - -void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs); -void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs); -#endif - -/* PCI region options */ - -bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength); - -void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region); - -/* PCI arbiter */ - -bool pciArbiterEnable(PCI_HOST host); -bool pciArbiterDisable(PCI_HOST host); -bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5); -bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5); -bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5); -bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); -bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); - -/* PCI-to-PCI (P2P) */ - -bool pciP2PConfig(PCI_HOST host, - unsigned int SecondBusLow,unsigned int SecondBusHigh, - unsigned int busNum,unsigned int devNum); -/* PCI Cache-coherency */ - -bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); - -PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev); - -#endif /* __INCpcih */ diff --git a/board/RPXClassic/Makefile b/board/RPXClassic/Makefile deleted file mode 100644 index 93907ba..0000000 --- a/board/RPXClassic/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o eccx.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c deleted file mode 100644 index 49cb8ad..0000000 --- a/board/RPXClassic/RPXClassic.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * (C) Copyright 2001 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * U-Boot port on RPXClassic LF (CLLF_BW31) board - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static unsigned char aschex_to_byte (unsigned char *cp); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, - 0x0CFFCC00, 0x33FFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXClassic\n"); - return (0); -} - -/*----------------------------------------------------------------------------- - * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM - *----------------------------------------------------------------------------- - */ -void board_get_enetaddr (uchar * enet) -{ - int i; - char buff[256], *cp; - - /* Initialize I2C */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x54, 0, 1, (uchar *)buff, 128); - i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128); - - /* Retrieve MAC address in buffer (key EA) */ - for (cp = buff;;) { - if (cp[0] == 'E' && cp[1] == 'A') { - cp += 3; - /* Read MAC address */ - for (i = 0; i < 6; i++, cp += 2) { - enet[i] = aschex_to_byte ((unsigned char *)cp); - } - } - /* Scan to the end of the record */ - while ((*cp != '\n') && (*cp != (char)0xff)) { - cp++; - } - /* If the next character is a \n, 0 or ff, we are done. */ - cp++; - if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff)) - break; - } - -#ifdef CONFIG_FEC_ENET - /* The MAC address is the same as normal ethernet except the 3rd byte */ - /* (See the E.P. Planet Core Overview manual */ - enet[3] |= 0x80; -#endif - - printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n", - enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]); - -} - -void rpxclassic_init (void) -{ - /* Enable NVRAM */ - *((uchar *) BCSR0) |= BCSR0_ENNVRAM; - -#ifdef CONFIG_FEC_ENET - - /* Validate the fast ethernet tranceiver */ - *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL; - *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN; - *((volatile uchar *) BCSR2) |= BCSR2_MIIRST; - *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN; -#endif - -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CFG_MPTPR; - - memctl->memc_mar = 0x00000000; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - - memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 10 column mode - */ - - size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - return (size10); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} -/*----------------------------------------------------------------------------- - * aschex_to_byte -- - *----------------------------------------------------------------------------- - */ -static unsigned char aschex_to_byte (unsigned char *cp) -{ - u_char byte, c; - - c = *cp++; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else { - c -= '0'; - } - - byte = c * 16; - - c = *cp; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else { - c -= '0'; - } - - byte += c; - - return (byte); -} diff --git a/board/RPXClassic/config.mk b/board/RPXClassic/config.mk deleted file mode 100644 index ae455e1..0000000 --- a/board/RPXClassic/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2001 -# Stäubli Faverges - -# Pierre AUBERT p.aubert@staubli.com -# U-Boot port on RPXClassic LF (CLLF_BW31) board -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xff000000 diff --git a/board/RPXClassic/eccx.c b/board/RPXClassic/eccx.c deleted file mode 100644 index cc76bbd..0000000 --- a/board/RPXClassic/eccx.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* Video support for the ECCX daughter board */ - - -#include -#include - -#ifdef CONFIG_VIDEO_SED13806 -#include - - -/* Screen configurations: the initialization of the SD13806 depends on - screen and on display mode. We handle only 8bpp and 16 bpp modes */ - -/* ECCX board is supplied with a NEC NL6448BC20 screen */ -#ifdef CONFIG_NEC_NL6448BC20 -#define DISPLAY_WIDTH 640 -#define DISPLAY_HEIGHT 480 - -#ifdef CONFIG_VIDEO_SED13806_8BPP -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0xe5}, /* General IO Pins Control Register 0 */ - {0x0009,0x1f}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x04}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register */ - {0x0041,0x02}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x40}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x01}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x00}, /* TV Output Control Register */ - {0x0060,0x03}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; -#endif /* CONFIG_VIDEO_SED13806_8BPP */ - -#ifdef CONFIG_VIDEO_SED13806_16BPP - -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0xe5}, /* General IO Pins Control Register 0 */ - {0x0009,0x1f}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x04}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x05}, /* LCD Display Mode Register */ - {0x0041,0x02}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x00}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x01}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; - -#endif /* CONFIG_VIDEO_SED13806_16BPP */ -#endif /* CONFIG_NEC_NL6448BC20 */ - - -#ifdef CONFIG_CONSOLE_EXTRA_INFO - -/*----------------------------------------------------------------------------- - * video_get_info_str -- setup a board string: type, speed, etc. - * line_number= location to place info string beside logo - * info= buffer for info string - *----------------------------------------------------------------------------- - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { - strcpy (info, " RPXClassic board"); - } - else { - info [0] = '\0'; - } - -} -#endif - -/*----------------------------------------------------------------------------- - * board_video_init -- init de l'EPSON, config du CS - *----------------------------------------------------------------------------- - */ -unsigned int board_video_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Program ECCX registers */ - *(ECCX_CSR12) |= ECCX_860; - *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2; - *(ECCX_CSR8) |= ECCX_ENEPSON; - - memctl->memc_or2 = SED13806_OR; - memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES; - - return (SED13806_REG_ADDR); -} - -/*----------------------------------------------------------------------------- - * board_validate_screen -- - *----------------------------------------------------------------------------- - */ -void board_validate_screen (unsigned int base) -{ - /* Activate the panel bias power */ - *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80; -} -/*----------------------------------------------------------------------------- - * board_get_regs -- - *----------------------------------------------------------------------------- - */ -const S1D_REGS *board_get_regs (void) -{ - return (init_regs); -} -/*----------------------------------------------------------------------------- - * board_get_width -- - *----------------------------------------------------------------------------- - */ -int board_get_width (void) -{ - return (DISPLAY_WIDTH); -} - -/*----------------------------------------------------------------------------- - * board_get_height -- - *----------------------------------------------------------------------------- - */ -int board_get_height (void) -{ - return (DISPLAY_HEIGHT); -} - -#endif /* CONFIG_VIDEO_SED13806 */ diff --git a/board/RPXClassic/flash.c b/board/RPXClassic/flash.c deleted file mode 100644 index 2e0b8f9..0000000 --- a/board/RPXClassic/flash.c +++ /dev/null @@ -1,447 +0,0 @@ -/* - * (C) Copyright 2001 - * Stäubli Faverges - - * Pierre AUBERT p.aubert@staubli.com - * U-Boot port on RPXClassic LF (CLLF_BW31) board - * - * RPXClassic uses Am29DL323B flash memory with 2 banks - * - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL323B: - printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Reset flash componeny */ - addr [0] = 0xf0f0f0f0; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0xAAAAAAAA ; - addr[0x555] = 0x55555555 ; - addr[0xAAA] = 0x90909090 ; - - value = addr[0] ; - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - switch (value & 0x00FF00FF) { - case (AMD_ID_DL323B & 0x00FF00FF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; /* 16 Mb */ - - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* set up sector start address table */ - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - - /* check for protected sectors */ - for (i = 0; i < 23; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - /* Check for protected sectors in the 2nd bank */ - addr[0x100AAA] = 0xAAAAAAAA ; - addr[0x100555] = 0x55555555 ; - addr[0x100AAA] = 0x90909090 ; - - for (i = 23; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank 1 */ - addr = (volatile unsigned long *)info->start[23]; - - *addr = 0xF0F0F0F0; /* reset bank 2 */ - - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds deleted file mode 100644 index 049f990..0000000 --- a/board/RPXClassic/u-boot.lds +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) -/* XXX ? - . = env_offset; -*/ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug deleted file mode 100644 index ddd4678..0000000 --- a/board/RPXClassic/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite/Makefile b/board/RPXlite/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/RPXlite/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c deleted file mode 100644 index f37e07b..0000000 --- a/board/RPXlite/RPXlite.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * DRAM related UPMA register values are modified. - * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = { - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, - 0x0CFFCC00, 0x33FFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXlite\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CFG_MPTPR; - - memctl->memc_mar = 0x00000000; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - - memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 10 column mode - */ - - size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - return (size10); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/RPXlite/config.mk b/board/RPXlite/config.mk deleted file mode 100644 index 6536b77..0000000 --- a/board/RPXlite/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# RPXlite boards -# - -TEXT_BASE = 0xfff00000 diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c deleted file mode 100644 index 846794d..0000000 --- a/board/RPXlite/flash.c +++ /dev/null @@ -1,524 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -/* volatile immap_t *immap = (immap_t *)CFG_IMMR; */ -/* volatile memctl8xx_t *memctl = &immap->im_memctl; */ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; -%%%*/ - /* Re-do sizing to get full correct info */ - - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0x00AA00AA ; - addr[0x555] = 0x00550055 ; - addr[0xAAA] = 0x00900090 ; - - value = addr[0] ; - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - switch (value & 0x00FF00FF) { - case (AMD_ID_LV400T & 0x00FF00FF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & 0x00FF00FF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & 0x00FF00FF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & 0x00FF00FF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /*%%% Size doubled by yooth */ - break; /* => 4 MB */ - - case (AMD_ID_LV160T & 0x00FF00FF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & 0x00FF00FF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /*%%% sector start address modified */ - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds deleted file mode 100644 index 049f990..0000000 --- a/board/RPXlite/u-boot.lds +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) -/* XXX ? - . = env_offset; -*/ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug deleted file mode 100644 index ddd4678..0000000 --- a/board/RPXlite/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite_dw/Makefile b/board/RPXlite_dw/Makefile deleted file mode 100644 index d457020..0000000 --- a/board/RPXlite_dw/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/RPXlite_dw/README b/board/RPXlite_dw/README deleted file mode 100644 index 28bcb31..0000000 --- a/board/RPXlite_dw/README +++ /dev/null @@ -1,161 +0,0 @@ - -After following the step of Yoo. Jonghoon and Wolfgang Denk, -I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW. - -There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW. - -Board(in U-Boot) version(in EmbeddedPlanet) CPU SDRAM FLASH -RPXlite RPXlite CW 850 16MB 4MB -RPXlite_DW RPXlite DW(EP 823 H1 DW) 823e 64MB 16MB - -This fireware is specially coded for EmbeddedPlanet Co. Software Development -Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel. - -It has the following three features: - -1. 64MHz/48MHz system frequence setting options. -The default setting is 48MHz.To get a 64MHz u-boot,just add -'64' in make command,like - -make distclean -make RPXlite_DW_64_config -make all - -2. CFG_ENV_IS_IN_FLASH/CFG_ENV_IS_IN_NVRAM - -The default environment parameter is stored in FLASH because it is a common choice for -environment parameter.So I make NVRAM as backup parameter storeage.The reason why I -didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter -home.Because of the possibility of using two firewares on this board,I didn't -'disturb' EEPROM.To get NVRAM support,you may use the following build command: - -make distclean -make RPXlite_DW_NVRAM_config -make all - -3. LCD panel support - -To support the Platform better,I added LCD panel(NL6448BC20-08) function. -For the convenience of debug, CONFIG_PERBOOT was supported. So you just -perss ENTER if you want to get a serial console in boot downcounting. -Then you can switch to LCD and serial console freely just typing -'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled. - -To get a LCD support u-boot,you can do the following: - -make distclean -make RPXlite_DW_LCD_config -make all - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The basic make commands could be: - -make RPXlite_DW_config -make RPXlite_DW_64_config -make RPXlite_DW_LCD_config -make RPXlite_DW_NVRAM_config - -BTW,you can combine the above features together and get a workable u-boot to meet your need. -For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type: - -make RPXlite_DW_NVRAM_64_LCD_config -make all - -So other combining make commands could be: - -make RPXlite_DW_NVRAM_64_config -make RPXlite_DW_NVRAM_LCD_config -make RPXlite_DW_64_LCD_config - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The boot process by "make RPXlite_DW_config" could be: - -U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) - -CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache -Board: RPXlite_DW -DRAM: 64 MB -FLASH: 16 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET -u-boot> - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -A word on the U-Boot enviroment variable setting and usage : - -In the beginning, you could just need very simple defult environment variable setting, -like[include/configs/RPXlite.h] : - -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -This is enough for kernel NFS test. But as debug process goes on, you would expect -to save some time on environment variable setting and u-boot/kernel updating. -So the default environment variable setting would become more complicated. Just like -the one I did in include/configs/RPXlite_DW.h. - -Two u-boot commands, ku and uu, should be careful to use. They were designed to update -kernel and u-boot image file respectively. You must tftp your image to default address -'100000' and then use them correctly. Yeah, you can create your own command to do this -job. :-) The example u-boot image updating process could be : - -u-boot>t 100000 RPXlite_DW_LCD.bin -Using SCC ETHERNET device -TFTP from server 172.16.115.6; our IP address is 172.16.115.7 -Filename 'RPXlite_DW_LCD.bin'. -Load address: 0x100000 -Loading: ############################# -done -Bytes transferred = 144700 (2353c hex) -u-boot>run uu -Un-Protect Flash Sectors 0-4 in Bank # 1 -Erase Flash Sectors 0-4 in Bank # 1 -.... done -Copy to Flash... done -ff000000: 27051956 552d426f 6f742031 2e312e32 '..VU-Boot 1.1.2 -ff000010: 20284175 67203239 20323030 34202d20 (Aug 29 2004 - -ff000020: 31353a32 303a3238 29000000 00000000 15:20:28)....... -ff000030: 00000000 00000000 00000000 00000000 ................ -ff000040: 00000000 00000000 00000000 00000000 ................ -ff000050: 00000000 00000000 00000000 00000000 ................ -ff000060: 00000000 00000000 00000000 00000000 ................ -ff000070: 00000000 00000000 00000000 00000000 ................ -ff000080: 00000000 00000000 00000000 00000000 ................ -ff000090: 00000000 00000000 00000000 00000000 ................ -ff0000a0: 00000000 00000000 00000000 00000000 ................ -ff0000b0: 00000000 00000000 00000000 00000000 ................ -ff0000c0: 00000000 00000000 00000000 00000000 ................ -ff0000d0: 00000000 00000000 00000000 00000000 ................ -ff0000e0: 00000000 00000000 00000000 00000000 ................ -ff0000f0: 00000000 00000000 00000000 00000000 ................ -u-boot updating finished -u-boot> - -Also for environment updating, 'run eu' could let you erase OLD default environment variable -and then use the working u-boot environment setting. - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Finally, if you want to keep the serial port to possible debug on spot for deployment, you -just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string -defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot. - -I'd like to extend my heartfelt gratitute to kind people for helping me work it out. -I would particually thank Wolfgang Denk for his nice help. - -Enjoy, - -Sam Song, samsongshu@yahoo.com.cn -Institute of Electrical Machinery and Controls -Shanghai University - -Oct. 11, 2004 diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c deleted file mode 100644 index 237c58a..0000000 --- a/board/RPXlite_dw/RPXlite_dw.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2004 - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Sam Song - * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW - * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz - * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75. - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ -static long int dram_size (long int, long int *, long int); -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, - 0x01FFCC20, 0x1FF74C20, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */ - _NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35, - _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, - 0x01FFFC24, 0x1FF74C25, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, - 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4, - /* INIT sequence RAM WORDS - * SDRAM Initialization (offset 0x36 in UPMA RAM) - * The above definition uses the remaining space - * to establish an initialization sequence, - * which is executed by a RUN command. - * The sequence is COMMAND INHIBIT(NOP),Precharge, - * Load Mode Register,NOP,Auto Refresh. - */ - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ -}; - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXlite_DW\n") ; - return (0) ; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size9; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CFG_MPTPR ; - - memctl->memc_mar = 0x00000088; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - - memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ - /*Disable Periodic timer A. */ - - udelay(200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002236; /* SDRAM bank 0 - refresh twice */ - - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - /*Enable Periodic timer A */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 9 column mode - */ - - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); - - /* - * Final mapping: - */ - - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - - udelay (1000); - - return (size9); -} - -void rpxlite_init (void) -{ - /* Enable NVRAM */ - *((uchar *) BCSR0) |= BCSR0_ENNVRAM; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/RPXlite_dw/config.mk b/board/RPXlite_dw/config.mk deleted file mode 100644 index 7970910..0000000 --- a/board/RPXlite_dw/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# RPXlite dw boards : lite_dw -# - -TEXT_BASE = 0xff000000 diff --git a/board/RPXlite_dw/flash.c b/board/RPXlite_dw/flash.c deleted file mode 100644 index 1cbd537..0000000 --- a/board/RPXlite_dw/flash.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -/* Yes,Yoo.They do use other FLASH for the board. - * - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * U-Boot port on RPXlite DW version board - * - * By now,it uses 4 AM29DL323DB90VI devices(4x8bit). - * The total FLASH has 16MB(4x4MB). - * I just made some necessary changes on the basis of Wolfgang and Yoo's job. - * - * June 8, 2004 */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions vu_long : volatile unsigned long IN include/common.h - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -unsigned long flash_init (void) -{ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE - /* If Monitor is in the cope of FLASH,then - * protect this area by default in case for - * other occupation. [SAM] */ - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, - &flash_info[0]); -#endif - flash_info[0].size = size_b0; - return (size_b0); -} - -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000); - } - } else { - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sector)\n"); - break; - /* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM] */ - default: printf ("Unknown Chip Type\n"); - break; - } - printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count); - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0x00AA00AA ; - addr[0x555] = 0x00550055 ; - addr[0xAAA] = 0x00900090 ; - - value = addr[0] ; - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: /* AMD_MANUFACT=0x00010001 in flash.h. */ - info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/ - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - switch (value & 0x00FF00FF) { - case (AMD_ID_LV400T & 0x00FF00FF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - case (AMD_ID_LV400B & 0x00FF00FF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - case (AMD_ID_LV800T & 0x00FF00FF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - case (AMD_ID_LV800B & 0x00FF00FF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /* Size doubled by yooth */ - break; /* => 4 MB */ - case (AMD_ID_LV160T & 0x00FF00FF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - case (AMD_ID_LV160B & 0x00FF00FF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - case (AMD_ID_DL323B & 0x00FF00FF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* => 16 MB(4x4MB) */ - /* AMD_ID_DL323B= 0x22532253 FLASH_AMDL323B= 0x0013 - * AMD_ID_DL323B could be found in .[SAM] - * So we could get : flash_id = 0x00000013. - * The first four-bit represents VEDOR ID,leaving others for FLASH ID. */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1, - * it means bottom boot flash. GOOD IDEA! [SAM] - */ - - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - /* info->protect[i] = addr[4] & 1 ; */ - /* Mask it for disorder FLASH protection **[Sam]** */ - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank */ - } - return (info->size); -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds deleted file mode 100644 index a9c88f6..0000000 --- a/board/RPXlite_dw/u-boot.lds +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) -/* XXX ? - . = env_offset; -*/ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug deleted file mode 100644 index c0cf1cb..0000000 --- a/board/RPXlite_dw/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/RRvision/Makefile b/board/RRvision/Makefile deleted file mode 100644 index fdc6fd5..0000000 --- a/board/RRvision/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/RRvision/RRvision.c b/board/RRvision/RRvision.c deleted file mode 100644 index f46bb9e..0000000 --- a/board/RRvision/RRvision.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Always return 1 (no second DRAM bank). - */ - -int checkboard (void) -{ - char *s = getenv ("serial#"); - - puts ("Board: RRvision "); - - for (; s && *s; ++s) { - if (*s == ' ') - break; - putc (*s); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long reg; - long int size8, size9; - long int size = 0; - - upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 1 the SDRAM bank 2 at physical address 0. - */ - memctl->memc_or1 = CFG_OR2_PRELIM; - memctl->memc_br1 = CFG_BR2_PRELIM; - - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, - SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, - SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type - * For types > 128 MBit leave it at the current (fast) rate - */ - if (size < 0x02000000) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - memctl->memc_or1 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/RRvision/config.mk b/board/RRvision/config.mk deleted file mode 100644 index ab1c8d6..0000000 --- a/board/RRvision/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# RedRock vision boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/RRvision/flash.c b/board/RRvision/flash.c deleted file mode 100644 index d8e07e6..0000000 --- a/board/RRvision/flash.c +++ /dev/null @@ -1,522 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define DEBUG - -#include -#include - -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: puts ("AMD "); break; - case FLASH_MAN_FUJ: puts ("FUJITSU "); break; - default: puts ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: puts ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - puts ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - puts ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - switch (value) { - case AMD_ID_LV400B: - case AMD_ID_LV800B: - case AMD_ID_LV160B: - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - break; - case AMD_ID_LV400T: - case AMD_ID_LV800T: - case AMD_ID_LV160T: - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - break; - case AMD_ID_LV320B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - case AMD_ID_LV320T: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The last 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < (info->sector_count - 8)) - ? 2 * (64 << 10) - : 2 * ( 8 << 10); - } - break; - default: - return (0); - break; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - puts ("- missing\n"); - } else { - puts ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - puts ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - puts ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - puts (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds deleted file mode 100644 index 1d6288f..0000000 --- a/board/RRvision/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = env_offset; - common/environment.o (.ppcenv) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/RRvision/video_ad7179.h b/board/RRvision/video_ad7179.h deleted file mode 100644 index f146738..0000000 --- a/board/RRvision/video_ad7179.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2003 Wolfgang Grandegger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define VIDEO_ENCODER_NAME "Analog Devices AD7179" - -#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */ -#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */ - -#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */ -#undef VIDEO_MODE_RGB -#define VIDEO_MODE_BPP 16 - -#ifdef VIDEO_MODE_PAL -#define VIDEO_ACTIVE_COLS 720 -#define VIDEO_ACTIVE_ROWS 576 -#define VIDEO_VISIBLE_COLS 640 -#define VIDEO_VISIBLE_ROWS 480 -#else -#error "NTSC mode is not supported" -#endif - -static unsigned char video_encoder_data[] = { - 0x05, /* Mode Register 0 */ - 0x11, /* Mode Register 1 */ - 0x20, /* Mode Register 2 */ - 0x0C, /* Mode Register 3 */ - 0x01, /* Mode Register 4 */ - 0x00, /* Reserved */ - 0x00, /* Reserved */ - 0x04, /* Timing Register 0 */ - 0x00, /* Timing Register 1 */ - 0xCB, /* Subcarrier Frequency Register 0 */ - 0x0A, /* Subcarrier Frequency Register 1 */ - 0x09, /* Subcarrier Frequency Register 2 */ - 0x2A, /* Subcarrier Frequency Register 3 */ - 0x00, /* Subcarrier Phase */ - 0x00, /* Closed Captioning Ext Reg 0 */ - 0x00, /* Closed Captioning Ext Reg 1 */ - 0x00, /* Closed Captioning Reg 0 */ - 0x00, /* Closed Captioning Reg 1 */ - 0x00, /* Pedestal Control Reg 0 */ - 0x00, /* Pedestal Control Reg 1 */ - 0x00, /* Pedestal Control Reg 2 */ - 0x00, /* Pedestal Control Reg 3 */ - 0x00, /* CGMS_WSS Reg 0 */ - 0x00, /* CGMS_WSS Reg 0 */ - 0x00, /* CGMS_WSS Reg 0 */ - 0x00 /* Teletext Req. Control Reg */ -} ; diff --git a/board/a3000/Makefile b/board/a3000/Makefile deleted file mode 100644 index 5fde362..0000000 --- a/board/a3000/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/a3000/README b/board/a3000/README deleted file mode 100644 index f0e92c5..0000000 --- a/board/a3000/README +++ /dev/null @@ -1,17 +0,0 @@ -U-Boot for Artis SBC-A3000 ---------------------------- - -Artis SBC-A3000 has one flash socket that the user uses Intel 28F128J3A (16MB) -or 28F064J3A (8MB) chips. - -In board's notation, bank 0 is the one at the address of 0xFF000000. -bank 1 is the one at the address of 0xFF800000 - -On power-up the processor jumps to the address of 0xFFF00100, the last -megabyte of the bank 0 of flash. - -Thus, U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is located in flash separately from -U-Boot, at the address of 0xFFFE0000. - -There is a National ns83815 10/100M ethernet controller on-board. diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c deleted file mode 100644 index ab707ae..0000000 --- a/board/a3000/a3000.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * Modified during 2003 by - * Ken Chou, kchou@ieee.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -int checkboard (void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; - -} - -long int initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_a3000_config_table[] = { - /* vendor, device, class */ - /* bus, dev, func */ - { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */ - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */ - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */ - pci_cfgfunc_config_device, { PCI_ENET2_IOADDR, - PCI_ENET2_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */ - pci_cfgfunc_config_device, { PCI_ENET3_IOADDR, - PCI_ENET3_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_a3000_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} diff --git a/board/a3000/config.mk b/board/a3000/config.mk deleted file mode 100644 index 798e032..0000000 --- a/board/a3000/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Artis A-3000 boards -# - -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/a3000/flash.c b/board/a3000/flash.c deleted file mode 100644 index 13a5ca5..0000000 --- a/board/a3000/flash.c +++ /dev/null @@ -1,454 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - - -/*---------------------------------------------------------------------*/ -#define DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_data (flash_info_t *info, uchar *dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -#define BS(b) (b) -#define BYTEME(x) ((x) & 0xFF) - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long flash_banks[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS; - unsigned long size, size_b[CFG_MAX_FLASH_BANKS]; - - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE - DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, CFG_MONITOR_LEN); - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - DEBUGF("protect environtment %x @ %x\n", CFG_ENV_ADDR, CFG_ENV_SECT_SIZE); - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - size = 0; - DEBUGF("## Final Flash bank sizes: "); - for (i=0; iflash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x00020000; /* 128k per bank */ - } - return; - - default: - printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id); - return; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A (32Mbit = 128K x 32)\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A (64Mbit = 128K x 64)\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - -#if 1 - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -#endif - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ - vu_char manuf, device; - - addr[0] = BS(0x90); - manuf = BS(addr[0]); - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, manuf); - - switch (manuf) { - case BYTEME(AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - case BYTEME(FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - case BYTEME(SST_MANUFACT): - info->flash_id = FLASH_MAN_SST; - break; - case BYTEME(STM_MANUFACT): - info->flash_id = FLASH_MAN_STM; - break; - case BYTEME(INTEL_MANUFACT): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */ - return 0; /* no or unknown flash */ - } - - device = BS(addr[2]); /* device ID */ - - DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", (ulong)(&addr[1]), device); - - switch (device) { - case BYTEME(INTEL_ID_28F320J3A): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case BYTEME(INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case BYTEME(INTEL_ID_28F128J3A): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */ - return 0; /* => no or unknown flash */ - - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = BS(0xFF); /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_char *addr = (vu_char *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x50); /* clear status register */ - *addr = BS(0x20); /* erase setup */ - *addr = BS(0xD0); /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = BS(0xB0); /* suspend erase */ - *addr = BS(0xFF); /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = BS(0xFF); /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 1 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - uchar *wp = (uchar *)addr; - int rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - while (cnt > 0) { - if ((rc = write_data(info, wp, *src)) != 0) { - return rc; - } - wp++; - src++; - cnt--; - } - - return cnt; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, uchar *dest, uchar data) -{ - vu_char *addr = (vu_char *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((BS(*addr) & data) != data) { - return 2; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x40); /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - start = get_timer (0); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *addr = BS(0xFF); /* restore read mode */ - return 1; - } - } - - *addr = BS(0xFF); /* restore read mode */ - - return 0; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/a3000/u-boot.lds b/board/a3000/u-boot.lds deleted file mode 100644 index acb9ffd..0000000 --- a/board/a3000/u-boot.lds +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/adder/Makefile b/board/adder/Makefile deleted file mode 100644 index 9123a80..0000000 --- a/board/adder/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# Copyright (C) 2004 Arabella Software Ltd. -# Yuli Barcohen -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/adder/adder.c b/board/adder/adder.c deleted file mode 100644 index cab6e2f..0000000 --- a/board/adder/adder.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Analogue&Micro Adder boards family. - * Tested on AdderII and Adder87x. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* - * SDRAM is single Samsung K4S643232F-T70 chip. - * Minimal CPU frequency is 40MHz. - */ -static uint sdram_table[] = { - /* Single read (offset 0x00 in UPM RAM) */ - 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00, - 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04, - - /* Burst read (offset 0x08 in UPM RAM) */ - 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44, - 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35, - 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35, - - /* Single write (offset 0x18 in UPM RAM) */ - 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47, - 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Burst write (offset 0x20 in UPM RAM) */ - 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Refresh (offset 0x30 in UPM RAM) */ - 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Exception (offset 0x3C in UPM RAM) */ - 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04 -}; - -long int initdram (int board_type) -{ - long int msize = CFG_SDRAM_SIZE; - volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* Configure SDRAM refresh */ - memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */ - - memctl->memc_mamr = (94 << 24) | CFG_MAMR; - memctl->memc_mar = 0x0; - udelay(200); - - /* Run precharge from location 0x15 */ - memctl->memc_mcr = 0x80002115; - udelay(200); - - /* Run 8 refresh cycles */ - memctl->memc_mcr = 0x80002830; - udelay(200); - - memctl->memc_mar = 0x88; - udelay(200); - - /* Run MRS pattern from location 0x16 */ - memctl->memc_mcr = 0x80002116; - udelay(200); - - return msize; -} - -int checkboard( void ) -{ - puts("Board: Adder"); -#if defined(CONFIG_MPC885_FAMILY) - puts("87x\n"); -#elif defined(CONFIG_MPC866_FAMILY) - puts("II\n"); -#endif - - return 0; -} diff --git a/board/adder/config.mk b/board/adder/config.mk deleted file mode 100644 index 4691a69..0000000 --- a/board/adder/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (C) 2004 Arabella Software Ltd. -# Yuli Barcohen -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Analogue&Micro Adder boards family -# -TEXT_BASE = 0xFE000000 diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds deleted file mode 100644 index 66c3246..0000000 --- a/board/adder/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Yuli Barcohen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/adsvix/Makefile b/board/adsvix/Makefile deleted file mode 100644 index 24d5d06..0000000 --- a/board/adsvix/Makefile +++ /dev/null @@ -1,48 +0,0 @@ - -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := adsvix.o pcmcia.o -SOBJS := lowlevel_init.o pxavoltage.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/adsvix/adsvix.c b/board/adsvix/adsvix.c deleted file mode 100644 index 5e770e9..0000000 --- a/board/adsvix/adsvix.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of ADSVIX-Board */ - gd->bd->bi_arch_number = 620; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa000003c; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; - - return 0; -} diff --git a/board/adsvix/config.mk b/board/adsvix/config.mk deleted file mode 100644 index 98be4eb..0000000 --- a/board/adsvix/config.mk +++ /dev/null @@ -1 +0,0 @@ -TEXT_BASE = 0xa1700000 diff --git a/board/adsvix/lowlevel_init.S b/board/adsvix/lowlevel_init.S deleted file mode 100644 index 8dea71c..0000000 --- a/board/adsvix/lowlevel_init.S +++ /dev/null @@ -1,466 +0,0 @@ -/* - * This was originally from the Lubbock u-boot port. - * - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - - -/* - * Memory setup - */ - -.globl lowlevel_init -lowlevel_init: - - /* Set up GPIO pins first ----------------------------------------- */ - - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPSR3 - ldr r1, =CFG_GPSR3_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPCR3 - ldr r1, =CFG_GPCR3_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GPDR3 - ldr r1, =CFG_GPDR3_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =GAFR3_L - ldr r1, =CFG_GAFR3_L_VAL - str r1, [r0] - - ldr r0, =GAFR3_U - ldr r1, =CFG_GAFR3_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1, =MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - ldr r2, =CFG_FLYCNFG_VAL - str r2, [r1, #FLYCNFG_OFFSET] - str r2, [r1, #FLYCNFG_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r4, [r1, #MDREFR_OFFSET] - ldr r2, =0xFFF - bic r4, r4, r2 - - ldr r3, =CFG_MDREFR_VAL - and r3, r3, r2 - - orr r4, r4, r3 - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - - orr r4, r4, #MDREFR_K0RUN - orr r4, r4, #MDREFR_K0DB4 - orr r4, r4, #MDREFR_K0FREE - orr r4, r4, #MDREFR_K0DB2 - orr r4, r4, #MDREFR_K1DB2 - bic r4, r4, #MDREFR_K1FREE - bic r4, r4, #MDREFR_K2FREE - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ - - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - ldr r2, =CFG_SXCNFG_VAL - str r2, [r1, #SXCNFG_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) - - orr r4, r4, #MDREFR_K1RUN - bic r4, r4, #MDREFR_K2DB2 - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - bic r4, r4, #MDREFR_SLFRSH - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - orr r4, r4, #MDREFR_E1PIN - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - nop - nop - - - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ - /* configure but not enable each SDRAM partition pair. */ - - ldr r4, =CFG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - ldr r3, =CFG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* (MDCNFG:DEx set to 1). */ - - ldr r3, [r1, #MDCNFG_OFFSET] - mov r4, r3 - orr r3, r3, #MDCNFG_DE0 - str r3, [r1, #MDCNFG_OFFSET] - mov r0, r3 - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - /* enable APD */ - ldr r3, [r1, #MDREFR_OFFSET] - orr r3, r3, #MDREFR_APD - str r3, [r1, #MDREFR_OFFSET] - - /* We are finished with Intel's memory controller initialisation */ - -setvoltage: - - mov r10, lr - bl initPXAvoltage /* In case the board is rebooting with a */ - mov lr, r10 /* low voltage raise it up to a good one. */ - -wakeup: - /* Are we waking from sleep? */ - ldr r0, =RCSR - ldr r1, [r0] - and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) - str r1, [r0] - teq r1, #RCSR_SMR - - bne initirqs - - ldr r0, =PSSR - mov r1, #PSSR_PH - str r1, [r0] - - /* if so, resume at PSPR */ - ldr r0, =PSPR - ldr r1, [r0] - mov pc, r1 - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - - /* Turn Off on-chip peripheral clocks (except for memory) */ - /* for re-configuration. */ - ldr r1, =CKEN - ldr r2, =CFG_CKEN - str r2, [r1] - - /* ... and write the core clock config register */ - ldr r2, =CFG_CCCR - ldr r1, =CCCR - str r2, [r1] - - /* Turn on turbo mode */ - mrc p14, 0, r2, c6, c0, 0 - orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ - mcr p14, 0, r2, c6, c0, 0 - - /* Re-write MDREFR */ - ldr r1, =MEMC_BASE - ldr r2, [r1, #MDREFR_OFFSET] - str r2, [r1, #MDREFR_OFFSET] -#ifdef RTC - /* enable the 32Khz oscillator for RTC and PowerManager */ - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#else -#error "RTC not defined" -#endif - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - /* FIXME */ - -#ifdef NODEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ -#endif - - /* ---------------------------------------------------------------- */ - /* End lowlevel_init */ - /* ---------------------------------------------------------------- */ - -endlowlevel_init: - - mov pc, lr diff --git a/board/adsvix/pcmcia.c b/board/adsvix/pcmcia.c deleted file mode 100644 index ba5be01..0000000 --- a/board/adsvix/pcmcia.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -void pcmcia_power_on(void) -{ -#if 0 - if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */ - GPCR(81) = GPIO_bit(81); - GPSR(82) = GPIO_bit(82); - } - else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */ - GPCR(81) = GPIO_bit(81); - GPCR(82) = GPIO_bit(82); - } -#else -#warning "Board will only supply 5V, wait for next HW spin for selectable power" - /* 5.0V */ - GPCR(81) = GPIO_bit(81); - GPCR(82) = GPIO_bit(82); -#endif - - udelay(300000); - - /* reset the card */ - GPSR(52) = GPIO_bit(52); - - /* enable PCMCIA */ - GPCR(83) = GPIO_bit(83); - - /* clear reset */ - udelay(10); - GPCR(52) = GPIO_bit(52); - - udelay(20000); -} - -void pcmcia_power_off(void) -{ - /* 0V */ - GPSR(81) = GPIO_bit(81); - GPSR(82) = GPIO_bit(82); - /* disable PCMCIA */ - GPSR(83) = GPIO_bit(83); -} diff --git a/board/adsvix/pxavoltage.S b/board/adsvix/pxavoltage.S deleted file mode 100644 index 2fe1cab..0000000 --- a/board/adsvix/pxavoltage.S +++ /dev/null @@ -1,230 +0,0 @@ -/* - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define LTC1663_ADDR 0x20 - -#define LTC1663_SY 0x01 /* Sync ACK */ -#define LTC1663_SD 0x04 /* shutdown */ -#define LTC1663_BG 0x04 /* Internal Voltage Ref */ - -#define VOLT_1_55 18 /* DAC value for 1.55V */ - - .global initPXAvoltage - -@ Set the voltage to 1.55V early in the boot process so we can run -@ at a high clock speed and boot quickly. Note that this is necessary -@ because the reset button does not reset the CPU voltage, so if the -@ voltage was low (say 0.85V) then the CPU would crash without this -@ routine - -@ This routine clobbers r0-r4 - -initializei2c: - - ldr r2, =CKEN - ldr r3, [r2] - orr r3, r3, #CKEN15_PWRI2C - str r3, [r2] - - ldr r2, =PCFR - ldr r3, [r2] - orr r3, r3, #PCFR_PI2C_EN - str r3, [r2] - - /* delay for about 250msec - */ - ldr r3, =OSCR - mov r2, #0 - str r2, [r3] - ldr r1, =0xC0000 - -1: - ldr r2, [r3] - cmp r1, r2 - bgt 1b - ldr r0, =PWRICR - ldr r1, [r0] - bic r1, r1, #(ICR_MA | ICR_START | ICR_STOP) - str r1, [r0] - - orr r1, r1, #ICR_UR - str r1, [r0] - - ldr r2, =PWRISR - ldr r3, =0x7ff - str r3, [r2] - - bic r1, r1, #ICR_UR - str r1, [r0] - - mov r1, #(ICR_GCD | ICR_SCLE) - str r1, [r0] - - orr r1, r1, #ICR_IUE - str r1, [r0] - - orr r1, r1, #ICR_FM - str r1, [r0] - - /* delay for about 1msec - */ - ldr r3, =OSCR - mov r2, #0 - str r2, [r3] - ldr r1, =0xC00 - -1: - ldr r2, [r3] - cmp r1, r2 - bgt 1b - mov pc, lr - -sendbytei2c: - ldr r3, =PWRIDBR - str r0, [r3] - ldr r3, =PWRICR - ldr r0, [r3] - orr r0, r0, r1 - bic r0, r0, r2 - str r0, [r3] - orr r0, r0, #ICR_TB - str r0, [r3] - - mov r2, #0x100000 - -waitfortxemptyi2c: - - ldr r0, =PWRISR - ldr r1, [r0] - - /* take it from the top if we don't get empty after a while */ - subs r2, r2, #1 - moveq lr, r4 - beq initPXAvoltage - - tst r1, #ISR_ITE - - beq waitfortxemptyi2c - - orr r1, r1, #ISR_ITE - str r1, [r0] - - mov pc, lr - -initPXAvoltage: - - mov r4, lr - - bl setleds - - bl initializei2c - - bl setleds - - /* now send the real message to set the correct voltage */ - ldr r0, =LTC1663_ADDR - mov r0, r0, LSL #1 - mov r1, #ICR_START - ldr r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK) - bl sendbytei2c - - bl setleds - - mov r0, #LTC1663_BG - mov r1, #0 - mov r2, #(ICR_STOP | ICR_START) - bl sendbytei2c - - bl setleds - - ldr r0, =VOLT_1_55 - and r0, r0, #0xff - mov r1, #0 - mov r2, #(ICR_STOP | ICR_START) - bl sendbytei2c - - bl setleds - - ldr r0, =VOLT_1_55 - mov r0, r0, ASR #8 - and r0, r0, #0xff - mov r1, #ICR_STOP - mov r2, #ICR_START - bl sendbytei2c - - bl setleds - - @ delay a little for the volatage to stablize - ldr r3, =OSCR - mov r2, #0 - str r2, [r3] - ldr r1, =0xC0 - -1: - ldr r2, [r3] - cmp r1, r2 - bgt 1b - mov pc, r4 - -setleds: - mov pc, lr - - ldr r5, =0x40e00058 - ldr r3, [r5] - bic r3, r3, #0x3 - str r3, [r5] - ldr r5, =0x40e0000c - ldr r3, [r5] - orr r3, r3, #0x00010000 - str r3, [r5] - - @ inner loop - mov r0, #0x2 -1: - - ldr r5, =0x40e00018 - mov r3, #0x00010000 - str r3, [r5] - - @ outer loop - mov r3, #0x00F00000 -2: - subs r3, r3, #1 - bne 2b - - ldr r5, =0x40e00024 - mov r3, #0x00010000 - str r3, [r5] - - @ outer loop - mov r3, #0x00F00000 -3: - subs r3, r3, #1 - bne 3b - - subs r0, r0, #1 - bne 1b - - mov pc, lr diff --git a/board/adsvix/u-boot.lds b/board/adsvix/u-boot.lds deleted file mode 100644 index f010239..0000000 --- a/board/adsvix/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/alaska/Makefile b/board/alaska/Makefile deleted file mode 100644 index a4c1d2e..0000000 --- a/board/alaska/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# (C) Copyright 2003-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c deleted file mode 100644 index 93874b2..0000000 --- a/board/alaska/alaska.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * (C) Copyright 2004, Freescale Inc. - * TsiChung Liew, Tsi-Chung.Liew@freescale.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -void setupBat (ulong size) -{ - ulong batu, batl; - int blocksize = 0; - - /* Flash 0 */ -#if defined (CFG_AMD_BOOT) - batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; -#else - batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; -#endif - batl = CFG_FLASH0_BASE | 0x22; - write_bat (IBAT0, batu, batl); - write_bat (DBAT0, batu, batl); - - /* Flash 1 */ -#if defined (CFG_AMD_BOOT) - batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; -#else - batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; -#endif - batl = CFG_FLASH1_BASE | 0x22; - write_bat (IBAT1, batu, batl); - write_bat (DBAT1, batu, batl); - - /* CPLD */ - batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; - batl = CFG_CPLD_BASE | 0x22; - write_bat (IBAT2, 0, 0); - write_bat (DBAT2, batu, batl); - - /* FPGA */ - batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; - batl = CFG_FPGA_BASE | 0x22; - write_bat (IBAT3, 0, 0); - write_bat (DBAT3, batu, batl); - - /* MBAR - Data only */ - batu = CFG_MBAR | BPP_RW | BPP_RX; - batl = CFG_MBAR | 0x22; - mtspr (IBAT4L, 0); - mtspr (IBAT4U, 0); - mtspr (DBAT4L, batl); - mtspr (DBAT4U, batu); - - /* MBAR - SRAM */ - batu = CFG_SRAM_BASE | BPP_RW | BPP_RX; - batl = CFG_SRAM_BASE | 0x42; - mtspr (IBAT5L, batl); - mtspr (IBAT5U, batu); - mtspr (DBAT5L, batl); - mtspr (DBAT5U, batu); - - if (size <= 0x800000) /* 8MB */ - blocksize = BL_8M << 2; - else if (size <= 0x1000000) /* 16MB */ - blocksize = BL_16M << 2; - else if (size <= 0x2000000) /* 32MB */ - blocksize = BL_32M << 2; - else if (size <= 0x4000000) /* 64MB */ - blocksize = BL_64M << 2; - else if (size <= 0x8000000) /* 128MB */ - blocksize = BL_128M << 2; - else if (size <= 0x10000000) /* 256MB */ - blocksize = BL_256M << 2; - - /* Memory */ - batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX; - batl = CFG_SDRAM_BASE | 0x42; - mtspr (IBAT6L, batl); - mtspr (IBAT6U, batu); - mtspr (DBAT6L, batl); - mtspr (DBAT6U, batu); - - /* memory size is less than 256MB */ - if (size <= 0x10000000) { - /* Nothing */ - batu = 0; - batl = 0; - } else { - size -= 0x10000000; - if (size <= 0x800000) /* 8MB */ - blocksize = BL_8M << 2; - else if (size <= 0x1000000) /* 16MB */ - blocksize = BL_16M << 2; - else if (size <= 0x2000000) /* 32MB */ - blocksize = BL_32M << 2; - else if (size <= 0x4000000) /* 64MB */ - blocksize = BL_64M << 2; - else if (size <= 0x8000000) /* 128MB */ - blocksize = BL_128M << 2; - else if (size <= 0x10000000) /* 256MB */ - blocksize = BL_256M << 2; - - batu = (CFG_SDRAM_BASE + - 0x10000000) | blocksize | BPP_RW | BPP_RX; - batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42; - } - - mtspr (IBAT7L, batl); - mtspr (IBAT7U, batu); - mtspr (DBAT7L, batl); - mtspr (DBAT7U, batu); -} - -long int initdram (int board_type) -{ - ulong size; - - size = dramSetup (); - -/* if iCache ad dCache is defined */ -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) -/* setupBat(size);*/ -#endif - - return size; -} - -int checkboard (void) -{ - puts ("Board: Alaska MPC8220 Evaluation Board\n"); - - return 0; -} diff --git a/board/alaska/config.mk b/board/alaska/config.mk deleted file mode 100644 index 99d28a5..0000000 --- a/board/alaska/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# alaska board -# - -TEXT_BASE = 0xfff00000 -# TEXT_BASE = 0x00100000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/alaska/flash.c b/board/alaska/flash.c deleted file mode 100644 index 383491f..0000000 --- a/board/alaska/flash.c +++ /dev/null @@ -1,936 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH8 - -typedef unsigned char FLASH_PORT_WIDTH; -typedef volatile unsigned char FLASH_PORT_WIDTHV; - -#define SWAP(x) (x) - -/* Intel-compatible flash ID */ -#define INTEL_COMPAT 0x89 -#define INTEL_ALT 0xB0 - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x10 -#define INTEL_ERASE 0x20 -#define INTEL_CLEAR 0x50 -#define INTEL_LOCKBIT 0x60 -#define INTEL_PROTECT 0x01 -#define INTEL_STATUS 0x70 -#define INTEL_READID 0x90 -#define INTEL_CONFIRM 0xD0 -#define INTEL_RESET 0xFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x80 -#define INTEL_OK 0x80 - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -#define WR_BLOCK 0x20 -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static int write_data_block (flash_info_t * info, ulong src, ulong dest); -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -static void flash_sync_real_protect (flash_info_t * info); -static unsigned char intel_sector_protected (flash_info_t *info, ushort sector); -static unsigned char same_chip_banks (int bank1, int bank2); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - ulong fsize = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - memset (&flash_info[i], 0, sizeof (flash_info_t)); - - switch (i) { - case 0: - flash_get_size ((FPW *) CFG_FLASH1_BASE, - &flash_info[i]); - flash_get_offsets (CFG_FLASH1_BASE, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) CFG_FLASH1_BASE, - &flash_info[i]); - fsize = CFG_FLASH1_BASE + flash_info[i - 1].size; - flash_get_offsets (fsize, &flash_info[i]); - break; - case 2: - flash_get_size ((FPW *) CFG_FLASH0_BASE, - &flash_info[i]); - flash_get_offsets (CFG_FLASH0_BASE, &flash_info[i]); - break; - case 3: - flash_get_size ((FPW *) CFG_FLASH0_BASE, - &flash_info[i]); - fsize = CFG_FLASH0_BASE + flash_info[i - 1].size; - flash_get_offsets (fsize, &flash_info[i]); - break; - default: - panic ("configured to many flash banks!\n"); - break; - } - size += flash_info[i].size; - - /* get the h/w and s/w protection status in sync */ - flash_sync_real_protect(&flash_info[i]); - } - - /* Protect monitor and environment sectors - */ -#if defined (CFG_AMD_BOOT) - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[2]); - flash_protect (FLAG_PROTECT_SET, - CFG_INTEL_BASE, - CFG_INTEL_BASE + monitor_flash_len - 1, - &flash_info[1]); -#else - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[3]); - flash_protect (FLAG_PROTECT_SET, - CFG_AMD_BASE, - CFG_AMD_BASE + monitor_flash_len - 1, &flash_info[0]); -#endif - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV1_ADDR, - CFG_ENV1_ADDR + CFG_ENV1_SIZE - 1, &flash_info[1]); - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[3]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) - return; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_AMD_SECT_SIZE); - info->protect[i] = 0; - } - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - case FLASH_MAN_AMD: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - - case FLASH_AM040: - printf ("AMD29F040B\n"); - break; - - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - FPWV value; - static int amd = 0; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ - __asm__ ("sync"); - addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ - __asm__ ("sync"); - addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */ - __asm__ ("sync"); - - udelay (100); - - switch (addr[0] & 0xff) { - - case (uchar) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - value = addr[1]; - break; - - case (uchar) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - value = addr[2]; - break; - - default: - printf ("unknown\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 64; - info->size = 0x00800000; /* => 16 MB */ - break; - - case (FPW) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - if (amd == 0) { - info->sector_count = 7; - info->size = 0x00070000; /* => 448 KB */ - amd = 1; - } else { - /* for Environment settings */ - info->sector_count = 1; - info->size = PHYS_AMD_SECT_SIZE; /* => 64 KB */ - amd = 0; - } - break; - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - if (value == (FPW) INTEL_ID_28F128J3A) - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - else - addr[0] = (FPW) 0x00F000F0; /* restore read mode */ - - return (info->size); -} - - -/* - * This function gets the u-boot flash sector protection status - * (flash_info_t.protect[]) in sync with the sector protection - * status stored in hardware. - */ -static void flash_sync_real_protect (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - for (i = 0; i < info->sector_count; ++i) { - info->protect[i] = intel_sector_protected(info, i); - } - break; - case FLASH_AM040: - default: - /* no h/w protect support */ - break; - } -} - - -/* - * checks if "sector" in bank "info" is protected. Should work on intel - * strata flash chips 28FxxxJ3x in 8-bit mode. - * Returns 1 if sector is protected (or timed-out while trying to read - * protection status), 0 if it is not. - */ -static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) -{ - FPWV *addr; - FPWV *lock_conf_addr; - ulong start; - unsigned char ret; - - /* - * first, wait for the WSM to be finished. The rationale for - * waiting for the WSM to become idle for at most - * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy - * because of: (1) erase, (2) program or (3) lock bit - * configuration. So we just wait for the longest timeout of - * the (1)-(3), i.e. the erase timeout. - */ - - /* wait at least 35ns (W12) before issuing Read Status Register */ - udelay(1); - addr = (FPWV *) info->start[sector]; - *addr = (FPW) INTEL_STATUS; - - start = get_timer (0); - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { - *addr = (FPW) INTEL_RESET; /* restore read mode */ - printf("WSM busy too long, can't get prot status\n"); - return 1; - } - } - - /* issue the Read Identifier Codes command */ - *addr = (FPW) INTEL_READID; - - /* wait at least 35ns (W12) before reading */ - udelay(1); - - /* Intel example code uses offset of 4 for 8-bit flash */ - lock_conf_addr = (FPWV *) info->start[sector] + 4; - ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0; - - /* put flash back in read mode */ - *addr = (FPW) INTEL_RESET; - - return ret; -} - - -/* - * Checks if "bank1" and "bank2" are on the same chip. Returns 1 if they - * are and 0 otherwise. - */ -static unsigned char same_chip_banks (int bank1, int bank2) -{ - unsigned char same_chip[CFG_MAX_FLASH_BANKS][CFG_MAX_FLASH_BANKS] = { - {1, 1, 0, 0}, - {1, 1, 0, 0}, - {0, 0, 1, 1}, - {0, 0, 1, 1} - }; - return same_chip[bank1][bank2]; -} - - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0, intel = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf ("- missing\n"); - else - printf ("- no sectors to erase\n"); - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_AMD)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - } - - if (type == FLASH_MAN_INTEL) - intel = 1; - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer (0); - - if (intel) { - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - } else { - FPWV *base; /* first address in bank */ - - base = (FPWV *) (CFG_AMD_BASE); - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ - *addr = (FPW) 0x00300030; /* erase sector */ - } - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - if (intel) { - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - } else - *addr = (FPW) 0x00F000F0; /* reset to read mode */ - - rcode = 1; - break; - } - } - - if (intel) { - *addr = (FPW) 0x00500050; /* clear status register cmd. */ - *addr = (FPW) 0x00FF00FF; /* resest to read mode */ - } else - *addr = (FPW) 0x00F000F0; /* reset to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - { - FPW data = 0; /* 16 or 32 bit word, matches flash bus width */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof (data), left -= - sizeof (data) - bytes) { - - bytes = addr & (sizeof (data) - 1); - addr &= ~(sizeof (data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof (data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } - - res = write_word_amd (info, (FPWV *) addr, - data); - } - return res; - } /* case FLASH_MAN_AMD */ - - case FLASH_MAN_INTEL: - { - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - /* get lower word aligned address */ - wp = addr; - port_width = 1; - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < port_width; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - if ((rc = - write_data (info, wp, SWAP (data))) != 0) - return (rc); - wp += port_width; - } - - if (cnt > WR_BLOCK) { - /* - * handle word aligned part - */ - count = 0; - while (cnt >= WR_BLOCK) { - - if ((rc = - write_data_block (info, - (ulong) src, - wp)) != 0) - return (rc); - - wp += WR_BLOCK; - src += WR_BLOCK; - cnt -= WR_BLOCK; - - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - } - - if (cnt < WR_BLOCK) { - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) - data = (data << 8) | *src++; - - if ((rc = - write_data (info, wp, - SWAP (data))) != 0) - return (rc); - - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - } - - if (cnt == 0) - return (0); - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; - ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - - for (; i < port_width; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - return (write_data (info, wp, SWAP (data))); - } /* case FLASH_MAN_INTEL */ - - } /* switch */ - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer (0); - - /* wait while polling the status register */ - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data_block (flash_info_t * info, ulong src, ulong dest) -{ - FPWV *srcaddr = (FPWV *) src; - FPWV *dstaddr = (FPWV *) dest; - ulong start; - int flag, i; - - /* Check if Flash is (sufficiently) erased */ - for (i = 0; i < WR_BLOCK; i++) - if ((*dstaddr++ & 0xff) != 0xff) { - printf ("not erased at %08lx (%lx)\n", - (ulong) dstaddr, *dstaddr); - return (2); - } - - dstaddr = (FPWV *) dest; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *dstaddr = (FPW) 0x00e800e8; /* write block setup */ - - /* arm simple, non interrupt dependent timer */ - start = get_timer (0); - - /* wait while polling the status register */ - while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *dstaddr = (FPW) 0x001f001f; /* write 32 to buffer */ - for (i = 0; i < WR_BLOCK; i++) - *dstaddr++ = *srcaddr++; - - dstaddr -= 1; - *dstaddr = (FPW) 0x00d000d0; /* write 32 to buffer */ - - /* arm simple, non interrupt dependent timer */ - start = get_timer (0); - - /* wait while polling the status register */ - while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *) (CFG_AMD_BASE); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - ulong start; - int i, j; - int curr_bank; - int bank; - int rc = 0; - FPWV *addr = (FPWV *) (info->start[sector]); - int flag = disable_interrupts (); - - /* - * 29F040B AMD flash does not support software protection/unprotection, - * the only way to protect the AMD flash is marked it as prot bit. - * This flash only support hardware protection, by supply or not supply - * 12vpp to the flash - */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) { - info->protect[sector] = prot; - - return 0; - } - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - start = get_timer (0); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) { - printf ("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf ("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint) addr, (uint) * addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - */ - if (!prot) { - /* - * re-locking must be done for all banks that belong on one - * FLASH chip, as all the sectors on the chip were unlocked - * by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope - * that banks never span chips, in particular chips which - * support h/w protection differently). - */ - - /* find the current bank number */ - curr_bank = CFG_MAX_FLASH_BANKS + 1; - for (j = 0; j < CFG_MAX_FLASH_BANKS; ++j) { - if (&flash_info[j] == info) { - curr_bank = j; - } - } - if (curr_bank == CFG_MAX_FLASH_BANKS + 1) { - printf("Error: can't determine bank number!\n"); - } - - for (bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank) { - if (!same_chip_banks(curr_bank, bank)) { - continue; - } - info = &flash_info[bank]; - for (i = 0; i < info->sector_count; i++) { - if (info->protect[i]) { - start = get_timer (0); - addr = (FPWV *) (info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - while ((*addr & INTEL_FINISHED) != - INTEL_FINISHED) { - if (get_timer (start) > - CFG_FLASH_UNLOCK_TOUT) { - printf ("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - } - } - } - - /* - * get the s/w sector protection status in sync with the h/w, - * in case something went wrong during the re-locking. - */ - flash_sync_real_protect(info); /* resets flash to read mode */ - } - - if (flag) - enable_interrupts (); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} diff --git a/board/alaska/u-boot.lds b/board/alaska/u-boot.lds deleted file mode 100644 index 889bc77..0000000 --- a/board/alaska/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8220/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/altera/common/flash.c b/board/altera/common/flash.c deleted file mode 100644 index 2638ea8..0000000 --- a/board/altera/common/flash.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/*--------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i, k; - unsigned long size; - int erased; - volatile unsigned char *flash; - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - - /* Check if whole sector is erased */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned char *) info->start[i]; - for (k = 0; k < size; k++) { - if (*flash++ != 0xff) { - erased = 0; - break; - } - } - - /* Print the info */ - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", info->start[i], erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*-------------------------------------------------------------------*/ - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; - int prot, sect; - unsigned oldpri; - ulong start; - - /* Some sanity checking */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - for (sect = s_first; sect <= s_last; sect++) { - printf("- Erase: Sect: %i @ 0x%08x\n", sect, info->start[sect]); - } -#endif - - /* NOTE: disabling interrupts on Nios can be very bad since it - * also disables the LO_LIMIT exception. It's better here to - * set the interrupt priority to 3 & restore it when we're done. - */ - oldpri = ipri (3); - - /* It's ok to erase multiple sectors provided we don't delay more - * than 50 usec between cmds ... at which point the erase time-out - * occurs. So don't go and put printf() calls in the loop ... it - * won't be very helpful ;-) - */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - *addr = 0xaa; - *addr = 0x55; - *addr = 0x80; - *addr = 0xaa; - *addr = 0x55; - *addr2 = 0x30; - /* Now just wait for 0xff & provide some user - * feedback while we wait. Here we have to grant - * timer interrupts. Otherwise get_timer() can't - * work right. */ - ipri(oldpri); - start = get_timer (0); - while (*addr2 != 0xff) { - udelay (1000 * 1000); - putc ('.'); - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { - printf ("timeout\n"); - return 1; - } - } - oldpri = ipri (3); /* disallow non important irqs again */ - } - } - - printf ("\n"); - - /* Restore interrupt priority */ - ipri (oldpri); - - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - - vu_char *cmd = (vu_char *) info->start[0]; - vu_char *dst = (vu_char *) addr; - unsigned char b; - unsigned oldpri; - ulong start; - - while (cnt) { - /* Check for sufficient erase */ - b = *src; - if ((*dst & b) != b) { - printf ("%02x : %02x\n", *dst, b); - return (2); - } - - /* Disable interrupts other than window underflow - * (interrupt priority 2) - */ - oldpri = ipri (3); - *cmd = 0xaa; - *cmd = 0x55; - *cmd = 0xa0; - *dst = b; - - /* Verify write */ - start = get_timer (0); - while (*dst != b) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - ipri (oldpri); - return 1; - } - } - dst++; - src++; - cnt--; - ipri (oldpri); - } - - return (0); -} diff --git a/board/altera/common/sevenseg.c b/board/altera/common/sevenseg.c deleted file mode 100644 index c53cec1..0000000 --- a/board/altera/common/sevenseg.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * common/sevenseg.c - * - * NIOS PIO based seven segment led support functions - */ - -#include -#include - -#ifdef CONFIG_SEVENSEG - -#define SEVENDEG_MASK_DP ((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP) - -#ifdef SEVENSEG_WRONLY /* emulate read access */ -#if (SEVENSEG_ACTIVE == 0) -static unsigned int sevenseg_portval = ~0; -#else -static unsigned int sevenseg_portval = 0; -#endif -#endif - -static int sevenseg_init_done = 0; - -static inline void __sevenseg_set_masked (unsigned int mask, int value) -{ - nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; - -#ifdef SEVENSEG_WRONLY /* emulate read access */ - -#if (SEVENSEG_ACTIVE == 0) - if (value) - sevenseg_portval &= ~mask; - else - sevenseg_portval |= mask; -#else - if (value) - sevenseg_portval |= mask; - else - sevenseg_portval &= ~mask; -#endif - - piop->data = sevenseg_portval; - -#else /* !SEVENSEG_WRONLY */ - -#if (SEVENSEG_ACTIVE == 0) - if (value) - piop->data &= ~mask; - else - piop->data |= mask; -#else - if (value) - piop->data |= mask; - else - piop->data &= ~mask; -#endif - -#endif /* SEVENSEG_WRONLY */ -} - -static inline void __sevenseg_toggle_masked (unsigned int mask) -{ - nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE; - -#ifdef SEVENSEG_WRONLY /* emulate read access */ - - sevenseg_portval ^= mask; - piop->data = sevenseg_portval; - -#else /* !SEVENSEG_WRONLY */ - - piop->data ^= mask; - -#endif /* SEVENSEG_WRONLY */ -} - -static inline void __sevenseg_set (unsigned int value) -{ - nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; - -#ifdef SEVENSEG_WRONLY /* emulate read access */ - -#if (SEVENSEG_ACTIVE == 0) - sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP) - | ((~value) & (~SEVENDEG_MASK_DP)); -#else - sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP) - | (value); -#endif - - piop->data = sevenseg_portval; - -#else /* !SEVENSEG_WRONLY */ - -#if (SEVENSEG_ACTIVE == 0) - piop->data = (piop->data & SEVENDEG_MASK_DP) - | ((~value) & (~SEVENDEG_MASK_DP)); -#else - piop->data = (piop->data & SEVENDEG_MASK_DP) - | (value); -#endif - -#endif /* SEVENSEG_WRONLY */ -} - -static inline void __sevenseg_init (void) -{ - nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE; - - __sevenseg_set(0); - -#ifndef SEVENSEG_WRONLY /* setup direction */ - - piop->direction |= mask; - -#endif /* SEVENSEG_WRONLY */ -} - - -void sevenseg_set(int value) -{ - unsigned char digits[] = { - SEVENSEG_DIGITS_0, - SEVENSEG_DIGITS_1, - SEVENSEG_DIGITS_2, - SEVENSEG_DIGITS_3, - SEVENSEG_DIGITS_4, - SEVENSEG_DIGITS_5, - SEVENSEG_DIGITS_6, - SEVENSEG_DIGITS_7, - SEVENSEG_DIGITS_8, - SEVENSEG_DIGITS_9, - SEVENSEG_DIGITS_A, - SEVENSEG_DIGITS_B, - SEVENSEG_DIGITS_C, - SEVENSEG_DIGITS_D, - SEVENSEG_DIGITS_E, - SEVENSEG_DIGITS_F - }; - - if (!sevenseg_init_done) { - __sevenseg_init(); - sevenseg_init_done++; - } - - switch (value & SEVENSEG_MASK_CTRL) { - - case SEVENSEG_RAW: - __sevenseg_set( ( - (digits[((value & SEVENSEG_MASK_VAL) >> 4)] << 8) | - digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) ); - return; - break; /* paranoia */ - - case SEVENSEG_OFF: - __sevenseg_set(0); - __sevenseg_set_masked(SEVENDEG_MASK_DP, 0); - return; - break; /* paranoia */ - - case SEVENSEG_SET_DPL: - __sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1); - return; - break; /* paranoia */ - - case SEVENSEG_SET_DPH: - __sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1); - return; - break; /* paranoia */ - - case SEVENSEG_RES_DPL: - __sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0); - return; - break; /* paranoia */ - - case SEVENSEG_RES_DPH: - __sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0); - return; - break; /* paranoia */ - - case SEVENSEG_TOG_DPL: - __sevenseg_toggle_masked(SEVENSEG_DIGIT_DP); - return; - break; /* paranoia */ - - case SEVENSEG_TOG_DPH: - __sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8)); - return; - break; /* paranoia */ - - case SEVENSEG_LO: - case SEVENSEG_HI: - case SEVENSEG_STR: - default: - break; - } -} - -#endif /* CONFIG_SEVENSEG */ diff --git a/board/altera/common/sevenseg.h b/board/altera/common/sevenseg.h deleted file mode 100644 index cbfd2e7..0000000 --- a/board/altera/common/sevenseg.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * common/sevenseg.h - * - * NIOS PIO based seven segment led support functions - */ - -#ifndef __DK1S10_SEVENSEG_H__ -#define __DK1S10_SEVENSEG_H__ - -#ifdef CONFIG_SEVENSEG - -/* - * 15 8 7 0 - * |-----------------------|--------| - * | controll value | value | - * ---------------------------------- - */ -#define SEVENSEG_RAW (int)(0) /* write out byte value (hex) */ -#define SEVENSEG_OFF (int)( 1 << 8) /* display switch off */ -#define SEVENSEG_SET_DPL (int)( 2 << 8) /* set dp low nibble */ -#define SEVENSEG_SET_DPH (int)( 3 << 8) /* set dp high nibble */ -#define SEVENSEG_RES_DPL (int)( 4 << 8) /* reset dp low nibble */ -#define SEVENSEG_RES_DPH (int)( 5 << 8) /* reset dp high nibble */ -#define SEVENSEG_TOG_DPL (int)( 6 << 8) /* toggle dp low nibble */ -#define SEVENSEG_TOG_DPH (int)( 7 << 8) /* toggle dp high nibble */ -#define SEVENSEG_LO (int)( 8 << 8) /* write out low nibble only */ -#define SEVENSEG_HI (int)( 9 << 8) /* write out high nibble only */ -#define SEVENSEG_STR (int)(10 << 8) /* write out a string */ - -#define SEVENSEG_MASK_VAL (0xff) /* only used by SEVENSEG_RAW */ -#define SEVENSEG_MASK_CTRL (~SEVENSEG_MASK_VAL) - -#ifdef SEVENSEG_DIGIT_HI_LO_EQUAL - -#define SEVENSEG_DIGITS_0 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F ) -#define SEVENSEG_DIGITS_1 ( SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C ) -#define SEVENSEG_DIGITS_2 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_3 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_4 ( SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_5 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_6 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_7 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C ) -#define SEVENSEG_DIGITS_8 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_9 ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_A ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_B ( SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_C ( SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_D ( SEVENSEG_DIGIT_B \ - | SEVENSEG_DIGIT_C \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_E ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_D \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) -#define SEVENSEG_DIGITS_F ( SEVENSEG_DIGIT_A \ - | SEVENSEG_DIGIT_E \ - | SEVENSEG_DIGIT_F \ - | SEVENSEG_DIGIT_G ) - -#else /* !SEVENSEG_DIGIT_HI_LO_EQUAL */ -#error SEVENSEG: different pin asssignments not supported -#endif - -void sevenseg_set(int value); - -#endif /* CONFIG_SEVENSEG */ - -#endif /* __DK1S10_SEVENSEG_H__ */ diff --git a/board/altera/dk1c20/Makefile b/board/altera/dk1c20/Makefile deleted file mode 100644 index 9182a4e..0000000 --- a/board/altera/dk1c20/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2001-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o misc.o - -SOBJS = vectors.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/altera/dk1c20/config.mk b/board/altera/dk1c20/config.mk deleted file mode 100644 index d200715..0000000 --- a/board/altera/dk1c20/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2003 -# Psyent Corporation -# Scott McNutt -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x018c0000 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/altera/dk1c20/dk1c20.c b/board/altera/dk1c20/dk1c20.c deleted file mode 100644 index 98ee7a7..0000000 --- a/board/altera/dk1c20/dk1c20.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * CompactFlash/IDE: - * (C) Copyright 2004, Shlomo Kut - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#if defined(CONFIG_SEVENSEG) -#include "../common/sevenseg.h" -#endif - -void _default_hdlr (void) -{ - printf ("default_hdlr\n"); -} - -int board_early_init_f (void) -{ -#if defined(CONFIG_SEVENSEG) - /* init seven segment led display and switch off */ - sevenseg_set(SEVENSEG_OFF); -#endif - return 0; -} - -int checkboard (void) -{ - puts ("Board: Altera Nios 1C20 Development Kit\n"); - return 0; -} - -long int initdram (int board_type) -{ - return (0); -} - -#if (CONFIG_COMMANDS & CFG_CMD_IDE) -int ide_preinit (void) -{ - nios_pio_t *present = (nios_pio_t *) CFG_CF_PRESENT; - nios_pio_t *power = (nios_pio_t *) CFG_CF_POWER; - nios_pio_t *atasel = (nios_pio_t *) CFG_CF_ATASEL; - - /* setup data direction registers */ - present->direction = NIOS_PIO_IN; - power->direction = NIOS_PIO_OUT; - atasel->direction = NIOS_PIO_OUT; - - /* Check for presence of card */ - if (present->data) - return 1; - printf ("Ok\n"); - - /* Finish setup */ - power->data = 1; /* Turn on power FET */ - atasel->data = 0; /* Put in ATA mode */ - - return 0; -} -#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ diff --git a/board/altera/dk1c20/flash.c b/board/altera/dk1c20/flash.c deleted file mode 100644 index 1f344dd..0000000 --- a/board/altera/dk1c20/flash.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -/* - * include common flash code (for altera boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------*/ -#define BANKSZ CFG_FLASH_SIZE -#define SECTSZ (64 * 1024) -#define USERFLASH (2 * 1024 * 1024) /* bottom 2 MB for user */ - -/*----------------------------------------------------------------------*/ -unsigned long flash_init (void) -{ - int i; - unsigned long addr; - flash_info_t *fli = &flash_info[0]; - - fli->size = BANKSZ; - fli->sector_count = CFG_MAX_FLASH_SECT; - fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; - - addr = CFG_FLASH_BASE; - for (i = 0; i < fli->sector_count; ++i) { - fli->start[i] = addr; - addr += SECTSZ; - - /* Protect all but 2 MByte user area */ - if (addr < (CFG_FLASH_BASE + USERFLASH)) - fli->protect[i] = 0; - else - fli->protect[i] = 1; - } - - return (BANKSZ); -} diff --git a/board/altera/dk1c20/misc.c b/board/altera/dk1c20/misc.c deleted file mode 100644 index f25cdeb..0000000 --- a/board/altera/dk1c20/misc.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * board/altera/dk1s10/misc.c - * - * miscellaneous board interfaces / drivers - */ - -#include - -#if defined(CONFIG_SEVENSEG) -#include "../common/sevenseg.h" -#include "../common/sevenseg.c" -#endif diff --git a/board/altera/dk1c20/u-boot.lds b/board/altera/dk1c20/u-boot.lds deleted file mode 100644 index 8b01f45..0000000 --- a/board/altera/dk1c20/u-boot.lds +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -OUTPUT_FORMAT("elf32-nios") -OUTPUT_ARCH(nios) -ENTRY(_start) - -SECTIONS -{ - .text : - { - cpu/nios/start.o (.text) - *(.text) - } - __text_end = .; - - . = ALIGN(4); - .rodata : - { - *(.rodata) - } - __rodata_end = .; - - . = ALIGN(4); - .data : - { - *(.data) - } - . = ALIGN(4); - __data_end = .; - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : - { - *(.u_boot_cmd) - } - . = ALIGN(4); - __u_boot_cmd_end = .; - - __bss_start = .; - . = ALIGN(4); - .bss : - { - *(.bss) - } - . = ALIGN(4); - __bss_end = .; -} diff --git a/board/altera/dk1c20/vectors.S b/board/altera/dk1c20/vectors.S deleted file mode 100644 index c83c0e7..0000000 --- a/board/altera/dk1c20/vectors.S +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -/************************************************************************* - * Exception Vector Table - * - * This could have gone in the cpu soure tree, but the whole point of - * Nios is customization -- and polluting the cpu source tree with - * board-specific ifdef's really defeats the purpose, no? With this in - * the board-specific tree, each board has the freedom to organize - * vectors/traps, etc anyway it wants. The init code copies this table - * to the proper location. - * - * Each board can do what it likes here. But there are four "standard" - * handlers availble: - * - * _cwp_lolimit -Handles register window underflows. - * _cwp_hilimit -Handles register window overflows. - * _timebase_int -Increments the timebase. - * _brkpt_hw_int -Hardware breakpoint handler. - * _brkpt_sw_int -Software breakpoint handler. - * _def_xhandler -Default exception handler. - * - * _timebase_int handles a Nios Timer interrupt and increments the - * timestamp used for the get_timer(), reset_timer(), etc. routines. It - * expects the timer to be configured like the standard-32 low priority - * timer. - * - * _def_xhandler dispatches exceptions/traps via the external_interrupt() - * routine. This lets you use the irq_install_handler() and handle your - * interrupts/traps with code written in C. - ************************************************************************/ - - .data - .global _vectors - .align 4 -_vectors: - - .long _def_xhandler@h /* Vector 0 - NMI */ - .long _cwp_lolimit@h /* Vector 1 - underflow */ - .long _cwp_hilimit@h /* Vector 2 - overflow */ - .long _brkpt_hw_int@h /* Vector 3 - Breakpoint */ - .long _brkpt_sw_int@h /* Vector 4 - Single step*/ - .long _def_xhandler@h /* Vector 5 - GNUPro debug */ - .long _def_xhandler@h /* Vector 6 - future reserved */ - .long _def_xhandler@h /* Vector 7 - future reserved */ - .long _def_xhandler@h /* Vector 8 - future reserved */ - .long _def_xhandler@h /* Vector 9 - future reserved */ - .long _def_xhandler@h /* Vector 10 - future reserved */ - .long _def_xhandler@h /* Vector 11 - future reserved */ - .long _def_xhandler@h /* Vector 12 - future reserved */ - .long _def_xhandler@h /* Vector 13 - future reserved */ - .long _def_xhandler@h /* Vector 14 - future reserved */ - .long _def_xhandler@h /* Vector 15 - future reserved */ - .long _def_xhandler@h /* Vector 16 */ - .long _def_xhandler@h /* Vector 17 */ - .long _def_xhandler@h /* Vector 18 */ - .long _def_xhandler@h /* Vector 19 */ - .long _def_xhandler@h /* Vector 20 */ - .long _def_xhandler@h /* Vector 21 */ - .long _def_xhandler@h /* Vector 22 */ - .long _def_xhandler@h /* Vector 23 */ - .long _def_xhandler@h /* Vector 24 */ - .long _def_xhandler@h /* Vector 25 */ - .long _def_xhandler@h /* Vector 26 */ - .long _def_xhandler@h /* Vector 27 */ - .long _def_xhandler@h /* Vector 28 */ - .long _def_xhandler@h /* Vector 29 */ - .long _def_xhandler@h /* Vector 30 */ - .long _def_xhandler@h /* Vector 31 */ - .long _def_xhandler@h /* Vector 32 */ - .long _def_xhandler@h /* Vector 33 */ - .long _def_xhandler@h /* Vector 34 */ - .long _def_xhandler@h /* Vector 35 */ - .long _def_xhandler@h /* Vector 36 */ - .long _def_xhandler@h /* Vector 37 */ - .long _def_xhandler@h /* Vector 38 */ - .long _def_xhandler@h /* Vector 39 */ - .long _def_xhandler@h /* Vector 40 */ - .long _def_xhandler@h /* Vector 41 */ - .long _def_xhandler@h /* Vector 42 */ - .long _def_xhandler@h /* Vector 43 */ - .long _def_xhandler@h /* Vector 44 */ - .long _def_xhandler@h /* Vector 45 */ - .long _def_xhandler@h /* Vector 46 */ - .long _def_xhandler@h /* Vector 47 */ - .long _def_xhandler@h /* Vector 48 */ - .long _def_xhandler@h /* Vector 49 */ - .long _timebase_int@h /* Vector 50 - lopri timer*/ - .long _def_xhandler@h /* Vector 51 */ - .long _def_xhandler@h /* Vector 52 */ - .long _def_xhandler@h /* Vector 53 */ - .long _def_xhandler@h /* Vector 54 */ - .long _def_xhandler@h /* Vector 55 */ - .long _def_xhandler@h /* Vector 56 */ - .long _def_xhandler@h /* Vector 57 */ - .long _def_xhandler@h /* Vector 58 */ - .long _def_xhandler@h /* Vector 59 */ - .long _def_xhandler@h /* Vector 60 */ - .long _def_xhandler@h /* Vector 61 */ - .long _def_xhandler@h /* Vector 62 */ - .long _def_xhandler@h /* Vector 63 */ diff --git a/board/altera/dk1s10/Makefile b/board/altera/dk1s10/Makefile deleted file mode 100644 index 9182a4e..0000000 --- a/board/altera/dk1s10/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2001-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o misc.o - -SOBJS = vectors.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/altera/dk1s10/config.mk b/board/altera/dk1s10/config.mk deleted file mode 100644 index d200715..0000000 --- a/board/altera/dk1s10/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2003 -# Psyent Corporation -# Scott McNutt -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x018c0000 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/altera/dk1s10/dk1s10.c b/board/altera/dk1s10/dk1s10.c deleted file mode 100644 index c45e7f1..0000000 --- a/board/altera/dk1s10/dk1s10.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined(CONFIG_SEVENSEG) -#include "../common/sevenseg.h" -#endif - -void _default_hdlr (void) -{ - printf ("default_hdlr\n"); -} - -int board_early_init_f (void) -{ -#if defined(CONFIG_SEVENSEG) - /* init seven segment led display and switch off */ - sevenseg_set(SEVENSEG_OFF); -#endif - return 0; -} - -int checkboard (void) -{ - puts ("Board: Altera Nios 1S10 Development Kit\n"); -#if defined(CONFIG_NIOS_SAFE_32) - puts ("Conf.: Altera Safe 32 (safe_32)\n"); -#elif defined(CONFIG_NIOS_STANDARD_32) - puts ("Conf.: Altera Standard 32 (standard_32)\n"); -#elif defined(CONFIG_NIOS_MTX_LDK_20) - puts ("Conf.: Microtronix LDK 2.0 (LDK2)\n"); -#endif - - return 0; -} - -long int initdram (int board_type) -{ - return (0); -} diff --git a/board/altera/dk1s10/flash.c b/board/altera/dk1s10/flash.c deleted file mode 100644 index 5c70933..0000000 --- a/board/altera/dk1s10/flash.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -/* - * include common flash code (for altera boards) - */ -#include "../common/flash.c" - -/*---------------------------------------------------------------------*/ -#define BANKSZ (8 * 1024 * 1024) -#define SECTSZ (64 * 1024) -#define USERFLASH (2 * 1024 * 1024) /* bottom 2 MB for user */ - -/*---------------------------------------------------------------------*/ -unsigned long flash_init (void) -{ - int i; - unsigned long addr; - flash_info_t *fli = &flash_info[0]; - - fli->size = BANKSZ; - fli->sector_count = CFG_MAX_FLASH_SECT; - fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; - - addr = CFG_FLASH_BASE; - for (i = 0; i < fli->sector_count; ++i) { - fli->start[i] = addr; - addr += SECTSZ; - - /* Protect all but 2 MByte user area */ - if (addr < (CFG_FLASH_BASE + USERFLASH)) - fli->protect[i] = 0; - else - fli->protect[i] = 1; - } - - return (BANKSZ); -} diff --git a/board/altera/dk1s10/misc.c b/board/altera/dk1s10/misc.c deleted file mode 100644 index f25cdeb..0000000 --- a/board/altera/dk1s10/misc.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * board/altera/dk1s10/misc.c - * - * miscellaneous board interfaces / drivers - */ - -#include - -#if defined(CONFIG_SEVENSEG) -#include "../common/sevenseg.h" -#include "../common/sevenseg.c" -#endif diff --git a/board/altera/dk1s10/u-boot.lds b/board/altera/dk1s10/u-boot.lds deleted file mode 100644 index 8b01f45..0000000 --- a/board/altera/dk1s10/u-boot.lds +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -OUTPUT_FORMAT("elf32-nios") -OUTPUT_ARCH(nios) -ENTRY(_start) - -SECTIONS -{ - .text : - { - cpu/nios/start.o (.text) - *(.text) - } - __text_end = .; - - . = ALIGN(4); - .rodata : - { - *(.rodata) - } - __rodata_end = .; - - . = ALIGN(4); - .data : - { - *(.data) - } - . = ALIGN(4); - __data_end = .; - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : - { - *(.u_boot_cmd) - } - . = ALIGN(4); - __u_boot_cmd_end = .; - - __bss_start = .; - . = ALIGN(4); - .bss : - { - *(.bss) - } - . = ALIGN(4); - __bss_end = .; -} diff --git a/board/altera/dk1s10/vectors.S b/board/altera/dk1s10/vectors.S deleted file mode 100644 index 2f44875..0000000 --- a/board/altera/dk1s10/vectors.S +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - - -/************************************************************************* - * Exception Vector Table - * - * This could have gone in the cpu soure tree, but the whole point of - * Nios is customization -- and polluting the cpu source tree with - * board-specific ifdef's really defeats the purpose, no? With this in - * the board-specific tree, each board has the freedom to organize - * vectors/traps, etc anyway it wants. The init code copies this table - * to the proper location. - * - * Each board can do what it likes here. But there are four "standard" - * handlers availble: - * - * _cwp_lolimit -Handles register window underflows. - * _cwp_hilimit -Handles register window overflows. - * _timebase_int -Increments the timebase. - * _def_xhandler -Default exception handler. - * - * _timebase_int handles a Nios Timer interrupt and increments the - * timestamp used for the get_timer(), reset_timer(), etc. routines. It - * expects the timer to be configured like the standard-32 low priority - * timer. - * - * _def_xhandler dispatches exceptions/traps via the external_interrupt() - * routine. This lets you use the irq_install_handler() and handle your - * interrupts/traps with code written in C. - ************************************************************************/ - - .data - .global _vectors - .align 4 -_vectors: - -#if defined(CFG_NIOS_CPU_OCI_BASE) - /* OCI does the reset job */ - .long _def_xhandler@h /* Vector 0 - NMI / Reset */ -#else - /* there is no OCI, so we have to do a direct reset jump here */ - .long CFG_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */ -#endif - .long _cwp_lolimit@h /* Vector 1 - underflow */ - .long _cwp_hilimit@h /* Vector 2 - overflow */ - - .long _def_xhandler@h /* Vector 3 - GNUPro debug */ - .long _def_xhandler@h /* Vector 4 - GNUPro debug */ - .long _def_xhandler@h /* Vector 5 - GNUPro debug */ - .long _def_xhandler@h /* Vector 6 - future reserved */ - .long _def_xhandler@h /* Vector 7 - future reserved */ - .long _def_xhandler@h /* Vector 8 - future reserved */ - .long _def_xhandler@h /* Vector 9 - future reserved */ - .long _def_xhandler@h /* Vector 10 - future reserved */ - .long _def_xhandler@h /* Vector 11 - future reserved */ - .long _def_xhandler@h /* Vector 12 - future reserved */ - .long _def_xhandler@h /* Vector 13 - future reserved */ - .long _def_xhandler@h /* Vector 14 - future reserved */ - .long _def_xhandler@h /* Vector 15 - future reserved */ -#if (CFG_NIOS_TMRIRQ == 16) - .long _timebase_int@h /* Vector 16 - lopri timer*/ -#else - .long _def_xhandler@h /* Vector 16 */ -#endif - .long _def_xhandler@h /* Vector 17 */ - .long _def_xhandler@h /* Vector 18 */ - .long _def_xhandler@h /* Vector 19 */ - .long _def_xhandler@h /* Vector 20 */ - .long _def_xhandler@h /* Vector 21 */ - .long _def_xhandler@h /* Vector 22 */ - .long _def_xhandler@h /* Vector 23 */ - .long _def_xhandler@h /* Vector 24 */ - .long _def_xhandler@h /* Vector 25 */ - .long _def_xhandler@h /* Vector 26 */ - .long _def_xhandler@h /* Vector 27 */ - .long _def_xhandler@h /* Vector 28 */ - .long _def_xhandler@h /* Vector 29 */ - .long _def_xhandler@h /* Vector 30 */ - .long _def_xhandler@h /* Vector 31 */ - .long _def_xhandler@h /* Vector 32 */ - .long _def_xhandler@h /* Vector 33 */ - .long _def_xhandler@h /* Vector 34 */ - .long _def_xhandler@h /* Vector 35 */ - .long _def_xhandler@h /* Vector 36 */ - .long _def_xhandler@h /* Vector 37 */ - .long _def_xhandler@h /* Vector 38 */ - .long _def_xhandler@h /* Vector 39 */ - .long _def_xhandler@h /* Vector 40 */ - .long _def_xhandler@h /* Vector 41 */ - .long _def_xhandler@h /* Vector 42 */ - .long _def_xhandler@h /* Vector 43 */ - .long _def_xhandler@h /* Vector 44 */ - .long _def_xhandler@h /* Vector 45 */ - .long _def_xhandler@h /* Vector 46 */ - .long _def_xhandler@h /* Vector 47 */ - .long _def_xhandler@h /* Vector 48 */ - .long _def_xhandler@h /* Vector 49 */ -#if (CFG_NIOS_TMRIRQ == 50) - .long _timebase_int@h /* Vector 50 - lopri timer*/ -#else - .long _def_xhandler@h /* Vector 50 */ -#endif - .long _def_xhandler@h /* Vector 51 */ - .long _def_xhandler@h /* Vector 52 */ - .long _def_xhandler@h /* Vector 53 */ - .long _def_xhandler@h /* Vector 54 */ - .long _def_xhandler@h /* Vector 55 */ - .long _def_xhandler@h /* Vector 56 */ - .long _def_xhandler@h /* Vector 57 */ - .long _def_xhandler@h /* Vector 58 */ - .long _def_xhandler@h /* Vector 59 */ - .long _def_xhandler@h /* Vector 60 */ - .long _def_xhandler@h /* Vector 61 */ - .long _def_xhandler@h /* Vector 62 */ - .long _def_xhandler@h /* Vector 63 */ diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile deleted file mode 100644 index 5654f91..0000000 --- a/board/amcc/bamboo/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o -OBJS += flash.o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c deleted file mode 100644 index 803995a..0000000 --- a/board/amcc/bamboo/bamboo.c +++ /dev/null @@ -1,2089 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include "bamboo.h" - -void ext_bus_cntlr_init(void); -void configure_ppc440ep_pins(void); -int is_nand_selected(void); - -unsigned char cfg_simulate_spd_eeprom[128]; - -gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; -#if 0 -{ /* GPIO Alternate1 Alternate2 Alternate3 */ - { - /* GPIO Core 0 */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */ - { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */ - }, - { - /* GPIO Core 1 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */ - } -}; -#endif - -/*----------------------------------------------------------------------------+ - | EBC Devices Characteristics - | Peripheral Bank Access Parameters - EBC0_BnAP - | Peripheral Bank Configuration Register - EBC0_BnCR - +----------------------------------------------------------------------------*/ -/* Small Flash */ -#define EBC0_BNAP_SMALL_FLASH \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(6) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(3) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ - EBC0_BNAP_PEN_DISABLED - -#define EBC0_BNCR_SMALL_FLASH_CS0 \ - EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_8BIT - -#define EBC0_BNCR_SMALL_FLASH_CS4 \ - EBC0_BNCR_BAS_ENCODE(0x87F00000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_8BIT - -/* Large Flash or SRAM */ -#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(8) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(1) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_RW | \ - EBC0_BNAP_PEN_DISABLED - -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \ - EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_16BIT - - -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \ - EBC0_BNCR_BAS_ENCODE(0x87800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_16BIT - -/* NVRAM - FPGA */ -#define EBC0_BNAP_NVRAM_FPGA \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(9) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ - EBC0_BNAP_PEN_DISABLED - -#define EBC0_BNCR_NVRAM_FPGA_CS5 \ - EBC0_BNCR_BAS_ENCODE(0x80000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_8BIT - -/* Nand Flash */ -#define EBC0_BNAP_NAND_FLASH \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(3) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(0) | \ - EBC0_BNAP_WBN_ENCODE(0) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_NOT_DELAYED | \ - EBC0_BNAP_BEM_RW | \ - EBC0_BNAP_PEN_DISABLED - - -#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000 - -/* NAND0 */ -#define EBC0_BNCR_NAND_FLASH_CS1 \ - EBC0_BNCR_BAS_ENCODE(0x90000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_32BIT -/* NAND1 - Bank2 */ -#define EBC0_BNCR_NAND_FLASH_CS2 \ - EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_32BIT - -/* NAND1 - Bank3 */ -#define EBC0_BNCR_NAND_FLASH_CS3 \ - EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_32BIT - -int board_early_init_f(void) -{ - ext_bus_cntlr_init(); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - /*-------------------------------------------------------------------- - * Setup the GPIO pins - *-------------------------------------------------------------------*/ - out32(GPIO0_OSRL, 0x00000400); - out32(GPIO0_OSRH, 0x00000000); - out32(GPIO0_TSRL, 0x00000400); - out32(GPIO0_TSRH, 0x00000000); - out32(GPIO0_ISR1L, 0x00000000); - out32(GPIO0_ISR1H, 0x00000000); - out32(GPIO0_ISR2L, 0x00000000); - out32(GPIO0_ISR2H, 0x00000000); - out32(GPIO0_ISR3L, 0x00000000); - out32(GPIO0_ISR3H, 0x00000000); - - out32(GPIO1_OSRL, 0x0C380000); - out32(GPIO1_OSRH, 0x00000000); - out32(GPIO1_TSRL, 0x0C380000); - out32(GPIO1_TSRH, 0x00000000); - out32(GPIO1_ISR1L, 0x0FC30000); - out32(GPIO1_ISR1H, 0x00000000); - out32(GPIO1_ISR2L, 0x0C010000); - out32(GPIO1_ISR2H, 0x00000000); - out32(GPIO1_ISR3L, 0x01400000); - out32(GPIO1_ISR3H, 0x00000000); - - configure_ppc440ep_pins(); - - return 0; -} - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -/*----------------------------------------------------------------------------+ - | nand_reset. - | Reset Nand flash - | This routine will abort previous cmd - +----------------------------------------------------------------------------*/ -int nand_reset(ulong addr) -{ - int wait=0, stat=0; - - out8(addr + NAND_CMD_REG, NAND0_CMD_RESET); - out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS); - - while ((stat != 0xc0) && (wait != 0xffff)) { - stat = in8(addr + NAND_DATA_REG); - wait++; - } - - if (stat == 0xc0) { - return 0; - } else { - printf("NAND Reset timeout.\n"); - return -1; - } -} - -void board_nand_set_device(int cs, ulong addr) -{ - /* Set NandFlash Core Configuration Register */ - out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24)); - - switch (cs) { - case 1: - /* ------- - * NAND0 - * ------- - * K9F1208U0A : 4 addr cyc, 1 col + 3 Row - * Set NDF1CR - Enable External CS1 in NAND FLASH controller - */ - out32(addr + NAND_CR1_REG, 0x80002222); - break; - - case 2: - /* ------- - * NAND1 - * ------- - * K9K2G0B : 5 addr cyc, 2 col + 3 Row - * Set NDF2CR : Enable External CS2 in NAND FLASH controller - */ - out32(addr + NAND_CR2_REG, 0xC0007777); - break; - } - - /* Perform Reset Command */ - if (nand_reset(addr) != 0) - return; -} - -void nand_init(void) -{ - board_nand_set_device(1, CFG_NAND_ADDR); - - nand_probe(CFG_NAND_ADDR); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } - -#if 0 /* NAND1 not supported yet */ - board_nand_set_device(2, CFG_NAND2_ADDR); - - nand_probe(CFG_NAND2_ADDR); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -#endif -} -#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ - -int checkboard(void) -{ - char *s = getenv("serial#"); - - printf("Board: Bamboo - AMCC PPC440EP Evaluation Board"); - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - - return (0); -} - -/************************************************************************* - * - * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM) - * - * Fixed memory is composed of : - * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, - * 13 row add bits, 10 column add bits (but 12 row used only). - * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, - * 12 row add bits, 10 column add bits. - * Prepare a subset (only the used ones) of SPD data - * - * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of - * the corresponding bank is divided by 2 due to number of Row addresses - * 12 in the ECC module - * - * Assumes: 64 MB, ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -static void init_spd_array(void) -{ - cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */ - cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */ - -#ifdef CONFIG_DDR_ECC - cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */ - cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */ - cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */ -#else - cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */ - cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */ - cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */ -#endif - - cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */ - cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */ - cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */ - cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */ - cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/ - cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */ - cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */ - cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */ - cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */ - cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */ - - cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */ - - cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */ - - cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ - cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */ - cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */ - cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */ -} - -long int initdram (int board_type) -{ - long dram_size = 0; - - /* - * First write simulated values in eeprom array for onboard bank 0 - */ - init_spd_array(); - - dram_size = spd_sdram (0); - - return dram_size; -} - -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *)0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - return 0; -} -#endif - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - /*-------------------------------------------------------------------------+ - | Set priority for all PLB3 devices to 0. - | Set PLB3 arbiter to fair mode. - +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); - - /*-------------------------------------------------------------------------+ - | Set priority for all PLB4 devices to 0. - +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); - - /*-------------------------------------------------------------------------+ - | Set Nebula PLB4 arbiter to fair mode. - +-------------------------------------------------------------------------*/ - /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); - - /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); - - return 1; -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Set up Direct MMIO registers - *--------------------------------------------------------------------------*/ - /*--------------------------------------------------------------------------+ - | PowerPC440 EP PCI Master configuration. - | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - -/************************************************************************* - * pci_master_init - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /*--------------------------------------------------------------------------+ - | Write the PowerPC440 EP PCI Configuration regs. - | Enable PowerPC440 EP to be a master on the PCI bus (PMM). - | Enable PowerPC440 EP to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - /* Bamboo is always configured as host. */ - return (1); -} -#endif /* defined(CONFIG_PCI) */ - -/*----------------------------------------------------------------------------+ - | is_powerpc440ep_pass1. - +----------------------------------------------------------------------------*/ -int is_powerpc440ep_pass1(void) -{ - unsigned long pvr; - - pvr = get_pvr(); - - if (pvr == PVR_POWERPC_440EP_PASS1) - return TRUE; - else if (pvr == PVR_POWERPC_440EP_PASS2) - return FALSE; - else { - printf("brdutil error 3\n"); - for (;;) - ; - } - - return(FALSE); -} - -/*----------------------------------------------------------------------------+ - | is_nand_selected. - +----------------------------------------------------------------------------*/ -int is_nand_selected(void) -{ -#ifdef CONFIG_BAMBOO_NAND - return TRUE; -#else - return FALSE; -#endif -} - -/*----------------------------------------------------------------------------+ - | config_on_ebc_cs4_is_small_flash => from EPLD - +----------------------------------------------------------------------------*/ -unsigned char config_on_ebc_cs4_is_small_flash(void) -{ - /* Not implemented yet => returns constant value */ - return TRUE; -} - -/*----------------------------------------------------------------------------+ - | Ext_bus_cntlr_init. - | Initialize the external bus controller - +----------------------------------------------------------------------------*/ -void ext_bus_cntlr_init(void) -{ - unsigned long sdr0_pstrp0, sdr0_sdstp1; - unsigned long bootstrap_settings, boot_selection, ebc_boot_size; - int computed_boot_device = BOOT_DEVICE_UNKNOWN; - unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0; - unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0; - unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0; - unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0; - unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0; - - - /*-------------------------------------------------------------------------+ - | - | PART 1 : Initialize EBC Bank 5 - | ============================== - | Bank5 is always associated to the NVRAM/EPLD. - | It has to be initialized prior to other banks settings computation since - | some board registers values may be needed - | - +-------------------------------------------------------------------------*/ - /* NVRAM - FPGA */ - mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA); - mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5); - - /*-------------------------------------------------------------------------+ - | - | PART 2 : Determine which boot device was selected - | ========================================= - | - | Read Pin Strap Register in PPC440EP - | In case of boot from IIC, read Serial Device Strap Register1 - | - | Result can either be : - | - Boot from EBC 8bits => SMALL FLASH - | - Boot from EBC 16bits => Large Flash or SRAM - | - Boot from NAND Flash - | - Boot from PCI - | - +-------------------------------------------------------------------------*/ - /* Read Pin Strap Register in PPC440EP */ - mfsdr(sdr_pstrp0, sdr0_pstrp0); - bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK; - - /*-------------------------------------------------------------------------+ - | PPC440EP Pass1 - +-------------------------------------------------------------------------*/ - if (is_powerpc440ep_pass1() == TRUE) { - switch(bootstrap_settings) { - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: - /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ - /* Boot from Small Flash */ - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: - /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */ - /* Boot from PCI */ - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: - /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */ - /* Boot from Nand Flash */ - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: - /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */ - /* Boot from Small Flash */ - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - - case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: - case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: - /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ - /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(sdr_sdstp1, sdr0_sdstp1); - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; - - switch(boot_selection) { - case SDR0_SDSTP1_BOOT_SEL_EBC: - switch(ebc_boot_size) { - case SDR0_SDSTP1_EBC_ROM_BS_16BIT: - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - case SDR0_SDSTP1_EBC_ROM_BS_8BIT: - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - } - break; - - case SDR0_SDSTP1_BOOT_SEL_PCI: - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_SDSTP1_BOOT_SEL_NDFC: - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - } - break; - } - } - - /*-------------------------------------------------------------------------+ - | PPC440EP Pass2 - +-------------------------------------------------------------------------*/ - else { - switch(bootstrap_settings) { - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: - /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ - /* Boot from Small Flash */ - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: - /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */ - /* Boot from PCI */ - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: - /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */ - /* Boot from Nand Flash */ - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: - /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */ - /* Boot from Large Flash or SRAM */ - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4: - /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */ - /* Boot from Large Flash or SRAM */ - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6: - /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */ - /* Boot from PCI */ - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: - case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: - /* Default Strap Settings 5-7 */ - /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ - /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(sdr_sdstp1, sdr0_sdstp1); - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; - - switch(boot_selection) { - case SDR0_SDSTP1_BOOT_SEL_EBC: - switch(ebc_boot_size) { - case SDR0_SDSTP1_EBC_ROM_BS_16BIT: - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - case SDR0_SDSTP1_EBC_ROM_BS_8BIT: - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - } - break; - - case SDR0_SDSTP1_BOOT_SEL_PCI: - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_SDSTP1_BOOT_SEL_NDFC: - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - } - break; - } - } - - /*-------------------------------------------------------------------------+ - | - | PART 3 : Compute EBC settings depending on selected boot device - | ====== ====================================================== - | - | Resulting EBC init will be among following configurations : - | - | - Boot from EBC 8bits => boot from SMALL FLASH selected - | EBC-CS0 = Small Flash - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Soft Config - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS5 = NVRAM / EPLD - | - | - Boot from EBC 16bits => boot from Large Flash or SRAM selected - | EBC-CS0 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Software Configuration - | EBC-CS4 = Small Flash - | EBC-CS5 = NVRAM / EPLD - | - | - Boot from NAND Flash - | EBC-CS0 = NAND Flash0 - | EBC-CS1,2,3 = NAND Flash1 - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS5 = NVRAM / EPLD - | - | - Boot from PCI - | EBC-CS0 = ... - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Software Configuration - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM or - | Small Flash depending on jumpers - | EBC-CS5 = NVRAM / EPLD - | - +-------------------------------------------------------------------------*/ - - switch(computed_boot_device) { - /*------------------------------------------------------------------------- */ - case BOOT_FROM_SMALL_FLASH: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH; - ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0; - if ((is_nand_selected()) == TRUE) { - /* NAND Flash */ - ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } else { - /* Expansion Slot */ - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } - ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_FROM_LARGE_FLASH_OR_SRAM: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0; - if ((is_nand_selected()) == TRUE) { - /* NAND Flash */ - ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } else { - /* Expansion Slot */ - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } - ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; - ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_FROM_NAND_FLASH0: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = 0; - ebc0_cs0_bncr_value = 0; - - ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - - /* Large Flash or SRAM */ - ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_FROM_PCI: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = 0; - ebc0_cs0_bncr_value = 0; - - if ((is_nand_selected()) == TRUE) { - /* NAND Flash */ - ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } else { - /* Expansion Slot */ - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } - - if ((config_on_ebc_cs4_is_small_flash()) == TRUE) { - /* Small Flash */ - ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; - ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; - } else { - /* Large Flash or SRAM */ - ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; - } - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_DEVICE_UNKNOWN: - /*------------------------------------------------------------------------- */ - /* Error */ - break; - - } - - - /*-------------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN | - EBC0_CFG_PTD_ENABLED | - EBC0_CFG_RTC_2048PERCLK | - EBC0_CFG_EMPL_LOW | - EBC0_CFG_EMPH_LOW | - EBC0_CFG_CSTC_DRIVEN | - EBC0_CFG_BPF_ONEDW | - EBC0_CFG_EMS_8BIT | - EBC0_CFG_PME_DISABLED | - EBC0_CFG_PMT_ENCODE(0) ); - - /*-------------------------------------------------------------------------+ - | Initialize EBC Bank 0-4 - +-------------------------------------------------------------------------*/ - /* EBC Bank0 */ - mtebc(pb0ap, ebc0_cs0_bnap_value); - mtebc(pb0cr, ebc0_cs0_bncr_value); - /* EBC Bank1 */ - mtebc(pb1ap, ebc0_cs1_bnap_value); - mtebc(pb1cr, ebc0_cs1_bncr_value); - /* EBC Bank2 */ - mtebc(pb2ap, ebc0_cs2_bnap_value); - mtebc(pb2cr, ebc0_cs2_bncr_value); - /* EBC Bank3 */ - mtebc(pb3ap, ebc0_cs3_bnap_value); - mtebc(pb3cr, ebc0_cs3_bncr_value); - /* EBC Bank4 */ - mtebc(pb4ap, ebc0_cs4_bnap_value); - mtebc(pb4cr, ebc0_cs4_bncr_value); - - return; -} - - -/*----------------------------------------------------------------------------+ - | get_uart_configuration. - +----------------------------------------------------------------------------*/ -uart_config_nb_t get_uart_configuration(void) -{ - return (L4); -} - -/*----------------------------------------------------------------------------+ - | set_phy_configuration_through_fpga => to EPLD - +----------------------------------------------------------------------------*/ -void set_phy_configuration_through_fpga(zmii_config_t config) -{ - - unsigned long fpga_selection_reg; - - fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK; - - switch(config) - { - case ZMII_CONFIGURATION_IS_MII: - fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII; - break; - case ZMII_CONFIGURATION_IS_RMII: - fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII; - break; - case ZMII_CONFIGURATION_IS_SMII: - fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII; - break; - case ZMII_CONFIGURATION_UNKNOWN: - default: - break; - } - out8(FPGA_SELECTION_1_REG,fpga_selection_reg); - -} - -/*----------------------------------------------------------------------------+ - | scp_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void scp_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; - fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | iic1_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void iic1_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; - fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_a_b_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_a_b_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_a_b_unselect_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_a_b_unselect_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_c_d_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_c_d_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_c_d_unselect_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_c_d_unselect_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | usb2_device_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void usb2_device_selection_in_fpga(void) -{ - unsigned long fpga_selection_1_reg; - - fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL; - out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); -} - -/*----------------------------------------------------------------------------+ - | usb2_device_reset_through_fpga. - +----------------------------------------------------------------------------*/ -void usb2_device_reset_through_fpga(void) -{ - /* Perform soft Reset pulse */ - unsigned long fpga_reset_reg; - int i; - - fpga_reset_reg = in8(FPGA_RESET_REG); - out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV); - for (i=0; i<500; i++) - udelay(1000); - out8(FPGA_RESET_REG,fpga_reset_reg); -} - -/*----------------------------------------------------------------------------+ - | usb2_host_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void usb2_host_selection_in_fpga(void) -{ - unsigned long fpga_selection_1_reg; - - fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL; - out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); -} - -/*----------------------------------------------------------------------------+ - | ndfc_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void ndfc_selection_in_fpga(void) -{ - unsigned long fpga_selection_1_reg; - - fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK; - fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1; - fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; - out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); -} - -/*----------------------------------------------------------------------------+ - | uart_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void uart_selection_in_fpga(uart_config_nb_t uart_config) -{ - /* FPGA register */ - unsigned char fpga_selection_3_reg; - - /* Read FPGA Reagister */ - fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG); - - switch (uart_config) - { - case L1: - /* ----------------------------------------------------------------------- */ - /* L1 configuration: UART0 = 8 pins */ - /* ----------------------------------------------------------------------- */ - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - - break; - - case L2: - /* ----------------------------------------------------------------------- */ - /* L2 configuration: UART0 = 4 pins */ - /* UART1 = 4 pins */ - /* ----------------------------------------------------------------------- */ - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - - break; - - case L3: - /* ----------------------------------------------------------------------- */ - /* L3 configuration: UART0 = 4 pins */ - /* UART1 = 2 pins */ - /* UART2 = 2 pins */ - /* ----------------------------------------------------------------------- */ - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - break; - - case L4: - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - - break; - - default: - /* Unsupported UART configuration number */ - for (;;) - ; - break; - - } -} - - -/*----------------------------------------------------------------------------+ - | init_default_gpio - +----------------------------------------------------------------------------*/ -void init_default_gpio(void) -{ - int i; - - /* Init GPIO0 */ - for(i=0; i> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT2: - gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT3: - gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg); - break; - } - } - if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) || - (gpio_tab[gpio_core][i].in_out == GPIO_BI )) - { - - switch (gpio_tab[gpio_core][i].alt_nb) - { - case GPIO_SEL: - break; - case GPIO_ALT1: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - case GPIO_ALT2: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - case GPIO_ALT3: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - } - } - } -} - -/*----------------------------------------------------------------------------+ - | force_bup_core_selection. - +----------------------------------------------------------------------------*/ -void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P) -{ - /* Pointer invalid */ - if (core_select_P == NULL) - { - printf("Configuration invalid pointer 1\n"); - for (;;) - ; - } - - /* L4 Selection */ - *(core_select_P+UART_CORE0) = CORE_SELECTED; - *(core_select_P+UART_CORE1) = CORE_SELECTED; - *(core_select_P+UART_CORE2) = CORE_SELECTED; - *(core_select_P+UART_CORE3) = CORE_SELECTED; - - /* RMII Selection */ - *(core_select_P+RMII_SEL) = CORE_SELECTED; - - /* External Interrupt 0-9 selection */ - *(core_select_P+UIC_0_3) = CORE_SELECTED; - *(core_select_P+UIC_4_9) = CORE_SELECTED; - - *(core_select_P+SCP_CORE) = CORE_SELECTED; - *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED; - *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED; - *(core_select_P+USB1_DEVICE) = CORE_SELECTED; - - if (is_nand_selected()) { - *(core_select_P+NAND_FLASH) = CORE_SELECTED; - } - - *config_val_P = CONFIG_IS_VALID; - -} - -/*----------------------------------------------------------------------------+ - | configure_ppc440ep_pins. - +----------------------------------------------------------------------------*/ -void configure_ppc440ep_pins(void) -{ - uart_config_nb_t uart_configuration; - config_validity_t config_val = CONFIG_IS_INVALID; - - /* Create Core Selection Table */ - core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] = - { - CORE_NOT_SELECTED, /* IIC_CORE, */ - CORE_NOT_SELECTED, /* SPC_CORE, */ - CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */ - CORE_NOT_SELECTED, /* UIC_4_9, */ - CORE_NOT_SELECTED, /* USB2_HOST, */ - CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */ - CORE_NOT_SELECTED, /* USB2_DEVICE, */ - CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */ - CORE_NOT_SELECTED, /* USB1_DEVICE, */ - CORE_NOT_SELECTED, /* EBC_MASTER, */ - CORE_NOT_SELECTED, /* NAND_FLASH, */ - CORE_NOT_SELECTED, /* UART_CORE0, */ - CORE_NOT_SELECTED, /* UART_CORE1, */ - CORE_NOT_SELECTED, /* UART_CORE2, */ - CORE_NOT_SELECTED, /* UART_CORE3, */ - CORE_NOT_SELECTED, /* MII_SEL, */ - CORE_NOT_SELECTED, /* RMII_SEL, */ - CORE_NOT_SELECTED, /* SMII_SEL, */ - CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */ - CORE_NOT_SELECTED, /* UIC_0_3 */ - CORE_NOT_SELECTED, /* USB1_HOST */ - CORE_NOT_SELECTED /* PCI_PATCH */ - }; - - - /* Table Default Initialisation + FPGA Access */ - init_default_gpio(); - set_chip_gpio_configuration(GPIO0); - set_chip_gpio_configuration(GPIO1); - - /* Update Table */ - force_bup_core_selection(ppc440ep_core_selection, &config_val); -#if 0 /* test-only */ - /* If we are running PIBS 1, force known configuration */ - update_core_selection_table(ppc440ep_core_selection, &config_val); -#endif - - /*----------------------------------------------------------------------------+ - | SDR + ios table update + fpga initialization - +----------------------------------------------------------------------------*/ - unsigned long sdr0_pfc1 = 0; - unsigned long sdr0_usb0 = 0; - unsigned long sdr0_mfr = 0; - - /* PCI Always selected */ - - /* I2C Selection */ - if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; - iic1_selection_in_fpga(); - } - - /* SCP Selection */ - if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; - scp_selection_in_fpga(); - } - - /* UIC 0:3 Selection */ - if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED) - { - update_uic_0_3_irq_ios(); - dma_a_b_unselect_in_fpga(); - } - - /* UIC 4:9 Selection */ - if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL; - update_uic_4_9_irq_ios(); - } - - /* DMA AB Selection */ - if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL; - update_dma_a_b_ios(); - dma_a_b_selection_in_fpga(); - } - - /* DMA CD Selection */ - if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED) - { - update_dma_c_d_ios(); - dma_c_d_selection_in_fpga(); - } - - /* EBC Master Selection */ - if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_ebc_master_ios(); - } - - /* PCI Patch Enable */ - if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_pci_patch_ios(); - } - - /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */ - if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED) - { - /* Not Implemented in PowerPC 440EP Pass1-Pass2 */ - printf("Invalid configuration => USB2 Host selected\n"); - for (;;) - ; - /*usb2_host_selection_in_fpga(); */ - } - - /* USB2.0 Device Selection */ - if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) - { - update_usb2_device_ios(); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; - - mfsdr(sdr_usb0, sdr0_usb0); - sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; - sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL; - mtsdr(sdr_usb0, sdr0_usb0); - - usb2_device_selection_in_fpga(); - } - - /* USB1.1 Device Selection */ - if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED) - { - mfsdr(sdr_usb0, sdr0_usb0); - sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; - sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL; - mtsdr(sdr_usb0, sdr0_usb0); - } - - /* USB1.1 Host Selection */ - if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED) - { - mfsdr(sdr_usb0, sdr0_usb0); - sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK; - sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE; - mtsdr(sdr_usb0, sdr0_usb0); - } - - /* NAND Flash Selection */ - if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) - { - update_ndfc_ios(); - - mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - SDR0_CUST0_CHIPSELGAT_EN1 | - SDR0_CUST0_CHIPSELGAT_EN2); - - ndfc_selection_in_fpga(); - } - else - { - /* Set Mux on EMAC */ - mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL); - } - - /* MII Selection */ - if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) - { - update_zii_ios(); - mfsdr(sdr_mfr, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; - mtsdr(sdr_mfr, sdr0_mfr); - - set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII); - } - - /* RMII Selection */ - if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) - { - update_zii_ios(); - mfsdr(sdr_mfr, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; - mtsdr(sdr_mfr, sdr0_mfr); - - set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII); - } - - /* SMII Selection */ - if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) - { - update_zii_ios(); - mfsdr(sdr_mfr, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; - mtsdr(sdr_mfr, sdr0_mfr); - - set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII); - } - - /* UART Selection */ - uart_configuration = get_uart_configuration(); - switch (uart_configuration) - { - case L1: /* L1 Selection */ - /* UART0 8 pins Only */ - /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS; - break; - case L2: /* L2 Selection */ - /* UART0 and UART1 4 pins */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - break; - case L3: /* L3 Selection */ - /* UART0 4 pins, UART1 and UART2 2 pins */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - break; - case L4: /* L4 Selection */ - /* UART0, UART1, UART2 and UART3 2 pins */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - break; - } - update_uart_ios(uart_configuration); - - /* UART Selection in all cases */ - uart_selection_in_fpga(uart_configuration); - - /* Packet Reject Function Available */ - if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED) - { - /* Set UPR Bit in SDR0_PFC1 Register */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE; - } - - /* Packet Reject Function Enable */ - if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED) - { - mfsdr(sdr_mfr, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;; - mtsdr(sdr_mfr, sdr0_mfr); - } - - /* Perform effective access to hardware */ - mtsdr(sdr_pfc1, sdr0_pfc1); - set_chip_gpio_configuration(GPIO0); - set_chip_gpio_configuration(GPIO1); - - /* USB2.0 Device Reset must be done after GPIO setting */ - if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) - usb2_device_reset_through_fpga(); - -} diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h deleted file mode 100644 index 5f5fcde..0000000 --- a/board/amcc/bamboo/bamboo.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*----------------------------------------------------------------------------+ - | FPGA registers and bit definitions - +----------------------------------------------------------------------------*/ -/* - * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0. - * TLB initialization makes it correspond to logical address 0x80001FF0. - * => Done init_chip.s in bootlib - */ -#define FPGA_BASE_ADDR 0x80002000 - -/*----------------------------------------------------------------------------+ - | Board Jumpers Setting Register - | Board Settings provided by jumpers - +----------------------------------------------------------------------------*/ -#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3) -/* Boot from small flash */ -#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80 -/* Operational Flash versus SRAM position in Memory Map */ -#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40 -#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40 -#define FPGA_SET_REG_SRAM_ABOVE 0x00 -/* Boot From NAND Flash */ -#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40 -#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00 -/* On Board PCI Arbiter Select */ -#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10 -#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00 - -/*----------------------------------------------------------------------------+ - | Functions Selection Register 1 - +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4) -#define FPGA_SEL_1_REG_PHY_MASK 0xE0 -#define FPGA_SEL_1_REG_MII 0x80 -#define FPGA_SEL_1_REG_RMII 0x40 -#define FPGA_SEL_1_REG_SMII 0x20 -#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */ -#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */ -#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */ -#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */ -#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */ -#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */ - -/*----------------------------------------------------------------------------+ - | Functions Selection Register 2 - +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5) -#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */ -#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */ -#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */ -#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */ -#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */ -#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */ -#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */ - /* 1 = TC - output from 440EP */ -#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */ - /* 1 = TC (output from 440EP) */ -#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */ -#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */ -#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */ - -/*----------------------------------------------------------------------------+ - | Functions Selection Register 3 - +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6) -#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70 -#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */ -#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */ -#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */ - -/*----------------------------------------------------------------------------+ - | Soft Reset Register - +----------------------------------------------------------------------------*/ -#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7) -#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */ -#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */ -#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */ - - -/*----------------------------------------------------------------------------+ -| SDR Configuration registers -+----------------------------------------------------------------------------*/ -/* Serial Device Strap Reg 0 */ -#define SDR0_SDSTP0 0x0020 -/* Serial Device Strap Reg 1 */ -#define SDR0_SDSTP1 0x0021 -/* Serial Device Strap Reg 2 */ -#define SDR0_SDSTP2 SDR0_STRP2 -/* Serial Device Strap Reg 3 */ -#define SDR0_SDSTP3 SDR0_STRP3 - -#define sdr_pstrp0 0x0040 - -#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */ -#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */ -#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */ -#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */ - -#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */ -#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */ -#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */ -#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */ - -/* Serial Device Enabled - Addr = 0xA8 */ -#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 -/* Serial Device Enabled - Addr = 0xA4 */ -#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 - -/* Pin Straps Reg */ -#define SDR0_PSTRP0 0x0040 -#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ - -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ - -/*----------------------------------------------------------------------------+ -| EBC Configuration Register - EBC0_CFG -+----------------------------------------------------------------------------*/ -/* External Bus Three-State Control */ -#define EBC0_CFG_EBTC_DRIVEN 0x80000000 -/* Device-Paced Time-out Disable */ -#define EBC0_CFG_PTD_ENABLED 0x00000000 -/* Ready Timeout Count */ -#define EBC0_CFG_RTC_MASK 0x38000000 -#define EBC0_CFG_RTC_16PERCLK 0x00000000 -#define EBC0_CFG_RTC_32PERCLK 0x08000000 -#define EBC0_CFG_RTC_64PERCLK 0x10000000 -#define EBC0_CFG_RTC_128PERCLK 0x18000000 -#define EBC0_CFG_RTC_256PERCLK 0x20000000 -#define EBC0_CFG_RTC_512PERCLK 0x28000000 -#define EBC0_CFG_RTC_1024PERCLK 0x30000000 -#define EBC0_CFG_RTC_2048PERCLK 0x38000000 -/* External Master Priority Low */ -#define EBC0_CFG_EMPL_LOW 0x00000000 -#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000 -#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000 -#define EBC0_CFG_EMPL_HIGH 0x06000000 -/* External Master Priority High */ -#define EBC0_CFG_EMPH_LOW 0x00000000 -#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000 -#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000 -#define EBC0_CFG_EMPH_HIGH 0x01800000 -/* Chip Select Three-State Control */ -#define EBC0_CFG_CSTC_DRIVEN 0x00400000 -/* Burst Prefetch */ -#define EBC0_CFG_BPF_ONEDW 0x00000000 -#define EBC0_CFG_BPF_TWODW 0x00100000 -#define EBC0_CFG_BPF_FOURDW 0x00200000 -/* External Master Size */ -#define EBC0_CFG_EMS_8BIT 0x00000000 -/* Power Management Enable */ -#define EBC0_CFG_PME_DISABLED 0x00000000 -#define EBC0_CFG_PME_ENABLED 0x00020000 -/* Power Management Timer */ -#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) - -/*----------------------------------------------------------------------------+ -| Peripheral Bank Configuration Register - EBC0_BnCR -+----------------------------------------------------------------------------*/ -/* BAS - Base Address Select */ -#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) -/* BS - Bank Size */ -#define EBC0_BNCR_BS_MASK 0x000E0000 -#define EBC0_BNCR_BS_1MB 0x00000000 -#define EBC0_BNCR_BS_2MB 0x00020000 -#define EBC0_BNCR_BS_4MB 0x00040000 -#define EBC0_BNCR_BS_8MB 0x00060000 -#define EBC0_BNCR_BS_16MB 0x00080000 -#define EBC0_BNCR_BS_32MB 0x000A0000 -#define EBC0_BNCR_BS_64MB 0x000C0000 -#define EBC0_BNCR_BS_128MB 0x000E0000 -/* BU - Bank Usage */ -#define EBC0_BNCR_BU_MASK 0x00018000 -#define EBC0_BNCR_BU_RO 0x00008000 -#define EBC0_BNCR_BU_WO 0x00010000 -#define EBC0_BNCR_BU_RW 0x00018000 -/* BW - Bus Width */ -#define EBC0_BNCR_BW_MASK 0x00006000 -#define EBC0_BNCR_BW_8BIT 0x00000000 -#define EBC0_BNCR_BW_16BIT 0x00002000 -#define EBC0_BNCR_BW_32BIT 0x00004000 - -/*----------------------------------------------------------------------------+ -| Peripheral Bank Access Parameters - EBC0_BnAP -+----------------------------------------------------------------------------*/ -/* Burst Mode Enable */ -#define EBC0_BNAP_BME_ENABLED 0x80000000 -#define EBC0_BNAP_BME_DISABLED 0x00000000 -/* Transfert Wait */ -#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */ -/* Chip Select On Timing */ -#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */ -/* Output Enable On Timing */ -#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */ -/* Write Back Enable On Timing */ -#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */ -/* Write Back Enable Off Timing */ -#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */ -/* Transfert Hold */ -#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */ -/* PerReady Enable */ -#define EBC0_BNAP_RE_ENABLED 0x00000100 -#define EBC0_BNAP_RE_DISABLED 0x00000000 -/* Sample On Ready */ -#define EBC0_BNAP_SOR_DELAYED 0x00000000 -#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080 -/* Byte Enable Mode */ -#define EBC0_BNAP_BEM_WRITEONLY 0x00000000 -#define EBC0_BNAP_BEM_RW 0x00000040 -/* Parity Enable */ -#define EBC0_BNAP_PEN_DISABLED 0x00000000 -#define EBC0_BNAP_PEN_ENABLED 0x00000020 - -/*----------------------------------------------------------------------------+ -| Define Boot devices -+----------------------------------------------------------------------------*/ -/* */ -#define BOOT_FROM_SMALL_FLASH 0x00 -#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 -#define BOOT_FROM_NAND_FLASH0 0x02 -#define BOOT_FROM_PCI 0x03 -#define BOOT_DEVICE_UNKNOWN 0x04 - - -#define PVR_POWERPC_440EP_PASS1 0x42221850 -#define PVR_POWERPC_440EP_PASS2 0x422218D3 - -#define TRUE 1 -#define FALSE 0 - -#define GPIO_GROUP_MAX 2 -#define GPIO_MAX 32 -#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ -#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ -#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ -#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ -#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ - /* For the other GPIO number, you must shift */ - -#define GPIO0 0 -#define GPIO1 1 - - -/*#define MAX_SELECTION_NB CORE_NB */ -#define MAX_CORE_SELECT_NB 22 - -/*----------------------------------------------------------------------------+ - | PPC440EP GPIOs addresses. - +----------------------------------------------------------------------------*/ -#define GPIO0_BASE 0xEF600B00 -#define GPIO0_REAL 0xEF600B00 - -#define GPIO1_BASE 0xEF600C00 -#define GPIO1_REAL 0xEF600C00 - -/* Offsets */ -#define GPIOx_OR 0x00 /* GPIO Output Register */ -#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ -#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ -#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ -#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ -#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ -#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ -#define GPIOx_IR 0x1C /* GPIO Input Register */ -#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ -#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ -#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ -#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ -#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ -#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ -#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ -#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ -#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ - -/* GPIO0 */ -#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L) -#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H) -#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L) -#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H) -#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L) -#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L) - -/* GPIO1 */ -#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L) -#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H) -#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L) -#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H) -#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L) -#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L) - -#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ -#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ -#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ -#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ -#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ - - -/*----------------------------------------------------------------------------+ - | Declare Configuration values - +----------------------------------------------------------------------------*/ -typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; -typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; - -typedef struct { unsigned long add; /* gpio core base address */ - gpio_driver_t in_out; /* Driver Setting */ - gpio_select_t alt_nb; /* Selected Alternate */ -} gpio_param_s; - -/*----------------------------------------------------------------------------+ - | XX XX - | - | XXXXXX XXX XX XXX XXX - | XX XX X XX XX XX - | XX XX X XX XX XX - | XX XX XX XX XX - | XXXXXX XXX XXX XXXX XXXX - +----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ - | Defines - +----------------------------------------------------------------------------*/ -typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN, - ZMII_CONFIGURATION_IS_MII, - ZMII_CONFIGURATION_IS_RMII, - ZMII_CONFIGURATION_IS_SMII -} zmii_config_t; - -/*----------------------------------------------------------------------------+ - | Declare Configuration values - +----------------------------------------------------------------------------*/ -typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t; -typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t; -typedef enum config_list { IIC_CORE, - SCP_CORE, - DMA_CHANNEL_AB, - UIC_4_9, - USB2_HOST, - DMA_CHANNEL_CD, - USB2_DEVICE, - PACKET_REJ_FUNC_AVAIL, - USB1_DEVICE, - EBC_MASTER, - NAND_FLASH, - UART_CORE0, - UART_CORE1, - UART_CORE2, - UART_CORE3, - MII_SEL, - RMII_SEL, - SMII_SEL, - PACKET_REJ_FUNC_EN, - UIC_0_3, - USB1_HOST, - PCI_PATCH, - CORE_NB -} core_list_t; - -typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5, - B3_V6, B3_V7, B3_V8, B3_V9, B3_V10, - B3_V11, B3_V12, B3_V13, B3_V14, B3_V15, - B3_V16, B3_VALUE_UNKNOWN -} block3_value_t; - -typedef enum config_validity { CONFIG_IS_VALID, - CONFIG_IS_INVALID -} config_validity_t; diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk deleted file mode 100644 index 35cb655..0000000 --- a/board/amcc/bamboo/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xFFF80000 - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c deleted file mode 100644 index a30ab7a..0000000 --- a/board/amcc/bamboo/flash.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu - * Add support for Am29F016D and dynamic switch setting. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include -#include -#include -#include -#include "bamboo.h" - -#undef DEBUG - -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 - */ -static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { - {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ - {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ - {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */ - {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/ - {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/ - {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */ - {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */ - {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */ - {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - unsigned long val; - unsigned long ebc_boot_size; - unsigned long boot_selection; - - mfsdr(sdr_pstrp0, val); - index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29; - - if ((index == 5) || (index == 7)) { - /* - * Boot Settings in IIC EEprom address 0xA8 or 0xA4 - * Read Serial Device Strap Register1 in PPC440EP - */ - mfsdr(sdr_sdstp1, val); - boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; - - switch(boot_selection) { - case SDR0_SDSTP1_BOOT_SEL_EBC: - switch(ebc_boot_size) { - case SDR0_SDSTP1_EBC_ROM_BS_16BIT: - index = 3; - break; - case SDR0_SDSTP1_EBC_ROM_BS_8BIT: - index = 0; - break; - } - break; - - case SDR0_SDSTP1_BOOT_SEL_PCI: - index = 1; - break; - - case SDR0_SDSTP1_BOOT_SEL_NDFC: - index = 2; - break; - } - } else if (index == 0) { - if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) { - index = 8; /* sram below op code flash -> new index 8 */ - } - } - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, - &flash_info[i]); -#if defined(CFG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S deleted file mode 100644 index 7820107..0000000 --- a/board/amcc/bamboo/init.S +++ /dev/null @@ -1,113 +0,0 @@ -/* -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_8M 0x00000060 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) - - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) - tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) - - /* PCI */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) - - /* USB 2.0 Device */ - tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I ) - - tlbtab_end diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds deleted file mode 100644 index 176900e..0000000 --- a/board/amcc/bamboo/u-boot.lds +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/amcc/bamboo/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/bubinga/Makefile b/board/amcc/bubinga/Makefile deleted file mode 100644 index f5bda55..0000000 --- a/board/amcc/bubinga/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c deleted file mode 100644 index fe6ce8a..0000000 --- a/board/amcc/bubinga/bubinga.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -long int spd_sdram(void); - -#include -#include - -int board_early_init_f(void) -{ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000010); - mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */ - mtdcr(uictr, 0x00000010); /* set int trigger levels */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: Bubinga - AMCC PPC405EP Evaluation Board"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - - return (0); -} - -/* - * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! - */ -void sdram_init(void) -{ - return; -} - -/* ------------------------------------------------------------------------- - initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of - the necessary info for SDRAM controller configuration - ------------------------------------------------------------------------- */ -long int initdram(int board_type) -{ - long int ret; - - ret = spd_sdram(); - return ret; -} - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("test: xxx MB - ok\n"); - - return (0); -} diff --git a/board/amcc/bubinga/config.mk b/board/amcc/bubinga/config.mk deleted file mode 100644 index 1bdf5e4..0000000 --- a/board/amcc/bubinga/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xFFFC0000 diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c deleted file mode 100644 index e4832eb..0000000 --- a/board/amcc/bubinga/flash.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); - -unsigned long flash_init(void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = - flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, - &flash_info[0]); -#ifdef CFG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - size_b1 = 0; - flash_info[0].size = size_b0; - } - - /* 2 banks */ - else { - size_b1 = - flash_get_size((vu_long *) FLASH_BASE1_PRELIM, - &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); - base_b1 = -size_b1; - pbcr = (pbcr & 0x0001ffff) | base_b1 | - (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); - base_b0 = base_b1 - size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | - (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ - } - - size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets(base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b0 + size_b0 - CFG_MONITOR_LEN, - base_b0 + size_b0 - 1, &flash_info[0]); - /* Also protect sector containing initial power-up instruction */ - /* (flash_protect() checks address range - other call ignored) */ - (void)flash_protect(FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = - flash_get_size((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets(base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b1 + size_b1 - CFG_MONITOR_LEN, - base_b1 + size_b1 - 1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - (void)flash_protect(FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - CFG_MONITOR_LEN, - base_b0 + size_b0 - 1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - } /* else 2 banks */ - return (size_b0 + size_b1); -} - -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} diff --git a/board/amcc/bubinga/u-boot.lds b/board/amcc/bubinga/u-boot.lds deleted file mode 100644 index be03092..0000000 --- a/board/amcc/bubinga/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c deleted file mode 100644 index 3a50b09..0000000 --- a/board/amcc/common/flash.c +++ /dev/null @@ -1,917 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu - * Add support for Am29F016D and dynamic switch setting. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CFG_FLASH_2ND_16BIT_DEV -static int write_word_1(flash_info_t * info, ulong dest, ulong data); -static int write_word_2(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_1(flash_info_t * info, int s_first, int s_last); -static int flash_erase_2(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); -#endif - -void flash_print_info(flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AMD016: - printf("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: - printf("AM29LV033C (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: - printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_STMW320DT: - printf ("M29W320DT (32 M, top sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - - -/* - * The following code cannot be run from FLASH! - */ -#ifdef CFG_FLASH_2ND_16BIT_DEV -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - /* bit 0 used for big flash marking */ - if ((ulong)addr & 0x1) { - return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info); - } else { - return flash_get_size_1(addr, info); - } -} - -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CFG_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_1(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef CFG_FLASH_2ND_16BIT_DEV -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return flash_erase_2(info, s_first, s_last); - } else { - return flash_erase_1(info, s_first, s_last); - } -} - -static int flash_erase_1(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_1(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef CFG_FLASH_2ND_16BIT_DEV -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return write_word_2(info, dest, data); - } else { - return write_word_1(info, dest, data); - } -} - -static int write_word_1(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -#ifdef CFG_FLASH_2ND_16BIT_DEV - -#undef CFG_FLASH_WORD_SIZE -#define CFG_FLASH_WORD_SIZE unsigned short - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) -{ - short i; - int n; - CFG_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = 0x00400000; break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - /* 1 x 16k boot sector */ - base -= 16 << 10; - --i; - info->start[i] = base; - /* 2 x 8k boot sectors */ - for (n=0; n<2; ++n) { - base -= 8 << 10; - --i; - info->start[i] = base; - } - /* 1 x 32k boot sector */ - base -= 32 << 10; - --i; - info->start[i] = base; - - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_2(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -static int flash_erase_2(flash_info_t * info, int s_first, int s_last) -{ - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_2(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -static int write_word_2(flash_info_t * info, ulong dest, ulong data) -{ - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} -#endif /* CFG_FLASH_2ND_16BIT_DEV */ diff --git a/board/amcc/ebony/Makefile b/board/amcc/ebony/Makefile deleted file mode 100644 index 4a3927b..0000000 --- a/board/amcc/ebony/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/amcc/ebony/config.mk b/board/amcc/ebony/config.mk deleted file mode 100644 index e5722dd..0000000 --- a/board/amcc/ebony/config.mk +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 - -ifeq ($(ramsym),1) -TEXT_BASE = 0x07FD0000 -else -TEXT_BASE = 0xFFFC0000 -endif - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c deleted file mode 100644 index a2595ee..0000000 --- a/board/amcc/ebony/ebony.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (C) 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -long int fixed_sdram(void); - -int board_early_init_f(void) -{ - uint reg; - unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; - unsigned char status; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ - - mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */ - mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ - mtebc(pb7ap, 0x01015280); /* FPGA registers */ - mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ - - /* read FPGA_REG0 and set the bus controller */ - status = *fpga_base; - if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) { - mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */ - mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ - mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */ - mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ - } else { - mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */ - mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ - - /* set CS2 if FLASH_ONBD_N == 0 */ - if (!(status & FLASH_ONBD_N)) { - mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */ - mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ - } - } - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - return 0; -} - -int checkboard(void) -{ - char *s = getenv("serial#"); - - printf("Board: Ebony - AMCC PPC440GP Evaluation Board"); - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - - return (0); -} - -long int initdram(int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram(0); -#else - dram_size = fixed_sdram(); -#endif - return dram_size; -} - -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram(void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay(400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram(mem_mcsts, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The ebony board is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); - if ((strap & 0x00100000) == 0) { - printf("PCI: CPC0_STRP1[PAE] not set.\n"); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - DECLARE_GLOBAL_DATA_PTR; - - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0SA, 0); /* disable */ - out32r(PCIX0_PIM1SA, 0); /* disable */ - out32r(PCIX0_PIM2SA, 0); /* disable */ - out32r(PCIX0_EROMBA, 0); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE); - out32r(PCIX0_PIM0LAH, 0); - out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); - - out32r(PCIX0_BAR0, 0); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); - out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); - - out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - /* The ebony board is always configured as host. */ - return (1); -} -#endif /* defined(CONFIG_PCI) */ diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c deleted file mode 100644 index e8fbbc4..0000000 --- a/board/amcc/ebony/flash.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu - * Add support for Am29F016D and dynamic switch setting. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include -#include -#include - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -#define BOOT_SMALL_FLASH_VAL 4 -#define FLASH_ONBD_N_VAL 2 -#define FLASH_SRAM_SEL_VAL 1 - -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { - {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */ - {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */ - {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */ - {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */ - {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; - unsigned char switch_status; - unsigned short index = 0; - int i; - - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - /* check the bitmap of switch status */ - if (switch_status & BOOT_SMALL_FLASH) { - index += BOOT_SMALL_FLASH_VAL; - } - if (switch_status & FLASH_ONBD_N) { - index += FLASH_ONBD_N_VAL; - } - if (switch_status & FLASH_SRAM_SEL) { - index += FLASH_SRAM_SEL_VAL; - } - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) - flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, - &flash_info[2]); -#ifdef CFG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[2]); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, - &flash_info[2]); -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S deleted file mode 100644 index cc8f8b4..0000000 --- a/board/amcc/ebony/init.S +++ /dev/null @@ -1,96 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) - tlbtab_end diff --git a/board/amcc/ebony/u-boot.lds b/board/amcc/ebony/u-boot.lds deleted file mode 100644 index 5a1c5b1..0000000 --- a/board/amcc/ebony/u-boot.lds +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/amcc/ebony/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/luan/Makefile b/board/amcc/luan/Makefile deleted file mode 100644 index 5654f91..0000000 --- a/board/amcc/luan/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o -OBJS += flash.o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/amcc/luan/config.mk b/board/amcc/luan/config.mk deleted file mode 100644 index f52c206..0000000 --- a/board/amcc/luan/config.mk +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0x00001000 - -ifeq ($(ramsym),1) -TEXT_BASE = 0xFBD00000 -else -TEXT_BASE = 0xFFFC0000 -endif - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h deleted file mode 100644 index 05362e0..0000000 --- a/board/amcc/luan/epld.h +++ /dev/null @@ -1,85 +0,0 @@ -#define EPLD0_FSEL_FB2 0x80 -#define EPLD0_BOOT_SMALL_FLASH 0x40 /* 0 boot from large flash, 1 from small flash */ -#define EPLD0_RAW_CARD_BIT0 0x20 /* raw card EC level */ -#define EPLD0_RAW_CARD_BIT1 0x10 -#define EPLD0_RAW_CARD_BIT2 0x08 -#define EPLD0_EXT_ARB_SEL_N 0x04 /* 0 select on-board ext PCI-X, 1 internal arbiter */ -#define EPLD0_FLASH_ONBRD_N 0x02 /* 0 small flash/SRAM active, 1 block access */ -#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */ - -#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */ -#define EPLD1_PCIX0_CNTL1 0x40 /* S*0 of 9531 */ -#define EPLD1_PCIX0_CNTL2 0x20 /* S*1 of 9531 */ -#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */ -#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */ -#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */ -#define EPLD1_MASTER_CLOCK7 0x02 /* clock source select 7 */ -#define EPLD1_MASTER_CLOCK8 0x01 /* clock source select 8 */ - -#define EPLD2_ETH_MODE_10 0x80 /* Ethernet mode 10 (default = 1) */ -#define EPLD2_ETH_MODE_100 0x40 /* Ethernet mode 100 (default = 1) */ -#define EPLD2_ETH_MODE_1000 0x20 /* Ethernet mode 1000 (default = 1) */ -#define EPLD2_ETH_DUPLEX_MODE 0x10 /* Ethernet force full duplex mode */ -#define EPLD2_RESET_ETH_N 0x08 /* Ethernet reset (default = 1) */ -#define EPLD2_ETH_AUTO_NEGO 0x04 /* Ethernet auto negotiation */ -#define EPLD2_DEFAULT_UART_N 0x01 /* 0 select DSR DTR for UART1 */ - -#define EPLD3_STATUS_LED4 0x08 /* status LED 8 (1 = LED on) */ -#define EPLD3_STATUS_LED3 0x04 /* status LED 4 (1 = LED on) */ -#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */ -#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */ - -#define EPLD4_PCIX0_VTH1 0x80 /* PCI-X 0 VTH1 status */ -#define EPLD4_PCIX0_VTH2 0x40 /* PCI-X 0 VTH2 status */ -#define EPLD4_PCIX0_VTH3 0x20 /* PCI-X 0 VTH3 status */ -#define EPLD4_PCIX0_VTH4 0x10 /* PCI-X 0 VTH4 status */ -#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */ -#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */ -#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */ -#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */ - -#define EPLD5_PCIX0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */ -#define EPLD5_PCIX0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */ -#define EPLD5_PCIX0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */ -#define EPLD5_PCIX0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */ -#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */ -#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */ -#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */ -#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */ - -#define EPLD6_PCIX0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */ -#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */ -#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */ -#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */ -#define EPLD6_PCI1_CLKCNTL1 0x80 /* PCI1 clock control S*0 of 9531 */ -#define EPLD6_PCI1_CLKCNTL2 0x40 /* PCI1 clock control S*1 of 9531 */ -#define EPLD6_PCI2_CLKCNTL1 0x20 /* PCI2 clock control S*0 of 9531 */ -#define EPLD6_PCI2_CLKCNTL2 0x10 /* PCI2 clock control S*1 of 9531 */ - -#define EPLD7_VTH1 0x80 /* PCI2 VTH1 status */ -#define EPLD7_VTH2 0x40 /* PCI2 VTH2 status */ -#define EPLD7_VTH3 0x20 /* PCI2 VTH3 status */ -#define EPLD7_VTH4 0x10 /* PCI2 VTH4 status */ -#define EPLD7_INTA_MODE 0x80 /* see S5 on SW2 for details */ -#define EPLD7_PCI_INT_MODE_N 0x40 /* see S1 on SW2 for details */ -#define EPLD7_WRITE_ENABLE_GPIO 0x20 /* see S2 on SW2 for details */ -#define EPLD7_WRITE_ENABLE_INT 0x10 /* see S3 on SW2 for details */ - - -typedef struct { - unsigned char status; /* misc status */ - unsigned char clock; /* clock status, PCI-X clock control */ - unsigned char ethuart; /* Ethernet, UART status */ - unsigned char leds; /* LED register */ - unsigned char vth01; /* PCI0, PCI1 VTH register */ - unsigned char pciints; /* PCI0, PCI1 interrupts */ - unsigned char pci2; /* PCI2 interrupts, clock control */ - unsigned char vth2; /* PCI2 VTH register */ - unsigned char filler1[4096-8]; - unsigned char gpio00; /* GPIO bits 0-7 */ - unsigned char gpio08; /* GPIO bits 8-15 */ - unsigned char gpio16; /* GPIO bits 16-23 */ - unsigned char gpio24; /* GPIO bits 24-31 */ - unsigned char filler2[4096-4]; - unsigned char version; /* EPLD version */ -} epld_t; diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c deleted file mode 100644 index d3c3c0d..0000000 --- a/board/amcc/luan/flash.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu - * Add support for Am29F016D and dynamic switch setting. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include -#include -#include - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -static unsigned long flash_addr_table[1][CFG_MAX_FLASH_BANKS] = { - {0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - /* read FPGA base register FPGA_REG0 */ - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) - flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, - &flash_info[2]); -#ifdef CFG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[2]); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, - &flash_info[2]); -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S deleted file mode 100644 index 7830ebd..0000000 --- a/board/amcc/luan/init.S +++ /dev/null @@ -1,132 +0,0 @@ -/* -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - -#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */ - /* large flash */ - tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) - tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) - tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) - tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) - - tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) -#else /* else booting from small flash */ - tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - - tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) -#endif - - tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I ) - -#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */ - tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) -#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */ - tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) -#elif (CFG_SMALL_FLASH == 0xfff00000) - tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) -#else - #error DONT KNOW SRAM LOCATION -#endif - - /* internal ram (l2 cache) */ - tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I ) - - /* peripherals at f0000000 */ - tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I ) - - /* PCI */ -#if (CONFIG_COMMANDS & CFG_CMD_PCI) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I ) -#endif - tlbtab_end diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c deleted file mode 100644 index c6b79a9..0000000 --- a/board/amcc/luan/luan.c +++ /dev/null @@ -1,458 +0,0 @@ -/* - * (C) Copyright 2005 - * John Otken, jotken@softadvances.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include "epld.h" - - -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/************************************************************************* - * int board_early_init_f() - * - ************************************************************************/ -int board_early_init_f(void) -{ - volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; - - mtebc( pb0ap, 0x03800000 ); /* set chip selects */ - mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ - mtebc( pb1ap, 0x03800000 ); - mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ - mtebc( pb2ap, 0x03800000 ); - mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ - - mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */ - mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */ - mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */ - mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */ - mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */ - mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */ - mtdcr( uic1sr, 0xffffffff ); - - mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */ - mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */ - mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */ - mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */ - mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */ - mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ - mtdcr( uic0sr, 0xffffffff ); - - x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */ - - return 0; -} - - -/************************************************************************* - * int misc_init_r() - * - ************************************************************************/ -int misc_init_r(void) -{ - volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; - x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */ - - return 0; -} - - -/************************************************************************* - * int checkboard() - * - ************************************************************************/ -int checkboard(void) -{ - char *s = getenv("serial#"); - - printf("Board: Luan - AMCC PPC440SP Evaluation Board"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - - return 0; -} - - -/************************************************************************* - * long int fixed_sdram() - * - ************************************************************************/ -static long int fixed_sdram(void) -{ /* DDR2 init from BDI2000 script */ - mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */ - mtdcr( 0x11, 0x84000000 ); - mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */ - mtdcr( 0x11, 0x2D122000 ); - mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */ - mtdcr( 0x11, 0x00800026 ); - mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */ - mtdcr( 0x11, 0x82000800 ); - mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */ - mtdcr( 0x11, 0x80000000 ); - mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */ - mtdcr( 0x11, 0x00000201 ); - mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */ - mtdcr( 0x11, 0x00000201 ); - mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */ - mtdcr( 0x11, 0x08200000 ); - mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */ - mtdcr( 0x11, 0x80201000 ); - mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */ - mtdcr( 0x11, 0x42103242 ); - mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */ - mtdcr( 0x11, 0x0C100D14 ); - mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */ - mtdcr( 0x11, 0x00000642 ); - mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */ - mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */ - - mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */ - mtdcr( 0x11, 0x81b80000 ); - mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */ - mtdcr( 0x11, 0x82100400 ); - mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */ - mtdcr( 0x11, 0x80820000 ); - mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */ - mtdcr( 0x11, 0x80830000 ); - mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */ - mtdcr( 0x11, 0x80810000 ); - mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */ - mtdcr( 0x11, 0x80800542 ); - mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */ - mtdcr( 0x11, 0x82100400 ); - mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */ - mtdcr( 0x11, 0x99080000 ); - mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */ - mtdcr( 0x11, 0x99080000 ); - mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */ - mtdcr( 0x11, 0x99080000 ); - mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */ - mtdcr( 0x11, 0x99080000 ); - mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */ - mtdcr( 0x11, 0x80800442 ); - mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */ - mtdcr( 0x11, 0x80810380 ); - mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */ - mtdcr( 0x11, 0x80810000 ); - udelay( 10*1000 ); - - mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */ - mtdcr( 0x11, 0x28000000 ); /* set DC_EN */ - udelay( 100*1000 ); - - mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */ - mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */ - - mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */ - mtdcr( 0x11, 0x00000000 ); - mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */ - mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */ - mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */ - mtdcr( 0x11, 0x00000200 ); - - return 512 << 20; -} - - -/************************************************************************* - * long int initdram - * - ************************************************************************/ -long int initdram( int board_type ) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (0); -#else - dram_size = fixed_sdram (); -#endif - - return dram_size; -} - - -/************************************************************************* - * int testdram() - * - ************************************************************************/ -#if defined(CFG_DRAM_TEST) -int testdram(void) -{ - unsigned long *mem = (unsigned long *) 0; - const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; - - mtmsr(0); - - for (k = 0; k < CFG_KBYTES_SDRAM; - ++k, mem += (1024 / sizeof(unsigned long))) { - if ((k & 1023) == 0) { - printf("%3d MB\r", k / 1024); - } - - memset(mem, 0xaaaaaaaa, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - - memset(mem, 0x55555555, 1024); - for (n = 0; n < kend; ++n) { - if (mem[n] != 0x55555555) { - printf("SDRAM test fails at: %08x\n", - (uint) & mem[n]); - return 1; - } - } - } - printf("SDRAM test passes\n"); - - return 0; -} -#endif - - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) -int pci_pre_init( struct pci_controller *hose ) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The luan board is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); - - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ - - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - DECLARE_GLOBAL_DATA_PTR; - - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIX0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); - - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - return 1; -} -#endif /* defined(CONFIG_PCI) */ - - -/************************************************************************* - * hw_watchdog_reset - * - * This routine is called to reset (keep alive) the watchdog timer - * - ************************************************************************/ -#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) -{ -} -#endif - - -/************************************************************************* - * int on_off() - * - ************************************************************************/ -static int on_off( const char *s ) -{ - if (strcmp(s, "on") == 0) { - return 1; - } else if (strcmp(s, "off") == 0) { - return 0; - } - return -1; -} - - -/************************************************************************* - * void l2cache_disable() - * - ************************************************************************/ -static void l2cache_disable(void) -{ - mtdcr( l2_cache_cfg, 0 ); -} - - -/************************************************************************* - * void l2cache_enable() - * - ************************************************************************/ -static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ -{ - mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ - - mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */ - - mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ - - while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */ - - mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ - - mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ - - mtdcr( l2_cache_snp0, 0 ); /* snoop registers */ - mtdcr( l2_cache_snp1, 0 ); - - __asm__ volatile ("sync"); /* msync */ - - mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */ - - __asm__ volatile ("sync"); -} - - -/************************************************************************* - * int l2cache_status() - * - ************************************************************************/ -static int l2cache_status(void) -{ - return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0; -} - - -/************************************************************************* - * int do_l2cache() - * - ************************************************************************/ -int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) -{ - switch (argc) { - case 2: /* on / off */ - switch (on_off(argv[1])) { - case 0: l2cache_disable(); - break; - case 1: l2cache_enable(); - break; - } - /* FALL TROUGH */ - case 1: /* get status */ - printf ("L2 Cache is %s\n", - l2cache_status() ? "ON" : "OFF"); - return 0; - default: - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - return 0; -} - - -U_BOOT_CMD( - l2cache, 2, 1, do_l2cache, - "l2cache - enable or disable L2 cache\n", - "[on, off]\n" - " - enable or disable L2 cache\n" - ); diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds deleted file mode 100644 index d122f49..0000000 --- a/board/amcc/luan/u-boot.lds +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/amcc/luan/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/ocotea/Makefile b/board/amcc/ocotea/Makefile deleted file mode 100644 index af223d2..0000000 --- a/board/amcc/ocotea/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend *~ - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/amcc/ocotea/config.mk b/board/amcc/ocotea/config.mk deleted file mode 100644 index 9e18335..0000000 --- a/board/amcc/ocotea/config.mk +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# AMCC 440GX Reference Platform (Ocotea) board -# - -#TEXT_BASE = 0xFFFE0000 - -ifeq ($(ramsym),1) -TEXT_BASE = 0x07FD0000 -else -TEXT_BASE = 0xFFFC0000 -endif - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/ocotea/flash.c b/board/amcc/ocotea/flash.c deleted file mode 100644 index 5614e20..0000000 --- a/board/amcc/ocotea/flash.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu - * Add support for Am29F016D and dynamic switch setting. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include -#include -#include - -#undef DEBUG - -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define BOOT_SMALL_FLASH 0x40 /* 01000000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -#define BOOT_SMALL_FLASH_VAL 4 -#define FLASH_ONBD_N_VAL 2 -#define FLASH_SRAM_SEL_VAL 1 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { - {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */ - {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */ - {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */ - {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */ - {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */ - {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */ - {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */ - {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; - unsigned char switch_status; - unsigned short index = 0; - int i; - - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - /* check the bitmap of switch status */ - if (switch_status & BOOT_SMALL_FLASH) { - index += BOOT_SMALL_FLASH_VAL; - } - if (switch_status & FLASH_ONBD_N) { - index += FLASH_ONBD_N_VAL; - } - if (switch_status & FLASH_SRAM_SEL) { - index += FLASH_SRAM_SEL_VAL; - } - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = - flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf - ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, - &flash_info[i]); -#ifdef CFG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[i]); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S deleted file mode 100644 index e33427a..0000000 --- a/board/amcc/ocotea/init.S +++ /dev/null @@ -1,97 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) - tlbtab_end diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c deleted file mode 100644 index d1a29c5..0000000 --- a/board/amcc/ocotea/ocotea.c +++ /dev/null @@ -1,528 +0,0 @@ -/* - * Copyright (C) 2004 PaulReynolds@lhsolutions.com - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include "ocotea.h" -#include -#include -#include - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -long int fixed_sdram (void); -void fpga_init (void); - -int board_early_init_f (void) -{ - unsigned long mfr; - unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE; - unsigned char switch_status; - unsigned long cs0_base; - unsigned long cs0_size; - unsigned long cs0_twt; - unsigned long cs2_base; - unsigned long cs2_size; - unsigned long cs2_twt; - - /*-------------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | - EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | - EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); - - /*-------------------------------------------------------------------------+ - | FPGA. Initialize bank 7 with default values. - +-------------------------------------------------------------------------*/ - mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| - EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - if (switch_status & 0x40) { - cs0_base = 0xFFE00000; - cs0_size = EBC_BXCR_BS_2MB; - cs0_twt = 8; - cs2_base = 0xFF800000; - cs2_size = EBC_BXCR_BS_4MB; - cs2_twt = 10; - } else { - cs0_base = 0xFFC00000; - cs0_size = EBC_BXCR_BS_4MB; - cs0_twt = 10; - cs2_base = 0xFF800000; - cs2_size = EBC_BXCR_BS_2MB; - cs2_twt = 8; - } - - /*-------------------------------------------------------------------------+ - | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. - +-------------------------------------------------------------------------*/ - mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)| - cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------------*/ - mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)| - EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | 4 MB FLASH. Initialize bank 2 with default values. - +-------------------------------------------------------------------------*/ - mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)| - cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | FPGA. Initialize bank 7 with default values. - +-------------------------------------------------------------------------*/ - mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| - EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); /* */ - mtdcr (uicb0tr, 0x00000000); /* */ - mtdcr (uicb0vr, 0x00000001); /* */ - mfsdr (sdr_mfr, mfr); - mfr &= ~SDR0_MFR_ECS_MASK; -/* mtsdr(sdr_mfr, mfr); */ - fpga_init(); - - return 0; -} - - -int checkboard (void) -{ - char *s = getenv ("serial#"); - - printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board"); - if (s != NULL) { - puts (", serial# "); - puts (s); - } - putc ('\n'); - - return (0); -} - - -long int initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (0); -#else - dram_size = fixed_sdram (); -#endif - return dram_size; -} - - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay (400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram (mem_mcsts, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) -int pci_pre_init(struct pci_controller * hose ) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The ocotea board is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - DECLARE_GLOBAL_DATA_PTR; - - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIX0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); - - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - /* The ocotea board is always configured as host. */ - return(1); -} -#endif /* defined(CONFIG_PCI) */ - - -void fpga_init(void) -{ - unsigned long group; - unsigned long sdr0_pfc0; - unsigned long sdr0_pfc1; - unsigned long sdr0_cust0; - unsigned long pvr; - - mfsdr (sdr_pfc0, sdr0_pfc0); - mfsdr (sdr_pfc1, sdr0_pfc1); - group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); - pvr = get_pvr (); - - sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE; - if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) { - sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; - out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | - FPGA_REG2_EXT_INTFACE_ENABLE); - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); - } else { - sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; - switch (group) - { - case 0: - case 1: - case 2: - /* CPU trace A */ - out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | - FPGA_REG2_EXT_INTFACE_ENABLE); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); - break; - case 3: - case 4: - case 5: - case 6: - /* CPU trace B - Over EBMI */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); - out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | - FPGA_REG2_EXT_INTFACE_DISABLE); - break; - } - } - - /* Initialize the ethernet specific functions in the fpga */ - mfsdr(sdr_pfc1, sdr0_pfc1); - mfsdr(sdr_cust0, sdr0_cust0); - if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && - ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || - (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) - { - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | - FPGA_REG3_ENET_GROUP7); - } - else - { - if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | - FPGA_REG3_ENET_GROUP7); - } - else - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | - FPGA_REG3_ENET_GROUP8); - } - } - } - else - { - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | - FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); - } - else - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | - FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); - } - } - out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 | - FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 | - FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS); - - /* reset the gigabyte phy if necessary */ - if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3) - { - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) - { - out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE); - udelay(10000); - out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE); - } - else - { - out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE); - udelay(10000); - out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE); - } - } - - /* - * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset - */ - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) { - out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE); - udelay(10000); - out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE); - } - - /* Turn off the LED's */ - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) | - FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB | - FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB); - - return; -} - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - - return (ctrlc()); -} -#endif diff --git a/board/amcc/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h deleted file mode 100644 index 95ce1fd..0000000 --- a/board/amcc/ocotea/ocotea.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Board specific FPGA stuff ... */ -#define FPGA_REG0 (CFG_FPGA_BASE + 0x00) -#define FPGA_REG0_SSCG_MASK 0x80 -#define FPGA_REG0_SSCG_DISABLE 0x00 -#define FPGA_REG0_SSCG_ENABLE 0x80 -#define FPGA_REG0_BOOT_MASK 0x40 -#define FPGA_REG0_BOOT_LARGE_FLASH 0x00 -#define FPGA_REG0_BOOT_SMALL_FLASH 0x40 -#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ARBITER_MASK 0x04 -#define FPGA_REG0_ARBITER_EXT 0x00 -#define FPGA_REG0_ARBITER_INT 0x04 -#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02 -#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00 -#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02 -#define FPGA_REG0_FLASH 0x01 -#define FPGA_REG1 (CFG_FPGA_BASE + 0x01) -#define FPGA_REG1_9772_FSELFBX_MASK 0x80 -#define FPGA_REG1_9772_FSELFBX_6 0x00 -#define FPGA_REG1_9772_FSELFBX_10 0x80 -#define FPGA_REG1_9531_SX_MASK 0x60 -#define FPGA_REG1_9531_SX_33MHZ 0x00 -#define FPGA_REG1_9531_SX_100MHZ 0x20 -#define FPGA_REG1_9531_SX_66MHZ 0x40 -#define FPGA_REG1_9531_SX_133MHZ 0x60 -#define FPGA_REG1_9772_FSELBX_MASK 0x18 -#define FPGA_REG1_9772_FSELBX_4 0x00 -#define FPGA_REG1_9772_FSELBX_6 0x08 -#define FPGA_REG1_9772_FSELBX_8 0x10 -#define FPGA_REG1_9772_FSELBX_10 0x18 -#define FPGA_REG1_SOURCE_MASK 0x07 -#define FPGA_REG1_SOURCE_TC 0x00 -#define FPGA_REG1_SOURCE_66MHZ 0x01 -#define FPGA_REG1_SOURCE_50MHZ 0x02 -#define FPGA_REG1_SOURCE_33MHZ 0x03 -#define FPGA_REG1_SOURCE_25MHZ 0x04 -#define FPGA_REG1_SOURCE_SSDIV1 0x05 -#define FPGA_REG1_SOURCE_SSDIV2 0x06 -#define FPGA_REG1_SOURCE_SSDIV4 0x07 -#define FPGA_REG2 (CFG_FPGA_BASE + 0x02) -#define FPGA_REG2_TC0 0x80 -#define FPGA_REG2_TC1 0x40 -#define FPGA_REG2_TC2 0x20 -#define FPGA_REG2_TC3 0x10 -#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/ -#define FPGA_REG2_EXT_INTFACE_MASK 0x04 -#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00 -#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04 -#define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/ -#define FPGA_REG2_DEFAULT_UART1_N 0x01 -#define FPGA_REG3 (CFG_FPGA_BASE + 0x03) -#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/ -#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/ -#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/ -#define FPGA_REG3_ENET_GROUP0 0x00 -#define FPGA_REG3_ENET_GROUP1 0x10 -#define FPGA_REG3_ENET_GROUP2 0x20 -#define FPGA_REG3_ENET_GROUP3 0x30 -#define FPGA_REG3_ENET_GROUP4 0x40 -#define FPGA_REG3_ENET_GROUP5 0x50 -#define FPGA_REG3_ENET_GROUP6 0x60 -#define FPGA_REG3_ENET_GROUP7 0x70 -#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/ -#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/ -#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/ -#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/ -#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/ -#define FPGA_REG3_STAT_MASK 0x0F -#define FPGA_REG3_STAT_LED8_ENAB 0x08 -#define FPGA_REG3_STAT_LED4_ENAB 0x04 -#define FPGA_REG3_STAT_LED2_ENAB 0x02 -#define FPGA_REG3_STAT_LED1_ENAB 0x01 -#define FPGA_REG3_STAT_LED8_DISAB 0x00 -#define FPGA_REG3_STAT_LED4_DISAB 0x00 -#define FPGA_REG3_STAT_LED2_DISAB 0x00 -#define FPGA_REG3_STAT_LED1_DISAB 0x00 -#define FPGA_REG4 (CFG_FPGA_BASE + 0x04) -#define FPGA_REG4_GPHY_MODE10 0x80 -#define FPGA_REG4_GPHY_MODE100 0x40 -#define FPGA_REG4_GPHY_MODE1000 0x20 -#define FPGA_REG4_GPHY_FRC_DPLX 0x10 -#define FPGA_REG4_GPHY_ANEG_DIS 0x08 -#define FPGA_REG4_CONNECT_PHYS 0x04 - - -#define SDR0_CUST0_ENET3_MASK 0x00000080 -#define SDR0_CUST0_ENET3_COPPER 0x00000000 -#define SDR0_CUST0_ENET3_FIBER 0x00000080 -#define SDR0_CUST0_RGMII3_MASK 0x00000070 -#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) -#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) -#define SDR0_CUST0_RGMII3_DISAB 0x00000000 -#define SDR0_CUST0_RGMII3_RTBI 0x00000040 -#define SDR0_CUST0_RGMII3_RGMII 0x00000050 -#define SDR0_CUST0_RGMII3_TBI 0x00000060 -#define SDR0_CUST0_RGMII3_GMII 0x00000070 -#define SDR0_CUST0_ENET2_MASK 0x00000008 -#define SDR0_CUST0_ENET2_COPPER 0x00000000 -#define SDR0_CUST0_ENET2_FIBER 0x00000008 -#define SDR0_CUST0_RGMII2_MASK 0x00000007 -#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) -#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) -#define SDR0_CUST0_RGMII2_DISAB 0x00000000 -#define SDR0_CUST0_RGMII2_RTBI 0x00000004 -#define SDR0_CUST0_RGMII2_RGMII 0x00000005 -#define SDR0_CUST0_RGMII2_TBI 0x00000006 -#define SDR0_CUST0_RGMII2_GMII 0x00000007 diff --git a/board/amcc/ocotea/u-boot.lds b/board/amcc/ocotea/u-boot.lds deleted file mode 100644 index 316fee8..0000000 --- a/board/amcc/ocotea/u-boot.lds +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/amcc/ocotea/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/walnut/Makefile b/board/amcc/walnut/Makefile deleted file mode 100644 index f5bda55..0000000 --- a/board/amcc/walnut/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/amcc/walnut/config.mk b/board/amcc/walnut/config.mk deleted file mode 100644 index 1bdf5e4..0000000 --- a/board/amcc/walnut/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xFFFC0000 diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c deleted file mode 100644 index 056f9b9..0000000 --- a/board/amcc/walnut/flash.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include -#include -#include - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); - -unsigned long flash_init(void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = - flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, - &flash_info[0]); -#ifdef CFG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - size_b1 = 0; - flash_info[0].size = size_b0; - } else { - /* 2 banks */ - size_b1 = - flash_get_size((vu_long *) FLASH_BASE1_PRELIM, - &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); - base_b1 = -size_b1; - pbcr = - (pbcr & 0x0001ffff) | base_b1 | - (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); - base_b0 = base_b1 - size_b0; - pbcr = - (pbcr & 0x0001ffff) | base_b0 | - (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ - } - - size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets(base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = - flash_get_size((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets(base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b1 + size_b1 - - monitor_flash_len, - base_b1 + size_b1 - 1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - (void)flash_protect(FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - - monitor_flash_len, - base_b0 + size_b0 - 1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - } /* else 2 banks */ - return (size_b0 + size_b1); -} - - -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} diff --git a/board/amcc/walnut/u-boot.lds b/board/amcc/walnut/u-boot.lds deleted file mode 100644 index 1dcbab5..0000000 --- a/board/amcc/walnut/u-boot.lds +++ /dev/null @@ -1,151 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c deleted file mode 100644 index f1a96a6..0000000 --- a/board/amcc/walnut/walnut.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -int board_early_init_f(void) -{ - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut/Sycamore board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* set UART1 control to select CTS/RTS */ -#define FPGA_BRDC 0xF0300004 - *(volatile char *)(FPGA_BRDC) |= 0x1; - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char *s = getenv("serial#"); - uint pvr = get_pvr(); - - if (pvr == PVR_405GPR_RB) { - puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board"); - } else { - puts("Board: Walnut - AMCC PPC405GP Evaluation Board"); - } - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - - return (0); -} - -/* - * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! - */ -void sdram_init(void) -{ - return; -} - -/* - * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of - * the necessary info for SDRAM controller configuration - */ -long int initdram(int board_type) -{ - return spd_sdram(0); -} - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("test: xxx MB - ok\n"); - - return (0); -} diff --git a/board/amcc/yellowstone/Makefile b/board/amcc/yellowstone/Makefile deleted file mode 100644 index 47116d3..0000000 --- a/board/amcc/yellowstone/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/amcc/yellowstone/config.mk b/board/amcc/yellowstone/config.mk deleted file mode 100644 index 4ab0ea0..0000000 --- a/board/amcc/yellowstone/config.mk +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0x00001000 - -ifeq ($(ramsym),1) -TEXT_BASE = 0xFBD00000 -else -TEXT_BASE = 0xFFF80000 -endif - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/yellowstone/init.S b/board/amcc/yellowstone/init.S deleted file mode 100644 index 425ad08..0000000 --- a/board/amcc/yellowstone/init.S +++ /dev/null @@ -1,112 +0,0 @@ -/* -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_8M 0x00000060 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) - - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) - - /* PCI */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) - - /* USB 2.0 Device */ - tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) - - tlbtab_end diff --git a/board/amcc/yellowstone/u-boot.lds b/board/amcc/yellowstone/u-boot.lds deleted file mode 100644 index a0ba44d..0000000 --- a/board/amcc/yellowstone/u-boot.lds +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/amcc/yellowstone/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c deleted file mode 100644 index 8ddf910..0000000 --- a/board/amcc/yellowstone/yellowstone.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -int board_early_init_f(void) -{ - register uint reg; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ - - mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ - mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */ - - mtebc(pb1ap, 0x00000000); - mtebc(pb1cr, 0x00000000); - - mtebc(pb2ap, 0x04814500); - /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ - - mtebc(pb3ap, 0x00000000); - mtebc(pb3cr, 0x00000000); - - mtebc(pb4ap, 0x00000000); - mtebc(pb4cr, 0x00000000); - - mtebc(pb5ap, 0x00000000); - mtebc(pb5cr, 0x00000000); - - /*-------------------------------------------------------------------- - * Setup the GPIO pins - *-------------------------------------------------------------------*/ - /*CPLD cs */ - /*setup Address lines for flash size 64Meg. */ - out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000); - - /*setup emac */ - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); - out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); - - /*UART1 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); - out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); - - /* external interrupts IRQ0...3 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000); - out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); - out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); - -#if 0 /* test-only */ - /*setup USB 2.0 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); - out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); -#endif - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - /*-------------------------------------------------------------------- - * Setup other serial configuration - *-------------------------------------------------------------------*/ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ - mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ - - /*clear tmrclk divisor */ - *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; - - /*enable ethernet */ - *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; - -#if 0 /* test-only */ - /*enable usb 1.1 fs device and remove usb 2.0 reset */ - *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; -#endif - - /*get rid of flash write protect */ - *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; - - return 0; -} - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - uint pbcr; - int size_val = 0; - - /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - switch (gd->bd->bi_flashsize) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - case 32 << 20: - size_val = 5; - break; - case 64 << 20: - size_val = 6; - break; - case 128 << 20: - size_val = 7; - break; - } - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, pbcr); - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - return 0; -} - -int checkboard(void) -{ - char *s = getenv("serial#"); - - printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - - return (0); -} - -/************************************************************************* - * sdram_init -- doesn't use serial presence detect. - * - * Assumes: 256 MB, ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -#define NUM_TRIES 64 -#define NUM_READS 10 - -void sdram_tr1_set(int ram_address, int* tr1_value) -{ - int i; - int j, k; - volatile unsigned int* ram_pointer = (unsigned int*)ram_address; - int first_good = -1, last_bad = 0x1ff; - - unsigned long test[NUM_TRIES] = { - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; - - /* go through all possible SDRAM0_TR1[RDCT] values */ - for (i=0; i<=0x1ff; i++) { - /* set the current value for TR1 */ - mtsdram(mem_tr1, (0x80800800 | i)); - - /* write values */ - for (j=0; j PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - -/************************************************************************* - * pci_master_init - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /*--------------------------------------------------------------------------+ - | Write the PowerPC440 EP PCI Configuration regs. - | Enable PowerPC440 EP to be a master on the PCI bus (PMM). - | Enable PowerPC440 EP to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - /* Bamboo is always configured as host. */ - return (1); -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * hw_watchdog_reset - * - * This routine is called to reset (keep alive) the watchdog timer - * - ************************************************************************/ -#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) -{ - -} -#endif diff --git a/board/amcc/yosemite/Makefile b/board/amcc/yosemite/Makefile deleted file mode 100644 index 47116d3..0000000 --- a/board/amcc/yosemite/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/amcc/yosemite/config.mk b/board/amcc/yosemite/config.mk deleted file mode 100644 index 4ab0ea0..0000000 --- a/board/amcc/yosemite/config.mk +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0x00001000 - -ifeq ($(ramsym),1) -TEXT_BASE = 0xFBD00000 -else -TEXT_BASE = 0xFFF80000 -endif - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S deleted file mode 100644 index 425ad08..0000000 --- a/board/amcc/yosemite/init.S +++ /dev/null @@ -1,112 +0,0 @@ -/* -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_8M 0x00000060 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) - - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) - - /* PCI */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) - - /* USB 2.0 Device */ - tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) - - tlbtab_end diff --git a/board/amcc/yosemite/u-boot.lds b/board/amcc/yosemite/u-boot.lds deleted file mode 100644 index a9a7b0a..0000000 --- a/board/amcc/yosemite/u-boot.lds +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/amcc/yosemite/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c deleted file mode 100644 index 509d8e4..0000000 --- a/board/amcc/yosemite/yosemite.c +++ /dev/null @@ -1,549 +0,0 @@ -/* - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -int board_early_init_f(void) -{ - register uint reg; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ - - mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ - mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */ - - mtebc(pb1ap, 0x00000000); - mtebc(pb1cr, 0x00000000); - - mtebc(pb2ap, 0x04814500); - /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ - - mtebc(pb3ap, 0x00000000); - mtebc(pb3cr, 0x00000000); - - mtebc(pb4ap, 0x00000000); - mtebc(pb4cr, 0x00000000); - - mtebc(pb5ap, 0x00000000); - mtebc(pb5cr, 0x00000000); - - /*-------------------------------------------------------------------- - * Setup the GPIO pins - *-------------------------------------------------------------------*/ - /*CPLD cs */ - /*setup Address lines for flash size 64Meg. */ - out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000); - - /*setup emac */ - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); - out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); - - /*UART1 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); - out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); - - /* external interrupts IRQ0...3 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000); - out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); - out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); - - /*setup USB 2.0 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); - out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - /*-------------------------------------------------------------------- - * Setup other serial configuration - *-------------------------------------------------------------------*/ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ - mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ - - /*clear tmrclk divisor */ - *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; - - /*enable ethernet */ - *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; - - /*enable usb 1.1 fs device and remove usb 2.0 reset */ - *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; - - /*get rid of flash write protect */ - *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; - - return 0; -} - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - uint pbcr; - int size_val = 0; - - /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - switch (gd->bd->bi_flashsize) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - case 32 << 20: - size_val = 5; - break; - case 64 << 20: - size_val = 6; - break; - case 128 << 20: - size_val = 7; - break; - } - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, pbcr); - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - return 0; -} - -int checkboard(void) -{ - char *s = getenv("serial#"); - - printf("Board: Yosemite - AMCC PPC440EP Evaluation Board"); - if (s != NULL) { - puts(", serial# "); - puts(s); - } - putc('\n'); - - return (0); -} - -/************************************************************************* - * sdram_init -- doesn't use serial presence detect. - * - * Assumes: 256 MB, ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -#define NUM_TRIES 64 -#define NUM_READS 10 - -void sdram_tr1_set(int ram_address, int* tr1_value) -{ - int i; - int j, k; - volatile unsigned int* ram_pointer = (unsigned int*)ram_address; - int first_good = -1, last_bad = 0x1ff; - - unsigned long test[NUM_TRIES] = { - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; - - /* go through all possible SDRAM0_TR1[RDCT] values */ - for (i=0; i<=0x1ff; i++) { - /* set the current value for TR1 */ - mtsdram(mem_tr1, (0x80800800 | i)); - - /* write values */ - for (j=0; j PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - -/************************************************************************* - * pci_master_init - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /*--------------------------------------------------------------------------+ - | Write the PowerPC440 EP PCI Configuration regs. - | Enable PowerPC440 EP to be a master on the PCI bus (PMM). - | Enable PowerPC440 EP to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - /* Bamboo is always configured as host. */ - return (1); -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * hw_watchdog_reset - * - * This routine is called to reset (keep alive) the watchdog timer - * - ************************************************************************/ -#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) -{ - -} -#endif diff --git a/board/amirix/ap1000/Makefile b/board/amirix/ap1000/Makefile deleted file mode 100644 index 4e1ef21..0000000 --- a/board/amirix/ap1000/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c deleted file mode 100644 index dd836ce..0000000 --- a/board/amirix/ap1000/ap1000.c +++ /dev/null @@ -1,699 +0,0 @@ -/* - * amirix.c: ppcboot platform support for AMIRIX board - * - * Copyright 2002 Mind NV - * Copyright 2003 AMIRIX Systems Inc. - * - * http://www.mind.be/ - * http://www.amirix.com/ - * - * Author : Peter De Schrijver (p2@mind.be) - * Frank Smith (smith@amirix.com) - * - * Derived from : Other platform support files in this tree, ml2 - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#include -#include -#include - -#include "powerspan.h" -#include "ap1000.h" - -int board_pre_init (void) -{ - return 0; -} - -/** serial number and platform display at startup */ -int checkboard (void) -{ - unsigned char *s = getenv ("serial#"); - unsigned char *e; - - /* After a loadace command, the SystemAce control register is left in a wonky state. */ - /* this code did not work in board_pre_init */ - unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE; - - p[SYSACE_CTRLREG0] = 0x0; - - /* add platform and device to banner */ - switch (get_device ()) { - case AP1xx_AP107_TARGET: - puts (AP1xx_AP107_TARGET_STR); - break; - case AP1xx_AP120_TARGET: - puts (AP1xx_AP120_TARGET_STR); - break; - case AP1xx_AP130_TARGET: - puts (AP1xx_AP130_TARGET_STR); - break; - case AP1xx_AP1070_TARGET: - puts (AP1xx_AP1070_TARGET_STR); - break; - case AP1xx_AP1100_TARGET: - puts (AP1xx_AP1100_TARGET_STR); - break; - default: - puts (AP1xx_UNKNOWN_STR); - break; - } - puts (AP1xx_TARGET_STR); - puts (" with "); - - switch (get_platform ()) { - case AP100_BASELINE_PLATFORM: - case AP1000_BASELINE_PLATFORM: - puts (AP1xx_BASELINE_PLATFORM_STR); - break; - case AP1xx_QUADGE_PLATFORM: - puts (AP1xx_QUADGE_PLATFORM_STR); - break; - case AP1xx_MGT_REF_PLATFORM: - puts (AP1xx_MGT_REF_PLATFORM_STR); - break; - case AP1xx_STANDARD_PLATFORM: - puts (AP1xx_STANDARD_PLATFORM_STR); - break; - case AP1xx_DUAL_PLATFORM: - puts (AP1xx_DUAL_PLATFORM_STR); - break; - case AP1xx_BASE_SRAM_PLATFORM: - puts (AP1xx_BASE_SRAM_PLATFORM_STR); - break; - case AP1xx_PCI_PCB_TESTPLATFORM: - case AP1000_PCI_PCB_TESTPLATFORM: - puts (AP1xx_PCI_PCB_TESTPLATFORM_STR); - break; - case AP1xx_DUAL_GE_MEZZ_TESTPLATFORM: - puts (AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR); - break; - case AP1xx_SFP_MEZZ_TESTPLATFORM: - puts (AP1xx_SFP_MEZZ_TESTPLATFORM_STR); - break; - default: - puts (AP1xx_UNKNOWN_STR); - break; - } - - if ((get_platform () & AP1xx_TESTPLATFORM_MASK) != 0) { - puts (AP1xx_TESTPLATFORM_STR); - } else { - puts (AP1xx_PLATFORM_STR); - } - - putc ('\n'); - - puts ("Serial#: "); - - if (!s) { - printf ("### No HW ID - assuming AMIRIX"); - } else { - for (e = s; *e; ++e) { - if (*e == ' ') - break; - } - - for (; s < e; ++s) { - putc (*s); - } - } - - putc ('\n'); - - return (0); -} - - -long int initdram (int board_type) -{ - unsigned char *s = getenv ("dramsize"); - - if (s != NULL) { - if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) { - s += 2; - } - return simple_strtoul (s, NULL, 16); - } else { - /* give all 64 MB */ - return 64 * 1024 * 1024; - } -} - -unsigned int get_platform (void) -{ - unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR; - - return (*revision_reg_ptr & AP1xx_PLATFORM_MASK); -} - -unsigned int get_device (void) -{ - unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR; - - return (*revision_reg_ptr & AP1xx_TARGET_MASK); -} - -#if 0 /* loadace is not working; it appears to be a hardware issue with the system ace. */ -/* - This function loads FPGA configurations from the SystemACE CompactFlash -*/ -int do_loadace (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE; - int cfg; - - if ((p[SYSACE_STATREG0] & 0x10) == 0) { - p[SYSACE_CTRLREG0] = 0x80; - printf ("\nNo CompactFlash Detected\n\n"); - p[SYSACE_CTRLREG0] = 0x00; - return 1; - } - - /* reset configuration controller: | 0x80 */ - /* select cpflash & ~0x40 */ - /* cfg start | 0x20 */ - /* wait for cfgstart & ~0x10 */ - /* force cfgmode: | 0x08 */ - /* do no force cfgaddr: & ~0x04 */ - /* clear mpulock: & ~0x02 */ - /* do not force lock request & ~0x01 */ - - p[SYSACE_CTRLREG0] = 0x80 | 0x20 | 0x08; - p[SYSACE_CTRLREG1] = 0x00; - - /* force config address if arg2 exists */ - if (argc == 2) { - cfg = simple_strtoul (argv[1], NULL, 10); - - if (cfg > 7) { - printf ("\nInvalid Configuration\n\n"); - p[SYSACE_CTRLREG0] = 0x00; - return 1; - } - /* Set config address */ - p[SYSACE_CTRLREG1] = (cfg << 5); - /* force cfgaddr */ - p[SYSACE_CTRLREG0] |= 0x04; - - } else { - cfg = (p[SYSACE_STATREG1] & 0xE0) >> 5; - } - - /* release configuration controller */ - printf ("\nLoading V2PRO with config %d...\n", cfg); - p[SYSACE_CTRLREG0] &= ~0x80; - - - while ((p[SYSACE_STATREG1] & 0x01) == 0) { - - if (p[SYSACE_ERRREG0] & 0x80) { - /* attempting to load an invalid configuration makes the cpflash */ - /* appear to be removed. Reset here to avoid that problem */ - p[SYSACE_CTRLREG0] = 0x80; - printf ("\nConfiguration %d Read Error\n\n", cfg); - p[SYSACE_CTRLREG0] = 0x00; - return 1; - } - } - - p[SYSACE_CTRLREG0] |= 0x20; - - return 0; -} -#endif - -/** Console command to display and set the software reconfigure byte - * 
-  * swconfig        - display the current value of the software reconfigure byte
-  * swconfig [#]    - change the software reconfigure byte to #
-  *
- * @param *cmdtp [IN] as passed by run_command (ignored) - * @param flag [IN] as passed by run_command (ignored) - * @param argc [IN] as passed by run_command if 1, display, if 2 change - * @param *argv[] [IN] contains the parameters to use - * @return - * 
-  *      0 if passed
-  *     -1 if failed
-  *
- */ -int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - unsigned char *sector_buffer = NULL; - unsigned char input_char; - int write_result; - unsigned int input_uint; - - /* display value if no argument */ - if (argc < 2) { - printf ("Software configuration byte is currently: 0x%02x\n", - *((unsigned char *) (SW_BYTE_SECTOR_ADDR + - SW_BYTE_SECTOR_OFFSET))); - return 0; - } else if (argc > 3) { - printf ("Too many arguments\n"); - return -1; - } - - /* if 3 arguments, 3rd argument is the address to use */ - if (argc == 3) { - input_uint = simple_strtoul (argv[1], NULL, 16); - sector_buffer = (unsigned char *) input_uint; - } else { - sector_buffer = (unsigned char *) DEFAULT_TEMP_ADDR; - } - - input_char = simple_strtoul (argv[1], NULL, 0); - if ((input_char & ~SW_BYTE_MASK) != 0) { - printf ("Input of 0x%02x will be masked to 0x%02x\n", - input_char, (input_char & SW_BYTE_MASK)); - input_char = input_char & SW_BYTE_MASK; - } - - memcpy (sector_buffer, (void *) SW_BYTE_SECTOR_ADDR, - SW_BYTE_SECTOR_SIZE); - sector_buffer[SW_BYTE_SECTOR_OFFSET] = input_char; - - - printf ("Erasing Flash..."); - if (flash_sect_erase - (SW_BYTE_SECTOR_ADDR, - (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))) { - return -1; - } - - printf ("Writing to Flash... "); - write_result = - flash_write (sector_buffer, SW_BYTE_SECTOR_ADDR, - SW_BYTE_SECTOR_SIZE); - if (write_result != 0) { - flash_perror (write_result); - return -1; - } else { - printf ("done\n"); - printf ("Software configuration byte is now: 0x%02x\n", - *((unsigned char *) (SW_BYTE_SECTOR_ADDR + - SW_BYTE_SECTOR_OFFSET))); - } - - return 0; -} - -#define ONE_SECOND 1000000 - -int do_pause (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - int pause_time; - unsigned int delay_time; - int break_loop = 0; - - /* display value if no argument */ - if (argc < 2) { - pause_time = 1; - } - - else if (argc > 2) { - printf ("Too many arguments\n"); - return -1; - } else { - pause_time = simple_strtoul (argv[1], NULL, 0); - } - - printf ("Pausing with a poll time of %d, press any key to reactivate\n", pause_time); - delay_time = pause_time * ONE_SECOND; - while (break_loop == 0) { - udelay (delay_time); - if (serial_tstc () != 0) { - break_loop = 1; - /* eat user key presses */ - while (serial_tstc () != 0) { - serial_getc (); - } - } - } - - return 0; -} - -int do_swreconfig (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - printf ("Triggering software reconfigure (software config byte is 0x%02x)...\n", - *((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))); - udelay (1000); - *((unsigned char *) AP1000_CPLD_BASE) = 1; - - return 0; -} - -#define GET_DECIMAL(low_byte) ((low_byte >> 5) * 125) -#define TEMP_BUSY_BIT 0x80 -#define TEMP_LHIGH_BIT 0x40 -#define TEMP_LLOW_BIT 0x20 -#define TEMP_EHIGH_BIT 0x10 -#define TEMP_ELOW_BIT 0x08 -#define TEMP_OPEN_BIT 0x04 -#define TEMP_ETHERM_BIT 0x02 -#define TEMP_LTHERM_BIT 0x01 - -int do_temp_sensor (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - char cmd; - int ret_val = 0; - unsigned char temp_byte; - int temp; - int temp_low; - int low; - int low_low; - int high; - int high_low; - int therm; - unsigned char user_data[4] = { 0 }; - int user_data_count = 0; - int ii; - - if (argc > 1) { - cmd = argv[1][0]; - } else { - cmd = 's'; /* default to status */ - } - - user_data_count = argc - 2; - for (ii = 0; ii < user_data_count; ii++) { - user_data[ii] = simple_strtoul (argv[2 + ii], NULL, 0); - } - switch (cmd) { - case 's': - if (I2CAccess - (0x2, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - printf ("Status : 0x%02x ", temp_byte); - if (temp_byte & TEMP_BUSY_BIT) - printf ("BUSY "); - - if (temp_byte & TEMP_LHIGH_BIT) - printf ("LHIGH "); - - if (temp_byte & TEMP_LLOW_BIT) - printf ("LLOW "); - - if (temp_byte & TEMP_EHIGH_BIT) - printf ("EHIGH "); - - if (temp_byte & TEMP_ELOW_BIT) - printf ("ELOW "); - - if (temp_byte & TEMP_OPEN_BIT) - printf ("OPEN "); - - if (temp_byte & TEMP_ETHERM_BIT) - printf ("ETHERM "); - - if (temp_byte & TEMP_LTHERM_BIT) - printf ("LTHERM"); - - printf ("\n"); - - if (I2CAccess - (0x3, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - printf ("Config : 0x%02x ", temp_byte); - - if (I2CAccess - (0x4, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - printf ("\n"); - goto fail; - } - printf ("Conversion: 0x%02x\n", temp_byte); - if (I2CAccess - (0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - printf ("Cons Alert: 0x%02x ", temp_byte); - - if (I2CAccess - (0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - printf ("\n"); - goto fail; - } - printf ("Therm Hyst: %d\n", temp_byte); - - if (I2CAccess - (0x0, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - temp = temp_byte; - if (I2CAccess - (0x6, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - low = temp_byte; - if (I2CAccess - (0x5, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - high = temp_byte; - if (I2CAccess - (0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - therm = temp_byte; - printf ("Local Temp: %2d Low: %2d High: %2d THERM: %2d\n", temp, low, high, therm); - - if (I2CAccess - (0x1, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - temp = temp_byte; - if (I2CAccess - (0x10, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - temp_low = temp_byte; - if (I2CAccess - (0x8, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - low = temp_byte; - if (I2CAccess - (0x14, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - low_low = temp_byte; - if (I2CAccess - (0x7, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - high = temp_byte; - if (I2CAccess - (0x13, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - high_low = temp_byte; - if (I2CAccess - (0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - therm = temp_byte; - if (I2CAccess - (0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &temp_byte, I2C_READ) != 0) { - goto fail; - } - printf ("Ext Temp : %2d.%03d Low: %2d.%03d High: %2d.%03d THERM: %2d Offset: %2d\n", temp, GET_DECIMAL (temp_low), low, GET_DECIMAL (low_low), high, GET_DECIMAL (high_low), therm, temp_byte); - break; - case 'l': /* alter local limits : low, high, therm */ - if (argc < 3) { - goto usage; - } - - /* low */ - if (I2CAccess - (0xC, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[0], I2C_WRITE) != 0) { - goto fail; - } - - if (user_data_count > 1) { - /* high */ - if (I2CAccess - (0xB, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[1], I2C_WRITE) != 0) { - goto fail; - } - } - - if (user_data_count > 2) { - /* therm */ - if (I2CAccess - (0x20, I2C_SENSOR_DEV, - I2C_SENSOR_CHIP_SEL, &user_data[2], - I2C_WRITE) != 0) { - goto fail; - } - } - break; - case 'e': /* alter external limits: low, high, therm, offset */ - if (argc < 3) { - goto usage; - } - - /* low */ - if (I2CAccess - (0xE, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[0], I2C_WRITE) != 0) { - goto fail; - } - - if (user_data_count > 1) { - /* high */ - if (I2CAccess - (0xD, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[1], I2C_WRITE) != 0) { - goto fail; - } - } - - if (user_data_count > 2) { - /* therm */ - if (I2CAccess - (0x19, I2C_SENSOR_DEV, - I2C_SENSOR_CHIP_SEL, &user_data[2], - I2C_WRITE) != 0) { - goto fail; - } - } - - if (user_data_count > 3) { - /* offset */ - if (I2CAccess - (0x11, I2C_SENSOR_DEV, - I2C_SENSOR_CHIP_SEL, &user_data[3], - I2C_WRITE) != 0) { - goto fail; - } - } - break; - case 'c': /* alter config settings: config, conv, cons alert, therm hyst */ - if (argc < 3) { - goto usage; - } - - /* config */ - if (I2CAccess - (0x9, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[0], I2C_WRITE) != 0) { - goto fail; - } - - if (user_data_count > 1) { - /* conversion */ - if (I2CAccess - (0xA, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL, - &user_data[1], I2C_WRITE) != 0) { - goto fail; - } - } - - if (user_data_count > 2) { - /* cons alert */ - if (I2CAccess - (0x22, I2C_SENSOR_DEV, - I2C_SENSOR_CHIP_SEL, &user_data[2], - I2C_WRITE) != 0) { - goto fail; - } - } - - if (user_data_count > 3) { - /* therm hyst */ - if (I2CAccess - (0x21, I2C_SENSOR_DEV, - I2C_SENSOR_CHIP_SEL, &user_data[3], - I2C_WRITE) != 0) { - goto fail; - } - } - break; - default: - goto usage; - } - - goto done; -fail: - printf ("Access to sensor failed\n"); - ret_val = -1; - goto done; -usage: - printf ("Usage:\n%s\n", cmdtp->help); - -done: - return ret_val; -} - -U_BOOT_CMD (temp, 6, 0, do_temp_sensor, - "temp - interact with the temperature sensor\n", - "temp [s]\n" - " - Show status.\n" - "temp l LOW [HIGH] [THERM]\n" - " - Set local limits.\n" - "temp e LOW [HIGH] [THERM] [OFFSET]\n" - " - Set external limits.\n" - "temp c CONFIG [CONVERSION] [CONS. ALERT] [THERM HYST]\n" - " - Set config options.\n" - "\n" - "All values can be decimal or hex (hex preceded with 0x).\n" - "Only whole numbers are supported for external limits.\n"); - -#if 0 -U_BOOT_CMD (loadace, 2, 0, do_loadace, - "loadace - load fpga configuration from System ACE compact flash\n", - "N\n" - " - Load configuration N (0-7) from System ACE compact flash\n" - "loadace\n" " - loads default configuration\n"); -#endif - -U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte, - "swconfig- display or modify the software configuration byte\n", - "N [ADDRESS]\n" - " - set software configuration byte to N, optionally use ADDRESS as\n" - " location of buffer for flash copy\n" - "swconfig\n" " - display software configuration byte\n"); - -U_BOOT_CMD (pause, 2, 0, do_pause, - "pause - sleep processor until any key is pressed with poll time of N seconds\n", - "N\n" - " - sleep processor until any key is pressed with poll time of N seconds\n" - "pause\n" - " - sleep processor until any key is pressed with poll time of 1 second\n"); - -U_BOOT_CMD (swrecon, 1, 0, do_swreconfig, - "swrecon - trigger a board reconfigure to the software selected configuration\n", - "\n" - " - trigger a board reconfigure to the software selected configuration\n"); diff --git a/board/amirix/ap1000/ap1000.h b/board/amirix/ap1000/ap1000.h deleted file mode 100644 index 118c4d1..0000000 --- a/board/amirix/ap1000/ap1000.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * ap1000.h: AP1000 (e.g. AP1070, AP1100) board specific definitions and functions that are needed globally - * - * Author : James MacAulay - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#ifndef __AP1000_H -#define __AP1000_H - -/* - * Revision Register stuff - */ -#define AP1xx_FPGA_REV_ADDR 0x29000000 - -#define AP1xx_PLATFORM_MASK 0xFF000000 -#define AP100_BASELINE_PLATFORM 0x01000000 -#define AP1xx_QUADGE_PLATFORM 0x02000000 -#define AP1xx_MGT_REF_PLATFORM 0x03000000 -#define AP1xx_STANDARD_PLATFORM 0x04000000 -#define AP1xx_DUAL_PLATFORM 0x05000000 -#define AP1xx_BASE_SRAM_PLATFORM 0x06000000 - -#define AP1000_BASELINE_PLATFORM 0x21000000 - -#define AP1xx_TESTPLATFORM_MASK 0xC0000000 -#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000 -#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000 -#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000 - -#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000 - -#define AP1xx_TARGET_MASK 0x00FF0000 -#define AP1xx_AP107_TARGET 0x00010000 -#define AP1xx_AP120_TARGET 0x00020000 -#define AP1xx_AP130_TARGET 0x00030000 -#define AP1xx_AP1070_TARGET 0x00040000 -#define AP1xx_AP1100_TARGET 0x00050000 - -#define AP1xx_UNKNOWN_STR "Unknown" - -#define AP1xx_PLATFORM_STR " Platform" -#define AP1xx_BASELINE_PLATFORM_STR "Baseline" -#define AP1xx_QUADGE_PLATFORM_STR "Quad GE" -#define AP1xx_MGT_REF_PLATFORM_STR "MGT Reference" -#define AP1xx_STANDARD_PLATFORM_STR "Standard" -#define AP1xx_DUAL_PLATFORM_STR "Dual" -#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM" - -#define AP1xx_TESTPLATFORM_STR " Test Platform" -#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base" -#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine" -#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine" - -#define AP1xx_TARGET_STR " Board" -#define AP1xx_AP107_TARGET_STR "AP107" -#define AP1xx_AP120_TARGET_STR "AP120" -#define AP1xx_AP130_TARGET_STR "AP130" - -#define AP1xx_AP1070_TARGET_STR "AP1070" -#define AP1xx_AP1100_TARGET_STR "AP1100" - -/* - * Flash Stuff - */ -#define AP1xx_PROGRAM_FLASH_INDEX 0 -#define AP1xx_CONFIG_FLASH_INDEX 1 - -/* - * System Ace Stuff - */ -#define AP1000_SYSACE_REGBASE 0x28000000 - -#define SYSACE_STATREG0 0x04 /* 7:0 */ -#define SYSACE_STATREG1 0x05 /* 15:8 */ -#define SYSACE_STATREG2 0x06 /* 23:16 */ -#define SYSACE_STATREG3 0x07 /* 31:24 */ - -#define SYSACE_ERRREG0 0x08 /* 7:0 */ -#define SYSACE_ERRREG1 0x09 /* 15:8 */ -#define SYSACE_ERRREG2 0x0a /* 23:16 */ -#define SYSACE_ERRREG3 0x0b /* 31:24 */ - -#define SYSACE_CTRLREG0 0x18 /* 7:0 */ -#define SYSACE_CTRLREG1 0x19 /* 15:8 */ -#define SYSACE_CTRLREG2 0x1A /* 23:16 */ -#define SYSACE_CTRLREG3 0x1B /* 31:24 */ - -/* - * Software reconfig thing - */ -#define SW_BYTE_SECTOR_ADDR 0x24FE0000 -#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF -#define SW_BYTE_SECTOR_SIZE 0x00020000 -#define SW_BYTE_MASK 0x00000003 - -#define DEFAULT_TEMP_ADDR 0x00100000 - -#define AP1000_CPLD_BASE 0x26000000 - -/* PowerSpan II Stuff */ -#define PSII_SYNC() asm("eieio") -#define PSPAN_BASEADDR 0x30000000 -#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \ - 0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \ - 0x0, /* Byte 4 - Powerspan reserved - start of short load */ \ - 0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \ - 0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \ - 0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \ - 0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \ - 0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \ - 0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \ - 0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \ - 0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \ - 0x00, /* Byte 15 - Vital Product Data Disabled. */ \ - 0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \ - 0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \ - 0x00, /* Byte 18 - I2O disabled */ \ - 0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \ - 0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \ - 0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \ - 0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \ - 0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \ - 0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \ - 0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \ - /* Long Load Information */ \ - 0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \ - 0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \ - 0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \ - 0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \ - 0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \ - 0x01, /* Byte 39 - Power span revision 1. */ \ - 0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \ - 0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \ - 0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \ - 0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \ - 0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \ - 0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \ - 0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \ - 0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \ - 0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \ - 0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \ - 0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \ - 0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \ - 0x01, /* Byte 59 - PCI-2 class revision 1 */ \ - 0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */ - - -#define EEPROM_LENGTH 64 /* Long Load */ - -#define I2C_SENSOR_DEV 0x9 -#define I2C_SENSOR_CHIP_SEL 0x4 - -/* - * Board Functions - */ -void set_eat_machine_checks(int a_flag); -int get_eat_machine_checks(void); -unsigned int get_platform(void); -unsigned int get_device(void); -void* memcpyb(void * dest,const void *src,size_t count); -int process_bootflag(ulong bootflag); -void user_led_on(void); -void user_led_off(void); - -#endif /* __COMMON_H_ */ diff --git a/board/amirix/ap1000/config.mk b/board/amirix/ap1000/config.mk deleted file mode 100644 index c09783a..0000000 --- a/board/amirix/ap1000/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# Start at bottom of RAM, but at an aliased address so that it looks -# like it's not in RAM. This is a bit of voodoo to allow it to be -# run from RAM instead of Flash. -TEXT_BASE = 0x08000000 diff --git a/board/amirix/ap1000/flash.c b/board/amirix/ap1000/flash.c deleted file mode 100644 index 1a3b252..0000000 --- a/board/amirix/ap1000/flash.c +++ /dev/null @@ -1,903 +0,0 @@ -/** - * @file flash.c - */ - -/* - * (C) Copyright 2003 - * AMIRIX Systems Inc. - * - * Originated from ppcboot-2.0.0/board/esd/cpci440/strataflash.c - * - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for ppcboot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char *cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); -static void flash_write_cmd (flash_info_t * info, int sect, uchar offset, - uchar cmd); -static int flash_isequal (flash_info_t * info, int sect, uchar offset, - uchar cmd); -static int flash_isset (flash_info_t * info, int sect, uchar offset, - uchar cmd); -static int flash_detect_cfi (flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t * info, ulong dest, - cfiword_t cword); -static int flash_full_status_check (flash_info_t * info, ulong sector, - ulong tout, char *prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, - int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -uchar *flash_make_addr (flash_info_t * info, int sect, int offset) -{ - return ((uchar *) (info->start[sect] + (offset * info->chipwidth))); -} - -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -uchar flash_read_uchar (flash_info_t * info, uchar offset) -{ - if (info->portwidth == FLASH_CFI_8BIT) { - volatile uchar *cp; - uchar c; - - cp = flash_make_addr (info, 0, offset); - c = *cp; -#ifdef DEBUG_FLASH - printf ("flash_read_uchar offset=%04x ptr=%08x c=%02x\n", - offset, (unsigned int) cp, c); -#endif - return (c); - - } else if (info->portwidth == FLASH_CFI_16BIT) { - volatile ushort *sp; - ushort s; - uchar c; - - sp = (ushort *) flash_make_addr (info, 0, offset); - s = *sp; - c = (uchar) s; -#ifdef DEBUG_FLASH - printf ("flash_read_uchar offset=%04x ptr=%08x s=%04x c=%02x\n", offset, (unsigned int) sp, s, c); -#endif - return (c); - - } - - return 0; -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort (flash_info_t * info, int sect, uchar offset) -{ - if (info->portwidth == FLASH_CFI_8BIT) { - volatile uchar *cp; - uchar c0, c1; - ushort s; - - cp = flash_make_addr (info, 0, offset); - c1 = cp[2]; - c0 = cp[0]; - s = c1 << 8 | c0; -#ifdef DEBUG_FLASH - printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) cp, c1, c0, s); -#endif - return (s); - - } else if (info->portwidth == FLASH_CFI_16BIT) { - volatile ushort *sp; - ushort s; - uchar c0, c1; - - sp = (ushort *) flash_make_addr (info, 0, offset); - s = *sp; - c1 = (uchar) sp[1]; - c0 = (uchar) sp[0]; - s = c1 << 8 | c0; -#ifdef DEBUG_FLASH - printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) sp, c1, c0, s); -#endif - return (s); - - } - - return 0; -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long (flash_info_t * info, int sect, uchar offset) -{ - if (info->portwidth == FLASH_CFI_8BIT) { - volatile uchar *cp; - uchar c0, c1, c2, c3; - ulong l; - - cp = flash_make_addr (info, 0, offset); - c3 = cp[6]; - c2 = cp[4]; - c1 = cp[2]; - c0 = cp[0]; - l = c3 << 24 | c2 << 16 | c1 << 8 | c0; -#ifdef DEBUG_FLASH - printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) cp, c3, c2, c1, c0, l); -#endif - return (l); - - } else if (info->portwidth == FLASH_CFI_16BIT) { - volatile ushort *sp; - uchar c0, c1, c2, c3; - ulong l; - - sp = (ushort *) flash_make_addr (info, 0, offset); - c3 = (uchar) sp[3]; - c2 = (uchar) sp[2]; - c1 = (uchar) sp[1]; - c0 = (uchar) sp[0]; - l = c3 << 24 | c2 << 16 | c1 << 8 | c0; -#ifdef DEBUG_FLASH - printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) sp, c3, c2, c1, c0, l); -#endif - return (l); - - } - - return 0; -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - - size = 0; - - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[0].portwidth = FLASH_CFI_16BIT; - flash_info[0].chipwidth = FLASH_CFI_16BIT; - size += flash_info[0].size = flash_get_size (CFG_PROGFLASH_BASE, 0); - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20); - }; - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].portwidth = FLASH_CFI_8BIT; - flash_info[1].chipwidth = FLASH_CFI_16BIT; - size += flash_info[1].size = flash_get_size (CFG_CONFFLASH_BASE, 1); - if (flash_info[1].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20); - }; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd (info, sect, 0, - FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sect, 0, - FLASH_CMD_BLOCK_ERASE); - flash_write_cmd (info, sect, 0, - FLASH_CMD_ERASE_CONFIRM); - - if (flash_full_status_check - (info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf ("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf ("CFI conformant FLASH (x%d device in x%d mode)", - (info->chipwidth << 3), (info->portwidth << 3)); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if ((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for (i = 0; i < aln; ++i, ++cp) - flash_add_byte (info, &cword, (*(uchar *) cp)); - - for (; (i < info->portwidth) && (cnt > 0); i++) { - flash_add_byte (info, &cword, *src++); - cnt--; - cp++; - } - for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte (info, &cword, (*(uchar *) cp)); - if ((rc = flash_write_cfiword (info, wp, cword)) != 0) - return rc; - wp = cp; - } -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while (cnt >= info->portwidth) { - i = info->buffer_size > cnt ? cnt : info->buffer_size; - if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -= i; - } -#else - /* handle the aligned part */ - while (cnt >= info->portwidth) { - cword.l = 0; - for (i = 0; i < info->portwidth; i++) { - flash_add_byte (info, &cword, *src++); - } - if ((rc = flash_write_cfiword (info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { - flash_add_byte (info, &cword, *src++); - --cnt; - } - for (; i < info->portwidth; ++i, ++cp) { - flash_add_byte (info, &cword, (*(uchar *) cp)); - } - - return flash_write_cfiword (info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); - if (prot) - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if ((retcode = - flash_full_status_check (info, sector, info->erase_blk_tout, - prot ? "protect" : "unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if (prot == 0) { - int i; - - for (i = 0; i < info->sector_count; i++) { - if (info->protect[i]) - flash_real_protect (info, i, 1); - } - } - } - - return retcode; -} - -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check (flash_info_t * info, ulong sector, ulong tout, - char *prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while (!flash_isset (info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer (start) > info->erase_blk_tout) { - printf ("Flash %s timeout at address %lx\n", prompt, - info->start[sector]); - flash_write_cmd (info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check (flash_info_t * info, ulong sector, - ulong tout, char *prompt) -{ - int retcode; - - retcode = flash_status_check (info, sector, tout, prompt); - if ((retcode == ERR_OK) - && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf ("Flash %s error at address %lx\n", prompt, - info->start[sector]); - if (flash_isset - (info, sector, 0, - FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { - printf ("Command Sequence Error.\n"); - } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) { - printf ("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) { - printf ("Locking Error\n"); - } - if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { - printf ("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) - printf ("Vpp Low Error.\n"); - } - flash_write_cmd (info, sector, 0, FLASH_CMD_RESET); - return retcode; -} - -/*----------------------------------------------------------------------- - */ -static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) -{ - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) -{ - /*int i; */ - uchar *cp = (uchar *) cmdbuf; - - /* for(i=0; i< info->portwidth; i++) */ - /* *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; */ - if (info->portwidth == FLASH_CFI_8BIT - && info->chipwidth == FLASH_CFI_16BIT) { - cp[0] = cmd; - } else if (info->portwidth == FLASH_CFI_16BIT - && info->chipwidth == FLASH_CFI_16BIT) { - cp[0] = '\0'; - cp[1] = cmd; - }; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd (flash_info_t * info, int sect, uchar offset, - uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - - addr.cp = flash_make_addr (info, sect, offset); - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal (flash_info_t * info, int sect, uchar offset, - uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - - cptr.cp = flash_make_addr (info, sect, offset); - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - */ -static int flash_isset (flash_info_t * info, int sect, uchar offset, - uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - - cptr.cp = flash_make_addr (info, sect, offset); - flash_make_cmd (info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi (flash_info_t * info) -{ - -#if 0 - for (info->portwidth = FLASH_CFI_8BIT; - info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) { - for (info->chipwidth = FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd (info, 0, FLASH_OFFSET_CFI, - FLASH_CMD_CFI); - if (flash_isequal - (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') - && flash_isequal (info, 0, - FLASH_OFFSET_CFI_RESP + 1, 'R') - && flash_isequal (info, 0, - FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } -#endif - flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && - flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { - return 1; - } else { - return 0; - }; -} - -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t *info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if (flash_detect_cfi (info)) { -#ifdef DEBUG_FLASH - printf ("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = 1; /* info->portwidth / info->chipwidth; */ - num_erase_regions = - flash_read_uchar (info, - FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf ("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for (i = 0; i < num_erase_regions; i++) { - if (i > NUM_ERASE_REGIONS) { - printf ("%d erase regions found, only %d used\n", num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long (info, 0, - FLASH_OFFSET_ERASE_REGIONS); - erase_region_count = (tmp & 0xffff) + 1; - tmp >>= 16; - erase_region_size = - (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; - for (j = 0; j < erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = - flash_isset (info, sect_cnt, - FLASH_OFFSET_PROTECT, - FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = - (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * - size_ratio; - info->buffer_size = - (1 << - flash_read_ushort (info, 0, - FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = - (tmp * - (1 << - flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = - (tmp * - (1 << - flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT); - info->write_tout = - (tmp * - (1 << - flash_read_uchar (info, - FLASH_OFFSET_WMAX_TOUT))) / 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t * info, ulong dest, - cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr (info, 0, 0); - cptr.cp = (uchar *) dest; - - /* Check if Flash is (sufficiently) erased */ - switch (info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if (!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); - - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - return flash_full_status_check (info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector (flash_info_t * info, ulong addr) -{ - int sector; - - for (sector = info->sector_count - 1; sector >= 0; sector--) { - if (addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, - int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *) dest; - sector = find_sector (info, dest); - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if ((retcode = - flash_status_check (info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) { - switch (info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd (info, sector, 0, - FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = - flash_full_status_check (info, sector, - info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/amirix/ap1000/init.S b/board/amirix/ap1000/init.S deleted file mode 100644 index 3aaa5c2..0000000 --- a/board/amirix/ap1000/init.S +++ /dev/null @@ -1,34 +0,0 @@ -/* - * init.S: Stubs for ppcboot initialization - * - * Copyright 2002 Mind NV - * - * http://www.mind.be/ - * - * Author : Peter De Schrijver (p2@mind.be) - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#include - -#include -#include - -#include -#include - - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - blr - - .globl sdram_init -sdram_init: - blr diff --git a/board/amirix/ap1000/pci.c b/board/amirix/ap1000/pci.c deleted file mode 100644 index a6436ac..0000000 --- a/board/amirix/ap1000/pci.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2003 - * AMIRIX Systems Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define PCI_MEM_82559ER_CSR_BASE 0x30200000 -#define PCI_IO_82559ER_CSR_BASE 0x40000200 - -/** AP1100 specific values */ -#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */ -#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */ -#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */ -#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */ -#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */ -#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */ -#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */ -#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */ - -/* static int G_verbosity_level = 1; */ -#define G_verbosity_level 1 - -void write1 (unsigned long addr, unsigned char val) -{ - volatile unsigned char *p = (volatile unsigned char *) addr; - - if (G_verbosity_level > 1) - printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr, - val); - *p = val; - asm ("eieio"); -} - -unsigned char read1 (unsigned long addr) -{ - unsigned char val; - volatile unsigned char *p = (volatile unsigned char *) addr; - - if (G_verbosity_level > 1) - printf ("read1: addr=%08x ", (unsigned int) addr); - val = *p; - asm ("eieio"); - if (G_verbosity_level > 1) - printf ("val=%08x\n", val); - return val; -} - -void write2 (unsigned long addr, unsigned short val) -{ - volatile unsigned short *p = (volatile unsigned short *) addr; - - if (G_verbosity_level > 1) - printf ("write2: addr=%08x val=%04x -> *p=%04x\n", - (unsigned int) addr, val, - ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8)); - - *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); - asm ("eieio"); -} - -unsigned short read2 (unsigned long addr) -{ - unsigned short val; - volatile unsigned short *p = (volatile unsigned short *) addr; - - if (G_verbosity_level > 1) - printf ("read2: addr=%08x ", (unsigned int) addr); - val = *p; - val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); - asm ("eieio"); - if (G_verbosity_level > 1) - printf ("*p=%04x -> val=%04x\n", - ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val); - return val; -} - -void write4 (unsigned long addr, unsigned long val) -{ - volatile unsigned long *p = (volatile unsigned long *) addr; - - if (G_verbosity_level > 1) - printf ("write4: addr=%08x val=%08x -> *p=%08x\n", - (unsigned int) addr, (unsigned int) val, - (unsigned int) (((val & 0xFF000000) >> 24) | - ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | - ((val & 0x0000FF00) << 8))); - - *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); - asm ("eieio"); -} - -unsigned long read4 (unsigned long addr) -{ - unsigned long val; - volatile unsigned long *p = (volatile unsigned long *) addr; - - if (G_verbosity_level > 1) - printf ("read4: addr=%08x", (unsigned int) addr); - - val = *p; - val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); - asm ("eieio"); - - if (G_verbosity_level > 1) - printf ("*p=%04x -> val=%04x\n", - (unsigned int) (((val & 0xFF000000) >> 24) | - ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | - ((val & 0x0000FF00) << 8)), - (unsigned int) val); - return val; -} - -void write4be (unsigned long addr, unsigned long val) -{ - volatile unsigned long *p = (volatile unsigned long *) addr; - - if (G_verbosity_level > 1) - printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr, - (unsigned int) val); - *p = val; - asm ("eieio"); -} - -/** One byte configuration write on PSII. - * Currently fixes destination PCI bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Address of location for received byte. - * @return Always Zero. - */ -static int psII_read_config_byte (struct pci_controller *hose, - pci_dev_t dev, int reg, u8 * val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - *val = read1 (PSII_CONFIG_DATA + (reg & 0x03)); - return (0); -} - -/** One byte configuration write on PSII. - * Currently fixes destination bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Output byte. - * @return Always Zero. - */ -static int psII_write_config_byte (struct pci_controller *hose, - pci_dev_t dev, int reg, u8 val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val); - - return (0); -} - -/** One word (16 bit) configuration read on PSII. - * Currently fixes destination PCI bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Address of location for received word. - * @return Always Zero. - */ -static int psII_read_config_word (struct pci_controller *hose, - pci_dev_t dev, int reg, u16 * val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - *val = read2 (PSII_CONFIG_DATA + (reg & 0x03)); - return (0); -} - -/** One word (16 bit) configuration write on PSII. - * Currently fixes destination bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Output word. - * @return Always Zero. - */ -static int psII_write_config_word (struct pci_controller *hose, - pci_dev_t dev, int reg, u16 val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val); - - return (0); -} - -/** One DWord (32 bit) configuration read on PSII. - * Currently fixes destination PCI bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Address of location for received byte. - * @return Always Zero. - */ -static int psII_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int reg, u32 * val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - *val = read4 (PSII_CONFIG_DATA); - return (0); -} - -/** One DWord (32 bit) configuration write on PSII. - * Currently fixes destination bus to PCI2, onboard - * pci. - * @param hose PCI Host controller information. Ignored. - * @param dev Encoded PCI device/Bus and Function value. - * @param reg PCI Configuration register number. - * @param val Output Dword. - * @return Always Zero. - */ -static int psII_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int reg, u32 val) -{ - write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */ - (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */ - - write4 (PSII_CONFIG_DATA, (unsigned long) val); - - return (0); -} - -static struct pci_config_table ap1000_config_table[] = { -#ifdef CONFIG_AP1000 - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS (CFG_ETH_DEV_FN), PCI_DEV (CFG_ETH_DEV_FN), - PCI_FUNC (CFG_ETH_DEV_FN), - pci_cfgfunc_config_device, - {CFG_ETH_IOBASE, CFG_ETH_MEMBASE, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, -#endif - {} -}; - -static struct pci_controller psII_hose = { - config_table:ap1000_config_table, -}; - -void pci_init_board (void) -{ - struct pci_controller *hose = &psII_hose; - - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region (hose->regions + 0, - AP1000_SYS_MEM_START, AP1000_SYS_MEM_START, - AP1000_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI Memory space */ - pci_set_region (hose->regions + 1, - PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE, - PSII_PCI_MEM_SIZE, PCI_REGION_MEM); - - /* No IO Memory space - for now */ - - pci_set_ops (hose, - psII_read_config_byte, - psII_read_config_word, - psII_read_config_dword, - psII_write_config_byte, - psII_write_config_word, psII_write_config_dword); - - hose->region_count = 2; - - pci_register_hose (hose); - - hose->last_busno = pci_hose_scan (hose); -} diff --git a/board/amirix/ap1000/powerspan.c b/board/amirix/ap1000/powerspan.c deleted file mode 100644 index f048155..0000000 --- a/board/amirix/ap1000/powerspan.c +++ /dev/null @@ -1,750 +0,0 @@ -/** - * @file powerspan.c Source file for PowerSpan II code. - */ - -/* - * (C) Copyright 2005 - * AMIRIX Systems Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "powerspan.h" -#define tolower(x) x -#include "ap1000.h" - -#ifdef INCLUDE_PCI - -/** Write one byte with byte swapping. - * @param addr [IN] the address to write to - * @param val [IN] the value to write - */ -void write1 (unsigned long addr, unsigned char val) -{ - volatile unsigned char *p = (volatile unsigned char *) addr; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("write1: addr=%08x val=%02x\n", addr, val); - } -#endif - *p = val; - PSII_SYNC (); -} - -/** Read one byte with byte swapping. - * @param addr [IN] the address to read from - * @return the value at addr - */ -unsigned char read1 (unsigned long addr) -{ - unsigned char val; - volatile unsigned char *p = (volatile unsigned char *) addr; - - val = *p; - PSII_SYNC (); -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("read1: addr=%08x val=%02x\n", addr, val); - } -#endif - return val; -} - -/** Write one 2-byte word with byte swapping. - * @param addr [IN] the address to write to - * @param val [IN] the value to write - */ -void write2 (unsigned long addr, unsigned short val) -{ - volatile unsigned short *p = (volatile unsigned short *) addr; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("write2: addr=%08x val=%04x -> *p=%04x\n", addr, val, - ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8)); - } -#endif - *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); - PSII_SYNC (); -} - -/** Read one 2-byte word with byte swapping. - * @param addr [IN] the address to read from - * @return the value at addr - */ -unsigned short read2 (unsigned long addr) -{ - unsigned short val; - volatile unsigned short *p = (volatile unsigned short *) addr; - - val = *p; - val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8); - PSII_SYNC (); -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p, - val); - } -#endif - return val; -} - -/** Write one 4-byte word with byte swapping. - * @param addr [IN] the address to write to - * @param val [IN] the value to write - */ -void write4 (unsigned long addr, unsigned long val) -{ - volatile unsigned long *p = (volatile unsigned long *) addr; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("write4: addr=%08x val=%08x -> *p=%08x\n", addr, val, - ((val & 0xFF000000) >> 24) | - ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | - ((val & 0x0000FF00) << 8)); - } -#endif - *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); - PSII_SYNC (); -} - -/** Read one 4-byte word with byte swapping. - * @param addr [IN] the address to read from - * @return the value at addr - */ -unsigned long read4 (unsigned long addr) -{ - unsigned long val; - volatile unsigned long *p = (volatile unsigned long *) addr; - - val = *p; - val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) | - ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8); - PSII_SYNC (); -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p, - val); - } -#endif - return val; -} - -int PCIReadConfig (int bus, int dev, int fn, int reg, int width, - unsigned long *val) -{ - unsigned int conAdrVal; - unsigned int conDataReg = REG_CONFIG_DATA; - unsigned int status; - int ret_val = 0; - - - /* DEST bit hardcoded to 1: local pci is PCI-2 */ - /* TYPE bit is hardcoded to 1: all config cycles are local */ - conAdrVal = (1 << 24) - | ((bus & 0xFF) << 16) - | ((dev & 0xFF) << 11) - | ((fn & 0x07) << 8) - | (reg & 0xFC); - - /* clear any pending master aborts */ - write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); - - /* Load the conAdrVal value first, then read from pb_conf_data */ - write4 (REG_CONFIG_ADDRESS, conAdrVal); - PSII_SYNC (); - - - /* Note: documentation does not match the pspan library code */ - /* Note: *pData comes back as -1 if device is not present */ - switch (width) { - case 4: - *(unsigned int *) val = read4 (conDataReg); - break; - case 2: - *(unsigned short *) val = read2 (conDataReg); - break; - case 1: - *(unsigned char *) val = read1 (conDataReg); - break; - default: - ret_val = ILLEGAL_REG_OFFSET; - break; - } - PSII_SYNC (); - - /* clear any pending master aborts */ - status = read4 (REG_P1_CSR); - if (status & CLEAR_MASTER_ABORT) { - ret_val = NO_DEVICE_FOUND; - write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); - } - - return ret_val; -} - - -int PCIWriteConfig (int bus, int dev, int fn, int reg, int width, - unsigned long val) -{ - unsigned int conAdrVal; - unsigned int conDataReg = REG_CONFIG_DATA; - unsigned int status; - int ret_val = 0; - - - /* DEST bit hardcoded to 1: local pci is PCI-2 */ - /* TYPE bit is hardcoded to 1: all config cycles are local */ - conAdrVal = (1 << 24) - | ((bus & 0xFF) << 16) - | ((dev & 0xFF) << 11) - | ((fn & 0x07) << 8) - | (reg & 0xFC); - - /* clear any pending master aborts */ - write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); - - /* Load the conAdrVal value first, then read from pb_conf_data */ - write4 (REG_CONFIG_ADDRESS, conAdrVal); - PSII_SYNC (); - - - /* Note: documentation does not match the pspan library code */ - /* Note: *pData comes back as -1 if device is not present */ - switch (width) { - case 4: - write4 (conDataReg, val); - break; - case 2: - write2 (conDataReg, val); - break; - case 1: - write1 (conDataReg, val); - break; - default: - ret_val = ILLEGAL_REG_OFFSET; - break; - } - PSII_SYNC (); - - /* clear any pending master aborts */ - status = read4 (REG_P1_CSR); - if (status & CLEAR_MASTER_ABORT) { - ret_val = NO_DEVICE_FOUND; - write4 (REG_P1_CSR, CLEAR_MASTER_ABORT); - } - - return ret_val; -} - - -int pci_read_config_byte (int bus, int dev, int fn, int reg, - unsigned char *val) -{ - unsigned long read_val; - int ret_val; - - ret_val = PCIReadConfig (bus, dev, fn, reg, 1, &read_val); - *val = read_val & 0xFF; - - return ret_val; -} - -int pci_write_config_byte (int bus, int dev, int fn, int reg, - unsigned char val) -{ - return PCIWriteConfig (bus, dev, fn, reg, 1, val); -} - -int pci_read_config_word (int bus, int dev, int fn, int reg, - unsigned short *val) -{ - unsigned long read_val; - int ret_val; - - ret_val = PCIReadConfig (bus, dev, fn, reg, 2, &read_val); - *val = read_val & 0xFFFF; - - return ret_val; -} - -int pci_write_config_word (int bus, int dev, int fn, int reg, - unsigned short val) -{ - return PCIWriteConfig (bus, dev, fn, reg, 2, val); -} - -int pci_read_config_dword (int bus, int dev, int fn, int reg, - unsigned long *val) -{ - return PCIReadConfig (bus, dev, fn, reg, 4, val); -} - -int pci_write_config_dword (int bus, int dev, int fn, int reg, - unsigned long val) -{ - return PCIWriteConfig (bus, dev, fn, reg, 4, val); -} - -#endif /* INCLUDE_PCI */ - -int I2CAccess (unsigned char theI2CAddress, unsigned char theDevCode, - unsigned char theChipSel, unsigned char *theValue, int RWFlag) -{ - int ret_val = 0; - unsigned int reg_value; - - reg_value = PowerSpanRead (REG_I2C_CSR); - - if (reg_value & I2C_CSR_ACT) { - printf ("Error: I2C busy\n"); - ret_val = I2C_BUSY; - } else { - reg_value = ((theI2CAddress & 0xFF) << 24) - | ((theDevCode & 0x0F) << 12) - | ((theChipSel & 0x07) << 9) - | I2C_CSR_ERR; - if (RWFlag == I2C_WRITE) { - reg_value |= I2C_CSR_RW | ((*theValue & 0xFF) << 16); - } - - PowerSpanWrite (REG_I2C_CSR, reg_value); - udelay (1); - - do { - reg_value = PowerSpanRead (REG_I2C_CSR); - - if ((reg_value & I2C_CSR_ACT) == 0) { - if (reg_value & I2C_CSR_ERR) { - ret_val = I2C_ERR; - } else { - *theValue = - (reg_value & I2C_CSR_DATA) >> - 16; - } - } - } while (reg_value & I2C_CSR_ACT); - } - - return ret_val; -} - -int EEPROMRead (unsigned char theI2CAddress, unsigned char *theValue) -{ - return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL, - theValue, I2C_READ); -} - -int EEPROMWrite (unsigned char theI2CAddress, unsigned char theValue) -{ - return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL, - &theValue, I2C_WRITE); -} - -int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - char cmd; - int ret_val = 0; - unsigned int address = 0; - unsigned char value = 1; - unsigned char read_value; - int ii; - int error = 0; - unsigned char *mem_ptr; - unsigned char default_eeprom[] = EEPROM_DEFAULT; - - if (argc < 2) { - goto usage; - } - - cmd = argv[1][0]; - if (argc > 2) { - address = simple_strtoul (argv[2], NULL, 16); - if (argc > 3) { - value = simple_strtoul (argv[3], NULL, 16) & 0xFF; - } - } - - switch (cmd) { - case 'r': - if (address > 256) { - printf ("Illegal Address\n"); - goto usage; - } - printf ("@0x%x: ", address); - for (ii = 0; ii < value; ii++) { - if (EEPROMRead (address + ii, &read_value) != - 0) { - printf ("Read Error\n"); - } else { - printf ("0x%02x ", read_value); - } - - if (((ii + 1) % 16) == 0) { - printf ("\n"); - } - } - printf ("\n"); - break; - case 'w': - if (address > 256) { - printf ("Illegal Address\n"); - goto usage; - } - if (argc < 4) { - goto usage; - } - if (EEPROMWrite (address, value) != 0) { - printf ("Write Error\n"); - } - break; - case 'g': - if (argc != 3) { - goto usage; - } - mem_ptr = (unsigned char *) address; - for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); - ii++) { - if (EEPROMRead (ii, &read_value) != 0) { - printf ("Read Error\n"); - error = 1; - } else { - *mem_ptr = read_value; - mem_ptr++; - } - } - break; - case 'p': - if (argc != 3) { - goto usage; - } - mem_ptr = (unsigned char *) address; - for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); - ii++) { - if (EEPROMWrite (ii, *mem_ptr) != 0) { - printf ("Write Error\n"); - error = 1; - } - - mem_ptr++; - } - break; - case 'd': - if (argc != 2) { - goto usage; - } - for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0)); - ii++) { - if (EEPROMWrite (ii, default_eeprom[ii]) != 0) { - printf ("Write Error\n"); - error = 1; - } - } - break; - default: - goto usage; - } - - goto done; - usage: - printf ("Usage:\n%s\n", cmdtp->help); - - done: - return ret_val; - -} - -U_BOOT_CMD (eeprom, 4, 0, do_eeprom, - "eeprom - read/write/copy to/from the PowerSpan II eeprom\n", - "eeprom r OFF [NUM]\n" - " - read NUM words starting at OFF\n" - "eeprom w OFF VAL\n" - " - write word VAL at offset OFF\n" - "eeprom g ADD\n" - " - store contents of eeprom at address ADD\n" - "eeprom p ADD\n" - " - put data stored at address ADD into the eeprom\n" - "eeprom d\n" " - return eeprom to default contents\n"); - -unsigned int PowerSpanRead (unsigned int theOffset) -{ - volatile unsigned int *ptr = - (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); - unsigned int ret_val; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("PowerSpanRead: offset=%08x ", theOffset); - } -#endif - ret_val = *ptr; - PSII_SYNC (); - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("value=%08x\n", ret_val); - } -#endif - - return ret_val; -} - -void PowerSpanWrite (unsigned int theOffset, unsigned int theValue) -{ - volatile unsigned int *ptr = - (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("PowerSpanWrite: offset=%08x val=%02x\n", theOffset, - theValue); - } -#endif - *ptr = theValue; - PSII_SYNC (); -} - -/** - * Sets the indicated bits in the indicated register. - * @param theOffset [IN] the register to access. - * @param theMask [IN] bits set in theMask will be set in the register. - */ -void PowerSpanSetBits (unsigned int theOffset, unsigned int theMask) -{ - volatile unsigned int *ptr = - (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); - unsigned int register_value; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("PowerSpanSetBits: offset=%08x mask=%02x\n", - theOffset, theMask); - } -#endif - register_value = *ptr; - PSII_SYNC (); - - register_value |= theMask; - *ptr = register_value; - PSII_SYNC (); -} - -/** - * Clears the indicated bits in the indicated register. - * @param theOffset [IN] the register to access. - * @param theMask [IN] bits set in theMask will be cleared in the register. - */ -void PowerSpanClearBits (unsigned int theOffset, unsigned int theMask) -{ - volatile unsigned int *ptr = - (volatile unsigned int *) (PSPAN_BASEADDR + theOffset); - unsigned int register_value; - -#ifdef VERBOSITY - if (gVerbosityLevel > 1) { - printf ("PowerSpanClearBits: offset=%08x mask=%02x\n", - theOffset, theMask); - } -#endif - register_value = *ptr; - PSII_SYNC (); - - register_value &= ~theMask; - *ptr = register_value; - PSII_SYNC (); -} - -/** - * Configures a slave image on the local bus, based on the parameters and some hardcoded system values. - * Slave Images are images that cause the PowerSpan II to be a master on the PCI bus. Thus, they - * are outgoing from the standpoint of the local bus. - * @param theImageIndex [IN] the PowerSpan II image to set (assumed to be 0-7). - * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: PB_SIx_CTL[BS]). - * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set. - * @param theEndianness [IN] the endian bits for the image (already shifted, use defines). - * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size). - * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size). - */ -int SetSlaveImage (int theImageIndex, unsigned int theBlockSize, - int theMemIOFlag, int theEndianness, - unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr) -{ - unsigned int reg_offset = theImageIndex * PB_SLAVE_IMAGE_OFF; - unsigned int reg_value = 0; - - /* Make sure that the Slave Image is disabled */ - PowerSpanClearBits ((REGS_PB_SLAVE_CSR + reg_offset), - PB_SLAVE_CSR_IMG_EN); - - /* Setup the mask required for requested PB Slave Image configuration */ - reg_value = PB_SLAVE_CSR_TA_EN | theEndianness | (theBlockSize << 24); - if (theMemIOFlag == PB_SLAVE_USE_MEM_IO) { - reg_value |= PB_SLAVE_CSR_MEM_IO; - } - - /* hardcoding the following: - TA_EN = 1 - MD_EN = 0 - MODE = 0 - PRKEEP = 0 - RD_AMT = 0 - */ - PowerSpanWrite ((REGS_PB_SLAVE_CSR + reg_offset), reg_value); - - /* these values are not checked by software */ - PowerSpanWrite ((REGS_PB_SLAVE_BADDR + reg_offset), theLocalBaseAddr); - PowerSpanWrite ((REGS_PB_SLAVE_TADDR + reg_offset), thePCIBaseAddr); - - /* Enable the Slave Image */ - PowerSpanSetBits ((REGS_PB_SLAVE_CSR + reg_offset), - PB_SLAVE_CSR_IMG_EN); - - return 0; -} - -/** - * Configures a target image on the local bus, based on the parameters and some hardcoded system values. - * Target Images are used when the PowerSpan II is acting as a target for an access. Thus, they - * are incoming from the standpoint of the local bus. - * In order to behave better on the host PCI bus, if thePCIBaseAddr is NULL (0x00000000), then the PCI - * base address will not be updated; makes sense given that the hosts own memory should be mapped to - * PCI address 0x00000000. - * @param theImageIndex [IN] the PowerSpan II image to set. - * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: Px_TIx_CTL[BS]). - * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set. - * @param theEndianness [IN] the endian bits for the image (already shifted, use defines). - * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size). - * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size). - */ -int SetTargetImage (int theImageIndex, unsigned int theBlockSize, - int theMemIOFlag, int theEndianness, - unsigned int theLocalBaseAddr, - unsigned int thePCIBaseAddr) -{ - unsigned int csr_reg_offset = theImageIndex * P1_TGT_IMAGE_OFF; - unsigned int pci_reg_offset = theImageIndex * P1_BST_OFF; - unsigned int reg_value = 0; - - /* Make sure that the Slave Image is disabled */ - PowerSpanClearBits ((REGS_P1_TGT_CSR + csr_reg_offset), - PB_SLAVE_CSR_IMG_EN); - - /* Setup the mask required for requested PB Slave Image configuration */ - reg_value = - PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) | - PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness; - if (theMemIOFlag == PX_TGT_USE_MEM_IO) { - reg_value |= PX_TGT_MEM_IO; - } - - /* hardcoding the following: - TA_EN = 1 - BAR_EN = 1 - MD_EN = 0 - MODE = 0 - DEST = 0 - RTT = 01010 - GBL = 0 - CI = 0 - WTT = 00010 - PRKEEP = 0 - MRA = 0 - RD_AMT = 0 - */ - PowerSpanWrite ((REGS_P1_TGT_CSR + csr_reg_offset), reg_value); - - PowerSpanWrite ((REGS_P1_TGT_TADDR + csr_reg_offset), - theLocalBaseAddr); - - if (thePCIBaseAddr != (unsigned int) NULL) { - PowerSpanWrite ((REGS_P1_BST + pci_reg_offset), - thePCIBaseAddr); - } - - /* Enable the Slave Image */ - PowerSpanSetBits ((REGS_P1_TGT_CSR + csr_reg_offset), - PB_SLAVE_CSR_IMG_EN); - - return 0; -} - -int do_bridge (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - char cmd; - int ret_val = 1; - unsigned int image_index; - unsigned int block_size; - unsigned int mem_io; - unsigned int local_addr; - unsigned int pci_addr; - int endianness; - - if (argc != 8) { - goto usage; - } - - cmd = argv[1][0]; - image_index = simple_strtoul (argv[2], NULL, 16); - block_size = simple_strtoul (argv[3], NULL, 16); - mem_io = simple_strtoul (argv[4], NULL, 16); - endianness = argv[5][0]; - local_addr = simple_strtoul (argv[6], NULL, 16); - pci_addr = simple_strtoul (argv[7], NULL, 16); - - - switch (cmd) { - case 'i': - if (tolower (endianness) == 'b') { - endianness = PX_TGT_CSR_BIG_END; - } else if (tolower (endianness) == 'l') { - endianness = PX_TGT_CSR_TRUE_LEND; - } else { - goto usage; - } - SetTargetImage (image_index, block_size, mem_io, - endianness, local_addr, pci_addr); - break; - case 'o': - if (tolower (endianness) == 'b') { - endianness = PB_SLAVE_CSR_BIG_END; - } else if (tolower (endianness) == 'l') { - endianness = PB_SLAVE_CSR_TRUE_LEND; - } else { - goto usage; - } - SetSlaveImage (image_index, block_size, mem_io, - endianness, local_addr, pci_addr); - break; - default: - goto usage; - } - - goto done; -usage: - printf ("Usage:\n%s\n", cmdtp->help); - -done: - return ret_val; -} diff --git a/board/amirix/ap1000/powerspan.h b/board/amirix/ap1000/powerspan.h deleted file mode 100644 index 4e9a8c1..0000000 --- a/board/amirix/ap1000/powerspan.h +++ /dev/null @@ -1,170 +0,0 @@ -/** - * @file powerspan.h Header file for PowerSpan II code. - */ - -/* - * (C) Copyright 2005 - * AMIRIX Systems Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef POWERSPAN_H -#define POWERSPAN_H - -#define CLEAR_MASTER_ABORT 0xdeadbeef -#define NO_DEVICE_FOUND -1 -#define ILLEGAL_REG_OFFSET -2 -#define I2C_BUSY -3 -#define I2C_ERR -4 - -#define REG_P1_CSR 0x004 -#define REGS_P1_BST 0x018 -#define REG_P1_ERR_CSR 0x150 -#define REG_P1_MISC_CSR 0x160 -#define REGS_P1_TGT_CSR 0x100 -#define REGS_P1_TGT_TADDR 0x104 -#define REGS_PB_SLAVE_CSR 0x200 -#define REGS_PB_SLAVE_TADDR 0x204 -#define REGS_PB_SLAVE_BADDR 0x208 -#define REG_CONFIG_ADDRESS 0x290 -#define REG_CONFIG_DATA 0x294 -#define REG_PB_ERR_CSR 0x2B0 -#define REG_PB_MISC_CSR 0x2C0 -#define REG_MISC_CSR 0x400 -#define REG_I2C_CSR 0x408 -#define REG_RESET_CSR 0x40C -#define REG_ISR0 0x410 -#define REG_ISR1 0x414 -#define REG_IER0 0x418 -#define REG_MBOX_MAP 0x420 -#define REG_HW_MAP 0x42C -#define REG_IDR 0x444 - -#define CSR_MEMORY_SPACE_ENABLE 0x00000002 -#define CSR_PCI_MASTER_ENABLE 0x00000004 - -#define P1_BST_OFF 0x04 - -#define PX_ERR_ERR_STATUS 0x01000000 - -#define PX_MISC_CSR_MAX_RETRY_MASK 0x00000F00 -#define PX_MISC_CSR_MAX_RETRY 0x00000F00 -#define PX_MISC_REG_BAR_ENABLE 0x00008000 -#define PB_MISC_TEA_ENABLE 0x00000010 -#define PB_MISC_MAC_TEA 0x00000040 - -#define P1_TGT_IMAGE_OFF 0x010 -#define PX_TGT_CSR_IMG_EN 0x80000000 -#define PX_TGT_CSR_TA_EN 0x40000000 -#define PX_TGT_CSR_BAR_EN 0x20000000 -#define PX_TGT_CSR_MD_EN 0x10000000 -#define PX_TGT_CSR_MODE 0x00800000 -#define PX_TGT_CSR_DEST 0x00400000 -#define PX_TGT_CSR_MEM_IO 0x00200000 -#define PX_TGT_CSR_GBL 0x00080000 -#define PX_TGT_CSR_CL 0x00040000 -#define PX_TGT_CSR_PRKEEP 0x00000080 - -#define PX_TGT_CSR_BS_MASK 0x0F000000 -#define PX_TGT_MEM_IO 0x00200000 -#define PX_TGT_CSR_RTT_MASK 0x001F0000 -#define PX_TGT_CSR_RTT_READ 0x000A0000 -#define PX_TGT_CSR_WTT_MASK 0x00001F00 -#define PX_TGT_CSR_WTT_WFLUSH 0x00000200 -#define PX_TGT_CSR_END_MASK 0x00000060 -#define PX_TGT_CSR_BIG_END 0x00000040 -#define PX_TGT_CSR_TRUE_LEND 0x00000060 -#define PX_TGT_CSR_RDAMT_MASK 0x00000007 - -#define PX_TGT_CSR_BS_64MB 0xa -#define PX_TGT_CSR_BS_16MB 0x8 - -#define PX_TGT_USE_MEM_IO 1 -#define PX_TGT_NOT_MEM_IO 0 - -#define PB_SLAVE_IMAGE_OFF 0x010 -#define PB_SLAVE_CSR_IMG_EN 0x80000000 -#define PB_SLAVE_CSR_TA_EN 0x40000000 -#define PB_SLAVE_CSR_MD_EN 0x20000000 -#define PB_SLAVE_CSR_MODE 0x00800000 -#define PB_SLAVE_CSR_DEST 0x00400000 -#define PB_SLAVE_CSR_MEM_IO 0x00200000 -#define PB_SLAVE_CSR_PRKEEP 0x00000080 - -#define PB_SLAVE_CSR_BS_MASK 0x1F000000 -#define PB_SLAVE_CSR_END_MASK 0x00000060 -#define PB_SLAVE_CSR_BIG_END 0x00000040 -#define PB_SLAVE_CSR_TRUE_LEND 0x00000060 -#define PB_SLAVE_CSR_RDAMT_MASK 0x00000007 - -#define PB_SLAVE_USE_MEM_IO 1 -#define PB_SLAVE_NOT_MEM_IO 0 - - -#define MISC_CSR_PCI1_LOCK 0x00000080 - -#define I2C_CSR_ADDR 0xFF000000 /* Specifies I2C Device Address to be Accessed */ -#define I2C_CSR_DATA 0x00FF0000 /* Specifies the Required Data for a Write */ -#define I2C_CSR_DEV_CODE 0x0000F000 /* Device Select. I2C 4-bit Device Code */ -#define I2C_CSR_CS 0x00000E00 /* Chip Select */ -#define I2C_CSR_RW 0x00000100 /* Read/Write */ -#define I2C_CSR_ACT 0x00000080 /* I2C Interface Active */ -#define I2C_CSR_ERR 0x00000040 /* Error */ - -#define I2C_EEPROM_DEV 0xa -#define I2C_EEPROM_CHIP_SEL 0 - -#define I2C_READ 0 -#define I2C_WRITE 1 - -#define RESET_CSR_EEPROM_LOAD 0x00000010 - -#define ISR_CLEAR_ALL 0xFFFFFFFF - -#define IER0_DMA_INTS_EN 0x0F000000 -#define IER0_PCI_1_EN 0x00400000 -#define IER0_HW_INTS_EN 0x003F0000 -#define IER0_MB_INTS_EN 0x000000FF -#define IER0_DEFAULT (IER0_DMA_INTS_EN | IER0_PCI_1_EN | IER0_HW_INTS_EN | IER0_MB_INTS_EN) - -#define MBOX_MAP_TO_INT4 0xCCCCCCCC - -#define HW_MAP_HW4_TO_INT4 0x000C0000 - -#define IDR_PCI_A_OUT 0x40000000 -#define IDR_MBOX_OUT 0x10000000 - - -int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val); -int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val); -int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val); -int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val); -int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val); -int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val); - -unsigned int PowerSpanRead(unsigned int theOffset); -void PowerSpanWrite(unsigned int theOffset, unsigned int theValue); - -int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag); - -int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val); -int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val); - -int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr); -int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr); - -#endif diff --git a/board/amirix/ap1000/serial.c b/board/amirix/ap1000/serial.c deleted file mode 100644 index 39c4157..0000000 --- a/board/amirix/ap1000/serial.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * (C) Copyright 2002 - * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include - -#include - -#if 0 -#include "serial.h" -#endif - -const NS16550_t COM_PORTS[] = - { (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 }; - -#undef CFG_DUART_CHAN -#define CFG_DUART_CHAN gComPort -static int gComPort = 0; - -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; - - (void) NS16550_init (COM_PORTS[0], clock_divisor); - gComPort = 0; - - return 0; -} - -void serial_putc (const char c) -{ - if (c == '\n') { - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r'); - } - - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c); -} - -int serial_getc (void) -{ - return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]); -} - -int serial_tstc (void) -{ - return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]); -} - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CFG_INIT_CHAN1 - NS16550_reinit (COM_PORTS[0], clock_divisor); -#endif -#ifdef CFG_INIT_CHAN2 - NS16550_reinit (COM_PORTS[1], clock_divisor); -#endif -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -void kgdb_serial_init (void) -{ -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif /* CFG_CMD_KGDB */ diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds deleted file mode 100644 index 109e7fe..0000000 --- a/board/amirix/ap1000/u-boot.lds +++ /dev/null @@ -1,145 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/amirix/ap1000/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/armadillo/Makefile b/board/armadillo/Makefile deleted file mode 100644 index 52ea7f2..0000000 --- a/board/armadillo/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := armadillo.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/armadillo/armadillo.c b/board/armadillo/armadillo.c deleted file mode 100644 index de04c66..0000000 --- a/board/armadillo/armadillo.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2005 Rowel Atienza - * Armadillo board HT1070 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Activate LED flasher */ - IO_LEDFLSH = 0x40; - - /* arch number MACH_TYPE_ARMADILLO - not official*/ - gd->bd->bi_arch_number = 83; - - /* location of boot parameters */ - gd->bd->bi_boot_params = 0xc0000100; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} diff --git a/board/armadillo/config.mk b/board/armadillo/config.mk deleted file mode 100644 index 23c432f..0000000 --- a/board/armadillo/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -#address where u-boot will be relocated -TEXT_BASE = 0xc0f80000 diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c deleted file mode 100644 index 037a643..0000000 --- a/board/armadillo/flash.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2005 Rowel Atienza - * Flash driver for armadillo board HT1070 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define FLASH_BANK_SIZE 0x400000 - -/*value used by hermit is 0x200*/ -/*document says sector size is either 64k in low mem reg and 8k in high mem reg*/ -#define MAIN_SECT_SIZE 0x10000 - -#define UNALIGNED_MASK (3) -#define FL_WORD(addr) (*(volatile unsigned short*)(addr)) -#define FLASH_TIMEOUT 20000000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = (FUJ_MANUFACT & FLASH_VENDMASK); - /*(INTEL_ID_28F128J3 & FLASH_TYPEMASK); */ - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (FUJ_MANUFACT & FLASH_VENDMASK): - printf ("Fujitsu: "); - break; - default: - printf ("Unknown Vendor "); - break; - } -/* - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf ("28F128J3 (128Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } -*/ - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -/* -Done: ; -*/ -} - -/* - * * Loop until both write state machines complete. - * */ -static unsigned short flash_status_wait (unsigned long addr, - unsigned short value) -{ - unsigned short status; - long timeout = FLASH_TIMEOUT; - - while (((status = (FL_WORD (addr))) != value) && timeout > 0) { - timeout--; - } - return status; -} - -/* - * Loop until the Write State machine is ready, then do a full error - * check. Clear status and leave the flash in Read Array mode; return - * 0 for no error, -1 for error. - */ -static int flash_status_full_check (unsigned long addr, unsigned short value1, - unsigned short value2) -{ - unsigned short status1, status2; - - status1 = flash_status_wait (addr, value1); - status2 = flash_status_wait (addr + 2, value2); - return (status1 != value1 || status2 != value2) ? -1 : 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - unsigned long base; - unsigned long addr; - - if ((info->flash_id & FLASH_VENDMASK) != - (FUJ_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - printf ("Erasing %d sectors starting at sector %2d.\n" - "This make take some time ... ", - s_last - s_first, sect); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - /* ARM simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - - addr = sect * MAIN_SECT_SIZE; - addr &= ~(unsigned long) UNALIGNED_MASK; /* word align */ - base = addr & 0xF0000000; - - FL_WORD (base + (0x555 << 1)) = 0xAA; - FL_WORD (base + (0x2AA << 1)) = 0x55; - FL_WORD (base + (0x555 << 1)) = 0x80; - FL_WORD (base + (0x555 << 1)) = 0xAA; - FL_WORD (base + (0x2AA << 1)) = 0x55; - FL_WORD (addr) = 0x30; - if (flash_status_full_check (addr, 0xFFFF, 0xFFFF)) - return ERR_PROTECTED; - } - } - printf ("\nDone.\n"); - if (ctrlc ()) - printf ("User Interrupt!\n"); - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (flag) - enable_interrupts (); - - return rc; -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ushort data) -{ - int flag; - unsigned long base; - - /* Check if Flash is (sufficiently) erased - */ - if ((FL_WORD (dest) & data) != data) - return ERR_NOT_ERASED; - - /*if(dest & UNALIGNED_MASK) return ERR_ALIGN; */ - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - base = dest & 0xF0000000; - FL_WORD (base + (0x555 << 1)) = 0xAA; - FL_WORD (base + (0x2AA << 1)) = 0x55; - FL_WORD (base + (0x555 << 1)) = 0xA0; - FL_WORD (dest) = data; - /*printf("writing 0x%p = 0x%x\n",dest,data); */ - if (flash_status_wait (dest, data) != data) - return ERR_PROG_ERROR; - - if (flag) - enable_interrupts (); - - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - printf ("Writing %d short data to 0x%p from 0x%p.\n ", cnt, wp, src); - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - printf ("\nDone.\n"); - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word (info, wp, data); -} diff --git a/board/armadillo/lowlevel_init.S b/board/armadillo/lowlevel_init.S deleted file mode 100644 index 6cf6426..0000000 --- a/board/armadillo/lowlevel_init.S +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Initialization stuff - taken from hermit - * (C) Copyright 2005 Rowel Atienza - * Armadillo board HT1070 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* some parameters for the board */ -/* setting up the memory */ -#define SRAM_START 0x60000000 -#define SRAM_SIZE 0x0000c000 - -.globl lowlevel_init -lowlevel_init: - mov r0, #0x70 /* 32-bit code + data, MMU mandatory */ - mcr p15, 0, r0, c1, c0, 0 /* MMU init */ - - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - mov r0, #0x80000000 /* I/O base */ - - mov r1, #0x6 /* CLKCTL_73 in SYSCON3 */ - add r2, r0, #0x2200 /* address of SYSCON3 in r2 */ - str r1, [r2] /* set clock speed to 73.728 MHz */ - - mov r1, #0x81 /* 64KHz DRAM refresh period */ - str r1, [r0, #0x200] /* set DRFPR */ - - mov r1, #0x500 /* permanent enable, 16bits wide */ - add r1, r1, #0x42 /* 128Mbit, CAS lat = 2 SDRAM */ - add r2, r0, #0x2300 /* load address in r2 */ - str r1, [r2] - - mov r1, #0x100 /* SDRAM refresh rate */ - add r2, r0, #0x2340 /* load address in r2 */ - str r1, [r2] - - mov sp, #SRAM_START /* init stack pointer */ - add sp, sp, #SRAM_SIZE - - /* everything is fine now */ - mov pc, lr diff --git a/board/armadillo/u-boot.lds b/board/armadillo/u-boot.lds deleted file mode 100644 index 64d946c..0000000 --- a/board/armadillo/u-boot.lds +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm720t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/assabet/Makefile b/board/assabet/Makefile deleted file mode 100644 index c49f1b4..0000000 --- a/board/assabet/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# 2004 (c) MontaVista Software, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := assabet.o -SOBJS := setup.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/assabet/assabet.c b/board/assabet/assabet.c deleted file mode 100644 index d3ccbb5..0000000 --- a/board/assabet/assabet.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * 2004 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -/* - * Board dependent initialisation - */ - -#define ECOR 0x8000 -#define ECOR_RESET 0x80 -#define ECOR_LEVEL_IRQ 0x40 -#define ECOR_WR_ATTRIB 0x04 -#define ECOR_ENABLE 0x01 - -#define ECSR 0x8002 -#define ECSR_IOIS8 0x20 -#define ECSR_PWRDWN 0x04 -#define ECSR_INT 0x02 -#define SMC_IO_SHIFT 2 -#define NCR_0 (*((volatile u_char *)(0x100000a0))) -#define NCR_ENET_OSC_EN (1<<3) - -static inline u8 -readb(volatile u8 * p) -{ - return *p; -} - -static inline void -writeb(u8 v, volatile u8 * p) -{ - *p = v; -} - -static void -smc_init(void) -{ - u8 ecor; - u8 ecsr; - volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25)); - - NCR_0 |= NCR_ENET_OSC_EN; - udelay(100); - - ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; - writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); - udelay(100); - - /* - * The device will ignore all writes to the enable bit while - * reset is asserted, even if the reset bit is cleared in the - * same write. Must clear reset first, then enable the device. - */ - writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); - writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); - - /* - * Set the appropriate byte/word mode. - */ - ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; - ecsr |= ECSR_IOIS8; - writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); - udelay(100); -} - -static void -neponset_init(void) -{ - smc_init(); -} - -int -board_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_arch_number = MACH_TYPE_ASSABET; - gd->bd->bi_boot_params = 0xc0000100; - - neponset_init(); - - return 0; -} - -int -dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} diff --git a/board/assabet/config.mk b/board/assabet/config.mk deleted file mode 100644 index 74cb419..0000000 --- a/board/assabet/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# -# SA-1110 based Intel Assabet board -# -# The Intel Assabet 1 bank of 32 MiB SDRAM -# - -TEXT_BASE = 0xc1f00000 diff --git a/board/assabet/setup.S b/board/assabet/setup.S deleted file mode 100644 index 56ea0dd..0000000 --- a/board/assabet/setup.S +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * 2004 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include "config.h" -#include "version.h" - - -/*----------------------------------------------------------------------- - * Board defines: - */ - -#define MDCNFG 0x00 -#define MDCAS00 0x04 -#define MDCAS01 0x08 -#define MDCAS02 0x0C -#define MSC0 0x10 -#define MSC1 0x14 -#define MECR 0x18 -#define MDREFR 0x1C -#define MDCAS20 0x20 -#define MDCAS21 0x24 -#define MDCAS22 0x28 -#define MSC2 0x2C -#define SMCNFG 0x30 - -#define ASSABET_BCR (0x12000000) -#define ASSABET_BCR_DB1110 (0x00a07490 | (0<<16) | (0<<17)) -#define ASSABET_SCR_nNEPONSET (1 << 9) -#define NEPONSET_LEDS (0x10000010) - - -/*----------------------------------------------------------------------- - * Setup parameters for the board: - */ - - -MEM_BASE: .long 0xa0000000 -MEM_START: .long 0xc0000000 - -mdcnfg: .long 0x72547254 -mdcas00: .long 0xaaaaaa7f -mdcas01: .long 0xaaaaaaaa -mdcas02: .long 0xaaaaaaaa -msc0: .long 0x4b384370 -msc1: .long 0x22212419 -mecr: .long 0x994a994a -mdrefr: .long 0x04340327 -mdcas20: .long 0xaaaaaa7f -mdcas21: .long 0xaaaaaaaa -mdcas22: .long 0xaaaaaaaa -msc2: .long 0x42196669 -smcnfg: .long 0x00000000 - -BCR: .long ASSABET_BCR -BCR_DB1110: .long ASSABET_BCR_DB1110 -LEDS: .long NEPONSET_LEDS - - - .globl lowlevel_init -lowlevel_init: - - /* Setting up the memory and stuff */ - - ldr r0, MEM_BASE - ldr r1, mdcas00 - str r1, [r0, #MDCAS00] - ldr r1, mdcas01 - str r1, [r0, #MDCAS01] - ldr r1, mdcas02 - str r1, [r0, #MDCAS02] - ldr r1, mdcas20 - str r1, [r0, #MDCAS20] - ldr r1, mdcas21 - str r1, [r0, #MDCAS21] - ldr r1, mdcas22 - str r1, [r0, #MDCAS22] - ldr r1, mdrefr - str r1, [r0, #MDREFR] - ldr r1, mecr - str r1, [r0, #MECR] - ldr r1, msc0 - str r1, [r0, #MSC0] - ldr r1, msc1 - str r1, [r0, #MSC1] - ldr r1, msc2 - str r1, [r0, #MSC2] - ldr r1, smcnfg - str r1, [r0, #SMCNFG] - - ldr r1, mdcnfg - str r1, [r0, #MDCNFG] - - /* Load something to activate bank */ - ldr r2, MEM_START -.rept 8 - ldr r3, [r2] -.endr - - /* Enable SDRAM */ - orr r1, r1, #0x00000001 - str r1, [r0, #MDCNFG] - - ldr r1, BCR - ldr r2, BCR_DB1110 - str r2, [r1] - - ldr r1, LEDS - mov r0, #0x3 - str r0, [r1] - - /* All done... */ - mov pc, lr diff --git a/board/assabet/u-boot.lds b/board/assabet/u-boot.lds deleted file mode 100644 index 7a3a9b8..0000000 --- a/board/assabet/u-boot.lds +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * 2004 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/sa1100/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/at91rm9200dk/Makefile b/board/at91rm9200dk/Makefile deleted file mode 100644 index ec77da9..0000000 --- a/board/at91rm9200dk/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := at91rm9200dk.o at45.o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/at91rm9200dk/at45.c b/board/at91rm9200dk/at45.c deleted file mode 100644 index 3c00132..0000000 --- a/board/at91rm9200dk/at45.c +++ /dev/null @@ -1,621 +0,0 @@ -/* Driver for ATMEL DataFlash support - * Author : Hamid Ikdoumi (Atmel) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -#ifdef CONFIG_HAS_DATAFLASH -#include - -#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to -the Continuous Array Read function */ - -/* AC Characteristics */ -/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -#define AT91C_TIMEOUT_WRDY 200000 -#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ -#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ - -void AT91F_SpiInit(void) { - -/*-------------------------------------------------------------------*/ -/* SPI DataFlash Init */ -/*-------------------------------------------------------------------*/ - /* Configure PIOs */ - AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - /* Enable CLock */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; - - /* Reset the SPI */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; - - /* Configure SPI in Master Mode with No CS selected !!! */ - AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; - - /* Configure CS0 and CS3 */ - *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - - *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - -} - -void AT91F_SpiEnable(int cs) { - switch(cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); - break; - case 3: /* Configure SPI CS3 for Serial DataFlash Card */ - /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ - AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ - /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; - /* Configure PCS */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - } - - /* SPI_Enable */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; -} - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiWrite */ -/* \brief Set the PDC registers for a transfert */ -/*----------------------------------------------------------------------------*/ -unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) -{ - unsigned int timeout; - - pDesc->state = BUSY; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - /* Initialize the Transmit and Receive Pointer */ - AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; - AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; - - /* Intialize the Transmit and Receive Counters */ - AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; - AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; - - if ( pDesc->tx_data_size != 0 ) { - /* Initialize the Next Transmit and Next Receive Pointer */ - AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; - AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; - - /* Intialize the Next Transmit and Next Receive Counters */ - AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; - AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; - } - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - timeout = 0; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; - while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - pDesc->state = IDLE; - - if (timeout >= CFG_SPI_WRITE_TOUT){ - printf("Error Timeout\n\r"); - return DATAFLASH_ERROR; - } - - return DATAFLASH_OK; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashSendCommand */ -/* \brief Generic function to send a command to the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashSendCommand( - AT91PS_DataFlash pDataFlash, - unsigned char OpCode, - unsigned int CmdSize, - unsigned int DataflashAddress) -{ - unsigned int adr; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* process the address to obtain page address and byte address */ - adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); - - /* fill the command buffer */ - pDataFlash->pDataFlashDesc->command[0] = OpCode; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); - } else { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - } - pDataFlash->pDataFlashDesc->command[5] = 0; - pDataFlash->pDataFlashDesc->command[6] = 0; - pDataFlash->pDataFlashDesc->command[7] = 0; - - /* Initialize the SpiData structure for the spi write fuction */ - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; - - /* send the command and read the data */ - return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashGetStatus */ -/* \brief Read the status register of the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) -{ - AT91S_DataFlashStatus status; - - /* if a transfert is in progress ==> return 0 */ - if( (pDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* first send the read status command (D7H) */ - pDesc->command[0] = DB_STATUS; - pDesc->command[1] = 0; - - pDesc->DataFlash_state = GET_STATUS; - pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ - pDesc->tx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_size = 2 ; - pDesc->tx_cmd_size = 2 ; - status = AT91F_SpiWrite (pDesc); - - pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); - - return status; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashWaitReady */ -/* \brief wait for dataflash ready (bit7 of the status register == 1) */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) -{ - pDataFlashDesc->DataFlash_state = IDLE; - - do { - AT91F_DataFlashGetStatus(pDataFlashDesc); - timeout--; - } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); - - if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) - return DATAFLASH_ERROR; - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashContinuousRead */ -/* Object : Continuous stream Read */ -/* Input Parameters : DataFlash Service */ -/* : = dataflash address */ -/* : <*dataBuffer> = data buffer pointer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( - AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead ) -{ - AT91S_DataFlashStatus status; - /* Test the size to read in the device */ - if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - - status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); - /* Send the command to the dataflash */ - return(status); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashPagePgmBuf */ -/* Object : Main memory page program through buffer 1 or buffer 2 */ -/* Input Parameters : DataFlash Service */ -/* : <*src> = Source buffer */ -/* : = dataflash destination address */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int SizeToWrite) -{ - int cmdsize; - pDataFlash->pDataFlashDesc->tx_data_pt = src ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->rx_data_pt = src; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; - - cmdsize = 4; - /* Send the command to the dataflash */ - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_MainMemoryToBufferTransfert */ -/* Object : Read a page in the SRAM Buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*----------------------------------------------------------------------------- */ -/* Function Name : AT91F_DataFlashWriteBuffer */ -/* Object : Write data to the internal sram buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : = command to write buffer1 or buffer2 */ -/* : <*dataBuffer> = data buffer to write */ -/* : = address in the internal buffer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite ) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) - return DATAFLASH_BAD_COMMAND; - - /* buffer address must be lower than page size */ - if (bufferAddress > pDataFlash->pDevice->pages_size) - return DATAFLASH_BAD_ADDRESS; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* Send first Write Command */ - pDataFlash->pDataFlashDesc->command[0] = BufferCommand; - pDataFlash->pDataFlashDesc->command[1] = 0; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[2] = 0; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - cmdsize = 5; - } else { - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - cmdsize = 4; - } - - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - - return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PageErase */ -/* Object : Erase a page */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PageErase( - AT91PS_DataFlash pDataFlash, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_BlockErase */ -/* Object : Erase a Block */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_BlockErase( - AT91PS_DataFlash pDataFlash, - unsigned int block) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_WriteBufferToMain */ -/* Object : Write buffer to the main memory */ -/* Input Parameters : DataFlash Service */ -/* : = command to send to buffer1 or buffer2 */ -/* : = main memory address */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_WriteBufferToMain ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest ) -{ - int cmdsize; - /* Test if the buffer command is correct */ - if ((BufferCommand != DB_BUF1_PAGE_PGM) && - (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && - (BufferCommand != DB_BUF2_PAGE_PGM) && - (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - /* Send the command to the dataflash */ - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PartialPageWrite */ -/* Object : Erase partielly a page */ -/* Input Parameters : = page number */ -/* : = adr to begin the fading */ -/* : = Number of bytes to erase */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PartialPageWrite ( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size) -{ - unsigned int page; - unsigned int AdrInPage; - - page = dest / (pDataFlash->pDevice->pages_size); - AdrInPage = dest % (pDataFlash->pDevice->pages_size); - - /* Read the contents of the page in the Sram Buffer */ - AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - /*Update the SRAM buffer */ - AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Erase page if a 128 Mbits device */ - if (pDataFlash->pDevice->pages_number >= 16384) { - AT91F_PageErase(pDataFlash, page); - /* Rewrite the modified Sram Buffer in the main memory */ - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - - /* Rewrite the modified Sram Buffer in the main memory */ - return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashWrite */ -/* Object : */ -/* Input Parameters : <*src> = Source buffer */ -/* : = dataflash adress */ -/* : = data buffer size */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWrite( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ) -{ - unsigned int length; - unsigned int page; - unsigned int status; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - /* If destination does not fit a page start address */ - if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { - length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); - - if (size < length) - length = size; - - if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= length; - dest += length; - src += length; - } - - while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { - /* program dataflash page */ - page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); - - status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - if (!status) - return DATAFLASH_ERROR; - - status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); - if(!status) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= pDataFlash->pDevice->pages_size ; - dest += pDataFlash->pDevice->pages_size ; - src += pDataFlash->pDevice->pages_size ; - } - - /* If still some bytes to read */ - if ( size > 0 ) { - /* program dataflash page */ - if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashRead */ -/* Object : Read a block in dataflash */ -/* Input Parameters : */ -/* Return value : */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataFlashRead( - AT91PS_DataFlash pDataFlash, - unsigned long addr, - unsigned long size, - char *buffer) -{ - unsigned long SizeToRead; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - while (size) { - SizeToRead = (size < 0x8000)? size:0x8000; - - if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) - return -1; - - size -= SizeToRead; - addr += SizeToRead; - buffer += SizeToRead; - } - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataflashProbe */ -/* Object : */ -/* Input Parameters : */ -/* Return value : Dataflash status register */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) -{ - AT91F_SpiEnable(cs); - AT91F_DataFlashGetStatus(pDesc); - return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); -} - -#endif diff --git a/board/at91rm9200dk/at91rm9200dk.c b/board/at91rm9200dk/at91rm9200dk.c deleted file mode 100644 index 77caed3..0000000 --- a/board/at91rm9200dk/at91rm9200dk.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Enable Ctrlc */ - console_init_f (); - - /* Correct IRDA resistor problem */ - /* Set PA23_TXD in Output */ - (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of AT91RM9200DK-Board */ - gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = dm9161_InitPhy; - p_phyops->IsPhyConnected = dm9161_IsPhyConnected; - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; - p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ -#endif /* CONFIG_DRIVER_ETHER */ - -/* - * Disk On Chip (NAND) Millenium initialization. - * The NAND lives in the CS2* space - */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -extern ulong nand_probe (ulong physadr); - -#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */ -void nand_init (void) -{ - /* Setup Smart Media, fitst enable the address range of CS3 */ - *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia; - /* set the bus interface characteristics based on - tDS Data Set up Time 30 - ns - tDH Data Hold Time 20 - ns - tALS ALE Set up Time 20 - ns - 16ns at 60 MHz ~= 3 */ -/*memory mapping structures */ -#define SM_ID_RWH (5 << 28) -#define SM_RWH (1 << 28) -#define SM_RWS (0 << 24) -#define SM_TDF (1 << 8) -#define SM_NWS (3) - AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS | - AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 | - SM_TDF | AT91C_SMC2_WSEN | SM_NWS); - - /* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */ - *AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | - AT91C_PC3_BFBAA_SMWE; - *AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | - AT91C_PC3_BFBAA_SMWE; - - /* Configure PC2 as input (signal READY of the SmartMedia) */ - *AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */ - *AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */ - - /* Configure PB1 as input (signal Card Detect of the SmartMedia) */ - *AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */ - *AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */ - - /* PIOB and PIOC clock enabling */ - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC; - - if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1) - printf (" No SmartMedia card inserted\n"); -#ifdef DEBUG - printf (" SmartMedia card inserted\n"); - - printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE); -#endif - printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20); -} -#endif diff --git a/board/at91rm9200dk/config.mk b/board/at91rm9200dk/config.mk deleted file mode 100644 index 9ce161e..0000000 --- a/board/at91rm9200dk/config.mk +++ /dev/null @@ -1 +0,0 @@ -TEXT_BASE = 0x21f00000 diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c deleted file mode 100644 index f6228ef..0000000 --- a/board/at91rm9200dk/flash.c +++ /dev/null @@ -1,504 +0,0 @@ -/* - * (C) Copyright 2002 - * Lineo, Inc. - * Bernhard Kuhn - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -ulong myflush(void); - - -/* Flash Organization Structure */ -typedef struct OrgDef -{ - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgAT49BV16x4[] = -{ - { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ - { 2, 32*1024 }, /* 2 * 32 kBytes sectors */ - { 30, 64*1024 }, /* 30 * 64 kBytes sectors */ -}; - -OrgDef OrgAT49BV16x4A[] = -{ - { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ - { 31, 64*1024 }, /* 31 * 64 kBytes sectors */ -}; - -OrgDef OrgAT49BV6416[] = -{ - { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ - { 127, 64*1024 }, /* 127 * 64 kBytes sectors */ -}; - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/* AT49BV1614A Codes */ -#define FLASH_CODE1 0xAA -#define FLASH_CODE2 0x55 -#define ID_IN_CODE 0x90 -#define ID_OUT_CODE 0xF0 - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 -#define CMD_SECTOR_UNLOCK 0x0070 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ -void flash_identification (flash_info_t * info) -{ - volatile u16 manuf_code, device_code, add_device_code; - - MEM_FLASH_ADDR1 = FLASH_CODE1; - MEM_FLASH_ADDR2 = FLASH_CODE2; - MEM_FLASH_ADDR1 = ID_IN_CODE; - - manuf_code = *(volatile u16 *) CFG_FLASH_BASE; - device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2); - add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1)); - - MEM_FLASH_ADDR1 = FLASH_CODE1; - MEM_FLASH_ADDR2 = FLASH_CODE2; - MEM_FLASH_ADDR1 = ID_OUT_CODE; - - /* Vendor type */ - info->flash_id = ATM_MANUFACT & FLASH_VENDMASK; - printf ("Atmel: "); - - if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) { - - if ((add_device_code & FLASH_TYPEMASK) == - (ATM_ID_BV1614A & FLASH_TYPEMASK)) { - info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK; - printf ("AT49BV1614A (16Mbit)\n"); - } else { /* AT49BV1614 Flash */ - info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK; - printf ("AT49BV1614 (16Mbit)\n"); - } - - } else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) { - info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK; - printf ("AT49BV6416 (64Mbit)\n"); - } -} - -ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks) -{ - int i, nb_sectors = 0; - - for (i=0; istart[sector]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - *addr = CMD_SECTOR_UNLOCK; -} - - -ulong flash_init (void) -{ - int i, j, k; - unsigned int flash_nb_blocks, sector; - unsigned int start_address; - OrgDef *pOrgDef; - - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_identification (&flash_info[i]); - - if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV1614 & FLASH_TYPEMASK)) { - - pOrgDef = OrgAT49BV16x4; - flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef); - } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV1614A & FLASH_TYPEMASK)){ /* AT49BV1614A Flash */ - - pOrgDef = OrgAT49BV16x4A; - flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef); - } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ - - pOrgDef = OrgAT49BV6416; - flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef); - } else { - flash_nb_blocks = 0; - pOrgDef = OrgAT49BV16x4; - } - - flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks); - memset (flash_info[i].protect, 0, flash_info[i].sector_count); - - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - - sector = 0; - start_address = flashbase; - flash_info[i].size = 0; - - for (j = 0; j < flash_nb_blocks; j++) { - for (k = 0; k < pOrgDef[j].sector_number; k++) { - flash_info[i].start[sector++] = start_address; - start_address += pOrgDef[j].sector_size; - flash_info[i].size += pOrgDef[j].sector_size; - } - } - - size += flash_info[i].size; - - if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ - - /* Unlock all sectors at reset */ - for (j=0; jflash_id & FLASH_VENDMASK) { - case (ATM_MANUFACT & FLASH_VENDMASK): - printf ("Atmel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (ATM_ID_BV1614 & FLASH_TYPEMASK): - printf ("AT49BV1614 (16Mbit)\n"); - break; - case (ATM_ID_BV1614A & FLASH_TYPEMASK): - printf ("AT49BV1614A (16Mbit)\n"); - break; - case (ATM_ID_BV6416 & FLASH_TYPEMASK): - printf ("AT49BV6416 (64Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - return; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (ATM_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - }; - - if ((int) src & 1) { - printf ("unaligned source not supported\n"); - return ERR_ALIGN; - }; - - wp = addr; - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << - 8); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - }; - - return ERR_OK; -} diff --git a/board/at91rm9200dk/u-boot.lds b/board/at91rm9200dk/u-boot.lds deleted file mode 100644 index f4fbf96..0000000 --- a/board/at91rm9200dk/u-boot.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/atc/Makefile b/board/atc/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/atc/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/atc/atc.c b/board/atc/atc.c deleted file mode 100644 index d2c6b3b..0000000 --- a/board/atc/atc.c +++ /dev/null @@ -1,399 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ - /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ - /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ - /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ - /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ - /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ -#if 1 - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ -#else - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ -#endif - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ - /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ - /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ -#if 0 - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ -#else - /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* PC15 */ -#endif - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SOFT_I2C) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ -#if 0 - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ -#else - /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* PD4 */ -#endif - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ - } -}; - -/* - * UPMB initialization table - */ -#define _NOT_USED_ 0xFFFFFFFF - -static const uint rtc_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800, - 0xfaf2080, 0xfaf2080, 0xfff2400, 0x1fff6c05, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800, - 0xfaf2080, 0xfaf2080, 0xfaf2400, 0x1fbf6c05, /* last */ - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - printf ("Board: ATC\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -int misc_init_r(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint)); - memctl->memc_mamr = MxMR_RLFx_6X | MxMR_WLFx_6X | MxMR_OP_NORM; - - return (0); -} - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CFG_RAMBOOT - ulong size8, size9; -#endif - long psize; - - psize = 8 * 1024 * 1024; - - memctl->memc_mptpr = CFG_MPTPR; - memctl->memc_psrt = CFG_PSRT; - -#ifndef CFG_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, - (uchar *) CFG_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - printf ("(60x:8COL) "); - } - -#endif /* CFG_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -extern void doc_probe (ulong physadr); -void doc_init (void) -{ - doc_probe (CFG_DOC_BASE); -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif diff --git a/board/atc/config.mk b/board/atc/config.mk deleted file mode 100644 index eee7a60..0000000 --- a/board/atc/config.mk +++ /dev/null @@ -1,38 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# ATC boards -# - -# This should be equal to the CFG_FLASH_BASE define in config_atc.h -# for the "final" configuration, with U-Boot in flash, or the address -# in RAM where U-Boot is loaded at for debugging. -# - -TEXT_BASE := 0xFF000000 - -# RAM version -#TEXT_BASE := 0x100000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/atc/flash.c b/board/atc/flash.c deleted file mode 100644 index 2ab60e8..0000000 --- a/board/atc/flash.c +++ /dev/null @@ -1,663 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { -#if 0 - ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; -#else - ulong flashbase = CFG_FLASH_BASE; -#endif - - memset(&flash_info[i], 0, sizeof(flash_info_t)); - - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", - i, flash_info[i].size); - } - - size += flash_info[i].size; - } - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base < info->start[0] + info->size) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} diff --git a/board/atc/u-boot.lds b/board/atc/u-boot.lds deleted file mode 100644 index eee83d0..0000000 --- a/board/atc/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - common/environment.o(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/barco/Makefile b/board/barco/Makefile deleted file mode 100644 index d6bbf2f..0000000 --- a/board/barco/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/barco/README b/board/barco/README deleted file mode 100644 index d255a3d..0000000 --- a/board/barco/README +++ /dev/null @@ -1,11 +0,0 @@ -This port of U-Boot is tuned to run on a range of Barco Control Rooms -Streaming Video Solutions, including: - - - Streaming Video Card (SVC) - - Sample Compress Network (SCN) - -For more information, see http://www.barcocontrolrooms.com/ - -Code and configuration are originally based on the Sandpoint board - -Marc Leeman diff --git a/board/barco/barco.c b/board/barco/barco.c deleted file mode 100644 index becbd0a..0000000 --- a/board/barco/barco.c +++ /dev/null @@ -1,363 +0,0 @@ -/******************************************************************** - * - * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms - * - * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco.c,v $ - * $Revision: 1.4 $ - * $Author: mleeman $ - * $Date: 2005/03/02 16:40:20 $ - * - * Last ChangeLog Entry - * $Log: barco.c,v $ - * Revision 1.4 2005/03/02 16:40:20 mleeman - * remove empty labels (3.4 complains) - * - * Revision 1.3 2005/02/21 12:48:58 mleeman - * update of copyright years (feedback wd) - * - * Revision 1.2 2005/02/21 10:10:53 mleeman - * - split up switch statement to a function call (Linux kernel coding guidelines) - * ( feedback wd) - * - * Revision 1.1 2005/02/14 09:31:07 mleeman - * renaming of files - * - * Revision 1.1 2005/02/14 09:23:46 mleeman - * - moved 'barcohydra' directory to a more generic barco; since we will be - * supporting and adding multiple boards - * - * Revision 1.3 2005/02/10 13:57:32 mleeman - * fixed flash corruption: I should exit from the moment I find the correct value - * - * Revision 1.2 2005/02/09 12:56:23 mleeman - * add generic header to track changes in sources - * - * - *******************************************************************/ - -/* - * (C) Copyright 2004 - * Marc Leeman - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include "config.h" -#include "barco_svc.h" - -#define TRY_WORKING (3) -#define BOOT_DEFAULT (2) -#define BOOT_WORKING (1) - -int checkboard (void) -{ - /*TODO: Check processor type */ - - puts ( "Board: Streaming Video Card for Hydra systems " -#ifdef CONFIG_MPC8240 - "8240" -#endif -#ifdef CONFIG_MPC8245 - "8245" -#endif - " Unity ##Test not implemented yet##\n"); - return 0; -} - -long int initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size (CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg (MEAR1); - emear1 = mpc824x_mpc107_getreg (EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg (MEAR1, mear1); - mpc824x_mpc107_setreg (EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_barcohydra_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_barcohydra_config_table, -#endif -}; - -void pci_init_board (void) -{ - pci_mpc824x_init (&hose); -} - -int write_flash (char *addr, char value) -{ - char *adr = (char *)0xFF800000; - int cnt = 0; - char status,oldstatus; - - *(adr+0x55) = 0xAA; udelay (1); - *(adr+0xAA) = 0x55; udelay (1); - *(adr+0x55) = 0xA0; udelay (1); - *addr = value; - - status = *addr; - do { - oldstatus = status; - status = *addr; - - if ((oldstatus & 0x40) == (status & 0x40)) { - return 4; - } - cnt++; - if (cnt > 10000) { - return 2; - } - } while ( (status & 0x20) == 0 ); - - oldstatus = *addr; - status = *addr; - - if ((oldstatus & 0x40) == (status & 0x40)) { - return 0; - } else { - *(adr+0x55) = 0xF0; - return 1; - } -} - -unsigned update_flash (unsigned char *buf) -{ - switch ((*buf) & 0x3) { - case TRY_WORKING: - printf ("found 3 and converted it to 2\n"); - write_flash ((char *)buf, (*buf) & 0xFE); - *((unsigned char *)0xFF800000) = 0xF0; - udelay (100); - printf ("buf [%#010x] %#010x\n", buf, (*buf)); - /* XXX - fall through??? */ - case BOOT_WORKING : - return BOOT_WORKING; - } - return BOOT_DEFAULT; -} - -unsigned scan_flash (void) -{ - char section[] = "kernel"; - int cfgFileLen = (CFG_FLASH_ERASE_SECTOR_LENGTH >> 1); - int sectionPtr = 0; - int foundItem = 0; /* 0: None, 1: section found, 2: "=" found */ - int bufPtr; - unsigned char *buf; - - buf = (unsigned char*)(CFG_FLASH_RANGE_BASE + CFG_FLASH_RANGE_SIZE \ - - CFG_FLASH_ERASE_SECTOR_LENGTH); - for (bufPtr = 0; bufPtr < cfgFileLen; ++bufPtr) { - if ((buf[bufPtr]==0xFF) && (*(int*)(buf+bufPtr)==0xFFFFFFFF)) { - return BOOT_DEFAULT; - } - /* This is the scanning loop, we try to find a particular - * quoted value - */ - switch (foundItem) { - case 0: - if ((section[sectionPtr] == 0)) { - ++foundItem; - } else if (buf[bufPtr] == section[sectionPtr]) { - ++sectionPtr; - } else { - sectionPtr = 0; - } - break; - case 1: - ++foundItem; - break; - case 2: - ++foundItem; - break; - case 3: - default: - return update_flash (&buf[bufPtr - 1]); - } - } - - printf ("Failed to read %s\n",section); - return BOOT_DEFAULT; -} - -TSBootInfo* find_boot_info (void) -{ - unsigned bootimage = scan_flash (); - TSBootInfo* info = (TSBootInfo*)malloc (sizeof(TSBootInfo)); - - switch (bootimage) { - case TRY_WORKING: - info->address = CFG_WORKING_KERNEL_ADDRESS; - break; - case BOOT_WORKING : - info->address = CFG_WORKING_KERNEL_ADDRESS; - break; - case BOOT_DEFAULT: - default: - info->address= CFG_DEFAULT_KERNEL_ADDRESS; - - } - info->size = *((unsigned int *)(info->address )); - - return info; -} - -void barcobcd_boot (void) -{ - TSBootInfo* start; - char *bootm_args[2]; - char *buf; - int cnt; - extern int do_bootm (cmd_tbl_t *, int, int, char *[]); - - buf = (char *)(0x00800000); - /* make certain there are enough chars to print the command line here! - */ - bootm_args[0] = (char *)malloc (16*sizeof(char)); - bootm_args[1] = (char *)malloc (16*sizeof(char)); - - start = find_boot_info (); - - printf ("Booting kernel at address %#10x with size %#10x\n", - start->address, start->size); - - /* give length of the kernel image to bootm */ - sprintf (bootm_args[0],"%x",start->size); - /* give address of the kernel image to bootm */ - sprintf (bootm_args[1],"%x",buf); - - printf ("flash address: %#10x\n",start->address+8); - printf ("buf address: %#10x\n",buf); - - /* aha, we reserve 8 bytes here... */ - for (cnt = 0; cnt < start->size ; cnt++) { - buf[cnt] = ((char *)start->address)[cnt+8]; - } - - /* initialise RAM memory */ - *((unsigned int *)0xFEC00000) = 0x00141A98; - do_bootm (NULL,0,2,bootm_args); -} - -int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ -#if 0 - if (argc > 1) { - printf ("Usage:\n (%d) %s\n", argc, cmdtp->usage); - return 1; - } -#endif - barcobcd_boot (); - - return 0; -} - -/* Currently, boot_working and boot_default are the same command. This is - * left in here to see what we'll do in the future */ - -U_BOOT_CMD ( - try_working, 1, 1, barcobcd_boot_image, - " try_working - check flash value and boot the appropriate image\n", - "\n" - ); - -U_BOOT_CMD ( - boot_working, 1, 1, barcobcd_boot_image, - " boot_working - check flash value and boot the appropriate image\n", - "\n" - ); - -U_BOOT_CMD ( - boot_default, 1, 1, barcobcd_boot_image, - " boot_default - check flash value and boot the appropriate image\n", - "\n" - ); -/* - * We are not using serial communication, so just provide empty functions - */ -int serial_init (void) -{ - return 0; -} -void serial_setbrg (void) -{ - return; -} -void serial_putc (const char c) -{ - return; -} -void serial_puts (const char *c) -{ - return; -} -void serial_addr (unsigned int i) -{ - return; -} -int serial_getc (void) -{ - return 0; -} -int serial_tstc (void) -{ - return 0; -} - -unsigned long post_word_load (void) -{ - return 0l; -} -void post_word_store (unsigned long val) -{ - return; -} diff --git a/board/barco/barco_svc.h b/board/barco/barco_svc.h deleted file mode 100644 index 088f61e..0000000 --- a/board/barco/barco_svc.h +++ /dev/null @@ -1,68 +0,0 @@ -/******************************************************************** - * - * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms - * - * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco_svc.h,v $ - * $Revision: 1.2 $ - * $Author: mleeman $ - * $Date: 2005/02/21 12:48:58 $ - * - * Last ChangeLog Entry - * $Log: barco_svc.h,v $ - * Revision 1.2 2005/02/21 12:48:58 mleeman - * update of copyright years (feedback wd) - * - * Revision 1.1 2005/02/14 09:31:07 mleeman - * renaming of files - * - * Revision 1.1 2005/02/14 09:23:46 mleeman - * - moved 'barcohydra' directory to a more generic barco; since we will be - * supporting and adding multiple boards - * - * Revision 1.1 2005/02/08 15:40:19 mleeman - * modified and added platform files - * - * Revision 1.2 2005/01/25 08:05:04 mleeman - * more cleanup of the code - * - * Revision 1.1 2004/07/20 08:49:55 mleeman - * Working version of the default and nfs kernel booting. - * - * - *******************************************************************/ - -#ifndef _LOCAL_BARCOHYDRA_H_ -#define _LOCAL_BARCOHYDRA_H_ - -#include -#include - -/* Defines for the barcohydra board */ -#ifndef CFG_FLASH_ERASE_SECTOR_LENGTH -#define CFG_FLASH_ERASE_SECTOR_LENGTH (0x10000) -#endif - -#ifndef CFG_DEFAULT_KERNEL_ADDRESS -#define CFG_DEFAULT_KERNEL_ADDRESS (CFG_FLASH_BASE + 0x30000) -#endif - -#ifndef CFG_WORKING_KERNEL_ADDRESS -#define CFG_WORKING_KERNEL_ADDRESS (0xFFE00000) -#endif - - -typedef struct SBootInfo { - unsigned int address; - unsigned int size; - unsigned char state; -}TSBootInfo; - -/* barcohydra.c */ -int checkboard(void); -long int initdram(int board_type); -void pci_init_board(void); -void check_flash(void); -int write_flash(char *addr, char value); -TSBootInfo* find_boot_info(void); -void final_boot(void); -#endif diff --git a/board/barco/config.mk b/board/barco/config.mk deleted file mode 100644 index f950c07..0000000 --- a/board/barco/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Barco Hydra/SCN boards -# - -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/barco/early_init.S b/board/barco/early_init.S deleted file mode 100644 index 07dafb7..0000000 --- a/board/barco/early_init.S +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2001 - * Thomas Koeller, tkoeller@gmx.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASSEMBLY__ -#define __ASSEMBLY__ 1 -#endif - -#include -#include -#include -#include - -#if defined(USE_DINK32) - /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ - #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) -#else - #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) -#endif - - .text - - /* Values to program into memory controller registers */ -tbl: .long MCCR1, MCCR1VAL - .long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT - .long MCCR3 - .long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ - (CFG_REFREC << MCCR3_REFREC_SHIFT) | \ - (CFG_RDLAT << MCCR3_RDLAT_SHIFT) - .long MCCR4 - .long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ - (CFG_REGISTERD_TYPE_BUFFER << 20) | \ - (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ - ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \ - (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ - (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ - ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) - .long MSAR1 - .long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR1 - .long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MSAR2 - .long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR2 - .long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR1 - .long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR1 - .long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR2 - .long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR2 - .long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long 0 - - - /* - * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This - * must be done in assembly, since we have no stack at this point. - */ - .global early_init_f -early_init_f: - mflr r10 - - /* basic memory controller configuration */ - lis r3, CONFIG_ADDR_HIGH - lis r4, CONFIG_DATA_HIGH - bl lab -lab: mflr r5 - lwzu r0, tbl - lab(r5) -loop: lwz r1, 4(r5) - stwbrx r0, 0, r3 - eieio - stwbrx r1, 0, r4 - eieio - lwzu r0, 8(r5) - cmpli cr0, 0, r0, 0 - bne cr0, loop - - /* set bank enable bits */ - lis r0, MBER@h - ori r0, 0, MBER@l - li r1, CFG_BANK_ENABLE - stwbrx r0, 0, r3 - eieio - stb r1, 0(r4) - eieio - - /* delay loop */ - lis r0, 0x0003 - mtctr r0 -delay: bdnz delay - - /* enable memory controller */ - lis r0, MCCR1@h - ori r0, 0, MCCR1@l - stwbrx r0, 0, r3 - eieio - lwbrx r0, 0, r4 - oris r0, 0, MCCR1_MEMGO@h - stwbrx r0, 0, r4 - eieio - - /* set up stack pointer */ - lis r1, CFG_INIT_SP_OFFSET@h - ori r1, r1, CFG_INIT_SP_OFFSET@l - - mtlr r10 - blr diff --git a/board/barco/flash.c b/board/barco/flash.c deleted file mode 100644 index 6cb19b7..0000000 --- a/board/barco/flash.c +++ /dev/null @@ -1,611 +0,0 @@ -/******************************************************************** - * - * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms - * - * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/flash.c,v $ - * $Revision: 1.3 $ - * $Author: mleeman $ - * $Date: 2005/02/21 12:48:58 $ - * - * Last ChangeLog Entry - * $Log: flash.c,v $ - * Revision 1.3 2005/02/21 12:48:58 mleeman - * update of copyright years (feedback wd) - * - * Revision 1.2 2005/02/21 11:04:04 mleeman - * remove dead code and Coding style (feedback wd) - * - * Revision 1.1 2005/02/14 09:23:46 mleeman - * - moved 'barcohydra' directory to a more generic barco; since we will be - * supporting and adding multiple boards - * - * Revision 1.2 2005/02/09 12:56:23 mleeman - * add generic header to track changes in sources - * - * - *******************************************************************/ - -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*flash command address offsets*/ - -#define ADDR0 (0xAAA) -#define ADDR1 (0x555) -#define ADDR3 (0x001) - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const)); - -typedef struct{ - FLASH_WORD_SIZE extval; - unsigned short intval; -} map_entry; - -static unsigned long flash_id(unsigned char mfct, unsigned char chip) -{ - static const map_entry mfct_map[] = { - {(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, - {(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, - {(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, - {(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, - {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, - {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} - }; - - static const map_entry chip_map[] = { - {AMD_ID_F040B, FLASH_AM040}, - {AMD_ID_F033C, FLASH_AM033}, - {AMD_ID_F065D, FLASH_AM065}, - {ATM_ID_LV040, FLASH_AT040}, - {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} - }; - - const map_entry *p; - unsigned long result = FLASH_UNKNOWN; - - /* find chip id */ - for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++){ - if(p->extval == chip){ - result = FLASH_VENDMASK | p->intval; - break; - } - } - - /* find vendor id */ - for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++){ - if(p->extval == mfct){ - result &= ~FLASH_VENDMASK; - result |= (unsigned long) p->intval << 16; - break; - } - } - - return result; -} - - -unsigned long flash_init(void) -{ - unsigned long i; - unsigned char j; - static const ulong flash_banks[] = CFG_FLASH_BANKS; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++){ - flash_info_t * const pflinfo = &flash_info[i]; - pflinfo->flash_id = FLASH_UNKNOWN; - pflinfo->size = 0; - pflinfo->sector_count = 0; - } - - /* Enable writes to Hydra/Argus flash */ - { - register unsigned int temp; - CONFIG_READ_WORD(PICR1,temp); - temp |= PICR1_FLASH_WR_EN; - CONFIG_WRITE_WORD(PICR1,temp); - } - - for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++){ - flash_info_t * const pflinfo = &flash_info[i]; - const unsigned long base_address = flash_banks[i]; - volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address; - - /* write autoselect sequence */ - flash[0x5555] = 0xaa; - flash[0x2aaa] = 0x55; - flash[0x5555] = 0x90; - __asm__ __volatile__("sync"); - - pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]); - - switch(pflinfo->flash_id & FLASH_TYPEMASK){ - case FLASH_AM033: - pflinfo->size = 0x00200000; - pflinfo->sector_count = 64; - for(j = 0; j < 64; j++){ - pflinfo->start[j] = base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_AM065: - pflinfo->size = 0x00800000; - pflinfo->sector_count =128; - for(j = 0; j < 128; j++){ - pflinfo->start[j] = base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_AT040: - pflinfo->size = 0x00080000; - pflinfo->sector_count = 2; - pflinfo->start[0] = base_address ; - pflinfo->start[1] = base_address + 0x00004000; - pflinfo->protect[0] = ((flash[0x02] & 0X01)==0) ? 0X02 : 0X01; - pflinfo->protect[1] = 0X02; - break; - case FLASH_AM040: - pflinfo->size = 0x00080000; - pflinfo->sector_count = 8; - for(j = 0; j < 8; j++){ - pflinfo->start[j] = base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_STM800AB: - pflinfo->size = 0x00100000; - pflinfo->sector_count = 19; - pflinfo->start[0] = base_address; - pflinfo->start[1] = base_address + 0x4000; - pflinfo->start[2] = base_address + 0x6000; - pflinfo->start[3] = base_address + 0x8000; - for(j = 1; j < 16; j++){ - pflinfo->start[j+3] = base_address + 0x00010000 * j; - } - break; - } - /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - /* reset device to read mode */ - flash[0x0000] = 0xf0; - __asm__ __volatile__("sync"); - } - - return flash_info[0].size + flash_info[1].size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if(info->flash_id != FLASH_UNKNOWN){ - switch(info->flash_id & FLASH_VENDMASK){ - case FLASH_MAN_ATM: - mfct = "Atmel"; - break; - case FLASH_MAN_AMD: - mfct = "AMD"; - break; - case FLASH_MAN_FUJ: - mfct = "FUJITSU"; - break; - case FLASH_MAN_STM: - mfct = "STM"; - break; - case FLASH_MAN_SST: - mfct = "SST"; - break; - case FLASH_MAN_BM: - mfct = "Bright Microelectonics"; - break; - case FLASH_MAN_INTEL: - mfct = "Intel"; - break; - } - - switch(info->flash_id & FLASH_TYPEMASK){ - case FLASH_AT040: - type = "AT49LV040 (512K * 8, uniform sector size)"; - break; - case FLASH_AM033: - type = "AM29F033C (4 Mbit * 8, uniform sector size)"; - break; - case FLASH_AM040: - type = "AM29F040B (512K * 8, uniform sector size)"; - break; - case FLASH_AM065: - type = "AM29F0465D ( 8 MBit * 8, uniform sector size) or part of AM29F652D( 16 MB)"; - break; - case FLASH_AM400B: - type = "AM29LV400B (4 Mbit, bottom boot sect)"; - break; - case FLASH_AM400T: - type = "AM29LV400T (4 Mbit, top boot sector)"; - break; - case FLASH_AM800B: - type = "AM29LV800B (8 Mbit, bottom boot sect)"; - break; - case FLASH_AM800T: - type = "AM29LV800T (8 Mbit, top boot sector)"; - break; - case FLASH_AM160T: - type = "AM29LV160T (16 Mbit, top boot sector)"; - break; - case FLASH_AM320B: - type = "AM29LV320B (32 Mbit, bottom boot sect)"; - break; - case FLASH_AM320T: - type = "AM29LV320T (32 Mbit, top boot sector)"; - break; - case FLASH_STM800AB: - type = "M29W800AB (8 Mbit, bottom boot sect)"; - break; - case FLASH_SST800A: - type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; - break; - case FLASH_SST160A: - type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; - break; - } - } - - printf( - "\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, - type, - info->size >> 10, - info->sector_count - ); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++){ - unsigned long size; - unsigned int erased; - unsigned long * flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = - (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for( - flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) && erased; - flash++ - ){ - erased = *flash == ~0x0UL; - } - - printf( - "%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", - info->protect[i] ? "RO" : " " - ); - } - - puts("\n"); - return; -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){ - sh8b = 3; - } - else{ - sh8b = 0; - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *)(info->start[0] + ( - (info->start[sect] - info->start[0]) << sh8b)); - if (info->flash_id & FLASH_MAN_SST){ - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - udelay(30000); /* wait 30 ms */ - } - else - addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag){ - enable_interrupts(); - } - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0){ - goto DONE; - } - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *)(info->start[0] + ( - (info->start[l_sect] - info->start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){ - sh8b = 3; - } - else{ - sh8b = 0; - } - - dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++){ - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag){ - enable_interrupts(); - } - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- */ diff --git a/board/barco/speed.h b/board/barco/speed.h deleted file mode 100644 index 46860e8..0000000 --- a/board/barco/speed.h +++ /dev/null @@ -1,78 +0,0 @@ -/******************************************************************** - * - * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms - * - * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/speed.h,v $ - * $Revision: 1.2 $ - * $Author: mleeman $ - * $Date: 2005/02/21 12:48:58 $ - * - * Last ChangeLog Entry - * $Log: speed.h,v $ - * Revision 1.2 2005/02/21 12:48:58 mleeman - * update of copyright years (feedback wd) - * - * Revision 1.1 2005/02/14 09:23:46 mleeman - * - moved 'barcohydra' directory to a more generic barco; since we will be - * supporting and adding multiple boards - * - * Revision 1.2 2005/02/09 12:56:23 mleeman - * add generic header to track changes in sources - * - * - *******************************************************************/ - -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/barco/u-boot.lds b/board/barco/u-boot.lds deleted file mode 100644 index 7bf8531..0000000 --- a/board/barco/u-boot.lds +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/bmw/Makefile b/board/bmw/Makefile deleted file mode 100644 index 621640b..0000000 --- a/board/bmw/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2002 -# James F. Dougherty, Broadcom Corporation, jfd@broadcom.com -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ns16550.o serial.o m48t59y.o - -SOBJS = early_init.o - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/bmw/README b/board/bmw/README deleted file mode 100644 index 70bc813..0000000 --- a/board/bmw/README +++ /dev/null @@ -1,331 +0,0 @@ -Broadcom 95xx BMW CPCI Platform - -Overview -========= -BMW is an MPC8245 system controller featuring: -* 3U CPCI Form Factor -* BCM5703 Gigabit Ethernet -* M48T59Y NVRAM -* 16MB DOC -* DIP Socket for Socketed DOC up to 1GB -* 64MB SDRAM -* LCD Display -* Configurable Jumper options for 66,85, and 100Mhz memory bus - - -BMW System Address Map -====================== -BMW uses the MPC8245 CHRP Address MAP B found in the MPC8245 Users Manual -(P.121, Section 3.1 Address Maps, Address Map B). Other I/O devices found -onboard the processor module are listed briefly below: - -0x00000000 - 0x40000000 - 64MB SDRAM SIMM - (Unregistered PC-100 SDRAM DIMM Module) - -0xFF000000 - 0xFF001FFF - M-Systems DiskOnChip (TM) 2000 - TSOP 16MB (MD2211-D16-V3) - -0x70000000 - 0x70001FFF - M-Systems DiskOnChip (TM) 2000 - DIP32 (Socketed 16MB - 1GB ) * - NOTE: this is not populated on all systems. - -0x7c000000 - 0x7c000000 - Reset Register - (Write 0 to reset) - -0x7c000001 - 0x7c000001 - System LED - (Clear Bit 7 to turn on, set to shut off) - -0x7c000002 - 0x7c000002 - M48T59 Watchdog IRQ3 - (Clear bit 7 to reset, set to assert IRQ3) - -0x7c000003 - 0x7c000003 - M48T59 Write-Protect Register - (Clear bit 7 to make R/W, set to make R/O) - -0x7c002000 - 0x7c002003 - Infineon OSRAM DLR2416 4 Character - 5x7 Dot Matrix Alphanumeric Display - (Each byte sets the appropriate character) - -0x7c004000 - 0x7c005FF0 - SGS-THOMSON M48T59Y 8K NVRAM/RTC - NVRAM Memory Region - -0x7c005FF0 - 0x7c005FFF - SGS-THOMSON M48T59Y 8K NVRAM/RTC - Realtime Clock Registers - -0xFFF00000 - 0xFFF80000 - 512K PLCC32 BootRom - (AMD AM29F040, ST 29W040B) - -0xFFF00100 - System Reset Vector - - -IO/MMU (BAT) Configuration -====================== -The following Block-Address-Translation (BAT) configuration -is recommended to access all I/O devices. - -#define CFG_IBAT0L (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - - -Interrupt Mappings -====================== -BMW uses MPC8245 discrete mode interrupts. With the following -hardwired mappings: - -BCM5701 10/100/1000 Ethernet IRQ1 -CompactPCI Interrupt A IRQ2 -RTC/Watchdog Interrupt IRQ3 -Internal NS16552 UART IRQ4 - - -Jumper Settings -====================== - -BMW has a jumper (JP600) for selecting 66, 85, or 100Mhz memory bus. -A jumper (X) is a 0 bit. - -Hence 66= 10110 - 85= 11000 - 100= 10000 - -Jumper Settings for various Speeds -======================= -J1 J2 J3 J4 J5 - X X 66Mhz -======================= -J1 J2 J3 J4 J5 - X X X 85Mhz -======================= -J1 J2 J3 J4 J5 - X X X X 100Mhz -======================= - -Obviously, 100Mhz memory bus is recommended for optimum performance. - - -U-Boot -=============== -Broadcom BMW board is supported under config_BWM option. -Supported features: - -- NVRAM setenv/getenv (used by Linux Kernel for configuration variables) -- BCM570x TFTP file transfer support -- LCD Display Support -- DOC Support - (underway) - - -U-Boot 1.2.0 (Aug 6 2002 - 17:44:48) - -CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache -Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B) -Built: Aug 6 2002 at 17:44:37 -Local Bus at 66 MHz -DRAM: 64 MB -FLASH: 4095 MB -In: serial -Out: serial -Err: serial -DOC: No DiskOnChip found -Hit any key to stop autoboot: 0 -=>printenv -bootdelay=5 -baudrate=9600 -clocks_in_mhz=1 -hostname=switch-2 -bootcmd=tftp 100000 vmlinux.img;bootm -gateway=10.16.64.1 -ethaddr=00:00:10:18:10:10 -nfsroot=172.16.40.111:/boot/root-fs -filesize=5ec8c -netmask=255.255.240.0 -ipaddr=172.16.40.114 -serverip=172.16.40.111 -root=/dev/nfs -stdin=serial -stdout=serial -stderr=serial - -Environment size: 315/8172 bytes -=>boot - - -DevTools -======== -ELDK - DENX Embedded Linux Development Kit - -ROM Emulator - Grammar Engine PROMICE P1160-90-AI21E (2MBx8bit, 90ns access time) - Grammar Engine PL32E 32Pin PLCC Emulation cables - Grammar Engine 3VA8CON (3Volt adapter with Short cables) - Grammar Engine FPNET PromICE Ethernet Adapters - -ICE - WRS/EST VisionICE-II (PPC8240) - - -=>reset - - -U-Boot 1.2.0 (Aug 6 2002 - 17:44:48) - -CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache -Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B) -Built: Aug 6 2002 at 17:44:37 -Local Bus at 66 MHz -DRAM: 64 MB -FLASH: 4095 MB -In: serial -Out: serial -Err: serial -DOC: No DiskOnChip found -Hit any key to stop autoboot: 0 - -Broadcom BCM5701 1000Base-T: bus 0, device 13, function 0: MBAR=0x80100000 -BCM570x PCI Memory base address @0x80100000 -eth0:Broadcom BCM5701 1000Base-T: 100 Mbps half duplex link up, flow control OFF -eth0: Broadcom BCM5701 1000Base-T @0x80100000,node addr 000010181010 -eth0: BCM5700 with Broadcom BCM5701 Integrated Copper transceiver found -eth0: 32-bit PCI 33MHz, MTU: 1500,Rx Checksum ON -ARP broadcast 1 -TFTP from server 172.16.40.111; our IP address is 172.16.40.114 -Filename 'vmlinux.img'. -Load address: 0x100000 -Loading: ################################################################# - ####################################T ############################# - ###################### -done -Bytes transferred = 777199 (bdbef hex) - -eth0:Broadcom BCM5701 1000Base-T,HALT,POWER DOWN,done - offline. -## Booting image at 00100000 ... - Image Name: vmlinux.bin.gz - Created: 2002-08-06 6:30:13 UTC - Image Type: PowerPC Linux Kernel Image (gzip compressed) - Data Size: 777135 Bytes = 758 kB = 0 MB - Load Address: 00000000 - Entry Point: 00000000 - Verifying Checksum ... OK - Uncompressing Kernel Image ... OK -Memory BAT mapping: BAT2=64Mb, BAT3=0Mb, residual: 0Mb -Linux version 2.4.19-rc3 (jfd@que) (gcc version 2.95.3 20010111 (prerelease/franzo/20010111)) #168 Mon Aug 5 23:29:20 PDT 2002 -CPU:82xx: 32 I-Cache Block Size, 32 D-Cache Block Size PVR: 0x810000 -U-Boot Environment: 0xc01b08f0 -IP PNP: 802.3 Ethernet Address=<0:0:10:18:10:10> -cpu0: MPC8245/KAHLUA-II : BMW Platform : 64MB RAM: BPLD Rev. 6e -NOTICE: mounting root file system via NFS -IP PNP: switch-2: eth0 IP 172.16.40.114/255.255.240.0 gateway 10.16.64.1 server 172.16.40.111 -On node 0 totalpages: 16384 -zone(0): 16384 pages. -zone(1): 0 pages. -zone(2): 0 pages. -Kernel command line: console=ttyS0,9600 ip=172.16.40.114:172.16.40.111:10.16.64.1:255.255.240.0:switch-2:eth0 root=/dev/nfs rw nfsroot=172.16.40.111:/boot/root-fs,timeo=200,retrans=500 nfsaddrs=172.16.40.114:172.16.40.111 -root_dev_setup:/dev/nfs or 00:ff -time_init: decrementer frequency = 16.501145 MHz -Calibrating delay loop... 175.71 BogoMIPS -Memory: 62572k available (1396k kernel code, 436k data, 100k init, 0k highmem) -Dentry cache hash table entries: 8192 (order: 4, 65536 bytes) -Inode cache hash table entries: 4096 (order: 3, 32768 bytes) -Mount-cache hash table entries: 1024 (order: 1, 8192 bytes) -Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes) -Page-cache hash table entries: 16384 (order: 4, 65536 bytes) -POSIX conformance testing by UNIFIX -PCI: Probing PCI hardware -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Initializing RT netlink socket -Starting kswapd -devfs: v1.12a (20020514) Richard Gooch (rgooch@atnf.csiro.au) -devfs: devfs_debug: 0x0 -devfs: boot_options: 0x1 -Installing knfsd (copyright (C) 1996 okir@monad.swb.de). -pty: 256 Unix98 ptys configured -Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled -Testing ttyS0 (0xf7f51500, 0xf7f51500)... -Testing ttyS1 (0xfc004600, 0xfc004600)... -ttyS00 at 0xf7f51500 (irq = 24) is a ST16650 -ttyS01 at 0xfc004600 (irq = 25) is a 16550A -Real Time Clock Driver v1.10e -RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize -loop: loaded (max 8 devices) -TFFS 5.1.1 Flash disk driver for DiskOnChip -Copyright (C) 1998,2001 M-Systems Flash Disk Pioneers Ltd. -DOC device(s) found: 1 -fl_init: registered device at major: 100 -fl_geninit: registered device at major: 100 -Partition check: - fla: p1 -partition: /dev/fl/0: start_sect: 0,nr_sects: 32000 Fl_blk_size[]: 16000KB -partition: /dev/fl/1: start_sect: 2,nr_sects: 31998 Fl_blk_size[]: 15999KB -partition: /dev/fl/2: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB -partition: /dev/fl/3: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB -Broadcom Gigabit Ethernet Driver bcm5700 ver. 3.0.7 (07/17/02) -eth0: Broadcom BCM5701 found at mem bfff0000, IRQ 1, node addr 000010181010 -eth0: Broadcom BCM5701 Integrated Copper transceiver found -eth0: Scatter-gather ON, 64-bit DMA ON, Tx Checksum ON, Rx Checksum ON, 802.1Q VLAN ON -bond0 registered without MII link monitoring, in bonding mode. -rtc: unable to get misc minor -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP, IGMP -IP: routing cache hash table of 512 buckets, 4Kbytes -TCP: Hash tables configured (established 4096 bind 4096) -bcm5700: eth0 NIC Link is UP, 100 Mbps half duplex -IP-Config: Gateway not on directly connected network. -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -802.1Q VLAN Support v1.7 Ben Greear -All bugs added by David S. Miller -Looking up port of RPC 100003/2 on 172.16.40.111 -Looking up port of RPC 100005/1 on 172.16.40.111 -VFS: Mounted root (nfs filesystem). -Mounted devfs on /dev -Freeing unused kernel memory: 100k init -INIT: version 2.78 booting -Mounting local filesystems... -not mounted anything -Setting up symlinks in /dev...done. -Setting up extra devices in /dev...done. -Starting devfsd...Started device management daemon for /dev -INIT: Entering runlevel: 2 -Starting internet superserver: inetd. - - -Welcome to Linux/PPC -MPC8245/BMW - - -switch-2 login: root -Password: -PAM_unix[49]: (login) session opened for user root by LOGIN(uid=0) -Last login: Thu Nov 25 11:51:14 1920 on console - - -Welcome to Linux/PPC -MPC8245/BMW - - -login[49]: ROOT LOGIN on `console' - -root@switch-2:~# cat /proc/cpuinfo -cpu : 82xx -revision : 16.20 (pvr 8081 1014) -bogomips : 175.71 -vendor : Broadcom -machine : BMW/MPC8245 -root@switch-2:~# diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c deleted file mode 100644 index 485e050..0000000 --- a/board/bmw/bmw.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * (C) Copyright 2002 - * James F. Dougherty, Broadcom Corporation, jfd@broadcom.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "bmw.h" -#include "m48t59y.h" -#include - - -int checkboard(void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n"); - printf("Built: %s at %s\n", __DATE__ , __TIME__ ); - /* printf("MPLD: Revision %d\n", SYS_REVID_GET()); */ - printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; -} - -long int initdram(int board_type) -{ - return 64*1024*1024; -} - - -void -get_tod(void) -{ - int year, month, day, hour, minute, second; - - m48_tod_get(&year, - &month, - &day, - &hour, - &minute, - &second); - - printf(" Current date/time: %d/%d/%d %d:%d:%d \n", - month, day, year, hour, minute, second); - -} - -/* - * EPIC, PCI, and I/O devices. - * Initialize Mousse Platform, probe for PCI devices, - * Query configuration parameters if not set. - */ -int misc_init_f (void) -{ -#if 0 - m48_tod_init(); /* Init SGS M48T59Y TOD/NVRAM */ - printf("RTC: M48T589 TOD/NVRAM (%d) bytes\n", - TOD_NVRAM_SIZE); - get_tod(); -#endif - - sys_led_msg("BOOT"); - return 0; -} - - -/* - * Initialize PCI Devices, report devices found. - */ -struct pci_controller hose; - -void pci_init_board (void) -{ - pci_mpc824x_init(&hose); - /* pci_dev_init(0); */ -} - -/* - * Write characters to LCD display. - * Note that the bytes for the first character is the last address. - */ -void -sys_led_msg(char* msg) -{ - LED_REG(0) = msg[3]; - LED_REG(1) = msg[2]; - LED_REG(2) = msg[1]; - LED_REG(3) = msg[0]; -} - -/* - * Map onboard TSOP-16MB DOC FLASH chip. - */ -void doc_init (void) -{ - doc_probe(DOC_BASE_ADDR); -} - -#define NV_ADDR ((volatile unsigned char *) CFG_ENV_ADDR) - -/* Read from NVRAM */ -void* -nvram_read(void *dest, const long src, size_t count) -{ - int i; - volatile unsigned char* d = (unsigned char*)dest; - volatile unsigned char* s = (unsigned char*)src; - - for( i = 0; i < count;i++) - d[i] = s[i]; - - return dest; -} - -/* Write to NVRAM */ -void -nvram_write(long dest, const void *src, size_t count) -{ - int i; - volatile unsigned char* d = (unsigned char*)dest; - volatile unsigned char* s = (unsigned char*)src; - - SYS_TOD_UNPROTECT(); - - for( i = 0; i < count;i++) - d[i] = s[i]; - - SYS_TOD_PROTECT(); -} diff --git a/board/bmw/bmw.h b/board/bmw/bmw.h deleted file mode 100644 index dd97569..0000000 --- a/board/bmw/bmw.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * BMW/MPC8245 Board definitions. - * For more info, see http://www.vooha.com/ - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * James Dougherty (jfd@broadcom.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __BMW_H -#define __BMW_H - -/* System addresses */ - -#define PCI_SPECIAL_BASE 0xfe000000 -#define PCI_SPECIAL_SIZE 0x01000000 - -#define EUMBBAR_VAL 0x80500000 /* Location of EUMB region */ -#define EUMBSIZE 0x00100000 /* Size of EUMB region */ - -/* Extended ROM space devices */ -#define DOC_BASE_ADDR 0xff000000 /* Onboard DOC TSOP 16MB */ -#define DOC2_BASE_ADDR 0x70000000 /* DIP32 socket -> 1GB */ -#define XROM_BASE_ADDR 0x7c000000 /* RCS2 (PAL / Satellite IO) */ -#define PLD_REG_BASE XROM_BASE_ADDR -#define LED_REG_BASE (XROM_BASE_ADDR | 0x2000) -#define TOD_BASE (XROM_BASE_ADDR | 0x4000) -#define LED_REG(x) (*(volatile unsigned char *) \ - (LED_REG_BASE + (x))) -#define XROM_DEV_SIZE 0x00006000 - -#define ENET_DEV_BASE 0x80000000 - -#define PLD_REG(off) (*(volatile unsigned char *)\ - (PLD_REG_BASE + (off))) - -#define PLD_REVID_B1 0x7f /* Fix me */ -#define PLD_REVID_B2 0x01 /* Fix me */ - -#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */ -#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f) -#define SYS_LED_OFF() (PLD_REG(1) |= 0x80) -#define SYS_LED_ON() (PLD_REG(1) &= ~0x80) -#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80) -#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80) -#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80) -#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80) - -#define TOD_REG_BASE (TOD_BASE | 0x1ff0) -#define TOD_NVRAM_BASE TOD_BASE -#define TOD_NVRAM_SIZE 0x1ff0 -#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE) -#define RTC(r) (TOD_BASE + r) - -/* Onboard BCM570x device */ -#define PCI_ENET_IOADDR 0x80000000 -#define PCI_ENET_MEMADDR 0x80000000 - - -#ifndef __ASSEMBLY__ -/* C Function prototypes */ -void sys_led_msg(char* msg); - -#endif /* !__ASSEMBLY__ */ - -#endif /* __BMW_H */ diff --git a/board/bmw/config.mk b/board/bmw/config.mk deleted file mode 100644 index f991549..0000000 --- a/board/bmw/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# CU824 board -# - -TEXT_BASE = 0xFFF00000 -# NOTE: The flags below affect how the BCM570x driver is compiled -PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\ - -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256\ - -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S deleted file mode 100644 index e6400c3..0000000 --- a/board/bmw/early_init.S +++ /dev/null @@ -1,1170 +0,0 @@ -#include -#include -#include -#include -#include - -#define USE_V2_INIT 1 /* Jimmy Blair's initialization. */ - - -/* - * Initialize the MMU using BAT entries and hardwired TLB - * This obviates the need for any code in cpu_init_f which - * configures the BAT registers. -*/ -#define MEMORY_MGMT_MSR_BITS (MSR_DR | MSR_IR) /* Data and Inst Relocate */ - .global iommu_setup - /* Initialize IO/MMU mappings via BAT method Ch. 7, - * PPC Programming Reference - */ -iommu_setup: - -/* initialize the BAT registers (SPRs 528 - 543 */ -#define mtibat0u(x) mtspr 528,(x) /* SPR 528 (IBAT0U) */ -#define mtibat0l(x) mtspr 529,(x) /* SPR 529 (IBAT0L) */ -#define mtibat1u(x) mtspr 530,(x) /* SPR 530 (IBAT1U) */ -#define mtibat1l(x) mtspr 531,(x) /* SPR 531 (IBAT1L) */ -#define mtibat2u(x) mtspr 532,(x) /* SPR 532 (IBAT2U) */ -#define mtibat2l(x) mtspr 533,(x) /* SPR 533 (IBAT2L) */ -#define mtibat3u(x) mtspr 534,(x) /* SPR 534 (IBAT3U) */ -#define mtibat3l(x) mtspr 535,(x) /* SPR 535 (IBAT3L) */ -#define mtdbat0u(x) mtspr 536,(x) /* SPR 536 (DBAT0U) */ -#define mtdbat0l(x) mtspr 537,(x) /* SPR 537 (DBAT0L) */ -#define mtdbat1u(x) mtspr 538,(x) /* SPR 538 (DBAT1U) */ -#define mtdbat1l(x) mtspr 539,(x) /* SPR 539 (DBAT1L) */ -#define mtdbat2u(x) mtspr 540,(x) /* SPR 540 (DBAT2U) */ -#define mtdbat2l(x) mtspr 541,(x) /* SPR 541 (DBAT2L) */ -#define mtdbat3u(x) mtspr 542,(x) /* SPR 542 (DBAT3U) */ -#define mtdbat3l(x) mtspr 543,(x) /* SPR 543 (DBAT3L) */ - - -/* PowerPC processors do not necessarily initialize the BAT - registers on power-up or reset. So they are in an unknown - state. Before programming the BATs for the first time, all - BAT registers MUST have their Vs and Vp bits cleared in the - upper BAT half in order to avoid possibly having 2 BATs - valid and mapping the same memory region. - - The reason for this is that, even with address translation - disabled, multiple BAT hits for an address are treated as - programming errors and can cause unpredictable results. - - It is up to the software to make sure it never has 2 IBAT - mappings or 2 DBAT mappings that are valid for the same - addresses. It is not necessary to perform this code - sequence every time the BATs are programmed, only when - there is a possibility that there may be overlapping BAT - entries. - - When programming the BATs in non-reset scenarios, even if - you are sure that your new mapping will not temporarily - create overlapping regions, it is still a wise idea to - invalidate a BAT entry by setting its upper BAT register to - all 0's before programming it. This will avoid having a - BAT marked valid that is in an unknown or transient state -*/ - - addis r5,0,0x0000 - mtibat0u(r5) - mtibat0l(r5) - mtibat1u(r5) - mtibat1l(r5) - mtibat2u(r5) - mtibat2l(r5) - mtibat3u(r5) - mtibat3l(r5) - mtdbat0u(r5) - mtdbat0l(r5) - mtdbat1u(r5) - mtdbat1l(r5) - mtdbat2u(r5) - mtdbat2l(r5) - mtdbat3u(r5) - mtdbat3l(r5) - isync - -/* - * Set up I/D BAT0 - */ - lis r4, CFG_DBAT0L@h - ori r4, r4, CFG_DBAT0L@l - lis r3, CFG_DBAT0U@h - ori r3, r3, CFG_DBAT0U@l - - mtdbat0l(r4) - isync - mtdbat0u(r3) - isync - sync - - lis r4, CFG_IBAT0L@h - ori r4, r4, CFG_IBAT0L@l - lis r3, CFG_IBAT0U@h - ori r3, r3, CFG_IBAT0U@l - - isync - mtibat0l(r4) - isync - mtibat0u(r3) - isync - -/* - * Set up I/D BAT1 - */ - lis r4, CFG_IBAT1L@h - ori r4, r4, CFG_IBAT1L@l - lis r3, CFG_IBAT1U@h - ori r3, r3, CFG_IBAT1U@l - - isync - mtibat1l(r4) - isync - mtibat1u(r3) - isync - mtdbat1l(r4) - isync - mtdbat1u(r3) - isync - sync - -/* - * Set up I/D BAT2 - */ - lis r4, CFG_IBAT2L@h - ori r4, r4, CFG_IBAT2L@l - lis r3, CFG_IBAT2U@h - ori r3, r3, CFG_IBAT2U@l - - isync - mtibat2l(r4) - isync - mtibat2u(r3) - isync - mtdbat2l(r4) - isync - mtdbat2u(r3) - isync - sync - -/* - * Setup I/D BAT3 - */ - lis r4, CFG_IBAT3L@h - ori r4, r4, CFG_IBAT3L@l - lis r3, CFG_IBAT3U@h - ori r3, r3, CFG_IBAT3U@l - - isync - mtibat3l(r4) - isync - mtibat3u(r3) - isync - mtdbat3l(r4) - isync - mtdbat3u(r3) - isync - sync - - -/* - * Invalidate all 64 TLB's - */ - lis r3, 0 - mtctr r3 - lis r5, 4 - -tlblp: - tlbie r3 - sync - addi r3, r3, 0x1000 - cmplw r3, r5 - blt tlblp - - sync - -/* - * Enable Data Translation - */ - lis r4, MEMORY_MGMT_MSR_BITS@h - ori r4, r4, MEMORY_MGMT_MSR_BITS@l - mfmsr r3 - or r3, r4, r3 - mtmsr r3 - isync - sync - - blr - - -#ifdef USE_V2_INIT -/* #define USER_I_CACHE_ENABLE 1*/ /* Fast rom boots */ -/* Macro for hiadjust and lo */ -#define HIADJ(arg) arg@ha -#define HI(arg) arg@h -#define LO(arg) arg@l - -#undef LOADPTR -#define LOADPTR(reg,const32) \ - addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32) - -.globl early_init_f - -early_init_f: -/* MPC8245/BMW CPCI System Init - * Jimmy Blair, Broadcom Corp, 2002. - */ - mflr r11 - /* Zero-out registers */ - - addis r0,r0,0 - mtspr SPRG0,r0 - mtspr SPRG1,r0 - mtspr SPRG2,r0 - mtspr SPRG3,r0 - - /* Set MPU/MSR to a known state. Turn on FP */ - - LOADPTR (r3, MSR_FP) - sync - mtmsr r3 - isync - - /* Init the floating point control/status register */ - - mtfsfi 7,0x0 - mtfsfi 6,0x0 - mtfsfi 5,0x0 - mtfsfi 4,0x0 - mtfsfi 3,0x0 - mtfsfi 2,0x0 - mtfsfi 1,0x0 - mtfsfi 0,0x0 - isync - - /* Set MPU/MSR to a known state. Turn off FP */ - -#if 1 /* Turn off floating point (remove to keep FP on) */ - andi. r3, r3, 0 - sync - mtmsr r3 - isync -#endif - - /* Init the Segment registers */ - - andi. r3, r3, 0 - isync - mtsr 0,r3 - isync - mtsr 1,r3 - isync - mtsr 2,r3 - isync - mtsr 3,r3 - isync - mtsr 4,r3 - isync - mtsr 5,r3 - isync - mtsr 6,r3 - isync - mtsr 7,r3 - isync - mtsr 8,r3 - isync - mtsr 9,r3 - isync - mtsr 10,r3 - isync - mtsr 11,r3 - isync - mtsr 12,r3 - isync - mtsr 13,r3 - isync - mtsr 14,r3 - isync - mtsr 15,r3 - isync - - /* Turn off data and instruction cache control bits */ - - mfspr r3, HID0 - isync - rlwinm r4, r3, 0, 18, 15 /* r4 has ICE and DCE bits cleared */ - sync - isync - mtspr HID0, r4 /* HID0 = r4 */ - isync - - /* Get cpu type */ - - mfspr r28, PVR - rlwinm r28, r28, 16, 16, 31 - - /* invalidate the MPU's data/instruction caches */ - - lis r3, 0x0 - cmpli 0, 0, r28, CPU_TYPE_603 - beq cpuIs603 - cmpli 0, 0, r28, CPU_TYPE_603E - beq cpuIs603 - cmpli 0, 0, r28, CPU_TYPE_603P - beq cpuIs603 - cmpli 0, 0, r28, CPU_TYPE_604R - bne cpuNot604R - -cpuIs604R: - lis r3, 0x0 - mtspr HID0, r3 /* disable the caches */ - isync - ori r4, r4, 0x0002 /* disable BTAC by setting bit 30 */ - -cpuNot604R: - ori r3, r3, (HID0_ICFI |HID0_DCI) - -cpuIs603: - ori r3, r3, (HID0_ICE | HID0_DCE) - or r4, r4, r3 /* set bits */ - sync - isync - mtspr HID0, r4 /* HID0 = r4 */ - andc r4, r4, r3 /* clear bits */ - isync - cmpli 0, 0, r28, CPU_TYPE_604 - beq cpuIs604 - cmpli 0, 0, r28, CPU_TYPE_604E - beq cpuIs604 - cmpli 0, 0, r28, CPU_TYPE_604R - beq cpuIs604 - mtspr HID0, r4 - isync - -#ifdef USER_I_CACHE_ENABLE - b instCacheOn603 -#else - b cacheEnableDone -#endif - -cpuIs604: - LOADPTR (r5, 0x1000) /* loop count, 0x1000 */ - mtspr CTR, r5 -loopDelay: - nop - bdnz loopDelay - isync - mtspr HID0, r4 - isync - - /* turn the Instruction cache ON for faster FLASH ROM boots */ - -#ifdef USER_I_CACHE_ENABLE - - ori r4, r4, (HID0_ICE | HID0_ICFI) - isync /* Synchronize for ICE enable */ - b writeReg4 -instCacheOn603: - ori r4, r4, (HID0_ICE | HID0_ICFI) - rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */ - - /* - * The setting of the instruction cache enable (ICE) bit must be - * preceded by an isync instruction to prevent the cache from being - * enabled or disabled while an instruction access is in progress. - */ - isync -writeReg4: - mtspr HID0, r4 /* Enable Instr Cache & Inval cache */ - cmpli 0, 0, r28, CPU_TYPE_604 - beq cacheEnableDone - cmpli 0, 0, r28, CPU_TYPE_604E - beq cacheEnableDone - - mtspr HID0, r3 /* using 2 consec instructions */ - /* PPC603 recommendation */ -#endif -cacheEnableDone: - - /* Detect map A or B */ - - addis r5,r0, HI(CHRP_REG_ADDR) - addis r6,r0, HI(CHRP_REG_DATA) - LOADPTR (r7, KAHLUA_ID) /* Kahlua PCI controller ID */ - LOADPTR (r8, BMC_BASE) - - stwbrx r8,0,(r5) - lwbrx r3,0,(r6) /* Store read value to r3 */ - cmp 0,0,r3,r7 - beq cr0, X4_KAHLUA_START - - /* It's not an 8240, is it an 8245? */ - - LOADPTR (r7, KAHLUA2_ID) /* Kahlua PCI controller ID */ - cmp 0,0,r3,r7 - beq cr0, X4_KAHLUA_START - - /* Save the PCI controller type in r7 */ - mr r7, r3 - - LOADPTR (r5, PREP_REG_ADDR) - LOADPTR (r6, PREP_REG_DATA) - -X4_KAHLUA_START: - /* MPC8245 changes begin here */ - LOADPTR (r3, MPC107_PCI_CMD) /* PCI command reg */ - stwbrx r3,0,r5 - li r4, 6 /* Command register value */ - sthbrx r4, 0, r6 - - LOADPTR (r3, MPC107_PCI_STAT) /* PCI status reg */ - stwbrx r3,0,r5 - li r4, -1 /* Write-to-clear all bits */ - li r3, 2 /* PCI_STATUS is at +2 offset */ - sthbrx r4, r3, r6 - - /*-------PROC_INT1_ADR */ - - LOADPTR (r3, PROC_INT1_ADR) /* Processor I/F Config 1 reg. */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xff141b98) - stwbrx r4,0,r6 - - /*-------PROC_INT2_ADR */ - - LOADPTR (r3, PROC_INT2_ADR) /* Processor I/F Config 2 reg. */ - stwbrx r3,0,r5 - lis r4, 0x2000 /* Flush PCI config writes */ - stwbrx r4,0,r6 - - LOADPTR (r9, KAHLUA2_ID) - cmpl 0, 0, r7, r9 - bne L1not8245 - - /* MIOCR1 -- turn on bit for DLL delay */ - - LOADPTR (r3, MIOCR1_ADR_X) - stwbrx r3,0,r5 - li r4, 0x04 - stb r4, MIOCR1_SHIFT(r6) - - /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */ - /* SDRAM_CLK_DEL (0x77)*/ - - LOADPTR (r3, MIOCR2_ADR_X) - stwbrx r3,0,r5 - li r4, 0x10 - stb r4, MIOCR2_SHIFT(r6) - - /* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */ - - LOADPTR (r3, PMCR2_ADR_X) - stwbrx r3,0,r5 - li r4, 0x20 - stb r4, PMCR2_SHIFT(r6) - - /* Initialize EUMBBAR early since 8245 has internal UART in EUMB */ - - LOADPTR (r3, EUMBBAR) - stwbrx r3,0,r5 - LOADPTR (r4, CFG_EUMB_ADDR) - stwbrx r4,0,r6 - -L1not8245: - - /* Toggle the DLL reset bit in AMBOR */ - - LOADPTR (r3, AMBOR) - stwbrx r3,0,r5 - lbz r4, 0(r6) - - andi. r4, r4, 0xdf - stb r4, 0(r6) /* Clear DLL_RESET */ - sync - - ori r4, r4, 0x20 /* Set DLL_RESET */ - stb r4, 0(r6) - sync - - andi. r4, r4, 0xdf - stb r4, 0(r6) /* Clear DLL_RESET */ - - - /* Enable RCS2, use supplied timings */ - LOADPTR (r3, ERCR1) - stwbrx r3,0,r5 - LOADPTR (r4, 0x80408000) - stwbrx r4,0,r6 - - /* Disable RCS3 parameters */ - LOADPTR (r3, ERCR2) - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000000) - stwbrx r4,0,r6 - - /* RCS3 at 0x70000000, 64KBytes */ - LOADPTR (r3, ERCR2) - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000004) - stwbrx r4,0,r6 - - /*-------MCCR1 */ - -#ifdef INCLUDE_ECC -#define MC_ECC 1 -#else /* INCLUDE_ECC */ -#define MC_ECC 0 -#endif /* INCLUDE_ECC */ - -#define MC1_ROMNAL 8 /* 0-15 */ -#define MC1_ROMFAL 11 /* 0-31 */ -#define MC1_DBUS_SIZE 0 /* 0-3, read only */ -#define MC1_BURST 0 /* 0-1 */ -#define MC1_MEMGO 0 /* 0-1 */ -#define MC1_SREN 1 /* 0-1 */ -#define MC1_RAM_TYPE 0 /* 0-1 */ -#define MC1_PCKEN MC_ECC /* 0-1 */ -#define MC1_BANKBITS 0x5555 /* 2 bits/bank 7-0 */ - - LOADPTR (r3, MEM_CONT1_ADR) /* Set MCCR1 (F0) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \ - MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \ - MC1_MEMGO << 19 | MC1_SREN << 18 | \ - MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 ) - li r3, MC1_BANKBITS - cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ - bne BankBitsAdd - cmpli 0, 0, r3, 0x5555 - beq K2BankBitsHack /* On 8245, 5555 ==> 0 */ -BankBitsAdd: - ori r4, r3, 0 -K2BankBitsHack: - stwbrx r4, 0, r6 - - /*------- MCCR2 */ - -#define MC2_TS_WAIT_TIMER 0 /* 0-7 */ -#define MC2_ASRISE 8 /* 0-15 */ -#define MC2_ASFALL 4 /* 0-15 */ -#define MC2_INLINE_PAR_NOT_ECC 0 /* 0-1 */ -#define MC2_WRITE_PARITY_CHK_EN MC_ECC /* 0-1 */ -#define MC2_INLRD_PARECC_CHK_EN MC_ECC /* 0-1 */ -#define MC2_ECC_EN 0 /* 0-1 */ -#define MC2_EDO 0 /* 0-1 */ -/* -* N.B. This refresh interval looks good up to 85 MHz with Hynix SDRAM. -* May need to be decreased for 100 MHz -*/ -#define MC2_REFINT 0x3a5 /* 0-0x3fff */ -#define MC2_RSV_PG 0 /* 0-1 */ -#define MC2_RMW_PAR MC_ECC /* 0-1 */ - - LOADPTR (r3, MEM_CONT2_ADR) /* Set MCCR2 (F4) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \ - MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \ - MC2_WRITE_PARITY_CHK_EN << 19 | \ - MC2_INLRD_PARECC_CHK_EN << 18 | \ - MC2_ECC_EN << 17 | MC2_EDO << 16 | \ - MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR) - cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ - bne notK2 - /* clear Kahlua2 reserved bits */ - LOADPTR (r3, 0xfffcffff) - and r4, r4, r3 -notK2: - stwbrx r4,0,r6 - - /*------- MCCR3 */ - -#define MC_BSTOPRE 0x079 /* 0-0x7ff */ - -#define MC3_BSTOPRE_U (MC_BSTOPRE >> 4 & 0xf) -#define MC3_REFREC 8 /* 0-15 */ -#define MC3_RDLAT (4+MC_ECC) /* 0-15 */ -#define MC3_CPX 0 /* 0-1 */ -#define MC3_RAS6P 0 /* 0-15 */ -#define MC3_CAS5 0 /* 0-7 */ -#define MC3_CP4 0 /* 0-7 */ -#define MC3_CAS3 0 /* 0-7 */ -#define MC3_RCD2 0 /* 0-7 */ -#define MC3_RP1 0 /* 0-7 */ - - LOADPTR (r3, MEM_CONT3_ADR) /* Set MCCR3 (F8) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \ - MC3_RDLAT << 20 | MC3_CPX << 19 | \ - MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \ - MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1) - cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ - bne notK2b - /* clear Kahlua2 reserved bits */ - LOADPTR (r3, 0xff000000) - and r4, r4, r3 -notK2b: - stwbrx r4,0,r6 - - /*------- MCCR4 */ - -#define MC4_PRETOACT 3 /* 0-15 */ -#define MC4_ACTOPRE 5 /* 0-15 */ -#define MC4_WMODE 0 /* 0-1 */ -#define MC4_INLINE MC_ECC /* 0-1 */ -#define MC4_REGISTERED (1-MC_ECC) /* 0-1 */ -#define MC4_BSTOPRE_UU (MC_BSTOPRE >> 8 & 3) -#define MC4_REGDIMM 0 /* 0-1 */ -#define MC4_SDMODE_CAS 2 /* 0-7 */ -#define MC4_DBUS_RCS1 1 /* 0-1, 8-bit */ -#define MC4_SDMODE_WRAP 0 /* 0-1 */ -#define MC4_SDMODE_BURST 2 /* 0-7 */ -#define MC4_ACTORW 3 /* 0-15 */ -#define MC4_BSTOPRE_L (MC_BSTOPRE & 0xf) - - LOADPTR (r3, MEM_CONT4_ADR) /* Set MCCR4 (FC) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \ - MC4_WMODE << 23 | MC4_INLINE << 22 | \ - MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \ - MC4_DBUS_RCS1 << 17 | \ - MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \ - MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \ - MC4_ACTORW << 4 | MC4_BSTOPRE_L) - cmpl 0, 0, r7, r9 /* Check for Kahlua 2 */ - bne notK2c - /* Turn on Kahlua2 extended ROM space */ - LOADPTR (r3, 0x00200000) - or r4, r4, r3 -notK2c: - stwbrx r4,0,r6 - -#ifdef INCLUDE_ECC - /*------- MEM_ERREN1 */ - - LOADPTR (r3, MEM_ERREN1_ADR) /* Set MEM_ERREN1 (c0) */ - stwbrx r3,0,r5 - lwbrx r4,0,r6 - ori r4,r4,4 /* Set MEM_PERR_EN */ - stwbrx r4,0,r6 -#endif /* INCLUDE_ECC */ - - /*------- MSAR/MEAR */ - - LOADPTR (r3, MEM_START1_ADR) /* Set MSAR1 (80) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xc0804000) - stwbrx r4,0,r6 - - LOADPTR (r3, MEM_START2_ADR) /* Set MSAR2 (84) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xc0804000) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_START1_ADR) /* Set MESAR1 (88) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000000) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_START2_ADR) /* Set MESAR2 (8c) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x01010101) - stwbrx r4,0,r6 - - LOADPTR (r3, MEM_END1_ADR) /* Set MEAR1 (90) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xffbf7f3f) - stwbrx r4,0,r6 - - LOADPTR (r3, MEM_END2_ADR) /* Set MEAR2 (94) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xffbf7f3f) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_END1_ADR) /* MEEAR1 (98) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000000) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_END2_ADR) /* MEEAR2 (9c) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x01010101) - stwbrx r4,0,r6 - - /*-------ODCR */ - - LOADPTR (r3, ODCR_ADR_X) /* Set ODCR */ - stwbrx r3,0,r5 - - li r4, 0x7f - stb r4, ODCR_SHIFT(r6) /* ODCR is at +3 offset */ - - /*-------MBEN */ - - LOADPTR (r3, MEM_EN_ADR) /* Set MBEN (a0) */ - stwbrx r3,0,r5 - li r4, 0x01 /* Enable bank 0 */ - stb r4, 0(r6) /* MBEN is at +0 offset */ - -#if 0 /* Jimmy: I think page made is broken */ - /*-------PGMAX */ - - LOADPTR (r3, MPM_ADR_X) - stwbrx r3,0,r5 - li r4, 0x32 - stb r4, MPM_SHIFT(r6) /* PAGE_MODE is at +3 offset */ -#endif - - /* Wait before initializing other registers */ - - lis r4,0x0001 - mtctr r4 - -KahluaX4wait200us: - bdnz KahluaX4wait200us - - /* Set MEMGO bit */ - - LOADPTR (r3, MEM_CONT1_ADR) /* MCCR1 (F0) |= PGMAX */ - stwbrx r3,0,r5 - lwbrx r4,0,r6 /* old MCCR1 */ - oris r4,r4,0x0008 /* MEMGO=1 */ - stwbrx r4, 0, r6 - - /* Wait again */ - - addis r4,r0,0x0002 - ori r4,r4,0xffff - - mtctr r4 - -KahluaX4wait8ref: - bdnz KahluaX4wait8ref - - sync - eieio - mtlr r11 - blr - -#else /* USE_V2_INIT */ - - -/* U-Boot works, but memory will not run reliably for all address ranges. - * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not - * initialized correctly. Could work if debugged. - */ -/* PCI Support routines */ - - .globl __pci_config_read_32 -__pci_config_read_32: - lis r4, 0xfec0 - stwbrx r3, r0, r4 - sync - lis r4, 0xfee0 - lwbrx r3, 0, r4 - blr - .globl __pci_config_read_16 -__pci_config_read_16: - lis r4, 0xfec0 - andi. r5, r3, 2 - stwbrx r3, r0, r4 - sync - oris r4, r5, 0xfee0 - lhbrx r3, r0, r4 - blr - .globl __pci_config_read_8 -__pci_config_read_8: - lis r4, 0xfec0 - andi. r5, r3, 3 - stwbrx r3, r0, r4 - sync - oris r4, r5, 0xfee0 - lbz r3, 0(4) - blr - .globl __pci_config_write_32 -__pci_config_write_32: - lis r5, 0xfec0 - stwbrx r3, r0, r5 - sync - lis r5, 0xfee0 - stwbrx r4, r0, r5 - sync - blr - .globl __pci_config_write_16 -__pci_config_write_16: - lis r5, 0xfec0 - andi. r6, r3, 2 - stwbrx r3, r0, 5 - sync - oris r5, r6, 0xfee0 - sthbrx r4, r0, r5 - sync - blr - .globl __pci_config_write_8 -__pci_config_write_8: - lis r5, 0xfec0 - andi. r6, r3, 3 - stwbrx r3, r0, r5 - sync - oris r5, r6, 0xfee0 - stb r4, 0(r5) - sync - blr - .globl in_8 -in_8: - oris r3, r3, 0xfe00 - lbz r3,0(r3) - blr - .globl in_16 -in_16: - oris r3, r3, 0xfe00 - lhbrx r3, 0, r3 - blr - .globl in_16_ne -in_16_ne: - oris r3, r3, 0xfe00 - lhzx r3, 0, r3 - blr - .globl in_32 -in_32: - oris r3, r3, 0xfe00 - lwbrx r3, 0, r3 - blr - .globl out_8 -out_8: - oris r3, r3, 0xfe00 - stb r4, 0(r3) - eieio - blr - .globl out_16 -out_16: - oris r3, r3, 0xfe00 - sthbrx r4, 0, r3 - eieio - blr - .globl out_16_ne -out_16_ne: - oris r3, r3, 0xfe00 - sth r4, 0(r3) - eieio - blr - .globl out_32 -out_32: - oris r3, r3, 0xfe00 - stwbrx r4, 0, r3 - eieio - blr - .globl read_8 -read_8: - lbz r3,0(r3) - blr - .globl read_16 -read_16: - lhbrx r3, 0, r3 - blr - .globl read_32 -read_32: - lwbrx r3, 0, r3 - blr - .globl read_32_ne -read_32_ne: - lwz r3, 0(r3) - blr - .globl write_8 -write_8: - stb r4, 0(r3) - eieio - blr - .globl write_16 -write_16: - sthbrx r4, 0, r3 - eieio - blr - .globl write_32 -write_32: - stwbrx r4, 0, r3 - eieio - blr - .globl write_32_ne -write_32_ne: - stw r4, 0(r3) - eieio - blr - - -.globl early_init_f - -early_init_f: - mflr r11 - lis r10, 0x8000 - - /* PCI Latency Timer */ - li r4, 0x0d - ori r3, r10, PLTR@l - bl __pci_config_write_8 - - /* Cache Line Size */ - li r4, 0x08 - ori r3, r10, PCLSR@l - bl __pci_config_write_8 - - /* PCI Cmd */ - li r4, 6 - ori r3, r10, PCICR@l - bl __pci_config_write_16 - -#if 1 - /* PCI Stat */ - ori r3, r10, PCISR@l - bl __pci_config_read_16 - ori r4, r4, 0xffff - ori r3, r10, PCISR@l - bl __pci_config_write_16 -#endif - - /* PICR1 */ - lis r4, 0xff14 - ori r4, r4, 0x1b98 - ori r3, r10, PICR1@l - bl __pci_config_write_32 - - - /* PICR2 */ - lis r4, 0x0404 - ori r4, r4, 0x0004 - ori r3, r10, PICR2@l - bl __pci_config_write_32 - - /* MIOCR1 */ - li r4, 0x04 - ori r3, r10, MIOCR1@l - bl __pci_config_write_8 - - /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */ - /* SDRAM_CLK_DEL (0x77)*/ - li r4, 0x10 - ori r3, r10, MIOCR2@l - bl __pci_config_write_8 - - /* EUMBBAR */ - lis r4, 0xfc00 - ori r3, r10, EUMBBAR@l - bl __pci_config_write_32 - - /* AMBOR */ - - /* Even if Address Map B is not being used (though it should), - * the memory DLL needs to be cleared/set/cleared before using memory. - */ - - ori r3, r10, AMBOR@l - bl __pci_config_read_8 /* get Current bits */ - - andi. r4, r4, 0xffdf - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Clear DLL_RESET */ - - ori r4, r4, 0x0020 - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Set DLL_RESET */ - - andi. r4, r4, 0xffdf - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Clear DLL_RESET */ - - /* ERCR1 */ - lis r4, 0x8040 /* Enable RCS2, use supplied timings */ - ori r4, r4, 0x8000 - ori r3, r10, ERCR1@l - bl __pci_config_write_32 - - /* ERCR2 */ - lis r4, 0x0000 /* Disable RCS3 parms */ - ori r4, r4, 0x0000 - ori r3, r10, ERCR2@l - bl __pci_config_write_32 - - /* ERCR3 */ - lis r4, 0x0000 /* RCS3 at 0x70000000, 64K bytes */ - ori r4, r4, 0x0004 - ori r3, r10, ERCR2@l - bl __pci_config_write_32 - - /* Preserve memgo bit */ - /* MCCR1 */ - -/* lis r4, 0x75a8 / Safe Local ROM = 11+3 clocks */ - lis r4, 0x75a0 /* Safe Local ROM = 11+3 clocks */ -/* lis r4, 0x73a0 / Fast Local ROM = 7+3 clocks */ -/* oris r4, r4, 0x0010 / Burst ROM/Flash enable */ -/* oris r4, r4, 0x0004 / Self-refresh enable */ - -/* ori r4,r4,0xFFFF / 16Mbit 2bank SDRAM */ -/* ori r4,r4,0xAAAA / 256Mbit 4bank SDRAM (8245 only) */ -/* ori r4,r4,0x5555 / 64Mbit 2bank SDRAM */ - ori r4,r4,0x0000 /* 64Mbit 4bank SDRAM */ - - ori r3, r10, MCCR1@l - bl __pci_config_write_32 - - /* MCCR2 */ - - lis r4,0x0000 -/* oris r4,r4,0x4000 / TS_WAIT_TIMER = 3 clocks */ - oris r4,r4,0x1000 /* ASRISE = 8 clocks */ - oris r4,r4,0x0080 /* ASFALL = 8 clocks */ -/* oris r4,r4,0x0010 / SDRAM Parity (else ECC) */ -/* oris r4,r4,0x0008 / Write parity check */ -/* oris r4,r4,0x0004 / SDRAM inline reads */ - - -/* Select a refresh rate; it needs to match the bus speed; if too */ -/* slow, data may be lost; if too fast, performance is lost. We */ -/* use the fastest value so we run at all speeds. */ -/* Refresh = (15600ns/busclk) - (213 (see UM)). */ - -/* ori r4,r4,0x1d2c / 133 MHz mem bus = 1867 */ -/* ori r4,r4,0x150c / 100 MHz mem bus = 1347 */ -/* ori r4,r4,0x10fc / 83 MHz mem bus = 1087 */ -/* ori r4,r4,0x0cc4 / 66 MHz mem bus = 817 */ - ori r4,r4,0x04cc /* 33 MHz mem bus (SAFE) = 307 */ -/* ori r4,r4,0x0002 / Reserve a page */ -/* ori r4,r4,0x0001 / RWM parity */ - - ori r3, r10, MCCR2@l - bl __pci_config_write_32 - - - /* MCCR3 */ - lis r4,0x0000 /* BSTOPRE_M = 7 (see A/N) */ - oris r4,r4,0x0500 /* REFREC = 8 clocks */ - ori r3, r10, MCCR3@l - bl __pci_config_write_32 - - /* MCCR4 */ /* Turn on registered buffer mode */ - lis r4, 0x2000 /* PRETOACT = 3 clocks */ - oris r4,r4,0x0400 /* ACTOPRE = 5 clocks */ -/* oris r4,r4,0x0080 / Enable 8-beat burst (32-bit bus) */ -/* oris r4,r4,0x0040 / Enable Inline ECC/Parity */ - oris r4,r4,0x0020 /* EXTROM enabled */ - oris r4,r4,0x0010 /* Registered buffers */ -/* oris r4,r4,0x0000 / BSTOPRE_U = 0 (see A/N) */ - oris r4,r4,0x0002 /* DBUS_SIZ[2] (8 bit on RCS1) */ - -/* ori r4,r4,0x8000 / Registered DIMMs */ - ori r4,r4,0x2000 /*CAS Latency (CL=3) (see RDLAT) */ -/* ori r4,r4,0x2000 / CAS Latency (CL=2) (see RDLAT) */ -/* ori r4,r4,0x0300 / Sequential wrap/8-beat burst */ - ori r4,r4,0x0200 /* Sequential wrap/4-beat burst */ - ori r4,r4,0x0030 /* ACTORW = 3 clocks */ - ori r4,r4,0x0009 /* BSTOPRE_L = 9 (see A/N) */ - - ori r3, r10, MCCR4@l - bl __pci_config_write_32 - - /* MSAR1 */ - lis r4, 0xc0804000@h - ori r4, r4, 0xc0804000@l - ori r3, r10, MSAR1@l - bl __pci_config_write_32 - - /* MSAR2 */ - lis r4, 0xc0804000@h - ori r4, r4, 0xc0804000@l - ori r3, r10, MSAR2@l - bl __pci_config_write_32 - - /* MESAR1 */ - lis r4, 0x00000000@h - ori r4, r4, 0x00000000@l - ori r3, r10, EMSAR1@l - bl __pci_config_write_32 - - /* MESAR2 */ - lis r4, 0x01010101@h - ori r4, r4, 0x01010101@l - ori r3, r10, EMSAR2@l - bl __pci_config_write_32 - - /* MEAR1 */ - lis r4, 0xffbf7f3f@h - ori r4, r4, 0xffbf7f3f@l - ori r3, r10, MEAR1@l - bl __pci_config_write_32 - - /* MEAR2 */ - lis r4, 0xffbf7f3f@h - ori r4, r4, 0xffbf7f3f@l - ori r3, r10, MEAR2@l - bl __pci_config_write_32 - - /* MEEAR1 */ - lis r4, 0x00000000@h - ori r4, r4, 0x00000000@l - ori r3, r10, EMEAR1@l - bl __pci_config_write_32 - - /* MEEAR2 */ - lis r4, 0x01010101@h - ori r4, r4, 0x01010101@l - ori r3, r10, EMEAR2@l - bl __pci_config_write_32 - - /* ODCR */ - li r4, 0x7f - ori r3, r10, ODCR@l - bl __pci_config_write_8 - - /* MBER */ - li r4, 0x01 - ori r3, r10, MBER@l - bl __pci_config_write_8 - - /* Page CTR aka PGMAX */ - li r4, 0x32 - ori r3, r10, 0x70 - bl __pci_config_write_8 - -#if 0 - /* CLK Drive */ - ori r4, r10, 0xfc01 /* Top bit will be ignored */ - ori r3, r10, 0x74 - bl __pci_config_write_16 -#endif - - /* delay */ - lis r7, 1 - mtctr r7 -label1: bdnz label1 - - /* Set memgo bit */ - /* MCCR1 */ - ori r3, r10, MCCR1@l - bl __pci_config_read_32 - lis r7, 0x0008 - or r4, r3, r7 - ori r3, r10, MCCR1@l - bl __pci_config_write_32 - - /* delay again */ - lis r7, 1 - mtctr r7 -label2: bdnz label2 -#if 0 -/* DEBUG: Infinite loop, write then read */ -loop: - lis r7, 0xffff - mtctr r7 - li r3, 0x5004 - lis r4, 0xa0a0 - ori r4, r4, 0x5050 - bl write_32_ne - li r3, 0x5004 - bl read_32_ne - bdnz loop -#endif - mtlr r11 - blr -#endif diff --git a/board/bmw/flash.c b/board/bmw/flash.c deleted file mode 100644 index 7fba174..0000000 --- a/board/bmw/flash.c +++ /dev/null @@ -1,779 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t * info, ulong dest, ulong data); - -#if 0 -static void flash_get_offsets (ulong base, flash_info_t * info); -#endif /* 0 */ - -/*flash command address offsets*/ - -#if 0 -#define ADDR0 (0x555) -#define ADDR1 (0x2AA) -#define ADDR3 (0x001) -#else -#define ADDR0 (0xAAA) -#define ADDR1 (0x555) -#define ADDR3 (0x001) -#endif - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -#if 0 -static int byte_parity_odd (unsigned char x) __attribute__ ((const)); -#endif /* 0 */ -static unsigned long flash_id (unsigned char mfct, unsigned char chip) - __attribute__ ((const)); - -typedef struct { - FLASH_WORD_SIZE extval; - unsigned short intval; -} map_entry; - -#if 0 -static int byte_parity_odd (unsigned char x) -{ - x ^= x >> 4; - x ^= x >> 2; - x ^= x >> 1; - return (x & 0x1) != 0; -} -#endif /* 0 */ - - -static unsigned long flash_id (unsigned char mfct, unsigned char chip) -{ - static const map_entry mfct_map[] = { - {(FLASH_WORD_SIZE) AMD_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, - {(FLASH_WORD_SIZE) FUJ_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, - {(FLASH_WORD_SIZE) STM_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, - {(FLASH_WORD_SIZE) MT_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, - {(FLASH_WORD_SIZE) INTEL_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, - {(FLASH_WORD_SIZE) INTEL_ALT_MANU, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} - }; - - static const map_entry chip_map[] = { - {AMD_ID_F040B, FLASH_AM040}, - {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} - }; - - const map_entry *p; - unsigned long result = FLASH_UNKNOWN; - - /* find chip id */ - for (p = &chip_map[0]; - p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) - if (p->extval == chip) { - result = FLASH_VENDMASK | p->intval; - break; - } - - /* find vendor id */ - for (p = &mfct_map[0]; - p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) - if (p->extval == mfct) { - result &= ~FLASH_VENDMASK; - result |= (unsigned long) p->intval << 16; - break; - } - - return result; -} - - -unsigned long flash_init (void) -{ - unsigned long i; - unsigned char j; - static const ulong flash_banks[] = CFG_FLASH_BANKS; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - - pflinfo->flash_id = FLASH_UNKNOWN; - pflinfo->size = 0; - pflinfo->sector_count = 0; - } - - for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - const unsigned long base_address = flash_banks[i]; - volatile FLASH_WORD_SIZE *const flash = - (FLASH_WORD_SIZE *) base_address; -#if 0 - volatile FLASH_WORD_SIZE *addr2; -#endif -#if 0 - /* write autoselect sequence */ - flash[0x5555] = 0xaa; - flash[0x2aaa] = 0x55; - flash[0x5555] = 0x90; -#else - flash[0xAAA << (3 * i)] = 0xaa; - flash[0x555 << (3 * i)] = 0x55; - flash[0xAAA << (3 * i)] = 0x90; -#endif - __asm__ __volatile__ ("sync"); - -#if 0 - pflinfo->flash_id = flash_id (flash[0x0], flash[0x1]); -#else - pflinfo->flash_id = - flash_id (flash[0x0], flash[0x2 + 14 * i]); -#endif - - switch (pflinfo->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - pflinfo->size = 0x00080000; - pflinfo->sector_count = 8; - for (j = 0; j < 8; j++) { - pflinfo->start[j] = - base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_STM800AB: - pflinfo->size = 0x00100000; - pflinfo->sector_count = 19; - pflinfo->start[0] = base_address; - pflinfo->start[1] = base_address + 0x4000; - pflinfo->start[2] = base_address + 0x6000; - pflinfo->start[3] = base_address + 0x8000; - for (j = 1; j < 16; j++) { - pflinfo->start[j + 3] = - base_address + 0x00010000 * j; - } -#if 0 - /* check for protected sectors */ - for (j = 0; j < pflinfo->sector_count; j++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE - *) (pflinfo->start[j]); - if (pflinfo->flash_id & FLASH_MAN_SST) - pflinfo->protect[j] = 0; - else - pflinfo->protect[j] = addr2[2] & 1; - } -#endif - break; - } - /* Protect monitor and environment sectors - */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - /* reset device to read mode */ - flash[0x0000] = 0xf0; - __asm__ __volatile__ ("sync"); - } - - return flash_info[0].size + flash_info[1].size; -} - -#if 0 -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} -#endif /* 0 */ - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if (info->flash_id != FLASH_UNKNOWN) { - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - mfct = "AMD"; - break; - case FLASH_MAN_FUJ: - mfct = "FUJITSU"; - break; - case FLASH_MAN_STM: - mfct = "STM"; - break; - case FLASH_MAN_SST: - mfct = "SST"; - break; - case FLASH_MAN_BM: - mfct = "Bright Microelectonics"; - break; - case FLASH_MAN_INTEL: - mfct = "Intel"; - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - type = "AM29F040B (512K * 8, uniform sector size)"; - break; - case FLASH_AM400B: - type = "AM29LV400B (4 Mbit, bottom boot sect)"; - break; - case FLASH_AM400T: - type = "AM29LV400T (4 Mbit, top boot sector)"; - break; - case FLASH_AM800B: - type = "AM29LV800B (8 Mbit, bottom boot sect)"; - break; - case FLASH_AM800T: - type = "AM29LV800T (8 Mbit, top boot sector)"; - break; - case FLASH_AM160T: - type = "AM29LV160T (16 Mbit, top boot sector)"; - break; - case FLASH_AM320B: - type = "AM29LV320B (32 Mbit, bottom boot sect)"; - break; - case FLASH_AM320T: - type = "AM29LV320T (32 Mbit, top boot sector)"; - break; - case FLASH_STM800AB: - type = "M29W800AB (8 Mbit, bottom boot sect)"; - break; - case FLASH_SST800A: - type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; - break; - case FLASH_SST160A: - type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; - break; - } - } - - printf ("\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, type, info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) { - unsigned long size; - unsigned int erased; - unsigned long *flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for (flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) - && erased; flash++) - erased = *flash == ~0x0UL; - - printf ("%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", info->protect[i] ? "RO" : " "); - } - - puts ("\n"); - return; -} - -#if 0 - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - - printf ("flash_get_size: \n"); - /* Write auto select command: read Manufacturer ID */ - eieio (); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90; - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - printf ("recognised manufacturer"); - - value = addr2[ADDR3]; /* device ID */ - debug ("\ndev_code=%x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf ("flash id %lx; sector count %x, size %lx\n", info->flash_id, - info->sector_count, info->size); - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - if (info->flash_id & FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -#endif - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info-> - start - [sect] - - - info-> - start - [0]) << - sh8b)); - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - udelay (30000); /* wait 30 ms */ - } else - addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - - info-> - start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/bmw/m48t59y.c b/board/bmw/m48t59y.c deleted file mode 100644 index d72c861..0000000 --- a/board/bmw/m48t59y.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and - * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD) - * registers which are used to set/get the internal date/time functions. - * - * This module implements Y2K compliance by taking full year numbers - * and translating back and forth from the TOD 2-digit year. - * - * NOTE: for proper interaction with an operating system, the TOD should - * be used to store Universal Coordinated Time (GMT) and timezone - * conversions should be used. - * - * Here is a diagram of the memory layout: - * - * +---------------------------------------------+ 0xffe0a000 - * | Non-volatile memory | . - * | | . - * | (8176 bytes of Non-volatile memory) | . - * | | . - * +---------------------------------------------+ 0xffe0bff0 - * | Flags | - * +---------------------------------------------+ 0xffe0bff1 - * | Unused | - * +---------------------------------------------+ 0xffe0bff2 - * | Alarm Seconds | - * +---------------------------------------------+ 0xffe0bff3 - * | Alarm Minutes | - * +---------------------------------------------+ 0xffe0bff4 - * | Alarm Date | - * +---------------------------------------------+ 0xffe0bff5 - * | Interrupts | - * +---------------------------------------------+ 0xffe0bff6 - * | WatchDog | - * +---------------------------------------------+ 0xffe0bff7 - * | Calibration | - * +---------------------------------------------+ 0xffe0bff8 - * | Seconds | - * +---------------------------------------------+ 0xffe0bff9 - * | Minutes | - * +---------------------------------------------+ 0xffe0bffa - * | Hours | - * +---------------------------------------------+ 0xffe0bffb - * | Day | - * +---------------------------------------------+ 0xffe0bffc - * | Date | - * +---------------------------------------------+ 0xffe0bffd - * | Month | - * +---------------------------------------------+ 0xffe0bffe - * | Year (2 digits only) | - * +---------------------------------------------+ 0xffe0bfff - */ -#include -#include -#include "bmw.h" - -/* - * Imported from mousse.h: - * - * TOD_REG_BASE Base of m48t59y TOD registers - * SYS_TOD_UNPROTECT() Disable NVRAM write protect - * SYS_TOD_PROTECT() Re-enable NVRAM write protect - */ - -#define YEAR 0xf -#define MONTH 0xe -#define DAY 0xd -#define DAY_OF_WEEK 0xc -#define HOUR 0xb -#define MINUTE 0xa -#define SECOND 0x9 -#define CONTROL 0x8 -#define WATCH 0x7 -#define INTCTL 0x6 -#define WD_DATE 0x5 -#define WD_HOUR 0x4 -#define WD_MIN 0x3 -#define WD_SEC 0x2 -#define _UNUSED 0x1 -#define FLAGS 0x0 - -#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE) - -int m48_tod_init(void) -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] = 0; - M48_ADDR[WATCH] = 0; - M48_ADDR[INTCTL] = 0; - - /* - * If the oscillator is currently stopped (as on a new part shipped - * from the factory), start it running. - * - * Here is an example of the TOD bytes on a brand new M48T59Y part: - * 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01 - */ - - if (M48_ADDR[SECOND] & 0x80) - M48_ADDR[SECOND] = 0; - - /* Is battery low */ - if ( M48_ADDR[FLAGS] & 0x10) { - printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n"); - } - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * m48_tod_set - */ - -static int to_bcd(int value) -{ - return value / 10 * 16 + value % 10; -} - -static int from_bcd(int value) -{ - return value / 16 * 10 + value % 16; -} - -static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */ -{ - static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4}; - y -= m < 3; - return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_set(int year, /* 1980-2079 */ - int month, /* 01-12 */ - int day, /* 01-31 */ - int hour, /* 00-23 */ - int minute, /* 00-59 */ - int second) /* 00-59 */ - -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */ - - M48_ADDR[YEAR] = to_bcd(year % 100); - M48_ADDR[MONTH] = to_bcd(month); - M48_ADDR[DAY] = to_bcd(day); - M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1; - M48_ADDR[HOUR] = to_bcd(hour); - M48_ADDR[MINUTE] = to_bcd(minute); - M48_ADDR[SECOND] = to_bcd(second); - - M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_get(int *year, /* 1980-2079 */ - int *month, /* 01-12 */ - int *day, /* 01-31 */ - int *hour, /* 00-23 */ - int *minute, /* 00-59 */ - int *second) /* 00-59 */ -{ - int y; - - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */ - - y = from_bcd(M48_ADDR[YEAR]); - *year = y < 80 ? 2000 + y : 1900 + y; - *month = from_bcd(M48_ADDR[MONTH]); - *day = from_bcd(M48_ADDR[DAY]); - /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */ - *hour = from_bcd(M48_ADDR[HOUR]); - *minute = from_bcd(M48_ADDR[MINUTE]); - *second = from_bcd(M48_ADDR[SECOND] & 0x7f); - - M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -int m48_tod_get_second(void) -{ - return from_bcd(M48_ADDR[SECOND] & 0x7f); -} - -/* - * Watchdog function - * - * If usec is 0, the watchdog timer is disarmed. - * - * If usec is non-zero, the watchdog timer is armed (or re-armed) for - * approximately usec microseconds (if the exact requested usec is - * not supported by the chip, the next higher available value is used). - * - * Minimum watchdog timeout = 62500 usec - * Maximum watchdog timeout = 124 sec (124000000 usec) - */ - -void m48_watchdog_arm(int usec) -{ - int mpy, res; - - SYS_TOD_UNPROTECT(); - - if (usec == 0) { - res = 0; - mpy = 0; - } else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */ - res = 0; - mpy = (usec + 62499) / 62500; - } else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */ - res = 1; - mpy = (usec + 249999) / 250000; - } else if (usec < 32000000) { /* Resolution: 1s if below 32s */ - res = 2; - mpy = (usec + 999999) / 1000000; - } else { /* Resolution: 4s up to 124s */ - res = 3; - mpy = (usec + 3999999) / 4000000; - if (mpy > 31) - mpy = 31; - } - - M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */ - mpy << 2 | - res); - - SYS_TOD_PROTECT(); -} - -/* - * U-Boot RTC support. - */ -void -rtc_get( struct rtc_time *tmp ) -{ - m48_tod_get(&tmp->tm_year, - &tmp->tm_mon, - &tmp->tm_mday, - &tmp->tm_hour, - &tmp->tm_min, - &tmp->tm_sec); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif -} - -void -rtc_set( struct rtc_time *tmp ) -{ - m48_tod_set(tmp->tm_year, /* 1980-2079 */ - tmp->tm_mon, /* 01-12 */ - tmp->tm_mday, /* 01-31 */ - tmp->tm_hour, /* 00-23 */ - tmp->tm_min, /* 00-59 */ - tmp->tm_sec); /* 00-59 */ - -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - -} - -void -rtc_reset (void) -{ - m48_tod_init(); -} diff --git a/board/bmw/m48t59y.h b/board/bmw/m48t59y.h deleted file mode 100644 index 717300d..0000000 --- a/board/bmw/m48t59y.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __M48_T59_Y_H -#define __M48_T59_Y_H - -/* - * M48 T59Y -Timekeeping Battery backed SRAM. - */ - -int m48_tod_init(void); - -int m48_tod_set(int year, - int month, - int day, - int hour, - int minute, - int second); - -int m48_tod_get(int *year, - int *month, - int *day, - int *hour, - int *minute, - int *second); - -int m48_tod_get_second(void); - -void m48_watchdog_arm(int usec); - -#endif /*!__M48_T59_Y_H */ diff --git a/board/bmw/ns16550.c b/board/bmw/ns16550.c deleted file mode 100644 index 7064567..0000000 --- a/board/bmw/ns16550.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * COM1 NS16550 support - * originally from linux source (arch/ppc/boot/ns16550.c) - * modified to use CFG_ISA_MEM and new defines - */ - -#include -#include "ns16550.h" - -typedef struct NS16550 *NS16550_t; - -const NS16550_t COM_PORTS[] = - { (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500), -(NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) }; - -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) -{ - volatile struct NS16550 *com_port; - - com_port = (struct NS16550 *) COM_PORTS[chan]; - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ - return (com_port); -} - -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor) -{ - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ -} - -void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c) -{ - while ((com_port->lsr & LSR_THRE) == 0); - com_port->thr = c; -} - -unsigned char NS16550_getc (volatile struct NS16550 *com_port) -{ - while ((com_port->lsr & LSR_DR) == 0); - return (com_port->rbr); -} - -int NS16550_tstc (volatile struct NS16550 *com_port) -{ - return ((com_port->lsr & LSR_DR) != 0); -} diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h deleted file mode 100644 index 104f45b..0000000 --- a/board/bmw/ns16550.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * NS16550 Serial Port - * originally from linux source (arch/ppc/boot/ns16550.h) - * modified slightly to - * have addresses as offsets from CFG_ISA_BASE - * added a few more definitions - * added prototypes for ns16550.c - * reduced no of com ports to 2 - * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - * further modified to support the 8245 duart - * modifications (c) Paul Jimenez, Musenki, Inc. 2001. - */ - - -struct NS16550 { - unsigned char rbrthrdlb; /* 0 */ - unsigned char ierdmb; /* 1 */ - unsigned char iirfcrafr; /* 2 */ - unsigned char lcr; /* 3 */ - unsigned char mcr; /* 4 */ - unsigned char lsr; /* 5 */ - unsigned char msr; /* 6 */ - unsigned char scr; /* 7 */ - unsigned char reserved[2]; /* 8 & 9 */ - unsigned char dsr; /* 10 */ - unsigned char dcr; /* 11 */ -}; - - -#define rbr rbrthrdlb -#define thr rbrthrdlb -#define dll rbrthrdlb -#define ier ierdmb -#define dlm ierdmb -#define iir iirfcrafr -#define fcr iirfcrafr -#define afr iirfcrafr - -#define FCR_FIFO_EN 0x01 /*fifo enable */ -#define FCR_RXSR 0x02 /*reciever soft reset */ -#define FCR_TXSR 0x04 /*transmitter soft reset */ -#define FCR_DMS 0x08 /* DMA Mode Select */ - -#define MCR_RTS 0x02 /* Readyu to Send */ -#define MCR_LOOP 0x10 /* Local loopback mode enable */ -/* #define MCR_DTR 0x01 noton 8245 duart */ -/* #define MCR_DMA_EN 0x04 noton 8245 duart */ -/* #define MCR_TX_DFR 0x08 noton 8245 duart */ - -#define LCR_WLS_MSK 0x03 /* character length slect mask */ -#define LCR_WLS_5 0x00 /* 5 bit character length */ -#define LCR_WLS_6 0x01 /* 6 bit character length */ -#define LCR_WLS_7 0x02 /* 7 bit character length */ -#define LCR_WLS_8 0x03 /* 8 bit character length */ -#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define LCR_PEN 0x08 /* Parity eneble */ -#define LCR_EPS 0x10 /* Even Parity Select */ -#define LCR_STKP 0x20 /* Stick Parity */ -#define LCR_SBRK 0x40 /* Set Break */ -#define LCR_BKSE 0x80 /* Bank select enable - aka DLAB on 8245 */ - -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -/* useful defaults for LCR*/ -#define LCR_8N1 0x03 - - -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor); -void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c); -unsigned char NS16550_getc (volatile struct NS16550 *com_port); -int NS16550_tstc (volatile struct NS16550 *com_port); -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor); diff --git a/board/bmw/serial.c b/board/bmw/serial.c deleted file mode 100644 index f36a41b..0000000 --- a/board/bmw/serial.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "ns16550.h" - -#if CONFIG_CONS_INDEX == 1 -static struct NS16550 *console = - (struct NS16550 *) (CFG_EUMB_ADDR + 0x4500); -#elif CONFIG_CONS_INDEX == 2 -static struct NS16550 *console = - (struct NS16550 *) (CFG_EUMB_ADDR + 0x4500); -#else -#error no valid console defined -#endif - -extern ulong get_bus_freq (ulong); - -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = gd->bus_clk / 16 / gd->baudrate; - - NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor); - - return (0); -} - -void serial_putc (const char c) -{ - if (c == '\n') { - serial_putc ('\r'); - } - NS16550_putc (console, c); -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - - -int serial_getc (void) -{ - return NS16550_getc (console); -} - -int serial_tstc (void) -{ - return NS16550_tstc (console); -} - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate; - - NS16550_reinit (console, clock_divisor); -} diff --git a/board/bmw/u-boot.lds b/board/bmw/u-boot.lds deleted file mode 100644 index eaee3fd..0000000 --- a/board/bmw/u-boot.lds +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/c2mon/Makefile b/board/c2mon/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/c2mon/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/c2mon/c2mon.c b/board/c2mon/c2mon.c deleted file mode 100644 index ca8eb0c..0000000 --- a/board/c2mon/c2mon.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - unsigned char *s = (unsigned char *)getenv ("serial#"); - - puts ("Board: TTTech C2MON "); - - for (; s && *s; ++s) { - if (*s == ' ') - break; - putc (*s); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long reg; - long int size8, size9; - long int size = 0; - - upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 2 the SDRAM bank 2 at physical address 0. - */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; - - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, - SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, - SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type - * For types > 128 MBit leave it at the current (fast) rate - */ - if (size < 0x02000000) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/c2mon/config.mk b/board/c2mon/config.mk deleted file mode 100644 index c2d21e2..0000000 --- a/board/c2mon/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TTTech C2MON boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/c2mon/flash.c b/board/c2mon/flash.c deleted file mode 100644 index b2be21c..0000000 --- a/board/c2mon/flash.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds deleted file mode 100644 index cdf550f..0000000 --- a/board/c2mon/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug deleted file mode 100644 index 3165d56..0000000 --- a/board/c2mon/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/canmb/Makefile b/board/canmb/Makefile deleted file mode 100644 index 607833f..0000000 --- a/board/canmb/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o -#../common/flash.o ../common/vpd.o ../common/am79c874.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c deleted file mode 100644 index 1782b31..0000000 --- a/board/canmb/canmb.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -#include "mt48lc16m32s2-75.h" -#endif - -#ifndef CFG_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. - */ - -#if defined(CONFIG_MPC5200) -long int initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CFG_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CFG_RAMBOOT */ - - return dramsize + dramsize2; -} - -#elif defined(CONFIG_MGT5100) - -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CFG_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CFG_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - -int checkboard (void) -{ - puts ("Board: CANMB\n"); - return 0; -} - -int board_early_init_r (void) -{ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - *(vu_long *)MPC5XXX_BOOTCS_START = - *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE); - *(vu_long *)MPC5XXX_BOOTCS_STOP = - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); - return 0; -} diff --git a/board/canmb/config.mk b/board/canmb/config.mk deleted file mode 100644 index a163b34..0000000 --- a/board/canmb/config.mk +++ /dev/null @@ -1,39 +0,0 @@ -# -# (C) Copyright 2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2003 -# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# CANMB board -# -# allowed and functional TEXT_BASE values: -# -# 0xfe000000 low boot at 0x00000100 (default board setting) -# 0x00100000 RAM load and test -# - -TEXT_BASE = 0xFE000000 -#TEXT_BASE = 0x00100000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h deleted file mode 100644 index ffdf039..0000000 --- a/board/canmb/mt48lc16m32s2-75.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 0 /* is SDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/canmb/u-boot.lds b/board/canmb/u-boot.lds deleted file mode 100644 index 88dc118..0000000 --- a/board/canmb/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cds/common/cadmus.c b/board/cds/common/cadmus.c deleted file mode 100644 index 5f86de5..0000000 --- a/board/cds/common/cadmus.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include - - -/* - * CADMUS Board System Registers - */ -#ifndef CFG_CADMUS_BASE_REG -#define CFG_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) -#endif - -typedef struct cadmus_reg { - u_char cm_ver; /* Board version */ - u_char cm_csr; /* General control/status */ - u_char cm_rst; /* Reset control */ - u_char cm_hsclk; /* High speed clock */ - u_char cm_hsxclk; /* High speed clock extended */ - u_char cm_led; /* LED data */ - u_char cm_pci; /* PCI control/status */ - u_char cm_dma; /* DMA control */ - u_char cm_reserved[248]; /* Total 256 bytes */ -} cadmus_reg_t; - - -unsigned int -get_board_version(void) -{ - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; - - return cadmus->cm_ver; -} - - -unsigned long -get_clock_freq(void) -{ - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; - - uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ - - if (pci1_speed == 0) { - return 33000000; - } else if (pci1_speed == 1) { - return 66000000; - } else { - /* Really, unknown. Be safe? */ - return 33000000; - } -} - - -unsigned int -get_pci_slot(void) -{ - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; - - /* - * PCI slot in USER bits CSR[6:7] by convention. - */ - return ((cadmus->cm_csr >> 6) & 0x3) + 1; -} - - -unsigned int -get_pci_dual(void) -{ - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; - - /* - * PCI DUAL in CM_PCI[3] - */ - return cadmus->cm_pci & 0x10; -} diff --git a/board/cds/common/cadmus.h b/board/cds/common/cadmus.h deleted file mode 100644 index 217ea64..0000000 --- a/board/cds/common/cadmus.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CADMUS_H_ -#define __CADMUS_H_ - - -/* - * CADMUS Board System Register interface. - */ - -/* - * Returns board version register. - */ -extern unsigned int get_board_version(void); - -/* - * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ. - */ -extern unsigned long get_clock_freq(void); - - -/* - * Returns 1 - 4, as found in the USER CSR[6:7] bits. - */ -extern unsigned int get_pci_slot(void); - - -/* - * Returns PCI DUAL as found in CM_PCI[3]. - */ -extern unsigned int get_pci_dual(void); - - -#endif /* __CADMUS_H_ */ diff --git a/board/cds/common/eeprom.c b/board/cds/common/eeprom.c deleted file mode 100644 index 5034e0c..0000000 --- a/board/cds/common/eeprom.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -#include "eeprom.h" - - -typedef struct { - char idee_pcbid[4]; /* "CCID" for CDC v1.X */ - u8 idee_major; - u8 idee_minor; - char idee_serial[10]; - char idee_errata[2]; - char idee_date[8]; /* yyyymmdd */ - /* The rest of the EEPROM space is reserved */ -} id_eeprom_t; - - -unsigned int -get_cpu_board_revision(void) -{ - uint major = 0; - uint minor = 0; - - id_eeprom_t id_eeprom; - - i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, - (uchar *) &id_eeprom, sizeof(id_eeprom)); - - major = id_eeprom.idee_major; - minor = id_eeprom.idee_minor; - - if (major == 0xff && minor == 0xff) { - major = minor = 0; - } - - return MPC85XX_CPU_BOARD_REV(major,minor); -} diff --git a/board/cds/common/eeprom.h b/board/cds/common/eeprom.h deleted file mode 100644 index 12a0789..0000000 --- a/board/cds/common/eeprom.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __EEPROM_H_ -#define __EEPROM_H_ - - -/* - * EEPROM Board System Register interface. - */ - - -/* - * CPU Board Revision - */ -#define MPC85XX_CPU_BOARD_REV(maj, min) ((((maj)&0xff) << 8) | ((min) & 0xff)) -#define MPC85XX_CPU_BOARD_MAJOR(rev) (((rev) >> 8) & 0xff) -#define MPC85XX_CPU_BOARD_MINOR(rev) ((rev) & 0xff) - -#define MPC85XX_CPU_BOARD_REV_UNKNOWN MPC85XX_CPU_BOARD_REV(0,0) -#define MPC85XX_CPU_BOARD_REV_1_0 MPC85XX_CPU_BOARD_REV(1,0) -#define MPC85XX_CPU_BOARD_REV_1_1 MPC85XX_CPU_BOARD_REV(1,1) - -/* - * Returns CPU board revision register as a 16-bit value with - * the Major in the high byte, and Minor in the low byte. - */ -extern unsigned int get_cpu_board_revision(void); - - -#endif /* __CADMUS_H_ */ diff --git a/board/cds/mpc8541cds/Makefile b/board/cds/mpc8541cds/Makefile deleted file mode 100644 index 0d4abbd..0000000 --- a/board/cds/mpc8541cds/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor. -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o \ - ../common/cadmus.o \ - ../common/eeprom.o - -SOBJS := init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/cds/mpc8541cds/config.mk b/board/cds/mpc8541cds/config.mk deleted file mode 100644 index 17cc8bc..0000000 --- a/board/cds/mpc8541cds/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8541cds board -# -TEXT_BASE = 0xfff80000 - -PLATFORM_CPPFLAGS += -DCONFIG_E500=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8541=1 diff --git a/board/cds/mpc8541cds/init.S b/board/cds/mpc8541cds/init.S deleted file mode 100644 index 53dcd0d..0000000 --- a/board/cds/mpc8541cds/init.S +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, sharen, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long TLB1_MAS0(1, 0, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - .long TLB1_MAS0(1, 5, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long TLB1_MAS0(1, 6, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers - */ - .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) - .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) - - entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * The defines below are 1-off of the actual LAWAR0 usage. - * So LAWAR3 define uses the LAWAR4 register in the ECM. - */ - -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ -#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - - .section .bootpg, "ax" - .globl law_entry - -law_entry: - entry_start - .long 6 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 - entry_end diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c deleted file mode 100644 index 6b8aa68..0000000 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ /dev/null @@ -1,504 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#include "../common/cadmus.h" -#include "../common/eeprom.h" - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -extern long int spd_sdram(void); - -void local_bus_init(void); -void sdram_init(void); - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - - /* PCI slot in USER bits CSR[6:7] by convention. */ - uint pci_slot = get_pci_slot (); - - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ - uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - - uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - - uint cpu_board_rev = get_cpu_board_revision (); - - printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", - get_board_version (), pci_slot); - - printf ("CPU Board Revision %d.%d (0x%04x)\n", - MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), - MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - - printf (" PCI1: %d bit, %s MHz, %s\n", - (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", - pci1_clk_sel ? "sync" : "async"); - - if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf (" PCI2: disabled\n"); - } - - /* - * Initialize local bus. - */ - local_bus_init (); - - return 0; -} - -long int -initdram(int board_type) -{ - long dram_size = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur= &immap->im_gur; - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - dram_size = spd_sdram(); - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - uint temp_lbcdll; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr |= 0x80000000; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr &= (~0x80000000); /* DLL Enabled */ - - } else { - lbc->lcrr &= (~0x8000000); /* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void -sdram_init(void) -{ -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - - uint idx; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - uint cpu_board_rev; - uint lsdmr_common; - - puts(" SDRAM: "); - - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - - /* - * Setup SDRAM Base and Option Registers - */ - lbc->or2 = CFG_OR2_PRELIM; - asm("msync"); - - lbc->br2 = CFG_BR2_PRELIM; - asm("msync"); - - lbc->lbcr = CFG_LBC_LBCR; - asm("msync"); - - - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; - asm("msync"); - - /* - * Determine which address lines to use baed on CPU board rev. - */ - cpu_board_rev = get_cpu_board_revision(); - lsdmr_common = CFG_LBC_LSDMR_COMMON; - if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { - lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; - } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { - lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; - } else { - /* - * Assume something unable to identify itself is - * really old, and likely has lines 16/17 mapped. - */ - lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; - } - - /* - * Issue PRECHARGE ALL command. - */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue 8 AUTO REFRESH commands. - */ - for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - } - - /* - * Issue 8 MODE-set command. - */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue NORMAL OP command. - */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(200); /* Overkill. Must wait > 200 bus cycles */ - -#endif /* enable SDRAM init */ -} - -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - -#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxcds_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - - pci_mpc85xx_init(&hose); -#endif -} diff --git a/board/cds/mpc8541cds/u-boot.lds b/board/cds/mpc8541cds/u-boot.lds deleted file mode 100644 index 1bea007..0000000 --- a/board/cds/mpc8541cds/u-boot.lds +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - board/cds/mpc8541cds/init.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc85xx/start.o (.text) - board/cds/mpc8541cds/init.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile deleted file mode 100644 index 0d4abbd..0000000 --- a/board/cds/mpc8548cds/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor. -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o \ - ../common/cadmus.o \ - ../common/eeprom.o - -SOBJS := init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/cds/mpc8548cds/config.mk b/board/cds/mpc8548cds/config.mk deleted file mode 100644 index 242a676..0000000 --- a/board/cds/mpc8548cds/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8548cds board -# -TEXT_BASE = 0xfff80000 - -PLATFORM_CPPFLAGS += -DCONFIG_E500=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S deleted file mode 100644 index 53dcd0d..0000000 --- a/board/cds/mpc8548cds/init.S +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, sharen, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long TLB1_MAS0(1, 0, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - .long TLB1_MAS0(1, 5, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long TLB1_MAS0(1, 6, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers - */ - .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) - .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) - - entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * The defines below are 1-off of the actual LAWAR0 usage. - * So LAWAR3 define uses the LAWAR4 register in the ECM. - */ - -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ -#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - - .section .bootpg, "ax" - .globl law_entry - -law_entry: - entry_start - .long 6 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 - entry_end diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c deleted file mode 100644 index 5bc0890..0000000 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include "../common/cadmus.h" -#include "../common/eeprom.h" - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -extern long int spd_sdram(void); - -void local_bus_init(void); -void sdram_init(void); - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - - /* PCI slot in USER bits CSR[6:7] by convention. */ - uint pci_slot = get_pci_slot (); - - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ - uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - - uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - - uint cpu_board_rev = get_cpu_board_revision (); - - printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", - get_board_version (), pci_slot); - - printf ("CPU Board Revision %d.%d (0x%04x)\n", - MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), - MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - - printf (" PCI1: %d bit, %s MHz, %s\n", - (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", - pci1_clk_sel ? "sync" : "async"); - - if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf (" PCI2: disabled\n"); - } - - /* - * Initialize local bus. - */ - local_bus_init (); - - - /* - * Hack TSEC 3 and 4 IO voltages. - */ - gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ - - return 0; -} - -long int -initdram(int board_type) -{ - long dram_size = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur= &immap->im_gur; - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - dram_size = spd_sdram(); - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - gur->lbiuiplldcr1 = 0x00078080; - if (clkdiv == 16) { - gur->lbiuiplldcr0 = 0x7c0f1bf0; - } else if (clkdiv == 8) { - gur->lbiuiplldcr0 = 0x6c0f1bf0; - } else if (clkdiv == 4) { - gur->lbiuiplldcr0 = 0x5c0f1bf0; - } - - lbc->lcrr |= 0x00030000; - - asm("sync;isync;msync"); -} - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void -sdram_init(void) -{ -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - - uint idx; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - uint cpu_board_rev; - uint lsdmr_common; - - puts(" SDRAM: "); - - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - - /* - * Setup SDRAM Base and Option Registers - */ - lbc->or2 = CFG_OR2_PRELIM; - asm("msync"); - - lbc->br2 = CFG_BR2_PRELIM; - asm("msync"); - - lbc->lbcr = CFG_LBC_LBCR; - asm("msync"); - - - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; - asm("msync"); - - /* - * MPC8548 uses "new" 15-16 style addressing. - */ - cpu_board_rev = get_cpu_board_revision(); - lsdmr_common = CFG_LBC_LSDMR_COMMON; - lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; - - /* - * Issue PRECHARGE ALL command. - */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue 8 AUTO REFRESH commands. - */ - for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - } - - /* - * Issue 8 MODE-set command. - */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue NORMAL OP command. - */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(200); /* Overkill. Must wait > 200 bus cycles */ - -#endif /* enable SDRAM init */ -} - -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - -#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxcds_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - - pci_mpc85xx_init(&hose); -#endif -} diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds deleted file mode 100644 index 2c8fe96..0000000 --- a/board/cds/mpc8548cds/u-boot.lds +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - board/cds/mpc8548cds/init.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc85xx/start.o (.text) - board/cds/mpc8548cds/init.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile deleted file mode 100644 index 0d4abbd..0000000 --- a/board/cds/mpc8555cds/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor. -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o \ - ../common/cadmus.o \ - ../common/eeprom.o - -SOBJS := init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/cds/mpc8555cds/config.mk b/board/cds/mpc8555cds/config.mk deleted file mode 100644 index 5dcaa77..0000000 --- a/board/cds/mpc8555cds/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8555cds board -# -TEXT_BASE = 0xfff80000 - -PLATFORM_CPPFLAGS += -DCONFIG_E500=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8555=1 diff --git a/board/cds/mpc8555cds/init.S b/board/cds/mpc8555cds/init.S deleted file mode 100644 index 53dcd0d..0000000 --- a/board/cds/mpc8555cds/init.S +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright 2002,2003, Motorola Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, sharen, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long TLB1_MAS0(1, 0, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - .long TLB1_MAS0(1, 5, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long TLB1_MAS0(1, 6, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers - */ - .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) - .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) - - entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * The defines below are 1-off of the actual LAWAR0 usage. - * So LAWAR3 define uses the LAWAR4 register in the ECM. - */ - -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ -#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - - .section .bootpg, "ax" - .globl law_entry - -law_entry: - entry_start - .long 6 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 - entry_end diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c deleted file mode 100644 index 18adf5b..0000000 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ /dev/null @@ -1,501 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#include "../common/cadmus.h" -#include "../common/eeprom.h" - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -extern long int spd_sdram(void); - -void local_bus_init(void); -void sdram_init(void); - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - - /* PCI slot in USER bits CSR[6:7] by convention. */ - uint pci_slot = get_pci_slot (); - - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ - uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - - uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - - uint cpu_board_rev = get_cpu_board_revision (); - - printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", - get_board_version (), pci_slot); - - printf ("CPU Board Revision %d.%d (0x%04x)\n", - MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), - MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - - printf (" PCI1: %d bit, %s MHz, %s\n", - (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", - pci1_clk_sel ? "sync" : "async"); - - if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf (" PCI2: disabled\n"); - } - - /* - * Initialize local bus. - */ - local_bus_init (); - - return 0; -} - -long int -initdram(int board_type) -{ - long dram_size = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur= &immap->im_gur; - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - dram_size = spd_sdram(); - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - uint temp_lbcdll; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr |= 0x80000000; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr &= (~0x80000000); /* DLL Enabled */ - - } else { - lbc->lcrr &= (~0x8000000); /* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void -sdram_init(void) -{ -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - - uint idx; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - uint cpu_board_rev; - uint lsdmr_common; - - puts(" SDRAM: "); - - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - - /* - * Setup SDRAM Base and Option Registers - */ - lbc->or2 = CFG_OR2_PRELIM; - asm("msync"); - - lbc->br2 = CFG_BR2_PRELIM; - asm("msync"); - - lbc->lbcr = CFG_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; - asm("msync"); - - /* - * Determine which address lines to use baed on CPU board rev. - */ - cpu_board_rev = get_cpu_board_revision(); - lsdmr_common = CFG_LBC_LSDMR_COMMON; - if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { - lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; - } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { - lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; - } else { - /* - * Assume something unable to identify itself is - * really old, and likely has lines 16/17 mapped. - */ - lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; - } - - /* - * Issue PRECHARGE ALL command. - */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue 8 AUTO REFRESH commands. - */ - for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - } - - /* - * Issue 8 MODE-set command. - */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue NORMAL OP command. - */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(200); /* Overkill. Must wait > 200 bus cycles */ - -#endif /* enable SDRAM init */ -} - -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - -#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxcds_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - - pci_mpc85xx_init(&hose); -#endif -} diff --git a/board/cds/mpc8555cds/u-boot.lds b/board/cds/mpc8555cds/u-boot.lds deleted file mode 100644 index 2aa2ad7..0000000 --- a/board/cds/mpc8555cds/u-boot.lds +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - board/cds/mpc8555cds/init.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc85xx/start.o (.text) - board/cds/mpc8555cds/init.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cerf250/Makefile b/board/cerf250/Makefile deleted file mode 100644 index 83e3ba4..0000000 --- a/board/cerf250/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := cerf250.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c deleted file mode 100644 index cc1bc16..0000000 --- a/board/cerf250/cerf250.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of cerf PXA Board */ - gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; - - return 0; -} diff --git a/board/cerf250/config.mk b/board/cerf250/config.mk deleted file mode 100644 index 1a86cc9..0000000 --- a/board/cerf250/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -# -# Cerf board with PXA250 cpu -# -# -TEXT_BASE = 0xa3080000 diff --git a/board/cerf250/flash.c b/board/cerf250/flash.c deleted file mode 100644 index ba82892..0000000 --- a/board/cerf250/flash.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/cerf250/lowlevel_init.S b/board/cerf250/lowlevel_init.S deleted file mode 100644 index c9b68d7..0000000 --- a/board/cerf250/lowlevel_init.S +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - - -/* - * Memory setup - */ - -.globl lowlevel_init -lowlevel_init: - - /* Set up GPIO pins first ----------------------------------------- */ - - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1, =MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field, set SDRAM clocks free running */ - - ldr r3, =CFG_MDREFR_VAL - ldr r2, =0xFFF - and r3, r3, r2 - - ldr r0, [r1, #MDREFR_OFFSET] - bic r0, r0, r2 - bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE) - orr r0, r0, r3 - - str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - /* FIXME: we use async mode for now */ - - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - /* set MDREFR according to user define with exception of a few bits */ - - ldr r4, =CFG_MDREFR_VAL - ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\ - MDREFR_K2RUN |MDREFR_K2DB2) - and r4, r4, r2 - bic r0, r0, r2 - orr r0, r0, r4 - - str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r0, [r1, #MDREFR_OFFSET] - - /* Step 4b: de-assert MDREFR:SLFRSH. */ - - bic r0, r0, #(MDREFR_SLFRSH) - str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r0, [r1, #MDREFR_OFFSET] - - - /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */ - - ldr r4, =CFG_MDREFR_VAL - ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \ - MDREFR_K1FREE | MDREFR_K2FREE) - and r4, r4, r2 - orr r0, r0, r4 - str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r0, [r1, #MDREFR_OFFSET] - - - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ - /* configure but not enable each SDRAM partition pair. */ - - ldr r4, =CFG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - ldr r3, =CFG_DRAM_BASE -.rept 8 - str r2, [r3] -.endr - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* (MDCNFG:DEx set to 1). */ - - ldr r3, [r1, #MDCNFG_OFFSET] - orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) - str r3, [r1, #MDCNFG_OFFSET] - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - - /* We are finished with Intel's memory controller initialisation */ - - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - - /* Turn Off ALL on-chip peripheral clocks for re-configuration */ - /* Note: See label 'ENABLECLKS' for the re-enabling */ - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - - /* default value in case no valid rotary switch setting is found */ - ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ - - /* ... and write the core clock config register */ - ldr r1, =CCCR - str r2, [r1] - -#ifdef RTC - /* enable the 32Khz oscillator for RTC and PowerManager */ - - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#endif - - /* ---------------------------------------------------------------- */ - /* */ - /* ---------------------------------------------------------------- */ - - /* Save SDRAM size */ - ldr r1, =DRAM_SIZE - str r8, [r1] - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - - /* FIXME */ - -#define NODEBUG -#ifdef NODEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ - -#endif - - /* ---------------------------------------------------------------- */ - /* End lowlevel_init */ - /* ---------------------------------------------------------------- */ - -endlowlevel_init: - - mov pc, lr diff --git a/board/cerf250/u-boot.lds b/board/cerf250/u-boot.lds deleted file mode 100644 index f010239..0000000 --- a/board/cerf250/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile deleted file mode 100644 index c66dd71..0000000 --- a/board/cm4008/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := cm4008.o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/cm4008/cm4008.c b/board/cm4008/cm4008.c deleted file mode 100644 index 4d2013b..0000000 --- a/board/cm4008/cm4008.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) -#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b) - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ -int env_flash_cmdline (void) -{ - unsigned char *sp = (unsigned char *) 0x0201c020; - unsigned char *ep; - int len; - - /* Check if "erase" push button is depressed */ - if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) { - printf("### Entering network recovery mode...\n"); - setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0"); - setenv("bootcmd", "bootp 0x400000; gofsk 0x400000"); - setenv("bootdelay", "2"); - return 0; - } - - /* Check for flash based kernel boot args to use as default */ - for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++) - ; - - if ((len > 0) && (len <1024)) - setenv("bootargs", sp); - - return 0; -} - -int board_late_init (void) -{ - return 0; -} - - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* arch number of CM4008 */ - gd->bd->bi_arch_number = 624; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - /* power down all but port 0 on the switch */ - ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005); - ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005); - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} diff --git a/board/cm4008/config.mk b/board/cm4008/config.mk deleted file mode 100644 index 74eaeb0..0000000 --- a/board/cm4008/config.mk +++ /dev/null @@ -1 +0,0 @@ -TEXT_BASE = 0x00f00000 diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c deleted file mode 100644 index 86c8e2a..0000000 --- a/board/cm4008/flash.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com - * - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, unsigned char data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - /* ignore for now */ - flash_info[i].flash_id = FLASH_UNKNOWN; - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _bss_start - _armboot_start, - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) - return; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info) -{ - volatile unsigned char value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = 0xAA; - addr[0x2AAA] = 0x55; - addr[0x5555] = 0x90; - - mb (); - value = addr[0]; - - switch (value) { - - case (unsigned char)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = 0xFF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[2]; /* device ID */ - - switch (value) { - - case (unsigned char)INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (unsigned char)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = 0xFF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - else - printf ("\n"); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - volatile unsigned char *addr; - unsigned char status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - addr = (volatile unsigned char *) (info->start[sect]); - *addr = 0x50; /* clear status register */ - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ - - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x50; /* clear status register cmd */ - *addr = 0xFF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - unsigned char data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - wp = addr; - port_width = 1; - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, unsigned char data) -{ - volatile unsigned char *addr = (volatile unsigned char *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = 0x40; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = 0xFF; /* restore read mode */ - return (1); - } - } - - *addr = 0xFF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/cm4008/u-boot.lds b/board/cm4008/u-boot.lds deleted file mode 100644 index ec09fa2..0000000 --- a/board/cm4008/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile deleted file mode 100644 index f0d3451..0000000 --- a/board/cm41xx/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := cm41xx.o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/cm41xx/cm41xx.c b/board/cm41xx/cm41xx.c deleted file mode 100644 index 65eaa94..0000000 --- a/board/cm41xx/cm41xx.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) -#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b) - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ -int env_flash_cmdline (void) -{ - unsigned char *sp = (unsigned char *) 0x0201c020; - unsigned char *ep; - int len; - - /* Check if "erase" push button is depressed */ - if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) { - printf("### Entering network recovery mode...\n"); - setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0"); - setenv("bootcmd", "bootp 0x400000; gofsk 0x400000"); - setenv("bootdelay", "2"); - return 0; - } - - /* Check for flash based kernel boot args to use as default */ - for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++) - ; - - if ((len > 0) && (len <1024)) - setenv("bootargs", sp); - - return 0; -} - -int board_late_init (void) -{ - return 0; -} - - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* arch number of CM41xx */ - gd->bd->bi_arch_number = 672; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - /* power down all but port 0 on the switch */ - ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005); - ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005); - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} diff --git a/board/cm41xx/config.mk b/board/cm41xx/config.mk deleted file mode 100644 index 74eaeb0..0000000 --- a/board/cm41xx/config.mk +++ /dev/null @@ -1 +0,0 @@ -TEXT_BASE = 0x00f00000 diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c deleted file mode 100644 index 86c8e2a..0000000 --- a/board/cm41xx/flash.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com - * - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, unsigned char data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - /* ignore for now */ - flash_info[i].flash_id = FLASH_UNKNOWN; - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _bss_start - _armboot_start, - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) - return; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info) -{ - volatile unsigned char value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = 0xAA; - addr[0x2AAA] = 0x55; - addr[0x5555] = 0x90; - - mb (); - value = addr[0]; - - switch (value) { - - case (unsigned char)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = 0xFF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[2]; /* device ID */ - - switch (value) { - - case (unsigned char)INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (unsigned char)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = 0xFF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - else - printf ("\n"); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - volatile unsigned char *addr; - unsigned char status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - addr = (volatile unsigned char *) (info->start[sect]); - *addr = 0x50; /* clear status register */ - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ - - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x50; /* clear status register cmd */ - *addr = 0xFF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - unsigned char data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - wp = addr; - port_width = 1; - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, unsigned char data) -{ - volatile unsigned char *addr = (volatile unsigned char *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = 0x40; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = 0xFF; /* restore read mode */ - return (1); - } - } - - *addr = 0xFF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/cm41xx/u-boot.lds b/board/cm41xx/u-boot.lds deleted file mode 100644 index ec09fa2..0000000 --- a/board/cm41xx/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/cmc_pu2/Makefile b/board/cmc_pu2/Makefile deleted file mode 100644 index d0def05..0000000 --- a/board/cmc_pu2/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/cmc_pu2/at45.c b/board/cmc_pu2/at45.c deleted file mode 100644 index 3c00132..0000000 --- a/board/cmc_pu2/at45.c +++ /dev/null @@ -1,621 +0,0 @@ -/* Driver for ATMEL DataFlash support - * Author : Hamid Ikdoumi (Atmel) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -#ifdef CONFIG_HAS_DATAFLASH -#include - -#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to -the Continuous Array Read function */ - -/* AC Characteristics */ -/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -#define AT91C_TIMEOUT_WRDY 200000 -#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ -#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ - -void AT91F_SpiInit(void) { - -/*-------------------------------------------------------------------*/ -/* SPI DataFlash Init */ -/*-------------------------------------------------------------------*/ - /* Configure PIOs */ - AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - /* Enable CLock */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; - - /* Reset the SPI */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; - - /* Configure SPI in Master Mode with No CS selected !!! */ - AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; - - /* Configure CS0 and CS3 */ - *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - - *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - -} - -void AT91F_SpiEnable(int cs) { - switch(cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); - break; - case 3: /* Configure SPI CS3 for Serial DataFlash Card */ - /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ - AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ - /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; - /* Configure PCS */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - } - - /* SPI_Enable */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; -} - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiWrite */ -/* \brief Set the PDC registers for a transfert */ -/*----------------------------------------------------------------------------*/ -unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) -{ - unsigned int timeout; - - pDesc->state = BUSY; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - /* Initialize the Transmit and Receive Pointer */ - AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; - AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; - - /* Intialize the Transmit and Receive Counters */ - AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; - AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; - - if ( pDesc->tx_data_size != 0 ) { - /* Initialize the Next Transmit and Next Receive Pointer */ - AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; - AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; - - /* Intialize the Next Transmit and Next Receive Counters */ - AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; - AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; - } - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - timeout = 0; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; - while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - pDesc->state = IDLE; - - if (timeout >= CFG_SPI_WRITE_TOUT){ - printf("Error Timeout\n\r"); - return DATAFLASH_ERROR; - } - - return DATAFLASH_OK; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashSendCommand */ -/* \brief Generic function to send a command to the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashSendCommand( - AT91PS_DataFlash pDataFlash, - unsigned char OpCode, - unsigned int CmdSize, - unsigned int DataflashAddress) -{ - unsigned int adr; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* process the address to obtain page address and byte address */ - adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); - - /* fill the command buffer */ - pDataFlash->pDataFlashDesc->command[0] = OpCode; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); - } else { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - } - pDataFlash->pDataFlashDesc->command[5] = 0; - pDataFlash->pDataFlashDesc->command[6] = 0; - pDataFlash->pDataFlashDesc->command[7] = 0; - - /* Initialize the SpiData structure for the spi write fuction */ - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; - - /* send the command and read the data */ - return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashGetStatus */ -/* \brief Read the status register of the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) -{ - AT91S_DataFlashStatus status; - - /* if a transfert is in progress ==> return 0 */ - if( (pDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* first send the read status command (D7H) */ - pDesc->command[0] = DB_STATUS; - pDesc->command[1] = 0; - - pDesc->DataFlash_state = GET_STATUS; - pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ - pDesc->tx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_size = 2 ; - pDesc->tx_cmd_size = 2 ; - status = AT91F_SpiWrite (pDesc); - - pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); - - return status; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashWaitReady */ -/* \brief wait for dataflash ready (bit7 of the status register == 1) */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) -{ - pDataFlashDesc->DataFlash_state = IDLE; - - do { - AT91F_DataFlashGetStatus(pDataFlashDesc); - timeout--; - } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); - - if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) - return DATAFLASH_ERROR; - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashContinuousRead */ -/* Object : Continuous stream Read */ -/* Input Parameters : DataFlash Service */ -/* : = dataflash address */ -/* : <*dataBuffer> = data buffer pointer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( - AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead ) -{ - AT91S_DataFlashStatus status; - /* Test the size to read in the device */ - if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - - status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); - /* Send the command to the dataflash */ - return(status); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashPagePgmBuf */ -/* Object : Main memory page program through buffer 1 or buffer 2 */ -/* Input Parameters : DataFlash Service */ -/* : <*src> = Source buffer */ -/* : = dataflash destination address */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int SizeToWrite) -{ - int cmdsize; - pDataFlash->pDataFlashDesc->tx_data_pt = src ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->rx_data_pt = src; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; - - cmdsize = 4; - /* Send the command to the dataflash */ - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_MainMemoryToBufferTransfert */ -/* Object : Read a page in the SRAM Buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*----------------------------------------------------------------------------- */ -/* Function Name : AT91F_DataFlashWriteBuffer */ -/* Object : Write data to the internal sram buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : = command to write buffer1 or buffer2 */ -/* : <*dataBuffer> = data buffer to write */ -/* : = address in the internal buffer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite ) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) - return DATAFLASH_BAD_COMMAND; - - /* buffer address must be lower than page size */ - if (bufferAddress > pDataFlash->pDevice->pages_size) - return DATAFLASH_BAD_ADDRESS; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* Send first Write Command */ - pDataFlash->pDataFlashDesc->command[0] = BufferCommand; - pDataFlash->pDataFlashDesc->command[1] = 0; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[2] = 0; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - cmdsize = 5; - } else { - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - cmdsize = 4; - } - - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - - return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PageErase */ -/* Object : Erase a page */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PageErase( - AT91PS_DataFlash pDataFlash, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_BlockErase */ -/* Object : Erase a Block */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_BlockErase( - AT91PS_DataFlash pDataFlash, - unsigned int block) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_WriteBufferToMain */ -/* Object : Write buffer to the main memory */ -/* Input Parameters : DataFlash Service */ -/* : = command to send to buffer1 or buffer2 */ -/* : = main memory address */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_WriteBufferToMain ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest ) -{ - int cmdsize; - /* Test if the buffer command is correct */ - if ((BufferCommand != DB_BUF1_PAGE_PGM) && - (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && - (BufferCommand != DB_BUF2_PAGE_PGM) && - (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - /* Send the command to the dataflash */ - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PartialPageWrite */ -/* Object : Erase partielly a page */ -/* Input Parameters : = page number */ -/* : = adr to begin the fading */ -/* : = Number of bytes to erase */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PartialPageWrite ( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size) -{ - unsigned int page; - unsigned int AdrInPage; - - page = dest / (pDataFlash->pDevice->pages_size); - AdrInPage = dest % (pDataFlash->pDevice->pages_size); - - /* Read the contents of the page in the Sram Buffer */ - AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - /*Update the SRAM buffer */ - AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Erase page if a 128 Mbits device */ - if (pDataFlash->pDevice->pages_number >= 16384) { - AT91F_PageErase(pDataFlash, page); - /* Rewrite the modified Sram Buffer in the main memory */ - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - - /* Rewrite the modified Sram Buffer in the main memory */ - return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashWrite */ -/* Object : */ -/* Input Parameters : <*src> = Source buffer */ -/* : = dataflash adress */ -/* : = data buffer size */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWrite( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ) -{ - unsigned int length; - unsigned int page; - unsigned int status; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - /* If destination does not fit a page start address */ - if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { - length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); - - if (size < length) - length = size; - - if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= length; - dest += length; - src += length; - } - - while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { - /* program dataflash page */ - page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); - - status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - if (!status) - return DATAFLASH_ERROR; - - status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); - if(!status) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= pDataFlash->pDevice->pages_size ; - dest += pDataFlash->pDevice->pages_size ; - src += pDataFlash->pDevice->pages_size ; - } - - /* If still some bytes to read */ - if ( size > 0 ) { - /* program dataflash page */ - if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashRead */ -/* Object : Read a block in dataflash */ -/* Input Parameters : */ -/* Return value : */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataFlashRead( - AT91PS_DataFlash pDataFlash, - unsigned long addr, - unsigned long size, - char *buffer) -{ - unsigned long SizeToRead; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - while (size) { - SizeToRead = (size < 0x8000)? size:0x8000; - - if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) - return -1; - - size -= SizeToRead; - addr += SizeToRead; - buffer += SizeToRead; - } - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataflashProbe */ -/* Object : */ -/* Input Parameters : */ -/* Return value : Dataflash status register */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) -{ - AT91F_SpiEnable(cs); - AT91F_DataFlashGetStatus(pDesc); - return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); -} - -#endif diff --git a/board/cmc_pu2/cmc_pu2.c b/board/cmc_pu2/cmc_pu2.c deleted file mode 100644 index 14168e6..0000000 --- a/board/cmc_pu2/cmc_pu2.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn - * (2004) garyj@denx.de - * - * Modified for CMC_BASIC by Martin Krause (2005), TQ-Systems GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ -#define CMC_HP_BASIC 1 -#define CMC_PU2 2 -#define CMC_BASIC 4 - -int hw_detect (void); - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - AT91PS_PIO piob = AT91C_BASE_PIOB; - AT91PS_PIO pioc = AT91C_BASE_PIOC; - - /* Enable Ctrlc */ - console_init_f (); - - /* Correct IRDA resistor problem */ - /* Set PA23_TXD in Output */ - /* (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; */ - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* PIOB and PIOC clock enabling */ - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC; - - /* - * configure PC0-PC3 as input without pull ups, so RS485 driver enable - * (CMC-PU2) and digital outputs (CMC-BASIC) are deactivated. - */ - pioc->PIO_ODR = AT91C_PIO_PC0 | AT91C_PIO_PC1 | - AT91C_PIO_PC2 | AT91C_PIO_PC3; - pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 | - AT91C_PIO_PC2 | AT91C_PIO_PC3; - pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 | - AT91C_PIO_PC2 | AT91C_PIO_PC3; - - /* - * On CMC-PU2 board configure PB3-PB6 to input without pull ups to - * clear the duo LEDs (the external pull downs assure a proper - * signal). On CMC-BASIC and CMC-HP-BASIC set PB3-PB6 to output and - * drive it high, to configure current measurement on AINx. - */ - if (hw_detect() & CMC_PU2) { - piob->PIO_ODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - } - else if ((hw_detect() & CMC_BASIC) || (hw_detect() & CMC_HP_BASIC)) { - piob->PIO_SODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - piob->PIO_OER = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - } - piob->PIO_PPUDR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - piob->PIO_PER = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - - /* - * arch number of CMC_PU2-Board. MACH_TYPE_CMC_PU2 is not supported in - * the linuxarm kernel, yet. - */ - /* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */ - gd->bd->bi_arch_number = 251; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -int checkboard (void) -{ - if (hw_detect() & CMC_PU2) - puts ("Board: CMC-PU2 (Rittal GmbH)\n"); - else if (hw_detect() & CMC_BASIC) - puts ("Board: CMC-BASIC (Rittal GmbH)\n"); - else if (hw_detect() & CMC_HP_BASIC) - puts ("Board: CMC-HP-BASIC (Rittal GmbH)\n"); - else - puts ("Board: unknown\n"); - return 0; -} - -int hw_detect (void) -{ - AT91PS_PIO pio = AT91C_BASE_PIOB; - - /* PIOB clock enabling */ - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; - - /* configure PB12 as input without pull up */ - pio->PIO_ODR = AT91C_PIO_PB12; - pio->PIO_PPUDR = AT91C_PIO_PB12; - pio->PIO_PER = AT91C_PIO_PB12; - - /* configure PB13 as input without pull up */ - pio->PIO_ODR = AT91C_PIO_PB13; - pio->PIO_PPUDR = AT91C_PIO_PB13; - pio->PIO_PER = AT91C_PIO_PB13; - - /* read board identification pin */ - if (pio->PIO_PDSR & AT91C_PIO_PB12) - return ((pio->PIO_PDSR & AT91C_PIO_PB13) - ? CMC_PU2 : 0); - else - return ((pio->PIO_PDSR & AT91C_PIO_PB13) - ? CMC_HP_BASIC : CMC_BASIC); -} - -#ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = dm9161_InitPhy; - p_phyops->IsPhyConnected = dm9161_IsPhyConnected; - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; - p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/cmc_pu2/config.mk b/board/cmc_pu2/config.mk deleted file mode 100644 index 7116eea..0000000 --- a/board/cmc_pu2/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -TEXT_BASE = 0x20F00000 -## For testing: load at 0x20100000 and "go" at 0x201000A4 -#TEXT_BASE = 0x20100000 diff --git a/board/cmc_pu2/flash.c b/board/cmc_pu2/flash.c deleted file mode 100644 index 9983c7b..0000000 --- a/board/cmc_pu2/flash.c +++ /dev/null @@ -1,468 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn - * garyj@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02AA - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_short *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, vu_short *dest, ushort data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - ulong flashbase = CFG_FLASH_BASE; - - /* Init: no FLASHes known */ - memset(&flash_info[0], 0, sizeof(flash_info_t)); - - flash_info[0].size = flash_get_size((vu_short *)flashbase, &flash_info[0]); - - size = flash_info[0].size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - vu_short *base = (vu_short *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = 0x00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = 0x00F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - info = NULL; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && info->start[0] <= base && - base <= info->start[0] + info->size - 1) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_S29GL064M: - printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (vu_short *addr, flash_info_t *info) -{ - int i; - ushort value; - ulong base = (ulong)addr; - - /* Write auto select command sequence */ - addr[FLASH_CYCLE1] = 0x00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = 0x0055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = 0x0090; /* selects Intel or AMD */ - - /* read Manufacturer ID */ - udelay(100); - value = addr[0]; - debug ("Manufacturer ID: %04X\n", value); - - switch (value) { - - case (AMD_MANUFACT & 0xFFFF): - debug ("Manufacturer: AMD (Spansion)\n"); - info->flash_id = FLASH_MAN_AMD; - break; - - case (INTEL_MANUFACT & 0xFFFF): - debug ("Manufacturer: Intel (not supported yet)\n"); - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - printf ("Unknown Manufacturer ID: %04X\n", value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - goto out; - } - - value = addr[1]; - debug ("Device ID: %04X\n", value); - - switch (addr[1]) { - - case (AMD_ID_MIRROR & 0xFFFF): - debug ("Mirror Bit flash: addr[14] = %08X addr[15] = %08X\n", - addr[14], addr[15]); - - switch(addr[14]) { - case (AMD_ID_GL064M_2 & 0xFFFF): - if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) { - printf ("Chip: S29GLxxxM -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } else { - debug ("Chip: S29GL064M-R6\n"); - info->flash_id += FLASH_S29GL064M; - info->sector_count = 128; - info->size = 0x00800000; - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x10000; - } - } - break; /* => 16 MB */ - default: - printf ("Chip: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - break; - - default: - printf ("Unknown Device ID: %04X\n", value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - -out: - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short *)(info->start[0]); - int flag, prot, sect, ssect, l_sect; - ulong now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* - * Start erase on unprotected sectors. - * Since the flash can erase multiple sectors with one command - * we take advantage of that by doing the erase in chunks of - * 3 sectors. - */ - for (sect = s_first; sect <= s_last; ) { - l_sect = -1; - - addr[FLASH_CYCLE1] = 0x00AA; - addr[FLASH_CYCLE2] = 0x0055; - addr[FLASH_CYCLE1] = 0x0080; - addr[FLASH_CYCLE1] = 0x00AA; - addr[FLASH_CYCLE2] = 0x0055; - - /* do the erase in chunks of at most 3 sectors */ - for (ssect = 0; ssect < 3; ssect++) { - if ((sect + ssect) > s_last) - break; - if (info->protect[sect + ssect] == 0) { /* not protected */ - addr = (vu_short *)(info->start[sect + ssect]); - addr[0] = 0x0030; - l_sect = sect + ssect; - } - } - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - reset_timer_masked (); - last = 0; - addr = (vu_short *)(info->start[l_sect]); - while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - sect += ssect; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - -DONE: - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - }; - - if ((int) src & 1) { - printf ("unaligned source not supported\n"); - return ERR_ALIGN; - }; - - wp = addr; - - while (cnt >= 2) { - data = *((vu_short *)src); - if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) { -printf ("write_buff 1: write_word_amd() rc=%d\n", rc); - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (ERR_OK); - } - - if (cnt == 1) { - data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << 8); - if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) { -printf ("write_buff 1: write_word_amd() rc=%d\n", rc); - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data) -{ - int flag; - vu_short *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (vu_short *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = 0x00AA; /* unlock */ - base[FLASH_CYCLE2] = 0x0055; /* unlock */ - base[FLASH_CYCLE1] = 0x00A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - reset_timer_masked (); - - /* data polling for D7 */ - while ((*dest & 0x0080) != (data & 0x0080)) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *dest = 0x00F0; /* reset bank */ - return (1); - } - } - return (0); -} diff --git a/board/cmc_pu2/load_sernum_ethaddr.c b/board/cmc_pu2/load_sernum_ethaddr.c deleted file mode 100644 index 94aa30d..0000000 --- a/board/cmc_pu2/load_sernum_ethaddr.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include - -#define I2C_CHIP 0x50 /* I2C bus address of onboard EEPROM */ -#define I2C_ALEN 1 /* length of EEPROM addresses in bytes */ -#define I2C_OFFSET 0x0 /* start address of manufacturere data block - * in EEPROM */ - -/* 64 Byte manufacturer data block in EEPROM */ -struct manufacturer_data { - unsigned int serial_number; /* serial number (0...999999) */ - unsigned short hardware; /* hardware version (e.g. V1.02) */ - unsigned short manuf_date; /* manufacture date (e.g. 25/02) */ - unsigned char name[20]; /* device name (in CHIP.INI) */ - unsigned char macadr[6]; /* MAC address */ - signed char a_kal[4]; /* calibration value for U */ - signed char i_kal[4]; /* calibration value for I */ - unsigned char reserve[18]; /* reserved */ - unsigned short save_nr; /* save count */ - unsigned short chksum; /* checksum */ -}; - - -int i2c_read (unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len); - -/*----------------------------------------------------------------------- - * Process manufacturer data block in EEPROM: - * - * If we boot on a system fresh from factory, check if the manufacturer data - * in the EEPROM is valid and save some information it contains. - * - * CMC manufacturer data is defined as follows: - * - * - located in the onboard EEPROM - * - starts at offset 0x0 - * - size 0x00000040 - * - * Internal structure: see struct definition - */ - -void load_sernum_ethaddr (void) -{ - struct manufacturer_data data; - unsigned char serial [9]; - unsigned char ethaddr[18]; - unsigned short chksum; - unsigned char *p; - unsigned short i, is, id; - -#if !defined(CONFIG_HARD_I2C) && !defined(CONFIG_SOFT_I2C) -#error you must define some I2C support (CONFIG_HARD_I2C or CONFIG_SOFT_I2C) -#endif - if (i2c_read(I2C_CHIP, I2C_OFFSET, I2C_ALEN, (unsigned char *)&data, - sizeof(data)) != 0) { - puts ("Error reading manufacturer data from EEPROM\n"); - return; - } - - /* check if manufacturer data block is valid */ - p = (unsigned char *)&data; - chksum = 0; - for (i = 0; i < (sizeof(data) - sizeof(data.chksum)); i++) - chksum += *p++; - - debug ("checksum of manufacturer data block: %#.4x\n", chksum); - - if (chksum != data.chksum) { - puts ("Error: manufacturer data block has invalid checksum\n"); - return; - } - - /* copy MAC address */ - is = 0; - id = 0; - for (i = 0; i < 6; i++) { - sprintf (ðaddr[id], "%02x", data.macadr[is++]); - id += 2; - if (is < 6) - ethaddr[id++] = ':'; - } - ethaddr[id] = '\0'; /* just to be sure */ - - /* copy serial number */ - sprintf (serial, "%d", data.serial_number); - - /* set serial# and ethaddr if not yet defined */ - if (getenv("serial#") == NULL) { - setenv ("serial#", serial); - } - - if (getenv("ethaddr") == NULL) { - setenv ("ethaddr", ethaddr); - } -} diff --git a/board/cmc_pu2/u-boot.lds b/board/cmc_pu2/u-boot.lds deleted file mode 100644 index f4fbf96..0000000 --- a/board/cmc_pu2/u-boot.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/cmi/Makefile b/board/cmi/Makefile deleted file mode 100644 index 2324d87..0000000 --- a/board/cmi/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de -# -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := flash.o cmi.o -SOBJS := - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/cmi/cmi.c b/board/cmi/cmi.c deleted file mode 100644 index cbf34f7..0000000 --- a/board/cmi/cmi.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * File: cmi.c - * - * Discription: For generic board specific functions - * - */ - - -#include -#include - -#define SRAM_SIZE 1024000L /* 1M RAM available*/ - -#if defined(__APPLE__) -/* Leading underscore on symbols */ -# define SYM_CHAR "_" -#else /* No leading character on symbols */ -# define SYM_CHAR -#endif - -/* - * Macros to generate global absolutes. - */ -#define GEN_SYMNAME(str) SYM_CHAR #str -#define GEN_VALUE(str) #str -#define GEN_ABS(name, value) \ - asm (".globl " GEN_SYMNAME(name)); \ - asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) - -/* - * Check the board - */ -int checkboard(void) -{ - puts ("Board: ### No HW ID - assuming CMI board\n"); - return (0); -} - -/* - * Get RAM size. - */ -long int initdram(int board_type) -{ - return (SRAM_SIZE); /* We currently have a static size adapted for cmi board. */ -} - -/* - * Absolute environment address for linker file. - */ -GEN_ABS(env_start, CFG_ENV_OFFSET + CFG_FLASH_BASE); diff --git a/board/cmi/config.mk b/board/cmi/config.mk deleted file mode 100644 index 564f638..0000000 --- a/board/cmi/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2003 -# Martin Winistoerfer, martinwinistoerfer@gmx.ch. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# EPQ Board Configuration -# - -# Boot from flash at location 0x00000000 -TEXT_BASE = 0x02000000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cmi/flash.c b/board/cmi/flash.c deleted file mode 100644 index f7c25f4..0000000 --- a/board/cmi/flash.c +++ /dev/null @@ -1,517 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * File: flash.c - * - * Discription: This Driver is for 28F320J3A, 28F640J3A and - * 28F128J3A Intel flashs working in 16 Bit mode. - * They are single bank flashs. - * - * Most of this code is taken from existing u-boot - * source code. - */ - - -#include -#include - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -#define FLASH_ID_MASK 0xFFFF -#define FLASH_BLOCK_SIZE 0x00010000 -#define FLASH_CMD_READ_ID 0x0090 -#define FLASH_CMD_RESET 0x00ff -#define FLASH_CMD_BLOCK_ERASE 0x0020 -#define FLASH_CMD_ERASE_CONFIRM 0x00D0 -#define FLASH_CMD_CLEAR_STATUS 0x0050 -#define FLASH_CMD_SUSPEND_ERASE 0x00B0 -#define FLASH_CMD_WRITE 0x0040 -#define FLASH_CMD_PROTECT 0x0060 -#define FLASH_CMD_PROTECT_SET 0x0001 -#define FLASH_CMD_PROTECT_CLEAR 0x00D0 -#define FLASH_STATUS_DONE 0x0080 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/* - * Local function prototypes - */ -static ulong flash_get_size (vu_short *addr, flash_info_t *info); -static int write_short (flash_info_t *info, ulong dest, ushort data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/* - * Initialize flash - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - return size_b0; -} - -/* - * Compute start adress of each sector (block) - */ - -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + i * FLASH_BLOCK_SIZE; - } - return; - - default: - printf ("Don't know sector offsets for flash type 0x%lx\n", - info->flash_id); - return; - } -} - -/* - * Print flash information - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: printf ("28F320J3A (32Mbit) 16-Bit\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64Mbit) 16-Bit\n"); - break; - case FLASH_28F128J3A: printf ("28F128J3A (128Mbit) 16-Bit\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * Get size of flash in bytes. - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_short *addr, flash_info_t *info) -{ - vu_short value; - - /* Read Manufacturer ID */ - addr[0] = FLASH_CMD_READ_ID; - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = FLASH_CMD_RESET; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (INTEL_ID_28F320J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 32 MBit */ - - case (INTEL_ID_28F640J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 64 MBit */ - - case (INTEL_ID_28F128J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 128 MBit */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = FLASH_CMD_RESET; /* restore read mode */ - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = FLASH_CMD_RESET; /* restore read mode */ - - return (info->size); -} - - -/* - * Erase unprotected sectors - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#ifdef DEBUG - printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]); -#endif - - *addr = FLASH_CMD_CLEAR_STATUS; - *addr = FLASH_CMD_BLOCK_ERASE; - *addr = FLASH_CMD_ERASE_CONFIRM; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Flash erase timeout at address %lx\n", info->start[sect]); - *addr = FLASH_CMD_SUSPEND_ERASE; - *addr = FLASH_CMD_RESET; - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - *addr = FLASH_CMD_RESET; - } - } - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int i, rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start byte - */ - - if (addr - wp) { - data = 0; - data = (data << 8) | *src++; - --cnt; - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - - while (cnt >= 2) { - data = 0; - for (i=0; i<2; ++i) { - data = (data << 8) | *src++; - } - - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_short(info, wp, data)); - -} - -/* - * Write 16 bit (short) to flash - */ - -static int write_short (flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if (!(info->flash_id & FLASH_VENDMASK)) { - return 4; - } - *addr = FLASH_CMD_ERASE_CONFIRM; - *addr = FLASH_CMD_WRITE; - - *((vu_short *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* data polling for D7 */ - start = get_timer (0); - - /* wait for error or finish */ - while(!(addr[0] & FLASH_STATUS_DONE)){ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - addr[0] = FLASH_CMD_RESET; - return (1); - } - } - - *addr = FLASH_CMD_RESET; - return (0); -} - -/* - * Protects a flash sector - */ - -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - vu_short *addr = (vu_short*)(info->start[sector]); - ulong start; - - *addr = FLASH_CMD_CLEAR_STATUS; - *addr = FLASH_CMD_PROTECT; - - if(prot) { - *addr = FLASH_CMD_PROTECT_SET; - } else { - *addr = FLASH_CMD_PROTECT_CLEAR; - } - - /* wait for error or finish */ - start = get_timer (0); - while(!(addr[0] & FLASH_STATUS_DONE)){ - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { - printf("Flash protect timeout at address %lx\n", info->start[sector]); - addr[0] = FLASH_CMD_RESET; - return (1); - } - } - /* Set software protect flag */ - info->protect[sector] = prot; - *addr = FLASH_CMD_RESET; - return (0); -} diff --git a/board/cmi/u-boot.lds b/board/cmi/u-boot.lds deleted file mode 100644 index 5b03fef..0000000 --- a/board/cmi/u-boot.lds +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de - * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc5xx/start.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -/* . = env_start; - .ppcenv : - { - common/environment.o (.ppcenv) - } -*/ -} diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile deleted file mode 100644 index e5d8446..0000000 --- a/board/cobra5272/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/cobra5272/bdm/cobra5272_uboot.gdb b/board/cobra5272/bdm/cobra5272_uboot.gdb deleted file mode 100644 index 61e778e..0000000 --- a/board/cobra5272/bdm/cobra5272_uboot.gdb +++ /dev/null @@ -1,169 +0,0 @@ -# -# GDB Init script for the Coldfire 5272 processor. -# -# The main purpose of this script is to configure the -# DRAM controller so code can be loaded. -# -# This file was changed to suite the senTec COBRA5272 board. -# - -define addresses - -set $mbar = 0x10000001 -set $scr = $mbar - 1 + 0x004 -set $spr = $mbar - 1 + 0x006 -set $pmr = $mbar - 1 + 0x008 -set $apmr = $mbar - 1 + 0x00e -set $dir = $mbar - 1 + 0x010 -set $icr1 = $mbar - 1 + 0x020 -set $icr2 = $mbar - 1 + 0x024 -set $icr3 = $mbar - 1 + 0x028 -set $icr4 = $mbar - 1 + 0x02c -set $isr = $mbar - 1 + 0x030 -set $pitr = $mbar - 1 + 0x034 -set $piwr = $mbar - 1 + 0x038 -set $pivr = $mbar - 1 + 0x03f -set $csbr0 = $mbar - 1 + 0x040 -set $csor0 = $mbar - 1 + 0x044 -set $csbr1 = $mbar - 1 + 0x048 -set $csor1 = $mbar - 1 + 0x04c -set $csbr2 = $mbar - 1 + 0x050 -set $csor2 = $mbar - 1 + 0x054 -set $csbr3 = $mbar - 1 + 0x058 -set $csor3 = $mbar - 1 + 0x05c -set $csbr4 = $mbar - 1 + 0x060 -set $csor4 = $mbar - 1 + 0x064 -set $csbr5 = $mbar - 1 + 0x068 -set $csor5 = $mbar - 1 + 0x06c -set $csbr6 = $mbar - 1 + 0x070 -set $csor6 = $mbar - 1 + 0x074 -set $csbr7 = $mbar - 1 + 0x078 -set $csor7 = $mbar - 1 + 0x07c -set $pacnt = $mbar - 1 + 0x080 -set $paddr = $mbar - 1 + 0x084 -set $padat = $mbar - 1 + 0x086 -set $pbcnt = $mbar - 1 + 0x088 -set $pbddr = $mbar - 1 + 0x08c -set $pbdat = $mbar - 1 + 0x08e -set $pcddr = $mbar - 1 + 0x094 -set $pcdat = $mbar - 1 + 0x096 -set $pdcnt = $mbar - 1 + 0x098 -set $sdcr = $mbar - 1 + 0x180 -set $sdtr = $mbar - 1 + 0x184 -set $wrrr = $mbar - 1 + 0x280 -set $wirr = $mbar - 1 + 0x283 -set $wcr = $mbar - 1 + 0x288 -set $wer = $mbar - 1 + 0x28c - -end - - -# -# Setup system configuration -# -define setup-sys -set *((unsigned short *) $scr) = 0x0003 -set *((unsigned short *) $spr) = 0xffff -set *((unsigned char *) $pivr) = 0x4f -end - - -# -# Setup Chip Selects (as per Motorola M5272C3 board) -# -define setup-cs - -# CS0 -- FLASH -set *((unsigned long *) $csbr0) = 0xffe00201 -set *((unsigned long *) $csor0) = 0xffe00014 - -# CS1 -- external bus test -set *((unsigned long *) $csbr1) = 0x0 -set *((unsigned long *) $csor1) = 0x0 - -# CS2 -- Optional FSRAM -set *((unsigned long *) $csbr2) = 0x30000001 -set *((unsigned long *) $csor2) = 0xfff80000 - -# CS3 -- not used -set *((unsigned long *) $csbr3) = 0x0 -set *((unsigned long *) $csor3) = 0x0 - -# CS4 -- not used -set *((unsigned long *) $csbr4) = 0x0 -set *((unsigned long *) $csor4) = 0x0 - -# CS5 -- PLI socket0 -set *((unsigned long *) $csbr5) = 0x0 -set *((unsigned long *) $csor5) = 0x0 - -# CS6 -- PLI socket1 -set *((unsigned long *) $csbr6) = 0x0 -set *((unsigned long *) $csor6) = 0x0 - -# CS7 -- SDRAM -set *((unsigned long *) $csbr7) = 0x00000701 -set *((unsigned long *) $csor7) = 0xff00007c - -end - - -# -# Setup the DRAM controller. -# - -define setup-dram -set *((unsigned long *) $sdtr) = 0x0000f539 -set *((unsigned long *) $sdcr) = 0x00004211 - -# Dummy write to start SDRAM -set *((unsigned long *) 0) = 0 -end - - -# -# Setup for GPIO pins -# -define setup-ppio - -# PORT A -- the LED's -set *((unsigned long *) $pacnt) = 0x00000000 -# lower 8 bits for output: -set *((unsigned short *) $paddr) = 0xff -# LED's off: -set *((unsigned short *) $padat) = 0xff - -# PORT B -set *((unsigned long *) $pbcnt) = 0x55554155 -set *((unsigned short *) $pbddr) = 0x0000 -set *((unsigned short *) $pbdat) = 0x17ea - -# PORT C -#set *((unsigned short *) $pcddr) = 0x0000 -#set *((unsigned short *) $pcdat) = 0x1898 - -# PORT D -set *((unsigned long *) $pdcnt) = 0x00000000 - -end - - -# -# Added for uClinux-coldfire target... -# -target bdm /dev/bdm - -addresses -setup-sys -setup-cs -setup-dram -setup-ppio -set print pretty -set print asm-demangle -display/i $pc - - -# -load u-boot -set $pc=0x20000 -c diff --git a/board/cobra5272/bdm/gdbinit.reset b/board/cobra5272/bdm/gdbinit.reset deleted file mode 100644 index 5f1e482..0000000 --- a/board/cobra5272/bdm/gdbinit.reset +++ /dev/null @@ -1,2 +0,0 @@ -target bdm /dev/bdmcf0 -q diff --git a/board/cobra5272/bdm/load-cobra_uboot b/board/cobra5272/bdm/load-cobra_uboot deleted file mode 100644 index 933c7e7..0000000 --- a/board/cobra5272/bdm/load-cobra_uboot +++ /dev/null @@ -1,2 +0,0 @@ -m68k-bdm-elf-gdb -n -x board/cobra5272/bdm/cobra5272_uboot.gdb u-boot - diff --git a/board/cobra5272/bdm/reset b/board/cobra5272/bdm/reset deleted file mode 100644 index 8bef00b..0000000 --- a/board/cobra5272/bdm/reset +++ /dev/null @@ -1,2 +0,0 @@ -m68k-bdm-elf-gdb -n -x bdm/gdbinit.reset - diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c deleted file mode 100644 index 26adb4a..0000000 --- a/board/cobra5272/cobra5272.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - - -int checkboard (void) -{ - puts ("Board: "); - puts ("senTec COBRA5272 Board\n"); - return 0; -}; - -long int initdram (int board_type) -{ - volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR); - - sdp->sdram_sdtr = 0xf539; - sdp->sdram_sdcr = 0x4211; - - /* Dummy write to start SDRAM */ - *((volatile unsigned long *) 0) = 0; - - return CFG_SDRAM_SIZE * 1024 * 1024; -}; - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/cobra5272/config.mk b/board/cobra5272/config.mk deleted file mode 100644 index ccb2cf7..0000000 --- a/board/cobra5272/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xffe00000 diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c deleted file mode 100644 index 6f5874a..0000000 --- a/board/cobra5272/flash.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define PHYS_FLASH_1 CFG_FLASH_BASE -#define FLASH_BANK_SIZE 0x200000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_PL160CB & FLASH_TYPEMASK): - printf ("AM29PL160CB (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_PL160CB & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j == 0) { - /* 1st is 16 KiB */ - flash_info[i].start[j] = flashbase; - } - if ((j >= 1) && (j <= 2)) { - /* 2nd and 3rd are 8 KiB */ - flash_info[i].start[j] = - flashbase + 0x4000 + 0x2000 * (j - 1); - } - if (j == 3) { - /* 4th is 224 KiB */ - flash_info[i].start[j] = flashbase + 0x8000; - } - if ((j >= 4) && (j <= 10)) { - /* rest is 256 KiB */ - flash_info[i].start[j] = - flashbase + 0x40000 + 0x40000 * (j - - 4); - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0x3ffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds deleted file mode 100644 index 872f094..0000000 --- a/board/cobra5272/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(m68k) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf52x2/start.o (.text) - cpu/mcf52x2/cpu_init.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) - common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - *(.got) - __got_end = .; - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - _sbss = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cogent/Makefile b/board/cogent/Makefile deleted file mode 100644 index 4084c7e..0000000 --- a/board/cogent/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o -SOBJS := - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/cogent/README b/board/cogent/README deleted file mode 100644 index e6eef66..0000000 --- a/board/cogent/README +++ /dev/null @@ -1,118 +0,0 @@ -Cogent Modular Architecture configuration ------------------------------------------ - -As the name suggests, the Cogent platform is a modular system where -you have a motherboard into which plugs a cpu module and one or more -i/o modules. This provides very nice flexibility, but makes the -configuration task somewhat harder. - -The possible Cogent motherboards are: - -Code Config Variable Description ----- --------------- ----------- - -CMA101 CONFIG_CMA101 32MB ram, 2 ser, 1 par, rtc, dipsw, - 2x16 lcd, eth(?) -CMA102 CONFIG_CMA102 32MB ram, 2 ser, 1 par, rtc, dipsw, - 2x16 lcd -CMA111 CONFIG_CMA111 32MB ram, 1MB flash, 4 ser, 1 par, - rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI, - 10/100TP eth -CMA120 CONFIG_CMA120 32MB ram, 1MB flash, 4 ser, 1 par, - rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI, - 10/100TP eth, 2xPCMCIA, video/lcd-panel -CMA150 CONFIG_CMA150 8MB ram, 1MB flash, 2 ser, 1 par, rtc, - ps/2 kbd/mse, 2x16 lcd - -The possible Cogent PowerPC CPU modules are: - -Code Config Variable Description ----- --------------- ----------- - -CMA278-603EV CONFIG_CMA278_603EV PPC603ev CPU, 66MHz clock, 512K EPROM, - JTAG/COP -CMA278-603ER CONFIG_CMA278_603ER PPC603er CPU, 66MHz clock, 512K EPROM, - JTAG/COP -CMA278-740 CONFIG_CMA278_740 PPC740 CPU, 66MHz clock, 512K EPROM, - JTAG/COP -CMA280-509 CONFIG_CMA280_509 MPC505/509 CPU, 50MHz clock, - 512K EPROM, BDM -CMA282 CONFIG_CMA282 MPC8260 CPU, 66MHz clock, 512K EPROM, - JTAG, 16M RAM, 1 x ser (SMC2), - 1 x 10baseT PHY (SCC4), 1 x 10/100 TP - PHY (FCC1), 2 x 48pin DIN (FCC2 + TDM1) -CMA285 CONFIG_CMA285 MPC801 CPU, 33MHz clock, 512K EPROM, - BDM -CMA286-21 CONFIG_CMA286_21 MPC821 CPU, 66MHz clock, 512K EPROM, - BDM, 16M RAM, 2 x ser (SMC1 + SMC2), - 1 x 10baseT PHY (SCC2) -CMA286-60-OLD CONFIG_CMA286_60_OLD MPC860 CPU, 33MHz clock, 128K EPROM, - BDM -CMA286-60 CONFIG_CMA286_60 MPC860 CPU, 66MHz clock, 512K EPROM, - BDM, 16M RAM, 2 x ser (SMC1 + SMC2), - 1 x 10baseT PHY (SCC2) -CMA286-60P CONFIG_CMA286_60P MPC860P CPU, 66MHz clock, 512K EPROM, - BDM, 16M RAM, 2 x ser (SMC1 + SMC2), - 1 x 10baseT PHY (SCC2) -CMA287-23 CONFIG_CMA287_23 MPC823 CPU, 33MHz clock, 512K EPROM, - BDM -CMA287-50 CONFIG_CMA287_50 MPC850 CPU, 33MHz clock, 512K EPROM, - BDM - -(there are a lot of other cpu modules with ARM, MIPS and M-CORE CPUs, -but we'll worry about those later). - -The possible Cogent CMA I/O Modules are: - -Code Config Variable Description ----- --------------- ----------- - -CMA302 CONFIG_CMA302 up to 16M flash, ps/2 keyboard/mouse -CMA352 CONFIG_CMA352 CMAbus <=> PCI - -Currently supported: - - Motherboards: CMA102 - CPU Modules: CMA286-60-OLD - I/O Modules: CMA302 I/O module - -To configure, perform the usual U-Boot configuration task of editing -"include/config_cogent_mpc8xx.h" and reviewing all the options and -settings in there. In particular, check the chip select values -installed into the memory controller's various option and base -registers - these are set by the defines CFG_CMA_CSn_{BASE,SIZE} and -CFG_{B,O}Rn_PRELIM. Also be careful of the clock settings installed -into the SCCR - via the define CFG_SCCR. Finally, decide whether you -want the serial console on motherboard serial port A or on one of the -8xx SMC ports, and set CONFIG_8xx_CONS_{SMC1,SMC2,NONE} accordingly -(NONE means use Cogent motherboard serial port A). - -Then edit the file "cogent/config.mk". Firstly, set TEXT_BASE to be -the base address of the EPROM for the CPU module. This should be the -same as the value selected for CFG_MONITOR_BASE in -"include/config_cogent_*.h" (in fact, I have made this automatic via -the -DTEXT_BASE=... option in CPPFLAGS). - -Finally, set the values of the make variables $(CMA_MB) and $(CMA_IOMS). - -$(CMA_MB) is the name of the directory that contains support for your -motherboard. At this stage, only "cma10x" exists, which supports the -CMA101 and CMA102 motherboards - but only selected devices, namely -serial, lcd and dipsw. - -$(CMA_IOMS) is a list of zero or more directories that contain -support for the i/o modules you have installed. At this stage, only -"cma302" exists, which supports the CMA302 flash i/o module - but -only the flash part, not the ps/2 keyboard and mouse interfaces. - -There should be a make variable for each of the above directories, -which is the directory name with "_O" appended. This make variable is -a list of object files to compile from that directory and include in -the library. - - e.g. cma10x_O = serial.o ... - -That's it. Good Luck. - -Murray.Jensen@cmst.csiro.au -August 31, 2000. diff --git a/board/cogent/README.cma286 b/board/cogent/README.cma286 deleted file mode 100644 index 0345fea..0000000 --- a/board/cogent/README.cma286 +++ /dev/null @@ -1,69 +0,0 @@ -CPU module revisions --------------------- - -My cpu module has the model number "CMA286-60-990526-01". My motherboard -has the model number "CMA102-32M-990526-01". These are both fairly old, -and may not reflect current design. In particular, I can see from the -Cogent web site that the CMA286 has been significantly redesigned - it -now has on board RAM (4M), ethernet 10baseT PHY (on SCC2), 2 serial ports -(SMC1 and SMC2), and 48pin DIN for the FEC (if present i.e. MPC860T), and -also the EPROM is 512K. - -My CMA286-60 has none of this, and only 128K EPROM. In addition, the CPU -clock is listed as 66MHz, whereas mine is 33.333MHz. - -Clocks ------- - -Quote from my "CMA286 MPC860/821 User's Manual": - -"When setting up the Periodic Interrupt Timer (PIT), be aware that the -CMA286 places the MPC860/821 in PLL X1 Mode. This means that we feed -a 25MHz clock directly into the MPC860/821. This mode sets the divisor -for the PIT to be 512. In addition, the Time Base Register (TMB) -divisor is set to 16." - -I interpreted this information to mean that EXTCLK is 25MHz and that at -power on reset, MODCK1=1 and MODCK2=0, which selects EXTCLK as the -source for OSCCLK and PITRTCLK, sets RTDIV to 512 and sets MF (the -multiplication factor) to 1 (I assume this is what they mean by X1 -mode above). MF=1 means the cpus internal clock runs at the same -rate as EXTCLK i.e. 25MHz. - -Furthermore, since SCCR[TBS] (the Time Base Source selector bit in the -System Clock and Reset Control register) is set in the cpu initialisation -code, the TMBCLK source is forced to be GCLK2 and the TMBCLK prescale is -forced to be 16. This results in TMBCLK=1562500. - -One problem - since PITRTCLK source is EXTCLK (25Mhz) and RTDIV is 512, -PITRTCLK will be 48828.125 (huh?). Another quote from the MPC860 Users -Manual: - -"When used by the real-time clock (RTC), the PITRTCLK source is first -divided as determined by RTDIV, and then divided in the RTC circuits by -either 8192 or 9600. Therefore, in order for the RTC to count in -seconds, the clock source must satisfy: - - (EXTCLK or OSCM) / [(4 or 512) x (8192 or 9600)] = 1 - -The RTC will operate with other frequencies, but it will not count in -units of seconds." - -Therefore, the internal RTC of the MPC860 is not going to count in -seconds, so we must use the motherboard RTC (if we need a RTC). - -I presume this means that they do not provide a fixed oscillator for -OSCM. The code in get_gclk_freq() assumes PITRTCLK source is OSCM, -RTDIV is 4, and that OSCM/4 is 8192 (i.e. a ~32KHz oscillator). Since -the CMA286-60 doesn't have this (at least mine doesn't) we can't use -the code in get_gclk_freq(). - -Finally, it appears that the internal clock in my CMA286-60 is actually -33.333MHz. Which makes TMBCLK=2083312.5 (another huh?) and -PITRTCLK=65103.515625 (bloody hell!). - -If anyone finds anything wrong with the stuff above, I would appreciate -an email about it. - -Murray Jensen -21-Aug-00 diff --git a/board/cogent/config.mk b/board/cogent/config.mk deleted file mode 100644 index ee77939..0000000 --- a/board/cogent/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Cogent Modular Architecture -# - -# Boot EPROM location -TEXT_BASE = 0xfff00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cogent/dipsw.c b/board/cogent/dipsw.c deleted file mode 100644 index d2027c9..0000000 --- a/board/cogent/dipsw.c +++ /dev/null @@ -1,50 +0,0 @@ -#include -#include - -unsigned char -dipsw_raw(void) -{ - return cma_mb_reg_read(&((cma_mb_dipsw *)CMA_MB_DIPSW_BASE)->dip_val); -} - -unsigned char -dipsw_cooked(void) -{ - unsigned char val1, val2, mask1, mask2; - - val1 = dipsw_raw(); - - /* - * we want to mirror the bits because the low bit is switch 1 and high - * bit is switch 8 and also invert them because 1=off and 0=on, according - * to manual. - * - * this makes the value more intuitive i.e. - * - left most, or high, or top, bit is left most switch (1); - * - right most, or low, or bottom, bit is right most switch (8) - * - a set bit means "on" and a clear bit means "off" - */ - - val2 = 0; - for (mask1 = 1 << 7, mask2 = 1; mask1 > 0; mask1 >>= 1, mask2 <<= 1) - if ((val1 & mask1) == 0) - val2 |= mask2; - - return (val2); -} - -void -dipsw_init(void) -{ - unsigned char val, mask; - - val = dipsw_cooked(); - - printf("|"); - for (mask = 1 << 7; mask > 0; mask >>= 1) - if (val & mask) - printf("on |"); - else - printf("off|"); - printf("\n"); -} diff --git a/board/cogent/dipsw.h b/board/cogent/dipsw.h deleted file mode 100644 index 4f52fd4..0000000 --- a/board/cogent/dipsw.h +++ /dev/null @@ -1,3 +0,0 @@ -extern unsigned char dipsw_raw(void); -extern unsigned char dipsw_cooked(void); -extern void dipsw_init(void); diff --git a/board/cogent/flash.c b/board/cogent/flash.c deleted file mode 100644 index 969520d..0000000 --- a/board/cogent/flash.c +++ /dev/null @@ -1,648 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - - -#if defined(CONFIG_CMA302) - -/* - * probe for the existence of flash at address "addr" - * 0 = yes, 1 = bad Manufacturer's Id, 2 = bad Device Id - */ -static int -c302f_probe_word(c302f_addr_t addr) -{ - /* reset the flash */ - *addr = C302F_BNK_CMD_RST; - - /* check the manufacturer id */ - *addr = C302F_BNK_CMD_RD_ID; - if (*C302F_BNK_ADDR_MAN(addr) != C302F_BNK_RD_ID_MAN) - return 1; - - /* check the device id */ - *addr = C302F_BNK_CMD_RD_ID; - if (*C302F_BNK_ADDR_DEV(addr) != C302F_BNK_RD_ID_DEV) - return 2; - -#ifdef FLASH_DEBUG - { - int i; - - printf("\nMaster Lock Config = 0x%08lx\n", - *C302F_BNK_ADDR_CFGM(addr)); - for (i = 0; i < C302F_BNK_NBLOCKS; i++) - printf("Block %2d Lock Config = 0x%08lx\n", - i, *C302F_BNK_ADDR_CFG(i, addr)); - } -#endif - - /* reset the flash again */ - *addr = C302F_BNK_CMD_RST; - - return 0; -} - -/* - * probe for Cogent CMA302 flash module at address "base" and store - * info for any found into flash_info entry "fip". Must find at least - * one bank. - */ -static void -c302f_probe(flash_info_t *fip, c302f_addr_t base) -{ - c302f_addr_t addr, eaddr; - int nbanks; - - fip->size = 0L; - fip->sector_count = 0; - - addr = base; - eaddr = C302F_BNK_ADDR_BASE(addr, C302F_MAX_BANKS); - nbanks = 0; - - while (addr < eaddr) { - c302f_addr_t addrw, eaddrw, addrb; - int i, osc, nsc; - - addrw = addr; - eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw); - - while (addrw < eaddrw) - if (c302f_probe_word(addrw++) != 0) - goto out; - - /* bank exists - append info for this bank to *fip */ - fip->flash_id = FLASH_MAN_INTEL|FLASH_28F008S5; - fip->size += C302F_BNK_SIZE; - osc = fip->sector_count; - fip->sector_count += C302F_BNK_NBLOCKS; - if ((nsc = fip->sector_count) >= CFG_MAX_FLASH_SECT) - panic("Too many sectors in flash at address 0x%08lx\n", - (unsigned long)base); - - addrb = addr; - for (i = osc; i < nsc; i++) { - fip->start[i] = (ulong)addrb; - fip->protect[i] = 0; - addrb = C302F_BNK_ADDR_NEXT_BLK(addrb); - } - - addr = C302F_BNK_ADDR_NEXT_BNK(addr); - nbanks++; - } - -out: - if (nbanks == 0) - panic("ERROR: no flash found at address 0x%08lx\n", - (unsigned long)base); -} - -static void -c302f_reset(flash_info_t *info, int sect) -{ - c302f_addr_t addrw, eaddrw; - - addrw = (c302f_addr_t)info->start[sect]; - eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw); - - while (addrw < eaddrw) { -#ifdef FLASH_DEBUG - printf(" writing reset cmd to addr 0x%08lx\n", - (unsigned long)addrw); -#endif - *addrw = C302F_BNK_CMD_RST; - addrw++; - } -} - -static void -c302f_erase_init(flash_info_t *info, int sect) -{ - c302f_addr_t addrw, saddrw, eaddrw; - int flag; - -#ifdef FLASH_DEBUG - printf("0x%08lx C302F_BNK_CMD_PROG\n", C302F_BNK_CMD_PROG); - printf("0x%08lx C302F_BNK_CMD_ERASE1\n", C302F_BNK_CMD_ERASE1); - printf("0x%08lx C302F_BNK_CMD_ERASE2\n", C302F_BNK_CMD_ERASE2); - printf("0x%08lx C302F_BNK_CMD_CLR_STAT\n", C302F_BNK_CMD_CLR_STAT); - printf("0x%08lx C302F_BNK_CMD_RST\n", C302F_BNK_CMD_RST); - printf("0x%08lx C302F_BNK_STAT_RDY\n", C302F_BNK_STAT_RDY); - printf("0x%08lx C302F_BNK_STAT_ERR\n", C302F_BNK_STAT_ERR); -#endif - - saddrw = (c302f_addr_t)info->start[sect]; - eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw); - -#ifdef FLASH_DEBUG - printf("erasing sector %d, start addr = 0x%08lx " - "(bank next word addr = 0x%08lx)\n", sect, - (unsigned long)saddrw, (unsigned long)eaddrw); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts(); - - for (addrw = saddrw; addrw < eaddrw; addrw++) { -#ifdef FLASH_DEBUG - printf(" writing erase cmd to addr 0x%08lx\n", - (unsigned long)addrw); -#endif - *addrw = C302F_BNK_CMD_ERASE1; - *addrw = C302F_BNK_CMD_ERASE2; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); -} - -static int -c302f_erase_poll(flash_info_t *info, int sect) -{ - c302f_addr_t addrw, saddrw, eaddrw; - int sectdone, haderr; - - saddrw = (c302f_addr_t)info->start[sect]; - eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw); - - sectdone = 1; - haderr = 0; - - for (addrw = saddrw; addrw < eaddrw; addrw++) { - c302f_word_t stat = *addrw; - -#ifdef FLASH_DEBUG - printf(" checking status at addr " - "0x%08lx [0x%08lx]\n", - (unsigned long)addrw, stat); -#endif - if ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY) - sectdone = 0; - else if ((stat & C302F_BNK_STAT_ERR) != 0) { - printf(" failed on sector %d " - "(stat = 0x%08lx) at " - "address 0x%08lx\n", - sect, stat, - (unsigned long)addrw); - *addrw = C302F_BNK_CMD_CLR_STAT; - haderr = 1; - } - } - - if (haderr) - return (-1); - else - return (sectdone); -} - -static int -c302f_write_word(c302f_addr_t addr, c302f_word_t value) -{ - c302f_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = C302F_BNK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY); - - if ((stat & C302F_BNK_STAT_ERR) != 0) { - printf("flash program failed (stat = 0x%08lx) " - "at address 0x%08lx\n", (ulong)stat, (ulong)addr); - *addr = C302F_BNK_CMD_CLR_STAT; - retval = 3; - } - -done: - /* reset to read mode */ - *addr = C302F_BNK_CMD_RST; - - return (retval); -} - -#endif /* CONFIG_CMA302 */ - -unsigned long -flash_init(void) -{ - unsigned long total; - int i; - flash_info_t *fip; - - /* Init: no FLASHes known */ - for (i=0; isize; - fip++; -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) - /* not yet ... - cmbf_probe(fip, (cmbf_addr_t)CMA_MB_FLASH_BASE); - total += fip->size; - fip++; - */ -#endif - - /* - * protect monitor and environment sectors - */ - -#if CFG_MONITOR_BASE == CFG_FLASH_BASE - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return total; -} - -/*----------------------------------------------------------------------- - */ -void -flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F008S5: printf ("28F008S5\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 4) == 0) - printf ("\n "); - printf (" %2d - %08lX%s", i, - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -int -flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - void (*erase_init)(flash_info_t *, int); - int (*erase_poll)(flash_info_t *, int); - void (*reset)(flash_info_t *, int); - int rcode = 0; - -#ifdef FLASH_DEBUG - printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info(info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id) { - -#if defined(CONFIG_CMA302) - case FLASH_MAN_INTEL|FLASH_28F008S5: - erase_init = c302f_erase_init; - erase_poll = c302f_erase_poll; - reset = c302f_reset; - break; -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) - case FLASH_MAN_INTEL|FLASH_28F800_B: - case FLASH_MAN_AMD|FLASH_AM29F800B: - /* not yet ... - erase_init = cmbf_erase_init; - erase_poll = cmbf_erase_poll; - reset = cmbf_reset; - break; - */ -#endif - - default: - printf ("Flash type %08lx not supported - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sector%s will not be erased!\n", - prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - (*erase_init)(info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer(start); - - do { - now = get_timer(start); - - if (now - estart > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - break; - } - -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = (*erase_poll)(info, sect); - - if (sectdone < 0) { - haderr = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) { - printf (" failed\n"); - rcode = 1; - } - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - (*reset)(info, sect); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - write error - */ - -int -write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - ulong start, now, last; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - start = get_timer (0); - last = 0; - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - - /* show that we're waiting */ - now = get_timer(start); - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - write error - */ -static int -write_word(flash_info_t *info, ulong dest, ulong data) -{ - int retval; - - /* Check if Flash is (sufficiently) erased */ - if ((*(ulong *)dest & data) != data) { - return (2); - } - - switch (info->flash_id) { - -#if defined(CONFIG_CMA302) - case FLASH_MAN_INTEL|FLASH_28F008S5: - retval = c302f_write_word((c302f_addr_t)dest, (c302f_word_t)data); - break; -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) - case FLASH_MAN_INTEL|FLASH_28F800_B: - case FLASH_MAN_AMD|FLASH_AM29F800B: - /* not yet ... - retval = cmbf_write_word((cmbf_addr_t)dest, (cmbf_word_t)data); - */ - retval = 3; - break; -#endif - - default: - printf ("Flash type %08lx not supported - aborted\n", - info->flash_id); - retval = 3; - break; - } - - return (retval); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cogent/flash.h b/board/cogent/flash.h deleted file mode 100644 index 0b8d6aa..0000000 --- a/board/cogent/flash.h +++ /dev/null @@ -1,305 +0,0 @@ -/**************** DEFINES for Intel 28F008S5 FLASH chip **********************/ - -/* register addresses, valid only following a I8S5_CMD_RD_ID command */ -#define I8S5_ADDR_MAN 0x00000 /* manufacturer's id */ -#define I8S5_ADDR_DEV 0x00001 /* device id */ -#define I8S5_ADDR_CFGM 0x00003 /* master lock configuration */ -#define I8S5_ADDR_CFG(b) (((b)<<16)|2) /* block lock configuration */ - -/* Commands */ -#define I8S5_CMD_RST 0xFF /* reset flash */ -#define I8S5_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define I8S5_CMD_RD_STAT 0x70 /* read the status register */ -#define I8S5_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define I8S5_CMD_ERASE1 0x20 /* first word for block erase */ -#define I8S5_CMD_ERASE2 0xD0 /* second word for block erase */ -#define I8S5_CMD_PROG 0x40 /* program word command */ -#define I8S5_CMD_LOCK 0x60 /* first word for all lock commands */ -#define I8S5_CMD_SET_LOCK_BLK 0x01 /* 2nd word for set block lock bit */ -#define I8S5_CMD_SET_LOCK_MSTR 0xF1 /* 2nd word for set master lock bit */ -#define I8S5_CMD_CLR_LOCK_BLK 0xD0 /* 2nd word for clear block lock bit */ - -/* status register bits */ -#define I8S5_STAT_DPS 0x02 /* Device Protect Status */ -#define I8S5_STAT_PSS 0x04 /* Program Suspend Status */ -#define I8S5_STAT_VPPS 0x08 /* VPP Status */ -#define I8S5_STAT_PSLBS 0x10 /* Program and Set Lock Bit Status */ -#define I8S5_STAT_ECLBS 0x20 /* Erase and Clear Lock Bit Status */ -#define I8S5_STAT_ESS 0x40 /* Erase Suspend Status */ -#define I8S5_STAT_RDY 0x80 /* Write State Machine Status, 1=rdy */ - -#define I8S5_STAT_ERR (I8S5_STAT_VPPS | I8S5_STAT_DPS | \ - I8S5_STAT_ECLBS | I8S5_STAT_PSLBS) - -/* ID and Lock Configuration */ -#define I8S5_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ -#define I8S5_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define I8S5_RD_ID_DEV 0xA6 /* Device code = 0xA6, 28F008S5 */ - -/* dimensions */ -#define I8S5_NBLOCKS 16 /* a 28F008S5 consists of 16 blocks */ -#define I8S5_BLKSZ (64*1024) /* of 64Kbyte each */ -#define I8S5_SIZE (I8S5_BLKSZ * I8S5_NBLOCKS) - -/**************** DEFINES for Intel 28F800B5 FLASH chip **********************/ - -/* register addresses, valid only following a I8S5_CMD_RD_ID command */ -#define I8B5_ADDR_MAN 0x00000 /* manufacturer's id */ -#define I8B5_ADDR_DEV 0x00001 /* device id */ - -/* Commands */ -#define I8B5_CMD_RST 0xFF /* reset flash */ -#define I8B5_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define I8B5_CMD_RD_STAT 0x70 /* read the status register */ -#define I8B5_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define I8B5_CMD_ERASE1 0x20 /* first word for block erase */ -#define I8B5_CMD_ERASE2 0xD0 /* second word for block erase */ -#define I8B5_CMD_PROG 0x40 /* program word command */ - -/* status register bits */ -#define I8B5_STAT_VPPS 0x08 /* VPP Status */ -#define I8B5_STAT_DWS 0x10 /* Program and Set Lock Bit Status */ -#define I8B5_STAT_ES 0x20 /* Erase and Clear Lock Bit Status */ -#define I8B5_STAT_ESS 0x40 /* Erase Suspend Status */ -#define I8B5_STAT_RDY 0x80 /* Write State Machine Status, 1=rdy */ - -#define I8B5_STAT_ERR (I8B5_STAT_VPPS | I8B5_STAT_DWS | I8B5_STAT_ES) - -/* ID Configuration */ -#define I8B5_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define I8B5_RD_ID_DEV1 0x889D /* Device code = 0x889D, 28F800B5 */ - -/* dimensions */ -#define I8B5_NBLOCKS 8 /* a 28F008S5 consists of 16 blocks */ -#define I8B5_BLKSZ (128*1024) /* of 64Kbyte each */ -#define I8B5_SIZE (I8B5_BLKSZ * I8B5_NBLOCKS) - -/****************** DEFINES for Cogent CMA302 Flash **************************/ - -/* - * Quoted from the CMA302 manual: - * - * Although the CMA302 supports 64-bit reads, all writes must be done with - * word size only. When programming the CMA302, the FLASH devices appear as 2 - * banks of interleaved, 32-bit wide FLASH. Each 32-bit word consists of four - * 28F008S5 devices. The first bank is accessed when the word address is even, - * while the second bank is accessed when the word address is odd. This must - * be taken into account when programming the desired word. Also, when locking - * blocks, software must lock both banks. The CMA302 does not directly support - * byte writing. Programming and/or erasing individual bytes is done with - * selective use of the Write Command. By not placing the Write Command value - * on a particular byte lane, that byte will not be written with the following - * Write Data. Also, remember that within a byte lane (i.e. D0-7), there are - * two 28F008S5 devices, one for each bank or every other word. - * - * End quote. - * - * Each 28F008S5 is 8Mbit, with 8 bit wide data. i.e. each is 1Mbyte. The - * chips are arranged on the CMA302 in multiples of two banks, each bank having - * 4 chips. Each bank must be accessed as a single 32 bit wide device (i.e. - * aligned on a 32 bit boundary), with each byte lane within the 32 bits (0-3) - * going to each of the 4 chips and the word address selecting the bank, even - * being the low bank and odd the high bank. For 64bit reads, both banks are - * read simultaneously with the second bank on byte lanes 4-7. Each 28F008S5 - * consists of 16 64Kbyte "block"s. Before programming a byte, the block that - * the byte resides within must be erased. So if you want to program contiguous - * memory locations, you must erase all 8 chips at the same time. i.e. the - * flash on the CMA302 can be viewed as a number of 512Kbyte blocks. - * - * Note: I am going to treat banks as 8 Mbytes (1Meg of 64bit words), whereas - * the example code treats them as a pair of interleaved 1 Mbyte x 32bit banks. - */ - -typedef unsigned long c302f_word_t; /* 32 or 64 bit unsigned integer */ -typedef volatile c302f_word_t *c302f_addr_t; -typedef unsigned long c302f_size_t; /* want this big - at least 32 bit */ - -/* layout of banks on cma302 board */ -#define C302F_BNK_WIDTH 8 /* each bank is 8 chips wide */ -#define C302F_BNK_WSHIFT 3 /* log base 2 of C302F_BNK_WIDTH */ -#define C302F_BNK_NBLOCKS I8S5_NBLOCKS -#define C302F_BNK_BLKSZ (I8S5_BLKSZ * C302F_BNK_WIDTH) -#define C302F_BNK_SIZE (I8S5_SIZE * C302F_BNK_WIDTH) - -#define C302F_MAX_BANKS 2 /* up to 2 banks (8M each) on CMA302 */ - -/* align addresses and sizes to bank boundaries */ -#define C302F_BNK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ - & ~(C302F_BNK_WIDTH - 1))) -#define C302F_BNK_SIZE_ALIGN(s) ((c302f_size_t)C302F_BNK_ADDR_ALIGN( \ - (c302f_size_t)(s) + (C302F_BNK_WIDTH - 1))) - -/* align addresses and sizes to block boundaries */ -#define C302F_BLK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ - & ~(C302F_BNK_BLKSZ - 1))) -#define C302F_BLK_SIZE_ALIGN(s) ((c302f_size_t)C302F_BLK_ADDR_ALIGN( \ - (c302f_size_t)(s) + (C302F_BNK_BLKSZ - 1))) - -/* add a byte offset to a flash address */ -#define C302F_ADDR_ADD_BYTEOFF(a,o) \ - (c302f_addr_t)((c302f_size_t)(a) + (o)) - -/* get base address of bank b, given flash base address a */ -#define C302F_BNK_ADDR_BASE(a,b) \ - C302F_ADDR_ADD_BYTEOFF((a), \ - (c302f_size_t)(b) * C302F_BNK_SIZE) - -/* adjust an address a (within a bank) to next word, block or bank */ -#define C302F_BNK_ADDR_NEXT_WORD(a) \ - C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_WIDTH) -#define C302F_BNK_ADDR_NEXT_BLK(a) \ - C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_BLKSZ) -#define C302F_BNK_ADDR_NEXT_BNK(a) \ - C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_SIZE) - -/* get bank address of chip register r given a bank base address a */ -#define C302F_BNK_ADDR_I8S5REG(a,r) \ - C302F_ADDR_ADD_BYTEOFF((a), \ - (r) << C302F_BNK_WSHIFT) - -/* make a bank representation for each chip address */ - -#define C302F_BNK_ADDR_MAN(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_MAN) -#define C302F_BNK_ADDR_DEV(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_DEV) -#define C302F_BNK_ADDR_CFGM(a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFGM) -#define C302F_BNK_ADDR_CFG(b,a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG(b)) - -/* - * replicate a chip cmd/stat/rd value into each byte position within a word - * so that multiple chips are accessed in a single word i/o operation - * - * this must be as wide as the c302f_word_t type - */ -#define C302F_FILL_WORD(o) (((unsigned long)(o) << 24) | \ - ((unsigned long)(o) << 16) | \ - ((unsigned long)(o) << 8) | \ - (unsigned long)(o)) - -/* make a bank representation for each chip cmd/stat/rd value */ - -/* Commands */ -#define C302F_BNK_CMD_RST C302F_FILL_WORD(I8S5_CMD_RST) -#define C302F_BNK_CMD_RD_ID C302F_FILL_WORD(I8S5_CMD_RD_ID) -#define C302F_BNK_CMD_RD_STAT C302F_FILL_WORD(I8S5_CMD_RD_STAT) -#define C302F_BNK_CMD_CLR_STAT C302F_FILL_WORD(I8S5_CMD_CLR_STAT) -#define C302F_BNK_CMD_ERASE1 C302F_FILL_WORD(I8S5_CMD_ERASE1) -#define C302F_BNK_CMD_ERASE2 C302F_FILL_WORD(I8S5_CMD_ERASE2) -#define C302F_BNK_CMD_PROG C302F_FILL_WORD(I8S5_CMD_PROG) -#define C302F_BNK_CMD_LOCK C302F_FILL_WORD(I8S5_CMD_LOCK) -#define C302F_BNK_CMD_SET_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_SET_LOCK_BLK) -#define C302F_BNK_CMD_SET_LOCK_MSTR C302F_FILL_WORD(I8S5_CMD_SET_LOCK_MSTR) -#define C302F_BNK_CMD_CLR_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define C302F_BNK_STAT_DPS C302F_FILL_WORD(I8S5_STAT_DPS) -#define C302F_BNK_STAT_PSS C302F_FILL_WORD(I8S5_STAT_PSS) -#define C302F_BNK_STAT_VPPS C302F_FILL_WORD(I8S5_STAT_VPPS) -#define C302F_BNK_STAT_PSLBS C302F_FILL_WORD(I8S5_STAT_PSLBS) -#define C302F_BNK_STAT_ECLBS C302F_FILL_WORD(I8S5_STAT_ECLBS) -#define C302F_BNK_STAT_ESS C302F_FILL_WORD(I8S5_STAT_ESS) -#define C302F_BNK_STAT_RDY C302F_FILL_WORD(I8S5_STAT_RDY) - -#define C302F_BNK_STAT_ERR C302F_FILL_WORD(I8S5_STAT_ERR) - -/* ID and Lock Configuration */ -#define C302F_BNK_RD_ID_LOCK C302F_FILL_WORD(I8S5_RD_ID_LOCK) -#define C302F_BNK_RD_ID_MAN C302F_FILL_WORD(I8S5_RD_ID_MAN) -#define C302F_BNK_RD_ID_DEV C302F_FILL_WORD(I8S5_RD_ID_DEV) - -/*************** DEFINES for Cogent Motherboard Flash ************************/ - -typedef unsigned short cmbf_word_t; /* 16 bit unsigned integer */ -typedef volatile cmbf_word_t *cmbf_addr_t; -typedef unsigned long cmbf_size_t; /* want this big - at least 32 bit */ - -/* layout of banks on cogent motherboard - only 1 bank, 16 bit wide */ -#define CMBF_BNK_WIDTH 1 /* each bank is one chip wide */ -#define CMBF_BNK_WSHIFT 0 /* log base 2 of CMBF_BNK_WIDTH */ -#define CMBF_BNK_NBLOCKS I8B5_NBLOCKS -#define CMBF_BNK_BLKSZ (I8B5_BLKSZ * CMBF_BNK_WIDTH) -#define CMBF_BNK_SIZE (I8B5_SIZE * CMBF_BNK_WIDTH) - -#define CMBF_MAX_BANKS 1 /* only 1 x 1Mbyte bank on cogent m/b */ - -/* align addresses and sizes to bank boundaries */ -#define CMBF_BNK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ - & ~(CMBF_BNK_WIDTH - 1))) -#define CMBF_BNK_SIZE_ALIGN(s) ((c302f_size_t)CMBF_BNK_ADDR_ALIGN( \ - (c302f_size_t)(s) + (CMBF_BNK_WIDTH - 1))) - -/* align addresses and sizes to block boundaries */ -#define CMBF_BLK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \ - & ~(CMBF_BNK_BLKSZ - 1))) -#define CMBF_BLK_SIZE_ALIGN(s) ((c302f_size_t)CMBF_BLK_ADDR_ALIGN( \ - (c302f_size_t)(s) + (CMBF_BNK_BLKSZ - 1))) - -/* add a byte offset to a flash address */ -#define CMBF_ADDR_ADD_BYTEOFF(a,o) \ - (c302f_addr_t)((c302f_size_t)(a) + (o)) - -/* get base address of bank b, given flash base address a */ -#define CMBF_BNK_ADDR_BASE(a,b) \ - CMBF_ADDR_ADD_BYTEOFF((a), \ - (c302f_size_t)(b) * CMBF_BNK_SIZE) - -/* adjust an address a (within a bank) to next word, block or bank */ -#define CMBF_BNK_ADDR_NEXT_WORD(a) \ - CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_WIDTH) -#define CMBF_BNK_ADDR_NEXT_BLK(a) \ - CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_BLKSZ) -#define CMBF_BNK_ADDR_NEXT_BNK(a) \ - CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_SIZE) - -/* get bank address of chip register r given a bank base address a */ -#define CMBF_BNK_ADDR_I8B5REG(a,r) \ - CMBF_ADDR_ADD_BYTEOFF((a), \ - (r) << CMBF_BNK_WSHIFT) - -/* make a bank representation for each chip address */ - -#define CMBF_BNK_ADDR_MAN(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_MAN) -#define CMBF_BNK_ADDR_DEV(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_DEV) -#define CMBF_BNK_ADDR_CFGM(a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFGM) -#define CMBF_BNK_ADDR_CFG(b,a) CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG(b)) - -/* - * replicate a chip cmd/stat/rd value into each byte position within a word - * so that multiple chips are accessed in a single word i/o operation - * - * this must be as wide as the c302f_word_t type - */ -#define CMBF_FILL_WORD(o) (((unsigned long)(o) << 24) | \ - ((unsigned long)(o) << 16) | \ - ((unsigned long)(o) << 8) | \ - (unsigned long)(o)) - -/* make a bank representation for each chip cmd/stat/rd value */ - -/* Commands */ -#define CMBF_BNK_CMD_RST CMBF_FILL_WORD(I8B5_CMD_RST) -#define CMBF_BNK_CMD_RD_ID CMBF_FILL_WORD(I8B5_CMD_RD_ID) -#define CMBF_BNK_CMD_RD_STAT CMBF_FILL_WORD(I8B5_CMD_RD_STAT) -#define CMBF_BNK_CMD_CLR_STAT CMBF_FILL_WORD(I8B5_CMD_CLR_STAT) -#define CMBF_BNK_CMD_ERASE1 CMBF_FILL_WORD(I8B5_CMD_ERASE1) -#define CMBF_BNK_CMD_ERASE2 CMBF_FILL_WORD(I8B5_CMD_ERASE2) -#define CMBF_BNK_CMD_PROG CMBF_FILL_WORD(I8B5_CMD_PROG) -#define CMBF_BNK_CMD_LOCK CMBF_FILL_WORD(I8B5_CMD_LOCK) -#define CMBF_BNK_CMD_SET_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_BLK) -#define CMBF_BNK_CMD_SET_LOCK_MSTR CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_MSTR) -#define CMBF_BNK_CMD_CLR_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define CMBF_BNK_STAT_DPS CMBF_FILL_WORD(I8B5_STAT_DPS) -#define CMBF_BNK_STAT_PSS CMBF_FILL_WORD(I8B5_STAT_PSS) -#define CMBF_BNK_STAT_VPPS CMBF_FILL_WORD(I8B5_STAT_VPPS) -#define CMBF_BNK_STAT_PSLBS CMBF_FILL_WORD(I8B5_STAT_PSLBS) -#define CMBF_BNK_STAT_ECLBS CMBF_FILL_WORD(I8B5_STAT_ECLBS) -#define CMBF_BNK_STAT_ESS CMBF_FILL_WORD(I8B5_STAT_ESS) -#define CMBF_BNK_STAT_RDY CMBF_FILL_WORD(I8B5_STAT_RDY) - -#define CMBF_BNK_STAT_ERR CMBF_FILL_WORD(I8B5_STAT_ERR) - -/* ID and Lock Configuration */ -#define CMBF_BNK_RD_ID_LOCK CMBF_FILL_WORD(I8B5_RD_ID_LOCK) -#define CMBF_BNK_RD_ID_MAN CMBF_FILL_WORD(I8B5_RD_ID_MAN) -#define CMBF_BNK_RD_ID_DEV CMBF_FILL_WORD(I8B5_RD_ID_DEV) diff --git a/board/cogent/kbm.c b/board/cogent/kbm.c deleted file mode 100644 index 8496402..0000000 --- a/board/cogent/kbm.c +++ /dev/null @@ -1,3 +0,0 @@ -/* keyboard/mouse not implemented yet */ - -int cma_kbm_not_implemented = 1; diff --git a/board/cogent/kbm.h b/board/cogent/kbm.h deleted file mode 100644 index 7eb419c..0000000 --- a/board/cogent/kbm.h +++ /dev/null @@ -1,79 +0,0 @@ -/* keyboard/mouse not implemented yet */ - -extern int cma_kbm_not_implemented; - -/**************** DEFINES for H8542B Keyboard/Mouse Controller ***************/ - -/* - * note the auxillary port is used to control the mouse - */ - -/* 8542B Commands (Sent to the Command Port) */ -#define HT8542_CMD_SET_BYTE 0x60 /* Set the command byte */ -#define HT8542_CMD_GET_BYTE 0x20 /* Get the command byte */ -#define HT8542_CMD_KBD_OBUFF 0xD2 /* Write to HT8542 Kbd Output Buffer */ -#define HT8542_CMD_AUX_OBUFF 0xD3 /* Write to HT8542 Mse Output Buffer */ -#define HT8542_CMD_AUX_WRITE 0xD4 /* Write to Mouse Port */ -#define HT8542_CMD_AUX_OFF 0xA7 /* Disable Mouse Port */ -#define HT8542_CMD_AUX_ON 0xA8 /* Re-Enable Mouse Port */ -#define HT8542_CMD_AUX_TEST 0xA9 /* Test for the presence of a Mouse */ -#define HT8542_CMD_DIAG 0xAA /* Start Diagnostics */ -#define HT8542_CMD_KBD_TEST 0xAB /* Test for presence of a keyboard */ -#define HT8542_CMD_KBD_OFF 0xAD /* Disable Kbd Port (use KBD_DAT_ON) */ -#define HT8542_CMD_KBD_ON 0xAE /* Enable Kbd Port (use KBD_DAT_OFF) */ - -/* HT8542B cmd byte set by KBD_CMD_SET_BYTE and retrieved by KBD_CMD_GET_BYTE */ -#define HT8542_CMD_BYTE_TRANS 0x40 -#define HT8542_CMD_BYTE_AUX_OFF 0x20 /* 1 = mse port disabled, 0 = enabled */ -#define HT8542_CMD_BYTE_KBD_OFF 0x10 /* 1 = kbd port disabled, 0 = enabled */ -#define HT8542_CMD_BYTE_OVER 0x08 /* 1 = override keyboard lock */ -#define HT8542_CMD_BYTE_RES 0x04 /* reserved */ -#define HT8542_CMD_BYTE_AUX_INT 0x02 /* 1 = enable mouse interrupt */ -#define HT8542_CMD_BYTE_KBD_INT 0x01 /* 1 = enable keyboard interrupt */ - -/* Keyboard Commands (Sent to the Data Port) */ -#define KBD_CMD_LED 0xED /* Set Keyboard LEDS with next byte */ -#define KBD_CMD_ECHO 0xEE /* Echo - we get 0xFA, 0xEE back */ -#define KBD_CMD_MODE 0xF0 /* set scan code mode with next byte */ -#define KBD_CMD_ID 0xF2 /* get keyboard/mouse ID */ -#define KBD_CMD_RPT 0xF3 /* Set Repeat Rate and Delay 2nd Byte */ -#define KBD_CMD_ON 0xF4 /* Enable keyboard */ -#define KBD_CMD_OFF 0xF5 /* Disables Scanning, Resets to Def */ -#define KBD_CMD_DEF 0xF6 /* Reverts kbd to default settings */ -#define KBD_CMD_RST 0xFF /* Reset - should get 0xFA, 0xAA back */ - -/* Set LED second bit defines */ -#define KBD_CMD_LED_SCROLL 0x01 /* Set SCROLL LOCK LED on */ -#define KBD_CMD_LED_NUM 0x02 /* Set NUM LOCK LED on */ -#define KBD_CMD_LED_CAPS 0x04 /* Set CAPS LOCK LED on */ - -/* Set Mode second byte defines */ -#define KBD_CMD_MODE_STAT 0x00 /* get current scan code mode */ -#define KBD_CMD_MODE_SCAN1 0x01 /* set mode to scan code 1 */ -#define KBD_CMD_MODE_SCAN2 0x02 /* set mode to scan code 2 */ -#define KBD_CMD_MODE_SCAN3 0x03 /* set mode to scan code 3 */ - -/* Keyboard/Mouse ID Codes */ -#define KBD_CMD_ID_1ST 0xAB /* 1st byte is 0xAB, 2nd is actual ID */ -#define KBD_CMD_ID_KBD 0x83 /* Keyboard */ -#define KBD_CMD_ID_MOUSE 0x00 /* Mouse */ - -/* Keyboard Data Return Defines */ -#define KBD_STAT_OVER 0x00 /* Buffer Overrun */ -#define KBD_STAT_DIAG_OK 0x55 /* Internal Self Test OK */ -#define KBD_STAT_RST_OK 0xAA /* Reset Complete */ -#define KBD_STAT_ECHO 0xEE /* Echo Command Return */ -#define KBD_STAT_BRK 0xF0 /* Prefix for Break Key Code */ -#define KBD_STAT_ACK 0xFA /* Received after all commands */ -#define KBD_STAT_DIAG_FAIL 0xFD /* Internal Self Test Failed */ -#define KBD_STAT_RESEND 0xFE /* Resend Last Command */ - -/* HT8542B Status Register Bit Defines */ -#define HT8542_STAT_OBF 0x01 /* 1 = output buffer is full */ -#define HT8542_STAT_IBF 0x02 /* 1 = input buffer is full */ -#define HT8542_STAT_SYS 0x04 /* system flag - unused */ -#define HT8542_STAT_CMD 0x08 /* 1 = cmd in input buffer, 0 = data */ -#define HT8542_STAT_INH 0x10 /* 1 = Inhibit - unused */ -#define HT8542_STAT_TX 0x20 /* 1 = Transmit Timeout has occured */ -#define HT8542_STAT_RX 0x40 /* 1 = Receive Timeout has occured */ -#define HT8542_STAT_PERR 0x80 /* 1 = Parity Error from Keyboard */ diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c deleted file mode 100644 index 814b4c8..0000000 --- a/board/cogent/lcd.c +++ /dev/null @@ -1,245 +0,0 @@ -/* most of this is taken from the file */ -/* hal/powerpc/cogent/current/src/hal_diag.c in the */ -/* Cygnus eCos source. Here is the copyright notice: */ -/* */ -/*============================================================================= */ -/* */ -/* hal_diag.c */ -/* */ -/* HAL diagnostic output code */ -/* */ -/*============================================================================= */ -/*####COPYRIGHTBEGIN#### */ -/* */ -/* ------------------------------------------- */ -/* The contents of this file are subject to the Cygnus eCos Public License */ -/* Version 1.0 (the "License"); you may not use this file except in */ -/* compliance with the License. You may obtain a copy of the License at */ -/* http://sourceware.cygnus.com/ecos */ -/* */ -/* Software distributed under the License is distributed on an "AS IS" */ -/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */ -/* License for the specific language governing rights and limitations under */ -/* the License. */ -/* */ -/* The Original Code is eCos - Embedded Cygnus Operating System, released */ -/* September 30, 1998. */ -/* */ -/* The Initial Developer of the Original Code is Cygnus. Portions created */ -/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */ -/* ------------------------------------------- */ -/* */ -/*####COPYRIGHTEND#### */ -/*============================================================================= */ -/*#####DESCRIPTIONBEGIN#### */ -/* */ -/* Author(s): nickg, jskov */ -/* Contributors: nickg, jskov */ -/* Date: 1999-03-23 */ -/* Purpose: HAL diagnostic output */ -/* Description: Implementations of HAL diagnostic output support. */ -/* */ -/*####DESCRIPTIONEND#### */ -/* */ -/*============================================================================= */ - -/*----------------------------------------------------------------------------- */ -/* Cogent board specific LCD code */ - -#include -#include -#include - -static char lines[2][LCD_LINE_LENGTH+1]; -static int curline; -static int linepos; -static int heartbeat_active; -/* make the next two strings exactly LCD_LINE_LENGTH (16) chars long */ -/* pad to the right with spaces if necessary */ -static char init_line0[LCD_LINE_LENGTH+1] = "U-Boot Cogent "; -static char init_line1[LCD_LINE_LENGTH+1] = "mjj, 11 Aug 2000"; - -static inline unsigned char -lcd_read_status(cma_mb_lcd *clp) -{ - /* read the Busy Status Register */ - return (cma_mb_reg_read(&clp->lcd_bsr)); -} - -static inline void -lcd_wait_not_busy(cma_mb_lcd *clp) -{ - /* - * wait for not busy - * Note: It seems that the LCD isn't quite ready to process commands - * when it clears the BUSY flag. Reading the status address an extra - * time seems to give it enough breathing room. - */ - - while (lcd_read_status(clp) & LCD_STAT_BUSY) - ; - - (void)lcd_read_status(clp); -} - -static inline void -lcd_write_command(cma_mb_lcd *clp, unsigned char cmd) -{ - lcd_wait_not_busy(clp); - - /* write the Command Register */ - cma_mb_reg_write(&clp->lcd_cmd, cmd); -} - -static inline void -lcd_write_data(cma_mb_lcd *clp, unsigned char data) -{ - lcd_wait_not_busy(clp); - - /* write the Current Character Register */ - cma_mb_reg_write(&clp->lcd_ccr, data); -} - -static inline void -lcd_dis(int addr, char *string) -{ - cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE; - int pos, linelen; - - linelen = LCD_LINE_LENGTH; - if (heartbeat_active && addr == LCD_LINE0) - linelen--; - - lcd_write_command(clp, LCD_CMD_ADD + addr); - for (pos = 0; *string != '\0' && pos < linelen; pos++) - lcd_write_data(clp, *string++); -} - -void -lcd_init(void) -{ - cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE; - int i; - - /* configure the lcd for 8 bits/char, 2 lines and 5x7 dot matrix */ - lcd_write_command(clp, LCD_CMD_MODE); - - /* turn the LCD display on */ - lcd_write_command(clp, LCD_CMD_DON); - - curline = 0; - linepos = 0; - - for (i = 0; i < LCD_LINE_LENGTH; i++) { - lines[0][i] = init_line0[i]; - lines[1][i] = init_line1[i]; - } - - lines[0][LCD_LINE_LENGTH] = lines[1][LCD_LINE_LENGTH] = 0; - - lcd_dis(LCD_LINE0, lines[0]); - lcd_dis(LCD_LINE1, lines[1]); - - printf("HD44780 2 line x %d char display\n", LCD_LINE_LENGTH); -} - -void -lcd_write_char(const char c) -{ - int i, linelen; - - /* ignore CR */ - if (c == '\r') - return; - - linelen = LCD_LINE_LENGTH; - if (heartbeat_active && curline == 0) - linelen--; - - if (c == '\n') { - lcd_dis(LCD_LINE0, &lines[curline^1][0]); - lcd_dis(LCD_LINE1, &lines[curline][0]); - - /* Do a line feed */ - curline ^= 1; - linelen = LCD_LINE_LENGTH; - if (heartbeat_active && curline == 0) - linelen--; - linepos = 0; - - for (i = 0; i < linelen; i++) - lines[curline][i] = ' '; - - return; - } - - /* Only allow to be output if there is room on the LCD line */ - if (linepos < linelen) - lines[curline][linepos++] = c; -} - -void -lcd_flush(void) -{ - lcd_dis(LCD_LINE1, &lines[curline][0]); -} - -void -lcd_write_string(const char *s) -{ - char *p; - - for (p = (char *)s; *p != '\0'; p++) - lcd_write_char(*p); -} - -void -lcd_printf(const char *fmt, ...) -{ - va_list args; - char buf[CFG_PBSIZE]; - - va_start(args, fmt); - (void)vsprintf(buf, fmt, args); - va_end(args); - - lcd_write_string(buf); -} - -void -lcd_heartbeat(void) -{ - cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE; -#if 0 - static char rotchars[] = { '|', '/', '-', '\\' }; -#else - /* HD44780 Rom Code A00 has no backslash */ - static char rotchars[] = { '|', '/', '-', '\315' }; -#endif - static int rotator_index = 0; - - heartbeat_active = 1; - - /* write the address */ - lcd_write_command(clp, LCD_CMD_ADD + LCD_LINE0 + (LCD_LINE_LENGTH - 1)); - - /* write the next char in the sequence */ - lcd_write_data(clp, rotchars[rotator_index]); - - if (++rotator_index >= (sizeof rotchars / sizeof rotchars[0])) - rotator_index = 0; -} - -#ifdef CONFIG_SHOW_ACTIVITY -void board_show_activity (ulong timestamp) -{ -#ifdef CONFIG_STATUS_LED - if ((timestamp % (CFG_HZ / 2) == 0) - lcd_heartbeat (); -#endif -} - -void show_activity(int arg) -{ -} -#endif diff --git a/board/cogent/lcd.h b/board/cogent/lcd.h deleted file mode 100644 index 1056eea..0000000 --- a/board/cogent/lcd.h +++ /dev/null @@ -1,84 +0,0 @@ -/* most of this is taken from the file */ -/* hal/powerpc/cogent/current/src/hal_diag.c in the */ -/* Cygnus eCos source. Here is the copyright notice: */ -/* */ -/*============================================================================= */ -/* */ -/* hal_diag.c */ -/* */ -/* HAL diagnostic output code */ -/* */ -/*============================================================================= */ -/*####COPYRIGHTBEGIN#### */ -/* */ -/* ------------------------------------------- */ -/* The contents of this file are subject to the Cygnus eCos Public License */ -/* Version 1.0 (the "License"); you may not use this file except in */ -/* compliance with the License. You may obtain a copy of the License at */ -/* http://sourceware.cygnus.com/ecos */ -/* */ -/* Software distributed under the License is distributed on an "AS IS" */ -/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the */ -/* License for the specific language governing rights and limitations under */ -/* the License. */ -/* */ -/* The Original Code is eCos - Embedded Cygnus Operating System, released */ -/* September 30, 1998. */ -/* */ -/* The Initial Developer of the Original Code is Cygnus. Portions created */ -/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. */ -/* ------------------------------------------- */ -/* */ -/*####COPYRIGHTEND#### */ -/*============================================================================= */ -/*#####DESCRIPTIONBEGIN#### */ -/* */ -/* Author(s): nickg, jskov */ -/* Contributors: nickg, jskov */ -/* Date: 1999-03-23 */ -/* Purpose: HAL diagnostic output */ -/* Description: Implementations of HAL diagnostic output support. */ -/* */ -/*####DESCRIPTIONEND#### */ -/* */ -/*============================================================================= */ - -/* FEMA 162B 16 character x 2 line LCD */ - -/* status register bit definitions */ -#define LCD_STAT_BUSY 0x80 /* 1 = display busy */ -#define LCD_STAT_ADD 0x7F /* bits 0-6 return current display address */ - -/* command register definitions */ -#define LCD_CMD_RST 0x01 /* clear entire display and reset display addr */ -#define LCD_CMD_HOME 0x02 /* reset display address and reset any shifting */ -#define LCD_CMD_ECL 0x04 /* move cursor left one pos on next data write */ -#define LCD_CMD_ESL 0x05 /* shift display left one pos on next data write */ -#define LCD_CMD_ECR 0x06 /* move cursor right one pos on next data write */ -#define LCD_CMD_ESR 0x07 /* shift disp right one pos on next data write */ -#define LCD_CMD_DOFF 0x08 /* display off, cursor off, blinking off */ -#define LCD_CMD_BL 0x09 /* blink character at current cursor position */ -#define LCD_CMD_CUR 0x0A /* enable cursor on */ -#define LCD_CMD_DON 0x0C /* turn display on */ -#define LCD_CMD_CL 0x10 /* move cursor left one position */ -#define LCD_CMD_SL 0x14 /* shift display left one position */ -#define LCD_CMD_CR 0x18 /* move cursor right one position */ -#define LCD_CMD_SR 0x1C /* shift display right one position */ -#define LCD_CMD_MODE 0x38 /* sets 8 bits, 2 lines, 5x7 characters */ -#define LCD_CMD_ACG 0x40 /* bits 0-5 sets character generator address */ -#define LCD_CMD_ADD 0x80 /* bits 0-6 sets display data addr to line 1 + */ - -/* LCD status values */ -#define LCD_OK 0x00 -#define LCD_ERR 0x01 - -#define LCD_LINE0 0x00 -#define LCD_LINE1 0x40 - -#define LCD_LINE_LENGTH 16 - -extern void lcd_init(void); -extern void lcd_write_char(const char); -extern void lcd_flush(void); -extern void lcd_write_string(const char *); -extern void lcd_printf(const char *, ...); diff --git a/board/cogent/mb.c b/board/cogent/mb.c deleted file mode 100644 index 917132b..0000000 --- a/board/cogent/mb.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_8260) - -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ {0, 0, 0, 0, 0, 0}, - /* PA30 */ {0, 0, 0, 0, 0, 0}, - /* PA29 */ {0, 0, 0, 0, 0, 0}, - /* PA28 */ {0, 0, 0, 0, 0, 0}, - /* PA27 */ {0, 0, 0, 0, 0, 0}, - /* PA26 */ {0, 0, 0, 0, 0, 0}, - /* PA25 */ {0, 0, 0, 0, 0, 0}, - /* PA24 */ {0, 0, 0, 0, 0, 0}, - /* PA23 */ {0, 0, 0, 0, 0, 0}, - /* PA22 */ {0, 0, 0, 0, 0, 0}, - /* PA21 */ {0, 0, 0, 0, 0, 0}, - /* PA20 */ {0, 0, 0, 0, 0, 0}, - /* PA19 */ {0, 0, 0, 0, 0, 0}, - /* PA18 */ {0, 0, 0, 0, 0, 0}, - /* PA17 */ {0, 0, 0, 0, 0, 0}, - /* PA16 */ {0, 0, 0, 0, 0, 0}, - /* PA15 */ {0, 0, 0, 0, 0, 0}, - /* PA14 */ {0, 0, 0, 0, 0, 0}, - /* PA13 */ {0, 0, 0, 0, 0, 0}, - /* PA12 */ {0, 0, 0, 0, 0, 0}, - /* PA11 */ {0, 0, 0, 0, 0, 0}, - /* PA10 */ {0, 0, 0, 0, 0, 0}, - /* PA9 */ {1, 1, 0, 1, 0, 0}, - /* SMC2 TXD */ - /* PA8 */ {1, 1, 0, 0, 0, 0}, - /* SMC2 RXD */ - /* PA7 */ {0, 0, 0, 0, 0, 0}, - /* PA6 */ {0, 0, 0, 0, 0, 0}, - /* PA5 */ {0, 0, 0, 0, 0, 0}, - /* PA4 */ {0, 0, 0, 0, 0, 0}, - /* PA3 */ {0, 0, 0, 0, 0, 0}, - /* PA2 */ {0, 0, 0, 0, 0, 0}, - /* PA1 */ {0, 0, 0, 0, 0, 0}, - /* PA0 */ {0, 0, 0, 0, 0, 0} - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ {0, 0, 0, 0, 0, 0}, - /* PB30 */ {0, 0, 0, 0, 0, 0}, - /* PB29 */ {0, 0, 0, 0, 0, 0}, - /* PB28 */ {0, 0, 0, 0, 0, 0}, - /* PB27 */ {0, 0, 0, 0, 0, 0}, - /* PB26 */ {0, 0, 0, 0, 0, 0}, - /* PB25 */ {0, 0, 0, 0, 0, 0}, - /* PB24 */ {0, 0, 0, 0, 0, 0}, - /* PB23 */ {0, 0, 0, 0, 0, 0}, - /* PB22 */ {0, 0, 0, 0, 0, 0}, - /* PB21 */ {0, 0, 0, 0, 0, 0}, - /* PB20 */ {0, 0, 0, 0, 0, 0}, - /* PB19 */ {0, 0, 0, 0, 0, 0}, - /* PB18 */ {0, 0, 0, 0, 0, 0}, - /* PB17 */ {0, 0, 0, 0, 0, 0}, - /* PB16 */ {0, 0, 0, 0, 0, 0}, - /* PB15 */ {0, 0, 0, 0, 0, 0}, - /* PB14 */ {0, 0, 0, 0, 0, 0}, - /* PB13 */ {0, 0, 0, 0, 0, 0}, - /* PB12 */ {0, 0, 0, 0, 0, 0}, - /* PB11 */ {0, 0, 0, 0, 0, 0}, - /* PB10 */ {0, 0, 0, 0, 0, 0}, - /* PB9 */ {0, 0, 0, 0, 0, 0}, - /* PB8 */ {0, 0, 0, 0, 0, 0}, - /* PB7 */ {0, 0, 0, 0, 0, 0}, - /* PB6 */ {0, 0, 0, 0, 0, 0}, - /* PB5 */ {0, 0, 0, 0, 0, 0}, - /* PB4 */ {0, 0, 0, 0, 0, 0}, - /* PB3 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PB2 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PB1 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PB0 */ {0, 0, 0, 0, 0, 0} - /* pin doesn't exist */ - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ {0, 0, 0, 0, 0, 0}, - /* PC30 */ {0, 0, 0, 0, 0, 0}, - /* PC29 */ {0, 0, 0, 0, 0, 0}, - /* PC28 */ {0, 0, 0, 0, 0, 0}, - /* PC27 */ {0, 0, 0, 0, 0, 0}, - /* PC26 */ {0, 0, 0, 0, 0, 0}, - /* PC25 */ {0, 0, 0, 0, 0, 0}, - /* PC24 */ {0, 0, 0, 0, 0, 0}, - /* PC23 */ {0, 0, 0, 0, 0, 0}, - /* PC22 */ {0, 0, 0, 0, 0, 0}, - /* PC21 */ {0, 0, 0, 0, 0, 0}, - /* PC20 */ {0, 0, 0, 0, 0, 0}, - /* PC19 */ {0, 0, 0, 0, 0, 0}, - /* PC18 */ {0, 0, 0, 0, 0, 0}, - /* PC17 */ {0, 0, 0, 0, 0, 0}, - /* PC16 */ {0, 0, 0, 0, 0, 0}, - /* PC15 */ {0, 0, 0, 0, 0, 0}, - /* PC14 */ {0, 0, 0, 0, 0, 0}, - /* PC13 */ {0, 0, 0, 0, 0, 0}, - /* PC12 */ {0, 0, 0, 0, 0, 0}, - /* PC11 */ {0, 0, 0, 0, 0, 0}, - /* PC10 */ {0, 0, 0, 0, 0, 0}, - /* PC9 */ {0, 0, 0, 0, 0, 0}, - /* PC8 */ {0, 0, 0, 0, 0, 0}, - /* PC7 */ {0, 0, 0, 0, 0, 0}, - /* PC6 */ {0, 0, 0, 0, 0, 0}, - /* PC5 */ {0, 0, 0, 0, 0, 0}, - /* PC4 */ {0, 0, 0, 0, 0, 0}, - /* PC3 */ {0, 0, 0, 0, 0, 0}, - /* PC2 */ {0, 0, 0, 0, 0, 0}, - /* PC1 */ {0, 0, 0, 0, 0, 0}, - /* PC0 */ {0, 0, 0, 0, 0, 0} - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ {0, 0, 0, 0, 0, 0}, - /* PD30 */ {0, 0, 0, 0, 0, 0}, - /* PD29 */ {0, 0, 0, 0, 0, 0}, - /* PD28 */ {0, 0, 0, 0, 0, 0}, - /* PD27 */ {0, 0, 0, 0, 0, 0}, - /* PD26 */ {0, 0, 0, 0, 0, 0}, - /* PD25 */ {0, 0, 0, 0, 0, 0}, - /* PD24 */ {0, 0, 0, 0, 0, 0}, - /* PD23 */ {0, 0, 0, 0, 0, 0}, - /* PD22 */ {0, 0, 0, 0, 0, 0}, - /* PD21 */ {0, 0, 0, 0, 0, 0}, - /* PD20 */ {0, 0, 0, 0, 0, 0}, - /* PD19 */ {0, 0, 0, 0, 0, 0}, - /* PD18 */ {0, 0, 0, 0, 0, 0}, - /* PD17 */ {0, 0, 0, 0, 0, 0}, - /* PD16 */ {0, 0, 0, 0, 0, 0}, - /* PD15 */ {1, 1, 1, 0, 0, 0}, - /* I2C SDA */ - /* PD14 */ {1, 1, 1, 0, 0, 0}, - /* I2C SCL */ - /* PD13 */ {0, 0, 0, 0, 0, 0}, - /* PD12 */ {0, 0, 0, 0, 0, 0}, - /* PD11 */ {0, 0, 0, 0, 0, 0}, - /* PD10 */ {0, 0, 0, 0, 0, 0}, - /* PD9 */ {1, 1, 0, 1, 0, 0}, - /* SMC1 TXD */ - /* PD8 */ {1, 1, 0, 0, 0, 0}, - /* SMC1 RXD */ - /* PD7 */ {0, 0, 0, 0, 0, 0}, - /* PD6 */ {0, 0, 0, 0, 0, 0}, - /* PD5 */ {0, 0, 0, 0, 0, 0}, - /* PD4 */ {0, 0, 0, 0, 0, 0}, - /* PD3 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PD2 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PD1 */ {0, 0, 0, 0, 0, 0}, - /* pin doesn't exist */ - /* PD0 */ {0, 0, 0, 0, 0, 0} - /* pin doesn't exist */ - } -}; - -#endif /* CONFIG_8260 */ - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a " - COGENT_CPU_MODULE " CPU Module\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations while still - * running in flash - */ - -int misc_init_f (void) -{ - printf ("DIPSW: "); - dipsw_init (); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ -#ifdef CONFIG_CMA111 - return (32L * 1024L * 1024L); -#else - unsigned char dipsw_val; - int dual, size0, size1; - long int memsize; - - dipsw_val = dipsw_cooked (); - - dual = dipsw_val & 0x01; - size0 = (dipsw_val & 0x08) >> 3; - size1 = (dipsw_val & 0x04) >> 2; - - if (size0) - if (size1) - memsize = 16L * 1024L * 1024L; - else - memsize = 1L * 1024L * 1024L; - else if (size1) - memsize = 4L * 1024L * 1024L; - else { - printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] "); - memsize = 16L * 1024L * 1024L; /* shouldn't happen - guess 16M */ - } - - if (dual) - memsize *= 2L; - - return (memsize); -#endif -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations after monitor - * has been relocated into ram - */ - -int misc_init_r (void) -{ - printf ("LCD: "); - lcd_init (); - -#if 0 - printf ("RTC: "); - rtc_init (); - - printf ("PAR: "); - par_init (); - - printf ("KBM: "); - kbm_init (); - - printf ("PCI: "); - pci_init (); -#endif - return (0); -} diff --git a/board/cogent/mb.h b/board/cogent/mb.h deleted file mode 100644 index f6eaf0a..0000000 --- a/board/cogent/mb.h +++ /dev/null @@ -1,529 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * defines for Cogent Motherboards - */ - -#ifndef _COGENT_MB_H -#define _COGENT_MB_H - -/* - * Cogent Motherboard Address Map - * - * The size of a Cogent motherboard address space is 256 Mbytes (i.e. 28 bits). - * - * The first 32 Mbyte (0x0000000-0x1FFFFFF) is usually RAM. The following - * 3 x 32 Mbyte areas (0x2000000-0x3FFFFFF, 0x4000000-0x5FFFFFF and - * 0x6000000-0x7FFFFFF) are general I/O "slots" (slots 1, 2 and 3). - * Most other motherboard devices have registers mapped into the area - * 0xE000000-0xFFFFFFF (Motherboard I/O slot?). The area 0x8000000-0xDFFFFFF - * is free for whatever. - * - * The location of the motherboard address space in the physical address space - * of the cpu is given by CMA_MB_BASE. This value is determined by the cpu - * module plugged into the motherboard and is configured above. - * - * Motherboard I/O devices mapped into the area (0xE000000-0xFFFFFFF) - * generally only use byte lane 0 (D0-7) for their transfers, i.e. only - * 8 bit, or 1 byte, transfers can take place, so all the registers are - * only 8 bits wide. The exceptions are the motherboard flash, which uses - * byte lanes 0 and 1 (i.e. 16 bits), and the mapped PCI address space. - * - * I/O registers within the mapped motherboard devices are 64 bit aligned - * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register - * will be at byte 7 (the address + 7). For little endian addressing, the - * register will be at byte 0 (the address + 0). To learn the endianess - * we must include - * - * Take the CMA102 and CMA111 motherboards as examples... - * - * The CMA102 has three CMABus I/O Expansion slots and no PCI bridge. The 3 - * CMABus slots are each mapped directly onto the three general I/O slots. - * - * The CMA111 has only one CMABus I/O Expansion slot, but has a V360EPC PCI - * bridge. The CMABus slot is mapped onto general I/O slot 1. The standard - * PCI Bus space is mapped onto general I/O slot 2, with a small area at the - * top reserved for access to the V360EPC registers (0x5FF0000-0x5FFFFFF). - * I/O slot 3 is unused. The extended PCI Bus space is mapped onto the area - * 0xA000000-0xDFFFFFF. - */ - -#define CMA_MB_RAM_BASE (CFG_CMA_MB_BASE+0x0000000) -#define CMA_MB_RAM_SIZE 0x2000000 /* dip sws set actual size */ - -#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1) -#define CMA_MB_SLOT1_BASE (CFG_CMA_MB_BASE+0x2000000) -#define CMA_MB_SLOT1_SIZE 0x2000000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2) -#define CMA_MB_SLOT2_BASE (CFG_CMA_MB_BASE+0x4000000) -#define CMA_MB_SLOT2_SIZE 0x2000000 -#endif -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) -#define CMA_MB_STDPCI_BASE (CFG_CMA_MB_BASE+0x4000000) -#define CMA_MB_STDPCI_SIZE 0x1ff0000 -#define CMA_MB_V360EPC_BASE (CFG_CMA_MB_BASE+0x5ff0000) -#define CMA_MB_V360EPC_SIZE 0x10000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3) -#define CMA_MB_SLOT3_BASE (CFG_CMA_MB_BASE+0x6000000) -#define CMA_MB_SLOT3_SIZE 0x2000000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) -#define CMA_MB_EXTPCI_BASE (CFG_CMA_MB_BASE+0xa000000) -#define CMA_MB_EXTPCI_SIZE 0x4000000 -#endif - -#define CMA_MB_ROMLOW_BASE (CFG_CMA_MB_BASE+0xe000000) -#define CMA_MB_ROMLOW_SIZE 0x800000 -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) -#define CMA_MB_FLLOW_EXEC_BASE (CFG_CMA_MB_BASE+0xe000000) -#define CMA_MB_FLLOW_EXEC_SIZE 0x100000 -#define CMA_MB_FLLOW_RDWR_BASE (CFG_CMA_MB_BASE+0xe400000) -#define CMA_MB_FLLOW_RDWR_SIZE 0x400000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_RTC) -#define CMA_MB_RTC_BASE (CFG_CMA_MB_BASE+0xe800000) -#define CMA_MB_RTC_SIZE 0x4000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) -#define CMA_MB_SERPAR_BASE (CFG_CMA_MB_BASE+0xe900000) -#define CMA_MB_SERIALB_BASE (CMA_MB_SERPAR_BASE+0x00) -#define CMA_MB_SERIALA_BASE (CMA_MB_SERPAR_BASE+0x40) -#define CMA_MB_PARALLEL_BASE (CMA_MB_SERPAR_BASE+0x80) -#define CMA_MB_SERPAR_SIZE 0xa0 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) -#define CMA_MB_PKBM_BASE (CFG_CMA_MB_BASE+0xe900100) -#define CMA_MB_PKBM_SIZE 0x10 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_LCD) -#define CMA_MB_LCD_BASE (CFG_CMA_MB_BASE+0xeb00000) -#define CMA_MB_LCD_SIZE 0x10 -#endif - -#define CMA_MB_DIPSW_BASE (CFG_CMA_MB_BASE+0xec00000) -#define CMA_MB_DIPSW_SIZE 0x10 - -#if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM)) -#define CMA_MB_SLOT1CFG_BASE (CFG_CMA_MB_BASE+0xf100000) -#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define CMA_MB_SER2_BASE (CMA_MB_SLOT1CFG_BASE+0x80) -#define CMA_MB_SER2B_BASE (CMA_MB_SER2_BASE+0x00) -#define CMA_MB_SER2A_BASE (CMA_MB_SER2_BASE+0x40) -#endif -#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT1) -#define CMA_MB_S1KBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200) -#endif -#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) && !defined(COGENT_CMA150) -#define CMA_MB_IREQ1STAT_BASE (CMA_MB_SLOT1CFG_BASE+0x100) -#define CMA_MB_AKBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200) -#define CMA_MB_IREQ1MASK_BASE (CMA_MB_SLOT1CFG_BASE+0x300) -#endif -#define CMA_MB_SLOT1CFG_SIZE 0x400 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2) -#define CMA_MB_SLOT2CFG_BASE (CFG_CMA_MB_BASE+0xf200000) -#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2) -#define CMA_MB_S2KBM_BASE (CMA_MB_SLOT2CFG_BASE+0x200) -#endif -#define CMA_MB_SLOT2CFG_SIZE 0x400 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) -#define CMA_MB_PCICTL_BASE (CFG_CMA_MB_BASE+0xf200000) -#define CMA_MB_PCI_V3CTL_BASE (CMA_MB_PCICTL_BASE+0x100) -#define CMA_MB_PCI_IDSEL_BASE (CMA_MB_PCICTL_BASE+0x200) -#define CMA_MB_PCI_IMASK_BASE (CMA_MB_PCICTL_BASE+0x300) -#define CMA_MB_PCI_ISTAT_BASE (CMA_MB_PCICTL_BASE+0x400) -#define CMA_MB_PCI_MBID_BASE (CMA_MB_PCICTL_BASE+0x500) -#define CMA_MB_PCI_MBREV_BASE (CMA_MB_PCICTL_BASE+0x600) -#define CMA_MB_PCICTL_SIZE 0x700 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3) -#define CMA_MB_SLOT3CFG_BASE (CFG_CMA_MB_BASE+0xf300000) -#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3) -#define CMA_MB_S3KBM_BASE (CMA_MB_SLOT3CFG_BASE+0x200) -#endif -#define CMA_MB_SLOT3CFG_SIZE 0x400 -#endif - -#define CMA_MB_ROMHIGH_BASE (CFG_CMA_MB_BASE+0xf800000) -#define CMA_MB_ROMHIGH_SIZE 0x800000 -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) -#define CMA_MB_FLHIGH_EXEC_BASE (CFG_CMA_MB_BASE+0xf800000) -#define CMA_MB_FLHIGH_EXEC_SIZE 0x100000 -#define CMA_MB_FLHIGH_RDWR_BASE (CFG_CMA_MB_BASE+0xfc00000) -#define CMA_MB_FLHIGH_RDWR_SIZE 0x400000 -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) - -/* PCI Control Register bits */ - -/* V360EPC Control register bits */ -#define CMA_MB_PCI_V3CTL_RESET 0x01 -#define CMA_MB_PCI_V3CTL_EXTADD 0x08 - -/* PCI ID Select register bits */ -#define CMA_MB_PCI_IDSEL_SLOTA 0x01 -#define CMA_MB_PCI_IDSEL_SLOTB 0x02 -#define CMA_MB_PCI_IDSEL_GD82559 0x04 -#define CMA_MB_PCI_IDSEL_B69000 0x08 -#define CMA_MB_PCI_IDSEL_PD6832 0x10 - -/* PCI Interrupt Mask/Status register bits */ -#define CMA_MB_PCI_IMS_INTA 0x01 -#define CMA_MB_PCI_IMS_INTB 0x02 -#define CMA_MB_PCI_IMS_INTC 0x04 -#define CMA_MB_PCI_IMS_INTD 0x08 -#define CMA_MB_PCI_IMS_CBINT 0x10 -#define CMA_MB_PCI_IMS_V3LINT 0x80 - -#endif - -#if (CMA_MB_CAPS & (CMA_MB_CAP_KBM|CMA_MB_CAP_SER2)) && !defined(COGENT_CMA150) - -/* - * IREQ1 Interrupt Mask/Status register bits - * (Note: not available on CMA150 - must poll HT6542B interrupt register) - */ - -#define IREQ1_MINT 0x01 -#define IREQ1_KINT 0x02 -#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define IREQ1_SINT2 0x04 -#define IREQ1_SINT3 0x08 -#endif - -#endif - -#ifndef __ASSEMBLY__ - -#ifdef USE_HOSTCC -#include /* avoid using private kernel header files */ -#else -#include /* use U-Boot provided headers */ -#endif - -/* a single CMA10x motherboard i/o register */ -typedef - struct { -#if __BYTE_ORDER == __LITTLE_ENDIAN - unsigned char value; -#endif - unsigned char filler[7]; -#if __BYTE_ORDER == __BIG_ENDIAN - unsigned char value; -#endif - } -cma_mb_reg; - -extern __inline__ unsigned char -cma_mb_reg_read(volatile cma_mb_reg *reg) -{ - unsigned char data = reg->value; - __asm__ __volatile__ ("eieio" : : : "memory"); - return data; -} - -extern __inline__ void -cma_mb_reg_write(volatile cma_mb_reg *reg, unsigned char data) -{ - reg->value = data; - __asm__ __volatile__ ("eieio" : : : "memory"); -} - -#if (CMA_MB_CAPS & CMA_MB_CAP_RTC) - -/* MK48T02 RTC registers */ -typedef - struct { - cma_mb_reg sram[2040];/* Battery-Backed SRAM */ - cma_mb_reg clk_ctl; /* Clock Control Register */ - cma_mb_reg clk_sec; /* Clock Seconds Register */ - cma_mb_reg clk_min; /* Clock Minutes Register */ - cma_mb_reg clk_hour; /* Clock Hour Register */ - cma_mb_reg clk_day; /* Clock Day Register */ - cma_mb_reg clk_date; /* Clock Date Register */ - cma_mb_reg clk_month; /* Clock Month Register */ - cma_mb_reg clk_year; /* Clock Year Register */ - } -cma_mb_rtc; - -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) - -/* ST16C522 Serial I/O */ -typedef - struct { - cma_mb_reg ser_rhr; /* Receive Holding Register (R, DLAB=0) */ - cma_mb_reg ser_ier; /* Interrupt Enable Register (R/W, DLAB=0) */ - cma_mb_reg ser_isr; /* Interrupt Status Register (R) */ - cma_mb_reg ser_lcr; /* Line Control Register (R/W) */ - cma_mb_reg ser_mcr; /* Modem Control Register (R/W) */ - cma_mb_reg ser_lsr; /* Line Status Register (R) */ - cma_mb_reg ser_msr; /* Modem Status Register (R/W) */ - cma_mb_reg ser_spr; /* Scratch Pad Register (R/W) */ - } -cma_mb_serial; - -#define ser_thr ser_rhr /* Transmit Holding Register (W, DLAB=0) */ -#define ser_brl ser_rhr /* Baud Rate Divisor Low Byte (R/W, DLAB=1) */ -#define ser_brh ser_ier /* Baud Rate Divisor High Byte (R/W, DLAB=1) */ -#define ser_fcr ser_isr /* FIFO Control Register (W) */ -#define ser_nop ser_lsr /* No Operation (W) */ - -/* ST16C522 Parallel I/O */ -typedef - struct { - cma_mb_reg par_rdr; /* Port Read Data Register (R) */ - cma_mb_reg par_sr; /* Status Register (R) */ - cma_mb_reg par_cmd; /* Command Register (R) */ - } -cma_mb_parallel; - -#define par_wdr par_rdr /* Port Write Data Register (W) */ -#define par_ios par_sr /* I/O Select Register (W) */ -#define par_ctl par_cmd /* Control Register (W) */ - -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302) - -/* HT6542B PS/2 Keyboard/Mouse Controller */ -typedef - struct { - cma_mb_reg kbm_rdr; /* Read Data Register (R) */ - cma_mb_reg kbm_sr; /* Status Register (R) */ - } -cma_mb_kbm; - -#define kbm_wdr kbm_rdr /* Write Data Register (W) */ -#define kbm_cmd kbm_sr /* Command Register (W) */ - -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_LCD) - -/* HD44780 LCD Display */ -typedef - struct { - cma_mb_reg lcd_ccr; /* Current Character Register (R/W) */ - cma_mb_reg lcd_bsr; /* Busy Status Register (R) */ - } -cma_mb_lcd; - -#define lcd_cmd lcd_bsr /* Command Register (W) */ - -#endif - -/* 8-Position Configuration Switch */ -typedef - struct { - cma_mb_reg dip_val; /* Dip Switch value (R) */ - } -cma_mb_dipsw; - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) - -/* V360EPC PCI Bridge */ -typedef - struct { -#if __BYTE_ORDER == __LITTLE_ENDIAN - unsigned short v3_pci_vendor; /* 0x00 */ - unsigned short v3_pci_device; - unsigned short v3_pci_cmd; /* 0x04 */ - unsigned short v3_pci_stat; - unsigned long v3_pci_cc_rev; /* 0x08 */ - unsigned long v3_pci_hdr_cfg; /* 0x0c */ - unsigned long v3_pci_io_base; /* 0x10 */ - unsigned long v3_pci_base0; /* 0x14 */ - unsigned long v3_pci_base1; /* 0x18 */ - unsigned long reserved1[4]; /* 0x1c */ - unsigned short v3_pci_sub_vendor; /* 0x2c */ - unsigned short v3_pci_sub_id; - unsigned long v3_pci_rom; /* 0x30 */ - unsigned long reserved2[2]; /* 0x34 */ - unsigned long v3_pci_bparam; /* 0x3c */ - unsigned long v3_pci_map0; /* 0x40 */ - unsigned long v3_pci_map1; /* 0x44 */ - unsigned long v3_pci_int_stat; /* 0x48 */ - unsigned long v3_pci_int_cfg; /* 0x4c */ - unsigned long reserved3[1]; /* 0x50 */ - unsigned long v3_lb_base0; /* 0x54 */ - unsigned long v3_lb_base1; /* 0x58 */ - unsigned short reserved4; /* 0x5c */ - unsigned short v3_lb_map0; - unsigned short reserved5; /* 0x60 */ - unsigned short v3_lb_map1; - unsigned short v3_lb_base2; /* 0x64 */ - unsigned short v3_lb_map2; - unsigned long v3_lb_size; /* 0x68 */ - unsigned short reserved6; /* 0x6c */ - unsigned short v3_lb_io_base; - unsigned short v3_fifo_cfg; /* 0x70 */ - unsigned short v3_fifo_priority; - unsigned short v3_fifo_stat; /* 0x74 */ - unsigned char v3_lb_istat; - unsigned char v3_lb_imask; - unsigned short v3_system; /* 0x78 */ - unsigned short v3_lb_cfg; - unsigned short v3_pci_cfg; /* 0x7c */ - unsigned short reserved7; - unsigned long v3_dma_pci_addr0; /* 0x80 */ - unsigned long v3_dma_local_addr0; /* 0x84 */ - unsigned long v3_dma_length0:24; /* 0x88 */ - unsigned long v3_dma_csr0:8; - unsigned long v3_dma_ctlb_adr0; /* 0x8c */ - unsigned long v3_dma_pci_addr1; /* 0x90 */ - unsigned long v3_dma_local_addr1; /* 0x94 */ - unsigned long v3_dma_length1:24; /* 0x98 */ - unsigned long v3_dma_csr1:8; - unsigned long v3_dma_ctlb_adr1; /* 0x9c */ - unsigned long v3_i20_mups[8]; /* 0xa0 */ - unsigned char v3_mail_data0; /* 0xc0 */ - unsigned char v3_mail_data1; - unsigned char v3_mail_data2; - unsigned char v3_mail_data3; - unsigned char v3_mail_data4; /* 0xc4 */ - unsigned char v3_mail_data5; - unsigned char v3_mail_data6; - unsigned char v3_mail_data7; - unsigned char v3_mail_data8; /* 0xc8 */ - unsigned char v3_mail_data9; - unsigned char v3_mail_data10; - unsigned char v3_mail_data11; - unsigned char v3_mail_data12; /* 0xcc */ - unsigned char v3_mail_data13; - unsigned char v3_mail_data14; - unsigned char v3_mail_data15; - unsigned short v3_pci_mail_iewr; /* 0xd0 */ - unsigned short v3_pci_mail_ierd; - unsigned short v3_lb_mail_iewr; /* 0xd4 */ - unsigned short v3_lb_mail_ierd; - unsigned short v3_mail_wr_stat; /* 0xd8 */ - unsigned short v3_mail_rd_stat; - unsigned long v3_qba_map; /* 0xdc */ - unsigned long v3_dma_delay:8; /* 0xe0 */ - unsigned long reserved8:24; - unsigned long reserved9[7]; /* 0xe4 */ -#endif -#if __BYTE_ORDER == __BIG_ENDIAN - unsigned short v3_pci_device; /* 0x00 */ - unsigned short v3_pci_vendor; - unsigned short v3_pci_stat; /* 0x04 */ - unsigned short v3_pci_cmd; - unsigned long v3_pci_cc_rev; /* 0x08 */ - unsigned long v3_pci_hdr_cfg; /* 0x0c */ - unsigned long v3_pci_io_base; /* 0x10 */ - unsigned long v3_pci_base0; /* 0x14 */ - unsigned long v3_pci_base1; /* 0x18 */ - unsigned long reserved1[4]; /* 0x1c */ - unsigned short v3_pci_sub_id; /* 0x2c */ - unsigned short v3_pci_sub_vendor; - unsigned long v3_pci_rom; /* 0x30 */ - unsigned long reserved2[2]; /* 0x34 */ - unsigned long v3_pci_bparam; /* 0x3c */ - unsigned long v3_pci_map0; /* 0x40 */ - unsigned long v3_pci_map1; /* 0x44 */ - unsigned long v3_pci_int_stat; /* 0x48 */ - unsigned long v3_pci_int_cfg; /* 0x4c */ - unsigned long reserved3; /* 0x50 */ - unsigned long v3_lb_base0; /* 0x54 */ - unsigned long v3_lb_base1; /* 0x58 */ - unsigned short v3_lb_map0; /* 0x5c */ - unsigned short reserved4; - unsigned short v3_lb_map1; /* 0x60 */ - unsigned short reserved5; - unsigned short v3_lb_map2; /* 0x64 */ - unsigned short v3_lb_base2; - unsigned long v3_lb_size; /* 0x68 */ - unsigned short v3_lb_io_base; /* 0x6c */ - unsigned short reserved6; - unsigned short v3_fifo_priority; /* 0x70 */ - unsigned short v3_fifo_cfg; - unsigned char v3_lb_imask; /* 0x74 */ - unsigned char v3_lb_istat; - unsigned short v3_fifo_stat; - unsigned short v3_lb_cfg; /* 0x78 */ - unsigned short v3_system; - unsigned short reserved7; /* 0x7c */ - unsigned short v3_pci_cfg; - unsigned long v3_dma_pci_addr0; /* 0x80 */ - unsigned long v3_dma_local_addr0; /* 0x84 */ - unsigned long v3_dma_csr0:8; /* 0x88 */ - unsigned long v3_dma_length0:24; - unsigned long v3_dma_ctlb_adr0; /* 0x8c */ - unsigned long v3_dma_pci_addr1; /* 0x90 */ - unsigned long v3_dma_local_addr1; /* 0x94 */ - unsigned long v3_dma_csr1:8; /* 0x98 */ - unsigned long v3_dma_length1:24; - unsigned long v3_dma_ctlb_adr1; /* 0x9c */ - unsigned long v3_i20_mups[8]; /* 0xa0 */ - unsigned char v3_mail_data3; /* 0xc0 */ - unsigned char v3_mail_data2; - unsigned char v3_mail_data1; - unsigned char v3_mail_data0; - unsigned char v3_mail_data7; /* 0xc4 */ - unsigned char v3_mail_data6; - unsigned char v3_mail_data5; - unsigned char v3_mail_data4; - unsigned char v3_mail_data11; /* 0xc8 */ - unsigned char v3_mail_data10; - unsigned char v3_mail_data9; - unsigned char v3_mail_data8; - unsigned char v3_mail_data15; /* 0xcc */ - unsigned char v3_mail_data14; - unsigned char v3_mail_data13; - unsigned char v3_mail_data12; - unsigned short v3_pci_mail_ierd; /* 0xd0 */ - unsigned short v3_pci_mail_iewr; - unsigned short v3_lb_mail_ierd; /* 0xd4 */ - unsigned short v3_lb_mail_iewr; - unsigned short v3_mail_rd_stat; /* 0xd8 */ - unsigned short v3_mail_wr_stat; - unsigned long v3_qba_map; /* 0xdc */ - unsigned long reserved8:24; /* 0xe0 */ - unsigned long v3_dma_delay:8; - unsigned long reserved9[7]; /* 0xe4 */ -#endif - } /* 0x100 */ -cma_mb_v360epc; - -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* _COGENT_MB_H */ diff --git a/board/cogent/par.c b/board/cogent/par.c deleted file mode 100644 index a03c0f1..0000000 --- a/board/cogent/par.c +++ /dev/null @@ -1,3 +0,0 @@ -/* parallel not implemented yet */ - -int cma_parallel_not_implemented = 1; diff --git a/board/cogent/par.h b/board/cogent/par.h deleted file mode 100644 index 664ae4a..0000000 --- a/board/cogent/par.h +++ /dev/null @@ -1,3 +0,0 @@ -/* parallel not implemented yet */ - -extern int cma_parallel_not_implemented; diff --git a/board/cogent/pci.c b/board/cogent/pci.c deleted file mode 100644 index 0a57c0c..0000000 --- a/board/cogent/pci.c +++ /dev/null @@ -1,3 +0,0 @@ -/* pci not implemented yet */ - -int cma_pci_not_implemented = 1; diff --git a/board/cogent/pci.h b/board/cogent/pci.h deleted file mode 100644 index 35aa354..0000000 --- a/board/cogent/pci.h +++ /dev/null @@ -1,3 +0,0 @@ -/* pci not implemented yet */ - -extern int cma_pci_not_implemented; diff --git a/board/cogent/rtc.c b/board/cogent/rtc.c deleted file mode 100644 index ace9193..0000000 --- a/board/cogent/rtc.c +++ /dev/null @@ -1,3 +0,0 @@ -/* rtc not implemented yet */ - -int cma_rtc_not_implemented = 1; diff --git a/board/cogent/rtc.h b/board/cogent/rtc.h deleted file mode 100644 index 4b55bd2..0000000 --- a/board/cogent/rtc.h +++ /dev/null @@ -1,3 +0,0 @@ -/* rtc not implemented yet */ - -extern int cma_rtc_not_implemented; diff --git a/board/cogent/serial.c b/board/cogent/serial.c deleted file mode 100644 index 4c20017..0000000 --- a/board/cogent/serial.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Simple serial driver for Cogent motherboard serial ports - * for use during boot - */ - -#include -#include - -#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) - -#if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \ - (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE)) - -#if CONFIG_CONS_INDEX == 1 -#define CMA_MB_SERIAL_BASE CMA_MB_SERIALA_BASE -#elif CONFIG_CONS_INDEX == 2 -#define CMA_MB_SERIAL_BASE CMA_MB_SERIALB_BASE -#elif CONFIG_CONS_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define CMA_MB_SERIAL_BASE CMA_MB_SER2A_BASE -#elif CONFIG_CONS_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define CMA_MB_SERIAL_BASE CMA_MB_SER2B_BASE -#else -#error CONFIG_CONS_INDEX must be configured for Cogent motherboard serial -#endif - -int serial_init (void) -{ -/* DECLARE_GLOBAL_DATA_PTR; */ - - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; - - cma_mb_reg_write(&mbsp->ser_ier, 0x00); /* turn off interrupts */ - serial_setbrg (); - cma_mb_reg_write(&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */ - cma_mb_reg_write(&mbsp->ser_mcr, 0x03); /* RTS/DTR */ - cma_mb_reg_write(&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */ - - return (0); -} - -void -serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; - unsigned int divisor; - unsigned char lcr; - - if ((divisor = br_to_div(gd->baudrate)) == 0) - divisor = DEFDIV; - - lcr = cma_mb_reg_read(&mbsp->ser_lcr); - cma_mb_reg_write(&mbsp->ser_lcr, lcr|0x80);/* Access baud rate(set DLAB)*/ - cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff); - cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff); - cma_mb_reg_write(&mbsp->ser_lcr, lcr); /* unset DLAB */ -} - -void -serial_putc(const char c) -{ - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; - - if (c == '\n') - serial_putc('\r'); - - while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0) - ; - - cma_mb_reg_write(&mbsp->ser_thr, c); -} - -void -serial_puts(const char *s) -{ - while (*s != '\0') - serial_putc(*s++); -} - -int -serial_getc(void) -{ - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; - - while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0) - ; - - return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f); -} - -int -serial_tstc(void) -{ - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE; - - return ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) != 0); -} - -#endif /* CONS_NONE */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && \ - defined(CONFIG_KGDB_NONE) - -#if CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX -#error Console and kgdb are on the same serial port - this is not supported -#endif - -#if CONFIG_KGDB_INDEX == 1 -#define CMA_MB_KGDB_SER_BASE CMA_MB_SERIALA_BASE -#elif CONFIG_KGDB_INDEX == 2 -#define CMA_MB_KGDB_SER_BASE CMA_MB_SERIALB_BASE -#elif CONFIG_KGDB_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define CMA_MB_KGDB_SER_BASE CMA_MB_SER2A_BASE -#elif CONFIG_KGDB_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2) -#define CMA_MB_KGDB_SER_BASE CMA_MB_SER2B_BASE -#else -#error CONFIG_KGDB_INDEX must be configured for Cogent motherboard serial -#endif - -void -kgdb_serial_init(void) -{ - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; - unsigned int divisor; - - if ((divisor = br_to_div(CONFIG_KGDB_BAUDRATE)) == 0) - divisor = DEFDIV; - - cma_mb_reg_write(&mbsp->ser_ier, 0x00); /* turn off interrupts */ - cma_mb_reg_write(&mbsp->ser_lcr, 0x80); /* Access baud rate(set DLAB)*/ - cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff); - cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff); - cma_mb_reg_write(&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */ - cma_mb_reg_write(&mbsp->ser_mcr, 0x03); /* RTS/DTR */ - cma_mb_reg_write(&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */ - - printf("[on cma10x serial port B] "); -} - -void -putDebugChar(int c) -{ - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; - - while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0) - ; - - cma_mb_reg_write(&mbsp->ser_thr, c & 0xff); -} - -void -putDebugStr(const char *str) -{ - while (*str != '\0') { - if (*str == '\n') - putDebugChar('\r'); - putDebugChar(*str++); - } -} - -int -getDebugChar(void) -{ - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; - - while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0) - ; - - return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f); -} - -void -kgdb_interruptible(int yes) -{ - cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE; - - if (yes == 1) { - printf("kgdb: turning serial ints on\n"); - cma_mb_reg_write(&mbsp->ser_ier, 0xf); - } - else { - printf("kgdb: turning serial ints off\n"); - cma_mb_reg_write(&mbsp->ser_ier, 0x0); - } -} - -#endif /* KGDB && KGDB_NONE */ - -#endif /* CAPS & SERPAR */ diff --git a/board/cogent/serial.h b/board/cogent/serial.h deleted file mode 100644 index 89962d8..0000000 --- a/board/cogent/serial.h +++ /dev/null @@ -1,15 +0,0 @@ -/* Line Status Register bits */ -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -#define CLKRATE 3686400 /* cogent motherboard serial clk = 3.6864MHz */ -#define DEFDIV 1 /* default to 230400 bps */ - -#define br_to_div(br) (CLKRATE / (16 * (br))) -#define div_to_br(div) (CLKRATE / (16 * (div))) diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds deleted file mode 100644 index 5ce2694..0000000 --- a/board/cogent/u-boot.lds +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - *(.text) - common/environment.o(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug deleted file mode 100644 index ddd4678..0000000 --- a/board/cogent/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile deleted file mode 100644 index ccb811b..0000000 --- a/board/cpc45/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o plx9030.o pd67290.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/cpc45/config.mk b/board/cpc45/config.mk deleted file mode 100644 index bf9d9de..0000000 --- a/board/cpc45/config.mk +++ /dev/null @@ -1,36 +0,0 @@ -# -# (C) Copyright 2001-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# CPC45 board -# - - -ifeq ($(CONFIG_BOOT_ROM),y) - TEXT_BASE := 0xFFF00000 - PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM -else - TEXT_BASE := 0xFFF00000 -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c deleted file mode 100644 index 51b0085..0000000 --- a/board/cpc45/cpc45.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -int sysControlDisplay(int digit, uchar ascii_code); -extern void Plx9030Init(void); -extern void SPD67290Init(void); - - /* We have to clear the initial data area here. Couldn't have done it - * earlier because DRAM had not been initialized. - */ -int board_early_init_f(void) -{ - - /* enable DUAL UART Mode on CPC45 */ - *(uchar*)DUART_DCR |= 0x1; /* set DCM bit */ - - return 0; -} - -int checkboard(void) -{ -/* - char revision = BOARD_REV; -*/ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - puts ("CPC45 "); -/* - printf("Revision %d ", revision); -*/ - printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); - - return 0; -} - -long int initdram (int board_type) -{ - int m, row, col, bank, i, ref; - unsigned long start, end; - uint32_t mccr1, mccr2; - uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; - uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; - uint8_t mber = 0; - unsigned int tmp; - - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); - - if (i2c_reg_read (0x50, 2) != 0x04) - return 0; /* Memory type */ - - m = i2c_reg_read (0x50, 5); /* # of physical banks */ - row = i2c_reg_read (0x50, 3); /* # of rows */ - col = i2c_reg_read (0x50, 4); /* # of columns */ - bank = i2c_reg_read (0x50, 17); /* # of logical banks */ - ref = i2c_reg_read (0x50, 12); /* refresh rate / type */ - - CONFIG_READ_WORD(MCCR1, mccr1); - mccr1 &= 0xffff0000; - - CONFIG_READ_WORD(MCCR2, mccr2); - mccr2 &= 0xffff0000; - - start = CFG_SDRAM_BASE; - end = start + (1 << (col + row + 3) ) * bank - 1; - - for (i = 0; i < m; i++) { - mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; - if (i < 4) { - msar1 |= ((start >> 20) & 0xff) << i * 8; - emsar1 |= ((start >> 28) & 0xff) << i * 8; - mear1 |= ((end >> 20) & 0xff) << i * 8; - emear1 |= ((end >> 28) & 0xff) << i * 8; - } else { - msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; - emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; - mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; - emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; - } - mber |= 1 << i; - start += (1 << (col + row + 3) ) * bank; - end += (1 << (col + row + 3) ) * bank; - } - for (; i < 8; i++) { - if (i < 4) { - msar1 |= 0xff << i * 8; - emsar1 |= 0x30 << i * 8; - mear1 |= 0xff << i * 8; - emear1 |= 0x30 << i * 8; - } else { - msar2 |= 0xff << (i-4) * 8; - emsar2 |= 0x30 << (i-4) * 8; - mear2 |= 0xff << (i-4) * 8; - emear2 |= 0x30 << (i-4) * 8; - } - } - - switch(ref) { - case 0x00: - case 0x80: - tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22; - break; - case 0x01: - case 0x81: - tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22; - break; - case 0x02: - case 0x82: - tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22; - break; - case 0x03: - case 0x83: - tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22; - break; - case 0x04: - case 0x84: - tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22; - break; - case 0x05: - case 0x85: - tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22; - break; - default: - tmp = 0x512; - break; - } - - CONFIG_WRITE_WORD(MCCR1, mccr1); - CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT); - CONFIG_WRITE_WORD(MSAR1, msar1); - CONFIG_WRITE_WORD(EMSAR1, emsar1); - CONFIG_WRITE_WORD(MEAR1, mear1); - CONFIG_WRITE_WORD(EMEAR1, emear1); - CONFIG_WRITE_WORD(MSAR2, msar2); - CONFIG_WRITE_WORD(EMSAR2, emsar2); - CONFIG_WRITE_WORD(MEAR2, mear2); - CONFIG_WRITE_WORD(EMEAR2, emear2); - CONFIG_WRITE_BYTE(MBER, mber); - - return (1 << (col + row + 3) ) * bank * m; -} - - -/* - * Initialize PCI Devices, report devices found. - */ - -static struct pci_config_table pci_cpc45_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR, - PCI_PLX9030_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCMCIA_IO_BASE, - PCMCIA_IO_BASE, - PCI_COMMAND_MEMORY | PCI_COMMAND_IO }}, -#endif /*CONFIG_PCI_PNP*/ - { } -}; - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_cpc45_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); - - /* init PCI_to_LOCAL Bus BRIDGE */ - Plx9030Init(); - - /* Clear Display */ - DISP_CWORD = 0x0; - - sysControlDisplay(0,' '); - sysControlDisplay(1,'C'); - sysControlDisplay(2,'P'); - sysControlDisplay(3,'C'); - sysControlDisplay(4,' '); - sysControlDisplay(5,'4'); - sysControlDisplay(6,'5'); - sysControlDisplay(7,' '); - -} - -/************************************************************************** -* -* sysControlDisplay - controls one of the Alphanum. Display digits. -* -* This routine will write an ASCII character to the display digit requested. -* -* SEE ALSO: -* -* RETURNS: NA -*/ - -int sysControlDisplay (int digit, /* number of digit 0..7 */ - uchar ascii_code /* ASCII code */ - ) -{ - if ((digit < 0) || (digit > 7)) - return (-1); - - *((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code; - - return (0); -} - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) - -#ifdef CFG_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR; -#endif - -int pcmcia_init(void) -{ - u_int rc; - - debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); - - rc = i82365_init(); - - return rc; -} - -#endif /* CFG_CMD_PCMCIA */ - -# ifdef CONFIG_IDE_LED -void ide_led (uchar led, uchar status) -{ - u_char val; - /* We have one PCMCIA slot and use LED H4 for the IDE Interface */ - val = readb(BCSR_BASE + 0x04); - if (status) { /* led on */ - val |= B_CTRL_LED0; - } else { - val &= ~B_CTRL_LED0; - } - writeb(val, BCSR_BASE + 0x04); -} -# endif diff --git a/board/cpc45/flash.c b/board/cpc45/flash.c deleted file mode 100644 index 37dd182..0000000 --- a/board/cpc45/flash.c +++ /dev/null @@ -1,522 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -#define FLASH_BANK_SIZE 0x800000 -#define MAIN_SECT_SIZE 0x40000 -#define PARAM_SECT_SIZE 0x8000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -static int write_data (flash_info_t * info, ulong dest, ulong * data); -static void write_via_fpu (vu_long * addr, ulong * data); -static __inline__ unsigned long get_msr (void); -static __inline__ void set_msr (unsigned long msr); - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -/*---------------------------------------------------------------------*/ -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - uchar tempChar; - vu_long *tmpaddr; - - /* Enable flash writes on CPC45 */ - - tempChar = BOARD_CTRL; - - tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1); - - tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0); - - BOARD_CTRL = tempChar; - - __asm__ volatile ("sync\n eieio"); - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE); - - addr[0] = 0x00900090; - - __asm__ volatile ("sync\n eieio"); - - udelay (100); - - DEBUGF ("Flash bank # %d:\n" - "\tManuf. ID @ 0x%08lX: 0x%08lX\n" - "\tDevice ID @ 0x%08lX: 0x%08lX\n", - i, - (ulong) (&addr[0]), addr[0], - (ulong) (&addr[2]), addr[2]); - - - if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) && - (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) { - - flash_info[i].flash_id = - (FLASH_MAN_INTEL & FLASH_VENDMASK) | - (INTEL_ID_28F160F3T & FLASH_TYPEMASK); - - } else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) - && (addr[2] == addr[3]) - && (addr[2] == INTEL_ID_28F160C3T)) { - - flash_info[i].flash_id = - (FLASH_MAN_INTEL & FLASH_VENDMASK) | - (INTEL_ID_28F160C3T & FLASH_TYPEMASK); - - } else { - flash_info[i].flash_id = FLASH_UNKNOWN; - addr[0] = 0xFFFFFFFF; - goto Done; - } - - DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); - - addr[0] = 0xFFFFFFFF; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j > 30) { - flash_info[i].start[j] = CFG_FLASH_BASE + - i * FLASH_BANK_SIZE + - (MAIN_SECT_SIZE * 31) + (j - - 31) * - PARAM_SECT_SIZE; - } else { - flash_info[i].start[j] = CFG_FLASH_BASE + - i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE; - } - } - - /* unlock sectors, if 160C3T */ - - for (j = 0; j < flash_info[i].sector_count; j++) { - tmpaddr = (vu_long *) flash_info[i].start[j]; - - if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) { - tmpaddr[0] = 0x00600060; - tmpaddr[0] = 0x00D000D0; - tmpaddr[1] = 0x00600060; - tmpaddr[1] = 0x00D000D0; - } - } - - size += flash_info[i].size; - - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - - /* Protect monitor and environment sectors - */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[1]); -#else - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); -#else - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif -#endif - -Done: - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch ((i = info->flash_id & FLASH_VENDMASK)) { - case (FLASH_MAN_INTEL & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor 0x%04x ", i); - break; - } - - switch ((i = info->flash_id & FLASH_TYPEMASK)) { - case (INTEL_ID_28F160F3T & FLASH_TYPEMASK): - printf ("28F160F3T (16Mbit)\n"); - break; - - case (INTEL_ID_28F160C3T & FLASH_TYPEMASK): - printf ("28F160C3T (16Mbit)\n"); - break; - - default: - printf ("Unknown Chip Type 0x%04x\n", i); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - DEBUGF ("Erase flash bank %d sect %d ... %d\n", - info - &flash_info[0], s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (FLASH_MAN_INTEL & FLASH_VENDMASK)) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - - DEBUGF ("Erase sect %d @ 0x%08lX\n", - sect, (ulong) addr); - - /* Disable interrupts which might cause a timeout - * here. - */ - flag = disable_interrupts (); - - addr[0] = 0x00500050; /* clear status register */ - addr[0] = 0x00200020; /* erase setup */ - addr[0] = 0x00D000D0; /* erase confirm */ - - addr[1] = 0x00500050; /* clear status register */ - addr[1] = 0x00200020; /* erase setup */ - addr[1] = 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080)) { - if ((now = get_timer (start)) > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - addr[0] = 0x00B000B0; /* suspend erase */ - addr[0] = 0x00FF00FF; /* to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - addr[0] = 0x00FF00FF; - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 8 /* flash bus width in bytes */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, cp, msr; - int l, rc, i; - ulong data[2]; - ulong *datah = &data[0]; - ulong *datal = &data[1]; - - DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", - addr, (ulong) src, cnt); - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - msr = get_msr (); - set_msr (msr | MSR_FP); - - wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - *datah = *datal = 0; - - for (i = 0, cp = wp; i < l; i++, cp++) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | (*(uchar *) cp); - } - for (; i < FLASH_WIDTH && cnt > 0; ++i) { - char tmp = *src++; - - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | tmp; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datah << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - set_msr (msr); - return (rc); - } - - wp += FLASH_WIDTH; - } - - /* - * handle FLASH_WIDTH aligned part - */ - while (cnt >= FLASH_WIDTH) { - *datah = *(ulong *) src; - *datal = *(ulong *) (src + 4); - if ((rc = write_data (info, wp, data)) != 0) { - set_msr (msr); - return (rc); - } - wp += FLASH_WIDTH; - cnt -= FLASH_WIDTH; - src += FLASH_WIDTH; - } - - if (cnt == 0) { - set_msr (msr); - return (0); - } - - /* - * handle unaligned tail bytes - */ - *datah = *datal = 0; - for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { - char tmp = *src++; - - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> - 24); - } - - *datal = (*datal << 8) | tmp; - --cnt; - } - - for (; i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> - 24); - } - - *datal = (*datal << 8) | (*(uchar *) cp); - } - - rc = write_data (info, wp, data); - set_msr (msr); - - return (rc); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, ulong * data) -{ - vu_long *addr = (vu_long *) dest; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if (((addr[0] & data[0]) != data[0]) || - ((addr[1] & data[1]) != data[1])) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[0] = 0x00400040; /* write setup */ - write_via_fpu (addr, data); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - addr[0] = 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - addr[0] = 0x00FF00FF; /* restore read mode */ - - return (0); -} - -/*----------------------------------------------------------------------- - */ -static void write_via_fpu (vu_long * addr, ulong * data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); -} - -/*----------------------------------------------------------------------- - */ -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - return msr; -} - -static __inline__ void set_msr (unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); -} diff --git a/board/cpc45/pd67290.c b/board/cpc45/pd67290.c deleted file mode 100644 index c84fbae..0000000 --- a/board/cpc45/pd67290.c +++ /dev/null @@ -1,68 +0,0 @@ -/* pd67290.c - system configuration module for SPD67290 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * (C) 2004 DENX Software Engineering, Heiko Schocher - */ - -#include -#include -#include -#include -#include - -/* imports */ -#include - -static struct pci_device_id supported[] = { - {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729}, - {} -}; - -/*************************************************************************** -* -* SPD67290Init - -* -* RETURNS: -1 on error, 0 if OK -*/ - -int SPD67290Init (void) -{ - pci_dev_t devno; - int idx = 0; /* general index */ - ulong membaseCsr; /* base address of device memory space */ - - /* find PD67290 device */ - if ((devno = pci_find_devices (supported, idx++)) < 0) { - printf ("No PD67290 device found !!\n"); - return -1; - } - /* - 0xfe000000 see MPC 8245 Users Manual Adress Map B */ - membaseCsr = PCMCIA_IO_BASE - 0xfe000000; - - /* set base address */ - pci_write_config_dword (devno, PCI_BASE_ADDRESS_0, membaseCsr); - - /* enable mapped memory and IO addresses */ - pci_write_config_dword (devno, - PCI_COMMAND, - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO | PCI_COMMAND_WAIT); - return 0; -} diff --git a/board/cpc45/plx9030.c b/board/cpc45/plx9030.c deleted file mode 100644 index 99ec39a..0000000 --- a/board/cpc45/plx9030.c +++ /dev/null @@ -1,173 +0,0 @@ -/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */ -/* - * (C) Copyright 2002-2003 - * Josef Wagner, MicroSys GmbH, wagner@microsys.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Date Modification by - * ------- ---------------------------------------------- --- - * 30sep02 converted from VxWorks to LINUX wa -*/ - - -/* -DESCRIPTION - -This is the configuration module for the PLX9030 PCI to Local Bus Bridge. -It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local -registers (CS3) on CPC45. -*/ - -/* includes */ - -#include -#include -#include -#include -#include - -/* imports */ - - -/* defines */ -#define PLX9030_VENDOR_ID 0x10B5 -#define PLX9030_DEVICE_ID 0x9030 - -#undef PLX_DEBUG - -/* PLX9030 register offsets */ -#define P9030_LAS0RR 0x00 -#define P9030_LAS1RR 0x04 -#define P9030_LAS2RR 0x08 -#define P9030_LAS3RR 0x0c -#define P9030_EROMRR 0x10 -#define P9030_LAS0BA 0x14 -#define P9030_LAS1BA 0x18 -#define P9030_LAS2BA 0x1c -#define P9030_LAS3BA 0x20 -#define P9030_EROMBA 0x24 -#define P9030_LAS0BRD 0x28 -#define P9030_LAS1BRD 0x2c -#define P9030_LAS2BRD 0x30 -#define P9030_LAS3BRD 0x34 -#define P9030_EROMBRD 0x38 -#define P9030_CS0BASE 0x3C -#define P9030_CS1BASE 0x40 -#define P9030_CS2BASE 0x44 -#define P9030_CS3BASE 0x48 -#define P9030_INTCSR 0x4c -#define P9030_CNTRL 0x50 -#define P9030_GPIOC 0x54 - -/* typedefs */ - - -/* locals */ - -static struct pci_device_id supported[] = { - { PLX9030_VENDOR_ID, PLX9030_DEVICE_ID }, - { } -}; - -/* forward declarations */ -void sysOutLong(ulong address, ulong value); - - -/*************************************************************************** -* -* Plx9030Init - init CS0..CS3 for CPC45 -* -* -* RETURNS: N/A -*/ - -void Plx9030Init (void) -{ - pci_dev_t devno; - ulong membaseCsr; /* base address of device memory space */ - int idx = 0; /* general index */ - - - /* find plx9030 device */ - - if ((devno = pci_find_devices(supported, idx++)) < 0) - { - printf("No PLX9030 device found !!\n"); - return; - } - - -#ifdef PLX_DEBUG - printf("PLX 9030 device found ! devno = 0x%x\n",devno); -#endif - - membaseCsr = PCI_PLX9030_MEMADDR; - - /* set base address */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr); - - /* enable mapped memory and IO addresses */ - pci_write_config_dword(devno, - PCI_COMMAND, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); - - - /* configure GBIOC */ - sysOutLong((membaseCsr + P9030_GPIOC), 0x00000FC0); /* CS2/CS3 enable */ - - /* configure CS0 (SRAM) */ - sysOutLong((membaseCsr + P9030_LAS0BA), 0x00000001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS0RR), 0x0FE00000); /* 2 MByte */ - sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900); /* 4 wait states */ - sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001); /* enable 2 MByte */ - /* remap CS0 (SRAM) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE); - - /* configure CS1 (ST16552 / CHAN A) */ - sysOutLong((membaseCsr + P9030_LAS1BA), 0x00400001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS1RR), 0x0FFFFF00); /* 256 byte */ - sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900); /* 4 wait states */ - sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081); /* enable 256 Byte */ - /* remap CS1 (ST16552 / CHAN A) */ - /* remap CS1 (ST16552 / CHAN A) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE); - - /* configure CS2 (ST16552 / CHAN B) */ - sysOutLong((membaseCsr + P9030_LAS2BA), 0x00800001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS2RR), 0x0FFFFF00); /* 256 byte */ - sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900); /* 4 wait states */ - sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081); /* enable 256 Byte */ - /* remap CS2 (ST16552 / CHAN B) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE); - - /* configure CS3 (BCSR) */ - sysOutLong((membaseCsr + P9030_LAS3BA), 0x00C00001); /* enable space base */ - sysOutLong((membaseCsr + P9030_LAS3RR), 0x0FFFFF00); /* 256 byte */ - sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80); /* 9 wait states */ - sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081); /* enable 256 Byte */ - /* remap CS3 (DISPLAY and BCSR) */ - pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE); -} - -void sysOutLong(ulong address, ulong value) -{ - *(ulong*)address = cpu_to_le32(value); -} diff --git a/board/cpc45/u-boot.lds b/board/cpc45/u-boot.lds deleted file mode 100644 index 9ea26aa..0000000 --- a/board/cpc45/u-boot.lds +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cpu86/Makefile b/board/cpu86/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/cpu86/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/cpu86/config.mk b/board/cpu86/config.mk deleted file mode 100644 index 00354c4..0000000 --- a/board/cpu86/config.mk +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# CPU86 boards -# - -# This should be equal to the CFG_FLASH_BASE define in config_CPU86.h -# for the "final" configuration, with U-Boot in flash, or the address -# in RAM where U-Boot is loaded at for debugging. -# - -ifeq ($(CONFIG_BOOT_ROM),y) - TEXT_BASE := 0xFF800000 - PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM -else - TEXT_BASE := 0xFF000000 -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c deleted file mode 100644 index 3eb5b35..0000000 --- a/board/cpu86/cpu86.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "cpu86.h" - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ - /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ - /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ - /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ - /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ - /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ - /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ - /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SOFT_I2C) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CFG_RAMBOOT - ulong size8, size9; -#endif - long psize; - - psize = 32 * 1024 * 1024; - - memctl->memc_mptpr = CFG_MPTPR; - memctl->memc_psrt = CFG_PSRT; - -#ifndef CFG_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, - (uchar *) CFG_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - printf ("(60x:8COL) "); - } - -#endif /* CFG_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -extern void doc_probe (ulong physadr); -void doc_init (void) -{ - doc_probe (CFG_DOC_BASE); -} -#endif diff --git a/board/cpu86/cpu86.h b/board/cpu86/cpu86.h deleted file mode 100644 index cf7852c..0000000 --- a/board/cpu86/cpu86.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __BOARD_CPU86__ -#define __BOARD_CPU86__ - -#include - -#define REG8(x) (*(volatile unsigned char *)(x)) - -/* CPU86 register definitions */ -#define CPU86_VME_EAC REG8(CFG_BCRS_BASE + 0x00) -#define CPU86_VME_SAC REG8(CFG_BCRS_BASE + 0x01) -#define CPU86_VME_MAC REG8(CFG_BCRS_BASE + 0x02) -#define CPU86_BCR REG8(CFG_BCRS_BASE + 0x03) -#define CPU86_BSR REG8(CFG_BCRS_BASE + 0x04) -#define CPU86_WDOG_RPORT REG8(CFG_BCRS_BASE + 0x05) -#define CPU86_MBOX_IRQ REG8(CFG_BCRS_BASE + 0x04) -#define CPU86_REV REG8(CFG_BCRS_BASE + 0x07) -#define CPU86_VME_IRQMASK REG8(CFG_BCRS_BASE + 0x80) -#define CPU86_VME_IRQSTATUS REG8(CFG_BCRS_BASE + 0x81) -#define CPU86_LOCAL_IRQMASK REG8(CFG_BCRS_BASE + 0x82) -#define CPU86_LOCAL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x83) -#define CPU86_PMCL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x84) - -/* Board Control Register bits */ -#define CPU86_BCR_FWPT 0x01 -#define CPU86_BCR_FWRE 0x02 - -#endif /* __BOARD_CPU86__ */ diff --git a/board/cpu86/flash.c b/board/cpu86/flash.c deleted file mode 100644 index 1535a6b..0000000 --- a/board/cpu86/flash.c +++ /dev/null @@ -1,615 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for Intel devices - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "cpu86.h" - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -ulong flash_int_get_size (volatile unsigned long *baseaddr, - flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - info->sector_count = info->size = 0; - info->flash_id = FLASH_UNKNOWN; - - /* Write identify command sequence and test FLASH answer - */ - baseaddr[0] = 0x00900090; - baseaddr[1] = 0x00900090; - - flashtest_h = baseaddr[0]; /* manufacturer ID */ - flashtest_l = baseaddr[1]; - - if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) - return (0); /* no or unknown flash */ - - flashtest_h = baseaddr[2]; /* device ID */ - flashtest_l = baseaddr[3]; - - if (flashtest_h != flashtest_l) - return (0); - - switch (flashtest_h) { - case INTEL_ID_28F160C3B: - info->flash_id = FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F160F3B: - info->flash_id = FLASH_28F160F3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - default: - return (0); /* no or unknown flash */ - } - - info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ - - if (info->flash_id & FLASH_BTYPE) { - volatile unsigned long *tmp = baseaddr; - - /* set up sector start adress table (bottom sector type) - * AND unlock the sectors (if our chip is 160C3) - */ - for (i = 0; i < info->sector_count; i++) { - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) { - tmp[0] = 0x00600060; - tmp[1] = 0x00600060; - tmp[0] = 0x00D000D0; - tmp[1] = 0x00D000D0; - } - info->start[i] = (uint) tmp; - tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ - } - } - - memset (info->protect, 0, info->sector_count); - - baseaddr[0] = 0x00FF00FF; - baseaddr[1] = 0x00FF00FF; - - return (info->size); -} - -static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info) -{ - short i; - uchar vendor, devid; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x90; - - udelay(1000); - - vendor = addr[0]; - devid = addr[1] & 0xff; - - /* only support AMD */ - if (vendor != 0x01) { - return 0; - } - - vendor &= 0xf; - devid &= 0xff; - - if (devid == AMD_ID_F040B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 8; - info->size = info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F080B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 16; - info->size = 4 * info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F016D) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 32; - info->size = 4 * info->sector_count * 0x10000; - } - else { - printf ("## Unknown Flash Type: %02x\n", devid); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - unsigned long size_b1 = 0; - int i; - - /* Init: no FLASHes known - */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Disable flash protection */ - CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE); - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]); - size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]); - - if (size_b0 > 0 || size_b1 > 0) { - - printf("("); - - if (size_b0 > 0) { - puts ("Bank#1 - "); - print_size (size_b0, (size_b1 > 0) ? ", " : ") "); - } - - if (size_b1 > 0) { - puts ("Bank#2 - "); - print_size (size_b1, ") "); - } - } - else { - printf ("## No FLASH found.\n"); - return 0; - } - /* protect monitor and environment sectors - */ - -#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE - if (size_b1) { - /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE - * but we shouldn't protect it. - */ - - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1] - ); - } -#else -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] - ); -#endif -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# if CFG_ENV_ADDR >= CFG_BOOTROM_BASE - if (size_b1) { - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); - } -# else - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -# endif -#endif - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x89: - printf ("INTEL "); - break; - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf ("28F160C3B (16 Mbit, bottom sector)\n"); - break; - case FLASH_28F160F3B: - printf ("28F160F3B (16 Mbit, bottom sector)\n"); - break; - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size < 0x100000) - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - else - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Check the type of erased flash - */ - if (info->flash_id >> 16 == 0x1) { - /* Erase AMD flash - */ - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto AMD_DONE; - - start = get_timer (0); - last = start; - addr = (vu_char *)(info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -AMD_DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - } else { - /* Erase Intel flash - */ - - /* Start erase on unprotected sectors - */ - for (sect = s_first; sect <= s_last; sect++) { - volatile ulong *addr = - (volatile unsigned long *) info->start[sect]; - - start = get_timer (0); - last = start; - if (info->protect[sect] == 0) { - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - /* Erase the block - */ - addr[0] = 0x00200020; - addr[1] = 0x00200020; - addr[0] = 0x00D000D0; - addr[1] = 0x00D000D0; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - last = start; - while ((addr[0] & 0x00800080) != 0x00800080 || - (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout (erase suspended!)\n"); - /* Suspend erase - */ - addr[0] = 0x00B000B0; - addr[1] = 0x00B000B0; - goto DONE; - } - /* show that we're waiting - */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { - printf ("*** ERROR: erase failed!\n"); - goto DONE; - } - } - /* Clear status register and reset to read mode - */ - addr[0] = 0x00500050; - addr[1] = 0x00500050; - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - } - - printf (" done\n"); - -DONE: - return 0; -} - -static int write_word (flash_info_t *, volatile unsigned long *, ulong); -static int write_byte (flash_info_t *info, ulong dest, uchar data); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong v; - int i, l, rc, cc = cnt, res = 0; - - if (info->flash_id >> 16 == 0x1) { - - /* Write to AMD 8-bit flash - */ - while (cnt > 0) { - if ((rc = write_byte(info, addr, *src)) != 0) { - return (rc); - } - addr++; - src++; - cnt--; - } - - return (0); - } else { - - /* Write to Intel 64-bit flash - */ - for (v=0; cc > 0; addr += 4, cc -= 4 - l) { - l = (addr & 3); - addr &= ~3; - - for (i = 0; i < 4; i++) { - v = (v << 8) + (i < l || i - l >= cc ? - *((unsigned char *) addr + i) : *src++); - } - - if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, volatile unsigned long *addr, - ulong data) -{ - int flag, res = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - *addr = 0x00400040; - *addr = data; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - /* Suspend program - */ - *addr = 0x00B000B0; - res = 1; - goto OUT; - } - } - - if (*addr & 0x00220022) { - printf ("*** ERROR: program failed!\n"); - res = 1; - } - -OUT: - /* Clear status register and reset to read mode - */ - *addr = 0x00500050; - *addr = 0x00FF00FF; - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cpu86/u-boot.lds b/board/cpu86/u-boot.lds deleted file mode 100644 index 05f29c6..0000000 --- a/board/cpu86/u-boot.lds +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - common/environment.o(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cpu87/Makefile b/board/cpu87/Makefile deleted file mode 100644 index 26f53ed..0000000 --- a/board/cpu87/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/cpu87/config.mk b/board/cpu87/config.mk deleted file mode 100644 index 6384c78..0000000 --- a/board/cpu87/config.mk +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# CPU87 board -# - -# This should be equal to the CFG_FLASH_BASE define in configs/cpu87.h -# for the "final" configuration, with U-Boot in flash, or the address -# in RAM where U-Boot is loaded at for debugging. -# - -ifeq ($(CONFIG_BOOT_ROM),y) - TEXT_BASE := 0xFF800000 - PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM -else - TEXT_BASE := 0xFF000000 -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c deleted file mode 100644 index 8363d86..0000000 --- a/board/cpu87/cpu87.c +++ /dev/null @@ -1,333 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "cpu87.h" -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ - /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ - /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ - /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ - /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ - /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ - /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ - /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SOFT_I2C) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CFG_RAMBOOT - ulong size8, size9; -#endif - long psize; - - psize = 32 * 1024 * 1024; - - memctl->memc_mptpr = CFG_MPTPR; - memctl->memc_psrt = CFG_PSRT; - -#ifndef CFG_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, - (uchar *) CFG_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - printf ("(60x:8COL) "); - } - -#endif /* CFG_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -extern void doc_probe (ulong physadr); -void doc_init (void) -{ - doc_probe (CFG_DOC_BASE); -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif diff --git a/board/cpu87/cpu87.h b/board/cpu87/cpu87.h deleted file mode 100644 index 5dbd4ae..0000000 --- a/board/cpu87/cpu87.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __BOARD_CPU87__ -#define __BOARD_CPU87__ - -#include - -#define REG8(x) (*(volatile unsigned char *)(x)) - -/* CPU86 register definitions */ -#define CPU86_VME_EAC REG8(CFG_BCRS_BASE + 0x00) -#define CPU86_VME_SAC REG8(CFG_BCRS_BASE + 0x01) -#define CPU86_VME_MAC REG8(CFG_BCRS_BASE + 0x02) -#define CPU86_BCR REG8(CFG_BCRS_BASE + 0x03) -#define CPU86_BSR REG8(CFG_BCRS_BASE + 0x04) -#define CPU86_WDOG_RPORT REG8(CFG_BCRS_BASE + 0x05) -#define CPU86_MBOX_IRQ REG8(CFG_BCRS_BASE + 0x04) -#define CPU86_REV REG8(CFG_BCRS_BASE + 0x07) -#define CPU86_VME_IRQMASK REG8(CFG_BCRS_BASE + 0x80) -#define CPU86_VME_IRQSTATUS REG8(CFG_BCRS_BASE + 0x81) -#define CPU86_LOCAL_IRQMASK REG8(CFG_BCRS_BASE + 0x82) -#define CPU86_LOCAL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x83) -#define CPU86_PMCL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x84) - -/* Board Control Register bits */ -#define CPU86_BCR_FWPT 0x01 -#define CPU86_BCR_FWRE 0x02 - -#endif /* __BOARD_CPU87__ */ diff --git a/board/cpu87/flash.c b/board/cpu87/flash.c deleted file mode 100644 index 076c2f9..0000000 --- a/board/cpu87/flash.c +++ /dev/null @@ -1,624 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for Intel devices - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "cpu87.h" - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -ulong flash_int_get_size (volatile unsigned long *baseaddr, - flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - info->sector_count = info->size = 0; - info->flash_id = FLASH_UNKNOWN; - - /* Write identify command sequence and test FLASH answer - */ - baseaddr[0] = 0x00900090; - baseaddr[1] = 0x00900090; - - flashtest_h = baseaddr[0]; /* manufacturer ID */ - flashtest_l = baseaddr[1]; - - if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) - return (0); /* no or unknown flash */ - - flashtest_h = baseaddr[2]; /* device ID */ - flashtest_l = baseaddr[3]; - - if (flashtest_h != flashtest_l) - return (0); - - switch (flashtest_h) { - case INTEL_ID_28F160C3B: - info->flash_id = FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F160F3B: - info->flash_id = FLASH_28F160F3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F640C3B: - info->flash_id = FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ - break; - default: - return (0); /* no or unknown flash */ - } - - info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ - - if (info->flash_id & FLASH_BTYPE) { - volatile unsigned long *tmp = baseaddr; - - /* set up sector start adress table (bottom sector type) - * AND unlock the sectors (if our chip is 160C3) - */ - for (i = 0; i < info->sector_count; i++) { - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { - tmp[0] = 0x00600060; - tmp[1] = 0x00600060; - tmp[0] = 0x00D000D0; - tmp[1] = 0x00D000D0; - } - info->start[i] = (uint) tmp; - tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ - } - } - - memset (info->protect, 0, info->sector_count); - - baseaddr[0] = 0x00FF00FF; - baseaddr[1] = 0x00FF00FF; - - return (info->size); -} - -static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info) -{ - short i; - uchar vendor, devid; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x90; - - udelay(1000); - - vendor = addr[0]; - devid = addr[1] & 0xff; - - /* only support AMD */ - if (vendor != 0x01) { - return 0; - } - - vendor &= 0xf; - devid &= 0xff; - - if (devid == AMD_ID_F040B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 8; - info->size = info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F080B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 16; - info->size = 4 * info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F016D) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 32; - info->size = 4 * info->sector_count * 0x10000; - } - else { - printf ("## Unknown Flash Type: %02x\n", devid); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - unsigned long size_b1 = 0; - int i; - - /* Init: no FLASHes known - */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Disable flash protection */ - CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE); - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]); - size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]); - - if (size_b0 > 0 || size_b1 > 0) { - - printf("("); - - if (size_b0 > 0) { - puts ("Bank#1 - "); - print_size (size_b0, (size_b1 > 0) ? ", " : ") "); - } - - if (size_b1 > 0) { - puts ("Bank#2 - "); - print_size (size_b1, ") "); - } - } - else { - printf ("## No FLASH found.\n"); - return 0; - } - /* protect monitor and environment sectors - */ - -#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE - if (size_b1) { - /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE - * but we shouldn't protect it. - */ - - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1] - ); - } -#else -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] - ); -#endif -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# if CFG_ENV_ADDR >= CFG_BOOTROM_BASE - if (size_b1) { - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); - } -# else - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -# endif -#endif - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x89: - printf ("INTEL "); - break; - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf ("28F160C3B (16 Mbit, bottom sector)\n"); - break; - case FLASH_28F160F3B: - printf ("28F160F3B (16 Mbit, bottom sector)\n"); - break; - case FLASH_28F640C3B: - printf ("28F640C3B (64 M, bottom sector)\n"); - break; - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size < 0x100000) - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - else - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Check the type of erased flash - */ - if (info->flash_id >> 16 == 0x1) { - /* Erase AMD flash - */ - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto AMD_DONE; - - start = get_timer (0); - last = start; - addr = (vu_char *)(info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -AMD_DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - } else { - /* Erase Intel flash - */ - - /* Start erase on unprotected sectors - */ - for (sect = s_first; sect <= s_last; sect++) { - volatile ulong *addr = - (volatile unsigned long *) info->start[sect]; - - start = get_timer (0); - last = start; - if (info->protect[sect] == 0) { - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - /* Erase the block - */ - addr[0] = 0x00200020; - addr[1] = 0x00200020; - addr[0] = 0x00D000D0; - addr[1] = 0x00D000D0; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - last = start; - while ((addr[0] & 0x00800080) != 0x00800080 || - (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout (erase suspended!)\n"); - /* Suspend erase - */ - addr[0] = 0x00B000B0; - addr[1] = 0x00B000B0; - goto DONE; - } - /* show that we're waiting - */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { - printf ("*** ERROR: erase failed!\n"); - goto DONE; - } - } - /* Clear status register and reset to read mode - */ - addr[0] = 0x00500050; - addr[1] = 0x00500050; - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - } - - printf (" done\n"); - -DONE: - return 0; -} - -static int write_word (flash_info_t *, volatile unsigned long *, ulong); -static int write_byte (flash_info_t *info, ulong dest, uchar data); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong v; - int i, l, rc, cc = cnt, res = 0; - - if (info->flash_id >> 16 == 0x1) { - - /* Write to AMD 8-bit flash - */ - while (cnt > 0) { - if ((rc = write_byte(info, addr, *src)) != 0) { - return (rc); - } - addr++; - src++; - cnt--; - } - - return (0); - } else { - - /* Write to Intel 64-bit flash - */ - for (v=0; cc > 0; addr += 4, cc -= 4 - l) { - l = (addr & 3); - addr &= ~3; - - for (i = 0; i < 4; i++) { - v = (v << 8) + (i < l || i - l >= cc ? - *((unsigned char *) addr + i) : *src++); - } - - if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, volatile unsigned long *addr, - ulong data) -{ - int flag, res = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - *addr = 0x00400040; - *addr = data; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - /* Suspend program - */ - *addr = 0x00B000B0; - res = 1; - goto OUT; - } - } - - if (*addr & 0x00220022) { - printf ("*** ERROR: program failed!\n"); - res = 1; - } - -OUT: - /* Clear status register and reset to read mode - */ - *addr = 0x00500050; - *addr = 0x00FF00FF; - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cpu87/u-boot.lds b/board/cpu87/u-boot.lds deleted file mode 100644 index fb7e665..0000000 --- a/board/cpu87/u-boot.lds +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - common/environment.o(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cradle/Makefile b/board/cradle/Makefile deleted file mode 100644 index 265d500..0000000 --- a/board/cradle/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := cradle.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/cradle/config.mk b/board/cradle/config.mk deleted file mode 100644 index aa40388..0000000 --- a/board/cradle/config.mk +++ /dev/null @@ -1,2 +0,0 @@ -TEXT_BASE = 0xa0f80000 -#TEXT_BASE = 0 diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c deleted file mode 100644 index 6f65f32..0000000 --- a/board/cradle/cradle.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - - -/* local prototypes */ -void set_led (int led, int color); -void error_code_halt (int code); -int init_sio (int led, unsigned long base); -inline void cradle_outb (unsigned short val, unsigned long base, - unsigned long reg); -inline unsigned char cradle_inb (unsigned long base, unsigned long reg); -inline void sleep (int i); - -inline void -/**********************************************************/ -sleep (int i) -/**********************************************************/ -{ - while (i--) { - udelay (1000000); - } -} - -void -/**********************************************************/ -error_code_halt (int code) -/**********************************************************/ -{ - while (1) { - led_code (code, RED); - sleep (1); - led_code (0, OFF); - sleep (1); - } -} - -void -/**********************************************************/ -led_code (int code, int color) -/**********************************************************/ -{ - int i; - - code &= 0xf; /* only 4 leds */ - - for (i = 0; i < 4; i++) { - if (code & (1 << i)) { - set_led (i, color); - } else { - set_led (i, OFF); - } - } -} - -void -/**********************************************************/ -set_led (int led, int color) -/**********************************************************/ -{ - int shift = led * 2; - unsigned long mask = 0x3 << shift; - - CRADLE_LED_CLR_REG = mask; /* clear bits */ - CRADLE_LED_SET_REG = (color << shift); /* set bits */ - udelay (5000); -} - -inline void -/**********************************************************/ -cradle_outb (unsigned short val, unsigned long base, unsigned long reg) -/**********************************************************/ -{ - *(volatile unsigned short *) (base + (reg * 2)) = val; -} - -inline unsigned char -/**********************************************************/ -cradle_inb (unsigned long base, unsigned long reg) -/**********************************************************/ -{ - unsigned short val; - - val = *(volatile unsigned short *) (base + (reg * 2)); - return (val & 0xff); -} - -int -/**********************************************************/ -init_sio (int led, unsigned long base) -/**********************************************************/ -{ - unsigned char val; - - set_led (led, YELLOW); - val = cradle_inb (base, CRADLE_SIO_INDEX); - val = cradle_inb (base, CRADLE_SIO_INDEX); - if (val != 0) { - set_led (led, RED); - return -1; - } - - /* map SCC2 to COM1 */ - cradle_outb (0x01, base, CRADLE_SIO_INDEX); - cradle_outb (0x00, base, CRADLE_SIO_DATA); - - /* enable SCC2 extended regs */ - cradle_outb (0x40, base, CRADLE_SIO_INDEX); - cradle_outb (0xa0, base, CRADLE_SIO_DATA); - - /* enable SCC2 clock multiplier */ - cradle_outb (0x51, base, CRADLE_SIO_INDEX); - cradle_outb (0x04, base, CRADLE_SIO_DATA); - - /* enable SCC2 */ - cradle_outb (0x00, base, CRADLE_SIO_INDEX); - cradle_outb (0x04, base, CRADLE_SIO_DATA); - - /* map SCC2 DMA to channel 0 */ - cradle_outb (0x4f, base, CRADLE_SIO_INDEX); - cradle_outb (0x09, base, CRADLE_SIO_DATA); - - /* read ID from SIO to check operation */ - cradle_outb (0xe4, base, 0x3f8 + 0x3); - val = cradle_inb (base, 0x3f8 + 0x0); - if ((val & 0xf0) != 0x20) { - set_led (led, RED); - /* disable SCC2 */ - cradle_outb (0, base, CRADLE_SIO_INDEX); - cradle_outb (0, base, CRADLE_SIO_DATA); - return -1; - } - /* set back to bank 0 */ - cradle_outb (0, base, 0x3f8 + 0x3); - set_led (led, GREEN); - return 0; -} - -/* - * Miscelaneous platform dependent initialisations - */ - -int -/**********************************************************/ -board_late_init (void) -/**********************************************************/ -{ - return (0); -} - -int -/**********************************************************/ -board_init (void) -/**********************************************************/ -{ - DECLARE_GLOBAL_DATA_PTR; - - led_code (0xf, YELLOW); - - /* arch number of HHP Cradle */ - gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Init SIOs to enable SCC2 */ - udelay (100000); /* delay makes it look neat */ - init_sio (0, CRADLE_SIO1_PHYS); - udelay (100000); - init_sio (1, CRADLE_SIO2_PHYS); - udelay (100000); - init_sio (2, CRADLE_SIO3_PHYS); - udelay (100000); - set_led (3, GREEN); - - return 1; -} - -int -/**********************************************************/ -dram_init (void) -/**********************************************************/ -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; - - return (PHYS_SDRAM_1_SIZE + - PHYS_SDRAM_2_SIZE + - PHYS_SDRAM_3_SIZE + - PHYS_SDRAM_4_SIZE ); -} diff --git a/board/cradle/flash.c b/board/cradle/flash.c deleted file mode 100644 index f3f9a8c..0000000 --- a/board/cradle/flash.c +++ /dev/null @@ -1,359 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define FLASH_BANK_SIZE 0x400000 -#define MAIN_SECT_SIZE 0x20000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - switch (i) { - case 0: - flashbase = PHYS_FLASH_1; - break; - case 1: - flashbase = PHYS_FLASH_2; - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i, j; - - for (j = 0; j < CFG_MAX_FLASH_BANKS; j++) { - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F320J3A & FLASH_TYPEMASK): - printf ("28F320J3A (32Mbit)\n"); - break; - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf ("28F128J3 (128Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - info++; - } - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ - - while ((*addr & 0x80) != 0x80) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - - /* clear status register command */ - *addr = 0x50; - /* reset to read mode */ - *addr = 0xFF; - } - printf ("ok.\n"); - } - if (ctrlc ()) - printf ("User Interrupt!\n"); - -outahere: - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest, val; - int rc = ERR_OK; - int flag; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* clear status register command */ - *addr = 0x50; - - /* program set-up command */ - *addr = 0x40; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - /* suspend program command */ - *addr = 0xB0; - goto outahere; - } - } - - if (val & 0x1A) { /* check for error */ - printf ("\nFlash write error %02x at address %08lx\n", - (int) val, (unsigned long) dest); - if (val & (1 << 3)) { - printf ("Voltage range error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if (val & (1 << 1)) { - printf ("Device protect error.\n"); - rc = ERR_PROTECTED; - goto outahere; - } - if (val & (1 << 4)) { - printf ("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - -outahere: - /* read array command */ - *addr = 0xFF; - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word (info, wp, data); -} diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S deleted file mode 100644 index 2fd307f..0000000 --- a/board/cradle/lowlevel_init.S +++ /dev/null @@ -1,515 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - - .macro SET_LED val - ldr r6, =CRADLE_LED_CLR_REG - ldr r7, =0 - str r7, [r6] - ldr r6, =CRADLE_LED_SET_REG - ldr r7, =\val - str r7, [r6] - .endm - - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - - /* Set up GPIO pins first */ - - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GRER0 - ldr r1, =CFG_GRER0_VAL - str r1, [r0] - - ldr r0, =GRER1 - ldr r1, =CFG_GRER1_VAL - str r1, [r0] - - ldr r0, =GRER2 - ldr r1, =CFG_GRER2_VAL - str r1, [r0] - - ldr r0, =GFER0 - ldr r1, =CFG_GFER0_VAL - str r1, [r0] - - ldr r0, =GFER1 - ldr r1, =CFG_GFER1_VAL - str r1, [r0] - - ldr r0, =GFER2 - ldr r1, =CFG_GFER2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - /* enable GPIO pins */ - ldr r0, =PSSR - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - - SET_LED 1 - - ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */ - ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */ - str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */ - ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */ - - -/********************************************************************* - Initlialize Memory Controller - - See PXA250 Operating System Developer's Guide - - pause for 200 uSecs- allow internal clocks to settle - *Note: only need this if hard reset... doing it anyway for now -*/ - - @ Step 1 - @ ---- Wait 200 usec - ldr r3, =OSCR @ reset the OS Timer Count to zero - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - SET_LED 2 - -mem_init: - @ get memory controller base address - ldr r1, =MEMC_BASE - - -@**************************************************************************** -@ Step 2 -@ - - @ Step 2a - @ write msc0, read back to ensure data latches - @ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] - - @ write msc1 - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - @ write msc2 - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - @ Step 2b - @ write mecr - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - - @ write mcmem0 - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - - @ write mcmem1 - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - - @ write mcatt0 - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - - @ write mcatt1 - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - - @ write mcio0 - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - - @ write mcio1 - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - - /*SET_LED 3 */ - - @ Step 2c - @ fly-by-dma is defeatured on this part - @ write flycnfg - @ldr r2, =CFG_FLYCNFG_VAL - @str r2, [r1, #FLYCNFG_OFFSET] - -/* FIXME Does this sequence really make sense */ -#ifdef REDBOOT_WAY - @ Step 2d - @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL - - @ extract DRI field (we need a valid DRI field) - @ - ldr r2, =0xFFF - - @ valid DRI field in r3 - @ - and r3, r3, r2 - - @ get the reset state of MDREFR - @ - ldr r4, [r1, #MDREFR_OFFSET] - - @ clear the DRI field - @ - bic r4, r4, r2 - - @ insert the valid DRI field loaded above - @ - orr r4, r4, r3 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ *Note: preserve the mdrefr value in r4 * - - /*SET_LED 4 */ - -@**************************************************************************** -@ Step 3 -@ -@ NO SRAM - - mov pc, r10 - - -@**************************************************************************** -@ Step 4 -@ - - @ Assumes previous mdrefr value in r4, if not then read current mdrefr - - @ clear the free-running clock bits - @ (clear K0Free, K1Free, K2Free - @ - bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000) - - @ set K0RUN for CPLD clock - @ - orr r4, r4, #0x00002000 - - @ set K1RUN if bank 0 installed - @ - orr r4, r4, #0x00010000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - @ deassert SLFRSH - @ - bic r4, r4, #0x00400000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ assert E1PIN - @ - orr r4, r4, #0x00008000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - nop - nop -#else - @ Step 2d - @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ Step 4 - - @ set K0RUN for CPLD clock - @ - orr r4, r4, #0x00002000 - - @ set K1RUN for bank 0 - @ - orr r4, r4, #0x00010000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - @ deassert SLFRSH - @ - bic r4, r4, #0x00400000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ assert E1PIN - @ - orr r4, r4, #0x00008000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - nop - nop -#endif - - @ Step 4d - @ fetch platform value of mdcnfg - @ - ldr r2, =CFG_MDCNFG_VAL - - @ disable all sdram banks - @ - bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) - bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3) - - @ program banks 0/1 for bus width - @ - bic r2, r2, #MDCNFG_DWID0 @0=32-bit - - @ write initial value of mdcnfg, w/o enabling sdram banks - @ - str r2, [r1, #MDCNFG_OFFSET] - - @ Step 4e - @ pause for 200 uSecs - @ - ldr r3, =OSCR @ reset the OS Timer Count to zero - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - /*SET_LED 5 */ - - /* Why is this here??? */ - mov r0, #0x78 @turn everything off - mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.) - - @ Step 4f - @ Access memory *not yet enabled* for CBR refresh cycles (8) - @ - CBR is generated for all banks - - ldr r2, =CFG_DRAM_BASE - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - - @ Step 4g - @get memory controller base address - @ - ldr r1, =MEMC_BASE - - @fetch current mdcnfg value - @ - ldr r3, [r1, #MDCNFG_OFFSET] - - @enable sdram bank 0 if installed (must do for any populated bank) - @ - orr r3, r3, #MDCNFG_DE0 - - @write back mdcnfg, enabling the sdram bank(s) - @ - str r3, [r1, #MDCNFG_OFFSET] - - @ Step 4h - @ write mdmrs - @ - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - @ Done Memory Init - - /*SET_LED 6 */ - - @******************************************************************** - @ Disable (mask) all interrupts at the interrupt controller - @ - - @ clear the interrupt level register (use IRQ, not FIQ) - @ - mov r1, #0 - ldr r2, =ICLR - str r1, [r2] - - @ Set interrupt mask register - @ - ldr r1, =CFG_ICMR_VAL - ldr r2, =ICMR - str r1, [r2] - - @ ******************************************************************** - @ Disable the peripheral clocks, and set the core clock - @ - - @ Turn Off ALL on-chip peripheral clocks for re-configuration - @ - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - @ set core clocks - @ - ldr r2, =CFG_CCCR_VAL - ldr r1, =CCCR - str r2, [r1] - -#ifdef ENABLE32KHZ - @ enable the 32Khz oscillator for RTC and PowerManager - @ - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - @ NOTE: spin here until OSCC.OOK get set, - @ meaning the PLL has settled. - @ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#endif - - @ Turn on needed clocks - @ - ldr r1, =CKEN - ldr r2, =CFG_CKEN_VAL - str r2, [r1] - - /*SET_LED 7 */ - -/* Is this needed???? */ -#define NODEBUG -#ifdef NODEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ - -#endif - - /*SET_LED 8 */ - - mov pc, r10 - -@ End lowlevel_init diff --git a/board/cradle/u-boot.lds b/board/cradle/u-boot.lds deleted file mode 100644 index f010239..0000000 --- a/board/cradle/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c deleted file mode 100644 index a7114eb..0000000 --- a/board/cray/L1/L1.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include <405gp_i2c.h> -#include -#include -#include -#include -#include - -#define L1_MEMSIZE (32*1024*1024) - -/* the std. DHCP stufff */ -#define DHCP_ROUTER 3 -#define DHCP_NETMASK 1 -#define DHCP_BOOTFILE 67 -#define DHCP_ROOTPATH 17 -#define DHCP_HOSTNAME 12 - -/* some extras used by CRAY - * - * on the server this looks like: - * - * option L1-initrd-image code 224 = string; - * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image" - */ -#define DHCP_L1_INITRD 224 - -/* new, [better?] way via official vendor-extensions, defining an option - * space. - * on the server this looks like: - * - * option space CRAYL1; - * option CRAYL1.initrd code 3 = string; - * ..etc... - */ -#define DHCP_VENDOR_SPECX 43 -#define DHCP_VX_INITRD 3 -#define DHCP_VX_BOOTCMD 4 -#define DHCP_VX_BOOTARGS 5 -#define DHCP_VX_ROOTDEV 6 -#define DHCP_VX_FROMFLASH 7 -#define DHCP_VX_BOOTSCRIPT 8 -#define DHCP_VX_RCFILE 9 -#define DHCP_VX_MAGIC 10 - -/* Things DHCP server can tellme about. If there's no flash address, then - * they dont participate in 'update' to flash, and we force their values - * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I - * know this is a pain... - * - * If I get no bootfile, boot from flash. If rootpath, use that. If no - * rootpath use initrd in flash. - */ -typedef struct dhcp_item_s { - u8 dhcp_option; - u8 dhcp_vendor_option; - char *dhcpvalue; - char *envname; -} dhcp_item_t; -static dhcp_item_t Things[] = { - {DHCP_ROUTER, 0, NULL, "gateway"}, - {DHCP_NETMASK, 0, NULL, "netmask"}, - {DHCP_BOOTFILE, 0, NULL, "bootfile"}, - {DHCP_ROOTPATH, 0, NULL, "rootpath"}, - {DHCP_HOSTNAME, 0, NULL, "hostname"}, - {DHCP_L1_INITRD, 0, NULL, "initrd"}, -/* and the other way.. */ - {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"}, - {DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"}, - {DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"}, - {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL}, - {DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL} -}; - -#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t))) - -extern char bootscript[]; - -/* Here is the boot logic as HUSH script. Overridden by any TFP provided - * bootscript file. - */ - -static void init_sdram (void); - -/* ------------------------------------------------------------------------- */ -int board_early_init_f (void) -{ - /* Running from ROM: global data is still READONLY */ - init_sdram (); - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - return 0; -} - -/* ------------------------------------------------------------------------- */ -int checkboard (void) -{ - return (0); -} -/* ------------------------------------------------------------------------- */ - -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ - char *s, *e; - image_header_t *hdr; - time_t timestamp; - struct rtc_time tm; - char bootcmd[32]; - - hdr = (image_header_t *) (CFG_MONITOR_BASE - sizeof (image_header_t)); - timestamp = (time_t) hdr->ih_time; - to_tm (timestamp, &tm); - printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); - -#define FACTORY_SETTINGS 0xFFFC0000 - if ((s = getenv ("ethaddr")) == NULL) { - e = (char *) (FACTORY_SETTINGS); - if (*(e + 0) != '0' - || *(e + 1) != '0' - || *(e + 2) != ':' - || *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') { - printf ("No valid MAC address in flash location 0x3C0000!\n"); - } else { - printf ("Factory MAC: %s\n", e); - setenv ("ethaddr", e); - } - } - sprintf (bootcmd,"autoscript %X",(unsigned)bootscript); - setenv ("bootcmd", bootcmd); - return (0); -} - -/* ------------------------------------------------------------------------- */ -long int initdram (int board_type) -{ - return (L1_MEMSIZE); -} - -/* ------------------------------------------------------------------------- */ -/* stubs so we can print dates w/o any nvram RTC.*/ -void rtc_get (struct rtc_time *tmp) -{ - return; -} -void rtc_set (struct rtc_time *tmp) -{ - return; -} -void rtc_reset (void) -{ - return; -} - -/* ------------------------------------------------------------------------- */ -/* Do sdram bank init in C so I can read it..no console to print to yet! - */ -static void init_sdram (void) -{ - unsigned long tmp; - - /* write SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, 0x00062001); - -/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ -/* To set the appropriate timings, we need to know the SDRAM speed. */ -/* We can use the PLB speed since the SDRAM speed is the same as */ -/* the PLB speed. The PLB speed is the FBK divider times the */ -/* 405GP reference clock, which on the L1 is 25Mhz. */ -/* Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is */ -/* 150Mhz; if FBK is 3, SDRAM is 150Mhz. */ - - /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ - -/* write SDRAM timing for 100Mhz. */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, 0x0086400D); - -/* write SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, 0x05F00000); - udelay (200); - -/* sdram controller.*/ - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, 0x90800000); - udelay (200); - -/* initially, disable ECC on all banks */ - udelay (200); - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); - tmp &= 0xff0fffff; - mtdcr (memcfga, mem_ecccf); - mtdcr (memcfgd, tmp); - - return; -} - -extern int memory_post_test (int flags); - -int testdram (void) -{ - unsigned long tmp; - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) L1_MEMSIZE; - uint *p; - - if (getenv_r("booted",NULL,0) <= 0) - { - printf ("testdram.."); - /*AA*/ - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, 0xaaaaaaaa); - return 1; - } - } - /*55*/ - for (p = pstart; p < pend; p++) - *p = 0x55555555; - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, 0x55555555); - return 1; - } - } - /*addr*/ - for (p = pstart; p < pend; p++) - *p = (unsigned)p; - for (p = pstart; p < pend; p++) { - if (*p != (unsigned)p) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, (uint)p); - return 1; - } - } - printf ("Success. "); - } - printf ("Enable ECC.."); - - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); - udelay (600); - for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) - ; - udelay (400); - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); - tmp |= 0x00800000; - mtdcr (memcfgd, tmp); - udelay (400); - printf ("enabled.\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ -static u8 *dhcp_env_update (u8 thing, u8 * pop) -{ - u8 i, oplen; - - oplen = *(pop + 1); - - if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) { - printf ("Whoops! failed to malloc space for DHCP thing %s\n", - Things[thing].envname); - return NULL; - } - for (i = 0; (i < oplen); i++) - if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ') - break; - *(Things[thing].dhcpvalue + i) = '\0'; - -/* set env. */ - if (Things[thing].envname) - { - setenv (Things[thing].envname, Things[thing].dhcpvalue); - } - return ((u8 *)(Things[thing].dhcpvalue)); -} - -/* ------------------------------------------------------------------------- */ -u8 *dhcp_vendorex_prep (u8 * e) -{ - u8 thing; - -/* ask for the things I want. */ - *e++ = 55; /* Parameter Request List */ - *e++ = N_THINGS; - for (thing = 0; thing < N_THINGS; thing++) - *e++ = Things[thing].dhcp_option; - *e++ = 255; - - return e; -} - -/* ------------------------------------------------------------------------- */ -/* .. return NULL means it wasnt mine, non-null means I got it..*/ -u8 *dhcp_vendorex_proc (u8 * pop) -{ - u8 oplen, *sub_op, sub_oplen, *retval; - u8 thing = 0; - - retval = NULL; - oplen = *(pop + 1); -/* if pop is vender spec indicator, there are sub-options. */ - if (*pop == DHCP_VENDOR_SPECX) { - for (sub_op = pop + 2; - oplen && (sub_oplen = *(sub_op + 1)); - oplen -= sub_oplen, sub_op += (sub_oplen + 2)) { - for (thing = 0; thing < N_THINGS; thing++) { - if (*sub_op == Things[thing].dhcp_vendor_option) { - if (!(retval = dhcp_env_update (thing, sub_op))) { - return NULL; - } - } - } - } - } else { - for (thing = 0; thing < N_THINGS; thing++) { - if (*pop == Things[thing].dhcp_option) - if (!(retval = dhcp_env_update (thing, pop))) - return NULL; - } - } - return (pop); -} diff --git a/board/cray/L1/L1.h b/board/cray/L1/L1.h deleted file mode 100644 index 1b41824..0000000 --- a/board/cray/L1/L1.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip - * - * Start Address Length - * +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash ----------------- - * | Failsafe Linux Image | (1M) - * +=======================+ 0xFFD0_0000 - * | (Reserved FlashFiles) | (1M) - * +=======================+ 0xFFE0_0000 - * | Failsafe RootFS | (1M) - * +=======================+ 0xFFF0_0000 - * | | - * | U N U S E D | - * | | - * +-----------------------+ 0xFFFD_0000 U-Boot image header (64 bytes) - * | environment settings | (64k) - * +-----------------------+ 0xFFFE_0000 U-Boot image header (64 bytes) - * | U-Boot | 0xFFFE_0040 _start of U-Boot - * | | 0xFFFE_FFFC reset vector - branch to _start - * +++++++++++++++++++++++++ 0xFFFF_FFFF End of Flash ----------------- - *****************************************************************************/ diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile deleted file mode 100644 index bfe0922..0000000 --- a/board/cray/L1/Makefile +++ /dev/null @@ -1,57 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o -SOBJS = init.o - -# HACK: depend needs bootscript.c, which needs tools/mkimage, which is not -# built in the depend stage. So... put bootscript.o here, not in OBJS -$(LIB): $(OBJS) $(SOBJS) bootscript.o - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) bootscript.c bootscript.image bootscript.o - -distclean: clean - rm -f $(LIB) core *.bak .depend - -$(BOARD).o : $(BOARD).c bootscript.o - -bootscript.c: bootscript.image - od -t x1 -v -A x $^ | awk -f x2c.awk > $@ - -bootscript.image: bootscript.hush Makefile - -$(TOPDIR)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d bootscript.hush $@ - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/cray/L1/bootscript.hush b/board/cray/L1/bootscript.hush deleted file mode 100644 index ec4839b..0000000 --- a/board/cray/L1/bootscript.hush +++ /dev/null @@ -1,117 +0,0 @@ -# $Header$ -# hush bootscript for PPCBOOT on L1 -# note: all #s are in hex, do _NOT_ prefix it with 0x - -flash_rfs=ffc00000 -flash_krl=fff00000 -tftp_addr=100000 -tftp2_addr=1000000 - -if printenv booted -then - echo already booted before -else - echo first boot in environment, create and save settings - setenv booted OK - saveenv -fi - -setenv autoload no -# clear out stale env stuff, so we get fresh from dhcp. -for setting in initrd fromflash kernel rootfs rootpath -do -setenv $setting -done - -dhcp - -# if host provides us with a different bootscript, us it. -if printenv bootscript - then - tftp $tftp_addr $bootcript - if imi $tftp_addr - then - autoscript $tftp_addr - fi -fi - -# default base kernel arguments. -setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120 - -# Have a kernel in flash? -if imi $flash_krl -then - echo ok kernel to boot from $flash_krl - setenv kernel $flash_krl -else - echo no kernel to boot from $flash_krl, need tftp -fi - -# Have a rootfs in flash? -echo test for SQUASHfs at $flash_rfs - -if imi $flash_rfs -then - echo appears to be a good initrd image at base of flash OK - setenv rootfs $flash_rfs -else - echo no image at base of flash, need nfsroot or initrd -fi - -# I boot from flash if told to and I can. -if printenv fromflash && printenv kernel && printenv rootfs -then - echo booting entirely from flash - setenv bootargs root=/dev/ram0 rw $bootargs - bootm $kernel $rootfs - echo oh no failed so I try some other stuff -fi - -# TFTP down a kernel -if printenv bootfile -then - tftp $tftp_addr $bootfile - setenv kernel $tftp_addr - echo I will boot the TFTP kernel -else - if printenv kernel - then - echo no bootfile specified, will use one from flash - else - setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image - echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile - tftp $tftp_addr $bootfile - setenv kernel $tftp_addr - fi -fi - -# the rootfs. -if printenv rootpath -then - echo rootpath is $rootpath - if printenv initrd - then - echo initrd is also specified, so use $initrd - tftp $tftp2_addr $initrd - setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs - bootm $kernel $tftp2_addr - else - echo initrd is not specified, so use NFSROOT $rootpat - setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs - bootm $kernel - fi -else - echo we have no rootpath check for one in flash - if printenv rootfs - then - echo I will use the one in flash - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs - bootm $kernel - else - setenv rootpath /export/crayl1 - echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs - bootm $kernel - fi -fi -reset diff --git a/board/cray/L1/config.mk b/board/cray/L1/config.mk deleted file mode 100644 index b69fe8e..0000000 --- a/board/cray/L1/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# Note: I make an "image" from U-Boot itself, which prefixes 0x40 bytes of -# header info, hence start address is thus shifted. -TEXT_BASE = 0xFFFD0040 diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c deleted file mode 100644 index f313274..0000000 --- a/board/cray/L1/flash.c +++ /dev/null @@ -1,470 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -/* - * Modified July 20, 2001 - * Strip down to support ONLY the AMD29F032B. - * Dave Updegraff - Cray, Inc. dave@cray.com - */ - -#include -#include -#include - -/* The flash chip we use... */ -#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */ -#define FLASH_AM320B 0x0009 - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; isector_count; i++) - info->start[i] = base + (i * 0x00010000); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F032B: - info->flash_id += FLASH_AM320B; - info->sector_count = 64; - info->size = 0x0400000; /* => 4 MB */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - printf("Erasing sector %p\n", addr2); - - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *)dest) & - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S deleted file mode 100644 index 72a10d3..0000000 --- a/board/cray/L1/init.S +++ /dev/null @@ -1,147 +0,0 @@ -/*------------------------------------------------------------------------------+ */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ - -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - NVRAM/RTC */ -/* Bank 2 - Keyboard/Mouse controller */ -/* Bank 3 - IR controller */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - FPGA registers */ -/*-----------------------------------------------------------------------------#include */ -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */ -/* except for #1 which we use for DMA'ing to IOCA-like things, so the */ -/* control registers to set that up are determined by what we've */ -/* empirically discovered work there. */ - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ - - /*------------------------------------------------------------------- */ - /* Delay to ensure all accesses to ROM are complete before changing */ - /* bank 0 timings. 200usec should be enough. */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - - /*---------------------------------------------------------------------- */ - /* Peripheral Bank 0 (Flash) initialization */ - /*---------------------------------------------------------------------- */ - /* 0x7F8FFE80 slowest boot */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 - addis r4,0,0x9B01 - ori r4,r4,0x5480 - mtdcr ebccfgd,r4 - - addi r4,0,pb0cr - mtdcr ebccfga,r4 - addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr ebccfgd,r4 - - blr - - /*---------------------------------------------------------------------- */ - /* Peripheral Bank 1 (NVRAM/RTC) initialization */ - /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */ - /* and we do DMA on it. The ConfigurationRegister part is threfore */ - /* almost arbitrary, except that our linux driver needs to know the */ - /* address, but it can query, it.. */ - /* */ - /* The AccessParameter is CRITICAL, */ - /* thouch, since it needs to agree with the electrical timings on the */ - /* IOCA parallel interface. That value is: 0x0185,4380 */ - /* BurstModeEnable BME=0 */ - /* TransferWait TWT=3 */ - /* ChipSelectOnTiming CSN=1 */ - /* OutputEnableOnTimimg OEN=1 */ - /* WriteByteEnableOnTiming WBN=1 */ - /* WriteByteEnableOffTiming WBF=0 */ - /* TransferHold TH=1 */ - /* ReadyEnable RE=1 */ - /* SampleOnReady SOR=1 */ - /* ByteEnableMode BEM=0 */ - /* ParityEnable PEN=0 */ - /* all reserved bits=0 */ - /*---------------------------------------------------------------------- */ - /*---------------------------------------------------------------------- */ - addi r4,0,pb1ap - mtdcr ebccfga,r4 - addis r4,0,0x0185 /* hiword */ - ori r4,r4,0x4380 /* loword */ - mtdcr ebccfgd,r4 - - addi r4,0,pb1cr - mtdcr ebccfga,r4 - addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr ebccfgd,r4 - - blr - -/*----------------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: Configures SDRAM memory banks. */ -/* NOTE: for CrayL1 we have ECC memory, so enable it. */ -/*....now done in C in L1.c:init_sdram for readability. */ -/*----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - blr diff --git a/board/cray/L1/patchme b/board/cray/L1/patchme deleted file mode 100644 index e77ee7e..0000000 --- a/board/cray/L1/patchme +++ /dev/null @@ -1,30 +0,0 @@ -# master confi.mk -echo "CROSS_COMPILE = powerpc-linux-" >>include/config.mk - -# patch the examples/Makefile to ignore return value from OBJCOPY -sed -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile - -# add a built target for mkimage on the target architecture -sed -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile - -cat <>tools/makefile -mkimage.ppc : mkimage.o.ppc crc32.o.ppc - powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^ - powerpc-linux-strip $@ - -XFLAGS="-D__KERNEL__ -I../include -DCONFIG_4xx -Wall -Wstict-prototypes" -mkimage.o.ppc: mkimage.c - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ - -crc32.o.ppc: crc32.c - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ - -EOF - -# make an image by default out of the u-boot image -sed -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile -cat <>makefile -u-boot.image: u-boot.bin - tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@ - -EOF diff --git a/board/cray/L1/u-boot.lds b/board/cray/L1/u-boot.lds deleted file mode 100644 index cf4bbb9..0000000 --- a/board/cray/L1/u-boot.lds +++ /dev/null @@ -1,153 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/cray/L1/init.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/*. = env_offset;*/ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug deleted file mode 100644 index 1608f8c..0000000 --- a/board/cray/L1/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cray/L1/x2c.awk b/board/cray/L1/x2c.awk deleted file mode 100644 index 9235e6c..0000000 --- a/board/cray/L1/x2c.awk +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/awk -BEGIN { print "unsigned char bootscript[] = { \n"} -{ for (i = 2; i <= NF ; i++ ) printf "0x"$i"," - print "" -} -END { print "\n};\n" } diff --git a/board/csb226/Makefile b/board/csb226/Makefile deleted file mode 100644 index 5b311a9..0000000 --- a/board/csb226/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := csb226.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/csb226/config.mk b/board/csb226/config.mk deleted file mode 100644 index 2354392..0000000 --- a/board/csb226/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -# Linux-Kernel is expected to be at c000'8000, entry c000'8000 -# -# we load ourself to c170'0000, the upper 1 MB of second bank -# -# download areas is c800'0000 -# - -# This is the address where U-Boot lives in flash: -#TEXT_BASE = 0 - -# FIXME: armboot does only work correctly when being compiled -# for the addresses _after_ relocation to RAM!! Otherwhise the -# .bss segment is assumed in flash... -TEXT_BASE = 0xa1fe0000 diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c deleted file mode 100644 index c99a715..0000000 --- a/board/csb226/csb226.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de - * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net - * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -/** - * misc_init_r: - misc initialisation routines - */ - -int misc_init_r(void) -{ -#if 0 - uchar *str; - - /* determine if the software update key is pressed during startup */ - /* not ported yet... */ - if (GPLR0 & 0x00000800) { - printf("using bootcmd_normal (sw-update button not pressed)\n"); - str = getenv("bootcmd_normal"); - } else { - printf("using bootcmd_update (sw-update button pressed)\n"); - str = getenv("bootcmd_update"); - } - - setenv("bootcmd",str); -#endif - return 0; -} - - -/** - * board_init: - setup some data structures - * - * @return: 0 in case of success - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of CSB226 board */ - gd->bd->bi_arch_number = MACH_TYPE_CSB226; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - - -/** - * dram_init: - setup dynamic RAM - * - * @return: 0 in case of success - */ - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - - -/** - * csb226_set_led: - switch LEDs on or off - * - * @param led: LED to switch (0,1,2) - * @param state: switch on (1) or off (0) - */ - -void csb226_set_led(int led, int state) -{ - switch(led) { - - case 0: if (state==1) { - GPCR0 |= CSB226_USER_LED0; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED0; - } - break; - - case 1: if (state==1) { - GPCR0 |= CSB226_USER_LED1; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED1; - } - break; - - case 2: if (state==1) { - GPCR0 |= CSB226_USER_LED2; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED2; - } - break; - } - - return; -} - - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - * The CSB226 does only have 3 LEDs, so we switch them on at the most - * important states (1, 5, 15). - */ - -void show_boot_progress (int status) -{ - switch(status) { - case 1: csb226_set_led(0,1); break; - case 5: csb226_set_led(1,1); break; - case 15: csb226_set_led(2,1); break; - } - - return; -} diff --git a/board/csb226/flash.c b/board/csb226/flash.c deleted file mode 100644 index f6dfd96..0000000 --- a/board/csb226/flash.c +++ /dev/null @@ -1,366 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, - * - * (C) Copyright 2003 (2 x 16 bit Flash bank patches) - * Rolf Peukert, IMMS gGmbH, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define FLASH_BANK_SIZE 0x02000000 -#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -/** - * flash_init: - initialize data structures for flash chips - * - * @return: size of the flash - */ - -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - - switch (i) { - case 0: - flashbase = PHYS_FLASH_1; - break; - default: - panic("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); - - return size; -} - - -/** - * flash_print_info: - print information about the flash situation - */ - -void flash_print_info (flash_info_t *info) -{ - int i, j; - - for (j=0; jflash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf("28F128J3 (128Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - info++; - } -} - - -/** - * flash_erase: - erase flash sectors - */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) prot++; - } - - if (prot) return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { - - printf("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - if (info->protect[sect] == 0) { /* not protected */ - u32 * volatile addr = (u32 * volatile)(info->start[sect]); - - /* erase sector: */ - /* The strata flashs are aligned side by side on */ - /* the data bus, so we have to write the commands */ - /* to both chips here: */ - - *addr = 0x00200020; /* erase setup */ - *addr = 0x00D000D0; /* erase confirm */ - - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { - *addr = 0x00B000B0; /* suspend erase*/ - *addr = 0x00FF00FF; /* read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* reset to read mode */ - } - printf("ok.\n"); - } - if (ctrlc()) printf("User Interrupt!\n"); - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked(10000); - - if (flag) enable_interrupts(); - - return rc; -} - -/** - * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each - */ - -static int write_long (flash_info_t *info, ulong dest, ulong data) -{ - u32 * volatile addr = (u32 * volatile)dest, val; - int rc = ERR_OK; - int flag; - - /* read array command - just for the case... */ - *addr = 0x00FF00FF; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts(); - - /* clear status register command */ - *addr = 0x00500050; - - /* program set-up command */ - *addr = 0x00400040; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - /* wait while polling the status register */ - while(((val = *addr) & 0x00800080) != 0x00800080) { - if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - /* suspend program command */ - *addr = 0x00B000B0; - goto outahere; - } - } - - /* check for errors */ - if(val & 0x001A001A) { - printf("\nFlash write error %02x at address %08lx\n", - (int)val, (unsigned long)dest); - if(val & 0x00080008) { - printf("Voltage range error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if(val & 0x00020002) { - printf("Device protect error.\n"); - rc = ERR_PROTECTED; - goto outahere; - } - if(val & 0x00100010) { - printf("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - -outahere: - /* read array command */ - *addr = 0x00FF00FF; - if (flag) enable_interrupts(); - - return rc; -} - - -/** - * write_buf: - Copy memory to flash. - * - * @param info: - * @param src: source of copy transaction - * @param addr: where to copy to - * @param cnt: number of bytes to copy - * - * @return error code - */ - -/* "long" version, uses 32bit words */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ulong data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 24); - } - for (; i<4 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - if ((rc = write_long(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((ulong*)src); - if ((rc = write_long(info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - return write_long(info, wp, data); -} diff --git a/board/csb226/lowlevel_init.S b/board/csb226/lowlevel_init.S deleted file mode 100644 index aa9dcba..0000000 --- a/board/csb226/lowlevel_init.S +++ /dev/null @@ -1,437 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -_TEXT_BASE: - .word TEXT_BASE - - -/* - * Memory setup - */ - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - - /* Set up GPIO pins first ----------------------------------------- */ - - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - -/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ -/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */ -/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ -/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ -/* */ -/* ldr r1, =LED_BLANK */ -/* mov r0, #0xFF */ -/* str r0, [r1] / turn on hex leds */ -/* */ -/*loop: */ -/* */ -/* ldr r0, =0xB0070001 */ -/* ldr r1, =_LED */ -/* str r0, [r1] / hex display */ - - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1, =MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - - /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ - adr r3, mem_init /* r0 <- current position of code */ - ldr r2, =mem_init - cmp r3, r2 /* skip init if in place */ - beq initirqs - - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r3, =CFG_MDREFR_VAL - ldr r2, =0xFFF - and r3, r3, r2 - ldr r4, =0x03ca4000 - orr r4, r4, r3 - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - /* FIXME: we use async mode for now */ - - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - /* Step 4a: assert MDREFR:K?RUN and configure */ - /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - - ldr r4, =CFG_MDREFR_VAL - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Step 4b: de-assert MDREFR:SLFRSH. */ - - bic r4, r4, #(MDREFR_SLFRSH) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4c: assert MDREFR:E1PIN and E0PIO */ - - orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ - /* configure but not enable each SDRAM partition pair. */ - - ldr r4, =CFG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - /* There should 9 writes, since the first write doesn't */ - /* trigger a refresh cycle on PXA250. See Intel PXA250 and */ - /* PXA210 Processors Specification Update, */ - /* Jan 2003, Errata #116, page 30. */ - - - ldr r3, =CFG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* (MDCNFG:DEx set to 1). */ - - ldr r3, [r1, #MDCNFG_OFFSET] - orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) - str r3, [r1, #MDCNFG_OFFSET] - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - - /* We are finished with Intel's memory controller initialisation */ - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - /* (hard-coding at 398.12MHz for now). */ - - /* Turn Off ALL on-chip peripheral clocks for re-configuration */ - /* Note: See label 'ENABLECLKS' for the re-enabling */ - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - - /* default value in case no valid rotary switch setting is found */ - ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ - - /* ... and write the core clock config register */ - ldr r1, =CCCR - str r2, [r1] - - /* enable the 32Khz oscillator for RTC and PowerManager */ -/* - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] -*/ - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b - - /* ---------------------------------------------------------------- */ - /* */ - /* ---------------------------------------------------------------- */ - - /* Save SDRAM size */ - ldr r1, =DRAM_SIZE - str r8, [r1] - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - - /* FIXME */ - -#ifndef DEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ -#endif - - /* ---------------------------------------------------------------- */ - /* End lowlevel_init */ - /* ---------------------------------------------------------------- */ - -endlowlevel_init: - - mov pc, lr diff --git a/board/csb226/u-boot.lds b/board/csb226/u-boot.lds deleted file mode 100644 index f010239..0000000 --- a/board/csb226/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/csb272/Makefile b/board/csb272/Makefile deleted file mode 100644 index 926e065..0000000 --- a/board/csb272/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -#OBJS = $(BOARD).o flash.o -#OBJS = $(BOARD).o strataflash.o -OBJS = $(BOARD).o - -SOBJS = init.o - - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/csb272/config.mk b/board/csb272/config.mk deleted file mode 100644 index 4672f08..0000000 --- a/board/csb272/config.mk +++ /dev/null @@ -1,36 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004 -# Tolunay Orkun, NextIO Inc., torkun@nextio.com. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Cogent CSB272 board -# - -LDFLAGS += $(LINKER_UNDEFS) - -TEXT_BASE := 0xFFFC0000 -#TEXT_BASE := 0x00100000 - -PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS) diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c deleted file mode 100644 index 24c6f0d..0000000 --- a/board/csb272/csb272.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -/* - * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator - * - * CLKA output => Epson LCD Controller - * CLKB output => Not Connected - * CLKC output => Ethernet - * CLKD output => UART external clock - * - * Note: these values are obtained from device after init by micromonitor -*/ -uchar pll_fs6377_regs[16] = { - 0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80, - 0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 }; - -/* - * pll_init: Initialize AMIS IC FS6377-01 PLL - * - * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock - * - */ -int pll_init(void) -{ - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); - - return i2c_write(CFG_I2C_PLL_ADDR, 0, 1, - (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs)); -} - -/* - * board_early_init_f: do early board initialization - * - */ -int board_early_init_f(void) -{ - /* initialize PLL so UART, LCD, Ethernet clocked at correctly */ - (void) get_clocks(); - pll_init(); - - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - - mtebc (epcr, 0xa8400000); /* EBC always driven */ - - return 0; /* success */ -} - -/* - * checkboard: identify/verify the board we are running - * - * Remark: we just assume it is correct board here! - * - */ -int checkboard(void) -{ - printf("BOARD: Cogent CSB272\n"); - - return 0; /* success */ -} - -/* - * initram: Determine the size of mounted DRAM - * - * Size is determined by reading SDRAM configuration registers as - * configured by initialization code - * - */ -long initdram (int board_type) -{ - ulong tot_size; - ulong bank_size; - ulong tmp; - - tot_size = 0; - - mtdcr (memcfga, mem_mb0cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (memcfga, mem_mb1cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (memcfga, mem_mb2cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (memcfga, mem_mb3cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - return tot_size; -} - -/* - * last_stage_init: final configurations (such as PHY etc) - * - */ -int last_stage_init(void) -{ - /* initialize the PHY */ - miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); - - /* AUTO neg */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - - /* LEDs */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); - - - return 0; /* success */ -} diff --git a/board/csb272/init.S b/board/csb272/init.S deleted file mode 100644 index e00ebf8..0000000 --- a/board/csb272/init.S +++ /dev/null @@ -1,216 +0,0 @@ -/****************************************************************************** - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - *****************************************************************************/ -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#define LI32(reg,val) \ - addis reg,0,val@h;\ - ori reg,reg,val@l - -#define WDCR_EBC(reg,val) \ - addi r4,0,reg;\ - mtdcr ebccfga,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr ebccfgd,r4 - -#define WDCR_SDRAM(reg,val) \ - addi r4,0,reg;\ - mtdcr memcfga,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr memcfgd,r4 - -/****************************************************************************** - * Function: ext_bus_cntlr_init - * - * Description: Configures EBC Controller and a few basic chip selects. - * - * CS0 is setup to get the Boot Flash out of the addresss range - * so that we may setup a stack. CS7 is setup so that we can - * access and reset the hardware watchdog. - * - * IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl ext_bus_cntlr_init - .type ext_bus_cntlr_init, @function -ext_bus_cntlr_init: - mflr r0 - /******************************************************************** - * Prefetch entire ext_bus_cntrl_init function into the icache. - * This is necessary because we are going to change the same CS we - * are executing from. Otherwise a CPU lockup may occur. - *******************************************************************/ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - - /* Calculate number of cache lines for this function */ - addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2) - mtctr r4 -..ebcloop: - icbt r0, r3 /* prefetch cache line for addr in r3*/ - addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */ - bdnz ..ebcloop /* continue for $CTR cache lines */ - - /******************************************************************** - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. - *******************************************************************/ - addis r3, 0, 0x0 - ori r3, r3, 0xA000 /* wait 200us from reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /******************************************************************** - * SETUP CPC0_CR0 - *******************************************************************/ - LI32(r4, 0x007000c0) - mtdcr cntrl0, r4 - - /******************************************************************** - * Setup CPC0_CR1: Change PCIINT signal to PerWE - *******************************************************************/ - mfdcr r4, cntrl1 - ori r4, r4, 0x4000 - mtdcr cntrl1, r4 - - /******************************************************************** - * Setup External Bus Controller (EBC). - *******************************************************************/ - WDCR_EBC(epcr, 0xd84c0000) - /******************************************************************** - * Memory Bank 0 (Intel 28F128J3 Flash) initialization - *******************************************************************/ - /*WDCR_EBC(pb0ap, 0x02869200)*/ - WDCR_EBC(pb0ap, 0x07869200) - WDCR_EBC(pb0cr, 0xfe0bc000) - /******************************************************************** - * Memory Bank 1 (Holtek HT6542B PS/2) initialization - *******************************************************************/ - WDCR_EBC(pb1ap, 0x1f869200) - WDCR_EBC(pb1cr, 0xf0818000) - /******************************************************************** - * Memory Bank 2 (Epson S1D13506) initialization - *******************************************************************/ - WDCR_EBC(pb2ap, 0x05860300) - WDCR_EBC(pb2cr, 0xf045a000) - /******************************************************************** - * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization - *******************************************************************/ - WDCR_EBC(pb3ap, 0x0387d200) - WDCR_EBC(pb3cr, 0xf021c000) - /******************************************************************** - * Memory Bank 4-7 (Unused) initialization - *******************************************************************/ - WDCR_EBC(pb4ap, 0) - WDCR_EBC(pb4cr, 0) - WDCR_EBC(pb5ap, 0) - WDCR_EBC(pb5cr, 0) - WDCR_EBC(pb6ap, 0) - WDCR_EBC(pb6cr, 0) - WDCR_EBC(pb7ap, 0) - WDCR_EBC(pb7cr, 0) - - /* We are all done */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ -.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init -/* end ext_bus_cntlr_init() */ - -/****************************************************************************** - * Function: sdram_init - * - * Description: Configures SDRAM memory banks. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl sdram_init - .type sdram_init, @function -sdram_init: - - /* - * Disable memory controller to allow - * values to be changed. - */ - WDCR_SDRAM(mem_mcopt1, 0x00000000) - - /* - * Configure Memory Banks - */ - WDCR_SDRAM(mem_mb0cf, 0x00084001) - WDCR_SDRAM(mem_mb1cf, 0x00000000) - WDCR_SDRAM(mem_mb2cf, 0x00000000) - WDCR_SDRAM(mem_mb3cf, 0x00000000) - - /* - * Set up SDTR1 (SDRAM Timing Register) - */ - WDCR_SDRAM(mem_sdtr1, 0x00854009) - - /* - * Set RTR (Refresh Timing Register) - */ - WDCR_SDRAM(mem_rtr, 0x10000000) - /* WDCR_SDRAM(mem_rtr, 0x05f00000) */ - - /******************************************************************** - * Delay to ensure 200usec have elapsed since reset. Assume worst - * case that the core is running 200Mhz: - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *******************************************************************/ - addis r3, 0, 0x0000 - ori r3, r3, 0xA000 /* Wait >200us from reset */ - mtctr r3 -..spinlp2: - bdnz ..spinlp2 /* spin loop */ - - /******************************************************************** - * Set memory controller options reg, MCOPT1. - *******************************************************************/ - WDCR_SDRAM(mem_mcopt1,0x80800000) - -..sdri_done: - blr /* Return to calling function */ -.Lfe1: .size sdram_init,.Lfe1-sdram_init -/* end sdram_init() */ diff --git a/board/csb272/u-boot.lds b/board/csb272/u-boot.lds deleted file mode 100644 index d75d6d1..0000000 --- a/board/csb272/u-boot.lds +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/csb272/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - - lib_ppc/extable.o (.text) - lib_ppc/board.o (.text) - lib_generic/zlib.o (.text) -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/csb472/Makefile b/board/csb472/Makefile deleted file mode 100644 index 926e065..0000000 --- a/board/csb472/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -#OBJS = $(BOARD).o flash.o -#OBJS = $(BOARD).o strataflash.o -OBJS = $(BOARD).o - -SOBJS = init.o - - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/csb472/config.mk b/board/csb472/config.mk deleted file mode 100644 index 04aefd1..0000000 --- a/board/csb472/config.mk +++ /dev/null @@ -1,36 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004 -# Tolunay Orkun, NextIO Inc., torkun@nextio.com. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Cogent CSB472 board -# - -LDFLAGS += $(LINKER_UNDEFS) - -TEXT_BASE := 0xFFFC0000 -#TEXT_BASE := 0x00100000 - -PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS) diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c deleted file mode 100644 index 833bbce..0000000 --- a/board/csb472/csb472.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -/* - * board_early_init_f: do early board initialization - * - */ -int board_early_init_f(void) -{ - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - - mtebc (epcr, 0xa8400000); /* EBC always driven */ - - return 0; /* success */ -} - -/* - * checkboard: identify/verify the board we are running - * - * Remark: we just assume it is correct board here! - * - */ -int checkboard(void) -{ - printf("BOARD: Cogent CSB472\n"); - - return 0; /* success */ -} - -/* - * initram: Determine the size of mounted DRAM - * - * Size is determined by reading SDRAM configuration registers as - * configured by initialization code - * - */ -long initdram (int board_type) -{ - ulong tot_size; - ulong bank_size; - ulong tmp; - - tot_size = 0; - - mtdcr (memcfga, mem_mb0cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (memcfga, mem_mb1cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (memcfga, mem_mb2cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (memcfga, mem_mb3cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - return tot_size; -} - -/* - * last_stage_init: final configurations (such as PHY etc) - * - */ -int last_stage_init(void) -{ - /* initialize the PHY */ - miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); - - /* AUTO neg */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - - /* LEDs */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); - - return 0; /* success */ -} diff --git a/board/csb472/init.S b/board/csb472/init.S deleted file mode 100644 index aec42a1..0000000 --- a/board/csb472/init.S +++ /dev/null @@ -1,212 +0,0 @@ -/****************************************************************************** - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - *****************************************************************************/ -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#define LI32(reg,val) \ - addis reg,0,val@h;\ - ori reg,reg,val@l - -#define WDCR_EBC(reg,val) \ - addi r4,0,reg;\ - mtdcr ebccfga,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr ebccfgd,r4 - -#define WDCR_SDRAM(reg,val) \ - addi r4,0,reg;\ - mtdcr memcfga,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr memcfgd,r4 - -/****************************************************************************** - * Function: ext_bus_cntlr_init - * - * Description: Configures EBC Controller and a few basic chip selects. - * - * CS0 is setup to get the Boot Flash out of the addresss range - * so that we may setup a stack. CS7 is setup so that we can - * access and reset the hardware watchdog. - * - * IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl ext_bus_cntlr_init - .type ext_bus_cntlr_init, @function -ext_bus_cntlr_init: - mflr r0 - /******************************************************************** - * Prefetch entire ext_bus_cntrl_init function into the icache. - * This is necessary because we are going to change the same CS we - * are executing from. Otherwise a CPU lockup may occur. - *******************************************************************/ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - - /* Calculate number of cache lines for this function */ - addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2) - mtctr r4 -..ebcloop: - icbt r0, r3 /* prefetch cache line for addr in r3*/ - addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */ - bdnz ..ebcloop /* continue for $CTR cache lines */ - - /******************************************************************** - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. - *******************************************************************/ - addis r3, 0, 0x0 - ori r3, r3, 0xA000 /* wait 200us from reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /******************************************************************** - * SETUP CPC0_CR0 - *******************************************************************/ - LI32(r4, 0x00c01030) - mtdcr cntrl0, r4 - - /******************************************************************** - * Setup CPC0_CR1: Change PCIINT signal to PerWE - *******************************************************************/ - mfdcr r4, cntrl1 - ori r4, r4, 0x4000 - mtdcr cntrl1, r4 - - /******************************************************************** - * Setup External Bus Controller (EBC). - *******************************************************************/ - WDCR_EBC(epcr, 0xd84c0000) - /******************************************************************** - * Memory Bank 0 (Intel 28F640J3 Flash) initialization - *******************************************************************/ - /*WDCR_EBC(pb0ap, 0x03055200)*/ - /*WDCR_EBC(pb0ap, 0x04055200)*/ - WDCR_EBC(pb0ap, 0x08055200) - WDCR_EBC(pb0cr, 0xff87a000) - /******************************************************************** - * Memory Bank 3 (Xilinx XC95144 CPLD) initialization - *******************************************************************/ - /*WDCR_EBC(pb3ap, 0x07869200)*/ - WDCR_EBC(pb3ap, 0x04055200) - WDCR_EBC(pb3cr, 0xf081c000) - /******************************************************************** - * Memory Bank 1,2,4-7 (Unused) initialization - *******************************************************************/ - WDCR_EBC(pb1ap, 0) - WDCR_EBC(pb1cr, 0) - WDCR_EBC(pb2ap, 0) - WDCR_EBC(pb2cr, 0) - WDCR_EBC(pb4ap, 0) - WDCR_EBC(pb4cr, 0) - WDCR_EBC(pb5ap, 0) - WDCR_EBC(pb5cr, 0) - WDCR_EBC(pb6ap, 0) - WDCR_EBC(pb6cr, 0) - WDCR_EBC(pb7ap, 0) - WDCR_EBC(pb7cr, 0) - - /* We are all done */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ -.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init -/* end ext_bus_cntlr_init() */ - -/****************************************************************************** - * Function: sdram_init - * - * Description: Configures SDRAM memory banks. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl sdram_init - .type sdram_init, @function -sdram_init: - - /* - * Disable memory controller to allow - * values to be changed. - */ - WDCR_SDRAM(mem_mcopt1, 0x00000000) - - /* - * Configure Memory Banks - */ - WDCR_SDRAM(mem_mb0cf, 0x00062001) - WDCR_SDRAM(mem_mb1cf, 0x00000000) - WDCR_SDRAM(mem_mb2cf, 0x00000000) - WDCR_SDRAM(mem_mb3cf, 0x00000000) - - /* - * Set up SDTR1 (SDRAM Timing Register) - */ - WDCR_SDRAM(mem_sdtr1, 0x00854009) - - /* - * Set RTR (Refresh Timing Register) - */ - WDCR_SDRAM(mem_rtr, 0x10000000) - /* WDCR_SDRAM(mem_rtr, 0x05f00000) */ - - /******************************************************************** - * Delay to ensure 200usec have elapsed since reset. Assume worst - * case that the core is running 200Mhz: - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *******************************************************************/ - addis r3, 0, 0x0000 - ori r3, r3, 0xA000 /* Wait >200us from reset */ - mtctr r3 -..spinlp2: - bdnz ..spinlp2 /* spin loop */ - - /******************************************************************** - * Set memory controller options reg, MCOPT1. - *******************************************************************/ - WDCR_SDRAM(mem_mcopt1,0x80800000) - -..sdri_done: - blr /* Return to calling function */ -.Lfe1: .size sdram_init,.Lfe1-sdram_init -/* end sdram_init() */ diff --git a/board/csb472/u-boot.lds b/board/csb472/u-boot.lds deleted file mode 100644 index 14ac3fb..0000000 --- a/board/csb472/u-boot.lds +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/csb472/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - - lib_ppc/extable.o (.text) - lib_ppc/board.o (.text) - lib_generic/zlib.o (.text) -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/csb637/Makefile b/board/csb637/Makefile deleted file mode 100644 index 61d5a35..0000000 --- a/board/csb637/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := csb637.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/csb637/config.mk b/board/csb637/config.mk deleted file mode 100644 index 4c6f631..0000000 --- a/board/csb637/config.mk +++ /dev/null @@ -1 +0,0 @@ -TEXT_BASE = 0x23fc0000 diff --git a/board/csb637/csb637.c b/board/csb637/csb637.c deleted file mode 100644 index 6100a53..0000000 --- a/board/csb637/csb637.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2005 REA Elektronik GmbH - * Anders Larsen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Enable Ctrlc */ - console_init_f (); - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of CSB637-Board */ - gd->bd->bi_arch_number = MACH_TYPE_CSB637; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = bcm5221_InitPhy; - p_phyops->IsPhyConnected = bcm5221_IsPhyConnected; - p_phyops->GetLinkSpeed = bcm5221_GetLinkSpeed; - p_phyops->AutoNegotiate = bcm5221_AutoNegotiate; -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/csb637/u-boot.lds b/board/csb637/u-boot.lds deleted file mode 100644 index 76df6b2..0000000 --- a/board/csb637/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/cu824/Makefile b/board/cu824/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/cu824/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/cu824/README b/board/cu824/README deleted file mode 100644 index cc0d207..0000000 --- a/board/cu824/README +++ /dev/null @@ -1,453 +0,0 @@ -ppcboot for a CU824 board ---------------------------- - -CU824 has two banks of flash 8MB each. In board's notation, bank 0 is -the one at the address of 0xFF800000 and bank 1 is the one at the -address of 0xFF000000. On power-up the processor jumps to the address -of 0xFFF00100, the last megabyte of the bank 0 of flash. Thus, -U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is not embedded in the U-Boot code -and is located in flash separately from U-Boot, at the address of -0xFF008000. - - -U-Boot test results --------------------- - -x.x Operation on all available serial consoles - -x.x.x CONFIG_CONS_INDEX 1 - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=>he -go - start application at address 'addr' -run - run commands in an environment variable -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -rarpboot- boot image via network using RARP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -loads - load S-Record file over serial line -loadb - load binary file over serial line (kermit mode) -md - memory display -mm - memory modify (auto-incrementing) -nm - memory modify (constant address) -mw - memory write (fill) -cp - memory copy -cmp - memory compare -crc32 - checksum calculation -base - print or set address offset -printenv- print environment variables -setenv - set environment variables -saveenv - save environment variables to persistent storage -protect - enable or disable FLASH write protection -erase - erase FLASH memory -flinfo - print FLASH memory information -bdinfo - print Board Info structure -iminfo - print header information for application image -coninfo - print console devices and informations -loop - infinite loop on address range -mtest - simple RAM test -icache - enable or disable instruction cache -dcache - enable or disable data cache -reset - Perform RESET of the CPU -echo - echo args to console -version - print monitor version -help - print online help -? - alias for 'help' -=> - - -x.x.x CONFIG_CONS_INDEX 2 - -**** NOT TESTED **** - -x.x Flash Driver Operation - -x.x.x Erase Operation - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=> -=>md ff000000 -ff000000: 27051956 70706362 6f6f7420 302e382e '..Vppcboot 0.8. -ff000010: 3320284d 61792031 31203230 3031202d 3 (May 11 2001 - -ff000020: 2031343a 35373a30 33290000 00000000 14:57:03)...... -ff000030: 00000000 00000000 00000000 00000000 ................ -ff000040: 00000000 00000000 00000000 00000000 ................ -ff000050: 00000000 00000000 00000000 00000000 ................ -ff000060: 00000000 00000000 00000000 00000000 ................ -ff000070: 00000000 00000000 00000000 00000000 ................ -ff000080: 00000000 00000000 00000000 00000000 ................ -ff000090: 00000000 00000000 00000000 00000000 ................ -ff0000a0: 00000000 00000000 00000000 00000000 ................ -ff0000b0: 00000000 00000000 00000000 00000000 ................ -ff0000c0: 00000000 00000000 00000000 00000000 ................ -ff0000d0: 00000000 00000000 00000000 00000000 ................ -ff0000e0: 00000000 00000000 00000000 00000000 ................ -ff0000f0: 00000000 00000000 00000000 00000000 ................ -=>erase ff000000 ff007fff -Erase Flash from 0xff000000 to 0xff007fff - done -Erased 1 sectors -=>md ff000000 -ff000000: ffffffff ffffffff ffffffff ffffffff ................ -ff000010: ffffffff ffffffff ffffffff ffffffff ................ -ff000020: ffffffff ffffffff ffffffff ffffffff ................ -ff000030: ffffffff ffffffff ffffffff ffffffff ................ -ff000040: ffffffff ffffffff ffffffff ffffffff ................ -ff000050: ffffffff ffffffff ffffffff ffffffff ................ -ff000060: ffffffff ffffffff ffffffff ffffffff ................ -ff000070: ffffffff ffffffff ffffffff ffffffff ................ -ff000080: ffffffff ffffffff ffffffff ffffffff ................ -ff000090: ffffffff ffffffff ffffffff ffffffff ................ -ff0000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000f0: ffffffff ffffffff ffffffff ffffffff ................ -=> - -x.x.x Information - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=> -=> -=>flinfo - -Bank # 1: Intel: 28F160F3B (16Mbit) - Size: 8 MB in 39 Sectors - Sector Start Addresses: - FF000000 FF008000 (RO) FF010000 FF018000 FF020000 - FF028000 FF030000 FF038000 FF040000 FF080000 - FF0C0000 FF100000 FF140000 FF180000 FF1C0000 - FF200000 FF240000 FF280000 FF2C0000 FF300000 - FF340000 FF380000 FF3C0000 FF400000 FF440000 - FF480000 FF4C0000 FF500000 FF540000 FF580000 - FF5C0000 FF600000 FF640000 FF680000 FF6C0000 - FF700000 FF740000 FF780000 FF7C0000 - -Bank # 2: Intel: 28F160F3B (16Mbit) - Size: 8 MB in 39 Sectors - Sector Start Addresses: - FF800000 FF808000 FF810000 FF818000 FF820000 - FF828000 FF830000 FF838000 FF840000 FF880000 - FF8C0000 FF900000 FF940000 FF980000 FF9C0000 - FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000 - FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000 - FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000 - FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000 - FFF00000 (RO) FFF40000 FFF80000 FFFC0000 -=> - -x.x.x Flash Programming - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=> -=> -=>cp 0 ff000000 20 -Copy to Flash... done -=>md 0 -00000000: 0ec08ce0 03f9800c 00000001 040c0000 ................ -00000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................ -00000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4. -00000030: 03fcd5bc 03fcdabc 00000000 00000000 ................ -00000040: 00000000 00000000 00000000 00000000 ................ -00000050: 00000000 00000000 00000000 00000000 ................ -00000060: 00000000 00000000 00000000 00000000 ................ -00000070: 00000000 00000000 00000000 00000000 ................ -00000080: 00000000 00000000 00000000 00000000 ................ -00000090: 00000000 00000000 00000000 00000000 ................ -000000a0: 00000000 00000000 00000000 00000000 ................ -000000b0: 00000000 00000000 00000000 00000000 ................ -000000c0: 00000000 00000000 00000000 00000000 ................ -000000d0: 00000000 00000000 00000000 00000000 ................ -000000e0: 00000000 00000000 00000000 00000000 ................ -000000f0: 00000000 00000000 00000000 00000000 ................ -=>md ff000000 -ff000000: 0ec08ce0 03f9800c 00000001 040c0000 ................ -ff000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00 ................ -ff000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0 ...X......4...4. -ff000030: 03fcd5bc 03fcdabc 00000000 00000000 ................ -ff000040: 00000000 00000000 00000000 00000000 ................ -ff000050: 00000000 00000000 00000000 00000000 ................ -ff000060: 00000000 00000000 00000000 00000000 ................ -ff000070: 00000000 00000000 00000000 00000000 ................ -ff000080: ffffffff ffffffff ffffffff ffffffff ................ -ff000090: ffffffff ffffffff ffffffff ffffffff ................ -ff0000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff0000f0: ffffffff ffffffff ffffffff ffffffff ................ -=> - -x.x.x Storage of environment variables in flash - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=>printenv -bootargs= -bootcmd=bootm FE020000 -bootdelay=5 -baudrate=9600 -ipaddr=192.168.4.2 -serverip=192.168.4.1 -ethaddr=00:40:42:01:00:a0 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 167/32764 bytes -=>setenv myvar 1234 -=>save_env -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Saving Environment to Flash... -Protected 1 sectors -=>reset - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=>printenv -bootargs= -bootcmd=bootm FE020000 -bootdelay=5 -baudrate=9600 -ipaddr=192.168.4.2 -serverip=192.168.4.1 -ethaddr=00:40:42:01:00:a0 -myvar=1234 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 178/32764 bytes -=> - -x.x Image Download and run over serial port - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=>mw 40000 0 10000 -=>md 40000 -00040000: 00000000 00000000 00000000 00000000 ................ -00040010: 00000000 00000000 00000000 00000000 ................ -00040020: 00000000 00000000 00000000 00000000 ................ -00040030: 00000000 00000000 00000000 00000000 ................ -00040040: 00000000 00000000 00000000 00000000 ................ -00040050: 00000000 00000000 00000000 00000000 ................ -00040060: 00000000 00000000 00000000 00000000 ................ -00040070: 00000000 00000000 00000000 00000000 ................ -00040080: 00000000 00000000 00000000 00000000 ................ -00040090: 00000000 00000000 00000000 00000000 ................ -000400a0: 00000000 00000000 00000000 00000000 ................ -000400b0: 00000000 00000000 00000000 00000000 ................ -000400c0: 00000000 00000000 00000000 00000000 ................ -000400d0: 00000000 00000000 00000000 00000000 ................ -000400e0: 00000000 00000000 00000000 00000000 ................ -000400f0: 00000000 00000000 00000000 00000000 ................ -=>loads -## Ready for S-Record download ... - -(Back at xpert.denx.de) -[vlad@xpert vlad]$ cat hello_world.srec >/dev/ttyS0 -[vlad@xpert vlad]$ kermit -l /dev/ttyS0 -b 9600 -c -Connecting to /dev/ttyS0, speed 9600. -The escape character is Ctrl-\ (ASCII 28, FS) -Type the escape character followed by C to get back, -or followed by ? to see other options. -md 40000 -00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378 ....|..x.?.8|.#x -00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00040040: 7c0803a6 4e800021 813f0038 7f84e378 |...N..!.?.8...x -00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! -00040060: 7c1be000 4181003c 80bd0000 813f0038 |...A..<.....?.8 -00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... -00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. -00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... -000400a0: 813f0038 807e8010 80090010 7c0803a6 .?.8.~......|... -000400b0: 4e800021 813f0038 80090004 7c0803a6 N..!.?.8....|... -000400c0: 4e800021 2c030000 4182ffec 813f0038 N..!,...A....?.8 -000400d0: 80090000 7c0803a6 4e800021 813f0038 ....|...N..!.?.8 -000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! -000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. -=>go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "" -Hit any key to exit ... - -## Application terminated, rc = 0x0 -=> - -x.x Image download and run over ethernet interface - - -ppcboot 0.9.2 (May 13 2001 - 17:56:46) - -Initializing... - CPU: MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache - Board: CU824 Revision 1 Local Bus at 99 MHz - DRAM: 64 MB - FLASH: 16 MB - In: serial - Out: serial - Err: serial - -Hit any key to stop autoboot: 0 -=> -=> -=>mw 40000 0 10000 -=>md 40000 -00040000: 00000000 00000000 00000000 00000000 ................ -00040010: 00000000 00000000 00000000 00000000 ................ -00040020: 00000000 00000000 00000000 00000000 ................ -00040030: 00000000 00000000 00000000 00000000 ................ -00040040: 00000000 00000000 00000000 00000000 ................ -00040050: 00000000 00000000 00000000 00000000 ................ -00040060: 00000000 00000000 00000000 00000000 ................ -00040070: 00000000 00000000 00000000 00000000 ................ -00040080: 00000000 00000000 00000000 00000000 ................ -00040090: 00000000 00000000 00000000 00000000 ................ -000400a0: 00000000 00000000 00000000 00000000 ................ -000400b0: 00000000 00000000 00000000 00000000 ................ -000400c0: 00000000 00000000 00000000 00000000 ................ -000400d0: 00000000 00000000 00000000 00000000 ................ -000400e0: 00000000 00000000 00000000 00000000 ................ -000400f0: 00000000 00000000 00000000 00000000 ................ -=>tftpboot 40000 hello_world.bin -ARP broadcast 1 -TFTP from server 192.168.4.1; our IP address is 192.168.4.2 -Filename 'hello_world.bin'. -Load address: 0x40000 -Loading: ############# -done -Bytes transferred = 65912 (10178 hex) -=>md 40000 -00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378 ....|..x.?.8|.#x -00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00040040: 7c0803a6 4e800021 813f0038 7f84e378 |...N..!.?.8...x -00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! -00040060: 7c1be000 4181003c 80bd0000 813f0038 |...A..<.....?.8 -00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... -00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. -00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... -000400a0: 813f0038 807e8010 80090010 7c0803a6 .?.8.~......|... -000400b0: 4e800021 813f0038 80090004 7c0803a6 N..!.?.8....|... -000400c0: 4e800021 2c030000 4182ffec 813f0038 N..!,...A....?.8 -000400d0: 80090000 7c0803a6 4e800021 813f0038 ....|...N..!.?.8 -000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! -000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. -=>go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "" -Hit any key to exit ... - -## Application terminated, rc = 0x0 -=> diff --git a/board/cu824/config.mk b/board/cu824/config.mk deleted file mode 100644 index 18673e1..0000000 --- a/board/cu824/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# CU824 board -# - -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c deleted file mode 100644 index 5844a5c..0000000 --- a/board/cu824/cu824.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, - - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define BOARD_REV_REG 0xFE80002B - -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - char revision = *(volatile char *)(BOARD_REV_REG); - char buf[32]; - - puts ("Board: CU824 "); - printf("Revision %d ", revision); - printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk)); - - return 0; -} - -long int initdram(int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} diff --git a/board/cu824/flash.c b/board/cu824/flash.c deleted file mode 100644 index 7368176..0000000 --- a/board/cu824/flash.c +++ /dev/null @@ -1,486 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -#define FLASH_BANK_SIZE 0x800000 -#define MAIN_SECT_SIZE 0x40000 -#define PARAM_SECT_SIZE 0x8000 - -#define BOARD_CTRL_REG 0xFE800013 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -static int write_data (flash_info_t *info, ulong dest, ulong *data); -static void write_via_fpu(vu_long *addr, ulong *data); -static __inline__ unsigned long get_msr(void); -static __inline__ void set_msr(unsigned long msr); - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -/*---------------------------------------------------------------------*/ -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - int i, j; - ulong size = 0; - volatile unsigned char *bcr = (volatile unsigned char *)(BOARD_CTRL_REG); - - DEBUGF("Write protect was: 0x%02X\n", *bcr); - *bcr &= 0x1; /* FWPT must be 0 */ - *bcr |= 0x6; /* FWP0 = FWP1 = 1 */ - DEBUGF("Write protect is: 0x%02X\n", *bcr); - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE); - - addr[0] = 0x00900090; - - DEBUGF ("Flash bank # %d:\n" - "\tManuf. ID @ 0x%08lX: 0x%08lX\n" - "\tDevice ID @ 0x%08lX: 0x%08lX\n", - i, - (ulong)(&addr[0]), addr[0], - (ulong)(&addr[2]), addr[2]); - - if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) && - (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3B)) - { - flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) | - (INTEL_ID_28F160F3B & FLASH_TYPEMASK); - } else { - flash_info[i].flash_id = FLASH_UNKNOWN; - addr[0] = 0xFFFFFFFF; - goto Done; - } - - DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); - - addr[0] = 0xFFFFFFFF; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 7) { - flash_info[i].start[j] = CFG_FLASH_BASE + - i * FLASH_BANK_SIZE + - j * PARAM_SECT_SIZE; - } else { - flash_info[i].start[j] = CFG_FLASH_BASE + - i * FLASH_BANK_SIZE + - (j - 7)*MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[1]); -#else - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[1]); -#else - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif -#endif - -Done: - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch ((i = info->flash_id & FLASH_VENDMASK)) { - case (FLASH_MAN_INTEL & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor 0x%04x ", i); - break; - } - - switch ((i = info->flash_id & FLASH_TYPEMASK)) { - case (INTEL_ID_28F160F3B & FLASH_TYPEMASK): - printf ("28F160F3B (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type 0x%04x\n", i); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - DEBUGF ("Erase flash bank %d sect %d ... %d\n", - info - &flash_info[0], s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (FLASH_MAN_INTEL & FLASH_VENDMASK)) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - DEBUGF ("Erase sect %d @ 0x%08lX\n", - sect, (ulong)addr); - - /* Disable interrupts which might cause a timeout - * here. - */ - flag = disable_interrupts(); - - addr[0] = 0x00500050; /* clear status register */ - addr[0] = 0x00200020; /* erase setup */ - addr[0] = 0x00D000D0; /* erase confirm */ - - addr[1] = 0x00500050; /* clear status register */ - addr[1] = 0x00200020; /* erase setup */ - addr[1] = 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080) ) { - if ((now=get_timer(start)) > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - addr[0] = 0x00B000B0; /* suspend erase */ - addr[0] = 0x00FF00FF; /* to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - addr[0] = 0x00FF00FF; - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 8 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp, cp, msr; - int l, rc, i; - ulong data[2]; - ulong *datah = &data[0]; - ulong *datal = &data[1]; - - DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", - addr, (ulong)src, cnt); - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - msr = get_msr(); - set_msr(msr | MSR_FP); - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - *datah = *datal = 0; - - for (i = 0, cp = wp; i < l; i++, cp++) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | (*(uchar *)cp); - } - for (; i < FLASH_WIDTH && cnt > 0; ++i) { - char tmp; - - tmp = *src; - - src++; - - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | tmp; - - --cnt; ++cp; - } - - for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | - ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datah << 8) | (*(uchar *)cp); - } - - if ((rc = write_data(info, wp, data)) != 0) { - set_msr(msr); - return (rc); - } - - wp += FLASH_WIDTH; - } - - /* - * handle FLASH_WIDTH aligned part - */ - while (cnt >= FLASH_WIDTH) { - *datah = *(ulong *)src; - *datal = *(ulong *)(src + 4); - if ((rc = write_data(info, wp, data)) != 0) { - set_msr(msr); - return (rc); - } - wp += FLASH_WIDTH; - cnt -= FLASH_WIDTH; - src += FLASH_WIDTH; - } - - if (cnt == 0) { - set_msr(msr); - return (0); - } - - /* - * handle unaligned tail bytes - */ - *datah = *datal = 0; - for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { - char tmp; - - tmp = *src; - - src++; - - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | tmp; - - --cnt; - } - - for (; i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | (*(uchar *)cp); - } - - rc = write_data(info, wp, data); - set_msr(msr); - - return (rc); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, ulong *data) -{ - vu_long *addr = (vu_long *)dest; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if (((addr[0] & data[0]) != data[0]) || - ((addr[1] & data[1]) != data[1]) ) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0] = 0x00400040; /* write setup */ - write_via_fpu(addr, data); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080) ) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - addr[0] = 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - addr[0] = 0x00FF00FF; /* restore read mode */ - - return (0); -} - -/*----------------------------------------------------------------------- - */ -static void write_via_fpu(vu_long *addr, ulong *data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr)); -} -/*----------------------------------------------------------------------- - */ -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - - __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); -} diff --git a/board/cu824/u-boot.lds b/board/cu824/u-boot.lds deleted file mode 100644 index 7be85e4..0000000 --- a/board/cu824/u-boot.lds +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/dave/B2/B2.c b/board/dave/B2/B2.c deleted file mode 100644 index 29676b8..0000000 --- a/board/dave/B2/B2.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* - * Miscelaneous platform dependent initialization - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - u32 temp; - - /* Configuration Port Control Register*/ - /* Port A */ - PCONA = 0x3ff; - - /* Port B */ - PCONB = 0xff; - PDATB = 0xFFFF; - - /* Port C */ - /* - PCONC = 0xff55ff15; - PDATC = 0x0; - PUPC = 0xffff; - */ - - /* Port D */ - /* - PCOND = 0xaaaa; - PUPD = 0xff; - */ - - /* Port E */ - PCONE = 0x0001aaa9; - PDATE = 0x0; - PUPE = 0xff; - - /* Port F */ - PCONF = 0x124955; - PDATF = 0xff; /* B2-eth_reset tied high level */ - /* - PUPF = 0x1e3; - */ - - /* Port G */ - PUPG = 0x1; - PCONG = 0x3; /*PG0= EINT0= ETH_INT prepared for linux kernel*/ - - INTMSK = 0x03fffeff; - INTCON = 0x05; - - /* - Configure chip ethernet interrupt as High level - Port G EINT 0-7 EINT0 -> CHIP ETHERNET - */ - temp = EXTINT; - temp &= ~0x7; - temp |= 0x1; /*LEVEL_HIGH*/ - EXTINT = temp; - - /* - Reset SMSC LAN91C96 chip - */ - temp= PCONF; - temp |= 0x00000040; - PCONF = temp; - - /* Reset high */ - temp = PDATF; - temp |= (1 << 3); - PDATF = temp; - - /* Short delay */ - for (temp=0;temp<10;temp++) - { - /* NOP */ - } - - /* Reset low */ - temp = PDATF; - temp &= ~(1 << 3); - PDATF = temp; - - /* arch number MACH_TYPE_MBA44B0 */ - gd->bd->bi_arch_number = MACH_TYPE_S3C44B0; - - /* location of boot parameters */ - gd->bd->bi_boot_params = 0x0c000100; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} diff --git a/board/dave/B2/Makefile b/board/dave/B2/Makefile deleted file mode 100644 index 548fd52..0000000 --- a/board/dave/B2/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := B2.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/dave/B2/config.mk b/board/dave/B2/config.mk deleted file mode 100644 index 5216622..0000000 --- a/board/dave/B2/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x0C100000 - -PLATFORM_CPPFLAGS += -Uarm diff --git a/board/dave/B2/flash.c b/board/dave/B2/flash.c deleted file mode 100644 index ad67e86..0000000 --- a/board/dave/B2/flash.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -#ifdef __DEBUG_START_FROM_SRAM__ - return CFG_DUMMY_FLASH_SIZE; -#else - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i $@ - -sinclude .depend - -######################################################################### diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c deleted file mode 100644 index 5f2c705..0000000 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ /dev/null @@ -1,302 +0,0 @@ -/* - * (C) Copyright 2003 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - -int board_early_init_f (void) -{ - out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */ - out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) - * IRQ 26 (EXT IRQ 1) - * IRQ 27 (EXT IRQ 2) - * IRQ 28 (EXT IRQ 3) - * IRQ 29 (EXT IRQ 4) - * IRQ 30 (EXT IRQ 5) - * IRQ 31 (EXT IRQ 6) - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ -#if 1 /* test-only */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ -#else - mtebc (epcr, 0x28400000); /* ebc in high-z */ -#endif - return 0; -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* adjust flash start and size as well as the offset */ - gd->bd->bi_flashstart = 0 - flash_info[0].size; - gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN; -#if 0 - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - volatile unsigned char *duart0_mcr = - (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = - (unsigned char *)((ulong)DUART1_BA + 4); - - bd_t *bd = gd->bd; - char * tmp; /* Temporary char pointer */ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - unsigned long cntrl0Reg; - - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ -#endif - -#if 0 - /* - * Enable power on PS/2 interface - */ - *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET; - - /* - * Enable interrupts in exar duart mcr[3] - */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; -#endif - return (0); -} - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming PPChameleonEVB"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 /* test-only */ - for (;;) { - NAND_DISABLE_CE(1); - udelay(100); - NAND_ENABLE_CE(1); - udelay(100); - } -#endif -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - -void -nand_init(void) -{ - ulong totlen = 0; - -/* - The HI model is equipped with a large block NAND chip not supported yet - by U-Boot - (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -*/ - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) - debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); - totlen += nand_probe (CFG_NAND0_BASE); -#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */ - - debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE); - totlen += nand_probe (CFG_NAND1_BASE); - - printf ("%3lu MB\n", totlen >>20); -} -#endif - -#ifdef CONFIG_CFB_CONSOLE -# ifdef CONFIG_CONSOLE_EXTRA_INFO -# include -extern GraphicDevice smi; - -void video_get_info_str (int line_number, char *info) -{ - uint pvr = get_pvr (); - - /* init video info strings for graphic console */ - switch (line_number) { - case 1: - switch (pvr) { - case PVR_405EP_RB: - sprintf (info, " AMCC PowerPC 405EP Rev. B"); - break; - default: - sprintf (info, " AMCC PowerPC 405EP Rev. "); - break; - } - return; - case 2: - sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it"); - return; - case 3: - sprintf (info, " %s", smi.modeIdent); - return; - } - - /* no more info lines */ - *info = 0; - return; -} -# endif /* CONFIG_CONSOLE_EXTRA_INFO */ -#endif /* CONFIG_CFB_CONSOLE */ diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk deleted file mode 100644 index 5856aec..0000000 --- a/board/dave/PPChameleonEVB/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# Reserve 256 kB for Monitor -TEXT_BASE = 0xFFFC0000 - -# Reserve 320 kB for Monitor -#TEXT_BASE = 0xFFFB0000 diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c deleted file mode 100644 index 692d275..0000000 --- a/board/dave/PPChameleonEVB/flash.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -#ifdef __DEBUG_START_FROM_SRAM__ - return CFG_DUMMY_FLASH_SIZE; -#else - unsigned long size; - int i; - uint pbcr; - unsigned long base; - int size_val = 0; - - debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__); - debug("[%s, %d] flash_info = 0x%08X ...\n", __FUNCTION__, __LINE__, flash_info); - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); - . = 0xFFFF8000; - .ppcenv : - { - common/environment.o(.ppcenv); - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/dave/common/flash.c b/board/dave/common/flash.c deleted file mode 100644 index bf0f2bf..0000000 --- a/board/dave/common/flash.c +++ /dev/null @@ -1,706 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - short n; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (i < info->sector_count) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("ST "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_STMW320DT: printf ("M29W320DT (32 M, top sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - short n; - CFG_FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; - - debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__); - - /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; - - value = addr2[CFG_FLASH_READ0]; - - switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[CFG_FLASH_READ1]; /* device ID */ - - switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000; break; /* => 8 MB */ - - case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (i < info->sector_count) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - /* 1 x 16k boot sector */ - base -= 16 << 10; - --i; - info->start[i] = base; - /* 2 x 8k boot sectors */ - for (n=0; n<2; ++n) { - base -= 8 << 10; - --i; - info->start[i] = base; - } - /* 1 x 32k boot sector */ - base -= 32 << 10; - --i; - info->start[i] = base; - - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[CFG_FLASH_READ2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - ulong start, now, last; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - if (sect == s_first) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - } - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { -#ifdef CONFIG_B2 - data = data | ((*src++)<<(8*i)); -#else - data = (data << 8) | *src++; -#endif - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { -#ifdef CONFIG_B2 - data = data | ((*(uchar *)cp)<<(8*i)); -#else - data = (data << 8) | (*(uchar *)cp); -#endif - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; -#ifdef CONFIG_B2 - data = (*(ulong*)src); - src += 4; -#else - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } -#endif - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { -#ifdef CONFIG_B2 - data = data | ((*src++)<<(8*i)); -#else - data = (data << 8) | *src++; -#endif - --cnt; - } - for (; i<4; ++i, ++cp) { -#ifdef CONFIG_B2 - data = data | ((*(uchar *)cp)<<(8*i)); -#else - data = (data << 8) | (*(uchar *)cp); -#endif - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile ulong *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) - { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/dave/common/fpga.c b/board/dave/common/fpga.c deleted file mode 100644 index 5b5b5e9..0000000 --- a/board/dave/common/fpga.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#ifdef FPGA_DEBUG -#define DBG(x...) printf(x) -#else -#define DBG(x...) -#endif /* DEBUG */ - -#define MAX_ONES 226 - -#ifdef CFG_FPGA_PRG -# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/ -# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */ -# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */ -# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */ -# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */ -#else -# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ -# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#endif - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ - -#define SET_FPGA(data) out32(GPIO0_OR, data) - -#define FPGA_WRITE_1 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG); /* set data to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#if 0 -static int fpga_boot (unsigned char *fpgadata, int size) -{ - int i, index, len; - int count; - -#ifdef CFG_FPGA_SPARTAN2 - int j; -#else - unsigned char b; - int bit; -#endif - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - DBG ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - -#ifdef CFG_FPGA_SPARTAN2 - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) - && (fpgadata[index + 2] == 0xff) - && (fpgadata[index + 3] == 0xff)) - break; /* preamble found */ - else - index++; - } -#else - /* search for preamble 0xFF2X */ - for (index = 0; index < size - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x30)) - break; - } - index += 2; -#endif - - DBG ("FPGA: configdata starts at position 0x%x\n", index); - DBG ("FPGA: length of fpga-data %d\n", size - index); - - /* - * Setup port pins for fpga programming - */ - out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */ - out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */ - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA (FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA init line low */ - count = 0; - while (in32 (GPIO0_IR) & FPGA_INIT) { - udelay (1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* deassert PROGRAM* */ - SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(in32 (GPIO0_IR) & FPGA_INIT)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - DBG ("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - -#ifdef CFG_FPGA_SPARTAN2 - /* - * Load uncompressed image into fpga - */ - for (i = index; i < size; i++) { - for (j = 0; j < 8; j++) { - if ((fpgadata[i] & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - fpgadata[i] <<= 1; - } - } -#else /* ! CFG_FPGA_SPARTAN2 */ - /* send 0xff 0x20 */ - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - - /* - ** Bit_DeCompression - ** Code 1 .. maxOnes : n '1's followed by '0' - ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' - ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' - ** 255 : '1' - */ - - for (i = index; i < size; i++) { - b = fpgadata[i]; - if ((b >= 1) && (b <= MAX_ONES)) { - for (bit = 0; bit < b; bit++) { - FPGA_WRITE_1; - } - FPGA_WRITE_0; - } else if (b == (MAX_ONES + 1)) { - for (bit = 1; bit < b; bit++) { - FPGA_WRITE_1; - } - } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { - for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { - FPGA_WRITE_0; - } - FPGA_WRITE_1; - } else if (b == 255) { - FPGA_WRITE_1; - } - } -#endif /* CFG_FPGA_SPARTAN2 */ - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Check if fpga's DONE signal - correctly booted ? - */ - - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(in32 (GPIO0_IR) & FPGA_DONE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - DBG ("FPGA: Booting successful!\n"); - return 0; -} -#endif /* 0 */ diff --git a/board/dave/common/pci.c b/board/dave/common/pci.c deleted file mode 100644 index f8f180c..0000000 --- a/board/dave/common/pci.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - - -u_long pci9054_iobase; - - -#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ -#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ - - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_read_config_dword -| Description: Read a PCI configuration register -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| value Address of the configuration register value -| Return value: -| 0 Successful -+-----------------------------------------------------------------------------*/ -int pci9054_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32* value) -{ - unsigned long conAdrVal; - unsigned long val; - - /* generate coded value for CON_ADR register */ - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - /* Note: *pResult comes back as -1 if machine check happened */ - val = in32r(PCI_PRIMARY_CDR); - - *value = (unsigned long) val; - - out32r(PCI_PRIMARY_CAR, 0); - - if ((*(unsigned long *)0x50000304) & 0x60000000) - { - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - } - - return 0; -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_write_config_dword -| Description: Write a PCI configuration register. -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| Value Configuration register value -| Return value: -| 0 Successful -| Updated for pass2 errata #6. Need to disable interrupts and clear the -| PCICFGADR reg after writing the PCICFGDATA reg. -+-----------------------------------------------------------------------------*/ -int pci9054_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - unsigned long conAdrVal; - - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - out32r(PCI_PRIMARY_CDR, value); - - out32r(PCI_PRIMARY_CAR, 0); - - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - - return (0); -} - -/*----------------------------------------------------------------------- - */ - -#ifdef CONFIG_DASA_SIM -static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *_) -{ - unsigned int iobase; - unsigned short status = 0; - unsigned char timer; - - /* - * Configure PLX PCI9054 - */ - pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status); - status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status); - - /* Check the latency timer for values >= 0x60. - */ - pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); - if (timer < 0x60) - { - pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); - } - - /* Set I/O base register. - */ - pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE); - pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); - - pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); - - if (pci9054_iobase == 0xffffffff) - { - printf("Error: Can not set I/O base register.\n"); - return; - } -} -#endif - -static struct pci_config_table pci9054_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN), - pci_cfgfunc_config_device, { CFG_ETH_IOBASE, - CFG_ETH_IOBASE, - PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, -#ifdef CONFIG_DASA_SIM - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN), - pci_dasa_sim_config_pci9054 }, -#endif -#endif - { } -}; - -static struct pci_controller pci9054_hose = { - config_table: pci9054_config_table, -}; - -void pci_init(void) -{ - struct pci_controller *hose = &pci9054_hose; - - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - 0x00000000, 0x00000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI Memory space */ - pci_set_region(hose->regions + 1, - 0x00000000, 0xc0000000, 0x10000000, - PCI_REGION_MEM); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - pci9054_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - pci9054_write_config_dword); - - hose->region_count = 2; - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); -} diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile deleted file mode 100644 index d9b0e2d..0000000 --- a/board/dbau1x00/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o -SOBJS = lowlevel_init.o - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/dbau1x00/README b/board/dbau1x00/README deleted file mode 100644 index b37ff36..0000000 --- a/board/dbau1x00/README +++ /dev/null @@ -1,63 +0,0 @@ -By Thomas.Lange@corelatus.se 2004-Oct-05 ----------------------------------------- -DbAu1xx0 are development boards from AMD containing -an Alchemy AU1xx0 series cpu with mips32 core. -Existing cpu:s are Au1000, Au1100, Au1500 and Au1550 - -Limitations & comments ----------------------- -Support was originally big endian only. -I have not tested, but several u-boot users report working -configurations in little endian mode. - -I named the board dbau1x00, to allow -support for all three development boards -( dbau1000, dbau1100 and dbau1500 ). -Now there is a new board called dbau1550 also, which -should be supported RSN. - -I only have a dbau1000, so my testing is limited -to this board. - -The board has two different flash banks, that can -be selected via dip switch. This makes it possible -to test new bootloaders without thrashing the YAMON -boot loader delivered with board. - -NOTE! When you switch between the two boot flashes, the -base addresses will be swapped. -Have this in mind when you compile u-boot. TEXT_BASE has -to match the address where u-boot is located when you -actually launch. - -Ethernet only supported for mac0. - -PCMCIA only supported for slot 0, only 3.3V. - -PCMCIA IDE tested with Sandisk Compact Flash and -IBM microdrive. - -################################### -######## NOTE!!!!!! ######### -################################### -If you partition a disk on another system (e.g. laptop), -all bytes will be swapped on 16bit level when using -PCMCIA and running cpu in big endian mode!!!! - -This is probably due to an error in Au1000 chip. - -Solution: - -a) Boot via network and partition disk directly from -dbau1x00. The endian will then be correct. - -b) Partition disk on "laptop" and fill it with all files -you need. Then write a simple program that endian swaps -whole disk, - -Example: -Original "laptop" byte order: -B0 B1 B2 B3 B4 B5 B6 B7 B8 B9... - -Dbau1000 byte order will then be: -B1 B0 B3 B2 B5 B4 B7 B6 B9 B8... diff --git a/board/dbau1x00/config.mk b/board/dbau1x00/config.mk deleted file mode 100644 index 39eb60a..0000000 --- a/board/dbau1x00/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# AMD development board AMD Alchemy DbAu1x00, MIPS32 core -# - -# ROM version -TEXT_BASE = 0xbfc00000 - -# RAM version -#TEXT_BASE = 0x80100000 diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c deleted file mode 100644 index d29e8d5..0000000 --- a/board/dbau1x00/dbau1x00.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2003 - * Thomas.Lange@corelatus.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -long int initdram(int board_type) -{ - /* Sdram is setup by assembler code */ - /* If memory could be changed, we should return the true value here */ - return MEM_SIZE*1024*1024; -} - -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 - -/* In cpu/mips/cpu.c */ -void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); - -int checkboard (void) -{ -#ifdef CONFIG_IDE_PCMCIA - u16 status; - volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10); -#endif /* CONFIG_IDE_PCMCIA */ - volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC); - volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; - u32 proc_id; - - *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - - proc_id = read_32bit_cp0_register(CP0_PRID); - - switch (proc_id >> 24) { - case 0: - puts ("Board: Merlot (DbAu1000)\n"); - printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 1: - puts ("Board: DbAu1500\n"); - printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 2: - puts ("Board: DbAu1100\n"); - printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 3: - puts ("Board: DbAu1550\n"); - printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - default: - printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); - } -#ifdef CONFIG_IDE_PCMCIA - /* Enable 3.3 V on slot 0 ( VCC ) - No 5V */ - status = 4; - *pcmcia_bcsr = status; - - status |= BCSR_PCMCIA_PC0DRVEN; - *pcmcia_bcsr = status; - au_sync(); - - udelay(300*1000); - - status |= BCSR_PCMCIA_PC0RST; - *pcmcia_bcsr = status; - au_sync(); - - udelay(100*1000); - - /* PCMCIA is on a 36 bit physical address. - We need to map it into a 32 bit addresses */ - -#if 0 - /* We dont need theese unless we run whole pcmcia package */ - write_one_tlb(20, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_IO_BASE, /* Hi */ - 0x3C000017, /* Lo0 */ - 0x3C200017); /* Lo1 */ - - write_one_tlb(21, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_ATTR_BASE, /* Hi */ - 0x3D000017, /* Lo0 */ - 0x3D200017); /* Lo1 */ -#endif /* 0 */ - write_one_tlb(22, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_MEM_ADDR, /* Hi */ - 0x3E000017, /* Lo0 */ - 0x3E200017); /* Lo1 */ -#endif /* CONFIG_IDE_PCMCIA */ - - /* Release reset of ethernet PHY chips */ - /* Always do this, because linux does not know about it */ - *phy = 3; - - return 0; -} diff --git a/board/dbau1x00/flash.c b/board/dbau1x00/flash.c deleted file mode 100644 index 3cf29e8..0000000 --- a/board/dbau1x00/flash.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - printf ("Skipping flash_init\n"); - return (0); -} - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - printf ("write_buff not implemented\n"); - return (-1); -} diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S deleted file mode 100644 index 7afd584..0000000 --- a/board/dbau1x00/lowlevel_init.S +++ /dev/null @@ -1,587 +0,0 @@ -/* Memory sub-system initialization code */ - -#include -#include -#include -#include -#include - -#define AU1500_SYS_ADDR 0xB1900000 -#define sys_endian 0x0038 -#define CP0_Config0 $16 -#define CPU_SCALE ((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */ -#define MEM_1MS ((CFG_MHZ) * 1000) - - .text - .set noreorder - .set mips32 - - .globl lowlevel_init -lowlevel_init: - /* - * Step 1) Establish CPU endian mode. - * Db1500-specific: - * Switch S1.1 Off(bit7 reads 1) is Little Endian - * Switch S1.1 On (bit7 reads 0) is Big Endian - */ -#ifdef CONFIG_DBAU1550 - li t0, MEM_STCFG2 - li t1, 0x00000040 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x10c03f00 - sw t1, 0(t0) -#else - li t0, MEM_STCFG1 - li t1, 0x00000080 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x10c03f00 - sw t1, 0(t0) -#endif - - li t0, DB1XX0_BCSR_ADDR - lw t1,8(t0) - andi t1,t1,0x80 - beq zero,t1,big_endian - nop -little_endian: - - /* Change Au1 core to little endian */ - li t0, AU1500_SYS_ADDR - li t1, 1 - sw t1, sys_endian(t0) - mfc0 t2, CP0_CONFIG - mtc0 t2, CP0_CONFIG - nop - nop - - /* Big Endian is default so nothing to do but fall through */ - -big_endian: - - /* - * Step 2) Establish Status Register - * (set BEV, clear ERL, clear EXL, clear IE) - */ - li t1, 0x00400000 - mtc0 t1, CP0_STATUS - - /* - * Step 3) Establish CP0 Config0 - * (set OD, set K0=3) - */ - li t1, 0x00080003 - mtc0 t1, CP0_CONFIG - - /* - * Step 4) Disable Watchpoint facilities - */ - li t1, 0x00000000 - mtc0 t1, CP0_WATCHLO - mtc0 t1, CP0_IWATCHLO - /* - * Step 5) Disable the performance counters - */ - mtc0 zero, CP0_PERFORMANCE - nop - - /* - * Step 6) Establish EJTAG Debug register - */ - mtc0 zero, CP0_DEBUG - nop - - /* - * Step 7) Establish Cause - * (set IV bit) - */ - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* Establish Wired (and Random) */ - mtc0 zero, CP0_WIRED - nop - -#ifdef CONFIG_DBAU1550 - /* No workaround if running from ram */ - lui t0, 0xffc0 - lui t3, 0xbfc0 - and t1, ra, t0 - bne t1, t3, noCacheJump - nop - - /*** From AMD YAMON ***/ - /* - * Step 8) Initialize the caches - */ - li t0, (16*1024) - li t1, 32 - li t2, 0x80000000 - addu t3, t0, t2 -cacheloop: - cache 0, 0(t2) - cache 1, 0(t2) - addu t2, t1 - bne t2, t3, cacheloop - nop - - /* Save return address */ - move t3, ra - - /* Run from cacheable space now */ - bal cachehere - nop -cachehere: - li t1, ~0x20000000 /* convert to KSEG0 */ - and t0, ra, t1 - addi t0, 5*4 /* 5 insns beyond cachehere */ - jr t0 - nop - - /* Restore return address */ - move ra, t3 - - /* - * Step 9) Initialize the TLB - */ - li t0, 0 # index value - li t1, 0x00000000 # entryhi value - li t2, 32 # 32 entries - -tlbloop: - /* Probe TLB for matching EntryHi */ - mtc0 t1, CP0_ENTRYHI - tlbp - nop - - /* Examine Index[P], 1=no matching entry */ - mfc0 t3, CP0_INDEX - li t4, 0x80000000 - and t3, t4, t3 - addiu t1, t1, 1 # increment t1 (asid) - beq zero, t3, tlbloop - nop - - /* Initialize the TLB entry */ - mtc0 t0, CP0_INDEX - mtc0 zero, CP0_ENTRYLO0 - mtc0 zero, CP0_ENTRYLO1 - mtc0 zero, CP0_PAGEMASK - tlbwi - - /* Do it again */ - addiu t0, t0, 1 - bne t0, t2, tlbloop - nop - - /* First setup pll:s to make serial work ok */ - /* We have a 12 MHz crystal */ - li t0, SYS_CPUPLL - li t1, CPU_SCALE /* CPU clock */ - sw t1, 0(t0) - sync - nop - nop - - /* wait 1mS for clocks to settle */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - /* Setup AUX PLL */ - li t0, SYS_AUXPLL - li t1, 0x20 /* 96 MHz */ - sw t1, 0(t0) /* aux pll */ - sync - - /* Static memory controller */ - /* RCE0 - can not change while fetching, do so from icache */ - move t2, ra /* Store return address */ - bal getAddr - nop - -getAddr: - move t1, ra - move ra, t2 /* Move return addess back */ - - cache 0x14,0(t1) - cache 0x14,32(t1) - /*** /From YAMON ***/ - -noCacheJump: -#endif /* CONFIG_DBAU1550 */ - -#ifdef CONFIG_DBAU1550 - li t0, MEM_STTIME0 - li t1, 0x040181D7 - sw t1, 0(t0) - - /* RCE0 AMD MirrorBit Flash (?) */ - li t0, MEM_STCFG0 - li t1, 0x00000003 - sw t1, 0(t0) - - li t0, MEM_STADDR0 - li t1, 0x11803E00 - sw t1, 0(t0) -#else /* CONFIG_DBAU1550 */ - li t0, MEM_STTIME0 - li t1, 0x00014C0F - sw t1, 0(t0) - - /* RCE0 AMD 29LV640M MirrorBit Flash */ - li t0, MEM_STCFG0 - li t1, 0x00000013 - sw t1, 0(t0) - - li t0, MEM_STADDR0 - li t1, 0x11E03F80 - sw t1, 0(t0) -#endif /* CONFIG_DBAU1550 */ - - /* RCE1 CPLD Board Logic */ - li t0, MEM_STCFG1 - li t1, 0x00000080 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x10c03f00 - sw t1, 0(t0) - -#ifdef CONFIG_DBAU1550 - /* RCE2 CPLD Board Logic */ - li t0, MEM_STCFG2 - li t1, 0x00000040 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x10c03f00 - sw t1, 0(t0) -#else - li t0, MEM_STCFG2 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x00000000 - sw t1, 0(t0) -#endif - - /* RCE3 PCMCIA 250ns */ - li t0, MEM_STCFG3 - li t1, 0x00000002 - sw t1, 0(t0) - - li t0, MEM_STTIME3 - li t1, 0x280E3E07 - sw t1, 0(t0) - - li t0, MEM_STADDR3 - li t1, 0x10000000 - sw t1, 0(t0) - - sync - - /* Set peripherals to a known state */ - li t0, IC0_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC0_CFG0CLR - sw t1, 0(t0) - - li t0, IC0_CFG1CLR - sw t1, 0(t0) - - li t0, IC0_CFG2CLR - sw t1, 0(t0) - - li t0, IC0_SRCSET - sw t1, 0(t0) - - li t0, IC0_ASSIGNSET - sw t1, 0(t0) - - li t0, IC0_WAKECLR - sw t1, 0(t0) - - li t0, IC0_RISINGCLR - sw t1, 0(t0) - - li t0, IC0_FALLINGCLR - sw t1, 0(t0) - - li t0, IC0_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, IC1_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC1_CFG0CLR - sw t1, 0(t0) - - li t0, IC1_CFG1CLR - sw t1, 0(t0) - - li t0, IC1_CFG2CLR - sw t1, 0(t0) - - li t0, IC1_SRCSET - sw t1, 0(t0) - - li t0, IC1_ASSIGNSET - sw t1, 0(t0) - - li t0, IC1_WAKECLR - sw t1, 0(t0) - - li t0, IC1_RISINGCLR - sw t1, 0(t0) - - li t0, IC1_FALLINGCLR - sw t1, 0(t0) - - li t0, IC1_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, SYS_FREQCTRL0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_FREQCTRL1 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_CLKSRC - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_PININPUTEN - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, 0xB1100100 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, 0xB1400100 - li t1, 0x00000000 - sw t1, 0(t0) - - - li t0, SYS_WAKEMSK - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_WAKESRC - li t1, 0x00000000 - sw t1, 0(t0) - - /* wait 1mS before setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - -#ifdef CONFIG_DBAU1550 -/* SDCS 0,1,2 DDR SDRAM */ - li t0, MEM_SDMODE0 - li t1, 0x04276221 - sw t1, 0(t0) - - li t0, MEM_SDMODE1 - li t1, 0x04276221 - sw t1, 0(t0) - - li t0, MEM_SDMODE2 - li t1, 0x04276221 - sw t1, 0(t0) - - li t0, MEM_SDADDR0 - li t1, 0xe21003f0 - sw t1, 0(t0) - - li t0, MEM_SDADDR1 - li t1, 0xe21043f0 - sw t1, 0(t0) - - li t0, MEM_SDADDR2 - li t1, 0xe21083f0 - sw t1, 0(t0) - - sync - - li t0, MEM_SDCONFIGA - li t1, 0x9030060a /* Program refresh - disabled */ - sw t1, 0(t0) - sync - - li t0, MEM_SDCONFIGB - li t1, 0x00028000 - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD /* Precharge all */ - li t1, 0 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x40000000 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x40000000 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD2 - li t1, 0x40000000 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x00000063 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x00000063 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD2 - li t1, 0x00000063 - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD /* Precharge all */ - sw zero, 0(t0) - sync - - /* Issue 2 autoref */ - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - - /* Enable refresh */ - li t0, MEM_SDCONFIGA - li t1, 0x9830060a /* Program refresh - enabled */ - sw t1, 0(t0) - sync - -#else /* CONFIG_DBAU1550 */ -/* SDCS 0,1 SDRAM */ - li t0, MEM_SDMODE0 - li t1, 0x005522AA - sw t1, 0(t0) - - li t0, MEM_SDMODE1 - li t1, 0x005522AA - sw t1, 0(t0) - - li t0, MEM_SDMODE2 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_SDADDR0 - li t1, 0x001003F8 - sw t1, 0(t0) - - - li t0, MEM_SDADDR1 - li t1, 0x001023F8 - sw t1, 0(t0) - - li t0, MEM_SDADDR2 - li t1, 0x00000000 - sw t1, 0(t0) - - sync - - li t0, MEM_SDREFCFG - li t1, 0x64000C24 /* Disable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD - sw zero, 0(t0) - sync - - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - sw zero, 0(t0) - sync - - li t0, MEM_SDREFCFG - li t1, 0x66000C24 /* Enable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x00000033 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x00000033 - sw t1, 0(t0) - sync - -#endif /* CONFIG_DBAU1550 */ - /* wait 1mS after setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - - li t0, SYS_PINFUNC - li t1, 0x00008080 - sw t1, 0(t0) - - li t0, SYS_TRIOUTCLR - li t1, 0x00001FFF - sw t1, 0(t0) - - li t0, SYS_OUTPUTCLR - li t1, 0x00008000 - sw t1, 0(t0) - sync - - j ra - nop diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds deleted file mode 100644 index 10c9917..0000000 --- a/board/dbau1x00/u-boot.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - _gp = ALIGN(16); - - __got_start = .; - .got : { *(.got) } - __got_end = .; - - .sdata : { *(.sdata) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) } - uboot_end = .; -} diff --git a/board/dnp1110/Makefile b/board/dnp1110/Makefile deleted file mode 100644 index eaa38bc..0000000 --- a/board/dnp1110/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := dnp1110.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/dnp1110/config.mk b/board/dnp1110/config.mk deleted file mode 100644 index 4f6af46..0000000 --- a/board/dnp1110/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# DNP/1110 board with SA1100 cpu -# -# http://www.dilnetpc.com -# - -# -# DILNETPC has 1 banks of 32 MB DRAM -# -# c000'0000 -# -# Linux-Kernel is expected to be at c000'8000, entry c000'8000 -# -# we load ourself to c1f8'0000, the upper 1 MB of the first (only) bank -# - -TEXT_BASE = 0xc1f80000 diff --git a/board/dnp1110/dnp1110.c b/board/dnp1110/dnp1110.c deleted file mode 100644 index 24c3e00..0000000 --- a/board/dnp1110/dnp1110.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of DNP1110-Board */ - gd->bd->bi_arch_number = MACH_TYPE_DNP1110; - - /* flash vpp on */ - PPDR |= 0x80; /* assumes LCD controller is off */ - PPSR |= 0x80; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} diff --git a/board/dnp1110/flash.c b/board/dnp1110/flash.c deleted file mode 100644 index 60874ba..0000000 --- a/board/dnp1110/flash.c +++ /dev/null @@ -1,424 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel(void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) - { - switch (i) - { - case 0: - flash_get_size((FPW *)PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets(PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); break; - default: printf ("Unknown Chip Type\n"); break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW)0x00AA00AA; - addr[0x2AAA] = (FPW)0x00550055; - addr[0x5555] = (FPW)0x00900090; - - mb(); - value = addr[0]; - - switch (value) { - - case (FPW)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb(); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *)(info->start[sect]); - FPW status; - - printf("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW)0x00B000B0; /* suspend erase */ - *addr = (FPW)0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = (FPW)0x00500050; /* clear status register cmd. */ - *addr = (FPW)0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= port_width) { - data = 0; - for (i=0; i 0x800) - { - spin_wheel(); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i CFG_FLASH_WRITE_TOUT) { - *addr = (FPW)0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW)0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline -spin_wheel(void) -{ - static int p=0; - static char w[] = "\\/-"; - - printf("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/dnp1110/lowlevel_init.S b/board/dnp1110/lowlevel_init.S deleted file mode 100644 index 7730be3..0000000 --- a/board/dnp1110/lowlevel_init.S +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include "config.h" -#include "version.h" - - -/* some parameters for the board */ - -MEM_BASE: .long 0xa0000000 -MEM_START: .long 0xc0000000 - -#define MDCNFG 0x00 -#define MDCAS00 0x04 /* CAS waveform rotate reg 0 */ -#define MDCAS01 0x08 /* CAS waveform rotate reg 1 bank */ -#define MDCAS02 0x0C /* CAS waveform rotate reg 2 bank */ -#define MDREFR 0x1C /* DRAM refresh control reg */ -#define MDCAS20 0x20 /* CAS waveform rotate reg 0 bank */ -#define MDCAS21 0x24 /* CAS waveform rotate reg 1 bank */ -#define MDCAS22 0x28 /* CAS waveform rotate reg 2 bank */ -#define MECR 0x18 /* Expansion memory (PCMCIA) bus configuration register */ -#define MSC0 0x10 /* static memory control reg 0 */ -#define MSC1 0x14 /* static memory control reg 1 */ -#define MSC2 0x2C /* static memory control reg 2 */ -#define SMCNFG 0x30 /* SMROM configuration reg */ - -mdcas00: .long 0x5555557F -mdcas01: .long 0x55555555 -mdcas02: .long 0x55555555 -mdcas20: .long 0x5555557F -mdcas21: .long 0x55555555 -mdcas22: .long 0x55555555 -mdcnfg: .long 0x0000B25C -mdrefr: .long 0x007000C1 -mecr: .long 0x10841084 -msc0: .long 0x00004774 -msc1: .long 0x00000000 -msc2: .long 0x00000000 -smcnfg: .long 0x00000000 - -/* setting up the memory */ - -.globl lowlevel_init -lowlevel_init: - - ldr r0, MEM_BASE - - /* Set up the DRAM */ - - /* MDCAS00 */ - ldr r1, mdcas00 - str r1, [r0, #MDCAS00] - - /* MDCAS01 */ - ldr r1, mdcas01 - str r1, [r0, #MDCAS01] - - /* MDCAS02 */ - ldr r1, mdcas02 - str r1, [r0, #MDCAS02] - - /* MDCAS20 */ - ldr r1, mdcas20 - str r1, [r0, #MDCAS20] - - /* MDCAS21 */ - ldr r1, mdcas21 - str r1, [r0, #MDCAS21] - - /* MDCAS22 */ - ldr r1, mdcas22 - str r1, [r0, #MDCAS22] - - /* MDREFR */ - ldr r1, mdrefr - str r1, [r0, #MDREFR] - - /* Set up PCMCIA space */ - ldr r1, mecr - str r1, [r0, #MECR] - - /* Setup the flash memory and other */ - ldr r1, msc0 - str r1, [r0, #MSC0] - - ldr r1, msc1 - str r1, [r0, #MSC1] - - ldr r1, msc2 - str r1, [r0, #MSC2] - - ldr r1, smcnfg - str r1, [r0, #SMCNFG] - - /* MDCNFG */ - ldr r1, mdcnfg - bic r1, r1, #0x00000001 - str r1, [r0, #MDCNFG] - - /* Load something to activate bank */ - ldr r2, MEM_START -.rept 8 - ldr r1, [r2] -.endr - - /* MDCNFG */ - ldr r1, mdcnfg - orr r1, r1, #0x00000001 - str r1, [r0, #MDCNFG] - - /* everything is fine now */ - mov pc, lr diff --git a/board/dnp1110/u-boot.lds b/board/dnp1110/u-boot.lds deleted file mode 100644 index 258bece..0000000 --- a/board/dnp1110/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/sa1100/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/eXalion/Makefile b/board/eXalion/Makefile deleted file mode 100644 index cfbf465..0000000 --- a/board/eXalion/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o -SOBJS = - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/eXalion/config.mk b/board/eXalion/config.mk deleted file mode 100644 index b3f65eb..0000000 --- a/board/eXalion/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Sandpoint boards -# - -#TEXT_BASE = 0x00090000 -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/eXalion/eXalion.c b/board/eXalion/eXalion.c deleted file mode 100644 index 2e3f519..0000000 --- a/board/eXalion/eXalion.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include "piix_pci.h" -#include "eXalion.h" - -int checkboard (void) -{ - ulong busfreq = get_bus_freq (0); - char buf[32]; - - printf ("Board: eXalion MPC824x - CHRP (MAP B)\n"); - printf ("Built: %s at %s\n", __DATE__, __TIME__); - printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); - - return 0; -} - -int checkflash (void) -{ - printf ("checkflash\n"); - flash_init (); - return (0); -} - -long int initdram (int board_type) -{ - int i, cnt; - volatile uchar *base = CFG_SDRAM_BASE; - volatile ulong *addr; - ulong save[32]; - ulong val, ret = 0; - - for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0; - cnt >>= 1) { - addr = (volatile ulong *) base + cnt; - save[i++] = *addr; - *addr = ~cnt; - } - - addr = (volatile ulong *) base; - save[i] = *addr; - *addr = 0; - - if (*addr != 0) { - *addr = save[i]; - goto Done; - } - - for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *) base + cnt; - val = *addr; - *addr = save[--i]; - if (val != ~cnt) { - ulong new_bank0_end = cnt * sizeof (long) - 1; - ulong mear1 = mpc824x_mpc107_getreg (MEAR1); - ulong emear1 = mpc824x_mpc107_getreg (EMEAR1); - - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> - MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> - MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg (MEAR1, mear1); - mpc824x_mpc107_setreg (EMEAR1, emear1); - - ret = cnt * sizeof (long); - goto Done; - } - } - - ret = CFG_MAX_RAM_SIZE; - Done: - return ret; -} - -int misc_init_r (void) -{ - pci_dev_t bdf; - u32 val32; - u8 val8; - - puts ("ISA: "); - bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0); - if (bdf == -1) { - puts ("Unable to find PIIX4 ISA bridge !\n"); - hang (); - } - - /* set device for normal ISA instead EIO */ - pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32); - val32 |= 0x00000001; - pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32); - printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf), - PCI_DEV (bdf), PCI_FUNC (bdf)); - - puts ("ISA: "); - bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0); - if (bdf == -1) { - puts ("Unable to find PIIX4 IDE controller !\n"); - hang (); - } - - /* Init BMIBA register */ - /* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */ - /* val32 |= 0x1000; */ - /* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */ - - /* Enable BUS master and IO access */ - val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO; - pci_write_config_dword (bdf, PCI_COMMAND, val32); - - /* Set latency */ - pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8); - val8 = 0x40; - pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8); - - /* Enable Primary ATA/IDE */ - pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32); - /* val32 = 0xa307a307; */ - val32 = 0x00008000; - pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32); - - - printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf), - PCI_DEV (bdf), PCI_FUNC (bdf)); - - /* Try to get FAT working... */ - /* fat_register_read(ide_read); */ - - - return (0); -} - -/* - * Show/Init PCI devices on the specified bus number. - */ - -void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char line; - - switch (PCI_DEV (dev)) { - case 16: - line = PCI_INT_A; - break; - case 17: - line = PCI_INT_B; - break; - case 18: - line = PCI_INT_C; - break; - case 19: - line = PCI_INT_D; - break; -#if defined (CONFIG_MPC8245) - case 20: - line = PCI_INT_A; - break; - case 21: - line = PCI_INT_B; - break; - case 22: - line = PCI_INT_NA; - break; -#endif - default: - line = PCI_INT_A; - break; - } - pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line); -} - - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -#if defined (CONFIG_MPC8240) -static struct pci_config_table pci_eXalion_config_table[] = { - { - /* Intel 82559ER ethernet controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 PCI to ISA bridge */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 IDE controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - {} -}; -#elif defined (CONFIG_MPC8245) -static struct pci_config_table pci_eXalion_config_table[] = { - { - /* Intel 82559ER ethernet controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Intel 82559ER ethernet controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00, - pci_cfgfunc_config_device, {PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Broadcom BCM5690 Gigabit switch */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00, - pci_cfgfunc_config_device, {PCI_ENET2_IOADDR, - PCI_ENET2_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Broadcom BCM5690 Gigabit switch */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00, - pci_cfgfunc_config_device, {PCI_ENET3_IOADDR, - PCI_ENET3_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 PCI to ISA bridge */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - { - /* Intel 82371AB PIIX4 IDE controller */ - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01, - pci_cfgfunc_config_device, {0, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER}}, - {} -}; -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -#endif /* #ifndef CONFIG_PCI_PNP */ - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_eXalion_config_table, - fixup_irq:pci_eXalion_fixup_irq, -#endif -}; - -void pci_init_board (void) -{ - pci_mpc824x_init (&hose); -} diff --git a/board/eXalion/eXalion.h b/board/eXalion/eXalion.h deleted file mode 100644 index 8dccabb..0000000 --- a/board/eXalion/eXalion.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2002 - * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * James Dougherty (jfd@broadcom.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __EXALION_H -#define __EXALION_H - -/* IRQ settings */ -#define PCI_INT_NA (0xff) /* PCI Intr. not used */ -#define PCI_INT_A (0x09) /* PCI Intr. A Interrupt Request Line Nr. */ -#define PCI_INT_B (0x0a) /* PCI Intr. B Interrupt Request Line Nr. */ -#define PCI_INT_C (0x0b) /* PCI Intr. C Interrupt Request Line Nr. */ -#define PCI_INT_D (0x0c) /* PCI Intr. D Interrupt Request Line Nr. */ -#if defined (CPU_MPC8245) -#define LN_1_INT PCI_INT_B /* ethernet interrupt level */ -#define LN_2_INT PCI_INT_C /* ethernet interrupt level */ -#define BCM_1_INT PCI_INT_A /* BCM5690 interrupt level */ -#define BCM_2_INT PCI_INT_B /* BCM5690 interrupt level */ -#elif defined (CPU_MPC8240) -#define BCM_INT PCI_INT_B /* BCM5600 interrupt level */ -#define LN_INT PCI_INT_C /* ethernet interrupt level */ -#endif - -#ifndef __ASSEMBLY__ -#endif /* !__ASSEMBLY__ */ - -#endif /* __EXALION_H */ diff --git a/board/eXalion/piix_pci.h b/board/eXalion/piix_pci.h deleted file mode 100644 index b3c9c16..0000000 --- a/board/eXalion/piix_pci.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _PIIX4_PCI_H -#define _PIIX4_PCI_H - -#include -#include -#include -#include -#include - -#define PIIX4_VENDOR_ID 0x8086 -#define PIIX4_ISA_DEV_ID 0x7110 -#define PIIX4_IDE_DEV_ID 0x7111 - -/* Function 0 ISA Bridge */ -#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */ -#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */ -#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/ -#define PCI_CFG_PIIX4_SERIRQ 0x64 -#define PCI_CFG_PIIX4_TOM 0x69 -#define PCI_CFG_PIIX4_MSTAT 0x6A -#define PCI_CFG_PIIX4_MBDMA 0x76 -#define PCI_CFG_PIIX4_APICBS 0x80 -#define PCI_CFG_PIIX4_DLC 0x82 -#define PCI_CFG_PIIX4_PDMACFG 0x90 -#define PCI_CFG_PIIX4_DDMABS 0x92 -#define PCI_CFG_PIIX4_GENCFG 0xB0 -#define PCI_CFG_PIIX4_RTCCFG 0xCB - -/* IO Addresses */ -#define PIIX4_ISA_DMA1_CH0BA 0x00 -#define PIIX4_ISA_DMA1_CH0CA 0x01 -#define PIIX4_ISA_DMA1_CH1BA 0x02 -#define PIIX4_ISA_DMA1_CH1CA 0x03 -#define PIIX4_ISA_DMA1_CH2BA 0x04 -#define PIIX4_ISA_DMA1_CH2CA 0x05 -#define PIIX4_ISA_DMA1_CH3BA 0x06 -#define PIIX4_ISA_DMA1_CH3CA 0x07 -#define PIIX4_ISA_DMA1_CMDST 0x08 -#define PIIX4_ISA_DMA1_REQ 0x09 -#define PIIX4_ISA_DMA1_WSBM 0x0A -#define PIIX4_ISA_DMA1_CH_MOD 0x0B -#define PIIX4_ISA_DMA1_CLR_PT 0x0C -#define PIIX4_ISA_DMA1_M_CLR 0x0D -#define PIIX4_ISA_DMA1_CLR_M 0x0E -#define PIIX4_ISA_DMA1_RWAMB 0x0F - -#define PIIX4_ISA_DMA2_CH0BA 0xC0 -#define PIIX4_ISA_DMA2_CH0CA 0xC1 -#define PIIX4_ISA_DMA2_CH1BA 0xC2 -#define PIIX4_ISA_DMA2_CH1CA 0xC3 -#define PIIX4_ISA_DMA2_CH2BA 0xC4 -#define PIIX4_ISA_DMA2_CH2CA 0xC5 -#define PIIX4_ISA_DMA2_CH3BA 0xC6 -#define PIIX4_ISA_DMA2_CH3CA 0xC7 -#define PIIX4_ISA_DMA2_CMDST 0xD0 -#define PIIX4_ISA_DMA2_REQ 0xD2 -#define PIIX4_ISA_DMA2_WSBM 0xD4 -#define PIIX4_ISA_DMA2_CH_MOD 0xD6 -#define PIIX4_ISA_DMA2_CLR_PT 0xD8 -#define PIIX4_ISA_DMA2_M_CLR 0xDA -#define PIIX4_ISA_DMA2_CLR_M 0xDC -#define PIIX4_ISA_DMA2_RWAMB 0xDE - -#define PIIX4_ISA_INT1_ICW1 0x20 -#define PIIX4_ISA_INT1_OCW2 0x20 -#define PIIX4_ISA_INT1_OCW3 0x20 -#define PIIX4_ISA_INT1_ICW2 0x21 -#define PIIX4_ISA_INT1_ICW3 0x21 -#define PIIX4_ISA_INT1_ICW4 0x21 -#define PIIX4_ISA_INT1_OCW1 0x21 - -#define PIIX4_ISA_INT1_ELCR 0x4D0 - -#define PIIX4_ISA_INT2_ICW1 0xA0 -#define PIIX4_ISA_INT2_OCW2 0xA0 -#define PIIX4_ISA_INT2_OCW3 0xA0 -#define PIIX4_ISA_INT2_ICW2 0xA1 -#define PIIX4_ISA_INT2_ICW3 0xA1 -#define PIIX4_ISA_INT2_ICW4 0xA1 -#define PIIX4_ISA_INT2_OCW1 0xA1 -#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */ - -#define PIIX4_ISA_INT2_ELCR 0x4D1 - -#define PIIX4_ISA_TMR0_CNT_ST 0x40 -#define PIIX4_ISA_TMR1_CNT_ST 0x41 -#define PIIX4_ISA_TMR2_CNT_ST 0x42 -#define PIIX4_ISA_TMR_TCW 0x43 - -#define PIIX4_ISA_RST_XBUS 0x60 - -#define PIIX4_ISA_NMI_CNT_ST 0x61 -#define PIIX4_ISA_NMI_ENABLE 0x70 - -#define PIIX4_ISA_RTC_INDEX 0x70 -#define PIIX4_ISA_RTC_DATA 0x71 -#define PIIX4_ISA_RTCEXT_IND 0x70 -#define PIIX4_ISA_RTCEXT_DATA 0x71 - -#define PIIX4_ISA_DMA1_CH2LPG 0x81 -#define PIIX4_ISA_DMA1_CH3LPG 0x82 -#define PIIX4_ISA_DMA1_CH1LPG 0x83 -#define PIIX4_ISA_DMA1_CH0LPG 0x87 -#define PIIX4_ISA_DMA2_CH2LPG 0x89 -#define PIIX4_ISA_DMA2_CH3LPG 0x8A -#define PIIX4_ISA_DMA2_CH1LPG 0x8B -#define PIIX4_ISA_DMA2_LPGRFR 0x8F - -#define PIIX4_ISA_PORT_92 0x92 - -#define PIIX4_ISA_APM_CONTRL 0xB2 -#define PIIX4_ISA_APM_STATUS 0xB3 - -#define PIIX4_ISA_COCPU_ERROR 0xF0 - -/* Function 1 IDE Controller */ -#define PCI_CFG_PIIX4_BMIBA 0x20 -#define PCI_CFG_PIIX4_IDETIM 0x40 -#define PCI_CFG_PIIX4_SIDETIM 0x44 -#define PCI_CFG_PIIX4_UDMACTL 0x48 -#define PCI_CFG_PIIX4_UDMATIM 0x4A - -/* Function 2 USB Controller */ -#define PCI_CFG_PIIX4_SBRNUM 0x60 -#define PCI_CFG_PIIX4_LEGSUP 0xC0 - -/* Function 3 Power Management */ -#define PCI_CFG_PIIX4_PMAB 0x40 -#define PCI_CFG_PIIX4_CNTA 0x44 -#define PCI_CFG_PIIX4_CNTB 0x48 -#define PCI_CFG_PIIX4_GPICTL 0x4C -#define PCI_CFG_PIIX4_DEVRESD 0x50 -#define PCI_CFG_PIIX4_DEVACTA 0x54 -#define PCI_CFG_PIIX4_DEVACTB 0x58 -#define PCI_CFG_PIIX4_DEVRESA 0x5C -#define PCI_CFG_PIIX4_DEVRESB 0x60 -#define PCI_CFG_PIIX4_DEVRESC 0x64 -#define PCI_CFG_PIIX4_DEVRESE 0x68 -#define PCI_CFG_PIIX4_DEVRESF 0x6C -#define PCI_CFG_PIIX4_DEVRESG 0x70 -#define PCI_CFG_PIIX4_DEVRESH 0x74 -#define PCI_CFG_PIIX4_DEVRESI 0x78 -#define PCI_CFG_PIIX4_PMMISC 0x80 -#define PCI_CFG_PIIX4_SMBBA 0x90 - - -#endif /* _PIIX4_PCI_H */ diff --git a/board/eXalion/u-boot.lds b/board/eXalion/u-boot.lds deleted file mode 100644 index eaee3fd..0000000 --- a/board/eXalion/u-boot.lds +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/eltec/bab7xx/Makefile b/board/eltec/bab7xx/Makefile deleted file mode 100644 index 7d8ed26..0000000 --- a/board/eltec/bab7xx/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o pci.o misc.o el_srom.o dc_srom.o l2cache.o - -SOBJS = asm_init.o - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/eltec/bab7xx/asm_init.S b/board/eltec/bab7xx/asm_init.S deleted file mode 100644 index 2a9b33e..0000000 --- a/board/eltec/bab7xx/asm_init.S +++ /dev/null @@ -1,1476 +0,0 @@ -/* - * (C) Copyright 2001 ELTEC Elektronik AG - * Frank Gottschling - * - * ELTEC BAB PPC RAM initialization - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include <74xx_7xx.h> -#include -#include - -#include -#include - -/* - * This following contains the entry code for the initialization code - * for the MPC 106, a PCI Bridge/Memory Controller. - * Register usage: - * r0 = ramtest scratch register, toggleError loop counter - * r1 = 0xfec0 0cf8 CONFIG_ADDRESS - * r2 = 0xfee0 0cfc CONFIG_DATA - * r3 = scratch register, subroutine argument and return value, ramtest size - * r4 = scratch register, spdRead clock mask, OutHex loop count - * r5 = ramtest scratch register - * r6 = toggleError 1st value, spdRead port mask - * r7 = toggleError 2nd value, ramtest scratch register, - * spdRead scratch register (0x00) - * r8 = ramtest scratch register, spdRead scratch register (0x80) - * r9 = ramtest scratch register, toggleError loop end, OutHex digit - * r10 = ramtest scratch register, spdWriteByte parameter, - * spdReadByte return value, printf pointer to COM1 - * r11 = startType - * r12 = ramtest scratch register, spdRead data mask - * r13 = pointer to message block - * r14 = pointer to GOT - * r15 = scratch register, SPD save - * r16 = bank0 size, total memory size - * r17 = bank1 size - * r18 = bank2 size - * r19 = bank3 size - * r20 = MCCR1, MSAR1 - * r21 = MCCR3, MEAR1 - * r22 = MCCR4, MBER - * r23 = EMSAR1 - * r24 = EMEAR1 - * r25 = save link register 1st level - * r26 = save link register 2nd level - * r27 = save link register 3rd level - * r30 = pointer to GPIO for spdRead - */ - - -.globl board_asm_init -board_asm_init: -/* - * setup pointer to message block - */ - mflr r25 /* save away link register */ - bl get_lnk_reg /* r3=addr of next instruction */ - subi r4, r3, 8 /* r4=board_asm_init addr */ - addi r13, r4, (MessageBlock-board_asm_init) -/* - * dcache_disable - */ - mfspr r3, HID0 - li r4, HID0_DCE - andc r3, r3, r4 - mr r2, r3 - ori r3, r3, HID0_DCI - sync - mtspr HID0, r3 - mtspr HID0, r2 - isync - sync -/* - * icache_disable - */ - mfspr r3, HID0 - li r4, 0 - ori r4, r4, HID0_ICE - andc r3, r3, r4 - sync - mtspr HID0, r3 -/* - * invalidate caches - */ - ori r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE) - or r4, r4, r3 - isync - mtspr HID0, r4 - andc r4, r4, r3 - isync - mtspr HID0, r4 - isync -/* - * icache_enable - */ - mfspr r3, HID0 - ori r3, r3, (HID0_ICE | HID0_ICFI) - sync - mtspr HID0, r3 - - lis r1, 0xfec0 - ori r1, r1, 0x0cf8 - lis r2, 0xfee0 - ori r2, r2, 0xcfc - -#ifdef CFG_ADDRESS_MAP_A -/* - * Switch to address map A if necessary. - */ - lis r3, MPC106_REG@h - ori r3, r3, PCI_PICR1 - stwbrx r3, 0, r1 - sync - lwbrx r4, 0, r2 - sync - lis r0, PICR1_XIO_MODE@h - ori r0, r0, PICR1_XIO_MODE@l - andc r4, r4, r0 - lis r0, PICR1_ADDRESS_MAP@h - ori r0, r0, PICR1_ADDRESS_MAP@l - or r4, r4, r0 - stwbrx r4, 0, r2 - sync -#endif - -/* - * Do the init for the SIO. - */ - bl .sioInit - - addi r3, r13, (MinitLogo-MessageBlock) - bl Printf - - addi r3, r13, (Mspd01-MessageBlock) - bl Printf -/* - * Memory cofiguration using SPD information stored on the SODIMMs - */ - li r17, 0 - li r18, 0 - li r19, 0 - - li r3, 0x0002 /* get RAM type from spd for bank0/1 */ - bl spdRead - - cmpi 0, 0, r3, -1 /* error ? */ - bne noSpdError - - addi r3, r13, (Mfail-MessageBlock) - bl Printf - - li r6, 0xe0 /* error codes in r6 and r7 */ - li r7, 0x00 - b toggleError /* fail - loop forever */ - -noSpdError: - mr r15, r3 /* save r3 */ - - addi r3, r13, (Mok-MessageBlock) - bl Printf - - cmpli 0, 0, r15, 0x0001 /* FPM ? */ - beq configFPM - cmpli 0, 0, r15, 0x0002 /* EDO ? */ - beq configEDO - cmpli 0, 0, r15, 0x0004 /* SDRAM ? */ - beq configSDRAM - - li r6, 0xe0 /* error codes in r6 and r7 */ - li r7, 0x01 - b toggleError /* fail - loop forever */ - -configSDRAM: - addi r3, r13, (MsdRam-MessageBlock) - bl Printf -/* - * set the Memory Configuration Reg. 1 - */ - li r3, 0x001f /* get bank size from spd bank0/1 */ - bl spdRead - - andi. r3, r3, 0x0038 - beq SD16MB2B - - li r3, 0x0011 /* get number of internal banks */ - /* from spd for bank0/1 */ - bl spdRead - - cmpli 0, 0, r3, 0x02 - beq SD64MB2B - - cmpli 0, 0, r3, 0x04 - beq SD64MB4B - - li r6, 0xe0 /* error codes in r6 and r7 */ - li r7, 0x02 - b toggleError /* fail - loop forever */ - -SD64MB2B: - li r20, 0x0005 /* 64-Mbit SDRAM 2 banks */ - b SDRow2nd - -SD64MB4B: - li r20, 0x0000 /* 64-Mbit SDRAM 4 banks */ - b SDRow2nd - -SD16MB2B: - li r20, 0x000f /* 16-Mbit SDRAM 2 banks */ - -SDRow2nd: - li r3, 0x0102 /* get RAM type spd for bank2/3 */ - bl spdRead - - cmpli 0, 0, r3, 0x0004 - bne S2D64MB4B /* bank2/3 isn't present or no SDRAM */ - - li r3, 0x011f /* get bank size from spd bank2/3 */ - bl spdRead - - andi. r3, r3, 0x0038 - beq S2D16MB2B -/* - * set the Memory Configuration Reg. 2 - */ - li r3, 0x0111 /* get number of internal banks */ - /* from spd for bank2/3 */ - bl spdRead - - cmpli 0, 0, r3, 0x02 - beq S2D64MB2B - - cmpli 0, 0, r3, 0x04 - beq S2D64MB4B - - li r6, 0xe0 /* error codes in r6 and r7 */ - li r7, 0x03 - b toggleError /* fail - loop forever */ - -S2D64MB2B: - ori r20, r20, 0x0050 /* 64-Mbit SDRAM 2 banks */ - b S2D64MB4B - -S2D16MB2B: - ori r20, r20, 0x00f0 /* 16-Mbit SDRAM 2 banks */ - -/* - * set the Memory Configuration Reg. 3 - */ -S2D64MB4B: - lis r21, 0x8630 /* BSTOPRE = 0x80, REFREC = 6, */ - /* RDLAT = 3 */ - -/* - * set the Memory Configuration Reg. 4 - */ - lis r22, 0x2430 /* PRETOACT = 2, ACTOPRE = 4, */ - /* WCBUF = 1, RCBUF = 1 */ - ori r22, r22, 0x2220 /* SDMODE = 0x022, ACTORW = 2 */ - -/* - * get the size of bank 0-3 - */ - li r3, 0x001f /* get bank size from spd bank0/1 */ - bl spdRead - - rlwinm r16, r3, 2, 24, 29 /* calculate size in MByte */ - /* (128 MB max.) */ - - li r3, 0x0005 /* get number of banks from spd */ - /* for bank0/1 */ - bl spdRead - - cmpi 0, 0, r3, 2 /* 2 banks ? */ - bne SDRAMnobank1 - - mr r17, r16 - -SDRAMnobank1: - addi r3, r13, (Mspd23-MessageBlock) - bl Printf - - li r3, 0x0102 /* get RAM type spd for bank2/3 */ - bl spdRead - - cmpli 0, 0, r3, 0x0001 /* FPM ? */ - bne noFPM23 /* handle as EDO */ - addi r3, r13, (Mok-MessageBlock) - bl Printf - addi r3, r13, (MfpmRam-MessageBlock) - bl Printf - b configRAMcommon -noFPM23: - cmpli 0, 0, r3, 0x0002 /* EDO ? */ - bne noEDO23 - addi r3, r13, (Mok-MessageBlock) - bl Printf - addi r3, r13, (MedoRam-MessageBlock) - bl Printf - b configRAMcommon -noEDO23: - cmpli 0, 0, r3, 0x0004 /* SDRAM ? */ - bne noSDRAM23 - addi r3, r13, (Mok-MessageBlock) - bl Printf - addi r3, r13, (MsdRam-MessageBlock) - bl Printf - b configSDRAM23 -noSDRAM23: - addi r3, r13, (Mna-MessageBlock) - bl Printf - b configRAMcommon /* bank2/3 isn't present or no SDRAM */ - -configSDRAM23: - li r3, 0x011f /* get bank size from spd bank2/3 */ - bl spdRead - - rlwinm r18, r3, 2, 24, 29 /* calculate size in MByte */ - /* (128 MB max.) */ - - li r3, 0x0105 /* get number of banks from */ - /* spd bank0/1 */ - bl spdRead - - cmpi 0, 0, r3, 2 /* 2 banks ? */ - bne SDRAMnobank3 - - mr r19, r18 - -SDRAMnobank3: - b configRAMcommon - -configFPM: - addi r3, r13, (MfpmRam-MessageBlock) - bl Printf - b configEDO0 -/* - * set the Memory Configuration Reg. 1 - */ -configEDO: - addi r3, r13, (MedoRam-MessageBlock) - bl Printf -configEDO0: - lis r20, MCCR1_TYPE_EDO@h - -getSpdRowBank01: - li r3, 0x0003 /* get number of row bits from */ - /* spd from bank0/1 */ - bl spdRead - ori r20, r20, (MCCR1_BK0_9BITS | MCCR1_BK1_9BITS) - cmpli 0, 0, r3, 0x0009 /* bank0 - 9 row bits */ - beq getSpdRowBank23 - - ori r20, r20, (MCCR1_BK0_10BITS | MCCR1_BK1_10BITS) - cmpli 0, 0, r3, 0x000a /* bank0 - 10 row bits */ - beq getSpdRowBank23 - - ori r20, r20, (MCCR1_BK0_11BITS | MCCR1_BK1_11BITS) - cmpli 0, 0, r3, 0x000b /* bank0 - 11 row bits */ - beq getSpdRowBank23 - - ori r20, r20, (MCCR1_BK0_12BITS | MCCR1_BK1_12BITS) - cmpli 0, 0, r3, 0x000c /* bank0 - 12 row bits */ - beq getSpdRowBank23 - - cmpli 0, 0, r3, 0x000d /* bank0 - 13 row bits */ - beq getSpdRowBank23 - - li r6, 0xe0 /* error codes in r6 and r7 */ - li r7, 0x10 - b toggleError /* fail - loop forever */ - -getSpdRowBank23: - li r3, 0x0103 /* get number of row bits from */ - /* spd for bank2/3 */ - bl spdRead - - ori r20, r20, (MCCR1_BK2_9BITS | MCCR1_BK3_9BITS) - cmpli 0, 0, r3, 0x0009 /* bank0 - 9 row bits */ - beq writeRowBits - - ori r20, r20, (MCCR1_BK2_10BITS | MCCR1_BK3_10BITS) - cmpli 0, 0, r3, 0x000a /* bank0 - 10 row bits */ - beq writeRowBits - - ori r20, r20, (MCCR1_BK2_11BITS | MCCR1_BK3_11BITS) - cmpli 0, 0, r3, 0x000b /* bank0 - 11 row bits */ - beq writeRowBits - - ori r20, r20, (MCCR1_BK2_12BITS | MCCR1_BK3_12BITS) - -/* - * set the Memory Configuration Reg. 3 - */ -writeRowBits: - lis r21, 0x000a /* CPX = 1, RAS6P = 4 */ - ori r21, r21, 0x2293 /* CAS5 = 2, CP4 = 1, */ - /* CAS3 = 2, RCD2 = 2, RP = 3 */ -/* - * set the Memory Configuration Reg. 4 - */ - lis r22, 0x0010 /* all SDRAM parameter 0, */ - /* WCBUF flow through, */ - /* RCBUF registered */ -/* - * get the size of bank 0-3 - */ - li r3, 0x0003 /* get row bits from spd bank0/1 */ - bl spdRead - - li r16, 0 /* bank size is: */ - /* (8*2^row*2^column)/0x100000 MB */ - ori r16, r16, 0x8000 - rlwnm r16, r16, r3, 0, 31 - - li r3, 0x0004 /* get column bits from spd bank0/1 */ - bl spdRead - - rlwnm r16, r16, r3, 0, 31 - - li r3, 0x0005 /* get number of banks from */ - /* spd for bank0/1 */ - bl spdRead - - cmpi 0, 0, r3, 2 /* 2 banks ? */ - bne EDOnobank1 - - mr r17, r16 - -EDOnobank1: - addi r3, r13, (Mspd23-MessageBlock) - bl Printf - - li r3, 0x0102 /* get RAM type spd for bank2/3 */ - bl spdRead - - cmpli 0, 0, r3, 0x0001 /* FPM ? */ - bne noFPM231 /* handle as EDO */ - addi r3, r13, (Mok-MessageBlock) - bl Printf - addi r3, r13, (MfpmRam-MessageBlock) - bl Printf - b EDObank2 -noFPM231: - cmpli 0, 0, r3, 0x0002 /* EDO ? */ - bne noEDO231 - addi r3, r13, (Mok-MessageBlock) - bl Printf - addi r3, r13, (MedoRam-MessageBlock) - bl Printf - b EDObank2 -noEDO231: - cmpli 0, 0, r3, 0x0004 /* SDRAM ? */ - bne noSDRAM231 - addi r3, r13, (Mok-MessageBlock) - bl Printf - addi r3, r13, (MsdRam-MessageBlock) - bl Printf - b configRAMcommon -noSDRAM231: - addi r3, r13, (Mfail-MessageBlock) - bl Printf - b configRAMcommon /* bank2/3 isn't present or no SDRAM */ - -EDObank2: - li r3, 0x0103 /* get row bits from spd for bank2/3 */ - bl spdRead - - li r18, 0 /* bank size is: */ - /* (8*2^row*2^column)/0x100000 MB */ - ori r18, r18, 0x8000 - rlwnm r18, r18, r3, 0, 31 - - li r3, 0x0104 /* get column bits from spd bank2/3 */ - bl spdRead - - rlwnm r18, r18, r3, 0, 31 - - li r3, 0x0105 /* get number of banks from */ - /* spd for bank2/3 */ - bl spdRead - - cmpi 0, 0, r3, 2 /* 2 banks ? */ - bne configRAMcommon - - mr r19, r18 - -configRAMcommon: - lis r1, MPC106_REG_ADDR@h - ori r1, r1, MPC106_REG_ADDR@l - lis r2, MPC106_REG_DATA@h - ori r2, r2, MPC106_REG_DATA@l - - li r0, 0 - -/* - * If we are already running in RAM (debug mode), we should - * NOT reset the MEMGO flag. Otherwise we will stop all memory - * accesses. - */ -#ifdef IN_RAM - lis r4, MCCR1_MEMGO@h - ori r4, r4, MCCR1_MEMGO@l - or r20, r20, r4 -#endif - -/* - * set the Memory Configuration Reg. 1 - */ - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_MCCR1 /* register number 0xf0 */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - stwbrx r20, r0, r2 /* write data to CONFIG_DATA */ -/* - * set the Memory Configuration Reg. 3 - */ - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_MCCR3 /* register number 0xf8 */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - stwbrx r21, r0, r2 /* write data to CONFIG_DATA */ -/* - * set the Memory Configuration Reg. 4 - */ - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_MCCR4 /* register number 0xfc */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - stwbrx r22, r0, r2 /* write data to CONFIG_DATA */ -/* - * set the memory boundary registers for bank 0-3 - */ - li r20, 0 - li r23, 0 - li r24, 0 - subi r21, r16, 1 /* calculate end address bank0 */ - li r22, (MBER_BANK0) - - cmpi 0, 0, r17, 0 /* bank1 present ? */ - beq nobank1 - - rlwinm r3, r16, 8, 16, 23 /* calculate start address of bank1 */ - or r20, r20, r3 - add r16, r16, r17 /* add to total memory size */ - subi r3, r16, 1 /* calculate end address of bank1 */ - rlwinm r3, r3, 8, 16, 23 - or r21, r21, r3 - ori r22, r22, (MBER_BANK1) /* enable bank1 */ - b bank2 - -nobank1: - ori r23, r23, 0x0300 /* set bank1 start to unused area */ - ori r24, r24, 0x0300 /* set bank1 end to unused area */ - -bank2: - cmpi 0, 0, r18, 0 /* bank2 present ? */ - beq nobank2 - - andi. r3, r16, 0x00ff /* calculate start address of bank2 */ - andi. r4, r16, 0x0300 - rlwinm r3, r3, 16, 8, 15 - or r20, r20, r3 - rlwinm r3, r4, 8, 8, 15 - or r23, r23, r3 - add r16, r16, r18 /* add to total memory size */ - subi r3, r16, 1 /* calculate end address of bank2 */ - andi. r4, r3, 0x0300 - andi. r3, r3, 0x00ff - rlwinm r3, r3, 16, 8, 15 - or r21, r21, r3 - rlwinm r3, r4, 8, 8, 15 - or r24, r24, r3 - ori r22, r22, (MBER_BANK2) /* enable bank2 */ - b bank3 - -nobank2: - lis r3, 0x0003 - or r23, r23, r3 /* set bank2 start to unused area */ - or r24, r24, r3 /* set bank2 end to unused area */ - -bank3: - cmpi 0, 0, r19, 0 /* bank3 present ? */ - beq nobank3 - - andi. r3, r16, 0x00ff /* calculate start address of bank3 */ - andi. r4, r16, 0x0300 - rlwinm r3, r3, 24, 0, 7 - or r20, r20, r3 - rlwinm r3, r4, 16, 0, 7 - or r23, r23, r3 - add r16, r16, r19 /* add to total memory size */ - subi r3, r16, 1 /* calculate end address of bank3 */ - andi. r4, r3, 0x0300 - andi. r3, r3, 0x00ff - rlwinm r3, r3, 24, 0, 7 - or r21, r21, r3 - rlwinm r3, r4, 16, 0, 7 - or r24, r24, r3 - ori r22, r22, (MBER_BANK3) /* enable bank3 */ - b writebound - -nobank3: - lis r3, 0x0300 - or r23, r23, r3 /* set bank3 start to unused area */ - or r24, r24, r3 /* set bank3 end to unused area */ - -writebound: - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_MSAR1 /* register number 0x80 */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - stwbrx r20, r0, r2 /* write data to CONFIG_DATA */ - - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_MEAR1 /* register number 0x90 */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - stwbrx r21, r0, r2 /* write data to CONFIG_DATA */ - - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_EMSAR1 /* register number 0x88 */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - stwbrx r23, r0, r2 /* write data to CONFIG_DATA */ - - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_EMEAR1 /* register number 0x98 */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - stwbrx r24, r0, r2 /* write data to CONFIG_DATA */ - -/* - * set boundaries of unused banks to unused address space - */ - lis r4, 0x0303 - ori r4, r4, 0x0303 /* bank 4-7 start and end adresses */ - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_EMSAR2 /* register number 0x8C */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - stwbrx r4, r0, r2 /* write data to CONFIG_DATA */ - - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_EMEAR2 /* register number 0x9C */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - stwbrx r4, r0, r2 /* write data to CONFIG_DATA */ - -/* - * set the Memory Configuration Reg. 2 - */ - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_MCCR2 /* register number 0xf4 */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - - li r3, 0x000c /* get refresh from spd for bank0/1 */ - bl spdRead - - cmpi 0, 0, r3, -1 /* error ? */ - bne common1 - - li r6, 0xe0 /* error codes in r6 and r7 */ - li r7, 0x20 - b toggleError /* fail - loop forever */ - -common1: - andi. r15, r3, 0x007f /* mask selfrefresh bit */ - li r3, 0x010c /* get refresh from spd for bank2/3 */ - bl spdRead - - cmpi 0, 0, r3, -1 /* error ? */ - beq common2 - andi. r3, r3, 0x007f /* mask selfrefresh bit */ - cmp 0, 0, r3, r15 /* find the lower */ - blt common3 - -common2: - mr r3, r15 - -common3: - li r4, 0x1010 /* refesh cycle 1028 clocks */ - /* left shifted 2 */ - cmpli 0, 0, r3, 0x0000 /* 15.6 us ? */ - beq writeRefresh - - li r4, 0x0808 /* refesh cycle 514 clocks */ - /* left shifted 2 */ - cmpli 0, 0, r3, 0x0002 /* 7.8 us ? */ - beq writeRefresh - - li r4, 0x2020 /* refesh cycle 2056 clocks */ - /* left shifted 2 */ - cmpli 0, 0, r3, 0x0003 /* 31.3 us ? */ - beq writeRefresh - - li r4, 0x4040 /* refesh cycle 4112 clocks */ - /* left shifted 2 */ - cmpli 0, 0, r3, 0x0004 /* 62.5 us ? */ - beq writeRefresh - - li r4, 0 - ori r4, r4, 0x8080 /* refesh cycle 8224 clocks */ - /* left shifted 2 */ - cmpli 0, 0, r3, 0x0005 /* 125 us ? */ - beq writeRefresh - - li r6, 0xe0 /* error codes in r6 and r7 */ - li r7, 0x21 - b toggleError /* fail - loop forever */ - -writeRefresh: - stwbrx r4, r0, r2 /* write data to CONFIG_DATA */ - -/* - * DRAM BANKS SHOULD BE ENABLED - */ - addi r3, r13, (Mactivate-MessageBlock) - bl Printf - mr r3, r16 - bl OutDec - addi r3, r13, (Mmbyte-MessageBlock) - bl Printf - - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_MBER /* register number 0xa0 */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - stb r22, 0(r2) /* write data to CONFIG_DATA */ - li r8, 0x63 /* PGMAX = 99 */ - stb r8, 3(r2) /* write data to CONFIG_DATA */ - -/* - * DRAM SHOULD NOW BE CONFIGURED AND ENABLED - * MUST WAIT 200us BEFORE ACCESSING - */ - li r0, 0x7800 - mtctr r0 - -wait200us: - bdnz wait200us - - lis r3, MPC106_REG@h /* start building new reg number */ - ori r3, r3, MPC106_MCCR1 /* register number 0xf0 */ - stwbrx r3, r0, r1 /* write this value to CONFIG_ADDR */ - eieio /* make sure mem. access is complete */ - - lwbrx r4, r0, r2 /* load r4 from CONFIG_DATA */ - - lis r0, MCCR1_MEMGO@h /* MEMGO=1 */ - ori r0, r0, MCCR1_MEMGO@l - or r4, r4, r0 /* set the MEMGO bit */ - stwbrx r4, r0, r2 /* write mdfd data to CONFIG_DATA */ - - li r0, 0x7000 - mtctr r0 - -wait8ref: - bdnz wait8ref - - addi r3, r13, (Mok-MessageBlock) - bl Printf - - mtlr r25 - blr - -/* - * Infinite loop called in case of an error during RAM initialisation. - * error codes in r6 and r7. - */ -toggleError: - li r0, 0 - lis r9, 127 - ori r9, r9, 65535 -toggleError1: - addic r0, r0, 1 - cmpw cr1, r0, r9 - ble cr1, toggleError1 - li r0, 0 - lis r9, 127 - ori r9, r9, 65535 -toggleError2: - addic r0, r0, 1 - cmpw cr1, r0, r9 - ble cr1, toggleError2 - b toggleError - - -/****************************************************************************** - * This function performs a basic initialisation of the superio chip - * to enable basic console output and SPD access during RAM initialisation. - * - * Upon completion, SIO resource registers are mapped as follows: - * Resource Enabled Address - * UART1 Yes 3F8-3FF COM1 - * UART2 Yes 2F8-2FF COM2 - * GPIO Yes 220-227 - */ -.set SIO_LUNINDEX, 0x07 /* SIO LUN index register */ -.set SIO_CNFG1, 0x21 /* SIO configuration #1 register */ -.set SIO_PCSCI, 0x23 /* SIO PCS configuration index reg */ -.set SIO_PCSCD, 0x24 /* SIO PCS configuration data reg */ -.set SIO_ACTIVATE, 0x30 /* SIO activate register */ -.set SIO_IOBASEHI, 0x60 /* SIO I/O port base address, 15:8 */ -.set SIO_IOBASELO, 0x61 /* SIO I/O port base address, 7:0 */ -.set SIO_LUNENABLE, 0x01 /* SIO LUN enable */ - -.sioInit: - mfspr r7, 8 /* save link register */ - -.sioInit_87308: - -/* - * Get base addr of ISA I/O space - */ - lis r6, CFG_ISA_IO@h - ori r6, r6, CFG_ISA_IO@l - -/* - * Set offset to base address for config registers. - */ -#if defined(CFG_NS87308_BADDR_0x) - addi r4, r0, 0x0279 -#elif defined(CFG_NS87308_BADDR_10) - addi r4, r0, 0x015C -#elif defined(CFG_NS87308_BADDR_11) - addi r4, r0, 0x002E -#endif - add r6, r6, r4 /* add offset to base */ - or r3, r6, r6 /* make a copy */ - -/* - * PMC (LUN 8) - */ - addi r4, r0, SIO_LUNINDEX /* select PMC LUN */ - addi r5, r0, 0x8 - bl .sio_bw - addi r4, r0, SIO_IOBASEHI /* initialize PMC address to 0x460 */ - addi r5, r0, 0x04 - bl .sio_bw - addi r4, r0, SIO_IOBASELO - addi r5, r0, 0x60 - bl .sio_bw - addi r4, r0, SIO_ACTIVATE /* enable PMC */ - addi r5, r0, SIO_LUNENABLE - bl .sio_bw - - lis r8, CFG_ISA_IO@h - ori r8, r8, 0x0460 - li r9, 0x03 - stb r9, 0(r8) /* select PMC2 register */ - eieio - li r9, 0x00 - stb r9, 1(r8) /* SuperI/O clock src: 24MHz via X1 */ - eieio - -/* - * map UART1 (LUN 6) or UART2 (LUN 5) to COM1 (0x3F8) - */ - addi r4, r0, SIO_LUNINDEX /* select COM1 LUN */ - addi r5, r0, 0x6 - bl .sio_bw - - addi r4, r0, SIO_IOBASEHI /* initialize COM1 address to 0x3F8 */ - addi r5, r0, 0x03 - bl .sio_bw - - addi r4, r0, SIO_IOBASELO - addi r5, r0, 0xF8 - bl .sio_bw - - addi r4, r0, SIO_ACTIVATE /* enable COM1 */ - addi r5, r0, SIO_LUNENABLE - bl .sio_bw - -/* - * Init COM1 for polled output - */ - lis r8, CFG_ISA_IO@h - ori r8, r8, 0x03f8 - li r9, 0x00 - stb r9, 1(r8) /* int disabled */ - eieio - li r9, 0x00 - stb r9, 4(r8) /* modem ctrl */ - eieio - li r9, 0x80 - stb r9, 3(r8) /* link ctrl, bank select */ - eieio - li r9, 115200/CONFIG_BAUDRATE - stb r9, 0(r8) /* baud rate (LSB)*/ - eieio - rotrwi r9, r9, 8 - stb r9, 1(r8) /* baud rate (MSB) */ - eieio - li r9, 0x03 - stb r9, 3(r8) /* 8 data bits, 1 stop bit, */ - /* no parity */ - eieio - li r9, 0x0b - stb r9, 4(r8) /* enable the receiver and transmitter */ - eieio - -waitEmpty: - lbz r9, 5(r8) /* transmit empty */ - andi. r9, r9, 0x40 - beq waitEmpty - li r9, 0x47 - stb r9, 3(r8) /* send break, 8 data bits, */ - /* 2 stop bits, no parity */ - eieio - - lis r0, 0x0001 - mtctr r0 - -waitCOM1: - lwz r0, 5(r8) /* load from port for delay */ - bdnz waitCOM1 - -waitEmpty1: - lbz r9, 5(r8) /* transmit empty */ - andi. r9, r9, 0x40 - beq waitEmpty1 - li r9, 0x07 - stb r9, 3(r8) /* 8 data bits, 2 stop bits, */ - /* no parity */ - eieio - -/* - * GPIO (LUN 7) - */ - addi r4, r0, SIO_LUNINDEX /* select GPIO LUN */ - addi r5, r0, 0x7 - bl .sio_bw - - addi r4, r0, SIO_IOBASEHI /* initialize GPIO address to 0x220 */ - addi r5, r0, 0x02 - bl .sio_bw - - addi r4, r0, SIO_IOBASELO - addi r5, r0, 0x20 - bl .sio_bw - - addi r4, r0, SIO_ACTIVATE /* enable GPIO */ - addi r5, r0, SIO_LUNENABLE - bl .sio_bw - -.sioInit_done: - -/* - * Get base addr of ISA I/O space - */ - lis r3, CFG_ISA_IO@h - ori r3, r3, CFG_ISA_IO@l - - addi r3, r3, 0x015C /* adjust to superI/O 87308 base */ - or r6, r3, r3 /* make a copy */ -/* - * CS0 - */ - addi r4, r0, SIO_PCSCI /* select PCSCIR */ - addi r5, r0, 0x00 - bl .sio_bw - addi r4, r0, SIO_PCSCD /* select PCSCDR */ - addi r5, r0, 0x00 - bl .sio_bw - addi r4, r0, SIO_PCSCI /* select PCSCIR */ - addi r5, r0, 0x01 - bl .sio_bw - addi r4, r0, SIO_PCSCD /* select PCSCDR */ - addi r5, r0, 0x76 - bl .sio_bw - addi r4, r0, SIO_PCSCI /* select PCSCIR */ - addi r5, r0, 0x02 - bl .sio_bw - addi r4, r0, SIO_PCSCD /* select PCSCDR */ - addi r5, r0, 0x40 - bl .sio_bw -/* - * CS1 - */ - addi r4, r0, SIO_PCSCI /* select PCSCIR */ - addi r5, r0, 0x05 - bl .sio_bw - addi r4, r0, SIO_PCSCD /* select PCSCDR */ - addi r5, r0, 0x00 - bl .sio_bw - addi r4, r0, SIO_PCSCI /* select PCSCIR */ - addi r5, r0, 0x05 - bl .sio_bw - addi r4, r0, SIO_PCSCD /* select PCSCDR */ - addi r5, r0, 0x70 - bl .sio_bw - addi r4, r0, SIO_PCSCI /* select PCSCIR */ - addi r5, r0, 0x06 - bl .sio_bw - addi r4, r0, SIO_PCSCD /* select PCSCDR */ - addi r5, r0, 0x1C - bl .sio_bw -/* - * CS2 - */ - addi r4, r0, SIO_PCSCI /* select PCSCIR */ - addi r5, r0, 0x08 - bl .sio_bw - addi r4, r0, SIO_PCSCD /* select PCSCDR */ - addi r5, r0, 0x00 - bl .sio_bw - addi r4, r0, SIO_PCSCI /* select PCSCIR */ - addi r5, r0, 0x09 - bl .sio_bw - addi r4, r0, SIO_PCSCD /* select PCSCDR */ - addi r5, r0, 0x71 - bl .sio_bw - addi r4, r0, SIO_PCSCI /* select PCSCIR */ - addi r5, r0, 0x0A - bl .sio_bw - addi r4, r0, SIO_PCSCD /* select PCSCDR */ - addi r5, r0, 0x1C - bl .sio_bw - - mtspr 8, r7 /* restore link register */ - bclr 20, 0 /* return to caller */ - -/* - * this function writes a register to the SIO chip - */ -.sio_bw: - stb r4, 0(r3) /* write index register with register offset */ - eieio - sync - stb r5, 1(r3) /* 1st write */ - eieio - sync - stb r5, 1(r3) /* 2nd write */ - eieio - sync - bclr 20, 0 /* return to caller */ -/* - * this function reads a register from the SIO chip - */ -.sio_br: - stb r4, 0(r3) /* write index register with register offset */ - eieio - sync - lbz r3, 1(r3) /* retrieve specified reg offset contents */ - eieio - sync - bclr 20, 0 /* return to caller */ - -/* - * Print a message to COM1 in polling mode - * r10=COM1 port, r3=(char*)string - */ -.globl Printf -Printf: - lis r10, CFG_ISA_IO@h /* COM1 port */ - ori r10, r10, 0x03f8 - -WaitChr: - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, WaitChr /* wait till empty */ - lbzx r0, r0, r3 /* get char */ - stb r0, 0(r10) /* write to transmit reg */ - eieio - addi r3, r3, 1 /* next char */ - lbzx r0, r0, r3 /* get char */ - cmpwi cr1, r0, 0 /* end of string ? */ - bne cr1, WaitChr - blr - -/* - * Print 8/4/2 digits hex value to COM1 in polling mode - * r10=COM1 port, r3=val - */ -OutHex2: - li r9, 4 /* shift reg for 2 digits */ - b OHstart -OutHex4: - li r9, 12 /* shift reg for 4 digits */ - b OHstart - .globl OutHex -OutHex: - li r9, 28 /* shift reg for 8 digits */ -OHstart: - lis r10, CFG_ISA_IO@h /* COM1 port */ - ori r10, r10, 0x03f8 -OutDig: - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDig - sraw r0, r3, r9 - clrlwi r0, r0, 28 - cmpwi cr1, r0, 9 - ble cr1, digIsNum - addic r0, r0, 55 - b nextDig -digIsNum: - addic r0, r0, 48 -nextDig: - stb r0, 0(r10) /* write to transmit reg */ - eieio - addic. r9, r9, -4 - bge OutDig - blr -/* - * Print 3 digits hdec value to COM1 in polling mode - * r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch - */ -.globl OutDec -OutDec: - li r6, 10 - divwu r0, r3, r6 /* r0 = r3 / 10, r9 = r3 mod 10 */ - mullw r10, r0, r6 - subf r9, r10, r3 - - mr r3, r0 - divwu r0, r3, r6 /* r0 = r3 / 10, r8 = r3 mod 10 */ - mullw r10, r0, r6 - subf r8, r10, r3 - - mr r3, r0 - divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */ - mullw r10, r0, r6 - subf r7, r10, r3 - - lis r10, CFG_ISA_IO@h /* COM1 port */ - ori r10, r10, 0x03f8 - - or. r7, r7, r7 - bne noblank1 - li r3, 0x20 - b OutDec4 - -noblank1: - addi r3, r7, 48 /* convert to ASCII */ - -OutDec4: - lbz r0, 0(r13) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec4 - stb r3, 0(r10) /* x00 to transmit */ - eieio - - or. r7, r7, r8 - beq OutDec5 - - addi r3, r8, 48 /* convert to ASCII */ -OutDec5: - lbz r0, 0(r13) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec5 - stb r3, 0(r10) /* x0 to transmit */ - eieio - - addi r3, r9, 48 /* convert to ASCII */ -OutDec6: - lbz r0, 0(r13) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec6 - stb r3, 0(r10) /* x to transmit */ - eieio - blr -/* - * Print a char to COM1 in polling mode - * r10=COM1 port, r3=char - */ -.globl OutChr -OutChr: - lis r10, CFG_ISA_IO@h /* COM1 port */ - ori r10, r10, 0x03f8 - -OutChr1: - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutChr1 /* wait till empty */ - stb r3, 0(r10) /* write to transmit reg */ - eieio - blr -/* - * Input: r3 adr to read - * Output: r3 val or -1 for error - */ -spdRead: - mfspr r26, 8 /* save link register */ - - lis r30, CFG_ISA_IO@h - ori r30, r30, 0x220 /* GPIO Port 1 */ - li r7, 0x00 - li r8, 0x100 - and. r5, r3, r8 - beq spdbank0 - li r12, 0x08 - li r4, 0x10 - li r6, 0x18 - b spdRead1 - -spdbank0: - li r12, 0x20 /* set I2C data */ - li r4, 0x40 /* set I2C clock */ - li r6, 0x60 /* set I2C clock and data */ - -spdRead1: - li r8, 0x80 - - bl spdStart /* access I2C bus as master */ - li r10, 0xa0 /* write to SPD */ - bl spdWriteByte - bl spdReadAck /* ACK returns in r10 */ - cmpw cr0, r10, r7 - bne AckErr /* r10 must be 0, if ACK received */ - mr r10, r3 /* adr to read */ - bl spdWriteByte - bl spdReadAck - cmpw cr0, r10, r7 - bne AckErr - bl spdStart - li r10, 0xa1 /* read from SPD */ - bl spdWriteByte - bl spdReadAck - cmpw cr0, r10, r7 - bne AckErr - bl spdReadByte /* return val in r10 */ - bl spdWriteAck - bl spdStop /* release I2C bus */ - mr r3, r10 - mtspr 8, r26 /* restore link register */ - blr -/* - * ACK error occurred - */ -AckErr: - bl spdStop - orc r3, r0, r0 /* return -1 */ - mtspr 8, r26 /* restore link register */ - blr - -/* - * Routines to read from RAM spd. - * r30 - GPIO Port1 address in all cases. - * r4 - clock mask for SPD - * r6 - port mask for SPD - * r12 - data mask for SPD - */ -waitSpd: - li r0, 0x1000 - mtctr r0 -wSpd: - bdnz wSpd - bclr 20, 0 /* return to caller */ - -/* - * establish START condition on I2C bus - */ -spdStart: - mfspr r27, 8 /* save link register */ - stb r6, 0(r30) /* set SDA and SCL */ - eieio - stb r6, 1(r30) /* switch GPIO to output */ - eieio - bl waitSpd - stb r4, 0(r30) /* reset SDA */ - eieio - bl waitSpd - stb r7, 0(r30) /* reset SCL */ - eieio - bl waitSpd - mtspr 8, r27 - bclr 20, 0 /* return to caller */ - -/* - * establish STOP condition on I2C bus - */ -spdStop: - mfspr r27, 8 /* save link register */ - stb r7, 0(r30) /* reset SCL and SDA */ - eieio - stb r6, 1(r30) /* switch GPIO to output */ - eieio - bl waitSpd - stb r4, 0(r30) /* set SCL */ - eieio - bl waitSpd - stb r6, 0(r30) /* set SDA and SCL */ - eieio - bl waitSpd - stb r7, 1(r30) /* switch GPIO to input */ - eieio - mtspr 8, r27 - bclr 20, 0 /* return to caller */ - -spdReadByte: - mfspr r27, 8 - stb r4, 1(r30) /* set GPIO for SCL output */ - eieio - li r9, 0x08 - li r10, 0x00 -loopRB: - stb r7, 0(r30) /* reset SDA and SCL */ - eieio - bl waitSpd - stb r4, 0(r30) /* set SCL */ - eieio - bl waitSpd - lbz r5, 0(r30) /* read from GPIO Port1 */ - rlwinm r10, r10, 1, 0, 31 - and. r5, r5, r12 - beq clearBit - ori r10, r10, 0x01 /* append _1_ */ -clearBit: - stb r7, 0(r30) /* reset SCL */ - eieio - bl waitSpd - addic. r9, r9, -1 - bne loopRB - mtspr 8, r27 - bclr 20, 0 /* return (r10) to caller */ - -/* - * spdWriteByte writes bits 24 - 31 of r10 to I2C. - * r8 contains bit mask 0x80 - */ -spdWriteByte: - mfspr r27, 8 /* save link register */ - li r9, 0x08 /* write octet */ - and. r5, r10, r8 - bne sWB1 - stb r7, 0(r30) /* set SDA to _0_ */ - eieio - b sWB2 -sWB1: - stb r12, 0(r30) /* set SDA to _1_ */ - eieio -sWB2: - stb r6, 1(r30) /* set GPIO to output */ - eieio -loopWB: - and. r5, r10, r8 - bne sWB3 - stb r7, 0(r30) /* set SDA to _0_ */ - eieio - b sWB4 -sWB3: - stb r12, 0(r30) /* set SDA to _1_ */ - eieio -sWB4: - bl waitSpd - and. r5, r10, r8 - bne sWB5 - stb r4, 0(r30) /* set SDA to _0_ and SCL */ - eieio - b sWB6 -sWB5: - stb r6, 0(r30) /* set SDA to _1_ and SCL */ - eieio -sWB6: - bl waitSpd - and. r5, r10, r8 - bne sWB7 - stb r7, 0(r30) /* set SDA to _0_ and reset SCL */ - eieio - b sWB8 -sWB7: - stb r12, 0(r30) /* set SDA to _1_ and reset SCL */ - eieio -sWB8: - bl waitSpd - rlwinm r10, r10, 1, 0, 31 /* next bit */ - addic. r9, r9, -1 - bne loopWB - mtspr 8, r27 - bclr 20, 0 /* return to caller */ - -/* - * Read ACK from SPD, return value in r10 - */ -spdReadAck: - mfspr r27, 8 /* save link register */ - stb r4, 1(r30) /* set GPIO to output */ - eieio - stb r7, 0(r30) /* reset SDA and SCL */ - eieio - bl waitSpd - stb r4, 0(r30) /* set SCL */ - eieio - bl waitSpd - lbz r10, 0(r30) /* read GPIO Port 1 and mask SDA */ - and r10, r10, r12 - bl waitSpd - stb r7, 0(r30) /* reset SDA and SCL */ - eieio - bl waitSpd - mtspr 8, r27 - bclr 20, 0 /* return (r10) to caller */ - -spdWriteAck: - mfspr r27, 8 - stb r12, 0(r30) /* set SCL */ - eieio - stb r6, 1(r30) /* set GPIO to output */ - eieio - bl waitSpd - stb r6, 0(r30) /* SDA and SCL */ - eieio - bl waitSpd - stb r12, 0(r30) /* reset SCL */ - eieio - bl waitSpd - mtspr 8, r27 - bclr 20, 0 /* return to caller */ - -get_lnk_reg: - mflr r3 /* return link reg */ - blr - -/* - * Messages for console output - */ -.globl MessageBlock -MessageBlock: -Mok: - .ascii "OK\015\012\000" -Mfail: - .ascii "FAILED\015\012\000" -Mna: - .ascii "NA\015\012\000" -MinitLogo: - .ascii "\015\012*** ELTEC Elektronik, Mainz ***\015\012" - .ascii "\015\012Initialising RAM\015\012\000" -Mspd01: - .ascii " Reading SPD of bank0/1 ..... \000" -Mspd23: - .ascii " Reading SPD of bank2/3 ..... \000" -MfpmRam: - .ascii " RAM-Type: FPM \015\012\000" -MedoRam: - .ascii " RAM-Type: EDO \015\012\000" -MsdRam: - .ascii " RAM-Type: SDRAM \015\012\000" -Mactivate: - .ascii " Activating \000" -Mmbyte: - .ascii " MB .......... \000" - .align 4 diff --git a/board/eltec/bab7xx/bab7xx.c b/board/eltec/bab7xx/bab7xx.c deleted file mode 100644 index fc48ed5..0000000 --- a/board/eltec/bab7xx/bab7xx.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH - * Andreas Heppel - * (C) Copyright 2001 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include <74xx_7xx.h> -#include -#include - -/*---------------------------------------------------------------------------*/ -/* - * Get Bus clock frequency - */ -ulong bab7xx_get_bus_freq (void) -{ - /* - * The GPIO Port 1 on BAB7xx reflects the bus speed. - */ - volatile struct GPIO *gpio = - (struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE); - - unsigned char data = gpio->dta1; - - if (data & 0x02) - return 66666666; - - return 83333333; -} - -/*---------------------------------------------------------------------------*/ - -/* - * Measure CPU clock speed (core clock GCLK1) (Approx. GCLK frequency in Hz) - */ -ulong bab7xx_get_gclk_freq (void) -{ - static const int pllratio_to_factor[] = { - 00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35, - 00, - }; - - return pllratio_to_factor[get_hid1 () >> 28] * - (bab7xx_get_bus_freq () / 10); -} - -/*----------------------------------------------------------------------------*/ - -int checkcpu (void) -{ - uint pvr = get_pvr (); - - printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF); - printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000, - bab7xx_get_bus_freq () / 1000000); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int checkboard (void) -{ -#ifdef CFG_ADDRESS_MAP_A - puts ("Board: ELTEC BAB7xx PReP\n"); -#else - puts ("Board: ELTEC BAB7xx CHRP\n"); -#endif - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int checkflash (void) -{ - /* TODO: XXX XXX XXX */ - printf ("2 MB ## Test not implemented yet ##\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - - -static unsigned int mpc106_read_cfg_dword (unsigned int reg) -{ - unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC); - - out32r (MPC106_REG_ADDR, reg_addr); - - return (in32r (MPC106_REG_DATA | (reg & 0x3))); -} - -/* ------------------------------------------------------------------------- */ - -long int dram_size (int board_type) -{ - /* No actual initialisation to do - done when setting up - * PICRs MCCRs ME/SARs etc in ram_init.S. - */ - - register unsigned long i, msar1, mear1, memSize; - -#if defined(CFG_MEMTEST) - register unsigned long reg; - - printf ("Testing DRAM\n"); - - /* write each mem addr with it's address */ - for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) - *reg = reg; - - for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) { - if (*reg != reg) - return -1; - } -#endif - - /* - * Since MPC106 memory controller chip has already been set to - * control all memory, just read and interpret its memory boundery register. - */ - memSize = 0; - msar1 = mpc106_read_cfg_dword (MPC106_MSAR1); - mear1 = mpc106_read_cfg_dword (MPC106_MEAR1); - i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf; - - do { - if (i & 0x01) /* is bank enabled ? */ - memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1; - msar1 >>= 8; - mear1 >>= 8; - i >>= 1; - } while (i); - - return (memSize * 0x100000); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - return dram_size (board_type); -} - -/* ------------------------------------------------------------------------- */ - -void after_reloc (ulong dest_addr) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* - * Jump to the main U-Boot board init code - */ - board_init_r ((gd_t *) gd, dest_addr); -} - -/* ------------------------------------------------------------------------- */ - -/* - * do_reset is done here because in this case it is board specific, since the - * 7xx CPUs can only be reset by external HW (the RTC in this case). - */ -void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) -{ -#if defined(CONFIG_RTC_MK48T59) - /* trigger watchdog immediately */ - rtc_set_watchdog (1, RTC_WD_RB_16TH); -#else -#error "You must define the macro CONFIG_RTC_MK48T59." -#endif -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) -/* - * Since the 7xx CPUs don't have an internal watchdog, this function is - * board specific. We use the RTC here. - */ -void watchdog_reset (void) -{ -#if defined(CONFIG_RTC_MK48T59) - /* we use a 32 sec watchdog timer */ - rtc_set_watchdog (8, RTC_WD_RB_4); -#else -#error "You must define the macro CONFIG_RTC_MK48T59." -#endif -} -#endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -extern GraphicDevice smi; - -void video_get_info_str (int line_number, char *info) -{ - /* init video info strings for graphic console */ - switch (line_number) { - case 1: - sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz", - (get_pvr () >> 8) & 0xFF, - get_pvr () & 0xFF, - bab7xx_get_gclk_freq () / 1000000, - bab7xx_get_bus_freq () / 1000000); - return; - case 2: - sprintf (info, - " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH", - dram_size (0) / 0x100000, flash_init () / 0x100000); - return; - case 3: - sprintf (info, " %s", smi.modeIdent); - return; - } - - /* no more info lines */ - *info = 0; - return; -} -#endif - -/*---------------------------------------------------------------------------*/ diff --git a/board/eltec/bab7xx/config.mk b/board/eltec/bab7xx/config.mk deleted file mode 100644 index aa463c5..0000000 --- a/board/eltec/bab7xx/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/eltec/bab7xx/dc_srom.c b/board/eltec/bab7xx/dc_srom.c deleted file mode 100644 index a44af6e..0000000 --- a/board/eltec/bab7xx/dc_srom.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * SRom I/O routines. - */ - -#include -#include -#include "srom.h" - -#define SROM_RD 0x00004000 /* Read from Boot ROM */ -#define SROM_WR 0x00002000 /* Write to Boot ROM */ -#define SROM_SR 0x00000800 /* Select Serial ROM when set */ - -#define DT_IN 0x00000004 /* Serial Data In */ -#define DT_CLK 0x00000002 /* Serial ROM Clock */ -#define DT_CS 0x00000001 /* Serial ROM Chip Select */ - -static u_int dc_srom_iobase; - -/*----------------------------------------------------------------------------*/ - -static int inl(u_long addr) -{ - return le32_to_cpu(*(volatile u_long *)(addr)); -} - -/*----------------------------------------------------------------------------*/ - -static void outl (int command, u_long addr) -{ - *(volatile u_long *)(addr) = cpu_to_le32(command); -} - -/*----------------------------------------------------------------------------*/ - -static void sendto_srom(u_int command, u_long addr) -{ - outl(command, addr); - udelay(1); - - return; -} - -/*----------------------------------------------------------------------------*/ - -static int getfrom_srom(u_long addr) -{ - s32 tmp; - - tmp = inl(addr); - udelay(1); - - return tmp; -} - -/*----------------------------------------------------------------------------*/ - -static void srom_latch (u_int command, u_long addr) -{ - sendto_srom (command, addr); - sendto_srom (command | DT_CLK, addr); - sendto_srom (command, addr); - - return; -} - -/*----------------------------------------------------------------------------*/ - -static void srom_command_rd (u_int command, u_long addr) -{ - srom_latch (command, addr); - srom_latch (command, addr); - srom_latch ((command & 0x0000ff00) | DT_CS, addr); - - return; -} - -/*----------------------------------------------------------------------------*/ - -static void srom_command_wr (u_int command, u_long addr) -{ - srom_latch (command, addr); - srom_latch ((command & 0x0000ff00) | DT_CS, addr); - srom_latch (command, addr); - - return; -} - -/*----------------------------------------------------------------------------*/ - -static void srom_address(u_int command, u_long addr, u_char offset) -{ - int i; - signed char a; - - a = (char)(offset << 2); - for (i=0; i<6; i++, a <<= 1) - { - srom_latch(command | ((a < 0) ? DT_IN : 0), addr); - } - udelay(1); - - i = (getfrom_srom(addr) >> 3) & 0x01; - - return; -} -/*----------------------------------------------------------------------------*/ - -static short srom_data_rd (u_int command, u_long addr) -{ - int i; - short word = 0; - s32 tmp; - - for (i=0; i<16; i++) - { - sendto_srom(command | DT_CLK, addr); - tmp = getfrom_srom(addr); - sendto_srom(command, addr); - - word = (word << 1) | ((tmp >> 3) & 0x01); - } - - sendto_srom(command & 0x0000ff00, addr); - - return word; -} - -/*----------------------------------------------------------------------------*/ - -static int srom_data_wr (u_int command, u_long addr, short val) -{ - int i; - u_long longVal; - s32 tmp; - - longVal = (u_long)(le16_to_cpu(val)); - - for (i=0; i<16; i++) - { - tmp = (longVal & 0x8000)>>13; - - sendto_srom (tmp | command, addr); - sendto_srom (tmp | command | DT_CLK, addr); - sendto_srom (tmp | command, addr); - - longVal = longVal<<1; - } - - sendto_srom(command & 0x0000ff00, addr); - sendto_srom(command, addr); - - tmp = 100; - do - { - if ((getfrom_srom(dc_srom_iobase) & 0x8) == 0x8) - break; - udelay(1000); - } while (--tmp); - - if (tmp == 0) - { - printf("Write DEC21143 SRom timed out !\n"); - return (-1); - } - - return 0; -} - - -/*----------------------------------------------------------------------------*/ -static short srom_rd (u_long addr, u_char offset) -{ - sendto_srom (SROM_RD | SROM_SR, addr); - srom_latch (SROM_RD | SROM_SR | DT_CS, addr); - - srom_command_rd (SROM_RD | SROM_SR | DT_IN | DT_CS, addr); - - srom_address (SROM_RD | SROM_SR | DT_CS, addr, offset); - - return srom_data_rd (SROM_RD | SROM_SR | DT_CS, addr); -} - -/*----------------------------------------------------------------------------*/ - -static void srom_wr_enable (u_long addr) -{ - int i; - - sendto_srom (SROM_WR | SROM_SR, addr); - srom_latch (SROM_WR | SROM_SR | DT_CS, addr); - - srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr); - srom_latch (SROM_WR | SROM_SR | DT_CS, addr); - srom_latch (SROM_WR | SROM_SR | DT_CS, addr); - - for (i=0; i<6; i++) - { - srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr); - } -} - -/*----------------------------------------------------------------------------*/ - -static int srom_wr (u_long addr, u_char offset, short val) -{ - srom_wr_enable (addr); - - sendto_srom (SROM_WR | SROM_SR, addr); - srom_latch (SROM_WR | SROM_SR | DT_CS, addr); - - srom_command_wr (SROM_WR | SROM_SR | DT_IN | DT_CS, addr); - - srom_address (SROM_WR | SROM_SR | DT_CS, addr, offset); - - return srom_data_wr (SROM_WR | SROM_SR | DT_CS, addr, val); -} - -/*----------------------------------------------------------------------------*/ -/* - * load data from the srom - */ -int dc_srom_load (u_short *dest) -{ - int offset; - short tmp; - - /* get srom iobase from local network controller */ - pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase); - dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK; - dc_srom_iobase = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase); - dc_srom_iobase += 0x48; /* io offset for srom access */ - - memset (dest, 0, 128); - for (offset=0; offset<64; offset++) - { - tmp = srom_rd (dc_srom_iobase, offset); - *dest++ = le16_to_cpu(tmp); - } - - return (0); -} - -/*----------------------------------------------------------------------------*/ - -/* - * store data into the srom - */ -int dc_srom_store (u_short *src) -{ - int offset; - - /* get srom iobase from local network controller */ - pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase); - dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK; - dc_srom_iobase = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase); - dc_srom_iobase += 0x48; /* io offset for srom access */ - - for (offset=0; offset<64; offset++) - { - if (srom_wr (dc_srom_iobase, offset, *src) == -1) - return (-1); - src++; - } - - return (0); -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/bab7xx/el_srom.c b/board/eltec/bab7xx/el_srom.c deleted file mode 100644 index 73f8066..0000000 --- a/board/eltec/bab7xx/el_srom.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "srom.h" - -/*----------------------------------------------------------------------------*/ -/* - * START sequence - * _ _________ - * SCLK _> \____ - * _ ____ - * SDIO _> \_________ - * : : : - */ -static void eepStart (void) -{ - out8(I2C_BUS_DAT, 0x60); /* SCLK = high SDIO = high */ - out8(I2C_BUS_DIR, 0x60); /* set output direction for SCLK/SDIO */ - udelay(10); - out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = low */ - udelay(10); - out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = low */ - udelay(10); -} - -/*----------------------------------------------------------------------------*/ -/* - * STOP sequence - * _______ - * SCLK _____/ - * _ ___ - * SDIO _>_______/ - * : : : - */ -static void eepStop (void) -{ - out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = low */ - out8(I2C_BUS_DIR, 0x60); /* set output direction for SCLK/SDIO */ - udelay(10); - out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = low */ - udelay(10); - out8(I2C_BUS_DAT, 0x60); /* SCLK = high SDIO = high */ - udelay(10); - out8(I2C_BUS_DIR, 0x00); /* reset to input direction */ -} - -/*----------------------------------------------------------------------------*/ -/* - * Read one byte from EEPROM - * ___ ___ ___ ___ ___ ___ ___ ___ - * SCLK ___/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \ - * _________________________________________________________________ - * SDIO > ^ ^ ^ ^ ^ ^ ^ ^ - * : : : : : : : : : : : : : : : : : - */ -static unsigned char eepReadByte (void) -{ - register unsigned char buf = 0x00; - register int i; - - out8(I2C_BUS_DIR, 0x40); - - for (i = 0; i < 8; i++) - { - out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */ - udelay(10); - out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = high */ - udelay(15); - buf <<= 1; - buf = (in8(I2C_BUS_DAT) & 0x20) ? (buf | 0x01) : (buf & 0xFE); - out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */ - udelay(10); - } - return(buf); -} - -/*----------------------------------------------------------------------------*/ -/* - * Write one byte to EEPROM - * ___ ___ ___ ___ ___ ___ ___ ___ - * SCLK __/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \__ - * _______ _______ _______ _______ _______ _______ _______ ________ - * SDIO X_______X_______X_______X_______X_______X_______X_______X________ - * : 7 : 6 : 5 : 4 : 3 : 2 : 1 : 0 - */ -static void eepWriteByte (register unsigned char buf) -{ - register int i; - - (buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = data */ - out8(I2C_BUS_DIR, 0x60); - - for (i = 7; i >= 0; i--) - { - (buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low SDIO=data */ - udelay(10); - (buf & 0x80) ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK=high SDIO=data */ - udelay(15); - (buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low SDIO=data */ - udelay(10); - buf <<= 1; - } -} - -/*----------------------------------------------------------------------------*/ -/* - * Read data acknowledge of EEPROM - * _______ - * SCLK ____/ \___ - * _______________ - * SDIO > - * : : ^ : - */ -static int eepReadAck (void) -{ - int retval; - - out8(I2C_BUS_DIR, 0x40); - out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */ - udelay(10); - out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = high */ - udelay(10); - retval = (in8(I2C_BUS_DAT) & 0x20) ? ERROR : 0; - udelay(10); - out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = high */ - udelay(10); - - return(retval); -} - -/*----------------------------------------------------------------------------*/ -/* - * Write data acknowledge to EEPROM - * _______ - * SCLK ____/ \___ - * - * SDIO >_______________ - * : : : - */ -static void eepWriteAck (unsigned char ack) -{ - ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = ack */ - out8(I2C_BUS_DIR, 0x60); - udelay(10); - ack ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK = high SDIO = ack */ - udelay(15); - ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low SDIO = ack */ - udelay(10); -} - -/*----------------------------------------------------------------------------*/ -/* - * Read bytes from EEPROM - */ -int el_srom_load (addr, buf, cnt, device, block) -unsigned char addr; -unsigned char *buf; -int cnt; -unsigned char device; -unsigned char block; -{ - register int i; - - for (i=0;i>= 1; accu ^= f; - byte >>= 1; - } - } - return(accu); -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/bab7xx/flash.c b/board/eltec/bab7xx/flash.c deleted file mode 100644 index 442dd00..0000000 --- a/board/eltec/bab7xx/flash.c +++ /dev/null @@ -1,512 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC). - * fixed monitor protection part - * - * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage - * of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use - * any other. - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*flash command address offsets*/ - -#define ADDR0 (0x555) -#define ADDR1 (0x2AA) -#define ADDR3 (0x001) - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------------*/ - -unsigned long flash_init (void) -{ - unsigned long size1, size2; - int i; - - /* Init: no FLASHes known */ - for (i=0; iflash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - flash_init(); - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F016D: - printf ("AM29F016D (16 Mbit)\n"); - break; - case AMD_ID_F032B: - printf ("AM29F032B (32 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - } else { - printf (" Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------------*/ -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong vendor, devid; - ulong base = (ulong)addr; - volatile unsigned char *caddr = (unsigned char *)addr; - -#ifdef DEBUG - printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr); -#endif - - /* Write auto select command: read Manufacturer ID */ - caddr[0] = 0xF0; /* reset bank */ - udelay(10); - - eieio(); - caddr[0x555] = 0xAA; - udelay(10); - caddr[0x2AA] = 0x55; - udelay(10); - caddr[0x555] = 0x90; - - udelay(10); - - vendor = caddr[0]; - devid = caddr[1]; - -#ifdef DEBUG - printf("Manufacturer: 0x%lx\n", vendor); -#endif - - vendor &= 0xff; - devid &= 0xff; - - /* We accept only two AMD types */ - switch (vendor) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - switch (devid) { - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id |= AMD_ID_F040B; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_F016D: - info->flash_id |= AMD_ID_F016D; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_F032B: - info->flash_id |= AMD_ID_F032B; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - -#ifdef DEBUG - printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - caddr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - -/*----------------------------------------------------------------------------*/ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - int rc = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *)(info->start[sect]); - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - udelay(30000); /* wait 30 ms */ - } - else - addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return rc; -} - -/*----------------------------------------------------------------------------*/ -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------------*/ -/* Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *)dest) & - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/bab7xx/l2cache.c b/board/eltec/bab7xx/l2cache.c deleted file mode 100644 index 1e75377..0000000 --- a/board/eltec/bab7xx/l2cache.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if defined(CFG_L2_BAB7xx) - -#include -#include -#include - -/* defines L2CR register for MPC750 */ - -#define L2CR_E 0x80000000 -#define L2CR_256K 0x10000000 -#define L2CR_512K 0x20000000 -#define L2CR_1024K 0x30000000 -#define L2CR_I 0x00200000 -#define L2CR_SL 0x00008000 -#define L2CR_IP 0x00000001 - -/*----------------------------------------------------------------------------*/ - -static int dummy (int dummy) -{ - return (dummy+1); -} - -/*----------------------------------------------------------------------------*/ - -int l2_cache_enable (int l2control) -{ - if (l2control) /* BAB750 */ - { - mtspr(SPRN_L2CR, l2control); - mtspr(SPRN_L2CR, (l2control | L2CR_I)); - while (mfspr(SPRN_L2CR) & L2CR_IP) - ; - mtspr(SPRN_L2CR, (l2control | L2CR_E)); - return (0); - } - else /* BAB740 */ - { - int picr1, picr2, mask; - int picr2CacheSize, cacheSize; - int *d; - int devbusfn; - u32 reg32; - - devbusfn = pci_find_device(PCI_VENDOR_ID_MOTOROLA, - PCI_DEVICE_ID_MOTOROLA_MPC106, 0); - if (devbusfn == -1) - return (-1); - - pci_read_config_dword (devbusfn, PCI_PICR2, ®32); - reg32 &= ~PICR2_L2_EN; - pci_write_config_dword (devbusfn, PCI_PICR2, reg32); - - /* cache size */ - if (*(volatile unsigned char *) (CFG_ISA_IO + 0x220) & 0x04) - { - /* cache size is 512 KB */ - picr2CacheSize = PICR2_L2_SIZE_512K; - cacheSize = 0x80000; - } - else - { - /* cache size is 256 KB */ - picr2CacheSize = PICR2_L2_SIZE_256K; - cacheSize = 0x40000; - } - - /* setup PICR1 */ - mask = - ~(PICR1_CF_BREAD_WS(1) | - PICR1_CF_BREAD_WS(2) | - PICR1_CF_CBA(0xff) | - PICR1_CF_CACHE_1G | - PICR1_CF_DPARK | - PICR1_CF_APARK | - PICR1_CF_L2_CACHE_MASK); - - picr1 = - (PICR1_CF_CBA(0x3f) | - PICR1_CF_CACHE_1G | - PICR1_CF_APARK | - PICR1_CF_DPARK | - PICR1_CF_L2_COPY_BACK); /* PICR1_CF_L2_WRITE_THROUGH */ - - pci_read_config_dword (devbusfn, PCI_PICR1, ®32); - reg32 &= mask; - reg32 |= picr1; - pci_write_config_dword (devbusfn, PCI_PICR1, reg32); - - /* - * invalidate all L2 cache - */ - picr2 = - (PICR2_CF_INV_MODE | - PICR2_CF_HIT_HIGH | - PICR2_CF_MOD_HIGH | - PICR2_CF_L2_HIT_DELAY(1) | - PICR2_CF_APHASE_WS(1) | - picr2CacheSize); - - pci_write_config_dword (devbusfn, PCI_PICR2, picr2); - - /* - * dummy transactions - */ - for (d=0; d<(int *)(2*cacheSize); d++) - dummy(*d); - - pci_write_config_dword (devbusfn, PCI_PICR2, - (picr2 | PICR2_CF_FLUSH_L2)); - - /* setup PICR2 */ - picr2 = - (PICR2_CF_FAST_CASTOUT | - PICR2_CF_WDATA | - PICR2_CF_ADDR_ONLY_DISABLE | - PICR2_CF_HIT_HIGH | - PICR2_CF_MOD_HIGH | - PICR2_L2_UPDATE_EN | - PICR2_L2_EN | - PICR2_CF_APHASE_WS(1) | - PICR2_CF_DATA_RAM_PBURST | - PICR2_CF_L2_HIT_DELAY(1) | - PICR2_CF_SNOOP_WS(2) | - picr2CacheSize); - - pci_write_config_dword (devbusfn, PCI_PICR2, picr2); - } - return (0); -} - -/*----------------------------------------------------------------------------*/ - -#endif /* (CFG_L2_BAB7xx) */ diff --git a/board/eltec/bab7xx/misc.c b/board/eltec/bab7xx/misc.c deleted file mode 100644 index 6a24807..0000000 --- a/board/eltec/bab7xx/misc.c +++ /dev/null @@ -1,547 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* includes */ -#include -#include -#include -#include -#include -#include -#include "srom.h" - -/* imports */ -extern char console_buffer[CFG_CBSIZE]; -extern int l2_cache_enable (int l2control); -extern void *nvram_read (void *dest, const short src, size_t count); -extern void nvram_write (short dest, const void *src, size_t count); - -/* globals */ -unsigned int ata_reset_time = 60; -unsigned int scsi_reset_time = 10; -unsigned int eltec_board; - -/* BAB750 uses SYM53C875(default) and BAB740 uses SYM53C860 - * values fixed after board identification - */ -unsigned short scsi_dev_id = PCI_DEVICE_ID_NCR_53C875; -unsigned int scsi_max_scsi_id = 15; -unsigned char scsi_sym53c8xx_ccf = 0x13; - -/*----------------------------------------------------------------------------*/ -/* - * handle sroms on BAB740/750 - * fix ether address - * L2 cache initialization - * ide dma control - */ -int misc_init_r (void) -{ - revinfo eerev; - char *ptr; - u_int i, l, initSrom, copyNv; - char buf[256]; - char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, - 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 }; - pci_dev_t bdf; - - char sromSYM[] = { -#ifdef TULIP_BUG - /* 10BaseT, 100BaseTx no full duplex modes */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08, - 0x02, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00, - 0x88, 0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0xe8 -#endif - /* 10BaseT, 10BaseT-FD, 100BaseTx, 100BaseTx-FD */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08, - 0x04, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00, - 0x86, 0x02, 0x04, 0xaf, 0x08, 0xa5, 0x00, 0x88, - 0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61, 0x80, - 0x88, 0x04, 0x05, 0x27, 0x08, 0x25, 0x00, 0x61, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x77 - }; - - char sromMII[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x5b, 0x00, - 0x2e, 0x4d, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08, - 0x01, 0x95, 0x03, 0x00, 0x00, 0x04, 0x01, 0x08, - 0x00, 0x00, 0x02, 0x08, 0x02, 0x00, 0x00, 0x78, - 0xe0, 0x01, 0x00, 0x50, 0x00, 0x18, 0x80, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xde, 0x41 - }; - - /* - * Check/Remake revision info - */ - initSrom = 0; - copyNv = 0; - - /* read out current revision srom contens */ - el_srom_load (0x0000, (u_char*)&eerev, sizeof(revinfo), - SECOND_DEVICE, FIRST_BLOCK); - - /* read out current nvram shadow image */ - nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE); - - if (strcmp (eerev.magic, "ELTEC") != 0) - { - /* srom is not initialized -> create a default revision info */ - for (i = 0, ptr = (char *)&eerev; i < sizeof(revinfo); i++) - *ptr++ = 0x00; - strcpy(eerev.magic, "ELTEC"); - eerev.revrev[0] = 1; - eerev.revrev[1] = 0; - eerev.size = 0x00E0; - eerev.category[0] = 0x01; - - /* node id from dead e128 as default */ - eerev.etheraddr[0] = 0x00; - eerev.etheraddr[1] = 0x00; - eerev.etheraddr[2] = 0x5B; - eerev.etheraddr[3] = 0x00; - eerev.etheraddr[4] = 0x2E; - eerev.etheraddr[5] = 0x4D; - - /* cache config word for bab750 */ - *(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH; - - initSrom = 1; /* force dialog */ - copyNv = 1; /* copy to nvram */ - } - - if ((copyNv == 0) && (el_srom_checksum((u_char*)&eerev, CFG_SROM_SIZE) != - el_srom_checksum((u_char*)buf, CFG_SROM_SIZE))) - { - printf ("Invalid revision info copy in nvram !\n"); - printf ("Press key:\n to copy current revision info to nvram.\n"); - printf (" to reenter revision info.\n"); - printf ("=> "); - if (0 != readline (NULL)) - { - switch ((char)toupper(console_buffer[0])) - { - case 'C': - copyNv = 1; - break; - case 'R': - copyNv = 1; - initSrom = 1; - break; - } - } - } - - if (initSrom) - { - memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */ - printf ("Enter revision number (0-9): %c ", eerev.revision[0][0]); - if (0 != readline (NULL)) - { - eerev.revision[0][0] = (char)toupper(console_buffer[0]); - memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */ - } - - printf ("Enter revision character (A-Z): %c ", eerev.revision[0][1]); - if (1 == readline (NULL)) - { - eerev.revision[0][1] = (char)toupper(console_buffer[0]); - } - - printf ("Enter board name (V-XXXX-XXXX): %s ", (char *)&eerev.board); - if (11 == readline (NULL)) - { - for (i=0; i<11; i++) - eerev.board[i] = (char)toupper(console_buffer[i]); - eerev.board[11] = '\0'; - } - - printf ("Enter serial number: %s ", (char *)&eerev.serial ); - if (6 == readline (NULL)) - { - for (i=0; i<6; i++) - eerev.serial[i] = console_buffer[i]; - eerev.serial[6] = '\0'; - } - - printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", - eerev.etheraddr[0], eerev.etheraddr[1], - eerev.etheraddr[2], eerev.etheraddr[3], - eerev.etheraddr[4], eerev.etheraddr[5]); - if (12 == readline (NULL)) - { - for (i=0; i<12; i+=2) - eerev.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] + - hex[toupper(console_buffer[i+1])-'0']); - } - - l = strlen ((char *)&eerev.text); - printf("Add to text section (max 64 chr): %s ", (char *)&eerev.text ); - if (0 != readline (NULL)) - { - for (i = l; i<63; i++) - eerev.text[i] = console_buffer[i-l]; - eerev.text[63] = '\0'; - } - - if (strstr ((char *)&eerev.board, "75") != NULL) - eltec_board = 750; - else - eltec_board = 740; - - if (eltec_board == 750) - { - if (CPU_TYPE == CPU_TYPE_750) - *(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH; - else - *(int*)&eerev.res[0] = CLK2P5TO1_1MB_PB_0P5DH; - - printf("Enter L2Cache config word with leading zero (HEX): %08X ", - *(int*)&eerev.res[0] ); - if (0 != readline (NULL)) - { - for (i=0; i<7; i+=2) - { - eerev.res[i>>1] = - (char)(16*hex[toupper(console_buffer[i])-'0'] + - hex[toupper(console_buffer[i+1])-'0']); - } - } - - /* prepare network eeprom */ - sromMII[20] = eerev.etheraddr[0]; - sromMII[21] = eerev.etheraddr[1]; - sromMII[22] = eerev.etheraddr[2]; - sromMII[23] = eerev.etheraddr[3]; - sromMII[24] = eerev.etheraddr[4]; - sromMII[25] = eerev.etheraddr[5]; - printf("\nSRom: Writing DEC21143 MII info .. "); - - if (dc_srom_store ((u_short *)sromMII) == -1) - printf("FAILED\n"); - else - printf("OK\n"); - } - - if (eltec_board == 740) - { - *(int *)&eerev.res[0] = 0; - sromSYM[20] = eerev.etheraddr[0]; - sromSYM[21] = eerev.etheraddr[1]; - sromSYM[22] = eerev.etheraddr[2]; - sromSYM[23] = eerev.etheraddr[3]; - sromSYM[24] = eerev.etheraddr[4]; - sromSYM[25] = eerev.etheraddr[5]; - printf("\nSRom: Writing DEC21143 SYM info .. "); - - if (dc_srom_store ((u_short *)sromSYM) == -1) - printf("FAILED\n"); - else - printf("OK\n"); - } - - /* update CRC */ - eerev.crc = el_srom_checksum((u_char *)eerev.board, eerev.size); - - /* write new values */ - printf("\nSRom: Writing revision info ...... "); - if (el_srom_store((BLOCK_SIZE-sizeof(revinfo)), (u_char *)&eerev, - sizeof(revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1) - printf("FAILED\n\n"); - else - printf("OK\n\n"); - - /* write new values as shadow image to nvram */ - nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE); - - } /*if (initSrom) */ - - /* copy current values as shadow image to nvram */ - if (initSrom == 0 && copyNv == 1) - nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE); - - /* update environment */ - sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", - eerev.etheraddr[0], eerev.etheraddr[1], - eerev.etheraddr[2], eerev.etheraddr[3], - eerev.etheraddr[4], eerev.etheraddr[5]); - setenv ("ethaddr", buf); - - /* print actual board identification */ - printf("Ident: %s Ser %s Rev %c%c\n", - eerev.board, (char *)&eerev.serial, - eerev.revision[0][0], eerev.revision[0][1]); - - /* global board ident */ - if (strstr ((char *)&eerev.board, "75") != NULL) - eltec_board = 750; - else - eltec_board = 740; - - /* - * L2 cache configuration - */ -#if defined(CFG_L2_BAB7xx) - ptr = getenv("l2cache"); - if (*ptr == '0') - { - printf ("Cache: L2 NOT activated on BAB%d\n", eltec_board); - } - else - { - printf ("Cache: L2 activated on BAB%d\n", eltec_board); - l2_cache_enable(*(int*)&eerev.res[0]); - } -#endif - - /* - * Reconfig ata reset timeout from environment - */ - if ((ptr = getenv ("ata_reset_time")) != NULL) - { - ata_reset_time = (int)simple_strtoul (ptr, NULL, 10); - } - else - { - sprintf (buf, "%d", ata_reset_time); - setenv ("ata_reset_time", buf); - } - - /* - * Reconfig scsi reset timeout from environment - */ - if ((ptr = getenv ("scsi_reset_time")) != NULL) - { - scsi_reset_time = (int)simple_strtoul (ptr, NULL, 10); - } - else - { - sprintf (buf, "%d", scsi_reset_time); - setenv ("scsi_reset_time", buf); - } - - - if ((bdf = pci_find_device(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, 0)) > 0) - { - if (pci_find_device(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, 0) > 0) - { - /* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 Mhz */ - scsi_dev_id = PCI_DEVICE_ID_NCR_53C860; - scsi_max_scsi_id = 7; - scsi_sym53c8xx_ccf = 0x15; - pci_write_config_byte (bdf, WINBOND_IDEIRCR, 0xb0); - } - - if ((ptr = getenv ("ide_dma_off")) != NULL) - { - u_long dma_off = simple_strtoul (ptr, NULL, 10); - /* - * setup user defined registers - * s.a. linux/drivers/ide/sl82c105.c - */ - bdf |= PCI_BDF(0,0,1); /* ide user reg at bdf function 1 */ - if (dma_off & 1) - { - pci_write_config_byte (bdf, 0x46, 1); - printf("IDE: DMA off flag set: Bus 0 : Dev 0\n"); - } - if (dma_off & 2) - { - pci_write_config_byte (bdf, 0x4a, 1); - printf("IDE: DMA off flag set: Bus 0 : Dev 1\n"); - } - if (dma_off & 4) - { - pci_write_config_byte (bdf, 0x4e, 1); - printf("IDE: DMA off flag set: Bus 1 : Dev 0\n"); - } - if (dma_off & 8) - { - pci_write_config_byte (bdf, 0x52, 1); - printf("IDE: DMA off flag set: Bus 1 : Dev 1\n"); - } - } - } - return (0); -} - -/*----------------------------------------------------------------------------*/ -/* - * BAB740 uses KENDIN KS8761 modem chip with not common setup values - */ -#ifdef CONFIG_TULIP_SELECT_MEDIA - -/* Register bits. - */ -#define BMR_SWR 0x00000001 /* Software Reset */ -#define STS_TS 0x00700000 /* Transmit Process State */ -#define STS_RS 0x000e0000 /* Receive Process State */ -#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ -#define OMR_SR 0x00000002 /* Start/Stop Receive */ -#define OMR_PS 0x00040000 /* Port Select */ -#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ -#define OMR_PM 0x00000080 /* Pass All Multicast */ -#define OMR_PR 0x00000040 /* Promiscuous Mode */ -#define OMR_PCS 0x00800000 /* PCS Function */ -#define OMR_TTM 0x00400000 /* Transmit Threshold Mode */ - -/* Ethernet chip registers. - */ -#define DE4X5_BMR 0x000 /* Bus Mode Register */ -#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ -#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ -#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */ -#define DE4X5_STS 0x028 /* Status Register */ -#define DE4X5_OMR 0x030 /* Operation Mode Register */ -#define DE4X5_SISR 0x060 /* SIA Status Register */ -#define DE4X5_SICR 0x068 /* SIA Connectivity Register */ -#define DE4X5_TXRX 0x070 /* SIA Transmit and Receive Register */ -#define DE4X5_GPPR 0x078 /* General Purpose Port register */ -#define DE4X5_APROM 0x048 /* Ethernet Address PROM */ - -/*----------------------------------------------------------------------------*/ - -static int INL(struct eth_device* dev, u_long addr) -{ - return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); -} - -/*----------------------------------------------------------------------------*/ - -static void OUTL(struct eth_device* dev, int command, u_long addr) -{ - *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); -} - -/*----------------------------------------------------------------------------*/ - -static void media_reg_init ( - struct eth_device* dev, - u32 csr14, - u32 csr15_dir, - u32 csr15_v0, - u32 csr15_v1, - u32 csr6 ) -{ - OUTL(dev, 0, DE4X5_OMR); /* CSR6 */ - udelay(10 * 1000); - OUTL(dev, 0, DE4X5_SICR); /* CSR13 */ - OUTL(dev, 1, DE4X5_SICR); /* CSR13 */ - udelay(10 * 1000); - OUTL(dev, csr14, DE4X5_TXRX); /* CSR14 */ - OUTL(dev, csr15_dir, DE4X5_GPPR); /* CSR15 */ - OUTL(dev, csr15_v0, DE4X5_GPPR); /* CSR15 */ - udelay(10 * 1000); - OUTL(dev, csr15_v1, DE4X5_GPPR); /* CSR15 */ - OUTL(dev, 0x00000301, DE4X5_SISR); /* CSR12 */ - OUTL(dev, csr6, DE4X5_OMR); /* CSR6 */ -} - -/*----------------------------------------------------------------------------*/ - -void dc21x4x_select_media(struct eth_device* dev) -{ - int i, status, ext; - extern unsigned int eltec_board; - - if (eltec_board == 740) - { - printf("SYM media select "); /* BAB740 */ - /* start autoneg. with 10 mbit */ - media_reg_init (dev, 0x3ffff, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400080); - ext = status = 0; - for (i=0; i<2000+ext; i++) - { - status = INL(dev, DE4X5_SISR); - udelay(1000); - if (status & 0x2000) ext = 2000; - if ((status & 0x7000) == 0x5000) break; - } - - /* autoneg. ok -> 100MB FD */ - if ((status & 0x0100f000) == 0x0100d000) - { - media_reg_init (dev, 0x37f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40280); - printf("100baseTx-FD\n"); - } - /* autoneg. ok -> 100MB HD */ - else if ((status & 0x0080f000) == 0x0080d000) - { - media_reg_init (dev, 0x17f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40080); - printf("100baseTx\n"); - } - /* autoneg. ok -> 10MB FD */ - else if ((status & 0x0040f000) == 0x0040d000) - { - media_reg_init (dev, 0x07f7f, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400280); - printf("10baseT-FD\n"); - } - /* autoneg. fail -> 10MB HD */ - else - { - media_reg_init (dev, 0x7f7f, 0x08af0008, 0x00a10008, 0x00a50008, - (OMR_SDP | OMR_TTM | OMR_PM)); - printf("10baseT\n"); - } - } - else - { - printf("MII media selected\n"); /* BAB750 */ - OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); /* CSR6 */ - } -} -#endif /* CONFIG_TULIP_SELECT_MEDIA */ - -/*---------------------------------------------------------------------------*/ diff --git a/board/eltec/bab7xx/pci.c b/board/eltec/bab7xx/pci.c deleted file mode 100644 index edbd3dd..0000000 --- a/board/eltec/bab7xx/pci.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCI initialisation for the MPC10x. - */ - -#include -#include -#include - -#ifdef CONFIG_PCI - -struct pci_controller local_hose; - -void pci_init_board(void) -{ - struct pci_controller* hose = (struct pci_controller *)&local_hose; - u32 reg32; - u16 reg16; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - /* - * Attention: pci_hose_phys_to_bus() failes in address compare, - * so we need (CFG_PCI_MEMORY_SIZE-1) - */ - CFG_PCI_MEMORY_SIZE-1, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CFG_PCI_MEM_BUS, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - CFG_ISA_MEM_BUS, - CFG_ISA_MEM_PHYS, - CFG_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - CFG_PCI_IO_BUS, - CFG_PCI_IO_PHYS, - CFG_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - CFG_ISA_IO_BUS, - CFG_ISA_IO_PHYS, - CFG_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; - - pci_setup_indirect(hose, - MPC106_REG_ADDR, - MPC106_REG_DATA); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - - /* Initialises the MPC10x PCI Configuration regs. */ - pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR2, ®32); - reg32 |= PICR2_CF_SNOOP_WS(3) | - PICR2_CF_FLUSH_L2 | - PICR2_CF_L2_HIT_DELAY(3) | - PICR2_CF_APHASE_WS(3); - reg32 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN); - pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR2, reg32); - - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); - - /* Clear non-reserved bits in status register */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - - pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR1, ®32); - reg32 |= PICR1_CF_CBA(63) | - PICR1_CF_BREAD_WS(2) | - PICR1_MCP_EN | - PICR1_CF_DPARK | - PICR1_PROC_TYPE_604 | - PICR1_CF_LOOP_SNOOP | - PICR1_CF_APARK; - pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR1, reg32); -} - -#endif /* CONFIG_PCI */ diff --git a/board/eltec/bab7xx/srom.h b/board/eltec/bab7xx/srom.h deleted file mode 100644 index c18ab91..0000000 --- a/board/eltec/bab7xx/srom.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* common srom defs */ -#define FIRST_DEVICE 0x00 -#define SECOND_DEVICE 0x04 -#define FIRST_BLOCK 0x00 -#define SECOND_BLOCK 0x02 -#define BLOCK_SIZE 0x100 -#define ERROR (-1) - -#define CLK2P0TO1_1MB_PB_0P5DH 0x79000100 -#define CLK2P5TO1_1MB_PB_0P5DH 0x7B000100 - -#define CPU_TYPE_740 0x08 -#define CPU_TYPE_750 0x08 -#define CPU_TYPE ((get_pvr()>>16)&0xffff) - -#define ABS(x) ((x<0)?-x:x) -#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8) - -/* bab7xx ELTEC srom */ -#define I2C_BUS_DAT (CFG_ISA_IO + 0x220) -#define I2C_BUS_DIR (CFG_ISA_IO + 0x221) - -/* srom at mpc107 */ -#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */ -#define MPC107_I2CFDR (mpc107_eumb_addr + 0x3004) /* freq divider */ -#define MPC107_I2CCR (mpc107_eumb_addr + 0x3008) /* control */ -#define MPC107_I2CSR (mpc107_eumb_addr + 0x300c) /* status */ -#define MPC107_I2CDR (mpc107_eumb_addr + 0x3010) /* data */ -#define MPC107_I2C_TIMEOUT 10000000 - -/* i82559 */ -#define EE_ADDR_BITS 6 -#define EE_SIZE 0x40 /* 0x40 words */ -#define EE_CHECKSUM 0xBABA - -/* dc21143 */ -#define DEC_SROM_SIZE 128 - - -/* - * structure of revision srom - */ -typedef struct { - char magic[8]; /* 000 - Magic number */ - char revrev[2]; /* 008 - Revision of structure */ - unsigned short size; /* 00A - Size of CRC area */ - unsigned long crc; /* 00C - CRC */ - char board[16]; /* 010 - Board Revision information */ - char option[4][16]; /* 020 - Option Revision information */ - char serial[8]; /* 060 - Board serial number */ - char etheraddr[6]; /* 068 - Ethernet node addresse */ - char reserved[2]; /* 06E - Reserved */ - char revision[7][2]; /* 070 - Revision codes */ - char category[2]; /* 07E - Category codes */ - char text[64]; /* 080 - Text field */ - char res[64]; /* 0C0 - Reserved */ -} revinfo; - -unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size); -int el_srom_load (unsigned char addr, unsigned char *buf, int cnt, - unsigned char device, unsigned char block); -int el_srom_store (unsigned char addr, unsigned char *buf, int cnt, - unsigned char device, unsigned char block); - -int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider); -int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset); -int mpc107_i2c_write_byte (unsigned char device, unsigned char block, - unsigned char offset, unsigned char val); -int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt, - unsigned char device, unsigned char block); -int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt, - unsigned char device, unsigned char block); - -int dc_srom_load (unsigned short *dest); -int dc_srom_store (unsigned short *src); - -unsigned short eepro100_srom_checksum (unsigned short *sromdata); -void eepro100_srom_load (unsigned short *destination); -int eepro100_srom_store (unsigned short *source); diff --git a/board/eltec/bab7xx/u-boot.lds b/board/eltec/bab7xx/u-boot.lds deleted file mode 100644 index d89eb6c..0000000 --- a/board/eltec/bab7xx/u-boot.lds +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/74xx_7xx/start.o (.text) - -/* store the environment in a seperate sector in the boot flash */ -/* . = env_offset; */ -/* common/environment.o(.text) */ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/eltec/elppc/Makefile b/board/eltec/elppc/Makefile deleted file mode 100644 index 76b2cfe..0000000 --- a/board/eltec/elppc/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o - -SOBJS = asm_init.o - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/eltec/elppc/asm_init.S b/board/eltec/elppc/asm_init.S deleted file mode 100644 index 1b8d399..0000000 --- a/board/eltec/elppc/asm_init.S +++ /dev/null @@ -1,878 +0,0 @@ -/* - * (C) Copyright 2001 ELTEC Elektronik AG - * Frank Gottschling - * - * ELTEC ELPPC RAM initialization - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#include -#include - -.globl board_asm_init -board_asm_init: - -/* - * setup pointer to message block - */ - mflr r13 /* save away link register */ - bl get_lnk_reg /* r3=addr of next instruction */ - subi r4, r3, 8 /* r4=board_asm_init addr */ - addi r29, r4, (MessageBlock-board_asm_init) - -/* - * dcache_disable - */ - mfspr r3, HID0 - li r4, HID0_DCE - andc r3, r3, r4 - mr r2, r3 - ori r3, r3, HID0_DCI - sync - mtspr HID0, r3 - mtspr HID0, r2 - isync - sync -/* - * icache_disable - */ - mfspr r3, HID0 - li r4, 0 - ori r4, r4, HID0_ICE - andc r3, r3, r4 - sync - mtspr HID0, r3 -/* - * invalidate caches - */ - ori r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE) - or r4, r4, r3 - isync - mtspr HID0, r4 - andc r4, r4, r3 - isync - mtspr HID0, r4 - isync -/* - * icache_enable - */ - mfspr r3, HID0 - ori r3, r3, (HID0_ICE | HID0_ICFI) - sync - mtspr HID0, r3 - - -/* - * setup memory controller - */ - lis r1, MPC106_REG_ADDR@h - ori r1, r1, MPC106_REG_ADDR@l - lis r2, MPC106_REG_DATA@h - ori r2, r2, MPC106_REG_DATA@l - - /* Configure PICR1 */ - lis r3, MPC106_REG@h - ori r3, r3, PCI_PICR1 - stwbrx r3, 0, r1 - addis r3, r0, 0xFF14 - ori r3, r3, 0x1CC8 - eieio - stwbrx r3, 0, r2 - - /* Configure PICR2 */ - lis r3, MPC106_REG@h - ori r3, r3, PCI_PICR2 - stwbrx r3, 0, r1 - addis r3, r0, 0x0000 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - /* Configure EUMBAR */ - lis r3, MPC106_REG@h - ori r3, r3, 0x0078 /* offest of EUMBAR in PCI config space */ - stwbrx r3, 0, r1 - lis r3, MPC107_EUMB_ADDR@h - eieio - stwbrx r3, 0, r2 - - /* Configure Address Map B Option Reg */ - lis r3, MPC106_REG@h - ori r3, r3, 0x00e0 /* offest of AMBOR in PCI config space */ - stwbrx r3, 0, r1 - lis r3, 0 - eieio - stwbrx r3, 0, r2 - - /* Configure I2C Controller */ - lis r14, MPC107_I2C_ADDR@h /* base of I2C controller */ - ori r14, r14, MPC107_I2C_ADDR@l - lis r3, 0x2b10 /* I2C clock = 100MHz/1024 */ - stw r3, 4(r14) - li r3, 0 /* clear arbitration */ - eieio - stw r3, 12(r14) - - /* Configure MCCR1 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR1 - stwbrx r3, 0, r1 - addis r3, r0, 0x0660 /* don't set MEMGO now ! */ - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - /* Configure MCCR2 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR2 - stwbrx r3, 0, r1 - addis r3, r0, 0x0400 - ori r3, r3, 0x1800 - eieio - stwbrx r3, 0, r2 - - - /* Configure MCCR3 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR3 - stwbrx r3, 0, r1 - addis r3, r0, 0x0230 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - /* Configure MCCR4 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR4 - stwbrx r3, 0, r1 - addis r3, r0, 0x2532 - ori r3, r3, 0x2220 - eieio - stwbrx r3, 0, r2 - -/* - * configure memory interface (MICRs) - */ - addis r3, r0, 0x8000 /* ADDR_80 */ - ori r3, r3, 0x0080 /* SMEMADD1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0x4000 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_84 */ - ori r3, r3, 0x0084 /* SMEMADD2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0xFFFF - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_88 */ - ori r3, r3, 0x0088 /* EXTSMEM1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_8C */ - ori r3, r3, 0x008c /* EXTSMEM2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0303 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_90 */ - ori r3, r3, 0x0090 /* EMEMADD1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0x7F3F - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_94 */ - ori r3, r3, 0x0094 /* EMEMADD2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0xFFFF - ori r3, r3, 0xFFFF - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_98 */ - ori r3, r3, 0x0098 /* EXTEMEM1 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0000 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_9C */ - ori r3, r3, 0x009c /* EXTEMEM2 */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0303 - ori r3, r3, 0x0303 - eieio - stwbrx r3, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_A0 */ - ori r3, r3, 0x00a0 /* MEMBNKEN */ - stwbrx r3, 0, r1 - addis r3, r0, 0x0000 - ori r3, r3, 0x0003 - eieio - stwbrx r3, 0, r2 - -/* - * must wait at least 100us after HRESET to issue a MEMGO - */ - lis r0, 1 - mtctr r0 -memStartWait: - bdnz memStartWait - -/* - * enable RAM Operations through MCCR1 (MEMGO) - */ - lis r3, 0x8000 - ori r3, r3, 0x00f0 - stwbrx r3, r0, r1 - sync - lwbrx r3, 0, r2 - lis r0, 0x0008 - or r3, r0, r3 - stwbrx r3, 0, r2 - sync - -/* - * set LEDs first time - */ - li r3, 0x1 - lis r30, CFG_USR_LED_BASE@h - stb r3, 2(r30) - sync - -/* - * init COM1 for polled output - */ - lis r8, CFG_NS16550_COM1@h /* COM1 base address*/ - ori r8, r8, CFG_NS16550_COM1@l - li r9, 0x00 - stb r9, 1(r8) /* int disabled */ - eieio - li r9, 0x00 - stb r9, 4(r8) /* modem ctrl */ - eieio - li r9, 0x80 - stb r9, 3(r8) /* link ctrl */ - eieio - li r9, (CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE) - stb r9, 0(r8) /* baud rate (LSB)*/ - eieio - li r9, ((CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8) - stb r9, 1(r8) /* baud rate (MSB) */ - eieio - li r9, 0x07 - stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */ - eieio - li r9, 0x0b - stb r9, 4(r8) /* enable the receiver and transmitter (modem ctrl) */ - eieio -waitEmpty: - lbz r9, 5(r8) /* transmit empty */ - andi. r9, r9, 0x40 - beq waitEmpty - li r9, 0x47 - stb r9, 3(r8) /* send break, 8 data bits, 2 stop bit, no parity */ - eieio - - lis r0, 0x0001 - mtctr r0 -waitCOM1: - lwz r0, 5(r8) /* load from port for delay */ - bdnz waitCOM1 - -waitEmpty1: - lbz r9, 5(r8) /* transmit empty */ - andi. r9, r9, 0x40 - beq waitEmpty1 - li r9, 0x07 - stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */ - eieio - -/* - * intro message from message block - */ - addi r3, r29, (MnewLine-MessageBlock) - bl Printf - addi r3, r29, (MinitLogo-MessageBlock) - bl Printf - -/* - * memory cofiguration using SPD information stored on the SODIMMs - */ - addi r3, r29, (Mspd01-MessageBlock) - bl Printf - - li r17, 0 - - li r3, 0x0002 /* get RAM type from spd for bank0/1 */ - bl spdRead - - cmpi 0, 0, r3, -1 /* error ? */ - bne noSpdError - - addi r3, r29, (Mfail-MessageBlock) - bl Printf - - li r6, 0xe /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ - -noSpdError: - mr r15, r3 /* save r3 */ - - addi r3, r29, (Mok-MessageBlock) - bl Printf - - cmpli 0, 0, r15, 0x0004 /* SDRAM ? */ - beq isSDRAM - - addi r3, r29, (MramTyp-MessageBlock) - bl Printf - - li r6, 0xd /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ - -isSDRAM: - li r3, 0x0012 /* get supported CAS latencies from byte 18 */ - bl spdRead - mr r15, r3 - li r3, 0x09 - andi. r0, r15, 0x04 - bne maxCLis3 - li r3, 0x17 -maxCLis3: - andi. r0, r15, 0x02 - bne CL2 - - addi r3, r29, (MramTyp-MessageBlock) - bl Printf - - li r6, 0xc /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ -CL2: - bl spdRead - cmpli 0, 0, r3, 0xa1 /* cycle time must be 10ns max. */ - blt speedOk - - addi r3, r29, (MramTyp-MessageBlock) - bl Printf - - li r6, 0xb /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ -speedOk: - lis r20, 0x06e8 /* preset MCR1 value */ - - li r3, 0x0011 /* get number of internal banks from spd for bank0/1 */ - bl spdRead - - cmpli 0, 0, r3, 0x02 - beq SD_2B - cmpli 0, 0, r3, 0x04 - beq SD_4B -memConfErr: - addi r3, r29, (MramConfErr-MessageBlock) - bl Printf - - li r6, 0xa /* error codes in r6 and r7 */ - li r7, 0x0 - b toggleError /* fail - loop forever */ - -SD_2B: - li r3, 0x0003 /* get number of row bits from spd for bank0/1 */ - bl spdRead - cmpli 0, 0, r3, 0x0b - beq row11x2 - cmpli 0, 0, r3, 0x0c - beq row12x2or13x2 - cmpli 0, 0, r3, 0x0d - beq row12x2or13x2 - b memConfErr -SD_4B: - li r3, 0x0003 /* get number of row bits from spd for bank0/1 */ - bl spdRead - cmpli 0, 0, r3, 0x0b - beq row11x4or12x4 - cmpli 0, 0, r3, 0x0c - beq row11x4or12x4 - cmpli 0, 0, r3, 0x0d - beq row13x4 - b memConfErr -row12x2or13x2: - ori r20, r20, 0x05 - b row11x4or12x4 -row13x4: - ori r20, r20, 0x0a - b row11x4or12x4 -row11x2: - ori r20, r20, 0x0f -row11x4or12x4: - /* get the size of bank 0-1 */ - - li r3, 0x001f /* get bank size from spd for bank0/1 */ - bl spdRead - - rlwinm r16, r3, 2, 24, 29 /* calculate size in MByte (128 MB max.) */ - - li r3, 0x0005 /* get number of banks from spd for bank0/1 */ - bl spdRead - - cmpi 0, 0, r3, 2 /* 2 banks ? */ - bne SDRAMnobank1 - - mr r17, r16 - -SDRAMnobank1: - li r3, 0x000c /* get refresh from spd for bank0/1 */ - bl spdRead - andi. r3, r3, 0x007f /* mask selfrefresh bit */ - li r4, 0x1800 /* refesh cycle 1536 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0000 /* 15.6 us ? */ - beq writeRefresh - - li r4, 0x0c00 /* refesh cycle 768 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0002 /* 7.8 us ? */ - beq writeRefresh - - li r4, 0x3000 /* refesh cycle 3072 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0003 /* 31.3 us ? */ - beq writeRefresh - - li r4, 0x6000 /* refesh cycle 6144 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0004 /* 62.5 us ? */ - beq writeRefresh - - li r4, 0 - ori r4, r4, 0xc000 /* refesh cycle 8224 clocks left shifted 2 */ - cmpli 0, 0, r3, 0x0005 /* 125 us ? */ - beq writeRefresh - - b memConfErr - -writeRefresh: - lis r21, 0x0400 /* preset MCCR2 value */ - or r21, r21, r4 - - /* Overwrite MCCR1 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR1 - stwbrx r3, 0, r1 - eieio - stwbrx r20, 0, r2 - - /* Overwrite MCCR2 */ - lis r3, MPC106_REG@h - ori r3, r3, MPC106_MCCR2 - stwbrx r3, 0, r1 - eieio - stwbrx r21, 0, r2 - - /* set the memory boundary registers for bank 0-3 */ - li r20, 0 - lis r23, 0x0303 - lis r24, 0x0303 - subi r21, r16, 1 /* calculate end address bank0 */ - li r22, 1 - - cmpi 0, 0, r17, 0 /* bank1 present ? */ - beq nobank1 - - andi. r3, r16, 0x00ff /* calculate start address of bank1 */ - andi. r4, r16, 0x0300 - rlwinm r3, r3, 8, 16, 23 - or r20, r20, r3 - or r23, r23, r4 - - add r16, r16, r17 /* add to total memory size */ - - subi r3, r16, 1 /* calculate end address of bank1 */ - andi. r4, r3, 0x0300 - andi. r3, r3, 0x00ff - rlwinm r3, r3, 8, 16, 23 - or r21, r21, r3 - or r24, r24, r4 - - ori r22, r22, 2 /* enable bank1 */ - b bankOk -nobank1: - ori r23, r23, 0x0300 /* set bank1 start to unused area */ - ori r24, r24, 0x0300 /* set bank1 end to unused area */ -bankOk: - addi r3, r29, (Mactivate-MessageBlock) - bl Printf - mr r3, r16 - bl OutDec - addi r3, r29, (Mact0123e-MessageBlock) - bl Printf - -/* - * overwrite MSAR1, MEAR1, EMSAR1, and EMEAR1 - */ - addis r3, r0, 0x8000 /* ADDR_80 */ - ori r3, r3, 0x0080 /* MSAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r20, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_88 */ - ori r3, r3, 0x0088 /* EMSAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r23, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_90 */ - ori r3, r3, 0x0090 /* MEAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r21, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_98 */ - ori r3, r3, 0x0098 /* EMEAR1 */ - stwbrx r3, 0, r1 - eieio - stwbrx r24, 0, r2 - - addis r3, r0, 0x8000 /* ADDR_A0 */ - ori r3, r3, 0x00a0 /* MBER */ - stwbrx r3, 0, r1 - eieio - stwbrx r22, 0, r2 - -/* - * delay to let SDRAM go through several initialization/refresh cycles - */ - lis r3, 3 - mtctr r3 -memStartWait_1: - bdnz memStartWait_1 - eieio - -/* - * set LEDs end - */ - li r3, 0xf - lis r30, CFG_USR_LED_BASE@h - stb r3, 2(r30) - sync - - mtlr r13 - blr /* EXIT board_asm_init ... */ - -/*----------------------------------------------------------------------------*/ -/* - * print a message to COM1 in polling mode (r10=COM1 port, r3=(char*)string) - */ - -Printf: - lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CFG_NS16550_COM1@l -WaitChr: - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, WaitChr /* wait till empty */ - lbzx r0, r0, r3 /* get char */ - stb r0, 0(r10) /* write to transmit reg */ - eieio - addi r3, r3, 1 /* next char */ - lbzx r0, r0, r3 /* get char */ - cmpwi cr1, r0, 0 /* end of string ? */ - bne cr1, WaitChr - blr - -/* - * print a char to COM1 in polling mode (r10=COM1 port, r3=char) - */ -OutChr: - lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CFG_NS16550_COM1@l -OutChr1: - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutChr1 /* wait till empty */ - stb r3, 0(r10) /* write to transmit reg */ - eieio - blr - -/* - * print 8/4/2 digits hex value to COM1 in polling mode (r10=COM1 port, r3=val) - */ -OutHex2: - li r9, 4 /* shift reg for 2 digits */ - b OHstart -OutHex4: - li r9, 12 /* shift reg for 4 digits */ - b OHstart -OutHex: - li r9, 28 /* shift reg for 8 digits */ -OHstart: - lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CFG_NS16550_COM1@l -OutDig: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDig - sraw r0, r3, r9 - clrlwi r0, r0, 28 - cmpwi cr1, r0, 9 - ble cr1, digIsNum - addic r0, r0, 55 - b nextDig -digIsNum: - addic r0, r0, 48 -nextDig: - stb r0, 0(r10) /* write to transmit reg */ - eieio - addic. r9, r9, -4 - bge OutDig - blr - -/* - * print 3 digits hdec value to COM1 in polling mode - * (r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch) - */ -OutDec: - li r6, 10 - divwu r0, r3, r6 /* r0 = r3 / 10, r9 = r3 mod 10 */ - mullw r10, r0, r6 - subf r9, r10, r3 - mr r3, r0 - divwu r0, r3, r6 /* r0 = r3 / 10, r8 = r3 mod 10 */ - mullw r10, r0, r6 - subf r8, r10, r3 - mr r3, r0 - divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */ - mullw r10, r0, r6 - subf r7, r10, r3 - lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CFG_NS16550_COM1@l - or. r7, r7, r7 - bne noblank1 - li r3, 0x20 - b OutDec4 -noblank1: - addi r3, r7, 48 /* convert to ASCII */ -OutDec4: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec4 - stb r3, 0(r10) /* x00 to transmit */ - eieio - or. r7, r7, r8 - beq OutDec5 - addi r3, r8, 48 /* convert to ASCII */ -OutDec5: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec5 - stb r3, 0(r10) /* x0 to transmit */ - eieio - addi r3, r9, 48 /* convert to ASCII */ -OutDec6: - lbz r0, 0(r29) /* slow down dummy read */ - lbz r0, 5(r10) /* read link status */ - eieio - andi. r0, r0, 0x40 /* mask transmitter empty bit */ - beq cr0, OutDec6 - stb r3, 0(r10) /* x to transmit */ - eieio - blr - -/* - * hang endless loop - */ -toggleError: /* fail type in r6, r7=0xff, toggle LEDs */ - stb r7, 2(r30) /* r7 to LED */ - li r0, 0 - lis r9, 127 - ori r9, r9, 65535 -toggleError1: - addic r0, r0, 1 - cmpw cr1, r0, r9 - ble cr1, toggleError1 - stb r6, 2(r30) /* r6 to LED */ - li r0, 0 - lis r9, 127 - ori r9, r9, 65535 -toggleError2: - addic r0, r0, 1 - cmpw cr1, r0, r9 - ble cr1, toggleError2 - b toggleError - -/* - * routines to read from ram spd - */ -spdWaitIdle: - lis r0, 0x1 /* timeout for about 100us */ - mtctr r0 -iSpd: - lbz r10, 12(r14) - andi. r10, r10, 0x20 /* mask and test MBB */ - beq idle - bdnz iSpd - orc. r10, r0, r0 /* return -1 to caller */ -idle: - bclr 20, 0 /* return to caller */ - -waitSpd: - lis r0, 0x10 /* timeout for about 1.5ms */ - mtctr r0 -wSpd: - lbz r10, 12(r14) - andi. r10, r10, 0x82 - cmpli 0, 0, r10, 0x82 /* test MCF and MIF set */ - beq wend - bdnz wSpd - orc. r10, r0, r0 /* return -1 to caller */ - bclr 20, 0 /* return to caller */ - -wend: - li r10, 0 - stb r10, 12(r14) /* clear status */ - bclr 20, 0 /* return to caller */ - -/* - * spdread - * in: r3 adr to read - * out: r3 val or -1 for error - * uses r10, assumes that r14 points to I2C controller - */ -spdRead: - mfspr r25, 8 /* save link register */ - - bl spdWaitIdle - bne spdErr - - li r10, 0x80 /* start with MEN */ - stb r10, 8(r14) - eieio - - li r10, 0xb0 /* start as master */ - stb r10, 8(r14) - eieio - - li r10, 0xa0 /* write device 0xA0 */ - stb r10, 16(r14) - eieio - bl waitSpd - bne spdErr - - lbz r10, 12(r14) /* test ACK */ - andi. r10, r10, 0x01 - bne gotNoAck - - stb r3, 16(r14) /* data address */ - eieio - bl waitSpd - bne spdErr - - - li r10, 0xb4 /* switch to read - restart */ - stb r10, 8(r14) - eieio - - li r10, 0xa1 /* read device 0xA0 */ - stb r10, 16(r14) - eieio - bl waitSpd - bne spdErr - - li r10, 0xa8 /* no ACK */ - stb r10, 8(r14) - eieio - - lbz r10, 16(r14) /* trigger read next byte */ - eieio - bl waitSpd - bne spdErr - - li r10, 0x88 /* generate STOP condition */ - stb r10, 8(r14) - eieio - - lbz r3, 16(r14) /* return read byte */ - - mtspr 8, r25 /* restore link register */ - blr - -gotNoAck: - li r10, 0x80 /* generate STOP condition */ - stb r10, 8(r14) - eieio -spdErr: - orc r3, r0, r0 /* return -1 */ - mtspr 8, r25 /* restore link register */ - blr - -get_lnk_reg: - mflr r3 /* return link reg */ - blr - -MessageBlock: - -MinitLogo: - .ascii "\015\012*** ELTEC Elektronik, Mainz ***\015\012" - .ascii "\015\012Initialising RAM\015\012\000" -Mspd01: - .ascii " Reading SPD of SODIMM ...... \000" -MramTyp: - .ascii "\015\012\SDRAM with CL=2 at 100 MHz required!\015\012\000" -MramConfErr: - .ascii "\015\012\Unsupported SODIMM Configuration!\015\012\000" -Mactivate: - .ascii " Activating \000" -Mact0123e: - .ascii " MByte.\015\012\000" -Mok: - .ascii "OK \015\012\000" -Mfail: - .ascii "FAILED \015\012\000" -MnewLine: - .ascii "\015\012\000" - .align 4 diff --git a/board/eltec/elppc/config.mk b/board/eltec/elppc/config.mk deleted file mode 100644 index aa463c5..0000000 --- a/board/eltec/elppc/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/eltec/elppc/eepro100_srom.c b/board/eltec/elppc/eepro100_srom.c deleted file mode 100644 index f021c50..0000000 --- a/board/eltec/elppc/eepro100_srom.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Local network srom writing for first time run - */ - -/* includes */ -#include -#include -#include -#include "srom.h" - -extern int eepro100_write_eeprom (struct eth_device* dev, - int location, int addr_len, unsigned short data); - -/*----------------------------------------------------------------------------*/ - -unsigned short eepro100_srom_checksum (unsigned short *sromdata) -{ - unsigned short sum = 0; - unsigned int i; - - for (i = 0; i < (EE_SIZE-1); i++) - { - sum += sromdata[i]; - } - return (EE_CHECKSUM - sum); -} - -/*----------------------------------------------------------------------------*/ - -int eepro100_srom_store (unsigned short *source) -{ - int count; - struct eth_device onboard_dev; - - /* get onboard network iobase */ - pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0, - (unsigned int *)&onboard_dev.iobase); - onboard_dev.iobase &= ~0xf; - - source[63] = eepro100_srom_checksum (source); - - for (count=0; count < EE_SIZE; count++) - { - if ( eepro100_write_eeprom ((struct eth_device*)&onboard_dev, - count, EE_ADDR_BITS, SROM_SHORT(source)) == -1 ) - return -1; - source++; - } - return 0; -} - -/*----------------------------------------------------------------------------*/ - -#ifdef EEPRO100_SROM_CHECK - -extern int read_eeprom (struct eth_device* dev, int location, int addr_len); - -void eepro100_srom_load (unsigned short *destination) -{ - int count; - struct eth_device onboard_dev; -#ifdef DEBUG - int lr = 0; - printf ("eepro100_srom_download:\n"); -#endif - - /* get onboard network iobase */ - pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0, - &onboard_dev.iobase); - onboard_dev.iobase &= ~0xf; - - memset (destination, 0x65, 128); - - for (count=0; count < 0x40; count++) - { - *destination++ = read_eeprom (struct eth_device*)&onboard_dev, - count, EE_ADDR_BITS); -#ifdef DEBUG - printf ("%04x ", *(destination - 1)); - if (lr++ == 7) - { - printf("\n"); - lr = 0; - } -#endif - } -} -#endif /* EEPRO100_SROM_CHECK */ - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c deleted file mode 100644 index a9dbeb2..0000000 --- a/board/eltec/elppc/elppc.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -int checkboard (void) -{ - puts ("Board: ELTEC PowerPC\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int checkflash (void) -{ - /* TODO */ - printf ("Test not implemented !\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -static unsigned int mpc106_read_cfg_dword (unsigned int reg) -{ - unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC); - - out32r (MPC106_REG_ADDR, reg_addr); - - return (in32r (MPC106_REG_DATA | (reg & 0x3))); -} - -/* ------------------------------------------------------------------------- */ - -long int dram_size (int board_type) -{ - /* - * No actual initialisation to do - done when setting up - * PICRs MCCRs ME/SARs etc in asm_init.S. - */ - - register unsigned long i, msar1, mear1, memSize; - -#if defined(CFG_MEMTEST) - register unsigned long reg; - - printf ("Testing DRAM\n"); - - /* write each mem addr with it's address */ - for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) - *reg = reg; - - for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) { - if (*reg != reg) - return -1; - } -#endif - - /* - * Since MPC107 memory controller chip has already been set to - * control all memory, just read and interpret its memory boundery register. - */ - memSize = 0; - msar1 = mpc106_read_cfg_dword (MPC106_MSAR1); - mear1 = mpc106_read_cfg_dword (MPC106_MEAR1); - i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf; - - do { - if (i & 0x01) /* is bank enabled ? */ - memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1; - msar1 >>= 8; - mear1 >>= 8; - i >>= 1; - } while (i); - - return (memSize * 0x100000); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - return dram_size (board_type); -} - -/* ------------------------------------------------------------------------- */ - -/* - * The BAB 911 can be reset by writing bit 0 of the Processor Initialization - * Register PI in the MPC 107 (at offset 0x41090 of the Embedded Utilities - * Memory Block). - */ -int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - out8 (MPC107_EUMB_PI, 1); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) - -/* - * Since the 7xx CPUs don't have an internal watchdog, this function is - * board specific. - */ -void watchdog_reset (void) -{ -} -#endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ - -void after_reloc (ulong dest_addr) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* - * Jump to the main U-Boot board init code - */ - board_init_r ((gd_t *)gd, dest_addr); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -extern GraphicDevice smi; - -void video_get_info_str (int line_number, char *info) -{ - /* init video info strings for graphic console */ - switch (line_number) { - case 1: - sprintf (info, " MPC7xx V%d.%d at %d / %d MHz", - (get_pvr () >> 8) & 0xFF, get_pvr () & 0xFF, 400, 100); - return; - case 2: - sprintf (info, " ELTEC ELPPC with %ld MB DRAM and %ld MB FLASH", - dram_size (0) / 0x100000, flash_init () / 0x100000); - return; - case 3: - sprintf (info, " %s", smi.modeIdent); - return; - } - - /* no more info lines */ - *info = 0; - return; -} -#endif diff --git a/board/eltec/elppc/flash.c b/board/eltec/elppc/flash.c deleted file mode 100644 index 442dd00..0000000 --- a/board/eltec/elppc/flash.c +++ /dev/null @@ -1,512 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC). - * fixed monitor protection part - * - * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage - * of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use - * any other. - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*flash command address offsets*/ - -#define ADDR0 (0x555) -#define ADDR1 (0x2AA) -#define ADDR3 (0x001) - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------------*/ - -unsigned long flash_init (void) -{ - unsigned long size1, size2; - int i; - - /* Init: no FLASHes known */ - for (i=0; iflash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - flash_init(); - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F016D: - printf ("AM29F016D (16 Mbit)\n"); - break; - case AMD_ID_F032B: - printf ("AM29F032B (32 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - } else { - printf (" Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------------*/ -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong vendor, devid; - ulong base = (ulong)addr; - volatile unsigned char *caddr = (unsigned char *)addr; - -#ifdef DEBUG - printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr); -#endif - - /* Write auto select command: read Manufacturer ID */ - caddr[0] = 0xF0; /* reset bank */ - udelay(10); - - eieio(); - caddr[0x555] = 0xAA; - udelay(10); - caddr[0x2AA] = 0x55; - udelay(10); - caddr[0x555] = 0x90; - - udelay(10); - - vendor = caddr[0]; - devid = caddr[1]; - -#ifdef DEBUG - printf("Manufacturer: 0x%lx\n", vendor); -#endif - - vendor &= 0xff; - devid &= 0xff; - - /* We accept only two AMD types */ - switch (vendor) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - switch (devid) { - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id |= AMD_ID_F040B; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_F016D: - info->flash_id |= AMD_ID_F016D; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_F032B: - info->flash_id |= AMD_ID_F032B; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - -#ifdef DEBUG - printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - caddr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - -/*----------------------------------------------------------------------------*/ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - int rc = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *)(info->start[sect]); - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - udelay(30000); /* wait 30 ms */ - } - else - addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return rc; -} - -/*----------------------------------------------------------------------------*/ -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------------*/ -/* Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *)dest) & - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c deleted file mode 100644 index 5fb20ae..0000000 --- a/board/eltec/elppc/misc.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* includes */ -#include -#include -#include -#include -#include "srom.h" - -/* imports */ -extern char console_buffer[CFG_CBSIZE]; -extern int l2_cache_enable (int l2control); -extern int eepro100_write_eeprom (struct eth_device *dev, int location, - int addr_len, unsigned short data); -extern int read_eeprom (struct eth_device *dev, int location, int addr_len); - -/*----------------------------------------------------------------------------*/ -/* - * read/write to nvram is only byte access - */ -void *nvram_read (void *dest, const long src, size_t count) -{ - uchar *d = (uchar *) dest; - uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src); - - while (count--) - *d++ = *s++; - - return dest; -} - -void nvram_write (long dest, const void *src, size_t count) -{ - uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest); - uchar *s = (uchar *) src; - - while (count--) - *d++ = *s++; -} - -/*----------------------------------------------------------------------------*/ -/* - * handle sroms on ELPPC - * fix ether address - * set serial console as default - */ -int misc_init_r (void) -{ - revinfo eerev; - u_char *ptr; - u_int i, l, initSrom, copyNv; - char buf[256]; - char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, - 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 - }; - - /* Clock setting for MPC107 i2c */ - mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b); - - /* Reset the EPIC */ - out32r (MPC107_EUMB_GCR, 0xa0000000); - while (in32r (MPC107_EUMB_GCR) & 0x80000000); /* Wait for reset to complete */ - out32r (MPC107_EUMB_GCR, 0x20000000); /* Put into into mixed mode */ - while (in32r (MPC107_EUMB_IACKR) != 0xff); /* Clear all pending interrupts */ - - /* - * Check/Remake revision info - */ - initSrom = 0; - copyNv = 0; - - /* read out current revision srom contens */ - mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo), - SECOND_DEVICE, FIRST_BLOCK); - - /* read out current nvram shadow image */ - nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE); - - if (strcmp (eerev.magic, "ELTEC") != 0) { - /* srom is not initialized -> create a default revision info */ - for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo); - i++) - *ptr++ = 0x00; - strcpy (eerev.magic, "ELTEC"); - eerev.revrev[0] = 1; - eerev.revrev[1] = 0; - eerev.size = 0x00E0; - eerev.category[0] = 0x01; - - /* node id from dead e128 as default */ - eerev.etheraddr[0] = 0x00; - eerev.etheraddr[1] = 0x00; - eerev.etheraddr[2] = 0x5B; - eerev.etheraddr[3] = 0x00; - eerev.etheraddr[4] = 0x2E; - eerev.etheraddr[5] = 0x4D; - - /* cache config word for ELPPC */ - *(int *) &eerev.res[0] = 0; - - initSrom = 1; /* force dialog */ - copyNv = 1; /* copy to nvram */ - } - - if ((copyNv == 0) - && (el_srom_checksum ((u_char *) & eerev, CFG_SROM_SIZE) != - el_srom_checksum ((u_char *) buf, CFG_SROM_SIZE))) { - printf ("Invalid revision info copy in nvram !\n"); - printf ("Press key:\n to copy current revision info to nvram.\n"); - printf (" to reenter revision info.\n"); - printf ("=> "); - if (0 != readline (NULL)) { - switch ((char) toupper (console_buffer[0])) { - case 'C': - copyNv = 1; - break; - case 'R': - copyNv = 1; - initSrom = 1; - break; - } - } - } - - if (initSrom) { - memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */ - printf ("Enter revision number (0-9): %c ", - eerev.revision[0][0]); - if (0 != readline (NULL)) { - eerev.revision[0][0] = - (char) toupper (console_buffer[0]); - memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */ - } - - printf ("Enter revision character (A-Z): %c ", - eerev.revision[0][1]); - if (1 == readline (NULL)) { - eerev.revision[0][1] = - (char) toupper (console_buffer[0]); - } - - printf ("Enter board name (V-XXXX-XXXX): %s ", - (char *) &eerev.board); - if (11 == readline (NULL)) { - for (i = 0; i < 11; i++) - eerev.board[i] = - (char) toupper (console_buffer[i]); - eerev.board[11] = '\0'; - } - - printf ("Enter serial number: %s ", (char *) &eerev.serial); - if (6 == readline (NULL)) { - for (i = 0; i < 6; i++) - eerev.serial[i] = console_buffer[i]; - eerev.serial[6] = '\0'; - } - - printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]); - if (12 == readline (NULL)) { - for (i = 0; i < 12; i += 2) - eerev.etheraddr[i >> 1] = - (char) (16 * - hex[toupper - (console_buffer[i]) - - '0'] + - hex[toupper - (console_buffer[i + 1]) - - '0']); - } - - l = strlen ((char *) &eerev.text); - printf ("Add to text section (max 64 chr): %s ", - (char *) &eerev.text); - if (0 != readline (NULL)) { - for (i = l; i < 63; i++) - eerev.text[i] = console_buffer[i - l]; - eerev.text[63] = '\0'; - } - - /* prepare network eeprom */ - memset (buf, 0, 128); - - buf[0] = eerev.etheraddr[1]; - buf[1] = eerev.etheraddr[0]; - buf[2] = eerev.etheraddr[3]; - buf[3] = eerev.etheraddr[2]; - buf[4] = eerev.etheraddr[5]; - buf[5] = eerev.etheraddr[4]; - - *(unsigned short *) &buf[20] = 0x48B2; - *(unsigned short *) &buf[22] = 0x0004; - *(unsigned short *) &buf[24] = 0x1433; - - printf ("\nSRom: Writing i82559 info ........ "); - if (eepro100_srom_store ((unsigned short *) buf) == -1) - printf ("FAILED\n"); - else - printf ("OK\n"); - - /* update CRC */ - eerev.crc = - el_srom_checksum ((u_char *) eerev.board, eerev.size); - - /* write new values */ - printf ("\nSRom: Writing revision info ...... "); - if (mpc107_srom_store - ((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev, - sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1) - printf ("FAILED\n\n"); - else - printf ("OK\n\n"); - - /* write new values as shadow image to nvram */ - nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev, - CFG_SROM_SIZE); - - } - - /*if (initSrom) */ - /* copy current values as shadow image to nvram */ - if (initSrom == 0 && copyNv == 1) - nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev, - CFG_SROM_SIZE); - - /* update environment */ - sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", - eerev.etheraddr[0], eerev.etheraddr[1], - eerev.etheraddr[2], eerev.etheraddr[3], - eerev.etheraddr[4], eerev.etheraddr[5]); - setenv ("ethaddr", buf); - - /* print actual board identification */ - printf ("Ident: %s Ser %s Rev %c%c\n", - eerev.board, (char *) &eerev.serial, - eerev.revision[0][0], eerev.revision[0][1]); - - return (0); -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/mpc107_i2c.c b/board/eltec/elppc/mpc107_i2c.c deleted file mode 100644 index ae6642e..0000000 --- a/board/eltec/elppc/mpc107_i2c.c +++ /dev/null @@ -1,320 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* includes */ -#include -#include "srom.h" - -/* locals */ -static unsigned long mpc107_eumb_addr = 0; - -/*----------------------------------------------------------------------------*/ - -/* - * calculate checksum for ELTEC revision srom - */ -unsigned long el_srom_checksum (ptr, size) -register unsigned char *ptr; -unsigned long size; -{ - u_long f, accu = 0; - u_int i; - u_char byte; - - for (; size; size--) - { - byte = *ptr++; - for (i = 8; i; i--) - { - f = ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0; - accu >>= 1; accu ^= f; - byte >>= 1; - } - } - return(accu); -} - -/*----------------------------------------------------------------------------*/ - -static int mpc107_i2c_wait ( unsigned long timeout ) -{ - unsigned long x; - - while (((x = in32r(MPC107_I2CSR)) & 0x82) != 0x82) - { - if (!timeout--) - return -1; - } - - if (x & 0x10) - { - return -1; - } - out32r(MPC107_I2CSR, 0); - - return 0; -} - -/*----------------------------------------------------------------------------*/ - -static int mpc107_i2c_wait_idle ( unsigned long timeout ) -{ - while (in32r(MPC107_I2CSR) & 0x20) - { - if (!timeout--) - return -1; - } - return 0; -} - - -/*----------------------------------------------------------------------------*/ - -int mpc107_i2c_read_byte ( - unsigned char device, - unsigned char block, - unsigned char offset ) -{ - unsigned long timeout = MPC107_I2C_TIMEOUT; - int data; - - if (!mpc107_eumb_addr) - return -6; - - mpc107_i2c_wait_idle (timeout); - - /* Start with MEN */ - out32r(MPC107_I2CCR, 0x80); - - /* Start as master */ - out32r(MPC107_I2CCR, 0xB0); - out32r(MPC107_I2CDR, (0xA0 | device | block)); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 1\n"); - return -2; - } - - if (in32r(MPC107_I2CSR)&0x1) - { - /* Generate STOP condition; device busy or not existing */ - out32r(MPC107_I2CCR, 0x80); - return -1; - } - - /* Data address */ - out32r(MPC107_I2CDR, offset); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 2\n"); - return -3; - } - - /* Switch to read - restart */ - out32r(MPC107_I2CCR, 0xB4); - out32r(MPC107_I2CDR, (0xA1 | device | block)); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 3\n"); - return -4; - } - - out32r(MPC107_I2CCR, 0xA8); /* no ACK */ - in32r(MPC107_I2CDR); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_read Error 4\n"); - return -5; - } - /* Generate STOP condition */ - out32r(MPC107_I2CCR, 0x88); - - /* read */ - data = in32r(MPC107_I2CDR); - - return (data); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_i2c_write_byte ( - unsigned char device, - unsigned char block, - unsigned char offset, - unsigned char val ) -{ - - unsigned long timeout = MPC107_I2C_TIMEOUT; - - if (!mpc107_eumb_addr) - return -6; - - mpc107_i2c_wait_idle(timeout); - - /* Start with MEN */ - out32r(MPC107_I2CCR, 0x80); - - /* Start as master */ - out32r(MPC107_I2CCR, 0xB0); - out32r(MPC107_I2CDR, (0xA0 | device | block)); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_write Error 1\n"); - return -1; - } - - /* Data address */ - out32r(MPC107_I2CDR, offset); - - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_write Error 2\n"); - return -1; - } - - /* Write */ - out32r(MPC107_I2CDR, val); - if (mpc107_i2c_wait(timeout) < 0) - { - printf("mpc107_i2c_write Error 3\n"); - return -1; - } - - /* Generate Stop Condition */ - out32r(MPC107_I2CCR, 0x80); - - /* Return ACK or no ACK */ - return (in32r(MPC107_I2CSR) & 0x01); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_srom_load ( - unsigned char addr, - unsigned char *pBuf, - int cnt, - unsigned char device, - unsigned char block ) -{ - register int i; - int val; - int timeout; - - for (i = 0; i < cnt; i++) - { - timeout=100; - do - { - val = mpc107_i2c_read_byte (device, block, addr); - if (val < -1) - { - printf("i2c_read_error %d at dev %x block %x addr %x\n", - val, device, block, addr); - return -1; - } - else if (timeout==0) - { - printf ("i2c_read_error: timeout at dev %x block %x addr %x\n", - device, block, addr); - return -1; - } - timeout--; - } while (val == -1); /* if no ack: try again! */ - - *pBuf++ = (unsigned char)val; - addr++; - - if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */ - { - if (block == FIRST_BLOCK) - block = SECOND_BLOCK; - else - { - printf ("ic2_read_error: read beyond 2. block !\n"); - return -1; - } - } - } - udelay(100000); - return (cnt); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_srom_store ( - unsigned char addr, - unsigned char *pBuf, - int cnt, - unsigned char device, - unsigned char block ) -{ - register int i; - - for (i = 0; i < cnt; i++) - { - while (mpc107_i2c_write_byte (device,block,addr,*pBuf) == 1); - addr++; - pBuf++; - - if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */ - { - if (block == FIRST_BLOCK) - block = SECOND_BLOCK; - else - { - printf ("ic2_write_error: write beyond 2. block !\n"); - return -1; - } - } - } - udelay(100000); - return(cnt); -} - -/*----------------------------------------------------------------------------*/ - -int mpc107_i2c_init ( unsigned long eumb_addr, unsigned long divider ) -{ - unsigned long x; - - if (eumb_addr) - mpc107_eumb_addr = eumb_addr; - else - return -1; - - /* Set I2C clock */ - x = in32r(MPC107_I2CFDR) & 0xffffff00; - out32r(MPC107_I2CFDR, (x | divider)); - - /* Clear arbitration */ - out32r(MPC107_I2CSR, 0); - - return mpc107_eumb_addr; -} - -/*----------------------------------------------------------------------------*/ diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c deleted file mode 100644 index 5b115ea..0000000 --- a/board/eltec/elppc/pci.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCI initialisation for the MPC10x. - */ - -#include -#include -#include - -#ifdef CONFIG_PCI - -struct pci_controller local_hose; - -void pci_init_board(void) -{ - struct pci_controller* hose = (struct pci_controller *)&local_hose; - u16 reg16; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CFG_PCI_MEM_BUS, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - CFG_ISA_MEM_BUS, - CFG_ISA_MEM_PHYS, - CFG_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - CFG_PCI_IO_BUS, - CFG_PCI_IO_PHYS, - CFG_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - CFG_ISA_IO_BUS, - CFG_ISA_IO_PHYS, - CFG_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; - - pci_setup_indirect(hose, - MPC106_REG_ADDR, - MPC106_REG_DATA); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - - /* Initialises the MPC10x PCI Configuration regs. */ - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); - - /* Clear non-reserved bits in status register */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); -} - -#endif /* CONFIG_PCI */ diff --git a/board/eltec/elppc/srom.h b/board/eltec/elppc/srom.h deleted file mode 100644 index c18ab91..0000000 --- a/board/eltec/elppc/srom.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* common srom defs */ -#define FIRST_DEVICE 0x00 -#define SECOND_DEVICE 0x04 -#define FIRST_BLOCK 0x00 -#define SECOND_BLOCK 0x02 -#define BLOCK_SIZE 0x100 -#define ERROR (-1) - -#define CLK2P0TO1_1MB_PB_0P5DH 0x79000100 -#define CLK2P5TO1_1MB_PB_0P5DH 0x7B000100 - -#define CPU_TYPE_740 0x08 -#define CPU_TYPE_750 0x08 -#define CPU_TYPE ((get_pvr()>>16)&0xffff) - -#define ABS(x) ((x<0)?-x:x) -#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8) - -/* bab7xx ELTEC srom */ -#define I2C_BUS_DAT (CFG_ISA_IO + 0x220) -#define I2C_BUS_DIR (CFG_ISA_IO + 0x221) - -/* srom at mpc107 */ -#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */ -#define MPC107_I2CFDR (mpc107_eumb_addr + 0x3004) /* freq divider */ -#define MPC107_I2CCR (mpc107_eumb_addr + 0x3008) /* control */ -#define MPC107_I2CSR (mpc107_eumb_addr + 0x300c) /* status */ -#define MPC107_I2CDR (mpc107_eumb_addr + 0x3010) /* data */ -#define MPC107_I2C_TIMEOUT 10000000 - -/* i82559 */ -#define EE_ADDR_BITS 6 -#define EE_SIZE 0x40 /* 0x40 words */ -#define EE_CHECKSUM 0xBABA - -/* dc21143 */ -#define DEC_SROM_SIZE 128 - - -/* - * structure of revision srom - */ -typedef struct { - char magic[8]; /* 000 - Magic number */ - char revrev[2]; /* 008 - Revision of structure */ - unsigned short size; /* 00A - Size of CRC area */ - unsigned long crc; /* 00C - CRC */ - char board[16]; /* 010 - Board Revision information */ - char option[4][16]; /* 020 - Option Revision information */ - char serial[8]; /* 060 - Board serial number */ - char etheraddr[6]; /* 068 - Ethernet node addresse */ - char reserved[2]; /* 06E - Reserved */ - char revision[7][2]; /* 070 - Revision codes */ - char category[2]; /* 07E - Category codes */ - char text[64]; /* 080 - Text field */ - char res[64]; /* 0C0 - Reserved */ -} revinfo; - -unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size); -int el_srom_load (unsigned char addr, unsigned char *buf, int cnt, - unsigned char device, unsigned char block); -int el_srom_store (unsigned char addr, unsigned char *buf, int cnt, - unsigned char device, unsigned char block); - -int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider); -int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset); -int mpc107_i2c_write_byte (unsigned char device, unsigned char block, - unsigned char offset, unsigned char val); -int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt, - unsigned char device, unsigned char block); -int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt, - unsigned char device, unsigned char block); - -int dc_srom_load (unsigned short *dest); -int dc_srom_store (unsigned short *src); - -unsigned short eepro100_srom_checksum (unsigned short *sromdata); -void eepro100_srom_load (unsigned short *destination); -int eepro100_srom_store (unsigned short *source); diff --git a/board/eltec/elppc/u-boot.lds b/board/eltec/elppc/u-boot.lds deleted file mode 100644 index d89eb6c..0000000 --- a/board/eltec/elppc/u-boot.lds +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/74xx_7xx/start.o (.text) - -/* store the environment in a seperate sector in the boot flash */ -/* . = env_offset; */ -/* common/environment.o(.text) */ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/eltec/mhpc/Makefile b/board/eltec/mhpc/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/eltec/mhpc/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/eltec/mhpc/config.mk b/board/eltec/mhpc/config.mk deleted file mode 100644 index 03934de..0000000 --- a/board/eltec/mhpc/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MHPC boards -# - -TEXT_BASE = 0xfe000000 -/*TEXT_BASE = 0x00200000 */ diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c deleted file mode 100644 index 4cc66a9..0000000 --- a/board/eltec/mhpc/flash.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE+monitor_flash_len-1, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F640J5 : - printf ("28F640J5 \n"); break; - default: printf ("Unknown Chip Type=0x%lXh\n", - info->flash_id & FLASH_TYPEMASK); break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW)0xAA00AA00; - addr[0x2AAA] = (FPW)0x55005500; - addr[0x5555] = (FPW)0x90009000; - - value = SWAP(addr[0]); - - switch (value) { - case (FPW)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW)0xFF00FF00; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = SWAP(addr[1]); /* device ID no swap !*/ - - switch (value) { - case (FPW)INTEL_ID_28F640J5 : - info->flash_id += FLASH_28F640J5 ; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW)0xFF00FF00; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rc = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *)(info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x50005000; /* clear status register */ - *addr = (FPW)0x20002000; /* erase setup */ - *addr = (FPW)0xD000D000; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW)0xB000B000; /* suspend erase */ - *addr = (FPW)0xFF00FF00; /* reset to read mode */ - rc = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW)0xFF00FF00; /* reset to read mode */ - printf (" done\n"); - } - } - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= port_width) { - data = 0; - for (i=0; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i CFG_FLASH_WRITE_TOUT) { - *addr = (FPW)0xFF00FF00; /* restore read mode */ - return (1); - } - } - - *addr = (FPW)0xFF00FF00; /* restore read mode */ - - return (0); -} diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c deleted file mode 100644 index 0ffbdf0..0000000 --- a/board/eltec/mhpc/mhpc.c +++ /dev/null @@ -1,483 +0,0 @@ -/* - * (C) Copyright 2001 - * ELTEC Elektronik AG - * Frank Gottschling - * - * Board specific routines for the miniHiPerCam - * - * - initialisation (eeprom) - * - memory controller - * - serial io initialisation - * - ethernet io initialisation - * - * ----------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include "mpc8xx.h" -#include - -/* imports from common/main.c */ -extern char console_buffer[CFG_CBSIZE]; - -extern void eeprom_init (void); -extern int eeprom_read (unsigned dev_addr, unsigned offset, - unsigned char *buffer, unsigned cnt); -extern int eeprom_write (unsigned dev_addr, unsigned offset, - unsigned char *buffer, unsigned cnt); - -/* globals */ -void *video_hw_init (void); -void video_set_lut (unsigned int index, /* color number */ - unsigned char r, /* red */ - unsigned char g, /* green */ - unsigned char b /* blue */ - ); - -GraphicDevice gdev; - -/* locals */ -static void video_circle (char *center, int radius, int color, int pitch); -static void video_test_image (void); -static void video_default_lut (unsigned int clut_type); - -/* revision info foer MHPC EEPROM offset 480 */ -typedef struct { - char board[12]; /* 000 - Board Revision information */ - char sensor; /* 012 - Sensor Type information */ - char serial[8]; /* 013 - Board serial number */ - char etheraddr[6]; /* 021 - Ethernet node addresse */ - char revision[2]; /* 027 - Revision code */ - char option[3]; /* 029 - resevered for options */ -} revinfo; - -/* ------------------------------------------------------------------------- */ - -static const unsigned int sdram_table[] = { - /* read single beat cycle */ - 0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00, - 0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35, - - /* read burst cycle */ - 0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00, - 0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* write single beat cycle */ - 0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* write burst cycle */ - 0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440, - 0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* periodic timer expired */ - 0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84, - 0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* exception */ - 0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04 -}; - -/* ------------------------------------------------------------------------- */ - -int board_early_init_f (void) -{ - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport); - - /* reset the port A s.a. cpm-routines */ - ip->iop_padat = 0x0000; - ip->iop_papar = 0x0000; - ip->iop_padir = 0x0800; - ip->iop_paodr = 0x0000; - - /* reset the port B for digital and LCD output */ - cp->cp_pbdat = 0x0300; - cp->cp_pbpar = 0x5001; - cp->cp_pbdir = 0x5301; - cp->cp_pbodr = 0x0000; - - /* reset the port C configured for SMC1 serial port and aqc. control */ - ip->iop_pcdat = 0x0800; - ip->iop_pcpar = 0x0000; - ip->iop_pcdir = 0x0e30; - ip->iop_pcso = 0x0000; - - /* Config port D for LCD output */ - ip->iop_pdpar = 0x1fff; - ip->iop_pddir = 0x1fff; - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity - */ -int checkboard (void) -{ - puts ("Board: ELTEC miniHiperCam\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r (void) -{ - revinfo mhpcRevInfo; - char nid[32]; - char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color", - "OMNIVISON OV7110 b&w", NULL - }; - char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, - 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 - }; - int i; - - /* check revision data */ - eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32); - - if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) { - printf ("Enter revision number (0-9): %c ", - mhpcRevInfo.revision[0]); - if (0 != readline (NULL)) { - mhpcRevInfo.revision[0] = - (char) toupper (console_buffer[0]); - } - - printf ("Enter revision character (A-Z): %c ", - mhpcRevInfo.revision[1]); - if (1 == readline (NULL)) { - mhpcRevInfo.revision[1] = - (char) toupper (console_buffer[0]); - } - - printf ("Enter board name (V-XXXX-XXXX): %s ", - (char *) &mhpcRevInfo.board); - if (11 == readline (NULL)) { - for (i = 0; i < 11; i++) { - mhpcRevInfo.board[i] = - (char) toupper (console_buffer[i]); - mhpcRevInfo.board[11] = '\0'; - } - } - - printf ("Supported sensor types:\n"); - i = 0; - do { - printf ("\n \'%d\' : %s\n", i, mhpcSensorTypes[i]); - } while (mhpcSensorTypes[++i] != NULL); - - do { - printf ("\nEnter sensor number (0-255): %d ", - (int) mhpcRevInfo.sensor); - if (0 != readline (NULL)) { - mhpcRevInfo.sensor = - (unsigned char) - simple_strtoul (console_buffer, NULL, - 10); - } - } while (mhpcRevInfo.sensor >= i); - - printf ("Enter serial number: %s ", - (char *) &mhpcRevInfo.serial); - if (6 == readline (NULL)) { - for (i = 0; i < 6; i++) { - mhpcRevInfo.serial[i] = console_buffer[i]; - } - mhpcRevInfo.serial[6] = '\0'; - } - - printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); - if (12 == readline (NULL)) { - for (i = 0; i < 12; i += 2) { - mhpcRevInfo.etheraddr[i >> 1] = - (char) (16 * - hex[toupper - (console_buffer[i]) - - '0'] + - hex[toupper - (console_buffer[i + 1]) - - '0']); - } - } - - /* setup new revision data */ - eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, - 32); - } - - /* set environment */ - sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x", - mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], - mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], - mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); - setenv ("ethaddr", nid); - - /* print actual board identification */ - printf ("Ident: %s %s Ser %s Rev %c%c\n", - mhpcRevInfo.board, - (mhpcRevInfo.sensor == 0 ? "color" : "b&w"), - (char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0], - mhpcRevInfo.revision[1]); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */ - memctl->memc_mptpr = MPTPR_PTP_DIV64; - memctl->memc_mar = 0x00008800; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - udelay (200); - - /* - * Map controller SDRAM bank 1 - */ - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002730; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (10000); - - /* leave place for framebuffers */ - return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE); -} - -/* ------------------------------------------------------------------------- */ - -static void video_circle (char *center, int radius, int color, int pitch) -{ - int x, y, d, dE, dSE; - - x = 0; - y = radius; - d = 1 - radius; - dE = 3; - dSE = -2 * radius + 5; - - *(center + x + y * pitch) = color; - *(center + y + x * pitch) = color; - *(center + y - x * pitch) = color; - *(center + x - y * pitch) = color; - *(center - x - y * pitch) = color; - *(center - y - x * pitch) = color; - *(center - y + x * pitch) = color; - *(center - x + y * pitch) = color; - while (y > x) { - if (d < 0) { - d += dE; - dE += 2; - dSE += 2; - x++; - } else { - d += dSE; - dE += 2; - dSE += 4; - x++; - y--; - } - *(center + x + y * pitch) = color; - *(center + y + x * pitch) = color; - *(center + y - x * pitch) = color; - *(center + x - y * pitch) = color; - *(center - x - y * pitch) = color; - *(center - y - x * pitch) = color; - *(center - y + x * pitch) = color; - *(center - x + y * pitch) = color; - } -} - -/* ------------------------------------------------------------------------- */ - -static void video_test_image (void) -{ - char *di; - int i, n; - - /* draw raster */ - for (i = 0; i < LCD_VIDEO_ROWS; i += 32) { - memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS), - LCD_VIDEO_FG, LCD_VIDEO_COLS); - for (n = i + 1; n < i + 32; n++) - memset ((char *) (LCD_VIDEO_ADDR + - n * LCD_VIDEO_COLS), LCD_VIDEO_BG, - LCD_VIDEO_COLS); - } - - for (i = 0; i < LCD_VIDEO_COLS; i += 32) { - for (n = 0; n < LCD_VIDEO_ROWS; n++) - *(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) = - LCD_VIDEO_FG; - } - - /* draw gray bar */ - di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 + - 97 * LCD_VIDEO_COLS); - for (n = 0; n < 63; n++) { - for (i = 0; i < 256; i++) { - *di++ = (char) i; - *(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255; - } - di += LCD_VIDEO_COLS - 256; - } - - video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 + - LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2, - LCD_VIDEO_FG, LCD_VIDEO_COLS); -} - -/* ------------------------------------------------------------------------- */ - -static void video_default_lut (unsigned int clut_type) -{ - unsigned int i; - unsigned char RGB[] = { - 0x00, 0x00, 0x00, /* black */ - 0x80, 0x80, 0x80, /* gray */ - 0xff, 0x00, 0x00, /* red */ - 0x00, 0xff, 0x00, /* green */ - 0x00, 0x00, 0xff, /* blue */ - 0x00, 0xff, 0xff, /* cyan */ - 0xff, 0x00, 0xff, /* magenta */ - 0xff, 0xff, 0x00, /* yellow */ - 0x80, 0x00, 0x00, /* dark red */ - 0x00, 0x80, 0x00, /* dark green */ - 0x00, 0x00, 0x80, /* dark blue */ - 0x00, 0x80, 0x80, /* dark cyan */ - 0x80, 0x00, 0x80, /* dark magenta */ - 0x80, 0x80, 0x00, /* dark yellow */ - 0xc0, 0xc0, 0xc0, /* light gray */ - 0xff, 0xff, 0xff, /* white */ - }; - - switch (clut_type) { - case 1: - for (i = 0; i < 240; i++) - video_set_lut (i, i, i, i); - for (i = 0; i < 16; i++) - video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1], - RGB[i * 3 + 2]); - break; - default: - for (i = 0; i < 256; i++) - video_set_lut (i, i, i, i); - } -} - -/* ------------------------------------------------------------------------- */ - -void *video_hw_init (void) -{ - unsigned int clut = 0; - unsigned char *penv; - immap_t *immr = (immap_t *) CFG_IMMR; - - /* enable video only on CLUT value */ - if ((penv = (uchar *)getenv ("clut")) != NULL) - clut = (u_int) simple_strtoul ((char *)penv, NULL, 10); - else - return NULL; - - /* disable graphic before write LCD regs. */ - immr->im_lcd.lcd_lccr = 0x96000866; - - /* config LCD regs. */ - immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR; - immr->im_lcd.lcd_lchcr = 0x010a0093; - immr->im_lcd.lcd_lcvcr = 0x900f0024; - - printf ("Video: 640x480 8Bit Index Lut %s\n", - (clut == 1 ? "240/16 (gray/vga)" : "256(gray)")); - - video_default_lut (clut); - - /* clear framebuffer */ - memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG, - LCD_VIDEO_ROWS * LCD_VIDEO_COLS); - - /* enable graphic */ - immr->im_lcd.lcd_lccr = 0x96000867; - - /* fill in Graphic Device */ - gdev.frameAdrs = LCD_VIDEO_ADDR; - gdev.winSizeX = LCD_VIDEO_COLS; - gdev.winSizeY = LCD_VIDEO_ROWS; - gdev.gdfBytesPP = 1; - gdev.gdfIndex = GDF__8BIT_INDEX; - - if (clut > 1) - /* return Graphic Device for console */ - return (void *) &gdev; - else - /* just graphic enabled - draw something beautiful */ - video_test_image (); - - return NULL; /* this disabels cfb - console */ -} - -/* ------------------------------------------------------------------------- */ - -void video_set_lut (unsigned int index, - unsigned char r, unsigned char g, unsigned char b) -{ - unsigned int lum; - unsigned short *pLut = (unsigned short *) (CFG_IMMR + 0x0e00); - - /* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */ - /* y = 0.299*R + 0.587*G + 0.114*B */ - lum = (2990 * r + 5870 * g + 1140 * b) / 10000; - pLut[index] = - ((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum & - 0x3f); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds deleted file mode 100644 index 7099fc4..0000000 --- a/board/eltec/mhpc/u-boot.lds +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug deleted file mode 100644 index 3165d56..0000000 --- a/board/eltec/mhpc/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/emk/common/am79c874.c b/board/emk/common/am79c874.c deleted file mode 100644 index 552813e..0000000 --- a/board/emk/common/am79c874.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * (C) Copyright 2003 - * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/***************************************************************************** - * check fiber optic link present, and then copper link present. do auto switch - * between both - *****************************************************************************/ diff --git a/board/emk/common/flash.c b/board/emk/common/flash.c deleted file mode 100644 index d6161bf..0000000 --- a/board/emk/common/flash.c +++ /dev/null @@ -1,591 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined (CONFIG_TOP860) - typedef unsigned short FLASH_PORT_WIDTH; - typedef volatile unsigned short FLASH_PORT_WIDTHV; - #define FLASH_ID_MASK 0xFF - - #define FPW FLASH_PORT_WIDTH - #define FPWV FLASH_PORT_WIDTHV - - #define FLASH_CYCLE1 0x0555 - #define FLASH_CYCLE2 0x02aa - #define FLASH_ID1 0 - #define FLASH_ID2 1 - #define FLASH_ID3 0x0e - #define FLASH_ID4 0x0F -#endif - -#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200) - typedef unsigned char FLASH_PORT_WIDTH; - typedef volatile unsigned char FLASH_PORT_WIDTHV; - #define FLASH_ID_MASK 0xFF - - #define FPW FLASH_PORT_WIDTH - #define FPWV FLASH_PORT_WIDTHV - - #define FLASH_CYCLE1 0x0aaa - #define FLASH_CYCLE2 0x0555 - #define FLASH_ID1 0 - #define FLASH_ID2 2 - #define FLASH_ID3 0x1c - #define FLASH_ID4 0x1E -#endif - -#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200) - typedef unsigned char FLASH_PORT_WIDTH; - typedef volatile unsigned char FLASH_PORT_WIDTHV; - #define FLASH_ID_MASK 0xFF - - #define FPW FLASH_PORT_WIDTH - #define FPWV FLASH_PORT_WIDTHV - - #define FLASH_CYCLE1 0x0555 - #define FLASH_CYCLE2 0x02aa - #define FLASH_ID1 0 - #define FLASH_ID2 1 - #define FLASH_ID3 0x0E - #define FLASH_ID4 0x0F -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i = 0; - extern void flash_preinit(void); - extern void flash_afterinit(uint, ulong, ulong); - ulong flashbase = CFG_FLASH_BASE; - - flash_preinit(); - - /* There is only ONE FLASH device */ - memset(&flash_info[i], 0, sizeof(flash_info_t)); - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - size += flash_info[i].size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - - flash_afterinit(i, flash_info[i].start[0], flash_info[i].size); - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && - info->start[0] <= base && base <= info->start[0] + info->size - 1) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; -#if 0 - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; -#endif - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160T: - case FLASH_AM160B: - fmt = "29LV160%s (16 Mbit, %s)\n"; - break; - case FLASH_AMLV640U: - fmt = "29LV640M (64 Mbit)\n"; - break; - case FLASH_AMDLV065D: - fmt = "29LV065D (64 Mbit)\n"; - break; - case FLASH_AMLV256U: - fmt = "29LV256M (256 Mbit)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - ulong size; - int erased; - ulong *flash = (unsigned long *) info->start[i]; - - if ((i % 5) == 0) { - printf ("\n "); - } - - /* - * Check if whole sector is erased - */ - size = - (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for ( - flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) && erased; - flash++ - ) - erased = *flash == ~0x0UL; - - printf (" %08lX %s %s", - info->start[i], - erased ? "E": " ", - info->protect[i] ? "(RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - int i; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[FLASH_ID1] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - -#if 0 - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; -#endif - - default: - printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[FLASH_ID2]) { - - case (FPW)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - info->start[0] = (ulong)addr; - info->start[1] = (ulong)addr + 0x4000; - info->start[2] = (ulong)addr + 0x6000; - info->start[3] = (ulong)addr + 0x8000; - for (i = 4; i < info->sector_count; i++) - { - info->start[i] = (ulong)addr + 0x10000 * (i-3); - } - break; - - case (FPW)AMD_ID_LV065D: - info->flash_id += FLASH_AMDLV065D; - info->sector_count = 128; - info->size = 0x00800000; - for (i = 0; i < info->sector_count; i++) - { - info->start[i] = (ulong)addr + 0x10000 * i; - } - break; - - case (FPW)AMD_ID_MIRROR: - /* MIRROR BIT FLASH, read more ID bytes */ - if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 && - (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3) - { - info->flash_id += FLASH_AMLV640U; - info->sector_count = 128; - info->size = 0x00800000; - for (i = 0; i < info->sector_count; i++) - { - info->start[i] = (ulong)addr + 0x10000 * i; - } - break; - } - if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 && - (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3) - { - /* attention: only the first 16 MB will be used in u-boot */ - info->flash_id += FLASH_AMLV256U; - info->sector_count = 256; - info->size = 0x01000000; - for (i = 0; i < info->sector_count; i++) - { - info->start[i] = (ulong)addr + 0x10000 * i; - } - break; - } - - /* fall thru to here ! */ - default: - printf ("unknown AMD device=%x %x %x", - (FPW)addr[FLASH_ID2], - (FPW)addr[FLASH_ID3], - (FPW)addr[FLASH_ID4]); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0x800000; - break; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160B: - case FLASH_AMLV640U: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} diff --git a/board/emk/common/vpd.c b/board/emk/common/vpd.c deleted file mode 100644 index 8a3a12b..0000000 --- a/board/emk/common/vpd.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2003 - * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/***************************************************************************** - * read "factory" part of EEPROM and set some environment variables - *****************************************************************************/ -void read_factory_r (void) -{ - /* read 'factory' part of EEPROM */ - uchar buf[81]; - uchar *p; - uint length; - uint addr; - uint len; - - /* get length first */ - addr = CFG_FACT_OFFSET; - if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, 2)) { - bailout: - printf ("cannot read factory configuration\n"); - printf ("be sure to set ethaddr yourself!\n"); - return; - } - length = buf[0] + (buf[1] << 8); - addr += 2; - - /* sanity check */ - if (length < 20 || length > CFG_FACT_SIZE - 2) - goto bailout; - - /* read lines */ - while (length > 0) { - /* read one line */ - len = length > 80 ? 80 : length; - if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, len)) - goto bailout; - /* mark end of buffer */ - buf[len] = 0; - /* search end of line */ - for (p = buf; *p && *p != 0x0a; p++); - if (!*p) - goto bailout; - *p++ = 0; - /* advance to next line start */ - length -= p - buf; - addr += p - buf; - /*printf ("%s\n", buf); */ - /* search for our specific entry */ - if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) { - setenv ("ethaddr", (char *)(buf + 19)); - } else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) { - setenv ("serial#", (char *)(buf + 15)); - } else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) { - setenv ("board_id", (char *)(buf + 13)); - } - } -} diff --git a/board/emk/top5200/Makefile b/board/emk/top5200/Makefile deleted file mode 100644 index 986608b..0000000 --- a/board/emk/top5200/Makefile +++ /dev/null @@ -1,47 +0,0 @@ - -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/emk/top5200/config.mk b/board/emk/top5200/config.mk deleted file mode 100644 index 84131fe..0000000 --- a/board/emk/top5200/config.mk +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2003 -# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TOP5200 board, on optional MINI5200 and EVAL5200 boards -# -# allowed and functional TEXT_BASE values: -# -# 0xff000000 low boot at 0x00000100 (default board setting) -# 0xfff00000 high boot at 0xfff00100 (board needs modification) -# 0x00100000 RAM load and test -# - -TEXT_BASE = 0xff000000 -#TEXT_BASE = 0xfff00000 -#TEXT_BASE = 0x00100000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c deleted file mode 100644 index 4508438..0000000 --- a/board/emk/top5200/top5200.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/***************************************************************************** - * initialize SDRAM/DDRAM controller. - * TBD: get data from I2C EEPROM - *****************************************************************************/ -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT -#if 0 - ulong t; - ulong tap_del; -#endif - - #define MODE_EN 0x80000000 - #define SOFT_PRE 2 - #define SOFT_REF 4 - - /* configure SDRAM start/end */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE; - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN; - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE; -#ifdef CFG_DRAM_DDR - /* set extended mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE; -#endif - /* set mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400; - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE; - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF; - /* set mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE; - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL; - /* write default TAP delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24; - -#if 0 - for (tap_del = 0; tap_del < 32; tap_del++) - { - *(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24; - - printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG); - for (t = 0; t < 0x04000000; t+=4) - *(vu_long *) t = t; - printf ("Checking DRAM...\n"); - for (t = 0; t < 0x04000000; t+=4) - { - ulong rval = *(vu_long *) t; - if (rval != t) - { - printf ("mismatch at %x: ", t); - printf (" 1.read %x", rval); - printf (" 2.read %x", *(vu_long *) t); - printf (" 3.read %x", *(vu_long *) t); - break; - } - } - } -#endif -#endif /* CFG_RAMBOOT */ - - dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20); - - /* return total ram size */ - return dramsize; -} - -/***************************************************************************** - * print board identification - *****************************************************************************/ -int checkboard (void) -{ -#if defined (CONFIG_EVAL5200) - puts ("Board: EMK TOP5200 on EVAL5200\n"); -#else -#if defined (CONFIG_LITE5200) - puts ("Board: LITE5200\n"); -#else -#if defined (CONFIG_MINI5200) - puts ("Board: EMK TOP5200 on MINI5200\n"); -#else - puts ("Board: EMK TOP5200\n"); -#endif -#endif -#endif - return 0; -} - -/***************************************************************************** - * prepare for FLASH detection - *****************************************************************************/ -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -/***************************************************************************** - * finalize FLASH setup - *****************************************************************************/ -void flash_afterinit(uint bank, ulong start, ulong size) -{ - if (bank == 0) { /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = - *(vu_long *)MPC5XXX_CS0_START = START_REG(start); - *(vu_long *)MPC5XXX_BOOTCS_STOP = - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size); - } -} - -/***************************************************************************** - * otherinits after RAM is there and we are relocated to RAM - * note: though this is an int function, nobody cares for the result! - *****************************************************************************/ -int misc_init_r (void) -{ -#if !defined (CONFIG_LITE5200) - /* read 'factory' part of EEPROM */ - extern void read_factory_r (void); - read_factory_r (); -#endif - return (0); -} - -/***************************************************************************** - * initialize the PCI system - *****************************************************************************/ -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -/***************************************************************************** - * provide the IDE Reset Function - *****************************************************************************/ -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) - -#define GPIO_PSC1_4 0x01000000UL - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; - } -} -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/emk/top5200/u-boot.lds b/board/emk/top5200/u-boot.lds deleted file mode 100644 index f23432e..0000000 --- a/board/emk/top5200/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/emk/top860/Makefile b/board/emk/top860/Makefile deleted file mode 100644 index a74dd2f..0000000 --- a/board/emk/top860/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/emk/top860/config.mk b/board/emk/top860/config.mk deleted file mode 100644 index 7b940cb..0000000 --- a/board/emk/top860/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TOP860 board -# - -TEXT_BASE = 0x80000000 diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c deleted file mode 100644 index 84afaaa..0000000 --- a/board/emk/top860/top860.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * (C) Copyright 2003 - * EMK Elektronik GmbH - * Reinhard Meyer - * - * Board specific routines for the TOP860 - * - * - initialisation - * - interface to VPD data (mac address, clock speeds) - * - memory controller - * - serial io initialisation - * - ethernet io initialisation - * - * ----------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/***************************************************************************** - * UPM table for 60ns EDO RAM at 25 MHz bus/external clock - *****************************************************************************/ -static const uint edo_60ns_25MHz_tbl[] = { - -/* single read (offset 0x00 in upm ram) */ - 0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00, - 0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05, -/* burst read (offset 0x08 in upm ram) */ - 0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40, - 0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48, - 0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05, - 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, -/* single write (offset 0x18 in upm ram) */ - 0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07, - 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, -/* burst write (offset 0x20 in upm ram) */ - 0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c, - 0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c, - 0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05, - 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, -/* refresh (offset 0x30 in upm ram) */ - 0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04, - 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, - 0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05, -/* exception (offset 0x3C in upm ram) */ - 0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05, -}; - -/***************************************************************************** - * Print Board Identity - *****************************************************************************/ -int checkboard (void) -{ - puts ("Board:"CONFIG_IDENT_STRING"\n"); - return (0); -} - -/***************************************************************************** - * Initialize DRAM controller - *****************************************************************************/ -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* - * Only initialize memory controller when running from FLASH. - * When running from RAM, don't touch it. - */ - if ((ulong) initdram & 0xff000000) { - volatile uint *addr1, *addr2; - uint i, j; - - upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl, - sizeof (edo_60ns_25MHz_tbl) / sizeof (uint)); - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = 0x0ca20330; - memctl->memc_or2 = -CFG_DRAM_MAX | OR_CSNT_SAM; - memctl->memc_br2 = CFG_DRAM_BASE | BR_MS_UPMA | BR_V; - /* - * Do 8 read accesses to DRAM - */ - addr1 = (volatile uint *) 0; - addr2 = (volatile uint *) 0x00400000; - for (i = 0, j = 0; i < 8; i++) - j = addr1[0]; - - /* - * Now check whether we got 4MB or 16MB populated - */ - addr1[0] = 0x12345678; - addr1[1] = 0x9abcdef0; - addr2[0] = 0xfeedc0de; - addr2[1] = 0x47110815; - if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) { - /* only 4MB populated */ - memctl->memc_or2 = -(CFG_DRAM_MAX / 4) | OR_CSNT_SAM; - } - } - - return -(memctl->memc_or2 & 0xffff0000); -} - -/***************************************************************************** - * prepare for FLASH detection - *****************************************************************************/ -void flash_preinit(void) -{ -} - -/***************************************************************************** - * finalize FLASH setup - *****************************************************************************/ -void flash_afterinit(uint bank, ulong start, ulong size) -{ -} - -/***************************************************************************** - * otherinits after RAM is there and we are relocated to RAM - * note: though this is an int function, nobody cares for the result! - *****************************************************************************/ -int misc_init_r (void) -{ - /* read 'factory' part of EEPROM */ - extern void read_factory_r (void); - read_factory_r (); - - return (0); -} diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds deleted file mode 100644 index b3747e4..0000000 --- a/board/emk/top860/u-boot.lds +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/emk/top860/u-boot.lds.debug b/board/emk/top860/u-boot.lds.debug deleted file mode 100644 index 580575a..0000000 --- a/board/emk/top860/u-boot.lds.debug +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/ep7312/Makefile b/board/ep7312/Makefile deleted file mode 100644 index c53a3c7..0000000 --- a/board/ep7312/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := ep7312.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/ep7312/config.mk b/board/ep7312/config.mk deleted file mode 100644 index 0ae16a2..0000000 --- a/board/ep7312/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xc0f80000 diff --git a/board/ep7312/ep7312.c b/board/ep7312/ep7312.c deleted file mode 100644 index 11eab23..0000000 --- a/board/ep7312/ep7312.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Activate LED flasher */ - IO_LEDFLSH = 0x40; - - /* arch number MACH_TYPE_EDB7312 */ - gd->bd->bi_arch_number = MACH_TYPE_EDB7312; - - /* location of boot parameters */ - gd->bd->bi_boot_params = 0xc0020100; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} diff --git a/board/ep7312/flash.c b/board/ep7312/flash.c deleted file mode 100644 index 272a9e5..0000000 --- a/board/ep7312/flash.c +++ /dev/null @@ -1,341 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define FLASH_BANK_SIZE 0x1000000 -#define MAIN_SECT_SIZE 0x20000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf ("28F128J3 (128Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ - - while ((*addr & 0x80) != 0x80) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - - /* clear status register command */ - *addr = 0x50; - /* reset to read mode */ - *addr = 0xFF; - } - printf ("ok.\n"); - } - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest, val; - int rc = ERR_OK; - int flag; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* clear status register command */ - *addr = 0x50; - - /* program set-up command */ - *addr = 0x40; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - /* suspend program command */ - *addr = 0xB0; - goto outahere; - } - } - - if (val & 0x1A) { /* check for error */ - printf ("\nFlash write error %02x at address %08lx\n", - (int) val, (unsigned long) dest); - if (val & (1 << 3)) { - printf ("Voltage range error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if (val & (1 << 1)) { - printf ("Device protect error.\n"); - rc = ERR_PROTECTED; - goto outahere; - } - if (val & (1 << 4)) { - printf ("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - - outahere: - /* read array command */ - *addr = 0xFF; - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word (info, wp, data); -} diff --git a/board/ep7312/lowlevel_init.S b/board/ep7312/lowlevel_init.S deleted file mode 100644 index 5dadb31..0000000 --- a/board/ep7312/lowlevel_init.S +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Memory Setup stuff - taken from ??? - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* some parameters for the board */ - -SYSCON1: .long 0x80000100 -SYSCON2: .long 0x80001100 -SYSCON3: .long 0x80002200 -MEMCFG1: .long 0x80000180 -MEMCFG2: .long 0x800001C0 -SDCONF: .long 0x80002300 -SDRFPR: .long 0x80002340 - -syscon1_val: .long 0x00040100 -syscon2_val: .long 0x00000102 -syscon3_val: .long 0x0000020E -memcfg1_val: .long 0x1f101710 -memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits -memcfg2_val: .long 0x00001f13 @ upper 16 bits are reserved for CS7 + CS6 -sdrfpr_val: .long 0x00000240 -sdconf_val: .long 0x00000522 -/* setting up the memory */ - -.globl lowlevel_init -lowlevel_init: - /* - * SYSCON1-3 - */ - ldr r0, SYSCON1 - ldr r1, syscon1_val - str r1, [r0] - - ldr r0, SYSCON2 - ldr r1, syscon2_val - str r1, [r0] - - ldr r0, SYSCON3 - ldr r1, syscon3_val - str r1, [r0] - - /* - * MEMCFG1 - */ - ldr r0, MEMCFG1 - ldr r1, memcfg1_val - str r1, [r0] - - /* - * MEMCFG2 - */ - ldr r0, MEMCFG2 - ldr r2, [r0] - ldr r1, memcfg2_mask - bic r2, r2, r1 - ldr r1, memcfg2_val - orr r2, r2, r1 - str r2, [r0] - - /* - * SDRFPR,SDCONF - */ - ldr r0, SDCONF - ldr r1, sdconf_val - str r1, [r0] - - ldr r0, SDRFPR - ldr r1, sdrfpr_val - str r1, [r0] - - /* everything is fine now */ - mov pc, lr diff --git a/board/ep7312/u-boot.lds b/board/ep7312/u-boot.lds deleted file mode 100644 index 1122d75..0000000 --- a/board/ep7312/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm720t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/ep8248/Makefile b/board/ep8248/Makefile deleted file mode 100644 index 8b10993..0000000 --- a/board/ep8248/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/ep8248/config.mk b/board/ep8248/config.mk deleted file mode 100644 index eda523b..0000000 --- a/board/ep8248/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Modified by, Yuli Barcohen, Arabella Software Ltd. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# EP82xx series boards by Embedded Planet -# - -TEXT_BASE = 0xFFF00000 diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c deleted file mode 100644 index 69975ca..0000000 --- a/board/ep8248/ep8248.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Embedded Planet EP8248 boards. - * Tested on EP8248E. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */ - /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */ - /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -int board_early_init_f (void) -{ - vu_char *bcsr = (vu_char *)CFG_BCSR; - - bcsr[4] |= 0x30; /* Turn the LEDs off */ - -#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC) - bcsr[6] |= 0x10; -#endif -#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC) - bcsr[7] |= 0x10; -#endif - -#if CFG_FCC1 - bcsr[8] |= 0xC0; -#endif /* CFG_FCC1 */ -#if CFG_FCC2 - bcsr[8] |= 0x30; -#endif /* CFG_FCC2 */ - - return 0; -} - -long int initdram(int board_type) -{ - vu_char *bcsr = (vu_char *)CFG_BCSR; - long int msize = 16L << (bcsr[2] & 3); - -#ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; - uchar c = 0xFF; - uint psdmr = CFG_PSDMR; - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x30126745; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CFG_MPTPR; - - /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_or1 = CFG_SDRAM_OR; - memctl->memc_br1 = CFG_SDRAM_BR; - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ - *ramaddr = c; -#endif /* !CFG_RAMBOOT */ - - /* Return total 60x bus SDRAM size */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - vu_char *bcsr = (vu_char *)CFG_BCSR; - - puts("Board: "); - switch (bcsr[0]) { - case 0x0C: - printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]); - break; - default: - printf("unknown: ID=%02X\n", bcsr[0]); - } - - return 0; -} diff --git a/board/ep8248/u-boot.lds b/board/ep8248/u-boot.lds deleted file mode 100644 index 18c4b46..0000000 --- a/board/ep8248/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Yuli Barcohen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/ep8260/Makefile b/board/ep8260/Makefile deleted file mode 100644 index 477e5ee..0000000 --- a/board/ep8260/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o mii_phy.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/ep8260/config.mk b/board/ep8260/config.mk deleted file mode 100644 index eaf1560..0000000 --- a/board/ep8260/config.mk +++ /dev/null @@ -1,36 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# EP8260 boards -# - -# This should be equal to the CFG_FLASH_BASE define in config_ep8260.h -# for the "final" configuration, with U-Boot in flash, or the address -# in RAM where U-Boot is loaded at for debugging. -# -#TEXT_BASE = 0x00100000 -#TEXT_BASE = 0xFF000000 -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/ep8260/ep8260.c b/board/ep8260/ep8260.c deleted file mode 100644 index b9e1df4..0000000 --- a/board/ep8260/ep8260.c +++ /dev/null @@ -1,320 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Frank Panno , Delphin Technology AG - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "ep8260.h" -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* */ - /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK15 */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK16 */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Setup CS4 to enable the Board Control/Status registers. - * Otherwise the smcs won't work. -*/ -int board_early_init_f (void) -{ - volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE; - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - memctl->memc_br4 = CFG_BR4_PRELIM; - memctl->memc_or4 = CFG_OR4_PRELIM; - regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */ - regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */ - return 0; -} - -void reset_phy (void) -{ - volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE; - - regs->bcsr4 = 0xC0; -} - -/* - * Check Board Identity: - * I don' know, how the next board revisions will be coded. - * Thats why its a static interpretation ... -*/ - -int checkboard (void) -{ - volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE; - uint major = 0, minor = 0; - - switch (regs->bcsr0) { - case 0x02: - major = 1; - break; - case 0x03: - major = 1; - minor = 1; - break; - case 0x06: - major = 1; - minor = 3; - break; - default: - break; - } - printf ("Board: Embedded Planet EP8260, Revision %d.%d\n", - major, minor); - return 0; -} - - -/* ------------------------------------------------------------------------- */ - - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0; - volatile uchar *ramaddr = (uchar *) (CFG_SDRAM_BASE) + 0x110; - -/* - ulong psdmr = CFG_PSDMR; -#ifdef CFG_LSDRAM - ulong lsdmr = CFG_LSDMR; -#endif -*/ - long size = CFG_SDRAM0_SIZE; - int i; - - -/* -* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): -* -* "At system reset, initialization software must set up the -* programmable parameters in the memory controller banks registers -* (ORx, BRx, P/LSDMR). After all memory parameters are configured, -* system software should execute the following initialization sequence -* for each SDRAM device. -* -* 1. Issue a PRECHARGE-ALL-BANKS command -* 2. Issue eight CBR REFRESH commands -* 3. Issue a MODE-SET command to initialize the mode register -* -* The initial commands are executed by setting P/LSDMR[OP] and -* accessing the SDRAM with a single-byte transaction." -* -* The appropriate BRx/ORx registers have already been set when we -* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. -*/ - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - - memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - -#ifndef CFG_RAMBOOT -#ifdef CFG_LSDRAM - size += CFG_SDRAM1_SIZE; - ramaddr = (uchar *) (CFG_SDRAM1_BASE) + 0x8c; - memctl->memc_lsrt = CFG_LSRT; - - memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; -#endif /* CFG_LSDRAM */ -#endif /* CFG_RAMBOOT */ - return (size * 1024 * 1024); -} diff --git a/board/ep8260/ep8260.h b/board/ep8260/ep8260.h deleted file mode 100644 index 3032b14..0000000 --- a/board/ep8260/ep8260.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef __EP8260_H__ -#define __EP8260_H__ - -typedef struct tt_ep_regs { - volatile unsigned char bcsr0; - volatile unsigned char bcsr1; - volatile unsigned char bcsr2; - volatile unsigned char bcsr3; - volatile unsigned char bcsr4; - volatile unsigned char bcsr5; - volatile unsigned char bcsr6; - volatile unsigned char bcsr7; - volatile unsigned char bcsr8; - volatile unsigned char bcsr9; - volatile unsigned char bcsr10; - volatile unsigned char bcsr11; - volatile unsigned char bcsr12; - volatile unsigned char bcsr13; - volatile unsigned char bcsr14; - volatile unsigned char bcsr15; -} t_ep_regs; -typedef t_ep_regs *tp_ep_regs; - -#endif diff --git a/board/ep8260/flash.c b/board/ep8260/flash.c deleted file mode 100644 index 278d606..0000000 --- a/board/ep8260/flash.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Frank Panno , Delphin Technology AG - * - * Flash Routines for AMD device AM29DL323DB on the EP8260 board. - * - * This file is based on board/tqm8260/flash.c. - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define V_ULONG(a) (*(volatile unsigned long *)( a )) -#define V_BYTE(a) (*(volatile unsigned char *)( a )) - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ -void flash_reset(void) -{ - if( flash_info[0].flash_id != FLASH_UNKNOWN ) { - V_ULONG( flash_info[0].start[0] ) = 0x00F000F0; - V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0; - } -} - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size( ulong baseaddr, flash_info_t *info ) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - /* Write auto select command sequence and test FLASH answer */ - V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA; - V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055; - V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090; - V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA; - V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055; - V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090; - - flashtest_h = V_ULONG(baseaddr); /* manufacturer ID */ - flashtest_l = V_ULONG(baseaddr + 4); - - if ((int)flashtest_h == AMD_MANUFACT) { - info->flash_id = FLASH_MAN_AMD; - } else { - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - flashtest_h = V_ULONG(baseaddr + 8); /* device ID */ - flashtest_l = V_ULONG(baseaddr + 12); - if (flashtest_h != flashtest_l) { - info->flash_id = FLASH_UNKNOWN; - return(0); - } - - switch((int)flashtest_h) { - case AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; /* 4 * 4 MB = 16 MB */ - break; - case AMD_ID_LV640U: /* AMDLV640 and AMDLV641 have same ID */ - info->flash_id += FLASH_AMLV640U; - info->sector_count = 128; - info->size = 0x02000000; /* 4 * 8 MB = 32 MB */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return(0); /* no or unknown flash */ - } - - if(flashtest_h == AMD_ID_LV640U) { - /* set up sector start adress table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = baseaddr + (i * 0x00040000); - } else { - /* set up sector start adress table (bottom sector type) */ - for (i = 0; i < 8; i++) { - info->start[i] = baseaddr + (i * 0x00008000); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000; - } - } - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) || - (V_ULONG( info->start[i] + 20 ) & 0x00010001)) { - info->protect[i] = 1; /* D0 = 1 if protected */ - } else { - info->protect[i] = 0; - } - } - - flash_reset(); - return(info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i>20); - } - - /* - * protect monitor and environment sectors - */ - -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL323B: printf ("29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AMLV640U: printf ("29LV640U (64 M, uniform sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080; - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - V_ULONG( info->start[sect] ) = 0x00300030; - V_ULONG( info->start[sect] + 4 ) = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 || - (V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080) - { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - flash_reset (); - - printf (" done\n"); - return 0; -} - -static int write_dword (flash_info_t *, ulong, unsigned char *); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong dp; - static unsigned char bb[8]; - int i, l, rc, cc = cnt; - - dp = (addr & ~7); /* get lower dword aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - dp) != 0) { - for (i = 0; i < 8; i++) - bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++; - if ((rc = write_dword(info, dp, bb)) != 0) - { - return (rc); - } - dp += 8; - cc -= 8 - l; - } - - /* - * handle word aligned part - */ - while (cc >= 8) { - if ((rc = write_dword(info, dp, src)) != 0) { - return (rc); - } - dp += 8; - src += 8; - cc -= 8; - } - - if (cc <= 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - for (i = 0; i < 8; i++) { - bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i); - } - return (write_dword(info, dp, bb)); -} - -/*----------------------------------------------------------------------- - * Write a dword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata) -{ - ulong start; - ulong cl = 0, ch =0; - int flag, i; - - for (ch=0, i=0; i < 4; i++) - ch = (ch << 8) + *pdata++; /* high word */ - for (cl=0, i=0; i < 4; i++) - cl = (cl << 8) + *pdata++; /* low word */ - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & ch) != ch - ||(*((vu_long *)(dest + 4)) & cl) != cl) - { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0; - V_ULONG( dest ) = ch; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA; - V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055; - V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0; - V_ULONG( dest + 4 ) = cl; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) || - ((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/ep8260/mii_phy.c b/board/ep8260/mii_phy.c deleted file mode 100644 index 813f020..0000000 --- a/board/ep8260/mii_phy.c +++ /dev/null @@ -1,107 +0,0 @@ -#include -#include -#include "ep8260.h" - -#define MII_MDIO 0x01 -#define MII_MDCK 0x02 -#define MII_MDIR 0x04 - -void -mii_discover_phy(void) -{ - int known; - unsigned short phy_reg; - unsigned long phy_id; - - known = 0; - printf("Discovering phy @ 0: "); - phy_id = mii_phy_read(2) << 16; - phy_id |= mii_phy_read(3); - if ((phy_id & 0xFFFFFC00) == 0x00137800) { - printf("Level One "); - if ((phy_id & 0x000003F0) == 0xE0) { - printf("LXT971A Revision %d\n", (int)(phy_id & 0xF)); - known = 1; - } - else printf("unknown type\n"); - } - else printf("unknown OUI = 0x%08lX\n", phy_id); - - phy_reg = mii_phy_read(1); - if (!(phy_reg & 0x0004)) printf("Link is down\n"); - if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n"); - if (phy_reg & 0x0002) printf("Jabber condition detected\n"); - if (phy_reg & 0x0010) printf("Remote fault condition detected \n"); - - if (known) { - phy_reg = mii_phy_read(17); - if (phy_reg & 0x0400) - printf("Phy operating at %d MBit/s in %s-duplex mode\n", - phy_reg & 0x4000 ? 100 : 10, - phy_reg & 0x0200 ? "full" : "half"); - else - printf("bad link!!\n"); -/* -left off: no link, green 100MBit, yellow 10MBit -right off: no activity, green full-duplex, yellow half-duplex -*/ - mii_phy_write(20, 0x0452); - } -} - -unsigned short -mii_phy_read(unsigned short reg) -{ - int i; - unsigned short tmp, val = 0, adr = 0; - t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE; - - tmp = 0x6002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - regs->bcsr4 |= MII_MDIR; - for (i = 0; i < 16; i++) { - val <<= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK); - if (regs->bcsr4 & MII_MDIO) val |= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK); - } - return val; -} - -void -mii_phy_write(unsigned short reg, unsigned short val) -{ - int i; - unsigned short tmp, adr = 0; - t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE; - - tmp = 0x5002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (val & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - val <<= 1; - } -} diff --git a/board/ep8260/u-boot.lds b/board/ep8260/u-boot.lds deleted file mode 100644 index 4250e83..0000000 --- a/board/ep8260/u-boot.lds +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2001, 2002, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/opt/cross/lib); SEARCH_DIR(/opt/cross/powerpc-linux/lib); -/* SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); */ -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) -/* common/environment.o(.text) */ - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/eric/Makefile b/board/eric/Makefile deleted file mode 100644 index f55e7e2..0000000 --- a/board/eric/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/eric/config.mk b/board/eric/config.mk deleted file mode 100644 index dd0b412..0000000 --- a/board/eric/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFF80000 -TEXT_BASE = 0xFFFC0000 diff --git a/board/eric/eric.c b/board/eric/eric.c deleted file mode 100644 index 5413ae1..0000000 --- a/board/eric/eric.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "eric.h" -#include - -#define PPC405GP_GPIO0_OR 0xef600700 /* GPIO Output */ -#define PPC405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */ -#define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */ -#define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */ - -int board_early_init_f (void) -{ - - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the ERIC board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FLASH; active low; level sensitive - | IRQ 26 (EXT IRQ 1) PHY ; active low; level sensitive - | IRQ 27 (EXT IRQ 2) HOST FAIL, active low; level sensitive - | indicates NO Power or HOST RESET active - | check GPIO7 (HOST RESET#) and GPIO8 (NO Power#) - | for real IRQ source - | IRQ 28 (EXT IRQ 3) HOST; active high; level sensitive - | IRQ 29 (EXT IRQ 4) PCI INTC#; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive - | -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting - | PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR, - | else tristate) - | Note for ERIC board: - | An interrupt taken for the HOST (IRQ 28) indicates that - | the HOST wrote a "1" to one of the following locations - | - VGA CRT_GPIO0 (if R1216 is loaded) - | - VGA CRT_GPIO1 (if R1217 is loaded) - | - +-------------------------------------------------------------------------*/ - - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all SMI to be non-critical */ - mtdcr (uicpr, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */ - mtdcr (uictr, 0x10000000); /* set int trigger levels, UART0 is EDGE */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - - mtdcr (cntrl0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */ - - out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */ - out32 (PPC405GP_GPIO0_TCR, 0x7E400000); - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char *s = getenv ("serial#"); - char *e; - - puts ("Board: "); - - if (!s || strncmp (s, "ERIC", 9)) { - puts ("### No HW ID - assuming ERIC"); - } else { - for (e = s; *e; ++e) { - if (*e == ' ') - break; - } - - for (; s < e; ++s) { - putc (*s); - } - } - - - putc ('\n'); - - return (0); -} - - -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -/* - initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of - the necessary info for SDRAM controller configuration -*/ -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -long int initdram (int board_type) -{ -#ifndef CONFIG_ERIC - int i; - unsigned char datain[128]; - int TotalSize; -#endif - - -#ifdef CONFIG_ERIC - /* - * we have no EEPROM on ERIC - * so let init.S do the init job for SDRAM - * and simply return 32MByte here - */ - return (CFG_SDRAM_SIZE * 1024 * 1024); -#else - - /* Read Serial Presence Detect Information */ - for (i = 0; i < 128; i++) - datain[i] = 127; - i2c_send (SPD_EEPROM_ADDRESS, 0, 1, datain, 128); - printf ("\nReading DIMM...\n"); -#if 0 - for (i = 0; i < 128; i++) { - printf ("%d=0x%x ", i, datain[i]); - if (((i + 1) % 10) == 0) - printf ("\n"); - } - printf ("\n"); -#endif - - /*****************************/ - /* Retrieve interesting data */ - /*****************************/ - /* size of a SDRAM bank */ - /* Number of bytes per side / number of banks per side */ - if (datain[31] == 0x08) - TotalSize = 32; - else if (datain[31] == 0x10) - TotalSize = 64; - else { - printf ("IIC READ ERROR!!!\n"); - TotalSize = 32; - } - - /* single-sided DIMM or double-sided DIMM? */ - if (datain[5] != 1) { - /* double-sided DIMM => SDRAM banks 0..3 are valid */ - printf ("double-sided DIMM\n"); - TotalSize *= 2; - } - /* else single-sided DIMM => SDRAM bank 0 and bank 2 are valid */ - else { - printf ("single-sided DIMM\n"); - } - - - /* return size in Mb unit => *(1024*1024) */ - return (TotalSize * 1024 * 1024); -#endif -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: xxx MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/eric/eric.h b/board/eric/eric.h deleted file mode 100644 index b50d521..0000000 --- a/board/eric/eric.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/eric/flash.c b/board/eric/flash.c deleted file mode 100644 index c08a760..0000000 --- a/board/eric/flash.c +++ /dev/null @@ -1,1128 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -#ifdef CFG_FLASH_16BIT -#define FLASH_WORD_SIZE unsigned short -#define FLASH_ID_MASK 0xFFFF -#else -#define FLASH_WORD_SIZE unsigned long -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -/* stolen from esteem192e/flash.c */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); - -#ifndef CFG_FLASH_16BIT -static int write_word (flash_info_t *info, ulong dest, ulong data); -#else -static int write_short (flash_info_t *info, ulong dest, ushort data); -#endif -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i=0; iflash_id & FLASH_TYPEMASK) == FLASH_28F320J3A || - (info->flash_id & FLASH_TYPEMASK) == FLASH_28F640J3A || - (info->flash_id & FLASH_TYPEMASK) == FLASH_28F128J3A) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * info->size/info->sector_count); - } - } else if (info->flash_id & FLASH_BTYPE) { - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CFG_FLASH_16BIT - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00008000; - info->start[3] = base + 0x0000C000; - info->start[4] = base + 0x00010000; - info->start[5] = base + 0x00014000; - info->start[6] = base + 0x00018000; - info->start[7] = base + 0x0001C000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x000E0000; - } - } - else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } -#else - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000A000; - info->start[6] = base + 0x0000C000; - info->start[7] = base + 0x0000E000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00070000; - } - } - else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } -#endif - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CFG_FLASH_16BIT - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00014000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x0001C000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - - } else { - - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - - } else { - - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -#endif - } - - -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar botboot[]=", bottom boot sect)\n"; - uchar topboot[]=", top boot sector)\n"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - if (info->flash_id & 0x0001 ) { - boottype = botboot; - } else { - boottype = topboot; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype); - break; - case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype); - break; - case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype); - break; - case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype); - break; - case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype); - break; - case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype); - break; - case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype); - break; - -#if 0 /* enable when devices are available */ - - case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype); - break; - case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype); - break; -#endif - case FLASH_28F320J3A: printf ("INTEL28F320J3A (32 Mbit%s",boottype); - break; - case FLASH_28F640J3A: printf ("INTEL28F640J3A (64 Mbit%s",boottype); - break; - case FLASH_28F128J3A: printf ("INTEL28F128J3A (128 Mbit%s",boottype); - break; - - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) -{ - short i; - ulong base = (ulong)addr; - FLASH_WORD_SIZE value; - - /* Write auto select command: read Manufacturer ID */ - - -#ifndef CFG_FLASH_16BIT - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x00890089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x00900090; - if(addr[0x0000] != 0x00890089){ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x0089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x0090; - - if(addr[0x0000] != 0x0089){ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0090; -#endif - } - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - - } - - value = addr[1]; /* device ID */ - - switch (value) { - - case (AMD_ID_LV400T & FLASH_ID_MASK): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & FLASH_ID_MASK): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & FLASH_ID_MASK): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & FLASH_ID_MASK): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160T & FLASH_ID_MASK): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & FLASH_ID_MASK): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & FLASH_ID_MASK): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_LV320B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case (INTEL_ID_28F800B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800T; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F800B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F160B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160T; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F160B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 /* enable when devices are available */ - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ -#endif - case (INTEL_ID_28F320J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 32 MBit */ - case (INTEL_ID_28F640J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 64 MBit */ - case (INTEL_ID_28F128J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 128 MBit */ - - default: - /* FIXME*/ - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){ - *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - } - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - - volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); - int flag, prot, sect, l_sect, barf; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - ((info->flash_id > FLASH_AMD_COMP) && - ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){ - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - if(info->flash_id < FLASH_AMD_COMP) { -#ifndef CFG_FLASH_16BIT - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; -#endif - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); - while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != - (0x00800080&FLASH_ID_MASK) ) - { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - barf = 0; -#ifndef CFG_FLASH_16BIT - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00200020; - addr[0] = 0x00D000D0; - while(!(addr[0] & 0x00800080)); /* wait for error or finish */ - if( addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if( barf ) { - barf >>=16; - } else { - barf = addr[0] & 0x0000003A; - } - } -#else - addr = (vu_short*)(info->start[sect]); - addr[0] = 0x0020; - addr[0] = 0x00D0; - while(!(addr[0] & 0x0080)); /* wait for error or finish */ - if( addr[0] & 0x003A) /* check for error */ - barf = addr[0] & 0x003A; -#endif - if(barf) { - printf("\nFlash error in sector at %lx\n",(unsigned long)addr); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if((barf & 0x0030) == 0x0030) - printf("Command Sequence error.\n"); - if((barf & 0x0030) == 0x0020) - printf("Block Erase error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - rcode = 1; - } else printf("."); - l_sect = sect; - } - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - - } - - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ - -/*flash_info_t *addr2info (ulong addr) -{ - flash_info_t *info; - int i; - - for (i=0, info=&flash_info[0]; i= info->start[0]) && - (addr < (info->start[0] + info->size)) ) { - return (info); - } - } - - return (NULL); -} -*/ -/*----------------------------------------------------------------------- - * Copy memory to flash. - * Make sure all target addresses are within Flash bounds, - * and no protected sectors are hit. - * Returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - target range includes protected sectors - * 8 - target address not in Flash memory - */ - -/*int flash_write (uchar *src, ulong addr, ulong cnt) -{ - int i; - ulong end = addr + cnt - 1; - flash_info_t *info_first = addr2info (addr); - flash_info_t *info_last = addr2info (end ); - flash_info_t *info; - - if (cnt == 0) { - return (0); - } - - if (!info_first || !info_last) { - return (8); - } - - for (info = info_first; info <= info_last; ++info) { - ulong b_end = info->start[0] + info->size;*/ /* bank end addr */ -/* short s_end = info->sector_count - 1; - for (i=0; isector_count; ++i) { - ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; - - if ((end >= info->start[i]) && (addr < e_addr) && - (info->protect[i] != 0) ) { - return (4); - } - } - } - -*/ /* finally write data to flash */ -/* for (info = info_first; info <= info_last && cnt>0; ++info) { - ulong len; - - len = info->start[0] + info->size - addr; - if (len > cnt) - len = cnt; - if ((i = write_buff(info, src, addr, len)) != 0) { - return (i); - } - cnt -= len; - addr += len; - src += len; - } - return (0); -} -*/ -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ -#ifndef CFG_FLASH_16BIT - ulong cp, wp, data; - int l; -#else - ulong cp, wp; - ushort data; -#endif - int i, rc; - -#ifndef CFG_FLASH_16BIT - - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); - -#else - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start byte - */ - if (addr - wp) { - data = 0; - data = (data << 8) | *src++; - --cnt; - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ -/* l = 0; used for debuging */ - while (cnt >= 2) { - data = 0; - for (i=0; i<2; ++i) { - data = (data << 8) | *src++; - } - -/* if(!l){ - printf("%x",data); - l = 1; - } used for debuging */ - - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_short(info, wp, data)); - - -#endif -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifndef CFG_FLASH_16BIT -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start,barf; - int flag; - - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if(info->flash_id > FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - } else { - /* intel stuff */ - *addr = 0x00400040; - } - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - - if(info->flash_id > FLASH_AMD_COMP) { - - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - } else { - - while(!(addr[0] & 0x00800080)){ /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - - if( addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if( barf ) { - barf >>=16; - } else { - barf = addr[0] & 0x0000003A; - } - printf("\nFlash write error at address %lx\n",(unsigned long)dest); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if(barf & 0x0010) printf("Programming error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - return(2); - } - - - } - - return (0); - -} - -#else - -static int write_short (flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - ulong start,barf; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if(info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - } else { - /* intel stuff */ - *addr = 0x00D0; - *addr = 0x0040; - } - *((vu_short *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - - if(info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - } else { - /* intel stuff */ - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); - } - - if( addr[0] & 0x003A) { /* check for error */ - barf = addr[0] & 0x003A; - printf("\nFlash write error at address %lx\n",(unsigned long)dest); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if(barf & 0x0010) printf("Programming error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - return(2); - } - *addr = 0x00B0; - *addr = 0x0070; - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); - } - - *addr = 0x00FF; - - } - - return (0); - -} - - -#endif - -/*----------------------------------------------------------------------- - */ diff --git a/board/eric/init.S b/board/eric/init.S deleted file mode 100644 index 9d4e7ff..0000000 --- a/board/eric/init.S +++ /dev/null @@ -1,355 +0,0 @@ -/*------------------------------------------------------------------------------+ */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ - -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* */ -/*----------------------------------------------------------------------------- */ -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ - - /*------------------------------------------------------------------- */ - /* Delay to ensure all accesses to ROM are complete before changing */ - /* bank 0 timings. 200usec should be enough. */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /*----------------------------------------------------------------------- */ - /* Memory Bank 0 (Flash) initialization (from openbios) */ - /*----------------------------------------------------------------------- */ - - addi r4,0,pb0ap - mtdcr ebccfga,r4 - addis r4,0,CS0_AP@h - ori r4,r4,CS0_AP@l - mtdcr ebccfgd,r4 - - addi r4,0,pb0cr - mtdcr ebccfga,r4 - addis r4,0,CS0_CR@h - ori r4,r4,CS0_CR@l - mtdcr ebccfgd,r4 - - /*----------------------------------------------------------------------- */ - /* Memory Bank 1 (NVRAM/RTC) initialization */ - /*----------------------------------------------------------------------- */ - - addi r4,0,pb1ap - mtdcr ebccfga,r4 - addis r4,0,CS1_AP@h - ori r4,r4,CS1_AP@l - mtdcr ebccfgd,r4 - - addi r4,0,pb1cr - mtdcr ebccfga,r4 - addis r4,0,CS1_CR@h - ori r4,r4,CS1_CR@l - mtdcr ebccfgd,r4 - - /*----------------------------------------------------------------------- */ - /* Memory Bank 2 (A/D converter) initialization */ - /*----------------------------------------------------------------------- */ - - addi r4,0,pb2ap - mtdcr ebccfga,r4 - addis r4,0,CS2_AP@h - ori r4,r4,CS2_AP@l - mtdcr ebccfgd,r4 - - addi r4,0,pb2cr - mtdcr ebccfga,r4 - addis r4,0,CS2_CR@h - ori r4,r4,CS2_CR@l - mtdcr ebccfgd,r4 - - /*----------------------------------------------------------------------- */ - /* Memory Bank 3 (Ethernet PHY Reset) initialization */ - /*----------------------------------------------------------------------- */ - - addi r4,0,pb3ap - mtdcr ebccfga,r4 - addis r4,0,CS3_AP@h - ori r4,r4,CS3_AP@l - mtdcr ebccfgd,r4 - - addi r4,0,pb3cr - mtdcr ebccfga,r4 - addis r4,0,CS3_CR@h - ori r4,r4,CS3_CR@l - mtdcr ebccfgd,r4 - - /*----------------------------------------------------------------------- */ - /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */ - /*----------------------------------------------------------------------- */ - - addi r4,0,pb4ap - mtdcr ebccfga,r4 - addis r4,0,CS4_AP@h - ori r4,r4,CS4_AP@l - mtdcr ebccfgd,r4 - - addi r4,0,pb4cr - mtdcr ebccfga,r4 - addis r4,0,CS4_CR@h - ori r4,r4,CS4_CR@l - mtdcr ebccfgd,r4 - - /*----------------------------------------------------------------------- */ - /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */ - /*----------------------------------------------------------------------- */ - - addi r4,0,pb5ap - mtdcr ebccfga,r4 - addis r4,0,CS5_AP@h - ori r4,r4,CS5_AP@l - mtdcr ebccfgd,r4 - - addi r4,0,pb5cr - mtdcr ebccfga,r4 - addis r4,0,CS5_CR@h - ori r4,r4,CS5_CR@l - mtdcr ebccfgd,r4 - - /*----------------------------------------------------------------------- */ - /* Memory Bank 6 (CPU LED0) initialization */ - /*----------------------------------------------------------------------- */ - - addi r4,0,pb6ap - mtdcr ebccfga,r4 - addis r4,0,CS6_AP@h - ori r4,r4,CS6_AP@l - mtdcr ebccfgd,r4 - - addi r4,0,pb6cr - mtdcr ebccfga,r4 - addis r4,0,CS6_CR@h - ori r4,r4,CS5_CR@l - mtdcr ebccfgd,r4 - - /*----------------------------------------------------------------------- */ - /* Memory Bank 7 (CPU LED1) initialization */ - /*----------------------------------------------------------------------- */ - - addi r4,0,pb7ap - mtdcr ebccfga,r4 - addis r4,0,CS7_AP@h - ori r4,r4,CS7_AP@l - mtdcr ebccfgd,r4 - - addi r4,0,pb7cr - mtdcr ebccfga,r4 - addis r4,0,CS7_CR@h - ori r4,r4,CS7_CR@l - mtdcr ebccfgd,r4 - -/* addis r4,r0,FPGA_BRDC@h */ -/* ori r4,r4,FPGA_BRDC@l */ -/* lbz r3,0(r4) /###*get FPGA board control reg */ -/* eieio */ -/* ori r3,r3,0x01 /###*set UART1 control to select CTS/RTS */ -/* stb r3,0(r4) */ - - nop /* pass2 DCR errata #8 */ - blr - -/*----------------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: Configures SDRAM memory banks on ERIC. */ -/* We do manually init our SDRAM. */ -/* If we have two SDRAM banks, simply undef SINGLE_BANK (ROLF :-) */ -/* It is assumed that a 32MB 12x8(2) SDRAM is used. */ -/*----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - - mflr r31 - -#ifdef CFG_SDRAM_MANUALLY - /*------------------------------------------------------------------- */ - /* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */ - /*------------------------------------------------------------------- */ - - addi r4,0,mem_mb0cf - mtdcr memcfga,r4 - addis r4,0,MB0CF@h - ori r4,r4,MB0CF@l - mtdcr memcfgd,r4 - - /*------------------------------------------------------------------- */ - /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */ - /*------------------------------------------------------------------- */ - - addi r4,0,mem_mb1cf - mtdcr memcfga,r4 - addis r4,0,MB1CF@h - ori r4,r4,MB1CF@l - mtdcr memcfgd,r4 - - /*------------------------------------------------------------------- */ - /* Set MB2CF for bank 2. off */ - /*------------------------------------------------------------------- */ - - addi r4,0,mem_mb2cf - mtdcr memcfga,r4 - addis r4,0,MB2CF@h - ori r4,r4,MB2CF@l - mtdcr memcfgd,r4 - - /*------------------------------------------------------------------- */ - /* Set MB3CF for bank 3. off */ - /*------------------------------------------------------------------- */ - - addi r4,0,mem_mb3cf - mtdcr memcfga,r4 - addis r4,0,MB3CF@h - ori r4,r4,MB3CF@l - mtdcr memcfgd,r4 - - /*------------------------------------------------------------------- */ - /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ - /* To set the appropriate timings, we need to know the SDRAM speed. */ - /* We can use the PLB speed since the SDRAM speed is the same as */ - /* the PLB speed. The PLB speed is the FBK divider times the */ - /* 405GP reference clock, which on the Walnut board is 33Mhz. */ - /* Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is */ - /* 100Mhz; if FBK is 3, SDRAM is 133Mhz. */ - /* NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and */ - /* maybe 133Mhz. */ - /*------------------------------------------------------------------- */ - - mfdcr r5,strap /* determine FBK divider */ - /* via STRAP reg to calc PLB speed. */ - /* SDRAM speed is the same as the PLB */ - /* speed. */ - rlwinm r4,r5,4,0x3 /* get FBK divide bits */ - -..chk_66: - cmpi %cr0,0,r4,0x1 - bne ..chk_100 - addis r6,0,SDTR_66@h /* SDTR1 value for 66Mhz */ - ori r6,r6,SDTR_66@l - addis r7,0,RTR_66 /* RTR value for 66Mhz */ - b ..sdram_ok -..chk_100: - cmpi %cr0,0,r4,0x2 - bne ..chk_133 - addis r6,0,SDTR_100@h /* SDTR1 value for 100Mhz */ - ori r6,r6,SDTR_100@l - addis r7,0,RTR_100 /* RTR value for 100Mhz */ - b ..sdram_ok -..chk_133: - addis r6,0,0x0107 /* SDTR1 value for 133Mhz */ - ori r6,r6,0x4015 - addis r7,0,0x07F0 /* RTR value for 133Mhz */ - -..sdram_ok: - /*------------------------------------------------------------------- */ - /* Set SDTR1 */ - /*------------------------------------------------------------------- */ - addi r4,0,mem_sdtr1 - mtdcr memcfga,r4 - mtdcr memcfgd,r6 - - /*------------------------------------------------------------------- */ - /* Set RTR */ - /*------------------------------------------------------------------- */ - addi r4,0,mem_rtr - mtdcr memcfga,r4 - mtdcr memcfgd,r7 - - /*------------------------------------------------------------------- */ - /* Delay to ensure 200usec have elapsed since reset. Assume worst */ - /* case that the core is running 200Mhz: */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*------------------------------------------------------------------- */ - addis r3,0,0x0000 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp2: - bdnz ..spinlp2 /* spin loop */ - - /*------------------------------------------------------------------- */ - /* Set memory controller options reg, MCOPT1. */ - /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ - /* read/prefetch. */ - /*------------------------------------------------------------------- */ - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x8080 /* set DC_EN=1 */ - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - /*------------------------------------------------------------------- */ - /* Delay to ensure 10msec have elapsed since reset. This is */ - /* required for the MPC952 to stabalize. Assume worst */ - /* case that the core is running 200Mhz: */ - /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */ - /* This delay should occur before accessing SDRAM. */ - /*------------------------------------------------------------------- */ - addis r3,0,0x001E - ori r3,r3,0x8480 /* ensure 10msec have passed since reset */ - mtctr r3 -..spinlp3: - bdnz ..spinlp3 /* spin loop */ - -#else -/*fixme: do SDRAM Autoconfig from EEPROM here */ - -#endif - mtlr r31 /* restore lr */ - blr diff --git a/board/eric/u-boot.lds b/board/eric/u-boot.lds deleted file mode 100644 index 4a0e5b4..0000000 --- a/board/eric/u-boot.lds +++ /dev/null @@ -1,153 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/eric/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile deleted file mode 100644 index 67cf29b..0000000 --- a/board/esd/adciop/Makefile +++ /dev/null @@ -1,47 +0,0 @@ - -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o ../common/pci.o - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/adciop/adciop.c b/board/esd/adciop/adciop.c deleted file mode 100644 index 7a11a12..0000000 --- a/board/esd/adciop/adciop.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "adciop.h" - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -/* ------------------------------------------------------------------------- */ - - -int board_early_init_f (void) -{ - /* - * Set port pin in escc2 to keep living, and configure user led output - */ - *(unsigned char *) 0x2000033e = 0x77; /* ESCC2: PCR bit3=pwr on, bit7=led out */ - *(unsigned char *) 0x2000033c = 0x88; /* ESCC2: PVR pwr on, led off */ - - /* - * Init pci regs - */ - *(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */ - *(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */ - *(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */ - *(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */ - *(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */ - *(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */ - *(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */ - - return 0; -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (!i || strncmp (str, "ADCIOP", 6)) { - puts ("### No HW ID - assuming ADCIOP\n"); - return (1); - } - - puts (str); - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/esd/adciop/adciop.h b/board/esd/adciop/adciop.h deleted file mode 100644 index 5fc313a..0000000 --- a/board/esd/adciop/adciop.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/adciop/config.mk b/board/esd/adciop/config.mk deleted file mode 100644 index 747f29f..0000000 --- a/board/esd/adciop/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -# FLASH: -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0xFFFD0000 - -# SDRAM: -#TEXT_BASE = 0x00FE0000 diff --git a/board/esd/adciop/flash.c b/board/esd/adciop/flash.c deleted file mode 100644 index d9eccba..0000000 --- a/board/esd/adciop/flash.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM+size_b0-monitor_flash_len, - FLASH_BASE0_PRELIM+size_b0-1, - &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(FLASH_BASE0_PRELIM + size_b0), - &flash_info[1]); - - flash_get_offsets (FLASH_BASE0_PRELIM + size_b0, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM+size_b0+size_b1-monitor_flash_len, - FLASH_BASE0_PRELIM+size_b0+size_b1-1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect(FLAG_PROTECT_CLEAR, - FLASH_BASE0_PRELIM+size_b0-monitor_flash_len, - FLASH_BASE0_PRELIM+size_b0-1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/adciop/u-boot.lds b/board/esd/adciop/u-boot.lds deleted file mode 100644 index ef937dd..0000000 --- a/board/esd/adciop/u-boot.lds +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile deleted file mode 100644 index 8529ec7..0000000 --- a/board/esd/apc405/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o strataflash.o ../common/misc.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c deleted file mode 100644 index 4b2b07a..0000000 --- a/board/esd/apc405/apc405.c +++ /dev/null @@ -1,376 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -extern void lxt971_no_sleep(void); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - - -#ifdef CONFIG_LCD_USED -/* logo bitmap data - gzip compressed and generated by bin2c */ -unsigned char logo_bmp[] = -{ -#include CFG_LCD_LOGO_NAME -}; - -/* - * include common lcd code (for esd boards) - */ -#include "../common/lcd.c" - -#include CFG_LCD_HEADER_NAME -#endif /* CONFIG_LCD_USED */ - - -int board_revision(void) -{ - unsigned long cntrl0Reg; - unsigned long value; - - /* - * Get version of APC405 board from GPIO's - */ - - /* - * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); - udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ - - /* - * Restore GPIO settings - */ - mtdcr(cntrl0, cntrl0Reg); - - switch (value) { - case 0x00180000: - /* CS2==1 && CS3==1 -> version <= 1.2 */ - return 2; - case 0x00080000: - /* CS2==0 && CS3==1 -> version 1.3 */ - return 3; -#if 0 /* not yet manufactured ! */ - case 0x00100000: - /* CS2==1 && CS3==0 -> version 1.4 */ - return 4; - case 0x00000000: - /* CS2==0 && CS3==0 -> version 1.5 */ - return 5; -#endif - default: - /* should not be reached! */ - return 0; - } -} - - -int board_early_init_f (void) -{ - /* - * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) - */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ - out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ - out32(GPIO0_OR, 0); /* pull prg low */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ -#if 1 /* test-only */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ -#else - mtebc (epcr, 0x28400000); /* ebc in high-z */ -#endif - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - volatile unsigned short *fpga_ctrl2 = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2); - volatile unsigned char *duart0_mcr = - (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = - (unsigned char *)((ulong)DUART1_BA + 4); - volatile unsigned short *fuji_lcdbl_pwm = - (unsigned short *)((ulong)0xf0100200 + 0xa0); - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - unsigned long cntrl0Reg; - - /* - * Setup GPIO pins (CS6+CS7 as GPIO) - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00300000); - - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - /* restore gpio/cs settings */ - mtdcr(cntrl0, cntrl0Reg); - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Write board revision in FPGA - */ - *fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f); - - /* - * Enable power on PS/2 interface (with reset) - */ - *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET; - for (i=0;i<100;i++) - udelay(1000); - udelay(1000); - *fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET; - - /* - * Enable interrupts in exar duart mcr[3] - */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; - - /* - * Init lcd interface and display logo - */ - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), - logo_bmp, sizeof(logo_bmp)); - - /* - * Reset microcontroller and setup backlight PWM controller - */ - *fpga_mode |= 0x0014; - for (i=0;i<10;i++) - udelay(1000); - *fpga_mode |= 0x001c; - *fuji_lcdbl_pwm = 0x00ff; - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming APC405"); - } else { - puts(str); - } - - gd->board_type = board_revision(); - printf(", Rev 1.%ld\n", gd->board_type); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_IDE_RESET - -void ide_set_reset(int on) -{ - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; - } -} - -#endif /* CONFIG_IDE_RESET */ - -/* ------------------------------------------------------------------------- */ diff --git a/board/esd/apc405/config.mk b/board/esd/apc405/config.mk deleted file mode 100644 index 11faad2..0000000 --- a/board/esd/apc405/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ABG405 boards -# - -TEXT_BASE = 0xFFF80000 diff --git a/board/esd/apc405/fpgadata.c b/board/esd/apc405/fpgadata.c deleted file mode 100644 index c31625a..0000000 --- a/board/esd/apc405/fpgadata.c +++ /dev/null @@ -1,2280 +0,0 @@ - 0x1f,0x8b,0x08,0x08,0x30,0x6a,0x41,0x42,0x00,0x03,0x61,0x62,0x67,0x34,0x30,0x35, - 0x5f,0x31,0x5f,0x30,0x32,0x2e,0x62,0x69,0x74,0x00,0xed,0xbd,0x0b,0x74,0x1c,0xd5, - 0x95,0x2e,0xbc,0xeb,0x54,0x49,0x2e,0x75,0xb7,0xd4,0xa5,0x87,0x89,0x00,0x63,0x4a, - 0x2d,0xd9,0xb4,0x3d,0x6d,0xb9,0x2d,0x1b,0x59,0x08,0x59,0x2a,0x3d,0x20,0x1d,0xec, - 0x60,0x41,0x98,0xc4,0x93,0x9f,0xcb,0x34,0xc4,0xc9,0x78,0xb2,0x9c,0x5c,0x43,0x72, - 0xe7,0x3a,0x8f,0x21,0x47,0x0f,0xdb,0x6d,0xcb,0xe0,0xb6,0x71,0x12,0x67,0xe2,0x24, - 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0x84,0x0a,0xd6,0x36,0x10,0x0e,0x00, diff --git a/board/esd/apc405/strataflash.c b/board/esd/apc405/strataflash.c deleted file mode 100644 index ad7a71d..0000000 --- a/board/esd/apc405/strataflash.c +++ /dev/null @@ -1,789 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for ppcboot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#else - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - - CFG_MONITOR_LEN, - - 1, &flash_info[1]); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO - int k; - int size; - int erased; - volatile unsigned long *flash; - - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;iportwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; iportwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; isector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/apc405/u-boot.lds b/board/esd/apc405/u-boot.lds deleted file mode 100644 index f7a20d1..0000000 --- a/board/esd/apc405/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile deleted file mode 100644 index a60495a..0000000 --- a/board/esd/ar405/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c deleted file mode 100644 index 3aac3c6..0000000 --- a/board/esd/ar405/ar405.c +++ /dev/null @@ -1,438 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "ar405.h" -#include -#include - -/*cmd_boot.c*/ -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -extern void lxt971_no_sleep(void); - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -const unsigned char fpgadata_xl30[] = { -#include "fpgadata_xl30.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int index, len, i; - int status; - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - - /* - * Boot onboard FPGA - */ - /* first try 40er image */ - gd->board_type = 40; - status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); - if (status != 0) { - /* try xl30er image */ - gd->board_type = 30; - status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc ('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf ("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay (1000); - } - putc ('\n'); - do_reset (NULL, 0, 0, NULL); - } - } - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - - *(ushort *) 0xf03000ec = 0x0fff; /* enable all interrupts in fpga */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int index; - int len; - char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); - const unsigned char *fpga; - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming AR405"); - } else { - puts(str); - } - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - if (gd->board_type == 30) { - fpga = fpgadata_xl30; - } else { - fpga = fpgadata; - } - index = 15; - for (i = 0; i < 4; i++) { - len = fpga[index]; - printf ("%s ", &(fpga[index + 1])); - index += len + 3; - } - - putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - -#if 1 /* test-only: some internal test routines... */ -/* - * Some test routines - */ -int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - volatile uchar *digen = (volatile uchar *)0xf03000b4; - volatile ushort *digout = (volatile ushort *)0xf03000b0; - volatile ushort *digin = (volatile ushort *)0xf03000a0; - int i; - int k; - int start; - int end; - - if (argc != 3) { - puts("Usage: digtest n_start n_end (digtest 0 7)\n"); - return 0; - } - - start = simple_strtol (argv[1], NULL, 10); - end = simple_strtol (argv[2], NULL, 10); - - /* - * Enable digital outputs - */ - *digen = 0x08; - - printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n", - start, end); - - /* - * Set outputs one by one - */ - for (;;) { - for (i=start; i<=end; i++) { - *digout = 0x0001 << i; - for (k=0; k<200; k++) - udelay(1000); - - if (*digin != (0x0001 << i)) { - printf("ERROR: OUT=0x%04X, IN=0x%04X\n", 0x0001 << i, *digin); - return 0; - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - } - } - - return 0; -} -U_BOOT_CMD( - digtest, 3, 1, do_digtest, - "digtest - Test digital in-/output\n", - NULL - ); - - -#define ERROR_DELTA 256 - -struct io { - volatile short val; - short dummy; -}; - -int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - volatile short val; - int i; - int volt; - struct io *out; - struct io *in; - - out = (struct io *)0xf0300090; - in = (struct io *)0xf0300000; - - i = simple_strtol (argv[1], NULL, 10); - - volt = 0; - printf("Setting Channel %d to %dV...\n", i, volt); - out[i].val = (volt * 0x7fff) / 10; - udelay(10000); - val = in[i*2].val; - printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - val = in[i*2+1].val; - printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - - volt = 5; - printf("Setting Channel %d to %dV...\n", i, volt); - out[i].val = (volt * 0x7fff) / 10; - udelay(10000); - val = in[i*2].val; - printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - val = in[i*2+1].val; - printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - - volt = 10; - printf("Setting Channel %d to %dV...\n", i, volt); - out[i].val = (volt * 0x7fff) / 10; - udelay(10000); - val = in[i*2].val; - printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - val = in[i*2+1].val; - printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff); - if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) || - (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) { - printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA, - ((volt * 0x7fff) / 40) + ERROR_DELTA); - return -1; - } - - printf("Channel %d OK!\n", i); - - return 0; -} -U_BOOT_CMD( - anatest, 2, 1, do_anatest, - "anatest - Test analog in-/output\n", - NULL - ); - - -int counter = 0; - -void cyclicInt(void *ptr) -{ - *(ushort *)0xf03000e8 = 0x0800; /* ack int */ - counter++; -} - - -int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - volatile uchar *digout = (volatile uchar *)0xf03000b4; - volatile ulong *incin; - int i; - - incin = (volatile ulong *)0xf0300040; - - /* - * Clear inc counter - */ - incin[0] = 0; - incin[1] = 0; - incin[2] = 0; - incin[3] = 0; - - incin = (volatile ulong *)0xf0300050; - - /* - * Inc a little - */ - for (i=0; i<10000; i++) { - switch (i & 0x03) { - case 0: - *digout = 0x02; - break; - case 1: - *digout = 0x03; - break; - case 2: - *digout = 0x01; - break; - case 3: - *digout = 0x00; - break; - } - udelay(10); - } - - printf("Inc 0 = %ld\n", incin[0]); - printf("Inc 1 = %ld\n", incin[1]); - printf("Inc 2 = %ld\n", incin[2]); - printf("Inc 3 = %ld\n", incin[3]); - - *(ushort *)0xf03000e0 = 0x0c80-1; /* set counter */ - *(ushort *)0xf03000ec |= 0x0800; /* enable int */ - irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL); - printf("counter=%d\n", counter); - - return 0; -} -U_BOOT_CMD( - inctest, 3, 1, do_inctest, - "inctest - Test incremental encoder inputs\n", - NULL - ); -#endif diff --git a/board/esd/ar405/ar405.h b/board/esd/ar405/ar405.h deleted file mode 100644 index 5fc313a..0000000 --- a/board/esd/ar405/ar405.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/ar405/config.mk b/board/esd/ar405/config.mk deleted file mode 100644 index 3e8baf6..0000000 --- a/board/esd/ar405/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd AR405 boards -# - -#TEXT_BASE = 0xFFFE0000 -#TEXT_BASE = 0xFFFD0000 -TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c deleted file mode 100644 index 89af119..0000000 --- a/board/esd/ar405/flash.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile deleted file mode 100644 index a60495a..0000000 --- a/board/esd/ash405/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c deleted file mode 100644 index 03ae7fd..0000000 --- a/board/esd/ash405/ash405.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); - volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4); - volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4); - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Reset external DUARTs - */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ - udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ - udelay(1000); /* wait 1ms */ - - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* - * Enable interrupts in exar duart mcr[3] - */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; - *duart2_mcr = 0x08; - *duart3_mcr = 0x08; - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming ASH405"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esd/ash405/config.mk b/board/esd/ash405/config.mk deleted file mode 100644 index 1d743a9..0000000 --- a/board/esd/ash405/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ASH405 boards -# - -TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c deleted file mode 100644 index 89af119..0000000 --- a/board/esd/ash405/flash.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/canbt/Makefile b/board/esd/canbt/Makefile deleted file mode 100644 index a60495a..0000000 --- a/board/esd/canbt/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c deleted file mode 100644 index 2ced6cb..0000000 --- a/board/esd/canbt/canbt.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * (C) Copyright 2001 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "canbt.h" -#include -#include - - -/*cmd_boot.c*/ -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -/* fpga configuration data */ -const unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned long cntrl0Reg; - int index, len, i; - int status; - - /* - * Setup GPIO pins - */ - cntrl0Reg = mfdcr (cntrl0) & 0xf0001fff; - cntrl0Reg |= 0x0070f000; - mtdcr (cntrl0, cntrl0Reg); - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - - /* - * Boot onboard FPGA - */ - status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc ('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf ("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay (1000); - } - putc ('\n'); - do_reset (NULL, 0, 0, NULL); - } - - /* - * Setup port pins for normal operation - */ - out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32 (GPIO0_TCR, 0x07038100); /* setup for output */ - out32 (GPIO0_OR, 0x07030100); /* set output pins to high (default) */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (!i || strncmp (str, "CANBT", 5)) { - puts ("### No HW ID - assuming CANBT\n"); - return (0); - } - - puts (str); - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("%s ", &(fpgadata[index + 1])); - index += len + 3; - } - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/esd/canbt/canbt.h b/board/esd/canbt/canbt.h deleted file mode 100644 index 5fc313a..0000000 --- a/board/esd/canbt/canbt.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/canbt/config.mk b/board/esd/canbt/config.mk deleted file mode 100644 index 80076cd..0000000 --- a/board/esd/canbt/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -TEXT_BASE = 0xFFFE0000 -#TEXT_BASE = 0xFFFD0000 diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c deleted file mode 100644 index de847f9..0000000 --- a/board/esd/canbt/flash.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile deleted file mode 100644 index a11ee82..0000000 --- a/board/esd/cms700/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -# Objects for Xilinx JTAG programming (CPLD) -CPLD = ../common/xilinx_jtag/lenval.o \ - ../common/xilinx_jtag/micro.o \ - ../common/xilinx_jtag/ports.o - -OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c deleted file mode 100644 index 649619d..0000000 --- a/board/esd/cms700/cms700.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * (C) Copyright 2005 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - - -extern void lxt971_no_sleep(void); - - -/* fpga configuration data - not compressed, generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; -int filesize = sizeof(fpgadata); - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ - - /* - * Reset CPLD via GPIO12 (CS3) pin - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET); - udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET); - udelay(1000); /* wait 1ms */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Setup and enable EEPROM write protection - */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); - - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - unsigned char str[64]; - int flashcnt; - int delay; - volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000); - volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001); - - puts ("Board: "); - - if (getenv_r("serial#", str, sizeof(str)) == -1) { - puts ("### No HW ID - assuming CMS700"); - } else { - puts(str); - } - - printf(" (PLD-Version=%02d)\n", *ver_reg); - - /* - * Flash LEDs - */ - for (flashcnt = 0; flashcnt < 3; flashcnt++) { - *led_reg = 0x00; /* LEDs off */ - for (delay = 0; delay < 100; delay++) - udelay(1000); - *led_reg = 0x0f; /* LEDs on */ - for (delay = 0; delay < 50; delay++) - udelay(1000); - } - *led_reg = 0x70; - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CFG_EEPROM_WREN) -/* Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) -{ - if (CFG_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); - break; - } - } - return state; -} - -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", - NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ - -/* ------------------------------------------------------------------------- */ - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} diff --git a/board/esd/cms700/config.mk b/board/esd/cms700/config.mk deleted file mode 100644 index 5c3c01c..0000000 --- a/board/esd/cms700/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd CMS405 boards -# - -TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c deleted file mode 100644 index 89af119..0000000 --- a/board/esd/cms700/flash.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c deleted file mode 100644 index d48e972..0000000 --- a/board/esd/common/auto_update.c +++ /dev/null @@ -1,556 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Gary Jennejohn, DENX Software Engineering, gj@denx.de. - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#include "auto_update.h" - -#ifdef CONFIG_AUTO_UPDATE - -#if !(CONFIG_COMMANDS & CFG_CMD_FAT) -#error "must define CFG_CMD_FAT" -#endif - -extern au_image_t au_image[]; -extern int N_AU_IMAGES; - -#define AU_DEBUG -#undef AU_DEBUG - -#undef debug -#ifdef AU_DEBUG -#define debug(fmt,args...) printf (fmt ,##args) -#else -#define debug(fmt,args...) -#endif /* AU_DEBUG */ - - -#define LOAD_ADDR ((unsigned char *)0x100000) /* where to load files into memory */ -#define MAX_LOADSZ 0x1e00000 - -/* externals */ -extern int fat_register_device(block_dev_desc_t *, int); -extern int file_fat_detectfs(void); -extern long file_fat_read(const char *, void *, unsigned long); -long do_fat_read (const char *filename, void *buffer, unsigned long maxsize, int dols); -#ifdef CONFIG_VFD -extern int trab_vfd (ulong); -extern int transfer_pic(unsigned char, unsigned char *, int, int); -#endif -extern int flash_sect_erase(ulong, ulong); -extern int flash_sect_protect (int, ulong, ulong); -extern int flash_write (char *, ulong, ulong); -/* change char* to void* to shutup the compiler */ -extern block_dev_desc_t *get_dev (char*, int); - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -/* references to names in cmd_nand.c */ -#define NANDRW_READ 0x01 -#define NANDRW_WRITE 0x00 -#define NANDRW_JFFS2 0x02 -#define NANDRW_JFFS2_SKIP 0x04 -extern struct nand_chip nand_dev_desc[]; -extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, - size_t * retlen, u_char * buf); -extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); -#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ - -extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; - - -int au_check_cksum_valid(int i, long nbytes) -{ - image_header_t *hdr; - unsigned long checksum; - - hdr = (image_header_t *)LOAD_ADDR; - - if ((au_image[i].type == AU_FIRMWARE) && (au_image[i].size != ntohl(hdr->ih_size))) { - printf ("Image %s has wrong size\n", au_image[i].name); - return -1; - } - - if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) { - printf ("Image %s bad total SIZE\n", au_image[i].name); - return -1; - } - /* check the data CRC */ - checksum = ntohl(hdr->ih_dcrc); - - if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) - != checksum) { - printf ("Image %s bad data checksum\n", au_image[i].name); - return -1; - } - return 0; -} - - -int au_check_header_valid(int i, long nbytes) -{ - image_header_t *hdr; - unsigned long checksum; - - hdr = (image_header_t *)LOAD_ADDR; - /* check the easy ones first */ -#undef CHECK_VALID_DEBUG -#ifdef CHECK_VALID_DEBUG - printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC); - printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_PPC); - printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes); - printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL); -#endif - if (nbytes < sizeof(*hdr)) - { - printf ("Image %s bad header SIZE\n", au_image[i].name); - return -1; - } - if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC) - { - printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name); - return -1; - } - /* check the hdr CRC */ - checksum = ntohl(hdr->ih_hcrc); - hdr->ih_hcrc = 0; - - if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) { - printf ("Image %s bad header checksum\n", au_image[i].name); - return -1; - } - hdr->ih_hcrc = htonl(checksum); - - /* check the type - could do this all in one gigantic if() */ - if ((au_image[i].type == AU_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) { - printf ("Image %s wrong type\n", au_image[i].name); - return -1; - } - if ((au_image[i].type == AU_SCRIPT) && (hdr->ih_type != IH_TYPE_SCRIPT)) { - printf ("Image %s wrong type\n", au_image[i].name); - return -1; - } - - /* recycle checksum */ - checksum = ntohl(hdr->ih_size); - -#if 0 /* test-only */ - /* for kernel and app the image header must also fit into flash */ - if (idx != IDX_DISK) - checksum += sizeof(*hdr); - /* check the size does not exceed space in flash. HUSH scripts */ - /* all have ausize[] set to 0 */ - if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { - printf ("Image %s is bigger than FLASH\n", au_image[i].name); - return -1; - } -#endif - - return 0; -} - - -int au_do_update(int i, long sz) -{ - image_header_t *hdr; - char *addr; - long start, end; - int off, rc; - uint nbytes; - int k; -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - int total; -#endif - - hdr = (image_header_t *)LOAD_ADDR; - - switch (au_image[i].type) { - case AU_SCRIPT: - printf("Executing script %s\n", au_image[i].name); - - /* execute a script */ - if (hdr->ih_type == IH_TYPE_SCRIPT) { - addr = (char *)((char *)hdr + sizeof(*hdr)); - /* stick a NULL at the end of the script, otherwise */ - /* parse_string_outer() runs off the end. */ - addr[ntohl(hdr->ih_size)] = 0; - addr += 8; - - /* - * Replace cr/lf with ; - */ - k = 0; - while (addr[k] != 0) { - if ((addr[k] == 10) || (addr[k] == 13)) { - addr[k] = ';'; - } - k++; - } - - run_command(addr, 0); - return 0; - } - - break; - - case AU_FIRMWARE: - case AU_NOR: - case AU_NAND: - start = au_image[i].start; - end = au_image[i].start + au_image[i].size - 1; - - /* - * do not update firmware when image is already in flash. - */ - if (au_image[i].type == AU_FIRMWARE) { - char *orig = (char*)start; - char *new = (char *)((char *)hdr + sizeof(*hdr)); - nbytes = ntohl(hdr->ih_size); - - while(--nbytes) { - if (*orig++ != *new++) { - break; - } - } - if (!nbytes) { - printf("Skipping firmware update - images are identical\n"); - break; - } - } - - /* unprotect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (au_image[i].type == AU_FIRMWARE) { - flash_sect_protect(0, start, end); - } - - /* - * erase the address range. - */ - if (au_image[i].type != AU_NAND) { - printf("Updating NOR FLASH with image %s\n", au_image[i].name); - debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase(start, end); - } else { -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - printf("Updating NAND FLASH with image %s\n", au_image[i].name); - debug ("nand_erase(%lx, %lx);\n", start, end); - rc = nand_erase (nand_dev_desc, start, end - start + 1, 0); - debug ("nand_erase returned %x\n", rc); -#endif - } - - udelay(10000); - - /* strip the header - except for the kernel and ramdisk */ - if (au_image[i].type != AU_FIRMWARE) { - addr = (char *)hdr; - off = sizeof(*hdr); - nbytes = sizeof(*hdr) + ntohl(hdr->ih_size); - } else { - addr = (char *)((char *)hdr + sizeof(*hdr)); - off = 0; - nbytes = ntohl(hdr->ih_size); - } - - /* - * copy the data from RAM to FLASH - */ - if (au_image[i].type != AU_NAND) { - debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write((uchar *)addr, start, nbytes); - } else { -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes); - rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, - start, nbytes, (size_t *)&total, (uchar *)addr); - debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); -#endif - } - if (rc != 0) { - printf("Flashing failed due to error %d\n", rc); - return -1; - } - - /* - * check the dcrc of the copy - */ - if (au_image[i].type != AU_NAND) { - rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)); - } else { -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, - start, nbytes, (size_t *)&total, (uchar *)addr); - rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size)); -#endif - } - if (rc != ntohl(hdr->ih_dcrc)) { - printf ("Image %s Bad Data Checksum After COPY\n", au_image[i].name); - return -1; - } - - /* protect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (au_image[i].type == AU_FIRMWARE) { - flash_sect_protect(1, start, end); - } - - break; - - default: - printf("Wrong image type selected!\n"); - } - - return 0; -} - - -static void process_macros (const char *input, char *output) -{ - char c, prev; - const char *varname_start = NULL; - int inputcnt = strlen (input); - int outputcnt = CFG_CBSIZE; - int state = 0; /* 0 = waiting for '$' */ - /* 1 = waiting for '(' or '{' */ - /* 2 = waiting for ')' or '}' */ - /* 3 = waiting for ''' */ -#ifdef DEBUG_PARSER - char *output_start = output; - - printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen(input), input); -#endif - - prev = '\0'; /* previous character */ - - while (inputcnt && outputcnt) { - c = *input++; - inputcnt--; - - if (state!=3) { - /* remove one level of escape characters */ - if ((c == '\\') && (prev != '\\')) { - if (inputcnt-- == 0) - break; - prev = c; - c = *input++; - } - } - - switch (state) { - case 0: /* Waiting for (unescaped) $ */ - if ((c == '\'') && (prev != '\\')) { - state = 3; - break; - } - if ((c == '$') && (prev != '\\')) { - state++; - } else { - *(output++) = c; - outputcnt--; - } - break; - case 1: /* Waiting for ( */ - if (c == '(' || c == '{') { - state++; - varname_start = input; - } else { - state = 0; - *(output++) = '$'; - outputcnt--; - - if (outputcnt) { - *(output++) = c; - outputcnt--; - } - } - break; - case 2: /* Waiting for ) */ - if (c == ')' || c == '}') { - int i; - char envname[CFG_CBSIZE], *envval; - int envcnt = input-varname_start-1; /* Varname # of chars */ - - /* Get the varname */ - for (i = 0; i < envcnt; i++) { - envname[i] = varname_start[i]; - } - envname[i] = 0; - - /* Get its value */ - envval = getenv (envname); - - /* Copy into the line if it exists */ - if (envval != NULL) - while ((*envval) && outputcnt) { - *(output++) = *(envval++); - outputcnt--; - } - /* Look for another '$' */ - state = 0; - } - break; - case 3: /* Waiting for ' */ - if ((c == '\'') && (prev != '\\')) { - state = 0; - } else { - *(output++) = c; - outputcnt--; - } - break; - } - prev = c; - } - - if (outputcnt) - *output = 0; - -#ifdef DEBUG_PARSER - printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n", - strlen(output_start), output_start); -#endif -} - - -/* - * this is called from board_init() after the hardware has been set up - * and is usable. That seems like a good time to do this. - * Right now the return value is ignored. - */ -int do_auto_update(void) -{ - block_dev_desc_t *stor_dev; - long sz; - int i, res, cnt, old_ctrlc, got_ctrlc; - char buffer[32]; - char str[80]; - - /* - * Check whether a CompactFlash is inserted - */ - if (ide_dev_desc[0].type == DEV_TYPE_UNKNOWN) { - return -1; /* no disk detected! */ - } - - /* check whether it has a partition table */ - stor_dev = get_dev("ide", 0); - if (stor_dev == NULL) { - debug ("Uknown device type\n"); - return -1; - } - if (fat_register_device(stor_dev, 1) != 0) { - debug ("Unable to register ide disk 0:1 for fatls\n"); - return -1; - } - - /* - * Check if magic file is present - */ - if (do_fat_read(AU_MAGIC_FILE, buffer, sizeof(buffer), LS_NO) <= 0) { - return -1; - } - -#ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show(1); -#endif - puts("\nAutoUpdate Disk detected! Trying to update system...\n"); - - /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc(0); - - /* just loop thru all the possible files */ - for (i = 0; i < N_AU_IMAGES; i++) { - /* - * Try to expand the environment var in the fname - */ - process_macros(au_image[i].name, str); - strcpy(au_image[i].name, str); - - printf("Reading %s ...", au_image[i].name); - /* just read the header */ - sz = do_fat_read(au_image[i].name, LOAD_ADDR, sizeof(image_header_t), LS_NO); - debug ("read %s sz %ld hdr %d\n", - au_image[i].name, sz, sizeof(image_header_t)); - if (sz <= 0 || sz < sizeof(image_header_t)) { - puts(" not found\n"); - continue; - } - if (au_check_header_valid(i, sz) < 0) { - puts(" header not valid\n"); - continue; - } - sz = do_fat_read(au_image[i].name, LOAD_ADDR, MAX_LOADSZ, LS_NO); - debug ("read %s sz %ld hdr %d\n", - au_image[i].name, sz, sizeof(image_header_t)); - if (sz <= 0 || sz <= sizeof(image_header_t)) { - puts(" not found\n"); - continue; - } - if (au_check_cksum_valid(i, sz) < 0) { - puts(" checksum not valid\n"); - continue; - } - puts(" done\n"); - - do { - res = au_do_update(i, sz); - /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc()) { - clear_ctrlc(); - if (res < 0) - got_ctrlc = 1; - break; - } - cnt++; - } while (res < 0); - } - - /* restore the old state */ - disable_ctrlc(old_ctrlc); - - puts("AutoUpdate finished\n\n"); -#ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show(0); -#endif - - return 0; -} - - -int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - do_auto_update(); - - return 0; -} -U_BOOT_CMD( - autoupd, 1, 1, auto_update, - "autoupd - Automatically update images\n", - NULL -); -#endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/esd/common/auto_update.h b/board/esd/common/auto_update.h deleted file mode 100644 index e2af3c7..0000000 --- a/board/esd/common/auto_update.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _AUTO_UPDATE_H_ -#define _AUTO_UPDATE_H_ - -#define MBR_MAGIC 0x07081967 -#define MBR_MAGIC_ADDR 0x100 /* offset 0x100 should be free space */ - -#define AU_MAGIC_FILE "__auto_update" - -#define AU_SCRIPT 1 -#define AU_FIRMWARE 2 -#define AU_NOR 3 -#define AU_NAND 4 - -struct au_image_s { - char name[80]; - ulong start; - ulong size; - int type; -}; - -typedef struct au_image_s au_image_t; - -int do_auto_update(void); -#ifdef CONFIG_AUTO_UPDATE_SHOW -void board_auto_update_show(int au_active); -#endif - -#endif /* #ifndef _AUTO_UPDATE_H_ */ diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c deleted file mode 100644 index dca10be..0000000 --- a/board/esd/common/flash.c +++ /dev/null @@ -1,672 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - short n; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (i < info->sector_count) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_SST320: printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n"); - break; - case FLASH_SST640: printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - short n; - CFG_FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; - - value = addr2[CFG_FLASH_READ0]; - - switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: - info->flash_id = FLASH_MAN_EXCEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[CFG_FLASH_READ1]; /* device ID */ - - switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000; break; /* => 8 MB */ - -#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM)) - case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF1601: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF1602: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CFG_FLASH_WORD_SIZE)SST_ID_xF3201: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF3202: - info->flash_id += FLASH_SST320; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)SST_ID_xF6401: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF6402: - info->flash_id += FLASH_SST640; - info->sector_count = 128; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (i < info->sector_count) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) - info->protect[i] = 0; - else - info->protect[i] = addr2[CFG_FLASH_READ2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - ulong start, now, last; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - if (sect == s_first) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - } - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) - { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c deleted file mode 100644 index ad56402..0000000 --- a/board/esd/common/fpga.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#ifdef FPGA_DEBUG -#define DBG(x...) printf(x) -#else -#define DBG(x...) -#endif /* DEBUG */ - -#define MAX_ONES 226 - -#ifdef CFG_FPGA_PRG -# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/ -# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */ -# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */ -# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */ -# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */ -#else -# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ -# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#endif - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ - -#ifndef SET_FPGA -# define SET_FPGA(data) out32(GPIO0_OR, data) -#endif - -#ifdef FPGA_PROG_ACTIVE_HIGH -# define FPGA_PRG_LOW FPGA_PRG -# define FPGA_PRG_HIGH 0 -#else -# define FPGA_PRG_LOW 0 -# define FPGA_PRG_HIGH FPGA_PRG -#endif - -#define FPGA_CLK_LOW 0 -#define FPGA_CLK_HIGH FPGA_CLK - -#define FPGA_DATA_LOW 0 -#define FPGA_DATA_HIGH FPGA_DATA - -#define FPGA_WRITE_1 { \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ - -#ifndef FPGA_DONE_STATE -# define FPGA_DONE_STATE (in32(GPIO0_IR) & FPGA_DONE) -#endif -#ifndef FPGA_INIT_STATE -# define FPGA_INIT_STATE (in32(GPIO0_IR) & FPGA_INIT) -#endif - - -static int fpga_boot(unsigned char *fpgadata, int size) -{ - int i,index,len; - int count; -#ifdef CFG_FPGA_SPARTAN2 - int j; -#else - unsigned char b; - int bit; -#endif - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) - { - len = fpgadata[index]; - DBG("FPGA: %s\n", &(fpgadata[index+1])); - index += len+3; - } - -#ifdef CFG_FPGA_SPARTAN2 - /* search for preamble 0xFFFFFFFF */ - while (1) - { - if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) && - (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff)) - break; /* preamble found */ - else - index++; - } -#else - /* search for preamble 0xFF2X */ - for (index = 0; index < size-1 ; index++) - { - if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x30)) - break; - } - index += 2; -#endif - - DBG("FPGA: configdata starts at position 0x%x\n",index); - DBG("FPGA: length of fpga-data %d\n", size-index); - - /* - * Setup port pins for fpga programming - */ -#ifndef CONFIG_M5249 - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */ -#endif - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */ - - DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); - DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA(FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */ - - /* Wait for FPGA init line low */ - count = 0; - while (FPGA_INIT_STATE) - { - udelay(1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) - { - DBG("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); - DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - - /* deassert PROGRAM* */ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */ - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(FPGA_INIT_STATE)) - { - udelay(1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) - { - DBG("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); - DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - - DBG("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - -#ifdef CFG_FPGA_SPARTAN2 - /* - * Load uncompressed image into fpga - */ - for (i=index; i= 1) && (b <= MAX_ONES)) - { - for(bit=0; bit= (MAX_ONES+2)) && (b <= 254)) - { - for(bit=0; bit<(b-(MAX_ONES+2)); bit++) - { - FPGA_WRITE_0; - } - FPGA_WRITE_1; - } - else if (b == 255) - { - FPGA_WRITE_1; - } - } -#endif - - DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); - DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - - /* - * Check if fpga's DONE signal - correctly booted ? - */ - - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(FPGA_DONE_STATE)) - { - udelay(1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) - { - DBG("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - DBG("FPGA: Booting successful!\n"); - return 0; -} diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c deleted file mode 100644 index 0edc083..0000000 --- a/board/esd/common/lcd.c +++ /dev/null @@ -1,334 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include "lcd.h" - - -extern int video_display_bitmap (ulong, int, int); - - -int palette_index; -int palette_value; -int lcd_depth; -unsigned char *glob_lcd_reg; -unsigned char *glob_lcd_mem; - -#ifdef CFG_LCD_ENDIAN -void lcd_setup(int lcd, int config) -{ - if (lcd == 0) { - /* - * Set endianess and reset lcd controller 0 (small) - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */ - udelay(10); /* wait 10us */ - if (config == 1) { - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ - } else { - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ - } - udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */ - } else { - /* - * Set endianess and reset lcd controller 1 (big) - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */ - udelay(10); /* wait 10us */ - if (config == 1) { - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ - } else { - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ - } - udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */ - } - - /* - * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive - */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */ -} -#endif /* #ifdef CFG_LCD_ENDIAN */ - - -void lcd_bmp(uchar *logo_bmp) -{ - int i; - uchar *ptr; - ushort *ptr2; - ushort val; - unsigned char *dst = NULL; - int x, y; - int width, height, bpp, colors, line_size; - int header_size; - unsigned char *bmp; - unsigned char r, g, b; - BITMAPINFOHEADER *bm_info; - ulong len; - - /* - * Check for bmp mark 'BM' - */ - if (*(ushort *)logo_bmp != 0x424d) { - - /* - * Decompress bmp image - */ - len = CFG_VIDEO_LOGO_MAX_SIZE; - dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); - if (dst == NULL) { - printf("Error: malloc in gunzip failed!\n"); - return; - } - if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) { - return; - } - if (len == CFG_VIDEO_LOGO_MAX_SIZE) { - printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); - } - - /* - * Check for bmp mark 'BM' - */ - if (*(ushort *)dst != 0x424d) { - printf("LCD: Unknown image format!\n"); - free(dst); - return; - } - } else { - /* - * Uncompressed BMP image, just use this pointer - */ - dst = (uchar *)logo_bmp; - } - - /* - * Get image info from bmp-header - */ - bm_info = (BITMAPINFOHEADER *)(dst + 14); - bpp = LOAD_SHORT(bm_info->biBitCount); - width = LOAD_LONG(bm_info->biWidth); - height = LOAD_LONG(bm_info->biHeight); - switch (bpp) { - case 1: - colors = 1; - line_size = width >> 3; - break; - case 4: - colors = 16; - line_size = width >> 1; - break; - case 8: - colors = 256; - line_size = width; - break; - case 24: - colors = 0; - line_size = width * 3; - break; - default: - printf("LCD: Unknown bpp (%d) im image!\n", bpp); - if ((dst != NULL) && (dst != (uchar *)logo_bmp)) { - free(dst); - } - return; - } - printf(" (%d*%d, %dbpp)\n", width, height, bpp); - - /* - * Write color palette - */ - if ((colors <= 256) && (lcd_depth <= 8)) { - ptr = (unsigned char *)(dst + 14 + 40); - for (i=0; i> 3; - g = *bmp++ >> 2; - r = *bmp++ >> 3; - val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f); - *ptr2++ = val; - } - } else if (bpp == 8) { - for (x=0; x> 3; - g = *ptr++ >> 2; - r = *ptr++ >> 3; - val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f); - *ptr2++ = val; - } - } - } else { - for (x=0; xusage); - return 1; - } - - addr = simple_strtoul(argv[1], NULL, 16); - - str = getenv("bd_type"); - if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) { - /* - * SM501 available, use standard bmp command - */ - return (video_display_bitmap(addr, 0, 0)); - } else { - /* - * No SM501 available, use esd epson bmp command - */ - lcd_bmp((uchar *)addr); - return 0; - } -} - -U_BOOT_CMD( - esdbmp, 2, 1, do_esdbmp, - "esdbmp - display BMP image\n", - " - display image\n" -); -#endif diff --git a/board/esd/common/lcd.h b/board/esd/common/lcd.h deleted file mode 100644 index 3169e6b..0000000 --- a/board/esd/common/lcd.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Neutralize little endians. - */ -#define SWAP_LONG(data) ((unsigned long) \ - (((unsigned long)(data) >> 24) | \ - ((unsigned long)(data) << 24) | \ - (((unsigned long)(data) >> 8) & 0x0000ff00 ) | \ - (((unsigned long)(data) << 8) & 0x00ff0000 ))) -#define SWAP_SHORT(data) ((unsigned short) \ - (((unsigned short)(data) >> 8 ) | \ - ((unsigned short)(data) << 8 ))) -#define LOAD_LONG(data) SWAP_LONG(data) -#define LOAD_SHORT(data) SWAP_SHORT(data) - -#ifndef FALSE -#define FALSE 0 -#define TRUE (!FALSE) -#endif - -#define S1D_WRITE_PALETTE(p,i,r,g,b) \ - { \ - ((volatile uchar*)(p))[palette_index] = (uchar)(i); \ - ((volatile uchar*)(p))[palette_value] = (uchar)(r); \ - ((volatile uchar*)(p))[palette_value] = (uchar)(g); \ - ((volatile uchar*)(p))[palette_value] = (uchar)(b); \ - } - -typedef struct -{ - ushort Index; - uchar Value; -} S1D_REGS; - -typedef struct /**** BMP file info structure ****/ -{ - unsigned int biSize; /* Size of info header */ - int biWidth; /* Width of image */ - int biHeight; /* Height of image */ - unsigned short biPlanes; /* Number of color planes */ - unsigned short biBitCount; /* Number of bits per pixel */ - unsigned int biCompression; /* Type of compression to use */ - unsigned int biSizeImage; /* Size of image data */ - int biXPelsPerMeter; /* X pixels per meter */ - int biYPelsPerMeter; /* Y pixels per meter */ - unsigned int biClrUsed; /* Number of colors used */ - unsigned int biClrImportant; /* Number of important colors */ -} BITMAPINFOHEADER; diff --git a/board/esd/common/misc.c b/board/esd/common/misc.c deleted file mode 100644 index 48b4b7c..0000000 --- a/board/esd/common/misc.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifdef CONFIG_LXT971_NO_SLEEP -#include -#endif - - -#ifdef CONFIG_LXT971_NO_SLEEP -void lxt971_no_sleep(void) -{ - unsigned short reg; - - miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, ®); - reg &= ~0x0040; /* disable sleep mode */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg); -} -#endif /* CONFIG_LXT971_NO_SLEEP */ diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c deleted file mode 100644 index f711205..0000000 --- a/board/esd/common/pci.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - - -u_long pci9054_iobase; - - -#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ -#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ - - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_read_config_dword -| Description: Read a PCI configuration register -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| value Address of the configuration register value -| Return value: -| 0 Successful -+-----------------------------------------------------------------------------*/ -int pci9054_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32* value) -{ - unsigned long conAdrVal; - unsigned long val; - - /* generate coded value for CON_ADR register */ - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - /* Note: *pResult comes back as -1 if machine check happened */ - val = in32r(PCI_PRIMARY_CDR); - - *value = (unsigned long) val; - - out32r(PCI_PRIMARY_CAR, 0); - - if ((*(unsigned long *)0x50000304) & 0x60000000) - { - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - } - - return 0; -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_write_config_dword -| Description: Write a PCI configuration register. -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| Value Configuration register value -| Return value: -| 0 Successful -| Updated for pass2 errata #6. Need to disable interrupts and clear the -| PCICFGADR reg after writing the PCICFGDATA reg. -+-----------------------------------------------------------------------------*/ -int pci9054_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - unsigned long conAdrVal; - - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - out32r(PCI_PRIMARY_CDR, value); - - out32r(PCI_PRIMARY_CAR, 0); - - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - - return (0); -} - -/*----------------------------------------------------------------------- - */ - -#ifdef CONFIG_DASA_SIM -static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *_) -{ - unsigned int iobase; - unsigned short status = 0; - unsigned char timer; - - /* - * Configure PLX PCI9054 - */ - pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status); - status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status); - - /* Check the latency timer for values >= 0x60. - */ - pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); - if (timer < 0x60) - { - pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); - } - - /* Set I/O base register. - */ - pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE); - pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); - - pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); - - if (pci9054_iobase == 0xffffffff) - { - printf("Error: Can not set I/O base register.\n"); - return; - } -} -#endif - -static struct pci_config_table pci9054_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN), - pci_cfgfunc_config_device, { CFG_ETH_IOBASE, - CFG_ETH_IOBASE, - PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, -#ifdef CONFIG_DASA_SIM - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN), - pci_dasa_sim_config_pci9054 }, -#endif -#endif - { } -}; - -static struct pci_controller pci9054_hose = { - config_table: pci9054_config_table, -}; - -void pci_init_board(void) -{ - struct pci_controller *hose = &pci9054_hose; - - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - 0x00000000, 0x00000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI Memory space */ - pci_set_region(hose->regions + 1, - 0x00000000, 0xc0000000, 0x10000000, - PCI_REGION_MEM); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - pci9054_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - pci9054_write_config_dword); - - hose->region_count = 2; - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); -} diff --git a/board/esd/common/s1d13704_320_240_4bpp.h b/board/esd/common/s1d13704_320_240_4bpp.h deleted file mode 100644 index 77c8a46..0000000 --- a/board/esd/common/s1d13704_320_240_4bpp.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * - * Generic Header information generated by 13704CFG.EXE (Build 10) - * - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * All rights reserved. - * - * Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz) - * - * This file defines the configuration environment and registers, - * which can be used by any software, such as display drivers. - * - * PLEASE NOTE: If you FTP this file to a non-Windows platform, make - * sure you transfer this file using ASCII, not BINARY - * mode. - * - */ - -static S1D_REGS regs_13704_320_240_4bpp[] = -{ - { 0x00, 0x00 }, /* Revision Code Register */ - { 0x01, 0x04 }, /*00*/ /* Mode Register 0 Register */ - { 0x02, 0xA4 }, /*a0*/ /* Mode Register 1 Register */ - { 0x03, 0x83 }, /*03*/ /* Mode Register 2 Register - bit7 is LUT bypass */ - { 0x04, 0x27 }, /* Horizontal Panel Size Register */ - { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ - { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ - { 0x07, 0x00 }, /* FPLINE Start Position Register */ - { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ - { 0x09, 0x00 }, /* FPFRAME Start Position Register */ - { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ - { 0x0B, 0x00 }, /* MOD Rate Register */ - { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ - { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ - { 0x0E, 0x00 }, /* Not Used */ - { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ - { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ - { 0x11, 0x00 }, /* Not Used */ - { 0x12, 0x00 }, /* Memory Address Offset Register */ - { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ - { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ - { 0x15, 0x00 }, /* Look-Up Table Address Register */ - { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ - { 0x17, 0x00 }, /* Look-Up Table Data Register */ - { 0x18, 0x01 }, /* GPIO Configuration Control Register */ - { 0x19, 0x01 }, /* GPIO Status/Control Register */ - { 0x1A, 0x00 }, /* Scratch Pad Register */ - { 0x1B, 0x00 }, /* SwivelView Mode Register */ - { 0x1C, 0xA0 }, /* Line Byte Count Register */ - { 0x1D, 0x00 }, /* Not Used */ - { 0x1E, 0x00 }, /* Not Used */ - { 0x1F, 0x00 }, /* Not Used */ -}; diff --git a/board/esd/common/s1d13705_320_240_8bpp.h b/board/esd/common/s1d13705_320_240_8bpp.h deleted file mode 100644 index 60843ac..0000000 --- a/board/esd/common/s1d13705_320_240_8bpp.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * - * Generic Header information generated by 13704CFG.EXE (Build 10) - * - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * All rights reserved. - * - * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz) - * - * This file defines the configuration environment and registers, - * which can be used by any software, such as display drivers. - * - * PLEASE NOTE: If you FTP this file to a non-Windows platform, make - * sure you transfer this file using ASCII, not BINARY - * mode. - * - */ - -static S1D_REGS regs_13705_320_240_8bpp[] = -{ - { 0x00, 0x00 }, /* Revision Code Register */ - { 0x01, 0x23 }, /* Mode Register 0 Register */ - { 0x02, 0xE0 }, /* Mode Register 1 Register */ - { 0x03, 0x03 }, /* Mode Register 2 Register - bit7 is LUT bypass */ - { 0x04, 0x27 }, /* Horizontal Panel Size Register */ - { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ - { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ - { 0x07, 0x00 }, /* FPLINE Start Position Register */ - { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ - { 0x09, 0x01 }, /* FPFRAME Start Position Register */ - { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ - { 0x0B, 0x00 }, /* MOD Rate Register */ - { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ - { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ - { 0x0E, 0x00 }, /* Not Used */ - { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ - { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ - { 0x11, 0x00 }, /* Not Used */ - { 0x12, 0x00 }, /* Memory Address Offset Register */ - { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ - { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ - { 0x15, 0x00 }, /* Look-Up Table Address Register */ - { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ - { 0x17, 0x00 }, /* Look-Up Table Data Register */ - { 0x18, 0x01 }, /* GPIO Configuration Control Register */ - { 0x19, 0x01 }, /* GPIO Status/Control Register */ - { 0x1A, 0x00 }, /* Scratch Pad Register */ - { 0x1B, 0x00 }, /* SwivelView Mode Register */ - { 0x1C, 0xFF }, /* Line Byte Count Register */ - { 0x1D, 0x00 }, /* Not Used */ - { 0x1E, 0x00 }, /* Not Used */ - { 0x1F, 0x00 }, /* Not Used */ -}; diff --git a/board/esd/common/s1d13806_1024_768_8bpp.h b/board/esd/common/s1d13806_1024_768_8bpp.h deleted file mode 100644 index 68801bf..0000000 --- a/board/esd/common/s1d13806_1024_768_8bpp.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * - * File generated by S1D13806CFG.EXE - * - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * All rights reserved. - * - * PLEASE NOTE: If you FTP this file to a non-Windows platform, make - * sure you transfer this file using ASCII, not BINARY mode. - * - * Panel: (active) 1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz) - * - */ - -static S1D_REGS regs_13806_1024_768_8bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x00}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x00}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x01}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x55}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x7F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x12}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xFF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x02}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x00}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x03}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/common/s1d13806_320_240_4bpp.h b/board/esd/common/s1d13806_320_240_4bpp.h deleted file mode 100644 index 24d7350..0000000 --- a/board/esd/common/s1d13806_320_240_4bpp.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * - * File generated by S1D13806CFG.EXE - * - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * All rights reserved. - * - * PLEASE NOTE: If you FTP this file to a non-Windows platform, make - * sure you transfer this file using ASCII, not BINARY mode. - * - * Panel: (active) 320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz) - * - */ - -static S1D_REGS regs_13806_320_240_4bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x08}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x08}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x08}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x32}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x00}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x27}, /* LCD Horizontal Display Width Register */ - {0x0034,0x03}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xEF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x00}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x02}, /* LCD Display Mode Register */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x50}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x00}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x03}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/common/s1d13806_640_480_16bpp.h b/board/esd/common/s1d13806_640_480_16bpp.h deleted file mode 100644 index 178f1a9..0000000 --- a/board/esd/common/s1d13806_640_480_16bpp.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * - * File generated by S1D13806CFG.EXE - * - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * All rights reserved. - * - * PLEASE NOTE: If you FTP this file to a non-Windows platform, make - * sure you transfer this file using ASCII, not BINARY mode. - * - * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) - * - */ - -static S1D_REGS regs_13806_640_480_16bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x18}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x18}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x00}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x05}, /* LCD Display Mode Register */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/common/s1d13806_640_480_8bpp.h b/board/esd/common/s1d13806_640_480_8bpp.h deleted file mode 100644 index c1f5b2b..0000000 --- a/board/esd/common/s1d13806_640_480_8bpp.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * - * File generated by S1D13806CFG.EXE - * - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * All rights reserved. - * - * PLEASE NOTE: If you FTP this file to a non-Windows platform, make - * sure you transfer this file using ASCII, not BINARY mode. - * - * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) - * - */ - -static S1D_REGS regs_13806_640_320_16bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x18}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x18}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x00}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register (8bpp) */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/common/xilinx_jtag/lenval.c b/board/esd/common/xilinx_jtag/lenval.c deleted file mode 100644 index 7316266..0000000 --- a/board/esd/common/xilinx_jtag/lenval.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*******************************************************/ -/* file: lenval.c */ -/* abstract: This file contains routines for using */ -/* the lenVal data structure. */ -/*******************************************************/ - -#include -#include - -#include "lenval.h" -#include "ports.h" - - -/***************************************************************************** - * Function: value - * Description: Extract the long value from the lenval array. - * Parameters: plvValue - ptr to lenval. - * Returns: long - the extracted value. - *****************************************************************************/ -long value( lenVal* plvValue ) -{ - long lValue; /* result to hold the accumulated result */ - short sIndex; - - lValue = 0; - for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex ) - { - lValue <<= 8; /* shift the accumulated result */ - lValue |= plvValue->val[ sIndex]; /* get the last byte first */ - } - - return( lValue ); -} - -/***************************************************************************** - * Function: initLenVal - * Description: Initialize the lenval array with the given value. - * Assumes lValue is less than 256. - * Parameters: plv - ptr to lenval. - * lValue - the value to set. - * Returns: void. - *****************************************************************************/ -void initLenVal( lenVal* plv, - long lValue ) -{ - plv->len = 1; - plv->val[0] = (unsigned char)lValue; -} - -/***************************************************************************** - * Function: EqualLenVal - * Description: Compare two lenval arrays with an optional mask. - * Parameters: plvTdoExpected - ptr to lenval #1. - * plvTdoCaptured - ptr to lenval #2. - * plvTdoMask - optional ptr to mask (=0 if no mask). - * Returns: short - 0 = mismatch; 1 = equal. - *****************************************************************************/ -short EqualLenVal( lenVal* plvTdoExpected, - lenVal* plvTdoCaptured, - lenVal* plvTdoMask ) -{ - short sEqual; - short sIndex; - unsigned char ucByteVal1; - unsigned char ucByteVal2; - unsigned char ucByteMask; - - sEqual = 1; - sIndex = plvTdoExpected->len; - - while ( sEqual && sIndex-- ) - { - ucByteVal1 = plvTdoExpected->val[ sIndex ]; - ucByteVal2 = plvTdoCaptured->val[ sIndex ]; - if ( plvTdoMask ) - { - ucByteMask = plvTdoMask->val[ sIndex ]; - ucByteVal1 &= ucByteMask; - ucByteVal2 &= ucByteMask; - } - if ( ucByteVal1 != ucByteVal2 ) - { - sEqual = 0; - } - } - - return( sEqual ); -} - - -/***************************************************************************** - * Function: RetBit - * Description: return the (byte, bit) of lv (reading from left to right). - * Parameters: plv - ptr to lenval. - * iByte - the byte to get the bit from. - * iBit - the bit number (0=msb) - * Returns: short - the bit value. - *****************************************************************************/ -short RetBit( lenVal* plv, - int iByte, - int iBit ) -{ - /* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */ - /* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */ - return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) ); -} - -/***************************************************************************** - * Function: SetBit - * Description: set the (byte, bit) of lv equal to val - * Example: SetBit("00000000",byte, 1) equals "01000000". - * Parameters: plv - ptr to lenval. - * iByte - the byte to get the bit from. - * iBit - the bit number (0=msb). - * sVal - the bit value to set. - * Returns: void. - *****************************************************************************/ -void SetBit( lenVal* plv, - int iByte, - int iBit, - short sVal ) -{ - unsigned char ucByteVal; - unsigned char ucBitMask; - - ucBitMask = (unsigned char)(1 << ( 7 - iBit )); - ucByteVal = (unsigned char)(plv->val[ iByte ] & (~ucBitMask)); - - if ( sVal ) - { - ucByteVal |= ucBitMask; - } - plv->val[ iByte ] = ucByteVal; -} - -/***************************************************************************** - * Function: AddVal - * Description: add val1 to val2 and store in resVal; - * assumes val1 and val2 are of equal length. - * Parameters: plvResVal - ptr to result. - * plvVal1 - ptr of addendum. - * plvVal2 - ptr of addendum. - * Returns: void. - *****************************************************************************/ -void addVal( lenVal* plvResVal, - lenVal* plvVal1, - lenVal* plvVal2 ) -{ - unsigned char ucCarry; - unsigned short usSum; - unsigned short usVal1; - unsigned short usVal2; - short sIndex; - - plvResVal->len = plvVal1->len; /* set up length of result */ - - /* start at least significant bit and add bytes */ - ucCarry = 0; - sIndex = plvVal1->len; - while ( sIndex-- ) - { - usVal1 = plvVal1->val[ sIndex ]; /* i'th byte of val1 */ - usVal2 = plvVal2->val[ sIndex ]; /* i'th byte of val2 */ - - /* add the two bytes plus carry from previous addition */ - usSum = (unsigned short)( usVal1 + usVal2 + ucCarry ); - - /* set up carry for next byte */ - ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 ); - - /* set the i'th byte of the result */ - plvResVal->val[ sIndex ] = (unsigned char)usSum; - } -} - -/***************************************************************************** - * Function: readVal - * Description: read from XSVF numBytes bytes of data into x. - * Parameters: plv - ptr to lenval in which to put the bytes read. - * sNumBytes - the number of bytes to read. - * Returns: void. - *****************************************************************************/ -void readVal( lenVal* plv, - short sNumBytes ) -{ - unsigned char* pucVal; - - plv->len = sNumBytes; /* set the length of the lenVal */ - for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal ) - { - /* read a byte of data into the lenVal */ - readByte( pucVal ); - } -} diff --git a/board/esd/common/xilinx_jtag/lenval.h b/board/esd/common/xilinx_jtag/lenval.h deleted file mode 100644 index 6bec4ea..0000000 --- a/board/esd/common/xilinx_jtag/lenval.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*******************************************************/ -/* file: lenval.h */ -/* abstract: This file contains a description of the */ -/* data structure "lenval". */ -/*******************************************************/ - -#ifndef lenval_dot_h -#define lenval_dot_h - -/* the lenVal structure is a byte oriented type used to store an */ -/* arbitrary length binary value. As an example, the hex value */ -/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes */ -/* and val[0]=0e and val[1]=3d. val[2-MAX_LEN] are undefined */ - -/* maximum length (in bytes) of value to read in */ -/* this needs to be at least 4, and longer than the */ -/* length of the longest SDR instruction. If there is, */ -/* only 1 device in the chain, MAX_LEN must be at least */ -/* ceil(27/8) == 4. For 6 devices in a chain, MAX_LEN */ -/* must be 5, for 14 devices MAX_LEN must be 6, for 20 */ -/* devices MAX_LEN must be 7, etc.. */ -/* You can safely set MAX_LEN to a smaller number if you*/ -/* know how many devices will be in your chain. */ -#define MAX_LEN 7000 - - -typedef struct var_len_byte -{ - short len; /* number of chars in this value */ - unsigned char val[MAX_LEN+1]; /* bytes of data */ -} lenVal; - - -/* return the long representation of a lenVal */ -extern long value(lenVal *x); - -/* set lenVal equal to value */ -extern void initLenVal(lenVal *x, long value); - -/* check if expected equals actual (taking the mask into account) */ -extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask); - -/* add val1+val2 and put the result in resVal */ -extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2); - -/* return the (byte, bit) of lv (reading from left to right) */ -extern short RetBit(lenVal *lv, int byte, int bit); - -/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1) - equals "01000000" */ -extern void SetBit(lenVal *lv, int byte, int bit, short val); - -/* read from XSVF numBytes bytes of data into x */ -extern void readVal(lenVal *x, short numBytes); - -#endif diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c deleted file mode 100644 index 318f229..0000000 --- a/board/esd/common/xilinx_jtag/micro.c +++ /dev/null @@ -1,1864 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/***************************************************************************** - * file: micro.c - * abstract: This file contains the function, xsvfExecute(), - * call for interpreting the XSVF commands. - * Usage: Call xsvfExecute() to process XSVF data. - * The XSVF data is retrieved by readByte() in ports.c - * Remove the main function if you already have one. - * Options: XSVF_SUPPORT_COMPRESSION - * This define supports the XC9500/XL compression scheme. - * This define adds support for XSDRINC and XSETSDRMASKS. - * XSVF_SUPPORT_ERRORCODES - * This define causes the xsvfExecute function to return - * an error code for specific errors. See error codes below. - * If this is not defined, the return value defaults to the - * legacy values for backward compatibility: - * 1 = success; 0 = failure. - * Debugging: DEBUG_MODE (Legacy name) - * Define DEBUG_MODE to compile with debugging features. - * Both micro.c and ports.c must be compiled with the DEBUG_MODE - * defined to enable the standalone main implementation in - * micro.c that reads XSVF from a file. - * History: v2.00 - Original XSVF implementation. - * v4.04 - Added delay at end of XSIR for XC18v00 support. - * Added new commands for CoolRunner support: - * XSTATE, XENDIR, XENDDR - * v4.05 - Cleanup micro.c but leave ports.c intact. - * v4.06 - Fix xsvfGotoTapState for retry transition. - * v4.07 - Update example waitTime implementations for - * compatibility with Virtex-II. - * v4.10 - Add new XSIR2 command that supports a 2-byte - * IR-length parameter for IR shifts > 255 bits. - * v4.11 - No change. Update version to match SVF2XSVF xlator. - * v4.14 - Added XCOMMENT. - * v5.00 - Improve XSTATE support. - * Added XWAIT. - *****************************************************************************/ - -#include -#include -#include - -#include "micro.h" -#include "lenval.h" -#include "ports.h" - - -extern const unsigned char fpgadata[]; -extern int filesize; - - -/*============================================================================ - * XSVF #define - ============================================================================*/ - -#define XSVF_VERSION "5.00" - -/***************************************************************************** - * Define: XSVF_SUPPORT_COMPRESSION - * Description: Define this to support the XC9500/XL XSVF data compression - * scheme. - * Code size can be reduced by NOT supporting this feature. - * However, you must use the -nc (no compress) option when - * translating SVF to XSVF using the SVF2XSVF translator. - * Corresponding, uncompressed XSVF may be larger. - *****************************************************************************/ -#ifndef XSVF_SUPPORT_COMPRESSION -#define XSVF_SUPPORT_COMPRESSION 1 -#endif - -/***************************************************************************** - * Define: XSVF_SUPPORT_ERRORCODES - * Description: Define this to support the new XSVF error codes. - * (The original XSVF player just returned 1 for success and - * 0 for an unspecified failure.) - *****************************************************************************/ -#ifndef XSVF_SUPPORT_ERRORCODES -#define XSVF_SUPPORT_ERRORCODES 1 -#endif - -#ifdef XSVF_SUPPORT_ERRORCODES -#define XSVF_ERRORCODE(errorCode) errorCode -#else /* Use legacy error code */ -#define XSVF_ERRORCODE(errorCode) ((errorCode==XSVF_ERROR_NONE)?1:0) -#endif /* XSVF_SUPPORT_ERRORCODES */ - - -/*============================================================================ - * DEBUG_MODE #define - ============================================================================*/ -#define DEBUG_MODE - -#ifdef DEBUG_MODE -#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat ); } -#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat, arg1 ); } -#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat, arg1, arg2 ); } -#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat, arg1, arg2, arg3 ); } -#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - xsvfPrintLenVal(plenVal); } -#else /* !DEBUG_MODE */ -#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) -#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) -#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) -#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) -#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) -#endif /* DEBUG_MODE */ - - -/*============================================================================ - * XSVF Type Declarations - ============================================================================*/ - -/***************************************************************************** - * Struct: SXsvfInfo - * Description: This structure contains all of the data used during the - * execution of the XSVF. Some data is persistent, predefined - * information (e.g. lRunTestTime). The bulk of this struct's - * size is due to the lenVal structs (defined in lenval.h) - * which contain buffers for the active shift data. The MAX_LEN - * #define in lenval.h defines the size of these buffers. - * These buffers must be large enough to store the longest - * shift data in your XSVF file. For example: - * MAX_LEN >= ( longest_shift_data_in_bits / 8 ) - * Because the lenVal struct dominates the space usage of this - * struct, the rough size of this struct is: - * sizeof( SXsvfInfo ) ~= MAX_LEN * 7 (number of lenVals) - * xsvfInitialize() contains initialization code for the data - * in this struct. - * xsvfCleanup() contains cleanup code for the data in this - * struct. - *****************************************************************************/ -typedef struct tagSXsvfInfo -{ - /* XSVF status information */ - unsigned char ucComplete; /* 0 = running; 1 = complete */ - unsigned char ucCommand; /* Current XSVF command byte */ - long lCommandCount; /* Number of commands processed */ - int iErrorCode; /* An error code. 0 = no error. */ - - /* TAP state/sequencing information */ - unsigned char ucTapState; /* Current TAP state */ - unsigned char ucEndIR; /* ENDIR TAP state (See SVF) */ - unsigned char ucEndDR; /* ENDDR TAP state (See SVF) */ - - /* RUNTEST information */ - unsigned char ucMaxRepeat; /* Max repeat loops (for xc9500/xl) */ - long lRunTestTime; /* Pre-specified RUNTEST time (usec) */ - - /* Shift Data Info and Buffers */ - long lShiftLengthBits; /* Len. current shift data in bits */ - short sShiftLengthBytes; /* Len. current shift data in bytes */ - - lenVal lvTdi; /* Current TDI shift data */ - lenVal lvTdoExpected; /* Expected TDO shift data */ - lenVal lvTdoCaptured; /* Captured TDO shift data */ - lenVal lvTdoMask; /* TDO mask: 0=dontcare; 1=compare */ - -#ifdef XSVF_SUPPORT_COMPRESSION - /* XSDRINC Data Buffers */ - lenVal lvAddressMask; /* Address mask for XSDRINC */ - lenVal lvDataMask; /* Data mask for XSDRINC */ - lenVal lvNextData; /* Next data for XSDRINC */ -#endif /* XSVF_SUPPORT_COMPRESSION */ -} SXsvfInfo; - -/* Declare pointer to functions that perform XSVF commands */ -typedef int (*TXsvfDoCmdFuncPtr)( SXsvfInfo* ); - -/*============================================================================ - * XSVF Command Bytes - ============================================================================*/ - -/* encodings of xsvf instructions */ -#define XCOMPLETE 0 -#define XTDOMASK 1 -#define XSIR 2 -#define XSDR 3 -#define XRUNTEST 4 -/* Reserved 5 */ -/* Reserved 6 */ -#define XREPEAT 7 -#define XSDRSIZE 8 -#define XSDRTDO 9 -#define XSETSDRMASKS 10 -#define XSDRINC 11 -#define XSDRB 12 -#define XSDRC 13 -#define XSDRE 14 -#define XSDRTDOB 15 -#define XSDRTDOC 16 -#define XSDRTDOE 17 -#define XSTATE 18 /* 4.00 */ -#define XENDIR 19 /* 4.04 */ -#define XENDDR 20 /* 4.04 */ -#define XSIR2 21 /* 4.10 */ -#define XCOMMENT 22 /* 4.14 */ -#define XWAIT 23 /* 5.00 */ -/* Insert new commands here */ -/* and add corresponding xsvfDoCmd function to xsvf_pfDoCmd below. */ -#define XLASTCMD 24 /* Last command marker */ - - -/*============================================================================ - * XSVF Command Parameter Values - ============================================================================*/ - -#define XSTATE_RESET 0 /* 4.00 parameter for XSTATE */ -#define XSTATE_RUNTEST 1 /* 4.00 parameter for XSTATE */ - -#define XENDXR_RUNTEST 0 /* 4.04 parameter for XENDIR/DR */ -#define XENDXR_PAUSE 1 /* 4.04 parameter for XENDIR/DR */ - -/* TAP states */ -#define XTAPSTATE_RESET 0x00 -#define XTAPSTATE_RUNTEST 0x01 /* a.k.a. IDLE */ -#define XTAPSTATE_SELECTDR 0x02 -#define XTAPSTATE_CAPTUREDR 0x03 -#define XTAPSTATE_SHIFTDR 0x04 -#define XTAPSTATE_EXIT1DR 0x05 -#define XTAPSTATE_PAUSEDR 0x06 -#define XTAPSTATE_EXIT2DR 0x07 -#define XTAPSTATE_UPDATEDR 0x08 -#define XTAPSTATE_IRSTATES 0x09 /* All IR states begin here */ -#define XTAPSTATE_SELECTIR 0x09 -#define XTAPSTATE_CAPTUREIR 0x0A -#define XTAPSTATE_SHIFTIR 0x0B -#define XTAPSTATE_EXIT1IR 0x0C -#define XTAPSTATE_PAUSEIR 0x0D -#define XTAPSTATE_EXIT2IR 0x0E -#define XTAPSTATE_UPDATEIR 0x0F - -/*============================================================================ - * XSVF Function Prototypes - ============================================================================*/ - -int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo ); /* Illegal command function */ -int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSIR( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDR( SXsvfInfo* pXsvfInfo ); -int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo ); -int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo ); -int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo ); -int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo ); -/* Insert new command functions here */ - -/*============================================================================ - * XSVF Global Variables - ============================================================================*/ - -/* Array of XSVF command functions. Must follow command byte value order! */ -/* If your compiler cannot take this form, then convert to a switch statement*/ -TXsvfDoCmdFuncPtr xsvf_pfDoCmd[] = -{ - xsvfDoXCOMPLETE, /* 0 */ - xsvfDoXTDOMASK, /* 1 */ - xsvfDoXSIR, /* 2 */ - xsvfDoXSDR, /* 3 */ - xsvfDoXRUNTEST, /* 4 */ - xsvfDoIllegalCmd, /* 5 */ - xsvfDoIllegalCmd, /* 6 */ - xsvfDoXREPEAT, /* 7 */ - xsvfDoXSDRSIZE, /* 8 */ - xsvfDoXSDRTDO, /* 9 */ -#ifdef XSVF_SUPPORT_COMPRESSION - xsvfDoXSETSDRMASKS, /* 10 */ - xsvfDoXSDRINC, /* 11 */ -#else - xsvfDoIllegalCmd, /* 10 */ - xsvfDoIllegalCmd, /* 11 */ -#endif /* XSVF_SUPPORT_COMPRESSION */ - xsvfDoXSDRBCE, /* 12 */ - xsvfDoXSDRBCE, /* 13 */ - xsvfDoXSDRBCE, /* 14 */ - xsvfDoXSDRTDOBCE, /* 15 */ - xsvfDoXSDRTDOBCE, /* 16 */ - xsvfDoXSDRTDOBCE, /* 17 */ - xsvfDoXSTATE, /* 18 */ - xsvfDoXENDXR, /* 19 */ - xsvfDoXENDXR, /* 20 */ - xsvfDoXSIR2, /* 21 */ - xsvfDoXCOMMENT, /* 22 */ - xsvfDoXWAIT /* 23 */ -/* Insert new command functions here */ -}; - -#ifdef DEBUG_MODE -char* xsvf_pzCommandName[] = -{ - "XCOMPLETE", - "XTDOMASK", - "XSIR", - "XSDR", - "XRUNTEST", - "Reserved5", - "Reserved6", - "XREPEAT", - "XSDRSIZE", - "XSDRTDO", - "XSETSDRMASKS", - "XSDRINC", - "XSDRB", - "XSDRC", - "XSDRE", - "XSDRTDOB", - "XSDRTDOC", - "XSDRTDOE", - "XSTATE", - "XENDIR", - "XENDDR", - "XSIR2", - "XCOMMENT", - "XWAIT" -}; - -char* xsvf_pzErrorName[] = -{ - "No error", - "ERROR: Unknown", - "ERROR: TDO mismatch", - "ERROR: TDO mismatch and exceeded max retries", - "ERROR: Unsupported XSVF command", - "ERROR: Illegal state specification", - "ERROR: Data overflows allocated MAX_LEN buffer size" -}; - -char* xsvf_pzTapState[] = -{ - "RESET", /* 0x00 */ - "RUNTEST/IDLE", /* 0x01 */ - "DRSELECT", /* 0x02 */ - "DRCAPTURE", /* 0x03 */ - "DRSHIFT", /* 0x04 */ - "DREXIT1", /* 0x05 */ - "DRPAUSE", /* 0x06 */ - "DREXIT2", /* 0x07 */ - "DRUPDATE", /* 0x08 */ - "IRSELECT", /* 0x09 */ - "IRCAPTURE", /* 0x0A */ - "IRSHIFT", /* 0x0B */ - "IREXIT1", /* 0x0C */ - "IRPAUSE", /* 0x0D */ - "IREXIT2", /* 0x0E */ - "IRUPDATE" /* 0x0F */ -}; -#endif /* DEBUG_MODE */ - -/*#ifdef DEBUG_MODE */ -/* FILE* in; /XXX* Legacy DEBUG_MODE file pointer */ -int xsvf_iDebugLevel; -/*#endif /XXX* DEBUG_MODE */ - -/*============================================================================ - * Utility Functions - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfPrintLenVal - * Description: Print the lenval value in hex. - * Parameters: plv - ptr to lenval. - * Returns: void. - *****************************************************************************/ -#ifdef DEBUG_MODE -void xsvfPrintLenVal( lenVal *plv ) -{ - int i; - - if ( plv ) - { - printf( "0x" ); - for ( i = 0; i < plv->len; ++i ) - { - printf( "%02x", ((unsigned int)(plv->val[ i ])) ); - } - } -} -#endif /* DEBUG_MODE */ - - -/***************************************************************************** - * Function: xsvfInfoInit - * Description: Initialize the xsvfInfo data. - * Parameters: pXsvfInfo - ptr to the XSVF info structure. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfInfoInit( SXsvfInfo* pXsvfInfo ) -{ - XSVFDBG_PRINTF1( 4, " sizeof( SXsvfInfo ) = %d bytes\n", - sizeof( SXsvfInfo ) ); - - pXsvfInfo->ucComplete = 0; - pXsvfInfo->ucCommand = XCOMPLETE; - pXsvfInfo->lCommandCount = 0; - pXsvfInfo->iErrorCode = XSVF_ERROR_NONE; - pXsvfInfo->ucMaxRepeat = 0; - pXsvfInfo->ucTapState = XTAPSTATE_RESET; - pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST; - pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST; - pXsvfInfo->lShiftLengthBits = 0L; - pXsvfInfo->sShiftLengthBytes= 0; - pXsvfInfo->lRunTestTime = 0L; - - return( 0 ); -} - -/***************************************************************************** - * Function: xsvfInfoCleanup - * Description: Cleanup the xsvfInfo data. - * Parameters: pXsvfInfo - ptr to the XSVF info structure. - * Returns: void. - *****************************************************************************/ -void xsvfInfoCleanup( SXsvfInfo* pXsvfInfo ) -{ -} - -/***************************************************************************** - * Function: xsvfGetAsNumBytes - * Description: Calculate the number of bytes the given number of bits - * consumes. - * Parameters: lNumBits - the number of bits. - * Returns: short - the number of bytes to store the number of bits. - *****************************************************************************/ -short xsvfGetAsNumBytes( long lNumBits ) -{ - return( (short)( ( lNumBits + 7L ) / 8L ) ); -} - -/***************************************************************************** - * Function: xsvfTmsTransition - * Description: Apply TMS and transition TAP controller by applying one TCK - * cycle. - * Parameters: sTms - new TMS value. - * Returns: void. - *****************************************************************************/ -void xsvfTmsTransition( short sTms ) -{ - setPort( TMS, sTms ); - setPort( TCK, 0 ); - setPort( TCK, 1 ); -} - -/***************************************************************************** - * Function: xsvfGotoTapState - * Description: From the current TAP state, go to the named TAP state. - * A target state of RESET ALWAYS causes TMS reset sequence. - * All SVF standard stable state paths are supported. - * All state transitions are supported except for the following - * which cause an XSVF_ERROR_ILLEGALSTATE: - * - Target==DREXIT2; Start!=DRPAUSE - * - Target==IREXIT2; Start!=IRPAUSE - * Parameters: pucTapState - Current TAP state; returns final TAP state. - * ucTargetState - New target TAP state. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfGotoTapState( unsigned char* pucTapState, - unsigned char ucTargetState ) -{ - int i; - int iErrorCode; - - iErrorCode = XSVF_ERROR_NONE; - if ( ucTargetState == XTAPSTATE_RESET ) - { - /* If RESET, always perform TMS reset sequence to reset/sync TAPs */ - xsvfTmsTransition( 1 ); - for ( i = 0; i < 5; ++i ) - { - setPort( TCK, 0 ); - setPort( TCK, 1 ); - } - *pucTapState = XTAPSTATE_RESET; - XSVFDBG_PRINTF( 3, " TMS Reset Sequence -> Test-Logic-Reset\n" ); - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } else if ( ( ucTargetState != *pucTapState ) && - ( ( ( ucTargetState == XTAPSTATE_EXIT2DR ) && ( *pucTapState != XTAPSTATE_PAUSEDR ) ) || - ( ( ucTargetState == XTAPSTATE_EXIT2IR ) && ( *pucTapState != XTAPSTATE_PAUSEIR ) ) ) ) - { - /* Trap illegal TAP state path specification */ - iErrorCode = XSVF_ERROR_ILLEGALSTATE; - } else { - if ( ucTargetState == *pucTapState ) - { - /* Already in target state. Do nothing except when in DRPAUSE - or in IRPAUSE to comply with SVF standard */ - if ( ucTargetState == XTAPSTATE_PAUSEDR ) - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2DR; - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } - else if ( ucTargetState == XTAPSTATE_PAUSEIR ) - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2IR; - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } - } - - /* Perform TAP state transitions to get to the target state */ - while ( ucTargetState != *pucTapState ) - { - switch ( *pucTapState ) - { - case XTAPSTATE_RESET: - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_RUNTEST; - break; - case XTAPSTATE_RUNTEST: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTDR; - break; - case XTAPSTATE_SELECTDR: - if ( ucTargetState >= XTAPSTATE_IRSTATES ) - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTIR; - } - else - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_CAPTUREDR; - } - break; - case XTAPSTATE_CAPTUREDR: - if ( ucTargetState == XTAPSTATE_SHIFTDR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTDR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1DR; - } - break; - case XTAPSTATE_SHIFTDR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1DR; - break; - case XTAPSTATE_EXIT1DR: - if ( ucTargetState == XTAPSTATE_PAUSEDR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_PAUSEDR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEDR; - } - break; - case XTAPSTATE_PAUSEDR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2DR; - break; - case XTAPSTATE_EXIT2DR: - if ( ucTargetState == XTAPSTATE_SHIFTDR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTDR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEDR; - } - break; - case XTAPSTATE_UPDATEDR: - if ( ucTargetState == XTAPSTATE_RUNTEST ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_RUNTEST; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTDR; - } - break; - case XTAPSTATE_SELECTIR: - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_CAPTUREIR; - break; - case XTAPSTATE_CAPTUREIR: - if ( ucTargetState == XTAPSTATE_SHIFTIR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTIR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1IR; - } - break; - case XTAPSTATE_SHIFTIR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1IR; - break; - case XTAPSTATE_EXIT1IR: - if ( ucTargetState == XTAPSTATE_PAUSEIR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_PAUSEIR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEIR; - } - break; - case XTAPSTATE_PAUSEIR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2IR; - break; - case XTAPSTATE_EXIT2IR: - if ( ucTargetState == XTAPSTATE_SHIFTIR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTIR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEIR; - } - break; - case XTAPSTATE_UPDATEIR: - if ( ucTargetState == XTAPSTATE_RUNTEST ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_RUNTEST; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTDR; - } - break; - default: - iErrorCode = XSVF_ERROR_ILLEGALSTATE; - *pucTapState = ucTargetState; /* Exit while loop */ - break; - } - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } - } - - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfShiftOnly - * Description: Assumes that starting TAP state is SHIFT-DR or SHIFT-IR. - * Shift the given TDI data into the JTAG scan chain. - * Optionally, save the TDO data shifted out of the scan chain. - * Last shift cycle is special: capture last TDO, set last TDI, - * but does not pulse TCK. Caller must pulse TCK and optionally - * set TMS=1 to exit shift state. - * Parameters: lNumBits - number of bits to shift. - * plvTdi - ptr to lenval for TDI data. - * plvTdoCaptured - ptr to lenval for storing captured TDO data. - * iExitShift - 1=exit at end of shift; 0=stay in Shift-DR. - * Returns: void. - *****************************************************************************/ -void xsvfShiftOnly( long lNumBits, - lenVal* plvTdi, - lenVal* plvTdoCaptured, - int iExitShift ) -{ - unsigned char* pucTdi; - unsigned char* pucTdo; - unsigned char ucTdiByte; - unsigned char ucTdoByte; - unsigned char ucTdoBit; - int i; - - /* assert( ( ( lNumBits + 7 ) / 8 ) == plvTdi->len ); */ - - /* Initialize TDO storage len == TDI len */ - pucTdo = 0; - if ( plvTdoCaptured ) - { - plvTdoCaptured->len = plvTdi->len; - pucTdo = plvTdoCaptured->val + plvTdi->len; - } - - /* Shift LSB first. val[N-1] == LSB. val[0] == MSB. */ - pucTdi = plvTdi->val + plvTdi->len; - while ( lNumBits ) - { - /* Process on a byte-basis */ - ucTdiByte = (*(--pucTdi)); - ucTdoByte = 0; - for ( i = 0; ( lNumBits && ( i < 8 ) ); ++i ) - { - --lNumBits; - if ( iExitShift && !lNumBits ) - { - /* Exit Shift-DR state */ - setPort( TMS, 1 ); - } - - /* Set the new TDI value */ - setPort( TDI, (short)(ucTdiByte & 1) ); - ucTdiByte >>= 1; - - /* Set TCK low */ - setPort( TCK, 0 ); - - if ( pucTdo ) - { - /* Save the TDO value */ - ucTdoBit = readTDOBit(); - ucTdoByte |= ( ucTdoBit << i ); - } - - /* Set TCK high */ - setPort( TCK, 1 ); - } - - /* Save the TDO byte value */ - if ( pucTdo ) - { - (*(--pucTdo)) = ucTdoByte; - } - } -} - -/***************************************************************************** - * Function: xsvfShift - * Description: Goes to the given starting TAP state. - * Calls xsvfShiftOnly to shift in the given TDI data and - * optionally capture the TDO data. - * Compares the TDO captured data against the TDO expected - * data. - * If a data mismatch occurs, then executes the exception - * handling loop upto ucMaxRepeat times. - * Parameters: pucTapState - Ptr to current TAP state. - * ucStartState - Starting shift state: Shift-DR or Shift-IR. - * lNumBits - number of bits to shift. - * plvTdi - ptr to lenval for TDI data. - * plvTdoCaptured - ptr to lenval for storing TDO data. - * plvTdoExpected - ptr to expected TDO data. - * plvTdoMask - ptr to TDO mask. - * ucEndState - state in which to end the shift. - * lRunTestTime - amount of time to wait after the shift. - * ucMaxRepeat - Maximum number of retries on TDO mismatch. - * Returns: int - 0 = success; otherwise TDO mismatch. - * Notes: XC9500XL-only Optimization: - * Skip the waitTime() if plvTdoMask->val[0:plvTdoMask->len-1] - * is NOT all zeros and sMatch==1. - *****************************************************************************/ -int xsvfShift( unsigned char* pucTapState, - unsigned char ucStartState, - long lNumBits, - lenVal* plvTdi, - lenVal* plvTdoCaptured, - lenVal* plvTdoExpected, - lenVal* plvTdoMask, - unsigned char ucEndState, - long lRunTestTime, - unsigned char ucMaxRepeat ) -{ - int iErrorCode; - int iMismatch; - unsigned char ucRepeat; - int iExitShift; - - iErrorCode = XSVF_ERROR_NONE; - iMismatch = 0; - ucRepeat = 0; - iExitShift = ( ucStartState != ucEndState ); - - XSVFDBG_PRINTF1( 3, " Shift Length = %ld\n", lNumBits ); - XSVFDBG_PRINTF( 4, " TDI = "); - XSVFDBG_PRINTLENVAL( 4, plvTdi ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF( 4, " TDO Expected = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoExpected ); - XSVFDBG_PRINTF( 4, "\n"); - - if ( !lNumBits ) - { - /* Compatibility with XSVF2.00: XSDR 0 = no shift, but wait in RTI */ - if ( lRunTestTime ) - { - /* Wait for prespecified XRUNTEST time */ - xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST ); - XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime ); - waitTime( lRunTestTime ); - } - } - else - { - do - { - /* Goto Shift-DR or Shift-IR */ - xsvfGotoTapState( pucTapState, ucStartState ); - - /* Shift TDI and capture TDO */ - xsvfShiftOnly( lNumBits, plvTdi, plvTdoCaptured, iExitShift ); - - if ( plvTdoExpected ) - { - /* Compare TDO data to expected TDO data */ - iMismatch = !EqualLenVal( plvTdoExpected, - plvTdoCaptured, - plvTdoMask ); - } - - if ( iExitShift ) - { - /* Update TAP state: Shift->Exit */ - ++(*pucTapState); - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - - if ( iMismatch && lRunTestTime && ( ucRepeat < ucMaxRepeat ) ) - { - XSVFDBG_PRINTF( 4, " TDO Expected = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoExpected ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF( 4, " TDO Captured = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoCaptured ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF( 4, " TDO Mask = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoMask ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF1( 3, " Retry #%d\n", ( ucRepeat + 1 ) ); - /* Do exception handling retry - ShiftDR only */ - xsvfGotoTapState( pucTapState, XTAPSTATE_PAUSEDR ); - /* Shift 1 extra bit */ - xsvfGotoTapState( pucTapState, XTAPSTATE_SHIFTDR ); - /* Increment RUNTEST time by an additional 25% */ - lRunTestTime += ( lRunTestTime >> 2 ); - } - else - { - /* Do normal exit from Shift-XR */ - xsvfGotoTapState( pucTapState, ucEndState ); - } - - if ( lRunTestTime ) - { - /* Wait for prespecified XRUNTEST time */ - xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST ); - XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime ); - waitTime( lRunTestTime ); - } - } - } while ( iMismatch && ( ucRepeat++ < ucMaxRepeat ) ); - } - - if ( iMismatch ) - { - XSVFDBG_PRINTF( 1, " TDO Expected = "); - XSVFDBG_PRINTLENVAL( 1, plvTdoExpected ); - XSVFDBG_PRINTF( 1, "\n"); - XSVFDBG_PRINTF( 1, " TDO Captured = "); - XSVFDBG_PRINTLENVAL( 1, plvTdoCaptured ); - XSVFDBG_PRINTF( 1, "\n"); - XSVFDBG_PRINTF( 1, " TDO Mask = "); - XSVFDBG_PRINTLENVAL( 1, plvTdoMask ); - XSVFDBG_PRINTF( 1, "\n"); - if ( ucMaxRepeat && ( ucRepeat > ucMaxRepeat ) ) - { - iErrorCode = XSVF_ERROR_MAXRETRIES; - } - else - { - iErrorCode = XSVF_ERROR_TDOMISMATCH; - } - } - - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfBasicXSDRTDO - * Description: Get the XSDRTDO parameters and execute the XSDRTDO command. - * This is the common function for all XSDRTDO commands. - * Parameters: pucTapState - Current TAP state. - * lShiftLengthBits - number of bits to shift. - * sShiftLengthBytes - number of bytes to read. - * plvTdi - ptr to lenval for TDI data. - * lvTdoCaptured - ptr to lenval for storing TDO data. - * iEndState - state in which to end the shift. - * lRunTestTime - amount of time to wait after the shift. - * ucMaxRepeat - maximum xc9500/xl retries. - * Returns: int - 0 = success; otherwise TDO mismatch. - *****************************************************************************/ -int xsvfBasicXSDRTDO( unsigned char* pucTapState, - long lShiftLengthBits, - short sShiftLengthBytes, - lenVal* plvTdi, - lenVal* plvTdoCaptured, - lenVal* plvTdoExpected, - lenVal* plvTdoMask, - unsigned char ucEndState, - long lRunTestTime, - unsigned char ucMaxRepeat ) -{ - readVal( plvTdi, sShiftLengthBytes ); - if ( plvTdoExpected ) - { - readVal( plvTdoExpected, sShiftLengthBytes ); - } - return( xsvfShift( pucTapState, XTAPSTATE_SHIFTDR, lShiftLengthBits, - plvTdi, plvTdoCaptured, plvTdoExpected, plvTdoMask, - ucEndState, lRunTestTime, ucMaxRepeat ) ); -} - -/***************************************************************************** - * Function: xsvfDoSDRMasking - * Description: Update the data value with the next XSDRINC data and address. - * Example: dataVal=0x01ff, nextData=0xab, addressMask=0x0100, - * dataMask=0x00ff, should set dataVal to 0x02ab - * Parameters: plvTdi - The current TDI value. - * plvNextData - the next data value. - * plvAddressMask - the address mask. - * plvDataMask - the data mask. - * Returns: void. - *****************************************************************************/ -#ifdef XSVF_SUPPORT_COMPRESSION -void xsvfDoSDRMasking( lenVal* plvTdi, - lenVal* plvNextData, - lenVal* plvAddressMask, - lenVal* plvDataMask ) -{ - int i; - unsigned char ucTdi; - unsigned char ucTdiMask; - unsigned char ucDataMask; - unsigned char ucNextData; - unsigned char ucNextMask; - short sNextData; - - /* add the address Mask to dataVal and return as a new dataVal */ - addVal( plvTdi, plvTdi, plvAddressMask ); - - ucNextData = 0; - ucNextMask = 0; - sNextData = plvNextData->len; - for ( i = plvDataMask->len - 1; i >= 0; --i ) - { - /* Go through data mask in reverse order looking for mask (1) bits */ - ucDataMask = plvDataMask->val[ i ]; - if ( ucDataMask ) - { - /* Retrieve the corresponding TDI byte value */ - ucTdi = plvTdi->val[ i ]; - - /* For each bit in the data mask byte, look for 1's */ - ucTdiMask = 1; - while ( ucDataMask ) - { - if ( ucDataMask & 1 ) - { - if ( !ucNextMask ) - { - /* Get the next data byte */ - ucNextData = plvNextData->val[ --sNextData ]; - ucNextMask = 1; - } - - /* Set or clear the data bit according to the next data */ - if ( ucNextData & ucNextMask ) - { - ucTdi |= ucTdiMask; /* Set bit */ - } - else - { - ucTdi &= ( ~ucTdiMask ); /* Clear bit */ - } - - /* Update the next data */ - ucNextMask <<= 1; - } - ucTdiMask <<= 1; - ucDataMask >>= 1; - } - - /* Update the TDI value */ - plvTdi->val[ i ] = ucTdi; - } - } -} -#endif /* XSVF_SUPPORT_COMPRESSION */ - -/*============================================================================ - * XSVF Command Functions (type = TXsvfDoCmdFuncPtr) - * These functions update pXsvfInfo->iErrorCode only on an error. - * Otherwise, the error code is left alone. - * The function returns the error code from the function. - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfDoIllegalCmd - * Description: Function place holder for illegal/unsupported commands. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo ) -{ - XSVFDBG_PRINTF2( 0, "ERROR: Encountered unsupported command #%d (%s)\n", - ((unsigned int)(pXsvfInfo->ucCommand)), - ((pXsvfInfo->ucCommand < XLASTCMD) - ? (xsvf_pzCommandName[pXsvfInfo->ucCommand]) - : "Unknown") ); - pXsvfInfo->iErrorCode = XSVF_ERROR_ILLEGALCMD; - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXCOMPLETE - * Description: XCOMPLETE (no parameters) - * Update complete status for XSVF player. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo ) -{ - pXsvfInfo->ucComplete = 1; - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXTDOMASK - * Description: XTDOMASK - * Prespecify the TDO compare mask. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo ) -{ - readVal( &(pXsvfInfo->lvTdoMask), pXsvfInfo->sShiftLengthBytes ); - XSVFDBG_PRINTF( 4, " TDO Mask = "); - XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvTdoMask) ); - XSVFDBG_PRINTF( 4, "\n"); - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXSIR - * Description: XSIR <(byte)shiftlen> - * Get the instruction and shift the instruction into the TAP. - * If prespecified XRUNTEST!=0, goto RUNTEST and wait after - * the shift for XRUNTEST usec. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSIR( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucShiftIrBits; - short sShiftIrBytes; - int iErrorCode; - - /* Get the shift length and store */ - readByte( &ucShiftIrBits ); - sShiftIrBytes = xsvfGetAsNumBytes( ucShiftIrBits ); - XSVFDBG_PRINTF1( 3, " XSIR length = %d\n", - ((unsigned int)ucShiftIrBits) ); - - if ( sShiftIrBytes > MAX_LEN ) - { - iErrorCode = XSVF_ERROR_DATAOVERFLOW; - } - else - { - /* Get and store instruction to shift in */ - readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( ucShiftIrBits ) ); - - /* Shift the data */ - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR, - ucShiftIrBits, &(pXsvfInfo->lvTdi), - /*plvTdoCaptured*/0, /*plvTdoExpected*/0, - /*plvTdoMask*/0, pXsvfInfo->ucEndIR, - pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 ); - } - - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSIR2 - * Description: XSIR <(2-byte)shiftlen> - * Get the instruction and shift the instruction into the TAP. - * If prespecified XRUNTEST!=0, goto RUNTEST and wait after - * the shift for XRUNTEST usec. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo ) -{ - long lShiftIrBits; - short sShiftIrBytes; - int iErrorCode; - - /* Get the shift length and store */ - readVal( &(pXsvfInfo->lvTdi), 2 ); - lShiftIrBits = value( &(pXsvfInfo->lvTdi) ); - sShiftIrBytes = xsvfGetAsNumBytes( lShiftIrBits ); - XSVFDBG_PRINTF1( 3, " XSIR2 length = %d\n", (int)lShiftIrBits); - - if ( sShiftIrBytes > MAX_LEN ) - { - iErrorCode = XSVF_ERROR_DATAOVERFLOW; - } - else - { - /* Get and store instruction to shift in */ - readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( lShiftIrBits ) ); - - /* Shift the data */ - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR, - lShiftIrBits, &(pXsvfInfo->lvTdi), - /*plvTdoCaptured*/0, /*plvTdoExpected*/0, - /*plvTdoMask*/0, pXsvfInfo->ucEndIR, - pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 ); - } - - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSDR - * Description: XSDR - * Shift the given TDI data into the JTAG scan chain. - * Compare the captured TDO with the expected TDO from the - * previous XSDRTDO command using the previously specified - * XTDOMASK. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDR( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes ); - /* use TDOExpected from last XSDRTDO instruction */ - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR, - pXsvfInfo->lShiftLengthBits, &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXRUNTEST - * Description: XRUNTEST - * Prespecify the XRUNTEST wait time for shift operations. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo ) -{ - readVal( &(pXsvfInfo->lvTdi), 4 ); - pXsvfInfo->lRunTestTime = value( &(pXsvfInfo->lvTdi) ); - XSVFDBG_PRINTF1( 3, " XRUNTEST = %ld\n", pXsvfInfo->lRunTestTime ); - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXREPEAT - * Description: XREPEAT - * Prespecify the maximum number of XC9500/XL retries. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo ) -{ - readByte( &(pXsvfInfo->ucMaxRepeat) ); - XSVFDBG_PRINTF1( 3, " XREPEAT = %d\n", - ((unsigned int)(pXsvfInfo->ucMaxRepeat)) ); - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXSDRSIZE - * Description: XSDRSIZE - * Prespecify the XRUNTEST wait time for shift operations. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - iErrorCode = XSVF_ERROR_NONE; - readVal( &(pXsvfInfo->lvTdi), 4 ); - pXsvfInfo->lShiftLengthBits = value( &(pXsvfInfo->lvTdi) ); - pXsvfInfo->sShiftLengthBytes= xsvfGetAsNumBytes( pXsvfInfo->lShiftLengthBits ); - XSVFDBG_PRINTF1( 3, " XSDRSIZE = %ld\n", pXsvfInfo->lShiftLengthBits ); - if ( pXsvfInfo->sShiftLengthBytes > MAX_LEN ) - { - iErrorCode = XSVF_ERROR_DATAOVERFLOW; - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSDRTDO - * Description: XSDRTDO - * Get the TDI and expected TDO values. Then, shift. - * Compare the expected TDO with the captured TDO using the - * prespecified XTDOMASK. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), - pXsvfInfo->lShiftLengthBits, - pXsvfInfo->sShiftLengthBytes, - &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), - pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, - pXsvfInfo->ucMaxRepeat ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSETSDRMASKS - * Description: XSETSDRMASKS - * - * Get the prespecified address and data mask for the XSDRINC - * command. - * Used for xc9500/xl compressed XSVF data. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -#ifdef XSVF_SUPPORT_COMPRESSION -int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo ) -{ - /* read the addressMask */ - readVal( &(pXsvfInfo->lvAddressMask), pXsvfInfo->sShiftLengthBytes ); - /* read the dataMask */ - readVal( &(pXsvfInfo->lvDataMask), pXsvfInfo->sShiftLengthBytes ); - - XSVFDBG_PRINTF( 4, " Address Mask = " ); - XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvAddressMask) ); - XSVFDBG_PRINTF( 4, "\n" ); - XSVFDBG_PRINTF( 4, " Data Mask = " ); - XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvDataMask) ); - XSVFDBG_PRINTF( 4, "\n" ); - - return( XSVF_ERROR_NONE ); -} -#endif /* XSVF_SUPPORT_COMPRESSION */ - -/***************************************************************************** - * Function: xsvfDoXSDRINC - * Description: XSDRINC - * ... - * Get the XSDRINC parameters and execute the XSDRINC command. - * XSDRINC starts by loading the first TDI shift value. - * Then, for numTimes, XSDRINC gets the next piece of data, - * replaces the bits from the starting TDI as defined by the - * XSETSDRMASKS.dataMask, adds the address mask from - * XSETSDRMASKS.addressMask, shifts the new TDI value, - * and compares the TDO to the expected TDO from the previous - * XSDRTDO command using the XTDOMASK. - * Used for xc9500/xl compressed XSVF data. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -#ifdef XSVF_SUPPORT_COMPRESSION -int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - int iDataMaskLen; - unsigned char ucDataMask; - unsigned char ucNumTimes; - unsigned char i; - - readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes ); - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR, - pXsvfInfo->lShiftLengthBits, - &(pXsvfInfo->lvTdi), &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat ); - if ( !iErrorCode ) - { - /* Calculate number of data mask bits */ - iDataMaskLen = 0; - for ( i = 0; i < pXsvfInfo->lvDataMask.len; ++i ) - { - ucDataMask = pXsvfInfo->lvDataMask.val[ i ]; - while ( ucDataMask ) - { - iDataMaskLen += ( ucDataMask & 1 ); - ucDataMask >>= 1; - } - } - - /* Get the number of data pieces, i.e. number of times to shift */ - readByte( &ucNumTimes ); - - /* For numTimes, get data, fix TDI, and shift */ - for ( i = 0; !iErrorCode && ( i < ucNumTimes ); ++i ) - { - readVal( &(pXsvfInfo->lvNextData), - xsvfGetAsNumBytes( iDataMaskLen ) ); - xsvfDoSDRMasking( &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvNextData), - &(pXsvfInfo->lvAddressMask), - &(pXsvfInfo->lvDataMask) ); - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), - XTAPSTATE_SHIFTDR, - pXsvfInfo->lShiftLengthBits, - &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), - pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, - pXsvfInfo->ucMaxRepeat ); - } - } - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} -#endif /* XSVF_SUPPORT_COMPRESSION */ - -/***************************************************************************** - * Function: xsvfDoXSDRBCE - * Description: XSDRB/XSDRC/XSDRE - * If not already in SHIFTDR, goto SHIFTDR. - * Shift the given TDI data into the JTAG scan chain. - * Ignore TDO. - * If cmd==XSDRE, then goto ENDDR. Otherwise, stay in ShiftDR. - * XSDRB, XSDRC, and XSDRE are the same implementation. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucEndDR; - int iErrorCode; - ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRE ) ? - pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR); - iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), - pXsvfInfo->lShiftLengthBits, - pXsvfInfo->sShiftLengthBytes, - &(pXsvfInfo->lvTdi), - /*plvTdoCaptured*/0, /*plvTdoExpected*/0, - /*plvTdoMask*/0, ucEndDR, - /*lRunTestTime*/0, /*ucMaxRepeat*/0 ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSDRTDOBCE - * Description: XSDRB/XSDRC/XSDRE - * If not already in SHIFTDR, goto SHIFTDR. - * Shift the given TDI data into the JTAG scan chain. - * Compare TDO, but do NOT use XTDOMASK. - * If cmd==XSDRTDOE, then goto ENDDR. Otherwise, stay in ShiftDR. - * XSDRTDOB, XSDRTDOC, and XSDRTDOE are the same implementation. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucEndDR; - int iErrorCode; - ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRTDOE ) ? - pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR); - iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), - pXsvfInfo->lShiftLengthBits, - pXsvfInfo->sShiftLengthBytes, - &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - /*plvTdoMask*/0, ucEndDR, - /*lRunTestTime*/0, /*ucMaxRepeat*/0 ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSTATE - * Description: XSTATE - * == XTAPSTATE; - * Get the state parameter and transition the TAP to that state. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucNextState; - int iErrorCode; - readByte( &ucNextState ); - iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucNextState ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXENDXR - * Description: XENDIR/XENDDR - * : 0 = RUNTEST; 1 = PAUSE. - * Get the prespecified XENDIR or XENDDR. - * Both XENDIR and XENDDR use the same implementation. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - unsigned char ucEndState; - - iErrorCode = XSVF_ERROR_NONE; - readByte( &ucEndState ); - if ( ( ucEndState != XENDXR_RUNTEST ) && ( ucEndState != XENDXR_PAUSE ) ) - { - iErrorCode = XSVF_ERROR_ILLEGALSTATE; - } - else - { - - if ( pXsvfInfo->ucCommand == XENDIR ) - { - if ( ucEndState == XENDXR_RUNTEST ) - { - pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST; - } - else - { - pXsvfInfo->ucEndIR = XTAPSTATE_PAUSEIR; - } - XSVFDBG_PRINTF1( 3, " ENDIR State = %s\n", - xsvf_pzTapState[ pXsvfInfo->ucEndIR ] ); - } - else /* XENDDR */ - { - if ( ucEndState == XENDXR_RUNTEST ) - { - pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST; - } - else - { - pXsvfInfo->ucEndDR = XTAPSTATE_PAUSEDR; - } - XSVFDBG_PRINTF1( 3, " ENDDR State = %s\n", - xsvf_pzTapState[ pXsvfInfo->ucEndDR ] ); - } - } - - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXCOMMENT - * Description: XCOMMENT - * == text comment; - * Arbitrary comment embedded in the XSVF. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo ) -{ - /* Use the comment for debugging */ - /* Otherwise, read through the comment to the end '\0' and ignore */ - unsigned char ucText; - - if ( xsvf_iDebugLevel > 0 ) - { - putc( ' ' ); - } - - do - { - readByte( &ucText ); - if ( xsvf_iDebugLevel > 0 ) - { - putc( ucText ? ucText : '\n' ); - } - } while ( ucText ); - - pXsvfInfo->iErrorCode = XSVF_ERROR_NONE; - - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXWAIT - * Description: XWAIT - * If not already in , then go to . - * Wait in for microseconds. - * Finally, if not already in , then goto . - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucWaitState; - unsigned char ucEndState; - long lWaitTime; - - /* Get Parameters */ - /* */ - readVal( &(pXsvfInfo->lvTdi), 1 ); - ucWaitState = pXsvfInfo->lvTdi.val[0]; - - /* */ - readVal( &(pXsvfInfo->lvTdi), 1 ); - ucEndState = pXsvfInfo->lvTdi.val[0]; - - /* */ - readVal( &(pXsvfInfo->lvTdi), 4 ); - lWaitTime = value( &(pXsvfInfo->lvTdi) ); - XSVFDBG_PRINTF2( 3, " XWAIT: state = %s; time = %ld\n", - xsvf_pzTapState[ ucWaitState ], lWaitTime ); - - /* If not already in , go to */ - if ( pXsvfInfo->ucTapState != ucWaitState ) - { - xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucWaitState ); - } - - /* Wait for microseconds */ - waitTime( lWaitTime ); - - /* If not already in , go to */ - if ( pXsvfInfo->ucTapState != ucEndState ) - { - xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucEndState ); - } - - return( XSVF_ERROR_NONE ); -} - - -/*============================================================================ - * Execution Control Functions - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfInitialize - * Description: Initialize the xsvf player. - * Call this before running the player to initialize the data - * in the SXsvfInfo struct. - * xsvfCleanup is called to clean up the data in SXsvfInfo - * after the XSVF is played. - * Parameters: pXsvfInfo - ptr to the XSVF information. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfInitialize( SXsvfInfo* pXsvfInfo ) -{ - /* Initialize values */ - pXsvfInfo->iErrorCode = xsvfInfoInit( pXsvfInfo ); - - if ( !pXsvfInfo->iErrorCode ) - { - /* Initialize the TAPs */ - pXsvfInfo->iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState), - XTAPSTATE_RESET ); - } - - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfRun - * Description: Run the xsvf player for a single command and return. - * First, call xsvfInitialize. - * Then, repeatedly call this function until an error is detected - * or until the pXsvfInfo->ucComplete variable is non-zero. - * Finally, call xsvfCleanup to cleanup any remnants. - * Parameters: pXsvfInfo - ptr to the XSVF information. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfRun( SXsvfInfo* pXsvfInfo ) -{ - /* Process the XSVF commands */ - if ( (!pXsvfInfo->iErrorCode) && (!pXsvfInfo->ucComplete) ) - { - /* read 1 byte for the instruction */ - readByte( &(pXsvfInfo->ucCommand) ); - ++(pXsvfInfo->lCommandCount); - - if ( pXsvfInfo->ucCommand < XLASTCMD ) - { - /* Execute the command. Func sets error code. */ - XSVFDBG_PRINTF1( 2, " %s\n", - xsvf_pzCommandName[pXsvfInfo->ucCommand] ); - /* If your compiler cannot take this form, - then convert to a switch statement */ -#if 0 /* test-only */ - xsvf_pfDoCmd[ pXsvfInfo->ucCommand ]( pXsvfInfo ); -#else - switch (pXsvfInfo->ucCommand) { - case 0: - xsvfDoXCOMPLETE(pXsvfInfo); /* 0 */ - break; - case 1: - xsvfDoXTDOMASK(pXsvfInfo); /* 1 */ - break; - case 2: - xsvfDoXSIR(pXsvfInfo); /* 2 */ - break; - case 3: - xsvfDoXSDR(pXsvfInfo); /* 3 */ - break; - case 4: - xsvfDoXRUNTEST(pXsvfInfo); /* 4 */ - break; - case 5: - xsvfDoIllegalCmd(pXsvfInfo); /* 5 */ - break; - case 6: - xsvfDoIllegalCmd(pXsvfInfo); /* 6 */ - break; - case 7: - xsvfDoXREPEAT(pXsvfInfo); /* 7 */ - break; - case 8: - xsvfDoXSDRSIZE(pXsvfInfo); /* 8 */ - break; - case 9: - xsvfDoXSDRTDO(pXsvfInfo); /* 9 */ - break; -#ifdef XSVF_SUPPORT_COMPRESSION - case 10: - xsvfDoXSETSDRMASKS(pXsvfInfo); /* 10 */ - break; - case 11: - xsvfDoXSDRINC(pXsvfInfo); /* 11 */ - break; -#else - case 10: - xsvfDoIllegalCmd(pXsvfInfo); /* 10 */ - break; - case 11: - xsvfDoIllegalCmd(pXsvfInfo); /* 11 */ - break; -#endif /* XSVF_SUPPORT_COMPRESSION */ - case 12: - xsvfDoXSDRBCE(pXsvfInfo); /* 12 */ - break; - case 13: - xsvfDoXSDRBCE(pXsvfInfo); /* 13 */ - break; - case 14: - xsvfDoXSDRBCE(pXsvfInfo); /* 14 */ - break; - case 15: - xsvfDoXSDRTDOBCE(pXsvfInfo); /* 15 */ - break; - case 16: - xsvfDoXSDRTDOBCE(pXsvfInfo); /* 16 */ - break; - case 17: - xsvfDoXSDRTDOBCE(pXsvfInfo); /* 17 */ - break; - case 18: - xsvfDoXSTATE(pXsvfInfo); /* 18 */ - break; - case 19: - xsvfDoXENDXR(pXsvfInfo); /* 19 */ - break; - case 20: - xsvfDoXENDXR(pXsvfInfo); /* 20 */ - break; - case 21: - xsvfDoXSIR2(pXsvfInfo); /* 21 */ - break; - case 22: - xsvfDoXCOMMENT(pXsvfInfo); /* 22 */ - break; - case 23: - xsvfDoXWAIT(pXsvfInfo); /* 23 */ - break; - } -#endif - } - else - { - /* Illegal command value. Func sets error code. */ - xsvfDoIllegalCmd( pXsvfInfo ); - } - } - - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfCleanup - * Description: cleanup remnants of the xsvf player. - * Parameters: pXsvfInfo - ptr to the XSVF information. - * Returns: void. - *****************************************************************************/ -void xsvfCleanup( SXsvfInfo* pXsvfInfo ) -{ - xsvfInfoCleanup( pXsvfInfo ); -} - - -/*============================================================================ - * xsvfExecute() - The primary entry point to the XSVF player - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfExecute - * Description: Process, interpret, and apply the XSVF commands. - * See port.c:readByte for source of XSVF data. - * Parameters: none. - * Returns: int - Legacy result values: 1 == success; 0 == failed. - *****************************************************************************/ -int xsvfExecute(void) -{ - SXsvfInfo xsvfInfo; - - xsvfInitialize( &xsvfInfo ); - - while ( !xsvfInfo.iErrorCode && (!xsvfInfo.ucComplete) ) - { - xsvfRun( &xsvfInfo ); - } - - if ( xsvfInfo.iErrorCode ) - { - XSVFDBG_PRINTF1( 0, "%s\n", xsvf_pzErrorName[ - ( xsvfInfo.iErrorCode < XSVF_ERROR_LAST ) - ? xsvfInfo.iErrorCode : XSVF_ERROR_UNKNOWN ] ); - XSVFDBG_PRINTF2( 0, "ERROR at or near XSVF command #%ld. See line #%ld in the XSVF ASCII file.\n", - xsvfInfo.lCommandCount, xsvfInfo.lCommandCount ); - } - else - { - XSVFDBG_PRINTF( 0, "SUCCESS - Completed XSVF execution.\n" ); - } - - xsvfCleanup( &xsvfInfo ); - - return( XSVF_ERRORCODE(xsvfInfo.iErrorCode) ); -} - - -/***************************************************************************** - * Function: do_cpld - * Description: main function. - * Specified here for creating stand-alone debug executable. - * Embedded users should call xsvfExecute() directly. - * Parameters: iArgc - number of command-line arguments. - * ppzArgv - array of ptrs to strings (command-line arguments). - * Returns: int - Legacy return value: 1 = success; 0 = error. - *****************************************************************************/ -int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int iErrorCode; - char* pzXsvfFileName; - unsigned long duration; - unsigned long long startClock, endClock; - - iErrorCode = XSVF_ERRORCODE( XSVF_ERROR_NONE ); - pzXsvfFileName = 0; - xsvf_iDebugLevel = 0; - - printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION); - printf("XSVF Filesize = %d bytes\n", filesize); - - /* Initialize the I/O. SetPort initializes I/O on first call */ - setPort( TMS, 1 ); - - /* Execute the XSVF in the file */ - startClock = get_ticks(); - iErrorCode = xsvfExecute(); - endClock = get_ticks(); - duration = (unsigned long)(endClock - startClock); - printf("\nExecution Time = %d seconds\n", (int)(duration/get_tbclk())); - - return( iErrorCode ); -} -U_BOOT_CMD( - cpld, 1, 1, do_cpld, - "cpld - Program onboard CPLD\n", - NULL - ); diff --git a/board/esd/common/xilinx_jtag/micro.h b/board/esd/common/xilinx_jtag/micro.h deleted file mode 100644 index 3c463ab..0000000 --- a/board/esd/common/xilinx_jtag/micro.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/***************************************************************************** - * File: micro.h - * Description: This header file contains the function prototype to the - * primary interface function for the XSVF player. - * Usage: FIRST - PORTS.C - * Customize the ports.c function implementations to establish - * the correct protocol for communicating with your JTAG ports - * (setPort() and readTDOBit()) and tune the waitTime() delay - * function. Also, establish access to the XSVF data source - * in the readByte() function. - * FINALLY - Call xsvfExecute(). - *****************************************************************************/ -#ifndef XSVF_MICRO_H -#define XSVF_MICRO_H - -/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */ -#define XSVF_LEGACY_SUCCESS 1 -#define XSVF_LEGACY_ERROR 0 - -/* 4.04 [NEW] Error codes for xsvfExecute. */ -/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */ -#define XSVF_ERROR_NONE 0 -#define XSVF_ERROR_UNKNOWN 1 -#define XSVF_ERROR_TDOMISMATCH 2 -#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */ -#define XSVF_ERROR_ILLEGALCMD 4 -#define XSVF_ERROR_ILLEGALSTATE 5 -#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/ -/* Insert new errors here */ -#define XSVF_ERROR_LAST 7 - -/***************************************************************************** - * Function: xsvfExecute - * Description: Process, interpret, and apply the XSVF commands. - * See port.c:readByte for source of XSVF data. - * Parameters: none. - * Returns: int - For error codes see above. - *****************************************************************************/ -int xsvfExecute(void); - -#endif /* XSVF_MICRO_H */ diff --git a/board/esd/common/xilinx_jtag/ports.c b/board/esd/common/xilinx_jtag/ports.c deleted file mode 100644 index 3ad94a5..0000000 --- a/board/esd/common/xilinx_jtag/ports.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*******************************************************/ -/* file: ports.c */ -/* abstract: This file contains the routines to */ -/* output values on the JTAG ports, to read */ -/* the TDO bit, and to read a byte of data */ -/* from the prom */ -/* */ -/*******************************************************/ - -#include -#include - -#include "ports.h" - -static unsigned long output = 0; -static int filepos = 0; -static int oldstate = 0; -static int newstate = 0; -static int readptr = 0; - -extern long filesize; -extern const unsigned char fpgadata[]; - - -/* if in debugging mode, then just set the variables */ -void setPort(short p,short val) -{ - if (p==TMS) { - if (val) { - output |= JTAG_TMS; - } else { - output &= ~JTAG_TMS; - } - } - if (p==TDI) { - if (val) { - output |= JTAG_TDI; - } else { - output &= ~JTAG_TDI; - } - } - if (p==TCK) { - if (val) { - output |= JTAG_TCK; - } else { - output &= ~JTAG_TCK; - } - out32(GPIO0_OR, output); - } -} - - -/* toggle tck LH */ -void pulseClock(void) -{ - setPort(TCK,0); /* set the TCK port to low */ - setPort(TCK,1); /* set the TCK port to high */ -} - - -/* read in a byte of data from the prom */ -void readByte(unsigned char *data) -{ - /* pretend reading using a file */ - *data = fpgadata[readptr++]; - newstate = (100 * filepos++) / filesize; - if (newstate != oldstate) { - printf("%4d\r\r\r\r", newstate); - oldstate = newstate; - } -} - -/* read the TDO bit from port */ -unsigned char readTDOBit(void) -{ - unsigned long inputs; - - inputs = in32(GPIO0_IR); - if (inputs & JTAG_TDO) - return 1; - else - return 0; -} - - -/* Wait at least the specified number of microsec. */ -/* Use a timer if possible; otherwise estimate the number of instructions */ -/* necessary to be run based on the microcontroller speed. For this example */ -/* we pulse the TCK port a number of times based on the processor speed. */ -void waitTime(long microsec) -{ - udelay(microsec); /* esd */ -} diff --git a/board/esd/common/xilinx_jtag/ports.h b/board/esd/common/xilinx_jtag/ports.h deleted file mode 100644 index 0e38990..0000000 --- a/board/esd/common/xilinx_jtag/ports.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*******************************************************/ -/* file: ports.h */ -/* abstract: This file contains extern declarations */ -/* for providing stimulus to the JTAG ports.*/ -/*******************************************************/ - -#ifndef ports_dot_h -#define ports_dot_h - -/* these constants are used to send the appropriate ports to setPort */ -/* they should be enumerated types, but some of the microcontroller */ -/* compilers don't like enumerated types */ -#define TCK (short) 0 -#define TMS (short) 1 -#define TDI (short) 2 - -/* - * Use CFG_FPGA_xxx defines from board include file. - */ -#define JTAG_TMS CFG_FPGA_PRG /* output */ -#define JTAG_TCK CFG_FPGA_CLK /* output */ -#define JTAG_TDI CFG_FPGA_DATA /* output */ -#define JTAG_TDO CFG_FPGA_DONE /* input */ - -/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */ -void setPort(short p, short val); - -/* read the TDO bit and store it in val */ -unsigned char readTDOBit(void); - -/* make clock go down->up->down*/ -void pulseClock(void); - -/* read the next byte of data from the xsvf file */ -void readByte(unsigned char *data); - -void waitTime(long microsec); - -#endif diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile deleted file mode 100644 index a60495a..0000000 --- a/board/esd/cpci2dp/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/cpci2dp/config.mk b/board/esd/cpci2dp/config.mk deleted file mode 100644 index 2da4c9f..0000000 --- a/board/esd/cpci2dp/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd CPCI2DP board -# - -TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c deleted file mode 100644 index df10c0e..0000000 --- a/board/esd/cpci2dp/cpci2dp.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * (C) Copyright 2005 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -int board_early_init_f (void) -{ - unsigned long cntrl0Reg; - - /* - * Setup GPIO pins (CS4+CS7 as GPIO) - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00900000); - - /* set output pins to high */ - out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED); - /* INTA# is open drain */ - out32(GPIO0_ODR, CFG_INTA_FAKE); - /* setup for output */ - out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) unused - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned long cntrl0Reg; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Select cts (and not dsr) on uart1 - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); - - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming CPCI2DP"); - } else { - puts(str); - } - - printf(" (Ver 1.0)"); - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 64 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CFG_EEPROM_WREN) -/* Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); - break; - } - } - return state; -} -#endif - -#if defined(CFG_EEPROM_WREN) -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD( - eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", - NULL - ); -#endif /* #if defined(CFG_EEPROM_WREN) */ diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c deleted file mode 100644 index de847f9..0000000 --- a/board/esd/cpci2dp/flash.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile deleted file mode 100644 index 9340a32..0000000 --- a/board/esd/cpci405/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk deleted file mode 100644 index 0be45c7..0000000 --- a/board/esd/cpci405/config.mk +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd CPCI405 boards -# - -ifeq ($(BOARD_REVISION),CPCI4052) -TEXT_BASE = 0xFFFC0000 -else -ifeq ($(BOARD_REVISION),CPCI405DT) -TEXT_BASE = 0xFFFC0000 -else -ifeq ($(BOARD_REVISION),CPCI405AB) -TEXT_BASE = 0xFFFC0000 -else -TEXT_BASE = 0xFFFD0000 -endif -endif -endif diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c deleted file mode 100644 index 2ab9673..0000000 --- a/board/esd/cpci405/cpci405.c +++ /dev/null @@ -1,799 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ -#if 0 -#define FPGA_DEBUG -#endif - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = -{ -#ifdef CONFIG_CPCI405_VER2 -# ifdef CONFIG_CPCI405AB -# include "fpgadata_cpci405ab.c" -# else -# include "fpgadata_cpci4052.c" -# endif -#else -# include "fpgadata_cpci405.c" -#endif -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -#include "../common/auto_update.h" - -#ifdef CONFIG_CPCI405AB -au_image_t au_image[] = { - {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT}, - {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR}, - {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, - {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, - {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT}, -}; -#else -#ifdef CONFIG_CPCI405_VER2 -au_image_t au_image[] = { - {"cpci4052/preinst.img", 0, -1, AU_SCRIPT}, - {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR}, - {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, - {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, - {"cpci4052/postinst.img", 0, 0, AU_SCRIPT}, -}; -#else -au_image_t au_image[] = { - {"cpci405/preinst.img", 0, -1, AU_SCRIPT}, - {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR}, - {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR}, - {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE}, - {"cpci405/postinst.img", 0, 0, AU_SCRIPT}, -}; -#endif -#endif - -int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); - - -/* Prototypes */ -int cpci405_version(void); -int gunzip(void *, int, unsigned char *, unsigned long *); -void lxt971_no_sleep(void); - - -int board_early_init_f (void) -{ -#ifndef CONFIG_CPCI405_VER2 - int index, len, i; - int status; -#endif - -#ifdef FPGA_DEBUG - DECLARE_GLOBAL_DATA_PTR; - - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f(); -#endif - - /* - * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) - */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ - out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ - out32(GPIO0_OR, 0); /* pull prg low */ - - /* - * Boot onboard FPGA - */ -#ifndef CONFIG_CPCI405_VER2 - if (cpci405_version() == 1) { - status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - DECLARE_GLOBAL_DATA_PTR; - - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f(); -#endif - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = fpgadata[index]; - printf("FPGA: %s\n", &(fpgadata[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - } -#endif /* !CONFIG_CPCI405_VER2 */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - if (cpci405_version() == 3) { - mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ - } else { - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - } - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int ctermm2(void) -{ -#ifdef CONFIG_CPCI405_VER2 - return 0; /* no, board is cpci405 */ -#else - if ((*(unsigned char *)0xf0000400 == 0x00) && - (*(unsigned char *)0xf0000401 == 0x01)) - return 0; /* no, board is cpci405 */ - else - return -1; /* yes, board is cterm-m2 */ -#endif -} - - -int cpci405_host(void) -{ - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) - return -1; /* yes, board is cpci405 host */ - else - return 0; /* no, board is cpci405 adapter */ -} - - -int cpci405_version(void) -{ - unsigned long cntrl0Reg; - unsigned long value; - - /* - * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); - udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ - - /* - * Restore GPIO settings - */ - mtdcr(cntrl0, cntrl0Reg); - - switch (value) { - case 0x00180000: - /* CS2==1 && CS3==1 -> version 1 */ - return 1; - case 0x00080000: - /* CS2==0 && CS3==1 -> version 2 */ - return 2; - case 0x00100000: - /* CS2==1 && CS3==0 -> version 3 */ - return 3; - case 0x00000000: - /* CS2==0 && CS3==0 -> version 4 */ - return 4; - default: - /* should not be reached! */ - return 2; - } -} - - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned long cntrl0Reg; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - -#ifdef CONFIG_CPCI405_VER2 - { - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - - /* - * On CPCI-405 version 2 the environment is saved in eeprom! - * FPGA can be gzip compressed (malloc) and booted this late. - */ - - if (cpci405_version() >= 2) { - /* - * Setup GPIO pins (CS6+CS7 as GPIO) - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00300000); - - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - /* restore gpio/cs settings */ - mtdcr(cntrl0, cntrl0Reg); - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - if (cpci405_version() == 3) { - volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; - volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR; - - /* - * Enable outputs in fpga on version 3 board - */ - *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT; - - /* - * Set outputs to 0 - */ - *leds = 0x00; - - /* - * Reset external DUART - */ - *fpga_mode |= CFG_FPGA_MODE_DUART_RESET; - udelay(100); - *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET); - } - } - else { - puts("\n*** U-Boot Version does not match Board Version!\n"); - puts("*** CPCI-405 Version 1.x detected!\n"); - puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n"); - } - } - -#else /* CONFIG_CPCI405_VER2 */ - -#if 0 /* test-only: code-plug now not relavant for ip-address any more */ - /* - * Generate last byte of ip-addr from code-plug @ 0xf0000400 - */ - if (ctermm2()) { - char str[32]; - unsigned char ipbyte = *(unsigned char *)0xf0000400; - - /* - * Only overwrite ip-addr with allowed values - */ - if ((ipbyte != 0x00) && (ipbyte != 0xff)) { - bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte; - sprintf(str, "%ld.%ld.%ld.%ld", - (bd->bi_ip_addr & 0xff000000) >> 24, - (bd->bi_ip_addr & 0x00ff0000) >> 16, - (bd->bi_ip_addr & 0x0000ff00) >> 8, - (bd->bi_ip_addr & 0x000000ff)); - setenv("ipaddr", str); - } - } -#endif - - if (cpci405_version() >= 2) { - puts("\n*** U-Boot Version does not match Board Version!\n"); - puts("*** CPCI-405 Board Version 2.x detected!\n"); - puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n"); - } - -#endif /* CONFIG_CPCI405_VER2 */ - - /* - * Select cts (and not dsr) on uart1 - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ -#ifndef CONFIG_CPCI405_VER2 - int index; - int len; -#endif - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - unsigned short ver; - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming CPCI405"); - } else { - puts(str); - } - - ver = cpci405_version(); - printf(" (Ver %d.x, ", ver); - -#if 0 /* test-only */ - if (ver >= 2) { - volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1; - - if (*fpga_status & CFG_FPGA_STATUS_FLASH) { - puts ("FLASH Bank B, "); - } else { - puts ("FLASH Bank A, "); - } - } -#endif - - if (ctermm2()) { - char str[4]; - - /* - * Read board-id and save in env-variable - */ - sprintf(str, "%d", *(unsigned char *)0xf0000400); - setenv("boardid", str); - printf("CTERM-M2 - Id=%s)", str); - } else { - if (cpci405_host()) { - puts ("PCI Host Version)"); - } else { - puts ("PCI Adapter Version)"); - } - } - -#ifndef CONFIG_CPCI405_VER2 - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = fpgadata[index]; - printf("%s ", &(fpgadata[index+1])); - index += len+3; - } -#endif - - putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_CPCI405_VER2 -#ifdef CONFIG_IDE_RESET - -void ide_set_reset(int on) -{ - volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; - - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_MODE_CF_RESET; - } -} - -#endif /* CONFIG_IDE_RESET */ -#endif /* CONFIG_CPCI405_VER2 */ - - -#ifdef CONFIG_CPCI405AB - -#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ - |= CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ - &= ~CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \ - & CFG_FPGA_MODE_1WIRE) - -/* - * Generate a 1-wire reset, return 1 if no presence detect was found, - * return 0 otherwise. - * (NOTE: Does not handle alarm presence from DS2404/DS1994) - */ -int OWTouchReset(void) -{ - int result; - - ONE_WIRE_CLEAR; - udelay(480); - ONE_WIRE_SET; - udelay(70); - - result = ONE_WIRE_GET; - - udelay(410); - return result; -} - - -/* - * Send 1 a 1-wire write bit. - * Provide 10us recovery time. - */ -void OWWriteBit(int bit) -{ - if (bit) { - /* - * write '1' bit - */ - ONE_WIRE_CLEAR; - udelay(6); - ONE_WIRE_SET; - udelay(64); - } else { - /* - * write '0' bit - */ - ONE_WIRE_CLEAR; - udelay(60); - ONE_WIRE_SET; - udelay(10); - } -} - - -/* - * Read a bit from the 1-wire bus and return it. - * Provide 10us recovery time. - */ -int OWReadBit(void) -{ - int result; - - ONE_WIRE_CLEAR; - udelay(6); - ONE_WIRE_SET; - udelay(9); - - result = ONE_WIRE_GET; - - udelay(55); - return result; -} - - -void OWWriteByte(int data) -{ - int loop; - - for (loop=0; loop<8; loop++) { - OWWriteBit(data & 0x01); - data >>= 1; - } -} - - -int OWReadByte(void) -{ - int loop, result = 0; - - for (loop=0; loop<8; loop++) { - result >>= 1; - if (OWReadBit()) { - result |= 0x80; - } - } - - return result; -} - - -int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - volatile unsigned short val; - int result; - int i; - unsigned char ow_id[6]; - char str[32]; - unsigned char ow_crc; - - /* - * Clear 1-wire bit (open drain with pull-up) - */ - val = *(volatile unsigned short *)0xf0400000; - val &= ~0x1000; /* clear 1-wire bit */ - *(volatile unsigned short *)0xf0400000 = val; - - result = OWTouchReset(); - if (result != 0) { - puts("No 1-wire device detected!\n"); - } - - OWWriteByte(0x33); /* send read rom command */ - OWReadByte(); /* skip family code ( == 0x01) */ - for (i=0; i<6; i++) { - ow_id[i] = OWReadByte(); - } - ow_crc = OWReadByte(); /* read crc */ - - sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]); - printf("Setting environment variable 'ow_id' to %s\n", str); - setenv("ow_id", str); - - return 0; -} -U_BOOT_CMD( - onewire, 1, 1, do_onewire, - "onewire - Read 1-write ID\n", - NULL - ); - - -#define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ -#define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ - -/* - * Write backplane ip-address... - */ -int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - DECLARE_GLOBAL_DATA_PTR; - - bd_t *bd = gd->bd; - char *buf; - ulong crc; - char str[32]; - char *ptr; - IPaddr_t ipaddr; - - buf = malloc(CFG_ENV_SIZE_2); - if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) { - puts("\nError reading backplane EEPROM!\n"); - } else { - crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4); - if (crc != *(ulong *)buf) { - printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf); - return -1; - } - - /* - * Find bp_ip - */ - ptr = strstr(buf+4, "bp_ip="); - if (ptr == NULL) { - printf("ERROR: bp_ip not found!\n"); - return -1; - } - ptr += 6; - ipaddr = string_to_ip(ptr); - - /* - * Update whole ip-addr - */ - bd->bi_ip_addr = ipaddr; - sprintf(str, "%ld.%ld.%ld.%ld", - (bd->bi_ip_addr & 0xff000000) >> 24, - (bd->bi_ip_addr & 0x00ff0000) >> 16, - (bd->bi_ip_addr & 0x0000ff00) >> 8, - (bd->bi_ip_addr & 0x000000ff)); - setenv("ipaddr", str); - printf("Updated ip_addr from bp_eeprom to %s!\n", str); - } - - free(buf); - - return 0; -} -U_BOOT_CMD( - getbpip, 1, 1, do_get_bpip, - "getbpip - Update IP-Address with Backplane IP-Address\n", - NULL - ); - -/* - * Set and print backplane ip... - */ -int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - char *buf; - char str[32]; - ulong crc; - - if (argc < 2) { - puts("ERROR!\n"); - return -1; - } - - printf("Setting bp_ip to %s\n", argv[1]); - buf = malloc(CFG_ENV_SIZE_2); - memset(buf, 0, CFG_ENV_SIZE_2); - sprintf(str, "bp_ip=%s", argv[1]); - strcpy(buf+4, str); - crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4); - *(ulong *)buf = crc; - - if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) { - puts("\nError writing backplane EEPROM!\n"); - } - - free(buf); - - return 0; -} -U_BOOT_CMD( - setbpip, 2, 1, do_set_bpip, - "setbpip - Write Backplane IP-Address\n", - NULL - ); - -#endif /* CONFIG_CPCI405AB */ diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c deleted file mode 100644 index e766895..0000000 --- a/board/esd/cpci405/flash.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long calc_size(unsigned long size) -{ - switch (size) { - case 1 << 20: - return 0; - case 2 << 20: - return 1; - case 4 << 20: - return 2; - case 8 << 20: - return 3; - case 16 << 20: - return 4; - default: - return 0; - } -} - - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - base_b0 = FLASH_BASE0_PRELIM; - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - base_b1 = FLASH_BASE1_PRELIM; - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - if (size_b1 < (1 << 20)) { - /* minimum CS size on PPC405GP is 1MB !!! */ - size_b1 = 1 << 20; - } - base_b1 = -size_b1; - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); - pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17); - mtdcr (ebccfgd, pbcr); -#if 0 /* test-only */ - printf("size_b1=%x base_b1=%x pb1cr = %x\n", - size_b1, base_b1, pbcr); /* test-only */ -#endif - } - - if (size_b0) { - if (size_b0 < (1 << 20)) { - /* minimum CS size on PPC405GP is 1MB !!! */ - size_b0 = 1 << 20; - } - base_b0 = base_b1 - size_b0; - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); - pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17); - mtdcr (ebccfgd, pbcr); -#if 0 /* test-only */ - printf("size_b0=%x base_b0=%x pb0cr = %x\n", - size_b0, base_b0, pbcr); /* test-only */ -#endif - } - - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b1 + size_b1 - monitor_flash_len, - base_b1 + size_b1 - 1, &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect (FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/cpci405/fpgadata_cpci405.c b/board/esd/cpci405/fpgadata_cpci405.c deleted file mode 100644 index 20e61c1..0000000 --- a/board/esd/cpci405/fpgadata_cpci405.c +++ /dev/null @@ -1,342 +0,0 @@ - 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d, - 0x63,0x70,0x63,0x69,0x34,0x30,0x35,0x32,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b, - 0x73,0x30,0x35,0x78,0x6c,0x76,0x71,0x31,0x30,0x30,0x00,0x63,0x00,0x0b,0x32,0x30, - 0x30,0x31,0x2f,0x30,0x35,0x2f,0x31,0x30,0x00,0x64,0x00,0x09,0x31,0x35,0x3a,0x31, - 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0x65,0x2d,0x67,0xda,0x88,0xb5,0xfc,0x7d,0x5c,0xcb,0xd6,0x12,0x9e,0xb4,0x96,0xd5, - 0x3f,0xb6,0x96,0x9d,0x36,0x7f,0xe4,0xf9,0x8c,0x5b,0xcb,0xc0,0xd7,0xb2,0xb5,0x84, - 0xad,0x45,0x8d,0x46,0xaf,0xf2,0x27,0xdf,0xe7,0x4f,0xf1,0x75,0x7f,0xca,0x73,0x86, - 0x0c,0x71,0xbe,0xc8,0xe7,0xab,0xb5,0xfc,0xff,0xbe,0x36,0xff,0xf9,0x27,0x04,0xba, - 0x44,0xf8,0xff,0x46,0xae,0xff,0x2f,0xfe,0xd3,0xaf,0x3e,0x5f,0x7d,0xbe,0xfa,0x7c, - 0xf5,0xf9,0xea,0xf3,0xd5,0xe7,0xab,0xcf,0x57,0x9f,0xff,0x5f,0x7c,0x78,0xbc,0x44, - 0x78,0xbc,0x64,0xfc,0x3f,0xdd,0x97,0xaf,0x3e,0x5f,0x7d,0xbe,0xfa,0x7c,0xf5,0xf9, - 0xea,0xf3,0xd5,0xe7,0xab,0xcf,0x57,0x9f,0xff,0xbb,0x3f,0x21,0x2e,0x0c,0x7b,0xa3, - 0x36,0x04,0xbc,0xa8,0x2b,0x87,0xc0,0xc8,0xfb,0xd3,0xfe,0x1d,0x6f,0xef,0x0a,0x41, - 0x42,0xca,0xdc,0xa7,0xe7,0x1f,0x27,0xf6,0xf5,0xff,0x02,0xd6,0x2c,0x67,0x26,0xbd, - 0xa4,0x00,0x00, diff --git a/board/esd/cpci405/u-boot.lds b/board/esd/cpci405/u-boot.lds deleted file mode 100644 index f7a20d1..0000000 --- a/board/esd/cpci405/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/cpci440/Makefile b/board/esd/cpci440/Makefile deleted file mode 100644 index 84d44fb..0000000 --- a/board/esd/cpci440/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o strataflash.o ../common/misc.o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/cpci440/config.mk b/board/esd/cpci440/config.mk deleted file mode 100644 index 8e5f63f..0000000 --- a/board/esd/cpci440/config.mk +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 - -ifeq ($(ramsym),1) -TEXT_BASE = 0x07FD0000 -else -TEXT_BASE = 0xFFFC0000 -#TEXT_BASE = 0x01fc0000 -endif - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 -endif diff --git a/board/esd/cpci440/cpci440.c b/board/esd/cpci440/cpci440.c deleted file mode 100644 index 43d8a3b..0000000 --- a/board/esd/cpci440/cpci440.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2002 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -extern void lxt971_no_sleep(void); - - -long int fixed_sdram( void ); - -int board_early_init_f (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr( ebccfga, xbcfg ); - reg = mfdcr( ebccfgd ); - mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */ - - mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */ - mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */ - /* test-only: other regs still missing... */ - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr( uic0sr, 0xffffffff ); /* clear all */ - mtdcr( uic0er, 0x00000000 ); /* disable all */ - mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */ - mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */ - mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */ - mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */ - mtdcr( uic0sr, 0xffffffff ); /* clear all */ - - mtdcr( uic1sr, 0xffffffff ); /* clear all */ - mtdcr( uic1er, 0x00000000 ); /* disable all */ - mtdcr( uic1cr, 0x00000000 ); /* all non-critical */ - mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */ - mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */ - mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */ - mtdcr( uic1sr, 0xffffffff ); /* clear all */ - - return 0; -} - - -int checkboard (void) -{ - sys_info_t sysinfo; - get_sys_info(&sysinfo); - - printf("Board: esd CPCI-440\n"); - printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000); - printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000); - printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000); - printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000); - printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return (0); -} - - -long int initdram (int board_type) -{ - long dram_size = 0; - - dram_size = fixed_sdram(); - return dram_size; -} - - -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 64 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram( void ) -{ - uint reg; - -#if 1 /* test-only */ - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */ - mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */ - mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */ - mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */ - mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/ - mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */ - udelay( 400 ); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */ - for(;;) - { - mfsdram( mem_mcsts, reg ); - if( reg & 0x80000000 ) - break; - } - - return( 64 * 1024 * 1024 ); /* 64 MB */ -#else - return( 32 * 1024 * 1024 ); /* 64 MB */ -#endif -} diff --git a/board/esd/cpci440/init.S b/board/esd/cpci440/init.S deleted file mode 100644 index 82f37fd..0000000 --- a/board/esd/cpci440/init.S +++ /dev/null @@ -1,94 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X ) - tlbtab_end diff --git a/board/esd/cpci440/strataflash.c b/board/esd/cpci440/strataflash.c deleted file mode 100644 index 2f055c2..0000000 --- a/board/esd/cpci440/strataflash.c +++ /dev/null @@ -1,755 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;iportwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; iportwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; isector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * - */ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpci440/u-boot.lds b/board/esd/cpci440/u-boot.lds deleted file mode 100644 index 57220d3..0000000 --- a/board/esd/cpci440/u-boot.lds +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : -/* .resetvec 0x01FFFFFC :*/ - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : -/* .bootpg 0x01FFF000 :*/ - { - cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/esd/cpci440/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile deleted file mode 100644 index 2ca73a9..0000000 --- a/board/esd/cpci5200/Makefile +++ /dev/null @@ -1,53 +0,0 @@ - -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -# Objects for Xilinx JTAG programming (CPLD) -# CPLD = ../common/xilinx_jtag/lenval.o \ -# ../common/xilinx_jtag/micro.o \ -# ../common/xilinx_jtag/ports.o - -# OBJS = $(BOARD).o flash.o $(CPLD) -OBJS = $(BOARD).o strataflash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/esd/cpci5200/config.mk b/board/esd/cpci5200/config.mk deleted file mode 100644 index 07b5de1..0000000 --- a/board/esd/cpci5200/config.mk +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# IceCube board: -# -# Valid values for TEXT_BASE are: -# -# 0xFFF00000 boot high (standard configuration) -# 0xFF000000 boot low for 16 MiB boards -# 0xFF800000 boot low for 8 MiB boards -# 0x00100000 boot from RAM (for testing only) -# - -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -## Standard: boot high -TEXT_BASE = 0xFFF00000 -## For testing: boot from RAM -# TEXT_BASE = 0x00100000 -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c deleted file mode 100644 index 6c98f13..0000000 --- a/board/esd/cpci5200/cpci5200.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * cpci5200.c - main board support/init for the esd cpci5200. - */ - -#include -#include -#include -#include - -#include "mt46v16m16-75.h" - -void init_ata_reset(void); - -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register: extended mode */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. - */ - -long int initdram(int board_type) -{ - ulong dramsize = 0; - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - - /* set tap delay */ - *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); - - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = - 0x13 + __builtin_ffs(dramsize >> 20) - 1; - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ - } else { -#if 0 - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ -#else - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = - 0x13 + __builtin_ffs(0x08000000 >> 20) - 1; - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */ -#endif - } - -#if 0 - /* find RAM size using SDRAM CS1 only */ - sdram_start(0); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); - sdram_start(1); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); - sdram_start(0); -#endif - /* set SDRAM CS1 size according to the amount of RAM found */ - - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - - init_ata_reset(); - return (dramsize); -} - -int checkboard(void) -{ - puts("Board: esd CPCI5200 (cpci5200)\n"); - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -void flash_afterinit(ulong size) -{ - if (size == 0x02000000) { - /* adjust mapping */ - *(vu_long *) MPC5XXX_BOOTCS_START = - *(vu_long *) MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); - *(vu_long *) MPC5XXX_BOOTCS_STOP = - *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); - } -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void - ) { - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) - -#define GPIO_PSC1_4 0x01000000UL - -void init_ide_reset(void) -{ - debug("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; -} - -void ide_set_reset(int idereset) -{ - debug("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; - } -} -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ - -#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) -#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C) -#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010) -#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014) - -#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020) -#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028) -#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C) -#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C) - -#define GPIO_WU6 0x40000000UL -#define GPIO_USB0 0x00010000UL -#define GPIO_USB9 0x08000000UL -#define GPIO_USB9S 0x00080000UL - -void init_ata_reset(void) -{ - debug("init_ata_reset\n"); - - /* Configure GPIO_WU6 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; - __asm__ volatile ("sync"); - - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0; - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0; - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0; - __asm__ volatile ("sync"); - - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9; - __asm__ volatile ("sync"); - - if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) { - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0; - __asm__ volatile ("sync"); - } -} - -int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - int i; - volatile unsigned long *ptr; - - addr = simple_strtol(argv[1], NULL, 16); - size = simple_strtol(argv[2], NULL, 16); - - printf("\nWriting at addr %08x, size %08x.\n", addr, size); - - while (1) { - ptr = (volatile unsigned long *)addr; - for (i = 0; i < (size >> 2); i++) { - *ptr++ = i; - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - putc('.'); - } - return 0; -} - -U_BOOT_CMD(writepci, 3, 1, do_writepci, - "writepci- Write some data to pcibus\n", - " \n" " - Write some data to pcibus.\n"); diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h deleted file mode 100644 index 22d0a55..0000000 --- a/board/esd/cpci5200/mt46v16m16-75.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 1 /* is DDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x705f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c deleted file mode 100644 index d76af02..0000000 --- a/board/esd/cpci5200/strataflash.c +++ /dev/null @@ -1,804 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char *cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, - uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, - uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size(ulong base, int banknum); -static int flash_write_cfiword(flash_info_t * info, ulong dest, - cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, - ulong tout, char *prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, - int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *) (info->start[sect] + (offset * info->portwidth))); -} - -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar *addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2 * info->portwidth) - 1] << 8) | - addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar *addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2 * info->portwidth) - 1] << 24) | - (addr[(info->portwidth) - 1] << 16) | - (addr[(4 * info->portwidth) - 1] << 8) | - addr[(3 * info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init(void) -{ - unsigned long size; - int i; - unsigned long address; - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf - ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, flash_info[0].size, flash_info[i].size << 20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - for (i = 0; - flash_info[0].start[i] < CFG_MONITOR_BASE + monitor_flash_len - 1; - i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if (info->flash_id != FLASH_MAN_CFI) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if (flash_full_status_check - (info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf(" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3), (info->chipwidth << 3)); - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf - (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, - info->buffer_size); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n"); - printf(" %08lX%5s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if ((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for (i = 0; i < aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *) cp)); - - for (; (i < info->portwidth) && (cnt > 0); i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *) cp)); - if ((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while (cnt >= info->portwidth) { - i = info->buffer_size > cnt ? cnt : info->buffer_size; - if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -= i; - } -#else - /* handle the aligned part */ - while (cnt >= info->portwidth) { - cword.l = 0; - for (i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if ((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i < info->portwidth; ++i, ++cp) { - flash_add_byte(info, &cword, (*(uchar *) cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t * info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if (prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if ((retcode = - flash_full_status_check(info, sector, info->erase_blk_tout, - prot ? "protect" : "unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if (prot == 0) { - int i; - for (i = 0; i < info->sector_count; i++) { - if (info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} - -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, - char *prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer(0); - while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, - info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, - ulong tout, char *prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if ((retcode == ERR_OK) - && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt, - info->start[sector]); - if (flash_isset - (info, sector, 0, - FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { - printf("Command Sequence Error.\n"); - } else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) { - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) { - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} - -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c) -{ - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf) -{ - int i; - uchar *cp = (uchar *) cmdbuf; - for (i = 0; i < info->portwidth; i++) - *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, - uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch (info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * - */ -static int flash_detect_cfi(flash_info_t * info) -{ - - for (info->portwidth = FLASH_CFI_8BIT; - info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) { - for (info->chipwidth = FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, - FLASH_CMD_CFI); - if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') - && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, - 'R') - && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, - 'Y')) - return 1; - } - } - return 0; -} - -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size(ulong base, int banknum) -{ - flash_info_t *info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio = 0; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; -#if 0 - invalidate_dcache_range(base, base + 0x400); -#endif - if (flash_detect_cfi(info)) { - - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = - flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); - - sect_cnt = 0; - sector = base; - for (i = 0; i < num_erase_regions; i++) { - if (i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = - flash_read_long(info, 0, - FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = - (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) + 1; - for (j = 0; j < erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = - flash_isset(info, sect_cnt, - FLASH_OFFSET_PROTECT, - FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = - (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * - size_ratio; - info->buffer_size = - (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = - (tmp * - (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = - (tmp * - (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = - (tmp * - (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) / - 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif -#ifdef DEBUG_FLASH - printf("size=%08x sectors=%08x \n", info->size, info->sector_count); -#endif - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *) dest; - - /* Check if Flash is (sufficiently) erased */ - switch (info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if (!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t * info, ulong addr) -{ - int sector; - for (sector = info->sector_count - 1; sector >= 0; sector--) { - if (addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, - int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *) dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if ((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) { - switch (info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, - FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = - flash_full_status_check(info, sector, - info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpci5200/u-boot.lds b/board/esd/cpci5200/u-boot.lds deleted file mode 100644 index f23432e..0000000 --- a/board/esd/cpci5200/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/cpci750/64360.h b/board/esd/cpci750/64360.h deleted file mode 100644 index 262abf3..0000000 --- a/board/esd/cpci750/64360.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * for cpci750 Reinhard Arlt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * main board support/init for the cpci750. - */ - -#ifndef __64360_H__ -#define __64360_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_SINGLE_CPU (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64360_H__ */ diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile deleted file mode 100644 index 0486729..0000000 --- a/board/esd/cpci750/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -SOBJS = misc.o - -OBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \ - mv_eth.o mpsc.o i2c.o \ - sdram_init.o strataflash.o ide.o - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/cpci750/config.mk b/board/esd/cpci750/config.mk deleted file mode 100644 index 7795dfa..0000000 --- a/board/esd/cpci750/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2004 -# Reinhard Arlt -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# cpci750 board -# - -TEXT_BASE = 0xfff00000 diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c deleted file mode 100644 index e4b062b..0000000 --- a/board/esd/cpci750/cpci750.c +++ /dev/null @@ -1,885 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com - * modifications for the cpci750 by reinhard.arlt@esd-electronics.com - */ - -/* - * cpci750.c - main board support/init for the esd cpci750. - */ - -#include -#include <74xx_7xx.h> -#include "../../Marvell/include/memory.h" -#include "../../Marvell/include/pci.h" -#include "../../Marvell/include/mv_gen_reg.h" -#include - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64360.h" -#include "mv_regs.h" - -#undef DEBUG -/*#define DEBUG */ - -#ifdef CONFIG_PCI -#define MAP_PCI -#endif /* of CONFIG_PCI */ - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -extern void flush_data_cache (void); -extern void invalidate_l1_instruction_cache (void); - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; -int display_mem_map (void); - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void my_remap_gt_regs (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - -/* original ppcboot 1.1.6 source - - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -original ppcboot 1.1.6 source end */ - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); -} - -#ifdef CONFIG_PCI - -static void gt_pci_config (void) -{ - unsigned int stat; - unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ - - /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's - * config registers by writing ones to the bus and device. - * We then update the Virtual register with the correct value for the bus and device. - */ - if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - - GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); - - } - if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); - } - - /* Enable master */ - PCI_MASTER_ENABLE (0, SELF); - PCI_MASTER_ENABLE (1, SELF); - - /* Enable PCI0/1 Mem0 and IO 0 disable all others */ - GT_REG_READ (BASE_ADDR_ENABLE, &stat); - stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 - << - 18); - stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); - GT_REG_WRITE (BASE_ADDR_ENABLE, stat); - - /* ronen- add write to pci remap registers for 64460. - in 64360 when writing to pci base go and overide remap automaticaly, - in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); - - /* PCI interface settings */ - /* Timeout set to retry forever */ - GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); - GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); - - /* ronen - enable only CS0 and Internal reg!! */ - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - -/*ronen update the pci internal registers base address.*/ -#ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) - pciWriteConfigReg (stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CFG_GT_REGS); -#endif - -} -#endif - -/* Setup CPU interface paramaters */ -static void gt_cpu_config (void) -{ - cpu_t cpu = get_cpu_type (); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD (CPU_CONFIGURATION); - - /* set the SINGLE_CPU bit see MV64360 P.399 */ -#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ - tmp |= CPU_CONF_SINGLE_CPU; -#endif - - tmp &= ~CPU_CONF_AACK_DELAY_2; - - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - - tmp |= CPU_CONF_PIPELINE; - - GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ - - /* CPU master control register */ - tmp = GTREGREAD (CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command (603e, 750) - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); - - /* No PCI in first release of Port To_do: enable it. */ -#ifdef CONFIG_PCI - gt_pci_config (); -#endif - /* mask all external interrupt sources */ - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - /* new in MV6436x */ - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); - /* --------------------- */ - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - /* does not exist in MV6436x - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - --------------------- */ - - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM ???? - * 1 - RTC ???? - * 2 - UART ???? - * 3 - Flash checked 32Bit Intel Strata - * boot - BootCS checked 8Bit 29LV040B - * - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ - - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); - - - /* configure device timing */ - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_DEV3_PAR); - -#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CFG_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ -#endif - - - gt_cpu_config (); - - /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); - - GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); - DEBUG_LED0_ON (); - DEBUG_LED1_ON (); - DEBUG_LED2_ON (); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r () -{ - icache_enable (); -#ifdef CFG_L2 - l2cache_enable (); -#endif -#ifdef CONFIG_MPSC - - mpsc_sdma_init (); - mpsc_init2 (); -#endif - -#if 0 - /* disable the dcache and MMU */ - dcache_lock (); -#endif - return 0; -} - -void after_reloc (ulong dest_addr, gd_t * gd) -{ - - memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE); - - display_mem_map (); - /* now, jump to the main ppcboot board init code */ - board_init_r (gd, dest_addr); - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * right now, assume borad type. (there is just one...after all) - */ - -int checkboard (void) -{ - int l_type = 0; - - printf ("BOARD: %s\n", CFG_BOARD_NAME); - return (l_type); -} - -/* utility functions */ -void debug_led (int led, int mode) -{ -} - -int display_mem_map (void) -{ - int i, j; - unsigned int base, size, width; - - /* SDRAM */ - printf ("SD (DDR) RAM\n"); - for (i = 0; i <= BANK3; i++) { - base = memoryGetBankBaseAddress (i); - size = memoryGetBankSize (i); - if (size != 0) { - printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", - i, base, size >> 20); - } - } -#ifdef CONFIG_PCI - /* CPU's PCI windows */ - for (i = 0; i <= PCI_HOST1; i++) { - printf ("\nCPU's PCI %d windows\n", i); - base = pciGetSpaceBase (i, PCI_IO); - size = pciGetSpaceSize (i, PCI_IO); - printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, - size >> 20); - for (j = 0; - j <= - PCI_REGION0 - /*ronen currently only first PCI MEM is used 3 */ ; - j++) { - base = pciGetSpaceBase (i, j); - size = pciGetSpaceSize (i, j); - printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); - } - } -#endif /* of CONFIG_PCI */ - /* Devices */ - printf ("\nDEVICES\n"); - for (i = 0; i <= DEVICE3; i++) { - base = memoryGetDeviceBaseAddress (i); - size = memoryGetDeviceSize (i); - width = memoryGetDeviceWidth (i) * 8; - printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); - if (i == 0) - printf ("\t- FLASH\n"); - else if (i == 1) - printf ("\t- FLASH\n"); - else if (i == 2) - printf ("\t- FLASH\n"); - else - printf ("\t- RTC/REGS/CAN\n"); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize (BOOT_DEVICE); - width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; - printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n", - base, size >> 20, width); - return (0); -} - -/* DRAM check routines copied from gw8260 */ - -#if defined (CFG_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CFG_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaLL, - 0xccccccccccccccccLL, - 0xf0f0f0f0f0f0f0f0LL, - 0xff00ff00ff00ff00LL, - 0xffff0000ffff0000LL, - 0xffffffff00000000LL, - 0x00000000ffffffffLL, - 0x0000ffff0000ffffLL, - 0x00ff00ff00ff00ffLL, - 0x0f0f0f0f0f0f0f0fLL, - 0x3333333333333333LL, - 0x5555555555555555LL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CFG_DRAM_TEST_DATA */ - -#if defined (CFG_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CFG_DRAM_TEST_ADDRESS */ - -#if defined (CFG_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CFG_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - char *s; - int rundata = 0; - int runaddress = 0; - int runwalk = 0; - -#ifdef CFG_DRAM_TEST_DATA - s = getenv ("testdramdata"); - rundata = (s && (*s == 'y')) ? 1 : 0; -#endif -#ifdef CFG_DRAM_TEST_ADDRESS - s = getenv ("testdramaddress"); - runaddress = (s && (*s == 'y')) ? 1 : 0; -#endif -#ifdef CFG_DRAM_TEST_WALK - s = getenv ("testdramwalk"); - runwalk = (s && (*s == 'y')) ? 1 : 0; -#endif - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); - } -#ifdef CFG_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CFG_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CFG_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed\n"); - } - return 0; - -} -#endif /* CFG_DRAM_TEST */ - -/* ronen - the below functions are used by the bootm function */ -/* - we map the base register to fbe00000 (same mapping as in the LSP) */ -/* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ -void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | - new_loc | - (INTERNAL_SPACE_DECODE))))) - != temp); - -} - -void board_prebootm_init () -{ - -/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ - GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); - -/* Stop GigE Rx DMA engines */ - GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); -/* GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */ -/* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */ - -/* Relocate MV64360 internal regs */ - my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS); - - icache_disable (); - invalidate_l1_instruction_cache (); - flush_data_cache (); - dcache_disable (); -} diff --git a/board/esd/cpci750/eth.h b/board/esd/cpci750/eth.h deleted file mode 100644 index aab32d2..0000000 --- a/board/esd/cpci750/eth.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __EVB64360_ETH_H__ -#define __EVB64360_ETH_H__ - -#include -#include -#include -#include - - -int db64360_eth0_poll(void); -int db64360_eth0_transmit(unsigned int s, volatile char *p); -void db64360_eth0_disable(void); -bool network_start(bd_t *bis); - - -#endif /* __EVB64360_ETH_H__ */ diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c deleted file mode 100644 index 5b1bc01..0000000 --- a/board/esd/cpci750/i2c.c +++ /dev/null @@ -1,487 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for the DB64360 board by Ingo.Assmus@keymile.com - * extra improvments by Brain Waite - * for cpci750 by reinhard.arlt@esd-electronics.com - */ -#include -#include -#include -#include "../../Marvell/include/mv_gen_reg.h" -#include "../../Marvell/include/core.h" - -#define I2C_DELAY 100 -#undef DEBUG_I2C - -#ifdef DEBUG_I2C -#define DP(x) x -#else -#define DP(x) -#endif - -/* Assuming that there is only one master on the bus (us) */ - -static void i2c_init (int speed, int slaveaddr) -{ - unsigned int n, m, freq, margin, power; - unsigned int actualN = 0, actualM = 0; - unsigned int minMargin = 0xffffffff; - unsigned int tclk = CFG_TCLK; - unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ - - DP (puts ("i2c_init\n")); -/* gtI2cMasterInit */ - for (n = 0; n < 8; n++) { - for (m = 0; m < 16; m++) { - power = 2 << n; /* power = 2^(n+1) */ - freq = tclk / (10 * (m + 1) * power); - if (i2cFreq > freq) - margin = i2cFreq - freq; - else - margin = freq - i2cFreq; - if (margin < minMargin) { - minMargin = margin; - actualN = n; - actualM = m; - } - } - } - - DP (puts ("setup i2c bus\n")); - - /* Setup bus */ - /* gtI2cReset */ - GT_REG_WRITE (I2C_SOFT_RESET, 0); - asm(" sync"); - GT_REG_WRITE (I2C_CONTROL, 0); - asm(" sync"); - - DP (puts ("set baudrate\n")); - - GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); - asm(" sync"); - - DP (puts ("udelay...\n")); - - udelay (I2C_DELAY); - - GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); - asm(" sync"); -} - - -static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit) -{ - unsigned int status, data, bits = 7; - unsigned int control; - int count = 0; - - DP (puts ("i2c_select_device\n")); - - /* Output slave address */ - - if (ten_bit) { - bits = 10; - } - - GT_REG_READ (I2C_CONTROL, &control); - control |= (0x1 << 2); - GT_REG_WRITE (I2C_CONTROL, control); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &control); - control |= (0x1 << 5); /* generate the I2C_START_BIT */ - GT_REG_WRITE (I2C_CONTROL, control); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x01 << 3)); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - - count = 0; - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){ - if (count > 200) { -#ifdef DEBUG_I2C - printf ("Failed to set startbit: 0x%02x\n", status); -#endif - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - DP (puts ("i2c_select_device:write addr byte\n")); - - /* assert the address */ - - data = (dev_addr << 1); - /* set the read bit */ - data |= read; - GT_REG_WRITE (I2C_DATA, data); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, BIT3); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count = 0; - while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { - if (count > 200) { -#ifdef DEBUG_I2C - printf ("Failed to write address: 0x%02x\n", status); -#endif - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - asm(" sync"); - count++; - } - - if (bits == 10) { - printf ("10 bit I2C addressing not yet implemented\n"); - return (0xff); - } - - return (0); -} - -static uchar i2c_get_data (uchar * return_data, int len) -{ - - unsigned int data, status; - int count = 0; - - DP (puts ("i2c_get_data\n")); - - while (len) { - - RESET_REG_BITS (I2C_CONTROL, BIT3); - asm(" sync"); - - /* Get and return the data */ - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x50) { - if (count > 20) { -#ifdef DEBUG_I2C - printf ("Failed to get data len status: 0x%02x\n", status); -#endif - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return 0; - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_READ (I2C_DATA, &data); - len--; - *return_data = (uchar) data; - return_data++; - - } - RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3); - asm(" sync"); - count = 0; - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - while ((status & 0xff) != 0x58) { - if (count > 2000) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */ - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - asm(" sync"); - - return (0); -} - - -static uchar i2c_write_data (unsigned int *data, int len) -{ - unsigned int status; - int count; - unsigned int temp; - unsigned int *temp_ptr = data; - - DP (puts ("i2c_write_data\n")); - - while (len) { - count = 0; - temp = (unsigned int) (*temp_ptr); - GT_REG_WRITE (I2C_DATA, temp); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - if (count > 200) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } - return (0); -} - - -static uchar i2c_write_byte (unsigned char *data, int len) -{ - unsigned int status; - int count; - unsigned int temp; - unsigned char *temp_ptr = data; - - DP (puts ("i2c_write_byte\n")); - - while (len) { - count = 0; - /* Set and assert the data */ - temp = *temp_ptr; - GT_REG_WRITE (I2C_DATA, temp); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - asm(" sync"); - - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - if (count > 200) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } - return (0); -} - -static uchar -i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit, - int alen) -{ - uchar status; - unsigned int table[2]; - - table[1] = (offset ) & 0x0ff; /* low byte */ - table[0] = (offset >> 8) & 0x0ff; /* high byte */ - - DP (puts ("i2c_set_dev_offset\n")); - - status = i2c_select_device (dev_addr, 0, ten_bit); - if (status) { -#ifdef DEBUG_I2C -22 printf ("Failed to select device setting offset: 0x%02x\n", - status); -#endif - return status; - } -/* check the address offset length */ - if (alen == 0) - /* no address offset */ - return (0); - else if (alen == 1) { - /* 1 byte address offset */ - status = i2c_write_data (&offset, 1); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else if (alen == 2) { - /* 2 bytes address offset */ - status = i2c_write_data (table, 2); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else { - /* address offset unknown or not supported */ - printf ("Address length offset %d is not supported\n", alen); - return 1; - } - return 0; /* sucessful completion */ -} - -uchar -i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; - - DP (puts ("i2c_read\n")); - - i2c_init (i2cFreq, 0); /* set the i2c frequency */ - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - status = i2c_select_device (dev_addr, 1, 0); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to select device for data read: 0x%02x\n", - status); -#endif - return status; - } - - status = i2c_get_data (data, len); - if (status) { -#ifdef DEBUG_I2C - printf ("Data not read: 0x%02x\n", status); -#endif - return status; - } - - return 0; -} - - -void i2c_stop (void) -{ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); - asm(" sync"); -} - - -uchar -i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; - - DP (puts ("i2c_write\n")); - - i2c_init (i2cFreq, 0); /* set the i2c frequency */ - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - - status = i2c_write_byte (data, len); /* write the data */ - if (status) { -#ifdef DEBUG_I2C - printf ("Data not written: 0x%02x\n", status); -#endif - return status; - } - /* issue a stop bit */ - i2c_stop (); - return 0; -} - - -int i2c_probe (uchar chip) -{ - -#ifdef DEBUG_I2C - unsigned int i2c_status; -#endif - uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; - - DP (puts ("i2c_probe\n")); - - i2c_init (i2cFreq, 0); /* set the i2c frequency */ - - status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address: 0x%02x\n", status); -#endif - return (int) status; - } -#ifdef DEBUG_I2C - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status); - printf ("address %#x returned %#x\n", chip, i2c_status); -#endif - /* issue a stop bit */ - i2c_stop (); - return 0; /* successful completion */ -} diff --git a/board/esd/cpci750/i2c.h b/board/esd/cpci750/i2c.h deleted file mode 100644 index b669ff0..0000000 --- a/board/esd/cpci750/i2c.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for the DB64360 board by Ingo.Assmus@keymile.com - */ - -#ifndef __I2C_H__ -#define __I2C_H__ - -/* function declarations */ -uchar i2c_read(uchar, unsigned int, int, uchar*, int); - -#endif diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c deleted file mode 100644 index bea99ce..0000000 --- a/board/esd/cpci750/ide.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* ide.c - ide support functions */ - - -#include -#ifdef CFG_CMD_IDE -#include -#include -#include - -extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; - -int ide_preinit (void) -{ - int status; - pci_dev_t devbusfn; - int l; - - status = 1; - for (l = 0; l < CFG_IDE_MAXBUS; l++) { - ide_bus_offset[l] = -ATA_STATUS; - } - devbusfn = pci_find_device (0x1103, 0x0004, 0); - if (devbusfn != -1) { - status = 0; - - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, - (u32 *) & ide_bus_offset[0]); - ide_bus_offset[0] &= 0xfffffffe; - ide_bus_offset[0] += CFG_PCI0_IO_SPACE; - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, - (u32 *) & ide_bus_offset[1]); - ide_bus_offset[1] &= 0xfffffffe; - ide_bus_offset[1] += CFG_PCI0_IO_SPACE; - } - return (status); -} - -void ide_set_reset (int flag) { - return; -} - -#endif /* of CONFIG_CMDS_IDE */ diff --git a/board/esd/cpci750/local.h b/board/esd/cpci750/local.h deleted file mode 100644 index bca0e1f..0000000 --- a/board/esd/cpci750/local.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * include/local.h - local configuration options, board specific - */ - -#ifndef __LOCAL_H -#define __LOCAL_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* This tells PPCBoot that the config options are compiled in */ -/* #undef ENV_IS_EMBEDDED */ -/* Don't touch this! PPCBOOT figures this out based on other - * magic. */ - -/* Uncomment and define any of the below options */ - -/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */ -#define CONFIG_750FX /* The 750FX doesn't support as many things in L2CR like 750CX*/ - -/* These want string arguments */ -/* #define CONFIG_BOOTARGS */ -/* #define CONFIG_BOOTCOMMAND */ -/* #define CONFIG_RAMBOOTCOMMAND */ -/* #define CONFIG_NFSBOOTCOMMAND */ -/* #define CFG_AUTOLOAD */ -/* #define CONFIG_PREBOOT */ - -/* These don't */ - -/* #define CONFIG_BOOTDELAY */ -/* #define CONFIG_BAUDRATE */ -/* #define CONFIG_LOADS_ECHO */ -/* #define CONFIG_ETHADDR */ -/* #define CONFIG_ETH2ADDR */ -/* #define CONFIG_ETH3ADDR */ -/* #define CONFIG_IPADDR */ -/* #define CONFIG_SERVERIP */ -/* #define CONFIG_ROOTPATH */ -/* #define CONFIG_GATEWAYIP */ -/* #define CONFIG_NETMASK */ -/* #define CONFIG_HOSTNAME */ -/* #define CONFIG_BOOTFILE */ -/* #define CONFIG_LOADADDR */ - -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -/* #define CONFIG_ETHADDR 86:06:2d:7e:c6:53 */ -#define CONFIG_ETHADDR 64:36:00:00:00:01 - -/* next two ethernet hwaddrs */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 86:06:2d:7e:c6:54 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 86:06:2d:7e:c6:55 - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ diff --git a/board/esd/cpci750/misc.S b/board/esd/cpci750/misc.S deleted file mode 100644 index 160b1d3..0000000 --- a/board/esd/cpci750/misc.S +++ /dev/null @@ -1,245 +0,0 @@ -#include -#include <74xx_7xx.h> -#include "version.h" - -#include -#include - -#include -#include - -#include "../../Marvell/include/mv_gen_reg.h" - -#ifdef CONFIG_ECC - /* Galileo specific asm code for initializing ECC */ - .globl board_relocate_rom -board_relocate_rom: - mflr r7 - /* update the location of the GT registers */ - lis r11, CFG_GT_REGS@h - /* if we're using ECC, we must use the DMA engine to copy ourselves */ - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - - mtlr r7 - blr - - .globl board_init_ecc -board_init_ecc: - mflr r7 - /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ - - /* now that we're running from ram, init the rest of main memory - * for ECC use */ - lis r8, CFG_MONITOR_LEN@h - ori r8, r8, CFG_MONITOR_LEN@l - - divw r3, r10, r8 - - /* set up the counter, and init the starting address */ - mtctr r3 - li r12, 0 - - /* bytes per transfer */ - mr r5, r8 -about_to_init_ecc: -1: mr r3, r12 - mr r4, r12 - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - add r12, r12, r8 - bdnz 1b - - mtlr r7 - blr - - /* r3: dest addr - * r4: source addr - * r5: byte count - * r11: gt regbase - * trashes: r6, r5 - */ -start_idma_transfer_0: - /* set the byte count, including the OWN bit */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_BYTE_COUNT - stwbrx r5, 0, (r6) - - /* set the source address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS - stwbrx r4, 0, (r6) - - /* set the dest address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS - stwbrx r3, 0, (r6) - - /* set the next record pointer */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0NEXT_RECORD_POINTER - stwbrx r5, 0, (r6) - - /* set the low control register */ - /* bit 9 is NON chained mode, bit 31 is new style descriptors. - bit 12 is channel enable */ - ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) - /* 15 shifted by 16 (oris) == bit 31 */ - oris r5, r5, (1 << 15) - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr - - /* this waits for the bytecount to return to zero, indicating - * that the trasfer is complete */ -wait_for_idma_0: - mr r5, r11 - lis r6, 0xff - ori r6, r6, 0xffff - ori r5, r5, CHANNEL0_DMA_BYTE_COUNT -1: lwbrx r4, 0, (r5) - and. r4, r4, r6 - bne 1b - - blr - - /* this turns off channel 0 of the idma engine */ -stop_idma_engine_0: - /* shut off the DMA engine */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr -#endif - -#ifdef CFG_BOARD_ASM_INIT - /* NOTE: trashes r3-r7 */ - .globl board_asm_init -board_asm_init: - /* just move the GT registers to where they belong */ - lis r3, CFG_DFL_GT_REGS@h - ori r3, r3, CFG_DFL_GT_REGS@l - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l - li r5, INTERNAL_SPACE_DECODE - - /* test to see if we've already moved */ - lwbrx r6, r5, r4 - andi. r6, r6, 0xffff - /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */ -/* rlwinm r7, r4, 8, 16, 31 - rlwinm r7, r4, 12, 16, 31 */ /* original */ - rlwinm r7, r4, 16, 16, 31 - /* -----------------------------------------------------*/ - cmp cr0, r7, r6 - beqlr - - /* nope, have to move the registers */ - lwbrx r6, r5, r3 - andis. r6, r6, 0xffff - or r6, r6, r7 - stwbrx r6, r5, r3 - - /* now, poll for the change */ -1: lwbrx r7, r5, r4 - cmp cr0, r7, r6 - bne 1b - - lis r3, CFG_INT_SRAM_BASE@h - ori r3, r3, CFG_INT_SRAM_BASE@l - rlwinm r3, r3, 16, 16, 31 - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l - li r5, INTEGRATED_SRAM_BASE_ADDR - stwbrx r3, r5, r4 - -2: lwbrx r6, r5, r4 - cmp cr0, r3, r6 - bne 2b - - /* done! */ - blr -#endif - -/* For use of the debug LEDs */ - .global led_on0_relocated -led_on0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC80 - ori r18, r18, 0x8000 -/* stw r21, 0x0(r18) */ - sync - blr - - .global led_off0_relocated -led_off0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC81 - ori r18, r18, 0x4000 -/* stw r21, 0x0(r18) */ - sync - blr - - .global led_on0 -led_on0: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0x8000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off0 -led_off0: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x4000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on1 -led_on1: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0xc000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off1 -led_off1: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x8000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on2 -led_on2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x0000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off2 -led_off2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0xc000 -/* stw r18, 0x0(r18) */ - sync - blr diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c deleted file mode 100644 index 52398b2..0000000 --- a/board/esd/cpci750/mpsc.c +++ /dev/null @@ -1,1018 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - -/* - * mpsc.c - driver for console over the MPSC. - */ - - -#include -#include -#include - -#include -#include "mpsc.h" - -#include "mv_regs.h" - -#include "../../Marvell/include/memory.h" - -/* Define this if you wish to use the MPSC as a register based UART. - * This will force the serial port to not use the SDMA engine at all. - */ - -#undef CONFIG_MPSC_DEBUG_PORT - - -int (*mpsc_putchar) (char ch) = mpsc_putchar_early; -char (*mpsc_getchar) (void) = mpsc_getchar_debug; -int (*mpsc_test_char) (void) = mpsc_test_char_debug; - - -static volatile unsigned int *rx_desc_base = NULL; -static unsigned int rx_desc_index = 0; -static volatile unsigned int *tx_desc_base = NULL; -static unsigned int tx_desc_index = 0; - -/* local function declarations */ -static int galmpsc_connect (int channel, int connect); -static int galmpsc_route_rx_clock (int channel, int brg); -static int galmpsc_route_tx_clock (int channel, int brg); -static int galmpsc_write_config_regs (int mpsc, int mode); -static int galmpsc_config_channel_regs (int mpsc); -static int galmpsc_set_char_length (int mpsc, int value); -static int galmpsc_set_stop_bit_length (int mpsc, int value); -static int galmpsc_set_parity (int mpsc, int value); -static int galmpsc_enter_hunt (int mpsc); -static int galmpsc_set_brkcnt (int mpsc, int value); -static int galmpsc_set_tcschar (int mpsc, int value); -static int galmpsc_set_snoop (int mpsc, int value); -static int galmpsc_shutdown (int mpsc); - -static int galsdma_set_RFT (int channel); -static int galsdma_set_SFM (int channel); -static int galsdma_set_rxle (int channel); -static int galsdma_set_txle (int channel); -static int galsdma_set_burstsize (int channel, unsigned int value); -static int galsdma_set_RC (int channel, unsigned int value); - -static int galbrg_set_CDV (int channel, int value); -static int galbrg_enable (int channel); -static int galbrg_disable (int channel); -static int galbrg_set_clksrc (int channel, int value); -static int galbrg_set_CUV (int channel, int value); - -static void galsdma_enable_rx (void); -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, - unsigned int size); - - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - -#ifdef CONFIG_MPSC_DEBUG_PORT -static void mpsc_debug_init (void) -{ - - volatile unsigned int temp; - - /* Clear the CFR (CHR4) */ - /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); - temp &= 0xffffff00; - temp |= BIT29; - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); - temp |= (BIT12 | BIT15); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set int mask */ - temp = GTREGREAD (GALMPSC_0_INT_MASK); - temp |= BIT6; - GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); -} -#endif - -char mpsc_getchar_debug (void) -{ - volatile int temp; - volatile unsigned int cause; - - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - while ((cause & BIT6) == 0) { - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - } - - temp = GTREGREAD (GALMPSC_CHANNELREG_10 + - (CHANNEL * GALMPSC_REG_GAP)); - /* By writing 1's to the set bits, the register is cleared */ - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), - temp); - GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); - return (temp >> 16) & 0xff; -} - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int mpsc_putchar_early (char ch) -{ - DECLARE_GLOBAL_DATA_PTR; - int mpsc = CHANNEL; - int temp = - GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - galmpsc_set_tcschar (mpsc, ch); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), - temp | 0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay (MAGIC_FACTOR / gd->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int mpsc_putchar_sdma (char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset ((void *) p, 0, 8 * sizeof (unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int) ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int) &p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int) &p[0]; - p[11] = (unsigned int) &p[12]; -#endif - - FLUSH_DCACHE (&p[0], &p[8]); - - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE (&p[1], &p[2]); - - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[1], &p[2]); - } - return 0; -} - -char mpsc_getchar_sdma (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP)); - temp |= (1 << 23); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP), temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - - -int mpsc_test_char_debug (void) -{ - if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) - return 0; - else { - return 1; - } -} - - -int mpsc_test_char_sdma (void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[1], &p[2]); - - if (p[1] & DESC_OWNER_BIT) - return 0; - else - return 1; -} - -int mpsc_init (int baud) -{ - /* BRG CONFIG */ - galbrg_set_baudrate (CHANNEL, baud); - galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ - galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ - galbrg_enable (CHANNEL); /* Enable BRG */ - - /* Set up clock routing */ - galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ - - galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ - galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ - - /* reset MPSC state */ - galmpsc_shutdown (CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle (CHANNEL); - galsdma_set_rxle (CHANNEL); - galsdma_set_RC (CHANNEL, 0xf); - galsdma_set_SFM (CHANNEL); - galsdma_set_RFT (CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs (CHANNEL); - galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - -#ifdef CONFIG_MPSC_DEBUG_PORT - mpsc_debug_init (); -#endif - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - - -void mpsc_sdma_init (void) -{ -/* Setup SDMA channel0 SDMA_CONFIG_REG*/ - GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); - -/* Enable MPSC-Window0 for DRAM Bank0 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_0_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK0)) != true) - printf ("%s: SDMA_Window0 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window1 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_1_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window1 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window2 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_2_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window2 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window3 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_3_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window3 memory setup failed !!! \n", - __FUNCTION__); - -/* Setup MPSC0 access mode Window0 full access */ - GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC1 access mode Window1 full access */ - GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); - -/* no high address remap*/ - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); - -/* clear interrupt cause register for MPSC (fault register)*/ - GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); -} - - -void mpsc_init2 (void) -{ - int i; - -#ifndef CONFIG_MPSC_DEBUG_PORT - mpsc_putchar = mpsc_putchar_sdma; - mpsc_getchar = mpsc_getchar_sdma; - mpsc_test_char = mpsc_test_char_sdma; -#endif - /* RX descriptors */ - rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset ((void *) rx_desc_base, 0, - (RX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ - rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ - rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i * 8] = 0x00100000; - } - rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; - - FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset ((void *) tx_desc_base, 0, - (TX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 3] = - (unsigned int) &tx_desc_base[i * 8 + 4]; - tx_desc_base[i * 8 + 2] = - (unsigned int) &tx_desc_base[(i + 1) * 8]; - tx_desc_base[i * 8 + 1] = - DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i * 8] = 0x00010001; - } - tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; - - FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); - - udelay (100); - - galsdma_enable_rx (); - - return; -} - -int galbrg_set_baudrate (int channel, int rate) -{ - DECLARE_GLOBAL_DATA_PTR; - int clock; - - galbrg_disable (channel); /*ok */ - -#ifdef ZUMA_NTL - /* from tclk */ - clock = (CFG_TCLK / (16 * rate)) - 1; -#else - clock = (CFG_TCLK / (16 * rate)) - 1; -#endif - - galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ - - galbrg_enable (channel); - - gd->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int galbrg_set_CDV (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_enable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x00010000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_disable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFEFFFF; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_set_clksrc (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ - temp |= (value << 18); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - return 0; -} - -static int galbrg_set_CUV (int channel, int value) -{ - /* set CountUpValue */ - GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int galbrg_reset (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int galsdma_set_RFT (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_SFM (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_rxle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_txle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_RC (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_burstsize (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int galmpsc_connect (int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int galmpsc_route_rx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_RxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_route_tx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_TxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_write_config_regs (int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int galmpsc_config_channel_regs (int mpsc) -{ - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt (mpsc, 0x3); - galmpsc_set_tcschar (mpsc, 0xab); - - return 0; -} - -static int galmpsc_set_brkcnt (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_tcschar (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_char_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_stop_bit_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFBFFF; - temp |= (value << 14); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_parity (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_enter_hunt (int mpsc) -{ - int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= 0x80000000; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & - MPSC_ENTER_HUNT) { - udelay (1); - } - return 0; -} - - -static int galmpsc_shutdown (int mpsc) -{ - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - GT_REG_WRITE (GALSDMA_0_COM_REG, 0); - GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); - - udelay (100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); - - udelay (100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); - - udelay (100); - - return 0; -} - -static void galsdma_enable_rx (void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt (CHANNEL); -} - -static int galmpsc_set_snoop (int mpsc, int value) -{ - int reg = - mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : - MPSC_0_ADDRESS_CONTROL_LOW; - int temp = GTREGREAD (reg); - - if (value) - temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); - else - temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); - GT_REG_WRITE (reg, temp); - return 0; -} - -/******************************************************************************* -* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map. -* -* DESCRIPTION: -* the MV64360 SDMA has its own address decoding map that is de-coupled -* from the CPU interface address decoding windows. The SDMA channels -* share four address windows. Each region can be individually configured -* by this function by associating it to a target interface and setting -* base and size values. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* The size must be a series of 1s followed by a series of zeros -* -* OUTPUT: -* None. -* -* RETURN: -* True for success, false otherwise. -* -*******************************************************************************/ - -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, unsigned int size) -{ - unsigned int temp; - - if (size == 0) { - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - return true; - } - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size < 0x10000) { - return false; - } - - /* Align size and base to 64K */ - baseAddress &= 0xffff0000; - size &= 0xffff0000; - temp = size >> 16; - - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - while ((temp > 0) && (temp & 0x1)) { - temp = temp >> 1; - } - - if (temp != 0) { - GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8), - (size - 1) & 0xffff0000); - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - } else { - /* An invalid size was specified */ - return false; - } - return true; -} diff --git a/board/esd/cpci750/mpsc.h b/board/esd/cpci750/mpsc.h deleted file mode 100644 index a03d1cc..0000000 --- a/board/esd/cpci750/mpsc.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus - * - ************************************************************************/ - - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include "../../Marvell/include/mv_gen_reg.h" - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_sdma_init(void); -void mpsc_init2(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -char mpsc_getchar_debug(void); -int mpsc_test_char_debug(void); - -int mpsc_test_char_sdma(void); - -extern int (*mpsc_putchar)(char ch); -extern char (*mpsc_getchar)(void); -extern int (*mpsc_test_char)(void); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER_BIT 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ -#define GALMPSC_0_INT_CAUSE 0xb804 -#define GALMPSC_0_INT_MASK 0xb884 - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c deleted file mode 100644 index be176dc..0000000 --- a/board/esd/cpci750/mv_eth.c +++ /dev/null @@ -1,3184 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mv_eth.c - header file for the polled mode GT ethernet driver - */ -#include -#include -#include - -#include "mv_eth.h" - -/* enable Debug outputs */ - -#undef DEBUG_MV_ETH - -#ifdef DEBUG_MV_ETH -#define DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#undef MV64360_CHECKSUM_OFFLOAD -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - -/* Definition for configuring driver */ -/* #define UPDATE_STATS_BY_SOFTWARE */ -#undef MV64360_RX_QUEUE_FILL_ON_TASK - - -/* Constants */ -#define MAGIC_ETH_RUNNING 8031971 -#define MV64360_INTERNAL_SRAM_SIZE _256K -#define EXTRA_BYTES 32 -#define WRAP ETH_HLEN + 2 + 4 + 16 -#define BUFFER_MTU dev->mtu + WRAP -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#ifdef MV64360_RX_FILL_ON_TASK -#define INT_CAUSE_MASK_ALL 0x00000000 -#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL -#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT -#endif - -/* Read/Write to/from MV64360 internal registers */ -#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) -#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) -#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) -#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) - -/* Static function declarations */ -static int mv64360_eth_real_open (struct eth_device *eth); -static int mv64360_eth_real_stop (struct eth_device *eth); -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device - *dev); -static void eth_port_init_mac_tables (ETH_PORT eth_port_num); -static void mv64360_eth_update_stat (struct eth_device *dev); -bool db64360_eth_start (struct eth_device *eth); -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset); -int mv64360_eth_receive (struct eth_device *dev); - -int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length); - -#ifndef UPDATE_STATS_BY_SOFTWARE -static void mv64360_eth_print_stat (struct eth_device *dev); -#endif -/* Processes a received packet */ -extern void NetReceive (volatile uchar *, int); - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/************************************************* - *Helper functions - used inside the driver only * - *************************************************/ -#ifdef DEBUG_MV_ETH -void print_globals (struct eth_device *dev) -{ - printf ("Ethernet PRINT_Globals-Debug function\n"); - printf ("Base Address for ETH_PORT_INFO: %08x\n", - (unsigned int) dev->priv); - printf ("Base Address for mv64360_eth_priv: %08x\n", - (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> - port_private)); - - printf ("GT Internal Base Address: %08x\n", - INTERNAL_REG_BASE_ADDR); - printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE); - printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE); - printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_rx_buffer_base[0], - (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32); - printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_tx_buffer_base[0], - (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32); -} -#endif - -#define my_cpu_to_le32(x) my_le32_to_cpu((x)) - -unsigned long my_le32_to_cpu (unsigned long x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); -} - - -/********************************************************************** - * mv64360_eth_print_phy_status - * - * Prints gigabit ethenret phy status - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_phy_status (struct eth_device *dev) -{ - struct mv64360_eth_priv *port_private; - unsigned int port_num; - ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; - unsigned int port_status, phy_reg_data; - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("Ethernet port changed link status to DOWN\n"); - } else { - port_status = - MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - printf ("Ethernet status port %d: Link up", port_num); - printf (", %s", - (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); - if (port_status & BIT4) - printf (", Speed 1 Gbps"); - else - printf (", %s", - (port_status & BIT5) ? "Speed 100 Mbps" : - "Speed 10 Mbps"); - printf ("\n"); - } -} - -/********************************************************************** - * u-boot entry functions for mv64360_eth - * - **********************************************************************/ -int db64360_eth_probe (struct eth_device *dev) -{ - return ((int) db64360_eth_start (dev)); -} - -int db64360_eth_poll (struct eth_device *dev) -{ - return mv64360_eth_receive (dev); -} - -int db64360_eth_transmit (struct eth_device *dev, volatile void *packet, - int length) -{ - mv64360_eth_xmit (dev, packet, length); - return 0; -} - -void db64360_eth_disable (struct eth_device *dev) -{ - mv64360_eth_stop (dev); -} - - -void mv6436x_eth_initialize (bd_t * bis) -{ - struct eth_device *dev; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - int devnum, x, temp; - char *s, *e, buf[64]; - - for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { - dev = calloc (sizeof (*dev), 1); - if (!dev) { - printf ("%s: mv_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than NAMESIZE (16) */ - sprintf (dev->name, "mv_enet%d", devnum); - -#ifdef DEBUG - printf ("Initializing %s\n", dev->name); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_r (s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - /* ronen - set the MAC addr in the HW */ - eth_port_uc_addr_set (devnum, dev->enetaddr, 0); - - dev->init = (void *) db64360_eth_probe; - dev->halt = (void *) ethernet_phy_reset; - dev->send = (void *) db64360_eth_transmit; - dev->recv = (void *) db64360_eth_poll; - - ethernet_private = - calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *) ethernet_private; - if (!ethernet_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Private Device Structure"); - free (dev); - return; - } - /* start with an zeroed ETH_PORT_INFO */ - memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - /* set pointer to memory for stats data structure etc... */ - port_private = - calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; - if (!port_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Port Private Device Structure"); - - free (ethernet_private); - free (dev); - return; - } - - port_private->stats = - calloc (sizeof (struct net_device_stats), 1); - if (!port_private->stats) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Net stat Structure"); - - free (port_private); - free (ethernet_private); - free (dev); - return; - } - memset (ethernet_private->port_private, 0, - sizeof (struct mv64360_eth_priv)); - switch (devnum) { - case 0: - ethernet_private->port_num = ETH_0; - break; - case 1: - ethernet_private->port_num = ETH_1; - break; - case 2: - ethernet_private->port_num = ETH_2; - break; - default: - printf ("Invalid device number %d\n", devnum); - break; - }; - - port_private->port_num = devnum; - /* - * Read MIB counter on the GT in order to reset them, - * then zero all the stats fields in memory - */ - mv64360_eth_update_stat (dev); - memset (port_private->stats, 0, - sizeof (struct net_device_stats)); - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_r (s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - DP (printf ("Allocating descriptor and buffer rings\n")); - - ethernet_private->p_rx_desc_area_base[0] = - (ETH_RX_DESC *) memalign (16, - RX_DESC_ALIGNED_SIZE * - MV64360_RX_QUEUE_SIZE + 1); - ethernet_private->p_tx_desc_area_base[0] = - (ETH_TX_DESC *) memalign (16, - TX_DESC_ALIGNED_SIZE * - MV64360_TX_QUEUE_SIZE + 1); - - ethernet_private->p_rx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - ethernet_private->p_tx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - -#ifdef DEBUG_MV_ETH - /* DEBUG OUTPUT prints adresses of globals */ - print_globals (dev); -#endif - eth_register (dev); - - } - DP (printf ("%s: exit\n", __FUNCTION__)); - -} - -/********************************************************************** - * mv64360_eth_open - * - * This function is called when openning the network device. The function - * should initialize all the hardware, initialize cyclic Rx/Tx - * descriptors chain and buffers and allocate an IRQ to the network - * device. - * - * Input : a pointer to the network device structure - * / / ronen - changed the output to match net/eth.c needs - * Output : nonzero of success , zero if fails. - * under construction - **********************************************************************/ - -int mv64360_eth_open (struct eth_device *dev) -{ - return (mv64360_eth_real_open (dev)); -} - -/* Helper function for mv64360_eth_open */ -static int mv64360_eth_real_open (struct eth_device *dev) -{ - - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - u32 port_status, phy_reg_data; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - /* ronen - when we update the MAC env params we only update dev->enetaddr - see ./net/eth.c eth_set_enetaddr() */ - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Clear the ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - - /* Unmask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL); - - /* Unmask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL_EXT); - - /* Set phy address of the port */ - ethernet_private->port_phy_addr = 0x8 + port_num; - - /* Activate the DMA channels etc */ - eth_port_init (ethernet_private); - - - /* "Allocate" setup TX rings */ - - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - unsigned int size; - - port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE; - size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ - ethernet_private->tx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_tx_desc_area_base[queue], - 0, ethernet_private->tx_desc_area_size[queue]); - - /* initialize tx desc ring with low level driver */ - if (ether_init_tx_desc_ring - (ethernet_private, ETH_Q0, - port_private->tx_ring_size[queue], - MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_tx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_tx_buffer_base[queue]) == false) - printf ("### Error initializing TX Ring\n"); - } - - /* "Allocate" setup RX rings */ - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - unsigned int size; - - /* Meantime RX Ring are fixed - but must be configurable by user */ - port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE; - size = (port_private->rx_ring_size[queue] * - RX_DESC_ALIGNED_SIZE); - ethernet_private->rx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_rx_desc_area_base[queue], - 0, ethernet_private->rx_desc_area_size[queue]); - if ((ether_init_rx_desc_ring - (ethernet_private, ETH_Q0, - port_private->rx_ring_size[queue], - MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_rx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_rx_buffer_base[queue])) == false) - printf ("### Error initializing RX Ring\n"); - } - - eth_port_start (ethernet_private); - - /* Set maximum receive buffer to 9700 bytes */ - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num), - (0x5 << 17) | - (MV_REG_READ - (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num)) - & 0xfff1ffff)); - - /* - * Set ethernet MTU for leaky bucket mechanism to 0 - this will - * disable the leaky bucket mechanism . - */ - - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - /* Reset PHY */ - if ((ethernet_phy_reset (port_num)) != true) { - printf ("$$ Warnning: No link on port %d \n", - port_num); - return 0; - } else { - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("### Error: Phy is not active\n"); - return 0; - } - } - } else { - mv64360_eth_print_phy_status (dev); - } - port_private->eth_running = MAGIC_ETH_RUNNING; - return 1; -} - - -static int mv64360_eth_free_tx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_TX_DESC *p_tx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop Tx Queues */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free TX rings */ - DP (printf ("Clearing previously allocated TX queues... ")); - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - /* Free on TX rings */ - for (p_tx_curr_desc = - ethernet_private->p_tx_desc_area_base[queue]; - ((unsigned int) p_tx_curr_desc <= (unsigned int) - ethernet_private->p_tx_desc_area_base[queue] + - ethernet_private->tx_desc_area_size[queue]); - p_tx_curr_desc = - (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + - TX_DESC_ALIGNED_SIZE)) { - /* this is inside for loop */ - if (p_tx_curr_desc->return_info != 0) { - p_tx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -static int mv64360_eth_free_rx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_RX_DESC *p_rx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free RX rings */ - DP (printf ("Clearing previously allocated RX queues... ")); - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - /* Free preallocated skb's on RX rings */ - for (p_rx_curr_desc = - ethernet_private->p_rx_desc_area_base[queue]; - (((unsigned int) p_rx_curr_desc < - ((unsigned int) ethernet_private-> - p_rx_desc_area_base[queue] + - ethernet_private->rx_desc_area_size[queue]))); - p_rx_curr_desc = - (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + - RX_DESC_ALIGNED_SIZE)) { - if (p_rx_curr_desc->return_info != 0) { - p_rx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -/********************************************************************** - * mv64360_eth_stop - * - * This function is used when closing the network device. - * It updates the hardware, - * release all memory that holds buffers and descriptors and release the IRQ. - * Input : a pointer to the device structure - * Output : zero if success , nonzero if fails - *********************************************************************/ - -int mv64360_eth_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Disable all gigE address decoder */ - MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); - DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); - mv64360_eth_real_stop (dev); - - return 0; -}; - -/* Helper function for mv64360_eth_stop */ - -static int mv64360_eth_real_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - mv64360_eth_free_tx_rings (dev); - mv64360_eth_free_rx_rings (dev); - - eth_port_reset (ethernet_private->port_num); - /* Disable ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - /* Mask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0); - /* Mask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); - MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH, - BIT0 << port_num); - /* Print Network statistics */ -#ifndef UPDATE_STATS_BY_SOFTWARE - /* - * Print statistics (only if ethernet is running), - * then zero all the stats fields in memory - */ - if (port_private->eth_running == MAGIC_ETH_RUNNING) { - port_private->eth_running = 0; - mv64360_eth_print_stat (dev); - } - memset (port_private->stats, 0, sizeof (struct net_device_stats)); -#endif - DP (printf ("\nEthernet stopped ... \n")); - return 0; -} - - -/********************************************************************** - * mv64360_eth_start_xmit - * - * This function is queues a packet in the Tx descriptor for - * required port. - * - * Input : skb - a pointer to socket buffer - * dev - a pointer to the required port - * - * Output : zero upon success - **********************************************************************/ - -int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, - int dataSize) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - PKT_INFO pkt_info; - ETH_FUNC_RET_STATUS status; - struct net_device_stats *stats; - ETH_FUNC_RET_STATUS release_result; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - stats = port_private->stats; - - /* Update packet info data structure */ - pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ - pkt_info.byte_cnt = dataSize; - pkt_info.buf_ptr = (unsigned int) dataPtr; - - status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); - if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { - printf ("Error on transmitting packet .."); - if (status == ETH_QUEUE_FULL) - printf ("ETH Queue is full. \n"); - if (status == ETH_QUEUE_LAST_RESOURCE) - printf ("ETH Queue: using last available resource. \n"); - goto error; - } - - /* Update statistics and start of transmittion time */ - stats->tx_bytes += dataSize; - stats->tx_packets++; - - /* Check if packet(s) is(are) transmitted correctly (release everything) */ - do { - release_result = - eth_tx_return_desc (ethernet_private, ETH_Q0, - &pkt_info); - switch (release_result) { - case ETH_OK: - DP (printf ("descriptor released\n")); - if (pkt_info.cmd_sts & BIT0) { - printf ("Error in TX\n"); - stats->tx_errors++; - - } - break; - case ETH_RETRY: - DP (printf ("transmission still in process\n")); - break; - - case ETH_ERROR: - printf ("routine can not access Tx desc ring\n"); - break; - - case ETH_END_OF_JOB: - DP (printf ("the routine has nothing to release\n")); - break; - default: /* should not happen */ - break; - } - } while (release_result == ETH_OK); - - - return 0; /* success */ - error: - return 1; /* Failed - higher layers will free the skb */ -} - -/********************************************************************** - * mv64360_eth_receive - * - * This function is forward packets that are received from the port's - * queues toward kernel core or FastRoute them to another interface. - * - * Input : dev - a pointer to the required interface - * max - maximum number to receive (0 means unlimted) - * - * Output : number of served packets - **********************************************************************/ - -int mv64360_eth_receive (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - PKT_INFO pkt_info; - struct net_device_stats *stats; - - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - stats = port_private->stats; - - while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == - ETH_OK)) { - -#ifdef DEBUG_MV_ETH - if (pkt_info.byte_cnt != 0) { - printf ("%s: Received %d byte Packet @ 0x%x\n", - __FUNCTION__, pkt_info.byte_cnt, - pkt_info.buf_ptr); - } -#endif - /* Update statistics. Note byte count includes 4 byte CRC count */ - stats->rx_packets++; - stats->rx_bytes += pkt_info.byte_cnt; - - /* - * In case received a packet without first / last bits on OR the error - * summary bit is on, the packets needs to be dropeed. - */ - if (((pkt_info. - cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != - (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) - || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { - stats->rx_dropped++; - - printf ("Received packet spread on multiple descriptors\n"); - - /* Is this caused by an error ? */ - if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { - stats->rx_errors++; - } - - /* free these descriptors again without forwarding them to the higher layers */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - /* /free these descriptors again */ - } else { - -/* !!! call higher layer processing */ -#ifdef DEBUG_MV_ETH - printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); -#endif - /* let the upper layer handle the packet */ - NetReceive ((uchar *) pkt_info.buf_ptr, - (int) pkt_info.byte_cnt); - -/* **************************************************************** */ -/* free descriptor */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - DP (printf - ("RX: pkt_info.buf_ptr = %x\n", - pkt_info.buf_ptr)); - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - -/* **************************************************************** */ - - } - } - mv64360_eth_get_stats (dev); /* update statistics */ - return 1; -} - -/********************************************************************** - * mv64360_eth_get_stats - * - * Returns a pointer to the interface statistics. - * - * Input : dev - a pointer to the required interface - * - * Output : a pointer to the interface's statistics - **********************************************************************/ - -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - mv64360_eth_update_stat (dev); - - return port_private->stats; -} - - -/********************************************************************** - * mv64360_eth_update_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_update_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - unsigned int port_num; - volatile unsigned int dummy; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - stats = port_private->stats; - - /* These are false updates */ - stats->rx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_RECEIVED); - stats->tx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_SENT); - stats->rx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); - /* - * Ideally this should be as follows - - * - * stats->rx_bytes += stats->rx_bytes + - * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , - * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); - * - * But the unsigned long in PowerPC and MIPS are 32bit. So the next read - * is just a dummy read for proper work of the GigE port - */ - dummy = eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); - stats->tx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_LOW); - dummy = eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_HIGH); - stats->rx_errors += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MAC_RECEIVE_ERROR); - - /* Rx dropped is for received packet with CRC error */ - stats->rx_dropped += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_BAD_CRC_EVENT); - stats->multicast += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MULTICAST_FRAMES_RECEIVED); - stats->collisions += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_COLLISION) + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_LATE_COLLISION); - /* detailed rx errors */ - stats->rx_length_errors += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_UNDERSIZE_RECEIVED) - + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_OVERSIZE_RECEIVED); - /* detailed tx errors */ -} - -#ifndef UPDATE_STATS_BY_SOFTWARE -/********************************************************************** - * mv64360_eth_print_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - stats = port_private->stats; - - /* These are false updates */ - printf ("\n### Network statistics: ###\n"); - printf ("--------------------------\n"); - printf (" Packets received: %ld\n", stats->rx_packets); - printf (" Packets send: %ld\n", stats->tx_packets); - printf (" Received bytes: %ld\n", stats->rx_bytes); - printf (" Send bytes: %ld\n", stats->tx_bytes); - if (stats->rx_errors != 0) - printf (" Rx Errors: %ld\n", - stats->rx_errors); - if (stats->rx_dropped != 0) - printf (" Rx dropped (CRC Errors): %ld\n", - stats->rx_dropped); - if (stats->multicast != 0) - printf (" Rx mulicast frames: %ld\n", - stats->multicast); - if (stats->collisions != 0) - printf (" No. of collisions: %ld\n", - stats->collisions); - if (stats->rx_length_errors != 0) - printf (" Rx length errors: %ld\n", - stats->rx_length_errors); -} -#endif - -/************************************************************************** - *network_start - Network Kick Off Routine UBoot - *Inputs : - *Outputs : - **************************************************************************/ - -bool db64360_eth_start (struct eth_device *dev) -{ - return (mv64360_eth_open (dev)); /* calls real open */ -} - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* - * based on Linux code - * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - */ - -/******************************************************************************** - * Marvell's Gigabit Ethernet controller low level driver - * - * DESCRIPTION: - * This file introduce low level API to Marvell's Gigabit Ethernet - * controller. This Gigabit Ethernet Controller driver API controls - * 1) Operations (i.e. port init, start, reset etc'). - * 2) Data flow (i.e. port send, receive etc'). - * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO - * struct. - * This struct includes user configuration information as well as - * driver internal data needed for its operations. - * - * Supported Features: - * - This low level driver is OS independent. Allocating memory for - * the descriptor rings and buffers are not within the scope of - * this driver. - * - The user is free from Rx/Tx queue managing. - * - This low level driver introduce functionality API that enable - * the to operate Marvell's Gigabit Ethernet Controller in a - * convenient way. - * - Simple Gigabit Ethernet port operation API. - * - Simple Gigabit Ethernet port data flow API. - * - Data flow and operation API support per queue functionality. - * - Support cached descriptors for better performance. - * - Enable access to all four DRAM banks and internal SRAM memory - * spaces. - * - PHY access and control API. - * - Port control register configuration API. - * - Full control over Unicast and Multicast MAC configurations. - * - * Operation flow: - * - * Initialization phase - * This phase complete the initialization of the ETH_PORT_INFO - * struct. - * User information regarding port configuration has to be set - * prior to calling the port initialization routine. For example, - * the user has to assign the port_phy_addr field which is board - * depended parameter. - * In this phase any port Tx/Rx activity is halted, MIB counters - * are cleared, PHY address is set according to user parameter and - * access to DRAM and internal SRAM memory spaces. - * - * Driver ring initialization - * Allocating memory for the descriptor rings and buffers is not - * within the scope of this driver. Thus, the user is required to - * allocate memory for the descriptors ring and buffers. Those - * memory parameters are used by the Rx and Tx ring initialization - * routines in order to curve the descriptor linked list in a form - * of a ring. - * Note: Pay special attention to alignment issues when using - * cached descriptors/buffers. In this phase the driver store - * information in the ETH_PORT_INFO struct regarding each queue - * ring. - * - * Driver start - * This phase prepares the Ethernet port for Rx and Tx activity. - * It uses the information stored in the ETH_PORT_INFO struct to - * initialize the various port registers. - * - * Data flow: - * All packet references to/from the driver are done using PKT_INFO - * struct. - * This struct is a unified struct used with Rx and Tx operations. - * This way the user is not required to be familiar with neither - * Tx nor Rx descriptors structures. - * The driver's descriptors rings are management by indexes. - * Those indexes controls the ring resources and used to indicate - * a SW resource error: - * 'current' - * This index points to the current available resource for use. For - * example in Rx process this index will point to the descriptor - * that will be passed to the user upon calling the receive routine. - * In Tx process, this index will point to the descriptor - * that will be assigned with the user packet info and transmitted. - * 'used' - * This index points to the descriptor that need to restore its - * resources. For example in Rx process, using the Rx buffer return - * API will attach the buffer returned in packet info to the - * descriptor pointed by 'used'. In Tx process, using the Tx - * descriptor return will merely return the user packet info with - * the command status of the transmitted buffer pointed by the - * 'used' index. Nevertheless, it is essential to use this routine - * to update the 'used' index. - * 'first' - * This index supports Tx Scatter-Gather. It points to the first - * descriptor of a packet assembled of multiple buffers. For example - * when in middle of Such packet we have a Tx resource error the - * 'curr' index get the value of 'first' to indicate that the ring - * returned to its state before trying to transmit this packet. - * - * Receive operation: - * The eth_port_receive API set the packet information struct, - * passed by the caller, with received information from the - * 'current' SDMA descriptor. - * It is the user responsibility to return this resource back - * to the Rx descriptor ring to enable the reuse of this source. - * Return Rx resource is done using the eth_rx_return_buff API. - * - * Transmit operation: - * The eth_port_send API supports Scatter-Gather which enables to - * send a packet spanned over multiple buffers. This means that - * for each packet info structure given by the user and put into - * the Tx descriptors ring, will be transmitted only if the 'LAST' - * bit will be set in the packet info command status field. This - * API also consider restriction regarding buffer alignments and - * sizes. - * The user must return a Tx resource after ensuring the buffer - * has been transmitted to enable the Tx ring indexes to update. - * - * BOARD LAYOUT - * This device is on-board. No jumper diagram is necessary. - * - * EXTERNAL INTERFACE - * - * Prior to calling the initialization routine eth_port_init() the user - * must set the following fields under ETH_PORT_INFO struct: - * port_num User Ethernet port number. - * port_phy_addr User PHY address of Ethernet port. - * port_mac_addr[6] User defined port MAC address. - * port_config User port configuration value. - * port_config_extend User port config extend value. - * port_sdma_config User port SDMA config value. - * port_serial_control User port serial control value. - * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. - * *port_private User scratch pad for user specific data structures. - * - * This driver introduce a set of default values: - * PORT_CONFIG_VALUE Default port configuration value - * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value - * PORT_SDMA_CONFIG_VALUE Default sdma control value - * PORT_SERIAL_CONTROL_VALUE Default port serial control value - * - * This driver data flow is done using the PKT_INFO struct which is - * a unified struct for Rx and Tx operations: - * byte_cnt Tx/Rx descriptor buffer byte count. - * l4i_chk CPU provided TCP Checksum. For Tx operation only. - * cmd_sts Tx/Rx descriptor command status. - * buf_ptr Tx/Rx descriptor buffer pointer. - * return_info Tx/Rx user resource return information. - * - * - * EXTERNAL SUPPORT REQUIREMENTS - * - * This driver requires the following external support: - * - * D_CACHE_FLUSH_LINE (address, address offset) - * - * This macro applies assembly code to flush and invalidate cache - * line. - * address - address base. - * address offset - address offset - * - * - * CPU_PIPE_FLUSH - * - * This macro applies assembly code to flush the CPU pipeline. - * - *******************************************************************************/ -/* includes */ - -/* defines */ -/* SDMA command macros */ -#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) - -#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ - (1 << (8 + tx_queue))) - -#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) - -#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) - -#define CURR_RFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) - -#define CURR_RFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_RFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) - -#define USED_RFD_SET(p_used_desc, queue)\ -(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) - - -#define CURR_TFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) - -#define CURR_TFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_TFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) - -#define USED_TFD_SET(p_used_desc, queue) \ - (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) - -#define FIRST_TFD_GET(p_first_desc, queue) \ - ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) - -#define FIRST_TFD_SET(p_first_desc, queue) \ - (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) - - -/* Macros that save access to desc in order to find next desc pointer */ -#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) - -#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) - -#define LINK_UP_TIMEOUT 100000 -#define PHY_BUSY_TIMEOUT 10000000 - -/* locals */ - -/* PHY routines */ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); -static int ethernet_phy_get (ETH_PORT eth_port_num); - -/* Ethernet Port routines */ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param); -static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, - ETH_QUEUE queue, int option); -#if 0 /* FIXME */ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option); -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option); -#endif - -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count); - -void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); - - -typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; -u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_BASE_ADDR); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_BASE_ADDR); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_BASE_ADDR); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_dram_bank_size (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_SIZE); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_SIZE); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_SIZE); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_SIZE); - result += 1; - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_internal_sram_base (void) -{ - u32 result; - - result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -/******************************************************************************* -* eth_port_init - Initialize the Ethernet port driver -* -* DESCRIPTION: -* This function prepares the ethernet port to start its activity: -* 1) Completes the ethernet port driver struct initialization toward port -* start routine. -* 2) Resets the device to a quiescent state in case of warm reboot. -* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -* 4) Clean MAC tables. The reset status of those tables is unknown. -* 5) Set PHY address. -* Note: Call this routine prior to eth_port_start routine and after setting -* user values in the user fields of Ethernet port control struct (i.e. -* port_phy_addr). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* See description. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - ETH_WIN_PARAM win_param; - - p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; - p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; - p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; - p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; - - p_eth_port_ctrl->port_rx_queue_command = 0; - p_eth_port_ctrl->port_tx_queue_command = 0; - - /* Zero out SW structs */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->rx_resource_err[queue] = false; - } - - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->tx_resource_err[queue] = false; - } - - eth_port_reset (p_eth_port_ctrl->port_num); - - /* Set access parameters for DRAM bank 0 */ - win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); - win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 1 */ - win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); - win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 2 */ - win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); - win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 3 */ - win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); - win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for Internal SRAM */ - win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ - win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ - win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; - win_param.high_addr = 0; - win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ - win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */ - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - eth_port_init_mac_tables (p_eth_port_ctrl->port_num); - - ethernet_phy_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_phy_addr); - - return; - -} - -/******************************************************************************* -* eth_port_start - Start the Ethernet port activity. -* -* DESCRIPTION: -* This routine prepares the Ethernet port for Rx and Tx activity: -* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -* has been initialized a descriptor's ring (using ether_init_tx_desc_ring -* for Tx and ether_init_rx_desc_ring for Rx) -* 2. Initialize and enable the Ethernet configuration port by writing to -* the port's configuration and command registers. -* 3. Initialize and enable the SDMA by writing to the SDMA's -* configuration and command registers. -* After completing these steps, the ethernet port SDMA can starts to -* perform Rx and Tx activities. -* -* Note: Each Rx and Tx queue descriptor's list must be initialized prior -* to calling this function (use ether_init_tx_desc_ring for Tx queues and -* ether_init_rx_desc_ring for Rx queues). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* Ethernet port is ready to receive and transmit. -* -* RETURN: -* false if the port PHY is not up. -* true otherwise. -* -*******************************************************************************/ -static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - volatile ETH_TX_DESC *p_tx_curr_desc; - volatile ETH_RX_DESC *p_rx_curr_desc; - unsigned int phy_reg_data; - ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; - - - /* Assignment of Tx CTRP of given queue */ - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_GET (p_tx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_tx_curr_desc)); - - } - - /* Assignment of Rx CRDP of given queue */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_GET (p_rx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_rx_curr_desc)); - - if (p_rx_curr_desc != NULL) - /* Add the assigned Ethernet address to the port's address table */ - eth_port_uc_addr_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_mac_addr, - queue); - } - - /* Assign port configuration and command. */ - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_config); - - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - p_eth_port_ctrl->port_config_extend); - - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - p_eth_port_ctrl->port_serial_control); - - MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - ETH_SERIAL_PORT_ENABLE); - - /* Assign port SDMA configuration */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_sdma_config); - - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT - (eth_port_num), 0x3fffffff); - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG - (eth_port_num), 0x03fffcff); - /* Turn off the port/queue bandwidth limitation */ - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); - - /* Enable port Rx. */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), - p_eth_port_ctrl->port_rx_queue_command); - - /* Check if link is up */ - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (!(phy_reg_data & 0x20)) - return false; - - return true; -} - -/******************************************************************************* -* eth_port_uc_addr_set - This function Set the port Unicast address. -* -* DESCRIPTION: -* This function Set the port Ethernet MAC address. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. -* -* OUTPUT: -* Set MAC address low and high registers. also calls eth_port_uc_addr() -* To set the unicast table with the proper information. -* -* RETURN: -* N/A. -* -*******************************************************************************/ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, ETH_QUEUE queue) -{ - unsigned int mac_h; - unsigned int mac_l; - - mac_l = (p_addr[4] << 8) | (p_addr[5]); - mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | - (p_addr[2] << 8) | (p_addr[3] << 0); - - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); - - /* Accept frames of this address */ - eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); - - return; -} - -/******************************************************************************* -* eth_port_uc_addr - This function Set the port unicast address table -* -* DESCRIPTION: -* This function locates the proper entry in the Unicast table for the -* specified MAC nibble and sets its properties according to function -* parameters. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* This function add/removes MAC addresses from the port unicast address -* table. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_uc_addr (ETH_PORT eth_port_num, - unsigned char uc_nibble, - ETH_QUEUE queue, int option) -{ - unsigned int unicast_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the Unicast table entry */ - uc_nibble = (0xf & uc_nibble); - tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ - reg_offset = uc_nibble % 4; /* Entry offset within the above register */ - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified unicast DA table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - - break; - - default: - return false; - } - return true; -} - -#if 0 /* FIXME */ -/******************************************************************************* -* eth_port_mc_addr - Multicast address settings. -* -* DESCRIPTION: -* This API controls the MV device MAC multicast support. -* The MV device supports multicast using two tables: -* 1) Special Multicast Table for MAC addresses of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* In this case, the function calls eth_port_smc_addr() routine to set the -* Special Multicast Table. -* 2) Other Multicast Table for multicast of another type. A CRC-8bit -* is used as an index to the Other Multicast Table entries in the -* DA-Filter table. -* In this case, the function calculates the CRC-8bit value and calls -* eth_port_omc_addr() routine to set the Other Multicast Table. -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if add_address_table_entry( ) failed. -* -*******************************************************************************/ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, int option) -{ - unsigned int mac_h; - unsigned int mac_l; - unsigned char crc_result = 0; - int mac_array[48]; - int crc[8]; - int i; - - - if ((p_addr[0] == 0x01) && - (p_addr[1] == 0x00) && - (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) - - eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); - else { - /* Calculate CRC-8 out of the given address */ - mac_h = (p_addr[0] << 8) | (p_addr[1]); - mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | - (p_addr[4] << 8) | (p_addr[5] << 0); - - for (i = 0; i < 32; i++) - mac_array[i] = (mac_l >> i) & 0x1; - for (i = 32; i < 48; i++) - mac_array[i] = (mac_h >> (i - 32)) & 0x1; - - - crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ - mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ - mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ - mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ - mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ - mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[0]; - - crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ - mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ - mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ - mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ - mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ - mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ - mac_array[0]; - - crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ - mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ - mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ - mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ - mac_array[2] ^ mac_array[1] ^ mac_array[0]; - - crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ - mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ - mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ - mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ - mac_array[2] ^ mac_array[1]; - - crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ - mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ - mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ - mac_array[2]; - - crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ - mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ - mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ - mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ - mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ - mac_array[3]; - - crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ - mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ - mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ - mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[6] ^ mac_array[5] ^ mac_array[4]; - - crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ - mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ - mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ - mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ - mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[5]; - - for (i = 0; i < 8; i++) - crc_result = crc_result | (crc[i] << i); - - eth_port_omc_addr (eth_port_num, crc_result, queue, option); - } - return; -} - -/******************************************************************************* -* eth_port_smc_addr - Special Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device special MAC multicast support. -* The Special Multicast Table for MAC addresses supports MAC of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* This function set the Special Multicast Table appropriate entry -* according to the argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option) -{ - unsigned int smc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the SMC table entry */ - tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ - reg_offset = mc_byte % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - default: - return false; - } - return true; -} - -/******************************************************************************* -* eth_port_omc_addr - Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device Other MAC multicast support. -* The Other Multicast Table is used for multicast of another type. -* A CRC-8bit is used as an index to the Other Multicast Table entries -* in the DA-Filter table. -* The function gets the CRC-8bit value from the calling routine and -* set the Other Multicast Table appropriate entry according to the -* CRC-8 argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option) -{ - unsigned int omc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the OMC table entry */ - tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ - reg_offset = crc8 % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - default: - return false; - } - return true; -} -#endif - -/******************************************************************************* -* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -* -* DESCRIPTION: -* Go through all the DA filter tables (Unicast, Special Multicast & Other -* Multicast) and set each entry to 0. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Multicast and Unicast packets are rejected. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init_mac_tables (ETH_PORT eth_port_num) -{ - int table_index; - - /* Clear DA filter unicast table (Ex_dFUT) */ - for (table_index = 0; table_index <= 0xC; table_index += 4) - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) + table_index), 0); - - for (table_index = 0; table_index <= 0xFC; table_index += 4) { - /* Clear DA filter special multicast table (Ex_dFSMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - /* Clear DA filter other multicast table (Ex_dFOMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - } -} - -/******************************************************************************* -* eth_clear_mib_counters - Clear all MIB counters -* -* DESCRIPTION: -* This function clears all MIB counters of a specific ethernet port. -* A read from the MIB counter will reset the counter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* After reading all MIB counters, the counters resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -static void eth_clear_mib_counters (ETH_PORT eth_port_num) -{ - int i; - unsigned int dummy; - - /* Perform dummy reads from MIB counters */ - for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) - dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); - - return; -} - -/******************************************************************************* -* eth_read_mib_counter - Read a MIB counter -* -* DESCRIPTION: -* This function reads a MIB counter of a specific ethernet port. -* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the -* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH -* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and -* ETH_MIB_GOOD_OCTETS_SENT_HIGH -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). -* -* OUTPUT: -* After reading the MIB counter, the counter resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset) -{ - return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num) - + mib_offset)); -} - -/******************************************************************************* -* ethernet_phy_set - Set the ethernet port PHY address. -* -* DESCRIPTION: -* This routine set the ethernet port PHY address according to given -* parameter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Set PHY Address Register with given PHY address parameter. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - reg_data &= ~(0x1F << (5 * eth_port_num)); - reg_data |= (phy_addr << (5 * eth_port_num)); - - MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data); - - return; -} - -/******************************************************************************* - * ethernet_phy_get - Get the ethernet port PHY address. - * - * DESCRIPTION: - * This routine returns the given ethernet port PHY address. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * PHY address. - * - *******************************************************************************/ -static int ethernet_phy_get (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - return ((reg_data >> (5 * eth_port_num)) & 0x1f); -} - -/******************************************************************************* - * ethernet_phy_reset - Reset Ethernet port PHY. - * - * DESCRIPTION: - * This routine utilize the SMI interface to reset the ethernet port PHY. - * The routine waits until the link is up again or link up is timeout. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * The ethernet port PHY renew its link. - * - * RETURN: - * None. - * -*******************************************************************************/ -static bool ethernet_phy_reset (ETH_PORT eth_port_num) -{ - unsigned int time_out = 50; - unsigned int phy_reg_data; - - /* Reset the PHY */ - eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); - phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ - eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); - - /* Poll on the PHY LINK */ - do { - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (time_out-- == 0) - return false; - } - while (!(phy_reg_data & 0x20)); - - return true; -} - -/******************************************************************************* - * eth_port_reset - Reset Ethernet port - * - * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and - * clearing the MIB counters. The Receiver and the Transmit unit are in - * idle state after this command is performed and the port is disabled. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * Channel activity is halted. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_port_reset (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - /* Stop Tx port activity. Check port Tx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Tx activity to terminate. */ - do { - /* Check port cause register that all Tx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Stop Rx port activity. Check port Rx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Rx activity to terminate. */ - do { - /* Check port cause register that all Rx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - - /* Clear all MIB counters */ - eth_clear_mib_counters (eth_port_num); - - /* Reset the Enable bit in the Configuration Register */ - reg_data = - MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG - (eth_port_num)); - reg_data &= ~ETH_SERIAL_PORT_ENABLE; - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - reg_data); - - return; -} - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_set_config_reg - Set specified bits in configuration register. - * - * DESCRIPTION: - * This function sets specified bits in the given ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are set in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_set_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = - MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num)); - eth_config_reg |= value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* FIXME */ -/******************************************************************************* - * ethernet_reset_config_reg - Reset specified bits in configuration register. - * - * DESCRIPTION: - * This function resets specified bits in the given Ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are reset in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_reset_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - eth_config_reg &= ~value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_get_config_reg - Get the port configuration register - * - * DESCRIPTION: - * This function returns the configuration register value of the given - * ethernet port. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * Port configuration register value. - * - *******************************************************************************/ -static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - return eth_config_reg; -} - -#endif - -/******************************************************************************* - * eth_port_read_smi_reg - Read PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform PHY register read. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int *value Register value buffer. - * - * OUTPUT: - * Write the value of a specified PHY register into given buffer. - * - * RETURN: - * false if the PHY is busy or read data is not in valid state. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); -/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ -#define PHY_UPDATE_TIMEOUT 10000 - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return true; -} - -/******************************************************************************* - * eth_port_write_smi_reg - Write to PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform writes to PHY registers. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int value Register value. - * - * OUTPUT: - * Write the given value to the specified PHY register. - * - * RETURN: - * false if the PHY is busy. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return true; -} - -/******************************************************************************* - * eth_set_access_control - Config address decode parameters for Ethernet unit - * - * DESCRIPTION: - * This function configures the address decode parameters for the Gigabit - * Ethernet Controller according the given parameters struct. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * ETH_WIN_PARAM *param Address decode parameter struct. - * - * OUTPUT: - * An access window is opened using the given access parameters. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param) -{ - unsigned int access_prot_reg; - - /* Set access control register */ - access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG - (eth_port_num)); - access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ - access_prot_reg |= (param->access_ctrl << (param->win * 2)); - MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num), - access_prot_reg); - - /* Set window Size reg (SR) */ - MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 + - (ETH_SIZE_REG_GAP * param->win)), - (((param->size / 0x10000) - 1) << 16)); - - /* Set window Base address reg (BA) */ - MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), - (param->target | param->attributes | param->base_addr)); - /* High address remap reg (HARR) */ - if (param->win < 4) - MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 + - (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), - param->high_addr); - - /* Base address enable reg (BARER) */ - if (param->enable == 1) - MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); - else - MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); -} - -/******************************************************************************* - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Rx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer - * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. - * unsigned int rx_buff_base_addr Rx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Rx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr) -{ - ETH_RX_DESC *p_rx_desc; - ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ - unsigned int buffer_addr; - int ix; /* a counter */ - - - p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; - p_rx_prev_desc = p_rx_desc; - buffer_addr = rx_buff_base_addr; - - /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (rx_buff_base_addr & 0xF) - return false; - - /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) - return false; - - /* Rx buffers must be 64-bit aligned. */ - if ((rx_buff_base_addr + rx_buff_size) & 0x7) - return false; - - /* initialize the Rx descriptors ring */ - for (ix = 0; ix < rx_desc_num; ix++) { - p_rx_desc->buf_size = rx_buff_size; - p_rx_desc->byte_cnt = 0x0000; - p_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - p_rx_desc->next_desc_ptr = - ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; - p_rx_desc->buf_ptr = buffer_addr; - p_rx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_rx_desc, 0); - buffer_addr += rx_buff_size; - p_rx_prev_desc = p_rx_desc; - p_rx_desc = (ETH_RX_DESC *) - ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); - } - - /* Closing Rx descriptors ring */ - p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); - D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); - - /* Save Rx desc pointer to driver struct. */ - CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - - p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = - (ETH_RX_DESC *) rx_desc_base_addr; - p_eth_port_ctrl->rx_desc_area_size[rx_queue] = - rx_desc_num * RX_DESC_ALIGNED_SIZE; - - p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); - - return true; -} - -/******************************************************************************* - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Tx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer - * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. - * unsigned int tx_buff_base_addr Tx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Tx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr) -{ - - ETH_TX_DESC *p_tx_desc; - ETH_TX_DESC *p_tx_prev_desc; - unsigned int buffer_addr; - int ix; /* a counter */ - - - /* save the first desc pointer to link with the last descriptor */ - p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; - p_tx_prev_desc = p_tx_desc; - buffer_addr = tx_buff_base_addr; - - /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (tx_buff_base_addr & 0xF) - return false; - - /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((tx_buff_size > TX_BUFFER_MAX_SIZE) - || (tx_buff_size < TX_BUFFER_MIN_SIZE)) - return false; - - /* Initialize the Tx descriptors ring */ - for (ix = 0; ix < tx_desc_num; ix++) { - p_tx_desc->byte_cnt = 0x0000; - p_tx_desc->l4i_chk = 0x0000; - p_tx_desc->cmd_sts = 0x00000000; - p_tx_desc->next_desc_ptr = - ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; - - p_tx_desc->buf_ptr = buffer_addr; - p_tx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_tx_desc, 0); - buffer_addr += tx_buff_size; - p_tx_prev_desc = p_tx_desc; - p_tx_desc = (ETH_TX_DESC *) - ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); - - } - /* Closing Tx descriptors ring */ - p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; - D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); - /* Set Tx desc pointer in driver struct. */ - CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - - /* Init Tx ring base and size parameters */ - p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = - (ETH_TX_DESC *) tx_desc_base_addr; - p_eth_port_ctrl->tx_desc_area_size[tx_queue] = - (tx_desc_num * TX_DESC_ALIGNED_SIZE); - - /* Add the queue to the list of Tx queues of this port */ - p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); - - return true; -} - -/******************************************************************************* - * eth_port_send - Send an Ethernet packet - * - * DESCRIPTION: - * This routine send a given packet described by p_pktinfo parameter. It - * supports transmitting of a packet spaned over multiple buffers. The - * routine updates 'curr' and 'first' indexes according to the packet - * segment passed to the routine. In case the packet segment is first, - * the 'first' index is update. In any case, the 'curr' index is updated. - * If the routine get into Tx resource error it assigns 'curr' index as - * 'first'. This way the function can abort Tx process of multiple - * descriptors per packet. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'curr' and 'first' indexes are updated. - * - * RETURN: - * ETH_QUEUE_FULL in case of Tx resource error. - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_first; - volatile ETH_TX_DESC *p_tx_desc_curr; - volatile ETH_TX_DESC *p_tx_next_desc_curr; - volatile ETH_TX_DESC *p_tx_desc_used; - unsigned int command_status; - - /* Do not process Tx ring in case of Tx ring resource error */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - return ETH_QUEUE_FULL; - - /* Get the Tx Desc ring indexes */ - CURR_TFD_GET (p_tx_desc_curr, tx_queue); - USED_TFD_GET (p_tx_desc_used, tx_queue); - - if (p_tx_desc_curr == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); - command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; - - if (command_status & (ETH_TX_FIRST_DESC)) { - /* Update first desc */ - FIRST_TFD_SET (p_tx_desc_curr, tx_queue); - p_tx_desc_first = p_tx_desc_curr; - } else { - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - command_status |= ETH_BUFFER_OWNED_BY_DMA; - } - - /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ - /* boundary. We use the memory allocated for Tx descriptor. This memory */ - /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ - if (p_pkt_info->byte_cnt <= 8) { - printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ - return ETH_ERROR; - - p_tx_desc_curr->buf_ptr = - (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; - eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, - p_pkt_info->byte_cnt); - } else - p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; - - p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; - p_tx_desc_curr->return_info = p_pkt_info->return_info; - - if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { - /* Set last desc with DMA ownership and interrupt enable. */ - p_tx_desc_curr->cmd_sts = command_status | - ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; - - if (p_tx_desc_curr != p_tx_desc_first) - p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; - - /* Flush CPU pipe */ - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); - CPU_PIPE_FLUSH; - - /* Apply send command */ - ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); - - /* Finish Tx packet. Update first desc in case of Tx resource error */ - p_tx_desc_first = p_tx_next_desc_curr; - FIRST_TFD_SET (p_tx_desc_first, tx_queue); - - } else { - p_tx_desc_curr->cmd_sts = command_status; - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - } - - /* Check for ring index overlap in the Tx desc ring */ - if (p_tx_next_desc_curr == p_tx_desc_used) { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_desc_first, tx_queue); - - p_eth_port_ctrl->tx_resource_err[tx_queue] = true; - return ETH_QUEUE_LAST_RESOURCE; - } else { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); - return ETH_OK; - } -} - -/******************************************************************************* - * eth_tx_return_desc - Free all used Tx descriptors - * - * DESCRIPTION: - * This routine returns the transmitted packet information to the caller. - * It uses the 'first' index to support Tx desc return in case a transmit - * of a packet spanned over multiple buffer still in process. - * In case the Tx queue was in "resource error" condition, where there are - * no available Tx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'first' and 'used' indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_RETRY in case there is transmission in process. - * ETH_END_OF_JOB if the routine has nothing to release. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_used = NULL; - volatile ETH_TX_DESC *p_tx_desc_first = NULL; - unsigned int command_status; - - - /* Get the Tx Desc ring indexes */ - USED_TFD_GET (p_tx_desc_used, tx_queue); - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - - - /* Sanity check */ - if (p_tx_desc_used == NULL) - return ETH_ERROR; - - command_status = p_tx_desc_used->cmd_sts; - - /* Still transmitting... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_RETRY; - } - - /* Stop release. About to overlap the current available Tx descriptor */ - if ((p_tx_desc_used == p_tx_desc_first) && - (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_END_OF_JOB; - } - - /* Pass the packet information to the caller */ - p_pkt_info->cmd_sts = command_status; - p_pkt_info->return_info = p_tx_desc_used->return_info; - p_tx_desc_used->return_info = 0; - - /* Update the next descriptor to release. */ - USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); - - /* Any Tx return cancels the Tx resource error status */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - p_eth_port_ctrl->tx_resource_err[tx_queue] = false; - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - - return ETH_OK; - -} - -/******************************************************************************* - * eth_port_receive - Get received information from Rx ring. - * - * DESCRIPTION: - * This routine returns the received data to the caller. There is no - * data copying during routine operation. All information is returned - * using pointer to packet information struct passed from the caller. - * If the routine exhausts Rx ring resources then the resource error flag - * is set. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Rx ring current and used indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_QUEUE_FULL if Rx ring resources are exhausted. - * ETH_END_OF_JOB if there is no received data. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_rx_curr_desc; - volatile ETH_RX_DESC *p_rx_next_curr_desc; - volatile ETH_RX_DESC *p_rx_used_desc; - unsigned int command_status; - - /* Do not process Rx ring in case of Rx ring resource error */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { - printf ("\nRx Queue is full ...\n"); - return ETH_QUEUE_FULL; - } - - /* Get the Rx Desc ring 'curr and 'used' indexes */ - CURR_RFD_GET (p_rx_curr_desc, rx_queue); - USED_RFD_GET (p_rx_used_desc, rx_queue); - - /* Sanity check */ - if (p_rx_curr_desc == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); - command_status = p_rx_curr_desc->cmd_sts; - - /* Nothing to receive... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); -/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ - return ETH_END_OF_JOB; - } - - p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; - p_pkt_info->cmd_sts = command_status; - p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; - p_pkt_info->return_info = p_rx_curr_desc->return_info; - p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ - - /* Clean the return info field to indicate that the packet has been */ - /* moved to the upper layers */ - p_rx_curr_desc->return_info = 0; - - /* Update 'curr' in data structure */ - CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); - - /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ - if (p_rx_next_curr_desc == p_rx_used_desc) - p_eth_port_ctrl->rx_resource_err[rx_queue] = true; - - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); - CPU_PIPE_FLUSH; - return ETH_OK; -} - -/******************************************************************************* - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. - * - * DESCRIPTION: - * This routine returns a Rx buffer back to the Rx ring. It retrieves the - * next 'used' descriptor and attached the returned buffer to it. - * In case the Rx ring was in "resource error" condition, where there are - * no available Rx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info Information on the returned buffer. - * - * OUTPUT: - * New available Rx resource in Rx descriptor ring. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ - - /* Get 'used' Rx descriptor */ - USED_RFD_GET (p_used_rx_desc, rx_queue); - - /* Sanity check */ - if (p_used_rx_desc == NULL) - return ETH_ERROR; - - p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; - p_used_rx_desc->return_info = p_pkt_info->return_info; - p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; - p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */ - - /* Flush the write pipe */ - CPU_PIPE_FLUSH; - - /* Return the descriptor to DMA ownership */ - p_used_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - - /* Flush descriptor and CPU pipe */ - D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); - CPU_PIPE_FLUSH; - - /* Move the used descriptor pointer to the next descriptor */ - USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); - - /* Any Rx return cancels the Rx resource error status */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) - p_eth_port_ctrl->rx_resource_err[rx_queue] = false; - - return ETH_OK; -} - -/******************************************************************************* - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path - * - * DESCRIPTION: - * This routine sets the RX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the tClk of the MV-643xx chip - * , and the required delay of the interrupt in usec. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in usec - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set RX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - ((coal & 0x3fff) << 8) | - (MV_REG_READ - (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num)) - & 0xffc000ff)); - return coal; -} - -#endif -/******************************************************************************* - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path - * - * DESCRIPTION: - * This routine sets the TX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the t_cLK frequency of the - * MV-643xx chip and the required delay in the interrupt in uSec - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in uSeconds - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set TX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), - coal << 4); - return coal; -} -#endif - -/******************************************************************************* - * eth_b_copy - Copy bytes from source to destination - * - * DESCRIPTION: - * This function supports the eight bytes limitation on Tx buffer size. - * The routine will zero eight bytes starting from the destination address - * followed by copying bytes from the source address to the destination. - * - * INPUT: - * unsigned int src_addr 32 bit source address. - * unsigned int dst_addr 32 bit destination address. - * int byte_count Number of bytes to copy. - * - * OUTPUT: - * See description. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count) -{ - /* Zero the dst_addr area */ - *(unsigned int *) dst_addr = 0x0; - - while (byte_count != 0) { - *(char *) dst_addr = *(char *) src_addr; - dst_addr++; - src_addr++; - byte_count--; - } -} diff --git a/board/esd/cpci750/mv_eth.h b/board/esd/cpci750/mv_eth.h deleted file mode 100644 index c57e679..0000000 --- a/board/esd/cpci750/mv_eth.h +++ /dev/null @@ -1,844 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mv_eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __DB64360_ETH_H__ -#define __DB64360_ETH_H__ - -#include -#include -#include -#include -#include -#include "mv_regs.h" -#include "../../Marvell/common/ppc_error_no.h" - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ -#ifndef MAX_SKB_FRAGS -#define MAX_SKB_FRAGS 0 -#endif - -/* Port attributes */ -/*#define MAX_RX_QUEUE_NUM 8*/ -/*#define MAX_TX_QUEUE_NUM 8*/ -#define MAX_RX_QUEUE_NUM 1 -#define MAX_TX_QUEUE_NUM 1 - - -/* Use one TX queue and one RX queue */ -#define MV64360_TX_QUEUE_NUM 1 -#define MV64360_RX_QUEUE_NUM 1 - -/* - * Number of RX / TX descriptors on RX / TX rings. - * Note that allocating RX descriptors is done by allocating the RX - * ring AND a preallocated RX buffers (skb's) for each descriptor. - * The TX descriptors only allocates the TX descriptors ring, - * with no pre allocated TX buffers (skb's are allocated by higher layers. - */ - -/* Default TX ring size is 10 descriptors */ -#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE -#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE -#else -#define MV64360_TX_QUEUE_SIZE 4 -#endif - -/* Default RX ring size is 4 descriptors */ -#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE -#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE -#else -#define MV64360_RX_QUEUE_SIZE 4 -#endif - -#ifdef CONFIG_RX_BUFFER_SIZE -#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE -#else -#define MV64360_RX_BUFFER_SIZE 1600 -#endif - -#ifdef CONFIG_TX_BUFFER_SIZE -#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE -#else -#define MV64360_TX_BUFFER_SIZE 1600 -#endif - - -/* - * Network device statistics. Akin to the 2.0 ether stats but - * with byte counters. - */ - -struct net_device_stats -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; -}; - - -/* Private data structure used for ethernet device */ -struct mv64360_eth_priv { - unsigned int port_num; - struct net_device_stats *stats; - -/* to buffer area aligned */ - char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ - char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ - - /* Size of Tx Ring per queue */ - unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; - - - /* Size of Rx Ring per queue */ - unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; - - /* Magic Number for Ethernet running */ - unsigned int eth_running; - -}; - - -int mv64360_eth_init (struct eth_device *dev); -int mv64360_eth_stop (struct eth_device *dev); -int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length); -/* return db64360_eth0_poll(); */ - -int mv64360_eth_open (struct eth_device *dev); - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - - -/******************************************************************************** - * Header File for : MV-643xx network interface header - * - * DESCRIPTION: - * This header file contains macros typedefs and function declaration for - * the Marvell Gig Bit Ethernet Controller. - * - * DEPENDENCIES: - * None. - * - *******************************************************************************/ - - -#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY -#ifdef CONFIG_MV64360_SRAM_CACHEABLE -/* In case SRAM is cacheable but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case SRAM is cache coherent or non-cacheable */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif -#else -#ifdef CONFIG_NOT_COHERENT_CACHE -/* In case of descriptors on DDR but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case of descriptors on DDR and cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif /* CONFIG_NOT_COHERENT_CACHE */ -#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ - - -#define CPU_PIPE_FLUSH \ -{ \ - __asm__ __volatile__ ("eieio"); \ -} - - -/* defines */ - -/* Default port configuration value */ -#define PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -/* Default port extend configuration value */ -#define PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - - -/* Default sdma control value */ -#ifdef CONFIG_NOT_COHERENT_CACHE -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_16_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_16_64BIT; -#else -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT; -#endif - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ETTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_1552BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; - -#define RX_BUFFER_MAX_SIZE 0xFFFF -#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ - -#define RX_BUFFER_MIN_SIZE 0x8 -#define TX_BUFFER_MIN_SIZE 0x8 - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ - -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 - -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define RX_DESC_ALIGNED_SIZE 0x20 -#define TX_DESC_ALIGNED_SIZE 0x20 - -/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -#define TX_BUF_OFFSET_IN_DESC 0x18 -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Gap define */ -#define ETH_BAR_GAP 0x8 -#define ETH_SIZE_REG_GAP 0x8 -#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define ETH_PORT_ACCESS_CTRL_GAP 0x4 - -/* Gigabit Ethernet Unit Global Registers */ - -/* MIB Counters register definitions */ -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 -#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc -#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 -#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c -#define ETH_MIB_FRAMES_64_OCTETS 0x20 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c -#define ETH_MIB_GOOD_FRAMES_SENT 0x40 -#define ETH_MIB_EXCESSIVE_COLLISION 0x44 -#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 -#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 -#define ETH_MIB_FC_SENT 0x54 -#define ETH_MIB_GOOD_FC_RECEIVED 0x58 -#define ETH_MIB_BAD_FC_RECEIVED 0x5c -#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 -#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 -#define ETH_MIB_OVERSIZE_RECEIVED 0x68 -#define ETH_MIB_JABBER_RECEIVED 0x6c -#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 -#define ETH_MIB_BAD_CRC_EVENT 0x74 -#define ETH_MIB_COLLISION 0x78 -#define ETH_MIB_LATE_COLLISION 0x7c - -/* Port serial status reg (PSR) */ -#define ETH_INTERFACE_GMII_MII 0 -#define ETH_INTERFACE_PCM BIT0 -#define ETH_LINK_IS_DOWN 0 -#define ETH_LINK_IS_UP BIT1 -#define ETH_PORT_AT_HALF_DUPLEX 0 -#define ETH_PORT_AT_FULL_DUPLEX BIT2 -#define ETH_RX_FLOW_CTRL_DISABLED 0 -#define ETH_RX_FLOW_CTRL_ENBALED BIT3 -#define ETH_GMII_SPEED_100_10 0 -#define ETH_GMII_SPEED_1000 BIT4 -#define ETH_MII_SPEED_10 0 -#define ETH_MII_SPEED_100 BIT5 -#define ETH_NO_TX 0 -#define ETH_TX_IN_PROGRESS BIT7 -#define ETH_BYPASS_NO_ACTIVE 0 -#define ETH_BYPASS_ACTIVE BIT8 -#define ETH_PORT_NOT_AT_PARTITION_STATE 0 -#define ETH_PORT_AT_PARTITION_STATE BIT9 -#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 -#define ETH_PORT_TX_FIFO_EMPTY BIT10 - - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define ETH_UNICAST_NORMAL_MODE 0 -#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 -#define ETH_DEFAULT_RX_QUEUE_0 0 -#define ETH_DEFAULT_RX_QUEUE_1 BIT1 -#define ETH_DEFAULT_RX_QUEUE_2 BIT2 -#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_4 BIT3 -#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) -#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) -#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 -#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 -#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 -#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 -#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) -#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) -#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 -#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 -#define ETH_RECEIVE_BC_IF_IP 0 -#define ETH_REJECT_BC_IF_IP BIT8 -#define ETH_RECEIVE_BC_IF_ARP 0 -#define ETH_REJECT_BC_IF_ARP BIT9 -#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 -#define ETH_CAPTURE_TCP_FRAMES_DIS 0 -#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 -#define ETH_CAPTURE_UDP_FRAMES_DIS 0 -#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 -#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 -#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 -#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 -#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 -#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) -#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) -#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 -#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 -#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 -#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 -#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) -#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) -#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 -#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 -#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 -#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 -#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) -#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) - - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define ETH_CLASSIFY_EN BIT0 -#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 -#define ETH_PARTITION_DISABLE 0 -#define ETH_PARTITION_ENABLE BIT2 - - -/* Tx/Rx queue command reg (RQCR/TQCR)*/ -#define ETH_QUEUE_0_ENABLE BIT0 -#define ETH_QUEUE_1_ENABLE BIT1 -#define ETH_QUEUE_2_ENABLE BIT2 -#define ETH_QUEUE_3_ENABLE BIT3 -#define ETH_QUEUE_4_ENABLE BIT4 -#define ETH_QUEUE_5_ENABLE BIT5 -#define ETH_QUEUE_6_ENABLE BIT6 -#define ETH_QUEUE_7_ENABLE BIT7 -#define ETH_QUEUE_0_DISABLE BIT8 -#define ETH_QUEUE_1_DISABLE BIT9 -#define ETH_QUEUE_2_DISABLE BIT10 -#define ETH_QUEUE_3_DISABLE BIT11 -#define ETH_QUEUE_4_DISABLE BIT12 -#define ETH_QUEUE_5_DISABLE BIT13 -#define ETH_QUEUE_6_DISABLE BIT14 -#define ETH_QUEUE_7_DISABLE BIT15 - - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define ETH_RIFB BIT0 -#define ETH_RX_BURST_SIZE_1_64BIT 0 -#define ETH_RX_BURST_SIZE_2_64BIT BIT1 -#define ETH_RX_BURST_SIZE_4_64BIT BIT2 -#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) -#define ETH_RX_BURST_SIZE_16_64BIT BIT3 -#define ETH_BLM_RX_NO_SWAP BIT4 -#define ETH_BLM_RX_BYTE_SWAP 0 -#define ETH_BLM_TX_NO_SWAP BIT5 -#define ETH_BLM_TX_BYTE_SWAP 0 -#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 -#define ETH_DESCRIPTORS_NO_SWAP 0 -#define ETH_TX_BURST_SIZE_1_64BIT 0 -#define ETH_TX_BURST_SIZE_2_64BIT BIT22 -#define ETH_TX_BURST_SIZE_4_64BIT BIT23 -#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) -#define ETH_TX_BURST_SIZE_16_64BIT BIT24 - - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define ETH_SERIAL_PORT_DISABLE 0 -#define ETH_SERIAL_PORT_ENABLE BIT0 -#define ETH_FORCE_LINK_PASS BIT1 -#define ETH_DO_NOT_FORCE_LINK_PASS 0 -#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 -#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 -#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 -#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 -#define ETH_ADV_NO_FLOW_CTRL 0 -#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 -#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 -#define ETH_FORCE_BP_MODE_NO_JAM 0 -#define ETH_FORCE_BP_MODE_JAM_TX BIT7 -#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 -#define ETH_FORCE_LINK_FAIL 0 -#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 -#define ETH_RETRANSMIT_16_ETTEMPTS 0 -#define ETH_RETRANSMIT_FOREVER BIT11 -#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 -#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 -#define ETH_DTE_ADV_0 0 -#define ETH_DTE_ADV_1 BIT14 -#define ETH_DISABLE_AUTO_NEG_BYPASS 0 -#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 -#define ETH_AUTO_NEG_NO_CHANGE 0 -#define ETH_RESTART_AUTO_NEG BIT16 -#define ETH_MAX_RX_PACKET_1518BYTE 0 -#define ETH_MAX_RX_PACKET_1522BYTE BIT17 -#define ETH_MAX_RX_PACKET_1552BYTE BIT18 -#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) -#define ETH_MAX_RX_PACKET_9192BYTE BIT19 -#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) -#define ETH_SET_EXT_LOOPBACK BIT20 -#define ETH_CLR_EXT_LOOPBACK 0 -#define ETH_SET_FULL_DUPLEX_MODE BIT21 -#define ETH_SET_HALF_DUPLEX_MODE 0 -#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 -#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define ETH_SET_GMII_SPEED_TO_10_100 0 -#define ETH_SET_GMII_SPEED_TO_1000 BIT23 -#define ETH_SET_MII_SPEED_TO_10 0 -#define ETH_SET_MII_SPEED_TO_100 BIT24 - - -/* SMI reg */ -#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ -#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ -#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ -#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ - -/* SDMA command status fields macros */ - -/* Tx & Rx descriptors status */ -#define ETH_ERROR_SUMMARY (BIT0) - -/* Tx & Rx descriptors command */ -#define ETH_BUFFER_OWNED_BY_DMA (BIT31) - -/* Tx descriptors status */ -#define ETH_LC_ERROR (0 ) -#define ETH_UR_ERROR (BIT1 ) -#define ETH_RL_ERROR (BIT2 ) -#define ETH_LLC_SNAP_FORMAT (BIT9 ) - -/* Rx descriptors status */ -#define ETH_CRC_ERROR (0 ) -#define ETH_OVERRUN_ERROR (BIT1 ) -#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) -#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) -#define ETH_VLAN_TAGGED (BIT19) -#define ETH_BPDU_FRAME (BIT20) -#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) -#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) -#define ETH_OTHER_FRAME_TYPE (BIT22) -#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) -#define ETH_FRAME_TYPE_IP_V_4 (BIT24) -#define ETH_FRAME_HEADER_OK (BIT25) -#define ETH_RX_LAST_DESC (BIT26) -#define ETH_RX_FIRST_DESC (BIT27) -#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) -#define ETH_RX_ENABLE_INTERRUPT (BIT29) -#define ETH_LAYER_4_CHECKSUM_OK (BIT30) - -/* Rx descriptors byte count */ -#define ETH_FRAME_FRAGMENTED (BIT2) - -/* Tx descriptors command */ -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) -#define ETH_FRAME_SET_TO_VLAN (BIT15) -#define ETH_TCP_FRAME (0 ) -#define ETH_UDP_FRAME (BIT16) -#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) -#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) -#define ETH_ZERO_PADDING (BIT19) -#define ETH_TX_LAST_DESC (BIT20) -#define ETH_TX_FIRST_DESC (BIT21) -#define ETH_GEN_CRC (BIT22) -#define ETH_TX_ENABLE_INTERRUPT (BIT23) -#define ETH_AUTO_MODE (BIT30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attributes */ -#define EBAR_ATTR_DRAM_CS0 0x00000E00 -#define EBAR_ATTR_DRAM_CS1 0x00000D00 -#define EBAR_ATTR_DRAM_CS2 0x00000B00 -#define EBAR_ATTR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 -#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 -#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 -#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 -#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 - -/* CPU 60x bus or internal SRAM interface */ -#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define EBAR_ATTR_CBS_SRAM 0x00000000 -#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY BIT0 -#define EWIN_ACCESS_FULL (BIT1 | BIT0) -#define EWIN0_ACCESS_MASK 0x0003 -#define EWIN1_ACCESS_MASK 0x000C -#define EWIN2_ACCESS_MASK 0x0030 -#define EWIN3_ACCESS_MASK 0x00C0 - -/* typedefs */ - -typedef enum _eth_port -{ - ETH_0 = 0, - ETH_1 = 1, - ETH_2 = 2 -}ETH_PORT; - -typedef enum _eth_func_ret_status -{ - ETH_OK, /* Returned as expected. */ - ETH_ERROR, /* Fundamental error. */ - ETH_RETRY, /* Could not process request. Try later. */ - ETH_END_OF_JOB, /* Ring has nothing to process. */ - ETH_QUEUE_FULL, /* Ring resource error. */ - ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ -}ETH_FUNC_RET_STATUS; - -typedef enum _eth_queue -{ - ETH_Q0 = 0, - ETH_Q1 = 1, - ETH_Q2 = 2, - ETH_Q3 = 3, - ETH_Q4 = 4, - ETH_Q5 = 5, - ETH_Q6 = 6, - ETH_Q7 = 7 -} ETH_QUEUE; - -typedef enum _addr_win -{ - ETH_WIN0, - ETH_WIN1, - ETH_WIN2, - ETH_WIN3, - ETH_WIN4, - ETH_WIN5 -} ETH_ADDR_WIN; - -typedef enum _eth_target -{ - ETH_TARGET_DRAM , - ETH_TARGET_DEVICE, - ETH_TARGET_CBS , - ETH_TARGET_PCI0 , - ETH_TARGET_PCI1 -}ETH_TARGET; - -typedef struct _eth_rx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short buf_size ; /* Buffer size */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_RX_DESC; - - -typedef struct _eth_tx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_TX_DESC; - -/* Unified struct for Rx and Tx operations. The user is not required to */ -/* be familier with neither Tx nor Rx descriptors. */ -typedef struct _pkt_info -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} PKT_INFO; - - -typedef struct _eth_win_param -{ - ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ - ETH_TARGET target; /* System targets. See ETH_TARGET enum */ - unsigned short attributes; /* BAR attributes. See above macros. */ - unsigned int base_addr; /* Window base address in unsigned int form */ - unsigned int high_addr; /* Window high address in unsigned int form */ - unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ - bool enable; /* Enable/disable access to the window. */ - unsigned short access_ctrl; /* Access ctrl register. see above macros */ -} ETH_WIN_PARAM; - - -/* Ethernet port specific infomation */ - -typedef struct _eth_port_ctrl -{ - ETH_PORT port_num; /* User Ethernet port number */ - int port_phy_addr; /* User phy address of Ethrnet port */ - unsigned char port_mac_addr[6]; /* User defined port MAC address. */ - unsigned int port_config; /* User port configuration value */ - unsigned int port_config_extend; /* User port config extend value */ - unsigned int port_sdma_config; /* User port SDMA config value */ - unsigned int port_serial_control; /* User port serial control value */ - unsigned int port_tx_queue_command; /* Port active Tx queues summary */ - unsigned int port_rx_queue_command; /* Port active Rx queues summary */ - - /* User function to cast virtual address to CPU bus address */ - unsigned int (*port_virt_to_phys)(unsigned int addr); - /* User scratch pad for user specific data structures */ - void *port_private; - - bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ - bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ - - /* Tx/Rx rings managment indexes fields. For driver use */ - - /* Next available Rx resource */ - volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; - /* Returning Rx resource */ - volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; - - /* Next available Tx resource */ - volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; - /* Returning Tx resource */ - volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; - /* An extra Tx index to support transmit of multiple buffers per packet */ - volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; - - /* Tx/Rx rings size and base variables fields. For driver use */ - - volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; - unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; - char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; - - volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; - unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; - char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; - -} ETH_PORT_INFO; - - -/* ethernet.h API list */ - -/* Port operation control routines */ -static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); -static void eth_port_reset(ETH_PORT eth_port_num); -static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); - - -/* Port MAC address routines */ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue); -#if 0 /* FIXME */ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, - int option); -#endif - -/* PHY and MIB routines */ -static bool ethernet_phy_reset(ETH_PORT eth_port_num); - -static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int value); - -static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int* value); - -static void eth_clear_mib_counters(ETH_PORT eth_port_num); - -/* Port data flow control routines */ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); - - -static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr); - -static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr); - -#endif /* MV64360_ETH_ */ diff --git a/board/esd/cpci750/mv_regs.h b/board/esd/cpci750/mv_regs.h deleted file mode 100644 index 0d6370b..0000000 --- a/board/esd/cpci750/mv_regs.h +++ /dev/null @@ -1,1124 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/******************************************************************************** -* gt64360r.h - GT-64360 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_regsh -#define __INCmv_regsh - -#define MV64360 - -/* Supported by the Atlantis */ -#define MV64360_INCLUDE_PCI_1 -#define MV64360_INCLUDE_PCI_0_ARBITER -#define MV64360_INCLUDE_PCI_1_ARBITER -#define MV64360_INCLUDE_SNOOP_SUPPORT -#define MV64360_INCLUDE_P2P -#define MV64360_INCLUDE_ETH_PORT_2 -#define MV64360_INCLUDE_CPU_MAPPING -#define MV64360_INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64360_CS_0_BASE_ADDR 0x008 -#define MV64360_CS_0_SIZE 0x010 -#define MV64360_CS_1_BASE_ADDR 0x208 -#define MV64360_CS_1_SIZE 0x210 -#define MV64360_CS_2_BASE_ADDR 0x018 -#define MV64360_CS_2_SIZE 0x020 -#define MV64360_CS_3_BASE_ADDR 0x218 -#define MV64360_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64360_PCI_0_IO_BASE_ADDR 0x048 -#define MV64360_PCI_0_IO_SIZE 0x050 -#define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64360_PCI_0_MEMORY0_SIZE 0x060 -#define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64360_PCI_0_MEMORY1_SIZE 0x088 -#define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64360_PCI_0_MEMORY2_SIZE 0x260 -#define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64360_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64360_PCI_1_IO_BASE_ADDR 0x090 -#define MV64360_PCI_1_IO_SIZE 0x098 -#define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64360_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64360_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64360_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64360_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64360_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64360_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64360_CPU_CONFIG 0x000 -#define MV64360_CPU_MODE 0x120 -#define MV64360_CPU_MASTER_CONTROL 0x160 -#define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64360_SMP_WHO_AM_I 0x200 -#define MV64360_SMP_CPU0_DOORBELL 0x214 -#define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64360_SMP_CPU1_DOORBELL 0x224 -#define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64360_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64360_SMP_SEMAPHOR0 0x244 -#define MV64360_SMP_SEMAPHOR1 0x24c -#define MV64360_SMP_SEMAPHOR2 0x254 -#define MV64360_SMP_SEMAPHOR3 0x25c -#define MV64360_SMP_SEMAPHOR4 0x264 -#define MV64360_SMP_SEMAPHOR5 0x26c -#define MV64360_SMP_SEMAPHOR6 0x274 -#define MV64360_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64360_CPU_ERROR_ADDR_LOW 0x070 -#define MV64360_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64360_CPU_ERROR_DATA_LOW 0x128 -#define MV64360_CPU_ERROR_DATA_HIGH 0x130 -#define MV64360_CPU_ERROR_PARITY 0x138 -#define MV64360_CPU_ERROR_CAUSE 0x140 -#define MV64360_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64360_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64360_SRAM_CONFIG 0x380 -#define MV64360_SRAM_TEST_MODE 0X3F4 -#define MV64360_SRAM_ERROR_CAUSE 0x388 -#define MV64360_SRAM_ERROR_ADDR 0x390 -#define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64360_SRAM_ERROR_DATA_LOW 0x398 -#define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64360_SDRAM_CONFIG 0x1400 -#define MV64360_D_UNIT_CONTROL_LOW 0x1404 -#define MV64360_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64360_SDRAM_ADDR_CONTROL 0x1410 -#define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64360_SDRAM_OPERATION 0x1418 -#define MV64360_SDRAM_MODE 0x141c -#define MV64360_EXTENDED_DRAM_MODE 0x1420 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64360_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64360_SDRAM_ERROR_ADDR 0x1450 -#define MV64360_SDRAM_RECEIVED_ECC 0x1448 -#define MV64360_SDRAM_CALCULATED_ECC 0x144c -#define MV64360_SDRAM_ECC_CONTROL 0x1454 -#define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64360_DFCDL_CONFIG0 0x1480 -#define MV64360_DFCDL_CONFIG1 0x1484 -#define MV64360_DLL_WRITE 0x1488 -#define MV64360_DLL_READ 0x148c -#define MV64360_SRAM_ADDR 0x1490 -#define MV64360_SRAM_DATA0 0x1494 -#define MV64360_SRAM_DATA1 0x1498 -#define MV64360_SRAM_DATA2 0x149c -#define MV64360_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64360_DUNIT_DEBUG_LOW 0x1460 -#define MV64360_DUNIT_DEBUG_HIGH 0x1464 -#define MV64360_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64360_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64360_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64360_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64360_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64360_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64360_DEVICE_ERROR_ADDR 0x4d8 -#define MV64360_DEVICE_ERROR_DATA 0x4dc -#define MV64360_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64360_DEVICE_DEBUG_LOW 0x4e4 -#define MV64360_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64360_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64360_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64360_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64360_PCI_0_COMMAND 0xc00 -#define MV64360_PCI_1_COMMAND 0xc80 -#define MV64360_PCI_0_MODE 0xd00 -#define MV64360_PCI_1_MODE 0xd80 -#define MV64360_PCI_0_RETRY 0xc04 -#define MV64360_PCI_1_RETRY 0xc84 -#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64360_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64360_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64360_PCI_0_P2P_CONFIG 0x1d14 -#define MV64360_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64360_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64360_PCI_1_CONFIG_ADDR 0xc78 -#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64360_PCI_0_SERR_MASK 0xc28 -#define MV64360_PCI_1_SERR_MASK 0xca8 -#define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64360_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64360_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64360_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64360_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64360_PCI_0_ERROR_MASK 0x1d5c -#define MV64360_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64360_PCI_0_MMASK 0X1D24 -#define MV64360_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64360_PCI_STATUS_AND_COMMAND 0x004 -#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64360_PCI_VPD_ADDR 0x048 -#define MV64360_PCI_VPD_DATA 0x04c -#define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64360_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64360_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64360_PCI_X_COMMAND 0x060 -#define MV64360_PCI_X_STATUS 0x064 -#define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64360_ETH_PHY_ADDR_REG 0x2000 -#define MV64360_ETH_SMI_REG 0x2004 -#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64360_ETH_BAR_0 0x2200 -#define MV64360_ETH_BAR_1 0x2208 -#define MV64360_ETH_BAR_2 0x2210 -#define MV64360_ETH_BAR_3 0x2218 -#define MV64360_ETH_BAR_4 0x2220 -#define MV64360_ETH_BAR_5 0x2228 -#define MV64360_ETH_SIZE_REG_0 0x2204 -#define MV64360_ETH_SIZE_REG_1 0x220c -#define MV64360_ETH_SIZE_REG_2 0x2214 -#define MV64360_ETH_SIZE_REG_3 0x221c -#define MV64360_ETH_SIZE_REG_4 0x2224 -#define MV64360_ETH_SIZE_REG_5 0x222c -#define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64360_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64360_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64360_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64360_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64360_CUNIT_SIZE0 0xf204 -#define MV64360_CUNIT_SIZE1 0xf20c -#define MV64360_CUNIT_SIZE2 0xf214 -#define MV64360_CUNIT_SIZE3 0xf21c -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64360_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64360_CUNIT_CONFIG_REG 0xb40c -#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64360_CUNIT_DEBUG_LOW 0xf340 -#define MV64360_CUNIT_DEBUG_HIGH 0xf344 -#define MV64360_CUNIT_MMASK 0xf380 - - /* Cunit Base Address Enable Window Bits*/ -#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 -#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 -#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 -#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 - - /* MPSCs Clocks Routing Registers */ - -#define MV64360_MPSC_ROUTING_REG 0xb400 -#define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64360_SDMA_CAUSE_REG 0xb800 -#define MV64360_SDMA_MASK_REG 0xb880 - - -/****************************************/ -/* SDMA Address Space Targets */ -/****************************************/ - -#define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00 -#define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00 -#define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00 -#define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700 - -#define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01 -#define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01 -#define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01 -#define MV64360_SDMA_DEV_CS_3_TARGET 0x1701 - -#define MV64360_SDMA_BOOT_CS_TARGET 0x0f00 - -#define MV64360_SDMA_SRAM_TARGET 0x0003 -#define MV64360_SDMA_60X_BUS_TARGET 0x4003 - -#define MV64360_PCI_0_TARGET 0x0003 -#define MV64360_PCI_1_TARGET 0x0004 - - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* SDMA Window access protection */ -#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0 -#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1 -#define MV64360_SDMA_WIN_ACCESS_FULL 2 - -/* BRG Interrupts */ - -#define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) -#define MV64360_BRG_CAUSE_REG 0xb834 -#define MV64360_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_CONTROL 0x840 -#define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64360_DMA_CHANNEL1_CONTROL 0x844 -#define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64360_DMA_CHANNEL2_CONTROL 0x848 -#define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64360_DMA_CHANNEL3_CONTROL 0x84C -#define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64360_DMA_BASE_ADDR_REG0 0xa00 -#define MV64360_DMA_BASE_ADDR_REG1 0xa08 -#define MV64360_DMA_BASE_ADDR_REG2 0xa10 -#define MV64360_DMA_BASE_ADDR_REG3 0xa18 -#define MV64360_DMA_BASE_ADDR_REG4 0xa20 -#define MV64360_DMA_BASE_ADDR_REG5 0xa28 -#define MV64360_DMA_BASE_ADDR_REG6 0xa30 -#define MV64360_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64360_DMA_SIZE_REG0 0xa04 -#define MV64360_DMA_SIZE_REG1 0xa0c -#define MV64360_DMA_SIZE_REG2 0xa14 -#define MV64360_DMA_SIZE_REG3 0xa1c -#define MV64360_DMA_SIZE_REG4 0xa24 -#define MV64360_DMA_SIZE_REG5 0xa2c -#define MV64360_DMA_SIZE_REG6 0xa34 -#define MV64360_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64360_DMA_ARBITER_CONTROL 0x860 -#define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64360_DMA_ERROR_ADDR 0x8c8 -#define MV64360_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64360_DMA_DEBUG_LOW 0x8e0 -#define MV64360_DMA_DEBUG_HIGH 0x8e4 -#define MV64360_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64360_TIMER_COUNTER0 0x850 -#define MV64360_TIMER_COUNTER1 0x854 -#define MV64360_TIMER_COUNTER2 0x858 -#define MV64360_TIMER_COUNTER3 0x85C -#define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64360_WATCHDOG_CONFIG_REG 0xb410 -#define MV64360_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64360_I2C_SLAVE_ADDR 0xc000 -#define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64360_I2C_DATA 0xc004 -#define MV64360_I2C_CONTROL 0xc008 -#define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64360_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64360_GPP_IO_CONTROL 0xf100 -#define MV64360_GPP_LEVEL_CONTROL 0xf110 -#define MV64360_GPP_VALUE 0xf104 -#define MV64360_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64360_GPP_INTERRUPT_MASK0 0xf10c -#define MV64360_GPP_INTERRUPT_MASK1 0xf114 -#define MV64360_GPP_VALUE_SET 0xf118 -#define MV64360_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64360_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64360_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64360_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64360_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64360_MPP_CONTROL0 0xf000 -#define MV64360_MPP_CONTROL1 0xf004 -#define MV64360_MPP_CONTROL2 0xf008 -#define MV64360_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64360_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64360_SERIAL_INIT_CONTROL 0xf328 -#define MV64360_SERIAL_INIT_STATUS 0xf32c - - -#endif /* __INCgt64360rh */ diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c deleted file mode 100644 index 3e44fb9..0000000 --- a/board/esd/cpci750/pci.c +++ /dev/null @@ -1,961 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* PCI.c - PCI functions */ - - -#include -#ifdef CONFIG_PCI -#include - -#ifdef CONFIG_PCI_PNP -void pciauto_config_init(struct pci_controller *hose); -int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar); -#endif - -#include "../../Marvell/include/pci.h" - -#undef DEBUG -#undef IDE_SET_NATIVE_MODE -static unsigned int local_buses[] = { 0, 0 }; - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { - {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, - {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, -}; - - -#ifdef DEBUG -static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; -static void gt_pci_bus_mode_display (PCI_HOST host) -{ - unsigned int mode; - - - mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; - switch (mode) { - case 0: - printf ("PCI %d bus mode: Conventional PCI\n", host); - break; - case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); - break; - case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); - break; - case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); - break; - default: - printf ("Unknown BUS %d\n", mode); - } -} -#endif - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_address_space_en[] = { - PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = 0; - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_WRITE (pci_configuration_data[host], data); -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, ®Base); - GT_REG_READ (regOffset + 8, ®End); - - if (regEnd <= regBase) - return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 16; - return regBase; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 16) & 0xffff; - high = ((bankBase + bankLength) >> 16) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xffff) << 16; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - return ((high & 0xffff) + 1) << 16; -} - - -/* ronen - 7/Dec/03*/ -/******************************************************************** -* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. -* Inputs: one of the PCI BAR -*********************************************************************/ -void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - /*ronen different function for 3rd bank. */ - unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; - - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + offset, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); - gtPciEnableInternalBAR (host, bank); -} - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData & regData); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum, unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE (pci_p2p_configuration[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), bus, - value); - } - return 0; -} - - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - /*ronen different function for 3rd bank. */ - unsigned int offset = - (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - - -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ -/* and is curently not called *. */ -#if 0 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - - {} -}; - -struct pci_controller pci0_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; -#ifdef CONFIG_PCI_PNP - unsigned int bar; -#endif - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST0); -#endif - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - -#ifdef CONFIG_PCI_PNP - pciauto_config_init(&pci0_hose); - pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar); -#endif -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno); - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); -#endif - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci1_hose.first_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -#ifdef CONFIG_PCI_PNP - pciauto_config_init(&pci1_hose); - pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar); -#endif - pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -} -#endif /* of CONFIG_PCI */ diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c deleted file mode 100644 index db545ef..0000000 --- a/board/esd/cpci750/sdram_init.c +++ /dev/null @@ -1,1683 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************* - * adaption for the Marvell DB64360 Board - * Ingo Assmus (ingo.assmus@keymile.com) - * - * adaption for the cpci750 Board - * Reinhard Arlt (reinhard.arlt@esd-electronics.com) - *************************************************************************/ - - -/* sdram_init.c - automatic memory sizing */ - -#include -#include <74xx_7xx.h> -#include "../../Marvell/include/memory.h" -#include "../../Marvell/include/pci.h" -#include "../../Marvell/include/mv_gen_reg.h" -#include - -#include "eth.h" -#include "mpsc.h" -#include "../../Marvell/common/i2c.h" -#include "64360.h" -#include "mv_regs.h" - - -#undef DEBUG -/* #define DEBUG */ -#ifdef CONFIG_PCI -#define MAP_PCI -#endif /* of CONFIG_PCI */ - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -int set_dfcdlInit(void); /* setup delay line of Mv64360 */ - -/* ------------------------------------------------------------------------- */ - -int -memory_map_bank(unsigned int bankNo, - unsigned int bankBase, - unsigned int bankLength) -{ -#ifdef MAP_PCI - PCI_HOST host; -#endif - - -#ifdef DEBUG - if (bankLength > 0) { - printf("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank(bankNo, bankBase, bankLength); - -#ifdef MAP_PCI - for (host=PCI_HOST0;host<=PCI_HOST1;host++) { - const int features= - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | - PCI_NO_SWAP; - - pciMapMemoryBank(host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength); - } -#endif - return 0; -} - -#define GB (1 << 30) - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; -} sdram_info_t; - -/* Typedefs for 'gtAuxilGetDIMMinfo' function */ - -typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE; - -typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, - SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, - } VOLTAGE_INTERFACE; - -typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR; -typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD; - - -/* SDRAM/DDR information struct */ -typedef struct _gtMemoryDimmInfo -{ - MEMORY_TYPE memoryType; - unsigned int numOfRowAddresses; - unsigned int numOfColAddresses; - unsigned int numOfModuleBanks; - unsigned int dataWidth; - VOLTAGE_INTERFACE voltageInterface; - unsigned int errorCheckType; /* ECC , PARITY..*/ - unsigned int sdramWidth; /* 4,8,16 or 32 */; - unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ - unsigned int minClkDelay; - unsigned int burstLengthSupported; - unsigned int numOfBanksOnEachDevice; - unsigned int suportedCasLatencies; - unsigned int RefreshInterval; - unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ - unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns)*/ - MAX_CL_SUPPORTED_DDR maxClSupported_DDR; - MAX_CL_SUPPORTED_SD maxClSupported_SD; - unsigned int moduleBankDensity; - /* module attributes (true for yes) */ - bool bufferedAddrAndControlInputs; - bool registeredAddrAndControlInputs; - bool onCardPLL; - bool bufferedDQMBinputs; - bool registeredDQMBinputs; - bool differentialClockInput; - bool redundantRowAddressing; - - /* module general attributes */ - bool suportedAutoPreCharge; - bool suportedPreChargeAll; - bool suportedEarlyRasPreCharge; - bool suportedWrite1ReadBurst; - bool suported5PercentLowVCC; - bool suported5PercentUpperVCC; - /* module timing parameters */ - unsigned int minRasToCasDelay; - unsigned int minRowActiveRowActiveDelay; - unsigned int minRasPulseWidth; - unsigned int minRowPrechargeTime; /* measured in ns */ - - int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ - int addrAndCommandSetupTime; /* (measured in ns/100) */ - int dataInputSetupTime; /* LoP left of point (measured in ns) */ - int dataInputHoldTime; /* LoP left of point (measured in ns) */ -/* tAC times for highest 2nd and 3rd highest CAS Latency values */ - unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns)*/ - unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns)*/ - unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns)*/ - - unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns)*/ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns)*/ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns)*/ - - /* Parameters calculated from - the extracted DIMM information */ - unsigned int size; - unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ - unsigned int numberOfDevices; - uchar drb_size; /* DRAM size in n*64Mbit */ - uchar slot; /* Slot Number this module is inserted in */ - uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ -#ifdef DEBUG - uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ - uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ - uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ - unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ - unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ - unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ - uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ - -#endif -} AUX_MEM_DIMM_INFO; - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short -NS10to10PS(unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return(ns*100 + ns10*10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short -NSto10PS(unsigned char spd_byte) -{ - return(spd_byte*100); -} - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ -static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned long spd_checksum; - - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; - -#ifdef DEBUG - unsigned int k; -#endif - unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; - int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; - uchar supp_cal, cal_val; - ulong memclk, tmemclk; - ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; - uchar data[128]; - - memclk = gd->bus_clk; - tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - - memset (data, 0, sizeof (data)); - - - ret = 0; - - DP (puts ("before i2c read\n")); - - ret = i2c_read (addr, 0, 2, data, 128); - - DP (puts ("after i2c read\n")); - - if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd') - || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm') - || (data[70] != 'b') || (data[71] != 'h')) { - ret = -1; - } - - if ((ret != 0) && (slot == 0)) { - memset (data, 0, sizeof (data)); - data[0] = 0x80; - data[1] = 0x08; - data[2] = 0x07; - data[3] = 0x0c; - data[4] = 0x09; - data[5] = 0x01; - data[6] = 0x48; - data[7] = 0x00; - data[8] = 0x04; - data[9] = 0x75; - data[10] = 0x80; - data[11] = 0x02; - data[12] = 0x80; - data[13] = 0x10; - data[14] = 0x08; - data[15] = 0x01; - data[16] = 0x0e; - data[17] = 0x04; - data[18] = 0x0c; - data[19] = 0x01; - data[20] = 0x02; - data[21] = 0x20; - data[22] = 0x00; - data[23] = 0xa0; - data[24] = 0x80; - data[25] = 0x00; - data[26] = 0x00; - data[27] = 0x50; - data[28] = 0x3c; - data[29] = 0x50; - data[30] = 0x32; - data[31] = 0x10; - data[32] = 0xb0; - data[33] = 0xb0; - data[34] = 0x60; - data[35] = 0x60; - data[64] = 'e'; - data[65] = 's'; - data[66] = 'd'; - data[67] = '-'; - data[68] = 'g'; - data[69] = 'm'; - data[70] = 'b'; - data[71] = 'h'; - ret = 0; - } - - /* zero all the values */ - memset (dimmInfo, 0, sizeof (*dimmInfo)); - - /* copy the SPD content 1:1 into the dimmInfo structure */ - for (i = 0; i <= 127; i++) { - dimmInfo->spd_raw_data[i] = data[i]; - } - - if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); - return 0; - } else - dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ - -#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT - - for (i = 0; i <= 127; i++) { - printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], - data[i]); - } - -#endif -#ifdef DEBUG - /* find Manufacturer of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { - dimmInfo->manufactura[i] = data[64 + i]; - } - printf ("\nThis RAM-Module is produced by: %s\n", - dimmInfo->manufactura); - - /* find Manul-ID of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { - dimmInfo->modul_id[i] = data[73 + i]; - } - printf ("The Module-ID of this RAM-Module is: %s\n", - dimmInfo->modul_id); - - /* find Vendor-Data of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { - dimmInfo->vendor_data[i] = data[99 + i]; - } - printf ("Vendor Data of this RAM-Module is: %s\n", - dimmInfo->vendor_data); - - /* find modul_serial_no of Dimm Module */ - dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); - printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", - dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); - - /* find Manufac-Data of Dimm Module */ - dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); - printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ - - /* find modul_revision of Dimm Module */ - dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); - printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ - - /* find manufac_place of Dimm Module */ - dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); - printf ("manufac_place of this RAM-Module is: %d\n", - dimmInfo->manufac_place); - -#endif -/*------------------------------------------------------------------------------------------------------------------------------*/ -/* calculate SPD checksum */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - spd_checksum = 0; -#if 0 /* test-only */ - for (i = 0; i <= 62; i++) { - spd_checksum += data[i]; - } - - if ((spd_checksum & 0xff) != data[63]) { - printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); - hang (); - } - - else - printf ("SPD Checksum ok!\n"); -#endif /* test-only */ - -/*------------------------------------------------------------------------------------------------------------------------------*/ - for (i = 2; i <= 35; i++) { - switch (i) { - case 2: /* Memory type (DDR / SDRAM) */ - dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; -#ifdef DEBUG - if (dimmInfo->memoryType == 0) - DP (printf - ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); - if (dimmInfo->memoryType == 1) - DP (printf - ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 3: /* Number Of Row Addresses */ - dimmInfo->numOfRowAddresses = data[i]; - DP (printf - ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 4: /* Number Of Column Addresses */ - dimmInfo->numOfColAddresses = data[i]; - DP (printf - ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 5: /* Number Of Module Banks */ - dimmInfo->numOfModuleBanks = data[i]; - DP (printf - ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 6: /* Data Width */ - dimmInfo->dataWidth = data[i]; - DP (printf - ("Module Data Width: %d\n", - dimmInfo->dataWidth)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 8: /* Voltage Interface */ - switch (data[i]) { - case 0x0: - dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); - break; - case 0x1: - dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); - break; - case 0x2: - dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); - break; - case 0x3: - dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); - break; - case 0x4: - dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); - break; - default: - dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); - break; - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 9: /* Minimum Cycle Time At Max CasLatancy */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = - rightOfPoint; - DP (printf - ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 10: /* Clock To Data Out */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOut_LoP = leftOfPoint; - dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out: %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); - /*dimmInfo->clockToDataOut */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - -#ifdef CONFIG_ECC - case 11: /* Error Check Type */ - dimmInfo->errorCheckType = data[i]; - DP (printf - ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); - break; -#endif -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 12: /* Refresh Interval */ - dimmInfo->RefreshInterval = data[i]; - DP (printf - ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 13: /* Sdram Width */ - dimmInfo->sdramWidth = data[i]; - DP (printf - ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 14: /* Error Check Data Width */ - dimmInfo->errorCheckDataWidth = data[i]; - DP (printf - ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 15: /* Minimum Clock Delay */ - dimmInfo->minClkDelay = data[i]; - DP (printf - ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 16: /* Burst Length Supported */ - /******-******-******-******* - * bit3 | bit2 | bit1 | bit0 * - *******-******-******-******* - burst length = * 8 | 4 | 2 | 1 * - ***************************** - - If for example bit0 and bit2 are set, the burst - length supported are 1 and 4. */ - - dimmInfo->burstLengthSupported = data[i]; -#ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); - if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); - if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); - if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); - if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 17: /* Number Of Banks On Each Device */ - dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf - ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 18: /* Suported Cas Latencies */ - - /* DDR: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - ********************************************************* - SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - dimmInfo->suportedCasLatencies = data[i]; -#ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); - if (dimmInfo->memoryType == 0) { /* SDRAM */ - for (k = 0; k <= 7; k++) { - if (dimmInfo-> - suportedCasLatencies & (1 << k)) - DP (printf - ("%d, ", - k + 1)); - } - - } else { /* DDR-RAM */ - - if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); - if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); - if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); - if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); - if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); - if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); - - } - DP (printf ("\n")); -#endif - /* Calculating MAX CAS latency */ - for (j = 7; j > 0; j--) { - if (((dimmInfo-> - suportedCasLatencies >> j) & 0x1) == - 1) { - switch (dimmInfo->memoryType) { - case DDR: - /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ - switch (j) { - case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3_5; - break; - case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3; - break; - case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2_5; - break; - case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2; - break; - case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_1_5; - break; - } - dimmInfo-> - maxCASlatencySupported_LoP - = - 1 + - (int) (5 * j / 10); - if (((5 * j) % 10) != 0) - dimmInfo-> - maxCASlatencySupported_RoP - = 5; - else - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - DP (printf - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP)); - break; - case SDRAM: - /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ - dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf - ("Max. Cas Latencies (SD): %d\n", - dimmInfo-> - maxClSupported_SD)); - dimmInfo-> - maxCASlatencySupported_LoP - = j; - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - DP (printf - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP)); - break; - } - break; - } - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); - dimmInfo->bufferedAddrAndControlInputs = - data[i] & BIT0; - dimmInfo->registeredAddrAndControlInputs = - (data[i] & BIT1) >> 1; - dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; - dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; - dimmInfo->registeredDQMBinputs = - (data[i] & BIT4) >> 4; - dimmInfo->differentialClockInput = - (data[i] & BIT5) >> 5; - dimmInfo->redundantRowAddressing = - (data[i] & BIT6) >> 6; -#ifdef DEBUG - if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); - else - DP (printf - (" - Buffered Address/Control Input: No \n")); - - if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); - else - DP (printf - (" - Registered Address/Control Input: No \n")); - - if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); - else - DP (printf - (" - On-Card PLL (clock): No \n")); - - if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); - else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); - - if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); - else - DP (printf - (" - Registered DQMB Inputs: No \n")); - - if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); - else - DP (printf - (" - Differential Clock Input: No \n")); - - if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); - else - DP (printf - (" - redundant Row Addressing: No \n")); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); - dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; - dimmInfo->suportedAutoPreCharge = - (data[i] & BIT1) >> 1; - dimmInfo->suportedPreChargeAll = - (data[i] & BIT2) >> 2; - dimmInfo->suportedWrite1ReadBurst = - (data[i] & BIT3) >> 3; - dimmInfo->suported5PercentLowVCC = - (data[i] & BIT4) >> 4; - dimmInfo->suported5PercentUpperVCC = - (data[i] & BIT5) >> 5; -#ifdef DEBUG - if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); - else - DP (printf - (" - Early Ras Precharge: No \n")); - - if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); - else - DP (printf - (" - AutoPreCharge: No \n")); - - if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); - else - DP (printf - (" - Precharge All: No \n")); - - if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); - else - DP (printf - (" - Write 1/ReadBurst: No \n")); - - if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); - else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); - - if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); - else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = - rightOfPoint; - DP (printf - ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); - /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = - rightOfPoint; - DP (printf - ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); - /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 27: /* Minimum Row Precharge Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ - trp_clocks = - (dimmInfo->minRowPrechargeTime + - (tmemclk - 1)) / tmemclk; - DP (printf - ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf - ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 28: /* Minimum Row Active to Row Active Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 29: /* Minimum Ras-To-Cas Delay */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 30: /* Minimum Ras Pulse Width */ - dimmInfo->minRasPulseWidth = data[i]; - tras_clocks = - (NSto10PS (data[i]) + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 31: /* Module Bank Density */ - dimmInfo->moduleBankDensity = data[i]; - DP (printf - ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); -#ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); - { - if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); - if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); - if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); - if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); - if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); - if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); - if ((dimmInfo->moduleBankDensity & 64) - || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); - hang (); - } - } - DP (printf ("\n")); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 32: /* Address And Command Setup Time (measured in ns/1000) */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 33: /* Address And Command Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 34: /* Data Input Setup Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 35: /* Data Input Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - } - } - /* calculating the sdram density */ - for (i = 0; - i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; - i++) { - density = density * 2; - } - dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * - dimmInfo->sdramWidth; - dimmInfo->numberOfDevices = - (dimmInfo->dataWidth / dimmInfo->sdramWidth) * - dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; - if ((dimmInfo->errorCheckType == 0x1) - || (dimmInfo->errorCheckType == 0x2) - || (dimmInfo->errorCheckType == 0x3)) { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - (dimmInfo->numberOfDevices - devicesForErrCheck); - } else { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - dimmInfo->numberOfDevices; - } - - /* compute the module DRB size */ - tmp = (1 << - (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); - tmp *= dimmInfo->numOfModuleBanks; - tmp *= dimmInfo->sdramWidth; - tmp = tmp >> 24; /* div by 0x4000000 (64M) */ - dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); - - /* try a CAS latency of 3 first... */ - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1; - - cal_val = 0; - if (supp_cal & 8) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 6; - } - if (supp_cal & 4) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 5; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 4; - } - - DP (printf ("cal_val = %d\n", cal_val * 5)); - - /* bummer, did't work... */ - if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); - hang (); - return 0; - } - - return true; -} - -/* sets up the GT properly with information passed in */ -int setup_sdram (AUX_MEM_DIMM_INFO * info) -{ - ulong tmp, check; - ulong tmp_sdram_mode = 0; /* 0x141c */ - ulong tmp_dunit_control_low = 0; /* 0x1404 */ - int i; - - /* sanity checking */ - if (!info->numOfModuleBanks) { - printf ("setup_sdram called with 0 banks\n"); - return 1; - } - - /* delay line */ - - /* Program the GT with the discovered data */ - if (info->registeredAddrAndControlInputs == true) - DP (printf - ("Module is registered, but we do not support registered Modules !!!\n")); - - - /* delay line */ - set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); - - /* set SDRAM mode NOP */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); - } - - /* SDRAM configuration */ - GT_REG_WRITE (SDRAM_CONFIG, 0x58200400); - DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG))); - - /* SDRAM open pages controll keep open as much as I can */ - GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf - ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); - - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); - else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); - - /* SDRAM set CAS Lentency according to SPD information */ - switch (info->memoryType) { - case SDRAM: - DP (printf ("### SD-RAM not supported yet !!!\n")); - hang (); - /* ToDo fill SD-RAM if needed !!!!! */ - break; - - case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); - - switch (info->maxClSupported_DDR) { - case DDR_CL_3: - tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */ - tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ - DP (printf - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - break; - - case DDR_CL_2_5: - if (tmp == 1) { /* clocks sync */ - tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */ - tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } else { /* clk sync. bypassed */ - - tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } - break; - - case DDR_CL_2: - if (tmp == 1) { /* Sync */ - tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - DP (printf - ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } else { /* Not sync. */ - - tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - DP (printf - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } - break; - - case DDR_CL_1_5: - if (tmp == 1) { /* Sync */ - tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */ - tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } else { /* not sync */ - - tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); - } - break; - - default: - printf ("Max. CL is out of range %d\n", - info->maxClSupported_DDR); - hang (); - break; - } - break; - } - - /* Write results of CL detection procedure */ - GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); - } - - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp != 1) { /*clocks are not sync */ - /* asyncmode */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, - (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) | - 0x18110780 | tmp_dunit_control_low); - } else { - /* syncmode */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, - (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) | - 0x00110000 | tmp_dunit_control_low); - } - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); - } - -/*------------------------------------------------------------------------------ */ - - - /* bank parameters */ - /* SDRAM address decode register */ - /* program this with the default value */ - tmp = 0x02; - - - DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); - switch (info->drb_size) { - case 1: /* 64 Mbit */ - case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); - tmp |= (0x00 << 4); - break; - case 4: /* 256 Mbit */ - case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); - tmp |= (0x01 << 4); - break; - case 16: /* 1 Gbit */ - case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); - tmp |= (0x02 << 4); - break; - default: - printf ("Error in dram size calculation\n"); - DP (printf ("Assume: RAM-Device_size 1Gbit or 2Gbit)\n")); - tmp |= (0x02 << 4); - return 1; - } - - /* SDRAM bank parameters */ - /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ - DP (printf - ("setting up slot %d config with: %08lx \n", info->slot, tmp)); - GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - -/* ------------------------------------------------------------------------------ */ - - DP (printf - ("setting up sdram_timing_control_low with: %08x \n", - 0x11511220)); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); - - -/* ------------------------------------------------------------------------------ */ - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIG); - - if (info->registeredAddrAndControlInputs - || info->registeredDQMBinputs) { - tmp |= (1 << 17); - DP (printf - ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", - info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); - } - - /* Use buffer 1 to return read data to the CPU - * Page 426 MV64360 */ - tmp |= (1 << 26); - DP (printf - ("Before Buffer assignment - sdram_conf: %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf - ("After Buffer assignment - sdram_conf: %08x\n", - GTREGREAD (SDRAM_CONFIG))); - - /* SDRAM timing To_do: */ - - - tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH); - DP (printf ("# sdram_timing_control_high is : %08lx \n", tmp)); - - /* SDRAM address decode register */ - /* program this with the default value */ - tmp = GTREGREAD (SDRAM_ADDR_CONTROL); - DP (printf - ("SDRAM address control (before: decode): %08x ", - GTREGREAD (SDRAM_ADDR_CONTROL))); - GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2)); - DP (printf - ("SDRAM address control (after: decode): %08x\n", - GTREGREAD (SDRAM_ADDR_CONTROL))); - - /* set the SDRAM configuration for each bank */ - -/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ - { - i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); -#if 1 /* test only */ - /* set SDRAM mode */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - check = GTREGREAD (SDRAM_OPERATION); - DP (printf - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); - - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION, 0); - check = GTREGREAD (SDRAM_OPERATION); - DP (printf - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); -#endif /* test only */ - /* unmap the bank */ - memory_map_bank (i, 0, 0); - } - - return 0; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -long int -dram_size(long int *base, long int maxsize) -{ - volatile long int *addr, *b=base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1=*addr; /* save contents of addr */ - save2=*b; /* save contents of base */ - - *addr=cnt; /* write cnt to addr */ - *b=0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr=save1; /* restore *addr */ - *b=save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - val = *addr; /* read *addr */ - - *addr=save1; - *b=save2; - - if (val != cnt) { - DP(printf("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr)); - /* fix boundary condition.. STARTVAL means zero */ - if(cnt==STARTVAL/sizeof(long)) cnt=0; - return (cnt * sizeof(long)); - } - } - return maxsize; -} - -/* ------------------------------------------------------------------------- */ - -/* ppcboot interface function to SDRAM init - this is where all the - * controlling logic happens */ -long int -initdram(int board_type) -{ - int s0 = 0, s1 = 0; - int checkbank[4] = { [0 ... 3] = 0 }; - ulong bank_no, realsize, total, check; - AUX_MEM_DIMM_INFO dimmInfo1; - AUX_MEM_DIMM_INFO dimmInfo2; - int nhr; - - /* first, use the SPD to get info about the SDRAM/ DDRRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0() & (1 << 16); - - if (nhr) { - printf("Skipping SD- DDRRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - s0 = check_dimm(0, &dimmInfo1); - - /* DIMM1 */ - s1 = check_dimm(1, &dimmInfo2); - - memory_map_bank(0, 0, 0); - memory_map_bank(1, 0, 0); - memory_map_bank(2, 0, 0); - memory_map_bank(3, 0, 0); - - if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) { - printf("Setup for DIMM1 failed.\n"); - } - - if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) { - printf("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0(get_hid0() | (1 << 16)); - } - /* next, size the SDRAM banks */ - - realsize = total = 0; - check = GB/4; - if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");} - if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");} - if (dimmInfo1.numOfModuleBanks > 2) - printf("Error, SPD claims DIMM1 has >2 banks\n"); - - if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");} - if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");} - if (dimmInfo2.numOfModuleBanks > 2) - printf("Error, SPD claims DIMM2 has >2 banks\n"); - - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (! checkbank[bank_no]) - continue; - - if ((total + check) > CFG_GT_REGS) - check = CFG_GT_REGS - total; - - memory_map_bank(bank_no, total, check); - realsize = dram_size((long int *)total, check); - memory_map_bank(bank_no, total, realsize); - - total += realsize; - } - -/* Setup Ethernet DMA Adress window to DRAM Area */ - return(total); -} - -/* *************************************************************************************** -! * SDRAM INIT * -! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * -! * This procedure fits only the Atlantis * -! * * -! *************************************************************************************** */ - - -/* *************************************************************************************** -! * DFCDL initialize MV643xx Design Considerations * -! * * -! *************************************************************************************** */ -int set_dfcdlInit (void) -{ - int i; - unsigned int dfcdl_word = 0x0000014f; - - for (i = 0; i < 64; i++) { - GT_REG_WRITE (SRAM_DATA0, dfcdl_word); - } - GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ - - - return (0); -} diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c deleted file mode 100644 index 44de052..0000000 --- a/board/esd/cpci750/serial.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * modified for cpci750 board by - * Reinhard Arlt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * serial.c - serial support for esd cpci750 board - */ - -/* supports the MPSC */ - -#include -#include -#include "../../Marvell/include/memory.h" -#include "serial.h" - - -#include "mpsc.h" - -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - mpsc_init (gd->baudrate); - - return (0); -} - -void serial_putc (const char c) -{ - if (c == '\n') - mpsc_putchar ('\r'); - - mpsc_putchar (c); -} - -int serial_getc (void) -{ - return mpsc_getchar (); -} - -int serial_tstc (void) -{ - return mpsc_test_char (); -} - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); -} - - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -void kgdb_serial_init (void) -{ -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif /* CFG_CMD_KGDB */ diff --git a/board/esd/cpci750/serial.h b/board/esd/cpci750/serial.h deleted file mode 100644 index c7fc8c1..0000000 --- a/board/esd/cpci750/serial.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/esd/cpci750/strataflash.c b/board/esd/cpci750/strataflash.c deleted file mode 100644 index c22fe5d..0000000 --- a/board/esd/cpci750/strataflash.c +++ /dev/null @@ -1,763 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;iportwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; iportwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; isector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * - */ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio = 0; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - invalidate_dcache_range(base, base+0x400); - - if(flash_detect_cfi(info)){ - - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); - - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif -#ifdef DEBUG_FLASH - printf("size=%08x sectors=%08x \n", info->size, info->sector_count); -#endif - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpci750/u-boot.lds b/board/esd/cpci750/u-boot.lds deleted file mode 100644 index d89eb6c..0000000 --- a/board/esd/cpci750/u-boot.lds +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/74xx_7xx/start.o (.text) - -/* store the environment in a seperate sector in the boot flash */ -/* . = env_offset; */ -/* common/environment.o(.text) */ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile deleted file mode 100644 index a60495a..0000000 --- a/board/esd/cpciiser4/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/cpciiser4/config.mk b/board/esd/cpciiser4/config.mk deleted file mode 100644 index 58574cb..0000000 --- a/board/esd/cpciiser4/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd CPCIISER4 boards -# - -#TEXT_BASE = 0xFFFE0000 -#TEXT_BASE = 0xFFFD0000 -TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c deleted file mode 100644 index 7bf7bb5..0000000 --- a/board/esd/cpciiser4/cpciiser4.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * (C) Copyright 2000 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "cpciiser4.h" -#include -#include - -/*cmd_boot.c*/ - -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -extern void lxt971_no_sleep(void); - - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -#if 0 -#define FPGA_DEBUG2 -#endif - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int index, len, i; - volatile unsigned char dummy; - int status; - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - - /* - * Boot onboard FPGA - */ - status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc ('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf ("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay (1000); - } - putc ('\n'); - do_reset (NULL, 0, 0, NULL); - } - - /* - * Init FPGA via RESET (read access on CS3) - */ - dummy = *(unsigned char *) 0xf0200000; - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - /* mtdcr(uicpr, 0xFFFFFF81); / set int polarities */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming AR405"); - } else { - puts(str); - } - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("%s ", &(fpgadata[index + 1])); - index += len + 3; - } - - putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/esd/cpciiser4/cpciiser4.h b/board/esd/cpciiser4/cpciiser4.h deleted file mode 100644 index 5fc313a..0000000 --- a/board/esd/cpciiser4/cpciiser4.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c deleted file mode 100644 index de847f9..0000000 --- a/board/esd/cpciiser4/flash.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/dasa_sim/Makefile b/board/esd/dasa_sim/Makefile deleted file mode 100644 index e3b1c87..0000000 --- a/board/esd/dasa_sim/Makefile +++ /dev/null @@ -1,47 +0,0 @@ - -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c deleted file mode 100644 index 89a4aaf..0000000 --- a/board/esd/dasa_sim/cmd_dasa_sim.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -#define OK 0 -#define ERROR (-1) - -#define TRUE 1 -#define FALSE 0 - - -extern u_long pci9054_iobase; - - -/*************************************************************************** - * - * Routines for PLX PCI9054 eeprom access - * - */ - -static unsigned int PciEepromReadLongVPD (int offs) -{ - unsigned int value; - unsigned int ret; - int count; - - pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c, - (offs << 16) | 0x0003); - count = 0; - - for (;;) { - udelay (10 * 1000); - pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret); - if ((ret & 0x80000000) != 0) { - break; - } else { - count++; - if (count > 10) { - printf ("\nTimeout: ret=%08x - Please try again!\n", ret); - break; - } - } - } - - pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x50, &value); - - return value; -} - - -static int PciEepromWriteLongVPD (int offs, unsigned int value) -{ - unsigned int ret; - int count; - - pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x50, value); - pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c, - (offs << 16) | 0x80000003); - count = 0; - - for (;;) { - udelay (10 * 1000); - pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret); - if ((ret & 0x80000000) == 0) { - break; - } else { - count++; - if (count > 10) { - printf ("\nTimeout: ret=%08x - Please try again!\n", ret); - break; - } - } - } - - return TRUE; -} - - -static void showPci9054 (void) -{ - int val; - int l, i; - - /* read 9054-values */ - for (l = 0; l < 6; l++) { - printf ("%02x: ", l * 0x10); - for (i = 0; i < 4; i++) { - pci_read_config_dword (CFG_PCI9054_DEV_FN, - l * 16 + i * 4, - (unsigned int *)&val); - printf ("%08x ", val); - } - printf ("\n"); - } - printf ("\n"); - - for (l = 0; l < 7; l++) { - printf ("%02x: ", l * 0x10); - for (i = 0; i < 4; i++) - printf ("%08x ", - PciEepromReadLongVPD ((i + l * 4) * 4)); - printf ("\n"); - } - printf ("\n"); -} - - -static void updatePci9054 (void) -{ - int val; - - /* - * Set EEPROM write-protect register to 0 - */ - out32 (pci9054_iobase + 0x0c, - in32 (pci9054_iobase + 0x0c) & 0xffff00ff); - - /* Long Serial EEPROM Load Registers... */ - val = PciEepromWriteLongVPD (0x00, 0x905410b5); - val = PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */ - val = PciEepromWriteLongVPD (0x08, 0x28140100); - - val = PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */ - val = PciEepromWriteLongVPD (0x10, 0x00000000); - - /* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */ - val = PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */ - val = PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */ - - val = PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */ - val = PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */ - - val = PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */ - val = PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */ - - val = PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */ - - val = PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */ - val = PciEepromWriteLongVPD (0x34, 0x00000000); - val = PciEepromWriteLongVPD (0x38, 0x00000000); - - val = PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */ - val = PciEepromWriteLongVPD (0x40, 0x00000000); - - /* Extra Long Serial EEPROM Load Registers... */ - val = PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */ - - /* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */ - /* Offset to LAS1: Group 1: 0x00040000 */ - /* Group 2: 0x00080000 */ - /* Group 3: 0x000c0000 */ - val = PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */ - val = PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */ - val = PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */ - - val = PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */ - - printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n"); -} - - -static void clearPci9054 (void) -{ - int val; - - /* - * Set EEPROM write-protect register to 0 - */ - out32 (pci9054_iobase + 0x0c, - in32 (pci9054_iobase + 0x0c) & 0xffff00ff); - - /* Long Serial EEPROM Load Registers... */ - val = PciEepromWriteLongVPD (0x00, 0xffffffff); - val = PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */ - - printf ("Finished clearing PLX PCI9054 EEPROM!\n"); -} - - -/* ------------------------------------------------------------------------- */ -int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc, - char *argv[]) -{ - if (strcmp (argv[1], "info") == 0) { - showPci9054 (); - return 0; - } - - if (strcmp (argv[1], "update") == 0) { - updatePci9054 (); - return 0; - } - - if (strcmp (argv[1], "clear") == 0) { - clearPci9054 (); - return 0; - } - - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - -} - -U_BOOT_CMD( - pci9054, 3, 1, do_pci9054, - "pci9054 - PLX PCI9054 EEPROM access\n", - "pci9054 info - print EEPROM values\n" - "pci9054 update - updates EEPROM with default values\n" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/esd/dasa_sim/config.mk b/board/esd/dasa_sim/config.mk deleted file mode 100644 index 747f29f..0000000 --- a/board/esd/dasa_sim/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -# FLASH: -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0xFFFD0000 - -# SDRAM: -#TEXT_BASE = 0x00FE0000 diff --git a/board/esd/dasa_sim/dasa_sim.c b/board/esd/dasa_sim/dasa_sim.c deleted file mode 100644 index 2f8ab1a..0000000 --- a/board/esd/dasa_sim/dasa_sim.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "dasa_sim.h" - -/* ------------------------------------------------------------------------- */ - -#undef FPGA_DEBUG - -#define _NOT_USED_ 0xFFFFFFFF - -/* ------------------------------------------------------------------------- */ - -/* fpga configuration data - generated by bit2inc */ -static unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */ -#define LOAD_LONG(a) a - - -/****************************************************************************** - * - * sysFpgaBoot - Load fpga-image into fpga - * - */ -static int fpgaBoot (void) -{ - int i, j, index, len; - unsigned char b; - int imageSize; - - imageSize = sizeof (fpgadata); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - index += len + 3; - } - - /* search for preamble 0xFF2X */ - for (index = 0; index < imageSize - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x20)) - break; - } - - /* enable cs1 instead of user0... */ - *(unsigned long *) 0x50000084 &= ~0x00000002; - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE"); -#endif - - /* init fpga by asserting and deasserting PROGRAM* (USER2)... */ - *(unsigned long *) 0x50000084 &= ~0x00000400; - udelay (FPGA_PRG_SLEEP * 1000); - - *(unsigned long *) 0x50000084 |= 0x00000400; - udelay (FPGA_PRG_SLEEP * 1000); - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE"); -#endif - - /* cs1: disable burst, disable ready */ - *(unsigned long *) 0x50000114 &= ~0x00000300; - - /* cs1: set write timing */ - *(unsigned long *) 0x50000118 |= 0x00010900; - - /* write configuration-data into fpga... */ - for (i = index; i < imageSize; i++) { - b = fpgadata[i]; - for (j = 0; j < 8; j++) { - *(unsigned long *) 0x30000000 = - ((b & 0x80) == 0x80) - ? LOAD_LONG (0x03030101) - : LOAD_LONG (0x02020000); - b <<= 1; - } - } - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE"); -#endif - - /* set cs1 to 32 bit data-width, disable burst, enable ready */ - *(unsigned long *) 0x50000114 |= 0x00000202; - *(unsigned long *) 0x50000114 &= ~0x00000100; - - /* cs1: set iop access to little endian */ - *(unsigned long *) 0x50000114 &= ~0x00000010; - - /* cs1: set read and write timing */ - *(unsigned long *) 0x50000118 = 0x00010000; - *(unsigned long *) 0x5000011c = 0x00010001; - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE"); -#endif - - /* wait for 30 ms... */ - udelay (30 * 1000); - /* check if fpga's DONE signal - correctly booted ? */ - if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0) - return -1; - - return 0; -} - - -int board_early_init_f (void) -{ - /* - * Init pci regs - */ - *(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */ - *(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */ - *(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */ - *(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */ - *(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */ - *(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */ - *(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */ - - return 0; -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); - int fpga; - unsigned short val; - - puts ("Board: "); - - /* - * Boot onboard FPGA - */ - fpga = fpgaBoot (); - - if (!i || strncmp (str, "DASA_SIM", 8)) { - puts ("### No HW ID - assuming DASA_SIM"); - } - - puts (str); - - if (fpga == 0) { - val = *(unsigned short *) 0x30000202; - printf (" (Id=%d Version=%d Revision=%d)", - (val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1); - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("%s ", &(fpgadata[index + 1])); - index += len + 3; - } - } else { - puts ("\nFPGA: Booting failed!"); - } - - putc ('\n'); - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/esd/dasa_sim/dasa_sim.h b/board/esd/dasa_sim/dasa_sim.h deleted file mode 100644 index 5fc313a..0000000 --- a/board/esd/dasa_sim/dasa_sim.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/dasa_sim/eeprom.c b/board/esd/dasa_sim/eeprom.c deleted file mode 100644 index 1b4c7b3..0000000 --- a/board/esd/dasa_sim/eeprom.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include - - -#define EEPROM_CAP 0x50000358 -#define EEPROM_DATA 0x5000035c - - -unsigned int eepromReadLong(int offs) -{ - unsigned int value; - volatile unsigned short ret; - int count; - - *(unsigned short *)EEPROM_CAP = offs; - - count = 0; - - for (;;) - { - count++; - ret = *(unsigned short *)EEPROM_CAP; - - if ((ret & 0x8000) != 0) - break; - } - - value = *(unsigned long *)EEPROM_DATA; - - return value; -} - - -unsigned char eepromReadByte(int offs) -{ - unsigned int valueLong; - unsigned char *ptr; - - valueLong = eepromReadLong(offs & ~3); - ptr = (unsigned char *)&valueLong; - - return ptr[offs & 3]; -} - - -void eepromWriteLong(int offs, unsigned int value) -{ - volatile unsigned short ret; - int count; - - count = 0; - - *(unsigned long *)EEPROM_DATA = value; - *(unsigned short *)EEPROM_CAP = 0x8000 + offs; - - for (;;) - { - count++; - ret = *(unsigned short *)EEPROM_CAP; - - if ((ret & 0x8000) == 0) - break; - } -} - - -void eepromWriteByte(int offs, unsigned char valueByte) -{ - unsigned int valueLong; - unsigned char *ptr; - - valueLong = eepromReadLong(offs & ~3); - ptr = (unsigned char *)&valueLong; - - ptr[offs & 3] = valueByte; - - eepromWriteLong(offs & ~3, valueLong); -} - - -void i2c_read (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - int len2, ptr; - - /* printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */ - - ptr = *(short *)addr; - - /* - * Read till lword boundary - */ - len2 = 4 - (*(short *)addr & 0x0003); - for (i=0; i> 2; - for (i=0; i> 2; - for (i=0; i -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - unsigned long base_b0; - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile deleted file mode 100644 index a11ee82..0000000 --- a/board/esd/dp405/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -# Objects for Xilinx JTAG programming (CPLD) -CPLD = ../common/xilinx_jtag/lenval.o \ - ../common/xilinx_jtag/micro.o \ - ../common/xilinx_jtag/ports.o - -OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/dp405/config.mk b/board/esd/dp405/config.mk deleted file mode 100644 index 3041b77..0000000 --- a/board/esd/dp405/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd VOH405 boards -# - -TEXT_BASE = 0xFFFC0000 -#TEXT_BASE = 0x00FC0000 diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c deleted file mode 100644 index fd51f7f..0000000 --- a/board/esd/dp405/dp405.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - - -/* fpga configuration data - not compressed, generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; -int filesize = sizeof(fpgadata); - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ - - /* - * Reset CPLD via GPIO13 (CS4) pin - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(0x80000000 >> 13)); - udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | (0x80000000 >> 13)); - udelay(1000); /* wait 1ms */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe, - 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf}; - unsigned char id1, id2; - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming DP405"); - } else { - puts(str); - } - - id1 = trans[(~(in32(GPIO0_IR) >> 5)) & 0x0000000f]; - id2 = trans[(~(in32(GPIO0_IR) >> 9)) & 0x0000000f]; - printf(" (ID=0x%1X%1X, PLD=0x%02X)\n", id2, id1, in8(0xf0001000)); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c deleted file mode 100644 index 89af119..0000000 --- a/board/esd/dp405/flash.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile deleted file mode 100644 index 5ec4a4f..0000000 --- a/board/esd/du405/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/du405/config.mk b/board/esd/du405/config.mk deleted file mode 100644 index d091d96..0000000 --- a/board/esd/du405/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd CPCIISER4 boards -# - -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0xFFFD0000 -#TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c deleted file mode 100644 index 26e8341..0000000 --- a/board/esd/du405/du405.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "du405.h" -#include -#include -#include <405gp_i2c.h> -#include - -/*cmd_boot.c*/ - -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -extern void lxt971_no_sleep(void); - - -#if 0 -#define FPGA_DEBUG -#endif - -#if 0 -#define FPGA_DEBUG2 -#endif - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int index, len, i; - int status; - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - - /* - * Boot onboard FPGA - */ - status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc ('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf ("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay (1000); - } - putc ('\n'); - do_reset (NULL, 0, 0, NULL); - } - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive - * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive - * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive - * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive - * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFFB1); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 100 us - */ - mtebc (epcr, 0xb8400000); - - return 0; -} - - -int misc_init_r (void) -{ - unsigned long cntrl0Reg; - - /* - * Setup UART1 handshaking: use CTS instead of DSR - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); - - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming DU405"); - } else { - puts (str); - } - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("%s ", &(fpgadata[index + 1])); - index += len + 3; - } - - putc ('\n'); - - /* - * Reset external DUART via FPGA - */ - *(volatile unsigned char *) FPGA_MODE_REG = 0xff; /* reset high active */ - *(volatile unsigned char *) FPGA_MODE_REG = 0x00; /* low again */ - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} - - -long int initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} diff --git a/board/esd/du405/du405.h b/board/esd/du405/du405.h deleted file mode 100644 index 768e843..0000000 --- a/board/esd/du405/du405.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c deleted file mode 100644 index 14549c0..0000000 --- a/board/esd/du405/flash.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - base_b0 = FLASH_BASE0_PRELIM; - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - base_b1 = FLASH_BASE1_PRELIM; - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); - base_b1 = -size_b1; - pbcr = (pbcr & 0x0001ffff) | base_b1 | - (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); - base_b0 = base_b1 - size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | - (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ - } - - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b1 + size_b1 - monitor_flash_len, - base_b1 + size_b1 - 1, &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect (FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/du405/fpgadata.c b/board/esd/du405/fpgadata.c deleted file mode 100644 index fd80d2c..0000000 --- a/board/esd/du405/fpgadata.c +++ /dev/null @@ -1,703 +0,0 @@ - 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d, - 0x64,0x75,0x72,0x61,0x67,0x34,0x30,0x35,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b, - 0x73,0x32,0x30,0x78,0x6c,0x74,0x71,0x31,0x34,0x34,0x00,0x63,0x00,0x0b,0x32,0x30, - 0x30,0x32,0x2f,0x30,0x32,0x2f,0x32,0x31,0x00,0x64,0x00,0x09,0x31,0x32,0x3a,0x35, - 0x31,0x3a,0x30,0x38,0x00,0x65,0xe2,0x01,0x00,0x00,0x2b,0x98,0xff,0x30,0xe6,0xe5, - 0xe5,0x02,0x04,0x01,0xe6,0x04,0x01,0x0d,0x04,0x04,0x02,0x01,0x04,0x04,0x03,0x07, - 0x01,0x03,0x01,0x04,0x11,0x01,0x06,0x02,0x15,0x09,0x02,0x05,0x07,0x02,0x02,0x01, - 0x09,0x03,0x07,0x01,0x03,0x01,0x0b,0x05,0x03,0x01,0x07,0x08,0xe5,0xe5,0x24,0x05, - 0x09,0x11,0x01,0x03,0x03,0x05,0x0d,0x09,0x0b,0x09,0x01,0x1d,0x09,0x13,0x03,0x05, - 0x12,0xe6,0x11,0x01,0x03,0x02,0x02,0x03,0x03,0x01,0x15,0x01,0x02,0x28,0x01,0x05, - 0x02,0xe5,0xe5,0x02,0x02,0x02,0x0d,0x02,0x02,0x03,0x02,0xe5,0xe5,0x14,0x01,0x02, - 0xe5,0x12,0x0b,0x03,0x0f,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x02,0x06,0x02,0x09, - 0x06,0xe7,0x05,0x04,0x06,0x02,0x06,0x02,0x09,0x07,0xe6,0x08,0x09,0x07,0xe6,0x08, - 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0xff,0xff,0xff,0xff, diff --git a/board/esd/du405/u-boot.lds b/board/esd/du405/u-boot.lds deleted file mode 100644 index 1cf375f..0000000 --- a/board/esd/du405/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile deleted file mode 100644 index 9340a32..0000000 --- a/board/esd/hh405/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/hh405/config.mk b/board/esd/hh405/config.mk deleted file mode 100644 index 7129ad5..0000000 --- a/board/esd/hh405/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd VOH405 boards -# - -#TEXT_BASE = 0xFFF00000 -TEXT_BASE = 0xFFF80000 -#TEXT_BASE = 0xFFFC0000 -#TEXT_BASE = 0x00FC0000 diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c deleted file mode 100644 index 89af119..0000000 --- a/board/esd/hh405/flash.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include -#include -#include - - -#ifdef CONFIG_VIDEO_SM501 - -#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ - (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) - -#ifdef CONFIG_VIDEO_SM501_8BPP -#error CONFIG_VIDEO_SM501_8BPP not supported. -#endif /* CONFIG_VIDEO_SM501_8BPP */ - -#ifdef CONFIG_VIDEO_SM501_16BPP -#define BPP 16 - -/* - * 800x600 display B084SN03: PCLK = 40MHz - * => 2*PCLK = 80MHz - * 336/4 = 84MHz - * => PCLK = 84MHz - */ -static const SMI_REGS init_regs_800x600 [] = -{ -#if 1 /* test-only */ - {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */ -#else - {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */ -#endif - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* panel control regs... */ - {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ - {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ - {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x02580320)}, /* panel plane br location */ - {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */ - {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */ - {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -/* - * 1024x768 display G150XG02: PCLK = 65MHz - * => 2*PCLK = 130MHz - * 288/2 = 144MHz - * => PCLK = 72MHz - */ -static const SMI_REGS init_regs_1024x768 [] = -{ - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* panel control regs... */ - {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ - {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ - {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x03000400)}, /* panel plane br location */ - {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */ - {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */ - {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -#endif /* CONFIG_VIDEO_SM501_16BPP */ - -#ifdef CONFIG_VIDEO_SM501_32BPP -#define BPP 32 - -/* - * 800x600 display B084SN03: PCLK = 40MHz - * => 2*PCLK = 80MHz - * 336/4 = 84MHz - * => PCLK = 84MHz - */ -static const SMI_REGS init_regs_800x600 [] = -{ -#if 0 /* test-only */ - {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */ -#else - {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */ -#endif - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x221a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* panel control regs... */ - {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ - {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */ - {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x02580320)}, /* panel plane br location */ - {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */ - {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */ - {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -/* - * 1024x768 display G150XG02: PCLK = 65MHz - * => 2*PCLK = 130MHz - * 288/2 = 144MHz - * => PCLK = 72MHz - */ -static const SMI_REGS init_regs_1024x768 [] = -{ - {0x00004, SWAP32(0x00000000)}, - /* clocks for pm1... */ - {0x00048, SWAP32(0x00021807)}, - {0x0004C, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000001)}, - /* clocks for pm0... */ - {0x00040, SWAP32(0x00021807)}, - {0x00044, SWAP32(0x011a0a01)}, - {0x00054, SWAP32(0x00000000)}, - /* panel control regs... */ - {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */ - {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */ - {0x8000C, SWAP32(0x00000000)}, /* panel fb address */ - {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */ - {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */ - {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */ - {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */ - {0x80020, SWAP32(0x03000400)}, /* panel plane br location */ - {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */ - {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */ - {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */ - {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */ - {0x80200, SWAP32(0x00010000)}, /* crt display control */ - {0, 0} -}; - -#endif /* CONFIG_VIDEO_SM501_32BPP */ - -#endif /* CONFIG_VIDEO_SM501 */ - -#if 0 -#define FPGA_DEBUG -#endif - -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -extern void lxt971_no_sleep(void); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - - -/* logo bitmap data - gzip compressed and generated by bin2c */ -unsigned char logo_bmp_320[] = -{ -#include "logo_320_240_4bpp.c" -}; - -unsigned char logo_bmp_320_8bpp[] = -{ -#include "logo_320_240_8bpp.c" -}; - -unsigned char logo_bmp_640[] = -{ -#include "logo_640_480_24bpp.c" -}; - -unsigned char logo_bmp_1024[] = -{ -#include "logo_1024_768_8bpp.c" -}; - - -/* - * include common lcd code (for esd boards) - */ -#include "../common/lcd.c" - -#include "../common/s1d13704_320_240_4bpp.h" -#include "../common/s1d13705_320_240_8bpp.h" -#include "../common/s1d13806_640_480_16bpp.h" -#include "../common/s1d13806_1024_768_8bpp.h" - - -/* - * include common auto-update code (for esd boards) - */ -#include "../common/auto_update.h" - -au_image_t au_image[] = { - {"hh405/preinst.img", 0, -1, AU_SCRIPT}, - {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE}, - {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND}, - {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND}, - {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND}, - {"hh405/postinst.img", 0, 0, AU_SCRIPT}, -}; - -int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); - - -int board_revision(void) -{ - unsigned long osrh_reg; - unsigned long isr1h_reg; - unsigned long tcr_reg; - unsigned long value; - - /* - * Get version of HH405 board from GPIO's - */ - - /* - * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO) - */ - osrh_reg = in32(GPIO0_OSRH); - isr1h_reg = in32(GPIO0_ISR1H); - tcr_reg = in32(GPIO0_TCR); - out32(GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */ - out32(GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */ - out32(GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */ - - udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x80400000; /* get config bits */ - - /* - * Restore GPIO settings - */ - out32(GPIO0_OSRH, osrh_reg); /* output select */ - out32(GPIO0_ISR1H, isr1h_reg); /* input select */ - out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ - - if (value & 0x80000000) { - /* Revision 1.0 or 1.1 detected */ - return 0x0101; - } else { - if (value & 0x00400000) { - /* unused */ - return 0x0103; - } else { - /* Revision >= 2.0 detected */ - /* rev. 2.x uses four SM501 GPIOs for revision coding */ - return 0x0200; - } - } -} - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, CFG_UIC0_POLARITY);/* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ - - return 0; -} - - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile unsigned short *fpga_ctrl = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - volatile unsigned short *lcd_contrast = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4); - volatile unsigned short *lcd_backlight = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6); - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - char *str; - unsigned long contrast0 = 0xffffffff; - - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_INIT pin - */ - out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */ - udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */ - udelay(1000); /* wait 1ms */ - - /* - * Write Board revision into FPGA - */ - *fpga_ctrl |= gd->board_type & 0x0003; - if (gd->board_type >= 0x0200) { - *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN; - } - - /* - * Setup and enable EEPROM write protection - */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); - - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* - * Reset touch-screen controller - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST); - udelay(1000); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST); - - /* - * Enable power on PS/2 interface (with reset) - */ - *fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR); - for (i=0;i<500;i++) - udelay(1000); - *fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR); - - /* - * Get contrast value from environment variable - */ - str = getenv("contrast0"); - if (str) { - contrast0 = simple_strtol(str, NULL, 16); - if (contrast0 > 255) { - printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0); - contrast0 = 0; - } - } - - /* - * Init lcd interface and display logo - */ - - str = getenv("bd_type"); - if (strcmp(str, "ppc230") == 0) { - /* - * Switch backlight on - */ - *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL; - *lcd_backlight = 0x0000; - - lcd_setup(1, 0); - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, - regs_13806_1024_768_8bpp, - sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]), - logo_bmp_1024, sizeof(logo_bmp_1024)); - } else if (strcmp(str, "ppc220") == 0) { - /* - * Switch backlight on - */ - *fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL; - *lcd_backlight = 0x0000; - - lcd_setup(1, 0); - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), - logo_bmp_640, sizeof(logo_bmp_640)); - } else if (strcmp(str, "ppc215") == 0) { - /* - * Set default display contrast voltage - */ - if (contrast0 == 0xffffffff) { - *lcd_contrast = 0x0082; - } else { - *lcd_contrast = contrast0; - } - *lcd_backlight = 0xffff; - /* - * Switch backlight on - */ - *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE; - /* - * Set lcd clock (small epson) - */ - *fpga_ctrl |= LCD_CLK_06250; - udelay(100); /* wait for 100 us */ - - lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, - regs_13705_320_240_8bpp, - sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]), - logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp)); - } else if (strcmp(str, "ppc210") == 0) { - /* - * Set default display contrast voltage - */ - if (contrast0 == 0xffffffff) { - *lcd_contrast = 0x0060; - } else { - *lcd_contrast = contrast0; - } - *lcd_backlight = 0xffff; - /* - * Switch backlight on - */ - *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE; - /* - * Set lcd clock (small epson) - */ - *fpga_ctrl |= LCD_CLK_08330; - - lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); -#ifdef CONFIG_VIDEO_SM501 - } else { - pci_dev_t devbusfn; - - /* - * Is SM501 connected (ppc221/ppc231)? - */ - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - puts("VGA: SM501 with 8 MB "); - if (strcmp(str, "ppc221") == 0) { - printf("(800*600, %dbpp)\n", BPP); - } else if (strcmp(str, "ppc231") == 0) { - printf("(1024*768, %dbpp)\n", BPP); - } else { - printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); - return 0; - } - } else { - printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); - return 0; - } -#endif /* CONFIG_VIDEO_SM501 */ - } - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming HH405"); - } else { - puts(str); - } - - if (getenv_r("bd_type", str, sizeof(str)) != -1) { - printf(" (%s", str); - } else { - puts(" (Missing bd_type!"); - } - - gd->board_type = board_revision(); - printf(", Rev %ld.%ld)\n", - (gd->board_type >> 8) & 0xff, - gd->board_type & 0xff); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} - - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; - } -} -#endif /* CONFIG_IDE_RESET */ - - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - -#if defined(CFG_EEPROM_WREN) -/* Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) -{ - if (CFG_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); - break; - } - } - return state; -} - -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", - NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ - - -#ifdef CONFIG_VIDEO_SM501 -#ifdef CONFIG_CONSOLE_EXTRA_INFO -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str (int line_number, char *info) -{ - DECLARE_GLOBAL_DATA_PTR; - - char str[64]; - char str2[64]; - int i = getenv_r("serial#", str2, sizeof(str)); - - if (line_number == 1) { - sprintf(str, " Board: "); - - if (i == -1) { - strcat(str, "### No HW ID - assuming HH405"); - } else { - strcat(str, str2); - } - - if (getenv_r("bd_type", str2, sizeof(str2)) != -1) { - strcat(str, " ("); - strcat(str, str2); - } else { - strcat(str, " (Missing bd_type!"); - } - - sprintf(str2, ", Rev %ld.%ld)", - (gd->board_type >> 8) & 0xff, gd->board_type & 0xff); - strcat(str, str2); - strcpy(info, str); - } else { - info [0] = '\0'; - } -} -#endif /* CONFIG_CONSOLE_EXTRA_INFO */ - -/* - * Returns SM501 register base address. First thing called in the driver. - */ -unsigned int board_video_init (void) -{ - pci_dev_t devbusfn; - u32 addr; - - /* - * Is SM501 connected (ppc221/ppc231)? - */ - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr); - return (addr & 0xfffffffe); - } - - return 0; -} - -/* - * Returns SM501 framebuffer address - */ -unsigned int board_video_get_fb (void) -{ - pci_dev_t devbusfn; - u32 addr; - - /* - * Is SM501 connected (ppc221/ppc231)? - */ - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr); - return (addr & 0xfffffffe); - } - - return 0; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen (unsigned int base) -{ -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs (void) -{ - char *str; - - str = getenv("bd_type"); - if (strcmp(str, "ppc221") == 0) { - return init_regs_800x600; - } else { - return init_regs_1024x768; - } -} - -int board_get_width (void) -{ - char *str; - - str = getenv("bd_type"); - if (strcmp(str, "ppc221") == 0) { - return 800; - } else { - return 1024; - } -} - -int board_get_height (void) -{ - char *str; - - str = getenv("bd_type"); - if (strcmp(str, "ppc221") == 0) { - return 600; - } else { - return 768; - } -} - -#endif /* CONFIG_VIDEO_SM501 */ diff --git a/board/esd/hh405/logo_1024_768_8bpp.c b/board/esd/hh405/logo_1024_768_8bpp.c deleted file mode 100644 index 2195547..0000000 --- a/board/esd/hh405/logo_1024_768_8bpp.c +++ /dev/null @@ -1,2544 +0,0 @@ - 0x1f,0x8b,0x08,0x08,0x20,0xb5,0x06,0x40,0x00,0x03,0x48,0x6f,0x6c,0x7a,0x2d,0x48, - 0x65,0x72,0x5f,0x64,0x74,0x5f,0x33,0x43,0x5f,0x31,0x30,0x32,0x34,0x78,0x37,0x36, - 0x38,0x5f,0x32,0x35,0x36,0x2e,0x62,0x6d,0x70,0x00,0xec,0xbd,0x0b,0x74,0x23,0xd7, - 0x79,0xa0,0x59,0x14,0x0d,0x1d,0x71,0xb6,0xc9,0x43,0x37,0xe4,0xe4,0xa8,0xa2,0x0c, - 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0x00, diff --git a/board/esd/hh405/u-boot.lds b/board/esd/hh405/u-boot.lds deleted file mode 100644 index f7a20d1..0000000 --- a/board/esd/hh405/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile deleted file mode 100644 index a60495a..0000000 --- a/board/esd/hub405/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/hub405/config.mk b/board/esd/hub405/config.mk deleted file mode 100644 index a6d31aa..0000000 --- a/board/esd/hub405/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd HUB405 boards -# - -TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c deleted file mode 100644 index 89af119..0000000 --- a/board/esd/hub405/flash.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include - - -extern void lxt971_no_sleep(void); - - -int board_revision(void) -{ - unsigned long osrl_reg; - unsigned long isr1l_reg; - unsigned long tcr_reg; - unsigned long value; - - /* - * Get version of HUB405 board from GPIO's - */ - - /* - * Setup GPIO pin(s) (IRQ6/GPIO23) - */ - osrl_reg = in32(GPIO0_OSRH); - isr1l_reg = in32(GPIO0_ISR1H); - tcr_reg = in32(GPIO0_TCR); - out32(GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */ - out32(GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */ - out32(GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */ - - udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00000100; /* get config bits */ - - /* - * Restore GPIO settings - */ - out32(GPIO0_OSRH, osrl_reg); /* output select */ - out32(GPIO0_ISR1H, isr1l_reg); /* input select */ - out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ - - if (value & 0x00000100) { - /* Revision 1.1 or 1.2 detected */ - return 1; - } - - /* Revision 1.0 */ - return 0; -} - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ - - return 0; -} - - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); - volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4); - volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4); - volatile unsigned char *led_reg = (unsigned char *)((ulong)DUART0_BA + 0x20); - unsigned long val; - int delay, flashcnt; - char *str; - char hw_rev[4]; - - /* - * Enable interrupts in exar duart mcr[3] - */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; - *duart2_mcr = 0x08; - *duart3_mcr = 0x08; - - /* - * Set RS232/RS422 control (RS232 = high on GPIO) - */ - val = in32(GPIO0_OR); - val &= ~(CFG_UART2_RS232 | CFG_UART3_RS232 | CFG_UART4_RS232 | CFG_UART5_RS232); - - str = getenv("phys0"); - if (!str || (str && (str[0] == '0'))) - val |= CFG_UART2_RS232; - - str = getenv("phys1"); - if (!str || (str && (str[0] == '0'))) - val |= CFG_UART3_RS232; - - str = getenv("phys2"); - if (!str || (str && (str[0] == '0'))) - val |= CFG_UART4_RS232; - - str = getenv("phys3"); - if (!str || (str && (str[0] == '0'))) - val |= CFG_UART5_RS232; - - out32(GPIO0_OR, val); - - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* - * check board type and setup AP power - */ - str = getenv("bd_type"); /* this is only set on non prototype hardware */ - if (str != NULL) { - if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) { - unsigned char led_reg_default = 0; - str = getenv("ap_pwr"); - if (!str || (str && (str[0] == '1'))) - led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */ - - /* - * Flash LEDs - */ - for (flashcnt = 0; flashcnt < 3; flashcnt++) { - *led_reg = led_reg_default; /* LED_A..D off */ - for (delay = 0; delay < 100; delay++) - udelay(1000); - *led_reg = led_reg_default | 0xf0; /* LED_A..D on */ - for (delay = 0; delay < 50; delay++) - udelay(1000); - } - *led_reg = led_reg_default; - } - } - - /* - * Reset external DUARTs - */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ - udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ - udelay(1000); /* wait 1ms */ - - /* - * Store hardware revision in environment for further processing - */ - sprintf(hw_rev, "1.%ld", gd->board_type); - setenv("hw_rev", hw_rev); - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming HUB405"); - } else { - puts(str); - } - - if (getenv_r("bd_type", str, sizeof(str)) != -1) { - printf(" (%s", str); - } else { - puts(" (Missing bd_type!"); - } - - gd->board_type = board_revision(); - printf(", Rev 1.%ld)\n", gd->board_type); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} - - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esd/hub405/u-boot.lds b/board/esd/hub405/u-boot.lds deleted file mode 100644 index 98338e9..0000000 --- a/board/esd/hub405/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile deleted file mode 100644 index b3039c6..0000000 --- a/board/esd/ocrtc/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o cmd_ocrtc.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c deleted file mode 100644 index ffbb4ad..0000000 --- a/board/esd/ocrtc/cmd_ocrtc.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include <405gp_pci.h> - - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -/* - * Set device number on pci board - */ -int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int idx = 1; /* start at 1 (skip device 0) */ - pci_dev_t bdf = 0; - u32 addr; - - while (bdf >= 0) { - if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) { - break; - } - printf("Found device nr %d at %x!\n", idx-1, bdf); - pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr); - addr &= ~0xf; - *(u32 *)addr = (bdf & 0x0000f800) >> 11; - printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr); - } - - return 0; -} -U_BOOT_CMD( - setdevice, 1, 1, do_setdevice, - "setdevice - Set device number on pci adapter boards\n", - NULL -); - - -/* - * Get device number on pci board - */ -int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - u32 device; - char str[32]; - - device = *(u32 *)0x0; - device = 0x16 - device; /* calculate vxworks bp slot id */ - sprintf(str, "%d", device); - setenv("slot", str); - printf("Variabel slot set to %x\n", device); - - return 0; -} -U_BOOT_CMD( - getdevice, 1, 1, do_getdevice, - "getdevice - Get device number and set slot env variable\n", - NULL -); - -#endif diff --git a/board/esd/ocrtc/config.mk b/board/esd/ocrtc/config.mk deleted file mode 100644 index f123319..0000000 --- a/board/esd/ocrtc/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0xFFFD0000 diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c deleted file mode 100644 index c3d8bec..0000000 --- a/board/esd/ocrtc/flash.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - base_b0 = FLASH_BASE0_PRELIM; - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - base_b1 = FLASH_BASE1_PRELIM; - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); - base_b1 = -size_b1; - switch (size_b1) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); - base_b0 = base_b1 - size_b0; - switch (size_b1) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ - } - - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b1 + size_b1 - monitor_flash_len, - base_b1 + size_b1 - 1, &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect (FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c deleted file mode 100644 index 261b8a5..0000000 --- a/board/esd/ocrtc/ocrtc.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "ocrtc.h" -#include -#include -#include - - -extern void lxt971_no_sleep(void); - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: clear EBTC -> high-Z ebc signals between - * transfers, set device-paced timeout to 256 cycles - */ - mtebc (epcr, 0x20400000); - - return 0; -} - - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (i == -1) { -#ifdef CONFIG_OCRTC - puts ("### No HW ID - assuming OCRTC"); -#endif -#ifdef CONFIG_ORSG - puts ("### No HW ID - assuming ORSG"); -#endif - } else { - puts (str); - } - - putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return (0); -} - - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr (memcfga, mem_mb0cf); - val = mfdcr (memcfgd); - -#if 0 - printf ("\nmb0cf=%x\n", val); /* test-only */ - printf ("strap=%x\n", mfdcr (strap)); /* test-only */ -#endif - - return (4 * 1024 * 1024 << ((val & 0x000e0000) >> 17)); -} - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} diff --git a/board/esd/ocrtc/ocrtc.h b/board/esd/ocrtc/ocrtc.h deleted file mode 100644 index b50d521..0000000 --- a/board/esd/ocrtc/ocrtc.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/ocrtc/u-boot.lds b/board/esd/ocrtc/u-boot.lds deleted file mode 100644 index 476b4a0..0000000 --- a/board/esd/ocrtc/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile deleted file mode 100644 index 6db564f..0000000 --- a/board/esd/pci405/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o cmd_pci405.o -SOBJS = writeibm.o - -$(LIB): $(OBJS) $(SOBJS) -# $(AR) crv $@ $(OBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c deleted file mode 100644 index 0315c3d..0000000 --- a/board/esd/pci405/cmd_pci405.c +++ /dev/null @@ -1,985 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include <405gp_pci.h> -#include - -#include "pci405.h" - - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -extern int do_bootm (cmd_tbl_t *, int, int, char *[]); -extern int do_bootvx (cmd_tbl_t *, int, int, char *[]); -unsigned long get_dcr(unsigned short); - - -/* - * Command loadpci: wait for signal from host and boot image. - */ -int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int *ptr = 0; - int count = 0; - int count2 = 0; - int status; - int i; - char addr[16]; - char str[] = "\\|/-"; - char *local_args[2]; - - /* - * Mark sync address - */ - ptr = 0; - *ptr = 0xffffffff; - puts("\nWaiting for image from pci host -"); - - /* - * Wait for host to write the start address - */ - while (*ptr == 0xffffffff) { - count++; - if (!(count % 100)) { - count2++; - putc(0x08); /* backspace */ - putc(str[count2 % 4]); - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(1000); - } - - if (*ptr == PCI_RECONFIG_MAGIC) { - /* - * Save own pci configuration in PRAM - */ - memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_read_config_dword(PCIDEVID_405GP, i, ptr++); - } - ptr = (unsigned int *)PCI_REGS_ADDR; - *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4); - - printf("\nStoring PCI Configuration Regs...\n"); - } else { - sprintf(addr, "%08x", *ptr); - -#if 0 - /* - * Boot image - */ - if (*ptr & 0x00000001) { - /* - * Boot VxWorks image via bootvx - */ - addr[strlen(addr)-1] = '0'; - printf("\nBooting VxWorks-Image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - - local_args[0] = argv[0]; - local_args[1] = NULL; - status = do_bootvx (cmdtp, 0, 1, local_args); - } else { - /* - * Boot image via bootm (normally Linux) - */ - printf("\nBooting Image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - - local_args[0] = argv[0]; - local_args[1] = NULL; - status = do_bootm (cmdtp, 0, 1, local_args); - } -#else - /* - * Boot image via bootm - */ - printf("\nBooting Image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - - local_args[0] = argv[0]; - local_args[1] = NULL; - status = do_bootm (cmdtp, 0, 1, local_args); -#endif - } - - return 0; -} -U_BOOT_CMD( - loadpci, 1, 1, do_loadpci, - "loadpci - Wait for pci-image and boot it\n", - NULL -); - -#endif - -#if 1 /* test-only */ -int do_getpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int val; - int i; - - printf("\nPCI Configuration Regs for PPC405GP:"); - for (i=0; i<0x64; i+=4) { - pci_read_config_dword(PCIDEVID_405GP, i, &val); - if (!(i % 0x10)) { - printf("\n%02x: ", i); - } - printf("%08x ", val); - } - printf("\n"); - - return 0; -} -U_BOOT_CMD( - getpci, 1, 1, do_getpci, - "getpci - Print own pci configuration registers\n", - NULL -); - -int do_setpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int val; - - addr = simple_strtol (argv[1], NULL, 16); - val = simple_strtol (argv[2], NULL, 16); - - printf("\nWriting %08x to PCI reg %08x.\n", val, addr); - pci_write_config_dword(PCIDEVID_405GP, addr, val); - - return 0; -} -U_BOOT_CMD( - setpci, 3, 1, do_setpci, - "setpci - Set one pci configuration lword\n", - " \n" - " - Write pci configuration lword to .\n" -); - -int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int i; - - printf("\nDevice Configuration Registers (DCR's) for PPC405GP:"); - for (i=0; i<=0x1e0; i++) { - if (!(i % 0x8)) { - printf("\n%04x ", i); - } - printf("%08lx ", get_dcr(i)); - } - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpdcr, 1, 1, do_dumpdcr, - "dumpdcr - Dump all DCR registers\n", - NULL -); - - -int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:"); - printf("\n%04x %08x ", 947, mfspr(947)); - printf("\n%04x %08x ", 9, mfspr(9)); - printf("\n%04x %08x ", 1014, mfspr(1014)); - printf("\n%04x %08x ", 1015, mfspr(1015)); - printf("\n%04x %08x ", 1010, mfspr(1010)); - printf("\n%04x %08x ", 957, mfspr(957)); - printf("\n%04x %08x ", 1008, mfspr(1008)); - printf("\n%04x %08x ", 1018, mfspr(1018)); - printf("\n%04x %08x ", 954, mfspr(954)); - printf("\n%04x %08x ", 950, mfspr(950)); - printf("\n%04x %08x ", 951, mfspr(951)); - printf("\n%04x %08x ", 981, mfspr(981)); - printf("\n%04x %08x ", 980, mfspr(980)); - printf("\n%04x %08x ", 982, mfspr(982)); - printf("\n%04x %08x ", 1012, mfspr(1012)); - printf("\n%04x %08x ", 1013, mfspr(1013)); - printf("\n%04x %08x ", 948, mfspr(948)); - printf("\n%04x %08x ", 949, mfspr(949)); - printf("\n%04x %08x ", 1019, mfspr(1019)); - printf("\n%04x %08x ", 979, mfspr(979)); - printf("\n%04x %08x ", 8, mfspr(8)); - printf("\n%04x %08x ", 945, mfspr(945)); - printf("\n%04x %08x ", 987, mfspr(987)); - printf("\n%04x %08x ", 287, mfspr(287)); - printf("\n%04x %08x ", 953, mfspr(953)); - printf("\n%04x %08x ", 955, mfspr(955)); - printf("\n%04x %08x ", 272, mfspr(272)); - printf("\n%04x %08x ", 273, mfspr(273)); - printf("\n%04x %08x ", 274, mfspr(274)); - printf("\n%04x %08x ", 275, mfspr(275)); - printf("\n%04x %08x ", 260, mfspr(260)); - printf("\n%04x %08x ", 276, mfspr(276)); - printf("\n%04x %08x ", 261, mfspr(261)); - printf("\n%04x %08x ", 277, mfspr(277)); - printf("\n%04x %08x ", 262, mfspr(262)); - printf("\n%04x %08x ", 278, mfspr(278)); - printf("\n%04x %08x ", 263, mfspr(263)); - printf("\n%04x %08x ", 279, mfspr(279)); - printf("\n%04x %08x ", 26, mfspr(26)); - printf("\n%04x %08x ", 27, mfspr(27)); - printf("\n%04x %08x ", 990, mfspr(990)); - printf("\n%04x %08x ", 991, mfspr(991)); - printf("\n%04x %08x ", 956, mfspr(956)); - printf("\n%04x %08x ", 284, mfspr(284)); - printf("\n%04x %08x ", 285, mfspr(285)); - printf("\n%04x %08x ", 986, mfspr(986)); - printf("\n%04x %08x ", 984, mfspr(984)); - printf("\n%04x %08x ", 256, mfspr(256)); - printf("\n%04x %08x ", 1, mfspr(1)); - printf("\n%04x %08x ", 944, mfspr(944)); - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpspr, 1, 1, do_dumpspr, - "dumpspr - Dump all SPR registers\n", - NULL -); - - -#define PCI0_BRDGOPT1 0x4a -#define plb0_acr 0x87 - -int do_getplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned short val; - - printf("PLB0_ACR=%08lx\n", get_dcr(0x87)); - pci_read_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, &val); - printf("PCI0_BRDGOPT1=%04x\n", val); - printf("CCR0=%08x\n", mfspr(ccr0)); - - return 0; -} -U_BOOT_CMD( - getplb, 1, 1, do_getplb, - "getplb - Dump all plb arbiter registers\n", - NULL -); - -int do_setplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int my_acr; - unsigned int my_brdgopt1; - unsigned int my_ccr0; - - my_acr = simple_strtol (argv[1], NULL, 16); - my_brdgopt1 = simple_strtol (argv[2], NULL, 16); - my_ccr0 = simple_strtol (argv[3], NULL, 16); - - mtdcr(plb0_acr, my_acr); - pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, my_brdgopt1); - mtspr(ccr0, my_ccr0); - - return 0; -} -U_BOOT_CMD( - setplb, 4, 1, do_setplb, - "setplb - Set all plb arbiter registers\n", - "PLB0_ACR PCI0_BRDGOPT1 CCR0\n" - " - Set all plb arbiter registers\n" -); - - -/*********************************************************************** - * - * The following code is only for test purposes!!!! - * Please ignore this ugly stuff!!!!!!!!!!!!!!!!!!! - * - ***********************************************************************/ - -#define PCI_ADDR 0xc0000000 - -int do_writepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - unsigned int countmax; - int i; - int max; - volatile unsigned long *ptr; - volatile unsigned long val; - int loopcount = 0; - int test_pci_read = 0; - int test_pci_cfg_write = 0; - int test_sync = 0; - int test_pci_pre_read = 0; - - addr = simple_strtol (argv[1], NULL, 16); - size = simple_strtol (argv[2], NULL, 16); - countmax = simple_strtol (argv[3], NULL, 16); - if (countmax == 0) - countmax = 1000; - - do_getplb(NULL, 0, 0, NULL); - -#if 0 - out32r(PMM0LA, 0); - out32r(PMM0PCILA, 0); - out32r(PMM0PCIHA, 0); - out32r(PMM0MA, 0); - out32r(PMM1LA, PCI_ADDR); - out32r(PMM1PCILA, addr & 0xff000000); - out32r(PMM1PCIHA, 0x00000000); - out32r(PMM1MA, 0xff000001); -#endif - - printf("PMM1LA =%08lx\n", in32r(PMM1LA)); - printf("PMM1MA =%08lx\n", in32r(PMM1MA)); - printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); - printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); - - addr = PCI_ADDR | (addr & 0x00ffffff); - printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); - - max = size >> 2; - - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - val = *(ulong *)0x00000000; - if (val & 0x00000008) { - test_pci_pre_read = 1; - printf("Running test with pre pci-memory-read access!\n"); - } - if (val & 0x00000004) { - test_sync = 1; - printf("Running test with sync instruction!\n"); - } - if (val & 0x00000001) { - test_pci_read = 1; - printf("Running test with pci-memory-read access!\n"); - } - if (val & 0x00000002) { - test_pci_cfg_write = 1; - printf("Running test with pci-config-write access!\n"); - } - - while (1) { - - if (test_pci_pre_read) { - /* - * Read one value back - */ - ptr = (volatile unsigned long *)addr; - val = *ptr; - } - - /* - * Write some values to host via pci busmastering - */ - ptr = (volatile unsigned long *)addr; - for (i=0; i countmax) { - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - putc('.'); - - loopcount = 0; - } - } - - return 0; -} -U_BOOT_CMD( - writepci, 4, 1, do_writepci, - "writepci - Write some data to pcibus\n", - " \n" - " - Write some data to pcibus.\n" -); - -#define PCI_CFGADDR 0xeec00000 -#define PCI_CFGDATA 0xeec00004 - -int ibmPciConfigWrite -( - int offset, /* offset into the configuration space */ - int width, /* data width */ - unsigned int data /* data to be written */ - ) -{ - /* - * Write config register address to the PCI config address register - * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation) - */ - out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC)); - -#if 0 /* test-only */ - ppcSync(); -#endif - - /* - * Write value to be written to the PCI config data register - */ - switch ( width ) { - case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF)); - break; - case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF)); - break; - case 4: out32r(PCI_CFGDATA | (offset & 0x3), data); - break; - } - - return (0); -} - -int do_writepci2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - unsigned int countmax; - int max; - volatile unsigned long *ptr; - volatile unsigned long val; - int loopcount = 0; - - addr = simple_strtol (argv[1], NULL, 16); - size = simple_strtol (argv[2], NULL, 16); - countmax = simple_strtol (argv[3], NULL, 16); - if (countmax == 0) - countmax = 1000; - - do_getplb(NULL, 0, 0, NULL); - -#if 0 - out32r(PMM0LA, 0); - out32r(PMM0PCILA, 0); - out32r(PMM0PCIHA, 0); - out32r(PMM0MA, 0); - out32r(PMM1LA, PCI_ADDR); - out32r(PMM1PCILA, addr & 0xff000000); - out32r(PMM1PCIHA, 0x00000000); - out32r(PMM1MA, 0xff000001); -#endif - - printf("PMM1LA =%08lx\n", in32r(PMM1LA)); - printf("PMM1MA =%08lx\n", in32r(PMM1MA)); - printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); - printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); - - addr = PCI_ADDR | (addr & 0x00ffffff); - printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); - - max = size >> 2; - - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - while (1) { - - /* - * Write one values to host via pci busmastering - */ - ptr = (volatile unsigned long *)addr; - *ptr = 0x01234567; - - /* - * Read one value back - */ - ptr = (volatile unsigned long *)addr; - val = *ptr; - - /* - * One pci config write - */ -/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */ -/* ibmPciConfigWrite(0x44, 1, 0x00); */ - ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */ - - if (loopcount++ > countmax) { - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - putc('.'); - - loopcount = 0; - } - } - - return 0; -} -U_BOOT_CMD( - writepci2, 4, 1, do_writepci2, - "writepci2- Write some data to pcibus\n", - " \n" - " - Write some data to pcibus.\n" -); - -int do_writepci22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - unsigned int countmax = 0; - volatile unsigned long *ptr; - volatile unsigned long val; - - addr = simple_strtol (argv[1], NULL, 16); - size = simple_strtol (argv[2], NULL, 16); - - addr = PCI_ADDR | (addr & 0x00ffffff); - printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - while (1) { - - /* - * Write one values to host via pci busmastering - */ - ptr = (volatile unsigned long *)addr; - *ptr = 0x01234567; - - /* - * Read one value back - */ - ptr = (volatile unsigned long *)addr; - val = *ptr; - - /* - * One pci config write - */ - ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */ - } - - return 0; -} -U_BOOT_CMD( - writepci22, 4, 1, do_writepci22, - "writepci22- Write some data to pcibus\n", - " \n" - " - Write some data to pcibus.\n" -); - -int ibmPciConfigWrite3 -( - int offset, /* offset into the configuration space */ - int width, /* data width */ - unsigned int data /* data to be written */ - ) -{ - /* - * Write config register address to the PCI config address register - * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation) - */ - out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC)); - -#if 1 /* test-only */ - ppcSync(); -#endif - - /* - * Write value to be written to the PCI config data register - */ - switch ( width ) { - case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF)); - break; - case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF)); - break; - case 4: out32r(PCI_CFGDATA | (offset & 0x3), data); - break; - } - - return (0); -} - -int do_writepci3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - unsigned int countmax; - int max; - volatile unsigned long *ptr; - volatile unsigned long val; - int loopcount = 0; - - addr = simple_strtol (argv[1], NULL, 16); - size = simple_strtol (argv[2], NULL, 16); - countmax = simple_strtol (argv[3], NULL, 16); - if (countmax == 0) - countmax = 1000; - - do_getplb(NULL, 0, 0, NULL); - -#if 0 - out32r(PMM0LA, 0); - out32r(PMM0PCILA, 0); - out32r(PMM0PCIHA, 0); - out32r(PMM0MA, 0); - out32r(PMM1LA, PCI_ADDR); - out32r(PMM1PCILA, addr & 0xff000000); - out32r(PMM1PCIHA, 0x00000000); - out32r(PMM1MA, 0xff000001); -#endif - - printf("PMM1LA =%08lx\n", in32r(PMM1LA)); - printf("PMM1MA =%08lx\n", in32r(PMM1MA)); - printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); - printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); - - addr = PCI_ADDR | (addr & 0x00ffffff); - printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); - - max = size >> 2; - - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - while (1) { - - /* - * Write one values to host via pci busmastering - */ - ptr = (volatile unsigned long *)addr; - *ptr = 0x01234567; - - /* - * Read one value back - */ - ptr = (volatile unsigned long *)addr; - val = *ptr; - - /* - * One pci config write - */ -/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */ -/* ibmPciConfigWrite(0x44, 1, 0x00); */ - ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */ - - if (loopcount++ > countmax) { - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - putc('.'); - - loopcount = 0; - } - } - - return 0; -} -U_BOOT_CMD( - writepci3, 4, 1, do_writepci3, - "writepci3- Write some data to pcibus\n", - " \n" - " - Write some data to pcibus.\n" -); - - -#define SECTOR_SIZE 32 /* 32 byte cache line */ -#define SECTOR_MASK 0x1F - -void my_flush_dcache(ulong lcl_addr, ulong count) -{ - unsigned int lcl_target; - - /* promote to nearest cache sector */ - lcl_target = (lcl_addr + count + SECTOR_SIZE - 1) & ~SECTOR_MASK; - lcl_addr &= ~SECTOR_MASK; - while (lcl_addr != lcl_target) - { - /* ppcDcbf((void *)lcl_addr);*/ - __asm__("dcbf 0,%0": :"r" (lcl_addr)); - lcl_addr += SECTOR_SIZE; - } - __asm__("sync"); /* Always flush prefetch queue in any case */ -} - -int do_writepci_cache(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - unsigned int countmax; - int i; - volatile unsigned long *ptr; - volatile unsigned long val; - int loopcount = 0; - - addr = simple_strtol (argv[1], NULL, 16); - size = simple_strtol (argv[2], NULL, 16); - countmax = simple_strtol (argv[3], NULL, 16); - if (countmax == 0) - countmax = 1000; - - do_getplb(NULL, 0, 0, NULL); - -#if 0 - out32r(PMM0LA, 0); - out32r(PMM0PCILA, 0); - out32r(PMM0PCIHA, 0); - out32r(PMM0MA, 0); - out32r(PMM1LA, PCI_ADDR); - out32r(PMM1PCILA, addr & 0xff000000); - out32r(PMM1PCIHA, 0x00000000); - out32r(PMM1MA, 0xff000001); -#endif - - printf("PMM1LA =%08lx\n", in32r(PMM1LA)); - printf("PMM1MA =%08lx\n", in32r(PMM1MA)); - printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); - printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); - - addr = PCI_ADDR | (addr & 0x00ffffff); - printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); - - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - i = 0; - - /* - * Set pci region as cachable - */ - ppcSync(); - __asm__ volatile (" addis 4,0,0x0000 "); - __asm__ volatile (" addi 4,4,0x0080 "); - __asm__ volatile (" mtdccr 4 "); - ppcSync(); - - while (1) { - - /* - * Write one values to host via pci busmastering - */ - ptr = (volatile unsigned long *)addr; - printf("A\n"); /* test-only */ - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - printf("B\n"); /* test-only */ - my_flush_dcache(addr, 32); - printf("C\n"); /* test-only */ - - /* - * Read one value back - */ - ptr = (volatile unsigned long *)addr; - val = *ptr; - printf("D\n"); /* test-only */ - - /* - * One pci config write - */ -/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */ -/* ibmPciConfigWrite(0x44, 1, 0x00); */ - ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */ - printf("E\n"); /* test-only */ - - if (loopcount++ > countmax) { - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - putc('.'); - - loopcount = 0; - } - } - - return 0; -} -U_BOOT_CMD( - writepci_cache, 4, 1, do_writepci_cache, - "writepci_cache - Write some data to pcibus\n", - " \n" - " - Write some data to pcibus.\n" -); - -int do_savepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int *ptr; - int i; - - /* - * Save own pci configuration in PRAM - */ - memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_read_config_dword(PCIDEVID_405GP, i, ptr++); - } - ptr = (unsigned int *)PCI_REGS_ADDR; - *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4); - - printf("\nStoring PCI Configuration Regs...\n"); - - return 0; -} -U_BOOT_CMD( - savepci, 4, 1, do_savepci, - "savepci - Save all pci regs\n", - " \n" - " - Write some data to pcibus.\n" -); - -int do_restorepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int *ptr; - int i; - - /* - * Rewrite pci config regs (only after soft-reset with magic set) - */ - ptr = (unsigned int *)PCI_REGS_ADDR; - if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { - puts("Restoring PCI Configurations Regs!\n"); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); - } - } - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} -U_BOOT_CMD( - restorepci, 4, 1, do_restorepci, - "restorepci - Restore all pci regs\n", - " \n" - " - Write some data to pcibus.\n" -); - - -extern void write_without_sync(void); -extern void write_with_sync(void); -extern void write_with_less_sync(void); -extern void write_with_more_sync(void); - -/* - * code from IBM-PPCSUPP - */ -int do_writeibm1(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - write_without_sync(); - - return 0; -} -U_BOOT_CMD( - writeibm1, 4, 1, do_writeibm1, - "writeibm1- Write some data to pcibus (without sync)\n", - " \n" - " - Write some data to pcibus.\n" -); - -int do_writeibm2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - write_with_sync(); - - return 0; -} -U_BOOT_CMD( - writeibm2, 4, 1, do_writeibm2, - "writeibm2- Write some data to pcibus (with sync)\n", - " \n" - " - Write some data to pcibus.\n" -); - -int do_writeibm22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - write_with_less_sync(); - - return 0; -} -U_BOOT_CMD( - writeibm22, 4, 1, do_writeibm22, - "writeibm22- Write some data to pcibus (with less sync)\n", - " \n" - " - Write some data to pcibus.\n" -); - -int do_writeibm3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - write_with_more_sync(); - - return 0; -} -U_BOOT_CMD( - writeibm3, 4, 1, do_writeibm3, - "writeibm3- Write some data to pcibus (with more sync)\n", - " \n" - " - Write some data to pcibus.\n" -); -#endif diff --git a/board/esd/pci405/config.mk b/board/esd/pci405/config.mk deleted file mode 100644 index 83f07fe..0000000 --- a/board/esd/pci405/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0xFFFD0000 diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c deleted file mode 100644 index 3b21781..0000000 --- a/board/esd/pci405/flash.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include -#include -#include <405gp_pci.h> - -#include "pci405.h" - - -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/ -unsigned long fpga_done_state(void); -unsigned long fpga_init_state(void); - -#if 0 -#define FPGA_DEBUG -#endif - -/* predefine these here */ -#define FPGA_DONE_STATE (fpga_done_state()) -#define FPGA_INIT_STATE (fpga_init_state()) - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - -#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_DONE) -#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_DONE_V12) - -#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_INIT) -#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_INIT_V12) - - -int board_revision(void) -{ - unsigned long cntrl0Reg; - unsigned long value; - - /* - * Get version of PCI405 board from GPIO's - */ - - /* - * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200); - udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00100200; /* get config bits */ - - /* - * Restore GPIO settings - */ - mtdcr(cntrl0, cntrl0Reg); - - switch (value) { - case 0x00100200: - /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */ - return 1; - case 0x00000200: - /* CS2==0 && IRQ5==1 -> version 1.2 */ - return 2; - case 0x00000000: - /* CS2==0 && IRQ5==0 -> version 1.3 */ - return 3; -#if 0 /* not yet manufactured ! */ - case 0x00100000: - /* CS2==1 && IRQ5==0 -> version 1.4 */ - return 4; -#endif - default: - /* should not be reached! */ - return 0; - } -} - - -unsigned long fpga_done_state(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - if (gd->board_type < 2) { - return FPGA_DONE_STATE_V11; - } else { - return FPGA_DONE_STATE_V12; - } -} - - -unsigned long fpga_init_state(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - if (gd->board_type < 2) { - return FPGA_INIT_STATE_V11; - } else { - return FPGA_INIT_STATE_V12; - } -} - - -int board_early_init_f (void) -{ - unsigned long cntrl0Reg; - - /* - * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) - */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ - out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ - out32(GPIO0_OR, 0); /* pull prg low */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive - * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive - * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive - * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive - * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * Setup GPIO pins (IRQ4/GPIO21 as GPIO) - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00008000); - - /* - * Setup GPIO pins (CS6+CS7 as GPIO) - */ - mtdcr(cntrl0, cntrl0Reg | 0x00300000); - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us - */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - unsigned int *ptr; - unsigned int *magic; - - /* - * On PCI-405 the environment is saved in eeprom! - * FPGA can be gzip compressed (malloc) and booted this late. - */ - - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Check if magic for pci reconfig is written - */ - magic = (unsigned int *)0x00000004; - if (*magic == PCI_RECONFIG_MAGIC) { - /* - * Rewrite pci config regs (only after soft-reset with magic set) - */ - ptr = (unsigned int *)PCI_REGS_ADDR; - if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { - puts("Restoring PCI Configurations Regs!\n"); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); - } - } - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - *magic = 0; /* clear pci reconfig magic again */ - } - -#if 1 /* test-only */ - /* - * Decrease PLB latency timeout and reduce priority of the PCI bridge master - */ -#define PCI0_BRDGOPT1 0x4a - pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); -/* pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60); */ - -#define plb0_acr 0x87 - /* - * Enable fairness and high bus utilization - */ - mtdcr(plb0_acr, 0x98000000); - -#if 0 /* test-only */ - printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */ -/* mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000); */ - mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000); -#endif -/* printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */ -#endif - - free(dst); - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming PCI405"); - } else { - puts (str); - } - - gd->board_type = board_revision(); - printf(" (Rev 1.%ld", gd->board_type); - - if (gd->board_type >= 2) { - unsigned long cntrl0Reg; - unsigned long value; - - /* - * Setup GPIO pins (Trace/GPIO1 to GPIO) - */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg & ~0x08000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000); - udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x40000000; /* get config bits */ - if (value) { - puts(", 33 MHz PCI"); - } else { - puts(", 66 Mhz PCI"); - } - } - - puts(")\n"); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - -#if 0 /* test-only: all PCI405 version must report 16mb */ - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -#else - return (16*1024*1024); -#endif -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ -int wpeeprom(int wp) -{ - int wp_state = wp; - volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404; - - if (wp == 1) { - *uart1_mcr &= ~0x02; - } else if (wp == 0) { - *uart1_mcr |= 0x02; - } else { - if (*uart1_mcr & 0x02) { - wp_state = 0; - } else { - wp_state = 1; - } - } - return wp_state; -} - -int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int wp = -1; - if (argc >= 2) { - if (argv[1][0] == '1') { - wp = 1; - } else if (argv[1][0] == '0') { - wp = 0; - } - } - - wp = wpeeprom(wp); - printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED"); - return 0; -} - -U_BOOT_CMD( - wpeeprom, 2, 1, do_wpeeprom, - "wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n", - "wpeeprom\n" - " - check I2C EEPROM write protection state\n" - "wpeeprom 1\n" - " - enable I2C EEPROM write protection\n" - "wpeeprom 0\n" - " - disable I2C EEPROM write protection\n" - ); diff --git a/board/esd/pci405/pci405.h b/board/esd/pci405/pci405.h deleted file mode 100644 index c11a20f..0000000 --- a/board/esd/pci405/pci405.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PCI405_H_ -#define _PCI405_H_ - -#define PCI_REGS_LEN 0x100 -#define PCI_REGS_ADDR ((unsigned long)0x01000000 - PCI_REGS_LEN) - -#define PCI_RECONFIG_MAGIC 0x07081967 - -#endif /* _PCI405_H_ */ diff --git a/board/esd/pci405/u-boot.lds b/board/esd/pci405/u-boot.lds deleted file mode 100644 index f7a20d1..0000000 --- a/board/esd/pci405/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S deleted file mode 100644 index 9f5c35b..0000000 --- a/board/esd/pci405/writeibm.S +++ /dev/null @@ -1,223 +0,0 @@ -/*------------------------------------------------------------------------------+ */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ - -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - NVRAM/RTC */ -/* Bank 2 - Keyboard/Mouse controller */ -/* Bank 3 - IR controller */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - FPGA registers */ -/*----------------------------------------------------------------------------- */ -#include - -#include -#include - -#include -#include - - - .globl write_without_sync -write_without_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start1: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - - b start1 - - blr /* never reached !!!! */ - - .globl write_with_sync -write_with_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start2: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - sync - - b start2 - - blr /* never reached !!!! */ - - .globl write_with_less_sync -write_with_less_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start2b: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id */ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 -/* sync */ - - b start2b - - blr /* never reached !!!! */ - - .globl write_with_more_sync -write_with_more_sync: - /* - * Write one values to host via pci busmastering - * ptr = 0xc0000000 -> 0x01000000 (PCI) - * *ptr = 0x01234567; - */ - addi r31,0,0 - lis r31,0xc000 - -start3: - lis r0,0x0123 - ori r0,r0,0x4567 - stw r0,0(r31) - sync - - /* - * Read one value back - * ptr = (volatile unsigned long *)addr; - * val = *ptr; - */ - - lwz r0,0(r31) - sync - - /* - * One pci config write - * ibmPciConfigWrite(0x2e, 2, 0x1234); - */ - /* subsystem id (PCIC0_SBSYSVID)*/ - - li r4,0x002C - oris r4,r4,0x8000 - lis r3,0xEEC0 - stwbrx r4,0,r3 - sync - - li r5,0x1234 - ori r3,r3,0x4 - stwbrx r5,0,r3 - sync - - b start3 - - blr /* never reached !!!! */ diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile deleted file mode 100644 index 603bbe2..0000000 --- a/board/esd/pf5200/Makefile +++ /dev/null @@ -1,53 +0,0 @@ - -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -# Objects for Xilinx JTAG programming (CPLD) -# CPLD = ../common/xilinx_jtag/lenval.o \ -# ../common/xilinx_jtag/micro.o \ -# ../common/xilinx_jtag/ports.o - -# OBJS = $(BOARD).o flash.o $(CPLD) -OBJS = $(BOARD).o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/esd/pf5200/config.mk b/board/esd/pf5200/config.mk deleted file mode 100644 index 07b5de1..0000000 --- a/board/esd/pf5200/config.mk +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# IceCube board: -# -# Valid values for TEXT_BASE are: -# -# 0xFFF00000 boot high (standard configuration) -# 0xFF000000 boot low for 16 MiB boards -# 0xFF800000 boot low for 8 MiB boards -# 0x00100000 boot from RAM (for testing only) -# - -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -## Standard: boot high -TEXT_BASE = 0xFFF00000 -## For testing: boot from RAM -# TEXT_BASE = 0x00100000 -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c deleted file mode 100644 index 53afbc0..0000000 --- a/board/esd/pf5200/flash.c +++ /dev/null @@ -1,461 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0x00FF - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x0aaa -#define FLASH_ID1 0x00 -#define FLASH_ID2 0x01 -#define FLASH_ID3 0x0E -#define FLASH_ID4 0x0F - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV * addr, flash_info_t * info); -static void flash_reset(flash_info_t * info); -static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init(void) -{ - unsigned long size = 0; - int i = 0; - extern void flash_preinit(void); - extern void flash_afterinit(uint, ulong, ulong); - - ulong flashbase = CFG_FLASH_BASE; - - flash_preinit(); - - /* There is only ONE FLASH device */ - memset(&flash_info[i], 0, sizeof(flash_info_t)); - flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]); - size += flash_info[i].size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - flash_afterinit(i, flash_info[i].start[0], flash_info[i].size); - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t * info) { - FPWV *base = (FPWV *) (info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) { - *base = (FPW) 0x00F000F0; /* AMD Read Mode */ - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) { - int i; - flash_info_t *info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - info = &flash_info[i]; - if ((info->size) && (info->start[0] <= base) - && (base <= info->start[0] + info->size - 1)) { - break; - } - } - return (i == CFG_MAX_FLASH_BANKS ? 0 : info); -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info(flash_info_t * info) { - int i; - char *fmt; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMLV256U: - fmt = "29LV256M (256 Mbit)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf(fmt); - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, - info->sector_count); - printf(" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - ulong size; - int erased; - ulong *flash = (unsigned long *)info->start[i]; - - if ((i % 5) == 0) { - printf("\n "); - } - - /* - * Check if whole sector is erased - */ - size = - (i != - (info->sector_count - 1)) ? (info->start[i + 1] - - info->start[i]) >> 2 : (info-> - start - [0] + - info-> - size - - info-> - start - [i]) - >> 2; - - for (flash = (unsigned long *)info->start[i], erased = 1; - (flash != (unsigned long *)info->start[i] + size) - && erased; flash++) { - erased = *flash == ~0x0UL; - } - printf(" %08lX %s %s", info->start[i], erased ? "E" : " ", - info->protect[i] ? "(RO)" : " "); - } - - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size(FPWV * addr, flash_info_t * info) { - int i; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. */ - /* This works for any bus width and any FLASH device width. */ - udelay(100); - switch (addr[FLASH_ID1] & 0x00ff) { - case (uchar) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) { - switch ((FPW) addr[FLASH_ID2]) { - case (FPW) AMD_ID_MIRROR: - /* MIRROR BIT FLASH, read more ID bytes */ - if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2 - && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) { - /* attention: only the first 16 MB will be used in u-boot */ - info->flash_id += FLASH_AMLV256U; - info->sector_count = 512; - info->size = 0x02000000; - for (i = 0; i < info->sector_count; i++) { - info->start[i] = - (ulong) addr + 0x10000 * i; - } - break; - } - /* fall thru to here ! */ - default: - printf("unknown AMD device=%x %x %x", - (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3], - (FPW) addr[FLASH_ID4]); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0x800000; - break; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - } - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) { - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMLV256U: - break; - case FLASH_UNKNOWN: - default: - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { - if (info->protect[sect] != 0) { /* protected, skip it */ - continue; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *) (info->start[sect]); - if (intel) { - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - } else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *) (info->start[0]); - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ - *addr = (FPW) 0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. */ - /* Let's wait 1 ms. */ - udelay(1000); - - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - if (intel) { - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - } - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { - /* every second */ - putc('.'); - last = get_timer(0); - } - } - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { - /* every second */ - putc('.'); - last = get_timer(0); - } - flash_reset(info); /* reset to read mode */ - } - printf(" done\n"); - return (rcode); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *) addr, data); - break; - default: - /* unknown flash type, error! */ - printf("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) { - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *) (info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - start = get_timer(0); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00F000F0; /* reset bank */ - res = 1; - } - } - return (res); -} diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h deleted file mode 100644 index 22d0a55..0000000 --- a/board/esd/pf5200/mt46v16m16-75.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 1 /* is DDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x705f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c deleted file mode 100644 index 2b47012..0000000 --- a/board/esd/pf5200/pf5200.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * pf5200.c - main board support/init for the esd pf5200. - */ - -#include -#include -#include -#include - -#include "mt46v16m16-75.h" - -void init_power_switch(void); - -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register: extended mode */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = - SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. - */ - -long int initdram(int board_type) -{ - ulong dramsize = 0; - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - - /* set tap delay */ - *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); - - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = - 0x13 + __builtin_ffs(dramsize >> 20) - 1; - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ - } else { -#if 0 - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ -#else - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = - 0x13 + __builtin_ffs(0x08000000 >> 20) - 1; - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */ -#endif - } - -#if 0 - /* find RAM size using SDRAM CS1 only */ - sdram_start(0); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); - sdram_start(1); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); - sdram_start(0); -#endif - /* set SDRAM CS1 size according to the amount of RAM found */ - - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - - init_power_switch(); - return (dramsize); -} - -int checkboard(void) -{ - puts("Board: esd ParaFinder (pf5200)\n"); - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -void flash_afterinit(ulong size) -{ - if (size == 0x02000000) { - /* adjust mapping */ - *(vu_long *) MPC5XXX_BOOTCS_START = - *(vu_long *) MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); - *(vu_long *) MPC5XXX_BOOTCS_STOP = - *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); - } -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void - ) { - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) - -#define GPIO_PSC1_4 0x01000000UL - -void init_ide_reset(void) -{ - debug("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; -} - -void ide_set_reset(int idereset) -{ - debug("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; - } -} -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ - -#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) -#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C) -#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010) -#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014) - -#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020) -#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028) -#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C) -#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C) - -#define GPIO_WU6 0x40000000UL -#define GPIO_USB0 0x00010000UL -#define GPIO_USB9 0x08000000UL -#define GPIO_USB9S 0x00080000UL - -void init_power_switch(void) -{ - debug("init_power_switch\n"); - - /* Configure GPIO_WU6 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; - __asm__ volatile ("sync"); - - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0; - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0; - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0; - __asm__ volatile ("sync"); - - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9; - __asm__ volatile ("sync"); - - if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) { - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0; - __asm__ volatile ("sync"); - } - *(vu_char *) CFG_CS1_START = 0x02; /* Red Power LED on */ - __asm__ volatile ("sync"); - - *(vu_char *) (CFG_CS1_START + 1) = 0x02; /* Disable driver for KB11 */ - __asm__ volatile ("sync"); -} - -void power_set_reset(int power) -{ - debug("ide_set_reset(%d)\n", power); - - if (power) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_WU6; - *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; - if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == - 0) { - *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= - GPIO_USB0; - } - - } -} - -int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - power_set_reset(1); - return (0); -} - -U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "poweroff- Switch off power\n", NULL); - -int phypower(int flag) -{ - u32 addr; - vu_long *reg; - int status; - pci_dev_t dev; - - dev = PCI_BDF(0, 0x18, 0); - status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr); - if (status == 0) { - reg = (vu_long *) (addr + 0x00000040); - *reg |= 0x40000000; - __asm__ volatile ("sync"); - - reg = (vu_long *) (addr + 0x001000c); - *reg |= 0x20000000; - __asm__ volatile ("sync"); - - reg = (vu_long *) (addr + 0x0010004); - if (flag != 0) { - *reg &= ~0x20000000; - } else { - *reg |= 0x20000000; - } - __asm__ volatile ("sync"); - } - return (status); -} - -int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - int status; - - if (argv[1][0] == '0') { - status = phypower(0); - } else { - status = phypower(1); - } - return (0); -} - -U_BOOT_CMD(phypower, 2, 2, do_phypower, - "phypower- Switch power of ethernet phy\n", NULL); - -int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - int i; - volatile unsigned long *ptr; - - addr = simple_strtol(argv[1], NULL, 16); - size = simple_strtol(argv[2], NULL, 16); - - printf("\nWriting at addr %08x, size %08x.\n", addr, size); - - while (1) { - ptr = (volatile unsigned long *)addr; - for (i = 0; i < (size >> 2); i++) { - *ptr++ = i; - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - putc('.'); - } - return 0; -} - -U_BOOT_CMD(writepci, 3, 1, do_writepci, - "writepci- Write some data to pcibus\n", - " \n" " - Write some data to pcibus.\n"); diff --git a/board/esd/pf5200/u-boot.lds b/board/esd/pf5200/u-boot.lds deleted file mode 100644 index f23432e..0000000 --- a/board/esd/pf5200/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile deleted file mode 100644 index 9340a32..0000000 --- a/board/esd/plu405/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk deleted file mode 100644 index 25b2105..0000000 --- a/board/esd/plu405/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd PLU405 boards -# - -TEXT_BASE = 0xFFFC0000 -#TEXT_BASE = 0x00FC0000 diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c deleted file mode 100644 index 89af119..0000000 --- a/board/esd/plu405/flash.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include - - -#if 0 -#define FPGA_DEBUG -#endif - -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -extern void lxt971_no_sleep(void); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -/* - * include common auto-update code (for esd boards) - */ -#include "../common/auto_update.h" - -au_image_t au_image[] = { - {"plu405/preinst.img", 0, -1, AU_SCRIPT}, - {"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, - {"plu405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND}, - {"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND}, - {"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND}, - {"plu405/postinst.img", 0, 0, AU_SCRIPT}, -}; - -int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); - - -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ - - return 0; -} - - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Reset external DUARTs - */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ - udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ - udelay(1000); /* wait 1ms */ - - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* - * Enable interrupts in exar duart mcr[3] - */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; - - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming PLU405"); - } else { - puts(str); - } - - putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} - - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; - } -} -#endif /* CONFIG_IDE_RESET */ - - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - -#ifdef CONFIG_AUTO_UPDATE_SHOW -void board_auto_update_show(int au_active) -{ - if (au_active) { - printf("\n Dies ist die board-funktion: Updating!!!\n"); - } else { - printf("\n Dies ist die board-funktion: Updating done!!!\n"); - } -} -#endif diff --git a/board/esd/plu405/u-boot.lds b/board/esd/plu405/u-boot.lds deleted file mode 100644 index 43f7765..0000000 --- a/board/esd/plu405/u-boot.lds +++ /dev/null @@ -1,151 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile deleted file mode 100644 index 1281be7..0000000 --- a/board/esd/pmc405/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -# Objects for Xilinx JTAG programming (CPLD) -CPLD = ../common/xilinx_jtag/lenval.o \ - ../common/xilinx_jtag/micro.o \ - ../common/xilinx_jtag/ports.o - -OBJS = $(BOARD).o ../common/misc.o $(CPLD) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/pmc405/config.mk b/board/esd/pmc405/config.mk deleted file mode 100644 index fc2794d..0000000 --- a/board/esd/pmc405/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd PMC405 boards -# - -TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/pmc405/fpgadata.c b/board/esd/pmc405/fpgadata.c deleted file mode 100644 index ebdf71d..0000000 --- a/board/esd/pmc405/fpgadata.c +++ /dev/null @@ -1,2472 +0,0 @@ - 0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08, - 0xfe,0x08,0x00,0x00,0x00,0x20,0x01,0x0f,0xff,0xff,0xff,0x09,0x00,0x00,0x00,0x00, - 0xf9,0x60,0x20,0x93,0x02,0x08,0xff,0x02,0x08,0xff,0x02,0x08,0xe8,0x08,0x00,0x00, - 0x00,0x06,0x01,0x00,0x09,0x05,0x00,0x02,0x08,0xed,0x04,0x00,0x03,0x0d,0x40,0x08, - 0x00,0x00,0x00,0x12,0x01,0x00,0x00,0x00,0x09,0x03,0xff,0xff,0x00,0x00,0x00,0x01, - 0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02, - 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0x00,0x01,0x09,0x00,0x35,0xb0,0x00,0x03,0x00,0x35,0xac,0x00,0x01,0x09,0x00,0x35, - 0xc0,0x00,0x03,0x00,0x35,0xb0,0x00,0x01,0x09,0x00,0x35,0xc4,0x00,0x03,0x00,0x35, - 0xc0,0x00,0x01,0x09,0x00,0x35,0xc8,0x00,0x03,0x00,0x35,0xc4,0x00,0x01,0x09,0x00, - 0x35,0xcc,0x00,0x03,0x00,0x35,0xc8,0x00,0x01,0x09,0x00,0x35,0xd0,0x00,0x03,0x00, - 0x35,0xcc,0x00,0x01,0x09,0x00,0x35,0xd0,0x00,0x03,0x00,0x35,0xd0,0x00,0x01,0x04, - 0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00,0x00,0x64,0x02,0x08,0xf0,0x04, - 0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x07,0x00,0x07,0x20,0x12,0x00,0x12,0x01,0x04, - 0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00, - 0x00,0x00, diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c deleted file mode 100644 index 33b5f77..0000000 --- a/board/esd/pmc405/pmc405.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - - -extern void lxt971_no_sleep(void); - - -/* fpga configuration data - not compressed, generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; -int filesize = sizeof(fpgadata); - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); - - /* - * Setup GPIO pins (CS6+CS7 as GPIO) - */ - mtdcr(cntrl0, mfdcr(cntrl0) | 0x00300000); - - /* - * Configure GPIO pins - */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA); /* setup for output */ - out32(GPIO0_OR, 0); /* outputs -> low */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming PMC405"); - } else { - puts(str); - } - - putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr; - volatile uchar *ptr; - volatile uchar val; - int i; - - addr = simple_strtol (argv[1], NULL, 16) + 0x16; - - i = 0; - for (;;) { - ptr = (uchar *)addr; - for (i=0; i<8; i++) { - *ptr = i; - val = *ptr; - - if (val != i) { - printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val); - return 0; - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - ptr++; - } - } - - return 0; -} -U_BOOT_CMD( - cantest, 3, 1, do_cantest, - "cantest - Test CAN controller", - NULL - ); diff --git a/board/esd/pmc405/u-boot.lds b/board/esd/pmc405/u-boot.lds deleted file mode 100644 index e84d69e..0000000 --- a/board/esd/pmc405/u-boot.lds +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/tasreg/Makefile b/board/esd/tasreg/Makefile deleted file mode 100644 index e5d8446..0000000 --- a/board/esd/tasreg/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/tasreg/config.mk b/board/esd/tasreg/config.mk deleted file mode 100644 index 69fd8b6..0000000 --- a/board/esd/tasreg/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xffc00000 diff --git a/board/esd/tasreg/flash.c b/board/esd/tasreg/flash.c deleted file mode 100644 index 13c07d2..0000000 --- a/board/esd/tasreg/flash.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -/*#include */ -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i -#include -#include -#include - - -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); - - -#if 0 -#define FPGA_DEBUG -#endif - -/* predefine these here for FPGA programming (before including fpga.c) */ -#define SET_FPGA(data) mbar2_writeLong(MCFSIM_GPIO1_OUT, data) -#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_DONE) -#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_INIT) -#define FPGA_PROG_ACTIVE_HIGH /* on this platform is PROG active high! */ -#define out32(a,b) /* nothing to do (gpio already configured) */ - - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int checkboard (void) { - ulong val; - uchar val8; - - puts ("Board: "); - puts("esd TASREG"); - val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf; - printf(" (Switch=%1X)\n", val8); - - /* - * Set LED on - */ - val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED; - mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ - - return 0; -}; - - -long int initdram (int board_type) { - unsigned long junk = 0xa5a59696; - - /* - * Note: - * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 - */ - -#ifdef CFG_FAST_CLK - /* - * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) - * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 - */ - mbar_writeShort(MCFSIM_DCR, 0x8239); -#elif CFG_PLL_BYPASS - /* - * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) - * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 - */ - mbar_writeShort(MCFSIM_DCR, 0x8202); -#else - /* - * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K) - * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) - */ - mbar_writeShort(MCFSIM_DCR, 0x8222); -#endif - - /* - * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port), - * PM=1 (continuous page mode) - */ - - /* RE=0 (keep auto-refresh disabled while setting up registers) */ - mbar_writeLong(MCFSIM_DACR0, 0x00003324); - - /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */ - mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); - - /** Precharge sequence **/ - mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ - *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */ - udelay(0x10); /* Allow several Precharge cycles */ - - /** Refresh Sequence **/ - mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ - udelay(0x7d0); /* Allow gobs of refresh cycles */ - - /** Mode Register initialization **/ - mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ - *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ - - return CFG_SDRAM_SIZE * 1024 * 1024; -}; - - -int testdram (void) { - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} - - -int misc_init_r (void) -{ - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - uchar buf[8]; - - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * - */ - buf[0] = 0x00; - buf[1] = 0x32; - buf[2] = 0x3f; - i2c_write(0x38, 0, 0, buf, 3); - - return (0); -} - - -#if 1 /* test-only: board specific test commands */ -int i2c_probe(uchar addr); - -/* - */ -int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr; - - if (argc < 2) { - puts("ERROR!\n"); - return -1; - } - - addr = simple_strtol (argv[1], NULL, 16); - - printf("iprobe looping on addr 0x%lx (cntrl-c aborts)...\n", addr); - - for (;;) { - i2c_probe(addr); - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(1000); - } - - return 0; -} -U_BOOT_CMD( - iploop, 2, 1, do_iploop, - "iploop - iprobe loop \n", - NULL - ); - -/* - */ -int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - uchar buf[8]; - - *(volatile ushort *)0xe0000000 = 0x4000; - - udelay(5000); /* wait for 5ms */ - - buf[0] = 0x10; - buf[1] = 0x07; - buf[2] = 0x03; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x01; - buf[2] = 0x80; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x02; - buf[2] = 0x03; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x03; - buf[2] = 0x29; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x04; - buf[2] = 0x00; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x05; - buf[2] = 0x00; - i2c_write(0x10, 0, 0, buf, 3); - - buf[0] = 0x10; - buf[1] = 0x07; - buf[2] = 0x02; - i2c_write(0x10, 0, 0, buf, 3); - - return 0; -} -U_BOOT_CMD( - codec, 1, 1, do_codec, - "codec - Enable codec\n", - NULL - ); - -/* - */ -int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr; - ulong instr; - ulong cntrl; - ulong data; - uchar buf[8]; - - if (argc < 5) { - puts("ERROR!\n"); - return -1; - } - - addr = simple_strtol (argv[1], NULL, 16); - instr = simple_strtol (argv[2], NULL, 16); - cntrl = simple_strtol (argv[3], NULL, 16); - data = simple_strtol (argv[4], NULL, 16); - - buf[0] = (uchar)instr; - buf[1] = (uchar)cntrl; - buf[2] = (uchar)data; - i2c_write(addr, 0, 0, buf, 3); - - return 0; -} -U_BOOT_CMD( - saa, 5, 1, do_saa, - "saa - Write to SAA1064 \n", - NULL - ); - -/* - */ -int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr; - ulong data0; - ulong data1; - ulong data2; - ulong data3; - uchar buf[8]; - int cnt; - - if (argc < 3) { - puts("ERROR!\n"); - return -1; - } - - addr = simple_strtol (argv[1], NULL, 16); - cnt = simple_strtol (argv[2], NULL, 16); - data0 = simple_strtol (argv[3], NULL, 16); - data1 = simple_strtol (argv[4], NULL, 16); - data2 = simple_strtol (argv[5], NULL, 16); - data3 = simple_strtol (argv[6], NULL, 16); - - printf("Writing %d bytes to device %lx!\n", cnt, addr); - buf[0] = (uchar)data0; - buf[1] = (uchar)data1; - buf[2] = (uchar)data2; - buf[3] = (uchar)data3; - i2c_write(addr, 0, 0, buf, cnt); - - return 0; -} -U_BOOT_CMD( - iwrite, 6, 1, do_iwrite, - "iwrite - Write n bytes to I2C-device\n", - "addr cnt data0 ... datan\n" - ); - -/* - */ -int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr; - ulong cnt; - uchar buf[32]; - int i; - - if (argc < 3) { - puts("ERROR!\n"); - return -1; - } - - addr = simple_strtol (argv[1], NULL, 16); - cnt = simple_strtol (argv[2], NULL, 16); - - i2c_read(addr, 0, 0, buf, cnt); - printf("I2C Data:"); - for (i=0; i \n", - NULL - ); - -/* - */ -int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr; - uchar buf[32]; - int cnt; - - if (argc < 2) { - puts("ERROR!\n"); - return -1; - } - - addr = simple_strtol (argv[1], NULL, 16); - cnt = 1; - - printf("iread looping on addr 0x%lx (cntrl-c aborts)...\n", addr); - - for (;;) { - i2c_read(addr, 0, 0, buf, cnt); - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(3000); - } - - return 0; -} -U_BOOT_CMD( - ireadl, 2, 1, do_ireadl, - "ireadl - Read-loop from I2C \n", - NULL - ); -#endif diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds deleted file mode 100644 index a803b1c..0000000 --- a/board/esd/tasreg/u-boot.lds +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(m68k) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mcf52x2/start.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) - common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - *(.got) - __got_end = .; - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - _sbss = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile deleted file mode 100644 index a60495a..0000000 --- a/board/esd/voh405/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/voh405/config.mk b/board/esd/voh405/config.mk deleted file mode 100644 index 219a4eb..0000000 --- a/board/esd/voh405/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd VOH405 boards -# - -TEXT_BASE = 0xFFF80000 diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c deleted file mode 100644 index 89af119..0000000 --- a/board/esd/voh405/flash.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c deleted file mode 100644 index eda3fd9..0000000 --- a/board/esd/voh405/voh405.c +++ /dev/null @@ -1,356 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -extern void lxt971_no_sleep(void); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - - -/* logo bitmap data - gzip compressed and generated by bin2c */ -unsigned char logo_bmp_320[] = -{ -#include "logo_320_240_4bpp.c" -}; - -unsigned char logo_bmp_640[] = -{ -#include "logo_640_480_24bpp.c" -}; - - -/* - * include common lcd code (for esd boards) - */ -#include "../common/lcd.c" - -#include "../common/s1d13704_320_240_4bpp.h" -#include "../common/s1d13806_320_240_4bpp.h" -#include "../common/s1d13806_640_480_16bpp.h" - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFFB5); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ - - return 0; -} - - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); - volatile unsigned short *lcd_contrast = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4); - volatile unsigned short *lcd_backlight = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6); - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - char *str; - - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_INIT pin - */ - out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */ - udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */ - udelay(1000); /* wait 1ms */ - - /* - * Reset external DUARTs - */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ - udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ - udelay(1000); /* wait 1ms */ - - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* - * Enable interrupts in exar duart mcr[3] - */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; - - /* - * Init lcd interface and display logo - */ - str = getenv("bd_type"); - if (strcmp(str, "voh405_bw") == 0) { - lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - } else if (strcmp(str, "voh405_bwbw") == 0) { - lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - lcd_setup(1, 1); - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, - regs_13806_320_240_4bpp, - sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - } else if (strcmp(str, "voh405_bwc") == 0) { - lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, - regs_13704_320_240_4bpp, - sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), - logo_bmp_320, sizeof(logo_bmp_320)); - lcd_setup(1, 0); - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), - logo_bmp_640, sizeof(logo_bmp_640)); - } else { - printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); - return 0; - } - - /* - * Set invert bit in small lcd controller - */ - *(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01; - - /* - * Set default contrast voltage on epson vga controller - */ - *lcd_contrast = 0x4646; - - /* - * Enable backlight - */ - *lcd_backlight = 0xffff; - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming VOH405"); - } else { - puts(str); - } - - if (getenv_r("bd_type", str, sizeof(str)) != -1) { - printf(" (%s)", str); - } else { - puts(" (Missing bd_type!)"); - } - - putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; - } -} -#endif /* CONFIG_IDE_RESET */ - - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile deleted file mode 100644 index a11ee82..0000000 --- a/board/esd/vom405/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -# Objects for Xilinx JTAG programming (CPLD) -CPLD = ../common/xilinx_jtag/lenval.o \ - ../common/xilinx_jtag/micro.o \ - ../common/xilinx_jtag/ports.o - -OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/vom405/config.mk b/board/esd/vom405/config.mk deleted file mode 100644 index 3041b77..0000000 --- a/board/esd/vom405/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd VOH405 boards -# - -TEXT_BASE = 0xFFFC0000 -#TEXT_BASE = 0x00FC0000 diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c deleted file mode 100644 index 89af119..0000000 --- a/board/esd/vom405/flash.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c deleted file mode 100644 index 445b8fc..0000000 --- a/board/esd/vom405/vom405.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - - -extern void lxt971_no_sleep(void); - - -/* fpga configuration data - not compressed, generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; -int filesize = sizeof(fpgadata); - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ - - /* - * Reset CPLD via GPIO12 (CS3) pin - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(0x80000000 >> 12)); - udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | (0x80000000 >> 12)); - udelay(1000); /* wait 1ms */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - unsigned char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - int flashcnt; - int delay; - volatile unsigned char *led_reg = (unsigned char *)((ulong)CAN_BA + 0x1000); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming VOM405"); - } else { - puts(str); - } - - printf(" (PLD-Version=%02d)\n", *led_reg); - - /* - * Flash LEDs - */ - for (flashcnt = 0; flashcnt < 3; flashcnt++) { - *led_reg = 0x40; /* LED_B..D off */ - for (delay = 0; delay < 100; delay++) - udelay(1000); - *led_reg = 0x47; /* LED_B..D on */ - for (delay = 0; delay < 50; delay++) - udelay(1000); - } - *led_reg = 0x40; - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile deleted file mode 100644 index a60495a..0000000 --- a/board/esd/wuh405/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../common/misc.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esd/wuh405/config.mk b/board/esd/wuh405/config.mk deleted file mode 100644 index 1d743a9..0000000 --- a/board/esd/wuh405/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ASH405 boards -# - -TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c deleted file mode 100644 index 89af119..0000000 --- a/board/esd/wuh405/flash.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c deleted file mode 100644 index db24122..0000000 --- a/board/esd/wuh405/wuh405.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); - volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4); - volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4); - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc ('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Reset external DUARTs - */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ - udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ - udelay(1000); /* wait 1ms */ - - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* - * Enable interrupts in exar duart mcr[3] - */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; - *duart2_mcr = 0x08; - *duart3_mcr = 0x08; - - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming WUH405"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esteem192e/Makefile b/board/esteem192e/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/esteem192e/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/esteem192e/config.mk b/board/esteem192e/config.mk deleted file mode 100644 index 9d6080b..0000000 --- a/board/esteem192e/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TQM8xxL boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/esteem192e/esteem192e.c b/board/esteem192e/esteem192e.c deleted file mode 100644 index 3959eea..0000000 --- a/board/esteem192e/esteem192e.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - * Modified By Conn Clark to work with Esteem 192E 7/31/00 - * - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - * - * active, NOP, read, precharge, NOP */ - 0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00, - 0x11FFCC05, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * NOP, Program - */ - 0x0F0A8C34, 0x1F354C37, /* last */ - - _NOT_USED_, /* Not used */ - - /* - * Burst Read. (Offset 8 in UPMA RAM) - * active, NOP, read, NOP, NOP, NOP, NOP, NOP */ - 0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00, - 0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - * active, NOP, write, NOP, precharge, NOP */ - 0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04, - 0x0FF74C04, 0x1FFFCC05, /* last */ - _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - * active, NOP, write, NOP, NOP, NOP, NOP, NOP */ - 0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00, - 0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - * precharge, NOP, auto_ref, NOP, NOP, NOP */ - 0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, - 0x0FFFCCB4, 0x1FFFCC35, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x0FFB8C00, 0x1FF74C03, /* last */ - _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: Esteem 192E\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size_b1; - - /* - * Explain frequency of refresh here - */ - - memctl->memc_mptpr = 0x0200; /* divide by 32 */ - - memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL; */ /* 0x18005112 TODO: explain here */ - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Map cs 2 and 3 to the SDRAM banks 0 and 1 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - - memctl->memc_or2 = CFG_OR2_PRELIM; /* not defined yet */ - memctl->memc_br2 = CFG_BR2_PRELIM; - - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - - - /* perform SDRAM initializsation sequence */ - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */ - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - - memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */ - memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ - - memctl->memc_mamr = CFG_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */ - -/* printf ("banks 0 and 1 are programed\n"); */ - - /* - * Check Bank 0 Memory Size for re-configuration - * - */ - size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - - printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1); - -/* printf ("bank 1 size %u\n",size_b1); */ - - if (size_b1 == 0) { - /* - * Adjust refresh rate if bank 0 isn't stuffed - */ - memctl->memc_mptpr = 0x0400; /* divide by 64 */ - memctl->memc_br3 &= 0x0FFFFFFFE; - - /* - * Adjust OR2 for size of bank 0 - */ - memctl->memc_or2 |= 7 * size_b0; - } else { - if (size_b0 < size_b1) { - memctl->memc_br2 &= 0x00007FFE; - memctl->memc_br3 &= 0x00007FFF; - - /* - * Adjust OR3 for size of bank 1 - */ - memctl->memc_or3 |= 15 * size_b1; - - /* - * Adjust OR2 for size of bank 0 - */ - memctl->memc_or2 |= 15 * size_b0; - memctl->memc_br2 += (size_b1 + 1); - } else { - memctl->memc_br3 &= 0x00007FFE; - - /* - * Adjust OR2 for size of bank 0 - */ - memctl->memc_or2 |= 15 * size_b0; - - /* - * Adjust OR3 for size of bank 1 - */ - memctl->memc_or3 |= 15 * size_b1; - memctl->memc_br3 += (size_b0 + 1); - } - } - - /* before leaving set all unused i/o pins to outputs */ - - /* - * --*Unused Pin List*-- - * - * group/port bit number - * IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx - * PA 5,7,8,9,14,15 - * PB 22,23,31 - * PC 4,5,6,7,10,11,12,13,14,15 - * PD 5,6,7 - * - */ - - /* - * --*Pin Used for I/O List*-- - * - * port input bit number output bit number either - * PB 18,26,27 - * PD 3,4 8,9,10,11,12,13,14,15 - * - */ - - immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */ - immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */ - immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */ - immap->im_ioport.iop_padat |= 0x05C3; /* set unused pins as high */ - - immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */ - immap->im_cpm.cp_pbdir |= 0x00001331; /* set unused port b pins as output */ - immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */ - immap->im_cpm.cp_pbdat |= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */ - - immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */ - immap->im_ioport.iop_pcdir |= 0x0F3F; /* set unused port c pins as output */ - immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */ - immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high */ - - immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */ - immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */ - immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */ - immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */ - - return (size_b0 + size_b1); -} diff --git a/board/esteem192e/flash.c b/board/esteem192e/flash.c deleted file mode 100644 index 5465dea..0000000 --- a/board/esteem192e/flash.c +++ /dev/null @@ -1,1095 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#ifdef CONFIG_FLASH_16BIT -#define FLASH_WORD_SIZE unsigned short -#define FLASH_ID_MASK 0xFFFF -#else -#define FLASH_WORD_SIZE unsigned long -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -/*----------------------------------------------------------------------- - * Functions - */ - -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); -#ifndef CONFIG_FLASH_16BIT -static int write_word (flash_info_t *info, ulong dest, ulong data); -#else -static int write_short (flash_info_t *info, ulong dest, ushort data); -#endif -/*int flash_write (uchar *, ulong, ulong); */ -/*flash_info_t *addr2info (ulong); */ - -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = CFG_FLASH_BASE | 0x00000801; /* (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;*/ - - /* Re-do sizing to get full correct info */ - - size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE, - &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = (CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK); - /*((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V;*/ - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start adress table */ - if (info->flash_id & FLASH_BTYPE) { - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_FLASH_16BIT - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00008000; - info->start[3] = base + 0x0000C000; - info->start[4] = base + 0x00010000; - info->start[5] = base + 0x00014000; - info->start[6] = base + 0x00018000; - info->start[7] = base + 0x0001C000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x000E0000; - } - } - else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } -#else - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000A000; - info->start[6] = base + 0x0000C000; - info->start[7] = base + 0x0000E000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00070000; - } - } - else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } -#endif - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_FLASH_16BIT - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00014000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x0001C000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - - } else { - - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - - } else { - - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -#endif - } - - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar botboot[]=", bottom boot sect)\n"; - uchar topboot[]=", top boot sector)\n"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - if (info->flash_id & 0x0001 ) { - boottype = botboot; - } else { - boottype = topboot; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype); - break; - case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype); - break; - case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype); - break; - case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype); - break; - case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype); - break; - case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype); - break; - case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype); - break; - -#if 0 /* enable when devices are available */ - - case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype); - break; - case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype); - break; -#endif - - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) -{ - short i; - ulong base = (ulong)addr; - FLASH_WORD_SIZE value; - - /* Write auto select command: read Manufacturer ID */ - - -#ifndef CONFIG_FLASH_16BIT - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x00890089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x00900090; - if(addr[0x0000] != 0x00890089){ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x0089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x0090; - - if(addr[0x0000] != 0x0089){ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0090; -#endif - } - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - - } - - value = addr[1]; /* device ID */ - - switch (value) { - - case (AMD_ID_LV400T & FLASH_ID_MASK): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & FLASH_ID_MASK): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & FLASH_ID_MASK): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & FLASH_ID_MASK): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160T & FLASH_ID_MASK): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & FLASH_ID_MASK): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & FLASH_ID_MASK): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_LV320B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case (INTEL_ID_28F800B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800T; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F800B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F160B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160T; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F160B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 /* enable when devices are available */ - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start adress table */ - if (info->flash_id & FLASH_BTYPE) { - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_FLASH_16BIT - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00008000; - info->start[3] = base + 0x0000C000; - info->start[4] = base + 0x00010000; - info->start[5] = base + 0x00014000; - info->start[6] = base + 0x00018000; - info->start[7] = base + 0x0001C000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x000E0000; - } - } - else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } -#else - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000A000; - info->start[6] = base + 0x0000C000; - info->start[7] = base + 0x0000E000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00070000; - } - } - else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } -#endif - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CONFIG_FLASH_16BIT - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00014000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x0001C000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - - } else { - - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - - } else { - - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -#endif - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){ - *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - } - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - - volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); - int flag, prot, sect, l_sect, barf; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - ((info->flash_id > FLASH_AMD_COMP) && - ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){ - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - if(info->flash_id < FLASH_AMD_COMP) { -#ifndef CONFIG_FLASH_16BIT - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; -#endif - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); - while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != - (0x00800080&FLASH_ID_MASK) ) - { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - barf = 0; -#ifndef CONFIG_FLASH_16BIT - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00200020; - addr[0] = 0x00D000D0; - while(!(addr[0] & 0x00800080)); /* wait for error or finish */ - if( addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if( barf ) { - barf >>=16; - } else { - barf = addr[0] & 0x0000003A; - } - } -#else - addr = (vu_short*)(info->start[sect]); - addr[0] = 0x0020; - addr[0] = 0x00D0; - while(!(addr[0] & 0x0080)); /* wait for error or finish */ - if( addr[0] & 0x003A) /* check for error */ - barf = addr[0] & 0x003A; -#endif - if(barf) { - printf("\nFlash error in sector at %lx\n",(unsigned long)addr); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if((barf & 0x0030) == 0x0030) - printf("Command Sequence error.\n"); - if((barf & 0x0030) == 0x0020) - printf("Block Erase error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - rcode = 1; - } else printf("."); - l_sect = sect; - } - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - - } - - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ -#ifndef CONFIG_FLASH_16BIT - ulong cp, wp, data; - int l; -#else - ulong cp, wp; - ushort data; -#endif - int i, rc; - -#ifndef CONFIG_FLASH_16BIT - - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); - -#else - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start byte - */ - if (addr - wp) { - data = 0; - data = (data << 8) | *src++; - --cnt; - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ -/* l = 0; used for debuging */ - while (cnt >= 2) { - data = 0; - for (i=0; i<2; ++i) { - data = (data << 8) | *src++; - } - -/* if(!l){ - printf("%x",data); - l = 1; - } used for debuging */ - - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_short(info, wp, data)); - - -#endif -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifndef CONFIG_FLASH_16BIT -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start,barf; - int flag; - - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if(info->flash_id > FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - } else { - /* intel stuff */ - *addr = 0x00400040; - } - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - - if(info->flash_id > FLASH_AMD_COMP) { - - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - } else { - - while(!(addr[0] & 0x00800080)){ /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - - if( addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if( barf ) { - barf >>=16; - } else { - barf = addr[0] & 0x0000003A; - } - printf("\nFlash write error at address %lx\n",(unsigned long)dest); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if(barf & 0x0010) printf("Programming error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - return(2); - } - - - } - - return (0); - -} - -#else - -static int write_short (flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - ulong start,barf; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if(info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - } else { - /* intel stuff */ - *addr = 0x00D0; - *addr = 0x0040; - } - *((vu_short *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - - if(info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - } else { - /* intel stuff */ - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); - } - - if( addr[0] & 0x003A) { /* check for error */ - barf = addr[0] & 0x003A; - printf("\nFlash write error at address %lx\n",(unsigned long)dest); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if(barf & 0x0010) printf("Programming error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - return(2); - } - *addr = 0x00B0; - *addr = 0x0070; - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); - } - - *addr = 0x00FF; - - } - - return (0); - -} - - -#endif - -/*----------------------------------------------------------------------- - */ diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds deleted file mode 100644 index 4c541bf..0000000 --- a/board/esteem192e/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/etin/debris/Makefile b/board/etin/debris/Makefile deleted file mode 100644 index 305a1bf..0000000 --- a/board/etin/debris/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o phantom.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/etin/debris/config.mk b/board/etin/debris/config.mk deleted file mode 100644 index 64debf5..0000000 --- a/board/etin/debris/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Sangmoon, Etin Systems, dogoil@etinsys.com. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Debris boards -# - -#TEXT_BASE = 0x00090000 -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c deleted file mode 100644 index 93c502c..0000000 --- a/board/etin/debris/debris.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * (C) Copyright 2000 - * Sangmoon Kim, Etin Systems. dogoil@etinsys.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -int checkboard (void) -{ - /*TODO: Check processor type */ - - puts ( "Board: Debris " -#ifdef CONFIG_MPC8240 - "8240" -#endif -#ifdef CONFIG_MPC8245 - "8245" -#endif - " ##Test not implemented yet##\n"); - return 0; -} - -#if 0 /* NOT USED */ -int checkflash (void) -{ - /* TODO: XXX XXX XXX */ - printf ("## Test not implemented yet ##\n"); - - return (0); -} -#endif - -long int initdram (int board_type) -{ - int m, row, col, bank, i; - unsigned long start, end; - uint32_t mccr1; - uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0; - uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; - uint8_t mber = 0; - - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); - - if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */ - m = i2c_reg_read (0x50, 5); /* # of physical banks */ - row = i2c_reg_read (0x50, 3); /* # of rows */ - col = i2c_reg_read (0x50, 4); /* # of columns */ - bank = i2c_reg_read (0x50, 17); /* # of logical banks */ - - CONFIG_READ_WORD(MCCR1, mccr1); - mccr1 &= 0xffff0000; - - start = CFG_SDRAM_BASE; - end = start + (1 << (col + row + 3) ) * bank - 1; - - for (i = 0; i < m; i++) { - mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2; - if (i < 4) { - msar1 |= ((start >> 20) & 0xff) << i * 8; - emsar1 |= ((start >> 28) & 0xff) << i * 8; - mear1 |= ((end >> 20) & 0xff) << i * 8; - emear1 |= ((end >> 28) & 0xff) << i * 8; - } else { - msar2 |= ((start >> 20) & 0xff) << (i-4) * 8; - emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8; - mear2 |= ((end >> 20) & 0xff) << (i-4) * 8; - emear2 |= ((end >> 28) & 0xff) << (i-4) * 8; - } - mber |= 1 << i; - start += (1 << (col + row + 3) ) * bank; - end += (1 << (col + row + 3) ) * bank; - } - for (; i < 8; i++) { - if (i < 4) { - msar1 |= 0xff << i * 8; - emsar1 |= 0x30 << i * 8; - mear1 |= 0xff << i * 8; - emear1 |= 0x30 << i * 8; - } else { - msar2 |= 0xff << (i-4) * 8; - emsar2 |= 0x30 << (i-4) * 8; - mear2 |= 0xff << (i-4) * 8; - emear2 |= 0x30 << (i-4) * 8; - } - } - - CONFIG_WRITE_WORD(MCCR1, mccr1); - CONFIG_WRITE_WORD(MSAR1, msar1); - CONFIG_WRITE_WORD(EMSAR1, emsar1); - CONFIG_WRITE_WORD(MEAR1, mear1); - CONFIG_WRITE_WORD(EMEAR1, emear1); - CONFIG_WRITE_WORD(MSAR2, msar2); - CONFIG_WRITE_WORD(EMSAR2, emsar2); - CONFIG_WRITE_WORD(MEAR2, mear2); - CONFIG_WRITE_WORD(EMEAR2, emear2); - CONFIG_WRITE_BYTE(MBER, mber); - - return (1 << (col + row + 3) ) * bank * m; -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_debris_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_debris_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -void *nvram_read(void *dest, const long src, size_t count) -{ - volatile uchar *d = (volatile uchar*) dest; - volatile uchar *s = (volatile uchar*) src; - while(count--) { - *d++ = *s++; - asm volatile("sync"); - } - return dest; -} - -void nvram_write(long dest, const void *src, size_t count) -{ - volatile uchar *d = (volatile uchar*)dest; - volatile uchar *s = (volatile uchar*)src; - while(count--) { - *d++ = *s++; - asm volatile("sync"); - } -} - -int misc_init_r(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Write ethernet addr in NVRAM for VxWorks */ - nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS, - (char*)&gd->bd->bi_enetaddr[0], 6); - return 0; -} diff --git a/board/etin/debris/flash.c b/board/etin/debris/flash.c deleted file mode 100644 index a4100e5..0000000 --- a/board/etin/debris/flash.c +++ /dev/null @@ -1,720 +0,0 @@ -/* - * board/eva/flash.c - * - * (C) Copyright 2002 - * Sangmoon Kim, Etin Systems, dogoil@etinsys.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t); -int (*write_dword)(flash_info_t*, ulong, uint64_t); - -typedef uint64_t cfi_word; - -#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr)) - -#define cfi_write(flash, val, addr) \ - move64((cfi_word*)&val, \ - (cfi_word*)(flash->start[0] + addr)) - -#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x))) - -static void write32(unsigned long addr, uint32_t value) -{ - *(volatile uint32_t*)(addr) = value; - asm volatile("sync"); -} - -static uint32_t read32(unsigned long addr) -{ - uint32_t value; - value = *(volatile uint32_t*)addr; - asm volatile("sync"); - return value; -} - -static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr) -{ - uint32_t base = flash->start[0]; - uint32_t val=(cmd << 16) | cmd; - addr <<= 3; - write32(base + addr, val); - return addr; -} - -static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr) -{ - uint32_t base = flash->start[0]; - addr <<= 3; - return (uint16_t)read32(base + addr); -} - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static void move64(uint64_t *src, uint64_t *dest) -{ - asm volatile("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0" ); /* Clobbers fr0 */ - return; -} - -static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data) -{ - unsigned long start; - cfi_word status = 0; - - status = cfi_read(flash, dest); - data &= status; - - cfi_cmd(flash, 0x40, 0); - cfi_write(flash, data, dest); - - udelay(10); - start = get_timer (0); - for(;;) { - status = cfi_read(flash, dest); - status &= CMD(0x80); - if(status == CMD(0x80)) - break; - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - cfi_cmd(flash, 0xff, 0); - return 1; - } - udelay(1); - } - cfi_cmd(flash, 0xff, 0); - - return 0; -} - -static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data) -{ - ulong start; - cfi_word status = 0; - - status = cfi_read(flash, dest); - if(status != CMD(0xffff)) return 2; - - cfi_cmd(flash, 0xaa, 0x555); - cfi_cmd(flash, 0x55, 0x2aa); - cfi_cmd(flash, 0xa0, 0x555); - - cfi_write(flash, data, dest); - - udelay(10); - start = get_timer (0); - status = ~data; - while(status != data) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) - return 1; - status = cfi_read(flash, dest); - udelay(1); - } - return 0; -} - -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); -} - -int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - int i, s, l, rc; - cfi_word data; - uint8_t *t = (uint8_t*)&data; - unsigned long base = flash->start[0]; - uint32_t msr; - - if (flash->flash_id == FLASH_UNKNOWN) - return 4; - - if (cnt == 0) - return 0; - - addr -= base; - - msr = get_msr(); - set_msr(msr|MSR_FP); - - wp = (addr & ~7); /* get lower word aligned address */ - - if((addr-wp) != 0) { - data = cfi_read(flash, wp); - s = addr & 7; - l = ( cnt < (8-s) ) ? cnt : (8-s); - for(i = 0; i < l; i++) - t[s+i] = *src++; - if ((rc = write_dword(flash, wp, data)) != 0) - goto DONE; - wp += 8; - cnt -= l; - } - - while (cnt >= 8) { - for (i = 0; i < 8; i++) - t[i] = *src++; - if ((rc = write_dword(flash, wp, data)) != 0) - goto DONE; - wp += 8; - cnt -= 8; - } - - if (cnt == 0) { - rc = 0; - goto DONE; - } - - data = cfi_read(flash, wp); - for(i = 0; i < cnt; i++) - t[i] = *src++; - rc = write_dword(flash, wp, data); -DONE: - set_msr(msr); - return rc; -} - -static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect) -{ - int sa; - int flag; - ulong start, last, now; - cfi_word status; - - flag = disable_interrupts(); - - sa = (flash->start[sect] - flash->start[0]); - write32(flash->start[sect], 0x00200020); - write32(flash->start[sect], 0x00d000d0); - - if (flag) - enable_interrupts(); - - udelay(1000); - start = get_timer (0); - last = start; - - for (;;) { - status = cfi_read(flash, sa); - status &= CMD(0x80); - if (status == CMD(0x80)) - break; - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - cfi_cmd(flash, 0xff, 0); - printf ("Timeout\n"); - return ERR_TIMOUT; - } - - if ((now - last) > 1000) { - serial_putc ('.'); - last = now; - } - udelay(10); - } - cfi_cmd(flash, 0xff, 0); - return ERR_OK; -} - -static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last) -{ - int sect; - int rc = ERR_OK; - - for (sect = s_first; sect <= s_last; sect++) { - if (flash->protect[sect] == 0) { - rc = cfi_erase_oneblock(flash, sect); - if (rc != ERR_OK) break; - } - } - printf (" done\n"); - return rc; -} - -static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last) -{ - int sect; - cfi_word status; - int sa = -1; - int flag; - ulong start, last, now; - - flag = disable_interrupts(); - - cfi_cmd(flash, 0xaa, 0x555); - cfi_cmd(flash, 0x55, 0x2aa); - cfi_cmd(flash, 0x80, 0x555); - cfi_cmd(flash, 0xaa, 0x555); - cfi_cmd(flash, 0x55, 0x2aa); - for ( sect = s_first; sect <= s_last; sect++) { - if (flash->protect[sect] == 0) { - sa = flash->start[sect] - flash->start[0]; - write32(flash->start[sect], 0x00300030); - } - } - if (flag) - enable_interrupts(); - - if (sa < 0) - goto DONE; - - udelay (1000); - start = get_timer (0); - last = start; - for(;;) { - status = cfi_read(flash, sa); - if (status == CMD(0xffff)) - break; - - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - - if ((now - last) > 1000) { - serial_putc ('.'); - last = now; - } - udelay(10); - } -DONE: - cfi_cmd(flash, 0xf0, 0); - - printf (" done\n"); - - return ERR_OK; -} - -int flash_erase (flash_info_t *flash, int s_first, int s_last) -{ - int sect; - int prot; - - if ((s_first < 0) || (s_first > s_last)) { - if (flash->flash_id == FLASH_UNKNOWN) - printf ("- missing\n"); - else - printf ("- no sectors to erase\n"); - return ERR_NOT_ERASED; - } - if (flash->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return ERR_NOT_ERASED; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) - if (flash->protect[sect]) prot++; - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - else - printf ("\n"); - - return do_flash_erase(flash, s_first, s_last); -} - -struct jedec_flash_info { - const uint16_t mfr_id; - const uint16_t dev_id; - const char *name; - const int DevSize; - const int InterfaceDesc; - const int NumEraseRegions; - const ulong regions[4]; -}; - -#define ERASEINFO(size,blocks) (size<<8)|(blocks-1) - -#define SIZE_1MiB 20 -#define SIZE_2MiB 21 -#define SIZE_4MiB 22 - -static const struct jedec_flash_info jedec_table[] = { - { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV800T, - name: "AMD AM29LV800T", - DevSize: SIZE_1MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x10000,15), - ERASEINFO(0x08000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x04000,1) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV800B, - name: "AMD AM29LV800B", - DevSize: SIZE_1MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x10000,15), - ERASEINFO(0x08000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x04000,1) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV160T, - name: "AMD AM29LV160T", - DevSize: SIZE_2MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x10000,31), - ERASEINFO(0x08000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x04000,1) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV160B, - name: "AMD AM29LV160B", - DevSize: SIZE_2MiB, - NumEraseRegions: 4, - regions: {ERASEINFO(0x04000,1), - ERASEINFO(0x02000,2), - ERASEINFO(0x08000,1), - ERASEINFO(0x10000,31) - } - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV320T, - name: "AMD AM29LV320T", - DevSize: SIZE_4MiB, - NumEraseRegions: 2, - regions: {ERASEINFO(0x10000,63), - ERASEINFO(0x02000,8) - } - - }, { - mfr_id: (uint16_t)AMD_MANUFACT, - dev_id: (uint16_t)AMD_ID_LV320B, - name: "AMD AM29LV320B", - DevSize: SIZE_4MiB, - NumEraseRegions: 2, - regions: {ERASEINFO(0x02000,8), - ERASEINFO(0x10000,63) - } - } -}; - -static ulong cfi_init(uint32_t base, flash_info_t *flash) -{ - int sector; - int block; - int block_count; - int offset = 0; - int reverse = 0; - int primary; - int mfr_id; - int dev_id; - - flash->start[0] = base; - cfi_cmd(flash, 0xF0, 0); - cfi_cmd(flash, 0x98, 0); - if ( !( cfi_read_query(flash, 0x10) == 'Q' && - cfi_read_query(flash, 0x11) == 'R' && - cfi_read_query(flash, 0x12) == 'Y' )) { - cfi_cmd(flash, 0xff, 0); - return 0; - } - - flash->size = 1 << cfi_read_query(flash, 0x27); - flash->size *= 4; - block_count = cfi_read_query(flash, 0x2c); - primary = cfi_read_query(flash, 0x15); - if ( cfi_read_query(flash, primary + 4) == 0x30) - reverse = (cfi_read_query(flash, 0x1) & 0x01); - else - reverse = (cfi_read_query(flash, primary+15) == 3); - - flash->sector_count = 0; - - for ( block = reverse ? block_count - 1 : 0; - reverse ? block >= 0 : block < block_count; - reverse ? block-- : block ++) { - int sector_size = - (cfi_read_query(flash, 0x2d + block*4+2) | - (cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8; - int sector_count = - (cfi_read_query(flash, 0x2d + block*4+0) | - (cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1; - for(sector = 0; sector < sector_count; sector++) { - flash->start[flash->sector_count++] = base + offset; - offset += sector_size * 4; - } - } - mfr_id = cfi_read_query(flash, 0x00); - dev_id = cfi_read_query(flash, 0x01); - - cfi_cmd(flash, 0xff, 0); - - flash->flash_id = (mfr_id << 16) | dev_id; - - for (sector = 0; sector < flash->sector_count; sector++) { - write32(flash->start[sector], 0x00600060); - write32(flash->start[sector], 0x00d000d0); - } - cfi_cmd(flash, 0xff, 0); - - for (sector = 0; sector < flash->sector_count; sector++) - flash->protect[sector] = 0; - - do_flash_erase = cfi_erase; - write_dword = cfi_write_dword; - - return flash->size; -} - -static ulong jedec_init(unsigned long base, flash_info_t *flash) -{ - int i; - int block, block_count; - int sector, offset; - int mfr_id, dev_id; - flash->start[0] = base; - cfi_cmd(flash, 0xF0, 0x000); - cfi_cmd(flash, 0xAA, 0x555); - cfi_cmd(flash, 0x55, 0x2AA); - cfi_cmd(flash, 0x90, 0x555); - mfr_id = cfi_read_query(flash, 0x000); - dev_id = cfi_read_query(flash, 0x0001); - cfi_cmd(flash, 0xf0, 0x000); - - for(i=0; iflash_id = (mfr_id << 16) | dev_id; - flash->size = 1 << jedec_table[0].DevSize; - flash->size *= 4; - block_count = jedec_table[i].NumEraseRegions; - offset = 0; - flash->sector_count = 0; - for (block = 0; block < block_count; block++) { - int sector_size = jedec_table[i].regions[block]; - int sector_count = (sector_size & 0xff) + 1; - sector_size >>= 8; - for (sector=0; sectorstart[flash->sector_count++] = - base + offset; - offset += sector_size * 4; - } - } - break; - } - } - - for (sector = 0; sector < flash->sector_count; sector++) - flash->protect[sector] = 0; - - do_flash_erase = jedec_erase; - write_dword = jedec_write_dword; - - return flash->size; -} - -inline void mtibat1u(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 530, %0" :: "r" (x)); -} - -inline void mtibat1l(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 531, %0" :: "r" (x)); -} - -inline void mtdbat1u(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 538, %0" :: "r" (x)); -} - -inline void mtdbat1l(unsigned int x) -{ - __asm__ __volatile__ ("mtspr 539, %0" :: "r" (x)); -} - -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - unsigned int msr; - - /* BAT1 */ - CONFIG_WRITE_WORD(ERCR3, 0x0C00000C); - CONFIG_WRITE_WORD(ERCR4, 0x0800000C); - msr = get_msr(); - set_msr(msr & ~(MSR_IR | MSR_DR)); - mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); - mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); - mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT); - mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); - set_msr(msr); - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) - flash_info[i].flash_id = FLASH_UNKNOWN; - size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]); - if (!size) - size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) - printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", - size, size<<20); - - return size; -} - -void flash_print_info (flash_info_t *flash) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *p; - - if (flash->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - flash_init(); - } - - if (flash->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (((flash->flash_id) >> 16) & 0xff) { - case 0x01: - printf ("AMD "); - break; - case 0x04: - printf("FUJITSU "); - break; - case 0x20: - printf("STM "); - break; - case 0xBF: - printf("SST "); - break; - case 0x89: - case 0xB0: - printf("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch ((flash->flash_id) & 0xffff) { - case (uint16_t)AMD_ID_LV800T: - printf ("AM29LV800T\n"); - break; - case (uint16_t)AMD_ID_LV800B: - printf ("AM29LV800B\n"); - break; - case (uint16_t)AMD_ID_LV160T: - printf ("AM29LV160T\n"); - break; - case (uint16_t)AMD_ID_LV160B: - printf ("AM29LV160B\n"); - break; - case (uint16_t)AMD_ID_LV320T: - printf ("AM29LV320T\n"); - break; - case (uint16_t)AMD_ID_LV320B: - printf ("AM29LV320B\n"); - break; - case (uint16_t)INTEL_ID_28F800C3T: - printf ("28F800C3T\n"); - break; - case (uint16_t)INTEL_ID_28F800C3B: - printf ("28F800C3B\n"); - break; - case (uint16_t)INTEL_ID_28F160C3T: - printf ("28F160C3T\n"); - break; - case (uint16_t)INTEL_ID_28F160C3B: - printf ("28F160C3B\n"); - break; - case (uint16_t)INTEL_ID_28F320C3T: - printf ("28F320C3T\n"); - break; - case (uint16_t)INTEL_ID_28F320C3B: - printf ("28F320C3B\n"); - break; - case (uint16_t)INTEL_ID_28F640C3T: - printf ("28F640C3T\n"); - break; - case (uint16_t)INTEL_ID_28F640C3B: - printf ("28F640C3B\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (flash->size >= (1 << 20)) { - printf (" Size: %ld MB in %d Sectors\n", - flash->size >> 20, flash->sector_count); - } else { - printf (" Size: %ld kB in %d Sectors\n", - flash->size >> 10, flash->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i = 0; i < flash->sector_count; ++i) { - /* Check if whole sector is erased*/ - if (i != (flash->sector_count-1)) - size = flash->start[i+1] - flash->start[i]; - else - size = flash->start[0] + flash->size - flash->start[i]; - - erased = 1; - p = (volatile unsigned long *)flash->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - flash->protect[i] ? "RO " : " "); - } - printf ("\n"); -} diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c deleted file mode 100644 index 0b81fc0..0000000 --- a/board/etin/debris/phantom.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * board/eva/phantom.c - * - * Phantom RTC device driver for EVA - * - * Author: Sangmoon Kim - * dogoil@etinsys.com - * - * Copyright 2002 Etinsys Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_DATE) - -#define RTC_BASE (CFG_NVRAM_BASE_ADDR + 0x7fff8) - -#define RTC_YEAR ( RTC_BASE + 7 ) -#define RTC_MONTH ( RTC_BASE + 6 ) -#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 ) -#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 ) -#define RTC_HOURS ( RTC_BASE + 3 ) -#define RTC_MINUTES ( RTC_BASE + 2 ) -#define RTC_SECONDS ( RTC_BASE + 1 ) -#define RTC_CENTURY ( RTC_BASE + 0 ) - -#define RTC_CONTROLA RTC_CENTURY -#define RTC_CONTROLB RTC_SECONDS -#define RTC_CONTROLC RTC_DAY_OF_WEEK - -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 - -#define RTC_CB_OSC_DISABLE 0x80 - -#define RTC_CC_BATTERY_FLAG 0x80 -#define RTC_CC_FREQ_TEST 0x40 - - -static int phantom_flag = -1; -static int century_flag = -1; - -static uchar rtc_read(unsigned int addr) -{ - return *(volatile unsigned char *)(addr); -} - -static void rtc_write(unsigned int addr, uchar val) -{ - *(volatile unsigned char *)(addr) = val; -} - -static unsigned char phantom_rtc_sequence[] = { - 0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c -}; - -static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8]) -{ - int i, j; - unsigned char v; - unsigned char save = rtc_read(addr); - - for (j = 0; j < 8; j++) { - v = phantom_rtc_sequence[j]; - for (i = 0; i < 8; i++) { - rtc_write(addr, v & 1); - v >>= 1; - } - } - for (j = 0; j < 8; j++) { - v = 0; - for (i = 0; i < 8; i++) { - if(rtc_read(addr) & 1) - v |= 1 << i; - } - rtc[j] = v; - } - rtc_write(addr, save); - return rtc; -} - -static void phantom_rtc_write(int addr, unsigned char rtc[8]) -{ - int i, j; - unsigned char v; - unsigned char save = rtc_read(addr); - for (j = 0; j < 8; j++) { - v = phantom_rtc_sequence[j]; - for (i = 0; i < 8; i++) { - rtc_write(addr, v & 1); - v >>= 1; - } - } - for (j = 0; j < 8; j++) { - v = rtc[j]; - for (i = 0; i < 8; i++) { - rtc_write(addr, v & 1); - v >>= 1; - } - } - rtc_write(addr, save); -} - -static int get_phantom_flag(void) -{ - int i; - unsigned char rtc[8]; - - phantom_rtc_read(RTC_BASE, rtc); - - for(i = 1; i < 8; i++) { - if (rtc[i] != rtc[0]) - return 1; - } - return 0; -} - -void rtc_reset(void) -{ - if (phantom_flag < 0) - phantom_flag = get_phantom_flag(); - - if (phantom_flag) { - unsigned char rtc[8]; - phantom_rtc_read(RTC_BASE, rtc); - if(rtc[4] & 0x30) { - printf( "real-time-clock was stopped. Now starting...\n" ); - rtc[4] &= 0x07; - phantom_rtc_write(RTC_BASE, rtc); - } - } else { - uchar reg_a, reg_b, reg_c; - reg_a = rtc_read( RTC_CONTROLA ); - reg_b = rtc_read( RTC_CONTROLB ); - - if ( reg_b & RTC_CB_OSC_DISABLE ) - { - printf( "real-time-clock was stopped. Now starting...\n" ); - reg_a |= RTC_CA_WRITE; - reg_b &= ~RTC_CB_OSC_DISABLE; - rtc_write( RTC_CONTROLA, reg_a ); - rtc_write( RTC_CONTROLB, reg_b ); - } - - /* make sure read/write clock register bits are cleared */ - reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); - rtc_write( RTC_CONTROLA, reg_a ); - - reg_c = rtc_read( RTC_CONTROLC ); - if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 ) - printf( "RTC battery low. Clock setting may not be reliable.\n"); - } -} - -inline unsigned bcd2bin (uchar n) -{ - return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); -} - -inline unsigned char bin2bcd (unsigned int n) -{ - return (((n / 10) << 4) | (n % 10)); -} - -static int get_century_flag(void) -{ - int flag = 0; - int bcd, century; - bcd = rtc_read( RTC_CENTURY ); - century = bcd2bin( bcd & 0x3F ); - rtc_write( RTC_CENTURY, bin2bcd(century+1)); - if (bcd == rtc_read( RTC_CENTURY )) - flag = 1; - rtc_write( RTC_CENTURY, bcd); - return flag; -} - -void rtc_get( struct rtc_time *tmp) -{ - if (phantom_flag < 0) - phantom_flag = get_phantom_flag(); - - if (phantom_flag) - { - unsigned char rtc[8]; - - phantom_rtc_read(RTC_BASE, rtc); - - tmp->tm_sec = bcd2bin(rtc[1] & 0x7f); - tmp->tm_min = bcd2bin(rtc[2] & 0x7f); - tmp->tm_hour = bcd2bin(rtc[3] & 0x1f); - tmp->tm_wday = bcd2bin(rtc[4] & 0x7); - tmp->tm_mday = bcd2bin(rtc[5] & 0x3f); - tmp->tm_mon = bcd2bin(rtc[6] & 0x1f); - tmp->tm_year = bcd2bin(rtc[7]) + 1900; - tmp->tm_yday = 0; - tmp->tm_isdst = 0; - - if( (rtc[3] & 0x80) && (rtc[3] & 0x40) ) tmp->tm_hour += 12; - if (tmp->tm_year < 1970) tmp->tm_year += 100; - } else { - uchar sec, min, hour; - uchar mday, wday, mon, year; - - int century; - - uchar reg_a; - - if (century_flag < 0) - century_flag = get_century_flag(); - - reg_a = rtc_read( RTC_CONTROLA ); - /* lock clock registers for read */ - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); - - sec = rtc_read( RTC_SECONDS ); - min = rtc_read( RTC_MINUTES ); - hour = rtc_read( RTC_HOURS ); - mday = rtc_read( RTC_DAY_OF_MONTH ); - wday = rtc_read( RTC_DAY_OF_WEEK ); - mon = rtc_read( RTC_MONTH ); - year = rtc_read( RTC_YEAR ); - century = rtc_read( RTC_CENTURY ); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); - - tmp->tm_sec = bcd2bin( sec & 0x7F ); - tmp->tm_min = bcd2bin( min & 0x7F ); - tmp->tm_hour = bcd2bin( hour & 0x3F ); - tmp->tm_mday = bcd2bin( mday & 0x3F ); - tmp->tm_mon = bcd2bin( mon & 0x1F ); - tmp->tm_wday = bcd2bin( wday & 0x07 ); - - if (century_flag) { - tmp->tm_year = bcd2bin( year ) + - ( bcd2bin( century & 0x3F ) * 100 ); - } else { - tmp->tm_year = bcd2bin( year ) + 1900; - if (tmp->tm_year < 1970) tmp->tm_year += 100; - } - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - } -} - -void rtc_set( struct rtc_time *tmp ) -{ - if (phantom_flag < 0) - phantom_flag = get_phantom_flag(); - - if (phantom_flag) { - uint year; - unsigned char rtc[8]; - - year = tmp->tm_year; - year -= (year < 2000) ? 1900 : 2000; - - rtc[0] = bin2bcd(0); - rtc[1] = bin2bcd(tmp->tm_sec); - rtc[2] = bin2bcd(tmp->tm_min); - rtc[3] = bin2bcd(tmp->tm_hour); - rtc[4] = bin2bcd(tmp->tm_wday); - rtc[5] = bin2bcd(tmp->tm_mday); - rtc[6] = bin2bcd(tmp->tm_mon); - rtc[7] = bin2bcd(year); - - phantom_rtc_write(RTC_BASE, rtc); - } else { - uchar reg_a; - if (century_flag < 0) - century_flag = get_century_flag(); - - /* lock clock registers for write */ - reg_a = rtc_read( RTC_CONTROLA ); - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); - - rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); - - rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); - rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); - rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); - rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); - rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); - - /* break year up into century and year in century */ - if (century_flag) { - rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); - rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 )); - reg_a &= 0xc0; - reg_a |= bin2bcd( tmp->tm_year / 100 ); - } else { - rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year - - ((tmp->tm_year < 2000) ? 1900 : 2000))); - } - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); - } -} - -#endif diff --git a/board/etin/debris/speed.h b/board/etin/debris/speed.h deleted file mode 100644 index b66393b..0000000 --- a/board/etin/debris/speed.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/etin/debris/u-boot.lds b/board/etin/debris/u-boot.lds deleted file mode 100644 index c742bcd..0000000 --- a/board/etin/debris/u-boot.lds +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/etx094/Makefile b/board/etx094/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/etx094/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/etx094/config.mk b/board/etx094/config.mk deleted file mode 100644 index 655c2db..0000000 --- a/board/etx094/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# ETX_094 Boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c deleted file mode 100644 index dba3c11..0000000 --- a/board/etx094/etx094.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static void read_hw_vers (void); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - - /* single read (offset 0x00 in upm ram) */ - - 0xEECEFC24, 0x100DFC24, 0xE02FBC04, 0x01AA7C04, - 0x1FB5FC00, 0xFFFFFC05, _NOT_USED_, _NOT_USED_, - - /* burst read (offset 0x08 in upm ram) */ - - 0xEECEFC24, 0x100DFC24, 0xE0FFBC04, 0x10FF7C04, - 0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC00, 0xFFFFFC00, - 0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write (offset 0x18 in upm ram) */ - - 0xEECEFC24, 0x100DFC24, 0xE02BBC04, 0x01A27C00, - 0xEFAAFC04, 0x1FB5FC05, _NOT_USED_, _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - - 0xEECEFC24, 0x103DFC24, 0xE0FBBC00, 0x10F77C00, - 0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC04, 0xFFFFFC05, - - /* init part1 (offset 0x28 in upm ram) */ - - 0xEFFAFC3C, 0x1FF4FC34, 0xEFFCBC34, 0x1FFC3C34, - 0xFFFC3C35, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* refresh (offset 0x30 in upm ram) */ - - 0xEFFEBC0C, 0x1FFD7C04, 0xFFFFFC04, 0xFFFFFC05, - - /* init part2 (offset 0x34 in upm ram) */ - - 0xFFFEBC04, 0xEFFC3CB4, 0x1FFC3C34, 0xFFFC3C34, - 0xFFFC3C34, 0xEFE83CB4, 0x1FB57C35, _NOT_USED_, - - /* exception (offset 0x3C in upm ram) */ - - 0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_, - -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ETX ID string (ETX_xxx...) - * - * Return 1 always. - */ - -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - char *s = getenv ("serial#"); - char *e; - - puts ("Board: "); - -#ifdef SB_ETX094 - gd->board_type = 0; /* 0 = 2SDRAM-Device */ -#else - gd->board_type = 1; /* 1 = 1SDRAM-Device */ -#endif - - if (!s || strncmp (s, "ETX_", 4)) { - puts ("### No HW ID - assuming ETX_094\n"); - read_hw_vers (); - return (0); - } - - for (e = s; *e; ++e) { - if (*e == ' ') - break; - } - - for (; s < e; ++s) { - putc (*s); - } - putc ('\n'); - - read_hw_vers (); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size_b1, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_1BK_4K; /* MPTPR_PTP_DIV32 0x0200 */ - - /* A3(SDRAM)=0 => Bursttype = Sequential - * A2-A0(SDRAM)=010 => Burst length = 4 - * A4-A6(SDRAM)=010 => CasLat=2 - */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; - - if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - } - - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004128; /* SDRAM bank 0 (CS2) - Init Part 1 */ - memctl->memc_mcr = 0x80004734; /* SDRAM bank 0 (CS2) - Init Part 2 */ - udelay (1); - - if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ - memctl->memc_mcr = 0x80006128; /* SDRAM bank 1 (CS3) - Init Part 1 */ - memctl->memc_mcr = 0x80006734; /* SDRAM bank 1 (CS3) - Init Part 2 */ - udelay (1); - } - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ - /* - * Check Bank 1 Memory Size - * use current column settings - * [9 column SDRAM may also be used in 8 column mode, - * but then only half the real size will be used.] - */ - size_b1 = - dram_size (memctl->memc_mamr, (long *) SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); -/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */ - } else { - size_b1 = 0; - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /*DIV16 */ - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - - memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b0 > 0) { - /* - * Position Bank 0 immediately above Bank 1 - */ - memctl->memc_or2 = - ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b1; - } else { - unsigned long reg; - - /* - * No bank 0 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - } else { /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or3 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b0; - } else { - unsigned long reg; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - } - - udelay (10000); - - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -/* HW-ID Table (Bits: 2^9;2^7;2^5) */ -#define HW_ID_0 0x0000 -#define HW_ID_1 0x0020 -#define HW_ID_2 0x0080 -#define HW_ID_3 0x00a0 -#define HW_ID_4 0x0200 -#define HW_ID_5 0x0220 -#define HW_ID_6 0x0280 -#define HW_ID_7 0x02a0 - -void read_hw_vers () -{ - unsigned short rd_msk = 0x02A0; - - /* HW-ID pin-definition */ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - immr->im_ioport.iop_pddir &= ~(rd_msk); - immr->im_ioport.iop_pdpar &= ~(rd_msk); - - /* debug printf("State of PD: %x\n",immr->im_ioport.iop_pddat); */ - - /* Check the HW-ID */ - printf ("HW-Version: "); - switch (immr->im_ioport.iop_pddat & rd_msk) { - case HW_ID_0: - printf ("V0.1 - V0.3 / W97238-Q3162-A1-1-2\n"); - break; - case HW_ID_1: - printf ("V0.9 / W50037-Q1-D6-1\n"); - break; - case HW_ID_2: - printf ("NOT USED - assuming ID#2\n"); - break; - case HW_ID_3: - printf ("NOT USED - assuming ID#3\n"); - break; - case HW_ID_4: - printf ("NOT USED - assuming ID#4\n"); - break; - case HW_ID_5: - printf ("NOT USED - assuming ID#5\n"); - break; - case HW_ID_6: - printf ("NOT USED - assuming ID#6\n"); - break; - case HW_ID_7: - printf ("NOT USED - assuming ID#7\n"); - break; - default: - printf ("###Error###\n"); - break; - } -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/etx094/flash.c b/board/etx094/flash.c deleted file mode 100644 index 98a7c0c..0000000 --- a/board/etx094/flash.c +++ /dev/null @@ -1,744 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); -#ifdef CONFIG_FLASH_16BIT - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */ -#else - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; -#endif - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); -#ifdef CONFIG_FLASH_16BIT - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V | BR_PS_16; -#else - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; -#endif - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00002000); - } - return; - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ -#ifdef CONFIG_FLASH_16BIT - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; -#else - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; -#endif - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n"); - break; - case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n"); - break; - case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n"); - break; - case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ -#ifdef CONFIG_FLASH_16BIT - vu_short *s_addr = (vu_short*)addr; - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x0090; - value = s_addr[0]; - value = value|(value<<16); -#else - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - addr[0x5555] = 0x00900090; - value = addr[0]; -#endif - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } -#ifdef CONFIG_FLASH_16BIT - value = s_addr[1]; - value = value|(value<<16); -#else - value = addr[1]; /* device ID */ -#endif - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; -#ifdef CONFIG_FLASH_16BIT - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MB */ -#else - info->sector_count = 19; - info->size = 0x00200000; /* => 2 MB */ -#endif - break; - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; -#ifdef CONFIG_FLASH_16BIT - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MB */ -#else - info->sector_count = 35; - info->size = 0x00400000; /* => 4 MB */ -#endif - - break; -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case SST_ID_xF200A: - info->flash_id += FLASH_SST200A; - info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */ - info->size = 0x00080000; - break; - case SST_ID_xF400A: - info->flash_id += FLASH_SST400A; - info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */ - info->size = 0x00100000; - break; - case SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */ - info->size = 0x00200000; - break; /* => 2 MB */ - case STM_ID_x800AB: - info->flash_id += FLASH_STM800AB; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00002000); - } - } else { /* AMD and Fujitsu types */ - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ -#ifdef CONFIG_FLASH_16BIT - - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; -#else - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; -#endif - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address: - * (A7 .. A0) = 0x02 - * D0 = 1 if protected - */ -#ifdef CONFIG_FLASH_16BIT - s_addr = (volatile unsigned short *)(info->start[i]); - info->protect[i] = s_addr[2] & 1; -#else - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; -#endif - } - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { -#ifdef CONFIG_FLASH_16BIT - s_addr = (volatile unsigned short *)(info->start[0]); - *s_addr = 0x00F0; /* reset bank */ -#else - addr = (volatile unsigned long *)info->start[0]; - *addr = 0x00F000F0; /* reset bank */ -#endif - - } - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect; - ulong start, now, last; -#ifdef CONFIG_FLASH_16BIT - vu_short *s_addr = (vu_short*)addr; -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } -/*#ifndef CONFIG_FLASH_16BIT - ulong type; - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return; - } -#endif*/ - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ -#ifdef CONFIG_FLASH_16BIT - vu_short *s_sect_addr = (vu_short*)(info->start[sect]); -#else - vu_long *sect_addr = (vu_long*)(info->start[sect]); -#endif - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#ifdef CONFIG_FLASH_16BIT - - /*printf("\ns_sect_addr=%x",s_sect_addr);*/ - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x0080; - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_sect_addr[0] = 0x0030; -#else - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - addr[0x5555] = 0x00800080; - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - sect_addr[0] = 0x00300030; -#endif - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#ifdef CONFIG_FLASH_16BIT - while ((s_sect_addr[0] & 0x0080) != 0x0080) { -#else - while ((sect_addr[0] & 0x00800080) != 0x00800080) { -#endif - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - } - } - - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#ifdef CONFIG_FLASH_16BIT - s_addr[0] = 0x00F0; /* reset bank */ -#else - addr[0] = 0x00F000F0; /* reset bank */ -#endif - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - -#ifdef CONFIG_FLASH_16BIT - vu_short high_data; - vu_short low_data; - vu_short *s_addr = (vu_short*)addr; -#endif - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - -#ifdef CONFIG_FLASH_16BIT - /* Write the 16 higher-bits */ - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - high_data = ((data>>16) & 0x0000ffff); - - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x00A0; - - *((vu_short *)dest) = high_data; - - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - - /* Write the 16 lower-bits */ -#endif - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); -#ifdef CONFIG_FLASH_16BIT - dest += 0x2; - low_data = (data & 0x0000ffff); - - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x00A0; - *((vu_short *)dest) = low_data; - -#else - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - addr[0x5555] = 0x00A000A0; - *((vu_long *)dest) = data; -#endif - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - -#ifdef CONFIG_FLASH_16BIT - while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) { -#else - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { -#endif - - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds deleted file mode 100644 index c50db8f..0000000 --- a/board/etx094/u-boot.lds +++ /dev/null @@ -1,143 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - cpu/mpc8xx/interrupts.o (.text) - cpu/mpc8xx/serial.o (.text) - cpu/mpc8xx/cpu_init.o (.text) - cpu/mpc8xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/etx094/u-boot.lds.debug b/board/etx094/u-boot.lds.debug deleted file mode 100644 index e4d8b10..0000000 --- a/board/etx094/u-boot.lds.debug +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - cpu/mpc8xx/interrupts.o (.text) - cpu/mpc8xx/cpu.o (.text) - cpu/mpc8xx/cpu_init.o (.text) - cpu/mpc8xx/speed.o (.text) - cpu/mpc8xx/serial.o (.text) - lib_ppc/extable.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/string.o (.text) - lib_generic/crc32.o (.text) - common/dlmalloc.o (.text) - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/evb4510/Makefile b/board/evb4510/Makefile deleted file mode 100644 index 10850a9..0000000 --- a/board/evb4510/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := evb4510.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/evb4510/config.mk b/board/evb4510/config.mk deleted file mode 100644 index 4d1a019..0000000 --- a/board/evb4510/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (c) 2004 Cucy Systems (http://www.cucy.com) -# Curt Brune -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x007d0000 diff --git a/board/evb4510/evb4510.c b/board/evb4510/evb4510.c deleted file mode 100644 index 0008e5a..0000000 --- a/board/evb4510/evb4510.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_EVB4510 - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - icache_enable(); - - /* address for the kernel command line */ - gd->bd->bi_boot_params = 0x800; - - /* enable board LEDs for output */ - PUT_REG( REG_IOPDATA, 0x0); - PUT_REG( REG_IOPMODE, 0xFFFF); - PUT_REG( REG_IOPDATA, 0xFF); - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -#if CONFIG_NR_DRAM_BANKS == 2 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif - return 0; -} - -#endif diff --git a/board/evb4510/flash.c b/board/evb4510/flash.c deleted file mode 100644 index aff92f9..0000000 --- a/board/evb4510/flash.c +++ /dev/null @@ -1,539 +0,0 @@ -/* - * - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -typedef enum { - FLASH_DEV_U9_512KB = 0, - FLASH_DEV_U7_2MB = 1 -} FLASH_DEV; - -#define FLASH_DQ7 (0x80) -#define FLASH_DQ5 (0x20) - -#define PROG_ADDR (0xAAA) -#define SETUP_ADDR (0xAAA) -#define ID_ADDR (0xAAA) -#define UNLOCK_ADDR1 (0xAAA) -#define UNLOCK_ADDR2 (0x555) - -#define UNLOCK_CMD1 (0xAA) -#define UNLOCK_CMD2 (0x55) -#define ERASE_SUSPEND_CMD (0xB0) -#define ERASE_RESUME_CMD (0x30) -#define RESET_CMD (0xF0) -#define ID_CMD (0x90) -#define SELECT_CMD (0x90) -#define CHIPERASE_CMD (0x10) -#define BYPASS_CMD (0x20) -#define SECERASE_CMD (0x30) -#define PROG_CMD (0xa0) -#define SETUP_CMD (0x80) - -#if 0 -#define WRITE_UNLOCK(addr) { \ - PUT__U8( addr + UNLOCK_ADDR1, UNLOCK_CMD1); \ - PUT__U8( addr + UNLOCK_ADDR2, UNLOCK_CMD2); \ -} - -/* auto select command */ -#define CMD_ID(addr) WRITE_UNLOCK(addr); { \ - PUT__U8( addr + ID_ADDR, ID_CMD); \ -} - -#define CMD_RESET(addr) WRITE_UNLOCK(addr); { \ - PUT__U8( addr + ID_ADDR, RESET_CMD); \ -} - -#define CMD_ERASE_SEC(base, addr) WRITE_UNLOCK(base); \ - PUT__U8( base + SETUP_ADDR, SETUP_CMD); \ - WRITE_UNLOCK(base); \ - PUT__U8( addr, SECERASE_CMD); - -#define CMD_ERASE_CHIP(base) WRITE_UNLOCK(base); \ - PUT__U8( base + SETUP_ADDR, SETUP_CMD); \ - WRITE_UNLOCK(base); \ - PUT__U8( base + SETUP_ADDR, CHIPERASE_CMD); - -/* prepare for bypass programming */ -#define CMD_UNLOCK_BYPASS(addr) WRITE_UNLOCK(addr); { \ - PUT__U8( addr + ID_ADDR, 0x20); \ -} - -/* terminate bypass programming */ -#define CMD_BYPASS_RESET(addr) { \ - PUT__U8(addr, 0x90); \ - PUT__U8(addr, 0x00); \ -} -#endif - -inline static void FLASH_CMD_UNLOCK (FLASH_DEV dev, u32 base) -{ - switch (dev) { - case FLASH_DEV_U7_2MB: - PUT__U8 (base + 0xAAA, 0xAA); - PUT__U8 (base + 0x555, 0x55); - break; - case FLASH_DEV_U9_512KB: - PUT__U8 (base + 0x555, 0xAA); - PUT__U8 (base + 0x2AA, 0x55); - break; - } -} - -inline static void FLASH_CMD_SELECT (FLASH_DEV dev, u32 base) -{ - switch (dev) { - case FLASH_DEV_U7_2MB: - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base + 0xAAA, SELECT_CMD); - break; - case FLASH_DEV_U9_512KB: - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base + 0x555, SELECT_CMD); - break; - } -} - -inline static void FLASH_CMD_RESET (FLASH_DEV dev, u32 base) -{ - switch (dev) { - case FLASH_DEV_U7_2MB: - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base + 0xAAA, RESET_CMD); - break; - case FLASH_DEV_U9_512KB: - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base + 0x555, RESET_CMD); - break; - } -} - -inline static void FLASH_CMD_ERASE_SEC (FLASH_DEV dev, u32 base, u32 addr) -{ - switch (dev) { - case FLASH_DEV_U7_2MB: - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base + 0xAAA, SETUP_CMD); - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (addr, SECERASE_CMD); - break; - case FLASH_DEV_U9_512KB: - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base + 0x555, SETUP_CMD); - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (addr, SECERASE_CMD); - break; - } -} - -inline static void FLASH_CMD_ERASE_CHIP (FLASH_DEV dev, u32 base) -{ - switch (dev) { - case FLASH_DEV_U7_2MB: - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base + 0xAAA, SETUP_CMD); - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base, CHIPERASE_CMD); - break; - case FLASH_DEV_U9_512KB: - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base + 0x555, SETUP_CMD); - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base, CHIPERASE_CMD); - break; - } -} - -inline static void FLASH_CMD_UNLOCK_BYPASS (FLASH_DEV dev, u32 base) -{ - switch (dev) { - case FLASH_DEV_U7_2MB: - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base + 0xAAA, BYPASS_CMD); - break; - case FLASH_DEV_U9_512KB: - FLASH_CMD_UNLOCK (dev, base); - PUT__U8 (base + 0x555, BYPASS_CMD); - break; - } -} - -inline static void FLASH_CMD_BYPASS_RESET (FLASH_DEV dev, u32 base) -{ - PUT__U8 (base, SELECT_CMD); - PUT__U8 (base, 0x0); -} - -/* poll for flash command completion */ -static u16 _flash_poll (FLASH_DEV dev, u32 addr, u16 data, ulong timeOut) -{ - u32 done = 0; - ulong t0; - - u16 error = 0; - volatile u16 flashData; - - data = data & 0xFF; - t0 = get_timer (0); - while (get_timer (t0) < timeOut) { - /* for( i = 0; i < POLL_LOOPS; i++) { */ - /* Read the Data */ - flashData = GET__U8 (addr); - - /* FLASH_DQ7 = Data? */ - if ((flashData & FLASH_DQ7) == (data & FLASH_DQ7)) { - done = 1; - break; - } - - /* Check Timeout (FLASH_DQ5==1) */ - if (flashData & FLASH_DQ5) { - /* Read the Data */ - flashData = GET__U8 (addr); - - /* FLASH_DQ7 = Data? */ - if (!((flashData & FLASH_DQ7) == (data & FLASH_DQ7))) { - printf ("_flash_poll(): FLASH_DQ7 & flashData not equal to write value\n"); - error = ERR_PROG_ERROR; - } - FLASH_CMD_RESET (dev, addr); - done = 1; - break; - } - /* spin delay */ - udelay (10); - } - - - /* error update */ - if (!done) { - printf ("_flash_poll(): Timeout\n"); - error = ERR_TIMOUT; - } - - /* Check the data */ - if (!error) { - /* Read the Data */ - flashData = GET__U8 (addr); - if (flashData != data) { - error = ERR_PROG_ERROR; - printf ("_flash_poll(): flashData(0x%04x) not equal to data(0x%04x)\n", - flashData, data); - } - } - - return error; -} - -/*----------------------------------------------------------------------- - */ -static int _flash_check_protection (flash_info_t * info, int s_first, int s_last) -{ - int sect, prot = 0; - - for (sect = s_first; sect <= s_last; sect++) - if (info->protect[sect]) { - printf (" Flash sector %d protected.\n", sect); - prot++; - } - return prot; -} - -static int _detectFlash (FLASH_DEV dev, u32 base, u8 venId, u8 devId) -{ - - u32 baseAddr = base | CACHE_DISABLE_MASK; - u8 vendorId, deviceId; - - /* printf(__FUNCTION__"(): detecting flash @ 0x%08x\n", base); */ - - /* Send auto select command and read manufacturer info */ - FLASH_CMD_SELECT (dev, baseAddr); - vendorId = GET__U8 (baseAddr); - FLASH_CMD_RESET (dev, baseAddr); - - /* Send auto select command and read device info */ - FLASH_CMD_SELECT (dev, baseAddr); - - if (dev == FLASH_DEV_U7_2MB) { - deviceId = GET__U8 (baseAddr + 2); - } else if (dev == FLASH_DEV_U9_512KB) { - deviceId = GET__U8 (baseAddr + 1); - } else { - return 0; - } - - FLASH_CMD_RESET (dev, baseAddr); - - /* printf (__FUNCTION__"(): found vendorId 0x%04x, deviceId 0x%04x\n", - vendorId, deviceId); - */ - - return (vendorId == venId) && (deviceId == devId); - -} - -/****************************************************************************** - * - * Public u-boot interface functions below - * - *****************************************************************************/ - -/*************************************************************************** - * - * Flash initialization - * - * This board has two banks of flash, but the base addresses depend on - * how the board is jumpered. - * - * The two flash types are: - * - * AMD Am29LV160DB (2MB) sectors layout 16KB, 2x8KB, 32KB, 31x64KB - * - * AMD Am29LV040B (512KB) sectors: 8x64KB - *****************************************************************************/ - -unsigned long flash_init (void) -{ - flash_info_t *info; - u16 i; - u32 flashtest; - s16 amd160 = -1; - u32 amd160base = 0; - -#if CFG_MAX_FLASH_BANKS == 2 - s16 amd040 = -1; - u32 amd040base = 0; -#endif - - /* configure PHYS_FLASH_1 */ - if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_1, 0x1, 0x49)) { - amd160 = 0; - amd160base = PHYS_FLASH_1; -#if CFG_MAX_FLASH_BANKS == 1 - } -#else - if (_detectFlash - (FLASH_DEV_U9_512KB, PHYS_FLASH_2, 0x1, 0x4F)) { - amd040 = 1; - amd040base = PHYS_FLASH_2; - } else { - printf (__FUNCTION__ - "(): Unable to detect PHYS_FLASH_2: 0x%08x\n", - PHYS_FLASH_2); - } - } else if (_detectFlash (FLASH_DEV_U9_512KB, PHYS_FLASH_1, 0x1, 0x4F)) { - amd040 = 0; - amd040base = PHYS_FLASH_1; - if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_2, 0x1, 0x49)) { - amd160 = 1; - amd160base = PHYS_FLASH_2; - } else { - printf (__FUNCTION__ - "(): Unable to detect PHYS_FLASH_2: 0x%08x\n", - PHYS_FLASH_2); - } - } -#endif - else { - printf ("flash_init(): Unable to detect PHYS_FLASH_1: 0x%08x\n", - PHYS_FLASH_1); - } - - /* Configure AMD Am29LV160DB (2MB) */ - info = &flash_info[amd160]; - info->flash_id = FLASH_DEV_U7_2MB; - info->sector_count = 35; - info->size = 2 * 1024 * 1024; /* 2MB */ - /* 1*16K Boot Block - 2*8K Parameter Block - 1*32K Small Main Block */ - info->start[0] = amd160base; - info->start[1] = amd160base + 0x4000; - info->start[2] = amd160base + 0x6000; - info->start[3] = amd160base + 0x8000; - for (i = 1; i < info->sector_count; i++) - info->start[3 + i] = amd160base + i * (64 * 1024); - - for (i = 0; i < info->sector_count; i++) { - /* Write auto select command sequence and query sector protection */ - FLASH_CMD_SELECT (info->flash_id, - info->start[i] | CACHE_DISABLE_MASK); - flashtest = - GET__U8 (((info->start[i] + 4) | CACHE_DISABLE_MASK)); - FLASH_CMD_RESET (info->flash_id, - amd160base | CACHE_DISABLE_MASK); - info->protect[i] = (flashtest & 0x0001); - } - - /* - * protect monitor and environment sectors in 2MB flash - */ - flash_protect (FLAG_PROTECT_SET, - amd160base, amd160base + monitor_flash_len - 1, info); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SIZE - 1, info); - -#if CFG_MAX_FLASH_BANKS == 2 - /* Configure AMD Am29LV040B (512KB) */ - info = &flash_info[amd040]; - info->flash_id = FLASH_DEV_U9_512KB; - info->sector_count = 8; - info->size = 512 * 1024; /* 512KB, 8 x 64KB */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = amd040base + i * (64 * 1024); - /* Write auto select command sequence and query sector protection */ - FLASH_CMD_SELECT (info->flash_id, - info->start[i] | CACHE_DISABLE_MASK); - flashtest = - GET__U8 (((info->start[i] + 2) | CACHE_DISABLE_MASK)); - FLASH_CMD_RESET (info->flash_id, - amd040base | CACHE_DISABLE_MASK); - info->protect[i] = (flashtest & 0x0001); - } -#endif - - return flash_info[0].size -#if CFG_MAX_FLASH_BANKS == 2 - + flash_info[1].size -#endif - ; -} - -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_DEV_U7_2MB) { - printf ("AMD Am29LV160DB (2MB) 16KB,2x8KB,32KB,31x64KB\n"); - } else if (info->flash_id == FLASH_DEV_U9_512KB) { - printf ("AMD Am29LV040B (512KB) 8x64KB\n"); - } else { - printf ("Unknown flash_id ...\n"); - return; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 4) == 0) - printf ("\n "); - printf (" S%02d @ 0x%08lX%s", i, - info->start[i], info->protect[i] ? " !" : " "); - } - printf ("\n"); -} - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - u16 i, error = 0; - - printf ("\n"); - - /* check flash protection bits */ - if (_flash_check_protection (info, s_first, s_last)) { - printf (" Flash erase aborted due to protected sectors\n"); - return ERR_PROTECTED; - } - - if ((s_first < info->sector_count) && (s_first <= s_last)) { - for (i = s_first; i <= s_last && !error; i++) { - printf (" Erasing Sector %d @ 0x%08lx ... ", i, - info->start[i]); - /* bypass the cache to access the flash memory */ - FLASH_CMD_ERASE_SEC (info->flash_id, - (info-> - start[0] | CACHE_DISABLE_MASK), - (info-> - start[i] | CACHE_DISABLE_MASK)); - /* look for sector to become 0xFF after erase */ - error = _flash_poll (info->flash_id, - info-> - start[i] | CACHE_DISABLE_MASK, - 0xFF, CFG_FLASH_ERASE_TOUT); - FLASH_CMD_RESET (info->flash_id, - (info-> - start[0] | CACHE_DISABLE_MASK)); - printf ("done\n"); - if (error) { - break; - } - } - } else - error = ERR_INVAL; - - return error; -} - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - u16 error = 0, i; - u32 n; - u8 *bp, *bps; - - /* Write Setup */ - /* bypass the cache to access the flash memory */ - FLASH_CMD_UNLOCK_BYPASS (info->flash_id, - (info->start[0] | CACHE_DISABLE_MASK)); - - /* Write the Data to Flash */ - - bp = (u8 *) (addr | CACHE_DISABLE_MASK); - bps = (u8 *) src; - - for (n = 0; n < cnt && !error; n++, bp++, bps++) { - - if (!(n % (cnt / 15))) { - printf ("."); - } - - /* write the flash command for flash memory */ - *bp = 0xA0; - - /* Write the data */ - *bp = *bps; - - /* Check if the write is done */ - for (i = 0; i < 0xff; i++); - error = _flash_poll (info->flash_id, (u32) bp, *bps, - CFG_FLASH_WRITE_TOUT); - if (error) { - return error; - } - } - - /* Reset the Flash Mode to read */ - FLASH_CMD_BYPASS_RESET (info->flash_id, info->start[0]); - - printf (" "); - - return error; -} diff --git a/board/evb4510/lowlevel_init.S b/board/evb4510/lowlevel_init.S deleted file mode 100644 index 7184d72..0000000 --- a/board/evb4510/lowlevel_init.S +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include - -/*********************************************************************** - * Configure Memory Map - * - * This memory map allows us to relocate from FLASH to SRAM. After - * power-on reset the CPU only knows about the FLASH memory at address - * 0x00000000. After lowlevel_init completes the memory map will be: - * - * Memory Addr - * 0x00000000 - * to 8MB SRAM (U5) -- 8MB Map - * 0x00800000 - * - * 0x01000000 - * to 2MB Flash @ 0x00000000 (U7) -- 2MB Map - * 0x01200000 - * - * 0x02000000 - * to 512KB Flash @ 0x02000000 (U9) -- 2MB Map - * 0x02080000 - * - * Load all 12 memory registers with the STMIA instruction since - * memory access is disabled once these registers are written. The - * last register written re-enables memory access. For more info see - * the user's manual for the S3C4510B, available from Samsung's web - * site. Search for part number "S3C4510B". - * - ***********************************************************************/ - -.globl lowlevel_init -lowlevel_init: - - /* preserve the temp register (r12 AKA ip) and remap it. */ - ldr r1, =SRAM_BASE+0xC - add r0, r12, #0x01000000 - str r0, [r1] - - /* remap the link register for when we return */ - add lr, lr, #0x01000000 - - /* store a short program in the on chip SRAM, which is - * unaffected when remapping memory. Note the cache must be - * disabled for the on chip SRAM to be available. - */ - ldr r1, =SRAM_BASE - ldr r0, =0xe8801ffe /* stmia r0, {r1-r12} */ - str r0, [r1] - add r1, r1, #4 - ldr r0, =0xe59fc000 /* ldr r12, [pc, #0] */ - str r0, [r1] - add r1, r1, #4 - ldr r0, =0xe1a0f00e /* mov pc, lr */ - str r0, [r1] - - adr r0, memory_map_data - ldmia r0, {r1-r12} - ldr r0, =REG_EXTDBWTH - - ldr pc, =SRAM_BASE - -.globl reset_cpu -reset_cpu: - /* - * reset the cpu by re-mapping FLASH 0 to 0x0 and jumping to - * address 0x0. We accomplish this by storing a few - * instructions into the on chip SRAM (8KB) and run from - * there. Note the cache must be disabled for the on chip - * SRAM to be available. - * - * load r2 with REG_ROMCON0 - * load r3 with 0x12040060 configure FLASH bank 0 @ 0x00000000 - * load r4 with REG_DRAMCON0 - * load r5 with 0x08000380 configure RAM bank 0 @ 0x01000000 - * load r6 with REG_REFEXTCON - * load r7 with 0x9c218360 - * load r8 with 0x0 - * store str r3,[r2] @ SRAM_BASE - * store str r5,[r4] @ SRAM_BASE + 0x4 - * store str r7,[r6] @ SRAM_BASE + 0x8 - * store mov pc,r8 @ SRAM_BASE + 0xC - * mov pc, SRAM_BASE - * - */ - - /* disable cache */ - ldr r0, =REG_SYSCFG - ldr r1, =0x83ffffa0 /* cache-disabled */ - str r1, [r0] - - ldr r2, =REG_ROMCON0 - ldr r3, =0x02000060 /* Bank0 2MB FLASH @ 0x00000000 */ - ldr r4, =REG_DRAMCON0 - ldr r5, =0x18040380 /* DRAM0 8MB SRAM @ 0x01000000 */ - ldr r6, =REG_REFEXTCON - ldr r7, =0xce278360 - ldr r8, =0x00000000 - ldr r1, =SRAM_BASE - ldr r0, =0xe5823000 /* str r3, [r2] */ - str r0, [r1] - ldr r1, =SRAM_BASE+4 - ldr r0, =0xe5845000 /* str r5, [r4] */ - str r0, [r1] - ldr r1, =SRAM_BASE+8 - ldr r0, =0xe5867000 /* str r7, [r6] */ - str r0, [r1] - ldr r1, =SRAM_BASE+0xC - ldr r0, =0xe1a0f008 /* mov pc, r8 */ - str r0, [r1] - ldr r1, =SRAM_BASE - mov pc, r1 - - /* never return */ - -/************************************************************************ - * Below are twelve 32-bit values for the twelve memory registers of - * the system manager, starting with register REG_EXTDBWTH. - ***********************************************************************/ -memory_map_data: - .long 0x00f03005 /* memory widths */ - .long 0x12040060 /* Bank0 2MB FLASH @ 0x01000000 */ - .long 0x22080060 /* Bank1 512KB FLASH @ 0x02000000 */ - .long 0x00000000 - .long 0x00000000 - .long 0x00000000 - .long 0x00000000 - .long 0x08000380 /* DRAM0 8MB SRAM @ 0x00000000 */ - .long 0x00000000 - .long 0x00000000 - .long 0x00000000 - .long 0x9c218360 /* enable memory */ diff --git a/board/evb4510/u-boot.lds b/board/evb4510/u-boot.lds deleted file mode 100644 index 5b70a40..0000000 --- a/board/evb4510/u-boot.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm720t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/board/evb64260/64260.h b/board/evb64260/64260.h deleted file mode 100644 index d106ced..0000000 --- a/board/evb64260/64260.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __64260_H__ -#define __64260_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_AACK_DELAY (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_TA_DELAY (1 << 15) -#define CPU_CONF_RD_OOO (1 << 16) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_FAST_CLK (1 << 23) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) -#define CPU_CONF_CONF_SB_DIS (1 << 28) -#define CPU_CONF_IO_SB_DIS (1 << 29) -#define CPU_CONF_CLK_SYNC (1 << 30) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64260_H__ */ diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile deleted file mode 100644 index c493d6c..0000000 --- a/board/evb64260/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -SOBJS = misc.o -OBJS = $(BOARD).o flash.o serial.o memory.o pci.o \ - eth.o eth_addrtbl.o mpsc.o i2c.o \ - sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o - - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt deleted file mode 100644 index 391d49a..0000000 --- a/board/evb64260/bootseq.txt +++ /dev/null @@ -1,94 +0,0 @@ -(cpu/mpc7xxx/start.S) - -start: - b boot_cold - -start_warm: - b boot_warm - - -boot_cold: -boot_warm: - clear bats - init l2 (if enabled) - init altivec (if enabled) - invalidate l2 (if enabled) - setup bats (from defines in config_EVB) - enable_addr_trans: (if MMU enabled) - enable MSR_IR and MSR_DR - jump to in_flash - -in_flash: - enable l1 dcache - gal_low_init: (board/evb64260/sdram_init.S) - config SDRAM (CFG, TIMING, DECODE) - init scratch regs (810 + 814) - - detect DIMM0 (bank 0 only) - config SDRAM_PARA0 to 256/512Mbit - bl sdram_op_mode - detect bank0 width - write scratch reg 810 - config SDRAM_PARA0 with results - config SDRAM_PARA1 with results - - detect DIMM1 (bank 2 only) - config SDRAM_PARA2 to 256/512Mbit - detect bank2 width - write scratch reg 814 - config SDRAM_PARA2 with results - config SDRAM_PARA3 with results - - setup device bus timings/width - setup boot device timings/width - - setup CPU_CONF (0x0) - setup cpu master control register 0x160 - setup PCI0 TIMEOUT - setup PCI1 TIMEOUT - setup PCI0 BAR - setup PCI1 BAR - - setup MPP control 0-3 - setup GPP level control - setup Serial ports multiplex - - setup stack pointer (r1) - setup GOT - call cpu_init_f - debug leds - board_init_f: (common/board.c) - board_early_init_f: - remap gt regs? - map PCI mem/io - map device space - clear out interupts - init_timebase - env_init - serial_init - console_init_f - display_options - initdram: (board/evb64260/evb64260.c) - detect memory - for each bank: - dram_size() - setup PCI slave memory mappings - setup SCS - setup monitor - alloc board info struct - init bd struct - relocate_code: (cpu/mpc7xxx/start.S) - copy,got,clearbss - board_init_r(bd, dest_addr) (common/board.c) - setup bd function pointers - trap_init - flash_init: (board/evb64260/flash.c) - setup bd flash info - cpu_init_r: (cpu/mpc7xxx/cpu_init.c) - nothing - mem_malloc_init - malloc_bin_reloc - spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) - env_relocated - misc_init_r(bd): (board/evb64260/evb64260.c) - mpsc_init2 diff --git a/board/evb64260/config.mk b/board/evb64260/config.mk deleted file mode 100644 index 0646a3e..0000000 --- a/board/evb64260/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# EVB64260 boards -# - -TEXT_BASE = 0xfff00000 diff --git a/board/evb64260/ecctest.c b/board/evb64260/ecctest.c deleted file mode 100644 index 5d3679a..0000000 --- a/board/evb64260/ecctest.c +++ /dev/null @@ -1,111 +0,0 @@ -indent: Standard input:27: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -#ifdef ECC_TEST -static inline void ecc_off (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000; -} - -static inline void ecc_on (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000; -} - -static int putshex (const char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) { - printf ("%02x", buf[i]); - } - return 0; -} - -static int char_memcpy (void *d, const void *s, int len) -{ - int i; - char *cd = d; - const char *cs = s; - - for (i = 0; i < len; i++) { - *(cd++) = *(cs++); - } - return 0; -} - -static int memory_test (char *buf) -{ - const char src[][16] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}, - {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, - 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}, - {0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, - 0x04, 0x04, 0x04, 0x04, 0x04, 0x04}, - {0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, - 0x08, 0x08, 0x08, 0x08, 0x08, 0x08}, - {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, - {0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x20, 0x20}, - {0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, - 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}, - {0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80}, - {0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, - 0x55, 0x55, 0x55, 0x55, 0x55, 0x55}, - {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}, - {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }; - const int foo[] = { 0 }; - int i, j, a; - - printf ("\ntest @ %d %p\n", foo[0], buf); - for (i = 0; i < 12; i++) { - for (a = 0; a < 8; a++) { - const char *s = src[i] + a; - int align = (unsigned) (s) & 0x7; - - /* ecc_off(); */ - memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - /* ecc_off(); */ - char_memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - } - } - - return 0; -} -#endif diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c deleted file mode 100644 index eafa48b..0000000 --- a/board/evb64260/eth.c +++ /dev/null @@ -1,807 +0,0 @@ -/************************************************************************** -Etherboot - BOOTP/TFTP Bootstrap Program -Skeleton NIC driver for Etherboot -***************************************************************************/ - -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2, or (at - * your option) any later version. - */ - -/* - * This file is a modified version from the Galileo polled mode - * network driver for the ethernet contained within the GT64260 - * chip. It has been modified to fit into the U-Boot framework, from - * the original (etherboot) setup. Also, additional cleanup and features - * were added. - * - * - Josh Huber - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "eth.h" -#include "eth_addrtbl.h" - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) - -#define GT6426x_ETH_BUF_SIZE 1536 - -/* if you like verbose output, turn this on! */ -#undef DEBUG - -/* Restart autoneg if we detect link is up on phy init. */ - -/* - * The GT doc's say that after Rst is deasserted, and the PHY - * reports autoneg complete, it runs through its autoneg - * procedures. This doesn't seem to be the case for MII - * PHY's. To work around this check for link up && autoneg - * complete when initilizing the port. If they are both set, - * then restart PHY autoneg. Of course, it may be something - * completly different. - */ -#ifdef CONFIG_ETHER_PORT_MII -# define RESTART_AUTONEG -#endif - -/* do this if you dont want to use snooping */ -#define USE_SOFTWARE_CACHE_MANAGEMENT - -#ifdef USE_SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -/* bummer - w/o flush, nothing works, even with snooping - FIXME */ -/* #define FLUSH_DCACHE(a,b) */ -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif -struct eth_dev_s { - eth0_tx_desc_single *eth_tx_desc; - eth0_rx_desc_single *eth_rx_desc; - char *eth_tx_buffer; - char *eth_rx_buffer[NR]; - int tdn, rdn; - int dev; - unsigned int reg_base; -}; - - -#ifdef CONFIG_INTEL_LXT97X -/* for intel LXT972 */ -static const char ether_port_phy_addr[3]={0,1,2}; -#else -static const char ether_port_phy_addr[3]={4,5,6}; -#endif - -/* MII PHY access routines are common for all i/f, use gal_ent0 */ -#define GT6426x_MII_DEVNAME "gal_enet0" - -int gt6426x_miiphy_read(char *devname, unsigned char phy, - unsigned char reg, unsigned short *val); - -static inline unsigned short -miiphy_read_ret(unsigned short phy, unsigned short reg) -{ - unsigned short val; - gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val); - return val; -} - - -/************************************************************************** -RESET - Reset adapter -***************************************************************************/ -void -gt6426x_eth_reset(void *v) -{ - /* we should do something here... - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = wp->priv; - */ - - printf ("RESET\n"); - /* put the card in its initial state */ -} - -static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr) -{ -#ifdef DEBUG - printf("SMI interrupt: "); - - if(icr&0x20000000) { - printf("SMI done\n"); - } -#endif - - if(icr&0x10000000) { - unsigned int psr; - psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); -#ifdef DEBUG - printf("PHY state change:\n" - " GT:%s:%s:%s:%s\n", - psr&1?"100":" 10", - psr&8?" Link":"nLink", - psr&2?"FD":"HD", - psr&4?" FC":"nFC"); - -#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */ - { - unsigned short mii_11; - mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11); - - printf(" mii:%s:%s:%s:%s %s:%s %s\n", - mii_11&(1<<14)?"100":" 10", - mii_11&(1<<10)?" Link":"nLink", - mii_11&(1<<9)?"FD":"HD", - mii_11&(1<<4)?" FC":"nFC", - - mii_11&(1<<7)?"ANc":"ANnc", - mii_11&(1<<8)?"AN":"Manual", - "" - ); - } -#endif /* CONFIG_INTEL_LXT97X */ -#endif /* DEBUG */ - } -} - -static int -gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr) -{ - int eth_len=0; - char *eth_data; - - eth0_rx_desc_single *rx=&p->eth_rx_desc[(p->rdn)]; - - INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); - - if (rx->command_status & 0x80000000) { - return 0; /* No packet received */ - } - - eth_len = (unsigned int) - (rx->buff_size_byte_count) & 0x0000ffff; - eth_data = (char *) p->eth_rx_buffer[p->rdn]; - -#ifdef DEBUG - if (eth_len) { - printf ("%s: Recived %d byte Packet @ 0x%p\n", - __FUNCTION__, eth_len, eth_data); - } -#endif - /* - * packet is now in: - * eth0_rx_buffer[RDN_ETH0]; - */ - - /* let the upper layer handle the packet */ - NetReceive ((uchar *)eth_data, eth_len); - - rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16; - - - /* GT96100 Owner */ - rx->command_status = 0x80000000; - - FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); - - p->rdn ++; - if (p->rdn == NR) {p->rdn = 0;} - - sync(); - - /* Start Rx*/ - GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080); - -#ifdef DEBUG - { - int i; - for (i=0;i<12;i++) { - printf(" %02x", eth_data[i]); - } - } - printf(": %d bytes\n", eth_len); -#endif - INVALIDATE_DCACHE((unsigned int)eth_data, - (unsigned int)eth_data+eth_len); - return eth_len; -} - -/************************************************************************** -POLL - look for an rx frame, handle other conditions -***************************************************************************/ -int -gt6426x_eth_poll(void *v) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = wp->priv; - unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base); - - if(icr) { - GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0); -#ifdef DEBUG - printf("poll got ICR %08x\n", icr); -#endif - /* SMI done or PHY state change*/ - if(icr&0x30000000) gt6426x_handle_SMI(p, icr); - } - /* always process. We aren't using RX interrupts */ - return gt6426x_eth_receive(p, icr); -} - -/************************************************************************** -TRANSMIT - Transmit a frame -***************************************************************************/ -int -gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv; -#ifdef DEBUG - unsigned int old_command_stat,old_psr; -#endif - eth0_tx_desc_single *tx=&dev->eth_tx_desc[dev->tdn]; - - /* wait for tx to be ready */ - INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); - while (tx->command_status & 0x80000000) { - int i; - for(i=0;i<1000;i++); - INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); - } - - GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base, - (unsigned int)tx); - -#ifdef DEBUG - printf("copying to tx_buffer [%p], length %x, desc = %p\n", - dev->eth_tx_buffer, s, dev->eth_tx_desc); -#endif - memcpy(dev->eth_tx_buffer, (char *) p, s); - - tx->buff_pointer = (uchar *)dev->eth_tx_buffer; - tx->bytecount_reserved = ((__u16)s) << 16; - - /* 31 - own - * 22 - gencrc - * 18:16 - pad, last, first */ - tx->command_status = (1<<31) | (1<<22) | (7<<16); -#if 0 - /* FEr #18 */ - tx->next_desc = NULL; -#else - tx->next_desc = - (struct eth0_tx_desc_struct *) - &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved; - - /* cpu owned */ - dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16); /* pad, last, first */ -#endif - -#ifdef DEBUG - old_command_stat=tx->command_status, - old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); -#endif - - FLUSH_DCACHE((unsigned int)tx, - (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]); - - FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s); - - GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000); - -#ifdef DEBUG - { - unsigned int command_stat=0; - printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr); - /* wait for tx to be ready */ - do { - unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); - command_stat=tx->command_status; - if(command_stat!=old_command_stat || psr !=old_psr) { - printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr); - old_command_stat = command_stat; - old_psr = psr; - } - /* gt6426x_eth0_poll(); */ - } while (command_stat & 0x80000000); - - printf("sent %d byte frame\n", s); - - if((command_stat & (3<<15)) == 3) { - printf("frame had error (stat=%08x)\n", command_stat); - } - } -#endif - return 0; -} - -/************************************************************************** -DISABLE - Turn off ethernet interface -***************************************************************************/ -void -gt6426x_eth_disable(void *v) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = (struct eth_dev_s *)wp->priv; - - GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000); -} - -/************************************************************************** -MII utilities - write: write to an MII register via SMI -***************************************************************************/ -int -gt6426x_miiphy_write(char *devname, unsigned char phy, - unsigned char reg, unsigned short data) -{ - unsigned int temp= (reg<<21) | (phy<<16) | data; - - while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ - - GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); - return 0; -} - -/************************************************************************** -MII utilities - read: read from an MII register via SMI -***************************************************************************/ -int -gt6426x_miiphy_read(char *devname, unsigned char phy, - unsigned char reg, unsigned short *val) -{ - unsigned int temp= (reg<<21) | (phy<<16) | 1<<26; - - while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ - - GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); - - while(1) { - temp=GTREGREAD(ETHERNET_SMI_REGISTER); - if(temp & (1<<27)) break; /* wait for ReadValid */ - } - *val = temp & 0xffff; - - return 0; -} - -#ifdef DEBUG -/************************************************************************** -MII utilities - dump mii registers -***************************************************************************/ -static void -gt6426x_dump_mii(bd_t *bis, unsigned short phy) -{ - printf("mii reg 0 - 3: %04x %04x %04x %04x\n", - miiphy_read_ret(phy, 0x0), - miiphy_read_ret(phy, 0x1), - miiphy_read_ret(phy, 0x2), - miiphy_read_ret(phy, 0x3) - ); - printf(" 4 - 7: %04x %04x %04x %04x\n", - miiphy_read_ret(phy, 0x4), - miiphy_read_ret(phy, 0x5), - miiphy_read_ret(phy, 0x6), - miiphy_read_ret(phy, 0x7) - ); - printf(" 8: %04x\n", - miiphy_read_ret(phy, 0x8) - ); - printf(" 16-19: %04x %04x %04x %04x\n", - miiphy_read_ret(phy, 0x10), - miiphy_read_ret(phy, 0x11), - miiphy_read_ret(phy, 0x12), - miiphy_read_ret(phy, 0x13) - ); - printf(" 20,30: %04x %04x\n", - miiphy_read_ret(phy, 20), - miiphy_read_ret(phy, 30) - ); -} -#endif - -#ifdef RESTART_AUTONEG - -/* If link is up && autoneg compleate, and if - * GT and PHY disagree about link capabilitys, - * restart autoneg - something screwy with FD/HD - * unless we do this. */ -static void -check_phy_state(struct eth_dev_s *p) -{ - int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR); - int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); - - if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) { - int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) & - miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR); - int want; - - if (nego & PHY_ANLPAR_TXFD) { - want = 0x3; - printf("MII: 100Base-TX, Full Duplex\n"); - } else if (nego & PHY_ANLPAR_TX) { - want = 0x1; - printf("MII: 100Base-TX, Half Duplex\n"); - } else if (nego & PHY_ANLPAR_10FD) { - want = 0x2; - printf("MII: 10Base-T, Full Duplex\n"); - } else if (nego & PHY_ANLPAR_10) { - want = 0x0; - printf("MII: 10Base-T, Half Duplex\n"); - } else { - printf("MII: Unknown link-foo! %x\n", nego); - return; - } - - if ((psr & 0x3) != want) { - printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n", - psr & 0x3, want); - miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0, - miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9)); - udelay(10000); /* the EVB's GT takes a while to notice phy - went down and up */ - } - } -} -#endif - -/************************************************************************** -PROBE - Look for an adapter, this routine's visible to the outside -***************************************************************************/ -int -gt6426x_eth_probe(void *v, bd_t *bis) -{ - struct eth_device *wp = (struct eth_device *)v; - struct eth_dev_s *p = (struct eth_dev_s *)wp->priv; - int dev = p->dev; - unsigned int reg_base = p->reg_base; - unsigned long temp; - int i; - - if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS )) - { /* This should never happen */ - printf("%s: Invalid device %d\n", __FUNCTION__, dev ); - return 0; - } - -#ifdef DEBUG - printf ("%s: initializing %s\n", __FUNCTION__, wp->name ); - printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n", - GTREGREAD(COMM_UNIT_ARBITER_CONTROL), - GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER)); -#endif - - /* clear MIB counters */ - for(i=0;i<255; i++) - temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i); - -#ifdef CONFIG_INTEL_LXT97X - /* for intel LXT972 */ - - /* led 1: 0x1=txact - led 2: 0xc=link/rxact - led 3: 0x2=rxact (N/C) - strch: 0,2=30 ms, enable */ - miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22); - - /* 2.7ns port rise time */ - /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */ -#else - /* already set up in mpsc.c */ - /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); / b400 */ - - /* already set up in sdram_init.S... */ - /* MPSC0, MPSC1, RMII */ - /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); / f010 */ -#endif - GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER, - ether_port_phy_addr[0] | - (ether_port_phy_addr[1]<<5) | - (ether_port_phy_addr[2]<<10)); /* 2000 */ - - /* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes) - * 9 - 1: RIFB - interrupt on frame boundaries only - * 6:7 - 00: big endian rx and tx - * 5:2 - 1111: 15 retries */ - GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base, - (2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */ - -#ifndef USE_SOFTWARE_CACHE_MANAGEMENT - /* enable rx/tx desc/buffer cache snoop */ - GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, - &temp); /* f200 */ - temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30); - GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, - temp); -#endif - - /* 31 28 27 24 23 20 19 16 - * 0000 0000 0000 0000 [0004] - * 15 12 11 8 7 4 3 0 - * 1000 1101 0000 0000 [4d00] - * 20 - 0=MII 1=RMII - * 19 - 0=speed autoneg - * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE) - * 11 - no force link pass - * 10 - 1=disable fctl autoneg - * 8 - override prio ?? */ - temp = 0x00004d00; -#ifndef CONFIG_ETHER_PORT_MII - temp |= (1<<20); /* RMII */ -#endif - /* set En */ - GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base, - temp); /* 2408 */ - - /* hardcode E1 also? */ - /* -- according to dox, this is safer due to extra pulldowns? */ - if (dev<2) { - GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400, - temp); /* 2408 */ - } - - /* wake up MAC */ /* 2400 */ - GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp); - temp |= (1<<7); /* enable port */ -#ifdef CONFIG_GT_USE_MAC_HASH_TABLE - temp |= (1<<12); /* hash size 1/2k */ -#else - temp |= 1; /* promisc */ -#endif - GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp); - /* 2400 */ - -#ifdef RESTART_AUTONEG - check_phy_state(p); -#endif - - printf("%s: Waiting for link up..\n", wp->name); - temp = 10 * 1000; - /* wait for link back up */ - while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8) - && (--temp > 0)){ - udelay(1000); /* wait 1 ms */ - } - if ( temp == 0) { - printf("%s: Failed!\n", wp->name); - return (0); - } - - printf("%s: OK!\n", wp->name); - - p->tdn = 0; - p->rdn = 0; - p->eth_tx_desc[p->tdn].command_status = 0; - - /* Initialize Rx Side */ - for (temp = 0; temp < NR; temp++) { - p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp]; - p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16; - - /* GT96100 Owner */ - p->eth_rx_desc[temp].command_status = 0x80000000; - p->eth_rx_desc[temp].next_desc = - (struct eth0_rx_desc_struct *) - &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count; - } - - FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0], - (unsigned int)&p->eth_tx_desc[NR]); - FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0], - (unsigned int)&p->eth_rx_desc[NR]); - - GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base, - (unsigned int) p->eth_tx_desc); - GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base, - (unsigned int) p->eth_rx_desc); - GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base, - (unsigned int) p->eth_rx_desc); - -#ifdef DEBUG - printf ("\nRx descriptor pointer is %08x %08x\n", - GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base), - GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base)); - printf ("\n\n%08x %08x\n", - (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status); - - printf ("Descriptor dump:\n"); - printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status); - printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count); - printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer); - printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc); - printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0)); - printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4)); - printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8)); - printf ("%08x\n\n", - *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc)); -#endif - -#ifdef DEBUG - gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]); -#endif - -#ifdef CONFIG_GT_USE_MAC_HASH_TABLE - { - unsigned int hashtable_base; - u8 *b = (u8 *)(wp->enetaddr); - u32 macH, macL; - - /* twist the MAC up into the way the discovery wants it */ - macH= (b[0]<<8) | b[1]; - macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5]; - - /* mode 0, size 0x800 */ - hashtable_base =initAddressTable(dev,0,1); - - if(!hashtable_base) { - printf("initAddressTable failed\n"); - return 0; - } - - addAddressTableEntry(dev, macH, macL, 1, 0); - GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base, - hashtable_base); - } -#endif - - /* Start Rx*/ - GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080); - printf("%s: gt6426x eth device %d init success \n", wp->name, dev ); - return 1; -} - -/* enter all the galileo ethernet devs into MULTI-BOOT */ -void -gt6426x_eth_initialize(bd_t *bis) -{ - struct eth_device *dev; - struct eth_dev_s *p; - int devnum, x, temp; - char *s, *e, buf[64]; - -#ifdef DEBUG - printf( "\n%s\n", __FUNCTION ); -#endif - - for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) { - dev = calloc(sizeof(*dev), 1); - if (!dev) { - printf( "%s: gal_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than NAMESIZE (16) */ - sprintf(dev->name, "gal_enet%d", devnum); - -#ifdef DEBUG - printf( "Initializing %s\n", dev->name ); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) - { - case 0: s = "ethaddr"; break; -#if (GAL_ETH_DEVS > 1) - case 1: s = "eth1addr"; break; -#endif -#if (GAL_ETH_DEVS > 2) - case 2: s = "eth2addr"; break; -#endif - default: /* this should never happen */ - printf( "%s: Invalid device number %d\n", - __FUNCTION__, devnum ); - return; - } - - temp = getenv_r (s, buf, sizeof(buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s ); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e+1 : e; - } - - dev->init = (void*)gt6426x_eth_probe; - dev->halt = (void*)gt6426x_eth_reset; - dev->send = (void*)gt6426x_eth_transmit; - dev->recv = (void*)gt6426x_eth_poll; - - p = calloc( sizeof(*p), 1 ); - dev->priv = (void*)p; - if (!p) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Private Device Structure"); - free(dev); - return; - } - - p->dev = devnum; - p->tdn=0; - p->rdn=0; - p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS; - - p->eth_tx_desc = - (eth0_tx_desc_single *) - (((unsigned int) malloc(sizeof (eth0_tx_desc_single) * - (NT+1)) & 0xfffffff0) + 0x10); - if (!p) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Tx Descriptor"); - free(dev); - return; - } - - p->eth_rx_desc = - (eth0_rx_desc_single *) - (((unsigned int) malloc(sizeof (eth0_rx_desc_single) * - (NR+1)) & 0xfffffff0) + 0x10); - if (!p->eth_rx_desc) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Rx Descriptor"); - free(dev); - free(p); - return; - } - - p->eth_tx_buffer = - (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); - if (!p->eth_tx_buffer) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Tx Bufffer"); - free(dev); - free(p); - free(p->eth_rx_desc); - return; - } - - for (temp = 0 ; temp < NR ; temp ++) { - p->eth_rx_buffer[temp] = - (char *) - (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); - if (!p->eth_rx_buffer[temp]) - { - printf( "%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, "Rx Buffers"); - free(dev); - free(p); - free(p->eth_tx_buffer); - free(p->eth_rx_desc); - free(p->eth_tx_desc); - while (temp >= 0) - free(p->eth_rx_buffer[--temp]); - return; - } - } - - - eth_register(dev); -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) - miiphy_register(dev->name, - gt6426x_miiphy_read, gt6426x_miiphy_write); -#endif - } - -} -#endif /* CFG_CMD_NET && CONFIG_NET_MULTI */ diff --git a/board/evb64260/eth.h b/board/evb64260/eth.h deleted file mode 100644 index beb6db1..0000000 --- a/board/evb64260/eth.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __GT6426x_ETH_H__ -#define __GT6426x_ETH_H__ - -#include -#include -#include -#include - -typedef struct eth0_tx_desc_struct { - volatile __u32 bytecount_reserved; - volatile __u32 command_status; - volatile struct eth0_tx_desc_struct * next_desc; - /* Note - the following will not work for 64 bit addressing */ - volatile unsigned char * buff_pointer; -} __attribute__ ((packed)) eth0_tx_desc_single; - -typedef struct eth0_rx_desc_struct { - volatile __u32 buff_size_byte_count; - volatile __u32 command_status; - volatile struct eth0_rx_desc_struct * next_desc; - volatile unsigned char * buff_pointer; -} __attribute__ ((packed)) eth0_rx_desc_single; - -#define NT 20 /* Number of Transmit buffers */ -#define NR 20 /* Number of Receive buffers */ -#define MAX_BUFF_SIZE (1536+2*CACHE_LINE_SIZE) /* 1600 */ -#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400 - -unsigned long TDN_ETH0 , RDN_ETH0; /* Rx/Tx current Descriptor Number*/ -unsigned int EVB64260_ETH0_irq; - -#define CLOSED 0 -#define OPENED 1 - -#define PORT_ETH0 0 - -extern eth0_tx_desc_single *eth0_tx_desc; -extern eth0_rx_desc_single *eth0_rx_desc; -extern char *eth0_tx_buffer; -extern char *eth0_rx_buffer[NR]; -extern char *eth_data; - -extern int gt6426x_eth_poll(void *v); -extern int gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s); -extern void gt6426x_eth_disable(void *v); -extern int gt6426x_eth_probe(void *v, bd_t *bis); - -#endif /* __GT64260x_ETH_H__ */ diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c deleted file mode 100644 index e8ef0e3..0000000 --- a/board/evb64260/eth_addrtbl.c +++ /dev/null @@ -1,221 +0,0 @@ -#include -#include -#include -#include -#include -#include "eth.h" -#include "eth_addrtbl.h" - -#define TRUE 1 -#define FALSE 0 - -#define PRINTF printf - -#ifdef CONFIG_GT_USE_MAC_HASH_TABLE - -static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, }; -static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, }; -static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, }; -static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, }; - -static const u32 hashLength[2] = { - (0x8000), /* 8K * 4 entries */ - (0x8000 / 16), /* 512 * 4 entries */ -}; - -/* Initialize the address table for a port, if needed */ -unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector) -{ - unsigned int tableBase; - - if (port < 0 || port >= GAL_ETH_DEVS) { - printf ("%s: Invalid port number %d\n", __FUNCTION__, port); - return 0; - } - - if (hashMode > 1) { - printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port); - return 0; - } - - if (realAddrTableBase[port] && - (addressTableHashSize[port] != hashSizeSelector)) { - /* we have been here before, - * but now we want a different sized table - */ - free (realAddrTableBase[port]); - realAddrTableBase[port] = 0; - addressTableBase[port] = 0; - - } - - tableBase = (unsigned int) addressTableBase[port]; - /* we get called for every probe, so only do this once */ - if (!tableBase) { - int bytes = - hashLength[hashSizeSelector] * sizeof (addrTblEntry); - - realAddrTableBase[port] = - malloc (bytes + 64); - tableBase = (unsigned int)realAddrTableBase; - - if (!tableBase) { - printf ("%s: alloc memory failed \n", __FUNCTION__); - return 0; - } - - /* align to octal byte */ - if (tableBase & 63) - tableBase = (tableBase + 63) & ~63; - - addressTableHashMode[port] = hashMode; - addressTableHashSize[port] = hashSizeSelector; - addressTableBase[port] = (addrTblEntry *) tableBase; - - memset ((void *) tableBase, 0, bytes); - } - - return tableBase; -} - -/* - * ---------------------------------------------------------------------------- - * This function will calculate the hash function of the address. - * depends on the hash mode and hash size. - * Inputs - * macH - the 2 most significant bytes of the MAC address. - * macL - the 4 least significant bytes of the MAC address. - * hashMode - hash mode 0 or hash mode 1. - * hashSizeSelector - indicates number of hash table entries (0=0x8000,1=0x800) - * Outputs - * return the calculated entry. - */ -u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode) -{ - u32 hashResult; - u32 addrH; - u32 addrL; - u32 addr0; - u32 addr1; - u32 addr2; - u32 addr3; - u32 addrHSwapped; - u32 addrLSwapped; - - - addrH = NIBBLE_SWAPPING_16_BIT (macH); - addrL = NIBBLE_SWAPPING_32_BIT (macL); - - addrHSwapped = FLIP_4_BITS (addrH & 0xf) - + ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4) - + ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8) - + ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12); - - addrLSwapped = FLIP_4_BITS (addrL & 0xf) - + ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4) - + ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8) - + ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12) - + ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16) - + ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20) - + ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24) - + ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28); - - addrH = addrHSwapped; - addrL = addrLSwapped; - - if (hash_mode == 0) { - addr0 = (addrL >> 2) & 0x03f; - addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2; - addr2 = (addrL >> 15) & 0x1ff; - addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8); - } else { - addr0 = FLIP_6_BITS (addrL & 0x03f); - addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff)); - addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff); - addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) | - ((addrH & 0x1) << 8))); - } - - hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); - - if (HashSize == _8K_TABLE) { - hashResult = hashResult & 0xffff; - } else { - hashResult = hashResult & 0x07ff; - } - - return (hashResult); -} - - -/* - * ---------------------------------------------------------------------------- - * This function will add an entry to the address table. - * depends on the hash mode and hash size that was initialized. - * Inputs - * port - ETHERNET port number. - * macH - the 2 most significant bytes of the MAC address. - * macL - the 4 least significant bytes of the MAC address. - * skip - if 1, skip this address. - * rd - the RD field in the address table. - * Outputs - * address table entry is added. - * TRUE if success. - * FALSE if table full - */ -int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip) -{ - addrTblEntry *entry; - u32 newHi; - u32 newLo; - u32 i; - - newLo = (((macH >> 4) & 0xf) << 15) - | (((macH >> 0) & 0xf) << 11) - | (((macH >> 12) & 0xf) << 7) - | (((macH >> 8) & 0xf) << 3) - | (((macL >> 20) & 0x1) << 31) - | (((macL >> 16) & 0xf) << 27) - | (((macL >> 28) & 0xf) << 23) - | (((macL >> 24) & 0xf) << 19) - | (skip << SKIP_BIT) | (rd << 2) | VALID; - - newHi = (((macL >> 4) & 0xf) << 15) - | (((macL >> 0) & 0xf) << 11) - | (((macL >> 12) & 0xf) << 7) - | (((macL >> 8) & 0xf) << 3) - | (((macL >> 21) & 0x7) << 0); - - /* - * Pick the appropriate table, start scanning for free/reusable - * entries at the index obtained by hashing the specified MAC address - */ - entry = addressTableBase[port]; - entry += hashTableFunction (macH, macL, addressTableHashSize[port], - addressTableHashMode[port]); - for (i = 0; i < HOP_NUMBER; i++, entry++) { - if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) { - break; - } else { /* if same address put in same position */ - if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8)) - && (entry->hi == newHi)) { - break; - } - } - } - - if (i == HOP_NUMBER) { - PRINTF ("addGT64260addressTableEntry: table section is full\n"); - return (FALSE); - } - - /* - * Update the selected entry - */ - entry->hi = newHi; - entry->lo = newLo; - DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE); - return (TRUE); -} - -#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */ diff --git a/board/evb64260/eth_addrtbl.h b/board/evb64260/eth_addrtbl.h deleted file mode 100644 index 5a62c67..0000000 --- a/board/evb64260/eth_addrtbl.h +++ /dev/null @@ -1,83 +0,0 @@ -#ifndef _ADDRESS_TABLE_H -#define _ADDRESS_TABLE_H 1 - -/* - * ---------------------------------------------------------------------------- - * addressTable.h - this file has all the declarations of the address table - */ - -#define _8K_TABLE 0 -#define ADDRESS_TABLE_ALIGNMENT 8 -#define HASH_DEFAULT_MODE 14 -#define HASH_MODE 13 -#define HASH_SIZE 12 -#define HOP_NUMBER 12 -#define MAC_ADDRESS_STRING_SIZE 12 -#define MAC_ENTRY_SIZE sizeof(addrTblEntry) -#define MAX_NUMBER_OF_ADDRESSES_TO_STORE 1000 -#define PROMISCUOUS_MODE 0 -#define SKIP 1<<1 -#define SKIP_BIT 1 -#define VALID 1 - -/* - * ---------------------------------------------------------------------------- - * XXX_MIKE - potential sign-extension bugs lurk here... - */ -#define NIBBLE_SWAPPING_32_BIT(X) ( (((X) & 0xf0f0f0f0) >> 4) \ - | (((X) & 0x0f0f0f0f) << 4) ) - -#define NIBBLE_SWAPPING_16_BIT(X) ( (((X) & 0x0000f0f0) >> 4) \ - | (((X) & 0x00000f0f) << 4) ) - -#define FLIP_4_BITS(X) ( (((X) & 0x01) << 3) | (((X) & 0x002) << 1) \ - | (((X) & 0x04) >> 1) | (((X) & 0x008) >> 3) ) - -#define FLIP_6_BITS(X) ( (((X) & 0x01) << 5) | (((X) & 0x020) >> 5) \ - | (((X) & 0x02) << 3) | (((X) & 0x010) >> 3) \ - | (((X) & 0x04) << 1) | (((X) & 0x008) >> 1) ) - -#define FLIP_9_BITS(X) ( (((X) & 0x01) << 8) | (((X) & 0x100) >> 8) \ - | (((X) & 0x02) << 6) | (((X) & 0x080) >> 6) \ - | (((X) & 0x04) << 4) | (((X) & 0x040) >> 4) \ - | ((X) & 0x10) | (((X) & 0x08) << 2) | (((X) & 0x020) >> 2) ) - -/* - * V: value we're operating on - * O: offset of rightmost bit in field - * W: width of field to shift - * S: distance to shift left - */ -#define MASK( fieldWidth ) ((1 << (fieldWidth)) - 1) -#define leftShiftedBitfield( V,O,W,S) (((V) & (MASK(W) << (O))) << (S)) -#define rightShiftedBitfield(V,O,W,S) (((u32)((V) & (MASK(W) << (O)))) >> (S)) - - -/* - * Push to main memory all cache lines associated with - * the specified range of virtual memory addresses - * - * A: Address of first byte in range to flush - * N: Number of bytes to flush - * Note - flush_dcache_range() does a "sync", does NOT invalidate - */ -#define DCACHE_FLUSH_N_SYNC( A, N ) flush_dcache_range( (A), ((A)+(N)) ) - - -typedef struct addressTableEntryStruct { - u32 hi; - u32 lo; -} addrTblEntry; - -u32 -uncachedPages( u32 pages ); -u32 -hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode ); - -unsigned int -initAddressTable( u32 port, u32 hashMode, u32 hashSize ); - -int -addAddressTableEntry( u32 port, u32 macH, u32 macL, u32 rd, u32 skip ); - -#endif /* #ifndef _ADDRESS_TABLE_H */ diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c deleted file mode 100644 index 6a9d164..0000000 --- a/board/evb64260/evb64260.c +++ /dev/null @@ -1,444 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * evb64260.c - main board support/init for the Galileo Eval board. - */ - -#include -#include <74xx_7xx.h> -#include -#include -#include -#include - -#include -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64260.h" -#ifdef CONFIG_ZUMA_V2 -extern void zuma_mbox_init(void); -#endif - -#undef DEBUG -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void -my_remap_gt_regs(u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -} - -static void -gt_pci_config(void) -{ - /* move PCI stuff out of the way - NTL */ - /* map PCI Host 0 */ - pciMapSpace(PCI_HOST0, PCI_REGION0, CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, CFG_PCI0_MEM_SIZE); - - pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0); - pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0); - pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0); - - pciMapSpace(PCI_HOST0, PCI_IO, CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE); - - /* map PCI Host 1 */ - pciMapSpace(PCI_HOST1, PCI_REGION0, CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, CFG_PCI1_MEM_SIZE); - - pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0); - pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0); - pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0); - - pciMapSpace(PCI_HOST1, PCI_IO, CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE); - - /* PCI interface settings */ - GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff); - GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff); - GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); - GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e); - - -} - -/* Setup CPU interface paramaters */ -static void -gt_cpu_config(void) -{ - cpu_t cpu = get_cpu_type(); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD(CPU_CONFIGURATION); - - /* set the AACK delay bit - * see Res#14 */ - tmp |= CPU_CONF_AACK_DELAY; - tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */ - - /* Galileo claims this is necessary for all busses >= 100 MHz */ - tmp |= CPU_CONF_FAST_CLK; - - if (cpu == CPU_750CX) { - tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */ - tmp &= ~CPU_CONF_AP_VALID; - } else { - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - } - - /* this only works with the MPX bus */ - tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */ - tmp |= CPU_CONF_PIPELINE; - tmp |= CPU_CONF_TA_DELAY; - - GT_REG_WRITE(CPU_CONFIGURATION, tmp); - - /* CPU master control register */ - tmp = GTREGREAD(CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || - (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE(CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - uchar sram_boot = 0; - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS); - - gt_pci_config(); - - /* mask all external interrupt sources */ - GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - - /* now, onto the configuration */ - GT_REG_WRITE(SDRAM_CONFIGURATION, CFG_SDRAM_CONFIG); - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM - * 1 - RTC - * 2 - UART - * 3 - Flash - * boot - BootCS - * - * Zuma - * 0 - Flash - * boot - BootCS - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ -#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) - /* Zuma has no SRAM */ - sram_boot = 0; -#else - if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CFG_MONITOR_BASE) - sram_boot = 1; -#endif - - if (!sram_boot) - memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - - memoryMapDeviceSpace(DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace(DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace(DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); - - /* configure device timing */ -#ifdef CFG_DEV0_PAR - if (!sram_boot) - GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); -#endif - -#ifdef CFG_DEV1_PAR - GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); -#endif -#ifdef CFG_DEV2_PAR - GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); -#endif - -#ifdef CONFIG_EVB64260 -#ifdef CFG_32BIT_BOOT_PAR - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); -#endif -#else /* CONFIG_EVB64260 not defined */ - /* We are booting from 16-bit flash. - */ - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_16BIT_BOOT_PAR); -#endif - - gt_cpu_config(); - - /* MPP setup */ - GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE(MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3); - - GT_REG_WRITE(GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); - GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CFG_SERIAL_PORT_MUX); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r (void) -{ - icache_enable(); -#ifdef CFG_L2 - l2cache_enable(); -#endif - -#ifdef CONFIG_MPSC - mpsc_init2(); -#endif - -#ifdef CONFIG_ZUMA_V2 - zuma_mbox_init(); -#endif - return (0); -} - -void -after_reloc(ulong dest_addr) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* check to see if we booted from the sram. If so, move things - * back to the way they should be. (we're running from main - * memory at this point now */ - - if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) { - memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace(BOOT_DEVICE, CFG_FLASH_BASE, _1M); - } - - /* now, jump to the main U-Boot board init code */ - board_init_r ((gd_t *)gd, dest_addr); - - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int -checkboard (void) -{ - puts ("Board: " CFG_BOARD_NAME "\n"); - return (0); -} - -/* utility functions */ -void -debug_led(int led, int mode) -{ -#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4) - volatile int *addr = NULL; - int dummy; - - if (mode == 1) { - switch (led) { - case 0: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x08000); - break; - - case 1: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x0c000); - break; - - case 2: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x10000); - break; - } - } else if (mode == 0) { - switch (led) { - case 0: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x14000); - break; - - case 1: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x18000); - break; - - case 2: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x1c000); - break; - } - } - WRITE_CHAR(addr, 0); - dummy = *addr; -#endif /* CONFIG_ZUMA_V2 */ -} - -void -display_mem_map(void) -{ - int i,j; - unsigned int base,size,width; - /* SDRAM */ - printf("SDRAM\n"); - for(i=0;i<=BANK3;i++) { - base = memoryGetBankBaseAddress(i); - size = memoryGetBankSize(i); - if(size !=0) - { - printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20); - } - } - - /* CPU's PCI windows */ - for(i=0;i<=PCI_HOST1;i++) { - printf("\nCPU's PCI %d windows\n", i); - base=pciGetSpaceBase(i,PCI_IO); - size=pciGetSpaceSize(i,PCI_IO); - printf(" IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20); - for(j=0;j<=PCI_REGION3;j++) { - base = pciGetSpaceBase(i,j); - size = pciGetSpaceSize(i,j); - printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base, - size>>20); - } - } - - /* Devices */ - printf("\nDEVICES\n"); - for(i=0;i<=DEVICE3;i++) { - base = memoryGetDeviceBaseAddress(i); - size = memoryGetDeviceSize(i); - width= memoryGetDeviceWidth(i) * 8; - printf("DEV %d: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n", - i, base, size>>20, width); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize(BOOT_DEVICE); - width= memoryGetDeviceWidth(BOOT_DEVICE) * 8; - printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n", - base, size>>20, width); -} diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c deleted file mode 100644 index 6ab23dc..0000000 --- a/board/evb64260/flash.c +++ /dev/null @@ -1,854 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * flash.c - flash support for the 512k, 8bit boot flash on the GEVB - * most of this file was based on the existing U-Boot - * flash drivers. - */ - -#include -#include -#include -#include -#include "intel_flash.h" - -#define FLASH_ROM 0xFFFD /* unknown flash type */ -#define FLASH_RAM 0xFFFE /* unknown flash type */ -#define FLASH_MAN_UNKNOWN 0xFFFF0000 - -/* #define DEBUG */ -/* #define FLASH_ID_OVERRIDE */ /* Hack to set type to 040B if ROM emulator is installed. - * Can be used to program a ROM in circuit if a programmer - * is not available by swapping the rom out. */ - -/* Intel flash commands */ -int flash_erase_intel(flash_info_t *info, int s_first, int s_last); -int write_word_intel(bank_addr_t addr, bank_word_t value); - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - */ - -unsigned long -flash_init (void) -{ - unsigned int i; - unsigned long size_b0 = 0, size_b1 = 0; - unsigned long base, flash_size; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - flash_size = size_b0 + size_b1; - return flash_size; -} - -/*----------------------------------------------------------------------- - */ -static void -flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - int sector_size; - - if(!info->sector_count) return; - - /* set up sector start address table */ - switch(info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - case FLASH_28F128J3A: - case FLASH_28F640J3A: - case FLASH_RAM: - /* this chip has uniformly spaced sectors */ - sector_size=info->size/info->sector_count; - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sector_size); - break; - default: - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base <= info->start[0] + info->size - 1) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ -void -flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A (64 Mbit)\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A (128 Mbit)\n"); - break; - case FLASH_ROM: - printf ("ROM\n"); - break; - case FLASH_RAM: - printf ("RAM\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - puts (" Size: "); - print_size (info->size, ""); - printf (" in %d Sectors\n", info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static inline void flash_cmd(int width, volatile unsigned char *addr, int offset, unsigned char cmd) -{ - /* supports 1x8, 1x16, and 2x16 */ - /* 2x8 and 4x8 are not supported */ - if(width==4) { - /* assuming chips are in 16 bit mode */ - /* 2x16 */ - unsigned long cmd32=(cmd<<16)|cmd; - *(volatile unsigned long *)(addr+offset*2)=cmd32; - } else if (width == 2) { - /* 1x16 */ - *(volatile unsigned short *)((unsigned short*)addr+offset)=cmd; - } else { - /* 1x8 */ - *(volatile unsigned char *)(addr+offset)=cmd; - } -} - -static ulong -flash_get_size (int portwidth, vu_long *addr, flash_info_t *info) -{ - short i; - volatile unsigned char *caddr = (unsigned char *)addr; - volatile unsigned short *saddr = (unsigned short *)addr; - volatile unsigned long *laddr = (unsigned long *)addr; - char old[2], save; - ulong id, manu, base = (ulong)addr; - - info->portwidth=portwidth; - - save = *caddr; - - flash_cmd(portwidth,caddr,0,0xf0); - flash_cmd(portwidth,caddr,0,0xf0); - - udelay(10); - - old[0] = caddr[0]; - old[1] = caddr[1]; - - - if(old[0]!=0xf0) { - flash_cmd(portwidth,caddr,0,0xf0); - flash_cmd(portwidth,caddr,0,0xf0); - - udelay(10); - - if(*caddr==0xf0) { - /* this area is ROM */ - *caddr=save; -#ifndef FLASH_ID_OVERRIDE - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; -#else - info->flash_id = FLASH_MAN_AMD + FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth=1; -#endif - flash_get_offsets(base, info); - return info->size; - } - } else { - *caddr=0; - - udelay(10); - - if(*caddr==0) { - /* this area is RAM */ - *caddr=save; - info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets(base, info); - return info->size; - } - flash_cmd(portwidth,caddr,0,0xf0); - - udelay(10); - } - - /* Write auto select command: read Manufacturer ID */ - flash_cmd(portwidth,caddr,0x555,0xAA); - flash_cmd(portwidth,caddr,0x2AA,0x55); - flash_cmd(portwidth,caddr,0x555,0x90); - - udelay(10); - - if ((caddr[0] == old[0]) && - (caddr[1] == old[1])) { - - /* this area is ROM */ -#ifndef FLASH_ID_OVERRIDE - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; -#else - info->flash_id = FLASH_MAN_AMD + FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth=1; -#endif - flash_get_offsets(base, info); - return info->size; -#ifdef DEBUG - } else { - printf("%px%d: %02x:%02x -> %02x:%02x\n", - caddr, portwidth, old[0], old[1], - caddr[0], caddr[1]); -#endif - } - - switch(portwidth) { - case 1: - manu = caddr[0]; - manu |= manu<<16; - id = caddr[1]; - break; - case 2: - manu = saddr[0]; - manu |= manu<<16; - id = saddr[1]; - id |= id<<16; - break; - case 4: - manu = laddr[0]; - id = laddr[1]; - break; - default: - id = manu = -1; - break; - } - -#ifdef DEBUG - printf("\n%08lx:%08lx:%08lx\n", base, manu, id); - printf("%08lx %08lx %08lx %08lx\n", - laddr[0],laddr[1],laddr[2],laddr[3]); -#endif - - switch (manu) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("Unknown Mfr [%08lx]:%08lx\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - switch (id) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth=1; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth=1; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth=1; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth=1; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth=1; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth=1; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth=1; - break; - - case INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 128*1024 * 64; /* 128kbytes x 64 blocks */ - info->chipwidth=2; - if(portwidth==4) info->size*=2; /* 2x16 */ - break; - - case INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 128*1024 * 128; /* 128kbytes x 128 blocks */ - info->chipwidth=2; - if(portwidth==4) info->size*=2; /* 2x16 */ - break; - - default: - printf("Unknown id %lx:[%lx]\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->chipwidth=1; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets(base, info); - -#if 0 - /* set up sector start address table */ - if (info->flash_id & FLASH_AM040) { - /* this chip has uniformly spaced sectors */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0)=0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - saddr = (volatile unsigned short *)(info->start[i]); - laddr = (volatile unsigned long *)(info->start[i]); - if(portwidth==1) - info->protect[i] = caddr[2] & 1; - else if(portwidth==2) - info->protect[i] = saddr[2] & 1; - else - info->protect[i] = laddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - - flash_cmd(portwidth,caddr,0,0xF0); /* reset bank */ - } - - return (info->size); -} - -/* TODO: 2x16 unsupported */ -int -flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile unsigned char *addr = (uchar *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - /* TODO: 2x16 unsupported */ - if(info->portwidth==4) return 1; - - if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1; - if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - for (sect = s_first; sect<=s_last; sect++) { - int sector_size=info->size/info->sector_count; - addr = (uchar *)(info->start[sect]); - memset((void *)addr, 0, sector_size); - } - return 0; - } - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id&FLASH_VENDMASK) == FLASH_MAN_INTEL) { - return flash_erase_intel(info, - (unsigned short)s_first, - (unsigned short)s_last); - } - -#if 0 - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } -#endif - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_cmd(info->portwidth,addr,0x555,0xAA); - flash_cmd(info->portwidth,addr,0x2AA,0x55); - flash_cmd(info->portwidth,addr,0x555,0x80); - flash_cmd(info->portwidth,addr,0x555,0xAA); - flash_cmd(info->portwidth,addr,0x2AA,0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (uchar *)(info->start[sect]); - flash_cmd(info->portwidth,addr,0,0x30); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - /* broken for 2x16: TODO */ - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - flash_cmd(info->portwidth,addr,0,0xf0); - flash_cmd(info->portwidth,addr,0,0xf0); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -/* broken for 2x16: TODO */ -int -write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - if(info->portwidth==4) return 1; - - if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 0; - if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - memcpy((void *)addr, src, cnt); - return 0; - } - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -/* broken for 2x16: TODO */ -static int -write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile unsigned char *addr = (uchar *)(info->start[0]); - ulong start; - int flag, i; - - if(info->portwidth==4) return 1; - - if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1; - if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - *(unsigned long *)dest=data; - return 0; - } - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - unsigned short low = data & 0xffff; - unsigned short hi = (data >> 16) & 0xffff; - int ret = write_word_intel((bank_addr_t)dest, hi); - - if (!ret) ret = write_word_intel((bank_addr_t)(dest+2), low); - - return ret; - } - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* first, perform an unlock bypass command to speed up flash writes */ - addr[0x555] = 0xAA; - addr[0x2AA] = 0x55; - addr[0x555] = 0x20; - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *)&data; - addr[0] = 0xA0; - *(((char *)dest)+i) = data_ch[i]; - udelay(10); /* XXX */ - } - - /* we're done, now do an unlock bypass reset */ - addr[0] = 0x90; - addr[0] = 0x00; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c deleted file mode 100644 index c62b647..0000000 --- a/board/evb64260/i2c.c +++ /dev/null @@ -1,315 +0,0 @@ -#include -#include -#include -#include -#include - -#define MAX_I2C_RETRYS 10 -#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */ -#undef DEBUG_I2C - -#ifdef DEBUG_I2C -#define DP(x) x -#else -#define DP(x) -#endif - -/* Assuming that there is only one master on the bus (us) */ - -static void -i2c_init(int speed, int slaveaddr) -{ - unsigned int n, m, freq, margin, power; - unsigned int actualFreq, actualN=0, actualM=0; - unsigned int control, status; - unsigned int minMargin = 0xffffffff; - unsigned int tclk = 125000000; - - DP(puts("i2c_init\n")); - - for(n = 0 ; n < 8 ; n++) - { - for(m = 0 ; m < 16 ; m++) - { - power = 2< freq) - margin = speed - freq; - else - margin = freq - speed; - if(margin < minMargin) - { - minMargin = margin; - actualFreq = freq; - actualN = n; - actualM = m; - } - } - } - - DP(puts("setup i2c bus\n")); - - /* Setup bus */ - - GT_REG_WRITE(I2C_SOFT_RESET, 0); - - DP(puts("udelay...\n")); - - udelay(I2C_DELAY); - - DP(puts("set baudrate\n")); - - GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); - GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); - - udelay(I2C_DELAY * 10); - - DP(puts("read control, baudrate\n")); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - GT_REG_READ(I2C_CONTROL, &control); -} - -static uchar -i2c_start(void) -{ - unsigned int control, status; - int count = 0; - - DP(puts("i2c_start\n")); - - /* Set the start bit */ - - GT_REG_READ(I2C_CONTROL, &control); - control |= (0x1 << 5); - GT_REG_WRITE(I2C_CONTROL, control); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - - count = 0; - while ((status & 0xff) != 0x08) { - udelay(I2C_DELAY); - if (count > 20) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return (status); - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - return (0); -} - -static uchar -i2c_select_device(uchar dev_addr, uchar read, int ten_bit) -{ - unsigned int status, data, bits = 7; - int count = 0; - - DP(puts("i2c_select_device\n")); - - /* Output slave address */ - - if (ten_bit) { - bits = 10; - } - - data = (dev_addr << 1); - /* set the read bit */ - data |= read; - GT_REG_WRITE(I2C_DATA, data); - /* assert the address */ - RESET_REG_BITS(I2C_CONTROL, BIT3); - - udelay(I2C_DELAY); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count = 0; - while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { - udelay(I2C_DELAY); - if (count > 20) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return(status); - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - if (bits == 10) { - printf("10 bit I2C addressing not yet implemented\n"); - return (0xff); - } - - return (0); -} - -static uchar -i2c_get_data(uchar* return_data, int len) { - - unsigned int data, status = 0; - int count = 0; - - DP(puts("i2c_get_data\n")); - - while (len) { - - /* Get and return the data */ - - RESET_REG_BITS(I2C_CONTROL, (0x1 << 3)); - - udelay(I2C_DELAY * 5); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x50) { - udelay(I2C_DELAY); - if(count > 2) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return 0; - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_READ(I2C_DATA, &data); - len--; - *return_data = (uchar)data; - return_data++; - } - RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3); - while ((status & 0xff) != 0x58) { - udelay(I2C_DELAY); - if(count > 200) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return (status); - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */ - - return (0); -} - -static uchar -i2c_write_data(unsigned int data, int len) -{ - unsigned int status; - int count = 0; - - DP(puts("i2c_write_data\n")); - - if (len > 4) - return -1; - - while (len) { - /* Set and assert the data */ - - GT_REG_WRITE(I2C_DATA, (unsigned int)data); - RESET_REG_BITS(I2C_CONTROL, (0x1 << 3)); - - udelay(I2C_DELAY); - - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - udelay(I2C_DELAY); - if(count > 20) { - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return (status); - } - GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - } - GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4)); - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); - - udelay(I2C_DELAY * 10); - - return (0); -} - -static uchar -i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit) -{ - uchar status; - - DP(puts("i2c_set_dev_offset\n")); - - status = i2c_select_device(dev_addr, 0, ten_bit); - if (status) { -#ifdef DEBUG_I2C - printf("Failed to select device setting offset: 0x%02x\n", - status); -#endif - return status; - } - - status = i2c_write_data(offset, 1); - if (status) { -#ifdef DEBUG_I2C - printf("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - - return (0); -} - -uchar -i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data, - int ten_bit) -{ - uchar status = 0; - unsigned int i2cFreq = 400000; - - DP(puts("i2c_read\n")); - - i2c_init(i2cFreq,0); - - status = i2c_start(); - - if (status) { -#ifdef DEBUG_I2C - printf("Transaction start failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_set_dev_offset(dev_addr, 0, 0); - if (status) { -#ifdef DEBUG_I2C - printf("Failed to set offset: 0x%02x\n", status); -#endif - return status; - } - - i2c_init(i2cFreq,0); - - status = i2c_start(); - if (status) { -#ifdef DEBUG_I2C - printf("Transaction restart failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_select_device(dev_addr, 1, ten_bit); - if (status) { -#ifdef DEBUG_I2C - printf("Address not acknowledged: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_get_data(data, len); - if (status) { -#ifdef DEBUG_I2C - printf("Data not recieved: 0x%02x\n", status); -#endif - return status; - } - - return 0; -} diff --git a/board/evb64260/i2c.h b/board/evb64260/i2c.h deleted file mode 100644 index 9c21992..0000000 --- a/board/evb64260/i2c.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __I2C_H__ -#define __I2C_H__ - -/* function declarations */ -uchar i2c_read(uchar, unsigned int, int, uchar*, int); - -#endif diff --git a/board/evb64260/intel_flash.c b/board/evb64260/intel_flash.c deleted file mode 100644 index ed6a2a0..0000000 --- a/board/evb64260/intel_flash.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for the Hymod board by Murray.Jensen@cmst.csiro.au, 20-Oct-00 - */ - -#include -#include -#include -#include -#include "intel_flash.h" - - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -static void -bank_reset(flash_info_t *info, int sect) -{ - bank_addr_t addrw, eaddrw; - - addrw = (bank_addr_t)info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD(addrw); - - while (addrw < eaddrw) { -#ifdef FLASH_DEBUG - printf(" writing reset cmd to addr 0x%08lx\n", - (unsigned long)addrw); -#endif - *addrw = BANK_CMD_RST; - addrw++; - } -} - -static void -bank_erase_init(flash_info_t *info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int flag; - -#ifdef FLASH_DEBUG - printf("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG); - printf("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1); - printf("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2); - printf("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT); - printf("0x%08x BANK_CMD_RST\n", BANK_CMD_RST); - printf("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY); - printf("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR); -#endif - - saddrw = (bank_addr_t)info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD(saddrw); - -#ifdef FLASH_DEBUG - printf("erasing sector %d, start addr = 0x%08lx " - "(bank next word addr = 0x%08lx)\n", sect, - (unsigned long)saddrw, (unsigned long)eaddrw); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts(); - - for (addrw = saddrw; addrw < eaddrw; addrw++) { -#ifdef FLASH_DEBUG - printf(" writing erase cmd to addr 0x%08lx\n", - (unsigned long)addrw); -#endif - *addrw = BANK_CMD_ERASE1; - *addrw = BANK_CMD_ERASE2; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); -} - -static int -bank_erase_poll(flash_info_t *info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int sectdone, haderr; - - saddrw = (bank_addr_t)info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD(saddrw); - - sectdone = 1; - haderr = 0; - - for (addrw = saddrw; addrw < eaddrw; addrw++) { - bank_word_t stat = *addrw; - -#ifdef FLASH_DEBUG - printf(" checking status at addr " - "0x%08x [0x%08x]\n", - (unsigned long)addrw, stat); -#endif - if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY) - sectdone = 0; - else if ((stat & BANK_STAT_ERR) != 0) { - printf(" failed on sector %d " - "(stat = 0x%08x) at " - "address 0x%p\n", - sect, stat, addrw); - *addrw = BANK_CMD_CLR_STAT; - haderr = 1; - } - } - - if (haderr) - return (-1); - else - return (sectdone); -} - -int -write_word_intel(bank_addr_t addr, bank_word_t value) -{ - bank_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BANK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); - - if ((stat & BANK_STAT_ERR) != 0) { - printf("flash program failed (stat = 0x%08lx) " - "at address 0x%08lx\n", (ulong)stat, (ulong)addr); - *addr = BANK_CMD_CLR_STAT; - retval = 3; - } - -done: - /* reset to read mode */ - *addr = BANK_CMD_RST; - - return (retval); -} - -/*----------------------------------------------------------------------- - */ - -int -flash_erase_intel(flash_info_t *info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - -#ifdef FLASH_DEBUG - printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info(info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sector%s will not be erased!\n", - prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - bank_erase_init(info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer(start); - - do { - now = get_timer(start); - - if (now - estart > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - break; - } - -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = bank_erase_poll(info, sect); - - if (sectdone < 0) { - haderr = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) - printf (" failed\n"); - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - bank_reset(info, sect); - } - } - return haderr; -} diff --git a/board/evb64260/intel_flash.h b/board/evb64260/intel_flash.h deleted file mode 100644 index dc2aa00..0000000 --- a/board/evb64260/intel_flash.h +++ /dev/null @@ -1,160 +0,0 @@ -/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ - -/* - * acceptable chips types are: - * - * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A - */ - -/* register addresses, valid only following an CHIP_CMD_RD_ID command */ -#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */ -#define CHIP_ADDR_REG_DEV 0x000001 /* device id */ -#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */ -#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */ - -/* Commands */ -#define CHIP_CMD_RST 0xFF /* reset flash */ -#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */ -#define CHIP_CMD_RD_STAT 0x70 /* read the status register */ -#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */ -#define CHIP_CMD_PROG 0x40 /* program word command */ -#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */ -#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */ -#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ -#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */ -#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ -#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ -#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ - -/* status register bits */ -#define CHIP_STAT_DPS 0x02 /* Device Protect Status */ -#define CHIP_STAT_VPPS 0x08 /* VPP Status */ -#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ -#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ -#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */ -#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ - -#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \ - CHIP_STAT_ECLBS | CHIP_STAT_PSLBS) - -/* ID and Lock Configuration */ -#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ -#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define CHIP_RD_ID_DEV CFG_FLASH_ID - -/* dimensions */ -#define CHIP_WIDTH 2 /* chips are in 16 bit mode */ -#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */ -#define CHIP_NBLOCKS 128 -#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */ -#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS) - -/********************** DEFINES for Hymod Flash ******************************/ - -/* - * The hymod board has 2 x 28F320J5 chips running in - * 16 bit mode, for a 32 bit wide bank. - */ - -typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */ -typedef volatile bank_word_t *bank_addr_t; -typedef unsigned long bank_size_t; /* want this big - >= 32 bit */ - -#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */ -#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */ - -#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH) -#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT) -#define BANK_NBLOCKS CHIP_NBLOCKS -#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH) -#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH) - -#define MAX_BANKS 1 /* only one bank possible */ - -/* align bank addresses and sizes to bank word boundaries */ -#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_WIDTH - 1))) -#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \ - (bank_size_t)(s) + (BANK_WIDTH - 1))) - -/* align bank addresses and sizes to bank block boundaries */ -#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_BLKSZ - 1))) -#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \ - (bank_size_t)(s) + (BANK_BLKSZ - 1))) - -/* align bank addresses and sizes to bank boundaries */ -#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(BANK_SIZE - 1))) -#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \ - (bank_size_t)(s) + (BANK_SIZE - 1))) - -/* add an offset to a bank address */ -#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \ - (bank_size_t)(o)) - -/* get base address of bank b, given flash base address a */ -#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - (bank_size_t)(b) * BANK_SIZE) - -/* adjust a bank address to start of next word, block or bank */ -#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ - BANK_WIDTH) -#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ - BANK_BLKSZ) -#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - BANK_SIZE) - -/* get bank address of chip register r given a bank base address a */ -#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ - ((bank_size_t)(r) << BANK_WSHIFT)) - -/* make a bank address for each chip register address */ - -#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN) -#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV) -#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM) -#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b)) - -/* - * replicate a chip cmd/stat/rd value into each byte position within a word - * so that multiple chips are accessed in a single word i/o operation - * - * this must be as wide as the bank_word_t type, and take into account the - * chip width and bank layout - */ - -#define BANK_FILL_WORD(o) ((bank_word_t)(o)) - -/* make a bank word value for each chip cmd/stat/rd value */ - -/* Commands */ -#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST) -#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID) -#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT) -#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT) -#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1) -#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2) -#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG) -#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK) -#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK) -#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR) -#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS) -#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS) -#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS) -#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS) -#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS) -#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS) -#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY) - -#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR) - -/* ID and Lock Configuration */ -#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK) -#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN) -#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV) diff --git a/board/evb64260/local.h b/board/evb64260/local.h deleted file mode 100644 index 3d9b443..0000000 --- a/board/evb64260/local.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * include/local.h - local configuration options, board specific - */ - -#ifndef __LOCAL_H -#define __LOCAL_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* This tells U-Boot that the config options are compiled in */ -/* #undef ENV_IS_EMBEDDED */ -/* Don't touch this! U-Boot figures this out based on other - * magic. */ - -/* Uncomment and define any of the below options */ - -/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */ - /* Note: If you defined CONFIG_EVB64260_750CX this */ - /* gets defined automatically. */ - -/* These want string arguments */ -/* #define CONFIG_BOOTARGS */ -/* #define CONFIG_BOOTCOMMAND */ -/* #define CONFIG_RAMBOOTCOMMAND */ -/* #define CONFIG_NFSBOOTCOMMAND */ -/* #define CFG_AUTOLOAD */ -/* #define CONFIG_PREBOOT */ - -/* These don't */ - -/* #define CONFIG_BOOTDELAY */ -/* #define CONFIG_BAUDRATE */ -/* #define CONFIG_LOADS_ECHO */ -/* #define CONFIG_ETHADDR */ -/* #define CONFIG_ETH2ADDR */ -/* #define CONFIG_ETH3ADDR */ -/* #define CONFIG_IPADDR */ -/* #define CONFIG_SERVERIP */ -/* #define CONFIG_ROOTPATH */ -/* #define CONFIG_GATEWAYIP */ -/* #define CONFIG_NETMASK */ -/* #define CONFIG_HOSTNAME */ -/* #define CONFIG_BOOTFILE */ -/* #define CONFIG_LOADADDR */ - -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -#define CONFIG_ETHADDR 00:11:22:33:44:55 - -/* next two ethernet hwaddrs */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:11:22:33:44:66 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:11:22:33:44:77 - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ diff --git a/board/evb64260/memory.c b/board/evb64260/memory.c deleted file mode 100644 index e339854..0000000 --- a/board/evb64260/memory.c +++ /dev/null @@ -1,457 +0,0 @@ -/* Memory.c - Memory mappings and remapping functions */ - -/* Copyright - Galileo technology. */ - -/* modified by Josh Huber to clean some things up, and - * fit it into the U-Boot framework */ - -#include -#include - -/******************************************************************** -* memoryGetBankBaseAddress - Gets the base address of a memory bank -* - If the memory bank size is 0 then this base address has no meaning!!! -* -* -* INPUTS: MEMORY_BANK bank - The bank we ask for its base Address. -* OUTPUT: N/A -* RETURNS: Memory bank base address. -*********************************************************************/ -static unsigned long memoryGetBankRegOffset(MEMORY_BANK bank) -{ - switch (bank) - { - case BANK0: - return SCS_0_LOW_DECODE_ADDRESS; - case BANK1: - return SCS_1_LOW_DECODE_ADDRESS; - case BANK2: - return SCS_2_LOW_DECODE_ADDRESS; - case BANK3: - return SCS_3_LOW_DECODE_ADDRESS; - } - return SCS_0_LOW_DECODE_ADDRESS; /* default value */ -} - -unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank) -{ - unsigned int base; - unsigned int regOffset=memoryGetBankRegOffset(bank); - - GT_REG_READ(regOffset,&base); - base = base << 20; - return base; -} - -/******************************************************************** -* memoryGetDeviceBaseAddress - Gets the base address of a device. -* - If the device size is 0 then this base address has no meaning!!! -* -* -* INPUT: DEVICE device - The device we ask for its base address. -* OUTPUT: N/A -* RETURNS: Device base address. -*********************************************************************/ -static unsigned int memoryGetDeviceRegOffset(DEVICE device) -{ - switch (device) - { - case DEVICE0: - return CS_0_LOW_DECODE_ADDRESS; - case DEVICE1: - return CS_1_LOW_DECODE_ADDRESS; - case DEVICE2: - return CS_2_LOW_DECODE_ADDRESS; - case DEVICE3: - return CS_3_LOW_DECODE_ADDRESS; - case BOOT_DEVICE: - return BOOTCS_LOW_DECODE_ADDRESS; - } - return CS_0_LOW_DECODE_ADDRESS; /* default value */ -} - -unsigned int memoryGetDeviceBaseAddress(DEVICE device) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset=memoryGetDeviceRegOffset(device); - - GT_REG_READ(regOffset, ®Base); - GT_REG_READ(regOffset+8, ®End); - - if(regEnd<=regBase) return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 20; - return regBase; -} - -/******************************************************************** -* memoryGetBankSize - Returns the size of a memory bank. -* -* -* INPUT: MEMORY_BANK bank - The bank we ask for its size. -* OUTPUT: N/A -* RETURNS: Memory bank size. -*********************************************************************/ -unsigned int memoryGetBankSize(MEMORY_BANK bank) -{ - unsigned int size,base; - unsigned int highValue; - unsigned int highAddress=memoryGetBankRegOffset(bank)+8; - - base = memoryGetBankBaseAddress(bank); - GT_REG_READ(highAddress,&highValue); - highValue = (highValue + 1) << 20; - if(base > highValue) - size=0; - else - size = highValue - base; - return size; -} - -/******************************************************************** -* memoryGetDeviceSize - Returns the size of a device memory space -* -* -* INPUT: DEVICE device - The device we ask for its base address. -* OUTPUT: N/A -* RETURNS: Size of a device memory space. -*********************************************************************/ -unsigned int memoryGetDeviceSize(DEVICE device) -{ - unsigned int size,base; - unsigned int highValue; - unsigned int highAddress=memoryGetDeviceRegOffset(device)+8; - - base = memoryGetDeviceBaseAddress(device); - GT_REG_READ(highAddress,&highValue); - if (highValue == 0xfff) - { - size = (~base) + 1; /* what the heck is this? */ - return size; - } - else - highValue = (highValue + 1) << 20; - - if(base > highValue) - size=0; - else - size = highValue - base; - return size; -} - -/******************************************************************** -* memoryGetDeviceWidth - A device can be with: 1,2,4 or 8 Bytes data width. -* The width is determine in registers: 'Device Parameters' -* registers (0x45c, 0x460, 0x464, 0x468, 0x46c - for each device. -* at bits: [21:20]. -* -* INPUT: DEVICE device - Device number -* OUTPUT: N/A -* RETURNS: Device width in Bytes (1,2,4 or 8), 0 if error had occurred. -*********************************************************************/ -unsigned int memoryGetDeviceWidth(DEVICE device) -{ - unsigned int width; - unsigned int regValue; - - GT_REG_READ(DEVICE_BANK0PARAMETERS + device*4,®Value); - width = (regValue & 0x00300000) >> 20; - switch (width) - { - case 0: - return 1; - case 1: - return 2; - case 2: - return 4; - case 3: - return 8; - default: - return 0; - } -} - -bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength) -{ - unsigned int low=0xfff; - unsigned int high=0x0; - unsigned int regOffset=memoryGetBankRegOffset(bank); - - if(bankLength!=0) { - low = (bankBase >> 20) & 0xffff; - high=((bankBase+bankLength)>>20)-1; - } - -#ifdef DEBUG - { - unsigned int oldLow, oldHigh; - GT_REG_READ(regOffset,&oldLow); - GT_REG_READ(regOffset+8,&oldHigh); - - printf("b%d %x-%x->%x-%x\n", bank, oldLow, oldHigh, low, high); - } -#endif - - GT_REG_WRITE(regOffset,low); - GT_REG_WRITE(regOffset+8,high); - - return true; -} -bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength) -{ - /* TODO: what are appropriate "unmapped" values? */ - unsigned int low=0xfff; - unsigned int high=0x0; - unsigned int regOffset=memoryGetDeviceRegOffset(device); - - if(deviceLength != 0) { - low=deviceBase>>20; - high=((deviceBase+deviceLength)>>20)-1; - } else { - /* big problems in here... */ - /* this will HANG */ - } - - GT_REG_WRITE(regOffset,low); - GT_REG_WRITE(regOffset+8,high); - - return true; -} - - -/******************************************************************** -* memoryMapInternalRegistersSpace - Sets new base address for the internals -* registers. -* -* INPUTS: unsigned int internalRegBase - The new base address. -* RETURNS: true on success, false on failure -*********************************************************************/ -bool memoryMapInternalRegistersSpace(unsigned int internalRegBase) -{ - unsigned int currentValue; - unsigned int internalValue = internalRegBase; - - internalRegBase = (internalRegBase >> 20); - GT_REG_READ(INTERNAL_SPACE_DECODE,¤tValue); - internalRegBase = (currentValue & 0xffff0000) | internalRegBase; - GT_REG_WRITE(INTERNAL_SPACE_DECODE,internalRegBase); - INTERNAL_REG_BASE_ADDR = internalValue; - return true; -} - -/******************************************************************** -* memoryGetInternalRegistersSpace - Gets internal registers Base Address. -* -* INPUTS: unsigned int internalRegBase - The new base address. -* RETURNS: true on success, false on failure -*********************************************************************/ -unsigned int memoryGetInternalRegistersSpace(void) -{ - return INTERNAL_REG_BASE_ADDR; -} - -/******************************************************************** -* memorySetProtectRegion - This function modifys one of the 8 regions with -* one of the three protection mode. -* - Be advised to check the spec before modifying them. -* -* -* Inputs: CPU_PROTECT_REGION - one of the eight regions. -* CPU_ACCESS - general access. -* CPU_WRITE - read only access. -* CPU_CACHE_PROTECT - chache access. -* we defining CPU because there is another protect from the pci SIDE. -* Returns: false if one of the parameters is wrong and true else -*********************************************************************/ -bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, - MEMORY_ACCESS memAccess, - MEMORY_ACCESS_WRITE memWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int protectHigh = baseAddress + regionLength; - - if(regionLength == 0) /* closing the region */ - { - GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,0x0000ffff); - GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,0); - return true; - } - baseAddress = (baseAddress & 0xfff00000) >> 20; - baseAddress = baseAddress | memAccess << 16 | memWrite << 17 - | cacheProtection << 18; - GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,baseAddress); - protectHigh = (protectHigh & 0xfff00000) >> 20; - GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,protectHigh - 1); - return true; -} - -/******************************************************************** -* memorySetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency. -* -* -* Inputs: SNOOP_REGION region - One of the four regions. -* SNOOP_TYPE snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* unsigned int baseAddress - Base Address of this region. -* unsigned int topAddress - Top Address of this region. -* Returns: false if one of the parameters is wrong and true else -*********************************************************************/ -bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, - MEMORY_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) ) - return false; - snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region; - snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region; - if(regionLength == 0) /* closing the region */ - { - GT_REG_WRITE(snoopXbaseAddress,0x0000ffff); - GT_REG_WRITE(snoopXtopAddress,0); - return true; - } - baseAddress = baseAddress & 0xffff0000; - data = (baseAddress >> 16) | snoopType << 16; - GT_REG_WRITE(snoopXbaseAddress,data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1); - return true; -} - -/******************************************************************** -* memoryRemapAddress - This fubction used for address remapping. -* -* -* Inputs: regOffset: remap register -* remapValue : -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ -bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue) -{ - unsigned int valueForReg; - valueForReg = (remapValue & 0xfff00000) >> 20; - GT_REG_WRITE(remapReg, valueForReg); - return true; -} - -/******************************************************************** -* memoryGetDeviceParam - This function used for getting device parameters from -* DEVICE BANK PARAMETERS REGISTER -* -* -* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK -* PARAMETERS REGISTER -* - deviceNum : number of device -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ -bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum) -{ - unsigned int valueOfReg; - unsigned int calcData; - - GT_REG_READ(DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg); - calcData = (0x7 & valueOfReg) + ((0x400000 & valueOfReg) >> 19); - deviceParam -> turnOff = calcData; /* Turn Off */ - - calcData = ((0x78 & valueOfReg) >> 3) + ((0x800000 & valueOfReg) >> 19); - deviceParam -> acc2First = calcData; /* Access To First */ - - calcData = ((0x780 & valueOfReg) >> 7) + ((0x1000000 & valueOfReg) >> 20); - deviceParam -> acc2Next = calcData; /* Access To Next */ - - calcData = ((0x3800 & valueOfReg) >> 11) + ((0x2000000 & valueOfReg) >> 22); - deviceParam -> ale2Wr = calcData; /* Ale To Write */ - - calcData = ((0x1c000 & valueOfReg) >> 14) + ((0x4000000 & valueOfReg) >> 23); - deviceParam -> wrLow = calcData; /* Write Active */ - - calcData = ((0xe0000 & valueOfReg) >> 17) + ((0x8000000 & valueOfReg) >> 24); - deviceParam -> wrHigh = calcData; /* Write High */ - - calcData = ((0x300000 & valueOfReg) >> 20); - switch (calcData) - { - case 0: - deviceParam -> deviceWidth = 1; /* one Byte - 8-bit */ - break; - case 1: - deviceParam -> deviceWidth = 2; /* two Bytes - 16-bit */ - break; - case 2: - deviceParam -> deviceWidth = 4; /* four Bytes - 32-bit */ - break; - case 3: - deviceParam -> deviceWidth = 8; /* eight Bytes - 64-bit */ - break; - default: - deviceParam -> deviceWidth = 1; - break; - } - return true; -} - -/******************************************************************** -* memorySetDeviceParam - This function used for setting device parameters to -* DEVICE BANK PARAMETERS REGISTER -* -* -* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK -* PARAMETERS REGISTER -* - deviceNum : number of device -* Returns: false if one of the parameters is erroneous,true otherwise. -*********************************************************************/ -bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum) -{ - unsigned int valueForReg; - - if((deviceParam -> turnOff >= 0xf) || (deviceParam -> acc2First >= 0x1f) || - (deviceParam -> acc2Next >= 0x1f) || (deviceParam -> ale2Wr >= 0xf) || - (deviceParam -> wrLow >= 0xf) || (deviceParam -> wrHigh >= 0xf)) - return false; - valueForReg = (((deviceParam -> turnOff) & 0x7) | - (((deviceParam -> turnOff) & 0x8) << 19) | - (((deviceParam -> acc2First) & 0xf) << 3) | - (((deviceParam -> acc2First) & 0x10) << 19) | - (((deviceParam -> acc2Next) & 0xf) << 7) | - (((deviceParam -> acc2Next) & 0x10) << 20) | - (((deviceParam -> ale2Wr) & 0x7) << 11) | - (((deviceParam -> ale2Wr) & 0xf) << 22) | - (((deviceParam -> wrLow) & 0x7) << 14) | - (((deviceParam -> wrLow) & 0xf) << 23) | - (((deviceParam -> wrHigh) & 0x7) << 17) | - (((deviceParam -> wrHigh) & 0xf) << 24)); - /* insert the device width: */ - switch(deviceParam->deviceWidth) - { - case 1: - valueForReg = valueForReg | _8BIT; - break; - case 2: - valueForReg = valueForReg | _16BIT; - break; - case 4: - valueForReg = valueForReg | _32BIT; - break; - case 8: - valueForReg = valueForReg | _64BIT; - break; - default: - valueForReg = valueForReg | _8BIT; - break; - } - GT_REG_WRITE(DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg); - return true; -} diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S deleted file mode 100644 index 438dea6..0000000 --- a/board/evb64260/misc.S +++ /dev/null @@ -1,182 +0,0 @@ -#include -#include <74xx_7xx.h> -#include - -#include -#include - -#include -#include - -#include - -#ifdef CONFIG_ECC - /* Galileo specific asm code for initializing ECC */ - .globl board_relocate_rom -board_relocate_rom: - mflr r7 - /* update the location of the GT registers */ - lis r11, CFG_GT_REGS@h - /* if we're using ECC, we must use the DMA engine to copy ourselves */ - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - - mtlr r7 - blr - - .globl board_init_ecc -board_init_ecc: - mflr r7 - /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ - - /* now that we're running from ram, init the rest of main memory - * for ECC use */ - lis r8, CFG_MONITOR_LEN@h - ori r8, r8, CFG_MONITOR_LEN@l - - divw r3, r10, r8 - - /* set up the counter, and init the starting address */ - mtctr r3 - li r12, 0 - - /* bytes per transfer */ - mr r5, r8 -about_to_init_ecc: -1: mr r3, r12 - mr r4, r12 - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - add r12, r12, r8 - bdnz 1b - - mtlr r7 - blr - - /* r3: dest addr - * r4: source addr - * r5: byte count - * r11: gt regbase - * trashes: r6, r5 - */ -start_idma_transfer_0: - /* set the byte count, including the OWN bit */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_BYTE_COUNT - stwbrx r5, 0, (r6) - - /* set the source address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS - stwbrx r4, 0, (r6) - - /* set the dest address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS - stwbrx r3, 0, (r6) - - /* set the next record pointer */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0NEXT_RECORD_POINTER - stwbrx r5, 0, (r6) - - /* set the low control register */ - /* bit 9 is NON chained mode, bit 31 is new style descriptors. - bit 12 is channel enable */ - ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) - /* 15 shifted by 16 (oris) == bit 31 */ - oris r5, r5, (1 << 15) - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr - - /* this waits for the bytecount to return to zero, indicating - * that the trasfer is complete */ -wait_for_idma_0: - mr r5, r11 - lis r6, 0xff - ori r6, r6, 0xffff - ori r5, r5, CHANNEL0_DMA_BYTE_COUNT -1: lwbrx r4, 0, (r5) - and. r4, r4, r6 - bne 1b - - blr - - /* this turns off channel 0 of the idma engine */ -stop_idma_engine_0: - /* shut off the DMA engine */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr -#endif - -#ifdef CFG_BOARD_ASM_INIT - /* NOTE: trashes r3-r7 */ - .globl board_asm_init -board_asm_init: - /* just move the GT registers to where they belong */ - lis r3, CFG_DFL_GT_REGS@h - ori r3, r3, CFG_DFL_GT_REGS@l - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l - li r5, INTERNAL_SPACE_DECODE - - /* test to see if we've already moved */ - lwbrx r6, r5, r4 - andi. r6, r6, 0xffff - rlwinm r7, r4, 12, 16, 31 - cmp cr0, r7, r6 - beqlr - - /* nope, have to move the registers */ - lwbrx r6, r5, r3 - andis. r6, r6, 0xffff - or r6, r6, r7 - stwbrx r6, r5, r3 - - /* now, poll for the change */ -1: lwbrx r7, r5, r4 - cmp cr0, r7, r6 - bne 1b - - /* done! */ - blr -#endif - -/* For use of the debug LEDs */ - .global led_on0 -led_on0: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0x8000 - stw r18, 0x0(r18) - sync - blr - - .global led_on1 -led_on1: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0xc000 - stw r18, 0x0(r18) - sync - blr - - .global led_on2 -led_on2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x0000 - stw r18, 0x0(r18) - sync - blr diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c deleted file mode 100644 index ee623ca..0000000 --- a/board/evb64260/mpsc.c +++ /dev/null @@ -1,868 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpsc.c - driver for console over the MPSC. - */ - -#include -#include -#include - -#include -#include "mpsc.h" - -int (*mpsc_putchar)(char ch) = mpsc_putchar_early; - -static volatile unsigned int *rx_desc_base=NULL; -static unsigned int rx_desc_index=0; -static volatile unsigned int *tx_desc_base=NULL; -static unsigned int tx_desc_index=0; - -/* local function declarations */ -static int galmpsc_connect(int channel, int connect); -static int galmpsc_route_serial(int channel, int connect); -static int galmpsc_route_rx_clock(int channel, int brg); -static int galmpsc_route_tx_clock(int channel, int brg); -static int galmpsc_write_config_regs(int mpsc, int mode); -static int galmpsc_config_channel_regs(int mpsc); -static int galmpsc_set_char_length(int mpsc, int value); -static int galmpsc_set_stop_bit_length(int mpsc, int value); -static int galmpsc_set_parity(int mpsc, int value); -static int galmpsc_enter_hunt(int mpsc); -static int galmpsc_set_brkcnt(int mpsc, int value); -static int galmpsc_set_tcschar(int mpsc, int value); -static int galmpsc_set_snoop(int mpsc, int value); -static int galmpsc_shutdown(int mpsc); - -static int galsdma_set_RFT(int channel); -static int galsdma_set_SFM(int channel); -static int galsdma_set_rxle(int channel); -static int galsdma_set_txle(int channel); -static int galsdma_set_burstsize(int channel, unsigned int value); -static int galsdma_set_RC(int channel, unsigned int value); - -static int galbrg_set_CDV(int channel, int value); -static int galbrg_enable(int channel); -static int galbrg_disable(int channel); -static int galbrg_set_clksrc(int channel, int value); -static int galbrg_set_CUV(int channel, int value); - -static void galsdma_enable_rx(void); - -/* static int galbrg_reset(int channel); */ - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - - -/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */ -#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack)) - -#define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);} -#define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M) - -#define GT_REG_WRITE_MIRROR(a,i,g,d) {MIRROR_HACK->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);} -#define GTREGREAD_MIRROR(a,i,g) (MIRROR_HACK->a ## _M[i]) - -/* make sure this isn't bigger than 16 long words (u-boot.h) */ -struct _tag_mirror_hack { - unsigned GALMPSC_PROTOCONF_REG_M[2]; /* 8008 */ - unsigned GALMPSC_CHANNELREG_1_M[2]; /* 800c */ - unsigned GALMPSC_CHANNELREG_2_M[2]; /* 8010 */ - unsigned GALBRG_0_CONFREG_M[2]; /* b200 */ - - unsigned GALMPSC_ROUTING_REGISTER_M; /* b400 */ - unsigned GALMPSC_RxC_ROUTE_M; /* b404 */ - unsigned GALMPSC_TxC_ROUTE_M; /* b408 */ - - unsigned int baudrate; /* current baudrate, for tsc delay calc */ -}; - -/* static struct _tag_mirror_hack *mh = NULL; */ - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int -mpsc_putchar_early(char ch) -{ - DECLARE_GLOBAL_DATA_PTR; - int mpsc=CHANNEL; - int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - galmpsc_set_tcschar(mpsc,ch); - GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), temp|0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay(MAGIC_FACTOR / MIRROR_HACK->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int -mpsc_putchar_sdma(char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset((void *)p, 0, 8 * sizeof(unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int)ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int)&p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int)&p[0]; - p[11] = (unsigned int)&p[12]; -#endif - - FLUSH_DCACHE(&p[0], &p[8]); - - GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&p[0]); - GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&p[0]); - - temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE(&p[1], &p[2]); - - while(p[1] & DESC_OWNER) { - udelay(100); - INVALIDATE_DCACHE(&p[1], &p[2]); - } - - return 0; -} - -char -mpsc_getchar(void) -{ - DECLARE_GLOBAL_DATA_PTR; - static unsigned int done = 0; - volatile char ch; - unsigned int len=0, idx=0, temp; - - volatile unsigned int *p; - - - do { - p=&rx_desc_base[rx_desc_index*8]; - - INVALIDATE_DCACHE(&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER){ - udelay(100); - INVALIDATE_DCACHE(&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1<<15)) { - printf("oops, error: %08x\n", p[1]); - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,CHANNEL,GALMPSC_REG_GAP); - temp |= (1 << 23); - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2, CHANNEL,GALMPSC_REG_GAP, temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay(100); - - galsdma_enable_rx(); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) idx = 4; - if (done > 7) idx = 7; - if (done > 11) idx = 6; - - INVALIDATE_DCACHE(&p[idx], &p[idx+1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE(&p[idx], &p[idx+1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE(&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len==0); /* galileo bug.. len might be zero */ - - return ch; -} - -int -mpsc_test_char(void) -{ - volatile unsigned int *p=&rx_desc_base[rx_desc_index*8]; - - INVALIDATE_DCACHE(&p[1], &p[2]); - - if (p[1] & DESC_OWNER) return 0; - else return 1; -} - -int -mpsc_init(int baud) -{ - DECLARE_GLOBAL_DATA_PTR; - - memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack)); - MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff; - - /* BRG CONFIG */ - galbrg_set_baudrate(CHANNEL, baud); -#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) - galbrg_set_clksrc(CHANNEL,0x8); /* connect TCLK -> BRG */ -#else - galbrg_set_clksrc(CHANNEL,0); -#endif - galbrg_set_CUV(CHANNEL, 0); - galbrg_enable(CHANNEL); - - /* Set up clock routing */ - galmpsc_connect(CHANNEL, GALMPSC_CONNECT); - galmpsc_route_serial(CHANNEL, GALMPSC_CONNECT); - galmpsc_route_rx_clock(CHANNEL, CHANNEL); - galmpsc_route_tx_clock(CHANNEL, CHANNEL); - - /* reset MPSC state */ - galmpsc_shutdown(CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize(CHANNEL, L1_CACHE_BYTES/8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle(CHANNEL); - galsdma_set_rxle(CHANNEL); - galsdma_set_RC(CHANNEL, 0xf); - galsdma_set_SFM(CHANNEL); - galsdma_set_RFT(CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs(CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs(CHANNEL); - galmpsc_set_char_length(CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity(CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length(CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop(CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop(CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - -void -mpsc_init2(void) -{ - int i; - - mpsc_putchar = mpsc_putchar_sdma; - - /* RX descriptors */ - rx_desc_base = (unsigned int *)malloc(((RX_DESC+1)*8) * - sizeof(unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int)rx_desc_base+32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset((void *)rx_desc_base, 0, (RX_DESC*8)*sizeof(unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i*8 + 3] = (unsigned int)&rx_desc_base[i*8 + 4]; /* Buffer */ - rx_desc_base[i*8 + 2] = (unsigned int)&rx_desc_base[(i+1)*8]; /* Next descriptor */ - rx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i*8] = 0x00100000; - } - rx_desc_base[(i-1)*8 + 2] = (unsigned int)&rx_desc_base[0]; - - FLUSH_DCACHE(&rx_desc_base[0], &rx_desc_base[RX_DESC*8]); - GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF), - (unsigned int)&rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *)malloc(((TX_DESC+1)*8) * - sizeof(unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int)tx_desc_base+32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset((void *)tx_desc_base, 0, (TX_DESC*8)*sizeof(unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i*8 + 5] = (unsigned int)0x23232323; - tx_desc_base[i*8 + 4] = (unsigned int)0x23232323; - tx_desc_base[i*8 + 3] = (unsigned int)&tx_desc_base[i*8 + 4]; - tx_desc_base[i*8 + 2] = (unsigned int)&tx_desc_base[(i+1)*8]; - tx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i*8] = 0x00010001; - } - tx_desc_base[(i-1)*8 + 2] = (unsigned int)&tx_desc_base[0]; - - FLUSH_DCACHE(&tx_desc_base[0], &tx_desc_base[TX_DESC*8]); - - udelay(100); - - galsdma_enable_rx(); - - return; -} - -int -galbrg_set_baudrate(int channel, int rate) -{ - DECLARE_GLOBAL_DATA_PTR; - int clock; - - galbrg_disable(channel); - -#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) - /* from tclk */ - clock = (CFG_BUS_HZ/(16*rate)) - 1; -#else - clock = (3686400/(16*rate)) - 1; -#endif - - galbrg_set_CDV(channel, clock); - - galbrg_enable(channel); - - MIRROR_HACK->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int -galbrg_set_CDV(int channel, int value) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel,GALBRG_REG_GAP, temp); - - return 0; -} - -static int -galbrg_enable(int channel) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); - temp |= 0x00010000; - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp); - - return 0; -} - -static int -galbrg_disable(int channel) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP); - temp &= 0xFFFEFFFF; - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp); - - return 0; -} - -static int -galbrg_set_clksrc(int channel, int value) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP); - temp &= 0xFF83FFFF; - temp |= (value << 18); - GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP,temp); - - return 0; -} - -static int -galbrg_set_CUV(int channel, int value) -{ - GT_REG_WRITE(GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int -galbrg_reset(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int -galsdma_set_RFT(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_SFM(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_rxle(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_txle(int channel) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_RC(int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp); - - return 0; -} - -static int -galsdma_set_burstsize(int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int -galmpsc_connect(int channel, int connect) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int -galmpsc_route_serial(int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD(GALMPSC_SERIAL_MULTIPLEX); - - if ((channel == 0) && connect) - temp |= 0x00000100; - else if ((channel == 1) && connect) - temp |= 0x00001000; - else if ((channel == 0) && !connect) - temp &= ~0x00000100; - else - temp &= ~0x00001000; - - GT_REG_WRITE(GALMPSC_SERIAL_MULTIPLEX,temp); - - return 0; -} - -static int -galmpsc_route_rx_clock(int channel, int brg) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE); - - if (channel == 0) - temp |= brg; - else - temp |= (brg << 8); - - GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE,temp); - - return 0; -} - -static int -galmpsc_route_tx_clock(int channel, int brg) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE); - - if (channel == 0) - temp |= brg; - else - temp |= (brg << 8); - - GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE,temp); - - return 0; -} - -static int -galmpsc_write_config_regs(int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE(GALMPSC_MCONF_LOW + (mpsc*GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE(GALMPSC_MCONF_HIGH +(mpsc*GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int -galmpsc_config_channel_regs(int mpsc) -{ - DECLARE_GLOBAL_DATA_PTR; - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0); - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1); - GT_REG_WRITE(GALMPSC_CHANNELREG_4+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_5+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_6+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_7+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_8+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_9+(mpsc*GALMPSC_REG_GAP), 0); - GT_REG_WRITE(GALMPSC_CHANNELREG_10+(mpsc*GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt(mpsc, 0x3); - galmpsc_set_tcschar(mpsc, 0xab); - - return 0; -} - -static int -galmpsc_set_brkcnt(int mpsc, int value) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_set_tcschar(int mpsc, int value) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_set_char_length(int mpsc, int value) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_set_stop_bit_length(int mpsc, int value) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP); - temp |= (value << 14); - GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP,temp); - - return 0; -} - -static int -galmpsc_set_parity(int mpsc, int value) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp); - - return 0; -} - -static int -galmpsc_enter_hunt(int mpsc) -{ - DECLARE_GLOBAL_DATA_PTR; - int temp; - - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - temp |= 0x80000000; - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp); - - /* Should Poll on Enter Hunt bit, but the register is write-only */ - /* errata suggests pausing 100 system cycles */ - udelay(100); - - return 0; -} - - -static int -galmpsc_shutdown(int mpsc) -{ - DECLARE_GLOBAL_DATA_PTR; -#if 0 - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp); -#endif - - GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0); - GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, - SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE(GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE(GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG, mpsc, GALMPSC_REG_GAP,0); - - udelay(100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF, - 0x000000fc); - - udelay(100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); - GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); - GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0); - - udelay(100); - - return 0; -} - -static void -galsdma_enable_rx(void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt(CHANNEL); -} - -static int -galmpsc_set_snoop(int mpsc, int value) -{ - int reg = mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : MPSC_0_ADDRESS_CONTROL_LOW; - int temp=GTREGREAD(reg); - if(value) - temp |= (1<< 6) | (1<<14) | (1<<22) | (1<<30); - else - temp &= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30)); - GT_REG_WRITE(reg, temp); - return 0; -} diff --git a/board/evb64260/mpsc.h b/board/evb64260/mpsc.h deleted file mode 100644 index 54b642a..0000000 --- a/board/evb64260/mpsc.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_init2(void); -char mpsc_getchar(void); -int mpsc_test_char(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -extern int (*mpsc_putchar)(char ch); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c deleted file mode 100644 index 59b9acb..0000000 --- a/board/evb64260/pci.c +++ /dev/null @@ -1,760 +0,0 @@ -/* PCI.c - PCI functions */ - -/* Copyright - Galileo technology. */ - -#include -#include - -#include - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { -#ifdef CONFIG_ZUMA_V2 - {0, 0, 0, 0, 0, 0, 0, 29,[8 ... PCI_MAX_DEVICES - 1] = 0}, - {0, 0, 0, 0, 0, 0, 0, 28,[8 ... PCI_MAX_DEVICES - 1] = 0} -#else /* EVB??? This is a guess */ - {0, 0, 0, 0, 0, 0, 0, 27, 27,[9 ... PCI_MAX_DEVICES - 1] = 0}, - {0, 0, 0, 0, 0, 0, 0, 29, 29,[9 ... PCI_MAX_DEVICES - 1] = 0} -#endif -}; - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static unsigned int local_buses[] = { 0, 0 }; - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = PCI_BUS (pciDevNum); - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = PCI_BUS (pciDevNum); - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - if (pciDevNum == SELF) { /* This board */ - GT_REG_WRITE (pci_configuration_data[host], data); - } else { /* configuration Transaction over the pci. */ - - /* The PCI is working in LE Mode So it swap the Data. */ - GT_REG_WRITE (pci_configuration_data[host], WORD_SWAP (data)); - } -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - if (pciDevNum == SELF) { /* This board */ - GT_REG_READ (pci_configuration_data[host], &data); - return data; - } else { /* The PCI is working in LE Mode So it swap the Data. */ - - GT_REG_READ (pci_configuration_data[host], &data); - return WORD_SWAP (data); - } -} - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 20) & 0xfff; - high = ((bankBase + bankLength) >> 20) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 20); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xfff) << 20; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - high &= 0xfff; - low &= 0xfff; - if (high <= low) - return 0; - return (high + 1 - low) << 20; -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + 4 * bank, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + 4 * bank, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); -} - - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -/* - * - */ - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), value, - bus); - } - return 0; -} - -/* - * - */ - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - -#ifndef CONFIG_P3G4 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - - {} -}; - -struct pci_controller pci0_hose = { -#ifndef CONFIG_P3G4 - fixup_irq:gt_fixup_irq, -#endif - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -#ifndef CONFIG_P3G4 - fixup_irq:gt_fixup_irq, -#endif - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - -#ifndef CONFIG_P3G4 - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); -#endif - - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci0_hose.last_busno = pci_hose_scan (&pci0_hose); - - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci0_hose.current_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - -#ifndef CONFIG_P3G4 - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); -#endif - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - - pci1_hose.last_busno = pci_hose_scan (&pci1_hose); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); -} diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c deleted file mode 100644 index 8d63c6f..0000000 --- a/board/evb64260/sdram_init.c +++ /dev/null @@ -1,662 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* sdram_init.c - automatic memory sizing */ - -#include -#include <74xx_7xx.h> -#include -#include -#include -#include - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64260.h" - -/* #define DEBUG */ -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#define GB (1 << 30) - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; - int size; /* detected size, not from I2C but from dram_size() */ -} sdram_info_t; - -#ifdef DEBUG -void dump_dimm_info (struct sdram_info *d) -{ - static const char *ecc_legend[] = { "", " Parity", " ECC" }; - - printf ("dimm%s %sDRAM: %dMibytes:\n", - ecc_legend[d->ecc], - d->registered ? "R" : "", (d->size >> 20)); - printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n", - d->drb_size, d->tpar, d->tras_clocks, d->burst_len, - d->banks, d->slot); -} -#endif - -static int -memory_map_bank (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ -#ifdef DEBUG - if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf ("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank (bankNo, bankBase, bankLength); - - return 0; -} - -#ifdef MAP_PCI -static int -memory_map_bank_pci (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ - PCI_HOST host; - - for (host = PCI_HOST0; host <= PCI_HOST1; host++) { - const int features = - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | PCI_NO_SWAP; - - pciMapMemoryBank (host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures (host, bankNo, features, bankBase, - bankLength); - } - return 0; -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NS10to10PS (unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - -#ifdef CONFIG_ZUMA_V2 -static int check_dimm (uchar slot, sdram_info_t * info) -{ - /* assume 2 dimms, 2 banks each 256M - we dont have an - * dimm i2c so rely on the detection routines later */ - - memset (info, 0, sizeof (*info)); - - info->slot = slot; - info->banks = 2; /* Detect later */ - info->registered = 0; - info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit - but doesn't matter, both do same - thing in setup_sdram() */ - info->tpar = 3; - info->tras_clocks = 5; - info->burst_len = 4; -#ifdef CONFIG_ECC - info->ecc = 0; /* Detect later */ -#endif /* CONFIG_ECC */ - return 0; -} - -#elif defined(CONFIG_P3G4) - -static int check_dimm (uchar slot, sdram_info_t * info) -{ - memset (info, 0, sizeof (*info)); - - if (slot) - return 0; - - info->slot = slot; - info->banks = 1; - info->registered = 0; - info->drb_size = 4; - info->tpar = 3; - info->tras_clocks = 6; - info->burst_len = 4; -#ifdef CONFIG_ECC - info->ecc = 2; -#endif - return 0; -} - -#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */ - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -static int check_dimm (uchar slot, sdram_info_t * info) -{ - DECLARE_GLOBAL_DATA_PTR; - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - uchar rows, cols, sdram_banks, supp_cal, width, cal_val; - ulong tmemclk; - uchar trp_clocks, trcd_clocks; - uchar data[128]; - - get_clocks (); - - tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */ - -#ifdef CONFIG_EVB64260_750CX - if (0 != slot) { - printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,"); - printf (" called with slot=%d insetad!\n", slot); - return 0; - } -#endif - DP (puts ("before i2c read\n")); - - ret = i2c_read (addr, 0, 128, data, 0); - - DP (puts ("after i2c read\n")); - - /* zero all the values */ - memset (info, 0, sizeof (*info)); - - if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); - return 0; - } - - /* first, do some sanity checks */ - if (data[2] != 0x4) { - printf ("Not SDRAM in slot %d\n", slot); - return 0; - } - - /* get various information */ - rows = data[3]; - cols = data[4]; - info->banks = data[5]; - sdram_banks = data[17]; - width = data[13] & 0x7f; - - DP (printf - ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks)); - - /* check if the memory is registered */ - if (data[21] & (BIT1 | BIT4)) - info->registered = 1; - -#ifdef CONFIG_ECC - /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ - info->ecc = (data[11] & 2) >> 1; -#endif - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (data[18] & 0x6) >> 1; - - /* compute the relevant clock values */ - trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk; - trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk; - info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk; - - DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n", - trp_clocks, trcd_clocks, info->tras_clocks)); - - /* try a CAS latency of 3 first... */ - cal_val = 0; - if (supp_cal & 3) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 3; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 2; - } - - DP (printf ("cal_val = %d\n", cal_val)); - - /* bummer, did't work... */ - if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); - return 0; - } - - /* get the largest delay -- these values need to all be the same - * see Res#6 */ - info->tpar = cal_val; - if (trp_clocks > info->tpar) - info->tpar = trp_clocks; - if (trcd_clocks > info->tpar) - info->tpar = trcd_clocks; - - DP (printf ("tpar set to: %d\n", info->tpar)); - -#ifdef CFG_BROKEN_CL2 - if (info->tpar == 2) { - info->tpar = 3; - DP (printf ("tpar fixed-up to: %d\n", info->tpar)); - } -#endif - /* compute the module DRB size */ - info->drb_size = - (((1 << (rows + cols)) * sdram_banks) * width) / _16M; - - DP (printf ("drb_size set to: %d\n", info->drb_size)); - - /* find the burst len */ - info->burst_len = data[16] & 0xf; - if ((info->burst_len & 8) == 8) { - info->burst_len = 1; - } else if ((info->burst_len & 4) == 4) { - info->burst_len = 0; - } else { - return 0; - } - - info->slot = slot; - return 0; -} -#endif /* ! CONFIG_ZUMA_V2 */ - -static int setup_sdram_common (sdram_info_t info[2]) -{ - ulong tmp; - int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2; - - if (!info[0].banks && !info[1].banks) - return 0; - - if (info[0].banks) { - if (info[0].tpar > tpar) - tpar = info[0].tpar; - if (info[0].tras_clocks > tras_clocks) - tras_clocks = info[0].tras_clocks; - if (!info[0].registered) - registered = 0; - if (info[0].ecc != 2) - ecc = 0; - } - - if (info[1].banks) { - if (info[1].tpar > tpar) - tpar = info[1].tpar; - if (info[1].tras_clocks > tras_clocks) - tras_clocks = info[1].tras_clocks; - if (!info[1].registered) - registered = 0; - if (info[1].ecc != 2) - ecc = 0; - } - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIGURATION); - - /* Turn on physical interleave if both DIMMs - * have even numbers of banks. */ - if ((info[0].banks == 0 || info[0].banks == 2) && - (info[1].banks == 0 || info[1].banks == 2)) { - /* physical interleave on */ - tmp &= ~(1 << 15); - } else { - /* physical interleave off */ - tmp |= (1 << 15); - } - - tmp |= (registered << 17); - - /* Use buffer 1 to return read data to the CPU - * See Res #12 */ - tmp |= (1 << 26); - - GT_REG_WRITE (SDRAM_CONFIGURATION, tmp); - DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION))); - - /* SDRAM timing */ - tmp = (((tpar == 3) ? 2 : 1) | - (((tpar == 3) ? 2 : 1) << 2) | - (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8)); - -#ifdef CONFIG_ECC - /* Setup ECC */ - if (ecc == 2) - tmp |= 1 << 13; -#endif /* CONFIG_ECC */ - - GT_REG_WRITE (SDRAM_TIMING, tmp); - DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n", - GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks)); - - /* SDRAM address decode register */ - /* program this with the default value */ - GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2); - DP (printf ("SDRAM decode: %08x\n", - GTREGREAD (SDRAM_ADDRESS_DECODE))); - - return 0; -} - -/* sets up the GT properly with information passed in */ -static int setup_sdram (sdram_info_t * info) -{ - ulong tmp, check; - ulong *addr = 0; - int i; - - /* sanity checking */ - if (!info->banks) - return 0; - - /* ---------------------------- */ - /* Program the GT with the discovered data */ - - /* bank parameters */ - tmp = (0xf << 16); /* leave all virt bank pages open */ - - DP (printf ("drb_size: %d\n", info->drb_size)); - switch (info->drb_size) { - case 1: - tmp |= (1 << 14); - break; - case 4: - case 8: - tmp |= (2 << 14); - break; - case 16: - case 32: - tmp |= (3 << 14); - break; - default: - printf ("Error in dram size calculation\n"); - return 1; - } - - /* SDRAM bank parameters */ - /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ - GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp); - GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp); - DP (printf - ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, - info->slot * 2, (info->slot * 2) + 1, tmp)); - - /* set the SDRAM configuration for each bank */ - for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) { - DP (printf ("*** Running a MRS cycle for bank %d ***\n", i)); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); - - /* set SDRAM mode */ - GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3); - check = GTREGREAD (SDRAM_OPERATION_MODE); - - /* dummy write */ - *addr = 0; - - /* wait for the command to complete */ - while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0); - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION_MODE, 0); - check = GTREGREAD (SDRAM_OPERATION_MODE); - - /* unmap the bank */ - memory_map_bank (i, 0, 0); - DP (printf ("*** MRS cycle for bank %d done ***\n", i)); - } - - return 0; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -static long int dram_size (long int *base, long int maxsize) -{ - volatile long int *addr, *b = base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); - cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr = cnt; /* write cnt to addr */ - *b = 0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr = save1; /* restore *addr */ - *b = save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - - *addr = save1; - *b = save2; - - if (val != cnt) { - /* fix boundary condition.. STARTVAL means zero */ - if (cnt == STARTVAL / sizeof (long)) - cnt = 0; - return (cnt * sizeof (long)); - } - } - return maxsize; -} - -/* ------------------------------------------------------------------------- */ - -/* U-Boot interface function to SDRAM init - this is where all the - * controlling logic happens */ -long int initdram (int board_type) -{ - ulong checkbank[4] = {[0 ... 3] = 0 }; - int bank_no; - ulong total; - int nhr; - sdram_info_t dimm_info[2]; - - - /* first, use the SPD to get info about the SDRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0 () & (1 << 16); - - if (nhr) { - printf ("Skipping SDRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - check_dimm (0, &dimm_info[0]); - - /* DIMM1 */ -#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */ - check_dimm (1, &dimm_info[1]); -#else /* CONFIG_EVB64260_750CX */ - memset (&dimm_info[1], 0, sizeof (sdram_info_t)); -#endif - - /* unmap all banks */ - memory_map_bank (0, 0, 0); - memory_map_bank (1, 0, 0); - memory_map_bank (2, 0, 0); - memory_map_bank (3, 0, 0); - - /* Now, program the GT with the correct values */ - if (setup_sdram_common (dimm_info)) { - printf ("Setup common failed.\n"); - } - - if (setup_sdram (&dimm_info[0])) { - printf ("Setup for DIMM1 failed.\n"); - } - - if (setup_sdram (&dimm_info[1])) { - printf ("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0 (get_hid0 () | (1 << 16)); - } - /* next, size the SDRAM banks */ - - total = 0; - if (dimm_info[0].banks > 0) - checkbank[0] = 1; - if (dimm_info[0].banks > 1) - checkbank[1] = 1; - if (dimm_info[0].banks > 2) - printf ("Error, SPD claims DIMM1 has >2 banks\n"); - - if (dimm_info[1].banks > 0) - checkbank[2] = 1; - if (dimm_info[1].banks > 1) - checkbank[3] = 1; - if (dimm_info[1].banks > 2) - printf ("Error, SPD claims DIMM2 has >2 banks\n"); - - /* Generic dram sizer: works even if we don't have i2c DIMMs, - * as long as the timing settings are more or less correct */ - - /* - * pass 1: size all the banks, using first bat (0-256M) - * limitation: we only support 256M per bank due to - * us only having 1 BAT for all DRAM - */ - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (!checkbank[bank_no]) - continue; - - DP (printf ("checking bank %d\n", bank_no)); - - memory_map_bank (bank_no, 0, GB / 4); - checkbank[bank_no] = dram_size (NULL, GB / 4); - memory_map_bank (bank_no, 0, 0); - - DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no])); - } - - /* - * pass 2: contiguously map each bank into physical address - * space. - */ - dimm_info[0].banks = dimm_info[1].banks = 0; - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { - if (!checkbank[bank_no]) - continue; - - dimm_info[bank_no / 2].banks++; - dimm_info[bank_no / 2].size += checkbank[bank_no]; - - memory_map_bank (bank_no, total, checkbank[bank_no]); -#ifdef MAP_PCI - memory_map_bank_pci (bank_no, total, checkbank[bank_no]); -#endif - total += checkbank[bank_no]; - } - -#ifdef CONFIG_ECC -#ifdef CONFIG_ZUMA_V2 - /* - * We always enable ECC when bank 2 and 3 are unpopulated - * If we 2 or 3 are populated, we CAN'T support ECC. - * (Zuma boards only support ECC in banks 0 and 1; assume that - * in that configuration, ECC chips are mounted, even for stacked - * chips) - */ - if (checkbank[2] == 0 && checkbank[3] == 0) { - dimm_info[0].ecc = 2; - GT_REG_WRITE (SDRAM_TIMING, - GTREGREAD (SDRAM_TIMING) | (1 << 13)); - /* TODO: do we have to run MRS cycles again? */ - } -#endif /* CONFIG_ZUMA_V2 */ - - if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) { - puts ("[ECC] "); - } -#endif /* CONFIG_ECC */ - -#ifdef DEBUG - dump_dimm_info (&dimm_info[0]); - dump_dimm_info (&dimm_info[1]); -#endif - /* TODO: return at MOST 256M? */ - /* return total > GB/4 ? GB/4 : total; */ - return total; -} diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c deleted file mode 100644 index d9c7a15..0000000 --- a/board/evb64260/serial.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * serial.c - serial support for the gal ev board - */ - -/* supports both the 16650 duart and the MPSC */ - -#include -#include -#include - -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) -#include -#endif - -#include "serial.h" - -#include "mpsc.h" - -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) -const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, - (NS16550_t) CFG_NS16550_COM2 }; -#endif - -#ifdef CONFIG_MPSC - -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; -#endif - - mpsc_init(gd->baudrate); - - /* init the DUART chans so that KGDB in the kernel can use them */ -#ifdef CFG_INIT_CHAN1 - NS16550_reinit(COM_PORTS[0], clock_divisor); -#endif -#ifdef CFG_INIT_CHAN2 - NS16550_reinit(COM_PORTS[1], clock_divisor); -#endif - return (0); -} - -void -serial_putc(const char c) -{ - if (c == '\n') - mpsc_putchar('\r'); - - mpsc_putchar(c); -} - -int -serial_getc(void) -{ - return mpsc_getchar(); -} - -int -serial_tstc(void) -{ - return mpsc_test_char(); -} - -void -serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate); -} - -#else /* ! CONFIG_MPSC */ - -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CFG_INIT_CHAN1 - (void)NS16550_init(COM_PORTS[0], clock_divisor); -#endif -#ifdef CFG_INIT_CHAN2 - (void)NS16550_init(COM_PORTS[1], clock_divisor); -#endif - - return (0); -} - -void -serial_putc(const char c) -{ - if (c == '\n') - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); - - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); -} - -int -serial_getc(void) -{ - return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); -} - -int -serial_tstc(void) -{ - return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); -} - -void -serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CFG_INIT_CHAN1 - NS16550_reinit(COM_PORTS[0], clock_divisor); -#endif -#ifdef CFG_INIT_CHAN2 - NS16550_reinit(COM_PORTS[1], clock_divisor); -#endif -} - -#endif /* CONFIG_MPSC */ - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -void -kgdb_serial_init(void) -{ -} - -void -putDebugChar (int c) -{ - serial_putc (c); -} - -void -putDebugStr (const char *str) -{ - serial_puts (str); -} - -int -getDebugChar (void) -{ - return serial_getc(); -} - -void -kgdb_interruptible (int yes) -{ - return; -} -#endif /* CFG_CMD_KGDB */ diff --git a/board/evb64260/serial.h b/board/evb64260/serial.h deleted file mode 100644 index bac9253..0000000 --- a/board/evb64260/serial.h +++ /dev/null @@ -1,63 +0,0 @@ -/* serial.h - mostly useful for DUART serial_init in serial.c */ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - -#if 0 - -#define B230400 1 -#define B115200 2 -#define B57600 4 -#define B38400 82 -#define B19200 163 -#define B9600 24 -#define B4800 651 -#define B2400 1302 -#define B1200 2604 -#define B600 5208 -#define B300 10417 -#define B150 20833 -#define B110 28409 -#define BDEFAULT B115200 - - /* this stuff is important to initialize - the DUART channels */ - -#define Scale 0x01L /* distance between port addresses */ -#define COM1 0x000003f8 /* Keyboard */ -#define COM2 0x000002f8 /* Host */ - - -/* Port Definitions relative to base COM port addresses */ -#define DataIn (0x00*Scale) /* data input port */ -#define DataOut (0x00*Scale) /* data output port */ -#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ -#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ -#define Ier (0x01*Scale) /* interrupt enable register */ -#define Iir (0x02*Scale) /* interrupt identification register */ -#define Lcr (0x03*Scale) /* line control register */ -#define Mcr (0x04*Scale) /* modem control register */ -#define Lsr (0x05*Scale) /* line status register */ -#define Msr (0x06*Scale) /* modem status register */ - -/* Bit Definitions for above ports */ -#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ -#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ - -#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ -#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ -#define McrDflt (McrRts|McrDtr) - -#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ - /* b6: transmitter empty */ -#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ - -#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ -#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ -#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ - -#define IerRda 0xf /* b0: Enable received data available interrupt */ - -#endif - -#endif /* __SERIAL_H__ */ diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds deleted file mode 100644 index d89eb6c..0000000 --- a/board/evb64260/u-boot.lds +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/74xx_7xx/start.o (.text) - -/* store the environment in a seperate sector in the boot flash */ -/* . = env_offset; */ -/* common/environment.o(.text) */ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c deleted file mode 100644 index d64025a..0000000 --- a/board/evb64260/zuma_pbb.c +++ /dev/null @@ -1,220 +0,0 @@ -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) -#include -#endif - -#include -#include -#include "zuma_pbb.h" - -#undef DEBUG - -#define PAT_LO 0x00010203 -#define PAT_HI 0x04050607 - -static PBB_DMA_REG_MAP *zuma_pbb_reg = NULL; -static char test_buf1[2048]; -static char test_buf2[2048]; -void zuma_init_pbb(void); -int zuma_mbox_init(void); -int zuma_test_dma(int cmd, int size); - -int zuma_test_dma (int cmd, int size) -{ - static const char *const test_legend[] = { - "write", "verify", - "copy", "compare", - "write inc", "verify inc" - }; - register int i, j; - unsigned int p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff); - unsigned int p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff); - volatile unsigned int *ps = (unsigned int *) p1; - volatile unsigned int *pd = (unsigned int *) p2; - unsigned int funct, pat_lo = PAT_LO, pat_hi = PAT_HI; - DMA_INT_STATUS stat; - int ret = 0; - - if (!zuma_pbb_reg) { - printf ("not initted\n"); - return -1; - } - - if (cmd < 0 || cmd > 5) { - printf ("inv cmd %d\n", cmd); - return -1; - } - - if (cmd == 2 || cmd == 3) { - /* not implemented */ - return 0; - } - - if (size <= 0 || size > 1024) - size = 1024; - - size &= (~7); /* throw away bottom 3 bits */ - - p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff); - p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff); - - memset ((void *) p1, 0, size); - memset ((void *) p2, 0, size); - - for (i = 0; i < size / 4; i += 2) { - ps[i] = pat_lo; - ps[i + 1] = pat_hi; - if (cmd == 4 || cmd == 5) { - unsigned char *pl = (unsigned char *) &pat_lo; - unsigned char *ph = (unsigned char *) &pat_hi; - - for (j = 0; j < 4; j++) { - pl[j] += 8; - ph[j] += 8; - } - } - } - - funct = (1 << 31) | (cmd << 24) | (size); - - zuma_pbb_reg->int_mask.pci_bits.chan0 = - EOF_RX_FLAG | EOF_TX_FLAG | EOB_TX_FLAG; - - zuma_pbb_reg->debug_57 = PAT_LO; /* patl */ - zuma_pbb_reg->debug_58 = PAT_HI; /* path */ - - zuma_pbb_reg->debug_54 = cpu_to_le32 (p1); /* src 0x01b0 */ - zuma_pbb_reg->debug_55 = cpu_to_le32 (p2); /* dst 0x01b8 */ - zuma_pbb_reg->debug_56 = cpu_to_le32 (funct); /* func, 0x01c0 */ - - /* give DMA time to chew on things.. dont use DRAM or PCI */ - /* if you can avoid it. */ - do { - for (i = 0; i < 1000 * 10; i++); - } while (le32_to_cpu (zuma_pbb_reg->debug_56) & (1 << 31)); - - stat.word = zuma_pbb_reg->status.word; - zuma_pbb_reg->int_mask.word = 0; - - printf ("stat: %08x (%x)\n", stat.word, stat.pci_bits.chan0); - - printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56)); - printf ("src @%08x: %08x %08x %08x %08x\n", p1, ps[0], ps[1], ps[2], - ps[3]); - printf ("dst @%08x: %08x %08x %08x %08x\n", p2, pd[0], pd[1], pd[2], - pd[3]); - printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56)); - - - if (cmd == 0 || cmd == 4) { - /* this is a write */ - if (!(stat.pci_bits.chan0 & EOF_RX_FLAG) || /* not done */ - (memcmp ((void *) ps, (void *) pd, size) != 0)) { /* cmp error */ - for (i = 0; i < size / 4; i += 2) { - if ((ps[i] != pd[i]) || (ps[i + 1] != pd[i + 1])) { - printf ("s @%p:%08x %08x\n", &ps[i], ps[i], ps[i + 1]); - printf ("d @%p:%08x %08x\n", &pd[i], pd[i], pd[i + 1]); - } - } - ret = -1; - } - } else { - /* this is a verify */ - if (!(stat.pci_bits.chan0 & EOF_TX_FLAG) || /* not done */ - (stat.pci_bits.chan0 & EOB_TX_FLAG)) { /* cmp error */ - printf ("%08x: %08x %08x\n", - le32_to_cpu (zuma_pbb_reg->debug_63), - zuma_pbb_reg->debug_61, zuma_pbb_reg->debug_62); - ret = -1; - } - } - - printf ("%s cmd %d, %d bytes: %s!\n", test_legend[cmd], cmd, size, - (ret == 0) ? "PASSED" : "FAILED"); - return 0; -} - -void zuma_init_pbb (void) -{ - unsigned int iobase; - pci_dev_t dev = - pci_find_device (VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); - - if (dev == -1) { - printf ("no zuma pbb\n"); - return; - } - - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0, &iobase); - - zuma_pbb_reg = - (PBB_DMA_REG_MAP *) (iobase & PCI_BASE_ADDRESS_MEM_MASK); - - if (!zuma_pbb_reg) { - printf ("zuma pbb bar none! (hah hah, get it?)\n"); - return; - } - - zuma_pbb_reg->int_mask.word = 0; - - printf ("pbb @ %p v%d.%d, timestamp %08x\n", zuma_pbb_reg, - zuma_pbb_reg->version.pci_bits.rev_major, - zuma_pbb_reg->version.pci_bits.rev_minor, - zuma_pbb_reg->timestamp); - -} - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -static int last_cmd = 4; /* write increment */ -static int last_size = 64; - -int -do_zuma_init_pbb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - zuma_init_pbb (); - return 0; -} - -int -do_zuma_test_dma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - if (argc > 1) { - last_cmd = simple_strtoul (argv[1], NULL, 10); - } - if (argc > 2) { - last_size = simple_strtoul (argv[2], NULL, 10); - } - zuma_test_dma (last_cmd, last_size); - return 0; -} - -int -do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - zuma_mbox_init (); - return 0; -} - -U_BOOT_CMD( - zinit, 1, 0, do_zuma_init_pbb, - "zinit - init zuma pbb\n", - "\n" - " - init zuma pbb\n" -); -U_BOOT_CMD( - zdtest, 3, 1, do_zuma_test_dma, - "zdtest - run dma test\n", - "[cmd [count]]\n" - " - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes\n" -); -U_BOOT_CMD( - zminit, 1, 0, do_zuma_init_mbox, - "zminit - init zuma mbox\n", - "\n" - " - init zuma mbox\n" -); - -#endif /* CFG_CMD_BSP */ diff --git a/board/evb64260/zuma_pbb.h b/board/evb64260/zuma_pbb.h deleted file mode 100644 index 300b2fe..0000000 --- a/board/evb64260/zuma_pbb.h +++ /dev/null @@ -1,346 +0,0 @@ -#ifndef ZUMA_PBB_H -#define ZUMA_PBB_H - -#define MAX_NUM_BUFFER_PER_RING 32 - -#ifdef __BIG_ENDIAN -#define cpu_bits _be_s_bits /* use with le32_to_cpu only */ -#define pci_bits _be_bits /* may contain swapped bytes, - but dont need le32_to_cpu */ -#endif - -#ifdef __LITTLE_ENDIAN -#define cpu_bits _le_bits -#define pci_bits _le_bits -#endif - -#define VENDOR_ID_ZUMA 0x1172 -#define DEVICE_ID_ZUMA_PBB 0x0004 - -#define RXDBP(chan) (&sip->rx_desc[chan].base) /* ch*8 */ -#define RXDP(chan) (&sip->rx_desc[chan].current) /* ch*8 + 4 */ -#define TXDBP(chan) (&sip->tx_desc[chan].base) /* ch*8 + 64 */ -#define TXDP(chan) (&sip->tx_desc[chan].current) /* ch*8 + 68 */ - -#define PBB_DMA_OWN_BIT 0x80000000 -#define PBB_DMA_LAST_BIT 0x40000000 - -#define EOF_RX_FLAG 1 /* bit 0 */ -#define EOB_RX_FLAG 2 /* bit 1 */ -#define EOF_TX_FLAG 4 /* bit 2 */ -#define EOB_TX_FLAG 8 /* bit 3 */ - -#define TX_MODE(m) (((m)&7) << 16) - -#define RX_DESC(i) (cs->rx_desc[i]) -#define TX_DESC(i) (cs->tx_desc[i]) - -#define RX_CONTROL(i) (RX_DESC(i).control.word) -#define RX_CONTROL_SIZE(i) (RX_DESC(i).control.rx.size) -#define TX_CONTROL(i) (TX_DESC(i).control.word) - -#define RX_DATA_P(i) (&RX_DESC(i).ptr) -#define TX_DATA_P(i) (&TX_DESC(i).ptr) - -typedef volatile unsigned char V8; -typedef volatile unsigned short V16; -typedef volatile unsigned int V32; - -/* RAM descriptor layout */ -typedef struct _tag_dma_descriptor { - V32 ptr; - union { - struct { - V32 owner:1; - V32 last:1; - V32 reserved0: 10; - V32 tx_mode: 4; - - V32 reserved1: 5; - V32 size: 11; - } tx; - struct { - V32 owner:1; - V32 last:1; - V32 reserved0: 14; - - V32 reserved1: 5; - V32 size: 11; - } rx; - V32 word; - } control; -} DMA_DESCRIPTOR; - -/* - * NOTE: DO NOT USE structure to write non-word values... all registers - * MUST be written 4 bytes at a time in SI version 0. - * Non-word writes will result in "unaccessed" bytes written as zero. - * - * Byte reads are allowed. - * - * V32 pads are because the registers are spaced every 8 bytes (64 bits) - * - */ - -/* NOTE!!! 4 dwords */ -typedef struct _tag_dma_descriptor_ring { - DMA_DESCRIPTOR *base; - V32 pad1; /* skip high dword */ - volatile DMA_DESCRIPTOR *current; - V32 pad3; /* skip high dword */ -} DMA_DESCRIPTOR_RING; - -/* 1 dword */ -typedef union _tag_dma_generic { - struct { /* byte 3 2 1 0 */ - V32 chan7:4; /* bits 31-28 */ - V32 chan6:4; /* bits 27-24 */ - V32 chan5:4; /* bits 23-20 */ - V32 chan4:4; /* bits 19-16 */ - V32 chan3:4; /* bits 15-12 */ - V32 chan2:4; /* bits 11-8 */ - V32 chan1:4; /* bits 7-4 */ - V32 chan0:4; /* bits 3-0 */ - } _be_s_bits; - struct { /* byte 0 1 2 3 */ - V32 chan1:4; /* bits 7-4 */ - V32 chan0:4; /* bits 3-0 */ - V32 chan3:4; /* bits 15-12 */ - V32 chan2:4; /* bits 11-8 */ - V32 chan5:4; /* bits 23-20 */ - V32 chan4:4; /* bits 19-16 */ - V32 chan7:4; /* bits 31-28 */ - V32 chan6:4; /* bits 27-24 */ - } _be_bits; - struct { /* byte 0 1 2 3 */ - V32 chan0:4; /* bits 0-3 */ - V32 chan1:4; /* bits 4-7 */ - V32 chan2:4; /* bits 8-11 */ - V32 chan3:4; /* bits 12-15 */ - V32 chan4:4; /* bits 16-19 */ - V32 chan5:4; /* bits 20-23 */ - V32 chan6:4; /* bits 24-27 */ - V32 chan7:4; /* bits 28-31 */ - } _le_bits; - V8 byte[4]; - V32 word; -} DMA_RXTX_ENABLE, DMA_RX_DELETE, - DMA_INT_STATUS, DMA_INT_MASK, - DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK; - -/* 1 dword */ -typedef union _tag_dma_rx_timer{ - struct { - V32 res0:8; /* bits 32-24 */ - V32 res1:7; /* bits 23-17 */ - V32 enable:1; /* bit 16 */ - V32 value:16; /* bits 15-0 */ - } _be_s_bits; - struct { - /* crosses byte boundary. must use swap. */ - V32 s_value:16; /* bits 7-0,15-8 */ - V32 enable:1; /* bit 16 */ - V32 res1:7; /* bits 23-17 */ - V32 res0:8; /* bits 32-24 */ - } _be_bits; - struct { - V32 value:16; /* bits 0-15 */ - V32 enable:1; /* bit 16 */ - V32 res1:7; /* bits 17-23 */ - V32 res0:8; /* bits 24-32 */ - } _le_bits; - V8 byte[4]; - V32 word; -} DMA_RX_TIMER; - -/* NOTE!!!: 2 dwords */ -typedef struct _tag_dma_desc_level{ - union { - struct { - V32 res1:8; /* bits 31-24 */ - V32 res0:7; /* bits 23-17 */ - V32 write:1; /* bit 16 */ - V32 thresh:8; /* bits 15-8 */ - V32 level:8; /* bits 7-0 */ - } _be_s_bits; - struct { - V32 level:8; /* bits 7-0 */ - V32 thresh:8; /* bits 15-8 */ - V32 res0:7; /* bits 30-17 */ - V32 write:1; /* bit 16 */ - V32 res1:8; /* bits 31-24 */ - } _be_bits; - struct { - V32 level:8; /* bits 0-7 */ - V32 thresh:8; /* bits 8-15 */ - V32 write:1; /* bit 16 */ - V32 res0:7; /* bit 17-30 */ - V32 res1:8; /* bits 24-31 */ - } _le_bits; - V8 byte[4]; - V32 word; - } desc; - V32 pad1; -} DMA_DESC_LEVEL; - -typedef struct _tag_pbb_dma_reg_map { - /* 0-15 (0x000-0x078) */ - DMA_DESCRIPTOR_RING rx_desc[8]; /* 4 dwords each, 128 bytes tot. */ - - /* 16-31 (0x080-0x0f8) */ - DMA_DESCRIPTOR_RING tx_desc[8]; /* 4 dwords each, 128 bytes tot. */ - - /* 32/33 (0x100/0x108) */ - V32 reserved_32; - V32 pad_32; - V32 reserved_33; - V32 pad_33; - - /* 34 (0x110) */ - DMA_RXTX_ENABLE rxtx_enable; - V32 pad_34; - - /* 35 (0x118) */ - DMA_RX_DELETE rx_delete; - V32 pad_35; - - /* 36-38 (0x120-0x130) */ - DMA_INT_STATUS status; - V32 pad_36; - DMA_INT_STATUS last_status; - V32 pad_37; - DMA_INT_MASK int_mask; - V32 pad_38; - - /* 39/40 (0x138/0x140) */ - union { - /* NOTE!! 4 dwords */ - struct { - V32 channel_3:8; - V32 channel_2:8; - V32 channel_1:8; - V32 channel_0:8; - V32 pad1; - V32 channel_7:8; - V32 channel_6:8; - V32 channel_5:8; - V32 channel_4:8; - V32 pad3; - } _be_s_bits; - struct { - V32 channel_0:8; - V32 channel_1:8; - V32 channel_2:8; - V32 channel_3:8; - V32 pad1; - V32 channel_4:8; - V32 channel_5:8; - V32 channel_6:8; - V32 channel_7:8; - V32 pad3; - } _be_bits, _le_bits; - V8 byte[16]; - V32 word[4]; - } rx_size; - - /* 41/42 (0x148/0x150) */ - V32 reserved_41; - V32 pad_41; - V32 reserved_42; - V32 pad_42; - - /* 43/44 (0x158/0x160) */ - DMA_RX_LEVEL_STATUS rx_level_status; - V32 pad_43; - DMA_RX_LEVEL_INT_MASK rx_level_int_mask; - V32 pad_44; - - /* 45 (0x168) */ - DMA_RX_TIMER rx_timer; - V32 pad_45; - - /* 46 (0x170) */ - V32 reserved_46; - V32 pad_46; - - /* 47 (0x178) */ - V32 mbox_status; - V32 pad_47; - - /* 48/49 (0x180/0x188) */ - V32 mbox_out; - V32 pad_48; - V32 mbox_in; - V32 pad_49; - - /* 50 (0x190) */ - V32 config; - V32 pad_50; - - /* 51/52 (0x198/0x1a0) */ - V32 c2a_ctr; - V32 pad_51; - V32 a2c_ctr; - V32 pad_52; - - /* 53 (0x1a8) */ - union { - struct { - V32 rev_major:8; /* bits 31-24 */ - V32 rev_minor:8; /* bits 23-16 */ - V32 reserved:16; /* bits 15-0 */ - } _be_s_bits; - struct { - V32 s_reserved:16; /* bits 7-0, 15-8 */ - V32 rev_minor:8; /* bits 23-16 */ - V32 rev_major:8; /* bits 31-24 */ - } _be_bits; - struct { - V32 reserved:16; /* bits 0-15 */ - V32 rev_minor:8; /* bits 16-23 */ - V32 rev_major:8; /* bits 24-31 */ - } _le_bits; - V8 byte[4]; - V32 word; - } version; - V32 pad_53; - - /* 54-59 (0x1b0-0x1d8) */ - V32 debug_54; - V32 pad_54; - V32 debug_55; - V32 pad_55; - V32 debug_56; - V32 pad_56; - V32 debug_57; - V32 pad_57; - V32 debug_58; - V32 pad_58; - V32 debug_59; - V32 pad_59; - - /* 60 (0x1e0) */ - V32 timestamp; - V32 pad_60; - - /* 61-63 (0x1e8-0x1f8) */ - V32 debug_61; - V32 pad_61; - V32 debug_62; - V32 pad_62; - V32 debug_63; - V32 pad_63; - - /* 64-71 (0x200 - 0x238) */ - DMA_DESC_LEVEL rx_desc_level[8]; /* 2 dwords each, 32 bytes tot. */ - - /* 72-98 (0x240 - 0x2f8) */ - /* reserved */ - - /* 96-127 (0x300 - 0x3f8) */ - /* mirrors (0x100 - 0x1f8) */ - -} PBB_DMA_REG_MAP; - - -#endif /* ZUMA_PBB_H */ diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c deleted file mode 100644 index 2b9a469..0000000 --- a/board/evb64260/zuma_pbb_mbox.c +++ /dev/null @@ -1,187 +0,0 @@ -#include -#include -#include -#include - -#include "zuma_pbb.h" -#include "zuma_pbb_mbox.h" - - -struct _zuma_mbox_dev zuma_mbox_dev; - - -static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data) -{ - unsigned int status, count = 0, i; - - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - - while((status & OUT_PENDING) && count < 1000) { - count++; - for(i=0;i<1000;i++); - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - } - if(count < 1000) { - /* if SET it means msg pending */ - /* printf("mbox real write %08x\n",data); */ - dev->sip->mbox_out = cpu_to_le32(data); - return 4; - } - - printf("mbox tx timeout\n"); - return 0; -} - -static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data) -{ - unsigned int status, count = 0, i; - - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - - while(!(status & IN_VALID) && count < 1000) { - count++; - for(i=0;i<1000;i++); - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - } - if(count < 1000) { - /* if SET it means msg pending */ - *data=le32_to_cpu(dev->sip->mbox_in); - /*printf("mbox real read %08x\n", *data); */ - return 4; - } - printf("mbox rx timeout\n"); - return 0; -} - -static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in) -{ - int ret; - ret=zuma_mbox_write(&zuma_mbox_dev,out); - /*printf("write 0x%08x (%d bytes)\n", out, ret); */ - if(ret!=4) return -1; - ret=zuma_mbox_read(&zuma_mbox_dev,in); - /*printf("read 0x%08x (%d bytes)\n", *in, ret); */ - if(ret!=4) return -1; - return 0; -} - - -#define RET_IF_FAILED(x) if ((x) == -1) return -1 - -static int zuma_mbox_do_all_mailbox(void) -{ - unsigned int data_in; - unsigned short sdata_in; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in)); - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in)); - memcpy(zuma_acc_mac+2,&data_in,4); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in)); - sdata_in=data_in&0xffff; - memcpy(zuma_acc_mac,&sdata_in,2); - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in)); - zuma_ip=data_in; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in)); - zuma_slot_bac=data_in>>3; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in)); - zuma_console_baud = data_in & 0xffff; - zuma_debug_baud = data_in >> 16; - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in)); - memcpy(zuma_prv_mac+2,&data_in,4); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in)); - sdata_in=data_in&0xffff; - memcpy(zuma_prv_mac,&sdata_in,2); - - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in)); - - return 0; -} - - -static void -zuma_mbox_dump(void) -{ - printf("ACC MAC=%04x%08x\n",*(unsigned short *)(&zuma_acc_mac),*(unsigned int *)((char *)&zuma_acc_mac+2)); - printf("PRV MAC=%04x%08x\n",*(unsigned short *)(&zuma_prv_mac),*(unsigned int *)((char *)&zuma_prv_mac+2)); - printf("slot:bac=%d:%d\n",(zuma_slot_bac>>2)&0xf, zuma_slot_bac & 0x3); - printf("BAUD1=%d BAUD2=%d\n",zuma_console_baud,zuma_debug_baud); -} - - -static void -zuma_mbox_setenv(void) -{ - char *data, buf[32]; - unsigned char save = 0; - - data = getenv("baudrate"); - - if(!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) { - sprintf(buf, "%6d", zuma_console_baud); - setenv("baudrate", buf); - save=1; - printf("baudrate doesn't match from mbox\n"); - } - - ip_to_string(zuma_ip, buf); - setenv("ipaddr", buf); - - sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x", - zuma_prv_mac[0], - zuma_prv_mac[1], - zuma_prv_mac[2], - zuma_prv_mac[3], - zuma_prv_mac[4], - zuma_prv_mac[5]); - setenv("ethaddr", buf); - - sprintf(buf,"%02x",zuma_slot_bac); - setenv("bacslot", buf); - - if(save) - saveenv(); -} - -/** - * zuma_mbox_init: - */ - -int zuma_mbox_init(void) -{ - unsigned int iobase; - memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev)); - - zuma_mbox_dev.dev = pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); - - if(zuma_mbox_dev.dev == -1) { - printf("no zuma pbb\n"); - return -1; - } - - pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase); - - zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) (iobase & PCI_BASE_ADDRESS_MEM_MASK); - - zuma_mbox_dev.sip->int_mask.word=0; - - printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip, - zuma_mbox_dev.sip->version.pci_bits.rev_major, - zuma_mbox_dev.sip->version.pci_bits.rev_minor, - zuma_mbox_dev.sip->timestamp); - - if (zuma_mbox_do_all_mailbox() == -1) { - printf("mailbox failed.. no ACC?\n"); - return -1; - } - - zuma_mbox_dump(); - - zuma_mbox_setenv(); - - return 0; -} diff --git a/board/evb64260/zuma_pbb_mbox.h b/board/evb64260/zuma_pbb_mbox.h deleted file mode 100644 index b4a4c0c..0000000 --- a/board/evb64260/zuma_pbb_mbox.h +++ /dev/null @@ -1,43 +0,0 @@ -#define IN_VALID 1 -#define OUT_PENDING 2 - -enum { - ZUMA_MBOXMSG_DONE, - ZUMA_MBOXMSG_MACL, - ZUMA_MBOXMSG_MACH, - ZUMA_MBOXMSG_IP, - ZUMA_MBOXMSG_SLOT, - ZUMA_MBOXMSG_RESET, - ZUMA_MBOXMSG_BAUD, - ZUMA_MBOXMSG_START, - ZUMA_MBOXMSG_ENG_PRV_MACL, - ZUMA_MBOXMSG_ENG_PRV_MACH, - - MBOXMSG_LAST -}; - -struct zuma_mailbox_info { - unsigned char acc_mac[6]; - unsigned char prv_mac[6]; - unsigned int ip; - unsigned int slot_bac; - unsigned int console_baud; - unsigned int debug_baud; -}; - -struct _zuma_mbox_dev { - pci_dev_t dev; - PBB_DMA_REG_MAP *sip; - struct zuma_mailbox_info mailbox; -}; - -#define zuma_prv_mac zuma_mbox_dev.mailbox.prv_mac -#define zuma_acc_mac zuma_mbox_dev.mailbox.acc_mac -#define zuma_ip zuma_mbox_dev.mailbox.ip -#define zuma_slot_bac zuma_mbox_dev.mailbox.slot_bac -#define zuma_console_baud zuma_mbox_dev.mailbox.console_baud -#define zuma_debug_baud zuma_mbox_dev.mailbox.debug_baud - - -extern struct _zuma_mbox_dev zuma_mbox_dev; -extern int zuma_mbox_init (void); diff --git a/board/exbitgen/Makefile b/board/exbitgen/Makefile deleted file mode 100644 index 34bd4b2..0000000 --- a/board/exbitgen/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -SOBJS = init.o - - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/exbitgen/config.mk b/board/exbitgen/config.mk deleted file mode 100644 index 42ea0c6..0000000 --- a/board/exbitgen/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# ExbitGen board -# - -LDFLAGS += $(LINKER_UNDEFS) - -TEXT_BASE := 0xFFF80000 -#TEXT_BASE := 0x00100000 - -PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS) diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c deleted file mode 100644 index 39a9722..0000000 --- a/board/exbitgen/exbitgen.c +++ /dev/null @@ -1,117 +0,0 @@ -#include -#include -#include -#include "exbitgen.h" - -/* ************************************************************************ */ -int board_early_init_f (void) -/* ------------------------------------------------------------------------ -- - * Purpose : - * Remarks : - * Restrictions: - * See also : - * Example : - * ************************************************************************ */ -{ - unsigned long i; - - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* Perform reset of PHY connected to PPC via register in CPLD */ - out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */ - for (i = 0; i < 10000000; i++) { - ; - } - out8 (PHY_CTRL_ADDR, 0x2f); /* deactivate nRESET */ - - return 0; -} - - -/* ************************************************************************ */ -int checkboard (void) -/* ------------------------------------------------------------------------ -- - * Purpose : - * Remarks : - * Restrictions: - * See also : - * Example : - * ************************************************************************ */ -{ - printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR)); - return (0); -} - -/* ************************************************************************ */ -long int initdram (int board_type) -/* ------------------------------------------------------------------------ -- - * Purpose : Determines size of mounted DRAM. - * Remarks : Size is determined by reading SDRAM configuration registers as - * set up by sdram_init. - * Restrictions: - * See also : - * Example : - * ************************************************************************ */ -{ - ulong tot_size; - ulong bank_size; - ulong tmp; - - tot_size = 0; - - mtdcr (memcfga, mem_mb0cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (memcfga, mem_mb1cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (memcfga, mem_mb2cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (memcfga, mem_mb3cf); - tmp = mfdcr (memcfgd); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - return tot_size; -} diff --git a/board/exbitgen/exbitgen.h b/board/exbitgen/exbitgen.h deleted file mode 100644 index 058ad48..0000000 --- a/board/exbitgen/exbitgen.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define GPIO_CPU_LED GPIO_3 - - -#define CPLD_BASE 0x10000000 /* t.b.m. */ -#define DEBUG_LEDS_ADDR CPLD_BASE + 0x01 -#define HW_ID_ADDR CPLD_BASE + 0x02 -#define DIP_SWITCH_ADDR CPLD_BASE + 0x04 -#define PHY_CTRL_ADDR CPLD_BASE + 0x05 -#define SPI_OUT_ADDR CPLD_BASE + 0x07 -#define SPI_IN_ADDR CPLD_BASE + 0x08 -#define MDIO_OUT_ADDR CPLD_BASE + 0x09 -#define MDIO_IN_ADDR CPLD_BASE + 0x0A -#define MISC_OUT_ADDR CPLD_BASE + 0x0B - -/* Addresses used on I2C bus */ -#define LM75_CHIP_ADDR 0x9C -#define LM75_CPU_ADDR 0x9E -#define SDRAM_SPD_ADDR 0xA0 - -#define SDRAM_SPD_WRITE_ADDRESS (SDRAM_SPD_ADDR) -#define SDRAM_SPD_READ_ADDRESS (SDRAM_SPD_ADDR+1) - -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef TRUE -#define TRUE 1 -#endif diff --git a/board/exbitgen/flash.c b/board/exbitgen/flash.c deleted file mode 100644 index ae88994..0000000 --- a/board/exbitgen/flash.c +++ /dev/null @@ -1,597 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -#ifdef MEIGSBOARD_ONBOARD_FLASH /* onboard = 2MB */ -# ifdef CONFIG_EXBITGEN -# define FLASH_WORD_SIZE unsigned long -# endif -#else /* Meigsboard socket flash = 512KB */ -# ifdef CONFIG_EXBITGEN -# define FLASH_WORD_SIZE unsigned char -# endif -#endif - -#ifdef CONFIG_EXBITGEN -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char -#endif - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long bank_size; - unsigned long tot_size; - unsigned long bank_addr; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = 0; - } - - tot_size = 0; - - /* Detect Boot Flash */ - bank_addr = CFG_FLASH0_BASE; - bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[0]); - if (bank_size > 0) { - (void)flash_protect(FLAG_PROTECT_CLEAR, - bank_addr, - bank_addr + bank_size - 1, - &flash_info[0]); - } - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Boot Flash Bank\n"); - } - flash_info[0].size = bank_size; - tot_size += bank_size; - - /* Detect Application Flash */ - bank_addr = CFG_FLASH1_BASE; - for (i = 1; i < CFG_MAX_FLASH_BANKS; ++i) { - bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[i]); - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - break; - } - if (bank_size > 0) { - (void)flash_protect(FLAG_PROTECT_CLEAR, - bank_addr, - bank_addr + bank_size - 1, - &flash_info[i]); - } - flash_info[i].size = bank_size; - tot_size += bank_size; - bank_addr += bank_size; - } - if (flash_info[1].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Application Flash Bank\n"); - } - - /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#if 0xfffffffc >= CFG_FLASH0_BASE -#if 0xfffffffc <= CFG_FLASH0_BASE + CFG_FLASH0_SIZE - 1 - flash_protect(FLAG_PROTECT_SET, - 0xfffffffc, 0xffffffff, - &flash_info[0]); -#endif -#endif -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return tot_size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDLV033C: printf ("AM29LV033C (32 Mbit, uniform sector size)\n"); - break; - case FLASH_AMDLV065D: printf ("AM29LV065D (64 Mbit, uniform sector size)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV065D: - info->flash_id += FLASH_AMDLV065D; - info->sector_count = 128; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - case (FLASH_WORD_SIZE)SST_ID_xF040: - info->flash_id += FLASH_SST040; - info->sector_count = 128; - info->size = 0x00080000; - break; /* => 512KB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040) || - (info->flash_id == FLASH_AMDLV033C) || - (info->flash_id == FLASH_AMDLV065D)) { - ulong sectsize = info->size / info->sector_count; - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sectsize); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* switch to the read mode */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while ((addr2[0] & 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now=get_timer(start)) > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; - } - } - - printf (" done\n"); - - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile ulong *)dest) & data) != data) { - printf("dest = %08lx, *dest = %08lx, data = %08lx\n", - dest, *(volatile ulong *)dest, data); - return 2; - } - - for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & 0x00800080) != (data2[i] & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - addr2[0] = (FLASH_WORD_SIZE)0x00F000F0; - return (1); - } - } - } - - addr2[0] = (FLASH_WORD_SIZE)0x00F000F0; - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S deleted file mode 100644 index 0e6cd04..0000000 --- a/board/exbitgen/init.S +++ /dev/null @@ -1,1009 +0,0 @@ -/*----------------------------------------------------------------------+ - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *----------------------------------------------------------------------- - */ - -#include -#include -#include "config.h" - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ -#define FPGA_BRDC 0xF0300004 - -#include -#include - -#include -#include - -#include "exbitgen.h" - -/* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */ -/* c-code declarations and consequently can't be included here). */ -/* (Possibly to be solved somehow else). */ -/*--------------------------------------------------------------------- */ -#define I2C_REGISTERS_BASE_ADDRESS 0xEF600500 -#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF) -#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF) -#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR) -#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR) -#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL) -#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL) -#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS) -#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) -#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) -#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) -#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV) -#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) -#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) -#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) -#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL) - -/* MDCNTL Register Bit definition */ -#define IIC_MDCNTL_HSCL 0x01 -#define IIC_MDCNTL_EUBS 0x02 -#define IIC_MDCNTL_FMDB 0x40 -#define IIC_MDCNTL_FSDB 0x80 - -/* CNTL Register Bit definition */ -#define IIC_CNTL_PT 0x01 -#define IIC_CNTL_READ 0x02 -#define IIC_CNTL_CHT 0x04 - -/* STS Register Bit definition */ -#define IIC_STS_PT 0X01 -#define IIC_STS_ERR 0X04 -#define IIC_STS_MDBS 0X20 - -/* EXTSTS Register Bit definition */ -#define IIC_EXTSTS_XFRA 0X01 -#define IIC_EXTSTS_ICT 0X02 -#define IIC_EXTSTS_LA 0X04 - -/* LED codes used for inditing progress and errors during read of DIMM SPD. */ -/*--------------------------------------------------------------------- */ -#define LED_SDRAM_CODE_1 0xef -#define LED_SDRAM_CODE_2 0xee -#define LED_SDRAM_CODE_3 0xed -#define LED_SDRAM_CODE_4 0xec -#define LED_SDRAM_CODE_5 0xeb -#define LED_SDRAM_CODE_6 0xea -#define LED_SDRAM_CODE_7 0xe9 -#define LED_SDRAM_CODE_8 0xe8 -#define LED_SDRAM_CODE_9 0xe7 -#define LED_SDRAM_CODE_10 0xe6 -#define LED_SDRAM_CODE_11 0xe5 -#define LED_SDRAM_CODE_12 0xe4 -#define LED_SDRAM_CODE_13 0xe3 -#define LED_SDRAM_CODE_14 0xe2 -#define LED_SDRAM_CODE_15 0xe1 -#define LED_SDRAM_CODE_16 0xe0 - - -#define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100 - -#define FLASH_8bit_AP 0x9B015480 -#define FLASH_8bit_CR 0xFFF18000 /* 1MB(min), 8bit, R/W */ - -#define FLASH_32bit_AP 0x9B015480 -#define FLASH_32bit_CR 0xFFE3C000 /* 2MB, 32bit, R/W */ - - -#define WDCR_EBC(reg,val) addi r4,0,reg;\ - mtdcr ebccfga,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr ebccfgd,r4 - -/*--------------------------------------------------------------------- - * Function: ext_bus_cntlr_init - * Description: Initializes the External Bus Controller for the external - * peripherals. IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * Bank 0 - Boot flash - * Bank 1-4 - application flash - * Bank 5 - CPLD - * Bank 6 - not used - * Bank 7 - Heathrow chip - *--------------------------------------------------------------------- - */ - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ - - mflr r31 /* save link register */ - - /*----------------------------------------------------------- - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *----------------------------------------------------------- - */ - - addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /*--------------------------------------------------------------- - * Memory Bank 0 (Boot Flash) initialization - *--------------------------------------------------------------- - */ - WDCR_EBC(pb0ap, FLASH_32bit_AP) - WDCR_EBC(pb0cr, 0xffe38000) -/*pnc WDCR_EBC(pb0cr, FLASH_32bit_CR) */ - - /*--------------------------------------------------------------- - * Memory Bank 5 (CPLD) initialization - *--------------------------------------------------------------- - */ - WDCR_EBC(pb5ap, 0x01010040) -/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */ - WDCR_EBC(pb5cr, 0x10038000) - - /*--------------------------------------------------------------- */ - /* Memory Bank 6 (not used) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(pb6cr, 0x00000000) - - /* Read HW ID to determine whether old H2 board or new generic CPU board */ - addis r3, 0, HW_ID_ADDR@h - ori r3, r3, HW_ID_ADDR@l - lbz r3,0x0000(r3) - cmpi 0, r3, 1 /* if (HW_ID==1) */ - beq setup_h2evalboard /* then jump */ - cmpi 0, r3, 2 /* if (HW_ID==2) */ - beq setup_genieboard /* then jump */ - cmpi 0, r3, 3 /* if (HW_ID==3) */ - beq setup_genieboard /* then jump */ - -setup_genieboard: - /*--------------------------------------------------------------- */ - /* Memory Bank 1 (Application Flash) initialization for generic CPU board */ - /*--------------------------------------------------------------- */ -/* WDCR_EBC(pb1ap, 0x7b015480) /###* T.B.M. */ -/* WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb1ap, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */ - -/* WDCR_EBC(pb1cr, 0x20098000) /###* 16 MB */ - WDCR_EBC(pb1cr, 0x200B8000) /* 32 MB */ - - /*--------------------------------------------------------------- */ - /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */ - /*--------------------------------------------------------------- */ - WDCR_EBC(pb4ap, 0x01010000) /* */ - WDCR_EBC(pb4cr, 0x1021c000) /* */ - - /*--------------------------------------------------------------- */ - /* Memory Bank 7 (Heathrow chip on Reference board) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(pb7ap, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */ - WDCR_EBC(pb7cr, 0X4001A000) - - bl setup_continue - - -setup_h2evalboard: - /*--------------------------------------------------------------- */ - /* Memory Bank 1 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(pb1ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb1cr, 0x20058000) - - /*--------------------------------------------------------------- */ - /* Memory Bank 2 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(pb2ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb2ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb2cr, 0x20458000) - - /*--------------------------------------------------------------- */ - /* Memory Bank 3 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(pb3ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb3ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb3cr, 0x20858000) - - /*--------------------------------------------------------------- */ - /* Memory Bank 4 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(pb4ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb4ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb4cr, 0x20C58000) - - /*--------------------------------------------------------------- */ - /* Memory Bank 7 (Heathrow chip) initialization */ - /*--------------------------------------------------------------- */ - WDCR_EBC(pb7ap, 0x02000280) /* No Ready, 4 wait states */ - WDCR_EBC(pb7cr, 0X4001A000) - -setup_continue: - - - mtlr r31 /* restore lr */ - nop /* pass2 DCR errata #8 */ - blr - -/*--------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: Configures SDRAM memory banks. */ -/*--------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: -#if CFG_MONITOR_BASE < CFG_FLASH_BASE - blr -#else - mflr r31 - - /* output SDRAM code on LEDs */ - addi r4, 0, LED_SDRAM_CODE_1 - addis r5, 0, 0x1000 - ori r5, r5, 0x0001 - stb r4,0(r5) - eieio - - /* Read contents of spd */ - /*--------------------- */ - bl read_spd - - /*----------------------------------------------------------- */ - /* */ - /* */ - /* Update SDRAM timing register */ - /* */ - /* */ - /*----------------------------------------------------------- */ - - /* Read PLL feedback divider and calculate clock period of local bus in */ - /* granularity of 10 ps. Save clock period in r30 */ - /*-------------------------------------------------------------- */ - mfdcr r4, pllmd - addi r9, 0, 25 - srw r4, r4, r9 - andi. r4, r4, 0x07 - addis r5, 0, TIMEBASE_10PS@h - ori r5, r5, TIMEBASE_10PS@l - divwu r30, r5, r4 - - /* Determine CASL */ - /*--------------- */ - bl find_casl /* Returns CASL in r3 */ - - /* Calc trp_clocks = (trp * 100 + (clk - 1)) / clk */ - /* (trp read from byte 27 in granularity of 1 ns) */ - /*------------------------------------------------ */ - mulli r16, r16, 100 - add r16, r16, r30 - addi r6, 0, 1 - subf r16, r6, r16 - divwu r16, r16, r30 - - /* Calc trcd_clocks = (trcd * 100 + (clk - 1) ) / clk */ - /* (trcd read from byte 29 in granularity of 1 ns) */ - /*--------------------------------------------------- */ - mulli r17, r17, 100 - add r17, r17, r30 - addi r6, 0, 1 - subf r17, r6, r17 - divwu r17, r17, r30 - - /* Calc tras_clocks = (tras * 100 + (clk - 1) ) / clk */ - /* (tras read from byte 30 in granularity of 1 ns) */ - /*--------------------------------------------------- */ - mulli r18, r18, 100 - add r18, r18, r30 - addi r6, 0, 1 - subf r18, r6, r18 - divwu r18, r18, r30 - - /* Calc trc_clocks = trp_clocks + tras_clocks */ - /*------------------------------------------- */ - add r18, r18, r16 - - /* CASL value */ - /*----------- */ - addi r9, 0, 23 - slw r4, r3, r9 - - /* PTA = trp_clocks - 1 */ - /*--------------------- */ - addi r6, 0, 1 - subf r5, r6, r16 - addi r9, 0, 18 - slw r5, r5, r9 - or r4, r4, r5 - - /* CTP = trc_clocks - trp_clocks - trcd_clocks - 1 */ - /*------------------------------------------------ */ - addi r5, r18, 0 - subf r5, r16, r5 - subf r5, r17, r5 - addi r6, 0, 1 - subf r5, r6, r5 - addi r9, 0, 16 - slw r5, r5, r9 - or r4, r4, r5 - - /* LDF = 1 */ - /*-------- */ - ori r4, r4, 0x4000 - - /* RFTA = trc_clocks - 4 */ - /*---------------------- */ - addi r6, 0, 4 - subf r5, r6, r18 - addi r9, 0, 2 - slw r5, r5, r9 - or r4, r4, r5 - - /* RCD = trcd_clocks - 1 */ - /*---------------------- */ - addi r6, 0, 1 - subf r5, r6, r17 - or r4, r4, r5 - - /*----------------------------------------------------------- */ - /* Set SDTR1 */ - /*----------------------------------------------------------- */ - addi r5,0,mem_sdtr1 - mtdcr memcfga,r5 - mtdcr memcfgd,r4 - - /*----------------------------------------------------------- */ - /* */ - /* */ - /* Update memory bank 0-3 configuration registers */ - /* */ - /* */ - /*----------------------------------------------------------- */ - - /* Build contents of configuration register for bank 0 into r6 */ - /*------------------------------------------------------------ */ - bl find_mode /* returns addressing mode in r3 */ - addi r29, r3, 0 /* save mode temporarily in r29 */ - bl find_size_code /* returns size code in r3 */ - addi r9, 0, 17 /* bit offset of size code in configuration register */ - slw r3, r3, r9 /* */ - addi r9, 0, 13 /* bit offset of addressing mode in configuration register */ - slw r29, r29, r9 /* */ - or r3, r29, r3 /* merge size code and addressing mode */ - ori r6, r3, CFG_SDRAM_BASE + 1 /* insert base address and enable bank */ - - /* Calculate banksize r15 = (density << 22) / 2 */ - /*--------------------------------------------- */ - addi r9, 0, 21 - slw r15, r15, r9 - - /* Set SDRAM bank 0 register and adjust r6 for next bank */ - /*------------------------------------------------------ */ - addi r7,0,mem_mb0cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 - - add r6, r6, r15 /* add bank size to base address for next bank */ - - /* If two rows/banks then set SDRAM bank 1 register and adjust r6 for next bank */ - /*---------------------------------------------------------------------------- */ - cmpi 0, r12, 2 - bne b1skip - - addi r7,0,mem_mb1cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 - - add r6, r6, r15 /* add bank size to base address for next bank */ - - /* Set SDRAM bank 2 register and adjust r6 for next bank */ - /*------------------------------------------------------ */ -b1skip: addi r7,0,mem_mb2cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 - - add r6, r6, r15 /* add bank size to base address for next bank */ - - /* If two rows/banks then set SDRAM bank 3 register */ - /*------------------------------------------------ */ - cmpi 0, r12, 2 - bne b3skip - - addi r7,0,mem_mb3cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 -b3skip: - - /*----------------------------------------------------------- */ - /* Set RTR */ - /*----------------------------------------------------------- */ - cmpi 0, r30, 1600 - bge rtr_1 - addis r7, 0, 0x05F0 /* RTR value for 100Mhz */ - bl rtr_2 -rtr_1: addis r7, 0, 0x03F8 -rtr_2: addi r4,0,mem_rtr - mtdcr memcfga,r4 - mtdcr memcfgd,r7 - - /*----------------------------------------------------------- */ - /* Delay to ensure 200usec have elapsed since reset. Assume worst */ - /* case that the core is running 200Mhz: */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*----------------------------------------------------------- */ - addis r3,0,0x0000 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp2: - bdnz ..spinlp2 /* spin loop */ - - /*----------------------------------------------------------- */ - /* Set memory controller options reg, MCOPT1. */ - /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ - /* read/prefetch. */ - /*----------------------------------------------------------- */ - addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 - addis r4,0,0x80C0 /* set DC_EN=1 */ - ori r4,r4,0x0000 - mtdcr memcfgd,r4 - - - /*----------------------------------------------------------- */ - /* Delay to ensure 10msec have elapsed since reset. This is */ - /* required for the MPC952 to stabalize. Assume worst */ - /* case that the core is running 200Mhz: */ - /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */ - /* This delay should occur before accessing SDRAM. */ - /*----------------------------------------------------------- */ - addis r3,0,0x001E - ori r3,r3,0x8480 /* ensure 10msec have passed since reset */ - mtctr r3 -..spinlp3: - bdnz ..spinlp3 /* spin loop */ - - /* output SDRAM code on LEDs */ - addi r4, 0, LED_SDRAM_CODE_16 - addis r5, 0, 0x1000 - ori r5, r5, 0x0001 - stb r4,0(r5) - eieio - - mtlr r31 /* restore lr */ - blr - -/*--------------------------------------------------------------------- */ -/* Function: read_spd */ -/* Description: Reads contents of SPD and saves parameters to be used for */ -/* configuration in dedicated registers (see code below). */ -/*--------------------------------------------------------------------- */ - -#define WRITE_I2C(reg,val) \ - addi r3,0,val;\ - addis r4, 0, 0xef60;\ - ori r4, r4, 0x0500 + reg;\ - stb r3, 0(r4);\ - eieio - -#define READ_I2C(reg) \ - addis r3, 0, 0xef60;\ - ori r3, r3, 0x0500 + reg;\ - lbz r3, 0x0000(r3);\ - eieio - -read_spd: - - mflr r5 - - /* Initialize i2c */ - /*--------------- */ - WRITE_I2C(IICLMADR, 0x00) /* clear lo master address */ - WRITE_I2C(IICHMADR, 0x00) /* clear hi master address */ - WRITE_I2C(IICLSADR, 0x00) /* clear lo slave address */ - WRITE_I2C(IICHSADR, 0x00) /* clear hi slave address */ - WRITE_I2C(IICSTS, 0x08) /* update status register */ - WRITE_I2C(IICEXTSTS, 0x8f) - WRITE_I2C(IICCLKDIV, 0x05) - WRITE_I2C(IICINTRMSK, 0x00) /* no interrupts */ - WRITE_I2C(IICXFRCNT, 0x00) /* clear transfer count */ - WRITE_I2C(IICXTCNTLSS, 0xf0) /* clear extended control & stat */ - WRITE_I2C(IICMDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB) /* mode control */ - READ_I2C(IICMDCNTL) - ori r3, r3, IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL - WRITE_I2C(IICMDCNTL, r3) /* mode control */ - WRITE_I2C(IICCNTL, 0x00) /* clear control reg */ - - /* Wait until initialization completed */ - /*------------------------------------ */ - bl wait_i2c_transfer_done - - WRITE_I2C(IICHMADR, 0x00) /* 7-bit addressing */ - WRITE_I2C(IICLMADR, SDRAM_SPD_WRITE_ADDRESS) - - /* Write 0 into buffer(start address) */ - /*----------------------------------- */ - WRITE_I2C(IICMDBUF, 0x00); - - /* Wait a little */ - /*-------------- */ - addis r3,0,0x0000 - ori r3,r3,0xA000 - mtctr r3 -in02: bdnz in02 - - /* Issue write command */ - /*-------------------- */ - WRITE_I2C(IICCNTL, IIC_CNTL_PT) - bl wait_i2c_transfer_done - - /* Read 128 bytes */ - /*--------------- */ - addi r7, 0, 0 /* byte counter in r7 */ - addi r8, 0, 0 /* checksum in r8 */ -rdlp: - /* issue read command */ - /*------------------- */ - cmpi 0, r7, 127 - blt rd01 - WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT) - bl rd02 -rd01: WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT) -rd02: bl wait_i2c_transfer_done - - /* Fetch byte from buffer */ - /*----------------------- */ - READ_I2C(IICMDBUF) - - /* Retrieve parameters that are going to be used during configuration. */ - /* Save them in dedicated registers. */ - /*------------------------------------------------------------ */ - cmpi 0, r7, 3 /* Save byte 3 in r10 */ - bne rd10 - addi r10, r3, 0 -rd10: cmpi 0, r7, 4 /* Save byte 4 in r11 */ - bne rd11 - addi r11, r3, 0 -rd11: cmpi 0, r7, 5 /* Save byte 5 in r12 */ - bne rd12 - addi r12, r3, 0 -rd12: cmpi 0, r7, 17 /* Save byte 17 in r13 */ - bne rd13 - addi r13, r3, 0 -rd13: cmpi 0, r7, 18 /* Save byte 18 in r14 */ - bne rd14 - addi r14, r3, 0 -rd14: cmpi 0, r7, 31 /* Save byte 31 in r15 */ - bne rd15 - addi r15, r3, 0 -rd15: cmpi 0, r7, 27 /* Save byte 27 in r16 */ - bne rd16 - addi r16, r3, 0 -rd16: cmpi 0, r7, 29 /* Save byte 29 in r17 */ - bne rd17 - addi r17, r3, 0 -rd17: cmpi 0, r7, 30 /* Save byte 30 in r18 */ - bne rd18 - addi r18, r3, 0 -rd18: cmpi 0, r7, 9 /* Save byte 9 in r19 */ - bne rd19 - addi r19, r3, 0 -rd19: cmpi 0, r7, 23 /* Save byte 23 in r20 */ - bne rd20 - addi r20, r3, 0 -rd20: cmpi 0, r7, 25 /* Save byte 25 in r21 */ - bne rd21 - addi r21, r3, 0 -rd21: - - /* Calculate checksum of the first 63 bytes */ - /*----------------------------------------- */ - cmpi 0, r7, 63 - bgt rd31 - beq rd30 - add r8, r8, r3 - bl rd31 - - /* Verify checksum at byte 63 */ - /*--------------------------- */ -rd30: andi. r8, r8, 0xff /* use only 8 bits */ - cmp 0, r8, r3 - beq rd31 - addi r4, 0, LED_SDRAM_CODE_8 - addis r5, 0, 0x1000 - ori r5, r5, 0x0001 - stb r4,0(r5) - eieio -rderr: bl rderr - -rd31: - - /* Increment byte counter and check whether all bytes have been read. */ - /*------------------------------------------------------------------- */ - addi r7, r7, 1 - cmpi 0, r7, 127 - bgt rd05 - bl rdlp -rd05: - mtlr r5 /* restore lr */ - blr - -wait_i2c_transfer_done: - mflr r6 -wt01: READ_I2C(IICSTS) - andi. r4, r3, IIC_STS_PT - cmpi 0, r4, IIC_STS_PT - beq wt01 - mtlr r6 /* restore lr */ - blr - -/*--------------------------------------------------------------------- */ -/* Function: find_mode */ -/* Description: Determines addressing mode to be used dependent on */ -/* number of rows (r10 = byte 3 from SPD), number of columns (r11 = */ -/* byte 4 from SPD) and number of banks (r13 = byte 17 from SPD). */ -/* mode is returned in r3. */ -/* (It would be nicer having a table, pnc). */ -/*--------------------------------------------------------------------- */ -find_mode: - - mflr r5 - - cmpi 0, r10, 11 - bne fm01 - cmpi 0, r11, 9 - bne fm01 - cmpi 0, r13, 2 - bne fm01 - addi r3, 0, 1 - bl fmfound - -fm01: cmpi 0, r10, 11 - bne fm02 - cmpi 0, r11, 10 - bne fm02 - cmpi 0, r13, 2 - bne fm02 - addi r3, 0, 1 - bl fmfound - -fm02: cmpi 0, r10, 12 - bne fm03 - cmpi 0, r11, 9 - bne fm03 - cmpi 0, r13, 4 - bne fm03 - addi r3, 0, 2 - bl fmfound - -fm03: cmpi 0, r10, 12 - bne fm04 - cmpi 0, r11, 10 - bne fm04 - cmpi 0, r13, 4 - bne fm04 - addi r3, 0, 2 - bl fmfound - -fm04: cmpi 0, r10, 13 - bne fm05 - cmpi 0, r11, 9 - bne fm05 - cmpi 0, r13, 4 - bne fm05 - addi r3, 0, 3 - bl fmfound - -fm05: cmpi 0, r10, 13 - bne fm06 - cmpi 0, r11, 10 - bne fm06 - cmpi 0, r13, 4 - bne fm06 - addi r3, 0, 3 - bl fmfound - -fm06: cmpi 0, r10, 13 - bne fm07 - cmpi 0, r11, 11 - bne fm07 - cmpi 0, r13, 4 - bne fm07 - addi r3, 0, 3 - bl fmfound - -fm07: cmpi 0, r10, 12 - bne fm08 - cmpi 0, r11, 8 - bne fm08 - cmpi 0, r13, 2 - bne fm08 - addi r3, 0, 4 - bl fmfound - -fm08: cmpi 0, r10, 12 - bne fm09 - cmpi 0, r11, 8 - bne fm09 - cmpi 0, r13, 4 - bne fm09 - addi r3, 0, 4 - bl fmfound - -fm09: cmpi 0, r10, 11 - bne fm10 - cmpi 0, r11, 8 - bne fm10 - cmpi 0, r13, 2 - bne fm10 - addi r3, 0, 5 - bl fmfound - -fm10: cmpi 0, r10, 11 - bne fm11 - cmpi 0, r11, 8 - bne fm11 - cmpi 0, r13, 4 - bne fm11 - addi r3, 0, 5 - bl fmfound - -fm11: cmpi 0, r10, 13 - bne fm12 - cmpi 0, r11, 8 - bne fm12 - cmpi 0, r13, 2 - bne fm12 - addi r3, 0, 6 - bl fmfound - -fm12: cmpi 0, r10, 13 - bne fm13 - cmpi 0, r11, 8 - bne fm13 - cmpi 0, r13, 4 - bne fm13 - addi r3, 0, 6 - bl fmfound - -fm13: cmpi 0, r10, 13 - bne fm14 - cmpi 0, r11, 9 - bne fm14 - cmpi 0, r13, 2 - bne fm14 - addi r3, 0, 7 - bl fmfound - -fm14: cmpi 0, r10, 13 - bne fm15 - cmpi 0, r11, 10 - bne fm15 - cmpi 0, r13, 2 - bne fm15 - addi r3, 0, 7 - bl fmfound - -fm15: - /* not found, error code to be issued on LEDs */ - addi r7, 0, LED_SDRAM_CODE_2 - addis r6, 0, 0x1000 - ori r6, r6, 0x0001 - stb r7,0(r6) - eieio -fmerr: bl fmerr - -fmfound:addi r6, 0, 1 - subf r3, r6, r3 - - mtlr r5 /* restore lr */ - blr - -/*--------------------------------------------------------------------- */ -/* Function: find_size_code */ -/* Description: Determines size code to be used in configuring SDRAM controller */ -/* dependent on density (r15 = byte 31 from SPD) */ -/*--------------------------------------------------------------------- */ -find_size_code: - - mflr r5 - - addi r3, r15, 0 /* density */ - addi r7, 0, 0 -fs01: andi. r6, r3, 0x01 - cmpi 0, r6, 1 - beq fs04 - - addi r7, r7, 1 - cmpi 0, r7, 7 - bge fs02 - addi r9, 0, 1 - srw r3, r3, r9 - bl fs01 - - /* not found, error code to be issued on LEDs */ -fs02: addi r4, 0, LED_SDRAM_CODE_3 - addis r8, 0, 0x1000 - ori r8, r8, 0x0001 - stb r4,0(r8) - eieio -fs03: bl fs03 - -fs04: addi r3, r7, 0 - cmpi 0, r3, 0 - beq fs05 - addi r6, 0, 1 - subf r3, r6, r3 -fs05: - mtlr r5 /* restore lr */ - blr - -/*--------------------------------------------------------------------- */ -/* Function: find_casl */ -/* Description: Determines CAS latency */ -/*--------------------------------------------------------------------- */ -find_casl: - - mflr r5 - - andi. r14, r14, 0x7f /* r14 holds supported CAS latencies */ - addi r3, 0, 0xff /* preset determined CASL */ - addi r4, 0, 6 /* Start at bit 6 of supported CAS latencies */ - addi r2, 0, 0 /* Start finding highest CAS latency */ - -fc01: srw r6, r14, r4 /* */ - andi. r6, r6, 0x01 /* */ - cmpi 0, r6, 1 /* Check bit for current latency */ - bne fc06 /* If not supported, go to next */ - - cmpi 0, r2, 2 /* Check if third-highest latency */ - bge fc04 /* If so, go calculate with another format */ - - cmpi 0, r2, 0 /* Check if highest latency */ - bgt fc02 /* */ - addi r7, r19, 0 /* SDRAM cycle time for highest CAS latenty */ - - bl fc03 -fc02: - addi r7, r20, 0 /* SDRAM cycle time for next-highest CAS latenty */ -fc03: - addi r8, r7, 0 - addi r9, 0, 4 - srw r7, r7, r9 - andi. r7, r7, 0x0f - mulli r7, r7, 100 - andi. r8, r8, 0x0f - mulli r8, r8, 10 - add r7, r7, r8 - cmp 0, r7, r30 - bgt fc05 - addi r3, r2, 0 - bl fc05 -fc04: - addi r7, r21, 0 /* SDRAM cycle time for third-highest CAS latenty */ - addi r8, r7, 0 - addi r9, 0, 2 - srw r7, r7, r9 - andi. r7, r7, 0x3f - mulli r7, r7, 100 - andi. r8, r8, 0x03 - mulli r8, r8, 25 - add r7, r7, r8 - - cmp 0, r7, r30 - bgt fc05 - addi r3, r2, 0 - -fc05: addi r2, r2, 1 /* next latency */ - cmpi 0, r2, 3 - bge fc07 -fc06: addi r6, 0, 1 - subf r4, r6, r4 - cmpi 0, r4, 0 - bne fc01 - -fc07: - - mtlr r5 /* restore lr */ - blr -#endif - - -/* Peripheral Bank 1 Access Parameters */ -/* 0 BME = 1 ; burstmode enabled */ -/* " 1:8" TWT=00110110 ;Transfer wait (details below) */ -/* 1:5 FWT=00110 ; first wait = 6 cycles */ -/* 6:8 BWT=110 ; burst wait = 6 cycles */ -/* 9:11 000 ; reserved */ -/* 12:13 CSN=00 ; chip select on timing = 0 */ -/* 14:15 OEN=01 ; output enable */ -/* 16:17 WBN=01 ; write byte enable on timing 1 cycle */ -/* 18:19 WBF=01 ; write byte enable off timing 1 cycle */ -/* 20:22 TH=010 ; transfer hold = 2 cycles */ -/* 23 RE=0 ; ready enable = disabled */ -/* 24 SOR=1 ; sample on ready = same PerClk */ -/* 25 BEM=0 ; byte enable mode = only for write cycles */ -/* 26 PEN=0 ; parity enable = disable */ -/* 27:31 00000 ;reserved */ -/* */ -/* 1 + 00110 + 110 + 000 + 00 + 01 + 01 + 01 + 010 + 0 + 1 + 0 + 0 + 00000 = 0x9b015480 */ -/* */ -/* */ -/* Code for BDI probe: */ -/* */ -/* WDCR 18 0x00000011 ;Select PB1AP */ -/* WDCR 19 0x1b015480 ;PB1AP: Flash */ -/* */ -/* Peripheral Bank 0 Access Parameters */ -/* 0:11 BAS=0x200 ; base address select = 0x200 * 0x100000 (1MB) = */ -/* 12:14 BS=100 ; bank size = 16MB (100) / 32MB (101) */ -/* 15:16 BU=11 ; bank usage = read/write */ -/* 17:18 BW=00 ; bus width = 8-bit */ -/* 19:31 ; reserved */ -/* */ -/* 0x200 + 100 + 11 + 00 + 0 0000 0000 0000 = 0x20098000 */ -/* WDCR 18 0x00000001 ;Select PB1CR */ -/* WDCR 19 0x20098000 ;PB1CR: 1MB at 0x00100000, r/w, 8bit */ - -/* For CPLD */ -/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */ -/* WDCR_EBC(pb5ap, 0x01010040) */ -/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */ -/* WDCR_EBC(pb5cr, 0X10018000) */ -/* Access parms */ -/* 100 3 8 0 0 0 */ -/* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */ -/* Address : 0x10000000 */ -/* Size: 2 MB */ -/* Usage: read/write */ -/* Width: 32 bit */ - -/* For Genie onboard fpga 32 bit interface */ -/* 0 1 0 1 0 0 0 0 */ -/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 0 + 0 + 00000 */ -/* 0x01010000 */ -/* Access parms */ -/* 102 1 c 0 0 0 */ -/* 0x102 + 000 + 11 + 10 + 0 0000 0000 0000 = 0x1021c000 */ -/* Address : 0x10200000 */ -/* Size: 2 MB */ -/* Usage: read/write */ -/* Width: 32 bit */ - -/* Walnut fpga pb7ap */ -/* 0 1 8 1 5 2 8 0 */ -/* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */ -/* Walnut fpga pb7cr */ -/* 0xF0318000 */ -/* */ diff --git a/board/exbitgen/u-boot.lds b/board/exbitgen/u-boot.lds deleted file mode 100644 index d5dea82..0000000 --- a/board/exbitgen/u-boot.lds +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/exbitgen/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - . = ALIGN(4); - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/fads/Makefile b/board/fads/Makefile deleted file mode 100644 index baa6c2e..0000000 --- a/board/fads/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o lamp.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/fads/config.mk b/board/fads/config.mk deleted file mode 100644 index 621b9a2..0000000 --- a/board/fads/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and -# MPC885ADS boards -# - -TEXT_BASE = 0xFE000000 -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/fads -HOST_CFLAGS += -I$(TOPDIR)/board/fads -HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/fads diff --git a/board/fads/fads.c b/board/fads/fads.c deleted file mode 100644 index 013b3cb..0000000 --- a/board/fads/fads.c +++ /dev/null @@ -1,953 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define _NOT_USED_ 0xFFFFFFFF - -/* ========================================================================= */ - -#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ - -#if defined(CONFIG_DRAM_50MHZ) -/* 50MHz tables */ -static const uint dram_60ns[] = -{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04, - 0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_, - 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c, - 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44, - 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00, - 0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, - 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint dram_70ns[] = -{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, - 0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, - 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00, - 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04, - 0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, - 0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_60ns[] = -{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04, - 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_, - 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c, - 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c, - 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, - 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_70ns[] = -{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04, - 0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c, - 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00, - 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00, - 0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, - 0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -#elif defined(CONFIG_DRAM_25MHZ) - -/* 25MHz tables */ - -static const uint dram_60ns[] = -{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint dram_70ns[] = -{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_60ns[] = -{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c, - 0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48, - 0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_70ns[] = -{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00, - 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00, - 0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00, - 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00, - 0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; -#else -#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ -#endif - -/* ------------------------------------------------------------------------- */ -static int _draminit (uint base, uint noMbytes, uint edo, uint delay) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* init upm */ - - switch (delay) { - case 70: - if (edo) { - upmconfig (UPMA, (uint *) edo_70ns, - sizeof (edo_70ns) / sizeof (uint)); - } else { - upmconfig (UPMA, (uint *) dram_70ns, - sizeof (dram_70ns) / sizeof (uint)); - } - - break; - - case 60: - if (edo) { - upmconfig (UPMA, (uint *) edo_60ns, - sizeof (edo_60ns) / sizeof (uint)); - } else { - upmconfig (UPMA, (uint *) dram_60ns, - sizeof (dram_60ns) / sizeof (uint)); - } - - break; - - default: - return -1; - } - - memctl->memc_mptpr = 0x0400; /* divide by 16 */ - - switch (noMbytes) { - case 4: /* 4 Mbyte uses only CS2 */ -#ifdef CONFIG_ADS - memctl->memc_mamr = 0xc0a21114; -#else - memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ -#endif - memctl->memc_or2 = 0xffc00800; /* 4M */ - break; - - case 8: /* 8 Mbyte uses both CS3 and CS2 */ - memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ - memctl->memc_or3 = 0xffc00800; /* 4M */ - memctl->memc_br3 = 0x00400081 + base; - memctl->memc_or2 = 0xffc00800; /* 4M */ - break; - - case 16: /* 16 Mbyte uses only CS2 */ -#ifdef CONFIG_ADS /* XXX: why PTA=0x60 only in 16M case? - NTL */ - memctl->memc_mamr = 0x60b21114; /* PTA 0x60 AMA 011 */ -#else - memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ -#endif - memctl->memc_or2 = 0xff000800; /* 16M */ - break; - - case 32: /* 32 Mbyte uses both CS3 and CS2 */ - memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ - memctl->memc_or3 = 0xff000800; /* 16M */ - memctl->memc_br3 = 0x01000081 + base; - memctl->memc_or2 = 0xff000800; /* 16M */ - break; - - default: - return -1; - } - - memctl->memc_br2 = 0x81 + base; /* use upma */ - - *((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */ - - /* if no dimm is inserted, noMbytes is still detected as 8m, so - * sanity check top and bottom of memory */ - - /* check bytes / 2 because get_ram_size tests at base+bytes, which - * is not mapped */ - if (noMbytes == 8) - if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) { - *((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */ - return -1; - } - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static void _dramdisable(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_br2 = 0x00000000; - memctl->memc_br3 = 0x00000000; - - /* maybe we should turn off upma here or something */ -} -#endif /* !CONFIG_MPC885ADS */ - -/* ========================================================================= */ - -#ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */ - -#if defined(CONFIG_SDRAM_100MHZ) - -/* ------------------------------------------------------------------------- */ -/* sdram table by Dan Malek */ - -/* This has the stretched early timing so the 50 MHz - * processor can make the 100 MHz timing. This will - * work at all processor speeds. - */ - -#ifdef SDRAM_ALT_INIT_SEQENCE -# define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */ -#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0 -# define SDRAM_MCRVALUE0 0x80808111 /* run upmb cs4 loop 1 addr 0x11 MRS */ -# define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0 /* ??? why not 0x80808130? */ -#else -# define SDRAM_MxMR_PTx 195 -# define UPM_MRS_ADDR 0x11 -# define UPM_REFRESH_ADDR 0x30 /* or 0x11 if we want to be like above? */ -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -static const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04, - 0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_, - - /* burst read. (offset 8 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04, - 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00, - 0x1ff77c45, - - /* precharge + MRS. (offset 11 in upm RAM) */ - 0xeffbbc04, 0x1ff77c34, 0xefeabc34, - 0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write. (offset 18 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04, - 0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst write. (offset 20 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, - 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* refresh. (offset 30 in upm RAM) */ - 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* exception. (offset 3c in upm RAM) */ - 0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ }; - -#elif defined(CONFIG_SDRAM_50MHZ) - -/* ------------------------------------------------------------------------- */ -/* sdram table stolen from the fads manual */ -/* for chip MB811171622A-100 */ - -/* this table is for 32-50MHz operation */ -#ifdef SDRAM_ALT_INIT_SEQENCE -# define SDRAM_MBMRVALUE0 0x80802114 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */ -# define SDRAM_MBMRVALUE1 0x80802118 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */ -# define SDRAM_MCRVALUE0 0x80808105 /* run upmb cs4 loop 1 addr 0x5 MRS */ -# define SDRAM_MCRVALUE1 0x80808130 /* run upmb cs4 loop 1 addr 0x30 REFRESH */ -# define SDRAM_MPTRVALUE 0x400 -#define SDRAM_MARVALUE 0x88 -#else -# define SDRAM_MxMR_PTx 128 -# define UPM_MRS_ADDR 0x5 -# define UPM_REFRESH_ADDR 0x30 -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -static const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* precharge + MRS. (offset 5 in upm RAM) */ - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -/* ------------------------------------------------------------------------- */ -#else -#error SDRAM not correctly configured -#endif -/* ------------------------------------------------------------------------- */ - -/* - * Memory Periodic Timer Prescaler - */ - -#define SDRAM_OR4VALUE 0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */ -#define SDRAM_BR4VALUE 0x000000c1 /* UPMB,base addr or'ed on later */ - -/* ------------------------------------------------------------------------- */ -#ifdef SDRAM_ALT_INIT_SEQENCE -/* ------------------------------------------------------------------------- */ - -static int _initsdram(uint base, uint noMbytes) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = SDRAM_MPTPRVALUE; - - /* Configure the refresh (mostly). This needs to be - * based upon processor clock speed and optimized to provide - * the highest level of performance. For multiple banks, - * this time has to be divided by the number of banks. - * Although it is not clear anywhere, it appears the - * refresh steps through the chip selects for this UPM - * on each refresh cycle. - * We have to be careful changing - * UPM registers after we ask it to run these commands. - */ - - memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */ - memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */ - - udelay(200); - - /* Now run the precharge/nop/mrs commands. - */ - - memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50Mhz) */ - /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100Mhz) */ - udelay(200); - - /* Run 8 refresh cycles */ - - memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 Mhz)*/ - /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */ - - udelay(200); - - memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 Mhz) or TLF 8 (50MHz) */ - memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 Mhz) */ - /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */ - - udelay(200); - - memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */ - - memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1); - memctl->memc_br4 = SDRAM_BR4VALUE | base; - - return 0; -} - -/* ------------------------------------------------------------------------- */ -#else /* !SDRAM_ALT_INIT_SEQUENCE */ -/* ------------------------------------------------------------------------- */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -# define MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -# define MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -# define MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -# define MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MxMR settings for SDRAM - */ - -/* 8 column SDRAM */ -# define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTBE | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -/* 9 column SDRAM */ -# define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTAE | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) - -static int _initsdram(uint base, uint noMbytes) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = MPTPR_2BK_4K; - memctl->memc_mbmr = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */ - - /* map CS 4 */ - memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1); - memctl->memc_br4 = SDRAM_BR4VALUE | base; - - /* Perform SDRAM initilization */ -# ifdef UPM_NOP_ADDR /* not currently in UPM table */ - /* step 1: nop */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(0) | UPM_NOP_ADDR; -# endif - - /* step 2: delay */ - udelay(200); - -# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */ - /* step 3: precharge */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(4) | UPM_PRECHARGE_ADDR; -# endif - - /* step 4: refresh */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(2) | UPM_REFRESH_ADDR; - - /* - * note: for some reason, the UPM values we are using include - * precharge with MRS - */ - - /* step 5: mrs */ - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(1) | UPM_MRS_ADDR; - -# ifdef UPM_NOP_ADDR - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(0) | UPM_NOP_ADDR; -# endif - /* - * Enable refresh - */ - - memctl->memc_mbmr |= MBMR_PTBE; - return 0; -} -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -/* ------------------------------------------------------------------------- */ - -static void _sdramdisable(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_br4 = 0x00000000; - - /* maybe we should turn off upmb here or something */ -} - -/* ------------------------------------------------------------------------- */ - -static int initsdram(uint base, uint *noMbytes) -{ - uint m = CFG_SDRAM_SIZE>>20; - - /* _initsdram needs access to sdram */ - *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */ - - if(!_initsdram(base, m)) - { - *noMbytes += m; - return 0; - } - else - { - *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */ - - _sdramdisable(); - - return -1; - } -} - -#endif /* CONFIG_FADS */ - -/* ========================================================================= */ - -long int initdram (int board_type) -{ - uint sdramsz = 0; /* size of sdram in Mbytes */ - uint base = 0; /* base of dram in bytes */ - uint m = 0; /* size of dram in Mbytes */ -#ifndef CONFIG_MPC885ADS - uint k, s; -#endif - -#ifdef CONFIG_FADS - if (!initsdram (0x00000000, &sdramsz)) { - base = sdramsz << 20; - printf ("(%u MB SDRAM) ", sdramsz); - } -#endif -#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ - k = (*((uint *) BCSR2) >> 23) & 0x0f; - - switch (k & 0x3) { - /* "MCM36100 / MT8D132X" */ - case 0x00: - m = 4; - break; - - /* "MCM36800 / MT16D832X" */ - case 0x01: - m = 32; - break; - /* "MCM36400 / MT8D432X" */ - case 0x02: - m = 16; - break; - /* "MCM36200 / MT16D832X ?" */ - case 0x03: - m = 8; - break; - - } - - switch (k >> 2) { - case 0x02: - k = 70; - break; - - case 0x03: - k = 60; - break; - - default: - printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k); - k = 70; - } - -#ifdef CONFIG_FADS - /* the FADS is missing this bit, all rams treated as non-edo */ - s = 0; -#else - s = (*((uint *) BCSR2) >> 27) & 0x01; -#endif - - if (!_draminit (base, m, s, k)) { - printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : ""); - } else { - _dramdisable (); - m = 0; - } -#endif /* !CONFIG_MPC885ADS */ - m += sdramsz; /* add sdram size to total */ - - return (m << 20); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ========================================================================= */ - -/* - * Check Board Identity: - */ - -#if defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD) -static void checkdboard(void) -{ - /* get db type from BCSR 3 */ - uint k = (*((uint *)BCSR3) >> 24) & 0x3f; - - puts (" with db "); - - switch(k) { - case 0x03 : - puts ("MPC823"); - break; - case 0x20 : - puts ("MPC801"); - break; - case 0x21 : - puts ("MPC850"); - break; - case 0x22 : - puts ("MPC821, MPC860 / MPC860SAR / MPC860T"); - break; - case 0x23 : - puts ("MPC860SAR"); - break; - case 0x24 : - case 0x2A : - puts ("MPC860T"); - break; - case 0x3F : - puts ("MPC850SAR"); - break; - default : printf("0x%x", k); - } -} -#endif /* defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD) */ - -int checkboard (void) -{ - /* get revision from BCSR 3 */ - uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3) - | (((*((uint *) BCSR3) >> 19) & 1) << 2) - | (((*((uint *) BCSR3) >> 16) & 3)); - - puts ("Board: "); - -#if defined(CONFIG_MPC86xADS) - puts ("MPC86xADS"); -#elif defined(CONFIG_MPC885ADS) - puts ("MPC885ADS"); - r = 0; /* I've got NR (No Revision) board */ -#elif defined(CONFIG_FADS) - puts ("FADS"); - checkdboard (); -#else - puts ("ADS"); -#endif - puts (" rev "); - - switch (r) { -#if defined(CONFIG_ADS) - case 0x00: - puts ("ENG - this board sucks, check the errata, not supported\n"); - return -1; - case 0x01: - puts ("PILOT - warning, read errata \n"); - break; - case 0x02: - puts ("A - warning, read errata \n"); - break; - case 0x03: - puts ("B \n"); - break; -#elif defined(CONFIG_MPC885ADS) - case 0x00: - puts ("NR\n"); - break; -#else /* FADS and newer */ - case 0x00: - puts ("ENG\n"); - break; - case 0x01: - puts ("PILOT\n"); - break; -#endif /* CONFIG_ADS */ - default: - printf ("unknown (0x%x)\n", r); - return -1; - } - - return 0; -} - -/* ========================================================================= */ - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) - -#ifdef CFG_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR; -#endif - -int pcmcia_init(void) -{ - volatile pcmconf8xx_t *pcmp; - uint v, slota = 0, slotb = 0; - - /* - ** Enable the PCMCIA for a Flash card. - */ - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - -#if 0 - pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR; - pcmp->pcmc_por0 = 0xc00ff05d; -#endif - - /* Set all slots to zero by default. */ - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; -#ifdef CONFIG_PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0x40; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0x40; -#endif - - /* enable PCMCIA buffers */ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - - /* Check if any PCMCIA card is plugged in. */ - -#ifdef CONFIG_PCMCIA_SLOT_A - slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ; -#endif - - if (!(slota || slotb)) { - printf("No card present\n"); - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; - return -1; - } - else - printf("Card present ("); - - v = 0; - - /* both the ADS and the FADS have a 5V keyed pcmcia connector (?) - ** - ** Paolo - Yes, but i have to insert some 3.3V card in that slot on - ** my FADS... :-) - */ - -#if defined(CONFIG_MPC86x) - switch ((pcmp->pcmc_pipr >> 30) & 3) -#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850) - switch ((pcmp->pcmc_pipr >> 14) & 3) -#endif - { - case 0x00 : - printf("5V"); - v = 5; - break; - case 0x01 : - printf("5V and 3V"); -#ifdef CONFIG_FADS - v = 3; /* User lower voltage if supported! */ -#else - v = 5; -#endif - break; - case 0x03 : - printf("5V, 3V and x.xV"); -#ifdef CONFIG_FADS - v = 3; /* User lower voltage if supported! */ -#else - v = 5; -#endif - break; - } - - switch (v) { -#ifdef CONFIG_FADS - case 3: - printf("; using 3V"); - /* - ** Enable 3 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCC1; - *((uint *)BCSR1) |= BCSR1_PCCVCC0; - break; -#endif - case 5: - printf("; using 5V"); -#ifdef CONFIG_ADS - /* - ** Enable 5 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCCON; -#endif -#ifdef CONFIG_FADS - /* - ** Enable 5 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCC0; - *((uint *)BCSR1) |= BCSR1_PCCVCC1; -#endif - break; - - default: - *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */ - - printf("; unknown voltage"); - return -1; - } - printf(")\n"); - /* disable pcmcia reset after a while */ - - udelay(20); - -#ifdef CONFIG_PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0; -#endif - - /* If you using a real hd you should give a short - * spin-up time. */ -#ifdef CONFIG_DISK_SPINUP_TIME - udelay(CONFIG_DISK_SPINUP_TIME); -#endif - - return 0; -} - -#endif /* CFG_CMD_PCMCIA */ - -/* ========================================================================= */ - -#ifdef CFG_PC_IDE_RESET - -void ide_set_reset(int on) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - - /* - * Configure PC for IDE Reset Pin - */ - if (on) { /* assert RESET */ - immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); - } else { /* release RESET */ - immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; - } - - /* program port pin as GPIO output */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; -} - -#endif /* CFG_PC_IDE_RESET */ diff --git a/board/fads/fads.h b/board/fads/fads.h deleted file mode 100644 index 1127c7f..0000000 --- a/board/fads/fads.h +++ /dev/null @@ -1,514 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum, - * and Dan Malek - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * This header file contains values common to all FADS family boards. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * Flash Memory Map as used by U-Boot: - * - * Start Address Length - * +-----------------------+ 0xFE00_0000 Start of Flash ----------------- - * | | 0xFE00_0100 Reset Vector - * + + 0xFE0?_???? - * | U-Boot code | - * | | - * +-----------------------+ 0xFE04_0000 (sector border) - * | | - * | | - * | U-Boot environment | - * | | ^ - * | | | U-Boot - * +=======================+ 0xFE08_0000 (sector border) ----------------- - * | Available | | Applications - * | ... | v - * - *****************************************************************************/ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ - -/* - * New MPC86xADS and Duet provide two Ethernet connectivity options: - * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on - * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have - * got FEC so FEC is the default. - */ -#ifndef CONFIG_ADS -#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */ -#define CONFIG_FEC_ENET /* Use FEC ethernet */ -#else /* Old ADS has not got FEC option */ -#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */ -#undef CONFIG_FEC_ENET /* No FEC ethernet */ -#endif /* !CONFIG_ADS */ - -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#ifdef CONFIG_FEC_ENET -#define CFG_DISCOVER_PHY -#endif - -#ifndef CONFIG_COMMANDS -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_MII \ - | CFG_CMD_PCMCIA \ - | CFG_CMD_PING \ - ) -#endif /* !CONFIG_COMMANDS */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ -#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ -#elif defined(CONFIG_FADS) /* Old/new FADS */ -#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ -#else /* Old ADS */ -#define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */ -#endif - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#if (CFG_SDRAM_SIZE) -#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ -#else -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#endif /* CFG_SDRAM_SIZE */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ - -#ifdef CONFIG_BZIP2 -#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ -#else -#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * Flash organization - */ -#define CFG_FLASH_BASE CFG_MONITOR_BASE -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ - -#define CFG_DIRECT_FLASH_TFTP - -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3" -#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)" -*/ - -#define CFG_JFFS2_SORT_FRAGMENTS -#endif /* CFG_CMD_JFFS2 */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * I2C configuration - */ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ -#define CFG_I2C_SLAVE 0x7F -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control - */ -#ifndef CFG_PLPRCR -#define CFG_PLPRCR PLPRCR_TEXPS -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/OR0 (Flash) - * BR1/OR1 (BCSR) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_ADDR ((uint) 0xFF080000) - -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* values according to the manual */ - -#define PCMCIA_MEM_ADDR ((uint)0xFF020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 0x00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* - * (F)ADS bitvalues by Helmut Buchsbaum - * - * See User's Manual for a proper - * description of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR1_PCCVCCON BCSR1_PCCVCC0 - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_FLASH_PD_SHIFT 28 -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT 23 -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#define BCSR4_FETH_EN ((uint)0x08000000) -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#define BCSR4_FETHFDE ((uint)0x02000000) -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#define BCSR4_FETHRST ((uint)0x00200000) - -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_MODEM_EN ((uint)0x00100000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC850 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC850 */ - -/* BSCR5 exists on MPC86xADS and Duet ADS only */ - -#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) - -#define BCSR5 (CFG_PHYDEV_ADDR + 0x300) - -#define BCSR5_MII2_EN 0x40 -#define BCSR5_MII2_RST 0x20 -#define BCSR5_T1_RST 0x10 -#define BCSR5_ATM155_RST 0x08 -#define BCSR5_ATM25_RST 0x04 -#define BCSR5_MII1_EN 0x02 -#define BCSR5_MII1_RST 0x01 - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_fads) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_ISO_PARTITION 1 - -#undef CONFIG_ATAPI -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR -#define CFG_ATA_IDE0_OFFSET 0x0000 - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0000 - -#define CONFIG_DISK_SPINUP_TIME 1000000 -#undef CONFIG_DISK_SPINUP_TIME /* usin´ Compact Flash */ diff --git a/board/fads/flash.c b/board/fads/flash.c deleted file mode 100644 index f0fb621..0000000 --- a/board/fads/flash.c +++ /dev/null @@ -1,560 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -#define QUAD_ID(id) ((((ulong)(id) & 0xFF) << 24) | \ - (((ulong)(id) & 0xFF) << 16) | \ - (((ulong)(id) & 0xFF) << 8) | \ - (((ulong)(id) & 0xFF) << 0) \ - ) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - vu_long *bcsr = (vu_long *)BCSR_ADDR; - unsigned long pd_size, total_size, bsize, or_am; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = 0; - flash_info[i].sector_count = 0; - flash_info[i].start[0] = 0xFFFFFFFF; /* For TFTP */ - } - - switch ((bcsr[2] & BCSR2_FLASH_PD_MASK) >> BCSR2_FLASH_PD_SHIFT) { - case 2: - case 4: - case 6: - pd_size = 0x800000; - or_am = 0xFF800000; - break; - - case 5: - case 7: - pd_size = 0x400000; - or_am = 0xFFC00000; - break; - - case 8: - pd_size = 0x200000; - or_am = 0xFFE00000; - break; - - default: - pd_size = 0; - or_am = 0xFFE00000; - printf("## Unsupported flash detected by BCSR: 0x%08X\n", bcsr[2]); - } - - total_size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS && total_size < pd_size; ++i) { - bsize = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size), - &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, bsize, bsize >> 20); - } - - total_size += bsize; - } - - if (total_size != pd_size) { - printf("## Detected flash size %lu conflicts with PD data %lu\n", - total_size, pd_size); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = or_am | CFG_OR_TIMING_FLASH; - - for (i = 0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) { -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - if (CFG_MONITOR_BASE >= flash_info[i].start[0]) - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[i]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - if (CFG_ENV_ADDR >= flash_info[i].start[0]) - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[i]); -#endif - } - - return total_size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_BM: - printf ("BRIGHT MICRO "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM080: - printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - * The following code can not run from flash! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - - switch (addr[0]) { - case QUAD_ID(AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - - case QUAD_ID(FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - switch (addr[1]) { /* device ID */ - case QUAD_ID(AMD_ID_F040B): - case QUAD_ID(AMD_ID_LV040B): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00200000; - break; /* => 2 MB */ - - case QUAD_ID(AMD_ID_F080B): - info->flash_id += FLASH_AM080; - info->sector_count = 16; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif /* 0 */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - -#if 0 - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = (ulong)addr + (i * 0x00040000); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *) (info->start[i]); - info->protect[i] = addr[2] & 1; - } - - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *) info->start[0]; - *addr = 0xF0F0F0F0; /* reset bank */ - } - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - vu_long *addr = (vu_long *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return ERR_INVAL; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); - return ERR_UNKNOWN_FLASH_TYPE; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *) (info->start[l_sect]); - while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) - { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *) info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & data) != data) { - return ERR_NOT_ERASED; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080)) - { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return ERR_TIMOUT; - } - } - return (0); -} diff --git a/board/fads/lamp.c b/board/fads/lamp.c deleted file mode 100644 index 4e58291..0000000 --- a/board/fads/lamp.c +++ /dev/null @@ -1,47 +0,0 @@ -#include - -#ifndef CONFIG_ADS /* Old ADS has not got any user-controllable LED */ - -#include - -void -signal_delay(unsigned int n) -{ - while (n--); -} - -void -signal_on(void) -{ - *((volatile uint *)BCSR4) &= ~(1<<(31-3)); /* led on */ -} - -void -signal_off(void) -{ - *((volatile uint *)BCSR4) |= (1<<(31-3)); /* led off */ -} - -void -slow_blink(unsigned int n) -{ - while (n--) { - signal_on(); - signal_delay(0x00400000); - signal_off(); - signal_delay(0x00400000); - } -} - -void -fast_blink(unsigned int n) -{ - while (n--) { - signal_on(); - signal_delay(0x00100000); - signal_off(); - signal_delay(0x00100000); - } -} - -#endif /* !CONFIG_ADS */ diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds deleted file mode 100644 index 21a2d9e..0000000 --- a/board/fads/u-boot.lds +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - - /*. = DEFINED(env_offset) ? env_offset : .;*/ - common/environment.o (.ppcenv) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/fads/u-boot.lds.debug b/board/fads/u-boot.lds.debug deleted file mode 100644 index 650572d..0000000 --- a/board/fads/u-boot.lds.debug +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/flagadm/Makefile b/board/flagadm/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/flagadm/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/flagadm/config.mk b/board/flagadm/config.mk deleted file mode 100644 index 9c72c79..0000000 --- a/board/flagadm/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TQM8xxL boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c deleted file mode 100644 index 9c55367..0000000 --- a/board/flagadm/flagadm.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define _NOT_USED_ 0xFFFFFFFF - -/*Orginal table, GPL4 disabled*/ -const uint sdram_table[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00, - 0x1ff74c47, - /* Precharge */ - 0x1FF74C05, - _NOT_USED_, - _NOT_USED_, - /* burst read (offset 0x08 in upm ram) */ - 0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00, - 0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* single write (offset 0x18 in upm ram) */ - 0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47, - /* Load moderegister */ - 0x1FF74C34, /*Precharge*/ - 0xEFEA8C34, /*NOP*/ - 0x1FB54C35, /*Load moderegister*/ - _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - 0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00, - 0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - 0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04, - 0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - 0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* GPL5 driven every cycle */ -/* the display and the DSP */ -const uint dsp_disp_table[] = -{ - /* single read (offset 0x00 in upm ram) */ - 0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004, - 0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05, - /* burst read (offset 0x08 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* single write (offset 0x18 in upm ram) */ - 0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004, - 0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05, - /* burst write (offset 0x20 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* refresh (offset 0x30 in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* exception (offset 0x3C in upm ram) */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -int checkboard (void) -{ - puts ("Board: FlagaDM V3.0\n"); - return 0; -} - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0; - - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; - - udelay(100); - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = MPTPR_PTP_DIV16; - memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_1X; - - /*Do the initialization of the SDRAM*/ - /*Start with the precharge cycle*/ - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(1) | MCR_MAD(0x5)); - - /*Then we need two refresh cycles*/ - memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_2X; - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(2) | MCR_MAD(0x30)); - - /*Mode register programming*/ - memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/ - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ - MCR_MLCF(1) | MCR_MAD(0x1C)); - - /* That should do it, just enable the periodic refresh in burst of 4*/ - memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X; - memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS); - - size_b0 = 16*1024*1024; - - /* - * No bank 1 or 3 - * invalidate bank - */ - memctl->memc_br1 = 0; - memctl->memc_br3 = 0; - - upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint)); - - memctl->memc_mbmr = MBMR_GPL_B4DIS; - - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; - - return (size_b0); -} diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c deleted file mode 100644 index fd0082c..0000000 --- a/board/flagadm/flash.c +++ /dev/null @@ -1,697 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -ulong flash_recognize (vu_long *base); -int write_word (flash_info_t *info, ulong dest, ulong data); -void flash_get_geometry (vu_long *base, flash_info_t *info); -void flash_unprotect(flash_info_t *info); -int _flash_real_protect(flash_info_t *info, long idx, int on); - - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - int i; - int rec; - - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br0 & ~(BR_BA_MSK)); - - rec = flash_recognize((vu_long*)CFG_FLASH_BASE); - - if (rec == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - flash_info[0].size, flash_info[0].size<<20); - } - -#if CFG_FLASH_PROTECTION - /*Unprotect all the flash memory*/ - flash_unprotect(&flash_info[0]); -#endif - - *((vu_short*)CFG_FLASH_BASE) = 0xffff; - - return (flash_info[0].size); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_OFFSET, - CFG_ENV_OFFSET+CFG_ENV_SIZE-1, - &flash_info[0]); -#endif - return (flash_info[0].size); -} - - -int flash_get_protect_status(flash_info_t * info, long idx) -{ - vu_short * base; - ushort res; - -#ifdef DEBUG - printf("\n Attempting to set protection info with %d sectors\n", info->sector_count); -#endif - - - base = (vu_short*)info->start[idx]; - - *(base) = 0xffff; - - *(base + 0x55) = 0x0098; - res = base[0x2]; - - *(base) = 0xffff; - - if(res != 0) - res = 1; - else - res = 0; - - return res; -} - -void flash_get_geometry (vu_long *base, flash_info_t *info) -{ - int i,j; - ulong ner = 0; - vu_short * sb = (vu_short*)base; - ulong offset = (ulong)base; - - /* Read Device geometry */ - - *sb = 0xffff; - - *sb = 0x0090; - - info->flash_id = ((ulong)base[0x0]); -#ifdef DEBUG - printf("Id is %x\n", (uint)(ulong)info->flash_id); -#endif - - *sb = 0xffff; - - *(sb+0x55) = 0x0098; - - info->size = 1 << (sb[0x27]); /* Read flash size */ - -#ifdef DEBUG - printf("Size is %x\n", (uint)(ulong)info->size); -#endif - - *sb = 0xffff; - - *(sb + 0x55) = 0x0098; - ner = sb[0x2c] ; /*Number of erase regions*/ - -#ifdef DEBUG - printf("Number of erase regions %x\n", (uint)ner); -#endif - - info->sector_count = 0; - - for(i = 0; i < ner; i++) - { - uint s; - uint count; - uint t1,t2,t3,t4; - - *sb = 0xffff; - - *(sb + 0x55) = 0x0098; - - t1 = sb[0x2d + i*4]; - t2 = sb[0x2e + i*4]; - t3 = sb[0x2f + i*4]; - t4 = sb[0x30 + i*4]; - - count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1; /*sector count*/ - s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;; /*Sector size*/ - -#ifdef DEBUG - printf("count and size %x, %x\n", count, s); - printf("sector count for erase region %d is %d\n", i, count); -#endif - for(j = 0; j < count; j++) - { -#ifdef DEBUG - printf("%x, ", (uint)offset); -#endif - info->start[ info->sector_count + j] = offset; - offset += s; - } - info->sector_count += count; - } - - if ((offset - (ulong)base) != info->size) - printf("WARNING reported size %x does not match to calculted size %x.\n" - , (uint)info->size, (uint)(offset - (ulong)base) ); - - /* Next check if there are any sectors protected.*/ - - for(i = 0; i < info->sector_count; i++) - info->protect[i] = flash_get_protect_status(info, i); - - *sb = 0xffff; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return ; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case INTEL_MANUFACT & FLASH_VENDMASK: - printf ("Intel "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case INTEL_ID_28F320C3B & FLASH_TYPEMASK: - printf ("28F320RC3(4 MB)\n"); - break; - case INTEL_ID_28F320J3A: - printf("28F320J3A (4 MB)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 4) == 0) - printf ("\n "); - printf (" %02d %08lX%s", - i, info->start[i], - info->protect[i]!=0 ? " (RO)" : " " - ); - } - printf ("\n"); - return ; -} - -ulong flash_recognize (vu_long *base) -{ - ulong id; - ulong res = FLASH_UNKNOWN; - vu_short * sb = (vu_short*)base; - - *sb = 0xffff; - - *sb = 0x0090; - id = base[0]; - - switch (id & 0x00FF0000) - { - case (MT_MANUFACT & 0x00FF0000): /* MT or => Intel */ - case (INTEL_ALT_MANU & 0x00FF0000): - res = FLASH_MAN_INTEL; - break; - default: - res = FLASH_UNKNOWN; - } - - *sb = 0xffff; - - return res; -} - -/*-----------------------------------------------------------------------*/ -#define INTEL_FLASH_STATUS_BLS 0x02 -#define INTEL_FLASH_STATUS_PSS 0x04 -#define INTEL_FLASH_STATUS_VPPS 0x08 -#define INTEL_FLASH_STATUS_PS 0x10 -#define INTEL_FLASH_STATUS_ES 0x20 -#define INTEL_FLASH_STATUS_ESS 0x40 -#define INTEL_FLASH_STATUS_WSMS 0x80 - -int flash_decode_status_bits(char status) -{ - int err = 0; - - if(!(status & INTEL_FLASH_STATUS_WSMS)) { - printf("Busy\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_ESS) { - printf("Erase suspended\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_ES) { - printf("Error in block erase\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_PS) { - printf("Error in programming\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_VPPS) { - printf("Vpp low, operation aborted\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_PSS) { - printf("Program is suspended\n"); - err = -1; - } - - if(status & INTEL_FLASH_STATUS_BLS) { - printf("Attempting to program/erase a locked sector\n"); - err = -1; - } - - if((status & INTEL_FLASH_STATUS_PS) && - (status & INTEL_FLASH_STATUS_ES) && - (status & INTEL_FLASH_STATUS_ESS)) { - printf("A command sequence error\n"); - return -1; - } - - return err; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr; - int flag, prot, sect; - ulong start, now; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - char tmp; - - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short *)(info->start[sect]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Single Block Erase Command */ - *addr = 0x0020; - /* Confirm */ - *addr = 0x00D0; - /* Resume Command, as per errata update */ - *addr = 0x00D0; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - *addr = 0x70; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read the status */ - while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - start) > 1000) { /* every second */ - putc ('.'); - } - udelay(100000); /* 100 ms */ - *addr = 0x0070; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read status */ - start = get_timer(0); - } - if( tmp & INTEL_FLASH_STATUS_ES ) - flash_decode_status_bits(tmp); - - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; /* Reset to read mode */ - } - } - - - printf (" done\n"); - return rcode; -} - -void flash_unprotect (flash_info_t *info) -{ - /*We can only unprotect the whole flash at once*/ - /*Therefore we must prevent the _flash_real_protect()*/ - /*from re-protecting sectors, that ware protected before */ - /*we called flash_real_protect();*/ - - int i; - - for(i = 0; i < info->sector_count; i++) - info->protect[i] = 0; - -#ifdef CFG_FLASH_PROTECTION - _flash_real_protect(info, 0, 0); -#endif -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_word (flash_info_t *info, ulong dest, ulong da) -{ - vu_short *addr = (vu_short *)dest; - ulong start; - char csr; - int flag; - ushort * d = (ushort*)&da; - int i; - - /* Check if Flash is (sufficiently) erased */ - if (((*addr & d[0]) != d[0]) || ((*(addr+1) & d[1]) != d[1])) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for(i = 0; i < 2; i++) - { - /* Write Command */ - *addr = 0x0010; - - /* Write Data */ - *addr = d[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - *addr = 0x0070; /*Read statusregister command */ - while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - *addr = 0x0070; /*Read statusregister command */ - } - if (csr & INTEL_FLASH_STATUS_PSS) { - printf ("CSR indicates write error (%0x) at %08lx\n", - csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x0050; - /* Reset to read array mode */ - *addr = 0xffff; - addr++; - } - - return (flag); -} - -int flash_real_protect(flash_info_t *info, long offset, int prot) -{ - int i, idx; - - for(idx = 0; idx < info->sector_count; idx++) - if(info->start[idx] == offset) - break; - - if(idx==info->sector_count) - return -1; - - if(prot == 0) { - /* Unprotect one sector, which means unprotect all flash - * and reprotect the other protected sectors. - */ - _flash_real_protect(info, 0, 0); /* Unprotects the whole flash*/ - info->protect[idx] = 0; - - for(i = 0; i < info->sector_count; i++) - if(info->protect[i]) - _flash_real_protect(info, i, 1); - } - else { - /* We can protect individual sectors */ - _flash_real_protect(info, idx, 1); - } - - for( i = 0; i < info->sector_count; i++) - info->protect[i] = flash_get_protect_status(info, i); - - return 0; -} - -int _flash_real_protect(flash_info_t *info, long idx, int prot) -{ - vu_short *addr; - int flag; - ushort cmd; - ushort tmp; - ulong now, start; - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) { - printf ("Can't change protection for unknown flash type %08lx - aborted\n", - info->flash_id); - return -1; - } - - if(prot == 0) { - /*Unlock the sector*/ - cmd = 0x00D0; - } - else { - /*Lock the sector*/ - cmd = 0x0001; - } - - addr = (vu_short *)(info->start[idx]); - - /* If chip is busy, wait for it */ - start = get_timer(0); - *addr = 0x0070; /*Read status register command*/ - tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/ - while(!(tmp & INTEL_FLASH_STATUS_WSMS)) { - /*Write State Machine Busy*/ - /*Wait untill done or timeout.*/ - if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; /* Reset the chip */ - printf ("TTimeout\n"); - return 1; - } - *addr = 0x0070; - tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/ - start = get_timer(0); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Unlock block*/ - *addr = 0x0060; - - *addr = cmd; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - *addr = 0x0070; /*Read status register command*/ - tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */ - while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { - /* Write State Machine Busy */ - if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { - *addr = 0x0050; /* Reset the status register */ - *addr = 0xffff; - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - start) > 1000) { /* every second */ - putc ('.'); - } - udelay(100000); /* 100 ms */ - *addr = 0x70; /*Read status register command*/ - tmp = (short)*addr & 0x00FF; /* Read status */ - start = get_timer(0); - } - if( tmp & INTEL_FLASH_STATUS_PS ) - flash_decode_status_bits(tmp); - - *addr =0x0050; /*Clear status register*/ - - /* reset to read mode */ - *addr = 0xffff; - - return 0; -} diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds deleted file mode 100644 index 04995ea..0000000 --- a/board/flagadm/u-boot.lds +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug deleted file mode 100644 index 3165d56..0000000 --- a/board/flagadm/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/funkwerk/vovpn-gw/Makefile b/board/funkwerk/vovpn-gw/Makefile deleted file mode 100644 index f77cc60..0000000 --- a/board/funkwerk/vovpn-gw/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o m88e6060.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/funkwerk/vovpn-gw/config.mk b/board/funkwerk/vovpn-gw/config.mk deleted file mode 100644 index e59b483..0000000 --- a/board/funkwerk/vovpn-gw/config.mk +++ /dev/null @@ -1,21 +0,0 @@ -# (C) Copyright 2004 -# Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) -# -# Support for the Elmeg VoVPN Gateway Module -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -TEXT_BASE = 0xfff00000 diff --git a/board/funkwerk/vovpn-gw/flash.c b/board/funkwerk/vovpn-gw/flash.c deleted file mode 100644 index 7dd0d3f..0000000 --- a/board/funkwerk/vovpn-gw/flash.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * (C) Copyright 2004 - * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) - * - * Support for the Elmeg VoVPN Gateway Module - * ------------------------------------------ - * This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3 - * and 28F128J3A flashs working in 8 Bit mode. - * - * Most of this code is taken from existing u-boot source code. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_READ_STATUS 0x70 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xd0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_SUSPEND_ERASE 0xb0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_WRITE_BUFF 0xe8 -#define FLASH_CMD_PROG_RESUME 0xd0 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xd0 -#define FLASH_STATUS_DONE 0x80 - -#define FLASH_WRITE_BUFFER_SIZE 32 - -#ifdef CFG_FLASH_16BIT -#define FLASH_WORD_SIZE unsigned short -#define FLASH_ID_MASK 0xffff -#define FLASH_CMD_ADDR_SHIFT 0 -#else -#define FLASH_WORD_SIZE unsigned char -#define FLASH_ID_MASK 0xff -/* A0 is not used in either 8x or 16x for READ ID */ -#define FLASH_CMD_ADDR_SHIFT 1 -#endif - - -static unsigned long -flash_get(volatile FLASH_WORD_SIZE *addr, flash_info_t *info) -{ - volatile FLASH_WORD_SIZE *p; - FLASH_WORD_SIZE value; - int i; - - addr[0] = FLASH_CMD_READ_ID; - - /* manufactor */ - value = addr[0 << FLASH_CMD_ADDR_SHIFT]; - switch (value) { - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - *addr = FLASH_CMD_RESET; - return (0); - - } - - /* device */ - value = addr[1 << FLASH_CMD_ADDR_SHIFT]; - switch (value) { - case (INTEL_ID_28F320J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; - case (INTEL_ID_28F640J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; - case (INTEL_ID_28F128J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - *addr = FLASH_CMD_RESET; - return (0); - } - - /* setup sectors */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = (unsigned long)addr + (i * info->size/info->sector_count); - } - - /* check protected sectors */ - for (i = 0; i < info->sector_count; i++) { - p = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = p[2 << FLASH_CMD_ADDR_SHIFT] & 1; - } - - /* reset bank */ - *addr = FLASH_CMD_RESET; - return (info->size); -} - -unsigned long -flash_init(void) -{ - unsigned long size; - int i; - - for (i=0; i= CFG_FLASH_BASE - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_FLASH, - CFG_MONITOR_FLASH+CFG_MONITOR_LEN-1, - &flash_info[0]); -#endif -#ifdef CFG_ENV_IS_IN_FLASH - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return (size); -} - -void -flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: printf ("28F320JA3 (32 Mbit)\n"); - break; - case FLASH_28F640J3A: printf ("28F640JA3 (64 Mbit)\n"); - break; - case FLASH_28F128J3A: printf ("28F128JA3 (128 Mbit)\n"); - break; - default: printf ("Unknown Chip Type"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -int -flash_erase(flash_info_t *info, int s_first, int s_last) -{ - unsigned long start, now, last; - int flag, prot, sect; - volatile FLASH_WORD_SIZE *addr; - FLASH_WORD_SIZE status; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return (1); - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Cannot erase unknown flash - aborted\n"); - return (1); - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect]) { - continue; - } - - addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#ifdef DEBUG - printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]); -#endif - - *addr = FLASH_CMD_CLEAR_STATUS; - *addr = FLASH_CMD_BLOCK_ERASE; - *addr = FLASH_CMD_ERASE_CONFIRM; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Flash erase timeout at address %lx\n", info->start[sect]); - *addr = FLASH_CMD_SUSPEND_ERASE; - *addr = FLASH_CMD_RESET; - return (1); - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - *addr = FLASH_CMD_RESET; - } - printf (" done\n"); - return (0); -} - -static int -write_buff2( volatile FLASH_WORD_SIZE *dst, - volatile FLASH_WORD_SIZE *src, - unsigned long cnt ) -{ - unsigned long start; - FLASH_WORD_SIZE status; - int flag, i; - - start = get_timer (0); - while (1) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - dst[0] = FLASH_CMD_WRITE_BUFF; - if ((status = *dst) & FLASH_STATUS_DONE) { - break; - } - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (-1); - } - } - dst[0] = (FLASH_WORD_SIZE)(cnt - 1); - for (i=0; i CFG_FLASH_WRITE_TOUT) { - *addr = FLASH_CMD_RESET; - return (-1); - } - } - *addr = FLASH_CMD_RESET; - return (0); -} - -/* - * write_buff return values: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ -int -write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt) -{ - volatile FLASH_WORD_SIZE *addr, *dst; - unsigned long bcnt; - int flag, i; - - if (info->flash_id == FLASH_UNKNOWN) { - return (4); - } - - addr = (volatile FLASH_WORD_SIZE *)(info->start[0]); - dst = (volatile FLASH_WORD_SIZE *) udst; - -#ifdef CFG_FLASH_16BIT -#error NYI -#else - while (cnt > 0) { - /* Check if buffer write is possible */ - if (cnt > 1 && (((unsigned long)dst & (FLASH_WRITE_BUFFER_SIZE - 1)) == 0)) { - bcnt = cnt > FLASH_WRITE_BUFFER_SIZE ? FLASH_WRITE_BUFFER_SIZE : cnt; - /* Check if Flash is (sufficiently) erased */ - for (i=0; istart[sector]); - *addr = FLASH_CMD_CLEAR_STATUS; - *addr = FLASH_CMD_PROTECT; - - if(prot) { - *addr = FLASH_CMD_PROTECT_SET; - } else { - *addr = FLASH_CMD_PROTECT_CLEAR; - } - - /* wait for error or finish */ - start = get_timer (0); - while(!(addr[0] & FLASH_STATUS_DONE)){ - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { - printf("Flash protect timeout at address %lx\n", info->start[sector]); - addr[0] = FLASH_CMD_RESET; - return (1); - } - } - - /* Set software protect flag */ - info->protect[sector] = prot; - *addr = FLASH_CMD_RESET; - return (0); -} diff --git a/board/funkwerk/vovpn-gw/m88e6060.c b/board/funkwerk/vovpn-gw/m88e6060.c deleted file mode 100644 index 03a03d0..0000000 --- a/board/funkwerk/vovpn-gw/m88e6060.c +++ /dev/null @@ -1,262 +0,0 @@ -/* - * (C) Copyright 2004 - * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) - * - * Support for the Elmeg VoVPN Gateway Module - * ------------------------------------------ - * Initialize Marvell M88E6060 Switch - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#include "m88e6060.h" - -#if (CONFIG_COMMANDS & CFG_CMD_NET) -static int prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 }; -static int phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 }; - -static m88x_regCfg_t prtCfg0[] = { - { 4, 0x3e7c, 0x8000 }, - { 4, 0x3e7c, 0x8003 }, - { 6, 0x0fc0, 0x001e }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t prtCfg1[] = { - { 4, 0x3e7c, 0x8000 }, - { 4, 0x3e7c, 0x8003 }, - { 6, 0x0fc0, 0x001d }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t prtCfg2[] = { - { 4, 0x3e7c, 0x8000 }, - { 4, 0x3e7c, 0x8003 }, - { 6, 0x0fc0, 0x001b }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t prtCfg3[] = { - { 4, 0x3e7c, 0x8000 }, - { 4, 0x3e7c, 0x8003 }, - { 6, 0x0fc0, 0x0017 }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t prtCfg4[] = { - { 4, 0x3e7c, 0x8000 }, - { 4, 0x3e7c, 0x8003 }, - { 6, 0x0fc0, 0x000f }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t *prtCfg[M88X_PRT_CNT] = { - prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL -}; - -static m88x_regCfg_t phyCfgX[] = { - { 4, 0xfa1f, 0x01e0 }, - { 0, 0x213f, 0x1200 }, - { 24, 0x81ff, 0x1200 }, - { -1, 0xffff, 0x0000 } -}; - -static m88x_regCfg_t *phyCfg[M88X_PHY_CNT] = { - phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL -}; - -#if 0 -static void -m88e6060_dump( int devAddr ) -{ - int i, j; - unsigned short val[6]; - - printf( "M88E6060 Register Dump\n" ); - printf( "====================================\n" ); - printf( "PortNo 0 1 2 3 4 5\n" ); - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] ); - printf( "STAT %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] ); - printf( "ID %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] ); - printf( "CNTL %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] ); - printf( "VLAN %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] ); - printf( "PAV %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] ); - printf( "RX %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - for (i=0; i<6; i++) - miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] ); - printf( "TX %04hx %04hx %04hx %04hx %04hx %04hx\n", - val[0],val[1],val[2],val[3],val[4],val[5] ); - - printf( "------------------------------------\n" ); - printf( "PhyNo 0 1 2 3 4\n" ); - for (i=0; i<9; i++) { - for (j=0; j<5; j++) { - miiphy_read( devAddr+phyTab[j],i,&val[j] ); - } - printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n", - i,val[0],val[1],val[2],val[3],val[4] ); - } - for (i=0x10; i<0x1d; i++) { - for (j=0; j<5; j++) { - miiphy_read( devAddr+phyTab[j],i,&val[j] ); - } - printf( "0x%02x %04hx %04hx %04hx %04hx %04hx\n", - i,val[0],val[1],val[2],val[3],val[4] ); - } -} -#endif - -int -m88e6060_initialize( int devAddr ) -{ - static char *_f = "m88e6060_initialize:"; - m88x_regCfg_t *p; - int err; - int i; - unsigned short val; - - /*** reset all phys into powerdown ************************************/ - for (i=0, err=0; ienetaddr - val = (ea[4] << 8) | ea[5]; - err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val ); - val = (ea[2] << 8) | ea[3]; - err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val ); - val = (ea[0] << 8) | ea[1]; -#undef ea - val &= 0xfeff; /* clear DiffAddr */ - err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val ); - if (err) { - printf( "%s [ERR] switch mac address register\n",_f ); - return( -1 ); - } - - /* !DiscardExcessive, MaxFrameSize, CtrMode */ - err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val ); - val &= 0xd870; - val |= 0x0500; - err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val ); - if (err) { - printf( "%s [ERR] switch global control register\n",_f ); - return( -1 ); - } - - /* LernDis off, ATUSize 1024, AgeTime 5min */ - err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val ); - val &= 0x000f; - val |= 0x2130; - err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val ); - if (err) { - printf( "%s [ERR] atu control register\n",_f ); - return( -1 ); - } - - /*** initialize ports *************************************************/ - for (i=0; ireg != -1) { - err = 0; - err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val ); - val &= p->msk; - val |= p->val; - err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val ); - if (err) { - printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg ); - /* XXX what todo */ - } - p++; - } - } - - /*** initialize phys **************************************************/ - for (i=0; ireg != -1) { - err = 0; - err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val ); - val &= p->msk; - val |= p->val; - err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val ); - if (err) { - printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg ); - /* XXX what todo */ - } - p++; - } - } - udelay(100000); - return( 0 ); -} -#endif diff --git a/board/funkwerk/vovpn-gw/m88e6060.h b/board/funkwerk/vovpn-gw/m88e6060.h deleted file mode 100644 index 15d4583..0000000 --- a/board/funkwerk/vovpn-gw/m88e6060.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2004 - * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) - * - * Support for the Elmeg VoVPN Gateway Module - * ------------------------------------------ - * Initialize Marvell M88E6060 Switch - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _INC_m88e6060_h_ -#define _INC_m88e6060_h_ - -/* ************************************************************************** */ -/* *** DEFINES ************************************************************** */ - -/* switch hw */ -#define M88X_PRT_CNT 6 -#define M88X_PHY_CNT 5 - -/* phy register offsets */ -#define M88X_PHY_CNTL 0x00 -#define M88X_PHY_STAT 0x00 -#define M88X_PHY_ID0 0x02 -#define M88X_PHY_ID1 0x03 -#define M88X_PHY_ANEG_ADV 0x04 -#define M88X_PHY_LPA 0x05 -#define M88X_PHY_ANEG_EXP 0x06 -#define M88X_PHY_NPT 0x07 -#define M88X_PHY_LPNP 0x08 - -/* port register offsets */ -#define M88X_PRT_STAT 0x00 -#define M88X_PRT_ID 0x03 -#define M88X_PRT_CNTL 0x04 -#define M88X_PRT_VLAN 0x06 -#define M88X_PRT_PAV 0x0b -#define M88X_PRT_RX 0x10 -#define M88X_PRT_TX 0x11 - -/* global/atu register offsets */ -#define M88X_GLB_STAT 0x00 -#define M88X_GLB_MAC01 0x01 -#define M88X_GLB_MAC23 0x02 -#define M88X_GLB_MAC45 0x03 -#define M88X_GLB_CNTL 0x04 -#define M88X_ATU_CNTL 0x0a -#define M88X_ATU_OP 0x0b - -/* id0 register - 0x02 */ -#define M88X_PHY_ID0_VALUE 0x0141 - -/* id1 register - 0x03 */ -#define M88X_PHY_ID1_VALUE 0x0c80 /* without revision ! */ - - -/* misc */ -#define M88E6060_ID ((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE) - -/* ************************************************************************** */ -/* *** TYPEDEFS ************************************************************* */ - -typedef struct { - int reg; - unsigned short msk; - unsigned short val; -} m88x_regCfg_t; - -/* ************************************************************************** */ -/* *** PROTOTYPES *********************************************************** */ - -extern int m88e6060_initialize( int ); - -#endif /* _INC_m88e6060_h_ */ diff --git a/board/funkwerk/vovpn-gw/u-boot.lds b/board/funkwerk/vovpn-gw/u-boot.lds deleted file mode 100644 index bf8048d..0000000 --- a/board/funkwerk/vovpn-gw/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Yuli Barcohen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c deleted file mode 100644 index 97f81ee..0000000 --- a/board/funkwerk/vovpn-gw/vovpn-gw.c +++ /dev/null @@ -1,375 +0,0 @@ -/* - * (C) Copyright 2004 - * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) - * - * Support for the Elmeg VoVPN Gateway Module - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include "m88e6060.h" - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1252 */ - /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* GPI BP_RES */ - /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1253 */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 RMII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII CRS_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII RX_ERR */ - /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ - /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ - /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ - /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ - /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */ - /* PA20 */ { 1, 0, 0, 1, 0, 1 }, /* GPO LED STATUS */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[1] */ - /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1255 */ - /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP???? */ - /* PA13 */ { 1, 0, 0, 1, 0, 1 }, /* GPO EN_BCTL1 XXX jse */ - /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* GPO SWITCH RESET */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL1 RESET */ - /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL2 RESET */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exit */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1257 */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII CRS_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 RMII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RX_ERR */ - /* PB27 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1TXD XXX val=0 */ - /* PB26 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1RXD XXX val,dr */ - /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1259 */ - /* PB24 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B2 L1RSYNC */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[1] */ - /* PB19 */ { 1, 0, 0, 1, 0, 1 }, /* GPO PHY MDC */ - /* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* GPIO PHY MDIO */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1183 */ - /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1184 */ - /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* CLK5 TDM_A1 RX */ - /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1185 */ - /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1178 */ - /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1186 */ - /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* CLK9 TDM_B2 RX */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* CLK10 FCC1 RMII REFCLK */ - /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1187 */ - /* PC20 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1182 */ - /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1188 */ - /* PC18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO HW RESET */ - /* PC17 */ { 1, 1, 0, 1, 0, 0 }, /* BRG8 SWITCH CLKIN */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* CLK16 FCC2 RMII REFCLK */ - /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_3 */ - /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_2 */ - /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_1 */ - /* PC12 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_0 */ - /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1176 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1177 */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_3 */ - /* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_2 */ - /* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_1 */ - /* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_0 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1192 */ - /* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* GPI RACK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1193 */ - /* PD30 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1194 */ - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1195 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1179 */ - /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1180 */ - /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1181 */ - /* PD22 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1TXD */ - /* PD21 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1RXD */ - /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */ - /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1196 */ - /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1197 */ - /* PD17 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1198 */ - /* PD16 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1199 */ - /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1250 */ - /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1251 */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD7 */ { 0, 0, 0, 1, 0, 0 }, /* GPO FL_BYTE */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */ - } -}; - -void reset_phy (void) -{ - volatile ioport_t *iop; -#if (CONFIG_COMMANDS & CFG_CMD_NET) - int i; - unsigned short val; -#endif - - iop = ioport_addr((immap_t *)CFG_IMMR, 0); - - /* Reset the PHY */ - iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */ -#if (CONFIG_COMMANDS & CFG_CMD_NET) - udelay(20000); - iop->pdat |= 0x00080000; - for (i=0; i<100; i++) { - udelay(20000); - if (bb_miiphy_read("FCC1 ETHERNET", CFG_PHY_ADDR,2,&val ) == 0) { - break; - } - } - /* initialize switch */ - m88e6060_initialize( CFG_PHY_ADDR ); -#endif -} - -static unsigned long UPMATable[] = { - 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ - 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */ - 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */ - 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ - 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ - 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */ - 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ - 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */ -}; - -int board_early_init_f (void) -{ - volatile immap_t *immap; - volatile memctl8260_t *memctl; - volatile unsigned char *dummy; - int i; - - immap = (immap_t *) CFG_IMMR; - memctl = &immap->im_memctl; - -#if 0 - /* CS2-5 - DSP via UPMA */ - dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK); - memctl->memc_mar = 0; - memctl->memc_mamr = MxMR_OP_WARR; - for (i = 0; i < 64; i++) { - memctl->memc_mdr = UPMATable[i]; - *dummy = 0; - } - memctl->memc_mamr = 0x00044440; -#else - /* CS7 - DPRAM via UPMA */ - dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); - memctl->memc_mar = 0; - memctl->memc_mamr = MxMR_OP_WARR; - for (i = 0; i < 64; i++) { - memctl->memc_mdr = UPMATable[i]; - *dummy = 0; - } - memctl->memc_mamr = 0x00044440; -#endif - return 0; -} - -int misc_init_r (void) -{ - volatile ioport_t *iop; - unsigned char temp; -#if 0 - /* DUMP UPMA RAM */ - volatile immap_t *immap; - volatile memctl8260_t *memctl; - volatile unsigned char *dummy; - unsigned char c; - int i; - - immap = (immap_t *) CFG_IMMR; - memctl = &immap->im_memctl; - - - dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); - memctl->memc_mar = 0; - memctl->memc_mamr = MxMR_OP_RARR; - for (i = 0; i < 64; i++) { - c = *dummy; - printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i, - memctl->memc_mamr, - memctl->memc_mar, - memctl->memc_mdr ); - } - memctl->memc_mamr = 0x00044440; -#endif - /* enable buffers (DSP, DPRAM) */ - iop = ioport_addr((immap_t *)CFG_IMMR, 0); - iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */ - - /* destroy DPRAM magic */ - *(volatile unsigned char *)0xf0500000 = 0x00; - - /* clear any pending DPRAM irq */ - temp = *(volatile unsigned char *)0xf05003ff; - - /* write module-id into DPRAM */ - *(volatile unsigned char *)0xf0500201 = 0x50; - - return 0; -} - -#if defined(CONFIG_HAVE_OWN_RESET) -int -do_reset (void *cmdtp, int flag, int argc, char *argv[]) -{ - volatile ioport_t *iop; - - iop = ioport_addr((immap_t *)CFG_IMMR, 2); - iop->pdat |= 0x00002000; /* PC18 = HW_RESET */ - return 1; -} -#endif /* CONFIG_HAVE_OWN_RESET */ - -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) - -long int initdram (int board_type) -{ -#ifndef CFG_RAMBOOT - volatile immap_t *immap; - volatile memctl8260_t *memctl; - volatile uchar *ramaddr; - int i; - uchar c; - - immap = (immap_t *) CFG_IMMR; - memctl = &immap->im_memctl; - ramaddr = (uchar *) CFG_SDRAM_BASE; - c = 0xff; - - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x01267893; - immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef; - immap->im_siu_conf.sc_tescr1 = 0x00000000; - immap->im_siu_conf.sc_tescr2 = 0x00000000; - - memctl->memc_mptpr = CFG_MPTPR; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_SDRAM_BASE | CFG_BR1_PRELIM; - - /* Precharge all banks */ - memctl->memc_psdmr = CFG_PSDMR | 0x28000000; - *ramaddr = c; - - /* CBR refresh */ - memctl->memc_psdmr = CFG_PSDMR | 0x08000000; - for (i = 0; i < 8; i++) - *ramaddr = c; - - /* Mode Register write */ - memctl->memc_psdmr = CFG_PSDMR | 0x18000000; - *ramaddr = c; - - /* Refresh enable */ - memctl->memc_psdmr = CFG_PSDMR | 0x40000000; - *ramaddr = c; -#endif /* CFG_RAMBOOT */ - - return (CFG_SDRAM_SIZE); -} - -int checkboard (void) -{ -#ifdef CONFIG_CLKIN_66MHz - puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n"); -#else - puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n"); -#endif - return 0; -} diff --git a/board/g2000/Makefile b/board/g2000/Makefile deleted file mode 100644 index 5471d13..0000000 --- a/board/g2000/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o strataflash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/g2000/config.mk b/board/g2000/config.mk deleted file mode 100644 index 25b2105..0000000 --- a/board/g2000/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd PLU405 boards -# - -TEXT_BASE = 0xFFFC0000 -#TEXT_BASE = 0x00FC0000 diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c deleted file mode 100644 index 3f78753..0000000 --- a/board/g2000/g2000.c +++ /dev/null @@ -1,312 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define MEM_MCOPT1_INIT_VAL 0x00800000 -#define MEM_RTR_INIT_VAL 0x04070000 -#define MEM_PMIT_INIT_VAL 0x07c00000 -#define MEM_MB0CF_INIT_VAL 0x00082001 -#define MEM_MB1CF_INIT_VAL 0x04082000 -#define MEM_SDTR1_INIT_VAL 0x00854005 -#define SDRAM0_CFG_ENABLE 0x80000000 - -#define CFG_SDRAM_SIZE 0x04000000 /* 64 MB */ - -int board_early_init_f (void) -{ -#if 0 /* test-only */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000010); - mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */ - mtdcr (uictr, 0x00000010); /* set int trigger levels */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ -#else - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFFF0); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ -#endif - -#if 1 /* test-only */ - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ -#endif - - return 0; -} - - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); -#endif - - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming G2000"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} - - -/* ------------------------------------------------------------------------- - G2000 rev B is an embeded design. we don't read for spd of this version. - Doing static SDRAM controller configuration in the following section. - ------------------------------------------------------------------------- */ - -long int init_sdram_static_settings(void) -{ -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) - /* disable memcontroller so updates work */ - mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL ); - mtsdram0( mem_rtr , MEM_RTR_INIT_VAL ); - mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL ); - mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL ); - mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL ); - mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL ); - - /* SDRAM have a power on delay, 500 micro should do */ - udelay(500); - mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); - - return (CFG_SDRAM_SIZE); /* CFG_SDRAM_SIZE is in G2000.h */ - } - - -long int initdram (int board_type) -{ - long int ret; - -/* flzt, we can still turn this on in the future */ -/* #ifdef CONFIG_SPD_EEPROM - ret = spd_sdram (); -#else - ret = init_sdram_static_settings(); -#endif -*/ - - ret = init_sdram_static_settings(); - - return ret; -} - - -#if 1 /* test-only */ -void sdram_init(void) -{ - init_sdram_static_settings(); -} -#endif - - -#if 0 /* test-only */ -long int initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} -#endif - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - -#if 0 /* test-only !!! */ -int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong ap, cr; - - printf("\nEBC registers for PPC405GP:\n"); - mfebc(pb0ap, ap); mfebc(pb0cr, cr); - printf("0: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb1ap, ap); mfebc(pb1cr, cr); - printf("1: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb2ap, ap); mfebc(pb2cr, cr); - printf("2: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb3ap, ap); mfebc(pb3cr, cr); - printf("3: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb4ap, ap); mfebc(pb4cr, cr); - printf("4: AP=%08lx CP=%08lx\n", ap, cr); - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpebc, 1, 1, do_dumpebc, - "dumpebc - Dump all EBC registers\n", - NULL -); - - -int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int i; - - printf("\nDevice Configuration Registers (DCR's) for PPC405GP:"); - for (i=0; i<=0x1e0; i++) { - if (!(i % 0x8)) { - printf("\n%04x ", i); - } - printf("%08lx ", get_dcr(i)); - } - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpdcr, 1, 1, do_dumpdcr, - "dumpdcr - Dump all DCR registers\n", - NULL -); - - -int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:"); - printf("\n%04x %08x ", 947, mfspr(947)); - printf("\n%04x %08x ", 9, mfspr(9)); - printf("\n%04x %08x ", 1014, mfspr(1014)); - printf("\n%04x %08x ", 1015, mfspr(1015)); - printf("\n%04x %08x ", 1010, mfspr(1010)); - printf("\n%04x %08x ", 957, mfspr(957)); - printf("\n%04x %08x ", 1008, mfspr(1008)); - printf("\n%04x %08x ", 1018, mfspr(1018)); - printf("\n%04x %08x ", 954, mfspr(954)); - printf("\n%04x %08x ", 950, mfspr(950)); - printf("\n%04x %08x ", 951, mfspr(951)); - printf("\n%04x %08x ", 981, mfspr(981)); - printf("\n%04x %08x ", 980, mfspr(980)); - printf("\n%04x %08x ", 982, mfspr(982)); - printf("\n%04x %08x ", 1012, mfspr(1012)); - printf("\n%04x %08x ", 1013, mfspr(1013)); - printf("\n%04x %08x ", 948, mfspr(948)); - printf("\n%04x %08x ", 949, mfspr(949)); - printf("\n%04x %08x ", 1019, mfspr(1019)); - printf("\n%04x %08x ", 979, mfspr(979)); - printf("\n%04x %08x ", 8, mfspr(8)); - printf("\n%04x %08x ", 945, mfspr(945)); - printf("\n%04x %08x ", 987, mfspr(987)); - printf("\n%04x %08x ", 287, mfspr(287)); - printf("\n%04x %08x ", 953, mfspr(953)); - printf("\n%04x %08x ", 955, mfspr(955)); - printf("\n%04x %08x ", 272, mfspr(272)); - printf("\n%04x %08x ", 273, mfspr(273)); - printf("\n%04x %08x ", 274, mfspr(274)); - printf("\n%04x %08x ", 275, mfspr(275)); - printf("\n%04x %08x ", 260, mfspr(260)); - printf("\n%04x %08x ", 276, mfspr(276)); - printf("\n%04x %08x ", 261, mfspr(261)); - printf("\n%04x %08x ", 277, mfspr(277)); - printf("\n%04x %08x ", 262, mfspr(262)); - printf("\n%04x %08x ", 278, mfspr(278)); - printf("\n%04x %08x ", 263, mfspr(263)); - printf("\n%04x %08x ", 279, mfspr(279)); - printf("\n%04x %08x ", 26, mfspr(26)); - printf("\n%04x %08x ", 27, mfspr(27)); - printf("\n%04x %08x ", 990, mfspr(990)); - printf("\n%04x %08x ", 991, mfspr(991)); - printf("\n%04x %08x ", 956, mfspr(956)); - printf("\n%04x %08x ", 284, mfspr(284)); - printf("\n%04x %08x ", 285, mfspr(285)); - printf("\n%04x %08x ", 986, mfspr(986)); - printf("\n%04x %08x ", 984, mfspr(984)); - printf("\n%04x %08x ", 256, mfspr(256)); - printf("\n%04x %08x ", 1, mfspr(1)); - printf("\n%04x %08x ", 944, mfspr(944)); - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpspr, 1, 1, do_dumpspr, - "dumpspr - Dump all SPR registers\n", - NULL -); -#endif diff --git a/board/g2000/strataflash.c b/board/g2000/strataflash.c deleted file mode 100644 index 8446e02..0000000 --- a/board/g2000/strataflash.c +++ /dev/null @@ -1,793 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for ppcboot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#else - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - - CFG_MONITOR_LEN, - - 1, &flash_info[1]); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO - int k; - int size; - int erased; - volatile unsigned long *flash; - - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;iportwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; iportwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; isector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - if (len & 0x1) { /* test-only: unaligned size */ - puts("\nUnalgined size!!!\n"); /* test-only */ - cnt++; - } - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/g2000/u-boot.lds b/board/g2000/u-boot.lds deleted file mode 100644 index 43f7765..0000000 --- a/board/g2000/u-boot.lds +++ /dev/null @@ -1,151 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/gcplus/Makefile b/board/gcplus/Makefile deleted file mode 100644 index 1954d66..0000000 --- a/board/gcplus/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# 2003 (c) MontaVista Software, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := gcplus.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/gcplus/config.mk b/board/gcplus/config.mk deleted file mode 100644 index 57326b8..0000000 --- a/board/gcplus/config.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# ADS GCPlus board with SA1110 cpu -# -# The ADS GCPlus has 2 banks of 16 MiB SDRAM -# -# We use the ADS GCPlus Linux boot ROM to load U-Boot into SDRAM -# at c020'0000 and then move ourself to c8f0'0000. Basically, just -# install the U-Boot binary as you would the Linux zImage and then -# reap the benfits of more convenient Linux development cycles, i.e. -# bootp;tftp;bootm, repeat, etc.,. -# - -TEXT_BASE = 0xc8f00000 diff --git a/board/gcplus/flash.c b/board/gcplus/flash.c deleted file mode 100644 index 36d7363..0000000 --- a/board/gcplus/flash.c +++ /dev/null @@ -1,440 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * 2003 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPW * addr, flash_info_t * info); -static int write_data(flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t * info); -void inline spin_wheel(void); - -/*----------------------------------------------------------------------- - */ - -unsigned long -flash_init(void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets(PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void -flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void -flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf("INTEL "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf("28F128J3A\n"); - break; - case FLASH_28F640J5: - printf("28F640J5\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong -flash_get_size(FPW * addr, flash_info_t * info) -{ - volatile FPW value; - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb(); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb(); - value = addr[1]; /* device ID */ - switch (value) { - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - case (FPW) INTEL_ID_28F640J5: - info->flash_id += FLASH_28F640J5; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int -flash_erase(flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - start = get_timer(0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = (FPW) 0x00500050; /* clear status register cmd. */ - *addr = (FPW) 0x00FF00FF; /* resest to read mode */ - - printf(" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int -write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data(info, wp, SWAP(data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data(info, wp, SWAP(data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel(); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data(info, wp, SWAP(data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_data(flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf("not erased at %08lX (%lX)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline -spin_wheel(void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/gcplus/gcplus.c b/board/gcplus/gcplus.c deleted file mode 100644 index 261e894..0000000 --- a/board/gcplus/gcplus.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * 2003-2004 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations - */ - -int -board_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_arch_number = MACH_TYPE_GRAPHICSCLIENT; - - gd->bd->bi_boot_params = 0xc000003c; /* Weird address? */ - - /* Most of the ADS GCPlus I/O is connected to Static nCS2. - * So I'm brute forcing nCS2 timiming here for worst case. - */ - MSC1 &= ~0xFFFF; - MSC1 |= 0x8649; - - /* Nothing is connected to Static nCS4 or nCS5. But I'm using - * nCS4 as a paranoia safe guard to force nCS2, nOE; nWE high - * after accessing I/O via (non-VLIO) nCS2. What can I say, I'm - * paranoid and lack decent tools to alleviate my fear. I sure - * do wish I had a logic analyzer. : ( - */ - - MSC2 = 0xfff9fff9; - - return 0; -} - -int -dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - - return (0); -} diff --git a/board/gcplus/lowlevel_init.S b/board/gcplus/lowlevel_init.S deleted file mode 100644 index f292c4d..0000000 --- a/board/gcplus/lowlevel_init.S +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * 2003-2004 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include "config.h" -#include "version.h" - - - .globl lowlevel_init -lowlevel_init: - /* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us. - * However the darn thing leaves the MMU enabled before handing control - * over to us. So we need to disable the MMU and we use lowlevel_init - * to do it. - */ - -@ The following code segment was borrowed with gratitude from: -@ linux-2.4.19-rmk7/arch/arm/boot/compressed/head-sa1100.S - - @ Data cache might be active. - @ Be sure to flush kernel binary out of the cache, - @ whatever state it is, before it is turned off. - @ This is done by fetching through currently executed - @ memory to be sure we hit the same cache. - bic r2, pc, #0x1f - add r3, r2, #0x4000 @ 16 kb is quite enough... -1: ldr r0, [r2], #32 - teq r2, r3 - bne 1b - mcr p15, 0, r0, c7, c10, 4 @ drain WB - mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches - - @ disabling MMU and caches - mrc p15, 0, r0, c1, c0, 0 @ read control reg - bic r0, r0, #0x0d @ clear WB, DC, MMU - bic r0, r0, #0x1000 @ clear Icache - mcr p15, 0, r0, c1, c0, 0 - - nop - nop - nop - nop - nop - - b 2f -2: - nop - nop - nop - nop - nop - - - mov pc, lr diff --git a/board/gcplus/u-boot.lds b/board/gcplus/u-boot.lds deleted file mode 100644 index 9900a57..0000000 --- a/board/gcplus/u-boot.lds +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * 2003 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/sa1100/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/gen860t/Makefile b/board/gen860t/Makefile deleted file mode 100644 index dd7ecf1..0000000 --- a/board/gen860t/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o beeper.o fpga.o ioport.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/gen860t/README b/board/gen860t/README deleted file mode 100644 index 7205afb..0000000 --- a/board/gen860t/README +++ /dev/null @@ -1,146 +0,0 @@ -This directory contains board specific code for a generic MPC860T based -embedded computer, called 'GEN860T'. The design is generic in the sense that -common, readily available components are used and that the architecture of the -system is relatively straightforward: - - One eight bit wide boot (FLASH) memory - 32 bit main memory using SDRAM - DOC 2000+ - Ethernet PHY - Some I2C peripheral devices: Atmel AT24C256 EEPROM, Maxim DS1337 RTC. - Some other miscellaneous peripherals - -NOTE: There are references to a XIlinx FPGA and Mil-Std 1553 databus in this -port. I guess the computer is not as generic as I first said 8) However, -these extras can be safely ignored. - -Given the GEN860T files, it should be pretty easy to reverse engineer the -hardware configuration, if that's useful to you. Hopefully, this code will -be useful to someone as a basis for a port to a new system or as a head start -on a custom design. If you end up using any of this, I would appreciate -hearing from you, especially if you discover bugs or find ways to improve the -quality of this U-Boot port. - -Here are the salient features of the system: -Clock : 33.3 Mhz oscillator -Processor core frequency : 66.6 Mhz if in 1:2:1 mode; can also run 1:1 -Bus frequency : 33.3 Mhz - -Main memory: - Type : SDRAM - Width : 32 bits - Size : 64 mibibytes - Chip : Two Micron MT48LC16M16A2TG-7E - CS : MPC860T CS1*/UPMA - UPMA CONNECTIONS: - SDRAM A10 : GPLA0* - SDRAM CAS* : GPLA2* - SDRAM WE* : GPLA3* - SDRAM RAS* : GPLA4* - -Boot memory: - Type : FLASH - Width : 8 bits - Size : 16 mibibytes - Chip : One Intel 28F128J3A (StrataFlash) - CS : MPC860T CS0*/GPCM (this is the "boot" chip select) - -EEPROM memory: - Type : Serial I2C EEPROM - Width : 8 bits - Size : 32 kibibytes - Chip : One Atmel AT25C256 - CS : 0x50 (external I2C address pins on device are tied to GND) - -Filesystem memory: - Type : NAND FLASH (Toshiba) - Width : 8 bits (i.e. interface to DOC is 8 bits) - Size : 32 mibibytes - Chip : One DiskOnCHip Millenium Plus (DOC 2000+) - CS : MPC860T CS2*/GPCM - -Network support: - MAC : MPC86OT FEC (Fast Ethernet Controller) - PHY : Intel LXT971A - MII Addr: 0x0 (hardwired on the board) - MII IRQ : - -Console: - RS-232 on SMC1 (Maxim MAX3232 LVCMOS-RS232 level shifter) - -Real Time Clock: - Type : Low power, I2C interface - Chip : Maxim DS1337 - CS : Address 0x68 on I2C bus - - The MPC860T's internal RTC has a defect in Mask rev D that increases - the current drain on the KAPWR line to 10 mA. Since this is an - unreasonable amount of current draw for a RTC, and Motorola does not - plan to fix this in future mask revisions, a serial (I2C) RTC that - works has been included instead. NOTE that the DS1337 can be - configured to output a 32768 Hz clock while the main power is on. - This clock output has been routed to the MPC860T's EXTAL pin to allow - the internal RTC to be used. NOTE also that due to yet another - defect in the rev D mask, the RTC does not operate reliably when the - internal RTC divisor is set to use a 32768 Hz reference. So just use - the I2C RTC. - -Miscellaneous: - Xilinx Virtex FPGA on CS3*/GPCM. - Virtex FPGA slave SelectMap interface on cs4*/UPMB. - Mil-Std 1553 databus interface on CS5*/GPCM. - Audio sounder (beeper) with digital volume control connected to SPKROUT. - -SC variant: - A reduced-feature version of the GEN860T port is also supported: GEN860T_SC. - The 'SC' variant only provides support for the Virtex FPGA, SDRAM main - memory, EEPROM and flash memory. The system clock frequency is reduced - to 24 MHz. - -Issues: - The DOC 2000+ returns 0x40 as its device ID when probed using the method - desxribed in the DOC datasheet. Unfortunately, the U-Boot DOC driver - does not recognize this device. As of this writing, it seems that MTD - does not support the DOC 2000+ either. - -Status: - Everything appears to work except DOC support. As of this writing, - David Woodhouse has stated on the MTD mailing list that he has no - knowledge of the DOC Millineum Plus and therfore there is no support - in MTD for this device. I wish I had known this sooner :( - -The GEN860T board specific files and configuration is based on the work -of others who have contributed to U-Boot. The copyright and license notices -of these authors have been retained wherever their code has been reused. -All new code to support the GEN860T board is: - - (C) Copyright 2001-2003 - Keith Outwater (keith_outwater@mvis.com) - -and the following license applies: - -This program is free software; you can redistribute it and/or -modify it under the terms of the GNU General Public License as -published by the Free Software Foundation; either version 2 of -the License, or (at your option) any later version. - -This program is distributed in the hope that it will be useful, -WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place, Suite 330, Boston, -MA 02111-1307 USA - -Thanks to Wolfgang Denk for a great software package and to everyone -who contributed to its development. - -Keith Outwater -Sr. Staff Engineer -Microvision, Inc. - - - -vim: set ts=4 sw=4 tw=78: diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c deleted file mode 100644 index 46fe66b..0000000 --- a/board/gen860t/beeper.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * (C) Copyright 2002 - * Keith Outwater, keith_outwater@mvis.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* - * Basic beeper support for the GEN860T board. The GEN860T includes - * an audio sounder driven by a Phillips TDA8551 amplifier. The - * TDA8551 features a digital volume control which uses a "trinary" - * input (high/high-Z/low) to set volume. The 860's SPKROUT pin - * drives the amplifier input. - */ - - -/* - * Initialize beeper-related hardware. Initialize timer 1 for use with - * the beeper. Use 66 Mhz internal clock with prescale of 33 to get - * 1 uS period per count. - * FIXME: we should really compute the prescale based on the reported - * core clock frequency. - */ -void -init_beeper(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1; - immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK) - | TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN; - immap->im_cpmtimer.cpmt_tcn1 = 0; - immap->im_cpmtimer.cpmt_ter1 = 0xffff; - immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1; -} - - -/* - * Set beeper frequency. Max allowed frequency is 2.5 KHz. This limit - * is mostly arbitrary, but the beeper isn't really much good beyond this - * frequency. - */ -void -set_beeper_frequency(uint frequency) -{ -#define FREQ_LIMIT 2500 - - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - /* - * Compute timer ticks given desired frequency. The timer is set up - * to count 0.5 uS per tick and it takes two ticks per cycle (Hz). - */ - if (frequency > FREQ_LIMIT) frequency = FREQ_LIMIT; - frequency = 1000000/frequency; - immap->im_cpmtimer.cpmt_trr1 = (ushort)frequency; -} - - -/* - * Turn the beeper on - */ -void -beeper_on(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1; -} - - -/* - * Turn the beeper off - */ -void -beeper_off(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1; -} - - -/* - * Increase or decrease the beeper volume. Volume can be set - * from off to full in 64 steps. To increase volume, the output - * pin is actively driven high, then returned to tristate. - * To decrease volume, output a low on the port pin (no need to - * change pin mode to tristate) then output a high to go back to - * tristate. - */ -void -set_beeper_volume(int steps) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - int i; - - if (steps >= 0) { - for (i = 0; i < (steps >= 64 ? 64 : steps); i++) { - immap->im_cpm.cp_pbodr &= ~(0x80000000 >> 19); - udelay(1); - immap->im_cpm.cp_pbodr |= (0x80000000 >> 19); - udelay(1); - } - } - else { - for (i = 0; i > (steps <= -64 ? -64 : steps); i--) { - immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19); - udelay(1); - immap->im_cpm.cp_pbdat |= (0x80000000 >> 19); - udelay(1); - } - } -} - - -/* - * Check the environment to see if the beeper needs beeping. - * Controlled by a sequence of the form: - * freq/delta volume/on time/off time;... where: - * freq = frequency in Hz (0 - 2500) - * delta volume = volume steps up or down (-64 <= vol <= 64) - * on time = time in mS - * off time = time in mS - * - * Return 1 on success, 0 on failure - */ -int -do_beeper(char *sequence) -{ -#define DELIMITER ';' - -int args[4]; -int i; -int val; -char *p = sequence; -char *tp; - - /* - * Parse the control sequence. This is a really simple parser - * without any real error checking. You can probably blow it - * up really easily. - */ - if (*p == '\0' || !isdigit(*p)) { - printf("%s:%d: null or invalid string (%s)\n", - __FILE__, __LINE__, p); - return 0; - } - - i = 0; - while (*p != '\0') { - while (*p != DELIMITER) { - if (i > 3) i = 0; - val = (int) simple_strtol(p, &tp, 0); - if (tp == p) { - printf("%s:%d: no digits or bad format\n", - __FILE__,__LINE__); - return 0; - } - else { - args[i] = val; - } - - i++; - if (*tp == DELIMITER) - p = tp; - else - p = ++tp; - } - p++; - - /* - * Well, we got something that has a chance of being correct - */ -#if 0 - for (i = 0; i < 4; i++) { - printf("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i, args[i]); - } - printf("\n"); -#endif - - set_beeper_frequency(args[0]); - set_beeper_volume(args[1]); - beeper_on(); - udelay(1000 * args[2]); - beeper_off(); - udelay(1000 * args[3]); - } - return 1; -} - -/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/gen860t/beeper.h b/board/gen860t/beeper.h deleted file mode 100644 index 535ee6c..0000000 --- a/board/gen860t/beeper.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2002 - * Keith Outwater, keith_outwater@mvis.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -void init_beeper(void); -void set_beeper_frequency(uint frequency); -void beeper_on(void); -void beeper_off(void); -void set_beeper_volume(int steps); -int do_beeper(char *sequence); - -/* vim: set ts=4 tw=78 sw=4: */ diff --git a/board/gen860t/config.mk b/board/gen860t/config.mk deleted file mode 100644 index 7acd904..0000000 --- a/board/gen860t/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# FLASH base address for GEN860T board -# - -TEXT_BASE = 0x40000000 diff --git a/board/gen860t/flash.c b/board/gen860t/flash.c deleted file mode 100644 index ec32d07..0000000 --- a/board/gen860t/flash.c +++ /dev/null @@ -1,644 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvsi.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/* - * Use buffered writes to flash by default - they are about 32x faster than - * single byte writes. - */ -#ifndef CFG_GEN860T_FLASH_USE_WRITE_BUFFER -#define CFG_GEN860T_FLASH_USE_WRITE_BUFFER -#endif - -/* - * Max time to wait (in mS) for flash device to allocate a write buffer. - */ -#ifndef CFG_FLASH_ALLOC_BUFFER_TOUT -#define CFG_FLASH_ALLOC_BUFFER_TOUT 100 -#endif - -/* - * These functions support a single Intel StrataFlash device (28F128J3A) - * in byte mode only!. The flash routines are very basic and simple - * since there isn't really any remapping necessary. - */ - -/* - * Intel SCS (Scalable Command Set) command definitions - * (taken from 28F128J3A datasheet) - */ -#define SCS_READ_CMD 0xff -#define SCS_READ_ID_CMD 0x90 -#define SCS_QUERY_CMD 0x98 -#define SCS_READ_STATUS_CMD 0x70 -#define SCS_CLEAR_STATUS_CMD 0x50 -#define SCS_WRITE_BUF_CMD 0xe8 -#define SCS_PROGRAM_CMD 0x40 -#define SCS_BLOCK_ERASE_CMD 0x20 -#define SCS_BLOCK_ERASE_RESUME_CMD 0xd0 -#define SCS_PROGRAM_RESUME_CMD 0xd0 -#define SCS_BLOCK_ERASE_SUSPEND_CMD 0xb0 -#define SCS_SET_BLOCK_LOCK_CMD 0x60 -#define SCS_CLR_BLOCK_LOCK_CMD 0x60 - -/* - * SCS status/extended status register bit definitions - */ -#define SCS_SR7 0x80 -#define SCS_XSR7 0x80 - -/*---------------------------------------------------------------------*/ -#if 0 -#define DEBUG_FLASH -#endif - -#ifdef DEBUG_FLASH -#define PRINTF(fmt,args...) printf(fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_data8 (flash_info_t *info, ulong dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - * Initialize the flash memory. - */ -unsigned long -flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - for (i= 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* - * The gen860t board only has one FLASH memory device, so the - * FLASH Bank configuration is done statically. - */ - PRINTF("\n## Get flash bank 1 size @ 0x%08x\n", FLASH_BASE0_PRELIM); - size_b0 = flash_get_size((vu_char *)FLASH_BASE0_PRELIM, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0: " - "ID 0x%lx, Size = 0x%08lx = %ld MB\n", - flash_info[0].flash_id,size_b0, size_b0 << 20); - } - - PRINTF("## Before remap:\n" - " BR0: 0x%08x OR0: 0x%08x\n BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* - * Remap FLASH according to real size - */ - memctl->memc_or0 |= (-size_b0 & 0xFFFF8000); - memctl->memc_br0 |= (CFG_FLASH_BASE & BR_BA_MSK); - - PRINTF("## After remap:\n" - " BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0); - - /* - * Re-do sizing to get full correct info - */ - size_b0 = flash_get_size ((vu_char *)CFG_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - flash_info[0].size = size_b0; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* - * Monitor protection is ON by default - */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* - * Environment protection ON by default - */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - PRINTF("## Final Flash bank size: 0x%08lx\n",size_b0); - return (size_b0); -} - - -/*----------------------------------------------------------------------- - * Fill in the FLASH offset table - */ -static void -flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 1024 * 128; - } - return; - - default: - printf ("Don't know sector offsets for FLASH" - " type 0x%lx\n", info->flash_id); - return; - } -} - - -/*----------------------------------------------------------------------- - * Display FLASH device info - */ -void -flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("Intel "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1024 * 1024)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - * Get size and other information for a FLASH device. - * NOTE: The following code cannot be run from FLASH! - */ -static -ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ -#define NO_FLASH 0 - - vu_char value[2]; - - /* - * Try to read the manufacturer ID - */ - addr[0] = SCS_READ_CMD; - addr[0] = SCS_READ_ID_CMD; - value[0] = addr[0]; - value[1] = addr[2]; - addr[0] = SCS_READ_CMD; - - PRINTF("Manuf. ID @ 0x%08lx: 0x%02x\n", (ulong)addr, value[0]); - switch (value[0]) { - case (INTEL_MANUFACT & 0xff): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (NO_FLASH); - } - - /* - * Read the device ID - */ - PRINTF("Device ID @ 0x%08lx: 0x%02x\n", (ulong)(&addr[2]), value[1]); - switch (value[1]) { - case (INTEL_ID_28F128J3A & 0xff): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 16 * 1024 * 1024; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (NO_FLASH); - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - return (info->size); -} - - -/*----------------------------------------------------------------------- - * Erase the specified sectors in the specified FLASH device - */ -int -flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* - * Start erase on unprotected sectors - */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_char *addr = (uchar *)(info->start[sect]); - vu_char status; - - /* - * Disable interrupts which might cause a timeout - */ - flag = disable_interrupts(); - - *addr = SCS_CLEAR_STATUS_CMD; - *addr = SCS_BLOCK_ERASE_CMD; - *addr = SCS_BLOCK_ERASE_RESUME_CMD; - - /* - * Re-enable interrupts if necessary - */ - if (flag) - enable_interrupts(); - - /* - * Wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - while (((status = *addr) & SCS_SR7) != SCS_SR7) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = SCS_BLOCK_ERASE_SUSPEND_CMD; - *addr = SCS_READ_CMD; - return 1; - } - - /* - * Show that we're waiting - */ - if ((now - last) > 1000) { /* 1 second */ - putc ('.'); - last = now; - } - } - *addr = SCS_READ_CMD; - } - } - printf (" done\n"); - return 0; -} - - -#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER -/* - * Allocate a flash buffer, fill it with data and write it to the flash. - * 0 - OK - * 1 - Timeout on buffer request - * - * NOTE: After the last call to this function, WSM status needs to be checked! - */ -static int -write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p, - uint count) -{ - vu_char *block_addr_p = NULL; - vu_char *start_addr_p = NULL; - ulong blocksize = info_p->size / (ulong)info_p->sector_count; - - int i; - uint time = get_timer(0); - - PRINTF("%s:%d: src: 0x%p dest: 0x%p count: %d\n", - __FUNCTION__, __LINE__, src_p, dest_p, count); - - /* - * What block are we in? We already know that the source address is - * in the flash address range, but we also can't cross a block boundary. - * We assume that the block does not cross a boundary (we'll check before - * calling this function). - */ - for (i = 0; i < info_p->sector_count; ++i) { - if ( ((ulong)dest_p >= info_p->start[i]) && - ((ulong)dest_p < (info_p->start[i] + blocksize)) ) { - PRINTF("%s:%d: Dest addr 0x%p is in block %d @ 0x%.8lx\n", - __FUNCTION__, __LINE__, dest_p, i, info_p->start[i]); - block_addr_p = (vu_char *)info_p->start[i]; - break; - } - } - - /* - * Request a buffer - */ - *block_addr_p = SCS_WRITE_BUF_CMD; - while ((*block_addr_p & SCS_XSR7) != SCS_XSR7) { - if (get_timer(time) > CFG_FLASH_ALLOC_BUFFER_TOUT) { - PRINTF("%s:%d: Buffer allocation timeout @ 0x%p (waited %d mS)\n", - __FUNCTION__, __LINE__, block_addr_p, - CFG_FLASH_ALLOC_BUFFER_TOUT); - return 1; - } - *block_addr_p = SCS_WRITE_BUF_CMD; - } - - /* - * Fill the buffer with data - */ - start_addr_p = dest_p; - *block_addr_p = count - 1; /* flash device wants count - 1 */ - PRINTF("%s:%d: Fill buffer at block addr 0x%p\n", - __FUNCTION__, __LINE__, block_addr_p); - for (i = 0; i < count; i++) { - *start_addr_p++ = *src_p++; - } - - /* - * Flush buffer to flash - */ - *block_addr_p = SCS_PROGRAM_RESUME_CMD; -#if 1 - time = get_timer(0); - while ((*block_addr_p & SCS_SR7) != SCS_SR7) { - if (get_timer(time) > CFG_FLASH_WRITE_TOUT) { - PRINTF("%s:%d: Write timeout @ 0x%p (waited %d mS)\n", - __FUNCTION__, __LINE__, block_addr_p, CFG_FLASH_WRITE_TOUT); - return 1; - } - } - -#endif - return 0; -} -#endif - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ -int -write_buff(flash_info_t *info_p, uchar *src_p, ulong addr, ulong count) -{ - int rc = 0; -#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER -#define FLASH_WRITE_BUF_SIZE 0x00000020 /* 32 bytes */ - int i; - uint bufs; - ulong buf_count; - vu_char *sp; - vu_char *dp; -#else - ulong wp; -#endif - - PRINTF("\n%s:%d: src: 0x%.8lx dest: 0x%.8lx size: %d (0x%.8lx)\n", - __FUNCTION__, __LINE__, (ulong)src_p, addr, (uint)count, count); - - if (info_p->flash_id == FLASH_UNKNOWN) { - return 4; - } - -#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER - sp = src_p; - dp = (uchar *)addr; - - /* - * For maximum performance, we want to align the start address to - * the beginning of a write buffer boundary (i.e. A4-A0 of the - * start address = 0). See how many bytes are required to get to a - * write-buffer-aligned address. If that number is non-zero, do - * non buffered writes of the non-aligned data. By doing non-buffered - * writes, we avoid the problem of crossing a block (sector) boundary - * with buffered writes. - */ - buf_count = FLASH_WRITE_BUF_SIZE - (addr & (FLASH_WRITE_BUF_SIZE - 1)); - if (buf_count == FLASH_WRITE_BUF_SIZE) { /* already on a boundary */ - buf_count = 0; - } - if (buf_count > count) { /* not a full buffers worth of data to write */ - buf_count = count; - } - count -= buf_count; - - PRINTF("%s:%d: Write buffer alignment count = %ld\n", - __FUNCTION__, __LINE__, buf_count); - while (buf_count-- >= 1) { - if ((rc = write_data8(info_p, (ulong)dp++, *sp++)) != 0) { - return (rc); - } - } - - PRINTF("%s:%d: count = %ld\n", __FUNCTION__, __LINE__, count); - if (count == 0) { /* all done */ - PRINTF("%s:%d: Less than 1 buffer (%d) worth of bytes\n", - __FUNCTION__, __LINE__, FLASH_WRITE_BUF_SIZE); - return (rc); - } - - /* - * Now that we are write buffer aligned, write full or partial buffers. - * The fact that we are write buffer aligned automatically avoids - * crossing a block address during a write buffer operation. - */ - bufs = count / FLASH_WRITE_BUF_SIZE; - PRINTF("%s:%d: %d (0x%x) buffers to write\n", __FUNCTION__, __LINE__, - bufs, bufs); - while (bufs >= 1) { - rc = write_flash_buffer8(info_p, sp, dp, FLASH_WRITE_BUF_SIZE); - if (rc != 0) { - PRINTF("%s:%d: ** Error writing buf %d\n", - __FUNCTION__, __LINE__, bufs); - return (rc); - } - bufs--; - sp += FLASH_WRITE_BUF_SIZE; - dp += FLASH_WRITE_BUF_SIZE; - } - - /* - * Do the leftovers - */ - i = count % FLASH_WRITE_BUF_SIZE; - PRINTF("%s:%d: %d (0x%x) leftover bytes\n", __FUNCTION__, __LINE__, i, i); - if (i > 0) { - rc = write_flash_buffer8(info_p, sp, dp, i); - } - - sp = (vu_char*)info_p->start[0]; - *sp = SCS_READ_CMD; - return (rc); - -#else - wp = addr; - while (count-- >= 1) { - if((rc = write_data8(info_p, wp++, *src_p++)) != 0) - return (rc); - } - return 0; -#endif -} - - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_data8 (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)dest; - vu_char status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = SCS_PROGRAM_CMD; - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((status = *addr) & SCS_SR7) != SCS_SR7) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *addr = SCS_READ_CMD; - return (1); - } - } - *addr = SCS_READ_CMD; - return (0); -} - -/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c deleted file mode 100644 index 37788d5..0000000 --- a/board/gen860t/fpga.c +++ /dev/null @@ -1,380 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* - * Virtex2 FPGA configuration support for the GEN860T computer - */ - -#include -#include -#include -#include "fpga.h" - -#if (CONFIG_FPGA) - -#if 0 -#define GEN860T_FPGA_DEBUG -#endif - -#ifdef GEN860T_FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * Port bit numbers for the Selectmap controls - */ -#define FPGA_INIT_BIT_NUM 22 /* PB22 */ -#define FPGA_RESET_BIT_NUM 11 /* PC11 */ -#define FPGA_DONE_BIT_NUM 16 /* PB16 */ -#define FPGA_PROGRAM_BIT_NUM 7 /* PA7 */ - -/* Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - */ -Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_init_fn, - fpga_err_fn, - fpga_done_fn, - fpga_clk_fn, - fpga_cs_fn, - fpga_wr_fn, - fpga_read_data_fn, - fpga_write_data_fn, - fpga_busy_fn, - fpga_abort_fn, - fpga_post_config_fn -}; - -Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - {Xilinx_Virtex2, - slave_selectmap, - XILINX_XC2V3000_SIZE, - (void *) &fpga_fns, - 0} -}; - -/* - * Display FPGA revision information - */ -void print_fpga_revision (void) -{ - vu_long *rev_p = (vu_long *) 0x60000008; - - printf ("FPGA Revision 0x%.8lx" - " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n", - *rev_p, - ((*rev_p >> 28) & 0xf), - ((*rev_p >> 20) & 0xff), - ((*rev_p >> 12) & 0xff), - ((*rev_p >> 8) & 0xf), (*rev_p & 0xff)); -} - - -/* - * Perform a simple test of the FPGA to processor interface using the FPGA's - * inverting bus test register. The great thing about doing a read/write - * test on a register that inverts it's contents is that you avoid any - * problems with bus charging. - * Return 0 on failure, 1 on success. - */ -int test_fpga_ibtr (void) -{ - vu_long *ibtr_p = (vu_long *) 0x60000010; - vu_long readback; - vu_long compare; - int i; - int j; - int k; - int pass = 1; - - static const ulong bitpattern[] = { - 0xdeadbeef, /* magic ID pattern for debug */ - 0x00000001, /* single bit */ - 0x00000003, /* two adjacent bits */ - 0x00000007, /* three adjacent bits */ - 0x0000000F, /* four adjacent bits */ - 0x00000005, /* two non-adjacent bits */ - 0x00000015, /* three non-adjacent bits */ - 0x00000055, /* four non-adjacent bits */ - 0xaaaaaaaa, /* alternating 1/0 */ - }; - - for (i = 0; i < 1024; i++) { - for (j = 0; j < 31; j++) { - for (k = 0; - k < sizeof (bitpattern) / sizeof (bitpattern[0]); - k++) { - *ibtr_p = compare = (bitpattern[k] << j); - readback = *ibtr_p; - if (readback != ~compare) { - printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback); - pass = 0; - break; - } - } - if (!pass) - break; - } - if (!pass) - break; - } - if (pass) { - printf ("FPGA inverting bus test passed\n"); - print_fpga_revision (); - } else { - printf ("** FPGA inverting bus test failed\n"); - } - return pass; -} - - -/* - * Set the active-low FPGA reset signal. - */ -void fpga_reset (int assert) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__); - if (assert) { - immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM); - PRINTF ("asserted\n"); - } else { - immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM); - PRINTF ("deasserted\n"); - } -} - - -/* - * Initialize the SelectMap interface. We assume that the mode and the - * initial state of all of the port pins have already been set! - */ -void fpga_selectmap_init (void) -{ - PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, - __LINE__); - fpga_pgm_fn (FALSE, FALSE, 0); /* make sure program pin is inactive */ -} - - -/* - * Initialize the fpga. Return 1 on success, 0 on failure. - */ -int gen860t_init_fpga (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int i; - - PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off); - fpga_init (gd->reloc_off); - fpga_selectmap_init (); - - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { - PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); - fpga_add (fpga_xilinx, &fpga[i]); - } - return 1; -} - - -/* - * Set the FPGA's active-low SelectMap program line to the specified level - */ -int fpga_pgm_fn (int assert, int flush, int cookie) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); - - if (assert) { - immap->im_ioport.iop_padat &= - ~(0x8000 >> FPGA_PROGRAM_BIT_NUM); - PRINTF ("asserted\n"); - } else { - immap->im_ioport.iop_padat |= - (0x8000 >> FPGA_PROGRAM_BIT_NUM); - PRINTF ("deasserted\n"); - } - return assert; -} - - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int fpga_init_fn (int cookie) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__); - if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) { - PRINTF ("high\n"); - return 0; - } else { - PRINTF ("low\n"); - return 1; - } -} - - -/* - * Test the state of the active-high FPGA DONE pin - */ -int fpga_done_fn (int cookie) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__); - if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) { - PRINTF ("high\n"); - return FPGA_SUCCESS; - } else { - PRINTF ("low\n"); - return FPGA_FAIL; - } -} - - -/* - * Read FPGA SelectMap data. - */ -int fpga_read_data_fn (unsigned char *data, int cookie) -{ - vu_char *p = (vu_char *) SELECTMAP_BASE; - - *data = *p; -#if 0 - PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data); -#endif - return (int) data; -} - - -/* - * Write data to the FPGA SelectMap port - */ -int fpga_write_data_fn (unsigned char data, int flush, int cookie) -{ - vu_char *p = (vu_char *) SELECTMAP_BASE; - -#if 0 - PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data); -#endif - *p = data; - return (int) data; -} - - -/* - * Abort and FPGA operation - */ -int fpga_abort_fn (int cookie) -{ - PRINTF ("%s:%d: FPGA program sequence aborted\n", - __FUNCTION__, __LINE__); - return FPGA_FAIL; -} - - -/* - * FPGA pre-configuration function. Just make sure that - * FPGA reset is asserted to keep the FPGA from starting up after - * configuration. - */ -int fpga_pre_config_fn (int cookie) -{ - PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - fpga_reset (TRUE); - return 0; -} - - -/* - * FPGA post configuration function. Blip the FPGA reset line and then see if - * the FPGA appears to be running. - */ -int fpga_post_config_fn (int cookie) -{ - int rc; - - PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); - fpga_reset (TRUE); - udelay (1000); - fpga_reset (FALSE); - udelay (1000); - - /* - * Use the FPGA,s inverting bus test register to do a simple test of the - * processor interface. - */ - rc = test_fpga_ibtr (); - return rc; -} - - -/* - * Clock, chip select and write signal assert functions and error check - * and busy functions. These are only stubs because the GEN860T selectmap - * interface handles sequencing of control signals automatically (it uses - * a memory-mapped interface to the FPGA SelectMap port). The design of - * the interface guarantees that the SelectMap port cannot be overrun so - * no busy check is needed. A configuration error is signalled by INIT - * going low during configuration, so there is no need for a separate error - * function. - */ -int fpga_clk_fn (int assert_clk, int flush, int cookie) -{ - return assert_clk; -} - -int fpga_cs_fn (int assert_cs, int flush, int cookie) -{ - return assert_cs; -} - -int fpga_wr_fn (int assert_write, int flush, int cookie) -{ - return assert_write; -} - -int fpga_err_fn (int cookie) -{ - return 0; -} - -int fpga_busy_fn (int cookie) -{ - return 0; -} -#endif - -/* vim: set ts=4 tw=78 sw=4: */ diff --git a/board/gen860t/fpga.h b/board/gen860t/fpga.h deleted file mode 100644 index 01967a4..0000000 --- a/board/gen860t/fpga.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* - * Virtex2 FPGA configuration support for the GEN860T computer - */ - -extern int gen860t_init_fpga(void); -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_err_fn(int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_cs_fn(int assert_cs, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_read_data_fn(unsigned char *data, int cookie); -extern int fpga_write_data_fn(unsigned char data, int flush, int cookie); -extern int fpga_busy_fn(int cookie); -extern int fpga_abort_fn(int cookie ); -extern int fpga_pre_config_fn(int cookie ); -extern int fpga_post_config_fn(int cookie ); - -/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c deleted file mode 100644 index b7a1b56..0000000 --- a/board/gen860t/gen860t.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include "beeper.h" -#include "fpga.h" -#include "ioport.h" - -#ifdef CONFIG_STATUS_LED -#include -#endif - -#if defined(CFG_CMD_MII) && defined(CONFIG_MII) -#include -#endif - -#if 0 -#define GEN860T_DEBUG -#endif - -#ifdef GEN860T_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * The following UPM init tables were generated automatically by - * Motorola's MCUINIT program. See the README file for UPM to - * SDRAM pin assignments if you want to type this data into - * MCUINIT in order to reverse engineer the waveforms. - */ - -/* - * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices - * (UPMA) and Virtex FPGA SelectMap interface (UPMB). - * NOTE that unused areas of the table are used to hold NOP, precharge - * and mode register set sequences. - * - */ -#define UPMA_NOP_ADDR 0x5 -#define UPMA_PRECHARGE_ADDR 0x6 -#define UPMA_MRS_ADDR 0x12 - -#define UPM_SINGLE_READ_ADDR 0x00 -#define UPM_BURST_READ_ADDR 0x08 -#define UPM_SINGLE_WRITE_ADDR 0x18 -#define UPM_BURST_WRITE_ADDR 0x20 -#define UPM_REFRESH_ADDR 0x30 - -const uint sdram_upm_table[] = { - /* single read (offset 0x00 in upm ram) */ - 0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05, - 0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff, - /* burst read (offset 0x08 in upm ram) */ - 0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00, - 0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff, - 0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4, - 0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff, - /* single write (offset 0x18 in upm ram) */ - 0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst write (offset 0x20 in upm ram) */ - 0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00, - 0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* refresh (offset 0x30 in upm ram) */ - 0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84, - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* exception (offset 0x3C in upm ram) */ -}; - -const uint selectmap_upm_table[] = { - /* single read (offset 0x00 in upm ram) */ - 0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00, - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst read (offset 0x08 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* single write (offset 0x18 in upm ram) */ - 0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* burst write (offset 0x20 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* refresh (offset 0x30 in upm ram) */ - 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - /* exception (offset 0x3C in upm ram) */ - 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff -}; - -/* - * Check board identity. Always successful (gives information only) - */ -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - char *s; - char buf[64]; - int i; - - i = getenv_r ("board_id", buf, sizeof (buf)); - s = (i > 0) ? buf : NULL; - - if (s) { - printf ("%s ", s); - } else { - printf (" "); - } - - i = getenv_r ("serial#", buf, sizeof (buf)); - s = (i > 0) ? buf : NULL; - - if (s) { - printf ("S/N %s\n", s); - } else { - printf ("S/N \n"); - } - - printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk)); - printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk)); - return (0); -} - -/* - * Initialize SDRAM - */ -long int initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - upmconfig (UPMA, - (uint *) sdram_upm_table, - sizeof (sdram_upm_table) / sizeof (uint) - ); - - /* - * Setup MAMR register - */ - memctl->memc_mptpr = CFG_MPTPR_1BK_8K; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - /* - * Map CS1* to SDRAM bank - */ - memctl->memc_or1 = CFG_OR1; - memctl->memc_br1 = CFG_BR1; - - /* - * Perform SDRAM initialization sequence: - * 1. Apply at least one NOP command - * 2. 100 uS delay (JEDEC standard says 200 uS) - * 3. Issue 4 precharge commands - * 4. Perform two refresh cycles - * 5. Program mode register - * - * Program SDRAM for standard operation, sequential burst, burst length - * of 4, CAS latency of 2. - */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (0) | UPMA_NOP_ADDR; - udelay (200); - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (4) | UPMA_PRECHARGE_ADDR; - - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (2) | UPM_REFRESH_ADDR; - - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (1) | UPMA_MRS_ADDR; - - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF (0) | UPMA_NOP_ADDR; - /* - * Enable refresh - */ - memctl->memc_mamr |= MAMR_PTAE; - - return (SDRAM_SIZE); -} - -/* - * Disk On Chip (DOC) Millenium initialization. - * The DOC lives in the CS2* space - */ -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -extern void doc_probe (ulong physadr); - -void doc_init (void) -{ - printf ("Probing at 0x%.8x: ", DOC_BASE); - doc_probe (DOC_BASE); -} -#endif - -/* - * Miscellaneous intialization - */ -int misc_init_r (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - /* - * Set up UPMB to handle the Virtex FPGA SelectMap interface - */ - upmconfig (UPMB, (uint *) selectmap_upm_table, - sizeof (selectmap_upm_table) / sizeof (uint)); - - memctl->memc_mbmr = 0x0; - - config_mpc8xx_ioports (immr); - -#if (CONFIG_COMMANDS & CFG_CMD_MII) - mii_init (); -#endif - -#if (CONFIG_FPGA) - gen860t_init_fpga (); -#endif - return 0; -} - -/* - * Final init hook before entering command loop. - */ -int last_stage_init (void) -{ -#if !defined(CONFIG_SC) - char buf[256]; - int i; - - /* - * Turn the beeper volume all the way down in case this is a warm boot. - */ - set_beeper_volume (-64); - init_beeper (); - - /* - * Read the environment to see what to do with the beeper - */ - i = getenv_r ("beeper", buf, sizeof (buf)); - if (i > 0) { - do_beeper (buf); - } -#endif - return 0; -} - -/* - * Stub to make POST code happy. Can't self-poweroff, so just hang. - */ -void board_poweroff (void) -{ - puts ("### Please power off the board ###\n"); - while (1); -} - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed (void) -{ - return 0; /* No hotkeys supported */ -} -#endif - -/* vim: set ts=4 sw=4 tw=78 : */ diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c deleted file mode 100644 index 1fc9545..0000000 --- a/board/gen860t/ioport.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "ioport.h" - -#if 0 -#define IOPORT_DEBUG -#endif - -#ifdef IOPORT_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* - * The ioport configuration table. - */ -const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { - /* - * Port A configuration - * Pin Signal Type Active Initial state - * PA7 fpgaProgramLowOut Out Low High - * PA1 fpgaCoreVoltageFailLow In Low N/A - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ - /* PA15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA9 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 1*/ - /* PA8 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 1*/ - /* PA7 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaProgramLow */ - /* PA6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA5 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 0*/ - /* PA4 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 0*/ - /* PA3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PA2 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PA1 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaCoreVoltageFail*/ -#else - /* PA1 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PA0 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - }, - - /* - * Port B configuration - * Pin Signal Type Active Initial state - * PB14 docBusyLowIn In Low X - * PB15 gpio1Sig Out High Low - * PB16 fpgaDoneBi In High X - * PB17 swBitOkLowOut Out Low High - * PB19 speakerVolSig Out/Hi-Z High/Low High (Hi-Z) - * PB22 fpgaInitLowBi In Low X - * PB23 batteryOkSig In High X - * PB31 pulseCatcherClr Out High 0 - */ - { /* conf ppar psor pdir podr pdat pint function */ -#if !defined(CONFIG_SC) - /* PB31 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#else - /* PB31 */ { 1, 0, 0, 1, 0, 0, 0 }, /* pulseCatcherClr */ -#endif - /* PB30 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB29 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB28 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB27 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB26 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB25 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB24 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PB23 */ { 1, 0, 0, 0, 0, 0, 0 }, /* batteryOk */ -#else - /* PB23 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PB22 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaInitLowBi */ - /* PB21 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB20 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PB19 */ { 1, 0, 0, 1, 1, 1, 0 }, /* speakerVol */ -#else - /* PB19 */ { 0, 0, 0, 1, 1, 1, 0 }, /* */ -#endif - /* PB18 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PB17 */ { 1, 0, 0, 1, 0, 1, 0 }, /* swBitOkLow */ - /* PB16 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaDone */ - /* PB15 */ { 1, 0, 0, 1, 0, 0, 0 }, /* gpio1 */ -#if !defined(CONFIG_SC) - /* PB14 */ { 1, 0, 0, 0, 0, 0, 0 } /* docBusyLow */ -#else - /* PB14 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ -#endif - }, - - /* - * Port C configuration - * Pin Signal Type Active Initial state - * PC4 i2cBus1EnSig Out High High - * PC5 i2cBus2EnSig Out High High - * PC6 gpio0Sig Out High Low - * PC8 i2cBus3EnSig Out High High - * PC10 i2cBus4EnSig Out High High - * PC11 fpgaResetLowOut Out Low High - * PC12 systemBitOkIn In High X - * PC15 selfDreqLow In Low X - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC15 */ { 1, 0, 0, 0, 0, 0, 0 }, /* selfDreqLowIn */ - /* PC14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PC12 */ { 1, 0, 0, 0, 0, 0, 0 }, /* systemBitOkIn */ -#else - /* PC12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#endif - /* PC11 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaResetLowOut */ -#if !defined(CONFIG_SC) - /* PC10 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus4EnSig */ -#else - /* PC10 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* PC9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ -#if !defined(CONFIG_SC) - /* PC8 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus3EnSig */ -#else - /* PC8 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* PC7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PC6 */ { 1, 0, 0, 1, 0, 1, 0 }, /* gpio0 */ -#if !defined(CONFIG_SC) - /* PC5 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus2EnSig */ - /* PC4 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus1EnSig */ -#else - /* PC5 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ - /* PC4 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */ -#endif - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - }, - - /* - * Port D configuration - */ - { /* conf ppar psor pdir podr pdat pint function */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD8 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD5 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD4 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* PD3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ - /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */ - } -}; - -/* - * Configure the MPC8XX I/O ports per the ioport configuration table - * (taken from ./cpu/mpc8260/cpu_init.c) - */ -void config_mpc8xx_ioports (volatile immap_t * immr) -{ - int portnum; - - for (portnum = 0; portnum < NUM_PORTS; portnum++) { - uint pmsk = 0, ppar = 0, psor = 0, pdir = 0; - uint podr = 0, pdat = 0, pint = 0; - uint msk = 1; - mpc8xx_iop_conf_t *iopc = - (mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0]; - mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS; - - /* - * For all ports except port B, ignore the two don't care entries - * in the configuration tables. - */ - if (portnum != 1) { - iopc = (mpc8xx_iop_conf_t *) & - iop_conf_tab[portnum][2]; - } - - /* - * NOTE: index 0 refers to pin 17, index 17 refers to pin 0 - */ - while (iopc < eiopc) { - if (iopc->conf) { - pmsk |= msk; - if (iopc->ppar) - ppar |= msk; - if (iopc->psor) - psor |= msk; - if (iopc->pdir) - pdir |= msk; - if (iopc->podr) - podr |= msk; - if (iopc->pdat) - pdat |= msk; - if (iopc->pint) - pint |= msk; - } - msk <<= 1; - iopc++; - } - - PRINTF ("%s:%d:\n portnum=%d ", __FUNCTION__, __LINE__, - portnum); -#ifdef IOPORT_DEBUG - switch (portnum) { - case 0: - printf ("(A)\n"); - break; - case 1: - printf ("(B)\n"); - break; - case 2: - printf ("(C)\n"); - break; - case 3: - printf ("(D)\n"); - break; - default: - printf ("(?)\n"); - break; - } -#endif - PRINTF (" ppar=0x%.8x pdir=0x%.8x podr=0x%.8x\n" - " pdat=0x%.8x psor=0x%.8x pint=0x%.8x pmsk=0x%.8x\n", - ppar, pdir, podr, pdat, psor, pint, pmsk); - - /* - * Have to handle the ioports on a port-by-port basis since there - * are three different flavors. - */ - if (pmsk != 0) { - uint tpmsk = ~pmsk; - - if (0 == portnum) { /* port A */ - immr->im_ioport.iop_papar &= tpmsk; - immr->im_ioport.iop_padat = - (immr->im_ioport. - iop_padat & tpmsk) | pdat; - immr->im_ioport.iop_padir = - (immr->im_ioport. - iop_padir & tpmsk) | pdir; - immr->im_ioport.iop_paodr = - (immr->im_ioport. - iop_paodr & tpmsk) | podr; - immr->im_ioport.iop_papar |= ppar; - } else if (1 == portnum) { /* port B */ - immr->im_cpm.cp_pbpar &= tpmsk; - immr->im_cpm.cp_pbdat = - (immr->im_cpm. - cp_pbdat & tpmsk) | pdat; - immr->im_cpm.cp_pbdir = - (immr->im_cpm. - cp_pbdir & tpmsk) | pdir; - immr->im_cpm.cp_pbodr = - (immr->im_cpm. - cp_pbodr & tpmsk) | podr; - immr->im_cpm.cp_pbpar |= ppar; - } else if (2 == portnum) { /* port C */ - immr->im_ioport.iop_pcpar &= tpmsk; - immr->im_ioport.iop_pcdat = - (immr->im_ioport. - iop_pcdat & tpmsk) | pdat; - immr->im_ioport.iop_pcdir = - (immr->im_ioport. - iop_pcdir & tpmsk) | pdir; - immr->im_ioport.iop_pcint = - (immr->im_ioport. - iop_pcint & tpmsk) | pint; - immr->im_ioport.iop_pcso = - (immr->im_ioport. - iop_pcso & tpmsk) | psor; - immr->im_ioport.iop_pcpar |= ppar; - } else if (3 == portnum) { /* port D */ - immr->im_ioport.iop_pdpar &= tpmsk; - immr->im_ioport.iop_pddat = - (immr->im_ioport. - iop_pddat & tpmsk) | pdat; - immr->im_ioport.iop_pddir = - (immr->im_ioport. - iop_pddir & tpmsk) | pdir; - immr->im_ioport.iop_pdpar |= ppar; - } - } - } - - PRINTF ("%s:%d: Port A:\n papar=0x%.4x padir=0x%.4x" - " paodr=0x%.4x\n padat=0x%.4x\n", __FUNCTION__, __LINE__, - immr->im_ioport.iop_papar, immr->im_ioport.iop_padir, - immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat); - PRINTF ("%s:%d: Port B:\n pbpar=0x%.8x pbdir=0x%.8x" - " pbodr=0x%.8x\n pbdat=0x%.8x\n", __FUNCTION__, __LINE__, - immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir, - immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat); - PRINTF ("%s:%d: Port C:\n pcpar=0x%.4x pcdir=0x%.4x" - " pcdat=0x%.4x\n pcso=0x%.4x pcint=0x%.4x\n ", - __FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar, - immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat, - immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint); - PRINTF ("%s:%d: Port D:\n pdpar=0x%.4x pddir=0x%.4x" - " pddat=0x%.4x\n", __FUNCTION__, __LINE__, - immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir, - immr->im_ioport.iop_pddat); -} diff --git a/board/gen860t/ioport.h b/board/gen860t/ioport.h deleted file mode 100644 index 34a2d7b..0000000 --- a/board/gen860t/ioport.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define NUM_PORTS 4 -#define PORT_BITS 18 - -/* - * This structure provides configuration information for one port pin. - * We include all fields needed to initialize any of the ioports. - */ -typedef struct { - unsigned char conf:1; /* If 1, configure this port */ - unsigned char ppar:1; /* Port Pin Assignment Register */ - unsigned char psor:1; /* Port Special Options Register */ - unsigned char pdir:1; /* Port Data Direction Register */ - unsigned char podr:1; /* Port Open Drain Register */ - unsigned char pdat:1; /* Port Data Register */ - unsigned char pint:1; /* Port Interrupt Register */ -} mpc8xx_iop_conf_t; - -extern void config_mpc8xx_ioports(volatile immap_t *immr); - -/* vim: set ts=4 tw=78 sw=4: */ diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds deleted file mode 100644 index 7926a2e..0000000 --- a/board/gen860t/u-boot-flashenv.lds +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Linker command file for the GEN860T board when the environment is - * stored in flash memory. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -SECTIONS -{ - /* - * Read-only sections, merged into text segment: - */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* - * Read-write section, merged into data segment: - */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data: - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); - - .ppcenv: - { - . = env_offset; - common/environment.o - } -} diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds deleted file mode 100644 index 1df4817..0000000 --- a/board/gen860t/u-boot.lds +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Linker command file for the GEN860T board. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -SECTIONS -{ - /* - * Read-only sections, merged into text segment: - */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* - * Read-write section, merged into data segment: - */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/genietv/Makefile b/board/genietv/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/genietv/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/genietv/config.mk b/board/genietv/config.mk deleted file mode 100644 index 69ab21f..0000000 --- a/board/genietv/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x00000000 -OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data diff --git a/board/genietv/flash.c b/board/genietv/flash.c deleted file mode 100644 index 1c1728b..0000000 --- a/board/genietv/flash.c +++ /dev/null @@ -1,469 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Detect size */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - /* Setup offsets */ - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - size_b1 = 0 ; - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - * Fix this to support variable sector sizes -*/ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - /* set sector offsets for bottom boot block type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) - { - puts ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) - { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >> 20) { - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - } else { - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); - } - - puts (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) - { - if ((i % 5) == 0) - { - puts ("\n "); - } - - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - putc ('\n'); - return; -} -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - volatile unsigned char *caddr; - char value; - - caddr = (volatile unsigned char *)addr ; - - /* Write auto select command: read Manufacturer ID */ - -#if 0 - printf("Base address is: %08x\n", caddr); -#endif - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - value = caddr[0]; - -#if 0 - printf("Manufact ID: %02x\n", value); -#endif - switch (value) - { - case 0x1: /* AMD_MANUFACT */ - info->flash_id = FLASH_MAN_AMD; - break; - - case 0x4: /* FUJ_MANUFACT */ - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = caddr[1]; /* device ID */ -#if 0 - printf("Device ID: %02x\n", value); -#endif - switch (value) - { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets ((ulong)addr, &flash_info[0]); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) - { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) - { - caddr = (volatile unsigned char *)info->start[0]; - *caddr = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile unsigned char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - - while ((addr[0] & 0xFF) != 0xFF) - { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - - addr[0] = 0xF0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]), - *cdest,*cdata; - ulong start; - int flag, count = 4 ; - - cdest = (volatile unsigned char *)dest ; - cdata = (volatile unsigned char *)&data ; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - while(count--) - { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *cdest = *cdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*cdest ^ *cdata) & 0x80) - { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - cdata++ ; - cdest++ ; - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/genietv/genietv.c b/board/genietv/genietv.c deleted file mode 100644 index 5f8c899..0000000 --- a/board/genietv/genietv.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * genietv/genietv.c - * - * The GENIETV is using the following physical memorymap (copied from - * the FADS configuration): - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM - * ff000000 -> ff00ffff : IMAP internal in the cpu - * 02800000 -> 0287ffff : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram setup by U-Boot - * - * CS pins are connected as follows: - * - * CS0 -512Kb boot flash - * CS1 - SDRAM #1 - * CS2 - SDRAM #2 - * CS3 - Flash #1 - * CS4 - Flash #2 - * CS5 - LON (if present) - * CS6 - PCMCIA #1 - * CS7 - PCMCIA #2 - * - * Ports are configured as follows: - * - * PA7 - SDRAM banks enable - */ - -#include -#include - -#define CFG_PA7 0x0100 - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBEEC00, - 0x1FFDDC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMB RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMB RAM) - */ - 0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFAC00, 0x10AF5C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMB RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMB RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity - */ - -int checkboard (void) -{ - puts ("Board: GenieTV\n"); - return 0; -} - -#if 0 -static void PrintState (void) -{ - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &im->im_memctl; - - printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0, - memctl->memc_or0); - printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1, - memctl->memc_or1); - printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2, - memctl->memc_or2); -} -#endif - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &im->im_memctl; - long int size_b0, size_b1, size8; - - /* Enable SDRAM */ - - /* Configuring PA7 for general purpouse output pin */ - im->im_ioport.iop_papar &= ~CFG_PA7; /* 0 = general purpouse */ - im->im_ioport.iop_padir |= CFG_PA7; /* 1 = output */ - - /* Enable SDRAM - PA7 = 1 */ - im->im_ioport.iop_padat |= CFG_PA7; /* value of PA7 */ - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - - memctl->memc_mbmr = CFG_MBMR_8COL; - - upmconfig (UPMB, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - - memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = - ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); - - memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); - - /* perform SDRAM initialization sequence */ - memctl->memc_mar = 0x00000088; - - memctl->memc_mcr = 0x80802105; /* SDRAM bank 0 */ - - memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */ - - /* Execute refresh 8 times */ - memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X; - - memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */ - - memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */ - - /* Execute refresh 4 times */ - memctl->memc_mbmr = CFG_MBMR_8COL; - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - -#if 0 - PrintState (); -#endif -/* printf ("\nChecking bank1..."); */ - size8 = dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - size_b0 = size8; - -/* printf ("\nChecking bank2..."); */ - size_b1 = - dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - /* - * Final mapping: map bigger bank first - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) + - (size_b0 & BR_BA_MSK); - } else { - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - /* adjust refresh rate depending on SDRAM type, one bank */ - memctl->memc_mptpr = CFG_MPTPR_1BK_4K; - } - - /* If no memory detected, disable SDRAM */ - if ((size_b0 + size_b1) == 0) { - printf ("disabling SDRAM!\n"); - /* Disable SDRAM - PA7 = 1 */ - im->im_ioport.iop_padat &= ~CFG_PA7; /* value of PA7 */ - } -/* else */ -/* printf("done! (%08lx)\n", size_b0 + size_b1); */ - -#if 0 - PrintState (); -#endif - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mbmr_value, long int *base, - long int maxsize) -{ - long size; - - /*memctl->memc_mbmr = mbmr_value; */ - - size = get_ram_size (base, maxsize); - - if (size) { -/* printf("(%08lx)", size); */ - } else { - printf ("(0)"); - } - - return (size); -} - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) - -#ifdef CFG_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char *) CFG_PCMCIA_MEM_ADDR; -#endif - -int pcmcia_init (void) -{ - volatile pcmconf8xx_t *pcmp; - uint v, slota, slotb; - - /* - ** Enable the PCMCIA for a Flash card. - */ - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia)); - -#if 0 - pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR; - pcmp->pcmc_por0 = 0xc00ff05d; -#endif - - /* Set all slots to zero by default. */ - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; -#ifdef PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0x40; -#endif -#ifdef PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0x40; -#endif - - /* Check if any PCMCIA card is luged in. */ - slota = (pcmp->pcmc_pipr & 0x18000000) == 0; - slotb = (pcmp->pcmc_pipr & 0x00001800) == 0; - - if (!(slota || slotb)) { - printf ("No card present\n"); -#ifdef PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0; -#endif -#ifdef PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0; -#endif - return -1; - } else - printf ("Unknown card ("); - - v = 0; - - switch ((pcmp->pcmc_pipr >> 14) & 3) { - case 0x00: - printf ("5V"); - v = 5; - break; - case 0x01: - printf ("5V and 3V"); - v = 3; - break; - case 0x03: - printf ("5V, 3V and x.xV"); - v = 3; - break; - } - - switch (v) { - case 3: - printf ("; using 3V"); - /* Enable 3 volt Vcc. */ - - break; - - default: - printf ("; unknown voltage"); - return -1; - } - printf (")\n"); - /* disable pcmcia reset after a while */ - - udelay (20); - - pcmp->pcmc_pgcrb = 0; - - /* If you using a real hd you should give a short - * spin-up time. */ -#ifdef CONFIG_DISK_SPINUP_TIME - udelay (CONFIG_DISK_SPINUP_TIME); -#endif - - return 0; -} -#endif /* CFG_CMD_PCMCIA */ diff --git a/board/genietv/genietv.h b/board/genietv/genietv.h deleted file mode 100644 index 7c95b56..0000000 --- a/board/genietv/genietv.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * The GENIETV is using the following physical memorymap (copied from - * the FADS configuration): - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM - * ff000000 -> ff00ffff : IMAP internal in the cpu - * 02800000 -> 0287ffff : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram setup by U-Boot - * - * CS pins are connected as follows: - * - * CS0 -512Kb boot flash - * CS1 - SDRAM #1 - * CS2 - SDRAM #2 - * CS3 - Flash #1 - * CS4 - Flash #2 - * CS5 - LON (if present) - * CS6 - PCMCIA #1 - * CS7 - PCMCIA #2 - * - * Ports are configured as follows: - * - * PA7 - SDRAM banks enable - */ diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds deleted file mode 100644 index f48b9ad..0000000 --- a/board/genietv/u-boot.lds +++ /dev/null @@ -1,145 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/environment.o (.ppcenv) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug deleted file mode 100644 index e843df6..0000000 --- a/board/genietv/u-boot.lds.debug +++ /dev/null @@ -1,143 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/environment.o (.ppcenv) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/gth/Makefile b/board/gth/Makefile deleted file mode 100644 index e14c12e..0000000 --- a/board/gth/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ee_access.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/gth/README b/board/gth/README deleted file mode 100644 index 241c70b..0000000 --- a/board/gth/README +++ /dev/null @@ -1,18 +0,0 @@ -Written by Thomas.Lange@corelatus.com 010805 - -To make a system for gth that actually works ;-) -the variable TBASE needs to be set to 0,1 or 2 -depending on location where image is supposed to -be started from. -E.g. make TBASE=1 - -0: Start from RAM, base 0 - -1: Start from flash_base + 0x10070 - -2: Start from flash_base + 0x30070 - -When using 1 or 2, the image is supposed to be launched -from miniboot that boots the first U-Boot image found in -flash. -For miniboot code, description, see www.opensource.se diff --git a/board/gth/config.mk b/board/gth/config.mk deleted file mode 100644 index 3c80156..0000000 --- a/board/gth/config.mk +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -ifeq ($(TBASE),0) -TEXT_BASE = 0 -else -ifeq ($(TBASE),1) -TEXT_BASE = 0x80010070 -else -ifeq ($(TBASE),2) -TEXT_BASE = 0x80030070 -else -## Only to make ordinary make work -TEXT_BASE = 0x90000000 -endif -endif -endif - -OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data diff --git a/board/gth/ee_access.c b/board/gth/ee_access.c deleted file mode 100644 index 716c90e..0000000 --- a/board/gth/ee_access.c +++ /dev/null @@ -1,335 +0,0 @@ -/* Module for handling DALLAS DS2438, smart battery monitor - Chip can store up to 40 bytes of user data in EEPROM, - perform temp, voltage and current measurements. - Chip also contains a unique serial number. - - Always read/write LSb first - - For documentaion, see data sheet for DS2438, 2438.pdf - - By Thomas.Lange@corelatus.com 001025 */ - -#include -#include -#include - -#include <../board/gth/ee_dev.h> - -/* We dont have kernel functions */ -#define printk printf -#define KERN_DEBUG -#define KERN_ERR -#define EIO 1 - -static int Debug = 0; - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -/* - * lookup table ripped from DS app note 17, understanding and using - * cyclic redundancy checks... - */ - -static u8 crc_lookup[256] = { - 0, 94, 188, 226, 97, 63, 221, 131, - 194, 156, 126, 32, 163, 253, 31, 65, - 157, 195, 33, 127, 252, 162, 64, 30, - 95, 1, 227, 189, 62, 96, 130, 220, - 35, 125, 159, 193, 66, 28, 254, 160, - 225, 191, 93, 3, 128, 222, 60, 98, - 190, 224, 2, 92, 223, 129, 99, 61, - 124, 34, 192, 158, 29, 67, 161, 255, - 70, 24, 250, 164, 39, 121, 155, 197, - 132, 218, 56, 102, 229, 187, 89, 7, - 219, 133, 103, 57, 186, 228, 6, 88, - 25, 71, 165, 251, 120, 38, 196, 154, - 101, 59, 217, 135, 4, 90, 184, 230, - 167, 249, 27, 69, 198, 152, 122, 36, - 248, 166, 68, 26, 153, 199, 37, 123, - 58, 100, 134, 216, 91, 5, 231, 185, - 140, 210, 48, 110, 237, 179, 81, 15, - 78, 16, 242, 172, 47, 113, 147, 205, - 17, 79, 173, 243, 112, 46, 204, 146, - 211, 141, 111, 49, 178, 236, 14, 80, - 175, 241, 19, 77, 206, 144, 114, 44, - 109, 51, 209, 143, 12, 82, 176, 238, - 50, 108, 142, 208, 83, 13, 239, 177, - 240, 174, 76, 18, 145, 207, 45, 115, - 202, 148, 118, 40, 171, 245, 23, 73, - 8, 86, 180, 234, 105, 55, 213, 139, - 87, 9, 235, 181, 54, 104, 138, 212, - 149, 203, 41, 119, 244, 170, 72, 22, - 233, 183, 85, 11, 136, 214, 52, 106, - 43, 117, 151, 201, 74, 20, 246, 168, - 116, 42, 200, 150, 21, 75, 169, 247, - 182, 232, 10, 84, 215, 137, 107, 53 -}; - -static u8 make_new_crc( u8 Old_crc, u8 New_value ){ - /* Compute a new checksum with new byte, using previous checksum as input - See DS app note 17, understanding and using cyclic redundancy checks... - Also see DS2438, page 11 */ - return( crc_lookup[Old_crc ^ New_value ]); -} - -int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){ - /* Check if the checksum for this buffer is correct */ - u8 Curr_crc=0; - int i; - u8 *Curr_byte = Buffer; - - for(i=0;i>=1; - } -} - -int ee_do_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){ - /* Execute this command string, including - giving reset and setting to idle after command - if Rx_len is set, we read out data from EEPROM */ - int i; - - E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len ); - - if(do_reset()){ - /* Failed! */ - return(-EIO); - } - - if(Send_skip) - /* Always send SKIP_ROM first to tell chip we are sending a command, - except when we read out rom data for chip */ - write_byte(SKIP_ROM); - - /* Always have Tx data */ - for(i=0;iim_ioport.iop_padat &= ~PA_FRONT_LED; - else - immap->im_ioport.iop_padat |= PA_FRONT_LED; - udelay(1); - } - - /* Set port to open drain to be able to read data from - port without setting it to input */ - PORT_B_PAR &= ~PB_EEPROM; - PORT_B_ODR |= PB_EEPROM; - SET_PORT_B_OUTPUT(PB_EEPROM); - - /* Set idle mode */ - set_idle(); - - /* Copy all User EEPROM data to scratchpad */ - for(i=0;iim_cpm.cp_pbpar -#define PORT_B_ODR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbodr -#define PORT_B_DIR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdir -#define PORT_B_DAT ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat - -#define SET_PORT_B_INPUT(Mask) PORT_B_DIR &= ~(Mask) -#define SET_PORT_B_OUTPUT(Mask) PORT_B_DIR |= Mask - -#define WRITE_PORT_B(Mask,Value) { \ - if (Value) PORT_B_DAT |= Mask; \ - else PORT_B_DAT &= ~(Mask); \ - } -#define WRITE_PORT(Value) WRITE_PORT_B(PB_EEPROM,Value) - -#define READ_PORT (PORT_B_DAT&PB_EEPROM) - -/* 64 bytes chip */ -#define EE_CHIP_SIZE 64 - -/* We use this resistor for measuring the current drain on 3.3V */ -#define CURRENT_RESISTOR 0.022 - -/* microsecs - Pull line down at least this long for reset pulse */ -#define RESET_LOW_TIME 490 - -/* Read presence pulse after we release reset pulse */ -#define PRESENCE_TIMEOUT 100 -#define PRESENCE_LOW_TIME 200 - -#define WRITE_0_LOW 80 -#define WRITE_1_LOW 2 -#define TOTAL_WRITE_LOW 80 - -#define READ_LOW 2 -#define READ_TIMEOUT 10 -#define TOTAL_READ_LOW 80 - -/*** Rom function commands ***/ -#define READ_ROM 0x33 -#define MATCH_ROM 0x55 -#define SKIP_ROM 0xCC -#define SEARCH_ROM 0xF0 - - -/*** Memory_command_function ***/ -#define WRITE_SCRATCHPAD 0x4E -#define READ_SCRATCHPAD 0xBE -#define COPY_SCRATCHPAD 0x48 -#define RECALL_MEMORY 0xB8 -#define CONVERT_TEMP 0x44 -#define CONVERT_VOLTAGE 0xB4 - -/* Chip is divided in 8 pages, 8 bytes each */ - -#define EE_PAGE_SIZE 8 - -/* All chip data we want are in page 0 */ - -/* Bytes in page 0 */ -#define EE_P0_STATUS 0 -#define EE_P0_TEMP_LSB 1 -#define EE_P0_TEMP_MSB 2 -#define EE_P0_VOLT_LSB 3 -#define EE_P0_VOLT_MSB 4 -#define EE_P0_CURRENT_LSB 5 -#define EE_P0_CURRENT_MSB 6 - - -/* 40 byte user data is located at page 3-7 */ -#define EE_USER_PAGE_0 3 -#define USER_PAGES 5 - -#endif /* INCeedevh */ diff --git a/board/gth/flash.c b/board/gth/flash.c deleted file mode 100644 index 41a5c50..0000000 --- a/board/gth/flash.c +++ /dev/null @@ -1,649 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /*printf("faking");*/ - - return(0x1fffff); - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) - { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) - { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - -#if 0 - if (FLASH_BASE1_PRELIM != 0x0) { - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20,size_b0, size_b0<<20); - - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - } else { -#endif - size_b1 = 0; - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR0_PRELIM; - memctl->memc_br0 = CFG_BR0_PRELIM; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - if (size_b1) - { - /* memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; */ - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - } - else - { -/* memctl->memc_or1 = CFG_OR1_PRELIM; - FIXME memctl->memc_br1 = CFG_BR1_PRELIM; */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - - -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start adress table */ - if (info->flash_id & FLASH_BTYPE) - { - /* set sector offsets for bottom boot block type */ - for (i = 0; i < info->sector_count; i++) - { - info->start[i] = base + (i * 0x00040000); - } - } - else - { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - for (; i >= 0; i--) - { - info->start[i] = base + i * 0x00040000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - -#if 0 - case FLASH_AM040B: - printf ("AM29F040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM040T: - printf ("AM29F040T (4 Mbit, top boot sect)\n"); - break; -#endif - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) - { - if ((i % 5) == 0) - { - printf ("\n "); - } - - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; -#if 0 - ulong base = (ulong)addr; -#endif - ulong value; - - /* Write auto select command: read Manufacturer ID */ -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; -#endif - - value = addr[0]; - - switch (value) - { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = addr[1]; /* device ID */ - - switch (value) - { -#if 0 - case AMD_ID_F040B: - info->flash_id += FLASH_AM040B; - info->sector_count = 8; - info->size = 0x00200000; - break; /* => 2 MB */ -#endif - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - -#if 0 - /* set up sector start adress table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - flash_get_offsets ((ulong)addr, &flash_info[0]); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) - { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) - { - addr = (volatile unsigned long *)info->start[0]; -#if 0 - *addr = 0x00F000F0; /* reset bank */ -#else - *addr = 0xF0F0F0F0; /* reset bank */ -#endif - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; -#endif - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); -#if 0 - addr[0] = 0x00300030; -#else - addr[0] = 0x30303030; -#endif - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); -#if 0 - while ((addr[0] & 0x00800080) != 0x00800080) -#else - while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) -#endif - { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#if 0 - addr[0] = 0x00F000F0; /* reset bank */ -#else - addr[0] = 0xF0F0F0F0; /* reset bank */ -#endif - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; -#endif - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); -#if 0 - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) -#else - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) -#endif - { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/gth/gth.c b/board/gth/gth.c deleted file mode 100644 index b1fcbf5..0000000 --- a/board/gth/gth.c +++ /dev/null @@ -1,595 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Adapted from FADS and other board config files to GTH by thomas@corelatus.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include "ee_access.h" -#include "ee_dev.h" - -#ifdef CONFIG_BDM -#undef printf -#define printf(a,...) /* nothing */ -#endif - - -int checkboard (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - int Id = 0; - int Rev = 0; - u32 Pbdat; - - puts ("Board: "); - - /* Turn on leds and setup for reading rev and id */ - -#define PB_OUTS (PB_BLUE_LED|PB_ID_GND) -#define PB_INS (PB_ID_0|PB_ID_1|PB_ID_2|PB_ID_3|PB_REV_1|PB_REV_0) - - immap->im_cpm.cp_pbpar &= ~(PB_OUTS | PB_INS); - - immap->im_cpm.cp_pbdir &= ~PB_INS; - - immap->im_cpm.cp_pbdir |= PB_OUTS; - immap->im_cpm.cp_pbodr |= PB_OUTS; - immap->im_cpm.cp_pbdat &= ~PB_OUTS; - - /* Hold 100 Mbit in reset until fpga is loaded */ - immap->im_ioport.iop_pcpar &= ~PC_ENET100_RESET; - immap->im_ioport.iop_pcdir |= PC_ENET100_RESET; - immap->im_ioport.iop_pcso &= ~PC_ENET100_RESET; - immap->im_ioport.iop_pcdat &= ~PC_ENET100_RESET; - - /* Turn on front led to show that we are alive */ - immap->im_ioport.iop_papar &= ~PA_FRONT_LED; - immap->im_ioport.iop_padir |= PA_FRONT_LED; - immap->im_ioport.iop_paodr |= PA_FRONT_LED; - immap->im_ioport.iop_padat &= ~PA_FRONT_LED; - - Pbdat = immap->im_cpm.cp_pbdat; - - if (!(Pbdat & PB_ID_0)) - Id += 1; - if (!(Pbdat & PB_ID_1)) - Id += 2; - if (!(Pbdat & PB_ID_2)) - Id += 4; - if (!(Pbdat & PB_ID_3)) - Id += 8; - - if (Pbdat & PB_REV_0) - Rev += 1; - if (Pbdat & PB_REV_1) - Rev += 2; - - /* Turn ID off since we dont need it anymore */ - immap->im_cpm.cp_pbdat |= PB_ID_GND; - - printf ("GTH board, rev %d, id=0x%01x\n", Rev, Id); - return 0; -} - -#define _NOT_USED_ 0xffffffff -const uint sdram_table[] = { - /* Single read, offset 0 */ - 0x0f3dfc04, 0x0eefbc04, 0x01bf7c04, 0x0feafc00, - 0x1fb5fc45, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* Burst read, Offset 0x8, 4 reads */ - 0x0f3dfc04, 0x0eefbc04, 0x00bf7c04, 0x00ffec00, - 0x00fffc00, 0x01eafc00, 0x1fb5fc00, 0xfffffc45, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* Not used part of burst read is used for MRS, Offset 0x14 */ - 0xefeabc34, 0x1fb57c34, 0xfffffc05, _NOT_USED_, - /* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */ - - /* Single write, Offset 0x18 */ - 0x0f3dfc04, 0x0eebbc00, 0x01a27c04, 0x1fb5fc45, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* Burst write, Offset 0x20. 4 writes */ - 0x0f3dfc04, 0x0eebbc00, 0x00b77c00, 0x00fffc00, - 0x00fffc00, 0x01eafc04, 0x1fb5fc45, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* Not used part of burst write is used for precharge, Offset 0x2C */ - 0x0ff5fc04, 0xfffffc05, _NOT_USED_, _NOT_USED_, - /* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */ - - /* Period timer service. Offset 0x30. Refresh. Wait at least 70 ns after refresh command */ - 0x1ffd7c04, 0xfffffc04, 0xfffffc04, 0xfffffc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* Exception, Offset 0x3C */ - 0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_ -}; - -const uint fpga_table[] = { - /* Single read, offset 0 */ - 0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04, - 0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05, - - /* Burst read, Offset 0x8 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* Single write, Offset 0x18 */ - 0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04, - 0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05, - - /* Burst write, Offset 0x20. */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* Period timer service. Offset 0x30. */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* Exception, Offset 0x3C */ - 0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_ -}; - -int _initsdram (uint base, uint * noMbytes) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *mc = &immap->im_memctl; - volatile u32 *memptr; - - mc->memc_mptpr = MPTPR_PTP_DIV16; /* (16-17) */ - - /* SDRAM in UPMA - - GPL_0 is connected instead of A19 to SDRAM. - According to table 16-17, AMx should be 001, i.e. type 1 - and GPL_0 should hold address A10 when multiplexing */ - - mc->memc_mamr = (0x2E << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_AMA_TYPE_1 | MAMR_G0CLA_A10 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X; /* (16-13) */ - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Perform init of sdram ( Datasheet Page 9 ) - Precharge */ - mc->memc_mcr = 0x8000212C; /* run upm a at 0x2C (16-15) */ - - /* Run 2 refresh cycles */ - mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */ - mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */ - - /* Set Mode register */ - mc->memc_mar = 0x00000088; /* set mode register (address) to 0x022 (16-17) */ - /* Lower 2 bits are not connected to chip */ - mc->memc_mcr = 0x80002114; /* run upm a at 0x14 (16-15) */ - - /* CS1, base 0x0000000 - 64 Mbyte, use UPM A */ - mc->memc_or1 = 0xfc000000 | OR_CSNT_SAM; - mc->memc_br1 = BR_MS_UPMA | BR_V; /* SDRAM base always 0 */ - - /* Test if we really have 64 MB SDRAM */ - memptr = (u32 *) 0; - *memptr = 0; - - memptr = (u32 *) 0x2000000; /* First u32 in upper 32 MB */ - *memptr = 0x12345678; - - memptr = (u32 *) 0; - if (*memptr == 0x12345678) { - /* Wrapped, only have 32 MB */ - mc->memc_or1 = 0xfe000000 | OR_CSNT_SAM; - *noMbytes = 32; - } else { - /* 64 MB */ - *noMbytes = 64; - } - - /* Setup FPGA in UPMB */ - upmconfig (UPMB, (uint *) fpga_table, - sizeof (fpga_table) / sizeof (uint)); - - /* Enable UPWAITB */ - mc->memc_mbmr = MBMR_GPL_B4DIS; /* (16-13) */ - - /* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */ - mc->memc_or2 = 0xffc00000 | OR_BI; - mc->memc_br2 = FPGA_2_BASE | BR_MS_UPMB | BR_V; - - /* CS3, base FPGA_3_BASE - 4 MByte, use UPM B 16 bit */ - mc->memc_or3 = 0xffc00000 | OR_BI; - mc->memc_br3 = FPGA_3_BASE | BR_MS_UPMB | BR_V | BR_PS_16; - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -void _sdramdisable (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_br1 = 0x00000000; - - /* maybe we should turn off upmb here or something */ -} - -/* ------------------------------------------------------------------------- */ - -int initsdram (uint base, uint * noMbytes) -{ - *noMbytes = 32; - -#ifdef CONFIG_START_IN_RAM - /* SDRAM is already setup. Dont touch it */ - return 0; -#else - - if (!_initsdram (base, noMbytes)) { - - return 0; - } else { - _sdramdisable (); - - return -1; - } -#endif -} - -long int initdram (int board_type) -{ - u32 *i; - u32 j; - u32 k; - - /* GTH only have SDRAM */ - uint sdramsz; - - if (!initsdram (0x00000000, &sdramsz)) { - printf ("(%u MB SDRAM) ", sdramsz); - } else { - /******************************** - *SDRAM ERROR, HALT PROCESSOR - *********************************/ - printf ("SDRAM ERROR\n"); - while (1); - } - -#ifndef CONFIG_START_IN_RAM - -#define U32_S ((sdramsz<<18)-1) - -#if 1 - /* Do a simple memory test */ - for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) { - *i = j + (j << 17); - *(i + 1) = ~(j + (j << 18)); - } - - WATCHDOG_RESET (); - - printf ("."); - - for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) { - k = *i; - if (k != (j + (j << 17))) { - printf ("Mem test error, i=0x%x, 0x%x\n, 0x%x", (u32) i, j, k); - while (1); - } - k = *(i + 1); - if (k != ~(j + (j << 18))) { - printf ("Mem test error(+1), i=0x%x, 0x%x\n, 0x%x", - (u32) i + 1, j, k); - while (1); - } - } -#endif - - WATCHDOG_RESET (); - - /* Clear memory */ - for (i = (u32 *) 0; (u32) i < U32_S; i++) { - *i = 0; - } -#endif /* !start in ram */ - - WATCHDOG_RESET (); - - return (sdramsz << 20); -} - -#define POWER_OFFSET 0xF0000 -#define SW_WATCHDOG_REASON 13 - -#define BOOTDATA_OFFSET 0xF8000 -#define MAX_ATTEMPTS 5 - -#define FAILSAFE_BOOT 1 -#define SYSTEM_BOOT 2 - -#define WRITE_FLASH16(a, d) \ -do \ -{ \ - *((volatile u16 *) (a)) = (d);\ - } while(0) - -static void write_bootdata (volatile u16 * addr, u8 System, u8 Count) -{ - u16 data; - volatile u16 *flash = (u16 *) (CFG_FLASH_BASE); - - if ((System != FAILSAFE_BOOT) & (System != SYSTEM_BOOT)) { - printf ("Invalid system data %u, setting failsafe\n", System); - System = FAILSAFE_BOOT; - } - - if ((Count < 1) | (Count > MAX_ATTEMPTS)) { - printf ("Invalid boot count %u, setting 1\n", Count); - Count = 1; - } - - if (System == FAILSAFE_BOOT) { - printf ("Setting failsafe boot in flash\n"); - } else { - printf ("Setting system boot in flash\n"); - } - printf ("Boot attempt %d\n", Count); - - data = (System << 8) | Count; - /* AMD 16 bit */ - WRITE_FLASH16 (&flash[0x555], 0xAAAA); - WRITE_FLASH16 (&flash[0x2AA], 0x5555); - WRITE_FLASH16 (&flash[0x555], 0xA0A0); - - WRITE_FLASH16 (addr, data); -} - -static void maybe_update_restart_reason (volatile u32 * addr32) -{ - /* Update addr if sw wd restart */ - volatile u16 *flash = (u16 *) (CFG_FLASH_BASE); - volatile u16 *addr_16 = (u16 *) addr32; - u32 rsr; - - /* Dont reset register now */ - rsr = ((volatile immap_t *) CFG_IMMR)->im_clkrst.car_rsr; - - rsr >>= 24; - - if (rsr & 0x10) { - /* Was really a sw wd restart, update reason */ - - printf ("Last restart by software watchdog\n"); - - /* AMD 16 bit */ - WRITE_FLASH16 (&flash[0x555], 0xAAAA); - WRITE_FLASH16 (&flash[0x2AA], 0x5555); - WRITE_FLASH16 (&flash[0x555], 0xA0A0); - - WRITE_FLASH16 (addr_16, 0); - - udelay (1000); - - WATCHDOG_RESET (); - - /* AMD 16 bit */ - WRITE_FLASH16 (&flash[0x555], 0xAAAA); - WRITE_FLASH16 (&flash[0x2AA], 0x5555); - WRITE_FLASH16 (&flash[0x555], 0xA0A0); - - WRITE_FLASH16 (addr_16 + 1, SW_WATCHDOG_REASON); - - } -} - -static void check_restart_reason (void) -{ - /* Update restart reason if sw watchdog was - triggered */ - - int i; - volatile u32 *raddr; - - raddr = (u32 *) (CFG_FLASH_BASE + POWER_OFFSET); - - if (*raddr == 0xFFFFFFFF) { - /* Nothing written */ - maybe_update_restart_reason (raddr); - } else { - /* Search for latest written reason */ - i = 0; - while ((*(raddr + 2) != 0xFFFFFFFF) & (i < 2000)) { - raddr += 2; - i++; - } - if (i >= 2000) { - /* Whoa, dont write any more */ - printf ("*** No free restart reason found ***\n"); - } else { - /* Check if written */ - if (*raddr == 0) { - /* Erased by kernel, no new reason written */ - maybe_update_restart_reason (raddr + 2); - } - } - } -} - -static void check_boot_tries (void) -{ - /* Count the number of boot attemps - switch system if too many */ - - int i; - volatile u16 *addr; - volatile u16 data; - int failsafe = 1; - u8 system; - u8 count; - - addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET); - - if (*addr == 0xFFFF) { - printf ("*** No bootdata exists. ***\n"); - write_bootdata (addr, FAILSAFE_BOOT, 1); - } else { - /* Search for latest written bootdata */ - i = 0; - while ((*(addr + 1) != 0xFFFF) & (i < 8000)) { - addr++; - i++; - } - if (i >= 8000) { - /* Whoa, dont write any more */ - printf ("*** No bootdata found. Not updating flash***\n"); - } else { - /* See how many times we have tried to boot real system */ - data = *addr; - system = data >> 8; - count = data & 0xFF; - if ((system != SYSTEM_BOOT) & (system != FAILSAFE_BOOT)) { - printf ("*** Wrong system %d\n", system); - system = FAILSAFE_BOOT; - count = 1; - } else { - switch (count) { - case 0: - case 1: - case 2: - case 3: - case 4: - /* Try same system again if needed */ - count++; - break; - - case 5: - /* Switch system and reset tries */ - count = 1; - system = 3 - system; - printf ("***Too many boot attempts, switching system***\n"); - break; - default: - /* Switch system, start over and hope it works */ - printf ("***Unexpected data on addr 0x%x, %u***\n", - (u32) addr, data); - count = 1; - system = 3 - system; - } - } - write_bootdata (addr + 1, system, count); - if (system == SYSTEM_BOOT) { - failsafe = 0; - } - } - } - if (failsafe) { - printf ("Booting failsafe system\n"); - setenv ("bootargs", "panic=1 root=/dev/hda7"); - setenv ("bootcmd", "disk 100000 0:5;bootm 100000"); - } else { - printf ("Using normal system\n"); - setenv ("bootargs", "panic=1 root=/dev/hda4"); - setenv ("bootcmd", "disk 100000 0:2;bootm 100000"); - } -} - -int misc_init_r (void) -{ - u8 Rx[80]; - u8 Tx[5]; - int page; - int read = 0; - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - /* Kill fpga */ - immap->im_ioport.iop_papar &= ~(PA_FL_CONFIG | PA_FL_CE); - immap->im_ioport.iop_padir |= (PA_FL_CONFIG | PA_FL_CE); - immap->im_ioport.iop_paodr &= ~(PA_FL_CONFIG | PA_FL_CE); - - /* Enable fpga, active low */ - immap->im_ioport.iop_padat &= ~PA_FL_CE; - - /* Start configuration */ - immap->im_ioport.iop_padat &= ~PA_FL_CONFIG; - udelay (2); - - immap->im_ioport.iop_padat |= (PA_FL_CONFIG | PA_FL_CE); - - /* Check if we need to boot failsafe system */ - check_boot_tries (); - - /* Check if we need to update restart reason */ - check_restart_reason (); - - if (ee_init_data ()) { - printf ("EEPROM init failed\n"); - return (0); - } - - /* Read the pages where ethernet address is stored */ - - for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) { - /* Copy from nvram to scratchpad */ - Tx[0] = RECALL_MEMORY; - Tx[1] = page; - if (ee_do_command (Tx, 2, NULL, 0, TRUE)) { - printf ("EE user page %d recall failed\n", page); - return (0); - } - - Tx[0] = READ_SCRATCHPAD; - if (ee_do_command (Tx, 2, Rx + read, 9, TRUE)) { - printf ("EE user page %d read failed\n", page); - return (0); - } - /* Crc in 9:th byte */ - if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) { - printf ("EE read failed, page %d. CRC error\n", page); - return (0); - } - read += 8; - } - - /* Add eos after eth addr */ - Rx[17] = 0; - - printf ("Ethernet addr read from eeprom: %s\n\n", Rx); - - if ((Rx[2] != ':') | - (Rx[5] != ':') | - (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) { - printf ("*** ethernet addr invalid, using default ***\n"); - } else { - setenv ("ethaddr", (char *)Rx); - } - return (0); -} diff --git a/board/gth/u-boot.lds b/board/gth/u-boot.lds deleted file mode 100644 index 8ac4bda..0000000 --- a/board/gth/u-boot.lds +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o(.text) - *(.text) - common/environment.o(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/gw8260/Makefile b/board/gw8260/Makefile deleted file mode 100644 index 827a6ac..0000000 --- a/board/gw8260/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := gw8260.o flash.o -SOBJS := - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/gw8260/config.mk b/board/gw8260/config.mk deleted file mode 100644 index ca0540d..0000000 --- a/board/gw8260/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MBX8xx boards -# - -TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/gw8260/flash.c b/board/gw8260/flash.c deleted file mode 100644 index 5620a1d..0000000 --- a/board/gw8260/flash.c +++ /dev/null @@ -1,523 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Oliver Brown - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*********************************************************************/ -/* DESCRIPTION: - * This file contains the flash routines for the GW8260 board. - * - * - * - * MODULE DEPENDENCY: - * None - * - * - * RESTRICTIONS/LIMITATIONS: - * - * Only supports the following flash devices: - * AMD 29F080B - * AMD 29F016D - * - * Copyright (c) 2001, Advent Networks, Inc. - * - */ -/*********************************************************************/ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*********************************************************************/ -/* functions */ -/*********************************************************************/ - -/*********************************************************************/ -/* NAME: flash_init() - initializes flash banks */ -/* */ -/* DESCRIPTION: */ -/* This function initializes the flash bank(s). */ -/* */ -/* RETURNS: */ -/* The size in bytes of the flash */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return (CFG_FLASH0_SIZE * 1024 * 1024); /*size*/ -} - -/*********************************************************************/ -/* NAME: flash_print_info() - prints flash imformation */ -/* */ -/* DESCRIPTION: */ -/* This function prints the flash information. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* */ -/* OUTPUTS: */ -/* Displays flash information to console */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F080B: - printf ("AM29F080B (8 Mbit)\n"); - break; - case AMD_ID_F016D: - printf ("AM29F016D (16 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*********************************************************************/ -/* The following code cannot be run from FLASH! */ -/*********************************************************************/ - -/*********************************************************************/ -/* NAME: flash_get_size() - detects the flash size */ -/* */ -/* DESCRIPTION: */ -/* 1) Reads vendor ID and devices ID from the flash devices. */ -/* 2) Initializes flash info struct. */ -/* 3) Return the flash size */ -/* */ -/* INPUTS: */ -/* vu_long *addr - pointer to start of flash */ -/* flash_info_t *info - flash information structure */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* Size of the flash in bytes, or 0 if device id is unknown. */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Only supports the following devices: */ -/* AM29F080D */ -/* AM29F016D */ -/* */ -/*********************************************************************/ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - vu_long vendor, devid; - ulong base = (ulong)addr; - - /*printf("addr = %08lx\n", (unsigned long)addr); */ - - /* Reset and Write auto select command: read Manufacturer ID */ - addr[0x0000] = 0xf0f0f0f0; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - udelay (1000); - - vendor = addr[0]; - /*printf("vendor = %08lx\n", vendor); */ - if (vendor != 0x01010101) { - info->size = 0; - goto out; - } - - devid = addr[1]; - /*printf("devid = %08lx\n", devid); */ - - if ((devid & 0xff) == AMD_ID_F080B) { - info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F080B; - /* we have 16 sectors with 64KB each x 4 */ - info->sector_count = 16; - info->size = 4 * info->sector_count * 64*1024; - } else if ((devid & 0xff) == AMD_ID_F016D){ - info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F016D; - /* we have 32 sectors with 64KB each x 4 */ - info->sector_count = 32; - info->size = 4 * info->sector_count * 64*1024; - } else { - info->size = 0; - goto out; - } - /*printf("sector count = %08x\n", info->sector_count); */ - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* reset command */ - addr = (vu_long *)info->start[0]; - - out: - addr[0] = 0xf0f0f0f0; - - /*printf("size = %08x\n", info->size); */ - return info->size; -} - -/*********************************************************************/ -/* NAME: flash_erase() - erases flash by sector */ -/* */ -/* DESCRIPTION: */ -/* This function erases flash sectors starting for s_first to */ -/* s_last. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* int s_first - first sector to erase */ -/* int s_last - last sector to erase */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* Returns 0 for success, 1 for failure. */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/*********************************************************************/ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - udelay (100); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*********************************************************************/ -/* NAME: write_buff() - writes a buffer to flash */ -/* */ -/* DESCRIPTION: */ -/* This function copies a buffer, *src, to flash. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* uchar *src - pointer to buffer to write to flash */ -/* ulong addr - address to start write at */ -/* ulong cnt - number of bytes to write to flash */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - OK */ -/* 1 - write timeout */ -/* 2 - Flash not erased */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/*********************************************************************/ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; (i < 4) && (cnt > 0); ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; (cnt == 0) && (i < 4); ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; (i < 4) && (cnt > 0); ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; (i < 4); ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*********************************************************************/ -/* NAME: write_word() - writes a word to flash */ -/* */ -/* DESCRIPTION: */ -/* This writes a single word to flash. */ -/* */ -/* INPUTS: */ -/* flash_info_t *info - flash information structure */ -/* ulong dest - address to write */ -/* ulong data - data to write */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - OK */ -/* 1 - write timeout */ -/* 2 - Flash not erased */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/*********************************************************************/ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} -/*********************************************************************/ -/* End of flash.c */ -/*********************************************************************/ diff --git a/board/gw8260/gw8260.c b/board/gw8260/gw8260.c deleted file mode 100644 index 2719a95..0000000 --- a/board/gw8260/gw8260.c +++ /dev/null @@ -1,659 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Oliver Brown - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*********************************************************************/ -/* DESCRIPTION: - * This file contains the board routines for the GW8260 board. - * - * MODULE DEPENDENCY: - * None - * - * RESTRICTIONS/LIMITATIONS: - * None - * - * Copyright (c) 2001, Advent Networks, Inc. - */ -/*********************************************************************/ - -#include -#include -#include - -/* - * I/O Port configuration table - * - */ -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* TP14 */ - /* PA30 */ { 1, 1, 1, 1, 0, 0 }, /* US_RTS */ - /* PA29 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_DATA */ - /* PA28 */ { 1, 0, 0, 1, 0, 1 }, /* LSSI_CLK */ - /* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* TP12 */ - /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* IO_STATUS */ - /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CLOCK */ - /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* IO_CONFIG */ - /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DONE */ - /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* IO_DATA */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* US_TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD1 */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* DS_RXD3 */ - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE7 */ - /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE6 */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE5 */ - /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE4 */ - /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE3 */ - /* PA8 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE2 */ - /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* LSSI_IN */ - /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* SPARE0 */ - /* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* DEMOD_RESET_ */ - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* MOD_RESET_ */ - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* IO_RESET */ - /* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* TX_ENABLE */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* RX_LOCK */ - /* PA0 */ { 1, 0, 0, 1, 0, 1 } /* MPC_RESET_ */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FETH0_TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD3 */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD2 */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD1 */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FETH0_TXD0 */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD0 */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD1 */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD2 */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RXD3 */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD3 */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD2 */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD1 */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RXD0 */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD0 */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD1 */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD2 */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FETH1_TXD3 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_RESET_ */ - /* PC30 */ { 1, 0, 0, 1, 0, 1 }, /* FAST_PAUSE_ */ - /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW1 */ - /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* FAST_SLEW0 */ - /* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* TP13 */ - /* PC26 */ { 1, 0, 0, 0, 0, 0 }, /* RXDECDFLG */ - /* PC25 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFAIL */ - /* PC24 */ { 1, 0, 0, 0, 0, 0 }, /* RXACQFLG */ - /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* WD_TCL */ - /* PC22 */ { 1, 0, 0, 1, 0, 0 }, /* WD_EN */ - /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* US_TXCLK */ - /* PC20 */ { 1, 0, 0, 0, 0, 0 }, /* DS_RXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FETH0_TX_CLK */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_RX_CLK */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FETH1_TX_CLK */ - /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* TX_SHUTDOWN_ */ - /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* RS_232_DTR_ */ - /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* TXERR */ - /* PC12 */ { 1, 0, 0, 1, 0, 1 }, /* FETH1_MDDIS */ - /* PC11 */ { 1, 0, 0, 1, 0, 1 }, /* FETH0_MDDIS */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */ - /* PC9 */ { 1, 0, 0, 1, 1, 1 }, /* MDIO */ - /* PC8 */ { 1, 0, 0, 1, 1, 1 }, /* SER_NUM */ - /* PC7 */ { 1, 1, 0, 0, 0, 0 }, /* US_CTS */ - /* PC6 */ { 1, 1, 0, 0, 0, 0 }, /* DS_CD_ */ - /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* FETH1_PWRDWN */ - /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* FETH0_PWRDWN */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED3 */ - /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED2 */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED1 */ - /* PC0 */ { 1, 0, 0, 1, 0, 1 }, /* MPULED0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* not used */ - /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* SDRAM_SCL */ - /* PD13 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED7 */ - /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED6 */ - /* PD11 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED5 */ - /* PD10 */ { 1, 0, 0, 1, 0, 0 }, /* MPULED4 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* RS232_TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* RD232_RXD */ - /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* not used */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/*********************************************************************/ -/* NAME: checkboard() - Displays the board type and serial number */ -/* */ -/* OUTPUTS: */ -/* Displays the board type and serial number */ -/* */ -/* RETURNS: */ -/* Always returns 1 */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int checkboard (void) -{ - char *str; - - puts ("Board: Advent Networks gw8260\n"); - - str = getenv ("serial#"); - if (str != NULL) { - printf ("SN: %s\n", str); - } - return 0; -} - - -#if defined (CFG_DRAM_TEST) -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CFG_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CFG_SDRAM_BASE; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CFG_DRAM_TEST_DATA */ - -#if defined (CFG_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CFG_SDRAM_BASE; - const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CFG_DRAM_TEST_ADDRESS */ - -#if defined (CFG_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CFG_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_SDRAM_BASE; - const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - char *s; - int rundata, runaddress, runwalk; - - s = getenv ("testdramdata"); - rundata = (s && (*s == 'y')) ? 1 : 0; - s = getenv ("testdramaddress"); - runaddress = (s && (*s == 'y')) ? 1 : 0; - s = getenv ("testdramwalk"); - runwalk = (s && (*s == 'y')) ? 1 : 0; - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM ... "); - } -#ifdef CFG_DRAM_TEST_DATA - if (rundata == 1) { - if (mem_test_data () == 1) { - return 1; - } - } -#endif -#ifdef CFG_DRAM_TEST_ADDRESS - if (runaddress == 1) { - if (mem_test_address () == 1) { - return 1; - } - } -#endif -#ifdef CFG_DRAM_TEST_WALK - if (runwalk == 1) { - if (mem_test_walk () == 1) { - return 1; - } - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed"); - } - return 0; - -} -#endif /* CFG_DRAM_TEST */ - -/*********************************************************************/ -/* NAME: initdram() - initializes SDRAM controller */ -/* */ -/* DESCRIPTION: */ -/* Initializes the MPC8260's SDRAM controller. */ -/* */ -/* INPUTS: */ -/* CFG_IMMR - MPC8260 Internal memory map */ -/* CFG_SDRAM_BASE - Physical start address of SDRAM */ -/* CFG_PSDMR - SDRAM mode register */ -/* CFG_MPTPR - Memory refresh timer prescaler register */ -/* CFG_SDRAM0_SIZE - SDRAM size */ -/* */ -/* RETURNS: */ -/* SDRAM size in bytes */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8); - ulong psdmr = CFG_PSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - *ramaddr = c; - } - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* return total ram size */ - return (CFG_SDRAM0_SIZE * 1024 * 1024); -} - -/*********************************************************************/ -/* End of gw8260.c */ -/*********************************************************************/ diff --git a/board/gw8260/u-boot.lds b/board/gw8260/u-boot.lds deleted file mode 100644 index ab65cb1..0000000 --- a/board/gw8260/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/hermes/Makefile b/board/hermes/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/hermes/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/hermes/config.mk b/board/hermes/config.mk deleted file mode 100644 index 008165f..0000000 --- a/board/hermes/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Multidata HERMES-PRO ISDN Routers -# - -TEXT_BASE = 0xFE000000 diff --git a/board/hermes/flash.c b/board/hermes/flash.c deleted file mode 100644 index 799fe83..0000000 --- a/board/hermes/flash.c +++ /dev/null @@ -1,460 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_byte (flash_info_t *info, ulong dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - uchar value; - vu_char *caddr = (vu_char *)addr; - ulong base = (ulong)addr; - - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0AAA] = 0xAA; - caddr[0x0555] = 0x55; - caddr[0x0AAA] = 0x90; - - value = caddr[0]; - switch (value) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = caddr[2]; /* device ID */ - - switch (value) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[4] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *)info->start[0]; - - *caddr = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_char *addr = (vu_char*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - addr[0x0AAA] = 0x80; - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char*)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_char*)(info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - addr[0x0AAA] = 0xA0; - - *((vu_char *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c deleted file mode 100644 index e95d9ee..0000000 --- a/board/hermes/hermes.c +++ /dev/null @@ -1,605 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static ulong board_init (void); -static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd, - uchar * msg); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1fe77c35, 0xffaffc34, 0x1fa57c35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00, - 0xf0afcc00, 0xe1bb8c06, 0x1ff77c47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ID string (HERMES...) - * - * Return code for board revision and network speed - */ - -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - char *s = getenv ("serial#"); - char *e; - - puts ("Board: "); - - if (!s || strncmp (s, "HERMES", 6)) { - puts ("### No HW ID - assuming HERMES-PRO"); - } else { - for (e = s; *e; ++e) { - if (*e == ' ') - break; - } - - for (; s < e; ++s) { - putc (*s); - } - } - - gd->board_type = board_init (); - - printf (" Rev. %ld.x\n", (gd->board_type >> 16)); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = 0x0400; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 1 to the SDRAM banks at preliminary address - */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - - /* HERMES-PRO boards have only one bank SDRAM */ - - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mamr = 0xD0802114; - memctl->memc_mcr = 0x80002105; - udelay (1); - memctl->memc_mamr = 0xD0802118; - memctl->memc_mcr = 0x80002130; - udelay (1); - memctl->memc_mamr = 0xD0802114; - memctl->memc_mcr = 0x80002106; - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - udelay (10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#define PB_LED_3 0x00020000 /* Status LED's */ -#define PB_LED_2 0x00010000 -#define PB_LED_1 0x00008000 -#define PB_LED_0 0x00004000 - -#define PB_LED_ALL (PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3) - -#define PC_REP_SPD1 0x00000800 -#define PC_REP_SPD0 0x00000400 - -#define PB_RESET_2081 0x00000020 /* Reset PEB2081 */ - -#define PB_MAI_4 0x00000010 /* Configuration */ -#define PB_MAI_3 0x00000008 -#define PB_MAI_2 0x00000004 -#define PB_MAI_1 0x00000002 -#define PB_MAI_0 0x00000001 - -#define PB_MAI_ALL (PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4) - - -#define PC_REP_MGRPRS 0x0200 -#define PC_REP_SPD 0x0040 /* Select 100 Mbps */ -#define PC_REP_RES 0x0004 -#define PC_BIT14 0x0002 /* ??? */ -#define PC_BIT15 0x0001 /* ??? ENDSL ?? */ - -/* ------------------------------------------------------------------------- */ - -static ulong board_init (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - ulong reg, revision, speed = 100; - int ethspeed; - char *s; - - if ((s = getenv ("ethspeed")) != NULL) { - if (strcmp (s, "100") == 0) { - ethspeed = 100; - } else if (strcmp (s, "10") == 0) { - ethspeed = 10; - } else { - ethspeed = 0; - } - } else { - ethspeed = 0; - } - - /* Configure Port B Output Pins => 0x0003cc3F */ - reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 | - PB_MAI_ALL; - immr->im_cpm.cp_pbpar &= ~reg; - immr->im_cpm.cp_pbodr &= ~reg; - immr->im_cpm.cp_pbdat &= ~reg; /* all 0 */ - immr->im_cpm.cp_pbdir |= reg; - - /* Check hardware revision */ - if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) { - /* - * Revision 3.x hardware - */ - revision = 3; - - immr->im_ioport.iop_pcdat = 0x0240; - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14); /* = 0x0246 */ - immr->im_ioport.iop_pcdat |= PC_REP_RES; - } else { - immr->im_ioport.iop_pcdat = 0x0002; - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0207 */ - - if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) { - /* - * Revision 2.x hardware: PC9 connected to PB21 - */ - revision = 2; - - if (ethspeed == 0) { - /* both 10 and 100 Mbps allowed: - * select 10 Mbps and autonegotiation - */ - puts (" [10+100]"); - immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */ - speed = 10; - } else if (ethspeed == 10) { - /* we are asked for 10 Mbps, - * so select 10 Mbps - */ - puts (" [10]"); - immr->im_cpm.cp_pbdat = 0; /* ??? */ - speed = 10; - } else { - /* anything else: - * select 100 Mbps - */ - puts (" [100]"); - immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1; - /* SPD1:SPD0 = 1:1 - 100 Mbps */ - speed = 100; - } - immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14); - - /* must be run from RAM */ - /* start_lxt980 (speed); */ - /*************************/ - } else { - /* - * Revision 1.x hardware - */ - revision = 1; - - immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14; /* = 0x0202 */ - immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0247 */ - - if (ethspeed == 0) { - /* both 10 and 100 Mbps allowed: - * select 100 Mbps and autonegotiation - */ - puts (" [10+100]"); - immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */ - immr->im_ioport.iop_pcdat |= PC_REP_SPD; - } else if (ethspeed == 10) { - /* we are asked for 10 Mbps, - * so select 10 Mbps - */ - puts (" [10]"); - immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */ - } else { - /* anything else: - * select 100 Mbps - */ - puts (" [100]"); - immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1; - /* SPD1:SPD0 = 1:1 - 100 Mbps */ - immr->im_ioport.iop_pcdat |= PC_REP_SPD; - } - - immr->im_ioport.iop_pcdat |= PC_REP_RES; - } - } - SHOW_BOOT_PROGRESS (0x00); - - return ((revision << 16) | (speed & 0xFFFF)); -} - -/* ------------------------------------------------------------------------- */ - -#define SCC_SM 1 /* Index => SCC2 */ -#define PROFF PROFF_SCC2 - -#define SMI_MSGLEN 8 /* Length of SMI Messages */ - -#define PHYGPCR_ADDR 0x109 /* Port Enable */ -#define PHYPCR_ADDR 0x132 /* PHY Port Control Reg. (port 1) */ -#define LEDPCR_ADDR 0x141 /* LED Port Control Reg. */ -#define RPRESET_ADDR 0x144 /* Repeater Reset */ - -#define PHYPCR_SPEED 0x2000 /* on for 100 Mbps, off for 10 Mbps */ -#define PHYPCR_AN 0x1000 /* on to enable Auto-Negotiation */ -#define PHYPCR_REST_AN 0x0200 /* on to restart Auto-Negotiation */ -#define PHYPCR_FDX 0x0100 /* on for Full Duplex, off for HDX */ -#define PHYPCR_COLT 0x0080 /* on to enable COL signal test */ - -/* ------------------------------------------------------------------------- */ - -/* - * Must run from RAM: - * uses parameter RAM area which is used for stack while running from ROM - */ -void hermes_start_lxt980 (int speed) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm); - volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]); - volatile cbd_t *bd; - volatile hdlc_pram_t *hp; - uchar smimsg[SMI_MSGLEN]; - ushort phypcrval; - uint bd_off; - int pnr; - - printf ("LXT9880: %3d Mbps\n", speed); - - immr->im_ioport.iop_paodr |= 0x0008; /* init PAODR: PA12 (TXD2) open drain */ - immr->im_ioport.iop_papar |= 0x400c; /* init PAPAR: TXD2, RXD2, BRGO4 */ - immr->im_ioport.iop_padir &= 0xbff3; /* init PADIR: BRGO4 */ - immr->im_ioport.iop_padir |= 0x4000; - - /* get temporary BD; no need for permanent alloc */ - bd_off = dpram_base_align (8); - - bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off); - - bd->cbd_bufaddr = 0; - bd->cbd_datlen = 0; - bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC; - - /* init. baudrate generator BRG4 */ - cp->cp_brgc4 = (0x00010000 | (50 << 1)); /* output 1 MHz */ - - cp->cp_sicr &= 0xFFFF00FF; /* SICR: mask SCC2 */ - cp->cp_sicr |= 0x00001B00; /* SICR: SCC2 clk BRG4 */ - - /* init SCC_SM register */ - sp->scc_psmr = 0x0000; /* init PSMR: no additional flags */ - sp->scc_todr = 0x0000; - sp->scc_dsr = 0x7e7e; - - /* init. SCC_SM parameter area */ - hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF]; - - hp->tbase = bd_off; /* offset from beginning of DPRAM */ - - hp->rfcr = 0x18; - hp->tfcr = 0x18; - hp->mrblr = 10; - - hp->c_mask = 0x0000f0b8; - hp->c_pres = 0x0000ffff; - - hp->disfc = 0; - hp->crcec = 0; - hp->abtsc = 0; - hp->nmarc = 0; - hp->retrc = 0; - - hp->mflr = 10; - - hp->rfthr = 1; - - hp->hmask = 0; - hp->haddr1 = 0; - hp->haddr2 = 0; - hp->haddr3 = 0; - hp->haddr4 = 0; - - cp->cp_cpcr = SCC_SM << 6 | 0x0001; /* SCC_SM: init TX/RX params */ - while (cp->cp_cpcr & CPM_CR_FLG); - - /* clear all outstanding SCC events */ - sp->scc_scce = ~0; - - /* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */ - sp->scc_gsmrh = 0; - sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 | - SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC; - -#if 0 - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = (RPRESET_ADDR << 4) & 0xf0; - smimsg[3] = RPRESET_ADDR >> 4; - smimsg[4] = 0x01; - smimsg[5] = 0x00; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); -#endif - - smimsg[0] = 0x7f; /* BROADCAST */ - smimsg[1] = 0x34; /* ASSIGN HUB ID */ - smimsg[2] = 0x00; - smimsg[3] = 0x00; - smimsg[4] = 0x00; /* HUB ID = 0 */ - smimsg[5] = 0x00; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - smimsg[0] = 0x7f; /* BROADCAST */ - smimsg[1] = 0x3c; /* SET ARBOUT TO 0 */ - smimsg[2] = 0x00; /* ADDRESS = 0 */ - smimsg[3] = 0x00; - smimsg[4] = 0x00; /* DATA = 0 */ - smimsg[5] = 0x00; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - if (speed == 100) { - phypcrval = PHYPCR_SPEED; /* 100 MBIT, disable autoneg. */ - } else { - phypcrval = 0; /* 10 MBIT, disable autoneg. */ - } - - /* send MSGs */ - for (pnr = 0; pnr < 8; pnr++) { - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0; - smimsg[3] = (PHYPCR_ADDR + pnr) >> 4; - smimsg[4] = (unsigned char) (phypcrval & 0xff); - smimsg[5] = (unsigned char) (phypcrval >> 8); - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - } - - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0; - smimsg[3] = PHYGPCR_ADDR >> 4; - smimsg[4] = 0xff; /* enable port 1-8 */ - smimsg[5] = 0x01; /* enable MII1 (0x01) */ - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - smimsg[0] = 0x00; /* CHIP/HUB ID */ - smimsg[1] = 0x38; /* WRITE CMD */ - smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0; - smimsg[3] = LEDPCR_ADDR >> 4; - smimsg[4] = 0xaa; /* Port 1-8 Conf.bits = 10 (Hardware control) */ - smimsg[5] = 0xaa; - smimsg[6] = 0x00; - smimsg[7] = 0x00; - - send_smi_frame (sp, bd, smimsg); - - /* - * Disable Transmitter (so that we can free the BD, too) - */ - sp->scc_gsmrl &= ~SCC_GSMRL_ENT; -} - -/* ------------------------------------------------------------------------- */ - -static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd, - uchar * msg) -{ -#ifdef DEBUG - unsigned hub, chip, cmd, length, addr; - - hub = msg[0] & 0x1F; - chip = msg[0] >> 5; - cmd = msg[1] & 0x1F; - length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3); - addr = (msg[2] >> 4) | (msg[3] << 4); - - printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: " - "%02x %02x %02x %02x\n", - hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]); -#endif /* DEBUG */ - - bd->cbd_bufaddr = (uint) msg; - bd->cbd_datlen = SMI_MSGLEN; - bd->cbd_sc |= BD_SC_READY; - - /* wait for msg transmitted */ - while ((sp->scc_scce & 0x0002) == 0); - /* clear all events */ - sp->scc_scce = ~0; -} - -/* ------------------------------------------------------------------------- */ - -void show_boot_progress (int status) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - status ^= 0x0F; - status = (status & 0x0F) << 14; - immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status; -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds deleted file mode 100644 index ef53ab7..0000000 --- a/board/hermes/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - cpu/mpc8xx/interrupts.o (.text) - lib_ppc/time.o (.text) - lib_ppc/ticks.o (.text) - lib_ppc/cache.o (.text) - lib_generic/crc32.o (.text) - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug deleted file mode 100644 index a961fa4..0000000 --- a/board/hermes/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - lib_ppc/ppcstring.o (.text) - cpu/mpc8xx/interrupts.o (.text) - lib_ppc/time.o (.text) - lib_ppc/ticks.o (.text) - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/hidden_dragon/Makefile b/board/hidden_dragon/Makefile deleted file mode 100644 index b9f1df6..0000000 --- a/board/hidden_dragon/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/hidden_dragon/README b/board/hidden_dragon/README deleted file mode 100644 index 529fe2b..0000000 --- a/board/hidden_dragon/README +++ /dev/null @@ -1,60 +0,0 @@ -U-Boot for Hidden Dragon board ------------------------------- - -Hidden Dragon is a MPC824x-based board by Motorola. For the most -part it is similar to Sandpoint8245 board. So unless otherwise -mentioned, the codes in this directory are adapted from ../sandpoint -directory. - -Apparently there are very few of this board out there. Even Motorola -website does not have any info on it. - -RAM: - start = 0x0000 0000 - size = 0x0200 0000 (32 MB) - -Flash: - BANK ONE: - start = 0xFFE0 0000 - size = 0x0020 0000 (2 MB) - flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits) - flash sectors = 16K, 2x8K, 32K, 31x64K - - BANK TWO: - NONE - -The processor interrupt vectors reside on the first 256 bytes -starting from address 0xFFF00000. The "reset vector" (first -instruction executed after reset) is located on 0xFFF0 0100. - -U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is located in flash separately from -U-Boot, at the second sector of the first flash bank, starting from -0xFFE04000 until 0xFFE06000 (8KB). - -Network: - - RTL8139 chip on the base board (SUPPORTED) - - RTL8129 chip on the processor board (NOT SUPPORTED) - -Serial: - - Two NS16550 compatible UART on the processor board (SUPPORTED) - - One NS16550 compatible UART on the base board (UNTESTED) - -Misc: - VIA686A PCI SuperIO peripheral controller - - 2 USB ports (UNTESTED) - - 2 PS2 ports (UNTESTED) - - Parallel port (UNTESTED) - - IDE & floppy interface (UNTESTED) - - S3 Savage4 video card (UNTESTED) - -TODO: ------ -- Support for the VIA686A based peripherals -- The RTL8139 driver frequently gives rx error. -- Support for RTL8129 network controller. (Why is the support removed from - rtl8139.c driver?) - -(C) Copyright 2004 -Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com diff --git a/board/hidden_dragon/config.mk b/board/hidden_dragon/config.mk deleted file mode 100644 index 5c36d05..0000000 --- a/board/hidden_dragon/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Hidden Dragon boards -# - -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/hidden_dragon/early_init.S b/board/hidden_dragon/early_init.S deleted file mode 100644 index 07dafb7..0000000 --- a/board/hidden_dragon/early_init.S +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2001 - * Thomas Koeller, tkoeller@gmx.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASSEMBLY__ -#define __ASSEMBLY__ 1 -#endif - -#include -#include -#include -#include - -#if defined(USE_DINK32) - /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ - #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) -#else - #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) -#endif - - .text - - /* Values to program into memory controller registers */ -tbl: .long MCCR1, MCCR1VAL - .long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT - .long MCCR3 - .long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ - (CFG_REFREC << MCCR3_REFREC_SHIFT) | \ - (CFG_RDLAT << MCCR3_RDLAT_SHIFT) - .long MCCR4 - .long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ - (CFG_REGISTERD_TYPE_BUFFER << 20) | \ - (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ - ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \ - (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ - (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ - ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) - .long MSAR1 - .long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR1 - .long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MSAR2 - .long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR2 - .long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR1 - .long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR1 - .long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR2 - .long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR2 - .long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long 0 - - - /* - * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This - * must be done in assembly, since we have no stack at this point. - */ - .global early_init_f -early_init_f: - mflr r10 - - /* basic memory controller configuration */ - lis r3, CONFIG_ADDR_HIGH - lis r4, CONFIG_DATA_HIGH - bl lab -lab: mflr r5 - lwzu r0, tbl - lab(r5) -loop: lwz r1, 4(r5) - stwbrx r0, 0, r3 - eieio - stwbrx r1, 0, r4 - eieio - lwzu r0, 8(r5) - cmpli cr0, 0, r0, 0 - bne cr0, loop - - /* set bank enable bits */ - lis r0, MBER@h - ori r0, 0, MBER@l - li r1, CFG_BANK_ENABLE - stwbrx r0, 0, r3 - eieio - stb r1, 0(r4) - eieio - - /* delay loop */ - lis r0, 0x0003 - mtctr r0 -delay: bdnz delay - - /* enable memory controller */ - lis r0, MCCR1@h - ori r0, 0, MCCR1@l - stwbrx r0, 0, r3 - eieio - lwbrx r0, 0, r4 - oris r0, 0, MCCR1_MEMGO@h - stwbrx r0, 0, r4 - eieio - - /* set up stack pointer */ - lis r1, CFG_INIT_SP_OFFSET@h - ori r1, r1, CFG_INIT_SP_OFFSET@l - - mtlr r10 - blr diff --git a/board/hidden_dragon/flash.c b/board/hidden_dragon/flash.c deleted file mode 100644 index 21c5a01..0000000 --- a/board/hidden_dragon/flash.c +++ /dev/null @@ -1,575 +0,0 @@ -/* - * (C) Copyright 2004 - * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com - * - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*flash command address offsets*/ - -#define ADDR0 (0xAAA) -#define ADDR1 (0x555) -#define ADDR3 (0x001) - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -static unsigned long flash_id (unsigned char mfct, unsigned char chip) - __attribute__ ((const)); - -typedef struct { - FLASH_WORD_SIZE extval; - unsigned short intval; -} map_entry; - -static unsigned long flash_id (unsigned char mfct, unsigned char chip) -{ - static const map_entry mfct_map[] = { - {(FLASH_WORD_SIZE) AMD_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, - {(FLASH_WORD_SIZE) FUJ_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, - {(FLASH_WORD_SIZE) STM_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, - {(FLASH_WORD_SIZE) MT_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, - {(FLASH_WORD_SIZE) INTEL_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, - {(FLASH_WORD_SIZE) INTEL_ALT_MANU, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} - }; - - static const map_entry chip_map[] = { - {AMD_ID_F040B, FLASH_AM040}, - {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} - }; - - const map_entry *p; - unsigned long result = FLASH_UNKNOWN; - - /* find chip id */ - for (p = &chip_map[0]; - p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) - if (p->extval == chip) { - result = FLASH_VENDMASK | p->intval; - break; - } - - /* find vendor id */ - for (p = &mfct_map[0]; - p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) - if (p->extval == mfct) { - result &= ~FLASH_VENDMASK; - result |= (unsigned long) p->intval << 16; - break; - } - - return result; -} - -unsigned long flash_init (void) -{ - unsigned long i; - unsigned char j; - static const ulong flash_banks[] = CFG_FLASH_BANKS; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - - pflinfo->flash_id = FLASH_UNKNOWN; - pflinfo->size = 0; - pflinfo->sector_count = 0; - } - - /* Enable writes to Hidden Dragon flash */ - { - register unsigned char temp; - - CONFIG_READ_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, - temp); - temp &= ~0x20; /* clear BIOSWP bit */ - CONFIG_WRITE_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, - temp); - } - - for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - const unsigned long base_address = flash_banks[i]; - volatile FLASH_WORD_SIZE *const flash = - (FLASH_WORD_SIZE *) base_address; - - flash[0xAAA << (3 * i)] = 0xaa; - flash[0x555 << (3 * i)] = 0x55; - flash[0xAAA << (3 * i)] = 0x90; - __asm__ __volatile__ ("sync"); - - pflinfo->flash_id = - flash_id (flash[0x0], flash[0x2 + 14 * i]); - - switch (pflinfo->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - pflinfo->size = 0x00080000; - pflinfo->sector_count = 8; - for (j = 0; j < 8; j++) { - pflinfo->start[j] = - base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_STM800AB: - pflinfo->size = 0x00100000; - pflinfo->sector_count = 19; - pflinfo->start[0] = base_address; - pflinfo->start[1] = base_address + 0x4000; - pflinfo->start[2] = base_address + 0x6000; - pflinfo->start[3] = base_address + 0x8000; - for (j = 1; j < 16; j++) { - pflinfo->start[j + 3] = - base_address + 0x00010000 * j; - } - break; - default: - /* The chip used is not listed in flash_id - TODO: Change this to explicitly detect the flash type - */ - { - int sector_addr = base_address; - - pflinfo->size = 0x00200000; - pflinfo->sector_count = 35; - pflinfo->start[0] = sector_addr; - sector_addr += 0x4000; /* 16K */ - pflinfo->start[1] = sector_addr; - sector_addr += 0x2000; /* 8K */ - pflinfo->start[2] = sector_addr; - sector_addr += 0x2000; /* 8K */ - pflinfo->start[3] = sector_addr; - sector_addr += 0x8000; /* 32K */ - - for (j = 4; j < 35; j++) { - pflinfo->start[j] = sector_addr; - sector_addr += 0x10000; /* 64K */ - } - } - break; - } - /* Protect monitor and environment sectors - */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - /* reset device to read mode */ - flash[0x0000] = 0xf0; - __asm__ __volatile__ ("sync"); - } - - /* only have 1 bank */ - return flash_info[0].size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if (info->flash_id != FLASH_UNKNOWN) { - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - mfct = "AMD"; - break; - case FLASH_MAN_FUJ: - mfct = "FUJITSU"; - break; - case FLASH_MAN_STM: - mfct = "STM"; - break; - case FLASH_MAN_SST: - mfct = "SST"; - break; - case FLASH_MAN_BM: - mfct = "Bright Microelectonics"; - break; - case FLASH_MAN_INTEL: - mfct = "Intel"; - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - type = "AM29F040B (512K * 8, uniform sector size)"; - break; - case FLASH_AM400B: - type = "AM29LV400B (4 Mbit, bottom boot sect)"; - break; - case FLASH_AM400T: - type = "AM29LV400T (4 Mbit, top boot sector)"; - break; - case FLASH_AM800B: - type = "AM29LV800B (8 Mbit, bottom boot sect)"; - break; - case FLASH_AM800T: - type = "AM29LV800T (8 Mbit, top boot sector)"; - break; - case FLASH_AM160T: - type = "AM29LV160T (16 Mbit, top boot sector)"; - break; - case FLASH_AM320B: - type = "AM29LV320B (32 Mbit, bottom boot sect)"; - break; - case FLASH_AM320T: - type = "AM29LV320T (32 Mbit, top boot sector)"; - break; - case FLASH_STM800AB: - type = "M29W800AB (8 Mbit, bottom boot sect)"; - break; - case FLASH_SST800A: - type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; - break; - case FLASH_SST160A: - type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; - break; - } - } - - printf ("\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, type, info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) { - unsigned long size; - unsigned int erased; - unsigned long *flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for (flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) - && erased; flash++) - erased = *flash == ~0x0UL; - - printf ("%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", info->protect[i] ? "RO" : " "); - } - - puts ("\n"); - return; -} - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *) (info->start[0] + - ((info->start[sect] - - info->start[0]) << sh8b)); - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - udelay (30000); /* wait 30 ms */ - } else - addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - - info-> - start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/hidden_dragon/hidden_dragon.c b/board/hidden_dragon/hidden_dragon.c deleted file mode 100644 index daab833..0000000 --- a/board/hidden_dragon/hidden_dragon.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2004 - * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com - * - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -int checkboard (void) -{ - /*TODO: Check processor type */ - - puts ( "Board: Hidden Dragon " -#ifdef CONFIG_MPC8240 - "8240" -#endif -#ifdef CONFIG_MPC8245 - "8245" -#endif - " ##Test not implemented yet##\n"); - /* TODO: Implement board test */ - return 0; -} - -long int initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_hidden_dragon_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_hidden_dragon_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} diff --git a/board/hidden_dragon/speed.h b/board/hidden_dragon/speed.h deleted file mode 100644 index b66393b..0000000 --- a/board/hidden_dragon/speed.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/hidden_dragon/u-boot.lds b/board/hidden_dragon/u-boot.lds deleted file mode 100644 index 2a5cd2e..0000000 --- a/board/hidden_dragon/u-boot.lds +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/hmi1001/Makefile b/board/hmi1001/Makefile deleted file mode 100644 index ed36ea7..0000000 --- a/board/hmi1001/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/hmi1001/config.mk b/board/hmi1001/config.mk deleted file mode 100644 index 51e8e84c..0000000 --- a/board/hmi1001/config.mk +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# INKA 4X0 board: -# -# Valid values for TEXT_BASE are: -# -# 0xFFE00000 boot high -# -# 0x00100000 boot from RAM (for testing only) -# - -ifndef TEXT_BASE -## Standard: boot high -TEXT_BASE = 0xFFF00000 -## For testing: boot from RAM -#TEXT_BASE = 0x00100000 -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c deleted file mode 100644 index 237e863..0000000 --- a/board/hmi1001/hmi1001.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#ifndef CFG_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. - */ - -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ -#else /* CFG_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CFG_RAMBOOT */ - -/* return dramsize + dramsize2; */ - return dramsize; -} - -int checkboard (void) -{ - puts ("Board: HMI1001\n"); - return 0; -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -#define S1_ROT 0xf0 -#define S2_Q 0x40 -#define S2_M 0x20 - -struct kbd_data_t { - char s1; - char s2; -}; - -struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) -{ - kbd_data->s1 = *((volatile uchar*)(CFG_STATUS1_BASE)); - kbd_data->s2 = *((volatile uchar*)(CFG_STATUS2_BASE)); - - return kbd_data; -} - -static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str) -{ - char s1 = str[0]; - char s2; - - if (s1 >= '0' && s1 <= '9') - s1 -= '0'; - else if (s1 >= 'a' && s1 <= 'f') - s1 = s1 - 'a' + 10; - else if (s1 >= 'A' && s1 <= 'F') - s1 = s1 - 'A' + 10; - else - return -1; - - if (((S1_ROT & kbd_data->s1) >> 4) != s1) - return -1; - - s2 = (S2_Q | S2_M) & kbd_data->s2; - - switch (str[1]) { - case 'q': - case 'Q': - if (s2 == S2_Q) - return -1; - break; - case 'm': - case 'M': - if (s2 == S2_M) - return -1; - break; - case '\0': - if (s2 == (S2_Q | S2_M)) - return 0; - default: - return -1; - } - - if (str[2]) - return -1; - - return 0; -} - -static uchar *key_match (const struct kbd_data_t *kbd_data) -{ - uchar magic[sizeof (kbd_magic_prefix) + 1]; - uchar *suffix; - uchar *kbd_magic_keys; - - /* - * The following string defines the characters that can be appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix = kbd_magic_keys; *suffix || - suffix == kbd_magic_keys; ++suffix) { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); - - if (compare_magic(kbd_data, getenv(magic)) == 0) { - uchar cmd_name[sizeof (kbd_command_prefix) + 1]; - char *cmd; - - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - cmd = getenv (cmd_name); - - return (cmd); - } - } - - return (NULL); -} - -#endif /* CONFIG_PREBOOT */ - -int misc_init_r (void) -{ -#ifdef CONFIG_PREBOOT - struct kbd_data_t kbd_data; - /* Decode keys */ - uchar *str = strdup (key_match (get_keys (&kbd_data))); - /* Set or delete definition */ - setenv ("preboot", str); - free (str); -#endif /* CONFIG_PREBOOT */ - - return 0; -} - -int board_early_init_r (void) -{ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - *(vu_long *)MPC5XXX_BOOTCS_START = - *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE); - *(vu_long *)MPC5XXX_BOOTCS_STOP = - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); - return 0; -} -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif diff --git a/board/hmi1001/u-boot.lds b/board/hmi1001/u-boot.lds deleted file mode 100644 index 123a14c..0000000 --- a/board/hmi1001/u-boot.lds +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc5xxx/start.o (.text) - cpu/mpc5xxx/traps.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) - - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/hymod/Makefile b/board/hymod/Makefile deleted file mode 100644 index b52af9a..0000000 --- a/board/hymod/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o bsp.o eeprom.o fetch.o input.o env.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c deleted file mode 100644 index 0596fa4..0000000 --- a/board/hymod/bsp.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01 - */ - -#include -#include -#include -#include - -/*----------------------------------------------------------------------- - * Board Special Commands: FPGA load/store, EEPROM erase - */ - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -#define LOAD_SUCCESS 0 -#define LOAD_FAIL_NOCONF 1 -#define LOAD_FAIL_NOINIT 2 -#define LOAD_FAIL_NODONE 3 - -#define STORE_SUCCESS 0 - -/* - * Programming the Hymod FPGAs - * - * The 8260 io port config table is set up so that the INIT pin is - * held Low (Open Drain output 0) - this will delay the automatic - * Power-On config until INIT is released (by making it an input). - * - * If the FPGA has been programmed before, then the assertion of PROGRAM - * will initiate configuration (i.e. it begins clearing the RAM). - * - * When the FPGA is ready to receive configuration data (either after - * releasing INIT after Power-On, or after asserting PROGRAM), it will - * pull INIT high. - * - * Notes from Paul Dunn: - * - * 1. program pin should be forced low for >= 300ns - * (about 20 bus clock cycles minimum). - * - * 2. then wait for init to go high, which signals - * that the FPGA has cleared its internal memory - * and is ready to load - * - * 3. perform load writes of entire config file - * - * 4. wait for done to go high, which should be - * within a few bus clock cycles. If done has not - * gone high after reasonable period, then load - * has not worked (wait several ms?) - */ - -int -fpga_load (int mezz, uchar *addr, ulong size) -{ - DECLARE_GLOBAL_DATA_PTR; - - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - xlx_info_t *fp; - xlx_iopins_t *fpgaio; - volatile uchar *fpgabase; - volatile uint cnt; - uchar *eaddr = addr + size; - int result; - - if (mezz) - fp = &cp->mezz.xlx[0]; - else - fp = &cp->main.xlx[0]; - - if (!fp->mmap.prog.exists) - return (LOAD_FAIL_NOCONF); - - fpgabase = (uchar *)fp->mmap.prog.base; - fpgaio = &fp->iopins; - - /* set enable HIGH if required */ - if (fpgaio->enable_pin.flag) - iopin_set_high (&fpgaio->enable_pin); - - /* ensure INIT is released (set it to be an input) */ - iopin_set_in (&fpgaio->init_pin); - - /* toggle PROG Low then High (will already be Low after Power-On) */ - iopin_set_low (&fpgaio->prog_pin); - udelay (1); /* minimum 300ns - 1usec should do it */ - iopin_set_high (&fpgaio->prog_pin); - - /* wait for INIT High */ - cnt = 0; - while (!iopin_is_high (&fpgaio->init_pin)) - if (++cnt == 10000000) { - result = LOAD_FAIL_NOINIT; - goto done; - } - - /* write configuration data */ - while (addr < eaddr) - *fpgabase = *addr++; - - /* wait for DONE High */ - cnt = 0; - while (!iopin_is_high (&fpgaio->done_pin)) - if (++cnt == 100000000) { - result = LOAD_FAIL_NODONE; - goto done; - } - - /* success */ - result = LOAD_SUCCESS; - - done: - - if (fpgaio->enable_pin.flag) - iopin_set_low (&fpgaio->enable_pin); - - return (result); -} - -/* ------------------------------------------------------------------------- */ -int -do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - uchar *addr, *save_addr; - ulong size; - int mezz, arg, result; - - switch (argc) { - - case 0: - case 1: - break; - - case 2: - if (strcmp (argv[1], "info") == 0) { - printf ("\nHymod FPGA Info...\n"); - printf ("\t\t\t\tAddress\t\tSize\n"); - printf ("\tMain Configuration:\t0x%08x\t%d\n", - FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE); - printf ("\tMain Register:\t\t0x%08x\t%d\n", - FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE); - printf ("\tMain Port:\t\t0x%08x\t%d\n", - FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE); - printf ("\tMezz Configuration:\t0x%08x\t%d\n", - FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE); - return 0; - } - break; - - case 3: - if (strcmp (argv[1], "store") == 0) { - addr = (uchar *) simple_strtoul (argv[2], NULL, 16); - - save_addr = addr; -#if 0 - /* fpga readback unimplemented */ - while (more readback data) - *addr++ = *fpga; - result = error ? STORE_FAIL_XXX : STORE_SUCCESS; -#else - result = STORE_SUCCESS; -#endif - - if (result == STORE_SUCCESS) { - printf ("SUCCEEDED (%d bytes)\n", - addr - save_addr); - return 0; - } else - printf ("FAILED (%d bytes)\n", - addr - save_addr); - return 1; - } - break; - - case 4: - if (strcmp (argv[1], "tftp") == 0) { - copy_filename (BootFile, argv[2], sizeof (BootFile)); - load_addr = simple_strtoul (argv[3], NULL, 16); - NetBootFileXferSize = 0; - - if (NetLoop (TFTP) <= 0) { - printf ("tftp transfer failed - aborting " - "fgpa load\n"); - return 1; - } - - if (NetBootFileXferSize == 0) { - printf ("can't determine file size - " - "aborting fpga load\n"); - return 1; - } - - printf ("File transfer succeeded - " - "beginning fpga load..."); - - result = fpga_load (0, (uchar *) load_addr, - NetBootFileXferSize); - - if (result == LOAD_SUCCESS) { - printf ("SUCCEEDED\n"); - return 0; - } else if (result == LOAD_FAIL_NOCONF) - printf ("FAILED (no CONF)\n"); - else if (result == LOAD_FAIL_NOINIT) - printf ("FAILED (no INIT)\n"); - else - printf ("FAILED (no DONE)\n"); - return 1; - - } - /* fall through ... */ - - case 5: - if (strcmp (argv[1], "load") == 0) { - if (argc == 5) { - if (strcmp (argv[2], "main") == 0) - mezz = 0; - else if (strcmp (argv[2], "mezz") == 0) - mezz = 1; - else { - printf ("FPGA type must be either " - "`main' or `mezz'\n"); - return 1; - } - arg = 3; - } else { - mezz = 0; - arg = 2; - } - - addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16); - size = (ulong) simple_strtoul (argv[arg], NULL, 16); - - result = fpga_load (mezz, addr, size); - - if (result == LOAD_SUCCESS) { - printf ("SUCCEEDED\n"); - return 0; - } else if (result == LOAD_FAIL_NOCONF) - printf ("FAILED (no CONF)\n"); - else if (result == LOAD_FAIL_NOINIT) - printf ("FAILED (no INIT)\n"); - else - printf ("FAILED (no DONE)\n"); - return 1; - } - break; - - default: - break; - } - - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; -} -U_BOOT_CMD( - fpga, 6, 1, do_fpga, - "fpga - FPGA sub-system\n", - "load [type] addr size\n" - " - write the configuration data at memory address `addr',\n" - " size `size' bytes, into the FPGA of type `type' (either\n" - " `main' or `mezz', default `main'). e.g.\n" - " `fpga load 100000 7d8f'\n" - " loads the main FPGA with config data at address 100000\n" - " HEX, size 7d8f HEX (32143 DEC) bytes\n" - "fpga tftp file addr\n" - " - transfers `file' from the tftp server into memory at\n" - " address `addr', then writes the entire file contents\n" - " into the main FPGA\n" - "fpga store addr\n" - " - read configuration data from the main FPGA (the mezz\n" - " FPGA is write-only), into address `addr'. There must be\n" - " enough memory available at `addr' to hold all the config\n" - " data - the size of which is determined by VC:???\n" - "fpga info\n" - " - print information about the Hymod FPGA, namely the\n" - " memory addresses at which the four FPGA local bus\n" - " address spaces appear in the physical address space\n" -); -/* ------------------------------------------------------------------------- */ -int -do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - uchar data[HYMOD_EEPROM_SIZE]; - uint addr = CFG_I2C_EEPROM_ADDR; - - switch (argc) { - - case 1: - addr |= HYMOD_EEOFF_MAIN; - break; - - case 2: - if (strcmp (argv[1], "main") == 0) { - addr |= HYMOD_EEOFF_MAIN; - break; - } - if (strcmp (argv[1], "mezz") == 0) { - addr |= HYMOD_EEOFF_MEZZ; - break; - } - /* fall through ... */ - - default: - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - memset (data, 0, HYMOD_EEPROM_SIZE); - - eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE); - - return 0; -} -U_BOOT_CMD( - eeclear, 1, 0, do_eecl, - "eeclear - Clear the eeprom on a Hymod board \n", - "[type]\n" - " - write zeroes into the EEPROM on the board of type `type'\n" - " (`type' is either `main' or `mezz' - default `main')\n" - " Note: the EEPROM write enable jumper must be installed\n" -); - -/* ------------------------------------------------------------------------- */ - -int -do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ -#if 0 - int rc; -#endif -#ifdef CONFIG_ETHER_LOOPBACK_TEST - extern void eth_loopback_test (void); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - - printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n"); - -#if 0 - /* Load FPGA with test program */ - - printf ("Loading test FPGA program ..."); - - rc = fpga_load (0, test_bitfile, sizeof (test_bitfile)); - - switch (rc) { - - case LOAD_SUCCESS: - printf (" SUCCEEDED\n"); - break; - - case LOAD_FAIL_NOCONF: - printf (" FAILED (no configuration space defined)\n"); - return 1; - - case LOAD_FAIL_NOINIT: - printf (" FAILED (timeout - no INIT signal seen)\n"); - return 1; - - case LOAD_FAIL_NODONE: - printf (" FAILED (timeout - no DONE signal seen)\n"); - return 1; - - default: - printf (" FAILED (unknown return code from fpga_load\n"); - return 1; - } - - /* run Local Bus <=> Xilinx tests */ - - /* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */ - - /* run SDRAM test */ -#endif - -#ifdef CONFIG_ETHER_LOOPBACK_TEST - /* run Ethernet test */ - eth_loopback_test (); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - - return 0; -} - -#endif /* CFG_CMD_BSP */ - -/* ------------------------------------------------------------------------- */ diff --git a/board/hymod/config.mk b/board/hymod/config.mk deleted file mode 100644 index 0a9985f..0000000 --- a/board/hymod/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# HYMOD boards -# - -TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -I$(TOPDIR) - -OBJCFLAGS = --remove-section=.ppcenv diff --git a/board/hymod/eeprom.c b/board/hymod/eeprom.c deleted file mode 100644 index c9b9b18..0000000 --- a/board/hymod/eeprom.c +++ /dev/null @@ -1,694 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* imports from fetch.c */ -extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *)); - -/* imports from input.c */ -extern int hymod_get_serno (const char *); - -/* this is relative to the root of the server's tftp directory */ -static char *def_bddb_cfgdir = "/hymod/bddb"; - -static int -hymod_eeprom_load (int which, hymod_eeprom_t *ep) -{ - unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - unsigned offset = 0; - uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp; - hymod_eehdr_t hdr; - ulong len, crc; - - memset (ep, 0, sizeof *ep); - - eeprom_read (dev_addr, offset, (uchar *)&hdr, sizeof (hdr)); - offset += sizeof (hdr); - - if (hdr.id != HYMOD_EEPROM_ID || hdr.ver > HYMOD_EEPROM_VER || - (len = hdr.len) > HYMOD_EEPROM_MAXLEN) - return (0); - - eeprom_read (dev_addr, offset, data, len); - offset += len; - - eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong)); - offset += sizeof (ulong); - - if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc) - return (0); - - ep->ver = hdr.ver; - dp = data; edp = dp + len; - - for (;;) { - ulong rtyp; - uchar rlen, *rdat; - - rtyp = *dp++; - if ((rtyp & 0x80) == 0) - rlen = *dp++; - else { - uchar islarge = rtyp & 0x40; - - rtyp = ((rtyp & 0x3f) << 8) | *dp++; - if (islarge) { - rtyp = (rtyp << 8) | *dp++; - rtyp = (rtyp << 8) | *dp++; - } - - rlen = *dp++; - rlen = (rlen << 8) | *dp++; - if (islarge) { - rlen = (rlen << 8) | *dp++; - rlen = (rlen << 8) | *dp++; - } - } - - if (rtyp == 0) - break; - - rdat = dp; - dp += rlen; - - if (dp > edp) /* error? */ - break; - - switch (rtyp) { - - case HYMOD_EEREC_SERNO: /* serial number */ - if (rlen == sizeof (ulong)) - ep->serno = \ - ((ulong)rdat[0] << 24) | \ - ((ulong)rdat[1] << 16) | \ - ((ulong)rdat[2] << 8) | \ - (ulong)rdat[3]; - break; - - case HYMOD_EEREC_DATE: /* date */ - if (rlen == sizeof (hymod_date_t)) { - ep->date.year = ((ushort)rdat[0] << 8) | \ - (ushort)rdat[1]; - ep->date.month = rdat[2]; - ep->date.day = rdat[3]; - } - break; - - case HYMOD_EEREC_BATCH: /* batch */ - if (rlen <= HYMOD_MAX_BATCH) - memcpy (ep->batch, rdat, ep->batchlen = rlen); - break; - - case HYMOD_EEREC_TYPE: /* board type */ - if (rlen == 1) - ep->bdtype = *rdat; - break; - - case HYMOD_EEREC_REV: /* board revision */ - if (rlen == 1) - ep->bdrev = *rdat; - break; - - case HYMOD_EEREC_SDRAM: /* sdram size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_SDRAM) { - int i; - - for (i = 0; i < rlen; i++) - ep->sdramsz[i] = rdat[i]; - ep->nsdram = rlen; - } - break; - - case HYMOD_EEREC_FLASH: /* flash size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_FLASH) { - int i; - - for (i = 0; i < rlen; i++) - ep->flashsz[i] = rdat[i]; - ep->nflash = rlen; - } - break; - - case HYMOD_EEREC_ZBT: /* zbt ram size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_ZBT) { - int i; - - for (i = 0; i < rlen; i++) - ep->zbtsz[i] = rdat[i]; - ep->nzbt = rlen; - } - break; - - case HYMOD_EEREC_XLXTYP: /* xilinx fpga type(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].type = rdat[i]; - ep->nxlx = rlen; - } - break; - - case HYMOD_EEREC_XLXSPD: /* xilinx fpga speed(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].speed = rdat[i]; - } - break; - - case HYMOD_EEREC_XLXTMP: /* xilinx fpga temperature(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].temp = rdat[i]; - } - break; - - case HYMOD_EEREC_XLXGRD: /* xilinx fpga grade(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].grade = rdat[i]; - } - break; - - case HYMOD_EEREC_CPUTYP: /* CPU type */ - if (rlen == 1) - ep->mpc.type = *rdat; - break; - - case HYMOD_EEREC_CPUSPD: /* CPU speed */ - if (rlen == 1) - ep->mpc.cpuspd = *rdat; - break; - - case HYMOD_EEREC_CPMSPD: /* CPM speed */ - if (rlen == 1) - ep->mpc.cpmspd = *rdat; - break; - - case HYMOD_EEREC_BUSSPD: /* bus speed */ - if (rlen == 1) - ep->mpc.busspd = *rdat; - break; - - case HYMOD_EEREC_HSTYPE: /* hs-serial chip type */ - if (rlen == 1) - ep->hss.type = *rdat; - break; - - case HYMOD_EEREC_HSCHIN: /* num hs-serial input chans */ - if (rlen == 1) - ep->hss.nchin = *rdat; - break; - - case HYMOD_EEREC_HSCHOUT: /* num hs-serial output chans */ - if (rlen == 1) - ep->hss.nchout = *rdat; - break; - - default: /* ignore */ - break; - } - } - - return (1); -} - -/* maps an ascii "name=value" into a binary eeprom data record */ -typedef - struct _eerec_map { - char *name; - uint type; - uchar *(*handler) \ - (struct _eerec_map *, uchar *, uchar *, uchar *); - uint length; - uint maxlen; - } -eerec_map_t; - -static uchar * -uint_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - char *eval; - ulong lval; - - lval = simple_strtol ((char *)val, &eval, 10); - - if ((uchar *)eval == val || *eval != '\0') { - printf ("%s rec (%s) is not a valid uint\n", rp->name, val); - return (NULL); - } - - if (dp + 2 + rp->length > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = rp->length; - - switch (rp->length) { - - case 1: - if (lval >= 256) { - printf ("%s rec value (%lu) out of range (0-255)\n", - rp->name, lval); - return (NULL); - } - *dp++ = lval; - break; - - case 2: - if (lval >= 65536) { - printf ("%s rec value (%lu) out of range (0-65535)\n", - rp->name, lval); - return (NULL); - } - *dp++ = lval >> 8; - *dp++ = lval; - break; - - case 4: - *dp++ = lval >> 24; - *dp++ = lval >> 16; - *dp++ = lval >> 8; - *dp++ = lval; - break; - - default: - printf ("huh? rp->length not 1, 2 or 4! (%d)\n", rp->length); - return (NULL); - } - - return (dp); -} - -static uchar * -date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - hymod_date_t date; - char *p = (char *)val; - char *ep; - ulong lval; - - lval = simple_strtol (p, &ep, 10); - if (ep == p || *ep++ != '-') { -bad_date: - printf ("%s rec (%s) is not a valid date\n", rp->name, val); - return (NULL); - } - if (lval >= 65536) - goto bad_date; - date.year = lval; - - lval = simple_strtol (p = ep, &ep, 10); - if (ep == p || *ep++ != '-' || lval == 0 || lval > 12) - goto bad_date; - date.month = lval; - - lval = simple_strtol (p = ep, &ep, 10); - if (ep == p || *ep != '\0' || lval == 0 || lval > 31) - goto bad_date; - date.day = lval; - - if (dp + 2 + rp->length > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = rp->length; - *dp++ = date.year >> 8; - *dp++ = date.year; - *dp++ = date.month; - *dp++ = date.day; - - return (dp); -} - -static uchar * -string_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - uint len; - - if ((len = strlen ((char *)val)) > rp->maxlen) { - printf ("%s rec (%s) string is too long (%d>%d)\n", - rp->name, val, len, rp->maxlen); - return (NULL); - } - - if (dp + 2 + len > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = len; - memcpy (dp, val, len); - dp += len; - - return (dp); -} - -static uchar * -bytes_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - uchar bytes[HYMOD_MAX_BYTES], nbytes, *p; - char *ep; - - for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) { - ulong lval; - - lval = simple_strtol ((char *)p, &ep, 10); - if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \ - lval >= 256) { - printf ("%s rec (%s) byte array has invalid uint\n", - rp->name, val); - return (NULL); - } - if (nbytes >= HYMOD_MAX_BYTES) { - printf ("%s rec (%s) byte array too long\n", - rp->name, val); - return (NULL); - } - bytes[nbytes++] = lval; - - if (*ep != '\0') - ep++; - } - - if (dp + 2 + nbytes > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = nbytes; - memcpy (dp, bytes, nbytes); - dp += nbytes; - - return (dp); -} - -static eerec_map_t eerec_map[] = { - /* name type handler len max */ - { "serno", HYMOD_EEREC_SERNO, uint_handler, 4, 0 }, - { "date", HYMOD_EEREC_DATE, date_handler, 4, 0 }, - { "batch", HYMOD_EEREC_BATCH, string_handler, 0, HYMOD_MAX_BATCH }, - { "type", HYMOD_EEREC_TYPE, uint_handler, 1, 0 }, - { "rev", HYMOD_EEREC_REV, uint_handler, 1, 0 }, - { "sdram", HYMOD_EEREC_SDRAM, bytes_handler, 0, HYMOD_MAX_SDRAM }, - { "flash", HYMOD_EEREC_FLASH, bytes_handler, 0, HYMOD_MAX_FLASH }, - { "zbt", HYMOD_EEREC_ZBT, bytes_handler, 0, HYMOD_MAX_ZBT }, - { "xlxtyp", HYMOD_EEREC_XLXTYP, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxspd", HYMOD_EEREC_XLXSPD, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxtmp", HYMOD_EEREC_XLXTMP, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxgrd", HYMOD_EEREC_XLXGRD, bytes_handler, 0, HYMOD_MAX_XLX }, - { "cputyp", HYMOD_EEREC_CPUTYP, uint_handler, 1, 0 }, - { "cpuspd", HYMOD_EEREC_CPUSPD, uint_handler, 1, 0 }, - { "cpmspd", HYMOD_EEREC_CPMSPD, uint_handler, 1, 0 }, - { "busspd", HYMOD_EEREC_BUSSPD, uint_handler, 1, 0 }, - { "hstype", HYMOD_EEREC_HSTYPE, uint_handler, 1, 0 }, - { "hschin", HYMOD_EEREC_HSCHIN, uint_handler, 1, 0 }, - { "hschout", HYMOD_EEREC_HSCHOUT, uint_handler, 1, 0 }, -}; - -static int neerecs = sizeof eerec_map / sizeof eerec_map[0]; - -static uchar data[HYMOD_EEPROM_SIZE], *sdp, *dp, *edp; - -static int -eerec_callback (uchar *name, uchar *val) -{ - eerec_map_t *rp; - - for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++) - if (strcmp ((char *)name, rp->name) == 0) - break; - - if (rp >= &eerec_map[neerecs]) - return (0); - - if ((dp = (*rp->handler) (rp, val, dp, edp)) == NULL) - return (0); - - return (1); -} - -static int -hymod_eeprom_fetch(int which, char *filename, ulong addr) -{ - unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0]; - ulong crc; - - memset (hp, 0, sizeof *hp); - hp->id = HYMOD_EEPROM_ID; - hp->ver = HYMOD_EEPROM_VER; - - dp = sdp = (uchar *)(hp + 1); - edp = dp + HYMOD_EEPROM_MAXLEN; - - if (fetch_and_parse (filename, addr, eerec_callback) == 0) - return (0); - - hp->len = dp - sdp; - - crc = crc32 (0, data, dp - data); - memcpy (dp, &crc, sizeof (ulong)); - dp += sizeof (ulong); - - eeprom_write (dev_addr, 0, data, dp - data); - - return (1); -} - -static char *type_vals[] = { - "NONE", "IO", "CLP", "DSP", "INPUT", "ALT-INPUT", "DISPLAY" -}; - -static char *xlxtyp_vals[] = { - "NONE", "XCV300E", "XCV400E", "XCV600E" -}; - -static char *xlxspd_vals[] = { - "NONE", "6", "7", "8" -}; - -static char *xlxtmp_vals[] = { - "NONE", "COM", "IND" -}; - -static char *xlxgrd_vals[] = { - "NONE", "NORMAL", "ENGSAMP" -}; - -static char *cputyp_vals[] = { - "NONE", "MPC8260" -}; - -static char *clk_vals[] = { - "NONE", "33", "66", "100", "133", "166", "200" -}; - -static char *hstype_vals[] = { - "NONE", "AMCC-S2064A" -}; - -static void -print_mem (char *l, char *s, uchar n, uchar a[]) -{ - if (n > 0) { - if (n == 1) - printf ("%s%dMB %s", s, 1 << (a[0] - 20), l); - else { - ulong t = 0; - int i; - - for (i = 0; i < n; i++) - t += 1 << (a[i] - 20); - - printf ("%s%luMB %s (%d banks:", s, t, l, n); - - for (i = 0; i < n; i++) - printf ("%dMB%s", - 1 << (a[i] - 20), - (i == n - 1) ? ")" : ","); - } - } - else - printf ("%sNO %s", s, l); -} - -void -hymod_eeprom_print (hymod_eeprom_t *ep) -{ - int i; - - printf (" Hymod %s board, rev %03d\n", - type_vals[ep->bdtype], ep->bdrev); - - printf (" serial #: %010lu, date %04d-%02d-%02d", - ep->serno, ep->date.year, ep->date.month, ep->date.day); - if (ep->batchlen > 0) - printf (", batch \"%.*s\"", ep->batchlen, ep->batch); - puts ("\n"); - - switch (ep->bdtype) { - - case HYMOD_BDTYPE_IO: - case HYMOD_BDTYPE_CLP: - case HYMOD_BDTYPE_DSP: - printf (" Motorola %s CPU, speeds: %s/%s/%s", - cputyp_vals[ep->mpc.type], clk_vals[ep->mpc.cpuspd], - clk_vals[ep->mpc.cpmspd], clk_vals[ep->mpc.busspd]); - - print_mem ("SDRAM", ", ", ep->nsdram, ep->sdramsz); - - print_mem ("FLASH", ", ", ep->nflash, ep->flashsz); - - puts ("\n"); - - print_mem ("ZBT", " ", ep->nzbt, ep->zbtsz); - - if (ep->nxlx > 0) { - hymod_xlx_t *xp; - - if (ep->nxlx == 1) { - xp = &ep->xlx[0]; - printf (", Xilinx %s FPGA (%s/%s/%s)", - xlxtyp_vals[xp->type], - xlxspd_vals[xp->speed], - xlxtmp_vals[xp->temp], - xlxgrd_vals[xp->grade]); - } - else { - printf (", %d Xilinx FPGAs (", ep->nxlx); - for (i = 0; i < ep->nxlx; i++) { - xp = &ep->xlx[i]; - printf ("%s[%s/%s/%s]%s", - xlxtyp_vals[xp->type], - xlxspd_vals[xp->speed], - xlxtmp_vals[xp->temp], - xlxgrd_vals[xp->grade], - (i == ep->nxlx - 1) ? ")" : ", "); - } - } - } - else - puts(", NO FPGAs"); - - puts ("\n"); - - if (ep->hss.type > 0) - printf (" High Speed Serial: " - "%s, %d input%s, %d output%s\n", - hstype_vals[ep->hss.type], - ep->hss.nchin, - (ep->hss.nchin == 1 ? "" : "s"), - ep->hss.nchout, - (ep->hss.nchout == 1 ? "" : "s")); - break; - - case HYMOD_BDTYPE_INPUT: - case HYMOD_BDTYPE_ALTINPUT: - case HYMOD_BDTYPE_DISPLAY: - break; - - default: - /* crap! */ - printf (" UNKNOWN BOARD TYPE: %d\n", ep->bdtype); - break; - } -} - -int -hymod_eeprom_read (int which, hymod_eeprom_t *ep) -{ - char *label = which ? "mezzanine" : "main"; - unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - char filename[50], prompt[50], *dir; - int serno, count = 0, rc; - - rc = eeprom_probe (dev_addr, 0); - - if (rc > 0) { - printf ("*** probe for eeprom failed with code %d\n", rc); - return (0); - } - - if (rc < 0) - return (rc); - - sprintf (prompt, "Enter %s board serial number: ", label); - - if ((dir = getenv ("bddb_cfgdir")) == NULL) - dir = def_bddb_cfgdir; - - for (;;) { - int rc; - - if (hymod_eeprom_load (which, ep)) - return (1); - - printf ("*** %s board EEPROM contents are %sinvalid\n", - label, count == 0 ? "" : "STILL "); - - puts ("*** will fetch from server (Ctrl-C to abort)\n"); - - serno = hymod_get_serno (prompt); - - if (serno < 0) { - if (serno == -1) - puts ("\n*** interrupted!"); - else - puts ("\n*** timeout!"); - puts (" - ignoring eeprom contents\n"); - return (0); - } - - sprintf (filename, "%s/%010d.cfg", dir, serno); - - printf ("*** fetching %s board EEPROM contents from server\n", - label); - - rc = hymod_eeprom_fetch (which, filename, CFG_LOAD_ADDR); - - if (rc == 0) { - puts ("*** fetch failed - ignoring eeprom contents\n"); - return (0); - } - - count++; - } -} diff --git a/board/hymod/env.c b/board/hymod/env.c deleted file mode 100644 index f9e1421..0000000 --- a/board/hymod/env.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2003 - * Murray Jensen, CSIRO-MIT, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* imports from fetch.c */ -extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *)); - -/* this is relative to the root of the server's tftp directory */ -static char *def_global_env_path = "/hymod/global_env"; - -static int -env_callback (uchar *name, uchar *value) -{ - DECLARE_GLOBAL_DATA_PTR; - - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - char ov[CFG_CBSIZE], nv[CFG_CBSIZE], *p, *q, *nn, c, *curver, *newver; - int override = 1, append = 0, remove = 0, nnl, ovl, nvl; - - nn = (char *)name; - - if (*nn == '-') { - override = 0; - nn++; - } - - while (*nn == ' ' || *nn == '\t') - nn++; - - if ((nnl = strlen (nn)) == 0) { - printf ("Empty name in global env file\n"); - return (0); - } - - if ((c = nn[nnl - 1]) == '+' || c == '-') { - if (c == '+') - append = 1; - else - remove = 1; - nn[--nnl] = '\0'; - } - - while (nnl > 0 && ((c = nn[nnl - 1]) == ' ' || c == '\t')) - nn[--nnl] = '\0'; - if (nnl == 0) { - printf ("Empty name in global env file\n"); - return (0); - } - - p = (char *)value; - q = nv; - - while ((c = *p) == ' ' || c == '\t') - p++; - - nvl = strlen (p); - while (nvl > 0 && ((c = p[nvl - 1]) == ' ' || c == '\t')) - p[--nvl] = '\0'; - - while ((*q = *p++) != '\0') { - if (*q == '%') { - switch (*p++) { - - case '\0': /* whoops - back up */ - p--; - break; - - case '%': /* a single percent character */ - q++; - break; - - case 's': /* main board serial number as string */ - q += sprintf (q, "%010lu", - cp->main.eeprom.serno); - break; - - case 'S': /* main board serial number as number */ - q += sprintf (q, "%lu", cp->main.eeprom.serno); - break; - - default: /* ignore any others */ - break; - } - } - else - q++; - } - - if ((nvl = q - nv) == 0) { - setenv (nn, NULL); - return (1); - } - - if ((curver = getenv ("global_env_version")) == NULL) - curver = "unknown"; - - if ((newver = getenv ("new_genv_version")) == NULL || \ - strcmp (curver, newver) == 0) { - if (strcmp (nn, "version") == 0) - setenv ("new_genv_version", nv); - return (1); - } - - if ((p = getenv (nn)) != NULL) { - - strcpy (ov, p); - ovl = strlen (ov); - - if (append) { - - if (strstr (ov, nv) == NULL) { - - printf ("Appending '%s' to env var '%s'\n", - nv, nn); - - while (nvl >= 0) { - nv[ovl + 1 + nvl] = nv[nvl]; - nvl--; - } - - nv[ovl] = ' '; - - while (--ovl >= 0) - nv[ovl] = ov[ovl]; - - setenv (nn, nv); - } - - return (1); - } - - if (remove) { - - if (strstr (ov, nv) != NULL) { - - printf ("Removing '%s' from env var '%s'\n", - nv, nn); - - while ((p = strstr (ov, nv)) != NULL) { - q = p + nvl; - if (*q == ' ') - q++; - strcpy(p, q); - } - - setenv (nn, ov); - } - - return (1); - } - - if (!override || strcmp (ov, nv) == 0) - return (1); - - printf ("Re-setting env cmd '%s' from '%s' to '%s'\n", - nn, ov, nv); - } - else - printf ("Setting env cmd '%s' to '%s'\n", nn, nv); - - setenv (nn, nv); - return (1); -} - -void -hymod_check_env (void) -{ - char *p, *path, *curver, *newver; - int firsttime = 0, needsave = 0; - - if (getenv ("global_env_loaded") == NULL) { - puts ("*** global environment has never been loaded\n"); - puts ("*** fetching from server"); - firsttime = 1; - } - else if ((p = getenv ("always_check_env")) != NULL && - strcmp (p, "yes") == 0) - puts ("*** checking for updated global environment"); - else - return; - - puts (" (Control-C to Abort)\n"); - - if ((path = getenv ("global_env_path")) == NULL || *path == '\0') - path = def_global_env_path; - - if (fetch_and_parse (path, CFG_LOAD_ADDR, env_callback) == 0) { - puts ("*** Fetch of global environment failed!\n"); - return; - } - - if ((newver = getenv ("new_genv_version")) == NULL) { - puts ("*** Version number not set - contents ignored!\n"); - return; - } - - if ((curver = getenv ("global_env_version")) == NULL || \ - strcmp (curver, newver) != 0) { - setenv ("global_env_version", newver); - needsave = 1; - } - else - printf ("*** Global environment up-to-date (ver %s)\n", curver); - - setenv ("new_genv_version", NULL); - - if (firsttime) { - setenv ("global_env_loaded", "yes"); - needsave = 1; - } - - if (needsave) - puts ("\n*** Remember to run the 'saveenv' " - "command to save the changes\n\n"); -} diff --git a/board/hymod/fetch.c b/board/hymod/fetch.c deleted file mode 100644 index e121d55..0000000 --- a/board/hymod/fetch.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* imports from input.c */ -extern int hymod_get_ethaddr (void); - -int -fetch_and_parse (char *fn, ulong addr, int (*cback)(uchar *, uchar *)) -{ - char *ethaddr; - uchar *fp, *efp; - int rc, count = 0; - - while ((ethaddr = getenv ("ethaddr")) == NULL || *ethaddr == '\0') { - - printf ("*** Ethernet address is%s not set\n", - count == 0 ? "" : " STILL"); - - if ((rc = hymod_get_ethaddr ()) < 0) { - if (rc == -1) - puts ("\n*** interrupted!"); - else - puts ("\n*** timeout!"); - printf (" - fetch of '%s' aborted\n", fn); - return (0); - } - - count++; - } - - copy_filename (BootFile, fn, sizeof (BootFile)); - load_addr = addr; - NetBootFileXferSize = 0; - - if (NetLoop (TFTP) == 0) { - printf ("tftp transfer of file '%s' failed\n", fn); - return (0); - } - - if (NetBootFileXferSize == 0) { - printf ("can't determine size of file '%s'\n", fn); - return (0); - } - - fp = (uchar *)load_addr; - efp = fp + NetBootFileXferSize; - - do { - uchar *name, *value; - - if (*fp == '#' || *fp == '\n') { - /* skip this line */ - while (fp < efp && *fp++ != '\n') - ; - continue; - } - - name = fp; - - while (fp < efp && *fp != '=' && *fp != '\n') - fp++; - if (fp >= efp) - break; - if (*fp == '\n') { - fp++; - continue; - } - *fp++ = '\0'; - - value = fp; - - while (fp < efp && *fp != '\n') - fp++; - if (fp[-1] == '\r') - fp[-1] = '\0'; - *fp++ = '\0'; /* ok if we go off the end here */ - - if ((*cback)(name, value) == 0) - return (0); - - } while (fp < efp); - - return (1); -} diff --git a/board/hymod/flash.c b/board/hymod/flash.c deleted file mode 100644 index ad0a229..0000000 --- a/board/hymod/flash.c +++ /dev/null @@ -1,506 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00 - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/*----------------------------------------------------------------------- - */ - -/* - * probe for flash bank at address "base" and store info about it - * in the flash_info entry "fip". Fatal error if nothing there. - */ -static void -bank_probe (flash_info_t *fip, volatile bank_addr_t base) -{ - volatile bank_addr_t addr; - bank_word_t word; - int i; - - /* reset the flash */ - *base = BANK_CMD_RST; - - /* put flash into read id mode */ - *base = BANK_CMD_RD_ID; - - /* check the manufacturer id - must be intel */ - word = *BANK_REG_MAN_CODE (base); - if (word != BANK_FILL_WORD (INTEL_MANUFACT&0xff)) - panic ("\nbad manufacturer's code (0x%08lx) at addr 0x%08lx", - (unsigned long)word, (unsigned long)base); - - /* check the device id */ - word = *BANK_REG_DEV_CODE (base); - switch (word) { - - case BANK_FILL_WORD (INTEL_ID_28F320J5&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J5; - fip->sector_count = 32; - break; - - case BANK_FILL_WORD (INTEL_ID_28F640J5&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J5; - fip->sector_count = 64; - break; - - case BANK_FILL_WORD (INTEL_ID_28F320J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J3A; - fip->sector_count = 32; - break; - - case BANK_FILL_WORD (INTEL_ID_28F640J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J3A; - fip->sector_count = 64; - break; - - case BANK_FILL_WORD (INTEL_ID_28F128J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F128J3A; - fip->sector_count = 128; - break; - - default: - panic ("\nbad device code (0x%08lx) at addr 0x%08lx", - (unsigned long)word, (unsigned long)base); - } - - if (fip->sector_count >= CFG_MAX_FLASH_SECT) - panic ("\ntoo many sectors (%d) in flash at address 0x%08lx", - fip->sector_count, (unsigned long)base); - - addr = base; - for (i = 0; i < fip->sector_count; i++) { - fip->start[i] = (unsigned long)addr; - fip->protect[i] = 0; - addr = BANK_ADDR_NEXT_BLK (addr); - } - - fip->size = (bank_size_t)addr - (bank_size_t)base; - - /* reset the flash */ - *base = BANK_CMD_RST; -} - -static void -bank_reset (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - -#ifdef FLASH_DEBUG - printf ("writing reset cmd to addr 0x%08lx\n", (unsigned long)addr); -#endif - - *addr = BANK_CMD_RST; -} - -static void -bank_erase_init (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - int flag; - -#ifdef FLASH_DEBUG - printf ("erasing sector %d, addr = 0x%08lx\n", - sect, (unsigned long)addr); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts (); - -#ifdef FLASH_DEBUG - printf ("writing erase cmd to addr 0x%08lx\n", (unsigned long)addr); -#endif - *addr = BANK_CMD_ERASE1; - *addr = BANK_CMD_ERASE2; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); -} - -static int -bank_erase_poll (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - bank_word_t stat = *addr; - -#ifdef FLASH_DEBUG - printf ("checking status at addr 0x%08lx [0x%08lx]\n", - (unsigned long)addr, (unsigned long)stat); -#endif - - if ((stat & BANK_STAT_RDY) == BANK_STAT_RDY) { - if ((stat & BANK_STAT_ERR) != 0) { - printf ("failed on sector %d [0x%08lx] at " - "address 0x%08lx\n", sect, - (unsigned long)stat, (unsigned long)addr); - *addr = BANK_CMD_CLR_STAT; - return (-1); - } - else - return (1); - } - else - return (0); -} - -static int -bank_write_word (volatile bank_addr_t addr, bank_word_t value) -{ - bank_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = BANK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); - - if ((stat & BANK_STAT_ERR) != 0) { - printf ("flash program failed [0x%08lx] at address 0x%08lx\n", - (unsigned long)stat, (unsigned long)addr); - *addr = BANK_CMD_CLR_STAT; - retval = 3; - } - -done: - /* reset to read mode */ - *addr = BANK_CMD_RST; - - return (retval); -} - -/*----------------------------------------------------------------------- - */ - -unsigned long -flash_init (void) -{ - int i; - - /* Init: no FLASHes known */ - for (i=0; iflash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J5: printf ("28F320J5 (32 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F640J5: printf ("28F640J5 (64 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F320J3A: printf ("28F320J3A (32 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F128J3A: printf ("28F320J3A (128 Mbit, 2 x 16bit)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -/*----------------------------------------------------------------------- - */ - -int -flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - int rcode = 0; - -#ifdef FLASH_DEBUG - printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info (info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sector%s will not be erased\n", - prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - bank_erase_init (info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer (start); - - do { - now = get_timer (start); - - if (now - estart > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - rcode = 1; - break; - } - -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = bank_erase_poll (info, sect); - - if (sectdone < 0) { - haderr = 1; - rcode = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) - printf (" failed\n"); - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - bank_reset (info, sect); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - Program failed - */ -static int -write_word (flash_info_t *info, ulong dest, ulong data) -{ - /* Check if Flash is (sufficiently) erased */ - if ((*(ulong *)dest & data) != data) - return (2); - - return (bank_write_word ((bank_addr_t)dest, (bank_word_t)data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - Program failed - */ - -int -write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/hymod/flash.h b/board/hymod/flash.h deleted file mode 100644 index ee047fe..0000000 --- a/board/hymod/flash.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen, CSIRO-MIT, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ - -/* Commands */ -#define ISF_CMD_RST 0xFF /* reset flash */ -#define ISF_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define ISF_CMD_RD_QUERY 0x98 /* read device capabilities */ -#define ISF_CMD_RD_STAT 0x70 /* read the status register */ -#define ISF_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define ISF_CMD_WR_BUF 0xE8 /* clear the staus register */ -#define ISF_CMD_PROG 0x40 /* program word command */ -#define ISF_CMD_ERASE1 0x20 /* 1st word for block erase */ -#define ISF_CMD_ERASE2 0xD0 /* 2nd word for block erase */ -#define ISF_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ -#define ISF_CMD_LOCK 0x60 /* 1st word for all lock cmds */ -#define ISF_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ -#define ISF_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ -#define ISF_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ - -/* status register bits */ -#define ISF_STAT_DPS 0x02 /* Device Protect Status */ -#define ISF_STAT_VPPS 0x08 /* VPP Status */ -#define ISF_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ -#define ISF_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ -#define ISF_STAT_ESS 0x40 /* Erase Suspend Status */ -#define ISF_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ - -#define ISF_STAT_ERR (ISF_STAT_VPPS | ISF_STAT_DPS | \ - ISF_STAT_ECLBS | ISF_STAT_PSLBS) - -/* register addresses, valid only following an ISF_CMD_RD_ID command */ -#define ISF_REG_MAN_CODE 0x00 /* manufacturer code */ -#define ISF_REG_DEV_CODE 0x01 /* device code */ -#define ISF_REG_BLK_LCK 0x02 /* block lock configuration */ -#define ISF_REG_MST_LCK 0x03 /* master lock configuration */ - -/********************** DEFINES for Hymod Flash ******************************/ - -/* - * this code requires that the flash on any Hymod board appear as a bank - * of two (identical) 16bit Intel StrataFlash chips with 64Kword erase - * sectors (or blocks), running in x16 bit mode and connected side-by-side - * to make a 32-bit wide bus. - */ - -typedef unsigned long bank_word_t; -typedef bank_word_t bank_blk_t[64 * 1024]; - -#define BANK_FILL_WORD(b) (((bank_word_t)(b) << 16) | (bank_word_t)(b)) - -#ifdef EXAMPLE - -/* theoretically the following examples should also work */ - -/* one flash chip in x8 mode with 128Kword sectors and 8bit bus */ -typedef unsigned char bank_word_t; -typedef bank_word_t bank_blk_t[128 * 1024]; -#define BANK_FILL_WORD(b) ((bank_word_t)(b)) - -/* four flash chips in x16 mode with 32Kword sectors and 64bit bus */ -typedef unsigned long long bank_word_t; -typedef bank_word_t bank_blk_t[32 * 1024]; -#define BANK_FILL_WORD(b) ( \ - ((bank_word_t)(b) << 48) \ - ((bank_word_t)(b) << 32) \ - ((bank_word_t)(b) << 16) \ - ((bank_word_t)(b) << 0) \ - ) - -#endif /* EXAMPLE */ - -/* the sizes of these two types should probably be the same */ -typedef bank_word_t *bank_addr_t; -typedef unsigned long bank_size_t; - -/* align bank addresses and sizes to bank word boundaries */ -#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(sizeof (bank_word_t) - 1))) -#define BANK_SIZE_WORD_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_word_t) - 1) \ - & ~(sizeof (bank_word_t) - 1)) - -/* align bank addresses and sizes to bank block boundaries */ -#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(sizeof (bank_blk_t) - 1))) -#define BANK_SIZE_BLK_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_blk_t) - 1) \ - & ~(sizeof (bank_blk_t) - 1)) - -/* add an offset to a bank address */ -#define BANK_ADDR_OFFSET(a, o) ((bank_addr_t)((bank_size_t)(a) + \ - (bank_size_t)(o))) - -/* adjust a bank address to start of next word, block or bank */ -#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ - sizeof (bank_word_t)) -#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ - sizeof (bank_blk_t)) - -/* get bank address of register r given a bank base address a and block num b */ -#define BANK_ADDR_REG(a, b, r) BANK_ADDR_OFFSET(BANK_ADDR_OFFSET((a), \ - (bank_size_t)(b) * sizeof (bank_blk_t)), \ - (bank_size_t)(r) * sizeof (bank_word_t)) - -/* make a bank word value for each StrataFlash value */ - -/* Commands */ -#define BANK_CMD_RST BANK_FILL_WORD(ISF_CMD_RST) -#define BANK_CMD_RD_ID BANK_FILL_WORD(ISF_CMD_RD_ID) -#define BANK_CMD_RD_STAT BANK_FILL_WORD(ISF_CMD_RD_STAT) -#define BANK_CMD_CLR_STAT BANK_FILL_WORD(ISF_CMD_CLR_STAT) -#define BANK_CMD_ERASE1 BANK_FILL_WORD(ISF_CMD_ERASE1) -#define BANK_CMD_ERASE2 BANK_FILL_WORD(ISF_CMD_ERASE2) -#define BANK_CMD_PROG BANK_FILL_WORD(ISF_CMD_PROG) -#define BANK_CMD_LOCK BANK_FILL_WORD(ISF_CMD_LOCK) -#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(ISF_CMD_SET_LOCK_BLK) -#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(ISF_CMD_SET_LOCK_MSTR) -#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(ISF_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define BANK_STAT_DPS BANK_FILL_WORD(ISF_STAT_DPS) -#define BANK_STAT_PSS BANK_FILL_WORD(ISF_STAT_PSS) -#define BANK_STAT_VPPS BANK_FILL_WORD(ISF_STAT_VPPS) -#define BANK_STAT_PSLBS BANK_FILL_WORD(ISF_STAT_PSLBS) -#define BANK_STAT_ECLBS BANK_FILL_WORD(ISF_STAT_ECLBS) -#define BANK_STAT_ESS BANK_FILL_WORD(ISF_STAT_ESS) -#define BANK_STAT_RDY BANK_FILL_WORD(ISF_STAT_RDY) - -#define BANK_STAT_ERR BANK_FILL_WORD(ISF_STAT_ERR) - -/* make a bank register address for each StrataFlash register address */ - -#define BANK_REG_MAN_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_MAN_CODE) -#define BANK_REG_DEV_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_DEV_CODE) -#define BANK_REG_BLK_LCK(a, b) BANK_ADDR_REG((a), (b), ISF_REG_BLK_LCK) -#define BANK_REG_MST_LCK(a) BANK_ADDR_REG((a), 0, ISF_REG_MST_LCK) diff --git a/board/hymod/global_env b/board/hymod/global_env deleted file mode 100644 index f61d080..0000000 --- a/board/hymod/global_env +++ /dev/null @@ -1,161 +0,0 @@ -# DONT FORGET TO CHANGE THE "version" VAR BELOW IF YOU MAKE CHANGES TO THIS FILE - -# (C) Copyright 2001 -# Murray Jensen, CSIRO-MIT, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -# -# global_env -# -# file used by Hymod boards to initialise the u-boot non-volatile -# environment when u-boot is first run (it determines this by the -# absence of the environment variable "global_env_loaded") -# -# format of this file is: -# -# 1. blank lines and lines beginning with '#' are ignored -# 2. all other lines must have the form = -# 3. if a percent appears anywhere, it is replaced like so: -# -# %s serial number of the main board (10 digit zero filled) -# %S serial number of the main board (plain number) -# %% a percentage character -# ... otherwise the %x is discarded -# -# if first character in is a dash ('-'), then an existing env var -# will not be overwritten (the dash is removed). i.e. it is only set if -# it does not exist -# -# if last character in is a plus ('+'), then will be appended -# to any existing env var (the plus is ignored). Duplicates of are -# removed. -# -# similarly, if the last character in is a minus ('-'), then any -# occurences of in the current value of will removed (the -# minus is ignored). -# -# leading and trailing whitespace is removed in both and -# (after processing any initial or final plus/minus in ). -# - -# MISCELLANEOUS PARAMETERS - -# version must always come first -version=4 - -# set the ip address based on the main board serial number -ipaddr=192.168.1.%S -serverip=192.168.1.254 - -# stop auto execute after tftp (not a very good name really) -autostart=no - -# setting this to "yes" forces the global_env file to be loaded and processed -# if the current version is different to the version in the file -always_check_env=no - -# BOOTING COMMANDS AND PARAMETERS - -# command to run when "auto-booting" -bootcmd=bootm 40080000 - -# how long the "countdown" to automatically running "bootcmd" is -bootdelay=2 - -# how long before it "times out" console input and attempts to run "bootcmd" -bootretry=5 - -# arguments passed to the boot program (i.e. linux kernel) via register 6 -# the linux kernel (v2.4) uses the following registers: -# r3 - address of board information structure -# r4 - address of initial ramdisk image (0 means no initrd) -# r5 - size of initial ramdisk image -# r6 - address of command line string --bootargs=root=/dev/mtdblock5 rootfstype=squashfs ro - -# these four are for hymod linux integrated into our Sun network -bootargs+=serialno=%S -bootargs+=nisclient nisdomain=mlb.dmt.csiro.au nissrvadr=138.194.112.4 -bootargs+=nfsclient -bootargs+=automount - -# start a web server by default -bootargs+=webserver - -# give negotiation time to finish -bootargs+=netsleep=5 - -# then our ciscos don't pass packets for 25-30 secs after that, so -# pinging the server until it responds prevents network connections -# from failing... -bootargs+=netping - -# these are old bootargs - we don't need them anymore -bootargs-=preload=unix,i2c-cpm,i2c-dev -bootargs-=ramdisk_size=32768 -bootargs-=ramdisk_size=24576 - -# FLASH MANIPULATION COMMANDS - -# -# 16M flash, 64 x 256K sectors, mapped at address 0x40000000 -# -# Sector(s) Address Size Description -# -# 0 - 0 0x40000000 256K boot code -# 1 - 1 0x40040000 256K non volatile environment -# 2 - 4 0x40080000 768K linux kernel image -# 5 - 7 0x40140000 768K alternate linux kernel image -# 8 - 47 0x40200000 10M linux initial ramdisk image -# 48 - 63 0x40c00000 4M ramdisk image for applications -# - -fetchboot=tftp 100000 /hymod/u-boot.bin -eraseboot=protect off 1:0 ; erase 1:0 ; protect on 1:0 -copyboot=protect off 1:0 ; cp.b 100000 40000000 40000 ; protect on 1:0 -cmpboot=cmp.b 100000 40000000 40000 -newboot=run fetchboot eraseboot copyboot cmpboot - -fetchlinux=tftp 100000 /hymod/linux.bin -eraselinux=erase 1:2-4 -copylinux=cp.b 100000 40080000 ${filesize} -cmplinux=cmp.b 100000 40080000 ${filesize} -newlinux=run fetchlinux eraselinux copylinux cmplinux - -fetchaltlinux=tftp 100000 /hymod/altlinux.bin -erasealtlinux=erase 1:5-7 -copyaltlinux=cp.b 100000 40140000 ${filesize} -cmpaltlinux=cmp.b 100000 40140000 ${filesize} -newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux - -fetchroot=tftp 100000 /hymod/root.bin -eraseroot=erase 1:8-47 -copyroot=cp.b 100000 40200000 ${filesize} -cmproot=cmp.b 100000 40200000 ${filesize} -newroot=run fetchroot eraseroot copyroot cmproot - -fetchard=tftp 100000 /hymod/apprd.bin -eraseard=erase 1:48-63 -copyard=cp.b 100000 40c00000 ${filesize} -cmpard=cmp.b 100000 40c00000 ${filesize} -newapprd=run fetchard eraseard copyard cmpard - -# pass above map to linux mtd driver -bootargs+=mtdparts=phys:256k(u-boot),256k(u-boot-env),768k(linux),768k(altlinux),10m(root),4m(hymod) diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c deleted file mode 100644 index dea0a70..0000000 --- a/board/hymod/hymod.c +++ /dev/null @@ -1,537 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00 - */ - -#include -#include -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -/* imports from eeprom.c */ -extern int hymod_eeprom_read (int, hymod_eeprom_t *); -extern void hymod_eeprom_print (hymod_eeprom_t *); - -/* imports from env.c */ -extern void hymod_check_env (void); - -/* ------------------------------------------------------------------------- */ - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 1, 0, 0, 0 }, /* PA31: FCC1 MII COL */ - { 1, 1, 1, 0, 0, 0 }, /* PA30: FCC1 MII CRS */ - { 1, 1, 1, 1, 0, 0 }, /* PA29: FCC1 MII TX_ER */ - { 1, 1, 1, 1, 0, 0 }, /* PA28: FCC1 MII TX_EN */ - { 1, 1, 1, 0, 0, 0 }, /* PA27: FCC1 MII RX_DV */ - { 1, 1, 1, 0, 0, 0 }, /* PA26: FCC1 MII RX_ER */ - { 1, 0, 0, 1, 0, 0 }, /* PA25: FCC2 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA24: FCC2 MII MDC */ - { 1, 0, 0, 1, 0, 0 }, /* PA23: FCC3 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA22: FCC3 MII MDC */ - { 1, 1, 0, 1, 0, 0 }, /* PA21: FCC1 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PA20: FCC1 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PA19: FCC1 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PA18: FCC1 MII TxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PA17: FCC1 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PA16: FCC1 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PA15: FCC1 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PA14: FCC1 MII RxD[0] */ - { 1, 0, 0, 1, 0, 0 }, /* PA13: FCC1 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA12: FCC1 MII MDC */ - { 1, 0, 0, 1, 0, 0 }, /* PA11: SEL_CD */ - { 1, 0, 0, 0, 0, 0 }, /* PA10: FLASH STS1 */ - { 1, 0, 0, 0, 0, 0 }, /* PA09: FLASH STS0 */ - { 1, 0, 0, 0, 0, 0 }, /* PA08: FLASH ~PE */ - { 1, 0, 0, 0, 0, 0 }, /* PA07: WATCH ~HRESET */ - { 1, 0, 0, 0, 1, 0 }, /* PA06: VC DONE */ - { 1, 0, 0, 1, 1, 0 }, /* PA05: VC INIT */ - { 1, 0, 0, 1, 0, 0 }, /* PA04: VC ~PROG */ - { 1, 0, 0, 1, 0, 0 }, /* PA03: VM ENABLE */ - { 1, 0, 0, 0, 1, 0 }, /* PA02: VM DONE */ - { 1, 0, 0, 1, 1, 0 }, /* PA01: VM INIT */ - { 1, 0, 0, 1, 0, 0 } /* PA00: VM ~PROG */ - }, - - /* Port B configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 0, 1, 0, 0 }, /* PB31: FCC2 MII TX_ER */ - { 1, 1, 0, 0, 0, 0 }, /* PB30: FCC2 MII RX_DV */ - { 1, 1, 1, 1, 0, 0 }, /* PB29: FCC2 MII TX_EN */ - { 1, 1, 0, 0, 0, 0 }, /* PB28: FCC2 MII RX_ER */ - { 1, 1, 0, 0, 0, 0 }, /* PB27: FCC2 MII COL */ - { 1, 1, 0, 0, 0, 0 }, /* PB26: FCC2 MII CRS */ - { 1, 1, 0, 1, 0, 0 }, /* PB25: FCC2 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PB24: FCC2 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PB23: FCC2 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PB22: FCC2 MII TxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PB21: FCC2 MII RxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PB20: FCC2 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PB19: FCC2 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PB18: FCC2 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PB17: FCC3 MII RX_DV */ - { 1, 1, 0, 0, 0, 0 }, /* PB16: FCC3 MII RX_ER */ - { 1, 1, 0, 1, 0, 0 }, /* PB15: FCC3 MII TX_ER */ - { 1, 1, 0, 1, 0, 0 }, /* PB14: FCC3 MII TX_EN */ - { 1, 1, 0, 0, 0, 0 }, /* PB13: FCC3 MII COL */ - { 1, 1, 0, 0, 0, 0 }, /* PB12: FCC3 MII CRS */ - { 1, 1, 0, 0, 0, 0 }, /* PB11: FCC3 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PB10: FCC3 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PB09: FCC3 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PB08: FCC3 MII RxD[0] */ - { 1, 1, 0, 1, 0, 0 }, /* PB07: FCC3 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PB06: FCC3 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PB05: FCC3 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PB04: FCC3 MII TxD[0] */ - { 0, 0, 0, 0, 0, 0 }, /* PB03: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PB02: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PB01: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 } /* PB00: pin doesn't exist */ - }, - - /* Port C configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 0, 0, 0, 0, 0 }, /* PC31: MEZ ~IACK */ - { 0, 0, 0, 0, 0, 0 }, /* PC30: ? */ - { 1, 1, 0, 0, 0, 0 }, /* PC29: CLK SCCx */ - { 1, 1, 0, 0, 0, 0 }, /* PC28: CLK4 */ - { 1, 1, 0, 0, 0, 0 }, /* PC27: CLK SCCF */ - { 1, 1, 0, 0, 0, 0 }, /* PC26: CLK 32K */ - { 1, 1, 0, 0, 0, 0 }, /* PC25: BRG4/CLK7 */ - { 0, 0, 0, 0, 0, 0 }, /* PC24: ? */ - { 1, 1, 0, 0, 0, 0 }, /* PC23: CLK SCCx */ - { 1, 1, 0, 0, 0, 0 }, /* PC22: FCC1 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC21: FCC1 MII TX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC20: CLK SCCF */ - { 1, 1, 0, 0, 0, 0 }, /* PC19: FCC2 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC18: FCC2 MII TX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC17: FCC3 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC16: FCC3 MII TX_CLK */ - { 1, 0, 0, 0, 0, 0 }, /* PC15: SCC1 UART ~CTS */ - { 1, 0, 0, 0, 0, 0 }, /* PC14: SCC1 UART ~CD */ - { 1, 0, 0, 0, 0, 0 }, /* PC13: SCC2 UART ~CTS */ - { 1, 0, 0, 0, 0, 0 }, /* PC12: SCC2 UART ~CD */ - { 1, 0, 0, 1, 0, 0 }, /* PC11: SCC1 UART ~DTR */ - { 1, 0, 0, 1, 0, 0 }, /* PC10: SCC1 UART ~DSR */ - { 1, 0, 0, 1, 0, 0 }, /* PC09: SCC2 UART ~DTR */ - { 1, 0, 0, 1, 0, 0 }, /* PC08: SCC2 UART ~DSR */ - { 1, 0, 0, 0, 0, 0 }, /* PC07: TEMP ~ALERT */ - { 1, 0, 0, 0, 0, 0 }, /* PC06: FCC3 INT */ - { 1, 0, 0, 0, 0, 0 }, /* PC05: FCC2 INT */ - { 1, 0, 0, 0, 0, 0 }, /* PC04: FCC1 INT */ - { 0, 1, 1, 1, 0, 0 }, /* PC03: SDMA IDMA2 ~DACK */ - { 0, 1, 1, 0, 0, 0 }, /* PC02: SDMA IDMA2 ~DONE */ - { 0, 1, 0, 0, 0, 0 }, /* PC01: SDMA IDMA2 ~DREQ */ - { 1, 1, 0, 1, 0, 0 } /* PC00: BRG7 */ - }, - - /* Port D configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 0, 0, 0, 0 }, /* PD31: SCC1 UART RxD */ - { 1, 1, 1, 1, 0, 0 }, /* PD30: SCC1 UART TxD */ - { 1, 0, 0, 1, 0, 0 }, /* PD29: SCC1 UART ~RTS */ - { 1, 1, 0, 0, 0, 0 }, /* PD28: SCC2 UART RxD */ - { 1, 1, 0, 1, 0, 0 }, /* PD27: SCC2 UART TxD */ - { 1, 0, 0, 1, 0, 0 }, /* PD26: SCC2 UART ~RTS */ - { 1, 0, 0, 0, 0, 0 }, /* PD25: SCC1 UART ~RI */ - { 1, 0, 0, 0, 0, 0 }, /* PD24: SCC2 UART ~RI */ - { 1, 0, 0, 1, 0, 0 }, /* PD23: CLKGEN PD */ - { 1, 0, 0, 0, 0, 0 }, /* PD22: USER3 */ - { 1, 0, 0, 0, 0, 0 }, /* PD21: USER2 */ - { 1, 0, 0, 0, 0, 0 }, /* PD20: USER1 */ - { 1, 1, 1, 0, 0, 0 }, /* PD19: SPI ~SEL */ - { 1, 1, 1, 0, 0, 0 }, /* PD18: SPI CLK */ - { 1, 1, 1, 0, 0, 0 }, /* PD17: SPI MOSI */ - { 1, 1, 1, 0, 0, 0 }, /* PD16: SPI MISO */ - { 1, 1, 1, 0, 1, 0 }, /* PD15: I2C SDA */ - { 1, 1, 1, 0, 1, 0 }, /* PD14: I2C SCL */ - { 1, 0, 0, 1, 0, 1 }, /* PD13: TEMP ~STDBY */ - { 1, 0, 0, 1, 0, 1 }, /* PD12: FCC3 ~RESET */ - { 1, 0, 0, 1, 0, 1 }, /* PD11: FCC2 ~RESET */ - { 1, 0, 0, 1, 0, 1 }, /* PD10: FCC1 ~RESET */ - { 1, 0, 0, 0, 0, 0 }, /* PD09: PD9 */ - { 1, 0, 0, 0, 0, 0 }, /* PD08: PD8 */ - { 1, 0, 0, 1, 0, 1 }, /* PD07: PD7 */ - { 1, 0, 0, 1, 0, 1 }, /* PD06: PD6 */ - { 1, 0, 0, 1, 0, 1 }, /* PD05: PD5 */ - { 1, 0, 0, 1, 0, 1 }, /* PD04: PD4 */ - { 0, 0, 0, 0, 0, 0 }, /* PD03: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PD02: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PD01: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 } /* PD00: pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * AMI FS6377 Clock Generator configuration table - * - * the "fs6377_regs[]" table entries correspond to FS6377 registers - * 0 - 15 (total of 16 bytes). - * - * the data is written to the FS6377 via the i2c bus using address in - * "fs6377_addr" (address is 7 bits - R/W bit not included). - * - * The fs6377 has four clock outputs: A, B, C and D. - * - * Outputs C and D can each provide two different clock outputs C1/D1 or - * C2/D2 depending on the state of the SEL_CD input which is connected to - * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0) - * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2. - * - * PA11 defaults to output low (or 0) in the i/o port config table above. - * - * Output A provides a 100MHz for the High Speed Serial chips. Output B - * provides a 3.6864MHz clock for more accurate asynchronous serial bit - * rates. Output C is routed to the mezzanine connector but is currently - * unused - both C1 and C2 are set to 16MHz. Output D is used by both the - * alt-input and display mezzanine boards for their video chips. The - * alt-input board requires a clock of 24.576MHz and this is available on - * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this - * is available on D2 (PA11=SEL_CD=1). - * - * So the default is a clock suitable for the alt-input board. PA11 is toggled - * later in misc_init_r(), if a display board is detected. - */ - -uchar fs6377_addr = 0x5c; - -uchar fs6377_regs[16] = { - 12, 75, 64, 25, 144, 128, 25, 192, - 0, 16, 135, 192, 224, 64, 64, 192 -}; - -/* ------------------------------------------------------------------------- */ - -/* - * special board initialisation, after clocks and timebase have been - * set up but before environment and serial are initialised. - * - * added so that very early initialisations can be done using the i2c - * driver (which requires the clocks, to calculate the dividers, and - * the timebase, for udelay()) - */ - -int -board_postclk_init (void) -{ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - - /* - * Initialise the FS6377 clock chip - * - * the secondary address is the register number from where to - * start the write - I want to write all the registers - * - * don't bother checking return status - we have no console yet - * to print it on, nor any RAM to store it in - it will be obvious - * if this doesn't work - */ - (void) i2c_write (fs6377_addr, 0, 1, fs6377_regs, - sizeof (fs6377_regs)); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: Hardwired to HYMOD - */ - -int -checkboard (void) -{ - puts ("Board: HYMOD\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * miscellaneous (early - while running in flash) initialisations. - */ - -#define _NOT_USED_ 0xFFFFFFFF - -uint upmb_table[] = { - /* Read Single Beat (RSS) - offset 0x00 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Read Burst (RBS) - offset 0x08 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Single Beat (WSS) - offset 0x18 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Burst (WSS) - offset 0x20 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Refresh Timer (PTS) - offset 0x30 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Exception Condition (EXS) - offset 0x3c */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -uint upmc_table[] = { - /* Read Single Beat (RSS) - offset 0x00 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Read Burst (RBS) - offset 0x08 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Single Beat (WSS) - offset 0x18 */ - 0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000, - 0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Burst (WSS) - offset 0x20 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Refresh Timer (PTS) - offset 0x30 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Exception Condition (EXS) - offset 0x3c */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -int -misc_init_f (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - printf ("UPMs: "); - - upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]); - memctl->memc_mbmr = CFG_MBMR; - - upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]); - memctl->memc_mcmr = CFG_MCMR; - - printf ("configured\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long -initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8); - ulong psdmr = CFG_PSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are conÞgured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - return (CFG_SDRAM_SIZE << 20); -} - -/* ------------------------------------------------------------------------- */ -/* miscellaneous initialisations after relocation into ram (misc_init_r) */ -/* */ -/* loads the data in the main board and mezzanine board eeproms into */ -/* the hymod configuration struct stored in the board information area. */ -/* */ -/* if the contents of either eeprom is invalid, prompts for a serial */ -/* number (and an ethernet address if required) then fetches a file */ -/* containing information to be stored in the eeprom from the tftp server */ -/* (the file name is based on the serial number and a built-in path) */ - -int -last_stage_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - int rc; - -#ifdef CONFIG_BOOT_RETRY_TIME - /* - * we use the readline () function, but we also want - * command timeout enabled - */ - init_cmd_timeout (); -#endif - - memset ((void *) cp, 0, sizeof (*cp)); - - /* set up main board config info */ - - rc = hymod_eeprom_read (0, &cp->main.eeprom); - - puts ("EEPROM:main..."); - if (rc < 0) - puts ("NOT PRESENT\n"); - else if (rc == 0) - puts ("INVALID\n"); - else { - cp->main.eeprom.valid = 1; - - printf ("OK (ver %u)\n", cp->main.eeprom.ver); - hymod_eeprom_print (&cp->main.eeprom); - - /* - * hard-wired assumption here: all hymod main boards will have - * one xilinx fpga, with the interrupt line connected to IRQ2 - * - * One day, this might be based on the board type - */ - - cp->main.xlx[0].mmap.prog.exists = 1; - cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE; - cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE; - - cp->main.xlx[0].mmap.reg.exists = 1; - cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE; - cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE; - - cp->main.xlx[0].mmap.port.exists = 1; - cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE; - cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE; - - cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT; - cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN; - cp->main.xlx[0].iopins.prog_pin.flag = 1; - cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT; - cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN; - cp->main.xlx[0].iopins.init_pin.flag = 1; - cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT; - cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN; - cp->main.xlx[0].iopins.done_pin.flag = 1; -#ifdef FPGA_MAIN_ENABLE_PORT - cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT; - cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN; - cp->main.xlx[0].iopins.enable_pin.flag = 1; -#endif - - cp->main.xlx[0].irq = FPGA_MAIN_IRQ; - } - - /* set up mezzanine board config info */ - - rc = hymod_eeprom_read (1, &cp->mezz.eeprom); - - puts ("EEPROM:mezz..."); - if (rc < 0) - puts ("NOT PRESENT\n"); - else if (rc == 0) - puts ("INVALID\n"); - else { - cp->main.eeprom.valid = 1; - - printf ("OK (ver %u)\n", cp->mezz.eeprom.ver); - hymod_eeprom_print (&cp->mezz.eeprom); - } - - cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc)); - - hymod_check_env (); - - return (0); -} - -#ifdef CONFIG_SHOW_ACTIVITY -void board_show_activity (ulong timebase) -{ -#ifdef CFG_HYMOD_DBLEDS - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile iop8260_t *iop = &immr->im_ioport; - static int shift = 0; - - if ((timestamp % CFG_HZ) == 0) { - if (++shift > 3) - shift = 0; - iop->iop_pdatd = - (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift)); - } -#endif /* CFG_HYMOD_DBLEDS */ -} - -void show_activity(int arg) -{ -} -#endif /* CONFIG_SHOW_ACTIVITY */ diff --git a/board/hymod/hymod.h b/board/hymod/hymod.h deleted file mode 100644 index 9d8d662..0000000 --- a/board/hymod/hymod.h +++ /dev/null @@ -1,322 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _HYMOD_H_ -#define _HYMOD_H_ - -#include -#ifdef CONFIG_8260 -#include -#endif - -/* - * hymod configuration data - passed by boot code via the board information - * structure (only U-Boot has support for this at the moment) - * - * there are three types of data passed up from the boot monitor. the first - * (type hymod_eeprom_t) is the eeprom data that was read off both the main - * (or mother) board and the mezzanine board (if any). this data defines how - * many Xilinx fpgas are on each board, and their types (among other things). - * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where - * in the physical address space the various Xilinx fpga access regions have - * been mapped by the boot rom. the third type of data (type xlx_iopins_t, - * one per Xilinx fpga) defines which io port pins are connected to the various - * signals required to program a Xilinx fpga. - * - * A ram/flash "bank" refers to memory controlled by the same chip select. - * - * the eeprom contents are defined as in technical note #2 - basically, - * a header, zero or more records in no particular order, and a 32 bit crc - * a record is 1 or more type bytes, a length byte and "length" bytes. - */ - -#define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */ -#define HYMOD_EEPROM_VER 1 /* eeprom contents version (0-127) */ -#define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */ - -/* eeprom header */ -typedef - struct { - unsigned char id; /* eeprom id byte */ - unsigned char :1; - unsigned char ver:7; /* eeprom contents version number */ - unsigned long len; /* total # of bytes btw hdr and crc */ - } -hymod_eehdr_t; - -/* maximum number of bytes available for eeprom data records */ -#define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \ - - sizeof (hymod_eehdr_t) \ - - sizeof (unsigned long)) - -/* eeprom data record */ -typedef - union { - struct { - unsigned char topbit:1; - unsigned char type:7; - unsigned char len; - unsigned char data[1]; /* variable length */ - } small; - struct { - unsigned short topbit:1; - unsigned short nxtbit:1; - unsigned short type:14; - unsigned short len; - unsigned char data[1]; /* variable length */ - } medium; - struct { - unsigned long topbit:1; - unsigned long nxtbit:1; - unsigned long type:30; - unsigned long len; - unsigned char data[1]; /* variable length */ - } large; - } -hymod_eerec_t; - -#define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */ -#define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */ - -/* eeprom record types */ -#define HYMOD_EEREC_SERNO 1 /* serial number */ -#define HYMOD_EEREC_DATE 2 /* date */ -#define HYMOD_EEREC_BATCH 3 /* batch id */ -#define HYMOD_EEREC_TYPE 4 /* board type */ -#define HYMOD_EEREC_REV 5 /* revision number */ -#define HYMOD_EEREC_SDRAM 6 /* sdram sizes */ -#define HYMOD_EEREC_FLASH 7 /* flash sizes */ -#define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */ -#define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */ -#define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */ -#define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */ -#define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */ -#define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */ -#define HYMOD_EEREC_CPUSPD 14 /* CPU speed */ -#define HYMOD_EEREC_BUSSPD 15 /* bus speed */ -#define HYMOD_EEREC_CPMSPD 16 /* CPM speed */ -#define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */ -#define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */ -#define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */ - -/* some dimensions */ -#define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */ -#define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */ -#define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */ -#define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */ -#define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */ - -#define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */ - -/* board types */ -#define HYMOD_BDTYPE_NONE 0 /* information not present */ -#define HYMOD_BDTYPE_IO 1 /* I/O main board */ -#define HYMOD_BDTYPE_CLP 2 /* CLP main board */ -#define HYMOD_BDTYPE_DSP 3 /* DSP main board */ -#define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */ -#define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */ -#define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */ -#define HYMOD_BDTYPE_MAX 7 /* first invalid value */ - -/* Xilinx fpga types */ -#define HYMOD_XTYP_NONE 0 /* information not present */ -#define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */ -#define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */ -#define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */ -#define HYMOD_XTYP_MAX 4 /* first invalid value */ - -/* Xilinx fpga speeds */ -#define HYMOD_XSPD_NONE 0 /* information not present */ -#define HYMOD_XSPD_SIX 1 -#define HYMOD_XSPD_SEVEN 2 -#define HYMOD_XSPD_EIGHT 3 -#define HYMOD_XSPD_MAX 4 /* first invalid value */ - -/* Xilinx fpga temperatures */ -#define HYMOD_XTMP_NONE 0 /* information not present */ -#define HYMOD_XTMP_COM 1 -#define HYMOD_XTMP_IND 2 -#define HYMOD_XTMP_MAX 3 /* first invalid value */ - -/* Xilinx fpga grades */ -#define HYMOD_XTMP_NONE 0 /* information not present */ -#define HYMOD_XTMP_NORMAL 1 -#define HYMOD_XTMP_ENGSAMP 2 -#define HYMOD_XTMP_MAX 3 /* first invalid value */ - -/* CPU types */ -#define HYMOD_CPUTYPE_NONE 0 /* information not present */ -#define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */ -#define HYMOD_CPUTYPE_MAX 2 /* first invalid value */ - -/* CPU/BUS/CPM clock speeds */ -#define HYMOD_CLKSPD_NONE 0 /* information not present */ -#define HYMOD_CLKSPD_33MHZ 1 -#define HYMOD_CLKSPD_66MHZ 2 -#define HYMOD_CLKSPD_100MHZ 3 -#define HYMOD_CLKSPD_133MHZ 4 -#define HYMOD_CLKSPD_166MHZ 5 -#define HYMOD_CLKSPD_200MHZ 6 -#define HYMOD_CLKSPD_MAX 7 /* first invalid value */ - -/* high speed serial chip types */ -#define HYMOD_HSSTYPE_NONE 0 /* information not present */ -#define HYMOD_HSSTYPE_AMCC52064 1 -#define HYMOD_HSSTYPE_MAX 2 /* first invalid value */ - -/* a date (yyyy-mm-dd) */ -typedef - struct { - unsigned short year; - unsigned char month; - unsigned char day; - } -hymod_date_t; - -/* describes a Xilinx fpga */ -typedef - struct { - unsigned char type; /* chip type */ - unsigned char speed; /* chip speed rating */ - unsigned char temp; /* chip temperature rating */ - unsigned char grade; /* chip grade */ - } -hymod_xlx_t; - -/* describes a Motorola embedded processor */ -typedef - struct { - unsigned char type; /* CPU type */ - unsigned char cpuspd; /* speed of the PowerPC core */ - unsigned char busspd; /* speed of the system and 60x bus */ - unsigned char cpmspd; /* speed of the CPM co-processor */ - } -hymod_mpc_t; - -/* info about high-speed (1Gbit) serial interface */ -typedef - struct { - unsigned char type; /* high-speed serial chip type */ - unsigned char nchin; /* number of input channels mounted */ - unsigned char nchout; /* number of output channels mounted */ - } -hymod_hss_t; - -/* - * this defines the contents of the serial eeprom that exists on every - * hymod board, including mezzanine boards (the serial eeprom will be - * faked for early development boards that don't have one) - */ - -typedef - struct { - unsigned char valid:1; /* contents of this struct is valid */ - unsigned char ver:7; /* eeprom contents version */ - unsigned char bdtype; /* board type */ - unsigned char bdrev; /* board revision */ - unsigned char batchlen; /* length of batch string below */ - unsigned long serno; /* serial number */ - hymod_date_t date; /* manufacture date */ - unsigned char batch[32]; /* manufacturer specific batch id */ - unsigned char nsdram; /* # of ram "banks" */ - unsigned char nflash; /* # of flash "banks" */ - unsigned char nzbt; /* # of ZBT rams */ - unsigned char nxlx; /* # of Xilinx fpgas */ - unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */ - unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */ - unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */ - hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */ - hymod_mpc_t mpc; /* Motorola MPC CPU info */ - hymod_hss_t hss; /* high-speed serial info */ - } -hymod_eeprom_t; - -/* - * this defines a region in the processor's physical address space - */ -typedef - struct { - unsigned long exists:1; /* 1 if the region exists, 0 if not */ - unsigned long size:31; /* size in bytes */ - unsigned long base; /* base address */ - } -xlx_prgn_t; - -/* - * this defines where the various Xilinx fpga access regions are mapped - * into the physical address space of the processor - */ -typedef - struct { - xlx_prgn_t prog; /* program access region */ - xlx_prgn_t reg; /* register access region */ - xlx_prgn_t port; /* port access region */ - } -xlx_mmap_t; - -/* - * this defines which 8260 i/o port pins are connected to the various - * signals required for programming a Xilinx fpga - */ -typedef - struct { - iopin_t prog_pin; /* assert for >= 300ns to program */ - iopin_t init_pin; /* goes high when fpga is cleared */ - iopin_t done_pin; /* goes high when program is done */ - iopin_t enable_pin; /* some fpgas need enabling */ - } -xlx_iopins_t; - -/* all info about one Xilinx chip */ -typedef - struct { - xlx_mmap_t mmap; - xlx_iopins_t iopins; - unsigned long irq:8; /* h/w intr req number for this fpga */ - } -xlx_info_t; - -/* all info about one hymod board */ -typedef - struct { - hymod_eeprom_t eeprom; - xlx_info_t xlx[HYMOD_MAX_XLX]; - } -hymod_board_t; - -/* - * this defines the configuration information of a hymod board-set - * (main board + possible mezzanine board). In future, there may be - * more than one mezzanine board (stackable?) - if so, add a "mezz2" - * field, and so on... or make mezz an array? - */ -typedef - struct { - unsigned long ver:8; /* version control */ - hymod_board_t main; /* main board info */ - hymod_board_t mezz; /* mezzanine board info */ - unsigned long crc; /* ensures kernel and boot prom agree */ - } -hymod_conf_t; - -#endif /* _HYMOD_H_ */ diff --git a/board/hymod/input.c b/board/hymod/input.c deleted file mode 100644 index 63aa13c..0000000 --- a/board/hymod/input.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * (C) Copyright 2003 - * Murray Jensen, CSIRO-MIT, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* imports from common/main.c */ -extern char console_buffer[CFG_CBSIZE]; - -int -hymod_get_serno (const char *prompt) -{ - for (;;) { - int n, serno; - char *p; - -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout (); -#endif - - n = readline (prompt); - - if (n < 0) - return (n); - - if (n == 0) - continue; - - serno = (int) simple_strtol (console_buffer, &p, 10); - - if (p > console_buffer && *p == '\0' && serno > 0) - return (serno); - - printf ("Invalid number (%s) - please re-enter\n", - console_buffer); - } -} - -int -hymod_get_ethaddr (void) -{ - for (;;) { - int n; - -#ifdef CONFIG_BOOT_RETRY_TIME - reset_cmd_timeout (); -#endif - - n = readline ("Enter board ethernet address: "); - - if (n < 0) - return (n); - - if (n == 0) - continue; - - if (n == 17) { - int i; - char *p, *q; - uchar ea[6]; - - /* see if it looks like an ethernet address */ - - p = console_buffer; - - for (i = 0; i < 6; i++) { - char term = (i == 5 ? '\0' : ':'); - - ea[i] = simple_strtol (p, &q, 16); - - if ((q - p) != 2 || *q++ != term) - break; - - p = q; - } - - if (i == 6) { - /* it looks ok - set it */ - printf ("Setting ethernet addr to %s\n", - console_buffer); - - setenv ("ethaddr", console_buffer); - - puts ("Remember to do a 'saveenv' to " - "make it permanent\n"); - - return (0); - } - } - - printf ("Invalid ethernet addr (%s) - please re-enter\n", - console_buffer); - } -} diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds deleted file mode 100644 index 337a395..0000000 --- a/board/hymod/u-boot.lds +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8260/start.o (.text) -/* - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; -*/ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/environment.o (.ppcenv) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug deleted file mode 100644 index ddd4678..0000000 --- a/board/hymod/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/icecube/Makefile b/board/icecube/Makefile deleted file mode 100644 index eb5ed59..0000000 --- a/board/icecube/Makefile +++ /dev/null @@ -1,47 +0,0 @@ - -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/icecube/config.mk b/board/icecube/config.mk deleted file mode 100644 index 07b5de1..0000000 --- a/board/icecube/config.mk +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# IceCube board: -# -# Valid values for TEXT_BASE are: -# -# 0xFFF00000 boot high (standard configuration) -# 0xFF000000 boot low for 16 MiB boards -# 0xFF800000 boot low for 8 MiB boards -# 0x00100000 boot from RAM (for testing only) -# - -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -## Standard: boot high -TEXT_BASE = 0xFFF00000 -## For testing: boot from RAM -# TEXT_BASE = 0x00100000 -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/icecube/flash.c b/board/icecube/flash.c deleted file mode 100644 index 713011c..0000000 --- a/board/icecube/flash.c +++ /dev/null @@ -1,491 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned char FLASH_PORT_WIDTH; -typedef volatile unsigned char FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - extern void flash_preinit(void); - extern void flash_afterinit(ulong); - ulong flashbase = CFG_FLASH_BASE; - - flash_preinit(); - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { - memset(&flash_info[i], 0, sizeof(flash_info_t)); - - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - - size += flash_info[i].size; - flashbase += 0x800000; - } -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - - flash_afterinit(size); - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && - info->start[0] <= base && base <= info->start[0] + info->size - 1) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDLV065D: - fmt = "29LV065 (64 Mbit, uniform sectors)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - int i; - FPWV* addr2; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { - - case (FPW)AMD_ID_LV065D: - info->flash_id += FLASH_AMDLV065D; - info->sector_count = 128; - info->size = 0x00800000; - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = (ulong)addr + (i * 0x10000); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - /* test for real flash at bank 1 */ - addr2 = (FPW *)((ulong)addr | 0x800000); - if (addr2 != addr && - ((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) { - /* Seems 2 banks are the same space (8Mb chip is installed, - * J24 in default position (CS0)). Disable this (first) bank. - */ - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDLV065D: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c deleted file mode 100644 index 1f1a74c..0000000 --- a/board/icecube/icecube.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -#include "mt48lc16m16a2-75.h" -#endif - -#ifndef CFG_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. - */ - -#if defined(CONFIG_MPC5200) -long int initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CFG_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CFG_RAMBOOT */ - - return dramsize + dramsize2; -} - -#elif defined(CONFIG_MGT5100) - -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CFG_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CFG_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - -int checkboard (void) -{ -#if defined(CONFIG_MPC5200) - puts ("Board: Motorola MPC5200 (IceCube)\n"); -#elif defined(CONFIG_MGT5100) - puts ("Board: Motorola MGT5100 (IceCube)\n"); -#endif - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -void flash_afterinit(ulong size) -{ - if (size == 0x800000) { /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); - } -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) - -#define GPIO_PSC1_4 0x01000000UL - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; - /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; - /* Make a delay. MPC5200 spec says 25 usec min */ - udelay(500000); - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; - } -} -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h deleted file mode 100644 index 4c0f9a7..0000000 --- a/board/icecube/mt46v16m16-75.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 1 /* is DDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x705f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h deleted file mode 100644 index ffdf039..0000000 --- a/board/icecube/mt48lc16m16a2-75.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 0 /* is SDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/icecube/u-boot.lds b/board/icecube/u-boot.lds deleted file mode 100644 index f23432e..0000000 --- a/board/icecube/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/icu862/Makefile b/board/icu862/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/icu862/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/icu862/config.mk b/board/icu862/config.mk deleted file mode 100644 index 315e70d..0000000 --- a/board/icu862/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# ICU862 boards -# - -TEXT_BASE = 0x40F00000 -OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data diff --git a/board/icu862/flash.c b/board/icu862/flash.c deleted file mode 100644 index ca5bcf3..0000000 --- a/board/icu862/flash.c +++ /dev/null @@ -1,617 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, - size_b0 >> 20); - } - - if (FLASH_BASE1_PRELIM != 0x0) { - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: Bank 1 (0x%08lx = %ld MB)" - " > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1 >> 20, - size_b0, size_b0 >> 20); - - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - } else { - size_b1 = 0; - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[0]); -#endif - - /* ICU862 Board has only one Flash Bank */ - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); - -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM033C)) { - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00040000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: puts ("AMD "); break; - case FLASH_MAN_FUJ: puts ("FUJITSU "); break; - case FLASH_MAN_BM: puts ("BRIGHT MICRO "); break; - default: puts ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: puts ("29F040/29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: puts ("AM29LV033C (32 Mbit)\n"); - break; - default: puts ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - puts ("\n "); - } - - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - - puts ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; -#if 0 - ulong base = (ulong)addr; -#endif - uchar value; - - /* Write auto select command: read Manufacturer ID */ -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; -#endif - - value = addr[0]; - - switch (value + (value << 16)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = addr[1]; /* device ID */ - - switch ((unsigned long)value) { - case AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case AMD_ID_LV033C: - info->flash_id += FLASH_AM033C; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16Mb */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - -#if 0 - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - flash_get_offsets ((ulong)addr, &flash_info[0]); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); -#if 1 - /* We don't know why it happens, but on ICU Board * - * for AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if ( i == 32 ) { - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - } -#endif - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; -#if 0 - *addr = 0x00F000F0; /* reset bank */ -#else - *addr = 0xF0F0F0F0; /* reset bank */ -#endif - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - puts ("- missing\n"); - } else { - puts ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - puts ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - puts ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; -#endif - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); -#if 0 - addr[0] = 0x00300030; -#else - addr[0] = 0x30303030; -#endif - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); -#if 0 - while ((addr[0] & 0x00800080) != 0x00800080) -#else - while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) -#endif - { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - puts ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#if 0 - addr[0] = 0x00F000F0; /* reset bank */ -#else - addr[0] = 0xF0F0F0F0; /* reset bank */ -#endif - - puts (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; -#endif - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); -#if 0 - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) -#else - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) -#endif - { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c deleted file mode 100644 index 8da9d1c..0000000 --- a/board/icu862/icu862.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * Memory Controller Using - * - * CS0 - Flash memory (0x40000000) - * CS1 - SDRAM (0x00000000} - * CS2 - S/UNI Ultra ATM155 - * CS3 - IDT 77106 ATM25 - * CS4 - DSP HPI - * CS5 - E1/T1 Interface device - * CS6 - PCMCIA device - * CS7 - PCMCIA device - */ - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -const uint sdram_table[] = { - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* MRS initialization (offset 5) */ - - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: ICU862 Board\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size_b0 = 0; - unsigned long reg; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 1 to the SDRAM bank at - * preliminary address - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (200); - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds deleted file mode 100644 index 4bc50c5..0000000 --- a/board/icu862/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) -/* - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) -*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug deleted file mode 100644 index 87f228b..0000000 --- a/board/icu862/u-boot.lds.debug +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/ids8247/Makefile b/board/ids8247/Makefile deleted file mode 100644 index cfef750..0000000 --- a/board/ids8247/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2005 -# Heiko Schocher, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/ids8247/config.mk b/board/ids8247/config.mk deleted file mode 100644 index 136cdb8..0000000 --- a/board/ids8247/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2005 -# Heiko Schocher, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# IDS 8247 Board -# - -# This should be equal to the CFG_FLASH_BASE define in config_IDS8247.h -# for the "final" configuration, with U-Boot in flash, or the address -# in RAM where U-Boot is loaded at for debugging. -# -TEXT_BASE = 0xfff00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/ids8247/flash.c b/board/ids8247/flash.c deleted file mode 100644 index 4eba4b9..0000000 --- a/board/ids8247/flash.c +++ /dev/null @@ -1,484 +0,0 @@ -/* - * (C) Copyright 2005 - * Heiko Schocher, DENX Software Engineering, - * - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#undef DEBUG - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH8 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#elif FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#else /* FLASH_PORT_WIDTH8 */ -#define FLASH_PORT_WIDTH uchar -#define FLASH_PORT_WIDTHV vu_char -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPWV * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - volatile immap_t * immr = (immap_t *)CFG_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size ((FPW *) CFG_FLASH0_BASE, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - memctl->memc_or0 = 0xff800060; - memctl->memc_br0 = 0xff800801; - - flash_get_offsets (0xff800000, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPWV * addr, flash_info_t * info) -{ - FPW value; - - addr[0] = (FPW) 0x00900090; - - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - -#ifdef FLASH_PORT_WIDTH8 - value = addr[2]; /* device ID */ -#else - value = addr[1]; /* device ID */ -#endif - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { - case (FPW) INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - - int i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#elif defined(FLASH_PORT_WIDTH32) - wp = (addr & ~3); - port_width = 4; -#else - wp = addr; - port_width = 1; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c deleted file mode 100644 index 081ef65..0000000 --- a/board/ids8247/ids8247.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2005 - * Heiko Schocher, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ - /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ -#if defined(CONFIG_SOFT_I2C) - /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ - /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */ -#else /* normal I/O port pins */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ -#endif - /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ - /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */ - /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */ - /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */ - /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */ - /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */ - /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */ - /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */ - /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */ - /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */ - /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */ - /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */ - /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */ - /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */ -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */ -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - puts ("Board: IDS 8247\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - long psize, lsize; - - psize = 16 * 1024 * 1024; - lsize = 0; - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - -#ifndef CFG_RAMBOOT - /* 60x SDRAM setup: - */ - psize = try_init (memctl, CFG_PSDMR, CFG_OR2, - (uchar *) CFG_SDRAM_BASE); -#endif /* CFG_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_flashstart = 0xff800000; -} - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -extern ulong -nand_probe (ulong physadr); - -void -nand_init (void) -{ - ulong totlen = 0; - - debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); - totlen += nand_probe (CFG_NAND0_BASE); - - printf ("%4lu MB\n", totlen >>20); -} - -#endif /* CFG_CMD_NAND */ diff --git a/board/ids8247/u-boot.lds b/board/ids8247/u-boot.lds deleted file mode 100644 index 788aed3..0000000 --- a/board/ids8247/u-boot.lds +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2001 - * Heiko Schocher, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - common/environment.o(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/impa7/Makefile b/board/impa7/Makefile deleted file mode 100644 index 08543f9..0000000 --- a/board/impa7/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := impa7.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/impa7/config.mk b/board/impa7/config.mk deleted file mode 100644 index 417d6a8..0000000 --- a/board/impa7/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xc1780000 diff --git a/board/impa7/flash.c b/board/impa7/flash.c deleted file mode 100644 index ca76fe8..0000000 --- a/board/impa7/flash.c +++ /dev/null @@ -1,357 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define FLASH_BANK_SIZE 0x800000 -#define MAIN_SECT_SIZE 0x20000 -#define PARAM_SECT_SIZE 0x4000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F320B3T & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else if (i == 1) - flashbase = PHYS_FLASH_2; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 7) { - flash_info[i].start[j] = - flashbase + j * PARAM_SECT_SIZE; - } else { - flash_info[i].start[j] = - flashbase + (j - 7) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F320B3T & FLASH_TYPEMASK): - printf ("28F320F3B (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done:; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - - *addr = 0x00200020; /* erase setup */ - *addr = 0x00D000D0; /* erase confirm */ - - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - *addr = 0x00B000B0; /* suspend erase */ - *addr = 0x00FF00FF; /* reset to read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - - *addr = 0x00FF00FF; /* reset to read mode */ - } - printf ("ok.\n"); - } - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) dest; - ulong barf; - int rc = ERR_OK; - int flag; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* clear status register command */ - *addr = 0x00500050; - - /* program set-up command */ - *addr = 0x00400040; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* read status register command */ - *addr = 0x00700070; - - /* wait while polling the status register */ - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - /* suspend program command */ - *addr = 0x00B000B0; - goto outahere; - } - - if (*addr & 0x003A003A) { /* check for error */ - barf = *addr; - if (barf & 0x003A0000) { - barf >>= 16; - } else { - barf &= 0x0000003A; - } - printf ("\nFlash write error %02lx at address %08lx\n", barf, (unsigned long) dest); - if (barf & 0x0002) { - printf ("Block locked, not erased.\n"); - rc = ERR_NOT_ERASED; - goto outahere; - } - if (barf & 0x0010) { - printf ("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if (barf & 0x0008) { - printf ("Vpp Low error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - } - - - outahere: - /* read array command */ - *addr = 0x00FF00FF; - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((vu_long *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - return write_word (info, wp, data); -} diff --git a/board/impa7/impa7.c b/board/impa7/impa7.c deleted file mode 100644 index e496923..0000000 --- a/board/impa7/impa7.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Activate LED flasher */ - IO_LEDFLSH = 0x40; - - /* arch number of EP7111 */ - gd->bd->bi_arch_number = MACH_TYPE_EDB7211; - - /* location of boot parameters for EP7111 */ - gd->bd->bi_boot_params = 0xc0020100; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - - return (0); -} diff --git a/board/impa7/lowlevel_init.S b/board/impa7/lowlevel_init.S deleted file mode 100644 index 7ce10a2..0000000 --- a/board/impa7/lowlevel_init.S +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Memory Setup stuff - taken from ??? - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* some parameters for the board */ - -SYSCON2: .long 0x80001100 -MEMCFG1: .long 0x80000180 -MEMCFG2: .long 0x800001C0 -DRFPR: .long 0x80000200 - -syscon2_mask: .long 0x00000004 -memcfg1_val: .long 0x160c1414 -memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits -memcfg2_val: .long 0x00000000 @ upper 16 bits are reserved for CS7 + CS6 -drfpr_val: .long 0x00000081 -/* setting up the memory */ - -.globl lowlevel_init -lowlevel_init: - /* - * DRFPR - * 64kHz DRAM refresh - */ - ldr r0, DRFPR - ldr r1, drfpr_val - str r1, [r0] - - /* - * SYSCON2: clear bit 2, DRAM is 32 bits wide - */ - ldr r0, SYSCON2 - ldr r2, [r0] - ldr r1, syscon2_mask - bic r2, r2, r1 - str r2, [r0] - - /* - * MEMCFG1 - * Setting up Keyboard at CS3, 8 Bit, 3 Waitstates - * Setting up CS8900 (Ethernet) at CS2, 32 Bit, 5 Waitstates - * Setting up flash at CS0 and CS1, 32 Bit, 3 Waitstates - */ - ldr r0, MEMCFG1 - ldr r1, memcfg1_val - str r1, [r0] - - /* - * MEMCFG2 - * Setting up ? with 0 - * - */ - ldr r0, MEMCFG2 - ldr r2, [r0] - ldr r1, memcfg2_mask - bic r2, r2, r1 - ldr r1, memcfg2_val - orr r2, r2, r1 - str r2, [r0] - - /* everything is fine now */ - mov pc, lr diff --git a/board/impa7/u-boot.lds b/board/impa7/u-boot.lds deleted file mode 100644 index 1122d75..0000000 --- a/board/impa7/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm720t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/incaip/Makefile b/board/incaip/Makefile deleted file mode 100644 index d9b0e2d..0000000 --- a/board/incaip/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o -SOBJS = lowlevel_init.o - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/incaip/config.mk b/board/incaip/config.mk deleted file mode 100644 index 0cecc01..0000000 --- a/board/incaip/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# INCA-IP board with MIPS 4Kc CPU core -# - -# ROM version -TEXT_BASE = 0xB0000000 - -# RAM version -#TEXT_BASE = 0x80100000 diff --git a/board/incaip/flash.c b/board/incaip/flash.c deleted file mode 100644 index 520514d..0000000 --- a/board/incaip/flash.c +++ /dev/null @@ -1,671 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -#if 0 -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa -#else -#define FLASH_CYCLE1 0x0554 -#define FLASH_CYCLE2 0x02ab -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { - ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; - ulong * buscon = (ulong *) - ((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2); - - /* Disable write protection */ - *buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS; - -#if 1 - memset(&flash_info[i], 0, sizeof(flash_info_t)); -#endif - - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", - i, flash_info[i].size); - } - - size += flash_info[i].size; - } - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base < info->start[0] + info->size) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[1] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) { - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c deleted file mode 100644 index b5d9e00..0000000 --- a/board/incaip/incaip.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - - -extern uint incaip_get_cpuclk(void); - -static ulong max_sdram_size(void) -{ - /* The only supported SDRAM data width is 16bit. - */ -#define CFG_DW 2 - - /* The only supported number of SDRAM banks is 4. - */ -#define CFG_NB 4 - - ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; - int cols = cfgpb0 & 0xF; - int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; - - return size; -} - -long int initdram(int board_type) -{ - int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0; - ulong size, max_size = 0; - ulong our_address; - - asm volatile ("move %0, $25" : "=r" (our_address) :); - - /* Can't probe for RAM size unless we are running from Flash. - */ - if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1)) - { - return max_sdram_size(); - } - - for (cols = 0x8; cols <= 0xC; cols++) - { - for (rows = 0xB; rows <= 0xD; rows++) - { - *INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) | - (rows << 4) | cols; - size = get_ram_size((long *)CFG_SDRAM_BASE, - max_sdram_size()); - - if (size > max_size) - { - best_val = *INCA_IP_SDRAM_MC_CFGPB0; - max_size = size; - } - } - } - - *INCA_IP_SDRAM_MC_CFGPB0 = best_val; - return max_size; -} - -int checkboard (void) -{ - - unsigned long chipid = *INCA_IP_WDT_CHIPID; - int part_num; - - puts ("Board: INCA-IP "); - part_num = (chipid >> 12) & 0xffff; - switch (part_num) { - case 0xc0: - printf ("Standard Version, "); - break; - case 0xc1: - printf ("Basic Version, "); - break; - default: - printf ("Unknown Part Number 0x%x ", part_num); - break; - } - - printf ("Chip V1.%ld, ", (chipid >> 28)); - - printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000); - - return 0; -} diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S deleted file mode 100644 index 14d738a..0000000 --- a/board/incaip/lowlevel_init.S +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Memory sub-system initialization code for INCA-IP development board. - * - * Copyright (c) 2003 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - - -#define EBU_MODUL_BASE 0xB8000200 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0100(value) -#define MC_ERRADDR(value) 0x0108(value) -#define MC_IOGP(value) 0x0800(value) -#define MC_SELFRFSH(value) 0x0A00(value) -#define MC_CTRLENA(value) 0x1000(value) -#define MC_MRSCODE(value) 0x1008(value) -#define MC_CFGDW(value) 0x1010(value) -#define MC_CFGPB0(value) 0x1018(value) -#define MC_LATENCY(value) 0x1038(value) -#define MC_TREFRESH(value) 0x1040(value) - -#define CGU_MODUL_BASE 0xBF107000 -#define CGU_PLL1CR(value) 0x0008(value) -#define CGU_DIVCR(value) 0x0010(value) -#define CGU_MUXCR(value) 0x0014(value) -#define CGU_PLL1SR(value) 0x000C(value) - - .set noreorder - - -/* - * void ebu_init(long) - * - * a0 has the clock value we are going to run at - */ - .globl ebu_init - .ent ebu_init -ebu_init: -__ebu_init: - - li t1, EBU_MODUL_BASE - li t2, 0xA0000041 - sw t2, EBU_ADDSEL0(t1) - li t2, 0xA0800041 - sw t2, EBU_ADDSEL2(t1) - li t2, 0xBE0000F1 - sw t2, EBU_ADDSEL1(t1) - - li t3, 100000000 - beq a0, t3, 1f - nop - li t3, 133000000 - beq a0, t3, 2f - nop - li t3, 150000000 - beq a0, t3, 2f - nop - b 3f - nop - - /* 100 MHz */ -1: - li t2, 0x8841417D - sw t2, EBU_BUSCON0(t1) - sw t2, EBU_BUSCON2(t1) - li t2, 0x684142BD - b 3f - sw t2, EBU_BUSCON1(t1) /* delay slot */ - - /* 133 or 150 MHz */ -2: - li t2, 0x8841417E - sw t2, EBU_BUSCON0(t1) - sw t2, EBU_BUSCON2(t1) - li t2, 0x684143FD - sw t2, EBU_BUSCON1(t1) -3: - j ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: -__cgu_init: - - li t1, CGU_MODUL_BASE - - li t3, 100000000 - beq a0, t3, 1f - nop - li t3, 133000000 - beq a0, t3, 2f - nop - li t3, 150000000 - beq a0, t3, 3f - nop - b 5f - nop - - /* 100 MHz clock */ -1: - li t2, 0x80000014 - sw t2, CGU_DIVCR(t1) - li t2, 0x80000000 - sw t2, CGU_MUXCR(t1) - li t2, 0x800B0001 - b 5f - sw t2, CGU_PLL1CR(t1) /* delay slot */ - - /* 133 MHz clock */ -2: - li t2, 0x80000054 - sw t2, CGU_DIVCR(t1) - li t2, 0x80000000 - sw t2, CGU_MUXCR(t1) - li t2, 0x800B0001 - b 5f - sw t2, CGU_PLL1CR(t1) /* delay slot */ - - /* 150 MHz clock */ -3: - li t2, 0x80000017 - sw t2, CGU_DIVCR(t1) - li t2, 0xC00B0001 - sw t2, CGU_PLL1CR(t1) - li t3, 0x80000000 -4: - lw t2, CGU_PLL1SR(t1) - and t2, t2, t3 - beq t2, zero, 4b - nop - li t2, 0x80000001 - sw t2, CGU_MUXCR(t1) -5: - j ra - nop - - .end cgu_init - - -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: -__sdram_init: - - li t1, MC_MODUL_BASE - -#if 0 - /* Disable memory controller before changing any of its registers */ - sw zero, MC_CTRLENA(t1) -#endif - - li t2, 100000000 - beq a0, t2, 1f - nop - li t2, 133000000 - beq a0, t2, 2f - nop - li t2, 150000000 - beq a0, t2, 3f - nop - b 5f - nop - - /* 100 MHz clock */ -1: - /* Set clock ratio (clkrat=1:1, rddel=3) */ - li t2, 0x00000003 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 100MHz) */ - li t2, 0x0000061A - b 4f - sw t2, MC_TREFRESH(t1) - - /* 133 MHz clock */ -2: - /* Set clock ratio (clkrat=1:1, rddel=3) */ - li t2, 0x00000003 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 133MHz) */ - li t2, 0x00000822 - b 4f - sw t2, MC_TREFRESH(t1) - - /* 150 MHz clock */ -3: - /* Set clock ratio (clkrat=3:2, rddel=4) */ - li t2, 0x00000014 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 150MHz) */ - li t2, 0x00000927 - sw t2, MC_TREFRESH(t1) - -4: - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 /* CL = 2 */ - sw t2, MC_MRSCODE(t1) - - /* Set word width to 16 bit */ - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014C9 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00026325 /* BC PC100 */ - sw t2, MC_LATENCY(t1) - -5: - /* Finally enable the controller */ - li t2, 0x00000001 - sw t2, MC_CTRLENA(t1) - - j ra - nop - - .end sdram_init - - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - - /* EBU, CGU and SDRAM Initialization. - */ - li a0, CPU_CLOCK_RATE - move t0, ra - - /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init() - * modify t0 and a0. - */ - bal __cgu_init - nop - bal __ebu_init - nop - bal __sdram_init - nop - move ra, t0 - - j ra - nop - - .end lowlevel_init diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds deleted file mode 100644 index 10c9917..0000000 --- a/board/incaip/u-boot.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - _gp = ALIGN(16); - - __got_start = .; - .got : { *(.got) } - __got_end = .; - - .sdata : { *(.sdata) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) } - uboot_end = .; -} diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile deleted file mode 100644 index bf83292..0000000 --- a/board/inka4x0/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/inka4x0/config.mk b/board/inka4x0/config.mk deleted file mode 100644 index cb19a7d..0000000 --- a/board/inka4x0/config.mk +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# INKA 4X0 board: -# -# Valid values for TEXT_BASE are: -# -# 0xFFE00000 boot low -# -# 0x00100000 boot from RAM (for testing only) -# - -ifndef TEXT_BASE -## Standard: boot low -TEXT_BASE = 0xFFE00000 -## For testing: boot from RAM -#TEXT_BASE = 0x00100000 -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/inka4x0/flash.c b/board/inka4x0/flash.c deleted file mode 100644 index b138655..0000000 --- a/board/inka4x0/flash.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * CPU to flash interface is 8-bit, so make declaration accordingly - */ -typedef unsigned char FLASH_PORT_WIDTH; -typedef volatile unsigned char FLASH_PORT_WIDTHV; - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - extern void flash_preinit(void); - ulong flashbase = CFG_FLASH_BASE; - - flash_preinit(); - - /* Init: no FLASHes known */ - memset(&flash_info[0], 0, sizeof(flash_info_t)); - - flash_info[0].size = - flash_get_size((FPW *)flashbase, &flash_info[0]); - - size = flash_info[0].size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && info->start[0] <= base && - base <= info->start[0] + info->size - 1) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM116DB: - printf ("AM29LV116DB (16Mbit, bottom boot sect)\n"); - break; - case FLASH_AMLV128U: - printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - int i; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - debug ("Manufacturer: AMD (Spansion)\n"); - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - debug ("Manufacturer: Intel (not supported yet)\n"); - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { - - case (uchar)AMD_ID_LV116DB: - debug ("Chip: AM29LV116DB\n"); - info->flash_id += FLASH_AM116DB; - info->sector_count = 35; - info->size = 0x00200000; - /* - * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all - * the other ones are 64 kB - */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for( i = 4; i < info->sector_count; i++ ) - info->start[i] = - base + (i * (64 << 10)) - 0x00030000; - break; /* => 2 MB */ - - case (FPW)AMD_ID_LV160B: - debug ("Chip: AM29LV160MB\n"); - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - /* - * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all - * the other ones are 64 kB - */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for( i = 4; i < info->sector_count; i++ ) - info->start[i] = - base + (i * 2 * (64 << 10)) - 0x00060000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr = (FPWV*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = (FPW)0x00AA00AA; - addr[0x02AA] = (FPW)0x00550055; - addr[0x0555] = (FPW)0x00800080; - addr[0x0555] = (FPW)0x00AA00AA; - addr[0x02AA] = (FPW)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FPWV*)(info->start[sect]); - addr[0] = (FPW)0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FPWV*)(info->start[l_sect]); - while ((addr[0] & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FPWV*)info->start[0]; - addr[0] = (FPW)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - int i, rc = 0; - - for (i = 0; i < cnt; i++) - if ((rc = write_word_amd(info, (FPW *)(addr+i), src[i])) != 0) { - return (rc); - } - - return rc; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - return (1); - } - } - return (0); -} diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c deleted file mode 100644 index 29878f9..0000000 --- a/board/inka4x0/inka4x0.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -#include "mt48lc16m16a2-75.h" -#endif - -#ifndef CFG_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. - */ - -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ -#else /* CFG_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CFG_RAMBOOT */ - -/* return dramsize + dramsize2; */ - return dramsize; -} - -int checkboard (void) -{ - puts ("Board: INKA 4X0\n"); - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -#define GPIO_WKUP_7 0x80000000UL -#define GPIO_PSC3_9 0x04000000UL - -int misc_init_f (void) -{ - uchar tmp[10]; - int i, br; - - i = getenv_r("brightness", tmp, sizeof(tmp)); - br = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CFG_BRIGHTNESS; - if (br > 255) - br = 255; - - /* Initialize GPIO output pins. - */ - /* Configure GPT as GPIO output (and set them as they control low-active LEDs */ - *(vu_long *)MPC5XXX_GPT0_ENABLE = - *(vu_long *)MPC5XXX_GPT1_ENABLE = - *(vu_long *)MPC5XXX_GPT2_ENABLE = - *(vu_long *)MPC5XXX_GPT3_ENABLE = - *(vu_long *)MPC5XXX_GPT4_ENABLE = - *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34; - - /* Configure GPT7 as PWM timer, 1kHz, no ints. */ - *(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */ - *(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe; - *(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16); - *(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */ - - /* Configure PSC3_6,7 as GPIO output */ - *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000; - *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000; - - /* Configure PSC3_8 as GPIO output, no interrupt */ - *(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000; - *(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000; - *(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000; - - /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */ - *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000; - *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000; - - /* Set LR mirror bit because it is low-active */ - *(vu_long *)MPC5XXX_WU_GPIO_DATA |= GPIO_WKUP_7; - /* - * Reset Coral-P graphics controller - */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9; - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) - -#define GPIO_PSC1_4 0x01000000UL - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; - /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; - /* Make a delay. MPC5200 spec says 25 usec min */ - udelay(500000); - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; - } -} -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h deleted file mode 100644 index f650faa..0000000 --- a/board/inka4x0/mt46v16m16-75.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 1 /* is DDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h deleted file mode 100644 index 13a97ac..0000000 --- a/board/inka4x0/mt48lc16m16a2-75.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 1 /* is SDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ -/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ -#define SDRAM_CONFIG2 0x8AD70000 -/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/inka4x0/u-boot.lds b/board/inka4x0/u-boot.lds deleted file mode 100644 index 123a14c..0000000 --- a/board/inka4x0/u-boot.lds +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc5xxx/start.o (.text) - cpu/mpc5xxx/traps.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) - - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/innokom/Makefile b/board/innokom/Makefile deleted file mode 100644 index 73f6a74..0000000 --- a/board/innokom/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := innokom.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/innokom/config.mk b/board/innokom/config.mk deleted file mode 100644 index 2354392..0000000 --- a/board/innokom/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -# Linux-Kernel is expected to be at c000'8000, entry c000'8000 -# -# we load ourself to c170'0000, the upper 1 MB of second bank -# -# download areas is c800'0000 -# - -# This is the address where U-Boot lives in flash: -#TEXT_BASE = 0 - -# FIXME: armboot does only work correctly when being compiled -# for the addresses _after_ relocation to RAM!! Otherwhise the -# .bss segment is assumed in flash... -TEXT_BASE = 0xa1fe0000 diff --git a/board/innokom/flash.c b/board/innokom/flash.c deleted file mode 100644 index 298acc8..0000000 --- a/board/innokom/flash.c +++ /dev/null @@ -1,419 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, - * - * (C) Copyright 2002 - * Auerswald GmbH & Co KG, Germany - * Kai-Uwe Bloem - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* Debugging macros ------------------------------------------------------ */ - -#undef FLASH_DEBUG - -/* Some debug macros */ -#if (FLASH_DEBUG > 2 ) -#define PRINTK3(args...) printf(args) -#else -#define PRINTK3(args...) -#endif - -#if FLASH_DEBUG > 1 -#define PRINTK2(args...) printf(args) -#else -#define PRINTK2(args...) -#endif - -#ifdef FLASH_DEBUG -#define PRINTK(args...) printf(args) -#else -#define PRINTK(args...) -#endif - -/* ------------------------------------------------------------------------ */ - -/* Development system: we have only 16 MB Flash */ -#ifdef CONFIG_MTD_INNOKOM_16MB -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB (during development) */ -#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */ -#endif - -/* Production system: we have 64 MB Flash */ -#ifdef CONFIG_MTD_INNOKOM_64MB -#define FLASH_BANK_SIZE 0x04000000 /* 64 MB */ -#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */ -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/** - * flash_init: - initialize data structures for flash chips - * - * @return: size of the flash - */ - -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - - switch (i) { - case 0: - flashbase = PHYS_FLASH_1; - break; - default: - panic("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect u-boot sectors */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + (256*1024) - 1, - &flash_info[0]); - -#ifdef CFG_ENV_IS_IN_FLASH - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return size; -} - - -/** - * flash_print_info: - print information about the flash situation - * - * @param info: - */ - -void flash_print_info (flash_info_t *info) -{ - int i, j; - - for (j=0; jflash_id & FLASH_VENDMASK) { - - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf("Intel: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf("28F128J3 (128Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - info++; - } -} - - -/** - * flash_erase: - erase flash sectors - * - */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) prot++; - } - - if (prot) return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { - - printf("Erasing sector %2d ... ", sect); - - PRINTK("\n"); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - if (info->protect[sect] == 0) { /* not protected */ - u16 * volatile addr = (u16 * volatile)(info->start[sect]); - - PRINTK("unlocking sector\n"); - *addr = 0x0060; - *addr = 0x00d0; - *addr = 0x00ff; - - PRINTK("erasing sector\n"); - *addr = 0x0020; - PRINTK("confirming erase\n"); - *addr = 0x00D0; - - while ((*addr & 0x0080) != 0x0080) { - PRINTK("."); - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { - *addr = 0x00B0; /* suspend erase*/ - *addr = 0x00FF; /* read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - - PRINTK("clearing status register\n"); - *addr = 0x0050; - PRINTK("resetting to read mode"); - *addr = 0x00FF; - } - - printf("ok.\n"); - } - - if (ctrlc()) printf("User Interrupt!\n"); - - outahere: - - /* allow flash to settle - wait 10 ms */ - udelay_masked(10000); - - if (flag) enable_interrupts(); - - return rc; -} - - -/** - * write_word: - copy memory to flash - * - * @param info: - * @param dest: - * @param data: - * @return: - */ - -static int write_word (flash_info_t *info, ulong dest, ushort data) -{ - volatile u16 *addr = (u16 *)dest, val; - int rc = ERR_OK; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts(); - - /* clear status register command */ - *addr = 0x50; - - /* program set-up command */ - *addr = 0x40; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - /* wait while polling the status register */ - while(((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - *addr = 0xB0; /* suspend program command */ - goto outahere; - } - } - - if(val & 0x1A) { /* check for error */ - printf("\nFlash write error %02x at address %08lx\n", - (int)val, (unsigned long)dest); - if(val & (1<<3)) { - printf("Voltage range error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if(val & (1<<1)) { - printf("Device protect error.\n"); - rc = ERR_PROTECTED; - goto outahere; - } - if(val & (1<<4)) { - printf("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - - outahere: - - *addr = 0xFF; /* read array command */ - if (flag) enable_interrupts(); - - return rc; -} - - -/** - * write_buf: - Copy memory to flash. - * - * @param info: - * @param src: source of copy transaction - * @param addr: where to copy to - * @param cnt: number of bytes to copy - * - * @return error code - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 8); - } - for (; i<2 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt==0 && i<2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - /* data = *((vushort*)src); */ - data = *((ushort*)src); - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - - return write_word(info, wp, data); -} diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c deleted file mode 100644 index ae5402e..0000000 --- a/board/innokom/innokom.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de - * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net - * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -/** - * i2c_init_board - reset i2c bus. When the board is powercycled during a - * bus transfer it might hang; for details see doc/I2C_Edge_Conditions. - * The Innokom board has GPIO70 connected to SCLK which can be toggled - * until all chips think that their current cycles are finished. - */ -int i2c_init_board(void) -{ - int i, icr; - - /* disable I2C controller first, otherwhise it thinks we want to */ - /* talk to the slave port... */ - icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE); - - /* set gpio pin low _before_ we change direction to output */ - GPCR(70) = GPIO_bit(70); - - /* now toggle between output=low and high-impedance */ - for (i = 0; i < 20; i++) { - GPDR(70) |= GPIO_bit(70); /* output */ - udelay(10); - GPDR(70) &= ~GPIO_bit(70); /* input */ - udelay(10); - } - - ICR = icr; - - return 0; -} - - -/** - * misc_init_r: - misc initialisation routines - */ - -int misc_init_r(void) -{ - uchar *str; - - /* determine if the software update key is pressed during startup */ - if (GPLR0 & 0x00000800) { - printf("using bootcmd_normal (sw-update button not pressed)\n"); - str = getenv("bootcmd_normal"); - } else { - printf("using bootcmd_update (sw-update button pressed)\n"); - str = getenv("bootcmd_update"); - } - - setenv("bootcmd",str); - - return 0; -} - - -/** - * board_init: - setup some data structures - * - * @return: 0 in case of success - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - gd->bd->bi_arch_number = MACH_TYPE_INNOKOM; - gd->bd->bi_boot_params = 0xa0000100; - gd->bd->bi_baudrate = CONFIG_BAUDRATE; - - return 0; -} - - -/** - * dram_init: - setup dynamic RAM - * - * @return: 0 in case of success - */ - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - - -/** - * innokom_set_led: - switch LEDs on or off - * - * @param led: LED to switch (0,1,2) - * @param state: switch on (1) or off (0) - */ - -void innokom_set_led(int led, int state) -{ - switch(led) { -/* - case 0: if (state==1) { - GPCR0 |= CSB226_USER_LED0; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED0; - } - break; - - case 1: if (state==1) { - GPCR0 |= CSB226_USER_LED1; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED1; - } - break; - - case 2: if (state==1) { - GPCR0 |= CSB226_USER_LED2; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED2; - } - break; -*/ - } - - return; -} - - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - * The CSB226 does only have 3 LEDs, so we switch them on at the most - * important states (1, 5, 15). - */ - -void show_boot_progress (int status) -{ - switch(status) { -/* - case 1: csb226_set_led(0,1); break; - case 5: csb226_set_led(1,1); break; - case 15: csb226_set_led(2,1); break; -*/ - } - - return; -} diff --git a/board/innokom/lowlevel_init.S b/board/innokom/lowlevel_init.S deleted file mode 100644 index aa9dcba..0000000 --- a/board/innokom/lowlevel_init.S +++ /dev/null @@ -1,437 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -_TEXT_BASE: - .word TEXT_BASE - - -/* - * Memory setup - */ - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - - /* Set up GPIO pins first ----------------------------------------- */ - - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - -/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ -/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */ -/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ -/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ -/* */ -/* ldr r1, =LED_BLANK */ -/* mov r0, #0xFF */ -/* str r0, [r1] / turn on hex leds */ -/* */ -/*loop: */ -/* */ -/* ldr r0, =0xB0070001 */ -/* ldr r1, =_LED */ -/* str r0, [r1] / hex display */ - - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1, =MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - - /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ - adr r3, mem_init /* r0 <- current position of code */ - ldr r2, =mem_init - cmp r3, r2 /* skip init if in place */ - beq initirqs - - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r3, =CFG_MDREFR_VAL - ldr r2, =0xFFF - and r3, r3, r2 - ldr r4, =0x03ca4000 - orr r4, r4, r3 - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - /* FIXME: we use async mode for now */ - - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - /* Step 4a: assert MDREFR:K?RUN and configure */ - /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - - ldr r4, =CFG_MDREFR_VAL - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Step 4b: de-assert MDREFR:SLFRSH. */ - - bic r4, r4, #(MDREFR_SLFRSH) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4c: assert MDREFR:E1PIN and E0PIO */ - - orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ - /* configure but not enable each SDRAM partition pair. */ - - ldr r4, =CFG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - /* There should 9 writes, since the first write doesn't */ - /* trigger a refresh cycle on PXA250. See Intel PXA250 and */ - /* PXA210 Processors Specification Update, */ - /* Jan 2003, Errata #116, page 30. */ - - - ldr r3, =CFG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* (MDCNFG:DEx set to 1). */ - - ldr r3, [r1, #MDCNFG_OFFSET] - orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) - str r3, [r1, #MDCNFG_OFFSET] - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - - /* We are finished with Intel's memory controller initialisation */ - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - /* (hard-coding at 398.12MHz for now). */ - - /* Turn Off ALL on-chip peripheral clocks for re-configuration */ - /* Note: See label 'ENABLECLKS' for the re-enabling */ - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - - /* default value in case no valid rotary switch setting is found */ - ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ - - /* ... and write the core clock config register */ - ldr r1, =CCCR - str r2, [r1] - - /* enable the 32Khz oscillator for RTC and PowerManager */ -/* - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] -*/ - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b - - /* ---------------------------------------------------------------- */ - /* */ - /* ---------------------------------------------------------------- */ - - /* Save SDRAM size */ - ldr r1, =DRAM_SIZE - str r8, [r1] - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - - /* FIXME */ - -#ifndef DEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ -#endif - - /* ---------------------------------------------------------------- */ - /* End lowlevel_init */ - /* ---------------------------------------------------------------- */ - -endlowlevel_init: - - mov pc, lr diff --git a/board/innokom/u-boot.lds b/board/innokom/u-boot.lds deleted file mode 100644 index f010239..0000000 --- a/board/innokom/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/integratorap/Makefile b/board/integratorap/Makefile deleted file mode 100644 index 358df62..0000000 --- a/board/integratorap/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004 -# ARM Ltd. -# Philippe Robin, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := integratorap.o flash.o -SOBJS := lowlevel_init.o memsetup.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/integratorap/config.mk b/board/integratorap/config.mk deleted file mode 100644 index 25b79b3..0000000 --- a/board/integratorap/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -# -# image should be loaded at 0x01000000 -# - -TEXT_BASE = 0x01000000 diff --git a/board/integratorap/flash.c b/board/integratorap/flash.c deleted file mode 100644 index b120d63..0000000 --- a/board/integratorap/flash.c +++ /dev/null @@ -1,473 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - OrgDef *pOrgDef; - - pOrgDef = OrgIntel_28F256L18T; - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - flash_unprotect_sectors (addr); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c deleted file mode 100644 index d4f61d6..0000000 --- a/board/integratorap/integratorap.c +++ /dev/null @@ -1,651 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifdef CONFIG_PCI -#include -#endif - -void flash__init (void); -void ether__init (void); -void peripheral_power_enable (void); - -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -void show_boot_progress(int progress) -{ - printf("Boot reached stage %d\n", progress); -} -#endif - -#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* arch number of Integrator Board */ - gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - gd->flags = 0; - -#ifdef CONFIG_CM_REMAP -extern void cm_remap(void); - cm_remap(); /* remaps writeable memory to 0x00000000 */ -#endif - - icache_enable (); - - flash__init (); - return 0; -} - - -int misc_init_r (void) -{ -#ifdef CONFIG_PCI - pci_init(); -#endif - setenv("verify", "n"); - return (0); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifdef CONFIG_PCI - -#ifndef CONFIG_PCI_PNP - -static struct pci_config_table pci_integrator_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif - -/* V3 access routines */ -#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v)) -#define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o))) - -#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v)) -#define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o))) - -/* Compute address necessary to access PCI config space for the given */ -/* bus and device. */ -#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({ \ - unsigned int __address, __devicebit; \ - unsigned short __mapaddress; \ - unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \ - \ - if (__bus == 0) { \ - /* local bus segment so need a type 0 config cycle */ \ - /* build the PCI configuration "address" with one-hot in A31-A11 */ \ - __address = PCI_CONFIG_BASE; \ - __address |= ((__devfn & 0x07) << 8); \ - __address |= __offset & 0xFF; \ - __mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \ - __devicebit = (1 << (__dev + 11)); \ - \ - if ((__devicebit & 0xFF000000) != 0) { \ - /* high order bits are handled by the MAP register */ \ - __mapaddress |= (__devicebit >> 16); \ - } else { \ - /* low order bits handled directly in the address */ \ - __address |= __devicebit; \ - } \ - } else { /* bus !=0 */ \ - /* not the local bus segment so need a type 1 config cycle */ \ - /* A31-A24 are don't care (so clear to 0) */ \ - __mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \ - __address = PCI_CONFIG_BASE; \ - __address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \ - __address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \ - __address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number */ \ - __address |= __offset & 0xFF; /* bits 7..0 = register number */ \ - } \ - _V3Write16 (V3_LB_MAP1, __mapaddress); \ - __address; \ -}) - -/* _V3OpenConfigWindow - open V3 configuration window */ -#define _V3OpenConfigWindow() { \ - /* Set up base0 to see all 512Mbytes of memory space (not */ \ - /* prefetchable), this frees up base1 for re-use by configuration*/ \ - /* memory */ \ - \ - _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \ - 0x90 | V3_LB_BASE_M_ENABLE)); \ - /* Set up base1 to point into configuration space, note that MAP1 */ \ - /* register is set up by pciMakeConfigAddress(). */ \ - \ - _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \ - 0x40 | V3_LB_BASE_M_ENABLE)); \ -} - -/* _V3CloseConfigWindow - close V3 configuration window */ -#define _V3CloseConfigWindow() { \ - /* Reassign base1 for use by prefetchable PCI memory */ \ - _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \ - | 0x84 | V3_LB_BASE_M_ENABLE)); \ - _V3Write16 (V3_LB_MAP1, \ - (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006); \ - \ - /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \ - \ - _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \ - 0x80 | V3_LB_BASE_M_ENABLE)); \ -} - -static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev, - int offset, unsigned char *val) -{ - _V3OpenConfigWindow (); - *val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset); - _V3CloseConfigWindow (); - - return 0; -} - -static int pci_integrator_read__word (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned short *val) -{ - _V3OpenConfigWindow (); - *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset); - _V3CloseConfigWindow (); - - return 0; -} - -static int pci_integrator_read_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned int *val) -{ - _V3OpenConfigWindow (); - *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset); - *val |= (*(volatile unsigned int *) - PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev), - (offset + 2))) << 16; - _V3CloseConfigWindow (); - - return 0; -} - -static int pci_integrator_write_byte (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned char val) -{ - _V3OpenConfigWindow (); - *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset) = val; - _V3CloseConfigWindow (); - - return 0; -} - -static int pci_integrator_write_word (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned short val) -{ - _V3OpenConfigWindow (); - *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset) = val; - _V3CloseConfigWindow (); - - return 0; -} - -static int pci_integrator_write_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned int val) -{ - _V3OpenConfigWindow (); - *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset) = (val & 0xFFFF); - *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - (offset + 2)) = ((val >> 16) & 0xFFFF); - _V3CloseConfigWindow (); - - return 0; -} -/****************************** - * PCI initialisation - ******************************/ - -struct pci_controller integrator_hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_integrator_config_table, -#endif -}; - -void pci_init_board (void) -{ - volatile int i, j; - struct pci_controller *hose = &integrator_hose; - - /* setting this register will take the V3 out of reset */ - - *(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1; - - /* wait a few usecs to settle the device and the PCI bus */ - - for (i = 0; i < 100; i++) - j = i + 1; - - /* Now write the Base I/O Address Word to V3_BASE + 0x6C */ - - *(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) = - (unsigned short) (V3_BASE >> 16); - - do { - *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA; - *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) = - 0x55; - } while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA - || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + - 4) != 0x55); - - /* Make sure that V3 register access is not locked, if it is, unlock it */ - - if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) & - V3_SYSTEM_M_LOCK) - == V3_SYSTEM_M_LOCK) - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F; - - /* Ensure that the slave accesses from PCI are disabled while we */ - /* setup windows */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &= - ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); - - /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ - - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &= - ~V3_SYSTEM_M_RST_OUT; - - /* Make all accesses from PCI space retry until we're ready for them */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |= - V3_PCI_CFG_M_RETRY_EN; - - /* Set up any V3 PCI Configuration Registers that we absolutely have to */ - /* LB_CFG controls Local Bus protocol. */ - /* Enable LocalBus byte strobes for READ accesses too. */ - /* set bit 7 BE_IMODE and bit 6 BE_OMODE */ - - *(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0; - - /* PCI_CMD controls overall PCI operation. */ - /* Enable PCI bus master. */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04; - - /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */ - - *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) = - (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE); - - /* PCI_BASE0 is the PCI address of the start of the window */ - - *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) = - INTEGRATOR_BOOT_ROM_BASE; - - /* PCI_MAP1 is LOCAL address of the start of the window */ - - *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) = - (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE); - - /* PCI_BASE1 is the PCI address of the start of the window */ - - *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) = - INTEGRATOR_HDR0_SDRAM_BASE; - - /* Set up the windows from local bus memory into PCI configuration, */ - /* I/O and Memory. */ - /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */ - - *(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) = - ((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE; - *(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0; - - /* PCI Configuration, use LB_BASE1/LB_MAP1. */ - - /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */ - /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */ - /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */ - - *(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) = - INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE); - - *(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) = - ((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006; - - /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ - - *(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) = - INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE); - - *(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) = - (((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006; - - /* Allow accesses to PCI Configuration space */ - /* and set up A1, A0 for type 1 config cycles */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) = - ((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) & - ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) | - V3_PCI_CFG_M_AD_LOW0; - - /* now we can allow in PCI MEMORY accesses */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) = - (*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) | - V3_COMMAND_M_MEM_EN; - - /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */ - /* initialise and lock the V3 system register so that no one else */ - /* can play with it */ - - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = - (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | - V3_SYSTEM_M_RST_OUT; - - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = - (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | - V3_SYSTEM_M_LOCK; - - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region (hose->regions + 0, - 0x00000000, 0x40000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI Memory - config space */ - pci_set_region (hose->regions + 1, - 0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM); - - /* PCI V3 regs */ - pci_set_region (hose->regions + 2, - 0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (hose->regions + 3, - 0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO); - - pci_set_ops (hose, - pci_integrator_read_byte, - pci_integrator_read__word, - pci_integrator_read_dword, - pci_integrator_write_byte, - pci_integrator_write_word, pci_integrator_write_dword); - - hose->region_count = 4; - - pci_register_hose (hose); - - pciauto_config_init (hose); - pciauto_config_device (hose, 0); - - hose->last_busno = pci_hose_scan (hose); -} -#endif - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - -#ifdef CONFIG_CM_SPD_DETECT - { -extern void dram_query(void); - unsigned long cm_reg_sdram; - unsigned long sdram_shift; - - dram_query(); /* Assembler accesses to CM registers */ - /* Queries the SPD values */ - - /* Obtain the SDRAM size from the CM SDRAM register */ - - cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM); - /* Register SDRAM size - * - * 0xXXXXXXbbb000bb 16 MB - * 0xXXXXXXbbb001bb 32 MB - * 0xXXXXXXbbb010bb 64 MB - * 0xXXXXXXbbb011bb 128 MB - * 0xXXXXXXbbb100bb 256 MB - * - */ - sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; - gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; - - } -#endif /* CM_SPD_DETECT */ - - return 0; -} - -/* The Integrator/AP timer1 is clocked at 24MHz - * can be divided by 16 or 256 - * and is a 16-bit counter - */ -/* U-Boot expects a 32 bit timer running at CFG_HZ*/ -static ulong timestamp; /* U-Boot ticks since startup */ -static ulong total_count = 0; /* Total timer count */ -static ulong lastdec; /* Timer reading at last call */ -static ulong div_clock = 256; /* Divisor applied to the timer clock */ -static ulong div_timer = 1; /* Divisor to convert timer reading - * change to U-Boot ticks - */ -/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */ - -#define TIMER_LOAD_VAL 0x0000FFFFL -#define READ_TIMER ((*(volatile ulong *)(CFG_TIMERBASE+4)) & 0x0000FFFFL) - -/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec - * - unless otherwise stated - */ - -/* starts a counter - * - the Integrator/AP timer issues an interrupt - * each time it reaches zero - */ -int interrupt_init (void) -{ - /* Load timer with initial value */ - *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL; - /* Set timer to be - * enabled 1 - * free-running 0 - * XX 00 - * divider 256 10 - * XX 00 - */ - *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x00000088; - total_count = 0; - /* init the timestamp and lastdec value */ - reset_timer_masked(); - - div_timer = CFG_HZ_CLOCK / CFG_HZ; - div_timer /= div_clock; - - return (0); -} - -/* - * timer without interrupts - */ -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base_ticks) -{ - return get_timer_masked () - base_ticks; -} - -void set_timer (ulong ticks) -{ - timestamp = ticks; - total_count = ticks * div_timer; - reset_timer_masked(); -} - -/* delay x useconds */ -void udelay (unsigned long usec) -{ - ulong tmo, tmp; - - /* Convert to U-Boot ticks */ - tmo = usec * CFG_HZ; - tmo /= (1000000L); - - tmp = get_timer_masked(); /* get current timestamp */ - tmo += tmp; /* wake up timestamp */ - - while (get_timer_masked () < tmo) { /* loop till event */ - /*NOP*/; - } -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; /* capture current decrementer value */ - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -/* converts the timer reading to U-Boot ticks */ -/* the timestamp is the number of ticks since reset */ -/* This routine does not detect wraps unless called regularly - ASSUMES a call at least every 16 seconds to detect every reload */ -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; /* current count */ - - if (now > lastdec) { - /* Must have wrapped */ - total_count += lastdec + TIMER_LOAD_VAL + 1 - now; - } else { - total_count += lastdec - now; - } - lastdec = now; - timestamp = total_count/div_timer; - - return timestamp; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) -{ - udelay(usec); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * Return the timebase clock frequency - * i.e. how often the timer decrements - */ -ulong get_tbclk (void) -{ - return CFG_HZ_CLOCK/div_clock; -} diff --git a/board/integratorap/lowlevel_init.S b/board/integratorap/lowlevel_init.S deleted file mode 100644 index ab9589c..0000000 --- a/board/integratorap/lowlevel_init.S +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004, ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - /* Reset using CM control register */ -.global reset_cpu -reset_cpu: - mov r0, #CM_BASE - ldr r1,[r0,#OS_CTRL] - orr r1,r1,#CMMASK_RESET - str r1,[r0,#OS_CTRL] - -reset_failed: - b reset_failed - -/* Set up the platform, once the cpu has been initialized */ -.globl lowlevel_init -lowlevel_init: - /* If U-Boot has been run after the ARM boot monitor - * then all the necessary actions have been done - * otherwise we are running from user flash mapped to 0x00000000 - * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED -- - * Changes to the (possibly soft) reset defaults of the processor - * itself should be performed in cpu/arm<>/start.S - * This function affects only the core module or board settings - */ - -#ifdef CONFIG_CM_INIT - /* CM has an initialization register - * - bits in it are wired into test-chip pins to force - * reset defaults - * - may need to change its contents for U-Boot - */ - - /* set the desired CM specific value */ - mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */ - -#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) - orr r2,r2,#CMMASK_INIT_102 -#else - -#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \ - !defined (CONFIG_CM940T) - -#ifdef CONFIG_CM_MULTIPLE_SSRAM - /* set simple mapping */ - and r2,r2,#CMMASK_MAP_SIMPLE -#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ - -#ifdef CONFIG_CM_TCRAM - /* disable TCRAM */ - and r2,r2,#CMMASK_TCRAM_DISABLE -#endif /* #ifdef CONFIG_CM_TCRAM */ - -#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \ - defined (CONFIG_CM1136JF_S) - - and r2,r2,#CMMASK_LE - -#endif /* cpu with little endian initialization */ - - orr r2,r2,#CMMASK_CMxx6_COMMON - -#endif /* CMxx6 code */ - -#endif /* ARM102xxE value */ - - /* read CM_INIT */ - mov r0, #CM_BASE - ldr r1, [r0, #OS_INIT] - /* check against desired bit setting */ - and r3,r1,r2 - cmp r3,r2 - beq init_reg_OK - - /* lock for change */ - mov r3, #CMVAL_LOCK1 - add r3,r3,#CMVAL_LOCK2 - str r3, [r0, #OS_LOCK] - /* set desired value */ - orr r1,r1,r2 - /* write & relock CM_INIT */ - str r1, [r0, #OS_INIT] - mov r1, #CMVAL_UNLOCK - str r1, [r0, #OS_LOCK] - - /* soft reset so new values used */ - b reset_cpu - -init_reg_OK: - -#endif /* CONFIG_CM_INIT */ - - mov pc, lr - -#ifdef CONFIG_CM_SPD_DETECT - /* Fast memory is available for the DRAM data - * - ensure it has been transferred, then summarize the data - * into a CM register - */ -.globl dram_query -dram_query: - stmfd r13!,{r4-r6,lr} - /* set up SDRAM info */ - /* - based on example code from the CM User Guide */ - mov r0, #CM_BASE - -readspdbit: - ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */ - and r1, r1, #0x20 /* mask SPD bit (5) */ - cmp r1, #0x20 /* test if set */ - bne readspdbit - -setupsdram: - add r0, r0, #OS_SPD /* address the copy of the SDP data */ - ldrb r1, [r0, #3] /* number of row address lines */ - ldrb r2, [r0, #4] /* number of column address lines */ - ldrb r3, [r0, #5] /* number of banks */ - ldrb r4, [r0, #31] /* module bank density */ - mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */ - mov r5, r5, ASL#2 /* size in MB */ - mov r0, #CM_BASE /* reload for later code */ - cmp r5, #0x10 /* is it 16MB? */ - bne not16 - mov r6, #0x2 /* store size and CAS latency of 2 */ - b writesize - -not16: - cmp r5, #0x20 /* is it 32MB? */ - bne not32 - mov r6, #0x6 - b writesize - -not32: - cmp r5, #0x40 /* is it 64MB? */ - bne not64 - mov r6, #0xa - b writesize - -not64: - cmp r5, #0x80 /* is it 128MB? */ - bne not128 - mov r6, #0xe - b writesize - -not128: - /* if it is none of these sizes then it is either 256MB, or - * there is no SDRAM fitted so default to 256MB - */ - mov r6, #0x12 - -writesize: - mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */ - orr r2, r1, r2, ASL#12 /* OR in column address lines */ - orr r3, r2, r3, ASL#16 /* OR in number of banks */ - orr r6, r6, r3 /* OR in size and CAS latency */ - str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */ - -#endif /* #ifdef CONFIG_CM_SPD_DETECT */ - - ldmfd r13!,{r4-r6,pc} /* back to caller */ - -#ifdef CONFIG_CM_REMAP - /* CM remap bit is operational - * - use it to map writeable memory at 0x00000000, in place of flash - */ -.globl cm_remap -cm_remap: - stmfd r13!,{r4-r10,lr} - - mov r0, #CM_BASE - ldr r1, [r0, #OS_CTRL] - orr r1, r1, #CMMASK_REMAP /* set remap and led bits */ - str r1, [r0, #OS_CTRL] - - /* Now 0x00000000 is writeable, replace the vectors */ - ldr r0, =_start /* r0 <- start of vectors */ - ldr r2, =_armboot_start /* r2 <- past vectors */ - sub r1,r1,r1 /* destination 0x00000000 */ - -copy_vec: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - ble copy_vec - - ldmfd r13!,{r4-r10,pc} /* back to caller */ - -#endif /* #ifdef CONFIG_CM_REMAP */ diff --git a/board/integratorap/memsetup.S b/board/integratorap/memsetup.S deleted file mode 100644 index dfdc784..0000000 --- a/board/integratorap/memsetup.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Memory setup for integratorAP - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * Memory setup - * - the reset defaults are assumed sufficient - */ - -.globl memsetup -memsetup: - mov pc,lr diff --git a/board/integratorap/split_by_variant.sh b/board/integratorap/split_by_variant.sh deleted file mode 100755 index 9f71bab..0000000 --- a/board/integratorap/split_by_variant.sh +++ /dev/null @@ -1,116 +0,0 @@ -#!/bin/sh -# --------------------------------------------------------- -# Set the platform defines -# --------------------------------------------------------- -echo -n "/* Integrator configuration implied " > tmp.fil -echo " by Makefile target */" >> tmp.fil -echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil -echo " /* Integrator board */" >> tmp.fil -echo -n "#define CONFIG_ARCH_INTEGRATOR" >> tmp.fil -echo " 1 /* Integrator/AP */" >> tmp.fil -# --------------------------------------------------------- -# Set the core module defines according to Core Module -# --------------------------------------------------------- -cpu="arm_intcm" -variant="unknown core module" - -if [ "$1" == "" ] -then - echo "$0:: No parameters - using arm_intcm" -else - case "$1" in - ap7_config) - cpu="arm_intcm" - variant="unported core module CM7TDMI" - ;; - - ap966) - cpu="arm_intcm" - variant="unported core module CM966E-S" - ;; - - ap922_config) - cpu="arm_intcm" - variant="unported core module CM922T" - ;; - - integratorap_config | \ - ap_config) - cpu="arm_intcm" - variant="unspecified core module" - ;; - - ap720t_config) - cpu="arm720t" - echo -n "#define CONFIG_CM720T" >> tmp.fil - echo " 1 /* CPU core is ARM720T */ " >> tmp.fil - variant="Core module CM720T" - ;; - - ap922_XA10_config) - cpu="arm_intcm" - variant="unported core module CM922T_XA10" - echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil - echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil - ;; - - ap920t_config) - cpu="arm920t" - variant="Core module CM920T" - echo -n "#define CONFIG_CM920T" >> tmp.fil - echo " 1 /* CPU core is ARM920T */" >> tmp.fil - ;; - - ap926ejs_config) - cpu="arm926ejs" - variant="Core module CM926EJ-S" - echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil - echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil - ;; - - ap946es_config) - cpu="arm946es" - variant="Core module CM946E-S" - echo -n "#define CONFIG_CM946E_S" >> tmp.fil - echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil - ;; - - *) - echo "$0:: Unknown core module" - variant="unknown core module" - cpu="arm_intcm" - ;; - - esac -fi - -if [ "$cpu" == "arm_intcm" ] -then - echo "/* Core module undefined/not ported */" >> tmp.fil - echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil - echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil - echo -n " /* CM may not have " >> tmp.fil - echo "multiple SSRAM mapping */" >> tmp.fil - echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil - echo -n " /* CM may not support SPD " >> tmp.fil - echo "query */" >> tmp.fil - echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil - echo -n " /* CM may not support " >> tmp.fil - echo "remapping */" >> tmp.fil - echo -n "#undef CONFIG_CM_INIT " >> tmp.fil - echo -n " /* CM may not have " >> tmp.fil - echo "initialization reg */" >> tmp.fil - echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil - echo " /* CM may not have TCRAM */" >> tmp.fil -fi -mv tmp.fil ./include/config.h -# --------------------------------------------------------- -# Ensure correct core object loaded first in U-Boot image -# --------------------------------------------------------- -sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorap/u-boot.lds.template > board/integratorap/u-boot.lds -# --------------------------------------------------------- -# Complete the configuration -# --------------------------------------------------------- -./mkconfig -a integratorap arm $cpu integratorap; -echo "Variant:: $variant with core $cpu" - diff --git a/board/integratorap/u-boot.lds.template b/board/integratorap/u-boot.lds.template deleted file mode 100644 index 0ec8087..0000000 --- a/board/integratorap/u-boot.lds.template +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -# Template used during configuration to emsure the core module processor code, -# from CPU_FILE, is placed at the start of the image */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - . = ALIGN(4); - .text : - { - CPU_FILE (.text) - *(.text) - } - .rodata : { *(.rodata) } - . = ALIGN(4); - .data : { *(.data) } - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/integratorcp/Makefile b/board/integratorcp/Makefile deleted file mode 100644 index 3d589fc..0000000 --- a/board/integratorcp/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := integratorcp.o flash.o -SOBJS := lowlevel_init.o memsetup.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/integratorcp/config.mk b/board/integratorcp/config.mk deleted file mode 100644 index 25b79b3..0000000 --- a/board/integratorcp/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -# -# image should be loaded at 0x01000000 -# - -TEXT_BASE = 0x01000000 diff --git a/board/integratorcp/flash.c b/board/integratorcp/flash.c deleted file mode 100644 index 4d6eff0..0000000 --- a/board/integratorcp/flash.c +++ /dev/null @@ -1,564 +0,0 @@ -/* - * (C) Copyright 2004 - * Xiaogeng (Shawn) Jin, Agilent Technologies, xiaogeng_jin@agilent.com - * - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define DEBUG - -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - -/* CP control register base address */ -#define CPCR_BASE 0xCB000000 -#define CPCR_EXTRABANK 0x8 -#define CPCR_FLASHSIZE 0x4 -#define CPCR_FLWREN 0x2 -#define CPCR_FLVPPEN 0x1 - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - int i, nbanks; - ulong size = 0; - vu_long *cpcr = (vu_long *)CPCR_BASE; - - /* Check if there is an extra bank of flash */ - if (cpcr[1] & CPCR_EXTRABANK) - nbanks = 2; - else - nbanks = 1; - - if (nbanks > CFG_MAX_FLASH_BANKS) - nbanks = CFG_MAX_FLASH_BANKS; - - /* Enable flash write */ - cpcr[1] |= 3; - - for (i = 0; i < nbanks; i++) { - flash_get_size ((FPW *)(CFG_FLASH_BASE + size), &flash_info[i]); - flash_get_offsets (CFG_FLASH_BASE + size, &flash_info[i]); - size += flash_info[i].size; - } - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection */ - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - /* Protect SIB (0x24800000) and bootMonitor (0x24c00000) */ - flash_protect (FLAG_PROTECT_SET, - flash_info[0].start[62], - flash_info[0].start[63] + PHYS_FLASH_SECT_SIZE - 1, - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* Integrator CP board uses 28F640J3C or 28F128J3C parts, - * which have the same device id numbers as 28F640J3A or - * 28F128J3A - */ - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - case FLASH_28F640J3A: - printf ("FLASH 28F640J3C\n"); - break; - case FLASH_28F128J3A: - printf ("FLASH 28F128J3C\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - vu_long *cpcr = (vu_long *)CPCR_BASE; - int nsects; - - /* Check the flash size */ - if (cpcr[1] & CPCR_FLASHSIZE) - nsects = 128; - else - nsects = 64; - - if (nsects > CFG_MAX_FLASH_SECT) - nsects = CFG_MAX_FLASH_SECT; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - case (FPW) (INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = nsects; - info->size = nsects * PHYS_FLASH_SECT_SIZE; - break; - - case (FPW) (INTEL_ID_28F128J3A): - info->flash_id += FLASH_28F128J3A; - info->sector_count = nsects; - info->size = nsects * PHYS_FLASH_SECT_SIZE; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ - FPW status; - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; - - reset_timer_masked(); - while (((status = *addr) & (FPW)0x00800080) != 0x00800080) { - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { - printf("Timeout"); - break; - } - } - - *addr = (FPW) 0x00FF00FF; -} - - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* flash_unprotect_sectors (addr); */ - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - mb(); - - udelay(1000); /* Let's wait 1 ms */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - *addr = (FPW)0x00700070; - status = *addr; - if ((status & (FPW) 0x00400040) == (FPW) 0x00400040) { - /* erase suspended? Resume it */ - reset_timer_masked(); - *addr = (FPW) 0x00D000D0; - } else { -#ifdef DEBUG - printf ("Timeout,0x%08x\n", status); -#else - printf("Timeout\n"); -#endif - - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - } - - *addr = (FPW) 0x00FF00FF; /* resest to read mode */ - printf (" done\n"); - } - } - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* flash_unprotect_sectors (addr); */ - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - mb(); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { -#ifdef DEBUG - *addr = (FPW) 0x00700070; - status = *addr; - printf("## status=0x%08x, addr=0x%08x\n", status, addr); -#endif - *addr = (FPW) 0x00500050; /* clear status register cmd */ - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/integratorcp/integratorcp.c b/board/integratorcp/integratorcp.c deleted file mode 100644 index 216876b..0000000 --- a/board/integratorcp/integratorcp.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -void flash__init (void); -void ether__init (void); -void peripheral_power_enable (void); - -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -void show_boot_progress(int progress) -{ - printf("Boot reached stage %d\n", progress); -} -#endif - -#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* arch number of Integrator Board */ - gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - gd->flags = 0; - -#ifdef CONFIG_CM_REMAP -extern void cm_remap(void); - cm_remap(); /* remaps writeable memory to 0x00000000 */ -#endif - - icache_enable (); - - flash__init (); - ether__init (); - return 0; -} - - -int misc_init_r (void) -{ - setenv("verify", "n"); - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - -#ifdef CONFIG_CM_SPD_DETECT - { -extern void dram_query(void); - unsigned long cm_reg_sdram; - unsigned long sdram_shift; - - dram_query(); /* Assembler accesses to CM registers */ - /* Queries the SPD values */ - - /* Obtain the SDRAM size from the CM SDRAM register */ - - cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM); - /* Register SDRAM size - * - * 0xXXXXXXbbb000bb 16 MB - * 0xXXXXXXbbb001bb 32 MB - * 0xXXXXXXbbb010bb 64 MB - * 0xXXXXXXbbb011bb 128 MB - * 0xXXXXXXbbb100bb 256 MB - * - */ - sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; - gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; - - } -#endif /* CM_SPD_DETECT */ - - return 0; -} - -/* The Integrator/CP timer1 is clocked at 1MHz - * can be divided by 16 or 256 - * and can be set up as a 32-bit timer - */ -/* U-Boot expects a 32 bit timer, running at CFG_HZ */ -/* Keep total timer count to avoid losing decrements < div_timer */ -static unsigned long long total_count = 0; -static unsigned long long lastdec; /* Timer reading at last call */ -static unsigned long long div_clock = 1; /* Divisor applied to timer clock */ -static unsigned long long div_timer = 1; /* Divisor to convert timer reading - * change to U-Boot ticks - */ -/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */ -static ulong timestamp; /* U-Boot ticks since startup */ - -#define TIMER_LOAD_VAL ((ulong)0xFFFFFFFF) -#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4)) - -/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec - * - unless otherwise stated - */ - -/* starts up a counter - * - the Integrator/CP timer can be set up to issue an interrupt */ -int interrupt_init (void) -{ - /* Load timer with initial value */ - *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL; - /* Set timer to be - * enabled 1 - * periodic 1 - * no interrupts 0 - * X 0 - * divider 1 00 == less rounding error - * 32 bit 1 - * wrapping 0 - */ - *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x000000C2; - /* init the timestamp */ - total_count = 0ULL; - reset_timer_masked(); - - div_timer = (unsigned long long)(CFG_HZ_CLOCK / CFG_HZ); - div_timer /= div_clock; - - return (0); -} - -/* - * timer without interrupts - */ -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base_ticks) -{ - return get_timer_masked () - base_ticks; -} - -void set_timer (ulong ticks) -{ - timestamp = ticks; - total_count = (unsigned long long)ticks * div_timer; -} - -/* delay usec useconds */ -void udelay (unsigned long usec) -{ - ulong tmo, tmp; - - /* Convert to U-Boot ticks */ - tmo = usec * CFG_HZ; - tmo /= (1000000L); - - tmp = get_timer_masked(); /* get current timestamp */ - tmo += tmp; /* form target timestamp */ - - while (get_timer_masked () < tmo) {/* loop till event */ - /*NOP*/; - } -} - -void reset_timer_masked (void) -{ - /* capure current decrementer value */ - lastdec = (unsigned long long)READ_TIMER; - /* start "advancing" time stamp from 0 */ - timestamp = 0L; -} - -/* converts the timer reading to U-Boot ticks */ -/* the timestamp is the number of ticks since reset */ -ulong get_timer_masked (void) -{ - /* get current count */ - unsigned long long now = (unsigned long long)READ_TIMER; - - if(now > lastdec) { - /* Must have wrapped */ - total_count += lastdec + TIMER_LOAD_VAL + 1 - now; - } else { - total_count += lastdec - now; - } - lastdec = now; - timestamp = (ulong)(total_count/div_timer); - - return timestamp; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) -{ - udelay(usec); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return (unsigned long long)get_timer(0); -} - -/* - * Return the timebase clock frequency - * i.e. how often the timer decrements - */ -ulong get_tbclk (void) -{ - return (ulong)(((unsigned long long)CFG_HZ_CLOCK)/div_clock); -} diff --git a/board/integratorcp/lowlevel_init.S b/board/integratorcp/lowlevel_init.S deleted file mode 100644 index 18f7d2e..0000000 --- a/board/integratorcp/lowlevel_init.S +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003, ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* Reset using CM control register */ -.global reset_cpu -reset_cpu: - mov r0, #CM_BASE - ldr r1,[r0,#OS_CTRL] - orr r1,r1,#CMMASK_RESET - str r1,[r0,#OS_CTRL] - -reset_failed: - b reset_failed - -/* Set up the platform, once the cpu has been initialized */ -.globl lowlevel_init -lowlevel_init: - /* If U-Boot has been run after the ARM boot monitor - * then all the necessary actions have been done - * otherwise we are running from user flash mapped to 0x00000000 - * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED -- - * Changes to the (possibly soft) reset defaults of the processor - * itself should be performed in cpu/arm<>/start.S - * This function affects only the core module or board settings - */ - -#ifdef CONFIG_CM_INIT - /* CM has an initialization register - * - bits in it are wired into test-chip pins to force - * reset defaults - * - may need to change its contents for U-Boot - */ - - /* set the desired CM specific value */ - mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */ - -#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) - orr r2,r2,#CMMASK_INIT_102 -#else - -#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \ - !defined (CONFIG_CM940T) - /* CMxx6 code */ - -#ifdef CONFIG_CM_MULTIPLE_SSRAM - /* set simple mapping */ - and r2,r2,#CMMASK_MAP_SIMPLE -#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ - -#ifdef CONFIG_CM_TCRAM - /* disable TCRAM */ - and r2,r2,#CMMASK_TCRAM_DISABLE -#endif /* #ifdef CONFIG_CM_TCRAM */ - -#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \ - defined (CONFIG_CM1136JF_S) - - and r2,r2,#CMMASK_LE - -#endif /* cpu with little endian initialization */ - - orr r2,r2,#CMMASK_CMxx6_COMMON - -#endif /* CMxx6 code */ - -#endif /* ARM102xxE value */ - - /* read CM_INIT */ - mov r0, #CM_BASE - ldr r1, [r0, #OS_INIT] - /* check against desired bit setting */ - and r3,r1,r2 - cmp r3,r2 - beq init_reg_OK - - /* lock for change */ - mov r3, #CMVAL_LOCK1 - and r3, r3, #CMVAL_LOCK2 - str r3, [r0, #OS_LOCK] - /* set desired value */ - orr r1,r1,r2 - /* write & relock CM_INIT */ - str r1, [r0, #OS_INIT] - mov r1, #CMVAL_UNLOCK - str r1, [r0, #OS_LOCK] - - /* soft reset so new values used */ - b reset_cpu - -init_reg_OK: - -#endif /* CONFIG_CM_INIT */ - - mov pc, lr - -#ifdef CONFIG_CM_SPD_DETECT - /* Fast memory is available for the DRAM data - * - ensure it has been transferred, then summarize the data - * into a CM register - */ -.globl dram_query -dram_query: - stmfd r13!,{r4-r6,lr} - /* set up SDRAM info */ - /* - based on example code from the CM User Guide */ - mov r0, #CM_BASE - -readspdbit: - ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */ - and r1, r1, #0x20 /* mask SPD bit (5) */ - cmp r1, #0x20 /* test if set */ - bne readspdbit - -setupsdram: - add r0, r0, #OS_SPD /* address the copy of the SDP data */ - ldrb r1, [r0, #3] /* number of row address lines */ - ldrb r2, [r0, #4] /* number of column address lines */ - ldrb r3, [r0, #5] /* number of banks */ - ldrb r4, [r0, #31] /* module bank density */ - mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */ - mov r5, r5, ASL#2 /* size in MB */ - mov r0, #CM_BASE /* reload for later code */ - cmp r5, #0x10 /* is it 16MB? */ - bne not16 - mov r6, #0x2 /* store size and CAS latency of 2 */ - b writesize - -not16: - cmp r5, #0x20 /* is it 32MB? */ - bne not32 - mov r6, #0x6 - b writesize - -not32: - cmp r5, #0x40 /* is it 64MB? */ - bne not64 - mov r6, #0xa - b writesize - -not64: - cmp r5, #0x80 /* is it 128MB? */ - bne not128 - mov r6, #0xe - b writesize - -not128: - /* if it is none of these sizes then it is either 256MB, or - * there is no SDRAM fitted so default to 256MB - */ - mov r6, #0x12 - -writesize: - mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */ - orr r2, r1, r2, ASL#12 /* OR in column address lines */ - orr r3, r2, r3, ASL#16 /* OR in number of banks */ - orr r6, r6, r3 /* OR in size and CAS latency */ - str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */ - -#endif /* #ifdef CONFIG_CM_SPD_DETECT */ - - ldmfd r13!,{r4-r6,pc} /* back to caller */ - -#ifdef CONFIG_CM_REMAP - /* CM remap bit is operational - * - use it to map writeable memory at 0x00000000, in place of flash - */ -.globl cm_remap -cm_remap: - stmfd r13!,{r4-r10,lr} - - mov r0, #CM_BASE - ldr r1, [r0, #OS_CTRL] - orr r1, r1, #CMMASK_REMAP /* set remap and led bits */ - str r1, [r0, #OS_CTRL] - - /* Now 0x00000000 is writeable, replace the vectors */ - ldr r0, =_start /* r0 <- start of vectors */ - ldr r2, =_armboot_start /* r2 <- past vectors */ - sub r1,r1,r1 /* destination 0x00000000 */ - -copy_vec: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - ble copy_vec - - ldmfd r13!,{r4-r10,pc} /* back to caller */ - -#endif /* #ifdef CONFIG_CM_REMAP */ diff --git a/board/integratorcp/memsetup.S b/board/integratorcp/memsetup.S deleted file mode 100644 index dfdc784..0000000 --- a/board/integratorcp/memsetup.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Memory setup for integratorAP - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * Memory setup - * - the reset defaults are assumed sufficient - */ - -.globl memsetup -memsetup: - mov pc,lr diff --git a/board/integratorcp/split_by_variant.sh b/board/integratorcp/split_by_variant.sh deleted file mode 100755 index 3a35433..0000000 --- a/board/integratorcp/split_by_variant.sh +++ /dev/null @@ -1,111 +0,0 @@ -#!/bin/sh -# --------------------------------------------------------- -# Set the platform defines -# --------------------------------------------------------- -echo -n "/* Integrator configuration implied " > tmp.fil -echo " by Makefile target */" >> tmp.fil -echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil -echo " /* Integrator board */" >> tmp.fil -echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> tmp.fil -echo " 1 /* Integrator/CP */" >> tmp.fil - -cpu="arm_intcm" -variant="unknown core module" - -if [ "$1" == "" ] -then - echo "$0:: No parameters - using arm_intcm" -else - case "$1" in - ap966) - cpu="arm_intcm" - variant="unported core module CM966E-S" - ;; - - ap922_config) - cpu="arm_intcm" - variant="unported core module CM922T" - ;; - - integratorcp_config | \ - cp_config) - cpu="arm_intcm" - variant="unspecified core module" - ;; - - cp922_XA10_config) - cpu="arm_intcm" - variant="unported core module CM922T_XA10" - echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil - echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil - ;; - - cp920t_config) - cpu="arm920t" - variant="Core module CM920T" - echo -n "#define CONFIG_CM920T" >> tmp.fil - echo " 1 /* CPU core is ARM920T */" >> tmp.fil - ;; - - cp926ejs_config) - cpu="arm926ejs" - variant="Core module CM926EJ-S" - echo -n "#define CONFIG_CM926EJ_S" >> tmp.fil - echo " 1 /* CPU core is ARM926EJ-S */ " >> tmp.fil - ;; - - - cp946es_config) - cpu="arm946es" - variant="Core module CM946E-S" - echo -n "#define CONFIG_CM946E_S" >> tmp.fil - echo " 1 /* CPU core is ARM946E-S */ " >> tmp.fil - ;; - - cp1136_config) - cpu="arm1136" - variant="Core module CM1136EJF-S" - echo -n "#define CONFIG_CM1136EJF_S" >> tmp.fil - echo " 1 /* CPU core is ARM1136JF-S */ " >> tmp.fil - ;; - - *) - echo "$0:: Unknown core module" - variant="unknown core module" - cpu="arm_intcm" - ;; - - esac - -fi - -if [ "$cpu" == "arm_intcm" ] -then - echo "/* Core module undefined/not ported */" >> tmp.fil - echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil - echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil - echo -n " /* CM may not have " >> tmp.fil - echo "multiple SSRAM mapping */" >> tmp.fil - echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil - echo -n " /* CM may not support SPD " >> tmp.fil - echo "query */" >> tmp.fil - echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil - echo -n " /* CM may not support " >> tmp.fil - echo "remapping */" >> tmp.fil - echo -n "#undef CONFIG_CM_INIT " >> tmp.fil - echo -n " /* CM may not have " >> tmp.fil - echo "initialization reg */" >> tmp.fil - echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil - echo " /* CM may not have TCRAM */" >> tmp.fil -fi -mv tmp.fil ./include/config.h -# --------------------------------------------------------- -# Ensure correct core object loaded first in U-Boot image -# --------------------------------------------------------- -sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorcp/u-boot.lds.template > board/integratorcp/u-boot.lds -# --------------------------------------------------------- -# Complete the configuration -# --------------------------------------------------------- -./mkconfig -a integratorcp arm $cpu integratorcp; -echo "Variant:: $variant with core $cpu" - diff --git a/board/integratorcp/u-boot.lds.template b/board/integratorcp/u-boot.lds.template deleted file mode 100644 index 0ec8087..0000000 --- a/board/integratorcp/u-boot.lds.template +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -# Template used during configuration to emsure the core module processor code, -# from CPU_FILE, is placed at the start of the image */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - . = ALIGN(4); - .text : - { - CPU_FILE (.text) - *(.text) - } - .rodata : { *(.rodata) } - . = ALIGN(4); - .data : { *(.data) } - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/ip860/Makefile b/board/ip860/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/ip860/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/ip860/config.mk b/board/ip860/config.mk deleted file mode 100644 index ea3b873..0000000 --- a/board/ip860/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MicroSys IP860 VMEBus Systems -# - -TEXT_BASE = 0x10000000 diff --git a/board/ip860/flash.c b/board/ip860/flash.c deleted file mode 100644 index 2cf23b3..0000000 --- a/board/ip860/flash.c +++ /dev/null @@ -1,456 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ - bcsr->bd_ctrl |= BD_CTRL_FLWE; - - for (i=0; imemc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br1 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* all possible flash types - * (28F016SV, 28F160S3, 28F320S3) - * have the same erase block size: 64 kB per chip, - * of 128 kB per bank - */ - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x00020000; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - - value = addr[0]; - switch (value) { - case (MT_MANUFACT & 0x00FF00FF): /* MT or => Intel */ - case (INTEL_ALT_MANU & 0x00FF00FF): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (INTEL_ID_28F016S): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F160S3): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F320S3): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 2x4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - - *addr = 0xFFFFFF; /* reset bank to read array mode */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Single Block Erase Command */ - *addr = 0x20202020; - /* Confirm */ - *addr = 0xD0D0D0D0; - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while ((*addr & 0x00800080) != 0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - } - } - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - while (((csr = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x00400040) { -printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - - return (flag); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c deleted file mode 100644 index 9dd809b..0000000 --- a/board/ip860/ip860.c +++ /dev/null @@ -1,356 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -unsigned long ip860_get_dram_size(void); -unsigned long ip860_get_clk_freq (void); -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -/* ------------------------------------------------------------------------- */ -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - -/* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */ - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * Test ID string (IP860...) - */ - -int checkboard (void) -{ - unsigned char *s, *e; - unsigned char buf[64]; - int i; - - puts ("Board: "); - - i = getenv_r ("serial#", (char *)buf, sizeof (buf)); - s = (i > 0) ? buf : NULL; - - if (!s || strncmp ((char *)s, "IP860", 5)) { - puts ("### No HW ID - assuming IP860"); - } else { - for (e = s; *e; ++e) { - if (*e == ' ') - break; - } - - for (; s < e; ++s) { - putc (*s); - } - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - ulong refresh_val; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh - */ - if (ip860_get_clk_freq() == 50000000) - { - memctl->memc_mptpr = 0x0400; - refresh_val = 0xC3000000; - } - else - { - memctl->memc_mptpr = 0x0200; - refresh_val = 0x9C000000; - } - - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 to the SDRAM address - */ - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; - - /* IP860 boards have only one bank SDRAM */ - - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mamr = 0x00804114 | refresh_val; - memctl->memc_mcr = 0x80004105; /* run precharge pattern from loc 5 */ - udelay(1); - memctl->memc_mamr = 0x00804118 | refresh_val; - memctl->memc_mcr = 0x80004130; /* run refresh pattern 8 times */ - - - udelay (1000); - - /* - * Check SDRAM Memory Size - */ - if (ip860_get_dram_size() == 16) - size = dram_size (refresh_val | 0x00804114, SDRAM_BASE, SDRAM_MAX_SIZE); - else - size = dram_size (refresh_val | 0x00906114, SDRAM_BASE, SDRAM_MAX_SIZE); - - udelay (1000); - - memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - udelay (10000); - - /* - * Also, map other memory to correct position - */ - -#if (defined(CFG_OR1) && defined(CFG_BR1_PRELIM)) - memctl->memc_or1 = CFG_OR1; - memctl->memc_br1 = CFG_BR1; -#endif - -#if defined(CFG_OR3) && defined(CFG_BR3) - memctl->memc_or3 = CFG_OR3; - memctl->memc_br3 = CFG_BR3; -#endif - -#if defined(CFG_OR4) && defined(CFG_BR4) - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; -#endif - -#if defined(CFG_OR5) && defined(CFG_BR5) - memctl->memc_or5 = CFG_OR5; - memctl->memc_br5 = CFG_BR5; -#endif - -#if defined(CFG_OR6) && defined(CFG_BR6) - memctl->memc_or6 = CFG_OR6; - memctl->memc_br6 = CFG_BR6; -#endif - -#if defined(CFG_OR7) && defined(CFG_BR7) - memctl->memc_or7 = CFG_OR7; - memctl->memc_br7 = CFG_BR7; -#endif - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -void reset_phy (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - ulong mask = PB_ENET_RESET | PB_ENET_JABD; - ulong reg; - - /* Make sure PHY is not in low-power mode */ - immr->im_cpm.cp_pbpar &= ~(mask); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(mask); /* active output */ - - /* Set JABD low (no JABber Disable), - * and RESET high (Reset PHY) - */ - reg = immr->im_cpm.cp_pbdat; - reg = (reg & ~PB_ENET_JABD) | PB_ENET_RESET; - immr->im_cpm.cp_pbdat = reg; - - /* now drive outputs */ - immr->im_cpm.cp_pbdir |= mask; /* output */ - udelay (1000); - /* - * Release RESET signal - */ - immr->im_cpm.cp_pbdat &= ~(PB_ENET_RESET); - udelay (1000); -} - -/* ------------------------------------------------------------------------- */ - -unsigned long ip860_get_clk_freq(void) -{ - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; - ulong temp; - uchar sysclk; - - if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */ - sysclk = (bcsr->bd_rev & 0x18) >> 3; - else - sysclk = 0x00; - - switch (sysclk) - { - case 0x00: - temp = 50000000; - break; - - case 0x01: - temp = 80000000; - break; - - default: - temp = 50000000; - break; - } - - return (temp); - -} - - -/* ------------------------------------------------------------------------- */ - -unsigned long ip860_get_dram_size(void) -{ - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; - ulong temp; - uchar dram_size; - - if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */ - dram_size = (bcsr->bd_rev & 0xE0) >> 5; - else - dram_size = 0x00; /* default is 16 MB */ - - switch (dram_size) - { - case 0x00: - temp = 16; - break; - - case 0x01: - temp = 32; - break; - - default: - temp = 16; - break; - } - - return (temp); - -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds deleted file mode 100644 index 8cb2504..0000000 --- a/board/ip860/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - cpu/mpc8xx/interrupts.o (.text) - lib_ppc/time.o (.text) - lib_ppc/ticks.o (.text) -/** - . = env_offset; - common/environment.o(.text) -**/ - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug deleted file mode 100644 index 43d2b3b..0000000 --- a/board/ip860/u-boot.lds.debug +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - lib_ppc/ppcstring.o (.text) - cpu/mpc8xx/interrupts.o (.text) - lib_ppc/time.o (.text) - lib_ppc/ticks.o (.text) -/** - . = env_offset; - common/environment.o(.text) -**/ - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/iphase4539/Makefile b/board/iphase4539/Makefile deleted file mode 100644 index 19da5d0..0000000 --- a/board/iphase4539/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2002 Wolfgang Grandegger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/iphase4539/config.mk b/board/iphase4539/config.mk deleted file mode 100644 index 632c1d2..0000000 --- a/board/iphase4539/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2002 Wolfgang Grandegger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# iphase4539 board -# - -TEXT_BASE = 0xffb00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/iphase4539/flash.c b/board/iphase4539/flash.c deleted file mode 100644 index 4eca467..0000000 --- a/board/iphase4539/flash.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Adapted for Interphase 4539 by Wolfgang Grandegger . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -extern int hwc_flash_size(void); -static ulong flash_get_size (u32 addr, flash_info_t *info); -static int flash_get_offsets (u32 base, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_reset (u32 addr); - -#define out8(a,v) *(volatile unsigned char*)(a) = v -#define in8(a) *(volatile unsigned char*)(a) -#define in32(a) *(volatile unsigned long*)(a) -#define iobarrier_rw() eieio() - -unsigned long flash_init (void) -{ - unsigned int i; - unsigned long flash_size = 0; - unsigned long bank_size; - unsigned int bank = 0; - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = 0; - flash_info[i].size = 0; - } - - /* Initialise the BOOT Flash */ - if (bank == CFG_MAX_FLASH_BANKS) { - puts ("Warning: not all Flashes are initialised !"); - return flash_size; - } - - bank_size = flash_get_size (CFG_FLASH_BASE, flash_info + bank); - if (bank_size) { -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \ - CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_MAX_FLASH_SIZE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - flash_info + bank); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - flash_info + bank); -#endif - - /* HWC protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0x10000 - 1, - flash_info + bank); - - flash_size += bank_size; - bank++; - } else { - puts ("Warning: the BOOT Flash is not initialised !"); - } - - return flash_size; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (u32 addr, flash_info_t *info) -{ - volatile uchar value; -#if 0 - int i; -#endif - - /* Write auto select command: read Manufacturer ID */ - out8(addr + 0x0555, 0xAA); - iobarrier_rw(); - udelay(10); - out8(addr + 0x02AA, 0x55); - iobarrier_rw(); - udelay(10); - out8(addr + 0x0555, 0x90); - iobarrier_rw(); - udelay(10); - - value = in8(addr); - iobarrier_rw(); - udelay(10); - switch (value | (value << 16)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - flash_reset (addr); - return 0; - } - - value = in8(addr + 1); /* device ID */ - iobarrier_rw(); - - switch (value) { - case AMD_ID_LV033C: - info->flash_id += FLASH_AM033C; - info->size = hwc_flash_size(); - if (info->size > CFG_MAX_FLASH_SIZE) { - printf("U-Boot supports only %d MB\n", - CFG_MAX_FLASH_SIZE); - info->size = CFG_MAX_FLASH_SIZE; - } - info->sector_count = info->size / 0x10000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - flash_reset (addr); - return (0); /* => no or unknown flash */ - - } - - if (!flash_get_offsets (addr, info)) { - flash_reset (addr); - return 0; - } - -#if 0 - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - value = in8(info->start[i] + 2); - iobarrier_rw(); - info->protect[i] = (value & 1) != 0; - } -#endif - - /* - * Reset bank to read mode - */ - flash_reset (addr); - - return (info->size); -} - -static int flash_get_offsets (u32 base, flash_info_t *info) -{ - unsigned int i, size; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM033C: - /* set sector offsets for uniform sector type */ - size = info->size / info->sector_count; - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + i * size; - } - break; - default: - return 0; - } - - return 1; -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile u32 addr = info->start[0]; - int flag, prot, sect, l_sect; - ulong start, now, last; - - if (s_first < 0 || s_first > s_last) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN || - info->flash_id > FLASH_AMD_COMP) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0x80); - iobarrier_rw(); - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = info->start[sect]; - out8(addr, 0x30); - iobarrier_rw(); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = info->start[l_sect]; - while ((in8(addr) & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - iobarrier_rw(); - } - -DONE: - /* reset to read mode */ - flash_reset (info->start[0]); - - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile u32 addr = info->start[0]; - ulong start; - int flag, i; - - /* Check if Flash is (sufficiently) erased */ - if ((in32(dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* first, perform an unlock bypass command to speed up flash writes */ - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0x20); - iobarrier_rw(); - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *)&data; - out8(addr, 0xA0); - iobarrier_rw(); - out8(dest+i, data_ch[i]); - iobarrier_rw(); - udelay(10); /* XXX */ - } - - /* we're done, now do an unlock bypass reset */ - out8(addr, 0x90); - iobarrier_rw(); - out8(addr, 0x00); - iobarrier_rw(); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((in32(dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - iobarrier_rw(); - } - - flash_reset (addr); - - return (0); -} - -/* - * Reset bank to read mode - */ -static void flash_reset (u32 addr) -{ - out8(addr, 0xF0); /* reset bank */ - iobarrier_rw(); -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM033C: printf ("AM29LV033C (32 Mbit, uniform sectors)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size % 0x100000 == 0) { - printf (" Size: %ld MB in %d Sectors\n", - info->size / 0x100000, info->sector_count); - } - else if (info->size % 0x400 == 0) { - printf (" Size: %ld KB in %d Sectors\n", - info->size / 0x400, info->sector_count); - } - else { - printf (" Size: %ld B in %d Sectors\n", - info->size, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} diff --git a/board/iphase4539/iphase4539.c b/board/iphase4539/iphase4539.c deleted file mode 100644 index 0ca9cf5..0000000 --- a/board/iphase4539/iphase4539.c +++ /dev/null @@ -1,424 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -int hwc_flash_size (void); -int hwc_local_sdram_size (void); -int hwc_main_sdram_size (void); -int hwc_serial_number (void); -int hwc_mac_address (char *str); -int hwc_manufact_date (char *str); -int seeprom_read (int addr, uchar * data, int size); - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - * - * The port definitions are taken from the old firmware (see - * also SYS/H/4539.H): - * - * ppar psor pdir podr pdat - * PA: 0x02ffffff 0x02c00000 0xfc403fe6 0x00000000 0x02403fc0 - * PB: 0x0fffdeb0 0x000000b0 0x0f032347 0x00000000 0x0f000290 - * PC: 0x030ffa55 0x030f0040 0xbcf005ea 0x00000000 0xc0c0ba7d - * PD: 0x09c04e3c 0x01000e3c 0x0a7ff1c3 0x00000000 0x00ce0ae9 - */ -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - {0, 1, 0, 0, 0, 0}, /* PA31 FCC1_TXENB SLAVE */ - {0, 1, 0, 1, 0, 0}, /* PA30 FCC1_TXCLAV SLAVE */ - {0, 1, 0, 1, 0, 0}, /* PA29 FCC1_TXSOC */ - {0, 1, 0, 0, 0, 0}, /* PA28 FCC1_RXENB SLAVE */ - {0, 1, 0, 0, 0, 0}, /* PA27 FCC1_RXSOC */ - {0, 1, 0, 1, 0, 0}, /* PA26 FCC1_RXCLAV SLAVE */ - {0, 1, 0, 1, 0, 1}, /* PA25 FCC1_TXD0 */ - {0, 1, 0, 1, 0, 1}, /* PA24 FCC1_TXD1 */ - {0, 1, 0, 1, 0, 1}, /* PA23 FCC1_TXD2 */ - {0, 1, 0, 1, 0, 1}, /* PA22 FCC1_TXD3 */ - {0, 1, 0, 1, 0, 1}, /* PA21 FCC1_TXD4 */ - {0, 1, 0, 1, 0, 1}, /* PA20 FCC1_TXD5 */ - {0, 1, 0, 1, 0, 1}, /* PA19 FCC1_TXD6 */ - {0, 1, 0, 1, 0, 1}, /* PA18 FCC1_TXD7 */ - {0, 1, 0, 0, 0, 0}, /* PA17 FCC1_RXD7 */ - {0, 1, 0, 0, 0, 0}, /* PA16 FCC1_RXD6 */ - {0, 1, 0, 0, 0, 0}, /* PA15 FCC1_RXD5 */ - {0, 1, 0, 0, 0, 0}, /* PA14 FCC1_RXD4 */ - {0, 1, 0, 0, 0, 0}, /* PA13 FCC1_RXD3 */ - {0, 1, 0, 0, 0, 0}, /* PA12 FCC1_RXD2 */ - {0, 1, 0, 0, 0, 0}, /* PA11 FCC1_RXD1 */ - {0, 1, 0, 0, 0, 0}, /* PA10 FCC1_RXD0 */ - {0, 1, 1, 1, 0, 1}, /* PA9 TDMA1_L1TXD */ - {0, 1, 1, 0, 0, 0}, /* PA8 TDMA1_L1RXD */ - {0, 0, 0, 0, 0, 0}, /* PA7 CONFIG0 */ - {0, 1, 1, 0, 0, 1}, /* PA6 TDMA1_L1RSYNC */ - {0, 0, 0, 1, 0, 0}, /* PA5 FCC2:RxAddr[2] */ - {0, 0, 0, 1, 0, 0}, /* PA4 FCC2:RxAddr[1] */ - {0, 0, 0, 1, 0, 0}, /* PA3 FCC2:RxAddr[0] */ - {0, 0, 0, 1, 0, 0}, /* PA2 FCC2:TxAddr[0] */ - {0, 0, 0, 1, 0, 0}, /* PA1 FCC2:TxAddr[1] */ - {0, 0, 0, 1, 0, 0} /* PA0 FCC2:TxAddr[2] */ - }, - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - {0, 0, 0, 1, 0, 0}, /* PB31 FCC2_RXSOC */ - {0, 0, 0, 1, 0, 0}, /* PB30 FCC2_TXSOC */ - {0, 0, 0, 1, 0, 0}, /* PB29 FCC2_RXCLAV */ - {0, 0, 0, 0, 0, 0}, /* PB28 CONFIG2 */ - {0, 1, 1, 0, 0, 1}, /* PB27 FCC2_TXD0 */ - {0, 1, 1, 0, 0, 0}, /* PB26 FCC2_TXD1 */ - {0, 0, 0, 1, 0, 0}, /* PB25 FCC2_TXD4 */ - {0, 1, 1, 0, 0, 1}, /* PB24 FCC2_TXD5 */ - {0, 0, 0, 1, 0, 0}, /* PB23 FCC2_TXD6 */ - {0, 1, 0, 1, 0, 1}, /* PB22 FCC2_TXD7 */ - {0, 1, 0, 0, 0, 0}, /* PB21 FCC2_RXD7 */ - {0, 1, 0, 0, 0, 0}, /* PB20 FCC2_RXD6 */ - {0, 1, 0, 0, 0, 0}, /* PB19 FCC2_RXD5 */ - {0, 0, 0, 1, 0, 0}, /* PB18 FCC2_RXD4 */ - {1, 1, 0, 0, 0, 0}, /* PB17 FCC3_RX_DV */ - {1, 1, 0, 0, 0, 0}, /* PB16 FCC3_RX_ER */ - {1, 1, 0, 1, 0, 0}, /* PB15 FCC3_TX_ER */ - {1, 1, 0, 1, 0, 0}, /* PB14 FCC3_TX_EN */ - {1, 1, 0, 0, 0, 0}, /* PB13 FCC3_COL */ - {1, 1, 0, 0, 0, 0}, /* PB12 FCC3_CRS */ - {1, 1, 0, 0, 0, 0}, /* PB11 FCC3_RXD3 */ - {1, 1, 0, 0, 0, 0}, /* PB10 FCC3_RXD2 */ - {1, 1, 0, 0, 0, 0}, /* PB9 FCC3_RXD1 */ - {1, 1, 0, 0, 0, 0}, /* PB8 FCC3_RXD0 */ - {1, 1, 0, 1, 0, 1}, /* PB7 FCC3_TXD0 */ - {1, 1, 0, 1, 0, 1}, /* PB6 FCC3_TXD1 */ - {1, 1, 0, 1, 0, 1}, /* PB5 FCC3_TXD2 */ - {1, 1, 0, 1, 0, 1}, /* PB4 FCC3_TXD3 */ - {0, 0, 0, 0, 0, 0}, /* PB3 */ - {0, 0, 0, 0, 0, 0}, /* PB2 */ - {0, 0, 0, 0, 0, 0}, /* PB1 */ - {0, 0, 0, 0, 0, 0}, /* PB0 */ - }, - /* Port C configuration */ - { /* conf ppar psor pdir podr pdat */ - {0, 1, 0, 0, 0, 1}, /* PC31 CLK1 */ - {0, 0, 0, 1, 0, 0}, /* PC30 U1MASTER_N */ - {0, 1, 0, 0, 0, 1}, /* PC29 CLK3 */ - {0, 0, 0, 1, 0, 1}, /* PC28 -MT90220_RST */ - {0, 1, 0, 0, 0, 1}, /* PC27 CLK5 */ - {0, 0, 0, 1, 0, 1}, /* PC26 -QUADFALC_RST */ - {0, 1, 1, 1, 0, 1}, /* PC25 BRG4 */ - {1, 0, 0, 1, 0, 0}, /* PC24 MDIO */ - {1, 0, 0, 1, 0, 0}, /* PC23 MDC */ - {0, 1, 0, 0, 0, 1}, /* PC22 CLK10 */ - {0, 0, 0, 1, 0, 0}, /* PC21 */ - {0, 1, 0, 0, 0, 1}, /* PC20 CLK12 */ - {0, 1, 0, 0, 0, 1}, /* PC19 CLK13 */ - {1, 1, 0, 0, 0, 1}, /* PC18 CLK14 */ - {0, 1, 0, 0, 0, 0}, /* PC17 CLK15 */ - {1, 1, 0, 0, 0, 1}, /* PC16 CLK16 */ - {0, 1, 1, 0, 0, 0}, /* PC15 FCC1_TXADDR0 SLAVE */ - {0, 1, 1, 0, 0, 0}, /* PC14 FCC1_RXADDR0 SLAVE */ - {0, 1, 1, 0, 0, 0}, /* PC13 FCC1_TXADDR1 SLAVE */ - {0, 1, 1, 0, 0, 0}, /* PC12 FCC1_RXADDR1 SLAVE */ - {0, 0, 0, 1, 0, 0}, /* PC11 FCC2_RXD2 */ - {0, 0, 0, 1, 0, 0}, /* PC10 FCC2_RXD3 */ - {0, 0, 0, 1, 0, 1}, /* PC9 LTMODE */ - {0, 0, 0, 1, 0, 1}, /* PC8 SELSYNC */ - {0, 1, 1, 0, 0, 0}, /* PC7 FCC1_TXADDR2 SLAVE */ - {0, 1, 1, 0, 0, 0}, /* PC6 FCC1_RXADDR2 SLAVE */ - {0, 0, 0, 1, 0, 0}, /* PC5 FCC2_TXCLAV MASTER */ - {0, 0, 0, 1, 0, 0}, /* PC4 FCC2_RXENB MASTER */ - {0, 0, 0, 1, 0, 0}, /* PC3 FCC2_TXD2 */ - {0, 0, 0, 1, 0, 0}, /* PC2 FCC2_TXD3 */ - {0, 0, 0, 0, 0, 1}, /* PC1 PTMC -PTEENB */ - {0, 0, 0, 1, 0, 1}, /* PC0 COMCLK_N */ - }, - /* Port D configuration */ - { /* conf ppar psor pdir podr pdat */ - {0, 0, 0, 1, 0, 1}, /* PD31 -CAM_RST */ - {0, 0, 0, 1, 0, 0}, /* PD30 FCC2_TXENB */ - {0, 1, 1, 0, 0, 0}, /* PD29 FCC1_RXADDR3 SLAVE */ - {0, 1, 1, 0, 0, 1}, /* PD28 TDMC1_L1TXD */ - {0, 1, 1, 0, 0, 0}, /* PD27 TDMC1_L1RXD */ - {0, 1, 1, 0, 0, 1}, /* PD26 TDMC1_L1RSYNC */ - {0, 0, 0, 1, 0, 1}, /* PD25 LED0 -OFF */ - {0, 0, 0, 1, 0, 1}, /* PD24 LED5 -OFF */ - {1, 0, 0, 1, 0, 1}, /* PD23 -LXT971_RST */ - {0, 1, 1, 0, 0, 1}, /* PD22 TDMA2_L1TXD */ - {0, 1, 1, 0, 0, 0}, /* PD21 TDMA2_L1RXD */ - {0, 1, 1, 0, 0, 1}, /* PD20 TDMA2_L1RSYNC */ - {0, 0, 0, 1, 0, 0}, /* PD19 FCC2_TXADDR3 */ - {0, 0, 0, 1, 0, 0}, /* PD18 FCC2_RXADDR3 */ - {0, 1, 0, 1, 0, 0}, /* PD17 BRG2 */ - {0, 0, 0, 1, 0, 0}, /* PD16 */ - {0, 0, 0, 1, 0, 0}, /* PD15 PT2TO1 */ - {0, 0, 0, 1, 0, 1}, /* PD14 PT4TO3 */ - {0, 0, 0, 1, 0, 1}, /* PD13 -SWMODE */ - {0, 0, 0, 1, 0, 1}, /* PD12 -PTMODE */ - {0, 0, 0, 1, 0, 0}, /* PD11 FCC2_RXD0 */ - {0, 0, 0, 1, 0, 0}, /* PD10 FCC2_RXD1 */ - {1, 1, 0, 1, 0, 1}, /* PD9 SMC1_SMTXD */ - {1, 1, 0, 0, 0, 1}, /* PD8 SMC1_SMRXD */ - {0, 1, 1, 0, 0, 0}, /* PD7 FCC1_TXADDR3 SLAVE */ - {0, 0, 0, 1, 0, 0}, /* PD6 IMAMODE */ - {0, 0, 0, 0, 0, 0}, /* PD5 CONFIG2 */ - {0, 1, 0, 1, 0, 0}, /* PD4 BRG8 */ - {0, 0, 0, 0, 0, 0}, /* PD3 */ - {0, 0, 0, 0, 0, 0}, /* PD2 */ - {0, 0, 0, 0, 0, 0}, /* PD1 */ - {0, 0, 0, 0, 0, 0}, /* PD0 */ - } -}; - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar *base; - ulong maxsize; - int i; - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - -#ifndef CFG_RAMBOOT - immap->im_siu_conf.sc_ppc_acr = 0x00000026; - immap->im_siu_conf.sc_ppc_alrh = 0x01276345; - immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_lcl_acr = 0x00000000; - immap->im_siu_conf.sc_lcl_alrh = 0x01234567; - immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - immap->im_siu_conf.sc_ltescr1 = 0x00004000; - - /* Init Main SDRAM */ -#define OP_VALUE 0x404A241A -#define OP_VALUE_M (OP_VALUE & 0x87FFFFFF); - base = (uchar *) CFG_SDRAM_BASE; - memctl->memc_psdmr = 0x28000000 | OP_VALUE_M; - *base = 0xFF; - memctl->memc_psdmr = 0x08000000 | OP_VALUE_M; - for (i = 0; i < 8; i++) - *base = 0xFF; - memctl->memc_psdmr = 0x18000000 | OP_VALUE_M; - *(base + 0x110) = 0xFF; - memctl->memc_psdmr = OP_VALUE; - memctl->memc_lsdmr = 0x4086A522; - *base = 0xFF; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2; - - maxsize = get_ram_size((long *)base, maxsize); - - memctl->memc_or1 |= ~(maxsize - 1); - - if (maxsize != hwc_main_sdram_size ()) - printf ("Oops: memory test has not found all memory!\n"); -#endif - - icache_enable (); - /* return total ram size of SDRAM */ - return (maxsize); -} - -int checkboard (void) -{ - char string[32]; - - hwc_manufact_date (string); - - printf ("Board: Interphase 4539 (#%d %s)\n", - hwc_serial_number (), - string); - -#ifdef DEBUG - printf ("Manufacturing date: %s\n", string); - printf ("Serial number : %d\n", hwc_serial_number ()); - printf ("FLASH size : %d MB\n", hwc_flash_size () >> 20); - printf ("Main SDRAM size : %d MB\n", hwc_main_sdram_size () >> 20); - printf ("Local SDRAM size : %d MB\n", hwc_local_sdram_size () >> 20); - hwc_mac_address (string); - printf ("MAC address : %s\n", string); -#endif - - return 0; -} - -int misc_init_r (void) -{ - char *s, str[32]; - int num; - - if ((s = getenv ("serial#")) == NULL && - (num = hwc_serial_number ()) != -1) { - sprintf (str, "%06d", num); - setenv ("serial#", str); - } - if ((s = getenv ("ethaddr")) == NULL && hwc_mac_address (str) == 0) { - setenv ("ethaddr", str); - } - return (0); -} - -/*************************************************************** - * We take some basic Hardware Configuration Parameter from the - * Serial EEPROM conected to the PSpan bridge. We keep it as - * simple as possible. - */ -int hwc_flash_size (void) -{ - uchar byte; - - if (!seeprom_read (0x40, &byte, sizeof (byte))) { - switch ((byte >> 2) & 0x3) { - case 0x1: - return 0x0400000; - break; - case 0x2: - return 0x0800000; - break; - case 0x3: - return 0x1000000; - default: - return 0x0100000; - } - } - return -1; -} -int hwc_local_sdram_size (void) -{ - uchar byte; - - if (!seeprom_read (0x40, &byte, sizeof (byte))) { - switch ((byte & 0x03)) { - case 0x1: - return 0x0800000; - case 0x2: - return 0x1000000; - default: - return 0; /* not present */ - } - } - return -1; -} -int hwc_main_sdram_size (void) -{ - uchar byte; - - if (!seeprom_read (0x41, &byte, sizeof (byte))) { - return 0x1000000 << ((byte >> 5) & 0x7); - } - return -1; -} -int hwc_serial_number (void) -{ - int sn = -1; - - if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) { - sn = cpu_to_le32 (sn); - } - return sn; -} -int hwc_mac_address (char *str) -{ - char mac[6]; - - if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) { - sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - } else { - strcpy (str, "ERROR"); - return -1; - } - return 0; -} -int hwc_manufact_date (char *str) -{ - uchar byte; - int value; - - if (seeprom_read (0x92, &byte, sizeof (byte))) - goto out; - value = byte; - if (seeprom_read (0x93, &byte, sizeof (byte))) - goto out; - value += byte << 8; - sprintf (str, "%02d/%02d/%04d", - value & 0x1F, (value >> 5) & 0xF, - 1980 + ((value >> 9) & 0x1FF)); - return 0; - - out: - strcpy (str, "ERROR"); - return -1; -} - -#define PSPAN_ADDR 0xF0020000 -#define EEPROM_REG 0x408 -#define EEPROM_READ_CMD 0xA000 -#define PSPAN_WRITE(a,v) \ - *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio() -#define PSPAN_READ(a) \ - *((volatile unsigned long *)(PSPAN_ADDR+(a))) - -int seeprom_read (int addr, uchar * data, int size) -{ - ulong val, cmd; - int i; - - for (i = 0; i < size; i++) { - - cmd = EEPROM_READ_CMD; - cmd |= ((addr + i) << 24) & 0xff000000; - - /* Wait for ACT to authorize write */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - - /* Write command */ - PSPAN_WRITE (EEPROM_REG, cmd); - - /* Wait for data to be valid */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - /* Do it twice, first read might be erratic */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - - /* Read error */ - if (val & 0x00000040) { - return -1; - } else { - data[i] = (val >> 16) & 0xff; - } - } - return 0; -} diff --git a/board/iphase4539/u-boot.lds b/board/iphase4539/u-boot.lds deleted file mode 100644 index 4ea01ea..0000000 --- a/board/iphase4539/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/ispan/Makefile b/board/ispan/Makefile deleted file mode 100644 index 9123a80..0000000 --- a/board/ispan/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# Copyright (C) 2004 Arabella Software Ltd. -# Yuli Barcohen -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/ispan/config.mk b/board/ispan/config.mk deleted file mode 100644 index 4600dbb..0000000 --- a/board/ispan/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright (C) 2004 Arabella Software Ltd. -# Yuli Barcohen -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Interphase iSPAN Communications Controllers -# -#TEXT_BASE = 0xFF800000 -#TEXT_BASE = 0xFFBA0000 -TEXT_BASE = 0xFE7A0000 diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c deleted file mode 100644 index d39b8cd..0000000 --- a/board/ispan/ispan.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Interphase iSPAN Communications Controllers - * (453x and others). Tested on 4532. - * - * Derived from iSPAN 4539 port (iphase4539) by - * Wolfgang Grandegger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* - * I/O Ports configuration table - * - * If conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) -#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3) - -const iop_conf_t iop_conf_tab[4][32] = { - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 SMTXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 SMRXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - /* PC18 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 } /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */ - /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPICLK */ - /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMOSI */ - /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMISO */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* MII MDIO */ - /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MII MDC */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { CFG_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */ - /* PD5 */ { CFG_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -#define PSPAN_ADDR 0xF0020000 -#define EEPROM_REG 0x408 -#define EEPROM_READ_CMD 0xA000 -#define PSPAN_WRITE(a,v) \ - *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio() -#define PSPAN_READ(a) \ - *((volatile unsigned long *)(PSPAN_ADDR+(a))) - -static int seeprom_read (int addr, uchar * data, int size) -{ - ulong val, cmd; - int i; - - for (i = 0; i < size; i++) { - - cmd = EEPROM_READ_CMD; - cmd |= ((addr + i) << 24) & 0xff000000; - - /* Wait for ACT to authorize write */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - - /* Write command */ - PSPAN_WRITE (EEPROM_REG, cmd); - - /* Wait for data to be valid */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - /* Do it twice, first read might be erratic */ - while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) - eieio (); - - /* Read error */ - if (val & 0x00000040) { - return -1; - } else { - data[i] = (val >> 16) & 0xff; - } - } - return 0; -} - -/*************************************************************** - * We take some basic Hardware Configuration Parameter from the - * Serial EEPROM conected to the PSpan bridge. We keep it as - * simple as possible. - */ -#ifdef DEBUG -static int hwc_flash_size (void) -{ - uchar byte; - - if (!seeprom_read (0x40, &byte, sizeof (byte))) { - switch ((byte >> 2) & 0x3) { - case 0x1: - return 0x0400000; - break; - case 0x2: - return 0x0800000; - break; - case 0x3: - return 0x1000000; - default: - return 0x0100000; - } - } - return -1; -} - -static int hwc_local_sdram_size (void) -{ - uchar byte; - - if (!seeprom_read (0x40, &byte, sizeof (byte))) { - switch ((byte & 0x03)) { - case 0x1: - return 0x0800000; - case 0x2: - return 0x1000000; - default: - return 0; /* not present */ - } - } - return -1; -} -#endif /* DEBUG */ - -static int hwc_main_sdram_size (void) -{ - uchar byte; - - if (!seeprom_read (0x41, &byte, sizeof (byte))) { - return 0x1000000 << ((byte >> 5) & 0x7); - } - return -1; -} - -static int hwc_serial_number (void) -{ - int sn = -1; - - if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) { - sn = cpu_to_le32 (sn); - } - return sn; -} - -static int hwc_mac_address (char *str) -{ - char mac[6]; - - if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) { - sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - } else { - strcpy (str, "ERROR"); - return -1; - } - return 0; -} - -static int hwc_manufact_date (char *str) -{ - uchar byte; - int value; - - if (seeprom_read (0x92, &byte, sizeof (byte))) - goto out; - value = byte; - if (seeprom_read (0x93, &byte, sizeof (byte))) - goto out; - value += byte << 8; - sprintf (str, "%02d/%02d/%04d", - value & 0x1F, (value >> 5) & 0xF, - 1980 + ((value >> 9) & 0x1FF)); - return 0; - -out: - strcpy (str, "ERROR"); - return -1; -} - -static int hwc_board_type (char **str) -{ - ushort id = 0; - - if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) { - switch (id) { - case 0x9080: - *str = "4532-002"; - break; - case 0x9081: - *str = "4532-001"; - break; - case 0x9082: - *str = "4532-000"; - break; - default: - *str = "Unknown"; - } - } else { - *str = "Unknown"; - } - - return id; -} - -long int initdram (int board_type) -{ - long maxsize = hwc_main_sdram_size(); - -#if !defined(CFG_RAMBOOT) && !defined(CFG_USE_FIRMWARE) - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar *base; - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x00000026; - immap->im_siu_conf.sc_ppc_alrh = 0x01276345; - immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_lcl_acr = 0x00000000; - immap->im_siu_conf.sc_lcl_alrh = 0x01234567; - immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - immap->im_siu_conf.sc_ltescr1 = 0x00004000; - - memctl->memc_mptpr = CFG_MPTPR; - - /* Initialise 60x bus SDRAM */ - base = (uchar *)(CFG_SDRAM_BASE | 0x110); - memctl->memc_psrt = CFG_PSRT; - memctl->memc_or1 = CFG_60x_OR; - memctl->memc_br1 = CFG_SDRAM_BASE | CFG_60x_BR; - - memctl->memc_psdmr = CFG_PSDMR | 0x28000000; - *base = 0xFF; - memctl->memc_psdmr = CFG_PSDMR | 0x08000000; - for (i = 0; i < 8; i++) - *base = 0xFF; - memctl->memc_psdmr = CFG_PSDMR | 0x18000000; - *base = 0xFF; - memctl->memc_psdmr = CFG_PSDMR | 0x40000000; - - /* Initialise local bus SDRAM */ - base = (uchar *)CFG_LSDRAM_BASE; - memctl->memc_lsrt = CFG_LSRT; - memctl->memc_or2 = CFG_LOC_OR; - memctl->memc_br2 = CFG_LSDRAM_BASE | CFG_LOC_BR; - - memctl->memc_lsdmr = CFG_LSDMR | 0x28000000; - *base = 0xFF; - memctl->memc_lsdmr = CFG_LSDMR | 0x08000000; - for (i = 0; i < 8; i++) - *base = 0xFF; - memctl->memc_lsdmr = CFG_LSDMR | 0x18000000; - *base = 0xFF; - memctl->memc_lsdmr = CFG_LSDMR | 0x40000000; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2; - - maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize); - - memctl->memc_or1 |= ~(maxsize - 1); - - if (maxsize != hwc_main_sdram_size()) - puts("Oops: memory test has not found all memory!\n"); -#endif /* !CFG_RAMBOOT && !CFG_USE_FIRMWARE */ - - /* Return total RAM size (size of 60x SDRAM) */ - return maxsize; -} - -int checkboard(void) -{ - char string[32], *id; - - hwc_manufact_date(string); - hwc_board_type(&id); - printf("Board: Interphase iSPAN %s (#%d %s)\n", - id, hwc_serial_number(), string); -#ifdef DEBUG - printf("Manufacturing date: %s\n", string); - printf("Serial number : %d\n", hwc_serial_number()); - printf("FLASH size : %d MB\n", hwc_flash_size() >> 20); - printf("Main SDRAM size : %d MB\n", hwc_main_sdram_size() >> 20); - printf("Local SDRAM size : %d MB\n", hwc_local_sdram_size() >> 20); - hwc_mac_address(string); - printf("MAC address : %s\n", string); -#endif - return 0; -} - -int misc_init_r(void) -{ - char *s, str[32]; - int num; - - if ((s = getenv("serial#")) == NULL && - (num = hwc_serial_number()) != -1) { - sprintf(str, "%06d", num); - setenv("serial#", str); - } - if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) { - setenv("ethaddr", str); - } - - return 0; -} diff --git a/board/ispan/u-boot.lds b/board/ispan/u-boot.lds deleted file mode 100644 index bf8048d..0000000 --- a/board/ispan/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Yuli Barcohen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/ivm/Makefile b/board/ivm/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/ivm/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/ivm/config.mk b/board/ivm/config.mk deleted file mode 100644 index 37e7185..0000000 --- a/board/ivm/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# IVM boards -# - -TEXT_BASE = 0xFF000000 diff --git a/board/ivm/flash.c b/board/ivm/flash.c deleted file mode 100644 index 140ba2d..0000000 --- a/board/ivm/flash.c +++ /dev/null @@ -1,598 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \ - BR_MS_GPCM | BR_PS_16 | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_MT: - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00020000); - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - return; - - case FLASH_MAN_SST: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00002000); - } - return; - - case FLASH_MAN_AMD: - case FLASH_MAN_FUJ: - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - return; - default: - printf ("Don't know sector ofsets for flash type 0x%lx\n", - info->flash_id); - return; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_MT: printf ("MT "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n"); - break; - case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n"); - break; - case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n"); - break; - case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n"); - break; - case FLASH_28F008S5: printf ("28F008S5 (1M = 64K x 16)\n"); - break; - case FLASH_28F400_T: printf ("28F400B3 (4Mbit, top boot sector)\n"); - break; - case FLASH_28F400_B: printf ("28F400B3 (4Mbit, bottom boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - ushort value; - vu_short *saddr = (vu_short *)addr; - - /* Read Manufacturer ID */ - saddr[0] = 0x0090; - value = saddr[0]; - - switch (value) { - case (AMD_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (SST_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_SST; - break; - case (STM_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_STM; - break; - case (MT_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_MT; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - saddr[0] = 0x00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = saddr[1]; /* device ID */ - - switch (value) { - case (AMD_ID_LV400T & 0xFFFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & 0xFFFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & 0xFFFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & 0xFFFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160T & 0xFFFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & 0xFFFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFFFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_LV320B & 0xFFFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case (SST_ID_xF200A & 0xFFFF): - info->flash_id += FLASH_SST200A; - info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */ - info->size = 0x00080000; - break; - case (SST_ID_xF400A & 0xFFFF): - info->flash_id += FLASH_SST400A; - info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */ - info->size = 0x00100000; - break; - case (SST_ID_xF800A & 0xFFFF): - info->flash_id += FLASH_SST800A; - info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */ - info->size = 0x00200000; - break; /* => 2 MB */ - case (STM_ID_x800AB & 0xFFFF): - info->flash_id += FLASH_STM800AB; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - case (MT_ID_28F400_T & 0xFFFF): - info->flash_id += FLASH_28F400_T; - info->sector_count = 7; - info->size = 0x00080000; - break; /* => 512 kB */ - case (MT_ID_28F400_B & 0xFFFF): - info->flash_id += FLASH_28F400_B; - info->sector_count = 7; - info->size = 0x00080000; - break; /* => 512 kB */ - default: - info->flash_id = FLASH_UNKNOWN; - saddr[0] = 0x00FF; /* restore read mode */ - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - saddr[0] = 0x00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MT) { - printf ("Can erase only MT flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *)(info->start[sect]); - unsigned short status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = 0x0050; /* clear status register */ - *addr = 0x0020; /* erase setup */ - *addr = 0x00D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & 0x0080) != 0x0080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0x00FF; /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = 0x00FF; /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 2 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= FLASH_WIDTH) { - data = 0; - for (i=0; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i CFG_FLASH_WRITE_TOUT) { - *addr = 0x00FF; /* restore read mode */ - return (1); - } - } - - *addr = 0x00FF; /* restore read mode */ - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c deleted file mode 100644 index 7927ea9..0000000 --- a/board/ivm/ivm.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_STATUS_LED -# include -#endif - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -/* - * 50 MHz SHARC access using UPM A - */ -const uint sharc_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04, - 0xFFFFEC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04, - 0xFFFFEC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -/* - * 50 MHz SDRAM access using UPM B - */ -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */ - _NOT_USED_, - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00, - 0xE1BBBC04, 0x1FF77C45, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84, - 0xFFFFFC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ -#ifdef CONFIG_IVMS8 - puts ("Board: IVMS8\n"); -#endif -#ifdef CONFIG_IVML24 - puts ("Board: IVM-L8/24\n"); -#endif - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - long int size_b0; - - /* enable SDRAM clock ("switch on" SDRAM) */ - immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */ - immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE; /* output */ - immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE; /* assert SDRAM CLKE */ - udelay (1); - - /* - * Map controller bank 1 for ELIC SACCO - */ - memctl->memc_or1 = CFG_OR1; - memctl->memc_br1 = CFG_BR1; - - /* - * Map controller bank 2 for ELIC EPIC - */ - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; - - /* - * Configure UPMA for SHARC - */ - upmconfig (UPMA, (uint *) sharc_table, - sizeof (sharc_table) / sizeof (uint)); - -#if defined(CONFIG_IVML24) - /* - * Map controller bank 4 for HDLC Address space - */ - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; -#endif - - /* - * Map controller bank 5 for SHARC - */ - memctl->memc_or5 = CFG_OR5; - memctl->memc_br5 = CFG_BR5; - - memctl->memc_mamr = 0x00001000; - - /* - * Configure UPMB for SDRAM - */ - upmconfig (UPMB, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = CFG_MPTPR_1BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - - memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ - - udelay (200); - memctl->memc_mcr = 0x80806105; /* precharge */ - udelay (1); - memctl->memc_mcr = 0x80806106; /* load mode register */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80806130; /* autorefresh */ - - memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ - - /* - * Check Bank 0 Memory Size for re-configuration - */ - size_b0 = - dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); - - memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE; - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - memctl->memc_mbmr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -void reset_phy (void) -{ - immap_t *immr = (immap_t *) CFG_IMMR; - - /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */ - immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN; /* output */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ - udelay (1000); - - /* - * RESET is implemented by a positive pulse of at least 1 us - * at the reset pin. - * - * Configure RESET pins for NS DP83843 PHY, and RESET chip. - * - * Note: The RESET pin is high active, but there is an - * inverter on the SPD823TS board... - */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET); - immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET; - /* assert RESET signal of PHY */ - immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET); - udelay (10); - /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET; - udelay (10); -} - -/* ------------------------------------------------------------------------- */ - -void show_boot_progress (int status) -{ -#if defined(CONFIG_STATUS_LED) -# if defined(STATUS_LED_YELLOW) - status_led_set (STATUS_LED_YELLOW, - (status < 0) ? STATUS_LED_ON : STATUS_LED_OFF); -# endif /* STATUS_LED_YELLOW */ -# if defined(STATUS_LED_BOOT) - if (status == 6) - status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF); -# endif /* STATUS_LED_BOOT */ -#endif /* CONFIG_STATUS_LED */ -} - -/* ------------------------------------------------------------------------- */ - -void ide_set_reset (int on) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - /* - * Configure PC for IDE Reset Pin - */ - if (on) { /* assert RESET */ - immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); - } else { /* release RESET */ - immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; - } - - /* program port pin as GPIO output */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds deleted file mode 100644 index fdeabc5..0000000 --- a/board/ivm/u-boot.lds +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - common/environment.o(.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug deleted file mode 100644 index 3214f3f..0000000 --- a/board/ivm/u-boot.lds.debug +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/ixdp425/Makefile b/board/ixdp425/Makefile deleted file mode 100644 index e4282c4..0000000 --- a/board/ixdp425/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := ixdp425.o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/ixdp425/config.mk b/board/ixdp425/config.mk deleted file mode 100644 index 9f616f3..0000000 --- a/board/ixdp425/config.mk +++ /dev/null @@ -1,2 +0,0 @@ -#TEXT_BASE = 0x00100000 -TEXT_BASE = 0x00f80000 diff --git a/board/ixdp425/flash.c b/board/ixdp425/flash.c deleted file mode 100644 index 1d958c8..0000000 --- a/board/ixdp425/flash.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) x -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _bss_start - _armboot_start, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = (FPW) 0x00500050; /* clear status register cmd. */ - *addr = (FPW) 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c deleted file mode 100644 index c04626a..0000000 --- a/board/ixdp425/ixdp425.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - - -/* local prototypes */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -/**********************************************************/ - -int board_post_init (void) -{ - return (0); -} - -/**********************************************************/ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* arch number of IXDP */ - gd->bd->bi_arch_number = MACH_TYPE_IXDP425; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - return 0; -} - -/**********************************************************/ - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} - -/**********************************************************/ - -extern struct pci_controller hose; -extern void pci_ixp_init(struct pci_controller * hose); - -void pci_init_board(void) -{ - extern void pci_ixp_init (struct pci_controller *hose); - - pci_ixp_init(&hose); -} diff --git a/board/ixdp425/u-boot.lds b/board/ixdp425/u-boot.lds deleted file mode 100644 index e2ceac7..0000000 --- a/board/ixdp425/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/ixp/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/jse/Makefile b/board/jse/Makefile deleted file mode 100644 index 0da27b6..0000000 --- a/board/jse/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2004 Picture Elements, Inc. -# Stephen Williams -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o sdram.o flash.o host_bridge.o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/jse/README.txt b/board/jse/README.txt deleted file mode 100644 index 84497db..0000000 --- a/board/jse/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -JSE Configuration Details - -Memory Bank 0 -- Flash chip ---------------------------- - -0xfff00000 - 0xffffffff - -The flash chip is really only 512Kbytes, but the high address bit of -the 1Meg region is ignored, so the flash is replicated through the -region. Thus, this is consistent with a flash base address 0xfff80000. - -The placement at the end is to be consistent with reset behavior, -where the processor itself initially uses this bus to load the branch -vector and start running. - -On-Chip Memory --------------- - -0xf4000000 - 0xf4000fff - -The 405GPr includes a 4K on-chip memory that can be placed however -software chooses. I choose to place the memory at this address, to -keep it out of the cachable areas. - - -Memory Bank 1 -- SystemACE Controller -------------------------------------- - -0xf0000000 - 0xf00fffff - -The SystemACE chip is along on peripheral bank CS#1. We don't need -much space, but 1Meg is the smallest we can configure the chip to -allocate. We need it far away from the flash region, because this -region is set to be non-cached. - - -Internal Peripherals --------------------- - -0xef600300 - 0xef6008ff - -These are scattered various peripherals internal to the PPC405GPr -chip. - -SDRAM ------ - -0x00000000 - 0x07ffffff (128 MBytes) diff --git a/board/jse/config.mk b/board/jse/config.mk deleted file mode 100644 index 03ec085..0000000 --- a/board/jse/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2003 Picture Elements, Inc. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Picture Elements, Inc. JSE boards -# - -TEXT_BASE = 0xFFF80000 diff --git a/board/jse/flash.c b/board/jse/flash.c deleted file mode 100644 index c462fe0..0000000 --- a/board/jse/flash.c +++ /dev/null @@ -1,520 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include -#include -#include - -#if CFG_MAX_FLASH_BANKS != 1 -#error "CFG_MAX_FLASH_BANKS must be 1" -#endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - - /* Init: no FLASHes known */ - flash_info[0].flash_id = FLASH_UNKNOWN; - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - /* Setup offsets */ - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM, - FLASH_BASE0_PRELIM + monitor_flash_len - 1, - &flash_info[0]); - flash_info[0].size = size_b0; - - return size_b0; -} - - -/*----------------------------------------------------------------------- - */ -/* - * This implementation assumes that the flash chips are uniform sector - * devices. This is true for all likely JSE devices. - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - unsigned idx; - unsigned long sector_size = info->size / info->sector_count; - - for (idx = 0; idx < info->sector_count; idx += 1) { - info->start[idx] = base + (idx * sector_size); - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("ST Micro "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* (Reduced table of only parts expected in JSE boards.) */ - switch (info->flash_id) { - case FLASH_MAN_AMD | FLASH_AM040: - printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_MAN_STM | FLASH_AM040: - printf ("MM29W040W (512 Kbit, uniform sector size)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *) info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; - - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - printf("Unknown flash manufacturer code: 0x%x\n", value); - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele JSE chip */ - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* Calculate the sector offsets (Use JSE Optimized code). */ - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7 (flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = - (FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); - printf ("Erasing sector %p\n", addr2); /* CLH */ - - if ((info->flash_id & FLASH_VENDMASK) == - FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay (1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7 (info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7 (info, l_sect); - -DONE: -#endif - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = - (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/jse/host_bridge.c b/board/jse/host_bridge.c deleted file mode 100644 index 363be97..0000000 --- a/board/jse/host_bridge.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2004 Picture Elements, Inc. - * Stephen Williams (steve@icarus.com) - * - * This source code is free software; you can redistribute it - * and/or modify it in source code form under the terms of the GNU - * General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ -#ident "$Id:$" - -# include -# include -# include "jse_priv.h" - -/* - * The JSE board has an Intel 21555 non-transparent bridge for - * communication with the host. We need to render it harmless on the - * JSE side, but leave it alone on the host (primary) side. Normally, - * this will all be done before the host BIOS can gain access to the - * board, due to the Primary Access Lockout bit. - * - * The host_bridge_init function is called as a late initialization - * function, after most of the board is set up, including a PCI scan. - */ - -void host_bridge_init (void) -{ - /* The bridge chip is at a fixed location. */ - pci_dev_t dev = PCI_BDF (0, 10, 0); - - /* Set PCI Class code -- - The primary side sees this class code at 0x08 in the - primary config space. This must be something other then a - bridge, or MS Windows starts doing weird stuff to me. */ - pci_write_config_dword (dev, 0x48, 0x04800000); - - /* Set subsystem ID -- - The primary side sees this value at 0x2c. We set it here so - that the host can tell what sort of device this is: - We are a Picture Elements [0x12c5] JSE [0x008a]. */ - pci_write_config_dword (dev, 0x6c, 0x008a12c5); - - /* Downstream (Primary-to-Secondary) BARs are set up mostly - off. We need only the Memory-0 Bar so that the host can get - at the CSR region to set up tables and the lot. */ - - /* Downstream Memory 0 setup (4K for CSR) */ - pci_write_config_dword (dev, 0xac, 0xfffff000); - /* Downstream Memory 1 setup (off) */ - pci_write_config_dword (dev, 0xb0, 0x00000000); - /* Downstream Memory 2 setup (off) */ - pci_write_config_dword (dev, 0xb4, 0x00000000); - /* Downstream Memory 3 setup (off) */ - pci_write_config_dword (dev, 0xb8, 0x00000000); - - /* Upstream (Secondary-to-Primary) BARs are used to get at - host memory from the JSE card. Create two regions: a small - one to manage individual word reads/writes, and a larger - one for doing bulk frame moves. */ - - /* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */ - pci_write_config_dword (dev, 0xc4, 0xfffff000); - /* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */ - pci_write_config_dword (dev, 0xc8, 0xfffff000); - - /* Upstream Memory 2 (BAR4) uses page translation, and is set - up in CCR1. Configure for 4K pages. */ - - /* Set CCR1,0 reigsters. This clears the Primary PCI Lockout - bit as well, so we are done configuring after this - point. Therefore, this must be the last step. - - CC1[15:12]= 0 (disable I2O message unit) - CC1[11:8] = 0x5 (4K page size) - CC0[11] = 1 (Secondary Clock Disable: disable clock) - CC0[10] = 0 (Primary Access Lockout: allow primary access) - */ - pci_write_config_dword (dev, 0xcc, 0x05000800); -} diff --git a/board/jse/init.S b/board/jse/init.S deleted file mode 100644 index 231cd1c..0000000 --- a/board/jse/init.S +++ /dev/null @@ -1,105 +0,0 @@ -/*------------------------------------------------------------------------+ */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------- */ - -/*------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* */ -/* */ -/* The layout for the PEI JSE board: */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - SystemACE */ -/* Bank 2 - not used */ -/* Bank 3 - not used */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - not used */ -/*------------------------------------------------------------------------- */ -#include - -#include -#include - -#include -#include - -#define cpc0_cr0 0xB1 - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ - - /*----------------------------------------------------------------- */ - /* Delay to ensure all accesses to ROM are complete before changing */ - /* bank 0 timings. 200usec should be enough. */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*----------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /*----------------------------------------------------------------- */ - /* Memory Bank 0 (Flash) initialization */ - /*----------------------------------------------------------------- */ - - addi r4,0,pb0ap - mtdcr ebccfga,r4 - addis r4,0,0x9B01 - ori r4,r4,0x5480 - mtdcr ebccfgd,r4 - - addi r4,0,pb0cr - mtdcr ebccfga,r4 - addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr ebccfgd,r4 - - blr - - -/*----------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: This function is called by cpu/ppc4xx/start.S code */ -/* to get the SDRAM initialized. */ -/*----------------------------------------------------------------------- */ - .globl sdram_init -sdram_init: - blr diff --git a/board/jse/jse.c b/board/jse/jse.c deleted file mode 100644 index 9290814..0000000 --- a/board/jse/jse.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (c) 2004 Picture Elements, Inc. - * Stephen Williams (steve@icarus.com) - * - * This source code is free software; you can redistribute it - * and/or modify it in source code form under the terms of the GNU - * General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ - -# include -# include -# include -# include -# include "jse_priv.h" - -/* - * This function is run very early, out of flash, and before devices are - * initialized. It is called by lib_ppc/board.c:board_init_f by virtue - * of being in the init_sequence array. - * - * The SDRAM has been initialized already -- start.S:start called - * init.S:init_sdram early on -- but it is not yet being used for - * anything, not even stack. So be careful. - */ -int board_early_init_f (void) -{ - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the JSE board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED/UNUSED - | IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive - | IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive - | IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive - | IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive - | IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high - | IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused) - | IRQ 31 (EXT IRQ 6) (unused) - +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* Configure the interface to the SystemACE MCU port. - The SystemACE is fast, but there is no reason to have - excessivly tight timings. So the settings are slightly - generous. */ - - /* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1, - WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, 0x01011000); - - /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */ - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, CFG_SYSTEMACE_BASE | 0x00018000); - - /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */ - /* CPC0_CR1 |= PCIPW */ - mtdcr (0xb2, mfdcr (0xb2) | 0x00004000); - - return 0; -} - -#ifdef CONFIG_BOARD_PRE_INIT -int board_pre_init (void) -{ - return board_early_init_f (); -} - -#endif - -/* - * This function is also called by lib_ppc/board.c:board_init_f (it is - * also in the init_sequence array) but later. Many more things are - * configured, but we are still running from flash. - */ -int checkboard (void) -{ - unsigned vers, status; - - /* check that the SystemACE chip is alive. */ - printf ("ACE: "); - vers = readw (CFG_SYSTEMACE_BASE + 0x16); - printf ("SystemACE %u.%u (build %u)", - (vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff); - - status = readl (CFG_SYSTEMACE_BASE + 0x04); -#ifdef DEBUG - printf (" STATUS=0x%08x", status); -#endif - /* If the flash card is present and there is an initial error, - then force a restart of the program. */ - if (status & 0x00000010) { - printf (" CFDETECT"); - - if (status & 0x04) { - /* CONTROLREG = CFGPROG */ - writew (0x1000, CFG_SYSTEMACE_BASE + 0x18); - udelay (500); - /* CONTROLREG = CFGRESET */ - writew (0x0080, CFG_SYSTEMACE_BASE + 0x18); - udelay (500); - writew (0x0000, CFG_SYSTEMACE_BASE + 0x18); - /* CONTROLREG = CFGSTART */ - writew (0x0020, CFG_SYSTEMACE_BASE + 0x18); - - status = readl (CFG_SYSTEMACE_BASE + 0x04); - } - } - - /* Wait for the SystemACE to program its chain of devices. */ - while ((status & 0x84) == 0x00) { - udelay (500); - status = readl (CFG_SYSTEMACE_BASE + 0x04); - } - - if (status & 0x04) - printf (" CFG-ERROR"); - if (status & 0x80) - printf (" CFGDONE"); - - printf ("\n"); - - /* Force /RTS to active. The board it not wired quite - correctly to use cts/rtc flow control, so just force the - /RST active and forget about it. */ - writeb (readb (0xef600404) | 0x03, 0xef600404); - - printf ("JSE: ready\n"); - - return 0; -} - -/* **** No more functions called by board_init_f. **** */ - -/* - * This function is called by lib_ppc/board.c:board_init_r. At this - * point, basic setup is done, U-Boot has been moved into SDRAM and - * PCI has been set up. From here we done late setup. - */ -int misc_init_r (void) -{ - host_bridge_init (); - return 0; -} diff --git a/board/jse/jse_priv.h b/board/jse/jse_priv.h deleted file mode 100644 index ed4894b..0000000 --- a/board/jse/jse_priv.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __jse_priv_H -#define __jse_prov_H -/* - * Copyright (c) 2004 Picture Elements, Inc. - * Stephen Williams (steve@icarus.com) - * - * This source code is free software; you can redistribute it - * and/or modify it in source code form under the terms of the GNU - * General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ - -extern void host_bridge_init(void); - -#endif diff --git a/board/jse/sdram.c b/board/jse/sdram.c deleted file mode 100644 index 9060d97..0000000 --- a/board/jse/sdram.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2004 Picture Elements, Inc. - * Stephen Williams (steve@icarus.com) - * - * This source code is free software; you can redistribute it - * and/or modify it in source code form under the terms of the GNU - * General Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ - -#include -#include -#include - -# define SDRAM_LEN 0x08000000 - -/* - * this is even after checkboard. It returns the size of the SDRAM - * that we have installed. This function is called by board_init_f - * in lib_ppc/board.c to initialize the memory and return what I - * found. - */ -long int initdram (int board_type) -{ - /* Configure the SDRAMS */ - - /* disable memory controller */ - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, 0x00000000); - - udelay (500); - - /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ - mtdcr (memcfga, mem_besra); - mtdcr (memcfgd, 0xffffffff); - - /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ - mtdcr (memcfga, mem_besrb); - mtdcr (memcfgd, 0xffffffff); - - /* Clear SDRAM0_ECCCFG (disable ECC) */ - mtdcr (memcfga, mem_ecccf); - mtdcr (memcfgd, 0x00000000); - - /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ - mtdcr (memcfga, mem_eccerr); - mtdcr (memcfgd, 0xffffffff); - - /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, 0x010a4016); - - /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, 0x00084001); - - /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */ - mtdcr (memcfga, mem_mb1cf); - mtdcr (memcfgd, 0x04084001); - - /* Memory Bank 2 Config == BE=0 */ - mtdcr (memcfga, mem_mb2cf); - mtdcr (memcfgd, 0x00000000); - - /* Memory Bank 3 Config == BE=0 */ - mtdcr (memcfga, mem_mb3cf); - mtdcr (memcfgd, 0x00000000); - - /* refresh timer = 0x400 */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, 0x04000000); - - /* Power management idle timer set to the default. */ - mtdcr (memcfga, mem_pmit); - mtdcr (memcfgd, 0x07c00000); - - udelay (500); - - /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */ - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, 0x80e00000); - - return SDRAM_LEN; -} - -/* - * The U-Boot core, as part of the initialization to prepare for - * loading the monitor into SDRAM, requests of this function that the - * memory be tested. Return 0 if the memory tests OK. - */ -int testdram (void) -{ - unsigned long idx; - unsigned val; - unsigned errors; - volatile unsigned long *sdram; - -#ifdef DEBUG - printf ("SDRAM Controller Registers --\n"); - - mtdcr (memcfga, mem_mcopt1); - val = mfdcr (memcfgd); - printf (" SDRAM0_CFG : 0x%08x\n", val); - - mtdcr (memcfga, 0x24); - val = mfdcr (memcfgd); - printf (" SDRAM0_STATUS: 0x%08x\n", val); - - mtdcr (memcfga, mem_mb0cf); - val = mfdcr (memcfgd); - printf (" SDRAM0_B0CR : 0x%08x\n", val); - - mtdcr (memcfga, mem_mb1cf); - val = mfdcr (memcfgd); - printf (" SDRAM0_B1CR : 0x%08x\n", val); - - mtdcr (memcfga, mem_sdtr1); - val = mfdcr (memcfgd); - printf (" SDRAM0_TR : 0x%08x\n", val); - - mtdcr (memcfga, mem_rtr); - val = mfdcr (memcfgd); - printf (" SDRAM0_RTR : 0x%08x\n", val); -#endif - - /* Wait for memory to be ready by testing MRSCMPbit - bit. Really, there should already have been plenty of time, - given it was started long ago. But, best to check. */ - for (idx = 0; idx < 1000000; idx += 1) { - mtdcr (memcfga, 0x24); - val = mfdcr (memcfgd); - if (val & 0x80000000) - break; - } - - if (!(val & 0x80000000)) { - printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n"); - return 1; - } - - /* Start memory test. */ - printf ("test: %u MB - ", SDRAM_LEN / 1048576); - - sdram = (unsigned long *) CFG_SDRAM_BASE; - - printf ("write - "); - for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) { - sdram[idx + 0] = idx; - sdram[idx + 1] = ~idx; - } - - printf ("read - "); - errors = 0; - for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) { - if (sdram[idx + 0] != idx) - errors += 1; - if (sdram[idx + 1] != ~idx) - errors += 1; - if (errors > 0) - break; - } - - if (errors > 0) { - printf ("NOT OK\n"); - printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n", - sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx); - return 1; - } - - printf ("ok\n"); - return 0; -} diff --git a/board/jse/u-boot.lds b/board/jse/u-boot.lds deleted file mode 100644 index 60c1115..0000000 --- a/board/jse/u-boot.lds +++ /dev/null @@ -1,143 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : { - /* The start.o file includes the initial jump vector that - must be located in the beginning. It is the basic run- - time function that calls all other functions. */ - cpu/ppc4xx/start.o (.text) - - board/jse/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/kb9202/Makefile b/board/kb9202/Makefile deleted file mode 100644 index f36d88d..0000000 --- a/board/kb9202/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Adapted for KwikByte KB920x boards - APR2005 -# -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := kb9202.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/kb9202/config.mk b/board/kb9202/config.mk deleted file mode 100644 index 9ce161e..0000000 --- a/board/kb9202/config.mk +++ /dev/null @@ -1 +0,0 @@ -TEXT_BASE = 0x21f00000 diff --git a/board/kb9202/kb9202.c b/board/kb9202/kb9202.c deleted file mode 100644 index 4a7cf77..0000000 --- a/board/kb9202/kb9202.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Adapted for KwikByte KB920x board from at91rm9200dk.c: 22APR2005 - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -void lowlevel_init(void) { - /* Required by assembly functions - do nothing */ -} - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Enable Ctrlc */ - console_init_f (); - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - gd->bd->bi_arch_number = MACH_TYPE_KB9200; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) - -unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac); -UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac); -UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac); -UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status); - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = lxt972_InitPhy; - p_phyops->IsPhyConnected = lxt972_IsPhyConnected; - p_phyops->GetLinkSpeed = lxt972_GetLinkSpeed; - p_phyops->AutoNegotiate = lxt972_AutoNegotiate; -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/kb9202/u-boot.lds b/board/kb9202/u-boot.lds deleted file mode 100644 index 76df6b2..0000000 --- a/board/kb9202/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/kup/Makefile b/board/kup/Makefile deleted file mode 100644 index 071f0d2..0000000 --- a/board/kup/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o kup.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/kup/common/flash.c b/board/kup/common/flash.c deleted file mode 100644 index 903c88f..0000000 --- a/board/kup/common/flash.c +++ /dev/null @@ -1,515 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -#endif - -#define CONFIG_FLASH_16BIT - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - vu_short *s_addr=(vu_short*)addr; - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x0090; - - value = s_addr[0]; - value = value|(value<<16); - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = s_addr[1]; - value = value|(value<<16); - - switch (value) { - case FUJI_ID_29F800BA: - info->flash_id += FLASH_AM400T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - s_addr = (volatile unsigned short *)(info->start[i]); - info->protect[i] = s_addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - s_addr = (volatile unsigned short *)info->start[0]; - *s_addr = 0x00F0; /* reset bank */ - } - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect; - ulong start, now, last; -#ifdef CONFIG_FLASH_16BIT - vu_short *s_addr = (vu_short*)addr; -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } -/*#ifndef CONFIG_FLASH_16BIT - ulong type; - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return; - } -#endif*/ - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ -#ifdef CONFIG_FLASH_16BIT - vu_short *s_sect_addr = (vu_short*)(info->start[sect]); -#else - vu_long *sect_addr = (vu_long*)(info->start[sect]); -#endif - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#ifdef CONFIG_FLASH_16BIT - - /*printf("\ns_sect_addr=%x",s_sect_addr);*/ - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x0080; - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_sect_addr[0] = 0x0030; -#else - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - addr[0x5555] = 0x00800080; - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - sect_addr[0] = 0x00300030; -#endif - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#ifdef CONFIG_FLASH_16BIT - while ((s_sect_addr[0] & 0x0080) != 0x0080) { -#else - while ((sect_addr[0] & 0x00800080) != 0x00800080) { -#endif - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - } - } - - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#ifdef CONFIG_FLASH_16BIT - s_addr[0] = 0x00F0; /* reset bank */ -#else - addr[0] = 0x00F000F0; /* reset bank */ -#endif - - printf (" done\n"); - return 0; -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - -#ifdef CONFIG_FLASH_16BIT - vu_short high_data; - vu_short low_data; - vu_short *s_addr = (vu_short*)addr; -#endif - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - -#ifdef CONFIG_FLASH_16BIT - /* Write the 16 higher-bits */ - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - high_data = ((data>>16) & 0x0000ffff); - - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x00A0; - - *((vu_short *)dest) = high_data; - - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - - /* Write the 16 lower-bits */ -#endif - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); -#ifdef CONFIG_FLASH_16BIT - dest += 0x2; - low_data = (data & 0x0000ffff); - - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x00A0; - *((vu_short *)dest) = low_data; - -#else - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - addr[0x5555] = 0x00A000A0; - *((vu_long *)dest) = data; -#endif - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - -#ifdef CONFIG_FLASH_16BIT - while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) { -#else - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { -#endif - - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/kup/common/kup.c b/board/kup/common/kup.c deleted file mode 100644 index d018e3c..0000000 --- a/board/kup/common/kup.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2004 - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "kup.h" - -int misc_init_f (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile sysconf8xx_t *siu = &immap->im_siu_conf; - - while (siu->sc_sipend & 0x20000000) { - /* printf("waiting for 5V VCC\n"); */ - ; - } - - /* RS232 / RS485 default is RS232 */ - immap->im_ioport.iop_padat &= ~(PA_RS485); - immap->im_ioport.iop_papar &= ~(PA_RS485); - immap->im_ioport.iop_paodr &= ~(PA_RS485); - immap->im_ioport.iop_padir |= (PA_RS485); - return (0); -} - - -#ifdef CONFIG_IDE_LED -void ide_led (uchar led, uchar status) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - /* We have one led for both pcmcia slots */ - if (status) { /* led on */ - immap->im_ioport.iop_padat &= ~(PA_LED_YELLOW); - } else { - immap->im_ioport.iop_padat |= (PA_LED_YELLOW); - } -} -#endif - -void poweron_key (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - immap->im_ioport.iop_pcpar &= ~(PC_SWITCH1); - immap->im_ioport.iop_pcdir &= ~(PC_SWITCH1); - - if (immap->im_ioport.iop_pcdat & (PC_SWITCH1)) - setenv ("key1", "off"); - else - setenv ("key1", "on"); -} - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed (void) -{ - return (0); -} -#endif diff --git a/board/kup/common/kup.h b/board/kup/common/kup.h deleted file mode 100644 index 70d7f01..0000000 --- a/board/kup/common/kup.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2004 - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __KUP_H -#define __KUP_H - -#define PA_8 0x0080 -#define PA_11 0x0010 -#define PA_12 0x0008 - -#define PB_14 0x00020000 -#define PB_17 0x00004000 - -#define PC_9 0x0040 - -#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ -#define PA_LED_YELLOW PA_8 -#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off*/ -#define PB_LCD_PWM PB_17 /* PB 17 */ -#define PC_SWITCH1 PC_9 /* Reboot switch */ - -extern void poweron_key (void); - -#endif /* __KUP_H */ diff --git a/board/kup/common/load_sernum_ethaddr.c b/board/kup/common/load_sernum_ethaddr.c deleted file mode 100644 index b7b7499..0000000 --- a/board/kup/common/load_sernum_ethaddr.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/*----------------------------------------------------------------------- - * Process Hardware Information Block: - * - * If we boot on a system fresh from factory, check if the Hardware - * Information Block exists and save the information it contains. - * - * The KUP Hardware Information Block is defined as - * follows: - * - located in first flash bank - * - starts at offset CFG_HWINFO_OFFSET - * - size CFG_HWINFO_SIZE - * - * Internal structure: - * - sequence of ASCII character lines - * - fields separated by - * - last field terminated by NUL character (0x00) - * - * Fields in Hardware Information Block: - * 1) Module Type - * 2) MAC Address - * 3) .... - */ - - -#define ETHADDR_TOKEN "ethaddr=" -#define LCD_TOKEN "lcd=" - -void load_sernum_ethaddr (void) -{ - unsigned char *hwi; - char *var; - unsigned char hwi_stack[CFG_HWINFO_SIZE]; - char *p; - - hwi = (unsigned char *) (CFG_FLASH_BASE + CFG_HWINFO_OFFSET); - if (*((unsigned long *) hwi) != (unsigned long) CFG_HWINFO_MAGIC) { - printf ("HardwareInfo not found!\n"); - return; - } - memcpy (hwi_stack, hwi, CFG_HWINFO_SIZE); - - /* - ** ethaddr - */ - var = strstr ((char *)hwi_stack, ETHADDR_TOKEN); - if (var) { - var += sizeof (ETHADDR_TOKEN) - 1; - p = strchr (var, '\r'); - if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) { - *p = '\0'; - setenv ("ethaddr", var); - *p = '\r'; - } - } - /* - ** lcd - */ - var = strstr ((char *)hwi_stack, LCD_TOKEN); - if (var) { - var += sizeof (LCD_TOKEN) - 1; - p = strchr (var, '\r'); - if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) { - *p = '\0'; - setenv ("lcd", var); - *p = '\r'; - } - } -} diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile deleted file mode 100644 index 62d289b..0000000 --- a/board/kup/kup4k/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/kup/kup4k/config.mk b/board/kup/kup4k/config.mk deleted file mode 100644 index 22e30b2..0000000 --- a/board/kup/kup4k/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# KUP4K board -# - -TEXT_BASE = 0x40000000 diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c deleted file mode 100644 index e621c43..0000000 --- a/board/kup/kup4k/kup4k.c +++ /dev/null @@ -1,459 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "../common/kup.h" -#ifdef CONFIG_KUP4K_LOGO - #include "s1d13706.h" -#endif - -#undef DEBUG -#ifdef DEBUG -# define debugk(fmt,args...) printf(fmt ,##args) -#else -# define debugk(fmt,args...) -#endif - -typedef struct { - volatile unsigned char *VmemAddr; - volatile unsigned char *RegAddr; -} FB_INFO_S1D13xxx; - - -/* ------------------------------------------------------------------------- */ - -#if 0 -static long int dram_size (long int, long int *, long int); -#endif - -#ifdef CONFIG_KUP4K_LOGO -void lcd_logo(bd_t *bd); -#endif - - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - uchar *latch,rev,mod; - - /* - * Init ChipSelect #4 (CAN + HW-Latch) - */ - immap->im_memctl.memc_or4 = 0xFFFF8926; - immap->im_memctl.memc_br4 = 0x90000401; - __asm__ ("eieio"); - latch=(uchar *)0x90000200; - rev = (*latch & 0xF8) >> 3; - mod=(*latch & 0x03); - printf ("Board: KUP4K Rev %d.%d\n",rev,mod); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - long int size_b1 = 0; - long int size_b2 = 0; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ -/* memctl->memc_or1 = CFG_OR1_PRELIM; */ -/* memctl->memc_br1 = CFG_BR1_PRELIM; */ - -/* memctl->memc_or2 = CFG_OR2_PRELIM; */ -/* memctl->memc_br2 = CFG_BR2_PRELIM; */ - - - memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ - udelay (1); - memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); - -#if 0 /* 3 x 8MB */ - size_b0 = 0x00800000; - size_b1 = 0x00800000; - size_b2 = 0x00800000; - memctl->memc_mptpr = CFG_MPTPR; - udelay (1000); - memctl->memc_or1 = 0xFF800A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFF000A00; - memctl->memc_br2 = 0x00800081; - memctl->memc_or3 = 0xFE000A00; - memctl->memc_br3 = 0x01000081; -#else /* 3 x 16 MB */ - size_b0 = 0x01000000; - size_b1 = 0x01000000; - size_b2 = 0x01000000; - memctl->memc_mptpr = CFG_MPTPR; - udelay (1000); - memctl->memc_or1 = 0xFF000A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFE000A00; - memctl->memc_br2 = 0x01000081; - memctl->memc_or3 = 0xFC000A00; - memctl->memc_br3 = 0x02000081; -#endif - - udelay (10000); - - return (size_b0 + size_b1 + size_b2); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -#if 0 -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - memctl->memc_mamr = mamr_value; - - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - return (cnt * sizeof (long)); - } - } - return (maxsize); -} -#endif - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_STATUS_LED - volatile immap_t *immap = (immap_t *) CFG_IMMR; -#endif -#ifdef CONFIG_KUP4K_LOGO - bd_t *bd = gd->bd; - - lcd_logo (bd); -#endif /* CONFIG_KUP4K_LOGO */ -#ifdef CONFIG_IDE_LED - /* Configure PA8 as output port */ - immap->im_ioport.iop_padir |= 0x80; - immap->im_ioport.iop_paodr |= 0x80; - immap->im_ioport.iop_papar &= ~0x80; - immap->im_ioport.iop_padat |= 0x80; /* turn it off */ -#endif - setenv("hw","4k"); - poweron_key(); - return (0); -} - -#ifdef CONFIG_KUP4K_LOGO - - -void lcd_logo (bd_t * bd) -{ - FB_INFO_S1D13xxx fb_info; - S1D_INDEX s1dReg; - S1D_VALUE s1dValue; - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl; - ushort i; - uchar *fb; - int rs, gs, bs; - int r = 8, g = 8, b = 4; - int r1, g1, b1; - int n; - char tmp[64]; /* long enough for environment variables */ - int tft = 0; - - immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM); - immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM); - immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */ - immr->im_cpm.cp_pbdir |= (PB_LCD_PWM); - -/*----------------------------------------------------------------------------- */ -/* Initialize the chip and the frame buffer driver. */ -/*----------------------------------------------------------------------------- */ - memctl = &immr->im_memctl; - - - /* - * Init ChipSelect #5 (S1D13768) - */ - memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */ - memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */ - __asm__ ("eieio"); - - fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR); - fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR); - - if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28) - || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { - printf ("Warning:LCD Controller S1D13706 not found\n"); - setenv ("lcd", "none"); - return; - } - - - for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) { - s1dReg = aS1DRegs_prelimn[i].Index; - s1dValue = aS1DRegs_prelimn[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = - s1dValue; - } - - - n = getenv_r ("lcd", tmp, sizeof (tmp)); - if (n > 0) { - if (!strcmp ("tft", tmp)) - tft = 1; - else - tft = 0; - } -#if 0 - if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04) - tft = 0; - else - tft = 1; -#endif - - debugk ("Port=0x%02x -> TFT=%d\n", tft, - ((S1D_VALUE *) fb_info.RegAddr)[0xAC]); - - /* init controller */ - if (!tft) { - for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) { - s1dReg = aS1DRegs_stn[i].Index; - s1dValue = aS1DRegs_stn[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_stn[i].Index, - aS1DRegs_stn[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] = - s1dValue; - } - n = getenv_r ("contrast", tmp, sizeof (tmp)); - ((S1D_VALUE *) fb_info.RegAddr)[0xB3] = - (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0; - switch (bd->bi_busfreq) { - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; - break; - case 48000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; - break; - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); - case 64000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; - break; - } - /* setenv("lcd","stn"); */ - } else { - for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) { - s1dReg = aS1DRegs_tft[i].Index; - s1dValue = aS1DRegs_tft[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_tft[i].Index, - aS1DRegs_tft[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = - s1dValue; - } - - switch (bd->bi_busfreq) { - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30; - break; - } - /* setenv("lcd","tft"); */ - } - - /* create and set colormap */ - rs = 256 / (r - 1); - gs = 256 / (g - 1); - bs = 256 / (b - 1); - for (i = 0; i < 256; i++) { - r1 = (rs * ((i / (g * b)) % r)) * 255; - g1 = (gs * ((i / b) % g)) * 255; - b1 = (bs * ((i) % b)) * 255; - debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4); - S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4), - (b1 >> 4)); - } - - /* copy bitmap */ - fb = (uchar *) (fb_info.VmemAddr); - memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240); -} -#endif /* CONFIG_KUP4K_LOGO */ diff --git a/board/kup/kup4k/s1d13706.h b/board/kup/kup4k/s1d13706.h deleted file mode 100644 index cd5eccc..0000000 --- a/board/kup/kup4k/s1d13706.h +++ /dev/null @@ -1,174 +0,0 @@ -/*---------------------------------------------------------------------------- */ -/* */ -/* File generated by S1D13706CFG.EXE */ -/* */ -/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ -/* All rights reserved. */ -/* */ -/*---------------------------------------------------------------------------- */ - -/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ - -#define S1D_DISPLAY_WIDTH 320 -#define S1D_DISPLAY_HEIGHT 240 -#define S1D_DISPLAY_BPP 8 -#define S1D_DISPLAY_SCANLINE_BYTES 320 -#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L -#define S1D_PHYSICAL_VMEM_SIZE 0x14000L -#define S1D_PHYSICAL_REG_ADDR 0x80080000L -#define S1D_PHYSICAL_REG_SIZE 0x100 -#define S1D_DISPLAY_PCLK 6250 -#define S1D_PALETTE_SIZE 256 -#define S1D_REGDELAYOFF 0xFFFE -#define S1D_REGDELAYON 0xFFFF - -#define S1D_WRITE_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ - ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ - ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ - ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ -} - -#define S1D_READ_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ - r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ - g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ - b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ -} - -typedef unsigned short S1D_INDEX; -typedef unsigned char S1D_VALUE; - - -typedef struct -{ - S1D_INDEX Index; - S1D_VALUE Value; -} S1D_REGS; - - -static S1D_REGS aS1DRegs_prelimn[] = -{ - {0x10,0x00}, /* PANEL Type Register */ - {0xA8,0x00}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - -}; - -static S1D_REGS aS1DRegs_stn[] = -{ - {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ - {0x10,0xD0}, /* PANEL Type Register */ - {0x11,0x00}, /* MOD Rate Register */ - {0x14,0x27}, /* Horizontal Display Period Register */ - {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ - {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ - {0x18,0xF0}, /* Vertical Total Register 0 */ - {0x19,0x00}, /* Vertical Total Register 1 */ - {0x1C,0xEF}, /* Vertical Display Period Register 0 */ - {0x1D,0x00}, /* Vertical Display Period Register 1 */ - {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ - {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ - {0x20,0x87}, /* Horizontal Sync Pulse Width Register */ - {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ - {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ - {0x24,0x80}, /* Vertical Sync Pulse Width Register */ - {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ - {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ - {0x70,0x83}, /* Display Mode Register */ - {0x71,0x00}, /* Special Effects Register */ - {0x74,0x00}, /* Main Window Display Start Address Register 0 */ - {0x75,0x00}, /* Main Window Display Start Address Register 1 */ - {0x76,0x00}, /* Main Window Display Start Address Register 2 */ - {0x78,0x50}, /* Main Window Address Offset Register 0 */ - {0x79,0x00}, /* Main Window Address Offset Register 1 */ - {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ - {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ - {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ - {0x80,0x50}, /* Sub Window Address Offset Register 0 */ - {0x81,0x00}, /* Sub Window Address Offset Register 1 */ - {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ - {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ - {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ - {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ - {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ - {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ - {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ - {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ - {0xA0,0x00}, /* Power Save Config Register */ - {0xA1,0x00}, /* CPU Access Control Register */ - {0xA2,0x00}, /* Software Reset Register */ - {0xA3,0x00}, /* BIG Endian Support Register */ - {0xA4,0x00}, /* Scratch Pad Register 0 */ - {0xA5,0x00}, /* Scratch Pad Register 1 */ - {0xA8,0x01}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - {0xAC,0x01}, /* GPIO Status Control Register 0 */ - {0xAD,0x00}, /* GPIO Status Control Register 1 */ - {0xB0,0x10}, /* PWM CV Clock Control Register */ - {0xB1,0x80}, /* PWM CV Clock Config Register */ - {0xB2,0x00}, /* CV Clock Burst Length Register */ - {0xAD,0x80}, /* reset seq */ - {0x70,0x03}, -}; - -static S1D_REGS aS1DRegs_tft[] = -{ - {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ - {0x05,0x42}, /* PCLK Config Register */ - {0x10,0x61}, /* PANEL Type Register */ - {0x11,0x00}, /* MOD Rate Register */ - {0x12,0x30}, /* Horizontal Total Register */ - {0x14,0x27}, /* Horizontal Display Period Register */ - {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */ - {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ - {0x18,0xFA}, /* Vertical Total Register 0 */ - {0x19,0x00}, /* Vertical Total Register 1 */ - {0x1C,0xEF}, /* Vertical Display Period Register 0 */ - {0x1D,0x00}, /* Vertical Display Period Register 1 */ - {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ - {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ - {0x20,0x07}, /* Horizontal Sync Pulse Width Register */ - {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ - {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ - {0x24,0x00}, /* Vertical Sync Pulse Width Register */ - {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */ - {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ - {0x70,0x03}, /* Display Mode Register */ - {0x71,0x00}, /* Special Effects Register */ - {0x74,0x00}, /* Main Window Display Start Address Register 0 */ - {0x75,0x00}, /* Main Window Display Start Address Register 1 */ - {0x76,0x00}, /* Main Window Display Start Address Register 2 */ - {0x78,0x50}, /* Main Window Address Offset Register 0 */ - {0x79,0x00}, /* Main Window Address Offset Register 1 */ - {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ - {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ - {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ - {0x80,0x50}, /* Sub Window Address Offset Register 0 */ - {0x81,0x00}, /* Sub Window Address Offset Register 1 */ - {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ - {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ - {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ - {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ - {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ - {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ - {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ - {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ - {0xA0,0x00}, /* Power Save Config Register */ - {0xA1,0x00}, /* CPU Access Control Register */ - {0xA2,0x00}, /* Software Reset Register */ - {0xA3,0x00}, /* BIG Endian Support Register */ - {0xA4,0x00}, /* Scratch Pad Register 0 */ - {0xA5,0x00}, /* Scratch Pad Register 1 */ - {0xA8,0x01}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - {0xAC,0x01}, /* GPIO Status Control Register 0 */ - {0xAD,0x00}, /* GPIO Status Control Register 1 */ - {0xB0,0x10}, /* PWM CV Clock Control Register */ - {0xB1,0x80}, /* PWM CV Clock Config Register */ - {0xB2,0x00}, /* CV Clock Burst Length Register */ - {0xAD,0x80}, /* reset seq */ - {0x70,0x03}, -}; diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds deleted file mode 100644 index 8625999..0000000 --- a/board/kup/kup4k/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) -/* - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) -*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug deleted file mode 100644 index c0cf1cb..0000000 --- a/board/kup/kup4k/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile deleted file mode 100644 index 62d289b..0000000 --- a/board/kup/kup4x/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/kup/kup4x/config.mk b/board/kup/kup4x/config.mk deleted file mode 100644 index 61d4e09..0000000 --- a/board/kup/kup4x/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# KUP4X board -# - -TEXT_BASE = 0x40000000 diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c deleted file mode 100644 index cd9ed13..0000000 --- a/board/kup/kup4x/kup4x.c +++ /dev/null @@ -1,312 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "../common/kup.h" -#ifdef CONFIG_KUP4K_LOGO -/* #include "s1d13706.h" */ -#endif - -#define KUP4X_USB - - -typedef struct { - volatile unsigned char *VmemAddr; - volatile unsigned char *RegAddr; -} FB_INFO_S1D13xxx; - -/* ------------------------------------------------------------------------- */ - -int usb_init_kup4x (void); - - -#ifdef CONFIG_KUP4K_LOGO -void lcd_logo (bd_t * bd); -#endif - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile uchar *latch; - uchar rev, mod; - - /* - * Init ChipSelect #4 (CAN + HW-Latch) - */ - memctl->memc_or4 = 0xFFFF8926; - memctl->memc_br4 = 0x90000401; - __asm__ ("eieio"); - latch = (volatile uchar *) 0x90000200; - rev = (*latch & 0xF8) >> 3; - mod = (*latch & 0x03); - printf ("Board: KUP4X Rev %d.%d\n",rev,mod); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - long int size_b1 = 0; - long int size_b2 = 0; - long int size_b3 = 0; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ -/* memctl->memc_or1 = CFG_OR1_PRELIM; */ -/* memctl->memc_br1 = CFG_BR1_PRELIM; */ - -/* memctl->memc_or2 = CFG_OR2_PRELIM; */ -/* memctl->memc_br2 = CFG_BR2_PRELIM; */ - - memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ - udelay (1); - memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mcr = 0x8000C105; /* SDRAM bank 2 */ - udelay (1); - memctl->memc_mcr = 0x8000C830; /* SDRAM bank 2 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x8000C106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); -#if 0 /* 4 x 8MB */ - size_b0 = 0x00800000; - size_b1 = 0x00800000; - size_b2 = 0x00800000; - size_b3 = 0x00800000; - memctl->memc_mptpr = CFG_MPTPR; - udelay (1000); - memctl->memc_or1 = 0xFF800A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFF000A00; - memctl->memc_br2 = 0x00800081; - memctl->memc_or3 = 0xFE000A00; - memctl->memc_br3 = 0x01000081; - memctl->memc_or6 = 0xFE000A00; - memctl->memc_br6 = 0x01800081; -#else /* 4 x 16 MB */ - size_b0 = 0x01000000; - size_b1 = 0x01000000; - size_b2 = 0x01000000; - size_b3 = 0x01000000; - memctl->memc_mptpr = CFG_MPTPR; - udelay (1000); - memctl->memc_or1 = 0xFF000A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFE000A00; - memctl->memc_br2 = 0x01000081; - memctl->memc_or3 = 0xFD000A00; - memctl->memc_br3 = 0x02000081; - memctl->memc_or6 = 0xFC000A00; - memctl->memc_br6 = 0x03000081; -#endif - udelay (10000); - - return (size_b0 + size_b1 + size_b2 + size_b3); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -#if 0 -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - memctl->memc_mamr = mamr_value; - - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - return (cnt * sizeof (long)); - } - } - return (maxsize); -} -#endif - -int misc_init_r (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - -#ifdef CONFIG_IDE_LED - /* Configure PA8 as output port */ - immap->im_ioport.iop_padir |= 0x80; - immap->im_ioport.iop_paodr |= 0x80; - immap->im_ioport.iop_papar &= ~0x80; - immap->im_ioport.iop_padat |= 0x80; /* turn it off */ -#endif -#ifdef KUP4X_USB - usb_init_kup4x (); -#endif - setenv ("hw", "4x"); - poweron_key (); - return (0); -} diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds deleted file mode 100644 index 8625999..0000000 --- a/board/kup/kup4x/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) -/* - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) -*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug deleted file mode 100644 index c0cf1cb..0000000 --- a/board/kup/kup4x/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/lantec/Makefile b/board/lantec/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/lantec/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/lantec/config.mk b/board/lantec/config.mk deleted file mode 100644 index 05ea3b9..0000000 --- a/board/lantec/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Lantec board (based on TQM8xxL config). -# - -TEXT_BASE = 0x40000000 diff --git a/board/lantec/flash.c b/board/lantec/flash.c deleted file mode 100644 index 0faa82c..0000000 --- a/board/lantec/flash.c +++ /dev/null @@ -1,625 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Derived from ../tqm8xx/flash.c - * [Torsten Stevens, FHG IMS; Bruno Achauer, Exet AG] - */ - -#include -#include - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - DEBUGF ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \ - BR_MS_GPCM | BR_PS_32 | BR_V; - - DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or5 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br5 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_PS_32 | BR_V; - - DEBUGF("## BR5: 0x%08x OR5: 0x%08x\n", - memctl->memc_br5, memctl->memc_or5); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_info[1].size = size_b1; - - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br5 = 0; /* invalidate bank */ - memctl->memc_or5 = 0; /* invalidate bank */ - - DEBUGF("## DISABLE BR5: 0x%08x OR5: 0x%08x\n", - memctl->memc_br5, memctl->memc_or5); - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - } - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/lantec/lantec.c b/board/lantec/lantec.c deleted file mode 100644 index 417dbbb..0000000 --- a/board/lantec/lantec.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2001 - * Torsten Stevens, FHG IMS, stevens@ims.fhg.de - * Bruno Achauer, Exet AG, bruno@exet-ag.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Derived from ../tqm8xx/tqm8xx.c - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1ff77c35, 0xefeabc34, 0x1fb57c35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, 0xfffffc07, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test TQ ID string (TQM8xx...) - * If present, check for "L" type (no second DRAM bank), - * otherwise "L" type is assumed as default. - * - * Return 1 for "L" type, 0 else. - */ - -int checkboard (void) -{ - printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0; - int i; - - /* - * Configure UPMA for SDRAM - */ - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */ ; - - /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - - /* initialize memory address register */ - memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */ - - /* mode initialization (offset 5) */ - udelay (200); /* 0x80006105 */ - memctl->memc_mcr = - MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05); - - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = - MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = - MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); - - udelay (1); /* 0x80006106 */ - memctl->memc_mcr = - MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06); - - memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */ - - udelay (200); - - /* Need at least 10 DRAM accesses to stabilize */ - for (i = 0; i < 10; ++i) { - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE3_PRELIM; - unsigned long val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* - * Check Bank 0 Memory Size for re-configuration - */ - size_b0 = dram_size (CFG_MAMR_8COL, - (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - - memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE; - - /* - * Final mapping: - */ - - memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - udelay (1000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds deleted file mode 100644 index 29ecabd..0000000 --- a/board/lantec/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug deleted file mode 100644 index 65b25b9..0000000 --- a/board/lantec/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/lart/Makefile b/board/lart/Makefile deleted file mode 100644 index 550aa1d..0000000 --- a/board/lart/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := lart.o flash.o -SOBJS := flashasm.o lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/lart/config.mk b/board/lart/config.mk deleted file mode 100644 index 3033c4f..0000000 --- a/board/lart/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -# -# LART board with SA1100 cpu -# -# see http://www.lart.tudelft.nl/ for more information on LART -# - -# -# LART has 4 banks of 8 MB DRAM -# -# c000'0000 -# c100'0000 -# c800'0000 -# c900'0000 -# -# Linux-Kernel is expected to be at c000'8000, entry c000'8000 -# -# we load ourself to c178'0000, the upper 1 MB of second bank -# -# download areas is c800'0000 -# - - -TEXT_BASE = 0xc1780000 diff --git a/board/lart/flash.c b/board/lart/flash.c deleted file mode 100644 index 5232ed2..0000000 --- a/board/lart/flash.c +++ /dev/null @@ -1,474 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -ulong myflush(void); - - -#define FLASH_BANK_SIZE 0x800000 -#define MAIN_SECT_SIZE 0x20000 -#define PARAM_SECT_SIZE 0x4000 - -/* puzzle magic for lart - * data_*_flash are def'd in flashasm.S - */ - -extern u32 data_from_flash(u32); -extern u32 data_to_flash(u32); - -#define PUZZLE_FROM_FLASH(x) data_from_flash((x)) -#define PUZZLE_TO_FLASH(x) data_to_flash((x)) - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x00FF00FF -#define CMD_IDENTIFY 0x00900090 -#define CMD_ERASE_SETUP 0x00200020 -#define CMD_ERASE_CONFIRM 0x00D000D0 -#define CMD_PROGRAM 0x00400040 -#define CMD_RESUME 0x00D000D0 -#define CMD_SUSPEND 0x00B000B0 -#define CMD_STATUS_READ 0x00700070 -#define CMD_STATUS_RESET 0x00500050 - -#define BIT_BUSY 0x00800080 -#define BIT_ERASE_SUSPEND 0x00400040 -#define BIT_ERASE_ERROR 0x00200020 -#define BIT_PROGRAM_ERROR 0x00100010 -#define BIT_VPP_RANGE_ERROR 0x00080008 -#define BIT_PROGRAM_SUSPEND 0x00040004 -#define BIT_PROTECT_ERROR 0x00020002 -#define BIT_UNDEFINED 0x00010001 - -#define BIT_SEQUENCE_ERROR 0x00300030 -#define BIT_TIMEOUT 0x80000000 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) - { - ulong flashbase = 0; - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F160F3B & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) - { - if (j <= 7) - { - flash_info[i].start[j] = flashbase + j * PARAM_SECT_SIZE; - } - else - { - flash_info[i].start[j] = flashbase + (j - 7)*MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) - { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf("Intel: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) - { - case (INTEL_ID_28F160F3B & FLASH_TYPEMASK): - printf("2x 28F160F3B (16Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - goto Done; - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) - { - if ((i % 5) == 0) - { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: - ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_error (ulong code) -{ - /* Check bit patterns */ - /* SR.7=0 is busy, SR.7=1 is ready */ - /* all other flags indicate error on 1 */ - /* SR.0 is undefined */ - /* Timeout is our faked flag */ - - /* sequence is described in Intel 290644-005 document */ - - /* check Timeout */ - if (code & BIT_TIMEOUT) - { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - - /* check Busy, SR.7 */ - if (~code & BIT_BUSY) - { - printf ("Busy\n"); - return ERR_PROG_ERROR; - } - - /* check Vpp low, SR.3 */ - if (code & BIT_VPP_RANGE_ERROR) - { - printf ("Vpp range error\n"); - return ERR_PROG_ERROR; - } - - /* check Device Protect Error, SR.1 */ - if (code & BIT_PROTECT_ERROR) - { - printf ("Device protect error\n"); - return ERR_PROG_ERROR; - } - - /* check Command Seq Error, SR.4 & SR.5 */ - if (code & BIT_SEQUENCE_ERROR) - { - printf ("Command seqence error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Error, SR.5 */ - if (code & BIT_ERASE_ERROR) - { - printf ("Block erase error\n"); - return ERR_PROG_ERROR; - } - - /* check Program Error, SR.4 */ - if (code & BIT_PROGRAM_ERROR) - { - printf ("Program error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Suspended, SR.6 */ - if (code & BIT_ERASE_SUSPEND) - { - printf ("Block erase suspended\n"); - return ERR_PROG_ERROR; - } - - /* check Program Suspended, SR.2 */ - if (code & BIT_PROGRAM_SUSPEND) - { - printf ("Program suspended\n"); - return ERR_PROG_ERROR; - } - - /* OK, no error */ - return ERR_OK; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status(); - icache_disable(); - iflag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) - { - printf("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - if (info->protect[sect] == 0) - { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET); - *addr = PUZZLE_TO_FLASH(CMD_ERASE_SETUP); - *addr = PUZZLE_TO_FLASH(CMD_ERASE_CONFIRM); - - /* wait until flash is ready */ - do - { - /* check timeout */ - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) - { - *addr = PUZZLE_TO_FLASH(CMD_SUSPEND); - result = BIT_TIMEOUT; - break; - } - - result = PUZZLE_FROM_FLASH(*addr); - } while (~result & BIT_BUSY); - - *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY); - - if ((rc = flash_error(result)) != ERR_OK) - goto outahere; - - printf("ok.\n"); - } - else /* it was protected */ - { - printf("protected!\n"); - } - } - - if (ctrlc()) - printf("User Interrupt!\n"); - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked(10000); - - if (iflag) - enable_interrupts(); - - if (cflag) - icache_enable(); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -volatile static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - - /* Check if Flash is (sufficiently) erased - */ - result = PUZZLE_FROM_FLASH(*addr); - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status(); - icache_disable(); - iflag = disable_interrupts(); - - *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET); - *addr = PUZZLE_TO_FLASH(CMD_PROGRAM); - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - /* wait until flash is ready */ - do - { - /* check timeout */ - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) - { - *addr = PUZZLE_TO_FLASH(CMD_SUSPEND); - result = BIT_TIMEOUT; - break; - } - - result = PUZZLE_FROM_FLASH(*addr); - } while (~result & BIT_BUSY); - - *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY); - - rc = flash_error(result); - - if (iflag) - enable_interrupts(); - - if (cflag) - icache_enable(); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 24); - } - for (; i<4 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((vu_long*)src); - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - return write_word(info, wp, data); -} diff --git a/board/lart/flashasm.S b/board/lart/flashasm.S deleted file mode 100644 index 9021972..0000000 --- a/board/lart/flashasm.S +++ /dev/null @@ -1,177 +0,0 @@ -/* - * flashasm.S: flash magic for LART - * - * Copyright (C) 1999 2000 2001 Jan-Derk bakker (J.D.Bakker@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -.text - - -.globl data_to_flash -.globl data_from_flash - /* Subroutine that takes data in r0 and formats it so it will be in */ - /* the correct order for the internal flash */ - /* used for LART only */ -data_to_flash: - mov r1, #0x0 - - tst r0, #0x00000001 - orrne r1, r1, #0x00001000 - tst r0, #0x00000002 - orrne r1, r1, #0x00004000 - tst r0, #0x00000004 - orrne r1, r1, #0x00000800 - tst r0, #0x00000008 - orrne r1, r1, #0x00000200 - tst r0, #0x00000010 - orrne r1, r1, #0x00000001 - tst r0, #0x00000020 - orrne r1, r1, #0x00000004 - tst r0, #0x00000040 - orrne r1, r1, #0x00000080 - tst r0, #0x00000080 - orrne r1, r1, #0x00000020 - - tst r0, #0x00000100 - orrne r1, r1, #0x00002000 - tst r0, #0x00000200 - orrne r1, r1, #0x00008000 - tst r0, #0x00000400 - orrne r1, r1, #0x00000400 - tst r0, #0x00000800 - orrne r1, r1, #0x00000100 - tst r0, #0x00001000 - orrne r1, r1, #0x00000002 - tst r0, #0x00002000 - orrne r1, r1, #0x00000008 - tst r0, #0x00004000 - orrne r1, r1, #0x00000040 - tst r0, #0x00008000 - orrne r1, r1, #0x00000010 - - tst r0, #0x00010000 - orrne r1, r1, #0x00100000 - tst r0, #0x00020000 - orrne r1, r1, #0x00400000 - tst r0, #0x00040000 - orrne r1, r1, #0x00080000 - tst r0, #0x00080000 - orrne r1, r1, #0x00020000 - tst r0, #0x00100000 - orrne r1, r1, #0x01000000 - tst r0, #0x00200000 - orrne r1, r1, #0x04000000 - tst r0, #0x00400000 - orrne r1, r1, #0x80000000 - tst r0, #0x00800000 - orrne r1, r1, #0x20000000 - - tst r0, #0x01000000 - orrne r1, r1, #0x00200000 - tst r0, #0x02000000 - orrne r1, r1, #0x00800000 - tst r0, #0x04000000 - orrne r1, r1, #0x00040000 - tst r0, #0x08000000 - orrne r1, r1, #0x00010000 - tst r0, #0x10000000 - orrne r1, r1, #0x02000000 - tst r0, #0x20000000 - orrne r1, r1, #0x08000000 - tst r0, #0x40000000 - orrne r1, r1, #0x40000000 - tst r0, #0x80000000 - orrne r1, r1, #0x10000000 - - mov r0, r1 - mov pc, lr - - /* Takes data received from the flash, and unshuffles it. */ -data_from_flash: - mov r1, #0x00 - - tst r0, #0x00000001 - orrne r1, r1, #0x00000010 - tst r0, #0x00000002 - orrne r1, r1, #0x00001000 - tst r0, #0x00000004 - orrne r1, r1, #0x00000020 - tst r0, #0x00000008 - orrne r1, r1, #0x00002000 - tst r0, #0x00000010 - orrne r1, r1, #0x00008000 - tst r0, #0x00000020 - orrne r1, r1, #0x00000080 - tst r0, #0x00000040 - orrne r1, r1, #0x00004000 - tst r0, #0x00000080 - orrne r1, r1, #0x00000040 - - tst r0, #0x00000100 - orrne r1, r1, #0x00000800 - tst r0, #0x00000200 - orrne r1, r1, #0x00000008 - tst r0, #0x00000400 - orrne r1, r1, #0x00000400 - tst r0, #0x00000800 - orrne r1, r1, #0x00000004 - tst r0, #0x00001000 - orrne r1, r1, #0x00000001 - tst r0, #0x00002000 - orrne r1, r1, #0x00000100 - tst r0, #0x00004000 - orrne r1, r1, #0x00000002 - tst r0, #0x00008000 - orrne r1, r1, #0x00000200 - - tst r0, #0x00010000 - orrne r1, r1, #0x08000000 - tst r0, #0x00020000 - orrne r1, r1, #0x00080000 - tst r0, #0x00040000 - orrne r1, r1, #0x04000000 - tst r0, #0x00080000 - orrne r1, r1, #0x00040000 - tst r0, #0x00100000 - orrne r1, r1, #0x00010000 - tst r0, #0x00200000 - orrne r1, r1, #0x01000000 - tst r0, #0x00400000 - orrne r1, r1, #0x00020000 - tst r0, #0x00800000 - orrne r1, r1, #0x02000000 - - tst r0, #0x01000000 - orrne r1, r1, #0x00100000 - tst r0, #0x02000000 - orrne r1, r1, #0x10000000 - tst r0, #0x04000000 - orrne r1, r1, #0x00200000 - tst r0, #0x08000000 - orrne r1, r1, #0x20000000 - tst r0, #0x10000000 - orrne r1, r1, #0x80000000 - tst r0, #0x20000000 - orrne r1, r1, #0x00800000 - tst r0, #0x40000000 - orrne r1, r1, #0x40000000 - tst r0, #0x80000000 - orrne r1, r1, #0x00400000 - - mov r0, r1 - mov pc, lr diff --git a/board/lart/lart.c b/board/lart/lart.c deleted file mode 100644 index 66b730d..0000000 --- a/board/lart/lart.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of LART-Board */ - gd->bd->bi_arch_number = MACH_TYPE_LART; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xc0000100; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - bd_t *bd = gd->bd; - - bd->bi_dram[0].start = PHYS_SDRAM_1; - bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - bd->bi_dram[1].start = PHYS_SDRAM_2; - bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - bd->bi_dram[2].start = PHYS_SDRAM_3; - bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - bd->bi_dram[3].start = PHYS_SDRAM_4; - bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; - - return (0); -} diff --git a/board/lart/lowlevel_init.S b/board/lart/lowlevel_init.S deleted file mode 100644 index db9fd63..0000000 --- a/board/lart/lowlevel_init.S +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* some parameters for the board */ - -MEM_BASE: .long 0xa0000000 -MEM_START: .long 0xc0000000 - -#define MDCNFG 0x00 -#define MDCAS0 0x04 -#define MDCAS1 0x08 -#define MDCAS2 0x0c -#define MSC0 0x10 -#define MSC1 0x14 -#define MECR 0x18 - -mdcas0: .long 0xc71c703f -mdcas1: .long 0xffc71c71 -mdcas2: .long 0xffffffff -/* mdcnfg: .long 0x0bb2bcbf */ -mdcnfg: .long 0x0334b22f @ alt -/* mcs0: .long 0xfff8fff8 */ -msc0: .long 0xad8c4888 @ alt -mecr: .long 0x00060006 -/* mecr: .long 0x994a994a @ alt */ - -/* setting up the memory */ - -.globl lowlevel_init -lowlevel_init: - ldr r0, MEM_BASE - - /* Setup the flash memory */ - ldr r1, msc0 - str r1, [r0, #MSC0] - - /* Set up the DRAM */ - - /* MDCAS0 */ - ldr r1, mdcas0 - str r1, [r0, #MDCAS0] - - /* MDCAS1 */ - ldr r1, mdcas1 - str r1, [r0, #MDCAS1] - - /* MDCAS2 */ - ldr r1, mdcas2 - str r1, [r0, #MDCAS2] - - /* MDCNFG */ - ldr r1, mdcnfg - str r1, [r0, #MDCNFG] - - /* Set up PCMCIA space */ - ldr r1, mecr - str r1, [r0, #MECR] - - /* Load something to activate bank */ - ldr r1, MEM_START - -.rept 8 - ldr r0, [r1] -.endr - - /* everything is fine now */ - mov pc, lr diff --git a/board/lart/u-boot.lds b/board/lart/u-boot.lds deleted file mode 100644 index 258bece..0000000 --- a/board/lart/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/sa1100/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/logodl/Makefile b/board/logodl/Makefile deleted file mode 100644 index c7cde7d..0000000 --- a/board/logodl/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := logodl.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/logodl/config.mk b/board/logodl/config.mk deleted file mode 100644 index 76c382d..0000000 --- a/board/logodl/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -# Linux-Kernel is expected to be at c000'8000, entry c000'8000 -# -# we load ourself to c170'0000, the upper 1 MB of second bank -# -# download areas is c800'0000 -# - -#TEXT_BASE = 0 - -# FIXME: armboot does only work correctly when being compiled -# # for the addresses _after_ relocation to RAM!! Otherwhise the -# # .bss segment is assumed in flash... -# -TEXT_BASE = 0x083E0000 diff --git a/board/logodl/flash.c b/board/logodl/flash.c deleted file mode 100644 index a947731..0000000 --- a/board/logodl/flash.c +++ /dev/null @@ -1,829 +0,0 @@ -/* - * (C) 2000 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) 2003 August Hoeraendl, Logotronic GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#undef CONFIG_FLASH_16BIT - -#include - -#define FLASH_BANK_SIZE 0x1000000 -#define MAIN_SECT_SIZE 0x20000 /* 2x64k = 128k per sector */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -#define write_word(in, de, da) write_word_amd(in, de, da) -static void flash_get_offsets(ulong base, flash_info_t *info); -#ifdef CFG_FLASH_PROTECTION -static void flash_sync_real_protect(flash_info_t *info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) - { - ulong flashbase = 0; - flash_info[i].flash_id = - (FLASH_MAN_AMD & FLASH_VENDMASK) | - (FLASH_AM640U & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - switch (i) - { - case 0: - flashbase = PHYS_FLASH_1; - break; - case 1: - flashbase = PHYS_FLASH_2; - break; - default: - panic("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) - { - flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _bss_start - _armboot_start, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - uchar *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -#ifdef CFG_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void flash_sync_real_protect(flash_info_t *info) -{ - FPWV *addr = (FPWV *)(info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW)0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *)(info->start[i]); - info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - break; - - case FLASH_AM640U: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer(0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00800080; /* erase mode */ - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/** - * write_buf: - Copy memory to flash. - * - * @param info: - * @param src: source of copy transaction - * @param addr: where to copy to - * @param cnt: number of bytes to copy - * - * @return error code - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 8); - } - for (; i<2 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt==0 && i<2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - /* data = *((vushort*)src); */ - data = *((FPW*)src); - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - src += sizeof(FPW); - wp += sizeof(FPW); - cnt -= sizeof(FPW); - } - - if (cnt == 0) return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - - return write_word(info, wp, data); -} - - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CFG_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset (info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset (info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect (info); - break; - - case FLASH_AM640U: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c deleted file mode 100644 index 95634ac..0000000 --- a/board/logodl/logodl.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) 2002 Kyle Harris , Nexus Technologies, Inc. - * (C) 2002 Marius Groeger , Sysgo GmbH - * (C) 2003 Robert Schwebel , Pengutronix - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/** - * board_init: - setup some data structures - * - * @return: 0 in case of success - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - gd->bd->bi_arch_number = MACH_TYPE_LOGODL; - gd->bd->bi_boot_params = 0x08000100; - gd->bd->bi_baudrate = CONFIG_BAUDRATE; - - (*((volatile short*)0x14800000)) = 0xff; /* power on eth0 */ - (*((volatile short*)0x14000000)) = 0xff; /* power on uart */ - - return 0; -} - - -/** - * dram_init: - setup dynamic RAM - * - * @return: 0 in case of success - */ - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - - -/** - * logodl_set_led: - switch LEDs on or off - * - * @param led: LED to switch (0,1) - * @param state: switch on (1) or off (0) - */ - -void logodl_set_led(int led, int state) -{ - switch(led) { - - case 0: - if (state==1) { - CFG_LED_A_CR = CFG_LED_A_BIT; - } else if (state==0) { - CFG_LED_A_SR = CFG_LED_A_BIT; - } - break; - - case 1: - if (state==1) { - CFG_LED_B_CR = CFG_LED_B_BIT; - } else if (state==0) { - CFG_LED_B_SR = CFG_LED_B_BIT; - } - break; - } - - return; -} - - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - * The LOGOTRONIC does only have 2 LEDs, so we switch them on at the most - * important states (1, 5, 15). - */ - -void show_boot_progress (int status) -{ - /* - switch(status) { - case 1: logodl_set_led(0,1); break; - case 5: logodl_set_led(1,1); break; - case 15: logodl_set_led(2,1); break; - } - */ - logodl_set_led(0, (status & 1)==1); - logodl_set_led(1, (status & 2)==2); - - return; -} diff --git a/board/logodl/lowlevel_init.S b/board/logodl/lowlevel_init.S deleted file mode 100644 index aa9dcba..0000000 --- a/board/logodl/lowlevel_init.S +++ /dev/null @@ -1,437 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -_TEXT_BASE: - .word TEXT_BASE - - -/* - * Memory setup - */ - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - - /* Set up GPIO pins first ----------------------------------------- */ - - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - -/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ -/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */ -/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ -/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ -/* */ -/* ldr r1, =LED_BLANK */ -/* mov r0, #0xFF */ -/* str r0, [r1] / turn on hex leds */ -/* */ -/*loop: */ -/* */ -/* ldr r0, =0xB0070001 */ -/* ldr r1, =_LED */ -/* str r0, [r1] / hex display */ - - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1, =MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - - /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ - adr r3, mem_init /* r0 <- current position of code */ - ldr r2, =mem_init - cmp r3, r2 /* skip init if in place */ - beq initirqs - - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r3, =CFG_MDREFR_VAL - ldr r2, =0xFFF - and r3, r3, r2 - ldr r4, =0x03ca4000 - orr r4, r4, r3 - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - /* FIXME: we use async mode for now */ - - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - /* Step 4a: assert MDREFR:K?RUN and configure */ - /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - - ldr r4, =CFG_MDREFR_VAL - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Step 4b: de-assert MDREFR:SLFRSH. */ - - bic r4, r4, #(MDREFR_SLFRSH) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4c: assert MDREFR:E1PIN and E0PIO */ - - orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ - /* configure but not enable each SDRAM partition pair. */ - - ldr r4, =CFG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - /* There should 9 writes, since the first write doesn't */ - /* trigger a refresh cycle on PXA250. See Intel PXA250 and */ - /* PXA210 Processors Specification Update, */ - /* Jan 2003, Errata #116, page 30. */ - - - ldr r3, =CFG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* (MDCNFG:DEx set to 1). */ - - ldr r3, [r1, #MDCNFG_OFFSET] - orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) - str r3, [r1, #MDCNFG_OFFSET] - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - - /* We are finished with Intel's memory controller initialisation */ - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - /* (hard-coding at 398.12MHz for now). */ - - /* Turn Off ALL on-chip peripheral clocks for re-configuration */ - /* Note: See label 'ENABLECLKS' for the re-enabling */ - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - - /* default value in case no valid rotary switch setting is found */ - ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ - - /* ... and write the core clock config register */ - ldr r1, =CCCR - str r2, [r1] - - /* enable the 32Khz oscillator for RTC and PowerManager */ -/* - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] -*/ - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b - - /* ---------------------------------------------------------------- */ - /* */ - /* ---------------------------------------------------------------- */ - - /* Save SDRAM size */ - ldr r1, =DRAM_SIZE - str r8, [r1] - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - - /* FIXME */ - -#ifndef DEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ -#endif - - /* ---------------------------------------------------------------- */ - /* End lowlevel_init */ - /* ---------------------------------------------------------------- */ - -endlowlevel_init: - - mov pc, lr diff --git a/board/logodl/u-boot.lds b/board/logodl/u-boot.lds deleted file mode 100644 index f010239..0000000 --- a/board/logodl/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/lpd7a40x/Makefile b/board/lpd7a40x/Makefile deleted file mode 100644 index ebe14df..0000000 --- a/board/lpd7a40x/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := lpd7a40x.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/lpd7a40x/config.mk b/board/lpd7a40x/config.mk deleted file mode 100644 index bc03874..0000000 --- a/board/lpd7a40x/config.mk +++ /dev/null @@ -1,38 +0,0 @@ -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# Logic ZOOM LH7A400 SDK board w/Logic LH7A400-10 card engine -# w/Sharp LH7A400 SoC (ARM920T) cpu -# - -# -# 32 or 64 MB SDRAM on SDCSC0 @ 0xc0000000 -# -# Linux-Kernel is @ 0xC0008000, entry 0xc0008000 -# params @ 0xc0000100 -# optionally with a ramdisk at 0xc0300000 -# -# we load ourself to 0xc1fc0000 (32M - 256K) -# -# download area is 0xc0f00000 -# - -TEXT_BASE = 0xc1fc0000 -#TEXT_BASE = 0x00000000 diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c deleted file mode 100644 index 2dfe376..0000000 --- a/board/lpd7a40x/flash.c +++ /dev/null @@ -1,489 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include -#include - -#define FLASH_BANK_SIZE 0x1000000 /* 16MB (2 x 8 MB) */ -#define MAIN_SECT_SIZE 0x40000 /* 256KB (2 x 128kB) */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x00FF00FF -#define CMD_IDENTIFY 0x00900090 -#define CMD_ERASE_SETUP 0x00200020 -#define CMD_ERASE_CONFIRM 0x00D000D0 -#define CMD_PROGRAM 0x00400040 -#define CMD_RESUME 0x00D000D0 -#define CMD_SUSPEND 0x00B000B0 -#define CMD_STATUS_READ 0x00700070 -#define CMD_STATUS_RESET 0x00500050 - -#define BIT_BUSY 0x00800080 -#define BIT_ERASE_SUSPEND 0x00400040 -#define BIT_ERASE_ERROR 0x00200020 -#define BIT_PROGRAM_ERROR 0x00100010 -#define BIT_VPP_RANGE_ERROR 0x00080008 -#define BIT_PROGRAM_SUSPEND 0x00040004 -#define BIT_PROTECT_ERROR 0x00020002 -#define BIT_UNDEFINED 0x00010001 - -#define BIT_SEQUENCE_ERROR 0x00300030 -#define BIT_TIMEOUT 0x80000000 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F640J3A & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = CFG_FLASH_BASE; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase; - - /* uniform sector size */ - flashbase += MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* - * Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - -#ifdef CFG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[0]); -#endif - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F640J3A & FLASH_TYPEMASK): - printf ("2x 28F640J3A (64Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - return; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -int flash_error (ulong code) -{ - /* Check bit patterns */ - /* SR.7=0 is busy, SR.7=1 is ready */ - /* all other flags indicate error on 1 */ - /* SR.0 is undefined */ - /* Timeout is our faked flag */ - - /* sequence is described in Intel 290644-005 document */ - - /* check Timeout */ - if (code & BIT_TIMEOUT) { - puts ("Timeout\n"); - return ERR_TIMOUT; - } - - /* check Busy, SR.7 */ - if (~code & BIT_BUSY) { - puts ("Busy\n"); - return ERR_PROG_ERROR; - } - - /* check Vpp low, SR.3 */ - if (code & BIT_VPP_RANGE_ERROR) { - puts ("Vpp range error\n"); - return ERR_PROG_ERROR; - } - - /* check Device Protect Error, SR.1 */ - if (code & BIT_PROTECT_ERROR) { - puts ("Device protect error\n"); - return ERR_PROG_ERROR; - } - - /* check Command Seq Error, SR.4 & SR.5 */ - if (code & BIT_SEQUENCE_ERROR) { - puts ("Command seqence error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Error, SR.5 */ - if (code & BIT_ERASE_ERROR) { - puts ("Block erase error\n"); - return ERR_PROG_ERROR; - } - - /* check Program Error, SR.4 */ - if (code & BIT_PROGRAM_ERROR) { - puts ("Program error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Suspended, SR.6 */ - if (code & BIT_ERASE_SUSPEND) { - puts ("Block erase suspended\n"); - return ERR_PROG_ERROR; - } - - /* check Program Suspended, SR.2 */ - if (code & BIT_PROGRAM_SUSPEND) { - puts ("Program suspended\n"); - return ERR_PROG_ERROR; - } - - /* OK, no error */ - return ERR_OK; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result, result1; - int iflag, prot, sect; - int rc = ERR_OK; - -#ifdef USE_920T_MMU - int cflag; -#endif - - debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last); - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - debug ("Erasing sector %2d @ %08lX... ", - sect, info->start[sect]); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - ulong bsR7, bsR7_2, bsR5, bsR5_2; - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_ERASE_SETUP; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - *addr = CMD_STATUS_RESET; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - bsR7 = result & (1 << 7); - bsR7_2 = result & (1 << 23); - } while (!bsR7 | !bsR7_2); - - *addr = CMD_STATUS_READ; - result1 = *addr; - bsR5 = result1 & (1 << 5); - bsR5_2 = result1 & (1 << 21); -#ifdef SAMSUNG_FLASH_DEBUG - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); - if (bsR5 != 0 && bsR5_2 != 0) - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); -#endif - - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - - if ((rc = flash_error (result)) != ERR_OK) - goto outahere; -#if 0 - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); -#endif - } - } - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) -{ - vu_long *addr = (vu_long *) dest; - ulong result; - int rc = ERR_OK; - int iflag; - -#ifdef USE_920T_MMU - int cflag; -#endif - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - *addr = CMD_SUSPEND; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - } while (~result & BIT_BUSY); - - /* *addr = CMD_READ_ARRAY; */ - *addr = CMD_STATUS_READ; - result = *addr; - - rc = flash_error (result); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((vu_long *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - return write_word (info, wp, data); -} diff --git a/board/lpd7a40x/lowlevel_init.S b/board/lpd7a40x/lowlevel_init.S deleted file mode 100644 index b3ed55c..0000000 --- a/board/lpd7a40x/lowlevel_init.S +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Memory Setup - initialize memory controller(s) for devices required - * to boot and relocate - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* memory controller */ -#define BCRX_DEFAULT (0x0000fbe0) -#define BCRX_MW_8 (0x00000000) -#define BCRX_MW_16 (0x10000000) -#define BCRX_MW_32 (0x20000000) -#define BCRX_PME (0x08000000) -#define BCRX_WP (0x04000000) -#define BCRX_WST2_SHIFT (11) -#define BCRX_WST1_SHIFT (5) -#define BCRX_IDCY_SHIFT (0) - -/* Bank0 Async Flash */ -#define BCR0 (0x80002000) -#define BCR0_FLASH (BCRX_MW_32 | (0x08< - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined(CONFIG_LH7A400) -#include -#elif defined(CONFIG_LH7A404) -#include -#else -#error "No CPU defined!" -#endif -#include - -#include - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* set up the I/O ports */ - - /* enable flash programming */ - *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_FLASH_REG)) |= FLASH_FPEN; - - /* Auto wakeup, LCD disable, WLAN enable */ - *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_CECTL_REG)) &= - ~(CECTL_AWKP|CECTL_LCDV|CECTL_WLPE); - - /* Status LED 2 on (leds are active low) */ - *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_EXTGPIO_REG)) = - (EXTGPIO_STATUS1|EXTGPIO_GPIO1) & ~(EXTGPIO_STATUS2); - -#if defined(CONFIG_LH7A400) - /* arch number of Logic-Board - MACH_TYPE_LPD7A400 */ - gd->bd->bi_arch_number = MACH_TYPE_LPD7A400; -#elif defined(CONFIG_LH7A404) - /* arch number of Logic-Board - MACH_TYPE_LPD7A400 */ - gd->bd->bi_arch_number = MACH_TYPE_LPD7A404; -#endif - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xc0000100; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} diff --git a/board/lpd7a40x/u-boot.lds b/board/lpd7a40x/u-boot.lds deleted file mode 100644 index 156b871..0000000 --- a/board/lpd7a40x/u-boot.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/lh7a40x/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile deleted file mode 100644 index 106622c..0000000 --- a/board/lubbock/Makefile +++ /dev/null @@ -1,48 +0,0 @@ - -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := lubbock.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/lubbock/config.mk b/board/lubbock/config.mk deleted file mode 100644 index 55c8b27..0000000 --- a/board/lubbock/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -#TEXT_BASE = 0xa1700000 -TEXT_BASE = 0xa3080000 -#TEXT_BASE = 0 diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c deleted file mode 100644 index ba82892..0000000 --- a/board/lubbock/flash.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/lubbock/lowlevel_init.S b/board/lubbock/lowlevel_init.S deleted file mode 100644 index 15276e8..0000000 --- a/board/lubbock/lowlevel_init.S +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - - -/* - * Memory setup - */ - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - - /* Set up GPIO pins first ----------------------------------------- */ - - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1, =MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r3, =CFG_MDREFR_VAL - ldr r2, =0xFFF - and r3, r3, r2 - ldr r4, =0x03ca4000 - orr r4, r4, r3 - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ - - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - /* FIXME: we use async mode for now */ - - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - /* set MDREFR according to user define with exception of a few bits */ - - ldr r4, =CFG_MDREFR_VAL - orr r4, r4, #(MDREFR_SLFRSH) - bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Step 4b: de-assert MDREFR:SLFRSH. */ - - bic r4, r4, #(MDREFR_SLFRSH) - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ - - ldr r4, =CFG_MDREFR_VAL - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ - /* configure but not enable each SDRAM partition pair. */ - - ldr r4, =CFG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - ldr r3, =CFG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* (MDCNFG:DEx set to 1). */ - - ldr r3, [r1, #MDCNFG_OFFSET] - orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) - str r3, [r1, #MDCNFG_OFFSET] - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - - /* We are finished with Intel's memory controller initialisation */ - - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - /* (hard-coding at 398.12MHz for now). */ - - /* Turn Off ALL on-chip peripheral clocks for re-configuration */ - /* Note: See label 'ENABLECLKS' for the re-enabling */ - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - - /* default value in case no valid rotary switch setting is found */ - ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ - - /* ... and write the core clock config register */ - ldr r1, =CCCR - str r2, [r1] - -#ifdef RTC - /* enable the 32Khz oscillator for RTC and PowerManager */ - - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#endif - - /* ---------------------------------------------------------------- */ - /* */ - /* ---------------------------------------------------------------- */ - - /* Save SDRAM size */ - ldr r1, =DRAM_SIZE - str r8, [r1] - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - - /* FIXME */ - -#define NODEBUG -#ifdef NODEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ - -#endif - - /* ---------------------------------------------------------------- */ - /* End lowlevel_init */ - /* ---------------------------------------------------------------- */ - -endlowlevel_init: - - mov pc, lr diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c deleted file mode 100644 index e618ab9..0000000 --- a/board/lubbock/lubbock.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of Lubbock-Board */ - gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; - - return 0; -} diff --git a/board/lubbock/u-boot.lds b/board/lubbock/u-boot.lds deleted file mode 100644 index f010239..0000000 --- a/board/lubbock/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/lwmon/Makefile b/board/lwmon/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/lwmon/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/lwmon/README.keybd b/board/lwmon/README.keybd deleted file mode 100644 index 54f0aeb..0000000 --- a/board/lwmon/README.keybd +++ /dev/null @@ -1,126 +0,0 @@ - -Tastaturabfrage: - -Die Implementierung / Decodierung beruht auf den Angaben aus dem Do- -kument "PIC LWE-Tastatur" in der Fassung vom 9. 3. 2001, insbesonde- -re Tabelle 3 im Kapitel 4.3 Tastencodes. In U-Boot werden die vom -Keyboard-Controller gelesenen Daten hexadezimal codiert in der auto- -matisch angelegten Environment-Variablen "keybd" übergeben. Ist kei- -ne Taste gedrückt worden, steht dort: - - keybd=000000000000000000 - -Der decodierte Tastencode ("keybd") kann mit den "bootargs" an den -Linux-Kernel übergeben und dort z. B. in einem Device-Treiber oder -einer Applikation ausgewertet werden. - - -Sonderfunktionen beim Booten: - -Es lassen sich eine oder mehrere (beliebig viele) Tasten oder Tasten- -kombinationen definieren, die Sonderfunktionen auslösen, wenn diese -Tasten beim Booten (Reset) gedrückt sind. - -Wird eine eingestellte Taste bzw. Tastenkombination erkannt, so wird -in U-Boot noch vor dem Start des "Countdown" und somit vor jedem an- -deren Kommando der Inhalt einer dieser Taste bzw. Tastenkombination -zugeordneten Environment-Variablen ausführen. - - -Die Environment-Variable "magic_keys" wird als Liste von Zeichen ver- -standen, die als Suffix an den Namen "key_magic" angefügt werden und -so die Namen der Environment-Variablen definieren, mit denen die -Tasten (-kombinationen) festgelegt werden: - -Ist "magic_keys" NICHT definiert, so wird nur die in der Environment- -Variablen "key_magic" codierte Tasten (-kombination) geprüft, und -ggf. der Inhalt der Environment-Variablen "key_cmd" ausgeführt (ge- -nauer: der Inhalt von "key_cmd" wird der Variablen "preboot" zugewie- -sen, die ausgeführt wird, unmittelbar bevor die interaktive Kommando- -interpretation beginnt). - -Enthält "magic_keys" z. B. die Zeichenkette "0123CB*", so werden -nacheinander folgende Aktionen ausgeführt: - - prüfe Tastencode ggf. führe aus Kommando - in Variable in Variable - ----------------------------------- - key_magic0 ==> key_cmd0 - key_magic1 ==> key_cmd1 - key_magic2 ==> key_cmd2 - key_magic3 ==> key_cmd3 - key_magicC ==> key_cmdC - key_magicB ==> key_cmdB - key_magicA ==> key_cmdA - key_magic* ==> key_cmd* - -Hinweis: sobald ein aktivierter Tastencode erkannt wurde, wird die -Bearbeitung abgebrochen; es wird daher höchstens eines der definier- -ten Kommandos ausgeführt, wobei die Priorität durch die Suchreihen- -folge festgelegt wird, also durch die Reihenfolge der Zeichen in der -Varuiablen "magic_keys". - - -Die Codierung der Tasten, die beim Booten gedrückt werden müssen, um -eine Funktion auszulösen, erfolgt nach der Tastaturtabelle. - -Die Definitionen - - => setenv key_magic0 3a+3b - => setenv key_cmd0 setenv bootdelay 30 - -bedeuten dementsprechend, daß die Tasten mit den Codes 0x3A (Taste -"F1") und 0x3B (Taste "F2") gleichzeitig gedrückt werden müssen. Sie -können dort eine beliebige Tastenkombination eintragen (jeweils 2 -Zeichen für die Hex-Codes der Tasten, und '+' als Trennzeichen). - -Wird die eingestellte Tastenkombination erkannt, so wird in U-Boot -noch vor dem Start des "Countdown" und somit vor jedem anderen Kom- -mando das angebene Kommando ausgeführt und somit ein langes Boot- -Delay eingetragen. - -Praktisch könnten Sie also in U-Boot "bootdelay" auf 0 setzen und -somit stets ohne jede User-Interaktion automatisch booten, außer, -wenn die beiden Tasten "F1" und "F2" beim Booten gedrückt werden: -dann würde ein Boot-Delay von 30 Sekunden eingefügt. - - -Hinweis: dem Zeichen '#' kommt innerhalb von "magic_keys" eine beson- -dere Bedeutung zu: die dadurch definierte Key-Sequenz schaltet den -Monitor in den "Debug-Modus" - das bedeutet zunächst, daß alle weite- -ren Meldungen von U-Boot über das LCD-Display ausgegeben werden; -außerdem kann man durch das mit dieser Tastenkombination verknüpfte -Kommando z. B. die Linux-Bootmeldungen ebenfalls auf das LCD-Display -legen, so daß der Boot-Vorgang direkt und ohne weitere Hilfsmittel -analysiert werden kann. - -Beispiel: - -In U-Boot werden folgende Environment-Variablen gesetzt und abgespei- -chert: - -(1) => setenv magic_keys 01234#X -(2) => setenv key_cmd# setenv addfb setenv bootargs \\${bootargs} console=tty0 console=ttyS1,\\${baudrate} -(3) => setenv nfsargs setenv bootargs root=/dev/nfs rw nfsroot=\${serverip}:\${rootpath} -(4) => setenv addip setenv bootargs \${bootargs} ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off panic=1 -(5) => setenv addfb setenv bootargs \${bootargs} console=ttyS1,\${baudrate} -(6) => setenv bootcmd bootp\;run nfsargs\;run addip\;run addfb\;bootm - -Hierbei wird die Linux Commandline (in der Variablen "bootargs") im -Boot-Kommando "bootcmd" (6) schrittweise zusammengesetzt: zunächst -werden die für Root-Filesystem über NFS erforderlichen Optionen ge- -setzt ("run nfsargs", vgl. (3)), dann die Netzwerkkonfiguration an- -gefügt ("run addip", vgl. (4)), und schließlich die Systemconsole -definiert ("run addfb"). - -Dabei wird im Normalfall die Definition (5) verwendt; wurde aller- -dings beim Reset die entsprechende Taste gedrückt gehalten, so wird -diese Definition bei der Ausführung des in (2) definierten Kommandos -überschrieben, so daß Linux die Bootmeldungen auch über das Frame- -buffer-Device (=LCD-Display) ausgibt. - -Beachten Sie die Verdoppelung der '\'-Escapes in der Definition von -"key_cmd#" - diese ist erforderlich, weil der String _zweimal_ inter- -pretiert wird: das erste Mal bei der Eingabe von "key_cmd#", das -zweite Mal, wenn der String (als Inhalt von "preboot") ausgeführt -wird. diff --git a/board/lwmon/config.mk b/board/lwmon/config.mk deleted file mode 100644 index dfa952a..0000000 --- a/board/lwmon/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# LWE Monitorcontroller Litronic LCD IV boards -# - -TEXT_BASE = 0x40000000 -#TEXT_BASE = 0x41000000 diff --git a/board/lwmon/flash.c b/board/lwmon/flash.c deleted file mode 100644 index b894887..0000000 --- a/board/lwmon/flash.c +++ /dev/null @@ -1,648 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include -#include - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, ulong data); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int write_data_buf (flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - debug ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* Remap FLASH according to real size */ - memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CFG_OR_TIMING_FLASH | - OR_CSNT_SAM | OR_ACS_DIV1; - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V; - - debug ("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CFG_OR_TIMING_FLASH | - OR_CSNT_SAM | OR_ACS_DIV1; - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_PS_32 | BR_V; - - debug ("## BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_info[1].size = size_b1; - - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - memctl->memc_or1 = 0; /* invalidate bank */ - - debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - } - - debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x00020000 * 2; /* 128k * 2 chips per bank */ - } - return; - - default: - printf ("Don't know sector ofsets for flash type 0x%lx\n", - info->flash_id); - return; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: printf ("28F320J3A (32Mbit = 128K x 32)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64Mbit = 128K x 64)\n"); - break; - case FLASH_28F128J3A: printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - ulong value; - - /* Read Manufacturer ID */ - addr[0] = 0x00900090; - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { - case INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000 * 2; - break; /* => 8 MB */ - - case INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000 * 2; - break; /* => 16 MB */ - - case INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000 * 2; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = 0x00FF00FF; /* restore read mode */ - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = 0x00600060; /* clear lock bit setup */ - *addr = 0x00D000D0; /* clear lock bit confirm */ - - udelay (1000); - /* This takes awfully long - up to 50 ms and more */ - while (((status = *addr) & 0x00800080) != 0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0x00FF00FF; /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - udelay (1000); /* to trigger the watchdog */ - } - - *addr = 0x00500050; /* clear status register */ - *addr = 0x00200020; /* erase setup */ - *addr = 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & 0x00800080) != 0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0x00B000B0; /* suspend erase */ - *addr = 0x00FF00FF; /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - udelay (1000); /* to trigger the watchdog */ - } - - *addr = 0x00FF00FF; /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 4 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= FLASH_WIDTH) { - i = CFG_FLASH_BUFFER_SIZE > cnt ? - (cnt & ~(FLASH_WIDTH - 1)) : CFG_FLASH_BUFFER_SIZE; - if((rc = write_data_buf(info, wp, src,i)) != 0) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - while (cnt >= FLASH_WIDTH) { - data = 0; - for (i=0; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i tout) { - printf("Flash %s timeout at address %p\n", prompt, addr); - *addr = 0x00FF00FF; /* restore read mode */ - return (1); - } - } - return 0; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = 0x00400040; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - if (flash_status_check(addr, CFG_FLASH_WRITE_TOUT, "write") != 0) { - return (1); - } - - *addr = 0x00FF00FF; /* restore read mode */ - - return (0); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE -/*----------------------------------------------------------------------- - * Write a buffer to Flash, returns: - * 0 - OK - * 1 - write timeout - */ -static int write_data_buf(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - vu_long *addr = (vu_long *)dest; - int sector; - int cnt; - int retcode; - vu_long * src = (vu_long *)cp; - vu_long * dst = (vu_long *)dest; - - /* find sector */ - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(dest >= info->start[sector]) - break; - } - - *addr = 0x00500050; /* clear status */ - *addr = 0x00e800e8; /* write buffer */ - - if((retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT, - "write to buffer")) == 0) { - cnt = len / FLASH_WIDTH; - *addr = (cnt-1) | ((cnt-1) << 16); - while(cnt-- > 0) { - *dst++ = *src++; - } - *addr = 0x00d000d0; /* write buffer confirm */ - retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT, - "buffer write"); - } - *addr = 0x00FF00FF; /* restore read mode */ - *addr = 0x00500050; /* clear status */ - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ - -/*----------------------------------------------------------------------- - */ diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c deleted file mode 100644 index a174b57..0000000 --- a/board/lwmon/lwmon.c +++ /dev/null @@ -1,1068 +0,0 @@ -/*********************************************************************** - * -M* Modul: lwmon.c -M* -M* Content: LWMON specific U-Boot commands. - * - * (C) Copyright 2001, 2002 - * DENX Software Engineering - * Wolfgang Denk, wd@denx.de - * All rights reserved. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - ***********************************************************************/ - -/*---------------------------- Headerfiles ----------------------------*/ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include /* for strdup */ - -/*------------------------ Local prototypes ---------------------------*/ -static long int dram_size (long int, long int *, long int); -static void kbd_init (void); -static int compare_magic (uchar *kbd_data, uchar *str); - - -/*--------------------- Local macros and constants --------------------*/ -#define _NOT_USED_ 0xFFFFFFFF - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void); -extern void disable_putc(void); -#endif /* CONFIG_MODEM_SUPPORT */ - -/* - * 66 MHz SDRAM access using UPM A - */ -const uint sdram_table[] = -{ -#if defined(CFG_MEMORY_75) || defined(CFG_MEMORY_8E) - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, - 0x1FF5FC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - 0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF, -#endif -#ifdef CFG_MEMORY_7E - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00, - 0xE1BAFC04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - 0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF, -#endif -}; - -/* - * Check Board Identity: - * - */ - -/*********************************************************************** -F* Function: int checkboard (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int - 0 is always returned - * -Z* Intention: This function is the checkboard() method implementation -Z* for the lwmon board. Only a standard message is printed. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int checkboard (void) -{ - puts ("Board: LICCON Konsole LCD3\n"); - return (0); -} - -/*********************************************************************** -F* Function: long int initdram (int board_type) P*A*Z* - * -P* Parameters: int board_type -P* - Usually type of the board - ignored here. -P* -P* Returnvalue: long int -P* - Size of initialized memory - * -Z* Intention: This function is the initdram() method implementation -Z* for the lwmon board. -Z* The memory controller is initialized to access the -Z* DRAM. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -long int initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - long int size_b0; - long int size8, size9; - int i; - - /* - * Configure UPMA for SDRAM - */ - upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = CFG_MPTPR; - - /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = CFG_MAR; - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - - /* initialize memory address register */ - memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */ - - /* mode initialization (offset 5) */ - udelay (200); /* 0x80006105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05); - - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); - - udelay (1); /* 0x80006106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06); - - memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */ - - udelay (200); - - /* Need at least 10 DRAM accesses to stabilize */ - for (i = 0; i < 10; ++i) { - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE3_PRELIM; - unsigned long val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; - memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE; - udelay (500); - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE; - udelay (500); - } - - /* - * Final mapping: - */ - - memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | - OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING; - memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - udelay (1000); - - return (size_b0); -} - -/*********************************************************************** -F* Function: static long int dram_size (long int mamr_value, -F* long int *base, -F* long int maxsize) P*A*Z* - * -P* Parameters: long int mamr_value -P* - Value for MAMR for the test -P* long int *base -P* - Base address for the test -P* long int maxsize -P* - Maximum size to test for -P* -P* Returnvalue: long int -P* - Size of probed memory - * -Z* Intention: Check memory range for valid RAM. A simple memory test -Z* determines the actually available RAM size between -Z* addresses `base' and `base + maxsize'. Some (not all) -Z* hardware errors are detected: -Z* - short between address lines -Z* - short between data lines - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#ifndef PB_ENET_TENA -# define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ -#endif - -/*********************************************************************** -F* Function: int board_early_init_f (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int -P* - 0 is always returned. - * -Z* Intention: This function is the board_early_init_f() method implementation -Z* for the lwmon board. -Z* Disable Ethernet TENA on Port B. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int board_early_init_f (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - /* Disable Ethernet TENA on Port B - * Necessary because of pull up in COM3 port. - * - * This is just a preliminary fix, intended to turn off TENA - * as soon as possible to avoid noise on the network. Once - * I²C is running we will make sure the interface is - * correctly initialized. - */ - immr->im_cpm.cp_pbpar &= ~PB_ENET_TENA; - immr->im_cpm.cp_pbodr &= ~PB_ENET_TENA; - immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA; /* set to 0 = disabled */ - immr->im_cpm.cp_pbdir |= PB_ENET_TENA; - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/*********************************************************************** -F* Function: void reset_phy (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: none - * -Z* Intention: Reset the PHY. In the lwmon case we do this by the -Z* signaling the PIC I/O expander. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -void reset_phy (void) -{ - uchar c; - -#ifdef DEBUG - printf ("### Switch on Ethernet for SCC2 ###\n"); -#endif - c = pic_read (0x61); -#ifdef DEBUG - printf ("Old PIC read: reg_61 = 0x%02x\n", c); -#endif - c |= 0x40; /* disable COM3 */ - c &= ~0x80; /* enable Ethernet */ - pic_write (0x61, c); -#ifdef DEBUG - c = pic_read (0x61); - printf ("New PIC read: reg_61 = 0x%02x\n", c); -#endif - udelay (1000); -} - - -/*------------------------- Keyboard controller -----------------------*/ -/* command codes */ -#define KEYBD_CMD_READ_KEYS 0x01 -#define KEYBD_CMD_READ_VERSION 0x02 -#define KEYBD_CMD_READ_STATUS 0x03 -#define KEYBD_CMD_RESET_ERRORS 0x10 - -/* status codes */ -#define KEYBD_STATUS_MASK 0x3F -#define KEYBD_STATUS_H_RESET 0x20 -#define KEYBD_STATUS_BROWNOUT 0x10 -#define KEYBD_STATUS_WD_RESET 0x08 -#define KEYBD_STATUS_OVERLOAD 0x04 -#define KEYBD_STATUS_ILLEGAL_WR 0x02 -#define KEYBD_STATUS_ILLEGAL_RD 0x01 - -/* Number of bytes returned from Keyboard Controller */ -#define KEYBD_VERSIONLEN 2 /* version information */ -#define KEYBD_DATALEN 9 /* normal key scan data */ - -/* maximum number of "magic" key codes that can be assigned */ - -static uchar kbd_addr = CFG_I2C_KEYBD_ADDR; - -static uchar *key_match (uchar *); - -#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */ - -/*********************************************************************** -F* Function: int board_postclk_init (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int -P* - 0 is always returned. - * -Z* Intention: This function is the board_postclk_init() method implementation -Z* for the lwmon board. - * - ***********************************************************************/ -int board_postclk_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - kbd_init(); - -#ifdef CONFIG_MODEM_SUPPORT - if (key_pressed()) { - disable_putc(); /* modem doesn't understand banner etc */ - gd->do_mdm_init = 1; - } -#endif - - return (0); -} - -struct serial_device * default_serial_console (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device; -} - -static void kbd_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - uchar kbd_data[KEYBD_DATALEN]; - uchar tmp_data[KEYBD_DATALEN]; - uchar val, errcd; - int i; - - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - - gd->kbd_status = 0; - - /* Forced by PIC. Delays <= 175us loose */ - udelay(1000); - - /* Read initial keyboard error code */ - val = KEYBD_CMD_READ_STATUS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, &errcd, 1); - /* clear unused bits */ - errcd &= KEYBD_STATUS_MASK; - /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */ - errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT); - if (errcd) { - gd->kbd_status |= errcd << 8; - } - /* Reset error code and verify */ - val = KEYBD_CMD_RESET_ERRORS; - i2c_write (kbd_addr, 0, 0, &val, 1); - udelay(1000); /* delay NEEDED by keyboard PIC !!! */ - - val = KEYBD_CMD_READ_STATUS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, &val, 1); - - val &= KEYBD_STATUS_MASK; /* clear unused bits */ - if (val) { /* permanent error, report it */ - gd->kbd_status |= val; - return; - } - - /* - * Read current keyboard state. - * - * After the error reset it may take some time before the - * keyboard PIC picks up a valid keyboard scan - the total - * scan time is approx. 1.6 ms (information by Martin Rajek, - * 28 Sep 2002). We read a couple of times for the keyboard - * to stabilize, using a big enough delay. - * 10 times should be enough. If the data is still changing, - * we use what we get :-( - */ - - memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */ - for (i=0; i<10; ++i) { - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) { - /* consistent state, done */ - break; - } - /* remeber last state, delay, and retry */ - memcpy (tmp_data, kbd_data, KEYBD_DATALEN); - udelay (5000); - } -} - -/*********************************************************************** -F* Function: int misc_init_r (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int -P* - 0 is always returned, even in the case of a keyboard -P* error. - * -Z* Intention: This function is the misc_init_r() method implementation -Z* for the lwmon board. -Z* The keyboard controller is initialized and the result -Z* of a read copied to the environment variable "keybd". -Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for -Z* this key, and if found display to the LCD will be enabled. -Z* The keys in "keybd" are checked against the magic -Z* keycommands defined in the environment. -Z* See also key_match(). - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - uchar kbd_data[KEYBD_DATALEN]; - char keybd_env[2 * KEYBD_DATALEN + 1]; - uchar kbd_init_status = gd->kbd_status >> 8; - uchar kbd_status = gd->kbd_status; - uchar val; - char *str; - int i; - - if (kbd_init_status) { - printf ("KEYBD: Error %02X\n", kbd_init_status); - } - if (kbd_status) { /* permanent error, report it */ - printf ("*** Keyboard error code %02X ***\n", kbd_status); - sprintf (keybd_env, "%02X", kbd_status); - setenv ("keybd", keybd_env); - return 0; - } - - /* - * Now we know that we have a working keyboard, so disable - * all output to the LCD except when a key press is detected. - */ - - if ((console_assign (stdout, "serial") < 0) || - (console_assign (stderr, "serial") < 0)) { - printf ("Can't assign serial port as output device\n"); - } - - /* Read Version */ - val = KEYBD_CMD_READ_VERSION; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN); - printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]); - - /* Read current keyboard state */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf (keybd_env + i + i, "%02X", kbd_data[i]); - } - setenv ("keybd", keybd_env); - - str = strdup ((char *)key_match (kbd_data)); /* decode keys */ -#ifdef KEYBD_SET_DEBUGMODE - if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */ - if ((console_assign (stdout, "lcd") < 0) || - (console_assign (stderr, "lcd") < 0)) { - printf ("Can't assign LCD display as output device\n"); - } - } -#endif /* KEYBD_SET_DEBUGMODE */ -#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ - setenv ("preboot", str); /* set or delete definition */ -#endif /* CONFIG_PREBOOT */ - if (str != NULL) { - free (str); - } - return (0); -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -static int compare_magic (uchar *kbd_data, uchar *str) -{ - uchar compare[KEYBD_DATALEN-1]; - char *nxt; - int i; - - /* Don't include modifier byte */ - memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); - - for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) { - uchar c; - int k; - - c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16); - - if (str == (uchar *)nxt) { /* invalid character */ - break; - } - - /* - * Check if this key matches the input. - * Set matches to zero, so they match only once - * and we can find duplicates or extra keys - */ - for (k = 0; k < sizeof(compare); ++k) { - if (compare[k] == '\0') /* only non-zero entries */ - continue; - if (c == compare[k]) { /* found matching key */ - compare[k] = '\0'; - break; - } - } - if (k == sizeof(compare)) { - return -1; /* unmatched key */ - } - } - - /* - * A full match leaves no keys in the `compare' array, - */ - for (i = 0; i < sizeof(compare); ++i) { - if (compare[i]) - { - return -1; - } - } - - return 0; -} - -/*********************************************************************** -F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z* - * -P* Parameters: uchar *kbd_data -P* - The keys to match against our magic definitions -P* -P* Returnvalue: uchar * -P* - != NULL: Pointer to the corresponding command(s) -P* NULL: No magic is about to happen - * -Z* Intention: Check if pressed key(s) match magic sequence, -Z* and return the command string associated with that key(s). -Z* -Z* If no key press was decoded, NULL is returned. -Z* -Z* Note: the first character of the argument will be -Z* overwritten with the "magic charcter code" of the -Z* decoded key(s), or '\0'. -Z* -Z* Note: the string points to static environment data -Z* and must be saved before you call any function that -Z* modifies the environment. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -static uchar *key_match (uchar *kbd_data) -{ - char magic[sizeof (kbd_magic_prefix) + 1]; - uchar *suffix; - char *kbd_magic_keys; - - /* - * The following string defines the characters that can pe appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); -#if 0 - printf ("### Check magic \"%s\"\n", magic); -#endif - if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) { - char cmd_name[sizeof (kbd_command_prefix) + 1]; - char *cmd; - - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - - cmd = getenv (cmd_name); -#if 0 - printf ("### Set PREBOOT to $(%s): \"%s\"\n", - cmd_name, cmd ? cmd : "<>"); -#endif - *kbd_data = *suffix; - return ((uchar *)cmd); - } - } -#if 0 - printf ("### Delete PREBOOT\n"); -#endif - *kbd_data = '\0'; - return (NULL); -} -#endif /* CONFIG_PREBOOT */ - -/*---------------Board Special Commands: PIC read/write ---------------*/ - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) -/*********************************************************************** -F* Function: int do_pic (cmd_tbl_t *cmdtp, int flag, -F* int argc, char *argv[]) P*A*Z* - * -P* Parameters: cmd_tbl_t *cmdtp -P* - Pointer to our command table entry -P* int flag -P* - If the CMD_FLAG_REPEAT bit is set, then this call is -P* a repetition -P* int argc -P* - Argument count -P* char *argv[] -P* - Array of the actual arguments -P* -P* Returnvalue: int -P* - 0 The command was handled successfully -P* 1 An error occurred - * -Z* Intention: Implement the "pic [read|write]" commands. -Z* The read subcommand takes one argument, the register, -Z* whereas the write command takes two, the register and -Z* the new value. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - uchar reg, val; - - switch (argc) { - case 3: /* PIC read reg */ - if (strcmp (argv[1], "read") != 0) - break; - - reg = simple_strtoul (argv[2], NULL, 16); - - printf ("PIC read: reg %02x: %02x\n\n", reg, pic_read (reg)); - - return 0; - case 4: /* PIC write reg val */ - if (strcmp (argv[1], "write") != 0) - break; - - reg = simple_strtoul (argv[2], NULL, 16); - val = simple_strtoul (argv[3], NULL, 16); - - printf ("PIC write: reg %02x val 0x%02x: %02x => ", - reg, val, pic_read (reg)); - pic_write (reg, val); - printf ("%02x\n\n", pic_read (reg)); - return 0; - default: - break; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; -} -U_BOOT_CMD( - pic, 4, 1, do_pic, - "pic - read and write PIC registers\n", - "read reg - read PIC register `reg'\n" - "pic write reg val - write value `val' to PIC register `reg'\n" -); - -/*********************************************************************** -F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag, -F* int argc, char *argv[]) P*A*Z* - * -P* Parameters: cmd_tbl_t *cmdtp -P* - Pointer to our command table entry -P* int flag -P* - If the CMD_FLAG_REPEAT bit is set, then this call is -P* a repetition -P* int argc -P* - Argument count -P* char *argv[] -P* - Array of the actual arguments -P* -P* Returnvalue: int -P* - 0 is always returned. - * -Z* Intention: Implement the "kbd" command. -Z* The keyboard status is read. The result is printed on -Z* the console and written into the "keybd" environment -Z* variable. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - uchar kbd_data[KEYBD_DATALEN]; - char keybd_env[2 * KEYBD_DATALEN + 1]; - uchar val; - int i; - -#if 0 /* Done in kbd_init */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); -#endif - - /* Read keys */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - puts ("Keys:"); - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf (keybd_env + i + i, "%02X", kbd_data[i]); - printf (" %02x", kbd_data[i]); - } - putc ('\n'); - setenv ("keybd", keybd_env); - return 0; -} - -U_BOOT_CMD( - kbd, 1, 1, do_kbd, - "kbd - read keyboard status\n", - NULL -); - -/* Read and set LSB switch */ -#define CFG_PC_TXD1_ENA 0x0008 /* PC.12 */ - -/*********************************************************************** -F* Function: int do_lsb (cmd_tbl_t *cmdtp, int flag, -F* int argc, char *argv[]) P*A*Z* - * -P* Parameters: cmd_tbl_t *cmdtp -P* - Pointer to our command table entry -P* int flag -P* - If the CMD_FLAG_REPEAT bit is set, then this call is -P* a repetition -P* int argc -P* - Argument count -P* char *argv[] -P* - Array of the actual arguments -P* -P* Returnvalue: int -P* - 0 The command was handled successfully -P* 1 An error occurred - * -Z* Intention: Implement the "lsb [on|off]" commands. -Z* The lsb is switched according to the first parameter by -Z* by signaling the PIC I/O expander. -Z* Called with no arguments, the current setting is -Z* printed. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - uchar val; - immap_t *immr = (immap_t *) CFG_IMMR; - - switch (argc) { - case 1: /* lsb - print setting */ - val = pic_read (0x60); - printf ("LSB is o%s\n", (val & 0x20) ? "n" : "ff"); - return 0; - case 2: /* lsb on or lsb off - set switch */ - val = pic_read (0x60); - - if (strcmp (argv[1], "on") == 0) { - val |= 0x20; - immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA); - immr->im_ioport.iop_pcdat |= CFG_PC_TXD1_ENA; - immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA; - } else if (strcmp (argv[1], "off") == 0) { - val &= ~0x20; - immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA); - immr->im_ioport.iop_pcdat &= ~(CFG_PC_TXD1_ENA); - immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA; - } else { - break; - } - pic_write (0x60, val); - return 0; - default: - break; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD( - lsb, 2, 1, do_lsb, - "lsb - check and set LSB switch\n", - "on - switch LSB on\n" - "lsb off - switch LSB off\n" - "lsb - print current setting\n" -); - -#endif /* CFG_CMD_BSP */ - -/*----------------------------- Utilities -----------------------------*/ -/*********************************************************************** -F* Function: uchar pic_read (uchar reg) P*A*Z* - * -P* Parameters: uchar reg -P* - Register to read -P* -P* Returnvalue: uchar -P* - Value read from register - * -Z* Intention: Read a register from the PIC I/O expander. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -uchar pic_read (uchar reg) -{ - return (i2c_reg_read (CFG_I2C_PICIO_ADDR, reg)); -} - -/*********************************************************************** -F* Function: void pic_write (uchar reg, uchar val) P*A*Z* - * -P* Parameters: uchar reg -P* - Register to read -P* uchar val -P* - Value to write -P* -P* Returnvalue: none - * -Z* Intention: Write to a register on the PIC I/O expander. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -void pic_write (uchar reg, uchar val) -{ - i2c_reg_write (CFG_I2C_PICIO_ADDR, reg, val); -} - -/*---------------------- Board Control Functions ----------------------*/ -/*********************************************************************** -F* Function: void board_poweroff (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: none - * -Z* Intention: Turn off the battery power and loop endless, so this -Z* should better be the last function you call... - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -void board_poweroff (void) -{ - /* Turn battery off */ - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13)); - - while (1); -} - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void) -{ - uchar kbd_data[KEYBD_DATALEN]; - uchar val; - - /* Read keys */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - return (compare_magic(kbd_data, (uchar *)CONFIG_MODEM_KEY_MAGIC) == 0); -} -#endif /* CONFIG_MODEM_SUPPORT */ - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - uchar kbd_data[KEYBD_DATALEN]; - uchar val; - - /* Read keys */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0); -} -#endif diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds deleted file mode 100644 index 6505d45..0000000 --- a/board/lwmon/u-boot.lds +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - common/environment.o(.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug deleted file mode 100644 index 828afbb..0000000 --- a/board/lwmon/u-boot.lds.debug +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/m5272c3/Makefile b/board/m5272c3/Makefile deleted file mode 100644 index e5d8446..0000000 --- a/board/m5272c3/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/m5272c3/config.mk b/board/m5272c3/config.mk deleted file mode 100644 index ccb2cf7..0000000 --- a/board/m5272c3/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xffe00000 diff --git a/board/m5272c3/flash.c b/board/m5272c3/flash.c deleted file mode 100644 index fb91843..0000000 --- a/board/m5272c3/flash.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define PHYS_FLASH_1 CFG_FLASH_BASE -#define FLASH_BANK_SIZE 0x200000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_PL160CB & FLASH_TYPEMASK): - printf ("AM29PL160CB (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_PL160CB & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j == 0) { - /* 1st is 16 KiB */ - flash_info[i].start[j] = flashbase; - } - if ((j >= 1) && (j <= 2)) { - /* 2nd and 3rd are 8 KiB */ - flash_info[i].start[j] = - flashbase + 0x4000 + 0x2000 * (j - 1); - } - if (j == 3) { - /* 4th is 224 KiB */ - flash_info[i].start[j] = flashbase + 0x8000; - } - if ((j >= 4) && (j <= 10)) { - /* rest is 256 KiB */ - flash_info[i].start[j] = - flashbase + 0x40000 + 0x40000 * (j - - 4); - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0x3ffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/m5272c3/m5272c3.c b/board/m5272c3/m5272c3.c deleted file mode 100644 index 0dfeaf2..0000000 --- a/board/m5272c3/m5272c3.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - - -int checkboard (void) { - puts ("Board: "); - puts("MOTOROLA MCF5272C3 EVB\n"); - return 0; - }; - -long int initdram (int board_type) { - volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR); - - sdp->sdram_sdtr = 0xf539; - sdp->sdram_sdcr = 0x4211; - - /* Dummy write to start SDRAM */ - *((volatile unsigned long *)0) = 0; - - return CFG_SDRAM_SIZE * 1024 * 1024; - }; - -int testdram (void) { - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/m5272c3/u-boot.lds b/board/m5272c3/u-boot.lds deleted file mode 100644 index f7dc070..0000000 --- a/board/m5272c3/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(m68k) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mcf52x2/start.o (.text) - lib_m68k/traps.o (.text) - cpu/mcf52x2/interrupts.o (.text) - common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - *(.got) - __got_end = .; - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - _sbss = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/m5282evb/Makefile b/board/m5282evb/Makefile deleted file mode 100644 index e5d8446..0000000 --- a/board/m5282evb/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/m5282evb/config.mk b/board/m5282evb/config.mk deleted file mode 100644 index 8484307..0000000 --- a/board/m5282evb/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x20000 diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c deleted file mode 100644 index ff70783..0000000 --- a/board/m5282evb/flash.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define PHYS_FLASH_1 CFG_FLASH_BASE -#define FLASH_BANK_SIZE 0x200000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_PL160CB & FLASH_TYPEMASK): - printf ("AM29PL160CB (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_PL160CB & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j == 0) { - /* 1st is 16 KiB */ - flash_info[i].start[j] = flashbase; - } - if ((j >= 1) && (j <= 2)) { - /* 2nd and 3rd are 8 KiB */ - flash_info[i].start[j] = - flashbase + 0x4000 + 0x2000 * (j - 1); - } - if (j == 3) { - /* 4th is 32 KiB */ - flash_info[i].start[j] = flashbase + 0x8000; - } - if ((j >= 4) && (j <= 34)) { - /* rest is 256 KiB */ - flash_info[i].start[j] = - flashbase + 0x10000 + 0x10000 * (j - - 4); - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0xffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - - -volatile static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/m5282evb/m5282evb.c b/board/m5282evb/m5282evb.c deleted file mode 100644 index a08af68..0000000 --- a/board/m5282evb/m5282evb.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -int checkboard (void) -{ - puts ("MOTOROLA M5272EVB Evaluation Board\n"); - return 0; -} - -long int initdram (int board_type) -{ - return 0x1000000; -} diff --git a/board/m5282evb/u-boot.lds b/board/m5282evb/u-boot.lds deleted file mode 100644 index c461d20..0000000 --- a/board/m5282evb/u-boot.lds +++ /dev/null @@ -1,143 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(m68k) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mcf52x2/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/string.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset; */ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - __got_start = .; - *(.got) - __got_end = .; - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - _sbss = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mbx8xx/Makefile b/board/mbx8xx/Makefile deleted file mode 100644 index 3e8376c..0000000 --- a/board/mbx8xx/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o vpd.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/mbx8xx/config.mk b/board/mbx8xx/config.mk deleted file mode 100644 index d5e8ed2..0000000 --- a/board/mbx8xx/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MBX8xx boards -# - -TEXT_BASE = 0xfe000000 -/*TEXT_BASE = 0x00200000 */ diff --git a/board/mbx8xx/csr.h b/board/mbx8xx/csr.h deleted file mode 100644 index 832e924..0000000 --- a/board/mbx8xx/csr.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef __csr_h -#define __csr_h - -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Control and Status Register definitions for the MBX - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* bits for control register #1 / status register #1 */ -#define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */ -#define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */ -#define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */ -#define CSR1_TPEN 0x10 /* TP manually selected */ -#define CSR1_FDDIS 0x08 /* Full Duplex Mode disabled */ -#define CSR1_FCTEN 0x04 /* Collision Testing of XCVR disabled */ -#define CSR1_COM1EN 0x02 /* COM1 signals routed to RS232 Transceiver */ -#define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */ - -/* bits for control register #2 */ -#define CR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ -#define CR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ -#define CR2_BRDFAIL 0x08 /* Board fail */ -#define CR2_SWS1 0x04 /* Software Status #2 LED */ -#define CR2_SWS2 0x02 /* Software Status #2 LED */ -#define CR2_QSPANRST 0x01 /* Reset QSPAN */ - -/* bits for status register #2 */ -#define SR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ -#define SR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ -#define SR2_BATGD 0x08 /* Low Voltage indication for onboard bat */ -#define SR2_NVBATGD 0x04 /* Low Voltage indication for NVRAM */ -#define SR2_RDY 0x02 /* Flash programming status bit */ -#define SR2_FT 0x01 /* Reserved for Factory test purposes */ - -#define MBX_CSR1 (*((uchar *)CFG_CSR_BASE)) -#define MBX_CSR2 (*((uchar *)CFG_CSR_BASE + 1)) - -#endif /* __csr_h */ diff --git a/board/mbx8xx/dimm.h b/board/mbx8xx/dimm.h deleted file mode 100644 index b40f112..0000000 --- a/board/mbx8xx/dimm.h +++ /dev/null @@ -1,98 +0,0 @@ -#ifndef __dimm_h -#define __dimm_h - -/* - * Module name: %M% - * Description: - * Serial Presence Detect Definitions Module - * SCCS identification: %I% - * Branch: %B% - * Sequence: %S% - * Date newest applied delta was created (MM/DD/YY): %G% - * Time newest applied delta was created (HH:MM:SS): %U% - * SCCS file name %F% - * Fully qualified SCCS file name: - * %P% - * Copyright: - * (C) COPYRIGHT MOTOROLA, INC. 1996 - * ALL RIGHTS RESERVED - * Notes: - * 1. All data was taken from an IBM application note titled - * "Serial Presence Detect Definitions". - * History: - * Date Who - * - * 10/24/96 Rob Baxter - * Initial release. - * - */ - -/* - * serial PD byte assignment address map (256 byte EEPROM) - */ -typedef struct dimm -{ - uchar n_bytes; /* 00 number of bytes written/used */ - uchar t_bytes; /* 01 total number of bytes in serial PD device */ - uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */ - uchar n_row; /* 03 number of rows */ - uchar n_col; /* 04 number of columns */ - uchar n_banks; /* 05 number of banks */ - uchar data_w_lo; /* 06 data width */ - uchar data_w_hi; /* 07 data width */ - uchar ifl; /* 08 interface levels */ - uchar a_ras; /* 09 RAS access */ - uchar a_cas; /* 0A CAS access */ - uchar ct; /* 0B configuration type (non-parity/parity/ECC) */ - uchar refresh_rt; /* 0C refresh rate/type */ - uchar p_dram_o; /* 0D primary DRAM organization */ - uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */ - uchar reserved[17]; /* 0F reserved fields for future offerings */ - uchar ss_info[32]; /* 20 superset information (may be used in the future) */ - uchar m_info[64]; /* 40 manufacturer information (optional) */ - uchar unused[128]; /* 80 unused storage locations */ -} dimm_t; - -/* - * memory type definitions - */ -#define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */ -#define DIMM_MT_EDO 2 /* EDO (extended data out) */ -#define DIMM_MT_PN 3 /* pipelined nibble */ -#define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */ - -/* - * row addresses definitions - */ -#define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */ -#define DIMM_RA_MASK 0x7f /* number of row addresses mask */ - -/* - * module interface levels definitions - */ -#define DIMM_IFL_TTL 0 /* TTL/5V tolerant */ -#define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */ -#define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */ -#define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */ -#define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */ - -/* - * DIMM configuration type definitions - */ -#define DIMM_CT_NONE 0 /* none */ -#define DIMM_CT_PARITY 1 /* parity */ -#define DIMM_CT_ECC 2 /* ECC */ - -/* - * row addresses definitions - */ -#define DIMM_RRT_SR (1<<7) /* self refresh flag */ -#define DIMM_RRT_MASK 0x7f /* refresh rate mask */ -#define DIMM_RRT_NRML 0x00 /* normal (15.625us) */ -#define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */ -#define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */ -#define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */ -#define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */ -#define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */ - -#endif /* __dimm_h */ diff --git a/board/mbx8xx/flash.c b/board/mbx8xx/flash.c deleted file mode 100644 index a491f7b..0000000 --- a/board/mbx8xx/flash.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AM290[48]0B devices - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "vpd.h" - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size, totsize; - int i; - ulong addr; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - return (totsize); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id >> 16) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F080B: - printf ("AM29F080B (8 Mbit)\n"); - break; - case AMD_ID_F016D: - printf ("AM29F016D (16 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong vendor, devid; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - - vendor = addr[0]; - devid = addr[1] & 0xff; - - /* only support AMD */ - if (vendor != 0x01010101) { - return 0; - } - - vendor &= 0xf; - devid &= 0xff; - - if (devid == AMD_ID_F040B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 8; - info->size = info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F080B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 16; - info->size = 4 * info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F016D) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 32; - info->size = 4 * info->sector_count * 0x10000; - } - else { - printf ("## Unknown Flash Type: %08lx\n", devid); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0XAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0XAAAAAAAA; - addr[0x02AA] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c deleted file mode 100644 index 9a9bf80..0000000 --- a/board/mbx8xx/mbx8xx.c +++ /dev/null @@ -1,379 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Board specific routines for the MBX - * - * - initialisation - * - interface to VPD data (mac address, clock speeds) - * - memory controller - * - serial io initialisation - * - ethernet io initialisation - * - * ----------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "dimm.h" -#include "vpd.h" -#include "csr.h" - -/* ------------------------------------------------------------------------- */ - -static const uint sdram_table_40[] = { - /* DRAM - single read. (offset 0 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00, - 0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst read. (offset 8 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08, - 0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08, - 0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - single write. (offset 18 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst write. (offset 20 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* refresh (offset 30 in upm RAM) - */ - 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, - 0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* exception. (offset 3c in upm RAM) - */ - 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, -}; - -static const uint sdram_table_50[] = { - /* DRAM - single read. (offset 0 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04, - 0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst read. (offset 8 in upm RAM) - */ - 0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04, - /* 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */ - 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, - 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04, - /* 0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */ - 0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005, - - /* DRAM - single write. (offset 18 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804, - 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst write. (offset 20 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* refresh (offset 30 in upm RAM) - */ - 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, - 0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* exception. (offset 3c in upm RAM) - */ - 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, -}; - -/* ------------------------------------------------------------------------- */ - -static unsigned int get_reffreq(void); -static unsigned int board_get_cpufreq(void); - -void mbx_init (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - ulong speed, refclock, plprcr, sccr; - ulong br0_32 = memctl->memc_br0 & 0x400; - - /* real-time clock status and control register */ - immr->im_sitk.sitk_rtcsck = KAPWR_KEY; - immr->im_sit.sit_rtcsc = 0x00C3; - - /* SIEL and SIMASK Registers (see MBX PRG 2-3) */ - immr->im_siu_conf.sc_simask = 0x00000000; - immr->im_siu_conf.sc_siel = 0xAAAA0000; - immr->im_siu_conf.sc_tesr = 0xFFFFFFFF; - - /* - * Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus: - * 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h) - * 2. RAM Specs (see dimm.h) - * 2. DIMM Specs (see dimm.h) - */ - vpd_init (); - - /* system clock and reset control register */ - immr->im_clkrstk.cark_sccrk = KAPWR_KEY; - sccr = immr->im_clkrst.car_sccr; - sccr &= SCCR_MASK; - sccr |= CFG_SCCR; - immr->im_clkrst.car_sccr = sccr; - - speed = board_get_cpufreq (); - refclock = get_reffreq (); - -#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0) - plprcr = CFG_PLPRCR; -#else - plprcr = immr->im_clkrst.car_plprcr; - plprcr &= PLPRCR_MF_MSK; /* isolate MF field */ - plprcr |= CFG_PLPRCR; /* reset control bits */ -#endif - -#ifdef CFG_USE_OSCCLK /* See doc/README.MBX ! */ - plprcr |= ((speed + refclock / 2) / refclock - 1) << 20; -#endif - - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - immr->im_clkrst.car_plprcr = plprcr; - - /* - * preliminary setup of memory controller: - * - map Flash, otherwise configuration/status - * registers won't be accessible when read - * by board_init_f. - * - map NVRAM and configuation/status registers. - * - map pci registers. - * - DON'T map ram yet, this is done in initdram(). - */ - switch (speed / 1000000) { - case 40: - memctl->memc_br0 = 0xFE000000 | br0_32 | 1; - memctl->memc_or0 = 0xFF800930; - memctl->memc_or4 = CFG_NVRAM_OR | 0x920; - memctl->memc_br4 = CFG_NVRAM_BASE | 0x401; - break; - case 50: - memctl->memc_br0 = 0xFE000000 | br0_32 | 1; - memctl->memc_or0 = 0xFF800940; - memctl->memc_or4 = CFG_NVRAM_OR | 0x930; - memctl->memc_br4 = CFG_NVRAM_BASE | 0x401; - break; - default: - hang (); - break; - } -#ifdef CONFIG_USE_PCI - memctl->memc_or5 = CFG_PCIMEM_OR; - memctl->memc_br5 = CFG_PCIMEM_BASE | 0x001; - memctl->memc_or6 = CFG_PCIBRIDGE_OR; - memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001; -#endif - /* - * FIXME: I do not understand why I have to call this to - * initialise the control register here before booting from - * the PCMCIA card but if I do not the Linux kernel falls - * over in a big heap. If you can answer this question I - * would like to know about it. - */ - board_ether_init(); -} - -void board_serial_init (void) -{ - MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS); -} - -void board_ether_init (void) -{ - MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN); - MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS; -} - -static unsigned int board_get_cpufreq (void) -{ -#ifndef CONFIG_8xx_GCLK_FREQ - vpd_packet_t *packet; - - packet = vpd_find_packet (VPD_PID_ICS); - return *((ulong *) packet->data); -#else - return((unsigned int)CONFIG_8xx_GCLK_FREQ ); -#endif /* CONFIG_8xx_GCLK_FREQ */ -} - -static unsigned int get_reffreq (void) -{ - vpd_packet_t *packet; - - packet = vpd_find_packet (VPD_PID_RCS); - return *((ulong *) packet->data); -} - -void board_get_enetaddr (uchar * addr) -{ - int i; - vpd_packet_t *packet; - - packet = vpd_find_packet (VPD_PID_EA); - for (i = 0; i < 6; i++) - addr[i] = packet->data[i]; -} - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - vpd_packet_t *packet; - int i; - const char *const fmt = - "\n *** Warning: Low Battery Status - %s Battery ***"; - - puts ("Board: "); - - packet = vpd_find_packet (VPD_PID_PID); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - packet = vpd_find_packet (VPD_PID_MT); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - serial_putc ('('); - packet = vpd_find_packet (VPD_PID_FAN); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - serial_putc (')'); - - if (!(MBX_CSR2 & SR2_BATGD)) - printf (fmt, "On-Board"); - if (!(MBX_CSR2 & SR2_NVBATGD)) - printf (fmt, "NVRAM"); - - serial_putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -static ulong get_ramsize (dimm_t * dimm) -{ - ulong size = 0; - - if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3 - || dimm->fmt == 4) { - size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks * - ((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8); - } - - return size; -} - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long ram_sz = 0; - unsigned long dimm_sz = 0; - dimm_t vpd_dimm, vpd_dram; - unsigned int speed = board_get_cpufreq () / 1000000; - - if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) { - dimm_sz = get_ramsize (&vpd_dimm); - } - if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) { - ram_sz = get_ramsize (&vpd_dram); - } - - /* - * Only initialize memory controller when running from FLASH. - * When running from RAM, don't touch it. - */ - if ((ulong) initdram & 0xff000000) { - ulong dimm_bank; - ulong br0_32 = memctl->memc_br0 & 0x400; - - switch (speed) { - case 40: - upmconfig (UPMA, (uint *) sdram_table_40, - sizeof (sdram_table_40) / sizeof (uint)); - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000; - memctl->memc_or7 = 0xff800930; - memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; - break; - case 50: - upmconfig (UPMA, (uint *) sdram_table_50, - sizeof (sdram_table_50) / sizeof (uint)); - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100; - memctl->memc_or7 = 0xff800940; - memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; - break; - default: - hang (); - break; - } - - /* now map ram and dimm, largest one first */ - dimm_bank = dimm_sz / 2; - if (!dimm_sz) { - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = CFG_SDRAM_BASE | 0x81; - memctl->memc_br2 = 0; - memctl->memc_br3 = 0; - } else if (ram_sz > dimm_bank) { - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = CFG_SDRAM_BASE | 0x81; - memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br2 = (CFG_SDRAM_BASE + ram_sz) | 0x81; - memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br3 = (CFG_SDRAM_BASE + ram_sz + dimm_bank) \ - | 0x81; - } else { - memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br2 = CFG_SDRAM_BASE | 0x81; - memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br3 = (CFG_SDRAM_BASE + dimm_bank) | 0x81; - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = (CFG_SDRAM_BASE + dimm_sz) | 0x81; - } - } - - return ram_sz + dimm_sz; -} diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds deleted file mode 100644 index 1400cea..0000000 --- a/board/mbx8xx/u-boot.lds +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug deleted file mode 100644 index 650572d..0000000 --- a/board/mbx8xx/u-boot.lds.debug +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mbx8xx/vpd.c b/board/mbx8xx/vpd.c deleted file mode 100644 index 6f88352..0000000 --- a/board/mbx8xx/vpd.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Code in faintly related to linux/arch/ppc/8xx_io: - * MPC8xx CPM I2C interface. Copyright (c) 1999 Dan Malek (dmalek@jlc.net). - * - * This file implements functions to read the MBX's Vital Product Data - * (VPD). I can't use the more general i2c code in mpc8xx/... since I need - * the VPD at a time where there is no RAM available yet. Hence the VPD is - * read into a special area in the DPRAM (see config_MBX.h::CFG_DPRAMVPD). - * - * ----------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#ifdef CONFIG_8xx -#include -#endif -#include "vpd.h" - -/* Location of receive/transmit buffer descriptors - * Allocate one transmit bd and one receive bd. - * IIC_BD_FREE points to free bd space which we'll use as tx buffer. - */ -#define IIC_BD_TX1 (BD_IIC_START + 0*sizeof(cbd_t)) -#define IIC_BD_TX2 (BD_IIC_START + 1*sizeof(cbd_t)) -#define IIC_BD_RX (BD_IIC_START + 2*sizeof(cbd_t)) -#define IIC_BD_FREE (BD_IIC_START + 3*sizeof(cbd_t)) - -/* FIXME -- replace 0x2000 with offsetof */ -#define VPD_P ((vpd_t *)(CFG_IMMR + 0x2000 + CFG_DPRAMVPD)) - -/* transmit/receive buffers */ -#define IIC_RX_LENGTH 128 - -#define WITH_MICROCODE_PATCH - -vpd_packet_t * vpd_find_packet(u_char ident) -{ - vpd_packet_t *packet; - vpd_t *vpd = VPD_P; - - packet = (vpd_packet_t *)&vpd->packets; - while ((packet->identifier != ident) && packet->identifier != 0xFF) - { - packet = (vpd_packet_t *)((char *)packet + packet->size + 2); - } - return packet; -} - -void vpd_init(void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); - volatile iic_t *iip; -#ifdef WITH_MICROCODE_PATCH - ulong reloc = 0; -#endif - - iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - - /* - * kludge: when running from flash, no microcode patch can be - * installed. However, the DPMEM usually contains non-zero - * garbage at the relocatable patch base location, so lets clear - * it now. This way the rest of the code can support the microcode - * patch dynamically. - */ - if ((ulong)vpd_init & 0xff000000) - iip->iic_rpbase = 0; - -#ifdef WITH_MICROCODE_PATCH - /* Check for and use a microcode relocation patch. */ - if ((reloc = iip->iic_rpbase)) - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - /* Initialize Port B IIC pins */ - cp->cp_pbpar |= 0x00000030; - cp->cp_pbdir |= 0x00000030; - cp->cp_pbodr |= 0x00000030; - - i2c->i2c_i2mod = 0x04; /* filter clock */ - i2c->i2c_i2add = 0x34; /* select an arbitrary (unique) address */ - i2c->i2c_i2brg = 0x07; /* make clock run maximum slow */ - i2c->i2c_i2cmr = 0x00; /* disable interrupts */ - i2c->i2c_i2cer = 0x1f; /* clear events */ - i2c->i2c_i2com = 0x01; /* configure i2c to work as master */ - - if (vpd_read(0xa4, (uchar*)VPD_P, VPD_EEPROM_SIZE, 0) != VPD_EEPROM_SIZE) - { - hang(); - } -} - - -/* Read from I2C. - * This is a two step process. First, we send the "dummy" write - * to set the device offset for the read. Second, we perform - * the read operation. - */ -int vpd_read(uint iic_device, uchar *buf, int count, int offset) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); - volatile iic_t *iip; - volatile cbd_t *tbdf1, *tbdf2, *rbdf; - uchar *tb; - uchar event; -#ifdef WITH_MICROCODE_PATCH - ulong reloc = 0; -#endif - - iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; -#ifdef WITH_MICROCODE_PATCH - /* Check for and use a microcode relocation patch. */ - if ((reloc = iip->iic_rpbase)) - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - tbdf1 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX1]; - tbdf2 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX2]; - rbdf = (cbd_t *)&cp->cp_dpmem[IIC_BD_RX]; - - /* Send a "dummy write" operation. This is a write request with - * only the offset sent, followed by another start condition. - * This will ensure we start reading from the first location - * of the EEPROM. - */ - tb = (uchar*)&cp->cp_dpmem[IIC_BD_FREE]; - tb[0] = iic_device & 0xfe; /* device address */ - tb[1] = offset; /* offset */ - tbdf1->cbd_bufaddr = (uint)tb; - tbdf1->cbd_datlen = 2; - tbdf1->cbd_sc = 0x8400; - - tb += 2; - tb[0] = iic_device | 1; /* device address */ - tbdf2->cbd_bufaddr = (uint)tb; - tbdf2->cbd_datlen = count+1; - tbdf2->cbd_sc = 0xbc00; - - rbdf->cbd_bufaddr = (uint)buf; - rbdf->cbd_datlen = 0; - rbdf->cbd_sc = 0xb000; - - iip->iic_tbase = IIC_BD_TX1; - iip->iic_tbptr = IIC_BD_TX1; - iip->iic_rbase = IIC_BD_RX; - iip->iic_rbptr = IIC_BD_RX; - iip->iic_rfcr = 0x15; - iip->iic_tfcr = 0x15; - iip->iic_mrblr = count; - iip->iic_rstate = 0; - iip->iic_tstate = 0; - - i2c->i2c_i2cer = 0x1f; /* clear event mask */ - i2c->i2c_i2mod |= 1; /* enable iic operation */ - i2c->i2c_i2com |= 0x80; /* start master */ - - /* wait for IIC transfer */ - do { - __asm__ volatile ("eieio"); - event = i2c->i2c_i2cer; - } while (event == 0); - - if ((event & 0x10) || (event & 0x04)) { - count = -1; - goto bailout; - } - -bailout: - i2c->i2c_i2mod &= ~1; /* turn off iic operation */ - i2c->i2c_i2cer = 0x1f; /* clear event mask */ - - return count; -} diff --git a/board/mbx8xx/vpd.h b/board/mbx8xx/vpd.h deleted file mode 100644 index 1d9eb7f..0000000 --- a/board/mbx8xx/vpd.h +++ /dev/null @@ -1,119 +0,0 @@ -#ifndef __vpd_h -#define __vpd_h - -/* - * Module name: %M% - * Description: - * Vital Product Data (VPD) Header Module - * SCCS identification: %I% - * Branch: %B% - * Sequence: %S% - * Date newest applied delta was created (MM/DD/YY): %G% - * Time newest applied delta was created (HH:MM:SS): %U% - * SCCS file name %F% - * Fully qualified SCCS file name: - * %P% - * Copyright: - * (C) COPYRIGHT MOTOROLA, INC. 1996 - * ALL RIGHTS RESERVED - * Notes: - * History: - * Date Who - * - * 10/24/96 Rob Baxter - * Initial release. - * - */ - -#define VPD_EEPROM_SIZE 256 /* EEPROM size in bytes */ - -/* - * packet tuple identifiers - * - * 0x0D - 0xBF reserved - * 0xC0 - 0xFE user defined - */ -#define VPD_PID_GI 0x00 /* guaranteed illegal */ -#define VPD_PID_PID 0x01 /* product identifier (ASCII) */ -#define VPD_PID_FAN 0x02 /* factory assembly-number (ASCII) */ -#define VPD_PID_SN 0x03 /* serial-number (ASCII) */ -#define VPD_PID_PCO 0x04 /* product configuration options(binary) */ -#define VPD_PID_ICS 0x05 /* internal clock speed in HZ (integer) */ -#define VPD_PID_ECS 0x06 /* external clock speed in HZ (integer) */ -#define VPD_PID_RCS 0x07 /* reference clock speed in HZ(integer) */ -#define VPD_PID_EA 0x08 /* ethernet address (binary) */ -#define VPD_PID_MT 0x09 /* microprocessor type (ASCII) */ -#define VPD_PID_CRC 0x0A /* EEPROM CRC (integer) */ -#define VPD_PID_FMC 0x0B /* FLASH memory configuration (binary) */ -#define VPD_PID_VLSI 0x0C /* VLSI revisions/versions (binary) */ -#define VPD_PID_TERM 0xFF /* termination */ - -/* - * VPD structure (format) - */ -#define VPD_EYE_SIZE 8 /* eyecatcher size */ -typedef struct vpd_header -{ - uchar eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "MOTOROLA" */ - ushort size; /* size of EEPROM */ -} vpd_header_t; - -#define VPD_DATA_SIZE (VPD_EEPROM_SIZE-sizeof(vpd_header_t)) -typedef struct vpd -{ - vpd_header_t header; /* header */ - uchar packets[VPD_DATA_SIZE]; /* data */ -} vpd_t; - -/* - * packet tuple structure (format) - */ -typedef struct vpd_packet -{ - uchar identifier; /* identifier (PIDs above) */ - uchar size; /* size of the following data area */ - uchar data[1]; /* data (size is dependent upon PID) */ -} vpd_packet_t; - -/* - * MBX product configuration options bit definitions - * - * Notes: - * 1. The bit numbering is reversed in perspective with the C compiler. - */ -#define PCO_BBRAM (1<<0) /* battery-backed RAM (BBRAM) and socket */ -#define PCO_BOOTROM (1<<1) /* boot ROM and socket (i.e., socketed FLASH) */ -#define PCO_KAPWR (1<<2) /* keep alive power source (lithium battey) and control circuit */ -#define PCO_ENET_TP (1<<3) /* ethernet twisted pair (TP) connector (RJ45) */ -#define PCO_ENET_AUI (1<<4) /* ethernet attachment unit interface (AUI) header */ -#define PCO_PCMCIA (1<<5) /* PCMCIA socket */ -#define PCO_DIMM (1<<6) /* DIMM module socket */ -#define PCO_DTT (1<<7) /* digital thermometer and thermostat (DTT) device */ -#define PCO_LCD (1<<8) /* liquid crystal display (LCD) device */ -#define PCO_PCI (1<<9) /* PCI-Bus bridge device (QSpan) and ISA-Bus bridge device (Winbond) */ -#define PCO_PCIO (1<<10) /* PC I/O (COM1, COM2, FDC, LPT, Keyboard/Mouse) */ -#define PCO_EIDE (1<<11) /* enhanced IDE (EIDE) header */ -#define PCO_FDC (1<<12) /* floppy disk controller (FDC) header */ -#define PCO_LPT_8XX (1<<13) /* parallel port header via MPC8xx */ -#define PCO_LPT_PCIO (1<<14) /* parallel port header via PC I/O */ - -/* - * FLASH memory configuration packet data - */ -typedef struct vpd_fmc -{ - ushort mid; /* manufacturer's idenitfier */ - ushort did; /* manufacturer's device idenitfier */ - uchar ddw; /* device data width (e.g., 8-bits, 16-bits) */ - uchar nod; /* number of devices present */ - uchar noc; /* number of columns */ - uchar cw; /* column width in bits */ - uchar wedw; /* write/erase data width */ -} vpd_fmc_t; - -/* function prototypes */ -extern void vpd_init(void); -extern int vpd_read(uint iic_device, uchar *buf, int count, int offset); -extern vpd_packet_t *vpd_find_packet(u_char ident); - -#endif /* __vpd_h */ diff --git a/board/ml2/Makefile b/board/ml2/Makefile deleted file mode 100644 index 40c60b1..0000000 --- a/board/ml2/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o serial.o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/ml2/config.mk b/board/ml2/config.mk deleted file mode 100644 index 41118d5..0000000 --- a/board/ml2/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0x18000000 diff --git a/board/ml2/flash.c b/board/ml2/flash.c deleted file mode 100644 index 87cb1ff..0000000 --- a/board/ml2/flash.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * flash.c: Support code for the flash chips on the Xilinx ML2 board - * - * Copyright 2002 Mind NV - * - * http://www.mind.be/ - * - * Author : Peter De Schrijver (p2@mind.be) - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire program - * is licensed under the GPL. - * - */ - -#include -#include -#include - -#define FLASH_BANK_SIZE (64*1024*1024) - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -#define SECT_SIZE (512*1024) - -#define CMD_READ_ARRAY 0x00FF00FF00FF00FULL -#define CMD_IDENTIFY 0x0090009000900090ULL -#define CMD_ERASE_SETUP 0x0020002000200020ULL -#define CMD_ERASE_CONFIRM 0x00D000D000D000D0ULL -#define CMD_PROGRAM 0x0040004000400040ULL -#define CMD_RESUME 0x00D000D000D000D0ULL -#define CMD_SUSPEND 0x00B000B000B000B0ULL -#define CMD_STATUS_READ 0x0070007000700070ULL -#define CMD_STATUS_RESET 0x0050005000500050ULL - -#define BIT_BUSY 0x0080008000800080ULL -#define BIT_ERASE_SUSPEND 0x004000400400040ULL -#define BIT_ERASE_ERROR 0x0020002000200020ULL -#define BIT_PROGRAM_ERROR 0x0010001000100010ULL -#define BIT_VPP_RANGE_ERROR 0x0008000800080008ULL -#define BIT_PROGRAM_SUSPEND 0x0004000400040004ULL -#define BIT_PROTECT_ERROR 0x0002000200020002ULL -#define BIT_UNDEFINED 0x0001000100010001ULL - -#define BIT_SEQUENCE_ERROR 0x0030003000300030ULL - -#define BIT_TIMEOUT 0x80000000 - - -inline void eieio(void) { - - __asm__ __volatile__ ("eieio" : : : "memory"); - -} - -ulong flash_init(void) { - - int i, j; - ulong size = 0; - - for(i=0;iflash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf("Intel: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F128J3A & FLASH_TYPEMASK): - printf("4x 28F128J3A (128Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) - printf("\n "); - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -int flash_error (unsigned long long code) { - - if (code & BIT_TIMEOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - - if (~code & BIT_BUSY) { - printf ("Busy\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_VPP_RANGE_ERROR) { - printf ("Vpp range error\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_PROTECT_ERROR) { - printf ("Device protect error\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_SEQUENCE_ERROR) { - printf ("Command seqence error\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_ERASE_ERROR) { - printf ("Block erase error\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_PROGRAM_ERROR) { - printf ("Program error\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_ERASE_SUSPEND) { - printf ("Block erase suspended\n"); - return ERR_PROG_ERROR; - } - - if (code & BIT_PROGRAM_SUSPEND) { - printf ("Program suspended\n"); - return ERR_PROG_ERROR; - } - - return ERR_OK; - -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) { - - int rc = ERR_OK; - int sect; - unsigned long long result; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) - return ERR_INVAL; - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - for (sect=s_first; sect<=s_last; ++sect) - if (info->protect[sect]) - return ERR_PROTECTED; - - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { - volatile unsigned long long *addr= - (unsigned long long *)(info->start[sect]); - - printf("Erasing sector %2d ... ", sect); - - *addr=CMD_STATUS_RESET; - eieio(); - *addr=CMD_ERASE_SETUP; - eieio(); - *addr=CMD_ERASE_CONFIRM; - eieio(); - - do { - result = *addr; - } while(~result & BIT_BUSY); - - *addr=CMD_READ_ARRAY; - - if ((rc = flash_error(result)) == ERR_OK) - printf("ok.\n"); - else - break; - } - - if (ctrlc()) - printf("User Interrupt!\n"); - - return rc; -} - -static int write_word (flash_info_t *info, ulong dest, unsigned long long data) { - - volatile unsigned long long *addr=(unsigned long long *)dest; - unsigned long long result; - int rc = ERR_OK; - - result=*addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - *addr=CMD_STATUS_RESET; - eieio(); - *addr=CMD_PROGRAM; - eieio(); - *addr=data; - eieio(); - - do { - result=*addr; - } while(~result & BIT_BUSY); - - *addr=CMD_READ_ARRAY; - - rc = flash_error(result); - - return rc; - -} - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { - - ulong cp, wp; - unsigned long long data; - int l; - int i,rc; - - wp=(addr & ~7); - - if((l=addr-wp) != 0) { - data=0; - for(i=0,cp=wp;i> 8) | (*(uchar *)cp << 24); - - for (; i<8 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - - for (; i<8; ++i, ++cp) - data = (data >> 8) | (*(uchar *)cp << 24); - - if ((rc = write_word(info, wp, data)) != 0) - return rc; - - wp+=8; - } - - while(cnt>=8) { - data=*((unsigned long long *)src); - if ((rc = write_word(info, wp, data)) != 0) - return rc; - src+=8; - wp+=8; - cnt-=8; - } - - if(cnt == 0) - return ERR_OK; - - data = 0; - for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i<8; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - return write_word(info, wp, data); - -} diff --git a/board/ml2/init.S b/board/ml2/init.S deleted file mode 100644 index 80f98c5..0000000 --- a/board/ml2/init.S +++ /dev/null @@ -1,34 +0,0 @@ -/* - * init.S: Stubs for U-Boot initialization - * - * Copyright 2002 Mind NV - * - * http://www.mind.be/ - * - * Author : Peter De Schrijver (p2@mind.be) - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#include - -#include -#include - -#include -#include - - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - blr - - .globl sdram_init -sdram_init: - blr diff --git a/board/ml2/ml2.c b/board/ml2/ml2.c deleted file mode 100644 index f32e512..0000000 --- a/board/ml2/ml2.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * ml2.c: U-Boot platform support for Xilinx ML2 board - * - * Copyright 2002 Mind NV - * - * http://www.mind.be/ - * - * Author : Peter De Schrijver (p2@mind.be) - * - * Derived from : Other platform support files in this tree - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#include -#include - - -int board_early_init_f (void) -{ - return 0; -} - - -int checkboard (void) -{ - char *s = getenv ("serial#"); - char *e; - - if (!s || strncmp (s, "ML2", 9)) { - printf ("### No HW ID - assuming ML2"); - } else { - for (e = s; *e; ++e) { - if (*e == ' ') - break; - } - - for (; s < e; ++s) { - putc (*s); - } - } - - - putc ('\n'); - - return (0); -} - - -long int initdram (int board_type) -{ - return 32 * 1024 * 1024; -} - -int testdram (void) -{ - printf ("test: xxx MB - ok\n"); - - return (0); -} diff --git a/board/ml2/serial.c b/board/ml2/serial.c deleted file mode 100644 index 92baba9..0000000 --- a/board/ml2/serial.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2002 - * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include - -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) -#include -#endif - -#if 0 -#include "serial.h" -#endif - -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) -const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, - (NS16550_t) CFG_NS16550_COM2 }; -#endif - -int -serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CFG_INIT_CHAN1 - (void)NS16550_init(COM_PORTS[0], clock_divisor); -#endif -#ifdef CFG_INIT_CHAN2 - (void)NS16550_init(COM_PORTS[1], clock_divisor); -#endif - return 0; - -} - -void -serial_putc(const char c) -{ - if (c == '\n') - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); - - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); -} - -int -serial_getc(void) -{ - return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); -} - -int -serial_tstc(void) -{ - return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); -} - -void -serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; - -#ifdef CFG_INIT_CHAN1 - NS16550_reinit(COM_PORTS[0], clock_divisor); -#endif -#ifdef CFG_INIT_CHAN2 - NS16550_reinit(COM_PORTS[1], clock_divisor); -#endif -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -void -kgdb_serial_init(void) -{ -} - -void -putDebugChar (int c) -{ - serial_putc (c); -} - -void -putDebugStr (const char *str) -{ - serial_puts (str); -} - -int -getDebugChar (void) -{ - return serial_getc(); -} - -void -kgdb_interruptible (int yes) -{ - return; -} -#endif /* CFG_CMD_KGDB */ diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds deleted file mode 100644 index f8e9e33..0000000 --- a/board/ml2/u-boot.lds +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/ml2/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/ml2/u-boot.lds.debug b/board/ml2/u-boot.lds.debug deleted file mode 100644 index 1608f8c..0000000 --- a/board/ml2/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/modnet50/Makefile b/board/modnet50/Makefile deleted file mode 100644 index ab2c376..0000000 --- a/board/modnet50/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := modnet50.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/modnet50/config.mk b/board/modnet50/config.mk deleted file mode 100644 index 49d4836..0000000 --- a/board/modnet50/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x00f00000 -#CROSS_COMPILE = arm-elf- diff --git a/board/modnet50/flash.c b/board/modnet50/flash.c deleted file mode 100644 index a50639e..0000000 --- a/board/modnet50/flash.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - * (C) Copyright 2002 - * MAZeT GmbH - * Stephan Linz , - * - * The most stuff comes from PPCBoot and Linux. - * - * IMMS gGmbH - * Thomas Elste - * - * Modifications for ModNET50 Board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define SCR (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_SYSTEM_CONTROL)) - -#define ALIGN_ABORT_OFF SCR = SCR & ~NETARM_GEN_SYS_CFG_ALIGN_ABORT -#define ALIGN_ABORT_ON SCR = SCR | NETARM_GEN_SYS_CFG_ALIGN_ABORT - -#define PROG_ADDR (0x555*2) -#define SETUP_ADDR (0x555*2) -#define ID_ADDR (0x555*2) -#define UNLOCK_ADDR1 (0x555*2) -#define UNLOCK_ADDR2 (0x2AA*2) - -#define UNLOCK_CMD1 (0xAA) -#define UNLOCK_CMD2 (0x55) -#define ERASE_SUSPEND_CMD (0xB0) -#define ERASE_RESUME_CMD (0x30) -#define RESET_CMD (0xF0) -#define ID_CMD (0x90) -#define SECERASE_CMD (0x30) -#define CHIPERASE_CMD (0x10) -#define PROG_CMD (0xa0) -#define SETUP_CMD (0x80) - -#define DQ2 (0x04) -#define DQ3 (DQ2*2) -#define DQ5 (DQ3*4) -#define DQ6 (DQ5*2) - -#define WRITE_UNLOCK(addr) { \ - *(volatile __u16*)(addr + UNLOCK_ADDR1) = (__u16)UNLOCK_CMD1; \ - *(volatile __u16*)(addr + UNLOCK_ADDR2) = (__u16)UNLOCK_CMD2; \ -} - -#define CONFIG_AM29_RESERVED (0) -#define K (1024) -#define MB (4) - -#define CELL_SIZE (64*K) -#define DEVICE_SIZE (MB*K*K) -#define CELLS_PER_DEVICE (DEVICE_SIZE/CELL_SIZE) -#define RESERVED_CELLS (CONFIG_AM29_RESERVED*K)/CELL_SIZE -#define MAX_FLASH_DEVICES (1) -#define AVAIL_SIZE (DEVICE_SIZE*MAX_FLASH_DEVICES - RESERVED_CELLS*CELL_SIZE) - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; -static __u16 toggling_bits; - - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (ulong baseaddr, flash_info_t * info) -{ - short i; - __u16 flashtest; - - /* Write auto select command sequence and test FLASH answer */ - WRITE_UNLOCK (baseaddr); - *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) ID_CMD; - flashtest /* manufacturer ID */ = *(volatile __u16 *) (baseaddr); - *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) RESET_CMD; - - switch ((__u32) ((flashtest << 16) + flashtest)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD & FLASH_VENDMASK; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ & FLASH_VENDMASK; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - /* Write auto select command sequence and test FLASH answer */ - WRITE_UNLOCK (baseaddr); - *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) ID_CMD; - flashtest /* device ID */ = *(volatile __u16 *) (baseaddr + 2); - *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) RESET_CMD; - - /* toggling_bits = (flashtest == TOSHIBA)?(DQ6):(DQ2|DQ6); */ - toggling_bits = (DQ2 | DQ6); - - switch ((__u32) ((flashtest << 16) + flashtest)) { - case AMD_ID_LV160B: - info->flash_id += - (FLASH_AM160LV | FLASH_AM160B) & FLASH_TYPEMASK; - info->sector_count = CFG_MAX_FLASH_SECT; - info->size = CFG_FLASH_SIZE; - /* 1*16K Boot Block - 2*8K Parameter Block - 1*32K Small Main Block */ - info->start[0] = baseaddr; - info->start[1] = baseaddr + 0x4000; - info->start[2] = baseaddr + 0x6000; - info->start[3] = baseaddr + 0x8000; - for (i = 1; i < info->sector_count; i++) - info->start[3 + i] = baseaddr + i * CFG_MAIN_SECT_SIZE; - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* no or unknown flash */ - } - - for (i = 0; i < info->sector_count; i++) { - /* Write auto select command sequence and test FLASH answer */ - WRITE_UNLOCK (info->start[i]); - *(volatile __u16 *) (info->start[i] + ID_ADDR) = (__u16) ID_CMD; - flashtest /* protected verify */ = *(volatile __u16 *) (info->start[i] + 4); - *(volatile __u16 *) (info->start[i] + ID_ADDR) = (__u16) RESET_CMD; - if (flashtest & 0x0001) { - info->protect[i] = 1; /* D0 = 1 if protected */ - } else { - info->protect[i] = 0; - } - } - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -ulong flash_init (void) -{ - ulong size = 0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - size = flash_get_size (CFG_FLASH_BASE, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN || size == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size >> 20); - } - - /* - * protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("Fujitsu "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL323B: - printf ("29DL323B (32 M, bottom sector)\n"); - break; - case (FLASH_AM160LV | FLASH_AM160B): - printf ("29LV160BE (1M x 16, bottom sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 4) == 0) - printf ("\n "); - printf (" S%02d @ 0x%08lX%s", i, - info->start[i], info->protect[i] ? " !" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ -int flash_check_protection (flash_info_t * info, int s_first, int s_last) -{ - int sect, prot = 0; - - for (sect = s_first; sect <= s_last; sect++) - if (info->protect[sect]) - prot++; - if (prot) - printf ("- can't erase %d protected sectors\n", prot); - return prot; -} - -/*----------------------------------------------------------------------- - */ -int flash_check_erase_amd (ulong start) -{ - __u16 v1, v2; - - v1 = *(volatile __u16 *) (start); - v2 = *(volatile __u16 *) (start); - - if (((v1 ^ v2) & toggling_bits) == toggling_bits) { - if (((v1 | v2) & DQ5) == DQ5) { - printf ("[DQ5] "); - /* OOPS: exceeded timing limits */ - - v1 = *(volatile __u16 *) (start); - v2 = *(volatile __u16 *) (start); - - if (((v1 ^ v2) & toggling_bits) == toggling_bits) { - - printf ("[%s] ", - ((toggling_bits & (DQ2 | DQ6)) == - (DQ2 | DQ6)) ? "DQ2,DQ6" : "DQ6"); - - /* OOPS: there is an erasure in progress, - * try to reset chip */ - *(volatile __u16 *) (start) = - (__u16) RESET_CMD; - - return 1; /* still busy */ - } - } - return 1; /* still busy */ - } - return 0; /* be free */ -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, sect, setup_offset = 0; - int rc = ERR_OK; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - return ERR_UNKNOWN_FLASH_TYPE; - } - - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return ERR_INVAL; - } - - if (flash_check_protection (info, s_first, s_last)) - return ERR_PROTECTED; - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_FUJ: - case FLASH_MAN_AMD: - switch (info->flash_id & FLASH_TYPEMASK) { - case (FLASH_AM160LV | FLASH_AM160B): - setup_offset = UNLOCK_ADDR1; /* just the adress for setup_cmd differs */ - case FLASH_AMDL323B: - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); - sect++) { - printf ("Erasing sector %2d ... ", sect); - - if (info->protect[sect] == 0) { - /* not protected */ - /* Write sector erase command sequence */ - WRITE_UNLOCK (info->start[0]); - *(volatile __u16 *) (info->start[0] + - setup_offset) = - (__u16) SETUP_CMD; - WRITE_UNLOCK (info->start[0]); - *(volatile __u16 *) (info-> - start[sect]) = - (__u16) SECERASE_CMD; - - /* wait some time */ - reset_timer_masked (); - while (get_timer_masked () < 1000) { - } - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - while (flash_check_erase_amd (info->start[sect])) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - printf ("timeout!\n"); - /* OOPS: reach timeout, - * try to reset chip - */ - *(volatile __u16 *) (info-> start[sect]) = (__u16) RESET_CMD; - rc = ERR_TIMOUT; - goto outahere_323B; - } - } - printf ("ok.\n"); - } else { - printf ("protected!\n"); - } - } - if (ctrlc ()) - printf ("User Interrupt!\n"); -outahere_323B: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - if (flag) - enable_interrupts (); - return rc; - default: - printf ("- unknown chip type\n"); - return ERR_UNKNOWN_FLASH_TYPE; - } - break; - default: - printf ("- unknown vendor "); - return ERR_UNKNOWN_FLASH_VENDOR; - } -} - -/*----------------------------------------------------------------------- - */ -int flash_check_write_amd (ulong dest) -{ - __u16 v1, v2; - - v1 = *(volatile __u16 *) (dest); - v2 = *(volatile __u16 *) (dest); - - /* DQ6 toggles during write */ - if (((v1 ^ v2) & DQ6) == DQ6) { - if (((v1 | v2) & DQ5) == DQ5) { - printf ("[DQ5] @ %08lX\n", dest); - - /* OOPS: exceeded timing limits, - * try to reset chip */ - *(volatile __u16 *) (dest) = (__u16) RESET_CMD; - return 0; /* be free */ - } - return 1; /* still busy */ - } - - return 0; /* be free */ -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ -static int write_word (flash_info_t * info, ulong dest, ushort data) -{ - int rc = ERR_OK; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*(__u16 *) (dest) & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* Write program command sequence */ - WRITE_UNLOCK (info->start[0]); - - /* Flash dependend program seqence */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_FUJ: - case FLASH_MAN_AMD: - switch (info->flash_id & FLASH_TYPEMASK) { - case (FLASH_AM160LV | FLASH_AM160B): - *(volatile __u16 *) (info->start[0] + UNLOCK_ADDR1) = - (__u16) PROG_CMD; - *(volatile __u16 *) (dest) = (__u16) data; - break; - case FLASH_AMDL323B: - *(volatile __u16 *) (dest) = (__u16) PROG_CMD; - *(volatile __u16 *) (dest) = (__u16) data; - break; - } - } - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - while (flash_check_write_amd (dest)) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - printf ("timeout! @ %08lX\n", dest); - /* OOPS: reach timeout, - * try to reset chip */ - *(volatile __u16 *) (dest) = (__u16) RESET_CMD; - - rc = ERR_TIMOUT; - goto outahere_323B; - } - } - - /* Check if Flash was (accurately) written */ - if (*(__u16 *) (dest) != data) - rc = ERR_PROG_ERROR; - -outahere_323B: - if (flag) - enable_interrupts (); - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((ushort *) src); - if ((rc = write_word (info, wp, data)) != 0) - return (rc); - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) - return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word (info, wp, data); -} diff --git a/board/modnet50/lowlevel_init.S b/board/modnet50/lowlevel_init.S deleted file mode 100644 index c98c155..0000000 --- a/board/modnet50/lowlevel_init.S +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Memory Setup stuff - taken from Linux - * - * Copyright (c) 2002 Stephan Linz , - * (c) 2004 IMMS gGmbH , Thomas Elste - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include - - -/* some parameters for the board */ -#define FLASH_90ns_WAIT_STATES ((NETARM_PLL_COUNT_VAL + 2) / 3) -#define FLASH_70ns_WAIT_STATES 4 - -#define NETARM_MMAP_CS0_BASE (PHYS_FLASH_1) -#if 1 -#define NETARM_MMAP_CS0_MASK (~(PHYS_FLASH_1_SIZE - 1)) -#else -#define NETARM_MMAP_CS0_MASK (~(1000000 - 1)) -#endif -#define NETARM_MMAP_CS1_BASE (PHYS_SDRAM_1) -#define NETARM_MMAP_CS1_MASK (~(PHYS_SDRAM_1_SIZE - 1)) -#define NETARM_MMAP_CS2_BASE (PHYS_SDRAM_2) -#define NETARM_MMAP_CS2_MASK (~(PHYS_SDRAM_2_SIZE - 1)) -#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE) -#define NETARM_MMAP_CS3_BASE (PHYS_NVRAM_1) -#define NETARM_MMAP_CS3_MASK (~(PHYS_NVRAM_SIZE - 1)) -#endif -#define NETARM_MMAP_CS4_BASE (PHYS_EXT_1) -#define NETARM_MMAP_CS4_MASK (~(PHYS_EXT_SIZE - 1)) - -/* setting up the memory */ -.globl lowlevel_init -lowlevel_init: - -#if defined(CONFIG_MODNET50) - ldr pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - TEXT_BASE) - -_jump_to_high: - /* - * MEM Config Reg - * --------------------------------------------------- - */ - ldr r0, =NETARM_MEM_MODULE_BASE - ldr r1, =( NETARM_MEM_REFR_PERIOD_USEC(16) | \ - NETARM_MEM_CFG_REFRESH_EN | \ - NETARM_MEM_CFG_REFR_CYCLE_5CLKS ) - str r1, [r0, #+NETARM_MEM_MODULE_CONFIG] - - -memsetup_cs0: - /* - * Base Addr / Option Reg 0 (Flash) - * --------------------------------------------------- - */ - ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS0_BASE) | \ - NETARM_MEM_BAR_DRAM_FP | \ - NETARM_MEM_BAR_DRAM_MUX_INT | \ - NETARM_MEM_BAR_DRAM_MUX_BAL | \ - NETARM_MEM_BAR_VALID ) - str r1, [r0, #+NETARM_MEM_CS0_BASE_ADDR] - - /* trust that the bus size for flash was strapped correctly */ - /* this saves the bus width in r2 and then ORs it back in */ - /* it's pretty safe assumption, otherwise it wouldn't boot */ - ldr r2, [r0, #+NETARM_MEM_CS0_OPTIONS] - and r2, r2, #NETARM_MEM_OPT_BUS_SIZE_MASK - -/* just a test: assume 32 bit flash mem */ -/* mov r2, #NETARM_MEM_OPT_32BIT */ - - ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS0_MASK) | \ - NETARM_MEM_OPT_WAIT_STATES(FLASH_70ns_WAIT_STATES) | \ - NETARM_MEM_OPT_BCYC_4 | \ - NETARM_MEM_OPT_BSIZE_16 | \ - NETARM_MEM_OPT_16BIT | \ - NETARM_MEM_OPT_READ_ASYNC | \ - NETARM_MEM_OPT_WRITE_ASYNC ) - - orr r1, r1, r2 - str r1, [r0, #+NETARM_MEM_CS0_OPTIONS] - - -memsetup_cs1: - /* - * Base Addr / Option Reg 1 (DRAM #1) - * --------------------------------------------------- - */ -#ifdef CONFIG_NETARM_NET40_REV2 - /* we have to config SDRAM in burst mode */ - ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \ - NETARM_MEM_OPT_BCYC_2 | \ - NETARM_MEM_OPT_BSIZE_16 | \ - NETARM_MEM_OPT_WAIT_STATES(0) | \ - NETARM_MEM_OPT_32BIT | \ - NETARM_MEM_OPT_READ_ASYNC | \ - NETARM_MEM_OPT_WRITE_ASYNC ) - str r1, [r0, #+NETARM_MEM_CS1_OPTIONS] - - ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \ - NETARM_MEM_BAR_DRAM_SYNC | \ - NETARM_MEM_BAR_DRAM_MUX_INT | \ - NETARM_MEM_BAR_DRAM_MUX_UNBAL | \ - NETARM_MEM_BAR_DRAM_SEL | \ - NETARM_MEM_BAR_BURST_EN | \ - NETARM_MEM_BAR_VALID ) - str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR] -#else - /* we have to config FPDRAM in burst mode with smaller burst access size */ - ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \ - NETARM_MEM_OPT_BCYC_2 | \ - NETARM_MEM_OPT_BSIZE_16 | \ - NETARM_MEM_OPT_WAIT_STATES(0) | \ - NETARM_MEM_OPT_32BIT | \ - NETARM_MEM_OPT_READ_ASYNC | \ - NETARM_MEM_OPT_WRITE_ASYNC ) - str r1, [r0, #+NETARM_MEM_CS1_OPTIONS] - - ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \ - NETARM_MEM_BAR_DRAM_SYNC | \ - NETARM_MEM_BAR_DRAM_MUX_INT | \ - NETARM_MEM_BAR_DRAM_MUX_UNBAL | \ - NETARM_MEM_BAR_DRAM_SEL | \ - NETARM_MEM_BAR_BURST_EN | \ - NETARM_MEM_BAR_VALID ) - str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR] - -#endif /* CONFIG_NETARM_NET40_REV2 */ - - -memsetup_cs3: - /* - * Base Addr / Option Reg 3 (EEPROM, NVRAM) - * --------------------------------------------------- - */ -#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE) - ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS3_MASK) | \ - NETARM_MEM_OPT_BCYC_3 | \ - NETARM_MEM_OPT_BSIZE_2 | \ - NETARM_MEM_OPT_WAIT_STATES(10) | \ - NETARM_MEM_OPT_8BIT | \ - NETARM_MEM_OPT_READ_ASYNC | \ - NETARM_MEM_OPT_WRITE_ASYNC ) - str r1, [r0, #+NETARM_MEM_CS3_OPTIONS] - - ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS3_BASE) | \ - NETARM_MEM_BAR_DRAM_FP | \ - NETARM_MEM_BAR_DRAM_MUX_INT | \ - NETARM_MEM_BAR_DRAM_MUX_BAL | \ - NETARM_MEM_BAR_VALID ) - str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR] -#else - /* we don't need EEPROM --> no config */ - ldr r1, =( 0 ) - str r1, [r0, #+NETARM_MEM_CS3_OPTIONS] - - ldr r1, =( 0 ) - str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR] -#endif - - -#else -/* -#error "missing CONFIG_MODNET50 (see your config.h)" -*/ -#endif /* CONFIG_MODNET50 */ - - -lowlevel_init_end: - /* - * manipulate address in lr and ip to match new - * address space - */ - ldr r3, =(NETARM_MMAP_CS0_BASE) - mov r0, lr - add r0, r3, r0 - mov lr, r0 - mov r0, ip - add r0, r3, r0 - mov ip, r0 - - /* everything is fine now */ - mov pc, lr diff --git a/board/modnet50/modnet50.c b/board/modnet50/modnet50.c deleted file mode 100644 index 448c623..0000000 --- a/board/modnet50/modnet50.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - /* address for the kernel command line */ - gd->bd->bi_boot_params = 0x800; - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - if (CONFIG_NR_DRAM_BANKS == 2) { - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - } - return (0); -} diff --git a/board/modnet50/u-boot.lds b/board/modnet50/u-boot.lds deleted file mode 100644 index 5b70a40..0000000 --- a/board/modnet50/u-boot.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm720t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/board/mousse/Makefile b/board/mousse/Makefile deleted file mode 100644 index ddc5546..0000000 --- a/board/mousse/Makefile +++ /dev/null @@ -1,41 +0,0 @@ - -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o m48t59y.o pci.o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/mousse/README b/board/mousse/README deleted file mode 100644 index d5dda7a..0000000 --- a/board/mousse/README +++ /dev/null @@ -1,346 +0,0 @@ - -U-Boot for MOUSSE/MPC8240 (KAHLUA) ----------------------------------- -James Dougherty (jfd@broadcom.com), 09/10/01 - -The Broadcom/Vooha Mousse board is a 3U Compact PCI system board -which uses the MPC8240, a 64MB SDRAM SIMM, and has onboard -DEC 21143, NS16550 UART, an SGS M48T59Y TOD, and 4MB FLASH. -See also: http://www.vooha.com/ - -* NVRAM setenv/printenv/savenv supported. -* Date Command -* Serial Console support -* Network support -* FLASH of kernel images is supported. -* FLASH of U-Boot to onboard and PLCC boot region. -* Kernel command line options from NVRAM is supported. -* IP PNP options supported. - -U-Boot Loading... - - -U-Boot 1.0.5 (Sep 10 2001 - 00:22:25) - -CPU: MPC8240 Revision 1.1 at 198 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B) -Built: Sep 10 2001 at 01:01:50 -MPLD: Revision 127 -Local Bus: 33 MHz -RTC: M48T589 TOD/NVRAM (8176) bytes - Current date/time: 9/10/2001 0:18:52 -DRAM: 64 MB -FLASH: 1.960 MB -PCI: scanning bus0 ... - bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE - 00 00 00 1057 0003 060000 11 00000008 00000000 01 00 - 00 0d 00 1011 0019 020000 41 80000001 80000000 01 01 - 00 0e 00 105a 4d38 018000 01 a0000001 a0001001 01 03 -In: serial -Out: serial -Err: serial - -Hit any key to stop autoboot: 0 -=> - -I. Root FileSystem/IP Configuration - -bootcmd=tftp 100000 vmlinux.img;bootm -bootdelay=3 -baudrate=9600 -ipaddr= -netmask= -hostname= -serverip= -ethaddr=00:00:10:20:30:44 -nfsroot=:/boot/root-fs -gateway= -root=/dev/nfs -stdin=serial -stdout=serial -stderr=serial - -NVRAM environment variables. - -use the command: - -setenv - -type "saveenv" to write to NVRAM. - - -II. To boot from a hard drive: - -setenv root /dev/hda1 - - -III. IP options which configure the network: - -ipaddr= -netmask= -hostname=mousse -ethaddr=00:00:10:20:30:44 -gateway= - - -IV. IP Options which configure NFS Root/Boot Support - -root=/dev/nfs -serverip= -nfsroot=:/boot/root-fs - -V. U-Boot Image Support - -The U-Boot boot loader assumes that after you build -your kernel (vmlinux), you will create a U-Boot image -using the following commands or script: - -#!/bin/csh -/bin/touch vmlinux.img -/bin/rm vmlinux.img -set path=($TOOLBASE/bin $path) -set path=($U_BOOT/tools $path) -powerpc-linux-objcopy -S -O binary vmlinux vmlinux.bin -gzip -vf vmlinux.bin -mkimage -A ppc -O linux -T kernel -C gzip -a 0 -e 0 -n vmlinux.bin.gz -d vmlinux.bin.gz vmlinux.img -ls -l vmlinux.img - - -VI. ONBOARD FLASH Support - -FLASH support is provided for the onboard FLASH chip Bootrom area. -U-Boot is loaded into either the ROM boot region of the FLASH chip, -after first being boot-strapped from a pre-progammed AMD29F040 PLCC -bootrom. The PLCC needs to be programmed with a ROM burner using -AMD 29F040 ROM parts and the u-boot.bin or u-boot.hex (S-Record) -images. - -The PLCC overlays this same region of flash as the onboard FLASH, -the jumper J100 is a chip-select for which flash chip you want to -progam. When jumper J100 is connected to pins 2-3, you boot from -PLCC FLASH. - -To bringup a system, simply flash a flash an AMD29F040 PLCC -bootrom, and put this in the PLCC socket. Move jumper J100 to -pins 2-3 and boot from the PLCC. - - -Now, while the system is running, move Jumper J100 to -pins 1-2 and follow the procedure below to FLASH a bootrom -(u-boot.bin) image into the onboard bootrom region (AMD29LV160DB): - -tftp 100000 u-boot.bin -protect off FFF00000 FFF7FFFF -erase FFF00000 FFF7FFFF -cp.b 100000 FFF00000 \${filesize}\ - - -Here is an example: - -=>tftp 100000 u-boot.bin -eth_halt -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -Filename 'u-boot.bin'. -Load address: 0x100000 -Loading: ######################### -done -Bytes transferred = 123220 (1e154 hex) -eth_halt -=>protect off FFF00000 FFF7FFFF -Un-Protected 8 sectors -=>erase FFF00000 FFF7FFFF -Erase Flash from 0xfff00000 to 0xfff7ffff -Erase FLASH[PLCC_BOOT] -8 sectors:........ done -Erased 8 sectors -=>cp.b 100000 FFF00000 1e154 -Copy to Flash... FLASH[PLCC_BOOT]:..done -=> - - -B. FLASH RAMDISK REGION - -FLASH support is provided for an Onboard 512K RAMDISK region. - -TThe following commands will FLASH a bootrom (u-boot.bin) image -into the onboard FLASH region (AMD29LV160DB 2MB FLASH): - -tftp 100000 u-boot.bin -protect off FFF80000 FFFFFFFF -erase FFF80000 FFFFFFFF -cp.b 100000 FFF80000 \${filesize}\ - - -C. FLASH KERNEL REGION (960KB) - -FLASH support is provided for the 960KB onboard FLASH1 segment. -This allows flashing of kernel images which U-Boot can load -and run (standalone) from the onboard FLASH chip. It also assumes - -The following commands will FLASH a kernel image to 0xffe10000 - -tftp 100000 vmlinux.img -protect off FFE10000 FFEFFFFF -erase FFE10000 FFEFFFFF -cp.b 100000 FFE10000 \${filesize}\ -reset - -Here is an example: - - -=>tftp 100000 vmlinux.img -eth_halt -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -TFTP from server 209.128.93.133; our IP address is 209.128.93.138 -Filename 'vmlinux.img'. -Load address: 0x100000 -Loading: ##################################################################################################################################################### -done -Bytes transferred = 760231 (b99a7 hex) -eth_halt -=>protect off FFE10000 FFEFFFFF -Un-Protected 15 sectors -=>erase FFE10000 FFEFFFFF -Erase Flash from 0xffe10000 to 0xffefffff -Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done -Erased 15 sectors -=>cp.b 100000 FFE10000 b99a7 -Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done -=> - - -When finished, use the command: - -bootm ffe10000 - -to start the kernel. - -Finally, to make this the default boot command, use -the following commands: - -setenv bootcmd bootm ffe10000 -savenv - -to make it automatically boot the kernel from FLASH. - - -To go back to development mode (NFS boot) - -setenv bootcmd tftp 100000 vmlinux.img\;bootm -savenv - - -=>tftp 100000 vmlinux.img -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -Filename 'vmlinux.img'. -Load address: 0x100000 -Loading: #################################################################################################################################################### -done -Bytes transferred = 752717 (b7c4d hex) -eth_halt -=>protect off FFE10000 FFEFFFFF -Un-Protected 15 sectors -=>erase FFE10000 FFEFFFFF -Erase Flash from 0xffe10000 to 0xffefffff -Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done -Erased 15 sectors -=>cp.b 100000 FFE10000 b7c4d -Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done -=>bootm ffe10000 -## Booting image at ffe10000 ... - Image Name: vmlinux.bin.gz - Image Type: PowerPC Linux Kernel Image (gzip compressed) - Data Size: 752653 Bytes = 735 kB = 0 MB - Load Address: 00000000 - Entry Point: 00000000 - Verifying Checksum ... OK - Uncompressing Kernel Image ... OK -Total memory = 64MB; using 0kB for hash table (at 00000000) -Linux version 2.4.2_hhl20 (jfd@atlantis) (gcc version 2.95.2 19991024 (release)) #597 Wed Sep 5 23:23:23 PDT 2001 -cpu0: MPC8240/KAHLUA : MOUSSE Platform : 64MB RAM: MPLD Rev. 7f -Sandpoint port (C) 2000, 2001 MontaVista Software, Inc. (source@mvista.com) -IP PNP: 802.3 Ethernet Address=<0:0:10:20:30:44> -NOTICE: mounting root file system via NFS -On node 0 totalpages: 16384 -zone(0): 16384 pages. -zone(1): 0 pages. -zone(2): 0 pages. -time_init: decrementer frequency = 16.665914 MHz -time_init: MPC8240 PCI Bus frequency = 33.331828 MHz -Calibrating delay loop... 133.12 BogoMIPS -Memory: 62436k available (1336k kernel code, 500k data, 88k init, 0k highmem) -Dentry-cache hash table entries: 8192 (order: 4, 65536 bytes) -Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes) -Page-cache hash table entries: 16384 (order: 4, 65536 bytes) -Inode-cache hash table entries: 4096 (order: 3, 32768 bytes) -POSIX conformance testing by UNIFIX -PCI: Probing PCI hardware -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Initializing RT netlink socket -Starting kswapd v1.8 -pty: 256 Unix98 ptys configured -block: queued sectors max/low 41394kB/13798kB, 128 slots per queue -Uniform Multi-Platform E-IDE driver Revision: 6.31 -ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx -PDC20262: IDE controller on PCI bus 00 dev 70 -PDC20262: chipset revision 1 -PDC20262: not 100% native mode: will probe irqs later -PDC20262: ROM enabled at 0x000d0000 -PDC20262: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode. -PDC20262: FORCING BURST BIT 0x00 -> 0x01 ACTIVE -PDC20262: irq=3 dev->irq=3 - ide0: BM-DMA at 0xbfff00-0xbfff07, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0xbfff08-0xbfff0f, BIOS settings: hdc:pio, hdd:pio -hda: WDC WD300AB-00BVA0, ATA DISK drive -hdc: SONY CD-RW CRX160E, ATAPI CD/DVD-ROM drive -ide0 at 0xbfff78-0xbfff7f,0xbfff76 on irq 3 -ide1 at 0xbfff68-0xbfff6f,0xbfff66 on irq 3 -hda: 58633344 sectors (30020 MB) w/2048KiB Cache, CHS=58168/16/63, UDMA(66) -hdc: ATAPI 32X CD-ROM CD-R/RW drive, 4096kB Cache -Uniform CD-ROM driver Revision: 3.12 -Partition check: - /dev/ide/host0/bus0/target0/lun0: p1 p2 -hd: unable to get major 3 for hard disk -udf: registering filesystem -loop: loaded (max 8 devices) -Serial driver version 5.02 (2000-08-09) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled -ttyS00 at 0xffe08080 (irq = 4) is a ST16650 -Linux Tulip driver version 0.9.13a (January 20, 2001) -eth0: Digital DS21143 Tulip rev 65 at 0xbfff80, EEPROM not present, 00:00:10:20:30:44, IRQ 1. -eth0: MII transceiver #0 config 3000 status 7829 advertising 01e1. -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP -IP: routing cache hash table of 512 buckets, 4Kbytes -TCP: Hash tables configured (established 4096 bind 4096) -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -devfs: v0.102 (20000622) Richard Gooch (rgooch@atnf.csiro.au) -devfs: boot_options: 0x0 -VFS: Mounted root (nfs filesystem). -Mounted devfs on /dev -Freeing unused kernel memory: 88k init 4k openfirmware -eth0: Setting full-duplex based on MII#0 link partner capability of 45e1. -INIT: version 2.78 booting -INIT: Entering runlevel: 2 - - -Welcome to Linux/PPC -MPC8240/MOUSSE - - -mousse login: root -Password: -PAM_unix[13]: (login) session opened for user root by LOGIN(uid=0) -Last login: Thu Sep 6 00:16:51 2001 on console - - -Welcome to Linux/PPC -MPC8240/MOUSSE - - -mousse# diff --git a/board/mousse/config.mk b/board/mousse/config.mk deleted file mode 100644 index 64cffa4..0000000 --- a/board/mousse/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MOUSSE boards -# -TEXT_BASE = 0xFFF00000 -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/mousse/flash.c b/board/mousse/flash.c deleted file mode 100644 index 2c32b8f..0000000 --- a/board/mousse/flash.c +++ /dev/null @@ -1,939 +0,0 @@ -/* - * MOUSSE/MPC8240 Board definitions. - * Flash Routines for MOUSSE onboard AMD29LV106DB devices - * - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "mousse.h" -#include "flash.h" - -int flashLibDebug = 0; -int flashLibInited = 0; - -#define OK 0 -#define ERROR -1 -#define STATUS int -#define PRINTF if (flashLibDebug) printf -#if 0 -#define PRIVATE static -#else -#define PRIVATE -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -#define SLEEP_DELAY 166 -#define FLASH_SECTOR_SIZE (64*1024) -/*********************************************************************** - * - * Virtual Flash Devices on Mousse board - * - * These must be kept in sync with the definitions in flashLib.h. - * - ***********************************************************************/ - -PRIVATE flash_dev_t flashDev[] = { - /* Bank 0 sector SA0 (16 kB) */ - { "SA0",FLASH0_BANK, FLASH0_SEG0_START, 1, 14, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA1 (8 kB) */ - { "SA1", FLASH0_BANK, FLASH0_SEG0_START + 0x4000, 1, 13, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA2 (8 kB) */ - { "SA2", FLASH0_BANK, FLASH0_SEG0_START + 0x6000, 1, 13, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA3 is occluded by Mousse I/O devices */ - /* Bank 0 sectors SA4-SA18, after Mousse devices up to PLCC (960 kB) */ - { "KERNEL", FLASH0_BANK, FLASH0_SEG1_START, 15, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sectors SA19-SA26, jumper can occlude this by PLCC (512 kB) */ - /* This is where the Kahlua boot vector and boot ROM code resides. */ - { "BOOT",FLASH0_BANK, FLASH0_SEG2_START, 8, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sectors SA27-SA34 (512 kB) */ - { "RAMDISK",FLASH0_BANK, FLASH0_SEG3_START, 8, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, -}; - -int flashDevCount = (sizeof (flashDev) / sizeof (flashDev[0])); - -#define DEV(no) (&flashDev[no]) -#define DEV_NO(dev) ((dev) - flashDev) - -/*********************************************************************** - * - * Private Flash Routines - * - ***********************************************************************/ - -/* - * The convention is: - * - * "addr" is always the PROM raw address, which is the address of an - * 8-bit quantity for flash 0 and 16-bit quantity for flash 1. - * - * "pos" is always a logical byte position from the PROM beginning. - */ - -#define FLASH0_ADDR(dev, addr) \ - ((unsigned char *) ((dev)->base + (addr))) - -#define FLASH0_WRITE(dev, addr, value) \ - (*FLASH0_ADDR(dev, addr) = (value)) - -#define FLASH0_READ(dev, addr) \ - (*FLASH0_ADDR(dev, addr)) - -PRIVATE int flashCheck (flash_dev_t * dev) -{ - if (!flashLibInited) { - printf ("flashCheck: flashLib not initialized\n"); - return ERROR; - } - - if (dev < &flashDev[0] || dev >= &flashDev[flashDevCount]) { - printf ("flashCheck: Bad dev parameter\n"); - return ERROR; - } - - if (!dev->found) { - printf ("flashCheck: Device %d not available\n", DEV_NO (dev)); - return ERROR; - } - - return OK; -} - -PRIVATE void flashReset (flash_dev_t * dev) -{ - PRINTF ("flashReset: dev=%d\n", DEV_NO (dev)); - - if (dev->bank == FLASH0_BANK) { - FLASH0_WRITE (dev, 0x555, 0xaa); - FLASH0_WRITE (dev, 0xaaa, 0x55); - FLASH0_WRITE (dev, 0x555, 0xf0); - } - - udelay (SLEEP_DELAY); - - PRINTF ("flashReset: done\n"); -} - -PRIVATE int flashProbe (flash_dev_t * dev) -{ - int rv, deviceID, vendorID; - - PRINTF ("flashProbe: dev=%d\n", DEV_NO (dev)); - - if (dev->bank != FLASH0_BANK) { - rv = ERROR; - goto DONE; - } - - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0x90); - - udelay (SLEEP_DELAY); - - vendorID = FLASH0_READ (dev, 0); - deviceID = FLASH0_READ (dev, 2); - - FLASH0_WRITE (dev, 0, 0xf0); - - PRINTF ("flashProbe: vendor=0x%x device=0x%x\n", vendorID, deviceID); - - if (vendorID == dev->vendorID && deviceID == dev->deviceID) - rv = OK; - else - rv = ERROR; - - DONE: - PRINTF ("flashProbe: rv=%d\n", rv); - - return rv; -} - -PRIVATE int flashWait (flash_dev_t * dev, int addr, int expect, int erase) -{ - int rv = ERROR; - int i, data; - int polls; - -#if 0 - PRINTF ("flashWait: dev=%d addr=0x%x expect=0x%x erase=%d\n", - DEV_NO (dev), addr, expect, erase); -#endif - - if (dev->bank != FLASH0_BANK) { - rv = ERROR; - goto done; - } - - if (erase) - polls = FLASH_ERASE_SECTOR_TIMEOUT; /* Ticks */ - else - polls = FLASH_PROGRAM_POLLS; /* Loops */ - - for (i = 0; i < polls; i++) { - if (erase) - udelay (SLEEP_DELAY); - - data = FLASH0_READ (dev, addr); - - if (((data ^ expect) & 0x80) == 0) { - rv = OK; - goto done; - } - - if (data & 0x20) { - /* - * If the 0x20 bit has come on, it could actually be because - * the operation succeeded, so check the done bit again. - */ - - data = FLASH0_READ (dev, addr); - - if (((data ^ expect) & 0x80) == 0) { - rv = OK; - goto done; - } - - printf ("flashWait: Program error (dev: %d, addr: 0x%x)\n", - DEV_NO (dev), addr); - - flashReset (dev); - rv = ERROR; - goto done; - } - } - - printf ("flashWait: Timeout %s (dev: %d, addr: 0x%x)\n", - erase ? "erasing sector" : "programming byte", - DEV_NO (dev), addr); - - done: - -#if 0 - PRINTF ("flashWait: rv=%d\n", rv); -#endif - - return rv; -} - -/*********************************************************************** - * - * Public Flash Routines - * - ***********************************************************************/ - -STATUS flashLibInit (void) -{ - int i; - - PRINTF ("flashLibInit: devices=%d\n", flashDevCount); - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - /* - * For bank 1, probe both without and with byte swappage, - * so that this module works on both old and new Mousse boards. - */ - - flashReset (dev); - - if (flashProbe (dev) != ERROR) - dev->found = 1; - - flashReset (dev); - - if (flashProbe (dev) != ERROR) - dev->found = 1; - - dev->swap = 0; - - if (dev->found) { - PRINTF ("\n FLASH %s[%d]: iobase=0x%x - %d sectors %d KB", - flashDev[i].name, i, flashDev[i].base, - flashDev[i].sectors, - (flashDev[i].sectors * FLASH_SECTOR_SIZE) / 1024); - - } - } - - flashLibInited = 1; - - PRINTF ("flashLibInit: done\n"); - - return OK; -} - -STATUS flashEraseSector (flash_dev_t * dev, int sector) -{ - int pos, addr; - - PRINTF ("flashErasesector: dev=%d sector=%d\n", DEV_NO (dev), sector); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (sector < 0 || sector >= dev->sectors) { - printf ("flashEraseSector: Sector out of range (dev: %d, sector: %d)\n", DEV_NO (dev), sector); - return ERROR; - } - - pos = FLASH_SECTOR_POS (dev, sector); - - if (dev->bank != FLASH0_BANK) { - return ERROR; - } - - addr = pos; - - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0x80); - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, addr, 0x30); - - return flashWait (dev, addr, 0xff, 1); -} - -/* - * Note: it takes about as long to flash all sectors together with Chip - * Erase as it does to flash them one at a time (about 30 seconds for 2 - * MB). Also since we want to be able to treat subsets of sectors as if - * they were complete devices, we don't use Chip Erase. - */ - -STATUS flashErase (flash_dev_t * dev) -{ - int sector; - - PRINTF ("flashErase: dev=%d sectors=%d\n", DEV_NO (dev), dev->sectors); - - if (flashCheck (dev) == ERROR) - return ERROR; - - for (sector = 0; sector < dev->sectors; sector++) { - if (flashEraseSector (dev, sector) == ERROR) - return ERROR; - } - return OK; -} - -/* - * Read and write bytes - */ - -STATUS flashRead (flash_dev_t * dev, int pos, char *buf, int len) -{ - int addr, words; - - PRINTF ("flashRead: dev=%d pos=0x%x buf=0x%x len=0x%x\n", - DEV_NO (dev), pos, (int) buf, len); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashRead: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - return ERROR; - } - - if (len == 0) - return OK; - - if (dev->bank == FLASH0_BANK) { - addr = pos; - words = len; - - PRINTF ("flashRead: memcpy(0x%x, 0x%x, 0x%x)\n", - (int) buf, (int) FLASH0_ADDR (dev, pos), len); - - memcpy (buf, FLASH0_ADDR (dev, addr), words); - - } - PRINTF ("flashRead: rv=OK\n"); - - return OK; -} - -STATUS flashWrite (flash_dev_t * dev, int pos, char *buf, int len) -{ - int addr, words; - - PRINTF ("flashWrite: dev=%d pos=0x%x buf=0x%x len=0x%x\n", - DEV_NO (dev), pos, (int) buf, len); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashWrite: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - return ERROR; - } - - if (len == 0) - return OK; - - if (dev->bank == FLASH0_BANK) { - unsigned char tmp; - - addr = pos; - words = len; - - while (words--) { - tmp = *buf; - if (~FLASH0_READ (dev, addr) & tmp) { - printf ("flashWrite: Attempt to program 0 to 1 " - "(dev: %d, addr: 0x%x, data: 0x%x)\n", - DEV_NO (dev), addr, tmp); - return ERROR; - } - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0xa0); - FLASH0_WRITE (dev, addr, tmp); - if (flashWait (dev, addr, tmp, 0) < 0) - return ERROR; - buf++; - addr++; - } - } - - PRINTF ("flashWrite: rv=OK\n"); - - return OK; -} - -/* - * flashWritable returns TRUE if a range contains all F's. - */ - -STATUS flashWritable (flash_dev_t * dev, int pos, int len) -{ - int addr, words; - int rv = ERROR; - - PRINTF ("flashWritable: dev=%d pos=0x%x len=0x%x\n", - DEV_NO (dev), pos, len); - - if (flashCheck (dev) == ERROR) - goto done; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashWritable: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - goto done; - } - - if (len == 0) { - rv = 1; - goto done; - } - - if (dev->bank == FLASH0_BANK) { - addr = pos; - words = len; - - while (words--) { - if (FLASH0_READ (dev, addr) != 0xff) { - rv = 0; - goto done; - } - addr++; - } - } - - rv = 1; - - done: - PRINTF ("flashWrite: rv=%d\n", rv); - return rv; -} - - -/* - * NOTE: the below code cannot run from FLASH!!! - */ -/*********************************************************************** - * - * Flash Diagnostics - * - ***********************************************************************/ - -STATUS flashDiag (flash_dev_t * dev) -{ - unsigned int *buf = 0; - int i, len, sector; - int rv = ERROR; - - if (flashCheck (dev) == ERROR) - return ERROR; - - printf ("flashDiag: Testing device %d, " - "base: 0x%x, %d sectors @ %d kB = %d kB\n", - DEV_NO (dev), dev->base, - dev->sectors, - 1 << (dev->lgSectorSize - 10), - dev->sectors << (dev->lgSectorSize - 10)); - - len = 1 << dev->lgSectorSize; - - printf ("flashDiag: Erasing\n"); - - if (flashErase (dev) == ERROR) { - printf ("flashDiag: Erase failed\n"); - goto done; - } - printf ("%d bytes requested ...\n", len); - buf = malloc (len); - printf ("allocated %d bytes ...\n", len); - if (buf == 0) { - printf ("flashDiag: Out of memory\n"); - goto done; - } - - /* - * Write unique counting pattern to each sector - */ - - for (sector = 0; sector < dev->sectors; sector++) { - printf ("flashDiag: Write sector %d\n", sector); - - for (i = 0; i < len / 4; i++) - buf[i] = sector << 24 | i; - - if (flashWrite (dev, - sector << dev->lgSectorSize, - (char *) buf, len) == ERROR) { - printf ("flashDiag: Write failed (dev: %d, sector: %d)\n", - DEV_NO (dev), sector); - goto done; - } - } - - /* - * Verify - */ - - for (sector = 0; sector < dev->sectors; sector++) { - printf ("flashDiag: Verify sector %d\n", sector); - - if (flashRead (dev, - sector << dev->lgSectorSize, - (char *) buf, len) == ERROR) { - printf ("flashDiag: Read failed (dev: %d, sector: %d)\n", - DEV_NO (dev), sector); - goto done; - } - - for (i = 0; i < len / 4; i++) { - if (buf[i] != (sector << 24 | i)) { - printf ("flashDiag: Verify error " - "(dev: %d, sector: %d, offset: 0x%x)\n", - DEV_NO (dev), sector, i); - printf ("flashDiag: Expected 0x%08x, got 0x%08x\n", - sector << 24 | i, buf[i]); - - goto done; - } - } - } - - printf ("flashDiag: Erasing\n"); - - if (flashErase (dev) == ERROR) { - printf ("flashDiag: Final erase failed\n"); - goto done; - } - - rv = OK; - - done: - if (buf) - free (buf); - - if (rv == OK) - printf ("flashDiag: Device %d passed\n", DEV_NO (dev)); - else - printf ("flashDiag: Device %d failed\n", DEV_NO (dev)); - - return rv; -} - -STATUS flashDiagAll (void) -{ - int i; - int rv = OK; - - PRINTF ("flashDiagAll: devices=%d\n", flashDevCount); - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found && flashDiag (dev) == ERROR) - rv = ERROR; - } - - if (rv == OK) - printf ("flashDiagAll: Passed\n"); - else - printf ("flashDiagAll: Failed because of earlier errors\n"); - - return OK; -} - - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - flash_dev_t *dev = NULL; - - flashLibInit (); - - /* - * Provide info for FLASH (up to 960K) of Kernel Image data. - */ - dev = FLASH_DEV_BANK0_LOW; - flash_info[FLASH_BANK_KERNEL].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_KERNEL].sector_count = dev->sectors; - flash_info[FLASH_BANK_KERNEL].size = - flash_info[FLASH_BANK_KERNEL].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_KERNEL].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_KERNEL].size; - - /* - * Provide info for 512K PLCC FLASH ROM (U-Boot) - */ - dev = FLASH_DEV_BANK0_BOOT; - flash_info[FLASH_BANK_BOOT].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_BOOT].sector_count = dev->sectors; - flash_info[FLASH_BANK_BOOT].size = - flash_info[FLASH_BANK_BOOT].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_BOOT].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_BOOT].size; - - - /* - * Provide info for 512K FLASH0 segment (U-Boot) - */ - dev = FLASH_DEV_BANK0_HIGH; - flash_info[FLASH_BANK_AUX].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_AUX].sector_count = dev->sectors; - flash_info[FLASH_BANK_AUX].size = - flash_info[FLASH_BANK_AUX].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_AUX].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_AUX].size; - - - return size; -} - -/* - * Get flash device from U-Boot flash info. - */ -flash_dev_t *getFlashDevFromInfo (flash_info_t * info) -{ - int i; - - if (!info) - return NULL; - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found && (dev->base == info->start[0])) - return dev; - } - printf ("ERROR: notice, no FLASH mapped at address 0x%x\n", - (unsigned int) info->start[0]); - return NULL; -} - -ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - int i; - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found) { - if (dev->base == (unsigned int) addr) { - info->flash_id = (dev->vendorID << 16) | dev->deviceID; - info->sector_count = dev->sectors; - info->size = info->sector_count * FLASH_SECTOR_SIZE; - return dev->sectors * FLASH_SECTOR_SIZE; - } - } - } - return 0; -} - -void flash_print_info (flash_info_t * info) -{ - int i; - unsigned int chip; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - chip = (unsigned int) info->flash_id & 0x000000ff; - - switch (chip) { - - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - - case AMD_ID_LV160B: - case FLASH_AM160LV: - case 0x49: - printf ("AM29LV160B (16 Mbit / 2M x 8bit)\n"); - break; - - default: - printf ("Unknown Chip Type:0x%x\n", chip); - break; - } - - printf (" Size: %ld bytes in %d Sectors\n", - info->size, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[FIRST_SECTOR] + i * FLASH_SECTOR_SIZE, - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - - -/* - * Erase a range of flash sectors. - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - vu_long *addr = (vu_long *) (info->start[0]); - int prot, sect, l_sect; - flash_dev_t *dev = NULL; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Start erase on unprotected sectors */ - dev = getFlashDevFromInfo (info); - if (dev) { - printf ("Erase FLASH[%s] -%d sectors:", dev->name, dev->sectors); - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (dev->base); - /* printf("erase_sector: sector=%d, addr=0x%x\n", - sect, addr); */ - printf ("."); - if (ERROR == flashEraseSector (dev, sect)) { - printf ("ERROR: could not erase sector %d on FLASH[%s]\n", sect, dev->name); - return 1; - } - } - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - - flash_dev_t *dev = getFlashDevFromInfo (info); - int addr = dest - info->start[0]; - - if (!dev) - return 1; - - if (OK != flashWrite (dev, addr, (char *) &data, sizeof (ulong))) { - printf ("ERROR: could not write to addr=0x%x, data=0x%x\n", - (unsigned int) addr, (unsigned) data); - return 1; - } - - if ((addr % FLASH_SECTOR_SIZE) == 0) - printf ("."); - - - PRINTF ("write_word:0x%x, base=0x%x, addr=0x%x, data=0x%x\n", - (unsigned) info->start[0], - (unsigned) dest, - (unsigned) (dest - info->start[0]), (unsigned) data); - - return (0); -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - flash_dev_t *dev = getFlashDevFromInfo (info); - - if (dev) { - printf ("FLASH[%s]:", dev->name); - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); - } - return 1; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/mousse/flash.h b/board/mousse/flash.h deleted file mode 100644 index b7e4619..0000000 --- a/board/mousse/flash.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef FLASH_LIB_H -#define FLASH_LIB_H - -#include - -/* PIO operations max */ -#define FLASH_PROGRAM_POLLS 100000 - -/* 10 Seconds default */ -#define FLASH_ERASE_SECTOR_TIMEOUT (10*1000 /*SEC*/ ) - -/* Flash device info structure */ -typedef struct flash_dev_s { - char name[24]; /* Bank Name */ - int bank; /* Bank 0 or 1 */ - unsigned int base; /* Base address */ - int sectors; /* Sector count */ - int lgSectorSize; /* Log2(usable bytes/sector) */ - int vendorID; /* Expected vendor ID */ - int deviceID; /* Expected device ID */ - int found; /* Set if found by flashLibInit */ - int swap; /* Set for bank 1 if byte swap req'd */ -} flash_dev_t; - -#define FLASH_MAX_POS(dev) \ - ((dev)->sectors << (dev)->lgSectorSize) - -#define FLASH_SECTOR_POS(dev, sector) \ - ((sector) << (dev)->lgSectorSize) - -/* AMD 29F040 */ -#define FLASH0_BANK 0 -#define FLASH0_VENDOR_ID 0x01 -#define FLASH0_DEVICE_ID 0x49 - -/* AMD29LV160DB */ -#define FLASH1_BANK 1 -#define FLASH1_VENDOR_ID 0x0001 -#define FLASH1_DEVICE_ID 0x2249 - -extern flash_dev_t flashDev[]; -extern int flashDevCount; - -/* - * Device pointers - * - * These must be kept in sync with the table in flashLib.c. - */ -#define FLASH_DEV_BANK0_SA0 (&flashDev[0]) -#define FLASH_DEV_BANK0_SA1 (&flashDev[1]) -#define FLASH_DEV_BANK0_SA2 (&flashDev[2]) -#define FLASH_DEV_BANK0_LOW (&flashDev[3]) /* 960K */ -#define FLASH_DEV_BANK0_BOOT (&flashDev[4]) /* PLCC */ -#define FLASH_DEV_BANK0_HIGH (&flashDev[5]) /* 512K PLCC shadow */ - -unsigned long flash_init(void); -int flashEraseSector(flash_dev_t *dev, int sector); -int flashErase(flash_dev_t *dev); -int flashRead(flash_dev_t *dev, int pos, char *buf, int len); -int flashWrite(flash_dev_t *dev, int pos, char *buf, int len); -int flashWritable(flash_dev_t *dev, int pos, int len); -int flashDiag(flash_dev_t *dev); -int flashDiagAll(void); - -ulong flash_get_size (vu_long *addr, flash_info_t *info); -void flash_print_info (flash_info_t *info); -int flash_erase (flash_info_t *info, int s_first, int s_last); -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); - -/* - * Flash info indices. - */ -#define FLASH_BANK_KERNEL 0 -#define FLASH_BANK_BOOT 1 -#define FLASH_BANK_AUX 2 -#define FIRST_SECTOR 0 - -#endif /* !FLASH_LIB_H */ diff --git a/board/mousse/m48t59y.c b/board/mousse/m48t59y.c deleted file mode 100644 index 37a6244..0000000 --- a/board/mousse/m48t59y.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and - * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD) - * registers which are used to set/get the internal date/time functions. - * - * This module implements Y2K compliance by taking full year numbers - * and translating back and forth from the TOD 2-digit year. - * - * NOTE: for proper interaction with an operating system, the TOD should - * be used to store Universal Coordinated Time (GMT) and timezone - * conversions should be used. - * - * Here is a diagram of the memory layout: - * - * +---------------------------------------------+ 0xffe0a000 - * | Non-volatile memory | . - * | | . - * | (8176 bytes of Non-volatile memory) | . - * | | . - * +---------------------------------------------+ 0xffe0bff0 - * | Flags | - * +---------------------------------------------+ 0xffe0bff1 - * | Unused | - * +---------------------------------------------+ 0xffe0bff2 - * | Alarm Seconds | - * +---------------------------------------------+ 0xffe0bff3 - * | Alarm Minutes | - * +---------------------------------------------+ 0xffe0bff4 - * | Alarm Date | - * +---------------------------------------------+ 0xffe0bff5 - * | Interrupts | - * +---------------------------------------------+ 0xffe0bff6 - * | WatchDog | - * +---------------------------------------------+ 0xffe0bff7 - * | Calibration | - * +---------------------------------------------+ 0xffe0bff8 - * | Seconds | - * +---------------------------------------------+ 0xffe0bff9 - * | Minutes | - * +---------------------------------------------+ 0xffe0bffa - * | Hours | - * +---------------------------------------------+ 0xffe0bffb - * | Day | - * +---------------------------------------------+ 0xffe0bffc - * | Date | - * +---------------------------------------------+ 0xffe0bffd - * | Month | - * +---------------------------------------------+ 0xffe0bffe - * | Year (2 digits only) | - * +---------------------------------------------+ 0xffe0bfff - */ -#include -#include -#include "mousse.h" - -/* - * Imported from mousse.h: - * - * TOD_REG_BASE Base of m48t59y TOD registers - * SYS_TOD_UNPROTECT() Disable NVRAM write protect - * SYS_TOD_PROTECT() Re-enable NVRAM write protect - */ - -#define YEAR 0xf -#define MONTH 0xe -#define DAY 0xd -#define DAY_OF_WEEK 0xc -#define HOUR 0xb -#define MINUTE 0xa -#define SECOND 0x9 -#define CONTROL 0x8 -#define WATCH 0x7 -#define INTCTL 0x6 -#define WD_DATE 0x5 -#define WD_HOUR 0x4 -#define WD_MIN 0x3 -#define WD_SEC 0x2 -#define _UNUSED 0x1 -#define FLAGS 0x0 - -#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE) - -int m48_tod_init(void) -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] = 0; - M48_ADDR[WATCH] = 0; - M48_ADDR[INTCTL] = 0; - - /* - * If the oscillator is currently stopped (as on a new part shipped - * from the factory), start it running. - * - * Here is an example of the TOD bytes on a brand new M48T59Y part: - * 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01 - */ - - if (M48_ADDR[SECOND] & 0x80) - M48_ADDR[SECOND] = 0; - - /* Is battery low */ - if ( M48_ADDR[FLAGS] & 0x10) { - printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n"); - } - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * m48_tod_set - */ - -static int to_bcd(int value) -{ - return value / 10 * 16 + value % 10; -} - -static int from_bcd(int value) -{ - return value / 16 * 10 + value % 16; -} - -static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */ -{ - static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4}; - y -= m < 3; - return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_set(int year, /* 1980-2079 */ - int month, /* 01-12 */ - int day, /* 01-31 */ - int hour, /* 00-23 */ - int minute, /* 00-59 */ - int second) /* 00-59 */ - -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */ - - M48_ADDR[YEAR] = to_bcd(year % 100); - M48_ADDR[MONTH] = to_bcd(month); - M48_ADDR[DAY] = to_bcd(day); - M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1; - M48_ADDR[HOUR] = to_bcd(hour); - M48_ADDR[MINUTE] = to_bcd(minute); - M48_ADDR[SECOND] = to_bcd(second); - - M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_get(int *year, /* 1980-2079 */ - int *month, /* 01-12 */ - int *day, /* 01-31 */ - int *hour, /* 00-23 */ - int *minute, /* 00-59 */ - int *second) /* 00-59 */ -{ - int y; - - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */ - - y = from_bcd(M48_ADDR[YEAR]); - *year = y < 80 ? 2000 + y : 1900 + y; - *month = from_bcd(M48_ADDR[MONTH]); - *day = from_bcd(M48_ADDR[DAY]); - /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */ - *hour = from_bcd(M48_ADDR[HOUR]); - *minute = from_bcd(M48_ADDR[MINUTE]); - *second = from_bcd(M48_ADDR[SECOND] & 0x7f); - - M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -int m48_tod_get_second(void) -{ - return from_bcd(M48_ADDR[SECOND] & 0x7f); -} - -/* - * Watchdog function - * - * If usec is 0, the watchdog timer is disarmed. - * - * If usec is non-zero, the watchdog timer is armed (or re-armed) for - * approximately usec microseconds (if the exact requested usec is - * not supported by the chip, the next higher available value is used). - * - * Minimum watchdog timeout = 62500 usec - * Maximum watchdog timeout = 124 sec (124000000 usec) - */ - -void m48_watchdog_arm(int usec) -{ - int mpy, res; - - SYS_TOD_UNPROTECT(); - - if (usec == 0) { - res = 0; - mpy = 0; - } else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */ - res = 0; - mpy = (usec + 62499) / 62500; - } else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */ - res = 1; - mpy = (usec + 249999) / 250000; - } else if (usec < 32000000) { /* Resolution: 1s if below 32s */ - res = 2; - mpy = (usec + 999999) / 1000000; - } else { /* Resolution: 4s up to 124s */ - res = 3; - mpy = (usec + 3999999) / 4000000; - if (mpy > 31) - mpy = 31; - } - - M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */ - mpy << 2 | - res); - - SYS_TOD_PROTECT(); -} - -/* - * U-Boot RTC support. - */ -void -rtc_get( struct rtc_time *tmp ) -{ - m48_tod_get(&tmp->tm_year, - &tmp->tm_mon, - &tmp->tm_mday, - &tmp->tm_hour, - &tmp->tm_min, - &tmp->tm_sec); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif -} - -void -rtc_set( struct rtc_time *tmp ) -{ - m48_tod_set(tmp->tm_year, /* 1980-2079 */ - tmp->tm_mon, /* 01-12 */ - tmp->tm_mday, /* 01-31 */ - tmp->tm_hour, /* 00-23 */ - tmp->tm_min, /* 00-59 */ - tmp->tm_sec); /* 00-59 */ - -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - -} - -void -rtc_reset (void) -{ - m48_tod_init(); -} diff --git a/board/mousse/m48t59y.h b/board/mousse/m48t59y.h deleted file mode 100644 index 717300d..0000000 --- a/board/mousse/m48t59y.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __M48_T59_Y_H -#define __M48_T59_Y_H - -/* - * M48 T59Y -Timekeeping Battery backed SRAM. - */ - -int m48_tod_init(void); - -int m48_tod_set(int year, - int month, - int day, - int hour, - int minute, - int second); - -int m48_tod_get(int *year, - int *month, - int *day, - int *hour, - int *minute, - int *second); - -int m48_tod_get_second(void); - -void m48_watchdog_arm(int usec); - -#endif /*!__M48_T59_Y_H */ diff --git a/board/mousse/mousse.c b/board/mousse/mousse.c deleted file mode 100644 index 7208a17..0000000 --- a/board/mousse/mousse.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * MOUSSE Board Support - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty, jfd@cs.stanford.edu - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "mousse.h" -#include "m48t59y.h" -#include - - -int checkboard (void) -{ - ulong busfreq = get_bus_freq (0); - char buf[32]; - - puts ("Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)\n"); - printf ("Built: %s at %s\n", __DATE__, __TIME__); - printf ("MPLD: Revision %d\n", SYS_REVID_GET ()); - printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); - - return 0; -} - -int checkflash (void) -{ - printf ("checkflash\n"); - flash_init (); - return 0; -} - -long int initdram (int board_type) -{ - return CFG_RAM_SIZE; -} - - -void get_tod (void) -{ - int year, month, day, hour, minute, second; - - m48_tod_get (&year, &month, &day, &hour, &minute, &second); - - printf (" Current date/time: %d/%d/%d %d:%d:%d \n", - month, day, year, hour, minute, second); - -} - -/* - * EPIC, PCI, and I/O devices. - * Initialize Mousse Platform, probe for PCI devices, - * Query configuration parameters if not set. - */ -int misc_init_f (void) -{ - m48_tod_init (); /* Init SGS M48T59Y TOD/NVRAM */ - printf ("RTC: M48T589 TOD/NVRAM (%d) bytes\n", TOD_NVRAM_SIZE); - get_tod (); - return 0; -} diff --git a/board/mousse/mousse.h b/board/mousse/mousse.h deleted file mode 100644 index 5468314..0000000 --- a/board/mousse/mousse.h +++ /dev/null @@ -1,259 +0,0 @@ -/* - * MOUSSE/MPC8240 Board definitions. - * For more info, see http://www.vooha.com/ - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MOUSSE_H -#define __MOUSSE_H - -/* System addresses */ - -#define PCI_SPECIAL_BASE 0xfe000000 -#define PCI_SPECIAL_SIZE 0x01000000 - -/* PORTX Device Addresses for Mousse */ - -#define PORTX_DEV_BASE 0xff000000 -#define PORTX_DEV_SIZE 0x01000000 - -#define ENET_DEV_BASE 0x80000000 - -#define PLD_REG_BASE (PORTX_DEV_BASE | 0xe09000) -#define PLD_REG(off) (*(volatile unsigned char *) \ - (PLD_REG_BASE + (off))) - -#define PLD_REVID_B1 0x7f -#define PLD_REVID_B2 0x01 - -/* MPLD */ -#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */ -#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f) -#define SYS_LED_OFF() (PLD_REG(1) |= 0x80) -#define SYS_LED_ON() (PLD_REG(1) &= ~0x80) -#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80) -#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80) -#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80) -#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80) - -/* SGS M48T59Y */ -#define TOD_BASE (PORTX_DEV_BASE | 0xe0a000) -#define TOD_REG_BASE (TOD_BASE | 0x1ff0) -#define TOD_NVRAM_BASE TOD_BASE -#define TOD_NVRAM_SIZE 0x1ff0 -#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE) - -/* NS16552 SIO */ -#define SERIAL_BASE(_x) (PORTX_DEV_BASE | 0xe08000 | ((_x) ? 0 : 0x80)) -#define N_SIO_CHANNELS 2 -#define N_COM_PORTS N_SIO_CHANNELS - -/* - * On-board Dec21143 PCI Ethernet - * Note: The PCI MBAR chosen here was used from MPC8240UM which states - * that PCI memory is at: 0x80000 - 0xFDFFFFFF, if AMBOR[CPU_FD_ALIAS] - * is set, then PCI memory maps 1-1 with this address range in the - * correct byte order. - */ -#define PCI_ENET_IOADDR 0x80000000 -#define PCI_ENET_MEMADDR 0x80000000 - -/* - * Flash Memory Layout - * - * 2 MB Flash Bank 0 runs in 8-bit mode. In Flash Bank 0, the 32 kB - * sector SA3 is obscured by the 32 kB serial/TOD access space, and - * the 64 kB sectors SA19-SA26 are obscured by the 512 kB PLCC - * containing the fixed boot ROM. (If the 512 kB PLCC is - * deconfigured by jumper, this window to Flash Bank 0 becomes - * visible, but it still contains the fixed boot code and should be - * considered read-only). Flash Bank 0 sectors SA0 (16 kB), SA1 (8 - * kB), and SA2 (8 kB) are currently unused. - * - * 2 MB Flash Bank 1 runs in 16-bit mode. Flash Bank 1 is fully - * usable, but it's a 16-bit wide device on a 64-bit bus. Therefore - * 16-bit words only exist at addresses that are multiples of 8. All - * PROM data and control addresses must be multiplied by 8. - * - * See flashMap.c for description of flash filesystem layout. - */ - -/* - * FLASH memory address space: 8-bit wide FLASH memory spaces. - */ -#define FLASH0_SEG0_START 0xffe00000 /* Baby 32Kb segment */ -#define FLASH0_SEG0_END 0xffe07fff /* 16 kB + 8 kB + 8 kB */ -#define FLASH0_SEG0_SIZE 0x00008000 /* (sectors SA0-SA2) */ - -#define FLASH0_SEG1_START 0xffe10000 /* 1MB - 64Kb FLASH0 seg */ -#define FLASH0_SEG1_END 0xffefffff /* 960 kB */ -#define FLASH0_SEG1_SIZE 0x000f0000 - -#define FLASH0_SEG2_START 0xfff00000 /* Boot Loader stored here */ -#define FLASH0_SEG2_END 0xfff7ffff /* 512 kB FLASH0/PLCC seg */ -#define FLASH0_SEG2_SIZE 0x00080000 - -#define FLASH0_SEG3_START 0xfff80000 /* 512 kB FLASH0 seg */ -#define FLASH0_SEG3_END 0xffffffff -#define FLASH0_SEG3_SIZE 0x00080000 - -/* Where Kahlua starts */ -#define FLASH_RESET_VECT 0xfff00100 - -/* - * CHRP / PREP (MAP A/B) definitions. - */ - -#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */ -#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */ -/* MPC107 (MPC8240 internal EUMBBAR mapped) */ -#define CHRP_REG_ADDR 0xfec00000 /* MPC106 Config, Map B */ -#define CHRP_REG_DATA 0xfee00000 /* MPC106 Config, Map B */ - -/* - * Mousse PCI IDSEL Assignments (Device Number) - */ -#define MOUSSE_IDSEL_ENET 13 /* On-board 21143 Ethernet */ -#define MOUSSE_IDSEL_LPCI 14 /* On-board PCI slot */ -#define MOUSSE_IDSEL_82371 15 /* That other thing */ -#define MOUSSE_IDSEL_CPCI2 31 /* CPCI slot 2 */ -#define MOUSSE_IDSEL_CPCI3 30 /* CPCI slot 3 */ -#define MOUSSE_IDSEL_CPCI4 29 /* CPCI slot 4 */ -#define MOUSSE_IDSEL_CPCI5 28 /* CPCI slot 5 */ -#define MOUSSE_IDSEL_CPCI6 27 /* CPCI slot 6 */ - -/* - * Mousse Interrupt Mapping: - * - * IRQ1 Enet (intA|intB|intC|intD) - * IRQ2 CPCI intA (See below) - * IRQ3 Local PCI slot intA|intB|intC|intD - * IRQ4 COM1 Serial port (Actually higher addressed port on duart) - * - * PCI Interrupt Mapping in CPCI chassis: - * - * | CPCI Slot - * | 1 (CPU) 2 3 4 5 6 - * -----------+--------+-------+-------+-------+-------+-------+ - * intA | X X X - * intB | X X X - * intC | X X X - * intD | X X X - */ - - -#define EPIC_VECTOR_EXT0 0 -#define EPIC_VECTOR_EXT1 1 -#define EPIC_VECTOR_EXT2 2 -#define EPIC_VECTOR_EXT3 3 -#define EPIC_VECTOR_EXT4 4 -#define EPIC_VECTOR_TM0 16 -#define EPIC_VECTOR_TM1 17 -#define EPIC_VECTOR_TM2 18 -#define EPIC_VECTOR_TM3 19 -#define EPIC_VECTOR_I2C 20 -#define EPIC_VECTOR_DMA0 21 -#define EPIC_VECTOR_DMA1 22 -#define EPIC_VECTOR_I2O 23 - - -#define INT_VEC_IRQ0 0 -#define INT_NUM_IRQ0 INT_VEC_IRQ0 -#define MOUSSE_IRQ_ENET EPIC_VECTOR_EXT1 /* Hardwired */ -#define MOUSSE_IRQ_CPCI EPIC_VECTOR_EXT2 /* Hardwired */ -#define MOUSSE_IRQ_LPCI EPIC_VECTOR_EXT3 /* Hardwired */ -#define MOUSSE_IRQ_DUART EPIC_VECTOR_EXT4 /* Hardwired */ - -/* Onboard DEC 21143 Ethernet */ -#define PCI_ENET_MEMADDR 0x80000000 -#define PCI_ENET_IOADDR 0x80000000 - -/* Some other PCI device */ -#define PCI_SLOT_MEMADDR 0x81000000 -#define PCI_SLOT_IOADDR 0x81000000 - -/* Promise ATA66 PCI Device (ATA controller) */ -#define PROMISE_MBAR0 0xa0000000 -#define PROMISE_MBAR1 (PROMISE_MBAR0 + 0x1000) -#define PROMISE_MBAR2 (PROMISE_MBAR0 + 0x2000) -#define PROMISE_MBAR3 (PROMISE_MBAR0 + 0x3000) -#define PROMISE_MBAR4 (PROMISE_MBAR0 + 0x4000) -#define PROMISE_MBAR5 (PROMISE_MBAR0 + 0x5000) - -/* ATA/66 Controller offsets */ -#define CFG_ATA_BASE_ADDR PROMISE_MBAR0 -#define CFG_IDE_MAXBUS 2 /* ide0/ide1 */ -#define CFG_IDE_MAXDEVICE 2 /* 2 drives per controller */ -#define CFG_ATA_IDE0_OFFSET 0 -#define CFG_ATA_IDE1_OFFSET 0x3000 -/* - * Definitions for accessing IDE controller registers - */ -#define CFG_ATA_DATA_OFFSET 0 -#define CFG_ATA_REG_OFFSET 0 -#define CFG_ATA_ALT_OFFSET (0x1000) - -/* - * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS - * are defined in config.h and Makefile. - * All definitions for these constants must be identical. - */ -#define ROM_BASE_ADRS 0xfff00000 /* base address of ROM */ -#define ROM_TEXT_ADRS (ROM_BASE_ADRS+0x0100) /* with PC & SP */ -#define ROM_WARM_ADRS (ROM_TEXT_ADRS+0x0004) /* warm reboot entry */ -#define ROM_SIZE 0x00080000 /* 512KB ROM space */ -#define RAM_LOW_ADRS 0x00010000 /* RAM address for vxWorks */ -#define RAM_HIGH_ADRS 0x00c00000 /* RAM address for bootrom */ - -/* - * NVRAM configuration - * NVRAM is implemented via the SGS Thomson M48T59Y - * 64Kbit (8Kbx8) Timekeeper SRAM. - * This 8KB NVRAM also has a TOD. See m48t59y.{h,c} for more information. - */ - -#define NV_RAM_ADRS TOD_NVRAM_BASE -#define NV_RAM_INTRVL 1 -#define NV_RAM_WR_ENBL SYS_TOD_UNPROTECT() -#define NV_RAM_WR_DSBL SYS_TOD_PROTECT() - -#define NV_OFF_BOOT0 0x0000 /* Boot string 0 (256b) */ -#define NV_OFF_BOOT1 0x0100 /* Boot string 1 (256b) */ -#define NV_OFF_BOOT2 0x0200 /* Boot string 2 (256b)*/ -#define NV_OFF_MACADDR 0x0400 /* 21143 MAC address (6b) */ -#define NV_OFF_ACTIVEBOOT 0x0406 /* Active boot string, 0 to 2 (1b) */ -#define NV_OFF_UNUSED1 0x0407 /* Unused (1b) */ -#define NV_OFF_BINDFIX 0x0408 /* See sysLib.c:sysBindFix() (1b) */ -#define NV_OFF_UNUSED2 0x0409 /* Unused (7b) */ -#define NV_OFF_TIMEZONE 0x0410 /* TIMEZONE env var (64b) */ -#define NV_OFF_VXWORKS_END 0x07FF /* 2047 VxWorks Total */ -#define NV_OFF_U_BOOT 0x0800 /* 2048 U-Boot boot-loader */ -#define NV_OFF_U_BOOT_ADDR (TOD_BASE + NV_OFF_U_BOOT) /* sysaddr*/ -#define NV_U_BOOT_ENV_SIZE 2048 /* 2K - U-Boot Total */ -#define NV_OFF__next_free (NV_U_BOOT_ENVSIZE +1) -#define NV_RAM_SIZE 8176 /* NVRAM End */ - -#endif /* __MOUSSE_H */ diff --git a/board/mousse/pci.c b/board/mousse/pci.c deleted file mode 100644 index 4f39398..0000000 --- a/board/mousse/pci.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge - */ -#include -#include -#include - -#include "mousse.h" - -/* - * Promise ATA/66 support. - */ -#define XFER_PIO_4 0x0C /* 0000|1100 */ -#define XFER_PIO_3 0x0B /* 0000|1011 */ -#define XFER_PIO_2 0x0A /* 0000|1010 */ -#define XFER_PIO_1 0x09 /* 0000|1001 */ -#define XFER_PIO_0 0x08 /* 0000|1000 */ -#define XFER_PIO_SLOW 0x00 /* 0000|0000 */ - -/* Promise Regs */ -#define REG_A 0x01 -#define REG_B 0x02 -#define REG_C 0x04 -#define REG_D 0x08 - -void -pdc202xx_decode_registers (unsigned char registers, unsigned char value) -{ - unsigned char bit = 0, bit1 = 0, bit2 = 0; - switch(registers) { - case REG_A: - bit2 = 0; - printf(" A Register "); - if (value & 0x80) printf("SYNC_IN "); - if (value & 0x40) printf("ERRDY_EN "); - if (value & 0x20) printf("IORDY_EN "); - if (value & 0x10) printf("PREFETCH_EN "); - if (value & 0x08) { printf("PA3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("PA2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("PA1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("PA0 ");bit2 |= 0x01; } - printf("PIO(A) = %d ", bit2); - break; - case REG_B: - bit1 = 0;bit2 = 0; - printf(" B Register "); - if (value & 0x80) { printf("MB2 ");bit1 |= 0x80; } - if (value & 0x40) { printf("MB1 ");bit1 |= 0x40; } - if (value & 0x20) { printf("MB0 ");bit1 |= 0x20; } - printf("DMA(B) = %d ", bit1 >> 5); - if (value & 0x10) printf("PIO_FORCED/PB4 "); - if (value & 0x08) { printf("PB3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("PB2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("PB1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("PB0 ");bit2 |= 0x01; } - printf("PIO(B) = %d ", bit2); - break; - case REG_C: - bit2 = 0; - printf(" C Register "); - if (value & 0x80) printf("DMARQp "); - if (value & 0x40) printf("IORDYp "); - if (value & 0x20) printf("DMAR_EN "); - if (value & 0x10) printf("DMAW_EN "); - - if (value & 0x08) { printf("MC3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("MC2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("MC1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("MC0 ");bit2 |= 0x01; } - printf("DMA(C) = %d ", bit2); - break; - case REG_D: - printf(" D Register "); - break; - default: - return; - } - printf("\n %s ", (registers & REG_D) ? "DP" : - (registers & REG_C) ? "CP" : - (registers & REG_B) ? "BP" : - (registers & REG_A) ? "AP" : "ERROR"); - for (bit=128;bit>0;bit/=2) - printf("%s", (value & bit) ? "1" : "0"); - printf("\n"); -} - -/* - * Promise ATA/66 Support: configure Promise ATA66 card in specified mode. - */ -int -pdc202xx_tune_chipset (pci_dev_t dev, int drive, unsigned char speed) -{ - unsigned short drive_conf; - int err = 0; - unsigned char drive_pci, AP, BP, CP, DP; - unsigned char TA = 0, TB = 0; - - switch (drive) { - case 0: drive_pci = 0x60; break; - case 1: drive_pci = 0x64; break; - case 2: drive_pci = 0x68; break; - case 3: drive_pci = 0x6c; break; - default: return -1; - } - - pci_read_config_word(dev, drive_pci, &drive_conf); - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - pci_read_config_byte(dev, (drive_pci)|0x03, &DP); - - if ((AP & 0x0F) || (BP & 0x07)) { - /* clear PIO modes of lower 8421 bits of A Register */ - pci_write_config_byte(dev, (drive_pci), AP & ~0x0F); - pci_read_config_byte(dev, (drive_pci), &AP); - - /* clear PIO modes of lower 421 bits of B Register */ - pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - } - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - - switch(speed) { - case XFER_PIO_4: TA = 0x01; TB = 0x04; break; - case XFER_PIO_3: TA = 0x02; TB = 0x06; break; - case XFER_PIO_2: TA = 0x03; TB = 0x08; break; - case XFER_PIO_1: TA = 0x05; TB = 0x0C; break; - case XFER_PIO_0: - default: TA = 0x09; TB = 0x13; break; - } - - pci_write_config_byte(dev, (drive_pci), AP|TA); - pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB); - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - pci_read_config_byte(dev, (drive_pci)|0x03, &DP); - - -#ifdef PDC202XX_DEBUG - pdc202xx_decode_registers(REG_A, AP); - pdc202xx_decode_registers(REG_B, BP); - pdc202xx_decode_registers(REG_C, CP); - pdc202xx_decode_registers(REG_D, DP); -#endif - return err; -} -/* - * Show/Init PCI devices on the specified bus number. - */ - -void pci_mousse_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned int line; - - switch(PCI_DEV(dev)) { - case 0x0d: - line = 0x00000101; - break; - - case 0x0e: - default: - line = 0x00000303; - break; - } - - pci_write_config_dword(dev, PCI_INTERRUPT_LINE, line); -} - -void pci_mousse_setup_pdc202xx(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *_) -{ - unsigned short vendorId; - unsigned int mbar0, cmd; - int bar, a; - - pci_read_config_word(dev, PCI_VENDOR_ID, &vendorId); - - if(vendorId == PCI_VENDOR_ID_PROMISE || vendorId == PCI_VENDOR_ID_CMD){ - /* PDC 202xx card is handled differently, it is a bootable - * device and needs all 5 MBAR's configured - */ - for(bar = 0; bar < 5; bar++){ - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, ~0); - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); -#ifdef DEBUG - printf(" ATA_bar[%d] = %dbytes\n", bar, - ~(mbar0 & PCI_BASE_ADDRESS_MEM_MASK) + 1); -#endif - } - - /* Program all BAR's */ - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PROMISE_MBAR0); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, PROMISE_MBAR1); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, PROMISE_MBAR2); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, PROMISE_MBAR3); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, PROMISE_MBAR4); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, PROMISE_MBAR5); - - for(bar = 0; bar < 5; bar++){ - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); -#ifdef DEBUG - printf(" ATA_bar[%d]@0x%x\n", bar, mbar0); -#endif - } - - /* Enable ROM Expansion base */ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, PROMISE_MBAR5|1); - - /* Io enable, Memory enable, master enable */ - pci_read_config_dword(dev, PCI_COMMAND, &cmd); - cmd &= ~0xffff0000; - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config_dword(dev, PCI_COMMAND, cmd); - - /* Breath some life into the controller */ - for( a = 0; a < 4; a++) - pdc202xx_tune_chipset(dev, a, XFER_PIO_0); - } -} - -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0e, 0x00, - pci_mousse_setup_pdc202xx }, -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0d, 0x00, - pci_cfgfunc_config_device, {PCI_ENET_IOADDR, - PCI_ENET_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_SLOT_IOADDR, - PCI_SLOT_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, -#endif - { } -}; - -struct pci_controller hose = { - config_table: pci_sandpoint_config_table, - fixup_irq: pci_mousse_fixup_irq, -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds deleted file mode 100644 index 57358b8..0000000 --- a/board/mousse/u-boot.lds +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram deleted file mode 100644 index eb47ae6..0000000 --- a/board/mousse/u-boot.lds.ram +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems Ltd. robt@flyingpig.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); - -MEMORY { - ram (!rx) : org = 0x00000000 , LENGTH = 8M - code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000) - rom (rx) : org = 0xfff00000 , LENGTH = 512K -} - -SECTIONS -{ - _f_init = .; - PROVIDE(_f_init = .); - _f_init_rom = .; - PROVIDE(_f_init_rom = .); - - .init : { - cpu/mpc824x/start.o (.text) - *(.init) - } > ram - _init_size = SIZEOF(.init); - PROVIDE(_init_size = SIZEOF(.init)); - - ENTRY(_start) - -/* _ftext = .; - _ftext_rom = .; - _text_size = SIZEOF(.text); - */ - .text : { - *(.text) - *(.got1) - } > ram - .rodata : { *(.rodata) } > ram - .dtors : { *(.dtors) } > ram - .data : { *(.data) } > ram - .sdata : { *(.sdata) } > ram - .sdata2 : { *(.sdata2) - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } > ram - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .sbss : { *(.sbss) } > ram - .sbss2 : { *(.sbss2) } > ram - .bss : { *(.bss) } > ram - .debug : { *(.debug) } > ram - .line : { *(.line) } > ram - .symtab : { *(.symtab) } > ram - .shrstrtab : { *(.shstrtab) } > ram - .strtab : { *(.strtab) } > ram - /* .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } > ram - */ - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - __start___ex_table = .; - __ex_table : { *(__ex_table) } > ram - __stop___ex_table = .; - - - .ppcenv : - { - common/environment.o (.ppcenv) - } > ram - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom deleted file mode 100644 index 5a5722e..0000000 --- a/board/mousse/u-boot.lds.rom +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - common/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mp2usb/Makefile b/board/mp2usb/Makefile deleted file mode 100644 index b6ea3cf..0000000 --- a/board/mp2usb/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := mp2usb.o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mp2usb/config.mk b/board/mp2usb/config.mk deleted file mode 100644 index e299bfd..0000000 --- a/board/mp2usb/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -TEXT_BASE = 0x27F00000 -## For testing: load at 0x20100000 and "go" at 0x201000A4 -#TEXT_BASE = 0x20100000 diff --git a/board/mp2usb/flash.c b/board/mp2usb/flash.c deleted file mode 100644 index 89ced16..0000000 --- a/board/mp2usb/flash.c +++ /dev/null @@ -1,552 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified for the MP2USB by (C) Copyright 2005 Eric Benard - * ebenard@eukrea.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define CFG_MAX_FLASH_BANKS 1 -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x00100010 -#define INTEL_ERASE 0x00200020 -#define INTEL_PROG 0x00400040 -#define INTEL_CLEAR 0x00500050 -#define INTEL_LOCKBIT 0x00600060 -#define INTEL_PROTECT 0x00010001 -#define INTEL_STATUS 0x00700070 -#define INTEL_READID 0x00900090 -#define INTEL_SUSPEND 0x00B000B0 -#define INTEL_CONFIRM 0x00D000D0 -#define INTEL_RESET 0xFFFFFFFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x00800080 -#define INTEL_OK 0x00800080 - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) INTEL_RESET; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) INTEL_RESET; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int prot, sect; - ulong type, start, last; - int rcode = 0; - int cflag, iflag; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - /* Disable interrupts which might cause a timeout here */ - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) INTEL_CLEAR; /* clear status register */ - *addr = (FPW) INTEL_ERASE; /* erase setup */ - *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ - - while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) INTEL_SUSPEND; /* suspend erase */ - *addr = (FPW) INTEL_RESET; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = (FPWV)INTEL_CLEAR; /* clear status register cmd. */ - *addr = (FPWV)INTEL_RESET; /* resest to read mode */ - - printf (" done\n"); - } - } - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - /* get lower word aligned address */ - wp = (addr & ~1); - port_width = 2; - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int cflag, iflag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - /* Disable interrupts which might cause a timeout here */ - iflag = disable_interrupts (); - - *addr = (FPW) INTEL_PROG; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) INTEL_RESET; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) INTEL_RESET; /* restore read mode */ - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int i; - int rc = 0; - FPWV *addr = (FPWV *)(info->start[sector]); - int flag = disable_interrupts(); - - *addr = (FPW) INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = (FPW) INTEL_LOCKBIT; /* Sector lock bit */ - *addr = (FPW) INTEL_PROTECT; /* set */ - } - else { /* Clear sector lock bit */ - *addr = (FPW) INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = (FPW) INTEL_CONFIRM; /* clear */ - } - - reset_timer_masked (); - - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != (FPW) INTEL_OK) { - printf("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - */ - if (!prot) - { - for (i = 0; i < info->sector_count; i++) - { - if (info->protect[i]) - { - reset_timer_masked (); - addr = (FPWV *) (info->start[i]); - *addr = (FPW) INTEL_LOCKBIT; /* Sector lock bit */ - *addr = (FPW) INTEL_PROTECT; /* set */ - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) - { - if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) - { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - } - } - } - - if (flag) - enable_interrupts(); - - *addr = (FPW) INTEL_RESET; /* Reset to read array mode */ - - return rc; -} diff --git a/board/mp2usb/mp2usb.c b/board/mp2usb/mp2usb.c deleted file mode 100644 index e75be1e..0000000 --- a/board/mp2usb/mp2usb.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Modified for the MP2USB by (C) Copyright 2005 Eric Benard - * ebenard@eukrea.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Enable Ctrlc */ - console_init_f (); - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of MP2USB-Board. */ - gd->bd->bi_arch_number = MACH_TYPE_MP2USB; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if (CONFIG_COMMANDS & CFG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = dm9161_InitPhy; - p_phyops->IsPhyConnected = dm9161_IsPhyConnected; - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; - p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/mp2usb/u-boot.lds b/board/mp2usb/u-boot.lds deleted file mode 100644 index 76df6b2..0000000 --- a/board/mp2usb/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/mpc8260ads/Makefile b/board/mpc8260ads/Makefile deleted file mode 100644 index cc519d1..0000000 --- a/board/mpc8260ads/Makefile +++ /dev/null @@ -1,47 +0,0 @@ - -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mpc8260ads/config.mk b/board/mpc8260ads/config.mk deleted file mode 100644 index eb6f7c9..0000000 --- a/board/mpc8260ads/config.mk +++ /dev/null @@ -1,37 +0,0 @@ -# -# (C) Copyright 2001-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com -# -# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MPC8260ADS, MPC8266ADS, and PQ2FADS-ZU/VR boards -# - -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -## Standard: boot high -TEXT_BASE = 0xFFF00000 -endif diff --git a/board/mpc8260ads/flash.c b/board/mpc8260ads/flash.c deleted file mode 100644 index 59997aa..0000000 --- a/board/mpc8260ads/flash.c +++ /dev/null @@ -1,492 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * (C) Copyright 2003 Arabella Software Ltd. - * Yuli Barcohen - * Re-written to support multi-bank flash SIMMs. - * Added support for real protection and JFFS2. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* Intel-compatible flash ID */ -#define INTEL_COMPAT 0x89898989 -#define INTEL_ALT 0xB0B0B0B0 - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x10101010 -#define INTEL_ERASE 0x20202020 -#define INTEL_CLEAR 0x50505050 -#define INTEL_LOCKBIT 0x60606060 -#define INTEL_PROTECT 0x01010101 -#define INTEL_STATUS 0x70707070 -#define INTEL_READID 0x90909090 -#define INTEL_CONFIRM 0xD0D0D0D0 -#define INTEL_RESET 0xFFFFFFFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x80808080 -#define INTEL_OK 0x80808080 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.) - * Up to 32MB of flash supported (up to 4 banks.) - * BCSR is used for flash presence detect (page 4-65 of the User's Manual) - * - * The following code can not run from flash! - */ -unsigned long flash_init (void) -{ - ulong size = 0, sect_start, sect_size = 0, bank_size; - ushort sect_count = 0; - int i, j, nbanks; - vu_long *addr = (vu_long *)CFG_FLASH_BASE; - vu_long *bcsr = (vu_long *)CFG_BCSR; - - switch (bcsr[2] & 0xF) { - case 0: - nbanks = 4; - break; - case 1: - nbanks = 2; - break; - case 2: - nbanks = 1; - break; - default: /* Unsupported configurations */ - nbanks = CFG_MAX_FLASH_BANKS; - } - - if (nbanks > CFG_MAX_FLASH_BANKS) - nbanks = CFG_MAX_FLASH_BANKS; - - for (i = 0; i < nbanks; i++) { - *addr = INTEL_READID; /* Read Intelligent Identifier */ - if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) { - switch (addr[1]) { - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - sect_count = 32; - sect_size = 0x40000; - break; - default: - flash_info[i].flash_id = FLASH_UNKNOWN; - sect_count = CFG_MAX_FLASH_SECT; - sect_size = - CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT; - } - } - else - flash_info[i].flash_id = FLASH_UNKNOWN; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n", - addr[0], addr[1], (ulong)addr); - size = 0; - *addr = INTEL_RESET; /* Reset bank to Read Array mode */ - break; - } - flash_info[i].sector_count = sect_count; - flash_info[i].size = bank_size = sect_size * sect_count; - size += bank_size; - sect_start = (ulong)addr; - for (j = 0; j < sect_count; j++) { - addr = (vu_long *)sect_start; - flash_info[i].start[j] = sect_start; - flash_info[i].protect[j] = (addr[2] == 0x01010101); - sect_start += sect_size; - } - *addr = INTEL_RESET; /* Reset bank to Read Array mode */ - addr = (vu_long *)sect_start; - } - - if (size == 0) { /* Unknown flash, fill with hard-coded values */ - sect_start = CFG_FLASH_BASE; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS; - flash_info[i].sector_count = sect_count; - for (j = 0; j < sect_count; j++) { - flash_info[i].start[j] = sect_start; - flash_info[i].protect[j] = 0; - sect_start += sect_size; - } - } - size = CFG_FLASH_SIZE; - } - else - for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = 0; - flash_info[i].sector_count = 0; - } - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Clear Status Register */ - *addr = INTEL_CLEAR; - /* Single Block Erase Command */ - *addr = INTEL_ERASE; - /* Confirm */ - *addr = INTEL_CONFIRM; - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = INTEL_CONFIRM; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = INTEL_RESET; /* reset bank */ - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - if (*addr != INTEL_OK) { - printf("Block erase failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - *addr = INTEL_RESET; /* reset bank */ - return 1; - } - - /* reset to read mode */ - *addr = INTEL_RESET; - } - } - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - ulong start; - int rc = 0; - int flag; - vu_long *addr = (vu_long *)dest; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - - *addr = INTEL_CLEAR; /* Clear status register */ - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = INTEL_PROGRAM; - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - printf("Write timed out\n"); - rc = 1; - break; - } - } - if (*addr != INTEL_OK) { - printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr); - rc = 1; - } - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - rc = write_word(info, wp, data); - - return rc; -} - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - ulong start; - int i; - int rc = 0; - vu_long *addr = (vu_long *)(info->start[sector]); - int flag = disable_interrupts(); - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } - else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - start = get_timer(0); - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - */ - if (!prot) - for (i = 0; i < info->sector_count; i++) - if (info->protect[i]) { - addr = (vu_long *)(info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - udelay(CFG_FLASH_LOCK_TOUT * 1000); - } - - if (flag) - enable_interrupts(); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} diff --git a/board/mpc8260ads/mpc8260ads.c b/board/mpc8260ads/mpc8260ads.c deleted file mode 100644 index 93550e2..0000000 --- a/board/mpc8260ads/mpc8260ads.c +++ /dev/null @@ -1,546 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified during 2001 by - * Advanced Communications Technologies (Australia) Pty. Ltd. - * Howard Walker, Tuong Vu-Dinh - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Added support for the 16M dram simm on the 8260ads boards - * - * (C) Copyright 2003-2004 Arabella Software Ltd. - * Yuli Barcohen - * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init. - * - * Copyright (c) 2005 MontaVista Software, Inc. - * Vitaly Bordug - * Added support for PCI. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_PCI -#include -#endif - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) -#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3) - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */ - /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */ - /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ -#if CONFIG_ADSTYPE == CFG_8272ADS - /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */ - /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */ -#else - /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ - /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ -#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ -#if CONFIG_ADSTYPE == CFG_8272ADS - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ -#else - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ -#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -void reset_phy (void) -{ - vu_long *bcsr = (vu_long *)CFG_BCSR; - - /* Reset the PHY */ -#if CFG_PHY_ADDR == 0 - bcsr[1] &= ~(FETHIEN1 | FETH1_RST); - udelay(2); - bcsr[1] |= FETH1_RST; -#else - bcsr[3] &= ~(FETHIEN2 | FETH2_RST); - udelay(2); - bcsr[3] |= FETH2_RST; -#endif /* CFG_PHY_ADDR == 0 */ - udelay(1000); -#ifdef CONFIG_MII -#if CONFIG_ADSTYPE >= CFG_PQ2FADS - /* - * Do not bypass Rx/Tx (de)scrambler (fix configuration error) - * Enable autonegotiation. - */ - bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610); - bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); -#else - /* - * Ethernet PHY is configured (by means of configuration pins) - * to work at 10Mb/s only. We reconfigure it using MII - * to advertise all capabilities, including 100Mb/s, and - * restart autonegotiation. - */ - - /* Advertise all capabilities */ - bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1); - - /* Do not bypass Rx/Tx (de)scrambler */ - bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000); - - bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); -#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ -#endif /* CONFIG_MII */ -} - -#ifdef CONFIG_PCI -typedef struct pci_ic_s { - unsigned long pci_int_stat; - unsigned long pci_int_mask; -}pci_ic_t; -#endif - -int board_early_init_f (void) -{ - vu_long *bcsr = (vu_long *)CFG_BCSR; - -#ifdef CONFIG_PCI - volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT; - - /* mask alll the PCI interrupts */ - pci_ic->pci_int_mask |= 0xfff00000; -#endif -#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1) - bcsr[1] &= ~RS232EN_1; -#endif -#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1) - bcsr[1] &= ~RS232EN_2; -#endif - -#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */ -#if CONFIG_ADSTYPE == CFG_PQ2FADS - if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */ -#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ - { - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; - immap->im_siu_conf.sc_siumcr = - (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) - | SIUMCR_LBPC01; - } -#endif /* CONFIG_ADSTYPE != CFG_8260ADS */ - - return 0; -} - -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) - -long int initdram (int board_type) -{ -#if CONFIG_ADSTYPE == CFG_PQ2FADS - long int msize = 32; -#elif CONFIG_ADSTYPE == CFG_8272ADS - long int msize = 64; -#else - long int msize = 16; -#endif - -#ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar *ramaddr, c = 0xff; - uint or; - uint psdmr; - uint psrt; - - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x00000002; - immap->im_siu_conf.sc_ppc_alrh = 0x01267893; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CFG_MPTPR; -#ifdef CFG_LSDRAM_BASE - /* - Initialise local bus SDRAM only if the pins - are configured as local bus pins and not as PCI. - The configuration is determined by the HRCW. - */ - if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { - memctl->memc_lsrt = CFG_LSRT; -#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */ - memctl->memc_or3 = 0xFF803280; - memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861; -#else /* CS4 */ - memctl->memc_or4 = 0xFFC01480; - memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; -#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ - memctl->memc_lsdmr = CFG_LSDMR | 0x28000000; - ramaddr = (uchar *) CFG_LSDRAM_BASE; - *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | 0x08000000; - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | 0x18000000; - *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | 0x40000000; - } -#endif /* CFG_LSDRAM_BASE */ - - /* Init 60x bus SDRAM */ -#ifdef CONFIG_SPD_EEPROM - { - spd_eeprom_t spd; - uint pbi, bsel, rowst, lsb, tmp; - - i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd)); - - /* Bank-based interleaving is not supported for physical bank - sizes greater than 128MB which is encoded as 0x20 in SPD - */ - pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI; - msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */ - or = ~(msize - 1) << 20; /* SDAM */ - switch (spd.nbanks) { /* BPD */ - case 2: - bsel = 1; - break; - case 4: - bsel = 2; - or |= 0x00002000; - break; - case 8: - bsel = 3; - or |= 0x00004000; - break; - } - lsb = 3; /* For 64-bit port, lsb is 3 bits */ - - if (pbi) { /* Bus partition depends on interleaving */ - rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb); - or |= (rowst << 9); /* ROWST */ - } else { - rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb); - or |= ((rowst * 2 - 12) << 9); /* ROWST */ - } - or |= ((spd.nrow_addr - 9) << 6); /* NUMR */ - - psdmr = (pbi << 31); /* PBI */ - /* Bus multiplexing parameters */ - tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */ - psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */ - psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */ - - tmp = (31 - lsb - 10) - tmp; - /* Pin connected to SDA10 is (31 - lsb - 10). - rowst is multiplexed over (32 - (lsb + spd.nrow_addr)), - so (rowst + tmp) alternates with AP. - */ - if (pbi) /* Table 10-7 */ - psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */ - else - psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */ - - /* SDRAM device-specific parameters */ - tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */ - switch (tmp) { /* RFRC */ - case 1: - case 2: - psdmr |= (1 << 15); - break; - case 3: - case 4: - case 5: - case 6: - case 7: - case 8: - psdmr |= ((tmp - 2) << 15); - break; - default: - psdmr |= (7 << 15); - } - psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */ - psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */ - /* BL=0 because for 64-bit SDRAM burst length must be 4 */ - /* LDOTOPRE ??? */ - for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++) - tmp >>= 1; - switch (i) { /* WRC */ - case 0: - case 1: - psdmr |= (1 << 4); - break; - case 2: - case 3: - psdmr |= (i << 4); - break; - } - /* EAMUX=0 - no external address multiplexing */ - /* BUFCMD=0 - no external buffers */ - for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++) - tmp >>= 1; - psdmr |= i; /* CL */ - - switch (spd.refresh & 0x7F) { - case 1: - tmp = 3900; - break; - case 2: - tmp = 7800; - break; - case 3: - tmp = 31300; - break; - case 4: - tmp = 62500; - break; - case 5: - tmp = 125000; - break; - default: - tmp = 15625; - } - psrt = tmp / (1000000000 / CONFIG_8260_CLKIN * - ((memctl->memc_mptpr >> 8) + 1)) - 1; -#ifdef SPD_DEBUG - printf ("\nDIMM type: %-18.18s\n", spd.mpart); - printf ("SPD size: %d\n", spd.info_size); - printf ("EEPROM size: %d\n", 1 << spd.chip_size); - printf ("Memory type: %d\n", spd.mem_type); - printf ("Row addr: %d\n", spd.nrow_addr); - printf ("Column addr: %d\n", spd.ncol_addr); - printf ("# of rows: %d\n", spd.nrows); - printf ("Row density: %d\n", spd.row_dens); - printf ("# of banks: %d\n", spd.nbanks); - printf ("Data width: %d\n", - 256 * spd.dataw_msb + spd.dataw_lsb); - printf ("Chip width: %d\n", spd.primw); - printf ("Refresh rate: %02X\n", spd.refresh); - printf ("CAS latencies: %02X\n", spd.cas_lat); - printf ("Write latencies: %02X\n", spd.write_lat); - printf ("tRP: %d\n", spd.trp); - printf ("tRCD: %d\n", spd.trcd); - - printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt); -#endif /* SPD_DEBUG */ - } -#else /* !CONFIG_SPD_EEPROM */ - or = CFG_OR2; - psdmr = CFG_PSDMR; - psrt = CFG_PSRT; -#endif /* CONFIG_SPD_EEPROM */ - memctl->memc_psrt = psrt; - memctl->memc_or2 = or; - memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041; - ramaddr = (uchar *) CFG_SDRAM_BASE; - memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */ - *ramaddr = c; -#endif /* CFG_RAMBOOT */ - - /* return total 60x bus SDRAM size */ - return (msize * 1024 * 1024); -} - -int checkboard (void) -{ -#if CONFIG_ADSTYPE == CFG_8260ADS - puts ("Board: Motorola MPC8260ADS\n"); -#elif CONFIG_ADSTYPE == CFG_8266ADS - puts ("Board: Motorola MPC8266ADS\n"); -#elif CONFIG_ADSTYPE == CFG_PQ2FADS - puts ("Board: Motorola PQ2FADS-ZU\n"); -#elif CONFIG_ADSTYPE == CFG_8272ADS - puts ("Board: Motorola MPC8272ADS\n"); -#else - puts ("Board: unknown\n"); -#endif - return 0; -} - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif diff --git a/board/mpc8260ads/u-boot.lds b/board/mpc8260ads/u-boot.lds deleted file mode 100644 index bf8048d..0000000 --- a/board/mpc8260ads/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Yuli Barcohen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/mpc8266ads/Makefile b/board/mpc8266ads/Makefile deleted file mode 100644 index cd0f40b..0000000 --- a/board/mpc8266ads/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mpc8266ads/config.mk b/board/mpc8266ads/config.mk deleted file mode 100644 index ecc2a7d..0000000 --- a/board/mpc8266ads/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8260ads board -# - -TEXT_BASE = 0xfe000000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/mpc8266ads/flash.c b/board/mpc8266ads/flash.c deleted file mode 100644 index 9512c72..0000000 --- a/board/mpc8266ads/flash.c +++ /dev/null @@ -1,509 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -#ifndef CONFIG_MPC8266ADS - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; -#endif - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ -#ifndef CONFIG_MPC8266ADS - bcsr->bd_ctrl |= BD_CTRL_FLWE; -#endif - - - for (i=0; imemc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) | - (memctl->memc_br1 & ~(BR_BA_MSK)); -#endif - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - - value = addr[0] & 0x00FF00FF; - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (INTEL_ID_28F016S): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F160S3): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F320S3): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - info->size = 0x00800000; - sector_offset = 0x20000; - break; /* => 2x4 MB */ - - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - info->sector_count = 32; - info->size = 0x00800000; - sector_offset = 0x40000; - break; /* => 4x2 MB */ - - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += sector_offset; - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - - *addr = 0xFFFFFF; /* reset bank to read array mode */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Reset Array */ - *addr = 0xffffffff; - /* Clear Status Register */ - *addr = 0x50505050; - /* Single Block Erase Command */ - *addr = 0x20202020; - /* Confirm */ - *addr = 0xD0D0D0D0; - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x80808080) != 0x80808080) { - if(*addr & 0x20202020){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - } - } - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - while (((csr = *addr) & 0x80808080) != 0x80808080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; - - /* Reset Array */ - *addr = 0xffffffff; - /* Clear Status Register */ - *addr = 0x50505050; - - *addr = 0x60606060; - *addr = 0xd0d0d0d0; - - start = get_timer (0); - while(*addr != 0x80808080){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - return 1; - } - } - return 0; -} diff --git a/board/mpc8266ads/mpc8266ads.c b/board/mpc8266ads/mpc8266ads.c deleted file mode 100644 index 8f7273c..0000000 --- a/board/mpc8266ads/mpc8266ads.c +++ /dev/null @@ -1,586 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified during 2001 by - * Advanced Communications Technologies (Australia) Pty. Ltd. - * Howard Walker, Tuong Vu-Dinh - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Added support for the 16M dram simm on the 8260ads boards - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -/* - * PBI Page Based Interleaving - * PSDMR_PBI page based interleaving - * 0 bank based interleaving - * External Address Multiplexing (EAMUX) adds a clock to address cycles - * (this can help with marginal board layouts) - * PSDMR_EAMUX adds a clock - * 0 no extra clock - * Buffer Command (BUFCMD) adds a clock to command cycles. - * PSDMR_BUFCMD adds a clock - * 0 no extra clock - */ -#define CONFIG_PBI 0 -#define PESSIMISTIC_SDRAM 0 -#define EAMUX 0 /* EST requires EAMUX */ -#define BUFCMD 0 - - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -typedef struct bscr_ { - unsigned long bcsr0; - unsigned long bcsr1; - unsigned long bcsr2; - unsigned long bcsr3; - unsigned long bcsr4; - unsigned long bcsr5; - unsigned long bcsr6; - unsigned long bcsr7; -} bcsr_t; - -typedef struct pci_ic_s { - unsigned long pci_int_stat; - unsigned long pci_int_mask; -} pci_ic_t; - -void reset_phy(void) -{ - volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; - - /* reset the FEC port */ - bcsr->bcsr1 &= ~FETH_RST; - bcsr->bcsr1 |= FETH_RST; -} - - -int board_early_init_f (void) -{ - volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; - volatile pci_ic_t *pci_ic = (pci_ic_t *) CFG_PCI_INT; - - bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2; - - /* mask all PCI interrupts */ - pci_ic->pci_int_mask |= 0xfff00000; - - return 0; -} - -int checkboard(void) -{ - puts ("Board: Motorola MPC8266ADS\n"); - return 0; -} - -long int initdram(int board_type) -{ - /* Autoinit part stolen from board/sacsng/sacsng.c */ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0xff; - volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8); - uint psdmr = CFG_PSDMR; - int i; - - uint psrt = 0x21; /* for no SPD */ - uint chipselects = 1; /* for no SPD */ - uint sdram_size = CFG_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CFG_OR2_PRELIM; /* for no SPD */ - uint data_width; - uint rows; - uint banks; - uint cols; - uint caslatency; - uint width; - uint rowst; - uint sdam; - uint bsma; - uint sda10; - u_char spd_size; - u_char data; - u_char cksum; - int j; - - /* Keep the compiler from complaining about potentially uninitialized vars */ - data_width = rows = banks = cols = caslatency = 0; - - /* - * Read the SDRAM SPD EEPROM via I2C. - */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - - i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); - spd_size = data; - cksum = data; - for(j = 1; j < 64; j++) - { /* read only the checksummed bytes */ - /* note: the I2C address autoincrements when alen == 0 */ - i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); - /*printf("addr %d = 0x%02x\n", j, data);*/ - if(j == 5) chipselects = data & 0x0F; - else if(j == 6) data_width = data; - else if(j == 7) data_width |= data << 8; - else if(j == 3) rows = data & 0x0F; - else if(j == 4) cols = data & 0x0F; - else if(j == 12) - { - /* - * Refresh rate: this assumes the prescaler is set to - * approximately 0.39uSec per tick and the target refresh period - * is about 85% of maximum. - */ - switch(data & 0x7F) - { - default: - case 0: psrt = 0x21; /* 15.625uS */ break; - case 1: psrt = 0x07; /* 3.9uS */ break; - case 2: psrt = 0x0F; /* 7.8uS */ break; - case 3: psrt = 0x43; /* 31.3uS */ break; - case 4: psrt = 0x87; /* 62.5uS */ break; - case 5: psrt = 0xFF; /* 125uS */ break; - } - } - else if(j == 17) banks = data; - else if(j == 18) - { - caslatency = 3; /* default CL */ -# if(PESSIMISTIC_SDRAM) - if((data & 0x04) != 0) caslatency = 3; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x01) != 0) caslatency = 1; -# else - if((data & 0x01) != 0) caslatency = 1; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x04) != 0) caslatency = 3; -# endif - else - { - printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n", - data); - } - } - else if(j == 63) - { - if(data != cksum) - { - printf ("WARNING: Configuration data checksum failure:" - " is 0x%02x, calculated 0x%02x\n", - data, cksum); - } - } - cksum += data; - } - - /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ - if(caslatency < 2) { - printf("CL was %d, forcing to 2\n", caslatency); - caslatency = 2; - } - if(rows > 14) { - printf("This doesn't look good, rows = %d, should be <= 14\n", rows); - rows = 14; - } - if(cols > 11) { - printf("This doesn't look good, columns = %d, should be <= 11\n", cols); - cols = 11; - } - - if((data_width != 64) && (data_width != 72)) - { - printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", - data_width); - } - width = 3; /* 2^3 = 8 bytes = 64 bits wide */ - /* - * Convert banks into log2(banks) - */ - if (banks == 2) banks = 1; - else if(banks == 4) banks = 2; - else if(banks == 8) banks = 3; - - - sdram_size = 1 << (rows + cols + banks + width); - /* hack for high density memory (512MB per CS) */ - /* !!!!! Will ONLY work with Page Based Interleave !!!!! - ( PSDMR[PBI] = 1 ) - */ - /* mamory actually has 11 column addresses, but the memory controller - doesn't really care. - the calculations that follow will however move the rows so that - they are muxed one bit off if you use 11 bit columns. - The solution is to tell the memory controller the correct size of the memory - but change the number of columns to 10 afterwards. - The 11th column addre will still be mucxed correctly onto the bus. - - Also be aware that the MPC8266ADS board Rev B has not connected - Row addres 13 to anything. - - The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126) - */ - if (cols > 10) - cols = 10; - -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - rowst = ((32 - 6) - (rows + cols + width)) * 2; -#else - rowst = 32 - (rows + banks + cols + width); -#endif - - or = ~(sdram_size - 1) | /* SDAM address mask */ - ((banks-1) << 13) | /* banks per device */ - (rowst << 9) | /* rowst */ - ((rows - 9) << 6); /* numr */ - - - /*printf("memctl->memc_or2 = 0x%08x\n", or);*/ - - /* - * SDAM specifies the number of columns that are multiplexed - * (reference AN2165/D), defined to be (columns - 6) for page - * interleave, (columns - 8) for bank interleave. - * - * BSMA is 14 - max(rows, cols). The bank select lines come - * into play above the highest "address" line going into the - * the SDRAM. - */ -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - sdam = cols - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam + 2; -#else - sdam = cols + banks - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam; -#endif -#if(PESSIMISTIC_SDRAM) - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_16_CLK |\ - PSDMR_PRETOACT_8W |\ - PSDMR_ACTTORW_8W |\ - PSDMR_WRC_4C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); -#else - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_WRC_1C | /* 1 clock + 7nSec */ - EAMUX |\ - BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); -#endif - /*printf("psdmr = 0x%08x\n", psdmr);*/ - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * Quote from Micron MT48LC8M16A2 data sheet: - * - * "...the SDRAM requires a 100uS delay prior to issuing any - * command other than a COMMAND INHIBIT or NOP. Starting at some - * point during this 100uS period and continuing at least through - * the end of this period, COMMAND INHIBIT or NOP commands should - * be applied." - * - * "Once the 100uS delay has been satisfied with at least one COMMAND - * INHIBIT or NOP command having been applied, a /PRECHARGE command/ - * should be applied. All banks must then be precharged, thereby - * placing the device in the all banks idle state." - * - * "Once in the idle state, /two/ AUTO REFRESH cycles must be - * performed. After the AUTO REFRESH cycles are complete, the - * SDRAM is ready for mode register programming." - * - * (/emphasis/ mine, gvb) - * - * The way I interpret this, Micron start up sequence is: - * 1. Issue a PRECHARGE-BANK command (initial precharge) - * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") - * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands - * 4. Issue a MODE-SET command to initialize the mode register - * - * -------- - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - memctl->memc_mptpr = CFG_MPTPR; - memctl->memc_psrt = psrt; - - memctl->memc_br2 = CFG_BR2_PRELIM; - memctl->memc_or2 = or; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* - * Do it a second time for the second set of chips if the DIMM has - * two chip selects (double sided). - */ - if(chipselects > 1) - { - ramaddr += sdram_size; - - memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size; - memctl->memc_or3 = or; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - } - - /* print info */ - printf("SDRAM configuration read from SPD\n"); - printf("\tSize per side = %dMB\n", sdram_size >> 20); - printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width); - printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency); -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - printf(", Using Bank Based Interleave\n"); -#else - printf(", Using Page Based Interleave\n"); -#endif - printf("\tTotal size: "); - - /* this delay only needed for original 16MB DIMM... - * Not needed for any other memory configuration */ - if ((sdram_size * chipselects) == (16 *1024 *1024)) - udelay (250000); - return (sdram_size * chipselects); - /*return (16 * 1024 * 1024);*/ -} - - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif diff --git a/board/mpc8266ads/u-boot.lds b/board/mpc8266ads/u-boot.lds deleted file mode 100644 index 2220758..0000000 --- a/board/mpc8266ads/u-boot.lds +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mpc8349ads/Makefile b/board/mpc8349ads/Makefile deleted file mode 100644 index 4327b0d..0000000 --- a/board/mpc8349ads/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mpc8349ads/config.mk b/board/mpc8349ads/config.mk deleted file mode 100644 index 4602169..0000000 --- a/board/mpc8349ads/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MPC83xxADS -# - -TEXT_BASE = 0xFE700000 diff --git a/board/mpc8349ads/mpc8349ads.c b/board/mpc8349ads/mpc8349ads.c deleted file mode 100644 index da8d3d7..0000000 --- a/board/mpc8349ads/mpc8349ads.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - */ - -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_PCI) -#include -#endif -#if defined(CONFIG_SPD_EEPROM) -#include -#endif -int fixed_sdram(void); -void sdram_init(void); - -int board_early_init_f (void) -{ - volatile u8* bcsr = (volatile u8*)CFG_BCSR; - - /* Enable flash write */ - bcsr[1] &= ~0x01; - - return 0; -} - - -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) - -long int initdram (int board_type) -{ - volatile immap_t *im = (immap_t *)CFG_IMMRBAR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(NULL); -#else - msize = fixed_sdram(); -#endif - /* - * Initialize SDRAM if it is on local bus. - */ - sdram_init(); - puts(" DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMRBAR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CFG_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 256) -#warning Currenly any ddr size other than 256 is not supported -#endif - - im->ddr.csbnds[0].csbnds = 0x00100017; - im->ddr.csbnds[1].csbnds = 0x0018001f; - im->ddr.csbnds[2].csbnds = 0x00000007; - im->ddr.csbnds[3].csbnds = 0x0008000f; - im->ddr.cs_config[0] = CFG_DDR_CONFIG; - im->ddr.cs_config[1] = CFG_DDR_CONFIG; - im->ddr.cs_config[2] = CFG_DDR_CONFIG; - im->ddr.cs_config[3] = CFG_DDR_CONFIG; - im->ddr.timing_cfg_1 = - 3 << TIMING_CFG1_PRETOACT_SHIFT | - 7 << TIMING_CFG1_ACTTOPRE_SHIFT | - 3 << TIMING_CFG1_ACTTORW_SHIFT | - 4 << TIMING_CFG1_CASLAT_SHIFT | - 3 << TIMING_CFG1_REFREC_SHIFT | - 3 << TIMING_CFG1_WRREC_SHIFT | - 2 << TIMING_CFG1_ACTTOACT_SHIFT | - 1 << TIMING_CFG1_WRTORD_SHIFT; - im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT; - im->ddr.sdram_cfg = - SDRAM_CFG_SREN -#if defined(CONFIG_DDR_2T_TIMING) - | SDRAM_CFG_2T_EN -#endif - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; - im->ddr.sdram_mode = - 0x2000 << SDRAM_MODE_ESD_SHIFT | - 0x0162 << SDRAM_MODE_SD_SHIFT; - - im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT | - 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT; - udelay(200); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} -#endif/*!CFG_SPD_EEPROM*/ - - -int checkboard (void) -{ - puts("Board: Freescale MPC8349ADS\n"); - return 0; -} - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxads_config_table[] = { - {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMON_MEMORY | PCI_COMMAND_MASTER - } }, - {} -} -#endif - - -volatile static struct pci_controller hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxads_config_table, -#endif - }, - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxads_config_table, -#endif - } -}; -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc83xx_init(volatile struct pci_controller *hose); - - pci_mpc83xx_init(hose); -#endif /* CONFIG_PCI */ -} - -/* - * if MPC8349ADS is soldered with SDRAM - */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) -/* - * Initialize SDRAM memory on the Local Bus. - */ - -void -sdram_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; - volatile lbus8349_t *lbc= &immap->lbus; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - - puts("\n SDRAM on Local Bus: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - - /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c - */ - - /*setup mtrpt, lsrt and lbcr for LB bus*/ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode Register. - */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/ - - lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/ - asm("sync"); - /*1 times*/ - *sdram_addr = 0xff; - udelay(100); - /*2 times*/ - *sdram_addr = 0xff; - udelay(100); - /*3 times*/ - *sdram_addr = 0xff; - udelay(100); - /*4 times*/ - *sdram_addr = 0xff; - udelay(100); - /*5 times*/ - *sdram_addr = 0xff; - udelay(100); - /*6 times*/ - *sdram_addr = 0xff; - udelay(100); - /*7 times*/ - *sdram_addr = 0xff; - udelay(100); - /*8 times*/ - *sdram_addr = 0xff; - udelay(100); - - /* 0x58636733;mode register write operation */ - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); -} -#else -void -sdram_init(void) -{ - put("SDRAM on Local Bus is NOT available!\n"); -} -#endif diff --git a/board/mpc8349ads/u-boot.lds b/board/mpc8349ads/u-boot.lds deleted file mode 100644 index 020cfa6..0000000 --- a/board/mpc8349ads/u-boot.lds +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc83xx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/mpc8540ads/Makefile b/board/mpc8540ads/Makefile deleted file mode 100644 index 5d8ea34..0000000 --- a/board/mpc8540ads/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o -SOBJS := init.o -#SOBJS := - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mpc8540ads/config.mk b/board/mpc8540ads/config.mk deleted file mode 100644 index 92f8931..0000000 --- a/board/mpc8540ads/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright 2004 Freescale Semiconductor. -# Modified by Xianghua Xiao, X.Xiao@motorola.com -# (C) Copyright 2002,Motorola Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8540ads board -# default CCARBAR is at 0xff700000 -# assume U-Boot is less than 0.5MB -# -TEXT_BASE = 0xfff80000 - -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1 -PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/mpc8540ads/init.S b/board/mpc8540ads/init.S deleted file mode 100644 index 242cb9f..0000000 --- a/board/mpc8540ads/init.S +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, sharen, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long TLB1_MAS0(1, 0, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long TLB1_MAS0(1, 5, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long TLB1_MAS0(1, 6, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) - .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - .long TLB1_MAS0(1, 8, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1, 9, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000), - 0,0,0,0,0,1,0,1,0,1) -#endif - - entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c deleted file mode 100644 index d0eb690..0000000 --- a/board/mpc8540ads/mpc8540ads.c +++ /dev/null @@ -1,344 +0,0 @@ - /* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -extern long int spd_sdram(void); - -void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void); - - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts("Board: ADS\n"); - -#ifdef CONFIG_PCI - printf(" PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf(" PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init(); - - return 0; -} - - -long int -initdram(int board_type) -{ - long dram_size = 0; - extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur= &immap->im_gur; - uint temp_ddrdll = 0; - - /* - * Work around to stabilize DDR DLL - */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * Initialize SDRAM. - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - - -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr(); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - - -/* - * Initialize SDRAM memory on the Local Bus. - */ - -void -sdram_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc= &immap->im_lbc; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - - puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - - /* - * Setup SDRAM Base and Option Registers - */ - lbc->or2 = CFG_OR2_PRELIM; - lbc->br2 = CFG_BR2_PRELIM; - lbc->lbcr = CFG_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; - asm("sync"); - - /* - * Configure the SDRAM controller. - */ - lbc->lsdmr = CFG_LBC_LSDMR_1; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_2; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_3; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_5; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); -} - - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) -{ - #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CFG_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CFG_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} diff --git a/board/mpc8540ads/u-boot.lds b/board/mpc8540ads/u-boot.lds deleted file mode 100644 index e7a88cf..0000000 --- a/board/mpc8540ads/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2002,2003, Motorola,Inc. - * Xianghua Xiao, X.Xiao@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - board/mpc8540ads/init.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc85xx/start.o (.text) - board/mpc8540ads/init.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile deleted file mode 100644 index 6f1995e..0000000 --- a/board/mpc8540eval/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o -#OBJS := $(BOARD).o flash.o $(BOARD)_slave.o -SOBJS := init.o -#SOBJS := - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mpc8540eval/config.mk b/board/mpc8540eval/config.mk deleted file mode 100644 index 68271bd..0000000 --- a/board/mpc8540eval/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# Modified by Xianghua Xiao, X.Xiao@motorola.com -# (C) Copyright 2002,Motorola Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# gda8540 board -# default CCARBAR is at 0xff700000 -# assume U-Boot is less than 0.5MB -# -#TEXT_BASE = 0x1000000 -TEXT_BASE = 0xfff80000 - - -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1 -PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/mpc8540eval/flash.c b/board/mpc8540eval/flash.c deleted file mode 100644 index 7300a04..0000000 --- a/board/mpc8540eval/flash.c +++ /dev/null @@ -1,892 +0,0 @@ -/* - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao,(X.Xiao@motorola.com) - * - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if !defined(CFG_NO_FLASH) - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/* - * The variable should be in the flash info structure. Since it - * is only used in this board specific file it is declared here. - * In the future I think an endian flag should be part of the - * flash_info_t structure. (Ron Alder) - */ -static ulong big_endian = 0; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_block (flash_info_t *info, uchar * src, ulong dest, ulong cnt); -static int write_short (flash_info_t *info, ulong dest, ushort data); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(flash_info_t *info, vu_long * addr); -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ - for (i=0; i= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - - /* only deal with 16 bit and 32 bit port width, 16bit chip */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value,va,vb,vc,vd; - ulong base = (ulong)addr; - ulong sector_offset; - -#ifdef DEBUG - printf("Check flash at 0x%08x\n",(uint)addr); -#endif - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - udelay(20); - asm("sync"); - -#ifndef CFG_FLASH_CFI - printf("Not define CFG_FLASH_CFI\n"); - return (0); -#else - value = addr[0]; - va=(value & 0xFF000000)>>24; - vb=(value & 0x00FF0000)>>16; - vc=(value & 0x0000FF00)>>8; - vd=(value & 0x000000FF); - if ((va==0) && (vb==0)) { - printf("cannot identify Flash\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - else if ((va==0) && (vb!=0)) { - big_endian = 1; - info->chipwidth = FLASH_CFI_BY16; - if(vb == vd) info->portwidth = FLASH_CFI_32BIT; - else info->portwidth = FLASH_CFI_16BIT; - } - else if ((va!=0) && (vb==0)) { - big_endian = 0; - info->chipwidth = FLASH_CFI_BY16; - if(va == vc) info->portwidth = FLASH_CFI_32BIT; - else info->portwidth = FLASH_CFI_16BIT; - } - else if ((va!=0) && (vb!=0)) { - big_endian = 1; /* no meaning for 8bit chip */ - info->chipwidth = FLASH_CFI_BY8; - if(va == vb) info->portwidth = FLASH_CFI_16BIT; - else info->portwidth = FLASH_CFI_8BIT; - } -#ifdef DEBUG - switch (info->portwidth) { - case FLASH_CFI_8BIT: - printf("port width is 8 bit.\n"); - break; - case FLASH_CFI_16BIT: - printf("port width is 16 bit, "); - break; - case FLASH_CFI_32BIT: - printf("port width is 32 bit, "); - break; - } - switch (info->chipwidth) { - case FLASH_CFI_BY16: - printf("chip width is 16 bit, "); - switch (big_endian) { - case 0: - printf("Little Endian.\n"); - break; - case 1: - printf("Big Endian.\n"); - break; - } - break; - } -#endif -#endif /*#ifdef CFG_FLASH_CFI*/ - - if (big_endian==0) value = (addr[0] & 0xFF000000) >>8; - else value = (addr[0] & 0x00FF0000); -#ifdef DEBUG - printf("manufacturer=0x%x\n",(uint)(value>>16)); -#endif - switch (value) { - case MT_MANUFACT & 0xFFFF0000: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU & 0xFFFF0000: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - if (info->portwidth==FLASH_CFI_16BIT) { - switch (big_endian) { - case 0: - value = (addr[0] & 0x0000FF00)>>8; - break; - case 1: - value = (addr[0] & 0x000000FF); - break; - } - } - else if (info->portwidth == FLASH_CFI_32BIT) { - switch (big_endian) { - case 0: - value = (addr[1] & 0x0000FF00)>>8; - break; - case 1: - value = (addr[1] & 0x000000FF); - break; - } - } - -#ifdef DEBUG - printf("deviceID=0x%x\n",(uint)value); -#endif - switch (value) { - case (INTEL_ID_28F016S & 0x0000FFFF): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - sector_offset = 0x10000; - break; /* => 2 MB */ - - case (INTEL_ID_28F160S3 & 0x0000FFFF): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - sector_offset = 0x10000; - break; /* => 2 MB */ - - case (INTEL_ID_28F320S3 & 0x0000FFFF): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - sector_offset = 0x10000; - break; /* => 4 MB */ - - case (INTEL_ID_28F640J3A & 0x0000FFFF): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - sector_offset = 0x20000; - break; /* => 8 MB */ - - case SHARP_ID_28F016SCL & 0x0000FFFF: - case SHARP_ID_28F016SCZ & 0x0000FFFF: - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - info->sector_count = 32; - sector_offset = 0x10000; - break; /* => 2 MB */ - - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - sector_offset = sector_offset * (info->portwidth / info->chipwidth); - info->size = info->sector_count * sector_offset; - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += sector_offset; - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - *addr = 0xFFFFFF; /* reset bank to read array mode */ - asm("sync"); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last, ready, erase_err_status; - - if (big_endian == 1) { - ready = 0x0080; - erase_err_status = 0x00a0; - } - else { - ready = 0x8000; - erase_err_status = 0xa000; - } - if ((info->portwidth / info->chipwidth)==2) { - ready += (ready <<16); - erase_err_status += (erase_err_status <<16); - } - -#ifdef DEBUG - printf ("\nReady flag is 0x%lx\nErase error flag is 0x%lx", ready, erase_err_status); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - printf("\nFlash Erase:\n"); -#endif - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit(info, (vu_long *)(info->start[s_first]))){ - return 1; - } - - /* Start erase on unprotected sectors */ -#if defined(DEBUG) - printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); -#endif - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr16 = (vu_short *)(info->start[sect]); - vu_long *addr = (vu_long *)(info->start[sect]); - printf("."); - switch (info->portwidth) { - case FLASH_CFI_16BIT: - asm("sync"); - last = start = get_timer (0); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - /* Reset Array */ - *addr16 = 0xffff; - asm("sync"); - /* Clear Status Register */ - *addr16 = 0x5050; - asm("sync"); - /* Single Block Erase Command */ - *addr16 = 0x2020; - asm("sync"); - /* Confirm */ - *addr16 = 0xD0D0; - asm("sync"); - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr16 = 0xD0D0; - asm("sync"); - } - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - /* wait at least 80us - let's wait 1 ms */ - *addr16 = 0x7070; - udelay (1000); - while ((*addr16 & ready) != ready) { - if((*addr16 & erase_err_status)== erase_err_status){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr16); - *addr16 = 0xFFFF; /* reset bank */ - asm("sync"); - return 1; - } - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr16 = 0xFFFF; /* reset bank */ - asm("sync"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - /* reset to read mode */ - *addr16 = 0xFFFF; - asm("sync"); - break; - case FLASH_CFI_32BIT: - asm("sync"); - last = start = get_timer (0); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - /* Single Block Erase Command */ - *addr = 0x20202020; - asm("sync"); - /* Confirm */ - *addr = 0xD0D0D0D0; - asm("sync"); - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - asm("sync"); - } - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - /* wait at least 80us - let's wait 1 ms */ - *addr = 0x70707070; - udelay (1000); - while ((*addr & ready) != ready) { - if((*addr & erase_err_status)==erase_err_status){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - /* reset to read mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - break; - } /* end switch */ - } /* end if */ - } /* end for */ - - printf ("flash erase done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -#define FLASH_BLOCK_SIZE 32 - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data, count, temp; -/* ulong temp[FLASH_BLOCK_SIZE/4];*/ - int i, l, rc; - - count = cnt; - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - cp = wp; - /* handle unaligned block bytes , flash block size = 16bytes */ - wp = (cp+FLASH_BLOCK_SIZE-1) & ~(FLASH_BLOCK_SIZE-1); - if ((wp-cp)>=cnt) { - if ((rc = write_block(info,src,cp,wp-cp)) !=0) - return (rc); - src += wp-cp; - cnt -= wp-cp; - } - /* handle aligned block bytes */ - temp = 0; - printf("\n"); - while ( cnt >= FLASH_BLOCK_SIZE) { - if ((rc = write_block(info,src,cp,FLASH_BLOCK_SIZE)) !=0) { - return (rc); - } - src += FLASH_BLOCK_SIZE; - cp += FLASH_BLOCK_SIZE; - cnt -= FLASH_BLOCK_SIZE; - if (((count-cnt)>>10)>temp) { - temp=(count-cnt)>>10; - printf("\r%d KB",temp); - } - } - printf("\n"); - wp = cp; - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} -#undef FLASH_BLOCK_SIZE - -/*----------------------------------------------------------------------- - * Write block to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * -1 Error - */ -static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt) -{ - vu_short *baddr, *addr = (vu_short *)dest; - ushort data; - ulong start, now, xsr,csr, ready; - int flag; - - if (cnt==0) return 0; - else if(cnt != (cnt& ~1)) return -1; - - /* Check if Flash is (sufficiently) erased */ - data = * src; - data = (data<<8) | *(src+1); - if ((*addr & data) != data) { - return (2); - } - if (big_endian == 1) { - ready = 0x0080; - } - else { - ready = 0x8000; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - do { - /* Write Command */ - *addr = 0xe8e8; - asm("sync"); - xsr = *addr; - asm("sync"); - } while (!(xsr & ready)); /*wait until read */ - /*write count=BLOCK SIZE -1 */ - data=(cnt>>1)-1; - data=(data<<8)|data; - *addr = data; /* word mode, cnt/2 */ - asm("sync"); - baddr = addr; - while(cnt) { - data = * src++; - data = (data<<8) | *src++; - asm("sync"); - *baddr = data; - asm("sync"); - ++baddr; - cnt = cnt -2; - } - *addr = 0xd0d0; /* confirm write */ - start = get_timer(0); - asm("sync"); - if (flag) - enable_interrupts(); - /* data polling for D7 */ - flag = 0; - while (((csr = *addr) & ready) != ready) { - if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x4040) { - printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - /* Clear Status Registers Command */ - *addr = 0x5050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFF; - asm("sync"); - return (flag); -} - - -/*----------------------------------------------------------------------- - * Write a short word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_short (flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *)dest; - ulong start, now, csr, ready; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x1010; - start = get_timer (0); - asm("sync"); - /* Write Data */ - *addr = data; - asm("sync"); - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - if (big_endian == 1) { - ready = 0x0080; - } - else { - ready = 0x8000; - } - /* data polling for D7 */ - flag = 0; - while (((csr = *addr) & ready) != ready) { - if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x4040) { - printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - /* Clear Status Registers Command */ - *addr = 0x5050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFF; - asm("sync"); - return (flag); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr, ready; - int flag=0; - - switch (info->portwidth) { - case FLASH_CFI_32BIT: - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if (big_endian == 1) { - ready = 0x0080; - } - else { - ready = 0x8000; - } - if ((info->portwidth / info->chipwidth)==2) { - ready += (ready <<16); - } - else { - ready = ready << 16; - } - /* Write Command */ - *addr = 0x10101010; - asm("sync"); - /* Write Data */ - *addr = data; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - while (((csr = *addr) & ready) != ready) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - /* Clear Status Registers Command */ - *addr = 0x50505050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - break; - case FLASH_CFI_16BIT: - flag = write_short (info, dest, (unsigned short) (data>>16)); - if (flag == 0) - flag = write_short (info, dest+2, (unsigned short) (data)); - break; - } - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(flash_info_t * info, vu_long * addr) -{ - ulong start, now, ready; - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - - *addr = 0x60606060; - asm("sync"); - *addr = 0xd0d0d0d0; - asm("sync"); - - - if (big_endian == 1) { - ready = 0x0080; - } - else { - ready = 0x8000; - } - if ((info->portwidth / info->chipwidth)==2) { - ready += (ready <<16); - } - else { - ready = ready << 16; - } -#ifdef DEBUG - printf ("%s: Ready flag is 0x%8lx\n", __FUNCTION__, ready); -#endif - *addr = 0x70707070; /* read status */ - start = get_timer (0); - while((*addr & ready) != ready){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - } - return 0; -} - -#endif /* !CFG_NO_FLASH */ diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S deleted file mode 100644 index 8c2ca65..0000000 --- a/board/mpc8540eval/init.S +++ /dev/null @@ -1,178 +0,0 @@ -/* -* Copyright (C) 2002,2003, Motorola Inc. -* Xianghua Xiao -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include -#include - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -/* TLB1 entries configuration: */ - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - .long 0x0a /* the following data table uses a few of 16 TLB entries */ - - .long TLB1_MAS0(1,1,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - #if defined(CFG_FLASH_PORT_WIDTH_16) - .long TLB1_MAS0(1,2,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) - .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,3,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) - .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1) - #else - .long TLB1_MAS0(1,2,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M) - .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,3,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - #endif - - #if !defined(CONFIG_SPD_EEPROM) - .long TLB1_MAS0(1,4,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) - .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,5,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0) - .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - #else - .long TLB1_MAS0(1,4,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,5,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - #endif - - .long TLB1_MAS0(1,6,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) - #if defined(CONFIG_RAM_AS_FLASH) - .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - #else - .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) - #endif - .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,7,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) - #ifdef CONFIG_L2_INIT_RAM - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0) - #else - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0) - #endif - .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,8,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,9,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) - .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - .long TLB1_MAS0(1,15,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - #else - .long TLB1_MAS0(1,15,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - #endif - entry_end - -/* LAW(Local Access Window) configuration: - * 0000_0000-0800_0000: DDR(128M) -or- larger - * f000_0000-f3ff_ffff: PCI(256M) - * f400_0000-f7ff_ffff: RapidIO(128M) - * f800_0000-ffff_ffff: localbus(128M) - * f800_0000-fbff_ffff: LBC SDRAM(64M) - * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M) - * fdf0_0000-fdff_ffff: CCSRBAR(1M) - * fe00_0000-ffff_ffff: Flash(32M) - * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access - * Window. - * Note: If flash is 8M at default position(last 8M),no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#if !defined(CONFIG_RAM_AS_FLASH) -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) -#else -#define LAWBAR2 0 -#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x03 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 - entry_end diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c deleted file mode 100644 index 3b3c8ed..0000000 --- a/board/mpc8540eval/mpc8540eval.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -extern long int spd_sdram (void); - -long int fixed_sdram (void); - -int board_pre_init (void) -{ -#if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; - - pci->peer &= 0xffffffdf; /* disable master abort */ -#endif - return 0; -} - -int checkboard (void) -{ - sys_info_t sysinfo; - - get_sys_info (&sysinfo); - - printf ("Board: Freescale MPC8540EVAL Board\n"); - printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); - printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000); - printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); - if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \ - || (CFG_LBC_LCRR & 0x0f) == 8) { - printf ("\tLBC: %lu MHz\n", - sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f)); - } else { - printf("\tLBC: unknown\n"); - } - printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n"); - return (0); -} - -long int initdram (int board_type) -{ - long dram_size = 0; - extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; -#if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc= &immap->im_lbc; - sys_info_t sysinfo; - uint temp_lbcdll = 0; -#endif -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur= &immap->im_gur; -#endif - -#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CFG_RAMBOOT) - return dram_size; -#endif - -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ - get_sys_info(&sysinfo); - /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; - } else { - lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; - udelay(200); - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; - asm("sync;isync;msync"); - } - lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ - lbc->br2 = CFG_BR2_PRELIM; - lbc->lbcr = CFG_LBC_LBCR; - lbc->lsdmr = CFG_LBC_LSDMR_1; - asm("sync"); - * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_2; - asm("sync"); - * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_3; - asm("sync"); - * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_5; - asm("sync"); - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - lbc->mrtpr = CFG_LBC_MRTPR; - asm("sync"); -#endif - -#if defined(CONFIG_DDR_ECC) - { - /* Initialize all of memory for ECC, then - * enable errors */ - uint *p = 0; - uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - dma_init(); - for (*p = 0; p < (uint *)(8 * 1024); p++) { - if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } - *p = (unsigned int)0xdeadbeef; - if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } - } - - /* 8K */ - dma_xfer((uint *)0x2000,0x2000,(uint *)0); - /* 16K */ - dma_xfer((uint *)0x4000,0x4000,(uint *)0); - /* 32K */ - dma_xfer((uint *)0x8000,0x8000,(uint *)0); - /* 64K */ - dma_xfer((uint *)0x10000,0x10000,(uint *)0); - /* 128k */ - dma_xfer((uint *)0x20000,0x20000,(uint *)0); - /* 256k */ - dma_xfer((uint *)0x40000,0x40000,(uint *)0); - /* 512k */ - dma_xfer((uint *)0x80000,0x80000,(uint *)0); - /* 1M */ - dma_xfer((uint *)0x100000,0x100000,(uint *)0); - /* 2M */ - dma_xfer((uint *)0x200000,0x200000,(uint *)0); - /* 4M */ - dma_xfer((uint *)0x400000,0x400000,(uint *)0); - - for (i = 1; i < dram_size / 0x800000; i++) { - dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); - } - - /* Enable errors for ECC */ - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - } -#endif - - return dram_size; -} - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) -{ -#ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; -#if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; -#endif - asm("sync;isync;msync"); - udelay(500); -#if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); -#else - ddr->sdram_cfg = CFG_DDR_CONTROL; -#endif - asm("sync; isync; msync"); - udelay(500); -#endif - return (CFG_SDRAM_SIZE * 1024 * 1024); -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/mpc8540eval/u-boot.lds b/board/mpc8540eval/u-boot.lds deleted file mode 100644 index 0755d01..0000000 --- a/board/mpc8540eval/u-boot.lds +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2002,2003, Motorola,Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Assumes that the size of u-boot is less than 512K and the - * start address is aligned on a 512K block. - * Boot page and reset vector is put at that end of the 512K block. */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc85xx/start.o (.text) - board/mpc8540eval/init.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); - - . = (. & 0xFFF80000) + 0x0007F000; - .bootpg : - { - cpu/mpc85xx/start.o (.bootpg) - board/mpc8540eval/init.o (.bootpg) - } = 0xffff - - . = (. & 0xFFF80000) + 0x0007FFFC; - .resetvec : - { - *(.resetvec) - } = 0xffff - -} diff --git a/board/mpc8560ads/Makefile b/board/mpc8560ads/Makefile deleted file mode 100644 index 5d8ea34..0000000 --- a/board/mpc8560ads/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o -SOBJS := init.o -#SOBJS := - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mpc8560ads/config.mk b/board/mpc8560ads/config.mk deleted file mode 100644 index 9aef2bb..0000000 --- a/board/mpc8560ads/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright 2004 Freescale Semiconductor. -# Modified by Xianghua Xiao, X.Xiao@motorola.com -# (C) Copyright 2002,2003 Motorola Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8560ads board -# default CCARBAR is at 0xff700000 -# assume U-Boot is less than 0.5MB -# -TEXT_BASE = 0xfff80000 - -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/mpc8560ads/init.S b/board/mpc8560ads/init.S deleted file mode 100644 index 242cb9f..0000000 --- a/board/mpc8560ads/init.S +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, sharen, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long TLB1_MAS0(1, 0, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long TLB1_MAS0(1, 5, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long TLB1_MAS0(1, 6, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) - .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - .long TLB1_MAS0(1, 8, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1, 9, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000), - 0,0,0,0,0,1,0,1,0,1) -#endif - - entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c deleted file mode 100644 index 25f69a0..0000000 --- a/board/mpc8560ads/mpc8560ads.c +++ /dev/null @@ -1,546 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -extern long int spd_sdram(void); - -void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void); - - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - - -/* - * MPC8560ADS Board Status & Control Registers - */ -typedef struct bcsr_ { - volatile unsigned char bcsr0; - volatile unsigned char bcsr1; - volatile unsigned char bcsr2; - volatile unsigned char bcsr3; - volatile unsigned char bcsr4; - volatile unsigned char bcsr5; -} bcsr_t; - - -int board_early_init_f (void) -{ - return 0; -} - -void reset_phy (void) -{ -#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ - volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR; -#endif - /* reset Giga bit Ethernet port if needed here */ - - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr->bcsr2 &= ~FETH2_RST; - udelay(2); - bcsr->bcsr2 |= FETH2_RST; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr->bcsr3 &= ~FETH3_RST; - udelay(2); - bcsr->bcsr3 |= FETH3_RST; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1 ETHERNET", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); -#endif /* CONFIG_MII */ -} - - -int checkboard (void) -{ - puts("Board: ADS\n"); - -#ifdef CONFIG_PCI - printf(" PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf(" PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init(); - - return 0; -} - - -long int -initdram(int board_type) -{ - long dram_size = 0; - extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur= &immap->im_gur; - uint temp_ddrdll = 0; - - /* - * Work around to stabilize DDR DLL - */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * Initialize SDRAM. - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - - -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr(); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - - -/* - * Initialize SDRAM memory on the Local Bus. - */ - -void -sdram_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc= &immap->im_lbc; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - - puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - - /* - * Setup SDRAM Base and Option Registers - */ - lbc->or2 = CFG_OR2_PRELIM; - lbc->br2 = CFG_BR2_PRELIM; - lbc->lbcr = CFG_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; - asm("sync"); - - /* - * Configure the SDRAM controller. - */ - lbc->lsdmr = CFG_LBC_LSDMR_1; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_2; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_3; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_5; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); -} - - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) -{ - #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CFG_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CFG_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} diff --git a/board/mpc8560ads/u-boot.lds b/board/mpc8560ads/u-boot.lds deleted file mode 100644 index 8dcee1f..0000000 --- a/board/mpc8560ads/u-boot.lds +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2002,2003,Motorola,Inc. - * Xianghua Xiao, X.Xiao@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - board/mpc8560ads/init.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc85xx/start.o (.text) - board/mpc8560ads/init.o (.text) - cpu/mpc85xx/commproc.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/serial_scc.o (.text) - cpu/mpc85xx/ether_fcc.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/i2c.o (.text) - cpu/mpc85xx/spd_sdram.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c deleted file mode 100644 index b331d6e..0000000 --- a/board/mpl/common/common_util.c +++ /dev/null @@ -1,674 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include -#include "common_util.h" -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_PIP405 -#include "../pip405/pip405.h" -#include <405gp_pci.h> -#endif -#ifdef CONFIG_MIP405 -#include "../mip405/mip405.h" -#include <405gp_pci.h> -#endif -#if defined(CONFIG_PATI) -#define FIRM_START 0xFFF00000 -#endif - -extern int gunzip(void *, int, uchar *, unsigned long *); -extern int mem_test(ulong start, ulong ramsize, int quiet); - -#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */ -#define IMAGE_SIZE CFG_MONITOR_LEN /* ugly, but it works for now */ - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -static image_header_t header; - - -static int -mpl_prg(uchar *src, ulong size) -{ - ulong start; - flash_info_t *info; - int i, rc; -#if defined(CONFIG_PATI) - int start_sect; -#endif -#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI) - char *copystr = (char *)src; - ulong *magic = (ulong *)src; -#endif - - info = &flash_info[0]; - -#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI) - if (ntohl(magic[0]) != IH_MAGIC) { - puts("Bad Magic number\n"); - return -1; - } - /* some more checks before we delete the Flash... */ - /* Checking the ISO_STRING prevents to program a - * wrong Firmware Image into the flash. - */ - i = 4; /* skip Magic number */ - while (1) { - if (strncmp(©str[i], "MEV-", 4) == 0) - break; - if (i++ >= 0x100) { - puts("Firmware Image for unknown Target\n"); - return -1; - } - } - /* we have the ISO STRING, check */ - if (strncmp(©str[i], CONFIG_ISO_STRING, sizeof(CONFIG_ISO_STRING)-1) != 0) { - printf("Wrong Firmware Image: %s\n", ©str[i]); - return -1; - } -#if !defined(CONFIG_PATI) - start = 0 - size; - for (i = info->sector_count-1; i > 0; i--) { - info->protect[i] = 0; /* unprotect this sector */ - if (start >= info->start[i]) - break; - } - /* set-up flash location */ - /* now erase flash */ - printf("Erasing at %lx (sector %d) (start %lx)\n", - start,i,info->start[i]); - if ((rc = flash_erase (info, i, info->sector_count-1)) != 0) { - puts("ERROR "); - flash_perror(rc); - return (1); - } - -#else /* #if !defined(CONFIG_PATI */ - start = FIRM_START; - start_sect = -1; - for (i = 0; i < info->sector_count; i++) { - if (start < info->start[i]) { - start_sect = i - 1; - break; - } - } - - info->protect[i - 1] = 0; /* unprotect this sector */ - for (; i < info->sector_count; i++) { - if ((start + size) < info->start[i]) - break; - info->protect[i] = 0; /* unprotect this sector */ - } - - i--; - /* set-up flash location */ - /* now erase flash */ - printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n", - start, start + size, start_sect, i, - info->start[start_sect], info->start[i]); - if ((rc = flash_erase (info, start_sect, i)) != 0) { - puts ("ERROR "); - flash_perror (rc); - return (1); - } -#endif /* defined(CONFIG_PATI) */ - -#elif defined(CONFIG_VCMA9) - start = 0; - for (i = 0; i sector_count; i++) { - info->protect[i] = 0; /* unprotect this sector */ - if (size < info->start[i]) - break; - } - /* set-up flash location */ - /* now erase flash */ - printf("Erasing at %lx (sector %d) (start %lx)\n", - start,0,info->start[0]); - if ((rc = flash_erase (info, 0, i)) != 0) { - puts("ERROR "); - flash_perror(rc); - return (1); - } - -#endif - printf("flash erased, programming from 0x%lx 0x%lx Bytes\n", - (ulong)src, size); - if ((rc = flash_write ((char *)src, start, size)) != 0) { - puts("ERROR "); - flash_perror(rc); - return (1); - } - puts("OK programming done\n"); - return 0; -} - - -static int -mpl_prg_image(uchar *ld_addr) -{ - unsigned long len, checksum; - uchar *data; - image_header_t *hdr = &header; - int rc; - - /* Copy header so we can blank CRC field for re-calculation */ - memcpy (&header, (char *)ld_addr, sizeof(image_header_t)); - if (ntohl(hdr->ih_magic) != IH_MAGIC) { - puts("Bad Magic Number\n"); - return 1; - } - print_image_hdr(hdr); - if (hdr->ih_os != IH_OS_U_BOOT) { - puts("No U-Boot Image\n"); - return 1; - } - if (hdr->ih_type != IH_TYPE_FIRMWARE) { - puts("No Firmware Image\n"); - return 1; - } - data = (uchar *)&header; - len = sizeof(image_header_t); - checksum = ntohl(hdr->ih_hcrc); - hdr->ih_hcrc = 0; - if (crc32 (0, (uchar *)data, len) != checksum) { - puts("Bad Header Checksum\n"); - return 1; - } - data = ld_addr + sizeof(image_header_t); - len = ntohl(hdr->ih_size); - puts("Verifying Checksum ... "); - if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) { - puts("Bad Data CRC\n"); - return 1; - } - puts("OK\n"); - - if (hdr->ih_comp != IH_COMP_NONE) { - uchar *buf; - /* reserve space for uncompressed image */ - if ((buf = malloc(IMAGE_SIZE)) == NULL) { - puts("Insufficient space for decompression\n"); - return 1; - } - - switch (hdr->ih_comp) { - case IH_COMP_GZIP: - puts("Uncompressing (GZIP) ... "); - rc = gunzip ((void *)(buf), IMAGE_SIZE, data, &len); - if (rc != 0) { - puts("GUNZIP ERROR\n"); - free(buf); - return 1; - } - puts("OK\n"); - break; -#ifdef CONFIG_BZIP2 - case IH_COMP_BZIP2: - puts("Uncompressing (BZIP2) ... "); - { - uint retlen = IMAGE_SIZE; - rc = BZ2_bzBuffToBuffDecompress ((char *)(buf), &retlen, - (char *)data, len, 0, 0); - len = retlen; - } - if (rc != BZ_OK) { - printf ("BUNZIP2 ERROR: %d\n", rc); - free(buf); - return 1; - } - puts("OK\n"); - break; -#endif - default: - printf ("Unimplemented compression type %d\n", hdr->ih_comp); - free(buf); - return 1; - } - - rc = mpl_prg(buf, len); - free(buf); - } else { - rc = mpl_prg(data, len); - } - - return(rc); -} - -#if !defined(CONFIG_PATI) -void get_backup_values(backup_t *buf) -{ - i2c_read(CFG_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t)); -} - -void set_backup_values(int overwrite) -{ - backup_t back; - int i; - - get_backup_values(&back); - if(!overwrite) { - if(strncmp(back.signature,"MPL\0",4)==0) { - puts("Not possible to write Backup\n"); - return; - } - } - memcpy(back.signature,"MPL\0",4); - i = getenv_r("serial#",back.serial_name,16); - if(i < 0) { - puts("Not possible to write Backup\n"); - return; - } - back.serial_name[16]=0; - i = getenv_r("ethaddr",back.eth_addr,20); - if(i < 0) { - puts("Not possible to write Backup\n"); - return; - } - back.eth_addr[20]=0; - i2c_write(CFG_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t)); -} - -void clear_env_values(void) -{ - backup_t back; - unsigned char env_crc[4]; - - memset(&back,0xff,sizeof(backup_t)); - memset(env_crc,0x00,4); - i2c_write(CFG_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t)); - i2c_write(CFG_DEF_EEPROM_ADDR,CFG_ENV_OFFSET,2,(void *)env_crc,4); -} - -/* - * check crc of "older" environment - */ -int check_env_old_size(ulong oldsize) -{ - ulong crc, len, new; - unsigned off; - uchar buf[64]; - - /* read old CRC */ - eeprom_read (CFG_DEF_EEPROM_ADDR, - CFG_ENV_OFFSET, - (uchar *)&crc, sizeof(ulong)); - - new = 0; - len = oldsize; - off = sizeof(long); - len = oldsize-off; - while (len > 0) { - int n = (len > sizeof(buf)) ? sizeof(buf) : len; - - eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, buf, n); - new = crc32 (new, buf, n); - len -= n; - off += n; - } - - return (crc == new); -} - -static ulong oldsizes[] = { - 0x200, - 0x800, - 0 -}; - -void copy_old_env(ulong size) -{ - uchar name_buf[64]; - uchar value_buf[0x800]; - uchar c; - ulong len; - unsigned off; - uchar *name, *value; - - name=&name_buf[0]; - value=&value_buf[0]; - len=size; - off = sizeof(long); - while (len > off) { - eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, &c, 1); - if(c != '=') { - *name++=c; - off++; - } - else { - *name++='\0'; - off++; - do { - eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, &c, 1); - *value++=c; - off++; - if(c == '\0') - break; - } while(len > off); - name=&name_buf[0]; - value=&value_buf[0]; - if(strncmp((char *)name,"baudrate",8)!=0) { - setenv((char *)name,(char *)value); - } - - } - } -} - - -void check_env(void) -{ - char *s; - int i=0; - char buf[32]; - backup_t back; - - s=getenv("serial#"); - if(!s) { - while(oldsizes[i]) { - if(check_env_old_size(oldsizes[i])) - break; - i++; - } - if(!oldsizes[i]) { - /* no old environment has been found */ - get_backup_values (&back); - if (strncmp (back.signature, "MPL\0", 4) == 0) { - sprintf (buf, "%s", back.serial_name); - setenv ("serial#", buf); - sprintf (buf, "%s", back.eth_addr); - setenv ("ethaddr", buf); - printf ("INFO: serial# and ethaddr recovered, use saveenv\n"); - return; - } - } - else { - copy_old_env(oldsizes[i]); - puts("INFO: old environment ajusted, use saveenv\n"); - } - } - else { - /* check if back up is set */ - get_backup_values(&back); - if(strncmp(back.signature,"MPL\0",4)!=0) { - set_backup_values(0); - } - } -} - - -extern device_t *stdio_devices[]; -extern char *stdio_names[]; - -void show_stdio_dev(void) -{ - /* Print information */ - puts("In: "); - if (stdio_devices[stdin] == NULL) { - puts("No input devices available!\n"); - } else { - printf ("%s\n", stdio_devices[stdin]->name); - } - - puts("Out: "); - if (stdio_devices[stdout] == NULL) { - puts("No output devices available!\n"); - } else { - printf ("%s\n", stdio_devices[stdout]->name); - } - - puts("Err: "); - if (stdio_devices[stderr] == NULL) { - puts("No error devices available!\n"); - } else { - printf ("%s\n", stdio_devices[stderr]->name); - } -} - -#endif /* #if !defined(CONFIG_PATI) */ - -int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong size,src,ld_addr; - int result; -#if !defined(CONFIG_PATI) - backup_t back; - src = MULTI_PURPOSE_SOCKET_ADDR; - size = IMAGE_SIZE; -#endif - - if (strcmp(argv[1], "flash") == 0) - { -#if (CONFIG_COMMANDS & CFG_CMD_FDC) - if (strcmp(argv[2], "floppy") == 0) { - char *local_args[3]; - extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]); - puts("\nupdating bootloader image from floppy\n"); - local_args[0] = argv[0]; - if(argc==4) { - local_args[1] = argv[3]; - local_args[2] = NULL; - ld_addr=simple_strtoul(argv[3], NULL, 16); - result=do_fdcboot(cmdtp, 0, 2, local_args); - } - else { - local_args[1] = NULL; - ld_addr=CFG_LOAD_ADDR; - result=do_fdcboot(cmdtp, 0, 1, local_args); - } - result=mpl_prg_image((uchar *)ld_addr); - return result; - } -#endif /* (CONFIG_COMMANDS & CFG_CMD_FDC) */ - if (strcmp(argv[2], "mem") == 0) { - if(argc==4) { - ld_addr=simple_strtoul(argv[3], NULL, 16); - } - else { - ld_addr=load_addr; - } - printf ("\nupdating bootloader image from memory at %lX\n",ld_addr); - result=mpl_prg_image((uchar *)ld_addr); - return result; - } -#if !defined(CONFIG_PATI) - if (strcmp(argv[2], "mps") == 0) { - puts("\nupdating bootloader image from MPS\n"); - result=mpl_prg((uchar *)src,size); - return result; - } -#endif /* #if !defined(CONFIG_PATI) */ - } - if (strcmp(argv[1], "mem") == 0) - { - result=0; - if(argc==3) - { - result = (int)simple_strtol(argv[2], NULL, 16); - } - src=(unsigned long)&result; - src-=CFG_MEMTEST_START; - src-=(100*1024); /* - 100k */ - src&=0xfff00000; - size=0; - do { - size++; - printf("\n\nPass %ld\n",size); - mem_test(CFG_MEMTEST_START,src,1); - if(ctrlc()) - break; - if(result>0) - result--; - - }while(result); - return 0; - } -#if !defined(CONFIG_PATI) - if (strcmp(argv[1], "clearenvvalues") == 0) - { - if (strcmp(argv[2], "yes") == 0) - { - clear_env_values(); - return 0; - } - } - if (strcmp(argv[1], "getback") == 0) { - get_backup_values(&back); - back.signature[3]=0; - back.serial_name[16]=0; - back.eth_addr[20]=0; - printf("GetBackUp: signature: %s\n",back.signature); - printf(" serial#: %s\n",back.serial_name); - printf(" ethaddr: %s\n",back.eth_addr); - return 0; - } - if (strcmp(argv[1], "setback") == 0) { - set_backup_values(1); - return 0; - } -#endif - printf("Usage:\n%s\n", cmdtp->usage); - return 1; -} - - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -extern void doc_probe(ulong physadr); -void doc_init (void) -{ - doc_probe(MULTI_PURPOSE_SOCKET_ADDR); -} -#endif - - -#ifdef CONFIG_VIDEO -/****************************************************** - * Routines to display the Board information - * to the screen (since the VGA will be initialized as last, - * we must resend the infos) - */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -extern GraphicDevice ctfb; -extern int get_boot_mode(void); - -void video_get_info_str (int line_number, char *info) -{ - /* init video info strings for graphic console */ - DECLARE_GLOBAL_DATA_PTR; - PPC405_SYS_INFO sys_info; - char rev; - int i,boot; - unsigned long pvr; - char buf[64]; - char tmp[16]; - char cpustr[16]; - char *s, *e, bc; - switch (line_number) - { - case 2: - /* CPU and board infos */ - pvr=get_pvr(); - get_sys_info (&sys_info); - switch (pvr) { - case PVR_405GP_RB: rev='B'; break; - case PVR_405GP_RC: rev='C'; break; - case PVR_405GP_RD: rev='D'; break; - case PVR_405GP_RE: rev='E'; break; - case PVR_405GPR_RB: rev='B'; break; - default: rev='?'; break; - } - if(pvr==PVR_405GPR_RB) - sprintf(cpustr,"PPC405GPr %c",rev); - else - sprintf(cpustr,"PPC405GP %c",rev); - /* Board info */ - i=0; - s=getenv ("serial#"); -#ifdef CONFIG_PIP405 - if (!s || strncmp (s, "PIP405", 6)) { - sprintf(buf,"### No HW ID - assuming PIP405"); - } -#endif -#ifdef CONFIG_MIP405 - if (!s || strncmp (s, "MIP405", 6)) { - sprintf(buf,"### No HW ID - assuming MIP405"); - } -#endif - else { - for (e = s; *e; ++e) { - if (*e == ' ') - break; - } - for (; s < e; ++s) { - if (*s == '_') { - ++s; - break; - } - buf[i++]=*s; - } - sprintf(&buf[i]," SN "); - i+=4; - for (; s < e; ++s) { - buf[i++]=*s; - } - buf[i++]=0; - } - sprintf (info," %s %s %s MHz (%lu/%lu/%lu MHz)", - buf, cpustr, - strmhz (tmp, gd->cpu_clk), sys_info.freqPLB / 1000000, - sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, - sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000); - return; - case 3: - /* Memory Info */ - boot = get_boot_mode(); - bc = in8 (CONFIG_PORT_ADDR); - sprintf(info, " %luMB RAM, %luMB Flash Cfg 0x%02X %s %s", - gd->bd->bi_memsize / 0x100000, - gd->bd->bi_flashsize / 0x100000, - bc, - (boot & BOOT_MPS) ? "MPS boot" : "Flash boot", - ctfb.modeIdent); - return; - case 1: - sprintf (buf, "%s",CONFIG_IDENT_STRING); - sprintf (info, " %s", &buf[1]); - return; - } - /* no more info lines */ - *info = 0; - return; -} -#endif /* CONFIG_CONSOLE_EXTRA_INFO */ - -#endif /* CONFIG_VIDEO */ diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h deleted file mode 100644 index 8f2ec03..0000000 --- a/board/mpl/common/common_util.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -#ifndef _COMMON_UTIL_H_ -#define _COMMON_UTIL_H_ - -typedef struct { - char signature[4]; - char serial_name[17]; /* "MIP405_1000xxxxx" */ - char eth_addr[21]; /* "00:60:C2:0a:00:00" */ -} backup_t; - -void get_backup_values(backup_t *buf); - -#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) -#define BOOT_MPS 0x01 -#define BOOT_PCI 0x02 -#endif - -void show_stdio_dev(void); -void check_env(void); -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -void doc_init (void); -#endif - -#endif /* _COMMON_UTIL_H_ */ diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c deleted file mode 100644 index fd43008..0000000 --- a/board/mpl/common/flash.c +++ /dev/null @@ -1,882 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -/* - * Modified 3/7/2001 - * - adapted for pip405, Denis Peter, MPL AG Switzerland - * TODO: - * clean-up - */ - -#include - -#if !defined(CONFIG_PATI) -#include -#include -#include "common_util.h" -#if defined(CONFIG_MIP405) -#include "../mip405/mip405.h" -#endif -#if defined(CONFIG_PIP405) -#include "../pip405/pip405.h" -#endif -#include <405gp_pci.h> -#else /* defined(CONFIG_PATI) */ -#include -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned short - -#define FALSE 0 -#define TRUE 1 - -#if !defined(CONFIG_PATI) - -/*----------------------------------------------------------------------- - * Some CS switching routines: - * - * On PIP/MIP405 we have 3 (4) possible boot mode - * - * - Boot from Flash (Flash CS = CS0, MPS CS = CS1) - * - Boot from MPS (Flash CS = CS1, MPS CS = CS0) - * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1) - * - Boot from PCI with MPS map (Flash CS = CS1, MPS CS = CS0) - * The flash init is the first board specific routine which is called - * after code relocation (running from SDRAM) - * The first thing we do is to map the Flash CS to the Flash area and - * the MPS CS to the MPS area. Since the flash size is unknown at this - * point, we use the max flash size and the lowest flash address as base. - * - * After flash detection we adjust the size of the CS area accordingly. - * The board_init_r will fill in wrong values in the board init structure, - * but this will be fixed in the misc_init_r routine: - * bd->bi_flashstart=0-flash_info[0].size - * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN - * bd->bi_flashoffset=0 - * - */ -int get_boot_mode(void) -{ - unsigned long pbcr; - int res = 0; - pbcr = mfdcr (strap); - if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) - /* boot via MPS or MPS mapping */ - res = BOOT_MPS; - if(pbcr & PSR_ROM_LOC) - /* boot via PCI.. */ - res |= BOOT_PCI; - return res; -} - -/* Map the flash high (in boot area) - This code can only be executed from SDRAM (after relocation). -*/ -void setup_cs_reloc(void) -{ - int mode; - /* Since we are relocated, we can set-up the CS finaly - * but first of all, switch off PCI mapping (in case it was a PCI boot) */ - out32r(PMM0MA,0L); - icache_enable (); /* we are relocated */ - /* get boot mode */ - mode=get_boot_mode(); - /* we map the flash high in every case */ - /* first findout on which cs the flash is */ - if(mode & BOOT_MPS) { - /* map flash high on CS1 and MPS on CS0 */ - mtdcr (ebccfga, pb0ap); - mtdcr (ebccfgd, MPS_AP); - mtdcr (ebccfga, pb0cr); - mtdcr (ebccfgd, MPS_CR); - /* we use the default values (max values) for the flash - * because its real size is not yet known */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, FLASH_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, FLASH_CR_B); - } - else { - /* map flash high on CS0 and MPS on CS1 */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, MPS_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, MPS_CR); - /* we use the default values (max values) for the flash - * because its real size is not yet known */ - mtdcr (ebccfga, pb0ap); - mtdcr (ebccfgd, FLASH_AP); - mtdcr (ebccfga, pb0cr); - mtdcr (ebccfgd, FLASH_CR_B); - } -} - -#endif /* #if !defined(CONFIG_PATI) */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - -#if !defined(CONFIG_PATI) - unsigned long size_b1,flashcr,size_reg; - int mode; - extern char version_string; - char *p=&version_string; - - /* Since we are relocated, we can set-up the CS finally */ - setup_cs_reloc(); - /* get and display boot mode */ - mode=get_boot_mode(); - if(mode & BOOT_PCI) - printf("(PCI Boot %s Map) ",(mode & BOOT_MPS) ? - "MPS" : "Flash"); - else - printf("(%s Boot) ",(mode & BOOT_MPS) ? - "MPS" : "Flash"); -#endif /* #if !defined(CONFIG_PATI) */ - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif -#if !defined(CONFIG_PATI) - /* protect reset vector */ - flash_info[0].protect[flash_info[0].sector_count-1] = 1; - size_b1 = 0 ; - flash_info[0].size = size_b0; - /* set up flash cs according to the size */ - size_reg=(flash_info[0].size >>20); - switch (size_reg) { - case 0: - case 1: i=0; break; /* <= 1MB */ - case 2: i=1; break; /* = 2MB */ - case 4: i=2; break; /* = 4MB */ - case 8: i=3; break; /* = 8MB */ - case 16: i=4; break; /* = 16MB */ - case 32: i=5; break; /* = 32MB */ - case 64: i=6; break; /* = 64MB */ - case 128: i=7; break; /*= 128MB */ - default: - printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg); - while(1); - } - if(mode & BOOT_MPS) { - /* flash is on CS1 */ - mtdcr(ebccfga, pb1cr); - flashcr = mfdcr (ebccfgd); - /* we map the flash high in every case */ - flashcr&=0x0001FFFF; /* mask out address bits */ - flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ - flashcr|= (i << 17); /* size addr */ - mtdcr(ebccfga, pb1cr); - mtdcr(ebccfgd, flashcr); - } - else { - /* flash is on CS0 */ - mtdcr(ebccfga, pb0cr); - flashcr = mfdcr (ebccfgd); - /* we map the flash high in every case */ - flashcr&=0x0001FFFF; /* mask out address bits */ - flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ - flashcr|= (i << 17); /* size addr */ - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, flashcr); - } -#if 0 - /* enable this (PIP405/MIP405 only) if you want to test if - the relocation has be done ok. - This will disable both Chipselects */ - mtdcr (ebccfga, pb0cr); - mtdcr (ebccfgd, 0L); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, 0L); - printf("CS0 & CS1 switched off for test\n"); -#endif - /* patch version_string */ - for(i=0;i<0x100;i++) { - if(*p=='\n') { - *p=0; - break; - } - p++; - } -#else /* #if !defined(CONFIG_PATI) */ -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif -#endif /* #if !defined(CONFIG_PATI) */ - return (size_b0); -} - - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_INTEL320T: printf ("TE28F320C3 (32 Mbit, top sector size)\n"); - break; - case FLASH_AM640U: printf ("AM29LV640U (64 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - -*/ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - - value = addr2[0]; - /* printf("flash_get_size value: %x\n",value); */ - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - case (FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - value = addr2[1]; /* device ID */ - /* printf("Device value %x\n",value); */ - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - case (FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - case (FLASH_WORD_SIZE)AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000; - break; /* => 8 MB */ -#if 0 /* enable when device IDs are available */ - - case (FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - case (FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - case (FLASH_WORD_SIZE)INTEL_ID_28F320C3T: - info->flash_id += FLASH_INTEL320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - - - case (FLASH_WORD_SIZE)SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* base address calculation */ - base=0-info->size; - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040) || - (info->flash_id == FLASH_AM640U)){ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - if(info->sector_count==71) { - - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) - info->start[i] = base + i * 0x000010000; - } - else { - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - return (info->size); -} - - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return ERR_OK; -} - -int intel_wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last, status; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - status = addr[0] & (FLASH_WORD_SIZE)0x00280028; - /* clear status register */ - addr[0] = (FLASH_WORD_SIZE)0x00500050; - /* check status for block erase fail and VPP low */ - return (status == 0 ? ERR_OK : ERR_NOT_ERASED); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i, rcode = 0; - - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - /* printf("Erasing sector %p\n", addr2); */ /* CLH */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - rcode |= wait_for_DQ7(info, sect); - } - else { - if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ - addr2[0] = (FLASH_WORD_SIZE)0x00600060; /* unlock sector */ - addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* sector erase */ - intel_wait_for_DQ7(info, sect); - addr2[0] = (FLASH_WORD_SIZE)0x00200020; /* sector erase */ - addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* sector erase */ - rcode |= intel_wait_for_DQ7(info, sect); - } - else { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - rcode |= wait_for_DQ7(info, sect); - } - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - /* wait_for_DQ7(info, sect); */ - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7(info, l_sect); - -DONE: -#endif - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - if (!rcode) - printf (" done\n"); - - return rcode; -} - - -void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt) -{ - int i; - volatile FLASH_WORD_SIZE *addr2; - long c; - c= (long)cnt; - for(i=info->sector_count-1;i>0;i--) - { - if(addr>=info->start[i]) - break; - } - do { - addr2 = (FLASH_WORD_SIZE *)(info->start[i]); - addr2[0] = (FLASH_WORD_SIZE)0x00600060; /* unlock sector setup */ - addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* unlock sector */ - intel_wait_for_DQ7(info, i); - i++; - c-=(info->start[i]-info->start[i-1]); - }while(c>0); -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ - unlock_intel_sectors(info,addr,cnt); - } - wp = (addr & ~3); /* get lower word aligned address */ - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - if((wp % 0x10000)==0) - printf("."); /* show Progress */ - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - rc=write_word(info, wp, data); - return rc; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static FLASH_WORD_SIZE *read_val = (FLASH_WORD_SIZE *)0x200000; - -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *)dest) & - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ - /* intel style writting */ - dest2[i] = (FLASH_WORD_SIZE)0x00500050; - dest2[i] = (FLASH_WORD_SIZE)0x00400040; - *read_val++ = data2[i]; - dest2[i] = data2[i]; - if (flag) - enable_interrupts(); - /* data polling for D7 */ - start = get_timer (0); - udelay(10); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) - { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) - return (1); - } - dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */ - udelay(10); - dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */ - if(dest2[i]!=data2[i]) - printf("Error at %p 0x%04X != 0x%04X\n",&dest2[i],dest2[i],data2[i]); - } - else { - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - dest2[i] = data2[i]; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c deleted file mode 100644 index 51b2773..0000000 --- a/board/mpl/common/isa.c +++ /dev/null @@ -1,494 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - * TODO: clean-up - */ - -#include -#include -#include -#include "isa.h" -#include "piix4_pci.h" -#include "kbd.h" -#include "video.h" - - -#undef ISA_DEBUG - -#ifdef ISA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -#if defined(CONFIG_PIP405) - -extern int drv_isa_kbd_init (void); - -/* fdc (logical device 0) */ -const SIO_LOGDEV_TABLE sio_fdc[] = { - {0x60, 3}, /* set IO to FDPort (3F0) */ - {0x61, 0xF0}, /* set IO to FDPort (3F0) */ - {0x70, 06}, /* set IRQ 6 for FDPort */ - {0x74, 02}, /* set DMA 2 for FDPort */ - {0xF0, 0x05}, /* set to PS2 type */ - {0xF1, 0x00}, /* default value */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; -/* paralell port (logical device 3) */ -const SIO_LOGDEV_TABLE sio_pport[] = { - {0x60, 3}, /* set IO to PPort (378) */ - {0x61, 0x78}, /* set IO to PPort (378) */ - {0x70, 07}, /* set IRQ 7 for PPort */ - {0xF1, 00}, /* set PPort to normal */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; -/* paralell port (logical device 3) Floppy assigned to lpt */ -const SIO_LOGDEV_TABLE sio_pport_fdc[] = { - {0x60, 3}, /* set IO to PPort (378) */ - {0x61, 0x78}, /* set IO to PPort (378) */ - {0x70, 07}, /* set IRQ 7 for PPort */ - {0xF1, 02}, /* set PPort to Floppy */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; -/* uart 1 (logical device 4) */ -const SIO_LOGDEV_TABLE sio_com1[] = { - {0x60, 3}, /* set IO to COM1 (3F8) */ - {0x61, 0xF8}, /* set IO to COM1 (3F8) */ - {0x70, 04}, /* set IRQ 4 for COM1 */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; -/* uart 2 (logical device 5) */ -const SIO_LOGDEV_TABLE sio_com2[] = { - {0x60, 2}, /* set IO to COM2 (2F8) */ - {0x61, 0xF8}, /* set IO to COM2 (2F8) */ - {0x70, 03}, /* set IRQ 3 for COM2 */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; - -/* keyboard controller (logical device 7) */ -const SIO_LOGDEV_TABLE sio_keyboard[] = { - {0x70, 1}, /* set IRQ 1 for keyboard */ - {0x72, 12}, /* set IRQ 12 for mouse */ - {0xF0, 0}, /* disable Port92 (this is a PowerPC!!) */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; - - -/******************************************************************************* -* Config SuperIO FDC37C672 -********************************************************************************/ -unsigned char open_cfg_super_IO(int address) -{ - out8(CFG_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */ - out8(CFG_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */ - if(in8(CFG_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */ - return TRUE; - else - return FALSE; -} - -void close_cfg_super_IO(int address) -{ - out8(CFG_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */ -} - - -unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr) -{ - /* assuming config reg is open */ - out8(CFG_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */ - out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */ - out8(CFG_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */ - return in8(CFG_ISA_IO_BASE_ADDRESS | address | 1); -} - -void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data) -{ - /* assuming config reg is open */ - out8(CFG_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */ - out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */ - out8(CFG_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */ - out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */ -} - -void isa_write_table(SIO_LOGDEV_TABLE *ldt,unsigned char ldev) -{ - while (ldt->index != 0xFF) { - write_cfg_super_IO(SIO_CFG_PORT, ldev, ldt->index, ldt->val); - ldt++; - } /* endwhile */ -} - -void isa_sio_loadtable(void) -{ - char *s = getenv("floppy"); - /* setup Floppy device 0*/ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_fdc,0); - /* setup parallel port device 3 */ - if(s && !strncmp(s, "lpt", 3)) { - printf("SIO: Floppy assigned to LPT\n"); - /* floppy is assigned to the LPT */ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport_fdc,3); - } - else { - /*printf("Floppy assigned to internal port\n");*/ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport,3); - } - /* setup Com1 port device 4 */ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_com1,4); - /* setup Com2 port device 5 */ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_com2,5); - /* setup keyboards device 7 */ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_keyboard,7); -} - - -void isa_sio_setup(void) -{ - if(open_cfg_super_IO(SIO_CFG_PORT)==TRUE) - { - isa_sio_loadtable(); - close_cfg_super_IO(0x3F0); - } -} -#endif - -/****************************************************************************** - * IRQ Controller - * we use the Vector mode - */ - -struct isa_irq_action { - interrupt_handler_t *handler; - void *arg; - int count; -}; - -static struct isa_irq_action isa_irqs[16]; - - -/* - * This contains the irq mask for both 8259A irq controllers, - */ -static unsigned int cached_irq_mask = 0xfff9; - -#define cached_imr1 (unsigned char)cached_irq_mask -#define cached_imr2 (unsigned char)(cached_irq_mask>>8) -#define IMR_1 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1 -#define IMR_2 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1 -#define ICW1_1 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1 -#define ICW1_2 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1 -#define ICW2_1 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2 -#define ICW2_2 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2 -#define ICW3_1 ICW2_1 -#define ICW3_2 ICW2_2 -#define ICW4_1 ICW2_1 -#define ICW4_2 ICW2_2 -#define ISR_1 ICW1_1 -#define ISR_2 ICW1_2 - - -void disable_8259A_irq(unsigned int irq) -{ - unsigned int mask = 1 << irq; - - cached_irq_mask |= mask; - if (irq & 8) - out8(IMR_2,cached_imr2); - else - out8(IMR_1,cached_imr1); -} - -void enable_8259A_irq(unsigned int irq) -{ - unsigned int mask = ~(1 << irq); - - cached_irq_mask &= mask; - if (irq & 8) - out8(IMR_2,cached_imr2); - else - out8(IMR_1,cached_imr1); -} -/* -int i8259A_irq_pending(unsigned int irq) -{ - unsigned int mask = 1<> 8); - spin_unlock_irqrestore(&i8259A_lock, flags); - - return ret; -} -*/ - -/* - * This function assumes to be called rarely. Switching between - * 8259A registers is slow. - */ -int i8259A_irq_real(unsigned int irq) -{ - int value; - int irqmask = 1<> 8); - out8(ISR_2,0x0A); /* back to the IRR register */ - return value; -} - -/* - * Careful! The 8259A is a fragile beast, it pretty - * much _has_ to be done exactly like this (mask it - * first, _then_ send the EOI, and the order of EOI - * to the two 8259s is important! - */ -void mask_and_ack_8259A(unsigned int irq) -{ - unsigned int irqmask = 1 << irq; - unsigned int temp_irqmask = cached_irq_mask; - /* - * Lightweight spurious IRQ detection. We do not want - * to overdo spurious IRQ handling - it's usually a sign - * of hardware problems, so we only do the checks we can - * do without slowing down good hardware unnecesserily. - * - * Note that IRQ7 and IRQ15 (the two spurious IRQs - * usually resulting from the 8259A-1|2 PICs) occur - * even if the IRQ is masked in the 8259A. Thus we - * can check spurious 8259A IRQs without doing the - * quite slow i8259A_irq_real() call for every IRQ. - * This does not cover 100% of spurious interrupts, - * but should be enough to warn the user that there - * is something bad going on ... - */ - if (temp_irqmask & irqmask) - goto spurious_8259A_irq; - temp_irqmask |= irqmask; - -handle_real_irq: - if (irq & 8) { - in8(IMR_2); /* DUMMY - (do we need this?) */ - out8(IMR_2,(unsigned char)(temp_irqmask>>8)); - out8(ISR_2,0x60+(irq&7));/* 'Specific EOI' to slave */ - out8(ISR_1,0x62); /* 'Specific EOI' to master-IRQ2 */ - out8(IMR_2,cached_imr2); /* turn it on again */ - } else { - in8(IMR_1); /* DUMMY - (do we need this?) */ - out8(IMR_1,(unsigned char)temp_irqmask); - out8(ISR_1,0x60+irq); /* 'Specific EOI' to master */ - out8(IMR_1,cached_imr1); /* turn it on again */ - } - - return; - -spurious_8259A_irq: - /* - * this is the slow path - should happen rarely. - */ - if (i8259A_irq_real(irq)) - /* - * oops, the IRQ _is_ in service according to the - * 8259A - not spurious, go handle it. - */ - goto handle_real_irq; - - { - static int spurious_irq_mask; - /* - * At this point we can be sure the IRQ is spurious, - * lets ACK and report it. [once per IRQ] - */ - if (!(spurious_irq_mask & irqmask)) { - PRINTF("spurious 8259A interrupt: IRQ%d.\n", irq); - spurious_irq_mask |= irqmask; - } - /* irq_err_count++; */ - /* - * Theoretically we do not have to handle this IRQ, - * but in Linux this does not cause problems and is - * simpler for us. - */ - goto handle_real_irq; - } -} - -void init_8259A(void) -{ - out8(IMR_1,0xff); /* mask all of 8259A-1 */ - out8(IMR_2,0xff); /* mask all of 8259A-2 */ - - out8(ICW1_1,0x11); /* ICW1: select 8259A-1 init */ - out8(ICW2_1,0x20 + 0); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */ - out8(ICW3_1,0x04); /* 8259A-1 (the master) has a slave on IR2 */ - out8(ICW4_1,0x01); /* master expects normal EOI */ - out8(ICW1_2,0x11); /* ICW2: select 8259A-2 init */ - out8(ICW2_2,0x20 + 8); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */ - out8(ICW3_2,0x02); /* 8259A-2 is a slave on master's IR2 */ - out8(ICW4_2,0x01); /* (slave's support for AEOI in flat mode - is to be investigated) */ - udelay(10000); /* wait for 8259A to initialize */ - out8(IMR_1,cached_imr1); /* restore master IRQ mask */ - udelay(10000); /* wait for 8259A to initialize */ - out8(IMR_2,cached_imr2); /* restore slave IRQ mask */ -} - - -#define PCI_INT_ACK_ADDR 0xEED00000 - -int handle_isa_int(void) -{ - unsigned long irqack; - unsigned char isr1,isr2,irq; - /* first we acknokledge the int via the PCI bus */ - irqack=in32(PCI_INT_ACK_ADDR); - /* now we get the ISRs */ - isr2=in8(ISR_2); - isr1=in8(ISR_1); - irq=(unsigned char)irqack; - irq-=32; -/* if((irq==7)&&((isr1&0x80)==0)) { - PRINTF("IRQ7 detected but not in ISR\n"); - } - else { -*/ /* we should handle cascaded interrupts here also */ - { -/* printf("ISA Irq %d\n",irq); */ - isa_irqs[irq].count++; - if(irq!=2) { /* just swallow the cascade irq 2 */ - if (isa_irqs[irq].handler != NULL) - (*isa_irqs[irq].handler)(isa_irqs[irq].arg); /* call isr */ - else { - PRINTF ("bogus interrupt vector 0x%x\n", irq); - } - } - } - /* issue EOI instruction to clear the IRQ */ - mask_and_ack_8259A(irq); - return 0; -} - - -/****************************************************************** - * Install and free an ISA interrupt handler. - */ - -void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) -{ - if (isa_irqs[vec].handler != NULL) { - printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n", - vec, (uint)handler, (uint)isa_irqs[vec].handler); - } - isa_irqs[vec].handler = handler; - isa_irqs[vec].arg = arg; - enable_8259A_irq(vec); - PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask); - -} - -void isa_irq_free_handler(int vec) -{ - disable_8259A_irq(vec); - isa_irqs[vec].handler = NULL; - isa_irqs[vec].arg = NULL; - PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask); - -} - -/****************************************************************************/ -void isa_init_irq_contr(void) -{ - int i; - /* disable all Interrupts */ - /* first write icws controller 1 */ - for(i=0;i<16;i++) - { - isa_irqs[i].handler=NULL; - isa_irqs[i].arg=NULL; - isa_irqs[i].count=0; - } - init_8259A(); - out8(IMR_2,0xFF); -} -/*************************************************************************/ - -void isa_show_irq(void) -{ - int vec; - - printf ("\nISA Interrupt-Information:\n"); - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec<16; vec++) { - if (isa_irqs[vec].handler != NULL) { - printf ("%02d %08lx %08lx %d\n", - vec, - (ulong)isa_irqs[vec].handler, - (ulong)isa_irqs[vec].arg, - isa_irqs[vec].count); - } - } -} - -int isa_irq_get_count(int vec) -{ - return(isa_irqs[vec].count); -} - -/****************************************************************** - * Init the ISA bus and devices. - */ - -#if defined(CONFIG_PIP405) - -int isa_init(void) -{ - isa_sio_setup(); - isa_init_irq_contr(); - drv_isa_kbd_init(); - return 0; -} -#endif diff --git a/board/mpl/common/isa.h b/board/mpl/common/isa.h deleted file mode 100644 index 28ed219..0000000 --- a/board/mpl/common/isa.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ISA_H_ -#define _ISA_H_ -/* Super IO */ -#define SIO_CFG_PORT 0x3F0 /* Config Port Address */ - -#if defined(CONFIG_PIP405) -/* table fore SIO initialization */ -typedef struct { - const uchar index; - const uchar val; -} SIO_LOGDEV_TABLE; - -typedef struct { - const uchar ldev; - const SIO_LOGDEV_TABLE *ldev_table; -} SIO_TABLE; - - -unsigned char open_cfg_super_IO(int address); -unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr); -void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data); -void close_cfg_super_IO(int address); -void isa_sio_setup(void); -#endif - -void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg); -void isa_irq_free_handler(int vec); -int handle_isa_int(void); -void isa_init_irq_contr(void); -void isa_show_irq(void); -int isa_irq_get_count(int vec); - - -#endif diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c deleted file mode 100644 index 7724e24..0000000 --- a/board/mpl/common/kbd.c +++ /dev/null @@ -1,647 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - * Source partly derived from: - * linux/drivers/char/pc_keyb.c - * - * - */ -#include -#include -#include -#include "isa.h" -#include "kbd.h" - - -unsigned char kbd_read_status(void); -unsigned char kbd_read_input(void); -void kbd_send_data(unsigned char data); -void disable_8259A_irq(unsigned int irq); -void enable_8259A_irq(unsigned int irq); - -/* used only by send_data - set by keyboard_interrupt */ - - -#undef KBG_DEBUG - -#ifdef KBG_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -#define KBD_STAT_KOBF 0x01 -#define KBD_STAT_IBF 0x02 -#define KBD_STAT_SYS 0x04 -#define KBD_STAT_CD 0x08 -#define KBD_STAT_LOCK 0x10 -#define KBD_STAT_MOBF 0x20 -#define KBD_STAT_TI_OUT 0x40 -#define KBD_STAT_PARERR 0x80 - -#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */ -#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */ -#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */ -/* - * Keyboard Controller Commands - */ - -#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ -#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ -#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ -#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ -#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ -#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ -#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ -#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ -#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ -#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ -#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if - initiated by the auxiliary device */ -#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ - -/* - * Keyboard Commands - */ - -#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ -#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ -#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ -#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */ -#define KBD_CMD_RESET 0xFF /* Reset */ - -/* - * Keyboard Replies - */ - -#define KBD_REPLY_POR 0xAA /* Power on reset */ -#define KBD_REPLY_ACK 0xFA /* Command ACK */ -#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ - -/* - * Status Register Bits - */ - -#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ -#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ -#define KBD_STAT_SELFTEST 0x04 /* Self test successful */ -#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ -#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ -#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ -#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ -#define KBD_STAT_PERR 0x80 /* Parity error */ - -#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF) - -/* - * Controller Mode Register Bits - */ - -#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ -#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ -#define KBD_MODE_SYS 0x04 /* The system flag (?) */ -#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ -#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ -#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ -#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ -#define KBD_MODE_RFU 0x80 - - -#define KDB_DATA_PORT 0x60 -#define KDB_COMMAND_PORT 0x64 - -#define LED_SCR 0x01 /* scroll lock led */ -#define LED_CAP 0x04 /* caps lock led */ -#define LED_NUM 0x02 /* num lock led */ - -#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ - - -static volatile char kbd_buffer[KBD_BUFFER_LEN]; -static volatile int in_pointer = 0; -static volatile int out_pointer = 0; - - -static unsigned char num_lock = 0; -static unsigned char caps_lock = 0; -static unsigned char scroll_lock = 0; -static unsigned char shift = 0; -static unsigned char ctrl = 0; -static unsigned char alt = 0; -static unsigned char e0 = 0; -static unsigned char leds = 0; - -#define DEVNAME "kbd" - -/* Simple translation table for the keys */ - -static unsigned char kbd_plain_xlate[] = { - 0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */ - 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */ - 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ - 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ - '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ - '\r',0xff,0xff - }; - -static unsigned char kbd_shift_xlate[] = { - 0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */ - 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */ - 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */ - 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ - 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ - '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ - '\r',0xff,0xff - }; - -static unsigned char kbd_ctrl_xlate[] = { - 0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */ - 0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */ - 0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */ - 0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ - 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ - '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ - '\r',0xff,0xff - }; - -/****************************************************************** - * Init - ******************************************************************/ -int isa_kbd_init(void) -{ - char* result; - result=kbd_initialize(); - if(result==NULL) { - PRINTF("AT Keyboard initialized\n"); - irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL); - isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL); - return (1); - } - else { - printf("%s\n",result); - return (-1); - } -} - -#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE -extern int overwrite_console (void); -#else -int overwrite_console (void) -{ - return (0); -} -#endif - -int drv_isa_kbd_init (void) -{ - int error; - device_t kbddev ; - char *stdinname = getenv ("stdin"); - - if(isa_kbd_init()==-1) - return -1; - memset (&kbddev, 0, sizeof(kbddev)); - strcpy(kbddev.name, DEVNAME); - kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbddev.putc = NULL ; - kbddev.puts = NULL ; - kbddev.getc = kbd_getc ; - kbddev.tstc = kbd_testc ; - - error = device_register (&kbddev); - if(error==0) { - /* check if this is the standard input device */ - if(strcmp(stdinname,DEVNAME)==0) { - /* reassign the console */ - if(overwrite_console()) { - return 1; - } - error=console_assign(stdin,DEVNAME); - if(error==0) - return 1; - else - return error; - } - return 1; - } - return error; -} - -/****************************************************************** - * Queue handling - ******************************************************************/ -/* puts character in the queue and sets up the in and out pointer */ -void kbd_put_queue(char data) -{ - if((in_pointer+1)==KBD_BUFFER_LEN) { - if(out_pointer==0) { - return; /* buffer full */ - } else{ - in_pointer=0; - } - } else { - if((in_pointer+1)==out_pointer) - return; /* buffer full */ - in_pointer++; - } - kbd_buffer[in_pointer]=data; - return; -} - -/* test if a character is in the queue */ -int kbd_testc(void) -{ - if(in_pointer==out_pointer) - return(0); /* no data */ - else - return(1); -} -/* gets the character from the queue */ -int kbd_getc(void) -{ - char c; - while(in_pointer==out_pointer); - if((out_pointer+1)==KBD_BUFFER_LEN) - out_pointer=0; - else - out_pointer++; - c=kbd_buffer[out_pointer]; - return (int)c; - -} - - -/* set LEDs */ - -void kbd_set_leds(void) -{ - if(caps_lock==0) - leds&=~LED_CAP; /* switch caps_lock off */ - else - leds|=LED_CAP; /* switch on LED */ - if(num_lock==0) - leds&=~LED_NUM; /* switch LED off */ - else - leds|=LED_NUM; /* switch on LED */ - if(scroll_lock==0) - leds&=~LED_SCR; /* switch LED off */ - else - leds|=LED_SCR; /* switch on LED */ - kbd_send_data(KBD_CMD_SET_LEDS); - kbd_send_data(leds); -} - - -void handle_keyboard_event(unsigned char scancode) -{ - unsigned char keycode; - - /* Convert scancode to keycode */ - PRINTF("scancode %x\n",scancode); - if(scancode==0xe0) { - e0=1; /* special charakters */ - return; - } - if(e0==1) { - e0=0; /* delete flag */ - if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */ - ((scancode&0x7F)==0x1D)|| /* the right alt key */ - ((scancode&0x7F)==0x35)|| /* the right '/' key */ - ((scancode&0x7F)==0x1C) )) /* the right enter key */ - /* we swallow unknown e0 codes */ - return; - } - /* special cntrl keys */ - switch(scancode) - { - case 0x2A: - case 0x36: /* shift pressed */ - shift=1; - return; /* do nothing else */ - case 0xAA: - case 0xB6: /* shift released */ - shift=0; - return; /* do nothing else */ - case 0x38: /* alt pressed */ - alt=1; - return; /* do nothing else */ - case 0xB8: /* alt released */ - alt=0; - return; /* do nothing else */ - case 0x1d: /* ctrl pressed */ - ctrl=1; - return; /* do nothing else */ - case 0x9d: /* ctrl released */ - ctrl=0; - return; /* do nothing else */ - case 0x46: /* scrollock pressed */ - scroll_lock=~scroll_lock; - kbd_set_leds(); - return; /* do nothing else */ - case 0x3A: /* capslock pressed */ - caps_lock=~caps_lock; - kbd_set_leds(); - return; - case 0x45: /* numlock pressed */ - num_lock=~num_lock; - kbd_set_leds(); - return; - case 0xC6: /* scroll lock released */ - case 0xC5: /* num lock released */ - case 0xBA: /* caps lock released */ - return; /* just swallow */ - } - if((scancode&0x80)==0x80) /* key released */ - return; - /* now, decide which table we need */ - if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */ - PRINTF("unkown scancode %X\n",scancode); - return; /* swallow it */ - } - /* setup plain code first */ - keycode=kbd_plain_xlate[scancode]; - if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */ - if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ - PRINTF("unkown caps-locked scancode %X\n",scancode); - return; /* swallow it */ - } - keycode=kbd_shift_xlate[scancode]; - if(keycode<'A') { /* we only want the alphas capital */ - keycode=kbd_plain_xlate[scancode]; - } - } - if(shift==1) { /* shift overwrites caps_lock */ - if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ - PRINTF("unkown shifted scancode %X\n",scancode); - return; /* swallow it */ - } - keycode=kbd_shift_xlate[scancode]; - } - if(ctrl==1) { /* ctrl overwrites caps_lock and shift */ - if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */ - PRINTF("unkown ctrl scancode %X\n",scancode); - return; /* swallow it */ - } - keycode=kbd_ctrl_xlate[scancode]; - } - /* check if valid keycode */ - if(keycode==0xff) { - PRINTF("unkown scancode %X\n",scancode); - return; /* swallow unknown codes */ - } - - kbd_put_queue(keycode); - PRINTF("%x\n",keycode); -} - -/* - * This reads the keyboard status port, and does the - * appropriate action. - * - */ -unsigned char handle_kbd_event(void) -{ - unsigned char status = kbd_read_status(); - unsigned int work = 10000; - - while ((--work > 0) && (status & KBD_STAT_OBF)) { - unsigned char scancode; - - scancode = kbd_read_input(); - - /* Error bytes must be ignored to make the - Synaptics touchpads compaq use work */ - /* Ignore error bytes */ - if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) - { - if (status & KBD_STAT_MOUSE_OBF) - ; /* not supported: handle_mouse_event(scancode); */ - else - handle_keyboard_event(scancode); - } - status = kbd_read_status(); - } - if (!work) - PRINTF("pc_keyb: controller jammed (0x%02X).\n", status); - return status; -} - - -/****************************************************************************** - * Lowlevel Part of keyboard section - */ -unsigned char kbd_read_status(void) -{ - return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT)); -} - -unsigned char kbd_read_input(void) -{ - return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT)); -} - -void kbd_write_command(unsigned char cmd) -{ - out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd); -} - -void kbd_write_output(unsigned char data) -{ - out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data); -} - -int kbd_read_data(void) -{ - int val; - unsigned char status; - - val=-1; - status = kbd_read_status(); - if (status & KBD_STAT_OBF) { - val = kbd_read_input(); - if (status & (KBD_STAT_GTO | KBD_STAT_PERR)) - val = -2; - } - return val; -} - -int kbd_wait_for_input(void) -{ - unsigned long timeout; - int val; - - timeout = KBD_TIMEOUT; - val=kbd_read_data(); - while(val < 0) - { - if(timeout--==0) - return -1; - udelay(1000); - val=kbd_read_data(); - } - return val; -} - - -int kb_wait(void) -{ - unsigned long timeout = KBC_TIMEOUT * 10; - - do { - unsigned char status = handle_kbd_event(); - if (!(status & KBD_STAT_IBF)) - return 0; /* ok */ - udelay(1000); - timeout--; - } while (timeout); - return 1; -} - -void kbd_write_command_w(int data) -{ - if(kb_wait()) - PRINTF("timeout in kbd_write_command_w\n"); - kbd_write_command(data); -} - -void kbd_write_output_w(int data) -{ - if(kb_wait()) - PRINTF("timeout in kbd_write_output_w\n"); - kbd_write_output(data); -} - -void kbd_send_data(unsigned char data) -{ - unsigned char status; - disable_8259A_irq(1); /* disable interrupt */ - kbd_write_output_w(data); - status = kbd_wait_for_input(); - if (status == KBD_REPLY_ACK) - enable_8259A_irq(1); /* enable interrupt */ -} - - -char * kbd_initialize(void) -{ - int status; - - in_pointer = 0; /* delete in Buffer */ - out_pointer = 0; - /* - * Test the keyboard interface. - * This seems to be the only way to get it going. - * If the test is successful a x55 is placed in the input buffer. - */ - kbd_write_command_w(KBD_CCMD_SELF_TEST); - if (kbd_wait_for_input() != 0x55) - return "Kbd: failed self test"; - /* - * Perform a keyboard interface test. This causes the controller - * to test the keyboard clock and data lines. The results of the - * test are placed in the input buffer. - */ - kbd_write_command_w(KBD_CCMD_KBD_TEST); - if (kbd_wait_for_input() != 0x00) - return "Kbd: interface failed self test"; - /* - * Enable the keyboard by allowing the keyboard clock to run. - */ - kbd_write_command_w(KBD_CCMD_KBD_ENABLE); - status = kbd_wait_for_input(); - /* - * Reset keyboard. If the read times out - * then the assumption is that no keyboard is - * plugged into the machine. - * This defaults the keyboard to scan-code set 2. - * - * Set up to try again if the keyboard asks for RESEND. - */ - do { - kbd_write_output_w(KBD_CMD_RESET); - status = kbd_wait_for_input(); - if (status == KBD_REPLY_ACK) - break; - if (status != KBD_REPLY_RESEND) - { - PRINTF("status: %X\n",status); - return "Kbd: reset failed, no ACK"; - } - } while (1); - if (kbd_wait_for_input() != KBD_REPLY_POR) - return "Kbd: reset failed, no POR"; - - /* - * Set keyboard controller mode. During this, the keyboard should be - * in the disabled state. - * - * Set up to try again if the keyboard asks for RESEND. - */ - do { - kbd_write_output_w(KBD_CMD_DISABLE); - status = kbd_wait_for_input(); - if (status == KBD_REPLY_ACK) - break; - if (status != KBD_REPLY_RESEND) - return "Kbd: disable keyboard: no ACK"; - } while (1); - - kbd_write_command_w(KBD_CCMD_WRITE_MODE); - kbd_write_output_w(KBD_MODE_KBD_INT - | KBD_MODE_SYS - | KBD_MODE_DISABLE_MOUSE - | KBD_MODE_KCC); - - /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */ - kbd_write_command_w(KBD_CCMD_READ_MODE); - if (!(kbd_wait_for_input() & KBD_MODE_KCC)) { - /* - * If the controller does not support conversion, - * Set the keyboard to scan-code set 1. - */ - kbd_write_output_w(0xF0); - kbd_wait_for_input(); - kbd_write_output_w(0x01); - kbd_wait_for_input(); - } - kbd_write_output_w(KBD_CMD_ENABLE); - if (kbd_wait_for_input() != KBD_REPLY_ACK) - return "Kbd: enable keyboard: no ACK"; - - /* - * Finally, set the typematic rate to maximum. - */ - kbd_write_output_w(KBD_CMD_SET_RATE); - if (kbd_wait_for_input() != KBD_REPLY_ACK) - return "Kbd: Set rate: no ACK"; - kbd_write_output_w(0x00); - if (kbd_wait_for_input() != KBD_REPLY_ACK) - return "Kbd: Set rate: no ACK"; - return NULL; -} - -void kbd_interrupt(void) -{ - handle_kbd_event(); -} diff --git a/board/mpl/common/kbd.h b/board/mpl/common/kbd.h deleted file mode 100644 index 229ba61..0000000 --- a/board/mpl/common/kbd.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _KBD_H_ -#define _KBD_H_ - -extern int kbd_testc(void); -extern int kbd_getc(void); -extern void kbd_interrupt(void); -extern char *kbd_initialize(void); - -unsigned char kbd_is_init(void); -#define KBD_INTERRUPT 1 -#endif diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c deleted file mode 100644 index 2c77d37..0000000 --- a/board/mpl/common/memtst.c +++ /dev/null @@ -1,590 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* NOT Used yet... - add following code to PIP405.c : -int testdram (void) -{ - unsigned char s[32]; - int i; - - i = getenv_r ("testmem", s, 32); - if (i != 0) { - i = (int) simple_strtoul (s, NULL, 10); - if ((i > 0) && (i < 0xf)) { - printf ("testing "); - i = mem_test (0, ramsize, i); - if (i > 0) - printf ("ERROR "); - else - printf ("Ok "); - } - } - return (1); -} -*/ - - -#include -#include -#include <405gp_i2c.h> - -#define FALSE 0 -#define TRUE 1 - -#define TEST_QUIET 8 -#define TEST_SHOW_PROG 4 -#define TEST_SHOW_ERR 2 -#define TEST_SHOW_ALL 1 - -#define TESTPAT1 0xAA55AA55 -#define TESTPAT2 0x55AA55AA -#define TEST_PASSED 0 -#define TEST_FAILED 1 -#define MEGABYTE (1024*1024) - - -typedef struct { - volatile unsigned long pat1; - volatile unsigned long pat2; -} RAM_MEMTEST_PATTERN2; - -typedef struct { - volatile unsigned long addr; -} RAM_MEMTEST_ADDRLINE; - -static __inline unsigned long Swap_32 (unsigned long val) -{ - return (((val << 16) & 0xFFFF0000) | ((val >> 16) & 0x0000FFFF)); -} - -void testm_puts (int quiet, char *buf) -{ - if ((quiet & TEST_SHOW_ALL) == TEST_SHOW_ALL) - puts (buf); -} - - -void Write_Error (int mode, unsigned long addr, unsigned long expected, - unsigned long actual) -{ - - char dispbuf[64]; - - sprintf (dispbuf, "\n ERROR @ 0x%08lX: (exp: 0x%08lX act: 0x%08lX) ", - addr, expected, actual); - testm_puts (((mode & TEST_SHOW_ERR) == - TEST_SHOW_ERR) ? TEST_SHOW_ALL : mode, dispbuf); -} - - -/* - * fills the memblock of bytes from with pat1 and pat2 - */ - - -void RAM_MemTest_WritePattern2 (unsigned long startaddr, - unsigned long size, unsigned long pat1, - unsigned long pat2) -{ - RAM_MEMTEST_PATTERN2 *p, *pe; - - p = (RAM_MEMTEST_PATTERN2 *) startaddr; - pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size); - - while (p < pe) { - p->pat1 = pat1; - p->pat2 = pat2; - p++; - } /* endwhile */ -} - -/* - * checks the memblock of bytes from with pat1 and pat2 - * returns the address of the first error or NULL if all is well - */ - -void *RAM_MemTest_CheckPattern2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long pat1, - unsigned long pat2) -{ - RAM_MEMTEST_PATTERN2 *p, *pe; - unsigned long actual1, actual2; - - p = (RAM_MEMTEST_PATTERN2 *) startaddr; - pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size); - - while (p < pe) { - actual1 = p->pat1; - actual2 = p->pat2; - - if (actual1 != pat1) { - Write_Error (mode, (unsigned long) &(p->pat1), pat1, actual1); - return ((void *) &(p->pat1)); - } - /* endif */ - if (actual2 != pat2) { - Write_Error (mode, (unsigned long) &(p->pat2), pat2, actual2); - return ((void *) &(p->pat2)); - } - /* endif */ - p++; - } /* endwhile */ - - return (NULL); -} - -/* - * fills the memblock of bytes from with the address - */ - -void RAM_MemTest_WriteAddrLine (unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - - p = (RAM_MEMTEST_ADDRLINE *) startaddr; - pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size); - - if (!swapped) { - while (p < pe) { - p->addr = (unsigned long) p; - p++; - } /* endwhile */ - } else { - while (p < pe) { - p->addr = Swap_32 ((unsigned long) p); - p++; - } /* endwhile */ - } /* endif */ -} - -/* - * checks the memblock of bytes from - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckAddrLine (int mode, unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - unsigned long actual, expected; - - p = (RAM_MEMTEST_ADDRLINE *) startaddr; - pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size); - - if (!swapped) { - while (p < pe) { - actual = p->addr; - expected = (unsigned long) p; - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p++; - } /* endwhile */ - } else { - while (p < pe) { - actual = p->addr; - expected = Swap_32 ((unsigned long) p); - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p++; - } /* endwhile */ - } /* endif */ - - return (NULL); -} - -/* - * checks the memblock of bytes from - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckAddrLineReverse (int mode, unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - unsigned long actual, expected; - - p = (RAM_MEMTEST_ADDRLINE *) (startaddr + size - sizeof (p->addr)); - pe = (RAM_MEMTEST_ADDRLINE *) startaddr; - - if (!swapped) { - while (p > pe) { - actual = p->addr; - expected = (unsigned long) p; - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p--; - } /* endwhile */ - } else { - while (p > pe) { - actual = p->addr; - expected = Swap_32 ((unsigned long) p); - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p--; - } /* endwhile */ - } /* endif */ - - return (NULL); -} - -/* - * fills the memblock of bytes from with walking bit pattern - */ - -void RAM_MemTest_WriteWalkBit (unsigned long startaddr, unsigned long size) -{ - volatile unsigned long *p, *pe; - unsigned long i; - - p = (unsigned long *) startaddr; - pe = (unsigned long *) (startaddr + size); - i = 0; - - while (p < pe) { - *p = 1UL << i; - i = (i + 1 + (((unsigned long) p) >> 7)) % 32; - p++; - } /* endwhile */ -} - -/* - * checks the memblock of bytes from - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckWalkBit (int mode, unsigned long startaddr, - unsigned long size) -{ - volatile unsigned long *p, *pe; - unsigned long actual, expected; - unsigned long i; - - p = (unsigned long *) startaddr; - pe = (unsigned long *) (startaddr + size); - i = 0; - - while (p < pe) { - actual = *p; - expected = (1UL << i); - if (actual != expected) { - Write_Error (mode, (unsigned long) p, expected, actual); - return ((void *) p); - } /* endif */ - i = (i + 1 + (((unsigned long) p) >> 7)) % 32; - p++; - } /* endwhile */ - - return (NULL); -} - -/* - * fills the memblock of bytes from with "random" pattern - */ - -void RAM_MemTest_WriteRandomPattern (unsigned long startaddr, - unsigned long size, - unsigned long *pat) -{ - unsigned long i, p; - - p = *pat; - - for (i = 0; i < (size / 4); i++) { - *(unsigned long *) (startaddr + i * 4) = p; - if ((p % 2) > 0) { - p ^= i; - p >>= 1; - p |= 0x80000000; - } else { - p ^= ~i; - p >>= 1; - } /* endif */ - } /* endfor */ - *pat = p; -} - -/* - * checks the memblock of bytes from - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckRandomPattern (int mode, unsigned long startaddr, - unsigned long size, - unsigned long *pat) -{ - void *perr = NULL; - unsigned long i, p, p1; - - p = *pat; - - for (i = 0; i < (size / 4); i++) { - p1 = *(unsigned long *) (startaddr + i * 4); - if (p1 != p) { - if (perr == NULL) { - Write_Error (mode, startaddr + i * 4, p, p1); - perr = (void *) (startaddr + i * 4); - } /* endif */ - } - /* endif */ - if ((p % 2) > 0) { - p ^= i; - p >>= 1; - p |= 0x80000000; - } else { - p ^= ~i; - p >>= 1; - } /* endif */ - } /* endfor */ - - *pat = p; - return (perr); -} - - -void RAM_MemTest_WriteData1 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT1, TESTPAT2); -} - -void *RAM_MemTest_CheckData1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckPattern2 - (mode, startaddr, size, TESTPAT1, TESTPAT2)); -} - -void RAM_MemTest_WriteData2 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT2, TESTPAT1); -} - -void *RAM_MemTest_CheckData2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckPattern2 - (mode, startaddr, size, TESTPAT2, TESTPAT1)); -} - -void RAM_MemTest_WriteAddr1 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WriteAddrLine (startaddr, size, FALSE); -} - -void *RAM_MemTest_Check1Addr1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, FALSE)); -} - -void *RAM_MemTest_Check2Addr1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLineReverse - (mode, startaddr, size, FALSE)); -} - -void RAM_MemTest_WriteAddr2 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WriteAddrLine (startaddr, size, TRUE); -} - -void *RAM_MemTest_Check1Addr2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, TRUE)); -} - -void *RAM_MemTest_Check2Addr2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLineReverse - (mode, startaddr, size, TRUE)); -} - - -typedef struct { - void (*test_write) (unsigned long startaddr, unsigned long size, - unsigned long *pat); - char *test_write_desc; - void *(*test_check1) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat); - void *(*test_check2) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat); -} RAM_MEMTEST_FUNC; - - -#define TEST_STAGES 5 -static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = { - {RAM_MemTest_WriteData1, "data test 1...\n", RAM_MemTest_CheckData1, - NULL}, - {RAM_MemTest_WriteData2, "data test 2...\n", RAM_MemTest_CheckData2, - NULL}, - {RAM_MemTest_WriteAddr1, "address line test...\n", - RAM_MemTest_Check1Addr1, RAM_MemTest_Check2Addr1}, - {RAM_MemTest_WriteAddr2, "address line test (swapped)...\n", - RAM_MemTest_Check1Addr2, RAM_MemTest_Check2Addr2}, - {RAM_MemTest_WriteRandomPattern, "random data test...\n", - RAM_MemTest_CheckRandomPattern, NULL} -}; - -void mem_test_reloc(void) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned long addr; - int i; - for (i=0; i< TEST_STAGES; i++) { - addr = (ulong) (test_stage[i].test_write) + gd->reloc_off; - test_stage[i].test_write= - (void (*) (unsigned long startaddr, unsigned long size, - unsigned long *pat))addr; - addr = (ulong) (test_stage[i].test_write_desc) + gd->reloc_off; - test_stage[i].test_write_desc=(char *)addr; - if(test_stage[i].test_check1) { - addr = (ulong) (test_stage[i].test_check1) + gd->reloc_off; - test_stage[i].test_check1= - (void *(*) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat))addr; - } - if(test_stage[i].test_check2) { - addr = (ulong) (test_stage[i].test_check2) + gd->reloc_off; - test_stage[i].test_check2= - (void *(*) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat))addr; - } - } -} - - -int mem_test (unsigned long start, unsigned long ramsize, int quiet) -{ - unsigned long errors, stage; - unsigned long startaddr, size, i; - const unsigned long blocksize = 0x80000; /* check in 512KB blocks */ - unsigned long *perr; - unsigned long rdatapat; - char dispbuf[80]; - int status = TEST_PASSED; - int prog = 0; - - errors = 0; - startaddr = start; - size = ramsize; - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - sprintf (dispbuf, "\nMemory Test: addr = 0x%lx size = 0x%lx\n", - startaddr, size); - testm_puts (quiet, dispbuf); - for (stage = 0; stage < TEST_STAGES; stage++) { - sprintf (dispbuf, test_stage[stage].test_write_desc); - testm_puts (quiet, dispbuf); - /* fill SDRAM */ - rdatapat = 0x12345678; - sprintf (dispbuf, "writing block: "); - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - test_stage[stage].test_write (startaddr + i, blocksize, - &rdatapat); - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - /* check SDRAM */ - rdatapat = 0x12345678; - sprintf (dispbuf, "checking block: "); - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - if ((perr = - test_stage[stage].test_check1 (quiet, startaddr + i, - blocksize, - &rdatapat)) != NULL) { - status = TEST_FAILED; - } /* endif */ - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - if (test_stage[stage].test_check2 != NULL) { - /* check2 SDRAM */ - sprintf (dispbuf, "2nd checking block: "); - rdatapat = 0x12345678; - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - if ((perr = - test_stage[stage].test_check2 (quiet, startaddr + i, - blocksize, - &rdatapat)) != NULL) { - status = TEST_FAILED; - } /* endif */ - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - } - - } /* next stage */ - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - while (prog-- > 0) - printf ("\b \b"); - } - - if (status == TEST_FAILED) - errors++; - - return (errors); -} diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c deleted file mode 100644 index 692930b..0000000 --- a/board/mpl/common/pci.c +++ /dev/null @@ -1,126 +0,0 @@ -/*-----------------------------------------------------------------------------+ -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1995 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+-----------------------------------------------------------------------------*/ -/* - * Adapted for PIP405 03.07.01 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * TODO: Clean-up - */ - -#include -#include -#include "isa.h" - -#ifdef CONFIG_405GP -#ifdef CONFIG_PCI - -#undef DEBUG - -#include "piix4_pci.h" -#include "pci_parts.h" - -void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *entry) -{ - struct pci_pip405_config_entry *table; - int i; - - table = (struct pci_pip405_config_entry*) entry->priv[0]; - - for (i=0; table[i].width; i++) - { -#ifdef DEBUG - printf("Reg 0x%02X Value 0x%08lX Width %02d written\n", - table[i].index, table[i].val, table[i].width); -#endif - - switch(table[i].width) - { - case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break; - case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break; - case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break; - } - } -} - - -static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line = 0xff; - unsigned char pin; - /* - * Write pci interrupt line register - */ - if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */ - return; - pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); - if ((pin == 0) || (pin > 4)) - return; - - int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28; - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); -#ifdef DEBUG - printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", - PCI_DEV(dev),dev,int_line,int_line); -#endif -} - -extern void pci_405gp_init(struct pci_controller *hose); - - -static struct pci_controller hose = { - config_table: pci_pip405_config_table, - fixup_irq: pci_pip405_fixup_irq, -}; - - -static void reloc_pci_cfg_table(struct pci_config_table *table) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned long addr; - - for (; table && table->vendor; table++) { - addr = (ulong) (table->config_device) + gd->reloc_off; -#ifdef DEBUG - printf ("device \"%d\": 0x%08lx => 0x%08lx\n", - table->device, (ulong) (table->config_device), addr); -#endif - table->config_device = - (void (*)(struct pci_controller* hose, pci_dev_t dev, - struct pci_config_table *))addr; - table->priv[0]+=gd->reloc_off; - } -} - -void pci_init_board(void) -{ - /*we want the ptrs to RAM not flash (ie don't use init list)*/ - hose.fixup_irq = pci_pip405_fixup_irq; - hose.config_table = pci_pip405_config_table; - reloc_pci_cfg_table(hose.config_table); -#ifdef DEBUG - printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose); -#endif - pci_405gp_init(&hose); -} - -#endif /* CONFIG_PCI */ -#endif /* CONFIG_405GP */ diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h deleted file mode 100644 index 60008e2..0000000 --- a/board/mpl/common/pci_parts.h +++ /dev/null @@ -1,193 +0,0 @@ - /* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -#ifndef _PCI_PARTS_H_ -#define _PCI_PARTS_H_ - - -/* Board specific file containing: - * - PCI Memory Mapping - * - PCI IO Mapping - * - PCI Interrupt Mapping - */ - -/* PIP405 PCI INT Routing: - * IRQ0 VECTOR - * PIXX4 IDSEL = AD16 INTA# 28 (Function 2 USB is INTD# = 31) - * VGA IDSEL = AD17 INTB# 29 - * SCSI IDSEL = AD18 INTC# 30 - * PC104 IDSEL0 = AD20 INTA# 28 - * PC104 IDSEL1 = AD21 INTB# 29 - * PC104 IDSEL2 = AD22 INTC# 30 - * PC104 IDSEL3 = AD23 INTD# 31 - * - * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00 - * ^ ^ ^ ^ ^ - * 31 23 15 10 7 - * E = Enabled - * B = Bussnumber - * D = Devicenumber (Device0 = AD10) - * F = Functionnumber - * R = Registernumber - * - * Device = (busdevfunc>>11) + 10 - * Vector = devicenumber % 4 + 28 - * - */ -#define PCI_HIGHEST_ON_BOARD_ID 19 -/*#define PCI_DEV_NUMBER(x) (((x>>11) & 0x1f) + 10) */ -#define PCI_IRQ_VECTOR(x) ((PCI_DEV(x) + 10) % 4) + 28 - - -/* PCI Device List for PIP405 */ - -/* Mapping: - * +-------------+------------+------------+--------------------------------+ - * ¦ PCI MemAddr | PCI IOAddr | Local Addr | Device / Function | - * +-------------+------------+------------+--------------------------------+ - * | 0x00000000 | | 0xA0000000 | ISA Memory (hard wired) | - * | 0x00FFFFFF | | 0xA0FFFFFF | | - * +-------------+------------+------------+--------------------------------+ - * | | 0x00000000 | 0xE8000000 | ISA IO (hard wired) | - * | | 0x0000FFFF | 0xE800FFFF | | - * +-------------+------------+------------+--------------------------------+ - * | 0x80000000 | | 0x80000000 | VGA Controller Memory | - * | 0x80FFFFFF | | 0x80FFFFFF | | - * +-------------+------------+------------+--------------------------------+ - * | 0x81000000 | | 0x81000000 | SCSI Controller Memory | - * | 0x81FFFFFF | | 0x81FFFFFF | | - * +-------------+------------+------------+--------------------------------+ - */ - -struct pci_pip405_config_entry { - int index; /* address */ - unsigned long val; /* value */ - int width; /* data size */ -}; - -extern void pci_pip405_write_regs(struct pci_controller *, - pci_dev_t, - struct pci_config_table *); - -/* PIIX4 ISA Bridge Function 0 */ -static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = { - {PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */ - {PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */ - {PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */ - {PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */ - {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */ -#if defined(CONFIG_PIP405) - {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */ - {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */ -#endif - {PCI_CFG_PIIX4_DLC, 0x0, 1}, /* disable passive release feature */ - { } /* end of device table */ -}; - -/* PIIX4 IDE Controller Function 1 */ -static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = { - {PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */ - {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ -#if !defined(CONFIG_MIP405T) - {PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */ -#else - {PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */ -#endif - { } /* end of device table */ -}; - -/* PIIX4 USB Controller Function 2 */ -static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = { -#if !defined(CONFIG_MIP405T) - {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */ - {PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */ - {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */ - {0xC0, 0x2000, 2}, /* Legacy support */ - {PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */ -#endif - { } /* end of device table */ -}; - -/* PIIX4 Power Management Function 3 */ -static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = { - {PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */ - {PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */ - {PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */ - {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ - { } /* end of device table */ -}; -/* PPC405 Dummy only used to prevent autosetup on this host bridge */ -static struct pci_pip405_config_entry ppc405_dummy[] = { - { } /* end of device table */ -}; - -void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *entry); - - -static struct pci_config_table pci_pip405_config_table[]={ - {PCI_VENDOR_ID_IBM, /* 405 dummy */ - PCI_DEVICE_ID_IBM_405GP, - PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, 0, - pci_pip405_write_regs, {(unsigned long) ppc405_dummy}}, - - {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */ - PCI_DEVICE_ID_INTEL_82371AB_0, - PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, 0, - pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}}, - - {PCI_VENDOR_ID_INTEL, /* PIIX4 IDE Controller Function 1 */ - PCI_DEVICE_ID_INTEL_82371AB, - PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, 1, - pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}}, - - {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 2 */ - PCI_DEVICE_ID_INTEL_82371AB_2, - PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, 2, - pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}}, - - {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 3 */ - PCI_DEVICE_ID_INTEL_82371AB_3, - PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, 3, - pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}}, - - {PCI_ANY_ID, - PCI_ANY_ID, - PCI_CLASS_DISPLAY_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_405gp_setup_vga}, - - {PCI_ANY_ID, - PCI_ANY_ID, - PCI_CLASS_NOT_DEFINED_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_405gp_setup_vga}, - - { } -}; -#endif /* _PCI_PARTS_H_ */ diff --git a/board/mpl/common/piix4_pci.h b/board/mpl/common/piix4_pci.h deleted file mode 100644 index 0ff802e..0000000 --- a/board/mpl/common/piix4_pci.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#ifndef _PIIX4_PCI_H -#define _PIIX4_PCI_H - -/*************************************************************************** -* Defines PIIX4 Config Registers -****************************************************************************/ - -/* Function 0 ISA Bridge */ -#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */ -#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */ -#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/ -#define PCI_CFG_PIIX4_SERIRQ 0x64 -#define PCI_CFG_PIIX4_TOM 0x69 -#define PCI_CFG_PIIX4_MSTAT 0x6A -#define PCI_CFG_PIIX4_MBDMA 0x76 -#define PCI_CFG_PIIX4_APICBS 0x80 -#define PCI_CFG_PIIX4_DLC 0x82 -#define PCI_CFG_PIIX4_PDMACFG 0x90 -#define PCI_CFG_PIIX4_DDMABS 0x92 -#define PCI_CFG_PIIX4_GENCFG 0xB0 -#define PCI_CFG_PIIX4_RTCCFG 0xCB - -/* IO Addresses */ -#define PIIX4_ISA_DMA1_CH0BA 0x00 -#define PIIX4_ISA_DMA1_CH0CA 0x01 -#define PIIX4_ISA_DMA1_CH1BA 0x02 -#define PIIX4_ISA_DMA1_CH1CA 0x03 -#define PIIX4_ISA_DMA1_CH2BA 0x04 -#define PIIX4_ISA_DMA1_CH2CA 0x05 -#define PIIX4_ISA_DMA1_CH3BA 0x06 -#define PIIX4_ISA_DMA1_CH3CA 0x07 -#define PIIX4_ISA_DMA1_CMDST 0x08 -#define PIIX4_ISA_DMA1_REQ 0x09 -#define PIIX4_ISA_DMA1_WSBM 0x0A -#define PIIX4_ISA_DMA1_CH_MOD 0x0B -#define PIIX4_ISA_DMA1_CLR_PT 0x0C -#define PIIX4_ISA_DMA1_M_CLR 0x0D -#define PIIX4_ISA_DMA1_CLR_M 0x0E -#define PIIX4_ISA_DMA1_RWAMB 0x0F - -#define PIIX4_ISA_DMA2_CH0BA 0xC0 -#define PIIX4_ISA_DMA2_CH0CA 0xC1 -#define PIIX4_ISA_DMA2_CH1BA 0xC2 -#define PIIX4_ISA_DMA2_CH1CA 0xC3 -#define PIIX4_ISA_DMA2_CH2BA 0xC4 -#define PIIX4_ISA_DMA2_CH2CA 0xC5 -#define PIIX4_ISA_DMA2_CH3BA 0xC6 -#define PIIX4_ISA_DMA2_CH3CA 0xC7 -#define PIIX4_ISA_DMA2_CMDST 0xD0 -#define PIIX4_ISA_DMA2_REQ 0xD2 -#define PIIX4_ISA_DMA2_WSBM 0xD4 -#define PIIX4_ISA_DMA2_CH_MOD 0xD6 -#define PIIX4_ISA_DMA2_CLR_PT 0xD8 -#define PIIX4_ISA_DMA2_M_CLR 0xDA -#define PIIX4_ISA_DMA2_CLR_M 0xDC -#define PIIX4_ISA_DMA2_RWAMB 0xDE - -#define PIIX4_ISA_INT1_ICW1 0x20 -#define PIIX4_ISA_INT1_OCW2 0x20 -#define PIIX4_ISA_INT1_OCW3 0x20 -#define PIIX4_ISA_INT1_ICW2 0x21 -#define PIIX4_ISA_INT1_ICW3 0x21 -#define PIIX4_ISA_INT1_ICW4 0x21 -#define PIIX4_ISA_INT1_OCW1 0x21 - -#define PIIX4_ISA_INT1_ELCR 0x4D0 - -#define PIIX4_ISA_INT2_ICW1 0xA0 -#define PIIX4_ISA_INT2_OCW2 0xA0 -#define PIIX4_ISA_INT2_OCW3 0xA0 -#define PIIX4_ISA_INT2_ICW2 0xA1 -#define PIIX4_ISA_INT2_ICW3 0xA1 -#define PIIX4_ISA_INT2_ICW4 0xA1 -#define PIIX4_ISA_INT2_OCW1 0xA1 -#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */ - -#define PIIX4_ISA_INT2_ELCR 0x4D1 - -#define PIIX4_ISA_TMR0_CNT_ST 0x40 -#define PIIX4_ISA_TMR1_CNT_ST 0x41 -#define PIIX4_ISA_TMR2_CNT_ST 0x42 -#define PIIX4_ISA_TMR_TCW 0x43 - -#define PIIX4_ISA_RST_XBUS 0x60 - -#define PIIX4_ISA_NMI_CNT_ST 0x61 -#define PIIX4_ISA_NMI_ENABLE 0x70 - -#define PIIX4_ISA_RTC_INDEX 0x70 -#define PIIX4_ISA_RTC_DATA 0x71 -#define PIIX4_ISA_RTCEXT_IND 0x70 -#define PIIX4_ISA_RTCEXT_DATA 0x71 - -#define PIIX4_ISA_DMA1_CH2LPG 0x81 -#define PIIX4_ISA_DMA1_CH3LPG 0x82 -#define PIIX4_ISA_DMA1_CH1LPG 0x83 -#define PIIX4_ISA_DMA1_CH0LPG 0x87 -#define PIIX4_ISA_DMA2_CH2LPG 0x89 -#define PIIX4_ISA_DMA2_CH3LPG 0x8A -#define PIIX4_ISA_DMA2_CH1LPG 0x8B -#define PIIX4_ISA_DMA2_LPGRFR 0x8F - -#define PIIX4_ISA_PORT_92 0x92 - -#define PIIX4_ISA_APM_CONTRL 0xB2 -#define PIIX4_ISA_APM_STATUS 0xB3 - -#define PIIX4_ISA_COCPU_ERROR 0xF0 - -/* Function 1 IDE Controller */ -#define PCI_CFG_PIIX4_BMIBA 0x20 -#define PCI_CFG_PIIX4_IDETIM 0x40 -#define PCI_CFG_PIIX4_SIDETIM 0x44 -#define PCI_CFG_PIIX4_UDMACTL 0x48 -#define PCI_CFG_PIIX4_UDMATIM 0x4A - -/* Function 2 USB Controller */ -#define PCI_CFG_PIIX4_SBRNUM 0x60 -#define PCI_CFG_PIIX4_LEGSUP 0xC0 - -/* Function 3 Power Management */ -#define PCI_CFG_PIIX4_PMBA 0x40 -#define PCI_CFG_PIIX4_CNTA 0x44 -#define PCI_CFG_PIIX4_CNTB 0x48 -#define PCI_CFG_PIIX4_GPICTL 0x4C -#define PCI_CFG_PIIX4_DEVRESD 0x50 -#define PCI_CFG_PIIX4_DEVACTA 0x54 -#define PCI_CFG_PIIX4_DEVACTB 0x58 -#define PCI_CFG_PIIX4_DEVRESA 0x5C -#define PCI_CFG_PIIX4_DEVRESB 0x60 -#define PCI_CFG_PIIX4_DEVRESC 0x64 -#define PCI_CFG_PIIX4_DEVRESE 0x68 -#define PCI_CFG_PIIX4_DEVRESF 0x6C -#define PCI_CFG_PIIX4_DEVRESG 0x70 -#define PCI_CFG_PIIX4_DEVRESH 0x74 -#define PCI_CFG_PIIX4_DEVRESI 0x78 -#define PCI_CFG_PIIX4_PMMISC 0x80 -#define PCI_CFG_PIIX4_SMBBA 0x90 - - -#endif diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c deleted file mode 100644 index 84c91c4..0000000 --- a/board/mpl/common/usb_uhci.c +++ /dev/null @@ -1,1169 +0,0 @@ -/* - * Part of this code has been derived from linux: - * Universal Host Controller Interface driver for USB (take II). - * - * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar) - * Deti Fliegl, deti@fliegl.de (executive slave) (lead voice) - * Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader) - * Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter) - * (c) 2000 Yggdrasil Computing, Inc. (port of new PCI interface support - * from usb-ohci.c by Adam Richter, adam@yggdrasil.com). - * (C) 2000 David Brownell, david-b@pacbell.net (usb-ohci.c) - * - * HW-initalization based on material of - * - * (C) Copyright 1999 Linus Torvalds - * (C) Copyright 1999 Johannes Erdfelt - * (C) Copyright 1999 Randy Dunlap - * (C) Copyright 1999 Gregory P. Smith - * - * - * Adapted for U-Boot: - * (C) Copyright 2001 Denis Peter, MPL AG Switzerland - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - */ - -/********************************************************************** - * How it works: - * ------------- - * The framelist / Transfer descriptor / Queue Heads are similar like - * in the linux usb_uhci.c. - * - * During initialization, the following skeleton is allocated in init_skel: - * - * framespecific | common chain - * - * framelist[] - * [ 0 ]-----> TD ---------\ - * [ 1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL - * ... TD ---------/ - * [1023]-----> TD --------/ - * - * ^^ ^^ ^^ ^^ ^^ - * 7 TDs for 1 TD for Start of Start of End Chain - * INT (2-128ms) 1ms-INT CTRL Chain BULK Chain - * - * - * Since this is a bootloader, the isochronous transfer descriptor have been removed. - * - * Interrupt Transfers. - * -------------------- - * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They - * will be inserted after the appropriate (depending the interval setting) skeleton TD. - * If an interrupt has been detected the dev->irqhandler is called. The status and number - * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the - * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned, - * the interrupt TD will be reactivated. - * - * Control Transfers - * ----------------- - * Control Transfers are issued by filling the tmp_td with the appropriate data and connect - * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued, - * the programm has to wait for completion. This does not allows asynchronous data transfer. - * - * Bulk Transfers - * -------------- - * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect - * them to the qh_bulk queue header. Before other control/bulk transfers can be issued, - * the programm has to wait for completion. This does not allows asynchronous data transfer. - * - * - */ - -#include -#include - -#ifdef CONFIG_USB_UHCI - -#include -#include "usb_uhci.h" - -#define USB_MAX_TEMP_TD 128 /* number of temporary TDs for bulk and control transfers */ -#define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */ - - -#undef USB_UHCI_DEBUG - -#ifdef USB_UHCI_DEBUG -#define USB_UHCI_PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define USB_UHCI_PRINTF(fmt,args...) -#endif - - -static int irqvec = -1; /* irq vector, if -1 uhci is stopped / reseted */ -unsigned int usb_base_addr; /* base address */ - -static uhci_td_t td_int[8]; /* Interrupt Transfer descriptors */ -static uhci_qh_t qh_cntrl; /* control Queue Head */ -static uhci_qh_t qh_bulk; /* bulk Queue Head */ -static uhci_qh_t qh_end; /* end Queue Head */ -static uhci_td_t td_last; /* last TD (linked with end chain) */ - -/* temporary tds */ -static uhci_td_t tmp_td[USB_MAX_TEMP_TD]; /* temporary bulk/control td's */ -static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD]; /* temporary interrupt td's */ - -static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */ - -static struct virt_root_hub rh; /* struct for root hub */ - -/********************************************************************** - * some forward decleration - */ -int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len,struct devrequest *setup); - -/* fill a td with the approproiate data. Link, status, info and buffer - * are used by the USB controller itselfes, dev is used to identify the - * "connected" device - */ -void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status, - unsigned long info, unsigned long buffer, unsigned long dev) -{ - td->link=swap_32(link); - td->status=swap_32(status); - td->info=swap_32(info); - td->buffer=swap_32(buffer); - td->dev_ptr=dev; -} - -/* fill a qh with the approproiate data. Head and element are used by the USB controller - * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh. - * Please note, that after completion of the td chain, the entry element is removed / - * marked invalid by the USB controller. - */ -void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element) -{ - qh->head=swap_32(head); - qh->element=swap_32(element); - qh->dev_ptr=0L; -} - -/* get the status of a td->status - */ -unsigned long usb_uhci_td_stat(unsigned long status) -{ - unsigned long result=0; - result |= (status & TD_CTRL_NAK) ? USB_ST_NAK_REC : 0; - result |= (status & TD_CTRL_STALLED) ? USB_ST_STALLED : 0; - result |= (status & TD_CTRL_DBUFERR) ? USB_ST_BUF_ERR : 0; - result |= (status & TD_CTRL_BABBLE) ? USB_ST_BABBLE_DET : 0; - result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0; - result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0; - result |= (status & TD_CTRL_ACTIVE) ? USB_ST_NOT_PROC : 0; - return result; -} - -/* get the status and the transfered len of a td chain. - * called from the completion handler - */ -int usb_get_td_status(uhci_td_t *td,struct usb_device *dev) -{ - unsigned long temp,info; - unsigned long stat; - uhci_td_t *mytd=td; - - if(dev->devnum==rh.devnum) - return 0; - dev->act_len=0; - stat=0; - do { - temp=swap_32((unsigned long)mytd->status); - stat=usb_uhci_td_stat(temp); - info=swap_32((unsigned long)mytd->info); - if(((info & 0xff)!= USB_PID_SETUP) && - (((info >> 21) & 0x7ff)!= 0x7ff) && - (temp & 0x7FF)!=0x7ff) - { /* if not setup and not null data pack */ - dev->act_len+=(temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */ - } - if(stat) { /* status no ok */ - dev->status=stat; - return -1; - } - temp=swap_32((unsigned long)mytd->link); - mytd=(uhci_td_t *)(temp & 0xfffffff0); - }while((temp & 0x1)==0); /* process all TDs */ - dev->status=stat; - return 0; /* Ok */ -} - - -/*------------------------------------------------------------------- - * LOW LEVEL STUFF - * assembles QHs und TDs for control, bulk and iso - *-------------------------------------------------------------------*/ - -/* Submits a control message. That is a Setup, Data and Status transfer. - * Routine does not wait for completion. - */ -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len,struct devrequest *setup) -{ - unsigned long destination, status; - int maxsze = usb_maxpacket(dev, pipe); - unsigned long dataptr; - int len; - int pktsze; - int i=0; - - if (!maxsze) { - USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe); - return -1; - } - if(((pipe>>8)&0x7f)==rh.devnum) { - /* this is the root hub -> redirect it */ - return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup); - } - USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze); - /* The "pipe" thing contains the destination in bits 8--18 */ - destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */ - /* 3 errors */ - status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); - /* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */ - /* Build the TD for the control request, try forever, 8 bytes of data */ - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev); -#if 0 - { - char *sp=(char *)setup; - printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe, - sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]); - } -#endif - dataptr = (unsigned long)buffer; - len=transfer_len; - - /* If direction is "send", change the frame from SETUP (0x2D) - to OUT (0xE1). Else change it from SETUP to IN (0x69). */ - destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN); - while (len > 0) { - /* data stage */ - pktsze = len; - i++; - if (pktsze > maxsze) - pktsze = maxsze; - destination ^= 1 << TD_TOKEN_TOGGLE; /* toggle DATA0/1 */ - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */ - tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); - - dataptr += pktsze; - len -= pktsze; - } - - /* Build the final TD for control status */ - /* It's only IN if the pipe is out AND we aren't expecting data */ - - destination &= ~UHCI_PID; - if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0)) - destination |= USB_PID_IN; - else - destination |= USB_PID_OUT; - destination |= 1 << TD_TOKEN_TOGGLE; /* End in Data1 */ - i++; - status &=~TD_CTRL_SPD; - /* no limit on errors on final packet , 0 bytes of data */ - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev); - tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); /* queue status td */ - /* usb_show_td(i+1);*/ - USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i); - /* first mark the control QH element terminated */ - qh_cntrl.element=0xffffffffL; - /* set qh active */ - qh_cntrl.dev_ptr=(unsigned long)dev; - /* fill in tmp_td_chain */ - qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]); - return 0; -} - -/*------------------------------------------------------------------- - * Prepare TDs for bulk transfers. - */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len) -{ - unsigned long destination, status,info; - unsigned long dataptr; - int maxsze = usb_maxpacket(dev, pipe); - int len; - int i=0; - - if(transfer_len < 0) { - printf("Negative transfer length in submit_bulk\n"); - return -1; - } - if (!maxsze) - return -1; - /* The "pipe" thing contains the destination in bits 8--18. */ - destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe); - /* 3 errors */ - status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); - /* ((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */ - /* Build the TDs for the bulk request */ - len = transfer_len; - dataptr = (unsigned long)buffer; - do { - int pktsze = len; - if (pktsze > maxsze) - pktsze = maxsze; - /* pktsze bytes of data */ - info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) | - (usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE); - - if((len-pktsze)==0) - status |= TD_CTRL_IOC; /* last one generates INT */ - - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */ - if(i>0) - tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); - i++; - dataptr += pktsze; - len -= pktsze; - usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)); - } while (len > 0); - /* first mark the bulk QH element terminated */ - qh_bulk.element=0xffffffffL; - /* set qh active */ - qh_bulk.dev_ptr=(unsigned long)dev; - /* fill in tmp_td_chain */ - qh_bulk.element=swap_32((unsigned long)&tmp_td[0]); - return 0; -} - - -/* search a free interrupt td - */ -uhci_td_t *uhci_alloc_int_td(void) -{ - int i; - for(i=0;i free TD */ - return &tmp_int_td[i]; - } - return NULL; -} - -#if 0 -void uhci_show_temp_int_td(void) -{ - int i; - for(i=0;i free TD */ - printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr); - } - printf("all others temp_tds are free\n"); -} -#endif -/*------------------------------------------------------------------- - * submits USB interrupt (ie. polling ;-) - */ -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval) -{ - int nint, n; - unsigned long status, destination; - unsigned long info,tmp; - uhci_td_t *mytd; - if (interval < 0 || interval >= 256) - return -1; - - if (interval == 0) - nint = 0; - else { - for (nint = 0, n = 1; nint <= 8; nint++, n += n) /* round interval down to 2^n */ - { - if(interval < n) { - interval = n / 2; - break; - } - } - nint--; - } - - USB_UHCI_PRINTF("Rounded interval to %i, chain %i\n", interval, nint); - mytd=uhci_alloc_int_td(); - if(mytd==NULL) { - printf("No free INT TDs found\n"); - return -1; - } - status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27); -/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27); -*/ - - destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21); - - info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE); - tmp = swap_32(td_int[nint].link); - usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev); - /* Link it */ - tmp = swap_32((unsigned long)mytd); - td_int[nint].link=tmp; - - usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)); - - return 0; -} - -/********************************************************************** - * Low Level functions - */ - - -void reset_hc(void) -{ - - /* Global reset for 100ms */ - out16r( usb_base_addr + USBPORTSC1,0x0204); - out16r( usb_base_addr + USBPORTSC2,0x0204); - out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS); - /* Turn off all interrupts */ - out16r(usb_base_addr + USBINTR,0); - wait_ms(50); - out16r( usb_base_addr + USBCMD,0); - wait_ms(10); -} - -void start_hc(void) -{ - int timeout = 1000; - - while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) { - if (!--timeout) { - printf("USBCMD_HCRESET timed out!\n"); - break; - } - } - /* Turn on all interrupts */ - out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP); - /* Start at frame 0 */ - out16r(usb_base_addr + USBFRNUM,0); - /* set Framebuffer base address */ - out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist); - /* Run and mark it configured with a 64-byte max packet */ - out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP); -} - -/* Initialize the skeleton - */ -void usb_init_skel(void) -{ - unsigned long temp; - int n; - - for(n=0;nstatus & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ - qh_cntrl.dev_ptr=0; - } - } - /* now process the bulk */ - if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */ - { - dev=(struct usb_device *)qh_bulk.dev_ptr; - usb_get_td_status(&tmp_td[0],dev); /* update status */ - if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ - qh_bulk.dev_ptr=0; - } - } -} - -/* check the interrupt chain, ubdate the status of the appropriate device, - * call the appropriate irqhandler and reactivate the TD if the irqhandler - * returns with 1 - */ -void usb_check_int_chain(void) -{ - int i,res; - unsigned long link,status; - struct usb_device *dev; - uhci_td_t *td,*prevtd; - - for(i=0;i<8;i++) { - prevtd=&td_int[i]; /* the first previous td is the skeleton td */ - link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */ - td=(uhci_td_t *)link; /* assign it */ - /* all interrupt TDs are finally linked to the td_int[0]. - * so we process all until we find the td_int[0]. - * if int0 chain points to a QH, we're also done - */ - while(((i>0) && (link != (unsigned long)&td_int[0])) || - ((i==0) && !(swap_32(td->link) & UHCI_PTR_QH))) - { - /* check if a device is assigned with this td */ - status=swap_32(td->status); - if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) { - /* td is not active and a device is assigned -> call irqhandler */ - dev=(struct usb_device *)td->dev_ptr; - dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */ - dev->irq_status=usb_uhci_td_stat(status); /* get status */ - res=dev->irq_handle(dev); /* call irqhandler */ - if(res==1) { - /* reactivate */ - status|=TD_CTRL_ACTIVE; - td->status=swap_32(status); - prevtd=td; /* previous td = this td */ - } - else { - prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */ - /* remove device pointer */ - td->dev_ptr=0L; - } - } /* if we call the irq handler */ - link=swap_32(td->link) & 0xfffffff0; /* next in chain */ - td=(uhci_td_t *)link; /* assign it */ - } /* process all td in this int chain */ - } /* next interrupt chain */ -} - - -/* usb interrupt service routine. - */ -void handle_usb_interrupt(void) -{ - unsigned short status; - - /* - * Read the interrupt status, and write it back to clear the - * interrupt cause - */ - - status = in16r(usb_base_addr + USBSTS); - - if (!status) /* shared interrupt, not mine */ - return; - if (status != 1) { - /* remove host controller halted state */ - if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) { - out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD)); - } - } - usb_check_int_chain(); /* call interrupt handlers for int tds */ - usb_check_skel(); /* call completion handler for common transfer routines */ - out16r(usb_base_addr+USBSTS,status); -} - - -/* init uhci - */ -int usb_lowlevel_init(void) -{ - unsigned char temp; - int busdevfunc; - - busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */ - if(busdevfunc==-1) { - printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID); - return -1; - } - pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp); - irqvec = temp; - irq_free_handler(irqvec); - USB_UHCI_PRINTF("Interrupt Line = %d, is %d\n",irqvec); - pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp); - USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp); - pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr); - USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr); - usb_base_addr&=0xFFFFFFF0; - usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS; - rh.devnum = 0; - usb_init_skel(); - reset_hc(); - start_hc(); - irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL); - return 0; -} - -/* stop uhci - */ -int usb_lowlevel_stop(void) -{ - if(irqvec==-1) - return 1; - irq_free_handler(irqvec); - reset_hc(); - irqvec=-1; - return 0; -} - -/******************************************************************************************* - * Virtual Root Hub - * Since the uhci does not have a real HUB, we simulate one ;-) - */ -#undef USB_RH_DEBUG - -#ifdef USB_RH_DEBUG -#define USB_RH_PRINTF(fmt,args...) printf (fmt ,##args) -static void usb_display_wValue(unsigned short wValue,unsigned short wIndex); -static void usb_display_Req(unsigned short req); -#else -#define USB_RH_PRINTF(fmt,args...) -static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {} -static void usb_display_Req(unsigned short req) {} -#endif - -static unsigned char root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x00, /* __u16 bcdUSB; v1.0 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x01, /* __u8 iManufacturer; */ - 0x00, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static unsigned char root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - - -static unsigned char root_hub_hub_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x29, /* __u8 bDescriptorType; Hub-descriptor */ - 0x02, /* __u8 bNbrPorts; */ - 0x00, /* __u16 wHubCharacteristics; */ - 0x00, - 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ - 0x00, /* __u8 bHubContrCurrent; 0 mA */ - 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ - 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'U', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - - -/* - * Root Hub Control Pipe (interrupt Pipes are not supported) - */ - - -int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd) -{ - void *data = buffer; - int leni = transfer_len; - int len = 0; - int status = 0; - int stat = 0; - int i; - - unsigned short cstatus; - - unsigned short bmRType_bReq; - unsigned short wValue; - unsigned short wIndex; - unsigned short wLength; - - if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { - printf("Root-Hub submit IRQ: NOT implemented\n"); -#if 0 - uhci->rh.urb = urb; - uhci->rh.send = 1; - uhci->rh.interval = urb->interval; - rh_init_int_timer (urb); -#endif - return 0; - } - bmRType_bReq = cmd->requesttype | cmd->request << 8; - wValue = swap_16(cmd->value); - wIndex = swap_16(cmd->index); - wLength = swap_16(cmd->length); - usb_display_Req(bmRType_bReq); - for (i = 0; i < 8; i++) - rh.c_p_r[i] = 0; - USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n", - dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(unsigned short *) data = swap_16(1); - len=2; - break; - case RH_GET_STATUS | RH_INTERFACE: - *(unsigned short *) data = swap_16(0); - len=2; - break; - case RH_GET_STATUS | RH_ENDPOINT: - *(unsigned short *) data = swap_16(0); - len=2; - break; - case RH_GET_STATUS | RH_CLASS: - *(unsigned long *) data = swap_32(0); - len=4; - break; /* hub power ** */ - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - - status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1)); - cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) | - ((status & USBPORTSC_PEC) >> (3 - 1)) | - (rh.c_p_r[wIndex - 1] << (0 + 4)); - status = (status & USBPORTSC_CCS) | - ((status & USBPORTSC_PE) >> (2 - 1)) | - ((status & USBPORTSC_SUSP) >> (12 - 2)) | - ((status & USBPORTSC_PR) >> (9 - 4)) | - (1 << 8) | /* power on ** */ - ((status & USBPORTSC_LSDA) << (-8 + 9)); - - *(unsigned short *) data = swap_16(status); - *(unsigned short *) (data + 2) = swap_16(cstatus); - len=4; - break; - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): - len=0; - break; - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case (RH_C_HUB_OVER_CURRENT): - len=0; /* hub power over current ** */ - break; - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - usb_display_wValue(wValue,wIndex); - switch (wValue) { - case (RH_PORT_ENABLE): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) & ~USBPORTSC_PE; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_SUSPEND): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) & ~USBPORTSC_SUSP; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_POWER): - len=0; /* port power ** */ - break; - case (RH_C_PORT_CONNECTION): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_CSC; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_C_PORT_ENABLE): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_PEC; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_C_PORT_SUSPEND): -/*** WR_RH_PORTSTAT(RH_PS_PSSC); */ - len=0; - break; - case (RH_C_PORT_OVER_CURRENT): - len=0; - break; - case (RH_C_PORT_RESET): - rh.c_p_r[wIndex - 1] = 0; - len=0; - break; - } - break; - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - usb_display_wValue(wValue,wIndex); - switch (wValue) { - case (RH_PORT_SUSPEND): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_SUSP; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_RESET): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_PR; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - wait_ms(10); - status = (status & 0xfff5) & ~USBPORTSC_PR; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - udelay(10); - status = (status & 0xfff5) | USBPORTSC_PE; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - wait_ms(10); - status = (status & 0xfff5) | 0xa; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_POWER): - len=0; /* port power ** */ - break; - case (RH_PORT_ENABLE): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_PE; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - } - break; - - case RH_SET_ADDRESS: - rh.devnum = wValue; - len=0; - break; - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - i=sizeof(root_hub_config_des); - status=i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_dev_des, len); - break; - case (0x02): /* configuration descriptor */ - i=sizeof(root_hub_config_des); - status=i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_config_des, len); - break; - case (0x03): /*string descriptors */ - if(wValue==0x0300) { - i=sizeof(root_hub_str_index0); - status = i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_str_index0, len); - break; - } - if(wValue==0x0301) { - i=sizeof(root_hub_str_index1); - status = i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_str_index1, len); - break; - } - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - root_hub_hub_des[2] = 2; - i=sizeof(root_hub_hub_des); - status= i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_hub_des, len); - break; - case RH_GET_CONFIGURATION: - *(unsigned char *) data = 0x01; - len = 1; - break; - case RH_SET_CONFIGURATION: - len=0; - break; - default: - stat = USB_ST_STALLED; - } - USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat, - in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2)); - dev->act_len=len; - dev->status=stat; - return stat; - -} - -/******************************************************************************** - * Some Debug Routines - */ - -#ifdef USB_RH_DEBUG - -static void usb_display_Req(unsigned short req) -{ - USB_RH_PRINTF("- Root-Hub Request: "); - switch (req) { - case RH_GET_STATUS: - USB_RH_PRINTF("Get Status "); - break; - case RH_GET_STATUS | RH_INTERFACE: - USB_RH_PRINTF("Get Status Interface "); - break; - case RH_GET_STATUS | RH_ENDPOINT: - USB_RH_PRINTF("Get Status Endpoint "); - break; - case RH_GET_STATUS | RH_CLASS: - USB_RH_PRINTF("Get Status Class"); - break; /* hub power ** */ - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - USB_RH_PRINTF("Get Status Class Others"); - break; - case RH_CLEAR_FEATURE | RH_ENDPOINT: - USB_RH_PRINTF("Clear Feature Endpoint "); - break; - case RH_CLEAR_FEATURE | RH_CLASS: - USB_RH_PRINTF("Clear Feature Class "); - break; - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - USB_RH_PRINTF("Clear Feature Other Class "); - break; - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - USB_RH_PRINTF("Set Feature Other Class "); - break; - case RH_SET_ADDRESS: - USB_RH_PRINTF("Set Address "); - break; - case RH_GET_DESCRIPTOR: - USB_RH_PRINTF("Get Descriptor "); - break; - case RH_GET_DESCRIPTOR | RH_CLASS: - USB_RH_PRINTF("Get Descriptor Class "); - break; - case RH_GET_CONFIGURATION: - USB_RH_PRINTF("Get Configuration "); - break; - case RH_SET_CONFIGURATION: - USB_RH_PRINTF("Get Configuration "); - break; - default: - USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req); - } - USB_RH_PRINTF("\n"); - -} - -static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) -{ - switch (wValue) { - case (RH_PORT_ENABLE): - USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex); - break; - case (RH_PORT_SUSPEND): - USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex); - break; - case (RH_PORT_POWER): - USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex); - break; - case (RH_C_PORT_CONNECTION): - USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex); - break; - case (RH_C_PORT_ENABLE): - USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex); - break; - case (RH_C_PORT_SUSPEND): - USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex); - break; - case (RH_C_PORT_OVER_CURRENT): - USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex); - break; - case (RH_C_PORT_RESET): - USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex); - break; - default: - USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex); - break; - } -} - -#endif - - -#ifdef USB_UHCI_DEBUG - -static int usb_display_td(uhci_td_t *td) -{ - unsigned long tmp; - int valid; - - printf("TD at %p:\n",td); - - tmp=swap_32(td->link); - printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0, - ((tmp & 0x4)==0x4) ? "Depth" : "Breath", - ((tmp & 0x2)==0x2) ? "QH" : "TD", - ((tmp & 0x1)==0x1) ? "invalid" : "valid"); - valid=((tmp & 0x1)==0x0); - tmp=swap_32(td->status); - printf(" %s %ld Errors %s %s %s \n %s %s %s %s %s %s\n Len 0x%lX\n", - (((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable", - ((tmp>>28)&0x3), - (((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed", - (((tmp>>25)&0x1)==0x1) ? "ISO " : "", - (((tmp>>24)&0x1)==0x1) ? "IOC " : "", - (((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ", - (((tmp>>22)&0x1)==0x1) ? "Stalled" : "", - (((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "", - (((tmp>>20)&0x1)==0x1) ? "Babble" : "", - (((tmp>>19)&0x1)==0x1) ? "NAK" : "", - (((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "", - (tmp&0x7ff)); - tmp=swap_32(td->info); - printf(" MaxLen 0x%lX\n",((tmp>>21)&0x7FF)); - printf(" %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "", - ((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF); - tmp=swap_32(td->buffer); - printf(" Buffer 0x%08lX\n",tmp); - printf(" DEV %08lX\n",td->dev_ptr); - return valid; -} - - -void usb_show_td(int max) -{ - int i; - if(max>0) { - for(i=0;i: */ -#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ -#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ -#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ -#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ -#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ -#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ -#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ -#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ -#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ -#define TD_CTRL_NAK (1 << 19) /* NAK Received */ -#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ -#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ -#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */ - -#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ - TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF) - -#define TD_TOKEN_TOGGLE 19 - -/* ------------------------------------------------------------------------------------ - Virtual Root HUB - ------------------------------------------------------------------------------------ */ -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -/* Our Vendor Specific feature */ -#define RH_REMOVE_EP 0x00 - - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* Transfer descriptor structure */ -typedef struct { - unsigned long link; /* next td/qh (LE)*/ - unsigned long status; /* status of the td */ - unsigned long info; /* Max Lenght / Endpoint / device address and PID */ - unsigned long buffer; /* pointer to data buffer (LE) */ - unsigned long dev_ptr; /* pointer to the assigned device (BE) */ - unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */ -} uhci_td_t, *puhci_td_t; - -/* Queue Header structure */ -typedef struct { - unsigned long head; /* Next QH (LE)*/ - unsigned long element; /* Queue element pointer (LE) */ - unsigned long res[5]; /* reserved */ - unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */ -} uhci_qh_t, *puhci_qh_t; - -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - int numports; /* number of ports */ - int c_p_r[8]; /* C_PORT_RESET */ -}; - - -#endif /* _USB_UHCI_H_ */ diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile deleted file mode 100644 index 9276f64..0000000 --- a/board/mpl/mip405/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \ - ../common/usb_uhci.o ../common/memtst.o ../common/common_util.o - -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c deleted file mode 100644 index 6fbc585..0000000 --- a/board/mpl/mip405/cmd_mip405.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * hacked for MIP405 - */ - -#include -#include -#include "mip405.h" -#include "../common/common_util.h" - - -extern void print_mip405_info(void); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - - -/* ------------------------------------------------------------------------- */ - -int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - - ulong led_on; - - if (strcmp(argv[1], "info") == 0) - { - print_mip405_info(); - return 0; - } - if (strcmp(argv[1], "led") == 0) - { - led_on = (ulong)simple_strtoul(argv[2], NULL, 10); - user_led0(led_on); - return 0; - } - return (do_mplcommon(cmdtp, flag, argc, argv)); -} -U_BOOT_CMD( - mip405, 8, 1, do_mip405, - "mip405 - MIP405 specific Cmds\n", - "flash mem [SrcAddr] - updates U-Boot with image in memory\n" - "mip405 flash mps - updates U-Boot with image from MPS\n" - "mip405 info - displays board information\n" - "mip405 led - switches LED on (on=1) or off (on=0)\n" - "mip405 mem [cnt] - Memory Test -times, = -1 loop forever\n" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/mip405/config.mk b/board/mpl/mip405/config.mk deleted file mode 100644 index 0f8d153..0000000 --- a/board/mpl/mip405/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0xFFF80000 diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S deleted file mode 100644 index 3351b5b..0000000 --- a/board/mpl/mip405/init.S +++ /dev/null @@ -1,233 +0,0 @@ -/*------------------------------------------------------------------------------+ - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *-------------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * Function: ext_bus_cntlr_init - * Description: Initializes the External Bus Controller for the external - * peripherals. IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * Bank 0 - Flash or Multi Purpose Socket - * Bank 1 - Multi Purpose Socket or Flash (set in C-Code) - * Bank 2 - UART 1 (set in C-Code) - * Bank 3 - UART 2 (set in C-Code) - * Bank 4 - not used - * Bank 5 - not used - * Bank 6 - not used - * Bank 7 - PLD Register - *-----------------------------------------------------------------------------*/ -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include -#include - -#include -#include -#include "mip405.h" - - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - mfdcr r3,strap /* get strapping reg */ - andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ - bnelr /* jump back if PCI boot */ - - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 14; used to prefetch */ - mtctr r4 /* 14 cache lines to fit this function */ - /* in cache (gives us 8x14=112 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 14 cache lines */ - - /*------------------------------------------------------------------- - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. - *------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /*----------------------------------------------------------------------- - * decide boot up mode - *----------------------------------------------------------------------- */ - addi r4,0,pb0cr - mtdcr ebccfga,r4 - mfdcr r4,ebccfgd - - andi. r0, r4, 0x2000 /* mask out irrelevant bits */ - beq 0f /* jump if 8 bit bus width */ - - /* setup 16 bit things - *----------------------------------------------------------------------- - * Memory Bank 0 (16 Bit Flash) initialization - *---------------------------------------------------------------------- */ - - addi r4,0,pb0ap - mtdcr ebccfga,r4 - addis r4,0,(FLASH_AP_B)@h - ori r4,r4,(FLASH_AP_B)@l - mtdcr ebccfgd,r4 - - addi r4,0,pb0cr - mtdcr ebccfga,r4 - /* BS=0x010(4MB),BU=0x3(R/W), */ - addis r4,0,(FLASH_CR_B)@h - ori r4,r4,(FLASH_CR_B)@l - mtdcr ebccfgd,r4 - b 1f - -0: - - /* 8Bit boot mode: */ - /*----------------------------------------------------------------------- - * Memory Bank 0 Multi Purpose Socket initialization - *----------------------------------------------------------------------- */ - /* 0x7F8FFE80 slowest boot */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 - addis r4,0,(MPS_AP_B)@h - ori r4,r4,(MPS_AP_B)@l - mtdcr ebccfgd,r4 - - addi r4,0,pb0cr - mtdcr ebccfga,r4 - /* BS=0x010(4MB),BU=0x3(R/W), */ - addis r4,0,(MPS_CR_B)@h - ori r4,r4,(MPS_CR_B)@l - - mtdcr ebccfgd,r4 - - -1: - /*----------------------------------------------------------------------- - * Memory Bank 2-3-4-5-6 (not used) initialization - *-----------------------------------------------------------------------*/ - addi r4,0,pb1cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb2cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb3cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb4cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb5cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb6cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb7cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - nop /* pass2 DCR errata #8 */ - blr - -/*----------------------------------------------------------------------------- - * Function: sdram_init - * Description: Configures the internal SRAM memory. and setup the - * Stackpointer in it. - *----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - - - blr - - -#if defined(CONFIG_BOOT_PCI) - .section .bootpg,"ax" - .globl _start_pci -/******************************************* - */ - -_start_pci: - /* first handle errata #68 / PCI_18 */ - iccci r0, r0 /* invalidate I-cache */ - lis r31, 0 - mticcr r31 /* ICCR = 0 (all uncachable) */ - isync - - mfccr0 r28 /* set CCR0[24] = 1 */ - ori r28, r28, 0x0080 - mtccr0 r28 - - /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ - lis r28, 0xEF40 - addi r28, r28, 0x0004 - stw r31, 0x0C(r28) /* clear PMM0PCIHA */ - lis r29, 0xFFF8 /* open 512 kByte */ - addi r29, r29, 0x0001/* and enable this region */ - stwbrx r29, r0, r28 /* write PMM0MA */ - - lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ - addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ - - lis r31, 0x8000 /* set en bit bus 0 */ - ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ - stwbrx r31, r0, r28 /* write it */ - - lwbrx r31, r0, r29 /* load XBCS register */ - oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ - stwbrx r31, r0, r29 /* write back XBCS register */ - - nop - nop - b _start /* normal start */ -#endif diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c deleted file mode 100644 index 9c469b0..0000000 --- a/board/mpl/mip405/mip405.c +++ /dev/null @@ -1,820 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - * TODO: clean-up - */ - -/* - * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM? - * - * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being - * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum - * parameters from the datasheet are: - * Tclk = 7.5ns (CL = 2) - * Trp = 15ns - * Trc = 60ns - * Trcd = 15ns - * Trfc = 66ns - * - * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock - * period is 10ns and the parameters needed for the Timing Register are: - * CASL = CL = 2 clock cycles - * PTA = Trp = 15ns / 10ns = 2 clock cycles - * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles - * LDF = 2 clock cycles (but can be extended to meet board-level timing) - * RFTA = Trfc = 66ns / 10ns= 7 clock cycles - * RCD = Trcd = 15ns / 10ns= 2 clock cycles - * - * The actual bit settings in the register would be: - * - * CASL = 0b01 - * PTA = 0b01 - * CTP = 0b10 - * LDF = 0b01 - * RFTA = 0b011 - * RCD = 0b01 - * - * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc - * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay - * defined as Trc rather than Trfc. - * When using DIMM modules, most but not all of the required timing parameters can be read - * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc - * are not available from the EEPROM - */ - -#include -#include "mip405.h" -#include -#include <405gp_i2c.h> -#include -#include "../common/common_util.h" -#include -#include -extern block_dev_desc_t * scsi_get_dev(int dev); -extern block_dev_desc_t * ide_get_dev(int dev); - -#undef SDRAM_DEBUG -#define ENABLE_ECC /* for ecc boards */ -#define FALSE 0 -#define TRUE 1 - -/* stdlib.h causes some compatibility problems; should fixe these! -- wd */ -#ifndef __ldiv_t_defined -typedef struct { - long int quot; /* Quotient */ - long int rem; /* Remainder */ -} ldiv_t; -extern ldiv_t ldiv (long int __numer, long int __denom); -# define __ldiv_t_defined 1 -#endif - - -#define PLD_PART_REG PER_PLD_ADDR + 0 -#define PLD_VERS_REG PER_PLD_ADDR + 1 -#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 -#define PLD_IRQ_REG PER_PLD_ADDR + 3 -#define PLD_COM_MODE_REG PER_PLD_ADDR + 4 -#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 - -#define MEGA_BYTE (1024*1024) - -typedef struct { - unsigned char boardtype; /* Board revision and Population Options */ - unsigned char cal; /* cas Latency (will be programmend as cal-1) */ - unsigned char trp; /* datain27 in clocks */ - unsigned char trcd; /* datain29 in clocks */ - unsigned char tras; /* datain30 in clocks */ - unsigned char tctp; /* tras - trcd in clocks */ - unsigned char am; /* Address Mod (will be programmed as am-1) */ - unsigned char sz; /* log binary => Size = (4MByte<baudrate = 9600; - serial_init (); -#endif - serial_puts ("\n"); - serial_puts (s); - serial_puts ("\n enable SDRAM_DEBUG for more info\n"); - for (;;); -} - - -unsigned char get_board_revcfg (void) -{ - out8 (PER_BOARD_ADDR, 0); - return (in8 (PER_BOARD_ADDR)); -} - - -#ifdef SDRAM_DEBUG - -void write_hex (unsigned char i) -{ - char cc; - - cc = i >> 4; - cc &= 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); - cc = i & 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); -} - -void write_4hex (unsigned long val) -{ - write_hex ((unsigned char) (val >> 24)); - write_hex ((unsigned char) (val >> 16)); - write_hex ((unsigned char) (val >> 8)); - write_hex ((unsigned char) val); -} - -#endif - - -int init_sdram (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned long tmp, baseaddr; - unsigned short i; - unsigned char trp_clocks, - trcd_clocks, - tras_clocks, - trc_clocks, - tctp_clocks; - unsigned char cal_val; - unsigned char bc; - unsigned long sdram_tim, sdram_bank; - - /*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/ - (void) get_clocks (); - gd->baudrate = 9600; - serial_init (); - /* set up the pld */ - mtdcr (ebccfga, pb7ap); - mtdcr (ebccfgd, PLD_AP); - mtdcr (ebccfga, pb7cr); - mtdcr (ebccfgd, PLD_CR); - /* THIS IS OBSOLETE */ - /* set up the board rev reg*/ - mtdcr (ebccfga, pb5ap); - mtdcr (ebccfgd, BOARD_AP); - mtdcr (ebccfga, pb5cr); - mtdcr (ebccfgd, BOARD_CR); -#ifdef SDRAM_DEBUG - /* get all informations from PLD */ - serial_puts ("\nPLD Part 0x"); - bc = in8 (PLD_PART_REG); - write_hex (bc); - serial_puts ("\nPLD Vers 0x"); - bc = in8 (PLD_VERS_REG); - write_hex (bc); - serial_puts ("\nBoard Rev 0x"); - bc = in8 (PLD_BOARD_CFG_REG); - write_hex (bc); - serial_puts ("\n"); -#endif - /* check board */ - bc = in8 (PLD_PART_REG); -#if defined(CONFIG_MIP405T) - if((bc & 0x80)==0) - SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n"); -#else - if((bc & 0x80)==0x80) - SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n"); -#endif - /* set-up the chipselect machine */ - mtdcr (ebccfga, pb0cr); /* get cs0 config reg */ - tmp = mfdcr (ebccfgd); - if ((tmp & 0x00002000) == 0) { - /* MPS Boot, set up the flash */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, FLASH_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, FLASH_CR); - } else { - /* Flash boot, set up the MPS */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, MPS_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, MPS_CR); - } - /* set up UART0 (CS2) and UART1 (CS3) */ - mtdcr (ebccfga, pb2ap); - mtdcr (ebccfgd, UART0_AP); - mtdcr (ebccfga, pb2cr); - mtdcr (ebccfgd, UART0_CR); - mtdcr (ebccfga, pb3ap); - mtdcr (ebccfgd, UART1_AP); - mtdcr (ebccfga, pb3cr); - mtdcr (ebccfgd, UART1_CR); - bc = in8 (PLD_BOARD_CFG_REG); -#ifdef SDRAM_DEBUG - serial_puts ("\nstart SDRAM Setup\n"); - serial_puts ("\nBoard Rev: "); - write_hex (bc); - serial_puts ("\n"); -#endif - i = 0; - baseaddr = CFG_SDRAM_BASE; - while (sdram_table[i].sz != 0xff) { - if (sdram_table[i].boardtype == bc) - break; - i++; - } - if (sdram_table[i].boardtype != bc) - SDRAM_err ("No SDRAM table found for this board!!!\n"); -#ifdef SDRAM_DEBUG - serial_puts (" found table "); - write_hex (i); - serial_puts (" \n"); -#endif - /* since the ECC initialisation needs some time, - * we show that we're alive - */ - if (sdram_table[i].ecc) - serial_puts ("\nInitializing SDRAM, Please stand by"); - cal_val = sdram_table[i].cal - 1; /* Cas Latency */ - trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */ - trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ - tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ - /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ - tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */ - /* trc_clocks is sum of trp_clocks + tras_clocks */ - trc_clocks = trp_clocks + tras_clocks; - /* get SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - sdram_tim = mfdcr (memcfgd) & ~0x018FC01F; - /* insert CASL value */ - sdram_tim |= ((unsigned long) (cal_val)) << 23; - /* insert PTA value */ - sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18; - /* insert CTP value */ - sdram_tim |= - ((unsigned long) (trc_clocks - trp_clocks - - trcd_clocks)) << 16; - /* insert LDF (always 01) */ - sdram_tim |= ((unsigned long) 0x01) << 14; - /* insert RFTA value */ - sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2; - /* insert RCD value */ - sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0; - - tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */ - /* insert SZ value; */ - tmp |= ((unsigned long) sdram_table[i].sz << 17); - /* get SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001; - sdram_bank |= (baseaddr | tmp | 0x01); - -#ifdef SDRAM_DEBUG - serial_puts ("sdtr: "); - write_4hex (sdram_tim); - serial_puts ("\n"); -#endif - - /* write SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, sdram_tim); - -#ifdef SDRAM_DEBUG - serial_puts ("mb0cf: "); - write_4hex (sdram_bank); - serial_puts ("\n"); -#endif - - /* write SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, sdram_bank); - - if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ - /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; - tmp |= 0x07F00000; - } else { - /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; - tmp |= 0x05F00000; - } - /* write SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, tmp); - /* enable ECC if used */ -#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) - if (sdram_table[i].ecc) { - /* disable checking for all banks */ - unsigned long *p; -#ifdef SDRAM_DEBUG - serial_puts ("disable ECC.. "); -#endif - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); - tmp &= 0xff0fffff; /* disable all banks */ - mtdcr (memcfga, mem_ecccf); - /* set up SDRAM Controller with ECC enabled */ -#ifdef SDRAM_DEBUG - serial_puts ("setup SDRAM Controller.. "); -#endif - mtdcr (memcfgd, tmp); - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); - udelay (600); -#ifdef SDRAM_DEBUG - serial_puts ("fill the memory..\n"); -#endif - serial_puts ("."); - /* now, fill all the memory */ - tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz); - p = (unsigned long) 0; - while ((unsigned long) p < tmp) { - *p++ = 0L; - if (!((unsigned long) p % 0x00800000)) /* every 8MByte */ - serial_puts ("."); - } - /* enable bank 0 */ - serial_puts ("."); -#ifdef SDRAM_DEBUG - serial_puts ("enable ECC\n"); -#endif - udelay (400); - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); - tmp |= 0x00800000; /* enable bank 0 */ - mtdcr (memcfgd, tmp); - udelay (400); - } else -#endif - { - /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); - udelay (400); - } - serial_puts ("\n"); - return (0); -} - -int board_early_init_f (void) -{ - init_sdram (); - - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the PIP405 board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive - | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive - | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for MIP405 board: - | An interrupt taken for the SouthBridge (IRQ 25) indicates that - | the Interrupt Controller in the South Bridge has caused the - | interrupt. The IC must be read to determine which device - | caused the interrupt. - | - +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - return 0; -} - - -/* - * Get some PLD Registers - */ - -unsigned short get_pld_parvers (void) -{ - unsigned short result; - unsigned char rc; - - rc = in8 (PLD_PART_REG); - result = (unsigned short) rc << 8; - rc = in8 (PLD_VERS_REG); - result |= rc; - return result; -} - - -void user_led0 (unsigned char on) -{ - if (on) - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4)); - else - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb)); -} - - -void ide_set_reset (int idereset) -{ - /* if reset = 1 IDE reset will be asserted */ - if (idereset) - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1)); - else { - udelay (10000); - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe)); - } -} - - -/* ------------------------------------------------------------------------- */ - -void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var) -{ -#if !defined(CONFIG_MIP405T) - unsigned char bc,rc,tmp; - int i; - - bc = in8 (PLD_BOARD_CFG_REG); - tmp = ~bc; - tmp &= 0xf; - rc = 0; - for (i = 0; i < 4; i++) { - rc <<= 1; - rc += (tmp & 0x1); - tmp >>= 1; - } - rc++; - if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */ - || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */ - && (rc==0x1)) /* Population Option 1 is a -3 */ - rc=3; - *pcbrev=(bc >> 4) & 0xf; - *var=rc; -#else - unsigned char bc; - bc = in8 (PLD_BOARD_CFG_REG); - *pcbrev=(bc >> 4) & 0xf; - *var=16-(bc & 0xf); -#endif -} - -/* - * Check Board Identity: - */ -/* serial String: "MIP405_1000" OR "MIP405T_1000" */ -#if !defined(CONFIG_MIP405T) -#define BOARD_NAME "MIP405" -#else -#define BOARD_NAME "MIP405T" -#endif - -int checkboard (void) -{ - char s[50]; - unsigned char bc, var; - int i; - backup_t *b = (backup_t *) s; - - puts ("Board: "); - get_pcbrev_var(&bc,&var); - i = getenv_r ("serial#", (char *)s, 32); - if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) { - get_backup_values (b); - if (strncmp (b->signature, "MPL\0", 4) != 0) { - puts ("### No HW ID - assuming " BOARD_NAME); - printf ("-%d Rev %c", var, 'A' + bc); - } else { - b->serial_name[sizeof(BOARD_NAME)-1] = 0; - printf ("%s-%d Rev %c SN: %s", b->serial_name, var, - 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]); - } - } else { - s[sizeof(BOARD_NAME)-1] = 0; - printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc, - &s[sizeof(BOARD_NAME)]); - } - bc = in8 (PLD_EXT_CONF_REG); - printf (" Boot Config: 0x%x\n", bc); - return (0); -} - - -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -/* - initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of - the necessary info for SDRAM controller configuration -*/ -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -static int test_dram (unsigned long ramsize); - -long int initdram (int board_type) -{ - - unsigned long bank_reg[4], tmp, bank_size; - int i, ds; - unsigned long TotalSize; - - ds = 0; - /* since the DRAM controller is allready set up, calculate the size with the - bank registers */ - mtdcr (memcfga, mem_mb0cf); - bank_reg[0] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb1cf); - bank_reg[1] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb2cf); - bank_reg[2] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb3cf); - bank_reg[3] = mfdcr (memcfgd); - TotalSize = 0; - for (i = 0; i < 4; i++) { - if ((bank_reg[i] & 0x1) == 0x1) { - tmp = (bank_reg[i] >> 17) & 0x7; - bank_size = 4 << tmp; - TotalSize += bank_size; - } else - ds = 1; - } - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); - - if (!tmp) - printf ("No "); - printf ("ECC "); - - test_dram (TotalSize * MEGA_BYTE); - return (TotalSize * MEGA_BYTE); -} - -/* ------------------------------------------------------------------------- */ - - -static int test_dram (unsigned long ramsize) -{ -#ifdef SDRAM_DEBUG - mem_test (0L, ramsize, 1); -#endif - /* not yet implemented */ - return (1); -} - -/* used to check if the time in RTC is valid */ -static unsigned long start; -static struct rtc_time tm; -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - /* adjust flash start and size as well as the offset */ - gd->bd->bi_flashstart=0-flash_info[0].size; - gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN; - gd->bd->bi_flashoffset=0; - - /* check, if RTC is running */ - rtc_get (&tm); - start=get_timer(0); - /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ - if (mfdcr(strap) & PSR_ROM_LOC) - mtspr(ccr0, (mfspr(ccr0) & ~0x80)); - - return (0); -} - - -void print_mip405_rev (void) -{ - unsigned char part, vers, pcbrev, var; - - get_pcbrev_var(&pcbrev,&var); - part = in8 (PLD_PART_REG); - vers = in8 (PLD_VERS_REG); - printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n", - var, pcbrev + 'A', part & 0x7F, vers); -} - - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - return 0; /* No hotkeys supported */ -} -#endif - -extern void mem_test_reloc(void); -extern int mk_date (char *, struct rtc_time *); - -int last_stage_init (void) -{ - unsigned long stop; - struct rtc_time newtm; - char *s; - mem_test_reloc(); - /* write correct LED configuration */ - if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) { - printf ("Error writing to the PHY\n"); - } - /* since LED/CFG2 is not connected on the -2, - * write to correct capability information */ - if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) { - printf ("Error writing to the PHY\n"); - } - print_mip405_rev (); - show_stdio_dev (); - check_env (); - /* check if RTC time is valid */ - stop=get_timer(start); - while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */ - udelay(1000); - stop=get_timer(start); - } - rtc_get (&newtm); - if(tm.tm_sec==newtm.tm_sec) { - s=getenv("defaultdate"); - if(!s) - mk_date ("010112001970", &newtm); - else - if(mk_date (s, &newtm)!=0) { - printf("RTC: Bad date format in defaultdate\n"); - return 0; - } - rtc_reset (); - rtc_set(&newtm); - } - return 0; -} - -/*************************************************************************** - * some helping routines - */ - -int overwrite_console (void) -{ - return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */ -} - - -/************************************************************************ -* Print MIP405 Info -************************************************************************/ -void print_mip405_info (void) -{ - unsigned char part, vers, cfg, irq_reg, com_mode, ext; - - part = in8 (PLD_PART_REG); - vers = in8 (PLD_VERS_REG); - cfg = in8 (PLD_BOARD_CFG_REG); - irq_reg = in8 (PLD_IRQ_REG); - com_mode = in8 (PLD_COM_MODE_REG); - ext = in8 (PLD_EXT_CONF_REG); - - printf ("PLD Part %d version %d\n", part & 0x7F, vers); - printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A'); - printf ("Population Options %d %d %d %d\n", (cfg) & 0x1, - (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1); - printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off"); - printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3); -#if !defined(CONFIG_MIP405T) - printf ("User Config Switch %d %d %d %d %d %d %d %d\n", - (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, - (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, - (ext >> 6) & 0x1, (ext >> 7) & 0x1); - printf ("SER1 uses handshakes %s\n", - (ext & 0x80) ? "DTR/DSR" : "RTS/CTS"); -#else - printf ("User Config Switch %d %d %d %d %d %d %d %d\n", - (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, - (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, - (ext >> 6) & 0x1,(ext >> 7) & 0x1); -#endif - printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted"); - printf ("IRQs:\n"); - printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active"); -#if !defined(CONFIG_MIP405T) - printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active"); - printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active"); -#endif - printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active"); - printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active"); - printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active"); -} diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h deleted file mode 100644 index b1d91de..0000000 --- a/board/mpl/mip405/mip405.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - /**************************************************************************** - * Global routines used for MIP405 - *****************************************************************************/ -#ifndef __ASSEMBLY__ -/*int switch_cs(unsigned char boot);*/ - -extern int mem_test(unsigned long start, unsigned long ramsize,int mode); - -void user_led0(unsigned char on); - - -#endif -/* timings */ -/* PLD (CS7) */ -#define PLD_BME 0 /* Burst disable */ -#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */ -#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define PLD_OEN 1 /* Cycles from CS low to OE low */ -#define PLD_WBN 1 /* Cycles from CS low to WE low */ -#define PLD_WBF 1 /* Cycles from WE high to CS high */ -#define PLD_TH 2 /* Number of hold cycles after transfer */ -#define PLD_RE 0 /* Ready disabled */ -#define PLD_SOR 1 /* Sample on Ready disabled */ -#define PLD_BEM 0 /* Byte Write only active on Write cycles */ -#define PLD_PEN 0 /* Parity disable */ -#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \ - (PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define PLD_BS 0 /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define PLD_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define PLD_BW 0 /* 16Bit */ -#define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13)) - - -/* timings */ - -#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024)) -/* Dummy CS to get the board revision */ -#define BOARD_BME 0 /* Burst disable */ -#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ -#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define BOARD_OEN 1 /* Cycles from CS low to OE low */ -#define BOARD_WBN 1 /* Cycles from CS low to WE low */ -#define BOARD_WBF 1 /* Cycles from WE high to CS high */ -#define BOARD_TH 2 /* Number of hold cycles after transfer */ -#define BOARD_RE 0 /* Ready disabled */ -#define BOARD_SOR 1 /* Sample on Ready disabled */ -#define BOARD_BEM 0 /* Byte Write only active on Write cycles */ -#define BOARD_PEN 0 /* Parity disable */ -#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \ - (BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define BOARD_BS 0 /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define BOARD_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define BOARD_BW 0 /* 16Bit */ -#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13)) - - -/* UART0 CS2 */ -#define UART0_BME 0 /* Burst disable */ -#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */ -#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define UART0_OEN 1 /* Cycles from CS low to OE low */ -#define UART0_WBN 1 /* Cycles from CS low to WE low */ -#define UART0_WBF 1 /* Cycles from WE high to CS high */ -#define UART0_TH 2 /* Number of hold cycles after transfer */ -#define UART0_RE 0 /* Ready disabled */ -#define UART0_SOR 1 /* Sample on Ready disabled */ -#define UART0_BEM 0 /* Byte Write only active on Write cycles */ -#define UART0_PEN 0 /* Parity disable */ -#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \ - (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define UART0_BS 0 /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define UART0_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define UART0_BW 0 /* 8Bit */ -#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13)) - -/* UART1 CS3 */ -#define UART1_AP UART0_AP /* same timing as UART0 */ -#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13)) - - -/* Flash CS0 or CS 1 */ -/* 0x7F8FFE80 slowest timing at all... */ -#define FLASH_BME_B 1 /* Burst enable */ -#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ -#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define FLASH_BME 0 /* Burst disable */ -#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ -#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define FLASH_OEN 1 /* Cycles from CS low to OE low */ -#define FLASH_WBN 1 /* Cycles from CS low to WE low */ -#define FLASH_WBF 1 /* Cycles from WE high to CS high */ -#define FLASH_TH 2 /* Number of hold cycles after transfer */ -#define FLASH_RE 0 /* Ready disabled */ -#define FLASH_SOR 1 /* Sample on Ready disabled */ -#define FLASH_BEM 0 /* Byte Write only active on Write cycles */ -#define FLASH_PEN 0 /* Parity disable */ -/* Access Parameter Register for non Boot */ -#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ - (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) -/* Access Parameter Register for Boot */ -#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ - (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define FLASH_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define FLASH_BW 1 /* 16Bit */ -/* CR register for Boot */ -#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) -/* CR register for non Boot */ -#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) - -/* MPS CS1 or CS0 */ -/* Boot CS: */ -#define MPS_BME_B 1 /* Burst enable */ -#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ -#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define MPS_BME 0 /* Burst disable */ -#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ -#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define MPS_OEN 1 /* Cycles from CS low to OE low */ -#define MPS_WBN 1 /* Cycles from CS low to WE low */ -#define MPS_WBF 1 /* Cycles from WE high to CS high */ -#define MPS_TH 2 /* Number of hold cycles after transfer */ -#define MPS_RE 0 /* Ready disabled */ -#define MPS_SOR 1 /* Sample on Ready disabled */ -#define MPS_BEM 0 /* Byte Write only active on Write cycles */ -#define MPS_PEN 0 /* Parity disable */ -/* Access Parameter Register for non Boot */ -#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ - (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) -/* Access Parameter Register for Boot */ -#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ - (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define MPS_BS 2 /* 4 MByte */ -#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define MPS_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define MPS_BW 0 /* 8Bit */ -/* CR register for Boot */ -#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13)) -/* CR register for non Boot */ -#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) diff --git a/board/mpl/mip405/u-boot.lds b/board/mpl/mip405/u-boot.lds deleted file mode 100644 index ad5f273..0000000 --- a/board/mpl/mip405/u-boot.lds +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - .bootpg 0xFFFFF000 : - { - board/mpl/mip405/init.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/mpl/mip405/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile deleted file mode 100644 index 1a9ce12..0000000 --- a/board/mpl/pati/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de -# -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o -#### cmd_pati.o -SOBJS := - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c deleted file mode 100644 index 98429c0..0000000 --- a/board/mpl/pati/cmd_pati.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Adapted for PATI - */ - -#include -#include -#define PLX9056_LOC -#include "plx9056.h" -#include "pati.h" -#include "pci_eeprom.h" - -extern void show_pld_regs(void); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -extern void user_led0(int led_on); -extern void user_led1(int led_on); - -/* ------------------------------------------------------------------------- */ -#if defined(CFG_PCI_CON_DEVICE) -extern void pci_con_disc(void); -extern void pci_con_connect(void); -#endif - -/****************************************************************************** - * Eeprom Support - ******************************************************************************/ -unsigned long get32(unsigned long addr) -{ - unsigned long *p=(unsigned long *)addr; - return *p; -} - -void set32(unsigned long addr,unsigned long data) -{ - unsigned long *p=(unsigned long *)addr; - *p=data; -} - -#define PCICFG_GET_REG(x) (get32((x) + PCI_CONFIG_BASE)) -#define PCICFG_SET_REG(x,y) (set32((x) + PCI_CONFIG_BASE,(y))) - - -/****************************************************************************** - * reload_pci_eeprom - ******************************************************************************/ - -static void reload_pci_eeprom(void) -{ - unsigned long reg; - /* Set Bit 29 and clear it again */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - udelay(1); - /* set it*/ - reg|=(1<<29); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - /* EECLK @ 33MHz = 125kHz - * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec - * use 20msec - */ - udelay(20000); /* wait 20ms */ - reg &= ~(1<<29); /* set it low */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ -} - -/****************************************************************************** - * clock_pci_eeprom - ******************************************************************************/ - -static void clock_pci_eeprom(void) -{ - unsigned long reg; - /* clock is low, data is valid */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - udelay(1); - /* set clck high */ - reg|=(1<<24); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ - reg &= ~(1<<24); /* set clock low */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ -} - -/****************************************************************************** - * send_pci_eeprom_cmd - ******************************************************************************/ -static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len) -{ - unsigned long reg; - int i; - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Clear all EEPROM bits */ - reg &= ~(0xF << 24); - /* Toggle EEPROM's Chip select to get it out of Shift Register Mode */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ - /* Enable EEPROM Chip Select */ - reg |= (1 << 25); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - /* Send EEPROM command - one bit at a time */ - for (i = (int)(len-1); i >= 0; i--) { - /* Check if current bit is 0 or 1 */ - if (cmd & (1 << i)) - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); - else - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - clock_pci_eeprom(); - } -} - -/****************************************************************************** - * write_pci_eeprom_offs - ******************************************************************************/ -static void write_pci_eeprom_offs(unsigned short offset, unsigned short value) -{ - unsigned long reg; - int bitpos, cmdshft, cmdlen, timeout; - /* we're using the Eeprom 93CS66 */ - cmdshft = 2; - cmdlen = EE66_CMD_LEN; - /* Send Write_Enable command to EEPROM */ - send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen); - /* Send EEPROM Write command and offset to EEPROM */ - send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Clear all EEPROM bits */ - reg &= ~(0xF << 24); - /* Make sure EEDO Input is disabled for some PLX chips */ - reg &= ~(1 << 31); - /* Enable EEPROM Chip Select */ - reg |= (1 << 25); - /* Write 16-bit value to EEPROM - one bit at a time */ - for (bitpos = 15; bitpos >= 0; bitpos--) { - /* Get bit value and shift into result */ - if (value & (1 << bitpos)) - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); - else - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg ); - clock_pci_eeprom(); - } /* for */ - /* Deselect Chip */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25)); - /* Re-select Chip */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25)); - /* A small delay is needed to let EEPROM complete */ - timeout = 0; - do { - udelay(10); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - timeout++; - } while (((reg & (1 << 27)) == 0) && timeout < 20000); - /* Send Write_Disable command to EEPROM */ - send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen); - /* Clear Chip Select and all other EEPROM bits */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); -} - - -/****************************************************************************** - * read_pci_eeprom_offs - ******************************************************************************/ -static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue) -{ - unsigned long reg; - int bitpos, cmdshft, cmdlen; - /* we're using the Eeprom 93CS66 */ - cmdshft = 2; - cmdlen = EE66_CMD_LEN; - /* Send EEPROM read command and offset to EEPROM */ - send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen); - /* Set EEPROM write output bit */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Set EEDO Input enable */ - reg |= (1 << 31); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26)); - /* Get 16-bit value from EEPROM - one bit at a time */ - for (bitpos = 0; bitpos < 16; bitpos++) { - clock_pci_eeprom(); - udelay(10); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Get bit value and shift into result */ - if (reg & (1 << 27)) - *pvalue = (unsigned short)((*pvalue << 1) | 1); - else - *pvalue = (unsigned short)(*pvalue << 1); - } - /* Clear EEDO Input enable */ - reg &= ~(1 << 31); - /* Clear Chip Select and all other EEPROM bits */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); -} - - -/****************************************************************************** - * EEPROM read/writes -******************************************************************************/ - -#undef EEPROM_DBG -static int pati_pci_eeprom_erase(void) -{ - int i; - printf("Erasing EEPROM "); - for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) { - write_pci_eeprom_offs(i,0xffff); - if((i%0x10)) - printf("."); - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_prg(void) -{ - int i; - i=0; - printf("Programming EEPROM "); - while(pati_eeprom[i].offset<0xffff) { - write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value); - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value); - #else - if((i%0x10)) - printf("."); - #endif - i++; - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size) -{ - int i; - unsigned short value; - unsigned short *buffer =(unsigned short *)addr; - if((offset + size) > PATI_EEPROM_LAST_OFFSET) { - size = PATI_EEPROM_LAST_OFFSET - offset; - } - printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2); - for( i = offset; i< (offset + size); i+=2) { - value = *buffer++; - write_pci_eeprom_offs(i,value); - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",i, value); - #else - if((i%0x10)) - printf("."); - #endif - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size) -{ - int i; - unsigned short value; - unsigned short *buffer =(unsigned short *)addr; - if((offset + size) > PATI_EEPROM_LAST_OFFSET) { - size = PATI_EEPROM_LAST_OFFSET - offset; - } - printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2); - for( i = offset; i< (offset + size); i+=2) { - read_pci_eeprom_offs(i,&value); - *buffer++=value; - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",i, value); - #else - if((i%0x10)) - printf("."); - #endif - } - printf("\nDone\n"); - return 0; -} - -/****************************************************************************** - * PCI Bridge Registers Dump -*******************************************************************************/ -static void display_pci_regs(void) -{ - printf(" PCI9056_SPACE0_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE)); - printf(" PCI9056_SPACE0_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP)); - printf(" PCI9056_LOCAL_DMA_ARBIT %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT)); - printf(" PCI9056_ENDIAN_DESC %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC)); - printf(" PCI9056_EXP_ROM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE)); - printf(" PCI9056_EXP_ROM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP)); - printf(" PCI9056_SPACE0_ROM_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC)); - printf(" PCI9056_DM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE)); - printf(" PCI9056_DM_MEM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE)); - printf(" PCI9056_DM_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE)); - printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP)); - printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG)); - printf(" PCI9056_SPACE1_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE)); - printf(" PCI9056_SPACE1_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP)); - printf(" PCI9056_SPACE1_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC)); - printf(" PCI9056_DM_DAC %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC)); - printf(" PCI9056_MAILBOX0 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0)); - printf(" PCI9056_MAILBOX1 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1)); - printf(" PCI9056_MAILBOX2 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2)); - printf(" PCI9056_MAILBOX3 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3)); - printf(" PCI9056_MAILBOX4 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4)); - printf(" PCI9056_MAILBOX5 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5)); - printf(" PCI9056_MAILBOX6 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6)); - printf(" PCI9056_MAILBOX7 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7)); - printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL)); - printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL)); - printf(" PCI9056_INT_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT)); - printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT)); - printf(" PCI9056_PERM_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID)); - printf(" PCI9056_REVISION_ID %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID)); - printf(" \n"); - printf(" PCI9056_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID)); - printf(" PCI9056_COMMAND %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND)); - printf(" PCI9056_REVISION %08lX\n",PCICFG_GET_REG(PCI9056_REVISION)); - printf(" PCI9056_CACHE_SIZE %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE)); - printf(" PCI9056_RTR_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE)); - printf(" PCI9056_RTR_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE)); - printf(" PCI9056_LOCAL_BASE0 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0)); - printf(" PCI9056_LOCAL_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1)); - printf(" PCI9056_UNUSED_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1)); - printf(" PCI9056_UNUSED_BASE2 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2)); - printf(" PCI9056_CIS_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR)); - printf(" PCI9056_SUB_ID %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID)); - printf(" PCI9056_EXP_ROM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE)); - printf(" PCI9056_CAP_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR)); - printf(" PCI9056_INT_LINE %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE)); - printf(" PCI9056_PM_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID)); - printf(" PCI9056_PM_CSR %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR)); - printf(" PCI9056_HS_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID)); - printf(" PCI9056_VPD_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID)); - printf(" PCI9056_VPD_DATA %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA)); -} - - -int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - if (strcmp(argv[1], "info") == 0) - { - show_pld_regs(); - return 0; - } - if (strcmp(argv[1], "pci") == 0) - { - display_pci_regs(); - return 0; - } - if (strcmp(argv[1], "led") == 0) - { - int led_nr,led_on; - led_nr = (int)simple_strtoul(argv[2], NULL, 10); - led_on = (int)simple_strtoul(argv[3], NULL, 10); - if(!led_nr) - user_led0(led_on); - else - user_led1(led_on); - return 0; - } -#if defined(CFG_PCI_CON_DEVICE) - if (strcmp(argv[1], "con") == 0) { - pci_con_connect(); - return 0; - } - if (strcmp(argv[1], "disc") == 0) { - pci_con_disc(); - return 0; - } -#endif - if (strcmp(argv[1], "eeprom") == 0) { - unsigned long addr; - int size, offset; - offset = 0; - size = PATI_EEPROM_LAST_OFFSET; - if(argc>2) { - if(argc>3) { - addr = simple_strtoul(argv[3], NULL, 16); - if(argc>4) - offset = (int) simple_strtoul(argv[4], NULL, 16); - if(argc>5) - size = (int) simple_strtoul(argv[5], NULL, 16); - if (strcmp(argv[2], "read") == 0) { - return (pati_pci_eeprom_read(offset, addr, size)); - } - if (strcmp(argv[2], "write") == 0) { - return (pati_pci_eeprom_write(offset, addr, size)); - } - } - if (strcmp(argv[2], "prg") == 0) { - return (pati_pci_eeprom_prg()); - } - if (strcmp(argv[2], "era") == 0) { - return (pati_pci_eeprom_erase()); - } - if (strcmp(argv[2], "reload") == 0) { - reload_pci_eeprom(); - return 0; - } - - - } - } - - return (do_mplcommon(cmdtp, flag, argc, argv)); -} - -U_BOOT_CMD( - pati, 8, 1, do_pati, - "pati - PATI specific Cmds\n", - "info - displays board information\n" - "pati pci - displays PCI registers\n" - "pati led \n" - " - switch LED \n" - "pati flash mem [SrcAddr]\n" - " - updates U-Boot with image in memory\n" - "pati eeprom - PCI EEPROM sub-system\n" - " read \n" - " - read PCI EEPROM to from words\n" - " write \n" - " - write PCI EEPROM from to words\n" - " prg - programm PCI EEPROM with default values\n" - " era - erase PCI EEPROM (write all word to 0xffff)\n" - " reload- Reload PCI Bridge with EEPROM Values\n" - " NOTE: must start on word boundary\n" - " and must be even byte values\n" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pati/config.mk b/board/mpl/pati/config.mk deleted file mode 100644 index b8a0985..0000000 --- a/board/mpl/pati/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2003 -# Martin Winistoerfer, martinwinistoerfer@gmx.ch. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# EPQ Board Configuration -# - -# Boot from flash at location 0x00000000 -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c deleted file mode 100644 index 0355b65..0000000 --- a/board/mpl/pati/pati.c +++ /dev/null @@ -1,618 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * Atapted for PATI - * Denis Peter, d.peter@mpl.ch - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*********************************************************************************** - * Bits for the SDRAM controller - * ----------------------------- - * - * CAL: CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on - * the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM - * controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3). - * RCD: RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default) - * tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns. - * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns. - * If set to 1 tWR must be equal or less 50ns. - * RP: Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less - * 25ns. If set to 1 tRP must be equal or less 50ns. - * RC: Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal - * or less 75ns. If set to 1 tRC must be equal or less 100ns. - * LMR: Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM - * is the Load Mode Register Command. - * IIP: Init in progress. Set to 1 for starting the init sequence - * (Precharge All). As long this bit is set, the Precharge All is still in progress. - * After command has completed, wait at least for 8 refresh (200usec) before proceed. - **********************************************************************************/ - -#include -#include -#include -#include -#define PLX9056_LOC -#include "plx9056.h" -#include "pati.h" - -#if defined(__APPLE__) -/* Leading underscore on symbols */ -# define SYM_CHAR "_" -#else /* No leading character on symbols */ -# define SYM_CHAR -#endif - -#undef SDRAM_DEBUG -/* - * Macros to generate global absolutes. - */ -#define GEN_SYMNAME(str) SYM_CHAR #str -#define GEN_VALUE(str) #str -#define GEN_ABS(name, value) \ - asm (".globl " GEN_SYMNAME(name)); \ - asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) - - -/************************************************************************ - * Early debug routines - */ -void write_hex (unsigned char i) -{ - char cc; - - cc = i >> 4; - cc &= 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); - cc = i & 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); -} - -#if defined(SDRAM_DEBUG) - -void write_4hex (unsigned long val) -{ - write_hex ((unsigned char) (val >> 24)); - write_hex ((unsigned char) (val >> 16)); - write_hex ((unsigned char) (val >> 8)); - write_hex ((unsigned char) val); -} - -#endif - -unsigned long in32(unsigned long addr) -{ - unsigned long *p=(unsigned long *)addr; - return *p; -} - -void out32(unsigned long addr,unsigned long data) -{ - unsigned long *p=(unsigned long *)addr; - *p=data; -} - -typedef struct { - unsigned short boardtype; /* Board revision and Population Options */ - unsigned char cal; /* cas Latency 0:CAL=2 1:CAL=3 */ - unsigned char rcd; /* ras to cas delay 0:<25ns 1:<50ns*/ - unsigned char wrec; /* write recovery 0:<25ns 1:<50ns */ - unsigned char pr; /* Precharge Command Time 0:<25ns 1:<50ns */ - unsigned char rc; /* Auto Refresh to Active Time 0:<75ns 1:<100ns */ - unsigned char sz; /* log binary => Size = (4MByte< Size 2 = 16MByte, 1=8 */ - }, - { 0xffff, /* terminator */ - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff } -}; - - -extern int mem_test (unsigned long start, unsigned long ramsize, int quiet); -extern void mem_test_reloc(void); - -/* - * Get RAM size. - */ -long int initdram(int board_type) -{ - unsigned char board_rev; - unsigned long reg; - unsigned long lmr; - int i,timeout; - -#if defined(SDRAM_DEBUG) - reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); - puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg)); - puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg)); - puts("\nSDRAM part 0x"); write_4hex(SDRAM_PART(reg)); - puts(" Vers 0x"); write_4hex(SDRAM_ID(reg)); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - puts("\nBoard rev. 0x"); write_4hex(SYSCNTR_BREV(reg)); - putc('\n'); -#endif - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - board_rev=(unsigned char)(SYSCNTR_BREV(reg)); - i=0; - while(1) { - if(sdram_table[i].boardtype==0xffff) { - puts("ERROR, found no table for Board 0x"); - write_hex(board_rev); - while(1); - } - if(sdram_table[i].boardtype==(unsigned char)board_rev) - break; - i++; - } - /* Set CAL, RCD, WREQ, PR and RC Bits */ -#if defined(SDRAM_DEBUG) - puts("Set CAL, RCD, WREQ, PR and RC Bits\n"); -#endif - /* mask bits */ - reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) | - SET_REG_BIT(1,SDRAM_PR) | SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR) | - SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0)); - /* set bits */ - reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) | - SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) | - SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) | - SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) | - SET_REG_BIT(sdram_table[i].rc,SDRAM_RC)); - - out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); - /* step 2 set IIP */ -#if defined(SDRAM_DEBUG) - puts("step 2 set IIP\n"); -#endif - /* step 2 set IIP */ - reg |= SET_REG_BIT(1,SDRAM_IIP); - timeout=0; - while (timeout!=0xffff) { - __asm__ volatile("eieio"); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - if((reg & SET_REG_BIT(1,SDRAM_IIP))==0) - break; - timeout++; - udelay(1); - } - /* wait for at least 8 refresh */ - udelay(1000); - /* set LMR */ - reg |= SET_REG_BIT(1,SDRAM_LMR); - out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); - __asm__ volatile("eieio"); - lmr=0x00000002; /* sequential burst 4 data */ - if(sdram_table[i].cal==1) - lmr|=0x00000030; /* cal = 3 */ - else - lmr|=0000000020; /* cal = 2 */ - /* rest standard operation programmed write burst length */ - /* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */ - lmr<<=2; - in32(CFG_SDRAM_BASE + lmr); - /* ok, we're done, return SDRAM size */ - return ((0x400000 << sdram_table[i].sz)); /* log2 value of 4MByte */ -} - - -void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp) -{ - unsigned long reg; - reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE); - reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) | - SET_REG_BIT(1,SYSCNTR_FL_VPP) | - SET_REG_BIT(1,SYSCNTR_FL_WP)); - - reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) | - SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) | - SET_REG_BIT(ext_wp,SYSCNTR_FL_WP)); - out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg); - udelay(100); -} - - -void show_pld_regs(void) -{ - unsigned long reg,reg1; - reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); - printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg)); - printf("SDRAM part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg)); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - printf("Board rev. %c\n",(char) (SYSCNTR_BREV(reg)+'A')); - printf("Waitstates %ld\n",GET_SYSCNTR_FLWAIT(reg)); - printf("SDRAM: CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n RC=%ld LMR=%ld IIP=%ld\n", - GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD), - GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR), - GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR), - GET_REG_BIT(reg,SDRAM_IIP)); - reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1); - reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2); - printf("HW Config: FLAG=%ld IP=%ld index=%ld PRPM=%ld\n ICW=%ld ISB=%ld BDIS=%ld PCIM=%ld\n", - GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP), - GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM), - GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg), - GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM)); - printf("Switches: MUX=%ld PCI_DIS=%ld Boot_EN=%ld Config=%ld\n",GET_SDRAM_MUX(reg), - GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN), - GET_SYSCNTR_CFG(reg1)); - printf("Misc: RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n", - GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP), - GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP)); -} - - -/**************************************************************** - * Setting IOs - * ----------- - * GPIO6 is User LED1 - * GPIO7 is Interrupt PLX (Output) - * GPIO5 is User LED0 - * GPIO2 is PLX USERi (Output) - * GPIO1 is PLX Interrupt (Input) - ****************************************************************/ - void init_ios(void) - { - volatile immap_t * immr = (immap_t *) CFG_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiocr; /* Data direction register */ - reg &= ~0x67000000; - reg |= 0x27000000; /* set outpupts */ - sysconf->sc_sgpiocr=reg; /* Data direction register */ - reg=sysconf->sc_sgpiodt2; /* Data register */ - /* set output to 0 */ - reg &= ~0x27000000; - /* set IRQ and USERi to 1 */ - reg |= 0x28000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - -void user_led0(int led_on) -{ - volatile immap_t * immr = (immap_t *) CFG_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiodt2; /* Data register */ - if(led_on) /* set output to 1 */ - reg |= 0x04000000; - else - reg &= ~0x04000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - -void user_led1(int led_on) -{ - volatile immap_t * immr = (immap_t *) CFG_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiodt2; /* Data register */ - if(led_on) /* set output to 1 */ - reg |= 0x02000000; - else - reg &= ~0x02000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - - -/**************************************************************** - * Last Stage Init - ****************************************************************/ -int last_stage_init (void) -{ - mem_test_reloc(); - init_ios(); - return 0; -} - -/**************************************************************** - * Check the board - ****************************************************************/ - -#define BOARD_NAME "PATI" - -int checkboard (void) -{ - unsigned char s[50]; - unsigned long reg; - char rev; - int i; - - puts ("\nBoard: "); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - rev=(char)(SYSCNTR_BREV(reg)+'A'); - i = getenv_r ("serial#", s, 32); - if ((i == -1)) { - puts ("### No HW ID - assuming " BOARD_NAME); - printf(" Rev. %c\n",rev); - } - else { - s[sizeof(BOARD_NAME)-1] = 0; - printf ("%s-1 Rev %c SN: %s\n", s,rev, - &s[sizeof(BOARD_NAME)]); - } - set_flash_vpp(1,0,0); /* set Flash VPP */ - return 0; -} - - -#ifdef CFG_PCI_CON_DEVICE -/************************************************************************ - * PCI Communication - * - * Alive (Pinging): - * ---------------- - * PCI Host sends message ALIVE, Local acknowledges with ALIVE - * - * PCI_CON console over PCI: - * ------------------------- - * Local side: - * - uses PCI9056_LOC_TO_PCI_DBELL register to signal that - * data is avaible (PCIMSG_CONN) - * - uses PCI9056_MAILBOX1 to send data - * - uses PCI9056_MAILBOX0 to receive data - * PCI side: - * - uses PCI9056_PCI_TO_LOC_DBELL register to signal that - * data is avaible (PCIMSG_CONN) - * - uses PCI9056_MAILBOX0 to send data - * - uses PCI9056_MAILBOX1 to receive data - * - * How it works: - * Send: - * - check if PCICON_TRANSMIT_REG is empty - * - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG - * - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data - * is waiting - * Receive: - * - get an interrupt via the PCICON_ACK_REG register message - * PCIMSG_CONN - * - write the data from the PCICON_RECEIVE_REG into the receive - * buffer and if the receive buffer is not full, clear the - * PCICON_RECEIVE_REG (this allows the counterpart to write more data) - * - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG - * - * The PCICON_RECEIVE_REG must be cleared by the routine which reads - * the receive buffer if the buffer is not full any more - * - */ - -#undef PCI_CON_DEBUG - -#ifdef PCI_CON_DEBUG -#define PCI_CON_PRINTF(fmt,args...) serial_printf (fmt ,##args) -#else -#define PCI_CON_PRINTF(fmt,args...) -#endif - - -/********************************************************* - * we work only with a receive buffer on eiter side. - * Transmit buffer is free, if mailbox is cleared. - * Transmit character is or'ed with 0x80000000 - * PATI receive register MAILBOX0 - * PATI transmit register MAILBOX1 - *********************************************************/ -#define PCICON_RECEIVE_REG PCI9056_MAILBOX0 -#define PCICON_TRANSMIT_REG PCI9056_MAILBOX1 -#define PCICON_DBELL_REG PCI9056_LOC_TO_PCI_DBELL -#define PCICON_ACK_REG PCI9056_PCI_TO_LOC_DBELL - - -#define PCIMSG_ALIVE 0x1 -#define PCIMSG_CONN 0x2 -#define PCIMSG_DISC 0x3 -#define PCIMSG_CON_DATA 0x5 - - -#define PCICON_GET_REG(x) (in32(x + PCI_CONFIG_BASE)) -#define PCICON_SET_REG(x,y) (out32(x + PCI_CONFIG_BASE,y)) -#define PCICON_TX_FLAG 0x80000000 - - -#define REC_BUFFER_SIZE 0x100 -int recbuf[REC_BUFFER_SIZE]; -static int r_ptr = 0; -int w_ptr; -device_t pci_con_dev; -int conn=0; -int buff_full=0; - -void pci_con_put_it(const char c) -{ - /* Test for completition */ - unsigned long reg; - do { - reg=PCICON_GET_REG(PCICON_TRANSMIT_REG); - }while(reg); - reg=PCICON_TX_FLAG + c; - PCICON_SET_REG(PCICON_TRANSMIT_REG,reg); - PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA); -} - -void pci_con_putc(const char c) -{ - pci_con_put_it(c); - if(c == '\n') - pci_con_put_it('\r'); -} - - -int pci_con_getc(void) -{ - int res; - int diff; - while(r_ptr==(volatile int)w_ptr); - res=recbuf[r_ptr++]; - if(r_ptr==REC_BUFFER_SIZE) - r_ptr=0; - if(w_ptr(REC_BUFFER_SIZE-4)) - buff_full=1; - else - /* clear Mail box */ - PCICON_SET_REG(PCICON_RECEIVE_REG,0L); - break; - default: - serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg); - } - /* clear IRQ */ - PCICON_SET_REG(PCICON_ACK_REG,~0L); - } - return 0; -} - -void pci_con_connect(void) -{ - unsigned long reg; - conn=0; - reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT); - /* default 0x0f010180 */ - reg &= 0xff000000; - reg |= 0x00030000; /* enable local dorbell */ - reg |= 0x00000300; /* enable PCI dorbell */ - PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg); - irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL); - memset (&pci_con_dev, 0, sizeof (pci_con_dev)); - strcpy (pci_con_dev.name, "pci_con"); - pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - pci_con_dev.putc = pci_con_putc; - pci_con_dev.puts = pci_con_puts; - pci_con_dev.getc = pci_con_getc; - pci_con_dev.tstc = pci_con_tstc; - device_register (&pci_con_dev); - printf("PATI ready for PCI connection, type ctrl-c for exit\n"); - do { - udelay(10); - if((volatile int)conn) - break; - if(ctrlc()) { - irq_free_handler(0x2); - return; - } - }while(1); - console_assign(stdin,"pci_con"); - console_assign(stderr,"pci_con"); - console_assign(stdout,"pci_con"); -} - -void pci_con_disc(void) -{ - console_assign(stdin,"serial"); - console_assign(stderr,"serial"); - console_assign(stdout,"serial"); - PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC); - /* reconnection */ - irq_free_handler(0x02); - pci_con_connect(); -} -#endif /* #ifdef CFG_PCI_CON_DEVICE */ - -/* - * Absolute environment address for linker file. - */ -GEN_ABS(env_start, CFG_ENV_OFFSET + CFG_FLASH_BASE); diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h deleted file mode 100644 index d521772..0000000 --- a/board/mpl/pati/pati.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter, d.peter@mpl.ch - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/************************************************************************ - * MACROS and register definitions for PATI Registers - ************************************************************************/ -#ifndef __PATI_H_ -#define __PATI_H_ 1 - -#define PLD_PART_ID 0x0 -#define PLD_BOARD_TIMING 0x4 -#define PLD_CONF_REG1 0x8 -#define PLD_CONF_REG2 0xC -#define PLD_CONF_RES 0x10 - -#define SET_REG_BIT(y,x) (y<<(31-x)) -#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L) - -/* SDRAM Controller PLD_PART_ID */ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_PART3 9 -#define SDRAM_PART2 10 -#define SDRAM_PART1 11 -#define SDRAM_PART0 12 -#define SDRAM_ID3 13 -#define SDRAM_ID2 14 -#define SDRAM_ID1 19 -#define SDRAM_ID0 31 - -#define SDRAM_PART(x) ( \ - (GET_REG_BIT(x,SDRAM_PART3)<<3) |\ - (GET_REG_BIT(x,SDRAM_PART2)<<2) |\ - (GET_REG_BIT(x,SDRAM_PART1)<<1) |\ - (GET_REG_BIT(x,SDRAM_PART0))) - -#define SDRAM_ID(x) ( \ - (GET_REG_BIT(x,SDRAM_ID3)<<3) |\ - (GET_REG_BIT(x,SDRAM_ID2)<<2) |\ - (GET_REG_BIT(x,SDRAM_ID1)<<1) |\ - (GET_REG_BIT(x,SDRAM_ID0))) - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_PART4 0 -#define SYSCNTR_PART3 1 -#define SYSCNTR_PART2 3 -#define SYSCNTR_PART1 4 -#define SYSCNTR_PART0 5 -#define SYSCNTR_ID4 16 -#define SYSCNTR_ID3 20 -#define SYSCNTR_ID2 28 -#define SYSCNTR_ID1 29 -#define SYSCNTR_ID0 30 - -#define SYSCNTR_PART(x) ( \ - (GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\ - (GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_PART0))) - -#define SYSCNTR_ID(x) ( \ - (GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\ - (GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_ID0))) - -/* SDRAM Controller PLD_BOARD_TIMING */ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_CAL 9 -#define SDRAM_RCD 10 -#define SDRAM_WREQ 11 -#define SDRAM_PR 12 -#define SDRAM_RC 13 -#define SDRAM_LMR 14 -#define SDRAM_IIP 19 -#define SDRAM_RES0 31 -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_BREV0 0 -#define SYSCNTR_BREV1 1 -#define SYSCNTR_BREV2 3 -#define SYSCNTR_BREV3 4 -#define SYSCNTR_RES0 5 -#define SYSCNTR_RES1 16 -#define SYSCNTR_RES2 20 -#define SYSCNTR_FLWAIT2 28 -#define SYSCNTR_FLWAIT1 29 -#define SYSCNTR_FLWAIT0 30 - -#define SYSCNTR_BREV(x) ( \ - (GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_BREV0))) - -#define GET_SYSCNTR_FLWAIT(x) ( \ - (GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_FLWAIT0))) - -#define SET_SYSCNTR_FLWAIT(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0))) - -/* SDRAM Controller REG 2*/ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_MUX0 9 -#define SDRAM_MUX1 10 -#define SDRAM_PDIS 11 -#define SDRAM_RES1 12 -#define SDRAM_RES2 13 -#define SDRAM_RES3 14 -#define SDRAM_RES4 19 -#define SDRAM_RIP 31 - -#define GET_SDRAM_MUX(x) ( \ - (GET_REG_BIT(x,SDRAM_MUX1)<<1)| \ - (GET_REG_BIT(x,SDRAM_MUX0))) - - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_FLAG 0 -#define SYSCNTR_IP 1 -#define SYSCNTR_BIND2 3 -#define SYSCNTR_BIND1 4 -#define SYSCNTR_BIND0 5 -#define SYSCNTR_PRM 16 -#define SYSCNTR_ICW 20 -#define SYSCNTR_ISB2 28 -#define SYSCNTR_ISB1 29 -#define SYSCNTR_ISB0 30 - -#define GET_SYSCNTR_BOOTIND(x) ( \ - (GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_BIND0))) - -#define SET_SYSCNTR_BOOTIND(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0))) - -#define GET_SYSCNTR_ISB(x) ( \ - (GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \ - (GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \ - (GET_REG_BIT(x,SYSCNTR_ISB0))) - -#define SET_SYSCNTR_ISB(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0))) - -/* SDRAM Controller REG 3*/ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_RES5 9 -#define SDRAM_CFG1 10 -#define SDRAM_CFG2 11 -#define SDRAM_CFG3 12 -#define SDRAM_RES6 13 -#define SDRAM_CFG5 14 -#define SDRAM_CFG6 19 -#define SDRAM_RES7 31 - -#define GET_SDRAM_CFG(x) ( \ - (GET_REG_BIT(x,SDRAM_CFG6)<<4) |\ - (GET_REG_BIT(x,SDRAM_CFG5)<<3) |\ - (GET_REG_BIT(x,SDRAM_CFG3)<<2) |\ - (GET_REG_BIT(x,SDRAM_CFG2)<<1) |\ - (GET_REG_BIT(x,SDRAM_CFG1))) - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_BDIS 0 -#define SYSCNTR_PCIM 1 -#define SYSCNTR_CFG0 3 -#define SYSCNTR_CFG1 4 -#define SYSCNTR_CFG2 5 -#define SYSCNTR_CFG3 16 -#define SYSCNTR_BOOTEN 20 -#define SYSCNTR_CPU_VPP 28 -#define SYSCNTR_FL_VPP 29 -#define SYSCNTR_FL_WP 30 - -#define GET_SYSCNTR_CFG(x) ( \ - (GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \ - (GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \ - (GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \ - (GET_REG_BIT(x,SYSCNTR_CFG0))) - - -/*************************************************************** - * MISC Defines - ***************************************************************/ - -#define PCI_VENDOR_ID_MPL 0x18E6 -#define PCI_DEVICE_ID_PATI 0x00DA - -#if defined(CONFIG_MIP405) -#define PATI_FIRMWARE_START_OFFSET 0x00300000 -#define PATI_ISO_STRING "MEV-10084-001" -#endif - -#define PATI_ENDIAN_MODE 0x3E - -/******************************************* - * PATI Mapping: - * ------------- - * PCI Map: - * ------- - * All addreses are mapped into the memory area - * (IO Area on some areas may also be possible) - * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes - * - pci_space0_addr: configurable - * - pci_space1_addr configurable - * - * Local Map: - * ---------- - * Local addresses (Remap) - * - SDRAM 0x06000000 Size 16MByte mask 0xff000000 - * - EPLD CFG 0x07000000 Size 512Bytes - * - FLASH 0x03000000 Size up to 8MByte - * - CPU 0x01000000 Size 4MByte (only accessable if special configured) - * - * Implemention: - * ------------- - * To prevent using large resources reservation on the host following - * PCI mapping is choosed: - * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes - * - pci_space0_addr: configured to the EPLD Config Area size 256Bytes - * - pci_space1_addr: configured to the SDRAM Area size 1MBytes, this - * space is used to switch between SDRAM, Flash and CPU - * - */ - -/* Attribute definitions */ -#define PATI_BUS_SIZE_8 0 -#define PATI_BUS_SIZE_16 1 -#define PATI_BUS_SIZE_32 3 - -#define PATI_SPACE0_MASK (0xFEFFFE00) /* Mask Attributes */ -#define PATI_SPACE1_MASK (0x00000000) /* Mask Attributes */ - -#define PATI_EXTRA_LONG_EEPROM 1 - -#define SPACE0_TA_ENABLE (1<<6) -#define SPACE1_TA_ENABLE (1<<6) - -/* Config Area */ -#define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */ -#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */ -/* Attributes */ -#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_CFG_BURST 0 /* No Burst */ -#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */ - -#define PATI_LOC_CFG_SPACE0_ATTR ( \ - PATI_LOC_CFG_BUS_SIZE | \ - (PATI_LOC_CFG_TA_ENABLE << 6) | \ - (PATI_LOC_CFG_NO_PREFETCH << 8) | \ - (PATI_LOC_CFG_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -/* should never be used */ -#define PATI_LOC_CFG_SPACE1_ATTR ( \ - PATI_LOC_CFG_BUS_SIZE | \ - (PATI_LOC_CFG_TA_ENABLE << 6) | \ - (PATI_LOC_CFG_NO_PREFETCH << 9) | \ - (PATI_LOC_CFG_BURST << 8)) - - -/* SDRAM Area */ -#define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */ -#define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */ -/* Attributes */ -#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_SDRAM_BURST 0 /* No Burst */ -#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */ -#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_SDRAM_SPACE0_ATTR ( \ - PATI_LOC_SDRAM_BUS_SIZE | \ - (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ - (PATI_LOC_SDRAM_NO_PREFETCH << 8) | \ - (PATI_LOC_SDRAM_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -#define PATI_LOC_SDRAM_SPACE1_ATTR ( \ - PATI_LOC_SDRAM_BUS_SIZE | \ - (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ - (PATI_LOC_SDRAM_NO_PREFETCH << 9) | \ - (PATI_LOC_SDRAM_BURST << 8)) - - -/* Flash Area */ -#define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */ -#define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */ -/* Attributes */ -#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */ -#define PATI_LOC_FLASH_BURST 0 /* No Burst */ -#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_FLASH_SPACE0_ATTR ( \ - PATI_LOC_FLASH_BUS_SIZE | \ - (PATI_LOC_FLASH_TA_ENABLE << 6) | \ - (PATI_LOC_FLASH_NO_PREFETCH << 8) | \ - (PATI_LOC_FLASH_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -#define PATI_LOC_FLASH_SPACE1_ATTR ( \ - PATI_LOC_FLASH_BUS_SIZE | \ - (PATI_LOC_FLASH_TA_ENABLE << 6) | \ - (PATI_LOC_FLASH_NO_PREFETCH << 9) | \ - (PATI_LOC_FLASH_BURST << 8)) - - -/* CPU Area */ -#define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */ -#define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */ -/* Attributes */ -#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_CPU_BURST 0 /* No Burst */ -#define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_CPU_SPACE0_ATTR ( \ - PATI_LOC_CPU_BUS_SIZE | \ - (PATI_LOC_CPU_TA_ENABLE << 6) | \ - (PATI_LOC_CPU_NO_PREFETCH << 8) | \ - (PATI_LOC_CPU_BURST << 24) | \ - (PATI_EXTRA_CPU_EEPROM << 25)) - -#define PATI_LOC_CPU_SPACE1_ATTR ( \ - PATI_LOC_CPU_BUS_SIZE | \ - (PATI_LOC_CPU_TA_ENABLE << 6) | \ - (PATI_LOC_CPU_NO_PREFETCH << 9) | \ - (PATI_LOC_CPU_BURST << 8)) - -/*************************************************** - * Hardware Config word definition - ***************************************************/ -#define BOOT_EXT_FLASH 0x00000000 -#define BOOT_INT_FLASH 0x00000004 -#define BOOT_FROM_PCI 0x00000006 -#define BOOT_FROM_SDRAM 0x00000005 - -#define ENABLE_INT_ARB 0x00000008 - -#define INITIAL_IRQ_PREF 0x00000010 - -#define INITIAL_MEM_0M 0x00000000 -#define INITIAL_MEM_4M 0x00000080 -#define INITIAL_MEM_8M 0x00000040 -#define INITIAL_MEM_12M 0x000000C0 -#define INITIAL_MEM_16M 0x00000020 -#define INITIAL_MEM_20M 0x000000A0 -#define INITIAL_MEM_24M 0x00000060 -#define INITIAL_MEM_28M 0x000000E0 -/* CONF */ -#define INTERNAL_HWCONF 0x00000100 -/* PRPM */ -#define LOCAL_CPU_SLAVE 0x00000200 -/* BDIS */ -#define DISABLE_MEM_CNTR 0x00000400 -/* PCIM */ -#define PCI_MASTER_ONLY 0x00000800 - - -#define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF)) -#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) -#define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) -#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE)) - -/*************************************************** - * Direct Master Config - ***************************************************/ -#define PATI_DMASTER_PCI_ADDR 0x01000000 -#define PATI_BUS_MASTER 1 - - -#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */ -#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */ - -#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */ -#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */ -#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */ -#define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000 -#define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008 -#define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000 -#define PATI_DMASTER_PRE_SIZE_CNTRL_16 0x00001008 -#define PATI_DMASTER_REL_PCI 0x00000000 -#define PATI_DMASTER_NOT_REL_PCI 0x00000010 -#define PATI_DMASTER_WR_INVAL 0x00000200 -#define PATI_DMASTER_NOT_WR_INVAL 0x00000000 -#define PATI_DMASTER_PRE_LIMIT 0x00000800 -#define PATI_DMASTER_PRE_CONT 0x00000000 -#define PATI_DMASTER_DELAY_WR_0 0x00000000 -#define PATI_DMASTER_DELAY_WR_4 0x00004000 -#define PATI_DMASTER_DELAY_WR_8 0x00008000 -#define PATI_DMASTER_DELAY_WR_16 0x0000C000 - -#define PATI_DMASTER_PCI_ADDR_MASK 0xFFFF0000 - -#define PATI_DMASTER_ATTR \ - PATI_DMASTER_MEMORY_EN | \ - PATI_DMASTER_READ_AHEAD | \ - PATI_DMASTER_PRE_SIZE_CNTRL_4 | \ - PATI_DMASTER_REL_PCI | \ - PATI_DMASTER_NOT_WR_INVAL | \ - PATI_DMASTER_PRE_LIMIT | \ - PATI_DMASTER_DELAY_WR_0 - - -#endif /* #ifndef __PATI_H_ */ diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h deleted file mode 100644 index 9658808..0000000 --- a/board/mpl/pati/pci_eeprom.h +++ /dev/null @@ -1,91 +0,0 @@ - -#ifndef __PCI_EEPROM_H_ -#define __PCI_EEPROM_H_ 1 - -#include "pati.h" -/****************************************************************************** - * Eeprom Support - ******************************************************************************/ -/********************************************** -* Definitions -**********************************************/ -#define EE46_CMD_LEN 9 /* Bits in instructions */ -#define EE56_CMD_LEN 11 /* Bits in instructions */ -#define EE66_CMD_LEN 11 /* Bits in instructions */ -#define EE_READ 0x0180 /* 01 1000 0000 read instruction */ -#define EE_WRITE 0x0140 /* 01 0100 0000 write instruction */ -#define EE_WREN 0x0130 /* 01 0011 0000 write enable instruction */ -#define EE_WRALL 0x0110 /* 01 0001 0000 write all registers */ -#define EE_PRREAD 0x0180 /* 01 1000 0000 read address stored in Protect Register */ -#define EE_PRWRITE 0x0140 /* 01 0100 0000 write the address into PR */ -#define EE_WDS 0x0100 /* 01 0000 0000 write disable instruction */ -#define EE_PREN 0x0130 /* 01 0011 0000 protect enable instruction */ -#define EE_PRCLEAR 0x01FF /* 01 1111 1111 clear protect register instr */ -#define EE_PRDS 0x0100 /* 01 0000 0000 ONE TIME ONLY, permenant */ - -/*************************************************** - * EEPROM - ***************************************************/ -#define LOW_WORD(x) (((x) & 0xFFFF)) -#define HIGH_WORD(x) (((x) >> 16) & 0xFFFF) - -typedef struct pci_eeprom_t { - unsigned short offset; - unsigned short value; -} pci_eeprom; - -static pci_eeprom pati_eeprom[] = { - { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */ - { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */ - { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */ - { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */ - { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */ - { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */ - { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */ - { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */ - { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */ - { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */ - { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */ - { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */ - { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */ - { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */ - { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */ - { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */ - { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */ - { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */ - { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */ - { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */ - { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */ - { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */ - { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */ - { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */ - { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */ - { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */ - { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */ - { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */ - { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */ - { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */ - { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */ - { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */ - { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/ - { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */ - { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */ - { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */ - { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */ - { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */ - { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */ - { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */ - { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */ - { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */ - { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */ - { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */ - { 0x58,0x0000 }, /* Reserved Reserved */ - { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */ - { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */ - { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/ - { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */ - { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */ - { 0xFFFF,0xFFFF} /* terminaror */ -}; -#define PATI_EEPROM_LAST_OFFSET 0x64 -#endif /* #ifndef __PCI_EEPROM_H_ */ diff --git a/board/mpl/pati/plx9056.h b/board/mpl/pati/plx9056.h deleted file mode 100644 index cd4df18..0000000 --- a/board/mpl/pati/plx9056.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter, d.peter@mpl.ch - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* PLX9096 register definitions -*/ -#ifndef __PLX9056_H_ -#define __PLX9056_H_ 1 - -#include - -#ifdef PLX9056_LOC -#define LOCAL_OFFSET 0x080 -/* PCI Config regs */ -#else -#define LOCAL_OFFSET 0x000 -#endif - -#define PCI9056_VENDOR_ID PCI_VENDOR_ID -/*#define PCI9656_DEVICE_ID PCI_DEVICE_ID */ -#define PCI9056_COMMAND PCI_COMMAND -/*#define PCI9656_STATUS PCI_STATUS */ -#define PCI9056_REVISION PCI_REVISION_ID - -#define PCI9056_CACHE_SIZE PCI_CACHE_LINE_SIZE -#define PCI9056_RTR_BASE PCI_BASE_ADDRESS_0 -#define PCI9056_RTR_IO_BASE PCI_BASE_ADDRESS_1 -#define PCI9056_LOCAL_BASE0 PCI_BASE_ADDRESS_2 -#define PCI9056_LOCAL_BASE1 PCI_BASE_ADDRESS_3 -#define PCI9056_UNUSED_BASE1 PCI_BASE_ADDRESS_4 -#define PCI9056_UNUSED_BASE2 PCI_BASE_ADDRESS_5 -#define PCI9056_CIS_PTR PCI_CARDBUS_CIS -#define PCI9056_SUB_ID PCI_SUBSYSTEM_VENDOR_ID -#define PCI9056_EXP_ROM_BASE PCI_ROM_ADDRESS -#define PCI9056_CAP_PTR PCI_CAPABILITY_LIST -#define PCI9056_INT_LINE PCI_INTERRUPT_LINE - -#if defined(PLX9056_LOC) - #define PCI9056_PM_CAP_ID 0x180 - #define PCI9056_PM_CSR 0x184 - #define PCI9056_HS_CAP_ID 0x188 - #define PCI9056_VPD_CAP_ID 0x18C - #define PCI9056_VPD_DATA 0x190 -#endif - - -#define PCI_DEVICE_ID_PLX9056 0x9056 - -/* Local Configuration Registers Accessible via the PCI Base address + Variable */ -#define PCI9056_SPACE0_RANGE (0x000 + LOCAL_OFFSET) -#define PCI9056_SPACE0_REMAP (0x004 + LOCAL_OFFSET) -#define PCI9056_LOCAL_DMA_ARBIT (0x008 + LOCAL_OFFSET) -#define PCI9056_ENDIAN_DESC (0x00c + LOCAL_OFFSET) -#define PCI9056_EXP_ROM_RANGE (0x010 + LOCAL_OFFSET) -#define PCI9056_EXP_ROM_REMAP (0x014 + LOCAL_OFFSET) -#define PCI9056_SPACE0_ROM_DESC (0x018 + LOCAL_OFFSET) -#define PCI9056_DM_RANGE (0x01c + LOCAL_OFFSET) -#define PCI9056_DM_MEM_BASE (0x020 + LOCAL_OFFSET) -#define PCI9056_DM_IO_BASE (0x024 + LOCAL_OFFSET) -#define PCI9056_DM_PCI_MEM_REMAP (0x028 + LOCAL_OFFSET) -#define PCI9056_DM_PCI_IO_CONFIG (0x02c + LOCAL_OFFSET) -#define PCI9056_SPACE1_RANGE (0x0f0 + LOCAL_OFFSET) -#define PCI9056_SPACE1_REMAP (0x0f4 + LOCAL_OFFSET) -#define PCI9056_SPACE1_DESC (0x0f8 + LOCAL_OFFSET) -#define PCI9056_DM_DAC (0x0fc + LOCAL_OFFSET) - -#ifdef PLX9056_LOC -#define PCI9056_ARBITER_CTRL 0x1A0 -#define PCI9056_ABORT_ADDRESS 0x1A4 -#endif - -/* Runtime registers PCI Address + LOCAL_OFFSET */ -#ifdef PLX9056_LOC -#define PCI9056_MAILBOX0 0x0C0 -#define PCI9056_MAILBOX1 0x0C4 -#else -#define PCI9056_MAILBOX0 0x078 -#define PCI9056_MAILBOX1 0x07c -#endif - -#define PCI9056_MAILBOX2 (0x048 + LOCAL_OFFSET) -#define PCI9056_MAILBOX3 (0x04c + LOCAL_OFFSET) -#define PCI9056_MAILBOX4 (0x050 + LOCAL_OFFSET) -#define PCI9056_MAILBOX5 (0x054 + LOCAL_OFFSET) -#define PCI9056_MAILBOX6 (0x058 + LOCAL_OFFSET) -#define PCI9056_MAILBOX7 (0x05c + LOCAL_OFFSET) -#define PCI9056_PCI_TO_LOC_DBELL (0x060 + LOCAL_OFFSET) -#define PCI9056_LOC_TO_PCI_DBELL (0x064 + LOCAL_OFFSET) -#define PCI9056_INT_CTRL_STAT (0x068 + LOCAL_OFFSET) -#define PCI9056_EEPROM_CTRL_STAT (0x06c + LOCAL_OFFSET) -#define PCI9056_PERM_VENDOR_ID (0x070 + LOCAL_OFFSET) -#define PCI9056_REVISION_ID (0x074 + LOCAL_OFFSET) - -#endif /* #ifndef __PLX9056_H_ */ diff --git a/board/mpl/pati/u-boot.lds b/board/mpl/pati/u-boot.lds deleted file mode 100644 index 5b03fef..0000000 --- a/board/mpl/pati/u-boot.lds +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de - * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc5xx/start.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -/* . = env_start; - .ppcenv : - { - common/environment.o (.ppcenv) - } -*/ -} diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile deleted file mode 100644 index a818d08..0000000 --- a/board/mpl/pip405/Makefile +++ /dev/null @@ -1,52 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o \ - ../common/flash.o cmd_pip405.o ../common/pci.o \ - ../common/isa.o ../common/kbd.o \ - ../common/usb_uhci.o \ - ../common/memtst.o ../common/common_util.o - -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c deleted file mode 100644 index 1bf4d7b..0000000 --- a/board/mpl/pip405/cmd_pip405.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * hacked for PIP405 - */ - -#include -#include -#include "pip405.h" -#include "../common/common_util.h" - - -extern void print_pip405_info(void); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - - -/* ------------------------------------------------------------------------- */ - -int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - - ulong led_on,led_nr; - - if (strcmp(argv[1], "info") == 0) - { - print_pip405_info(); - return 0; - } - if (strcmp(argv[1], "led") == 0) - { - led_nr = (ulong)simple_strtoul(argv[2], NULL, 10); - led_on = (ulong)simple_strtoul(argv[3], NULL, 10); - if(!led_nr) - user_led0(led_on); - else - user_led1(led_on); - return 0; - } - - return (do_mplcommon(cmdtp, flag, argc, argv)); -} -U_BOOT_CMD( - pip405, 6, 1, do_pip405, - "pip405 - PIP405 specific Cmds\n", - "flash mem [SrcAddr] - updates U-Boot with image in memory\n" - "pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n" - "pip405 flash mps - updates U-Boot with image from MPS\n" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pip405/config.mk b/board/mpl/pip405/config.mk deleted file mode 100644 index 0f8d153..0000000 --- a/board/mpl/pip405/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0xFFF80000 diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S deleted file mode 100644 index 39f2ea5..0000000 --- a/board/mpl/pip405/init.S +++ /dev/null @@ -1,230 +0,0 @@ -/*------------------------------------------------------------------------------+ - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *-------------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------- - * Function: ext_bus_cntlr_init - * Description: Initializes the External Bus Controller for the external - * peripherals. IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * Bank 0 - Flash or Multi Purpose Socket - * Bank 1 - Multi Purpose Socket or Flash - * Bank 2 - not used - * Bank 3 - not used - * Bank 4 - not used - * Bank 5 - not used - * Bank 6 - used to switch on the 12V for the Multipurpose socket - * Bank 7 - Config Register - *-----------------------------------------------------------------------------*/ -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include -#include - -#include -#include -#include "pip405.h" - - .globl ext_bus_cntlr_init - ext_bus_cntlr_init: - mflr r4 /* save link register */ - mfdcr r3,strap /* get strapping reg */ - andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ - bnelr /* jump back if PCI boot */ - - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 14; used to prefetch */ - mtctr r4 /* 14 cache lines to fit this function */ - /* in cache (gives us 8x14=112 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 14 cache lines */ - - /*------------------------------------------------------------------- - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. - *------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /*----------------------------------------------------------------------- - * decide boot up mode - *----------------------------------------------------------------------- */ - addi r4,0,pb0cr - mtdcr ebccfga,r4 - mfdcr r4,ebccfgd - - andi. r0, r4, 0x2000 /* mask out irrelevant bits */ - beq 0f /* jump if 8 bit bus width */ - - /* setup 16 bit things - *----------------------------------------------------------------------- - * Memory Bank 0 (16 Bit Flash) initialization - *---------------------------------------------------------------------- */ - - addi r4,0,pb0ap - mtdcr ebccfga,r4 - addis r4,0,(FLASH_AP_B)@h - ori r4,r4,(FLASH_AP_B)@l - mtdcr ebccfgd,r4 - - addi r4,0,pb0cr - mtdcr ebccfga,r4 - /* BS=0x010(4MB),BU=0x3(R/W), */ - addis r4,0,(FLASH_CR_B)@h - ori r4,r4,(FLASH_CR_B)@l - mtdcr ebccfgd,r4 - b 1f - -0: - /* 8Bit boot mode: */ - /*----------------------------------------------------------------------- - * Memory Bank 0 Multi Purpose Socket initialization - *----------------------------------------------------------------------- */ - /* 0x7F8FFE80 slowest boot */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 - addis r4,0,(MPS_AP_B)@h - ori r4,r4,(MPS_AP_B)@l - mtdcr ebccfgd,r4 - - addi r4,0,pb0cr - mtdcr ebccfga,r4 - /* BS=0x010(4MB),BU=0x3(R/W), */ - addis r4,0,(MPS_CR_B)@h - ori r4,r4,(MPS_CR_B)@l - mtdcr ebccfgd,r4 - - -1: - /*----------------------------------------------------------------------- - * Memory Bank 2-3-4-5-6 (not used) initialization - *-----------------------------------------------------------------------*/ - addi r4,0,pb1cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb2cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb3cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb4cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb5cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb6cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - - addi r4,0,pb7cr - mtdcr ebccfga,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr ebccfgd,r4 - nop /* pass2 DCR errata #8 */ - blr - -/*----------------------------------------------------------------------------- - * Function: sdram_init - * Description: Configures the internal SRAM memory. and setup the - * Stackpointer in it. - *----------------------------------------------------------------------------- */ - .globl sdram_init - -sdram_init: - - - blr - - -#if defined(CONFIG_BOOT_PCI) - .section .bootpg,"ax" - .globl _start_pci -/******************************************* - */ - -_start_pci: - /* first handle errata #68 / PCI_18 */ - iccci r0, r0 /* invalidate I-cache */ - lis r31, 0 - mticcr r31 /* ICCR = 0 (all uncachable) */ - isync - - mfccr0 r28 /* set CCR0[24] = 1 */ - ori r28, r28, 0x0080 - mtccr0 r28 - - /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ - lis r28, 0xEF40 - addi r28, r28, 0x0004 - stw r31, 0x0C(r28) /* clear PMM0PCIHA */ - lis r29, 0xFFF8 /* open 512 kByte */ - addi r29, r29, 0x0001/* and enable this region */ - stwbrx r29, r0, r28 /* write PMM0MA */ - - lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ - addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ - - lis r31, 0x8000 /* set en bit bus 0 */ - ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ - stwbrx r31, r0, r28 /* write it */ - - lwbrx r31, r0, r29 /* load XBCS register */ - oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ - stwbrx r31, r0, r29 /* write back XBCS register */ - - nop - nop - b _start /* normal start */ -#endif diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c deleted file mode 100644 index a398362..0000000 --- a/board/mpl/pip405/pip405.c +++ /dev/null @@ -1,960 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - * TODO: clean-up - */ - -#include -#include "pip405.h" -#include -#include -#include "../common/isa.h" -#include "../common/common_util.h" - -#undef SDRAM_DEBUG - -#define FALSE 0 -#define TRUE 1 - -/* stdlib.h causes some compatibility problems; should fixe these! -- wd */ -#ifndef __ldiv_t_defined -typedef struct { - long int quot; /* Quotient */ - long int rem; /* Remainder */ -} ldiv_t; -extern ldiv_t ldiv (long int __numer, long int __denom); - -# define __ldiv_t_defined 1 -#endif - - -typedef enum { - SDRAM_NO_ERR, - SDRAM_SPD_COMM_ERR, - SDRAM_SPD_CHKSUM_ERR, - SDRAM_UNSUPPORTED_ERR, - SDRAM_UNKNOWN_ERR -} SDRAM_ERR; - -typedef struct { - const unsigned char mode; - const unsigned char row; - const unsigned char col; - const unsigned char bank; -} SDRAM_SETUP; - -static const SDRAM_SETUP sdram_setup_table[] = { - {1, 11, 9, 2}, - {1, 11, 10, 2}, - {2, 12, 9, 4}, - {2, 12, 10, 4}, - {3, 13, 9, 4}, - {3, 13, 10, 4}, - {3, 13, 11, 4}, - {4, 12, 8, 2}, - {4, 12, 8, 4}, - {5, 11, 8, 2}, - {5, 11, 8, 4}, - {6, 13, 8, 2}, - {6, 13, 8, 4}, - {7, 13, 9, 2}, - {7, 13, 10, 2}, - {0, 0, 0, 0} -}; - -static const unsigned char cal_indextable[] = { - 9, 23, 25 -}; - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ - -unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns.ns/4 coding of SPD timing values - * into 10 ps unit values - */ - -unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version) -{ - unsigned short ns, ns4; - - /* isolate upper 6 bits */ - ns = (spd_byte >> 2) & 0x3F; - /* isloate lower 2 bits */ - ns4 = (spd_byte & 0x03); - - return (ns * 100 + ns4 * 25); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ - -unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - -void SDRAM_err (const char *s) -{ -#ifndef SDRAM_DEBUG - DECLARE_GLOBAL_DATA_PTR; - - (void) get_clocks (); - gd->baudrate = 9600; - serial_init (); -#endif - serial_puts ("\n"); - serial_puts (s); - serial_puts ("\n enable SDRAM_DEBUG for more info\n"); - for (;;); -} - - -#ifdef SDRAM_DEBUG - -void write_hex (unsigned char i) -{ - char cc; - - cc = i >> 4; - cc &= 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); - cc = i & 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); -} - -void write_4hex (unsigned long val) -{ - write_hex ((unsigned char) (val >> 24)); - write_hex ((unsigned char) (val >> 16)); - write_hex ((unsigned char) (val >> 8)); - write_hex ((unsigned char) val); -} - -#endif - -int board_early_init_f (void) -{ - unsigned char dataout[1]; - unsigned char datain[128]; - unsigned long sdram_size = 0; - SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table; - unsigned long memclk; - unsigned long tmemclk = 0; - unsigned long tmp, bank, baseaddr, bank_size; - unsigned short i; - unsigned char rows, cols, banks, sdram_banks, density; - unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks, - trc_clocks, tctp_clocks; - unsigned char cal_index, cal_val, spd_version, spd_chksum; - unsigned char buf[8]; -#ifdef SDRAM_DEBUG - DECLARE_GLOBAL_DATA_PTR; -#endif - /* set up the config port */ - mtdcr (ebccfga, pb7ap); - mtdcr (ebccfgd, CONFIG_PORT_AP); - mtdcr (ebccfga, pb7cr); - mtdcr (ebccfgd, CONFIG_PORT_CR); - - memclk = get_bus_freq (tmemclk); - tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - -#ifdef SDRAM_DEBUG - (void) get_clocks (); - gd->baudrate = 9600; - serial_init (); - serial_puts ("\nstart SDRAM Setup\n"); -#endif - - /* Read Serial Presence Detect Information */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - dataout[0] = 0; - for (i = 0; i < 128; i++) - datain[i] = 127; - i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128); -#ifdef SDRAM_DEBUG - serial_puts ("\ni2c_read returns "); - write_hex (i); - serial_puts ("\n"); -#endif - -#ifdef SDRAM_DEBUG - for (i = 0; i < 128; i++) { - write_hex (datain[i]); - serial_puts (" "); - if (((i + 1) % 16) == 0) - serial_puts ("\n"); - } - serial_puts ("\n"); -#endif - spd_chksum = 0; - for (i = 0; i < 63; i++) { - spd_chksum += datain[i]; - } /* endfor */ - if (datain[63] != spd_chksum) { -#ifdef SDRAM_DEBUG - serial_puts ("SPD chksum: 0x"); - write_hex (datain[63]); - serial_puts (" != calc. chksum: 0x"); - write_hex (spd_chksum); - serial_puts ("\n"); -#endif - SDRAM_err ("SPD checksum Error"); - } - /* SPD seems to be ok, use it */ - - /* get SPD version */ - spd_version = datain[62]; - - /* do some sanity checks on the kind of RAM */ - if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */ - (datain[2] != 0x04) || /* if not SDRAM */ - (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */ - (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */ - (datain[126] == 0x66)) /* or a 66Mhz modules */ - SDRAM_err ("unsupported SDRAM"); -#ifdef SDRAM_DEBUG - serial_puts ("SDRAM sanity ok\n"); -#endif - - /* get number of rows/cols/banks out of byte 3+4+5 */ - rows = datain[3]; - cols = datain[4]; - banks = datain[5]; - - /* get number of SDRAM banks out of byte 17 and - supported CAS latencies out of byte 18 */ - sdram_banks = datain[17]; - supported_cal = datain[18] & ~0x81; - - while (t->mode != 0) { - if ((t->row == rows) && (t->col == cols) - && (t->bank == sdram_banks)) - break; - t++; - } /* endwhile */ - -#ifdef SDRAM_DEBUG - serial_puts ("rows: "); - write_hex (rows); - serial_puts (" cols: "); - write_hex (cols); - serial_puts (" banks: "); - write_hex (banks); - serial_puts (" mode: "); - write_hex (t->mode); - serial_puts ("\n"); -#endif - if (t->mode == 0) - SDRAM_err ("unsupported SDRAM"); - /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */ -#ifdef SDRAM_DEBUG - serial_puts ("tRP: "); - write_hex (datain[27]); - serial_puts ("\ntRCD: "); - write_hex (datain[29]); - serial_puts ("\ntRAS: "); - write_hex (datain[30]); - serial_puts ("\n"); -#endif - - trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk; - trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk; - tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk; - density = datain[31]; - - /* trc_clocks is sum of trp_clocks + tras_clocks */ - trc_clocks = trp_clocks + tras_clocks; - /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ - tctp_clocks = - ((NSto10PS (datain[30]) - NSto10PS (datain[29])) + - (tmemclk - 1)) / tmemclk; - -#ifdef SDRAM_DEBUG - serial_puts ("c_RP: "); - write_hex (trp_clocks); - serial_puts ("\nc_RCD: "); - write_hex (trcd_clocks); - serial_puts ("\nc_RAS: "); - write_hex (tras_clocks); - serial_puts ("\nc_RC: (RP+RAS): "); - write_hex (trc_clocks); - serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): "); - write_hex (tctp_clocks); - serial_puts ("\nt_CTP: RAS - RCD: "); - write_hex ((unsigned - char) ((NSto10PS (datain[30]) - - NSto10PS (datain[29])) >> 8)); - write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29]))); - serial_puts ("\ntmemclk: "); - write_hex ((unsigned char) (tmemclk >> 8)); - write_hex ((unsigned char) (tmemclk)); - serial_puts ("\n"); -#endif - - - cal_val = 255; - for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) { - /* is this CAS latency supported ? */ - if ((supported_cal >> i) & 0x01) { - buf[0] = datain[cal_indextable[cal_index]]; - if (cal_index < 2) { - if (NS10to10PS (buf[0], spd_version) <= tmemclk) - cal_val = i; - } else { - /* SPD bytes 25+26 have another format */ - if (NS4to10PS (buf[0], spd_version) <= tmemclk) - cal_val = i; - } /* endif */ - cal_index++; - } /* endif */ - } /* endfor */ -#ifdef SDRAM_DEBUG - serial_puts ("CAL: "); - write_hex (cal_val + 1); - serial_puts ("\n"); -#endif - - if (cal_val == 255) - SDRAM_err ("unsupported SDRAM"); - - /* get SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - tmp = mfdcr (memcfgd) & ~0x018FC01F; - /* insert CASL value */ -/* tmp |= ((unsigned long)cal_val) << 23; */ - tmp |= ((unsigned long) cal_val) << 23; - /* insert PTA value */ - tmp |= ((unsigned long) (trp_clocks - 1)) << 18; - /* insert CTP value */ -/* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */ - tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16; - /* insert LDF (always 01) */ - tmp |= ((unsigned long) 0x01) << 14; - /* insert RFTA value */ - tmp |= ((unsigned long) (trc_clocks - 4)) << 2; - /* insert RCD value */ - tmp |= ((unsigned long) (trcd_clocks - 1)) << 0; - -#ifdef SDRAM_DEBUG - serial_puts ("sdtr: "); - write_4hex (tmp); - serial_puts ("\n"); -#endif - - /* write SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, tmp); - baseaddr = CFG_SDRAM_BASE; - bank_size = (((unsigned long) density) << 22) / 2; - /* insert AM value */ - tmp = ((unsigned long) t->mode - 1) << 13; - /* insert SZ value; */ - switch (bank_size) { - case 0x00400000: - tmp |= ((unsigned long) 0x00) << 17; - break; - case 0x00800000: - tmp |= ((unsigned long) 0x01) << 17; - break; - case 0x01000000: - tmp |= ((unsigned long) 0x02) << 17; - break; - case 0x02000000: - tmp |= ((unsigned long) 0x03) << 17; - break; - case 0x04000000: - tmp |= ((unsigned long) 0x04) << 17; - break; - case 0x08000000: - tmp |= ((unsigned long) 0x05) << 17; - break; - case 0x10000000: - tmp |= ((unsigned long) 0x06) << 17; - break; - default: - SDRAM_err ("unsupported SDRAM"); - } /* endswitch */ - /* get SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; - bank |= (baseaddr | tmp | 0x01); -#ifdef SDRAM_DEBUG - serial_puts ("bank0: baseaddr: "); - write_4hex (baseaddr); - serial_puts (" banksize: "); - write_4hex (bank_size); - serial_puts (" mb0cf: "); - write_4hex (bank); - serial_puts ("\n"); -#endif - baseaddr += bank_size; - sdram_size += bank_size; - - /* write SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, bank); - - /* get SDRAM bank 1 register */ - mtdcr (memcfga, mem_mb1cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; - sdram_size = 0; - -#ifdef SDRAM_DEBUG - serial_puts ("bank1: baseaddr: "); - write_4hex (baseaddr); - serial_puts (" banksize: "); - write_4hex (bank_size); -#endif - if (banks == 2) { - bank |= (baseaddr | tmp | 0x01); - baseaddr += bank_size; - sdram_size += bank_size; - } /* endif */ -#ifdef SDRAM_DEBUG - serial_puts (" mb1cf: "); - write_4hex (bank); - serial_puts ("\n"); -#endif - /* write SDRAM bank 1 register */ - mtdcr (memcfga, mem_mb1cf); - mtdcr (memcfgd, bank); - - /* get SDRAM bank 2 register */ - mtdcr (memcfga, mem_mb2cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; - - bank |= (baseaddr | tmp | 0x01); - -#ifdef SDRAM_DEBUG - serial_puts ("bank2: baseaddr: "); - write_4hex (baseaddr); - serial_puts (" banksize: "); - write_4hex (bank_size); - serial_puts (" mb2cf: "); - write_4hex (bank); - serial_puts ("\n"); -#endif - - baseaddr += bank_size; - sdram_size += bank_size; - - /* write SDRAM bank 2 register */ - mtdcr (memcfga, mem_mb2cf); - mtdcr (memcfgd, bank); - - /* get SDRAM bank 3 register */ - mtdcr (memcfga, mem_mb3cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; - -#ifdef SDRAM_DEBUG - serial_puts ("bank3: baseaddr: "); - write_4hex (baseaddr); - serial_puts (" banksize: "); - write_4hex (bank_size); -#endif - - if (banks == 2) { - bank |= (baseaddr | tmp | 0x01); - baseaddr += bank_size; - sdram_size += bank_size; - } - /* endif */ -#ifdef SDRAM_DEBUG - serial_puts (" mb3cf: "); - write_4hex (bank); - serial_puts ("\n"); -#endif - - /* write SDRAM bank 3 register */ - mtdcr (memcfga, mem_mb3cf); - mtdcr (memcfgd, bank); - - - /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; - - if (tmemclk < NSto10PS (16)) - tmp |= 0x05F00000; - else - tmp |= 0x03F80000; - - /* write SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, tmp); - - /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); - - - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the PIP405 board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive - | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive - | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for PIP405 board: - | An interrupt taken for the SouthBridge (IRQ 25) indicates that - | the Interrupt Controller in the South Bridge has caused the - | interrupt. The IC must be read to determine which device - | caused the interrupt. - | - +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char s[50]; - unsigned char bc; - int i; - backup_t *b = (backup_t *) s; - - puts ("Board: "); - - i = getenv_r ("serial#", (char *)s, 32); - if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) { - get_backup_values (b); - if (strncmp (b->signature, "MPL\0", 4) != 0) { - puts ("### No HW ID - assuming PIP405"); - } else { - b->serial_name[6] = 0; - printf ("%s SN: %s", b->serial_name, - &b->serial_name[7]); - } - } else { - s[6] = 0; - printf ("%s SN: %s", s, &s[7]); - } - bc = in8 (CONFIG_PORT_ADDR); - printf (" Boot Config: 0x%x\n", bc); - return (0); -} - - -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -/* - initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of - the necessary info for SDRAM controller configuration -*/ -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -static int test_dram (unsigned long ramsize); - -long int initdram (int board_type) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned long bank_reg[4], tmp, bank_size; - int i, ds; - unsigned long TotalSize; - - ds = 0; - /* since the DRAM controller is allready set up, - * calculate the size with the bank registers - */ - mtdcr (memcfga, mem_mb0cf); - bank_reg[0] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb1cf); - bank_reg[1] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb2cf); - bank_reg[2] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb3cf); - bank_reg[3] = mfdcr (memcfgd); - TotalSize = 0; - for (i = 0; i < 4; i++) { - if ((bank_reg[i] & 0x1) == 0x1) { - tmp = (bank_reg[i] >> 17) & 0x7; - bank_size = 4 << tmp; - TotalSize += bank_size; - } else - ds = 1; - } - if (ds == 1) - printf ("single-sided DIMM "); - else - printf ("double-sided DIMM "); - test_dram (TotalSize * 1024 * 1024); - /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */ - (void) get_clocks(); - if (gd->cpu_clk > 220000000) - TotalSize /= 2; - return (TotalSize * 1024 * 1024); -} - -/* ------------------------------------------------------------------------- */ - - -static int test_dram (unsigned long ramsize) -{ - /* not yet implemented */ - return (1); -} - - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - /* adjust flash start and size as well as the offset */ - gd->bd->bi_flashstart=0-flash_info[0].size; - gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN; - gd->bd->bi_flashoffset=0; - - /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ - if (mfdcr(strap) & PSR_ROM_LOC) - mtspr(ccr0, (mfspr(ccr0) & ~0x80)); - - return (0); -} - -/*************************************************************************** - * some helping routines - */ - -int overwrite_console (void) -{ - return (in8 (CONFIG_PORT_ADDR) & 0x1); /* return TRUE if console should be overwritten */ -} - - -extern int isa_init (void); - - -void print_pip405_rev (void) -{ - unsigned char part, vers, cfg; - - part = in8 (PLD_PART_REG); - vers = in8 (PLD_VERS_REG); - cfg = in8 (PLD_BOARD_CFG_REG); - printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n", - 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf, - vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf); -} - -extern void check_env(void); - - -int last_stage_init (void) -{ - print_pip405_rev (); - isa_init (); - show_stdio_dev (); - check_env(); - return 0; -} - -/************************************************************************ -* Print PIP405 Info -************************************************************************/ -void print_pip405_info (void) -{ - unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr, - compwr, nicvga, scsirst; - - part = in8 (PLD_PART_REG); - vers = in8 (PLD_VERS_REG); - cfg = in8 (PLD_BOARD_CFG_REG); - ledu = in8 (PLD_LED_USER_REG); - sysman = in8 (PLD_SYS_MAN_REG); - flashcom = in8 (PLD_FLASH_COM_REG); - can = in8 (PLD_CAN_REG); - serpwr = in8 (PLD_SER_PWR_REG); - compwr = in8 (PLD_COM_PWR_REG); - nicvga = in8 (PLD_NIC_VGA_REG); - scsirst = in8 (PLD_SCSI_RST_REG); - printf ("PLD Part %d version %d\n", - part & 0xf, vers & 0xf); - printf ("PLD Part %d version %d\n", - (part >> 4) & 0xf, (vers >> 4) & 0xf); - printf ("Board Revision %c\n", (cfg & 0xf) + 'A'); - printf ("Population Options %d %d %d %d\n", - (cfg >> 4) & 0x1, (cfg >> 5) & 0x1, - (cfg >> 6) & 0x1, (cfg >> 7) & 0x1); - printf ("User LED0 %s User LED1 %s\n", - ((ledu & 0x1) == 0x1) ? "on" : "off", - ((ledu & 0x2) == 0x2) ? "on" : "off"); - printf ("Additionally Options %d %d\n", - (ledu >> 2) & 0x1, (ledu >> 3) & 0x1); - printf ("User Config Switch %d %d %d %d\n", - (ledu >> 4) & 0x1, (ledu >> 5) & 0x1, - (ledu >> 6) & 0x1, (ledu >> 7) & 0x1); - switch (sysman & 0x3) { - case 0: - printf ("PCI Clocks are running\n"); - break; - case 1: - printf ("PCI Clocks are stopped in POS State\n"); - break; - case 2: - printf ("PCI Clocks are stopped when PCI_STP# is asserted\n"); - break; - case 3: - printf ("PCI Clocks are stopped\n"); - break; - } - switch ((sysman >> 2) & 0x3) { - case 0: - printf ("Main Clocks are running\n"); - break; - case 1: - printf ("Main Clocks are stopped in POS State\n"); - break; - case 2: - case 3: - printf ("PCI Clocks are stopped\n"); - break; - } - printf ("INIT asserts %sINT2# (SMI)\n", - ((sysman & 0x10) == 0x10) ? "" : "not "); - printf ("INIT asserts %sINT1# (NMI)\n", - ((sysman & 0x20) == 0x20) ? "" : "not "); - printf ("INIT occured %d\n", (sysman >> 6) & 0x1); - printf ("SER1 is routed to %s\n", - ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232"); - printf ("COM2 is routed to %s\n", - ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232"); - printf ("RS485 is configured as %s duplex\n", - ((flashcom & 0x4) == 0x4) ? "full" : "half"); - printf ("RS485 is connected to %s\n", - ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2"); - printf ("SER1 uses handshakes %s\n", - ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS"); - printf ("Bootflash is %swriteprotected\n", - ((flashcom & 0x20) == 0x20) ? "not " : ""); - printf ("Bootflash VPP is %s\n", - ((flashcom & 0x40) == 0x40) ? "on" : "off"); - printf ("Bootsector is %swriteprotected\n", - ((flashcom & 0x80) == 0x80) ? "not " : ""); - switch ((can) & 0x3) { - case 0: - printf ("CAN Controller is on address 0x1000..0x10FF\n"); - break; - case 1: - printf ("CAN Controller is on address 0x8000..0x80FF\n"); - break; - case 2: - printf ("CAN Controller is on address 0xE000..0xE0FF\n"); - break; - case 3: - printf ("CAN Controller is disabled\n"); - break; - } - switch ((can >> 2) & 0x3) { - case 0: - printf ("CAN Controller Reset is ISA Reset\n"); - break; - case 1: - printf ("CAN Controller Reset is ISA Reset and POS State\n"); - break; - case 2: - case 3: - printf ("CAN Controller is in reset\n"); - break; - } - if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13)) - printf ("CAN Interrupt is disabled\n"); - else - printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf); - switch (serpwr & 0x3) { - case 0: - printf ("SER0 Drivers are enabled\n"); - break; - case 1: - printf ("SER0 Drivers are disabled in the POS state\n"); - break; - case 2: - case 3: - printf ("SER0 Drivers are disabled\n"); - break; - } - switch ((serpwr >> 2) & 0x3) { - case 0: - printf ("SER1 Drivers are enabled\n"); - break; - case 1: - printf ("SER1 Drivers are disabled in the POS state\n"); - break; - case 2: - case 3: - printf ("SER1 Drivers are disabled\n"); - break; - } - switch (compwr & 0x3) { - case 0: - printf ("COM1 Drivers are enabled\n"); - break; - case 1: - printf ("COM1 Drivers are disabled in the POS state\n"); - break; - case 2: - case 3: - printf ("COM1 Drivers are disabled\n"); - break; - } - switch ((compwr >> 2) & 0x3) { - case 0: - printf ("COM2 Drivers are enabled\n"); - break; - case 1: - printf ("COM2 Drivers are disabled in the POS state\n"); - break; - case 2: - case 3: - printf ("COM2 Drivers are disabled\n"); - break; - } - switch ((nicvga) & 0x3) { - case 0: - printf ("PHY is running\n"); - break; - case 1: - printf ("PHY is in Power save mode in POS state\n"); - break; - case 2: - case 3: - printf ("PHY is in Power save mode\n"); - break; - } - switch ((nicvga >> 2) & 0x3) { - case 0: - printf ("VGA is running\n"); - break; - case 1: - printf ("VGA is in Power save mode in POS state\n"); - break; - case 2: - case 3: - printf ("VGA is in Power save mode\n"); - break; - } - printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not "); - printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not "); - printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1, - (nicvga >> 7) & 0x1); - switch ((scsirst) & 0x3) { - case 0: - printf ("SCSI Controller is running\n"); - break; - case 1: - printf ("SCSI Controller is in Power save mode in POS state\n"); - break; - case 2: - case 3: - printf ("SCSI Controller is in Power save mode\n"); - break; - } - printf ("SCSI termination is %s\n", - ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled"); - printf ("SCSI Controller is %sreseted\n", - ((scsirst & 0x10) == 0x10) ? "" : "not "); - printf ("IDE disks are %sreseted\n", - ((scsirst & 0x20) == 0x20) ? "" : "not "); - printf ("ISA Bus is %sreseted\n", - ((scsirst & 0x40) == 0x40) ? "" : "not "); - printf ("Super IO is %sreseted\n", - ((scsirst & 0x80) == 0x80) ? "" : "not "); -} - -void user_led0 (unsigned char on) -{ - if (on == TRUE) - out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1)); - else - out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe)); -} - -void user_led1 (unsigned char on) -{ - if (on == TRUE) - out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2)); - else - out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd)); -} - -void ide_set_reset (int idereset) -{ - /* if reset = 1 IDE reset will be asserted */ - unsigned char resreg; - - resreg = in8 (PLD_SCSI_RST_REG); - if (idereset == 1) - resreg |= 0x20; - else { - udelay(10000); - resreg &= 0xdf; - } - out8 (PLD_SCSI_RST_REG, resreg); -} diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h deleted file mode 100644 index b41c5bb..0000000 --- a/board/mpl/pip405/pip405.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - /**************************************************************************** - * Global routines used for PIP405 - *****************************************************************************/ - -#ifndef __ASSEMBLY__ - -extern int mem_test(unsigned long start, unsigned long ramsize,int mode); - -void print_pip405_info(void); - -void user_led0(unsigned char on); -void user_led1(unsigned char on); - - -#define PLD_BASE_ADDRESS CFG_ISA_IO_BASE_ADDRESS + 0x800 -#define PLD_PART_REG PLD_BASE_ADDRESS + 0 -#define PLD_VERS_REG PLD_BASE_ADDRESS + 1 -#define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2 -#define PLD_LED_USER_REG PLD_BASE_ADDRESS + 3 -#define PLD_SYS_MAN_REG PLD_BASE_ADDRESS + 4 -#define PLD_FLASH_COM_REG PLD_BASE_ADDRESS + 5 -#define PLD_CAN_REG PLD_BASE_ADDRESS + 6 -#define PLD_SER_PWR_REG PLD_BASE_ADDRESS + 7 -#define PLD_COM_PWR_REG PLD_BASE_ADDRESS + 8 -#define PLD_NIC_VGA_REG PLD_BASE_ADDRESS + 9 -#define PLD_SCSI_RST_REG PLD_BASE_ADDRESS + 0xA - -#define PIIX4_VENDOR_ID 0x8086 -#define PIIX4_IDE_DEV_ID 0x7111 - -#endif - -/* timings */ - -/* CS Config register (CS7) */ -#define CONFIG_PORT_BME 0 /* Burst disable */ -#define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ -#define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */ -#define CONFIG_PORT_WBN 1 /* Cycles from CS low to WE low */ -#define CONFIG_PORT_WBF 1 /* Cycles from WE high to CS high */ -#define CONFIG_PORT_TH 2 /* Number of hold cycles after transfer */ -#define CONFIG_PORT_RE 0 /* Ready disabled */ -#define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */ -#define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */ -#define CONFIG_PORT_PEN 0 /* Parity disable */ -#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \ - (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define CONFIG_PORT_BS 0 /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define CONFIG_PORT_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define CONFIG_PORT_BW 0 /* 16Bit */ -#define CONFIG_PORT_CR ((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13)) - -/* Flash CS0 or CS 1 */ -/* 0x7F8FFE80 slowest timing at all... */ -#define FLASH_BME_B 1 /* Burst enable */ -#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ -#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define FLASH_BME 0 /* Burst disable */ -#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ -#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define FLASH_OEN 1 /* Cycles from CS low to OE low */ -#define FLASH_WBN 1 /* Cycles from CS low to WE low */ -#define FLASH_WBF 1 /* Cycles from WE high to CS high */ -#define FLASH_TH 2 /* Number of hold cycles after transfer */ -#define FLASH_RE 0 /* Ready disabled */ -#define FLASH_SOR 1 /* Sample on Ready disabled */ -#define FLASH_BEM 0 /* Byte Write only active on Write cycles */ -#define FLASH_PEN 0 /* Parity disable */ -/* Access Parameter Register for non Boot */ -#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ - (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) -/* Access Parameter Register for Boot */ -#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ - (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define FLASH_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define FLASH_BW 1 /* 16Bit */ -/* CR register for Boot */ -#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) -/* CR register for non Boot */ -#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) - -/* MPS CS1 or CS0 */ -/* Boot CS: */ -#define MPS_BME_B 1 /* Burst enable */ -#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ -#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define MPS_BME 0 /* Burst disable */ -#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ -#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define MPS_OEN 1 /* Cycles from CS low to OE low */ -#define MPS_WBN 1 /* Cycles from CS low to WE low */ -#define MPS_WBF 1 /* Cycles from WE high to CS high */ -#define MPS_TH 2 /* Number of hold cycles after transfer */ -#define MPS_RE 0 /* Ready disabled */ -#define MPS_SOR 1 /* Sample on Ready disabled */ -#define MPS_BEM 0 /* Byte Write only active on Write cycles */ -#define MPS_PEN 0 /* Parity disable */ -/* Access Parameter Register for non Boot */ -#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ - (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) -/* Access Parameter Register for Boot */ -#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ - (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define MPS_BS 2 /* 4 MByte */ -#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define MPS_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define MPS_BW 0 /* 8Bit */ -/* CR register for Boot */ -#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) -/* CR register for non Boot */ -#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds deleted file mode 100644 index 11819a4..0000000 --- a/board/mpl/pip405/u-boot.lds +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/mpl/pip405/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug deleted file mode 100644 index 1608f8c..0000000 --- a/board/mpl/pip405/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile deleted file mode 100644 index 304c965..0000000 --- a/board/mpl/vcma9/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := vcma9.o flash.o cmd_vcma9.o -OBJS += ../common/common_util.o ../common/memtst.o - -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c deleted file mode 100644 index 44b4112..0000000 --- a/board/mpl/vcma9/cmd_vcma9.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2002 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * adapted for VCMA9 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include "vcma9.h" -#include "../common/common_util.h" - -#if defined(CONFIG_DRIVER_CS8900) -#include <../drivers/cs8900.h> - -static uchar cs8900_chksum(ushort data) -{ - return((data >> 8) & 0x00FF) + (data & 0x00FF); -} - -#endif - -extern void print_vcma9_info(void); -extern int vcma9_cantest(int); -extern int vcma9_nandtest(void); -extern int vcma9_nanderase(void); -extern int vcma9_nandread(ulong); -extern int vcma9_nandwrite(ulong); -extern int vcma9_dactest(int); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -/* ------------------------------------------------------------------------- */ - -int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - DECLARE_GLOBAL_DATA_PTR; - - if (strcmp(argv[1], "info") == 0) - { - print_vcma9_info(); - return 0; - } -#if defined(CONFIG_DRIVER_CS8900) - if (strcmp(argv[1], "cs8900") == 0) { - if (strcmp(argv[2], "read") == 0) { - uchar addr; ushort data; - - addr = simple_strtoul(argv[3], NULL, 16); - cs8900_e2prom_read(addr, &data); - printf("0x%2.2X: 0x%4.4X\n", addr, data); - } else if (strcmp(argv[2], "write") == 0) { - uchar addr; ushort data; - - addr = simple_strtoul(argv[3], NULL, 16); - data = simple_strtoul(argv[4], NULL, 16); - cs8900_e2prom_write(addr, data); - } else if (strcmp(argv[2], "setaddr") == 0) { - uchar addr, i, csum; ushort data; - - /* check for valid ethaddr */ - for (i = 0; i < 6; i++) - if (gd->bd->bi_enetaddr[i] != 0) - break; - - if (i < 6) { - addr = 1; - data = 0x2158; - cs8900_e2prom_write(addr, data); - csum = cs8900_chksum(data); - addr++; - for (i = 0; i < 6; i+=2) { - data = gd->bd->bi_enetaddr[i+1] << 8 | - gd->bd->bi_enetaddr[i]; - cs8900_e2prom_write(addr, data); - csum += cs8900_chksum(data); - addr++; - } - /* calculate header link byte */ - data = 0xA100 | (addr * 2); - cs8900_e2prom_write(0, data); - csum += cs8900_chksum(data); - /* write checksum word */ - cs8900_e2prom_write(addr, (0 - csum) << 8); - } else { - puts("\nplease defined 'ethaddr'\n"); - } - } else if (strcmp(argv[2], "dump") == 0) { - uchar addr = 0, endaddr, csum; ushort data; - - puts("Dump of CS8900 config device: "); - cs8900_e2prom_read(addr, &data); - if ((data & 0xE000) == 0xA000) { - endaddr = (data & 0x00FF) / 2; - csum = cs8900_chksum(data); - for (addr = 1; addr <= endaddr; addr++) { - cs8900_e2prom_read(addr, &data); - printf("\n0x%2.2X: 0x%4.4X", addr, data); - csum += cs8900_chksum(data); - } - printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong"); - } else { - puts("no valid config found"); - } - puts("\n"); - } - - return 0; - } -#endif -#if 0 - if (strcmp(argv[1], "cantest") == 0) { - if (argc >= 3) - vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1); - else - vcma9_cantest(0); - return 0; - } - if (strcmp(argv[1], "nandtest") == 0) { - vcma9_nandtest(); - return 0; - } - if (strcmp(argv[1], "nanderase") == 0) { - vcma9_nanderase(); - return 0; - } - if (strcmp(argv[1], "nandread") == 0) { - ulong offset = 0; - - if (argc >= 3) - offset = simple_strtoul(argv[2], NULL, 16); - - vcma9_nandread(offset); - return 0; - } - if (strcmp(argv[1], "nandwrite") == 0) { - ulong offset = 0; - - if (argc >= 3) - offset = simple_strtoul(argv[2], NULL, 16); - - vcma9_nandwrite(offset); - return 0; - } - if (strcmp(argv[1], "dactest") == 0) { - if (argc >= 3) - vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1); - else - vcma9_dactest(0); - return 0; - } -#endif - - return (do_mplcommon(cmdtp, flag, argc, argv)); -} - -U_BOOT_CMD( - vcma9, 6, 1, do_vcma9, - "vcma9 - VCMA9 specific commands\n", - "flash mem [SrcAddr]\n - updates U-Boot with image in memory\n" -); diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk deleted file mode 100644 index 1fa09c9..0000000 --- a/board/mpl/vcma9/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2002, 2003 -# David Mueller, ELSOFT AG, -# -# MPL VCMA9 board with S3C2410X (ARM920T) cpu -# -# see http://www.mpl.ch/ for more information about the MPL VCMA9 -# - -# -# MPL VCMA9 has 1 bank of minimal 16 MB DRAM -# from 0x30000000 -# -# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 -# optionally with a ramdisk at 3040'0000 -# -# we load ourself to 33F8'0000 -# -# download area is 3080'0000 -# - - -#TEXT_BASE = 0x30F80000 -TEXT_BASE = 0x33F80000 diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c deleted file mode 100644 index ccfe176..0000000 --- a/board/mpl/vcma9/flash.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -ulong myflush (void); - - -#define FLASH_BANK_SIZE PHYS_FLASH_SIZE -#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x000000F0 -#define CMD_UNLOCK1 0x000000AA -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000A0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = -#if defined(CONFIG_AMD_LV400) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV400B & FLASH_TYPEMASK); -#elif defined(CONFIG_AMD_LV800) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); -#else -#error "Unknown flash configured" -#endif - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 3) { - /* 1st one is 16 KB */ - if (j == 0) { - flash_info[i].start[j] = - flashbase + 0; - } - - /* 2nd and 3rd are both 8 KB */ - if ((j == 1) || (j == 2)) { - flash_info[i].start[j] = - flashbase + 0x4000 + (j - - 1) * - 0x2000; - } - - /* 4th 32 KB */ - if (j == 3) { - flash_info[i].start[j] = - flashbase + 0x8000; - } - } else { - flash_info[i].start[j] = - flashbase + (j - 3) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - puts ("AMD: "); - break; - default: - puts ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV400B & FLASH_TYPEMASK): - puts ("1x Amd29LV400BB (4Mbit)\n"); - break; - case (AMD_ID_LV800B & FLASH_TYPEMASK): - puts ("1x Amd29LV800BB (8Mbit)\n"); - break; - default: - puts ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - puts ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - puts ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ushort result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip = TMO; - break; - } - - if (!chip - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip = READY; - - if (!chip - && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip = ERR; - - } while (!chip); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - puts ("ok.\n"); - } else { /* it was protected */ - - puts ("protected!\n"); - } - } - - if (ctrlc ()) - puts ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -volatile static int write_hword (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - int cflag, iflag; - int chip; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - chip = ERR | TMO; - break; - } - if (!chip && ((result & 0x80) == (data & 0x80))) - chip = READY; - - if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip = READY; - else - chip = ERR; - } - - } while (!chip); - - *addr = CMD_READ_ARRAY; - - if (chip == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_hword (info, wp, data); -} diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S deleted file mode 100644 index a023353..0000000 --- a/board/mpl/vcma9/lowlevel_init.S +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* some parameters for the board */ - -#define BWSCON 0x48000000 -#define PLD_BASE 0x2C000000 -#define SDRAM_REG 0x2C000106 - -/* BWSCON */ -#define DW8 (0x0) -#define DW16 (0x1) -#define DW32 (0x2) -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -/* BANKSIZE */ -#define BURST_EN (0x1<<7) - -#define B1_BWSCON (DW16) -#define B2_BWSCON (DW32) -#define B3_BWSCON (DW32) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW8 + UBLB) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x1 /* 1clk */ -/*#define B0_Tcos 0x0 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -/*#define B0_Tacc 0x5 8clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* page mode is not used */ -#define B0_PMC 0x0 /* page mode disabled */ - -/* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x1 /* 1clk */ -/*#define B1_Tcos 0x0 0clk */ -#define B1_Tacc 0x7 /* 14clk */ -/*#define B1_Tacc 0x5 8clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 /* page mode is not used */ -#define B1_PMC 0x0 /* page mode disabled */ - -#define B2_Tacs 0x3 /* 4clk */ -#define B2_Tcos 0x3 /* 4clk */ -#define B2_Tacc 0x7 /* 14clk */ -#define B2_Tcoh 0x3 /* 4clk */ -#define B2_Tah 0x3 /* 4clk */ -#define B2_Tacp 0x0 /* page mode is not used */ -#define B2_PMC 0x0 /* page mode disabled */ - -#define B3_Tacs 0x3 /* 4clk */ -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 /* 14clk */ -#define B3_Tcoh 0x3 /* 4clk */ -#define B3_Tah 0x3 /* 4clk */ -#define B3_Tacp 0x0 /* page mode is not used */ -#define B3_PMC 0x0 /* page mode disabled */ - -#define B4_Tacs 0x3 /* 4clk */ -#define B4_Tcos 0x1 /* 1clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x1 /* 1clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 /* page mode is not used */ -#define B4_PMC 0x0 /* page mode disabled */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x3 /* 4clk */ -#define B5_Tacc 0x5 /* 8clk */ -#define B5_Tcoh 0x2 /* 2clk */ -#define B5_Tah 0x1 /* 1clk */ -#define B5_Tacp 0x0 /* page mode is not used */ -#define B5_PMC 0x0 /* page mode disabled */ - -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ -#define B6_SCAN 0x2 /* 10bit */ - -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ -#define B7_SCAN 0x2 /* 10bit */ - -/* REFRESH parameter */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ -/**************************************/ - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevel_init -lowlevel_init: - /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =CSDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #CSDATA_END-CSDATA -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* PLD access is now possible */ - /* r0 == SDRAMDATA */ - /* r1 == SDRAM controller regs */ - ldr r2, =PLD_BASE - ldrb r3, [r2, #SDRAM_REG-PLD_BASE] - mov r4, #SDRAMDATA1_END-SDRAMDATA - /* calculate start and end point */ - mla r0, r3, r4, r0 - add r2, r0, r4 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ - -CSDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) -CSDATA_END: - -SDRAMDATA: -/* 4Mx8x4 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 -SDRAMDATA1_END: - -/* 8Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 2Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 4Mx8x2 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 diff --git a/board/mpl/vcma9/u-boot.lds b/board/mpl/vcma9/u-boot.lds deleted file mode 100644 index f4fbf96..0000000 --- a/board/mpl/vcma9/u-boot.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c deleted file mode 100644 index ffdba5d..0000000 --- a/board/mpl/vcma9/vcma9.c +++ /dev/null @@ -1,353 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "vcma9.h" -#include "../common/common_util.h" - -/* ------------------------------------------------------------------------- */ - -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; - - /* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - - /* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x002AAAAA; - gpio->GPBUP = 0x000002BF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x000037F7; - gpio->GPFCON = 0x00000000; - gpio->GPFUP = 0x00000000; - gpio->GPGCON = 0xFFEAFF5A; - gpio->GPGUP = 0x0000F0DC; - gpio->GPHCON = 0x0028AAAA; - gpio->GPHUP = 0x00000656; - - /* setup correct IRQ modes for NIC */ - gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */ - - /* select USB port 2 to be host or device (fix to host for now) */ - gpio->MISCCR |= 0x08; - - /* init serial */ - gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; - serial_init(); - - /* arch number of VCMA9-Board */ - gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x30000100; - - icache_enable(); - dcache_enable(); - - return 0; -} - -/* - * NAND flash initialization. - */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - - -static inline void NF_Reset(void) -{ - int i; - - NF_SetCE(NFCE_LOW); - NF_Cmd(0xFF); /* reset command */ - for(i = 0; i < 10; i++); /* tWB = 100ns. */ - NF_WaitRB(); /* wait 200~500us; */ - NF_SetCE(NFCE_HIGH); -} - - -static inline void NF_Init(void) -{ -#if 0 /* a little bit too optimistic */ -#define TACLS 0 -#define TWRPH0 3 -#define TWRPH1 0 -#else -#define TACLS 0 -#define TWRPH0 4 -#define TWRPH1 2 -#endif - - NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); - /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ - /* 1 1 1 1, 1 xxx, r xxx, r xxx */ - /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ - - NF_Reset(); -} - -void -nand_init(void) -{ - S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); - - NF_Init(); -#ifdef DEBUG - printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); -#endif - printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); -} -#endif - -/* - * Get some Board/PLD Info - */ - -static u8 Get_PLD_ID(void) -{ - VCMA9_PLD * const pld = VCMA9_GetBase_PLD(); - - return(pld->ID); -} - -static u8 Get_PLD_BOARD(void) -{ - VCMA9_PLD * const pld = VCMA9_GetBase_PLD(); - - return(pld->BOARD); -} - -static u8 Get_PLD_SDRAM(void) -{ - VCMA9_PLD * const pld = VCMA9_GetBase_PLD(); - - return(pld->SDRAM); -} - -static u8 Get_PLD_Version(void) -{ - return((Get_PLD_ID() >> 4) & 0x0F); -} - -static u8 Get_PLD_Revision(void) -{ - return(Get_PLD_ID() & 0x0F); -} - -#if 0 /* not used */ -static int Get_Board_Config(void) -{ - u8 config = Get_PLD_BOARD() & 0x03; - - if (config == 3) - return 1; - else - return 0; -} -#endif - -static uchar Get_Board_PCB(void) -{ - return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A'); -} - -static u8 Get_SDRAM_ChipNr(void) -{ - switch ((Get_PLD_SDRAM() >> 4) & 0x0F) { - case 0: return 4; - case 1: return 1; - case 2: return 2; - default: return 0; - } -} - -static ulong Get_SDRAM_ChipSize(void) -{ - switch (Get_PLD_SDRAM() & 0x0F) { - case 0: return 16 * (1024*1024); - case 1: return 32 * (1024*1024); - case 2: return 8 * (1024*1024); - case 3: return 8 * (1024*1024); - default: return 0; - } -} -static const char * Get_SDRAM_ChipGeom(void) -{ - switch (Get_PLD_SDRAM() & 0x0F) { - case 0: return "4Mx8x4"; - case 1: return "8Mx8x4"; - case 2: return "2Mx8x4"; - case 3: return "4Mx8x2"; - default: return "unknown"; - } -} - -static void Show_VCMA9_Info(char *board_name, char *serial) -{ - printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", - board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision()); - printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom()); -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr(); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ - unsigned char s[50]; - int i; - backup_t *b = (backup_t *) s; - - i = getenv_r("serial#", s, 32); - if ((i < 0) || strncmp (s, "VCMA9", 5)) { - get_backup_values (b); - if (strncmp (b->signature, "MPL\0", 4) != 0) { - puts ("### No HW ID - assuming VCMA9"); - } else { - b->serial_name[5] = 0; - Show_VCMA9_Info(b->serial_name, &b->serial_name[6]); - } - } else { - s[5] = 0; - Show_VCMA9_Info(s, &s[6]); - } - /*printf("\n");*/ - return(0); -} - - -extern void mem_test_reloc(void); - -int last_stage_init(void) -{ - mem_test_reloc(); - checkboard(); - show_stdio_dev(); - check_env(); - return 0; -} - -/*************************************************************************** - * some helping routines - */ -#if !CONFIG_USB_KEYBOARD -int overwrite_console(void) -{ - /* return TRUE if console should be overwritten */ - return 0; -} -#endif - -/************************************************************************ -* Print VCMA9 Info -************************************************************************/ -void print_vcma9_info(void) -{ - unsigned char s[50]; - int i; - - if ((i = getenv_r("serial#", s, 32)) < 0) { - puts ("### No HW ID - assuming VCMA9"); - printf("i %d", i*24); - } else { - s[5] = 0; - Show_VCMA9_Info(s, &s[6]); - } -} diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h deleted file mode 100644 index c0167d5..0000000 --- a/board/mpl/vcma9/vcma9.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2002, 2003 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - /**************************************************************************** - * Global routines used for VCMA9 - *****************************************************************************/ - -#include - -extern int mem_test(unsigned long start, unsigned long ramsize,int mode); - -void print_vcma9_info(void); - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -typedef enum { - NFCE_LOW, - NFCE_HIGH -} NFCE_STATE; - -static inline void NF_Conf(u16 conf) -{ - S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); - - nand->NFCONF = conf; -} - -static inline void NF_Cmd(u8 cmd) -{ - S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); - - nand->NFCMD = cmd; -} - -static inline void NF_CmdW(u8 cmd) -{ - NF_Cmd(cmd); - udelay(1); -} - -static inline void NF_Addr(u8 addr) -{ - S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); - - nand->NFADDR = addr; -} - -static inline void NF_SetCE(NFCE_STATE s) -{ - S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); - - switch (s) { - case NFCE_LOW: - nand->NFCONF &= ~(1<<11); - break; - - case NFCE_HIGH: - nand->NFCONF |= (1<<11); - break; - } -} - -static inline void NF_WaitRB(void) -{ - S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); - - while (!(nand->NFSTAT & (1<<0))); -} - -static inline void NF_Write(u8 data) -{ - S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); - - nand->NFDATA = data; -} - -static inline u8 NF_Read(void) -{ - S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); - - return(nand->NFDATA); -} - -static inline void NF_Init_ECC(void) -{ - S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); - - nand->NFCONF |= (1<<12); -} - -static inline u32 NF_Read_ECC(void) -{ - S3C2410_NAND * const nand = S3C2410_GetBase_NAND(); - - return(nand->NFECC); -} - -#endif - -/* VCMA9 PLD regsiters */ -typedef struct { - S3C24X0_REG8 ID; - S3C24X0_REG8 NIC; - S3C24X0_REG8 CAN; - S3C24X0_REG8 MISC; - S3C24X0_REG8 GPCD; - S3C24X0_REG8 BOARD; - S3C24X0_REG8 SDRAM; -} /*__attribute__((__packed__))*/ VCMA9_PLD; - -#define VCMA9_PLD_BASE 0x2C000100 -static inline VCMA9_PLD * const VCMA9_GetBase_PLD(void) -{ - return (VCMA9_PLD * const)VCMA9_PLD_BASE; -} diff --git a/board/musenki/Makefile b/board/musenki/Makefile deleted file mode 100644 index 24dc026..0000000 --- a/board/musenki/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o -SOBJS = - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/musenki/README b/board/musenki/README deleted file mode 100644 index 135a01a..0000000 --- a/board/musenki/README +++ /dev/null @@ -1,298 +0,0 @@ -U-Boot for a Musenki M-3/M-1 board ---------------------------- - -Musenki M-1 and M-3 have two banks of flash of 4MB or 8MB each. - -In board's notation, bank 0 is the one at the address of 0xFF800000 -and bank 1 is the one at the address of 0xFF000000. - -On power-up the processor jumps to the address of 0xFFF00100, the last -megabyte of the bank 0 of flash. - -Thus, U-Boot is configured to reside in flash starting at the address of -0xFFF00000. The environment space is located in flash separately from -U-Boot, at the address of 0xFF800000. - -There is a Davicom 9102A on-board, but I don't have it working yet. - -U-Boot test results --------------------- - -x.x Operation on all available serial consoles - -x.x.x CONFIG_CONS_INDEX 1 - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> help -autoscr - run script from memory -base - print or set address offset -bdinfo - print Board Info structure -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -cmp - memory compare -coninfo - print console devices and informations -cp - memory copy -crc32 - checksum calculation -dcache - enable or disable data cache -echo - echo args to console -erase - erase FLASH memory -flinfo - print FLASH memory information -go - start application at address 'addr' -help - print online help -icache - enable or disable instruction cache -iminfo - print header information for application image -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loop - infinite loop on address range -md - memory display -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nm - memory modify (constant address) -printenv- print environment variables -protect - enable or disable FLASH write protection -rarpboot- boot image via network using RARP/TFTP protocol -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -version - print monitor version -? - alias for 'help' - - -x.x.x CONFIG_CONS_INDEX 2 - -**** NOT TESTED **** - -x.x Flash Driver Operation - - -Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> -=> md ff800000 -ff800000: 46989bf8 626f6f74 636d643d 626f6f74 F...bootcmd=boot -ff800010: 6d204646 38323030 30300062 6f6f7464 m FF820000.bootd -ff800020: 656c6179 3d350062 61756472 6174653d elay=5.baudrate= -ff800030: 39363030 00636c6f 636b735f 696e5f6d 9600.clocks_in_m -ff800040: 687a3d31 00737464 696e3d73 65726961 hz=1.stdin=seria -ff800050: 6c007374 646f7574 3d736572 69616c00 l.stdout=serial. -ff800060: 73746465 72723d73 65726961 6c006970 stderr=serial.ip -ff800070: 61646472 3d313932 2e313638 2e302e34 addr=192.168.0.4 -ff800080: 32007365 72766572 69703d31 39322e31 2.serverip=192.1 -ff800090: 36382e30 2e380000 00000000 00000000 68.0.8.......... -ff8000a0: 00000000 00000000 00000000 00000000 ................ -ff8000b0: 00000000 00000000 00000000 00000000 ................ -ff8000c0: 00000000 00000000 00000000 00000000 ................ -ff8000d0: 00000000 00000000 00000000 00000000 ................ -ff8000e0: 00000000 00000000 00000000 00000000 ................ -ff8000f0: 00000000 00000000 00000000 00000000 ................ -=> protect off ff800000 ff81ffff -Un-Protected 1 sectors -=> erase ff800000 ff81ffff -Erase Flash from 0xff800000 to 0xff81ffff - done -Erased 1 sectors -=> md ff800000 -ff800000: ffffffff ffffffff ffffffff ffffffff ................ -ff800010: ffffffff ffffffff ffffffff ffffffff ................ -ff800020: ffffffff ffffffff ffffffff ffffffff ................ -ff800030: ffffffff ffffffff ffffffff ffffffff ................ -ff800040: ffffffff ffffffff ffffffff ffffffff ................ -ff800050: ffffffff ffffffff ffffffff ffffffff ................ -ff800060: ffffffff ffffffff ffffffff ffffffff ................ -ff800070: ffffffff ffffffff ffffffff ffffffff ................ -ff800080: ffffffff ffffffff ffffffff ffffffff ................ -ff800090: ffffffff ffffffff ffffffff ffffffff ................ -ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ - -x.x.x Information - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> flinfo - -Bank # 1: Intel 28F320J3A (32Mbit = 128K x 32) - Size: 4 MB in 32 Sectors - Sector Start Addresses: - FF800000 (RO) FF820000 FF840000 FF860000 FF880000 - FF8A0000 FF8C0000 FF8E0000 FF900000 FF920000 - FF940000 FF960000 FF980000 FF9A0000 FF9C0000 - FF9E0000 FFA00000 FFA20000 FFA40000 FFA60000 - FFA80000 FFAA0000 FFAC0000 FFAE0000 FFB00000 - FFB20000 FFB40000 FFB60000 FFB80000 FFBA0000 - FFBC0000 FFBE0000 - -Bank # 2: missing or unknown FLASH type -=> - - -x.x.x Flash Programming - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB - -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> -=> -=> -=> protect off ff800000 ff81ffff -Un-Protected 1 sectors -=> cp 0 ff800000 20 -Copy to Flash... done -=> md ff800000 -ff800000: 37ce33ec 33cc334c 33c031cc 33cc35cc 7.3.3.3L3.1.3.5. -ff800010: 33ec13ce 30ccb3ec b3c833c4 31c836cc 3...0.....3.1.6. -ff800020: 33cc3b9d 31ec33ee 13ecf3cc 338833ec 3.;.1.3.....3.3. -ff800030: 234c33ec 32cc22cc 33883bdc 534433cc #L3.2.".3.;.SD3. -ff800040: 33cc30c8 31cc32ec 338c33cc 330c33dc 3.0.1.2.3.3.3.3. -ff800050: 33cc13dc 334c534c b1c433d8 128c13cc 3...3LSL..3..... -ff800060: 37ec36cd 33dc33cc bbc9f7e8 bbcc77cc 7.6.3.3.......w. -ff800070: 314c0adc 139c30ed 33cc334c 33c833ec 1L....0.3.3L3.3. -ff800080: ffffffff ffffffff ffffffff ffffffff ................ -ff800090: ffffffff ffffffff ffffffff ffffffff ................ -ff8000a0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000b0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000c0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000d0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000e0: ffffffff ffffffff ffffffff ffffffff ................ -ff8000f0: ffffffff ffffffff ffffffff ffffffff ................ - - -x.x.x Storage of environment variables in flash - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> printenv -bootcmd=bootm FF820000 -bootdelay=5 -baudrate=9600 -clocks_in_mhz=1 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 106/16380 bytes -=> setenv myvar 1234 -=> saveenv -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Saving Environment to Flash... -Protected 1 sectors -=> reset - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> printenv -bootcmd=bootm FF820000 -bootdelay=5 -baudrate=9600 -clocks_in_mhz=1 -myvar=1234 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 117/16380 bytes - -x.x Image Download and run over serial port - - -U-Boot 1.1.1 (Nov 20 2001 - 15:55:32) - -CPU: MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MUSENKI Local Bus at 100 MHz -DRAM: 32 MB -FLASH: 4 MB -In: serial -Out: serial -Err: serial -Hit any key to stop autoboot: 0 -=> loads -## Ready for S-Record download ... - -## First Load Addr = 0x00040000 -## Last Load Addr = 0x00050177 -## Total Size = 0x00010178 = 65912 Bytes -## Start Addr = 0x00040004 -=> go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "" -Hit any key to exit ... - -## Application terminated, rc = 0x0 - - -x.x Image download and run over ethernet interface - -untested (not working yet, actually) diff --git a/board/musenki/config.mk b/board/musenki/config.mk deleted file mode 100644 index 18673e1..0000000 --- a/board/musenki/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# CU824 board -# - -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/musenki/flash.c b/board/musenki/flash.c deleted file mode 100644 index cd33d8e..0000000 --- a/board/musenki/flash.c +++ /dev/null @@ -1,512 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_data (flash_info_t *info, uchar *dest, uchar data); -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/* - * don't ask. its stupid, but more than one soul has had to live with this mistake - * "swaptab[i]" is the value of "i" with the bits reversed. - */ - -#define MUSENKI_BROKEN_FLASH 1 - -#ifdef MUSENKI_BROKEN_FLASH -unsigned char swaptab[256] = { - 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, - 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, - 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, - 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, - 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, - 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, - 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, - 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, - 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, - 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, - 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, - 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, - 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, - 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, - 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, - 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, - 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, - 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, - 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, - 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, - 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, - 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, - 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, - 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, - 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, - 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, - 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, - 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, - 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, - 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, - 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, - 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff, -}; - -#define BS(b) (swaptab[b]) - -#else - -#define BS(b) (b) - -#endif - -#define BYTEME(x) ((x) & 0xFF) - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE - DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, monitor_flash_len); - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - DEBUGF("protect environtment %x @ %x\n", CFG_ENV_ADDR, CFG_ENV_SECT_SIZE); - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - flash_info[1].size = size_b1; - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - } - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x00020000; /* 128k per bank */ - } - return; - - default: - printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id); - return; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: printf ("28F320J3A (32Mbit = 128K x 32)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64Mbit = 128K x 64)\n"); - break; - case FLASH_28F128J3A: printf ("28F128J3A (128Mbit = 128K x 128)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ - vu_char manuf, device; - - addr[0] = BS(0x90); - manuf = BS(addr[0]); - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (vu_char *)addr, manuf); - - switch (manuf) { - case BYTEME(AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - case BYTEME(FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - case BYTEME(SST_MANUFACT): - info->flash_id = FLASH_MAN_SST; - break; - case BYTEME(STM_MANUFACT): - info->flash_id = FLASH_MAN_STM; - break; - case BYTEME(INTEL_MANUFACT): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = BS(0xFF); /* restore read mode, (yes, BS is a NOP) */ - return 0; /* no or unknown flash */ - } - - device = BS(addr[2]); /* device ID */ - - DEBUGF("Device ID @ 0x%08x: 0x%08x\n", (&addr[1]), device); - - switch (device) { - case BYTEME(INTEL_ID_28F320J3A): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case BYTEME(INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case BYTEME(INTEL_ID_28F128J3A): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = BS(0xFF); /* restore read mode (yes, a NOP) */ - return 0; /* => no or unknown flash */ - - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = BS(0xFF); /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_char *addr = (vu_char *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x50); /* clear status register */ - *addr = BS(0x20); /* erase setup */ - *addr = BS(0xD0); /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = BS(0xB0); /* suspend erase */ - *addr = BS(0xFF); /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = BS(0xFF); /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 1 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - uchar *wp = (uchar *)addr; - int rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - while (cnt > 0) { - if ((rc = write_data(info, wp, *src)) != 0) { - return rc; - } - wp++; - src++; - cnt--; - } - - return cnt; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, uchar *dest, uchar data) -{ - vu_char *addr = (vu_char *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((BS(*addr) & data) != data) { - return 2; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = BS(0x40); /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - start = get_timer (0); - - while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *addr = BS(0xFF); /* restore read mode */ - return 1; - } - } - - *addr = BS(0xFF); /* restore read mode */ - - return 0; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c deleted file mode 100644 index 88ef83a..0000000 --- a/board/musenki/musenki.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -int checkboard (void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - printf("Board: MUSENKI Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; - -} - -#if 0 /* NOT USED */ -int checkflash (void) -{ - /* TODO: XXX XXX XXX */ - printf ("## Test not implemented yet ##\n"); - - return (0); -} -#endif - -long int initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { -#if 0 - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - 0x0, 0x0, 0x0, /* unknown eth0 divice */ - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - 0x0, 0x0, 0x0, /* unknown eth1 device */ - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER }}, -#endif - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} diff --git a/board/musenki/u-boot.lds b/board/musenki/u-boot.lds deleted file mode 100644 index 7c05109..0000000 --- a/board/musenki/u-boot.lds +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mv_feroceon/USP/ethSwitch/mvSwitch.c b/board/mv_feroceon/USP/ethSwitch/mvSwitch.c new file mode 100644 index 0000000..7ceb021 --- /dev/null +++ b/board/mv_feroceon/USP/ethSwitch/mvSwitch.c @@ -0,0 +1,447 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "mvSwitch.h" +#include "eth-phy/mvEthPhy.h" +#include "mvSwitchRegs.h" +#include "mvCtrlEnvLib.h" + + +static void switchVlanInit(MV_U32 ethPortNum, + MV_U32 switchCpuPort, + MV_U32 switchMaxPortsNum, + MV_U32 switchPortsOffset, + MV_U32 switchEnabledPortsMask); + + + +/******************************************************************************* +* mvEthE6065_61PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE6065_61SwitchBasicInit(MV_U32 ethPortNum) +{ + switchVlanInit(ethPortNum, + MV_E6065_CPU_PORT, + MV_E6065_MAX_PORTS_NUM, + MV_E6065_PORTS_OFFSET, + MV_E6065_ENABLED_PORTS); +} + +/******************************************************************************* +* mvEthE6063PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE6063SwitchBasicInit(MV_U32 ethPortNum) +{ + switchVlanInit(ethPortNum, + MV_E6063_CPU_PORT, + MV_E6063_MAX_PORTS_NUM, + MV_E6063_PORTS_OFFSET, + MV_E6063_ENABLED_PORTS); +} + +/******************************************************************************* +* mvEthE6131PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE6131SwitchBasicInit(MV_U32 ethPortNum) +{ + + MV_U16 reg; + + /*Enable Phy power up*/ + mvEthPhyRegWrite (0,0,0x9140); + mvEthPhyRegWrite (1,0,0x9140); + mvEthPhyRegWrite (2,0,0x9140); + + + /*Enable PPU*/ + mvEthPhyRegWrite (0x1b,4,0x4080); + + + /*Enable Phy detection*/ + mvEthPhyRegRead (0x13,0,®); + reg &= ~(1<<12); + mvEthPhyRegWrite (0x13,0,reg); + + mvOsDelay(100); + mvEthPhyRegWrite (0x13,1,0x33); + + + switchVlanInit(ethPortNum, + MV_E6131_CPU_PORT, + MV_E6131_MAX_PORTS_NUM, + MV_E6131_PORTS_OFFSET, + MV_E6131_ENABLED_PORTS); + +} + + +/******************************************************************************* +* mvEthE6161PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE6161SwitchBasicInit(MV_U32 ethPortNum) +{ + + MV_U32 prt; + MV_U16 reg; + volatile MV_U32 timeout; + + /* The 6161/5 needs a delay */ + mvOsDelay(1000); + + /* Init vlan */ + switchVlanInit(ethPortNum, + MV_E6161_CPU_PORT, + MV_E6161_MAX_PORTS_NUM, + MV_E6161_PORTS_OFFSET, + MV_E6161_ENABLED_PORTS); + + /* Enable RGMII delay on Tx and Rx for CPU port */ + mvEthSwitchRegWrite (ethPortNum, 0x14,0x1a,0x81e7); + mvEthSwitchRegRead (ethPortNum, 0x15,0x1a,®); + mvEthSwitchRegWrite (ethPortNum, 0x15,0x1a, reg | 0x18); + mvEthSwitchRegWrite (ethPortNum, 0x14,0x1a,0xc1e7); + + + for(prt=0; prt < MV_E6161_MAX_PORTS_NUM - 1; prt++) + { + if (prt != MV_E6161_CPU_PORT) + { + /*Enable Phy power up*/ + mvEthSwitchRegWrite (ethPortNum, MV_E6161_GLOBAL_2_REG_DEV_ADDR, + MV_E6161_SMI_PHY_DATA, 0x3360); + mvEthSwitchRegWrite (ethPortNum, MV_E6161_GLOBAL_2_REG_DEV_ADDR, + MV_E6161_SMI_PHY_COMMAND, (0x9410 | (prt << 5))); + + /*Make sure SMIBusy bit cleared before another SMI operation can take place*/ + timeout = E6161_PHY_TIMEOUT; + do + { + mvEthSwitchRegRead(ethPortNum, MV_E6161_GLOBAL_2_REG_DEV_ADDR, + MV_E6161_SMI_PHY_COMMAND,®); + if(timeout-- == 0) + { + mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n"); + return; + } + }while (reg & E6161_PHY_SMI_BUSY_MASK); + + mvEthSwitchRegWrite (ethPortNum, MV_E6161_GLOBAL_2_REG_DEV_ADDR, + MV_E6161_SMI_PHY_DATA,0x1140); + mvEthSwitchRegWrite (ethPortNum, MV_E6161_GLOBAL_2_REG_DEV_ADDR, + MV_E6161_SMI_PHY_COMMAND,(0x9400 | (prt << 5))); + + /*Make sure SMIBusy bit cleared before another SMI operation can take place*/ + timeout = E6161_PHY_TIMEOUT; + do + { + mvEthSwitchRegRead(ethPortNum, MV_E6161_GLOBAL_2_REG_DEV_ADDR, + MV_E6161_SMI_PHY_COMMAND,®); + if(timeout-- == 0) + { + mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n"); + return; + } + }while (reg & E6161_PHY_SMI_BUSY_MASK); + + } + + /*Enable port*/ + mvEthSwitchRegWrite (ethPortNum, MV_E6161_PORTS_OFFSET + prt, 4, 0x7f); + + /*Change MDI port polarity to fix board erratum of reverse connector*/ +#define MDI_POLARITY_FIX +#if defined(MDI_POLARITY_FIX) && defined(RD_88F6281A) + if(mvBoardIdGet() == RD_88F6281A_ID) + { + /*Make sure SMIBusy bit cleared before another SMI operation can take place*/ + timeout = E6161_PHY_TIMEOUT; + do + { + mvEthSwitchRegRead(ethPortNum, MV_E6161_GLOBAL_2_REG_DEV_ADDR, + MV_E6161_SMI_PHY_COMMAND,®); + if(timeout-- == 0) + { + mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n"); + return; + } + }while (reg & E6161_PHY_SMI_BUSY_MASK); + mvEthSwitchRegWrite (ethPortNum, MV_E6161_GLOBAL_2_REG_DEV_ADDR, + MV_E6161_SMI_PHY_DATA, 0xf); + mvEthSwitchRegWrite (ethPortNum, MV_E6161_GLOBAL_2_REG_DEV_ADDR, + MV_E6161_SMI_PHY_COMMAND, (0x9414 + (prt*0x20))); + mvEthSwitchRegRead (ethPortNum, MV_E6161_GLOBAL_2_REG_DEV_ADDR, + MV_E6161_SMI_PHY_DATA, ®);/* used for delay */ + } +#endif /*MDI_POLARITY_FIX*/ + } + + /*Force CPU port to RGMII FDX 1000Base*/ + mvEthSwitchRegWrite (ethPortNum, MV_E6161_PORTS_OFFSET + MV_E6161_CPU_PORT, 1, 0x3e); + +} + +static void switchVlanInit(MV_U32 ethPortNum, + MV_U32 switchCpuPort, + MV_U32 switchMaxPortsNum, + MV_U32 switchPortsOffset, + MV_U32 switchEnabledPortsMask) +{ + MV_U32 prt; + MV_U16 reg; + + /* be sure all ports are disabled */ + for(prt=0; prt < switchMaxPortsNum; prt++) + { + mvEthSwitchRegRead (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_CONTROL_REG,®); + reg &= ~0x3; + mvEthSwitchRegWrite (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_CONTROL_REG,reg); + + } + + /* Set CPU port VID to 0x1 */ + mvEthSwitchRegRead (ethPortNum, MV_SWITCH_PORT_OFFSET(switchCpuPort), + MV_SWITCH_PORT_VID_REG,®); + reg &= ~0xfff; + reg |= 0x1; + mvEthSwitchRegWrite (ethPortNum, MV_SWITCH_PORT_OFFSET(switchCpuPort), + MV_SWITCH_PORT_VID_REG,reg); + + + /* Setting Port default priority for all ports to zero */ + for(prt=0; prt < switchMaxPortsNum; prt++) + { + + mvEthSwitchRegRead (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_VID_REG,®); + reg &= ~0xc000; + mvEthSwitchRegWrite (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_VID_REG,reg); + } + + /* Setting VID and VID map for all ports except CPU port */ + for(prt=0; prt < switchMaxPortsNum; prt++) + { + + /* only for enabled ports */ + if ((1 << prt)& switchEnabledPortsMask) + { + /* skip CPU port */ + if (prt== switchCpuPort) continue; + + /* + * set Ports VLAN Mapping. + * port prt <--> MV_SWITCH_CPU_PORT VLAN #prt+1. + */ + + mvEthSwitchRegRead (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_VID_REG,®); + reg &= ~0x0fff; + reg |= (prt+1); + mvEthSwitchRegWrite (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_VID_REG,reg); + + + /* Set Vlan map table for all ports to send only to MV_SWITCH_CPU_PORT */ + mvEthSwitchRegRead (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_VMAP_REG,®); + reg &= ~((1 << switchMaxPortsNum) - 1); + reg |= (1 << switchCpuPort); + mvEthSwitchRegWrite (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_VMAP_REG,reg); + } + + } + + + /* Set Vlan map table for MV_SWITCH_CPU_PORT to see all ports*/ + mvEthSwitchRegRead (ethPortNum, MV_SWITCH_PORT_OFFSET(switchCpuPort), + MV_SWITCH_PORT_VMAP_REG,®); + reg &= ~((1 << switchMaxPortsNum) - 1); + reg |= switchEnabledPortsMask & ~(1 << switchCpuPort); + mvEthSwitchRegWrite (ethPortNum, MV_SWITCH_PORT_OFFSET(switchCpuPort), + MV_SWITCH_PORT_VMAP_REG,reg); + + + /*enable only appropriate ports to forwarding mode - and disable the others*/ + for(prt=0; prt < switchMaxPortsNum; prt++) + { + + if ((1 << prt)& switchEnabledPortsMask) + { + mvEthSwitchRegRead (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_CONTROL_REG,®); + reg |= 0x3; + mvEthSwitchRegWrite (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_CONTROL_REG,reg); + + } + else + { + /* Disable port */ + mvEthSwitchRegRead (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_CONTROL_REG,®); + reg &= ~0x3; + mvEthSwitchRegWrite (ethPortNum, MV_SWITCH_PORT_OFFSET(prt), + MV_SWITCH_PORT_CONTROL_REG,reg); + } + } + return; +} + +void mvEthSwitchRegWrite(MV_U32 ethPortNum, MV_U32 phyAddr, + MV_U32 regOffs, MV_U16 data) +{ + MV_U16 reg; + MV_U32 switchMultiChipMode; + + if(mvBoardSmiScanModeGet(ethPortNum) == 0x2) + { + switchMultiChipMode = mvBoardPhyAddrGet(ethPortNum); + do + { + mvEthPhyRegRead(switchMultiChipMode, 0x0, ®); + } while((reg & BIT15)); // Poll till SMIBusy bit is clear + mvEthPhyRegWrite(switchMultiChipMode, 0x1, data); // Write data to Switch indirect data register + mvEthPhyRegWrite(switchMultiChipMode, 0x0, (MV_U16)(regOffs | (phyAddr << 5) | + BIT10 | BIT12 | BIT15)); // Write command to Switch indirect command register + } + else + mvEthPhyRegWrite(phyAddr, regOffs, data); +} + +void mvEthSwitchRegRead(MV_U32 ethPortNum, MV_U32 phyAddr, + MV_U32 regOffs, MV_U16 *data) +{ + MV_U16 reg; + MV_U32 switchMultiChipMode; + + if(mvBoardSmiScanModeGet(ethPortNum) == 0x2) + { + switchMultiChipMode = mvBoardPhyAddrGet(ethPortNum); + do + { + mvEthPhyRegRead(switchMultiChipMode, 0x0, ®); + } while((reg & BIT15)); // Poll till SMIBusy bit is clear + mvEthPhyRegWrite(switchMultiChipMode, 0x0, (MV_U16)(regOffs | (phyAddr << 5) | + BIT11 | BIT12 | BIT15)); // Write command to Switch indirect command register + do + { + mvEthPhyRegRead(switchMultiChipMode, 0, ®); + } while((reg & BIT15)); // Poll till SMIBusy bit is clear + mvEthPhyRegRead(switchMultiChipMode, 0x1, data); // read data from Switch indirect data register + } + else + mvEthPhyRegRead(phyAddr, regOffs, data); +} diff --git a/board/mv_feroceon/USP/ethSwitch/mvSwitch.h b/board/mv_feroceon/USP/ethSwitch/mvSwitch.h new file mode 100644 index 0000000..ea2da25 --- /dev/null +++ b/board/mv_feroceon/USP/ethSwitch/mvSwitch.h @@ -0,0 +1,75 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCETHSWITCHH +#define __INCETHSWITCHH + +#include "mvTypes.h" + +MV_VOID mvEthE6063SwitchBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE6065_61SwitchBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE6131SwitchBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE6161SwitchBasicInit(MV_U32 ethPortNum); + +#endif /* #ifndef __INCETHSWITCHH */ diff --git a/board/mv_feroceon/USP/ethSwitch/mvSwitchRegs.h b/board/mv_feroceon/USP/ethSwitch/mvSwitchRegs.h new file mode 100644 index 0000000..dd8370e --- /dev/null +++ b/board/mv_feroceon/USP/ethSwitch/mvSwitchRegs.h @@ -0,0 +1,109 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCethswitchregsh +#define __INCethswitchregsh + +#define MV_SWITCH_PORT_CONTROL_REG 0x4 +#define MV_SWITCH_PORT_VMAP_REG 0x6 +#define MV_SWITCH_PORT_VID_REG 0x7 + + +#define MV_SWITCH_PORT_OFFSET(port) (switchPortsOffset+port) + +/* E6063 related */ +#define MV_E6063_CPU_PORT 5 +#define MV_E6063_PORTS_OFFSET 0x8 +#define MV_E6063_MAX_PORTS_NUM 7 +#define MV_E6063_ENABLED_PORTS ((1 << 0)|(1 << 1)|(1 << 2)| \ + (1 << 3)|(1 << 4)|(1 << 5)) + +/* E6065 related */ +#define MV_E6065_CPU_PORT 5 +#define MV_E6065_PORTS_OFFSET 0x8 +#define MV_E6065_MAX_PORTS_NUM 6 +#define MV_E6065_ENABLED_PORTS ((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4)|(1 << 5)) + +/* E6063 related */ +#define MV_E6131_CPU_PORT 0x3 +#define MV_E6131_PORTS_OFFSET 0x10 +#define MV_E6131_MAX_PORTS_NUM 8 +#define MV_E6131_ENABLED_PORTS ((1 << 0)|(1 << 1)|(1 << 2)| \ + (1 << 3)|(1 << 5)|(1 << 7)) +/* E6161 related */ +#define MV_E6161_CPU_PORT 0x5 +#define MV_E6161_PORTS_OFFSET 0x10 +#define MV_E6161_SMI_PHY_COMMAND 0x18 +#define MV_E6161_SMI_PHY_DATA 0x19 +#define MV_E6161_GLOBAL_2_REG_DEV_ADDR 0x1C +#define MV_E6161_MAX_PORTS_NUM 6 +#define MV_E6161_ENABLED_PORTS ((1 << 0)|(1 << 1)|(1 << 2)|(1 << 3)|(1 << 4)|(1 << 5)) +#define E6161_PHY_TIMEOUT 10000 +#define E6161_PHY_SMI_BUSY_BIT 15 /* Busy */ +#define E6161_PHY_SMI_BUSY_MASK (1 << ETH_PHY_SMI_BUSY_BIT) + + + + +#endif /* __INCethswitchregsh */ diff --git a/board/mv_feroceon/USP/jump.S b/board/mv_feroceon/USP/jump.S new file mode 100644 index 0000000..3e1e397 --- /dev/null +++ b/board/mv_feroceon/USP/jump.S @@ -0,0 +1,336 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvSysHwConfig.h" +#include "mvBoardEnvSpec.h" +#include "mvOsAsm.h" +#include "pci/mvPciRegs.h" +#include "pex/mvPexRegs.h" +#include "mvCtrlEnvSpec.h" +#include "mvCtrlEnvAsm.h" +#include "sys/mvCpuIfRegs.h" + + +jumpStart: + +.section ".reset_vector_sect",#alloc, #execinstr +#if defined(MV_88F6082) || defined(MV_88F6183) || defined(DB_88F5181_OLD) || defined(DB_FPGA) || \ + defined(MV88F6281) || defined(MV88F6282) || defined(MV88F6192) || defined(MV88F6180) || defined(MV_88F6183L) || \ + defined(MV88F6190) || defined(MV88F6280) +#if defined(__BE) + /* disable I-Cache */ + .word 0x100f11ee /* mrc 15, 0, r0, cr1, cr0, {0} */ + .word 0x010ac0e3 /* bic r0, r0, #4096 ; 0x1000 */ + .word 0x0700c0e3 /* bic r0, r0, #7 ; 0x7 */ + .word 0x020080e3 /* orr r0, r0, #2 ; 0x2 */ + .word 0x100f01ee /* mcr 15, 0, r0, cr1, cr0, {0} */ + /* disable L2 prefetch */ + .word 0x110f3fee /* mrc p15, 1, r0, c15, c1 */ + .word 0x010480e3 /* orr r0, r0, #(1<<24) */ + .word 0x110f2fee /* mcr p15, 1, r0, c15, c1 */ + /* convert CPU to big endian */ + .word 0x100f11ee /* mrc p15, 0, r0, c1, c0 */ + .word 0x800080e3 /* orr r0, r0, #0x80 */ + .word 0x100f01ee /* mcr p15, 0, r0, c1, c0 */ + nop;nop;nop;nop; + nop;nop;nop;nop; + +#endif +#endif + + /* Check if we booted from DRAM. If we did someone already */ + /* initialize the DRAM controller */ + + adr r4, jumpStart /* r4 <- current position of code */ + mov r5, #~0xff + and r4, r4, r5 + +#if defined(MV78XX0) +/* Add for load code into I cache */ + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* Load source code from 0xffff0000-0xffff1000 */ + mov r8, r4 /* U-boot reset vector address on flash */ + mov r2, #0x1000 /* U-boot size of code in reset vector */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00000007 /* 2:0 (CAM) */ + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00001000 /* Enabled I-cache */ + mcr p15, 0, r0, c1, c0, 0 + nop + nop + + /* Load code into I Cache */ +load_loop: + mcr p15, 0, r8, c7, c13, 1 + add r8, r8, #32 /* 8 dwords * 4 bytes */ + sub r2, r2, #32 /* 8 dwords * 4 bytes */ + cmp r2, #0 /* check if we have read a full Page */ + bne load_loop + + /* Load source code from 0xfff80000-0xfff84000 */ + mov r8, #0 + mov r0, #0xff /* U-boot base address on flash */ + orr r8, r8, r0, LSL #24 + mov r0, #0xf8 /* U-boot base address on flash */ + orr r8, r8, r0, LSL #16 + mov r2, #0x4000 /* U-boot size of code in reset vector */ + + /* Load code into I Cache */ +load_loop1: + mcr p15, 0, r8, c7, c13, 1 + add r8, r8, #32 /* 8 dwords * 4 bytes */ + sub r2, r2, #32 /* 8 dwords * 4 bytes */ + cmp r2, #0 /* check if we have read a full Page */ + bne load_loop1 + + /* Lock I-cache */ + mrc p15, 0, r0, c9, c0, 1 + orr r0, r0, #0xf + mcr p15, 0, r0, c9, c0, 1 + nop + nop +/* End of code load */ +#endif /* MV78XX0 */ + + ldr r5, __start /* r5 <- linker results for _start */ + ldr r2, _jumpStart /* r2 <- linker results reset vector */ + sub r8, r2, r5 /* r8 <- (reset vector address - start address) */ + sub r8, r4, r8 /* r8 <- absolute address to jump to */ + /* r8 <- (current code address - */ + ldr sp, =0 + ldr lr, =0 + ldr r5, =CFG_RESET_ADDRESS /* test if we run from flash or RAM */ + cmp r4, r5 /* don't reloc during debug */ + beq romBoot + + mov r5, #1 + ldr r4, =dramBoot + str r5, [r4] /* We started executing from DRAM */ +romBoot: + +#if defined(MV78200) + mov r0, #0 + mrc p15, 1, r0, c15, c1, 0 + /* Check if we are CPU0 or CPU1 */ + and r0, r0, #0x4000 + cmp r0, #0x4000 + beq device_cont + +/* Setting the PEX header device ID for 0x78200 due to a problem in engineering sample devices */ +/* There is no need to implement this workaround for production devices */ + MV_DV_REG_READ_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID)) + ldr r1, =MV_78200_DEV_ID + ldr r2, =0xffff + and r6, r6, r2 + orr r6, r6, r1, LSL #PXDAVI_DEV_ID_OFFS + MV_DV_REG_WRITE_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID)) +#endif + +#if defined(MV_88F1181) + + /* set gpp out en */ + ldr r2, = 0xf33 + MV_DV_REG_WRITE_ASM(r1, r1, 0x10104) + + /* turn on debug led to 2 */ + ldr r2, = 0x8 + MV_DV_REG_WRITE_ASM(r1, r1, 0x10100) + + ldr pc, = 0xfff90000 + +#else + +#if defined(DB_FPGA) + b device_cont +#endif /* DB_FPGA */ + +#if !defined(MV78XX0) + /* Read device ID */ + MV_DV_CTRL_MODEL_GET_ASM(r6, r1); + ldr r1, =0x5281 + cmp r6, r1 + beq device_5281 + + /* TC90 acts as Orion 2 C0 */ + ldr r1, =0x1281 + cmp r6, r1 + beq device_5281_C0 + + /* 6183 & 6183L */ + ldr r1, =0x6183 + cmp r6, r1 + bne device_cont +#endif + +#if defined(MV_88F6183L) +/* Setting the PEX header device ID for 6183L */ + MV_DV_REG_READ_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID)) + ldr r1, =MV_6183L_DEV_ID + ldr r2, =0xffff + and r6, r6, r2 + orr r6, r6, r1, LSL #PXDAVI_DEV_ID_OFFS + MV_DV_REG_WRITE_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID)) +#endif /* MV_88F6183L */ + + +#if !defined(MV78XX0) + /* Read device revision */ + MV_DV_CTRL_REV_GET_ASM(r6, r1); + cmp r6, #0x3 /* 6183 == B0 */ + bne device_cont + + MV_DV_REG_READ_ASM (r6, r1, CPU_FTDLL_CONFIG_REG) + ldr r1, =0x10000 + orr r6, r6, r1 + MV_DV_REG_WRITE_ASM (r6, r1, CPU_FTDLL_CONFIG_REG) +#endif + + b device_cont + +device_5281: + + /* Read device revision */ + MV_DV_CTRL_REV_GET_ASM(r6, r1); + cmp r6, #0x0 /* Orion 2 == A0 */ + beq device_5281_A0 + + cmp r6, #0x1 /* Orion 2 == B0 */ + beq device_5281_B0 + + cmp r6, #0x2 /* Orion 2 == C0 */ + beq device_5281_C0 + + cmp r6, #0x4 /* Orion 2 == d0 */ + beq device_5281_D0 + + cmp r6, #0x5 /* Orion 2 == d1 */ + beq device_5281_D1 + + cmp r6, #0x6 /* Orion 2 == d2 */ + beq device_5281_D2 + + b device_cont + +device_5281_D0: +device_5281_D1: +device_5281_D2: +#if !defined(MV78XX0) + MV_DV_REG_READ_ASM (r6, r1, CPU_FTDLL_CONFIG_REG) + + ldr r1, =0xFFFF8080 + and r6, r6, r1 + ldr r1, =0x1902 + orr r6, r6, r1 + + MV_DV_REG_WRITE_ASM (r6, r1, CPU_FTDLL_CONFIG_REG) +#endif + b device_cont + +device_5281_C0: +#if !defined(MV78XX0) + MV_DV_REG_READ_ASM (r6, r1, CPU_FTDLL_CONFIG_REG) + + ldr r1, =0xFFFF8080 + and r6, r6, r1 + ldr r1, =0x8308 + orr r6, r6, r1 + + MV_DV_REG_WRITE_ASM (r6, r1, CPU_FTDLL_CONFIG_REG) +#endif + b device_cont + +device_5281_B0: +#if !defined(MV78XX0) + MV_DV_REG_READ_ASM (r6, r1, CPU_FTDLL_CONFIG_REG) + + ldr r1, =0xFFFF8080 + and r6, r6, r1 + ldr r1, =0x821b + orr r6, r6, r1 + + MV_DV_REG_WRITE_ASM (r6, r1, CPU_FTDLL_CONFIG_REG) +#endif + b device_cont +device_5281_A0: +device_cont: +#if defined(MV88F6190) || defined(MV88F6192) + MV_DV_REG_READ_ASM(r6, r1, CHIP_BOND_REG) + ldr r2, =0x3 + and r6, r6, r2 + cmp r6, #0x1 + bne not619X + +/* Setting the PEX header device ID for 6190 and 6192 */ + MV_DV_REG_READ_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID)) +#if defined(MV88F6190) + ldr r1, =MV_6190_DEV_ID +#else + ldr r1, =MV_6192_DEV_ID +#endif /* MV_88F6190 */ + ldr r2, =0xffff + and r6, r6, r2 + orr r6, r6, r1, LSL #PXDAVI_DEV_ID_OFFS + MV_DV_REG_WRITE_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID)) +not619X: +#endif +#if defined(MV88F6280) +/* Setting the PEX header device ID for 6280 */ + MV_DV_REG_READ_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID)) + ldr r1, =MV_6280_DEV_ID + ldr r2, =0xffff + and r6, r6, r2 + orr r6, r6, r1, LSL #PXDAVI_DEV_ID_OFFS + MV_DV_REG_WRITE_ASM(r6, r1, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID)) +#endif + + mov lr, r8 + mov pc, lr + +#endif + + +__start: + .word _start + +.globl dramBoot +dramBoot: + .word 0 + +_jumpStart: + .word .reset_vector_sect + +.section ".dummy",#alloc, #execinstr + .long 0xffffffff + .long 0xffffffff + .long 0xffffffff + .long 0xffffffff + + diff --git a/board/mv_feroceon/USP/mvDiag.c b/board/mv_feroceon/USP/mvDiag.c new file mode 100644 index 0000000..bf856ba --- /dev/null +++ b/board/mv_feroceon/USP/mvDiag.c @@ -0,0 +1,130 @@ + +#include "uart/mvUart.h" +#include "rtc/integ_rtc/mvRtc.h" + +/* UART timeout = UART_TIMEOUT * 100 usec */ +#define UART_TIMEOUT 500 + +/* Function prototypes */ +MV_VOID mvBoardEnvInit(MV_VOID); +MV_STATUS mvCtrlEnvInit(MV_VOID); +MV_VOID mvCpuIfInit(MV_VOID); + +MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); +MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); +MV_U32 mvDramIfSizeGet(MV_VOID); + +/* Global variables */ +extern unsigned int _TEXT_BASE; + +/* Source code */ + +void diag_board_init(char *board_name) +{ + mvBoardEnvInit(); + mvCtrlEnvInit(); + mvCpuIfInit(); + + mvBoardNameGet(board_name); +} + +void diag_get_mem_detail(unsigned int **mem_test_start_offset, + unsigned int **mem_test_end_offset) +{ + unsigned int start_offset, end_offset; + + /* Get the base address of memory bank 0 */ + end_offset = start_offset = mvDramIfBankBaseGet(0); + + /* Start from the location where u-boot ends + * FIXME: Additional _1M is added for heap size + */ + start_offset += _TEXT_BASE + _1M + _1M; + + /* TODO: If we are using same DRAM register init file for base and + * client, we need to hard-code end-offset for base to be 256M */ + end_offset += mvDramIfSizeGet(); + + *mem_test_start_offset = (unsigned int *)start_offset; + *mem_test_end_offset = (unsigned int *)end_offset; +} + +void diag_serial_init(int port, int baud_rate) +{ + mvUartInit(port, CFG_TCLK / (16 * baud_rate), mvUartBase(port)); + +#if defined(LCP_88F6281) + unsigned int reg_val = 0; + if(port) + { + /* Change MPP settings for UART1 */ + reg_val = MV_REG_READ(mvCtrlMppRegGet(1)); + + reg_val &= ~(0xFF << 20); + reg_val |= (0x33 << 20); + + MV_REG_WRITE(mvCtrlMppRegGet(1), reg_val); + + /* Select UART from SD/UART selection switch - MPP34 */ + MV_REG_WRITE(0x10140, MV_REG_READ(0x10140) | BIT2); + + /* Output enable */ + MV_REG_WRITE(0x10144, MV_REG_READ(0x10144) & ~(BIT2)); + } +#endif + +} + +void diag_int_lpbk(int port, int set) +{ + volatile MV_UART_PORT *pUartPort = (volatile MV_UART_PORT *)mvUartBase(port); + + if(set) + pUartPort->mcr |= 0x10; + else + pUartPort->mcr &= ~(0x10); +} + +void diag_uart_putc(int port, unsigned char c) +{ + mvUartPutc(port, c); +} + +int diag_uart_getc(int port, unsigned char *c) +{ + volatile MV_UART_PORT *pUartPort = (volatile MV_UART_PORT *)mvUartBase(port); + int timeout = 0; + + while ( ((pUartPort->lsr & LSR_DR) == 0) && (++timeout < UART_TIMEOUT) ) + { + udelay(100); + } + + if (timeout == UART_TIMEOUT) + return 1; + + *c = pUartPort->rbr; + return 0; +} + +void diag_get_rtc_time(int *hour, int *minute, int *second) +{ + MV_RTC_TIME mvRtcTime; + + mvRtcTimeGet(&mvRtcTime); + + *hour = mvRtcTime.hours; + *minute = mvRtcTime.minutes; + *second = mvRtcTime.seconds; +} + +void diag_set_rtc_time(int hour, int minute, int second) +{ + MV_RTC_TIME mvRtcTime; + + mvRtcTime.hours = hour; + mvRtcTime.minutes = minute; + mvRtcTime.seconds = second; + + mvRtcTimeSet(&mvRtcTime); +} diff --git a/board/mv_feroceon/USP/mv_egiga.c b/board/mv_feroceon/USP/mv_egiga.c new file mode 100644 index 0000000..4b39516 --- /dev/null +++ b/board/mv_feroceon/USP/mv_egiga.c @@ -0,0 +1,579 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include +#include + +#if defined (MV_INCLUDE_GIG_ETH) +#include "sys/mvSysGbe.h" +#include "mvOs.h" +#include "mvSysHwConfig.h" +#include "eth/mvEth.h" +#include "gpp/mvGppRegs.h" +#include "eth/gbe/mvEthGbe.h" +#include "eth-phy/mvEthPhy.h" +#include "ethSwitch/mvSwitch.h" +#include "mvBoardEnvLib.h" +#if defined(DUAL_OS_78200) || defined(DUAL_OS_SHARED_MEM_78200) +#include "mv78200/mvSocUnitMap.h" +#include "mv78200/mvSemaphore.h" +#endif +/* #define MV_DEBUG*/ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/****************************************************** + * driver internal definitions -- * + ******************************************************/ +/* use only tx-queue0 and rx-queue0 */ +#define EGIGA_DEF_TXQ 0 +#define EGIGA_DEF_RXQ 0 + +/* rx buffer size */ +#define ETH_HLEN 14 +#define WRAP (2 + ETH_HLEN + 4 + 32) /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch)*/ +#define MTU 1500 +#define RX_BUFFER_SIZE (MTU + WRAP) + +/* rings length */ +#define EGIGA_TXQ_LEN 20 +#define EGIGA_RXQ_LEN 20 + + +typedef struct _egigaPriv +{ + int port; + MV_VOID *halPriv; + MV_U32 rxqCount; + MV_U32 txqCount; + MV_BOOL devInit; +} egigaPriv; + + + +/****************************************************** + * functions prototype -- * + ******************************************************/ +static int mvEgigaLoad( int port, char *name, char *enet_addr ); + +static int mvEgigaInit( struct eth_device *dev, bd_t *p ); +static int mvEgigaHalt( struct eth_device *dev ); +static int mvEgigaTx( struct eth_device *dev, volatile MV_VOID *packet, int len ); +static int mvEgigaRx( struct eth_device *dev ); + +static MV_PKT_INFO* mvEgigaRxFill(MV_VOID); + + + +/*********************************************************** + * mv_eth_initialize -- * + * main driver initialization. loading the interfaces. * + ***********************************************************/ +int mv_eth_initialize( bd_t *bis ) +{ + + int port; + MV_8 *enet_addr; + MV_8 name[NAMESIZE+1]; + MV_8 enetvar[9]; + MV_8 ethPortNum = mvCtrlEthMaxPortGet(); + MV_U32 ctrlId = mvCtrlModelGet(); + + mvEthInit(); + + for(port=0; portname, name, NAMESIZE ); + mvMacStrToHex(enet_addr, (MV_8 *)(dev->enetaddr)); + + /* set MAC addres even if port was not used yet. */ + dummy_port_handle.portNo = port; + + mvEthMacAddrSet( &dummy_port_handle, dev->enetaddr, EGIGA_DEF_RXQ); + + dev->init = (void *)mvEgigaInit; + dev->halt = (void *)mvEgigaHalt; + dev->send = (void *)mvEgigaTx; + dev->recv = (void *)mvEgigaRx; + dev->priv = priv; + dev->iobase = 0; + priv->port = port; + + /* register the interface */ + eth_register(dev); + + + DB( printf( "%s: %s load ok\n", __FUNCTION__, name ) ); + return 0; + + error: + printf( "%s: %s load failed\n", __FUNCTION__, name ); + if( priv ) free( dev->priv ); + if( dev ) free( dev ); + return -1; +} + + +static MV_PKT_INFO* mvEgigaRxFill(MV_VOID) +{ + MV_BUF_INFO *pBufInfo; + MV_PKT_INFO *pPktInfo; + MV_U8 *buf = (MV_U8 *)memalign( 32, RX_BUFFER_SIZE ); /* align on 32B */ + if( !buf ) { + DB(printf("failed to alloc buffer\n")); + return NULL; + } + + if( ((MV_U32)buf) & 0xf ) + printf( "un-align rx buffer %x\n", (MV_U32)buf ); + + pPktInfo = malloc(sizeof(MV_PKT_INFO)); + if (pPktInfo == NULL) { + printf("Error: cannot allocate memory for pktInfo\n"); + free(buf); + return NULL; + } + + pBufInfo = malloc(sizeof(MV_BUF_INFO)); + if (pBufInfo == NULL) { + printf("Error: cannot allocate memory for bufInfo\n"); + free(buf); + free(pPktInfo); + return NULL; + } + pBufInfo->bufPhysAddr = mvOsIoVirtToPhy(NULL, buf); + pBufInfo->bufVirtPtr = buf; + pBufInfo->bufSize = RX_BUFFER_SIZE; + pBufInfo->dataSize = 0; + pPktInfo->osInfo = (MV_ULONG)buf; + pPktInfo->pFrags = pBufInfo; + pPktInfo->pktSize = RX_BUFFER_SIZE; /* how much to invalidate */ + pPktInfo->numFrags = 1; + pPktInfo->status = 0; + pPktInfo->ownerId = -1; + return pPktInfo; +} + + +unsigned int egiga_init=0; + +static int mvEgigaInit( struct eth_device *dev, bd_t *p ) +{ + egigaPriv *priv = dev->priv; + MV_ETH_PORT_INIT halInitStruct; + MV_PKT_INFO *pktInfo; + MV_STATUS status; + int i; + + DB( printf( "%s: %s init - ", __FUNCTION__, dev->name ) ); + + /* egiga not ready */ + DB( printf ("mvBoardsAddrGet()=0x%x , priv->port =0x%x\n",mvBoardPhyAddrGet(priv->port),priv->port)); + + /* If speed is not auto then link is force */ + if (BOARD_MAC_SPEED_AUTO == mvBoardMacSpeedGet(priv->port)) + { +#if defined(DUAL_OS_78200) || defined(DUAL_OS_SHARED_MEM_78200) + mvSemaLock(MV_SEMA_SMI); +#endif + /* Check Link status on phy */ + if( mvEthPhyCheckLink( mvBoardPhyAddrGet(priv->port) ) == MV_FALSE ) { +#if defined(DUAL_OS_78200) || defined(DUAL_OS_SHARED_MEM_78200) + mvSemaUnlock(MV_SEMA_SMI); +#endif + printf( "%s no link\n", dev->name ); + return 0; + } + else { +#if defined(DUAL_OS_78200) || defined(DUAL_OS_SHARED_MEM_78200) + mvSemaUnlock(MV_SEMA_SMI); +#endif + DB( printf( "link up\n" ) ); + } + } + + egiga_init = 1; + + /* init the hal -- create internal port control structure and descriptor rings, */ + /* open address decode windows, disable rx and tx operations. mask interrupts. */ + halInitStruct.maxRxPktSize = RX_BUFFER_SIZE; + halInitStruct.rxDefQ = EGIGA_DEF_RXQ; + + halInitStruct.txDescrNum[0] = EGIGA_TXQ_LEN; + halInitStruct.rxDescrNum[0] = EGIGA_RXQ_LEN; + halInitStruct.osHandle = NULL; + + priv->halPriv = mvEthPortInit( priv->port, &halInitStruct ); + + if( !priv->halPriv ) { + DB( printf( "falied to init eth port (error)\n" ) ); + goto error; + } + + /* set new addr in hw */ + if( mvEthMacAddrSet( priv->halPriv, dev->enetaddr, EGIGA_DEF_RXQ) != MV_OK ) { + printf("%s: ethSetMacAddr failed\n", dev->name ); + goto error; + } + + priv->devInit = MV_TRUE; + + /* fill rx ring with buffers */ + for( i=0; ihalPriv, EGIGA_DEF_RXQ, pktInfo ); + if( status == MV_OK ) { + priv->rxqCount++; + } + else if( status == MV_FULL ) { + /* the ring is full */ + priv->rxqCount++; + DB( printf( "ring full\n" ) ); + break; + } + else { + printf( "error\n" ); + goto error; + } + } + +#ifdef MV_DEBUG + ethPortQueues(priv->port, EGIGA_DEF_RXQ, EGIGA_DEF_TXQ, 1); + + printf("%s : after calling ethPortQueues\n",__FUNCTION__); + +#endif + + + /* start the hal - rx/tx activity */ + /* Check if link is up for 2 Sec */ + for (i = 1; i < 100 ; i ++) + { + status = mvEthPortEnable( priv->halPriv ); + if (status == MV_OK) + break; + mvOsDelay(20); + } + + if( status != MV_OK ) { + printf( "%s: %s mvEthPortEnable failed (error)\n", __FUNCTION__, dev->name ); + goto error; + } + +#ifdef MV_DEBUG + ethRegs(priv->port); + ethPortRegs(priv->port); + ethPortStatus(priv->port); + + ethPortQueues(priv->port, EGIGA_DEF_RXQ, -1/*EGIGA_DEF_TXQ*/, 0); +#endif + + DB( printf( "%s: %s complete ok\n", __FUNCTION__, dev->name ) ); + return 1; + + error: + if( priv->devInit ) + mvEgigaHalt( dev ); + printf( "%s: %s failed\n", __FUNCTION__, dev->name ); + return 0; +} + +static int mvEgigaHalt( struct eth_device *dev ) +{ + + egigaPriv *priv = dev->priv; + MV_PKT_INFO *pktInfo; + + DB( printf( "%s: %s halt - ", __FUNCTION__, dev->name ) ); + if( priv->devInit == MV_TRUE ) { + + /* stop the port activity, mask all interrupts */ + if( mvEthPortDisable( priv->halPriv ) != MV_OK ) + printf( "mvEthPortDisable failed (error)\n" ); + + /* free the buffs in the rx ring */ + while( (pktInfo = mvEthPortForceRx( priv->halPriv, EGIGA_DEF_RXQ )) != NULL ) { + priv->rxqCount--; + if( pktInfo->osInfo ) + free( (void *)pktInfo->osInfo ); + else + printf( "mvEthPortForceRx failed (error)\n" ); + if( pktInfo->pFrags ) + free( (void *)pktInfo->pFrags ); + else + printf( "mvEthPortForceRx failed (error)\n" ); + free( (void *)pktInfo ); + } + + /* Clear Cause registers (must come before mvEthPortFinish) */ + MV_REG_WRITE(ETH_INTR_CAUSE_REG(((ETH_PORT_CTRL*)(priv->halPriv))->portNo),0); + MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(((ETH_PORT_CTRL*)(priv->halPriv))->portNo),0); + + /* Clear Cause registers */ + MV_REG_WRITE(ETH_INTR_CAUSE_REG(((ETH_PORT_CTRL*)(priv->halPriv))->portNo),0); + MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(((ETH_PORT_CTRL*)(priv->halPriv))->portNo),0); + + mvEthPortFinish( priv->halPriv ); + priv->devInit = MV_FALSE; + + } + egiga_init = 0; + + DB( printf( "%s: %s complete\n", __FUNCTION__, dev->name ) ); + return 0; +} + +static int mvEgigaTx( struct eth_device *dev, volatile void *buf, int len ) +{ + egigaPriv *priv = dev->priv; + MV_BUF_INFO bufInfo; + MV_PKT_INFO pktInfo; + MV_PKT_INFO *pPktInfo; + MV_STATUS status; + + DB( printf( "mvEgigaTx start\n" ) ); + /* if no link exist */ + if(!egiga_init) return 0; + + + pktInfo.osInfo = (MV_ULONG)0x44CAFE44; + pktInfo.pktSize = len; + pktInfo.pFrags = &bufInfo; + pktInfo.status = 0; + pktInfo.numFrags = 1; + bufInfo.bufVirtPtr = (MV_U8*)buf; + bufInfo.bufPhysAddr = mvOsIoVirtToPhy(NULL, buf); + bufInfo.dataSize = len; + + /* send the packet */ + status = mvEthPortTx( priv->halPriv, EGIGA_DEF_TXQ, &pktInfo ); + + if( status != MV_OK ) { + if( status == MV_NO_RESOURCE ) + DB( printf( "ring is full (error)\n" ) ); + else if( status == MV_ERROR ) + printf( "error\n" ); + else + printf( "unrecognize status (error) ethPortSend\n" ); + goto error; + } + else DB( printf( "ok\n" ) ); + + priv->txqCount++; + + /* release the transmitted packet(s) */ + while( 1 ) { + + DB( printf( "%s: %s tx-done - ", __FUNCTION__, dev->name ) ); + + /* get a packet */ + pPktInfo = mvEthPortTxDone( priv->halPriv, EGIGA_DEF_TXQ); + + if( pPktInfo != NULL ) { + + priv->txqCount--; + + /* validate skb */ + if( (pPktInfo != &pktInfo) || (pPktInfo->osInfo != 0x44CAFE44 ) ) { + printf( "error\n" ); + goto error; + } + + /* handle tx error */ + if( pPktInfo->status & (ETH_ERROR_SUMMARY_BIT) ) { + printf( "bad status (error)\n" ); + goto error; + } + DB( printf( "ok\n" ) ); + break; + } + else + DB(printf( "NULL pPktInfo\n" )); + } + + DB( printf( "%s: %s complete ok\n", __FUNCTION__, dev->name ) ); + return 0; + + error: + printf( "%s: %s failed\n", __FUNCTION__, dev->name ); + return 1; +} + + +static int mvEgigaRx( struct eth_device *dev ) +{ + egigaPriv* priv = dev->priv; + MV_PKT_INFO *pktInfo; + MV_STATUS status; + + /* if no link exist */ + if(!egiga_init) return 0; + + while( 1 ) { + + /* get rx packet from hal */ + pktInfo = mvEthPortRx( priv->halPriv, EGIGA_DEF_RXQ); + + if( pktInfo != NULL ) { + /*DB( printf( "good rx\n" ) );*/ + priv->rxqCount--; + + /* check rx error status */ + if( pktInfo->status & (ETH_ERROR_SUMMARY_MASK) ) { + MV_U32 err = pktInfo->status & ETH_RX_ERROR_CODE_MASK; + /*DB( printf( "bad rx status %08x, ", (MV_U32)pktInfo->cmdSts ) );*/ + if( err == ETH_RX_RESOURCE_ERROR ) + DB( printf( "(resource error)" ) ); + else if( err == ETH_RX_MAX_FRAME_LEN_ERROR ) + DB( printf( "(max frame length error)" ) ); + else if( err == ETH_RX_OVERRUN_ERROR ) + DB( printf( "(overrun error)" ) ); + else if( err == ETH_RX_CRC_ERROR ) + DB( printf( "(crc error)" ) ); + else { + DB( printf( "(unknown error)" ) ); + goto error; + } + DB( printf( "\n" ) ); + } + else { + + DB( printf( "%s: %s calling NetRecieve ", __FUNCTION__, dev->name) ); + DB( printf( "%s: calling NetRecieve pkInfo = 0x%x\n", __FUNCTION__, pktInfo) ); + DB( printf( "%s: calling NetRecieve osInfo = 0x%x\n", __FUNCTION__, pktInfo->osInfo) ); + DB( printf( "%s: calling NetRecieve pktSize = 0x%x\n", __FUNCTION__, pktInfo->pFrags->dataSize) ); + /* good rx - push the packet up (skip on two first empty bytes) */ + NetReceive( ((MV_U8 *)pktInfo->osInfo) + 2, (int)pktInfo->pFrags->dataSize); + } + + + DB( printf( "%s: %s refill rx buffer - ", __FUNCTION__, dev->name) ); + + /* give the buffer back to hal (re-init the buffer address) */ + pktInfo->pktSize = RX_BUFFER_SIZE; /* how much to invalidate */ + status = mvEthPortRxDone( priv->halPriv, EGIGA_DEF_RXQ, pktInfo ); + + if( status == MV_OK ) { + priv->rxqCount++; + } + else if( status == MV_FULL ) { + /* this buffer made the ring full */ + priv->rxqCount++; + DB( printf( "ring full\n" ) ); + break; + } + else { + printf( "error\n" ); + goto error; + } + + } else { + /* no more rx packets ready */ + /* DB( printf( "no more work\n" ) ); */ + break; + } + } + + /*DB( printf( "%s: %s complete ok\n", __FUNCTION__, dev->name ) );*/ + return 0; + + error: + DB( printf( "%s: %s failed\n", __FUNCTION__, dev->name ) ); + return 1; +} +#endif /* #if defined (MV_INCLUDE_GIG_ETH) */ diff --git a/board/mv_feroceon/USP/mv_ext2_boot.c b/board/mv_feroceon/USP/mv_ext2_boot.c new file mode 100644 index 0000000..146af1e --- /dev/null +++ b/board/mv_feroceon/USP/mv_ext2_boot.c @@ -0,0 +1,186 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +#include +#include +#include +#include +#include +#include +#include +#include "xor/mvXor.h" + + +#if (CONFIG_COMMANDS & CFG_CMD_EXT2) + +#define DOS_PART_MAGIC_OFFSET 0x1fe +#define PARTITION_CRC_OFF 0x0 +#ifdef CONFIG_ISO_PARTITION +/* Make the buffers bigger if ISO partition support is enabled -- CD-ROMS + have 2048 byte blocks */ +#define DEFAULT_SECTOR_SIZE 2048 +#else +#define DEFAULT_SECTOR_SIZE 512 +#endif + +#define MAX_BOOT_PART 2 + +extern block_dev_desc_t * ide_get_dev(int dev); + +static char tmp_string[100]; +static char tmp_string1[100]; + +int do_bootext2 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + int dev,part,active_part= -1 ; + ulong addr; + volatile disk_partition_t info[2]; + volatile char *env,*env2; + block_dev_desc_t *dev_desc; + ulong boot_part[MAX_BOOT_PART]; + char *ep; + + if (argc != 5) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + dev = simple_strtoul(argv[1], &ep, 16); + if (*ep) { + if (*ep != ':') + { + printf ("Usage:\n%s\n", cmdtp->usage); + return(1); + } + + for (part=0 ; part < MAX_BOOT_PART-1 ; part++) + { + ep++; + boot_part[part] = (ulong)simple_strtoul(ep, &ep, 16); + if (*ep != ',') { + printf ("Usage:\n%s\n", cmdtp->usage); + return(1); + } + + } + boot_part[part] = (ulong)simple_strtoul(++ep, NULL, 16); + + } + else + { + puts ("\n** Invalid boot device, use `dev:boot_part1,boot_part2' **\n"); + return(1); + } + + addr = simple_strtoul(argv[2], NULL, 16); + + dev_desc = (dev >= CFG_IDE_MAXDEVICE) ? NULL : ide_get_dev(dev); + + if (dev_desc == NULL) + { + printf("Non valid dev number %x\n",dev); + return 1; + } + + + /* Initialize IDE */ + sprintf(tmp_string,"ide reset"); + run_command(tmp_string,0); + + + /* Search for Active partition in partition #1 and partition #2*/ + for (part = 0; part < MAX_BOOT_PART ;part++ ) + { + if (get_partition_info (dev_desc, + boot_part[part], + (disk_partition_t*)&info[part])) + { + continue; + } + + if (info[part].boot_ind ) + { + active_part = part; + break; + } + } + + /* If no active partition then return */ + if (active_part == -1) + { + printf("No active partition on %d and %d\n", + boot_part[0],boot_part[1]); + return 1; + } + + /* Load /boot/uImage from active_part to addr */ + sprintf(tmp_string,"ext2load ide %x:%x %x %s", dev, boot_part[active_part], addr,argv[3]); + printf("%s\n",tmp_string); + run_command(tmp_string,0); + + sprintf(tmp_string,"root=%s%d ro",argv[4],boot_part[active_part]); + setenv("bootargs_root",tmp_string); + + env = getenv("bootargs"); + env2 = getenv("bootargs_root"); + /* Save bootargs for secondary boot option if boot from active partition will fail */ + sprintf(tmp_string1,"%s",env); + sprintf(tmp_string,"%s %s",env,env2); + setenv("bootargs",tmp_string); + + sprintf(tmp_string,"bootm %x", addr); + + printf("%s\n",tmp_string); + run_command(tmp_string,0); + + /* If we get here then first boot fail */ + active_part = (active_part + 1)%MAX_BOOT_PART; + + sprintf(tmp_string,"ext2load ide %x:%x %x %s", dev, boot_part[active_part], addr,argv[3]); + printf("%s\n",tmp_string); + run_command(tmp_string,0); + + sprintf(tmp_string,"root=%s%d ro",argv[4],boot_part[active_part]); + setenv("bootargs_root",tmp_string); + env2 = getenv("bootargs_root"); + sprintf(tmp_string,"%s %s %s",tmp_string1,env2, "boot_failure"); + setenv("bootargs",tmp_string); + + sprintf(tmp_string,"bootm %x", addr); + + printf("Starting secondary boot...\n"); + printf("%s\n",tmp_string); + run_command(tmp_string,0); + printf("Secondary boot fail...\n"); + return 1; +} + +U_BOOT_CMD( + bootext2, 5, 0, do_bootext2, + "bootext2 dev:boot_part1,boot_part2 addr boot_image linux_dev_name \n", + "dev:boot_part1,boot_part2 addr boot_image linux_dev_name\n" + "- boot boot_image from active ext2 partition\n" +); +#endif + + diff --git a/board/mv_feroceon/USP/mv_flash.c b/board/mv_feroceon/USP/mv_flash.c new file mode 100644 index 0000000..9000cfa --- /dev/null +++ b/board/mv_feroceon/USP/mv_flash.c @@ -0,0 +1,1687 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) +#include +#include "norflash/mvFlash.h" +#include "device/mvDeviceRegs.h" +#include "mvBoardEnvSpec.h" + +#include "mvOs.h" +#include "mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "mvCpuIf.h" + +#if defined (MV_INCLUDE_INTEG_MFLASH) +#include "mvMFlash.h" +#include "mvMFlashSpec.h" +#include "mvSMFlash.h" +#include "mvPMFlash.h" +#endif + +#if defined (MV_INC_BOARD_SPI_FLASH) +#include "sflash/mvSFlash.h" +#endif + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +#define FLASH_ROM 0xFFFD /* unknown flash type */ +#define FLASH_RAM 0xFFFE /* unknown flash type */ +#define FLASH_MAN_UNKNOWN 0xFFFF0000 +#define NL_HASHES_PER_LINE 65 + +#define CFI_CMDSET_INTEL_EXTENDED 1 +#define CFI_CMDSET_AMD_STANDARD 2 +#define CFI_CMDSET_INTEL_STANDARD 3 +#define CFI_CMDSET_AMD_EXTENDED 4 + +extern unsigned int whoAmI(void); + +void flashInfoCopy(flash_info_t *flash_info, MV_FLASH_INFO *pFlash); +MV_U32 getMvFlashInfoNum(flash_info_t *flash_info); +MV_FLASH_INFO* getMvFlashInfo(int index); +int mv_flash_real_protect(flash_info_t *info, long sector, int prot); +int mv_flash_real_protect_bank(flash_info_t *info, int prot); +#if defined (MV_INCLUDE_INTEG_MFLASH) +void mflash_print_info (MV_MFLASH_INFO * pInfo); +unsigned long mflash_init (MV_MFLASH_INFO * mflInfo); +#endif + +#if defined (MV_INC_BOARD_SPI_FLASH) +void sflash_print_info (MV_SFLASH_INFO * pInfo); +unsigned long sflash_init (MV_SFLASH_INFO * sflInfo); +#endif + +/* use CFG_MAX_FLASH_BANKS_DETECT if defined */ +#ifdef CFG_MAX_FLASH_BANKS_DETECT +static MV_FLASH_INFO mvFlashInfo[CFG_MAX_FLASH_BANKS_DETECT]; +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */ +extern int mv_board_num_flash_banks; +#else +static MV_FLASH_INFO mvFlashInfo[CFG_MAX_FLASH_BANKS]; +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +#endif + +/* Static Variables */ +#if defined (MV_INCLUDE_INTEG_MFLASH) +static MV_MFLASH_INFO mflash; +#endif + +#if defined (MV_INC_BOARD_SPI_FLASH) +static MV_SFLASH_INFO sflash = {0x0, 0, 0, 0, 0, 0, MV_INVALID_DEVICE_NUMBER}; +#endif + +static unsigned long norFlashBanksNum = 0; +static unsigned long mFlashBanksNum = 0; +static unsigned long sFlashBanksNum = 0; + +typedef enum +{ + MV_UNKNOWN_FLASH = 0, + MV_NOR_FLASH, + MV_MARVELL_FLASH, + MV_SPI_FLASH +} MV_FLASH_TYPE; + +/* return NULL in case didn't find a matching mvFlashInfo */ +MV_FLASH_INFO* getMvFlashInfo(int index) +{ + if (CFG_MAX_FLASH_BANKS < index) + return NULL; + return &mvFlashInfo[index]; +} + +/* based on index get the type of flash */ +static MV_FLASH_TYPE mvFlashTypeFromIndexGet(MV_U32 indx) +{ + if ((indx >= 0) && (indx < norFlashBanksNum)) + return MV_NOR_FLASH; + else if ((indx >= norFlashBanksNum) && \ + (indx < (norFlashBanksNum + mFlashBanksNum))) + return MV_MARVELL_FLASH; + else if ((indx >= (norFlashBanksNum + mFlashBanksNum)) && + (indx < (norFlashBanksNum + mFlashBanksNum + sFlashBanksNum))) + return MV_SPI_FLASH; + + return MV_UNKNOWN_FLASH; +} + +/* return 0xFFFFFFFF in case didn't find a matching mvFlashInfo */ +MV_U32 +getMvFlashInfoNum(flash_info_t * pFlash_info) +{ + MV_U32 i; + + DB(mvOsPrintf("%s\n", __FUNCTION__)); + if( pFlash_info->flash_id == FLASH_UNKNOWN ) + { + DB(printf("%s : ERROR didn't find mvFlashInfo matching to flash_info_t.\n", __FUNCTION__)); + return 0xFFFFFFFF; + } + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + if (&flash_info[i] == pFlash_info) + { + DB(printf("getMvFlashInfoNum found mvFlashInfo %d \n",i)); + return i; + } + DB(mvOsPrintf(" %x %x \n",mvFlashBaseAddrGet(&mvFlashInfo[i]), mvFlashVenIdGet(&mvFlashInfo[i]))); + } + + DB(mvOsPrintf("%s(%d): ERROR didn't find mvFlashInfo matching to flash_info_t.\n", __FUNCTION__)); + + return 0xFFFFFFFF; +} + + +/* make sure that #define CFG_FLASH_PROTECTION present in MV64xx.h */ + +int +mv_flash_real_protect(flash_info_t *info, long sector, int prot) +{ + MV_U32 s; + s = getMvFlashInfoNum(info); + if(s >= CFG_MAX_FLASH_BANKS) + { + DB(printf("mv_flash_real_protect illegal mvFlashInfo \n")); + return 1; + } + + switch(mvFlashTypeFromIndexGet(s)) + { +#if defined (MV_INC_BOARD_NOR_FLASH) + case MV_NOR_FLASH: + if( mvFlashSecLockSet(&mvFlashInfo[s],sector,prot) != MV_OK) + return 1; /* Write was not completed */ + info->protect[sector] = prot; + break; +#endif + +#if defined (MV_INCLUDE_INTEG_MFLASH) + case MV_MARVELL_FLASH: + /* printf("MFlash WP modification per sector is not supported by this command!!\n"); */ + if(mv_flash_real_protect_bank(info, prot) != MV_OK) + return 1; + break; +#endif + +#if defined (MV_INC_BOARD_SPI_FLASH) + case MV_SPI_FLASH: + /* printf("SPI Flash WP modification per sector is not supported by this command!!\n"); */ + if(mv_flash_real_protect_bank(info, prot) != MV_OK) + return 1; + break; +#endif + + default: + return 1; + } + + return 0; /* write completed succefully */ +} + +int +mv_flash_real_protect_bank(flash_info_t *info, int prot) +{ + MV_U32 s; + MV_U32 i; + + s = getMvFlashInfoNum(info); + if(s >= CFG_MAX_FLASH_BANKS) + { + DB(printf("mv_flash_real_protect_bank illegal mvFlashInfo \n")); + return 1; + } + + switch(mvFlashTypeFromIndexGet(s)) + { +#if defined (MV_INC_BOARD_NOR_FLASH) + case MV_NOR_FLASH: + for (i=0; isector_count; ++i) + { + if( mvFlashSecLockSet(&mvFlashInfo[s],i,prot) != MV_OK) + return 1; /* Write was not completed */ + + info->protect[i] = prot; + putc ('.'); + } + break; +#endif + +#if defined (MV_INCLUDE_INTEG_MFLASH) + case MV_MARVELL_FLASH: + if (mvMFlashWriteProtectSet(&mflash, prot) != MV_OK) + return 1; + + for (i=0; isector_count; ++i) + info->protect[i] = prot; + break; +#endif + +#if defined (MV_INC_BOARD_SPI_FLASH) + case MV_SPI_FLASH: + if (prot) + { + if (mvSFlashWpRegionSet(&sflash, MV_WP_ALL) != MV_OK) + return 1; + } + else + { + if (mvSFlashWpRegionSet(&sflash, MV_WP_NONE) != MV_OK) + return 1; + } + + for (i=0; isector_count; ++i) + info->protect[i] = prot; + break; +#endif + + default: + return 1; + } + + return 0; /* write completed succefully */ +} + +/******************************************************************** +* Copy global CFI info into Marvell FLash info +********************************************************************/ +void flashMvInfoCopy(flash_info_t *flash_info, MV_FLASH_INFO *pFlash) +{ + MV_U32 i; + + /* Check if flash_info containe CFI data */ + if(mvFlashVenIdGet(pFlash) != FLASH_UNKNOWN) + { + return; + } + + if(flash_info->flash_id == FLASH_UNKNOWN) + { + pFlash->flashSpec.flashVen = FLASH_UNKNOWN; + return; + } + + /* convert to MV_FLASH_INFO manufactor Id */ + switch (flash_info->vendor) + { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + pFlash->flashSpec.flashVen = INTEL_MANUF; + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + pFlash->flashSpec.flashVen = AMD_MANUF; + break; + default: + pFlash->flashSpec.flashVen = 0; + break; + } + + /* convert to MV_FLASH_INFO flash Id */ + pFlash->flashSpec.flashId = (flash_info->flash_id & FLASH_TYPEMASK); + + /* other flash info parameters */ + pFlash->flashSpec.size = (flash_info->size / (flash_info->portwidth / flash_info->chipwidth)); + pFlash->flashSpec.sectorNum = flash_info->sector_count; + pFlash->busWidth = flash_info->portwidth; + pFlash->devWidth = flash_info->chipwidth; + + /* sectors parameters */ + for(i = 0; i < flash_info->sector_count; i++) + { + pFlash->sector[i].baseOffs = flash_info->start[i] - flash_info->start[0]; + pFlash->sector[i].protect = flash_info->protect[i]; + if (i + 1 < flash_info->sector_count) + pFlash->sector[i].size = flash_info->start[i+1] - flash_info->start[i]; + else + pFlash->sector[i].size = (flash_info->start[0] + flash_info->size) - flash_info->start[i]; + } + + pFlash->baseAddr = flash_info->start[0]; + + return; +} + +void +flashInfoCopy(flash_info_t *flash_info, MV_FLASH_INFO *pFlash) +{ + MV_U32 i; + + /* Check if flash_info containe CFI data */ + if(flash_info->flash_id != FLASH_UNKNOWN) + { + return; + } + + if(mvFlashVenIdGet(pFlash) == FLASH_UNKNOWN) + { + flash_info->flash_id = FLASH_UNKNOWN; + return; + } + /* convert to U-Boot manufactor Id */ + flash_info->flash_id = ((mvFlashVenIdGet(pFlash) << 16) & FLASH_VENDMASK); + /* convert to U-Boot flash Id */ + flash_info->flash_id |= (mvFlashDevIdGet(pFlash) & FLASH_TYPEMASK); + + /* other flash info parameters */ + flash_info->size = mvFlashSizeGet(pFlash); + flash_info->sector_count = mvFlashNumOfSecsGet(pFlash); + flash_info->portwidth = mvFlashBusWidthGet(pFlash); + flash_info->chipwidth = mvFlashDevWidthGet(pFlash); + + /* sectors parameters */ + for(i = 0; i < mvFlashNumOfSecsGet(pFlash); i++) + { + flash_info->start[i] = mvFlashSecOffsGet(pFlash,i) + mvFlashBaseAddrGet(pFlash); + flash_info->protect[i] = mvFlashSecLockGet(pFlash,i); + } + + return; +} + +#if defined (MV_INCLUDE_INTEG_MFLASH) +void +mflashInfoCopy(flash_info_t *flash_info, MV_MFLASH_INFO *pFlash) +{ + MV_U32 i; + MV_U32 mfId; + MV_U16 devId; + MV_BOOL wp; + + /* Check if the Model was detected during the init stage and read the WP status */ + if ((pFlash->flashModel == MV_MFLASH_MODEL_UNKNOWN) || + (mvMFlashIdGet(pFlash, &mfId, &devId) != MV_OK) || + (mvMFlashWriteProtectGet(pFlash, &wp) != MV_OK)) + { + flash_info->flash_id = FLASH_UNKNOWN; + return; + } + + /* Discard the manufacturer ID and use the device ID alnoe because we lack 16 bits */ + flash_info->flash_id = devId; + + /* other flash info parameters */ + flash_info->size = (pFlash->sectorSize * pFlash->sectorNumber); + flash_info->sector_count = pFlash->sectorNumber; + flash_info->portwidth = 1; /* Assuming 8bit although that this parameter is not used */ + flash_info->chipwidth = 1; /* Assuming 8bit although that this parameter is not used */ + + /* sectors parameters */ + for(i = 0; i < pFlash->sectorNumber; i++) + { + flash_info->start[i] = (pFlash->baseAddr + (i * pFlash->sectorSize)); + flash_info->protect[i] = wp; + } + + return; +} +#endif /* #if defined (MV_INCLUDE_INTEG_MFLASH) */ + +#if defined (MV_INC_BOARD_SPI_FLASH) +void +sflashInfoCopy(flash_info_t *flash_info, MV_SFLASH_INFO *pFlash) +{ + MV_U32 i; + MV_SFLASH_WP_REGION wp; + MV_BOOL wpVal; + + /* Check if the Model was detected during the init stage and read thw WP status */ + if ((pFlash->manufacturerId == 0) || + (mvSFlashWpRegionGet(pFlash, &wp) != MV_OK)) + { + flash_info->flash_id = FLASH_UNKNOWN; + return; + } + + /* Discard the manufacturer ID and use the device ID alnoe because we lack 16 bits */ + flash_info->flash_id = ((pFlash->manufacturerId << 16) | pFlash->deviceId); + + /* other flash info parameters */ + flash_info->size = (pFlash->sectorSize * pFlash->sectorNumber); + flash_info->sector_count = pFlash->sectorNumber; + flash_info->portwidth = 0; /* Serial interface */ + flash_info->chipwidth = 0; /* Serial interface */ + + if (wp == MV_WP_ALL) + wpVal = MV_TRUE; + else + wpVal = MV_FALSE; + + /* sectors parameters */ + for(i = 0; i < pFlash->sectorNumber; i++) + { + flash_info->start[i] = (pFlash->baseAddr + (i * pFlash->sectorSize)); + flash_info->protect[i] = wpVal; + } + + return; +} +#endif + +unsigned long +mvFlash_init (void) +{ + + MV_U32 i; + unsigned long current_bank_size=0; + unsigned long flash_size=0; + int spi_access = 0; + char *env; + +#if defined (MV_INC_BOARD_SPI_FLASH) || defined (MV_INCLUDE_INTEG_MFLASH) + MV_U32 bankIndx; +#endif /* defined (MV_INC_BOARD_SPI_FLASH) || defined (MV_INCLUDE_INTEG_MFLASH) */ + + /* Init: no FLASHes known */ + for (i=0; i CFG_MAX_FLASH_BANKS) + { + printf("%s ERROR: Number of flash devices exceeds the CFG_MAX_FLASH_BANKS=0x%x\n", + __FUNCTION__,CFG_MAX_FLASH_BANKS); + return 0; + } + + for (i=0; i < norFlashBanksNum; ++i) + { + /* CFI driver detected the device */ + if (flash_info[i].flash_id != FLASH_UNKNOWN) + { + printf("[%ldkB@%x] ", flash_info[i].size/1024, flash_info[i].start[0]); + continue; + } + + mvFlashInfo[i].baseAddr = mvBoardGetDeviceBaseAddr(i, BOARD_DEV_NOR_FLASH); + DB(printf("mvFlashInfo[%d].baseAddr %x\n",i,mvFlashInfo[i].baseAddr);) + mvFlashInfo[i].busWidth = mvBoardGetDeviceBusWidth(i, BOARD_DEV_NOR_FLASH)/8; + DB(printf("mvFlashInfo[%d].busWidth %x\n",i,mvFlashInfo[i].busWidth);) + mvFlashInfo[i].devWidth = mvBoardGetDeviceWidth(i, BOARD_DEV_NOR_FLASH)/8; + DB(printf("mvFlashInfo[%d].devWidth %x\n",i,mvFlashInfo[i].devWidth);) + + if (mvFlashInfo[i].baseAddr == 0xffffffff) continue; + + current_bank_size = mvFlashInit(&mvFlashInfo[i]); + + flashInfoCopy(&flash_info[i], &mvFlashInfo[i]); + + printf("[%ldkB@%x] ", flash_info[i].size/1024, flash_info[i].start[0]); + + if (flash_info[i].flash_id == FLASH_UNKNOWN) + { + printf ("## Unknown FLASH at %08x: Size = 0x%08lx = %ld MB\n", + mvFlashInfo[i].baseAddr, current_bank_size, current_bank_size<<20); + } + + flash_size += current_bank_size; + } + + /* Copy from CFI to MV_FLASH_INFO the CFI data */ + for (i=0; i < norFlashBanksNum; ++i) + flashMvInfoCopy(&flash_info[i], &mvFlashInfo[i]); + +#endif /* #if defined (MV_INC_BOARD_NOR_FLASH) */ + +#if defined (MV_INCLUDE_INTEG_MFLASH) + +#ifdef MV_INCLUDE_INTEG_MFLASH_SPI + if (mvCtrlSpiBusModeSet(MV_SPI_CONN_TO_MFLASH) != MV_OK) + { + printf("Failed to set the SPI bus to the MFlash mode\n"); + } +#endif + mflash.ifMode = MV_SPI_CONN_UNKNOWN; /* to be detected from H/W */ + mflash.baseAddr = mvCpuIfTargetWinBaseLowGet(MFLASH_CS); + mflash.flashModel = MV_MFLASH_MODEL_UNKNOWN; /* will be detected in init */ + mflash.sectorSize = 0; /* will be detected in init */ + mflash.sectorNumber = 0; /* will be detected in init */ + mflash.infoSize = 0; /* will be detected in init */ + + /* Try to initialize the Marvell Flash - returns the size of flash detected */ + if (mflash_init(&mflash) != 0) + { + /* update the number of Marvell flashes detected to be used in index calculation */ + mFlashBanksNum = 1; + DB(printf("Number of Marvell flashes on board %d\n", mFlashBanksNum);) + + /* check that we did not exceed the MAX flash banks supported */ + if ((norFlashBanksNum + mFlashBanksNum) > CFG_MAX_FLASH_BANKS) + { + printf("%s ERROR: Number of flash devices exceeds the CFG_MAX_FLASH_BANKS\n", __FUNCTION__); + return 0; + } + + /* Set the default sector size to small - needed for saveenv in the UBoot */ + if (mvMFlashSectorSizeSet(&mflash, MV_MFLASH_SECTOR_SIZE_SMALL) != MV_OK) + { + printf("%s ERROR: Failed to set MFlash sector size to SMALL\n", __FUNCTION__); + return 0; + } + + current_bank_size = (mflash.sectorSize * mflash.sectorNumber); + + bankIndx = norFlashBanksNum; + mflashInfoCopy(&flash_info[bankIndx], &mflash); + + printf("[%ldkB@%x] ", current_bank_size/1024, mflash.baseAddr); + + if (mflash.flashModel == MV_MFLASH_MODEL_UNKNOWN) + { + printf ("## Unknown MFLASH at %08x: Size = 0x%08lx = %ld MB\n", + mflash.baseAddr, current_bank_size, current_bank_size<<20); + } + + flash_size += current_bank_size; + } + else + { + DB(printf("Failed to initialize the Marvell Flash!\n");) + } + +#endif /* #if defined (MV_INCLUDE_INTEG_MFLASH) */ + +#if defined (MV_INC_BOARD_SPI_FLASH) + +#ifdef MV78200 + /* Check in dual CPU system which CPU use spi */ + if (mvSocUnitIsMappedToThisCpu(SPI_FLASH)) + spi_access = 1; +#else + spi_access = 1; +#endif + + if (spi_access) + { + sflash.baseAddr = mvCpuIfTargetWinBaseLowGet(SPI_CS); + sflash.manufacturerId = 0; /* will be detected in init */ + sflash.deviceId = 0; /* will be detected in init */ + sflash.sectorSize = 0; /* will be detected in init */ + sflash.sectorNumber = 0; /* will be detected in init */ + sflash.pageSize = 0; /* will be detected in init */ + sflash.index = MV_INVALID_DEVICE_NUMBER; /* will be detected in init */ + + /* Try to initialize an external SPI flash and retreive the size in case of success */ + if ((current_bank_size = sflash_init(&sflash)) != 0) + { + /* update the number of SPI flashes detected to be used in index calculation */ + sFlashBanksNum = 1; + DB(printf("Number of SPI flashes on board %d\n", sFlashBanksNum);) + + /* check that we did not exceed the MAX flash banks supported */ + if ((norFlashBanksNum + mFlashBanksNum + sFlashBanksNum) > CFG_MAX_FLASH_BANKS) + { + printf("%s ERROR: Number of flash devices exceeds the CFG_MAX_FLASH_BANKS\n", __FUNCTION__); + return 0; + } + + /* convert the SFlash structure into the Uboot structre */ + bankIndx = (norFlashBanksNum + mFlashBanksNum); + sflashInfoCopy(&flash_info[bankIndx], &sflash); + + printf("[%ldkB@%x] ", current_bank_size/1024, sflash.baseAddr); + + /* verify that the manufacturer Id was detected */ + if (sflash.manufacturerId == 0) + { + printf ("## Unknown SFLASH at %08x: Size = 0x%08lx = %ld MB\n", + sflash.baseAddr, current_bank_size, current_bank_size<<20); + } + + flash_size += current_bank_size; + } + else + { + DB(printf("Failed to initialize the SPI Flash!\n");) + } + } + +#endif /* #if defined (MV_INC_BOARD_SPI_FLASH) */ + + /* Set the write protection */ + if (norFlashBanksNum >= 1) + { + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[0]); + + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SECT_SIZE, + &flash_info[0]); + } + + return flash_size; + +} + + +/*----------------------------------------------------------------------- + */ +void +mv_flash_print_info (flash_info_t *info) +{ + MV_U32 s; + + s = getMvFlashInfoNum(info); + if(s >= CFG_MAX_FLASH_BANKS) + { + printf("missing or unknown FLASH type\n"); + return; + } + + switch(mvFlashTypeFromIndexGet(s)) + { +#if defined (MV_INC_BOARD_NOR_FLASH) + case MV_NOR_FLASH: + flashPrint(&mvFlashInfo[s]); + break; +#endif + +#if defined (MV_INCLUDE_INTEG_MFLASH) + case MV_MARVELL_FLASH: + mflash_print_info(&mflash); + break; +#endif + +#if defined (MV_INC_BOARD_SPI_FLASH) + case MV_SPI_FLASH: + sflash_print_info(&sflash); + break; +#endif + + default: + printf("Unknown flash type on selected bank!\n"); + } + + return; +} + +/*----------------------------------------------------------------------- + */ + + + +int +mv_flash_erase (flash_info_t *info, int s_first, int s_last) +{ + MV_U32 i,s; + MV_STATUS ret; +#if defined (MV_INCLUDE_INTEG_MFLASH) + MV_BOOL mvMFstatus; +#endif +#if defined (MV_INC_BOARD_SPI_FLASH) + MV_SFLASH_WP_REGION mvSFstatus; +#endif + + DB(printf("%s: sectors %d - %d \n", __FUNCTION__, s_first, s_last)); + s = getMvFlashInfoNum(info); + if(s >= CFG_MAX_FLASH_BANKS) + { + DB(printf("%s: illegal mvFlashInfo \n", __FUNCTION__)); + return 1; + } + printf("\n"); + + for(i = s_first; i <= s_last; i++) + { + switch(mvFlashTypeFromIndexGet(s)) + { +#if defined (MV_INC_BOARD_NOR_FLASH) + case MV_NOR_FLASH: + DB(printf("%s: calling mvFlashSecErase sector %d, base=%x, sec=%x\n", __FUNCTION__, i,mvFlashInfo[s].baseAddr, mvFlashInfo[s].sector[i].baseOffs)); + ret = mvFlashSecErase(&mvFlashInfo[s],i); + break; +#endif + +#if defined (MV_INCLUDE_INTEG_MFLASH) + case MV_MARVELL_FLASH: + DB(printf("%s: calling mvMFlashSecErase sector %d, base=%x, sec=%x\n", __FUNCTION__, i,mvFlashInfo[s].baseAddr, mvFlashInfo[s].sector[i].baseOffs)); + /* Check protect on/off */ + mvMFlashWriteProtectGet(&mflash,&mvMFstatus); + if (mvMFstatus == MV_TRUE) + { + ret = MV_FAIL; + break; + } + ret = mvMFlashSecErase(&mflash, i); + break; +#endif + +#if defined (MV_INC_BOARD_SPI_FLASH) + case MV_SPI_FLASH: + DB(printf("%s: calling mvSFlashSectorErase sector %d, base=%x, sec=%x\n", __FUNCTION__, i,mvFlashInfo[s].baseAddr, mvFlashInfo[s].sector[i].baseOffs)); + /* Check protect on/off */ + + mvSFlashWpRegionGet (&sflash, &mvSFstatus); + if (mvSFstatus == MV_WP_ALL) + { + ret = MV_FAIL; + break; + } + ret = mvSFlashSectorErase(&sflash, i); + break; +#endif + + default: + mv_flash_print_info(info); + return 1; + } + + if(ret != MV_OK) + { + printf("Erase fail!\n"); + mv_flash_print_info(info); + return 1; + } + + putc ('.'); + if (((i+1) % (NL_HASHES_PER_LINE)) == 0) + { + puts ("\n"); + } + } + puts("\n"); + + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int +mv_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + unsigned int s = 0; + + s = getMvFlashInfoNum(info); + if(s >= CFG_MAX_FLASH_BANKS) + { + DB(printf("mv_write_buff illegal mvFlashInfo \n")); + return 1; + } + + switch(mvFlashTypeFromIndexGet(s)) + { +#if defined (MV_INC_BOARD_NOR_FLASH) + char *env; + + case MV_NOR_FLASH: + env = getenv("enaFlashBuf"); + if(( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) )) + { + if( mvFlashBlockWr(&mvFlashInfo[s],addr - mvFlashBaseAddrGet(&mvFlashInfo[s]) ,cnt,src) != cnt) + return 1; /* Write was not completed */ + } + else + { + if( mvFlashBlockUnbufWr(&mvFlashInfo[s],addr - mvFlashBaseAddrGet(&mvFlashInfo[s]) ,cnt,src) != cnt) + return 1; /* Write was not completed */ + } + break; +#endif + +#if defined (MV_INCLUDE_INTEG_MFLASH) + case MV_MARVELL_FLASH: + if (mvMFlashBlockWr(&mflash, (addr - mflash.baseAddr), cnt, src, MV_FALSE /* no compare */) != MV_OK) + return 1; /* Write was not completed */ + break; +#endif + +#if defined (MV_INC_BOARD_SPI_FLASH) + case MV_SPI_FLASH: + if (mvSFlashBlockWr(&sflash, (addr - sflash.baseAddr), src, cnt) != MV_OK) + return 1; /* Write was not completed */ + break; +#endif + + default: + return 1; + } + + return 0; /* write completed succefully */ +} + +#if (defined (MV_INCLUDE_INTEG_MFLASH)|| defined (MV_INC_BOARD_SPI_FLASH)) +/******************************************************************************* +* rangeStrDecode - Decode a range string into 2 integers +* +* DESCRIPTION: +* Decode a string indicating a range like M-N into 2 integers M and N. +* +********************************************************************************/ +static int rangeStrDecode (char * str, int * first, int * last, unsigned int sectNum) +{ + char * sl, * ep; + + if ((sl = strchr (str, '-')) == NULL) /* a single sector */ + { + /* only a single bank is specified */ + *first = simple_strtoul (str, &ep, 10); + if ((ep == str) || (*ep != '\0') || (*first >= sectNum) || (*first < 0)) + return -1; + + *last = *first; + return 0; + } + else /* we have a complete range M-N */ + { + *sl++ = '\0'; + *first = simple_strtoul (str, &ep, 10); + if ((ep == str) || (*ep != '\0') || (*first >= sectNum) || (*first < 0)) + return -1; + + *last = simple_strtoul (sl, &ep, 10); + if ((ep == str) || (*ep != '\0') || (*last >= sectNum) || (*last < 0)) + return -1; + } + + if (*first > *last) + return -1; + + return 0; +} +#endif /* (defined (MV_INCLUDE_INTEG_MFLASH)|| defined (MV_INC_BOARD_SPI_FLASH)) */ + +/*#############################################################################*/ +/*#############################################################################*/ +/*###################### MFLASH COMMANDS #############################*/ +/*#############################################################################*/ +/*#############################################################################*/ + +#if defined (MV_INCLUDE_INTEG_MFLASH) +/******************************************************************************* +* mflash_init - Detect and Initialize the Integrated Marvell Flash +* +* DESCRIPTION: +* Try to detect the Marvell Flash integrated in the SOC. Based on the +* model detected, determine the flash size +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +unsigned long mflash_init (MV_MFLASH_INFO * mflInfo) +{ + /* based on the SPI mode try to detect the Mflash device interface type */ + if (mvCtrlSpiBusModeDetect() == MV_SPI_CONN_TO_MFLASH) + mflInfo->ifMode = MV_MFLASH_SPI; + else + mflInfo->ifMode = MV_MFLASH_PARALLEL; + + /* Try to detect the flash and initialize it over the IF deteced */ + if (mvMFlashInit(mflInfo) != MV_OK) + { + printf("%s ERROR: MFlash init failed\n", __FUNCTION__); + return 0; + } + + return (mflInfo->sectorSize * mflInfo->sectorNumber); +} + +/******************************************************************************* +* mflash_print_info - Print the Marvell flash info +* +* DESCRIPTION: +* Print the flash information of the specified instance +* +* INPUT: +* pInfo: pointer to the instance flash information structure. +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +void mflash_print_info (MV_MFLASH_INFO * pInfo) +{ + MV_U32 manf = 0; + MV_U16 dev = 0; + MV_BOOL wp; + + printf("\nFlash Base Address : 0x%08x",pInfo->baseAddr); + + if (pInfo->ifMode == MV_MFLASH_SPI) + printf("\nFlash Mode : SPI"); + else if (pInfo->ifMode == MV_MFLASH_PARALLEL) + printf("\nFlash Mode : Parallel"); + else + printf("\nFlash Mode : Unknown"); + + if (pInfo->flashModel != 0) + printf("\nFlash Model : SUNOL %d",(MV_U32)pInfo->flashModel); + else + printf("\nFlash Model : Unknown"); + + printf("\nSector Size : %dK", (pInfo->sectorSize / 1024)); + printf("\nNumber of sectors : %d", pInfo->sectorNumber); + + /* Get the Flash ID from the chip */ + if (mvMFlashIdGet(pInfo, &manf, &dev) != MV_OK) + { + printf("\n\nFailed to get the Manufacturer and Device IDs!\n"); + return; + } + + /* Get the WP status from the chip */ + if (mvMFlashWriteProtectGet(pInfo, &wp) != MV_OK) + { + printf("\n\nFailed to get the WP status!\n"); + return; + } + + printf("\nManufacturer ID : %08x", manf); + printf("\nDevice ID : %03x", (dev >> 4)); + printf("\nDevice Revision : %01x", (dev & 0xF)); + if (wp) + printf("\nWrite Protection : Enabled"); + else + printf("\nWrite Protection : Disabled"); + + printf("\n\n"); + +} + +/******************************************************************************* +* mflash_erase - Erase a set of sectors +* +* DESCRIPTION: +* Erase a set of sectors in the main flash region. +* +* INPUT: +* pInfo: pointer to the instance flash information structure. +* s_first: first sector to erase. +* s_last: last sector to erase. +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +int mflash_erase (MV_MFLASH_INFO *pInfo, MV_U32 s_first, MV_U32 s_last) +{ + MV_U32 i; + + for (i=s_first; i<=s_last; i++) + { + /* perform the erase in serial mode */ + if (mvMFlashSecErase(pInfo, i) != MV_OK) + return 1; + } + + return 0; +} + +/******************************************************************************* +* mflash_cmd - mflash command implimentation +* +* DESCRIPTION: +* parse and decode the mflash command +* +* INPUT: +* cmdtp: command table pointer +* flag: flags +* argc: command argument count +* argv: command argument vector +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +*******************************************************************************/ +int mflash_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int first, last; + MV_U32 source, offset, size, dest; + MV_BOOL verify; + char * cp; + + if (mFlashBanksNum < 1) + { + printf ("No Marvell Flash detected!\n"); + return 1; + } + + if (argc < 2) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[1], "info") == 0) + { + /* check that we have the correct number of parameters */ + if (argc != 2) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + mflash_print_info(&mflash); + } + else if (strcmp(argv[1], "protect") == 0) + { + /* check that we have the correct number of parameters */ + if (argc != 3) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[2], "on") == 0) /* the whole chip */ + { + if (mvMFlashWriteProtectSet(&mflash, MV_TRUE) != 0) + printf("\nFailed to enable write protection!\n"); + } + else if (strcmp(argv[2], "off") == 0) /* the whole chip */ + { + if (mvMFlashWriteProtectSet(&mflash, MV_FALSE) != 0) + printf("\nFailed to disable write protection!\n"); + } + else + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + } + else if (strcmp(argv[1], "sector") == 0) + { + MV_U32 i,j; + + /* check that we have the correct number of parameters */ + if (argc != 3) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[2], "small") == 0) /* the whole chip */ + { + if (mvMFlashSectorSizeSet(&mflash, 0x1000) != 0) + { + printf("\nFailed to enable write protection!\n"); + return 1; + } + } + else if (strcmp(argv[2], "large") == 0) /* the whole chip */ + { + if (mvMFlashSectorSizeSet(&mflash, 0x8000) != 0) + { + printf("\nFailed to disable write protection!\n"); + return 1; + } + } + else + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Find the Mflash entry and update the sector count and protection status */ + for (i=0; iusage); + return 1; + } + + if (strcmp(argv[2], "chip") == 0) /* the whole chip */ + { + if (mvMFlashChipErase(&mflash) != 0) + printf("\nFailed to erase the whole MFlash chip.\n", first, last); + } + else if (strcmp(argv[2], "main") == 0) /* only the main region */ + { + if (mvMFlashMainErase(&mflash) != 0) + printf("\nFailed to erase the main region.\n", first, last); + } + else if (strcmp(argv[2], "info") == 0) /* ony the information region */ + { + if (mvMFlashInfErase(&mflash) != 0) + printf("\nFailed to erase the information region\n", first, last); + } + else /* check if a range of sectors is specified */ + { + if (rangeStrDecode(argv[2], &first, &last, mflash.sectorNumber) == 0) + { + if (mflash_erase(&mflash, first, last) != 0) + printf("\nFailed to erase sectors %d-%d\n", first, last); + } + else + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + } + } + else if (strcmp(argv[1], "read") == 0) + { + /* check that we have the correct number of parameters */ + if (argc != 6) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + offset = simple_strtoul (argv[3], &cp, 16); + if ((cp == argv[3]) || (*cp != '\0') || (offset < 0)) + { + printf ("Invalid offset."); + return 1; + } + + dest = simple_strtoul (argv[4], &cp, 16); + if ((cp == argv[4]) || (*cp != '\0') || (size < 0)) + { + printf ("Invalid dest."); + return 1; + } + + size = simple_strtoul (argv[5], &cp, 16); + if ((cp == argv[5]) || (*cp != '\0') || (size < 0)) + { + printf ("Invalid size."); + return 1; + } + + if (strcmp(argv[2], "main") == 0) /* ony the information region */ + { + if (mvMFlashBlockRd(&mflash, offset, size, (MV_U8*) dest) != MV_OK) + printf ("Failed to read from the MFlash main region!\n"); + } + else if (strcmp(argv[2], "info") == 0) /* ony the information region */ + { + if (mvMFlashBlockInfRd(&mflash, offset, size, (MV_U8*) dest) != MV_OK) + printf ("Failed to read from the MFlash information region!\n"); + } + else + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + } + else if (strcmp(argv[1], "write") == 0) + { + /* check that we have the correct number of parameters */ + if ((argc != 6) && (argc != 7)) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + source = simple_strtoul (argv[3], &cp, 16); + if ((cp == argv[3]) || (*cp != '\0') || (source < 0)) + { + printf ("Invalid size!\n"); + return 1; + } + + offset = simple_strtoul (argv[4], &cp, 16); + if ((cp == argv[4]) || (*cp != '\0') || (offset < 0)) + { + printf ("Invalid offset!\n"); + return 1; + } + size = simple_strtoul (argv[5], &cp, 16); + if ((cp == argv[5]) || (*cp != '\0') || (size < 0)) + { + printf ("Invalid size!\n"); + return 1; + } + + /* check if the verify flag was used */ + if (argc == 7) + { + if (strcmp(argv[6], "verify") != 0) + { + printf("Invalid verify flag!\n"); + return 1; + } + + verify = MV_TRUE; + } + else + verify = MV_FALSE; + + if (strcmp(argv[2], "main") == 0) /* ony the information region */ + { + if (mvMFlashBlockWr(&mflash,offset, size, (MV_U8*) source, verify) != MV_OK) + { + printf ("Failed to write to the MFlash main region!\n"); + return 1; + } + } + else if (strcmp(argv[2], "info") == 0) /* ony the information region */ + { + if (mvMFlashInfBlockWr(&mflash,offset, size, (MV_U8*) source, verify) != MV_OK) + { + printf ("Failed to write to the MFlash information region!\n"); + return 1; + } + } + else + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + } + else + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return 1; +} + +/*U_BOOT_CMD(name,maxargs,rep,cmd,usage,help)*/ +U_BOOT_CMD( + mflash, 8, 1, mflash_cmd, + "mflash\t- read, write or erase the Marvell Flash.\n", + "info\n - Retreive the Marvell flash infomation.\n" + "mflash protect \n - Enable or disable write protect over the whole MFlash chip.\n" + "mflash sector \n - Set the sector size to small (4K).\n" + "mflash erase \n - Erase the whole chip, main or information region.\n" + "mflash erase SF[-SL]\n - Erase (set back to 0xFF) sectors SF-SL in main region.\n" + "mflash read
offset dest size\n - Read data from the main or info region into the destination address.\n" + "mflash write
source offset size [verify]\n - Write a buffer into the main or information region.\n" +); +#endif /* #if defined (MV_INCLUDE_INTEG_MFLASH) */ + + + +/*#############################################################################*/ +/*#############################################################################*/ +/*###################### SFLASH COMMANDS #############################*/ +/*#############################################################################*/ +/*#############################################################################*/ + +#if defined (MV_INC_BOARD_SPI_FLASH) +/******************************************************************************* +* sflash_init - Detect and Initialize an external SPI flash device +* +* DESCRIPTION: +* Try to detect the SPI Flash. Based on the model detected, determine +* the flash size. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +unsigned long sflash_init (MV_SFLASH_INFO * sflInfo) +{ +#if (defined (MV_INCLUDE_SPI) && defined (MV_INCLUDE_INTEG_MFLASH)) + /* First check that SIP mode is configured */ + if (mvCtrlSpiBusModeDetect() != MV_SPI_CONN_TO_EXT_FLASH) + { + mvOsPrintf("%s ERROR: SPI interface is not routed to external SPI flash!\n", __FUNCTION__); + return 0; + } +#endif + + /* Try to detect the flash and initialize it over SPI */ + if (mvSFlashInit(sflInfo) != MV_OK) + { + mvOsPrintf("%s ERROR: SFlash init falied!\n", __FUNCTION__); + return 0; + } + + /* return the size of the detected SFLash */ + return (mvSFlashSizeGet(sflInfo)); +} + +/******************************************************************************* +* sflash_print_info - Print the SPI flash info +* +* DESCRIPTION: +* Print the flash information of the specified instance +* +* INPUT: +* pInfo: pointer to the instance flash information structure. +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +void sflash_print_info (MV_SFLASH_INFO * pInfo) +{ + MV_SFLASH_WP_REGION wp; + + printf("\nFlash Base Address : 0x%08x", pInfo->baseAddr); + printf("\nFlash Model : %s", mvSFlashModelGet(pInfo)); + printf("\nManufacturer ID : 0x%02x", pInfo->manufacturerId); + printf("\nDevice Id : 0x%04x", pInfo->deviceId); + printf("\nSector Size : %dK", (pInfo->sectorSize / 1024)); + printf("\nNumber of sectors : %d", pInfo->sectorNumber); + printf("\nPage Size : %d", pInfo->pageSize); + + if (mvSFlashWpRegionGet(pInfo, &wp) != MV_OK) + { + DB(mvOsPrintf("%s WARNING: Failed to get write protect mode!\n", __FUNCTION__);) + printf("\nWrite Protection : UNKNOWN"); + } + else + { + switch (wp) + { + case MV_WP_NONE: + printf("\nWrite Protection : Off"); + break; + case MV_WP_UPR_1OF64: + printf("\nWrite Protection : Upper 1 of 64"); + break; + case MV_WP_UPR_1OF32: + printf("\nWrite Protection : Upper 1 of 32"); + break; + case MV_WP_UPR_1OF16: + printf("\nWrite Protection : Upper 1 of 16"); + break; + case MV_WP_UPR_1OF8: + printf("\nWrite Protection : Upper 1 of 8"); + break; + case MV_WP_UPR_1OF4: + printf("\nWrite Protection : Upper 1 of 4"); + break; + case MV_WP_UPR_1OF2: + printf("\nWrite Protection : Upper 1 of 2"); + break; + case MV_WP_ALL: + printf("\nWrite Protection : All"); + break; + default: + DB(mvOsPrintf("%s WARNING: Invalid Write protect mode!\n", __FUNCTION__);) + printf("\nWrite Protection : UNKNOWN"); + break; + } + } + + printf("\n\n"); +} + +/******************************************************************************* +* sflash_erase - Erase a set of sectors +* +* DESCRIPTION: +* Erase a set of sectors in the SPI flash +* +* INPUT: +* pInfo: pointer to the instance flash information structure. +* s_first: first sector to erase. +* s_last: last sector to erase. +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +int sflash_erase (MV_SFLASH_INFO *pInfo, MV_U32 s_first, MV_U32 s_last) +{ + MV_U32 i; + + for (i=s_first; i<=s_last; i++) + { + /* perform the erase in serial mode */ + if (mvSFlashSectorErase(pInfo, i) != MV_OK) + { + DB(mvOsPrintf("%s WARNING: Failed to erase sector %d in SFlash %s!\n", \ + __FUNCTION__, i, mvSFlashModelGet(pInfo));) + return 1; + } + } + + return 0; +} + +/***********************************************************************/ +/************************ U-Boot Commands ******************************/ +/***********************************************************************/ + +/******************************************************************************* +* sflash_cmd - sflash command implimentation +* +* DESCRIPTION: +* parse and decode the sflash command +* +* INPUT: +* cmdtp: command table pointer +* flag: flags +* argc: command argument count +* argv: command argument vector +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +*******************************************************************************/ +int sflash_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int first, last; + MV_U32 source, offset, size, dest; + char * cp; + + if (sFlashBanksNum < 1) + { + printf ("No SPI Flash detected!\n"); + return 1; + } + + if (argc < 2) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[1], "info") == 0) + { + /* check that we have the correct number of parameters */ + if (argc != 2) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + sflash_print_info(&sflash); + } + else if (strcmp(argv[1], "protect") == 0) + { + /* check that we have the correct number of parameters */ + if (argc != 3) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[2], "off") == 0) + { + if (mvSFlashWpRegionSet(&sflash, MV_WP_NONE) != 0) + printf("\nFailed to set the write protection to NONE.\n"); + } + else if (strcmp(argv[2], "on") == 0) + { + if (mvSFlashWpRegionSet(&sflash, MV_WP_ALL) != 0) + printf("\nFailed to set the write protection to ALL.\n"); + } + else + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + } + else if (strcmp(argv[1], "erase") == 0) /* erase command */ + { + /* check that we have the correct number of parameters */ + if (argc != 3) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[2], "all") == 0) /* the whole chip */ + { + if (mvSFlashChipErase(&sflash) != 0) + printf("\nFailed to erase the whole SPI flash chip.\n"); + } + else /* check if a range of sectors is specified */ + { + if (rangeStrDecode(argv[2], &first, &last, sflash.sectorNumber) == 0) + { + if (sflash_erase(&sflash, first, last) != 0) + printf("\nFailed to erase sectors %d-%d\n", first, last); + } + else + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + } + } + else if (strcmp(argv[1], "read") == 0) + { + /* check that we have the correct number of parameters */ + if (argc != 5) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + offset = simple_strtoul (argv[2], &cp, 16); + if ((cp == argv[2]) || (*cp != '\0') || (offset < 0)) + { + printf ("Invalid offset."); + return 1; + } + + dest = simple_strtoul (argv[3], &cp, 16); + if ((cp == argv[3]) || (*cp != '\0') || (size < 0)) + { + printf ("Invalid size."); + return 1; + } + + size = simple_strtoul (argv[4], &cp, 16); + if ((cp == argv[4]) || (*cp != '\0') || (size < 0)) + { + printf ("Invalid size."); + return 1; + } + + if (mvSFlashBlockRd(&sflash, offset, (MV_U8*)dest, size) != MV_OK) + { + printf ("Failed to read from the SPI flash!\n"); + return 1; + } + } + else if (strcmp(argv[1], "write") == 0) + { + /* check that we have the correct number of parameters */ + if (argc != 5) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + source = simple_strtoul (argv[2], &cp, 16); + if ((cp == argv[2]) || (*cp != '\0') || (source < 0)) + { + printf ("Invalid size."); + return 1; + } + + offset = simple_strtoul (argv[3], &cp, 16); + if ((cp == argv[3]) || (*cp != '\0') || (offset < 0)) + { + printf ("Invalid offset."); + return 1; + } + size = simple_strtoul (argv[4], &cp, 16); + if ((cp == argv[4]) || (*cp != '\0') || (size < 0)) + { + printf ("Invalid size!\n"); + return 1; + } + + if (mvSFlashBlockWr(&sflash, offset, (MV_U8*) source, size) != MV_OK) + { + printf ("Failed to write to the SPI flash!\n"); + return 1; + } + } + else + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return 1; +} + +/*U_BOOT_CMD(name,maxargs,rep,cmd,usage,help)*/ +U_BOOT_CMD( + sflash, 6, 1, sflash_cmd, + "sflash\t- read, write or erase the external SPI Flash.\n", + "info\n - Retreive the SPI flash infomation.\n" + "sflash protect \n - Enable or diasble write protection over the whole SPI flash.\n" + "sflash erase all \n - Erase (set back to 0xFF) the whole chip.\n" + "sflash erase SF[-SL]\n - Erase (set back to 0xFF) sectors SF-SL.\n" + "sflash read offset dest size\n - Read data from the flash into the destination address.\n" + "sflash write source offset size\n - Program a buffer from the source address into the flash offset (size in bytes).\n" +); +#endif +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FLASH) */ + diff --git a/board/mv_feroceon/USP/mv_fs.c b/board/mv_feroceon/USP/mv_fs.c new file mode 100644 index 0000000..f0149c0 --- /dev/null +++ b/board/mv_feroceon/USP/mv_fs.c @@ -0,0 +1,2962 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +#include +#include +#include +#include +#include + +#include "mvSysHwConfig.h" +#if defined(MV_INCLUDE_MONT_EXT) && defined (MV_INCLUDE_MONT_FFS) + +#include "mvTypes.h" +#include "norflash/mvFlash.h" +#include "mvCpuIf.h" +/*#include "mv_mon.h"*/ +#include "mv_fs.h" + +#if CONFIG_COMMANDS & CFG_CMD_BSP + +/* #define DEBUG */ +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_FLASH_INFO *mvFlashInfo; + +/* File system data base variables */ +/* FAT signature */ +char FATsignature[] = "FAT024136764000"; +unsigned int initializationFlag; +unsigned int mvFSTimeStamp; +unsigned int operationMode; +unsigned int mvFSOffset; +unsigned int mvFSTopOffset; +unsigned int nextFreeBlock; +FS_FILE_TABLE_ENTRY mvFSEntries[FS_MAX_NUM_OF_ENTRIES]; +FS_FILE_CACHE_BLOCK mvFSCacheBlocks[FS_NUMBER_OF_BLOCKS_FOR_CACHE]; + +/* Functions */ +extern void d_i_cache_clean(unsigned int Address, unsigned int byteCount); +extern int load_net(MV_U32 *loadnet_addr); +extern unsigned int VIRTUAL_TO_PHY(unsigned int address); +extern void mv_go(unsigned long addr,int argc, char *argv[]); +extern MV_FLASH_INFO* getMvFlashInfo(int index); + +/******************************************************************************* +* mvFSFormat - Formats the mvFlash mvMemory for file system usage. +* +* DESCRIPTION: +* This function formats the flash memory for file system usage. It +* allocates 10 blocks for FAT in a form of a linked list and write the +* signature (signature defind in mvFS.h) in each FAT header block +* within the flash. The format starts from the ‘offset’ parameter value +* within the flash if the offset is aligned with one of the flash's +* sectors start address, otherwise it will be incremented to the nearest +* sector start address and then perform the format.The format can be +* accomplished in 2 modes as described below. +* +* INPUT: +* offset - Starting point of the format within the flash. +* +* mode - Defines whether an erasing counter will be enabled or not . +* When erasing counter is enabled , the function will allocate one +* block at the end of each sector to act as a counter for the +* number of erasures of that sector . The possible values : +* - ENABLE_ERASING_COUNTER +* - NO_ERASING_COUNTER +* OUTPUT: +* Initialized flash for file system usage. +* +* RETURN: +* The actual offset (after alignment to the nearest sector start address) +* or: +* FLASH_MEMORY_NOT_PRESENT - if no flash memory present . +* VALID_FILE_SYS_IN_LOWER_OFFSET - if a valid file system residing in a +* lower offset. +* +*******************************************************************************/ +unsigned int mvFSFormat(unsigned int offset,unsigned int mode) +{ + unsigned int i,sectorSize,tempOffset,limit,previousCount; + unsigned int erasingCounterWasEnabled = 0,status; + + DB(printf("start mvFSFormat\n")); + DB(printf("Flash base addr 0x%x\n",mvFlashInfo->baseAddr)); + + if(offset != mvFlashSecOffsGet(mvFlashInfo, mvFlashInWhichSec(mvFlashInfo, offset))) + { + offset = mvFlashSecOffsGet(mvFlashInfo, mvFlashInWhichSec(mvFlashInfo, offset) + 1); + } + if(offset != 0xffffffff) + { + if(mode == FS_ENABLE_ERASING_COUNTER) + { + tempOffset = mvFSSearchForSignature(); + if(tempOffset != FS_NO_VALID_FAT_STRING) + { + if(tempOffset < offset) + return FS_VALID_FILE_SYS_IN_LOWER_OFFSET; + if(mvFlash32Rd(mvFlashInfo, tempOffset + FS_ERSAING_COUNTER_FLAG_OFFSET) + == FS_ENABLE_ERASING_COUNTER) + { + erasingCounterWasEnabled = 1; + } + } + } + tempOffset = offset; + /* Eraseing the sectors dedicated for the file system */ + while(mvFlashInWhichSec(mvFlashInfo, offset) != 0xffffffff) + { + if(mode == FS_NO_ERASING_COUNTER) + { + DB(printf("mvFSFormat - mode = FS_NO_ERASING_COUNTER\n")); + i = mvFlashInWhichSec(mvFlashInfo, offset); + sectorSize = mvFlashSecSizeGet(mvFlashInfo, i); + limit = offset + sectorSize; + for(; offset < limit ; offset+=4) + { + if(mvFlash32Rd(mvFlashInfo, offset) != 0xffffffff) + { + DB(printf("mvFSFormat - Erase flash sector 0x%x\n", mvFlashInWhichSec(mvFlashInfo, offset))); + status = mvFlashSecErase(mvFlashInfo, mvFlashInWhichSec(mvFlashInfo, offset)); + if (status != MV_OK) + { + printf("mvFlashSecErase - FAIL!\n"); + return status; + } + + break; + } + } + offset += sectorSize; + } + else /* mode == FS_ENABLE_ERASING_COUNTER */ + { + DB(printf("mvFSFormat - mode = FS_ENABLE_ERASING_COUNTER\n")); + i = mvFlashInWhichSec(mvFlashInfo, offset); + sectorSize = mvFlashSecSizeGet(mvFlashInfo, i); + limit = offset + sectorSize - FS_BLOCK_SIZE; + previousCount = mvFlash32Rd(mvFlashInfo, limit); + for(; offset <= (limit + 4) ; offset+=4) + { + if(mvFlash32Rd(mvFlashInfo, offset) != 0xffffffff) + { + mvFlashSecErase(mvFlashInfo, mvFlashInWhichSec(mvFlashInfo, offset)); + if(erasingCounterWasEnabled) + { + /* Increment the counter */ + mvFlash32Wr(mvFlashInfo, limit, previousCount + 1); + mvFlash8Wr(mvFlashInfo, limit+FS_BLOCK_STATUS_FLAG_OFFSET, + FS_BLOCK_USED_FOR_ERASING_COUNTER); + } + break; + } + } + if(!erasingCounterWasEnabled) + { + /* Initialize the counter */ + mvFlash32Wr(mvFlashInfo, limit, 0); + mvFlash8Wr(mvFlashInfo, limit + FS_BLOCK_STATUS_FLAG_OFFSET, + FS_BLOCK_USED_FOR_ERASING_COUNTER); + } + offset = limit + FS_BLOCK_SIZE; + } + } + /* Fill the FAT's header */ + offset = tempOffset; + /* Update the status flag */ + mvFlash8Wr(mvFlashInfo, offset + FS_BLOCK_STATUS_FLAG_OFFSET,FS_FAT_BLOCK); + /* Write the FAT's signature */ + mvFlashBlockWr(mvFlashInfo, offset + FS_SIGNATURE_OFFSET, FS_FAT_SIGNATURE_SIZE, + (MV_U8 *)FATsignature); + /* Check if we were able to burn the mvFlash */ + for(i = 0 ; i < FS_FAT_SIGNATURE_SIZE ; i++) + { + if(mvFlash8Rd(mvFlashInfo, offset + FS_SIGNATURE_OFFSET + i) != FATsignature[i]) + return FS_FLASH_MEMORY_NOT_PRESENT; + } + if(mode == FS_ENABLE_ERASING_COUNTER) + { + mvFlash32Wr(mvFlashInfo, offset + FS_ERSAING_COUNTER_FLAG_OFFSET, + FS_ENABLE_ERASING_COUNTER); + } + mvFlash32Wr(mvFlashInfo, offset, offset + FS_BLOCK_SIZE); + /* Alocate 9 more blocks for the FAT */ + for(i = 1 ; i < (FS_MAX_NUM_OF_FAT_BLOCKS - 1) ; i++) + { + /* Next block pointer */ + mvFlash32Wr(mvFlashInfo, offset+(FS_BLOCK_SIZE*(i)),offset+ + (FS_BLOCK_SIZE*(i+1))); + /* Flag */ + mvFlash8Wr(mvFlashInfo, offset+(FS_BLOCK_SIZE*(i)) + + FS_BLOCK_STATUS_FLAG_OFFSET, FS_FAT_BLOCK); + } + /* The last block's next pointer is 0xffffffff since it is the last */ + mvFlash8Wr(mvFlashInfo, offset + (FS_BLOCK_SIZE * i) + + FS_BLOCK_STATUS_FLAG_OFFSET, FS_FAT_BLOCK); + } + return offset; +} + +/******************************************************************************* +* mvFSInit - Initializes the flash system's data base variables. +* +* DESCRIPTION: +* This function initializes the flash system's database variables residing +* in the systems dynamic memory (SDRAM) . It searches within the flash +* memory from the begining, for the first occurrence of a valid signature. +* If found, a valid file system is assumed to be exist starting from the +* sector the signature was found and all the database variables will than +* be initialized ,otherwise it returns NO_VALID_FAT_STRING or +* OFFSET_OUT_OF_RANGE to indicate that no valid file system was found +* within the flash .If a valid file system was found ,the function returns +* the number of files within the flash .The ‘mode’ parameter delivered to +* the function is for future needs to support two cache modes(cache mode, +* non - cache mode) and currently this feature is not implemented in this +* current version of this function. +* NOTE!!!!: +* It is a MUST to call this function before any attempt to use file-system +* driver. +* INPUT: +* mode - For future needs to support cache or non-cache modes (currently +* not implemented). +* +* OUTPUT: +* Initialized data base for the file system. +* +* RETURN: +* Number of files currently on the system or: +* NO_VALID_FAT_STRING - if no file system was found (Try to use +* ‘fileSysFormat’ function in this case). +* OFFSET_OUT_OF_RANGE - if there was an error finding a signature found is +* SYSTEM_ALREADY_INITIALIZED. +* +*******************************************************************************/ +unsigned int mvFSInit(unsigned int mode) +{ + /* Initially we are not going to support the FS_ENABLE_CACHE mode */ + unsigned int offset = 0,i = 0,numOfFiles,nextBlockOffset; + unsigned int fileEntryOffset,tempOffset; + + /* set the global flash info structure */ + mvFlashInfo = getMvFlashInfo(MAIN_FLASH_INDEX); + + /* Seek for the FAT signature */ + offset = mvFSSearchForSignature(); + if(offset == FS_NO_VALID_FAT_STRING) + return FS_NO_VALID_FAT_STRING; + if(offset >= mvFlashSizeGet(mvFlashInfo)) + return FS_OFFSET_OUT_OF_RANGE; + mvFSTopOffset = mvFlashSizeGet(mvFlashInfo); + + /* Check if the system is already initialized , if so we will not + re-initialize */ + if(initializationFlag == FS_FILE_SYSTEM_INITIALIZED) + return FS_SYSTEM_ALREADY_INITIALIZED; + + /* We found the FAT's signature, now we need to initialize the file system + data base and count the number of files */ + mvFSTimeStamp = 0; + operationMode = mode; + mvFSOffset = offset; + nextFreeBlock = 0xffffffff - FS_BLOCK_SIZE; + /* Initialize the files entries */ + for(i = 0 ; i < FS_MAX_NUM_OF_ENTRIES ; i++) + { + mvFSEntries[i].filePointer = 0; + mvFSEntries[i].statusFlag = FS_FREE_ENTRY; + mvFSEntries[i].mode[0] = '\0'; + mvFSEntries[i].pointerToFAT = 0xffffffff; + mvFSEntries[i].EOFpointer = 0; + } + /* Initialize the cache blocks */ + for(i = 0 ; i < FS_NUMBER_OF_BLOCKS_FOR_CACHE ; i++) + { + mvFSCacheBlocks[i].currentBlockAddress = 0xffffffff; + mvFSCacheBlocks[i].fileHandler = 0; + mvFSCacheBlocks[i].usageCounter = 0; + mvFSCacheBlocks[i].timeStamp = 0; + } + /* Count the number of files currently on the system */ + numOfFiles = 0; + nextBlockOffset = mvFSOffset; + while(nextBlockOffset != 0xffffffff) + { + /* Skip the block's header */ + fileEntryOffset = nextBlockOffset + FS_FAT_HEADER_SIZE; + for(i = 0 ; i < 15 ; i++) + { + if(mvFlash8Rd(mvFlashInfo, fileEntryOffset + FS_ENTRY_STATUS_FLAG_OFFSET) + == FS_ENTRY_IN_USE) + numOfFiles++; + /* If we have files which were not properly closed we need to + to remove them from the system */ + if(mvFlash8Rd(mvFlashInfo, fileEntryOffset + FS_ENTRY_STATUS_FLAG_OFFSET) + == FS_ENTRY_IN_UPDATE) + { + mvFlash8Wr(mvFlashInfo, fileEntryOffset + FS_ENTRY_STATUS_FLAG_OFFSET, + FS_FREE_DIRTY_ENTRY); + /* Free the file's data blocks */ + tempOffset = mvFlash32Rd(mvFlashInfo, fileEntryOffset); + while(tempOffset != 0xffffffff) + { + tempOffset = tempOffset & FS_BLOCK_OFFSET_MASK; + mvFlash8Wr(mvFlashInfo, tempOffset + FS_BLOCK_STATUS_FLAG_OFFSET, + FS_FREE_DIRTY_BLOCK); + tempOffset = mvFlash32Rd(mvFlashInfo, tempOffset); + } + } + /* point to the next entry */ + fileEntryOffset += FS_FAT_FILE_ENTRY_SIZE; + } + nextBlockOffset = mvFlash32Rd(mvFlashInfo, nextBlockOffset); + } + initializationFlag = FS_FILE_SYSTEM_INITIALIZED; + return numOfFiles; +} + +/******************************************************************************* +* mvFSDelete - Deletes a file for the file system. +* +* DESCRIPTION: +* This function deletes a file in the file-system. The function actually +* marks the file's entry status flag as FREE_DIRTY_ENTRY and the file's +* status flag of each data block with the value FREE_DIRTY_BLOCKs to +* indicate that this entery and all the file’s data blocks are no longer +* associated by this file. If the file has valid handles associated with +* it the file will not be deleted . +* NOTE: +* The file system's data base must be initialized by ‘fileSysInit’ +* function before using this function . +* +* INPUT: +* fileName - A string containing the file name. +* +* OUTPUT: +* On success the file will be deleted.. +* +* RETURN: +* On success - The return value will be FS_FILE_DELETED. +* On failure one of the following parameters: +* FS_FILE_NOT_FOUND - if the data base was initialized or file was not +* found. +* FS_FILE_IS_NOT_CLOSED - if the file has valid handles associated with +* it. +*******************************************************************************/ +unsigned int mvFSDelete(char * fileName) +{ + unsigned int fileOffset,numOfHandles,tempOffset; + + /* Check if the file system's data base was initialized */ + if(initializationFlag != FS_FILE_SYSTEM_INITIALIZED) + return FS_FILE_NOT_FOUND; + + if((fileOffset = mvFSFileFind(fileName)) == FS_FILE_NOT_FOUND) + return FS_FILE_NOT_FOUND; + if((numOfHandles = mvFSNumOfHandles(fileName)) == FS_FILE_NOT_FOUND) + return FS_FILE_NOT_FOUND; + if(numOfHandles > 0) + return FS_FILE_IS_NOT_CLOSED; + + mvFlash8Wr(mvFlashInfo, fileOffset + FS_ENTRY_STATUS_FLAG_OFFSET, + FS_FREE_DIRTY_ENTRY); + /* Free the file's data blocks */ + tempOffset = mvFlash32Rd(mvFlashInfo, fileOffset); + while(tempOffset != 0xffffffff) + { + tempOffset = tempOffset & FS_BLOCK_OFFSET_MASK; + mvFlash8Wr(mvFlashInfo, tempOffset + FS_BLOCK_STATUS_FLAG_OFFSET, + FS_FREE_DIRTY_BLOCK); + tempOffset = mvFlash32Rd(mvFlashInfo, tempOffset); + } + return FS_FILE_DELETED; +} + +/******************************************************************************* +* mvFSFileFind - Check if a file exists in the file system. +* +* DESCRIPTION: +* This function checks if the file ‘fileName’ exists in the file system. +* The function will search for the file with the matching name and +* extension and if found , the file's entry offset in the FAT is returned. +* NOTE: +* The file system's data base must be initialized by ‘fileSysInit’ +* function before using this function . +* +* INPUT: +* fileName - A string containing the file name. +* +* OUTPUT: +* None. +* +* RETURN: +* FILE_NOT_FOUND or the file's entery offset in the FAT. +* +*******************************************************************************/ +unsigned int mvFSFileFind(char * fileName) +{ + unsigned int nextBlockOffset,fileEntryOffset,index; + char tempString[20]; + + /* Check if the file system's data base was initialized */ + if(initializationFlag != FS_FILE_SYSTEM_INITIALIZED) + return FS_FILE_NOT_FOUND; + nextBlockOffset = mvFSOffset; + while(nextBlockOffset != 0xffffffff) + { + /* Skip the block's header */ + for(fileEntryOffset = nextBlockOffset + FS_FAT_HEADER_SIZE; + fileEntryOffset < (nextBlockOffset + FS_BLOCK_SIZE); + fileEntryOffset += FS_FAT_FILE_ENTRY_SIZE) + { + index = 0; + if(mvFlash8Rd(mvFlashInfo, fileEntryOffset + FS_ENTRY_STATUS_FLAG_OFFSET) + == FS_ENTRY_IN_USE) + { + /* Read the file's name */ + mvFSReadFileNameFromFATentry(fileEntryOffset,tempString); + if(strcmp(tempString,fileName) == 0) return fileEntryOffset; + /* else , try the next entry */ + } + } + nextBlockOffset = mvFlash32Rd(mvFlashInfo, nextBlockOffset); + } + return FS_FILE_NOT_FOUND; +} + +/******************************************************************************* +* mvFSNumOfHandles - Counts the number of handles currently pointing to a file. +* +* DESCRIPTION: +* This function counts the number of handles currently associated to the +* file ‘fileName’.The entry table in the dynamic database is formed from +* an array of FILE_TABLE_ENTRY (structure defined in mvFS.h) and the +* file handler acts as the index of that array . The function counts each +* entry within the array that points to the file ‘fileName’ and return +* that value. +* NOTE: +* The file system's data base must be initialized by ‘fileSysInit’ +* function before using this function . +* +* INPUT: +* fileName - A string containing the file name. +* +* OUTPUT: +* None. +* +* RETURN: +* on success , the Number of handlers currently associated to the file +* ‘fileName’. +* on failure , FS_FILE_NOT_FOUND. +* +*******************************************************************************/ +unsigned int mvFSNumOfHandles(char * fileName) +{ + unsigned int fileEntryOffset,i,numOfHandles; + if((fileEntryOffset = mvFSFileFind(fileName)) == 0xffffffff) + return FS_FILE_NOT_FOUND; + + numOfHandles = 0; + for(i = 0 ; i < FS_MAX_NUM_OF_ENTRIES ; i++) + { + if(fileEntryOffset == mvFSEntries[i].filePointer) + numOfHandles++; + } + return numOfHandles; +} + +/******************************************************************************* +* mvFSSearchForSignature - Searches for the FAT's signature string, if the +* string is found we are assuming a valid file system. +* +* DESCRIPTION: +* This function searches within the flash memory from the begining for the +* first occurrence of a valid signature .If found , it returns the sector +* offset on which the signature first occurred , otherwise it returns +* NO_VALID_FAT_STRING to indicate the flash is not formated , in that case +* you might want to use fileSysformat function. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* The offset of the sector in which the signature was found, +* otherwise FS_NO_VALID_FAT_STRING . +* +*******************************************************************************/ +unsigned int mvFSSearchForSignature(void) +{ + unsigned int offset = 0,i,sectorNumber; + + sectorNumber = mvFlashInWhichSec(mvFlashInfo, offset); + while((offset = mvFlashSecOffsGet(mvFlashInfo, sectorNumber)) != 0xffffffff) + { + for(i = 0 ; i < FS_FAT_SIGNATURE_SIZE ; i++) + { + if(mvFlash8Rd(mvFlashInfo, offset + FS_SIGNATURE_OFFSET + + i) != FATsignature[i]) + break; + } + if(i == FS_FAT_SIGNATURE_SIZE) break; + offset += mvFlashSecSizeGet(mvFlashInfo, sectorNumber); + sectorNumber = mvFlashInWhichSec(mvFlashInfo, offset); + if(sectorNumber == 0xffffffff) return FS_NO_VALID_FAT_STRING; + } + if(offset == 0xffffffff) return FS_NO_VALID_FAT_STRING; + return offset; +} + +/******************************************************************************* +* mvFSOpen - Opens a file for read/write/append. +* +* DESCRIPTION: +* This function opens a file for reading , writing or appending data .The +* function will act differantly upon each mode delivered by the parameter +* ‘mode’. +* NOTE: +* The file system's data base must be initialized by ‘fileSysInit’ +* function before using this function . +* +* INPUT: +* mode - defines on which mode the file will be open .All possible values +* for ‘mode’ parameter are described below: +* +“ "r" - Opens the file for reading only . If the file does not +* exist or cannot be found , the function fails . After the +* file has been found , the function searches for an empty +* entry within the dynamic data base entry table and if it +* found one , it associates the file ‘fileName’ to that +* entry and returns the handler of the file. +* "r+" - Opens the file for both reading and writing. If the file +* does not exist or cannot be found , the function fails. +* After the file has been found , the function searches +* for an empty entry within the dynamic data base entry +* table and if found , it associates the file ‘fileName’ +* to that entry and returns the handler of the file . When +* a file is opened with the “r+” all write operations +* occur at the end of the file. The file pointer can be +* repositioned using fileSysSeek or fileSysRewind , but is +* always moved back to the end of the file before any write +* operation is carried out. Thus ,existing data cannot be +* overwritten. +* "w" - Opens an empty file for writing only. If the file does +* not exist the function will create it, otherwise if the +* given file exists the function will open it but its +* content will be destroyed . On both cases the function +* searches for an empty entry within the dynamic data base +* entry table and if found , it associates the file +* ‘fileName’ to that entry and returns the handler of the +* file . +* "w+" - Opens an empty file for both reading and writing data. If +* the given file exists, its contents is destroyed . When a +* file is opened with the "w+" access type , all write +* operations occur at the end of the file. The file pointer +* can be repositioned using fileSysSeek or fileSysRewind , +* but is always moved back to the end of the file before any +* write operation is carried out. Thus ,existing data cannot +* be overwritten. +* "a+" - Opens a file for reading and appending data. If the given +* file exists ,its contents is destroyed .The appending +* operation includes the removal of the EOF marker before +* new data is written to the file and the EOF marker is +* restored after the writing has completed . When a file is +* opened with the "a+" access type ,all write operations +* occur at the end of the file. The file pointer can be +* repositioned using fileSysSeek or fileSysRewind , but is +* always moved back to the end of the file before any write +* operation is carried out .Thus , existing data cannot be +* overwritten. +* fileName - A string containing the file name. +* +* OUTPUT: +* None. +* +* RETURN: +* File handler on success or FILE_OPEN_ERROR in one of the following +* reasons: +* - File system not initialized. +* - In cases of the modes "r" or "r+" and the file is not found. +* - No free entries in the file system's data base. +* - In modes "w" and w+" if we try to open a file which already exists it +* must be deleted first , an error can occur at the delete function. +* - No more free entries on the flash memory. +* - Not supported mode. +* +*******************************************************************************/ +FS_FILE_HANDLER mvFSOpen(char * fileName,char *mode) +{ + unsigned int fileFAToffset,fh; + + /* Check if the file system's data base was initialized */ + if(initializationFlag != FS_FILE_SYSTEM_INITIALIZED) + { + return FS_FILE_OPEN_ERROR; + } + /* Mode == "r" or "r+" - the file must exist */ + if((mode[0] == 'r') && + (mode[1] == '\0'|| (mode[1] == '+' && mode[2] == '\0'))) + { + fileFAToffset = mvFSFileFind(fileName); + if(fileFAToffset == FS_FILE_NOT_FOUND) + return FS_FILE_OPEN_ERROR; + for(fh = 0 ; fh < FS_MAX_NUM_OF_ENTRIES ; fh++) + { + if(mvFSEntries[fh].statusFlag == FS_FREE_ENTRY) + { + mvFSEntries[fh].statusFlag = FS_ENTRY_IN_USE; + mvFSEntries[fh].filePointer = 0; + mvFSEntries[fh].mode[0] = mode[0]; + mvFSEntries[fh].mode[1] = mode[1]; + mvFSEntries[fh].mode[2] = mode[2]; + mvFSEntries[fh].pointerToFAT = fileFAToffset; + mvFSEntries[fh].EOFpointer = mvFSGetEOFoffset(fileName); + return fh; + } + } + return FS_FILE_OPEN_ERROR; + } + /* Mode == "w" ,"w+" or "a+" */ + if((mode[0] == 'w' || mode[0] == 'a') && + (mode[1] == '\0'||(mode[1] == '+' && mode[2] == '\0'))) + { + /* Check if the file exists on the system */ + fileFAToffset = mvFSFileFind(fileName); + if(fileFAToffset != FS_FILE_NOT_FOUND) + { + if( mode[0] != 'a') + { + if(mvFSDelete(fileName) != FS_FILE_DELETED) + return FS_FILE_OPEN_ERROR; + /* Get a free entry on the FAT */ + fileFAToffset = mvFSGetFreeEntry(); + if(fileFAToffset == FS_NO_FREE_ENTRIES) + return FS_FILE_OPEN_ERROR; + } + } + else + { + /* Get a free entry on the FAT */ + fileFAToffset = mvFSGetFreeEntry(); + if(fileFAToffset == FS_NO_FREE_ENTRIES) + return FS_FILE_OPEN_ERROR; + } + /* Search for a free entry on the file system's data base */ + for(fh = 0 ; fh < FS_MAX_NUM_OF_ENTRIES ; fh++) + { + if(mvFSEntries[fh].statusFlag == FS_FREE_ENTRY) + { + mvFSEntries[fh].statusFlag = FS_ENTRY_IN_USE; + mvFSEntries[fh].filePointer = 0; + mvFSEntries[fh].mode[0] = mode[0]; + mvFSEntries[fh].mode[1] = mode[1]; + mvFSEntries[fh].mode[2] = mode[2]; + mvFSEntries[fh].pointerToFAT= fileFAToffset; + mvFSEntries[fh].EOFpointer = mvFSGetEOFoffset(fileName); + /* Update the entry on the FAT */ + /* Write the file's name */ + mvFSWriteFileNameToFATentry(fileFAToffset,fileName); + /* Update the status flag */ + mvFlash8Wr(mvFlashInfo, fileFAToffset + FS_ENTRY_STATUS_FLAG_OFFSET, + FS_ENTRY_IN_UPDATE); + return fh; + } + } + return FS_FILE_OPEN_ERROR; + } + return FS_FILE_OPEN_ERROR; /* Has no meaning, just for the compiler */ +} + +/******************************************************************************* +* mvFSClose - Closes a file. +* +* DESCRIPTION: +* This function closes a file by removing the file's entry from the file +* system's data base , updating the file's FAT entry and data block's +* status flags and offset . After calling this function , the virtual EOF +* character is created by updating the last block’s 9 bits of the next +* block pointer if data was not appended to that block . If data was +* appended , the offset field of the last block of data will be updated +* (as described at the Introduction ). +* +* INPUT: +* fileName - A string containing the file name. +* +* OUTPUT: +* None. +* +* RETURN: +* The return value can be either FS_FILE_CLOSED on seccess or +* FILE_CLOSE_ERROR in one of the following reasons: +* - If the handler is out of range (bigger or equal to MAX_NUM_OF_ENTRIES +* defind in mvFS.h). +* - If the handler points to an entry with a FREE_ENTRY status. +* +*******************************************************************************/ +unsigned int mvFSClose(FS_FILE_HANDLER fileHandler) +{ + unsigned int FATentryOffset,nextBlockPointer,prevBlockPointer; + unsigned int offset; + + if(fileHandler >= FS_MAX_NUM_OF_ENTRIES) + return FS_FILE_CLOSE_ERROR; + if(mvFSEntries[fileHandler].statusFlag == FS_FREE_ENTRY) + return FS_FILE_CLOSE_ERROR; + /* mode = "r" */ + if(mvFSEntries[fileHandler].mode[0] == 'r' && + mvFSEntries[fileHandler].mode[1] == '\0') + { + mvFSEntries[fileHandler].statusFlag = FS_FREE_ENTRY; + return FS_FILE_CLOSED; + } + /* mode = "r+","w","w+" or "a+" */ + FATentryOffset = mvFSEntries[fileHandler].pointerToFAT; + /* Empty file => next block pointer == 0xFFFFFFFF */ + nextBlockPointer = mvFlash32Rd(mvFlashInfo, FATentryOffset); + if(nextBlockPointer == 0xffffffff) + { + if(mvFlash8Rd(mvFlashInfo, FATentryOffset + FS_ENTRY_STATUS_FLAG_OFFSET) == + FS_ENTRY_IN_UPDATE) + { + /* Update the file's entry status flag */ + mvFlash8Wr(mvFlashInfo, FATentryOffset + FS_ENTRY_STATUS_FLAG_OFFSET, + FS_ENTRY_IN_USE); + } + mvFSEntries[fileHandler].statusFlag = FS_FREE_ENTRY; + return FS_FILE_CLOSED; + } + /* search for the last block */ + prevBlockPointer = FATentryOffset; + while(mvFlash32Rd(mvFlashInfo, nextBlockPointer & + FS_BLOCK_OFFSET_MASK) != 0xffffffff) + { + prevBlockPointer = nextBlockPointer; + nextBlockPointer = mvFlash32Rd(mvFlashInfo, nextBlockPointer & + FS_BLOCK_OFFSET_MASK); + } + + if(mvFlash8Rd(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_STATUS_FLAG_OFFSET) == FS_BLOCK_IN_USE) + { + /* Old block, need to use the offset field */ + if(!((mvFlash8Rd(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_FLAG_OFFSET) == FS_FULL_BLOCK) || + (mvFlash16Rd(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_OFFSET) != 0xffff))) + { + /* File was modified */ + /* We need to update the offset field */ + if(prevBlockPointer == FATentryOffset) + { + offset = mvFlash32Rd(mvFlashInfo, prevBlockPointer) & FS_BLOCK_OFFSET; + } + else + { + offset = mvFlash32Rd(mvFlashInfo, prevBlockPointer & + FS_BLOCK_OFFSET_MASK) & FS_BLOCK_OFFSET; + } + offset = (mvFSEntries[fileHandler].EOFpointer + & FS_BLOCK_OFFSET) - offset; + mvFlash16Wr(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_OFFSET,offset); + } + /* else - File not modified */ + mvFSEntries[fileHandler].statusFlag = FS_FREE_ENTRY; + return FS_FILE_CLOSED; + } + else + { + /* Update the block's status flag */ + mvFlash8Wr(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_STATUS_FLAG_OFFSET,FS_BLOCK_IN_USE); + /* Update the offset at the previous block's next block pointer */ + offset = mvFSEntries[fileHandler].EOFpointer & FS_BLOCK_OFFSET; + if(prevBlockPointer != FATentryOffset) + { + offset = (mvFlash32Rd(mvFlashInfo, prevBlockPointer & FS_BLOCK_OFFSET_MASK) + & FS_BLOCK_OFFSET_MASK) | offset; + mvFlash32Wr(mvFlashInfo, prevBlockPointer & FS_BLOCK_OFFSET_MASK,offset); + } + else /* prevBlockPointer == FATentryOffset */ + { + offset = (mvFlash32Rd(mvFlashInfo, prevBlockPointer) & FS_BLOCK_OFFSET_MASK) + | offset; + mvFlash32Wr(mvFlashInfo, prevBlockPointer, offset); + } + mvFSEntries[fileHandler].statusFlag = FS_FREE_ENTRY; + } + return FS_FILE_CLOSED; +} + +/******************************************************************************* +* mvFSFileSize - Counts the number of bytes the file consist of. +* +* DESCRIPTION: +* This function counts and return the number of bytes the file consist of. +* If the file handler delivered to the function is erroneous the function +* will return the value 0xFFFFFFFF. +* +* INPUT: +* fileHandler - The file handler to count its bytes. +* +* OUTPUT: +* None. +* +* RETURN: +* The file's number of bytes of the on success or 0xFFFFFFFF on failier. +* +*******************************************************************************/ +unsigned int mvFSFileSize(FS_FILE_HANDLER fileHandler) +{ + unsigned int numOfBytes = 0,nextBlockPointer; + + if((fileHandler >= FS_MAX_NUM_OF_ENTRIES) || + (mvFSEntries[fileHandler].statusFlag == FS_FREE_ENTRY)) + return 0xffffffff; + nextBlockPointer = mvFlash32Rd(mvFlashInfo, mvFSEntries[fileHandler].pointerToFAT); + if(nextBlockPointer == 0xffffffff) + return 0; + while(nextBlockPointer != 0xffffffff) + { + if(((nextBlockPointer & FS_BLOCK_OFFSET) + 1) != FS_BLOCK_SIZE) + { + if(mvFlash8Rd(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_FLAG_OFFSET) == FS_FULL_BLOCK) + { + numOfBytes += (FS_BLOCK_SIZE - FS_BLOCK_HEADER_SIZE); + } + else + { + if(mvFlash16Rd(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_OFFSET) != 0xffff) + { + numOfBytes += ((nextBlockPointer & FS_BLOCK_OFFSET) + + mvFlash16Rd(mvFlashInfo, (nextBlockPointer & + FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_OFFSET) - + FS_BLOCK_HEADER_SIZE + 1); + } + else + { + numOfBytes += ((nextBlockPointer & FS_BLOCK_OFFSET) - + FS_BLOCK_HEADER_SIZE + 1); + } + } + } + else + { + if((mvFSEntries[fileHandler].EOFpointer & FS_BLOCK_OFFSET_MASK) == + (nextBlockPointer & FS_BLOCK_OFFSET_MASK)) /* Last block */ + { + numOfBytes += ((mvFSEntries[fileHandler].EOFpointer + & FS_BLOCK_OFFSET)- FS_BLOCK_HEADER_SIZE + 1); + } + else + { + numOfBytes += (FS_BLOCK_SIZE - FS_BLOCK_HEADER_SIZE); + } + } + nextBlockPointer = mvFlash32Rd(mvFlashInfo, nextBlockPointer & + FS_BLOCK_OFFSET_MASK); + } + if(numOfBytes == 0) + return 0; + return numOfBytes; +} + +/******************************************************************************* +* mvFSGetEOFoffset - Gets the file's EOF offset in the flash memory. +* +* DESCRIPTION: +* This function searches for the file’s EOF offset relatively to the +* begining of the last block offset . The EOF offset could be either the 9 +* least significant bits of the next block pointer or , if data was +* appended to last block , the offset field within that block . +* +* INPUT: +* fileName - The file name to get its EOF offset . +* +* OUTPUT: +* None. +* +* RETURN: +* The file's EOF offset or FILE_NOT_FOUND. +* +*******************************************************************************/ +unsigned int mvFSGetEOFoffset(char * fileName) +{ + unsigned int EOFoffset = 0,fileFAToffset,nextBlockOffset; + + fileFAToffset = mvFSFileFind(fileName); + if(fileFAToffset == FS_FILE_NOT_FOUND) + return FS_FILE_NOT_FOUND; + nextBlockOffset = mvFlash32Rd(mvFlashInfo, fileFAToffset); + if(nextBlockOffset == 0xffffffff) + return 0; + while(nextBlockOffset != 0xffffffff) + { + EOFoffset = nextBlockOffset; + nextBlockOffset = mvFlash32Rd(mvFlashInfo, nextBlockOffset & + FS_BLOCK_OFFSET_MASK); + } + nextBlockOffset = EOFoffset & FS_BLOCK_OFFSET_MASK; + if(mvFlash8Rd(mvFlashInfo, nextBlockOffset + FS_BLOCK_OFFSET_FLAG_OFFSET) == + FS_FULL_BLOCK) + { + EOFoffset = nextBlockOffset + (FS_BLOCK_SIZE - + FS_BLOCK_HEADER_SIZE - 1); + } + else + { + if(mvFlash16Rd(mvFlashInfo, nextBlockOffset + FS_BLOCK_OFFSET_OFFSET) + != 0xffff) + { + EOFoffset = EOFoffset + mvFlash16Rd(mvFlashInfo, nextBlockOffset + + FS_BLOCK_OFFSET_OFFSET); + } + else + { + return EOFoffset; /* Not necessary - just for readability */ + } + } + return EOFoffset; +} + +/******************************************************************************* +* mvFSGetFreeBlockForWrite - Returns the offset of a free block (if found). +* +* DESCRIPTION: +* This function searches for a free block in more efficient way than +* ‘fileSysGetFreeBlock’ function by saving the last free block offset +* that was found in the previous search and searches from that point. In +* case it couldnt find a free block , it uses the function +* ‘fileSysGetFreeBlock’. +* NOTE: +* The file system's data base must be initialized by ‘fileSysInit’ +* function before using this function . +* If during the copying of the sector containing the most free dirty block +* to the dynamic memory the system will loose power the file system will +* crash. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Offset to a free block , FS_NO_FREE_BLOCKS if there are no more free +* blocks or the file system was not initilized (use ‘fileSysInit’ before +* using this function in that case). +* +*******************************************************************************/ +unsigned int mvFSGetFreeBlockForWrite() +{ + unsigned char status; + + nextFreeBlock += FS_BLOCK_SIZE; + if((nextFreeBlock == 0xffffffff) || + ((nextFreeBlock != 0xffffffff) && (nextFreeBlock >= mvFSTopOffset))) + { + nextFreeBlock = mvFSGetFreeBlock(); + return nextFreeBlock; + } + else + { + while(1) + { + status = mvFlash8Rd(mvFlashInfo, nextFreeBlock + + FS_BLOCK_STATUS_FLAG_OFFSET); + if(status == FS_FREE_BLOCK) + { + return nextFreeBlock; + } + nextFreeBlock += FS_BLOCK_SIZE; + if(nextFreeBlock >= mvFSTopOffset || status == FS_FREE_DIRTY_BLOCK) + { + nextFreeBlock = mvFSGetFreeBlock(); + return nextFreeBlock; + } + } + } +} + +/******************************************************************************* +* mvFSGetFreeBlock - Returns the offset of a free block (if found). +* +* DESCRIPTION: +* This function searches for a free block from the begining of the file +* system ( from ‘fileSysOffset’ parameter initialized by ‘fileSysInit’ +* function ) to the last sector and return its offset in case it found +* one .While the function perform the search for a free block within each +* sector it also searches for the sector containing the most free dirty +* block in case a free block will not be found .If indeed a free block was +* not found ,the function erases that sector ( the one with the most free +* dirty blocks ) after copying it to a temporary buffer in the dynamic +* memory (SDRAM) and write back only the valid blocks to it .In that way +* the function free blocks from the sector containing the most free dirty +* blocks and return the next free block within that sector. +* NOTE: +* The file system's data base must be initialized by ‘fileSysInit’ +* function before using this function . +* If during the copying of the sector containing the most free dirty block +* to the dynamic memory the system will loose power the file system will +* crash. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Offset to a free block , NO_FREE_BLOCKS if there are no more free blocks +* or the file system was not initilized (use ‘fileSysInit’ before using +* this function in that case). +* +*******************************************************************************/ +unsigned int mvFSGetFreeBlock() +{ + unsigned int freeBlockOffset,sectorTopOffset,i; + unsigned int maxFreeDirtyBlocks = 0,sectorNumber,lastSector; + unsigned int dirtyBlocksCounter = 0,dirtyBlocksSector,blockSize; + unsigned int sectorBaseOffset,previousCounter,counterOffset; + char * rmwBlockPointer,* tempBlockPointer; + + /* Check if the file system's data base was initialized */ + if(initializationFlag != FS_FILE_SYSTEM_INITIALIZED) + return FS_NO_FREE_BLOCKS; + freeBlockOffset = mvFSOffset + FS_BLOCK_SIZE; + sectorNumber = mvFlashInWhichSec(mvFlashInfo, freeBlockOffset); + lastSector = mvFlashNumOfSecsGet(mvFlashInfo); + dirtyBlocksSector = sectorNumber; + /* Search for a free block, while doing that I am searching for the sector + with the most dirty free blocks in case I will not find a free block */ + for(i = sectorNumber ; i < lastSector ; i++) + { + sectorTopOffset = mvFlashSecOffsGet(mvFlashInfo, sectorNumber) + + mvFlashSecSizeGet(mvFlashInfo, sectorNumber) - 1; + dirtyBlocksCounter = 0; + while(freeBlockOffset < sectorTopOffset) + { + if(mvFlash8Rd(mvFlashInfo, freeBlockOffset + FS_BLOCK_STATUS_FLAG_OFFSET) + == FS_FREE_BLOCK) + { + return freeBlockOffset; + } + if(mvFlash8Rd(mvFlashInfo, freeBlockOffset + FS_BLOCK_STATUS_FLAG_OFFSET) + == FS_FREE_DIRTY_BLOCK) dirtyBlocksCounter++; + freeBlockOffset += FS_BLOCK_SIZE; + } + if(dirtyBlocksCounter > maxFreeDirtyBlocks) + { + maxFreeDirtyBlocks = dirtyBlocksCounter; + dirtyBlocksSector = sectorNumber; + } + sectorNumber = mvFlashInWhichSec(mvFlashInfo, freeBlockOffset); + } + /* We are here since we have'nt found a free block */ + /* Lets check if we have a free dirty block */ + if(maxFreeDirtyBlocks > 0) + { + /* Now we need to perform the read modify write dispensing the free + dirty blocks */ + blockSize = mvFlashSecSizeGet(mvFlashInfo, dirtyBlocksSector); + sectorBaseOffset = mvFlashSecOffsGet(mvFlashInfo, dirtyBlocksSector); + rmwBlockPointer = (char *)malloc(blockSize); + if(rmwBlockPointer == NULL) return FS_NO_FREE_BLOCKS; + /* Read the block */ + for(i = 0 ; i < blockSize ; i++) + { + rmwBlockPointer[i] = mvFlash8Rd(mvFlashInfo, sectorBaseOffset + i); + } + /* Erase the sector */ + if(mvFlash32Rd(mvFlashInfo, mvFSOffset + FS_ERSAING_COUNTER_FLAG_OFFSET) + == FS_ENABLE_ERASING_COUNTER) + { + counterOffset = sectorBaseOffset + blockSize - FS_BLOCK_SIZE; + previousCounter = mvFlash32Rd(mvFlashInfo, counterOffset); + mvFlashSecErase(mvFlashInfo, dirtyBlocksSector); + mvFlash32Wr(mvFlashInfo, counterOffset, previousCounter + 1); + mvFlash8Wr(mvFlashInfo, counterOffset + FS_BLOCK_STATUS_FLAG_OFFSET, + FS_BLOCK_USED_FOR_ERASING_COUNTER); + blockSize -= FS_BLOCK_SIZE; + } + else + { + mvFlashSecErase(mvFlashInfo, dirtyBlocksSector); + } + /* Write back only the valid blocks */ + for(i = 0 ; i < blockSize ; i += FS_BLOCK_SIZE) + { + if(rmwBlockPointer[i + FS_BLOCK_STATUS_FLAG_OFFSET] == + FS_BLOCK_IN_USE || rmwBlockPointer[i + + FS_BLOCK_STATUS_FLAG_OFFSET] == FS_BLOCK_IN_UPDATE || + rmwBlockPointer[i + FS_BLOCK_STATUS_FLAG_OFFSET] == FS_FAT_BLOCK) + { + tempBlockPointer = rmwBlockPointer + i; + mvFlashBlockWr(mvFlashInfo, sectorBaseOffset + i, FS_BLOCK_SIZE, + (MV_U8 *)tempBlockPointer); + } + } + free(rmwBlockPointer); + for(i = 0 ; i < blockSize ; i += FS_BLOCK_SIZE) + { + if(mvFlash8Rd(mvFlashInfo, sectorBaseOffset + i + + FS_BLOCK_STATUS_FLAG_OFFSET) + == FS_FREE_BLOCK) + return (sectorBaseOffset + i); + } + } + return FS_NO_FREE_BLOCKS; +} + +/******************************************************************************* +* mvFSGetFreeEntry - Finds a free entry in the FAT and returns its offset. +* +* DESCRIPTION: +* This function finds a free entry in the FAT and returns its offset. +* During the search for a free entry the function also finds the sector +* containing the most free dirty entries . If the fuction cant find any +* free entry within the FAT it copies the sector containing the most free +* dirty entries to the dynamic memory (SDRAM), erase that sector and write +* back only the valid entries. In that way the function free space for +* new entries and return the next free entry offset. +* NOTE: +* The file system's data base must be initialized by ‘fileSysInit’ +* function before using this function . +* If during the copying of the sector containing the most free dirty +* enrties to the dynamic memory the system will loose power the file +* system will crash. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Offset to a free entry , NO_FREE_ENTRIES if there are no more free +* entries in the file system`s FAT or the file system was not initialized +* (use ‘fileSysInit’ before using this function in that case). +* +*******************************************************************************/ +unsigned int mvFSGetFreeEntry() +{ + unsigned int nextBlockOffset,sectorNumber,i,previousSector; + unsigned int dirtyEntriesCounter = 0,dirtyEntriesSector,blockSize,j; + unsigned int maxFreeDirtyBlocks = 0; + unsigned int sectorBaseOffset,previousCounter,counterOffset; + char * rmwBlockPointer,* tempBlockPointer; + + /* Check if the file system's data base was initialized */ + if(initializationFlag != FS_FILE_SYSTEM_INITIALIZED) + return FS_NO_FREE_ENTRIES; + /* First FAT block */ + nextBlockOffset = mvFSOffset; + sectorNumber = mvFlashInWhichSec(mvFlashInfo, nextBlockOffset); + dirtyEntriesSector = sectorNumber; + previousSector = sectorNumber; + while(nextBlockOffset != 0xffffffff) + { + if(previousSector != sectorNumber) + { + if(dirtyEntriesSector > maxFreeDirtyBlocks) + { + maxFreeDirtyBlocks = dirtyEntriesSector; + dirtyEntriesSector = sectorNumber; + } + previousSector = sectorNumber; + dirtyEntriesSector = 0; + } + sectorNumber = mvFlashInWhichSec(mvFlashInfo, nextBlockOffset); + for(i = 0 ; i < FS_BLOCK_SIZE ; i += FS_FAT_FILE_ENTRY_SIZE) + { + if(mvFlash8Rd(mvFlashInfo, nextBlockOffset +i+ FS_ENTRY_STATUS_FLAG_OFFSET) + == FS_FREE_ENTRY) + return (nextBlockOffset + i); + if(mvFlash8Rd(mvFlashInfo, nextBlockOffset +i+ FS_ENTRY_STATUS_FLAG_OFFSET) + == FS_FREE_DIRTY_ENTRY) + dirtyEntriesCounter++; + } + nextBlockOffset = mvFlash32Rd(mvFlashInfo, nextBlockOffset); + } + /* Now we need to perform the read modify write dispensing the free + dirty entries and blocks */ + blockSize = mvFlashSecSizeGet(mvFlashInfo, dirtyEntriesSector); + sectorBaseOffset = mvFlashSecOffsGet(mvFlashInfo, dirtyEntriesSector); + rmwBlockPointer = (char *)malloc(blockSize); + if(rmwBlockPointer == NULL) return FS_NO_FREE_ENTRIES; + /* Read the block */ + for(i = 0 ; i < blockSize ; i++) + { + rmwBlockPointer[i] = mvFlash8Rd(mvFlashInfo, sectorBaseOffset + i); + } + /* Erase the sector */ + if(mvFlash32Rd(mvFlashInfo, mvFSOffset + 20) == FS_ENABLE_ERASING_COUNTER) + { + counterOffset = sectorBaseOffset + blockSize - FS_BLOCK_SIZE; + previousCounter = mvFlash32Rd(mvFlashInfo, counterOffset); + mvFlashSecErase(mvFlashInfo, dirtyEntriesSector); + mvFlash32Wr(mvFlashInfo, counterOffset,previousCounter + 1); + mvFlash8Wr(mvFlashInfo, counterOffset + FS_BLOCK_STATUS_FLAG_OFFSET, + FS_BLOCK_USED_FOR_ERASING_COUNTER); + blockSize -= FS_BLOCK_SIZE; + } + else + { + mvFlashSecErase(mvFlashInfo, dirtyEntriesSector); + } + /* Write back only the valid blocks */ + for(i = 0 ; i < blockSize ; i += FS_BLOCK_SIZE) + { + if(rmwBlockPointer[i + FS_BLOCK_STATUS_FLAG_OFFSET] == + FS_BLOCK_IN_USE || rmwBlockPointer[i + FS_BLOCK_STATUS_FLAG_OFFSET] + == FS_BLOCK_IN_UPDATE) + { + tempBlockPointer = rmwBlockPointer + i; + mvFlashBlockWr(mvFlashInfo, sectorBaseOffset + i, FS_BLOCK_SIZE, + (MV_U8 *)tempBlockPointer); + } + if(rmwBlockPointer[i + FS_BLOCK_STATUS_FLAG_OFFSET] == FS_FAT_BLOCK) + { + for(j = FS_FAT_FILE_ENTRY_SIZE ; j < FS_BLOCK_SIZE ; + j+= FS_FAT_FILE_ENTRY_SIZE) + { + if(rmwBlockPointer[j + FS_ENTRY_STATUS_FLAG_OFFSET] + == FS_ENTRY_IN_USE || + rmwBlockPointer[j + FS_ENTRY_STATUS_FLAG_OFFSET] + == FS_ENTRY_IN_UPDATE) + { + tempBlockPointer = rmwBlockPointer + j; + mvFlashBlockWr(mvFlashInfo, sectorBaseOffset + j, + FS_FAT_FILE_ENTRY_SIZE, (MV_U8 *)tempBlockPointer); + } + } + } + } + free(rmwBlockPointer); + for(i = 0 ; i < blockSize ; i += FS_BLOCK_SIZE) + { + if(mvFlash32Rd(mvFlashInfo, sectorBaseOffset + i + FS_BLOCK_STATUS_FLAG_OFFSET) + == FS_FAT_BLOCK) + { + for(j = i + FS_FAT_FILE_ENTRY_SIZE ; j < (i + FS_BLOCK_SIZE) ; + j+= FS_FAT_FILE_ENTRY_SIZE) + { + if(mvFlash32Rd(mvFlashInfo, sectorBaseOffset +j+ + FS_ENTRY_STATUS_FLAG_OFFSET) == FS_FREE_ENTRY) + return (sectorBaseOffset + j); + } + } + } + return FS_NO_FREE_ENTRIES; +} + +/******************************************************************************* +* mvFSWriteFileNameToFATentry - Write the file name to an entry in the FAT . +* +* DESCRIPTION: +* This function writes the file name to an entry in the FAT.The function +* extarcts the file name and extention and write it to the entry at +* ‘entryOffset’ within the FAT. +* +* INPUT: +* entryOffset - Pointer to the desired entry to write the file name at. +* fileName - The file name and extention. +* +* OUTPUT: +* None. +* +* RETURN: +* 0 for invalid file name, 1 for success. +* +*******************************************************************************/ +unsigned int mvFSWriteFileNameToFATentry(unsigned int entryOffset, + char * fileName) +{ + char name[FS_FILE_NAME_LENGTH]; + char ext[FS_FILE_EXT_LENGTH]; + unsigned int index,extIndex; + + /* Extract the name */ + for(index = 0 ; index < FS_FILE_NAME_LENGTH ; index++) + { + if(fileName[index] == '.' || fileName[index] == '\0') + { + break; + } + else + { + name[index] = fileName[index]; + } + } + /* Write the name */ + if(index != 0) + mvFlashBlockWr(mvFlashInfo, entryOffset + FS_FILE_NAME_OFFSET, index, (MV_U8 *)name); + if(index == 0 && fileName[index] == '\0') /* Not a valid name */ + return 0; + if(fileName[index] == '\0') /* No extension */ + return 1; + /* Extract the extension */ + index++; /* Skip the dot */ + for(extIndex = 0 ; extIndex < FS_FILE_EXT_LENGTH ; extIndex++) + { + if(fileName[index + extIndex] == '\0') + { + // ronen fix a bug ---> extIndex++; + break; + } + else + { + ext[extIndex] = fileName[index + extIndex]; + } + } + /* Write the extension */ + if(extIndex != 0) + mvFlashBlockWr(mvFlashInfo, entryOffset + FS_FILE_EXT_OFFSET, extIndex, (MV_U8 *)ext); + return 1; +} + +/******************************************************************************* +* mvFSReadFileNameFromFATentry - Read the file name from an entry in the FAT. +* +* DESCRIPTION: +* This function reads the file name from an entry in the FAT. If the given +* entry is not used by any file , the function will return 0 to remark a +* failier. +* +* INPUT: +* entryOffset - Pointer to the desired entry to read the file name from. +* fileName - pointer to an empty array to be filled by this functoin with +* the file name and extention. +* OUTPUT: +* None. +* +* RETURN: +* 0 for failure, 1 for success. +* +* +*******************************************************************************/ +unsigned int mvFSReadFileNameFromFATentry(unsigned int entryOffset, + char * fileName) +{ + unsigned int index = 0,offset; + unsigned char c; + + if( (mvFlash8Rd(mvFlashInfo, entryOffset + FS_ENTRY_STATUS_FLAG_OFFSET) + == FS_ENTRY_IN_USE) || + (mvFlash8Rd(mvFlashInfo, entryOffset + FS_ENTRY_STATUS_FLAG_OFFSET) + == FS_ENTRY_IN_UPDATE) ) + { + for(offset = 0 ; offset < FS_FILE_NAME_LENGTH ; offset++) + { + c = mvFlash8Rd(mvFlashInfo, entryOffset + FS_FILE_NAME_OFFSET + offset); + if(c == 0xff) + break; + fileName[index++] = c; + } + if(mvFlash8Rd(mvFlashInfo, entryOffset + FS_FILE_EXT_OFFSET) != 0xff) + { + fileName[index++] = '.'; + for(offset = 0 ; offset < FS_FILE_EXT_LENGTH ; offset++) + { + c = mvFlash8Rd(mvFlashInfo, entryOffset + FS_FILE_EXT_OFFSET + offset); + if(c == 0xff) break; + fileName[index++] = c; + } + } + fileName[index++] = '\0'; + return 1; + } + return 0; +} + +/******************************************************************************* +* mvFSWrite - Writes a block of data to an opened file. +* +* DESCRIPTION: +* This function writes a block of data to a file opened by all modes +* except mode “r” indicating the file is a read only file. The function +* will append the data to the last block ( if the offset flag is not set +* yet ) or to a new block if this is a new file , the function also takes +* care of updating the EOF pointer , updating the file's entry and data +* blocks status flags. During the write attempt , the function will +* return 0 value in the following cases: +* - if the given file handler is invalid that is , grater or equal to +* MAX_NUM_OF_ENTRIES (defined in mvFS.h). +* - if the entry of the file handler holds the status FREE_ENTRY. +* - if the ‘numberOfBytes’ parameter is 0. +* - if this is the first write attempt to the file ( new file ) , the +* function will allocate a new block for the data , in this case a +* failier can occur resulting from lack of free blocks. In all other +* cases the function will return the number of bytes actually written. +* Note that the number of bytes actually written returned by this +* function may not be equal to the ‘numberOfBytes’ parameter , in that +* case consider the write action as a fatal error and do not try to +* re-write the data. +* +* INPUT: +* fileHandler - The file handler of the file to be written. +* numOfBytes - The number of bytes to be written from the data array. +* block - The data array to write to the file. +* +* OUTPUT: +* None. +* +* RETURN: +* Returns the number of bytes actually written, if the number of +* bytes actually written is not equal to the numberOfBytes consider it as +* a fatal error, do not try to re-write the data. +* +*******************************************************************************/ +unsigned int mvFSWrite(FS_FILE_HANDLER fileHandler, + unsigned int numberOfBytes,char * block) +{ + unsigned int remainingBytes,nextBlockPointer,newBlockPointer,blockSize; + unsigned int freeBytesInBlock,writtenBytes,blockIndex = 0; + unsigned int totalWrittenBytes = 0,numberOfBlocks,i; + + blockSize = FS_BLOCK_SIZE - FS_BLOCK_HEADER_SIZE; + if((fileHandler >= FS_MAX_NUM_OF_ENTRIES) || + (mvFSEntries[fileHandler].statusFlag == FS_FREE_ENTRY) || + numberOfBytes == 0) + return 0; + if(mvFSEntries[fileHandler].mode[0] == 'r' && + mvFSEntries[fileHandler].mode[1] == '\0') + return 0; /* File was opened as read only */ + nextBlockPointer = mvFlash32Rd(mvFlashInfo, mvFSEntries[fileHandler].pointerToFAT); + remainingBytes = numberOfBytes; + if(nextBlockPointer == 0xffffffff) + { + /* New file, no blocks allocated yet */ + newBlockPointer = mvFSGetFreeBlock(); + mvFSEntries[fileHandler].blockPointer = newBlockPointer; + if(newBlockPointer == FS_NO_FREE_BLOCKS) + return 0; + /* Update the entry's status flag and next block pointer */ + mvFlash32Wr(mvFlashInfo, mvFSEntries[fileHandler].pointerToFAT, + newBlockPointer | FS_BLOCK_OFFSET); + mvFlash8Wr(mvFlashInfo, mvFSEntries[fileHandler].pointerToFAT + + FS_ENTRY_STATUS_FLAG_OFFSET, FS_ENTRY_IN_USE); + /* Start writing the data */ + if(numberOfBytes <= blockSize) + { + /* Only one block needed */ + /* Update the blocks status flag */ + mvFlash8Wr(mvFlashInfo, newBlockPointer + FS_BLOCK_STATUS_FLAG_OFFSET, + FS_BLOCK_IN_UPDATE); + /* Update the EOFpointer */ + mvFSEntries[fileHandler].EOFpointer = newBlockPointer + + numberOfBytes + FS_BLOCK_HEADER_SIZE - 1; + /* Update the File pointer */ + mvFSEntries[fileHandler].filePointer = + mvFSEntries[fileHandler].EOFpointer; + /* Write the data */ + return + mvFlashBlockWr(mvFlashInfo, newBlockPointer + FS_BLOCK_HEADER_SIZE, + numberOfBytes, (MV_U8 *)block); + } + else /* More than one block is needed */ + { + /* I will take care of the first block in here, the rest + will be handled later in the fuction */ + /* Update the block's status flag */ + mvFlash8Wr(mvFlashInfo, newBlockPointer + FS_BLOCK_STATUS_FLAG_OFFSET, + FS_BLOCK_IN_USE);/* Fully exploited block */ + /* Write the data */ + writtenBytes = mvFlashBlockWr(mvFlashInfo, newBlockPointer + + FS_BLOCK_HEADER_SIZE, blockSize, (MV_U8 *)block); + /* Update the EOFpointer */ + mvFSEntries[fileHandler].EOFpointer = newBlockPointer + + writtenBytes + FS_BLOCK_HEADER_SIZE - 1; + /* Update the File pointer */ + mvFSEntries[fileHandler].filePointer = + mvFSEntries[fileHandler].EOFpointer; + if(writtenBytes != blockSize) + return writtenBytes; /* Write operation failed */ + totalWrittenBytes += writtenBytes; + remainingBytes = numberOfBytes - blockSize; + nextBlockPointer = newBlockPointer; + blockIndex += blockSize; + } + } + /* Search for the last block */ + while(mvFlash32Rd(mvFlashInfo, nextBlockPointer & FS_BLOCK_OFFSET_MASK) != + 0xffffffff) + { + nextBlockPointer = mvFlash32Rd(mvFlashInfo, nextBlockPointer & + FS_BLOCK_OFFSET_MASK); + mvFSEntries[fileHandler].blockPointer = nextBlockPointer; + } + freeBytesInBlock = FS_BLOCK_SIZE - 1 - + (mvFSEntries[fileHandler].EOFpointer & FS_BLOCK_OFFSET); + if(mvFlash8Rd(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_STATUS_FLAG_OFFSET) == FS_BLOCK_IN_USE) + { + /* We can use the offset flag to append data, or the FS_FULL_BLOCK + flag in case the block will be fully exploited */ + if(freeBytesInBlock != 0) + { + if((remainingBytes < freeBytesInBlock) && + mvFlash16Rd(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_OFFSET) == 0xffff) + { + writtenBytes = mvFlashBlockWr(mvFlashInfo, + mvFSEntries[fileHandler].EOFpointer + 1, + remainingBytes, (MV_U8 *)&block[blockIndex]); + mvFSEntries[fileHandler].EOFpointer += writtenBytes; + /* Update the File pointer */ + mvFSEntries[fileHandler].filePointer = + mvFSEntries[fileHandler].EOFpointer; + if(remainingBytes == freeBytesInBlock) + { + mvFlash8Wr(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_FLAG_OFFSET, FS_FULL_BLOCK); + } + /* else the OFFSET will be updated by mvFSClose */ + return writtenBytes; + } + else + { + if(remainingBytes >= freeBytesInBlock) + { + writtenBytes = mvFlashBlockWr(mvFlashInfo, + mvFSEntries[fileHandler].EOFpointer + 1, + freeBytesInBlock, (MV_U8 *)&block[blockIndex]); + mvFSEntries[fileHandler].EOFpointer += freeBytesInBlock; + /* Update the File pointer */ + mvFSEntries[fileHandler].filePointer = + mvFSEntries[fileHandler].EOFpointer; + totalWrittenBytes += writtenBytes; + if(writtenBytes != freeBytesInBlock) /* error */ + return totalWrittenBytes; + mvFlash8Wr(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_FLAG_OFFSET, FS_FULL_BLOCK); + remainingBytes -= freeBytesInBlock; + blockIndex += freeBytesInBlock; + } + } + } + } + else /* The block is not sealed yet, we can simply append the data */ + { + if(remainingBytes <= freeBytesInBlock) + { + writtenBytes = mvFlashBlockWr(mvFlashInfo, + mvFSEntries[fileHandler].EOFpointer + 1, + remainingBytes, (MV_U8 *)&block[blockIndex]); + mvFSEntries[fileHandler].EOFpointer += writtenBytes; + /* Update the File pointer */ + mvFSEntries[fileHandler].filePointer = + mvFSEntries[fileHandler].EOFpointer; + if(remainingBytes == freeBytesInBlock) + { + mvFlash8Wr(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_STATUS_FLAG_OFFSET, FS_BLOCK_IN_USE); + } + return writtenBytes; + } + else /* More blocks are needed */ + { + /* Fill the current block */ + writtenBytes = mvFlashBlockWr(mvFlashInfo, + mvFSEntries[fileHandler].EOFpointer + 1, + freeBytesInBlock, (MV_U8 *)&block[blockIndex]); + mvFSEntries[fileHandler].EOFpointer += writtenBytes; + /* Update the File pointer */ + mvFSEntries[fileHandler].filePointer = + mvFSEntries[fileHandler].EOFpointer; + totalWrittenBytes += writtenBytes; + if(writtenBytes != freeBytesInBlock) /* error */ + return totalWrittenBytes; + mvFlash8Wr(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_STATUS_FLAG_OFFSET, FS_BLOCK_IN_USE); + remainingBytes -= freeBytesInBlock; + blockIndex += freeBytesInBlock; + } + } + numberOfBlocks = remainingBytes / blockSize; + for(i = 0 ; i < numberOfBlocks ; i++) + { + /* All the blocks in this loop will be fully exploited */ + newBlockPointer = mvFSGetFreeBlockForWrite(); + if(newBlockPointer == FS_NO_FREE_BLOCKS) + return totalWrittenBytes; + /* Update the nextBlockPointer */ + mvFlash32Wr(mvFlashInfo, nextBlockPointer & FS_BLOCK_OFFSET_MASK, + newBlockPointer | FS_BLOCK_OFFSET); + /* Update the status flag */ + mvFlash8Wr(mvFlashInfo, (newBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_STATUS_FLAG_OFFSET, FS_BLOCK_IN_USE); + /* Write The Data */ + writtenBytes = mvFlashBlockWr(mvFlashInfo, (newBlockPointer & + FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_HEADER_SIZE, blockSize, + (MV_U8 *)&block[blockIndex]); + blockIndex += blockSize; + totalWrittenBytes += writtenBytes; + /* Make sure the EOFpointer is set for error handling */ + mvFSEntries[fileHandler].EOFpointer = (newBlockPointer + & FS_BLOCK_OFFSET_MASK) + FS_BLOCK_HEADER_SIZE + writtenBytes - 1; + /* Update the File pointer */ + mvFSEntries[fileHandler].filePointer = + mvFSEntries[fileHandler].EOFpointer; + if(writtenBytes != blockSize)/* Error */ + return totalWrittenBytes; + remainingBytes -= blockSize; + nextBlockPointer = newBlockPointer; + } + if(remainingBytes == 0) + return totalWrittenBytes; + /* Allocate a new block for the remaining bytes */ + newBlockPointer = mvFSGetFreeBlockForWrite(); + if(newBlockPointer == FS_NO_FREE_BLOCKS) + return totalWrittenBytes; + /* Update the nextBlockPointer */ + mvFlash32Wr(mvFlashInfo, nextBlockPointer & FS_BLOCK_OFFSET_MASK, + newBlockPointer | FS_BLOCK_OFFSET); + /* Update the status flag */ + mvFlash8Wr(mvFlashInfo, (newBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_STATUS_FLAG_OFFSET, FS_BLOCK_IN_UPDATE); + /* Write The Data */ + writtenBytes = mvFlashBlockWr(mvFlashInfo, (newBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_HEADER_SIZE, remainingBytes, + (MV_U8 *)&block[blockIndex]); + mvFSEntries[fileHandler].EOFpointer = (newBlockPointer + & FS_BLOCK_OFFSET_MASK) + FS_BLOCK_HEADER_SIZE + writtenBytes - 1; + /* Update the File pointer */ + mvFSEntries[fileHandler].filePointer = + mvFSEntries[fileHandler].EOFpointer; + totalWrittenBytes += writtenBytes; + return totalWrittenBytes; +} + +/******************************************************************************* +* mvFSGetNumOfValidBytes - Return the number of valid bytes from +* blockOffsetPointer to the end of the block. +* +* DESCRIPTION: +* None. +* +* INPUT: +* blockPointer - The offset of the block to read its valid bytes. +* blockOffsetPointer - The offset within the block to read the valid +* bytes from. +* EOFpointer - The EOF offset. +* OUTPUT: +* None. +* +* RETURN: +* Number of valid bytes. +* +*******************************************************************************/ +unsigned int mvFSGetNumOfValidBytes(unsigned int blockPointer, + unsigned int blockOffsetPointer, + unsigned int EOFpointer) +{ + if((blockOffsetPointer & FS_BLOCK_OFFSET_MASK) == + (EOFpointer & FS_BLOCK_OFFSET_MASK)) + { + /* This is the last block */ + if(EOFpointer > blockOffsetPointer) + return (EOFpointer - blockOffsetPointer); + else + return 0; + } + else + { + if((mvFlash8Rd(mvFlashInfo, (blockOffsetPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_FLAG_OFFSET) == FS_FULL_BLOCK) + || ((blockPointer & FS_BLOCK_OFFSET) == FS_BLOCK_OFFSET)) + { + return (FS_BLOCK_SIZE - 1 - (blockOffsetPointer & FS_BLOCK_OFFSET)); + } + else /* offset field is used */ + { + return ((blockPointer & FS_BLOCK_OFFSET) + mvFlash16Rd(mvFlashInfo, + (blockPointer & FS_BLOCK_OFFSET_MASK) + FS_BLOCK_OFFSET_OFFSET) + - (blockOffsetPointer & FS_BLOCK_OFFSET)); + } + } +} + +/******************************************************************************* +* mvFSRead - Read a block of data into block from a file. +* +* DESCRIPTION: +* This function reads a block of data from a file opened by all modes +* except “ w ” mode , into a given block (‘block’ parameter ) .While the +* file is opened , the function will start reading the file from the +* begining if its the first read attempt after opening the file or from +* the last point within the block of data were the previous read action +* ended .The read action will not exceed the EOF pointer if the +* ‘numberOfBytes’ parameter is larger than the whole file or the number of +* bytes left from the previous read action . During the read attempt , the +* function will return an error code or 0 in the following cases: +* +* - if the given file handler is invalid that is , grater or equal to +* MAX_NUM_OF_ENTRIES (defined in fileSys.h). +* - if the entry of the file handler within the dynamic database holds the +* status FREE_ENTRY . +* - if the mode of the opened file is write only - “ w” . +* - if the EOF pointer is equal to the file pointer that indicates the +* curruent position within the file. +* - if the ‘nextBlockPointer’ field within the entry in the FAT is equal +* to 0xFFFFFFFF indicating the file is empty. +* In a successfull read operation the function will return the number of +* bytes read , if this value is not equal to the ‘numberOfBytes’ +* parameter delivered to the function , the read action reached EOF. +* +* INPUT: +* fileHandler - The file handler of the file to be read. +* numOfBytes - The number of bytes to be read from the file to the data +* array. +* block - The data array to hold the read data from the file. +* +* OUTPUT: +* block filled with data from the file. +* +* RETURN: +* The number of bytes actually read . If this value is not equal to the +* ‘numberOfBytes’ parameter delivered to the function , the read action +* reached EOF.The function can also return the following values in case of +* an error : +* - FILE_READ_ERROR if the fileHandler is larger or equal to +* MAX_NUM_OF_ENTRIES defined in fileSys.h or if the status flag of the +* file entry in the dynamic database holds the value FREE_ENTRY. +* - 0 if the file was opened as write only , the EOF pointer is equal to +* the file pointer indicating the current loaction within the file or +* the ‘nextBlockPointer’ field within the file entry in the flash is +* equal to 0xFFFFFFFF (empty file). +* +*******************************************************************************/ +unsigned int mvFSRead(FS_FILE_HANDLER fileHandler, + unsigned int numberOfBytes,char * block) +{ + unsigned int blockIndex = 0,nextBlockPointer,EOFpointer; + unsigned int remainingBytes,freeBytesInBlock,bytesRead; + unsigned int totalBytesRead = 0,blockSize; + + if((fileHandler >= FS_MAX_NUM_OF_ENTRIES) || + (mvFSEntries[fileHandler].statusFlag == FS_FREE_ENTRY) || + numberOfBytes == 0) + return FS_FILE_READ_ERROR; + if(mvFSEntries[fileHandler].mode[0] == 'w' && + mvFSEntries[fileHandler].mode[1] == '\0') + return 0; /* File was opened as write only */ + if(mvFSEntries[fileHandler].EOFpointer == + mvFSEntries[fileHandler].filePointer) + return 0; + blockSize = FS_BLOCK_SIZE - FS_BLOCK_HEADER_SIZE; + EOFpointer = mvFSEntries[fileHandler].EOFpointer; + remainingBytes = numberOfBytes; + nextBlockPointer = mvFlash32Rd(mvFlashInfo, mvFSEntries[fileHandler].pointerToFAT); + if(nextBlockPointer == 0xffffffff) + return 0; /* An empty file */ + if(mvFSEntries[fileHandler].filePointer == 0) + { + /* Read one byte and set the filePointer to the first block */ + block[blockIndex] = mvFlash8Rd(mvFlashInfo, (nextBlockPointer + & FS_BLOCK_OFFSET_MASK) + FS_BLOCK_HEADER_SIZE); + remainingBytes--; + totalBytesRead++; + mvFSEntries[fileHandler].filePointer = (nextBlockPointer + & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_HEADER_SIZE; + blockIndex++; + mvFSEntries[fileHandler].blockPointer= nextBlockPointer; + } + else + { + /* update the block's file pointer */ + nextBlockPointer = mvFSEntries[fileHandler].blockPointer; + } + while(1) + { + if((mvFSEntries[fileHandler].filePointer & FS_BLOCK_OFFSET_MASK) != + (nextBlockPointer & FS_BLOCK_OFFSET_MASK)) + { /* Forward the file pointer to the current block */ + block[blockIndex] = mvFlash8Rd(mvFlashInfo, (nextBlockPointer + & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_HEADER_SIZE); + remainingBytes--; + totalBytesRead++; + mvFSEntries[fileHandler].filePointer = (nextBlockPointer + & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_HEADER_SIZE; + blockIndex++; + } + freeBytesInBlock = mvFSGetNumOfValidBytes(nextBlockPointer, + mvFSEntries[fileHandler].filePointer, + EOFpointer); + if(freeBytesInBlock <= remainingBytes) + { + bytesRead = mvFlashBlockRd(mvFlashInfo, mvFSEntries[fileHandler].filePointer + +1,freeBytesInBlock, (MV_U8 *)&block[blockIndex]); + remainingBytes -= bytesRead; + totalBytesRead += bytesRead; + mvFSEntries[fileHandler].filePointer += bytesRead; + blockIndex += bytesRead; + if(bytesRead != freeBytesInBlock) /* Fatal error */ + { + return totalBytesRead; + } + } + else + { + bytesRead = mvFlashBlockRd(mvFlashInfo, mvFSEntries[fileHandler].filePointer + +1,remainingBytes,(MV_U8 *)&block[blockIndex]); + totalBytesRead += bytesRead; + mvFSEntries[fileHandler].filePointer += bytesRead; + blockIndex += bytesRead; + if(bytesRead != remainingBytes) /* Fatal error */ + { + return totalBytesRead; + } + remainingBytes -= bytesRead; + } + if(((nextBlockPointer & FS_BLOCK_OFFSET_MASK) == + (EOFpointer & FS_BLOCK_OFFSET_MASK)) || remainingBytes == 0) + { /* Last valid block */ + return totalBytesRead; + } + nextBlockPointer = mvFlash32Rd(mvFlashInfo, nextBlockPointer & + FS_BLOCK_OFFSET_MASK); + mvFSEntries[fileHandler].blockPointer = nextBlockPointer; + } + return totalBytesRead; +} + +/******************************************************************************* +* mvFSRewind - Set the file pointer the beginning of the file. +* +* DESCRIPTION: +* This function set the file pointer the beginning of the given file. +* +* INPUT: +* fileHandler - The file handler of the file to rewind its pointer. +* +* OUTPUT: +* None. +* +* RETURN: +* 0 on succes otherwise 0xffffffff. +* +*******************************************************************************/ +unsigned int mvFSRewind(FS_FILE_HANDLER fileHandler) +{ + if((fileHandler >= FS_MAX_NUM_OF_ENTRIES) || + (mvFSEntries[fileHandler].statusFlag == FS_FREE_ENTRY)) + return 0xffffffff; + mvFSEntries[fileHandler].filePointer = 0; + return 0; +} + +/******************************************************************************* +* mvFSSeek - Move the file pointer from the origin specified. +* +* DESCRIPTION: +* This function move’s the file-pointer associated with ‘filehandler’ to a +* new location that is ‘offset’ bytes from ‘origin’.The argument ‘origin’ +* must be one of the following constants , defined in mvFS.h : +* +* SEEK_CUR - Current position of file pointer. +* SEEK_END - End of file. +* SEEK_SET - Beginning of file. +* +* The ‘offset’ argument indicates the number of bytes to move relatively +* to ‘origin’. +* +* INPUT: +* fileHandler - The file-handler of the file to reposition its +* file-pointer. +* Offset - The number of bytes to move the file pointer from ‘origin’. +* Origin - The relative point within the file to move the file-pointer +* ‘offset’ bytes from it.Must be one of the three values +* described above. +* +* OUTPUT: +* File-pointer located on its new place ( on success ). +* +* RETURN: +* true on succes, 0xffffffff otherwise. +* +*******************************************************************************/ +unsigned int mvFSSeek(FS_FILE_HANDLER fileHandler,int offset,int origin) +{ + unsigned int nextBlockPointer,fileSize; + unsigned int validBytes,temp; + int tempSize = 0,tempOffset = 0; + + if((fileHandler >= FS_MAX_NUM_OF_ENTRIES) || + (mvFSEntries[fileHandler].statusFlag == FS_FREE_ENTRY)) + return 0xffffffff; + fileSize = mvFSFileSize(fileHandler); + if(fileSize == 0xffffffff || fileSize == 0) + return 0xffffffff; + nextBlockPointer = mvFlash32Rd(mvFlashInfo, mvFSEntries[fileHandler].pointerToFAT); + switch(origin) + { + case FS_SEEK_END: + if(offset <= 0) + return 1/*true*/; + if((unsigned int)offset >= fileSize) + { + mvFSEntries[fileHandler].filePointer = 0; + return 1/*true*/; + } + offset = fileSize - offset; + break; + case FS_SEEK_SET: + if(offset <= 0) + { + mvFSEntries[fileHandler].filePointer = 0; + return 1/*true*/; + } + if((unsigned int)offset >= fileSize) + { + mvFSEntries[fileHandler].filePointer = + mvFSEntries[fileHandler].EOFpointer; + return 1/*true*/; + } + while(tempOffset < offset) + { + validBytes = mvFSGetNumOfValidBytes(nextBlockPointer, + (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_HEADER_SIZE, + mvFSEntries[fileHandler].EOFpointer); + if((tempOffset + (int)validBytes) >= offset) + break; + tempOffset += validBytes; + nextBlockPointer = mvFlash32Rd(mvFlashInfo, nextBlockPointer + & FS_BLOCK_OFFSET_MASK); + mvFSEntries[fileHandler].blockPointer = nextBlockPointer; + } + mvFSEntries[fileHandler].filePointer = + (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + (offset - tempOffset) + FS_BLOCK_HEADER_SIZE - 1; + return 1/*true*/; + case FS_SEEK_CUR: /* In this case offset can be negative */ + if(offset == 0) + return 1/*true*/; + /* tempSize = Size in bytes up-to filePointer */ + temp = nextBlockPointer; + nextBlockPointer = + mvFlash32Rd(mvFlashInfo, mvFSEntries[fileHandler].pointerToFAT); + mvFSEntries[fileHandler].blockPointer = nextBlockPointer; + while(nextBlockPointer != 0xffffffff) + { + if(mvFSEntries[fileHandler].filePointer == 0) + break; + if((mvFSEntries[fileHandler].filePointer & FS_BLOCK_OFFSET_MASK) == + (nextBlockPointer & FS_BLOCK_OFFSET_MASK)) /* Last block for us*/ + { + tempSize += (mvFSEntries[fileHandler].filePointer + & FS_BLOCK_OFFSET) - FS_BLOCK_HEADER_SIZE + 1; + break; + } + if(((nextBlockPointer & FS_BLOCK_OFFSET) + 1) != FS_BLOCK_SIZE) + { + if(mvFlash8Rd(mvFlashInfo, (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_FLAG_OFFSET) == FS_FULL_BLOCK) + { + tempSize += (FS_BLOCK_SIZE - FS_BLOCK_HEADER_SIZE); + } + else + { + if(mvFlash16Rd(mvFlashInfo, (nextBlockPointer & + FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_OFFSET) != 0xffff) + { + tempSize += ((nextBlockPointer & FS_BLOCK_OFFSET) + + mvFlash16Rd(mvFlashInfo, (nextBlockPointer & + FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_OFFSET_OFFSET) - + FS_BLOCK_HEADER_SIZE + 1); + } + else + { + tempSize += ((nextBlockPointer & FS_BLOCK_OFFSET) - + FS_BLOCK_HEADER_SIZE + 1); + } + } + } + else + { + tempSize += (FS_BLOCK_SIZE - FS_BLOCK_HEADER_SIZE); + } + nextBlockPointer = mvFlash32Rd(mvFlashInfo, nextBlockPointer & + FS_BLOCK_OFFSET_MASK); + mvFSEntries[fileHandler].blockPointer = nextBlockPointer; + } + nextBlockPointer = temp; + offset = tempSize + offset; + if(offset >= (int)fileSize) + { + mvFSEntries[fileHandler].filePointer = + mvFSEntries[fileHandler].EOFpointer; + return 1/*true*/; + } + if(offset <= (int)0) + { + mvFSEntries[fileHandler].filePointer = 0; + return 1/*true*/; + } + while(tempOffset < offset) + { + validBytes = mvFSGetNumOfValidBytes(nextBlockPointer, + (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + FS_BLOCK_HEADER_SIZE, + mvFSEntries[fileHandler].EOFpointer); + if((tempOffset + (int)validBytes) >= offset) + break; + tempOffset += validBytes; + nextBlockPointer = mvFlash32Rd(mvFlashInfo, nextBlockPointer + & FS_BLOCK_OFFSET_MASK); + mvFSEntries[fileHandler].blockPointer = nextBlockPointer; + } + mvFSEntries[fileHandler].filePointer = + (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + + (offset - tempOffset) + FS_BLOCK_HEADER_SIZE - 1; + return 1/*true*/; + default: + return 0xffffffff; + } + return 0xffffffff; +} + +/******************************************************************************* +* mvFSReadErasingCounter - Reads the value of the erasing counter (if +* implemented). +* +* DESCRIPTION: +* This function reads the value of the erasing counter ( if implemented ) +* of the given sector .The erasing counter is enabled by the function +* ‘fileSysFormat’ (by the ‘mode’ parameter) . It is implimented by +* allocating one block at the end of each sector and it helps monitoring +* the number of erasures of the sector the counter is at . +* NOTE: +* he file system's data base must be initialized by ‘fileSysInit’ function +* before using this function . +* +* INPUT: +* sectorNumber - The sector number to read its erasing counter +* (if implemented). +* +* OUTPUT: +* None. +* +* RETURN: +* The vlaue of the erasing counter, 0xffffffff in case the erasing +* counter was not implemented or the sector number is not valid. +* +*******************************************************************************/ +unsigned int mvFSReadErasingCounter(unsigned int sectorNumber) +{ + unsigned int counterValue,sectorBaseAddr,sectorSize; + + if(initializationFlag != FS_FILE_SYSTEM_INITIALIZED) + return 0xffffffff; + if(mvFlash32Rd(mvFlashInfo, mvFSOffset + FS_ERSAING_COUNTER_FLAG_OFFSET) != + FS_ENABLE_ERASING_COUNTER) + return 0xffffffff; + if((sectorBaseAddr = mvFlashSecOffsGet(mvFlashInfo, sectorNumber)) == 0xffffffff) + return 0xffffffff; + if(sectorBaseAddr < mvFSOffset) + return 0xffffffff; + sectorSize = mvFlashSecSizeGet(mvFlashInfo, sectorNumber); + counterValue = mvFlash32Rd(mvFlashInfo, sectorBaseAddr + sectorSize - FS_BLOCK_SIZE); + return counterValue; +} + +/******************************************************************************* +* mvFSGetFreeSize - Returns the number of free bytes in the file system. +* +* DESCRIPTION: +* This function returns the number of free bytes in the entire file +* system. It counts the number of free blocks and dirty blocks ( blocks +* that are no longer in use by any file ) from the begining of the +* file-system to the end , and return that value multiply by block size +* (in bytes). +* NOTE: +* The file system's data base must be initialized by ‘fileSysInit’ +* function before using this function . +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Number of free bytes in the entire file-system on success, 0xFFFFFFFF +* otherwise. +* +*******************************************************************************/ +unsigned int mvFSGetFreeSize() +{ + unsigned int freeBlockOffset,sectorTopOffset,i; + unsigned int sectorNumber,lastSector; + unsigned int dirtyBlocksCounter = 0,dirtyBlocksSector; + unsigned int freeBlocksCounter = 0; + + /* Check if the file system's data base was initialized */ + if(initializationFlag != FS_FILE_SYSTEM_INITIALIZED) + return 0xffffffff; + freeBlockOffset = mvFSOffset + FS_BLOCK_SIZE; + sectorNumber = mvFlashInWhichSec(mvFlashInfo, freeBlockOffset); + lastSector = mvFlashNumOfSecsGet(mvFlashInfo); + dirtyBlocksSector = sectorNumber; + for(i = sectorNumber ; i < lastSector ; i++) + { + sectorTopOffset = mvFlashSecOffsGet(mvFlashInfo, sectorNumber) + + mvFlashSecSizeGet(mvFlashInfo, sectorNumber) - 1; + while(freeBlockOffset < sectorTopOffset) + { + if(mvFlash8Rd(mvFlashInfo, freeBlockOffset + FS_BLOCK_STATUS_FLAG_OFFSET) + == FS_FREE_BLOCK) freeBlocksCounter++; + if(mvFlash8Rd(mvFlashInfo, freeBlockOffset + FS_BLOCK_STATUS_FLAG_OFFSET) + == FS_FREE_DIRTY_BLOCK) dirtyBlocksCounter++; + freeBlockOffset += FS_BLOCK_SIZE; + } + sectorNumber = mvFlashInWhichSec(mvFlashInfo, freeBlockOffset); + } + return (freeBlocksCounter + dirtyBlocksCounter) * + (FS_BLOCK_SIZE - FS_BLOCK_HEADER_SIZE); +} + +/********************************************************************************/ +/********************************************************************************/ +/********************************************************************************/ + +/***********************************************************************/ +/* ask the user to give a file name and chck if the file already exist.*/ +/***********************************************************************/ +MV_VOID get_filename(MV_8 *fileName, MV_BOOL exeType) +{ + int i; + extern MV_8 console_buffer[]; + + while(1) + { + i = 0; + printf("Enter name & extension for the file (maximum %d characters for the name)\n", + FS_FILE_NAME_LENGTH); + readline(" # "); + + strcpy(fileName, console_buffer); + while( i < FS_FILE_NAME_LENGTH && + fileName[i] != '\0' && fileName[i] != ' ') i++; + fileName[i] = '\0'; + if(i == 0) + { + strcpy(fileName,"NoName"); + i = 6; + fileName[i] = '\0'; + } + /* if exe file type */ + if(exeType == MV_TRUE){ + i = 0; + while(fileName[i] != '.' && i < FS_FILE_NAME_LENGTH && + fileName[i] != '\0') i++; + fileName[i] = '.'; + fileName[i+1] = 'e'; + fileName[i+2] = 'x'; + fileName[i+3] = 'e'; + fileName[i+4] = '\0'; + } + + if (mvFSFileFind(fileName) != FS_FILE_NOT_FOUND) + { + printf("File already exists, overwrite? (Y/N)\n"); + readline(" ? "); + if(strcmp(console_buffer,"N") == 0 || strcmp(console_buffer,"no") == 0 || + strcmp(console_buffer,"n") == 0) + { + continue; + } + else + { + if(mvFSDelete(fileName) != FS_FILE_DELETED) + { + printf("File could not be deleted!\n"); + continue; + } + else + { + break; + } + } + } + else + { + break; + } + } + return; +} + +/***********************************************/ +/* load a file to the flash FS using the tftp. */ +/***********************************************/ +int +tftpfs_cmd(cmd_tbl_t *cmdtp, int flag, int argc, MV_8 *argv[]) +{ + int filesize; + MV_8 fileName[CFG_CBSIZE]; + MV_U32 status; + FS_FILE_HANDLER fileHandler; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + load_addr = 0x400000; + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + status = mvFSInit(FS_NO_CACHE); + if(status == FS_NO_VALID_FAT_STRING) + { + printf("ERROR: FS_NO_VALID_FAT_STRING\n"); + return 0; + } + if(status == FS_OFFSET_OUT_OF_RANGE) + { + printf("ERROR: FS_OFFSET_OUT_OF_RANGE\n"); + return 0; + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + + /* done if no file was loaded (no errors though) */ + if (filesize <= 0) + return 0; + + /* get a file name from the user */ + get_filename(fileName,MV_FALSE); + + fileHandler = mvFSOpen(fileName,"w"); + if(fileHandler == FS_FILE_OPEN_ERROR) + { + printf("ERROR: Can't open file!\n"); + return 0; + } + if(mvFSWrite(fileHandler,filesize,(MV_8 *)load_addr) != filesize) + { + printf("ERROR: Writing data to file.\n"); + return 0; + } + printf("File loaded to file system successfully...\n"); + mvFSClose(fileHandler); + + return 1; +} + +U_BOOT_CMD( + FStftp, 2, 1, tftpfs_cmd, + "FStftp - tftp a file to the Flash MV FS\n", + " filename.\n" + "\tDownload a file through the network interface to the DRAM(0x400000) using\n" + "\ttftp, and copy the file to the MV Flash FS.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/***********************************************/ +/* load a file to the flash FS using the tftp. */ +/***********************************************/ +int +tftpefs_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + char fileName[CFG_CBSIZE],c; + unsigned int status, entryAddress; + FS_FILE_HANDLER fileHandler; + unsigned char addressBuffer[8]; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 3) { + entryAddress = simple_strtoul(argv[1], NULL, 16); + load_addr = entryAddress; + copy_filename (BootFile, argv[2], sizeof(BootFile)); + + }else{ + printf ("Usage:\n%s %d\n", cmdtp->usage,argc); + return 0; + } + + status = mvFSInit(FS_NO_CACHE); + if(status == FS_NO_VALID_FAT_STRING) + { + printf("ERROR: FS_NO_VALID_FAT_STRING\n"); + return 0; + } + if(status == FS_OFFSET_OUT_OF_RANGE) + { + printf("ERROR: FS_OFFSET_OUT_OF_RANGE\n"); + return 0; + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + + /* done if no file was loaded (no errors though) */ + if (filesize <= 0) + return 0; + + /* get a file name from the user */ + get_filename(fileName,MV_TRUE); + + fileHandler = mvFSOpen(fileName,"w"); + if(fileHandler == FS_FILE_OPEN_ERROR) + { + printf("ERROR: Can't open file!\n"); + return 0; + } + + /* Set the entry address for the file */ + c = (entryAddress >> 28) & 0x0f; + if(c < 10) + addressBuffer[0] = c + '0'; + else + addressBuffer[0] = c + 'A' - 10; + c = (entryAddress >> 24) & 0x0f; + if(c < 10) + addressBuffer[1] = c + '0'; + else + addressBuffer[1] = c + 'A' - 10; + c = (entryAddress >> 20) & 0x0f; + if(c < 10) + addressBuffer[2] = c + '0'; + else + addressBuffer[2] = c + 'A' - 10; + c = (entryAddress >> 16) & 0x0f; + if(c < 10) + addressBuffer[3] = c + '0'; + else + addressBuffer[3] = c + 'A' - 10; + c = (entryAddress >> 12) & 0x0f; + if(c < 10) + addressBuffer[4] = c + '0'; + else + addressBuffer[4] = c + 'A' - 10; + c = (entryAddress >> 8) & 0x0f; + if(c < 10) + addressBuffer[5] = c + '0'; + else + addressBuffer[5] = c + 'A' - 10; + c = (entryAddress >> 4) & 0x0f; + if(c < 10) + addressBuffer[6] = c + '0'; + else + addressBuffer[6] = c + 'A' - 10; + c = (entryAddress) & 0x0f; + if(c < 10) + addressBuffer[7] = c + '0'; + else + addressBuffer[7] = c + 'A' - 10; + + if(mvFSWrite(fileHandler,8,(char *)addressBuffer)!= 8) + { + printf("ERROR: Writing data to file.\n"); + return 0; + } + + if(mvFSWrite(fileHandler,filesize,(char *)load_addr) != filesize) + { + printf("ERROR: Writing data to file.\n"); + return 0; + } + printf("File loaded to file system successfully...\n"); + mvFSClose(fileHandler); + + return 1; +} + +U_BOOT_CMD( + FStftpe, 3, 1, tftpefs_cmd, + "FStftpe - tftp an exe file to the Flash MV FS\n", + " entry_address filename.\n" + "\tDownload a file through the network interface to entry_address using\n" + "\ttftp, and copy the file to the MV Flash FS.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/**************************************************/ +/* load a file to the flash FS using the loadnet. */ +/**************************************************/ +#if 0 +int +loadfs_cmd(cmd_tbl_t *cmdtp, int flag, int argc, MV_8 *argv[]) +{ + int filesize; + MV_8 fileName[CFG_CBSIZE]; + MV_U32 status,addr = 0x20000; + FS_FILE_HANDLER fileHandler; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + status = mvFSInit(FS_NO_CACHE); + if(status == FS_NO_VALID_FAT_STRING) + { + printf("ERROR: FS_NO_VALID_FAT_STRING\n"); + return 0; + } + if(status == FS_OFFSET_OUT_OF_RANGE) + { + printf("ERROR: FS_OFFSET_OUT_OF_RANGE\n"); + return 0; + } + + filesize = load_net(&addr); + printf("\nFile loaded successfully...\n"); + printf("File size: %d bytes.\n",filesize); + + + /* done if no file was loaded (no errors though) */ + if (filesize <= 0) + return 0; + + /* get a file name from the user */ + get_filename(fileName, MV_FALSE); + + fileHandler = mvFSOpen(fileName,"w"); + if(fileHandler == FS_FILE_OPEN_ERROR) + { + printf("ERROR: Can't open file!\n"); + return 0; + } + if(mvFSWrite(fileHandler,filesize,(MV_8 *)addr) != filesize) + { + printf("ERROR: Writing data to file.\n"); + return 0; + } + printf("File loaded to file system successfully...\n"); + mvFSClose(fileHandler); + + return 1; +} + +U_BOOT_CMD( + FSlf, 1, 1, loadfs_cmd, + "FSlf - Load a file to the Flash MV FS\n", + " \n" + "\tLoad S-Record file via the first available ethernet port, to the DRAM\n" + "\t(0x200000) and copy it to the MV Flash FS.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); +#endif + +/*******************************************************/ +/* load an exe file to the flash FS using the loadnet. */ +/*******************************************************/ +#if 0 +int +loadexefs_cmd(cmd_tbl_t *cmdtp, int flag, int argc, MV_8 *argv[]) +{ + int filesize; + MV_8 fileName[CFG_CBSIZE],c; + MV_U32 status,entryAddress = 0x0; + FS_FILE_HANDLER fileHandler; + MV_U8 addressBuffer[8]; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + status = mvFSInit(FS_NO_CACHE); + if(status == FS_NO_VALID_FAT_STRING) + { + printf("ERROR: FS_NO_VALID_FAT_STRING\n"); + return 0; + } + if(status == FS_OFFSET_OUT_OF_RANGE) + { + printf("ERROR: FS_OFFSET_OUT_OF_RANGE\n"); + return 0; + } + + filesize = load_net(&entryAddress); + printf("\nFile loaded successfully...\n"); + printf("File size: %d bytes.\n",filesize); + + + /* done if no file was loaded (no errors though) */ + if (filesize <= 0) + return 0; + + /* get a file name from the user */ + get_filename(fileName, MV_TRUE); + + fileHandler = mvFSOpen(fileName,"w"); + if(fileHandler == FS_FILE_OPEN_ERROR) + { + printf("ERROR: Can't open file!\n"); + return 0; + } + /* Set the entry address for the file */ + c = (entryAddress >> 28) & 0x0f; + if(c < 10) + addressBuffer[0] = c + '0'; + else + addressBuffer[0] = c + 'A' - 10; + c = (entryAddress >> 24) & 0x0f; + if(c < 10) + addressBuffer[1] = c + '0'; + else + addressBuffer[1] = c + 'A' - 10; + c = (entryAddress >> 20) & 0x0f; + if(c < 10) + addressBuffer[2] = c + '0'; + else + addressBuffer[2] = c + 'A' - 10; + c = (entryAddress >> 16) & 0x0f; + if(c < 10) + addressBuffer[3] = c + '0'; + else + addressBuffer[3] = c + 'A' - 10; + c = (entryAddress >> 12) & 0x0f; + if(c < 10) + addressBuffer[4] = c + '0'; + else + addressBuffer[4] = c + 'A' - 10; + c = (entryAddress >> 8) & 0x0f; + if(c < 10) + addressBuffer[5] = c + '0'; + else + addressBuffer[5] = c + 'A' - 10; + c = (entryAddress >> 4) & 0x0f; + if(c < 10) + addressBuffer[6] = c + '0'; + else + addressBuffer[6] = c + 'A' - 10; + c = (entryAddress) & 0x0f; + if(c < 10) + addressBuffer[7] = c + '0'; + else + addressBuffer[7] = c + 'A' - 10; + + if(mvFSWrite(fileHandler,8,(MV_8 *)addressBuffer)!= 8) + { + printf("ERROR: Writing data to file.\n"); + return 0; + } + + if(mvFSWrite(fileHandler,filesize,(MV_8 *)entryAddress)!= filesize) + { + printf("ERROR: Writing data to file.\n"); + return 0; + } + printf("File loaded to file system successfully...\n"); + mvFSClose(fileHandler); + return 1; +} + +U_BOOT_CMD( + FSlef, 1, 1, loadexefs_cmd, + "FSlef - Load an exe file to the Flash MV FS\n", + " \n" + "\tLoad S-Record EXE file via the first available ethernet port to the DRAM\n" + "\t(0x200000) and copy it to the MV Flash FS.\n" + "\tAfter load is complete the EXE file can be run by using: FSrun filename.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); +#endif + +/********************************************************************************* + * Load Exe file from the Flash FS. + *********************************************************************************/ +MV_U32 loadExe(MV_8 * fname) +{ + register MV_U32 byteCount; + register MV_U32 entryAddress = 0xffffffff; + MV_8 addressBuffer[9]; + FS_FILE_HANDLER fileHandler; + MV_U32 nextBlockPointer, sourceAddress, destAddress, status; + MV_U32 mvFlashBaseAddress; + + mvFlashBaseAddress = MV_BOARD_FLASH_BASE_ADRS; + + status = mvFSInit(FS_NO_CACHE); + if(status == FS_NO_VALID_FAT_STRING) + { + printf("ERROR: FS_NO_VALID_FAT_STRING\n"); + return entryAddress; + } + if(status == FS_OFFSET_OUT_OF_RANGE) + { + printf("ERROR: FS_OFFSET_OUT_OF_RANGE\n"); + return entryAddress; + } + if((fileHandler = mvFSOpen(fname,"r")) == FS_FILE_OPEN_ERROR) + { + printf("ERROR in file open\n"); + return entryAddress; + } + + /* Extract the file's entry address */ + mvFSRead(fileHandler,8,addressBuffer); + addressBuffer[8]='\0'; + entryAddress = simple_strtoul(addressBuffer, NULL, 16); + debug("entryAddress = %x \n",entryAddress); + + nextBlockPointer = mvFlash32Rd(mvFlashInfo, mvFSEntries[fileHandler].pointerToFAT); + /* The First block contain the address, thus treated differently */ + byteCount = FS_BLOCK_SIZE - FS_BLOCK_HEADER_SIZE - 8 /* Address size */ ; + destAddress = entryAddress; + sourceAddress = (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + mvFlashBaseAddress + + FS_BLOCK_HEADER_SIZE + 8/* Address size */; + + /* Flush the block from the cache before executing it */ + debug("memcpy transfer src %x dst %x bytecnt %x\n",\ + sourceAddress,destAddress,byteCount); + memcpy((void *)destAddress, (void *)sourceAddress, byteCount); + destAddress += byteCount; + + nextBlockPointer = mvFlash32Rd(mvFlashInfo, nextBlockPointer & FS_BLOCK_OFFSET_MASK); + byteCount = FS_BLOCK_SIZE - FS_BLOCK_HEADER_SIZE; + + while(nextBlockPointer != 0xffffffff) + { + sourceAddress = (nextBlockPointer & FS_BLOCK_OFFSET_MASK) + mvFlashBaseAddress + + FS_BLOCK_HEADER_SIZE; + + memcpy((MV_U32*)destAddress,(MV_U32*)sourceAddress,byteCount); + + destAddress += byteCount; + nextBlockPointer = mvFlash32Rd(mvFlashInfo, nextBlockPointer & FS_BLOCK_OFFSET_MASK); + } + mvFSClose(fileHandler); + return entryAddress; +} + +int runexeFS_cmd(cmd_tbl_t *cmdtp, int flag, int argc, MV_8 *argv[]) +{ + MV_8 fileName[CFG_CBSIZE]; + MV_U32 i,entryAddress; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc >= 2) { + copy_filename(fileName, argv[1], sizeof(fileName)); + + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + for(i = 0 ; i < FS_FILE_NAME_LENGTH; i++) + { + if(fileName[i] == '.') + break; + if(fileName[i] == '\0') + { + fileName[i] = '.'; + fileName[i+1] = 'e'; + fileName[i+2] = 'x'; + fileName[i+3] = 'e'; + fileName[i+4] = 0; + break; + } + } + if((entryAddress = loadExe(fileName)) == 0xffffffff) + { + printf ("%s: Command not found.\n", fileName); + return 0; + } + mv_go(entryAddress, --argc, &argv[1]); + return 1; +} + +U_BOOT_CMD( + FSrun, CFG_MAXARGS, 1, runexeFS_cmd, + "FSrun - Load an exe file from the Flash MV FS and run it\n", + " filename\n" + "\tLoad an exe file 'filename' from the Flash MV FS and run it.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + + +/****************************************************************************** +* Functionality- The commands allows the user to view the contents of a file +* located in the file system. +*****************************************************************************/ +int type_cmd(cmd_tbl_t *cmdtp, int flag, int argc, MV_8 *argv[]) +{ + MV_8 fileName[128]={},readBuffer[101],key; + FS_FILE_HANDLER fileHandler; + MV_U32 readCount=0, newLineCount=0, flagm,readCounttmp, lineCount=0,i; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 2) { + copy_filename(fileName, argv[1], sizeof(fileName)); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + fileHandler = mvFSOpen(fileName,"r"); + if(fileHandler != FS_FILE_OPEN_ERROR) + { + while(readCount < mvFSFileSize(fileHandler)) + { + readCounttmp = mvFSRead(fileHandler,100,readBuffer); + readBuffer[100] = '\0'; + if(readCounttmp < 100) + readBuffer[readCounttmp] = '\0'; + readCount += readCounttmp; + lineCount += readCounttmp; + for(i = 0 ; i <= readCounttmp ; i++) + if(readBuffer[i] == '\n') + newLineCount++; + printf("%s",readBuffer); + if(newLineCount >= 20 || lineCount > 1600) + { + flagm = 0; + while(1) + { + key = getc(); + switch(key) + { + case ' ': + flagm = 1; + newLineCount = 0; + lineCount = 0; + break; + case 'x': + mvFSClose(fileHandler); + printf("\n"); + return 1; + } + if(flagm == 1) + break; + } + } + } + } + mvFSClose(fileHandler); + printf("\n"); + return 1; +} + +U_BOOT_CMD( + FStype, CFG_MAXARGS, 1, type_cmd, + "FStype - cat file from the Flash MV FS\n", + " filename \n" + "\tDisplay an ascii file 'filename' found on the MV Flash FS.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + + + +/****************************************************************************** +* Functionality- Formats the mvFlash mvMemory at a given offset +*****************************************************************************/ +int format_cmd(cmd_tbl_t *cmdtp, int flag, int argc, MV_8 *argv[]) +{ + MV_U32 offset =0,result; + extern MV_8 console_buffer[]; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 2) { + offset = simple_strtoul(argv[1], NULL, 16); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + printf("\a\a\aThis action will erase the FLASH Memory!!!\n"); + printf("Are you sure (y/n) "); + readline(" ? "); + + if(strcmp(console_buffer,"y") == 0 || strcmp(console_buffer,"yes") == 0 || strcmp(console_buffer,"Y") == 0) + { + if(offset == 0xffffffff) + { + printf("Bad offset!\n"); + } + result = mvFSFormat(offset,FS_NO_ERASING_COUNTER); + if(result == FS_VALID_FILE_SYS_IN_LOWER_OFFSET) + { + printf("ERROR: FS_VALID_FILE_SYS_IN_LOWER_OFFSET\n"); + return 0; + } + if(result == FS_FLASH_MEMORY_NOT_PRESENT) + { + printf("ERROR: FS_FLASH_MEMORY_NOT_PRESENT\n"); + return 1; + } + printf("Flash Memory formated successfully, actual offset is: %x\n" + ,result); + } + return 1; +} + +U_BOOT_CMD( + FSformat, 2, 1, format_cmd, + "FSformat- format the Flash MV FS\n", + " address \n" + "\tInitialize the MV Flash FS starting at offset 'address' in the Flash.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + + +/****************************************************************************** +* Functionality- Display the list of files currently on the system (file name + size) +*****************************************************************************/ +int dir_cmd(cmd_tbl_t *cmdtp, int flag, int argc, MV_8 *argv[]) +{ + MV_U32 fileEntryOffset,nextBlockOffset,mvFSOffset; + MV_U32 status,i,j,spaces = 20; + FS_FILE_HANDLER fileHandler; + MV_8 fileName[20]; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + status = mvFSInit(FS_NO_CACHE); + if(status == FS_NO_VALID_FAT_STRING) + { + printf("ERROR: FS_NO_VALID_FAT_STRING\n"); + return 0; + } + if(status == FS_OFFSET_OUT_OF_RANGE) + { + printf("ERROR: FS_OFFSET_OUT_OF_RANGE\n"); + return 0; + } + if(status != FS_SYSTEM_ALREADY_INITIALIZED) + { + printf("Number of files in system: %d\n",status); + } + + mvFSOffset = mvFSSearchForSignature(); + nextBlockOffset = mvFSOffset; + while(nextBlockOffset != 0xffffffff) + { + /* Skip the block's header */ + fileEntryOffset = nextBlockOffset + FS_FAT_HEADER_SIZE; + for(i = 0 ; i < 15 ; i++) + { + if(mvFlash8Rd(mvFlashInfo, fileEntryOffset + FS_ENTRY_STATUS_FLAG_OFFSET) + == FS_ENTRY_IN_USE) + { + mvFSReadFileNameFromFATentry(fileEntryOffset,fileName); + fileHandler = mvFSOpen(fileName,"r"); + printf("%s",fileName); + spaces = 22 - strlen(fileName); + for(j = 0 ; j < spaces ; j++) + printf(" "); + printf("size: %d bytes\n",mvFSFileSize(fileHandler)); + mvFSClose(fileHandler); + } + /* point to the next entry */ + fileEntryOffset += FS_FAT_FILE_ENTRY_SIZE; + } + nextBlockOffset = mvFlash32Rd(mvFlashInfo, nextBlockOffset); + } + printf("\n %d free bytes\n", + mvFSGetFreeSize()); + return 1; +} + + +U_BOOT_CMD( + FSdir, 1, 1, dir_cmd, + "FSdir - ls the Flash MV FS\n", + " \n" + "\tDisplay the MV Flash FS contents.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/****************************************************************************** +* Functionality- Deletes a file from the system +*****************************************************************************/ +int del_cmd(cmd_tbl_t *cmdtp, int flag, int argc, MV_8 *argv[]) +{ + MV_U32 status; + MV_8 cmd[30]; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 2) { + copy_filename (cmd, argv[1], sizeof(cmd)); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + status = mvFSInit(FS_NO_CACHE); + if(status == FS_NO_VALID_FAT_STRING) + { + printf("ERROR: FS_NO_VALID_FAT_STRING\n"); + return 0; + } + if(status == FS_OFFSET_OUT_OF_RANGE) + { + printf("ERROR: FS_OFFSET_OUT_OF_RANGE\n"); + return 0; + } + if(mvFSFileFind(cmd) != FS_FILE_NOT_FOUND) + { + if(mvFSDelete(cmd) == FS_FILE_DELETED) + { + printf("File deleted\n"); + } + } + else + { + printf("%s:No such file\n",cmd); + } + return 1; +} + +U_BOOT_CMD( + FSdel, 2, 1, del_cmd, + "FSdel - del a file from the Flash MV FS\n", + " filename \n" + "\tDelete a file 'filename' from the MV Flash FS.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + + +#endif /* CONFIG_COMMANDS & CFG_CMD_BSP */ + +#endif /* MV_INC_BOARD_NOR_FLASH */ diff --git a/board/mv_feroceon/USP/mv_fs.h b/board/mv_feroceon/USP/mv_fs.h new file mode 100644 index 0000000..8c0542b --- /dev/null +++ b/board/mv_feroceon/USP/mv_fs.h @@ -0,0 +1,184 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************** +* FileSys.h - Flash file system header +* +* DESCRIPTION: +* File system API for the flash unit integrated within the devices. +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmvFSh +#define __INCmvFSh + +#ifdef __cplusplus +extern "C" { +#endif + +/* defines */ +/* 10 Blocks are dedicated for the FAT, the first one includes the FAT + signature which is 32 Bytes, each file entry is 32 Bytes long , each block + has a header 8 bytes long (in the FAT block the other 24 are not used) => + FS_MAX_NUM_OF_ENTRIES = 150 */ +#define FS_FILE_HANDLER unsigned int +#define FS_MAX_NUM_OF_FAT_BLOCKS 10 +#define FS_MAX_NUM_OF_ENTRIES 150 +#define FS_FAT_SIGNATURE_SIZE 15 +#define FS_SIGNATURE_OFFSET 5 +#define FS_FAT_HEADER_SIZE 32 +#define FS_FAT_FILE_ENTRY_SIZE 32 +#define FS_FILE_SYSTEM_INITIALIZED 0x24136764 +#define FS_FILE_NAME_OFFSET 5 +#define FS_FILE_NAME_LENGTH 16 +#define FS_FILE_EXT_OFFSET (FS_FILE_NAME_OFFSET+ \ + FS_FILE_NAME_LENGTH) +#define FS_FILE_EXT_LENGTH 3 + +#define FS_BLOCK_SIZE 512 +#define FS_BLOCK_HEADER_SIZE 8 +#define FS_BLOCK_OFFSET_MASK 0xfffffe00 +#define FS_BLOCK_OFFSET (0xffffffff - FS_BLOCK_OFFSET_MASK) +#define FS_ERSAING_COUNTER_FLAG_OFFSET (FS_SIGNATURE_OFFSET+ \ + FS_FAT_SIGNATURE_SIZE) +#define FS_BLOCK_STATUS_FLAG_OFFSET 4 +#define FS_BLOCK_OFFSET_FLAG_OFFSET 5 +#define FS_BLOCK_OFFSET_OFFSET 6 +#define FS_NO_FREE_BLOCKS 0xffffffff +#define FS_FREE_BLOCK 0xff +#define FS_BLOCK_IN_UPDATE 0x7f +#define FS_FAT_BLOCK 0x3f +#define FS_BLOCK_IN_USE 0x1f +#define FS_BLOCK_USED_FOR_ERASING_COUNTER 0x01 +#define FS_FREE_DIRTY_BLOCK 0x00 +#define FS_FULL_BLOCK 0x0F + +#define FS_ENTRY_STATUS_FLAG_OFFSET 4 +#define FS_NO_FREE_ENTRIES 0xffffffff +#define FS_FREE_ENTRY 0xff +#define FS_ENTRY_IN_UPDATE 0x7f +#define FS_ENTRY_IN_USE 0x1f +#define FS_FREE_DIRTY_ENTRY 0x00 + +#define FS_FILE_NOT_FOUND 0xffffffff +#define FS_FILE_IS_NOT_CLOSED 0x1 +#define FS_FILE_DELETED 0x2 +#define FS_FILE_EXIST 0x3 +#define FS_ENABLE_ERASING_COUNTER 0X0000ffff +#define FS_NO_ERASING_COUNTER 0Xffffffff +#define FS_NO_VALID_FAT_STRING 0xffffffff +#define FS_OFFSET_OUT_OF_RANGE 0xfffffff0 +#define FS_FLASH_MEMORY_NOT_PRESENT 0xffffffff +#define FS_SYSTEM_ALREADY_INITIALIZED 0xfffffffc +#define FS_VALID_FILE_SYS_IN_LOWER_OFFSET 0xfffffff0 +#define FS_FILE_OPEN_ERROR 0xffffffff +#define FS_FILE_CLOSED 0x1 +#define FS_FILE_CLOSE_ERROR 0xffffffff +#define FS_FILE_READ_ERROR 0xffffffff +/* Cache size = 8 Kb */ +#define FS_NUMBER_OF_BLOCKS_FOR_CACHE 16 +/* Operation mode defined in the call to mvFSInit */ +#define FS_ENABLE_CACHE 1 +#define FS_NO_CACHE 0 +/* Defines for the seek operation */ +/* Beginning of file */ +#define FS_SEEK_SET 0 +/* End of file */ +#define FS_SEEK_END -1 +/* Current position of file pointer */ +#define FS_SEEK_CUR 1 + +/* File entry on the system's dynamic mvMemory */ +typedef struct _fileTableEntry +{ + char mode[4]; + unsigned int pointerToFAT; + unsigned int filePointer; + unsigned int blockPointer; /* For read optimization */ + unsigned int EOFpointer; + unsigned int statusFlag; +} FS_FILE_TABLE_ENTRY; +/* File entry on the FLASH mvMemory (FAT) - 32 Bytes long */ +typedef struct _fileEntry +{ + unsigned int nextBlockAddr; + unsigned int reserved1; + unsigned int reserved2; + char statusFlag; + char fileName[16]; + char fileExt[3]; +} FS_FILE_ENTRY; +/* 8 Bytes long */ +typedef struct _blockHeader +{ + unsigned int nextBlockAddr; + char statusFlag; + char offsetFlag; + unsigned short offset; +} FS_BLOCK_HEADER; +/* Cache properties defines */ +typedef struct _fileCacheBlock +{ + unsigned int fileHandler; + unsigned int currentBlockAddress; + unsigned int usageCounter; + unsigned int timeStamp; + char data[512]; +} FS_FILE_CACHE_BLOCK; + +/* Functions */ + +unsigned int mvFSFormat(unsigned int offset,unsigned int mode); +unsigned int mvFSInit(unsigned int mode); + +FS_FILE_HANDLER mvFSOpen(char * fileName,char *mode); +unsigned int mvFSClose(FS_FILE_HANDLER fileHandler); +unsigned int mvFSDelete(char * fileName); +unsigned int mvFSFileFind(char * fileName); +unsigned int mvFSFileSize(FS_FILE_HANDLER fileHandler); +unsigned int mvFSWrite(FS_FILE_HANDLER fileHandler, + unsigned int numberOfBytes,char * block); +unsigned int mvFSRead(FS_FILE_HANDLER fileHandler, + unsigned int numberOfBytes,char * block); +unsigned int mvFSSeek(FS_FILE_HANDLER fileHandler,int offset,int origin); +unsigned int mvFSRewind(FS_FILE_HANDLER fileHandler); +unsigned int mvFSReadErasingCounter(unsigned int sectorNumber); + +unsigned int mvFSNumOfHandles(char * fileName); +unsigned int mvFSSearchForSignature(void); +unsigned int mvFSGetEOFoffset(char * fileName); +unsigned int mvFSGetFreeEntry(void); +unsigned int mvFSGetFreeBlock(void); +unsigned int mvFSGetFreeBlockForWrite(void); +unsigned int mvFSWriteFileNameToFATentry(unsigned int entryOffset, + char * fileName); +unsigned int mvFSReadFileNameFromFATentry(unsigned int entryOffset, + char * fileName); +unsigned int mvFSGetFreeSize(void); +unsigned int mvFSFlushCache(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __INCmvFSh */ + diff --git a/board/mv_feroceon/USP/mv_i2c.c b/board/mv_feroceon/USP/mv_i2c.c new file mode 100644 index 0000000..d26ead5 --- /dev/null +++ b/board/mv_feroceon/USP/mv_i2c.c @@ -0,0 +1,171 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +#include +#include +#include +#include +#include "twsi/mvTwsi.h" + +#if CONFIG_COMMANDS & CFG_CMD_I2C + +#define MAX_I2C_RETRYS 10 +#define I2C_DELAY 300 /* Should be at least the # of MHz of Tclk */ +#undef DEBUG_I2C +//#define DEBUG_I2C + +#ifdef DEBUG_I2C +#define DP(x) x +#else +#define DP(x) +#endif + +/* Assuming that there is only one master on the bus (us) */ + +void +i2c_init(MV_U8 chanNum, int speed, int slaveaddr) +{ + MV_TWSI_ADDR slave; + slave.type = ADDR7_BIT; + slave.address = slaveaddr; + mvTwsiInit(chanNum, speed, CFG_TCLK, &slave, 0); +} + +/* + * Read interface: + * dev_addr:I2C chip address, range 0..127 + * offset: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * data: Where to read the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int +i2c_read(MV_U8 chanNum, MV_U8 dev_addr, unsigned int offset, int alen, MV_U8* data, int len) +{ + MV_TWSI_SLAVE twsiSlave; + unsigned int i2cFreq = CFG_I2C_SPEED; + DP(puts("i2c_read\n")); + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.slaveAddr.address = dev_addr; + if(alen != 0){ + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = offset; + if(alen == 2) + { + twsiSlave.moreThen256 = MV_TRUE; + } + else + { + twsiSlave.moreThen256 = MV_FALSE; + } + } + + i2c_init(chanNum, i2cFreq,0); /* set the i2c frequency */ + return mvTwsiRead (chanNum, &twsiSlave, data, len); +} + +/* + * Write interface: + * dev_addr:I2C chip address, range 0..127 + * offset: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * data: Where to write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ + +uchar +i2c_write(MV_U8 chanNum, uchar dev_addr, unsigned int offset, int alen, uchar* data, int len) +{ + MV_TWSI_SLAVE twsiSlave; + unsigned int i2cFreq = CFG_I2C_SPEED; + DP(puts("i2c_write\n")); + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.slaveAddr.address = dev_addr; + if(alen != 0){ + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = offset; + if(alen == 2) + { + twsiSlave.moreThen256 = MV_TRUE; + } + else + { + twsiSlave.moreThen256 = MV_FALSE; + } + } + + i2c_init(chanNum, i2cFreq,0); /* set the i2c frequency */ + + return mvTwsiWrite (chanNum, &twsiSlave, data, len); +} + +/* function to determine if an I2C device is present */ +/* chip = device address of chip to check for */ +/* */ +/* returns 0 = sucessful, the device exists */ +/* anything other than zero is failure, no device */ +int i2c_probe (MV_U8 chanNum, uchar chip) +{ + + /* We are just looking for an back. */ + /* To see if the device/chip is there */ + + MV_TWSI_ADDR eepromAddress; + + unsigned int status = 0; + unsigned int i2cFreq = CFG_I2C_SPEED; + + DP(puts("i2c_probe\n")); + + i2c_init(chanNum, i2cFreq,0); /* set the i2c frequency */ + + status = mvTwsiStartBitSet(chanNum); + + if (status) { + DP(printf("Transaction start failed: 0x%02x\n", status)); + mvTwsiStopBitSet(chanNum); + return (int)status; + } + + eepromAddress.type = ADDR7_BIT; + eepromAddress.address = chip; + + status = mvTwsiAddrSet(chanNum, &eepromAddress, MV_TWSI_WRITE); /* send the slave address */ + if (status) { + DP(printf("Failed to set slave address: 0x%02x\n", status)); + mvTwsiStopBitSet(chanNum); + return (int)status; + } + DP(printf("address %#x returned %#x\n",chip,MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)))); + + /* issue a stop bit */ + mvTwsiStopBitSet(chanNum); + + DP(printf("*** successful completion \n")); + return 0; /* successful completion */ +} +#endif diff --git a/board/mv_feroceon/USP/mv_ide.c b/board/mv_feroceon/USP/mv_ide.c new file mode 100644 index 0000000..95c4c7a --- /dev/null +++ b/board/mv_feroceon/USP/mv_ide.c @@ -0,0 +1,1526 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +/* + * IDE support + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mvCtrlEnvLib.h" + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + +#include "sata/CoreDriver/mvOsS.h" +#include "sata/CoreDriver/mvSata.h" +#include "sata/CoreDriver/mvStorageDev.h" + +extern unsigned int whoAmI(void); + +#ifdef MV_LOGGER +char *szModules[] = {"Core Driver", +"BIOS IAL" +}; +#endif + +#undef IDE_DEBUG + +#ifdef IDE_DEBUG +#define DP(fmt,args...) printf (fmt ,##args) +#else +#define DP(fmt,args...) +#endif + +#define SHOW_BOOT_PROGRESS(arg) + +#if defined(MV_INCLUDE_INTEG_SATA) +extern MV_STATUS mvSataWinInit(void); +#endif + +#ifndef MRVL_SATA_BUFF_BOUNDARY +#define MRVL_SATA_BUFF_BOUNDARY (1 << 24) +#endif /* MRVL_SATA_BUFF_BOUNDARY */ + +#define MRVL_SATA_BOUNDARY_MASK (MRVL_SATA_BUFF_BOUNDARY - 1) + +#if (__BE) +void swapATABuffer(unsigned short *buffer, ulong count); +#endif +/* ------------------------------------------------------------------------- */ + +/* Current I/O Device */ +static int curr_device = -1; + + +#define ATA_CURR_BASE(dev) (CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) +#define MV_PM 0xF + +typedef struct mvSataPMDeviceInfo +{ + MV_U16 vendorId; + MV_U16 deviceId; + MV_U8 productRevision; + MV_U8 PMSpecRevision:4; + MV_U8 numberOfPorts:4; +} MV_SATA_PM_DEVICE_INFO; + +typedef struct _MV_CHANNEL_INFO +{ + MV_SATA_DEVICE_TYPE deviceType; + MV_U8 numberOfPorts; + MV_U16 connected; +}MV_CHANNEL_INFO; +typedef struct _HW_ADAPTER_DESCRIPTION +{ + MV_BOOLEAN valid; + int devno; + MV_SATA_ADAPTER mvSataAdapter; /* CoreDriver Adapter data structure*/ + MV_SATA_CHANNEL mvSataChannels[MV_SATA_CHANNELS_NUM]; + MV_CHANNEL_INFO channelInfo[MV_SATA_PM_MAX_PORTS]; +} HW_ADAPTER_DESCRIPTION, *PHW_ADAPTER_DESCRIPTION; + +/* Data structure describing mvSata adapter and channels */ +/* The data structure describes 4 adapters */ +#define MAX_NUM_OF_ADAPTERS 4 +HW_ADAPTER_DESCRIPTION sataAdapters[CFG_IDE_MAXBUS]; +static block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; +static unsigned int ide_initiated=0,ide_detected=0; + +MV_SATA_EDMA_PRD_ENTRY prd_table[2] __attribute__ ((aligned(32))); +unsigned char request_q[MV_EDMA_REQUEST_ENTRY_SIZE] __attribute__ ((aligned(1024))); +unsigned char response_q[MV_EDMA_RESPONSE_ENTRY_SIZE] __attribute__ ((aligned(256))); + +/* ------------------------------------------------------------------------- */ + +static MV_BOOLEAN StartPM(HW_ADAPTER_DESCRIPTION *sataAdapter, MV_U8 channelIndex); + +static MV_BOOLEAN initDisk(MV_SATA_ADAPTER *pSataAdapter, MV_U8 channelIndex, + MV_U8 port, block_dev_desc_t *dev_desc); + +static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); + +static ulong pio_read_write (MV_SATA_ADAPTER *pSataAdapter, + unsigned int channelIndex, + MV_U8 port, + lbaint_t blknr, ulong blkcnt, ulong *buffer, int read); +static +ulong dma_read_write (MV_SATA_ADAPTER *pSataAdapter, + unsigned int channelIndex, + MV_U8 port, + lbaint_t blknr, ulong blkcnt, ulong *buffer, int read); +static +ulong dma_read_write_cmd (MV_SATA_ADAPTER *pSataAdapter, + unsigned int channelIndex, + MV_U8 port, + lbaint_t blknr, ulong blkcnt, ulong *buffer, int read); +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_PCI + +static struct pci_device_id supported[] = { + {MV_SATA_VENDOR_ID, MV_SATA_DEVICE_ID_5080}, + {MV_SATA_VENDOR_ID, MV_SATA_DEVICE_ID_5081}, + {MV_SATA_VENDOR_ID, MV_SATA_DEVICE_ID_5040}, + {MV_SATA_VENDOR_ID, MV_SATA_DEVICE_ID_5041}, + {MV_SATA_VENDOR_ID, MV_SATA_DEVICE_ID_6041}, + {MV_SATA_VENDOR_ID, MV_SATA_DEVICE_ID_6081}, + {MV_SATA_VENDOR_ID, MV_SATA_DEVICE_ID_6042}, + {MV_SATA_VENDOR_ID, MV_SATA_DEVICE_ID_7042}, +}; + +#endif /* CONFIG_PCI */ + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = 0; + + /* Check if we have already called reset or not */ + if (ide_initiated == 0) + { + /* If this is not a call to reset !!!! */ + if (!((argc==2)&&(strncmp(argv[1],"res",3) == 0))) + { + puts ("\nWarning: Please run 'ide reset' before running other ide commands \n\n"); + return 1; + } + } + else /* We have already called reset */ + { + if (ide_detected == 0) + { + puts ("\nno IDE devices available\n"); + return 1; + } + } + + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strncmp(argv[1],"res",3) == 0) { + puts ("\nReset IDE" +#ifdef CONFIG_IDE_8xx_DIRECT + " on PCMCIA " PCMCIA_SLOT_MSG +#endif + ": "); + + ide_init (); + return 0; + } else if (strncmp(argv[1],"inf",3) == 0) { + int i; + + putc ('\n'); + + for (i=0; i= CFG_IDE_MAXDEVICE)) { + puts ("\nno IDE devices available\n"); + return 1; + } + printf ("\nIDE device %x: ", curr_device); + dev_print(&ide_dev_desc[curr_device]); + return 0; + } else if (strncmp(argv[1],"part",4) == 0) { + int dev, ok; + + for (ok=0, dev=0; devusage); + return 1; + case 3: + if (strncmp(argv[1],"dev",3) == 0) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + + printf ("\nIDE device %x: ", dev); + if (dev >= CFG_IDE_MAXDEVICE) { + puts ("unknown device\n"); + return 1; + } + dev_print(&ide_dev_desc[dev]); + /*ide_print (dev);*/ + + if (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN) { + return 1; + } + + curr_device = dev; + + puts ("... is now current device\n"); + + return 0; + } else if (strncmp(argv[1],"part",4) == 0) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + + if (ide_dev_desc[dev].part_type!=PART_TYPE_UNKNOWN) { + print_part(&ide_dev_desc[dev]); + } else { + printf ("\nIDE device %x not available\n", dev); + rcode = 1; + } + return rcode; + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + default: + /* at least 4 args */ + + if (strcmp(argv[1],"read") == 0) { + ulong addr = simple_strtoul(argv[2], NULL, 16); + ulong cnt = simple_strtoul(argv[4], NULL, 16); + ulong n; + + if (curr_device == -1) + { + printf ("\n\nIDE device not available\n"); + return 1; + } +#ifdef CFG_64BIT_STRTOUL + lbaint_t blk = simple_strtoull(argv[3], NULL, 16); + + printf ("\nIDE read: device %x block # %qd, count %ld ... ", + curr_device, blk, cnt); +#else + lbaint_t blk = simple_strtoul(argv[3], NULL, 16); + + printf ("\nIDE read: device %x block # %ld, count %ld ... ", + curr_device, blk, cnt); +#endif + + n = ide_dev_desc[curr_device].block_read (curr_device, + blk, cnt, + (ulong *)addr); + /* flush cache after read */ + flush_cache (addr, cnt*ide_dev_desc[curr_device].blksz); + + printf ("%ld blocks read: %s\n", + n, (n==cnt) ? "OK" : "ERROR"); + if (n==cnt) { + return 0; + } else { + return 1; + } + } else if (strcmp(argv[1],"write") == 0) { + ulong addr = simple_strtoul(argv[2], NULL, 16); + ulong cnt = simple_strtoul(argv[4], NULL, 16); + ulong n; + + if (curr_device == -1) + { + printf ("\n\nIDE device not available\n"); + return 1; + } +#ifdef CFG_64BIT_STRTOUL + lbaint_t blk = simple_strtoull(argv[3], NULL, 16); + + printf ("\nIDE write: device %x block # %qd, count %ld ... ", + curr_device, blk, cnt); +#else + lbaint_t blk = simple_strtoul(argv[3], NULL, 16); + + printf ("\nIDE write: device %x block # %ld, count %ld ... ", + curr_device, blk, cnt); +#endif + + n = ide_write (curr_device, blk, cnt, (ulong *)addr); + + printf ("%ld blocks written: %s\n", + n, (n==cnt) ? "OK" : "ERROR"); + if (n==cnt) { + return 0; + } else { + return 1; + } + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + rcode = 1; + } + + return rcode; + } +} +#endif + +int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *boot_device = NULL; + char *ep; + int dev, part = 0; + ulong cnt; + ulong addr; + disk_partition_t info; + image_header_t *hdr; + int rcode = 0; + + switch (argc) { + case 1: + addr = CFG_LOAD_ADDR; + boot_device = getenv ("bootdevice"); + break; + case 2: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = getenv ("bootdevice"); + break; + case 3: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + if (!boot_device) { + puts ("\n** No boot device **\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + dev = simple_strtoul(boot_device, &ep, 16); + + if (ide_dev_desc[dev].type==DEV_TYPE_UNKNOWN) { + printf ("\n** Device %x not available\n", dev); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + if (*ep) { + if (*ep != ':') { + puts ("\n** Invalid boot device, use `dev[:part]' **\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + part = simple_strtoul(++ep, NULL, 16); + } + if (get_partition_info (&ide_dev_desc[dev], part, &info)) { + SHOW_BOOT_PROGRESS (-1); + return 1; + } + if ((strncmp((const char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) && + (strncmp((const char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) { + printf ("\n** Invalid partition type \"%.32s\"" + " (expect \"" BOOT_PART_TYPE "\")\n", + info.type); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + printf ("\nLoading from IDE device %x, partition %d: " + "Name: %.32s Type: %.32s\n", + dev, part, info.name, info.type); + + DP ("First Block: %ld, # of blocks: %ld, Block Size: %ld\n", + info.start, info.size, info.blksz); + + if (ide_dev_desc[dev].block_read (dev, info.start, 1, (ulong *)addr) != 1) { + printf ("** Read error on %x:%d\n", dev, part); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + hdr = (image_header_t *)addr; + + if (ntohl(hdr->ih_magic) == IH_MAGIC) { + + print_image_hdr (hdr); + + cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); + cnt += info.blksz - 1; + cnt /= info.blksz; + cnt -= 1; + } else { + printf("\n** Bad Magic Number **\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + if (ide_dev_desc[dev].block_read (dev, info.start+1, cnt, + (ulong *)(addr+info.blksz)) != cnt) { + printf ("** Read error on %x:%d\n", dev, part); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + + /* Loading ok, update default load address */ + + load_addr = addr; + + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { + char *local_args[2]; + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + + local_args[0] = argv[0]; + local_args[1] = NULL; + + printf ("Automatic boot of image at addr 0x%08lX ...\n", addr); + + do_bootm (cmdtp, 0, 1, local_args); + rcode = 1; + } + return rcode; +} + +/* ------------------------------------------------------------------------- */ +MV_SATA_DEVICE_TYPE mvGetSataDeviceType( + MV_STORAGE_DEVICE_REGISTERS *mvStorageDevRegisters) +{ + if (((mvStorageDevRegisters->sectorCountRegister & 0xff) != 1) || + ((mvStorageDevRegisters->lbaLowRegister & 0xff) != 1)) + { + return MV_SATA_DEVICE_TYPE_UNKNOWN; + } + if (((mvStorageDevRegisters->lbaMidRegister & 0xff) == 0) && + ((mvStorageDevRegisters->lbaHighRegister & 0xff) == 0)) + { + return MV_SATA_DEVICE_TYPE_ATA_DISK; + } + if ((((mvStorageDevRegisters->lbaMidRegister & 0xff) == 0x14) && + ((mvStorageDevRegisters->lbaHighRegister & 0xff) == 0xEB))/* || + (((mvStorageDevRegisters->lbaMidRegister & 0xff) == 0x69) && + ((mvStorageDevRegisters->lbaHighRegister & 0xff) == 0x96))*/) + { + return MV_SATA_DEVICE_TYPE_ATAPI_DEVICE; + } + if (((mvStorageDevRegisters->lbaMidRegister & 0xff) == 0x69) && + ((mvStorageDevRegisters->lbaHighRegister & 0xff) == 0x96)) + { + return MV_SATA_DEVICE_TYPE_PM; + } + return MV_SATA_DEVICE_TYPE_UNKNOWN; +} + +MV_BOOLEAN mvGetPMDeviceInfo(MV_SATA_ADAPTER *pSataAdapter, + MV_U8 channelIndex, + MV_SATA_PM_DEVICE_INFO *pPMDeviceInfo) +{ + MV_U32 regVal; + + if (mvPMDevReadReg(pSataAdapter, channelIndex, MV_SATA_PM_CONTROL_PORT, + MV_SATA_GSCR_ID_REG_NUM, ®Val, NULL) == MV_FALSE) + { + printf("Error [%d %d]: Failed to read PM GSCR ID register\n", + pSataAdapter->adapterId, channelIndex); + return MV_FALSE; + } + pPMDeviceInfo->vendorId = (MV_U16)(regVal & 0xffff); + pPMDeviceInfo->deviceId = (MV_U16)((regVal & 0xffff0000) >> 16); + + if (mvPMDevReadReg(pSataAdapter, channelIndex, MV_SATA_PM_CONTROL_PORT, + MV_SATA_GSCR_REVISION_REG_NUM, ®Val, NULL)== MV_FALSE) + { + printf("Error:[%d %d]: Failed to read PM GSCR REVISION register\n", pSataAdapter->adapterId, + channelIndex); + return MV_FALSE; + } + pPMDeviceInfo->PMSpecRevision = (MV_U8)(regVal & 0xff); + pPMDeviceInfo->productRevision = (MV_U8)((regVal & 0xff00) >> 8); + + if (mvPMDevReadReg(pSataAdapter, channelIndex, MV_SATA_PM_CONTROL_PORT, + MV_SATA_GSCR_INFO_REG_NUM, ®Val, NULL)== MV_FALSE) + { + printf("Error: [%d %d]: Failed to read PM GSCR INFO\n", pSataAdapter->adapterId, + channelIndex); + return MV_FALSE; + } + pPMDeviceInfo->numberOfPorts = (MV_U8)(regVal & 0xf); + return MV_TRUE; +} + +static MV_BOOLEAN +StartPM(HW_ADAPTER_DESCRIPTION *sataAdapter, + MV_U8 channelIndex) +{ + MV_SATA_ADAPTER *pSataAdapter = &sataAdapter->mvSataAdapter; + MV_U8 PMPort; + MV_SATA_PM_DEVICE_INFO PMInfo; + + if (mvGetPMDeviceInfo(pSataAdapter, channelIndex, &PMInfo) == MV_FALSE) { + printf("Error: Failed to get PortMultiplier Info\n", + pSataAdapter->adapterId, channelIndex); + return MV_FALSE; + } + printf("Port Multiplier found @ %d %d. Vendor: %04x ports: %d\n", + pSataAdapter->adapterId, channelIndex, PMInfo.vendorId, + PMInfo.numberOfPorts); + + for (PMPort = 0; PMPort < PMInfo.numberOfPorts; PMPort++){ + MV_U32 SStatus; + /* + * Skip PMPort #0 - this should be already enabled due to legacy mode + * transition of PM + */ + if (PMPort >= 0) { + if (mvPMDevEnableStaggeredSpinUp(pSataAdapter, channelIndex, + PMPort) == MV_FALSE){ + printf("Error:[%d %d %d]: EnableStaggeredSpinUp Failed\n", + pSataAdapter->adapterId, channelIndex, PMPort); + if (mvStorageDevATASoftResetDevice(pSataAdapter, channelIndex, + MV_SATA_PM_CONTROL_PORT, NULL) == MV_FALSE) + { + printf("Error: [%d %d]: failed to Soft Reset PM control port\n" + , pSataAdapter->adapterId, channelIndex); + } + continue; + } + } + if (mvPMDevReadReg(pSataAdapter, channelIndex, PMPort, + MV_SATA_PSCR_SSTATUS_REG_NUM, &SStatus, NULL) == + MV_FALSE) + { + printf("Error:[%d %d %d]: mvPMDevReadReg Failed\n", + pSataAdapter->adapterId, channelIndex, PMPort); + if (mvStorageDevATASoftResetDevice(pSataAdapter, channelIndex, + MV_SATA_PM_CONTROL_PORT, NULL) == MV_FALSE) + { + printf("Error: [%d %d]: failed to Soft Reset PM control port\n" + , pSataAdapter->adapterId, channelIndex); + } + continue; + } + DP("[%d %d %x]: S-Status: 0x%x\n", pSataAdapter->adapterId, + channelIndex, PMPort, SStatus); + if ((SStatus & 0xf) == 3){ + MV_STORAGE_DEVICE_REGISTERS ATARegs; + if (mvPMDevWriteReg(pSataAdapter, channelIndex, PMPort, + MV_SATA_PSCR_SERROR_REG_NUM, 0xffffffff, NULL) == MV_FALSE) + { + printf("Error [%d %d %d]: PM Write SERROR Failed\n", + pSataAdapter->adapterId, channelIndex, PMPort); + continue; + } + + if (mvStorageDevATASoftResetDevice(pSataAdapter, + channelIndex, PMPort, &ATARegs) == MV_FALSE) + { + printf("Error - SRST for port %d on channel %d failed\n", PMPort, channelIndex); + return MV_FALSE; + } + if(mvGetSataDeviceType(&ATARegs) == MV_SATA_DEVICE_TYPE_ATA_DISK) + { + sataAdapter->channelInfo[channelIndex].connected |= 1 << PMPort; + } + } + } + sataAdapter->channelInfo[channelIndex].numberOfPorts = PMInfo.numberOfPorts; + return MV_TRUE; +} + + +static MV_BOOLEAN StartChannel(HW_ADAPTER_DESCRIPTION *sataAdapter, + MV_U8 channelIndex) +{ + MV_SATA_ADAPTER *pSataAdapter = &sataAdapter->mvSataAdapter; + MV_STORAGE_DEVICE_REGISTERS ATARegs; + MV_SATA_CHANNEL *pSataChannel; + MV_SATA_DEVICE_TYPE deviceType; + + pSataChannel = pSataAdapter->sataChannel[channelIndex]; + if (!pSataChannel) + { + printf ("Error in StartChannel - Channel data structure is null\n"); + return MV_FALSE; + } + if (mvStorageDevATASoftResetDevice(pSataAdapter, + channelIndex, MV_PM, &ATARegs) == MV_FALSE) + { + printf("Error - Failed initializing(SRST) drive on channel %d\n", channelIndex); + return MV_FALSE; + } + deviceType = mvGetSataDeviceType(&ATARegs); + mvStorageDevSetDeviceType(pSataAdapter, channelIndex,deviceType); + sataAdapter->channelInfo[channelIndex].deviceType = deviceType; + sataAdapter->channelInfo[channelIndex].numberOfPorts = 0; + sataAdapter->channelInfo[channelIndex].connected = 0; + switch(deviceType) + { + case MV_SATA_DEVICE_TYPE_UNKNOWN: + printf("Error - unknown device at channel %d\n", channelIndex); + return MV_FALSE; + case MV_SATA_DEVICE_TYPE_ATAPI_DEVICE: + printf("Error - unknown device at channel %d\n", channelIndex); + return MV_FALSE; + case MV_SATA_DEVICE_TYPE_ATA_DISK: + sataAdapter->channelInfo[channelIndex].numberOfPorts = 1; + sataAdapter->channelInfo[channelIndex].connected = 1; + return MV_TRUE; + case MV_SATA_DEVICE_TYPE_PM: + return StartPM(sataAdapter, channelIndex); + } + + return MV_TRUE; +} +static MV_BOOLEAN initDisk(MV_SATA_ADAPTER *pSataAdapter, MV_U8 channelIndex, + MV_U8 port, block_dev_desc_t *dev_desc) +{ + MV_STORAGE_DEVICE_REGISTERS ATARegs; + ulong identifyBuffer[ATA_SECTORWORDS]; + hd_driveid_t *iop = (hd_driveid_t *)identifyBuffer; + MV_U16_PTR iden = (MV_U16_PTR) identifyBuffer; + MV_U8 PIOMode; + MV_U8 UDMAMode; + MV_SATA_DEVICE_TYPE deviceType = mvStorageDevGetDeviceType(pSataAdapter,channelIndex); + if (deviceType == MV_SATA_DEVICE_TYPE_PM) + { +#if 0 + if (mvStorageDevATASoftResetDevice(pSataAdapter, + channelIndex, port, &ATARegs) == MV_FALSE) + { + printf("Error - SRST for port %d on channel %d failed\n", port, channelIndex); + return MV_FALSE; + } + if(mvGetSataDeviceType(&ATARegs) != MV_SATA_DEVICE_TYPE_ATA_DISK) + { + return MV_FALSE; + } +#endif + } + + /* identify device*/ + memset(&ATARegs, 0, sizeof(ATARegs)); + ATARegs.commandRegister = MV_ATA_COMMAND_IDENTIFY; + if (mvStorageDevATAIdentifyDevice(pSataAdapter, channelIndex, port, + (unsigned short *)identifyBuffer) == MV_FALSE) + { + printf("[%d %d %d]: failed to perform ATA Identify command\n", pSataAdapter->adapterId, + channelIndex, port); + return MV_FALSE; + } + /* Check if read look ahead is supported. If so enable it */ + if (iden[IDEN_SUPPORTED_COMMANDS1] & MV_BIT6) + { + if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, port, + MV_ATA_SET_FEATURES_ENABLE_RLA,0,0,0, 0) == MV_FALSE) + { + printf("[%d %d %d]: failed to perform Enable RLA command\n", pSataAdapter->adapterId, + channelIndex, port); + return MV_FALSE; + } + } + if ((iden[IDEN_VALID] & MV_BIT1) == 0) + { + printf("[%d %d %d]: Unable to find PIO Mode\n", pSataAdapter->adapterId, channelIndex, port); + return MV_FALSE; + } + else if (iden[IDEN_PIO_MODE_SPPORTED] & MV_BIT0) + { + PIOMode = MV_ATA_TRANSFER_PIO_3; + } + else if (iden[IDEN_PIO_MODE_SPPORTED] & MV_BIT1) + { + PIOMode = MV_ATA_TRANSFER_PIO_4; + } + else + { + printf("[%d %d %d]: PIO modes 3 and 4 are not supported\n", pSataAdapter->adapterId, channelIndex, port); + PIOMode = MV_ATA_TRANSFER_PIO_SLOW; + } + if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, port, + MV_ATA_SET_FEATURES_TRANSFER,PIOMode,0,0, 0) == MV_FALSE) + { + printf("[%d %d %d]: failed to enable PIO mode\n", + pSataAdapter->adapterId, channelIndex, port); + return MV_FALSE; + } + + if (iden[IDEN_UDMA_MODE] & MV_BIT6) + { + UDMAMode = MV_ATA_TRANSFER_UDMA_6; + } + else if (iden[IDEN_UDMA_MODE] & MV_BIT5) + { + UDMAMode = MV_ATA_TRANSFER_UDMA_5; + } + else if (iden[IDEN_UDMA_MODE] & MV_BIT4) + { + UDMAMode = MV_ATA_TRANSFER_UDMA_4; + } + else + { + UDMAMode = MV_ATA_TRANSFER_UDMA_4; + } + + if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, port, + MV_ATA_SET_FEATURES_TRANSFER, + UDMAMode, + 0,0, 0) == MV_FALSE) + { + printf("[%d %d %d]: failed to perform Enable DMA mode\n", + pSataAdapter->adapterId, channelIndex, port); + return MV_FALSE; + } + printf("[%d %d %d]: Enable DMA mode (%d)\n", pSataAdapter->adapterId, channelIndex, port, UDMAMode - MV_ATA_TRANSFER_UDMA_0); + /* Continue parsing identify buffer*/ + int device; + device=dev_desc->dev; + printf (" Device %d @ %d %d", device, pSataAdapter->adapterId, channelIndex); + if(deviceType == MV_SATA_DEVICE_TYPE_PM) + printf(" %d:\n", port); + else + printf(":\n"); + + ident_cpy (dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision)); + ident_cpy (dev_desc->vendor, iop->model, sizeof(dev_desc->vendor)); + ident_cpy (dev_desc->product, iop->serial_no, sizeof(dev_desc->product)); + + if ((iop->config & 0x0080)==0x0080) + dev_desc->removable = 1; + else + dev_desc->removable = 0; + +#ifdef __BIG_ENDIAN + /* swap shorts */ + dev_desc->lba = (iop->lba_capacity << 16) | (iop->lba_capacity >> 16); +#else /* ! __BIG_ENDIAN */ + dev_desc->lba = iop->lba_capacity; +#endif /* __BIG_ENDIAN */ + +#ifdef CONFIG_LBA48 + if (iop->command_set_2 & 0x0400) { /* LBA 48 support */ + dev_desc->lba48 = 1; + dev_desc->lba = (unsigned long long)iop->lba48_capacity[0] | + ((unsigned long long)iop->lba48_capacity[1] << 16) | + ((unsigned long long)iop->lba48_capacity[2] << 32) | + ((unsigned long long)iop->lba48_capacity[3] << 48); + } else { + dev_desc->lba48 = 0; + } +#endif /* CONFIG_LBA48 */ + + /* assuming HD */ + dev_desc->type=DEV_TYPE_HARDDISK; + dev_desc->blksz=ATA_BLOCKSIZE; + dev_desc->lun=0; /* just to fill something in... */ + + return MV_TRUE; +} + +void +InitChannel( + PHW_ADAPTER_DESCRIPTION HwDeviceExtension, + MV_U8 channelIndex) +{ + MV_SATA_ADAPTER *pSataAdapter = &(HwDeviceExtension->mvSataAdapter); + MV_SATA_CHANNEL *pSataChannel; + + pSataChannel = &HwDeviceExtension->mvSataChannels[channelIndex]; + pSataAdapter->sataChannel[channelIndex] = pSataChannel; + pSataChannel->channelNumber = channelIndex; + pSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *)request_q; + pSataChannel->requestQueuePciLowAddress = (MV_U32)request_q; + pSataChannel->requestQueuePciHiAddress = 0; + pSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) response_q; + pSataChannel->responseQueuePciLowAddress = (MV_U32)response_q; + pSataChannel->responseQueuePciHiAddress = 0; +} + +MV_BOOLEAN +mvSataEventNotify(MV_SATA_ADAPTER *pSataAdapter, MV_EVENT_TYPE eventType, + MV_U32 param1, MV_U32 param2) +{ + + switch (eventType) + { + case MV_EVENT_TYPE_SATA_CABLE: + switch(param1) + { + case MV_SATA_CABLE_EVENT_CONNECT: + printf("[%d,%d]: device connected event received\n", + pSataAdapter->adapterId, param2); + break; + case MV_SATA_CABLE_EVENT_DISCONNECT: + printf("[%d,%d]: device disconnected event received \n", + pSataAdapter->adapterId, param2); + break; + case MV_SATA_CABLE_EVENT_PM_HOT_PLUG: + printf("[%d,%d]: Port Multiplier hotplug event received \n", + pSataAdapter->adapterId, param2); + break; + default: + printf( "illegal value for param1(%d) at " + "connect/disconect event, host=%d\n", param1, + pSataAdapter->adapterId ); + } + break; + case MV_EVENT_TYPE_ADAPTER_ERROR: + printf("DEVICE error event received, pci cause " + "reg=%x, don't know how to handle this\n", param1); + return MV_TRUE; + case MV_EVENT_TYPE_SATA_ERROR: + switch (param1) + { + case MV_SATA_RECOVERABLE_COMMUNICATION_ERROR: + printf(" [%d %d] sata recoverable error occured\n", + pSataAdapter->adapterId, param2); + break; + case MV_SATA_UNRECOVERABLE_COMMUNICATION_ERROR: + printf(" [%d %d] sata unrecoverable error occured, restart channel\n", + pSataAdapter->adapterId, param2); + break; + case MV_SATA_DEVICE_ERROR: + printf( " [%d %d] device error occured\n", + pSataAdapter->adapterId, param2); + break; + } + break; + default: + printf(" adapter %d unknown event %d" + " param1= %x param2 = %x\n", pSataAdapter->adapterId, + eventType - MV_EVENT_TYPE_ADAPTER_ERROR, param1, param2); + return MV_FALSE; + + }/*switch*/ + + return MV_TRUE; +} + +/* ------------------------------------------------------------------------- */ +#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) +#if defined(CONFIG_BUFFALO_PLATFORM) +MV_BOOL hdd_found = MV_FALSE; +#endif + +void ide_init (void) +{ + int j, numOfDrives; + int idx = 0; + unsigned int temp, initAdapterResult, pciCommand; + unsigned short stemp; + MV_SATA_ADAPTER *pMvSataAdapter; + int devno = -1; + unsigned char channelIndex; + unsigned int numOfIdeDev = 0; + unsigned int numOfAdapters = 0; + MV_BOOLEAN integratedSataDetected = MV_FALSE; + MV_BOOLEAN integratedSataInitialized = MV_FALSE; + int intSataAccess = 0; + int pexSataAccess = 0; + char *env; +#if defined(CONFIG_BUFFALO_PLATFORM) + hdd_found = MV_FALSE; +#endif + +#ifdef MV78200 + /* Check in dual CPU system which CPU use integrated SATA */ + if (mvSocUnitIsMappedToThisCpu(SATA)) + intSataAccess = 1; + + /* Check in dual CPU system which CPU use integrated SATA */ + if ( (mvSocUnitIsMappedToThisCpu(PEX00)) || (mvSocUnitIsMappedToThisCpu(PEX10)) ) + pexSataAccess = 1; +#else + intSataAccess = 1; + pexSataAccess = 1; +#endif + +#ifdef MV_LOGGER +#if defined (MV_LOG_DEBUG) + mvLogRegisterModule(MV_CORE_DRIVER_LOG_ID, 0x1FF, + szModules[MV_CORE_DRIVER_LOG_ID]); +#elif defined (MV_LOG_ERROR) + mvLogRegisterModule(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + szModules[MV_CORE_DRIVER_LOG_ID]); +#endif +#endif + curr_device = -1; + + memset(sataAdapters,0, sizeof(HW_ADAPTER_DESCRIPTION)*CFG_IDE_MAXBUS); + /* Init ide structure */ + for(j = 0; j < CFG_IDE_MAXDEVICE; j++) + { + ide_dev_desc[j].type=DEV_TYPE_UNKNOWN; + ide_dev_desc[j].if_type=IF_TYPE_IDE; + ide_dev_desc[j].dev=j; + ide_dev_desc[j].part_type=PART_TYPE_UNKNOWN; + ide_dev_desc[j].blksz=0; + ide_dev_desc[j].lba=0; + ide_dev_desc[j].block_read=ide_read; + } + + while ((numOfIdeDev < CFG_IDE_MAXDEVICE) && (numOfAdapters < CFG_IDE_MAXBUS)) { + MV_BOOLEAN integratedSataDevice = MV_FALSE; + numOfDrives = 0; + + #if defined(MV_INCLUDE_INTEG_SATA) + if(intSataAccess) + if (integratedSataInitialized != MV_TRUE) + { + printf("\nMarvell Serial ATA Adapter\n"); + if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, 0)) + { + printf("Warning Integrated SATA is Powered Off\n"); + } + else + { + integratedSataDetected = MV_TRUE; + integratedSataDevice = MV_TRUE; + + mvSataWinInit(); + printf("Integrated Sata device found\n"); + } + } + #endif + + +#ifdef CONFIG_PCI + if(pexSataAccess) + { + if ((integratedSataDetected == MV_FALSE) || + (integratedSataInitialized == MV_TRUE)) + { + /* Find PCI device(s) */ + if ((devno = pci_find_devices(supported, idx++)) < 0) { + if(!numOfAdapters) printf("no device found \n"); + break; + } + } + } +#endif /* CONFIG_PCI */ + + integratedSataInitialized = MV_TRUE; + sataAdapters[numOfAdapters].devno = devno; + sataAdapters[numOfAdapters].valid = MV_TRUE; + + memset (&sataAdapters[numOfAdapters].mvSataAdapter, 0, sizeof(MV_SATA_ADAPTER)); + pMvSataAdapter = &sataAdapters[numOfAdapters].mvSataAdapter; + + if (integratedSataDevice == MV_TRUE){ + pMvSataAdapter->adapterIoBaseAddress = INTER_REGS_BASE + SATA_REG_BASE - 0x20000; + pMvSataAdapter->pciConfigDeviceId = mvCtrlModelGet(); + pMvSataAdapter->pciConfigRevisionId = 0; + } +#ifdef CONFIG_PCI + else{ + if(pexSataAccess) + { + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 ,&temp); + pMvSataAdapter->adapterIoBaseAddress = bus_to_phys(devno, (temp & 0xfffffff0)); + pci_read_config_word(devno, PCI_DEVICE_ID, &stemp); + pMvSataAdapter->pciConfigDeviceId = stemp; + pci_read_config_word(devno, PCI_REVISION_ID, &stemp); + pMvSataAdapter->pciConfigRevisionId = stemp & 0xff; + } + } +#endif /*CONFIG_PCI */ + + pMvSataAdapter->adapterId = numOfAdapters; + + pMvSataAdapter->intCoalThre[0]= 4; + pMvSataAdapter->intCoalThre[1]= 4; + pMvSataAdapter->intTimeThre[0] = 150*50 ; + pMvSataAdapter->intTimeThre[1] = 150*50; + pMvSataAdapter->mvSataEventNotify = mvSataEventNotify; + pMvSataAdapter->IALData = (void *)&sataAdapters[numOfAdapters]; + pMvSataAdapter->pciSerrMask = MV_PCI_SERR_MASK_REG_ENABLE_ALL; + pMvSataAdapter->pciInterruptMask = 0; + pMvSataAdapter->pciCommand = MV_PCI_COMMAND_REG_DEFAULT; + +#ifdef CONFIG_PCI + if (integratedSataDevice != MV_TRUE) { + if(pexSataAccess) + { + /* Enable master / IO / Memory accesses */ + pci_read_config_dword(devno, PCI_COMMAND ,&pciCommand); + pci_write_config_dword(devno, PCI_COMMAND, pciCommand | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + printf("Found adapter at bus %d, device %d ... Scanning channels\n",PCI_BUS(devno), PCI_DEV(devno)); + } + } +#endif /*CONFIG_PCI */ + + /* Check if found adapter */ + if( (integratedSataDetected == MV_FALSE) && (devno == -1) ) + { + printf("no device found \n"); + break; + } + + /* Check if found adapter over PEX/PCI */ + if( (numOfAdapters > 0) && (devno == -1) ) + break; + + /* Init adapter */ + initAdapterResult = mvSataInitAdapter(pMvSataAdapter); + if (initAdapterResult == MV_FALSE){ + printf("Error Initializing SATA Adapter\n"); + sataAdapters[numOfAdapters].valid = MV_FALSE; + numOfAdapters ++; + continue; + } + + /* Enable staggered spin-up of all SATA channels */ + if (mvSataEnableStaggeredSpinUpAll(pMvSataAdapter) == MV_FALSE) { + printf("Error in mvSataEnableStaggeredSpinUpAll\n"); + sataAdapters[numOfAdapters].valid = MV_FALSE; + numOfAdapters ++; + continue; + } + /* when sending DMA command we poll interrupt for completion*/ + mvSataUnmaskAdapterInterrupt(pMvSataAdapter); + + /* find and init channels */ + for (channelIndex = 0 ; channelIndex < pMvSataAdapter->numberOfChannels ; channelIndex++) { + if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channelIndex, NULL) == + MV_TRUE){ + DP("Channel %x is connected ... ", channelIndex); + InitChannel(&sataAdapters[numOfAdapters], channelIndex); + if (mvSataConfigureChannel(pMvSataAdapter, channelIndex) == + MV_FALSE) + { + printf("Error in mvSataConfigureChannel on channel %d\n",channelIndex); + pMvSataAdapter->sataChannel[channelIndex] = NULL; + numOfIdeDev++; + + } + else if (StartChannel(&sataAdapters[numOfAdapters], + channelIndex) == MV_FALSE){ + printf ("Failed initializing storage deivce connected " + "to SATA channel %d\n",channelIndex); + pMvSataAdapter->sataChannel[channelIndex] = NULL; + numOfIdeDev++; + }else{ + int port; + MV_CHANNEL_INFO *channelInfo=&sataAdapters[numOfAdapters].channelInfo[channelIndex]; + for(port = 0; port < channelInfo->numberOfPorts; port++){ + if(!(channelInfo->connected & (1 << port))) + { + numOfIdeDev++; + continue; + } + + if(initDisk(pMvSataAdapter, channelIndex, port, &ide_dev_desc[numOfIdeDev]) == MV_FALSE){ + /* mark it as not connected */ + sataAdapters[numOfAdapters].channelInfo[channelIndex].connected &= ~(1 << port); + numOfIdeDev++; + continue; + } + dev_print(&ide_dev_desc[numOfIdeDev]); + if ((ide_dev_desc[numOfIdeDev].lba > 0) && + (ide_dev_desc[numOfIdeDev].blksz > 0)) + { + /* initialize partition type */ + init_part (&ide_dev_desc[numOfIdeDev]); + if (curr_device < 0) + curr_device = numOfIdeDev; + } + numOfDrives++; + numOfIdeDev++; +#if defined(CONFIG_BUFFALO_PLATFORM) + hdd_found = MV_TRUE; +#endif + } + } + }else{ + pMvSataAdapter->sataChannel[channelIndex] = NULL; + sataAdapters[numOfAdapters].channelInfo[channelIndex].numberOfPorts = 1; + numOfIdeDev++; + } + + } + + numOfAdapters++; + } + + ide_detected = numOfIdeDev; + ide_initiated=1; + + putc ('\n'); +} + +/* ------------------------------------------------------------------------- */ + +block_dev_desc_t * ide_get_dev(int dev) +{ + return ((block_dev_desc_t *)&ide_dev_desc[dev]); +} + +/* ------------------------------------------------------------------------- */ + +ulong ide_read_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer, int read) +{ + MV_SATA_ADAPTER *pSataAdapter = NULL; + unsigned int channelIndex = 0; + unsigned int adapter; + int port; + char *env; + + /* read count is 0 no read is needed */ + if(blkcnt == 0) { + return 0; + } + + /* data buffer must be 2 bytes aligned */ + if((long)buffer & 1) { + printf("\nide error: address (0x%08p) is not 2 bytes aligned!\n",buffer); + return 0; + } + + + DP("ide %s: device %x, blknr %x blkcnt %x, buffer %x\n", + ((read)?"read":"write"),device, (unsigned int)blknr, blkcnt, (unsigned int)buffer); + /* find device */ + for(adapter = 0 ; adapter < CFG_IDE_MAXBUS; adapter++) + { + if(sataAdapters[adapter].valid == MV_FALSE) + continue; + + pSataAdapter = &(sataAdapters[adapter].mvSataAdapter); + + for(channelIndex = 0; channelIndex < pSataAdapter->numberOfChannels; channelIndex++) + { + for(port = 0; port < sataAdapters[adapter].channelInfo[channelIndex].numberOfPorts; port++) + { + if(device == 0) + goto found_device; + + device--; + } + } + } + +found_device: + if(adapter == CFG_IDE_MAXBUS) + { + printf("Error didn't find requested device (%d).\n", device); + return 0; + } + if(pSataAdapter->sataChannel[channelIndex] == NULL) + { + printf("Error No HD connection \n"); + return 0; + } + + env = getenv("sata_dma_mode"); + if(( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) )){ + return dma_read_write(pSataAdapter, channelIndex, port, + blknr, blkcnt, buffer, read); + }else { + return pio_read_write(pSataAdapter, channelIndex, port, + blknr, blkcnt, buffer, read); + } +} + +static +ulong pio_read_write (MV_SATA_ADAPTER *pSataAdapter, + unsigned int channelIndex, + MV_U8 port, + lbaint_t blknr, ulong blkcnt, ulong *buffer, int read) +{ + MV_STORAGE_DEVICE_REGISTERS inATARegs; + MV_STORAGE_DEVICE_REGISTERS outATARegs; + MV_BOOLEAN isExt = MV_FALSE; + unsigned int command; + ulong blk_transferred = 0; + + +#if (__BE) + if(read == 0) + swapATABuffer((unsigned short *)buffer, blkcnt * ATA_SECTOR_SIZE); +#endif + + /* read all blocks */ + while(blkcnt > 0) { + ulong cmd_blkcnt = (blkcnt > 128 ) ? 128 : blkcnt; + + /* Set transfer mode */ + memset(&inATARegs, 0, sizeof(inATARegs)); + memset(&outATARegs, 0, sizeof(outATARegs)); + inATARegs.commandRegister = (read)? MV_ATA_COMMAND_READ_SECTORS: MV_ATA_COMMAND_WRITE_SECTORS; + inATARegs.sectorCountRegister = cmd_blkcnt; + inATARegs.lbaLowRegister = ((blknr >> 0) & 0xFF); + inATARegs.lbaMidRegister = ((blknr >> 8) & 0xFF); + inATARegs.lbaHighRegister = ((blknr >> 16) & 0xFF); + inATARegs.deviceRegister = BIT6 | ((blknr >> 24) & 0xF); + +#ifdef CONFIG_LBA48 + /* more than 28 bits used, use 48bit mode */ + if (blknr & IDE_BLOCK_NUMBER_MASK) { + inATARegs.commandRegister = (read)? MV_ATA_COMMAND_READ_SECTORS_EXT : MV_ATA_COMMAND_WRITE_SECTORS_EXT; + inATARegs.lbaLowRegister |= ((blknr >> LBA_LOW_REG_SHIFT) & 0xFF) << 8; + inATARegs.lbaMidRegister |= ((blknr >> LBA_MID_REG_SHIFT) & 0xFF) << 8; + inATARegs.lbaHighRegister |= ((blknr >> LBA_HIGH_REG_SHIFT) & 0xFF) << 8; + inATARegs.deviceRegister = BIT6; + isExt = MV_TRUE; + } +#endif + command = (read)? MV_NON_UDMA_PROTOCOL_PIO_DATA_IN: MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT; + if (mvStorageDevExecutePIO(pSataAdapter, channelIndex, port, command, + isExt, (MV_U16 *)buffer, (cmd_blkcnt * 512)/2 , &inATARegs, &outATARegs) == MV_FALSE) + { + printf("[%d %d]: %s Fail for PIO\n", + pSataAdapter->adapterId, channelIndex, ((read)?"Read":"Write")); + return 0; + } + blknr += cmd_blkcnt; + blkcnt = blkcnt - cmd_blkcnt; + buffer += (cmd_blkcnt * ATA_SECTORWORDS); + blk_transferred += cmd_blkcnt; + } +#if (__BE) + swapATABuffer((unsigned short *)buffer, blkcnt * ATA_SECTOR_SIZE); +#endif + + return blk_transferred; +} +static int command_completed; +static MV_COMPLETION_TYPE completion_type; +static +MV_BOOLEAN cmd_callback(struct mvSataAdapter *pSataAdapter, + MV_U8 channel_index, + MV_COMPLETION_TYPE type, + MV_VOID_PTR command_id, MV_U16 edma_error_cause, + MV_U32 time_stamp, + struct mvStorageDevRegisters *deviceRegs){ + command_completed = 1; + completion_type = type; + return MV_TRUE; +} +ulong dma_read_write (MV_SATA_ADAPTER *pSataAdapter, + unsigned int channelIndex, + MV_U8 port, + lbaint_t blknr, ulong blkcnt, ulong *buffer, int read) +{ + int res = 0; + int transfered_blks = 0; + + /* we use single PRD table entry (limited to 64KB - 128 sector) */ + while(blkcnt){ + int chunk = (blkcnt > 128) ? 128: blkcnt; + + res = dma_read_write_cmd(pSataAdapter, channelIndex, port, blknr, chunk, + buffer, read) ; + + if(res != chunk) + return transfered_blks; + + transfered_blks += res; + buffer += res << 7; //buffer is in long + blknr += res; + blkcnt -= res; + } + return transfered_blks; +} + +static +ulong dma_read_write_cmd (MV_SATA_ADAPTER *pSataAdapter, + unsigned int channelIndex, + MV_U8 port, + lbaint_t blknr, ulong blkcnt, ulong *buffer, int read) +{ + MV_QUEUE_COMMAND_INFO q_cmd_info; + MV_UDMA_COMMAND_PARAMS *udmaCommand = &q_cmd_info.commandParams.udmaCommand; + MV_SATA_DEVICE_TYPE deviceType; + MV_U32 byte_count = blkcnt << 9; + MV_U32 buffer_addr = (MV_U32) buffer; + + if ( blkcnt > 128){ + printf("error in %s: blk count %d exceeded max limit\n", + __func__, blkcnt); + } + + // mvSataDisableChannelDma(pSataAdapter, channelIndex); + /* reset the request/response pointers as we allcated one entry*/ + /* but some info need to be preserved */ + deviceType = mvStorageDevGetDeviceType(pSataAdapter, channelIndex); + mvSataConfigureChannel(pSataAdapter, channelIndex); + mvStorageDevSetDeviceType(pSataAdapter, channelIndex,deviceType); + mvSataConfigEdmaMode(pSataAdapter, channelIndex, + MV_EDMA_MODE_NOT_QUEUED, 2); + mvSataEnableChannelDma(pSataAdapter, channelIndex); + + + memset(&q_cmd_info, 0, sizeof(MV_QUEUE_COMMAND_INFO)); + memset(prd_table, 0, 2 * sizeof(MV_SATA_EDMA_PRD_ENTRY)); + + /* buffer must not cross address decode window */ + if(((buffer_addr & MRVL_SATA_BOUNDARY_MASK) + byte_count) > MRVL_SATA_BUFF_BOUNDARY) + { + MV_U32 chunk_len = MRVL_SATA_BUFF_BOUNDARY - + (buffer_addr & MRVL_SATA_BOUNDARY_MASK); + + memset(prd_table + 1, 0, sizeof(MV_SATA_EDMA_PRD_ENTRY)); + prd_table[0].lowBaseAddr = cpu_to_le32(buffer_addr); + prd_table[0].byteCount = cpu_to_le16(chunk_len & 0xFFFF); + + byte_count -= chunk_len; + buffer_addr += chunk_len; + prd_table[1].lowBaseAddr = cpu_to_le32(buffer_addr); + prd_table[1].byteCount = cpu_to_le16(byte_count & 0xFFFF); + prd_table[1].flags = cpu_to_le16(MV_EDMA_PRD_EOT_FLAG); + + } + else + { + prd_table[0].lowBaseAddr = cpu_to_le32(buffer_addr); + prd_table[0].byteCount = cpu_to_le16(byte_count & 0xFFFF); + prd_table[0].flags = cpu_to_le16(MV_EDMA_PRD_EOT_FLAG); + } + + q_cmd_info.type = MV_QUEUED_COMMAND_TYPE_UDMA; + q_cmd_info.PMPort = port; + udmaCommand->readWrite = (read)? MV_UDMA_TYPE_READ : MV_UDMA_TYPE_WRITE; + udmaCommand->isEXT = MV_FALSE; + +#ifdef CONFIG_LBA48 + /* more than 28 bits used, use 48bit mode */ + if (blknr & IDE_BLOCK_NUMBER_MASK) { + udmaCommand->isEXT = MV_TRUE; + } +#endif + + udmaCommand->FUA = MV_FALSE; + udmaCommand->lowLBAAddress = blknr & 0xFFFFFFFF; + udmaCommand->highLBAAddress = (blknr >> 32 )& 0xFFFFFFFF; + udmaCommand->numOfSectors = blkcnt; + udmaCommand->prdLowAddr = (MV_U32)prd_table; + udmaCommand->callBack = cmd_callback; +#if 0 + printf("send dma command: %s lba %x sect %x addr %x\n", read?"read":"write", + udmaCommand->lowLBAAddress, udmaCommand->numOfSectors, + prd_table[0].lowBaseAddr); +#endif + command_completed = 0; + if(mvSataQueueCommand(pSataAdapter, + channelIndex, + &q_cmd_info) != MV_QUEUE_COMMAND_RESULT_OK){ + printf("error in mv_ide: queue command failed\n"); + mvSataDisableChannelDma(pSataAdapter, channelIndex); + return 0; + } + + do{ + mvSataInterruptServiceRoutine(pSataAdapter); + udelay(1000); + + }while(!command_completed); + + mvSataDisableChannelDma(pSataAdapter, channelIndex); + if(completion_type == MV_COMPLETION_TYPE_NORMAL) + return blkcnt; + else + return 0; +} + +/* ------------------------------------------------------------------------- */ +#if (__BE) +void swapATABuffer(unsigned short *buffer, ulong count) +{ + count >>= 1; + while(count--) + { + buffer[count] = MV_CPU_TO_LE16(buffer[count]); + } +} +#endif + +ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer) +{ + return ide_read_write (device, blknr, blkcnt, buffer, MV_TRUE); +} + +ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer) +{ + return ide_read_write (device, blknr, blkcnt, buffer, MV_FALSE); +} + +/* ------------------------------------------------------------------------- */ + +/* + * copy src to dest, skipping leading and trailing blanks and null + * terminate the string + * "len" is the size of available memory including the terminating '\0' + */ +static void ident_cpy (unsigned char *dst, unsigned char *src, unsigned int len) +{ + unsigned char *end, *last; + + last = dst; + + /* Make sure lenis multiple of 2 + 1 for '\0'*/ + if( !(len % 2) || (len == 0)) + goto OUT; + + end = src + len - 1; + + while ((*src) && (src +#include +#include +#include "mvSysHwConfig.h" +#if defined(MV_INCLUDE_MONT_EXT) && defined (MV_INCLUDE_MONT_LOAD_NET) + +#if CONFIG_COMMANDS & CFG_CMD_BSP + +#include "mvTypes.h" +#include "idma/mvIdma.h" + + + +extern void d_i_cache_clean(unsigned int Address, unsigned int byteCount); +extern unsigned int VIRTUAL_TO_PHY(unsigned int address); + +/* defines relevant for the protocol between the loadnet and the fileloader.*/ +#define ENTRY_ADDR_OFFSET 0x2c - ETHER_HDR_SIZE - IP_HDR_SIZE +#define PKT_HEADER_SIZE 0x38 - ETHER_HDR_SIZE - IP_HDR_SIZE +#define LAST_PACKET_FLAG 0xffffffff + +#define NL_HASHES_PER_LINE 65 + +/* indication for loadnet reached EOF */ +static MV_BOOL loadnet_done; +/* the real load address */ +static MV_U32 loadnet_addr_gl; +/* the files Size that was receied by loadnet. */ +static MV_U32 fileSize; +/* in case we received an srec file, the srec program Entry. */ +static MV_U32 programAdressEntry; +/* for print banner */ +static MV_U32 NetloadBlock; + +/* This function will be called from the NetReceive (net.c) whenever we will receive + * a UDP packet with our IP address. + * This function know how to process the packets received from the Marvell file + * Loader utility. + * input - pointer to the packet buffer after stripping the IP header. + * (other input aren't relevant for us in this function) + * output - update the global parameters, see above. + */ +static void +mv_private_loadnet_handler(uchar * pkt, unsigned dest, unsigned src, unsigned len) +{ + + MV_U32 entryAddress,byteCount,sourceAddress,destAddress; + MV_U32 packetEnd; + + /* print progress.*/ + NetloadBlock++; + putc ('#'); + if ((NetloadBlock % (NL_HASHES_PER_LINE)) == 0) { + puts ("\n"); + } + + /* in case the file Loader transfer Srec to Bin it will send us the + entry address of each packet data. */ + /* fixed for MIPS alignment was: entryAddress = (*(MV_U32 *)(pkt + ENTRY_ADDR_OFFSET)); */ + entryAddress = 0; +#ifdef CONFIG_MV_LE + entryAddress |= *(unsigned char *)(pkt + ENTRY_ADDR_OFFSET + 0) << 24; + entryAddress |= *(unsigned char *)(pkt + ENTRY_ADDR_OFFSET + 1) << 16; + entryAddress |= *(unsigned char *)(pkt + ENTRY_ADDR_OFFSET + 2) << 8; + entryAddress |= *(unsigned char *)(pkt + ENTRY_ADDR_OFFSET + 3) << 0; +#else + { + int i; + for(i = 0; i < 2; i++ ){ + entryAddress |= (*(unsigned short *)(pkt + ENTRY_ADDR_OFFSET + i*2)) << ((1-i)*16);} + } +#endif + /* last packet of a received file is marked. */ + if(entryAddress == LAST_PACKET_FLAG){ + loadnet_done = 1; + return;} + /* the byte count of the packet data */ +#ifdef CONFIG_MV_LE + byteCount = 0; + byteCount |= *(unsigned char *)(pkt + ENTRY_ADDR_OFFSET +6) << 8; + byteCount |= *(unsigned char *)(pkt + ENTRY_ADDR_OFFSET +7); +#else + byteCount = (*(short *)(pkt + ENTRY_ADDR_OFFSET +6)) ; +#endif + packetEnd = entryAddress + byteCount; + + /* should be set only in the first time */ + if(programAdressEntry == 0x0){ + programAdressEntry = entryAddress; + debug("programAdressEntry = %x\n",programAdressEntry);} + if(loadnet_addr_gl == 0x0){ + loadnet_addr_gl = entryAddress; + debug("loadnet_addr_gl = %x\n",loadnet_addr_gl);} + + destAddress = (MV_U32)(entryAddress - programAdressEntry + + loadnet_addr_gl); + sourceAddress = (MV_U32)(pkt + PKT_HEADER_SIZE); + + debug(" Transfering from Source %x to Dest %x %x bytes\n",\ + sourceAddress,destAddress,byteCount); + + memcpy((MV_U32*)destAddress,(MV_U32*)sourceAddress,byteCount); + + fileSize = packetEnd - programAdressEntry; + + return; +} +/* load a file through the network interface, using UDP protocol only!! + * ( this function is basically the client for Marvell fileLoader utility. ) + * this function doesn't transmit any thing, only receive!! + * input - the address you want the file to be loaded to. + * if set to 0, the file will be loaded to the address given by the file + * loader according to the srec entry address. + * output - the address that the file was loaded to. + * return - the file size received from the file loader. + */ +int load_net(MV_U32 *loadnet_addr){ + + DECLARE_GLOBAL_DATA_PTR; + bd_t *bd = gd->bd; + + /* delay for MIPS LE stuck issue - probably unstable board. ??? */ + printf("\n"); + eth_halt(); + /* initilize the ethernet port */ + if(eth_init(bd) < 0) + return(-1); + /* set the Network parameters */ + memcpy (NetOurEther, bd->bi_enetaddr, 6); + NetCopyIP(&NetOurIP, &bd->bi_ip_addr); + NetOurGatewayIP = getenv_IPaddr ("gatewayip"); + NetOurSubnetMask= getenv_IPaddr ("netmask"); + NetServerIP = getenv_IPaddr ("serverip"); + /* set the Rx handler */ + NetSetHandler (mv_private_loadnet_handler); + /* initialize global parameters. */ + programAdressEntry = 0; + loadnet_done = 0; + fileSize = 0; + loadnet_addr_gl = *loadnet_addr; + NetloadBlock = 0; + + printf("Load File - Send your file when ready...\n"); + /* main loop */ + for (;;) { + /* Check the ethernet for a new packet. The ethernet + * receive routine will process it. */ + eth_rx(); + + /* Abort if ctrl-c was pressed. */ + if (ctrlc()) { + eth_halt(); + printf("\nAbort\n"); + return (-1); + } + /* if load net detected EOF*/ + if(loadnet_done == 1) break; + } + /* close the ethernet port */ + eth_halt(); + *loadnet_addr = loadnet_addr_gl; + return fileSize; +} + +int +loadnet_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int size; + MV_U32 tmp = 0; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + size = load_net(&tmp); + printf("\nFile loaded successfully...\n"); + printf("Entry Address: 0x%x\n",tmp); + printf("File size: %d bytes.\n",size); + return 1; + +} + + +U_BOOT_CMD( + ln, 1, 1, loadnet_cmd, + "ln - Load S-Record executable file through the network interface. \n", + "\t \n" + "\tLoad S-Record executable file via thr first avilable ethernet port.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +#endif + +#endif /* #if defined(MV_INCLUDE_MONT_EXT) */ diff --git a/board/mv_feroceon/USP/mv_mon_init.c b/board/mv_feroceon/USP/mv_mon_init.c new file mode 100644 index 0000000..94759e1 --- /dev/null +++ b/board/mv_feroceon/USP/mv_mon_init.c @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2001 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + /* + * Dink_command.c - driver for special Marvell coammnds taken from Dink. + */ + +#include +#include +#include + +#include "mvSysHwConfig.h" +#if defined(MV_INCLUDE_MONT_EXT) + +#include "mvTypes.h" +#include "mvCtrlEnvLib.h" +#include "mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "mv_fs.h" + +#if defined(MV_INCLUDE_MONT_MMU) +extern void pageTableInit(void); +#endif +#if defined(MV_INCLUDE_MONT_MPU) +extern void MPU_Init(void); +#endif +/* global */ + +int g_stack_cachable = 0; + + +#if defined(MV_INCLUDE_MONT_MMU) + +/***********************************************************************************/ +/* hook function that is called after CPU detection and Serial init and before */ +/* initializing of the DRAM. */ +/***********************************************************************************/ + +int PTexist(void) +{ + char *env; +#ifdef CFG_MV_PT + env = getenv("enaPT"); +#ifdef CONFIG_MV_LE + /* if LE page table disable is the default. ( MIPS - unstable, PPC need to change the page settings) */ + if( ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ){ +#else + /* if BE page table enable is the default. */ + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ){ +#endif + return 1; + } +#endif + return 0; +} +#endif +/***********************************************************************************/ +/* hook function that is called after rellocating to the DRAM, Flash Init, PCI init*/ +/* and malloc init are done, and before Gig port init. */ +/***********************************************************************************/ +void mon_extension_after_relloc(void) +{ +#if defined(MV_INCLUDE_MONT_FFS) + unsigned int status; +#endif + +#if defined(MV_INCLUDE_MONT_MMU) + if ((mvOsCpuPartGet() == CPU_PART_ARM926) || + (mvOsCpuPartGet() == CPU_PART_MRVL131)) + { + /* Page Table */ + if(PTexist() ) + { + pageTableInit(); + + /* set the stack to be cachable */ + __asm__ __volatile__ ( " orr sp, sp, #0x80000000 " : ); + g_stack_cachable = 1; + setenv("enaPT","yes"); + } + else + setenv("enaPT","no"); + } +#endif /* MV_INCLUDE_MONT_MMU */ +#ifndef MV_TINY_IMAGE + +#if defined(MV_INCLUDE_MONT_MPU) + else if (mvOsCpuPartGet() == CPU_PART_ARM946) + { + char *env; + env = getenv("enaMPU"); + + if ((!env)||( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) )) + { + setenv("enaMPU","yes"); + MPU_Init(); + } + } +#endif /* MV_INCLUDE_MONT_MPU */ + +#if CONFIG_COMMANDS & CFG_CMD_BSP +#if defined(MV_INCLUDE_MONT_FFS) + if (whoAmI() == MASTER_CPU) + { + status = mvFSInit(FS_NO_CACHE); + + + if(!(status == FS_NO_VALID_FAT_STRING || status == FS_OFFSET_OUT_OF_RANGE)) + { + printf("File system present and initialized on the main Flash Memory\n"); + } + else + { + printf("No File system on the main Flash Memory\n"); + } + } +#endif /* MV_INCLUDE_MONT_FFS */ +#endif +#endif + return; +} +#endif /* #if defined(MV_INCLUDE_MONT_EXT) */ + diff --git a/board/mv_feroceon/USP/mv_mon_init.h b/board/mv_feroceon/USP/mv_mon_init.h new file mode 100644 index 0000000..a4e0825 --- /dev/null +++ b/board/mv_feroceon/USP/mv_mon_init.h @@ -0,0 +1,36 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#ifndef __INCmvMONEXTh +#define __INCmvMONEXTh + +#ifdef __cplusplus +extern "C" { +#endif + +void mon_extension_before_relloc(void); +void mon_extension_after_relloc(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __INCmvMONEXTh */ + diff --git a/board/mv_feroceon/USP/mv_nand.c b/board/mv_feroceon/USP/mv_nand.c new file mode 100644 index 0000000..a1ab397 --- /dev/null +++ b/board/mv_feroceon/USP/mv_nand.c @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include +#include +#include "mvBoardEnvLib.h" +#ifdef MV78200 +extern MV_BOOL mvSocUnitIsMappedToThisCpu(MV_SOC_UNIT unit); +#endif + +/* + * hardware specific access to control-lines + */ +#define MASK_CLE 0x01 +#define MASK_ALE 0x02 + + +static void mv_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + /* TODO add auto detect for nand width */ + MV_U32 shift = 0; + + if (shift == MV_ERROR) + { + printf("No NAND detection\n"); + shift = 0; + } + + IO_ADDR_W &= ~((MASK_ALE|MASK_CLE) << shift); + switch (cmd) { + case NAND_CTL_SETCLE: IO_ADDR_W |= (MASK_CLE << shift); break; + case NAND_CTL_SETALE: IO_ADDR_W |= (MASK_ALE << shift); break; + } + this->IO_ADDR_W = (void *) IO_ADDR_W; +} + + +int board_nand_init(struct nand_chip *nand) +{ +#ifdef MV78200 + /* Check in dual CPU system which CPU use nand */ + /* if (mvSocUnitIsMappedToThisCpu(NAND_FLASH)) + {*/ +#endif +#if defined(MV_LARGE_PAGE) + nand->options = NAND_SAMSUNG_LP_OPTIONS; +#endif + + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = mv_nand_hwcontrol; + nand->chip_delay = 30; + return 0; +#ifdef MV78200 +/* } + else + return 1;*/ +#endif +} +#endif diff --git a/board/mv_feroceon/USP/mv_pageTable.c b/board/mv_feroceon/USP/mv_pageTable.c new file mode 100644 index 0000000..544d737 --- /dev/null +++ b/board/mv_feroceon/USP/mv_pageTable.c @@ -0,0 +1,594 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +/* Code for setting up pagetables or the protection unit, + * and enabling the cache. */ + +#include +#include +#include +#include + +#include "mvSysHwConfig.h" +#if defined(MV_INCLUDE_MONT_EXT) && defined (MV_INCLUDE_MONT_MMU) + +#include "mvCpuIf.h" +#include "cpu/mvCpu.h" + + +int mpuMap(void); + +/* This file refers to the A.R.M.--The ARM Architecture Reference Manual */ + +enum access +{ + NO_ACCESS, + NO_USR_W, + SVC_RW, + ALL_ACCESS +}; + +enum entrytype +{ + INVALID, + PAGE, + SECTION +}; + +#define U_BIT 16 +#define C_BIT 8 +#define B_BIT 4 + +#define WRITE_BACK (C_BIT|B_BIT) +#define WRITE_THROUGH (C_BIT) + +#define L1Entry(type,addr,dom,ucb,acc) \ + ( (type == SECTION) ? ( ((addr) & 0xfff00000) | \ + ((acc) << 10) | ((dom) << 5) | \ + (ucb) | (type) ) : \ + (type == PAGE) ? ( ((addr) &0xfffffc00) | \ + ((dom) << 5) | \ + ((ucb) & U_BIT) | (type) ) : \ + 0) + +#define L1EntryAddr(type, entry) \ + ( (type == SECTION) ? ((entry) & 0xfff00000): \ + (type == PAGE) ? ((entry) &0xfffffc00):0) + +#define L1EntryAcc(type, entry) \ + (((entry) & 0xc00) >> 10) + +#define L1EntryUcb(type, entry) \ + ((entry) & 0x1c) + +#define L1EntryType(type, entry) \ + ((entry) & 0x3) + +static void detectPageTable(void) +{ + int i; +#if defined(MV78XX0) + unsigned int *p = (unsigned int *)CFG_PT_BASE(whoAmI()); +#else + unsigned int *p = (unsigned int *)CFG_PT_BASE; +#endif + unsigned int entry; + unsigned int ucb; + unsigned int acc; + unsigned int nextEntry; + char* envCacheMode = getenv("cacheMode"); + unsigned int startVirAddr = 0; + unsigned int startPhyAddr = 0; + + + if(envCacheMode && (strcmp(envCacheMode,"write-through") == 0)) + { + + printf("Cache Mode - write-through\n"); + } + else /*"write-back"*/ + { + printf("Cache Mode - write-back\n"); + } + + printf("page table:\n"); + for (i = 0; i < 4096; i++) + { + entry = *p; + nextEntry = *(++p); + ucb = L1EntryUcb(SECTION, entry); + acc = L1EntryAcc(SECTION, entry); + if ( (ucb != L1EntryUcb(SECTION, nextEntry))|| + (acc != L1EntryAcc(SECTION, nextEntry))|| + (L1EntryAddr(SECTION, entry) > L1EntryAddr(SECTION, nextEntry)) || + ((L1EntryAddr(SECTION, entry) + _1M) < L1EntryAddr(SECTION, nextEntry))) + { + printf("Section (0x%08x - 0x%08x) =>",startPhyAddr, ((i << 20)| 0xfffff)); + printf(" (0x%08x - 0x%08x)",startVirAddr, (L1EntryAddr(SECTION, entry)| 0xfffff)); + if (ucb & C_BIT) + printf(" Cachable/"); + else + printf(" Non-Cachable/"); + + if (ucb & B_BIT) + printf(" Bufferable"); + else + printf(" Non-Bufferable"); + + switch(acc){ + case(NO_ACCESS): + printf("\tNO_ACCESS"); + break; + case(NO_USR_W): + printf("\tNO_USR_W"); + break; + case(SVC_RW): + printf("\tSVC_RW"); + break; + case(ALL_ACCESS): + printf("\tALL_ACCESS"); + break; + default: + printf("\tALL_ACCESS"); + break; + } + printf("\n"); + startVirAddr = L1EntryAddr(SECTION, nextEntry); + startPhyAddr = ((i+1) << 20); + } + } +} + +static unsigned int createPageTable(void) +{ + int i; + unsigned int entry; + char* envCacheMode = getenv("cacheMode"); + unsigned int cacheMode; + +#if defined(MV78XX0) + unsigned int *p = (unsigned int *)CFG_PT_BASE(whoAmI()); +#else + unsigned int *p = (unsigned int *)CFG_PT_BASE; +#endif + + if(envCacheMode && (strcmp(envCacheMode,"write-through") == 0)) + { + setenv("cacheMode","write-through"); + cacheMode = WRITE_THROUGH; + } + else /*"write-back"*/ + { + setenv("cacheMode","write-back"); + cacheMode = WRITE_BACK; + } + + /* first region 0 MB - 0x10000000(256MB) none cacheable/bufferable */ + entry = L1Entry(SECTION, 0, 0, U_BIT, ALL_ACCESS); + for (i = 0; i < 256; i++) + { + *p++ = (entry | (i << 20)); + } + + /* second region 0x10000000 (256MB) - 0x80000000 (2GB) cacheable/bufferable */ + entry = L1Entry(SECTION, 0, 0, U_BIT|cacheMode, ALL_ACCESS); + for (; i < 2048 ; i++) + { + *p++ = (entry | (i << 20)); + } + + /* 3rd region 0x80000000 (2GB) - 0x90000000 cacheable/ bufferable to 0x0*/ + entry = L1Entry(SECTION, 0, 0, U_BIT|cacheMode, ALL_ACCESS); + for (; i < 2304; i++) + { + *p++ = (entry | ((i - 2048) << 20)); + } + + /* 4rd region 0x90000000 - 0xa0000000 not cacheable/not bufferable */ + entry = L1Entry(SECTION, 0, 0, U_BIT, ALL_ACCESS); + for (; i < 2560; i++) + { + *p++ = (entry | (i << 20)); + } + + /* 5th region 0xa0000000 - 0xb0000000 cacheable/bufferable to 0x90000000 */ + entry = L1Entry(SECTION, 0, 0, U_BIT|cacheMode, ALL_ACCESS); + for (; i < 2816; i++) + { + *p++ = (entry | ((i - 256) << 20)); + } + + /* 6th region 0xb0000000 - 0xe0000000 cacheable/bufferable */ + entry = L1Entry(SECTION, 0, 0, U_BIT|cacheMode, ALL_ACCESS); + for (; i < 3584; i++) + { + *p++ = (entry | (i << 20)); + } + + /* 7th region 0xe0000000 - 0xf0000000 cacheable/bufferable to 0xf0000000 */ + entry = L1Entry(SECTION, 0, 0, U_BIT|cacheMode, ALL_ACCESS); + for (; i < 3840; i++) + { + *p++ = (entry | ((i+256) << 20)); + } + + /* 8th region 0xf0000000 - 0xffffffff none cacheable/bufferable */ + entry = L1Entry(SECTION, 0, 0, U_BIT, ALL_ACCESS); + for (; i < 4096; i++) + { + *p++ = (entry | (i << 20)); + } + +#if defined(MV78XX0) + return CFG_PT_BASE(whoAmI()); +#else + return CFG_PT_BASE; +#endif +} + +extern int PTexist(void); +int cpumap_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("CPU Memory mapping :\n"); + if ((mvOsCpuPartGet() == CPU_PART_ARM926) || + (mvOsCpuPartGet() == CPU_PART_MRVL131)) + { + if(enaMonExt()) + { + if(PTexist()) + { + detectPageTable(); + } + else + printf("No page table. \n"); + } + else + printf("No page table. \n"); + + + } +#ifndef MV_TINY_IMAGE +#if defined(MV_INCLUDE_MONT_EXT) && defined (MV_INCLUDE_MONT_MPU) + else if (mvOsCpuPartGet() == CPU_PART_ARM946) + { + mpuMap(); + } +#endif +#endif + return 1; +} + +U_BOOT_CMD( + cpumap, 1, 1, cpumap_cmd, + "cpumap - Display CPU memory mapping settings.\n", + " \n" + "\tdisplay CPU memory mapping settings.\n" +); + +/* These are all the bits currently defined for the control register */ +/* A.R.M. 7.4.2 */ +#define MMU_V 0x2000 +#define MMU_I 0x1000 +#define MMU_Z 0x0800 +#define MMU_F 0x0400 +#define MMU_R 0x0200 +#define MMU_S 0x0100 +#define MMU_B 0x0080 +#define MMU_RES 0x50078 /* reserved bits should be 1 */ +#define MMU_C 0x0004 +#define MMU_A 0x0002 +#define MMU_M 0x0001 + + + +/* + * The functions below take arguments to specify which "caches" the + * action is to be directed at. For the I-cache, pass "MMU_I". For + * the D-cache, "MMU_C". For both, pass "MMU_ID". For combined ID-Cache + * processors, use "MMU_C" + */ +#define MMU_ID (MMU_I | MMU_C) + +/* + * Inline functions for MMU functions + */ + +/* Set the page tables base register: register 2 (A.R.M. 7.4.3) */ +inline void mmuSetPageTabBase(unsigned int pagetab) +{ + __asm__ __volatile__( + "mcr p15, 0, %0, c2, c0\n" + : + : "r" (pagetab)); +} + +/* Set the domain access-control register: register 3 (A.R.M. 7.4.4) */ +inline void mmuSetDomainAccessControl(unsigned long flags) +{ + __asm__ __volatile__( + "mcr p15, 0, %0, c3, c0\n" + : + : "r" (flags)); +} + +/* Flush the cache(s). + */ +inline void mmuInvCache(unsigned caches) +{ + unsigned long dummy = 0; + + switch (caches) + { + case MMU_C: + __asm__ __volatile__( + "mcr p15, 0, %0, c7, c6, 0\n" + : + : "r" (dummy)); + break; + case MMU_I: + __asm__ __volatile__( + "mcr p15, 0, %0, c7, c5, 0\n" + : + : "r" (dummy)); + + break; + case MMU_ID: + __asm__ __volatile__( + "mcr p15, 0, %0, c7, c7, 0\n" + : + : "r" (dummy)); + break; + } +} + +/* Flush the TLB(s) + */ +inline void mmuFlushTLB( unsigned tlbs) +{ + unsigned long dummy = 0; + + /* flush TLB(s): write to register 8, with flags (A.R.M. 7.4.9) */ + switch (tlbs) + { + case MMU_C: + __asm__ __volatile__( + "mcr p15, 0, %0, c8, c6, 0\n" + : + : "r" (dummy)); + break; + case MMU_I: + __asm__ __volatile__( + "mcr p15, 0, %0, c8, c5, 0\n" + : + : "r" (dummy)); + break; + case MMU_ID: + __asm__ __volatile__( + "mcr p15, 0, %0, c8, c7, 0\n" + : + : "r" (dummy)); + break; + } +} + +/* Enable the cache/MMU/TLB etc. + */ +inline void cpuCfgEnable(unsigned long flags, MV_BOOL enable) +{ + unsigned long tmp; + + if (enable == MV_TRUE) + { + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp)); + tmp |= flags; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp)); + } + else + { + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp)); + tmp &= ~flags; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp)); + } +} + +/* Disable the I/D cache. + */ + +inline void disableIDCache(void) +{ + unsigned long tmp; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp)); + tmp &= ~MMU_ID; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp)); + + /* invalidate I/D-cache */ + tmp = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (tmp)); +} + +/* return 0 in case cache is absent */ +inline unsigned long getDCacheAssociativity(void) +{ + + unsigned long tmp, dassoc, mul; + + /* Read cache type information */ + /* Bit[11:0] - I cache size */ + /* Bit[23:12] - D cache size */ + /* Bit 24 - if '1' Seperate I-cache and D-cache */ + /* bit[28:24] - ctype */ + asm ("mrc p15, 0, %0, c0, c0, 1":"=r" (tmp)); + + /* D cache data only */ + /* Bit[1:0] - cache line length */ + /* Bit2 - M */ + /* Bit[5:3] - cache associativity */ + /* Bit[9:6] - cache size */ + tmp = (tmp >> 12) & 0xfff; + + /* Detect cache associativity - the formulae are teken from ARM DDI reference manual */ + mul = 2 + ((tmp >> 2) & 1); + dassoc = ((tmp >> 3) & 0x7); + if ((dassoc == 0) && (mul == 2)) + dassoc = 1; + else + { + if ((dassoc == 0) && (mul == 3)) + dassoc = 0; + else + dassoc = mul << (dassoc - 1); + } + + return dassoc; +} + +inline unsigned long getDCacheSize(void) +{ + + unsigned long tmp, dsize, mul; + + /* Read cache type information */ + /* Bit[11:0] - I cache size */ + /* Bit[23:12] - D cache size */ + /* Bit 24 - if '1' Seperate I-cache and D-cache */ + /* bit[28:24] - ctype */ + asm ("mrc p15, 0, %0, c0, c0, 1":"=r" (tmp)); + + /* D cache data only */ + /* Bit[1:0] - cache line length */ + /* Bit2 - M */ + /* Bit[5:3] - cache associativity */ + /* Bit[9:6] - cache size */ + tmp = (tmp >> 12) & 0xfff; + + /* Detect cache size - the formulae are teken from ARM DDI reference manual */ + mul = 2 + ((tmp >> 2) & 1); + dsize = ((tmp >> 6) & 0xf); + dsize = mul << (dsize + 8); + + return dsize; +} + +inline unsigned long getDCacheLine(void) +{ + + unsigned long tmp, dline; + + /* Read cache type information */ + /* Bit[11:0] - I cache size */ + /* Bit[23:12] - D cache size */ + /* Bit 24 - if '1' Seperate I-cache and D-cache */ + /* bit[28:24] - ctype */ + asm ("mrc p15, 0, %0, c0, c0, 1":"=r" (tmp)); + + /* D cache data only */ + /* Bit[1:0] - cache line length */ + /* Bit2 - M */ + /* Bit[5:3] - cache associativity */ + /* Bit[9:6] - cache size */ + tmp = (tmp >> 12) & 0xfff; + + /* Detect cache line - the formulae are teken from ARM DDI reference manual */ + dline = 1 << ((tmp & 0x3) + 3); + + return dline; +} + +extern ulong _dcache_index_max; +extern ulong _dcache_index_inc; +extern ulong _dcache_set_max; +extern ulong _dcache_set_index; + +void pageTableInit(void) +{ + unsigned long dsize, dassoc, dline, log2Assoc, tmp; + + printf("D-Cache type information\n"); + + /* Detect cache size */ + dsize = getDCacheSize(); + /* Detect cache number of way */ + dassoc = getDCacheAssociativity(); + /* Detect cache number of way */ + dline = getDCacheLine(); + + /* Detected cache absent */ + if (dassoc == 0) + { + printf("DCache absent!\n"); + return; + } + else + { + printf("DCache size: %dKB\n",dsize/1024); + printf("DCache associativity: %d way\n",dassoc); + printf("DCache line length: %dB\n",dline); + } + + + /* Calc num of digits for assoc representation */ + log2Assoc = 0; + tmp = dassoc - 1; + do + { + log2Assoc++; + tmp = tmp >> 1; + }while (tmp > 0); + + printf("Intializing Page Table..."); + + /* The num of assoc is set in the ip address from bit 31 backward */ + if (dassoc == 1) + { + _dcache_index_max = 0; + _dcache_index_inc = 0; + } + else + { + _dcache_index_max = ~ ((1 << (31 - log2Assoc + 1)) - 1); + _dcache_index_inc = (1 << (31 - log2Assoc + 1)); + } + + _dcache_set_max = (dsize/dassoc) - dline; + _dcache_set_index = dline; + + disableIDCache(); + /* Disable D cache and MMU. */ + cpuCfgEnable(MMU_C | MMU_M, MV_FALSE); + /* set up the page table, domain control registers */ + mmuSetPageTabBase(createPageTable()); + mmuSetDomainAccessControl(3); + /* flush caches and TLBs */ + mmuInvCache(MMU_ID); + mmuFlushTLB(MMU_ID); + /* write to control register :- + * I-cache on, 32-bit data and program space, + * write-buffer on, D-cache on, MMU on + */ + cpuCfgEnable(MMU_I | MMU_RES | MMU_C | MMU_M, MV_TRUE); + + printf("Done \n"); + return ; +} + +#endif /* defined(MV_INCLUDE_MONT_EXT) */ + + + diff --git a/board/mv_feroceon/USP/mv_pci.c b/board/mv_feroceon/USP/mv_pci.c new file mode 100644 index 0000000..eaac808 --- /dev/null +++ b/board/mv_feroceon/USP/mv_pci.c @@ -0,0 +1,877 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +/* PCI.c - PCI functions */ + +#include +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_PCI) + + +#include +#include "pci-if/mvPciIf.h" +#include "mvCpuIf.h" +#include "pci-if/pci_util/mvPciUtils.h" + + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif /* DEBUG */ + +/* global definetion */ +#define REG_NUM_MASK (0x3F << 2) +/* global indicate wether we are in the scan process */ +unsigned int bus_scan = 0; +extern unsigned int whoAmI(void); + + +#if CONFIG_COMMANDS & CFG_CMD_BSP + +/****************************************************************************** +* Category - PCI0 +* Functionality- Scans PCI0 for devices and prints relevant information +* Need modifications (Yes/No) - No +*****************************************************************************/ +MV_BOOL scanPci(MV_U32 host) +{ + MV_U32 index,numOfElements=4*8,barIndex; + MV_PCI_DEVICE pciDevices[4*8]; //3 slots and us,Max 8 functions per slot + + memset (&pciDevices,0,12*sizeof(MV_PCI_DEVICE)); + + if (mvPciScan(host, pciDevices , &numOfElements) != MV_OK ) + { + DB(printf("scanPci:mvPciScan failed for host %d \n",host)); + return MV_FALSE; + } + + + for(index = 0; index < numOfElements ; index++) + { + printf("\nBus: %x Device: %x Func: %x Vendor ID: %x Device ID: %x\n", + pciDevices[index].busNumber, + pciDevices[index].deviceNum, + pciDevices[index].function, + pciDevices[index].venID, + pciDevices[index].deviceID); + + printf("-------------------------------------------------------------------\n"); + + printf("Class: %s\n",pciDevices[index].type); + + /* check if we are bridge*/ + if ((pciDevices[index].baseClassCode == PCI_BRIDGE_CLASS)&& + (pciDevices[index].subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) + { + printf("Primary Bus:0x%x \tSecondary Bus:0x%x \tSubordinate Bus:0x%x\n", + pciDevices[index].p2pPrimBusNum, + pciDevices[index].p2pSecBusNum, + pciDevices[index].p2pSubBusNum); + + printf("IO Base:0x%x \t\tIO Limit:0x%x",pciDevices[index].p2pIObase, + pciDevices[index].p2pIOLimit); + + (pciDevices[index].bIO32)? (printf(" (32Bit IO)\n")): + (printf(" (16Bit IO)\n")); + + printf("Memory Base:0x%x \tMemory Limit:0x%x\n",pciDevices[index].p2pMemBase, + pciDevices[index].p2pMemLimit); + + printf("Pref Memory Base:0x%x \tPref Memory Limit:0x%x", + pciDevices[index].p2pPrefMemBase, + pciDevices[index].p2pPrefMemLimit); + + (pciDevices[index].bPrefMem64)? (printf(" (64Bit PrefMem)\n")): + (printf(" (32Bit PrefMem)\n")); + if (pciDevices[index].bPrefMem64) + { + printf("Pref Base Upper 32bit:0x%x \tPref Limit Base Upper32 bit:0x%x\n", + pciDevices[index].p2pPrefBaseUpper32Bits, + pciDevices[index].p2pPrefLimitUpper32Bits); + } + } + + for (barIndex = 0 ; barIndex < pciDevices[index].barsNum ; barIndex++) + { + + if (pciDevices[index].pciBar[barIndex].barType == PCI_64BIT_BAR) + { + printf("PCI_BAR%d (%s-%s) base: %x%08x%s",barIndex, + (pciDevices[index].pciBar[barIndex].barMapping == PCI_MEMORY_BAR)?"Mem":"I/O", + "64bit", + pciDevices[index].pciBar[barIndex].barBaseHigh, + pciDevices[index].pciBar[barIndex].barBaseLow, + (pciDevices[index].pciBar[barIndex].barBaseLow == 0)?"\t\t":"\t"); + } + else if (pciDevices[index].pciBar[barIndex].barType == PCI_32BIT_BAR) + { + printf("PCI_BAR%d (%s-%s) base: %x%s",barIndex, + (pciDevices[index].pciBar[barIndex].barMapping == PCI_MEMORY_BAR)?"Mem":"I/O", + "32bit", + pciDevices[index].pciBar[barIndex].barBaseLow, + (pciDevices[index].pciBar[barIndex].barBaseLow == 0)?"\t\t\t":"\t\t"); + } + + if(pciDevices[index].pciBar[barIndex].barSizeHigh != 0) + printf("size: %d%08d bytes\n",pciDevices[index].pciBar[barIndex].barSizeHigh, + pciDevices[index].pciBar[barIndex].barSizeLow); + else + printf("size: %d bytes\n", pciDevices[index].pciBar[barIndex].barSizeLow); + } + } + return MV_TRUE; +} + + +int sp_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 host = 0; + + + if (argc > 1) { + host = simple_strtoul (argv[1], NULL, 10); + } + if(host >= mvCtrlPexMaxIfGet()){ + printf("PCI %d doesn't exist\n",host); + return 1; + } + if( scanPci(host) == MV_FALSE) + printf("PCI %d Scan - FAILED!!.\n",host); + return 1; +} + +U_BOOT_CMD( + sp, 2, 1, sp_cmd, + "sp - Scan PCI bus.\n", + " [0/1] \n" + "\tScan and detecect all devices on mvPCI bus 0/1 \n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +int me_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 host = 0; + if (argc > 1) + { + host = simple_strtoul (argv[1], NULL, 10); + } + + if(host >= mvCtrlPexMaxIfGet()) + { + printf("Master %d doesn't exist\n",host); + return 1; + } + + if(mvPciIfMasterEnable(host,MV_TRUE) == MV_OK) + printf("PCI %d Master enabled.\n",host); + else + printf("PCI %d Master enabled -FAILED!!\n",host); + + return 1; +} + +U_BOOT_CMD( + me, 2, 1, me_cmd, + "me - PCI master enable\n", + " [0/1] \n" + "\tEnable the MV device as Master on PCI 0/1. \n" +); + +int se_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 host=0,dev = 0,bus=0; + + if(argc != 4) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + host = simple_strtoul (argv[1], NULL, 10); + bus = simple_strtoul (argv[2], NULL, 16); + dev = simple_strtoul (argv[3], NULL, 16); + + if(host >= mvCtrlPexMaxIfGet()) + { + printf("PCI %d doesn't exist\n",host); + return 1; + } + if(mvPciIfSlaveEnable(host,bus,dev,MV_TRUE) == MV_OK ) + printf("PCI %d Bus %d Slave 0x%x enabled.\n",host,bus,dev); + else + printf("PCI %d Bus %d Slave 0x%x enabled - FAILED!!.\n",host,bus,dev); + return 1; +} + +U_BOOT_CMD( + se, 4, 1, se_cmd, + "se - PCI Slave enable\n", + " [0/1] bus dev \n" + "\tEnable the PCI device as Slave on PCI 0/1. \n" +); + +/****************************************************************************** +* Functionality- The commands changes the pci remap register and displays the +* address to be used in order to access PCI 0. +*****************************************************************************/ +int mapPci_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + MV_ADDR_WIN pciWin; + MV_TARGET target=0; + MV_U32 host=0,effectiveBaseAddress=0; + + pciWin.baseLow=0; + pciWin.baseHigh=0; + + if (argc > 1) { + host = simple_strtoul(argv[1], NULL, 10); + } + if(argc > 2) { + pciWin.baseLow = simple_strtoul(argv[2], NULL, 16); + } + if(host >= mvCtrlPexMaxIfGet()){ + printf("PCI %d doesn't exist\n",host); + return 1; + } + + target = PCI0_MEM0 + (2 * host); + + printf("mapping pci %x to address 0x%x\n",host,pciWin.baseLow); + +#if defined(MV_INCLUDE_PEX) || defined(MV_INCLUDE_PCI) + effectiveBaseAddress = mvCpuIfPciIfRemap(target,&pciWin); +#endif + + if ( effectiveBaseAddress == 0xffffffff) + { + printf("Error remapping\n"); + return 1; + } + + printf("PCI %x Access base address : %x\n",host,effectiveBaseAddress); + return 1; +} + +U_BOOT_CMD( + mp, 3, 1, mapPci_cmd, + "mp - map PCI BAR\n", + " [0/1] address \n" + "\tChange the remap of PCI 0/1 window 0 to address 'addrress'.\n" + "\tIt also displays the new access address, since the remap is not always\n" + "\tthe same as requested. \n" +); + +#endif + +MV_U32 mv_mem_ctrl_dev(MV_U32 pciIf, MV_U32 bus,MV_U32 dev) +{ + MV_U32 ven, class; + ven = mvPciIfConfigRead(pciIf,bus,dev,0,PCI_VENDOR_ID) & 0xffff; + class = (mvPciIfConfigRead(pciIf,bus,dev,0,PCI_REVISION_ID) >> 16 ) & 0xffff; + /* if we got any other Marvell PCI cards ignore it. */ + if(((ven == 0x11ab) && (class == PCI_CLASS_MEMORY_OTHER))|| + ((ven == 0x11ab) && (class == PCI_CLASS_BRIDGE_HOST))) + { + return 1; + } + return 0; +} + +static int mv_read_config_dword(struct pci_controller *hose, + pci_dev_t dev, + int offset, u32* value) +{ + MV_U32 bus,func,regOff,dev_no; + char *env; + + bus = PCI_BUS(dev); + dev_no = PCI_DEV(dev); + + func = (MV_U32)PCI_FUNC(dev); + regOff = (MV_U32)offset & REG_NUM_MASK; + + /* We will scan only ourselves and the PCI slots that exist on the + board, because we may have a case that we have one slot that has + a Cardbus connector, and because CardBus answers all IDsels we want + to scan only this slot and ourseleves. + */ + + #if defined(MV_INCLUDE_PCI) + env = getenv("pciMode"); + if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet((MV_U32)hose->cfg_addr)) && + ((strcmp(env,"host") == 0) || (strcmp(env,"Host") == 0))) + { + if ( !mvBoardIsOurPciSlot(bus, dev_no) && + (mvBoardIdGet() != DB_88F5181_DDR1_MNG) && + (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && + (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet())) + { + *value = 0xffffffff; + return 0; + } + } + #endif /* defined(MV_INCLUDE_PCI) */ + + if( bus_scan == 1 ) + { + env = getenv("disaMvPnp"); + if(env && ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + { + if( mv_mem_ctrl_dev((MV_U32)hose->cfg_addr, bus, dev_no) ) + { + *value = 0xffffffff; + return 0; + } + } + } + DB(printf("mv_read_config_dword hose->cfg_addr %x\n",hose->cfg_addr);) + DB(printf("mv_read_config_dword bus %x\n",bus);) + DB(printf("mv_read_config_dword dev_no %x\n",dev_no);) + DB(printf("mv_read_config_dword func %x\n",func);) + DB(printf("mv_read_config_dword regOff %x\n",regOff);) + + *value = (u32) mvPciIfConfigRead((MV_U32)hose->cfg_addr,bus,dev_no,func,regOff); + + DB(printf("mv_read_config_dword value %x\n",*value);) + + return 0; +} + +static int mv_write_config_dword(struct pci_controller *hose, + pci_dev_t dev, + int offset, u32 value) +{ + MV_U32 bus,func,regOff,dev_no; + + bus = PCI_BUS(dev); + dev_no = PCI_DEV(dev); + func = (MV_U32)PCI_FUNC(dev); + regOff = offset & REG_NUM_MASK; + mvPciIfConfigWrite((MV_U32)hose->cfg_addr,bus,dev_no,func,regOff,value); + + return 0; +} + + + +static void mv_setup_ide(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ + static const int ide_bar[]={8,4,8,4,16,1024}; + u32 bar_response, bar_value; + int bar; + + for (bar=0; bar<6; bar++) + { + /*ronen different function for 3rd bank.*/ + unsigned int offset = (bar < 2)? bar*8: 0x100 + (bar-2)*8; + + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + offset, 0x0); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + offset, &bar_response); + + pciauto_region_allocate(bar_response & PCI_BASE_ADDRESS_SPACE_IO ? + hose->pci_io : hose->pci_mem, ide_bar[bar], &bar_value); + + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar*4, bar_value); + } +} + +static void mv_setup_host(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ + //skip our host + DB(printf("skipping :bus=%x dev=%x fun=%x\n", + (unsigned int)PCI_BUS(dev), + (unsigned int)PCI_DEV(dev), + (unsigned int)PCI_FUNC(dev))); + return; +} + + +static void mv_pci_bus_mode_display(MV_U32 host) +{ + + if (PCI_IF_TYPE_PEX == mvPciIfTypeGet(host)) + { + #if defined(MV_INCLUDE_PEX) + + MV_PEX_MODE pexMode; + if (mvPexModeGet(mvPciRealIfNumGet(host),&pexMode) != MV_OK) + { + printf("mv_pci_bus_mode_display: mvPexModeGet failed\n"); + } + switch (pexMode.pexType) + { + case MV_PEX_ROOT_COMPLEX: + printf("PEX %d: PCI Express Root Complex Interface\n",host); + break; + case MV_PEX_END_POINT: + printf("PEX %d: PCI Express End Point Interface\n",host); + break; + } + + if (!(pexMode.pexLinkUp)) + { + printf("PEX interface detected no Link.\n"); + } + else + { + if (MV_PEX_WITDH_X1 == pexMode.pexWidth) + { + printf("PEX interface detected Link X1\n"); + } + else + { + printf("PEX interface detected Link X4\n"); + } + } + + return ; + + #endif /* MV_INCLUDE_PEX */ + } + + + + + + if (PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(host)) + { + #if defined(MV_INCLUDE_PCI) + + MV_PCI_MODE pciMode; + + if (mvPciModeGet(mvPciRealIfNumGet(host),&pciMode) != MV_OK) + { + printf("mv_pci_bus_mode_display: mvPciIfModeGet failed\n"); + + } + + switch (pciMode.pciType) + { + case MV_PCI_CONV: + + printf("PCI %d: Conventional PCI",host); + break; + + case MV_PCIX: + + printf("PCI %d: PCI-X",host); + break; + + default: + printf("PCI %d: Unknown",host); + return; + break; + + } + + printf(", speed = %d\n",pciMode.pciSpeed); + + #endif /* #if defined(MV_INCLUDE_PCI) */ + } + + + +} + +struct pci_config_table mv_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, mv_setup_ide}, + + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, mv_setup_host}, //PCI host + + {} + +}; + + +/* Defines for more modularity of the pci_init_board function */ + +struct pci_controller pci_hose[8]; + + +#if (MV_PCI_IF_MAX_IF == 2) + +#define PCI_IF_MEM(pciIf) ((pciIf==0)?PCI_IF0_MEM0:PCI_IF1_MEM0) +#define PCI_IF_REMAPED_MEM_BASE(pciIf) ((pciIf==0)?PCI_IF0_REMAPED_MEM_BASE:PCI_IF1_REMAPED_MEM_BASE) +#define PCI_IF_MEM_BASE(pciIf) ((pciIf==0)?PCI_IF0_MEM0_BASE:PCI_IF1_MEM0_BASE) +#define PCI_IF_MEM_SIZE(pciIf) ((pciIf==0)?PCI_IF0_MEM0_SIZE:PCI_IF1_MEM0_SIZE) +#define PCI_IF_IO_BASE(pciIf) ((pciIf==0)?PCI_IF0_IO_BASE:PCI_IF1_IO_BASE) +#define PCI_IF_IO_SIZE(pciIf) ((pciIf==0)?PCI_IF0_IO_SIZE:PCI_IF1_IO_SIZE) + +#else + +#define PCI_IF_MEM(pciIf) (PCI_IF0_MEM0) +#define PCI_IF_REMAPED_MEM_BASE(pciIf) (PCI_IF0_REMAPED_MEM_BASE) +#define PCI_IF_MEM_BASE(pciIf) (PCI_IF0_MEM0_BASE) +#define PCI_IF_MEM_SIZE(pciIf) (PCI_IF0_MEM0_SIZE) +#define PCI_IF_IO_BASE(pciIf) (PCI_IF0_IO_BASE) +#define PCI_IF_IO_SIZE(pciIf) (PCI_IF0_IO_SIZE) + +#endif + +/* because of CIV tem needs we are gonna do a remap to PCI memory */ +#define PCI_IF0_REMAPED_MEM_BASE 0x90000000 +#define PCI_IF1_REMAPED_MEM_BASE 0x90000000 + +void +pci_init_board(void) +{ + MV_U32 pciIfNum = mvCtrlPexMaxIfGet(); + MV_U32 pciIf=0; + MV_ADDR_WIN rempWin; + char *env; + int first_busno=0; + int status; + MV_CPU_DEC_WIN cpuAddrDecWin; + PCI_IF_MODE pciIfMode = PCI_IF_MODE_HOST; + int pciIfStart = 0; +#ifdef MV78200 + int pciIfAccess[2] = {0,0}; + int i = 0; + char str[30]; +#endif + + if(pciIfNum == 0) + return; + env = getenv("disaMvPnp"); + + if(env && ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + printf("Warning: skip configuration of Marvell devices!!!\n"); +#if defined(MV_INCLUDE_PEX) && defined(MV78XX0) + /* Power down the none lanes 0.1, 0.2, and 0.3 if PEX0 is X4 */ + if ( !(PCI0_IS_QUAD_X1) ) + { + for (pciIf = 1; pciIf < 4; pciIf++) + mvCtrlPwrClckSet(PEX_UNIT_ID, mvPciRealIfNumGet(pciIf),MV_FALSE); + } + + /* Power down the none lanes 1.1, 1.2, and 1.3 if PEX1 is X4 */ + if ( !(PCI1_IS_QUAD_X1) ) + { + for (pciIf = 5; pciIf < 8; pciIf++) + mvCtrlPwrClckSet(PEX_UNIT_ID, mvPciRealIfNumGet(pciIf),MV_FALSE); + } +#endif + +#ifdef MV78200 +#if defined(DUAL_OS_78200) || defined(DUAL_OS_SHARED_MEM_78200) + /* Check CPU access to PEX */ + if(mvSocUnitIsMappedToThisCpu(PEX00)) + pciIfAccess[0] = 1; + + if(mvSocUnitIsMappedToThisCpu(PEX10)) + pciIfAccess[1] = 1; +#if !defined(MV632X) + /* Calc pci If start and last */ + pciIfNum = 0; + for(i=1; i >= 0 ; i--) + { + if(pciIfAccess[i] == 1) + { + pciIfStart = (i * 4); + pciIfNum += 4; + } + } + pciIfNum += pciIfStart; +#endif +#endif +#endif + + /* start pci scan */ + for (pciIf = pciIfStart; pciIf < pciIfNum; pciIf++) + { + pci_hose[pciIf].config_table = mv_config_table; + if (PCI_IF_TYPE_PEX == mvPciIfTypeGet(pciIf)) + { + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, mvPciRealIfNumGet(pciIf))) + { + continue; + } + } +#if defined(MV_INCLUDE_PCI) + else + { + if (MV_FALSE == mvCtrlPwrClckGet(PCI_UNIT_ID, mvPciRealIfNumGet(pciIf))) + { + continue; + } + } +#endif + /* device or host ? */ + if (PCI_IF_TYPE_PEX == mvPciIfTypeGet(pciIf)) + { +#if defined(MV_INCLUDE_PEX) +#if !defined(MV_88F6183) && !defined(MV_88F6183L) && !defined(MV_88F6082) && !defined(MV88F6281) && \ + !defined(MV88F6192) && !defined(MV88F6180) && !defined(MV88F6190) && !defined(MV88F6282) + MV_PEX_MODE pexMode; + if (mvPexModeGet(mvPciRealIfNumGet(pciIf),&pexMode) != MV_OK) + { + printf("pci_init_board: mvPexModeGet failed\n"); + } + + if (MV_PEX_ROOT_COMPLEX == pexMode.pexType) + pciIfMode = PCI_IF_MODE_HOST; + else + pciIfMode = PCI_IF_MODE_DEVICE; + +#else + /* Set pex mode incase S@R not exist */ + env = getenv("pexMode"); + + if( env && ( ((strcmp(env,"EP") == 0) || (strcmp(env,"ep") == 0) ))) + { + pciIfMode = PCI_IF_MODE_DEVICE; + } + else + { + pciIfMode = PCI_IF_MODE_HOST; + } + +#if defined(MV88F6282) + /* 6282 Pex 1 interface is only RC */ + if (pciIf == 1) + pciIfMode = PCI_IF_MODE_HOST; +#endif +#endif +#endif + } + else /* PCI */ + { + #if defined(MV_INCLUDE_PCI) + char *env; + env = getenv("pciMode"); + if((!env) || (strcmp(env,"host") == 0) || (strcmp(env,"Host") == 0) ) + { + pciIfMode = PCI_IF_MODE_HOST; + } + else + { + pciIfMode = PCI_IF_MODE_DEVICE; + } + #endif + } +#ifdef MV78200 + if ((pciIf == 0 && !mvSocUnitIsMappedToThisCpu(PEX00)) || + (pciIf == 4 && !mvSocUnitIsMappedToThisCpu(PEX10))) + continue; + else +#endif + { + if ((status = mvPciIfInit(pciIf, pciIfMode)) == MV_ERROR) + { + printf("pci_init_board:Error calling mvPciIfInit for pciIf %d\n",pciIf); + } + else + { + if (status == MV_OK) + mv_pci_bus_mode_display(pciIf); + else + { + /* Interface with no link */ + printf("PEX %d: interface detected no Link.\n", pciIf); + continue; + } + } + } + + if (PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) + { + #if defined(MV_INCLUDE_PCI) + if(enaMonExt()) + { + /* WA for first PCI interface */ + /* mvPciWaFix(mvPciRealIfNumGet(pciIf)); */ + } + #endif /* MV_INCLUDE_PCI */ + + if (pciIfMode == PCI_IF_MODE_DEVICE) + { + mvPciIfLocalDevNumSet(pciIf, 0x1f); + } + } + +#if defined(DB_PRPMC) + mvPciIfLocalDevNumSet(pciIf, 0x1f); +#endif + + /* start Uboot PCI scan */ + if (pciIf == 0) + pci_hose[pciIf].first_busno = 0; + else + pci_hose[pciIf].first_busno = pci_hose[pciIf-1].last_busno + 1; + + /* start Uboot PCI scan */ + pci_hose[pciIf].current_busno = pci_hose[pciIf].first_busno; + pci_hose[pciIf].last_busno = 0xff; + + if (mvPciIfLocalBusNumSet(pciIf,pci_hose[pciIf].first_busno) != MV_OK) + { + printf("pci_init_board:Error calling mvPciIfLocalBusNumSet for pciIf %d\n",pciIf); + } + + /* If no link on the interface it will not be scan */ + if (status == MV_NO_SUCH) + { + pci_hose[pciIf].last_busno =pci_hose[pciIf].first_busno; + continue; + } + +#ifdef PCI_DIS_INTERFACE + /* The disable interface will not be scan */ + if (pciIf == PCI_DIS_INTERFACE) + { + printf("***Interface is disable***\n"); + pci_hose[pciIf].last_busno =pci_hose[pciIf].first_busno; + continue; + } +#endif + if (MV_OK != mvCpuIfTargetWinGet(PCI_MEM(pciIf, 0), &cpuAddrDecWin)) + { + printf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return ; + } + + rempWin.baseLow = ((cpuAddrDecWin.addrWin.baseLow & 0x0fffffff) | PCI_IF_REMAPED_MEM_BASE(pciIf)); + rempWin.baseHigh = 0; + + /* perform a remap for the PEX0 interface*/ + if (0xffffffff == mvCpuIfPciIfRemap(PCI_MEM(pciIf, 0),&rempWin)) + { + printf("%s:mvCpuIfPciIfRemap failed\n",__FUNCTION__); + return; + } + + /* PCI memory space */ + pci_set_region(pci_hose[pciIf].regions + 0, + rempWin.baseLow, /* bus address */ + cpuAddrDecWin.addrWin.baseLow, + cpuAddrDecWin.addrWin.size, + PCI_REGION_MEM); + + if (MV_OK != mvCpuIfTargetWinGet(PCI_IO(pciIf), &cpuAddrDecWin)) + { + /* No I/O space */ + pci_hose[pciIf].region_count = 1; + } + else + { + + /* PCI I/O space */ + pci_set_region(pci_hose[pciIf].regions + 1, + cpuAddrDecWin.addrWin.baseLow, + cpuAddrDecWin.addrWin.baseLow, + cpuAddrDecWin.addrWin.size, + PCI_REGION_IO); + pci_hose[pciIf].region_count = 2; + } + + pci_set_ops(&pci_hose[pciIf], + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + mv_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + mv_write_config_dword); + + pci_hose[pciIf].cfg_addr = (unsigned int*) pciIf; + + pci_hose[pciIf].config_table[1].bus = mvPciIfLocalBusNumGet(pciIf); + pci_hose[pciIf].config_table[1].dev = mvPciIfLocalDevNumGet(pciIf); + + pci_register_hose(&pci_hose[pciIf]); + + if (pciIfMode == PCI_IF_MODE_HOST) + { + MV_U32 pciData=0,baseClassCode=0,subClassCode; + + bus_scan = 1; + + pci_hose[pciIf].last_busno = pci_hose_scan(&pci_hose[pciIf]); + bus_scan = 0; + + pciData = mvPciIfConfigRead(pciIf,pci_hose[pciIf].first_busno,1,0, PCI_CLASS_CODE_AND_REVISION_ID); + + baseClassCode = (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; + subClassCode = (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; + + if ((baseClassCode == PCI_BRIDGE_CLASS) && + (subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) + { + mvPciIfConfigWrite(pciIf,pci_hose[pciIf].first_busno,1,0,P2P_MEM_BASE_LIMIT,pciData); + /* In rthe bridge : We want to open its memory and + IO to the maximum ! after the u-boot Scan */ + /* first the IO */ + pciData = mvPciIfConfigRead(pciIf,pci_hose[pciIf].first_busno,1,0,P2P_IO_BASE_LIMIT_SEC_STATUS); + /* keep the secondary status */ + pciData &= PIBLSS_SEC_STATUS_MASK; + /* set to the maximum - 0 - 0xffff */ + pciData |= 0xff00; + mvPciIfConfigWrite(pciIf,pci_hose[pciIf].first_busno,1,0,P2P_IO_BASE_LIMIT_SEC_STATUS,pciData); + + /* the the Memory */ + pciData = mvPciIfConfigRead(pciIf,pci_hose[pciIf].first_busno,1,0,P2P_MEM_BASE_LIMIT); + /* set to the maximum - PCI_IF_REMAPED_MEM_BASE(pciIf) - 0xf000000 */ + pciData = 0xEFF00000 | (PCI_IF_REMAPED_MEM_BASE(pciIf) >> 16); + mvPciIfConfigWrite(pciIf,pci_hose[pciIf].first_busno,1,0,P2P_MEM_BASE_LIMIT,pciData); + } + } + else /* PCI_IF_MODE_HOST */ + { + pci_hose[pciIf].last_busno = pci_hose[pciIf].first_busno; + } + + first_busno = pci_hose[pciIf].last_busno + 1; + } +#ifdef DB_FPGA + MV_REG_BIT_RESET(PCI_BASE_ADDR_ENABLE_REG(0), BIT10); +#endif +} + +#endif /* CONFIG_PCI */ + diff --git a/board/mv_feroceon/USP/mv_protectionUnit.c b/board/mv_feroceon/USP/mv_protectionUnit.c new file mode 100644 index 0000000..37817c2 --- /dev/null +++ b/board/mv_feroceon/USP/mv_protectionUnit.c @@ -0,0 +1,1021 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +/* Code for setting up pagetables or the protection unit, + * and enabling the cache. */ + +#include +#include +#include +#include + +#include "mvSysHwConfig.h" +#if defined(MV_INCLUDE_MONT_EXT) && defined (MV_INCLUDE_MONT_MPU) + + +#include "mvTypes.h" +#include "mvCtrlEnvLib.h" +#include "mvCpuIf.h" +#include "cpu/mvCpu.h" + + +#ifndef MV_TINY_IMAGE + +/* This file refers to the A.R.M.--The ARM Architecture Reference Manual */ + + +typedef enum _access_type{ + + /* priveliged - user */ + NO_NO = 0 , /* No access _ No Access */ + RW_NO = 1, /* Read/Write _ No Access */ + RW_RO = 2 , /* Read/Write _ Read Only */ + RW_RW = 3, /* Read/Write _ Read/Write */ + RO_NO = 5 , /* Read Only _ No Access */ + RO_RO = 6 /* Read Only _ Read Only */ + +}ACCESS_TYPE; + + +typedef enum _region_size{ + + REG_4KB = 0xB, + REG_8KB = 0xC, + REG_16KB = 0xD, + REG_32KB = 0xE, + REG_64KB = 0xF, + REG_128KB = 0x10, + REG_256KB = 0x11, + REG_512KB = 0x12, + REG_1MB = 0x13, + REG_2MB = 0x14, + REG_4MB = 0x15, + REG_8MB = 0x16, + REG_16MB = 0x17, + REG_32MB = 0x18, + REG_64MB = 0x19, + REG_128MB = 0x1A, + REG_256MB = 0x1B, + REG_512MB = 0x1C, + REG_1GB = 0x1D, + REG_2GB = 0x1E, + REG_4GB = 0x1F + +}REGION_SIZE; + +typedef unsigned char bool; + +typedef struct _mpu_region +{ + unsigned int base; + REGION_SIZE size; + bool iCache; + bool dCache; + bool wb; + ACCESS_TYPE dAccess; + ACCESS_TYPE iAccess; + +}MPU_REGION; + + +typedef enum _cache_type{ + + D_CACHE, + I_CACHE + +}CACHE_TYPE; + + +typedef enum _mem_type{ + + D_MEM, + I_MEM + +}MEM_TYPE; + +static unsigned int sizeToBits(unsigned int size) +{ + + switch (size) + { + case 0x00001000: + return REG_4KB; + break; + case 0x00002000: + return REG_8KB; + break; + case 0x00004000: + return REG_16KB; + break; + case 0x00008000: + return REG_32KB; + break; + case 0x00010000: + return REG_64KB; + break; + case 0x00020000: + return REG_128KB; + break; + case 0x00040000: + return REG_256KB; + break; + case 0x00080000: + return REG_512KB; + break; + case 0x00100000: + return REG_1MB; + break; + case 0x00200000: + return REG_2MB; + break; + case 0x00400000: + return REG_4MB; + break; + case 0x00800000: + return REG_8MB; + break; + case 0x01000000: + return REG_16MB; + break; + case 0x02000000: + return REG_32MB; + break; + case 0x04000000: + return REG_64MB; + break; + case 0x08000000: + return REG_128MB; + break; + case 0x10000000: + return REG_256MB; + break; + case 0x20000000: + return REG_512MB; + break; + case 0x40000000: + return REG_1GB; + break; + case 0x80000000: + return REG_2GB; + break; + + } + return 0; +} + +static void printSizeOfRegion(REGION_SIZE bits) +{ + + switch (bits) + { + case REG_4KB: + printf("4KB"); + break; + case REG_8KB: + printf("8KB"); + break; + case REG_16KB: + printf("16KB"); + break; + case REG_32KB: + printf("32KB"); + break; + case REG_64KB: + printf("64KB"); + break; + case REG_128KB: + printf("128KB"); + break; + case REG_256KB: + printf("256KB"); + break; + case REG_512KB: + printf("512KB"); + break; + case REG_1MB: + printf("1MB"); + break; + case REG_2MB: + printf("2MB"); + break; + case REG_4MB: + printf("4MB"); + break; + case REG_8MB: + printf("8MB"); + break; + case REG_16MB: + printf("16MB"); + break; + case REG_32MB: + printf("32MB"); + break; + case REG_64MB: + printf("64MB"); + break; + case REG_128MB: + printf("128MB"); + break; + case REG_256MB: + printf("256MB"); + break; + case REG_512MB: + printf("512MB"); + break; + case REG_1GB: + printf("1GB"); + case REG_2GB: + printf("2GB"); + break; + case REG_4GB: + printf("4GB"); + break; + } +} + +/* + get Control register +*/ +unsigned int get_control(void) +{ + unsigned int value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0\n" + : "=r" (value) + : + : "memory"); + + return value; + + +} + +/* + set Control register +*/ +void set_control(unsigned int value) +{ + + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0\n" + : + : "r" (value)); + + +} + +/* + get Write Buffer Configuration +*/ +static unsigned int get_wb(void) +{ + unsigned int value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c3, c0, 0\n" + : "=r" (value) + : + : "memory"); + + return value; + + +} + +/* + set Write Buffer Configuration +*/ +static void set_wb(unsigned int value) +{ + + __asm__ __volatile__( + "mcr p15, 0, %0, c3, c0, 0\n" + : + : "r" (value)); + + +} + +/* + Read cache configuration +*/ + +static unsigned int get_cache_config(CACHE_TYPE type) +{ + unsigned int value = 0; + + switch (type) + { + case D_CACHE: + __asm__ __volatile__( + "mrc p15, 0, %0, c2, c0, 0\n" + : "=r" (value) + : + : "memory"); + + break; + case I_CACHE: + __asm__ __volatile__( + "mrc p15, 0, %0, c2, c0, 1\n" + : "=r" (value) + : + : "memory"); + + break; + + } + + return value; + + +} + +/* + Write cache configuration +*/ + +static void set_cache_config(CACHE_TYPE type,unsigned int value) +{ + + switch (type) + { + case D_CACHE: + __asm__ __volatile__( + "mcr p15, 0, %0, c2, c0, 0\n" + : + : "r" (value)); + + + break; + case I_CACHE: + __asm__ __volatile__( + "mcr p15, 0, %0, c2, c0, 1\n" + : + : "r" (value)); + + break; + + } + + + +} + + + + + + + +/* + Read access permision +*/ + +static unsigned int get_access(MEM_TYPE type) +{ + unsigned int value = 0; + + switch (type) + { + case D_MEM: + __asm__ __volatile__( + "mrc p15, 0, %0, c5, c0, 2\n" + : "=r" (value) + : + : "memory"); + + break; + case I_MEM: + __asm__ __volatile__( + "mrc p15, 0, %0, c5, c0, 3\n" + : "=r" (value) + : + : "memory"); + + break; + + } + + return value; + + +} + +/* + Write cache configuration +*/ + +static void set_access(MEM_TYPE type,unsigned int value) +{ + + switch (type) + { + case D_MEM: + __asm__ __volatile__( + "mcr p15, 0, %0, c5, c0, 2\n" + : + : "r" (value)); + + break; + case I_MEM: + __asm__ __volatile__( + "mcr p15, 0, %0, c5, c0, 3\n" + : + : "r" (value)); + + break; + + } + + + +} + +/* + get protection region size\base\enable +*/ + +unsigned int get_prot_attrib(int region) +{ + unsigned int value = 0; + + switch (region) + { + case 0: + + __asm__ __volatile__( + "mrc p15, 0, %0, c6, c0, 0\n" + : "=r" (value) + : + : "memory"); + + break; + case 1: + + __asm__ __volatile__( + "mrc p15, 0, %0, c6, c1, 0\n" + : "=r" (value) + : + : "memory"); + + break; + case 2: + + __asm__ __volatile__( + "mrc p15, 0, %0, c6, c2, 0\n" + : "=r" (value) + : + : "memory"); + + break; + case 3: + + __asm__ __volatile__( + "mrc p15, 0, %0, c6, c3, 0\n" + : "=r" (value) + : + : "memory"); + + break; + case 4: + + __asm__ __volatile__( + "mrc p15, 0, %0, c6, c4, 0\n" + : "=r" (value) + : + : "memory"); + + break; + case 5: + + __asm__ __volatile__( + "mrc p15, 0, %0, c6, c5, 0\n" + : "=r" (value) + : + : "memory"); + + break; + case 6: + + __asm__ __volatile__( + "mrc p15, 0, %0, c6, c6, 0\n" + : "=r" (value) + : + : "memory"); + + break; + case 7: + + __asm__ __volatile__( + "mrc p15, 0, %0, c6, c7, 0\n" + : "=r" (value) + : + : "memory"); + + break; + + + + } + + return value; +} + +/* + set protection region size\base\enable +*/ + +static void set_prot_attrib(int region,unsigned int value) +{ + switch (region) + { + case 0: + + __asm__ __volatile__( + "mcr p15, 0, %0, c6, c0, 0\n" + : + : "r" (value)); + + + break; + case 1: + + __asm__ __volatile__( + "mcr p15, 0, %0, c6, c1, 0\n" + : + : "r" (value)); + + break; + case 2: + + __asm__ __volatile__( + "mcr p15, 0, %0, c6, c2, 0\n" + : + : "r" (value)); + + break; + case 3: + + __asm__ __volatile__( + "mcr p15, 0, %0, c6, c3, 0\n" + : + : "r" (value)); + + break; + case 4: + + __asm__ __volatile__( + "mcr p15, 0, %0, c6, c4, 0\n" + : + : "r" (value)); + + break; + case 5: + + __asm__ __volatile__( + "mcr p15, 0, %0, c6, c5, 0\n" + : + : "r" (value)); + + break; + case 6: + + __asm__ __volatile__( + "mcr p15, 0, %0, c6, c6, 0\n" + : + : "r" (value)); + + break; + case 7: + + __asm__ __volatile__( + "mcr p15, 0, %0, c6, c7, 0\n" + : + : "r" (value)); + + break; + + + + } + +} + + +static void createMPUEntry(int region,MPU_REGION *mpuEntry) +{ + unsigned int value = 0; + + /* set data cache attributes */ + value = get_cache_config(D_CACHE); + + if (mpuEntry->dCache) + { + value |= (1<< region); + } + else + { + value &= ~(1<< region); + } + + set_cache_config(D_CACHE,value); + + /* set instruction cache attributes */ + value = get_cache_config(I_CACHE); + + if (mpuEntry->iCache) + { + value |= (1<< region); + } + else + { + value &= ~(1<< region); + } + + set_cache_config(I_CACHE,value); + + /* set write buffer */ + + value = get_wb(); + + if (mpuEntry->wb) + { + value |= (1<< region); + } + else + { + value &= ~(1<< region); + } + + set_wb(value); + + /* set access permision for data accesses*/ + + value = get_access(D_MEM); + value &= ~(0xf << (region*4)); + value |= (mpuEntry->dAccess << (region*4)); + set_access(D_MEM , value); + + /* set access permision for instruction accesses*/ + + value = get_access(I_MEM); + value &= ~(0xf << (region*4)); + value |= (mpuEntry->iAccess << (region*4)); + set_access(I_MEM, value); + + + + /*set base and size and enable*/ + value = 0; + value |= (mpuEntry->base) & (0xFFFFF << 12); + value |= ( mpuEntry->size << 1); + value |= 1; + + set_prot_attrib(region,value); + + + +} + + +/* These are all the bits currently defined for the control register */ +/* A.R.M. 7.4.2 */ +#define MPU_V 0x2000 /* alternae vector select */ +#define MPU_I 0x1000 /* Instruction cache */ +#define MPU_B 0x0080 /* big endian */ +#define MPU_RES 0x00F79 /* reserved bits should be 1 */ +#define MPU_C 0x0004 /* data cache */ +#define MPU_P 0x0001 /* protection unit */ + + + +/* + * The functions below take arguments to specify which "caches" the + * action is to be directed at. For the I-cache, pass "MMU_I". For + * the D-cache, "MMU_C". For both, pass "MMU_ID". For combined ID-Cache + * processors, use "MMU_C" + */ +#define MPU_ID (MPU_I + MPU_C) + + +int mpuMap(void) +{ + + unsigned int value; + int region; + + value = get_control(); + + if (value & MPU_P) + { + printf("\nProtection Unit:\n"); + + for (region = 1 ; region < 8 ; region++) + { + value = get_prot_attrib(region); + /* check if region is enabled */ + if (value & 1) + { + printf("region %d base=0x%08x size =",region,value & (0xFFFFF << 12)); + printSizeOfRegion(((value & (0x1f << 1)) >> 1)); + + value = get_cache_config(D_CACHE); + + if (value & (1 << region)) + { + printf(" :DCache enabled - "); + } + else + { + printf(" :DCache disabled - "); + } + + value = get_cache_config(I_CACHE); + + if (value & (1 << region)) + { + printf("ICache enabled - "); + } + else + { + printf("ICache disabled - "); + } + + value = get_wb(); + + if (value & (1 << region)) + { + printf("Bufferable"); + } + else + { + printf("non Bufferable"); + } + + printf("\n"); + + + + } + + } + + } + else + { + printf("MPU is disabled\n"); + } + + return 1; +} + + + +/* Flush the cache(s). + */ +inline void mpuInvCache(unsigned caches) +{ + unsigned long dummy = 0; + + switch (caches) + { + case MPU_C: + __asm__ __volatile__( + "mcr p15, 0, %0, c7, c6, 0\n" + : + : "r" (dummy)); + break; + case MPU_I: + __asm__ __volatile__( + "mcr p15, 0, %0, c7, c5, 0\n" + : + : "r" (dummy)); + break; + case MPU_ID: + __asm__ __volatile__( + "mcr p15, 0, %0, c7, c7, 0\n" + : + : "r" (dummy)); + break; + } +} + + +/* Enable the cache/MMU/TLB etc. + */ +inline void _cpuCfgEnable(unsigned long flags, MV_BOOL enable) +{ + unsigned long tmp; + + if (enable == MV_TRUE) + { + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp)); + tmp |= flags; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp)); + } + else + { + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp)); + tmp &= ~flags; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp)); + } +} + +/* Disable the I/D cache. + */ + +inline void _disableIDCache(void) +{ + unsigned long tmp; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (tmp)); + tmp &= ~MPU_ID; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (tmp)); + + /* invalidate I/D-cache */ + tmp = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (tmp)); + +} + + +void MPU_Init(void) +{ + MPU_REGION mpuEntry; +#if defined(MV_INCLUDE_SDRAM_CS1) + MV_CPU_DEC_WIN win; + MV_TARGET target; + unsigned int totalSize=0; +#endif + int region=0; + char *env; + + printf("Intializing Protection Unit\n"); + _disableIDCache(); + + /* enable I cache - doesn't need MPU enabling */ + /*_enable(MPU_RES);*/ + + /* set region 0 - include all memory and have I and D caches disabled + and write buffer disabled */ + + mpuEntry.base = 0; + mpuEntry.size = REG_4GB; + mpuEntry.dCache = 0; + mpuEntry.iCache = 0; + mpuEntry.wb = 0; + mpuEntry.iAccess = NO_NO; + mpuEntry.dAccess = NO_NO; + + createMPUEntry(region++ , &mpuEntry); + + + + /* set region 1 - CS0 DRAM region */ + + mpuEntry.base = mvCpuIfTargetWinBaseLowGet(SDRAM_CS0); + + mpuEntry.size = sizeToBits(mvCpuIfTargetWinSizeGet(SDRAM_CS0)); + + mpuEntry.dCache = 0; + mpuEntry.iCache = 1; + mpuEntry.wb = 0; + + mpuEntry.iAccess = RW_RW; + mpuEntry.dAccess = RW_RW; + + createMPUEntry(region++ , &mpuEntry); + + + /* set region 2 - CS0-CS3 DRAM region */ +#if defined(MV_INCLUDE_SDRAM_CS1) + for (target = SDRAM_CS1 ; target < MV_DRAM_MAX_CS ; target++) + { + mvCpuIfTargetWinGet(target, &win); + + if (win.enable) break; + } + + target = SDRAM_CS1; + mpuEntry.base = mvCpuIfTargetWinBaseLowGet(target); + + for (target = SDRAM_CS1; target < MV_DRAM_MAX_CS ; target++) + { + totalSize += mvCpuIfTargetWinSizeGet(target); + } + + + mpuEntry.size = sizeToBits(totalSize); + + mpuEntry.dCache = 0; + mpuEntry.iCache = 0; + mpuEntry.wb = 0; + + mpuEntry.iAccess = RW_RW; + mpuEntry.dAccess = RW_RW; +#endif + + env = getenv("dramCached"); + + if((!env)||( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) )) + { + setenv("dramCached","yes"); + + mpuEntry.dCache = 1; + mpuEntry.iCache = 1; + mpuEntry.wb = 1; + + } + + createMPUEntry(region++ , &mpuEntry); + + /* set region 3 - devices region */ + mpuEntry.base = 0xF0000000; + + mpuEntry.size = REG_256MB; + + mpuEntry.dCache = 0; + mpuEntry.iCache = 0; + mpuEntry.wb = 0; + + mpuEntry.iAccess = RW_RW; + mpuEntry.dAccess = RW_RW; + + createMPUEntry(region++ , &mpuEntry); + + /* set region 4 - pci region */ + mpuEntry.base = 0x90000000; + + mpuEntry.size = REG_256MB; + + mpuEntry.dCache = 0; + mpuEntry.iCache = 0; + mpuEntry.wb = 0; + + mpuEntry.iAccess = RW_RW; + mpuEntry.dAccess = RW_RW; + + env = getenv("pciCached"); + + if(!env) + setenv("pciCached","no"); + else + { + if( ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + { + mpuEntry.dCache = 1; + mpuEntry.iCache = 1; + mpuEntry.wb = 1; + + } + + } + + createMPUEntry(region++ , &mpuEntry); + + /* set region 5 - stack pointer */ + mpuEntry.base = 0xF00000; + + mpuEntry.size = REG_64KB; + + mpuEntry.dCache = 1; + mpuEntry.iCache = 1; + mpuEntry.wb = 1; + + mpuEntry.iAccess = RW_RW; + mpuEntry.dAccess = RW_RW; + + + createMPUEntry(region++ , &mpuEntry); + + + /*mpuInvCache(MPU_ID);*/ + /* write to control register :- + * I-cache on, 32-bit data and program space, + * write-buffer on, D-cache on, MMU on + */ + _cpuCfgEnable((MPU_I|MPU_C|MPU_P|MPU_RES), MV_TRUE); + + return ; +} +#endif + +#endif /* MV_INCLUDE_MONT_EXT */ + diff --git a/board/mv_feroceon/USP/mv_rtc.c b/board/mv_feroceon/USP/mv_rtc.c new file mode 100644 index 0000000..4feba29 --- /dev/null +++ b/board/mv_feroceon/USP/mv_rtc.c @@ -0,0 +1,94 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +/* #define RTC_DEBUG */ + +#include +#include +#include + +#ifdef MV_INCLUDE_RTC +#include "rtc/integ_rtc/mvRtc.h" +#elif defined(CONFIG_RTC_DS1338_DS1339) +#include "rtc/ext_rtc/mvDS133x.h" +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) + +/* since this rtc dosen't support century we will use 20 as default */ +#define CENTURY 20 + +void rtc_get( struct rtc_time *tmp ) +{ + MV_RTC_TIME time; +#ifdef MV_INCLUDE_RTC + mvRtcTimeGet(&time); +#elif defined(CONFIG_RTC_DS1338_DS1339) + mvRtcDS133xTimeGet(&time); +#endif + tmp->tm_year = (CENTURY * 100) + time.year; + tmp->tm_mon = time.month; + tmp->tm_mday = time.date; + tmp->tm_wday = time.day; + tmp->tm_hour = time.hours; + tmp->tm_min = time.minutes; + tmp->tm_sec = time.seconds; + tmp->tm_yday = 0; + tmp->tm_isdst= 0; +#ifdef RTC_DEBUG + printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); +#endif +} + +void rtc_set( struct rtc_time *tmp ) +{ + MV_RTC_TIME time; +#ifdef RTC_DEBUG + printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + time.month = tmp->tm_mon; + time.date = tmp->tm_mday; + time.day = tmp->tm_wday; + time.hours = tmp->tm_hour; + time.minutes = tmp->tm_min; + time.seconds = tmp->tm_sec; + if((tmp->tm_year/100) != CENTURY) + printf("Warning: century isn't supported to be set(always %d) \n",CENTURY); + time.year = tmp->tm_year%100; +#ifdef MV_INCLUDE_RTC + mvRtcTimeSet(&time); +#elif defined(CONFIG_RTC_DS1338_DS1339) + mvRtcDS133xTimeSet(&time); +#endif +} + +void rtc_reset (void) +{ + /* No need for init in any of the devices */ + /* The OSC enable bit in the DS1338 is clear at the first date set */ +} + + +#endif /* CFG_CMD_DATE */ diff --git a/board/mv_feroceon/USP/mv_serial.c b/board/mv_feroceon/USP/mv_serial.c new file mode 100644 index 0000000..fd08bf3 --- /dev/null +++ b/board/mv_feroceon/USP/mv_serial.c @@ -0,0 +1,155 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +/* + * serial.c - serial support. + */ + +#include +#include +#include "uart/mvUart.h" + +#if defined(MV78XX0) +extern unsigned int whoAmI(void); +#else + #define whoAmI() 0 +#endif + +extern void print_mvBanner(void); +extern void print_dev_id(void); + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = (CFG_TCLK / 16)/gd->baudrate; + + if (whoAmI() == MASTER_CPU) + { +#ifdef CFG_INIT_CHAN1 + mvUartInit(0, clock_divisor, mvUartBase(0)); +#endif + } + +#if defined(MV78XX0) + if ((whoAmI() == MASTER_CPU) || (whoAmI() == SLAVE_CPU)) +#endif + { +#ifdef CFG_INIT_CHAN2 + mvUartInit(1, clock_divisor, mvUartBase(1)); +#endif + } + /* print banner */ + print_mvBanner(); + print_dev_id(); + + return (0); +} + +void +serial_putc(const char c) +{ +#if defined(CONFIG_MV_SMP) || (defined(MV78XX0) && defined(MV78200)) + if (c == '\n') + mvUartPutc((whoAmI())%2, '\r'); + + mvUartPutc((whoAmI())%2, c); +#else + if (c == '\n') + mvUartPutc(CFG_DUART_CHAN, '\r'); + + mvUartPutc(CFG_DUART_CHAN, c); +#endif +} + +int +serial_getc(void) +{ +#if defined(CONFIG_MV_SMP) || (defined(MV78XX0) && defined(MV78200)) + return mvUartGetc((whoAmI())%2); +#else + return mvUartGetc(CFG_DUART_CHAN); +#endif +} + +int +serial_tstc(void) +{ +#if defined(CONFIG_MV_SMP) || (defined(MV78XX0) && defined(MV78200)) + return mvUartTstc((whoAmI())%2); +#else + return mvUartTstc(CFG_DUART_CHAN); +#endif +} + +void +serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = (CFG_TCLK / 16)/gd->baudrate; + +#ifdef CFG_INIT_CHAN1 + mvUartInit(0, clock_divisor, mvUartBase(0)); +#endif +#ifdef CFG_INIT_CHAN2 + mvUartInit(1, clock_divisor, mvUartBase(1)); +#endif +} + + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +void +kgdb_serial_init(void) +{ +} + +void +putDebugChar (int c) +{ + serial_putc (c); +} + +void +putDebugStr (const char *str) +{ + serial_puts (str); +} + +int +getDebugChar (void) +{ + return serial_getc(); +} + +void +kgdb_interruptible (int yes) +{ + return; +} +#endif /* CFG_CMD_KGDB */ diff --git a/board/mv_feroceon/USP/mv_usb_dev.c b/board/mv_feroceon/USP/mv_usb_dev.c new file mode 100644 index 0000000..88abf73 --- /dev/null +++ b/board/mv_feroceon/USP/mv_usb_dev.c @@ -0,0 +1,379 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include + +#include "mvOs.h" +#include "mvCommon.h" +#include "mvDebug.h" +#include "mvBoardEnvSpec.h" +#include "mvUsb.h" +#include "mvUsbDevApi.h" +#include "disk.h" +#include "mouse.h" + +#define USB_DISK_DEFAULT_SIZE 2048 + +extern MV_U32 mvUsbGetCapRegAddr(int devNo); + +typedef struct +{ + _usb_device_handle handle; + MV_BOOL isMouse; + int gppNo; + +} MV_USB_DEVICE; + +MV_BOOL mvUsbIsFirst = MV_TRUE; +MV_USB_DEVICE mvUsbDevice[MV_BOARD_MAX_USB_IF]; + + +USB_IMPORT_FUNCS usbImportFuncs = +{ + printf, + mvOsSPrintf, + mvOsIoUncachedMalloc, + mvOsIoUncachedFree, + mvOsMalloc, + mvOsFree, + memset, + memcpy, + mvOsCacheFlush, + mvOsCacheInvalidate, + mvOsIoVirtToPhy, + NULL, + NULL, + mvUsbGetCapRegAddr, + NULL +}; + + +static void print_args(int argc, char** argv) +{ + int i; + + for(i=0; i= 1000000) + { /* Body */ + usbMousePeriodicResume(mvUsbDevice[dev].handle); + } + } /* Endbody */ + } + if( (counter & 0xFFFFF) == 0) + mvOsPrintf("."); + + if (ctrlc()) + { + puts ("\nAbort\n"); + return; + } + } /* Endwhile */ +} + +static void mvUsbUnload(int dev) +{ + if(mvUsbDevice[dev].handle == NULL) + { + mvOsPrintf("USB-%d Device is not loaded\n", dev); + return; + } + + mvOsPrintf("Unload USB=%d Device: handle=%p\n", + dev, mvUsbDevice[dev].handle); + if(mvUsbDevice[dev].isMouse) + { + usbMouseUnload(mvUsbDevice[dev].handle); + } + else + { + usbDiskUnload(mvUsbDevice[dev].handle); + } + mvUsbDevice[dev].handle = NULL; + mvUsbDevice[dev].gppNo = -1; + mvUsbDevice[dev].isMouse = MV_FALSE; +} + + +static void mvUsbDisk(int dev, int diskSize) +{ + if(mvUsbDevice[dev].handle != NULL) + { + mvOsPrintf("USB-%d device already in use\n", dev); + return; + } + + if(diskSize == 0) + diskSize = USB_DISK_DEFAULT_SIZE; + + mvOsPrintf("Load USB-%d Disk example: disk size is %d Kbytes\n", + dev, diskSize); + + mvUsbDevice[dev].handle = usbDiskLoad(dev, diskSize); + if(mvUsbDevice[dev].handle == NULL) + { + mvOsPrintf("usbDiskLoad-%d FAILED\n", dev); + return; + } + mvUsbPolling(); +} + +static void mvUsbMouse(int dev) +{ + if(mvUsbDevice[dev].handle != NULL) + { + mvOsPrintf("USB-%d device is already in use\n", dev); + return; + } + + mvOsPrintf("Load USB-%d Mouse example\n", dev); + + mvUsbDevice[dev].handle = usbMouseLoad(dev); + if(mvUsbDevice[dev].handle == NULL) + { + mvOsPrintf("usbMouseLoad-%d FAILED\n", dev); + return; + } + mvUsbDevice[dev].isMouse = MV_TRUE; + mvUsbPolling(); +} + +int mvUsbCmdMain(int argc, char *argv[]) +{ + _usb_device_handle handle = NULL; + int i, mode, dev; + + if(mvUsbIsFirst == MV_TRUE) + { + mvUsbDevsInit(); + mvUsbIsFirst = MV_FALSE; + } + if(argc <= 1) + { + mvOsPrintf("usbTest: not enough parameters\n"); + return 2; + } + print_args(argc, argv); + + if(memcmp(argv[1], "flags", strlen(argv[1])) == 0) + { + mvOsPrintf("USB old debug flags = 0x%x\n", _usb_debug_get_flags()); + if(argc > 2) + { + mode = strtol(argv[2], NULL, 16); + _usb_debug_set_flags(mode); + mvOsPrintf("USB new debug flags = 0x%x\n", _usb_debug_get_flags()); + } + return 0; + } + if(memcmp(argv[1], "poll", strlen(argv[1])) == 0) + { + mvUsbPolling(); + return 0; + } + + dev = 0; + if(argc > 2) + dev = strtol(argv[2], NULL, 10); + + handle = mvUsbDevice[dev].handle; + if(handle == NULL) + { + mvOsPrintf("USB Device core is not initialized\n"); + return 3; + } + + if(memcmp(argv[1], "show", strlen(argv[1])) == 0) + { + mode = 0; + if(argc > 3) + mode = strtol(argv[3], NULL, 16); + + if( MV_BIT_CHECK(mode, 0) ) + _usb_regs(handle); + + if( MV_BIT_CHECK(mode, 1) ) + _usb_status(handle); + + if( MV_BIT_CHECK(mode, 2) ) + _usb_stats(handle); + + if( MV_BIT_CHECK(mode, 3) ) + _usb_debug_print_trace_log(); + + for(i=0; i<_usb_device_get_max_endpoint(handle); i++) + { + if( MV_BIT_CHECK(mode, (8+i)) ) + { + _usb_ep_status(handle, i, ARC_USB_RECV); + _usb_ep_status(handle, i, ARC_USB_SEND); + } + } + return 0; + } + + if(memcmp(argv[1], "test", strlen(argv[1])) == 0) + { + /* Set Test mode */ + mode = 0; + if(argc > 3) + mode = strtol(argv[3], NULL, 10); + + mvOsPrintf("USB test: set test mode %d\n", mode); + _usb_dci_vusb20_set_test_mode(handle, (mode & 0x7) << 8); + + return 0; + } + + mvOsPrintf("USB test: Unexpected command %s\n", argv[1]); + return 3; +} + +int mvUsbDevMain(int argc, char *argv[]) +{ + int dev, diskSize = 0; + + if(mvUsbIsFirst == MV_TRUE) + { + mvUsbDevsInit(); + mvUsbIsFirst = MV_FALSE; + } + + dev = strtol(argv[1], NULL, 10); + + if(memcmp(argv[2], "disk", strlen(argv[2])) == 0) + { + if(argc > 3) + diskSize = strtol(argv[3], NULL, 10); + + mvUsbDisk(dev, diskSize); + return 0; + } + + if(memcmp(argv[2], "mouse", strlen(argv[2])) == 0) + { + mvUsbMouse(dev); + return 0; + } + + if( memcmp(argv[2], "unload", strlen(argv[2])) == 0) + { + mvUsbUnload(dev); + return 0; + } + + mvOsPrintf("usbDev unknown command\n"); + return 1; +} + +int mvUsbCmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if( (argc == 0) || (argc == 1) ) + { + mvOsPrintf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + return mvUsbCmdMain(argc, argv); +} + +int mvUsbDev(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if(argc < 2) + { + mvOsPrintf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + return mvUsbDevMain(argc, argv); +} + + +U_BOOT_CMD( + usbCmd, 4, 1, mvUsbCmd, + "usbCmd - USB Device sub-system\n", + "\n" + "\t usbCmd flags [mask] - Get/Set debug flags\n" + "\t usbCmd poll - Polling IRQs for all USB devices for never\n" + "\t usbCmd show [mask] - Print out USB device information\n" + "\t usbCmd test [mode] - Set USB device to test mode\n" +); + +U_BOOT_CMD( + usbDev, 5, 0, mvUsbDev, + "usbDev - Load/Unload USB Devices\n", + "\t usbDev disk [kBytes] - Load USB Disk device\n" + "\t usbDev mouse - Load USB Mouse device\n" + "\t usbDev unload - Unload USB device\n" +); diff --git a/board/mv_feroceon/USP/mv_usb_host.c b/board/mv_feroceon/USP/mv_usb_host.c new file mode 100644 index 0000000..1162cba --- /dev/null +++ b/board/mv_feroceon/USP/mv_usb_host.c @@ -0,0 +1,152 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include + +#include "mvOs.h" +#include "mvDebug.h" +#include "mvBoardEnvSpec.h" +#include "mvCtrlEnvLib.h" + +#include "mvUsbHostApi.h" + +extern USB_HOST_STATE_STRUCT_PTR usb_host_state_struct_ptr; +extern void _usb_hci_vusb20_isr(void); +extern void hidMouseMain(void); + +static void print_args(int argc, char** argv) +{ + int i; + + for(i=0; i 2) + mode = strtol(argv[2], NULL, 16); + + if( MV_BIT_CHECK(mode, 3) ) + ARC_PRINT_DEBUG_TRACE(); + + return 0; + } + + if( (usb_host_state_struct_ptr != NULL) && + (memcmp(argv[1], "poll", strlen(argv[1])) == 0)) + { + i = 0; + while(TRUE) + { + if( (i & 0xFFFFF) == 0) + { + mvOsPrintf("."); + } + _usb_hci_vusb20_isr(); + i++; + + if (ctrlc()) + { + puts ("\nAbort\n"); + return 0; + } + } + mvOsPrintf("\n"); + + return 0; + } + + if( (usb_host_state_struct_ptr == NULL) && + (memcmp(argv[1], "mouse", strlen(argv[1])) == 0)) + { + mvOsPrintf("Start hidmouse driver\n"); + MV_REG_WRITE(MV_USB_CORE_MODE_REG, 0x3); + hidMouseMain(); + return 0; + } + + mvOsPrintf("USB test: Unexpected command %s\n", argv[1]); + return 3; +} + +int mvUsbHost(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if( (argc == 0) || (argc == 1) ) + { + mvOsPrintf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + mvUsbHostMain(argc, argv); + return 1; +} + +U_BOOT_CMD( + usbHost, 5, 0, mvUsbHost, + "usbHost - USB Host specific commands\n", + "\t usbHost mouse <1 | 0> - Load/Unload USB HID mouse driver\n" + "\t usbHost show [mask] - Print out all USB information\n" +); diff --git a/board/mv_feroceon/USP/nBootloader.c b/board/mv_feroceon/USP/nBootloader.c new file mode 100644 index 0000000..f6d093e --- /dev/null +++ b/board/mv_feroceon/USP/nBootloader.c @@ -0,0 +1,254 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "cntmr/mvCntmr.h" +#include "uart/mvUart.h" +#include "nBootstrap.h" +#include + +#define CFG_NAND_READ_DELAY \ + { volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; } + +typedef void (*VOIDFUNCPTR) (void); /* ptr to function returning void */ + +extern void board_nand_init(struct nand_chip *nand); +extern void mv_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd); +static void mv_nand_write_byte(struct mtd_info *mtd, u_char byte); +static u_char mv_nand_read_byte(struct mtd_info *mtd); + + +static int nand_is_bad_block(struct mtd_info *mtd, int block) +{ + struct nand_chip *this = mtd->priv; + int page_addr = block * CFG_NAND_PAGE_COUNT; + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); +#ifdef MV_LARGE_PAGE + this->write_byte(mtd, NAND_CMD_READ0); +#else + this->write_byte(mtd, NAND_CMD_READOOB); +#endif + /* Set ALE and clear CLE to start address cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + this->hwcontrol(mtd, NAND_CTL_SETALE); +#ifdef MV_LARGE_PAGE + /* Column address */ + this->write_byte(mtd, CFG_NAND_BAD_BLOCK_POS); /* A[7:0] */ + this->write_byte(mtd, 8); /* A[11:8] */ + /* Row address */ + this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[19:12] */ + this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[27:20] */ + this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x03)); /* A[29:28] */ +#else + /* Column address */ + this->write_byte(mtd, CFG_NAND_BAD_BLOCK_POS); /* A[7:0] */ + /* Row address */ + this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */ + this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */ +#endif + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); +#ifdef MV_LARGE_PAGE + /* Set command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_READSTART); + /* Clear CLE to latch command cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); +#endif + + /* + * Wait a while for the data to be ready + */ + if (this->dev_ready) + this->dev_ready(mtd); + else + CFG_NAND_READ_DELAY; + + /* + * Read on byte + */ + if (this->read_byte(mtd) != 0xff) + return 1; + + return 0; +} + +static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst) +{ + struct nand_chip *this = mtd->priv; + int page_addr = page + block * CFG_NAND_PAGE_COUNT; + int i; + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_READ0); + /* Set ALE and clear CLE to start address cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + this->hwcontrol(mtd, NAND_CTL_SETALE); +#ifdef MV_LARGE_PAGE + /* Column address */ + this->write_byte(mtd, 0); /* A[7:0] */ + this->write_byte(mtd, 0); /* A[11:8] */ + /* Row address */ + this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[19:12] */ + this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[27:20] */ + this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x03)); /* A[29:28] */ +#else + /* Column address */ + this->write_byte(mtd, 0); /* A[7:0] */ + /* Row address */ + this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */ + this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */ +#endif + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); +#ifdef MV_LARGE_PAGE + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_READSTART); + /* Set clear CLE to start address cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); +#endif + + /* + * Wait a while for the data to be ready + */ + if (this->dev_ready) + this->dev_ready(mtd); + else + CFG_NAND_READ_DELAY; + + /* + * Read page into buffer + */ + for (i=0; iread_byte(mtd); + + return 0; +} + +static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst) +{ + int block; + int blockcopy_count; + int page; + + /* + * offs has to be aligned to a block address! + */ + block = offs / CFG_NAND_BLOCK_SIZE; + blockcopy_count = 0; + + while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) { + if (!nand_is_bad_block(mtd, block)) { + /* + * Skip bad blocks + */ + for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) { + nand_read_page(mtd, block, page, dst); + dst += CFG_NAND_PAGE_SIZE; + } + + blockcopy_count++; + } + + block++; + /* End of NAND device */ + if (block >= NUM_BLOCKS) + return -1; + } + + return 0; +} + +void nand_boot(void) +{ + + ulong mem_size; + struct nand_chip nand_chip; + nand_info_t nand_info; + int ret; + + /* + * DRAM was init in nBootstrap.S so we have access to memory + */ + mem_size = 0x08000000; + + /* + * Init board specific nand support + */ + nand_info.priv = &nand_chip; + nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CFG_NAND_BASE; + nand_chip.dev_ready = NULL; /* preset to NULL */ + board_nand_init(&nand_chip); + + /* Add write and read byte functions */ + nand_chip.write_byte = mv_nand_write_byte; + nand_chip.read_byte = mv_nand_read_byte; + + /* + * Load U-Boot image from NAND into RAM + */ + ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE, + (uchar *)CFG_NAND_U_BOOT_DST); + if (ret != 0) + /* Error reading NAND */ + while(1); + + /* + * Jump to U-Boot image + */ +#if defined(MV_LARGE_PAGE) + VOIDFUNCPTR ubootStart = (VOIDFUNCPTR)(CFG_NAND_U_BOOT_START + 0x90000); +#else + VOIDFUNCPTR ubootStart = (VOIDFUNCPTR)(CFG_NAND_U_BOOT_START + 0x90000); +#endif + (*ubootStart)(); +} + + +/** + * mv_nand_read_byte - [DEFAULT] read one byte to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + * + * Default read function for 8it buswith + */ +static u_char mv_nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return readb(this->IO_ADDR_R); +} + +/** + * nand_write_byte - [DEFAULT] write one byte to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + * + * Default write function for 8it buswith + */ +static void mv_nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *this = mtd->priv; + writeb(byte, this->IO_ADDR_W); +} diff --git a/board/mv_feroceon/USP/sdio/mmc.c b/board/mv_feroceon/USP/sdio/mmc.c new file mode 100644 index 0000000..8012387 --- /dev/null +++ b/board/mv_feroceon/USP/sdio/mmc.c @@ -0,0 +1,2209 @@ +/* + + + * (C) Copyright 2003 + + + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + + + * + + + * See file CREDITS for list of people who contributed to this + + + * project. + + + * + + + * This program is free software; you can redistribute it and/or + + + * modify it under the terms of the GNU General Public License as + + + * published by the Free Software Foundation; either version 2 of + + + * the License, or (at your option) any later version. + + + * + + + * This program is distributed in the hope that it will be useful, + + + * but WITHOUT ANY WARRANTY; without even the implied warranty of + + + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + + + * GNU General Public License for more details. + + + * + + + * You should have received a copy of the GNU General Public License + + + * along with this program; if not, write to the Free Software + + + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + + + * MA 02111-1307 USA + + + */ + + +//#define DEBUG + + + + +#include + + +#include + + +#include "mvsdmmc.h" + + +#include + + +#include + + +#include + + +#include "mvOs.h" + + + + +#ifdef CONFIG_MMC + + + + +static int is_sdhc; + + + + +extern int + + +fat_register_device(block_dev_desc_t *dev_desc, int part_no); + + + + +static block_dev_desc_t mmc_dev; + + + + +block_dev_desc_t * mmc_get_dev(int dev) + + +{ + + + return ((block_dev_desc_t *)&mmc_dev); + + +} + + + + +/* + + + * FIXME needs to read cid and csd info to determine block size + + + * and other parameters + + + */ + + +static uchar mmc_buf[MMC_BLOCK_SIZE]; + + +static mmc_csd_t mmc_csd; + + +static int mmc_ready = 0; + + + + +/* MMC_DEFAULT_RCA should probably be just 1, but this may break other code + + + that expects it to be shifted. */ + + +static u_int16_t rca = 0; + + + + +static u_int32_t mmc_size(const struct mmc_csd *csd) + + +{ + + + u_int32_t block_len, mult, blocknr; + + + + + block_len = csd->read_bl_len << 12; + + + mult = csd->c_size_mult1 << 8; + + + blocknr = (csd->c_size+1) * mult; + + + + + return blocknr * block_len; + + +} + + + + +static int isprint (unsigned char ch) + + +{ + + + if (ch >= 32 && ch < 127) + + + return (1); + + + + + return (0); + + +} + + + + +static int toprint(char *dst, char c) + + +{ + + + if (isprint(c)) { + + + *dst = c; + + + return 1; + + + } + + + + + return sprintf(dst,"\\x%02x", c); + + + + +} + + + + +static void print_mmc_cid(mmc_cid_t *cid) + + +{ + + + printf("MMC found. Card desciption is:\n"); + + + printf("Manufacturer ID = %02x%02x%02x\n", + + + cid->id[0], cid->id[1], cid->id[2]); + + + printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev); + + + cid->hwrev = cid->fwrev = 0; /* null terminate string */ + + + printf("Product Name = %s\n",cid->name); + + + printf("Serial Number = %02x%02x%02x\n", + + + cid->sn[0], cid->sn[1], cid->sn[2]); + + + printf("Month = %d\n",cid->month); + + + printf("Year = %d\n",1997 + cid->year); + + +} + + + + +static void print_sd_cid(sd_cid_t *cid) + + +{ + + + int len; + + + char tbuf[64]; + + + + + printf("SD%s found. Card desciption is:\n", is_sdhc?"HC":""); + + + + + len = 0; + + + len += toprint(&tbuf[len], cid->oid_0); + + + len += toprint(&tbuf[len], cid->oid_1); + + + tbuf[len] = 0; + + + + + printf("Manufacturer: 0x%02x, OEM \"%s\"\n", + + + cid->mid, tbuf); + + + + + len = 0; + + + len += toprint(&tbuf[len], cid->pnm_0); + + + len += toprint(&tbuf[len], cid->pnm_1); + + + len += toprint(&tbuf[len], cid->pnm_2); + + + len += toprint(&tbuf[len], cid->pnm_3); + + + len += toprint(&tbuf[len], cid->pnm_4); + + + tbuf[len] = 0; + + + + + printf("Product name: \"%s\", revision %d.%d\n", + + + tbuf, + + + cid->prv >> 4, cid->prv & 15); + + + + + printf("Serial number: %u\n", + + + cid->psn_0 << 24 | cid->psn_1 << 16 | cid->psn_2 << 8 | + + + cid->psn_3); + + + printf("Manufacturing date: %d/%d\n", + + + cid->mdt_1 & 15, + + + 2000+((cid->mdt_0 & 15) << 4)+((cid->mdt_1 & 0xf0) >> 4)); + + + + + printf("CRC: 0x%02x, b0 = %d\n", + + + cid->crc >> 1, cid->crc & 1); + + +} + + + + +static void mvsdmmc_set_clock(unsigned int clock) + + +{ + + + unsigned int m; + + + + + m = MVSDMMC_BASE_FAST_CLOCK/(2*clock) - 1; + + + + + debug("mvsdmmc_set_clock: dividor = 0x%x clock=%d\n", + + + m, clock); + + + + + SDIO_REG_WRITE32(SDIO_CLK_DIV, m & 0x7ff); + + + + + if (isprint(1)) + + + udelay(10*1000); + + +} + + + + + + +static ulong * + + +/****************************************************/ + + +mmc_cmd(ulong cmd, ulong arg, ushort xfermode, ushort resptype, ushort waittype) + + +/****************************************************/ + + +{ + + + static ulong resp[4]; + + + ushort done ; + + + int err = 0 ; + + + ulong curr, start, diff, hz; + + + ushort response[8], resp_indx = 0; + + + + + debug("mmc_cmd %x, arg: %x,xfer: %x,resp: %x, wait : %x\n", cmd, arg, xfermode, resptype, waittype); + + + + + //clear status + + + SDIO_REG_WRITE16(SDIO_NOR_INTR_STATUS, 0xffff); + + + SDIO_REG_WRITE16(SDIO_ERR_INTR_STATUS, 0xffff); + + + + + start = get_ticks(); + + + hz = get_tbclk(); + + + + + while((SDIO_REG_READ16(SDIO_PRESENT_STATE0) & CARD_BUSY)) { + + + curr = get_ticks(); + + + diff = (long) curr - (long) start; + + + if (diff > (3*hz)) + + + { + + + // 3 seconds timeout, card busy, can't sent cmd + + + printf("card too busy \n"); + + + return 0; + + + } + + + } + + + + + SDIO_REG_WRITE16(SDIO_ARG_LOW, (ushort)(arg&0xffff) ); + + + SDIO_REG_WRITE16(SDIO_ARG_HI, (ushort)(arg>>16) ); + + + SDIO_REG_WRITE16(SDIO_XFER_MODE, xfermode); + + + if( (cmd == MMC_CMD_READ_BLOCK) || (cmd == 25) ) + + + { + + + SDIO_REG_WRITE16(SDIO_CMD, ((cmd << 8) | resptype | 0x3c ) ); + + + debug("cmd reg : %x\n", SDIO_REG_READ16( SDIO_CMD )) ; + + + } + + + else + + + { + + + SDIO_REG_WRITE16(SDIO_CMD, ((cmd << 8) | resptype ) ); + + + } + + + + + done = SDIO_REG_READ16(SDIO_NOR_INTR_STATUS) & waittype; + + + start = get_ticks(); + + + + + while( done!=waittype) + + + { + + + done = SDIO_REG_READ16(SDIO_NOR_INTR_STATUS) & waittype; + + + + + if( SDIO_REG_READ16(SDIO_NOR_INTR_STATUS) & 0x8000 ) + + + { + + + printf("Error! cmd : %d, err : %04x\n", cmd, SDIO_REG_READ16(SDIO_ERR_INTR_STATUS) ) ; + + + return 0 ; // error happen + + + } + + + + + curr = get_ticks(); + + + diff = (long) curr - (long) start; + + + if (diff > (3*hz)) + + + { + + + printf("cmd timeout, status : %04x\n", SDIO_REG_READ16(SDIO_NOR_INTR_STATUS)); + + + printf("xfer mode : %04x\n", SDIO_REG_READ16(SDIO_XFER_MODE)); + + + err = 1 ; + + + break; + + + } + + + } + + + + + for (resp_indx = 0 ; resp_indx < 8; resp_indx++) + + + response[resp_indx] = SDIO_REG_READ16(SDIO_RSP(resp_indx)); + + + + + memset(resp, 0, sizeof(resp)); + + + + + switch (resptype & 0x3) { + + + case SDIO_CMD_RSP_48: + + + case SDIO_CMD_RSP_48BUSY: + + + resp[0] = ((response[2] & 0x3f) << (8 - 8)) | + + + ((response[1] & 0xffff) << (14 - 8)) | + + + ((response[0] & 0x3ff) << (30 - 8)); + + + resp[1] = ((response[0] & 0xfc00) >> 10); + + + break; + + + + + case SDIO_CMD_RSP_136: + + + resp[3] = ((response[7] & 0x3fff) << 8) | + + + ((response[6] & 0x3ff) << 22); + + + resp[2] = ((response[6] & 0xfc00) >> 10) | + + + ((response[5] & 0xffff) << 6) | + + + ((response[4] & 0x3ff) << 22); + + + resp[1] = ((response[4] & 0xfc00) >> 10) | + + + ((response[3] & 0xffff) << 6) | + + + ((response[2] & 0x3ff) << 22); + + + resp[0] = ((response[2] & 0xfc00) >> 10) | + + + ((response[1] & 0xffff) << 6) | + + + ((response[0] & 0x3ff) << 22); + + + break; + + + default: + + + return 0; + + + } + + +#ifdef MMC_DEBUG + + + int i; + + + printf("MMC resp :"); + + + for (i=0; i<4; ++i ) { + + + printf(" %08x", resp[i]); + + + } + + + printf("\n"); + + +#endif + + + if( err ) + + + return NULL ; + + + else + + + return resp; + + +} + + + + +int + + +/****************************************************/ + + +mmc_block_read(uchar *dst, ulong src, ulong len) + + +/****************************************************/ + + +{ + + + ulong *resp; + + + //ushort argh, argl; + + + //ulong status; + + + + + if (len == 0) { + + + return 0; + + + } + + + + + if (is_sdhc) { + + + /* SDHC: use block address */ + + + src >>= 9; + + + } + + + + + debug("mmc_block_rd dst %lx src %lx len %d\n", (ulong)dst, src, len); + + + + +#if 0 + + + /* set block len */ + + + resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, len, 0, SDIO_CMD_RSP_48, SDIO_NOR_CMD_DONE ); + + + if (!resp) { + + + printf("mmc_block_read: set blk len fails\n"); + + + return -EIO; + + + } + + +#endif + + + + + // prepare for dma transfer + + + SDIO_REG_WRITE16(SDIO_SYS_ADDR_LOW,((ulong)(dst))&0xffff); + + + SDIO_REG_WRITE16(SDIO_SYS_ADDR_HI,(((ulong)dst)>>16)&0xffff); + + + SDIO_REG_WRITE16(SDIO_BLK_SIZE,len); + + + SDIO_REG_WRITE16(SDIO_BLK_COUNT,1); + + + + + + /* send read command */ + + + resp = mmc_cmd(MMC_CMD_READ_BLOCK, src, 0x10 , // 0x12, + + + SDIO_CMD_RSP_48, SDIO_NOR_XFER_DONE); + + + if (!resp) { + + + printf("mmc_block_read: mmc read block cmd fails\n"); + + + return -EIO; + + + } + + + + + return 0; + + +} + + + + +int + + +/****************************************************/ + + +mmc_block_write(ulong dst, uchar *src, int len) + + +/****************************************************/ + + +{ + + + //uchar *resp; + + + //ushort argh, argl; + + + //ulong status; + + + return -1 ; + + +#if 0 + + + if (len == 0) { + + + return 0; + + + } + + + + + debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong)src, len); + + + + + argh = len >> 16; + + + argl = len & 0xffff; + + + + + /* set block len */ + + + resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); + + + + + /* send write command */ + + + argh = dst >> 16; + + + argl = dst & 0xffff; + + + MMC_STRPCL = MMC_STRPCL_STOP_CLK; + + + MMC_NOB = 1; + + + MMC_BLKLEN = len; + + + resp = mmc_cmd(MMC_CMD_WRITE_BLOCK, argh, argl, + + + MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN); + + + + + MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ; + + + while (len) { + + + if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) { + + + int i, bytes = min(32,len); + + + + + for (i=0; imid, cid->oid_0, cid->oid_1, + + + cid->pnm_0, cid->pnm_1, cid->pnm_2, cid->pnm_3, cid->pnm_4); + + + + + sprintf((char *) mmc_dev.product, "%d", + + + (cid->psn_0 << 24) | (cid->psn_1 <<16) | (cid->psn_2 << 8) | (cid->psn_3 << 8)); + + + + + + sprintf((char *) mmc_dev.revision, "%d.%d", cid->prv>>4, cid->prv & 0xff); + + + + + + } else { + + + /* TODO configure mmc driver depending on card attributes */ + + + mmc_cid_t *cid = (mmc_cid_t *) resp; + + + + + memcpy(cidbuf, resp, sizeof(sd_cid_t)); + + + + + + + sprintf((char *) mmc_dev.vendor, + + + "Man %02x%02x%02x Snr %02x%02x%02x", + + + cid->id[0], cid->id[1], cid->id[2], + + + cid->sn[0], cid->sn[1], cid->sn[2]); + + + sprintf((char *) mmc_dev.product, "%s", cid->name); + + + sprintf((char *) mmc_dev.revision, "%x %x", cid->hwrev, cid->fwrev); + + + } + + + + + + /* fill in device description */ + + + mmc_dev.if_type = IF_TYPE_MMC; + + + mmc_dev.part_type = PART_TYPE_DOS; + + + mmc_dev.dev = 0; + + + mmc_dev.lun = 0; + + + mmc_dev.type = 0; + + + + + /* FIXME fill in the correct size (is set to 128MByte) */ + + + mmc_dev.blksz = 512; + + + mmc_dev.lba = 0x10000; + + + + + mmc_dev.removable = 0; + + + mmc_dev.block_read = mmc_bread; + + + + + /* MMC exists, get CSD too */ + + + resp = mmc_cmd(MMC_CMD_SET_RCA, 0, 0, SDIO_CMD_RSP_48, SDIO_NOR_CMD_DONE ); + + + if (resp == NULL) { + + + debug ("set rca fails\n"); + + + return -ENODEV; + + + } + + + debug("cmd3 resp : 0x%08x 0x%08x 0x%08x 0x%08x\n", resp[0], resp[1], resp[2], resp[3]); + + + + + if (is_sd) + + + rca = resp[0] >> 16; + + + else + + + rca = 0; + + + + + resp = mmc_cmd(MMC_CMD_SEND_CSD, rca<<16, 0, SDIO_CMD_RSP_136,SDIO_NOR_CMD_DONE ); + + + debug("cmd 9 resp : %08x %08x %08x %08x\n", resp[0], resp[1], resp[2], resp[3] ); + + + if (resp == NULL) { + + + debug ("read csd fails\n"); + + + return -ENODEV; + + + } + + + + + memcpy(&mmc_csd, (mmc_csd_t *) resp, sizeof(mmc_csd_t)); + + + rc = 0; + + + mmc_ready = 1; + + + + + /* FIXME add verbose printout for csd */ + + + debug ("size = %u\n", mmc_size(&mmc_csd)); + + + + + resp = mmc_cmd(7, rca<<16, 0, SDIO_CMD_RSP_48BUSY, SDIO_NOR_CMD_DONE); + + + if (resp == NULL) { + + + debug ("select card fails\n"); + + + return -ENODEV; + + + } + + + debug("cmd 7 resp : %08x %08x %08x %08x\n", resp[0], resp[1], resp[2], resp[3] ); + + + + + if (is_sd) { + + + resp = mmc_cmd(55, rca<<16, 0, SDIO_CMD_RSP_48, SDIO_NOR_CMD_DONE ); + + + if (resp == NULL) { + + + debug ("cmd55 fails\n"); + + + return -ENODEV; + + + } + + + debug("cmd55 resp : 0x%08x 0x%08x 0x%08x 0x%08x\n", resp[0], resp[1], resp[2], resp[3]); + + + + + resp = mmc_cmd(6, (rca<<16) | 0x2 , 0, SDIO_CMD_RSP_48, SDIO_NOR_CMD_DONE ); + + + if (resp == NULL) { + + + debug ("cmd55 fails\n"); + + + return -ENODEV; + + + } + + + debug("cmd6 resp : 0x%08x 0x%08x 0x%08x 0x%08x\n", resp[0], resp[1], resp[2], resp[3]); + + + } + + + + + resp = (ulong *) &mmc_csd; + + + debug("csd: 0x%08x 0x%08x 0x%08x 0x%08x\n", resp[0], resp[1], resp[2], resp[3]); + + + + + /* check SDHC */ + + + if ((resp[0]&0xf0000000)==0x40000000) + + + is_sdhc = 1; + + + + + /* set block len */ + + + resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, 512, 0, SDIO_CMD_RSP_48, SDIO_NOR_CMD_DONE ); + + + if (!resp) { + + + printf("mmc_block_read: set blk len fails\n"); + + + return -EIO; + + + } + + + + + if (verbose) { + + + if (is_sd) + + + print_sd_cid((sd_cid_t *) cidbuf); + + + else + + + print_mmc_cid((mmc_cid_t *) cidbuf); + + + } + + + + + mvsdmmc_set_clock(25000000); + + + + + fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ + + + + + return rc; + + +} + + + + +int + + +mmc_ident(block_dev_desc_t *dev) + + +{ + + + return 0; + + +} + + + + +int + + +mmc2info(ulong addr) + + +{ + + + /* FIXME hard codes to 256 MB device */ + + + if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0xffffffff) { + + + return 1; + + + } + + + return 0; + + +} + + + + +#endif /* CONFIG_MMC */ + + diff --git a/board/mv_feroceon/USP/sdio/mustang_sdiodef.h b/board/mv_feroceon/USP/sdio/mustang_sdiodef.h new file mode 100644 index 0000000..ab92d5a --- /dev/null +++ b/board/mv_feroceon/USP/sdio/mustang_sdiodef.h @@ -0,0 +1,211 @@ + + +#define MUSTANG_SDHC_BASE 0xf1080000 // from 00-4c +#define INTEGRATOR_GPIO_BASE 0x1b000000 +//#define SC_BASE + +#define P(x) (MUSTANG_SDHC_BASE + (2 * x)) + +#define GPIO_REG_READ32(addr) (*(volatile unsigned int*)(INTEGRATOR_GPIO_BASE+addr)) +#define GPIO_REG_WRITE32(addr, val) (*(volatile unsigned int*)(INTEGRATOR_GPIO_BASE+addr)=val) + +#define SDIO_REG_WRITE16(addr,val) (*(volatile unsigned short*)(P(addr)) = val) +#define SDIO_REG_READ16(addr) (*(volatile unsigned short*)(P(addr))) + +/* SDIO register offset */ +#define SDIO_SYS_ADDR_LOW 0x000 +#define SDIO_SYS_ADDR_HI 0x002 +#define SDIO_BLK_SIZE 0x004 +#define SDIO_BLK_COUNT 0x006 +#define SDIO_ARG_LOW 0x008 +#define SDIO_ARG_HI 0x00A +#define SDIO_XFER_MODE 0x00C +#define SDIO_CMD 0x00E +#define SDIO_RSP0 0x010 +#define SDIO_RSP1 0x012 +#define SDIO_RSP2 0x014 +#define SDIO_RSP3 0x016 +#define SDIO_RSP4 0x018 +#define SDIO_RSP5 0x01A +#define SDIO_RSP6 0x01C +#define SDIO_RSP7 0x01E +#define SDIO_BUF_DATA_PORT 0x020 +#define SDIO_RSVED 0x022 +#define SDIO_PRESENT_STATE0 0x024 +#define CARD_BUSY ((unsigned short)(0x1 << 1)) +#define SDIO_PRESENT_STATE1 0x026 +#define SDIO_HOST_CTRL 0x028 +#define SDIO_BLK_GAP_CTRL 0x02A +#define SDIO_CLK_CTRL 0x02C +#define SDIO_SW_RESET 0x02E +#define SDIO_NOR_INTR_STATUS 0x030 +#define SDIO_ERR_INTR_STATUS 0x032 +#define SDIO_NOR_STATUS_EN 0x034 +#define SDIO_ERR_STATUS_EN 0x036 +#define SDIO_NOR_INTR_EN 0x038 +#define SDIO_ERR_INTR_EN 0x03A +#define SDIO_AUTOCMD12_ERR_STATUS 0x03C +#define SDIO_CURR_BLK_SIZE 0x03E +#define SDIO_CURR_BLK_COUNT 0x040 +#define SDIO_AUTOCMD12_ARG_LOW 0x042 +#define SDIO_AUTOCMD12_ARG_HI 0x044 +#define SDIO_AUTOCMD12_INDEX 0x046 +#define SDIO_AUTO_RSP0 0x048 +#define SDIO_AUTO_RSP1 0x04A +#define SDIO_AUTO_RSP2 0x04C + +/************** SDIO_HOST_CTRL ****/ +#define SDIO_HOST_CTRL_PUSH_PULL_EN 1 +#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY 0 +#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1<<1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2<<1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3<<1) +#define SDIO_HOST_CTRL_BIG_ENDAN (1<<3) +#define SDIO_HOST_CTRL_LSB_FIRST (1<<4) +#define SDIO_HOST_CTRL_ID_MODE_LOW_FREQ (1<<5) +#define SDIO_HOST_CTRL_HALF_SPEED (1<<6) +#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1<<9) +#define SDIO_HOST_CTRL_HI_SPEED_EN (1<<10) +#define SDIO_HOST_CTRL_TMOUT_SHIFT 11 +#define SDIO_HOST_CTRL_TMOUT_EN (1<<15) + +#define SDIO_HOST_CTRL_DFAULT_OPEN_DRAIN (0xF< EXTINT1 (IRQ24) a can be used as SD_CARD_IN +// GPIO6 => can be used as SD_WP +// GPIO7 => can be used as SD_ON + +#define SDHC_GPIO_CARD_IN 0x00000002 +#define SDHC_GPIO_WP 0x00000040 +#define SDHC_GPIO_POWER 0x00000080 + +#define MUSTANG_GPIO_DIRECTION_OFFSET 8 +#define MUSTANG_GPIO_CLEAR_OFFSET 4 +#define MUSTANG_GPIO_SET_OFFSET 0 +#define MUSTANG_GPIO_DATAIN 0 + +//SC Flag bit 0 for Card Detection +// if bit 0 of 0x11000030 is zero, +// Card Insertion interrupt will be detected +// if bit 0 of 0x11000030 is 1 +// card Removal interrupt will be detected +#define MUSTANG_SCFLAG_STATUS_OFFSET 0x0 +#define MUSTANG_SCFLAG_SET_OFFSET 0x0 +#define MUSTANG_SCFLAG_CLEAR_OFFSET 0x4 + +#define MUSTANG_SD_CARDDET_TOGGLE_BIT 0x1 + +typedef struct mmc_cid +{ + /* FIXME: BYTE_ORDER */ + uchar year:4, + month:4; + uchar sn[3]; + uchar fwrev:4, + hwrev:4; + uchar name[6]; + uchar id[3]; +} mmc_cid_t; + +typedef struct mmc_csd +{ + uchar ecc:2, + file_format:2, + tmp_write_protect:1, + perm_write_protect:1, + copy:1, + file_format_grp:1; + uint64_t content_prot_app:1, + rsvd3:4, + write_bl_partial:1, + write_bl_len:4, + r2w_factor:3, + default_ecc:2, + wp_grp_enable:1, + wp_grp_size:5, + erase_grp_mult:5, + erase_grp_size:5, + c_size_mult1:3, + vdd_w_curr_max:3, + vdd_w_curr_min:3, + vdd_r_curr_max:3, + vdd_r_curr_min:3, + c_size:12, + rsvd2:2, + dsr_imp:1, + read_blk_misalign:1, + write_blk_misalign:1, + read_bl_partial:1; + ushort read_bl_len:4, + ccc:12; + uchar tran_speed; + uchar nsac; + uchar taac; + uchar rsvd1:2, + spec_vers:4, + csd_structure:2; +} mmc_csd_t; + diff --git a/board/mv_feroceon/USP/sdio/mvsdmmc.h b/board/mv_feroceon/USP/sdio/mvsdmmc.h new file mode 100644 index 0000000..85514d2 --- /dev/null +++ b/board/mv_feroceon/USP/sdio/mvsdmmc.h @@ -0,0 +1,294 @@ +/* + * Copyright (C) 2008 Marvell Semiconductors, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _MVSDMMC_INCLUDE +#define _MVSDMMC_INCLUDE + + +#define MV88F6281_SDHC_BASE 0xf1090000 // from 00-4c + +#define P(x) (MV88F6281_SDHC_BASE + (x)) + +// #define GPIO_REG_READ32(addr) (*(volatile unsigned int*)(INTEGRATOR_GPIO_BASE+addr)) +// #define GPIO_REG_WRITE32(addr, val) (*(volatile unsigned int*)(INTEGRATOR_GPIO_BASE+addr)=val) + +#define SDIO_REG_WRITE32(addr,val) (*(volatile unsigned long*)(P(addr)) = val) +#define SDIO_REG_WRITE16(addr,val) (*(volatile unsigned short*)(P(addr)) = val) +#define SDIO_REG_READ16(addr) (*(volatile unsigned short*)(P(addr))) +#define SDIO_REG_READ32(addr) (*(volatile unsigned long*)(P(addr))) + +#define MVSDMMC_DMA_SIZE 65536 + +#define MVSDMMC_CMD_TIMEOUT 2 /* 100 usec*/ + + +/* + * The base MMC clock rate + */ + +#define MVSDMMC_CLOCKRATE_MIN 100000 +#define MVSDMMC_CLOCKRATE_MAX 50000000 + +#define MVSDMMC_BASE_FAST_CLOCK 200000000//100000000 + + +/* + * SDIO register + */ + +#define SDIO_SYS_ADDR_LOW 0x000 +#define SDIO_SYS_ADDR_HI 0x004 +#define SDIO_BLK_SIZE 0x008 +#define SDIO_BLK_COUNT 0x00c +#define SDIO_ARG_LOW 0x010 +#define SDIO_ARG_HI 0x014 +#define SDIO_XFER_MODE 0x018 +#define SDIO_CMD 0x01c +#define SDIO_RSP(i) (0x020 + ((i)<<2)) +#define SDIO_RSP0 0x020 +#define SDIO_RSP1 0x024 +#define SDIO_RSP2 0x028 +#define SDIO_RSP3 0x02c +#define SDIO_RSP4 0x030 +#define SDIO_RSP5 0x034 +#define SDIO_RSP6 0x038 +#define SDIO_RSP7 0x03c +#define SDIO_BUF_DATA_PORT 0x040 +#define SDIO_RSVED 0x044 + +#define SDIO_PRESENT_STATE0 0x048 +#define SDIO_PRESENT_STATE1 0x04c +#define SDIO_HOST_CTRL 0x050 +#define SDIO_BLK_GAP_CTRL 0x054 +#define SDIO_CLK_CTRL 0x058 +#define SDIO_SW_RESET 0x05c +#define SDIO_NOR_INTR_STATUS 0x060 +#define SDIO_ERR_INTR_STATUS 0x064 +#define SDIO_NOR_STATUS_EN 0x068 +#define SDIO_ERR_STATUS_EN 0x06c +#define SDIO_NOR_INTR_EN 0x070 +#define SDIO_ERR_INTR_EN 0x074 +#define SDIO_AUTOCMD12_ERR_STATUS 0x078 +#define SDIO_CURR_BYTE_LEFT 0x07c +#define SDIO_CURR_BLK_LEFT 0x080 +#define SDIO_AUTOCMD12_ARG_LOW 0x084 +#define SDIO_AUTOCMD12_ARG_HI 0x088 +#define SDIO_AUTOCMD12_INDEX 0x08c +#define SDIO_AUTO_RSP(i) (0x090 + ((i)<<2)) +#define SDIO_AUTO_RSP0 0x090 +#define SDIO_AUTO_RSP1 0x094 +#define SDIO_AUTO_RSP2 0x098 +#define SDIO_CLK_DIV 0x128 + +#define WINDOW_CTRL(i) (0x108 + ((i) << 3)) +#define WINDOW_BASE(i) (0x10c + ((i) << 3)) + + +/* + * SDIO_PRESENT_STATE + */ + +#define CARD_BUSY (1 << 1) +#define CMD_INHIBIT (1 << 0) +#define CMD_TXACTIVE (1 << 8) +#define CMD_RXACTIVE (1 << 9) +#define CMD_AUTOCMD12ACTIVE (1 << 14) + +#define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE| \ + CMD_RXACTIVE| \ + CMD_TXACTIVE| \ + CMD_INHIBIT| \ + CARD_BUSY) + +/* + * SDIO_CMD + */ + +#define SDIO_CMD_RSP_NONE (0 << 0) +#define SDIO_CMD_RSP_136 (1 << 0) +#define SDIO_CMD_RSP_48 (2 << 0) +#define SDIO_CMD_RSP_48BUSY (3 << 0) + +#define SDIO_CMD_CHECK_DATACRC16 (1 << 2) +#define SDIO_CMD_CHECK_CMDCRC (1 << 3) +#define SDIO_CMD_INDX_CHECK (1 << 4) +#define SDIO_CMD_DATA_PRESENT (1 << 5) +#define SDIO_UNEXPECTED_RESP (1 << 7) + + +/* + * SDIO_XFER_MODE + */ + +#define SDIO_XFER_MODE_STOP_CLK (1 << 5) +#define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1) +#define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2) +#define SDIO_XFER_MODE_INT_CHK_EN (1 << 3) +#define SDIO_XFER_MODE_TO_HOST (1 << 4) + + +/* + * SDIO_HOST_CTRL + */ + +#define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0) + +#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1) +#define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1) + +#define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3) +#define SDIO_HOST_CTRL_LSB_FIRST (1 << 4) +#define SDIO_HOST_CTRL_ID_MODE_LOW_FREQ (1 << 5) +#define SDIO_HOST_CTRL_HALF_SPEED (1 << 6) +#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9) +#define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10) + + +#define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11) +#define SDIO_HOST_CTRL_TMOUT_MAX (0xf << 11) +#define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11) +#define SDIO_HOST_CTRL_TMOUT_EN (1 << 15) + +#define SDIO_HOST_CTRL_DFAULT_OPEN_DRAIN \ + (SDIO_HOST_CTRL_TMOUT(x)(0xf)) +#define SDIO_HOST_CTRL_DFAULT_PUSH_PULL \ + (SDIO_HOST_CTRL_TMOUT(x)(0xf) | SDIO_HOST_CTRL_PUSH_PULL_EN) + + +/* + * NOR status bits + */ + +#define SDIO_NOR_ERROR (1 << 15) +#define SDIO_NOR_UNEXP_RSP (1 << 14) +#define SDIO_NOR_AUTOCMD12_DONE (1 << 13) +#define SDIO_NOR_SUSPEND_ON (1 << 12) +#define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11) +#define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10) +#define SDIO_NOR_READ_WAIT_ON (1 << 9) +#define SDIO_NOR_CARD_INT (1 << 8) +#define SDIO_NOR_READ_READY (1 << 5) +#define SDIO_NOR_WRITE_READY (1 << 4) +#define SDIO_NOR_DMA_INI (1 << 3) +#define SDIO_NOR_BLK_GAP_EVT (1 << 2) +#define SDIO_NOR_XFER_DONE (1 << 1) +#define SDIO_NOR_CMD_DONE (1 << 0) + + +/* + * ERR status bits + */ + +#define SDIO_ERR_CRC_STATUS (1 << 14) +#define SDIO_ERR_CRC_STARTBIT (1 << 13) +#define SDIO_ERR_CRC_ENDBIT (1 << 12) +#define SDIO_ERR_RESP_TBIT (1 << 11) +#define SDIO_ERR_SIZE (1 << 10) +#define SDIO_ERR_CMD_STARTBIT (1 << 9) +#define SDIO_ERR_AUTOCMD12 (1 << 8) +#define SDIO_ERR_DATA_ENDBIT (1 << 6) +#define SDIO_ERR_DATA_CRC (1 << 5) +#define SDIO_ERR_DATA_TIMEOUT (1 << 4) +#define SDIO_ERR_CMD_INDEX (1 << 3) +#define SDIO_ERR_CMD_ENDBIT (1 << 2) +#define SDIO_ERR_CMD_CRC (1 << 1) +#define SDIO_ERR_CMD_TIMEOUT (1 << 0) + +#define SDIO_POLL_MASK 0xffff /* enable all for polling */ + + +#define MMC_BLOCK_SIZE 512 +#define MMC_CMD_RESET 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RCA 3 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_BLOCK 17 +#define MMC_CMD_RD_BLK_MULTI 18 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_MAX_BLOCK_SIZE 512 + +typedef struct mmc_cid +{ + /* FIXME: BYTE_ORDER */ + uchar year:4, + month:4; + uchar sn[3]; + uchar fwrev:4, + hwrev:4; + uchar name[6]; + uchar id[3]; +} mmc_cid_t; + +typedef struct mmc_csd +{ + uchar ecc:2, + file_format:2, + tmp_write_protect:1, + perm_write_protect:1, + copy:1, + file_format_grp:1; + uint64_t content_prot_app:1, + rsvd3:4, + write_bl_partial:1, + write_bl_len:4, + r2w_factor:3, + default_ecc:2, + wp_grp_enable:1, + wp_grp_size:5, + erase_grp_mult:5, + erase_grp_size:5, + c_size_mult1:3, + vdd_w_curr_max:3, + vdd_w_curr_min:3, + vdd_r_curr_max:3, + vdd_r_curr_min:3, + c_size:12, + rsvd2:2, + dsr_imp:1, + read_blk_misalign:1, + write_blk_misalign:1, + read_bl_partial:1; + ushort read_bl_len:4, + ccc:12; + uchar tran_speed; + uchar nsac; + uchar taac; + uchar rsvd1:2, + spec_vers:4, + csd_structure:2; +} mmc_csd_t; + +typedef struct { + char pnm_0; /* product name */ + char oid_1; /* OEM/application ID */ + char oid_0; + uint8_t mid; /* manufacturer ID */ + char pnm_4; + char pnm_3; + char pnm_2; + char pnm_1; + uint8_t psn_2; /* product serial number */ + uint8_t psn_1; + uint8_t psn_0; /* MSB */ + uint8_t prv; /* product revision */ + uint8_t crc; /* CRC7 checksum, b0 is unused and set to 1 */ + uint8_t mdt_1; /* manufacturing date, LSB, RRRRyyyy yyyymmmm */ + uint8_t mdt_0; /* MSB */ + uint8_t psn_3; /* LSB */ +} sd_cid_t; + +#endif /* _MVSDMMC_INCLUDE */ diff --git a/board/mv_feroceon/common/mv802_3.h b/board/mv_feroceon/common/mv802_3.h new file mode 100644 index 0000000..3769dde --- /dev/null +++ b/board/mv_feroceon/common/mv802_3.h @@ -0,0 +1,213 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmv802_3h +#define __INCmv802_3h + + +/* includes */ +#include "mvTypes.h" + +/* Defines */ +#define MV_MAX_ETH_DATA 1500 + +/* 802.3 types */ +#define MV_IP_TYPE 0x0800 +#define MV_IP_ARP_TYPE 0x0806 +#define MV_APPLE_TALK_ARP_TYPE 0x80F3 +#define MV_NOVELL_IPX_TYPE 0x8137 +#define MV_EAPOL_TYPE 0x888e + + + +/* Encapsulation header for RFC1042 and Ethernet_tunnel */ + +#define MV_RFC1042_SNAP_HEADER {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00} + +#define MV_ETH_SNAP_LSB 0xF8 + + +#define MV_MAC_ADDR_SIZE (6) +#define MV_MAC_STR_SIZE (20) +#define MV_VLAN_HLEN (4) + +/* This macro checks for a multicast mac address */ +#define MV_IS_MULTICAST_MAC(mac) (((mac)[0] & 0x1) == 1) + + +/* This macro checks for an broadcast mac address */ +#define MV_IS_BROADCAST_MAC(mac) \ + (((mac)[0] == 0xFF) && \ + ((mac)[1] == 0xFF) && \ + ((mac)[2] == 0xFF) && \ + ((mac)[3] == 0xFF) && \ + ((mac)[4] == 0xFF) && \ + ((mac)[5] == 0xFF)) + + +/* Typedefs */ +typedef struct +{ + MV_U8 pDA[MV_MAC_ADDR_SIZE]; + MV_U8 pSA[MV_MAC_ADDR_SIZE]; + MV_U16 typeOrLen; + +} MV_802_3_HEADER; + +enum { + MV_IP_PROTO_NULL = 0, /* Dummy protocol for TCP */ + MV_IP_PROTO_ICMP = 1, /* Internet Control Message Protocol */ + MV_IP_PROTO_IGMP = 2, /* Internet Group Management Protocol */ + MV_IP_PROTO_IPIP = 4, /* IPIP tunnels (older KA9Q tunnels use 94) */ + MV_IP_PROTO_TCP = 6, /* Transmission Control Protocol */ + MV_IP_PROTO_EGP = 8, /* Exterior Gateway Protocol */ + MV_IP_PROTO_PUP = 12, /* PUP protocol */ + MV_IP_PROTO_UDP = 17, /* User Datagram Protocol */ + MV_IP_PROTO_IDP = 22, /* XNS IDP protocol */ + MV_IP_PROTO_DCCP = 33, /* Datagram Congestion Control Protocol */ + MV_IP_PROTO_IPV6 = 41, /* IPv6-in-IPv4 tunnelling */ + MV_IP_PROTO_RSVP = 46, /* RSVP protocol */ + MV_IP_PROTO_GRE = 47, /* Cisco GRE tunnels (rfc 1701,1702) */ + MV_IP_PROTO_ESP = 50, /* Encapsulation Security Payload protocol */ + MV_IP_PROTO_AH = 51, /* Authentication Header protocol */ + MV_IP_PROTO_BEETPH = 94, /* IP option pseudo header for BEET */ + MV_IP_PROTO_PIM = 103, + MV_IP_PROTO_COMP = 108, /* Compression Header protocol */ + MV_IP_PROTO_ZERO_HOP = 114, /* Any 0 hop protocol (IANA) */ + MV_IP_PROTO_SCTP = 132, /* Stream Control Transport Protocol */ + MV_IP_PROTO_UDPLITE = 136, /* UDP-Lite (RFC 3828) */ + + MV_IP_PROTO_RAW = 255, /* Raw IP packets */ + MV_IP_PROTO_MAX +}; + +typedef struct +{ + MV_U8 version; + MV_U8 tos; + MV_U16 totalLength; + MV_U16 identifier; + MV_U16 fragmentCtrl; + MV_U8 ttl; + MV_U8 protocol; + MV_U16 checksum; + MV_U32 srcIP; + MV_U32 dstIP; + +} MV_IP_HEADER; + +typedef struct +{ + MV_U32 spi; + MV_U32 seqNum; +} MV_ESP_HEADER; + +#define MV_ICMP_ECHOREPLY 0 /* Echo Reply */ +#define MV_ICMP_DEST_UNREACH 3 /* Destination Unreachable */ +#define MV_ICMP_SOURCE_QUENCH 4 /* Source Quench */ +#define MV_ICMP_REDIRECT 5 /* Redirect (change route) */ +#define MV_ICMP_ECHO 8 /* Echo Request */ +#define MV_ICMP_TIME_EXCEEDED 11 /* Time Exceeded */ +#define MV_ICMP_PARAMETERPROB 12 /* Parameter Problem */ +#define MV_ICMP_TIMESTAMP 13 /* Timestamp Request */ +#define MV_ICMP_TIMESTAMPREPLY 14 /* Timestamp Reply */ +#define MV_ICMP_INFO_REQUEST 15 /* Information Request */ +#define MV_ICMP_INFO_REPLY 16 /* Information Reply */ +#define MV_ICMP_ADDRESS 17 /* Address Mask Request */ +#define MV_ICMP_ADDRESSREPLY 18 /* Address Mask Reply */ + +typedef struct +{ + MV_U8 type; + MV_U8 code; + MV_U16 checksum; + MV_U16 id; + MV_U16 sequence; + +} MV_ICMP_ECHO_HEADER; + +typedef struct +{ + MV_U16 source; + MV_U16 dest; + MV_U32 seq; + MV_U32 ack_seq; + MV_U16 flags; + MV_U16 window; + MV_U16 chksum; + MV_U16 urg_offset; + +} MV_TCP_HEADER; + +typedef struct +{ + MV_U16 source; + MV_U16 dest; + MV_U16 len; + MV_U16 check; + +} MV_UDP_HEADER; + +#endif /* __INCmv802_3h */ diff --git a/board/mv_feroceon/common/mvCommon.c b/board/mv_feroceon/common/mvCommon.c new file mode 100644 index 0000000..dc0e0cf --- /dev/null +++ b/board/mv_feroceon/common/mvCommon.c @@ -0,0 +1,277 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "mv802_3.h" +#include "mvCommon.h" + + +/******************************************************************************* +* mvMacStrToHex - Convert MAC format string to hex. +* +* DESCRIPTION: +* This function convert MAC format string to hex. +* +* INPUT: +* macStr - MAC address string. Fornat of address string is +* uu:vv:ww:xx:yy:zz, where ":" can be any delimiter. +* +* OUTPUT: +* macHex - MAC in hex format. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex) +{ + int i; + char tmp[3]; + + for(i = 0; i < MV_MAC_ADDR_SIZE; i++) + { + tmp[0] = macStr[(i * 3) + 0]; + tmp[1] = macStr[(i * 3) + 1]; + tmp[2] = '\0'; + macHex[i] = (MV_U8) (strtol(tmp, NULL, 16)); + } + return MV_OK; +} + +/******************************************************************************* +* mvMacHexToStr - Convert MAC in hex format to string format. +* +* DESCRIPTION: +* This function convert MAC in hex format to string format. +* +* INPUT: +* macHex - MAC in hex format. +* +* OUTPUT: +* macStr - MAC address string. String format is uu:vv:ww:xx:yy:zz. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr) +{ + int i; + + for(i = 0; i < MV_MAC_ADDR_SIZE; i++) + { + mvOsSPrintf(&macStr[i * 3], "%02x:", macHex[i]); + } + macStr[(i * 3) - 1] = '\0'; + + return MV_OK; +} + +/******************************************************************************* +* mvSizePrint - Print the given size with size unit description. +* +* DESCRIPTION: +* This function print the given size with size unit description. +* FOr example when size paramter is 0x180000, the function prints: +* "size 1MB+500KB" +* +* INPUT: +* size - Size in bytes. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvSizePrint(MV_U32 size) +{ + mvOsOutput("size "); + + if(size >= _1G) + { + mvOsOutput("%3dGB ", size / _1G); + size %= _1G; + if(size) + mvOsOutput("+"); + } + if(size >= _1M ) + { + mvOsOutput("%3dMB ", size / _1M); + size %= _1M; + if(size) + mvOsOutput("+"); + } + if(size >= _1K) + { + mvOsOutput("%3dKB ", size / _1K); + size %= _1K; + if(size) + mvOsOutput("+"); + } + if(size > 0) + { + mvOsOutput("%3dB ", size); + } +} + +/******************************************************************************* +* mvHexToBin - Convert hex to binary +* +* DESCRIPTION: +* This function Convert hex to binary. +* +* INPUT: +* pHexStr - hex buffer pointer. +* size - Size to convert. +* +* OUTPUT: +* pBin - Binary buffer pointer. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) +{ + int j, i; + char tmp[3]; + MV_U8 byte; + + for(j=0, i=0; j> 1; + result++; + } + return result; +} + + diff --git a/board/mv_feroceon/common/mvCommon.h b/board/mv_feroceon/common/mvCommon.h new file mode 100644 index 0000000..c8e9ce1 --- /dev/null +++ b/board/mv_feroceon/common/mvCommon.h @@ -0,0 +1,308 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + + +#ifndef __INCmvCommonh +#define __INCmvCommonh + +#include "mvTypes.h" + +/* Swap tool */ + +/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ +#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ + ((X&0xf0) >> 4) | \ + ((X&0xf00) << 4) | \ + ((X&0xf000) >> 4)) + +/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ +#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ + ((X&0xf0) >> 4) | \ + ((X&0xf00) << 4) | \ + ((X&0xf000) >> 4) | \ + ((X&0xf0000) << 4) | \ + ((X&0xf00000) >> 4) | \ + ((X&0xf000000) << 4) | \ + ((X&0xf0000000) >> 4)) + +/* 16bit byte swap. For example 0x1122 -> 0x2211 */ +#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) + +/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ +#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ + (((X)&0xff00)<<8) | \ + (((X)&0xff0000)>>8) | \ + (((X)&0xff000000)>>24)) + +/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ +#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ + (((X)&0xff00ULL)<<40) | \ + (((X)&0xff0000ULL)<<24) | \ + (((X)&0xff000000ULL)<<8) | \ + (((X)&0xff00000000ULL)>>8) | \ + (((X)&0xff0000000000ULL)>>24) | \ + (((X)&0xff000000000000ULL)>>40) | \ + (((X)&0xff00000000000000ULL)>>56))) + +/* Endianess macros. */ +#if defined(MV_CPU_LE) + #define MV_16BIT_LE(X) (X) + #define MV_32BIT_LE(X) (X) + #define MV_64BIT_LE(X) (X) + #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) + #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) + #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) +#elif defined(MV_CPU_BE) + #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) + #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) + #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) + #define MV_16BIT_BE(X) (X) + #define MV_32BIT_BE(X) (X) + #define MV_64BIT_BE(X) (X) +#else + #error "CPU endianess isn't defined!\n" +#endif + + +/* Bit field definitions */ +#define NO_BIT 0x00000000 +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +/* Handy sizes */ +#define _1K 0x00000400 +#define _2K 0x00000800 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + +/* Tclock and Sys clock define */ +#define _100MHz 100000000 +#define _125MHz 125000000 +#define _133MHz 133333334 +#define _150MHz 150000000 +#define _160MHz 160000000 +#define _166MHz 166666667 +#define _175MHz 175000000 +#define _178MHz 178000000 +#define _183MHz 183333334 +#define _187MHz 187000000 +#define _192MHz 192000000 +#define _194MHz 194000000 +#define _200MHz 200000000 +#define _233MHz 233333334 +#define _250MHz 250000000 +#define _266MHz 266666667 +#define _300MHz 300000000 + +/* For better address window table readability */ +#define EN MV_TRUE +#define DIS MV_FALSE +#define N_A -1 /* Not applicable */ + +/* Cache configuration options for memory (DRAM, SRAM, ... ) */ + +/* Memory uncached, HW or SW cache coherency is not needed */ +#define MV_UNCACHED 0 +/* Memory cached, HW cache coherency supported in WriteThrough mode */ +#define MV_CACHE_COHER_HW_WT 1 +/* Memory cached, HW cache coherency supported in WriteBack mode */ +#define MV_CACHE_COHER_HW_WB 2 +/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ +#define MV_CACHE_COHER_SW 3 + + +/* Macro for testing aligment. Positive if number is NOT aligned */ +#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) + +/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ +#define MV_ALIGN_UP(number, align) \ +(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) + +/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ +#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) + +/* This macro returns absolute value */ +#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) + + +/* Bit fields manipulation macros */ + +/* An integer word which its 'x' bit is set */ +#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) + +/* Checks wheter bit 'x' in integer word is set */ +#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) + +/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ +#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) + +/* Set bit 'x' in integer word (RMW) */ +#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) + +/* Invert bit 'x' in integer word (RMW) */ +#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) + +/* Get the min between 'a' or 'b' */ +#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) + +/* Get the max between 'a' or 'b' */ +#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) + +/* Temporary */ +#define mvOsDivide(num, div) \ +({ \ + int i=0, rem=(num); \ + \ + while(rem >= (div)) \ + { \ + rem -= (div); \ + i++; \ + } \ + (i); \ +}) + +/* Temporary */ +#define mvOsReminder(num, div) \ +({ \ + int rem = (num); \ + \ + while(rem >= (div)) \ + rem -= (div); \ + (rem); \ +}) + +#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ + ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) + +#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) + +#ifndef MV_ASMLANGUAGE +/* mvCommon API list */ + +MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); +void mvAsciiToHex(const char* asciiStr, char* hexStr); +void mvBinToHex(const MV_U8* bin, char* hexStr, int size); +void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); + +MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); +MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); +void mvSizePrint(MV_U32); + +MV_U32 mvLog2(MV_U32 num); + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __INCmvCommonh */ diff --git a/board/mv_feroceon/common/mvCompVer.txt b/board/mv_feroceon/common/mvCompVer.txt new file mode 100644 index 0000000..c6e1229 --- /dev/null +++ b/board/mv_feroceon/common/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_2 +Unit HAL Version: 3.1.0 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/common/mvDebug.c b/board/mv_feroceon/common/mvDebug.c new file mode 100644 index 0000000..087f36d --- /dev/null +++ b/board/mv_feroceon/common/mvDebug.c @@ -0,0 +1,326 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + + +/* includes */ +#include "mvOs.h" +#include "mv802_3.h" +#include "mvCommon.h" +#include "mvDebug.h" + +/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros + * mvDebug - map of bits (one for each module) bit=1 means enable + * debug code and messages for this module + * mvModuleDebug - array of 32 bits varables one for each module + */ +MV_U32 mvDebug = 0; +MV_U32 mvDebugModules[MV_MODULE_MAX]; + +/* Init mvModuleDebug array to default values */ +void mvDebugInit(void) +{ + int bit; + + mvDebug = 0; + for(bit=0; bit 0) + { + mvOsPrintf("%08x: ", memAddr); + i = 0; + /* 32 bytes in the line */ + while(i < 32) + { + if(memAddr >= (MV_U32)addr) + { + switch(access) + { + case 1: + if( memAddr == CPU_PHY_MEM(memAddr) ) + { + mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); + } + else + { + mvOsPrintf("%02x ", *((MV_U8*)memAddr)); + } + break; + + case 2: + if( memAddr == CPU_PHY_MEM(memAddr) ) + { + mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); + } + else + { + mvOsPrintf("%04x ", *((MV_U16*)memAddr)); + } + break; + + case 4: + if( memAddr == CPU_PHY_MEM(memAddr) ) + { + mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); + } + else + { + mvOsPrintf("%08x ", *((MV_U32*)memAddr)); + } + break; + } + } + else + { + for(j=0; j<(access*2+1); j++) + mvOsPrintf(" "); + } + i += access; + memAddr += access; + size -= access; + if(size <= 0) + break; + } + mvOsPrintf("\n"); + } +} + +void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) +{ + if(pBufInfo == NULL) + { + mvOsPrintf("\n!!! pBufInfo = NULL\n"); + return; + } + mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", + (unsigned int)pBufInfo, + (unsigned int)pBufInfo->cmdSts, + (unsigned int)pBufInfo->pBuff, + (unsigned int)pBufInfo->bufSize); + mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", + (unsigned int)pBufInfo->pData, + (unsigned int)pBufInfo->byteCnt, + (unsigned int)pBufInfo->pNextBufInfo, + (unsigned int)pBufInfo->userInfo1, + (unsigned int)pBufInfo->userInfo2); + if(pBufInfo->pData != NULL) + { + if(size > pBufInfo->byteCnt) + size = pBufInfo->byteCnt; + mvDebugMemDump(pBufInfo->pData, size, access); + } +} + +void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) +{ + int frag, len; + + if(pPktInfo == NULL) + { + mvOsPrintf("\n!!! pPktInfo = NULL\n"); + return; + } + mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", + pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, + pPktInfo->pFrags, pPktInfo->osInfo); + + for(frag=0; fragnumFrags; frag++) + { + mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", + frag, pPktInfo->pFrags[frag].bufVirtPtr, + pPktInfo->pFrags[frag].bufSize); + if(size > 0) + { + len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); + mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); + size -= len; + } + } + +} + +void mvDebugPrintIpAddr(MV_U32 ipAddr) +{ + mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), + ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); +} + +void mvDebugPrintMacAddr(const MV_U8* pMacAddr) +{ + int i; + + mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); + for(i=1; ibegin = 0; + pTimeEntry->count = count; + pTimeEntry->end = 0; + pTimeEntry->left = pTimeEntry->count; + pTimeEntry->total = 0; + pTimeEntry->min = 0xFFFFFFFF; + pTimeEntry->max = 0x0; + strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); + pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; +} + +/* Print out MV_DEBUG_TIMES entry */ +void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) +{ + int num; + + if(isTitle == MV_TRUE) + mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); + + num = pTimeEntry->count-pTimeEntry->left; + if(num > 0) + { + mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", + pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, + pTimeEntry->min, pTimeEntry->max); + } +} + +/* Update MV_DEBUG_TIMES entry */ +void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) +{ + MV_U32 delta; + + if(pTimeEntry->left > 0) + { + if(pTimeEntry->end <= pTimeEntry->begin) + { + delta = pTimeEntry->begin - pTimeEntry->end; + } + else + { + delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; + } + pTimeEntry->total += delta; + + if(delta < pTimeEntry->min) + pTimeEntry->min = delta; + + if(delta > pTimeEntry->max) + pTimeEntry->max = delta; + + pTimeEntry->left--; + } +} + diff --git a/board/mv_feroceon/common/mvDebug.h b/board/mv_feroceon/common/mvDebug.h new file mode 100644 index 0000000..e4975be --- /dev/null +++ b/board/mv_feroceon/common/mvDebug.h @@ -0,0 +1,178 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + + +#ifndef __INCmvDebugh +#define __INCmvDebugh + +/* includes */ +#include "mvTypes.h" + +typedef enum +{ + MV_MODULE_INVALID = -1, + MV_MODULE_ETH = 0, + MV_MODULE_IDMA, + MV_MODULE_XOR, + MV_MODULE_TWASI, + MV_MODULE_MGI, + MV_MODULE_USB, + MV_MODULE_CESA, + + MV_MODULE_MAX +}MV_MODULE_ID; + +/* Define generic flags useful for most of modules */ +#define MV_DEBUG_FLAG_ALL (0) +#define MV_DEBUG_FLAG_INIT (1 << 0) +#define MV_DEBUG_FLAG_RX (1 << 1) +#define MV_DEBUG_FLAG_TX (1 << 2) +#define MV_DEBUG_FLAG_ERR (1 << 3) +#define MV_DEBUG_FLAG_TRACE (1 << 4) +#define MV_DEBUG_FLAG_DUMP (1 << 5) +#define MV_DEBUG_FLAG_CACHE (1 << 6) +#define MV_DEBUG_FLAG_IOCTL (1 << 7) +#define MV_DEBUG_FLAG_STATS (1 << 8) + +extern MV_U32 mvDebug; +extern MV_U32 mvDebugModules[MV_MODULE_MAX]; + +#ifdef MV_DEBUG +# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg +# define MV_DEBUG_CODE(module, flags, code) code +#elif defined(MV_RT_DEBUG) +# define MV_DEBUG_PRINT(module, flags, msg) \ + if( (mvDebug & (1<<(module))) && \ + ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ + mvOsPrintf msg +# define MV_DEBUG_CODE(module, flags, code) \ + if( (mvDebug & (1<<(module))) && \ + ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ + code +#else +# define MV_DEBUG_PRINT(module, flags, msg) +# define MV_DEBUG_CODE(module, flags, code) +#endif + + + +/* typedefs */ + +/* time measurement structure used to check how much time pass between + * two points + */ +typedef struct { + char name[20]; /* name of the entry */ + unsigned long begin; /* time measured on begin point */ + unsigned long end; /* time measured on end point */ + unsigned long total; /* Accumulated time */ + unsigned long left; /* The rest measurement actions */ + unsigned long count; /* Maximum measurement actions */ + unsigned long min; /* Minimum time from begin to end */ + unsigned long max; /* Maximum time from begin to end */ +} MV_DEBUG_TIMES; + + +/* mvDebug.h API list */ + +/****** Error Recording ******/ + +/* Dump memory in specific format: + * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 + */ +void mvDebugMemDump(void* addr, int size, int access); + +void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); + +void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); + +void mvDebugPrintIpAddr(MV_U32 ipAddr); + +void mvDebugPrintMacAddr(const MV_U8* pMacAddr); + +/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ + +/* Reset MV_DEBUG_TIMES entry */ +void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); + +/* Update MV_DEBUG_TIMES entry */ +void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); + +/* Print out MV_DEBUG_TIMES entry */ +void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); + + +/******** General ***********/ + +/* Change value of mvDebugPrint global variable */ + +void mvDebugInit(void); +void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); +void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); +void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); + + +#endif /* __INCmvDebug.h */ + diff --git a/board/mv_feroceon/common/mvDeviceId.h b/board/mv_feroceon/common/mvDeviceId.h new file mode 100644 index 0000000..18316f4 --- /dev/null +++ b/board/mv_feroceon/common/mvDeviceId.h @@ -0,0 +1,235 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDeviceIdh +#define __INCmvDeviceIdh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ +#define MARVELL_VEN_ID 0x11ab + +/* Disco-3 */ +#define MV64460_DEV_ID 0x6480 +#define MV64460B_DEV_ID 0x6485 +#define MV64430_DEV_ID 0x6420 + +/* Disco-5 */ +#define MV64560_DEV_ID 0x6450 + +/* Disco-6 */ +#define MV64660_DEV_ID 0x6460 + +/* Orion */ +#define MV_1181_DEV_ID 0x1181 +#define MV_5181_DEV_ID 0x5181 +#define MV_5281_DEV_ID 0x5281 +#define MV_5182_DEV_ID 0x5182 +#define MV_8660_DEV_ID 0x8660 +#define MV_5180_DEV_ID 0x5180 +#define MV_5082_DEV_ID 0x5082 +#define MV_1281_DEV_ID 0x1281 +#define MV_6082_DEV_ID 0x6082 +#define MV_6183_DEV_ID 0x6183 +#define MV_6183L_DEV_ID 0x6083 + +#define MV_5281_D0_REV 0x4 +#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) +#define MV_5281_D0_NAME "88F5281 D0" + +#define MV_5281_D1_REV 0x5 +#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) +#define MV_5281_D1_NAME "88F5281 D1" + +#define MV_5281_D2_REV 0x6 +#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) +#define MV_5281_D2_NAME "88F5281 D2" + + +#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ +#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ +#define MV_5181_B0_REV 0x2 +#define MV_5181_B1_REV 0x3 +#define MV_5182_A1_REV 0x1 +#define MV_5180N_B1_REV 0x3 +#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) + + + +/* kw */ +#define MV_6281_DEV_ID 0x6281 +#define MV_6282_DEV_ID 0x6282 +#define MV_6192_DEV_ID 0x6192 +#define MV_6190_DEV_ID 0x6190 +#define MV_6180_DEV_ID 0x6180 +#define MV_6280_DEV_ID 0x6280 + +#define MV_6281_A0_REV 0x2 +#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) +#define MV_6281_A0_NAME "88F6281 A0" + +#define MV_6192_A0_REV 0x2 +#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) +#define MV_6192_A0_NAME "88F6192 A0" + +#define MV_6190_A0_REV 0x2 +#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) +#define MV_6190_A0_NAME "88F6190 A0" + +#define MV_6180_A0_REV 0x2 +#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) +#define MV_6180_A0_NAME "88F6180 A0" + +#define MV_6281_A1_REV 0x3 +#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) +#define MV_6281_A1_NAME "88F6281 A1" + +#define MV_6282_A0_REV 0x0 +#define MV_6282_A0_ID ((MV_6282_DEV_ID << 16) | MV_6282_A0_REV) +#define MV_6282_A0_NAME "88F6282 A0" + +#define MV_6280_A1_REV 0x3 +#define MV_6280_A1_ID ((MV_6280_DEV_ID << 16) | MV_6280_A1_REV) +#define MV_6280_A1_NAME "88F6280 A1" + +#define MV_6192_A1_REV 0x3 +#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) +#define MV_6192_A1_NAME "88F6192 A1" + +#define MV_6190_A1_REV 0x3 +#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) +#define MV_6190_A1_NAME "88F6190 A1" + +#define MV_6180_A1_REV 0x3 +#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) +#define MV_6180_A1_NAME "88F6180 A1" + +#define MV_88F6XXX_A0_REV 0x2 +#define MV_88F6XXX_A1_REV 0x3 +/* Disco-Duo */ +#define MV_78XX0_ZY_DEV_ID 0x6381 +#define MV_78XX0_ZY_NAME "MV78X00" + +#define MV_78XX0_Z0_REV 0x1 +#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) +#define MV_78XX0_Z0_NAME "78X00 Z0" + +#define MV_78XX0_Y0_REV 0x2 +#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) +#define MV_78XX0_Y0_NAME "78X00 Y0" + +#define MV_78XX0_DEV_ID 0x7800 +#define MV_78XX0_NAME "MV78X00" + +#define MV_76100_DEV_ID 0x7610 +#define MV_78200_DEV_ID 0x7820 +#define MV_78100_DEV_ID 0x7810 +#define MV_78XX0_A0_REV 0x1 +#define MV_78XX0_A1_REV 0x2 + +#define MV_76100_NAME "MV76100" +#define MV_78100_NAME "MV78100" +#define MV_78200_NAME "MV78200" + +#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) +#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) +#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) + +#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) +#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) +#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) + +#define MV_76100_A0_NAME "MV76100 A0" +#define MV_78100_A0_NAME "MV78100 A0" +#define MV_78200_A0_NAME "MV78200 A0" +#define MV_78XX0_A0_NAME "MV78XX0 A0" + +#define MV_76100_A1_NAME "MV76100 A1" +#define MV_78100_A1_NAME "MV78100 A1" +#define MV_78200_A1_NAME "MV78200 A1" +#define MV_78XX0_A1_NAME "MV78XX0 A1" + +/*MV88F632X family*/ +#define MV_6321_DEV_ID 0x6321 +#define MV_6322_DEV_ID 0x6322 +#define MV_6323_DEV_ID 0x6323 + +#define MV_6321_NAME "88F6321" +#define MV_6322_NAME "88F6322" +#define MV_6323_NAME "88F6323" + +#define MV_632X_A1_REV 0x2 + +#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) +#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) +#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) + +#define MV_6321_A1_NAME "88F6321 A1" +#define MV_6322_A1_NAME "88F6322 A1" +#define MV_6323_A1_NAME "88F6323 A1" + + +#endif /* __INCmvDeviceIdh */ diff --git a/board/mv_feroceon/common/mvHalVer.h b/board/mv_feroceon/common/mvHalVer.h new file mode 100644 index 0000000..6c3f973 --- /dev/null +++ b/board/mv_feroceon/common/mvHalVer.h @@ -0,0 +1,73 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvHalVerh +#define __INCmvHalVerh + +/* Defines */ +#define MV_HAL_VERSION "FEROCEON_HAL_3_1_5" +#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_6_14_2009_NetBSD_KW_2_1_3" + +#endif /* __INCmvHalVerh */ \ No newline at end of file diff --git a/board/mv_feroceon/common/mvStack.c b/board/mv_feroceon/common/mvStack.c new file mode 100644 index 0000000..fad0c4e --- /dev/null +++ b/board/mv_feroceon/common/mvStack.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* Copyright 2003, Marvell Semiconductor Israel LTD. * +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * +* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * +* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * +* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * +* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * +* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * +* * +* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * +* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * +* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * +* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * +******************************************************************************** +* mvQueue.c +* +* FILENAME: $Workfile: mvStack.c $ +* REVISION: $Revision: $ +* LAST UPDATE: $Modtime: $ +* +* DESCRIPTION: +* This file implements simple Stack LIFO functionality. +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mvTypes.h" +#include "mvDebug.h" +#include "mvStack.h" + +/* defines */ + + +/* Public functions */ + + +/* Purpose: Create new stack + * Inputs: + * - MV_U32 noOfElements - maximum number of elements in the stack. + * Each element 4 bytes size + * Return: void* - pointer to created stack. + */ +void* mvStackCreate(int numOfElements) +{ + MV_STACK* pStack; + MV_U32* pStackElements; + + pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); + pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); + if( (pStack == NULL) || (pStackElements == NULL) ) + { + mvOsPrintf("mvStack: Can't create new stack\n"); + return NULL; + } + memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); + pStack->numOfElements = numOfElements; + pStack->stackIdx = 0; + pStack->stackElements = pStackElements; + + return pStack; +} + +/* Purpose: Delete existing stack + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function + * + * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. + * MV_OK - Success. + */ +MV_STATUS mvStackDelete(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + + if( (pStack == NULL) || (pStack->stackElements == NULL) ) + return MV_NOT_FOUND; + + mvOsFree(pStack->stackElements); + mvOsFree(pStack); + + return MV_OK; +} + + +/* PrintOut status of the stack */ +void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) +{ + int i; + MV_STACK* pStack = (MV_STACK*)stackHndl; + + mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", + stackHndl, pStack->stackElements, pStack->numOfElements, + pStack->stackIdx); + if(isPrintElements == MV_TRUE) + { + for(i=0; istackIdx; i++) + { + mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); + } + } +} diff --git a/board/mv_feroceon/common/mvStack.h b/board/mv_feroceon/common/mvStack.h new file mode 100644 index 0000000..27f1597 --- /dev/null +++ b/board/mv_feroceon/common/mvStack.h @@ -0,0 +1,140 @@ +/******************************************************************************* +* Copyright 2003, Marvell Semiconductor Israel LTD. * +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * +* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * +* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * +* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * +* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * +* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * +* * +* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * +* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * +* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * +* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * +******************************************************************************** +* mvStack.h - Header File for : +* +* FILENAME: $Workfile: mvStack.h $ +* REVISION: $Revision: $ +* LAST UPDATE: $Modtime: $ +* +* DESCRIPTION: +* This file defines simple Stack (LIFO) functionality. +* +*******************************************************************************/ + +#ifndef __mvStack_h__ +#define __mvStack_h__ + + +/* includes */ +#include "mvTypes.h" + + +/* defines */ + + +/* typedefs */ +/* Data structure describes general purpose Stack */ +typedef struct +{ + int stackIdx; + int numOfElements; + MV_U32* stackElements; +} MV_STACK; + +static INLINE MV_BOOL mvStackIsFull(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + + if(pStack->stackIdx == pStack->numOfElements) + return MV_TRUE; + + return MV_FALSE; +} + +static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + + if(pStack->stackIdx == 0) + return MV_TRUE; + + return MV_FALSE; +} +/* Purpose: Push new element to stack + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. + * - MV_U32 value - New element. + * + * Return: MV_STATUS MV_FULL - Failure. Stack is full. + * MV_OK - Success. Element is put to stack. + */ +static INLINE void mvStackPush(void* stackHndl, MV_U32 value) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + +#ifdef MV_RT_DEBUG + if(pStack->stackIdx == pStack->numOfElements) + { + mvOsPrintf("mvStackPush: Stack is FULL\n"); + return; + } +#endif /* MV_RT_DEBUG */ + + pStack->stackElements[pStack->stackIdx] = value; + pStack->stackIdx++; +} + +/* Purpose: Pop element from the top of stack and copy it to "pValue" + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. + * - MV_U32 value - Element in the top of stack. + * + * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. + * MV_OK - Success. Element is removed from the stack and + * copied to pValue argument + */ +static INLINE MV_U32 mvStackPop(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + +#ifdef MV_RT_DEBUG + if(pStack->stackIdx == 0) + { + mvOsPrintf("mvStackPop: Stack is EMPTY\n"); + return 0; + } +#endif /* MV_RT_DEBUG */ + + pStack->stackIdx--; + return pStack->stackElements[pStack->stackIdx]; +} + +static INLINE int mvStackIndex(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + + return pStack->stackIdx; +} + +static INLINE int mvStackFreeElements(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + + return (pStack->numOfElements - pStack->stackIdx); +} + +/* mvStack.h API list */ + +/* Create new Stack */ +void* mvStackCreate(int numOfElements); + +/* Delete existing stack */ +MV_STATUS mvStackDelete(void* stackHndl); + +/* Print status of the stack */ +void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); + +#endif /* __mvStack_h__ */ + diff --git a/board/mv_feroceon/common/mvTypes.h b/board/mv_feroceon/common/mvTypes.h new file mode 100644 index 0000000..de212a1 --- /dev/null +++ b/board/mv_feroceon/common/mvTypes.h @@ -0,0 +1,245 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvTypesh +#define __INCmvTypesh + +/* Defines */ + +/* The following is a list of Marvell status */ +#define MV_ERROR (-1) +#define MV_OK (0x00) /* Operation succeeded */ +#define MV_FAIL (0x01) /* Operation failed */ +#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ +#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ +#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ +#define MV_BAD_PTR (0x05) /* Illegal pointer value */ +#define MV_BAD_SIZE (0x06) /* Illegal size */ +#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ +#define MV_SET_ERROR (0x08) /* Set operation failed */ +#define MV_GET_ERROR (0x09) /* Get operation failed */ +#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ +#define MV_NOT_FOUND (0x0B) /* Item not found */ +#define MV_NO_MORE (0x0C) /* No more items found */ +#define MV_NO_SUCH (0x0D) /* No such item */ +#define MV_TIMEOUT (0x0E) /* Time Out */ +#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ +#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ +#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ +#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ +#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ +#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ +#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ +#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ +#define MV_HW_ERROR (0x17) /* Hardware error */ +#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ +#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ +#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ +#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ +#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ +#define MV_NOT_STARTED (0x1D) /* Not started yet */ +#define MV_BUSY (0x1E) /* Item is busy. */ +#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ +#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ +#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ +#define MV_WRITE_PROTECT (0x22) /* Write protected */ + + +#define MV_INVALID (int)(-1) + +#define MV_FALSE 0 +#define MV_TRUE (!(MV_FALSE)) + + +#ifndef NULL +#define NULL ((void*)0) +#endif + + +#ifndef MV_ASMLANGUAGE +/* typedefs */ + +typedef char MV_8; +typedef unsigned char MV_U8; + +typedef int MV_32; +typedef unsigned int MV_U32; + +typedef short MV_16; +typedef unsigned short MV_U16; + +#ifdef MV_PPC64 +typedef long MV_64; +typedef unsigned long MV_U64; +#else +typedef long long MV_64; +typedef unsigned long long MV_U64; +#endif + +typedef long MV_LONG; /* 32/64 */ +typedef unsigned long MV_ULONG; /* 32/64 */ + +typedef int MV_STATUS; +typedef int MV_BOOL; +typedef void MV_VOID; +typedef float MV_FLOAT; + +typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ +typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ +typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ +typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ + +typedef MV_U32 MV_KHZ; +typedef MV_U32 MV_MHZ; +typedef MV_U32 MV_HZ; + + +/* This enumerator describes the set of commands that can be applied on */ +/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ +/* status (see MV_STATE enumerator) */ +/* Start can be applied only when status is IDLE */ +/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ +/* Pause can be applied only when status is ACTIVE */ +/* Restart can be applied only when status is PAUSED */ +typedef enum _mvCommand +{ + MV_START, /* Start */ + MV_STOP, /* Stop */ + MV_PAUSE, /* Pause */ + MV_RESTART /* Restart */ +} MV_COMMAND; + +/* This enumerator describes the set of state conditions. */ +/* Moving from one state to other is stricted. */ +typedef enum _mvState +{ + MV_IDLE, + MV_ACTIVE, + MV_PAUSED, + MV_UNDEFINED_STATE +} MV_STATE; + + +/* This structure describes address space window. Window base can be */ +/* 64 bit, window size up to 4GB */ +typedef struct _mvAddrWin +{ + MV_U32 baseLow; /* 32bit base low */ + MV_U32 baseHigh; /* 32bit base high */ + MV_U32 size; /* 32bit size */ +}MV_ADDR_WIN; + +/* This binary enumerator describes protection attribute status */ +typedef enum _mvProtRight +{ + ALLOWED, /* Protection attribute allowed */ + FORBIDDEN /* Protection attribute forbidden */ +}MV_PROT_RIGHT; + +/* Unified struct for Rx and Tx packet operations. The user is required to */ +/* be familier only with Tx/Rx descriptor command status. */ +typedef struct _bufInfo +{ + MV_U32 cmdSts; /* Tx/Rx command status */ + MV_U16 byteCnt; /* Size of valid data in the buffer */ + MV_U16 bufSize; /* Total size of the buffer */ + MV_U8 *pBuff; /* Pointer to Buffer */ + MV_U8 *pData; /* Pointer to data in the Buffer */ + MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ + MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ + struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ +} BUF_INFO; + +/* This structure contains information describing one of buffers + * (fragments) they are built Ethernet packet. + */ +typedef struct +{ + MV_U8* bufVirtPtr; + MV_ULONG bufPhysAddr; + MV_U32 bufSize; + MV_U32 dataSize; + MV_U32 memHandle; + MV_32 bufAddrShift; +} MV_BUF_INFO; + +/* This structure contains information describing Ethernet packet. + * The packet can be divided for few buffers (fragments) + */ +typedef struct +{ + MV_ULONG osInfo; + MV_BUF_INFO *pFrags; + MV_U32 status; + MV_U16 pktSize; + MV_U16 numFrags; + MV_U32 ownerId; + MV_U32 fragIP; +} MV_PKT_INFO; + +#endif /* MV_ASMLANGUAGE */ + +#endif /* __INCmvTypesh */ + diff --git a/board/mv_feroceon/config/Makefile b/board/mv_feroceon/config/Makefile new file mode 100644 index 0000000..162f4a6 --- /dev/null +++ b/board/mv_feroceon/config/Makefile @@ -0,0 +1,81 @@ +include mvRules.mk + + +# Objects list + +COMMON_OBJS = $(COMMON_DIR)/mvCommon.o + +OSSERVICES_OBJS = $(OSSERVICES_DIR)/mvOs.o $(OSSERVICES_DIR)/mvOsSata.o + +BOARD_OBJS = $(BOARD_ENV_DIR)/mvBoardEnvLib.o $(BOARD_ENV_DIR)/mvBoardEnvSpec.o + +HAL_OBJS = $(HAL_FLASH_DIR)/mvFlash.o $(HAL_FLASH_DIR)/mvAmdFlash.o $(HAL_FLASH_DIR)/mvIntelFlash.o \ + $(HAL_FLASH_DIR)/mvFlashCom.o $(HAL_DRAM_DIR)/mvDram.o $(HAL_DRAM_DIR)/mvDramIf.o \ + $(HAL_SATA_CORE_DIR)/mvSata.o $(HAL_SATA_CORE_DIR)/mvStorageDev.o \ + $(HAL_SATA_CORE_DIR)/mvLog.o $(HAL_SFLASH_DIR)/mvSFlash.o \ + $(HAL_ETHPHY_DIR)/mvEthPhy.o $(HAL_RTC_DIR)/mvDS133x.o \ + $(HAL_CNTMR_DIR)/mvCntmr.o $(HAL_TWSI_DIR)/mvTwsi.o \ + $(HAL_UART_DIR)/mvUart.o $(HAL_GPP_DIR)/mvGpp.o $(HAL_SPI_DIR)/mvSpi.o \ + $(HAL_SPI_DIR)/mvSpiCmnd.o $(HAL_PCI_DIR)/mvPci.o $(HAL_USB_DIR)/mvUsb.o \ + $(HAL_IDMA_DIR)/mvIdma.o $(HAL_XOR_DIR)/mvXor.o \ + $(HAL_ETH_GBE_DIR)/mvEth.o $(HAL_PCIIF_DIR)/mvPciIf.o \ + $(HAL_PEX_DIR)/mvPex.o + + +SOC_OBJS = $(SOC_DIR)/mv_cmd.o $(SOC_DIR)/mv_dram.o $(SOC_DIR)/mv_main.o $(SOC_DIR)/mv_service.o \ + $(SOC_ENV_DIR)/mvCtrlEnvLib.o $(SOC_ENV_DIR)/mvCtrlEnvPadCalibration.o \ + $(SOC_ENV_DIR)/mvCtrlEnvAddrDec.o $(SOC_SYS_DIR)/mvAhbToMbus.o \ + $(SOC_SYS_DIR)/mvCpuIf.o $(SOC_SYS_DIR)/mvSysXor.o \ + $(SOC_SYS_DIR)/mvSysGbe.o $(SOC_SYS_DIR)/mvSysIdma.o $(SOC_SYS_DIR)/mvSysPci.o \ + $(SOC_SYS_DIR)/mvSysPex.o $(SOC_SYS_DIR)/mvSysSata.o $(SOC_SYS_DIR)/mvSysUsb.o \ + $(SOC_CPU_DIR)/mvCpuArm.o $(SOC_DEVICE_DIR)/mvDevice.o + +ifneq ($(MV_TINY_IMAGE), y) +SOC_OBJS += $(HAL_PCIIF_DIR)/pci_util/mvPciUtils.o +endif + +USP_OBJS = $(USP_DIR)/mv_flash.o $(USP_DIR)/mv_serial.o \ + $(USP_DIR)/mv_pageTable.o $(USP_DIR)/mv_rtc.o $(USP_DIR)/mv_mon_init.o \ + $(USP_DIR)/mv_pci.o $(USP_DIR)/mv_nand.o \ + $(USP_DIR)/mv_ide.o $(USP_DIR)/mv_egiga.o \ + $(USP_DIR)/mv_fs.o $(USP_DIR)/mv_loadnet.o $(USP_DIR)/mv_protectionUnit.o \ + $(USP_DIR)/mv_i2c.o $(USP_DIR)/mv_ext2_boot.o $(USP_ETH_SWITCH_DIR)/mvSwitch.o + +ifeq ($(NAND_BOOT), y) +USP_OBJS += $(USP_DIR)/nBootloader.o +endif + +SOBJS = ../USP/jump.o \ + ../mv_orion/platform.o \ + $(HAL_DRAM_DIR)/mvDramIfBasicInit.o \ + $(HAL_DRAM_DIR)/mvDramIfConfig.o \ + $(HAL_DIR)/twsi/mvTwsiEeprom.o \ + $(SOC_SYS_DIR)/mvCpuIfInit.o + +ifeq ($(NAND_BOOT), y) +ifeq ($(NAND_LARGE_PAGE), y) +SOBJS += ../mv_orion/nBootstrap_LP.o +else +SOBJS += ../mv_orion/nBootstrap.o +endif +endif + + +OBJS = $(COMMON_OBJS) $(OSSERVICES_OBJS) $(HAL_OBJS) $(SOC_OBJS) $(BOARD_OBJS) $(USP_OBJS) + +LIB = lib$(BOARD).a + +all: $(LIB) + +$(LIB): .depend $(SOBJS) $(OBJS) + $(AR) crv $@ $(SOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### + diff --git a/board/mv_feroceon/config/config.mk b/board/mv_feroceon/config/config.mk new file mode 100644 index 0000000..695d9aa --- /dev/null +++ b/board/mv_feroceon/config/config.mk @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00f10000 +# + +TEXT_BASE = 0x00200000 diff --git a/board/mv_feroceon/config/config_16mb.mk b/board/mv_feroceon/config/config_16mb.mk new file mode 100644 index 0000000..9452ff9 --- /dev/null +++ b/board/mv_feroceon/config/config_16mb.mk @@ -0,0 +1,4 @@ +# +# image should be loaded at 0x00c00000 +# +TEXT_BASE = 0x00c10000 diff --git a/board/mv_feroceon/config/config_def.mk b/board/mv_feroceon/config/config_def.mk new file mode 100644 index 0000000..695d9aa --- /dev/null +++ b/board/mv_feroceon/config/config_def.mk @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00f10000 +# + +TEXT_BASE = 0x00200000 diff --git a/board/mv_feroceon/config/config_nand.mk b/board/mv_feroceon/config/config_nand.mk new file mode 100644 index 0000000..c16140f --- /dev/null +++ b/board/mv_feroceon/config/config_nand.mk @@ -0,0 +1,15 @@ + +BOOT_TEXT_BASE = 0x00020000 + +NAND_LDSCRIPT = ./board/$(BOARDDIR)/u-boot-nand.lds + +NAND_LDFLAGS += -Bdynamic -T $(NAND_LDSCRIPT) -Ttext $(BOOT_TEXT_BASE) $(PLATFORM_LDFLAGS) + + +ifeq ($(NAND_LARGE_PAGE), y) +NAND_OBJS = ./board/mv_feroceon/USP/nBootstrap_LP.o +else +NAND_OBJS = ./board/mv_feroceon/USP/nBootstrap.o +endif + +NAND_OBJS += ./board/mv_feroceon/USP/nBootloader.o diff --git a/board/mv_feroceon/config/config_prpmc.mk b/board/mv_feroceon/config/config_prpmc.mk new file mode 100644 index 0000000..ac0295c --- /dev/null +++ b/board/mv_feroceon/config/config_prpmc.mk @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x02f00000 +# + +TEXT_BASE = 0x02f10000 diff --git a/board/mv_feroceon/config/mvRules.mk b/board/mv_feroceon/config/mvRules.mk new file mode 100644 index 0000000..38348dd --- /dev/null +++ b/board/mv_feroceon/config/mvRules.mk @@ -0,0 +1,77 @@ +# This flags will be used only by the Marvell arch files compilation. +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk + + +# General definitions +CPU_ARCH = ARM +CHIP = orion +VENDOR = Marvell +ENDIAN = LE +LD_ENDIAN = -EL + +ifeq ($(BIG_ENDIAN),y) +ENDIAN = BE +LD_ENDIAN = -EB +endif + + +# Main directory structure +SRC_PATH = $(TOPDIR)/board/mv_feroceon +HAL_DIR = $(SRC_PATH)/mv_hal +COMMON_DIR = $(SRC_PATH)/common +USP_DIR = $(SRC_PATH)/USP +SOC_DIR = $(SRC_PATH)/mv_$(CHIP) +SYS_DIR = $(SRC_PATH)/mv_$(CHIP)/$(CHIP)_sys +ORION_FAM_DIR = $(SOC_DIR)/$(CHIP)_family +SOC_ENV_DIR = $(ORION_FAM_DIR)/ctrlEnv +SOC_SYS_DIR = $(ORION_FAM_DIR)/ctrlEnv/sys +SOC_CPU_DIR = $(ORION_FAM_DIR)/cpu +SOC_DEVICE_DIR = $(ORION_FAM_DIR)/device +BOARD_ENV_DIR = $(ORION_FAM_DIR)/boardEnv +USP_ETH_SWITCH_DIR = $(USP_DIR)/ethSwitch + +# HAL components +HAL_DRAM_DIR = $(HAL_DIR)/ddr1_2 +HAL_ETHPHY_DIR = $(HAL_DIR)/eth-phy +HAL_FLASH_DIR = $(HAL_DIR)/norflash +HAL_PCI_DIR = $(HAL_DIR)/pci +HAL_PCIIF_DIR = $(HAL_DIR)/pci-if +HAL_RTC_DIR = $(HAL_DIR)/rtc/ext_rtc +HAL_SFLASH_DIR = $(HAL_DIR)/sflash +HAL_SATA_CORE_DIR = $(HAL_DIR)/sata/CoreDriver/ +HAL_CNTMR_DIR = $(HAL_DIR)/cntmr +HAL_GPP_DIR = $(HAL_DIR)/gpp +HAL_IDMA_DIR = $(HAL_DIR)/idma +HAL_PEX_DIR = $(HAL_DIR)/pex +HAL_TWSI_DIR = $(HAL_DIR)/twsi +HAL_ETH_DIR = $(HAL_DIR)/eth +HAL_ETH_GBE_DIR = $(HAL_DIR)/eth/gbe +HAL_UART_DIR = $(HAL_DIR)/uart +HAL_XOR_DIR = $(HAL_DIR)/xor +HAL_USB_DIR = $(HAL_DIR)/usb +HAL_SATA_DIR = $(HAL_DIR)/sata +HAL_MFLASH_DIR = $(HAL_DIR)/mflash +HAL_SPI_DIR = $(HAL_DIR)/spi + +# OS services +OSSERVICES_DIR = $(SRC_PATH)/uboot_oss + +# Internal definitions +MV_DEFINE = -DMV_UBOOT -DMV_CPU_$(ENDIAN) -DMV_$(CPU_ARCH) + +# Internal include path +HAL_PATH = -I$(HAL_DIR) -I$(HAL_SATA_CORE_DIR) +COMMON_PATH = -I$(COMMON_DIR) +OSSERVICES_PATH = -I$(OSSERVICES_DIR) +USP_PATH = -I$(USP_DIR) +SOC_PATH = -I$(ORION_FAM_DIR) -I$(SOC_DIR) -I$(SOC_ENV_DIR) -I$(SOC_SYS_DIR) -I$(SOC_CPU_DIR) -I$(SOC_DEVICE_DIR) +BOARD_PATH = -I$(BOARD_ENV_DIR) +SYS_PATH = -I$(SYS_DIR) + +CFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +AFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + diff --git a/board/mv_feroceon/config/u-boot-nand.lds b/board/mv_feroceon/config/u-boot-nand.lds new file mode 100644 index 0000000..bd515d5 --- /dev/null +++ b/board/mv_feroceon/config/u-boot-nand.lds @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : { *(.text) } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + __u_boot_cmd_end = .; + + . = ALIGN(4); + _bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config/u-boot-sec128k-tiny.lds b/board/mv_feroceon/config/u-boot-sec128k-tiny.lds new file mode 100644 index 0000000..9df76fa --- /dev/null +++ b/board/mv_feroceon/config/u-boot-sec128k-tiny.lds @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x20000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config/u-boot-sec128k.lds b/board/mv_feroceon/config/u-boot-sec128k.lds new file mode 100644 index 0000000..3e8ec79 --- /dev/null +++ b/board/mv_feroceon/config/u-boot-sec128k.lds @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x20000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config/u-boot-sec256k.lds b/board/mv_feroceon/config/u-boot-sec256k.lds new file mode 100644 index 0000000..203ff14 --- /dev/null +++ b/board/mv_feroceon/config/u-boot-sec256k.lds @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x40000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config/u-boot-sec4k-header-tiny.lds b/board/mv_feroceon/config/u-boot-sec4k-header-tiny.lds new file mode 100644 index 0000000..fc85653 --- /dev/null +++ b/board/mv_feroceon/config/u-boot-sec4k-header-tiny.lds @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3ec00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x3ee00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config/u-boot-sec4k-tiny.lds b/board/mv_feroceon/config/u-boot-sec4k-tiny.lds new file mode 100644 index 0000000..988fbd9 --- /dev/null +++ b/board/mv_feroceon/config/u-boot-sec4k-tiny.lds @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3c000; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config/u-boot-sec4k.lds b/board/mv_feroceon/config/u-boot-sec4k.lds new file mode 100644 index 0000000..47712f8 --- /dev/null +++ b/board/mv_feroceon/config/u-boot-sec4k.lds @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config/u-boot-sec64k-header-nand.lds b/board/mv_feroceon/config/u-boot-sec64k-header-nand.lds new file mode 100644 index 0000000..f292c75 --- /dev/null +++ b/board/mv_feroceon/config/u-boot-sec64k-header-nand.lds @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7DC00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/mv_feroceon/config/u-boot-sec64k-header.lds b/board/mv_feroceon/config/u-boot-sec64k-header.lds new file mode 100644 index 0000000..3685db3 --- /dev/null +++ b/board/mv_feroceon/config/u-boot-sec64k-header.lds @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FE00; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/mv_feroceon/config/u-boot-sec64k-tiny.lds b/board/mv_feroceon/config/u-boot-sec64k-tiny.lds new file mode 100644 index 0000000..d3bece6 --- /dev/null +++ b/board/mv_feroceon/config/u-boot-sec64k-tiny.lds @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x10000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/mv_feroceon/config/u-boot-sec64k.lds b/board/mv_feroceon/config/u-boot-sec64k.lds new file mode 100644 index 0000000..353b77d --- /dev/null +++ b/board/mv_feroceon/config/u-boot-sec64k.lds @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x10000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x60000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config/u-boot.lds b/board/mv_feroceon/config/u-boot.lds new file mode 100644 index 0000000..3685db3 --- /dev/null +++ b/board/mv_feroceon/config/u-boot.lds @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FE00; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/mv_feroceon/config/u-boot_16mb.lds b/board/mv_feroceon/config/u-boot_16mb.lds new file mode 100644 index 0000000..5ce504e --- /dev/null +++ b/board/mv_feroceon/config/u-boot_16mb.lds @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .dummy 0x00c00000 : { board/mv_feroceon/USP/jump.o (.dummy) } + . = 0x0c10000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + .reset_vector_sect 0x00c70000 : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_dd/Makefile b/board/mv_feroceon/config_dd/Makefile new file mode 100644 index 0000000..3111351 --- /dev/null +++ b/board/mv_feroceon/config_dd/Makefile @@ -0,0 +1,81 @@ +include mvRules.mk + + +# Objects list + +COMMON_OBJS = $(COMMON_DIR)/mvCommon.o + +OSSERVICES_OBJS = $(OSSERVICES_DIR)/mvOs.o $(OSSERVICES_DIR)/mvOsSata.o + +BOARD_OBJS = $(BOARD_ENV_DIR)/mvBoardEnvLib.o $(BOARD_ENV_DIR)/mvBoardEnvSpec.o + +HAL_OBJS = $(HAL_FLASH_DIR)/mvFlash.o $(HAL_FLASH_DIR)/mvAmdFlash.o $(HAL_FLASH_DIR)/mvIntelFlash.o \ + $(HAL_FLASH_DIR)/mvFlashCom.o $(HAL_SPD_DIR)/mvSpd.o $(HAL_DRAM_DIR)/mvDramIf.o \ + $(HAL_SATA_CORE_DIR)/mvSata.o $(HAL_SATA_CORE_DIR)/mvStorageDev.o \ + $(HAL_SATA_CORE_DIR)/mvLog.o $(HAL_SFLASH_DIR)/mvSFlash.o \ + $(HAL_ETHPHY_DIR)/mvEthPhy.o $(HAL_RTC_DIR)/mvDS133x.o \ + $(HAL_CNTMR_DIR)/mvCntmr.o $(HAL_TWSI_DIR)/mvTwsi.o \ + $(HAL_UART_DIR)/mvUart.o $(HAL_GPP_DIR)/mvGpp.o \ + $(HAL_SPI_DIR)/mvSpi.o \ + $(HAL_SPI_DIR)/mvSpiCmnd.o $(HAL_USB_DIR)/mvUsb.o \ + $(HAL_IDMA_DIR)/mvIdma.o $(HAL_XOR_DIR)/mvXor.o \ + $(HAL_ETH_GBE_DIR)/mvEth.o $(HAL_PCIIF_DIR)/mvPciIf.o \ + $(HAL_ETH_GBE_DIR)/mvEthDebug.o $(HAL_PEX_DIR)/mvPex.o $(HAL_PEX_DIR)/mvVrtBrgPex.o \ + $(HAL_CESA_DIR)/mvMD5.o + + +SOC_OBJS = $(SOC_DIR)/mv_cmd.o $(SOC_DIR)/mv_dram.o $(SOC_DIR)/mv_main.o \ + $(SOC_DIR)/mv_service.o $(SOC_ENV_DIR)/mvCtrlEnvLib.o \ + $(SOC_ENV_DIR)/mvCtrlEnvAddrDec.o $(SOC_SYS_DIR)/mvAhbToMbus.o \ + $(SOC_SYS_DIR)/mvCpuIf.o $(SOC_SYS_DIR)/mvSysXor.o $(SOC_SYS_DIR)/mvSysDram.o\ + $(SOC_SYS_DIR)/mvSysGbe.o $(SOC_SYS_DIR)/mvSysIdma.o \ + $(SOC_SYS_DIR)/mvSysPex.o $(SOC_SYS_DIR)/mvSysSata.o $(SOC_SYS_DIR)/mvSysUsb.o \ + $(SOC_DEVICE_DIR)/mvDevice.o $(SOC_CPU_DIR)/mvCpu.o $(HAL_PCIIF_DIR)/pci_util/mvPciUtils.o + +ifeq ($(MV78200), y) +SOC_OBJS += $(ORION_FAM_DIR)/mv78200/mvSocUnitMap.o +SOC_OBJS += $(ORION_FAM_DIR)/mv78200/mvSemaphore.o +endif + +USP_OBJS = $(USP_DIR)/mv_flash.o $(USP_DIR)/mv_serial.o \ + $(USP_DIR)/mv_pageTable.o $(USP_DIR)/mv_rtc.o $(USP_DIR)/mv_mon_init.o \ + $(USP_DIR)/mv_pci.o $(USP_DIR)/mv_nand.o \ + $(USP_DIR)/mv_ide.o $(USP_DIR)/mv_egiga.o \ + $(USP_DIR)/mv_fs.o $(USP_DIR)/mv_loadnet.o $(USP_DIR)/mv_protectionUnit.o \ + $(USP_DIR)/mv_i2c.o $(USP_DIR)/mv_ext2_boot.o \ + $(USP_DIR)/ethSwitch/mvSwitch.o + +ifeq ($(NAND_BOOT), y) +USP_OBJS += $(USP_DIR)/nBootloader.o +endif + +SOBJS = $(USP_DIR)/jump.o \ + $(SOC_DIR)/platform.o \ + $(HAL_DRAM_DIR)/mvDramIfBasicInit.o \ + $(HAL_DRAM_DIR)/mvDramIfConfig.o \ + $(HAL_TWSI_DIR)/mvTwsiEeprom.o +# $(SOC_SYS_DIR)/mvCpuIfInit.o + +ifeq ($(NAND_BOOT), y) +SOBJS += $(SOC_DIR)/nBootstrap.o +endif + + +OBJS = $(COMMON_OBJS) $(OSSERVICES_OBJS) $(HAL_OBJS) $(SOC_OBJS) $(BOARD_OBJS) $(USP_OBJS) + +LIB = lib$(BOARD).a + +all: $(LIB) + +$(LIB): .depend $(SOBJS) $(OBJS) + $(AR) crv $@ $(SOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### + diff --git a/board/mv_feroceon/config_dd/config.mk b/board/mv_feroceon/config_dd/config.mk new file mode 100644 index 0000000..1e65e79 --- /dev/null +++ b/board/mv_feroceon/config_dd/config.mk @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00f10000 +# + +TEXT_BASE = 0x00600000 diff --git a/board/mv_feroceon/config_dd/config_def.mk b/board/mv_feroceon/config_dd/config_def.mk new file mode 100644 index 0000000..1e65e79 --- /dev/null +++ b/board/mv_feroceon/config_dd/config_def.mk @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00f10000 +# + +TEXT_BASE = 0x00600000 diff --git a/board/mv_feroceon/config_dd/config_nand.mk b/board/mv_feroceon/config_dd/config_nand.mk new file mode 100644 index 0000000..95267ce --- /dev/null +++ b/board/mv_feroceon/config_dd/config_nand.mk @@ -0,0 +1,15 @@ + +BOOT_TEXT_BASE = 0x00020000 + +NAND_LDSCRIPT = ./board/$(BOARDDIR)/u-boot-nand.lds + +NAND_LDFLAGS += -Bdynamic -T $(NAND_LDSCRIPT) -Ttext $(BOOT_TEXT_BASE) $(PLATFORM_LDFLAGS) + + +ifeq ($(NAND_LARGE_PAGE), y) +NAND_OBJS = ./board/mv_feroceon/mv_dd/nBootstrap_LP.o +else +NAND_OBJS = ./board/mv_feroceon/mv_dd/nBootstrap.o +endif + +NAND_OBJS += ./board/mv_feroceon/USP/nBootloader.o diff --git a/board/mv_feroceon/config_dd/mvRules.mk b/board/mv_feroceon/config_dd/mvRules.mk new file mode 100644 index 0000000..e7b43a8 --- /dev/null +++ b/board/mv_feroceon/config_dd/mvRules.mk @@ -0,0 +1,79 @@ +# This flags will be used only by the Marvell arch files compilation. +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk + + +# General definitions +CPU_ARCH = ARM +CHIP = dd +VENDOR = Marvell +ENDIAN = LE +LD_ENDIAN = -EL + +ifeq ($(BIG_ENDIAN),y) +ENDIAN = BE +LD_ENDIAN = -EB +endif + + +# Main directory structure +SRC_PATH = $(TOPDIR)/board/mv_feroceon +HAL_DIR = $(SRC_PATH)/mv_hal +COMMON_DIR = $(SRC_PATH)/common +USP_DIR = $(SRC_PATH)/USP +SOC_DIR = $(SRC_PATH)/mv_$(CHIP) +ORION_FAM_DIR = $(SOC_DIR)/$(CHIP)_family +SOC_ENV_DIR = $(ORION_FAM_DIR)/ctrlEnv +SOC_SYS_DIR = $(ORION_FAM_DIR)/ctrlEnv/sys +SOC_CPU_DIR = $(ORION_FAM_DIR)/cpu +SOC_DEVICE_DIR = $(ORION_FAM_DIR)/device +BOARD_ENV_DIR = $(ORION_FAM_DIR)/boardEnv + +# HAL components +HAL_DRAM_DIR = $(HAL_DIR)/ddr2 +HAL_SPD_DIR = $(HAL_DRAM_DIR)/spd +HAL_ETHPHY_DIR = $(HAL_DIR)/eth-phy +HAL_FLASH_DIR = $(HAL_DIR)/norflash +HAL_PCI_DIR = $(HAL_DIR)/pci +HAL_PCIIF_DIR = $(HAL_DIR)/pci-if +HAL_RTC_DIR = $(HAL_DIR)/rtc/ext_rtc +HAL_SFLASH_DIR = $(HAL_DIR)/sflash +HAL_SATA_CORE_DIR = $(HAL_DIR)/sata/CoreDriver/ +HAL_CNTMR_DIR = $(HAL_DIR)/cntmr +HAL_GPP_DIR = $(HAL_DIR)/gpp +HAL_IDMA_DIR = $(HAL_DIR)/idma +HAL_PEX_DIR = $(HAL_DIR)/pex +HAL_TWSI_DIR = $(HAL_DIR)/twsi +HAL_TWSI_ARCH_DIR = $(HAL_TWSI_DIR)/Arch$(CPU_ARCH) +HAL_ETH_DIR = $(HAL_DIR)/eth +HAL_ETH_GBE_DIR = $(HAL_ETH_DIR)/gbe +HAL_UART_DIR = $(HAL_DIR)/uart +HAL_XOR_DIR = $(HAL_DIR)/xor +HAL_USB_DIR = $(HAL_DIR)/usb +HAL_SATA_DIR = $(HAL_DIR)/sata +HAL_MFLASH_DIR = $(HAL_DIR)/mflash +HAL_SPI_DIR = $(HAL_DIR)/spi +HAL_TS_DIR = $(HAL_DIR)/ts +HAL_AUDIO_DIR = $(HAL_DIR)/audio +HAL_CESA_DIR = $(HAL_DIR)/cesa + +# OS services +OSSERVICES_DIR = $(SRC_PATH)/uboot_oss + +# Internal definitions +MV_DEFINE = -DMV_UBOOT -DMV_CPU_$(ENDIAN) -DMV_$(CPU_ARCH) + +# Internal include path +HAL_PATH = -I$(HAL_DIR) -I$(HAL_SATA_CORE_DIR) +COMMON_PATH = -I$(COMMON_DIR) +OSSERVICES_PATH = -I$(OSSERVICES_DIR) +USP_PATH = -I$(USP_DIR) +SOC_PATH = -I$(ORION_FAM_DIR) -I$(SOC_DIR) -I$(SOC_ENV_DIR) -I$(SOC_SYS_DIR) -I$(SOC_CPU_DIR) -I$(SOC_DEVICE_DIR) +BOARD_PATH = -I$(BOARD_ENV_DIR) + +CFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +AFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + diff --git a/board/mv_feroceon/config_dd/u-boot-nand.lds b/board/mv_feroceon/config_dd/u-boot-nand.lds new file mode 100644 index 0000000..a0ed0b5 --- /dev/null +++ b/board/mv_feroceon/config_dd/u-boot-nand.lds @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : { *(.text) } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_dd/u-boot-sec128k.lds b/board/mv_feroceon/config_dd/u-boot-sec128k.lds new file mode 100644 index 0000000..3e8ec79 --- /dev/null +++ b/board/mv_feroceon/config_dd/u-boot-sec128k.lds @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x20000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_dd/u-boot-sec256k.lds b/board/mv_feroceon/config_dd/u-boot-sec256k.lds new file mode 100644 index 0000000..203ff14 --- /dev/null +++ b/board/mv_feroceon/config_dd/u-boot-sec256k.lds @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x40000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_dd/u-boot-sec4k-tiny.lds b/board/mv_feroceon/config_dd/u-boot-sec4k-tiny.lds new file mode 100644 index 0000000..988fbd9 --- /dev/null +++ b/board/mv_feroceon/config_dd/u-boot-sec4k-tiny.lds @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3c000; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_dd/u-boot.lds b/board/mv_feroceon/config_dd/u-boot.lds new file mode 100644 index 0000000..3e8ec79 --- /dev/null +++ b/board/mv_feroceon/config_dd/u-boot.lds @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x20000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_dd/u-boot_def.lds b/board/mv_feroceon/config_dd/u-boot_def.lds new file mode 100644 index 0000000..8fb42ae --- /dev/null +++ b/board/mv_feroceon/config_dd/u-boot_def.lds @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x10000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_kw/.depend b/board/mv_feroceon/config_kw/.depend new file mode 100644 index 0000000..5fe4b78 --- /dev/null +++ b/board/mv_feroceon/config_kw/.depend @@ -0,0 +1,4447 @@ +jump.o: \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/USP/jump.S \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvSpec.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/uboot_oss/mvOsAsm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/common/mvCommon.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/common/mvTypes.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/USP/sdio/mvsdmmc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/mmc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/errno.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/uboot_oss/mvOs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/common/mvTypes.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/common/mvCommon.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/common/mvTypes.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvSpec.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/common/mvDeviceId.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/board/mv_feroceon/mv_kw/mvSysHwConfig.h diff --git a/board/mv_feroceon/config_kw/Makefile b/board/mv_feroceon/config_kw/Makefile new file mode 100644 index 0000000..8c1b38c --- /dev/null +++ b/board/mv_feroceon/config_kw/Makefile @@ -0,0 +1,83 @@ +include mvRules.mk + + +# Objects list + +COMMON_OBJS = $(COMMON_DIR)/mvCommon.o + +OSSERVICES_OBJS = $(OSSERVICES_DIR)/mvOs.o $(OSSERVICES_DIR)/mvOsSata.o + +BOARD_OBJS = $(BOARD_ENV_DIR)/mvBoardEnvLib.o $(BOARD_ENV_DIR)/mvBoardEnvSpec.o + +HAL_OBJS = $(HAL_FLASH_DIR)/mvFlash.o $(HAL_FLASH_DIR)/mvAmdFlash.o $(HAL_FLASH_DIR)/mvIntelFlash.o \ + $(HAL_FLASH_DIR)/mvFlashCom.o $(HAL_SPD_DIR)/mvSpd.o $(HAL_DRAM_DIR)/mvDramIf.o \ + $(HAL_SATA_CORE_DIR)/mvSata.o $(HAL_SATA_CORE_DIR)/mvStorageDev.o \ + $(HAL_SATA_CORE_DIR)/mvLog.o $(HAL_SFLASH_DIR)/mvSFlash.o \ + $(HAL_ETHPHY_DIR)/mvEthPhy.o $(HAL_RTC_DIR)/mvRtc.o \ + $(HAL_CNTMR_DIR)/mvCntmr.o $(HAL_TWSI_DIR)/mvTwsi.o \ + $(HAL_UART_DIR)/mvUart.o $(HAL_GPP_DIR)/mvGpp.o \ + $(HAL_SPI_DIR)/mvSpi.o $(HAL_SPI_DIR)/mvSpiCmnd.o $(HAL_USB_DIR)/mvUsb.o \ + $(HAL_XOR_DIR)/mvXor.o $(HAL_ETH_GBE_DIR)/mvEth.o $(HAL_PCIIF_DIR)/mvPciIf.o \ + $(HAL_ETH_GBE_DIR)/mvEthDebug.o $(HAL_PEX_DIR)/mvPex.o $(HAL_AUDIO_DIR)/mvAudio.o \ + $(HAL_TS_DIR)/mvTsu.o $(HAL_CESA_DIR)/mvMD5.o $(HAL_LCD_DIR)/mvLcd.o + +ifeq ($(findstring CONFIG_BUFFALO_PLATFORM,$(CPPFLAGS)),) +else +HAL_OBJS += $(HAL_DIR)/buffalo/BuffaloWol.o +endif + + +SOC_OBJS = $(SOC_DIR)/mv_cmd.o $(SOC_DIR)/mv_dram.o $(SOC_DIR)/mv_main.o $(SOC_DIR)/mv_service.o\ + $(SOC_ENV_DIR)/mvCtrlEnvLib.o \ + $(SOC_ENV_DIR)/mvCtrlEnvAddrDec.o $(SOC_SYS_DIR)/mvAhbToMbus.o \ + $(SOC_SYS_DIR)/mvCpuIf.o $(SOC_SYS_DIR)/mvSysXor.o $(SOC_SYS_DIR)/mvSysDram.o \ + $(SOC_SYS_DIR)/mvSysGbe.o $(SOC_SYS_DIR)/mvSysAudio.o $(SOC_SYS_DIR)/mvSysTs.o\ + $(SOC_SYS_DIR)/mvSysPex.o $(SOC_SYS_DIR)/mvSysSata.o $(SOC_SYS_DIR)/mvSysUsb.o \ + $(SOC_CPU_DIR)/mvCpu.o $(SOC_DEVICE_DIR)/mvDevice.o $(SOC_SYS_DIR)/mvSysLCD.o + +ifneq ($(MV_TINY_IMAGE), y) +SOC_OBJS += $(HAL_PCIIF_DIR)/pci_util/mvPciUtils.o +endif + +USP_OBJS = $(USP_DIR)/mv_flash.o $(USP_DIR)/mv_serial.o \ + $(USP_DIR)/mv_pageTable.o $(USP_DIR)/mv_rtc.o $(USP_DIR)/mv_mon_init.o \ + $(USP_DIR)/mv_pci.o $(USP_DIR)/mv_nand.o \ + $(USP_DIR)/mv_ide.o $(USP_DIR)/mv_egiga.o \ + $(USP_DIR)/mv_fs.o $(USP_DIR)/mv_loadnet.o $(USP_DIR)/mv_protectionUnit.o \ + $(USP_DIR)/mv_i2c.o $(USP_DIR)/mv_ext2_boot.o $(USP_ETH_SWITCH_DIR)/mvSwitch.o \ + $(USP_DIR)/sdio/mmc.o + +ifeq ($(NAND_BOOT), y) +USP_OBJS += $(USP_DIR)/nBootloader.o +endif + +SOBJS = $(USP_DIR)/jump.o \ + $(SOC_DIR)/platform.o \ + $(HAL_DRAM_DIR)/mvDramIfBasicInit.o \ + $(HAL_DRAM_DIR)/mvDramIfConfig.o \ + $(HAL_TWSI_DIR)/mvTwsiEeprom.o \ + $(SOC_SYS_DIR)/mvCpuIfInit.o + +ifeq ($(NAND_BOOT), y) +SOBJS += ../mv_kw/nBootstrap.o +endif + + +OBJS = $(COMMON_OBJS) $(OSSERVICES_OBJS) $(HAL_OBJS) $(SOC_OBJS) $(BOARD_OBJS) $(USP_OBJS) + +LIB = lib$(BOARD).a + +all: $(LIB) + +$(LIB): .depend $(SOBJS) $(OBJS) + $(AR) crv $@ $(SOBJS) $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) $(USB_OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### + diff --git a/board/mv_feroceon/config_kw/config.mk b/board/mv_feroceon/config_kw/config.mk new file mode 100644 index 0000000..cca0183 --- /dev/null +++ b/board/mv_feroceon/config_kw/config.mk @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00600000 +# + +TEXT_BASE = 0x00600000 diff --git a/board/mv_feroceon/config_kw/config_16mb.mk b/board/mv_feroceon/config_kw/config_16mb.mk new file mode 100644 index 0000000..9452ff9 --- /dev/null +++ b/board/mv_feroceon/config_kw/config_16mb.mk @@ -0,0 +1,4 @@ +# +# image should be loaded at 0x00c00000 +# +TEXT_BASE = 0x00c10000 diff --git a/board/mv_feroceon/config_kw/config_def.mk b/board/mv_feroceon/config_kw/config_def.mk new file mode 100644 index 0000000..cca0183 --- /dev/null +++ b/board/mv_feroceon/config_kw/config_def.mk @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x00600000 +# + +TEXT_BASE = 0x00600000 diff --git a/board/mv_feroceon/config_kw/config_nand.mk b/board/mv_feroceon/config_kw/config_nand.mk new file mode 100644 index 0000000..93c4799 --- /dev/null +++ b/board/mv_feroceon/config_kw/config_nand.mk @@ -0,0 +1,8 @@ + +BOOT_TEXT_BASE = 0x00020000 + +NAND_LDSCRIPT = ./board/$(BOARDDIR)/u-boot-nand.lds + +NAND_LDFLAGS += -Bdynamic -T $(NAND_LDSCRIPT) -Ttext $(BOOT_TEXT_BASE) $(PLATFORM_LDFLAGS) +NAND_OBJS = ./board/mv_feroceon/mv_kw/nBootstrap.o +NAND_OBJS += ./board/mv_feroceon/USP/nBootloader.o diff --git a/board/mv_feroceon/config_kw/config_prpmc.mk b/board/mv_feroceon/config_kw/config_prpmc.mk new file mode 100644 index 0000000..ac0295c --- /dev/null +++ b/board/mv_feroceon/config_kw/config_prpmc.mk @@ -0,0 +1,5 @@ +# +# image should be loaded at 0x02f00000 +# + +TEXT_BASE = 0x02f10000 diff --git a/board/mv_feroceon/config_kw/mvRules.mk b/board/mv_feroceon/config_kw/mvRules.mk new file mode 100644 index 0000000..bf364b5 --- /dev/null +++ b/board/mv_feroceon/config_kw/mvRules.mk @@ -0,0 +1,81 @@ +# This flags will be used only by the Marvell arch files compilation. +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk + + +# General definitions +CPU_ARCH = ARM +CHIP = kw +VENDOR = Marvell +ENDIAN = LE +LD_ENDIAN = -EL + +ifeq ($(BIG_ENDIAN),y) +ENDIAN = BE +LD_ENDIAN = -EB +endif + + +# Main directory structure +SRC_PATH = $(TOPDIR)/board/mv_feroceon +HAL_DIR = $(SRC_PATH)/mv_hal +COMMON_DIR = $(SRC_PATH)/common +USP_DIR = $(SRC_PATH)/USP +SOC_DIR = $(SRC_PATH)/mv_$(CHIP) +ORION_FAM_DIR = $(SOC_DIR)/$(CHIP)_family +SOC_ENV_DIR = $(ORION_FAM_DIR)/ctrlEnv +SOC_SYS_DIR = $(ORION_FAM_DIR)/ctrlEnv/sys +SOC_CPU_DIR = $(ORION_FAM_DIR)/cpu +SOC_DEVICE_DIR = $(ORION_FAM_DIR)/device +BOARD_ENV_DIR = $(ORION_FAM_DIR)/boardEnv +USP_ETH_SWITCH_DIR = $(USP_DIR)/ethSwitch + +# HAL components +HAL_DRAM_DIR = $(HAL_DIR)/ddr2 +HAL_SPD_DIR = $(HAL_DRAM_DIR)/spd +HAL_ETHPHY_DIR = $(HAL_DIR)/eth-phy +HAL_FLASH_DIR = $(HAL_DIR)/norflash +HAL_PCI_DIR = $(HAL_DIR)/pci +HAL_PCIIF_DIR = $(HAL_DIR)/pci-if +HAL_RTC_DIR = $(HAL_DIR)/rtc/integ_rtc +HAL_SFLASH_DIR = $(HAL_DIR)/sflash +HAL_SATA_CORE_DIR = $(HAL_DIR)/sata/CoreDriver/ +HAL_CNTMR_DIR = $(HAL_DIR)/cntmr +HAL_GPP_DIR = $(HAL_DIR)/gpp +HAL_IDMA_DIR = $(HAL_DIR)/idma +HAL_PEX_DIR = $(HAL_DIR)/pex +HAL_TWSI_DIR = $(HAL_DIR)/twsi +HAL_TWSI_ARCH_DIR = $(HAL_TWSI_DIR)/Arch$(CPU_ARCH) +HAL_ETH_DIR = $(HAL_DIR)/eth +HAL_ETH_GBE_DIR = $(HAL_ETH_DIR)/gbe +HAL_UART_DIR = $(HAL_DIR)/uart +HAL_XOR_DIR = $(HAL_DIR)/xor +HAL_LCD_DIR = $(HAL_DIR)/lcd +HAL_USB_DIR = $(HAL_DIR)/usb +HAL_SATA_DIR = $(HAL_DIR)/sata +HAL_MFLASH_DIR = $(HAL_DIR)/mflash +HAL_SPI_DIR = $(HAL_DIR)/spi +HAL_TS_DIR = $(HAL_DIR)/ts +HAL_AUDIO_DIR = $(HAL_DIR)/audio +HAL_CESA_DIR = $(HAL_DIR)/cesa + +# OS services +OSSERVICES_DIR = $(SRC_PATH)/uboot_oss + +# Internal definitions +MV_DEFINE = -DMV_UBOOT -DMV_CPU_$(ENDIAN) -DMV_$(CPU_ARCH) + +# Internal include path +HAL_PATH = -I$(HAL_DIR) -I$(HAL_SATA_CORE_DIR) +COMMON_PATH = -I$(COMMON_DIR) +OSSERVICES_PATH = -I$(OSSERVICES_DIR) +USP_PATH = -I$(USP_DIR) +SOC_PATH = -I$(ORION_FAM_DIR) -I$(SOC_DIR) -I$(SOC_ENV_DIR) -I$(SOC_SYS_DIR) -I$(SOC_CPU_DIR) -I$(SOC_DEVICE_DIR) +BOARD_PATH = -I$(BOARD_ENV_DIR) + +CFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + +AFLAGS += $(MV_DEFINE) $(OSSERVICES_PATH) $(HAL_PATH) $(COMMON_PATH) \ + $(USP_PATH) $(SOC_PATH) $(BOARD_PATH) $(SYS_PATH) + diff --git a/board/mv_feroceon/config_kw/u-boot-mvlsxh.lds b/board/mv_feroceon/config_kw/u-boot-mvlsxh.lds new file mode 100644 index 0000000..f8ccfd0 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-mvlsxh.lds @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x60000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_kw/u-boot-nand.lds b/board/mv_feroceon/config_kw/u-boot-nand.lds new file mode 100644 index 0000000..bd515d5 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-nand.lds @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : { *(.text) } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + __u_boot_cmd_end = .; + + . = ALIGN(4); + _bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_kw/u-boot-sec128k-tiny.lds b/board/mv_feroceon/config_kw/u-boot-sec128k-tiny.lds new file mode 100644 index 0000000..9df76fa --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-sec128k-tiny.lds @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x20000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_kw/u-boot-sec128k.lds b/board/mv_feroceon/config_kw/u-boot-sec128k.lds new file mode 100644 index 0000000..548b2a4 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-sec128k.lds @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_kw/u-boot-sec256k.lds b/board/mv_feroceon/config_kw/u-boot-sec256k.lds new file mode 100644 index 0000000..548b2a4 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-sec256k.lds @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_kw/u-boot-sec4k-header-tiny.lds b/board/mv_feroceon/config_kw/u-boot-sec4k-header-tiny.lds new file mode 100644 index 0000000..fc85653 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-sec4k-header-tiny.lds @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3ec00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x3ee00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_kw/u-boot-sec4k-tiny.lds b/board/mv_feroceon/config_kw/u-boot-sec4k-tiny.lds new file mode 100644 index 0000000..988fbd9 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-sec4k-tiny.lds @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x3c000; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_kw/u-boot-sec4k.lds b/board/mv_feroceon/config_kw/u-boot-sec4k.lds new file mode 100644 index 0000000..47712f8 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-sec4k.lds @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x70000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_kw/u-boot-sec64k-header-nand.lds b/board/mv_feroceon/config_kw/u-boot-sec64k-header-nand.lds new file mode 100644 index 0000000..f292c75 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-sec64k-header-nand.lds @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = _start + 0x7DC00; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/mv_feroceon/config_kw/u-boot-sec64k-header.lds b/board/mv_feroceon/config_kw/u-boot-sec64k-header.lds new file mode 100644 index 0000000..3685db3 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-sec64k-header.lds @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FE00; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + + . = _start + 0x7DE00; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/mv_feroceon/config_kw/u-boot-sec64k-tiny.lds b/board/mv_feroceon/config_kw/u-boot-sec64k-tiny.lds new file mode 100644 index 0000000..d3bece6 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-sec64k-tiny.lds @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start - 0x10000; + .dummy : { board/mv_feroceon/USP/jump.o (.dummy) } + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = _start + 0x30000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/mv_feroceon/config_kw/u-boot-sec64k.lds b/board/mv_feroceon/config_kw/u-boot-sec64k.lds new file mode 100644 index 0000000..f8ccfd0 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot-sec64k.lds @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x60000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_kw/u-boot.lds b/board/mv_feroceon/config_kw/u-boot.lds new file mode 100644 index 0000000..f8ccfd0 --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot.lds @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = _start; + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .got : { *(.got) } + + + . = _start + 0x60000; + .reset_vector_sect : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = _start + 0x6FFF0; + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/config_kw/u-boot_16mb.lds b/board/mv_feroceon/config_kw/u-boot_16mb.lds new file mode 100644 index 0000000..5ce504e --- /dev/null +++ b/board/mv_feroceon/config_kw/u-boot_16mb.lds @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .dummy 0x00c00000 : { board/mv_feroceon/USP/jump.o (.dummy) } + . = 0x0c10000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + .reset_vector_sect 0x00c70000 : { board/mv_feroceon/USP/jump.o (.reset_vector_sect) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + +} diff --git a/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvLib.c b/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvLib.c new file mode 100644 index 0000000..4148ca9 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvLib.c @@ -0,0 +1,1760 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "boardEnv/mvBoardEnvLib.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cntmr/mvCntmr.h" +#include "device/mvDevice.h" +#include "gpp/mvGpp.h" +#include "twsi/mvTwsi.h" +#include "cpu/mvCpu.h" +#include "device/mvDeviceRegs.h" +#include "eth-phy/mvEthPhy.h" +/* defines */ +#ifdef DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* defines */ +#define REF_TIMER 0 /* reference timer number */ + +/* local */ +MV_BOOL mvBoardIsBootFromNand(MV_VOID); +static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +/* Locals */ +MV_U32 refClkDevInit(MV_VOID); +MV_VOID refClkDevRelease(MV_U32 prevState); +MV_U32 refClkDevBitRateGet(MV_VOID); +MV_VOID refClkDevStart(MV_U32 refClkDevBits); +MV_U32 sysClkRate = -1; +MV_U32 tClkRate = -1; +MV_U32 gBoardId = 0; + + +MV_DEV_CS_INFO dbBoardCsInfoNor8Boot[] = + /*{deviceCS, params, devType, devWidth}*/ + { + {DEVICE_CS0, N_A, BOARD_DEV_NOR_FLASH, 32}, + {DEVICE_CS1, N_A, BOARD_DEV_SEVEN_SEG, 4}, + {DEVICE_CS2, N_A, BOARD_DEV_NAND_FLASH, 8}, + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 8}, +#if !defined (MV78XX0_Z0) + {SPI_CS, N_A, BOARD_DEV_SPI_FLASH, 8}, +#endif + {MAX_TARGETS, 0, 0, 0} + }; + +MV_DEV_CS_INFO dbBoardCsInfoNor32Boot[] = + /*{deviceCS, params, devType, devWidth}*/ + { + /* {DEVICE_CS0, N_A, BOARD_DEV_NOR_FLASH, 8},*/ + {DEVICE_CS1, N_A, BOARD_DEV_SEVEN_SEG, 4}, + {DEVICE_CS2, N_A, BOARD_DEV_NAND_FLASH, 8}, + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 32}, +#if !defined (MV78XX0_Z0) + {SPI_CS, N_A, BOARD_DEV_SPI_FLASH, 8}, +#endif + {MAX_TARGETS, 0, 0, 0} + }; + + +MV_DEV_CS_INFO dbBoardCsBootFromSpiInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + { + {DEVICE_CS0, N_A, BOARD_DEV_NOR_FLASH, 32}, + {DEVICE_CS1, N_A, BOARD_DEV_SEVEN_SEG, 4}, + {DEVICE_CS2, N_A, BOARD_DEV_NAND_FLASH, 8}, +#if !defined (MV78XX0_Z0) + {SPI_CS, N_A, BOARD_DEV_SPI_FLASH, 8}, +#endif + {MAX_TARGETS, 0, 0, 0} + }; + +MV_DEV_CS_INFO dbBoard632XCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + { + {DEV_BOOCS, N_A, BOARD_DEV_NAND_FLASH, 8}, +#if !defined (MV78XX0_Z0) + {SPI_CS, N_A, BOARD_DEV_SPI_FLASH, 8}, +#endif + {MAX_TARGETS, 0, 0, 0} + }; + + +MV_DEV_CS_INFO db78200BoardCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + { + {DEVICE_CS1, N_A, BOARD_DEV_SEVEN_SEG, 4}, + {DEVICE_CS3, N_A, BOARD_DEV_NAND_FLASH, 8}, + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 16}, +#if !defined (MV78XX0_Z0) + {SPI_CS, N_A, BOARD_DEV_SPI_FLASH, 8}, +#endif + {MAX_TARGETS, 0, 0, 0} + }; + + +MV_DEV_CS_INFO dbBoardCsInfoBootFromNand[] = + /*{deviceCS, params, devType, devWidth}*/ + { + {DEV_BOOCS, N_A, BOARD_DEV_NAND_FLASH, 8}, +#if !defined (MV78XX0_Z0) + {SPI_CS, N_A, BOARD_DEV_SPI_FLASH, 8}, +#endif + {MAX_TARGETS, 0, 0, 0} + }; + +MV_DEV_CS_INFO rdPcacBoardCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + { + {DEV_BOOCS, N_A, BOARD_DEV_NOR_FLASH, 8}, +#if !defined (MV78XX0_Z0) + {SPI_CS, N_A, BOARD_DEV_SPI_FLASH, 8}, +#endif + {MAX_TARGETS, 0, 0, 0} + }; + +MV_DEV_CS_INFO rdAmcBoardCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + { + {DEV_BOOCS, N_A, BOARD_DEV_NAND_FLASH, 8}, +#if !defined (MV78XX0_Z0) + {SPI_CS, N_A, BOARD_DEV_SPI_FLASH, 8}, +#endif + {MAX_TARGETS, 0, 0, 0} + }; + +static MV_DEV_CS_INFO* boardGetCsArray(MV_VOID) +{ + MV_U32 boardId = mvBoardIdGet(); + if (DB_78200_ID == boardId) + { + if (MV_TRUE == mvBoardIsBootFromNand()) + return dbBoardCsInfoBootFromNand; + else + return db78200BoardCsInfo; + } + else + { + if (RD_78XX0_PCAC_ID == boardId) + return rdPcacBoardCsInfo; + else if (RD_78XX0_AMC_ID == boardId) + return rdAmcBoardCsInfo; + else if (DB_632X_ID == boardId) + return dbBoard632XCsInfo; + else if (MV_TRUE == mvBoardIsBootFromNand()) + return dbBoardCsInfoBootFromNand; + else if (MV_TRUE == mvBoardIsBootFromSpi()) + return dbBoardCsBootFromSpiInfo; + else if (MV_TRUE == mvBoardIsBootFromNor32()) + return dbBoardCsInfoNor32Boot; + else + return dbBoardCsInfoNor8Boot; + } + +} + +/******************************************************************************* +* mvBoardEnvInit - Init board +* +* DESCRIPTION: +* In this function the board environment take care of device bank +* initialization. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardEnvInit(MV_VOID) +{ + MV_U32 devNum, gpioLedMask; + MV_U32 devBankParam = -1; + MV_U32 devBankParamWr = -1; + MV_U32 boardId = mvBoardIdGet(); + + if (UNKNOWN_BOARD_ID == boardId) + { + mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); + return; + } + + for (devNum = DEV_CS0; devNum <= BOOT_CS; devNum++) + { + switch(devNum) + { +#if !defined(MV632X) + case (DEV_CS0): + if (DB_78200_ID == boardId) + devBankParam = DEVICE_78200_CS0_PARAM; + else + devBankParam = DEVICE_CS0_PARAM; + devBankParamWr = DEVICE_CS0_PARAM_WR; + break; + case (DEV_CS1): + devBankParam = DEVICE_CS1_PARAM; + devBankParamWr = DEVICE_CS1_PARAM_WR; + break; + case (DEV_CS2): + if (DB_78200_ID == boardId) + devBankParam = DEVICE_78200_CS2_PARAM; + else + devBankParam = DEVICE_CS2_PARAM; + devBankParamWr = DEVICE_CS2_PARAM_WR; + break; + case (DEV_CS3): + if (DB_78200_ID == boardId) + devBankParam = DEVICE_78200_CS3_PARAM; + else + devBankParam = DEVICE_CS3_PARAM; + devBankParamWr = DEVICE_CS3_PARAM_WR; + break; +#endif + case (BOOT_CS): + if (DB_78200_ID == boardId) + devBankParam = BOOTDEV_78200_CS_PARAM; + else + devBankParam = MV_REG_READ(DEV_BANK_PARAM_REG(devNum)); + devBankParam &= DBP_DEVWIDTH_MASK; + devBankParam |= BOOTDEV_CS_PARAM; + devBankParamWr = DEVICE_CS3_PARAM_WR; + break; + default: + devBankParam = -1; + devBankParamWr = -1; + break; + } + + if(devBankParam != -1) + MV_REG_WRITE(DEV_BANK_PARAM_REG(devNum), devBankParam); + if(devBankParamWr != -1) + MV_REG_WRITE(DEV_BANK_PARAM_REG_WR(devNum), devBankParamWr); + + devBankParam = -1; + devBankParamWr = -1; + } + + /* Check if boot from NAND - do nothing */ + if (!mvBoardIsBootFromNand()) + { + /* Assign NAND CS and care in control reg */ + if (DB_78200_ID == boardId) + mvDevNandDevCsSet(MV_NAND_78200_CS, MV_NAND_CARE); + else if (DB_632X_ID == boardId) + mvDevNandDevCsSet(MV_NAND_632X_CS, MV_NAND_CARE); + else if (RD_78XX0_AMC_ID == boardId) + mvDevNandDevCsSet(MV_NAND_AMC_CS, MV_NAND_CARE); + else + mvDevNandDevCsSet(MV_NAND_CS, MV_NAND_CARE); + } + + /* Set GPP value before set OE to prevent reset */ + switch (boardId) { + case DB_78XX0_ID: + MV_REG_WRITE(GPP_DATA_OUT_SET_REG, (1 << DB_78XX0_SW_RESET)); + break; + case DB_78200_ID: + MV_REG_WRITE(GPP_DATA_OUT_CLEAR_REG, (1 << DB_78200_SW_RESET)); + break; + case RD_78XX0_AMC_ID: + MV_REG_WRITE(GPP_DATA_OUT_CLEAR_REG, (1 << RD_AMC_SW_RESET)); + break; + case RD_78XX0_MASA_ID: + MV_REG_WRITE(GPP_DATA_OUT_SET_REG, (1 << RD_MASA_DEBUG_LED_GPP_PIN(1))); + break; + case RD_78XX0_H3C_ID: + MV_REG_WRITE(GPP_DATA_OUT_SET_REG, (1 << RD_H3C_SW_RESET_SELECT)); + break; + case DB_632X_ID: + MV_REG_WRITE(GPP_DATA_OUT_SET_REG, (1 << DB_6323_SW_RESET)); + /* Change SATA active led polarity for DB-6323 */ + MV_REG_BIT_SET(0xa002c, BIT3); + break; + default: + break; + } + /* Debug Led operates via GPP. Initialize GPP */ + gpioLedMask = mvBoardDbgLedGpioMaskGet(); + switch(boardId) { + case DB_78XX0_ID: + gpioLedMask |= 1 << DB_78XX0_SW_RESET; +#ifdef MV_INCLUDE_MODEM_ON_TTYS1 + gpioLedMask |= 1 << DB_78XX0_SERIAL_DTR; /* set DTR as output*/ +#endif + break; + case DB_78200_ID: + gpioLedMask |= DB_78200_GPIO_OUTPUT_EN; + break; + case RD_78XX0_AMC_ID: + gpioLedMask |= RD_AMC_GPIO_OUTPUT_EN; + break; + case RD_78XX0_MASA_ID: + gpioLedMask |= RD_MASA_GPIO_OUTPUT_EN; /* set DTR as output*/ + break; + case RD_78XX0_H3C_ID: + gpioLedMask |= RD_H3C_GPIO_OUTPUT_EN; /* set DTR as output*/ + break; + case DB_632X_ID: + gpioLedMask |= DB_6323_GPIO_OUTPUT_EN; + break; + default: + break; + } + + /* Set the GPP interrupt pins to output. */ + mvGppTypeSet (0, gpioLedMask, (gpioLedMask & MV_GPP_OUT)); +} + +/******************************************************************************* +* mvBoardIsBootFromNand - +* +* DESCRIPTION: +* This routine returns MV_TRUE if the board is configure to boot from nand +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - boot from nand. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsBootFromNand(MV_VOID) +{ + /* Check if boot from NAND - do nothing */ + if (((MV_REG_READ(CPU_RESET_SAMPLE_L_REG) & MSAR_BOOTDEV_MASK) == MSAR_BOOTDEV_DCE_NAND) || + ((MV_REG_READ(CPU_RESET_SAMPLE_L_REG) & MSAR_BOOTDEV_MASK) == MSAR_BOOTDEV_CE_NAND)) + { + return MV_TRUE; + } + return MV_FALSE; +} +/******************************************************************************* +* mvBoardIsBootFromSpi - +* +* DESCRIPTION: +* This routine returns MV_TRUE if the board is configure to boot from SPI flash +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - boot from SPI. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsBootFromSpi(MV_VOID) +{ + /* Check if boot from NAND - do nothing */ + if ((MV_REG_READ(CPU_RESET_SAMPLE_L_REG) & MSAR_BOOTDEV_MASK) == MSAR_BOOTDEV_SPI) + { + return MV_TRUE; + } + return MV_FALSE; +} +/******************************************************************************* +* mvBoardIsBootFromNor - +* +* DESCRIPTION: +* This routine returns MV_TRUE if the board is configure to boot from NOR flash +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - boot from Nor. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsBootFromNor(MV_VOID) +{ + /* Check if boot from NAND - do nothing */ + if ((MV_REG_READ(CPU_RESET_SAMPLE_L_REG) & MSAR_BOOTDEV_MASK) == MSAR_BOOTDEV_FLASH) + { + return MV_TRUE; + } + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardIsBootFromNor32 - +* +* DESCRIPTION: +* This routine returns MV_TRUE if the board is configure to boot from NOR 32-bit +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - boot from Nor. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsBootFromNor32(MV_VOID) +{ + /* Check if boot from NAND - do nothing */ + if ((MV_REG_READ(CPU_RESET_SAMPLE_L_REG) & MSAR_BOOTDEV_WIDTH_MASK) + == MSAR_BOOTDEV_WIDTH_32BIT) + { + return MV_TRUE; + } + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardNameGet - Get Board name +* +* DESCRIPTION: +* This function returns a string describing the board model and revision. +* String is extracted from board I2C EEPROM. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvBoardNameGet(char *pNameBuff) +{ + char ctrlStr[132] = ""; + MV_U32 boardId = mvBoardIdGet(); + mvCtrlNameGet(ctrlStr); + + if (RD_78XX0_H3C_ID == boardId) + { + sprintf (pNameBuff, "RD-"); + strcat (pNameBuff, ctrlStr); + strcat (pNameBuff, "-H3C"); + } + else + if (DB_78XX0_ID == boardId || + DB_78200_ID == boardId || + DB_632X_ID == boardId) + { + sprintf (pNameBuff, "DB-"); + strcat (pNameBuff, ctrlStr); + strcat (pNameBuff, "-A-BP"); + } + else + if (RD_78XX0_AMC_ID == boardId) + { + sprintf (pNameBuff, "DB-"); + strcat (pNameBuff, ctrlStr); + strcat (pNameBuff, "-A-AMC"); + } + else + if (RD_78XX0_MASA_ID == boardId) + { + sprintf (pNameBuff, "RD-"); + strcat (pNameBuff, ctrlStr); + strcat (pNameBuff, "-MASA"); + } + else + if (RD_78XX0_PCAC_ID == boardId) + { + sprintf (pNameBuff, "RD-"); + strcat (pNameBuff, ctrlStr); + strcat (pNameBuff, "-PCAC"); + } + else + { + sprintf (pNameBuff, "Board unknown.\n"); + return MV_ERROR; + } + + return MV_OK; +} + +/******************************************************************************* +* mvBoardIsPortInSgmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE +* For all other options. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in SGMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) +{ + MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; + + if (ethPortNum > BOARD_ETH_END_PORT_NUM) + { + mvOsPrintf ("mvBoardIsPortInSgmii: Invalid portNo=%d.\n", ethPortNum); + return MV_FALSE; + } + return ethPortSgmiiSupport[ethPortNum - BOARD_ETH_START_PORT_NUM]; +} + +/******************************************************************************* +* mvBoardPhyAddrGet - Get the phy address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, '-1' if the port number is wrong. +* +*******************************************************************************/ +MV_U32 mvBoardPhyAddrGet(MV_U32 ethPortNum) +{ + MV_U32 ethPortPhyAddr[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_PHY_ADDR; + + if(ethPortNum > BOARD_ETH_END_PORT_NUM) + { + mvOsPrintf ("mvBoardPhyAddrGet: Invalid portNo=%d.\n", ethPortNum); + return MV_ERROR; + } + + return ethPortPhyAddr[ethPortNum - BOARD_ETH_START_PORT_NUM]; +} + + +/******************************************************************************* +* mvBoardMacSpeedGet - Get the Mac speed +* +* DESCRIPTION: +* This routine returns the Mac speed if pre define of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BOARD_MAC_SPEED, -1 the port number is wrong. +* +*******************************************************************************/ +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) +{ + MV_32 boardId = mvBoardIdGet(); + if (boardId == RD_78XX0_H3C_ID) + /* RD-H3C 1145 works in RGMII to SGMII mode which disable speed AN, + force speed to 1000*/ + return BOARD_MAC_SPEED_1000M; + + if ((boardId == RD_78XX0_AMC_ID) && (ethPortNum == 3)) + /* RD-AMC 1145 port 3 works in RGMII to SGMII mode which disable speed AN, + force speed to 100 */ + return BOARD_MAC_SPEED_100M; + + return BOARD_MAC_SPEED_AUTO; +} +/******************************************************************************* +* mvBoardSpecInitGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: Return MV_TRUE and parameters in case board need specific phy init, +* otherwise return MV_FALSE. +* +* +*******************************************************************************/ + +MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) +{ + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardTclkGet - Get the board Tclk (Controller clock) +* +* DESCRIPTION: +* This routine extract the controller T clock. +* +* INPUT: +* None. +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_32 mvBoardTclkGet(MV_VOID) +{ + MV_32 tmpTClkRate=0; + + if (-1 == tClkRate) + { + tmpTClkRate = MV_REG_READ(CPU_RESET_SAMPLE_H_REG); + /* Internal PLL */ + if ((tmpTClkRate & MSAR_TCLCK_MODE_MASK) == MSAR_TCLCK_MODE_PLL) + { + switch(tmpTClkRate & MSAR_TCLCK_MASK) + { + case(MSAR_TCLCK_167): + tmpTClkRate = MV_BOARD_TCLK_166MHZ; + break; + case(MSAR_TCLCK_200): + tmpTClkRate = MV_BOARD_TCLK_200MHZ; + break; + default: + tmpTClkRate = MV_BOARD_TCLK_200MHZ; + break; + } + } + else + /* External PLL */ + { + switch(tmpTClkRate & MSAR_TCLCK_DES_MASK) + { + case(MSAR_TCLCK_DES_167): + tmpTClkRate = MV_BOARD_TCLK_166MHZ; + break; + case(MSAR_TCLCK_DES_200): + tmpTClkRate = MV_BOARD_TCLK_200MHZ; + break; + default: + tmpTClkRate = MV_BOARD_TCLK_200MHZ; + break; + } + } + + tClkRate = tmpTClkRate ; + } + else + { + tmpTClkRate = tClkRate; + } + + + return tmpTClkRate; +} + +/******************************************************************************* +* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) +* +* DESCRIPTION: +* This routine extract the CPU bus clock. +* Note: In the MPC745x, DEC is decremented and the time base +* increments at 1/4 of the system bus clock frequancy. +* Note: In order to avoid interference, make sure task context switch +* and interrupts will not occure during this function operation +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_32 mvBoardSysClkGet(MV_VOID) +{ + MV_32 tmpSysClkRate=0; + + if (-1 == sysClkRate) + { + tmpSysClkRate = MV_REG_READ(CPU_RESET_SAMPLE_L_REG); + switch(tmpSysClkRate & MSAR_SYSCLCK_MASK) + { + case(MSAR_SYSCLCK_200): + tmpSysClkRate = MV_BOARD_SYSCLK_200MHZ; + break; + case(MSAR_SYSCLCK_267): + tmpSysClkRate = MV_BOARD_SYSCLK_267MHZ; + break; + case(MSAR_SYSCLCK_333): + tmpSysClkRate = MV_BOARD_SYSCLK_333MHZ; + break; + case(MSAR_SYSCLCK_400): + tmpSysClkRate = MV_BOARD_SYSCLK_400MHZ; + break; + case(MSAR_SYSCLCK_250): + tmpSysClkRate = MV_BOARD_SYSCLK_250MHZ; + break; + case(MSAR_SYSCLCK_300): + tmpSysClkRate = MV_BOARD_SYSCLK_300MHZ; + break; + default: + tmpSysClkRate = MV_BOARD_SYSCLK_267MHZ; + break; + } + + sysClkRate = tmpSysClkRate; + } + else + { + tmpSysClkRate = sysClkRate; + } + + return tmpSysClkRate; +} + +/******************************************************************************* +* mvBoardDebugLed - Set the board debug LEDs +* +* DESCRIPTION: +* This function sets the board debug LEDs as the input number in hex, +* e.g - if state == 3 -->> debug leds 0 and 1 are turned on +* +* INPUT: +* hexNum - Number to be displied in hex by LEDs. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardDebugLed(MV_U32 binNum) +{ + int ledNum; + MV_32 boardId = mvBoardIdGet(); + + /* Binary number limited by the number of LEDs */ + binNum %= (1 << MV_BOARD_LED_NUM); + + for(ledNum = 0 ; ledNum < MV_BOARD_LED_NUM ; ledNum++) + { + if(binNum & (1 << ledNum)) /* turn led on */ + { + if (DB_78XX0_ID == boardId || DB_632X_ID == boardId) + mvGppValueSet( 0, + (1 << DB_78XX0_LED_GPP_PIN(ledNum)), /* mask */ + (1 << DB_78XX0_LED_GPP_PIN(ledNum))); /* value */ + else if (RD_78XX0_AMC_ID == boardId) + mvGppValueSet( 0, + (1 << RD_AMC_LED_GPP_PIN(ledNum)), /* mask */ + (1 << RD_AMC_LED_GPP_PIN(ledNum))); /* value */ + } + else /* turn led off */ + { + if (DB_78XX0_ID == boardId || DB_632X_ID == boardId) + mvGppValueSet( 0, + (1 << DB_78XX0_LED_GPP_PIN(ledNum)), /* mask */ + ~(1 << DB_78XX0_LED_GPP_PIN(ledNum))); /* value */ + if (RD_78XX0_AMC_ID == boardId) + mvGppValueSet( 0, + (1 << RD_AMC_LED_GPP_PIN(ledNum)), /* mask */ + ~(1 << RD_AMC_LED_GPP_PIN(ledNum))); /* value */ + } + } +} + + +/******************************************************************************* +* mvBoardDebug7Seg - Set the board debug 7Seg +* +* DESCRIPTION: +* +* INPUT: +* hexNum - Number to be displied in hex by 7Seg. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardDebug7Seg(MV_U32 hexNum) +{ + MV_U32 dummy, address; + + MV_32 boardId = mvBoardIdGet(); + + if (DB_632X_ID == boardId) + { + MV_REG_WRITE(GPP_DATA_OUT_REG(0), (MV_REG_READ(GPP_DATA_OUT_REG(0))& ~(0xf << 17)) | (hexNum << 17)); + } + else if ((DB_78XX0_ID == boardId) || (DB_78200_ID == boardId)) +#if !defined (MV78XX0_Z0) + MV_MEMIO8_WRITE(MV_BOARD_7SEG_BASE, hexNum); +#else + { + + address = MV_BOARD_7SEG_BASE + (hexNum << 4); + dummy = MV_MEMIO32_READ(CPU_MEMIO_UNCACHED_ADDR(address)); + } +#endif + else + { + /* The 7Seg on the device bus uses the address to set the sement */ + if (mvBoardIdGet() == RD_78XX0_H3C_ID) { + dummy = (hexNum % 4); + MV_MEMIO8_WRITE(CPU_MEMIO_UNCACHED_ADDR(MV_BOARD_7SEG_BASE), dummy); + } +#if !defined (MV78XX0_Z0) + else { + address = MV_BOARD_7SEG_BASE + (hexNum << 4); + dummy = MV_MEMIO32_READ(CPU_MEMIO_UNCACHED_ADDR(address)); + } +#endif + } +} +/******************************************************************************* +* mvBoardReset - mvBoardReset +* +* DESCRIPTION: +* Reset the board +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvBoardReset(MV_VOID) +{ + MV_32 boardId = mvBoardIdGet(); + if ((boardId == DB_78XX0_ID) || + (boardId == RD_78XX0_MASA_ID) || + (boardId == DB_632X_ID) || + (boardId == RD_78XX0_H3C_ID)) + { + MV_REG_WRITE(CPU_RESET_OUT_MASK_REG, (CPU_SOFT_RESET_OUT_MASK)); + MV_REG_WRITE(CPU_SOFT_RESET_OUT_REG, (CPU_SOFT_RESET_OUT)); + while(1); + } + + if (boardId == DB_78200_ID) + { + MV_REG_WRITE(GPP_DATA_OUT_REG(0), (1 << DB_78200_SW_RESET)); + while(1); + } + + if (boardId == RD_78XX0_AMC_ID) + { + MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), (1 << RD_AMC_SW_RESET )); + MV_REG_BIT_RESET(GPP_DATA_OUT_EN_REG(0), (1 << RD_AMC_SW_RESET )); + while(1); + } +} + +/******************************************************************************* +* mvBoardUSBVbusGpioPinGet - Get board GPP pin number connected to USB VBUS +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusGpioPinGet(int devId) +{ + MV_U32 boardID; + + boardID = mvBoardIdGet(); + + if (boardID == DB_78XX0_ID || + boardID == DB_78200_ID || + boardID == DB_632X_ID) + { + return DB_78XX0_USB_VBUS_PIN(devId); + } + + if (boardID == RD_78XX0_AMC_ID) + { + return RD_AMC_USB_VBUS_PIN(devId); + } + + if (boardID == RD_78XX0_H3C_ID) + { + return RD_H3C_USB_VBUS_PIN(devId); + } + + return MV_ERROR; +} + +/******************************************************************************* +* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusEnGpioPinGet(int devId) +{ + return N_A; +} +/******************************************************************************* +* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins +* +* DESCRIPTION: +* This function returns a 32-bit mask of GPP pins that connected to +* interrupt generating sources on board. +* For example if UART channel A is hardwired to GPP pin 8 and +* UART channel B is hardwired to GPP pin 4 the fuinction will return +* the value 0x000000110 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* See description. The function return -1 if board is not identified. +* +*******************************************************************************/ +MV_32 mvBoardGpioIntMaskGet(MV_VOID) +{ + MV_U32 boardID; + + boardID = mvBoardIdGet(); + + if (boardID == RD_78XX0_MASA_ID) + { + return RD_78XX0_MASA_INT_MASK; + } + + return MV_ERROR; /* Error */ +} +/******************************************************************************* +* mvBoardMppGet - Get board dependent MPP register value +* +* DESCRIPTION: +* MPP settings are derived from board design. +* MPP group consist of 8 MPPs. An MPP group represent MPP +* control register. +* This function retrieves board dependend MPP register value. +* +* INPUT: +* mppGroupNum - MPP group number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit value describing MPP control register value. +* +*******************************************************************************/ +MV_U32 mvBoardMppGet(MV_U32 mppGroupNum) +{ + MV_U32 boardID; + + boardID = mvBoardIdGet(); + + /* This id DB-MV78100-BP */ + if (DB_78XX0_ID == boardID) + { + switch(mppGroupNum) + { + case (0): + return DB_78XX0_MPP0_7; + case (1): + return DB_78XX0_MPP8_15; + case (2): + if (mvBoardIsBootFromNand()) + return DB_78XX0_MPP16_23_NAND; + else + return DB_78XX0_MPP16_23; + case (3): + return DB_78XX0_MPP24_31; + default: + return 0; + } + } + /* This id DB-MV78200-BP */ + else if (DB_78200_ID == boardID) + { + switch(mppGroupNum) + { + case (0): + return DB_78200_MPP0_7; + case (1): + return DB_78200_MPP8_15; + case (2): + return DB_78200_MPP16_23; + case (3): + return DB_78200_MPP24_31; + case (4): + return DB_78200_MPP32_39; + default: + return 0; + } + } + /* This id DB-MV88F632X-BP */ + else if (DB_632X_ID == boardID) + { + switch(mppGroupNum) + { + case (0): + return DB_632X_MPP0_7; + case (1): + return DB_632X_MPP8_15; + case (2): + return DB_632X_MPP16_23; + case (3): + return DB_632X_MPP32_39; + case (4): + return DB_632X_MPP40_47; + case (5): + return DB_632X_MPP24_31; + default: + return 0; + } + } + else if(RD_78XX0_AMC_ID == boardID) + { + switch(mppGroupNum) + { + case (0): + return RD_AMC_MPP0_7; + case (1): + return RD_AMC_MPP8_15; + case (2): + return RD_AMC_MPP16_23; + case (3): + return RD_AMC_MPP24_31; + case (4): + return RD_AMC_MPP32_39; + case (5): + return RD_AMC_MPP40_47; + case (6): + return RD_AMC_MPP48_49; + default: + DB(mvOsPrintf("mvBoardMppGet: ERR. Unsupported MPP group %d\n", + mppGroupNum)); + } + } + else if(RD_78XX0_H3C_ID == boardID) + { + switch(mppGroupNum) + { + case (0): + return RD_H3C_MPP0_7; + case (1): + return RD_H3C_MPP8_15; + case (2): + return RD_H3C_MPP16_23; + case (3): + return RD_H3C_MPP24_31; + default: + DB(mvOsPrintf("mvBoardMppGet: ERR. Unsupported MPP group %d\n", + mppGroupNum)); + } + } + else if(RD_78XX0_MASA_ID == boardID) + { + switch(mppGroupNum) + { + case (0): + return RD_MASA_MPP0_7; + case (1): + return RD_MASA_MPP8_15; + case (2): + return RD_MASA_MPP16_23; + case (3): + return RD_MASA_MPP24_31; + default: + DB(mvOsPrintf("mvBoardMppGet: ERR. Unsupported MPP group %d\n", + mppGroupNum)); + } + } + else + { + DB(mvOsPrintf("mvBoardMppGet: ERR. Board not spported\n")); + } + + return 0; +} +/* Board devices API managments */ + +/******************************************************************************* +* mvBoardGetDeviceNumber - Get number of device of some type on the board +* +* DESCRIPTION: +* +* INPUT: +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* number of those devices else the function returns 0 +* +* +*******************************************************************************/ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) +{ + MV_32 i, count = 0; + MV_DEV_CS_INFO* devEntry = boardGetCsArray(); + + for (i = 0; devEntry[i].deviceCS != MAX_TARGETS; i++) + { + if (devClass == devEntry[i].devClass) + count++; + } + return count; +} + +/******************************************************************************* +* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Base address else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_U32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return mvCpuIfTargetWinBaseLowGet(devEntry->deviceCS); + } + return 0xFFFFFFFF; +} + + +/******************************************************************************* +* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Bus width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_U32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + MV_DEVICE dev; + MV_U32 ret; + /*Convert target to device*/ + switch(devEntry->deviceCS) + { + case DEVICE_CS0: + dev = DEV_CS0; + break; + case DEVICE_CS1: + dev = DEV_CS1; + break; + case DEVICE_CS2: + dev = DEV_CS2; + break; + case DEVICE_CS3: + dev = DEV_CS3; + break; + case DEV_BOOCS: + dev = BOOT_CS; + break; + default: + return 0xFFFFFFFF; + } + ret = mvDevWidthGet(dev); + return ret; + } + + return 0xFFFFFFFF; +} + + +/******************************************************************************* +* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* window size else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_U32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return mvCpuIfTargetWinSizeGet(devEntry->deviceCS); + } + return 0xFFFFFFFF; +} + + + +/******************************************************************************* +* mvBoardRtcTwsiAddrTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardRtcTwsiAddrTypeGet() +{ + return MV_BOARD_RTC_I2C_ADDR_TYPE; +} + +/******************************************************************************* +* mvBoardRtcTwsiAddrGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardRtcTwsiAddrGet() +{ + return MV_BOARD_RTC_I2C_ADDR; +} + + +/******************************************************************************* +* boardGetDevEntry - returns the entry pointer of a device on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +* +*******************************************************************************/ +static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex = 0, i; + MV_DEV_CS_INFO* devEntry = boardGetCsArray(); + + for (i = 0; devEntry[i].deviceCS != MAX_TARGETS; i++) + { + if (devEntry[i].devClass == devClass) + { + if (foundIndex == devNum) + { + return &devEntry[i]; + } + foundIndex++; + } + } + + /* device not found */ + return NULL; +} + + +/******************************************************************************* +* mvBoardGetDevCS - +* +* DESCRIPTION: +* Return device CS target +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None +* +*******************************************************************************/ +MV_TARGET mvBoardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return devEntry->deviceCS; + } + return MAX_TARGETS; +} + + + +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + return devEntry->devWidth; + + return 0xFFFFFFFF; + +} + + +MV_U32 mvBoardFlashParamGet(MV_VOID) +{ + MV_U32 boardId = mvBoardIdGet(); + if (RD_78XX0_AMC_ID == boardId || + RD_78XX0_MASA_ID == boardId || + RD_78XX0_H3C_ID == boardId || + DB_632X_ID == boardId) + return 0; + else + return MV_BOARD_FLASH_PARAM_VAL; +} + +MV_U32 mvBoardGetMaxUsbIf(MV_VOID) +{ + MV_U32 boardId = mvBoardIdGet(); + if (RD_78XX0_AMC_ID == boardId || + RD_78XX0_H3C_ID == boardId) + return 1; + else + return 3; +} + + +/*********************************************************** +* Init the PHY or Switch of the board * + ***********************************************************/ +MV_VOID mvBoardEgigaPhySwitchInit(void) +{ + MV_U16 port; + MV_U32 boardID = mvBoardIdGet(); + + + /* First init the SGMII to copper on the test board */ + if (boardID == RD_78XX0_H3C_ID) + for (port = BOARD_ETH_START_PORT_NUM;port <= BOARD_ETH_END_PORT_NUM; port++) + { + mvEthSgmiiToCopperPhyBasicInit(port); + mvEth1145PhyBasicInit(port); + } + + /* This id RD-78XX0-AMC */ + if (boardID == RD_78XX0_AMC_ID) + for (port = BOARD_ETH_START_PORT_NUM;port <= BOARD_ETH_END_PORT_NUM; port++) + { + mvEth1145PhyBasicInit(port); + } + + /* This id DB-78XX0-BP */ + if ((boardID == DB_78XX0_ID) || (boardID == RD_78XX0_MASA_ID) || (boardID == DB_632X_ID)) + for (port = BOARD_ETH_START_PORT_NUM;port <= BOARD_ETH_END_PORT_NUM; port++) + mvEth1121PhyBasicInit(port); + + /* This id DB-78200-BP */ + if (boardID == DB_78200_ID) + for (port = BOARD_ETH_START_PORT_NUM;port <= BOARD_ETH_END_PORT_NUM; port++) + { + if ((port == 0) || (port == 1)) + mvEth1121PhyBasicInit(port); + else + mvEthE1116PhyBasicInit(port); + } + + /* This id RD_MV78XX0_PCAC */ + if (boardID == RD_78XX0_PCAC_ID) + mvEthE1116PhyBasicInit(0); +} + +/******************************************************************************* +* mvBoardIdGet - Get Board model +* +* DESCRIPTION: +* This function returns board ID. +* Board ID is 32bit word constructed of board model (16bit) and +* board revision (16bit) in the following way: 0xMMMMRRRR. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit board ID number, '-1' if board is undefined. +* +*******************************************************************************/ +MV_U32 mvBoardIdGet(MV_VOID) +{ + MV_U32 ctrlModel; + if (gBoardId != 0) + return gBoardId; +/*No detection mechanism*/ +#if defined(RD_MV78XX0_AMC) + return RD_78XX0_AMC_ID; +#elif defined(RD_MV78XX0_MASA) + return RD_78XX0_MASA_ID; +#elif defined(RD_MV78XX0_H3C) + return RD_78XX0_H3C_ID; +#elif defined(RD_MV78XX0_PCAC) + return RD_78XX0_PCAC_ID; +#endif + + ctrlModel = mvCtrlModelGet(); + + if (MV_78XX0_DEV_ID == ctrlModel || + MV_78100_DEV_ID == ctrlModel || + MV_76100_DEV_ID == ctrlModel) + { + return DB_78XX0_ID; + } + else + if (MV_78200_DEV_ID == ctrlModel) + { + return DB_78200_ID; + } + else + if (MV_6321_DEV_ID == ctrlModel || + MV_6322_DEV_ID == ctrlModel || + MV_6323_DEV_ID == ctrlModel) + { + return DB_632X_ID; + } + else + return UNKNOWN_BOARD_ID; +} +/******************************************************************************* +* refClkDevInit - Initialize the reference clock device. +* +* DESCRIPTION: +* This function initialize the on board DUART device to be used as +* reference clock device which its baudrate is known. +* Note that the channel to be used is channel 'B' and baudrate is set +* to 115200. +* Note that the module extract the DUART channel B base using the CPU +* interface API. This is done in order to make this code independed +* of its location relative to CPU interface initialization where address +* decodes are updated. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 refClkDevInit(MV_VOID) +{ + return 0; +} + +/******************************************************************************* +* refClkDevRelease - Release the reference clock device. +* +* DESCRIPTION: +* This function release the on board DUART device to its previous +* state before using it as a reference clocking device. +* Note that the module extract the DUART channel B base using the CPU +* interface API. This is done in order to make this code independed +* of its location relative to CPU interface initialization where address +* decodes are updated. +* +* INPUT: +* prevState - Previous state with the following encoding: +* byte0 - previous IER +* byte1 - previous DLL +* byte2 - previous DLM +* byte3 - previous divisior high +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID refClkDevRelease(MV_U32 prevState) +{ + return; +} + +/******************************************************************************* +* refClkDevBitRateGet - Get the reference clock device bit rate. +* +* DESCRIPTION: +* The UART device bauderate is theoretical. The UART protocol insert +* control bits along with data transport (start and stop bits). +* This means that for each 8 bit data (we use the UART with 8 bit data) +* two bits are for control, which gives us actual bauderate ~82.5% of +* the theoretical one. +* This function retrieve the on board DUART device bauderate. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 refClkDevBitRateGet(MV_VOID) +{ + return (mvBoardTclkGet() * TCLK_TO_COUNTER_RATIO); +} + +/******************************************************************************* +* refClkDevStart - Start the reference clock device. +* +* DESCRIPTION: +* This enable counter REF_TIMER for an input number of tikcs. +* +* INPUT: +* refClkDevBits - Number of bits to transmit (must be a multiple of 8). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID refClkDevStart(MV_U32 refClkDevBits) +{ + MV_CNTMR_CTRL cntmrCtrl; + + cntmrCtrl.enable = MV_TRUE; + + + if (MV_OK != mvCntmrStart(REF_TIMER, refClkDevBits, &cntmrCtrl)) + { + DB(mvOsPrintf("refClkDevStart - Can't start counter %d\n", REF_TIMER)); + } + else + { + while(mvCntmrRead(REF_TIMER)); + } +} + +/******************************************************************************* +* mvBoardVoiceAssembleModeGet - return SLIC/DAA assembly & interrupt modes +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ + +MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) +{ + switch(mvBoardIdGet()) + { + case DB_78XX0_ID: + case DB_78200_ID: + case DB_632X_ID: + *connMode = DUAL_CHIP_SELECT_MODE; + *irqMode = INTERRUPT_TO_TDM; + break; + default: + *connMode = *irqMode = -1; + mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); + } + return; + +} +/******************************************************************************* +* mvBoardTdmMppSet - set MPPs in TDM module +* +* DESCRIPTION: +* +* INPUT: type of second telephony device +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardTdmMppSet(MV_32 chType) +{ + return; +} +/******************************************************************************* +* mvBoardSlicGpioPinGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) +{ + MV_U32 boardId; + boardId = mvBoardIdGet(); + + switch (boardId) + { + case DB_78XX0_ID: + case DB_78200_ID: + case DB_632X_ID: + default: + return MV_ERROR; + } +} + diff --git a/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvLib.h b/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvLib.h new file mode 100644 index 0000000..c44d485 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvLib.h @@ -0,0 +1,203 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvBoardEnvLibh +#define __INCmvBoardEnvLibh + +/* defines */ +/* The below constant macros defines the board I2C EEPROM data offsets */ + +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" + +#define BD_NAME_OFFS +#define BD_MODEL_MAJOR_OFFS +#define BD_MODEL_MINOR_OFFS +#define BD_REV_MAJOR_OFFS +#define BD_REV_MINOR_OFFS + +/* Voice devices assembly modes */ +#define DAISY_CHAIN_MODE 1 +#define DUAL_CHIP_SELECT_MODE 0 +#define INTERRUPT_TO_MPP 1 +#define INTERRUPT_TO_TDM 0 + +/* Board specific */ +/* =============================== */ + +/* boards ID numbers */ + +/* New board ID numbers */ + +#define DB_78XX0_ID 0x00000050 +#define DB_78200_ID 0x00000090 +#define DB_78XX0_BP_MLL_ID 1683 +#define RD_78XX0_AMC_ID 0x00000060 +#define RD_78XX0_MASA_ID 0x00000070 +#define RD_78XX0_H3C_ID 0x00000080 +#define RD_78XX0_PCAC_ID 0x000000A0 +#define DB_632X_ID 0x00000010 + +#define MAX_BOARD_NAME_LEN 0x20 +#define UNKNOWN_BOARD_ID 0x0 + +/* DUART stuff for Tclk detection only */ +#define DUART_BAUD_RATE 115200 +#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ + + +typedef enum _devBoardClass +{ + BOARD_DEV_NOR_FLASH, + BOARD_DEV_NAND_FLASH, + BOARD_DEV_SEVEN_SEG, + BOARD_DEV_FPGA, + BOARD_DEV_SRAM, + BOARD_DEV_RTC, + BOARD_DEV_PEX_TO_PCI_BRIDGE, + BOARD_DEV_MV_SWITCH, + BOARD_DEV_USB_VBUS, + BOARD_DEV_REF_CLCK, + BOARD_DEV_VOIP_SLIC, + BOARD_DEV_BUTTON, + BOARD_DEV_POWER_BUTTON, + BOARD_DEV_RESTOR_BUTTON, + BOARD_DEV_HDD0_POWER, + BOARD_DEV_HDD1_POWER, + BOARD_DEV_FAN_POWER, + BOARD_DEV_SPI_FLASH, + BOARD_DEV_RESET, + BOARD_DEV_POWER_ON_LED, + BOARD_DEV_HDD_POWER, + BOARD_DEV_OTHER, +} MV_BOARD_DEV_CLASS; + + +typedef struct _devCsInfo +{ + MV_U8 deviceCS; + MV_U32 params; + MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ + MV_U8 devWidth; + +}MV_DEV_CS_INFO; + +typedef enum _boardMacSpeed +{ + BOARD_MAC_SPEED_10M, + BOARD_MAC_SPEED_100M, + BOARD_MAC_SPEED_1000M, + BOARD_MAC_SPEED_AUTO, + +}MV_BOARD_MAC_SPEED; + +/* Locals */ + + +MV_VOID mvBoardEnvInit(MV_VOID); +MV_U32 mvBoardIdGet(MV_VOID); +MV_STATUS mvBoardNameGet(char *pNameBuff); +MV_U32 mvBoardPhyAddrGet(MV_U32 ethPortNum); +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); +MV_32 mvBoardTclkGet(MV_VOID); +MV_32 mvBoardSysClkGet(MV_VOID); +MV_VOID mvBoardDebugLed(MV_U32 hexNum); +MV_VOID mvBoardDebug7Seg(MV_U32 hexNum); + +MV_U32 mvBoardMppGet(MV_U32 mppGroupNum); + +MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); +MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); + + +MV_32 mvBoardPciGpioPinGet(MV_U32 pciIf, MV_U32 idSel, MV_U32 intPin); +MV_32 mvBoardWDGpioPinGet(MV_VOID); +MV_32 mvBoardDbgLedGpioMaskGet(MV_VOID); + +MV_32 mvBoardGpioIntMaskGet(MV_VOID); +MV_32 mvBoardUSBVbusGpioPinGet(int devId); +MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); + + +MV_VOID mvBoardReset(MV_VOID); +MV_TARGET mvBoardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); +MV_U32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +MV_BOOL mvBoardIsBootFromNand(MV_VOID); +MV_BOOL mvBoardIsBootFromSpi(MV_VOID); +MV_BOOL mvBoardIsBootFromNor(MV_VOID); +MV_BOOL mvBoardIsBootFromNor32(MV_VOID); +MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); +MV_U32 mvBoardFlashParamGet(MV_VOID); +MV_U32 mvBoardGetMaxUsbIf(MV_VOID); +MV_VOID mvBoardTdmMppSet(MV_32 chType); +MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); +MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); +#endif /* __INCmvBoardEnvLibh */ diff --git a/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvSpec.c b/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvSpec.c new file mode 100644 index 0000000..f3ca762 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvSpec.c @@ -0,0 +1,184 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cntmr/mvCntmr.h" +#include "device/mvDevice.h" + +/* defines */ +#ifdef DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + + +/******************************************************************************* +* mvBoardPciGpioPinGet - Get board PCI interrupt level. +* +* DESCRIPTION: +* This function returns the value of Gpp Pin that is connected +* to the specified IDSEL and interrupt pin (A,B,C,D). For example, If +* IDSEL 8 (device 8) interrupt A is connected to GPIO pin 4 the function +* will return the value 4. +* This function supports multiple PCI interfaces. +* +* INPUT: +* pciIf - PCI interface number. +* devNum - device number (IDSEL). +* intPin - Interrupt pin (A=1, B=2, C=3, D=4). +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardPciGpioPinGet(MV_U32 pciIf, MV_U32 devNum, MV_U32 intPin) +{ + /*No PCI*/ + return MV_ERROR; +} + +/******************************************************************************* +* mvBoardWDGpioPinGet - Get board Watchdog NMI GPP pin number. +* +* DESCRIPTION: +* This function returns the number of Gpp Pin that is connected +* to the watchdog NMI interrupt. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardWDGpioPinGet(MV_VOID) +{ + int intPin = -1; + MV_U32 boardID; + + boardID = mvBoardIdGet(); + + if ((boardID == DB_78XX0_ID) || (boardID == DB_632X_ID) || + (boardID == RD_78XX0_AMC_ID) || (boardID == RD_78XX0_MASA_ID) || + (boardID == RD_78XX0_H3C_ID) || (boardID == RD_78XX0_PCAC_ID)) + { + return MV_ERROR; + } + + return intPin; +} + +/******************************************************************************* +* mvBoardDbgLedGpioMaskGet - Get board debug LED GPP bit mask. +* +* DESCRIPTION: +* This function returns a bit-mask of Gpp Pin that is connected +* to the debug LED. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32-bit bit-mask. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardDbgLedGpioMaskGet(MV_VOID) +{ + MV_U32 boardID; + MV_U32 intPin = -1; + + boardID = mvBoardIdGet(); + switch(boardID){ + case DB_78XX0_ID: +#ifdef MV_INCLUDE_MODEM_ON_TTYS1 + intPin = 0; +#else + return MV_ERROR; +#endif + break; + case RD_78XX0_AMC_ID: + intPin = 0; + break; + case RD_78XX0_MASA_ID: + intPin = (BIT22 | BIT23); + break; + case DB_632X_ID: + intPin = 0; + break; + } + + return intPin; +} + diff --git a/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvSpec.h b/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvSpec.h new file mode 100644 index 0000000..d4e9cad --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/boardEnv/mvBoardEnvSpec.h @@ -0,0 +1,392 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvBoardEnvSpech +#define __INCmvBoardEnvSpech + +#include "mvSysHwConfig.h" + +#define DB_MODEL_BACKPLAIN 0x0100 + +/* Clocks stuff */ +#define MV_BOARD_DEFAULT_TCLK 166000000 /* Default Tclk 166MHz */ +#define MV_BOARD_DEFAULT_SYSCLK 200000000 /* Default SysClk 200MHz */ + +/* MPP[0] = GE_TXCLK MPP[1] = GE_TXCTL */ +/* MPP[2] = GE_RXCTL MPP[3] = GE_RXCLK */ +/* MPP[4] = GE_TXD0 MPP[5] = GE_TXD1 */ +/* MPP[6] = GE_TXD2 MPP[7] = GE_TXD3 */ +#define RD_MASA_MPP0_7 0x22222222 + +/* MPP[8] = GE_RXD0 MPP[9] = GE_RXD1 */ +/* MPP[10] = GE_RXD2 MPP[11] = GE_RXD3 */ +/* MPP[12] = DC MPP[13] = SysRst */ +/* MPP[14] = SATA_ACT MPP[15] = SATA_ACT */ +#define RD_MASA_MPP8_15 0x33302222 + +/* MPP[16] = DC MPP[17] = DC */ +/* MPP[18] = DC MPP[19] = DC */ +/* MPP[20] = DC MPP[21] = DC */ +/* MPP[22] = DC MPP[23] = DC */ +#define RD_MASA_MPP16_23 0x00000000 + +/* MPP[24] = DC MPP[25] = DC */ +/* MPP[26] = DC MPP[26] = DC */ +/* MPP[28] = DC MPP[27] = DC */ +/* MPP[30] = DC MPP[28] = DC */ +#define RD_MASA_MPP24_31 0x00000000 + +/* MPP[0] = GE_TXCLK MPP[1] = GE_TXCTL */ +/* MPP[2] = GE_RXCTL MPP[3] = GE_RXCLK */ +/* MPP[4] = GE_TXD0 MPP[5] = GE_TXD1 */ +/* MPP[6] = GE_TXD2 MPP[7] = GE_TXD3 */ +#define RD_AMC_MPP0_7 0x22222222 + +/* MPP[8] = GE_RXD0 MPP[9] = GE_RXD1 */ +/* MPP[10] = GE_RXD2 MPP[11] = GE_RXD3 */ +/* MPP[12] = DC MPP[13] = DC */ +/* MPP[14] = DC MPP[15] = DC */ +#define RD_AMC_MPP8_15 0x22222222 + +/* MPP[16] = DC MPP[17] = DC */ +/* MPP[18] = DC MPP[19] = DC */ +/* MPP[20] = DC MPP[21] = DC */ +/* MPP[22] = DC MPP[23] = DC */ +#define RD_AMC_MPP16_23 0x22222222 + +/* MPP[24] = DC MPP[25] = DC */ +/* MPP[26] = DC MPP[26] = DC */ +/* MPP[28] = DC MPP[27] = DC */ +/* MPP[30] = DC MPP[28] = DC */ +#define RD_AMC_MPP24_31 0x22222222 + +/* MPP[24] = DC MPP[25] = DC */ +/* MPP[26] = DC MPP[26] = DC */ +/* MPP[28] = DC MPP[27] = DC */ +/* MPP[30] = DC MPP[28] = DC */ +#define RD_AMC_MPP32_39 0x11112222 +#define RD_AMC_MPP40_47 0x0 +#define RD_AMC_MPP48_49 0x31 + +/* MPP[0] = GE_TXCLK MPP[1] = GE_TXCTL */ +/* MPP[2] = GE_RXCTL MPP[3] = GE_RXCLK */ +/* MPP[4] = GE_TXD0 MPP[5] = GE_TXD1 */ +/* MPP[6] = GE_TXD2 MPP[7] = GE_TXD3 */ +#define RD_H3C_MPP0_7 0x22222222 + +/* MPP[8] = GE_RXD0 MPP[9] = GE_RXD1 */ +/* MPP[10] = GE_RXD2 MPP[11] = GE_RXD3 */ +/* MPP[12] = DC MPP[13] = DC */ +/* MPP[14] = DC MPP[15] = DC */ +#define RD_H3C_MPP8_15 0x00302222 + +/* MPP[16] = DC MPP[17] = DC */ +/* MPP[18] = DC MPP[19] = DC */ +/* MPP[20] = DC MPP[21] = DC */ +/* MPP[22] = DC MPP[23] = DC */ +#define RD_H3C_MPP16_23 0x00000000 + +/* MPP[24] = DC MPP[25] = DC */ +/* MPP[26] = DC MPP[26] = DC */ +/* MPP[28] = DC MPP[27] = DC */ +/* MPP[30] = DC MPP[28] = DC */ +#define RD_H3C_MPP24_31 0x00000000 + +/* MPP[0] = GE_TXCLK MPP[1] = GE_TXCTL */ +/* MPP[2] = GE_RXCTL MPP[3] = GE_RXCLK */ +/* MPP[4] = GE_TXD0 MPP[5] = GE_TXD1 */ +/* MPP[6] = GE_TXD2 MPP[7] = GE_TXD3 */ +#define DB_78XX0_MPP0_7 0x22222222 + +/* MPP[8] = GE_RXD0 MPP[9] = GE_RXD1 */ +/* MPP[10] = GE_RXD2 MPP[11] = GE_RXD3 */ +/* MPP[12] = GPIO[12] - USB1_VBUS MPP[13] = MV_SYS_RST */ +/* MPP[14] = SATA1_ACT MPP[15] = SATA2_ACT */ +#define DB_78XX0_MPP8_15 0x33302222 + +/* MPP[16] = UART2_TXD MPP[17] = UART2_RXD */ +/* MPP[18] = UART0_CTS MPP[19] = UART0_RTS */ +/* MPP[20] = UART1_CTS MPP[21] = UART1_RTS */ +/* MPP[22] = UART3_TXD MPP[23] = UART3_RXD */ +#define DB_78XX0_MPP16_23 0x44444444 +#define DB_78XX0_MPP16_23_NAND 0x44445544 + +/* MPP[24] = DC MPP[25] = DC */ +/* MPP[26] = DC MPP[26] = DC */ +/* MPP[28] = DC MPP[27] = DC */ +/* MPP[30] = DC MPP[28] = DC */ +#define DB_78XX0_MPP24_31 0x00000000 + + +#define DB_632X_MPP0_7 0x22222222 +#define DB_632X_MPP8_15 0x22222222 +#define DB_632X_MPP16_23 0x22222222 +#define DB_632X_MPP24_31 0x01311111 +#define DB_632X_MPP32_39 0x60666666 +#define DB_632X_MPP40_47 0x66661115 + +/* MPP[0] = GE_TXCLK MPP[1] = GE_TXCTL */ +/* MPP[2] = GE_RXCTL MPP[3] = GE_RXCLK */ +/* MPP[4] = GE_TXD0 MPP[5] = GE_TXD1 */ +/* MPP[6] = GE_TXD2 MPP[7] = GE_TXD3 */ +#define DB_78200_MPP0_7 0x22222222 + +/* MPP[8] = GE_RXD0 MPP[9] = GE_RXD1 */ +/* MPP[10] = GE_RXD2 MPP[11] = GE_RXD3 */ +/* MPP[12] = GPIO[12] - USB1_VBUS MPP[13] = MV_SYS_RST */ +/* MPP[14] = SATA1_ACT MPP[15] = SATA2_ACT */ +#define DB_78200_MPP8_15 0x22222222 + +/* MPP[16] = UART2_TXD MPP[17] = UART2_RXD */ +/* MPP[18] = UART0_CTS MPP[19] = UART0_RTS */ +/* MPP[20] = UART1_CTS MPP[21] = UART1_RTS */ +/* MPP[22] = UART3_TXD MPP[23] = UART3_RXD */ +#define DB_78200_MPP16_23 0x22222222 + +/* MPP[24] = DC MPP[25] = DC */ +/* MPP[26] = DC MPP[26] = DC */ +/* MPP[28] = DC MPP[27] = DC */ +/* MPP[30] = DC MPP[28] = DC */ +#define DB_78200_MPP24_31 0x22222222 + +/* MPP[24] = DC MPP[25] = DC */ +/* MPP[26] = DC MPP[26] = DC */ +/* MPP[28] = DC MPP[27] = DC */ +/* MPP[30] = DC MPP[28] = DC */ +#define DB_78200_MPP32_39 0x11112222 + +#define DB_78XX0_HAS_PTP_BRIDGE 1 + +/* 7-Segment stuff */ +#define MV_BOARD_7SEG_BASE ((RD_78XX0_H3C_ID == mvBoardIdGet())? \ + DEVICE_CS2_BASE : DEVICE_CS1_BASE) +#define MV_BOARD_7SEG_PARAM 0x003E07CF /* 8 bit */ + +/* Board main flash */ +#define MV_BOARD_FLASH_BASE_ADRS DEVICE_CS0_BASE +#define MV_BOARD_FLASH_BUS_WIDTH 32 /* Two byte width bus */ +#define MV_BOARD_FLASH_DEVICE_WIDTH 16 /* 16-bit width Flash mode*/ +#define MV_BOARD_FLASH_PARAM (mvBoardFlashParamGet()) +#define MV_BOARD_FLASH_PARAM_VAL 0x803E07CF /* 32 bit */ + +/* NAND flash */ +#define MV_NAND_CS DEV_CS2 +#define MV_NAND_632X_CS BOOT_CS +#define MV_NAND_78200_CS DEV_CS3 +#define MV_NAND_AMC_CS BOOT_CS +#define MV_NAND_CARE 0 +#define MV_BOARD_NFLASH_DEVICE_WIDTH 8 /* 8-bit width Flash mode*/ +#define MV_BOARD_NFLASH_BASE_ADRS DEVICE_CS2_BASE /* empty */ +#define MV_BOARD_NFLASH_PARAM 0x003E07CF /* 8 bit */ + +/* Boot Flash definitions */ +#define MV_BOARD_BOOT_FLASH_BASE_ADRS BOOTDEV_CS_BASE +#define MV_BOARD_BOOT_FLASH_BUS_WIDTH 8 /* One byte width bus */ +#define MV_BOARD_BOOT_FLASH_DEVICE_WIDTH 8 /* 8-bit width Flash mode */ +#define MV_BOARD_BOOT_FLASH_PARAM 0x003E07CF /* 8 bit */ +#define MV_BOARD_78200_BOOT_FLASH_PARAM 0x403E07CF /* 16 bit */ + + +#define DEVICE_CS0_PARAM MV_BOARD_FLASH_PARAM +#define DEVICE_78200_CS0_PARAM 0 +#define DEVICE_CS1_PARAM MV_BOARD_7SEG_PARAM +#define DEVICE_CS2_PARAM MV_BOARD_NFLASH_PARAM +#define DEVICE_78200_CS2_PARAM 0 + +#define DEVICE_CS3_PARAM 0 +#define DEVICE_78200_CS3_PARAM MV_BOARD_NFLASH_PARAM + +#define DEVICE_CS0_PARAM_WR 0xF0F0F +#define DEVICE_CS1_PARAM_WR 0xF0F0F +#define DEVICE_CS2_PARAM_WR 0xF0F0F +#define DEVICE_CS3_PARAM_WR 0xF0F0F + +#define BOOTDEV_CS_PARAM MV_BOARD_BOOT_FLASH_PARAM +#define BOOTDEV_78200_CS_PARAM MV_BOARD_78200_BOOT_FLASH_PARAM + +#define DRAM_SLOT_NUM 2 + +/* Debug Led stuff. GPP pin assigments. Board depended. */ +#define MV_BOARD_LED_NUM 0 + +/* Other GPIOs */ +/* DB-78100-A-BP */ +#define DB_78XX0_LED_GPP_PIN(ledNum) (0) +#define DB_78XX0_SW_RESET 13 +#define DB_78XX0_USB_VBUS_PIN(usb) 12 + +/* DB-78200-A-BP */ +#define DB_78200_SW_RESET 7 +#define DB_78200_GPIO_OUTPUT_EN (BIT7) + +/* RD-AMC */ +#define RD_AMC_LED_GPP_PIN(ledNum) (0) +#define RD_AMC_SW_RESET 7 +#define RD_AMC_USB_VBUS_PIN(usb) ((usb == 0) ? 22 : ((usb == 1) ? 12 : 23)) +/* GPP 12, 13, 16-19 are output */ +#define RD_AMC_GPIO_OUTPUT_EN (BIT8 | BIT12 | BIT13 | BIT16 | BIT17 | BIT18 | BIT19 | BIT25) + +#define RD_H3C_SW_RESET 13 +#define RD_H3C_SW_RESET_SELECT 14 +#define RD_H3C_USB_VBUS_PIN(usb) 12 +/* GPP 14 is output */ +#define RD_H3C_GPIO_OUTPUT_EN (BIT14) + +#define RD_MASA_LED_GPP_PIN(ledNum) 23 +#define RD_MASA_DEBUG_LED_GPP_PIN(ledNum) 22 +#define RD_MASA_SW_RESET 13 +/* GPP 12, 13, 16-19 are output */ +#define RD_MASA_GPIO_OUTPUT_EN (BIT17 | BIT18 | BIT22 | BIT23) +#define RD_MASA_USB_OC BIT16 +#define RD_MASA_USB_PWR BIT17 +#define RD_MASA_HDD_PWR BIT18 +#define RD_MASA_SW_INT BIT19 +#define RD_MASA_RTC_INT BIT20 +#define RD_MASA_PHY_INT BIT21 +#define RD_78XX0_MASA_INT_MASK (RD_MASA_USB_OC | RD_MASA_SW_INT | \ + RD_MASA_RTC_INT | RD_MASA_PHY_INT) + +/* DB-6323-A-BP */ +#define DB_6323_GPIO_OUTPUT_EN (BIT0 | BIT1 | BIT2 | BIT3 | BIT17 | BIT18 | BIT19 | BIT20) +#define DB_6323_SW_RESET (0) + + +#ifdef MV_INCLUDE_MODEM_ON_TTYS1 +#define DB_78XX0_SERIAL_DTR 2 +#define DB_78XX0_SERIAL_DSR 3 +#define DB_78XX0_SERIAL_DCD 1 +#define DB_78XX0_SERIAL_RI 19 +#endif + +/* GPIO interrupt connectivity on the DB-MV78XX0 board */ + +/* I2C bus addresses */ +#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ +#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 +#ifdef RD_MV78XX0_MASA +/* SODIMM only two bit TWSI address */ +#define MV_BOARD_DIMM0_I2C_ADDR 0x50 +#define MV_BOARD_DIMM1_I2C_ADDR 0x51 +#else +#define MV_BOARD_DIMM0_I2C_ADDR 0x56 +#define MV_BOARD_DIMM1_I2C_ADDR 0x54 +#endif +#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_CPU0_I2C_ADDR 0x51 +#define MV_BOARD_CPU0_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_CPU1_I2C_ADDR 0x51 /* Both CPU use the same I2C EEPROM */ +#define MV_BOARD_CPU1_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_SYS_I2C_ADDR 0x50 +#define MV_BOARD_SYS_I2C_ADDR_TYPE ADDR7_BIT +#if defined (MV78XX0_Z0) || defined (MV632X) +#define MV_BOARD_RTC_I2C_CHANNEL 0x0 +#else +#define MV_BOARD_RTC_I2C_CHANNEL 0x1 +#endif +#define MV_BOARD_RTC_I2C_ADDR 0x68 +#define MV_BOARD_RTC_I2C_ADDR_TYPE ADDR7_BIT + +/* Ethernet stuff */ +#define MV78XX0_ETH_MAX_PORTS 2 +#define MV78200_ETH_MAX_PORTS 4 + +#define BOARD_ETH_START_PORT_NUM 0 +#define BOARD_ETH_END_PORT_NUM 3 +#define BOARD_ETH_PORT_NUM 4 +#define MV_ETH_PORT_SGMII {0, 0, 0, 0}; +#define MV_ETH_PORT_PHY_ADDR {0x8, 0x9, 0xA, 0xB}; + +#define MV_BOARD_MAX_USB_IF (mvBoardGetMaxUsbIf()) + +#define MV_BOARD_MAX_TWSI_DEV 8 +#define MV_BOARD_MAX_PCI_DEV 5 + +/* Supported clocks */ +#define MV_BOARD_TCLK_100MHZ 100000000 +#define MV_BOARD_TCLK_125MHZ 125000000 +#define MV_BOARD_TCLK_133MHZ 133333334 +#define MV_BOARD_TCLK_150MHZ 150000000 +#define MV_BOARD_TCLK_166MHZ 166666667 +#define MV_BOARD_TCLK_200MHZ 200000000 + +#define MV_BOARD_SYSCLK_100MHZ 100000000 +#define MV_BOARD_SYSCLK_125MHZ 125000000 +#define MV_BOARD_SYSCLK_133MHZ 133333334 +#define MV_BOARD_SYSCLK_150MHZ 150000000 +#define MV_BOARD_SYSCLK_166MHZ 166666667 +#define MV_BOARD_SYSCLK_200MHZ 200000000 +#define MV_BOARD_SYSCLK_160MHZ 160000000 +#define MV_BOARD_SYSCLK_233MHZ 233333334 +#define MV_BOARD_SYSCLK_250MHZ 250000000 +#define MV_BOARD_SYSCLK_267MHZ 266666667 +#define MV_BOARD_SYSCLK_300MHZ 300000000 +#define MV_BOARD_SYSCLK_333MHZ 333333334 +#define MV_BOARD_SYSCLK_400MHZ 400000000 + + +#define SGMII_OUTBAND_AN +#define PHY_UPDATE_TIMEOUT 10000 +#endif /* __INCmvBoardEnvSpech */ diff --git a/board/mv_feroceon/mv_dd/dd_family/cpu/mvCpu.c b/board/mv_feroceon/mv_dd/dd_family/cpu/mvCpu.c new file mode 100644 index 0000000..293fc3c --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/cpu/mvCpu.c @@ -0,0 +1,292 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/*#include "mvCpu.h"*/ +#include "boardEnv/mvBoardEnvLib.h" +#include "cpu/mvCpu.h" +#include "twsi/mvTwsi.h" + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* locals */ +static int cpuCoreIdGet(MV_VOID); +/******************************************************************************* +* mvCpuSampleAtResetGet - Get the CPU sample at reset register value +* +* DESCRIPTION: +* Relevent for 1160 only. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit sample at reset register +* +*******************************************************************************/ +MV_U32 mvCpuSampleAtResetGet(MV_VOID) +{ + MV_U8 data[4]; + MV_U32 mvSampleAtReset = 0; + + /* Read 88F1160 S@R register */ + MV_TWSI_SLAVE twsiSlave; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.slaveAddr.address = CPU_TWSI_DEBUG_ADDR; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_TRUE; + + if( MV_OK != mvTwsiRead (0, &twsiSlave, data, 4)) + { + return 0xffffffff; + } + else + { + mvSampleAtReset = (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3]; + } + + return mvSampleAtReset; +} + +/******************************************************************************* +* mvCpuPclkGet - Get the CPU pClk (pipe clock) +* +* DESCRIPTION: +* This routine extract the CPU core clock. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ + +/* Mul constant */ +int sys2cpu_clk_ratio_m[] = {1, 3, 2, 5, 3, 7, 4, 9, 5, 1, 6}; +/* Div constant */ +int sys2cpu_clk_ratio_n[] = {1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1}; + +MV_U32 mvCpuPclkGet(MV_VOID) +{ + int p = 0; + MV_U32 tmpPClkRate = MV_REG_READ(CPU_RESET_SAMPLE_L_REG); + if(whoAmI() == 0) + p = ((tmpPClkRate & MSAR_SYSCLK2CPU_MASK0) >> MSAR_SYSCLK2CPU_OFFS0); + else + p = ((tmpPClkRate & MSAR_SYSCLK2CPU_MASK1) >> MSAR_SYSCLK2CPU_OFFS1); + tmpPClkRate = sys2cpu_clk_ratio_m[p]; + tmpPClkRate *= mvBoardSysClkGet(); + + return (tmpPClkRate/sys2cpu_clk_ratio_n[p]); +} + +MV_U32 mvCpuL2ClkGet(MV_VOID) +{ + MV_U32 tmpL2ClkRate = MV_REG_READ(CPU_RESET_SAMPLE_L_REG); + + if(whoAmI() == 0) + tmpL2ClkRate = ((tmpL2ClkRate & MSAR_CPUL2CLK_MASK0) >> MSAR_CPUL2CLK_OFFS0); + else + tmpL2ClkRate = ((tmpL2ClkRate & MSAR_CPUL2CLK_MASK1) >> MSAR_CPUL2CLK_OFFS1); + tmpL2ClkRate++; + + return (mvCpuPclkGet() / tmpL2ClkRate); +} +/******************************************************************************* +* mvAHBclkGet - Get the AHB Clk +* +* DESCRIPTION: +* This routine extract the AHB core clock. Relevent for 1160 only. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvAHBclkGet(MV_VOID) +{ + MV_U32 mvSampleAtReset = 0; + MV_U32 mvSysClkDiv = 0; + MV_U32 tmpPClkRate=0; + + /* Read 88F1160 S@R register */ + mvSampleAtReset = mvCpuSampleAtResetGet(); + if (mvSampleAtReset & BIT12) + { + mvSysClkDiv = 32 + (2 * ((mvSampleAtReset >> 7) & 0x1f)); + } + else + { + mvSysClkDiv = (mvSampleAtReset >> 7) & 0x1f; + } + + tmpPClkRate = mvCpuPclkGet() / mvSysClkDiv; + + return tmpPClkRate; +} + +/******************************************************************************* +* mvCpuNameGet - Get CPU name +* +* DESCRIPTION: +* This function returns a string describing the CPU model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* None. +*******************************************************************************/ +MV_VOID mvCpuNameGet(char *pNameBuff) +{ + MV_U32 cpuModel; + + cpuModel = mvOsCpuPartGet(); + + /* The CPU module is indicated in the Processor Version Register (PVR) */ + switch(cpuModel) + { + case CPU_PART_ARM926: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); + break; + case CPU_PART_ARM946: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); + break; + case CPU_PART_MRVL571: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "MRVL571",mvOsCpuRevGet()); + break; + case CPU_PART_MRVL521: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "MRVL521",mvOsCpuRevGet()); + break; + default: + mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); + } /* switch */ +} + + +/******************************************************************************* +* whoAmI - Get CPU name +* +* DESCRIPTION: +* This function returns a string describing the CPU model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* None. +*******************************************************************************/ +unsigned int whoAmI(void) +{ +#if !defined(MV78XX0_Z0) + MV_U16 model = mvCtrlModelGet(); + switch (model) { + default: + return (unsigned int)MASTER_CPU; + case MV_78200_DEV_ID: + case MV_6321_DEV_ID: + case MV_6322_DEV_ID: + case MV_6323_DEV_ID: + return (cpuCoreIdGet() > 0) ? SLAVE_CPU: MASTER_CPU; + } +#else + return MASTER_CPU; +#endif + +} + +static int cpuCoreIdGet(MV_VOID) +{ + MV_U32 value; + + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0 @ read control reg\n" + : "=r" (value) :: "memory"); + return !!(value & (1 << 14)); +} + + diff --git a/board/mv_feroceon/mv_dd/dd_family/cpu/mvCpu.h b/board/mv_feroceon/mv_dd/dd_family/cpu/mvCpu.h new file mode 100644 index 0000000..524439e --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/cpu/mvCpu.h @@ -0,0 +1,101 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuArmh +#define __INCmvCpuArmh + +/* defines */ +#define MASTER_CPU 0 +#define SLAVE_CPU 1 + + +#define CPU_PART_MRVL131 0x131 +#define CPU_PART_ARM926 0x926 +#define CPU_PART_ARM946 0x946 +#define CPU_PART_MRVL571 0x571 +#define CPU_PART_MRVL521 0x521 +#define MV_CPU_ARM_CLK_ELM_SIZE 12 +#define MV_CPU_ARM_CLK_RATIO_OFF 8 +#define MV_CPU_ARM_CLK_DDR_OFF 4 + +#define CPU_TWSI_DEBUG_ADDR 0x2f + +#ifndef MV_ASMLANGUAGE +typedef struct _mvCpuArmClk +{ + MV_U32 cpuClk; /* CPU clock in MHz */ + MV_U32 ddrClk; /* DDR clock in MHz */ + MV_U32 clkRatio; /* CPU DDR clock ratio */ + +}MV_CPU_ARM_CLK; + +MV_U32 mvAHBclkGet(MV_VOID); +unsigned int whoAmI(MV_VOID); +MV_U32 mvCpuPclkGet(MV_VOID); +MV_U32 mvCpuL2ClkGet(MV_VOID); +MV_VOID mvCpuNameGet(char *pNameBuff); + +#endif /* MV_ASMLANGUAGE */ +#endif /* __INCmvCpuArmh */ diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvAddrDec.c b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvAddrDec.c new file mode 100644 index 0000000..e830ca8 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvAddrDec.c @@ -0,0 +1,427 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/******************************************************************************* +* mvCtrlEnvAddrDec.h - Marvell controller address decode library +* +* DESCRIPTION: +* The Marvell controller device has a fully programmable address map. +* There is a separate address map to each of the interfaces: +* - CPU address space +* - PCI_0 address space +* - PCI_1 address space +* - Gigabit Ethernet/FIFO interface address space +* - IDMA address space +* - XOR DMA address space (where XOR available) +* - Serial communication address space. +* Each interface includes programmable address windows that allows it +* to access any of the MV6456x resources. Each window can map up to +* 4 GB of address space. +* This file contains Marvell Controller address decode library API +* for Gigabit Ethernet, Serial communication, IDMA and XOR that shares +* the same address space decode implementation. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* #define MV_DEBUG */ + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* Base Address Register (BAR) */ +#define BAR_TARGET_DRAM DRAM_TARGET_ID +#define BAR_TARGET_DEVICE DEV_TARGET_ID + + +#define BAR_TARGET_PCI0 PCI0_TARGET_ID +#define BAR_TARGET_PCI1 PCI0_TARGET_ID +#define BAR_TARGET_PCI2 PCI0_TARGET_ID +#define BAR_TARGET_PCI3 PCI1_TARGET_ID +#define BAR_TARGET_PCI4 PCI1_TARGET_ID +#define BAR_TARGET_PCI5 PCI1_TARGET_ID + +/* DRAM attributes */ +#define BAR_DRAM_BANK_MASK 0xF +#define BAR_DRAM_BANK(bankNo) (~(1 << (bankNo)) & BAR_DRAM_BANK_MASK) +#define BAR_DRAM_COHERENCY_OFFS 4 /* DRAM Cache coherency offset */ +#define BAR_DRAM_COHERENCY_MASK (0x3 << BAR_DRAM_COHERENCY_OFFS) +#define BAR_DRAM_NO_COHERENCY (NO_COHERENCY << BAR_DRAM_COHERENCY_OFFS) +#define BAR_DRAM_WT_COHERENCY (WT_COHERENCY << BAR_DRAM_COHERENCY_OFFS) +#define BAR_DRAM_WB_COHERENCY (WB_COHERENCY << BAR_DRAM_COHERENCY_OFFS) + + /* Device attributes */ +#define BAR_DEVICE_BANK_MASK 0x1F +#define BAR_DEVICE_BANK(bankNo) (~(1 << (bankNo)) & BAR_DEVICE_BANK_MASK) + + /* PCI0/1 attributes */ +#define BAR_PCI_BYTE_SWAP_OFFS 0 +#define BAR_PCI_BYTE_SWAP_MASK (0x3 << BAR_PCI_BYTE_SWAP_OFFS) +#define BAR_PCI_BYTE_SWAP MV_BYTE_SWAP +#define BAR_PCI_NO_SWAP MV_NO_SWAP +#define BAR_PCI_BYTE_WORD_SWAP MV_BYTE_WORD_SWAP +#define BAR_PCI_WORD_SWAP MV_WORD_SWAP +#define BAR_PCIX_NO_SNOOP_OFFS 2 +#define BAR_PCIX_NO_SNOOP_MASK (1 << BAR_PCIX_NO_SNOOP_OFFS) +#define BAR_PCI_BAR_TYPE_OFFS 3 /* PCI MEM/IO space */ +#define BAR_PCI_BAR_TYPE_MASK (1 << BAR_PCI_BAR_TYPE_OFFS) +#define BAR_PCI_IO_SPACE (0 << BAR_PCI_BAR_TYPE_OFFS) +#define BAR_PCI_MEMORY_SPACE (1 << BAR_PCI_BAR_TYPE_OFFS) +#define BAR_PCI_REQ64_MODE_OFFS 4 /* PCIx_REQ64n control */ +#define BAR_PCI_REQ64_MODE_MASK (1 << BAR_PCI_REQ64_MODE_OFFS) +#define BAR_PCI_REQ64_ALWAYS (0 << BAR_PCI_REQ64_MODE_OFFS) +#define BAR_PCI_REQ64_PER_REQU (1 << BAR_PCI_REQ64_MODE_OFFS) + +#define BAR_PCI_LANE_SELECT_OFF 4 +#define BAR_PCI_LANE_SELECT_MASK (0xf << BAR_PCI_LANE_SELECT_OFF) +#define BAR_PCI_LANE_0 (0xe << BAR_PCI_LANE_SELECT_OFF) +#define BAR_PCI_LANE_1 (0xd << BAR_PCI_LANE_SELECT_OFF) +#define BAR_PCI_LANE_2 (0xb << BAR_PCI_LANE_SELECT_OFF) +#define BAR_PCI_LANE_3 (0x7 << BAR_PCI_LANE_SELECT_OFF) + +/* Size register */ +#define BAR_SIZE_ALIGNMENT 0x10000 /* Minimum size 64K */ + +/* typedefs */ + +/* Locals */ + +MV_TARGET_ATTRIB mvTargetDefaultsArray[] = +{ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ + {0x0B,DRAM_TARGET_ID}, /* SDRAM_CS2 */ + {0x07,DRAM_TARGET_ID}, /* SDRAM_CS3 */ + {0x3E,DEV_TARGET_ID}, /* DEVICE_CS0 */ + {0x3D,DEV_TARGET_ID}, /* DEVICE_CS1 */ + {0x3B,DEV_TARGET_ID}, /* DEVICE_CS2 */ + {0x37,DEV_TARGET_ID}, /* DEVICE_CS3 */ + {0x2F,DEV_TARGET_ID}, /* DEV_BOOCS*/ +#if !defined(MV78XX0_Z0) + {0x1F,DEV_TARGET_ID}, /* DEV_SPI*/ +#endif + {0xE0,PCI0_TARGET_ID}, /* PCI0_IO */ + {0xE8,PCI0_TARGET_ID}, /* PCI0_MEM */ + {0xD0,PCI0_TARGET_ID}, /* PCI1_IO */ + {0xD8,PCI0_TARGET_ID}, /* PCI1_MEM */ + {0xB0,PCI0_TARGET_ID}, /* PCI2_IO */ + {0xB8,PCI0_TARGET_ID}, /* PCI2_MEM */ + {0x70,PCI0_TARGET_ID}, /* PCI3_IO */ + {0x78,PCI0_TARGET_ID}, /* PCI3_MEM */ + {0xE0,PCI1_TARGET_ID}, /* PCI4_IO */ + {0xE8,PCI1_TARGET_ID}, /* PCI4_MEM */ + {0xD0,PCI1_TARGET_ID}, /* PCI5_IO */ + {0xD8,PCI1_TARGET_ID}, /* PCI5_MEM */ + {0xB0,PCI1_TARGET_ID}, /* PCI6_IO */ + {0xB8,PCI1_TARGET_ID}, /* PCI6_MEM */ + {0x70,PCI1_TARGET_ID}, /* PCI7_IO */ + {0x78,PCI1_TARGET_ID}, /* PCI7_MEM */ + {0x01,CRYPT_TARGET_ID}, /* CRYPT_ENG */ + {0xFF, 0xFF} /* INTER_REGS */ +}; + +#define CTRL_DEC_BASE_OFFS 16 +#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) +#define CTRL_DEC_BASE_ALIGNMENT 0x10000 + +#define CTRL_DEC_SIZE_OFFS 16 +#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) +#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 + +#define CTRL_DEC_WIN_EN BIT0 + + +/******************************************************************************* +* mvCtrlAddrDecToReg - Get address decode register format values +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) +{ + + MV_U32 baseToReg=0 , sizeToReg=0; + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; + + /* Write to address decode Base Address Register */ + pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; + pAddrDecRegs->baseReg |= baseToReg; + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + return MV_BAD_PARAM; + } + + /* set size */ + pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; + pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); + + + return MV_OK; + +} + + +/******************************************************************************* +* mvCtrlRegToAddrDec - Extract address decode struct from registers. +* +* DESCRIPTION: +* This function extract address decode struct from address decode +* registers given as parameters. +* +* INPUT: +* pAddrDecRegs - Address decode register struct. +* +* OUTPUT: +* pAddrDecWin - Target window data structure. +* +* RETURN: +* MV_BAD_PARAM if address decode registers data is invalid. +* +*******************************************************************************/ +MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 sizeRegVal; + + sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> + CTRL_DEC_SIZE_OFFS; + + pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); + + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; + + pAddrDecWin->baseHigh = 0; + + return MV_OK; + +} + + +/******************************************************************************* +* mvCtrlAddrDecToParams - Get address decode register format values +* +* DESCRIPTION: +* This function returns the given address window information in the +* format of address decode base and size registers. +* +* INPUT: +* pAddrDecWin - Target window data structure. +* +* OUTPUT: +* pWinParam - Address decode window parameters. +* +* RETURN: +* MV_BAD_PARAM if base address is invalid parameter or target is +* unknown. +* +*******************************************************************************/ +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, + MV_DEC_WIN_PARAMS *pWinParam) +{ + MV_TARGET_ATTRIB targetAttrib; + MV_U32 size; /* Holds BAR size */ + /* 2) Initialize Size register */ + /* 2.1 Get address decode size register value to given size */ + size = ctrlSizeToReg(pAddrDecWin->addrWin.size, BAR_SIZE_ALIGNMENT); + /* Size parameter validity check. */ + if (-1 == size) + { + DB(mvOsPrintf("mvCtrlAddrDecToParams: ERR. addrDecSizeToReg failed.\n")); + return MV_BAD_PARAM; + } + + /* Write the size register value */ + pWinParam->size = size; + /* Base address */ + pWinParam->baseAddr = pAddrDecWin->addrWin.baseLow; + /* attrib and targetId */ + mvCtrlAttribGet(pAddrDecWin->target, &targetAttrib); + pWinParam->attrib = targetAttrib.attrib; + pWinParam->targetId = targetAttrib.targetId; + return MV_OK; + +} + +/******************************************************************************* +* mvCtrlParamsToAddrDec - Extract address decode struct from registers. +* +* DESCRIPTION: +* This function extract address decode struct from address decode +* registers given as parameters. +* +* INPUT: +* pWinParam - Address decode register parameters +* +* OUTPUT: +* pAddrDecWin - Target window data structure. +* +* RETURN: +* MV_BAD_PARAM if address decode registers data is invalid. +* +*******************************************************************************/ +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, + MV_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttrib; + + pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; + + /* Upper 32bit address base is supported under PCI High Address remap */ + pAddrDecWin->addrWin.baseHigh = 0; + + /* Prepare sizeReg to ctrlRegToSize function */ + pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, BAR_SIZE_ALIGNMENT); + + if (-1 == pAddrDecWin->addrWin.size) + { + DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); + return MV_BAD_PARAM; + } + + /* attrib and targetId */ + targetAttrib.attrib = pWinParam->attrib; + targetAttrib.targetId = pWinParam->targetId; + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + if (MAX_TARGETS == pAddrDecWin->target) + { + DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. 0x%x, 0x%x\n",targetAttrib.targetId, targetAttrib.attrib)); + return MV_ERROR; + } + return MV_OK; +} + + +/******************************************************************************* +* mvCtrlAttribGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ + +MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib) +{ + + targetAttrib->attrib = mvTargetDefaultsArray[target].attrib; + targetAttrib->targetId = mvTargetDefaultsArray[target].targetId; + + return MV_OK; + +} +/******************************************************************************* +* mvCtrlTargetGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) +{ + MV_TARGET target; + for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) + { + if ((mvTargetDefaultsArray[target].attrib == targetAttrib->attrib) && + (mvTargetDefaultsArray[target].targetId == targetAttrib->targetId)) + { + /* found it */ + break; + } + } + + return target; +} + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvAddrDec.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvAddrDec.h new file mode 100644 index 0000000..c4dea05 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvAddrDec.h @@ -0,0 +1,126 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvAddrDech +#define __INCmvCtrlEnvAddrDech + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" + +/* defines */ + +typedef struct _mvDecRegs +{ + MV_U32 baseReg; + MV_U32 baseRegHigh; + MV_U32 sizeReg; +} MV_DEC_REGS; + + +/* This structure describes address decode window */ +typedef struct _mvDecWin +{ + MV_TARGET target; /* Target for addr decode window */ + MV_ADDR_WIN addrWin; /* Address window of target */ + MV_BOOL enable; /* Window enable/disable */ +}MV_DEC_WIN; + +typedef struct _mvDecWinParams +{ + MV_TARGET_ID targetId; /* Target ID field */ + MV_U8 attrib; /* Attribute field */ + MV_U32 baseAddr; /* Base address in register format */ + MV_U32 size; /* Size in register format */ +}MV_DEC_WIN_PARAMS; + +typedef struct _mvTargetAttrib +{ + MV_U8 attrib; /* chip select attributes */ + MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ + +}MV_TARGET_ATTRIB; + +/* mvCtrlEnvAddrDec API list */ +MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, + MV_DEC_REGS *pAddrDecRegs); +MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, + MV_ADDR_WIN *pAddrDecWin); + +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, + MV_DEC_WIN_PARAMS *pWinParam); + +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, + MV_DEC_WIN *pAddrDecWin); +MV_STATUS mvCtrlAttribGet(MV_TARGET target, MV_TARGET_ATTRIB *targetAttrib); +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvCtrlEnvAddrDech */ diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvAsm.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvAsm.h new file mode 100644 index 0000000..d5a7501 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvAsm.h @@ -0,0 +1,94 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAsmh +#define __INCmvCtrlEnvAsmh + +#include "pex/mvPexRegs.h" + +/* Read device ID into toReg bits 15:0 from 0xd0000000 */ +/* defines */ +#define NPXDAVI_DEV_ID_OFFS #PXDAVI_DEV_ID_OFFS +#if defined(MV_INCLUDE_PEX) +#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID));\ + mov toReg, toReg, LSR NPXDAVI_DEV_ID_OFFS /* toReg = toReg >> 16 */ +#else + #error "No Way to get Device ID" +#endif /* MV_INCLUDE_PEX */ + +/* Read Revision into toReg bits 7:0 0xd0000000*/ +#define NPXCCARI_REVID_MASK #PXCCARI_REVID_MASK + +#if defined(MV_INCLUDE_PEX) +#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, NPXCCARI_REVID_MASK /* Mask for calss ID */ +#else + #error "No Way to get Revision ID" +#endif /* MV_INCLUDE_PEX */ + +#endif /* __INCmvCtrlEnvAsmh */ diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvLib.c new file mode 100644 index 0000000..1450cf3 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvLib.c @@ -0,0 +1,1332 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#ifdef MV_INCLUDE_PEX +#include "pex/mvPex.h" +#include "ctrlEnv/sys/mvSysPex.h" +#endif +#include "cpu/mvCpu.h" + +#include "ctrlEnv/sys/mvCpuIf.h" +#include "eth/mvEth.h" +#include "ctrlEnv/sys/mvSysGbe.h" +#ifdef MV_INCLUDE_IDMA +#include "idma/mvIdma.h" +#include "ctrlEnv/sys/mvSysIdma.h" +#endif +#ifdef MV_INCLUDE_XOR +#include "xor/mvXor.h" +#include "ctrlEnv/sys/mvSysXor.h" +#endif +#ifdef MV_INCLUDE_USB +#include "usb/mvUsb.h" +#include "ctrlEnv/sys/mvSysUsb.h" +#endif +#ifdef MV_INCLUDE_SATA +#include "ctrlEnv/sys/mvSysSata.h" +#endif + +#include "device/mvDevice.h" + +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 + +#define PCCRIR_REVID_OFFS 0 /* Revision ID */ +#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) + + + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + + +/* Global paramters initial value '-1' to indicate they are uninitialized. */ +/* In case of data section is located in ROM, this value will not be able */ +/* to change. */ +MV_32 ctrlDevModel = -1; +MV_32 ctrlDevRev = -1; + +/******************************************************************************* +* mvCtrlEnvInit - Initialize Marvell controller environment. +* +* DESCRIPTION: +* This function get environment information and initialize controller +* internal/external environment. For example +* 1) MPP settings according to board MPP macros. +* NOTE: It is the user responsibility to shut down all DMA channels +* in device and disable controller sub units interrupts during +* boot process. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCtrlEnvInit(MV_VOID) +{ + MV_U32 mppGroup; + + /* Read MPP group from board level and assign to MPP register */ + for (mppGroup = 0; mppGroup < MV_MPP_MAX_GROUP; mppGroup++) + { + MV_REG_WRITE(MPP_CONTROL_REG(mppGroup), mvBoardMppGet(mppGroup)); + } + /*Only CPU0 bridge influences the system*/ + MV_REG_BIT_SET(CPU_CTRL_STAT_REG(0), CCSR_PEX0_ENABLE); + MV_REG_BIT_SET(CPU_CTRL_STAT_REG(0), CCSR_PEX1_ENABLE); + return MV_OK; +} + +/******************************************************************************* +* mvCtrlSramSizeGet - Get Marvell controller integrated SRAM size +* +* DESCRIPTION: +* This function returns Marvell controller integrated SRAM size +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlSramSizeGet(MV_VOID) +{ + return 0; +} + +/******************************************************************************* +* mvCtrlPciMaxIfGet - Get Marvell controller number of PCI interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PCI interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PCI interfaces. +* +*******************************************************************************/ +MV_U32 mvCtrlPciMaxIfGet(MV_VOID) +{ + return 0; +} + +/******************************************************************************* +* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX interfaces. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxIfGet(MV_VOID) +{ + MV_U16 model = mvCtrlModelGet(); + switch (model) { + case MV_76100_DEV_ID: + return MV_PEX_76100_MAX_IF; + case MV_6321_DEV_ID: + return MV_PEX_6321_MAX_IF; + case MV_6322_DEV_ID: + case MV_6323_DEV_ID: + return MV_PEX_6322_6323_MAX_IF; + default: + return MV_PEX_MAX_IF; + } +} + +/******************************************************************************* +* mvCtrlPciIfiMaxIfGet - Get Marvell controller number of PCI interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PCI interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PCI interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPciIfMaxIfGet(MV_VOID) +{ + return mvCtrlPexMaxIfGet(); +} +/******************************************************************************* +* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of etherent port. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of etherent port. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlEthMaxPortGet(MV_VOID) +{ + MV_U16 model = mvCtrlModelGet(); + switch (model) { + case MV_78200_DEV_ID: + return MV78200_ETH_MAX_PORTS; + case MV_6323_DEV_ID: + return MV6323_ETH_MAX_PORTS; + default: + return MV78XX0_ETH_MAX_PORTS; + } +} + +/******************************************************************************* +* mvCtrlIdmaMaxChanGet - Get Marvell controller number of IDMA channels. +* +* DESCRIPTION: +* This function returns Marvell controller number of IDMA channels. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of IDMA channels. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlIdmaMaxChanGet(MV_VOID) +{ + return MV_IDMA_MAX_CHAN; +} + +/******************************************************************************* +* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* returns number of Marvell USB controllers. +* +*******************************************************************************/ +MV_U32 mvCtrlUsbMaxGet(void) +{ + MV_U16 model = mvCtrlModelGet(); + switch (model) { + case MV_6321_DEV_ID: + return MV6321_USB_MAX_PORTS; + case MV_6322_DEV_ID: + return MV6322_USB_MAX_PORTS; + default: + return MV_USB_MAX_PORTS; + } +} + + +#if defined(MV_INCLUDE_PEX) + +/******************************************************************************* +* mvCtrlModelGet - Get Marvell controller device model (Id) +* +* DESCRIPTION: +* This function returns 16bit describing the device model (ID) as defined +* in PCI Device and Vendor ID configuration register offset 0x0. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit desscribing Marvell controller ID +* +*******************************************************************************/ +MV_U16 mvCtrlModelGet(MV_VOID) +{ + + MV_32 tmpCtrlDevModel; + + /* Check if global variable has already been intialized */ + if (-1 == ctrlDevModel) + { +#if !defined(MV76100) && !defined(MV632X) + /* Extract device number */ + tmpCtrlDevModel = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID)); + tmpCtrlDevModel &= PXDAVI_DEV_ID_MASK; + tmpCtrlDevModel = (tmpCtrlDevModel >> PXDAVI_DEV_ID_OFFS); +#else +#if defined(MV76100) + tmpCtrlDevModel = MV_76100_DEV_ID; +#elif defined(MV6321) + tmpCtrlDevModel = MV_6321_DEV_ID; +#elif defined(MV6322) + tmpCtrlDevModel = MV_6322_DEV_ID; +#elif defined(MV6323) + tmpCtrlDevModel = MV_6323_DEV_ID; +#endif +#endif + +#ifndef MV_UBOOT + ctrlDevModel = tmpCtrlDevModel; +#endif + } + else + { + tmpCtrlDevModel = ctrlDevModel; + } + + if (MV_78XX0_ZY_DEV_ID == tmpCtrlDevModel) + { + tmpCtrlDevModel = MV_78XX0_DEV_ID; + } + + return (MV_U16)tmpCtrlDevModel; +} + +/******************************************************************************* +* mvCtrlRevGet - Get Marvell controller revision +* +* DESCRIPTION: +* This function returns 16bit describing the device revision as defined +* in PCI Class Code and Revision ID configuration register offset 0x8. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit desscribing Marvell controller revision +* +*******************************************************************************/ +MV_U8 mvCtrlRevGet(MV_VOID) +{ + + MV_32 tmpCtrlDevRev; + + /* Check if global variable has already been intialized */ + if (-1 == ctrlDevRev) + { + tmpCtrlDevRev = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID)); + tmpCtrlDevRev &= PXCCARI_REVID_MASK; + tmpCtrlDevRev = (tmpCtrlDevRev >> PXCCARI_REVID_OFFS); +#ifndef MV_UBOOT + ctrlDevRev = tmpCtrlDevRev; +#endif + } + else + { + tmpCtrlDevRev = ctrlDevRev; + } + + return (MV_U8)tmpCtrlDevRev; +} + + +#else +/******************************************************************************* +* mvCtrlModelGet - Get Marvell controller device model (Id) +* +* DESCRIPTION: +* This function returns 16bit describing the device model (ID) as defined +* in PCI Device and Vendor ID configuration register offset 0x0. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit desscribing Marvell controller ID +* +*******************************************************************************/ +MV_U16 mvCtrlModelGet(MV_VOID) +{ + MV_U32 localBusNum; + MV_U32 localDevNum; + MV_U32 pciData; + MV_32 tmpCtrlDevModel; + MV_BOOL ifPwrOn; + /* Check if global variable has already been intialized */ + /* In U-boot we are still in the flash so we skeep it */ +#ifndef MV_UBOOT + if (-1 == ctrlDevModel) + { +#endif + ifPwrOn = mvCtrlPwrClckGet(PEX_UNIT_ID, PEX_DEFAULT_IF); + if (MV_FALSE == ifPwrOn) + { + mvCtrlPwrClckSet(PEX_UNIT_ID, PEX_DEFAULT_IF, MV_TRUE); + } + /* Get PCI local bus number */ + localBusNum = mvPciLocalBusNumGet(PEX_DEFAULT_IF); + /* Get PCI local dev number */ + localDevNum = mvPciLocalDevNumGet(PEX_DEFAULT_IF); + + /* Read configuration register 0 */ + pciData=mvPciConfigRead(PEX_DEFAULT_IF, localBusNum, localDevNum, 0, 0); + + /* Extract device number */ + tmpCtrlDevModel = ((pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS); + if (MV_FALSE == ifPwrOn) + { + mvCtrlPwrClckSet(PEX_UNIT_ID, PEX_DEFAULT_IF, MV_FALSE); + } +#ifndef MV_UBOOT + ctrlDevModel = tmpCtrlDevModel; + } + else + { + tmpCtrlDevModel = ctrlDevModel; + } +#endif + if (MV_78XX0_ZY_DEV_ID == tmpCtrlDevModel) + { + tmpCtrlDevModel = MV_78XX0_DEV_ID; + } + + return (MV_U16)tmpCtrlDevModel; +} + +/******************************************************************************* +* mvCtrlRevGet - Get Marvell controller revision +* +* DESCRIPTION: +* This function returns 16bit describing the device revision as defined +* in PCI Class Code and Revision ID configuration register offset 0x8. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit desscribing Marvell controller revision +* +*******************************************************************************/ +MV_U8 mvCtrlRevGet(MV_VOID) +{ + MV_U32 localBusNum; + MV_U32 localDevNum; + MV_U32 pciData; + MV_32 tmpCtrlDevRev; + + /* Check if global variable has already been intialized */ + if (-1 == ctrlDevRev) + { + //MV_BOOL ifPwrOn = mvCtrlPwrClckGet(PEX_UNIT_ID, pciIf); + //if (MV_FALSE == ifPwrOn) + { + // mvCtrlPwrClckSet(PEX_UNIT_ID, PEX_DEFAULT_IF, MV_TRUE); + } + /* Get PCI local bus number */ + localBusNum = mvPciLocalBusNumGet(PEX_DEFAULT_IF); + /* Get PCI local dev number */ + localDevNum = mvPciLocalDevNumGet(PEX_DEFAULT_IF); + + /* Read configuration register 8 */ + pciData=mvPciConfigRead(PEX_DEFAULT_IF, localBusNum, localDevNum, 0, 8); + + /* Extract revision number */ + tmpCtrlDevRev = ((pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); + + ctrlDevRev = tmpCtrlDevRev; + } + //if (MV_FALSE == ifPwrOn) + //{ + // mvCtrlPwrClckSet(PEX_UNIT_ID, pciIf, MV_FALSE); + //} + } + else + { + tmpCtrlDevRev = ctrlDevRev; + } + + return (MV_U8)tmpCtrlDevRev; +} + +#endif + +/******************************************************************************* +* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision +* +* DESCRIPTION: +* This function returns 32bit value describing both Device ID and Revision +* as defined in PCI Express Device and Vendor ID Register and device revision +* as defined in PCI Express Class Code and Revision ID Register. + +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing both controller device ID and revision number +* +*******************************************************************************/ +MV_U32 mvCtrlModelRevGet(MV_VOID) +{ +#ifndef MV_UBOOT + if (-1 == ctrlDevModel) + ctrlDevModel = mvCtrlModelGet(); + return ((ctrlDevModel << 16) | mvCtrlRevGet()); +#else + return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); +#endif +} + + +/******************************************************************************* +* mvCtrlNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlNameGet(char *pNameBuff) +{ +#ifndef MV_UBOOT + if (-1 == ctrlDevModel) + ctrlDevModel = mvCtrlModelGet(); + switch(ctrlDevModel) { +#else + switch(mvCtrlModelGet()) { +#endif + case MV_78XX0_DEV_ID: + sprintf (pNameBuff, "%s", MV_78XX0_NAME); + break; + case MV_78100_DEV_ID: + sprintf (pNameBuff, "%s", MV_78100_NAME); + break; + case MV_78200_DEV_ID: + sprintf (pNameBuff, "%s", MV_78200_NAME); + break; + case MV_76100_DEV_ID: + sprintf (pNameBuff, "%s", MV_76100_NAME); + break; + case MV_6321_DEV_ID: + sprintf (pNameBuff, "%s", MV_6321_NAME); + break; + case MV_6322_DEV_ID: + sprintf (pNameBuff, "%s", MV_6322_NAME); + break; + case MV_6323_DEV_ID: + sprintf (pNameBuff, "%s", MV_6323_NAME); + break; + + default: + sprintf (pNameBuff, "Controller device ID 0x%x unknown.\n", mvCtrlModelGet()); + return MV_ERROR; + } + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlModelRevNameGet - Get Marvell controller rev name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ + +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) +{ + switch (mvCtrlModelRevGet()) + { + case MV_78XX0_Z0_ID: + mvOsSPrintf (pNameBuff, "%s", MV_78XX0_Z0_NAME); + break; + case MV_78XX0_Y0_ID: + mvOsSPrintf (pNameBuff, "%s", MV_78XX0_Y0_NAME); + break; + case MV_76100_A0_ID: + mvOsSPrintf (pNameBuff, "%s", MV_76100_A0_NAME); + break; + case MV_78100_A0_ID: + mvOsSPrintf (pNameBuff, "%s", MV_78100_A0_NAME); + break; + case MV_78200_A0_ID: + mvOsSPrintf (pNameBuff, "%s", MV_78200_A0_NAME); + break; + case MV_76100_A1_ID: + mvOsSPrintf (pNameBuff, "%s", MV_76100_A1_NAME); + break; + case MV_78100_A1_ID: + mvOsSPrintf (pNameBuff, "%s", MV_78100_A1_NAME); + break; + case MV_78200_A1_ID: + mvOsSPrintf (pNameBuff, "%s", MV_78200_A1_NAME); + break; + case MV_6321_A1_ID: + mvOsSPrintf (pNameBuff, "%s", MV_6321_A1_NAME); + break; + case MV_6322_A1_ID: + mvOsSPrintf (pNameBuff, "%s", MV_6322_A1_NAME); + break; + case MV_6323_A1_ID: + mvOsSPrintf (pNameBuff, "%s", MV_6323_A1_NAME); + break; + default: + mvCtrlNameGet(pNameBuff); + break; + } + + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlMppRegGet - return reg address of mpp group +* +* DESCRIPTION: +* +* INPUT: +* mppGroup - MPP group. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 - Register address. +* +*******************************************************************************/ +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) +{ + return MPP_CONTROL_REG(mppGroup); +} + +/******************************************************************************* +* ctrlWinOverlapTest - Test address windows for overlaping. +* +* DESCRIPTION: +* This function checks the given two address windows for overlaping. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* +* MV_TRUE if address window overlaps, MV_FALSE otherwise. +*******************************************************************************/ +MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size; + winTop2 = winBase2 + pAddrWin2->size; + + if (((winBase1 < winTop2 ) && ( winTop2 < winTop1)) || + ((winBase1 < winBase2) && (winBase2 < winTop1))) + { + return MV_TRUE; + } + else + { + return MV_FALSE; + } +} + +/******************************************************************************* +* ctrlWinWithinWinTest - Test address windows for overlaping. +* +* DESCRIPTION: +* This function checks the given win1 boundries is within +* win2 boundries. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* +* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. +*******************************************************************************/ +MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size -1; + winTop2 = winBase2 + pAddrWin2->size -1; + + if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || + ((winTop1 >= winBase2) && (winTop1 <= winTop2))) + { + return MV_TRUE; + } + else + { + return MV_FALSE; + } +} + +/******************************************************************************* +* mvCtrlTargetNameGet - Get Marvell controller target name +* +* DESCRIPTION: +* This function convert the trget enumeration to string. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Target name (const MV_8 *) +*******************************************************************************/ +const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) +{ + switch( target ) + { + case SDRAM_CS0: + return "SDRAM_CS0...."; + case SDRAM_CS1: + return "SDRAM_CS1...."; + case SDRAM_CS2: + return "SDRAM_CS2...."; + case SDRAM_CS3: + return "SDRAM_CS3...."; + case DEVICE_CS0: + return "DEVICE_CS0..."; + case DEVICE_CS1: + return "DEVICE_CS1..."; + case DEVICE_CS2: + return "DEVICE_CS2..."; + case DEVICE_CS3: + return "DEVICE_CS3..."; +#if !defined (MV78XX0_Z0) + case SPI_CS: + return "DEVICE_SPI..."; +#endif + case DEV_BOOCS: + return "DEV_BOOCS...."; + case PCI0_IO: + return "PEX0_IO......"; + case PCI0_MEM0: + return "PEX0_MEM0...."; + case PCI1_IO: + return "PEX1_IO......"; + case PCI1_MEM0: + return "PEX1_MEM0...."; + case PCI2_IO: + return "PEX2_IO......"; + case PCI2_MEM0: + return "PEX2_MEM0...."; + case PCI3_IO: + return "PEX3_IO......"; + case PCI3_MEM0: + return "PEX3_MEM0...."; + case PCI4_IO: + return "PEX4_IO......"; + case PCI4_MEM0: + return "PEX4_MEM0...."; + case PCI5_IO: + return "PEX5_IO......"; + case PCI5_MEM0: + return "PEX5_MEM0...."; + case PCI6_IO: + return "PEX6_IO......"; + case PCI6_MEM0: + return "PEX6_MEM0...."; + case PCI7_IO: + return "PEX7_IO......"; + case PCI7_MEM0: + return "PEX7_MEM0...."; + case CRYPT_ENG: + return "CRYPT_ENG...."; + case INTER_REGS: + return "INTER_REGS..."; + case USB_IF: + return "USB_IF......."; + default: + return "target unknown"; + } +} + +/******************************************************************************* +* mvCtrlAddrDecShow - Print the Controller units address decode map. +* +* DESCRIPTION: +* This function the Controller units address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCtrlAddrDecShow(MV_VOID) +{ + mvCpuIfAddrDecShow(whoAmI()); +#ifdef MV_INCLUDE_PEX + mvPexAddrDecShow(); +#endif +#ifdef MV_INCLUDE_IDMA + mvDmaAddrDecShow(); +#endif + mvEthAddrDecShow(); +#ifdef MV_INCLUDE_XOR + mvXorAddrDecShow(); +#endif +#ifdef MV_INCLUDE_SATA + mvSataAddrDecShow(); +#endif +#ifdef MV_INCLUDE_USB + mvUsbAddrDecShow(); +#endif +} + +/******************************************************************************* +* ctrlSizeToReg - Extract size value for register assignment. +* +* DESCRIPTION: +* Address decode size parameter must be programed from LSB to MSB as +* sequence of 1's followed by sequence of 0's. The number of 1's +* specifies the size of the window in 64 KB granularity (e.g. a +* value of 0x00ff specifies 256x64k = 16 MB). +* This function extract the size value from the size parameter according +* to given aligment paramter. For example for size 0x1000000 (16MB) and +* aligment 0x10000 (64KB) the function will return 0x00FF. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size register value correspond to size parameter. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) +{ + MV_U32 retVal; + + /* Check size parameter alignment */ + if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); + return -1; + } + + /* Take out the "alignment" portion out of the size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + /* and size is 0x1000000 (16MB) for example */ + while(alignment & 1) /* Check that alignmet LSB is set */ + { + size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ + alignment = (alignment >> 1); + } + + /* If after the alignment first '0' was met we still have '1' in */ + /* it then aligment is invalid (not power of 2) */ + if (alignment) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", + (MV_U32)alignment)); + return -1; + } + + /* Now the size is shifted right according to aligment: 0x0100 */ + size--; /* Now the size is a sequance of '1': 0x00ff */ + + retVal = size ; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + while(size & 1) /* Check that LSB is set */ + { + size = (size >> 1); /* If LSB is set, move one bit to the right */ + } + + if (size) /* Sequance of 1's is over. Check that we have no other 1's */ + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", + size)); + return -1; + } + + return retVal; + +} + +/******************************************************************************* +* ctrlRegToSize - Extract size value from register value. +* +* DESCRIPTION: +* This function extract a size value from the register size parameter +* according to given aligment paramter. For example for register size +* value 0xff and aligment 0x10000 the function will return 0x01000000. +* +* INPUT: +* regSize - Size as in register format. See ctrlSizeToReg. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) +{ + MV_U32 temp; + if (0 == regSize) + { + return 0; + } + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + temp = regSize; /* Now the size is a sequence of '1': 0x00ff */ + + while(temp & 1) /* Check that LSB is set */ + { + temp = (temp >> 1); /* If LSB is set, move one bit to the right */ + } + + if (temp) /* Sequence of 1's is over. Check that we have no other 1's */ + { + DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", + regSize)); + return -1; + } + + + /* Check that aligment is a power of two */ + temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ + + while(temp & 1) /* Check that alignmet LSB is set */ + { + temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ + } + + /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ + /* then 'temp' is invalid (not power of 2) */ + if (temp) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", + alignment)); + return -1; + } + + regSize++; /* Now the size is 0x0100 */ + + /* Add in the "alignment" portion to the register size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + + while(alignment & 1) /* Check that alignmet LSB is set */ + { + regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ + alignment = (alignment >> 1); + } + + return regSize; +} + + +/******************************************************************************* +* ctrlSizeRegRoundUp - Round up given size +* +* DESCRIPTION: +* This function round up a given size to a size that is a power of 2. +* For example, for size parameter 0xa1000 and aligment 0x1000 the +* function will return 0x100000. For size parametr 0x200 and aligment +* 0x10000 the function will return 0x10000. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size value correspond to size in register. +*******************************************************************************/ +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) +{ + MV_U32 msbBit = 0; + MV_U32 retSize; + + /* Check if size parameter is already comply with restriction */ + if (!(-1 == ctrlSizeToReg(size, alignment))) + { + return size; + } + while(size) + { + size = (size >> 1); + msbBit++; + } + retSize = (1 << msbBit); + + if (retSize < alignment) + { + return alignment; + } + else + { + return retSize; + } +} + + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +/******************************************************************************* +* mvCtrlPwrClckSet - Set Power State for specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEX_MASK(index)); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG,PMC_PEX_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GE_MASK(index)); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GE_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATA_MASK(index)); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATA_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SE_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SE_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USB_MASK(index)); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USB_MASK(index)); + } + break; +#endif + default: + break; + } +} + +/******************************************************************************* +* mvCtrlPwrClckGet - Get Power State of specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); + MV_BOOL state = MV_TRUE; + + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (0 == (reg & PMC_PEX_UP(index))) + { + state = MV_FALSE; + } + else state = MV_TRUE; + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (0 == (reg & PMC_GE_UP(index))) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + if (0 == (reg & PMC_SATA_UP(index))) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (0 == (reg & PMC_SE_UP)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (0 == (reg & PMC_USB_UP(index))) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_XOR) || defined(MV_INCLUDE_IDMA) + case XOR_UNIT_ID: + /*check 2 bits for IDMA and XOR*/ + if ((0 == (reg & PMC_XOR_UP)) && (0 == (reg & PMC_IDMA_UP))) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if !defined(MV78XX0_Z0) + case SPI_UNIT_ID: + if (0 == (reg & PMC_DEVBUS_UP)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_TDM) + case TDM_UNIT_ID: + if (0 == (reg & PMC_TDM_UP)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif + default: + state = MV_TRUE; + break; + } + return state; +} +#else +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} +#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + +/******************************************************************************* +* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_VOID mvMPPConfigToSPI(MV_VOID) +{ +} + + +/******************************************************************************* +* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_VOID mvMPPConfigToDefault(MV_VOID) +{ +} + + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvLib.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvLib.h new file mode 100644 index 0000000..52b4b74 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvLib.h @@ -0,0 +1,163 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvLibh +#define __INCmvCtrlEnvLibh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ +#include "mvSysHwConfig.h" +#include "mvCommon.h" +#include "mvTypes.h" +#include "mvOs.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#if defined(MV78200) +#include "mv78200/mvSocUnitMap.h" +#endif +/* defines */ + +#define PCI0_IS_QUAD_X1 (MV_REG_READ(CPU_RESET_SAMPLE_L_REG) & 0x8) +#define PCI1_IS_QUAD_X1 (MV_REG_READ(CPU_RESET_SAMPLE_L_REG) & 0x10) +#if defined(MV78200) + #define IS_CPU1_ENABLED (MV_REG_READ(CPU_RESET_SAMPLE_L_REG) & (0x100000)) +#endif + +/* typedefs */ + +/* This enumerator describes the possible HW cache coherency policies the */ +/* controllers supports. */ +typedef enum _mvCachePolicy +{ + NO_COHERENCY, /* No HW cache coherency support */ + WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ + WB_COHERENCY /* HW cache coherency supported in Write Back policy */ +}MV_CACHE_POLICY; + +/* The swapping is referred to a 64-bit words (as this is the controller */ +/* internal data path width). This enumerator describes the possible */ +/* data swap types. Below is an example of the data 0x0011223344556677 */ +typedef enum _mvSwapType +{ + MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ + MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ + MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ + MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ + SWAP_TYPE_MAX /* Delimiter for this enumerator */ +}MV_SWAP_TYPE; + +/* This structure describes access rights for Access protection windows */ +/* that can be found in IDMA, XOR, Ethernet etc. */ +/* Note that the permission enumerator coresponds to its register format. */ +/* For example, Read only premission is presented as "1" in register field. */ +typedef enum _mvAccessRights +{ + NO_ACCESS_ALLOWED = 0, /* No access allowed */ + READ_ONLY = 1, /* Read only permission */ + ACC_RESERVED = 2, /* Reserved access right */ + FULL_ACCESS = 3, /* Read and Write permission */ + MAX_ACC_RIGHTS +}MV_ACCESS_RIGHTS; + +/* mcspLib.h API list */ +MV_STATUS mvCtrlEnvInit(MV_VOID); +MV_U32 mvCtrlSramSizeGet(MV_VOID); +MV_U32 mvCtrlPciMaxIfGet(MV_VOID); +MV_U32 mvCtrlPexMaxIfGet(MV_VOID); +MV_U32 mvCtrlPciIfMaxIfGet(MV_VOID); +MV_U32 mvCtrlEthMaxPortGet(MV_VOID); +MV_U32 mvCtrlIdmaMaxChanGet(MV_VOID); +MV_U32 mvCtrlUsbMaxGet(MV_VOID); +MV_U32 mvCtrlNandSupport(MV_VOID); +MV_U16 mvCtrlModelGet(MV_VOID); +MV_U8 mvCtrlRevGet(MV_VOID); +MV_U32 mvCtrlModelRevGet(MV_VOID); +MV_STATUS mvCtrlNameGet(char *pNameBuff); +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); + +MV_VOID mvCtrlAddrDecShow(MV_VOID); +const MV_8* mvCtrlTargetNameGet( MV_TARGET ); + +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); +MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); +MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); + +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); +MV_U32 mvCtrlPexIfBaseGet(MV_U32 pexIf); +MV_VOID mvMPPConfigToSPI(MV_VOID); +MV_VOID mvMPPConfigToDefault(MV_VOID); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvCtrlEnvLibh */ diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvSpec.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvSpec.h new file mode 100644 index 0000000..c186c35 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/mvCtrlEnvSpec.h @@ -0,0 +1,532 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvSpech +#define __INCmvCtrlEnvSpech + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ +#include "mvDeviceId.h" +#include "mvSysHwConfig.h" + +#define SOC_NAME_PREFIX "MV" + +#define INTER_REGS_SIZE _1M + +#define MV78XX0_ETH_MAX_PORTS 2 +#define MV78200_ETH_MAX_PORTS 4 +#define MV6323_ETH_MAX_PORTS 3 + +#define INTERNAL_REG_BASE_DEFAULT 0xD0000000 + + +/* Define Register base adress for each unit */ + +#if defined(MV78200) + #define MV_MAX_CPU 2 + #define CPU_IF_BASE(cpu) (0x20000 + ((cpu) << 14)) +#else + #define MV_MAX_CPU 1 + #define CPU_IF_BASE(cpu) 0x20000 +#endif + +#define AHB_TO_MBUS_BASE CPU_IF_BASE + +#define DRAM_BASE 0x00000 +#define DEVICE_BUS_BASE 0x10000 + +#if defined(MV_ASMLANGUAGE) + #define PEX_IF_BASE(pexIf) 0x40000 +#else + #define PEX_IF_BASE(pexIf) (((pexIf) < 4) ? \ + (0x40000 + (pexIf) * 0x4000) : \ + (0x80000 + ((pexIf) - 4) * 0x4000)) +#endif + +#define PEX_IF_BASE0 (0x40000) +#define PEX_IF_BASE1 (0x44000) +#define PEX_IF_BASE2 (0x48000) +#define PEX_IF_BASE3 (0x4C000) +#define PEX_IF_BASE4 (0x80000) +#define PEX_IF_BASE5 (0x84000) +#define PEX_IF_BASE6 (0x88000) +#define PEX_IF_BASE7 (0x8C000) + +#define MV_ETH_VERSION 3 +#define MV_ETH_MAX_RXQ 8 +#define MV_ETH_MAX_TXQ 8 +#define MV_ETH_MAX_PORTS 4 + +#define MV_ETH_REG_BASE(port) ((((port) < 2)? 0x72000 : 0x32000) \ + + (0x4000*(port & 1))) + +#define MV_ETH_REG_BASE0 (0x72000) +#define MV_ETH_REG_BASE1 (0x76000) +#define MV_ETH_REG_BASE2 (0x32000) +#define MV_ETH_REG_BASE3 (0x36000) + + +#define INT_CTRL_BASE (0x20200+(whoAmI()*0x4000)) +#define CNTMR_BASE (0x20300+(whoAmI()*0x4000)) +#define USB_REG_BASE(dev) (0x50000 + (0x1000*(dev))) + +#define USB_REG_BASE0 (0x50000) +#define USB_REG_BASE1 (0x51000) +#define USB_REG_BASE2 (0x52000) + +#define IDMA_UNIT_BASE 0x60800 +#define XOR_UNIT_BASE(unit) 0x60900 +#define MV_XOR_REG_BASE 0x60000 + + +#define WD_BASE 0x10000 +#define TWSI_SLAVE_BASE(chanNum) (0x11000 + (0x100 * (chanNum))) + +#define GPP_BASE 0x10000 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (0x100 * (chanNum))) +#define MPP_BASE 0x10000 +#define SATA_REG_BASE 0xA0000 +#define TDM_REG_BASE 0xB0000 +/* MPP control registers offsets */ +#define MPP_CONTROL_REG(groupNum) (MPP_BASE + ((groupNum) * 4)) + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 4 +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +#ifndef MV632X +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 +#endif + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ +#define MV_MPP_MAX_GROUP 7 + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 4 + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 5 + +#define MV_SATA_MAX_CHAN 2 +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + +/* This define describes the maximum number of available XOR channels. */ +#define MV_XOR_MAX_UNIT 1 +#define MV_XOR_MAX_CHAN_PER_UNIT 2 +#define MV_XOR_MAX_CHAN 2 + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_MAX_IF 0 +#define MV_PCI_START_IF 0 + +/* This define describes the maximum number of supported PEX Interfaces */ +#define MV_DISABLE_PEX_DEVICE_BAR +#define MV_PEX_START_IF MV_PCI_MAX_IF + +/* This define describes the maximum number of supported PEX & PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) +#define MV_PEX_MAX_IF 8 +#define MV_PEX_76100_MAX_IF 5 +#define MV_PEX_6321_MAX_IF 1 +#define MV_PEX_6322_6323_MAX_IF 5 + +#define PEX_DEFAULT_IF 0 +#ifndef MV632X +#define MV_INCLUDE_PEX1 +#define MV_INCLUDE_PEX2 +#define MV_INCLUDE_PEX3 +#endif +#define PEX0_MEM PCI0_MEM0 +#define PEX1_MEM PCI1_MEM0 +#define PEX2_MEM PCI2_MEM0 +#define PEX3_MEM PCI3_MEM0 +/* This define describes the maximum number of available USB channels. */ +#define MV6321_USB_MAX_PORTS 1 +#define MV6322_USB_MAX_PORTS 2 +#define MV_USB_MAX_PORTS 3 +#define MV_USB_VERSION 1 + +/* CESA version #2: One channel, 2KB SRAM, TDMA */ +#define MV_CESA_VERSION 2 +#define MV_CESA_REG_BASE 0x9D000 +#define MV_CESA_TDMA_REG_BASE 0x90000 +#define MV_CESA_SRAM_SIZE 2*1024 + +/* main interrupt */ +#define MV_TWSI_MAX_CHAN 2 +#define TWSI_CPU_MAIN_INT_CAUSE_REG(chanNum) CPU_INT_LOW_REG(whoAmI()) +#define TWSI_CPU_MAIN_INT_BIT(chanNum) ((chanNum)?(1 << 8):(1<<4) + + +/* These macros help units to identify a target Xbar group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEV_BOOCS)) + +#define MV_TARGET_IS_PCI0(target) \ + ((target >= PCI0_IO) && (target <= PCI0_MEM0)) + +#define MV_TARGET_IS_PCI1(target) \ + ((target >= PCI1_IO) && (target <= PCI1_MEM0)) + +#define MV_TARGET_IS_PCI2(target) \ + ((target >= PCI2_IO) && (target <= PCI2_MEM0)) + +#define MV_TARGET_IS_PCI3(target) \ + ((target >= PCI3_IO) && (target <= PCI3_MEM0)) + +#define MV_TARGET_IS_PCI4(target) \ + ((target >= PCI4_IO) && (target <= PCI4_MEM0)) + +#define MV_TARGET_IS_PCI5(target) \ + ((target >= PCI5_IO) && (target <= PCI5_MEM0)) +/*No conventional PCI*/ +#define MV_TARGET_IS_PEX(target) 1 +#define MV_TARGET_IS_PCI(target) 0 + +#define MV_TARGET_IS_PCI_IO(target) \ + ((target == PCI0_IO) || (target == PCI1_IO)|| (target == PCI2_IO) || \ + (target == PCI3_IO) || (target == PCI4_IO)|| (target == PCI5_IO)) + +#define MV_TARGET_IS_AS_BOOT(target) (0) + +#if !defined(MV632X) && !defined (MV78200) +#define MV_CHANGE_BOOT_CS(target) ((target) == DEV_BOOCS)?\ + sampleAtResetTargetArray[((MV_REG_READ(CPU_RESET_SAMPLE_L_REG)\ + & MSAR_BOOTDEV_MASK) >> MSAR_BOOTDEV_OFFS)]\ + :(target) +#else +#define MV_CHANGE_BOOT_CS(target) (target) +#endif + +#if !defined(MV78XX0_Z0) +#define BOOT_TARGETS_NAME_ARRAY { \ + DEV_BOOCS, \ + SPI_CS, \ + DEV_BOOCS, \ + DEV_BOOCS, \ + TBL_TERM, \ +} +#else +#define BOOT_TARGETS_NAME_ARRAY { \ + DEV_BOOCS, \ + TBL_TERM, \ +} +#endif + +#if defined (MV_INCLUDE_PEX) + #define PCI_IF0_MEM0 PEX0_MEM + #define PCI_IF0_IO PEX0_IO +#endif + + + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* MV78XX0 Register Map Table for the Miscellaneous Registers registers offsets */ +#define GENERAL_USAGE_REGISTER_0 (0x000100E0) +#define GENERAL_USAGE_REGISTER_1 (0x000100E4) +#define GENERAL_USAGE_REGISTER_2 (0x000100E8) +#define GENERAL_USAGE_REGISTER_3 (0x000100Ec) + + +/* MV78XX0 sample @ reset registers offsets */ +/*******************************************/ +#define CPU_RESET_SAMPLE_L_REG (0x10030) +#define CPU_RESET_SAMPLE_H_REG (0x10034) +/* S@R Register low */ +#define MSAR_SYSCLCK_OFFS 5 +#define MSAR_SYSCLCK_MASK (0x7 << MSAR_SYSCLCK_OFFS) +#define MSAR_SYSCLCK_200 (0x1 << MSAR_SYSCLCK_OFFS) +#define MSAR_SYSCLCK_267 (0x2 << MSAR_SYSCLCK_OFFS) +#define MSAR_SYSCLCK_333 (0x3 << MSAR_SYSCLCK_OFFS) +#define MSAR_SYSCLCK_400 (0x4 << MSAR_SYSCLCK_OFFS) +#define MSAR_SYSCLCK_250 (0x5 << MSAR_SYSCLCK_OFFS) +#define MSAR_SYSCLCK_300 (0x6 << MSAR_SYSCLCK_OFFS) + +#define MSAR_SYSCLK2CPU_OFFS0 8 +#define MSAR_SYSCLK2CPU_MASK0 (0xF << MSAR_SYSCLK2CPU_OFFS0) +#define MSAR_SYSCLK2CPU_OFFS1 14 +#define MSAR_SYSCLK2CPU_MASK1 (0xF << MSAR_SYSCLK2CPU_OFFS1) +/* 1_5 == sysclk * 1.5 */ +#define MSAR_SYSCLK2CPU_1 (0x0 << MSAR_SYSCLK2CPU_OFFS) +#define MSAR_SYSCLK2CPU_1_5 (0x1 << MSAR_SYSCLK2CPU_OFFS) +#define MSAR_SYSCLK2CPU_2 (0x2 << MSAR_SYSCLK2CPU_OFFS) +#define MSAR_SYSCLK2CPU_2_5 (0x3 << MSAR_SYSCLK2CPU_OFFS) +#define MSAR_SYSCLK2CPU_3 (0x4 << MSAR_SYSCLK2CPU_OFFS) +#define MSAR_SYSCLK2CPU_3_5 (0x5 << MSAR_SYSCLK2CPU_OFFS) +#define MSAR_SYSCLK2CPU_4 (0x6 << MSAR_SYSCLK2CPU_OFFS) +#define MSAR_SYSCLK2CPU_4_5 (0x7 << MSAR_SYSCLK2CPU_OFFS) +#define MSAR_SYSCLK2CPU_5 (0x8 << MSAR_SYSCLK2CPU_OFFS) + +#define MSAR_CPUL2CLK_OFFS0 12 +#define MSAR_CPUL2CLK_MASK0 (0x3 << MSAR_CPUL2CLK_OFFS0) +#define MSAR_CPUL2CLK_OFFS1 18 +#define MSAR_CPUL2CLK_MASK1 (0x3 << MSAR_CPUL2CLK_OFFS1) + +#define MSAR_BOOTDEV_OFFS 23 +#define MSAR_BOOTDEV_MASK (0x3 << MSAR_BOOTDEV_OFFS) +#define MSAR_BOOTDEV_FLASH (0x0 << MSAR_BOOTDEV_OFFS) +#define MSAR_BOOTDEV_SPI (0x1 << MSAR_BOOTDEV_OFFS) +#define MSAR_BOOTDEV_DCE_NAND (0x2 << MSAR_BOOTDEV_OFFS) +#define MSAR_BOOTDEV_CE_NAND (0x3 << MSAR_BOOTDEV_OFFS) + +#define MSAR_BOOTDEV_WIDTH_OFFS 21 +#define MSAR_BOOTDEV_WIDTH_MASK (0x3 << MSAR_BOOTDEV_WIDTH_OFFS) +#define MSAR_BOOTDEV_WIDTH_32BIT (0x2 << MSAR_BOOTDEV_WIDTH_OFFS) + +#define MSAR_CPU1_EN_OFFS 20 +#define MSAR_CPU1_EN_MASK (0x1 << MSAR_CPU1_EN_OFFS) +#define MSAR_CPU1_DIS (0x0 << MSAR_CPU1_EN_OFFS) +#define MSAR_CPU1_EN (0x1 << MSAR_CPU1_EN_OFFS) + +/* S@R Register high */ +#define MSAR_TCLCK_MODE_OFFS 6 +#define MSAR_TCLCK_MODE_MASK (0x1 << MSAR_TCLCK_MODE_OFFS) +#define MSAR_TCLCK_MODE_EXT (0x0 << MSAR_TCLCK_MODE_OFFS) +#define MSAR_TCLCK_MODE_PLL (0x1 << MSAR_TCLCK_MODE_OFFS) +#define MSAR_TCLCK_OFFS 7 +#define MSAR_TCLCK_MASK (0x3 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_167 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_200 (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_DES_OFFS 9 +#define MSAR_TCLCK_DES_MASK (0x1 << MSAR_TCLCK_DES_OFFS) +#define MSAR_TCLCK_DES_167 (0x0 << MSAR_TCLCK_DES_OFFS) +#define MSAR_TCLCK_DES_200 (0x1 << MSAR_TCLCK_DES_OFFS) + +/* CPU system reset mask register */ +#define CPU_RESET_OUT_MASK_REG (CPU_IF_BASE(whoAmI())+0x108) +#define CPU_PEX_RESET_OUT_MASK_OFF 0 +#define CPU_PEX_RESET_OUT_MASK (0x1 << CPU_PEX_RESET_OUT_MASK_OFF) +#define CPU_WD_RESET_OUT_MASK_OFF 1 +#define CPU_WD_RESET_OUT_MASK (0x1 << CPU_WD_RESET_OUT_MASK_OFF) +#define CPU_SOFT_RESET_OUT_MASK_OFF 2 +#define CPU_SOFT_RESET_OUT_MASK (0x1 << CPU_SOFT_RESET_OUT_MASK_OFF) + +/* CPU soft system reset register */ +#define CPU_SOFT_RESET_OUT_REG (CPU_IF_BASE(whoAmI())+0x10C) +#define CPU_SOFT_RESET_OUT_OFF 0 +#define CPU_SOFT_RESET_OUT (0x1 << CPU_SOFT_RESET_OUT_OFF) + + +#define POWER_MNG_CTRL_REG (CPU_IF_BASE(whoAmI())+0x11C) + +#define PMC_GE_OFFS(port) ((port)+1) +#define PMC_GE_MASK(port) (1 << PMC_GE_OFFS(port)) +#define PMC_GE_UP(port) (1 << PMC_GE_OFFS(port)) + +#define PMC_PEX_OFFS(port) ((port)+5) +#define PMC_PEX_MASK(port) (1 << PMC_PEX_OFFS(port)) +#define PMC_PEX_UP(port) (1 << PMC_PEX_OFFS(port)) + +#define PMC_SATA_OFFS(port) (((port)<<1)+14) +#define PMC_SATA_MASK(port) (1 << PMC_SATA_OFFS(port)) +#define PMC_SATA_UP(port) (1 << PMC_SATA_OFFS(port)) + +#define PMC_USB_OFFS(port) ((port)+17) +#define PMC_USB_MASK(port) (1 << PMC_USB_OFFS(port)) +#define PMC_USB_UP(port) (1 << PMC_USB_OFFS(port)) + +#define PMC_IDMA_OFFS 20 +#define PMC_IDMA_MASK (1 << PMC_IDMA_OFFS) +#define PMC_IDMA_UP (1 << PMC_IDMA_OFFS) + +#define PMC_XOR_OFFS 21 +#define PMC_XOR_MASK (1 << PMC_XOR_OFFS) +#define PMC_XOR_UP (1 << PMC_XOR_OFFS) + +#define PMC_SE_OFFS 22 +#define PMC_SE_MASK (1 << PMC_SE_OFFS) +#define PMC_SE_UP (1 << PMC_SE_OFFS) + +#define PMC_DEVBUS_OFFS 23 +#define PMC_DEVBUS_MASK (1 << PMC_DEVBUS_OFFS) +#define PMC_DEVBUS_UP (1 << PMC_DEVBUS_OFFS) + +#define PMC_TDM_OFFS 24 +#define PMC_TDM_MASK (1 << PMC_TDM_OFFS) +#define PMC_TDM_UP (1 << PMC_TDM_OFFS) + + + +/* typedefs */ + +#ifndef MV_ASMLANGUAGE + +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ + +typedef enum _mvTarget +{ + TBL_TERM=-1, /* Invalid Target*/ + SDRAM_CS0, /* 0 SDRAM chip select 0 */ + SDRAM_CS1, /* 1 SDRAM chip select 1 */ + SDRAM_CS2, /* 2 SDRAM chip select 2 */ + SDRAM_CS3, /* 3 SDRAM chip select 3 */ + DEVICE_CS0, /* 4 Device chip select 0 */ + DEVICE_CS1, /* 5 Device chip select 1 */ + DEVICE_CS2, /* 6 Device chip select 2 */ + DEVICE_CS3, /* 7 Device chip select 3 */ + DEV_BOOCS, /* 8 Boot device chip select */ +#if !defined(MV78XX0_Z0) + SPI_CS, /* x SPI device chip select */ +#endif + PCI0_IO, /* 9 PCI 0 IO */ + PCI0_MEM0, /* 10 PCI 0 memory 0 */ + PCI1_IO, /* 11 PCI 1 IO */ + PCI1_MEM0, /* 12 PCI 1 memory 0 */ + PCI2_IO, /* 13 PCI 2 IO */ + PCI2_MEM0, /* 14 PCI 2 memory 0 */ + PCI3_IO, /* 15 PCI 3 IO */ + PCI3_MEM0, /* 16 PCI 3 memory 0 */ + PCI4_IO, /* 17 PCI 4 IO */ + PCI4_MEM0, /* 18 PCI 4 memory 0 */ + PCI5_IO, /* 19 PCI 4 IO */ + PCI5_MEM0, /* 20 PCI 4 memory 0 */ + PCI6_IO, /* 21 PCI 4 IO */ + PCI6_MEM0, /* 22 PCI 4 memory 0 */ + PCI7_IO, /* 23 PCI 4 IO */ + PCI7_MEM0, /* 24 PCI 4 memory 0 */ + CRYPT_ENG, /* 25 Crypto Engine - map to bar 4 without remap */ + INTER_REGS, /* 26 Internal registers */ + MAX_TARGETS, + USB_IF, /* USB interface. Note: This is a logic target! */ +}MV_TARGET; + +#define SDRAM_CS(dramScNum) (SDRAM_CS0 + dramScNum) +#define DEVICE_CS(devNum) (DEVICE_CS0 + devNum) +#define PCI_IO(pciIf) (PCI0_IO + (2 * pciIf)) +#define PCI_MEM(pciIf, memNum) (PCI0_MEM0 + (2 * pciIf)) +/* convert device number to its target number */ +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0, + DEV_TARGET_ID = 1, + PCI0_TARGET_ID = 4, + PCI1_TARGET_ID = 8, + CRYPT_TARGET_ID =9, + MAX_TARGET_ID +}MV_TARGET_ID; + + +/* This enumerator describes the Marvell controller possible devices that */ +/* can be connected to its device interface. */ +typedef enum _mvDevice +{ + DEV_CS0, /* Device connected to dev CS[0] */ + DEV_CS1, /* Device connected to dev CS[1] */ + DEV_CS2, /* Device connected to dev CS[2] */ + DEV_CS3, /* Device connected to dev CS[3] */ + BOOT_CS, /* Device connected to boot CS */ + MV_DEV_MAX_CS +}MV_DEVICE; + +/* This enumerator defines the Marvell Units ID */ +typedef enum _mvUnitId +{ + DRAM_UNIT_ID, + PEX_UNIT_ID, + PCI_UNIT_ID, + ETH_GIG_UNIT_ID, + ETH_UNM_UNIT_ID, + USB_UNIT_ID, + IDMA_UNIT_ID, + XOR_UNIT_ID, + SATA_UNIT_ID, + TDM_UNIT_ID, + UART_UNIT_ID, + CESA_UNIT_ID, +#if !defined(MV78XX0_Z0) + SPI_UNIT_ID, +#endif + MAX_UNITS_ID, +}MV_UNIT_ID; + +#endif /* MV_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvCtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbus.c b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbus.c new file mode 100644 index 0000000..537dd95 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbus.c @@ -0,0 +1,894 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#undef MV_DEBUG +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* typedefs */ + + +/* CPU address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _ahbToMbusRemapRegOffs +{ + MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ + MV_U32 highRegOffs; /* High 32 bit remap register offset */ +}AHB_TO_MBUS_REMAP_REG_OFFS; + +/* locals */ +static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 cpu, + MV_U32 winNum, + AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); + +/******************************************************************************* +* mvAhbToMbusInit - Initialize AHB To Mbus Address Map ! +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK always. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusInit(MV_VOID) +{ + return MV_OK; + +} + +/******************************************************************************* +* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* This function sets +* address window, also known as address decode window. +* A new address decode window is set for specified winNum address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the winNum window, allowing CPU to access +* the winNum window. +* +* INPUT: +* winNum - Windows number. +* pAddrDecWin - CPU winNum window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU winNum window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinSet(MV_U32 cpu, MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttribs; + MV_DEC_REGS decRegs; + + /* Parameter checking */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid cpu %d\n", cpu); + return MV_NOT_SUPPORTED; + } + + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + + /* read base register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(cpu, winNum)); + } + else + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG(cpu)); + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read control register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(cpu, winNum)); + } + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + /* enable\Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + decRegs.sizeReg |= ATMWCR_WIN_ENABLE; + } + else + { + decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; + decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; + decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; + + /* for the safe side we disable the window before writing the new + values */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + mvAhbToMbusWinEnable(cpu, winNum,MV_FALSE); + } + + /* 3) Write to address decode Base Address Register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(cpu, winNum), decRegs.baseReg); + } + else + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG(cpu), decRegs.baseReg); + } + + + /* Internal register space have no size */ + /* register. Do not perform size register assigment for those targets */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + /* Write to address decode Size Register */ + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(cpu, winNum), decRegs.sizeReg); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* Get the CPU peripheral winNum address window. +* +* INPUT: +* cpu - CPU id +* winNum - Peripheral winNum enumerator +* +* OUTPUT: +* pAddrDecWin - CPU winNum window information data structure. +* +* RETURN: +* MV_OK if winNum exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinGet(MV_U32 cpu, MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid cpu %d\n", cpu); + return MV_NOT_SUPPORTED; + } + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal register space size have no size register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(cpu, winNum)); + } + else + { + decRegs.sizeReg = 0; + } + + /* Read base and size */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(cpu, winNum)); + } + else + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG(cpu)); + } + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + { + pAddrDecWin->addrWin.size = INTER_REGS_SIZE; + pAddrDecWin->target = INTER_REGS; + pAddrDecWin->enable = MV_TRUE; + + return MV_OK; + } + + if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + if (-1 == pAddrDecWin->addrWin.size) + { + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> + ATMWCR_WIN_ATTR_OFFS; + targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> + ATMWCR_WIN_TARGET_OFFS; + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinTargetGet(MV_U32 cpu, MV_TARGET target) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + /* Parameter checking */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: ERR. Invalid cpu %d\n", cpu); + return MV_NOT_SUPPORTED; + } + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + if (INTER_REGS == target) + { + return MV_AHB_TO_MBUS_INTREG_WIN; + } + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) + { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(cpu,winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail, win %d\n", winNum); + return 0xffffffff; + } + + if (decWin.enable == MV_TRUE) + { + if (decWin.target == target) + { + return winNum; + } + } + } + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvAhbToMbusWinAvailGet - Get First Available window number. +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinAvailGet(MV_U32 cpu) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvAhbToMbusWinAvailGet: ERR. Invalid cpu %d\n", cpu); + return MV_NOT_SUPPORTED; + } + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) + { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(cpu, winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + } + + if (decWin.enable == MV_FALSE) + { + return winNum; + } + } + + return 0xFFFFFFFF; +} + + +/******************************************************************************* +* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* cpu - CPU id +* winNum - Peripheral winNum enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other winNum window. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinEnable(MV_U32 cpu, MV_U32 winNum, MV_BOOL enable) +{ + + /* Parameter checking */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid cpu %d\n", cpu); + return MV_NOT_SUPPORTED; + } + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal registers bar can't be disable or enabled */ + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + { + return (enable ? MV_OK : MV_ERROR); + } + + if (enable == MV_TRUE) + { + /* enable the window */ + MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(cpu, winNum), ATMWCR_WIN_ENABLE); + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(cpu, winNum), ATMWCR_WIN_ENABLE); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvAhbToMbusWinRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* After a CPU address hits one of PCI address decode windows there is an +* option to remap the address to a different one. For example, CPU +* executes a read from PCI winNum window address 0x1200.0000. This +* can be modified so the address on the PCI bus would be 0x1400.0000 +* Using the PCI address remap mechanism. +* +* INPUT: +* cpu - CPU id +* winNum - Peripheral winNum enumerator. Must be a PCI winNum. +* pAddrDecWin - CPU winNum window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinRemap(MV_U32 cpu, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddr; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; + + MV_U32 effectiveBaseAddress=0,baseAddrValue=0,windowSizeValue=0; + + + /* Parameter checking */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid cpu %d\n", cpu); + return MV_NOT_SUPPORTED; + } + + /* Get registers offsets of given winNum */ + if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(cpu, winNum, &remapRegOffs)) + { + return 0xffffffff; + } + + /* 1) Set address remap low */ + baseAddr = pAddrWin->baseLow; + + /* Check base address aligment */ + /* + if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) + { + mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", baseAddr); + return MV_ERROR; + } + */ + + /* BaseLow[31:16] => base register [31:16] */ + baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; + + MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); + + MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); + + + baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(cpu, winNum)); + windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(cpu, winNum)); + + baseAddrValue &= ATMWBR_BASE_MASK; + windowSizeValue &=ATMWCR_WIN_SIZE_MASK; + + /* Start calculating the effective Base Address */ + effectiveBaseAddress = baseAddrValue; + + /* The effective base address will be combined from the chopped (if any) + remap value (according to the size value and remap mechanism) and the + window's base address */ + effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); + /* If the effectiveBaseAddress exceed the window boundaries return an + invalid value. */ + + if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) + { + mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); + return 0xffffffff; + } + + return effectiveBaseAddress; +} +/******************************************************************************* +* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets +* +* DESCRIPTION: +* +* INPUT: +* cpu - CPU id +* target1 - CPU Interface target 1 +* target2 - CPU Interface target 2 +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if targets are illigal, or if one of the targets is not +* associated to a valid window . +* MV_OK otherwise. +* +*******************************************************************************/ + + +MV_STATUS mvAhbToMbusWinTargetSwap(MV_U32 cpu, MV_TARGET target1,MV_TARGET target2) +{ + MV_U32 winNum1,winNum2; + MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; + MV_U32 remapBaseLow1=0,remapBaseLow2=0; + MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; + + /* Check parameters */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: ERR. Invalid cpu %d\n", cpu); + return MV_NOT_SUPPORTED; + } + + if (target1 >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); + return MV_ERROR; + } + + if (target2 >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); + return MV_ERROR; + } + + /* get window associated with this target */ + winNum1 = mvAhbToMbusWinTargetGet(cpu, target1); + if (winNum1 == 0xffffffff) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", + target1,winNum1); + return MV_ERROR; + } + + /* get window associated with this target */ + winNum2 = mvAhbToMbusWinTargetGet(cpu, target2); + if (winNum2 == 0xffffffff) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", + target2,winNum2); + return MV_ERROR; + } + + /* now Get original values of both Windows */ + if (MV_OK != mvAhbToMbusWinGet(cpu, winNum1,&winDec1)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", + winNum1); + return MV_ERROR; + } + if (MV_OK != mvAhbToMbusWinGet(cpu, winNum2,&winDec2)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", + winNum2); + return MV_ERROR; + } + + + /* disable both windows */ + if (MV_OK != mvAhbToMbusWinEnable(cpu, winNum1,MV_FALSE)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", + winNum1); + return MV_ERROR; + } + + if (MV_OK != mvAhbToMbusWinEnable(cpu, winNum2,MV_FALSE)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", + winNum2); + return MV_ERROR; + } + + /* now swap targets */ + /* first save winDec2 values */ + winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; + winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; + winDecTemp.addrWin.size = winDec2.addrWin.size; + winDecTemp.enable = winDec2.enable; + winDecTemp.target = winDec2.target; + + /* winDec2 = winDec1 */ + winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; + winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; + winDec2.addrWin.size = winDec1.addrWin.size; + winDec2.enable = winDec1.enable; + winDec2.target = winDec1.target; + + /* winDec1 = winDecTemp */ + winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; + winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; + winDec1.addrWin.size = winDecTemp.addrWin.size; + winDec1.enable = winDecTemp.enable; + winDec1.target = winDecTemp.target; + + /* now set the new values */ + mvAhbToMbusWinSet(cpu, winNum1,&winDec1); + mvAhbToMbusWinSet(cpu, winNum2,&winDec2); + + /* now we will treat the remap windows if exist */ + /* now check if one or both windows has a remap window + as well after the swap ! */ + /* if a window had a remap value differnt than the base value + before the swap , then after the swap the remap value will be + equal to the base value unless both windows has a remap windows*/ + + /* first get old values */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(cpu, winNum1,&remapRegs1)) + { + remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); + remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); + } + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(cpu, winNum2,&remapRegs2)) + { + remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); + remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); + } + + /* now do the swap */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(cpu, winNum1,&remapRegs1)) + { + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(cpu, winNum2,&remapRegs2)) + { + /* Two windows has a remap !!! so swap */ + + MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); + MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); + + MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); + MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); + } + else + { + /* remap == base */ + MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); + MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); + } + } + else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(cpu,winNum2,&remapRegs2)) + { + /* remap == base */ + MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); + MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); + } + + return MV_OK; +} + + + + +/******************************************************************************* +* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets +* +* DESCRIPTION: +* CPU to PCI address remap registers offsets are inconsecutive. +* This function returns PCI address remap registers offsets. +* +* INPUT: +* cpu - CPU id +* winNum - Address decode window number. See MV_U32 enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one. +* +*******************************************************************************/ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 cpu, MV_U32 winNum, + AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) +{ + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(cpu, winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(cpu, winNum); + + if ((pRemapRegs->lowRegOffs == 0) || (pRemapRegs->highRegOffs == 0)) + { + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", + winNum)); + return MV_NO_SUCH; + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusCpuWinCopy - Copy the Ahb2MBus registers value of CPU 0 to CPU 1. +* +* DESCRIPTION: +* This function copy CPU 0 address decode map to CPU 1. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#if defined(MV78XX0) && defined(MV78200) +MV_VOID mvAhbToMbusCpuWinCopy(MV_VOID) +{ + MV_U32 winNum; + + for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) + { + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(1, winNum), + MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(0, winNum))); + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(1, winNum), + MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(0, winNum))); + /* We have remap register only for win [7..0] */ + if (winNum != MAX_AHB_TO_MBUS_REMAP_WINS) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(1, winNum), + MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(0, winNum))); + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(1, winNum), + MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(0, winNum))); + } + } + else + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG(1), + MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG(0))); + } + } +} +#endif +/******************************************************************************* +* mvAhbToMbusAddDecShow - Print the Ahb to MBus bridge address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* cpu - CPU id +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvAhbToMbusAddDecShow(MV_U32 cpu) +{ + MV_AHB_TO_MBUS_DEC_WIN win; + MV_U32 winNum; + /* Check parameters */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvAhbToMbusAddDecShow: ERR. Invalid cpu %d\n", cpu); + return; + } + + mvOsOutput( "\n" ); + mvOsOutput( "CPU %d, AHB To MBUS Bridge:\n", cpu); + mvOsOutput( "-------------------\n" ); + + for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) + { + memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); + + mvOsOutput( "win%d - ", winNum ); + + if( mvAhbToMbusWinGet(cpu, winNum, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbus.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbus.h new file mode 100644 index 0000000..79bb21d --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbus.h @@ -0,0 +1,99 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbush +#define __INCmvAhbToMbush + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* defines */ + + +typedef struct _mvAhbtoMbusDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_AHB_TO_MBUS_DEC_WIN; + +/* mvAhbToMbus.h API list */ + +MV_STATUS mvAhbToMbusInit(MV_VOID); +MV_STATUS mvAhbToMbusWinSet(MV_U32 cpu, MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinGet(MV_U32 cpu, MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinEnable(MV_U32 cpu, MV_U32 winNum,MV_BOOL enable); +MV_U32 mvAhbToMbusWinRemap(MV_U32 cpu, MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); +MV_U32 mvAhbToMbusWinTargetGet(MV_U32 cpu, MV_TARGET target); +MV_U32 mvAhbToMbusWinAvailGet(MV_U32 cpu); +MV_STATUS mvAhbToMbusWinTargetSwap(MV_U32 cpu, MV_TARGET target1,MV_TARGET target2); +MV_VOID mvAhbToMbusAddDecShow(MV_U32 cpu); +#if defined(MV78XX0) && defined(MV78200) +MV_VOID mvAhbToMbusCpuWinCopy(MV_VOID); +#endif +#endif /* __INCmvAhbToMbush */ diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbusConfig.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbusConfig.h new file mode 100644 index 0000000..c54906a --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbusConfig.h @@ -0,0 +1,74 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbusConfigh +#define __INCmvAhbToMbusConfigh + +#include "mvSysHwConfig.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" + + + +#endif /* __INCmvAhbToMbusConfigh */ diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbusRegs.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbusRegs.h new file mode 100644 index 0000000..f046929 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvAhbToMbusRegs.h @@ -0,0 +1,156 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbusRegsh +#define __INCmvAhbToMbusRegsh + +/******************************/ +/* ARM Address Map Registers */ +/******************************/ + +#define MAX_AHB_TO_MBUS_WINS 15 +#define MAX_AHB_TO_MBUS_REMAP_WINS 8 +#define MV_AHB_TO_MBUS_INTREG_WIN 14 + + +#define AHB_TO_MBUS_WIN_CTRL_REG(cpu, winNum) (((winNum) < 8)? \ + (AHB_TO_MBUS_BASE(cpu) + (winNum)*0x10): \ + (AHB_TO_MBUS_BASE(cpu) + 0x900 + ((winNum)-8)*0x10)) + +#define AHB_TO_MBUS_WIN_BASE_REG(cpu, winNum) (((winNum) < 8)? \ + (AHB_TO_MBUS_BASE(cpu) + 0x4 + (winNum)*0x10): \ + (AHB_TO_MBUS_BASE(cpu) + 0x904 + ((winNum)-8)*0x10)) + +#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(cpu, winNum) (((winNum) < 8)? \ + (AHB_TO_MBUS_BASE(cpu) + 0x8 + (winNum)*0x10): \ + (0)) + +#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(cpu, winNum) (((winNum) < 8)? \ + (AHB_TO_MBUS_BASE(cpu) + 0xC + (winNum)*0x10): \ + (0)) + +#define AHB_TO_MBUS_WIN_INTEREG_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x80) + +/* Window Control Register */ +/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ +#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ + +#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated + with this window*/ +#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) + +#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes + Associated with this window */ +#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) + + +/* +Used with the Base register to set the address window size and location +Must be programed from LSB to MSB as sequence of 1’s followed +by sequence of 0’s. The number of 1’s specifies the size of the window +in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). + +NOTE: A value of 0x0 specifies 64KB size. +*/ +#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ +#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) +#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 + +/* Window Base Register */ +/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ + +/* +Used with the size field to set the address window size and location. +Corresponds to transaction address[31:16] +*/ +#define ATMWBR_BASE_OFFS 16 /* Base Address */ +#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) +#define ATMWBR_BASE_ALIGNMENT 0x10000 + +/* Window Remap Low Register */ +/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ + +/* +Used with the size field to specifies address bits[31:0] to be driven to +the target interface.: +target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) +*/ +#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ +#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) +#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 + +/* Window Remap High Register */ +/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ + +/* +Specifies address bits[63:32] to be driven to the target interface. +target_addr[63:32] = (RemapHigh[31:0] +*/ +#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ +#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) + + +#endif /* __INCmvAhbToMbusRegsh */ + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIf.c b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIf.c new file mode 100644 index 0000000..fcfb304 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIf.c @@ -0,0 +1,1140 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/sys/mvSysDram.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#ifdef MV78200 +#include "mv78200/mvSocUnitMap.h" +#endif +/*#define MV_DEBUG*/ +/* defines */ + +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* typedefs */ +/* CPU address decode registers offsets are inconsecutive. This struct */ +/* describes address decode register offsets */ +typedef struct _cpuDecRegOffs +{ + MV_U32 baseRegOffs; /* Base address register offset. */ + MV_U32 sizeRegOffs; /* Size address register offset. */ + /* Used as size itself for windows with no size */ + /* registers (e.g. internal registers) */ +}CPU_DEC_REG_OFFS; + +/* CPU address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _cpuRemapRegOffs +{ + MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ + MV_U32 highRegOffs; /* High 32 bit remap register offset */ +}CPU_REMAP_REG_OFFS; + +#if defined (MV_BRIDGE_SYNC_REORDER) +MV_U32 *mvUncachedParam = NULL; +#endif + +/* locals */ + +/* CPU address decode table. Note that table entry number must match its */ +/* target enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* target which is represent by DEVICE_CS0 enumerator (4). */ + + +/* locals */ +/* static functions */ +static MV_BOOL cpuTargetWinOverlap(MV_U32 cpu, MV_TARGET target, MV_ADDR_WIN *pAddrWin); +#ifdef MV_INCLUDE_MONT_EXT +MV_STATUS mvBoardSpecWinMapOverride(MV_VOID); +#endif +MV_TARGET sampleAtResetTargetArray[] = BOOT_TARGETS_NAME_ARRAY; +/******************************************************************************* +* mvCpuIfInit - Initialize Controller CPU interface +* +* DESCRIPTION: +* This function initialize Controller CPU interface: +* 1. Set CPU interface configuration registers. +* 2. Set CPU master Pizza arbiter control according to static +* configuration described in configuration file. +* 3. Opens CPU address decode windows. DRAM windows are assumed to be +* already set (auto detection). +* +* INPUT: +* cpu - CPU id +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCpuIfInitForCpu(MV_U32 cpu, MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + MV_U32 regVal; + MV_TARGET target; + MV_ADDR_WIN addrWin; + MV_CPU_DEC_WIN *winMap = cpuAddrWinMap; + + if (cpuAddrWinMap == NULL) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); + return MV_ERROR; + } + + /* Set ARM Configuration register */ + regVal = MV_REG_READ(CPU_CONFIG_REG(cpu)); + regVal &= ~CPU_CONFIG_DEFAULT_MASK; + regVal |= CPU_CONFIG_DEFAULT; + + + MV_REG_WRITE(CPU_CONFIG_REG(cpu),regVal); + + /* Set ARM Control and Status register */ + regVal = MV_REG_READ(CPU_CTRL_STAT_REG(cpu)); + regVal &= ~CPU_CTRL_STAT_DEFAULT_MASK; + regVal |= CPU_CTRL_STAT_DEFAULT; + MV_REG_WRITE(CPU_CTRL_STAT_REG(cpu),regVal); + + + /* First disable all CPU target windows */ + for (target = 0; winMap[target].enable != TBL_TERM; target++) + { + if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) + { + continue; + } + +#ifdef MV_MEM_OVER_PEX_WA + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + { + continue; + } +#endif + mvCpuIfTargetWinEnableForCpu(cpu, MV_CHANGE_BOOT_CS(target),MV_FALSE); + } + + /* Go through all targets in user table until table terminator */ + for (target = 0; winMap[target].enable != TBL_TERM; target++) + { + /* if DRAM auto sizing is used do not initialized DRAM target windows, */ + /* assuming this already has been done earlier. */ +#ifdef MV_DRAM_AUTO_SIZE + if (MV_TARGET_IS_DRAM(target)) + { + continue; + } +#endif + +#ifdef MV_MEM_OVER_PEX_WA + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + { + continue; + } +#endif + /* If the target attribute is the same as the boot device attribute */ + /* then it's stays disable */ +#if !defined(MV78XX0_Z0) +#if !defined(MV632X) && !defined (MV78200) + if (mvBoardIsBootFromSpi() && (target == SPI_CS)) + continue; +#endif +#endif + if (MV_TARGET_IS_AS_BOOT(target)) + { + continue; + } + + if((0 == winMap[target].addrWin.size) || + (DIS == winMap[target].enable)) + + { + + if (MV_OK != mvCpuIfTargetWinEnableForCpu(cpu, target, MV_FALSE)) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); + return MV_ERROR; + } + + } + else + { + if (MV_OK != mvCpuIfTargetWinSetForCpu(cpu, + target, + &winMap[target])) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + + + return MV_ERROR; + } + + addrWin.baseLow = winMap[target].addrWin.baseLow; + addrWin.baseHigh = winMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpu, winMap[target].winNum ,&addrWin)) + { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + winMap[target].winNum)); + } + } + } + return MV_OK; +} + +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + return mvCpuIfInitForCpu(whoAmI(), cpuAddrWinMap); +} + + +#if defined (MV_BRIDGE_SYNC_REORDER) +MV_STATUS mvCpuIfBridgeReorderWAInit(void) +{ + MV_ULONG tmpPhysAddress; + mvUncachedParam = mvOsIoUncachedMalloc(NULL, 4, &tmpPhysAddress, NULL); + if (mvUncachedParam == NULL) { + mvOsPrintf("Uncached memory allocation failed\n"); + return MV_ERROR; + } + return MV_OK; +} +#endif + +/******************************************************************************* +* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window +* +* DESCRIPTION: +* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) +* address window, also known as address decode window. +* A new address decode window is set for specified target address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the target window, allowing CPU to access +* the target window. +* +* INPUT: +* cpu - cpu id +* target - Peripheral target enumerator. +* pAddrDecWin - CPU target window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU target window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU target window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the target is unsupported. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinSetForCpu(MV_U32 cpu, MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 existingWinNum; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvCpuIfTargetWinSet: ERR. Invalid cpu %d\n", cpu); + return MV_ERROR; + } + + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illegal\n", target); + return MV_ERROR; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_TRUE == cpuTargetWinOverlap(cpu, target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); + return MV_BAD_PARAM; + } + + if (MV_TARGET_IS_DRAM(target)) + { + /* copy relevant data to MV_DRAM_DEC_WIN structure */ + addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; + addrDecWin.enable = pAddrDecWin->enable; + + if (MV_OK != mvDramIfWinSet(cpu,target,&addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); + return MV_ERROR; + } + + } + else + { + /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ + decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + decWin.addrWin.size = pAddrDecWin->addrWin.size; + decWin.enable = pAddrDecWin->enable; + decWin.target = target; + + existingWinNum = mvAhbToMbusWinTargetGet(cpu, target); + + /* check if there is already another Window configured + for this target */ + if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& + (existingWinNum != pAddrDecWin->winNum)) + { + /* if we want to enable the new winow number + passed by the user , then the old one should + be disabled */ + if (MV_TRUE == pAddrDecWin->enable) + { + /* be sure it is disabled */ + mvAhbToMbusWinEnable(cpu, existingWinNum , MV_FALSE); + } + } + + if (mvAhbToMbusWinSet(cpu, pAddrDecWin->winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); + return MV_ERROR; + } + } + + return MV_OK; +} + +MV_STATUS mvCpuIfTargetWinSet( MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + return mvCpuIfTargetWinSetForCpu(whoAmI(), target, pAddrDecWin); +} + +/******************************************************************************* +* mvCpuIfTargetWinGetForCpu - Get CPU-to-peripheral target address window +* +* DESCRIPTION: +* Get the CPU peripheral target address window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* pAddrDecWin - CPU target window information data structure. +* +* RETURN: +* MV_OK if target exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinGetForCpu(MV_U32 cpu, MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + + MV_U32 winNum=0xffffffff; + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvCpuIfTargetWinGet: ERR. Invalid cpu %d\n", cpu); + return MV_ERROR; + } + + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); + return MV_ERROR; + } + + if (MV_TARGET_IS_DRAM(target)) + { + if (mvDramIfWinGet(cpu,target,&addrDecWin) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", + target); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; + pAddrDecWin->enable = addrDecWin.enable; + pAddrDecWin->winNum = 0xffffffff; + + } + else + { + /* get the Window number associated with this target */ + + winNum = mvAhbToMbusWinTargetGet(cpu, target); + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + return MV_NO_SUCH; + + } + + if (mvAhbToMbusWinGet(cpu, winNum , &decWin) != MV_OK) + { + mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", + __FUNCTION__, winNum); + return MV_ERROR; + + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = decWin.addrWin.size; + pAddrDecWin->enable = decWin.enable; + pAddrDecWin->winNum = winNum; + + } + + return MV_OK; +} + + +/******************************************************************************* +* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window +* +* DESCRIPTION: +* Get the CPU peripheral target address window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* pAddrDecWin - CPU target window information data structure. +* +* RETURN: +* MV_OK if target exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + return mvCpuIfTargetWinGetForCpu(whoAmI(), target, pAddrDecWin); +} + +/******************************************************************************* +* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* cpu - CPU id +* target - Peripheral target enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other target window. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinEnableForCpu(MV_U32 cpu, MV_TARGET target,MV_BOOL enable) +{ + MV_U32 winNum, temp; + MV_CPU_DEC_WIN addrDecWin; + + /* Check parameters */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvCpuIfTargetWinEnable: ERR. Invalid cpu %d\n", cpu); + return MV_ERROR; + } + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* get the window and check if it exist */ + temp = mvCpuIfTargetWinGetForCpu(cpu, target, &addrDecWin); + if (MV_NO_SUCH == temp) + { + return (enable? MV_ERROR: MV_OK); + } + else if( MV_OK != temp) + { + mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); + return MV_ERROR; + } + + + /* check overlap */ + + if (MV_TRUE == enable) + { + if (MV_TRUE == cpuTargetWinOverlap(cpu, target, &addrDecWin.addrWin)) + { + DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); + return MV_ERROR; + } + + } + + + if (MV_TARGET_IS_DRAM(target)) + { + if (mvDramIfWinEnable(cpu, target, enable) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); + return MV_ERROR; + + } + + } + else + { + /* get the Window number associated with this target */ + + winNum = mvAhbToMbusWinTargetGet(cpu, target); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + return (enable? MV_ERROR: MV_OK); + } + + if (mvAhbToMbusWinEnable(cpu, winNum, enable) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", + winNum); + return MV_ERROR; + + } + + } + + return MV_OK; +} + +MV_STATUS mvCpuIfTargetWinEnable( MV_TARGET target,MV_BOOL enable) +{ + return mvCpuIfTargetWinEnableForCpu(whoAmI(), target, enable); +} + +/******************************************************************************* +* mvCpuIfTargetWinSizeGet - Get CPU target address window size +* +* DESCRIPTION: +* Get the size of CPU-to-peripheral target window. +* +* INPUT: +* cpu - CPU id +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit size. Function also returns '0' if window is closed. +* Function returns 0xFFFFFFFF in case of an error. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinSizeGetForCpu(MV_U32 cpu, MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + MV_STATUS retVal; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvCpuIfTargetWinSizeGet: ERR. Invalid cpu %d\n", cpu); + return 0; + } + + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); + return 0; + } + + /* Get the winNum window */ + retVal = mvCpuIfTargetWinGetForCpu(cpu, target, &addrDecWin); + if (MV_NO_SUCH == retVal) + { + return 0; + } + if (MV_OK != retVal) + { + mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", + target); + return 0; + } + + /* Check if window is enabled */ + if (addrDecWin.enable == MV_TRUE) + { + return (addrDecWin.addrWin.size); + } + else + { + return 0; /* Window disabled. return 0 */ + } +} + +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) +{ + return mvCpuIfTargetWinSizeGetForCpu(whoAmI(), target); +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target low base address. +* +* INPUT: +* cpu - CPU id +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit low base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseLowGetForCpu(MV_U32 cpu, MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: ERR. Invalid cpu %d\n", cpu); + return 0xffffffff; + } + + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGetForCpu(cpu, target, &addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", + target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + { + return 0xffffffff; + } + return (addrDecWin.addrWin.baseLow); +} + +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) +{ + return mvCpuIfTargetWinBaseLowGetForCpu(whoAmI(), target); +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target high base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* cpu - CPU id +* None. +* +* RETURN: +* 32bit high base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseHighGetForCpu(MV_U32 cpu, MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvCpuIfTargetWinBaseHighGet: ERR. Invalid cpu %d\n", cpu); + return 0xffffffff; + } + + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGetForCpu(cpu, target, &addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", + target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + { + return 0; + } + + return (addrDecWin.addrWin.baseHigh); +} + +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) +{ + return mvCpuIfTargetWinBaseHighGetForCpu(whoAmI(), target); +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCpuIfPciIfRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pciTarget - Peripheral target enumerator. Must be a PCI target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) +{ + if (MV_TARGET_IS_PEX(pciIfTarget)) + { + return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); + } + return 0; +} + +/******************************************************************************* +* mvCpuIfPexRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* cpu - CPU id +* pexTarget - Peripheral target enumerator. Must be a PEX target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PEX one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPexRemapForCpu(MV_U32 cpu, MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* Check parameters */ + + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvCpuIfPexRemap: ERR. Invalid cpu %d\n", cpu); + return 0xffffffff; + } + + if (!MV_TARGET_IS_PEX(pexTarget)) + { + mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); + return 0xffffffff; + } + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(cpu, pexTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + + } + + return mvAhbToMbusWinRemap(cpu, winNum, pAddrDecWin); +} + +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) +{ + return mvCpuIfPexRemapForCpu(whoAmI(), pexTarget, pAddrDecWin); +} + +#endif + + +/******************************************************************************* +* cpuTargetWinOverlap - Detect CPU address decode windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case CPU address decode +* windows overlapps. +* This function detects CPU address decode windows overlapping of a +* specified target. The function does not check the target itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* cpu - cpu Id +* target - Peripheral target enumerator. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL cpuTargetWinOverlap(MV_U32 cpu, MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 targetNum; + MV_CPU_DEC_WIN addrDecWin; + MV_STATUS status; + + + for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) + { + + /* don't check our target or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + status = mvCpuIfTargetWinGetForCpu(cpu, targetNum, &addrDecWin); + if(MV_NO_SUCH == status) + { + continue; + } + if(MV_OK != status) + { + DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); + return MV_TRUE; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + DB(mvOsPrintf("cpuTargetWinOverlap: Required target %d overlap current %d\n", + target, targetNum)); + return MV_TRUE; + } + } + return MV_FALSE; +} + + + +/******************************************************************************* +* mvCpuIfAddDecShow - Print the CPU address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ + +MV_VOID mvCpuIfAddrDecShow(MV_U32 cpu) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + if (cpu >= MV_MAX_CPU) + { + mvOsPrintf("mvCpuIfAddrDecShow: ERR. Invalid cpu %d\n", cpu); + return; + } + + mvOsOutput( "\n" ); + mvOsOutput( "CPU %d, CPU Interface\n", cpu); + mvOsOutput( "-------------\n" ); + + for( target = 0; target < MAX_TARGETS; target++ ) + { + + memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); + + mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); + mvOsOutput( "...." ); + + if( mvCpuIfTargetWinGetForCpu(cpu, target, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "base %08x, ", win.addrWin.baseLow ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + + } + else + mvOsOutput( "disable\n" ); + } + else if( mvCpuIfTargetWinGetForCpu(cpu, target, &win ) == MV_NO_SUCH ) + { + mvOsOutput( "no such\n" ); + } + + } + +} + + +/*******************************************************************************/ + +#if defined(MV78XX0) + +#define MV_PROC_STR_SIZE 50 + +void mvCpuIfGetL2EccMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_CONFIG_REG(0)); + if (regVal & BIT22) + mvOsSPrintf(buf, "L2 ECC Enabled"); + else + mvOsSPrintf(buf, "L2 ECC Disabled"); +} + +void mvCpuIfGetL2Mode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT22) + mvOsSPrintf(buf, "L2 Enabled in %s mode", + (MV_REG_READ(CPU_CTRL_STAT_REG(whoAmI())) & CCSR_L2WT) ? + "Write-Trough" : "Write-Back"); + else + mvOsSPrintf(buf, "L2 Disabled"); +} + +void mvCpuIfGetL2PrefetchMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT24) + mvOsSPrintf(buf, "L2 Prefetch Disabled"); + else + mvOsSPrintf(buf, "L2 Prefetch Enabled"); +} + +void mvCpuIfGetVfpMode(MV_8 *buf) +{ + +} + +void mvCpuIfGetWriteAllocMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT28) + mvOsSPrintf(buf, "Write Allocate Enabled"); + else + mvOsSPrintf(buf, "Write Allocate Disabled"); +} + +void mvCpuIfGetCpuStreamMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT29) + mvOsSPrintf(buf, "CPU Streaming Enabled"); + else + mvOsSPrintf(buf, "CPU Streaming Disabled"); +} + +void mvCpuIfGetDramEccMode(MV_8 *buf) +{ + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) + { + mvOsSPrintf(buf, "DRAM ECC enabled"); + } + else + { + mvOsSPrintf(buf, "DRAM ECC Disabled"); + } +} + +void mvCpuIfGetCasLatency(MV_8 *buf) +{ + MV_U32 sdramCasLat = mvDramIfCalGet(); + + mvOsSPrintf(buf, "CAS Latency %d.%d", sdramCasLat/10, sdramCasLat%10); +} +void mvCpuIfGetBranchPredictionMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT11) + mvOsSPrintf(buf, "Branch prediction Enabled"); + else + mvOsSPrintf(buf, "Branch prediction Disabled"); +} + + + +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) +{ + MV_U32 count = 0; + + MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; + MV_8 L2_En_str[MV_PROC_STR_SIZE]; + MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; + /*MV_8 VFP_mode_str[MV_PROC_STR_SIZE];*/ + MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; + MV_8 BranchPrediction_str[MV_PROC_STR_SIZE]; + MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; + MV_8 Dram_ECC_str[MV_PROC_STR_SIZE]; + MV_8 Cas_Latency_str[MV_PROC_STR_SIZE]; +#ifdef MV78200 + MV_8 Soc_Unit_Map_str[MV_PROC_STR_SIZE*3]; +#endif + mvCpuIfGetL2Mode(L2_En_str); + mvCpuIfGetL2EccMode(L2_ECC_str); + mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); + /*mvCpuIfGetVfpMode(VFP_mode_str);*/ + mvCpuIfGetWriteAllocMode(Write_Alloc_str); + mvCpuIfGetBranchPredictionMode(BranchPrediction_str); + mvCpuIfGetCpuStreamMode(Cpu_Stream_str); + mvCpuIfGetDramEccMode(Dram_ECC_str); + mvCpuIfGetCasLatency(Cas_Latency_str); +#ifdef MV78200 + mvSocUnitMapPrint(Soc_Unit_Map_str); +#endif + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); + /*count += mvOsSPrintf(buffer + count + index, "%s\n", VFP_mode_str);*/ + count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", BranchPrediction_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Dram_ECC_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Cas_Latency_str); +#ifdef MV78200 + count += mvOsSPrintf(buffer + count + index, "%s\n", Soc_Unit_Map_str); +#endif + return count; +} + +#endif + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIf.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIf.h new file mode 100644 index 0000000..fb5c945 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIf.h @@ -0,0 +1,119 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfh +#define __INCmvCpuIfh + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ctrlEnv/sys/mvCpuIfConfig.h" +#include "ddr2/mvDramIf.h" + +/* defines */ + +/* typedefs */ +/* This structure describes CPU interface address decode window */ +typedef struct _mvCpuIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_CPU_DEC_WIN; + + + +/* mvCpuIfLib.h API list */ + +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *winMap); +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); + + + +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin); +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); +MV_U32 mvCpuIfPexRemapForCpu(MV_U32 cpu, MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); +#endif +MV_STATUS mvCpuIfInitForCpu(MV_U32 cpu, MV_CPU_DEC_WIN *winMap); +MV_STATUS mvCpuIfTargetWinSetForCpu(MV_U32 cpu, MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinGetForCpu(MV_U32 cpu, MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinEnableForCpu(MV_U32 cpu, MV_TARGET target,MV_BOOL enable); +MV_U32 mvCpuIfTargetWinSizeGetForCpu(MV_U32 cpu, MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseLowGetForCpu(MV_U32 cpu, MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseHighGetForCpu(MV_U32 cpu, MV_TARGET target); + +MV_VOID mvCpuIfAddrDecShow(MV_U32 cpu); +MV_STATUS mvCpuIfBridgeReorderWAInit(void); +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); + +#endif /* __INCmvCpuIfh */ diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIfConfig.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIfConfig.h new file mode 100644 index 0000000..95c814c --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIfConfig.h @@ -0,0 +1,123 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfconfigh +#define __INCmvCpuIfConfigh + +#include "mvSysHwConfig.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" + + +/* CPU control register map */ +/* Set bits means value is about to change according to new value */ +#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | \ + CCR_AHB_ERROR_PROP_MASK) + + +#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) + +/* CPU Control and status defaults */ +#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PEX0_ENABLE | \ + CCSR_PEX1_ENABLE) + + +#define CPU_CTRL_STAT_DEFAULT (CCSR_PEX0_ENABLE | \ + CCSR_PEX1_ENABLE | \ + CCSR_L2_PARITY_PROTECTION) + +/* Ratio options for CPU to DDR */ +#define CPU_2_DDR_CLK_1x1 1 +#define CPU_2_DDR_CLK_1x2 2 +#define CPU_2_DDR_CLK_1x3 3 +#define CPU_2_DDR_CLK_1x4 4 +#define CPU_2_DDR_CLK_1x5 5 +#define CPU_2_DDR_CLK_1x6 6 +#define CPU_2_DDR_CLK_1x7 7 + +/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ +/* CPU to Mbus-L Tick Sample fields in CPU config register */ +#define TICK_DRV_1x2 0 +#define TICK_SMPL_1x2 0 +#define TICK_DRV_1x3 1 +#define TICK_SMPL_1x3 2 +#define TICK_DRV_1x4 2 +#define TICK_SMPL_1x4 2 + +#define CPU_2_AHB_DDR_CLK_1x2 \ + ((TICK_DRV_1x2 << CCR_CPU_2_AHB_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x2 << CCR_CPU_2_AHB_TICK_SMPL_OFFS)) +#define CPU_2_AHB_DDR_CLK_1x3 \ + ((TICK_DRV_1x3 << CCR_CPU_2_AHB_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x3 << CCR_CPU_2_AHB_TICK_SMPL_OFFS)) +#define CPU_2_AHB_DDR_CLK_1x4 \ + ((TICK_DRV_1x4 << CCR_CPU_2_AHB_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x4 << CCR_CPU_2_AHB_TICK_SMPL_OFFS)) + + +#define CPU_FTDLL_IC_CONFIG_DEFAULT 0x1b +#define CPU_FTDLL_DC_CONFIG_DEFAULT 0x2 + + +#endif /* __INCmvCpuIfConfigh */ diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIfRegs.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIfRegs.h new file mode 100644 index 0000000..9d5e747 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvCpuIfRegs.h @@ -0,0 +1,258 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfRegsh +#define __INCmvCpuIfRegsh + +/****************************************/ +/* ARM Control and Status Registers Map */ +/****************************************/ +#define CPU_CONFIG_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x100) +#define CPU_CTRL_STAT_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x104) +#define CPU_AHB_MBUS_CAUSE_INT_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x110) +#define CPU_AHB_MBUS_MASK_INT_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x114) +#define CPU_PM_CTRL_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x11C) +#define CPU_TIMING_ADJUST_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x120) +#define CPU_L1_RAM_TIMING0_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x128) +#define CPU_L1_RAM_TIMING1_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x12C) +#define CPU_MBUS_TIMEOUT_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x130) +#define CPU_L2_RAM_TIMING0_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x134) +#define CPU_L2_RAM_TIMING1_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x138) +#define CPU_MEMORY_PM_CTRL_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x140) +#define CPU_L2_RAM_PM_CTRL_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x144) + +/* ARM Configuration register */ +/* CPU_CONFIG_REG (CCR) */ + +/* Reset vector location */ +#define CCR_VEC_INIT_LOC_OFFS 1 +#define CCR_VEC_INIT_LOC_MASK BIT1 +/* reset at 0x00000000 */ +#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0xFFFF0000 */ +#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) + +#define CCR_AHB_ERROR_PROP_OFFS 2 +#define CCR_AHB_ERROR_PROP_MASK BIT2 +/* Erros are not propogated to AHB */ +#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) +/* Erros are propogated to AHB */ +#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) + + +#define CCR_ENDIAN_INIT_OFFS 3 +#define CCR_ENDIAN_INIT_MASK BIT3 +#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) + +#define CCR_CPU_ID_OFFS 4 +#define CCR_CPU_ID_MASK BIT4 +#define CCR_ARM_CPU_ID (0 << CCR_CPU_ID_OFFS) +#define CCR_MRVL_CPU_ID (1 << CCR_CPU_ID_OFFS) + + +#define CCR_MMU_DISABLED_OFFS 5 +#define CCR_MMU_DISABLED_MASK (1 << CCR_MMU_DISABLED_OFFS) +#define CCR_MMU_ENABLED (0 << CCR_MMU_DISABLED_OFFS) +#define CCR_MMU_DISABLED (1 << CCR_MMU_DISABLED_OFFS) + +#define CCR_CPU_2_AHB_TICK_DRV_OFFS 8 +#define CCR_CPU_2_AHB_TICK_DRV_MASK (0xF << CCR_CPU_2_AHB_TICK_DRV_OFFS) +#define CCR_CPU_2_AHB_TICK_SMPL_OFFS 12 +#define CCR_CPU_2_AHB_TICK_SMPL_MASK (0xF << CCR_CPU_2_AHB_TICK_SMPL_OFFS) +#define CCR_ICACH_PREF_BUF_ENABLE BIT16 +#define CCR_DCACH_PREF_BUF_ENABLE BIT17 + +#define CCR_AHB_ERROR_PROP_OFFS 2 +#define CCR_AHB_ERROR_PROP_MASK BIT2 +/* Erros are not propogated to AHB */ +#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) +/* Erros are propogated to AHB */ +#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) + +/* ARM Control and Status register */ +/* CPU_CTRL_STAT_REG (CCSR) */ + + +/* +This is used to block PCI express\PCI from access Socrates/Feroceon GP +while ARM boot is still in progress +*/ + +#define CCSR_PEX0_ENABLE BIT0 +#define CCSR_PEX1_ENABLE BIT1 +#define CCSR_ARM_RESET BIT3 +#define CCSR_SELF_INT BIT2 +#define CCSR_BIG_ENDIAN BIT15 +#define CCSR_L2WT BIT17 +#define CCSR_DDR_RD_WIDTH BIT18 +#define CCSR_DDR_WR_WIDTH BIT19 +#define CCSR_L2_PARITY_PROTECTION BIT24 + +/* Mbus-L to Mbus Bridge Interrupt Cause Register*/ +/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ + +#define CMMCIR_ARM_SELF_INT BIT0 +#define CMMCIR_ARM_TIMER0_INT_REQ BIT1 +#define CMMCIR_ARM_TIMER1_INT_REQ BIT2 +#define CMMCIR_ARM_WD_TIMER_INT_REQ BIT3 +#define CMMCIR_ARM_TIMER2_INT_REQ BIT6 +#define CMMCIR_ARM_TIMER3_INT_REQ BIT7 + + +/* Mbus-L to Mbus Bridge Interrupt Mask Register*/ +/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ + +#define CMMCIR_ARM_SELF_INT_OFFS 0 +#define CMMCIR_ARM_SELF_INT_MASK BIT0 +#define CMMCIR_ARM_SELF_INT_EN (1 << CMMCIR_ARM_SELF_INT_OFFS) +#define CMMCIR_ARM_SELF_INT_DIS (0 << CMMCIR_ARM_SELF_INT_OFFS) + + +#define CMMCIR_ARM_TIMER0_INT_REQ_OFFS 1 +#define CMMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 +#define CMMCIR_ARM_TIMER0_INT_REQ_EN (1 << CMMCIR_ARM_TIMER0_INT_REQ_OFFS) +#define CMMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CMMCIR_ARM_TIMER0_INT_REQ_OFFS) + +#define CMMCIR_ARM_TIMER1_INT_REQ_OFFS 2 +#define CMMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 +#define CMMCIR_ARM_TIMER1_INT_REQ_EN (1 << CMMCIR_ARM_TIMER1_INT_REQ_OFFS) +#define CMMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CMMCIR_ARM_TIMER1_INT_REQ_OFFS) + +#define CMMCIR_ARM_TIMER2_INT_REQ_OFFS 6 +#define CMMCIR_ARM_TIMER2_INT_REQ_MASK BIT6 +#define CMMCIR_ARM_TIMER2_INT_REQ_EN (1 << CMMCIR_ARM_TIMER0_INT_REQ_OFFS) +#define CMMCIR_ARM_TIMER2_INT_REQ_DIS (0 << CMMCIR_ARM_TIMER0_INT_REQ_OFFS) + +#define CMMCIR_ARM_TIMER3_INT_REQ_OFFS 7 +#define CMMCIR_ARM_TIMER3_INT_REQ_MASK BIT7 +#define CMMCIR_ARM_TIMER3_INT_REQ_EN (1 << CMMCIR_ARM_TIMER1_INT_REQ_OFFS) +#define CMMCIR_ARM_TIMER3_INT_REQ_DIS (0 << CMMCIR_ARM_TIMER1_INT_REQ_OFFS) + + +#define CMMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 +#define CMMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 +#define CMMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CMMCIR_ARM_WD_TIMER_INT_REQ_OFFS) +#define CMMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CMMCIR_ARM_WD_TIMER_INT_REQ_OFFS) + + +/*******************************************/ +/* Main Interrupt Controller Registers Map */ +/*******************************************/ + +#define CPU_INT_ERROR_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x200) +#define CPU_INT_LOW_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x204) +#define CPU_INT_HIGH_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x208) +#define CPU_INT_MASK_ERROR_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x20C) +#define CPU_INT_MASK_LOW_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x210) +#define CPU_INT_MASK_HIGH_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x214) +#define CPU_INT_SELECT_CAUSE_REG(cpu) (AHB_TO_MBUS_BASE(cpu) + 0x218) + + +/*******************************************/ +/* Power Management control */ +/*******************************************/ + +#define CPMCR_CLOCK_REALIGN BIT0 +#define CPMCR_GBE_POWER_UP(num) (BIT1 << (num)) +#define CPMCR_PEX_POWER_UP(num, bar) ((BIT5 << (bar)) << ((num)*4)) +#define CPMCR_SATA_PHY_POWER_UP(num) (BIT13 << (num*2)) +#define CPMCR_SATA_HC_POWER_UP(num) (BIT14 << (num*2)) +#define CPMCR_USB_POWER_UP(num) (BIT17 << (num)) +#define CPMCR_IDMA_POWER_UP BIT20 +#define CPMCR_XOR_POWER_UP BIT21 +#define CPMCR_CRYPTO_POWER_UP BIT22 +#define CPMCR_DEVICE_POWER_UP BIT23 + + + + +/*******************************************/ +/* ARM Doorbell Registers Map */ +/*******************************************/ + +#define CPU_HOST_TO_ARM_DRBL_REG (AHB_TO_MBUS_BASE(cpu) + 0x400) +#define CPU_HOST_TO_ARM_MASK_REG (AHB_TO_MBUS_BASE(cpu) + 0x404) +#define CPU_ARM_TO_HOST_DRBL_REG (AHB_TO_MBUS_BASE(cpu) + 0x408) +#define CPU_ARM_TO_HOST_MASK_REG (AHB_TO_MBUS_BASE(cpu) + 0x40C) + + +#ifdef MV_CPU_LE +#define CL2CR_L2_ECC_EN_OFFS 24 +#define CL2CR_L2_WT_MODE_OFFS 17 +#else +#define CL2CR_L2_ECC_EN_OFFS 0 +#define CL2CR_L2_WT_MODE_OFFS 9 +#endif + +#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) +#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) + +#define CPU_L2_CONFIG_REG 0x20104 +#define CPU_CORE1_OFFSET 0x4000 + + +#endif /* __INCmvCpuIfRegsh */ + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysCesa.c b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysCesa.c new file mode 100644 index 0000000..71270f0 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysCesa.c @@ -0,0 +1,379 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvSysCesa.h" +#include "cpu/mvCpu.h" + +#if (MV_CESA_VERSION >= 2) +MV_TARGET tdmaAddrDecPrioTable[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif + + TBL_TERM +}; + +/******************************************************************************* +* mvCesaWinGet - Get TDMA target address window. +* +* DESCRIPTION: +* Get TDMA target address window. +* +* INPUT: +* winNum - TDMA target address decode window number. +* +* OUTPUT: +* pDecWin - TDMA target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) +{ + MV_DEC_WIN_PARAMS winParam; + MV_U32 sizeReg, baseReg; + + /* Parameter checking */ + if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) + { + mvOsPrintf("%s : ERR. Invalid winNum %d\n", + __FUNCTION__, winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); + sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); + + /* Check if window is enabled */ + if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) + { + pDecWin->enable = MV_TRUE; + + /* Extract window parameters from registers */ + winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; + winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; + winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; + winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); + + /* Translate the decode window parameters to address decode struct */ + if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) + { + mvOsPrintf("Failed to translate register parameters to CESA address" \ + " decode window structure\n"); + return MV_ERROR; + } + } + else + { + pDecWin->enable = MV_FALSE; + } + return MV_OK; +} + +/******************************************************************************* +* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case TDMA address decode +* windows overlapps. +* This function detects TDMA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - if the given address window overlap current address +* decode map, +* MV_FALSE - otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_DEC_WIN addrDecWin; + + for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) + { + mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) + { + mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pDecWin->target), + pDecWin->addrWin.baseLow, + pDecWin->addrWin.size); + return MV_ERROR; + } + + if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) + { + mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* set Size, Attributes and TargetID */ + sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | + ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | + ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); + + if (pDecWin->enable == MV_TRUE) + { + sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; + } + else + { + sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; + } + + /* Update Base value */ + baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); + + MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); + MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); + + return MV_OK; +} + + +MV_STATUS mvCesaTdmaAddrDecInit (void) +{ + MV_U32 winNum; + MV_STATUS status; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_DEC_WIN cesaWin; + MV_U32 winPrioIndex = 0; + + /* First disable all address decode windows */ + for(winNum=0; winNum= 2 */ + + + + +MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) +{ + MV_U32 cesaCryptEngBase; + MV_CPU_DEC_WIN addrDecWin; + + if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) + { + mvOsPrintf("mvCesaInit: Wrong SRAM map - %d > %d\n", + sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); + return MV_FAIL; + } + + if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) + cesaCryptEngBase = addrDecWin.addrWin.baseLow; + else + { + mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); + return MV_ERROR; + } + +#if (MV_CESA_VERSION >= 2) + mvCesaTdmaAddrDecInit(); +#endif /* MV_CESA_VERSION >= 2 */ + + return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, + osHandle); + +} diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysCesa.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysCesa.h new file mode 100644 index 0000000..73bcdc5 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysCesa.h @@ -0,0 +1,100 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvSysCesa_h__ +#define __mvSysCesa_h__ + + +#include "mvCommon.h" +#include "cesa/mvCesa.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +/***************************** TDMA Registers *************************************/ + +#define MV_CESA_TDMA_ADDR_DEC_WIN 4 + +#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) + +#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) + +#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 +#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) + +#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 +#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) + +#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 +#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) + +#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 +#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) + +#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 +#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) + + +MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); + +#endif diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysDram.c b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysDram.c new file mode 100644 index 0000000..3dc7d0a --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysDram.c @@ -0,0 +1,398 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ + +#include "ddr2/mvDramIf.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvSysDram.h" + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_BOOL sdramIfWinOverlap(MV_U32 cpu, MV_TARGET target, MV_ADDR_WIN *pAddrWin); + +/******************************************************************************* +* mvDramIfWinSet - Set DRAM interface address decode window +* +* DESCRIPTION: +* This function sets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* pAddrDecWin - SDRAM address window structure. +* +* OUTPUT: +* None +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinSet(MV_U32 cpu, MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg=0,sizeReg=0; + MV_U32 baseToReg=0 , sizeToReg=0; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlaps with current enabled windows */ + if (MV_TRUE == sdramIfWinOverlap(cpu, target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + target, + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read base register*/ + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(cpu,target)); + + /* read size register */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(cpu,target)); + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; + + /* Write to address decode Base Address Register */ + baseReg &= ~SCBAR_BASE_MASK; + baseReg |= baseToReg; + + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); + return MV_BAD_PARAM; + } + + /* set size */ + sizeReg &= ~SCSR_SIZE_MASK; + /* Size is located at upper 16 bits */ + sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); + + /* enable/Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + sizeReg |= SCSR_WIN_EN; + } + else + { + sizeReg &= ~SCSR_WIN_EN; + } + + /* 3) Write to address decode Base Address Register */ + MV_REG_WRITE(SDRAM_BASE_ADDR_REG(cpu,target), baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(SDRAM_SIZE_REG(cpu,target), sizeReg); + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinGet - Get DRAM interface address decode window +* +* DESCRIPTION: +* This function gets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* pAddrDecWin - SDRAM address window structure. +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinGet(MV_U32 cpu, MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg,sizeReg; + MV_U32 sizeRegVal; + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Read base and size registers */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(cpu,target)); + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(cpu,target)); + + sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; + + pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, + SCSR_SIZE_ALIGNMENT); + + /* Check if ctrlRegToSize returned OK */ + if (-1 == pAddrDecWin->addrWin.size) + { + mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; + + pAddrDecWin->addrWin.baseHigh = 0; + + + if (sizeReg & SCSR_WIN_EN) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinEnable - Enable/Disable SDRAM address decode window +* +* DESCRIPTION: +* This function enable/Disable SDRAM address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case function parameter are invalid, MV_OK otherewise. +* +*******************************************************************************/ +MV_STATUS mvDramIfWinEnable(MV_U32 cpu, MV_TARGET target, MV_BOOL enable) +{ + MV_DRAM_DEC_WIN addrDecWin; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + if (MV_OK != mvDramIfWinGet(cpu, target, &addrDecWin)) + { + mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", + target); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == sdramIfWinOverlap(cpu, target, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode winNum window */ + MV_REG_BIT_SET(SDRAM_SIZE_REG(cpu,target), SCSR_WIN_EN); + } + else + { /* Overlap detected */ + mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", + target); + return MV_ERROR; + } + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(SDRAM_SIZE_REG(cpu, target), SCSR_WIN_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window +* +* DESCRIPTION: +* This function scan each SDRAM address decode window to test if it +* overlapps the given address windoow +* +* INPUT: +* target - SDRAM target where the function skips checking. +* pAddrDecWin - The tested address window for overlapping with +* SDRAM windows. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps any enabled address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL sdramIfWinOverlap(MV_U32 cpu, MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_TARGET targetNum; + MV_DRAM_DEC_WIN addrDecWin; + + for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) + { + /* don't check our winNum or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(cpu, targetNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf( + "sdramIfWinOverlap: Required target %d overlap winNum %d\n", + target, targetNum); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +#if defined(MV78200) +MV_VOID mvDramIfCpuWinCopy(MV_VOID) +{ + MV_U32 i; + + for(i = 0; i < MV_DRAM_MAX_CS; i++) + { + MV_REG_WRITE(SDRAM_SIZE_REG(1, i), + MV_REG_READ(SDRAM_SIZE_REG(0, i))); + MV_REG_WRITE(SDRAM_BASE_ADDR_REG(1, i), + MV_REG_READ(SDRAM_BASE_ADDR_REG(0, i))); + } +} + +MV_VOID mvDramIfSlaveCpuWinInit(MV_VOID) +{ + MV_U32 size = 0; + /* Copy the base address of DRAM CS0 CPU 0 to DRAM CS2 CPU 1 */ + MV_REG_WRITE(SDRAM_BASE_ADDR_REG(1, SDRAM_CS2), + MV_REG_READ(SDRAM_BASE_ADDR_REG(0, SDRAM_CS0))); + /* Copy the size of DRAM CS2 CPU 0 to DRAM CS2 CPU 1 */ + MV_REG_WRITE(SDRAM_SIZE_REG(1, SDRAM_CS2), + MV_REG_READ(SDRAM_SIZE_REG(0, SDRAM_CS2))); + /* Copy the base address of DRAM CS1 CPU 0 to DRAM CS3 CPU 1 */ + MV_REG_WRITE(SDRAM_BASE_ADDR_REG(1, SDRAM_CS3), + MV_REG_READ(SDRAM_BASE_ADDR_REG(0, SDRAM_CS1))); + /* Copy the size of DRAM CS3 CPU 0 to DRAM CS3 CPU 1 */ + /* In 4GB dram CS3 will be set to 0 in init phase */ + size = mvDramCsSizeGet(SDRAM_CS3); + if (size == _1G) + { + size--; + size = ((size & SCSR_SIZE_MASK) | 0xd); + MV_REG_WRITE(SDRAM_SIZE_REG(1, SDRAM_CS3),size); + } + else + { + MV_REG_WRITE(SDRAM_SIZE_REG(1, SDRAM_CS3), + MV_REG_READ(SDRAM_SIZE_REG(0, SDRAM_CS3))); + } + + /* Close CPU1 DRAM windows 0 and 1 */ + MV_REG_WRITE(SDRAM_SIZE_REG(1, SDRAM_CS0), 0); + MV_REG_WRITE(SDRAM_SIZE_REG(1, SDRAM_CS1), 0); + /* Close CPU0 DRAM windows 2 and 3 */ + MV_REG_WRITE(SDRAM_SIZE_REG(0, SDRAM_CS2), 0); + MV_REG_WRITE(SDRAM_SIZE_REG(0, SDRAM_CS3), 0); +} +#endif + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysDram.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysDram.h new file mode 100644 index 0000000..7c59e73 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysDram.h @@ -0,0 +1,82 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __sysDram +#define __sysDram + +/* This structure describes CPU interface address decode window */ +typedef struct _mvDramIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +}MV_DRAM_DEC_WIN; + +MV_STATUS mvDramIfWinSet(MV_U32 cpu, MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinGet(MV_U32 cpu, MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinEnable(MV_U32 cpu, MV_TARGET target, MV_BOOL enable); +#if defined(MV78200) +MV_VOID mvDramIfCpuWinCopy(MV_VOID); +#endif +#endif diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysGbe.c b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysGbe.c new file mode 100644 index 0000000..d5feff2 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysGbe.c @@ -0,0 +1,675 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "ctrlEnv/sys/mvSysGbe.h" +#include "cpu/mvCpu.h" + + +typedef struct _mvEthDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_ETH_DEC_WIN; + +MV_TARGET ethAddrDecPrioTap[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_DEVICE_CS0) + DEVICE_CS0, +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEVICE_CS1, +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEVICE_CS2, +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEVICE_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PCI0_IO, +#endif + TBL_TERM +}; + +static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); +static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); +static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); + + +/******************************************************************************* +* mvEthWinInit - Initialize ETH address decode windows +* +* DESCRIPTION: +* This function initialize ETH window decode unit. It set the +* default address decode windows of the unit. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if setting fail. +*******************************************************************************/ +/* Configure EthDrv memory map registes. */ +MV_STATUS mvEthWinInit (int port) +{ + MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; + MV_ETH_DEC_WIN ethWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + static MV_U32 accessProtReg = 0; + +#if (MV_ETH_VERSION <= 1) + static MV_BOOL isFirst = MV_TRUE; + + if(isFirst == MV_FALSE) + { + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); + return MV_OK; + } + isFirst = MV_FALSE; +#endif /* MV_GIGA_ETH_VERSION */ + + /* Initiate Ethernet address decode */ + + /* First disable all address decode windows */ + for(winNum=0; winNum= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + + decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); + decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; + decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; + decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; + + /* for the safe side we disable the window before writing the new + values */ + mvEthWinEnable(port, winNum, MV_FALSE); + MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); + + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + { + mvEthWinEnable(port, winNum, MV_TRUE); + } + + return MV_OK; +} + +/******************************************************************************* +* mvETHWinGet - Get dma peripheral target address window. +* +* DESCRIPTION: +* Get ETH peripheral target address window. +* +* INPUT: +* winNum - ETH to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - ETH target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); + decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; + targetAttrib.targetId = + (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvEthWinEnable - Enable/disable a ETH to target address window +* +* DESCRIPTION: +* This function enable/disable a ETH to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling ETH accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - ETH to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) +{ + MV_ETH_DEC_WIN addrDecWin; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) + { + mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + } + else + { /* Overlap detected */ + mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { /* Disable address decode target window */ + MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + } + return MV_OK; +} + +/******************************************************************************* +* mvEthWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* window number +* +*******************************************************************************/ +MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) +{ + MV_ETH_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + for (winNum=0; winNum= mvCtrlEthMaxPortGet()) + { + mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); + return MV_ERROR; + } + + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) + { + mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); + return MV_ERROR; + } + /* Read current protection register */ + protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); + + /* Clear protection window field */ + protReg &= ~(ETH_PROT_WIN_MASK(winNum)); + + /* Set new protection field value */ + protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); + + /* Write protection register back */ + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); + + return MV_OK; +} + +/******************************************************************************* +* ethWinOverlapDetect - Detect ETH address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case ETH address decode +* windows overlapps. +* This function detects ETH address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex; + MV_ETH_DEC_WIN addrDecWin; + + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); + + for (winNumIndex=0; winNumIndex= IDMA_MAX_ADDR_DEC_WIN) + { + mvOsPrintf("mvDmaWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == dmaWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvDmaWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvDmaWinSet: Error setting IDMA window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + + decRegs.baseReg = MV_REG_READ(IDMA_BASE_ADDR_REG(winNum)); + decRegs.sizeReg = MV_REG_READ(IDMA_SIZE_REG(winNum)); + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvDmaWinSet: mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + +#if defined(MV_INCLUDE_CESA) + /* See BTS Nastore #19.*/ + /* To access Tunit SRAM from IDMA use targetId = 0x5 */ + /* To access Tunit SRAM from the CPU use targetId = 0x9 */ + if(pAddrDecWin->target == CRYPT_ENG) + targetAttribs.targetId = 5; +#endif /* defined(MV_INCLUDE_CESA) */ + + /* set attributes */ + decRegs.baseReg &= ~IDMA_WIN_ATTR_MASK; + decRegs.baseReg |= targetAttribs.attrib << IDMA_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.baseReg &= ~IDMA_WIN_TARGET_MASK; + decRegs.baseReg |= targetAttribs.targetId << IDMA_WIN_TARGET_OFFS; + + /* for the safe side we disable the window before writing the new + values */ + mvDmaWinEnable(winNum,MV_FALSE); + + MV_REG_WRITE(IDMA_BASE_ADDR_REG(winNum), decRegs.baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(IDMA_SIZE_REG(winNum), decRegs.sizeReg); + + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + { + mvDmaWinEnable(winNum, MV_TRUE); + } + + return MV_OK; +} + +/******************************************************************************* +* mvDmaWinGet - Get dma peripheral target address window. +* +* DESCRIPTION: +* Get IDMA peripheral target address window. +* +* INPUT: +* winNum - IDMA to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - IDMA target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvDmaWinGet(MV_U32 winNum, MV_DMA_DEC_WIN *pAddrDecWin) +{ + + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= IDMA_MAX_ADDR_DEC_WIN) + { + mvOsPrintf("mvDmaWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(IDMA_BASE_ADDR_REG(winNum)); + decRegs.sizeReg = MV_REG_READ(IDMA_SIZE_REG(winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvDmaWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (decRegs.baseReg & IDMA_WIN_ATTR_MASK) >> IDMA_WIN_ATTR_OFFS; + targetAttrib.targetId = + (decRegs.baseReg & IDMA_WIN_TARGET_MASK) >> IDMA_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if (~(MV_REG_READ(IDMA_BASE_ADDR_ENABLE_REG)) & (IBAER_ENABLE(winNum))) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvDmaWinEnable - Enable/disable a DMA to target address window +* +* DESCRIPTION: +* This function enable/disable a DMA to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling DMA accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - IDMA to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvDmaWinEnable(MV_U32 winNum,MV_BOOL enable) +{ + MV_DMA_DEC_WIN addrDecWin; + + /* Parameter checking */ + if (winNum >= IDMA_MAX_ADDR_DEC_WIN) + { + mvOsPrintf("mvDmaWinEnable:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvDmaWinGet(winNum, &addrDecWin)) + { + mvOsPrintf("mvDmaWinEnable:ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == dmaWinOverlapDetect(winNum, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_RESET(IDMA_BASE_ADDR_ENABLE_REG, IBAER_ENABLE(winNum)); + } + else + { /* Overlap detected */ + mvOsPrintf("mvDmaWinEnable:ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { /* Disable address decode target window */ + MV_REG_BIT_SET(IDMA_BASE_ADDR_ENABLE_REG, IBAER_ENABLE(winNum)); + } + return MV_OK; +} + +/******************************************************************************* +* mvDmaWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* window number +* +*******************************************************************************/ +MV_U32 mvDmaWinTargetGet(MV_TARGET target) +{ + MV_DMA_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvDmaWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + for (winNum = 0; winNum < IDMA_MAX_ADDR_DEC_WIN ; winNum++) + { + if (mvDmaWinGet(winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvDmaWinTargetGet: mvDmaWinGet returned error\n"); + return 0xffffffff; + } + if (decWin.enable == MV_TRUE) + { + if (decWin.target == target) + { + return winNum; + } + } + } + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvDmaProtWinSet - Set access protection of IDMA to target window. +* +* DESCRIPTION: +* Each IDMA channel can be configured with access attributes for each +* of the IDMA to target windows (address decode windows). This +* function sets access attributes to a given window for the given channel. +* +* INPUTS: +* chan - IDMA channel number. See MV_DMA_CHANNEL enumerator. +* winNum - IDMA to target address decode window number. +* access - IDMA access rights. See MV_ACCESS_RIGHTS enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case window number is invalid or access right reserved. +* +*******************************************************************************/ +MV_STATUS mvDmaProtWinSet (MV_U32 chan, MV_U32 winNum, MV_ACCESS_RIGHTS access) +{ + MV_U32 protReg; + + /* Parameter checking */ + if ((chan >= MV_IDMA_MAX_CHAN) || (winNum >= IDMA_MAX_ADDR_DEC_WIN)) + { + mvOsPrintf("mvDmaProtWinSet:ERR. Invalid chan number %d\n", chan); + return MV_ERROR; + } + if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) + { + mvOsPrintf("mvDmaProtWinSet:ERR. Inv access param %d\n", access); + return MV_ERROR; + } + /* Read current protection register */ + protReg = MV_REG_READ(IDMA_ACCESS_PROTECT_REG(chan)); + + /* Clear protection window field */ + protReg &= ~(ICAPR_PROT_WIN_MASK(winNum)); + + /* Set new protection field value */ + protReg |= (access << (ICAPR_PROT_WIN_OFFS(winNum))); + + /* Write protection register back */ + MV_REG_WRITE(IDMA_ACCESS_PROTECT_REG(chan), protReg); + + return MV_OK; +} + +/******************************************************************************* +* mvDmaOverrideSet - Set DMA target window override +* +* DESCRIPTION: +* The address override feature enables additional address decoupling. +* For example, it allows the use of the same source and destination +* addresses while the source is targeted to one interface and +* destination to a second interface. +* DMA source/destination/next descriptor addresses can be override per +* address decode windows 1, 2 and 3 only. +* This function set override parameters per DMA channel. It access +* DMA control register low. +* +* INPUT: +* chan - IDMA channel number. See MV_DMA_CHANNEL enumerator. +* winNum - Override window numver. +* Note: 1) Not all windows can override. +* 2) Window '0' means disable override. +* override - Type of override. See MV_DMA_OVERRIDE enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM in case window can not perform override. +* +*******************************************************************************/ +MV_STATUS mvDmaOverrideSet(MV_U32 chan, MV_U32 winNum, MV_DMA_OVERRIDE override) +{ + MV_U32 ctrlLowReg; + + /* Parameter checking */ + if ((chan >= MV_IDMA_MAX_CHAN) || (winNum >= IDMA_MAX_OVERRIDE_WIN)) + { + mvOsPrintf("mvDmaOverrideSet:ERR. Invalid chan num %d\n", chan); + return MV_ERROR; + } + /* Read control register */ + ctrlLowReg = MV_REG_READ(IDMA_CTRL_LOW_REG(chan)); + + switch (override) + { + case (DMA_SRC_ADDR): + ctrlLowReg &= ~ICCLR_OVRRD_SRC_MASK; /* Clear SRC field */ + ctrlLowReg |= ICCLR_OVRRD_SRC_BAR(winNum); /* Set reg field */ + break; + case (DMA_DST_ADDR): + ctrlLowReg &= ~ICCLR_OVRRD_DST_MASK; /* Clear DST field */ + ctrlLowReg |= ICCLR_OVRRD_DST_BAR(winNum); /* Set reg field */ + break; + case (DMA_NEXT_DESC): + ctrlLowReg &= ~ICCLR_OVRRD_NDSC_MASK; /* Clear N_Desc field*/ + ctrlLowReg |= ICCLR_OVRRD_NDSC_BAR(winNum); /* Set reg field */ + break; + default: + { + mvOsPrintf("mvDmaOverrideSet:ERR. Inv override param%d\n",override); + return MV_BAD_PARAM; + } + } + /* Write control word back */ + MV_REG_WRITE(IDMA_CTRL_LOW_REG(chan), ctrlLowReg); + + return MV_OK; +} + +/******************************************************************************* +* mvDmaPciRemap - Set DMA remap register for PCI address windows. +* +* DESCRIPTION: +* The PCI interface supports 64-bit addressing. Four of the eight +* address windows have an upper 32-bit address register. To access the +* PCI bus with 64-bit addressing cycles (DAC cycles), this function +* assigns one (or more) of these four windows to target the PCI bus. +* The address generated on the PCI bus is composed of the window base +* address and the High Remap register. +* +* INPUT: +* winNum - IDMA to target address decode window number. Only 0 - 3. +* addrHigh - upper 32-bit address. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if window number is not between 0 and 3. +* +*******************************************************************************/ +MV_STATUS mvDmaPciRemap(MV_U32 winNum, MV_U32 addrHigh) +{ + /* Parameter checking */ + if (winNum >= IDMA_MAX_OVERRIDE_WIN) + { + mvOsPrintf("mvDmaPciRemap:ERR. Invalid window num %d\n", winNum); + return MV_BAD_PARAM; + } + + MV_REG_WRITE(IDMA_HIGH_ADDR_REMAP_REG(winNum), addrHigh); + + return MV_OK; +} + +/******************************************************************************* +* dmaWinOverlapDetect - Detect DMA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case DMA address decode +* windows overlapps. +* This function detects DMA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS dmaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex; + MV_DMA_DEC_WIN addrDecWin; + + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(IDMA_BASE_ADDR_ENABLE_REG); + + for (winNumIndex = 0; winNumIndex < IDMA_MAX_ADDR_DEC_WIN; winNumIndex++) + { + /* Do not check window itself */ + if (winNumIndex == winNum) + { + continue; + } + + /* Do not check disabled windows */ + if (baseAddrEnableReg & (IBAER_ENABLE(winNumIndex))) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvDmaWinGet(winNumIndex, &addrDecWin)) + { + DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + return MV_FALSE; +} + +/******************************************************************************* +* mvDmaAddrDecShow - Print the DMA address decode map. +* +* DESCRIPTION: +* This function print the DMA address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvDmaAddrDecShow(MV_VOID) +{ + + MV_DMA_DEC_WIN win; + int i; +#if defined (MV78200) + if (mvSocUnitIsMappedToThisCpu(IDMA) == MV_FALSE) + return; +#endif + + mvOsOutput( "\n" ); + mvOsOutput( "DMA:\n" ); + mvOsOutput( "----\n" ); + + for( i = 0; i < IDMA_MAX_ADDR_DEC_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_DMA_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvDmaWinGet( i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} +/******************************************************************************* +* mvDmaAllStop - Stop any IDMA activity. +* +* DESCRIPTION: +* This function stops any DMA activity. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvDmaAllStop(MV_VOID) +{ + MV_U32 dmaChanNum; + + for(dmaChanNum = 0; dmaChanNum < MV_IDMA_MAX_CHAN; dmaChanNum++) + { + mvDmaCommandSet(dmaChanNum, MV_STOP); + } + + return; +} + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysIdma.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysIdma.h new file mode 100644 index 0000000..e16ca6d --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysIdma.h @@ -0,0 +1,143 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvSysIdmah +#define __INCmvSysIdmah + +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* General IDMA */ +#define IDMA_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ +#define IDMA_MAX_OVERRIDE_WIN 4 /* Maximum address override windows */ + +/* IDMA Address Decoding Base and size Registers */ +#define IDMA_BASE_ADDR_REG(winNum) (0x60a00 + ((winNum) * 8)) +#define IDMA_SIZE_REG(winNum) (0x60a04 + ((winNum) * 8)) + +/* IDMA Address Decoding High Address Remap,. Note that only window 0 - 3 */ +/* has remap capabilities */ +#define IDMA_HIGH_ADDR_REMAP_REG(winNum) (0x60a60 + ((winNum) * 4)) + +/* IDMA Base Addres enable register*/ +#define IDMA_BASE_ADDR_ENABLE_REG 0x60a80 + +/* IDMA Access Protection Registers */ +#define IDMA_ACCESS_PROTECT_REG(chan) (0x60a70 + ((chan) * 4)) + /* IDMA Headers Retarget Registers */ +#define IDMA_HEADERS_RETARGET_CTRL_REG 0x60a84 +#define IDMA_HEADERS_RETARGET_BASE_REG 0x60a88 + + +/* Base Addr reg */ +#define IDMA_WIN_TARGET_OFFS 0 /* The target interface associated with window*/ +#define IDMA_WIN_TARGET_MASK (0xf << IDMA_WIN_TARGET_OFFS) +#define IDMA_WIN_ATTR_OFFS 8 /* The target attributes Associated with window*/ +#define IDMA_WIN_ATTR_MASK (0xff << IDMA_WIN_ATTR_OFFS) + +/* IDMA Base Address Enable Register (IBAER) */ +#define IBAER_ENABLE_OFFS 0 +#define IBAER_ENABLE_MASK (0xFF << IBAER_ENABLE_OFFS) +#define IBAER_ENABLE(winNum) (1 << (winNum)) + +/* IDMA Channel Access Protect Register (ICAPR)*/ +#define ICAPR_PROT_NO_ACCESS NO_ACCESS_ALLOWED +#define ICAPR_PROT_READ_ONLY READ_ONLY +#define ICAPR_PROT_FULL_ACCESS FULL_ACCESS +#define ICAPR_PROT_WIN_OFFS(winNum) (2 * (winNum)) +#define ICAPR_PROT_WIN_MASK(winNum) (0x3 << ICAPR_PROT_WIN_OFFS(winNum)) + +/* This struct describes address decode override types */ +typedef enum _mvDmaOverride +{ + DMA_SRC_ADDR, /* Override source address */ + DMA_DST_ADDR, /* Override destination address */ + DMA_NEXT_DESC /* Override next descriptor address */ +}MV_DMA_OVERRIDE; + + +typedef struct _mvDmaDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_DMA_DEC_WIN; + +MV_STATUS mvDmaInit (MV_VOID); + +MV_STATUS mvDmaWinSet(MV_U32 winNum, MV_DMA_DEC_WIN *pAddrDecWin); +MV_STATUS mvDmaWinGet(MV_U32 winNum, MV_DMA_DEC_WIN *pAddrDecWin); +MV_STATUS mvDmaWinEnable(MV_U32 winNum,MV_BOOL enable); +MV_U32 mvDmaWinTargetGet(MV_TARGET target); + +MV_STATUS mvDmaProtWinSet (MV_U32 chan, MV_U32 winNum, MV_ACCESS_RIGHTS access); +MV_STATUS mvDmaOverrideSet(MV_U32 chan, MV_U32 winNum, MV_DMA_OVERRIDE override); +MV_STATUS mvDmaPciRemap(MV_U32 winNum, MV_U32 addrHigh); + +MV_VOID mvDmaAddrDecShow(MV_VOID); +MV_VOID mvDmaAllStop(MV_VOID); + +#endif /* __INCmvSysIdmaBarh */ + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysPex.c b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysPex.c new file mode 100644 index 0000000..1be52bd --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysPex.c @@ -0,0 +1,1638 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/sys/mvSysPex.h" +#include "cpu/mvCpu.h" +#include "pex/mvPex.h" +#if defined (MV78200) +#include "mv78200/mvSocUnitMap.h" +#endif + +#define MV_DEBUG +#ifdef MV_DEBUG +#define mvOsPrintf printf +#define DB(x) x +#else +#define DB(x) +#endif + +/* locals */ +/* this structure describes the mapping between a Pex Window and a CPU target*/ +typedef struct _pexWinToTarget +{ + MV_TARGET target; + MV_BOOL enable; +}PEX_WIN_TO_TARGET; + +/* this array is a priority array that define How Pex windows should be +configured , We have only 6 Pex Windows that can be configured , but we +have morethat that CPU target windows ! the following array is a priority +array where the lowest index has the highest priotiy and the highest +index has the lowest priority of being cnfigured */ +MV_U32 pexDevBarPrioTable[] = +{ + DEVICE_CS0, + DEVICE_CS1, + DEVICE_CS2, + DEV_BOOCS, + TBL_TERM +}; + +/* PEX Wins registers offsets are inconsecutive. This struct describes WIN */ +/* register offsets and its function where its is located. */ +/* Also, PEX address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _pexWinRegInfo +{ + MV_U32 winCtrlRegOffs; + MV_U32 winBaseRegOffs; + MV_U32 winRemapLowRegOffs; + MV_U32 winRemapHighRegOffs; + +}PEX_WIN_REG_INFO; + +static MV_STATUS pexWinOverlapDetect(MV_U32 pexIf, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin); +static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, MV_U32 winNum, + PEX_WIN_REG_INFO *pWinRegInfo); +static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size); +static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf,MV_ADDR_WIN *pAddrWin); +static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf,MV_U32 barNum, + MV_ADDR_WIN *pAddrWin); +static MV_VOID mvPexDecWinShow(MV_U32 pexIf); + +/******************************************************************************* +* mvPexInit - Initialize PEX interfaces +* +* DESCRIPTION: +* +* This function is responsible of intialization of the Pex Interface , It +* configure the Pex Bars and Windows in the following manner: +* +* Assumptions : +* Bar0 is always internal registers bar +* Bar1 is always the DRAM bar +* Bar2 is always the Device bar +* +* 1) Sets the Internal registers bar base by obtaining the base from +* the CPU Interface +* 2) Sets the DRAM bar base and size by getting the base and size from +* the CPU Interface when the size is the sum of all enabled DRAM +* chip selects and the base is the base of CS0 . +* 3) Sets the Device bar base and size by getting these values from the +* CPU Interface when the base is the base of the lowest base of the +* Device chip selects, and the +* +* +* INPUT: +* +* pexIf - PEX interface number. +* +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM +* +*******************************************************************************/ +MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType) +{ + MV_U32 bar; + MV_U32 winNum,winIndex; + MV_PEX_BAR pexBar; + MV_PEX_DEC_WIN pexWin; + MV_CPU_DEC_WIN addrDecWin; + MV_TARGET target; + MV_U32 pexStartWindow; + MV_U32 pexCurrWin=0; + MV_U32 status; + /* default and expansion ROM are always configured */ + MV_U32 maxBase=0,sizeOfMaxBase=0; + MV_U32 dramSize = mvDramIfSizeGet(); + int Ix; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + /* Start with bars */ + /* First disable all PEX bars*/ + for (bar = 0; bar < PEX_MAX_BARS; bar++) + { + if (PEX_INTER_REGS_BAR != bar) + { + if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) + { + mvOsPrintf("mvPexInit: Closing all BARs failed at bar %d\n",bar); + return MV_ERROR; + } + } + } + + /* and disable all PEX target windows */ + for (winNum = 0; winNum < PEX_GRNERAL_WIN_NUM; winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) + { + mvOsPrintf("mvPexInit: Disable all windows failed at win %d\n",winNum); + return MV_ERROR; + } + } + + /* Now, go through all bars*/ + +/******************************************************************************/ +/* Internal registers bar */ +/******************************************************************************/ + + /* first get the CS attribute from the CPU Interface */ + if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) + { + mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); + return MV_ERROR; + } + + /* mvOsPrintf("mvPexInit: dramSize =%dGBYTE\n",dramSize/_1M); */ + if (dramSize > _2G) + { + pexBar.addrWin.baseHigh = 1; + } + else + { + pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + } + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexBar.addrWin.size = addrDecWin.addrWin.size; + pexBar.enable = MV_TRUE; + + if (MV_OK != mvPexBarSet(pexIf, PEX_INTER_REGS_BAR, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", PEX_INTER_REGS_BAR); + return MV_ERROR; + } + +/******************************************************************************/ +/* DRAM bar */ +/******************************************************************************/ + + bar = PEX_DRAM_BAR; + + pexBar.addrWin.size = 0; + pexBar.addrWin.baseLow = pexBar.addrWin.baseHigh = 0; + + target = mvDramIfGetFirstCS(); + + for (Ix = 0;Ix <= SDRAM_CS3; Ix++ ) + { + target = mvDramIfGetCSorder(Ix); + status = mvCpuIfTargetWinGet(target, &addrDecWin); + if((MV_NO_SUCH == status) && (target != SDRAM_CS0)) + { + continue; + } + /* first get attributes from CPU If */ + if (MV_OK != status) + { + mvOsPrintf("mvPexInit: ERR. Getting DRAM address decode window "\ + "%d from CPU interface failed\n",target - SDRAM_CS0); + return MV_ERROR; + } + + DB(mvOsPrintf("mvPexInit: target %d, size =%d MBYTE \n",target,addrDecWin.addrWin.size/_1M)); + if (addrDecWin.enable == MV_TRUE) + { + /* the base is the First DIMM on address 0 */ + if (mvDramIfGetFirstCS() == target ) + { + pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + } + + /* Accumulate bar size */ + pexBar.addrWin.size += addrDecWin.addrWin.size; + + + /* set a Pex window for this target ! + DRAM CS always will have a Pex Window , and is not a + part of the priority table */ + pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexWin.addrWin.size = addrDecWin.addrWin.size; + + /* we disable the windows at first because we are not + sure that it is witihin bar boundries */ + pexWin.enable =MV_FALSE; + pexWin.target = target; + pexWin.targetBar = bar; + + if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) + { + mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); + return MV_ERROR; + } + } + if (pexBar.addrWin.size >= _2G) + { + break; + } + } + + /* check if the size of the bar is illeggal */ + pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); + + /* check if the size and base are valid */ + if (MV_TRUE == pexBarOverlapDetect(pexIf, bar, &pexBar.addrWin)) + { + mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); + mvOsPrintf("it will be disabled\n"); + mvOsPrintf("please check Pex and CPU windows configuration\n"); + } + else + { + pexBar.enable = MV_TRUE; + + /* configure the bar */ + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + + /* after the bar was configured then we enable the Pex windows*/ + for (winNum = 0;winNum < pexCurrWin ;winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) + { + mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); + return MV_ERROR; + } + + } + } + + +/******************************************************************************/ +/* DEVICE bar */ +/******************************************************************************/ + + /* then device bar*/ + bar = PEX_DEVICE_BAR; + + /* save the starting window */ + pexStartWindow = pexCurrWin; + maxBase = 0; + if (dramSize <= _2G) + { + pexBar.addrWin.size = 0; + pexBar.addrWin.baseLow = 0xffffffff; + pexBar.addrWin.baseHigh = 0; + } + else + { + /********************************************/ + /* DEVICE bar config windows over 2G */ + /********************************************/ + Ix++; + /* the base is the base of DRAM CS0 always */ + pexBar.addrWin.baseHigh = 0; + pexBar.addrWin.baseLow = _2G; + pexBar.addrWin.size = _2G; + for ( ;Ix <= SDRAM_CS3; Ix++ ) + { + target = mvDramIfGetCSorder(Ix); + status = mvCpuIfTargetWinGet(target, &addrDecWin); + if (MV_NO_SUCH == status) + { + continue; + } + + /* first get attributes from CPU If */ + if (MV_OK != status) + { + mvOsPrintf("mvPexInit: ERR. Getting DRAM address decode window "\ + "%d from CPU interface failed\n",target - SDRAM_CS0); + return MV_ERROR; + } + + if (addrDecWin.enable == MV_TRUE) + { + + /* set a Pex window for this target ! + DRAM CS always will have a Pex Window , and is not a + part of the priority table */ + pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexWin.addrWin.size = addrDecWin.addrWin.size; + DB(mvOsPrintf("mvPexInit: target %d, size =%d MBYTE \n",target,addrDecWin.addrWin.size/_1M)); + + /* we disable the windows at first because we are not + sure that it is witihin bar boundries */ + pexWin.enable =MV_FALSE; + pexWin.target = target; + pexWin.targetBar = bar; + if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) + { + mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); + return MV_ERROR; + } + } + } + } + + for (target = DEV_TO_TARGET(DEV_CS0); + target < DEV_TO_TARGET(MV_DEV_MAX_CS); + target++ ) + { + status = mvCpuIfTargetWinGet(target, &addrDecWin); + if (MV_NO_SUCH == status) + { + continue; + } + + if (MV_OK != status) + { + mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); + return MV_ERROR; + } + + if (addrDecWin.enable == MV_TRUE) + { + /* get the minimum base */ + if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) + { + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + } + + /* get the maximum base */ + if (addrDecWin.addrWin.baseLow > maxBase) + { + maxBase = addrDecWin.addrWin.baseLow; + sizeOfMaxBase = addrDecWin.addrWin.size; + } + + /* search in the priority table for this target */ + for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; + winIndex++) + { + if (pexDevBarPrioTable[winIndex] != target) + { + continue; + } + /*found it */ + + /* if the index of this target in the prio table is valid + then we set the Pex window for this target, a valid index is + an index that is lower than the number of the windows that + was not configured yet */ + if ( pexCurrWin < PEX_GRNERAL_WIN_NUM) + { + /* set a Pex window for this target ! */ + pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexWin.addrWin.size = addrDecWin.addrWin.size; + + /* we disable the windows at first because we are not + sure that it is witihin bar boundries */ + pexWin.enable = MV_FALSE; + pexWin.target = target; + pexWin.targetBar = bar; + if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, &pexWin)) + { + mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); + return MV_ERROR; + } + } + } + } + } + + if (dramSize <= _2G) + { + pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; + } + pexBar.enable = MV_TRUE; + + pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); + + /* check if the size and base are valid */ + if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) + { + mvOsPrintf("mvPexInit:Warning :Bar %d size is illegal\n",bar); + mvOsPrintf("it will be disabled\n"); + mvOsPrintf("please check Pex and CPU windows configuration\n"); + } + else + { + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + + /* now enable the windows */ + for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) + { + mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", + winNum); + return MV_ERROR; + } + } + } + /* WA - to set default value for default window */ + MV_REG_WRITE(PEX_WIN_DEFAULT_CTRL_REG(pexIf),0xf10); + + return mvPexHalInit(pexIf, pexType); +} + +/******************************************************************************* +* mvPexTargetWinSet - Set PEX to peripheral target address window BAR +* +* DESCRIPTION: +* +* INPUT: +* pexIf - PEX interface number. +* winNum - Address window number. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if PEX BAR target window was set correctly, +* MV_BAD_PARAM on bad params +* MV_ERROR otherwise +* (e.g. address window overlapps with other active PEX target window). +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, MV_PEX_DEC_WIN *pPexAddrDecWin) +{ + + MV_DEC_WIN_PARAMS winParams; + PEX_WIN_REG_INFO winRegOffs; + MV_U32 winCtrlReg = 0; + MV_U32 winBaseReg = 0; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + if (MV_TRUE == pPexAddrDecWin->enable) + { + /* Check if the requested window overlaps with current windows */ + if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pPexAddrDecWin->addrWin)) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window is within its BAR */ + if (MV_FALSE == pexIsWinWithinBar(pexIf,&pPexAddrDecWin->addrWin)) + { + mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", + winNum); + return MV_BAD_PARAM; + } + } + + /* Translate the PEX address decode structure to register fields format */ + if (MV_OK != mvCtrlAddrDecToParams((MV_DEC_WIN*)pPexAddrDecWin, &winParams)) + { + mvOsPrintf("Failed to translate the PEX address decode structure to "\ + "register fields format\n"); + return MV_ERROR; + } + + /* set bar Mapping */ + winCtrlReg |= PXWCR_WIN_BAR_MAP_BAR(pPexAddrDecWin->targetBar); + + /* set attributes */ + winCtrlReg |= (winParams.attrib << PXWCR_ATTRIB_OFFS); + + /* If window is DRAM with HW cache coherency, make sure bit2 is set */ + winCtrlReg &= ~PXWCR_SLV_WR_SPLT_MASK; + winCtrlReg |= PXWCR_SLV_WR_SPLT_128B; + + /* set target ID */ + winCtrlReg |= (winParams.targetId << PXWCR_TARGET_OFFS); + + /* set window size */ + winCtrlReg |= (winParams.size << PXWCR_SIZE_OFFS); + + /* enable\Disable */ + if (MV_TRUE == pPexAddrDecWin->enable) + { + winCtrlReg |= PXWCR_WIN_EN; + } + + /* PCI Express Default Window Control Register reserve some fields */ + if (MV_PEX_WIN_DEFAULT == winNum) + { + winCtrlReg &= (PXWCR_TARGET_MASK | PXWCR_ATTRIB_MASK | PXWCR_SLV_WR_SPLT_MASK); + } + + /* PCI Express Expansion ROM Window Control Register reserve some fields */ + if (MV_PEX_WIN_EXP_ROM == winNum) + { + winCtrlReg &= (PXWCR_TARGET_MASK | PXWCR_ATTRIB_MASK); + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf, winNum, &winRegOffs); + + /* Write to window control register */ + MV_REG_WRITE(winRegOffs.winCtrlRegOffs, winCtrlReg); + + /* PCI Express Default Window and Expansion ROM Window does not have */ + /* base register */ + if (0 != winRegOffs.winBaseRegOffs) + { + /* Base parameter */ + winBaseReg = (winParams.baseAddr & PXWBR_BASE_MASK); + + /* Write to window base register */ + MV_REG_WRITE(winRegOffs.winBaseRegOffs, winBaseReg); + } + + return MV_OK; + +} + +/******************************************************************************* +* mvPexTargetWinGet - Get PEX to peripheral target address window +* +* DESCRIPTION: +* Get the PEX to peripheral target address window BAR. +* +* INPUT: +* pexIf - PEX interface number. +* winNum - Address window number. +* +* OUTPUT: +* pAddrBarWin - PEX target window information data structure. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, MV_PEX_DEC_WIN *pPexAddrDecWin) +{ + MV_DEC_WIN_PARAMS winParams; + PEX_WIN_REG_INFO winRegOffs; + MV_U32 winCtrlReg = 0; + MV_U32 winBaseReg = 0; + + /* Parameter checking */ + if(pexIf > mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf,winNum, &winRegOffs); + + /* Read Control register */ + winCtrlReg = MV_REG_READ(winRegOffs.winCtrlRegOffs); + + /* Read size reg if there is valid base information */ + if (winRegOffs.winBaseRegOffs) + { + winBaseReg = MV_REG_READ(winRegOffs.winBaseRegOffs); + } + + /* Extract window parameters from registers */ + winParams.attrib = (winCtrlReg & PXWCR_ATTRIB_MASK) >> PXWCR_ATTRIB_OFFS; + winParams.targetId = (winCtrlReg & PXWCR_TARGET_MASK) >> PXWCR_TARGET_OFFS; + winParams.size = (winCtrlReg & PXWCR_SIZE_MASK) >> PXWCR_SIZE_OFFS; + winParams.baseAddr = winBaseReg & PXWBR_BASE_MASK; + + /* Translate the decode window parameters to address decode struct */ + if (MV_OK != mvCtrlParamsToAddrDec(&winParams, (MV_DEC_WIN*)pPexAddrDecWin)) + { + mvOsPrintf("Failed to translate register parameters to PEX address" \ + " decode window structure\n"); + return MV_ERROR; + } + + /* get target bar */ + pPexAddrDecWin->targetBar = ((winCtrlReg & PXWCR_WIN_BAR_MAP_MASK) >> + PXWCR_WIN_BAR_MAP_OFFS) + 1; + + pPexAddrDecWin->slvWrSpltCnt = ((winCtrlReg & PXWCR_SLV_WR_SPLT_MASK) >> + PXWCR_SLV_WR_SPLT_OFFS); + + pPexAddrDecWin->enable = (winCtrlReg & PXWCR_WIN_EN) >> PXWCR_WIN_EN_OFFS; + + return MV_OK; + +} + +/******************************************************************************* +* mvPexTargetWinEnable - Enable/disable a PEX BAR window +* +* DESCRIPTION: +* This function enable/disable a PEX BAR window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling PEX accesses for that BAR (before enabling the +* window it is tested for overlapping). Otherwise, the window will +* be disabled. +* +* INPUT: +* pexIf - PEX interface number. +* winNum - Address window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) +{ + PEX_WIN_REG_INFO winRegOffs; + MV_PEX_DEC_WIN addrDecWin; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); + return MV_BAD_PARAM; + } + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + /* Enable/Disable not relevant to default and expantion rom windows */ + if ((MV_PEX_WIN_DEFAULT == winNum) || (MV_PEX_WIN_EXP_ROM == winNum)) + { + return MV_BAD_PARAM; + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf, winNum, &winRegOffs); + + /* if the address windows is disabled , we only disable the appropriare + pex window and ignore other settings */ + if (MV_FALSE == enable) + { + MV_REG_BIT_RESET(winRegOffs.winCtrlRegOffs, PXWCR_WIN_EN); + } + else + { + if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) + { + mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); + return MV_ERROR; + } + + /* Check if the requested window overlaps with current windows */ + if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) + { + mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); + return MV_BAD_PARAM; + } + + if (MV_FALSE == pexIsWinWithinBar(pexIf, &addrDecWin.addrWin)) + { + mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", + winNum); + return MV_BAD_PARAM; + } + + MV_REG_BIT_SET(winRegOffs.winCtrlRegOffs, PXWCR_WIN_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* mvPexTargetWinRemap - Set PEX to target address window remap. +* +* DESCRIPTION: +* The PEX interface supports remap of the BAR original address window. +* For each BAR it is possible to define a remap address. For example +* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified +* according to remap register but will also be targeted to the +* SDRAM CS[0]. +* +* INPUT: +* pexIf - PEX interface number. +* winNum - Address window number. +* pAddrWin - Address window to be checked. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_REMAP_WIN *pAddrWin) +{ + + PEX_WIN_REG_INFO winRegOffs; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", + pexIf); + return MV_BAD_PARAM; + } + + if ((MV_PEX_WIN_DEFAULT == winNum) || (winNum >= PEX_MAX_TARGET_WIN)) + { + mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); + + return MV_BAD_PARAM; + } + + if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) + { + mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + pexIf, + winNum, + pAddrWin->addrWin.baseLow, + pAddrWin->addrWin.size); + + return MV_ERROR; + } + + pexWinRegInfoGet(pexIf, winNum, &winRegOffs); + + /* Set remap low register value */ + MV_REG_WRITE(winRegOffs.winRemapLowRegOffs, pAddrWin->addrWin.baseLow); + + /* Skip base high settings if the BAR has only base low (32-bit) */ + if (0 != winRegOffs.winRemapHighRegOffs) + { + MV_REG_WRITE(winRegOffs.winRemapHighRegOffs, pAddrWin->addrWin.baseHigh); + } + + + if (pAddrWin->enable == MV_TRUE) + { + MV_REG_BIT_SET(winRegOffs.winRemapLowRegOffs,PXWRR_REMAP_EN); + } + else + { + MV_REG_BIT_RESET(winRegOffs.winRemapLowRegOffs,PXWRR_REMAP_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* mvPexTargetWinRemapEnable - +* +* DESCRIPTION: +* +* INPUT: +* pexIf - PEX interface number. +* winNum - Address window number. +* +* OUTPUT: +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, + MV_BOOL enable) +{ + PEX_WIN_REG_INFO winRegOffs; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", + pexIf); + return MV_BAD_PARAM; + } + + if ((MV_PEX_WIN_DEFAULT == winNum) || (winNum >= PEX_MAX_TARGET_WIN)) + { + mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); + + return MV_BAD_PARAM; + } + + pexWinRegInfoGet(pexIf, winNum, &winRegOffs); + + if (enable == MV_TRUE) + { + MV_REG_BIT_SET(winRegOffs.winRemapLowRegOffs,PXWRR_REMAP_EN); + } + else + { + MV_REG_BIT_RESET(winRegOffs.winRemapLowRegOffs,PXWRR_REMAP_EN); + } + + return MV_OK; + +} + +/******************************************************************************* +* mvPexBarSet - Set PEX bar address and size +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexBarSet(MV_U32 pexIf, + MV_U32 barNum, + MV_PEX_BAR *pAddrWin) +{ + MV_U32 regBaseLow; + MV_U32 regSize,sizeToReg; + + + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + + if (pAddrWin->addrWin.size == 0) + { + mvOsPrintf("mvPexBarSet: Size zero is Illegal\n" ); + return MV_BAD_PARAM; + } + + + /* Check if the window complies with PEX spec */ + if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, + pAddrWin->addrWin.size)) + { + mvOsPrintf("mvPexBarSet: ERR. BAR %d window invalid\n", barNum); + return MV_BAD_PARAM; + } + + /* 2) Check if the requested bar overlaps with current bars */ + if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) + { + mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); + return MV_BAD_PARAM; + } + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); + + /* Read bar size */ + if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ + { + regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); + return MV_BAD_PARAM; + } + + regSize &= ~PXBCR_BAR_SIZE_MASK; + regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; + + MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); + + } + + /* set size */ + + + + /* Read base address low */ + regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_MV_BAR_BASE(barNum))); + + /* clear current base */ + if (PEX_INTER_REGS_BAR == barNum) + { + regBaseLow &= ~PXBIR_BASE_MASK; + regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); + } + else + { + regBaseLow &= ~PXBR_BASE_MASK; + regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); + } + + /* if we had a previous value that contain the bar type (MeM\IO), we want to + restore it */ + regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; + + /* write base low */ + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), + regBaseLow); + + if (pAddrWin->addrWin.baseHigh != 0) + { + /* Read base address high */ + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), + pAddrWin->addrWin.baseHigh); + + } + + /* lastly enable the Bar */ + if (pAddrWin->enable == MV_TRUE) + { + if (PEX_INTER_REGS_BAR != barNum) /* internal registers + are enabled always */ + { + MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + } + } + else if (MV_FALSE == pAddrWin->enable) + { + if (PEX_INTER_REGS_BAR != barNum) /* internal registers + are enabled always */ + { + MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + } + + } + + + + return MV_OK; +} + + +/******************************************************************************* +* mvPexBarGet - Get PEX bar address and size +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexBarGet(MV_U32 pexIf, + MV_U32 barNum, + MV_PEX_BAR *pAddrWin) +{ + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + /* read base low */ + pAddrWin->addrWin.baseLow = + MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); + + + if (PEX_INTER_REGS_BAR == barNum) + { + pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; + } + else + { + pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; + } + + + /* read base high */ + pAddrWin->addrWin.baseHigh = + MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); + + + /* Read bar size */ + if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ + { + pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); + + /* check if enable or not */ + if (pAddrWin->addrWin.size & PXBCR_BAR_EN) + { + pAddrWin->enable = MV_TRUE; + } + else + { + pAddrWin->enable = MV_FALSE; + } + + /* now get the size */ + pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; + pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; + + pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, + PXBCR_BAR_SIZE_ALIGNMENT); + + } + else /* PEX_INTER_REGS_BAR */ + { + pAddrWin->addrWin.size = INTER_REGS_SIZE; + pAddrWin->enable = MV_TRUE; + } + + + return MV_OK; +} + +/******************************************************************************* +* mvPexBarEnable - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) +{ + + MV_PEX_BAR pexBar; + + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + if (PEX_INTER_REGS_BAR == barNum) + { + if (MV_TRUE == enable) + { + return MV_OK; + } + else + { + return MV_ERROR; + } + } + + + if (MV_FALSE == enable) + { + /* disable bar and quit */ + MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + return MV_OK; + } + + /* else */ + + if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) + { + mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); + return MV_ERROR; + + } + + if (MV_TRUE == pexBar.enable) + { + /* it is already enabled !!! */ + return MV_OK; + } + + /* else enable the bar*/ + + pexBar.enable = MV_TRUE; + + if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) + { + mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); + return MV_ERROR; + + } + + return MV_OK; +} + + +/******************************************************************************* +* pexWinOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PEX BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, + MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 win; + MV_PEX_DEC_WIN addrDecWin; + + for(win = 0; win < PEX_GRNERAL_WIN_NUM ; win++) + { + /* don't check our target or illegal targets */ + if (winNum == win) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) + { + mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", + win); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", winNum, win); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* pexIsWinWithinBar - Detect if address is within PEX bar boundries +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 bar; + MV_PEX_BAR addrDecWin; + + for(bar = 0; bar < PEX_MAX_BARS; bar++) + { + /* Get window parameters */ + if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) + { + mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled bars */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) + { + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* pexBarOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PEX BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, + MV_U32 barNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 bar; + MV_PEX_BAR barDecWin; + + + for(bar = 0; bar < PEX_MAX_BARS; bar++) + { + /* don't check our target or illegal targets */ + if (barNum == bar) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) + { + mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* don'nt check disabled bars */ + if (barDecWin.enable == MV_FALSE) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) + { + mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", barNum, bar); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* pexBarIsValid - Check if the given address window is valid +* +* DESCRIPTION: +* PEX spec restrict BAR base to be aligned to BAR size. +* This function checks if the given address window is valid. +* +* INPUT: +* baseLow - 32bit low base address. +* size - Window size. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the address window is valid, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) +{ + + /* PCI spec restrict BAR base to be aligned to BAR size */ + if(MV_IS_NOT_ALIGN(baseLow, size)) + { + return MV_ERROR; + } + else + { + return MV_TRUE; + } + + return MV_TRUE; +} + +/******************************************************************************* +* pexBarRegInfoGet - Get BAR register information +* +* DESCRIPTION: +* PEX BARs registers offsets are inconsecutive. +* This function gets a PEX BAR register information like register offsets +* and function location of the BAR. +* +* INPUT: +* pexIf - PEX interface number. +* winNum - The PEX address decode window in question. +* +* OUTPUT: +* pBarRegInfo - BAR register info struct. +* +* RETURN: +* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK +* +*******************************************************************************/ +static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, + MV_U32 winNum, + PEX_WIN_REG_INFO *pWinRegInfo) +{ + + if (MV_PEX_WIN_DEFAULT == winNum) + { + pWinRegInfo->winCtrlRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); + pWinRegInfo->winBaseRegOffs = 0; + pWinRegInfo->winRemapLowRegOffs = 0; + pWinRegInfo->winRemapHighRegOffs = 0; + } + else if (MV_PEX_WIN_EXP_ROM == winNum) + { + pWinRegInfo->winCtrlRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); + pWinRegInfo->winBaseRegOffs = 0; + pWinRegInfo->winRemapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); + pWinRegInfo->winRemapHighRegOffs = 0; + + } + else + { + pWinRegInfo->winCtrlRegOffs = PEX_WIN_CTRL_REG(pexIf,winNum); + pWinRegInfo->winBaseRegOffs = PEX_WIN_BASE_REG(pexIf,winNum); + pWinRegInfo->winRemapLowRegOffs = PEX_WIN_REMAP_REG(pexIf,winNum); + pWinRegInfo->winRemapHighRegOffs = PEX_WIN_REMAP_HIGH_REG(pexIf,winNum); + } + + + return MV_OK; +} + +/******************************************************************************* +* pexBarNameGet - Get the string name of PEX BAR. +* +* DESCRIPTION: +* This function get the string name of PEX BAR. +* +* INPUT: +* bar - PEX bar number. +* +* OUTPUT: +* None. +* +* RETURN: +* pointer to the string name of PEX BAR. +* +*******************************************************************************/ +const MV_8* pexBarNameGet( MV_U32 bar ) +{ + switch( bar ) + { + case PEX_INTER_REGS_BAR: + return "Internal Regs Bar0...."; + case PEX_DRAM_BAR: + return "DRAM Bar1............."; + case PEX_DEVICE_BAR: + return "Devices Bar2.........."; + default: + return "Bar unknown"; + } +} +/******************************************************************************* +* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). +* +* DESCRIPTION: +* This function print the PEX address decode map (BARs and windows). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvPexAddrDecShow(MV_VOID) +{ + MV_PEX_BAR pexBar; + MV_U32 pexIf; + MV_U32 pexIfMax = mvCtrlPexMaxIfGet(); + MV_U32 bar; + + for( pexIf = 0; pexIf < pexIfMax; pexIf++ ) + { +#if defined (MV78200) + if (mvSocUnitIsMappedToThisCpu(PEX00+(pexIf/4)) == MV_FALSE) + { + continue; + } +#endif + mvOsOutput( "\n" ); + mvOsOutput( "PEX%d:\n", pexIf ); + mvOsOutput( "-----\n" ); + if (mvPexIsPowerUp(pexIf) == MV_FALSE) + { + mvOsOutput( "Pex interface is shutdown\n"); + continue; + } + mvOsOutput( "Pex Bars \n\n"); + + for( bar = 0; bar < PEX_MAX_BARS; bar++ ) + { + memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); + + mvOsOutput( "%s ", pexBarNameGet(bar) ); + + + if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) + { + if( pexBar.enable ) + { + mvOsOutput( "base %08x:%08x, ", pexBar.addrWin.baseHigh, pexBar.addrWin.baseLow ); + mvSizePrint( pexBar.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } + + mvPexDecWinShow(pexIf); + } +} + + +/******************************************************************************* +* mvPexDecWinShow - Print the PEX address decode windows. +* +* DESCRIPTION: +* This function print the PEX address decode windows. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID mvPexDecWinShow(MV_U32 pexIf) +{ + MV_PEX_DEC_WIN win; + int winNum; + + mvOsOutput( "\nPex Decode Windows\n\n"); + + for( winNum = 0; winNum < PEX_GRNERAL_WIN_NUM; winNum++ ) + { + memset( &win, 0, sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "win%d - ", winNum ); + + if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x:%08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseHigh, win.addrWin.baseLow ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } + + memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "default win - " ); + + if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) + { + mvOsOutput( "%s ", + mvCtrlTargetNameGet(win.target) ); + mvOsOutput( "\n" ); + } + memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "Expansion ROM - " ); + + if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) + { + mvOsOutput( "%s ", + mvCtrlTargetNameGet(win.target) ); + mvOsOutput( "\n" ); + } +} + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysPex.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysPex.h new file mode 100644 index 0000000..37cb4e9 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysPex.h @@ -0,0 +1,286 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCSysPEXH +#define __INCSysPEXH + +#include "mvCommon.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "pex/mvPex.h" + + +#define MV_PEX_WIN_DEFAULT 6 +#define MV_PEX_WIN_EXP_ROM 7 +#define PEX_GRNERAL_WIN_NUM 6 +#define PEX_MAX_TARGET_WIN 8 + + +#define PEX_MAX_BARS 3 +#define PEX_INTER_REGS_BAR 0 +#define PEX_DRAM_BAR 1 +#define PEX_DEVICE_BAR 2 + +/*************************************/ +/* PCI Express BAR Control Registers */ +/*************************************/ +#define PEX_BAR_CTRL_REG(pexIf, bar) ((PEX_IF_BASE(pexIf)) + 0x1800 + (bar * 4)) +#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x180C) +/************************************************/ +/* PCI Express Address Window Control Registers */ +/************************************************/ +#define PEX_WIN_REG_OFFS(winNum) ((winNum >= 5) ? 0x60 : (winNum * 0x10)) + +#define PEX_WIN_CTRL_REG(pexIf,winNum) \ + ((PEX_IF_BASE(pexIf)) + 0x1820 + PEX_WIN_REG_OFFS(winNum)) + +#define PEX_WIN_BASE_REG(pexIf,winNum) \ + ((PEX_IF_BASE(pexIf)) + 0x1824 + PEX_WIN_REG_OFFS(winNum)) + +#define PEX_WIN_REMAP_REG(pexIf,winNum) \ + ((PEX_IF_BASE(pexIf)) + 0x182C + PEX_WIN_REG_OFFS(winNum)) + +#define PEX_WIN_REMAP_HIGH_REG(pexIf,winNum) \ + ((winNum >= 4) ? ((PEX_IF_BASE(pexIf)) + 0x1870 + ((winNum - 4) * 0x20)) : 0) + +#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18B0) +#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18C0) +#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18C4) + +/* PCI Express Window Control Register */ +/* PEX_WIN_CTRL_REG (PXWCR) */ +#define PXWCR_WIN_EN_OFFS 0 +#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ +#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ +#define PXWCR_WIN_BAR_MAP_MASK (1 << PXWCR_WIN_BAR_MAP_OFFS) +#define PXWCR_WIN_BAR_MAP_BAR(barNum) ((barNum-1) << PXWCR_WIN_BAR_MAP_OFFS) +#define PXWCR_SLV_WR_SPLT_OFFS 2 +#define PXWCR_SLV_WR_SPLT_MASK (1 << PXWCR_SLV_WR_SPLT_OFFS) +#define PXWCR_SLV_WR_SPLT_128B (0 << PXWCR_SLV_WR_SPLT_OFFS) +#define PXWCR_SLV_WR_SPLT_32B (1 << PXWCR_SLV_WR_SPLT_OFFS) +#define PXWCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) +#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) +#define PXWCR_SIZE_OFFS 16 /* size */ +#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) +#define PXWCR_SIZE_ALIGNMENT 0x10000 + +/* PCI Express Window Base Register */ +/* PEX_WIN_BASE_REG (PXWBR)*/ +#define PXWBR_BASE_OFFS 16 /* address[31:16] */ +#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) +#define PXWBR_BASE_ALIGNMENT 0x10000 + +/* PCI Express Window Remap Register */ +/* PEX_WIN_REMAP_REG (PXWRR)*/ +#define PXWRR_REMAP_EN BIT0 +#define PXWRR_REMAP_OFFS 16 +#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) +#define PXWRR_REMAP_ALIGNMENT 0x10000 + +/* PCI Express Window Remap (High) Register */ +/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ +#define PXWRHR_REMAP_HIGH_OFFS 0 +#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) + +/* PCI Express Default Window Control Register */ +/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ +#define PXWDCR_SLV_WR_SPLT_CNT_OFFS 2 +#define PXWDCR_SLV_WR_SPLT_CNT_MASK (1 << PXWDCR_SLV_WR_SPLT_CNT_OFFS) +#define PXWDCR_SLV_WR_SPLT_CNT_128B (0 << PXWDCR_SLV_WR_SPLT_CNT_OFFS) +#define PXWDCR_SLV_WR_SPLT_CNT_32B (1 << PXWDCR_SLV_WR_SPLT_CNT_OFFS) +#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) +#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) + +/* PCI Express Expansion ROM Window Control Register */ +/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ +#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) +#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) + +/* PCI Express Expansion ROM Window Remap Register */ +/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ +#define PXWERRR_REMAP_EN BIT0 +#define PXWERRR_REMAP_OFFS 16 +#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) +#define PXWERRR_REMAP_ALIGNMENT 0x10000 + + +/* PCI Express BAR Control Register */ +/* PEX_BAR_CTRL_REG (PXBCR) */ +#define PXBCR_BAR_EN BIT0 +#define PXBCR_BAR_SIZE_OFFS 16 +#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) +#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 + +/* PCI Express Expansion ROM BAR Control Register */ +/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ +#define PXERBCR_EXPROM_EN BIT0 +#define PXERBCR_EXPROMSZ_OFFS 19 +#define PXERBCR_EXPROMSZ_MASK (0x7 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) + + +/* PCI Express BAR0 Internal Register*/ +/* PEX BAR0_INTER_REG (PXBIR)*/ +#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ +#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) +#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) +#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) +#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ +#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ +#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) +#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) + +/* PCI Express BAR1 Register and PCI Express BAR2 Register*/ +/* PEX BAR1_REG (PXBR) and PEX BAR2_REG (PXBR) */ +#define PXBR_IOSPACE PXBIR_IOSPACE +#define PXBR_TYPE_OFFS PXBIR_TYPE_OFFS +#define PXBR_TYPE_MASK PXBIR_TYPE_MASK +#define PXBR_TYPE_32BIT_ADDR PXBIR_TYPE_32BIT_ADDR +#define PXBR_TYPE_64BIT_ADDR PXBIR_TYPE_64BIT_ADDR +#define PXBR_PREFETCH_EN PXBIR_PREFETCH_EN +#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ +#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) +#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) + +/* This macro defines default BAR attributes */ +#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ + +/* PEX Bar attributes */ +typedef struct _mvPexBar +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +}MV_PEX_BAR; + +/* PEX Remap Window attributes */ +typedef struct _mvPexRemapWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_PEX_REMAP_WIN; + +/* PEX Window attributes */ +typedef struct _mvPexDecWin +{ + MV_TARGET target; /* Target for addr decode window */ + MV_ADDR_WIN addrWin; /* Address window of target */ + MV_BOOL enable; /* Window enable/disable */ + MV_U32 targetBar; + MV_BOOL slvWrSpltCnt; +} MV_PEX_DEC_WIN; + + +/* Global Functions prototypes */ +/* mvPexHalInit - Initialize PEX interfaces*/ +MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); + + +/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ +MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, + MV_U32 winNum, MV_PEX_DEC_WIN *pPexAddrDecWin); + +/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ +MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pPexAddrDecWin); +/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ +MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf, + MV_U32 winNum, MV_BOOL enable); + +/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ +MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_REMAP_WIN *pAddrWin); + +/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ +MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, + MV_BOOL enable); + +/* mvPexBarSet - Set PEX bar address and size */ +MV_STATUS mvPexBarSet(MV_U32 pexIf, + MV_U32 barNum, + MV_PEX_BAR *pAddrWin); + +/* mvPexBarGet - Get PEX bar address and size */ +MV_STATUS mvPexBarGet(MV_U32 pexIf, + MV_U32 barNum, + MV_PEX_BAR *pAddrWin); + +/* mvPexBarEnable - enable\disable a PEX bar*/ +MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); + +/* mvPexAddrDecShow - Display address decode windows attributes */ +MV_VOID mvPexAddrDecShow(MV_VOID); + +#endif diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysSata.c b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysSata.c new file mode 100644 index 0000000..2542f01 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysSata.c @@ -0,0 +1,438 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "sata/CoreDriver/mvRegs.h" +#include "ctrlEnv/sys/mvSysSata.h" +#include "cpu/mvCpu.h" +#if defined (MV78200) +#include "mv78200/mvSocUnitMap.h" +#endif + +MV_TARGET sataAddrDecPrioTab[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif + TBL_TERM +}; + + +/******************************************************************************* +* sataWinOverlapDetect - Detect SATA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case SATA address decode +* windows overlapps. +* This function detects SATA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_SATA_DEC_WIN addrDecWin; + + for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = 0; + decRegs.sizeReg = 0; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; + decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); + + /* set target ID */ + decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; + decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); + + if (pAddrDecWin->enable == MV_TRUE) + { + decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; + } + else + { + decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; + } + + MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); + MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvSataWinGet - Get SATA peripheral target address window. +* +* DESCRIPTION: +* Get SATA peripheral target address window. +* +* INPUT: +* winNum - SATA target address decode window number. +* +* OUTPUT: +* pAddrDecWin - SATA target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", + __FUNCTION__, dev, winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); + decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) + { + mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> + MV_SATA_WIN_ATTR_OFFSET; + targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> + MV_SATA_WIN_TARGET_OFFSET; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + return MV_OK; +} +/******************************************************************************* +* mvSataAddrDecShow - Print the SATA address decode map. +* +* DESCRIPTION: +* This function print the SATA address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvSataAddrDecShow(MV_VOID) +{ + + MV_SATA_DEC_WIN win; + int i,j; + +#if defined (MV78200) + if (mvSocUnitIsMappedToThisCpu(SATA) == MV_FALSE) + return; +#endif + + + for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) + { + if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) + return; + + mvOsOutput( "\n" ); + mvOsOutput( "SATA %d:\n", j ); + mvOsOutput( "----\n" ); + + for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvSataWinGet(j, i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } + } +} + + +/******************************************************************************* +* mvSataWinInit - Initialize the integrated SATA target address window. +* +* DESCRIPTION: +* Initialize the SATA peripheral target address window. +* +* INPUT: +* +* +* OUTPUT: +* +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSataWinInit(MV_VOID) +{ + int winNum; + MV_SATA_DEC_WIN sataWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 status, winPrioIndex = 0; + + /* Initiate Sata address decode */ + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); + regVal &= ~MV_SATA_WIN_ENABLE_MASK; + MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); + } + + winNum = 0; + while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && + (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) + { + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], + &cpuAddrDecWin); + + if(MV_NO_SUCH == status) + { + winPrioIndex++; + continue; + } + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; + sataWin.enable = MV_TRUE; + sataWin.target = sataAddrDecPrioTab[winPrioIndex]; + + if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) + { + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} + + + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysSata.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysSata.h new file mode 100644 index 0000000..325fb8d --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysSata.h @@ -0,0 +1,128 @@ + +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCMVSysSataAddrDech +#define __INCMVSysSataAddrDech + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct _mvSataDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +} MV_SATA_DEC_WIN; + + +#define MV_SATA_MAX_ADDR_DECODE_WIN 4 + +#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) +#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) + +/* BITs in Bridge Interrupt Cause and Mask registers */ +#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 +#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); + decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* for the safe side we disable the window before writing the new + values */ + mvTdmWinEnable(winNum, MV_FALSE); + + ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); + ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); + ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); + + /* Write to address base and control registers */ + MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); + MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + { + mvTdmWinEnable(winNum, MV_TRUE); + } + return MV_OK; +} + +/******************************************************************************* +* mvTdmWinGet - Get peripheral target address window. +* +* DESCRIPTION: +* Get TDM peripheral target address window. +* +* INPUT: +* winNum - TDM to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - TDM target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ + +MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) +{ + + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); + decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; + targetAttrib.targetId = + (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvTdmWinEnable - Enable/disable a TDM to target address window +* +* DESCRIPTION: +* This function enable/disable a TDM to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling TDM accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - TDM to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) +{ + MV_TDM_DEC_WIN addrDecWin; + + if (MV_TRUE == enable) + { + if (winNum >= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) + { + mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); + } + else + { /* Overlap detected */ + mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { + MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); + } + return MV_OK; +} + + +/******************************************************************************* +* tdmWinOverlapDetect - Detect TDM address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviour is expected in case TDM address decode +* windows overlapps. +* This function detects TDM address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_TDM_DEC_WIN addrDecWin; + + for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) + { + /* Do not check window itself */ + if (winNumIndex == winNum) + { + continue; + } + /* Do not check disabled windows */ + if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) + { + /* Get window parameters */ + if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) + { + DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + } + return MV_FALSE; +} + +/******************************************************************************* +* mvTdmAddrDecShow - Print the TDM address decode map. +* +* DESCRIPTION: +* This function print the TDM address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvTdmAddrDecShow(MV_VOID) +{ + MV_TDM_DEC_WIN win; + int i; + + mvOsOutput( "\n" ); + mvOsOutput( "TDM:\n" ); + mvOsOutput( "----\n" ); + + for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if (mvTdmWinGet(i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); + mvOsOutput( "...." ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysTdm.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysTdm.h new file mode 100644 index 0000000..a281b2a --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysTdm.h @@ -0,0 +1,105 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvSysTdmh +#define __INCmvSysTdmh + +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +typedef struct _mvTdmDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +} MV_TDM_DEC_WIN; + +MV_STATUS mvTdmWinInit(MV_VOID); +MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); +MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); +MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); +MV_VOID mvTdmAddrDecShow(MV_VOID); + + +#define TDM_MBUS_MAX_WIN 4 +#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) +#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) + +/* TDM_WIN_CTRL_REG bits */ +#define TDM_WIN_ENABLE_OFFS 0 +#define TDM_WIN_ENABLE_MASK (1<mcr = MCR_AFCE; /* Enable Auto flow control */ +#endif + + /*set the UART channel to use the IDMA*/ + MV_REG_BIT_SET(UART_EXTERNAL_CONTROL_REG, BIT0 | (BIT8 << port)); + + /* Set IDMA BAR target to UART*/ + MV_REG_BIT_RESET(IDMA_BASE_ADDR_REG(idmaWinNum), 0xffff0000); + /*Set BAR to UART*/ + MV_REG_BIT_SET(IDMA_BASE_ADDR_REG(idmaWinNum), 0x0101); + + /* Set IDMA0 channel to UART mode*/ + switch (srcBurstSize) + { + case 8: + srcBurstLim = ICCLR_SRC_BURST_LIM_8BYTE; + break; + case 16: + srcBurstLim = ICCLR_SRC_BURST_LIM_16BYTE; + break; + case 32: + srcBurstLim = ICCLR_SRC_BURST_LIM_32BYTE; + break; + case 64: + srcBurstLim = ICCLR_SRC_BURST_LIM_64BYTE; + break; + case 128: + srcBurstLim = ICCLR_SRC_BURST_LIM_128BYTE; + break; + default: + mvOsPrintf("mvUartDmaInit:ERR. Illegal source burst limit, setting to 128B default\n"); + srcBurstLim = ICCLR_SRC_BURST_LIM_128BYTE; + break; + } + mvDmaCtrlLowSet(0, 0x18220 | srcBurstLim); /*channel control low according FS*/ + mvDmaOverrideSet(0, idmaWinNum, DMA_DST_ADDR); + return; +} + + +/******************************************************************************* +* mvUartDmaTransmit - Transmit a buffer over the UART using the IDMA. +* +* DESCRIPTION: +* This routine transmits a buffer over the UART port using IDMA0. +* +* INPUT: +* port - uart port number. +* byteCount - The total number of bytes to be transferred to the UART. +* srcAddr - The source address of the buffer to be transferred. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK. +* +*******************************************************************************/ +MV_STATUS mvUartDmaTransmit(MV_U32 port, MV_U32 byteCount, MV_U32 srcAddr) +{ + MV_U32 dstAddr, tmp; + + /* Verify IDMA 0 is not busy */ + if(mvDmaStateGet(port) != MV_IDLE) + { + mvOsPrintf("mvUartDmaTransmit: ERR. IDMA 0 busy.\n"); + return MV_ERROR; + } + + /* Verify byte count is legal, and choose either 64K mode or 16M mode */ + if(byteCount >= 0x1000000) + { + mvOsPrintf("mvUartDmaTransmit: ERR. Illegal Byte count.\n"); + return MV_ERROR; + } + else if (byteCount >= 0x10000) + { + byteCount |= BIT31; + } + + /* Calculate UART destination address from assigned BAR*/ + tmp = MV_REG_READ(IDMA_CTRL_LOW_REG(0)); + tmp = (tmp >> 23) & 0x3; /* Extract the destination override window number*/ + + /* Check that destination BAR is configured and calculate destination address*/ + if((MV_REG_READ(IDMA_BASE_ADDR_REG(tmp)) & 0xffff) != 0x0101) + { + mvOsPrintf("mvUartDmaTransmit: ERR. IDMA UART BAR isn't configured.\n"); + return MV_ERROR; + } + else + dstAddr = (MV_REG_READ(IDMA_BASE_ADDR_REG(tmp)) & 0xffff0000 ) | (port << 8); + + /* Start transfer */ + if(mvDmaTransfer(0, srcAddr, dstAddr, byteCount, 0x0) == MV_OK) + return MV_OK; + else + return MV_ERROR; +} + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysUart.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysUart.h new file mode 100644 index 0000000..1969e80 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysUart.h @@ -0,0 +1,75 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __MVSYSUART_H__ +#define __MVSYSUART_H__ + + + +/* APIs */ +MV_VOID mvUartDmaInit(MV_U32 port, MV_U32 baudDivisor, MV_UART_PORT* base, + MV_U32 idmaWinNum, MV_U32 srcBurstSize); +MV_STATUS mvUartDmaTransmit(MV_U32 port, MV_U32 byteCount, MV_U32 srcAddr); + +#endif /* __MVSYSUART_H__ */ diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysUsb.c b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysUsb.c new file mode 100644 index 0000000..8e5f417 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysUsb.c @@ -0,0 +1,505 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/sys/mvSysUsb.h" +#include "cpu/mvCpu.h" +#if defined (MV78200) +#include "mv78200/mvSocUnitMap.h" +#endif + +MV_TARGET usbAddrDecPrioTab[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) + CRYPT_ENG, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif + TBL_TERM +}; + + + +MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) +{ + MV_STATUS status; + + status = mvUsbWinInit(dev); + if(status != MV_OK) + return status; + + return mvUsbHalInit(dev, isHost); +} + + +/******************************************************************************* +* usbWinOverlapDetect - Detect USB address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case USB address decode +* windows overlapps. +* This function detects USB address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_DEC_WIN addrDecWin; + + for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) + { + mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pDecWin->target), + pDecWin->addrWin.baseLow, + pDecWin->addrWin.size); + return MV_ERROR; + } + + if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) + { + mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* set Size, Attributes and TargetID */ + sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | + ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | + ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); + +#if defined(MV645xx) || defined(MV646xx) + /* If window is DRAM with HW cache coherency, make sure bit2 is set */ + sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; + + if((MV_TARGET_IS_DRAM(pDecWin->target)) && + (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) + { + sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; + } + else + { + sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; + } +#endif /* MV645xx || MV646xx */ + + if (pDecWin->enable == MV_TRUE) + { + sizeReg |= MV_USB_WIN_ENABLE_MASK; + } + else + { + sizeReg &= ~MV_USB_WIN_ENABLE_MASK; + } + + /* Update Base value */ + baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); + + MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); + MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvUsbWinGet - Get USB peripheral target address window. +* +* DESCRIPTION: +* Get USB peripheral target address window. +* +* INPUT: +* winNum - USB target address decode window number. +* +* OUTPUT: +* pDecWin - USB target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) +{ + MV_DEC_WIN_PARAMS winParam; + MV_U32 sizeReg, baseReg; + + /* Parameter checking */ + if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", + __FUNCTION__, dev, winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); + sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); + + /* Check if window is enabled */ + if(sizeReg & MV_USB_WIN_ENABLE_MASK) + { + pDecWin->enable = MV_TRUE; + + /* Extract window parameters from registers */ + winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; + winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; + winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; + winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); + + /* Translate the decode window parameters to address decode struct */ + if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) + { + mvOsPrintf("Failed to translate register parameters to USB address" \ + " decode window structure\n"); + return MV_ERROR; + } + } + else + { + pDecWin->enable = MV_FALSE; + } + return MV_OK; +} + +/******************************************************************************* +* mvUsbWinInit - +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvUsbWinInit(int dev) +{ + MV_STATUS status; + MV_DEC_WIN usbWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + int winNum; + MV_U32 winPrioIndex = 0; + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); + } + + /* Go through all windows in user table until table terminator */ + winNum = 0; + while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && + (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) + { + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], + &cpuAddrDecWin); + + if(MV_NO_SUCH == status) + { + winPrioIndex++; + continue; + } + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; + usbWin.enable = MV_TRUE; + usbWin.target = usbAddrDecPrioTab[winPrioIndex]; + +#if defined(MV645xx) || defined(MV646xx) + /* Get the default attributes for that target window */ + mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); +#endif /* MV645xx || MV646xx */ + + if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) + { + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} + +/******************************************************************************* +* mvUsbAddrDecShow - Print the USB address decode map. +* +* DESCRIPTION: +* This function print the USB address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvUsbAddrDecShow(MV_VOID) +{ + MV_DEC_WIN addrDecWin; + int i, winNum; + + mvOsOutput( "\n" ); + mvOsOutput( "USB:\n" ); + mvOsOutput( "----\n" ); + + for(i=0; i= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + if (pAddrDecWin == NULL) + { + DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + /* Check if the requested window overlaps with current windows */ + if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) + { + DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); + return MV_ERROR; + } + + xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); + xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); + + /* Get Base Address and size registers values */ + if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) + { + DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); + return MV_BAD_PARAM; + } + + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; + xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; + /* set target ID */ + xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; + xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; + + + /* Write to address decode Base Address Register */ + MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); + + /* Write to Size Register */ + MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + if (pAddrDecWin->enable) + { + MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), + (XEXWCR_WIN_EN_MASK(winNum)) | + (XEXWCR_WIN_ACC_MASK(winNum))); + } + else + { + MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), + (XEXWCR_WIN_EN_MASK(winNum)) | + (XEXWCR_WIN_ACC_MASK(winNum))); + } + } + return MV_OK; +} + +/******************************************************************************* +* mvXorTargetWinGet - Get xor peripheral target address window. +* +* DESCRIPTION: +* Get xor peripheral target address window. +* +* INPUT: +* winNum - One of the possible XOR memory decode windows. +* +* OUTPUT: +* base - Window base address. +* size - Window size. +* enable - window enable/disable. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS xorDecRegs; + MV_TARGET_ATTRIB targetAttrib; + MV_U32 chan=0,chanWinEn; + + /* Parameter checking */ + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); + return MV_ERROR; + } + + if (NULL == pAddrDecWin) + { + DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + + chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ + { + /* Check if enable bit is equal for all channels */ + if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & + XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) + { + mvOsPrintf("%s: ERR. Window enable field must be equal in " + "all channels(chan=%d)\n",__FUNCTION__, chan); + return MV_ERROR; + } + } + + + + xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); + xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; + targetAttrib.targetId = + (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; + + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + if(chanWinEn) + { + pAddrDecWin->enable = MV_TRUE; + } + else pAddrDecWin->enable = MV_FALSE; + + return MV_OK; +} + +/******************************************************************************* +* mvXorTargetWinEnable - Enable/disable a Xor address decode window +* +* DESCRIPTION: +* This function enable/disable a XOR address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling XOR accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) +{ + MV_XOR_DEC_WIN addrDecWin; + MV_U32 chan; + + /* Parameter checking */ + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { + /* Get current window */ + if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) + { + DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); + return MV_ERROR; + } + + /* Check for overlapping */ + if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) + { + /* Overlap detected */ + DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); + return MV_ERROR; + } + + /* No Overlap. Enable address decode target window */ + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + + } + else + { + /* Disable address decode target window */ + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + + } + + return MV_OK; +} + +/******************************************************************************* +* mvXorSetProtWinSet - Configure access attributes of a XOR engine +* to one of the XOR memory windows. +* +* DESCRIPTION: +* Each engine can be configured with access attributes for each of the +* memory spaces. This function sets access attributes +* to a given window for the given engine +* +* INPUTS: +* chan - One of the possible engines. +* winNum - One of the possible XOR memory spaces. +* access - Protection access rights. +* write - Write rights. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, + MV_BOOL write) +{ + MV_U32 temp; + + /* Parameter checking */ + if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) + { + DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); + return MV_BAD_PARAM; + } + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + + temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & + (~XEXWCR_WIN_ACC_MASK(winNum)); + + /* if access is disable */ + if (!access) + { + /* disable access */ + temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); + } + /* if access is enable */ + else + { + /* if write is enable */ + if (write) + { + /* enable write */ + temp |= XEXWCR_WIN_ACC_RW(winNum); + } + /* if write is disable */ + else + { + /* disable write */ + temp |= XEXWCR_WIN_ACC_RO(winNum); + } + } + MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); + return MV_OK; +} + +/******************************************************************************* +* mvXorPciRemap - Set XOR remap register for PCI address windows. +* +* DESCRIPTION: +* only Windows 0-3 can be remapped. +* +* INPUT: +* winNum - window number +* pAddrDecWin - pointer to address space window structure +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) +{ + /* Parameter checking */ + if (winNum >= XOR_MAX_REMAP_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + + MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); + + return MV_OK; +} + +/******************************************************************************* +* xorWinOverlapDetect - Detect XOR address windows overlaping +* +* DESCRIPTION: +* An unpredicted behaviour is expected in case XOR address decode +* windows overlaps. +* This function detects XOR address decode windows overlaping of a +* specified window. The function does not check the window itself for +* overlaping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex,chan; + MV_XOR_DEC_WIN addrDecWin; + + if (pAddrWin == NULL) + { + DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); + + for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) + { + /* Do not check window itself */ + if (winNumIndex == winNum) + { + continue; + } + + /* Do not check disabled windows */ + if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) + { + DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + } + + return MV_FALSE; +} + +static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) +{ + MV_XOR_DEC_WIN win; + int i; + + mvOsOutput( "\n" ); + mvOsOutput( "XOR %d:\n", unit ); + mvOsOutput( "----\n" ); + + for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + +/******************************************************************************* +* mvXorAddrDecShow - Print the XOR address decode map. +* +* DESCRIPTION: +* This function print the XOR address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvXorAddrDecShow(MV_VOID) +{ + int i; +#if defined (MV78200) + if (mvSocUnitIsMappedToThisCpu(XOR) == MV_FALSE) + return; +#endif + + for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) + mvXorAddrDecShowUnit(i); + +} + +/******************************************************************************* +* mvXorAllStop - Stop any XOR activity. +* +* DESCRIPTION: +* This function stops any XOR activity. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvXorAllStop(MV_VOID) +{ + MV_U32 xorChanNum; + + /* Abort any XOR activity */ + for(xorChanNum = 0; xorChanNum < MV_XOR_MAX_CHAN; xorChanNum++) + { + mvXorCommandSet(xorChanNum, MV_STOP); + } + + return; +} + + diff --git a/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysXor.h b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysXor.h new file mode 100644 index 0000000..c7b7075 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/ctrlEnv/sys/mvSysXor.h @@ -0,0 +1,141 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCMVSysXorh +#define __INCMVSysXorh + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ctrlEnv/sys/mvCpuIf.h" + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ +#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ + +/* XOR Engine Address Decoding Register Map */ +#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) +#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) +#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) +#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) + +/* XOR Engine [0..1] Window Control Registers (XExWCR) */ +#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) +#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) +#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) +#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) + +#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) +#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) + +/* XOR Engine Base Address Registers (XEBARx) */ +#define XEBARX_TARGET_OFFS (0) +#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) +#define XEBARX_ATTR_OFFS (8) +#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) +#define XEBARX_BASE_OFFS (16) +#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) + +/* XOR Engine Size Mask Registers (XESMRx) */ +#define XESMRX_SIZE_MASK_OFFS (16) +#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) + +/* XOR Engine High Address Remap Register (XEHARRx1) */ +#define XEHARRX_REMAP_OFFS (0) +#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) + +typedef struct _mvXorDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_XOR_DEC_WIN; + +MV_STATUS mvXorInit (MV_VOID); +MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, + MV_XOR_DEC_WIN *pAddrDecWin); +MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, + MV_XOR_DEC_WIN *pAddrDecWin); +MV_STATUS mvXorTargetWinEnable(MV_U32 unit, + MV_U32 winNum, MV_BOOL enable); +MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, + MV_BOOL write); +MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); + +MV_VOID mvXorAddrDecShow(MV_VOID); +MV_VOID mvXorAllStop(MV_VOID); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/board/mv_feroceon/mv_dd/dd_family/device/mvDevice.c b/board/mv_feroceon/mv_dd/dd_family/device/mvDevice.c new file mode 100644 index 0000000..94a4496 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/device/mvDevice.c @@ -0,0 +1,375 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvTypes.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "device/mvDevice.h" + +/* defines */ +#ifdef DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + + + +/******************************************************************************* +* mvDevPramSet - Set device interface bank parameters +* +* DESCRIPTION: +* This function sets a device bank parameters to a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* *pDevParams - Device bank parameter struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam = 0; + /* check parameters */ + if (device >= MV_DEV_MAX_CS) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + + } + if (pDevParams->turnOff > MAX_DBP_TURNOFF) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->turnOff out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2First > MAX_DBP_ACC2FIRST) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->acc2First out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2Next > MAX_DBP_ACC2NEXT) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->acc2Next out of range\n")); + return MV_ERROR; + } + if (pDevParams->ale2Wr > MAX_DBP_ALE2WR) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrLow > MAX_DBP_WRLOW) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrHigh > MAX_DBP_WRHIGH) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->ale2Wr out of range\n")); + return MV_ERROR; + } + if ((pDevParams->badrSkew << DBP_BADRSKEW_OFFS) > DBP_BADRSKEW_2CYCLE ) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->badrSkew out of range\n")); + return MV_ERROR; + } + if ((pDevParams->deviceWidth != 8 )&& + (pDevParams->deviceWidth != 16 )) + { +#if defined(MV78XX0) + if (pDevParams->deviceWidth != 32) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth out of range\n")); + return MV_ERROR; + } +#endif + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth out of range\n")); + return MV_ERROR; + } + + /* devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); */ + /* Bit 31 must be 1 */ +#if !defined(MV78XX0) + devParam = DEV_BANK_PARAM_REG_DV; +#endif + /* setting values */ + devParam |= DBP_TURNOFF_SET(pDevParams->turnOff); + devParam |= DBP_ACC2FIRST_SET(pDevParams->acc2First); + devParam |= DBP_ACC2NEXT_SET(pDevParams->acc2Next); +#if !defined(MV78XX0) + devParam |= DBP_ALE2WR_SET(pDevParams->ale2Wr); + devParam |= DBP_WRLOW_SET(pDevParams->wrLow); + devParam |= DBP_WRHIGH_SET(pDevParams->wrHigh); +#endif + devParam |= ((pDevParams->badrSkew & DBP_BADRSKEW_MASK) << DBP_BADRSKEW_OFFS); + + switch (pDevParams->deviceWidth) + { + case 8: + devParam |= DBP_DEVWIDTH_8BIT; + break; + case 16: + devParam |= DBP_DEVWIDTH_16BIT; + break; +#if defined(MV78XX0) + case 32: + devParam |= DBP_DEVWIDTH_32BIT; + break; +#endif + default: + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth non valid value\n")); + return MV_ERROR; + break; + } + + MV_REG_WRITE(DEV_BANK_PARAM_REG(device),devParam); + +#if defined(MV78XX0) + devParam = 0; + devParam |= DBP_ALE2WR_SET(pDevParams->ale2Wr); + devParam |= DBP_WRLOW_SET(pDevParams->wrLow); + devParam |= DBP_WRHIGH_SET(pDevParams->wrHigh); + MV_REG_WRITE(DEV_BANK_PARAM_REG_WR(device),devParam); +#endif + + return MV_OK; +} + +/******************************************************************************* +* mvDevPramget - Get device interface bank parameters +* +* DESCRIPTION: +* This function retrieves a device bank parameter settings. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* *pDevParams - Device bank parameter struct. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam = 0; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + pDevParams->turnOff = DBP_TURNOFF_GET(devParam); + pDevParams->acc2First = DBP_ACC2FIRST_GET(devParam); + pDevParams->acc2Next = DBP_ACC2NEXT_GET(devParam); +#if !defined(MV78XX0) + pDevParams->ale2Wr = DBP_ALE2WR_GET(devParam); + pDevParams->wrLow = DBP_WRLOW_GET(devParam); + pDevParams->wrHigh = DBP_WRHIGH_GET(devParam); +#endif + pDevParams->badrSkew = (devParam & DBP_BADRSKEW_MASK) >> DBP_BADRSKEW_OFFS; + + switch (devParam & DBP_DEVWIDTH_MASK) + { + case DBP_DEVWIDTH_8BIT: + pDevParams->deviceWidth=8; + break; + case DBP_DEVWIDTH_16BIT: + pDevParams->deviceWidth=16; + break; +#if defined(MV78XX0) + case DBP_DEVWIDTH_32BIT: + pDevParams->deviceWidth=32; + break; +#endif + default: + DB(mvOsPrintf("mvDevIfPramSet: ERR. pDevParams->deviceWidth non valid value\n")); + return MV_ERROR; + break; + } + +#if defined(MV78XX0) + devParam = MV_REG_READ(DEV_BANK_PARAM_REG_WR(device)); + pDevParams->ale2Wr = DBP_ALE2WR_GET(devParam); + pDevParams->wrLow = DBP_WRLOW_GET(devParam); + pDevParams->wrHigh = DBP_WRHIGH_GET(devParam); +#endif + + return MV_OK; +} + +/******************************************************************************* +* mvDevWidthGet - Get device width parameter +* +* DESCRIPTION: +* This function gets width parameter of a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* Device width in bytes. +* +*******************************************************************************/ +MV_U32 mvDevWidthGet(MV_DEVICE device) +{ + MV_U32 devParam; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + devParam = (devParam & DBP_DEVWIDTH_MASK) >> DBP_DEVWIDTH_OFFS; + + return (MV_U32)(0x8 << devParam); + +} + +/******************************************************************************* +* mvDevNandDevCsSet - Set NAND chip-select, care mode and init sequence +* +* DESCRIPTION: +* This function set the NAND flash controller registers with NAND +* device chip-select. +* +* INPUT: +* devNum - Device number. See MV_DEVICE enumerator. +* careMode - NAND device care mode (0 = Don't care, '1' = care). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvDevNandDevCsSet(MV_DEVICE device, MV_BOOL careMode) +{ + MV_U32 nfCtrlReg; /* NAND Flash Control Register */ + + /* Set chip select */ + nfCtrlReg = MV_REG_READ(DEV_NAND_CTRL_REG); + + nfCtrlReg |= (DINFCR_NF_CS_MASK(device)); + + if (careMode) + nfCtrlReg |= (DINFCR_NF_ACT_CE_MASK(device)); + else + nfCtrlReg &= ~(DINFCR_NF_ACT_CE_MASK(device)); + + + MV_REG_WRITE(DEV_NAND_CTRL_REG, nfCtrlReg); +} + +/******************************************************************************* +* mvDevNandDevCsGet - Get NAND chip-select. +* +* DESCRIPTION: +* This function get the NAND flash chip-select. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Nand device chip-select. +* +*******************************************************************************/ +MV_32 mvDevNandDevCsGet(MV_VOID) +{ + MV_U32 nfCtrlReg; /* NAND Flash Control Register */ + MV_U32 cs = MV_NAND_CS; + + nfCtrlReg = MV_REG_READ(DEV_NAND_CTRL_REG); + if (mvBoardIsBootFromNand() && (mvBoardIdGet() == DB_78XX0_ID)) + cs = BOOT_CS; + nfCtrlReg &= (DINFCR_NF_CS_MASK(cs)); + + if (nfCtrlReg) + return cs; + else + return 0xffffffff; + +} + diff --git a/board/mv_feroceon/mv_dd/dd_family/device/mvDevice.h b/board/mv_feroceon/mv_dd/dd_family/device/mvDevice.h new file mode 100644 index 0000000..d8a9d75 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/device/mvDevice.h @@ -0,0 +1,102 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvDeviceH +#define __INCmvDeviceH + +#include "device/mvDeviceRegs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* This structure describes device interface parameters to be assigned to */ +/* device bank parameter */ +typedef struct _mvDeviceParam +{ /* boundary values */ + MV_U32 turnOff; /* 0x0 - 0xf */ + MV_U32 acc2First; /* 0x0 - 0x1f */ + MV_U32 acc2Next; /* 0x0 - 0x1f */ + MV_U32 ale2Wr; /* 0x0 - 0xf */ + MV_U32 wrLow; /* 0x0 - 0xf */ + MV_U32 wrHigh; /* 0x0 - 0xf */ + MV_U32 badrSkew; /* 0x0 - 0x2 */ + MV_U32 deviceWidth; /* in Bytes */ +} MV_DEVICE_PARAM; + + +/* mvDevPramSet - Set device interface bank parameters */ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevPramget - Get device interface bank parameters */ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevWidthGet - Get device width parameter*/ +MV_U32 mvDevWidthGet(MV_DEVICE device); + +/* mvDevNandDevCsSet - Set the NAND flash control registers with NAND device- */ +/* select and care mode */ +MV_VOID mvDevNandDevCsSet(MV_DEVICE device, MV_BOOL careMode); + +/* mvDevNandDevCsGet - Get the NAND flash chip-select */ +MV_32 mvDevNandDevCsGet(MV_VOID); + +#endif /* #ifndef __INCmvDeviceH */ diff --git a/board/mv_feroceon/mv_dd/dd_family/device/mvDeviceRegs.h b/board/mv_feroceon/mv_dd/dd_family/device/mvDeviceRegs.h new file mode 100644 index 0000000..60300a7 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/device/mvDeviceRegs.h @@ -0,0 +1,265 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvDeviceRegsH +#define __INCmvDeviceRegsH + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define MV_DEVICE_MAX_XBAR_TIMEOUT 0x0FFF +#define DEV_BANK_PARAM_REG_DV 0x80000000 +/* registers offsets */ + +static INLINE MV_U32 DEV_BANK_PARAM_REG(int num) +{ + switch(num) + { + case (BOOT_CS): + return DEVICE_BUS_BASE + 0x400; + case (DEV_CS0): + return DEVICE_BUS_BASE + 0x408; + case (DEV_CS1): + return DEVICE_BUS_BASE + 0x410; + case (DEV_CS2): + return DEVICE_BUS_BASE + 0x418; + case (DEV_CS3): + return DEVICE_BUS_BASE + 0x420; + default: + return 0xFFFFFFFF; + + } +} + +#define DEV_BANK_PARAM_REG_WR(num) (DEV_BANK_PARAM_REG(num)+0x4) +#define DEV_NAND_CTRL_REG (DEVICE_BUS_BASE + 0x0470) + +/* Device Bank Parameters register fields (DBP_REG)*/ +/* Boot Device Bank Parameters (DBP) register fields (DEV_BOOT_BANK_PARAM_REG)*/ +/* DBP_XXX_MASK_HIGH is the offset of the extend bit from the msb of the input value */ + +#define DBP_TURNOFF_OFFS_LOW 0 +#define DBP_TURNOFF_MASK_LOW 0x3F +#define MAX_DBP_TURNOFF 0xf + + +#define DBP_TURNOFF_SET(value) \ +((value & DBP_TURNOFF_MASK_LOW) << DBP_TURNOFF_OFFS_LOW) + +#define DBP_TURNOFF_GET(value) \ +((value >> DBP_TURNOFF_OFFS_LOW) & DBP_TURNOFF_MASK_LOW) + +#define DBP_ACC2FIRST_OFFS_LOW 6 +#define DBP_ACC2FIRST_MASK_LOW 0x3f +#define MAX_DBP_ACC2FIRST 0x3f + +#define DBP_ACC2FIRST_SET(value) \ +((value & DBP_ACC2FIRST_MASK_LOW) << DBP_ACC2FIRST_OFFS_LOW) + +#define DBP_ACC2FIRST_GET(value) \ +((value >> DBP_ACC2FIRST_OFFS_LOW) & DBP_ACC2FIRST_MASK_LOW) + +#define DBP_ACC2NEXT_OFFS_LOW 17 +#define DBP_ACC2NEXT_MASK_LOW 0x3f +#define MAX_DBP_ACC2NEXT 0x3f + +#define DBP_ACC2NEXT_SET(value) \ +((value & DBP_ACC2FIRST_MASK_LOW) << DBP_ACC2FIRST_OFFS_LOW) + +#define DBP_ACC2NEXT_GET(value) \ +((value >> DBP_ACC2NEXT_OFFS_LOW) & DBP_ACC2NEXT_MASK_LOW) + +#define DBP_DEVWIDTH_OFFS 30 /* Device Width */ +#define DBP_DEVWIDTH_MASK (0x3 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_8BIT (0x0 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_16BIT (0x1 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_32BIT (0x2 << DBP_DEVWIDTH_OFFS) + +#define DBP_BADRSKEW_OFFS 28 +#define DBP_BADRSKEW_MASK (0x3 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_NOGAP (0x0 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_1CYCLE (0x1 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_2CYCLE (0x2 << DBP_BADRSKEW_OFFS) + +#define DBP_ALE2WR_OFFS_LOW 0 +#define DBP_ALE2WR_MASK_LOW 0x3f +#define MAX_DBP_ALE2WR 0x3F + + +#define DBP_ALE2WR_SET(value) \ +((value & DBP_ALE2WR_MASK_LOW) << DBP_ALE2WR_OFFS_LOW) + +#define DBP_ALE2WR_GET(value) \ +((value >> DBP_ALE2WR_OFFS_LOW) & DBP_ALE2WR_MASK_LOW) + +#define DBP_WRLOW_OFFS_LOW 8 +#define DBP_WRLOW_MASK_LOW 0x3F +#define MAX_DBP_WRLOW 0x3F + +#define DBP_WRLOW_SET(value) \ +((value & DBP_WRLOW_MASK_LOW) << DBP_WRLOW_OFFS_LOW) + +#define DBP_WRLOW_GET(value) \ +((value >> DBP_WRLOW_OFFS_LOW) & DBP_WRLOW_MASK_LOW) + +#define DBP_WRHIGH_OFFS_LOW 16 +#define DBP_WRHIGH_MASK_LOW 0x3F +#define MAX_DBP_WRHIGH 0x3F + +#define DBP_WRHIGH_SET(value) \ +((value & DBP_WRHIGH_MASK_LOW) << DBP_WRHIGH_OFFS_LOW) + +#define DBP_WRHIGH_GET(value) \ +((value >> DBP_WRHIGH_OFFS_LOW) & DBP_WRHIGH_MASK_LOW) + + +/* Device Interface Control register fields (DIC) (DIC_REG)*/ +#define DIC_TIMEOUT_OFFS 0 /* Timeout Timer Preset Value. */ +#define DIC_TIMEOUT_MASK (0xffff << DIC_TIMEOUT_OFFS) +#define MAX_DIC_TIMEOUT 0xffff + +/* NAND Flash Control register fields (NF) (NF_REG)*/ +#define NF_BOOTCS_OFFS 0 /* Define if BOOTCS is connected to NAND Flash */ +#define NF_BOOT_MASK (1 << NF_BOOTCS_OFFS) +#define NF_BOOT_NC (0 << NF_BOOTCS_OFFS) +#define NF_BOOT_C (1 << NF_BOOTCS_OFFS) + +#define NF_BOOTCS_CE_ACT_OFFS 1 /* Define if NAND Flash on BOOTCS is CE care or CE don't care */ +#define NF_BOOTCS_CE_ACT_MASK (1 << NF_BOOTCS_CE_ACT_OFFS) +#define NF_BOOTCS_CE_ACT_NCARE (0 << NF_BOOTCS_CE_ACT_OFFS) +#define NF_BOOTCS_CE_ACT_CARE (1 << NF_BOOTCS_CE_ACT_OFFS) + +#define NF_CS0_OFFS 2 /* Define if CS0 is connected to NAND Flash */ +#define NF_CS0_MASK (1 << NF_CS0_OFFS) +#define NF_CS0_NC (0 << NF_CS0_OFFS) +#define NF_CS0_C (1 << NF_CS0_OFFS) + +#define NF_CS0_CE_ACT_OFFS 3 /* Define if NAND Flash on CS0 is CE care or CE don't care */ +#define NF_CS0_CE_ACT_MASK (1 << NF_CS0_CE_ACT_OFFS) +#define NF_CS0_CE_ACT_NCARE (0 << NF_CS0_CE_ACT_OFFS) +#define NF_CS0_CE_ACT_CARE (1 << NF_CS0_CE_ACT_OFFS) + +#define NF_CS1_OFFS 4 /* Define if CS1 is connected to NAND Flash */ +#define NF_CS1_MASK (1 << NF_CS1_OFFS) +#define NF_CS1_NC (0 << NF_CS1_OFFS) +#define NF_CS1_C (1 << NF_CS1_OFFS) + +#define NF_CS1_CE_ACT_OFFS 5 /* Define if NAND Flash on CS1 is CE care or CE don't care */ +#define NF_CS1_CE_ACT_MASK (1 << NF_CS1_CE_ACT_OFFS) +#define NF_CS1_CE_ACT_NCARE (0 << NF_CS1_CE_ACT_OFFS) +#define NF_CS1_CE_ACT_CARE (1 << NF_CS1_CE_ACT_OFFS) + +#define NF_CS2_OFFS 6 /* Define if CS2 is connected to NAND Flash */ +#define NF_CS2_MASK (1 << NF_CS2_OFFS) +#define NF_CS2_NC (0 << NF_CS2_OFFS) +#define NF_CS2_C (1 << NF_CS2_OFFS) + +#define NF_CS2_CE_ACT_OFFS 7 /* Define if NAND Flash on CS2 is CE care or CE don't care */ +#define NF_CS2_CE_ACT_MASK (1 << NF_CS2_CE_ACT_OFFS) +#define NF_CS2_CE_ACT_NCARE (0 << NF_CS2_CE_ACT_OFFS) +#define NF_CS2_CE_ACT_CARE (1 << NF_CS2_CE_ACT_OFFS) + +#define NF_INIT_SEQ_OFFS 8 /* NAND Flash initialization sequence */ +#define NF_INIT_SEQ_MASK (1 << NF_INIT_SEQ_OFFS) +#define NF_INIT_SEQ_EN (0 << NF_INIT_SEQ_OFFS) +#define NF_INIT_SEQ_DIS (1 << NF_INIT_SEQ_OFFS) + +#define NF_OE_HIGHW_OFFS 9 /* NAND Flash OE high width in core clocks units (value + 1) */ +#define NF_OE_HIGHW_MASK (0x1f << NF_OE_HIGHW_OFFS) +#define MAX_OE_HIGHW (0x1f << NF_OE_HIGHW_OFFS) + +#define NF_TREADY_OFFS 14 /* NAND Flash time ready in core clocks units (value + 1) */ +#define NF_TREADY_MASK (0x1f << NF_TREADY_OFFS) +#define MAX_TREADY (0x1f << NF_TREADY_OFFS) + +#define NF_OE_TCTRL_OFFS 19 /* NAND Flash OE toggle control */ +#define NF_OE_TCTRL_MASK (1 << NF_OE_TCTRL_OFFS) +#define NF_OE_TCTRL_1_CYC_AFT (0 << NF_OE_TCTRL_OFFS) +#define NF_OE_TCTRL_SAME_CYC (1 << NF_OE_TCTRL_OFFS) + +#define NF_CS3_OFFS 20 /* Define if CS3 is connected to NAND Flash */ +#define NF_CS3_MASK (1 << NF_CS3_OFFS) +#define NF_CS3_NC (0 << NF_CS3_OFFS) +#define NF_CS3_C (1 << NF_CS3_OFFS) + +#define NF_CS3_CE_ACT_OFFS 21 /* Define if NAND Flash on CS3 is CE care or CE don't care */ +#define NF_CS3_CE_ACT_MASK (1 << NF_CS3_CE_ACT_OFFS) +#define NF_CS3_CE_ACT_NCARE (0 << NF_CS3_CE_ACT_OFFS) +#define NF_CS3_CE_ACT_CARE (1 << NF_CS3_CE_ACT_OFFS) + + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) \ +(csNum == BOOT_CS) ? 0x1 : ((csNum == DEV_CS3) ? (0x1 << 20) : (0x1 << (((csNum+1) % MV_DEV_MAX_CS) * 2))) + + +#define DINFCR_NF_ACT_CE_MASK(csNum) \ +(csNum == DEV_CS3) ? (0x2 << 20) : (0x2 << (((csNum+1) % MV_DEV_MAX_CS) * 2)) + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* #ifndef __INCmvDeviceRegsH */ diff --git a/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSemaphore.c b/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSemaphore.c new file mode 100644 index 0000000..e5cd103 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSemaphore.c @@ -0,0 +1,114 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "mv78200/mvSemaphore.h" + + +MV_BOOL mvSemaLock(MV_32 num) +{ + MV_U32 tmp; + MV_U32 cpuId; + if (num > MV_MAX_SEMA) + { + mvOsPrintf("Invalid semaphore number\n"); + return MV_FALSE; + } + cpuId = whoAmI(); + do + { + tmp = MV_REG_BYTE_READ(MV_SEMA_REG_BASE+num); + } while ((tmp & 0xFF) != cpuId); + return MV_TRUE; +} + +MV_BOOL mvSemaTryLock(MV_32 num) +{ + MV_U32 tmp; + if (num > MV_MAX_SEMA) + { + mvOsPrintf("Invalid semaphore number\n"); + return MV_FALSE; + } + tmp = MV_REG_BYTE_READ(MV_SEMA_REG_BASE+num); + if ((tmp & 0xFF) != whoAmI()) + { + return MV_FALSE; + } + else + return MV_TRUE; +} + +MV_BOOL mvSemaUnlock(MV_32 num) +{ + if (num > MV_MAX_SEMA) + { + mvOsPrintf("Invalid semaphore number\n"); + return MV_FALSE; + } + MV_REG_BYTE_WRITE(MV_SEMA_REG_BASE+(num), 0xFF); + return MV_TRUE; +} diff --git a/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSemaphore.h b/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSemaphore.h new file mode 100644 index 0000000..a225ce6 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSemaphore.h @@ -0,0 +1,79 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef mvsemaphore_h +#define mvsemaphore_h + +#define MV_SEMA_REG_BASE (0x20500) +#define MV_MAX_SEMA 128 +#define MV_SEMA_SMI 50 +#define MV_SEMA_RTC 51 +#define MV_SEMA_NOR_FLASH 0 +#define MV_SEMA_BOOT 1 +#ifndef MV_ASMLANGUAGE +MV_BOOL mvSemaLock(MV_32 num); +MV_BOOL mvSemaTryLock(MV_32 num); +MV_BOOL mvSemaUnlock(MV_32 num); +#endif + +#endif diff --git a/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSocUnitMap.c b/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSocUnitMap.c new file mode 100644 index 0000000..399a8d1 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSocUnitMap.c @@ -0,0 +1,248 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "mv78200/mvSocUnitMap.h" + + +static MV_RES_MAP mv_res_table[] = { + {0, MV_FALSE, "uart0"}, + {1, MV_FALSE, "uart1"}, + {0, MV_FALSE, "pcie0"}, + {0, MV_FALSE, "pcie1"}, + {0, MV_FALSE, "egiga0"}, + {0, MV_FALSE, "egiga1"}, + {1, MV_FALSE, "egiga2"}, + {1, MV_FALSE, "egiga3"}, + {0, MV_FALSE, "sata"}, + {0, MV_FALSE, "xor"}, + {0, MV_FALSE, "idma"}, + {0, MV_FALSE, "usb0"}, + {0, MV_FALSE, "usb1"}, + {0, MV_FALSE, "usb2"}, + {0, MV_FALSE, "cesa"}, + {0, MV_FALSE, "nor"}, + {0, MV_FALSE, "nand"}, + {0, MV_FALSE, "spi"}, + {0, MV_FALSE, "tdm"}, + {0, MV_FALSE, "twsi0"}, + {0, MV_FALSE, "twsi1"}, + {0, MV_FALSE, "Reserved0"}, + {0, MV_FALSE, "Reserved1"}, + {-1, MV_FALSE, 0}, + }; + + + + +int mvSocUnitMapGet(MV_SOC_UNIT unit) +{ + return mv_res_table[unit].cpuId; +} + +MV_BOOL mvSocUnitIsMappedToThisCpu(MV_SOC_UNIT unit) +{ +#ifdef DUAL_OS_78200 + return (mvSocUnitMapGet(unit) == whoAmI()); +#else + return MV_TRUE; +#endif +} + + +MV_VOID mvSocUnitMapSet(MV_SOC_UNIT unit, int cpuId) +{ + if (MV_TRUE == mv_res_table[unit].mapped) + { + mvOsPrintf("Warning! Unit %s is already mapped to CPU%d\n", + mv_res_table[unit].unitName, + mv_res_table[unit].cpuId); + return; + } + mv_res_table[unit].cpuId = cpuId; + mv_res_table[unit].mapped = MV_TRUE; +} + + +MV_BOOL mvSocUnitMapFillTable(char* p, int cpuId, STRSTR_FUNCPTR strstr_func) +{ + int i; + char* tmp; + const char *syntaxErr = "mvSocUnitMapFillTable: syntax error (%s)\n"; + for (i = 0; mv_res_table[i].cpuId != -1; i++) { + char *t = mv_res_table[i].unitName; + int len; + tmp = strstr_func(p, t); + if (!tmp) continue; + /*Look for delimiter*/ + if (tmp > p) { + if (tmp[-1] != ' ' && tmp[-1] != ',') { + mvOsPrintf(syntaxErr, mv_res_table[i].unitName); + continue; + } + } + while (*t++ != '\0'); + len = t - mv_res_table[i].unitName - 1; + if (tmp[len] != ' ' && tmp[len] != ',' && tmp[len] != '\0') { + mvOsPrintf(syntaxErr, mv_res_table[i].unitName); + continue; + } + mvSocUnitMapSet(i, cpuId); + } + return MV_TRUE; +} + +MV_BOOL mvSocUnitMapFillTableFormBitMap(MV_U32 flag) +{ + int i,bit,cpuId; + for (i = 0; mv_res_table[i].cpuId != -1; i++) + { + switch (i) + { + case UART0: bit=UART0_T0_CPU1; break; + case UART1: bit=UART1_TO_CPU1; break; + case PEX00: bit=PEX0_TO_CPU1; break; + case PEX10: bit=PEX1_TO_CPU1; break; + case GIGA0: bit=GIGA0_TO_CPU1; break; + case GIGA1: bit=GIGA1_TO_CPU1; break; + case GIGA2: bit=GIGA2_TO_CPU1; break; + case GIGA3: bit=GIGA3_TO_CPU1; break; + case SATA: bit=SATA_TO_CPU1; break; + case XOR: bit=XOR_TO_CPU1; break; + case IDMA: bit=IDMA_TO_CPU1; break; + case USB0: bit=USB0_TO_CPU1; break; + case USB1: bit=USB1_TO_CPU1; break; + case USB2: bit=USB2_TO_CPU1; break; + case CESA: bit=CESA_TO_CPU1; break; + case NOR_FLASH: bit=CESA_TO_CPU1; break; + case NAND_FLASH: bit=CESA_TO_CPU1; break; + case SPI_FLASH: bit=CESA_TO_CPU1; break; + case TDM: bit=TDM_TO_CPU1; break; + case TWSI0: bit=TWSI0_TO_CPU1; break; + case TWSI1: bit=TWSI1_TO_CPU1; break; + case RESERVED_0: bit=RSRVD0_TO_CPU1; break; + case RESERVED_1: bit=RSRVD1_TO_CPU1; break; + default: bit=0; break; + } + cpuId = (flag & bit) ? SLAVE_CPU:MASTER_CPU; + mvSocUnitMapSet(i, cpuId); + } + return MV_TRUE; +} + +MV_U32 mvSocUnitMapFillFlagFormTable(void) +{ + int i; + MV_U32 flag = 0; + for (i = 0; mv_res_table[i].cpuId != -1; i++) + { + if (mvSocUnitMapGet(i) == SLAVE_CPU) + { + switch (i) + { + case UART0: flag |= UART0_T0_CPU1; break; + case UART1: flag |= UART1_TO_CPU1; break; + case PEX00: flag |= PEX0_TO_CPU1; break; + case PEX10: flag |= PEX1_TO_CPU1; break; + case GIGA0: flag |= GIGA0_TO_CPU1; break; + case GIGA1: flag |= GIGA1_TO_CPU1; break; + case GIGA2: flag |= GIGA2_TO_CPU1; break; + case GIGA3: flag |= GIGA3_TO_CPU1; break; + case SATA: flag |= SATA_TO_CPU1; break; + case XOR: flag |= XOR_TO_CPU1; break; + case IDMA: flag |= IDMA_TO_CPU1; break; + case USB0: flag |= USB0_TO_CPU1; break; + case USB1: flag |= USB1_TO_CPU1; break; + case USB2: flag |= USB2_TO_CPU1; break; + case CESA: flag |= CESA_TO_CPU1; break; + case NOR_FLASH: flag |= CESA_TO_CPU1; break; + case NAND_FLASH: flag |= CESA_TO_CPU1; break; + case SPI_FLASH: flag |= CESA_TO_CPU1; break; + case TDM: flag |= TDM_TO_CPU1; break; + case TWSI0: flag |= TWSI0_TO_CPU1; break; + case TWSI1: flag |= TWSI1_TO_CPU1; break; + case RESERVED_0: flag |= RSRVD0_TO_CPU1; break; + case RESERVED_1: flag |= RSRVD1_TO_CPU1; break; + default: + break; + } + } + } + + return flag; +} + +MV_VOID mvSocUnitMapPrint(MV_8* buf) +{ + int i, count; + count = mvOsSPrintf(buf, "CPU core %d, SoC units in use:\n", whoAmI()); + for (i = 0; mv_res_table[i].cpuId != -1; i++) { + if (mv_res_table[i].cpuId == whoAmI()) { + count += mvOsSPrintf(buf+count, "%s ", mv_res_table[i].unitName); + } + } +} diff --git a/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSocUnitMap.h b/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSocUnitMap.h new file mode 100644 index 0000000..17cc504 --- /dev/null +++ b/board/mv_feroceon/mv_dd/dd_family/mv78200/mvSocUnitMap.h @@ -0,0 +1,138 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef mvifmap_h +#define mvifmap_h + +typedef enum +{ + UART0=0, + UART1, + PEX00, + PEX10, + GIGA0, + GIGA1, + GIGA2, + GIGA3, + SATA, + XOR, + IDMA, + USB0, + USB1, + USB2, + CESA, + NOR_FLASH, + NAND_FLASH, + SPI_FLASH, + TDM, + TWSI0, + TWSI1, + RESERVED_0, + RESERVED_1, + MAX_UNITS +} MV_SOC_UNIT; + +/* binary flags for mvSocUnitMapFillTableFormBitMap */ +#define UART0_T0_CPU1 0x0000001 +#define UART1_TO_CPU1 0x0000002 +#define PEX0_TO_CPU1 0x0000004 +#define PEX1_TO_CPU1 0x0000008 +#define GIGA0_TO_CPU1 0x0000010 +#define GIGA1_TO_CPU1 0x0000020 +#define GIGA2_TO_CPU1 0x0000040 +#define GIGA3_TO_CPU1 0x0000080 +#define SATA_TO_CPU1 0x0000100 +#define XOR_TO_CPU1 0x0000200 +#define IDMA_TO_CPU1 0x0000400 +#define USB0_TO_CPU1 0x0000800 +#define USB1_TO_CPU1 0x0001000 +#define USB2_TO_CPU1 0x0002000 +#define CESA_TO_CPU1 0x0004000 +#define NOR_TO_CPU1 0x0008000 +#define NAND_TO_CPU1 0x0010000 +#define SPI_TO_CPU1 0x0020000 +#define TDM_TO_CPU1 0x0040000 +#define TWSI0_TO_CPU1 0x0080000 +#define TWSI1_TO_CPU1 0x0100000 +#define RSRVD0_TO_CPU1 0x0200000 +#define RSRVD1_TO_CPU1 0x0400000 + +#define CPU1_DEFAULT_INTERFACE (UART1_TO_CPU1 | PEX1_TO_CPU1 | GIGA2_TO_CPU1 | GIGA3_TO_CPU1 | IDMA_TO_CPU1 | USB1_TO_CPU1 | TWSI1_TO_CPU1) + +typedef struct __MV_RES_MAP +{ + int cpuId; + MV_BOOL mapped; + char* unitName; +} MV_RES_MAP; + +typedef char *(*STRSTR_FUNCPTR)(const char *s1, const char *s2); + +MV_BOOL mvSocUnitIsMappedToThisCpu(MV_SOC_UNIT unit); +int mvSocUnitMapGet(MV_SOC_UNIT unit); +MV_VOID mvSocUnitMapSet(MV_SOC_UNIT unit, int cpuId); +MV_BOOL mvSocUnitMapFillTable(char* p, int cpuId, STRSTR_FUNCPTR func); +MV_VOID mvSocUnitMapPrint(MV_8* buf); +MV_BOOL mvSocUnitMapFillTableFormBitMap(MV_U32 flag); +MV_U32 mvSocUnitMapFillFlagFormTable(void); +#endif diff --git a/board/mv_feroceon/mv_dd/mvSysHwConfig.h b/board/mv_feroceon/mv_dd/mvSysHwConfig.h new file mode 100644 index 0000000..796632b --- /dev/null +++ b/board/mv_feroceon/mv_dd/mvSysHwConfig.h @@ -0,0 +1,738 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmvSysHwConfigh +#define __INCmvSysHwConfigh +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ + +#define MV_INCLUDE_PEX +#define MV_INCLUDE_GIG_ETH +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_CLK_PWR_CNTRL +#define MV_INCLUDE_INTEG_SATA +#ifndef MV_TINY_IMAGE +#define MV_INCLUDE_SATA +#define MV_INCLUDE_IDMA +#define MV_INCLUDE_XOR +#define MV_INCLUDE_SPI +#define MV_INCLUDE_USB +#endif +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NOR Flash support */ +#define MV_INC_BOARD_NOR_FLASH +#ifndef MV_TINY_IMAGE +/* On-Board PCI\PEX SATA driver*/ +#define MV_INC_BOARD_PCI_SATA +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board SPI Flash support */ +#define MV_INC_BOARD_SPI_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC +#endif + +#if defined(DB_MV78XX0) || defined (DB_MV88F632X) +#define CFG_DRAM_BANKS 4 +#elif defined(RD_MV78XX0_AMC) +#define PCIE_VIRTUAL_BRIDGE_SUPPORT +#define MV_STATIC_DRAM_ON_BOARD +#define CFG_DRAM_BANKS 1 +#elif defined(RD_MV78XX0_PCAC) +#define MV_STATIC_DRAM_ON_BOARD +#define CFG_DRAM_BANKS 1 +#elif defined(RD_MV78XX0_MASA) +#define CFG_DRAM_BANKS 2 +#define CFG_NO_FLASH +#undef MV_INC_BOARD_NOR_FLASH +#define CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_NAND +#elif defined(RD_MV78XX0_H3C) +#define MV_STATIC_DRAM_ON_BOARD +#define CFG_DRAM_BANKS 1 +#define AMD_FLASH_16BIT_IN_8BIT_MODE +#endif + +/************************************************/ +/* U-Boot Specific */ +/************************************************/ +#ifndef MV_TINY_IMAGE +#define MV_INCLUDE_MONT_EXT +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#endif +#endif + + +#define MV_CACHEABLE(address) ((address) | 0x80000000) + +/* includes */ +#define _1K 0x00000400 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _8M + +#define SDRAM_CS1_BASE 0x00800000 +#define SDRAM_CS1_SIZE _8M + +#define SDRAM_CS2_BASE 0x01000000 +#define SDRAM_CS2_SIZE _8M + +#define SDRAM_CS3_BASE 0x01800000 +#define SDRAM_CS3_SIZE _8M + +/* PCI/PEX: IO and memory size */ +#define PCIx_IO_SIZE _1M +#define PCIx_MEM0_SIZE _32M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ + +/* PCI0: IO and memory space */ +#define PCI0_IO_BASE 0xf0000000 +#define PCI0_IO_SIZE _1M +#define PCI0_MEM0_BASE 0xc0000000 +#define PCI0_MEM0_ME_BASE 0x90000000 +#define PCI0_MEM0_SIZE _64M +#define PCI0_MEM0_ME_SIZE _32M + +/* PCI1: IO and memory space */ +#define PCI1_IO_BASE 0xf0100000 +#define PCI1_IO_SIZE _1M +#define PCI1_MEM0_BASE 0xc4000000 +#define PCI1_MEM0_ME_BASE 0x92000000 +#define PCI1_MEM0_SIZE _64M +#define PCI1_MEM0_ME_SIZE _32M + +/* PCI2: IO and memory space */ +#define PCI2_IO_BASE 0xf0200000 +#define PCI2_IO_SIZE _1M +#define PCI2_MEM0_BASE 0xd0000000 +#define PCI2_MEM0_ME_BASE 0x94000000 +#define PCI2_MEM0_SIZE _64M +#define PCI2_MEM0_ME_SIZE _32M + +/* PCI3: IO and memory space */ +#define PCI3_IO_BASE 0xf0300000 +#define PCI3_IO_SIZE _1M +#define PCI3_MEM0_BASE 0xcc000000 +#define PCI3_MEM0_ME_BASE 0x96000000 +#define PCI3_MEM0_SIZE _64M +#define PCI3_MEM0_ME_SIZE _32M + +/* PCI4: IO and memory space */ +#define PCI4_IO_BASE 0xf0400000 +#define PCI4_IO_SIZE _1M +#define PCI4_MEM0_BASE 0xc8000000 +#define PCI4_MEM0_ME_BASE 0x98000000 +#define PCI4_MEM0_SIZE _64M +#define PCI4_MEM0_ME_SIZE _32M + +/* PCI5: IO and memory space */ +#define PCI5_IO_BASE 0 +#define PCI5_IO_SIZE 0 +#define PCI5_MEM0_BASE 0xd4000000 +#define PCI5_MEM0_ME_BASE 0x9A000000 +#define PCI5_MEM0_SIZE _64M +#define PCI5_MEM0_ME_SIZE _32M + +/* PCI6: IO and memory space */ +#define PCI6_IO_BASE 0 +#define PCI6_IO_SIZE 0 +#define PCI6_MEM0_BASE 0xd8000000 +#define PCI6_MEM0_ME_BASE 0x9C000000 +#define PCI6_MEM0_SIZE _64M +#define PCI6_MEM0_ME_SIZE _32M + +/* PCI7: IO and memory space */ +#define PCI7_IO_BASE 0 +#define PCI7_IO_SIZE 0 +#define PCI7_MEM0_BASE 0xdc000000 +#define PCI7_MEM0_ME_BASE 0x9E000000 +#define PCI7_MEM0_SIZE _64M +#define PCI7_MEM0_ME_SIZE _32M + +/* Crypto memory space */ +#define CRYPTO_BASE 0xd8000000 +#define CRYPTO_SIZE _1M + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xf1000000 /*0x14000000*/ +/* #define IDMA_INTER_REGS_BASE 0xf1060000 0x14000000 */ + +/* Device: CS0 - 32MB 32bit FLASH, CS1 - 7seg, CS2 - NAND, CS3 - SPI */ +#ifdef MV78200 +#define DEVICE_CS0_BASE 0xf8000000 +#define DEVICE_CS0_SIZE _1M + +#define DEVICE_CS1_BASE 0xf9000000 +#define DEVICE_CS1_SIZE _1M + +#define DEVICE_CS2_BASE 0xfc000000 +#define DEVICE_CS2_SIZE _8M + +#define DEVICE_CS3_BASE 0xfd000000 +#define DEVICE_CS3_SIZE _1M +#else +#define DEVICE_CS0_BASE 0xf8000000 +#define DEVICE_CS0_SIZE _1M + +#define DEVICE_CS1_BASE 0xf9000000 +#define DEVICE_CS1_SIZE _1M + +#define DEVICE_CS2_BASE 0xfc000000 +#define DEVICE_CS2_SIZE _1M + +#define DEVICE_CS3_BASE 0xfd000000 +#define DEVICE_CS3_SIZE _8M +#endif + +#define BOOTDEV_CS_BASE ((0xFFFFFFFF - BOOTDEV_CS_SIZE) + 1) + +#ifdef MV78200 +#define DEVICE_SPI_BASE DEVICE_CS2_BASE +#define DEVICE_SPI_SIZE DEVICE_CS2_SIZE +#else +#define DEVICE_SPI_BASE DEVICE_CS3_BASE +#define DEVICE_SPI_SIZE DEVICE_CS3_SIZE +#endif + +#ifdef MV632X +#undef DEVICE_SPI_BASE +#undef DEVICE_SPI_SIZE +#undef BOOTDEV_CS_BASE +#ifdef MV_NAND_BOOT +#define DEVICE_SPI_BASE DEVICE_CS2_BASE +#define DEVICE_SPI_SIZE _8M +#define BOOTDEV_CS_BASE ((0xFFFFFFFF - BOOTDEV_CS_SIZE) + 1) +#else /*MV_NAND_BOOT*/ +#define DEVICE_SPI_BASE ((0xFFFFFFFF - _8M) + 1) +#define DEVICE_SPI_SIZE _8M +#define BOOTDEV_CS_BASE DEVICE_CS2_BASE +#endif /*MV_NAND_BOOT*/ +#endif /* MV632X */ + +#if defined(MV_NAND_BOOT) + +#define BOOTDEV_CS_SIZE _512K + +#elif defined(MV_BOOTSIZE_256K) + +#define BOOTDEV_CS_SIZE _256K + +#elif defined(MV_BOOTSIZE_512K) + +#define BOOTDEV_CS_SIZE _512K + +#elif defined(MV_BOOTSIZE_4M) + +#define BOOTDEV_CS_SIZE _4M + +#elif defined(MV_BOOTSIZE_8M) + +#define BOOTDEV_CS_SIZE _8M + +#elif defined(MV_BOOTSIZE_16M) + +#define BOOTDEV_CS_SIZE _16M + +#elif defined(MV_BOOTSIZE_32M) + +#define BOOTDEV_CS_SIZE _32M + +#elif defined(MV_BOOTSIZE_64M) + +#define BOOTDEV_CS_SIZE _64M + +#else + +#define Error MV_BOOTSIZE undefined + +#endif + +#if defined(MV632X) +#undef MV_INC_BOARD_NOR_FLASH +#endif + + + +#if !defined(MV_NAND_BOOT) +#ifdef MV78200 +#ifdef RD_MV78XX0_AMC +#define CFG_NAND_BASE DEVICE_CS2_BASE +#elif defined(MV632X) +#define CFG_NAND_BASE BOOTDEV_CS_BASE +#else /*MV632X*/ +#define CFG_NAND_BASE DEVICE_CS3_BASE +#endif +#else /*MV78200*/ +#define CFG_NAND_BASE DEVICE_CS2_BASE +#endif +#else /*MV_NAND_BOOT*/ +#define CFG_NAND_BASE BOOTDEV_CS_BASE +#endif /*MV_NAND_BOOT*/ + +#if (defined(DB_MV78XX0) || defined(MV78200) || defined(RD_MV78XX0_PCAC)) && !defined(MV_SPI_BOOT) +#define BOOT_FLASH_INDEX 0 +#define MAIN_FLASH_INDEX 1 +#else +#define BOOT_FLASH_INDEX 1 +#define MAIN_FLASH_INDEX 0 +#endif + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +/* These addresses defines the place where global parameters will be placed */ +/* in case running from ROM. We Use SYS_MEM_TOP. See bootInit.c file */ +#define DRAM_DETECT_FLAG_ADDR 0x03000000 +#define DRAM_CONFIG_ROM_ADDR 0x03000004 +#ifdef RD_MV78XX0_AMC +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable/disable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, EN },/* 7 */ \ + {{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \ + {{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, DIS },/* 9 */ \ + {{PCI0_MEM0_BASE , 0, PCI0_MEM0_SIZE }, 0, EN },/* 10 */ \ + {{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 1, DIS },/* 11 */ \ + {{PCI1_MEM0_BASE , 0, PCI1_MEM0_SIZE }, 1, EN },/* 12 */ \ + {{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 2, DIS},/* 13 */ \ + {{PCI2_MEM0_BASE , 0, PCI2_MEM0_SIZE }, 2, EN},/* 14 */ \ + {{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 3, DIS },/* 15 */ \ + {{PCI3_MEM0_BASE , 0, PCI3_MEM0_SIZE }, 3, EN },/* 16 */ \ + {{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 4, DIS },/* 17 */ \ + {{PCI4_MEM0_BASE , 0, PCI4_MEM0_SIZE }, 4, EN },/* 18 */ \ + {{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \ + {{PCI5_MEM0_BASE , 0, PCI5_MEM0_SIZE }, 5, EN},/* 20 */ \ + {{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \ + {{PCI6_MEM0_BASE , 0, PCI6_MEM0_SIZE }, 6, EN},/* 22 */ \ + {{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \ + {{PCI7_MEM0_BASE , 0, PCI7_MEM0_SIZE }, 7, EN},/* 24 */ \ + {{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \ +}; + +#define MV_CPU_IF_ADDR_WIN_MON_EXT_MAP_TBL { \ +/* base low base high size WinNum enable/disable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, EN },/* 7 */ \ + {{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \ + {{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, DIS },/* 9 */ \ + {{PCI0_MEM0_ME_BASE, 0, PCI0_MEM0_ME_SIZE }, 0, EN },/* 10 */ \ + {{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 1, DIS },/* 11 */ \ + {{PCI1_MEM0_ME_BASE, 0, PCI1_MEM0_ME_SIZE }, 1, EN },/* 12 */ \ + {{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 2, DIS},/* 13 */ \ + {{PCI2_MEM0_ME_BASE, 0, PCI2_MEM0_ME_SIZE }, 2, EN},/* 14 */ \ + {{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 3, DIS },/* 15 */ \ + {{PCI3_MEM0_ME_BASE, 0, PCI3_MEM0_ME_SIZE }, 3, EN },/* 16 */ \ + {{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 4, DIS },/* 17 */ \ + {{PCI4_MEM0_ME_BASE, 0, PCI4_MEM0_ME_SIZE }, 4, EN },/* 18 */ \ + {{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \ + {{PCI5_MEM0_ME_BASE, 0, PCI5_MEM0_ME_SIZE }, 5, EN},/* 20 */ \ + {{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \ + {{PCI6_MEM0_ME_BASE, 0, PCI6_MEM0_ME_SIZE }, 6, EN},/* 22 */ \ + {{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \ + {{PCI7_MEM0_ME_BASE, 0, PCI7_MEM0_ME_SIZE }, 7, EN},/* 24 */ \ + {{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \ +}; +#elif defined(DB_MV88F632X) + +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable/disable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, DIS },/* 4 */ \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, DIS },/* 5 */ \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, DIS },/* 7 */ \ + {{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \ + {{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \ + {{PCI0_MEM0_BASE , 0, PCI0_MEM0_SIZE }, 1, EN },/* 10 */ \ + {{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, DIS },/* 11 */ \ + {{PCI1_MEM0_BASE , 0, PCI1_MEM0_SIZE }, 3, DIS },/* 12 */ \ + {{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \ + {{PCI2_MEM0_BASE , 0, PCI2_MEM0_SIZE }, 5, DIS},/* 14 */ \ + {{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, DIS },/* 15 */ \ + {{PCI3_MEM0_BASE , 0, PCI3_MEM0_SIZE }, 5, DIS },/* 16 */ \ + {{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \ + {{PCI4_MEM0_BASE , 0, PCI4_MEM0_SIZE }, 7, EN },/* 18 */ \ + {{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \ + {{PCI5_MEM0_BASE , 0, PCI5_MEM0_SIZE }, 5, DIS},/* 20 */ \ + {{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \ + {{PCI6_MEM0_BASE , 0, PCI6_MEM0_SIZE }, 6, DIS},/* 22 */ \ + {{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \ + {{PCI7_MEM0_BASE , 0, PCI7_MEM0_SIZE }, 7, DIS},/* 24 */ \ + {{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \ +}; + +#define MV_CPU_IF_ADDR_WIN_MON_EXT_MAP_TBL { \ +/* base low base high size WinNum enable/disable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, DIS },/* 4 */ \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, DIS },/* 5 */ \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, DIS },/* 7 */ \ + {{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \ + {{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \ + {{PCI0_MEM0_ME_BASE, 0, PCI0_MEM0_ME_SIZE }, 1, EN },/* 10 */ \ + {{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, DIS },/* 11 */ \ + {{PCI1_MEM0_ME_BASE, 0, PCI1_MEM0_ME_SIZE }, 3, DIS },/* 12 */ \ + {{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \ + {{PCI2_MEM0_BASE , 0, PCI2_MEM0_ME_SIZE }, 5, DIS},/* 14 */ \ + {{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, DIS },/* 15 */ \ + {{PCI3_MEM0_ME_BASE, 0, PCI3_MEM0_ME_SIZE }, 5, DIS },/* 16 */ \ + {{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \ + {{PCI4_MEM0_ME_BASE, 0, PCI4_MEM0_ME_SIZE }, 7, EN },/* 18 */ \ + {{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \ + {{PCI5_MEM0_ME_BASE , 0, PCI5_MEM0_ME_SIZE }, 5, DIS},/* 20 */ \ + {{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \ + {{PCI6_MEM0_ME_BASE , 0, PCI6_MEM0_ME_SIZE }, 6, DIS},/* 22 */ \ + {{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \ + {{PCI7_MEM0_ME_BASE , 0, PCI7_MEM0_ME_SIZE }, 7, DIS},/* 24 */ \ + {{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \ +}; +#elif MV78200 +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable/disable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, EN },/* 7 */ \ + {{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \ + {{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \ + {{PCI0_MEM0_BASE , 0, PCI0_MEM0_SIZE }, 1, EN },/* 10 */ \ + {{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, EN },/* 11 */ \ + {{PCI1_MEM0_BASE , 0, PCI1_MEM0_SIZE }, 3, EN },/* 12 */ \ + {{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \ + {{PCI2_MEM0_BASE , 0, PCI2_MEM0_SIZE }, 5, DIS},/* 14 */ \ + {{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, EN },/* 15 */ \ + {{PCI3_MEM0_BASE , 0, PCI3_MEM0_SIZE }, 5, EN },/* 16 */ \ + {{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \ + {{PCI4_MEM0_BASE , 0, PCI4_MEM0_SIZE }, 7, EN },/* 18 */ \ + {{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \ + {{PCI5_MEM0_BASE , 0, PCI5_MEM0_SIZE }, 5, DIS},/* 20 */ \ + {{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \ + {{PCI6_MEM0_BASE , 0, PCI6_MEM0_SIZE }, 6, DIS},/* 22 */ \ + {{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \ + {{PCI7_MEM0_BASE , 0, PCI7_MEM0_SIZE }, 7, DIS},/* 24 */ \ + {{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \ +}; + +#define MV_CPU_IF_ADDR_WIN_MON_EXT_MAP_TBL { \ +/* base low base high size WinNum enable/disable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, DIS },/* 6 */ \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, EN },/* 7 */ \ + {{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \ + {{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 12, EN },/* 7 */ \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \ + {{PCI0_MEM0_ME_BASE, 0, PCI0_MEM0_ME_SIZE }, 1, EN },/* 10 */ \ + {{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, EN },/* 11 */ \ + {{PCI1_MEM0_ME_BASE, 0, PCI1_MEM0_ME_SIZE }, 3, EN },/* 12 */ \ + {{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \ + {{PCI2_MEM0_BASE , 0, PCI2_MEM0_ME_SIZE }, 5, DIS},/* 14 */ \ + {{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, EN },/* 15 */ \ + {{PCI3_MEM0_ME_BASE, 0, PCI3_MEM0_ME_SIZE }, 5, EN },/* 16 */ \ + {{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \ + {{PCI4_MEM0_ME_BASE, 0, PCI4_MEM0_ME_SIZE }, 7, EN },/* 18 */ \ + {{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \ + {{PCI5_MEM0_ME_BASE , 0, PCI5_MEM0_ME_SIZE }, 5, DIS},/* 20 */ \ + {{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \ + {{PCI6_MEM0_ME_BASE , 0, PCI6_MEM0_ME_SIZE }, 6, DIS},/* 22 */ \ + {{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \ + {{PCI7_MEM0_ME_BASE , 0, PCI7_MEM0_ME_SIZE }, 7, DIS},/* 24 */ \ + {{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \ +}; +#else +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable/disable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, EN },/* 6 */ \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, DIS },/* 7 */ \ + {{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \ + {{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 9, EN },/* 7 */ \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \ + {{PCI0_MEM0_BASE , 0, PCI0_MEM0_SIZE }, 1, EN },/* 10 */ \ + {{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, EN },/* 11 */ \ + {{PCI1_MEM0_BASE , 0, PCI1_MEM0_SIZE }, 3, EN },/* 12 */ \ + {{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \ + {{PCI2_MEM0_BASE , 0, PCI2_MEM0_SIZE }, 5, DIS},/* 14 */ \ + {{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, EN },/* 15 */ \ + {{PCI3_MEM0_BASE , 0, PCI3_MEM0_SIZE }, 5, EN },/* 16 */ \ + {{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \ + {{PCI4_MEM0_BASE , 0, PCI4_MEM0_SIZE }, 7, EN },/* 18 */ \ + {{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \ + {{PCI5_MEM0_BASE , 0, PCI5_MEM0_SIZE }, 5, DIS},/* 20 */ \ + {{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \ + {{PCI6_MEM0_BASE , 0, PCI6_MEM0_SIZE }, 6, DIS},/* 22 */ \ + {{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \ + {{PCI7_MEM0_BASE , 0, PCI7_MEM0_SIZE }, 7, DIS},/* 24 */ \ + {{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \ +}; + +#define MV_CPU_IF_ADDR_WIN_MON_EXT_MAP_TBL { \ +/* base low base high size WinNum enable/disable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, 0xFFFFFFFF, EN },/* 0 */ \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, 0xFFFFFFFF, EN },/* 1 */ \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, 0xFFFFFFFF, EN },/* 2 */ \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, 0xFFFFFFFF, EN },/* 3 */ \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE}, 10, EN },/* 4 */ \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE}, 11, EN },/* 5 */ \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE}, 12, EN },/* 6 */ \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE}, 9, DIS },/* 7 */ \ + {{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE}, 13, EN },/* 8 */ \ + {{DEVICE_SPI_BASE, 0, DEVICE_SPI_SIZE}, 9, EN },/* 7 */ \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE }, 0, EN },/* 9 */ \ + {{PCI0_MEM0_ME_BASE, 0, PCI0_MEM0_ME_SIZE }, 1, EN },/* 10 */ \ + {{PCI1_IO_BASE , 0, PCI1_IO_SIZE }, 2, EN },/* 11 */ \ + {{PCI1_MEM0_ME_BASE, 0, PCI1_MEM0_ME_SIZE }, 3, EN },/* 12 */ \ + {{PCI2_IO_BASE , 0, PCI2_IO_SIZE }, 4, DIS},/* 13 */ \ + {{PCI2_MEM0_ME_BASE , 0, PCI2_MEM0_ME_SIZE }, 5, DIS},/* 14 */ \ + {{PCI3_IO_BASE , 0, PCI3_IO_SIZE }, 4, EN },/* 15 */ \ + {{PCI3_MEM0_ME_BASE, 0, PCI3_MEM0_ME_SIZE }, 5, EN },/* 16 */ \ + {{PCI4_IO_BASE , 0, PCI4_IO_SIZE }, 6, EN },/* 17 */ \ + {{PCI4_MEM0_ME_BASE, 0, PCI4_MEM0_ME_SIZE }, 7, EN },/* 18 */ \ + {{PCI5_IO_BASE , 0, PCI5_IO_SIZE }, 5, DIS},/* 19 */ \ + {{PCI5_MEM0_ME_BASE , 0, PCI5_MEM0_ME_SIZE }, 5, DIS},/* 20 */ \ + {{PCI6_IO_BASE , 0, PCI6_IO_SIZE }, 6, DIS},/* 21 */ \ + {{PCI6_MEM0_ME_BASE , 0, PCI6_MEM0_ME_SIZE }, 6, DIS},/* 22 */ \ + {{PCI7_IO_BASE , 0, PCI7_IO_SIZE }, 7, DIS},/* 23 */ \ + {{PCI7_MEM0_ME_BASE , 0, PCI7_MEM0_ME_SIZE }, 7, DIS},/* 24 */ \ + {{CRYPTO_BASE , 0, CRYPTO_SIZE }, 8, EN },/* 25 */ \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE}, 14, EN },/* 26 */ \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM, TBL_TERM} \ +}; +#endif + +/* We use the following registers to store DRAM interface pre configuration */ +/* auto-detection results */ +#define DRAM_BUF_REG0 0x60810 /* sdram bank 0 size */ +#define DRAM_BUF_REG1 0x60814 /* sdram config */ +#define DRAM_BUF_REG2 0x60818 /* sdram mode */ +#define DRAM_BUF_REG3 0x6081c /* dunit control low */ +#define DRAM_BUF_REG4 0x60820 /* sdram address control */ +#define DRAM_BUF_REG5 0x60824 /* sdram timing control low */ +#define DRAM_BUF_REG6 0x60828 /* sdram timing control high */ +#define DRAM_BUF_REG7 0x6082c /* sdram ODT control low */ +#define DRAM_BUF_REG8 0x60830 /* sdram ODT control high */ +#define DRAM_BUF_REG9 0x60834 /* sdram Dunit ODT control */ +#define DRAM_BUF_REG10 0x60838 /* sdram Extended Mode */ +#define DRAM_BUF_REG11 0x6083c /* sdram Ddr2 Timing Low */ +#define DRAM_BUF_REG12 0x60870 /* sdram Ddr2 Timing High */ +#define DRAM_BUF_REG13 0x60874 /* dunit control high */ +#define DRAM_BUF_REG14 0x60878 /* if == '1' second dimm exist */ + +/* HW cache coherency configuration */ +#define DRAM_COHERENCY NO_COHERENCY + +/* PCI stuff */ +/* Local bus and device number of PCI0/1*/ +#define PCI_HOST_BUS_NUM(pciIf) 0 +#define PCI_HOST_DEV_NUM(pciIf) 0 +#define PEX_HOST_BUS_NUM(pexIf) (1 * pexIf) +#define PEX_HOST_DEV_NUM(pexIf) 0 + + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + +/* Board clock detection */ +#undef TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#undef SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ + +/* Memory uncached, HW or SW cache coherency is not needed */ +#define MV_UNCACHED 0 +/* Memory cached, HW cache coherency supported in WriteThrough mode */ +#define MV_CACHE_COHER_HW_WT 1 +/* Memory cached, HW cache coherency supported in WriteBack mode */ +#define MV_CACHE_COHER_HW_WB 2 +/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ +#define MV_CACHE_COHER_SW 3 + + +#if INTEG_SRAM_COHER == MV_CACHE_COHER_HW_WB +# define INTEG_SRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif INTEG_SRAM_COHER == MV_CACHE_COHER_HW_WT +# define INTEG_SRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif INTEG_SRAM_COHER == MV_CACHE_COHER_SW +# define INTEG_SRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif INTEG_SRAM_COHER == MV_UNCACHED +# define INTEG_SRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected INTEG_SRAM_COHER value" +#endif /* INTEG_SRAM_COHER */ + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +#define ETH_DEF_TXQ 0 +#define ETH_DEF_RXQ 0 +#define MV_ETH_TX_Q_NUM 1 +#define MV_ETH_RX_Q_NUM 1 +#define ETH_NUM_OF_RX_DESCR 64 +#define ETH_NUM_OF_TX_DESCR ETH_NUM_OF_RX_DESCR*2 + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if defined(ETH_DESCR_IN_SRAM) +# define ETH_DESCR_CONFIG_STR "ETH_DESCR_IN_SRAM" +#elif defined(ETH_DESCR_IN_SDRAM) +# define ETH_DESCR_CONFIG_STR "ETH_DESCR_IN_SDRAM" +#else +# error "ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM must be defined" +#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" + +#endif /* ETHER_DRAM_COHER */ + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + +#define MV_BRIDGE_REORDER_WA(param) \ +{ \ + volatile MV_U8 dummy = (MV_U8)param;\ +} + + +#endif /* __INCmvSysHwConfigh */ diff --git a/board/mv_feroceon/mv_dd/mv_cmd.c b/board/mv_feroceon/mv_dd/mv_cmd.c new file mode 100644 index 0000000..739e202 --- /dev/null +++ b/board/mv_feroceon/mv_dd/mv_cmd.c @@ -0,0 +1,1220 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include +#include + +#include "mvTypes.h" +#include "mvCtrlEnvLib.h" + +#if defined(MV_INC_BOARD_DDIM) +#include "ddr2/spd/mvSpd.h" +#endif + +#if defined(MV_INC_BOARD_NOR_FLASH) +#include "norflash/mvFlash.h" +#endif + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) +#include "eth-phy/mvEthPhy.h" +#endif + +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif + +#if defined(MV_INCLUDE_IDMA) +#include "idma/mvIdma.h" +#include "sys/mvSysIdma.h" +#endif + +extern unsigned int whoAmI(void); + +#if defined(CFG_NAND_BOOT) || defined(CFG_CMD_NAND) +#include + +/* references to names in cmd_nand.c */ +#define NANDRW_READ 0x01 +#define NANDRW_WRITE 0x00 +#define NANDRW_JFFS2 0x02 +//extern struct nand_chip nand_dev_desc[]; +extern nand_info_t nand_info[]; /* info for NAND chips */ +/* int nand_rw (struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf); + int nand_erase(struct nand_chip* nand, size_t ofs, + size_t len, int clean); +*/ +extern int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); +extern int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts); + + +#endif /* CFG_NAND_BOOT */ + +#if !defined(CFG_NAND_BOOT) +static unsigned int flash_in_which_sec(flash_info_t *fl,unsigned int offset) +{ + unsigned int sec_num; + if(NULL == fl) + return 0xFFFFFFFF; + + for( sec_num = 0; sec_num < fl->sector_count ; sec_num++){ + /* If last sector*/ + if (sec_num == fl->sector_count -1) + { + if((offset >= fl->start[sec_num]) && + (offset <= (fl->size + fl->start[0] - 1)) ) + { + return sec_num; + } + + } + else + { + if((offset >= fl->start[sec_num]) && + (offset < fl->start[sec_num + 1]) ) + { + return sec_num; + } + + } + } + /* return illegal sector Number */ + return 0xFFFFFFFF; + +} + +#endif /* !defined(CFG_NAND_BOOT) */ + + +/******************************************************************************* +burn a u-boot.bin on the Boot Flash +********************************************************************************/ +#include + +int nandenvECC = 0; +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if defined(CFG_NAND_BOOT) +/* Boot from NAND flash */ +/* Write u-boot image into the nand flash */ +int nand_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize, eccEnv = 0; + MV_U32 ret = 0; + extern char console_buffer[]; + nand_info_t *nand = &nand_info[0]; + nand_erase_options_t er_opts; + nand_write_options_t wr_opts; + + load_addr = CFG_LOAD_ADDR; + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "u-boot.bin", sizeof(BootFile)); + printf("using default file \"u-boot.bin\" \n"); + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + + /* The environment has Reed-Solomon ECC protection in the NAND */ + nandenvECC = 1; + printf("\n**Warning**\n"); + printf("Env parameters will be overriden!\n"); + printf("Erase %d - %d ... ",CFG_MONITOR_BASE, CFG_MONITOR_LEN); + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_MONITOR_BASE; + er_opts.length = CFG_MONITOR_LEN; + er_opts.quiet = 1; + nand_erase_opts(nand, &er_opts); + //nand_erase(nand_dev_desc + 0, CFG_MONITOR_BASE, CFG_MONITOR_LEN, 0); + + printf("\nCopy to Nand Flash... "); + memset(&wr_opts, 0, sizeof(wr_opts)); + wr_opts.buffer = (u_char*) load_addr; + wr_opts.length = CFG_MONITOR_LEN; + wr_opts.offset = CFG_MONITOR_BASE; + /* opts.forcejffs2 = 1; */ + wr_opts.pad = 1; + wr_opts.blockalign = 1; + wr_opts.quiet = 1; + ret = nand_write_opts(nand, &wr_opts); + /* ret = nand_rw(nand_dev_desc + 0, + NANDRW_WRITE | NANDRW_JFFS2, CFG_MONITOR_BASE, CFG_MONITOR_LEN, + &total, (u_char*)0x100000 + CFG_MONITOR_IMAGE_OFFSET); + */ + if (ret) + printf("Error - NAND burn faild!\n"); + else + printf("\ndone\n"); + + /* The environment has Reed-Solomon ECC protection in the NAND */ + nandenvECC = 0; + + return 1; +} + +U_BOOT_CMD( + bubt, 2, 1, nand_burn_uboot_cmd, + "bubt - Burn an image on the Boot Nand Flash.\n", + " file-name \n" + "\tBurn a binary image on the Boot Nand Flash, default file-name is u-boot.bin .\n" +); + +/* Write nboot loader image into the nand flash */ +int nand_burn_nboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 ret = 0; + extern char console_buffer[]; + nand_info_t *nand = &nand_info[0]; + nand_erase_options_t er_opts; + nand_write_options_t wr_opts; + + + load_addr = CFG_LOAD_ADDR; + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "nboot.bin", sizeof(BootFile)); + printf("using default file \"nboot.bin\" \n"); + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + + printf("Erase %d - %d ... ",CFG_NBOOT_BASE, CFG_NBOOT_LEN); + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_NBOOT_BASE; + er_opts.length = CFG_NBOOT_LEN; + er_opts.quiet = 1; + + nand_erase_opts(nand, &er_opts); + //nand_erase(nand_dev_desc + 0, CFG_NBOOT_BASE, CFG_NBOOT_LEN , 0); + + printf("\nCopy to Nand Flash... "); + memset(&wr_opts, 0, sizeof(wr_opts)); + wr_opts.buffer = (u_char*) load_addr; + wr_opts.length = CFG_NBOOT_LEN; + wr_opts.offset = CFG_NBOOT_BASE; + /* opts.forcejffs2 = 1; */ + wr_opts.pad = 1; + wr_opts.blockalign = 1; + wr_opts.quiet = 1; + ret = nand_write_opts(nand, &wr_opts); + /* ret = nand_rw(nand_dev_desc + 0, + NANDRW_WRITE | NANDRW_JFFS2, CFG_NBOOT_BASE, CFG_NBOOT_LEN, + &total, (u_char*)0x100000); + */ + if (ret) + printf("Error - NAND burn faild!\n"); + else + printf("\ndone\n"); + + return 1; +} + +U_BOOT_CMD( + nbubt, 2, 1, nand_burn_nboot_cmd, + "nbubt - Burn a boot loader image on the Boot Nand Flash.\n", + " file-name \n" + "\tBurn a binary boot loader image on the Boot Nand Flash, default file-name is nboot.bin .\n" +); + +#else +extern flash_info_t flash_info[]; /* info for FLASH chips */ +/* Boot from Nor flash */ +int nor_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 s_first,s_end,env_sec; + extern char console_buffer[]; + + + s_first = flash_in_which_sec(&flash_info[BOOT_FLASH_INDEX], CFG_MONITOR_BASE); + s_end = flash_in_which_sec(&flash_info[BOOT_FLASH_INDEX], CFG_MONITOR_BASE + CFG_MONITOR_LEN -1); + + env_sec = flash_in_which_sec(&flash_info[BOOT_FLASH_INDEX], CFG_ENV_ADDR); + + load_addr = CFG_LOAD_ADDR; + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "u-boot.bin", sizeof(BootFile)); + printf("using default file \"u-boot.bin\" \n"); + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + + printf("Un-Protect Flash Monitor space\n"); + flash_protect (FLAG_PROTECT_CLEAR, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[BOOT_FLASH_INDEX]); + + printf("\n**Warning**\n"); + printf("If U-Boot Endiannes is going to change (LE->BE or BE->LE), Then Env parameters should be overriden..\n"); + printf("Override Env parameters? (y/n)"); + readline(" "); + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + flash_protect (FLAG_PROTECT_CLEAR, + flash_info[BOOT_FLASH_INDEX].start[env_sec], + flash_info[BOOT_FLASH_INDEX].start[env_sec] + CFG_ENV_SECT_SIZE - 1, + &flash_info[BOOT_FLASH_INDEX]); + + printf("Erase Env parameters sector %d... ",env_sec); + flash_erase(&flash_info[BOOT_FLASH_INDEX], env_sec, env_sec); + + if (MV_FALSE == mvBoardIsBootFromSpi()) + flash_protect (FLAG_PROTECT_SET, + flash_info[BOOT_FLASH_INDEX].start[env_sec], + flash_info[BOOT_FLASH_INDEX].start[env_sec] + CFG_ENV_SECT_SIZE - 1, + &flash_info[BOOT_FLASH_INDEX]); + + } + + printf("Erase %d - %d sectors... ",s_first,s_end); + flash_erase(&flash_info[BOOT_FLASH_INDEX], s_first, s_end); + + printf("Copy to Flash... "); + flash_write ( (uchar *)(CFG_LOAD_ADDR + CFG_MONITOR_IMAGE_OFFSET), +#ifdef MV_SPI_BOOT + (ulong)CFG_MONITOR_BASE - 0x30000, +#else + (ulong)CFG_MONITOR_BASE, +#endif + (ulong)(filesize - CFG_MONITOR_IMAGE_OFFSET)); + printf("done\nProtect Flash Monitor space\n"); + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[BOOT_FLASH_INDEX]); + + return 1; +} + +U_BOOT_CMD( + bubt, 2, 1, nor_burn_uboot_cmd, + "bubt - Burn an image on the Boot Flash.\n", + " file-name \n" + "\tBurn a binary image on the Boot Flash, default file-name is u-boot.bin .\n" +); +#endif /* defined(CFG_NAND_BOOT) */ +#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */ + + + +/******************************************************************************* +Reset environment variables. +********************************************************************************/ +#ifndef CFG_NAND_BOOT +extern flash_info_t flash_info[]; /* info for FLASH chips */ +#endif +int resetenv_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CFG_NAND_BOOT) + if (whoAmI()) + { + puts ("Only Master CPU can resetenv!\n"); + return 0; + } + printf("Erase Env parameters offset 0x%x... ",CFG_ENV_OFFSET); + nand_info_t *nand = &nand_info[0]; + nand_erase_options_t er_opts; + int i = 0, goodBlockCounter = 0; + + while(i * nand_info[0].erasesize < nand_info[0].size) + { + if(nand_info[0].block_isbad(&nand_info[0], i * nand_info[0].erasesize) == 0) + goodBlockCounter++; + if((goodBlockCounter * nand_info[0].erasesize) >= CFG_ENV_OFFSET + CFG_ENV_SECT_SIZE) + break; + i++; + } + + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_ENV_OFFSET + (1 + i - goodBlockCounter) * nand_info[0].erasesize; + er_opts.length = CFG_ENV_SECT_SIZE; + er_opts.quiet = 1; + + nand_erase_opts(nand, &er_opts); + //nand_erase(nand_dev_desc + 0, CFG_ENV_OFFSET, CFG_ENV_SECT_SIZE, 0); + printf("done"); +#else + MV_U32 env_sec = flash_in_which_sec(&flash_info[BOOT_FLASH_INDEX], CFG_ENV_ADDR); + + if (env_sec == -1) + { + printf("Could not find ENV Sector\n"); + return 0; + } + + if (whoAmI()) + { + puts ("Only Master CPU can resetenv!\n"); + return 0; + } + + printf("Un-Protect ENV Sector\n"); + + flash_protect(FLAG_PROTECT_CLEAR, + CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[BOOT_FLASH_INDEX]); + + + printf("Erase sector %d ... ",env_sec); + flash_erase(&flash_info[BOOT_FLASH_INDEX], env_sec, env_sec); + printf("done\nProtect ENV Sector\n"); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[BOOT_FLASH_INDEX]); + +#endif /* defined(CFG_NAND_BOOT) */ + printf("\nWarning: Default Environment Variables will take effect Only after RESET \n\n"); + return 1; +} + +U_BOOT_CMD( + resetenv, 1, 1, resetenv_cmd, + "resetenv - Return all environment variable to default.\n", + " \n" + "\t Erase the environemnt variable sector.\n" +); + +#if CONFIG_COMMANDS & CFG_CMD_BSP + +/****************************************************************************** +* Category - General +* Functionality- The commands allows the user to view the contents of the MV +* internal registers and modify them. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int ir_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_U32 regNum = 0x0, regVal, regValTmp, res; + MV_8 regValBin[40]; + MV_8 cmd[40]; + int i,j = 0, flagm = 0; + extern MV_8 console_buffer[]; + + if( argc == 2 ) { + regNum = simple_strtoul( argv[1], NULL, 16 ); + } + else { + printf( "Usage:\n%s\n", cmdtp->usage ); + return 0; + } + + regVal = MV_REG_READ( regNum ); + regValTmp = regVal; + printf( "Internal register 0x%x value : 0x%x\n ",regNum, regVal ); + printf( "\n 31 24 16 8 0" ); + printf( "\n | | | | |\nOLD: " ); + + for( i = 31 ; i >= 0 ; i-- ) { + if( regValTmp > 0 ) { + res = regValTmp % 2; + regValTmp = (regValTmp - res) / 2; + if( res == 0 ) + regValBin[i] = '0'; + else + regValBin[i] = '1'; + } + else + regValBin[i] = '0'; + } + + for( i = 0 ; i < 32 ; i++ ) { + printf( "%c", regValBin[i] ); + if( (((i+1) % 4) == 0) && (i > 1) && (i < 31) ) + printf( "-" ); + } + + readline( "\nNEW: " ); + strcpy(cmd, console_buffer); + if( (cmd[0] == '0') && (cmd[1] == 'x') ) { + regVal = simple_strtoul( cmd, NULL, 16 ); + flagm=1; + } + else { + for( i = 0 ; i < 40 ; i++ ) { + if(cmd[i] == '\0') + break; + if( i == 4 || i == 9 || i == 14 || i == 19 || i == 24 || i == 29 || i == 34 ) + continue; + if( cmd[i] == '1' ) { + regVal = regVal | (0x80000000 >> j); + flagm = 1; + } + else if( cmd[i] == '0' ) { + regVal = regVal & (~(0x80000000 >> j)); + flagm = 1; + } + j++; + } + } + + if( flagm == 1 ) { + MV_REG_WRITE( regNum, regVal ); + printf( "\nNew value = 0x%x\n\n", MV_REG_READ(regNum) ); + } + return 1; +} + +U_BOOT_CMD( + ir, 2, 1, ir_cmd, + "ir - reading and changing MV internal register values.\n", + " address\n" + "\tDisplays the contents of the internal register in 2 forms, hex and binary.\n" + "\tIt's possible to change the value by writing a hex value beginning with \n" + "\t0x or by writing 0 or 1 in the required place. \n" + "\tPressing enter without any value keeps the value unchanged.\n" +); + +/****************************************************************************** +* Category - General +* Functionality- Display the auto detect values of the TCLK and SYSCLK. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int clk_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf( "TCLK %dMhz, SYSCLK %dMhz (UART baudrate %d)\n", + mvTclkGet()/1000000, mvSysClkGet()/1000000, CONFIG_BAUDRATE); + return 1; +} + +U_BOOT_CMD( + dclk, 1, 1, clk_cmd, + "dclk - Display the MV device CLKs.\n", + " \n" + "\tDisplay the auto detect values of the TCLK and SYSCLK.\n" +); + +/****************************************************************************** +* Functional only when using Lauterbach to load image into DRAM +* Category - DEBUG +* Functionality- Display the array of registers the u-boot write to. +* +*****************************************************************************/ +#if defined(REG_DEBUG) +int reg_arry[REG_ARRAY_SIZE][2]; +int reg_arry_index = 0; +int print_registers( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + printf("Register display\n"); + + for (i=0; i < reg_arry_index; i++) + printf("Index %d 0x%x=0x%08x\n", i, (reg_arry[i][0] & 0x000fffff), reg_arry[i][1]); + + /* Print DRAM registers */ + printf("Index %d 0x%x=0x%08x\n", i++, 0x1500, MV_REG_READ(0x1500)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1504, MV_REG_READ(0x1504)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1508, MV_REG_READ(0x1508)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x150c, MV_REG_READ(0x150c)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1510, MV_REG_READ(0x1510)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1514, MV_REG_READ(0x1514)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1518, MV_REG_READ(0x1518)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x151c, MV_REG_READ(0x151c)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1400, MV_REG_READ(0x1400)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1404, MV_REG_READ(0x1404)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1408, MV_REG_READ(0x1408)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x140c, MV_REG_READ(0x140c)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1410, MV_REG_READ(0x1410)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x141c, MV_REG_READ(0x141c)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1420, MV_REG_READ(0x1420)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1424, MV_REG_READ(0x1424)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1428, MV_REG_READ(0x1428)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x147c, MV_REG_READ(0x147c)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1494, MV_REG_READ(0x1494)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1498, MV_REG_READ(0x1498)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x149c, MV_REG_READ(0x149c)); + + printf("Number of Reg %d \n", i); + + return 1; +} + +U_BOOT_CMD( + printreg, 1, 1, print_registers, + "printreg - Display the register array the u-boot write to.\n", + " \n" + "\tDisplay the register array the u-boot write to.\n" +); +#endif + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) +/****************************************************************************** +* Category - Etherent +* Functionality- Display PHY ports status (using SMI access). +* Need modifications (Yes/No) - No +*****************************************************************************/ +#ifndef MV_TINY_IMAGE +int sg_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(MV_INC_BOARD_QD_SWITCH) + printf( "Switch status not supported\n"); +#else + MV_U32 port; + for( port = 0 ; port < mvCtrlEthMaxPortGet(); port++ ) { + + printf( "PHY %d :\n", port ); + printf( "---------\n" ); + + mvEthPhyPrintStatus( mvBoardPhyAddrGet(port) ); + + printf("\n"); + } +#endif + return 1; +} + +U_BOOT_CMD( + sg, 1, 1, sg_cmd, + "sg - scanning the PHYs status\n", + " \n" + "\tScan all the Gig port PHYs and display their Duplex, Link, Speed and AN status.\n" +); +#endif +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + +#if defined(MV_INCLUDE_IDMA) + +/****************************************************************************** +* Category - DMA +* Functionality- Perform a DMA transaction +* Need modifications (Yes/No) - No +*****************************************************************************/ +int mvDma_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_8 cmd[20], c; + extern MV_8 console_buffer[]; + MV_U32 chan, src, dst, byteCount, ctrlLo; + MV_DMA_DEC_WIN win; + MV_BOOL err; + + /* IDMA channel */ + if( argc == 2 ) + chan = simple_strtoul( argv[1], NULL, 16 ); + else + chan = 0; + + /* source address */ + while(1) { + readline( "Source Address: " ); + strcpy( cmd, console_buffer ); + src = simple_strtoul( cmd, NULL, 16 ); + if( src == 0xffffffff ) printf( "Bad address !!!\n" ); + else break; + } + + /* desctination address */ + while(1) { + readline( "Destination Address: " ); + strcpy(cmd, console_buffer); + dst = simple_strtoul( cmd, NULL, 16 ); + if( dst == 0xffffffff ) printf("Bad address !!!\n"); + else break; + } + + /* byte count */ + while(1) { + readline( "Byte Count (up to 16M (0xffffff-1)): " ); + strcpy( cmd, console_buffer ); + byteCount = simple_strtoul( cmd, NULL, 16 ); + if( (byteCount > 0xffffff) || (byteCount == 0) ) printf("Bad value !!!\n"); + else break; + } + + /* compose the command */ + ctrlLo = ICCLR_BLOCK_MODE | ICCLR_NON_CHAIN_MODE | ICCLR_SRC_INC | ICCLR_DST_INC; + + + if (byteCount > _64K) + { + ctrlLo |= ICCLR_DESC_MODE_16M; + } + + /* set data transfer limit */ + while(1) { + printf( "Data transfer limit:\n" ); + printf( "(1) 8 bytes at a time.\n" ); + printf( "(2) 16 bytes at a time.\n" ); + printf( "(3) 32 bytes at a time.\n" ); + printf( "(4) 64 bytes at a time.\n" ); + printf( "(5) 128 bytes at a time.\n" ); + + c = getc(); + printf( "%c\n", c ); + + err = MV_FALSE; + + switch( c ) { + case 13: /* Enter */ + ctrlLo |= (ICCLR_DST_BURST_LIM_32BYTE | ICCLR_SRC_BURST_LIM_32BYTE); + printf( "32 bytes at a time.\n" ); + break; + case '1': + ctrlLo |= (ICCLR_DST_BURST_LIM_8BYTE | ICCLR_SRC_BURST_LIM_8BYTE); + break; + case '2': + ctrlLo |= (ICCLR_DST_BURST_LIM_16BYTE | ICCLR_SRC_BURST_LIM_16BYTE); + break; + case '3': + ctrlLo |= (ICCLR_DST_BURST_LIM_32BYTE | ICCLR_SRC_BURST_LIM_32BYTE); + break; + case '4': + ctrlLo |= (ICCLR_DST_BURST_LIM_64BYTE | ICCLR_SRC_BURST_LIM_64BYTE); + break; + case '5': + ctrlLo |= (ICCLR_DST_BURST_LIM_128BYTE | ICCLR_SRC_BURST_LIM_128BYTE); + break; + default: + printf( "Bad value !!!\n" ); + err = MV_TRUE; + } + + if( !err ) break; + } + + /* set ovveride source option */ + while(1) { + printf( "Override Source:\n" ); + printf( "(0) - no override\n" ); + mvDmaWinGet( 1, &win ); + printf( "(1) - use Win1 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 2, &win ); + printf( "(2) - use Win2 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 3, &win ); + printf( "(3) - use Win3 (%s)\n",mvCtrlTargetNameGet(win.target)); + + c = getc(); + printf( "%c\n", c ); + + err = MV_FALSE; + + switch( c ) { + case 13: /* Enter */ + case '0': + printf( "No override\n" ); + break; + case '1': + ctrlLo |= ICCLR_OVRRD_SRC_BAR(1); + break; + case '2': + ctrlLo |= ICCLR_OVRRD_SRC_BAR(2); + break; + case '3': + ctrlLo |= ICCLR_OVRRD_SRC_BAR(3); + break; + default: + printf("Bad value !!!\n"); + err = MV_TRUE; + } + + if( !err ) break; + } + + /* set override destination option */ + while(1) { + printf( "Override Destination:\n" ); + printf( "(0) - no override\n" ); + mvDmaWinGet( 1, &win ); + printf( "(1) - use Win1 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 2, &win ); + printf( "(2) - use Win2 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 3, &win ); + printf( "(3) - use Win3 (%s)\n",mvCtrlTargetNameGet(win.target)); + + c = getc(); + printf( "%c\n", c ); + + err = MV_FALSE; + + switch( c ) { + case 13: /* Enter */ + case '0': + printf( "No override\n" ); + break; + case '1': + ctrlLo |= ICCLR_OVRRD_DST_BAR(1); + break; + case '2': + ctrlLo |= ICCLR_OVRRD_DST_BAR(2); + break; + case '3': + ctrlLo |= ICCLR_OVRRD_DST_BAR(3); + break; + default: + printf("Bad value !!!\n"); + err = MV_TRUE; + } + + if( !err ) break; + } + + /* wait for previous transfer completion */ + while( mvDmaStateGet(chan) != MV_IDLE ); + + /* issue the transfer */ + mvDmaCtrlLowSet( chan, ctrlLo ); + mvDmaTransfer( chan, src, dst, byteCount, 0 ); + + /* wait for completion */ + while( mvDmaStateGet(chan) != MV_IDLE ); + + printf( "Done...\n" ); + return 1; +} + +U_BOOT_CMD( + dma, 2, 1, mvDma_cmd, + "dma - Perform DMA\n", + " \n" + "\tPerform DMA transaction with the parameters given by the user.\n" +); + +#endif /* #if defined(MV_INCLUDE_IDMA) */ +#ifndef MV_TINY_IMAGE +/****************************************************************************** +* Category - Memory +* Functionality- Displays the MV's Memory map +* Need modifications (Yes/No) - Yes +*****************************************************************************/ +int displayMemoryMap_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvCtrlAddrDecShow(); + return 1; +} + +U_BOOT_CMD( + map, 1, 1, displayMemoryMap_cmd, + "map - Diasplay address decode windows\n", + " \n" + "\tDisplay controller address decode windows: CPU, PCI, Gig, DMA, XOR and COMM\n" +); + + + +#include "ddr2/spd/mvSpd.h" +#if defined(MV_INC_BOARD_DDIM) + +/****************************************************************************** +* Category - Memory +* Functionality- Displays the SPD information for a givven dimm +* Need modifications (Yes/No) - +*****************************************************************************/ + +int dimminfo_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int num = 0; + + if (argc > 1) { + num = simple_strtoul (argv[1], NULL, 10); + } + + printf("*********************** DIMM%d *****************************\n",num); + + dimmSpdPrint(num); + + printf("************************************************************\n"); + + return 1; +} + +U_BOOT_CMD( + ddimm, 2, 1, dimminfo_cmd, + "ddimm - Display SPD Dimm Info\n", + " [0/1]\n" + "\tDisplay Dimm 0/1 SPD information.\n" +); + +/****************************************************************************** +* Category - Memory +* Functionality- Copy the SPD information of dimm 0 to dimm 1 +* Need modifications (Yes/No) - +*****************************************************************************/ + +int spdcpy_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + printf("Copy DIMM 0 SPD data into DIMM 1 SPD..."); + + if (MV_OK != dimmSpdCpy()) + printf("\nDIMM SPD copy fail!\n"); + else + printf("Done\n"); + + return 1; +} + +U_BOOT_CMD( + spdcpy, 2, 1, spdcpy_cmd, + "spdcpy - Copy Dimm 0 SPD to Dimm 1 SPD \n", + "" + "" +); +#endif /* #if defined(MV_INC_BOARD_DDIM) */ + +/****************************************************************************** +* Functionality- Go to an address and execute the code there and return, +* defualt address is 0x40004 +*****************************************************************************/ +extern void cpu_dcache_flush_all(void); +extern void cpu_icache_flush_invalidate_all(void); + +void mv_go(unsigned long addr,int argc, char *argv[]) +{ + int rc; + addr = MV_CACHEABLE(addr); + char* envCacheMode = getenv("cacheMode"); + + /* + * pass address parameter as argv[0] (aka command name), + * and all remaining args + */ + + if(envCacheMode && (strcmp(envCacheMode,"write-through") == 0)) + { + int i=0; + + /* Flush Invalidate I-Cache */ + cpu_icache_flush_invalidate_all(); + + /* Drain write buffer */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); + + + } + else /*"write-back"*/ + { + int i=0; + + /* Flush Invalidate I-Cache */ + cpu_icache_flush_invalidate_all(); + + /* Drain write buffer */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); + + + /* Flush invalidate D-cache */ + cpu_dcache_flush_all(); + + + } + + + rc = ((ulong (*)(int, char *[]))addr) (--argc, &argv[1]); + + return; +} + +int g_cmd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0; + } + + addr = 0x40000; + + if (argc > 1) { + addr = simple_strtoul(argv[1], NULL, 16); + } + mv_go(addr,argc,&argv[0]); + return 1; +} + +U_BOOT_CMD( + g, CFG_MAXARGS, 1, g_cmd, + "g - start application at cached address 'addr'(default addr 0x40000)\n", + " addr [arg ...] \n" + "\tStart application at address 'addr'cachable!!!(default addr 0x40004/0x240004)\n" + "\tpassing 'arg' as arguments\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/****************************************************************************** +* Functionality- Searches for a value +*****************************************************************************/ +int fi_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 s_address,e_address,value,i,tempData; + MV_BOOL error = MV_FALSE; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 4){ + value = simple_strtoul(argv[1], NULL, 16); + s_address = simple_strtoul(argv[2], NULL, 16); + e_address = simple_strtoul(argv[3], NULL, 16); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + if(s_address == 0xffffffff || e_address == 0xffffffff) error = MV_TRUE; + if(s_address%4 != 0 || e_address%4 != 0) error = MV_TRUE; + if(s_address > e_address) error = MV_TRUE; + if(error) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + for(i = s_address; i < e_address ; i+=4) + { + tempData = (*((volatile unsigned int *)i)); + if(tempData == value) + { + printf("Value: %x found at ",value); + printf("address: %x\n",i); + return 1; + } + } + printf("Value not found!!\n"); + return 1; +} + +U_BOOT_CMD( + fi, 4, 1, fi_cmd, + "fi - Find value in the memory.\n", + " value start_address end_address\n" + "\tSearch for a value 'value' in the memory from address 'start_address to\n" + "\taddress 'end_address'.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/****************************************************************************** +* Functionality- Compare the memory with Value. +*****************************************************************************/ +int cmpm_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 s_address,e_address,value,i,tempData; + MV_BOOL error = MV_FALSE; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 4){ + value = simple_strtoul(argv[1], NULL, 16); + s_address = simple_strtoul(argv[2], NULL, 16); + e_address = simple_strtoul(argv[3], NULL, 16); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + if(s_address == 0xffffffff || e_address == 0xffffffff) error = MV_TRUE; + if(s_address%4 != 0 || e_address%4 != 0) error = MV_TRUE; + if(s_address > e_address) error = MV_TRUE; + if(error) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + for(i = s_address; i < e_address ; i+=4) + { + tempData = (*((volatile unsigned int *)i)); + if(tempData != value) + { + printf("Value: %x found at address: %x\n",tempData,i); + } + } + return 1; +} + +U_BOOT_CMD( + cmpm, 4, 1, cmpm_cmd, + "cmpm - Compare Memory\n", + " value start_address end_address.\n" + "\tCompare the memory from address 'start_address to address 'end_address'.\n" + "\twith value 'value'\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +#endif /* MV_TINY_IMAGE */ + + +#if 0 +/****************************************************************************** +* Category - Etherent +* Functionality- Display PHY ports status (using SMI access). +* Need modifications (Yes/No) - No +*****************************************************************************/ +int eth_show_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ethRegs(argv[1]); + ethPortRegs(argv[1]); + ethPortStatus(argv[1]); + ethPortQueues(argv[1],0,0,1); + return 1; +} + +U_BOOT_CMD( + ethShow, 2, 2, eth_show_cmd, + "ethShow - scanning the PHYs status\n", + " \n" + "\tScan all the Gig port PHYs and display their Duplex, Link, Speed and AN status.\n" +); +#endif + +#ifndef MV_TINY_IMAGE +#if defined(MV_INCLUDE_PEX) + +#include "pci/mvPci.h" + +int pcie_phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvPexPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + pciePhyRead, 3, 3, pcie_phy_read_cmd, + "phyRead - Read PCI-E Phy register\n", + " PCI-E_interface Phy_offset. \n" + "\tRead the PCI-E Phy register. \n" +); + + +int pcie_phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvPexPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + pciePhyWrite, 4, 4, pcie_phy_write_cmd, + "pciePhyWrite - Write PCI-E Phy register\n", + " PCI-E_interface Phy_offset value.\n" + "\tWrite to the PCI-E Phy register.\n" +); +#endif +#endif +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) + +#ifndef MV_TINY_IMAGE +#include "eth-phy/mvEthPhy.h" + +int phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvEthPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + phyRead, 3, 3, phy_read_cmd, + "phyRead - Read Phy register\n", + " Phy_address Phy_offset. \n" + "\tRead the Phy register. \n" +); + + +int phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvEthPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + phyWrite, 4, 4, phy_write_cmd, + "phyWrite - Write Phy register\n", + " Phy_address Phy_offset value.\n" + "\tWrite to the Phy register.\n" +); + +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + +#endif +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) +extern void recoveryHandle(void); +int do_rcvr (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + recoveryHandle(); + return 1; +} + +U_BOOT_CMD( + rcvr, 3, 1, do_rcvr, + "rcvr\t- Satrt recovery process (Distress Beacon with TFTP server)\n", + "\n" +); +#endif /* CFG_CMD_RCVR */ + +#ifdef MV78200 +#include "mv78200/mvSemaphore.h" + +int do_lock (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvSemaLock(simple_strtoul( argv[1], NULL, 16 )); + return 1; +} + +U_BOOT_CMD( + lockSem, 2, 0, do_lock, + "lockSem\t- Lock semaphore \n", + "Wait in busy loop until succeed\n" +); + +int do_unlock (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvSemaUnlock(simple_strtoul( argv[1], NULL, 16 )); + return 1; +} + +U_BOOT_CMD( + unlockSem, 2, 0, do_unlock, + "unlockSem\t- Unlock semaphore \n", + "\n" +); +#endif /* CFG_CMD_RCVR */ diff --git a/board/mv_feroceon/mv_dd/mv_dram.c b/board/mv_feroceon/mv_dd/mv_dram.c new file mode 100644 index 0000000..39f9882 --- /dev/null +++ b/board/mv_feroceon/mv_dd/mv_dram.c @@ -0,0 +1,341 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "ddr2/mvDramIf.h" +#include "mvOs.h" +#include "mvBoardEnvLib.h" +#include "ddr2/mvDramIfRegs.h" +#include "mvCpuIfRegs.h" +#include "cpu/mvCpu.h" + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +extern void i2c_init(int speed, int slaveaddr); +extern void _start(void); +extern unsigned int mvCpuPclkGet(void); +extern void reset_cpu(void); +extern int dramBoot; + + +#ifdef MV_INC_DRAM_MFG_TEST +static MV_VOID mvDramMfgTrst(void); +static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count); +static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count); +#endif + +MV_VOID mvIntrfaceWidthPrint(MV_VOID) +{ + MV_U32 deviceW, temp; + temp = MV_REG_READ(SDRAM_CONFIG_REG); + deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; + printf(" %dbit width",deviceW); +} + +MV_VOID mvIntrfaceParamPrint(MV_VOID) +{ + MV_U32 temp; + + printf("DRAM"); + switch((MV_REG_READ(SDRAM_MODE_REG) >> 4) & 0x7) + { + case 0x3: printf(" CAS Latency = 3"); + break; + case 0x4: printf(" CAS Latency = 4"); + break; + case 0x5: printf(" CAS Latency = 5"); + break; + case 0x6: printf(" CAS Latency = 6"); + break; + default: printf(" unknown CAL "); + break; + } + + temp = MV_REG_READ(SDRAM_TIMING_CTRL_LOW_REG); + printf(" tRP = %d tRAS = %d tRCD=%d\n", + ((temp >> 8) & 0xf) + 1, ((temp >> 16) & 0x10) + (temp & 0xf) + 1, ((temp >> 4) & 0xf) + 1); +} + +int dram_init (void) +{ + + DECLARE_GLOBAL_DATA_PTR; + unsigned int i, dramTotalSize=0; + char name[15]; + MV_32 memBase; + + mvCtrlModelRevNameGet(name); + printf("\nSoc: %s", name); + printf(" (DDR2)\n", name); + + printf("CPU running @ %dMhz L2 running @ %dMhz\n", mvCpuPclkGet()/1000000, mvCpuL2ClkGet()/1000000); +#ifdef MV_TCLK_CALC + printf("SysClock = %dMhz , Calc TClock = %dMhz \n\n", CFG_BUS_CLK/1000000, CFG_TCLK/1000000); +#else + printf("SysClock = %dMhz , TClock = %dMhz \n\n", CFG_BUS_CLK/1000000, CFG_TCLK/1000000); +#endif +#if defined(MV_INC_BOARD_DDIM) + /* Call dramInit */ + if (whoAmI() == MASTER_CPU) + { + if (0 == initdram(0)) + { + printf("DRAM Initialization Failed\n"); + reset_cpu(); + return (1); + } + } +#endif + + mvIntrfaceParamPrint(); + + for(i = 0; i< MV_DRAM_MAX_CS; i++) + { +#ifdef DUAL_OS_78200 + if (!enaMP() || ((whoAmI() == MASTER_CPU) && ((i == SDRAM_CS0) || (i == SDRAM_CS1))) ) + { +#endif + memBase = mvDramIfBankBaseGet(i); + if (MV_ERROR == memBase) + gd->bd->bi_dram[i].start = 0; + else + gd->bd->bi_dram[i].start = memBase; + + gd->bd->bi_dram[i].size = mvDramIfBankSizeGet(i); + dramTotalSize += gd->bd->bi_dram[i].size; + if (gd->bd->bi_dram[i].size) + { + printf("DRAM CS[%d] base 0x%08x ",i, gd->bd->bi_dram[i].start); + mvSizePrint(gd->bd->bi_dram[i].size); + printf("\n"); + } +#ifdef DUAL_OS_78200 + } + else if ((whoAmI() == SLAVE_CPU) && ((i == SDRAM_CS2) || (i == SDRAM_CS3))) + { + memBase = mvDramIfBankBaseGet(i); + if (MV_ERROR == memBase) + gd->bd->bi_dram[i].start = 0; + else + gd->bd->bi_dram[i].start = memBase; + + gd->bd->bi_dram[i].size = mvDramIfBankSizeGet(i); + dramTotalSize += gd->bd->bi_dram[i].size; + if (gd->bd->bi_dram[i].size) + { + printf("DRAM CS[%d] base 0x%08x ",i, gd->bd->bi_dram[i].start); + mvSizePrint(gd->bd->bi_dram[i].size); + printf("\n"); + } + } +#endif + } + + printf("DRAM Total "); + mvSizePrint(dramTotalSize); + mvIntrfaceWidthPrint(); + printf("\n"); +#ifdef MV_INC_DRAM_MFG_TEST + mvDramMfgTrst(); +#endif + return 0; +} + +#if defined(MV_INC_BOARD_DDIM) + +/* u-boot interface function to SDRAM init - this is where all the + * controlling logic happens */ +long int initdram(int board_type) +{ + MV_VOIDFUNCPTR pRom; + MV_U32 forcedCl; /* Forced CAS Latency */ + MV_U32 disEcc; /* disable ECC */ + MV_U32 totalSize; + char * env; + MV_TWSI_ADDR slave; + + /* r0 <- current position of code */ + /* test if we run from flash or RAM */ + if(dramBoot != 1) + { + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(MV_BOARD_DIMM_I2C_CHANNEL, CFG_I2C_SPEED, CFG_TCLK, &slave, 0); + + /* Calculating MIN/MAX CAS latency according to user settings */ + env = getenv("CASset"); + + if(env && (strcmp(env,"1.5") == 0)) + { + forcedCl = 15; + } + else if(env && (strcmp(env,"2") == 0)) + { + forcedCl = 20; + } + else if(env && (strcmp(env,"2.5") == 0)) + { + forcedCl = 25; + } + else if(env && (strcmp(env,"3") == 0)) + { + forcedCl = 30; + } + else if(env && (strcmp(env,"4") == 0)) + { + forcedCl = 40; + } + else if(env && (strcmp(env,"5") == 0)) + { + forcedCl = 50; + } + else if(env && (strcmp(env,"6") == 0)) + { + forcedCl = 60; + } + else + { + forcedCl = 0; + } + + disEcc = 1; +#ifdef CONFIG_MV_ECC + /* update the enaECC env parameter */ + env = getenv("enaECC"); + if(env && ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + disEcc = 0; +#endif + /* detect the dram configuartion parameters */ + if (MV_OK != mvDramIfDetect(forcedCl,disEcc)) + { + printf("DRAM Auto Detection Failed! System Halt!\n"); + return 0; + } + + /* set the dram configuration */ + /* Calculate jump address of _mvDramIfConfig() */ + +#if defined(MV_BOOTROM) + pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) + + (MV_VOIDFUNCPTR)CFG_MONITOR_BASE + (MV_VOIDFUNCPTR)MONITOR_HEADER_LEN); +#else + pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) + + (MV_VOIDFUNCPTR)CFG_MONITOR_BASE); +#endif + + (*pRom) (); /* Jump to _mvDramIfConfig*/ + } + + totalSize = mvDramIfSizeGet(); + + return(totalSize); +} + +#endif /* #if defined(MV_INC_BOARD_DDIM) */ + +#ifdef MV_INC_DRAM_MFG_TEST +static MV_VOID mvDramMfgTrst(void) +{ + + /* Memory test */ + DECLARE_GLOBAL_DATA_PTR; + unsigned int mem_len,i,j, pattern; + unsigned int *mem_start; + char *env; + + env = getenv("enaPost"); + if(!env || ( (strcmp(env,"Yes") == 0) || (strcmp(env,"yes") == 0) ) ) + { + printf("Memory test pattern: "); + + for (j = 0 ; j<2 ; j++) + { + + switch(j){ + case 0: + pattern=0x55555555; + printf("0x%X, ",pattern); + break; + case 1: + pattern=0xAAAAAAAA; + printf("0x%X, ",pattern); + break; + default: + pattern=0x0; + printf("0x%X, ",pattern); + break; + } + + for(i = 0; i< MV_DRAM_MAX_CS; i++) + { + mem_start = (unsigned int *)gd->bd->bi_dram[i].start; + mem_len = gd->bd->bi_dram[i].size; + if (i == 0) + { + mem_start+= _4M; + mem_len-= _4M; + } + mem_len/=4; + if (MV_OK != mv_mem_test(mem_start, pattern, mem_len)) + { + printf(" Fail!\n"); + while(1); + } + } + } + printf(" Pass\n"); + } +} + + +static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count) +{ + int i; + for (i=0 ; i< count ; i+=1) + *(pMem + i) = pattern; + + if (MV_OK != mv_mem_cmp(pMem, pattern, count)) + { + return MV_ERROR; + } + return MV_OK; +} + +static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count) +{ + int i; + for (i=0 ; i< count ; i+=1) + { + if (*(pMem + i) != pattern) + { + printf("Fail\n"); + printf("Test failed at 0x%x\n",(pMem + i)); + return MV_ERROR; + } + } + + return MV_OK; +} +#endif /* MV_INC_DRAM_MFG_TEST */ diff --git a/board/mv_feroceon/mv_dd/mv_main.c b/board/mv_feroceon/mv_dd/mv_main.c new file mode 100644 index 0000000..c3ef7f9 --- /dev/null +++ b/board/mv_feroceon/mv_dd/mv_main.c @@ -0,0 +1,1623 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +#include "mvCtrlEnvLib.h" +#include +#include "mvTypes.h" +#include "mvBoardEnvLib.h" +#include "mvCpuIf.h" +#include "mvCtrlEnvLib.h" +#include "mv_mon_init.h" +#include "mvDebug.h" +#include "device/mvDevice.h" +#include "twsi/mvTwsi.h" +#include "eth/mvEth.h" +#include "pex/mvPex.h" +#include "eth-phy/mvEthPhy.h" +#include "ethSwitch/mvSwitch.h" +#include "gpp/mvGpp.h" +#include "sys/mvSysUsb.h" + +#ifdef MV_INCLUDE_RTC +#include "rtc/integ_rtc/mvRtc.h" +#elif defined CONFIG_RTC_DS1338_DS1339 +#include "rtc/ext_rtc/mvDS133x.h" +#endif + +#if defined(MV_INCLUDE_XOR) +#include "xor/mvXor.h" +extern MV_STATUS mvXorInit (MV_VOID); +#endif +#if defined(MV_INCLUDE_IDMA) +#include "sys/mvSysIdma.h" +#include "idma/mvIdma.h" +extern MV_STATUS mvDmaInit (MV_VOID); +#endif +#if defined(MV_INCLUDE_USB) +#include "usb/mvUsb.h" +#endif + +#include "cpu/mvCpu.h" + +#ifdef CONFIG_PCI +# include +#endif +#include "pci/mvPciRegs.h" + +#include +#include + +#include "net.h" +#include + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +#if defined(DUAL_OS_78200) && defined(MV_NAND_BOOT) +#error "Dual OS boot from NAND is not supported: use LNX_SHARED=1 configuration" +#endif + +/* CPU address decode table. */ +MV_CPU_DEC_WIN mvCpuAddrWinMap[] = MV_CPU_IF_ADDR_WIN_MAP_TBL; +#if defined(MV78XX0) && defined(MV_INCLUDE_MONT_EXT) +MV_CPU_DEC_WIN mvCpuAddrWinMonExtMap[] = MV_CPU_IF_ADDR_WIN_MON_EXT_MAP_TBL; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) +static void recoveryDetection(void); +void recoveryHandle(void); +static u32 rcvrflag = 0; +#endif +void mv_cpu_init(void); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +int mv_set_power_scheme(void); +#endif + +#ifdef CFG_FLASH_CFI_DRIVER +MV_VOID mvUpdateNorFlashBaseAddrBank(MV_VOID); +int mv_board_num_flash_banks; +extern flash_info_t flash_info[]; /* info for FLASH chips */ +extern unsigned long flash_add_base_addr (uint flash_index, ulong flash_base_addr); +#endif /* CFG_FLASH_CFI_DRIVER */ + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) +extern MV_VOID mvBoardEgigaPhySwitchInit(void); +#endif + +extern unsigned int whoAmI(void); + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +/* Define for SDK 2.0 */ +int __aeabi_unwind_cpp_pr0(int a,int b,int c) {return 0;} +int __aeabi_unwind_cpp_pr1(int a,int b,int c) {return 0;} +#endif + +#if 0 +MV_VOID mvMppModuleTypePrint(MV_VOID); +#endif + +/* Define for SDK 2.0 */ +int raise(void) {return 0;} + +void print_mvBanner(void) +{ +#ifdef CONFIG_SILENT_CONSOLE + DECLARE_GLOBAL_DATA_PTR; + gd->flags |= GD_FLG_SILENT; +#endif + printf("\n"); + printf(" __ __ _ _\n"); + printf(" | \\/ | __ _ _ ____ _____| | |\n"); + printf(" | |\\/| |/ _` | '__\\ \\ / / _ \\ | |\n"); + printf(" | | | | (_| | | \\ V / __/ | |\n"); + printf(" |_| |_|\\__,_|_| \\_/ \\___|_|_|\n"); + printf(" _ _ ____ _\n"); + printf("| | | | | __ ) ___ ___ | |_ \n"); + printf("| | | |___| _ \\ / _ \\ / _ \\| __| \n"); + printf("| |_| |___| |_) | (_) | (_) | |_ \n"); + printf(" \\___/ |____/ \\___/ \\___/ \\__| "); +#if !defined(MV_NAND_BOOT) +#if defined(MV_INCLUDE_MONT_EXT) + if(!enaMonExt()) + printf(" ** LOADER **"); + else + printf(" ** MONITOR **"); +#else + + printf(" ** Forcing LOADER mode only **"); +#endif /* MV_INCLUDE_MONT_EXT */ +#endif + return; +} + +void print_dev_id(void){ + static char boardName[30]; + + mvBoardNameGet(boardName); + +#if defined(MV_CPU_BE) + printf("\n ** MARVELL BOARD: %s BE ",boardName); +#else + printf("\n ** MARVELL BOARD: %s LE ",boardName); +#endif + + return; +} + + +void maskAllInt(void) +{ + /* mask all external interrupt sources */ + MV_REG_WRITE(CPU_AHB_MBUS_MASK_INT_REG(whoAmI()), 0); + MV_REG_WRITE(CPU_INT_MASK_ERROR_REG(whoAmI()), 0); + MV_REG_WRITE(CPU_INT_MASK_LOW_REG(whoAmI()), 0); + MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(whoAmI()), 0); +} + +/* init for the Master*/ +void misc_init_r_dec_win(void) +{ +#if defined(MV_INCLUDE_USB) + { + char *env; + + env = getenv("usb0Mode"); + if((!env) || (strcmp(env,"host") == 0) || (strcmp(env,"Host") == 0) ) + { + setenv("usb0Mode","host"); + printf("USB 0: host mode\n"); + mvUsbInit(0, MV_TRUE); + } + else + { + printf("USB 0: device mode\n"); + mvUsbInit(0, MV_FALSE); + } + + env = getenv("usb1Mode"); + if((!env) || (strcmp(env,"host") == 0) || (strcmp(env,"Host") == 0) ) + { + setenv("usb1Mode","host"); + printf("USB 1: host mode\n"); + mvUsbInit(1, MV_TRUE); + } + else + { + printf("USB 1: device mode\n"); + mvUsbInit(1, MV_FALSE); + } + + env = getenv("usb2Mode"); + if((!env) || (strcmp(env,"device") == 0) || (strcmp(env,"Device") == 0) ) + { + setenv("usb2Mode","device"); + printf("USB 2: device mode\n"); + mvUsbInit(2, MV_FALSE); + } + else + { + printf("USB 2: host mode\n"); + mvUsbInit(2, MV_TRUE); + } + + + } +#endif/* #if defined(MV_INCLUDE_USB) */ + +#if defined(MV_INCLUDE_XOR) + mvXorInit(); +#endif +#if defined(MV_INCLUDE_IDMA) + mvDmaInit(); +#endif +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + mv_set_power_scheme(); +#endif + + return; +} + + +/* + * Miscellaneous platform dependent initialisations + */ + +extern MV_STATUS mvEthPhyRegRead(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 *data); +extern MV_STATUS mvEthPhyRegWrite(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 data); + +/* golabal mac address for yukon EC */ +unsigned char yuk_enetaddr[6]; +extern int interrupt_init (void); +extern void i2c_init(int speed, int slaveaddr); + +int cpuMapInit (void) +{ +#ifndef MV_TINY_IMAGE + /* For Mon ext mode only we reset the PEX mem base from 0xc0000000 to + 0x90000000 in order to enable working with CIV page table */ +#if defined(MV78XX0) + if (enaMonExt()) + mvCpuIfInit(mvCpuAddrWinMonExtMap); +#endif +#endif + return 0; +} + + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; +#if defined(MV_INCLUDE_TWSI) + MV_TWSI_ADDR slave; +#endif + unsigned int i; + + maskAllInt(); + + if (whoAmI() == MASTER_CPU) + { + /* must initialize the int in order for udelay to work */ + interrupt_init(); + +#if defined(MV_INCLUDE_TWSI) + slave.type = ADDR7_BIT; + slave.address = 0; + for (i = 0; i < MV_TWSI_MAX_CHAN; i++) + mvTwsiInit(i, CFG_I2C_SPEED, CFG_TCLK, &slave, 0); +#endif + + /* Init the Board environment module (device bank params init) */ + mvBoardEnvInit(); + } + + /* Init the Controlloer environment module (MPP init) */ + mvCtrlEnvInit(); + + if (whoAmI() == MASTER_CPU) + mvBoardDebug7Seg(3); + + /* Init the Controller CPU interface */ + mvCpuIfInit(mvCpuAddrWinMap); +#ifdef RD_MV78XX0_AMC + /* Set NAND on BootCS */ + MV_AHB_TO_MBUS_DEC_WIN addrDecWin; + addrDecWin.target = DEV_BOOCS; + addrDecWin.addrWin.baseLow = DEVICE_CS2_BASE; + addrDecWin.addrWin.baseHigh = 0; + addrDecWin.addrWin.size = _1M; + addrDecWin.enable = MV_TRUE; + mvAhbToMbusWinSet(0, 12, &addrDecWin); +#endif + + /* relocate the exception vectors */ + /* U-Boot is running from DRAM at this stage */ + for(i = 0; i < 0x100; i+=4) + { + *(unsigned int *)(0x0 + i) = *(unsigned int*)(TEXT_BASE + i); + } + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) + /* Init the PHY or Switch of the board */ + if (whoAmI() == MASTER_CPU) + mvBoardEgigaPhySwitchInit(); +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + + if (whoAmI() == MASTER_CPU) + mvBoardDebug7Seg(4); + + /* arch number of Integrator Board */ + gd->bd->bi_arch_number = 528; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + /* Update NOR flash base address bank for CFI driver */ +#ifdef CFG_FLASH_CFI_DRIVER + mvUpdateNorFlashBaseAddrBank(); +#endif /* CFG_FLASH_CFI_DRIVER */ + + return 0; +} + +void misc_init_r_env(void){ + char *env; + char tmp_buf[10]; + unsigned int malloc_len; + DECLARE_GLOBAL_DATA_PTR; + + unsigned int flashSize =0 , secSize =0, ubootSize =0; + char buff[256]; + +#if defined(MV_BOOTSIZE_4M) + flashSize = _4M; +#elif defined(MV_BOOTSIZE_8M) + flashSize = _8M; +#elif defined(MV_BOOTSIZE_16M) + flashSize = _16M; +#elif defined(MV_BOOTSIZE_32M) + flashSize = _32M; +#elif defined(MV_BOOTSIZE_64M) + flashSize = _64M; +#endif + +#if defined(MV_SEC_64K) + secSize = _64K; +#if defined(MV_TINY_IMAGE) + ubootSize = _256K; +#else + ubootSize = _512K; +#endif +#elif defined(MV_SEC_128K) + secSize = _128K; +#if defined(MV_TINY_IMAGE) + ubootSize = _128K * 3; +#else + ubootSize = _128K * 5; +#endif +#elif defined(MV_SEC_256K) + secSize = _256K; +#if defined(MV_TINY_IMAGE) + ubootSize = _256K * 3; +#else + ubootSize = _256K * 3; +#endif +#endif + /* Dual CPU Firmware load address */ + env = getenv("fw_image_base"); + if(!env) + setenv("fw_image_base", "0x0"); + + /* Dual CPU Firmware size */ + env = getenv("fw_image_size"); + if(!env) + setenv("fw_image_size", "0x0"); +#ifndef MV632X +#ifndef MV_STATIC_DRAM_ON_BOARD +#ifdef CONFIG_MV_ECC + /* update the enaECC env parameter */ + env = getenv("enaECC"); + if(env && ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("enaECC","yes"); + else +#endif + setenv("enaECC","no"); +#endif +#endif + if ((0 == flashSize) || (0 == secSize) || (0 == ubootSize)) + { + env = getenv("console"); + if(!env) + setenv("console","console=ttyS0,115200"); + } + else + { + sprintf(buff,"console=ttyS0,115200 mtdparts=cfi_flash:0x%x(root),0x%x(uboot)ro", + flashSize - ubootSize, ubootSize); + env = getenv("console"); + if(!env) + setenv("console",buff); + } + + + /* Linux open port support */ + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + setenv("mainlineLinux","yes"); + else + setenv("mainlineLinux","no"); + + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + /* arch number for open port Linux */ + env = getenv("arcNumber"); + if(!env ) + { + /* arch number according to board ID */ + int board_id = mvBoardIdGet(); + switch(board_id){ + case(DB_78XX0_ID): + sprintf(tmp_buf,"%d", DB_78XX0_BP_MLL_ID); + board_id = DB_78XX0_BP_MLL_ID; + /* Set CPU ID to MRVL */ + MV_REG_BIT_SET(CPU_CONFIG_REG(whoAmI()),CCR_MRVL_CPU_ID); + + break; + default: + sprintf(tmp_buf,"%d", board_id); + board_id = board_id; + break; + } + gd->bd->bi_arch_number = board_id; + setenv("arcNumber", tmp_buf); + } + else + { + gd->bd->bi_arch_number = simple_strtoul(env, NULL, 10); + } + } + + /* update the CASset env parameter */ + env = getenv("CASset"); + if(!env ) + { +#ifdef MV_MIN_CAL + setenv("CASset","min"); +#else + setenv("CASset","max"); +#endif + } + /* Monitor extension */ +#ifdef MV_INCLUDE_MONT_EXT + env = getenv("enaMonExt"); + if(/* !env || */ ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("enaMonExt","yes"); + else +#endif + setenv("enaMonExt","no"); + +#if defined (MV_INC_BOARD_NOR_FLASH) + env = getenv("enaFlashBuf"); + if( ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("enaFlashBuf","no"); + else + setenv("enaFlashBuf","yes"); +#endif + + /* CPU streaming */ + env = getenv("enaCpuStream"); + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("enaCpuStream","yes"); + else + setenv("enaCpuStream","no"); + + /* Write allocation */ + env = getenv("enaWrAllo"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaWrAllo","no"); + else + setenv("enaWrAllo","yes"); + + /* FPU */ + env = getenv("enaFPU"); + if( !env || ( ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ))) + setenv("enaFPU","yes"); + else + setenv("enaFPU","no"); + + /* Pex mode */ + env = getenv("pexMode"); + if( env && ( ((strcmp(env,"EP") == 0) || (strcmp(env,"ep") == 0) ))) + setenv("pexMode","EP"); + else + setenv("pexMode","RC"); + + env = getenv("disL2Cache"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("disL2Cache","no"); + else + setenv("disL2Cache","yes"); + + env = getenv("setL2CacheWT"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("setL2CacheWT","no"); + else + setenv("setL2CacheWT","yes"); + + env = getenv("disL2Prefetch"); + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("disL2Prefetch","yes"); + else + setenv("disL2Prefetch","no"); +#if !defined(MV76100) && !defined(MV632X) + env = getenv("setL2Size256K"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("setL2Size256K","no"); + else + setenv("setL2Size256K","yes"); +#else + setenv("setL2Size256K","yes"); +#endif + + env = getenv("disL2Ecc"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("disL2Ecc","no"); + else + setenv("disL2Ecc","yes"); + + + env = getenv("sata_dma_mode"); + if( env && ((strcmp(env,"No") == 0) || (strcmp(env,"no") == 0) ) ) + setenv("sata_dma_mode","no"); + else + setenv("sata_dma_mode","yes"); + + + /* Malloc length */ + env = getenv("MALLOC_len"); + malloc_len = simple_strtoul(env, NULL, 10) << 20; + if(malloc_len == 0){ + sprintf(tmp_buf,"%d",CFG_MALLOC_LEN>>20); + setenv("MALLOC_len",tmp_buf); + } + + /* primary network interface */ + env = getenv("ethprime"); + if(!env) + setenv("ethprime",ENV_ETH_PRIME); + + /* netbsd boot arguments */ + env = getenv("netbsd_en"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("netbsd_en","no"); + else + { + setenv("netbsd_en","yes"); + env = getenv("netbsd_gw"); + if(!env) + setenv("netbsd_gw","192.168.0.254"); + + env = getenv("netbsd_mask"); + if(!env) + setenv("netbsd_mask","255.255.255.0"); + + env = getenv("netbsd_fs"); + if(!env) + setenv("netbsd_fs","nfs"); + + env = getenv("netbsd_server"); + if(!env) + setenv("netbsd_server","192.168.0.1"); + + env = getenv("netbsd_ip"); + if(!env) + { + env = getenv("ipaddr"); + setenv("netbsd_ip",env); + } + + env = getenv("netbsd_rootdev"); + if(!env) + setenv("netbsd_rootdev","mgi0"); + + env = getenv("netbsd_add"); + if(!env) + setenv("netbsd_add","0x800000"); + + env = getenv("netbsd_get"); + if(!env) + setenv("netbsd_get","tftpboot $(netbsd_add) $(image_name)"); + +#if defined(MV_INC_BOARD_QD_SWITCH) + env = getenv("netbsd_netconfig"); + if(!env) + setenv("netbsd_netconfig","mv_net_config=<((mgi0,00:00:11:22:33:44,0)(mgi1,00:00:11:22:33:55,1:2:3:4)),mtu=1500>"); +#endif + env = getenv("netbsd_set_args"); + if(!env) + setenv("netbsd_set_args","setenv bootargs nfsroot=$(netbsd_server):$(rootpath) fs=$(netbsd_fs) \ +ip=$(netbsd_ip) serverip=$(netbsd_server) mask=$(netbsd_mask) gw=$(netbsd_gw) rootdev=$(netbsd_rootdev) \ +ethaddr=$(ethaddr) eth1addr=$(eth1addr) ethmtu=$(ethmtu) eth1mtu=$(eth1mtu) $(netbsd_netconfig)"); + + env = getenv("netbsd_boot"); + if(!env) + setenv("netbsd_boot","bootm $(netbsd_add) $(bootargs)"); + + env = getenv("netbsd_bootcmd"); + if(!env) + setenv("netbsd_bootcmd","run netbsd_get ; run netbsd_set_args ; run netbsd_boot"); + } + + /* linux boot arguments */ + env = getenv("bootargs_root"); + if(!env) +#if defined(DUAL_OS_SHARED_MEM_78200) + setenv("bootargs_root","mem=120M root=/dev/nfs rw"); +#else + setenv("bootargs_root","root=/dev/nfs rw"); +#endif + /* For open Linux we set boot args differently */ + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + env = getenv("bootargs_end"); + if(!env) + setenv("bootargs_end",":::orion:eth0:none"); + } + else + { + env = getenv("bootargs_end"); + if(!env) +#if defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootargs_end",CFG_BOOTARGS_END_SWITCH); +#else + setenv("bootargs_end",CFG_BOOTARGS_END); +#endif + } + + env = getenv("image_name"); + if(!env) + setenv("image_name","uImage"); + + +#if (CONFIG_BOOTDELAY >= 0) + env = getenv("bootcmd"); + if(!env) +#if defined(MV_INCLUDE_TDM) && defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootcmd","tftpboot 0x400000 $(image_name);\ +setenv bootargs $(console) $(bootargs_root) nfsroot=$(serverip):$(rootpath) cpu0=$(cpu0_res) cpu1=$(cpu1_res) \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig) $(mvPhoneConfig); bootm 0x400000; "); +#elif defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootcmd","tftpboot 0x400000 $(image_name);\ +setenv bootargs $(console) $(bootargs_root) nfsroot=$(serverip):$(rootpath) cpu0=$(cpu0_res) cpu1=$(cpu1_res) \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig); bootm 0x400000; "); +#elif defined(MV_INCLUDE_TDM) + setenv("bootcmd","tftpboot 0x400000 $(image_name);\ +setenv bootargs $(console) $(bootargs_root) nfsroot=$(serverip):$(rootpath) cpu0=$(cpu0_res) cpu1=$(cpu1_res) \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvPhoneConfig); bootm 0x400000; "); +#else + setenv("bootcmd","tftpboot 0x400000 $(image_name);\ +setenv bootargs $(console) $(bootargs_root) nfsroot=$(serverip):$(rootpath) cpu0=$(cpu0_res) cpu1=$(cpu1_res) \ +ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "); +#endif +#endif /* (CONFIG_BOOTDELAY >= 0) */ + + env = getenv("standalone"); + if(!env) +#if defined(DUAL_OS_SHARED_MEM_78200) + setenv("standalone","lockSem 1;fsload 0x2000000 $(image_name);setenv bootargs $(console) root=/dev/mtdblock0 rw \ + ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig) $(mvPhoneConfig); bootm 0x2000000;"); +#else +#if defined(MV_INCLUDE_TDM) && defined(MV_INC_BOARD_QD_SWITCH) + setenv("standalone","fsload 0x2000000 $(image_name);setenv bootargs $(console) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig) $(mvPhoneConfig); bootm 0x2000000;"); +#elif defined(MV_INC_BOARD_QD_SWITCH) + setenv("standalone","fsload 0x2000000 $(image_name);setenv bootargs $(console) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig); bootm 0x2000000;"); +#elif defined(MV_INCLUDE_TDM) + setenv("standalone","fsload 0x2000000 $(image_name);setenv bootargs $(console) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvPhoneConfig); bootm 0x2000000;"); +#else + setenv("standalone","fsload 0x2000000 $(image_name);setenv bootargs $(console) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x2000000;"); +#endif +#endif + /* Set boodelay to 3 sec, if Monitor extension are disabled */ + if(!enaMonExt()){ + setenv("bootdelay","3"); + setenv("disaMvPnp","no"); + } + + /* Disable PNP config of Marvel memory controller devices. */ + env = getenv("disaMvPnp"); + if(!env) + setenv("disaMvPnp","no"); + +#if (defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH)) +#include "cesa/mvMD5.h" + /* Generate random ip and mac address */ + /* Read DRAM FTDLL register to create random data for enc */ + unsigned int xi, xj, xk, xl, i; + char ethaddr[4][30]; + + char temp[20]; + MV_U32 random[16]; + unsigned char digest[16]; + + MV_REG_BIT_SET(0x1478, BIT7); + for(i=0; i < 16;i++) + random[i] = MV_REG_READ(0x1470); + + /* Run MD5 over the ftdll buffer */ +#ifndef MV_TINY_IMAGE + mvMD5((unsigned char*)random, 64, digest); +#endif + + xi = (digest[0]%254); + /* No valid ip with one of the fileds has the value 0 */ + if (xi == 0) + xi+=2; + + xj = (digest[1]%254); + /* No valid ip with one of the fileds has the value 0 */ + if (xj == 0) + xj+=2; + + /* Check if the ip address is the same as the server ip */ + if ((xj == 1) && (xi == 11)) + xi+=2; + + xk = digest[2]; + xl = digest[3]; + + sprintf(ethaddr[0],"00:50:43:%02x:%02x:%02x",xk,xi,xj); + sprintf(ethaddr[1],"00:50:43:%02x:%02x:%02x",xl,xi,xj); + sprintf(ethaddr[2],"00:50:43:%02x:%02x:%02x",xk,xj,xi); + sprintf(ethaddr[3],"00:50:43:%02x:%02x:%02x",xl,xj,xi); + + /* MAC addresses */ + for (i = 0 ;i < mvCtrlEthMaxPortGet();i++) + { + sprintf( temp,(i ? "eth%daddr" : "ethaddr"), i); + env = getenv(temp); + if(!env) + setenv(temp,ethaddr[i]); + + sprintf( temp,(i ? "eth%dmtu" : "ethmtu"), i); + env = getenv(temp); + if(!env) + setenv(temp,"1500"); + } +#if defined(MV_INCLUDE_TDM) + /* Set mvPhoneConfig env parameter */ + env = getenv("mvPhoneConfig"); + if(!env ) + setenv("mvPhoneConfig","mv_phone_config=dev0:fxs,dev1:fxo"); +#endif +#if defined(MV_INC_BOARD_QD_SWITCH) + /* Set mvNetConfig env parameter */ + env = getenv("mvNetConfig"); + if(!env ) + setenv("mvNetConfig","mv_net_config=(00:aa:bb:cc:dd:ee,0)(00:11:22:33:44:55,1:2:3:4),mtu=1500"); +#endif +#endif /* (MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) */ + +#if defined(MV_INCLUDE_USB) + /* USB Host */ + env = getenv("usb0Mode"); + if(!env) + setenv("usb0Mode",ENV_USB0_MODE); + + env = getenv("usb1Mode"); + if(!env) + setenv("usb1Mode",ENV_USB1_MODE); + + env = getenv("usb2Mode"); + if(!env) + setenv("usb2Mode",ENV_USB2_MODE); +#endif /* (MV_INCLUDE_USB) */ + +#if defined(YUK_ETHADDR) + env = getenv("yuk_ethaddr"); + if(!env) + setenv("yuk_ethaddr",YUK_ETHADDR); + + { + int i; + char *tmp = getenv ("yuk_ethaddr"); + char *end; + + for (i=0; i<6; i++) { + yuk_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + } +#endif /* defined(YUK_ETHADDR) */ + +#if defined(MV_NAND) + env = getenv("nandEcc"); + if(!env) + { + setenv("nandEcc", "1bit"); + } +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) + env = getenv("netretry"); + if (!env) + setenv("netretry","no"); + + env = getenv("rcvrip"); + if (!env) + setenv("rcvrip",RCVR_IP_ADDR); + + env = getenv("loadaddr"); + if (!env) + setenv("loadaddr",RCVR_LOAD_ADDR); + + env = getenv("autoload"); + if (!env) + setenv("autoload","no"); + +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) + /* Check the recovery trigger */ + recoveryDetection(); +#endif +#endif + int vxWorksFlags = 0; + +#if defined(MV78200) && (defined(DUAL_OS_78200) || defined(DUAL_OS_SHARED_MEM_78200)) + char ethnum[20]; + + /* U-boot none shared device policy */ + /* + env = getenv("cpu0_res"); + if (env) + mvSocUnitMapFillTable(env, MASTER_CPU, strstr); + env = getenv("cpu1_res"); + if (env) + mvSocUnitMapFillTable(env, SLAVE_CPU, strstr); + */ + vxWorksFlags = mvSocUnitMapFillFlagFormTable(); + + /* CPU resource arguments */ + env = getenv("cpu0_res"); + if (!env) +#if defined(MV_SPI_BOOT) + setenv("cpu0_res","egiga0,egiga1,pcie0,pcie1,sata,nor,nand,usb0,usb1,usb2,xor"); +#elif defined(MV_NAND_BOOT) + setenv("cpu0_res","egiga0,egiga1,pcie0,pcie1,sata,nor,spi,usb0,usb1,usb2,xor"); +#else + setenv("cpu0_res","egiga0,egiga1,pcie0,pcie1,sata,nand,spi,usb0,usb1,usb2,xor"); +#endif + + env = getenv("cpu1_res"); + if (!env) +#ifdef MV6323 + setenv("cpu1_res","egiga2"); +#else + setenv("cpu1_res","egiga2,egiga3"); +#endif + + /* Second linux boot arguments */ + env = getenv("ipaddr2"); + if(!env) + setenv("ipaddr2","10.4.50.166"); + + env = getenv("image_name2"); + if(!env) + setenv("image_name2","uImage"); + + env = getenv("console2"); + if(!env) + setenv("console2","console=ttyS0,115200"); + + env = getenv("rootpath2"); + if(!env) + setenv("rootpath2","/mnt/ARM_FS/"); + + env = getenv("bootargs_end2"); + if(!env) + setenv("bootargs_end2",":::DB78xx0:eth0:none"); + + env = getenv("bootcmd2"); + if(!env) +#if defined(DUAL_OS_SHARED_MEM_78200) + setenv("bootcmd2","lockSem 1;tftpboot 0xA000000 $(image_name2); setenv bootargs2 $(console2) \ +$(bootargs_root2) nfsroot=$(serverip):$(rootpath2) cpu0=$(cpu0_res) cpu1=$(cpu1_res) ip=$(ipaddr2):$(serverip)$(bootargs_end2); \ +bootm 0xA000000; "); +#else + setenv("bootcmd2","tftpboot 0x2000000 $(image_name2); setenv bootargs2 $(console2) \ +$(bootargs_root2) nfsroot=$(serverip):$(rootpath2) cpu0=$(cpu0_res) cpu1=$(cpu1_res) ip=$(ipaddr2):$(serverip)$(bootargs_end2); \ +bootm 0x2000000; "); +#endif + env = getenv("bootargs_root2"); + if(!env) +#if defined(DUAL_OS_SHARED_MEM_78200) + setenv("bootargs_root2","mem=128M root=/dev/nfs rw"); +#else + setenv("bootargs_root2","root=/dev/nfs rw"); +#endif + env = getenv("enaMP"); + if(!env) + setenv("enaMP","no"); +#endif + + + /* vxWorks boot arguments */ + env = getenv("vxworks_en"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("vxworks_en","no"); + else + { + char* buff = (char *)0x1100; + int usbFlag = 0; + char usbFlagSt[10]; + setenv("vxworks_en","yes"); + + /* Getting image name for each CPU */ + sprintf(buff,"mgi(0,0) host:"); + if (whoAmI()) + env = getenv("image_name2"); + else + env = getenv("image_name"); + strcat(buff,env); + + /* Getting ip address and server ip */ + env = getenv("serverip"); + strcat(buff, " h="); + strcat(buff,env); + + if (whoAmI()) + env = getenv("ipaddr2"); + else + env = getenv("ipaddr"); + + strcat(buff, " e="); + strcat(buff,env); + + /* Getting USB mode for each port */ + env = getenv("usb0Mode"); + if((!env) || (strcmp(env,"host") == 0) || (strcmp(env,"Host") == 0) ) + { + usbFlag |= 0x2000; + } + + env = getenv("usb1Mode"); + if((!env) || (strcmp(env,"host") == 0) || (strcmp(env,"Host") == 0) ) + { + usbFlag |= 0x4000; + } + + env = getenv("usb2Mode"); + if((!env) || (strcmp(env,"host") == 0) || (strcmp(env,"Host") == 0) ) + { + usbFlag |= 0x8000; + } + + strcat(buff, ":ffff0000 u=anonymous pw=target f="); + sprintf(usbFlagSt,"0x%x",usbFlag); + strcat(buff, usbFlagSt); + setenv("vxWorks_bootargs",buff); + MV_REG_WRITE(GENERAL_USAGE_REGISTER_0, vxWorksFlags); + } + + return; +} + +#ifdef BOARD_LATE_INIT +int board_late_init (void) +{ + /* Check if to use the LED's for debug or to use single led for init and Linux heartbeat */ + mvBoardDebug7Seg(0); + return 0; +} +#endif + +#if defined(MV78200) +extern MV_VOID mvDramIfSlaveCpuWinInit(MV_VOID); +extern MV_VOID mvDramIfCpuWinCopy(MV_VOID); +void second_cpu_realloc_and_load(void) +{ + char *env; + + if (whoAmI() == MASTER_CPU) + { + /* default no MP */ + env = getenv("enaMP"); + if(env && ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + { + if (IS_CPU1_ENABLED) + { + printf("\nRelocate and enable second CPU\n"); + /* Copy CPU 0 address map to CPU 1 */ + mvAhbToMbusCpuWinCopy(); +#if defined(DUAL_OS_78200) + /* kick of the second CPU!! */ + if (mvDramIfBankSizeGet(2)) + { + /* Copy CPU 0 DRAM address map to CPU 1 */ + mvDramIfSlaveCpuWinInit(); + MV_REG_BIT_RESET(CPU_CTRL_STAT_REG(1), BIT3); + } + else + printf("\nFail to enabled second CPU - no Dram on CS 2!\n"); +#else + /* Copy CPU 0 DRAM address map to CPU 1 */ + mvDramIfCpuWinCopy(); +#if defined(DUAL_OS_SHARED_MEM_78200) + /* Copy CPU 0 DRAM address map to CPU 1 */ + MV_REG_BIT_RESET(CPU_CONFIG_REG(1), BIT1); + { + volatile unsigned int *a = (0x0); + extern volatile unsigned int* _start; + a[0] = 0xe3a00008; /*mov r0, #8 ; 0x4*/ + a[1] = 0xe590f000; /*ldr pc, [r0]*/ + a[2] = ((unsigned int)&_start)+0x70000; + __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); + } + /* kick off the second CPU!! */ +#endif + MV_REG_BIT_RESET(CPU_CTRL_STAT_REG(1), BIT3); +#endif + } + } + else + setenv("enaMP", "no"); + } +} +#endif + +int misc_init_r (void) +{ + char name[128]; + + if (whoAmI() == MASTER_CPU) + { + mvBoardDebug7Seg(5); + + } + /* init special env variables */ + misc_init_r_env(); + + mvCpuNameGet(name); + printf("\nCPU %d: %s\n", whoAmI(), name); + + mv_cpu_init(); + +#if defined(MV_INCLUDE_MONT_EXT) + if(enaMonExt()){ + printf("\n Marvell monitor extension:\n"); + mon_extension_after_relloc(); + } + printf("\n"); +#endif /* MV_INCLUDE_MONT_EXT */ + + printf("\n"); + /* init the units decode windows */ + if (whoAmI() == MASTER_CPU) + { + misc_init_r_dec_win(); + + mvBoardDebug7Seg(6); + } +#ifdef CONFIG_PCI +#if !defined(MV_MEM_OVER_PCI_WA) && !defined(MV_MEM_OVER_PEX_WA) +#ifdef MV78200 + if ( ! ((whoAmI() == SLAVE_CPU) && enaMonExt() && enaMP()) ) +#endif + pci_init(); +#endif +#endif + if (whoAmI() == MASTER_CPU) + { + mvBoardDebug7Seg(7); + } + + return 0; +} + +MV_U32 mvTclkGet(void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* get it only on first time */ + if(gd->tclk == 0) + gd->tclk = mvBoardTclkGet(); + + return gd->tclk; +} + +MV_U32 mvSysClkGet(void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* get it only on first time */ + if(gd->bus_clk == 0) + gd->bus_clk = mvBoardSysClkGet(); + + return gd->bus_clk; +} + +/* exported for EEMBC */ +MV_U32 mvGetRtcSec(void) +{ +#if (CONFIG_COMMANDS & CFG_CMD_DATE) + MV_RTC_TIME time; +#ifdef MV_INCLUDE_RTC + mvRtcTimeGet(&time); +#elif defined CONFIG_RTC_DS1338_DS1339 + mvRtcDS133xTimeGet(&time); +#endif + return (time.minutes * 60) + time.seconds; +#else + return 0; +#endif +} + +void reset_cpu(void) +{ + mvBoardReset(); +} + +void mv_cpu_init(void) +{ + char *env; + volatile unsigned int temp; + + /* Invalidate and Unlock CPU L1 I-cache which was locked in jump.s */ + temp = 0; + __asm__ __volatile__("mcr p15, 1, %0, c7, c5, 0" : "=r" (temp)); + __asm__ __volatile__("nop"); + __asm__ __volatile__("nop"); + __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 1" : "=r" (temp)); + __asm__ __volatile__("nop"); + __asm__ __volatile__("nop"); + + if (whoAmI()) + MV_REG_BIT_SET(CPU_CONFIG_REG(1), BIT1); + + /*CPU streaming & write allocate */ + env = getenv("enaWrAllo"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0" : "=r" (temp)); + temp |= BIT28; + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 0" :: "r" (temp)); + + } + else + { + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0" : "=r" (temp)); + temp &= ~BIT28; + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 0" :: "r" (temp)); + } + + env = getenv("enaCpuStream"); + if(!env || (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) + { + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0" : "=r" (temp)); + temp &= ~BIT29; + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 0" :: "r" (temp)); + } + else + { + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0" : "=r" (temp)); + temp |= BIT29; + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 0" :: "r" (temp)); + } + + /* Verify write allocate and streaming */ + printf("\n"); + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0" : "=r" (temp)); + if (temp & BIT29) + printf("Streaming enabled \n"); + else + printf("Streaming disabled \n"); + if (temp & BIT28) + printf("Write allocate enabled\n"); + else + printf("Write allocate disabled\n"); + + env = getenv("enaFPU"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + /* init and Enable FPU to Run Fast Mode */ + printf("FPU initialized to Run Fast Mode.\n"); + /* Enable */ + temp = FPEXC_ENABLE; + fmxr(FPEXC, temp); + /* Run Fast Mode */ + temp = fmrx(FPSCR); + temp |= (FPSCR_DEFAULT_NAN | FPSCR_FLUSHTOZERO); + fmxr(FPSCR, temp); + } + else + { + printf("FPU not initialized\n"); + /* Disable */ + temp = fmrx(FPEXC); + temp &= ~FPEXC_ENABLE; + fmxr(FPEXC, temp); + } + + /* DCache Pref */ + env = getenv("enaDCPref"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + MV_REG_BIT_SET( CPU_CONFIG_REG(whoAmI()) , CCR_DCACH_PREF_BUF_ENABLE); + + if(env && ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + MV_REG_BIT_RESET( CPU_CONFIG_REG(whoAmI()) , CCR_DCACH_PREF_BUF_ENABLE); + + /* ICache Pref */ + env = getenv("enaICPref"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + MV_REG_BIT_SET( CPU_CONFIG_REG(whoAmI()) , CCR_ICACH_PREF_BUF_ENABLE); + + if(env && ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + MV_REG_BIT_RESET( CPU_CONFIG_REG(whoAmI()) , CCR_ICACH_PREF_BUF_ENABLE); + + /* Set L2C WT mode - Set bit 17 */ + temp = MV_REG_READ(CPU_CTRL_STAT_REG(whoAmI())); + env = getenv("setL2CacheWT"); + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + temp |= BIT17; + else + temp &= ~BIT17; + + /* Set L2C size */ + env = getenv("setL2Size256K"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + temp &= ~BIT21; + else + temp |= BIT21; + MV_REG_WRITE(CPU_CTRL_STAT_REG(whoAmI()),temp); + + /* Set L2 ECC en/dis - Set bit 22 */ + temp = MV_REG_READ(CPU_CONFIG_REG(whoAmI())); + env = getenv("disL2Ecc"); + if(env && ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + temp |= BIT22; + else + temp &= ~BIT22; + MV_REG_WRITE(CPU_CONFIG_REG(whoAmI()),temp); + + /* L2Cache settings */ + asm ("mrc p15, 1, %0, c15, c1, 0":"=r" (temp)); + + /* Disable L2C pre fetch - Set bit 24 */ + env = getenv("disL2Prefetch"); + if(env && ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + temp &= ~BIT24; + else + temp |= BIT24; + + asm ("mcr p15, 1, %0, c15, c1, 0": :"r" (temp)); + + /* WA for CPU L2 cache clock ratio limited to 1:3 erratum FE-CPU-180*/ + MV_REG_BIT_RESET(CPU_TIMING_ADJUST_REG(0), BIT28); + MV_REG_BIT_RESET(CPU_TIMING_ADJUST_REG(1), BIT28); + while((MV_REG_READ(CPU_TIMING_ADJUST_REG(0)) & BIT28) == BIT28); + + /* enable L2C - Set bit 22 */ + env = getenv("disL2Cache"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + temp |= BIT22; + else + temp &= ~BIT22; + + asm ("mcr p15, 1, %0, c15, c1, 0": :"r" (temp)); + + + /* Enable i cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (temp)); + temp |= BIT12; + /* Change reset vector to address 0x0 */ + temp &= ~BIT13; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (temp)); +} +#if 0 +/******************************************************************************* +* mvBoardMppModuleTypePrint - print module detect +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvMppModuleTypePrint(MV_VOID) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U32 maxMppGrp = 1; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6282_DEV_ID: + maxMppGrp = MV_6282_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + mppGroupType = mvBoardMppGroupTypeGet(devClass); + + switch(mppGroupType) + { + case MV_BOARD_TDM: + printf("Module %d is TDM\n", devClass); + break; + case MV_BOARD_AUDIO: + printf("Module %d is AUDIO\n", devClass); + break; + case MV_BOARD_RGMII: + printf("Module %d is RGMII\n", devClass); + break; + case MV_BOARD_GMII: + printf("Module %d is GMII\n", devClass); + break; + case MV_BOARD_TS: + printf("Module %d is TS\n", devClass); + break; + default: + break; + } + } +} +#endif +/* Set unit in power off mode acording to the detection of MPP */ +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +int mv_set_power_scheme(void) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId) + { + case MV_6321_DEV_ID: + mvCtrlPwrClckSet(PEX_UNIT_ID, 1, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 2, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 3, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 4, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 5, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 6, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 7, MV_FALSE); + mvCtrlPwrClckSet(SATA_UNIT_ID, 0, MV_FALSE); + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT13); + mvCtrlPwrClckSet(SATA_UNIT_ID, 1, MV_FALSE); + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT15); + mvCtrlPwrClckSet(USB_UNIT_ID, 1, MV_FALSE); + mvCtrlPwrClckSet(USB_UNIT_ID, 2, MV_FALSE); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 2, MV_FALSE); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 3, MV_FALSE); + break; + case MV_6322_DEV_ID: + mvCtrlPwrClckSet(PEX_UNIT_ID, 1, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 2, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 3, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 5, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 6, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 7, MV_FALSE); + mvCtrlPwrClckSet(SATA_UNIT_ID, 0, MV_FALSE); + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT13); + mvCtrlPwrClckSet(SATA_UNIT_ID, 1, MV_FALSE); + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT15); + mvCtrlPwrClckSet(USB_UNIT_ID, 2, MV_FALSE); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 2, MV_FALSE); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 3, MV_FALSE); + break; + case MV_6323_DEV_ID: + mvCtrlPwrClckSet(PEX_UNIT_ID, 1, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 2, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 3, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 5, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 6, MV_FALSE); + mvCtrlPwrClckSet(PEX_UNIT_ID, 7, MV_FALSE); + mvCtrlPwrClckSet(SATA_UNIT_ID, 1, MV_FALSE); + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT15); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 3, MV_FALSE); + break; + } + return MV_OK; +} + +#endif /* defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + +/******************************************************************************* +* mvUpdateNorFlashBaseAddrBank - +* +* DESCRIPTION: +* This function update the CFI driver base address bank with on board NOR +* devices base address. +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* None +* +*******************************************************************************/ +#ifdef CFG_FLASH_CFI_DRIVER +MV_VOID mvUpdateNorFlashBaseAddrBank(MV_VOID) +{ + + MV_U32 devBaseAddr; + MV_U32 devNum = 0; + int i; + + /* Update NOR flash base address bank for CFI flash init driver */ + for (i = 0 ; i < CFG_MAX_FLASH_BANKS_DETECT; i++) + { + devBaseAddr = mvBoardGetDeviceBaseAddr(i,BOARD_DEV_NOR_FLASH); + if (devBaseAddr != 0xFFFFFFFF) + { + flash_add_base_addr (devNum, devBaseAddr); + devNum++; + } + } + mv_board_num_flash_banks = devNum; + + /* Update SPI flash count for CFI flash init driver */ + /* Assumption only 1 SPI flash on board */ + for (i = 0 ; i < CFG_MAX_FLASH_BANKS_DETECT; i++) + { + devBaseAddr = mvBoardGetDeviceBaseAddr(i,BOARD_DEV_SPI_FLASH); + if (devBaseAddr != 0xFFFFFFFF) + mv_board_num_flash_banks += 1; + } +} +#endif /* CFG_FLASH_CFI_DRIVER */ + +#if 0 +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) +static void recoveryDetection(void) +{ + MV_32 stateButtonBit = mvBoarGpioPinNumGet(BOARD_GPP_WPS_BUTTON,0); + MV_32 buttonHigh = 0; + char* env; + + /* Check if auto recovery is en */ + env = getenv("enaAutoRecovery"); + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("enaAutoRecovery","yes"); + else + { + setenv("enaAutoRecovery","no"); + rcvrflag = 0; + return; + } + + if (stateButtonBit == MV_ERROR) + { + rcvrflag = 0; + return; + } + + if (stateButtonBit > 31) + { + stateButtonBit = stateButtonBit % 32; + buttonHigh = 1; + } + + /* Set state input indication pin as input */ + MV_REG_BIT_SET(GPP_DATA_OUT_EN_REG(buttonHigh),(1< +#include "sflash/mvSFlash.h" + +void memcpyFlash(env_t *env_ptr, void* buffer, MV_U32 size) +{ + MV_SFLASH_INFO *pFlash; + pFlash = getMvFlashInfo(BOOT_FLASH_INDEX); + mvSFlashBlockRd(pFlash,(MV_U32 *)env_ptr - mvFlashBaseAddrGet(pFlash), + (MV_U8 *)buffer, size); +} +#endif + +#if defined(DUAL_OS_78200) +void mvUsbSwapWindows() +{ + /* Disable the window that belongs to the CS of the second CPU */ + MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(0, 1 - whoAmI()), 1); + MV_REG_BIT_SET(MV_USB_WIN_CTRL_REG(0, whoAmI()), 1); + MV_REG_WRITE(MV_USB_WIN_BASE_REG(0, whoAmI()), 0x0); +} +#endif + diff --git a/board/mv_feroceon/mv_dd/mv_service.c b/board/mv_feroceon/mv_dd/mv_service.c new file mode 100644 index 0000000..d7e9792 --- /dev/null +++ b/board/mv_feroceon/mv_dd/mv_service.c @@ -0,0 +1,66 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mv_service.h" + diff --git a/board/mv_feroceon/mv_dd/mv_service.h b/board/mv_feroceon/mv_dd/mv_service.h new file mode 100644 index 0000000..16ca10d --- /dev/null +++ b/board/mv_feroceon/mv_dd/mv_service.h @@ -0,0 +1,65 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + diff --git a/board/mv_feroceon/mv_dd/nBootstrap.S b/board/mv_feroceon/mv_dd/nBootstrap.S new file mode 100644 index 0000000..6701e41 --- /dev/null +++ b/board/mv_feroceon/mv_dd/nBootstrap.S @@ -0,0 +1,458 @@ +#define MV_ASMLANGUAGE +#include "nBootstrap.h" +#include "ddr2/mvDramIfRegs.h" +#include "ddr2/mvDramIfConfig.h" +#include "xor/mvXorRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */ +#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */ +#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */ + +/* XOR Engine Address Decoding Register Map */ +#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) +#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) +#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) + +#if !defined(MV_BOOTROM) +.globl nbootStart +nbootStart: + /* + * set the cpu to SVC32 mode, I and F disabled. + */ + mov r1, #0xd3 + msr cpsr,r1 + + /* + * flush v4 I/D caches + */ + mcr p15, 0, r1, c7, c7, 0 /* invalidate v3/v4 cache */ + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r1, c1, c0, 0 + bic r1, r1, #0x00000300 /* clear bits 9:8 (--V- --RS) */ + bic r1, r1, #0x00000007 /* clear bits 2:0 (-CAM) */ + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Add nop commands for cache flush operations */ + nop + nop + nop + nop + nop + nop + + /* here. MUST BE IN THE SAME CACHE LINE */ + + mov r0, #0 /* We use r0 as always '0' */ + +#ifdef NAND_CTRL_88F528x + + /* Load CPU controller base address 0xD0020000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x20000 + + MV_REG_READ_ASM (r1, r2, 0x20120) + bic r1, r1, #MV_32BIT_LE(0x7F00) + orr r1, r1, #MV_32BIT_LE(0x8200) + bic r1, r1, #MV_32BIT_LE(0x007F) + orr r1, r1, #MV_32BIT_LE(0x001b) + MV_REG_WRITE_ASM(r1, r2, 0x20120) + + /* Set CPU to Mbus-L DDR Interface Tick Driver and Tick Sample */ + MV_REG_READ_ASM (r1, r2, 0x20100) + bic r1, r1, #MV_32BIT_LE(0xFF00) + orr r1, r1, #MV_32BIT_LE(CPU_2_MBUSL_DDR_CLK) + MV_REG_WRITE_ASM(r1, r2, 0x20100) + +#endif /* NAND_CTRL_88F528x */ + + + /* DRAM memory initialization */ + + /* Load SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + + /* Write to SDRAM coniguration register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_CONFIG_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_CONFIG_REG) + + /* Write Dunit control low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_DUNIT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_DUNIT_CTRL_REG); + + /* Write SDRAM address control register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_ADDR_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_ADDR_CTRL_REG) + + /* Write SDRAM timing Low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_LOW_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_LOW_REG) + + /* Write SDRAM timing High register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_HIGH_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_HIGH_REG) + + /* Write DDR2 SDRAM timing Low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_DDR2_TIMING_LO_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_DDR2_TIMING_LO_REG) + + /* Write DDR2 SDRAM timing High register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_DDR2_TIMING_HI_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_DDR2_TIMING_HI_REG) + + /* Write SDRAM mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_MODE_REG) + + /* Write SDRAM Extended mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_EXTENDED_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_EXTENDED_MODE_REG) + + /* Config DDR2 On Die Termination (ODT) registers */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_LOW_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_LOW_REG) + + /* Write SDRAM DDR2 ODT control high register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + + /* Write SDRAM DDR2 Dunit ODT control register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_DUNIT_ODT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_DUNIT_ODT_CONTROL_REG) + + /*SDRAM_DUNIT_CTRL_HI_REG */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_DUNIT_CTRL_HI_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_DUNIT_CTRL_HI_REG) + + /* DDR SDRAM Initialization Control Register. Init enable */ + mov r1, #MV_32BIT_LE(DSICR_INIT_EN) + MV_REG_WRITE_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + +ddrInitLoop: + MV_REG_READ_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + cmp r1, #0 + bne ddrInitLoop + + /* Continue in next NAND page */ + + +/*****************************************************************************/ +/* This code open NAND page 1 for read and relocates the CPU to read */ +/* from that page. */ +/*****************************************************************************/ + + +/* r2 - is the page number */ +/* r5 - nand flash base */ +/* r6 - is cmd read */ +/* r0 - 0 */ +/* r9 - is cmd status */ +/* r4 - next address to jump */ + + /* Load the NAND base address */ + GPR_LOAD(r5, NAND_FLASH_BASE) + + /* init */ + mov r0, #0 + mov r2, #0x1 /* start with page 1 */ + mov r6, #CMD_READ + + mov r9, #CMD_STATUS + orr r4, r5, #0x200 + +.align 5 + b ncl +sop: + /* issue read command */ + strb r6, [r5, #NAND_CMD_PORT] + + /* issue address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r2, [r5, #NAND_ADDR_PORT] /* page address */ + strb r0, [r5, #NAND_ADDR_PORT] + + /* Check status */ + strb r9, [r5, #NAND_CMD_PORT] + b busy_loop + +.align 5 +ncl: + b ncl2 +busy_loop: + ldrb r1, [r5] + tst r1, #STATUS_READY + beq busy_loop + + /* back to read mode */ + strb r6, [r5, #NAND_CMD_PORT] + mov pc, r4 + +.align 5 +ncl2: + b sop + + +/* Next page must be in page offset - 512 bytes */ +.align 9 +page1: +/*****************************************************************************/ +/* This code extract the booter from the rest of block 1 which is known to */ +/* be error free (no need for ECC). This booter should copy the U-boot code */ +/* to DRAM */ +/*****************************************************************************/ + /* DRAM init - Cont'd */ + + /* Load back SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + /* Open SDRAM bank 0 size register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_SIZE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_SIZE_REG(0,0)) +#ifdef RD_MV78XX0_MASA_2DIMM + orr r1, #0x5 + MV_REG_WRITE_ASM(r1, r2, SDRAM_SIZE_REG(0,1)) + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_BASE1_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_BASE_ADDR_REG(0,1)) +#else + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(0,1)) +#endif + /* Close SDRAM bank 2,3 */ + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(0,2)) + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(0,3)) + + /* Prepare the address where to find the nandBoot function pointer */ + mov lr, #0x20000 + orr lr, lr, #0x620 +#if 1 + /* Load xor controller base address 0xd0060000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x60000 + + /* Disable all XOR address decode windows to avoid possible overlap */ + MV_REG_WRITE_ASM (r0, r2, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))) + + /* Init first XOR_SIZE_MASK_REG */ + MV_REG_WRITE_ASM (r1, r2, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) + + /* Update destination & size */ + MV_REG_WRITE_ASM(r0, r2, XOR_DST_PTR_REG(XOR_UNIT0,XOR_CHAN0)) + mov r6, #0xe00 + MV_REG_WRITE_ASM (r6, r2, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) + mov r6, #0xf0000 + orr r6, r6, #0xf000 + orr r6, r6, #0x1 + MV_REG_WRITE_ASM (r6, r2, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)) + + /* Configure XOR engine for memory init function. */ + MV_REG_READ_ASM (r6, r2, XOR_CONFIG_REG(XOR_UNIT0,XOR_CHAN0)) + and r6, r6, #~0x7 /* Clear operation mode field */ + orr r6, r6, #0x4 /* Set operation to memory init */ + MV_REG_WRITE_ASM(r6, r2, XOR_CONFIG_REG(XOR_UNIT0,XOR_CHAN0)) + + /* Set initVal in the XOR Engine Initial Value Registers */ + GPR_LOAD(r6, MV_32BIT_LE(0xfeedfeed)) + MV_REG_WRITE_ASM(r6, r2, XOR_INIT_VAL_LOW_REG(XOR_UNIT0)) + MV_REG_WRITE_ASM(r6, r2, XOR_INIT_VAL_HIGH_REG(XOR_UNIT0)) + + /* Set block size using DRAM bank size */ + and r6, r1, #SCSR_SIZE_MASK + mov r1, r6, LSR #SCSR_SIZE_OFFS + add r1, r1, #1 + mov r6, r5, LSL #SCSR_SIZE_OFFS + + MV_REG_WRITE_ASM(r6, r2, XOR_BLOCK_SIZE_REG(XOR_UNIT0,XOR_CHAN0)) + + /* Clean interrupt cause*/ + MV_REG_WRITE_ASM(r0, r2, XOR_CAUSE_REG(XOR_UNIT0)) + + /* Clean error interrupt cause*/ + MV_REG_READ_ASM(r6, r2, XOR_ERROR_CAUSE_REG(XOR_UNIT0)) + MV_REG_READ_ASM(r6, r2, XOR_ERROR_ADDR_REG(XOR_UNIT0)) + + /* Start transfer */ + MV_REG_READ_ASM (r6, r2, XOR_ACTIVATION_REG(XOR_UNIT0,XOR_CHAN0)) + orr r6, r6, #0x1 /* Preform start command */ + MV_REG_WRITE_ASM(r6, r2, XOR_ACTIVATION_REG(XOR_UNIT0,XOR_CHAN0)) + +.align 5 + b ncl32 +sop1: + /* Wait for engine to finish */ +waitForComplete: + MV_REG_READ_ASM(r6, r2, XOR_CAUSE_REG(XOR_UNIT0)) + and r6, r6, #2 + cmp r6, #0 + beq waitForComplete + + b cp_page_init + +#else + /* Initialize UART 0 to 115200 bps */ + GPR_LOAD(r2, 0xd0012000) + mov r1, #0x07 + strb r1, [r2, #0x8] + + mov r1, #0x83 + strb r1, [r2, #0xC] + + mov r1, #0x5A + strb r1, [r2, #0x0] + + mov r1, #0x03 + strb r1, [r2, #0xC] + + mov r1, #'N' + strb r1, [r2] + mov r1, #'A' + strb r1, [r2] + mov r1, #'N' + strb r1, [r2] + mov r1, #'D' + strb r1, [r2] + mov r1, #' ' + strb r1, [r2] + mov r1, #'b' + strb r1, [r2] + mov r1, #'o' + strb r1, [r2] + mov r1, #'o' + strb r1, [r2] + mov r1, #'t' + strb r1, [r2] + mov r1, #'s' + strb r1, [r2] + mov r1, #'t' + strb r1, [r2] + mov r1, #'r' + strb r1, [r2] + mov r1, #'a' + strb r1, [r2] + mov r1, #'p' + strb r1, [r2] + mov r1, #10 + strb r1, [r2] + mov r1, #13 + strb r1, [r2] + +#endif +.align 5 +ncl32: + b ncl33 +cp_page_init: + /* init */ + mov r2, #0x3 /* start with page 3 */ + mov r3, #0x20000 + orr r3, r3, #0x600 + b cp_page_loop + +.align 5 +ncl33: + b ncl31 + +cp_page_loop: + mov r0, #0 + mov r6, #CMD_READ + mov r9, #CMD_STATUS + mov r4, #PAGE_SIZE /* Byte counter */ + b startRead + +.align 5 +ncl31: + b ncl3 +startRead: + /* issue read command */ + strb r6, [r5, #NAND_CMD_PORT] + + /* issue address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r2, [r5, #NAND_ADDR_PORT] /* page address */ + strb r0, [r5, #NAND_ADDR_PORT] + + /* Check status */ + strb r9, [r5, #NAND_CMD_PORT] + b busy_loop1 + +.align 5 +ncl3: + b ncl4 + +busy_loop1: + ldrb r1, [r5] + tst r1, #STATUS_READY + beq busy_loop1 + + /* back to read mode */ + strb r6, [r5, #NAND_CMD_PORT] + + /* now perform reading */ + mov r0, r5 + b copy_loop1 + +.align 5 +ncl4: + b ncl5 + +copy_loop1: + sub r4, r4, #32 /* 8 dwords * 4 bytes */ + ldmia r0!, {r6-r13} + stmia r3!, {r6-r13} + + cmp r4, #0 /* check if we have read a full Page */ + bne copy_loop1 + b nextPage + +.align 5 +ncl5: + b ncl6 + +nextPage: + add r2, r2, #1 /* increment page number */ + cmp r2, #BOOTER_PAGE_NUM + bne cp_page_loop + b stack_setup + +.align 5 +ncl6: + b sop1 + + + /* Set up the stack */ +stack_setup: + sub sp, lr, #40 /* leave 3 words for abort-stack */ + + /* jump to new code */ + mov pc, lr + + +.align 9 + +/* This is known to be address (BOOTER_BASE + 2 * PAGE_SIZE) */ +_nandBootPtr: + .word nand_boot + +#else /* MV_BOOTROM */ + +.globl nbootStart +nbootStart: + /* Enable I-Cache */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Set up the stack */ + mov r0, #BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + + /* jump to new code */ + + ldr lr, =nand_boot + mov pc, lr +#endif /* !defined(MV_BOOTROM) */ diff --git a/board/mv_feroceon/mv_dd/nBootstrap.h b/board/mv_feroceon/mv_dd/nBootstrap.h new file mode 100644 index 0000000..e26a331 --- /dev/null +++ b/board/mv_feroceon/mv_dd/nBootstrap.h @@ -0,0 +1,279 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCnBootstraph +#define __INCnBootstraph + +/* includes */ + +/* defines */ + +#if defined(RD_MV78XX0_AMC) +/* On board DDR2 512MB 333MHz */ +#define SDRAM_CONFIG_REG_DV 0x43008a25 /* 1400 */ +#define SDRAM_DUNIT_CTRL_REG_DV 0x38543000 /* 1404 */ +#define SDRAM_TIMING_CTRL_LOW_REG_DVAL 0x2202444e /* 1408 */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DVAL 0x00000A22 /* 140C */ +#define SDRAM_ADDR_CTRL_REG_DV 0x000000DD /* 1410 */ +#define SDRAM_MODE_REG_DV 0x00000652 /* 141C */ +#define SDRAM_EXTENDED_MODE_REG_DV 0x00000040 /* 1420 */ +#define SDRAM_DUNIT_CTRL_HI_REG_DV 0x0000ff7f /* 1424*/ +#define SDRAM_DDR2_TIMING_LO_REG_DV 0x00085520 /* 1428 */ +#define SDRAM_DDR2_TIMING_HI_REG_DV 0x00008552 /* 147C */ +#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x84210000 /* 1494 */ +#define DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV 0x00000000 /* 1498 */ +#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x0000EB0F /* 149C */ +#define SDRAM_SIZE_REG_DV 0x1ffffff1 /* 1504 */ + +#elif defined(RD_MV78XX0_H3C) +/* On board DDR2 512MB 333MHz + ECC */ +#define SDRAM_CONFIG_REG_DV 0x43048a25 /* 1400 */ +#define SDRAM_DUNIT_CTRL_REG_DV 0x38543000 /* 1404 */ +#define SDRAM_TIMING_CTRL_LOW_REG_DVAL 0x2202444e /* 1408 */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DVAL 0x00000A22 /* 140C */ +#define SDRAM_ADDR_CTRL_REG_DV 0x00000088 /* 1410 */ +#define SDRAM_MODE_REG_DV 0x00000652 /* 141C */ +#define SDRAM_EXTENDED_MODE_REG_DV 0x00000040 /* 1420 */ +#define SDRAM_DDR2_TIMING_LO_REG_DV 0x00085520 /* 1428 */ +#define SDRAM_DDR2_TIMING_HI_REG_DV 0x00008552 /* 147C */ +#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x84210000 /* 1494 */ +#define DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV 0x00000000 /* 1498 */ +#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x0000EB0F /* 149C */ +#define SDRAM_SIZE_REG_DV 0x1ffffff1 /* 1504 */ + +#elif defined(RD_MV78XX0_MASA) + +/* Single/Dual DDR2 boards 512MB 400MHz */ +#define SDRAM_CONFIG_REG_DV 0x43088a25 /* 1400 */ +#ifdef RD_MV78XX0_MASA_2DIMM +#define SDRAM_DUNIT_CTRL_REG_DV 0x38543010 /* 1404 */ +#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x003c003c /* 1494 */ +#define SDRAM_EXTENDED_MODE_REG_DV 0x00000044 /* 1420 */ +#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x0000EC0F /* 149C */ +#else +#define SDRAM_DUNIT_CTRL_REG_DV 0x38543000 /* 1404 */ +#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x84210000 /* 1494 */ +#define SDRAM_EXTENDED_MODE_REG_DV 0x00000040 /* 1420 */ +#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x0000E80F /* 149C */ +#endif +#define SDRAM_TIMING_CTRL_LOW_REG_DVAL 0x2203444E /* 1408 */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DVAL 0x00000A2A /* 140C */ +#define SDRAM_ADDR_CTRL_REG_DV 0x000000DD /* 1410 */ +#define SDRAM_MODE_REG_DV 0x00000652 /* 141C */ +#define SDRAM_DDR2_TIMING_LO_REG_DV 0x00085520 /* 1428 */ +#define SDRAM_DDR2_TIMING_HI_REG_DV 0x00008552 /* 147C */ +#define DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV 0x00000000 /* 1498 */ +#define SDRAM_SIZE_REG_DV 0x1ffffff1 /* 1504 */ +#define SDRAM_BASE1_REG_DV 0x20000000 /* 1508 */ + +#elif defined(DB_MV88F632X) + +/* On board DDR2 512MB 333MHz 32 bit*/ +#define SDRAM_CONFIG_REG_DV 0x43000a25 /* 1400 */ +#define SDRAM_DUNIT_CTRL_REG_DV 0x37543000 /* 1404 */ +#define SDRAM_TIMING_CTRL_LOW_REG_DVAL 0x2202433e /* 1408 */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DVAL 0x00000a22 /* 140C */ +#define SDRAM_ADDR_CTRL_REG_DV 0x00000088 /* 1410 */ +#define SDRAM_MODE_REG_DV 0x00000652 /* 141C */ +#define SDRAM_EXTENDED_MODE_REG_DV 0x00000040 /* 1420 */ +#define SDRAM_DUNIT_CTRL_HI_REG_DV 0x0000ff7f /* 1424*/ +#define SDRAM_DDR2_TIMING_LO_REG_DV 0x00085520 /* 1428 */ +#define SDRAM_DDR2_TIMING_HI_REG_DV 0x00000003 /* 147C */ +#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x84210000 /* 1494 */ +#define DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV 0x00000000 /* 1498 */ +#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x0000E80F /* 149C */ +#define SDRAM_SIZE_REG_DV 0xffffff1 /* 1504 */ + +#elif defined(DB_MV78XX0) ||defined(DB_MV78200) +/* On board DDR2 512MB 333MHz */ +#define SDRAM_CONFIG_REG_DV 0x43008c30 /* 1400 */ +#define SDRAM_DUNIT_CTRL_REG_DV 0x37543000 /* 1404 */ +#define SDRAM_TIMING_CTRL_LOW_REG_DVAL 0x22125441 /* 1408 */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DVAL 0x00000a29 /* 140C */ +#define SDRAM_ADDR_CTRL_REG_DV 0x00000088 /* 1410 */ +#define SDRAM_MODE_REG_DV 0x00000652 /* 141C */ +#define SDRAM_EXTENDED_MODE_REG_DV 0x00000040 /* 1420 */ +#define SDRAM_DUNIT_CTRL_HI_REG_DV 0x0000ff7f /* 1424*/ +#define SDRAM_DDR2_TIMING_LO_REG_DV 0x00085520 /* 1428 */ +#define SDRAM_DDR2_TIMING_HI_REG_DV 0x00008552 /* 147C */ +#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x84210000 /* 1494 */ +#define DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV 0x00000000 /* 1498 */ +#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x0000E80F /* 149C */ +#define SDRAM_SIZE_REG_DV 0x1ffffff1 /* 1504 */ +#endif + +/* NAND Flash access */ +#define NAND_CMD_PORT (0x1 << (NFLASH_DEV_WIDTH >> 4)) +#define NAND_ADDR_PORT (0x2 << (NFLASH_DEV_WIDTH >> 4)) + +/* NAND Flash Chip Capability */ +#ifdef MV_LARGE_PAGE +#define NUM_BLOCKS 2048 +#define PAGES_PER_BLOCK 64 +#define PAGE_SIZE 2048 /* Bytes */ +#define SPARE_SIZE 64 +#define CFG_NAND_PAGE_SIZE (2048) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (64) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (0) /* Location of bad block marker */ + +#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ + +#else /* ! LARGE PAGE NAND */ +/* NAND Flash Chip Capability */ +#define NUM_BLOCKS 2048 +#define PAGES_PER_BLOCK 32 +#define PAGE_SIZE 512 /* Bytes */ +#define SPARE_SIZE 16 +#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */ + +#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ + +#endif + +/* NAND Flash Command. This appears to be generic across all NAND flash chips */ +#define CMD_READ 0x00 /* Read */ +#define CMD_READ1 0x01 /* Read1 */ +#define CMD_READ2 0x50 /* Read2 */ +#define CMD_START_READ 0x30 /* Read command after write addr */ +#define CMD_READID 0x90 /* ReadID */ +#define CMD_READID2 0x91 /* Read extended ID */ +#define CMD_WRITE 0x80 /* Write phase 1 */ +#define CMD_WRITE2 0x10 /* Write phase 2 */ +#define CMD_ERASE 0x60 /* Erase phase 1 */ +#define CMD_ERASE2 0xd0 /* Erase phase 2 */ +#define CMD_STATUS 0x70 /* Status read */ +#define CMD_RESET 0xff /* Reset */ + +/* Status bit pattern */ +#define STATUS_READY 0x40 /* Ready */ +#define STATUS_ERROR 0x01 /* Error */ + + +#define NFLASH_DEV_WIDTH 8 +#ifdef MV_LARGE_PAGE +#define BOOTER_PAGE_NUM 2 +#define BOOTER_BASE 0x00020000 + PAGE_SIZE +#else +#define BOOTER_PAGE_NUM 5 +#define BOOTER_BASE 0x00020000 + (3 * PAGE_SIZE) +#endif /* MV_LARGE_PAGE */ +#define BOOTER_END (BOOTER_BASE + (BOOTER_PAGE_NUM * PAGE_SIZE)) + +#undef INTER_REGS_BASE +#define INTER_REGS_BASE 0xd0000000 +#define NAND_FLASH_BASE 0xffff0000 + +#define NBOOT_UART_CHAN 0 +#define NBOOT_BAUDRATE 115200 +#define NBOOT_TIMER_NUM 0 + + +/* CPU config register (0x20100) bit[15:8] value for CPU to DDR clock ratio */ +#define CPU_2_MBUSL_DDR_CLK 0x0000 /* clock ratio 1x2 */ +/* #define CPU_2_MBUSL_DDR_CLK 0x2100 *//* clock ratio 1x3 */ +/* #define CPU_2_MBUSL_DDR_CLK 0x2200 *//* clock ratio 1x4 */ + +/* Load General Purpose Register (GPR) with 32-bit constant value */ +#define GPR_LOAD(reg, val) \ + mov reg, $(val & 0xFF) ;\ + orr reg, reg, $(val & 0xFF00) ;\ + orr reg, reg, $(val & 0xFF0000) ;\ + orr reg, reg, $(val & 0xFF000000) + +/* Register Read/Write */ +#define MV_REG_READ_ASM(toReg, baseReg, regOffs) \ + ldr toReg, [baseReg, $(regOffs & 0xFFF)] + +#define MV_REG_WRITE_ASM(fromReg, baseReg, regOffs) \ + str fromReg, [baseReg, $(regOffs & 0xFFF)] + + +/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ +#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ + (((X)&0xff00)<<8) | \ + (((X)&0xff0000)>>8) | \ + (((X)&0xff000000)>>24)) +/* Endianess macros. */ +#if defined(MV_CPU_LE) + #define MV_32BIT_LE(X) (X) + #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) +#elif defined(MV_CPU_BE) + #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) + #define MV_32BIT_BE(X) (X) +#else + #error "CPU endianess isn't defined!\n" +#endif + +#endif /* __INCnBootstraph */ diff --git a/board/mv_feroceon/mv_dd/nBootstrap_LP.S b/board/mv_feroceon/mv_dd/nBootstrap_LP.S new file mode 100644 index 0000000..b82af69 --- /dev/null +++ b/board/mv_feroceon/mv_dd/nBootstrap_LP.S @@ -0,0 +1,272 @@ +#define MV_ASMLANGUAGE +#include "ddr2/mvDramIfRegs.h" +#include "ddr2/mvDramIfConfig.h" +#include "nBootstrap.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + + +/* #define NAND_DEBUG */ +#if !defined(MV_BOOTROM) +.globl nbootStart +nbootStart: + /* + * set the cpu to SVC32 mode, I and F disabled. + */ + mov r1, #0xd3 + msr cpsr,r1 + + /* + * flush v4 I/D caches + */ + mcr p15, 0, r1, c7, c7, 0 /* invalidate v3/v4 cache */ + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r1, c1, c0, 0 + bic r1, r1, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r1, r1, #0x00000007 /* clear bits 2:0 (-CAM) */ + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Add nop commands for cache flush operations */ + nop + nop + nop + nop + nop + /* here. MUST BE IN THE SAME CACHE LINE */ + + mov r0, #0 /* We use r0 as always '0' */ + + /* lock I-Cache */ + mrc p15, 0, r8, c9, c0, 1 + orr r8, r8, #0xf + mcr p15, 0, r8, c9, c0, 1 + + /* Start load code into I-Cache */ + mov r2, #0x500 + mov r8, pc +.align 5 + bic r8, #0x1f + add r8, r8, #32 +load_loop: + mcr p15, 0, r8, c7, c13, 1 + add r8, r8, #32 /* 8 dwords * 4 bytes */ + sub r2, r2, #32 /* 8 dwords * 4 bytes */ + cmp r2, #0 /* check if we have read a full Page */ + bne load_loop + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0xf0ffffff + MV_REG_WRITE_ASM(r1, r2, 0x104) + mov r1, #0x1000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + + /* DRAM memory initialization */ + /* Load SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + /* Write to SDRAM coniguration register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_CONFIG_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_CONFIG_REG) + + /* Write Dunit control low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_DUNIT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_DUNIT_CTRL_REG) + + /* Write SDRAM address control register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_ADDR_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_ADDR_CTRL_REG) + + /* Write SDRAM timing Low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_LOW_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_LOW_REG) + + /* Write SDRAM timing High register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_HIGH_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_HIGH_REG) + + /* Write SDRAM mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_MODE_REG) + + /* Write SDRAM Extended mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_EXTENDED_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_EXTENDED_MODE_REG) + + /* Config DDR2 On Die Termination (ODT) registers */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_LOW_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_LOW_REG) + + /* Write SDRAM DDR2 ODT control high register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + + /* Write SDRAM DDR2 Dunit ODT control register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_DUNIT_ODT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_DUNIT_ODT_CONTROL_REG) + + mov r3, #MV_32BIT_LE(DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV) + mov r4, #MV_32BIT_LE(DDR2_DATA_PAD_STRENGTH_TYPICAL_DV) + b next + +next: + /* DDR SDRAM Initialization Control Register. Init enable */ + mov r1, #MV_32BIT_LE(DSICR_INIT_EN) + MV_REG_WRITE_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x2000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + +ddrInitLoop: + MV_REG_READ_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + cmp r1, #0 + bne ddrInitLoop + + /* Load back SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + /* Open SDRAM bank 0 size register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_SIZE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_SIZE_REG(0,0)) + + /* Close SDRAM bank 1,2,3 */ + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(0,1)) + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(0,2)) + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(0,3)) + + /* Prepare the address where to find the nandBoot function pointer */ + mov lr, #BOOTER_BASE + add lr, lr, #0x20 + +#ifdef DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x2000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + + /* init */ + mov r2, #0x1 /* start with page 1 */ + mov r3, #BOOTER_BASE /* start of DRAM buffer */ + GPR_LOAD(r5, NAND_FLASH_BASE) + +cp_page_loop: + mov r0, #0 + mov r6, #CMD_READ + mov r7, #CMD_START_READ + mov r9, #CMD_RESET + mov r4, #PAGE_SIZE /* Byte counter */ + + +startRead: + /* issue reset command */ + strb r9, [r5, #NAND_CMD_PORT] + + mov r9, #0x1000000 +loop_delay1: + sub r9, r9, #1 + cmp r9, #0 + bne loop_delay1 + + /* issue read command */ + strb r6, [r5, #NAND_CMD_PORT] + + /* issue address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r0, [r5, #NAND_ADDR_PORT] + strb r2, [r5, #NAND_ADDR_PORT] /* page address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r0, [r5, #NAND_ADDR_PORT] + strb r7, [r5, #NAND_CMD_PORT] + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r6, #0xd0000000 + orr r6, r6, #0x10000 + mov r1, #0x3000000 + MV_REG_WRITE_ASM(r1, r6, 0x100) +#endif + /* Delay of at least 25uSec (NAND flash tR) */ + mov r9, #0x1000000 +loop_delay3: + sub r9, r9, #1 + cmp r9, #0 + bne loop_delay3 + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r6, #0xd0000000 + orr r6, r6, #0x10000 + mov r1, #0x4000000 + MV_REG_WRITE_ASM(r1, r6, 0x100) +#endif + + /* now perform reading */ + mov r0, r5 + +copy_loop1: + sub r4, r4, #16 /* 4 dwords * 4 bytes */ + ldmia r0!, {r6-r9} + stmia r3!, {r6-r9} + + cmp r4, #0 /* check if we have read a full Page */ + bne copy_loop1 + +nextPage: + add r2, r2, #1 /* increment page number */ + cmp r2, #BOOTER_PAGE_NUM + bne cp_page_loop + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x5000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + + /* Set up the stack */ +stack_setup: + mov r0, #BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + /* jump to new code */ + mov pc, lr + +.align 10 +/* This is known to be address (BOOTER_BASE + 2 * PAGE_SIZE) */ +_nandBootPtr: + .word nand_boot + +#else /* MV_BOOTROM */ + +.globl nbootStart +nbootStart: + /* Enable I-Cache */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Set up the stack */ + mov r0, #BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + + /* jump to new code */ + + ldr lr, =nandBoot + mov pc, lr +#endif /* !defined(MV_BOOTROM) */ diff --git a/board/mv_feroceon/mv_dd/platform.S b/board/mv_feroceon/mv_dd/platform.S new file mode 100644 index 0000000..92b00da --- /dev/null +++ b/board/mv_feroceon/mv_dd/platform.S @@ -0,0 +1,178 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include +#include +#include "mvBoardEnvSpec.h" +#include "mvCtrlEnvSpec.h" +#include "mvCpuIfConfig.h" +#include "pci/mvPciRegs.h" +#include "pex/mvPexRegs.h" +#include "ddr2/mvDramIfRegs.h" +#include "mvCtrlEnvAsm.h" +#include "mvAhbToMbusRegs.h" +#if defined(MV_INC_BOARD_SPI_FLASH) +#include "spi/mvSpiSpec.h" +#endif + +.globl lowlevel_init + +/************************************************/ +/* lowlevel_init * +/************************************************/ + +lowlevel_init: + mov r2, lr +#if defined(MV78200) + mov r0, #0 + mrc p15, 1, r0, c15, c1, 0 + /* Check if we are CPU0 or CPU1 */ + and r0, r0, #0x4000 + cmp r0, #0x4000 + bne cpu0_reg_offset + b done_cpu1 +#endif + + /* change CPU0 reg base to 0xf1000000 */ +cpu0_reg_offset: + ldr r4, =CFG_MV_REGS + MV_DV_REG_WRITE_ASM(r4, r1, (AHB_TO_MBUS_WIN_INTEREG_REG(0))) + ldr r4, =CFG_MV_REGS + MV_REG_WRITE_ASM (r4, r1, (AHB_TO_MBUS_WIN_INTEREG_REG(1))) + +#if defined(MV_INC_BOARD_SPI_FLASH) + /* configure the Prescale of SPI clk Tclk = 200MHz */ + MV_REG_READ_ASM (r6, r1, MV_SPI_IF_CONFIG_REG) + and r6, r6, #~MV_SPI_CLK_PRESCALE_MASK + orr r6, r6, #0x15 + orr r6, r6, #0x4000 + MV_REG_WRITE_ASM (r6, r1, MV_SPI_IF_CONFIG_REG) +#endif +#if 0 + /* Set CPU_2_AHB_TICK_DRV and CCR_CPU_2_AHB_TICK_SMPL tiks */ + MV_REG_READ_ASM (r6, r1, CPU_RESET_SAMPLE_L_REG) + and r6, r6 , #MSAR_SYSCLK2CPU_MASK0 + mov r6, r6, LSR #MSAR_SYSCLK2CPU_OFFS0 + ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (0 << CCR_CPU_2_AHB_TICK_DRV_OFFS)) + cmp r6, #0x2 + beq set_cpu_config + ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (1 << CCR_CPU_2_AHB_TICK_DRV_OFFS)) + cmp r6, #0x4 + beq set_cpu_config + ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (2 << CCR_CPU_2_AHB_TICK_DRV_OFFS)) + cmp r6, #0x6 + beq set_cpu_config + ldr r4, =0 +set_cpu_config: + /* Don't change R4 !!! use for Second CPU as well */ + MV_REG_READ_ASM (r6, r1, CPU_CONFIG_REG(MASTER_CPU)) + orr r6, r6, r4 + MV_REG_WRITE_ASM (r6, r1, CPU_CONFIG_REG(MASTER_CPU)) + + + MV_REG_READ_ASM (r6, r1, CPU_RESET_SAMPLE_L_REG) + and r6, r6 , #MSAR_SYSCLK2CPU_MASK1 + mov r6, r6, LSR #MSAR_SYSCLK2CPU_OFFS1 + ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (0 << CCR_CPU_2_AHB_TICK_DRV_OFFS)) + cmp r6, #0x2 + beq set_cpu1_config + ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (1 << CCR_CPU_2_AHB_TICK_DRV_OFFS)) + cmp r6, #0x4 + beq set_cpu1_config + ldr r4, = ((1 << CCR_CPU_2_AHB_TICK_SMPL_OFFS) | (2 << CCR_CPU_2_AHB_TICK_DRV_OFFS)) + cmp r6, #0x6 + beq set_cpu1_config + ldr r4, =0 +set_cpu1_config: + MV_REG_READ_ASM (r6, r1, CPU_CONFIG_REG(SLAVE_CPU)) + orr r6, r6, r4 + MV_REG_WRITE_ASM (r6, r1, CPU_CONFIG_REG(SLAVE_CPU)) +#endif + + /* init MPP */ + ldr r6, =DB_78XX0_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_78XX0_MPP8_15 + /* Clear SATA_ACT for load indication */ + and r6, r6 ,#0xffffff + MV_REG_WRITE_ASM (r6, r1, 0x10004) +#if defined(DB_MV78XX0) && defined(MV_NAND_BOOT) + ldr r6, =DB_78XX0_MPP16_23_NAND +#else + ldr r6, =DB_78XX0_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10008) +#endif + /* init GPP , Out enable */ + MV_REG_READ_ASM(r6, r1, 0x10104); + bic r6, #(0x3 << 14) + MV_REG_WRITE_ASM(r6, r1, 0x10104); + ldr r6, =(0x1 << 15) + MV_REG_WRITE_ASM(r6, r1, 0x10120); + ldr r6, =(0x1 << 14) + MV_REG_WRITE_ASM(r6, r1, 0x10124); + +#if defined(RD_MV78XX0_AMC) + /* init MPP */ + ldr r6, =RD_AMC_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_AMC_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =RD_AMC_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10008) + /* init GPP , Out enable */ +#endif + +#if defined(RD_MV78XX0_MASA) + /* init MPP */ + ldr r6, =RD_MASA_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_MASA_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =RD_MASA_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10008) + /* init GPP , Out enable, blink */ + ldr r6, = (1 << RD_MASA_LED_GPP_PIN(0)); + MV_REG_WRITE_ASM(r6, r1, 0x10108); + MV_REG_WRITE_ASM(r6, r1, 0x10128); + MV_REG_WRITE_ASM(r6, r1, 0x10124); +#endif + +#if defined(MV_STATIC_DRAM_ON_BOARD) + + bl _mvDramIfStaticInit +#else + bl _mvDramIfBasicInit + + /* SATA LEDs */ + ldr r6, =(0x1 << 14) + MV_REG_WRITE_ASM(r6, r1, 0x10120); + ldr r6, =(0x1 << 15) + MV_REG_WRITE_ASM(r6, r1, 0x10124); +#endif + + +done: + + mov lr, r2 +done_cpu1: + mov pc, lr + diff --git a/board/mv_feroceon/mv_hal/audio/dac/mvCLAudioCodec.c b/board/mv_feroceon/mv_hal/audio/dac/mvCLAudioCodec.c new file mode 100644 index 0000000..fad52d7 --- /dev/null +++ b/board/mv_feroceon/mv_hal/audio/dac/mvCLAudioCodec.c @@ -0,0 +1,500 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCLAudioCodec.h" +#include "mvCLAudioCodecRegs.h" + +/******************************************************************************* +* mvCLAudioCodecInit - Initizlize the Cirrus Logic device +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* OUTPUT: +* None +* RETURN: +* MV_TRUE or MV_FALSE. +* +*******************************************************************************/ +MV_BOOL mvCLAudioCodecInit(MV_AUDIO_CODEC_DEV *pCodecDev) +{ + MV_U8 nData; + + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return MV_FALSE; + } + + /* Verify chip ID and revision */ + nData = mvCLAudioCodecRegGet(pCodecDev,CL_AUDIO_CODEC_ID_REG); + if((MV_CL_AUDIO_CODEC_CHIP_ID != (nData >> 3)) || + (MV_CL_AUDIO_CODEC_REV_ID != (nData & 0x7))) + { + mvOsPrintf("%s: Error - Invalid Cirrus Logic chip/rev ID!\n",__FUNCTION__); + return MV_FALSE; + } + + /* Set the digital Interface format */ + nData = mvCLAudioCodecRegGet(pCodecDev,CL_AUDIO_CODEC_IF_CTRL_REG); + nData &= ~(0x7<<3); + nData |= (pCodecDev->DACDigitalIFFormat << 3); + mvCLAudioCodecRegSet(pCodecDev,CL_AUDIO_CODEC_IF_CTRL_REG,nData); + + /* Set the ADC Mode */ + if(MV_LEFT_JUSTIFIED_MODE == pCodecDev->ADCMode) + mvCLAudioCodecRegBitsReset(pCodecDev,CL_AUDIO_CODEC_IF_CTRL_REG,BIT2); + else + mvCLAudioCodecRegBitsSet(pCodecDev,CL_AUDIO_CODEC_IF_CTRL_REG,BIT2); + + + return MV_TRUE; +} + +/******************************************************************************* +* mvCLAudioCodecOutputVolumeSet - Set the Cirrus Logic output volume of OUTA +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* nVolume : Volume level. +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvCLAudioCodecOutputVolumeSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_8 nVolume) +{ + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return; + } + mvCLAudioCodecRegSet(pCodecDev,CL_AUDIO_CODEC_VOL_OUTA_CTRL_REG,nVolume); +} + +/******************************************************************************* +* mvCLAudioCodecOutputVolumeGet - Get the Cirrus Logic output volume of OUTA +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* OUTPUT: +* None +* RETURN: +* Volume level. +* +*******************************************************************************/ +MV_U8 mvCLAudioCodecOutputVolumeGet(MV_AUDIO_CODEC_DEV *pCodecDev) +{ + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return 0; + } + return mvCLAudioCodecRegGet(pCodecDev,CL_AUDIO_CODEC_VOL_OUTA_CTRL_REG); +} + +/******************************************************************************* +* mvCLAudioCodecOutputVolumeMute - Mute the Cirrus Logic output volume of OUTA +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* bMute : MV_TRUE for mute, MV_FALSE to un-mute +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvCLAudioCodecOutputVolumeMute(MV_AUDIO_CODEC_DEV *pCodecDev, MV_BOOL bMute) +{ + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return; + } + if(MV_TRUE == bMute) + mvCLAudioCodecRegBitsSet(pCodecDev,CL_AUDIO_CODEC_DAC_OUTPUT_CTRL_REG,BIT0); + else + mvCLAudioCodecRegBitsReset(pCodecDev,CL_AUDIO_CODEC_DAC_OUTPUT_CTRL_REG,BIT0); +} + +/******************************************************************************* +* mvCLAudioCodecInputVolumeSet - Set the Cirrus Logic input volume of INA +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* nVolume : Volume level. +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvCLAudioCodecInputVolumeSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_8 nVolume) +{ + MV_U8 nData; + + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return; + } + nData = mvCLAudioCodecRegGet(pCodecDev,CL_AUDIO_CODEC_PGAA_VOL_CTRL_REG); + nData &= ~0x1f; + nData |= (0x1f & nVolume); + mvCLAudioCodecRegSet(pCodecDev,CL_AUDIO_CODEC_PGAA_VOL_CTRL_REG,nData); +} + +/******************************************************************************* +* mvCLAudioCodecInputVolumeGet - Get the Cirrus Logic input volume of INA +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* OUTPUT: +* None +* RETURN: +* Volume level. +* +*******************************************************************************/ +MV_U8 mvCLAudioCodecInputVolumeGet(MV_AUDIO_CODEC_DEV *pCodecDev) +{ + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return 0; + } + return mvCLAudioCodecRegGet(pCodecDev,CL_AUDIO_CODEC_PGAA_VOL_CTRL_REG) & 0x1f; +} + +/******************************************************************************* +* mvCLAudioCodecInputVolumeMute - Mute the Cirrus Logic input volume of INA +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* bMute : MV_TRUE for mute, MV_FALSE to un-mute +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvCLAudioCodecInputVolumeMute(MV_AUDIO_CODEC_DEV *pCodecDev, + MV_BOOL bMute) +{ + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return; + } + if(MV_TRUE == bMute) + mvCLAudioCodecRegBitsSet(pCodecDev,CL_AUDIO_CODEC_ADC_INPUT_INV_MUTE_REG, + BIT0); + else + mvCLAudioCodecRegBitsReset(pCodecDev,CL_AUDIO_CODEC_ADC_INPUT_INV_MUTE_REG, + BIT0); +} + +/******************************************************************************* +* mvCLAudioCodecTrebleSet - Set the Cirrus Logic output treble of INA +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* nTreble : treble value. +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvCLAudioCodecTrebleSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_8 nTreble) +{ + MV_U8 nData; + + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return; + } + nData = mvCLAudioCodecRegGet(pCodecDev,CL_AUDIO_CODEC_TONE_CTRL_REG); + nData &= 0xF; + nData |= (nTreble<<4); + mvCLAudioCodecRegSet(pCodecDev,CL_AUDIO_CODEC_TONE_CTRL_REG,nData); +} + +/******************************************************************************* +* mvCLAudioCodecTrebleGet - Get the Cirrus Logic output treble of INA +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* OUTPUT: +* None +* RETURN: +* treble value +* +*******************************************************************************/ +MV_U8 mvCLAudioCodecTrebleGet(MV_AUDIO_CODEC_DEV *pCodecDev) +{ + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return 0; + } + return mvCLAudioCodecRegGet(pCodecDev,CL_AUDIO_CODEC_TONE_CTRL_REG)>>4; +} +/******************************************************************************* +* mvCLAudioCodecBassSet - Set the Cirrus Logic output bass of INA +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* nBass : Bass level. +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvCLAudioCodecBassSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_8 nBass) +{ + MV_U8 nData; + + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return; + } + nData = mvCLAudioCodecRegGet(pCodecDev,CL_AUDIO_CODEC_TONE_CTRL_REG); + nData &= 0xf0; + nData |= nBass; + mvCLAudioCodecRegSet(pCodecDev,CL_AUDIO_CODEC_TONE_CTRL_REG,nData); +} + +/******************************************************************************* +* mvCLAudioCodecBassGet - Get the Cirrus Logic output bass of INA +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* OUTPUT: +* None +* RETURN: +* Bass level +* +*******************************************************************************/ +MV_U8 mvCLAudioCodecBassGet(MV_AUDIO_CODEC_DEV *pCodecDev) +{ + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return 0; + } + return mvCLAudioCodecRegGet(pCodecDev,CL_AUDIO_CODEC_TONE_CTRL_REG)& 0xF; +} + +/******************************************************************************* +* mvCLAudioCodecRegSet - Set Cirrus Logic register value +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* nOffset : register offset +* nData : register data +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvCLAudioCodecRegSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_U8 nOffset, + MV_U8 nData) +{ + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return; + } + pCodecDev->twsiSlave.offset = nOffset; + if(mvTwsiWrite(MV_BOARD_DIMM_I2C_CHANNEL,&pCodecDev->twsiSlave,&nData,1) != MV_OK) + { + mvOsPrintf("%s: Error while writing register!\n",__FUNCTION__); + return; + } +} + +/******************************************************************************* +* mvCLAudioCodecRegGet - Set Cirrus Logic register value +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* nOffset : register offset +* OUTPUT: +* None +* RETURN: +* register data +* +*******************************************************************************/ +MV_U8 mvCLAudioCodecRegGet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_U8 nOffset) +{ + MV_U8 nData; + + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return 0; + } + pCodecDev->twsiSlave.offset = nOffset; + if(mvTwsiRead(MV_BOARD_DIMM_I2C_CHANNEL,&pCodecDev->twsiSlave,&nData,1) != MV_OK) + { + mvOsPrintf("%s: Error while reading register!\n",__FUNCTION__); + return 0; + } + return nData; +} + +/******************************************************************************* +* mvCLAudioCodecRegBitsSet - Set Cirrus Logic register bits value +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* nOffset : register offset +* nBits : register bits +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvCLAudioCodecRegBitsSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_U8 nOffset, + MV_U8 nBits) +{ + MV_U8 nData; + + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return; + } + + pCodecDev->twsiSlave.offset = nOffset; + nData = mvCLAudioCodecRegGet(pCodecDev,nOffset); + nData |= nBits; + mvCLAudioCodecRegSet(pCodecDev,nOffset,nData); + +} + +/******************************************************************************* +* mvCLAudioCodecRegGet - Reset Cirrus Logic register bits value +* +* DESCRIPTION: +* +* INPUT: +* pCodecDev: pointer to MV_AUDIO_CODEC_DEV structure. +* nOffset : register offset +* nBits : register bits +* OUTPUT: +* None +* RETURN: +* register data +* +*******************************************************************************/ +MV_VOID mvCLAudioCodecRegBitsReset(MV_AUDIO_CODEC_DEV *pCodecDev, MV_U8 nOffset, MV_U8 nBits) +{ + MV_U8 nData; + + if(NULL == pCodecDev) + { + mvOsPrintf("%s: Error - pCodecDev = NULL!\n",__FUNCTION__); + return; + } + + pCodecDev->twsiSlave.offset = nOffset; + nData = mvCLAudioCodecRegGet(pCodecDev,nOffset); + nData &= ~nBits; + mvCLAudioCodecRegSet(pCodecDev,nOffset,nData); +} diff --git a/board/mv_feroceon/mv_hal/audio/dac/mvCLAudioCodec.h b/board/mv_feroceon/mv_hal/audio/dac/mvCLAudioCodec.h new file mode 100644 index 0000000..74b3c72 --- /dev/null +++ b/board/mv_feroceon/mv_hal/audio/dac/mvCLAudioCodec.h @@ -0,0 +1,139 @@ + +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCLAudioCodech +#define __INCmvCLAudioCodech + +#include "mvTypes.h" +#include "twsi/mvTwsi.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvSpec.h" + +#define MV_CL_AUDIO_CODEC_CHIP_ID 0x1B +#define MV_CL_AUDIO_CODEC_REV_ID 0x1 + +/* Selects the digital interface format used for the data in on SDIN. */ +typedef enum _mvDACDigitalIFFormat +{ + MV_L_JUSTIFIED_UP_TO_24_BIT, + MV_I2S_UP_TO_24_BIT, + MV_R_JUSTIFIED_UP_TO_24_BIT, + MV_R_JUSTIFIED_20_BIT, + MV_R_JUSTIFIED_18_BIT, + MV_R_JUSTIFIED_16_BIT + +} MV_DAC_DIGITAL_IF_FORMAT; + +/* Selects either the I2S or Left-Justified digital interface format for the + data on SDOUT. */ +typedef enum _mvADCMode +{ + MV_LEFT_JUSTIFIED_MODE, + MV_I2S_MODE +} MV_ADC_MODE; + + +/* Cirrus Logic device structure */ +typedef struct _mvAudioCodecDev +{ + /* MUST be set by user!!! */ + MV_TWSI_SLAVE twsiSlave; + MV_DAC_DIGITAL_IF_FORMAT DACDigitalIFFormat; + MV_ADC_MODE ADCMode; + + /* Set by driver */ + MV_U8 nChipID; + MV_U8 nRevID; + +} MV_AUDIO_CODEC_DEV; + +/* Initialize the Cirrus Logic device */ +MV_BOOL mvCLAudioCodecInit(MV_AUDIO_CODEC_DEV *pCodecDev); + +/* Function to control output volume (playback) */ +MV_VOID mvCLAudioCodecOutputVolumeSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_8 nVolume); +MV_U8 mvCLAudioCodecOutputVolumeGet(MV_AUDIO_CODEC_DEV *pCodecDev); +MV_VOID mvCLAudioCodecOutputVolumeMute(MV_AUDIO_CODEC_DEV *pCodecDev, MV_BOOL bMute); + +/* Function to control input volume (record) */ +MV_VOID mvCLAudioCodecInputVolumeSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_8 nVolume); +MV_U8 mvCLAudioCodecInputVolumeGet(MV_AUDIO_CODEC_DEV *pCodecDev); +MV_VOID mvCLAudioCodecInputVolumeMute(MV_AUDIO_CODEC_DEV *pCodecDev, MV_BOOL bMute); + +/* Function to control output tone */ +MV_VOID mvCLAudioCodecTrebleSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_8 nTreble); +MV_U8 mvCLAudioCodecTrebleGet(MV_AUDIO_CODEC_DEV *pCodecDev); +MV_VOID mvCLAudioCodecBassSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_8 nBass); +MV_U8 mvCLAudioCodecBassGet(MV_AUDIO_CODEC_DEV *pCodecDev); + +/* Function to access the Cirrus Logic CODEC registers */ +MV_VOID mvCLAudioCodecRegSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_U8 nOffset, MV_U8 nData); +MV_U8 mvCLAudioCodecRegGet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_U8 nOffset); +MV_VOID mvCLAudioCodecRegBitsSet(MV_AUDIO_CODEC_DEV *pCodecDev, MV_U8 nOffset, MV_U8 nBits); +MV_VOID mvCLAudioCodecRegBitsReset(MV_AUDIO_CODEC_DEV *pCodecDev, MV_U8 nOffset, MV_U8 nBits); + + +#endif /* __INCmvCLAudioCodech */ + diff --git a/board/mv_feroceon/mv_hal/audio/dac/mvCLAudioCodecRegs.h b/board/mv_feroceon/mv_hal/audio/dac/mvCLAudioCodecRegs.h new file mode 100644 index 0000000..aef84a7 --- /dev/null +++ b/board/mv_feroceon/mv_hal/audio/dac/mvCLAudioCodecRegs.h @@ -0,0 +1,83 @@ + +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCLAudioCodecRegsh +#define __INCmvCLAudioCodecRegsh + +#include "mvTypes.h" +//#include "mvRegs.h" + +#define CL_AUDIO_CODEC_ID_REG 0x1 +#define CL_AUDIO_CODEC_IF_CTRL_REG 0x4 +#define CL_AUDIO_CODEC_ADC_INPUT_INV_MUTE_REG 0x7 +#define CL_AUDIO_CODEC_DAC_OUTPUT_CTRL_REG 0x8 +#define CL_AUDIO_CODEC_DAC_CTRL_REG 0x9 +#define CL_AUDIO_CODEC_PGAA_VOL_CTRL_REG 0xa +#define CL_AUDIO_CODEC_TONE_CTRL_REG 0x15 +#define CL_AUDIO_CODEC_VOL_OUTA_CTRL_REG 0x16 + + +#endif /* __INCmvCLAudioCodecRegsh */ + diff --git a/board/mv_feroceon/mv_hal/audio/mvAudio.c b/board/mv_feroceon/mv_hal/audio/mvAudio.c new file mode 100644 index 0000000..bd1a0d4 --- /dev/null +++ b/board/mv_feroceon/mv_hal/audio/mvAudio.c @@ -0,0 +1,1050 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvAudio.h" +#include "mvAudioRegs.h" +#include "ctrlEnv/sys/mvSysAudio.h" + +static MV_U32 audioBurstBytesNumGet(MV_AUDIO_BURST_SIZE burst); + +/******************************************************************************* +* mvAudioHalInit - Initialize the Audio subsystem +* +* DESCRIPTION: +* +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvAudioHalInit(MV_U8 unit) +{ + int timeout; + + MV_REG_BIT_RESET(MV_AUDIO_PLL_CTRL1_REG(unit),0x333FF8); + MV_REG_BIT_SET(MV_AUDIO_PLL_CTRL1_REG(unit),0x111D18); + + /*MV_REG_BIT_RESET(0x10074,0xC018000); + MV_REG_BIT_SET(0x10074,0x4008000);*/ + + timeout = 10000000; + while(timeout--); + + MV_REG_BIT_RESET(MV_AUDIO_PLL_CTRL1_REG(unit),0x333FF8); + MV_REG_BIT_SET(MV_AUDIO_PLL_CTRL1_REG(unit),0x111D18); + + /*MV_REG_BIT_RESET(0x10074,0xC018000); + MV_REG_BIT_SET(0x10074,0x4008000);*/ + +} + + + +/* Clocks Control and Status related*/ +/******************************************************************************* +* mvAudioDCOCtrlSet - Set DCO control register +* +* DESCRIPTION: +* +* INPUT: +* dcoCtrl: pointer to MV_AUDIO_FREQ_DATA structure +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ + +MV_STATUS mvAudioDCOCtrlSet(int unit, MV_AUDIO_FREQ_DATA *dcoCtrl) +{ + MV_U32 reg; + /* Check parameters*/ + if (dcoCtrl->baseFreq > AUDIO_FREQ_96KH) + { + mvOsPrintf("mvAudioDCOCtrlSet: dcoCtrl->baseFreq value (0x%x) invalid\n", + dcoCtrl->baseFreq); + return MV_BAD_PARAM; + + } + if ((dcoCtrl->offset > 0xFD0)||(dcoCtrl->offset < 0x20)) + { + mvOsPrintf("mvAudioDCOCtrlSet: dcoCtrl->offset value (0x%x) invalid\n", + dcoCtrl->baseFreq); + return MV_BAD_PARAM; + } + reg = MV_REG_READ(MV_AUDIO_DCO_CTRL_REG(unit)); + + reg &= ~(ADCR_DCO_CTRL_FS_MASK|ADCR_DCO_CTRL_OFFSET_MASK); + reg |= ((dcoCtrl->baseFreq << ADCR_DCO_CTRL_FS_OFFS) | + (dcoCtrl->offset << ADCR_DCO_CTRL_OFFSET_OFFS)); + MV_REG_WRITE(MV_AUDIO_DCO_CTRL_REG(unit), reg); + + return MV_OK; +} + +/******************************************************************************* +* mvAudioDCOCtrlGet - Set DCO control register +* +* DESCRIPTION: +* +* INPUT: +* dcoCtrl: pointer to MV_AUDIO_FREQ_DATA structure +* OUTPUT: +* dcoCtrl: pointer to MV_AUDIO_FREQ_DATA structure +* RETURN: +* None +* +*******************************************************************************/ + +MV_VOID mvAudioDCOCtrlGet(int unit, MV_AUDIO_FREQ_DATA *dcoCtrl) +{ + MV_U32 reg = MV_REG_READ(MV_AUDIO_DCO_CTRL_REG(unit)); + + dcoCtrl->baseFreq = (reg & ADCR_DCO_CTRL_FS_MASK) >> ADCR_DCO_CTRL_FS_OFFS ; + dcoCtrl->offset = (reg & ADCR_DCO_CTRL_OFFSET_MASK) >> ADCR_DCO_CTRL_OFFSET_OFFS ; +} +/******************************************************************************* +* mvAudioSpcrCtrlGet - Set SPCR control register +* +* DESCRIPTION: +* +* INPUT: +* spcrCtrl: pointer to MV_AUDIO_FREQ_DATA structure +* OUTPUT: +* spcrCtrl: pointer to MV_AUDIO_FREQ_DATA structure +* RETURN: +* None +* +*******************************************************************************/ + +MV_VOID mvAudioSpcrCtrlGet(int unit, MV_AUDIO_FREQ_DATA *spcrCtrl) +{ + MV_U32 reg = MV_REG_READ(MV_AUDIO_SPCR_DCO_STATUS_REG(unit)); + + spcrCtrl->baseFreq = (reg & ASDSR_SPCR_CTRLFS_MASK) >> ASDSR_SPCR_CTRLFS_OFFS ; + spcrCtrl->offset = (reg & ASDSR_SPCR_CTRLOFFSET_MASK) >> ASDSR_SPCR_CTRLOFFSET_OFFS; +} + + +/* Audio PlayBack related*/ +/******************************************************************************* +* mvAudioPlaybackControlSet - Set Playback general parameters +* +* DESCRIPTION: +* +* INPUT: +* ctrl: pointer to MV_AUDIO_PLAYBACK_CTRL structure +* OUTPUT: +* None +* RETURN: +* MV_OK on success , MV_FAIL on fail +* +*******************************************************************************/ +MV_STATUS mvAudioPlaybackControlSet(int unit, MV_AUDIO_PLAYBACK_CTRL *ctrl) +{ + MV_AUDIO_DEC_WIN audioWin; + MV_CPU_DEC_WIN cpuWin; + MV_ADDR_WIN bufAddrWin; + MV_U32 target; + MV_U32 reg; + + if (ctrl->monoMode >= AUDIO_PLAY_OTHER_MONO) + { + mvOsPrintf("mvAudioPlaybackControlSet: Error ,illegal monoMode %x\n", + ctrl->monoMode ); + + return MV_FAIL; + + } + + if ((ctrl->burst != AUDIO_32BYTE_BURST) && + (ctrl->burst != AUDIO_128BYTE_BURST)) + { + mvOsPrintf("mvAudioPlaybackControlSet: Error ,illegal burst %x\n", + ctrl->burst ); + + return MV_FAIL; + + } + + if (ctrl->bufferPhyBase & (MV_AUDIO_BUFFER_MIN_ALIGN - 1)) + { + mvOsPrintf("mvAudioPlaybackControlSet: Error ,bufferPhyBase is not"\ + "\n aligned to 0x%x bytes\n",MV_AUDIO_BUFFER_MIN_ALIGN ); + + return MV_FAIL; + } + + if ((ctrl->bufferSize <= audioBurstBytesNumGet(ctrl->burst))|| + (ctrl->bufferSize & (audioBurstBytesNumGet(ctrl->burst) - 1))|| + (ctrl->bufferSize > AUDIO_REG_TO_SIZE(APBBCR_SIZE_MAX)) + ) + { + mvOsPrintf("mvAudioPlaybackControlSet: Error, bufferSize smaller"\ + "\nthan or not multiple of 0x%x bytes or larger than"\ + "\n 0x%x", + audioBurstBytesNumGet(ctrl->burst), + AUDIO_REG_TO_SIZE(APBBCR_SIZE_MAX)); + + return MV_FAIL; + } + + + reg = MV_REG_READ(MV_AUDIO_PLAYBACK_CTRL_REG(unit)); + reg &= ~(APCR_PLAY_BURST_SIZE_MASK|APCR_LOOPBACK_MASK|APCR_PLAY_MONO_MASK | + APCR_PLAY_SAMPLE_SIZE_MASK); + reg |= ctrl->burst << APCR_PLAY_BURST_SIZE_OFFS; + reg |= ctrl->loopBack << APCR_LOOPBACK_OFFS; + reg |= ctrl->monoMode << APCR_PLAY_MONO_OFFS; + reg |= ctrl->sampleSize << APCR_PLAY_SAMPLE_SIZE_OFFS; + MV_REG_WRITE(MV_AUDIO_PLAYBACK_CTRL_REG(unit), reg); + + /* Get the details of the Playback address window*/ + if( mvAudioWinGet( MV_AUDIO_PLAYBACK_WIN_NUM, &audioWin ) != MV_OK ) + { + mvOsPrintf("mvAudioPlaybackControlSet: Error calling mvAudioWinGet on win %d\n", + MV_AUDIO_PLAYBACK_WIN_NUM); + return MV_FAIL; + } + + bufAddrWin.baseHigh = 0; + bufAddrWin.baseLow = ctrl->bufferPhyBase; + bufAddrWin.size = ctrl->bufferSize; + + /* If Playback window is not enabled or buffer address is not within window boundries + then try to set a new value to the Playback window by + Geting the target of where the buffer exist, if the buffer is within the window + of the new target then set the Playback window to that target + else return Fail + */ + + if((audioWin.enable != MV_TRUE) || + (MV_TRUE != ctrlWinWithinWinTest(&bufAddrWin, &audioWin.addrWin))) + { + /* Get the target of the buffer that user require*/ + target = mvCpuIfTargetOfBaseAddressGet(ctrl->bufferPhyBase); + if (MAX_TARGETS == target) + { + mvOsPrintf("mvCpuIfTargetOfBaseAddressGet: Error calling mvAudioWinGet on address 0x%x\n", + ctrl->bufferPhyBase); + return MV_FAIL; + } + + /* Get the window details of this target*/ + if (MV_OK != mvCpuIfTargetWinGet(target, &cpuWin)) + { + mvOsPrintf("mvAudioPlaybackControlSet: Error calling mvCpuIfTargetWinGet on target %d\n", + target); + return MV_FAIL; + + } + + /* if the address window of the target is enabled and te user buffer is within + that target address window then set the palyback\recording window to the + target window + + */ + if((cpuWin.enable == MV_TRUE) && + (MV_TRUE == ctrlWinWithinWinTest(&bufAddrWin, &cpuWin.addrWin))) + { + audioWin.addrWin.baseHigh = cpuWin.addrWin.baseHigh; + audioWin.addrWin.baseLow = cpuWin.addrWin.baseLow; + audioWin.addrWin.size = cpuWin.addrWin.size; + audioWin.enable = cpuWin.enable; + audioWin.target = target; + + + if( mvAudioWinSet( MV_AUDIO_PLAYBACK_WIN_NUM, &audioWin ) != MV_OK ) + { + mvOsPrintf("mvAudioPlaybackControlSet: Error calling mvAudioWinGet on win %d\n", + MV_AUDIO_PLAYBACK_WIN_NUM); + return MV_FAIL; + } + + } + else + { + mvOsPrintf("mvAudioPlaybackControlSet: Error buffer is not within a valid target\n"); + return MV_FAIL; + + } + } + /* Set the interrupt byte count. */ + reg = ctrl->intByteCount & APBCI_BYTE_COUNT_MASK; + MV_REG_WRITE(MV_AUDIO_PLAYBACK_BYTE_CNTR_INT_REG(unit), reg); + + MV_REG_WRITE(MV_AUDIO_PLAYBACK_BUFF_START_REG(unit), ctrl->bufferPhyBase); + MV_REG_WRITE(MV_AUDIO_PLAYBACK_BUFF_SIZE_REG(unit), + AUDIO_SIZE_TO_REG(ctrl->bufferSize)); + + return MV_OK; +} + +/******************************************************************************* +* mvAudioPlaybackControlGet - Get Playback general parameters +* +* DESCRIPTION: +* +* INPUT: +* ctrl: pointer to MV_AUDIO_PLAYBACK_CTRL structure +* OUTPUT: +* ctrl: pointer to MV_AUDIO_PLAYBACK_CTRL structure +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvAudioPlaybackControlGet(int unit, MV_AUDIO_PLAYBACK_CTRL *ctrl) +{ + MV_U32 reg = MV_REG_READ(MV_AUDIO_PLAYBACK_CTRL_REG(unit)); + + ctrl->burst = (reg & APCR_PLAY_BURST_SIZE_MASK) >> APCR_PLAY_BURST_SIZE_OFFS; + ctrl->loopBack = (reg & APCR_LOOPBACK_MASK) >> APCR_LOOPBACK_OFFS; + ctrl->monoMode = (reg & APCR_PLAY_MONO_MASK) >> APCR_PLAY_MONO_OFFS; + + ctrl->bufferPhyBase = MV_REG_READ(MV_AUDIO_PLAYBACK_BUFF_START_REG(unit)); + reg = MV_REG_READ(MV_AUDIO_PLAYBACK_BUFF_SIZE_REG(unit)); + ctrl->bufferSize = AUDIO_REG_TO_SIZE(reg); + + ctrl->intByteCount = MV_REG_READ(MV_AUDIO_PLAYBACK_BYTE_CNTR_INT_REG(unit)); +} +/******************************************************************************* +* mvAudioPlaybackStatusGet - Get Playback status parameters +* +* DESCRIPTION: +* +* INPUT: +* ctrl: pointer to MV_AUDIO_PLAYBACK_STATUS structure +* OUTPUT: +* ctrl: pointer to MV_AUDIO_PLAYBACK_STATUS structure +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvAudioPlaybackStatusGet(int unit, MV_AUDIO_PLAYBACK_STATUS *status) +{ + status->muteI2S = ((MV_REG_READ(MV_AUDIO_PLAYBACK_CTRL_REG(unit))&APCR_PLAY_I2S_MUTE_MASK)? + MV_TRUE:MV_FALSE); + status->enableI2S = ((MV_REG_READ(MV_AUDIO_PLAYBACK_CTRL_REG(unit))&APCR_PLAY_I2S_ENABLE_MASK)? + MV_TRUE:MV_FALSE); + status->muteSPDIF = ((MV_REG_READ(MV_AUDIO_PLAYBACK_CTRL_REG(unit))&APCR_PLAY_SPDIF_MUTE_MASK)? + MV_TRUE:MV_FALSE); + status->enableSPDIF = ((MV_REG_READ(MV_AUDIO_PLAYBACK_CTRL_REG(unit))&APCR_PLAY_SPDIF_ENABLE_MASK)? + MV_TRUE:MV_FALSE); + status->pause = ((MV_REG_READ(MV_AUDIO_PLAYBACK_CTRL_REG(unit))&APCR_PLAY_PAUSE_MASK)? + MV_TRUE:MV_FALSE); + +} + +/******************************************************************************* +* mvSPDIFPlaybackCtrlGet - Set SPDIF Playback control parameters +* +* DESCRIPTION: +* +* INPUT: +* ctrl: pointer to MV_SPDIF_PLAYBACK_CTRL structure +* OUTPUT: +* ctrl: pointer to MV_SPDIF_PLAYBACK_CTRL structure +* RETURN: +* None +* +*******************************************************************************/ +/* Audio SPDIF PlayBack related*/ +MV_VOID mvSPDIFPlaybackCtrlSet(int unit, MV_SPDIF_PLAYBACK_CTRL *ctrl) +{ + if (ctrl->blockStartInternally) + { + MV_REG_BIT_RESET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_BLOCK_START_MASK); + } + else + { + MV_REG_BIT_SET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_BLOCK_START_MASK); + } + + if (ctrl->validityFromMemory) + { + MV_REG_BIT_SET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_PB_EN_MEM_VALIDITY_MASK); + } + else + { + MV_REG_BIT_RESET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_PB_EN_MEM_VALIDITY_MASK); + } + + if (ctrl->userBitsFromMemory) + { + MV_REG_BIT_SET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_PB_MEM_USR_EN_MASK); + } + else + { + MV_REG_BIT_RESET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_PB_MEM_USR_EN_MASK); + } + + if (ctrl->underrunData) + { + MV_REG_BIT_SET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_UNDERRUN_DATA_MASK); + } + else + { + MV_REG_BIT_RESET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_UNDERRUN_DATA_MASK); + } + + if (ctrl->validity) + { + MV_REG_BIT_SET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_PB_REG_VALIDITY_MASK); + } + else + { + MV_REG_BIT_RESET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_PB_REG_VALIDITY_MASK); + } + + if (ctrl->nonPcm) + { + MV_REG_BIT_SET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_PB_NONPCM_MASK); + } + else + { + MV_REG_BIT_RESET(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit),ASPCR_SPDIF_PB_NONPCM_MASK); + } +} +/******************************************************************************* +* mvSPDIFPlaybackCtrlGet - Get SPDIF Playback control parameters +* +* DESCRIPTION: +* +* INPUT: +* ctrl: pointer to MV_SPDIF_PLAYBACK_CTRL structure +* OUTPUT: +* ctrl: pointer to MV_SPDIF_PLAYBACK_CTRL structure +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSPDIFPlaybackCtrlGet(int unit, MV_SPDIF_PLAYBACK_CTRL *ctrl) +{ + ctrl->blockStartInternally = + ((MV_REG_READ(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit))&ASPCR_SPDIF_BLOCK_START_MASK)? + MV_TRUE:MV_FALSE); + ctrl->nonPcm = + ((MV_REG_READ(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit))&ASPCR_SPDIF_PB_NONPCM_MASK)? + MV_TRUE:MV_FALSE); + ctrl->underrunData = + ((MV_REG_READ(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit))&ASPCR_SPDIF_UNDERRUN_DATA_MASK)? + MV_TRUE:MV_FALSE); + ctrl->userBitsFromMemory = + ((MV_REG_READ(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit))&ASPCR_SPDIF_PB_MEM_USR_EN_MASK)? + MV_TRUE:MV_FALSE); + ctrl->validity = + ((MV_REG_READ(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit))&ASPCR_SPDIF_PB_REG_VALIDITY_MASK)? + MV_TRUE:MV_FALSE); + ctrl->validityFromMemory = + ((MV_REG_READ(MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit))&ASPCR_SPDIF_PB_EN_MEM_VALIDITY_MASK)? + MV_TRUE:MV_FALSE); + + + +} + +/******************************************************************************* +* mvI2SPlaybackCtrlSet - Set I2S Playback control parameters +* +* DESCRIPTION: +* +* INPUT: +* ctrl: pointer to MV_I2S_PLAYBACK_CTRL structure +* OUTPUT: +* ctrl: pointer to MV_I2S_PLAYBACK_CTRL structure +* RETURN: +* MV_OK on success, and MV_FAIL on fail. +* +*******************************************************************************/ + +/* Audio I2S PlayBack related*/ +MV_STATUS mvI2SPlaybackCtrlSet(int unit, MV_I2S_PLAYBACK_CTRL *ctrl) +{ + MV_U32 reg = MV_REG_READ(MV_AUDIO_I2S_PLAY_CTRL_REG(unit)) & + ~(AIPCR_I2S_PB_JUSTF_MASK|AIPCR_I2S_PB_SAMPLE_SIZE_MASK); + + if (ctrl->sampleSize > SAMPLE_16BIT) + { + mvOsPrintf("mvI2SPlaybackCtrlSet: illigal sample size\n"); + return MV_FAIL; + } + + reg |= ctrl->sampleSize << AIPCR_I2S_PB_SAMPLE_SIZE_OFFS; + + if (ctrl->sendLastFrame) + { + MV_REG_BIT_SET(MV_AUDIO_I2S_PLAY_CTRL_REG(unit),AIPCR_I2S_SEND_LAST_FRM_MASK); + } + else + { + MV_REG_BIT_RESET(MV_AUDIO_I2S_PLAY_CTRL_REG(unit),AIPCR_I2S_SEND_LAST_FRM_MASK); + } + + + switch (ctrl->justification) + { + case I2S_JUSTIFIED: + case LEFT_JUSTIFIED: + case RIGHT_JUSTIFIED: + reg |= ctrl->justification << AIPCR_I2S_PB_JUSTF_OFFS; + break; + default: + mvOsPrintf("mvI2SPlaybackCtrlSet: illigal Justification value\n"); + return MV_FAIL; + + } + + MV_REG_WRITE(MV_AUDIO_I2S_PLAY_CTRL_REG(unit), reg); + return MV_OK; + +} + +/******************************************************************************* +* mvI2SPlaybackCtrlGet - Get I2S Playback control parameters +* +* DESCRIPTION: +* +* INPUT: +* ctrl: pointer to MV_I2S_PLAYBACK_CTRL structure +* OUTPUT: +* ctrl: pointer to MV_I2S_PLAYBACK_CTRL structure +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvI2SPlaybackCtrlGet(int unit, MV_I2S_PLAYBACK_CTRL *ctrl) +{ + ctrl->sendLastFrame = + ((MV_REG_READ(MV_AUDIO_I2S_PLAY_CTRL_REG(unit))&AIPCR_I2S_SEND_LAST_FRM_MASK)? + MV_TRUE:MV_FALSE); + + ctrl->justification = + ((MV_REG_READ(MV_AUDIO_I2S_PLAY_CTRL_REG(unit))&AIPCR_I2S_PB_JUSTF_MASK) >> + AIPCR_I2S_PB_JUSTF_OFFS); + + ctrl->sampleSize = + ((MV_REG_READ(MV_AUDIO_I2S_PLAY_CTRL_REG(unit))&AIPCR_I2S_PB_SAMPLE_SIZE_MASK ) >> + AIPCR_I2S_PB_SAMPLE_SIZE_OFFS); + +} +/******************************************************************************* +* mvAudioRecordControlGet - Get Recording control parameters +* +* DESCRIPTION: +* +* INPUT: +* ctrl: pointer to MV_AUDIO_RECORD_CTRL structure +* OUTPUT: +* ctrl: pointer to MV_AUDIO_RECORD_CTRL structure +* RETURN: +* MV_OK on success , MV_FAIL on fail. +* +*******************************************************************************/ +/* Audio Recording*/ +MV_STATUS mvAudioRecordControlSet(int unit, MV_AUDIO_RECORD_CTRL *ctrl) +{ + MV_AUDIO_DEC_WIN audioWin; + MV_CPU_DEC_WIN cpuWin; + MV_ADDR_WIN bufAddrWin; + MV_U32 target; + MV_U32 reg; + + if (ctrl->monoChannel > AUDIO_REC_RIGHT_MONO) + { + mvOsPrintf("mvAudioRecordControlSet: Error ,illegal monoChannel %x\n", + ctrl->monoChannel ); + + return MV_FAIL; + } + + if ((ctrl->burst != AUDIO_32BYTE_BURST) && + (ctrl->burst != AUDIO_128BYTE_BURST)) + { + mvOsPrintf("mvAudioRecordControlSet: Error ,illegal burst %x\n", + ctrl->burst ); + + return MV_FAIL; + + } + + if (ctrl->bufferPhyBase & (MV_AUDIO_BUFFER_MIN_ALIGN - 1)) + { + mvOsPrintf("mvAudioRecordControlSet: Error ,bufferPhyBase is not"\ + "\n aligned to 0x%x bytes\n",MV_AUDIO_BUFFER_MIN_ALIGN ); + + return MV_FAIL; + } + + if ((ctrl->bufferSize <= audioBurstBytesNumGet(ctrl->burst))|| + (ctrl->bufferSize & (audioBurstBytesNumGet(ctrl->burst) - 1))|| + (ctrl->bufferSize > AUDIO_REG_TO_SIZE(APBBCR_SIZE_MAX)) + ) + { + mvOsPrintf("mvAudioRecordControlSet: Error, bufferSize smaller"\ + "\nthan or not multiple of 0x%x bytes or larger than"\ + "\n 0x%x", + audioBurstBytesNumGet(ctrl->burst), + AUDIO_REG_TO_SIZE(APBBCR_SIZE_MAX)); + + return MV_FAIL; + } + + + reg = MV_REG_READ(MV_AUDIO_RECORD_CTRL_REG(unit)); + reg &= ~(ARCR_RECORD_BURST_SIZE_MASK|ARCR_RECORDED_MONO_CHNL_MASK| + ARCR_RECORD_SAMPLE_SIZE_MASK); + switch (ctrl->sampleSize) + { + case SAMPLE_16BIT: + case SAMPLE_16BIT_NON_COMPACT: + case SAMPLE_20BIT: + case SAMPLE_24BIT: + case SAMPLE_32BIT: + reg |= ctrl->sampleSize << ARCR_RECORD_SAMPLE_SIZE_OFFS; + break; + default: + mvOsPrintf("mvAudioRecordControlSet: Error ,illegal sampleSize %x\n", + ctrl->sampleSize ); + + return MV_FAIL; + } + + reg |= ctrl->burst << ARCR_RECORD_BURST_SIZE_OFFS; + reg |= ctrl->monoChannel << ARCR_RECORDED_MONO_CHNL_OFFS; + MV_REG_WRITE(MV_AUDIO_RECORD_CTRL_REG(unit), reg); + + if (ctrl->mono) + { + MV_REG_BIT_SET (MV_AUDIO_RECORD_CTRL_REG(unit), + ARCR_RECORD_MONO_MASK); + } + else + { + MV_REG_BIT_RESET (MV_AUDIO_RECORD_CTRL_REG(unit), + ARCR_RECORD_MONO_MASK); + } + + /* Get the details of the Record address window*/ + if( mvAudioWinGet( MV_AUDIO_RECORD_WIN_NUM, &audioWin ) != MV_OK ) + { + mvOsPrintf("mvAudioRecordControlSet: Error calling mvAudioWinGet on win %d\n", + MV_AUDIO_RECORD_WIN_NUM); + return MV_FAIL; + } + + bufAddrWin.baseHigh = 0; + bufAddrWin.baseLow = ctrl->bufferPhyBase; + bufAddrWin.size = ctrl->bufferSize; + + /* If Record window is not enabled or buffer address is not within window boundries + then try to set a new value to the Record window by + Geting the target of where the buffer exist, if the buffer is within the window + of the new target then set the Record window to that target + else return Fail + */ + + if((audioWin.enable != MV_TRUE) || + (MV_TRUE != ctrlWinWithinWinTest(&bufAddrWin, &audioWin.addrWin))) + { + /* Get the target of the buffer that user require*/ + target = mvCpuIfTargetOfBaseAddressGet(ctrl->bufferPhyBase); + if (MAX_TARGETS == target) + { + mvOsPrintf("mvAudioRecordControlSet: Error calling mvAudioWinGet on address 0x%x\n", + ctrl->bufferPhyBase); + return MV_FAIL; + } + + /* Get the window details of this target*/ + if (MV_OK != mvCpuIfTargetWinGet(target, &cpuWin)) + { + mvOsPrintf("mvAudioRecordControlSet: Error calling mvCpuIfTargetWinGet on target %d\n", + target); + return MV_FAIL; + + } + + /* if the address window of the target is enabled and te user buffer is within + that target address window then set the palyback\recording window to the + target window + + */ + if((cpuWin.enable == MV_TRUE) && + (MV_TRUE == ctrlWinWithinWinTest(&bufAddrWin, &cpuWin.addrWin))) + { + + audioWin.addrWin.baseHigh = cpuWin.addrWin.baseHigh; + audioWin.addrWin.baseLow = cpuWin.addrWin.baseLow; + audioWin.addrWin.size = cpuWin.addrWin.size; + audioWin.enable = cpuWin.enable; + audioWin.target = target; + + if( mvAudioWinSet( MV_AUDIO_RECORD_WIN_NUM, &audioWin ) != MV_OK ) + { + mvOsPrintf("mvAudioRecordControlSet: Error calling mvAudioWinGet on win %d\n", + MV_AUDIO_RECORD_WIN_NUM); + return MV_FAIL; + } + + } + else + { + mvOsPrintf("mvAudioRecordControlSet: Error buffer is not within a valid target\n"); + return MV_FAIL; + + } + } + + /* Set the interrupt byte count. */ + reg = ctrl->intByteCount & ARBCI_BYTE_COUNT_MASK; + MV_REG_WRITE(MV_AUDIO_RECORD_BYTE_CNTR_INT_REG(unit), reg); + + MV_REG_WRITE(MV_AUDIO_RECORD_START_ADDR_REG(unit), ctrl->bufferPhyBase); + MV_REG_WRITE(MV_AUDIO_RECORD_BUFF_SIZE_REG(unit), + AUDIO_SIZE_TO_REG(ctrl->bufferSize)); + + return MV_OK; +} + +/******************************************************************************* +* mvAudioRecordControlGet - Get Recording control parameters +* +* DESCRIPTION: +* +* INPUT: +* ctrl: pointer to MV_AUDIO_RECORD_CTRL structure +* OUTPUT: +* ctrl: pointer to MV_AUDIO_RECORD_CTRL structure +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvAudioRecordControlGet(int unit, MV_AUDIO_RECORD_CTRL *ctrl) +{ + MV_U32 reg; + + ctrl->mono = + ((MV_REG_READ(MV_AUDIO_RECORD_CTRL_REG(unit))&ARCR_RECORD_MONO_MASK)? + MV_TRUE:MV_FALSE); + + ctrl->burst = + ((MV_REG_READ(MV_AUDIO_RECORD_CTRL_REG(unit))&ARCR_RECORD_BURST_SIZE_MASK) >> + ARCR_RECORD_BURST_SIZE_OFFS); + + ctrl->monoChannel = + ((MV_REG_READ(MV_AUDIO_RECORD_CTRL_REG(unit))&ARCR_RECORDED_MONO_CHNL_MASK) >> + ARCR_RECORDED_MONO_CHNL_OFFS); + + ctrl->sampleSize = + ((MV_REG_READ(MV_AUDIO_RECORD_CTRL_REG(unit))&ARCR_RECORD_SAMPLE_SIZE_MASK) >> + ARCR_RECORD_SAMPLE_SIZE_OFFS); + + ctrl->bufferPhyBase = MV_REG_READ(MV_AUDIO_RECORD_START_ADDR_REG(unit)); + reg = MV_REG_READ(MV_AUDIO_RECORD_BUFF_SIZE_REG(unit)); + ctrl->bufferSize = AUDIO_REG_TO_SIZE(reg); + + ctrl->intByteCount = MV_REG_READ(MV_AUDIO_RECORD_BYTE_CNTR_INT_REG(unit)); + +} + +/******************************************************************************* +* mvAudioRecordControlGet - Get Recording status parameters +* +* DESCRIPTION: +* +* INPUT: +* status: pointer to MV_AUDIO_RECORD_STATUS structure +* OUTPUT: +* status: pointer to MV_AUDIO_RECORD_STATUS structure +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvAudioRecordStatusGet(int unit, MV_AUDIO_RECORD_STATUS *status) +{ + status->I2SEnable = + ((MV_REG_READ(MV_AUDIO_RECORD_CTRL_REG(unit))&ARCR_RECORD_I2S_EN_MASK)? + MV_TRUE:MV_FALSE); + + status->mute = + ((MV_REG_READ(MV_AUDIO_RECORD_CTRL_REG(unit))&ARCR_RECORD_MUTE_MASK)? + MV_TRUE:MV_FALSE); + + status->pause = + ((MV_REG_READ(MV_AUDIO_RECORD_CTRL_REG(unit))&ARCR_RECORD_PAUSE_MASK)? + MV_TRUE:MV_FALSE); + + status->spdifEnable = + ((MV_REG_READ(MV_AUDIO_RECORD_CTRL_REG(unit))&ARCR_RECORD_SPDIF_EN_MASK)? + MV_TRUE:MV_FALSE); + +} +/******************************************************************************* +* mvSPDIFRecordTclockSet - Set T-clock for SPDIF +* +* DESCRIPTION: +* +* INPUT: +* none +* OUTPUT: +* none +* RETURN: +* MV_OK on success , MV_NOT_SUPPORTED on non supported T-clock +* +*******************************************************************************/ + +/* SPDIF Recording Related*/ +MV_STATUS mvSPDIFRecordTclockSet(int unit) +{ + MV_U32 tclock = mvBoardTclkGet(); + MV_U32 reg = MV_REG_READ(MV_AUDIO_SPDIF_REC_GEN_REG(unit)); + + reg &= ~ASRGR_CORE_CLK_FREQ_MASK; + + switch (tclock) + { + case MV_BOARD_TCLK_133MHZ: + reg |= ASRGR_CORE_CLK_FREQ_133MHZ; + break; + case MV_BOARD_TCLK_150MHZ: + reg |= ASRGR_CORE_CLK_FREQ_150MHZ; + break; + case MV_BOARD_TCLK_166MHZ: + reg |= ASRGR_CORE_CLK_FREQ_166MHZ; + break; + case MV_BOARD_TCLK_200MHZ: + reg |= ASRGR_CORE_CLK_FREQ_200MHZ; + break; + default: + mvOsPrintf("mvSPDIFRecordTclockSet: Not supported core clock %d\n",tclock); + return MV_NOT_SUPPORTED; + } + + MV_REG_WRITE(MV_AUDIO_SPDIF_REC_GEN_REG(unit), reg); + + return MV_OK; + +} +/******************************************************************************* +* mvSPDIFRecordTclockGet - Get T-clock for SPDIF +* +* DESCRIPTION: +* +* INPUT: +* none +* OUTPUT: +* none +* RETURN: +* T-clock configured in the SPDIF. +* +*******************************************************************************/ +MV_U32 mvSPDIFRecordTclockGet(int unit) +{ + MV_U32 reg = (MV_REG_READ(MV_AUDIO_SPDIF_REC_GEN_REG(unit)) & ASRGR_CORE_CLK_FREQ_MASK); + + switch (reg) + { + case ASRGR_CORE_CLK_FREQ_133MHZ: + return MV_BOARD_TCLK_133MHZ; + case ASRGR_CORE_CLK_FREQ_150MHZ: + return MV_BOARD_TCLK_150MHZ; + case ASRGR_CORE_CLK_FREQ_166MHZ: + return MV_BOARD_TCLK_166MHZ; + case ASRGR_CORE_CLK_FREQ_200MHZ: + return MV_BOARD_TCLK_200MHZ; + } + + return 0; +} + +/******************************************************************************* +* mvAudioRecordControlGet - Get SPDIF Recording status parameters +* +* DESCRIPTION: +* +* INPUT: +* status: pointer to MV_SPDIF_RECORD_STATUS structure +* OUTPUT: +* status: pointer to MV_SPDIF_RECORD_STATUS structure +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvSPDIFRecordStatusGet(int unit, MV_SPDIF_RECORD_STATUS *status) +{ + status->freq = + ((MV_REG_READ(MV_AUDIO_SPDIF_REC_GEN_REG(unit))&ASRGR_CORE_CLK_FREQ_MASK) >> + ASRGR_CORE_CLK_FREQ_OFFS); + + status->nonLinearPcm = + ((MV_REG_READ(MV_AUDIO_SPDIF_REC_GEN_REG(unit))&ASRGR_NON_PCM_MASK)? + MV_TRUE:MV_FALSE); + + status->validPcm = + ((MV_REG_READ(MV_AUDIO_SPDIF_REC_GEN_REG(unit))&ASRGR_VALID_PCM_INFO_MASK)? + MV_TRUE:MV_FALSE); + +} + +/* I2S Recording Related*/ +/******************************************************************************* +* mvI2SRecordCntrlSet - Get I2S Recording status parameters +* +* DESCRIPTION: +* +* INPUT: +* ctrl: pointer to MV_I2S_RECORD_CTRL structure +* OUTPUT: +* ctrl: pointer to MV_I2S_RECORD_CTRL structure +* RETURN: +* MV_OK on success , MV_FAIL on fail. +* +*******************************************************************************/ +MV_STATUS mvI2SRecordCntrlSet(int unit, MV_I2S_RECORD_CTRL *ctrl) +{ + MV_U32 reg; + +#if 0 + if (ctrl->sample > SAMPLE_16BIT) + { + mvOsPrintf("mvI2SRecordCntrlSet: Error , Illigal sample size %d\n", + ctrl->sample); + return MV_FAIL; + } +#endif + + reg = MV_REG_READ(MV_AUDIO_I2S_REC_CTRL_REG(unit)); + reg &= ~(AIRCR_I2S_RECORD_JUSTF_MASK|AIRCR_I2S_SAMPLE_SIZE_MASK); + + switch (ctrl->justf) + { + case I2S_JUSTIFIED: + case LEFT_JUSTIFIED: + case RIGHT_JUSTIFIED: + case RISE_BIT_CLCK_JUSTIFIED: + reg |= ctrl->justf << AIRCR_I2S_RECORD_JUSTF_OFFS; + break; + default: + return MV_FAIL; + } + + reg |= ctrl->sample << AIRCR_I2S_SAMPLE_SIZE_OFFS; + + MV_REG_WRITE(MV_AUDIO_I2S_REC_CTRL_REG(unit), reg); + return MV_OK; +} + +/******************************************************************************* +* mvAudioRecordControlGet - Get I2S Recording status parameters +* +* DESCRIPTION: +* +* INPUT: +* ctrl: pointer to MV_I2S_RECORD_CTRL structure +* OUTPUT: +* ctrl: pointer to MV_I2S_RECORD_CTRL structure +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvI2SRecordCntrlGet(int unit, MV_I2S_RECORD_CTRL *ctrl) +{ + ctrl->sample = + ((MV_REG_READ(MV_AUDIO_I2S_REC_CTRL_REG(unit))&AIRCR_I2S_SAMPLE_SIZE_MASK) >> + AIRCR_I2S_SAMPLE_SIZE_OFFS); + + ctrl->justf = + ((MV_REG_READ(MV_AUDIO_I2S_REC_CTRL_REG(unit))&AIRCR_I2S_RECORD_JUSTF_MASK) >> + AIRCR_I2S_RECORD_JUSTF_OFFS); +} + + +/******************************************************************************* +* audioBurstBytesNumGet - Convert Burst enum to bytes number +* +* DESCRIPTION: +* +* INPUT: +* burst: MV_AUDIO_BURST_SIZE enum +* OUTPUT: +* none +* RETURN: +* number of burst bytes +* +*******************************************************************************/ +static MV_U32 audioBurstBytesNumGet(MV_AUDIO_BURST_SIZE burst) +{ + switch (burst) + { + case AUDIO_32BYTE_BURST: + return 32; + case AUDIO_128BYTE_BURST: + return 128; + default: + return 0xffffffff; + } +} + diff --git a/board/mv_feroceon/mv_hal/audio/mvAudio.h b/board/mv_feroceon/mv_hal/audio/mvAudio.h new file mode 100644 index 0000000..d4b2f8b --- /dev/null +++ b/board/mv_feroceon/mv_hal/audio/mvAudio.h @@ -0,0 +1,342 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCMVAudioH +#define __INCMVAudioH + +#include "mvCommon.h" +#include "audio/mvAudioRegs.h" + + +/*********************************/ +/* General enums and structures */ +/*********************************/ +/* Type of Audio operations*/ +typedef enum _mvAudioOperation +{ + AUDIO_PLAYBACK = 0, + AUDIO_RECORD = 1 + +}MV_AUDIO_OP; + +typedef struct _mvAudioFreqData +{ + MV_AUDIO_FREQ baseFreq; /* Control FS, selects the base frequency of the DCO */ + MV_U32 offset; /* Offset control in which each step equals to 0.9536 ppm */ + +} MV_AUDIO_FREQ_DATA; + + +/*********************************/ +/* Play Back related structures */ +/*********************************/ + + +typedef struct _mvAudioPlaybackCtrl +{ + MV_AUDIO_BURST_SIZE burst; /* Specifies the Burst Size of the DMA */ + MV_BOOL loopBack; /* When Loopback is enabled, playback + data is looped back to be recorded */ + MV_AUDIO_PLAYBACK_MONO monoMode; /* Mono Mode is used */ + MV_U32 bufferPhyBase; /* Physical Address of DMA buffer */ + MV_U32 bufferSize; /* Size of DMA buffer */ + MV_U32 intByteCount; /* Number of bytes after which an + interrupt will be issued.*/ + MV_AUDIO_SAMPLE_SIZE sampleSize; /* Playback Sample Size*/ +}MV_AUDIO_PLAYBACK_CTRL; + +typedef struct _mvAudioPlaypackStatus +{ + MV_BOOL muteI2S; + MV_BOOL enableI2S; + MV_BOOL muteSPDIF; + MV_BOOL enableSPDIF; + MV_BOOL pause; + +}MV_AUDIO_PLAYBACK_STATUS; + + +typedef struct _mvSpdifPlaybackCtrl +{ + MV_BOOL nonPcm; /* PCM or non-PCM mode*/ + MV_BOOL validity; /* Validity bit value when using + registers (userBitsFromMemory=0)*/ + MV_BOOL underrunData; /* If true send last frame on mute/pause/underrun + otherwise send 24 binary*/ + MV_BOOL userBitsFromMemory; /* otherwise from intenal registers*/ + MV_BOOL validityFromMemory; /* otherwise from internal registers*/ + MV_BOOL blockStartInternally; /* When user and valid bits are form registers + then this bit should be zero */ +}MV_SPDIF_PLAYBACK_CTRL; + +typedef struct _mvI2SPlaybackCtrl +{ + MV_AUDIO_SAMPLE_SIZE sampleSize; + MV_AUDIO_I2S_JUSTIFICATION justification; + MV_BOOL sendLastFrame; /* If true send last frame on mute/pause/underrun + otherwise send 64 binary*/ +}MV_I2S_PLAYBACK_CTRL; + + +/*********************************/ +/* Recording related structures */ +/*********************************/ + +typedef struct _mvAudioRecordCtrl +{ + MV_AUDIO_BURST_SIZE burst; /* Recording DMA Burst Size */ + MV_AUDIO_SAMPLE_SIZE sampleSize; /*Recording Sample Size */ + MV_BOOL mono; /* If true then recording mono else recording stereo*/ + MV_AUDIO_RECORD_MONO monoChannel; /* Left or right moono*/ + MV_U32 bufferPhyBase; /* Physical Address of DMA buffer */ + MV_U32 bufferSize; /* Size of DMA buffer */ + + MV_U32 intByteCount; /* Number of bytes after which an + interrupt will be issued.*/ + + +}MV_AUDIO_RECORD_CTRL; + +typedef struct _mvAudioRecordStatus +{ + MV_BOOL mute; + MV_BOOL pause; + MV_BOOL spdifEnable; + MV_BOOL I2SEnable; + +}MV_AUDIO_RECORD_STATUS; + + +typedef struct _mvSPDIFRecordStatus +{ + MV_BOOL nonLinearPcm; /* pcm non-pcm*/ + MV_BOOL validPcm; /* valid non-valid pcm*/ + MV_AUDIO_SAMPLE_FREQ freq; /* sampled frequency*/ + +}MV_SPDIF_RECORD_STATUS; + +typedef struct _mvI2SRecordCntrl +{ + MV_AUDIO_SAMPLE_SIZE sample; /* I2S Recording Sample Size*/ + MV_AUDIO_I2S_JUSTIFICATION justf; +}MV_I2S_RECORD_CTRL; + + + +/*********************************/ +/* Usefull Macros */ +/* + -- Clocks Control and Status related -- +mvAudioIsDcoLocked() +mvAudioIsSpcrLocked() +mvAudioIsPllLocked() +mvAudioAllCountersClear() +mvAudioPlayCounterClear() +mvAudioRecCounterClear() +mvAudioAllCountersStart() +mvAudioPlayCounterStart() +mvAudioRecCounterStart() +mvAudioAllCountersStop() +mvAudioPlayCounterStop() +mvAudioRecCounterStop() + + -- PlayBack related -- +mvAudioIsPlaybackBusy() +mvAudioI2SPlaybackMute(mute) +mvAudioI2SPlaybackEnable(enable) +mvAudioSPDIFPlaybackMute(mute) +mvAudioSPDIFPlaybackEnable(enable) +mvAudioPlaybackPause(pause) + +---- Recording --- +mvAudioSPDIFRecordingEnable(enable) +mvAudioI2SRecordingEnable(enable) +mvAudioRecordMute(mute) +mvAudioRecordPause(pause) + +********************************/ + + + + +/* Clocks Control and Status related*/ +#define mvAudioIsDcoLocked() \ + (ASDSR_DCO_LOCK_MASK & MV_REG_READ(MV_AUDIO_SPCR_DCO_STATUS_REG)) +#define mvAudioIsSpcrLocked() \ + (ASDSR_SPCR_LOCK_MASK & MV_REG_READ(AUDIO_SPCR_DCO_STATUS_REG)) +#define mvAudioIsPllLocked() \ + (ASDSR_PLL_LOCK_MASK & MV_REG_READ(AUDIO_SPCR_DCO_STATUS_REG)) + +#define mvAudioAllCountersClear() \ + (MV_REG_BIT_SET(MV_AUDIO_SAMPLE_CNTR_CTRL_REG(0),(ASCCR_CLR_REC_CNTR_MASK|ASCCR_CLR_PLAY_CNTR_MASK))) +#define mvAudioPlayCounterClear() \ + (MV_REG_BIT_SET(MV_AUDIO_SAMPLE_CNTR_CTRL_REG(0),(ASCCR_CLR_PLAY_CNTR_MASK))) +#define mvAudioRecCounterClear() \ + (MV_REG_BIT_SET(MV_AUDIO_SAMPLE_CNTR_CTRL_REG(0),(ASCCR_CLR_REC_CNTR_MASK))) + +#define mvAudioAllCountersStart() \ + (MV_REG_BIT_SET(MV_AUDIO_SAMPLE_CNTR_CTRL_REG(0),(ASCCR_ACTIVE_PLAY_CNTR_MASK|ASCCR_ACTIVE_REC_CNTR_MASK))) +#define mvAudioPlayCounterStart() \ + (MV_REG_BIT_SET(MV_AUDIO_SAMPLE_CNTR_CTRL_REG(0),(ASCCR_ACTIVE_PLAY_CNTR_MASK))) +#define mvAudioRecCounterStart() \ + (MV_REG_BIT_SET(MV_AUDIO_SAMPLE_CNTR_CTRL_REG(0),(ASCCR_ACTIVE_REC_CNTR_MASK))) + +#define mvAudioAllCountersStop() \ + (MV_REG_BIT_RESET(MV_AUDIO_SAMPLE_CNTR_CTRL_REG(0),(ASCCR_ACTIVE_PLAY_CNTR_MASK|ASCCR_ACTIVE_REC_CNTR_MASK))) +#define mvAudioPlayCounterStop() \ + (MV_REG_BIT_RESET(MV_AUDIO_SAMPLE_CNTR_CTRL_REG(0),(ASCCR_ACTIVE_PLAY_CNTR_MASK))) +#define mvAudioRecCounterStop() \ + (MV_REG_BIT_RESET(MV_AUDIO_SAMPLE_CNTR_CTRL_REG(0),(ASCCR_ACTIVE_REC_CNTR_MASK))) + +/* Audio PlayBack related*/ +#define mvAudioIsPlaybackBusy() \ + (APCR_PLAY_BUSY_MASK & MV_REG_READ(MV_AUDIO_PLAYBACK_CTRL_REG(0))) + +#define mvAudioI2SPlaybackMute(mute) \ + (void)((mute)?(MV_REG_BIT_SET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_PLAY_I2S_MUTE_MASK)): \ + MV_REG_BIT_RESET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_PLAY_I2S_MUTE_MASK)) +#define mvAudioI2SPlaybackEnable(enable) \ + (void)((enable)?(MV_REG_BIT_SET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_PLAY_I2S_ENABLE_MASK)): \ + MV_REG_BIT_RESET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_PLAY_I2S_ENABLE_MASK)) + +#define mvAudioSPDIFPlaybackMute(mute) \ + (void)((mute)?(MV_REG_BIT_SET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_PLAY_SPDIF_MUTE_MASK)): \ + MV_REG_BIT_RESET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_PLAY_SPDIF_MUTE_MASK)) +#define mvAudioSPDIFPlaybackEnable(enable) \ + (void)((enable)?(MV_REG_BIT_SET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_PLAY_SPDIF_ENABLE_MASK)): \ + MV_REG_BIT_RESET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_PLAY_SPDIF_ENABLE_MASK)) + +#define mvAudioAllIfPlaybackEnable(enable) \ + (void)((enable)? \ + (MV_REG_BIT_SET(MV_AUDIO_PLAYBACK_CTRL_REG(0), \ + (APCR_PLAY_I2S_ENABLE_MASK | APCR_PLAY_SPDIF_ENABLE_MASK))): \ + MV_REG_BIT_RESET(MV_AUDIO_PLAYBACK_CTRL_REG(0), \ + (APCR_PLAY_I2S_ENABLE_MASK | APCR_PLAY_SPDIF_ENABLE_MASK))) + +#define mvAudioPlaybackPause(pause) \ + (void)((pause)?(MV_REG_BIT_SET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_PLAY_PAUSE_MASK)): \ + MV_REG_BIT_RESET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_PLAY_PAUSE_MASK)) + +#define mvAudioPlaybackLoopbackEnable(enable) \ + (void)((enable)?(MV_REG_BIT_SET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_LOOPBACK_MASK)): \ + MV_REG_BIT_RESET(MV_AUDIO_PLAYBACK_CTRL_REG(0),APCR_LOOPBACK_MASK)) + + +/* Audio Recording*/ +#define mvAudioSPDIFRecordingEnable(enable) \ + (void)((enable)?(MV_REG_BIT_SET(MV_AUDIO_RECORD_CTRL_REG(0),ARCR_RECORD_SPDIF_EN_MASK)): \ + MV_REG_BIT_RESET(MV_AUDIO_RECORD_CTRL_REG(0),ARCR_RECORD_SPDIF_EN_MASK)) + +#define mvAudioI2SRecordingEnable(enable) \ + (void)((enable)?(MV_REG_BIT_SET(MV_AUDIO_RECORD_CTRL_REG(0),ARCR_RECORD_I2S_EN_MASK)): \ + MV_REG_BIT_RESET(MV_AUDIO_RECORD_CTRL_REG(0),ARCR_RECORD_I2S_EN_MASK)) + +#define mvAudioRecordMute(mute) \ + (void)((mute)?(MV_REG_BIT_SET(MV_AUDIO_RECORD_CTRL_REG(0),ARCR_RECORD_MUTE_MASK)): \ + MV_REG_BIT_RESET(MV_AUDIO_RECORD_CTRL_REG(0),ARCR_RECORD_MUTE_MASK)) + +#define mvAudioRecordPause(pause) \ + (void)((pause)?(MV_REG_BIT_SET(MV_AUDIO_RECORD_CTRL_REG(0),ARCR_RECORD_PAUSE_MASK)): \ + MV_REG_BIT_RESET(MV_AUDIO_RECORD_CTRL_REG(0),ARCR_RECORD_PAUSE_MASK)) + + + +/*********************************/ +/* Functions API */ +/*********************************/ + +MV_VOID mvAudioHalInit(MV_U8 unit); + +/* Clocks Control and Status related*/ +MV_STATUS mvAudioDCOCtrlSet(int unit, MV_AUDIO_FREQ_DATA *dcoCtrl); +MV_VOID mvAudioDCOCtrlGet(int unit, MV_AUDIO_FREQ_DATA *dcoCtrl); +MV_VOID mvAudioSpcrCtrlGet(int unit, MV_AUDIO_FREQ_DATA *spcrCtrl); + +/* Audio PlayBack related*/ +MV_STATUS mvAudioPlaybackControlSet(int unit, MV_AUDIO_PLAYBACK_CTRL *ctrl); +MV_VOID mvAudioPlaybackControlGet(int unit, MV_AUDIO_PLAYBACK_CTRL *ctrl); +MV_VOID mvAudioPlaybackStatusGet(int unit, MV_AUDIO_PLAYBACK_STATUS *status); + +/* Audio SPDIF PlayBack related*/ +MV_VOID mvSPDIFPlaybackCtrlSet(int unit, MV_SPDIF_PLAYBACK_CTRL *ctrl); +MV_VOID mvSPDIFPlaybackCtrlGet(int unit, MV_SPDIF_PLAYBACK_CTRL *ctrl); + +/* Audio I2S PlayBack related*/ +MV_STATUS mvI2SPlaybackCtrlSet(int unit, MV_I2S_PLAYBACK_CTRL *ctrl); +MV_VOID mvI2SPlaybackCtrlGet(int unit, MV_I2S_PLAYBACK_CTRL *ctrl); + +/* Audio Recording*/ +MV_STATUS mvAudioRecordControlSet(int unit, MV_AUDIO_RECORD_CTRL *ctrl); +MV_VOID mvAudioRecordControlGet(int unit, MV_AUDIO_RECORD_CTRL *ctrl); +MV_VOID mvAudioRecordStatusGet(int unit, MV_AUDIO_RECORD_STATUS *status); + +/* SPDIF Recording Related*/ +MV_STATUS mvSPDIFRecordTclockSet(int unit); +MV_U32 mvSPDIFRecordTclockGet(int unit); +MV_VOID mvSPDIFRecordStatusGet(int unit, MV_SPDIF_RECORD_STATUS *status); + +/* I2S Recording Related*/ +MV_STATUS mvI2SRecordCntrlSet(int unit, MV_I2S_RECORD_CTRL *ctrl); +MV_VOID mvI2SRecordCntrlGet(int unit, MV_I2S_RECORD_CTRL *ctrl); + +#endif diff --git a/board/mv_feroceon/mv_hal/audio/mvAudioRegs.h b/board/mv_feroceon/mv_hal/audio/mvAudioRegs.h new file mode 100644 index 0000000..e9fe958 --- /dev/null +++ b/board/mv_feroceon/mv_hal/audio/mvAudioRegs.h @@ -0,0 +1,411 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCMVAudioRegsH +#define __INCMVAudioRegsH + +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* Audio source Clocks enum*/ +typedef enum _mvAudioClock +{ + AUDIO_DCO_CLK = 0, + AUDIO_SPCR_CLK = 2, + AUDIO_EXT_CLK = 3 + +}MV_AUDIO_CLOCK; + +typedef enum _mvAudioFreq +{ + AUDIO_FREQ_44_1KH = 0, /* 11.2896Mhz */ + AUDIO_FREQ_48KH = 1, /* 12.288Mhz */ + AUDIO_FREQ_96KH =2, /* 24.576Mhz */ + AUDIO_FREQ_LOWER_44_1KH = 3 ,/*Lower than 11.2896MHz*/ + AUDIO_FREQ_HIGHER_96KH = 4, /*Higher than 24.576MHz*/ + AUDIO_FREQ_OTHER = 7, /*Other frequency*/ +}MV_AUDIO_FREQ; + + +typedef enum _mvAudioSampleFreq +{ + SMAPLE_8KHZ = 0, + SMAPLE_16KHZ, + SMAPLE_22_05KHZ, + SMAPLE_24KHZ, + SMAPLE_32KHZ, + SMAPLE_44_1KHZ, + SMAPLE_48KHZ, + SMAPLE_64KHZ, + SMAPLE_88KHZ, + SMAPLE_96KHZ, + SMAPLE_176KHZ, + SMAPLE_192KHZ +}MV_AUDIO_SAMPLE_FREQ; + +typedef enum _mvAudioBurstSize +{ + AUDIO_32BYTE_BURST = 1, + AUDIO_128BYTE_BURST = 2, + +}MV_AUDIO_BURST_SIZE; + +typedef enum _mvAudioPlaybackMono +{ + AUDIO_PLAY_MONO_OFF = 0, + AUDIO_PLAY_LEFT_MONO = 1, + AUDIO_PLAY_RIGHT_MONO = 2, + AUDIO_PLAY_BOTH_MONO = 3, + AUDIO_PLAY_OTHER_MONO = 4 + +}MV_AUDIO_PLAYBACK_MONO; + +typedef enum _mvAudioRecordMono +{ + AUDIO_REC_LEFT_MONO = 0, + AUDIO_REC_RIGHT_MONO = 1, + +}MV_AUDIO_RECORD_MONO; + +typedef enum _mvAudioSampleSize +{ + SAMPLE_32BIT = 0, + SAMPLE_24BIT = 1, + SAMPLE_20BIT = 2, + SAMPLE_16BIT = 3, + SAMPLE_16BIT_NON_COMPACT = 7 + +}MV_AUDIO_SAMPLE_SIZE; + +typedef enum _mvAudioI2SJustification +{ + LEFT_JUSTIFIED = 0, + I2S_JUSTIFIED = 5, + RISE_BIT_CLCK_JUSTIFIED =7, + RIGHT_JUSTIFIED = 8, + +}MV_AUDIO_I2S_JUSTIFICATION; + + +#define APBBCR_SIZE_MAX 0x3FFFFF +#define APBBCR_SIZE_SHIFT 0x2 + +#define AUDIO_REG_TO_SIZE(reg) (((reg) + 1) << APBBCR_SIZE_SHIFT) +#define AUDIO_SIZE_TO_REG(size) (((size) >> APBBCR_SIZE_SHIFT) - 1) + +#define MV_AUDIO_BUFFER_MIN_ALIGN 0x8 + +/********************/ +/* Clocking Control*/ +/*******************/ +#define MV_AUDIO_PLL_CTRL1_REG(unit) (AUDIO_REG_BASE(unit) + 0x1200) + + +#define MV_AUDIO_DCO_CTRL_REG(unit) (AUDIO_REG_BASE(unit) + 0x1204) +#define MV_AUDIO_SPCR_DCO_STATUS_REG(unit) (AUDIO_REG_BASE(unit) + 0x120c) +#define MV_AUDIO_SAMPLE_CNTR_CTRL_REG(unit) (AUDIO_REG_BASE(unit) + 0x1220) +#define MV_AUDIO_PLAYBACK_SAMPLE_CNTR_REG(unit) (AUDIO_REG_BASE(unit) + 0x1224) +#define MV_AUDIO_RECORD_SAMPLE_CNTR_REG(unit) (AUDIO_REG_BASE(unit) + 0x1228) +#define MV_AUDIO_CLOCK_CTRL_REG(unit) (AUDIO_REG_BASE(unit) + 0x1230) + + +/* MV_AUDIO_DCO_CTRL_REG */ +#define ADCR_DCO_CTRL_FS_OFFS 0 +#define ADCR_DCO_CTRL_FS_MASK (0x3 << ADCR_DCO_CTRL_FS_OFFS) +#define ADCR_DCO_CTRL_FS_44_1KHZ (0x0 << ADCR_DCO_CTRL_FS_OFFS) +#define ADCR_DCO_CTRL_FS_48KHZ (0x1 << ADCR_DCO_CTRL_FS_OFFS) +#define ADCR_DCO_CTRL_FS_96KHZ (0x2 << ADCR_DCO_CTRL_FS_OFFS) + + +#define ADCR_DCO_CTRL_OFFSET_OFFS 2 +#define ADCR_DCO_CTRL_OFFSET_MASK (0xfff << ADCR_DCO_CTRL_OFFSET_OFFS) + +/* MV_AUDIO_SPCR_DCO_STATUS_REG */ +#define ASDSR_SPCR_CTRLFS_OFFS 0 +#define ASDSR_SPCR_CTRLFS_MASK (0x7 << ASDSR_SPCR_CTRLFS_OFFS) +#define ASDSR_SPCR_CTRLFS_44_1KHZ (0x0 << ASDSR_SPCR_CTRLFS_OFFS) +#define ASDSR_SPCR_CTRLFS_48KHZ (0x1 << ASDSR_SPCR_CTRLFS_OFFS) +#define ASDSR_SPCR_CTRLFS_96KHZ (0x2 << ASDSR_SPCR_CTRLFS_OFFS) +#define ASDSR_SPCR_CTRLFS_44_1KHZ_LESS (0x3 << ASDSR_SPCR_CTRLFS_OFFS) +#define ASDSR_SPCR_CTRLFS_96KHZ_MORE (0x4 << ASDSR_SPCR_CTRLFS_OFFS) +#define ASDSR_SPCR_CTRLFS_OTHER (0x7 << ASDSR_SPCR_CTRLFS_OFFS) + + +#define ASDSR_SPCR_CTRLOFFSET_OFFS 3 +#define ASDSR_SPCR_CTRLOFFSET_MASK (0xfff << ASDSR_SPCR_CTRLOFFSET_OFFS) + +#define ASDSR_SPCR_LOCK_OFFS 15 +#define ASDSR_SPCR_LOCK_MASK (0x1 << ASDSR_SPCR_LOCK_OFFS) + +#define ASDSR_DCO_LOCK_OFFS 16 +#define ASDSR_DCO_LOCK_MASK (0x1 << ASDSR_DCO_LOCK_OFFS) + +#define ASDSR_PLL_LOCK_OFFS 17 +#define ASDSR_PLL_LOCK_MASK (0x1 << ASDSR_PLL_LOCK_OFFS) + +/*MV_AUDIO_SAMPLE_CNTR_CTRL_REG */ + +#define ASCCR_CLR_PLAY_CNTR_OFFS 9 +#define ASCCR_CLR_PLAY_CNTR_MASK (0x1 << ASCCR_CLR_PLAY_CNTR_OFFS) + +#define ASCCR_CLR_REC_CNTR_OFFS 8 +#define ASCCR_CLR_REC_CNTR_MASK (0x1 << ASCCR_CLR_REC_CNTR_OFFS) + +#define ASCCR_ACTIVE_PLAY_CNTR_OFFS 1 +#define ASCCR_ACTIVE_PLAY_CNTR_MASK (0x1 << ASCCR_ACTIVE_PLAY_CNTR_OFFS) + +#define ASCCR_ACTIVE_REC_CNTR_OFFS 0 +#define ASCCR_ACTIVE_REC_CNTR_MASK (0x1 << ASCCR_ACTIVE_REC_CNTR_OFFS) + +/* MV_AUDIO_CLOCK_CTRL_REG */ +#define ACCR_MCLK_SOURCE_OFFS 0 +#define ACCR_MCLK_SOURCE_MASK (0x3 << ACCR_MCLK_SOURCE_OFFS) +#define ACCR_MCLK_SOURCE_DCO (0x0 << ACCR_MCLK_SOURCE_OFFS) +#define ACCR_MCLK_SOURCE_SPCR (0x2 << ACCR_MCLK_SOURCE_OFFS) +#define ACCR_MCLK_SOURCE_EXT (0x3 << ACCR_MCLK_SOURCE_OFFS) + + + +/********************/ +/* Interrupts */ +/*******************/ +#define MV_AUDIO_ERROR_CAUSE_REG(unit) (AUDIO_REG_BASE(unit) + 0x1300) +#define MV_AUDIO_ERROR_MASK_REG(unit) (AUDIO_REG_BASE(unit) + 0x1304) +#define MV_AUDIO_INT_CAUSE_REG(unit) (AUDIO_REG_BASE(unit) + 0x1308) +#define MV_AUDIO_INT_MASK_REG(unit) (AUDIO_REG_BASE(unit) + 0x130C) +#define MV_AUDIO_RECORD_BYTE_CNTR_INT_REG(unit) (AUDIO_REG_BASE(unit) + 0x1310) +#define MV_AUDIO_PLAYBACK_BYTE_CNTR_INT_REG(unit) (AUDIO_REG_BASE(unit) + 0x1314) + +/* MV_AUDIO_INT_CAUSE_REG*/ +#define AICR_RECORD_BYTES_INT (0x1 << 13) +#define AICR_PLAY_BYTES_INT (0x1 << 14) + +#define ARBCI_BYTE_COUNT_MASK 0xFFFFFF +#define APBCI_BYTE_COUNT_MASK 0xFFFFFF + +/********************/ +/* Audio Playback */ +/*******************/ +/* General */ +#define MV_AUDIO_PLAYBACK_CTRL_REG(unit) (AUDIO_REG_BASE(unit) + 0x1100) +#define MV_AUDIO_PLAYBACK_BUFF_START_REG(unit) (AUDIO_REG_BASE(unit) + 0x1104) +#define MV_AUDIO_PLAYBACK_BUFF_SIZE_REG(unit) (AUDIO_REG_BASE(unit) + 0x1108) +#define MV_AUDIO_PLAYBACK_BUFF_BYTE_CNTR_REG(unit) (AUDIO_REG_BASE(unit) + 0x110c) + +/*SPDIF */ +#define MV_AUDIO_SPDIF_PLAY_CTRL_REG(unit) (AUDIO_REG_BASE(unit) + 0x2204) +#define MV_AUDIO_SPDIF_PLAY_CH_STATUS_LEFT_REG(unit,ind) \ + (AUDIO_REG_BASE(unit) + 0x2280 + (ind << 2)) +#define MV_AUDIO_SPDIF_PLAY_CH_STATUS_RIGHT_REG(unit,ind) \ + (AUDIO_REG_BASE(unit) + 0x22a0 + (ind << 2)) +#define MV_AUDIO_SPDIF_PLAY_USR_BITS_LEFT_REG(unit,ind) \ + (AUDIO_REG_BASE(unit) + 0x22c0 + (ind << 2)) +#define MV_AUDIO_SPDIF_PLAY_USR_BITS_RIGHT_REG(unit,ind) \ + (AUDIO_REG_BASE(unit) + 0x22e0 + (ind << 2)) +/*I2S*/ +#define MV_AUDIO_I2S_PLAY_CTRL_REG(unit) (AUDIO_REG_BASE(unit) + 0x2508) + + +/* MV_AUDIO_PLAYBACK_CTRL_REG */ +#define APCR_PLAY_SAMPLE_SIZE_OFFS 0 +#define APCR_PLAY_SAMPLE_SIZE_MASK (0x7 << APCR_PLAY_SAMPLE_SIZE_OFFS) + +#define APCR_PLAY_I2S_ENABLE_OFFS 3 +#define APCR_PLAY_I2S_ENABLE_MASK (0x1 << APCR_PLAY_I2S_ENABLE_OFFS) + +#define APCR_PLAY_SPDIF_ENABLE_OFFS 4 +#define APCR_PLAY_SPDIF_ENABLE_MASK (0x1 << APCR_PLAY_SPDIF_ENABLE_OFFS) + +#define APCR_PLAY_MONO_OFFS 5 +#define APCR_PLAY_MONO_MASK (0x3 << APCR_PLAY_MONO_OFFS) + +#define APCR_PLAY_I2S_MUTE_OFFS 7 +#define APCR_PLAY_I2S_MUTE_MASK (0x1 << APCR_PLAY_I2S_MUTE_OFFS) + +#define APCR_PLAY_SPDIF_MUTE_OFFS 8 +#define APCR_PLAY_SPDIF_MUTE_MASK (0x1 << APCR_PLAY_SPDIF_MUTE_OFFS) + +#define APCR_PLAY_PAUSE_OFFS 9 +#define APCR_PLAY_PAUSE_MASK (0x1 << APCR_PLAY_PAUSE_OFFS) + +#define APCR_LOOPBACK_OFFS 10 +#define APCR_LOOPBACK_MASK (0x1 << APCR_LOOPBACK_OFFS) + +#define APCR_PLAY_BURST_SIZE_OFFS 11 +#define APCR_PLAY_BURST_SIZE_MASK (0x3 << APCR_PLAY_BURST_SIZE_OFFS) + +#define APCR_PLAY_BUSY_OFFS 16 +#define APCR_PLAY_BUSY_MASK (0x1 << APCR_PLAY_BUSY_OFFS) + +/* MV_AUDIO_PLAYBACK_BUFF_BYTE_CNTR_REG */ +#define APBBCR_SIZE_MAX 0x3FFFFF +#define APBBCR_SIZE_SHIFT 0x2 + + +/* MV_AUDIO_SPDIF_PLAY_CTRL_REG */ +#define ASPCR_SPDIF_BLOCK_START_OFFS 0x0 +#define ASPCR_SPDIF_BLOCK_START_MASK (0x1 << ASPCR_SPDIF_BLOCK_START_OFFS) + +#define ASPCR_SPDIF_PB_EN_MEM_VALIDITY_OFFS 0x1 +#define ASPCR_SPDIF_PB_EN_MEM_VALIDITY_MASK (0x1 << ASPCR_SPDIF_PB_EN_MEM_VALIDITY_OFFS) + +#define ASPCR_SPDIF_PB_MEM_USR_EN_OFFS 0x2 +#define ASPCR_SPDIF_PB_MEM_USR_EN_MASK (0x1 << ASPCR_SPDIF_PB_MEM_USR_EN_OFFS) + +#define ASPCR_SPDIF_UNDERRUN_DATA_OFFS 0x5 +#define ASPCR_SPDIF_UNDERRUN_DATA_MASK (0x1 << ASPCR_SPDIF_UNDERRUN_DATA_OFFS) + +#define ASPCR_SPDIF_PB_REG_VALIDITY_OFFS 16 +#define ASPCR_SPDIF_PB_REG_VALIDITY_MASK (0x1 << ASPCR_SPDIF_PB_REG_VALIDITY_OFFS) + +#define ASPCR_SPDIF_PB_NONPCM_OFFS 17 +#define ASPCR_SPDIF_PB_NONPCM_MASK (0x1 << ASPCR_SPDIF_PB_NONPCM_OFFS) + + + +/* MV_AUDIO_I2S_PLAY_CTRL_REG */ +#define AIPCR_I2S_SEND_LAST_FRM_OFFS 23 +#define AIPCR_I2S_SEND_LAST_FRM_MASK (1 << AIPCR_I2S_SEND_LAST_FRM_OFFS) + +#define AIPCR_I2S_PB_JUSTF_OFFS 26 +#define AIPCR_I2S_PB_JUSTF_MASK (0xf << AIPCR_I2S_PB_JUSTF_OFFS) + +#define AIPCR_I2S_PB_SAMPLE_SIZE_OFFS 30 +#define AIPCR_I2S_PB_SAMPLE_SIZE_MASK (0x3 << AIPCR_I2S_PB_SAMPLE_SIZE_OFFS) + +/********************/ +/* Audio Recordnig */ +/*******************/ +/* General */ +#define MV_AUDIO_RECORD_CTRL_REG(unit) (AUDIO_REG_BASE(unit) + 0x1000) +#define MV_AUDIO_RECORD_START_ADDR_REG(unit) (AUDIO_REG_BASE(unit) + 0x1004) +#define MV_AUDIO_RECORD_BUFF_SIZE_REG(unit) (AUDIO_REG_BASE(unit) + 0x1008) +#define MV_AUDIO_RECORD_BUF_BYTE_CNTR_REG(unit) (AUDIO_REG_BASE(unit) + 0x100C) + +/*SPDIF */ +#define MV_AUDIO_SPDIF_REC_GEN_REG(unit) (AUDIO_REG_BASE(unit) + 0x2004) +#define MV_AUDIO_SPDIF_REC_INT_CAUSE_MASK_REG(unit) (AUDIO_REG_BASE(unit) + 0x2008) +#define MV_AUDIO_SPDIF_REC_CH_STATUS_LEFT_REG(unit,ind) \ + (AUDIO_REG_BASE(unit) + 0x2180 + ((ind) << 2)) +#define MV_AUDIO_SPDIF_REC_CH_STATUS_RIGHT_REG(unit,ind) \ + (AUDIO_REG_BASE(unit) + 0x21a0 + ((ind) << 2)) +#define MV_AUDIO_SPDIF_REC_USR_BITS_LEFT_REG(unit,ind) \ + (AUDIO_REG_BASE(unit) + 0x21c0 + ((ind) << 2)) +#define MV_AUDIO_SPDIF_REC_USR_BITS_RIGHT_REG(unit,ind) \ + (AUDIO_REG_BASE(unit) + 0x21e0 + ((ind) << 2)) + +/*I2S*/ +#define MV_AUDIO_I2S_REC_CTRL_REG(unit) (AUDIO_REG_BASE(unit) + 0x2408) + + +/* MV_AUDIO_RECORD_CTRL_REG*/ +#define ARCR_RECORD_SAMPLE_SIZE_OFFS 0 +#define ARCR_RECORD_SAMPLE_SIZE_MASK (0x7 << ARCR_RECORD_SAMPLE_SIZE_OFFS) + +#define ARCR_RECORDED_MONO_CHNL_OFFS 3 +#define ARCR_RECORDED_MONO_CHNL_MASK (0x1 << ARCR_RECORDED_MONO_CHNL_OFFS) + +#define ARCR_RECORD_MONO_OFFS 4 +#define ARCR_RECORD_MONO_MASK (0x1 << ARCR_RECORD_MONO_OFFS) + +#define ARCR_RECORD_BURST_SIZE_OFFS 5 +#define ARCR_RECORD_BURST_SIZE_MASK (0x3 << ARCR_RECORD_BURST_SIZE_OFFS) + +#define ARCR_RECORD_MUTE_OFFS 8 +#define ARCR_RECORD_MUTE_MASK (0x1 << ARCR_RECORD_MUTE_OFFS) + +#define ARCR_RECORD_PAUSE_OFFS 9 +#define ARCR_RECORD_PAUSE_MASK (0x1 << ARCR_RECORD_PAUSE_OFFS) + +#define ARCR_RECORD_I2S_EN_OFFS 10 +#define ARCR_RECORD_I2S_EN_MASK (0x1 << ARCR_RECORD_I2S_EN_OFFS) + +#define ARCR_RECORD_SPDIF_EN_OFFS 11 +#define ARCR_RECORD_SPDIF_EN_MASK (0x1 << ARCR_RECORD_SPDIF_EN_OFFS) + + +/* MV_AUDIO_SPDIF_REC_GEN_REG*/ +#define ASRGR_CORE_CLK_FREQ_OFFS 1 +#define ASRGR_CORE_CLK_FREQ_MASK (0x3 << ASRGR_CORE_CLK_FREQ_OFFS) +#define ASRGR_CORE_CLK_FREQ_133MHZ (0x0 << ASRGR_CORE_CLK_FREQ_OFFS) +#define ASRGR_CORE_CLK_FREQ_150MHZ (0x1 << ASRGR_CORE_CLK_FREQ_OFFS) +#define ASRGR_CORE_CLK_FREQ_166MHZ (0x2 << ASRGR_CORE_CLK_FREQ_OFFS) +#define ASRGR_CORE_CLK_FREQ_200MHZ (0x3 << ASRGR_CORE_CLK_FREQ_OFFS) + +#define ASRGR_VALID_PCM_INFO_OFFS 7 +#define ASRGR_VALID_PCM_INFO_MASK (0x1 << ASRGR_VALID_PCM_INFO_OFFS) + +#define ASRGR_SAMPLE_FREQ_OFFS 8 +#define ASRGR_SAMPLE_FREQ_MASK (0xf << ASRGR_SAMPLE_FREQ_OFFS) + +#define ASRGR_NON_PCM_OFFS 14 +#define ASRGR_NON_PCM_MASK (1 << ASRGR_NON_PCM_OFFS) + +/* MV_AUDIO_I2S_REC_CTRL_REG*/ +#define AIRCR_I2S_RECORD_JUSTF_OFFS 26 +#define AIRCR_I2S_RECORD_JUSTF_MASK (0xf << AIRCR_I2S_RECORD_JUSTF_OFFS) + +#define AIRCR_I2S_SAMPLE_SIZE_OFFS 30 +#define AIRCR_I2S_SAMPLE_SIZE_MASK (0x3 << AIRCR_I2S_SAMPLE_SIZE_OFFS) + +#endif /* __INCMVAudioRegsH */ + diff --git a/board/mv_feroceon/mv_hal/audio/mvCompVer.txt b/board/mv_feroceon/mv_hal/audio/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/audio/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/buffalo/BuffaloWol.c b/board/mv_feroceon/mv_hal/buffalo/BuffaloWol.c new file mode 100644 index 0000000..6363787 --- /dev/null +++ b/board/mv_feroceon/mv_hal/buffalo/BuffaloWol.c @@ -0,0 +1,862 @@ +#if defined(__KERNEL__) && !defined(MV_UBOOT) +/* include file on kernel */ +#include +#include + +#include "BuffaloGpio.h" +#include "eth-phy/mvEthPhy.h" +#include "eth-phy/mvEthPhyRegs.h" +#include "eth/mvEth.h" +#include "eth/gbe/mvEthGbe.h" +#include "eth/gbe/mvEthRegs.h" +#include "BuffaloWol.h" +#else +/* include file on u-boot */ +#include "eth-phy/mvEthPhy.h" +#include "eth-phy/mvEthPhyRegs.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "eth/mvEth.h" +#include "eth/gbe/mvEthGbe.h" +#include "eth/gbe/mvEthRegs.h" +#include "BuffaloWol.h" + +#include +#endif + + +#if defined(__KERNEL__) && !defined(MV_UBOOT) +#define DEBUG(fmt, args...) printk(fmt, ##args) +typedef unsigned char uchar; + +/* + * Ethernet header + */ +typedef struct { + uchar et_dest[6]; /* Destination node */ + uchar et_src[6]; /* Source node */ + ushort et_protlen; /* Protocol or length */ + uchar et_dsap; /* 802 DSAP */ + uchar et_ssap; /* 802 SSAP */ + uchar et_ctl; /* 802 control */ + uchar et_snap1; /* SNAP */ + uchar et_snap2; + uchar et_snap3; + ushort et_prot; /* 802 protocol */ +} Ethernet_t; + +#define ETHER_HDR_SIZE 14 /* Ethernet header size */ +#define E802_HDR_SIZE 22 /* 802 ethernet header size */ + +typedef ulong IPaddr_t; + +/* + * Internet Protocol (IP) header. + */ +typedef struct { + uchar ip_hl_v; /* header length and version */ + uchar ip_tos; /* type of service */ + ushort ip_len; /* total length */ + ushort ip_id; /* identification */ + ushort ip_off; /* fragment offset field */ + uchar ip_ttl; /* time to live */ + uchar ip_p; /* protocol */ + ushort ip_sum; /* checksum */ + IPaddr_t ip_src; /* Source IP address */ + IPaddr_t ip_dst; /* Destination IP address */ + ushort udp_src; /* UDP source port */ + ushort udp_dst; /* UDP destination port */ + ushort udp_len; /* Length of UDP packet */ + ushort udp_xsum; /* Checksum */ +} IP_t; + +#define IP_HDR_SIZE_NO_UDP (sizeof (IP_t) - 8) +#define IP_HDR_SIZE (sizeof (IP_t)) + +#else +#define DEBUG(fmt, args...) printf(fmt, ##args) +#endif + +#define FLAG_BUFFALO_WOL_UCAST (0 << 0) +#define FLAG_BUFFALO_WOL_BCAST (1 << 0) +#define FLAG_BUFFALO_WITH_UDP_H (0 << 1) +#define FLAG_BUFFALO_WITHOUT_UDP_H (1 << 1) +#define FLAG_BUFFALO_DISACTIVE_PACKET (0 << 2) +#define FLAG_BUFFALO_ACTIVE_PACKET (1 << 2) + +struct bfWolSupportPhyList_st { + MV_U32 OUI; + MV_U16 ModelNumber; +}; + +struct bfWolInfo_st{ + char name[32]; + MV_U8 packet_type; + MV_U16 port_num; +}; + +static const struct bfWolSupportPhyList_st bfWolSupportPhyList[] = { + {0x005043, 0x29}, /* Marvell, 1318 */ +}; + +static const struct bfWolInfo_st bfWolPacketType[] = { + {"active", (FLAG_BUFFALO_ACTIVE_PACKET | FLAG_BUFFALO_WOL_BCAST), 0x0009}, /* broadcast active packet */ + {"active", (FLAG_BUFFALO_ACTIVE_PACKET), 0x0009}, /* unicast active packet */ + {"wol", (FLAG_BUFFALO_ACTIVE_PACKET | FLAG_BUFFALO_WOL_BCAST), 0x0900}, /* broadcast wol packet */ + {"wol", (FLAG_BUFFALO_ACTIVE_PACKET), 0x0900}, /* unicast wol packet */ + {"wol", (FLAG_BUFFALO_ACTIVE_PACKET | FLAG_BUFFALO_WITHOUT_UDP_H), 0}, /* unicast udp header less wol packet */ + {"wol", (FLAG_BUFFALO_ACTIVE_PACKET | FLAG_BUFFALO_WOL_BCAST | FLAG_BUFFALO_WITHOUT_UDP_H), 0}, /* broadcast udp header less wol packet */ +}; + +#define MAX_WOL_PHY_LIST ((sizeof(bfWolSupportPhyList)) / (sizeof(bfWolSupportPhyList[0]))) +#define MAX_WOL_TYPE ((sizeof(bfWolPacketType)) / (sizeof(bfWolPacketType[0]))) + +/* used for return buffer of bfGetWolPatternString */ +static char bfWolPatternString[128]; + +#if defined(__KERNEL__) && !defined(MV_UBOOT) +/******************************************************************************* +* mvEthPhyDisableAN - Disable Phy Auto-Negotiation and set forced Speed and Duplex +* +* DESCRIPTION: +* This function disable AN and set duplex and speed. +* +* INPUT: +* phyAddr - Phy address. +* speed - port speed. 0 - 10 Mbps, 1-100 Mbps, 2 - 1000 Mbps +* duplex - port duplex. 0 - Half duplex, 1 - Full duplex +* +* OUTPUT: +* None. +* +* RETURN: MV_OK - Success +* MV_FAIL - Failure +* +*******************************************************************************/ +MV_STATUS mvEthPhyDisableAN(MV_U32 phyAddr, int speed, int duplex) +{ + MV_U16 phyRegData; + + if(mvEthPhyRegRead (phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK) + return MV_FAIL; + + switch(speed) + { + case 0: /* 10 Mbps */ + phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK; + phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK; + break; + + case 1: /* 100 Mbps */ + phyRegData |= ETH_PHY_CTRL_SPEED_LSB_MASK; + phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK; + break; + + case 2: /* 1000 Mbps */ + phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK; + phyRegData |= ETH_PHY_CTRL_SPEED_MSB_MASK; + break; + + default: + mvOsOutput("Unexpected speed = %d\n", speed); + return MV_FAIL; + } + + switch(duplex) + { + case 0: /* half duplex */ + phyRegData &= ~ETH_PHY_CTRL_DUPLEX_MASK; + break; + + case 1: /* full duplex */ + phyRegData |= ETH_PHY_CTRL_DUPLEX_MASK; + break; + + default: + mvOsOutput("Unexpected duplex = %d\n", duplex); + } + /* Clear bit 12 to Disable autonegotiation of the PHY */ + phyRegData &= ~ETH_PHY_CTRL_AN_ENABLE_MASK; + + /* Clear bit 9 to DISABLE, Restart autonegotiation of the PHY */ + phyRegData &= ~ETH_PHY_CTRL_AN_RESTART_MASK; + mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData); + + return MV_OK; +} +#endif + + + +/******************************************************************************* +* bfIsSupportWol +* +* DESCRIPTION: +* Check specified ethPortNum support WOL or not. +* +* INPUT: +* ethPortNum : port No. to check. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE : Specified eth port suports WOL function. +* MV_FALSE : Specified eth port doesn't support WOL function. +* +*******************************************************************************/ +MV_BOOL +bfIsSupportWol(MV_U32 ethPortNum) +{ + MV_U8 i = 0; + MV_U16 old_page; + MV_U16 reg; + MV_U32 OUI = 0; + MV_U16 ModelNumber = 0; + + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page); + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 0); + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 2, ®); + OUI |= (MV_U32)(reg << 6); + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 3, ®); + OUI |= ((reg & 0xFC00) >> 10); + ModelNumber = ((reg & 0x03F0) >> 4); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page); + + for(i = 0; i < MAX_WOL_PHY_LIST; i++) + { + if(bfWolSupportPhyList[i].OUI == OUI && bfWolSupportPhyList[i].ModelNumber == ModelNumber) + return MV_TRUE; + } + return MV_FALSE; +} + +/******************************************************************************* +* bfResetEthPhy +* +* DESCRIPTION: +* Do reset eth phy. +* +* INPUT: +* ethPortNum : port No. to to reset. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void +bfResetEthPhy(MV_U32 ethPortNum) +{ + DEBUG("Resetting EthPhy\n"); + mvEthPhyReset(mvBoardPhyAddrGet(ethPortNum), 1000); +} + +/******************************************************************************* +* bfControlWolInterrupt +* +* DESCRIPTION: +* Control WOL interrupt status (to Enable / Disable). +* +* INPUT: +* ethPortNum : port No. to control interrupt status. +* ope : specify operation mode to do. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void +bfControlWolInterrupt(MV_U32 ethPortNum, MV_U8 ope) +{ + MV_U16 reg; + MV_U16 old_page; + + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page); /* backup present page information */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,3); /* change to Page 3 */ + + if(ope == FLAG_BUFFALO_WOL_INTERRUPT_ENABLE) + { + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16, ®); + reg &= ~0x0fff; + reg |= 0x08AA; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16, reg); /* change led[0][1] off (force Hi-Z)*/ + + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),18, ®); + reg |= 0x0880; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),18, reg); /* change led[2] to intn pin */ + } + else + { + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16, ®); + reg &= ~0x0fff; + reg |= 0x0911; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, reg); + + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),18, ®); + reg &= ~0x0880; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 18, reg); + } + + /* change to Page 0*/ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0); + /*WOL Interrupt Enable*/ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),18, ®); + if(ope == FLAG_BUFFALO_WOL_INTERRUPT_ENABLE) + reg |= 0x80 ; + else + reg &= ~(0x80); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),18,reg); + + if(ope == FLAG_BUFFALO_WOL_INTERRUPT_ENABLE) + mvEthPhyDisableAN(mvBoardPhyAddrGet(ethPortNum), 0, 0); + else + mvEthPhyRestartAN(mvBoardPhyAddrGet(ethPortNum), 1000); + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page); /* restore previous page */ +} + +/******************************************************************************* +* bfSetPowerSaveMode +* +* DESCRIPTION: +* Do settings to reduce power consumption during WOL mode. +* +* INPUT: +* ethPortNum : port No. to set to WOL mode. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void +bfSetPowerSaveMode(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /*RGMII BUS treansistor OFF*/ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x2); /* change to Page 2 */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),24, ®); + reg &= ~(BIT8 | BIT9 | BIT10 | BIT2 | BIT1 | BIT0); + reg |= BIT6 ; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,reg); + + /*STOP CLK125 OUTPUT */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 16, ®); + reg |= ( BIT2 | BIT1 | BIT11| BIT12); + reg &= ~BIT3 ; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, reg); + /* change to Page 0*/ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 0); + +#if defined(energy_detect) + /*RGMII STOP for Power Saving */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 16, ®); + reg |= (BIT2 | BIT8 | BIT9) ; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, reg); +#endif +} + + +/******************************************************************************* +* bfSetWolMagicWaitMode +* +* DESCRIPTION: +* Set specified ethernet port to Wake on Lan waiting mode. +* +* INPUT: +* ethPortNum : port No. to set to WOL mode. +* phyAddr : Phy address. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_BOOL +bfSetWolMagicWaitMode(MV_U32 ethPortNum) +{ + MV_U16 reg ; + unsigned char MacAddr[6]; + + if(bfIsSupportWol(ethPortNum) == MV_FALSE) + return MV_FALSE; + + memset(MacAddr, 0, sizeof(MacAddr)); + mvEthMacAddrGet(ethPortNum, MacAddr); + + /* Set WOL mode */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,17); /* change to Page 17 */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x5500); /* 0101 0101 0000 0000 */ + + /* set wol mac address from env data */ + reg = (MacAddr[4]) | (MacAddr[5] << 8) ; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),23,reg); + reg = (MacAddr[2]) | (MacAddr[3] << 8) ; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,reg); + reg = (MacAddr[0]) | (MacAddr[1] << 8) ; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),25,reg); + + /*Enable Magic Packet*/ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x5500); + + bfControlWolInterrupt(ethPortNum, FLAG_BUFFALO_WOL_INTERRUPT_ENABLE); + bfSetPowerSaveMode(ethPortNum); + return MV_TRUE; +} + +/******************************************************************************* +* bfSetFrameEventWol +* +* DESCRIPTION: +* generate frame pattern used to matching. +* +* INPUT: +* frame : buffer to store generated frame pattern. +* mask : buffer to stora generated mask pattern. +* pmacAddr : MAC address to generate frame pattern. +* bfWPT : flags to generate frame pattern. +* debug : debug flag. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_U8 +bfSetFrameEventWol(MV_U8 *frame, MV_U8 *mask, MV_U8 *pMacAddr, const struct bfWolInfo_st *bfWPT, int debug) +{ + MV_U8 i; + MV_U8 magic_len = 0; + MV_U8 frame_match_len = 0; + + Ethernet_t *eth_h = (Ethernet_t *)&frame[0]; + Ethernet_t *eth_h_mask = (Ethernet_t *)&mask[0]; + + IP_t *ip_h = (IP_t *)&frame[ETHER_HDR_SIZE]; + IP_t *ip_h_mask = (IP_t *)&mask[ETHER_HDR_SIZE]; + + MV_U8 *data = NULL; + MV_U8 *data_mask = NULL; + + for(i = 0; i < 6; i++) + { + if(bfWPT->packet_type & FLAG_BUFFALO_WOL_BCAST) + eth_h->et_dest[i] = 0xFF; + else + eth_h->et_dest[i] = pMacAddr[i]; + memset(&(eth_h_mask->et_dest[i]), 0xFF, sizeof(eth_h_mask->et_dest[i])); + } + + if(bfWPT->packet_type & FLAG_BUFFALO_WITHOUT_UDP_H) + { + data = &frame[ETHER_HDR_SIZE]; + data_mask = &mask[ETHER_HDR_SIZE]; + magic_len = 128 - ETHER_HDR_SIZE; + frame_match_len = ETHER_HDR_SIZE; + } + else + { + data = &frame[ETHER_HDR_SIZE + IP_HDR_SIZE]; + data_mask = &mask[ETHER_HDR_SIZE + IP_HDR_SIZE]; + ip_h->udp_dst = htons(bfWPT->port_num); + memset(&(ip_h_mask->udp_dst), 0xFF, sizeof(ip_h_mask->udp_dst)); + magic_len = 128 - ETHER_HDR_SIZE - IP_HDR_SIZE; + frame_match_len = ETHER_HDR_SIZE + IP_HDR_SIZE; + } + if(magic_len > 6 * 17) magic_len = 6*17; + frame_match_len += magic_len - 1; + + if(debug) DEBUG("matching len = %d\n", magic_len); + for(i = 0; i < magic_len ; i ++) + { + if((i < 6) && (bfWPT->packet_type & FLAG_BUFFALO_ACTIVE_PACKET)) + data[i] = 0xFF; + else + data[i] = pMacAddr[i % 6]; + memset(&(data_mask[i]), -1, sizeof(data_mask[i])); + } + + return frame_match_len; +} + +/******************************************************************************* +* bfDumpSramData +* +* DESCRIPTION: +* Set matching frame pattern and mask information to SRAM of EthPhy. +* +* INPUT: +* ethPortNum : No. of target ethernet port. +* num_frame_pattern: No. of frame pattern to display dump result. +* +* OUTPUT: +* SRAM dump result. +* +* RETURN: +* None. +* +*******************************************************************************/ +void +bfDumpSramData(MV_U32 ethPortNum, MV_U8 num_frame_pattern) +{ + MV_U8 i; + MV_U16 old_page; + MV_U16 reg; + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page); /* backup present page status */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,17); /* change to Page 17 */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 16, ®); + + DEBUG("verifying SRAM value. pattern=%d\n", num_frame_pattern); + if(reg & (1 << num_frame_pattern)) + DEBUG("patern %d is Enabled\n", num_frame_pattern); + else + DEBUG("patern %d is Disabled\n", num_frame_pattern); + + switch(num_frame_pattern) + { + case 0: + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 21, ®); + break; + case 1: + case 2: + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 20, ®); + break; + case 3: + case 4: + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 19, ®); + break; + case 5: + case 6: + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 18, ®); + break; + default: + return ; + } + if(num_frame_pattern == 0 || num_frame_pattern == 1 || num_frame_pattern == 3 || num_frame_pattern == 5) + DEBUG("Matching frame pattern length = %d Bytes\n", (reg & 0x007F) + 1); + else if(num_frame_pattern == 2 || num_frame_pattern == 4 || num_frame_pattern == 6) + DEBUG("Matching frame pattern length = %d Bytes\n", (((reg >> 7) & 0x007F) + 1)); + + for(i = 0; i < 128; i++) + { + if((i!= 0) && ((i % 0x10) == 0)) + DEBUG("\n0x%02x : ", (i / 0x10) * 0x10); + else if (((i % 0x10) != 0) && ((i % 0x08) ==0)) + DEBUG(" "); + else if(i == 0) + DEBUG("\n0x%02x : ", 0); + + /* read data from SRAM */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 26, 0x0800 | i | (num_frame_pattern << 7)); /* 0000 0100 0000 0000 | i */ + + /* read value recorded in SRAM */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 28, ®); + if(reg & 0x0100) + { + DEBUG("%02x ", reg & 0xFF); + } + else + { + DEBUG("-- "); + } + } + DEBUG("\n"); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page); /* restore previous page status */ +} + +/******************************************************************************* +* bfWriteFramePaternToSram +* +* DESCRIPTION: +* Set matching frame pattern and mask information to SRAM of EthPhy. +* +* INPUT: +* ethPortNum : No. of target ethernet port. +* frame : 128 byte frame pattern +* mask : 128 byte mask information. which frame byte is used to matching. +* num_frame_pattern: No. of frame pattern to set frame pattern. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void +bfWriteFramePaternToSram(MV_U32 ethPortNum, MV_U8 *frame, MV_U8 *mask, MV_U8 num_frame_pattern) +{ + MV_U16 i; + MV_U16 reg; + MV_U16 old_page; + + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 17); + + for(i = 0; i < 128; i++) + { + /* set value to 17.27 */ + reg = ((mask[i] > 0)? 1:0) << 8 | frame[i]; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 27, reg); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 26, 0x0400 | i | (num_frame_pattern << 7)); /* 0000 0100 0000 0000 | i */ + } + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page); +} + +/******************************************************************************* +* bfWriteWolFrameMatchingLen +* +* DESCRIPTION: +* Set wol frame matching length to 17.18, 17.19, 17.20 or 17.21 +* +* INPUT: +* ethPortNum : No. of target ethernet port. +* num_frame_patern : No. of frame patern to set matching length. +* matching_len : matching length to set. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void +bfWriteWolFrameMatchingLen(MV_U32 ethPortNum, MV_U8 num_frame_pattern, MV_U8 matching_len) +{ + MV_U16 reg; + MV_U16 old_page; + + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 17); + + switch(num_frame_pattern) + { + case 0: + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 21, matching_len); + break; + case 1: + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 20, ®); + reg &= ~(0x007F); + reg |= matching_len; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 20, reg); + break; + case 2: + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 20, ®); + reg &= ~(0x3F80); + reg |= (matching_len << 7); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 20, reg); + break; + case 3: + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 19, ®); + reg &= ~(0x007F); + reg |= matching_len; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 19, reg); + break; + case 4: + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 19, ®); + reg &= ~(0x3F80); + reg |= (matching_len << 7); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 19, reg); + break; + case 5: + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 18, ®); + reg &= ~(0x007F); + reg |= matching_len; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 18, reg); + break; + case 6: + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 18, ®); + reg &= ~(0x3F80); + reg |= (matching_len << 7); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 18, reg); + break; + } + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page); +} + +/******************************************************************************* +* bfSetWolFrameWaitMode +* +* DESCRIPTION: +* Set wol frame wait mode. +* +* INPUT: +* ethPortNum : No. of target ethernet port. +* pMacAddr : MAC address to set. +* debug : debug flag(for verbose output) +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE : success to set wol mode. +* MV_FALSE : failed to set wol mode. +* +*******************************************************************************/ +MV_BOOL +bfSetWolFrameWaitMode(MV_U32 ethPortNum, int debug) +{ + MV_U16 old_page; + MV_U16 reg; + MV_U16 enabling_pattern = 0; + MV_U8 i; + MV_U8 frame[128]; + MV_U8 mask[128]; + MV_U8 matching_len = 128; + unsigned char MacAddr[6]; + + if(bfIsSupportWol(ethPortNum) == MV_FALSE) + return MV_FALSE; + +#if defined(__KERNEL__) && !defined(MV_UBOOT) + DEBUG("Setting WOL ... "); + if(!bfGppInRegBitTest(BIT_PWRAUTO_SW)) + { + DEBUG("Switch status is not AUTO\n"); + return MV_FALSE; + } +#endif + + memset(MacAddr, 0, sizeof(MacAddr)); + mvEthMacAddrGet(ethPortNum, MacAddr); + + bfControlWolInterrupt(ethPortNum, FLAG_BUFFALO_WOL_INTERRUPT_DISABLE); + + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page); /* backup present page status */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 17); /* change to Page 17 */ + /* Disabling WOL Match Enable flags */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 16, ®); + reg &= ~(0xC07F); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, reg); + + for(i = 0; i < MAX_WOL_TYPE; i++) + { + memset(frame, 0, sizeof(frame)); + memset(mask, 0, sizeof(mask)); + matching_len = bfSetFrameEventWol(frame, mask, MacAddr, &(bfWolPacketType[i]), debug); + bfWriteFramePaternToSram(ethPortNum, frame, mask, i); + bfWriteWolFrameMatchingLen(ethPortNum, i, matching_len); + enabling_pattern |= (1 << i); + } + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, enabling_pattern); /* 1001 0000 0000 0011 */ + + if(debug) + for (i = 0; i < 7; i++) + bfDumpSramData(ethPortNum, i); + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, 0x9000 | enabling_pattern); /* 1001 0000 0000 0011 */ + + bfControlWolInterrupt(ethPortNum, FLAG_BUFFALO_WOL_INTERRUPT_ENABLE); + bfSetPowerSaveMode(ethPortNum); + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page); /* restore previous page status */ +#if defined(__KERNEL__) && !defined(MV_UBOOT) + DEBUG("Success\n"); +#endif + return MV_TRUE; +} + +/******************************************************************************* +* bfGetWolPatternString +* +* DESCRIPTION: +* generate string to send kernel from the information of which frame pattern matched. +* +* INPUT: +* wol_stat : register value of 17.17 +* +* OUTPUT: +* None. +* +* RETURN: +* pointer to string. +* +*******************************************************************************/ +char *bfGetWolPatternString(MV_U16 wol_stat) +{ + MV_U8 i; + + memset(bfWolPatternString, 0, sizeof(bfWolPatternString)); + for(i = 0; i < MAX_WOL_TYPE; i++) + { + if(wol_stat & (1 << i) && (strstr(bfWolPatternString, bfWolPacketType[i].name) == 0)) { + if(strlen(bfWolPatternString) == 0) + sprintf(bfWolPatternString, "%s", bfWolPacketType[i].name); + else + sprintf(bfWolPatternString, ",%s", bfWolPacketType[i].name); + } + } + + return (bfWolPatternString[0])? bfWolPatternString : NULL; +} + +/******************************************************************************* +* bfGetWolInterruptStatus +* +* DESCRIPTION: +* Get interrupt status +* +* INPUT: +* ethPortNum : No. of target ethernet port. +* +* OUTPUT: +* None. +* +* RETURN: +* register value of 17.17(which frame pattern received) +* +*******************************************************************************/ +MV_U16 bfGetWolInterruptStatus(MV_U32 ethPortNum, int debug) +{ + MV_U16 old_page; + MV_U16 reg; + + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, &old_page); /* backup present page status */ + + if(debug) + { + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 17); + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 17, ®); + DEBUG("WOL status(17.17)=0x%04x\n", reg); + } + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 0); + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 19, ®); + if(debug) + { + DEBUG("WOL status(0.19)=0x%04x\n", reg); + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 23, ®); + DEBUG("Global Interrupt Status(0.23)=0x%04x\n", reg); + } + + if(reg & 0x0080) + { + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 17); + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 17, ®); + } + else + { + reg = 0; + } + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, old_page); /* restore previous page status */ + + return (reg & 0x003F); +} + + diff --git a/board/mv_feroceon/mv_hal/buffalo/BuffaloWol.h b/board/mv_feroceon/mv_hal/buffalo/BuffaloWol.h new file mode 100644 index 0000000..aaf97f9 --- /dev/null +++ b/board/mv_feroceon/mv_hal/buffalo/BuffaloWol.h @@ -0,0 +1,22 @@ +#if defined(__BUFFALOWOL_H__) +#else +#define __BUFFALOWOL_H__ + +#define FLAG_BUFFALO_WOL_INTERRUPT_ENABLE 1 +#define FLAG_BUFFALO_WOL_INTERRUPT_DISABLE 0 + +#if defined(__KERNEL__) && !defined(MV_UBOOT) + +#else +/* on u-boot */ +void bfResetEthPhy(MV_U32 ethPortNum); +void bfControlWolInterrupt(MV_U32 ethPortNum, MV_U8 ope); +MV_BOOL bfIsSupportWol(MV_U32 ethPortNum); +MV_BOOL bfSetWolMagicWaitMode(MV_U32 ethPortNum); +MV_BOOL bfSetWolFrameWaitMode(MV_U32 ethPortNum, int debug); +MV_U16 bfGetWolInterruptStatus(MV_U32 ethPortNum, int debug); +void bfPhyPowerUp(MV_U32 ethPortNum); +char *bfGetWolPatternString(MV_U16 wol_stat); +#endif // defined(__KERNEL__) && !defined(MV_UBOOT) + +#endif diff --git a/board/mv_feroceon/mv_hal/cesa/AES/mvAes.h b/board/mv_feroceon/mv_hal/cesa/AES/mvAes.h new file mode 100644 index 0000000..07a8601 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/AES/mvAes.h @@ -0,0 +1,62 @@ +/* mvAes.h v2.0 August '99 + * Reference ANSI C code + */ + +/* AES Cipher header file for ANSI C Submissions + Lawrence E. Bassham III + Computer Security Division + National Institute of Standards and Technology + + April 15, 1998 + + This sample is to assist implementers developing to the Cryptographic +API Profile for AES Candidate Algorithm Submissions. Please consult this +document as a cross-reference. + + ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE +MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH +THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT +BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE +IMPLEMENTATION SPECIFIC INFORMATION. +*/ + +/* Includes: + Standard include files +*/ + +#include "mvOs.h" + + +/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ + +/* Key direction is invalid, e.g., unknown value */ +#define AES_BAD_KEY_DIR -1 + +/* Key material not of correct length */ +#define AES_BAD_KEY_MAT -2 + +/* Key passed is not valid */ +#define AES_BAD_KEY_INSTANCE -3 + +/* Params struct passed to cipherInit invalid */ +#define AES_BAD_CIPHER_MODE -4 + +/* Cipher in wrong state (e.g., not initialized) */ +#define AES_BAD_CIPHER_STATE -5 + +#define AES_BAD_CIPHER_INSTANCE -7 + + +/* Function protoypes */ +/* CHANGED: makeKey(): parameter blockLen added + this parameter is absolutely necessary if you want to + setup the round keys in a variable block length setting + cipherInit(): parameter blockLen added (for obvious reasons) + */ +int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); +int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *plain, int numBlocks, MV_U32 *cipher); +int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *plain, int numBlocks, MV_U32 *cipher); + + diff --git a/board/mv_feroceon/mv_hal/cesa/AES/mvAesAlg.c b/board/mv_feroceon/mv_hal/cesa/AES/mvAesAlg.c new file mode 100644 index 0000000..a65dc28 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/AES/mvAesAlg.c @@ -0,0 +1,317 @@ +/* rijndael-alg-ref.c v2.0 August '99 + * Reference ANSI C code + * authors: Paulo Barreto + * Vincent Rijmen, K.U.Leuven + * + * This code is placed in the public domain. + */ + +#include "mvOs.h" + +#include "mvAesAlg.h" + +#include "mvAesBoxes.dat" + + +MV_U8 mul1(MV_U8 aa, MV_U8 bb); +void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); +void ShiftRow128Enc(MV_U8 a[4][MAXBC]); +void ShiftRow128Dec(MV_U8 a[4][MAXBC]); +void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); +void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); +void InvMixColumn(MV_U8 a[4][MAXBC]); + + +#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) + +MV_U8 mul1(MV_U8 aa, MV_U8 bb) +{ + return mask[bb] & Alogtable[aa + Logtable[bb]]; +} + + +void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) +{ + /* Exor corresponding text input and round key input bytes + */ + ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; + ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; + ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; + ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; + +} + +void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { + /* Row 0 remains unchanged + * The other three rows are shifted a variable amount + */ + MV_U8 tmp[MAXBC]; + + tmp[0] = a[1][1]; + tmp[1] = a[1][2]; + tmp[2] = a[1][3]; + tmp[3] = a[1][0]; + + ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[1][0] = tmp[0]; + a[1][1] = tmp[1]; + a[1][2] = tmp[2]; + a[1][3] = tmp[3]; + */ + tmp[0] = a[2][2]; + tmp[1] = a[2][3]; + tmp[2] = a[2][0]; + tmp[3] = a[2][1]; + + ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[2][0] = tmp[0]; + a[2][1] = tmp[1]; + a[2][2] = tmp[2]; + a[2][3] = tmp[3]; + */ + tmp[0] = a[3][3]; + tmp[1] = a[3][0]; + tmp[2] = a[3][1]; + tmp[3] = a[3][2]; + + ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[3][0] = tmp[0]; + a[3][1] = tmp[1]; + a[3][2] = tmp[2]; + a[3][3] = tmp[3]; + */ +} + +void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { + /* Row 0 remains unchanged + * The other three rows are shifted a variable amount + */ + MV_U8 tmp[MAXBC]; + + tmp[0] = a[1][3]; + tmp[1] = a[1][0]; + tmp[2] = a[1][1]; + tmp[3] = a[1][2]; + + ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[1][0] = tmp[0]; + a[1][1] = tmp[1]; + a[1][2] = tmp[2]; + a[1][3] = tmp[3]; + */ + + tmp[0] = a[2][2]; + tmp[1] = a[2][3]; + tmp[2] = a[2][0]; + tmp[3] = a[2][1]; + + ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[2][0] = tmp[0]; + a[2][1] = tmp[1]; + a[2][2] = tmp[2]; + a[2][3] = tmp[3]; + */ + + tmp[0] = a[3][1]; + tmp[1] = a[3][2]; + tmp[2] = a[3][3]; + tmp[3] = a[3][0]; + + ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[3][0] = tmp[0]; + a[3][1] = tmp[1]; + a[3][2] = tmp[2]; + a[3][3] = tmp[3]; + */ +} + +void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { + /* Replace every byte of the input by the byte at that place + * in the nonlinear S-box + */ + int i, j; + + for(i = 0; i < 4; i++) + for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; +} + +void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { + /* Mix the four bytes of every column in a linear way + */ + MV_U8 b[4][MAXBC]; + int i, j; + + for(j = 0; j < 4; j++){ + b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; + b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; + b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; + b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; + } + for(i = 0; i < 4; i++) + /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ + ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; +} + +void InvMixColumn(MV_U8 a[4][MAXBC]) { + /* Mix the four bytes of every column in a linear way + * This is the opposite operation of Mixcolumn + */ + MV_U8 b[4][MAXBC]; + int i, j; + + for(j = 0; j < 4; j++){ + b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); + b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); + b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); + b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); + } + for(i = 0; i < 4; i++) + /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ + ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; +} + +int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) +{ + /* Calculate the necessary round keys + * The number of calculations depends on keyBits and blockBits + */ + int KC, BC, ROUNDS; + int i, j, t, rconpointer = 0; + MV_U8 tk[4][MAXKC]; + + switch (keyBits) { + case 128: KC = 4; break; + case 192: KC = 6; break; + case 256: KC = 8; break; + default : return (-1); + } + + switch (blockBits) { + case 128: BC = 4; break; + case 192: BC = 6; break; + case 256: BC = 8; break; + default : return (-2); + } + + switch (keyBits >= blockBits ? keyBits : blockBits) { + case 128: ROUNDS = 10; break; + case 192: ROUNDS = 12; break; + case 256: ROUNDS = 14; break; + default : return (-3); /* this cannot happen */ + } + + + for(j = 0; j < KC; j++) + for(i = 0; i < 4; i++) + tk[i][j] = k[i][j]; + t = 0; + /* copy values into round key array */ + for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) + for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; + + while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ + /* calculate new values */ + for(i = 0; i < 4; i++) + tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; + tk[0][0] ^= rcon[rconpointer++]; + + if (KC != 8) + for(j = 1; j < KC; j++) + for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; + else { + for(j = 1; j < KC/2; j++) + for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; + for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; + for(j = KC/2 + 1; j < KC; j++) + for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; + } + /* copy values into round key array */ + for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) + for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; + } + + return 0; +} + + + +int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) +{ + /* Encryption of one block. + */ + int r, BC, ROUNDS; + + BC = 4; + ROUNDS = rounds; + + /* begin with a key addition + */ + + KeyAddition(a,rk[0],BC); + + /* ROUNDS-1 ordinary rounds + */ + for(r = 1; r < ROUNDS; r++) { + Substitution(a,S); + ShiftRow128Enc(a); + MixColumn(a, rk[r]); + /*KeyAddition(a,rk[r],BC);*/ + } + + /* Last round is special: there is no MixColumn + */ + Substitution(a,S); + ShiftRow128Enc(a); + KeyAddition(a,rk[ROUNDS],BC); + + return 0; +} + + +int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) +{ + int r, BC, ROUNDS; + + BC = 4; + ROUNDS = rounds; + + /* To decrypt: apply the inverse operations of the encrypt routine, + * in opposite order + * + * (KeyAddition is an involution: it 's equal to its inverse) + * (the inverse of Substitution with table S is Substitution with the inverse table of S) + * (the inverse of Shiftrow is Shiftrow over a suitable distance) + */ + + /* First the special round: + * without InvMixColumn + * with extra KeyAddition + */ + KeyAddition(a,rk[ROUNDS],BC); + ShiftRow128Dec(a); + Substitution(a,Si); + + /* ROUNDS-1 ordinary rounds + */ + for(r = ROUNDS-1; r > 0; r--) { + KeyAddition(a,rk[r],BC); + InvMixColumn(a); + ShiftRow128Dec(a); + Substitution(a,Si); + + } + + /* End with the extra key addition + */ + + KeyAddition(a,rk[0],BC); + + return 0; +} + diff --git a/board/mv_feroceon/mv_hal/cesa/AES/mvAesAlg.h b/board/mv_feroceon/mv_hal/cesa/AES/mvAesAlg.h new file mode 100644 index 0000000..ec81e40 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/AES/mvAesAlg.h @@ -0,0 +1,19 @@ +/* rijndael-alg-ref.h v2.0 August '99 + * Reference ANSI C code + * authors: Paulo Barreto + * Vincent Rijmen, K.U.Leuven + */ +#ifndef __RIJNDAEL_ALG_H +#define __RIJNDAEL_ALG_H + +#define MAXBC (128/32) +#define MAXKC (256/32) +#define MAXROUNDS 14 + + +int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); + +int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); +int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); + +#endif /* __RIJNDAEL_ALG_H */ diff --git a/board/mv_feroceon/mv_hal/cesa/AES/mvAesApi.c b/board/mv_feroceon/mv_hal/cesa/AES/mvAesApi.c new file mode 100644 index 0000000..b432dc6 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/AES/mvAesApi.c @@ -0,0 +1,312 @@ +/* rijndael-api-ref.c v2.1 April 2000 + * Reference ANSI C code + * authors: v2.0 Paulo Barreto + * Vincent Rijmen, K.U.Leuven + * v2.1 Vincent Rijmen, K.U.Leuven + * + * This code is placed in the public domain. + */ +#include "mvOs.h" + +#include "mvAes.h" +#include "mvAesAlg.h" + + +/* Defines: + Add any additional defines you need +*/ + +#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ +#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ +#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ + + +int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) +{ + MV_U8 W[MAXROUNDS+1][4][MAXBC]; + MV_U8 k[4][MAXKC]; + MV_U8 j; + int i, rounds, KC; + + if (expandedKey == NULL) + { + return AES_BAD_KEY_INSTANCE; + } + + if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) + { + return AES_BAD_KEY_MAT; + } + + if (keyMaterial == NULL) + { + return AES_BAD_KEY_MAT; + } + + /* initialize key schedule: */ + for(i=0; i= 3) +MV_U32 cesaChainLength = 0; +int chainReqNum = 0; +MV_U32 chainIndex = 0; +MV_CESA_REQ* pNextActiveChain = 0; +MV_CESA_REQ* pEndCurrChain = 0; +MV_BOOL isFirstReq = MV_TRUE; +#endif + +static INLINE MV_U8* mvCesaSramAddrGet(void) +{ +#ifdef MV_CESA_NO_SRAM + return (MV_U8*)cesaSramVirtPtr; +#else + return (MV_U8*)cesaCryptEngBase; +#endif /* MV_CESA_NO_SRAM */ +} + +static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) +{ +#ifdef MV_CESA_NO_SRAM + return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); +#else + return (MV_ULONG)pSramVirt; +#endif /* MV_CESA_NO_SRAM */ +} + +/* Internal Function prototypes */ + +static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, + int cryptoOffset, int ivOffset, int cryptoLength, + int macOffset, int digestOffset, int macLength, int macTotalLen, + MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); + +static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); + +static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, + MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, + int offset, int copySize, MV_BOOL skipFlush); + +static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, + unsigned char innerIV[], unsigned char outerIV[]); + +static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, + int macDataSize); + +static MV_CESA_COMMAND* mvCesaCtrModeInit(void); + +static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); +static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); +static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); + +static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); +static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); + +static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); +static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); + +static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, + int cryptoOffset, int macOffset, + int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); +static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); + +/* Go to the next request in the request queue */ +static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) +{ + if(pReq == pCesaReqLast) + return pCesaReqFirst; + + return pReq+1; +} + +#if (MV_CESA_VERSION >= 3) +/* Go to the previous request in the request queue */ +static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) +{ + if(pReq == pCesaReqFirst) + return pCesaReqLast; + + return pReq-1; +} + +#endif + + +static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) +{ + int frag; + +#if (MV_CESA_VERSION >= 3) + pReq->state = MV_CESA_CHAIN; +#else + pReq->state = MV_CESA_PROCESS; +#endif + cesaStats.startCount++; + + if(pReq->fragMode == MV_CESA_FRAG_NONE) + { + frag = 0; + } + else + { + frag = pReq->frags.nextFrag; + pReq->frags.nextFrag++; + } +#if (MV_CESA_VERSION >= 2) + /* Enable TDMA engine */ + MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); + MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, + (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); +#else + /* Enable IDMA engine */ + MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); + MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), + (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); +#endif /* MV_CESA_VERSION >= 2 */ + +#if defined(MV_BRIDGE_SYNC_REORDER) + mvOsBridgeReorderWA(); +#endif + + /* Start Accelerator */ + MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); +} + + +/******************************************************************************* +* mvCesaHalInit - Initialize the CESA driver +* +* DESCRIPTION: +* This function initialize the CESA driver. +* 1) Session database +* 2) Request queue +* 4) DMA descriptor lists - one list per request. Each list +* has MV_CESA_MAX_DMA_DESC descriptors. +* +* INPUT: +* numOfSession - maximum number of supported sessions +* queueDepth - number of elements in the request queue. +* pSramBase - virtual address of Sram +* osHandle - A handle used by the OS to allocate memory for the +* module (Passed to the OS Services layer) +* +* RETURN: +* MV_OK - Success +* MV_NO_RESOURCE - Fail, can't allocate resources: +* Session database, request queue, +* DMA descriptors list, LRU cache database. +* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. +* +*******************************************************************************/ +MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, + void *osHandle) +{ + int i, req; + MV_U32 descOffsetReg, configReg; + + mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", + numOfSession, queueDepth, pSramBase); + + cesaOsHandle = osHandle; + /* Create initial Session database */ + pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA*)*numOfSession); + if(pCesaSAD == NULL) + { + mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", + sizeof(MV_CESA_SA*)*numOfSession, numOfSession); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pCesaSAD, 0, sizeof(MV_CESA_SA*)*numOfSession); + cesaMaxSA = numOfSession; + + /* Create request queue */ + pCesaReqFirst = mvOsMalloc(sizeof(MV_CESA_REQ)*queueDepth); + if(pCesaReqFirst == NULL) + { + mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d requests\n", + sizeof(MV_CESA_REQ)*queueDepth, queueDepth); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pCesaReqFirst, 0, sizeof(MV_CESA_REQ)*queueDepth); + pCesaReqEmpty = pCesaReqFirst; + pCesaReqLast = pCesaReqFirst + (queueDepth-1); + pCesaReqProcess = pCesaReqEmpty; + cesaQueueDepth = queueDepth; + cesaReqResources = queueDepth; +#if (MV_CESA_VERSION >= 3) + cesaChainLength = MAX_CESA_CHAIN_LENGTH; +#endif + /* pSramBase must be 8 byte aligned */ + if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) + { + mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", + pSramBase); + mvCesaFinish(); + return MV_NOT_ALIGNED; + } + cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; + + cesaCryptEngBase = cryptEngBase; + + /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ + + /* Clear registers */ + MV_REG_WRITE( MV_CESA_CFG_REG, 0); + MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); + MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); + + /* Initialize DMA descriptor lists for all requests in Request queue */ + descOffsetReg = configReg = 0; + for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + + CPU_D_CACHE_LINE_SIZE; + + pReq->cesaDescBuf.bufVirtPtr = + mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, + &pReq->cesaDescBuf.bufPhysAddr, + &pReq->cesaDescBuf.memHandle); + + if(pReq->cesaDescBuf.bufVirtPtr == NULL) + { + mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", + req, pReq->cesaDescBuf.bufSize); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); + pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + + CPU_D_CACHE_LINE_SIZE; + + pReq->dmaDescBuf.bufVirtPtr = + mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, + &pReq->dmaDescBuf.bufPhysAddr, + &pReq->dmaDescBuf.memHandle); + + if(pReq->dmaDescBuf.bufVirtPtr == NULL) + { + mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", + req, pReq->dmaDescBuf.bufSize); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); + pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + for(frag=0; fragdma[frag]; + + pDma->pDmaFirst = pDmaDesc; + pDma->pDmaLast = NULL; + + for(i=0; ipDmaFirst[i].phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); + } + pDma->pDmaFirst[i].phyNextDescPtr = 0; + mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); + + pDmaDesc += MV_CESA_MAX_DMA_DESC; + } + } + /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ + descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); + MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); + + configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); +#if (MV_CESA_VERSION >= 3) + configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; +#endif + +#if (MV_CESA_VERSION >= 2) + /* Initialize TDMA engine */ + MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); + MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); + MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); +#else + /* Initialize IDMA #0 engine */ + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); + MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); + MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); + MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE +#ifdef MV_CPU_LE + | ICCHR_DESC_BYTE_SWAP_EN +#endif + ); + /* Clear Cause Byte of IDMA channel to be used */ + MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); +#endif /* (MV_CESA_VERSION >= 2) */ + + /* Set CESA configuration registers */ + MV_REG_WRITE( MV_CESA_CFG_REG, configReg); + mvCesaDebugStatsClear(); + + return MV_OK; +} + +/******************************************************************************* +* mvCesaFinish - Shutdown the CESA driver +* +* DESCRIPTION: +* This function shutdown the CESA driver and free all allocted resources. +* +* INPUT: None +* +* RETURN: +* MV_OK - Success +* Other - Fail +* +*******************************************************************************/ +MV_STATUS mvCesaFinish (void) +{ + int req, sid; + MV_CESA_REQ* pReq; + + mvOsPrintf("mvCesaFinish: \n"); + + cesaSramVirtPtr = NULL; + + /* Free all resources: DMA list, etc. */ + for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) + { + mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, + pReq->dmaDescBuf.bufPhysAddr, + pReq->dmaDescBuf.bufVirtPtr, + pReq->dmaDescBuf.memHandle); + } + if(pReq->cesaDescBuf.bufVirtPtr != NULL) + { + mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, + pReq->cesaDescBuf.bufPhysAddr, + pReq->cesaDescBuf.bufVirtPtr, + pReq->cesaDescBuf.memHandle); + } + } +#if (MV_CESA_VERSION < 2) + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); +#endif /* (MV_CESA_VERSION < 2) */ + + /* Free request queue */ + if(pCesaReqFirst != NULL) + { + mvOsFree(pCesaReqFirst); + pCesaReqFirst = pCesaReqLast = NULL; + pCesaReqEmpty = pCesaReqProcess = NULL; + cesaQueueDepth = cesaReqResources = 0; + } + /* Free SA database */ + if(pCesaSAD != NULL) + { + for(sid = 0;sid < cesaMaxSA; sid++) + { + /* Free SRAM SA structure */ + mvOsIoCachedFree(cesaOsHandle, pCesaSAD[sid]->sramSABuffSize, + pCesaSAD[sid]->sramSAPhysAddr, + pCesaSAD[sid]->sramSABuff, + pCesaSAD[sid]->memHandle); + /* Free SA structure */ + mvOsFree(pCesaSAD[sid]); + pCesaSAD[sid] = NULL; + } + + cesaMaxSA = 0; + } + MV_REG_WRITE( MV_CESA_CFG_REG, 0); + MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); + MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); + + return MV_OK; +} + +/******************************************************************************* +* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode +* +* DESCRIPTION: +* This function set IV value using by Crypto algorithms in CBC mode. +* Each channel has its own IV value. +* This function gets IV value from the caller. If no IV value passed from +* the caller or only part of IV passed, the function will init the rest part +* of IV value (or the whole IV) by random value. +* +* INPUT: +* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL +* the function will generate random IV value. +* int ivSize - size (in bytes) of IV provided by user. If ivSize is +* smaller than maximum IV size, the function will complete +* IV by random value. +* +* RETURN: +* MV_OK - Success +* Other - Fail +* +*******************************************************************************/ +MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) +{ + MV_U8* pSramIV; +#if defined(MV646xx) + mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); +#endif + pSramIV = cesaSramVirtPtr->cryptoIV; + if(ivSize > MV_CESA_MAX_IV_LENGTH) + { + mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); + ivSize = MV_CESA_MAX_IV_LENGTH; + } + if(pIV != NULL) + { + memcpy(pSramIV, pIV, ivSize); + ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; + pSramIV += ivSize; + } + + while(ivSize > 0) + { + int size, mv_random = mvOsRand(); + + size = MV_MIN(ivSize, sizeof(mv_random)); + memcpy(pSramIV, (void*)&mv_random, size); + + pSramIV += size; + ivSize -= size; + } +/* + mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, + MV_CESA_MAX_IV_LENGTH); + mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, + MV_CESA_MAX_IV_LENGTH); +*/ + return MV_OK; +} + +/******************************************************************************* +* mvCesaSessionOpen - Open new uni-directional crypto session +* +* DESCRIPTION: +* This function open new session. +* +* INPUT: +* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters +* +* OUTPUT: +* short *pSid - session ID, should be used for all future +* requests over this session. +* +* RETURN: +* MV_OK - Session opend successfully. +* MV_FULL - All sessions are in use, no free place in +* SA database. +* MV_BAD_PARAM - One of session input parameters is invalid. +* +*******************************************************************************/ +MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) +{ + short sid; + MV_U32 config = 0; + int digestSize; + MV_BUF_INFO cesaSramSaBuf; + + cesaStats.openedCount++; + + /* Find free entry in SAD */ + for(sid=0; sidsramSABuff = cesaSramSaBuf.bufVirtPtr; + pCesaSAD[sid]->sramSABuffSize = cesaSramSaBuf.bufSize; + pCesaSAD[sid]->memHandle = cesaSramSaBuf.memHandle; + pCesaSAD[sid]->pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + /* Align physical address to the beginning of SRAM SA */ + pCesaSAD[sid]->sramSAPhysAddr = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pCesaSAD[sid]->pSramSA)); + + /* Check Input parameters for Open session */ + if (pSession->operation >= MV_CESA_MAX_OPERATION) + { + mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", + pSession->operation); + return MV_BAD_PARAM; + } + config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); + + if( (pSession->direction != MV_CESA_DIR_ENCODE) && + (pSession->direction != MV_CESA_DIR_DECODE) ) + { + mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", + pSession->direction); + return MV_BAD_PARAM; + } + config |= (pSession->direction << MV_CESA_DIRECTION_BIT); + /* Clear SA entry */ + /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ + + /* Check AUTH parameters and update SA entry */ + if(pSession->operation != MV_CESA_CRYPTO_ONLY) + { + /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ + if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || + (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) + { + if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) + { + mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", + pSession->macKeyLength); + return MV_BAD_PARAM; + } + mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, + pCesaSAD[sid]->pSramSA->macInnerIV, + pCesaSAD[sid]->pSramSA->macOuterIV); + pCesaSAD[sid]->macKeyLength = pSession->macKeyLength; + } + switch(pSession->macMode) + { + case MV_CESA_MAC_MD5: + case MV_CESA_MAC_HMAC_MD5: + digestSize = MV_CESA_MD5_DIGEST_SIZE; + break; + + case MV_CESA_MAC_SHA1: + case MV_CESA_MAC_HMAC_SHA1: + digestSize = MV_CESA_SHA1_DIGEST_SIZE; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", + pSession->macMode); + return MV_BAD_PARAM; + } + config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); + + /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ + /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ + if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) + { + mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", + pSession->digestSize); + mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); + return MV_BAD_PARAM; + } + pCesaSAD[sid]->digestSize = pSession->digestSize; + + if(pCesaSAD[sid]->digestSize == 12) + { + /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ + config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); + } + } + + /* Check CRYPTO parameters and update SA entry */ + if(pSession->operation != MV_CESA_MAC_ONLY) + { + switch(pSession->cryptoAlgorithm) + { + case MV_CESA_CRYPTO_DES: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; + pCesaSAD[sid]->cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; + break; + + case MV_CESA_CRYPTO_3DES: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; + pCesaSAD[sid]->cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; + /* Only EDE mode is supported */ + config |= (MV_CESA_CRYPTO_3DES_EDE << + MV_CESA_CRYPTO_3DES_MODE_BIT); + break; + + case MV_CESA_CRYPTO_AES: + switch(pSession->cryptoKeyLength) + { + case 16: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_128 << + MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + + case 24: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_192 << + MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + + case 32: + default: + pCesaSAD[sid]->cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_256 << + MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + } + pCesaSAD[sid]->cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", + pSession->cryptoAlgorithm); + return MV_BAD_PARAM; + } + config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); + + if(pSession->cryptoKeyLength != pCesaSAD[sid]->cryptoKeyLength) + { + mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", + pSession->cryptoKeyLength, pCesaSAD[sid]->cryptoKeyLength); + return MV_BAD_PARAM; + } + + /* Copy Crypto key */ + if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && + (pSession->direction == MV_CESA_DIR_DECODE)) + { + /* Crypto Key for AES decode is computed from original key material */ + /* and depend on cryptoKeyLength (128/192/256 bits) */ + aesMakeKey(pCesaSAD[sid]->pSramSA->cryptoKey, pSession->cryptoKey, + pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); + } + else + { + /*panic("mvCesaSessionOpen2");*/ + memcpy(pCesaSAD[sid]->pSramSA->cryptoKey, pSession->cryptoKey, + pCesaSAD[sid]->cryptoKeyLength); + + } + + switch(pSession->cryptoMode) + { + case MV_CESA_CRYPTO_ECB: + pCesaSAD[sid]->cryptoIvSize = 0; + break; + + case MV_CESA_CRYPTO_CBC: + pCesaSAD[sid]->cryptoIvSize = pCesaSAD[sid]->cryptoBlockSize; + break; + + case MV_CESA_CRYPTO_CTR: + /* Supported only for AES algorithm */ + if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) + { + mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); + return MV_BAD_PARAM; + } + pCesaSAD[sid]->cryptoIvSize = 0; + pCesaSAD[sid]->ctrMode = 1; + /* Replace to ECB mode for HW */ + pSession->cryptoMode = MV_CESA_CRYPTO_ECB; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", + pSession->cryptoMode); + return MV_BAD_PARAM; + } + + config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); + } + pCesaSAD[sid]->config = config; + + mvOsCacheFlush(NULL, pCesaSAD[sid]->pSramSA, sizeof(MV_CESA_SRAM_SA)); + if(pSid != NULL) + *pSid = sid; + + return MV_OK; +} + +/******************************************************************************* +* mvCesaSessionClose - Close active crypto session +* +* DESCRIPTION: +* This function closes existing session +* +* INPUT: +* short sid - Unique identifier of the session to be closed +* +* RETURN: +* MV_OK - Session closed successfully. +* MV_BAD_PARAM - Session identifier is out of valid range. +* MV_NOT_FOUND - There is no active session with such ID. +* +*******************************************************************************/ +MV_STATUS mvCesaSessionClose(short sid) +{ + cesaStats.closedCount++; + + if(sid >= cesaMaxSA) + { + mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); + return MV_BAD_PARAM; + } + + if(pCesaSAD[sid] == NULL) + { + mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); + return MV_NOT_FOUND; + } + if(cesaLastSid == sid) + cesaLastSid = -1; + + /* Free SA structures */ + mvOsIoCachedFree(cesaOsHandle, pCesaSAD[sid]->sramSABuffSize, + pCesaSAD[sid]->sramSAPhysAddr, + pCesaSAD[sid]->sramSABuff, + pCesaSAD[sid]->memHandle); + mvOsFree(pCesaSAD[sid]); + + pCesaSAD[sid] = NULL; + + return MV_OK; +} + +/******************************************************************************* +* mvCesaAction - Perform crypto operation +* +* DESCRIPTION: +* This function set new CESA request FIFO queue for further HW processing. +* The function checks request parameters before set new request to the queue. +* If one of the CESA channels is ready for processing the request will be +* passed to HW. When request processing is finished the CESA interrupt will +* be generated by HW. The caller should call mvCesaReadyGet() function to +* complete request processing and get result. +* +* INPUT: +* MV_CESA_COMMAND *pCmd - pointer to new CESA request. +* It includes pointers to Source and Destination +* buffers, session identifier get from +* mvCesaSessionOpen() function, pointer to caller +* private data and all needed crypto parameters. +* +* RETURN: +* MV_OK - request successfully added to request queue +* and will be processed. +* MV_NO_MORE - request successfully added to request queue and will +* be processed, but request queue became Full and next +* request will not be accepted. +* MV_NO_RESOURCE - request queue is FULL and the request can not +* be processed. +* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is +* failed. Request can not be processed. +* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed +* as one request and should be splitted for two requests: +* CRYPTO_ONLY and MAC_ONLY. +* MV_BAD_PARAM - One of the request parameters is out of valid range. +* The request can not be processed. +* +*******************************************************************************/ +MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) +{ + MV_STATUS status; + MV_CESA_REQ* pReq = pCesaReqEmpty; + int sid = pCmd->sessionId; + MV_CESA_SA* pSA = pCesaSAD[sid]; +#if (MV_CESA_VERSION >= 3) + MV_CESA_REQ* pFromReq; + MV_CESA_REQ* pToReq; +#endif + cesaStats.reqCount++; + + /* Check that the request queue is not FULL */ + if(cesaReqResources == 0) + return MV_NO_RESOURCE; + + if( (sid >= cesaMaxSA) || (pSA == NULL) ) + { + mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); + return MV_BAD_PARAM; + } + pSA->count++; + + if(pSA->ctrMode) + { + /* AES in CTR mode can't be mixed with Authentication */ + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); + return MV_NOT_ALLOWED; + } + /* All other request parameters should not be checked because key stream */ + /* (not user data) processed by AES HW engine */ + pReq->pOrgCmd = pCmd; + /* Allocate temporary pCmd structure for Key stream */ + pCmd = mvCesaCtrModeInit(); + if(pCmd == NULL) + return MV_OUT_OF_CPU_MEM; + + /* Prepare Key stream */ + mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); + pReq->fixOffset = 0; + } + else + { + /* Check request parameters and calculae fixOffset */ + status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); + if(status != MV_OK) + { + return status; + } + } + pReq->pCmd = pCmd; + + /* Check if the packet need fragmentation */ + if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) + { + /* request size is smaller than single buffer size */ + pReq->fragMode = MV_CESA_FRAG_NONE; + + /* Prepare NOT fragmented packets */ + status = mvCesaReqProcess(pReq); + if(status != MV_OK) + { + mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", + pReq, status); + } +#if (MV_CESA_VERSION >= 3) + pReq->frags.numFrag = 1; +#endif + } + else + { + MV_U8 frag = 0; + + /* request size is larger than buffer size - needs fragmentation */ + + /* Check restrictions for processing fragmented packets */ + status = mvCesaFragParamCheck(pSA, pCmd); + if(status != MV_OK) + return status; + + pReq->fragMode = MV_CESA_FRAG_FIRST; + pReq->frags.nextFrag = 0; + + /* Prepare Process Fragmented packets */ + while(pReq->fragMode != MV_CESA_FRAG_LAST) + { + if(frag >= MV_CESA_MAX_REQ_FRAGS) + { + mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); + return MV_OUT_OF_CPU_MEM; + } + status = mvCesaFragReqProcess(pReq, frag); + if(status == MV_OK) { +#if (MV_CESA_VERSION >= 3) + if(frag) { + pReq->dma[frag-1].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); + mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); + } +#endif + frag++; + } + } + pReq->frags.numFrag = frag; +#if (MV_CESA_VERSION >= 3) + if(chainReqNum) { + chainReqNum += pReq->frags.numFrag; + if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) + chainReqNum = MAX_CESA_CHAIN_LENGTH; + } +#endif + } + + pReq->state = MV_CESA_PENDING; + + pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); + cesaReqResources -= 1; + +/* #ifdef CESA_DEBUG */ + if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) + cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); +/* #endif CESA_DEBUG */ + + cesaLastSid = sid; + +#if (MV_CESA_VERSION >= 3) + /* Are we within chain bounderies and follows the first request ? */ + if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { + if(chainIndex) { + pFromReq = MV_CESA_REQ_PREV_PTR(pReq); + pToReq = pReq; + pReq->state = MV_CESA_CHAIN; + /* assume concatenating is possible */ + pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); + mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); + + /* align active & next pointers */ + if(pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); + } + else { /* we have only one chain, start new one */ + chainReqNum = 0; + chainIndex++; + /* align active & next pointers */ + if(pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = pReq; + } + } + else { + /* In case we concatenate full chain */ + if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { + chainIndex++; + if(pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = pReq; + chainReqNum = 0; + } + + pReq = pCesaReqProcess; + if(pReq->state == MV_CESA_PENDING) { + pNextActiveChain = pReq; + pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); + /* Start Process new request */ + mvCesaReqProcessStart(pReq); + } + } + + chainReqNum++; + + if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) + cesaStats.maxChainUsage = chainReqNum; + +#else + + /* Check status of CESA channels and process requests if possible */ + pReq = pCesaReqProcess; + if(pReq->state == MV_CESA_PENDING) + { + /* Start Process new request */ + mvCesaReqProcessStart(pReq); + } +#endif + /* If request queue became FULL - return MV_NO_MORE */ + if(cesaReqResources == 0) + return MV_NO_MORE; + + return MV_OK; + +} + +/******************************************************************************* +* mvCesaReadyGet - Get crypto request that processing is finished +* +* DESCRIPTION: +* This function complete request processing and return ready request to +* caller. To don't miss interrupts the caller must call this function +* while MV_OK or MV_TERMINATE values returned. +* +* INPUT: +* MV_U32 chanMap - map of CESA channels finished thier job +* accordingly with CESA Cause register. +* MV_CESA_RESULT* pResult - pointer to structure contains information +* about ready request. It includes pointer to +* user private structure "pReqPrv", session identifier +* for this request "sessionId" and return code. +* Return code set to MV_FAIL if calculated digest value +* on decode direction is different than digest value +* in the packet. +* +* RETURN: +* MV_OK - Success, ready request is returned. +* MV_NOT_READY - Next request is not ready yet. New interrupt will +* be generated for futher request processing. +* MV_EMPTY - There is no more request for processing. +* MV_BUSY - Fragmented request is not ready yet. +* MV_TERMINATE - Call this function once more to complete processing +* of fragmented request. +* +*******************************************************************************/ +MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) +{ + MV_STATUS status, readyStatus = MV_NOT_READY; + MV_U32 statusReg; + MV_CESA_REQ* pReq; + MV_CESA_SA* pSA; + +#if (MV_CESA_VERSION >= 3) + if(isFirstReq == MV_TRUE) { + if(chainIndex == 0) + chainReqNum = 0; + + isFirstReq = MV_FALSE; + + if(pNextActiveChain->state == MV_CESA_PENDING) { + /* Start request Process */ + mvCesaReqProcessStart(pNextActiveChain); + pEndCurrChain = pNextActiveChain; + if(chainIndex > 0) + chainIndex--; + /* Update pNextActiveChain to next chain head */ + while(pNextActiveChain->state == MV_CESA_CHAIN) + pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); + } + } + + /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ + if(pCesaReqProcess == pEndCurrChain) { + isFirstReq = MV_TRUE; + pEndCurrChain = pNextActiveChain; +#else + if(pCesaReqProcess->state != MV_CESA_PROCESS) { +#endif + return MV_EMPTY; + } + +#ifdef CESA_DEBUG + statusReg = MV_REG_READ(MV_CESA_STATUS_REG); + if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) + { + mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); + cesaStats.notReadyCount++; + return MV_NOT_READY; + } +#endif /* CESA_DEBUG */ + + cesaStats.readyCount++; + + pReq = pCesaReqProcess; + pSA = pCesaSAD[pReq->pCmd->sessionId]; + + pResult->retCode = MV_OK; + if(pReq->fragMode != MV_CESA_FRAG_NONE) + { + MV_U8* pNewDigest; + int frag; +#if (MV_CESA_VERSION >= 3) + pReq->frags.nextFrag = 1; + while(pReq->frags.nextFrag <= pReq->frags.numFrag) { +#endif + frag = (pReq->frags.nextFrag - 1); + + /* Restore DMA descriptor list */ + pReq->dma[frag].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); + pReq->dma[frag].pDmaLast = NULL; + + /* Special processing for finished fragmented request */ + if(pReq->frags.nextFrag >= pReq->frags.numFrag) + { + mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); + + /* Fragmented packet is ready */ + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; + + if(macDataSize != 0) + { + /* Calculate all other blocks by SW */ + mvCesaFragAuthComplete(pReq, pSA, macDataSize); + } + + /* Copy new digest from SRAM to the Destination buffer */ + pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; + status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, + pReq->pCmd->digestOffset, pSA->digestSize); + + /* For decryption: Compare new digest value with original one */ + if((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) + { + if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) + { +/* + mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", + chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); +*/ + /* Signiture verification is failed */ + pResult->retCode = MV_FAIL; + } + } + } + readyStatus = MV_OK; + } +#if (MV_CESA_VERSION >= 3) + pReq->frags.nextFrag++; + } +#endif + } + else + { + mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); + + /* Restore DMA descriptor list */ + pReq->dma[0].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); + pReq->dma[0].pDmaLast = NULL; + if( ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) + { + /* For AUTH on decode : Check Digest result in Status register */ + statusReg = MV_REG_READ(MV_CESA_STATUS_REG); + if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) + { +/* + mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", + chan, statusReg); +*/ + /* Signiture verification is failed */ + pResult->retCode = MV_FAIL; + } + } + readyStatus = MV_OK; + } + + if(readyStatus == MV_OK) + { + /* If Request is ready - Prepare pResult structure */ + pResult->pReqPrv = pReq->pCmd->pReqPrv; + pResult->sessionId = pReq->pCmd->sessionId; + + pReq->state = MV_CESA_IDLE; + pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); + cesaReqResources++; + + if(pSA->ctrMode) + { + /* For AES CTR mode - complete processing and free allocated resources */ + mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); + mvCesaCtrModeFinish(pReq->pCmd); + pReq->pOrgCmd = NULL; + } + } + +#if (MV_CESA_VERSION < 3) + if(pCesaReqProcess->state == MV_CESA_PROCESS) + { + /* Start request Process */ + mvCesaReqProcessStart(pCesaReqProcess); + if(readyStatus == MV_NOT_READY) + readyStatus = MV_BUSY; + } + else if(pCesaReqProcess != pCesaReqEmpty) + { + /* Start process new request from the queue */ + mvCesaReqProcessStart(pCesaReqProcess); + } +#endif + return readyStatus; +} + +/***************** Functions to work with CESA_MBUF structure ******************/ + +/******************************************************************************* +* mvCesaMbufOffset - Locate offset in the Mbuf structure +* +* DESCRIPTION: +* This function locates offset inside Multi-Bufeer structure. +* It get fragment number and place in the fragment where the offset +* is located. +* +* +* INPUT: +* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure +* int offset - Offset from the beginning of the data presented by +* the Mbuf structure. +* +* OUTPUT: +* int* pBufOffset - Offset from the beginning of the fragment where +* the offset is located. +* +* RETURN: +* int - Number of fragment, where the offset is located\ +* +*******************************************************************************/ +int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) +{ + int frag = 0; + + while(offset > 0) + { + if(frag >= pMbuf->numFrags) + { + mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", + frag, pMbuf->numFrags); + return MV_INVALID; + } + if(offset < pMbuf->pFrags[frag].bufSize) + { + break; + } + offset -= pMbuf->pFrags[frag].bufSize; + frag++; + } + if(pBufOffset != NULL) + *pBufOffset = offset; + + return frag; +} + +/******************************************************************************* +* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer +* +* DESCRIPTION: +* +* +* INPUT: +* MV_U8* pDstBuf - Pointer to continuous buffer, where data is +* copied to. +* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is +* copied from. +* int offset - Offset in the Mbuf structure where located first +* byte of data should be copied. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. +* No data is copied. +* MV_EMPTY - Multi-buffer structure has not enough data to copy +* Data from the offset to end of Mbuf data is copied. +* +*******************************************************************************/ +MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, + int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8* pBuf; + + if(size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); + if(frag == MV_INVALID) + { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while(MV_TRUE) + { + if(size <= bufSize) + { + memcpy(pDstBuf, pBuf, size); + return MV_OK; + } + memcpy(pDstBuf, pBuf, bufSize); + size -= bufSize; + frag++; + pDstBuf += bufSize; + if(frag >= pSrcMbuf->numFrags) + break; + + bufSize = pSrcMbuf->pFrags[frag].bufSize; + pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", + size); + return MV_EMPTY; +} + +/******************************************************************************* +* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure +* +* DESCRIPTION: +* +* +* INPUT: +* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is +* copied from. +* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is +* copied to. +* int offset - Offset in the Mbuf structure where located first +* byte of data should be copied. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. +* No data is copied. +* MV_FULL - Multi-buffer structure has not enough place to copy +* all data. Data from the offset to end of Mbuf data +* is copied. +* +*******************************************************************************/ +MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, + int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8* pBuf; + + if(size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); + if(frag == MV_INVALID) + { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while(MV_TRUE) + { + if(size <= bufSize) + { + memcpy(pBuf, pSrcBuf, size); + return MV_OK; + } + memcpy(pBuf, pSrcBuf, bufSize); + size -= bufSize; + frag++; + pSrcBuf += bufSize; + if(frag >= pDstMbuf->numFrags) + break; + + bufSize = pDstMbuf->pFrags[frag].bufSize; + pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", + size); + return MV_FULL; +} + +/******************************************************************************* +* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure +* +* DESCRIPTION: +* +* +* INPUT: +* +* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is +* copied to. +* int dstMbufOffset - Offset in the dstMbuf structure where first byte +* of data should be copied to. +* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is +* copied from. +* int srcMbufOffset - Offset in the srcMbuf structure where first byte +* of data should be copied from. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of +* srcMbuf or dstMbuf structure correspondently. +* No data is copied. +* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy +* all data. Partial data is copied +* +*******************************************************************************/ +MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, + MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) +{ + int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; + int copySize; + MV_U8 *pSrc, *pDst; + + if(size == 0) + return MV_OK; + + srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); + if(srcFrag == MV_INVALID) + { + mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); + return MV_OUT_OF_RANGE; + } + pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; + srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; + + dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); + if(dstFrag == MV_INVALID) + { + mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); + return MV_OUT_OF_RANGE; + } + pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; + dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; + + while(size > 0) + { + copySize = MV_MIN(srcSize, dstSize); + if(size <= copySize) + { + memcpy(pDst, pSrc, size); + return MV_OK; + } + memcpy(pDst, pSrc, copySize); + size -= copySize; + srcSize -= copySize; + dstSize -= copySize; + + if(srcSize == 0) + { + srcFrag++; + if(srcFrag >= pMbufSrc->numFrags) + break; + + pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; + srcSize = pMbufSrc->pFrags[srcFrag].bufSize; + } + + if(dstSize == 0) + { + dstFrag++; + if(dstFrag >= pMbufDst->numFrags) + break; + + pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; + dstSize = pMbufDst->pFrags[dstFrag].bufSize; + } + } + mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", + size); + + return MV_BAD_SIZE; +} + +MV_STATUS mvCesaUpdateSADSize(MV_U32 size) +{ + MV_CESA_SA** pNewCesaSAD = NULL; + + /*mvOsPrintf("mvCesaUpdateSADSize: Increasing SA Database to %d sessions\n",size);*/ + + /* Allocate new buffer to hold larger SAD */ + pNewCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA*) * size); + if(pNewCesaSAD == NULL) + { + mvOsPrintf("mvCesaUpdateSADSize: Can't allocate %d bytes for new SAD buffer\n", size); + return MV_FAIL; + } + memset(pNewCesaSAD, 0, (sizeof(MV_CESA_SA*) * size)); + mvOsMemcpy(pNewCesaSAD, pCesaSAD, (sizeof(MV_CESA_SA*) * cesaMaxSA)); + mvOsFree(pCesaSAD); + pCesaSAD = pNewCesaSAD; + cesaMaxSA = size; + + return MV_OK; +} + +static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8* pBuf; + + if(size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); + if(frag == MV_INVALID) + { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while(MV_TRUE) + { + if(size <= bufSize) + { + mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); + return MV_OK; + } + + mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); + size -= bufSize; + frag++; + if(frag >= pMbuf->numFrags) + break; + + bufSize = pMbuf->pFrags[frag].bufSize; + pBuf = pMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", + __FUNCTION__, size); + return MV_FULL; +} + + +/*************************************** Local Functions ******************************/ + +/******************************************************************************* +* mvCesaFragReqProcess - Process fragmented request +* +* DESCRIPTION: +* This function processes a fragment of fragmented request (First, Middle or Last) +* +* +* INPUT: +* MV_CESA_REQ* pReq - Pointer to the request in the request queue. +* +* RETURN: +* MV_OK - The fragment is successfully passed to HW for processing. +* MV_TERMINATE - Means, that HW finished its work on this packet and no more +* interrupts will be generated for this request. +* Function mvCesaReadyGet() must be called to complete request +* processing and get request result. +* +*******************************************************************************/ +static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) +{ + int i, copySize, cryptoDataSize, macDataSize, sid; + int cryptoIvOffset, digestOffset; + MV_U32 config; + MV_CESA_COMMAND* pCmd = pReq->pCmd; + MV_CESA_SA* pSA; + MV_CESA_MBUF* pMbuf; + MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; + MV_U8* pSramBuf = cesaSramVirtPtr->buf; + int macTotalLen = 0; + int fixOffset, cryptoOffset, macOffset; + + cesaStats.fragCount++; + + sid = pReq->pCmd->sessionId; + + pSA = pCesaSAD[sid]; + + cryptoIvOffset = digestOffset = 0; + i = macDataSize = 0; + cryptoDataSize = 0; + + /* First fragment processing */ + if(pReq->fragMode == MV_CESA_FRAG_FIRST) + { + /* pReq->frags monitors processing of fragmented request between fragments */ + pReq->frags.bufOffset = 0; + pReq->frags.cryptoSize = 0; + pReq->frags.macSize = 0; + + config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); + + /* fixOffset can be not equal to zero only for FIRST fragment */ + fixOffset = pReq->fixOffset; + /* For FIRST fragment crypto and mac offsets are taken from pCmd */ + cryptoOffset = pCmd->cryptoOffset; + macOffset = pCmd->macOffset; + + copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; + + /* Find fragment size: Must meet all requirements for CRYPTO and MAC + * cryptoDataSize - size of data will be encrypted/decrypted in this fragment + * macDataSize - size of data will be signed/verified in this fragment + * copySize - size of data will be copied from srcMbuf to SRAM and + * back to dstMbuf for this fragment + */ + mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, + ©Size, &cryptoDataSize, &macDataSize); + + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) + { + /* CryptoIV special processing */ + if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == + (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) + { + /* In CBC mode for encode direction when IV from user */ + if( (pCmd->ivFromUser) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) + { + + /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, + * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place + * in the buffer to SRAM IVPointer + */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], + MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); + } + + /* Special processing when IV is not located in the first fragment */ + if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) + { + /* Prepare dummy place for cryptoIV in SRAM */ + cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); + + /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ + if((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) + { + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], + MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); + } + else + { + /* For Encryption when IV is NOT from User: */ + /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ + if(pCmd->ivFromUser == 0) + { + /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], + MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); + } + } + } + else + { + cryptoIvOffset = pCmd->ivOffset; + } + } + } + + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + /* MAC digest special processing on Decode direction */ + if((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) + { + /* Save digest from pCmd->digestOffset */ + mvCesaCopyFromMbuf(pReq->frags.orgDigest, + pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); + + /* If pCmd->digestOffset is not located on the first */ + if(pCmd->digestOffset > (copySize - pSA->digestSize)) + { + MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; + + /* Set zeros to pCmd->digestOffset (DRAM) */ + memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); + mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); + + /* Prepare dummy place for digest in SRAM */ + digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + } + else + { + digestOffset = pCmd->digestOffset; + } + } + } + /* Update SA in SRAM */ + if(cesaLastSid != sid) + { + mvCesaSramSaUpdate(sid, &pDmaDesc[i]); + i++; + } + + pReq->fragMode = MV_CESA_FRAG_MIDDLE; + } + else + { + /* Continue fragment */ + fixOffset = 0; + cryptoOffset = 0; + macOffset = 0; + if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) + { + /* Last fragment */ + config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); + pReq->fragMode = MV_CESA_FRAG_LAST; + copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; + + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + macDataSize = pCmd->macLength - pReq->frags.macSize; + + /* If pCmd->digestOffset is not located on last fragment */ + if(pCmd->digestOffset < pReq->frags.bufOffset) + { + /* Prepare dummy place for digest in SRAM */ + digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + } + else + { + digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; + } + pReq->frags.newDigestOffset = digestOffset; + macTotalLen = pCmd->macLength; + + /* HW can't calculate the Digest correctly for fragmented packets + * in the following cases: + * - MV88F5182 || + * - MV88F5181L when total macLength more that 16 Kbytes || + * - total macLength more that 64 Kbytes + */ + if( (mvCtrlModelGet() == MV_5182_DEV_ID) || + ( (mvCtrlModelGet() == MV_5181_DEV_ID) && + (mvCtrlRevGet() >= MV_5181L_A0_REV) && + (pCmd->macLength >= (1 << 14)) ) ) + { + return MV_TERMINATE; + } + } + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; + } + + /* cryptoIvOffset - don't care */ + } + else + { + /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ + if( (mvCtrlModelGet() == MV_5182_DEV_ID) && + (((pSA->config & MV_CESA_MAC_MODE_MASK) == + (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || + ((pSA->config & MV_CESA_MAC_MODE_MASK) == + (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) + { + pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + pReq->fragMode = MV_CESA_FRAG_LAST; + + return MV_TERMINATE; + } + /* Middle fragment */ + config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); + copySize = sizeof(cesaSramVirtPtr->buf); + /* digestOffset and cryptoIvOffset - don't care */ + + /* Find fragment size */ + mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, + ©Size, &cryptoDataSize, &macDataSize); + } + } + /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ + pMbuf = pCmd->pSrc; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); + + /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ + mvCesaSramDescrBuild(config, frag, + cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, + cryptoDataSize, macOffset + fixOffset, + digestOffset + fixOffset, macDataSize, macTotalLen, + pReq, &pDmaDesc[i]); + i++; + + /* Add special descriptor Ownership for CPU */ + pDmaDesc[i].byteCnt = 0; + pDmaDesc[i].phySrcAdd = 0; + pDmaDesc[i].phyDestAdd = 0; + i++; + + /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ + pMbuf = pCmd->pDst; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); + + /* Next field of Last DMA descriptor must be NULL */ + pDmaDesc[i-1].phyNextDescPtr = 0; + pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; + mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, + i*sizeof(MV_DMA_DESC)); + + /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ + + pReq->frags.bufOffset += copySize; + pReq->frags.cryptoSize += cryptoDataSize; + pReq->frags.macSize += macDataSize; + + return MV_OK; +} + + +/******************************************************************************* +* mvCesaReqProcess - Process regular (Non-fragmented) request +* +* DESCRIPTION: +* This function processes the whole (not fragmented) request +* +* INPUT: +* MV_CESA_REQ* pReq - Pointer to the request in the request queue. +* +* RETURN: +* MV_OK - The request is successfully passed to HW for processing. +* Other - Failure. The request will not be processed +* +*******************************************************************************/ +static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) +{ + MV_CESA_MBUF *pMbuf; + MV_DMA_DESC *pDmaDesc; + MV_U8 *pSramBuf; + int sid, i, fixOffset; + MV_CESA_SA *pSA; + MV_CESA_COMMAND *pCmd = pReq->pCmd; + + cesaStats.procCount++; + + sid = pCmd->sessionId; + pSA = pCesaSAD[sid]; + pDmaDesc = pReq->dma[0].pDmaFirst; + pSramBuf = cesaSramVirtPtr->buf; + fixOffset = pReq->fixOffset; + +/* + mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", + sid, pSA, pDmaDesc, pSramBuf); +*/ + i = 0; + + /* Crypto IV Special processing in CBC mode for Encryption direction */ + if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && + ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && + (pCmd->ivFromUser) ) + { + /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, + * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place + * in the buffer to SRAM IVPointer + */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], + MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); + } + + /* Update SA in SRAM */ + if(cesaLastSid != sid) + { + mvCesaSramSaUpdate(sid, &pDmaDesc[i]); + i++; + } + + /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ + pMbuf = pCmd->pSrc; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); + + /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ + mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, + pCmd->ivOffset + fixOffset, pCmd->cryptoLength, + pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, + pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); + i++; + + /* Add special descriptor Ownership for CPU */ + pDmaDesc[i].byteCnt = 0; + pDmaDesc[i].phySrcAdd = 0; + pDmaDesc[i].phyDestAdd = 0; + i++; + + /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ + pMbuf = pCmd->pDst; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); + + /* Next field of Last DMA descriptor must be NULL */ + pDmaDesc[i-1].phyNextDescPtr = 0; + pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; + mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); + + return MV_OK; +} + + +/******************************************************************************* +* mvCesaSramDescrBuild - Set CESA descriptor in SRAM +* +* DESCRIPTION: +* This function builds CESA descriptor in SRAM from all Command parameters +* +* +* INPUT: +* int chan - CESA channel uses the descriptor +* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure +* int cryptoOffset - Offset from the beginning of SRAM buffer where +* data for encryption/decription is started. +* int ivOffset - Offset of crypto IV from the SRAM base. Valid only +* for first fragment. +* int cryptoLength - Size (in bytes) of data for encryption/descryption +* operation on this fragment. +* int macOffset - Offset from the beginning of SRAM buffer where +* data for Authentication is started +* int digestOffset - Offset from the beginning of SRAM buffer where +* digest is located. Valid for first and last fragments. +* int macLength - Size (in bytes) of data for Authentication +* operation on this fragment. +* int macTotalLen - Toatl size (in bytes) of data for Authentication +* operation on the whole request (packet). Valid for +* last fragment only. +* +* RETURN: None +* +*******************************************************************************/ +static void mvCesaSramDescrBuild(MV_U32 config, int frag, + int cryptoOffset, int ivOffset, int cryptoLength, + int macOffset, int digestOffset, int macLength, + int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) +{ + MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; + MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; + MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); + + pCesaDesc->config = MV_32BIT_LE(config); + + if( (config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + /* word 1 */ + pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); + pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); + /* word 2 */ + pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); + /* word 3 */ + pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - + mvCesaSramAddrGet())); + /* word 4 */ + pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - + mvCesaSramAddrGet())); + pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); + } + + if( (config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + /* word 5 */ + pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); + pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); + + /* word 6 */ + pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); + pCesaDesc->macDataLen = MV_16BIT_LE(macLength); + + /* word 7 */ + pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - + mvCesaSramAddrGet())); + pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - + mvCesaSramAddrGet())); + } + /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ + pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); + pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); + pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); + + /* flush Source buffer */ + mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); +} + +/******************************************************************************* +* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. +* +* DESCRIPTION: +* Copy to SRAM values of the required SA. +* +* +* INPUT: +* short sid - Session ID needs SRAM Cache update +* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to +* copy SA values from DRAM to SRAM. +* +* RETURN: +* MV_OK - Cache entry for this SA copied to SRAM. +* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM +* +*******************************************************************************/ +static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) +{ + MV_CESA_SA *pSA = pCesaSAD[sid]; + + /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ + pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); + pDmaDesc->phySrcAdd = pSA->sramSAPhysAddr; + pDmaDesc->phyDestAdd = + MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); + + /* Source buffer is already flushed during OpenSession*/ + /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ +} + +/******************************************************************************* +* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by +* Mbuf structure from DRAM to SRAM +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request +* data in DRAM +* MV_U8* pSramBuf - pointer to buffer in SRAM where data should +* be copied to. +* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. +* The function set number of DMA descriptors needed +* to copy the copySize bytes from Mbuf. +* MV_BOOL isToMbuf - Copy direction. +* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. +* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. +* int offset - Offset in the Mbuf structure that copy should be +* started from. +* int copySize - Size of data should be copied. +* +* RETURN: +* int - number of DMA descriptors used for the copy. +* +*******************************************************************************/ +#ifndef MV_NETBSD +static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, + MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, + int offset, int copySize, MV_BOOL skipFlush) +{ + int bufOffset, bufSize, size, frag, i; + MV_U8* pBuf; + + i = 0; + + /* Calculate start place for copy: fragment number and offset in the fragment */ + frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); + bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; + + /* Size accumulate total copy size */ + size = 0; + + /* Create DMA lists to copy mBuf from pSrc to SRAM */ + while(size < copySize) + { + /* Find copy size for each DMA descriptor */ + bufSize = MV_MIN(bufSize, (copySize - size)); + pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); + if(isToMbuf) + { + pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + pDmaDesc[i].phySrcAdd = + MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); + /* invalidate the buffer */ + if(skipFlush == MV_FALSE) + mvOsCacheInvalidate(NULL, pBuf, bufSize); + } + else + { + pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + pDmaDesc[i].phyDestAdd = + MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); + /* flush the buffer */ + if(skipFlush == MV_FALSE) + mvOsCacheFlush(NULL, pBuf, bufSize); + } + + /* Count number of used DMA descriptors */ + i++; + size += bufSize; + + /* go to next fragment in the Mbuf */ + frag++; + pBuf = pMbuf->pFrags[frag].bufVirtPtr; + bufSize = pMbuf->pFrags[frag].bufSize; + } + return i; +} +#else /* MV_NETBSD */ +static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, + MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, + int offset, int copySize, MV_BOOL skipFlush) +{ + int bufOffset, bufSize, thisSize, size, frag, i; + MV_ULONG bufPhys, sramPhys; + MV_U8* pBuf; + + /* + * Calculate start place for copy: fragment number and offset in + * the fragment + */ + frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); + + /* + * Get SRAM physical address only once. We can update it in-place + * as we build the descriptor chain. + */ + sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); + + /* + * 'size' accumulates total copy size, 'i' counts desccriptors. + */ + size = i = 0; + + /* Create DMA lists to copy mBuf from pSrc to SRAM */ + while (size < copySize) { + /* + * Calculate # of bytes to copy from the current fragment, + * and the pointer to the start of data + */ + bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; + bufOffset = 0; /* First frag may be non-zero */ + frag++; + + /* + * As long as there is data in the current fragment... + */ + while (bufSize > 0) { + /* + * Ensure we don't cross an MMU page boundary. + * XXX: This is NetBSD-specific, but it is a + * quick and dirty way to fix the problem. + * A true HAL would rely on the OS-specific + * driver to do this... + */ + thisSize = PAGE_SIZE - + (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); + thisSize = MV_MIN(bufSize, thisSize); + /* + * Make sure we don't copy more than requested + */ + if (thisSize > (copySize - size)) { + thisSize = copySize - size; + bufSize = 0; + } + + /* + * Physicall address of this fragment + */ + bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + + /* + * Set up the descriptor + */ + pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); + if(isToMbuf) { + pDmaDesc[i].phyDestAdd = bufPhys; + pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); + /* invalidate the buffer */ + if(skipFlush == MV_FALSE) + mvOsCacheInvalidate(NULL, pBuf, thisSize); + } else { + pDmaDesc[i].phySrcAdd = bufPhys; + pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); + /* flush the buffer */ + if(skipFlush == MV_FALSE) + mvOsCacheFlush(NULL, pBuf, thisSize); + } + + pDmaDesc[i].phyNextDescPtr = + MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); + + /* flush the DMA desc */ + mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); + + /* Update state */ + bufSize -= thisSize; + sramPhys += thisSize; + pBuf += thisSize; + size += thisSize; + i++; + } + } + + return i; +} +#endif /* MV_NETBSD */ +/******************************************************************************* +* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key +* +* DESCRIPTION: +* This function calculate Inner and Outer values used for HMAC algorithm. +* This operation allows improve performance fro the whole HMAC processing. +* +* INPUT: +* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. +* unsigned char key[] - Pointer to HMAC key. +* int keyLength - Size of HMAC key (maximum 64 bytes) +* +* OUTPUT: +* unsigned char innerIV[] - HASH(key^inner) +* unsigned char outerIV[] - HASH(key^outter) +* +* RETURN: None +* +*******************************************************************************/ +static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, + unsigned char innerIV[], unsigned char outerIV[]) +{ + unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; + unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; + int i, digestSize = 0; +#if defined(MV_CPU_LE) || defined(MV_PPC) + MV_U32 swapped32, val32, *pVal32; +#endif + for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; + size = pMbuf->pFrags[frag].bufSize - fragOffset; + + /* Complete Inner part */ + while(macLeftSize > 0) + { + if(macLeftSize <= size) + { + mvSHA1Update(&ctx, pData, macLeftSize); + break; + } + mvSHA1Update(&ctx, pData, size); + macLeftSize -= size; + frag++; + pData = pMbuf->pFrags[frag].bufVirtPtr; + size = pMbuf->pFrags[frag].bufSize; + } + mvSHA1Final(pDigest, &ctx); +/* + mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", + pOuterIV, macLeftSize, macTotalSize); + mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); +*/ + + if(pOuterIV != NULL) + { + /* If HMAC - Complete Outer part */ + for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; + size = pMbuf->pFrags[frag].bufSize - fragOffset; + + /* Complete Inner part */ + while(macLeftSize > 0) + { + if(macLeftSize <= size) + { + mvMD5Update(&ctx, pData, macLeftSize); + break; + } + mvMD5Update(&ctx, pData, size); + macLeftSize -= size; + frag++; + pData = pMbuf->pFrags[frag].bufVirtPtr; + size = pMbuf->pFrags[frag].bufSize; + } + mvMD5Final(pDigest, &ctx); + +/* + mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", + pOuterIV, macLeftSize, macTotalSize); + mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); +*/ + if(pOuterIV != NULL) + { + /* Complete Outer part */ + for(i=0; ipCmd; + MV_U8* pDigest; + MV_CESA_MAC_MODE macMode; + MV_U8* pOuterIV = NULL; + + /* Copy data from Source fragment to Destination */ + if(pCmd->pSrc != pCmd->pDst) + { + mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, + pCmd->pSrc, pReq->frags.bufOffset, macDataSize); + } + +/* + mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); + mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); +*/ + pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); + + macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; +/* + mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", + macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); +*/ + switch(macMode) + { + case MV_CESA_MAC_HMAC_MD5: + pOuterIV = pSA->pSramSA->macOuterIV; + + case MV_CESA_MAC_MD5: + mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, + macDataSize, pCmd->macLength, pDigest); + break; + + case MV_CESA_MAC_HMAC_SHA1: + pOuterIV = pSA->pSramSA->macOuterIV; + + case MV_CESA_MAC_SHA1: + mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, + macDataSize, pCmd->macLength, pDigest); + break; + + default: + mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); + return MV_BAD_PARAM; + } + return MV_OK; +} + +/******************************************************************************* +* mvCesaCtrModeInit - +* +* DESCRIPTION: +* +* +* INPUT: NONE +* +* +* RETURN: +* MV_CESA_COMMAND* +* +*******************************************************************************/ +static MV_CESA_COMMAND* mvCesaCtrModeInit(void) +{ + MV_CESA_MBUF *pMbuf; + MV_U8 *pBuf; + MV_CESA_COMMAND *pCmd; + + pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); + if(pBuf == NULL) + { + mvOsPrintf("mvCesaCtrModeInit: Can't allocate %u bytes for CTR Mode\n", + sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); + return NULL; + } + pCmd = (MV_CESA_COMMAND*)pBuf; + pBuf += sizeof(MV_CESA_COMMAND); + + pMbuf = (MV_CESA_MBUF*)pBuf; + pBuf += sizeof(MV_CESA_MBUF); + + pMbuf->pFrags = (MV_BUF_INFO*)pBuf; + + pMbuf->numFrags = 1; + pCmd->pSrc = pMbuf; + pCmd->pDst = pMbuf; +/* + mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", + pCmd, pCmd->pSrc, pCmd->pDst, + pMbuf->pFrags); +*/ + return pCmd; +} + +/******************************************************************************* +* mvCesaCtrModePrepare - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) +{ + MV_CESA_MBUF *pMbuf; + MV_U8 *pBuf, *pIV; + MV_U32 counter, *pCounter; + int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); +/* + mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", + pCmd, pCmd->pSrc, pCmd->pDst, + pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); +*/ + pMbuf = pCtrModeCmd->pSrc; + + /* Allocate buffer for Key stream */ + pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, + &pMbuf->pFrags[0].bufPhysAddr, + &pMbuf->pFrags[0].memHandle); + if(pBuf == NULL) + { + mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); + return MV_OUT_OF_CPU_MEM; + } + memset(pBuf, 0, cryptoSize); + mvOsCacheFlush(NULL, pBuf, cryptoSize); + + pMbuf->pFrags[0].bufVirtPtr = pBuf; + pMbuf->mbufSize = cryptoSize; + pMbuf->pFrags[0].bufSize = cryptoSize; + + pCtrModeCmd->pReqPrv = pCmd->pReqPrv; + pCtrModeCmd->sessionId = pCmd->sessionId; + + /* ivFromUser and ivOffset are don't care */ + pCtrModeCmd->cryptoOffset = 0; + pCtrModeCmd->cryptoLength = cryptoSize; + + /* digestOffset, macOffset and macLength are don't care */ + + mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); + pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); + counter = *pCounter; + counter = MV_32BIT_BE(counter); + pIV = pBuf; + cryptoSize -= MV_CESA_AES_BLOCK_SIZE; + + /* fill key stream */ + while(cryptoSize > 0) + { + pBuf += MV_CESA_AES_BLOCK_SIZE; + memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); + pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); + counter++; + *pCounter = MV_32BIT_BE(counter); + cryptoSize -= MV_CESA_AES_BLOCK_SIZE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvCesaCtrModeComplete - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) +{ + int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; + int cryptoSize = pCmd->cryptoLength; + MV_U8 *pSrc, *pDst, *pKey; + MV_STATUS status = MV_OK; +/* + mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", + pCmd, pCmd->pSrc, pCmd->pDst, + pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); +*/ + /* XOR source data with key stream to destination data */ + pKey = pCmd->pDst->pFrags[0].bufVirtPtr; + keyOffset = 0; + + if( (pOrgCmd->pSrc != pOrgCmd->pDst) && + (pOrgCmd->cryptoOffset > 0) ) + { + /* Copy Prefix from source buffer to destination buffer */ + + status = mvCesaMbufCopy(pOrgCmd->pDst, 0, + pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); +/* + status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, + 0, pOrgCmd->cryptoOffset); + status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, + 0, pOrgCmd->cryptoOffset); +*/ + } + + srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); + pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; + srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; + + dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); + pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; + dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; + + while(cryptoSize > 0) + { + pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); + + cryptoSize--; + dstOffset++; + srcOffset++; + keyOffset++; + + if(srcOffset >= srcSize) + { + srcFrag++; + srcOffset = 0; + pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; + srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; + } + + if(dstOffset >= dstSize) + { + dstFrag++; + dstOffset = 0; + pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; + dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; + } + } + + if(pOrgCmd->pSrc != pOrgCmd->pDst) + { + /* Copy Suffix from source buffer to destination buffer */ + srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; + + if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) + { + status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, + pOrgCmd->pSrc, srcOffset, + pOrgCmd->pDst->mbufSize - srcOffset); + } + +/* + status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, + srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); + status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, + srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); +*/ + } + + /* Free buffer used for Key stream */ + mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, + pCmd->pDst->pFrags[0].bufPhysAddr, + pCmd->pDst->pFrags[0].bufVirtPtr, + pCmd->pDst->pFrags[0].memHandle); + + return MV_OK; +} + +/******************************************************************************* +* mvCesaCtrModeFinish - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_COMMAND* pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) +{ + mvOsFree(pCmd); +} + +/******************************************************************************* +* mvCesaParamCheck - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, + MV_U8* pFixOffset) +{ + MV_U8 fixOffset = 0xFF; + +/* + mvOsPrintf("mvCesaParamCheck:macOffset=%d digestOffset=%d cryptoOffset=%d ivOffset=%d cryptoLength=%d cryptoBlockSize=%d mbufSize=%d\n", + pCmd->macOffset, pCmd->digestOffset, pCmd->cryptoOffset, pCmd->ivOffset, + pCmd->cryptoLength, pSA->cryptoBlockSize, pCmd->pSrc->mbufSize); +*/ + + /* Check AUTH operation parameters */ + if( ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) + { + /* MAC offset should be at least 4 byte aligned */ + if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) + { + mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", + pCmd->macOffset); + return MV_BAD_PARAM; + } + /* Digest offset must be 4 byte aligned */ + if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) + { + mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", + pCmd->digestOffset); + return MV_BAD_PARAM; + } + /* In addition all offsets should be the same alignment: 8 or 4 */ + if(fixOffset == 0xFF) + { + fixOffset = (pCmd->macOffset % 8); + } + else + { + if( (pCmd->macOffset % 8) != fixOffset) + { + mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", + pCmd->macOffset, fixOffset); + return MV_BAD_PARAM; + } + } + if( (pCmd->digestOffset % 8) != fixOffset) + { + mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", + pCmd->digestOffset, fixOffset); + return MV_BAD_PARAM; + } + } + /* Check CRYPTO operation parameters */ + if( ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) + { + /* CryptoOffset should be at least 4 byte aligned */ + if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) + { + mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", + pCmd->cryptoOffset); + return MV_BAD_PARAM; + } + /* cryptoLength should be the whole number of blocks */ + if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) + { + mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", + pCmd->cryptoLength, pSA->cryptoBlockSize); + return MV_BAD_PARAM; + } + if(fixOffset == 0xFF) + { + fixOffset = (pCmd->cryptoOffset % 8); + } + else + { + /* In addition all offsets should be the same alignment: 8 or 4 */ + if( (pCmd->cryptoOffset % 8) != fixOffset) + { + mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", + pCmd->cryptoOffset, fixOffset); + return MV_BAD_PARAM; + } + } + + /* check for CBC mode */ + if(pSA->cryptoIvSize > 0) + { + /* cryptoIV must not be part of CryptoLength */ + if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && + (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) + { + mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", + pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); + return MV_BAD_PARAM; + } + + /* ivOffset must be 4 byte aligned */ + if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) + { + mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", + pCmd->ivOffset); + return MV_BAD_PARAM; + } + /* In addition all offsets should be the same alignment: 8 or 4 */ + if( (pCmd->ivOffset % 8) != fixOffset) + { + mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", + pCmd->ivOffset, fixOffset); + return MV_BAD_PARAM; + } + } + } + return MV_OK; +} + +/******************************************************************************* +* mvCesaFragParamCheck - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) +{ + int offset; + + if( ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) + { + /* macOffset must be less that SRAM buffer size */ + if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) + { + mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", + pCmd->macOffset); + return MV_BAD_PARAM; + } + /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ + if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || + ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= + sizeof(cesaSramVirtPtr->buf)) ) + { + mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", + pCmd->macLength, pCmd->pSrc->mbufSize); + return MV_BAD_PARAM; + } + } + + if( ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) + { + /* cryptoOffset must be less that SRAM buffer size */ + /* 4 for possible fixOffset */ + if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) + { + mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", + pCmd->cryptoOffset); + return MV_BAD_PARAM; + } + + /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ + if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || + ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= + (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) + { + mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", + pCmd->cryptoLength, pCmd->pSrc->mbufSize); + return MV_BAD_PARAM; + } + } + + /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ + if( ((pSA->config & MV_CESA_OPERATION_MASK) == + (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || + ((pSA->config & MV_CESA_OPERATION_MASK) == + (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) + { + if( (mvCtrlModelGet() == MV_5182_DEV_ID) || + ( (mvCtrlModelGet() == MV_5181_DEV_ID) && + (mvCtrlRevGet() >= MV_5181L_A0_REV) && + (pCmd->macLength >= (1 << 14)) ) ) + { + return MV_NOT_ALLOWED; + } + + /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ + if(pCmd->cryptoOffset > pCmd->macOffset) + { + offset = pCmd->cryptoOffset - pCmd->macOffset; + } + else + { + offset = pCmd->macOffset - pCmd->cryptoOffset; + } + + if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) + { +/* + mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", + pSA->cryptoBlockSize); +*/ + return MV_NOT_ALLOWED; + } + /* Digest must not be part of CryptoLength */ + if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && + (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) + { +/* + mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", + pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); +*/ + return MV_NOT_ALLOWED; + } + } + return MV_OK; +} + +/******************************************************************************* +* mvCesaFragSizeFind - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, +* int cryptoOffset, int macOffset, +* +* OUTPUT: +* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, + int cryptoOffset, int macOffset, + int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) +{ + MV_CESA_COMMAND *pCmd = pReq->pCmd; + int cryptoDataSize, macDataSize, copySize; + + cryptoDataSize = macDataSize = 0; + copySize = *pCopySize; + + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + cryptoDataSize = MV_MIN( (copySize - cryptoOffset), + (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); + + /* cryptoSize for each fragment must be the whole number of blocksSize */ + if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) + { + cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); + copySize = cryptoOffset + cryptoDataSize; + } + } + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + macDataSize = MV_MIN( (copySize - macOffset), + (pCmd->macLength - (pReq->frags.macSize + 1))); + + /* macSize for each fragment (except last) must be the whole number of blocksSize */ + if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) + { + macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); + copySize = macOffset + macDataSize; + } + cryptoDataSize = copySize - cryptoOffset; + } + *pCopySize = copySize; + + if(pCryptoDataSize != NULL) + *pCryptoDataSize = cryptoDataSize; + + if(pMacDataSize != NULL) + *pMacDataSize = macDataSize; +} diff --git a/board/mv_feroceon/mv_hal/cesa/mvCesa.h b/board/mv_feroceon/mv_hal/cesa/mvCesa.h new file mode 100644 index 0000000..12ee24e --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/mvCesa.h @@ -0,0 +1,414 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator +* +* DESCRIPTION: +* This header file contains macros typedefs and function declaration for +* the Marvell Cryptographic Engines and Security Accelerator. +* +*******************************************************************************/ + +#ifndef __mvCesa_h__ +#define __mvCesa_h__ + +#include "mvOs.h" +#include "mvCommon.h" +#include "mvDebug.h" + +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#include "cesa/mvMD5.h" +#include "cesa/mvSHA1.h" + +#include "cesa/mvCesa.h" +#include "cesa/AES/mvAes.h" +#include "mvSysHwConfig.h" + +#ifdef MV_INCLUDE_IDMA +#include "idma/mvIdma.h" +#include "idma/mvIdmaRegs.h" +#else +/* Redefine MV_DMA_DESC structure */ +typedef struct _mvDmaDesc +{ + MV_U32 byteCnt; /* The total number of bytes to transfer */ + MV_U32 phySrcAdd; /* The physical source address */ + MV_U32 phyDestAdd; /* The physical destination address */ + MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ + /* then this pointer should point to the */ + /* physical address of the next descriptor, */ + /* otherwise it should be NULL. */ +}MV_DMA_DESC; +#endif /* MV_INCLUDE_IDMA */ + +#include "cesa/mvCesaRegs.h" + +#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ + +#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ +#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ + +#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE + +#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ +#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ +#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ +#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ +#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ + +#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH + +#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ +#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ + +#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ + +#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE + +#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ + +typedef struct +{ + MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; + MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; + MV_CESA_OPERATION operation; + MV_CESA_DIRECTION direction; + MV_CESA_CRYPTO_ALG cryptoAlgorithm; + MV_CESA_CRYPTO_MODE cryptoMode; + MV_U8 cryptoKeyLength; + MV_CESA_MAC_MODE macMode; + MV_U8 macKeyLength; + MV_U8 digestSize; + +} MV_CESA_OPEN_SESSION; + +typedef struct +{ + MV_BUF_INFO *pFrags; + MV_U16 numFrags; + MV_U16 mbufSize; + +} MV_CESA_MBUF; + +typedef struct +{ + void* pReqPrv; /* instead of reqId */ + MV_U32 retCode; + MV_16 sessionId; + +} MV_CESA_RESULT; + +typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); + + +typedef struct +{ + void* pReqPrv; /* instead of reqId */ + MV_CESA_MBUF* pSrc; + MV_CESA_MBUF* pDst; + MV_CESA_CALLBACK* pFuncCB; + MV_16 sessionId; + MV_U16 ivFromUser; + MV_U16 ivOffset; + MV_U16 cryptoOffset; + MV_U16 cryptoLength; + MV_U16 digestOffset; + MV_U16 macOffset; + MV_U16 macLength; + MV_BOOL skipFlush; +} MV_CESA_COMMAND; + + + +MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); +MV_STATUS mvCesaFinish (void); +MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); +MV_STATUS mvCesaSessionClose(short sid); +MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); + +MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); + +MV_U32 mvCesaInProcessGet(void); +MV_STATUS mvCesaReadyDispatch(void); +MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); +MV_BOOL mvCesaIsReady(void); + +int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); +MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, + int offset, int size); +MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, + int offset, int size); +MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, + MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); +MV_STATUS mvCesaUpdateSADSize(MV_U32 size); +/********** Debug functions ********/ + +void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); +void mvCesaDebugSA(short sid, int mode); +void mvCesaDebugStats(void); +void mvCesaDebugStatsClear(void); +void mvCesaDebugRegs(void); +void mvCesaDebugStatus(void); +void mvCesaDebugQueue(int mode); +void mvCesaDebugSram(int mode); +void mvCesaDebugSAD(int mode); + + +/******** CESA Private definitions ********/ +#if (MV_CESA_VERSION >= 2) +#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) +#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ + | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ + | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ + | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ + | MV_CESA_TDMA_ENABLE_MASK +#else +#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ + | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ + /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ + | MV_CESA_TDMA_ENABLE_MASK + +#endif +#else +#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ + | ICCLR_SRC_BURST_LIM_128BYTE \ + | ICCLR_INT_MODE_MASK \ + | ICCLR_BLOCK_MODE \ + | ICCLR_CHAN_ENABLE \ + | ICCLR_DESC_MODE_16M +#endif /* MV_CESA_VERSION >= 2 */ + +#define MV_CESA_MAX_PKT_SIZE (64 * 1024) +#define MV_CESA_MAX_MBUF_FRAGS 20 + +#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) + +#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) + +#define MAX_CESA_CHAIN_LENGTH 20 + +typedef enum +{ + MV_CESA_IDLE = 0, + MV_CESA_PENDING, + MV_CESA_PROCESS, + MV_CESA_READY, +#if (MV_CESA_VERSION >= 3) + MV_CESA_CHAIN, +#endif +} MV_CESA_STATE; + + +/* Session database */ + +/* Map of Key materials of the session in SRAM. + * Each field must be 8 byte aligned + * Total size: 32 + 24 + 24 = 80 bytes + */ +typedef struct +{ + MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; + MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; + MV_U8 reservedInner[4]; + MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; + MV_U8 reservedOuter[4]; + +} MV_CESA_SRAM_SA; + +typedef struct +{ + MV_CESA_SRAM_SA* pSramSA; + MV_U8* sramSABuff; /* holds initial allocation virtual address */ + MV_U32 sramSABuffSize; + MV_ULONG sramSAPhysAddr; /* holds initial allocation physical address */ + MV_U32 memHandle; + MV_U32 config; + MV_U8 cryptoKeyLength; + MV_U8 cryptoIvSize; + MV_U8 cryptoBlockSize; + MV_U8 digestSize; + MV_U8 macKeyLength; + MV_U8 ctrMode; + MV_U32 count; +} MV_CESA_SA; + +/* DMA list management */ +typedef struct +{ + MV_DMA_DESC* pDmaFirst; + MV_DMA_DESC* pDmaLast; + +} MV_CESA_DMA; + + +typedef struct +{ + MV_U8 numFrag; + MV_U8 nextFrag; + int bufOffset; + int cryptoSize; + int macSize; + int newDigestOffset; + MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; + +} MV_CESA_FRAGS; + +/* Request queue */ +typedef struct +{ + MV_U8 state; + MV_U8 fragMode; + MV_U8 fixOffset; + MV_CESA_COMMAND* pCmd; + MV_CESA_COMMAND* pOrgCmd; + MV_BUF_INFO dmaDescBuf; + MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; + MV_BUF_INFO cesaDescBuf; + MV_CESA_DESC* pCesaDesc; + MV_CESA_FRAGS frags; + + +} MV_CESA_REQ; + + +/* SRAM map */ +/* Total SRAM size calculation */ +/* SRAM size = + * MV_CESA_MAX_BUF_SIZE + + * sizeof(MV_CESA_DESC) + + * MV_CESA_MAX_IV_LENGTH + + * MV_CESA_MAX_IV_LENGTH + + * MV_CESA_MAX_DIGEST_SIZE + + * sizeof(MV_CESA_SRAM_SA) + * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes + * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes + */ +typedef struct +{ + MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; + MV_CESA_DESC desc; + MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; + MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; + MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; + MV_CESA_SRAM_SA sramSA; + +} MV_CESA_SRAM_MAP; + + +typedef struct +{ + MV_U32 openedCount; + MV_U32 closedCount; + MV_U32 fragCount; + MV_U32 reqCount; + MV_U32 maxReqCount; + MV_U32 procCount; + MV_U32 readyCount; + MV_U32 notReadyCount; + MV_U32 startCount; +#if (MV_CESA_VERSION >= 3) + MV_U32 maxChainUsage; +#endif + +} MV_CESA_STATS; + + +/* External variables */ + +extern MV_CESA_STATS cesaStats; +extern MV_CESA_FRAGS cesaFrags; + +extern MV_BUF_INFO cesaSramSaBuf; + +extern MV_CESA_SA** pCesaSAD; +extern MV_U32 cesaMaxSA; + +extern MV_CESA_REQ* pCesaReqFirst; +extern MV_CESA_REQ* pCesaReqLast; +extern MV_CESA_REQ* pCesaReqEmpty; +extern MV_CESA_REQ* pCesaReqProcess; +extern int cesaQueueDepth; +extern int cesaReqResources; +#if (MV_CESA_VERSION>= 3) +extern MV_U32 cesaChainLength; +#endif + +extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; +extern MV_U32 cesaSramPhysAddr; + +static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) +{ + return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); +} + +/* Additional DEBUG functions */ +void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); +void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); +void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); + + + +#endif /* __mvCesa_h__ */ diff --git a/board/mv_feroceon/mv_hal/cesa/mvCesaDebug.c b/board/mv_feroceon/mv_hal/cesa/mvCesaDebug.c new file mode 100644 index 0000000..3606fa6 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/mvCesaDebug.c @@ -0,0 +1,487 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "mvDebug.h" + +#include "cesa/mvMD5.h" +#include "cesa/mvSHA1.h" + +#include "cesa/mvCesa.h" +#include "cesa/mvCesaRegs.h" +#include "cesa/AES/mvAes.h" + +static const char* mvCesaDebugStateStr(MV_CESA_STATE state) +{ + switch(state) + { + case MV_CESA_IDLE: + return "Idle"; + + case MV_CESA_PENDING: + return "Pend"; + + case MV_CESA_PROCESS: + return "Proc"; + + case MV_CESA_READY: + return "Ready"; + + default: + break; + } + return "Unknown"; +} + +static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) +{ + switch(oper) + { + case MV_CESA_MAC_ONLY: + return "MacOnly"; + + case MV_CESA_CRYPTO_ONLY: + return "CryptoOnly"; + + case MV_CESA_MAC_THEN_CRYPTO: + return "MacCrypto"; + + case MV_CESA_CRYPTO_THEN_MAC: + return "CryptoMac"; + + default: + break; + } + return "Null"; +} + +static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) +{ + switch(cryptoAlg) + { + case MV_CESA_CRYPTO_DES: + return "DES"; + + case MV_CESA_CRYPTO_3DES: + return "3DES"; + + case MV_CESA_CRYPTO_AES: + return "AES"; + + default: + break; + } + return "Null"; +} + +static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) +{ + switch(macMode) + { + case MV_CESA_MAC_MD5: + return "MD5"; + + case MV_CESA_MAC_SHA1: + return "SHA1"; + + case MV_CESA_MAC_HMAC_MD5: + return "HMAC-MD5"; + + case MV_CESA_MAC_HMAC_SHA1: + return "HMAC_SHA1"; + + default: + break; + } + return "Null"; +} + +void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) +{ + mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", + pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, + pCmd->pFuncCB, pCmd->sessionId); + mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", + pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, + pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); +} + +/* no need to use in tool */ +void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) +{ + int frag, len, fragOffset; + + if(str != NULL) + mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", + str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); + + frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); + if(frag == MV_INVALID) + { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return; + } + + for(; fragnumFrags; frag++) + { + mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", + frag, pMbuf->pFrags[frag].bufVirtPtr, + pMbuf->pFrags[frag].bufSize); + if(size > 0) + { + len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); + mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); + size -= len; + fragOffset = 0; + } + } +} + +void mvCesaDebugRegs(void) +{ + mvOsPrintf("\t CESA Registers:\n"); + + mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", + MV_CESA_CMD_REG, + MV_REG_READ( MV_CESA_CMD_REG ) ); + + mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", + MV_CESA_CHAN_DESC_OFFSET_REG, + MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); + + mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", + MV_CESA_CFG_REG, + MV_REG_READ( MV_CESA_CFG_REG ) ); + + mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", + MV_CESA_STATUS_REG, + MV_REG_READ( MV_CESA_STATUS_REG ) ); + + mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", + MV_CESA_ISR_CAUSE_REG, + MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); + + mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", + MV_CESA_ISR_MASK_REG, + MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); +#if (MV_CESA_VERSION >= 2) + mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_CTRL_REG, + MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_BYTE_COUNT_REG, + MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_SRC_ADDR_REG, + MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_DST_ADDR_REG, + MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_NEXT_DESC_PTR_REG, + MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_CURR_DESC_PTR_REG, + MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_ERROR_CAUSE_REG, + MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_ERROR_MASK_REG, + MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); + +#endif +} + +void mvCesaDebugStatus(void) +{ + mvOsPrintf("\n\t CESA Status\n\n"); + + mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", + pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), + cesaReqResources); +#if (MV_CESA_VERSION >= 3) + mvOsPrintf("chainLength=%u\n",cesaChainLength); +#else + mvOsPrintf("\n"); +#endif + + mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", + pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); + + mvOsPrintf("\n"); + + mvCesaDebugRegs(); + mvCesaDebugStats(); + mvCesaDebugStatsClear(); +} + +void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) +{ + mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", + pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); + + mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", + pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, + pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); + + mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", + pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, + pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); +} + +void mvCesaDebugQueue(int mode) +{ + mvOsPrintf("\n\t CESA Request Queue:\n\n"); + + mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", + pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); + + mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", + pCesaReqEmpty, pCesaReqProcess, + cesaReqResources); + + if(mode != 0) + { + int count = 0; + MV_CESA_REQ* pReq = pCesaReqFirst; + + for(count=0; countstate), + pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); + if(pReq->fragMode != MV_CESA_FRAG_NONE) + { + int frag; + + mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", + &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, + pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); + for(frag=0; fragfrags.numFrag; frag++) + { + mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, + pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); + } + } + if(mode > 1) + { + /* Print out Command */ + mvCesaDebugCmd(pReq->pCmd, mode); + + /* Print out Descriptor */ + mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); + } + pReq++; + } + } +} + + +void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) +{ + if(pSramSA == NULL) + { + mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); + return; + } + mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", + pSramSA, sizeof(MV_CESA_SRAM_SA)); + + if(mode != 0) + { + mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", + pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); + mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); + + mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", + pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); + mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); + + mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", + pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); + mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); + } +} + +void mvCesaDebugSA(short sid, int mode) +{ + MV_CESA_OPERATION oper; + MV_CESA_DIRECTION dir; + MV_CESA_CRYPTO_ALG cryptoAlg; + MV_CESA_CRYPTO_MODE cryptoMode; + MV_CESA_MAC_MODE macMode; + MV_CESA_SA* pSA = pCesaSAD[sid]; + + if(pSA != NULL) + { + /*if(((pSA->count != 0) && (mode > 0)) || (mode >= 2)) + {*/ + mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", + sid, pSA, + (pSA != NULL) ? "Valid" : "Invalid", pSA->count); + + oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; + dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; + mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), + (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); + if(oper != MV_CESA_MAC_ONLY) + { + cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; + cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; + mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), + (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); + } + if(oper != MV_CESA_CRYPTO_ONLY) + { + macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; + mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); + } + mvOsPrintf("\n"); + + if(mode > 0) + { + mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", + pCesaSAD[sid]->config, pCesaSAD[sid]->cryptoKeyLength, + pCesaSAD[sid]->digestSize); + + mvCesaDebugSramSA(pCesaSAD[sid]->pSramSA, mode); + } + /*}*/ + } +} + + +/**/ +void mvCesaDebugSram(int mode) +{ + mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", + sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); + + mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", + MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); + if(mode != 0) + mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); + + mvOsPrintf("\n"); + mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", + sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); + if(mode != 0) + { + mvOsPrintf("\n"); + mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); + } + mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", + MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); + if(mode != 0) + { + mvOsPrintf("\n"); + mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); + } + mvOsPrintf("\n"); + mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); +} + +void mvCesaDebugSAD(int mode) +{ + int sid; + + mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", + pCesaSAD, cesaMaxSA); + + for(sid=0; sid= 3) + mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); +#endif + mvOsPrintf("\n"); + mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", + cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); +} + +void mvCesaDebugStatsClear(void) +{ + memset(&cesaStats, 0, sizeof(cesaStats)); +} diff --git a/board/mv_feroceon/mv_hal/cesa/mvCesaRegs.h b/board/mv_feroceon/mv_hal/cesa/mvCesaRegs.h new file mode 100644 index 0000000..6b7ce12 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/mvCesaRegs.h @@ -0,0 +1,357 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvCesaRegs_h__ +#define __mvCesaRegs_h__ + +#include "mvTypes.h" + +typedef struct +{ + /* word 0 */ + MV_U32 config; + /* word 1 */ + MV_U16 cryptoSrcOffset; + MV_U16 cryptoDstOffset; + /* word 2 */ + MV_U16 cryptoDataLen; + MV_U16 reserved1; + /* word 3 */ + MV_U16 cryptoKeyOffset; + MV_U16 reserved2; + /* word 4 */ + MV_U16 cryptoIvOffset; + MV_U16 cryptoIvBufOffset; + /* word 5 */ + MV_U16 macSrcOffset; + MV_U16 macTotalLen; + /* word 6 */ + MV_U16 macDigestOffset; + MV_U16 macDataLen; + /* word 7 */ + MV_U16 macInnerIvOffset; + MV_U16 macOuterIvOffset; + +} MV_CESA_DESC; + +/* operation */ +typedef enum +{ + MV_CESA_MAC_ONLY = 0, + MV_CESA_CRYPTO_ONLY = 1, + MV_CESA_MAC_THEN_CRYPTO = 2, + MV_CESA_CRYPTO_THEN_MAC = 3, + + MV_CESA_MAX_OPERATION + +} MV_CESA_OPERATION; + +#define MV_CESA_OPERATION_OFFSET 0 +#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) + +/* mac algorithm */ +typedef enum +{ + MV_CESA_MAC_NULL = 0, + MV_CESA_MAC_MD5 = 4, + MV_CESA_MAC_SHA1 = 5, + MV_CESA_MAC_HMAC_MD5 = 6, + MV_CESA_MAC_HMAC_SHA1 = 7, + +} MV_CESA_MAC_MODE; + +#define MV_CESA_MAC_MODE_OFFSET 4 +#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) + +typedef enum +{ + MV_CESA_MAC_DIGEST_FULL = 0, + MV_CESA_MAC_DIGEST_96B = 1, + +} MV_CESA_MAC_DIGEST_SIZE; + +#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 +#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) + + +typedef enum +{ + MV_CESA_CRYPTO_NULL = 0, + MV_CESA_CRYPTO_DES = 1, + MV_CESA_CRYPTO_3DES = 2, + MV_CESA_CRYPTO_AES = 3, + +} MV_CESA_CRYPTO_ALG; + +#define MV_CESA_CRYPTO_ALG_OFFSET 8 +#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) + + +/* direction */ +typedef enum +{ + MV_CESA_DIR_ENCODE = 0, + MV_CESA_DIR_DECODE = 1, + +} MV_CESA_DIRECTION; + +#define MV_CESA_DIRECTION_BIT 12 +#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) + +/* crypto IV mode */ +typedef enum +{ + MV_CESA_CRYPTO_ECB = 0, + MV_CESA_CRYPTO_CBC = 1, + + /* NO HW Support */ + MV_CESA_CRYPTO_CTR = 10, + +} MV_CESA_CRYPTO_MODE; + +#define MV_CESA_CRYPTO_MODE_BIT 16 +#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) + +/* 3DES mode */ +typedef enum +{ + MV_CESA_CRYPTO_3DES_EEE = 0, + MV_CESA_CRYPTO_3DES_EDE = 1, + +} MV_CESA_CRYPTO_3DES_MODE; + +#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 +#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) + + +/* AES Key Length */ +typedef enum +{ + MV_CESA_CRYPTO_AES_KEY_128 = 0, + MV_CESA_CRYPTO_AES_KEY_192 = 1, + MV_CESA_CRYPTO_AES_KEY_256 = 2, + +} MV_CESA_CRYPTO_AES_KEY_LEN; + +#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 +#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) + +/* Fragmentation mode */ +typedef enum +{ + MV_CESA_FRAG_NONE = 0, + MV_CESA_FRAG_FIRST = 1, + MV_CESA_FRAG_LAST = 2, + MV_CESA_FRAG_MIDDLE = 3, + +} MV_CESA_FRAG_MODE; + +#define MV_CESA_FRAG_MODE_OFFSET 30 +#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) +/*---------------------------------------------------------------------------*/ + +/********** Security Accelerator Command Register **************/ +#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) + +#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 +#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) + +#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 +#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) + +/********** Security Accelerator Descriptor Pointers Register **********/ +#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) + +/********** Security Accelerator Configuration Register **********/ +#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) + +#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 +#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) + +#define MV_CESA_CFG_WAIT_DMA_BIT 7 +#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) + +#define MV_CESA_CFG_ACT_DMA_BIT 9 +#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) + +#define MV_CESA_CFG_CHAIN_MODE_BIT 11 +#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) + +/********** Security Accelerator Status Register ***********/ +#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) + +#define MV_CESA_STATUS_ACTIVE_BIT 0 +#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) + +#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 +#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) + + +/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ +#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) + +/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ +#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) + +#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) +#define MV_CESA_CAUSE_DES_MASK (1 << 1) +#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) +#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) +#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) + +#define MV_CESA_CAUSE_ACC_BIT 5 +#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) + +#define MV_CESA_CAUSE_ACC_DMA_BIT 7 +#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) +#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) + +#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 +#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) + +#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 +#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) + +#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 +#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) + + +#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) +#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) +#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) + +#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) + +#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) +#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) + +#define MV_CESA_AUTH_ALGORITHM_BIT 0 +#define MV_CESA_AUTH_ALGORITHM_MD5 (0< +wait_queue_head_t cesaTest_waitq; +spinlock_t cesaLock; + +#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) +#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); + +#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) +#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) +#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) + +#define CESA_TEST_TICK_GET() jiffies +#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) + +#elif defined(MV_NETBSD) + +#include +#include +static int cesaLock; + +#define CESA_TEST_LOCK(flags) flags = splnet() +#define CESA_TEST_UNLOCK(flags) splx(flags) + +#define CESA_TEST_WAIT_INIT() /* nothing */ +#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) +#define CESA_TEST_WAIT(cond, ms) \ +do { \ + while (!(cond)) \ + tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ +} while (/*CONSTCOND*/0) + +#define CESA_TEST_TICK_GET() hardclock_ticks +#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) + +#define request_irq(i,h,t,n,a) \ + !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) + +#else +#error "Only Linux, VxWorks, or NetBSD OS are supported" +#endif + +#include "mvDebug.h" + +#include "mvSysHwConfig.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cntmr/mvCntmr.h" +#include "cesa/mvCesa.h" +#include "cesa/mvCesaRegs.h" +#include "cesa/mvMD5.h" +#include "cesa/mvSHA1.h" +#include "ctrlEnv/sys/mvSysCesa.h" + +#if defined(CONFIG_MV646xx) +#include "marvell_pic.h" +#endif + +#define MV_CESA_USE_TIMER_ID 0 +#define CESA_DEF_BUF_SIZE 1500 +#define CESA_DEF_BUF_NUM 1 +#define CESA_DEF_SESSION_NUM 32 + +#define CESA_DEF_ITER_NUM 100 + +#define CESA_DEF_REQ_SIZE 256 + + +/* CESA Tests Debug */ +#undef CESA_TEST_DEBUG + +#ifdef CESA_TEST_DEBUG + +# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg +# define CESA_TEST_DEBUG_CODE(code) code + +typedef struct +{ + int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ + MV_U32 timeStamp; + MV_U32 cause; + MV_U32 realCause; + MV_U32 dmaCause; + int resources; + MV_CESA_REQ* pReqReady; + MV_CESA_REQ* pReqEmpty; + MV_CESA_REQ* pReqProcess; +} MV_CESA_TEST_TRACE; + +#define MV_CESA_TEST_TRACE_SIZE 25 + +static int cesaTestTraceIdx = 0; +static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; + +static void cesaTestTraceAdd(int type, MV_U32 cause) +{ + cesaTestTrace[cesaTestTraceIdx].type = type; + cesaTestTrace[cesaTestTraceIdx].cause = cause; + cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); + cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); + cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; + cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; + cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; + cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; + cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); + cesaTestTraceIdx++; + if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) + cesaTestTraceIdx = 0; +} + +#else + +# define CESA_TEST_DEBUG_PRINT(msg) +# define CESA_TEST_DEBUG_CODE(code) + +#endif /* CESA_TEST_DEBUG */ + +int cesaExpReqId=0; +int cesaCbIter=0; + +int cesaIdx; +int cesaIteration; +int cesaRateSize; +int cesaReqSize; +unsigned long cesaTaskId; +int cesaBufNum; +int cesaBufSize; +int cesaCheckOffset; +int cesaCheckSize; +int cesaCheckMode; +int cesaTestIdx; +int cesaCaseIdx; + + +MV_U32 cesaTestIsrCount = 0; +MV_U32 cesaTestIsrMissCount = 0; + +MV_U32 cesaCryptoError = 0; +MV_U32 cesaReqIdError = 0; +MV_U32 cesaError = 0; + +char* cesaHexBuffer = NULL; + +char* cesaBinBuffer = NULL; +char* cesaExpBinBuffer = NULL; + +char* cesaInputHexStr = NULL; +char* cesaOutputHexStr = NULL; + +MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; + +MV_CESA_COMMAND* cesaCmdRing; +MV_CESA_RESULT cesaResult; + +int cesaTestFull = 0; + +MV_BOOL cesaIsReady = MV_FALSE; +MV_U32 cesaCycles = 0; +MV_U32 cesaBeginTicks = 0; +MV_U32 cesaEndTicks = 0; +MV_U32 cesaRate = 0; +MV_U32 cesaRateAfterDot = 0; + +void *cesaTestOSHandle = NULL; + +enum +{ + CESA_FAST_CHECK_MODE = 0, + CESA_FULL_CHECK_MODE, + CESA_NULL_CHECK_MODE, + CESA_SHOW_CHECK_MODE, + CESA_SW_SHOW_CHECK_MODE, + CESA_SW_NULL_CHECK_MODE, + + CESA_MAX_CHECK_MODE +}; + +enum +{ + DES_TEST_TYPE = 0, + TRIPLE_DES_TEST_TYPE = 1, + AES_TEST_TYPE = 2, + MD5_TEST_TYPE = 3, + SHA_TEST_TYPE = 4, + COMBINED_TEST_TYPE = 5, + + MAX_TEST_TYPE +}; + +/* Tests data base */ +typedef struct +{ + short sid; + char cryptoAlgorithm; /* DES/3DES/AES */ + char cryptoMode; /* ECB or CBC */ + char macAlgorithm; /* MD5 / SHA1 */ + char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ + char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ + unsigned char* pCryptoKey; + int cryptoKeySize; + unsigned char* pMacKey; + int macKeySize; + const char* name; + +} MV_CESA_TEST_SESSION; + +typedef struct +{ + MV_CESA_TEST_SESSION* pSessions; + int numSessions; + +} MV_CESA_TEST_DB_ENTRY; + +typedef struct +{ + char* plainHexStr; + char* cipherHexStr; + unsigned char* pCryptoIV; + int cryptoLength; + int macLength; + int digestOffset; + +} MV_CESA_TEST_CASE; + +typedef struct +{ + int size; + const char* outputHexStr; + +} MV_CESA_SIZE_TEST; + +static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; + +static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; +static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; + + +static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; + +static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; + +static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; + +static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, + 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; + + +static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, + 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, + 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; + +/* Input ASCII string: The quick brown fox jump */ +static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; +static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; + +static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, + 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, + 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; + +static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; + +static char plain3des2[] = "326a494cd33fe756"; + +static char cipher3desCbc2[] = "8e29f75ea77e5475" + "b22b8d66de970692"; + +static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, + 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, + 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; + +static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; + +static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; + +static char cipher3desCbc3[] = "3d1de3cc132e3b65" + "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; + +static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, + 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; + +static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, + 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; + +static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; + +static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; + +static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b}; + +static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa}; + +static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; + +static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, + 0x11, 0x12, 0x13, 0x14}; + + +static MV_CESA_TEST_SESSION desTestSessions[] = +{ +/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), + NULL, 0, + "DES ECB encode", + }, +/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), + NULL, 0, + "DES ECB decode", + }, +/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), + NULL, 0, + "DES CBC encode" + }, +/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), + NULL, 0, + "DES CBC decode" + }, +/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, NULL, 0, + "NULL Crypto Algorithm encode" + }, +}; + + +static MV_CESA_TEST_SESSION tripleDesTestSessions[] = +{ +/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + NULL, 0, + "3DES ECB encode", + }, +/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + NULL, 0, + "3DES ECB decode", + }, +/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + NULL, 0, + "3DES CBC encode" + }, +/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + NULL, 0, + "3DES CBC decode" + }, +/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + key3des1, sizeof(key3des1), + NULL, 0, + "3DES ECB encode" + }, +/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + key3des2, sizeof(key3des2), + NULL, 0, + "3DES ECB encode" + }, +/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + key3des3, sizeof(key3des3), + NULL, 0, + "3DES ECB encode" + }, +}; + + +static MV_CESA_TEST_SESSION aesTestSessions[] = +{ +/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), + NULL, 0, + "AES-128 ECB encode" + }, +/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), + NULL, 0, + "AES-128 ECB decode" + }, +/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), + NULL, 0, + "AES-128 CBC encode" + }, +/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), + NULL, 0, + "AES-128 CBC decode" + }, +/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), + NULL, 0, + "AES-192 ECB encode" + }, +/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), + NULL, 0, + "AES-192 ECB decode" + }, +/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), + NULL, 0, + "AES-256 ECB encode" + }, +/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), + NULL, 0, + "AES-256 ECB decode" + }, +/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), + NULL, 0, + "AES-128 CTR encode" + }, +}; + + +static MV_CESA_TEST_SESSION md5TestSessions[] = +{ +/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + mdKey1, sizeof(mdKey1), + "HMAC-MD5 Generate Signature" + }, +/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + mdKey1, sizeof(mdKey1), + "HMAC-MD5 Verify Signature" + }, +/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + mdKey2, sizeof(mdKey2), + "HMAC-MD5 Generate Signature" + }, +/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + mdKey2, sizeof(mdKey2), + "HMAC-MD5 Verify Signature" + }, +/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + mdKey4, sizeof(mdKey4), + "HMAC-MD5 Generate Signature" + }, +/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + NULL, 0, + "HASH-MD5 Generate Signature" + }, +}; + + +static MV_CESA_TEST_SESSION shaTestSessions[] = +{ +/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + shaKey1, sizeof(shaKey1), + "HMAC-SHA1 Generate Signature" + }, +/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + shaKey1, sizeof(shaKey1), + "HMAC-SHA1 Verify Signature" + }, +/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + shaKey2, sizeof(shaKey2), + "HMAC-SHA1 Generate Signature" + }, +/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + shaKey2, sizeof(shaKey2), + "HMAC-SHA1 Verify Signature" + }, +/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + shaKey4, sizeof(shaKey4), + "HMAC-SHA1 Generate Signature" + }, +/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + NULL, 0, + "HASH-SHA1 Generate Signature" + }, +}; + +static MV_CESA_TEST_SESSION combinedTestSessions[] = +{ +/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, MV_CESA_DES_KEY_LENGTH, + mdKey4, sizeof(mdKey4), + "DES + MD5 encode" + }, +/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, MV_CESA_DES_KEY_LENGTH, + shaKey4, sizeof(shaKey4), + "DES + SHA1 encode" + }, +/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + mdKey4, sizeof(mdKey4), + "3DES + MD5 encode" + }, +/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + shaKey4, sizeof(shaKey4), + "3DES + SHA1 encode" + }, +/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + mdKey4, sizeof(mdKey4), + "3DES CBC + MD5 encode" + }, +/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + shaKey4, sizeof(shaKey4), + "3DES CBC + SHA1 encode" + }, +/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), + mdKey4, sizeof(mdKey4), + "AES-128 CBC + MD5 encode" + }, +/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), + shaKey4, sizeof(shaKey4), + "AES-128 CBC + SHA1 encode" + }, +/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, + MV_CESA_DIR_DECODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + mdKey4, sizeof(mdKey4), + "HMAC-MD5 + 3DES decode" + }, +}; + + +static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = +{ + { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, + { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, + { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, + { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, + { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, + { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, + { NULL, 0 } +}; + + +char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; + +char cesaPlainAsciiText[] = "Now is the time for all "; +char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; +char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; +char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; +char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; + +char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; +char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; +char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; +char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; + +char cesaAsciiStr1[] = "Hi There"; +char cesaDataHexStr1[] = "4869205468657265"; +char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; +char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; +char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; +char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; + +char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" + "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" + "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" + "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; + +char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" + "0f3af07a9a31a9c684db207eb0ef8e4e" + "35907aa632c3ffdf868bb7b29d3d46ad" + "83ce9f9a102ee99d49a53e87f4c3da55"; + +char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" + "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" + "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" + "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" + "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; + +char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" + "c30e32ffedc0774e6aff6af0869f71aa" + "0f3af07a9a31a9c684db207eb0ef8e4e" + "35907aa632c3ffdf868bb7b29d3d46ad" + "83ce9f9a102ee99d49a53e87f4c3da55"; + +char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" + "000102030405060708090A0B0C0D0E0F" + "101112131415161718191A1B1C1D1E1F" + "20212223"; + +char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" + "C1CF48A89F2FFDD9CF4652E9EFDB72D7" + "4540A42BDE6D7836D59A5CEAAEF31053" + "25B2072F"; + + + +/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ +char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; +char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; +char cesaDataHexStr3[50*2+1] = ""; +char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; +char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; + +/* Ascii string is "abc" */ +char hashHexStr3[] = "616263"; +char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; +char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; + +char hashHexStr80[] = "31323334353637383930" + "31323334353637383930" + "31323334353637383930" + "31323334353637383930" + "31323334353637383930" + "31323334353637383930" + "31323334353637383930" + "31323334353637383930"; + +char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; + +char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; +char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; + +char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; +char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; + +char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; +char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; + + +static MV_CESA_TEST_CASE cesaTestCases[] = +{ + /* plainHexStr cipherHexStr IV crypto mac digest */ + /* Length Length Offset */ + /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, + /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, + /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, + /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, + /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, + /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, + /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, + /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, + /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, + /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, +/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, +/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, +/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, +/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, +/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, +/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, +/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, +/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, +/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, +/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, +/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, +/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, +/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, +/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, +/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, +/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, +/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, +/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, +}; + + +/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa + * Input 0xdd repeated "size" times + */ +static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = +{ + { 80, "7a031a640c14a4872814930b1ef3a5b2" }, + { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, + { 1000, "d00814f586a8b78a05724239d2531821" }, + { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, + { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, + { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, + { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, + { 1005, "e082790b4857fcfc266e92e59e608814" }, + { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, + { 1336, "e42edcce57d0b75b01aa09d71427948b" }, + { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, + { 1399, "0f44d793e744b24d53f44f295082ee8c" }, + { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, + { 1401, "e913858b484cbe2b384099ea88d8855b" }, + { 1402, "d9848a164af53620e0540c1d7d87629e" }, + { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, + { 1404, "12edd4f609416e3c936170360561b064" }, + { 1405, "7fc912718a05446395345009132bf562" }, + { 1406, "882f17425e579ff0d85a91a59f308aa0" }, + { 1407, "005cae408630a2fb5db82ad9db7e59da" }, + { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, + { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, + { 2048, "67caf64475650732def374ebb8bde3fd" }, + { 2049, "6c84f11f472825f7e6cd125c2981884b" }, + { 2050, "8999586754a73a99efbe4dbad2816d41" }, + { 2051, "ba6946b610e098d286bc81091659dfff" }, + { 2052, "d0afa01c92d4d13def2b024f36faed83" }, + { 3072, "61d8beac61806afa2585d74a9a0e6974" }, + { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, + { 3075, "ea4a6929be67e33e61ff475369248b73" }, + { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, + { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, + { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, + { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, + { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, + { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, + { 6528, "b1d707b027354aca152c45ee559ccd3f" }, + { 8192, "c600ea4429ac47f9941f09182166e51a" }, + {16384, "16e8754bfbeb4c649218422792267a37" }, + {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, + { 0, NULL }, +}; + +/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + */ +static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = +{ + { 80, "a456c4723fee6068530af5a2afa71627" }, + { 512, "f85c2a2344f5de68b432208ad13e5794" }, + { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, + { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, + { 1002, "5664f71800c011cc311cb6943339c1b8" }, + { 1003, "779c723b044c585dc7802b13e8501bdc" }, + { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, + { 1005, "d5f978954f5c38529d1679d2b714f068" }, + { 1006, "cd3efc827ce628b7281b72172693abf9" }, + { 1336, "6f04479910785878ae6335b8d1e87edf" }, + { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, + { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, + { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, + { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, + { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, + { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, + { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, + { 1405, "d1487bd42f6edd9b4dab316631159221" }, + { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, + { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, + { 1408, "a9e13335612c0356f5e2c27086e86c43" }, + { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, + { 2048, "396905c9b961cd0f6152abfb69c4449c" }, + { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, + { 2050, "3a2b4823bc4d0415656550226a63e34a" }, + { 2051, "dec60580d406c782540f398ad0bcc7e0" }, + { 2052, "32f76610a14310309eb748fe025081bf" }, + { 3072, "45edc1a42bf9d708a621076b63b774da" }, + { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, + { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, + { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, + { 4052, "81976bcaeb274223983996c137875cb8" }, + { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, + { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, + { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, + { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, + { 6528, "216f44f23047cfee03a7a64f88f9a995" }, + { 8192, "ac7a993b2cad54879dba1bde63e39097" }, + { 8320, "55ed7be9682d6c0025b3221a62088d08" }, + {16384, "c6c722087653b62007aea668277175e5" }, + {18432, "f1faca8e907872c809e14ffbd85792d6" }, + { 0, NULL }, +}; + +/* HASH-MD5 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * repeated "size" times + */ +static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = +{ + { 80, "57edf4a22be3c955ac49da2e2107b67a" }, + { 512, "c729ae8f0736cc377a9767a660eaa04e" }, + { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, + { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, + { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, + { 1003, "961753017feee04c9b93a8e51658a829" }, + { 1004, "dd68c4338608dcc87807a711636bf2af" }, + { 1005, "e338d567d3ce66bf69ada29658a8759b" }, + { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, + { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, + { 1344, "335a919805f370b9e402a62c6fe01739" }, + { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, + { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, + { 1401, "49590f61298a76719bc93a57a30136f5" }, + { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, + { 1403, "37073a02ab00ecba2645c57c228860db" }, + { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, + { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, + { 1406, "4b6695772a4c66313fa4871017d05f36" }, + { 1407, "d1539b97fbfda1c075624e958de19c5b" }, + { 1408, "b801b9b69920907cd018e8063092ede9" }, + { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, + { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, + { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, + { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, + { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, + { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, + { 3072, "37d158e33b21390822739d13db7b87fe" }, + { 3074, "aef3b209d01d39d0597fe03634bbf441" }, + { 3075, "335ffb428eabf210bada96d74d5a4012" }, + { 4048, "2434c2b43d798d2819487a886261fc64" }, + { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, + { 4058, "856781f85616c341c3533d090c1e1e84" }, + { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, + { 6150, "a09a353be7795fac2401dac5601872e6" }, + { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, + { 6528, "3d47aa193a8540c091e7e02f779e6751" }, + { 8192, "d3164e710c0626f6f395b38f20141cb7" }, + { 8320, "b727589d9183ff4e8491dd24466974a3" }, + {16384, "3f54d970793d2274d5b20d10a69938ac" }, + {18432, "f558511dcf81985b7a1bb57fad970531" }, + { 0, NULL }, +}; + + +/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa + * 0xaa, 0xaa, 0xaa, 0xaa + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + */ +static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = +{ + { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, + { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, + { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, + { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, + { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, + { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, + { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, + { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, + { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, + { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, + { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, + { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, + { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, + { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, + { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, + { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, + { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, + { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, + { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, + { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, + { 1408, "3987511182b18473a564436003139b808fa46343" }, + { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, + { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, + { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, + { 2050, "8831939904009338de10e7fa670847041387807d" }, + { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, + { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, + { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, + { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, + { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, + { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, + { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, + { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, + { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, + { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, + { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, + { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, + { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, + { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, + {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, + {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, + { 0, NULL }, +}; + +/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + */ +static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = +{ + { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, + { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, + { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, + { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, + { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, + { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, + { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, + { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, + { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, + { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, + { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, + { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, + { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, + { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, + { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, + { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, + { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, + { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, + { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, + { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, + { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, + { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, + { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, + { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, + { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, + { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, + { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, + { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, + { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, + { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, + { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, + { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, + { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, + { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, + { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, + { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, + { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, + { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, + { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, + {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, + {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, + { 0, NULL }, +}; + +/* HASH-SHA1 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * repeated "size" times + */ +static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = +{ + { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, + { 512, "f14516a08948fa27917a974d219741a697ba0087" }, + { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, + { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, + { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, + { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, + { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, + { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, + { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, + { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, + { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, + { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, + { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, + { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, + { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, + { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, + { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, + { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, + { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, + { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, + { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, + { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, + { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, + { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, + { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, + { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, + { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, + { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, + { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, + { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, + { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, + { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, + { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, + { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, + { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, + { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, + { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, + { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, + { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, + {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, + {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, + { 0, NULL }, +}; + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = +{ + { 64, "9586962a2aaaef28803dec2e17807a7f" }, + { 80, "b7726a03aad490bd6c5a452a89a1b271" }, + { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, + { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, + { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, + { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, + { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, + { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, + { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, + { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, + { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, + { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, + { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, + { 6400, "44e4613496ba622deb0e7cb768135a2f" }, + { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, + { 8192, "d581780b7163138a0f412be681457d82" }, + {16384, "03b8ac05527faaf1bed03df149c65ccf" }, + {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, + { 0, NULL }, +}; + + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = +{ + { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, + { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, + { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, + { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, + { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, + { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, + { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, + { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, + { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, + { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, + { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, + { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, + { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, + { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, + { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, + { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, + {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, + {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, + { 0, NULL }, +}; + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = +{ + { 64, "8d10e00802460ede0058c139ba48bd2d" }, + { 80, "6f463057e1a90e0e91ae505b527bcec0" }, + { 352, "4938d48bdf86aece2c6851e7c6079788" }, + { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, + { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, + { 1336, "44af60087b74ed07950088efbe3b126a" }, + { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, + { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, + { 1408, "4fb436624b02516fc9d1535466574bf9" }, + { 2048, "c909b0985c423d8d86719f701e9e83db" }, + { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, + { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, + { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, + { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, + { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, + { 8192, "afe101fbe745bb449ae4f50d10801456" }, + {16384, "9741706d0b1c923340c4660ff97cacdf" }, + {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, + { 0, NULL }, +}; + + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = +{ + { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, + { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, + { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, + { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, + { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, + { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, + { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, + { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, + { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, + { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, + { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, + { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, + { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, + { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, + { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, + { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, + {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, + {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, + { 0, NULL }, +}; + + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to AES block size (16 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = +{ + { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, + { 64, "7dba7fb988e80da609b1fea7254bced8" }, + { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, + { 352, "a1ceb9c2e3021002400d525187a9f38c" }, + { 512, "596c055c1c55db748379223164075641" }, + { 1008, "f920989c02f3b3603f53c99d89492377" }, + { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, + { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, + { 2048, "a917f0099c69eb94079a8421714b6aad" }, + { 3072, "693cd5033d7f5391d3c958519fa9e934" }, + { 4048, "139dca91bcff65b3c40771749052906b" }, + { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, + { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, + { 6528, "ad876f6297186a7be1f1b907ed860eda" }, + { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, + {16384, "60fda559c74f91df538100c9842f2f15" }, + {18432, "4a3eb1cba1fa45f3981270953f720c42" }, + { 0, NULL }, +}; + + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to AES block size (16 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = +{ + { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, + { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, + { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, + { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, + { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, + { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, + { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, + { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, + { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, + { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, + { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, + { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, + { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, + { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, + { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, + {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, + {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, + { 0, NULL }, +}; + + +void cesaTestPrintStatus(void); + + +/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ +MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, + MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); +MV_STATUS testClose(int idx); +MV_STATUS testOpen(int idx); +void close_session(int sid); +void cesaTestCheckReady(const MV_CESA_RESULT *r); +void cesaCheckReady(MV_CESA_RESULT* r); +void printTestResults(int idx, MV_STATUS status, int checkMode); +void cesaLastResult(void); +void cesaTestPrintReq(int req, int offset, int size); + +void cesaTestPrintStatus(void); +void cesaTestPrintSession(int idx); +void sizeTest(int testIdx, int iter, int checkMode); +void multiTest(int iter, int reqSize, int checkMode); +void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); +void multiSizeTest(int idx, int iter, int checkMode, char* inputData); +void cesaTest(int iter, int reqSize, int checkMode); +void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); +void combiTest(int iter, int reqSize, int checkMode); +void shaTest(int iter, int reqSize, int checkMode); +void mdTest(int iter, int reqSize, int checkMode); +void aesTest(int iter, int reqSize, int checkMode); +void tripleDesTest(int iter, int reqSize, int checkMode); +void desTest(int iter, int reqSize, int checkMode); +void cesaTestStop(void); +MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); +void cesaTestStart(int bufNum, int bufSize); + + +static MV_U32 getRate(MV_U32* remainder) +{ + MV_U32 kBits, milliSec, rate; + + milliSec = 0; + if( (cesaEndTicks - cesaBeginTicks) > 0) + { + milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); + } + if(milliSec == 0) + { + if(remainder != NULL) + *remainder = 0; + return 0; + } + + kBits = (cesaIteration*cesaRateSize*8)/1000; + rate = kBits/milliSec; + if(remainder != NULL) + *remainder = ((kBits % milliSec)*10)/milliSec; + + return rate; +} + +static char* extractMbuf(MV_CESA_MBUF *pMbuf, + int offset, int size, char* hexStr) +{ + mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); + mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); + + return hexStr; +} + +static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, + const char* hexString, int offset, + int checkSize) +{ + MV_BOOL isFailed = MV_FALSE; + MV_STATUS status; + int size = strlen(hexString)/2; + int checkedSize = 0; +/* + mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", + pMbuf, offset, checkSize, pMbuf->mbufSize); +*/ + if(pMbuf->mbufSize < (checkSize + offset)) + { + mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", + checkSize, offset, pMbuf->mbufSize); + return MV_TRUE; + } + status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); + if(status != MV_OK) + { + mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", + checkSize, pMbuf, cesaBinBuffer); + return MV_TRUE; + } +/* + mvDebugMemDump(cesaBinBuffer, size, 1); +*/ + mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); + + /* Compare buffers */ + while(checkSize > checkedSize) + { + size = MV_MIN(size, (checkSize - checkedSize)); + if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) + { + mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", + checkSize, size, checkedSize); + mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); + mvDebugMemDump(cesaExpBinBuffer, size, 1); + + isFailed = MV_TRUE; + break; + } + checkedSize += size; + } + + return isFailed; +} + +static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, + const char* hexString, + int offset, int reqSize) +{ + MV_STATUS status = MV_OK; + int copySize, size = strlen(hexString)/2; + + mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); + + copySize = 0; + while(reqSize > copySize) + { + size = MV_MIN(size, (reqSize - copySize)); + + status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); + if(status != MV_OK) + { + mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", + copySize, reqSize); + break; + } + copySize += size; + } + pMbuf->mbufSize = offset+copySize; + return status; +} + +static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) +{ + int testIdx, dbIdx = idx/100; + + if(dbIdx > MAX_TEST_TYPE) + { + mvOsPrintf("Wrong index %d - No such test type\n", idx); + return NULL; + } + testIdx = idx % 100; + + if(testIdx >= cesaTestsDB[dbIdx].numSessions) + { + mvOsPrintf("Wrong index %d - No such test\n", idx); + return NULL; + } + if(pTestIdx != NULL) + *pTestIdx = testIdx; + + return cesaTestsDB[dbIdx].pSessions; +} + +/* Debug */ +void cesaTestPrintReq(int req, int offset, int size) +{ + MV_CESA_MBUF* pMbuf; + + mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", + req, offset, size); + mvDebugMemDump(cesaCmdRing, 128, 4); + + pMbuf = cesaCmdRing[req].pSrc; + mvCesaDebugMbuf("src", pMbuf, offset,size); + pMbuf = cesaCmdRing[req].pDst; + mvCesaDebugMbuf("dst", pMbuf, offset, size); + + cesaTestPrintStatus(); +} + +void cesaLastResult(void) +{ + mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", + (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, + cesaResult.retCode); +} + +void printTestResults(int idx, MV_STATUS status, int checkMode) +{ + int testIdx; + MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); + + if(pTestSessions == NULL) + return; + + mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, + cesaIteration, cesaReqSize); + if( (status == MV_OK) && + (cesaCryptoError == 0) && + (cesaError == 0) && + (cesaReqIdError == 0) ) + { + mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", + cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); + } + else + { + mvOsPrintf("Failed, Status = 0x%x\n", status); + if(cesaCryptoError > 0) + mvOsPrintf("cryptoError : %d\n", cesaCryptoError); + if(cesaReqIdError > 0) + mvOsPrintf("reqIdError : %d\n", cesaReqIdError); + if(cesaError > 0) + mvOsPrintf("cesaError : %d\n", cesaError); + } + if(cesaTestIsrMissCount > 0) + mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); +} + +void cesaCheckReady(MV_CESA_RESULT* r) +{ + int reqId; + MV_CESA_MBUF *pMbuf; + MV_BOOL isFailed; + + cesaResult = *r; + reqId = (int)cesaResult.pReqPrv; + pMbuf = cesaCmdRing[reqId].pDst; + +/* + mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", + reqId, cesaCheckOffset, cesaCheckSize); +*/ + /* Check expected reqId */ + if(reqId != cesaExpReqId) + { + cesaReqIdError++; +/* + mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", + cesaCbIter, cesaIteration, reqId, cesaExpReqId); +*/ + } + else + { + if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || + (cesaCheckMode == CESA_FAST_CHECK_MODE) ) + { + if(cesaResult.retCode != MV_OK) + { + cesaError++; + + mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", + cesaCbIter, cesaIteration, reqId, cesaResult.retCode); + } + else + { + if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) + { + /* Check expected output */ + + isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); + if(isFailed) + { + mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", + cesaCbIter, cesaIteration, reqId); + + CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", + reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); + + CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); + + CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); + + cesaCryptoError++; + } + } + } + } + } + if(cesaCheckMode == CESA_SHOW_CHECK_MODE) + { + extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); + mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); + } + + cesaCbIter++; + if(cesaCbIter >= cesaIteration) + { + cesaCbIter = 0; + cesaExpReqId = 0; + cesaIsReady = MV_TRUE; + + cesaEndTicks = CESA_TEST_TICK_GET(); + cesaRate = getRate(&cesaRateAfterDot); + } + else + { + cesaExpReqId = reqId + 1; + if(cesaExpReqId == CESA_DEF_REQ_SIZE) + cesaExpReqId = 0; + } +} + + +#ifdef MV_NETBSD +static int cesaTestReadyIsr(void *arg) +#else +#ifdef __KERNEL__ +static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) +#endif +#ifdef MV_VXWORKS +void cesaTestReadyIsr(void) +#endif +#endif +{ + MV_U32 cause; + MV_STATUS status; + MV_CESA_RESULT result; + + cesaTestIsrCount++; + /* Clear cause register */ + cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); + if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) + { + mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); +#ifdef MV_NETBSD + return 0; +#else +#ifdef __KERNEL__ + return 1; +#else + return; +#endif +#endif + } + + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); + + while(MV_TRUE) + { + /* Get Ready requests */ + status = mvCesaReadyGet(&result); + if(status == MV_OK) + cesaCheckReady(&result); + + break; + } + if( (cesaTestFull == 1) && (status != MV_BUSY) ) + { + cesaTestFull = 0; + CESA_TEST_WAKE_UP(); + } + +#ifdef __KERNEL__ + return 1; +#endif +} + +void +cesaTestCheckReady(const MV_CESA_RESULT *r) +{ + MV_CESA_RESULT result = *r; + + cesaCheckReady(&result); + + if (cesaTestFull == 1) { + cesaTestFull = 0; + CESA_TEST_WAKE_UP(); + } +} + +static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) +{ + MV_U16 sid; + MV_STATUS status; + + status = mvCesaSessionOpen(pOs, (short*)&sid); + if(status != MV_OK) + { + mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", + status); + return -1; + } + + return (int)sid; +} + +void close_session(int sid) +{ + MV_STATUS status; + + status = mvCesaSessionClose(sid); + if(status != MV_OK) + { + mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", + sid, status); + } +} + +MV_STATUS testOpen(int idx) +{ + MV_CESA_OPEN_SESSION os; + int sid, i, testIdx; + MV_CESA_TEST_SESSION* pTestSession; + MV_U16 digestSize = 0; + + pTestSession = getTestSessionDb(idx, &testIdx); + if(pTestSession == NULL) + { + mvOsPrintf("Test %d is not exist\n", idx); + return MV_BAD_PARAM; + } + pTestSession = &pTestSession[testIdx]; + + if(pTestSession->sid != -1) + { + mvOsPrintf("Session for test %d already created: sid=%d\n", + idx, pTestSession->sid); + return MV_OK; + } + + os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; + os.macMode = pTestSession->macAlgorithm; + switch(os.macMode) + { + case MV_CESA_MAC_MD5: + case MV_CESA_MAC_HMAC_MD5: + digestSize = MV_CESA_MD5_DIGEST_SIZE; + break; + + case MV_CESA_MAC_SHA1: + case MV_CESA_MAC_HMAC_SHA1: + digestSize = MV_CESA_SHA1_DIGEST_SIZE; + break; + + case MV_CESA_MAC_NULL: + digestSize = 0; + } + os.cryptoMode = pTestSession->cryptoMode; + os.direction = pTestSession->direction; + os.operation = pTestSession->operation; + + for(i=0; icryptoKeySize; i++) + os.cryptoKey[i] = pTestSession->pCryptoKey[i]; + + os.cryptoKeyLength = pTestSession->cryptoKeySize; + + for(i=0; imacKeySize; i++) + os.macKey[i] = pTestSession->pMacKey[i]; + + os.macKeyLength = pTestSession->macKeySize; + os.digestSize = digestSize; + + sid = open_session(&os); + if(sid == -1) + { + mvOsPrintf("Can't open session for test %d: rc=0x%x\n", + idx, cesaResult.retCode); + return cesaResult.retCode; + } + CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); + pTestSession->sid = sid; + return MV_OK; +} + +MV_STATUS testClose(int idx) +{ + int testIdx; + MV_CESA_TEST_SESSION* pTestSession; + + pTestSession = getTestSessionDb(idx, &testIdx); + if(pTestSession == NULL) + { + mvOsPrintf("Test %d is not exist\n", idx); + return MV_BAD_PARAM; + } + pTestSession = &pTestSession[testIdx]; + + if(pTestSession->sid == -1) + { + mvOsPrintf("Test session %d is not opened\n", idx); + return MV_NO_SUCH; + } + + close_session(pTestSession->sid); + pTestSession->sid = -1; + + return MV_OK; +} + +MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, + MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) +{ + int cmdReqId = 0; + int i; + MV_STATUS rc = MV_OK; + char ivZeroHex[] = "0000"; + + if(iter == 0) + iter = CESA_DEF_ITER_NUM; + + if(pCmd == NULL) + { + mvOsPrintf("testCmd failed: pCmd=NULL\n"); + return MV_BAD_PARAM; + } + pCmd->sessionId = sid; + + cesaCryptoError = 0; + cesaReqIdError = 0; + cesaError = 0; + cesaTestIsrMissCount = 0; + cesaIsReady = MV_FALSE; + cesaIteration = iter; + + if(cesaInputHexStr == NULL) + cesaInputHexStr = cesaPlainHexEbc; + + for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); + if(pIV != NULL) + { + /* If IV from SA - set IV in Source buffer to zeros */ + cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); + cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, + (cesaReqSize - pCmd->cryptoOffset)); + } + else + { + cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); + } + pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); + cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); + + memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); + } + + if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) + { + MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; + + if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) + { + mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); + mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", + cesaReqSize, pCmd->macLength); + mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); + return MV_OK; + } + if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) + { + mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); + mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", + cesaReqSize, pCmd->macLength); + mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); + return MV_OK; + } + } + + cesaBeginTicks = CESA_TEST_TICK_GET(); + CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); + cesaTestTraceIdx = 0; + ); + + if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) + { + volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; + + for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) + { + mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); + } + if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) + { + mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); + } + } + cesaEndTicks = CESA_TEST_TICK_GET(); + cesaRate = getRate(&cesaRateAfterDot); + cesaIsReady = MV_TRUE; + + return MV_OK; + } + + /*cesaTestIsrCount = 0;*/ + /*mvCesaDebugStatsClear();*/ + +#ifndef MV_NETBSD + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); +#endif + + for(i=0; ipReqPrv = (void*)cmdReqId; + + CESA_TEST_LOCK(flags); + + rc = mvCesaAction(pCmd); + if(rc == MV_NO_RESOURCE) + cesaTestFull = 1; + + CESA_TEST_UNLOCK(flags); + + if(rc == MV_NO_RESOURCE) + { + CESA_TEST_LOCK(flags); + CESA_TEST_WAIT( (cesaTestFull == 0), 100); + CESA_TEST_UNLOCK(flags); + if(cesaTestFull == 1) + { + mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", + i, iter, cesaTestFull); + cesaTestFull = 0; + return MV_TIMEOUT; + } + + CESA_TEST_LOCK(flags); + + rc = mvCesaAction(pCmd); + + CESA_TEST_UNLOCK(flags); + } + if( (rc != MV_OK) && (rc != MV_NO_MORE) ) + { + mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); + return rc; + } + + cmdReqId++; + if(cmdReqId >= CESA_DEF_REQ_SIZE) + cmdReqId = 0; + +#ifdef MV_LINUX + /* Reschedule each 16 requests */ + if( (i & 0xF) == 0) + schedule(); +#endif + } + return MV_OK; +} + +void cesaTestStart(int bufNum, int bufSize) +{ + int i, j, idx; + MV_CESA_MBUF *pMbufSrc, *pMbufDst; + MV_BUF_INFO *pFragsSrc, *pFragsDst; + char *pBuf; +#ifndef MV_NETBSD + int numOfSessions, queueDepth; + char *pSram; + MV_STATUS status; + MV_CPU_DEC_WIN addrDecWin; +#endif + + cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); + if(cesaCmdRing == NULL) + { + mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", + sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); + return; + } + memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); + + if(bufNum == 0) + bufNum = CESA_DEF_BUF_NUM; + + if(bufSize == 0) + bufSize = CESA_DEF_BUF_SIZE; + + cesaBufNum = bufNum; + cesaBufSize = bufSize; + mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", + bufNum, bufSize); + + cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); + if(cesaHexBuffer == NULL) + { + mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", + 2*bufNum*bufSize); + return; + } + memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); + + cesaBinBuffer = mvOsMalloc(bufNum*bufSize); + if(cesaBinBuffer == NULL) + { + mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", + bufNum*bufSize); + return; + } + memset(cesaBinBuffer, 0, (bufNum*bufSize)); + + cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); + if(cesaExpBinBuffer == NULL) + { + mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", + bufNum*bufSize); + return; + } + memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); + + CESA_TEST_WAIT_INIT(); + + pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || + (pMbufDst == NULL) || (pFragsDst == NULL) ) + { + mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); + /* !!!! Dima cesaTestCleanup();*/ + return; + } + + memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", + pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); + + idx = 0; + for(i=0; ipFrags = &pFragsSrc[idx]; + cesaCmdRing[i].pSrc->numFrags = bufNum; + cesaCmdRing[i].pSrc->mbufSize = 0; + + cesaCmdRing[i].pDst = &pMbufDst[i]; + cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; + cesaCmdRing[i].pDst->numFrags = bufNum; + cesaCmdRing[i].pDst->mbufSize = 0; + + for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; + cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; + pBuf += bufSize; + cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; + cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; + pBuf += bufSize; + } + idx += bufNum; + } + +#ifndef MV_NETBSD + if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) + pSram = (char*)addrDecWin.addrWin.baseLow; + else + { + mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); + return; + } + +#ifdef MV_CESA_NO_SRAM + pSram = mvOsMalloc(4*1024+8); + if(pSram == NULL) + { + mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", + 4*1024+8); + /* !!!! Dima cesaTestCleanup();*/ + return; + } + pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); +#endif /* MV_CESA_NO_SRAM */ + + numOfSessions = CESA_DEF_SESSION_NUM; + queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; + + status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); + if(status != MV_OK) + { + mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); + /* !!!! Dima cesaTestCleanup();*/ + return; + } +#endif /* !MV_NETBSD */ + + /* Prepare data for tests */ + for(i=0; i<50; i++) + strcat((char*)cesaDataHexStr3, "dd"); + + strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); + strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); + + /* Digest must be 8 byte aligned */ + for(; i<56; i++) + { + strcat((char*)cesaDataAndMd5digest3, "00"); + strcat((char*)cesaDataAndSha1digest3, "00"); + } + strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); + strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); + +#ifndef MV_NETBSD + MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); + MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); +#endif + +#ifdef MV_VXWORKS + { + MV_STATUS status; + + status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); + if (status != OK) + { + mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", + INT_LVL_CESA, status); + /* !!!! Dima cesaTestCleanup();*/ + return; + } + cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); + if(cesaSemId == NULL) + { + mvOsPrintf("cesaTestStart: Can't create semaphore\n"); + return; + } + intEnable(INT_LVL_CESA); + } +#endif /* MV_VXWORKS */ + +#if !defined(MV_NETBSD) && defined(__KERNEL__) + if( request_irq(CESA_IRQ, cesaTestReadyIsr, (IRQF_DISABLED) , "cesa_test", NULL ) ) + { + mvOsPrintf( "cannot assign irq\n" ); + /* !!!! Dima cesaTestCleanup();*/ + return; + } + spin_lock_init( &cesaLock ); +#endif +} + +MV_STATUS testRun(int idx, int caseIdx, int iter, + int reqSize, int checkMode) +{ + int testIdx, count, sid, digestSize; + int blockSize; + MV_CESA_TEST_SESSION* pTestSession; + MV_CESA_COMMAND cmd; + MV_STATUS status; + + memset(&cmd, 0, sizeof(cmd)); + + pTestSession = getTestSessionDb(idx, &testIdx); + if(pTestSession == NULL) + { + mvOsPrintf("Test %d is not exist\n", idx); + return MV_BAD_PARAM; + } + pTestSession = &pTestSession[testIdx]; + + sid = pTestSession->sid; + if(sid == -1) + { + mvOsPrintf("Test %d is not opened\n", idx); + return MV_BAD_STATE; + } + switch(pTestSession->cryptoAlgorithm) + { + case MV_CESA_CRYPTO_DES: + case MV_CESA_CRYPTO_3DES: + blockSize = MV_CESA_DES_BLOCK_SIZE; + break; + + case MV_CESA_CRYPTO_AES: + blockSize = MV_CESA_AES_BLOCK_SIZE; + break; + + case MV_CESA_CRYPTO_NULL: + blockSize = 0; + break; + + default: + mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", + pTestSession->cryptoAlgorithm); + return MV_BAD_PARAM; + } + switch(pTestSession->macAlgorithm) + { + case MV_CESA_MAC_MD5: + case MV_CESA_MAC_HMAC_MD5: + digestSize = MV_CESA_MD5_DIGEST_SIZE; + break; + + case MV_CESA_MAC_SHA1: + case MV_CESA_MAC_HMAC_SHA1: + digestSize = MV_CESA_SHA1_DIGEST_SIZE; + break; + default: + digestSize = 0; + } + + if(iter == 0) + iter = CESA_DEF_ITER_NUM; + + if(pTestSession->direction == MV_CESA_DIR_ENCODE) + { + cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; + cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; + } + else + { + cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; + cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; + } + + cmd.sessionId = sid; + if(checkMode == CESA_FAST_CHECK_MODE) + { + cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; + cmd.macLength = cesaTestCases[caseIdx].macLength; + } + else + { + cmd.cryptoLength = reqSize; + cmd.macLength = reqSize; + } + cesaRateSize = cmd.cryptoLength; + cesaReqSize = cmd.cryptoLength; + cmd.cryptoOffset = 0; + if(pTestSession->operation != MV_CESA_MAC_ONLY) + { + if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || + (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) + { + cmd.ivOffset = 0; + cmd.cryptoOffset = blockSize; + if(cesaTestCases[caseIdx].pCryptoIV == NULL) + { + cmd.ivFromUser = 1; + } + else + { + cmd.ivFromUser = 0; + mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); + } + cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; + } + } + +/* + mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", + cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); +*/ + if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) + { + cmd.macOffset = cmd.cryptoOffset; + + if(cesaTestCases[caseIdx].digestOffset == -1) + { + cmd.digestOffset = cmd.macOffset + cmd.macLength; + cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); + } + else + { + cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; + } + if( (cmd.digestOffset + digestSize) > cesaReqSize) + cesaReqSize = cmd.digestOffset + digestSize; + } + + cesaCheckMode = checkMode; + + if(checkMode == CESA_NULL_CHECK_MODE) + { + cesaCheckSize = 0; + cesaCheckOffset = 0; + } + else + { + if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) + { + cesaCheckOffset = 0; + cesaCheckSize = cmd.cryptoLength; + } + else + { + cesaCheckSize = digestSize; + cesaCheckOffset = cmd.digestOffset; + } + } +/* + mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", + cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); + + mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", + blockSize, cmd.ivOffset, cmd.ivFromUser, + cmd.cryptoOffset, cmd.cryptoLength); + + mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", + cmd.macOffset, cmd.digestOffset, cmd.macLength); +*/ + status = testCmd(sid, iter, &cmd, pTestSession, + cesaTestCases[caseIdx].pCryptoIV, blockSize); + + if(status != MV_OK) + return status; + + /* Wait when all callbacks is received */ + count = 0; + while(cesaIsReady == MV_FALSE) + { + mvOsSleep(10); + count++; + if(count > 100) + { + mvOsPrintf("testRun: Timeout occured\n"); + return MV_TIMEOUT; + } + } + + return MV_OK; +} + + +void cesaTestStop(void) +{ + MV_CESA_MBUF *pMbufSrc, *pMbufDst; + MV_BUF_INFO *pFragsSrc, *pFragsDst; + int i; + + /* Release all allocated memories */ + pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); + pFragsSrc = cesaCmdRing[0].pSrc->pFrags; + + pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); + pFragsDst = cesaCmdRing[0].pDst->pFrags; + + mvOsFree(pMbufSrc); + mvOsFree(pMbufDst); + mvOsFree(pFragsSrc); + mvOsFree(pFragsDst); + + for(i=0; i 0) + cryptoError++; + if(cesaReqIdError > 0) + reqIdError++; + + testClose(idx); + } + } + if(cryptoError > 0) + mvOsPrintf("cryptoError : %d\n", cryptoError); + if(reqIdError > 0) + mvOsPrintf("reqIdError : %d\n", reqIdError); + + if(openErrors > 0) + { + mvOsPrintf("Open Errors = %d\n", openErrors); + for(i=0; i<100; i++) + { + if(openErrDisp[i] != 0) + mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); + } + } +} + + +void loopback_test(int idx, int iter, int size, char* pPlainData) +{ +} + + +#if defined(MV_VXWORKS) +int testMode = 0; +unsigned __TASKCONV cesaTask(void* args) +{ + int reqSize = cesaReqSize; + + if(testMode == 0) + { + cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, + reqSize, cesaCheckMode); + } + else + { + if(testMode == 1) + { + cesaTest(cesaIteration, reqSize, cesaCheckMode); + combiTest(cesaIteration, reqSize, cesaCheckMode); + } + else + { + multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); + } + } + return 0; +} + +void oneTest(int testIdx, int caseIdx, + int iter, int reqSize, int checkMode) +{ + long rc; + + cesaIteration = iter; + cesaReqSize = cesaRateSize = reqSize; + cesaCheckMode = checkMode; + testMode = 0; + cesaTestIdx = testIdx; + cesaCaseIdx = caseIdx; + rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); + if (rc != MV_OK) + { + mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); + } +} + +void multiTest(int iter, int reqSize, int checkMode) +{ + long rc; + + cesaIteration = iter; + cesaCheckMode = checkMode; + cesaReqSize = reqSize; + testMode = 1; + rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); + if (rc != MV_OK) + { + mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); + } +} + +void sizeTest(int testIdx, int iter, int checkMode) +{ + long rc; + + cesaIteration = iter; + cesaCheckMode = checkMode; + testMode = 2; + cesaIdx = testIdx; + rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); + if (rc != MV_OK) + { + mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); + } +} + +#endif /* MV_VXWORKS */ + +extern void mvCesaDebugSA(short sid, int mode); +void cesaTestPrintSession(int idx) +{ + int testIdx; + MV_CESA_TEST_SESSION* pTestSession; + + pTestSession = getTestSessionDb(idx, &testIdx); + if(pTestSession == NULL) + { + mvOsPrintf("Test %d is not exist\n", idx); + return; + } + pTestSession = &pTestSession[testIdx]; + + if(pTestSession->sid == -1) + { + mvOsPrintf("Test session %d is not opened\n", idx); + return; + } + + mvCesaDebugSA(pTestSession->sid, 1); +} + +void cesaTestPrintStatus(void) +{ + mvOsPrintf("\n\t Cesa Test Status\n\n"); + + mvOsPrintf("isrCount=%d\n", + cesaTestIsrCount); + +#ifdef CESA_TEST_DEBUG + { + int i, j; + j = cesaTestTraceIdx; + mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); + for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); + if(pLruCache->table == NULL) + { + mvOsFree(pLruCache); + return NULL; + } + memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); + pLruCache->tableSize = numOfEntries; + + for(i=0; itable[i].next = i+1; + pLruCache->table[i].prev = i-1; + } + pLruCache->least = 0; + pLruCache->most = numOfEntries-1; + + return pLruCache; +} + +void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) +{ + mvOsFree(pLruCache->table); + mvOsFree(pLruCache); +} + +/* Update LRU cache database after using cache Index */ +void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) +{ + int prev, next; + + if(cacheIdx == pLruHndl->most) + return; + + next = pLruHndl->table[cacheIdx].next; + if(cacheIdx == pLruHndl->least) + { + pLruHndl->least = next; + } + else + { + prev = pLruHndl->table[cacheIdx].prev; + + pLruHndl->table[next].prev = prev; + pLruHndl->table[prev].next = next; + } + + pLruHndl->table[pLruHndl->most].next = cacheIdx; + pLruHndl->table[cacheIdx].prev = pLruHndl->most; + pLruHndl->most = cacheIdx; +} + +/* Delete LRU cache entry */ +void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) +{ + int prev, next; + + if(cacheIdx == pLruHndl->least) + return; + + prev = pLruHndl->table[cacheIdx].prev; + if(cacheIdx == pLruHndl->most) + { + pLruHndl->most = prev; + } + else + { + next = pLruHndl->table[cacheIdx].next; + + pLruHndl->table[next].prev = prev; + pLruHndl->table[prev].next = next; + } + pLruHndl->table[pLruHndl->least].prev = cacheIdx; + pLruHndl->table[cacheIdx].next = pLruHndl->least; + pLruHndl->least = cacheIdx; +} diff --git a/board/mv_feroceon/mv_hal/cesa/mvLru.h b/board/mv_feroceon/mv_hal/cesa/mvLru.h new file mode 100644 index 0000000..896e7f8 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/mvLru.h @@ -0,0 +1,112 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/******************************************************************************* +* mvLru.h - Header File for Least Recently Used Cache algorithm +* +* DESCRIPTION: +* This header file contains macros typedefs and function declaration for +* the Least Recently Used Cache algorithm. +* +*******************************************************************************/ + +#ifndef __mvLru_h__ +#define __mvLru_h__ + + +typedef struct +{ + int next; + int prev; +} MV_LRU_ENTRY; + +typedef struct +{ + int least; + int most; + MV_LRU_ENTRY* table; + int tableSize; + +}MV_LRU_CACHE; + + +/* Find Cache index for replacement LRU */ +static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) +{ + return pLruHndl->least; +} + +/* Init LRU cache module */ +MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); + +/* Finish LRU cache module */ +void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); + +/* Update LRU cache database after using cache Index */ +void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); + +/* Delete LRU cache entry */ +void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); + + +#endif /* __mvLru_h__ */ diff --git a/board/mv_feroceon/mv_hal/cesa/mvMD5.c b/board/mv_feroceon/mv_hal/cesa/mvMD5.c new file mode 100644 index 0000000..189f629 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/mvMD5.c @@ -0,0 +1,349 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "mvMD5.h" + +static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); + +#ifdef MV_CPU_LE +#define mvByteReverse(buf, len) /* Nothing */ +#else +static void mvByteReverse(unsigned char *buf, unsigned longs); + +/* + * Note: this code is harmless on little-endian machines. + */ +static void mvByteReverse(unsigned char *buf, unsigned longs) +{ + MV_U32 t; + + do + { + t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | + ((unsigned) buf[1] << 8 | buf[0]); + *(MV_U32 *) buf = t; + buf += 4; + } while (--longs); +} +#endif + +/* + * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious + * initialization constants. + */ +void mvMD5Init(MV_MD5_CONTEXT *ctx) +{ + ctx->buf[0] = 0x67452301; + ctx->buf[1] = 0xefcdab89; + ctx->buf[2] = 0x98badcfe; + ctx->buf[3] = 0x10325476; + + ctx->bits[0] = 0; + ctx->bits[1] = 0; +} + +/* + * Update context to reflect the concatenation of another buffer full + * of bytes. + */ +void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) +{ + MV_U32 t; + + /* Update bitcount */ + + t = ctx->bits[0]; + if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) + ctx->bits[1]++; /* Carry from low to high */ + ctx->bits[1] += len >> 29; + + t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ + + /* Handle any leading odd-sized chunks */ + + if (t) + { + unsigned char *p = (unsigned char *) ctx->in + t; + + t = 64 - t; + if (len < t) + { + memcpy(p, buf, len); + return; + } + memcpy(p, buf, t); + mvByteReverse(ctx->in, MV_MD5_MAC_LEN); + mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); + buf += t; + len -= t; + } + /* Process data in 64-byte chunks */ + + while (len >= 64) + { + memcpy(ctx->in, buf, 64); + mvByteReverse(ctx->in, MV_MD5_MAC_LEN); + mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); + buf += 64; + len -= 64; + } + + /* Handle any remaining bytes of data. */ + + memcpy(ctx->in, buf, len); +} + +/* + * Final wrapup - pad to 64-byte boundary with the bit pattern + * 1 0* (64-bit count of bits processed, MSB-first) + */ +void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) +{ + unsigned count; + unsigned char *p; + + /* Compute number of bytes mod 64 */ + count = (ctx->bits[0] >> 3) & 0x3F; + + /* Set the first char of padding to 0x80. This is safe since there is + always at least one byte free */ + p = ctx->in + count; + *p++ = 0x80; + + /* Bytes of padding needed to make 64 bytes */ + count = 64 - 1 - count; + + /* Pad out to 56 mod 64 */ + if (count < 8) + { + /* Two lots of padding: Pad the first block to 64 bytes */ + memset(p, 0, count); + mvByteReverse(ctx->in, MV_MD5_MAC_LEN); + mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); + + /* Now fill the next block with 56 bytes */ + memset(ctx->in, 0, 56); + } + else + { + /* Pad block to 56 bytes */ + memset(p, 0, count - 8); + } + mvByteReverse(ctx->in, 14); + + /* Append length in bits and transform */ + ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; + ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; + + mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); + mvByteReverse((unsigned char *) ctx->buf, 4); + memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); + memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ +} + +/* The four core functions - F1 is optimized somewhat */ + +/* #define F1(x, y, z) (x & y | ~x & z) */ +#define F1(x, y, z) (z ^ (x & (y ^ z))) +#define F2(x, y, z) F1(z, x, y) +#define F3(x, y, z) (x ^ y ^ z) +#define F4(x, y, z) (y ^ (x | ~z)) + +/* This is the central step in the MD5 algorithm. */ +#define MD5STEP(f, w, x, y, z, data, s) \ + ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) + +/* + * The core of the MD5 algorithm, this alters an existing MD5 hash to + * reflect the addition of 16 longwords of new data. MD5Update blocks + * the data and converts bytes into longwords for this routine. + */ +static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) +{ + register MV_U32 a, b, c, d; + + a = buf[0]; + b = buf[1]; + c = buf[2]; + d = buf[3]; + + MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); + MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); + MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); + MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); + MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); + MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); + MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); + MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); + MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); + MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); + MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); + MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); + MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); + MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); + MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); + MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); + + MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); + MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); + MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); + MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); + MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); + MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); + MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); + MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); + MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); + MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); + MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); + MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); + MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); + MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); + MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); + MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); + + MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); + MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); + MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); + MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); + MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); + MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); + MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); + MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); + MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); + MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); + MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); + MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); + MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); + MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); + MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); + MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); + + MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); + MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); + MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); + MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); + MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); + MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); + MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); + MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); + MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); + MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); + MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); + MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); + MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); + MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); + MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); + MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); + + buf[0] += a; + buf[1] += b; + buf[2] += c; + buf[3] += d; +} + +void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) +{ + MV_MD5_CONTEXT ctx; + + mvMD5Init(&ctx); + mvMD5Update(&ctx, buf, len); + mvMD5Final(digest, &ctx); +} + + +void mvHmacMd5(unsigned char const* text, int text_len, + unsigned char const* key, int key_len, + unsigned char* digest) +{ + int i; + MV_MD5_CONTEXT ctx; + unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ + unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ + + /* start out by storing key in pads */ + memset(k_ipad, 0, 64); + memcpy(k_ipad, key, key_len); + memset(k_opad, 0, 64); + memcpy(k_opad, key, key_len); + + /* XOR key with ipad and opad values */ + for (i=0; i<64; i++) + { + k_ipad[i] ^= 0x36; + k_opad[i] ^= 0x5c; + } + + /* perform inner MD5 */ + mvMD5Init(&ctx); /* init ctx for 1st pass */ + mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ + mvMD5Update(&ctx, text, text_len); /* then text of datagram */ + mvMD5Final(digest, &ctx); /* finish up 1st pass */ + + /* perform outer MD5 */ + mvMD5Init(&ctx); /* init ctx for 2nd pass */ + mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ + mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ + mvMD5Final(digest, &ctx); /* finish up 2nd pass */ +} diff --git a/board/mv_feroceon/mv_hal/cesa/mvMD5.h b/board/mv_feroceon/mv_hal/cesa/mvMD5.h new file mode 100644 index 0000000..d05c6b6 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/mvMD5.h @@ -0,0 +1,93 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvMD5_h__ +#define __mvMD5_h__ + +#include "mvMD5.h" + +#define MV_MD5_MAC_LEN 16 + + +typedef struct +{ + MV_U32 buf[4]; + MV_U32 bits[2]; + MV_U8 in[64]; + +} MV_MD5_CONTEXT; + +void mvMD5Init(MV_MD5_CONTEXT *context); +void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, + unsigned len); +void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); + +void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); + +void mvHmacMd5(unsigned char const* text, int text_len, + unsigned char const* key, int key_len, + unsigned char* digest); + + +#endif /* __mvMD5_h__ */ diff --git a/board/mv_feroceon/mv_hal/cesa/mvSHA1.c b/board/mv_feroceon/mv_hal/cesa/mvSHA1.c new file mode 100644 index 0000000..0e0786b --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/mvSHA1.c @@ -0,0 +1,239 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "mvSHA1.h" + +#define SHA1HANDSOFF + +typedef union +{ + MV_U8 c[64]; + MV_U32 l[16]; + +} CHAR64LONG16; + +static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); + +#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) + + +#ifdef MV_CPU_LE +#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ + (rol(block->l[i], 8) & 0x00FF00FF)) +#else +#define blk0(i) block->l[i] +#endif +#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ + block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) + +/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ +#define R0(v,w,x,y,z,i) \ + z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ + w = rol(w, 30); +#define R1(v,w,x,y,z,i) \ + z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ + w = rol(w, 30); +#define R2(v,w,x,y,z,i) \ + z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); +#define R3(v,w,x,y,z,i) \ + z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ + w = rol(w, 30); +#define R4(v,w,x,y,z,i) \ + z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ + w=rol(w, 30); + +/* Hash a single 512-bit block. This is the core of the algorithm. */ +static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) +{ + MV_U32 a, b, c, d, e; + CHAR64LONG16* block; + +#ifdef SHA1HANDSOFF + static MV_U32 workspace[16]; + + block = (CHAR64LONG16 *) workspace; + memcpy(block, buffer, 64); +#else + block = (CHAR64LONG16 *) buffer; +#endif + /* Copy context->state[] to working vars */ + a = state[0]; + b = state[1]; + c = state[2]; + d = state[3]; + e = state[4]; + /* 4 rounds of 20 operations each. Loop unrolled. */ + R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); + R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); + R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); + R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); + R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); + R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); + R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); + R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); + R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); + R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); + R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); + R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); + R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); + R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); + R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); + R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); + R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); + R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); + R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); + R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); + /* Add the working vars back into context.state[] */ + state[0] += a; + state[1] += b; + state[2] += c; + state[3] += d; + state[4] += e; + /* Wipe variables */ + a = b = c = d = e = 0; +} + +void mvSHA1Init(MV_SHA1_CTX* context) +{ + /* SHA1 initialization constants */ + context->state[0] = 0x67452301; + context->state[1] = 0xEFCDAB89; + context->state[2] = 0x98BADCFE; + context->state[3] = 0x10325476; + context->state[4] = 0xC3D2E1F0; + context->count[0] = context->count[1] = 0; +} + + +/* Run your data through this. */ +void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, + unsigned int len) +{ + MV_U32 i, j; + + j = (context->count[0] >> 3) & 63; + if ((context->count[0] += len << 3) < (len << 3)) + context->count[1]++; + context->count[1] += (len >> 29); + if ((j + len) > 63) + { + memcpy(&context->buffer[j], data, (i = 64-j)); + mvSHA1Transform(context->state, context->buffer); + for ( ; i + 63 < len; i += 64) + { + mvSHA1Transform(context->state, &data[i]); + } + j = 0; + } + else + { + i = 0; + } + memcpy(&context->buffer[j], &data[i], len - i); +} + +void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) +{ + MV_U32 i; + MV_U8 finalcount[8]; + + for (i = 0; i < 8; i++) + { + finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> + ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ + } + mvSHA1Update(context, (const unsigned char *) "\200", 1); + while ((context->count[0] & 504) != 448) + { + mvSHA1Update(context, (const unsigned char *) "\0", 1); + } + mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() + */ + for (i = 0; i < 20; i++) + { + digest[i] = (unsigned char) + ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); + } + /* Wipe variables */ + i = 0; + memset(context->buffer, 0, 64); + memset(context->state, 0, 20); + memset(context->count, 0, 8); + memset(finalcount, 0, 8); + +#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ + mvSHA1Transform(context->state, context->buffer); +#endif +} + + +void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) +{ + MV_SHA1_CTX ctx; + + mvSHA1Init(&ctx); + mvSHA1Update(&ctx, buf, len); + mvSHA1Final(digest, &ctx); +} diff --git a/board/mv_feroceon/mv_hal/cesa/mvSHA1.h b/board/mv_feroceon/mv_hal/cesa/mvSHA1.h new file mode 100644 index 0000000..17df9fc --- /dev/null +++ b/board/mv_feroceon/mv_hal/cesa/mvSHA1.h @@ -0,0 +1,88 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvSHA1_h__ +#define __mvSHA1_h__ + +#include "mvSHA1.h" + +#define MV_SHA1_MAC_LEN 20 + + +typedef struct +{ + MV_U32 state[5]; + MV_U32 count[2]; + MV_U8 buffer[64]; + +} MV_SHA1_CTX; + +void mvSHA1Init(MV_SHA1_CTX *context); +void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); +void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); + +void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); + + +#endif /* __mvSHA1_h__ */ diff --git a/board/mv_feroceon/mv_hal/cntmr/mvCntmr.c b/board/mv_feroceon/mv_hal/cntmr/mvCntmr.c new file mode 100644 index 0000000..717c150 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cntmr/mvCntmr.c @@ -0,0 +1,376 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCntmr.h" +#include "cpu/mvCpu.h" + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +extern unsigned int whoAmI(void); + +/******************************************************************************* +* mvCntmrLoad - +* +* DESCRIPTION: +* Load an init Value to a given counter/timer +* +* INPUT: +* countNum - counter number +* value - value to be loaded +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) +{ + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); + return MV_BAD_PARAM;; + + } + + MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); + MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrRead - +* +* DESCRIPTION: +* Returns the value of the given Counter/Timer +* +* INPUT: +* countNum - counter number +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 counter value +*******************************************************************************/ +MV_U32 mvCntmrRead(MV_U32 countNum) +{ + return MV_REG_READ(CNTMR_VAL_REG(countNum)); +} + +/******************************************************************************* +* mvCntmrWrite - +* +* DESCRIPTION: +* Returns the value of the given Counter/Timer +* +* INPUT: +* countNum - counter number +* countVal - value to write +* +* OUTPUT: +* None. +* +* RETURN: +* None +*******************************************************************************/ +void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) +{ + MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); +} + +/******************************************************************************* +* mvCntmrCtrlSet - +* +* DESCRIPTION: +* Set the Control to a given counter/timer +* +* INPUT: +* countNum - counter number +* pCtrl - pointer to MV_CNTMR_CTRL structure +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); + return MV_BAD_PARAM;; + + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); + + + if (pCtrl->enable) /* enable counter\timer */ + { + cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); + } + else /* disable counter\timer */ + { + cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); + } + + if ( pCtrl->autoEnable ) /* Auto mode */ + { + cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); + + } + else /* no auto mode */ + { + cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); + } + + MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); + + return MV_OK; + +} + +/******************************************************************************* +* mvCntmrCtrlGet - +* +* DESCRIPTION: +* Get the Control value of a given counter/timer +* +* INPUT: +* countNum - counter number +* pCtrl - pointer to MV_CNTMR_CTRL structure +* +* OUTPUT: +* Counter\Timer control value +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); + return MV_BAD_PARAM;; + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); + + /* enable counter\timer */ + if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) + { + pCtrl->enable = MV_TRUE; + } + else + { + pCtrl->enable = MV_FALSE; + } + + /* counter mode */ + if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) + { + pCtrl->autoEnable = MV_TRUE; + } + else + { + pCtrl->autoEnable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrEnable - +* +* DESCRIPTION: +* Set the Enable-Bit to logic '1' ==> starting the counter +* +* INPUT: +* countNum - counter number +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrEnable(MV_U32 countNum) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); + return MV_BAD_PARAM;; + + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); + + /* enable counter\timer */ + cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); + + + MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrDisable - +* +* DESCRIPTION: +* Stop the counter/timer running, and returns its Value +* +* INPUT: +* countNum - counter number +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 counter\timer value +*******************************************************************************/ +MV_STATUS mvCntmrDisable(MV_U32 countNum) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); + return MV_BAD_PARAM;; + + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); + + /* disable counter\timer */ + cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); + + MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrStart - +* +* DESCRIPTION: +* Combined all the sub-operations above to one function: Load,setMode,Enable +* +* INPUT: +* countNum - counter number +* value - value of the counter\timer to be set +* pCtrl - pointer to MV_CNTMR_CTRL structure +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, + MV_CNTMR_CTRL *pCtrl) +{ + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); + return MV_BAD_PARAM;; + + } + + /* load value onto counter\timer */ + mvCntmrLoad(countNum,value); + + /* set the counter to load in the first time */ + mvCntmrWrite(countNum,value); + + /* set control for timer \ cunter and enable */ + mvCntmrCtrlSet(countNum,pCtrl); + + return MV_OK; +} + diff --git a/board/mv_feroceon/mv_hal/cntmr/mvCntmr.h b/board/mv_feroceon/mv_hal/cntmr/mvCntmr.h new file mode 100644 index 0000000..b911d0f --- /dev/null +++ b/board/mv_feroceon/mv_hal/cntmr/mvCntmr.h @@ -0,0 +1,121 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvTmrWtdgh +#define __INCmvTmrWtdgh + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "cntmr/mvCntmrRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + + +/* This enumerator describe counters\watchdog numbers */ +typedef enum _mvCntmrID +{ + TIMER0 = 0, + TIMER1, + WATCHDOG, + TIMER2, + TIMER3, +}MV_CNTMR_ID; + + +/* Counter / Timer control structure */ +typedef struct _mvCntmrCtrl +{ + MV_BOOL enable; /* enable */ + MV_BOOL autoEnable; /* counter/Timer */ +}MV_CNTMR_CTRL; + + +/* Functions */ + +/* Load an init Value to a given counter/timer */ +MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); + +/* Returns the value of the given Counter/Timer */ +MV_U32 mvCntmrRead(MV_U32 countNum); + +/* Write a value of the given Counter/Timer */ +void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); + +/* Set the Control to a given counter/timer */ +MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); + +/* Get the value of a given counter/timer */ +MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); + +/* Set the Enable-Bit to logic '1' ==> starting the counter. */ +MV_STATUS mvCntmrEnable(MV_U32 countNum); + +/* Stop the counter/timer running, and returns its Value. */ +MV_STATUS mvCntmrDisable(MV_U32 countNum); + +/* Combined all the sub-operations above to one function: Load,setMode,Enable */ +MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, + MV_CNTMR_CTRL *pCtrl); + +#endif /* __INCmvTmrWtdgh */ diff --git a/board/mv_feroceon/mv_hal/cntmr/mvCntmrRegs.h b/board/mv_feroceon/mv_hal/cntmr/mvCntmrRegs.h new file mode 100644 index 0000000..15a6c28 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cntmr/mvCntmrRegs.h @@ -0,0 +1,121 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvTmrwtdgRegsh +#define __INCmvTmrwtdgRegsh + +/*******************************************/ +/* ARM Timers Registers Map */ +/*******************************************/ + +#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ + (((tmrNum) < 3)?0:8)) +#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ + (((tmrNum) < 3)?0:8)) +#define CNTMR_CTRL_REG (CNTMR_BASE) + +/*For MV78XX0*/ +#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) +#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) + +/* ARM Timers Registers Map */ +/*******************************************/ + + +/* ARM Timers Control Register */ +/* CPU_TIMERS_CTRL_REG (CTCR) */ + +#define TIMER0_NUM 0 +#define TIMER1_NUM 1 +#define WATCHDOG_NUM 2 +#define TIMER2_NUM 3 +#define TIMER3_NUM 4 + +#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) +#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) +#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) +#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) + +#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) +#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) +#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) + + +/* ARM Timer\Watchdog Reload Register */ +/* CNTMR_RELOAD_REG (TRR) */ + +#define TRG_ARM_TIMER_REL_OFFS 0 +#define TRG_ARM_TIMER_REL_MASK 0xffffffff + +/* ARM Timer\Watchdog Register */ +/* CNTMR_VAL_REG (TVRG) */ + +#define TVR_ARM_TIMER_OFFS 0 +#define TVR_ARM_TIMER_MASK 0xffffffff +#define TVR_ARM_TIMER_MAX 0xffffffff + + + +#endif /* __INCmvTmrwtdgRegsh */ diff --git a/board/mv_feroceon/mv_hal/cntmr/mvCompVer.txt b/board/mv_feroceon/mv_hal/cntmr/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cntmr/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/cpu/mvCpuCntrs.c b/board/mv_feroceon/mv_hal/cpu/mvCpuCntrs.c new file mode 100644 index 0000000..609e674 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cpu/mvCpuCntrs.c @@ -0,0 +1,207 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "mvOs.h" +#include "mvCpuCntrs.h" + + +const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = +{ + /*0*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, + MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, + MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, + }, + /*1*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, + MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, + }, + /*2*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, + MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, + }, + /*3*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, + MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, + MV_CPU_CNTRS_INVALID, + } +}; + +MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; + +MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; + +void mvCpuCntrsReset(void) +{ + MV_U32 reg = 0; + + MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); +} + +void program_counter(int counter, int op) +{ + MV_U32 reg = (1 << op) | 0x1; /*enable*/ + + switch(counter) + { + case 0: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); + return; + + case 1: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); + return; + + case 2: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); + return; + + case 3: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); + return; + + default: + mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); + } + return; +} + +void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) +{ + int i; + + for(i=0; icounters_sum[i] = 0; + } + pEvent->num_of_measurements = 0; +} + + +MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) +{ + int i; + MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); + + if(event) + { + strncpy(event->name, name, sizeof(event->name)); + event->num_of_measurements = 0; + event->avg_sample_count = print_threshold; + for(i=0; icounters_before[i] = 0; + event->counters_after[i] = 0; + event->counters_sum[i] = 0; + } + } + return event; +} + +void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) +{ + if(event != NULL) + mvOsFree(event); +} + + +MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, + char* name, MV_U32 overhead) +{ + int i; + + /* Find required operations */ + for(i=0; inum_of_measurements < pEvent->avg_sample_count) + return; + + mvOsPrintf("%16s: ", pEvent->name); + for(i=0; icounters_sum[i], + pEvent->num_of_measurements, NULL); + if(counters_avg >= mvCpuCntrsTbl[i].overhead) + counters_avg -= mvCpuCntrsTbl[i].overhead; + else + counters_avg = 0; + + mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); + } + mvOsPrintf("\n"); + mvCpuCntrsEventClear(pEvent); + mvCpuCntrsReset(); +} + +void mvCpuCntrsStatus(void) +{ + int i; + + for(i=0; icounters_before[i] = mvCpuCntrsRead(i); +#else + pEvent->counters_before[1] = mvCpuCntrsRead(1); + pEvent->counters_before[3] = mvCpuCntrsRead(3); + pEvent->counters_before[0] = mvCpuCntrsRead(0); + pEvent->counters_before[2] = mvCpuCntrsRead(2); +#endif +} + +static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) +{ + int i; + +#if 0 + /* order is important - we want to measure the cycle count first here! */ + for(i=0; icounters_after[i] = mvCpuCntrsRead(i); +#else + pEvent->counters_after[2] = mvCpuCntrsRead(2); + pEvent->counters_after[0] = mvCpuCntrsRead(0); + pEvent->counters_after[3] = mvCpuCntrsRead(3); + pEvent->counters_after[1] = mvCpuCntrsRead(1); +#endif + + for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); + } + pEvent->num_of_measurements++; +} + + +#ifdef CONFIG_MV_CPU_PERF_CNTRS + +#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) + +#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) + +#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) + +#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) + +#else + +#define MV_CPU_CNTRS_READ(counter) +#define MV_CPU_CNTRS_START(event) +#define MV_CPU_CNTRS_STOP(event) +#define MV_CPU_CNTRS_SHOW(event) + +#endif /* CONFIG_MV_CPU_PERF_CNTRS */ + + +#endif /* __mvCpuCntrs_h__ */ + diff --git a/board/mv_feroceon/mv_hal/cpu/mvCpuL2Cntrs.c b/board/mv_feroceon/mv_hal/cpu/mvCpuL2Cntrs.c new file mode 100644 index 0000000..0333862 --- /dev/null +++ b/board/mv_feroceon/mv_hal/cpu/mvCpuL2Cntrs.c @@ -0,0 +1,143 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "mvOs.h" +#include "mvCpuL2Cntrs.h" + + + +MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; + +MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; + +void mvCpuL2CntrsReset(void) +{ + MV_U32 reg = 0; + + MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); + MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); + MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); + MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); +} + +static void mvCpuL2CntrConfig(int counter, int op) +{ + MV_U32 reg = (1 << op) | 0x1; /*enable*/ + + switch(counter) + { + case 0: + MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); + return; + + case 1: + MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); + return; + + default: + mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); + } + return; +} + +void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) +{ + int i; + + for(i=0; icounters_sum[i] = 0; + } + pEvent->num_of_measurements = 0; +} + + +MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) +{ + int i; + MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); + + if(event) + { + strncpy(event->name, name, sizeof(event->name)); + event->num_of_measurements = 0; + event->avg_sample_count = print_threshold; + for(i=0; icounters_before[i] = 0; + event->counters_after[i] = 0; + event->counters_sum[i] = 0; + } + } + return event; +} + +void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) +{ + if(event != NULL) + mvOsFree(event); +} + + +MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, + char* name, MV_U32 overhead) +{ + strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); + mvCpuL2CntrsTbl[counter].operation = op; + mvCpuL2CntrsTbl[counter].opIdx = op; + mvCpuL2CntrsTbl[counter].overhead = overhead; + mvCpuL2CntrConfig(counter, op); + mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", + counter, op, overhead); + return MV_OK; +} + +void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) +{ + int i; + MV_U64 counters_avg; + + if(pEvent->num_of_measurements < pEvent->avg_sample_count) + return; + + mvOsPrintf("%16s: ", pEvent->name); + for(i=0; icounters_sum[i], + pEvent->num_of_measurements, NULL); + + if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) + counters_avg -= mvCpuL2CntrsTbl[i].overhead; + else + counters_avg = 0; + + mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); + } + mvOsPrintf("\n"); + mvCpuL2CntrsEventClear(pEvent); + mvCpuL2CntrsReset(); +} + +void mvCpuL2CntrsStatus(void) +{ + int i; + + for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); +} + +static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) +{ + int i; + + for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); + pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); + } + pEvent->num_of_measurements++; +} + + +#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS + +#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) + +#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) + +#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) + +#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) + +#else + +#define MV_CPU_L2_CNTRS_READ(counter) +#define MV_CPU_L2_CNTRS_START(event) +#define MV_CPU_L2_CNTRS_STOP(event) +#define MV_CPU_L2_CNTRS_SHOW(event) + +#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ + + +#endif /* __mvCpuL2Cntrs_h__ */ + diff --git a/board/mv_feroceon/mv_hal/ddr1_2/mvCompVer.txt b/board/mv_feroceon/mv_hal/ddr1_2/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr1_2/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/ddr1_2/mvDram.c b/board/mv_feroceon/mv_hal/ddr1_2/mvDram.c new file mode 100644 index 0000000..d1b8a3d --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr1_2/mvDram.c @@ -0,0 +1,1479 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ddr1_2/mvDram.h" +#include "boardEnv/mvBoardEnvLib.h" + +#undef MV_DEBUG +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, + MV_DRAM_BANK_INFO *pBankInfo); +static MV_U32 cas2ps(MV_U8 spd_byte); +/******************************************************************************* +* mvDramBankGet - Get the DRAM bank paramters. +* +* DESCRIPTION: +* This function retrieves DRAM bank parameters as described in +* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board +* has its DRAM on DIMMs it will use its EEPROM to extract SPD data +* from it. Otherwise, if the DRAM is soldered on board, the function +* should insert its bank information into MV_DRAM_BANK_INFO struct. +* +* INPUT: +* bankNum - Board DRAM bank number. +* +* OUTPUT: +* pBankInfo - DRAM bank information struct. +* +* RETURN: +* MV_FAIL - Bank parameters could not be read. +* +*******************************************************************************/ +MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_DIMM_INFO dimmInfo; + + DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); + /* zero pBankInfo structure */ + memset(pBankInfo, 0, sizeof(*pBankInfo)); + + if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) + { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); + return MV_FAIL; + } + if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); + return MV_FAIL; + } + + /* convert Dimm info to Bank info */ + cpyDimm2BankInfo(&dimmInfo, pBankInfo); + + return MV_OK; +} + +/******************************************************************************* +* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. +* +* DESCRIPTION: +* Convert a Dimm info struct into a bank info struct. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* pBankInfo - DRAM bank information struct. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, + MV_DRAM_BANK_INFO *pBankInfo) +{ + pBankInfo->memoryType = pDimmInfo->memoryType; + + /* DIMM dimensions */ + pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; + pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; + pBankInfo->dataWidth = pDimmInfo->dataWidth; + pBankInfo->errorCheckType = pDimmInfo->errorCheckType; + pBankInfo->sdramWidth = pDimmInfo->sdramWidth; + pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; + pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; + pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; + pBankInfo->refreshInterval = pDimmInfo->refreshInterval; + + /* DIMM timing parameters */ + pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; + pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = + pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; + pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = + pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; + + pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; + pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; + pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; + pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; + pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; + pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; + pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; + pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; + + /* Parameters calculated from the extracted DIMM information */ + pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; + pBankInfo->deviceDensity = pDimmInfo->deviceDensity; + pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / + pDimmInfo->numOfModuleBanks; + + /* DIMM attributes (MV_TRUE for yes) */ + + if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || + (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) + { + if (pDimmInfo->dimmAttributes & BIT1) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } + else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ + { + if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } + + return; +} + +/******************************************************************************* +* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. +* +* DESCRIPTION: +* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdCpy(MV_VOID) +{ + MV_U32 i; + MV_U32 spdChecksum; + + MV_TWSI_SLAVE twsiSlave; + MV_U8 data[SPD_SIZE]; + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, + &twsiSlave, data, SPD_SIZE) ) + { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); + return MV_FAIL; + } + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for(i = 0 ; i <= 62 ; i++) + { + spdChecksum += data[i]; + } + + if ((spdChecksum & 0xff) != data[63]) + { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32)(spdChecksum & 0xff), data[63])); + } + else + { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the DIMM 1 SPD */ + twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + for(i = 0 ; i < SPD_SIZE ; i++) + { + twsiSlave.offset = i; + if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, + &twsiSlave, &data[i], 1) ) + { + mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); + return MV_FAIL; + } + mvOsDelay(5); + } + + DB(puts("DRAM: Reading dimm info succeded.\n")); + return MV_OK; +} + +/******************************************************************************* +* dimmSpdGet - Get the SPD parameters. +* +* DESCRIPTION: +* Read the DIMM SPD parameters into given struct parameter. +* +* INPUT: +* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. +* +* OUTPUT: +* pDimmInfo - DIMM information structure. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) +{ + MV_U32 i; + MV_U32 density = 1; + MV_U32 spdChecksum; + + MV_TWSI_SLAVE twsiSlave; + MV_U8 data[SPD_SIZE]; + + if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) + { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + twsiSlave.slaveAddr.address = (dimmNum == 0) ? + MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, + &twsiSlave, data, SPD_SIZE) ) + { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); + return MV_FAIL; + } + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for(i = 0 ; i <= 62 ; i++) + { + spdChecksum += data[i]; + } + + if ((spdChecksum & 0xff) != data[63]) + { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32)(spdChecksum & 0xff), data[63])); + } + else + { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the dimmInfo structure*/ + for(i = 0 ; i < SPD_SIZE ; i++) + { + pDimmInfo->spdRawData[i] = data[i]; + DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); + } + + DB(mvOsPrintf("DRAM SPD Information:\n")); + + /* Memory type (DDR / SDRAM) */ + switch (data[DIMM_MEM_TYPE]) + { + case (DIMM_MEM_TYPE_SDRAM): + pDimmInfo->memoryType = MEM_TYPE_SDRAM; + DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); + break; + case (DIMM_MEM_TYPE_DDR1): + pDimmInfo->memoryType = MEM_TYPE_DDR1; + DB(mvOsPrintf("DRAM Memeory type DDR1\n")); + break; + case (DIMM_MEM_TYPE_DDR2): + pDimmInfo->memoryType = MEM_TYPE_DDR2; + DB(mvOsPrintf("DRAM Memeory type DDR2\n")); + break; + default: + mvOsPrintf("ERROR: Undefined memory type!\n"); + return MV_ERROR; + } + + + /* Number Of Row Addresses */ + pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; + DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); + + /* Number Of Column Addresses */ + pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; + DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); + + /* Number Of Module Banks */ + pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", + pDimmInfo->numOfModuleBanks)); + + /* Number of module banks encoded differently for DDR2 */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) + pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; + + /* Data Width */ + pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; + DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); + + /* Minimum Cycle Time At Max CasLatancy */ + pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); + + /* Error Check Type */ + pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; + DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", + pDimmInfo->errorCheckType)); + + /* Refresh Interval */ + pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; + DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", + pDimmInfo->refreshInterval)); + + /* Sdram Width */ + pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; + DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); + + /* Error Check Data Width */ + pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; + DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", + pDimmInfo->errorCheckDataWidth)); + + /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + + pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; + DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", + pDimmInfo->burstLengthSupported)); + + /* Number Of Banks On Each Device */ + pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", + pDimmInfo->numOfBanksOnEachDevice)); + + /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; + DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", + pDimmInfo->suportedCasLatencies)); + + /* For DDR2 only, get the DIMM type information */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) + { + pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; + DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", + pDimmInfo->dimmTypeInfo)); + } + + /* SDRAM Modules Attributes */ + pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; + DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", + pDimmInfo->dimmAttributes)); + + /* Minimum Cycle Time At Max CasLatancy Minus 1*/ + pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = + cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); + + /* Minimum Cycle Time At Max CasLatancy Minus 2*/ + pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = + cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); + + pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; + DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", + pDimmInfo->minRowPrechargeTime)); + pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; + DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", + pDimmInfo->minRowActiveToRowActive)); + pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; + DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", + pDimmInfo->minRasToCasDelay)); + pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; + DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", + pDimmInfo->minRasPulseWidth)); + + /* DIMM Bank Density */ + pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; + DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", + pDimmInfo->dimmBankDensity)); + + /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ + pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; + DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", + pDimmInfo->minWriteRecoveryTime)); + + /* Only DDR2 includes Internal Write To Read Command Delay field. */ + pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; + DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", + pDimmInfo->minWriteToReadCmdDelay)); + + /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ + pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; + DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", + pDimmInfo->minReadToPrechCmdDelay)); + + /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ + pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; + DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", + pDimmInfo->minRefreshToActiveCmd)); + + /* calculating the sdram density. Representing device density from */ + /* bit 20 to allow representation of 4GB and above. */ + /* For example, if density is 512Mbit 0x20000000, will be represent in */ + /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ + /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ + density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); + pDimmInfo->deviceDensity = density * + pDimmInfo->numOfBanksOnEachDevice * + pDimmInfo->sdramWidth; + DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); + + /* Number of devices includeing Error correction */ + pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * + pDimmInfo->numOfModuleBanks; + DB(mvOsPrintf("DRAM numberOfDevices %d\n", + pDimmInfo->numberOfDevices)); + + pDimmInfo->size = 0; + + /* Note that pDimmInfo->size is in MB units */ + if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 8; /* Equal to 8MB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 4096; /* Equal to 4GB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 8192; /* Equal to 8GB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 16384; /* Equal to 16GB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + + pDimmInfo->size *= pDimmInfo->numOfModuleBanks; + + DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); + + return MV_OK; +} + +/******************************************************************************* +* dimmSpdPrint - Print the SPD parameters. +* +* DESCRIPTION: +* Print the Dimm SPD parameters. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID dimmSpdPrint(MV_U32 dimmNum) +{ + MV_DIMM_INFO dimmInfo; + MV_U32 i, temp = 0; + MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; + MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; + MV_U32 busClkPs; + MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, + temp_buf[40], *spdRawData; + + busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ + + spdRawData = dimmInfo.spdRawData; + + if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) + { + mvOsOutput("ERROR: Could not read SPD information!\n"); + return; + } + + /* find Manufactura of Dimm Module */ + mvOsOutput("\nManufacturer's JEDEC ID Code: "); + for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) + { + mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); + } + mvOsOutput("\n"); + + /* Manufacturer's Specific Data */ + for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) + { + temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; + } + mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); + + /* Module Part Number */ + for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) + { + temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; + } + mvOsOutput("Module Part Number: %s\n", temp_buf); + + /* Module Serial Number */ + for(i = 0; i < sizeof(MV_U32); i++) + { + temp |= spdRawData[95+i] << 8*i; + } + mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, + (long)temp); + + /* find Manufac-Data of Dimm Module */ + mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", + ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), + ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); + /* find modul_revision of Dimm Module */ + mvOsOutput("Module Revision: %d.%d\n", + spdRawData[91], spdRawData[92]); + + /* find manufac_place of Dimm Module */ + mvOsOutput("manufac_place: %d\n", spdRawData[72]); + + /* go over the first 35 I2C data bytes */ + for(i = 2 ; i <= 35 ; i++) + switch(i) + { + case 2: /* Memory type (DDR1/2 / SDRAM) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + mvOsOutput("Dram Type is: SDRAM\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + mvOsOutput("Dram Type is: SDRAM DDR1\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + mvOsOutput("Dram Type is: SDRAM DDR2\n"); + else + mvOsOutput("Dram Type unknown\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 3: /* Number Of Row Addresses */ + mvOsOutput("Module Number of row addresses: %d\n", + dimmInfo.numOfRowAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 4: /* Number Of Column Addresses */ + mvOsOutput("Module Number of col addresses: %d\n", + dimmInfo.numOfColAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 5: /* Number Of Module Banks */ + mvOsOutput("Number of Banks on Mod.: %d\n", + dimmInfo.numOfModuleBanks); + break; +/*----------------------------------------------------------------------------*/ + + case 6: /* Data Width */ + mvOsOutput("Module Data Width: %d bit\n", + dimmInfo.dataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 8: /* Voltage Interface */ + switch(spdRawData[i]) + { + case 0x0: + mvOsOutput("Module is TTL_5V_TOLERANT\n"); + break; + case 0x1: + mvOsOutput("Module is LVTTL\n"); + break; + case 0x2: + mvOsOutput("Module is HSTL_1_5V\n"); + break; + case 0x3: + mvOsOutput("Module is SSTL_3_3V\n"); + break; + case 0x4: + mvOsOutput("Module is SSTL_2_5V\n"); + break; + case 0x5: + if (dimmInfo.memoryType != MEM_TYPE_SDRAM) + { + mvOsOutput("Module is SSTL_1_8V\n"); + break; + } + default: + mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); + break; + } + break; +/*----------------------------------------------------------------------------*/ + + case 9: /* Minimum Cycle Time At Max CasLatancy */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 10: /* Clock To Data Out */ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 11: /* Error Check Type */ + mvOsOutput("Error Check Type (0=NONE): %d\n", + dimmInfo.errorCheckType); + break; +/*----------------------------------------------------------------------------*/ + + case 12: /* Refresh Interval */ + mvOsOutput("Refresh Rate: %x\n", + dimmInfo.refreshInterval); + break; +/*----------------------------------------------------------------------------*/ + + case 13: /* Sdram Width */ + mvOsOutput("Sdram Width: %d bits\n", + dimmInfo.sdramWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 14: /* Error Check Data Width */ + mvOsOutput("Error Check Data Width: %d bits\n", + dimmInfo.errorCheckDataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 15: /* Minimum Clock Delay is unsupported */ + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || + (dimmInfo.memoryType == MEM_TYPE_DDR1)) + { + mvOsOutput("Minimum Clk Delay back to back: %d\n", + spdRawData[i]); + } + break; +/*----------------------------------------------------------------------------*/ + + case 16: /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + mvOsOutput("Burst Length Supported: "); + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || + (dimmInfo.memoryType == MEM_TYPE_DDR1)) + { + if (dimmInfo.burstLengthSupported & BIT0) + mvOsOutput("1, "); + if (dimmInfo.burstLengthSupported & BIT1) + mvOsOutput("2, "); + } + if (dimmInfo.burstLengthSupported & BIT2) + mvOsOutput("4, "); + if (dimmInfo.burstLengthSupported & BIT3) + mvOsOutput("8, "); + + mvOsOutput(" Bit \n"); + break; +/*----------------------------------------------------------------------------*/ + + case 17: /* Number Of Banks On Each Device */ + mvOsOutput("Number Of Banks On Each Chip: %d\n", + dimmInfo.numOfBanksOnEachDevice); + break; +/*----------------------------------------------------------------------------*/ + + case 18: /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + mvOsOutput("Suported Cas Latencies: (CL) "); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + for (k = 0; k <=7; k++) + { + if (dimmInfo.suportedCasLatencies & (1 << k)) + mvOsOutput("%d, ", k+1); + } + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.suportedCasLatencies & BIT0) + mvOsOutput("1, "); + if (dimmInfo.suportedCasLatencies & BIT1) + mvOsOutput("1.5, "); + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("2.5, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("3.5, "); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("4, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("5, "); + } + else + mvOsOutput("?.?, "); + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 20: /* DDR2 DIMM type info */ + if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) + mvOsOutput("Registered DIMM (RDIMM)\n"); + else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) + mvOsOutput("Unbuffered DIMM (UDIMM)\n"); + else + mvOsOutput("Unknown DIMM type.\n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 21: /* SDRAM Modules Attributes */ + mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" Bufferd DQMB Input: Yes \n"); + else + mvOsOutput(" Bufferd DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" Registered DQMB Inputs: Yes \n"); + else + mvOsOutput(" Registered DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" redundant Row Addressing: Yes \n"); + else + mvOsOutput(" redundant Row Addressing: No \n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); + else + mvOsOutput(" FET Switch On-Card Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + mvOsOutput(" Number of Active Registers on the DIMM: %d\n", + (dimmInfo.dimmAttributes & 0x3) + 1); + + mvOsOutput(" Number of PLLs on the DIMM: %d\n", + ((dimmInfo.dimmAttributes) >> 2) & 0x3); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" Analysis probe installed: Yes \n"); + else + mvOsOutput(" Analysis probe installed: No \n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 22: /* Suported AutoPreCharge */ + mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Early Ras Precharge: Yes \n"); + else + mvOsOutput(" Early Ras Precharge: No \n"); + + if ( spdRawData[i] & BIT1 ) + mvOsOutput(" AutoPreCharge: Yes \n"); + else + mvOsOutput(" AutoPreCharge: No \n"); + + if ( spdRawData[i] & BIT2 ) + mvOsOutput(" Precharge All: Yes \n"); + else + mvOsOutput(" Precharge All: No \n"); + + if ( spdRawData[i] & BIT3 ) + mvOsOutput(" Write 1/ReadBurst: Yes \n"); + else + mvOsOutput(" Write 1/ReadBurst: No \n"); + + if ( spdRawData[i] & BIT4 ) + mvOsOutput(" lower VCC tolerance: 5%%\n"); + else + mvOsOutput(" lower VCC tolerance: 10%%\n"); + + if ( spdRawData[i] & BIT5 ) + mvOsOutput(" upper VCC tolerance: 5%%\n"); + else + mvOsOutput(" upper VCC tolerance: 10%%\n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + + if ( !(spdRawData[i] & BIT4) ) + mvOsOutput(" lower VCC tolerance: 0.2V\n"); + + if ( !(spdRawData[i] & BIT5) ) + mvOsOutput(" upper VCC tolerance: 0.2V\n"); + + if ( spdRawData[i] & BIT6 ) + mvOsOutput(" Concurrent Auto Preharge: Yes \n"); + else + mvOsOutput(" Concurrent Auto Preharge: No \n"); + + if ( spdRawData[i] & BIT7 ) + mvOsOutput(" Supports Fast AP: Yes \n"); + else + mvOsOutput(" Supports Fast AP: No \n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + } + break; +/*----------------------------------------------------------------------------*/ + + case 23: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + + mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 25: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } + else /* DDR1 or DDR2 */ + { + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + } + mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = 0; + rightOfPoint = time_tmp; + } + mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 27: /* Minimum Row Precharge Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ + trp_clocks = (temp + (busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " + "in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 28: /* Minimum Row Active to Row Active Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ + trrd_clocks = (temp + (busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " + "%d.%d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 29: /* Minimum Ras-To-Cas Delay */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ + trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; + mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " + "in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 30: /* Minimum Ras Pulse Width */ + tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " + "in Clk cycles %d\n", spdRawData[i], tras_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 31: /* Module Bank Density */ + mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("8MB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("4GB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("8GB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("16GB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 32: /* Address And Command Setup Time (measured in ns/1000) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 33: /* Address And Command Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 34: /* Data Input Setup Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 35: /* Data Input Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 36: /* Relevant for DDR2 only: Write Recovery Time */ + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); + rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; + mvOsOutput("Write Recovery Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + } + +} + + +/* + * translate ns.ns/10 coding of SPD timing values + * into ps unit values + */ +/******************************************************************************* +* cas2ps - Translate x.y ns parameter to pico-seconds values +* +* DESCRIPTION: +* This function translates x.y nano seconds to its value in pico seconds. +* For example 3.75ns will return 3750. +* +* INPUT: +* spd_byte - DIMM SPD byte. +* +* OUTPUT: +* None. +* +* RETURN: +* value in pico seconds. +* +*******************************************************************************/ +static MV_U32 cas2ps(MV_U8 spd_byte) +{ + MV_U32 ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + if( ns10 < 10 ) { + ns10 *= 10; + } + else if( ns10 == 10 ) + ns10 = 25; + else if( ns10 == 11 ) + ns10 = 33; + else if( ns10 == 12 ) + ns10 = 66; + else if( ns10 == 13 ) + ns10 = 75; + else + { + mvOsOutput("cas2ps Err. unsupported cycle time.\n"); + } + + return (ns*1000 + ns10*10); +} + diff --git a/board/mv_feroceon/mv_hal/ddr1_2/mvDram.h b/board/mv_feroceon/mv_hal/ddr1_2/mvDram.h new file mode 100644 index 0000000..678e224 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr1_2/mvDram.h @@ -0,0 +1,191 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDram +#define __INCmvDram + +#include "ddr1_2/mvDramIf.h" +#include "twsi/mvTwsi.h" + +#define MAX_DIMM_NUM 2 +#define SPD_SIZE 128 + +/* Dimm spd offsets */ +#define DIMM_MEM_TYPE 2 +#define DIMM_ROW_NUM 3 +#define DIMM_COL_NUM 4 +#define DIMM_MODULE_BANK_NUM 5 +#define DIMM_DATA_WIDTH 6 +#define DIMM_VOLT_IF 8 +#define DIMM_MIN_CC_AT_MAX_CAS 9 +#define DIMM_ERR_CHECK_TYPE 11 +#define DIMM_REFRESH_INTERVAL 12 +#define DIMM_SDRAM_WIDTH 13 +#define DIMM_ERR_CHECK_DATA_WIDTH 14 +#define DIMM_MIN_CLK_DEL 15 +#define DIMM_BURST_LEN_SUP 16 +#define DIMM_DEV_BANK_NUM 17 +#define DIMM_SUP_CAL 18 +#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ +#define DIMM_BUF_ADDR_CONT_IN 21 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 +#define DIMM_MIN_ROW_PRECHARGE_TIME 27 +#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 +#define DIMM_MIN_RAS_TO_CAS_DELAY 29 +#define DIMM_MIN_RAS_PULSE_WIDTH 30 +#define DIMM_BANK_DENSITY 31 +#define DIMM_MIN_WRITE_RECOVERY_TIME 36 +#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 +#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 +#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 + +/* Dimm Memory Type values */ +#define DIMM_MEM_TYPE_SDRAM 0x4 +#define DIMM_MEM_TYPE_DDR1 0x7 +#define DIMM_MEM_TYPE_DDR2 0x8 + +#define DIMM_MODULE_MANU_OFFS 64 +#define DIMM_MODULE_MANU_SIZE 8 +#define DIMM_MODULE_VEN_OFFS 73 +#define DIMM_MODULE_VEN_SIZE 25 +#define DIMM_MODULE_ID_OFFS 99 +#define DIMM_MODULE_ID_SIZE 18 + +/* enumeration for voltage levels. */ +typedef enum _mvDimmVoltageIf +{ + TTL_5V_TOLERANT, + LVTTL, + HSTL_1_5V, + SSTL_3_3V, + SSTL_2_5V, + VOLTAGE_UNKNOWN, +} MV_DIMM_VOLTAGE_IF; + + +/* enumaration for SDRAM CAS Latencies. */ +typedef enum _mvDimmSdramCas +{ + SD_CL_1 =1, + SD_CL_2, + SD_CL_3, + SD_CL_4, + SD_CL_5, + SD_CL_6, + SD_CL_7, + SD_FAULT +}MV_DIMM_SDRAM_CAS; + + +/* DIMM information structure */ +typedef struct _mvDimmInfo +{ + MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ + + MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 numOfModuleBanks; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY..*/ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + MV_U32 dimmBankDensity; + MV_U32 dimmTypeInfo; /* DDR2 only */ + MV_U32 dimmAttributes; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ + MV_U32 numberOfDevices; + +} MV_DIMM_INFO; + + +MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); +MV_VOID dimmSpdPrint(MV_U32 dimmNum); +MV_STATUS dimmSpdCpy(MV_VOID); + +#endif /* __INCmvDram */ diff --git a/board/mv_feroceon/mv_hal/ddr1_2/mvDramIf.c b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIf.c new file mode 100644 index 0000000..12fb26a --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIf.c @@ -0,0 +1,1599 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "ddr1_2/mvDramIf.h" +#include "ctrlEnv/sys/mvCpuIf.h" + + + +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* DRAM bank presence encoding */ +#define BANK_PRESENT_CS0 0x1 +#define BANK_PRESENT_CS0_CS1 0x3 +#define BANK_PRESENT_CS0_CS2 0x5 +#define BANK_PRESENT_CS0_CS1_CS2 0x7 +#define BANK_PRESENT_CS0_CS2_CS3 0xd +#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf + +/* locals */ +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); +#if defined(MV_INC_BOARD_DDIM) +static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); +static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); +static MV_U32 sdramModeRegCalc(MV_U32 minCas); +static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); +static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); +static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); +static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, + MV_U32 forcedCl); +static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, + MV_U32 minCas, MV_U32 busClk); +static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, + MV_U32 busClk); + +/******************************************************************************* +* mvDramIfDetect - Prepare DRAM interface configuration values. +* +* DESCRIPTION: +* This function implements the full DRAM detection and timing +* configuration for best system performance. +* Since this routine runs from a ROM device (Boot Flash), its stack +* resides on RAM, that might be the system DRAM. Changing DRAM +* configuration values while keeping vital data in DRAM is risky. That +* is why the function does not preform the configuration setting but +* prepare those in predefined 32bit registers (in this case IDMA +* registers are used) for other routine to perform the settings. +* The function will call for board DRAM SPD information for each DRAM +* chip select. The function will then analyze those SPD parameters of +* all DRAM banks in order to decide on DRAM configuration compatible +* for all DRAM banks. +* The function will set the CPU DRAM address decode registers. +* Note: This routine prepares values that will overide configuration of +* mvDramBasicAsmInit(). +* +* INPUT: +* forcedCl - Forced CAL Latency. If equal to zero, do not force. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvDramIfDetect(MV_U32 forcedCl) +{ + MV_U32 retVal = MV_OK; /* return value */ + MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; + MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; + MV_U8 minCas; + MV_DRAM_DEC_WIN dramDecWin; + + dramDecWin.addrWin.baseHigh = 0; + + busClk = mvBoardSysClkGet(); + + if (0 == busClk) + { + mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); + return MV_ERROR; + } + + /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ +#if defined(MV_INCLUDE_SDRAM_CS1) + for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) + mvCpuIfTargetWinEnable(i, MV_FALSE); +#endif + + /* we will use bank 0 as the representative of the all the DRAM banks, */ + /* since bank 0 must exist. */ + for(i = 0; i < MV_DRAM_MAX_CS; i++) + { + /* if Bank exist */ + if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) + { + /* check it isn't SDRAM */ + if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) + { + mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); + return MV_ERROR; + } + /* All banks must support registry in order to activate it */ + if(bankInfo[i].registeredAddrAndControlInputs != + bankInfo[0].registeredAddrAndControlInputs) + { + mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); + return MV_ERROR; + } + + /* Init the CPU window decode */ + /* Note that the size in Bank info is in MB units */ + /* Note that the Dimm width might be different then the device DRAM width */ + temp = MV_REG_READ(SDRAM_CONFIG_REG); + + deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; + dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); + size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); + + /* We can not change DRAM window settings while excecuting */ + /* code from it. That is why we skip the DRAM CS[0], saving */ + /* it to the ROM configuration routine */ + if(i == SDRAM_CS0) + { + MV_U32 sizeToReg; + + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" + ,i); + return MV_BAD_PARAM; + } + + /* Size is located at upper 16 bits */ + sizeToReg <<= SCSR_SIZE_OFFS; + + /* enable it */ + sizeToReg |= SCSR_WIN_EN; + + MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); + } + else + { + dramDecWin.addrWin.baseLow = base; + dramDecWin.addrWin.size = size; + dramDecWin.enable = MV_TRUE; + + if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) + { + mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", + SDRAM_CS0 + i); + return MV_ERROR; + } + } + + base += size; + + /* update the suportedCasLatencies mask */ + bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; + + } + else + { + if( i == 0 ) /* bank 0 doesn't exist */ + { + mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); + return MV_ERROR; + } + else + { + DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); + bankInfo[i].size = 0; /* Mark this bank as non exist */ + } + } + } + + /* calculate minimum CAS */ + minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); + if (0 == minCas) + { + mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", + (busClk / 1000000)); + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + minCas = DDR2_CL_4; /* Continue with this CAS */ + mvOsPrintf("Set default CAS latency 4\n"); + } + else + { + minCas = DDR1_CL_3; /* Continue with this CAS */ + mvOsPrintf("Set default CAS latency 3\n"); + } + } + + /* calc SDRAM_CONFIG_REG and save it to temp register */ + temp = sdramConfigRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG1, temp); + + /* calc SDRAM_MODE_REG and save it to temp register */ + temp = sdramModeRegCalc(minCas); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG2, temp); + + /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ + temp = sdramExtModeRegCalc(&bankInfo[0]); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG10, temp); + + /* calc D_UNIT_CONTROL_LOW and save it to temp register */ + temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG3, temp); + + /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ + temp = sdramAddrCtrlRegCalc(&bankInfo[0]); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG4, temp); + + /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ + temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG5, temp); + + /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ + temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG6, temp); + + /* Config DDR2 On Die Termination (ODT) registers */ + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + sdramDDr2OdtConfig(bankInfo); + } + + /* Note that DDR SDRAM Address/Control and Data pad calibration */ + /* settings is done in mvSdramIfConfig.s */ + + return retVal; +} + +/******************************************************************************* +* minCasCalc - Calculate the Minimum CAS latency which can be used. +* +* DESCRIPTION: +* Calculate the minimum CAS latency that can be used, base on the DRAM +* parameters and the SDRAM bus Clock freq. +* +* INPUT: +* busClk - the DRAM bus Clock. +* pBankInfo - bank info parameters. +* +* OUTPUT: +* None +* +* RETURN: +* The minimum CAS Latency. The function returns 0 if max CAS latency +* supported by banks is incompatible with system bus clock frequancy. +* +*******************************************************************************/ +static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, + MV_U32 forcedCl) +{ + MV_U32 count = 1, j; + MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ + MV_U32 startBit, stopBit; + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + + /* If we are asked to use the forced CAL */ + if (forcedCl) + { + mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), + (forcedCl % 10)); + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + if (forcedCl == 30) + pBankInfo->suportedCasLatencies = 0x08; + else if (forcedCl == 40) + pBankInfo->suportedCasLatencies = 0x10; + else + { + mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", + (forcedCl / 10), (forcedCl % 10)); + pBankInfo->suportedCasLatencies = 0x10; + } + } + else + { + if (forcedCl == 15) + pBankInfo->suportedCasLatencies = 0x02; + else if (forcedCl == 20) + pBankInfo->suportedCasLatencies = 0x04; + else if (forcedCl == 25) + pBankInfo->suportedCasLatencies = 0x08; + else if (forcedCl == 30) + pBankInfo->suportedCasLatencies = 0x10; + else if (forcedCl == 40) + pBankInfo->suportedCasLatencies = 0x40; + else + { + mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", + (forcedCl / 10), (forcedCl % 10)); + pBankInfo->suportedCasLatencies = 0x10; + } + } + + return pBankInfo->suportedCasLatencies; + } + + /* go over the supported cas mask from Max Cas down and check if the */ + /* SysClk stands in its time requirments. */ + + + DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", + pBankInfo->suportedCasLatencies,busClkPs )); + for(j = 7; j > 0; j--) + { + if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) + { + /* Reset the bits for CL incompatible for the sysClk */ + switch (count) + { + case 1: + if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 2: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 3: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + default: + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + break; + } + } + } + + DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", + pBankInfo->suportedCasLatencies )); + + /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ + /* SDRAM DDR2 controller supports CL 3 to 5 */ + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ + stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ + } + else + { + startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ + stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ + } + + for(j = startBit; j <= stopBit ; j++) + { + if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) + { + DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); + return (BIT0 << j); + } + } + + return 0; +} + +/******************************************************************************* +* sdramConfigRegCalc - Calculate sdram config register +* +* DESCRIPTION: Calculate sdram config register optimized value based +* on the bank info parameters. +* +* INPUT: +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram config reg value. +* +*******************************************************************************/ +static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 sdramConfig = 0; + MV_U32 refreshPeriod; + + busClk /= 1000000; /* we work with busClk in MHz */ + + sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); + + /* figure out the memory refresh internal */ + switch (pBankInfo->refreshInterval & 0xf) + { + case 0x0: /* refresh period is 15.625 usec */ + refreshPeriod = 15625; + break; + case 0x1: /* refresh period is 3.9 usec */ + refreshPeriod = 3900; + break; + case 0x2: /* refresh period is 7.8 usec */ + refreshPeriod = 7800; + break; + case 0x3: /* refresh period is 31.3 usec */ + refreshPeriod = 31300; + break; + case 0x4: /* refresh period is 62.5 usec */ + refreshPeriod = 62500; + break; + case 0x5: /* refresh period is 125 usec */ + refreshPeriod = 125000; + break; + default: /* refresh period undefined */ + mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); + return -1; + } + + /* Now the refreshPeriod is in register format value */ + refreshPeriod = (busClk * refreshPeriod) / 1000; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", + refreshPeriod)); + + /* make sure the refresh value is only 14 bits */ + if(refreshPeriod > SDRAM_REFRESH_MAX) + { + refreshPeriod = SDRAM_REFRESH_MAX; + DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", + refreshPeriod)); + } + + /* Clear the refresh field */ + sdramConfig &= ~SDRAM_REFRESH_MASK; + + /* Set new value to refresh field */ + sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); + + /* registered DRAM ? */ + if ( pBankInfo->registeredAddrAndControlInputs ) + { + /* it's registered DRAM, so set the reg. DRAM bit */ + sdramConfig |= SDRAM_REGISTERED; + mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); + } + + /* set DDR SDRAM devices configuration */ + sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ + + switch (pBankInfo->sdramWidth) + { + case 8: /* memory is x8 */ + sdramConfig |= SDRAM_DCFG_X8_DEV; + DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); + break; + case 16: + sdramConfig |= SDRAM_DCFG_X16_DEV; + DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); + break; + default: /* memory width unsupported */ + mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); + return -1; + } + + /* Set static default settings */ + sdramConfig |= SDRAM_CONFIG_DV; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", + sdramConfig)); + + return sdramConfig; +} + +/******************************************************************************* +* sdramModeRegCalc - Calculate sdram mode register +* +* DESCRIPTION: Calculate sdram mode register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramModeRegCalc(MV_U32 minCas) +{ + MV_U32 sdramMode; + + sdramMode = MV_REG_READ(SDRAM_MODE_REG); + + /* Clear CAS Latency field */ + sdramMode &= ~SDRAM_CL_MASK; + + mvOsPrintf("DRAM CAS Latency "); + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + switch (minCas) + { + case DDR2_CL_3: + sdramMode |= SDRAM_DDR2_CL_3; + mvOsPrintf("3.\n"); + break; + case DDR2_CL_4: + sdramMode |= SDRAM_DDR2_CL_4; + mvOsPrintf("4.\n"); + break; + case DDR2_CL_5: + sdramMode |= SDRAM_DDR2_CL_5; + mvOsPrintf("5.\n"); + break; + default: + mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); + return -1; + } + sdramMode |= DDR2_MODE_REG_DV; + } + else /* DDR1 */ + { + switch (minCas) + { + case DDR1_CL_1_5: + sdramMode |= SDRAM_DDR1_CL_1_5; + mvOsPrintf("1.5\n"); + break; + case DDR1_CL_2: + sdramMode |= SDRAM_DDR1_CL_2; + mvOsPrintf("2\n"); + break; + case DDR1_CL_2_5: + sdramMode |= SDRAM_DDR1_CL_2_5; + mvOsPrintf("2.5\n"); + break; + case DDR1_CL_3: + sdramMode |= SDRAM_DDR1_CL_3; + mvOsPrintf("3\n"); + break; + case DDR1_CL_4: + sdramMode |= SDRAM_DDR1_CL_4; + mvOsPrintf("4\n"); + break; + default: + mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); + return -1; + } + sdramMode |= DDR1_MODE_REG_DV; + } + + DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); + + return sdramMode; +} + +/******************************************************************************* +* sdramExtModeRegCalc - Calculate sdram Extended mode register +* +* DESCRIPTION: +* Return sdram Extended mode register value based +* on the bank info parameters and bank presence. +* +* INPUT: +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram Extended mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_U32 populateBanks = 0; + int bankNum; + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + { + populateBanks |= (1 << bankNum); + } + } + + switch(populateBanks) + { + case(BANK_PRESENT_CS0): + return DDR_SDRAM_EXT_MODE_CS0_DV; + + case(BANK_PRESENT_CS0_CS1): + return DDR_SDRAM_EXT_MODE_CS0_DV; + + case(BANK_PRESENT_CS0_CS2): + return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; + + case(BANK_PRESENT_CS0_CS1_CS2): + return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; + + case(BANK_PRESENT_CS0_CS2_CS3): + return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; + + case(BANK_PRESENT_CS0_CS2_CS3_CS4): + return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; + + default: + mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); + return -1; + } + } + return 0; +} + +/******************************************************************************* +* dunitCtrlLowRegCalc - Calculate sdram dunit control low register +* +* DESCRIPTION: Calculate sdram dunit control low register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram dunit control low reg value. +* +*******************************************************************************/ +static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) +{ + MV_U32 dunitCtrlLow; + + dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); + + /* Clear StBurstDel field */ + dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; + +#ifdef MV_88W8660 + /* Clear address/control output timing field */ + dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; +#endif /* MV_88W8660 */ + + DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); + + /* For proper sample of read data set the Dunit Control register's */ + /* stBurstDel bits [27:24] */ + /********-********-********-********-********-********* + * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * + *********-********-********-********-********-********* +Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * + *********-********-********-********-********-********* +Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * + *********-********-********-********-********-*********/ + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + switch (minCas) + { + case DDR2_CL_3: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; + break; + case DDR2_CL_4: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; + break; + default: + mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", + minCas); + return -1; + } + } + else /* DDR1 */ + { + switch (minCas) + { + case DDR1_CL_1_5: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; + break; + case DDR1_CL_2: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; + break; + case DDR1_CL_2_5: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; + break; + case DDR1_CL_3: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; + break; + case DDR1_CL_4: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; + break; + default: + mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", + minCas); + return -1; + } + + } + DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); + + return dunitCtrlLow; +} + +/******************************************************************************* +* sdramAddrCtrlRegCalc - Calculate sdram address control register +* +* DESCRIPTION: Calculate sdram address control register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram address control reg value. +* +*******************************************************************************/ +static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_U32 addrCtrl = 0; + + /* Set Address Control register static configuration bits */ + addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); + + /* Set address control default value */ + addrCtrl |= SDRAM_ADDR_CTRL_DV; + + /* Clear DSize field */ + addrCtrl &= ~SDRAM_DSIZE_MASK; + + /* Note that density is in MB units */ + switch (pBankInfo->deviceDensity) + { + case 128: /* 128 Mbit */ + DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); + addrCtrl |= SDRAM_DSIZE_128Mb; + break; + case 256: /* 256 Mbit */ + DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); + addrCtrl |= SDRAM_DSIZE_256Mb; + break; + case 512: /* 512 Mbit */ + DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); + addrCtrl |= SDRAM_DSIZE_512Mb; + break; + default: + mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", + pBankInfo->deviceDensity); + return -1; + } + + /* SDRAM address control */ + DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); + + return addrCtrl; +} + +/******************************************************************************* +* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register +* +* DESCRIPTION: +* This function calculates sdram timing control low register +* optimized value based on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timinf control low reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, + MV_U32 minCas, MV_U32 busClk) +{ + MV_U32 tRp = 0; + MV_U32 tRrd = 0; + MV_U32 tRcd = 0; + MV_U32 tRas = 0; + MV_U32 tWr = 0; + MV_U32 tWtr = 0; + MV_U32 tRtp = 0; + + MV_U32 bankNum; + + busClk = busClk / 1000000; /* In MHz */ + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); + tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); + tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); + tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ + /* by shifting the data two bits right. */ + tRp = tRp >> 2; /* For example 0x50 -> 20ns */ + tRrd = tRrd >> 2; + tRcd = tRcd >> 2; + + /* Extract clock cycles from time parameter. We need to round up */ + tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); + /* Micron work around for 133MHz */ + if (busClk == 133) + tRp += 1; + DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); + tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRrd = 2 */ + if (tRrd < 2) + tRrd = 2; + DB(mvOsPrintf("tRrd = %d ", tRrd)); + tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRcd = %d ", tRcd)); + tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRas = %d ", tRas)); + + /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); + tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); + tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ + /* part by shifting the data two bits right. */ + tWr = tWr >> 2; /* For example 0x50 -> 20ns */ + tWtr = tWtr >> 2; + tRtp = tRtp >> 2; + + /* Extract clock cycles from time parameter. We need to round up */ + tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); + DB(mvOsPrintf("tWr = %d ", tWr)); + tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tWtr = 2 */ + if (tWtr < 2) + tWtr = 2; + DB(mvOsPrintf("tWtr = %d ", tWtr)); + tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRtp = 2 */ + if (tRtp < 2) + tRtp = 2; + DB(mvOsPrintf("tRtp = %d ", tRtp)); + } + else + { + tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); + + if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) + { + tWtr = 2; + } + else + { + tWtr = 1; + } + + tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ + } + + DB(mvOsPrintf("tWtr = %d\n", tWtr)); + + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + return (((tRp - 1) << SDRAM_TRP_OFFS) | + ((tRrd - 1) << SDRAM_TRRD_OFFS) | + ((tRcd - 1) << SDRAM_TRCD_OFFS) | + ((tRas - 1) << SDRAM_TRAS_OFFS) | + ((tWr - 1) << SDRAM_TWR_OFFS) | + ((tWtr - 1) << SDRAM_TWTR_OFFS) | + ((tRtp - 1) << SDRAM_TRTP_OFFS)); +} + +/******************************************************************************* +* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register +* +* DESCRIPTION: +* This function calculates sdram timing control high register +* optimized value based on the bank info parameters and the bus clock. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timinf control high reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, + MV_U32 busClk) +{ + MV_U32 tRfc; + MV_U32 timeNs = 0; + int bankNum; + MV_U32 sdramTw2wCyc = 0; + + busClk = busClk / 1000000; /* In MHz */ + + /* tRfc is different for DDR1 and DDR2. */ + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + MV_U32 bankNum; + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); + } + else + { + if (pBankInfo[0].deviceDensity == _1G) + { + timeNs = SDRAM_TRFC_1G; + } + else + { + if (200 == busClk) + { + timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; + } + else + { + timeNs = SDRAM_TRFC_64_512M; + } + } + } + + tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); + + DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); + + + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + sdramTw2wCyc++; + } + + /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ + if (sdramTw2wCyc > 1) + sdramTw2wCyc = 1; + else + sdramTw2wCyc = 0; + + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | + ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | + ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | + (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | + (sdramTw2wCyc << SDRAM_TW2W_OFFS)); + +} + +/******************************************************************************* +* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. +* +* DESCRIPTION: +* This function config DDR2 On Die Termination (ODT) registers. +* ODT configuration is done according to DIMM presence: +* +* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode +* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 +* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 +* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 +* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 +* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 +* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 +* +* INPUT: +* pBankInfo - bank info parameters. +* +* OUTPUT: +* None +* +* RETURN: +* None +*******************************************************************************/ +static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_U32 populateBanks = 0; + MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; + int bankNum; + + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + { + populateBanks |= (1 << bankNum); + } + } + + switch(populateBanks) + { + case(BANK_PRESENT_CS0): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; + break; + case(BANK_PRESENT_CS0_CS1): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; + break; + case(BANK_PRESENT_CS0_CS2): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; + break; + case(BANK_PRESENT_CS0_CS1_CS2): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; + break; + case(BANK_PRESENT_CS0_CS2_CS3): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; + break; + case(BANK_PRESENT_CS0_CS2_CS3_CS4): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; + break; + default: + mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); + return; + } + MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); + MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); + MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); + return; +} +#endif /* defined(MV_INC_BOARD_DDIM) */ + +/******************************************************************************* +* mvDramIfWinSet - Set DRAM interface address decode window +* +* DESCRIPTION: +* This function sets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* pAddrDecWin - SDRAM address window structure. +* +* OUTPUT: +* None +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg=0,sizeReg=0; + MV_U32 baseToReg=0 , sizeToReg=0; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlaps with current enabled windows */ + if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + target, + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read base register*/ + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); + + /* read size register */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; + + /* Write to address decode Base Address Register */ + baseReg &= ~SCBAR_BASE_MASK; + baseReg |= baseToReg; + + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); + return MV_BAD_PARAM; + } + + /* set size */ + sizeReg &= ~SCSR_SIZE_MASK; + /* Size is located at upper 16 bits */ + sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); + + /* enable/Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + sizeReg |= SCSR_WIN_EN; + } + else + { + sizeReg &= ~SCSR_WIN_EN; + } + + /* 3) Write to address decode Base Address Register */ + MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinGet - Get DRAM interface address decode window +* +* DESCRIPTION: +* This function gets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* pAddrDecWin - SDRAM address window structure. +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg,sizeReg; + MV_U32 sizeRegVal; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Read base and size registers */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); + + sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; + + pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, + SCSR_SIZE_ALIGNMENT); + + /* Check if ctrlRegToSize returned OK */ + if (-1 == pAddrDecWin->addrWin.size) + { + mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; + + pAddrDecWin->addrWin.baseHigh = 0; + + + if (sizeReg & SCSR_WIN_EN) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinEnable - Enable/Disable SDRAM address decode window +* +* DESCRIPTION: +* This function enable/Disable SDRAM address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case function parameter are invalid, MV_OK otherewise. +* +*******************************************************************************/ +MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) +{ + MV_DRAM_DEC_WIN addrDecWin; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", + target); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode winNum window */ + MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); + } + else + { /* Overlap detected */ + mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", + target); + return MV_ERROR; + } + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window +* +* DESCRIPTION: +* This function scan each SDRAM address decode window to test if it +* overlapps the given address windoow +* +* INPUT: +* target - SDRAM target where the function skips checking. +* pAddrDecWin - The tested address window for overlapping with +* SDRAM windows. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps any enabled address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_TARGET targetNum; + MV_DRAM_DEC_WIN addrDecWin; + + for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) + { + /* don't check our winNum or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf( + "sdramIfWinOverlap: Required target %d overlap winNum %d\n", + target, targetNum); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvDramIfBankSizeGet - Get DRAM interface bank size. +* +* DESCRIPTION: +* This function returns the size of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled the function return '0'. In case +* or paramter is invalid, the function returns -1. +* +*******************************************************************************/ +MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) +{ + MV_DRAM_DEC_WIN addrDecWin; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(bankNum)) + { + mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); + return -1; + } + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return -1; + } + + if (MV_TRUE == addrDecWin.enable) + { + return addrDecWin.addrWin.size; + } + else + { + return 0; + } +} + + +/******************************************************************************* +* mvDramIfSizeGet - Get DRAM interface total size. +* +* DESCRIPTION: +* This function get the DRAM total size. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM total size. In case or paramter is invalid, the function +* returns -1. +* +*******************************************************************************/ +MV_32 mvDramIfSizeGet(MV_VOID) +{ + MV_U32 totalSize = 0, bankSize = 0, bankNum; + + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + bankSize = mvDramIfBankSizeGet(bankNum); + + if (-1 == bankSize) + { + mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); + return -1; + } + else + { + totalSize += bankSize; + } + } + + DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); + + return totalSize; +} + +/******************************************************************************* +* mvDramIfBankBaseGet - Get DRAM interface bank base. +* +* DESCRIPTION: +* This function returns the 32 bit base address of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled or paramter is invalid, the +* function returns -1. +* +*******************************************************************************/ +MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) +{ + MV_DRAM_DEC_WIN addrDecWin; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(bankNum)) + { + mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); + return -1; + } + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return -1; + } + + if (MV_TRUE == addrDecWin.enable) + { + return addrDecWin.addrWin.baseLow; + } + else + { + return -1; + } +} + + diff --git a/board/mv_feroceon/mv_hal/ddr1_2/mvDramIf.h b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIf.h new file mode 100644 index 0000000..8bfa3e8 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIf.h @@ -0,0 +1,179 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDramIfh +#define __INCmvDramIfh + +/* includes */ +#include "ddr1_2/mvDramIfRegs.h" +#include "ddr1_2/mvDramIfConfig.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +/* defines */ +/* DRAM Timing parameters */ +#define SDRAM_TWR 15 /* ns tWr */ +#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ +#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ +#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ +#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ +#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ + +/* typedefs */ + +/* enumeration for memory types */ +typedef enum _mvMemoryType +{ + MEM_TYPE_SDRAM, + MEM_TYPE_DDR1, + MEM_TYPE_DDR2 +}MV_MEMORY_TYPE; + +/* enumeration for DDR1 supported CAS Latencies */ +typedef enum _mvDimmDdr1Cas +{ + DDR1_CL_1_5 = 0x02, + DDR1_CL_2 = 0x04, + DDR1_CL_2_5 = 0x08, + DDR1_CL_3 = 0x10, + DDR1_CL_4 = 0x40, + DDR1_CL_FAULT +} MV_DIMM_DDR1_CAS; + +/* enumeration for DDR2 supported CAS Latencies */ +typedef enum _mvDimmDdr2Cas +{ + DDR2_CL_3 = 0x08, + DDR2_CL_4 = 0x10, + DDR2_CL_5 = 0x20, + DDR2_CL_FAULT +} MV_DIMM_DDR2_CAS; + + +typedef struct _mvDramBankInfo +{ + MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY..*/ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ + MV_U32 numberOfDevices; + + /* DIMM attributes (MV_TRUE for yes) */ + MV_BOOL registeredAddrAndControlInputs; + +}MV_DRAM_BANK_INFO; + +/* This structure describes CPU interface address decode window */ +typedef struct _mvDramIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +}MV_DRAM_DEC_WIN; + +#include "ddr1_2/mvDram.h" + +/* mvDramIf.h API list */ +MV_VOID mvDramIfBasicAsmInit(MV_VOID); +MV_STATUS mvDramIfDetect(MV_U32 forcedCl); +MV_VOID _mvDramIfConfig(MV_VOID); + +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); +MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); +MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); +MV_32 mvDramIfSizeGet(MV_VOID); + +#if 0 +MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); +MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); +#endif + +#endif /* __INCmvDramIfh */ diff --git a/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfBasicInit.S b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfBasicInit.S new file mode 100644 index 0000000..f2a9365 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfBasicInit.S @@ -0,0 +1,988 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvSysHwConfig.h" +#include "mvOsAsm.h" +#include "mvBoardEnvSpec.h" +#include "mvCpuIfRegs.h" +#include "mvDramIfConfig.h" +#include "mvDramIfRegs.h" +#include "pex/mvPexRegs.h" +#include "pci/mvPciRegs.h" +#include "mvCtrlEnvSpec.h" +#include "mvCtrlEnvAsm.h" +#include "cpu/mvCpuArm.h" +#include "mvCommon.h" + +/* defines */ + +#if !defined(MV_INC_BOARD_DDIM) +.globl dramBoot1 +dramBoot1: + .word 0 + +/****************************************************************************** +* +* +* +* +*******************************************************************************/ +#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG) + +/* PEX_PCI and PRPMC boards 256 MB*/ +#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 +#define STATIC_SDRAM_CONFIG 0x03248400 +#define STATIC_SDRAM_MODE 0x62 +#define STATIC_DUNIT_CTRL_LOW 0x4041000 +#define STATIC_SDRAM_ADDR_CTRL 0x00000020 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F +#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 +#define STATIC_SDRAM_ODT_CTRL_HI 0x0 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 +#define STATIC_SDRAM_EXT_MODE 0x0 + +#elif defined(DB_FPGA) + +/* FPGA DC boards 256 MB*/ +#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 +#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */ +#define STATIC_SDRAM_MODE 0x22 +#define STATIC_DUNIT_CTRL_LOW 0x03041000 +#define STATIC_SDRAM_ADDR_CTRL 0x00000020 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D +#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 +#define STATIC_SDRAM_ODT_CTRL_HI 0x0 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 +#define STATIC_SDRAM_EXT_MODE 0x1 + +#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER) + +/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */ +#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 +#define STATIC_SDRAM_CONFIG 0x03158400 +#define STATIC_SDRAM_MODE 0x452 +#define STATIC_DUNIT_CTRL_LOW 0x06041000 +#define STATIC_SDRAM_ADDR_CTRL 0x00000020 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 +#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 +#define STATIC_SDRAM_EXT_MODE 0x00000440 + + +#elif defined(RD_88F6183AP) + +/* DDR2 1 devices 512Mbit by 16 bit */ +#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 +#define STATIC_SDRAM_CONFIG 0x1f154400 +#define STATIC_SDRAM_MODE 0x432 +#define STATIC_DUNIT_CTRL_LOW 0x04041000 +#define STATIC_SDRAM_ADDR_CTRL 0x00000020 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 +#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 +#define STATIC_SDRAM_EXT_MODE 0x00000440 + +/* 6082L MARVELL DIMM */ +#elif defined(DB_88F6082LBP) +#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 +#define STATIC_SDRAM_CONFIG 0x7f158400 +#define STATIC_SDRAM_MODE 0x432 +#define STATIC_DUNIT_CTRL_LOW 0x04041040 +#define STATIC_SDRAM_ADDR_CTRL 0x00000020 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501 +#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01 +#define STATIC_SDRAM_EXT_MODE 0x00000440 + +#elif defined(RD_88W8660_AP82S) + +/* Shark RD */ + +#if defined(MV_DRAM_32M) +#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x00000010 +#elif defined(MV_DRAM_16M) + +#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x00000000 + +#else +#error "NO DDR size selected" +#endif + +#define STATIC_SDRAM_CONFIG 0x03144400 +#define STATIC_SDRAM_MODE 0x62 +#define STATIC_DUNIT_CTRL_LOW 0x4041000 + +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b +#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 +#define STATIC_SDRAM_ODT_CTRL_HI 0x0 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 +#define STATIC_SDRAM_EXT_MODE 0x0 + +#elif defined(RD_88W8660) + +/* Shark RD */ +#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 +#define STATIC_SDRAM_CONFIG 0x03144400 +#define STATIC_SDRAM_MODE 0x62 +#define STATIC_DUNIT_CTRL_LOW 0x4041000 +#define STATIC_SDRAM_ADDR_CTRL 0x00000010 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b +#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 +#define STATIC_SDRAM_ODT_CTRL_HI 0x0 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 +#define STATIC_SDRAM_EXT_MODE 0x0 + +#else /* NAS */ + + +#if defined(RD_88F5182) + +#if defined(MV_88F5082) +#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x20 +#else +#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x20 +#endif + +#elif defined(RD_88F5182_3) + +#if defined(MV_88F5082) +#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x20 +#else +#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x20 +#endif + +#else + +#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x0 + +#endif + +#if defined(MV_88F5082) +#define STATIC_SDRAM_CONFIG 0x3144400 +#else +#define STATIC_SDRAM_CONFIG 0x3148400 +#endif +#define STATIC_SDRAM_MODE 0x62 +#define STATIC_DUNIT_CTRL_LOW 0x4041000 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x40c +#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 +#define STATIC_SDRAM_ODT_CTRL_HI 0x0 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 +#define STATIC_SDRAM_EXT_MODE 0x0 + +#endif + + .globl _mvDramIfStaticInit +_mvDramIfStaticInit: + + mov r11, LR /* Save link register */ + mov r10, r2 + + /* If we boot from NAND jump to DRAM sddress */ + + mov r5, #1 + ldr r6, =dramBoot1 + str r5, [r6] /* We started executing from DRAM */ + + ldr r6, dramBoot1 + cmp r6, #0 + bne 1f + + + /* set all dram windows to 0 */ + mov r6, #0 + MV_REG_WRITE_ASM(r6, r5, 0x1504) + MV_REG_WRITE_ASM(r6, r5, 0x150c) + MV_REG_WRITE_ASM(r6, r5, 0x1514) + MV_REG_WRITE_ASM(r6, r5, 0x151c) + + /* set all dram configuration in temp registers */ + ldr r6, = STATIC_SDRAM0_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) + ldr r6, = STATIC_SDRAM_CONFIG + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) + ldr r6, = STATIC_SDRAM_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) + ldr r6, = STATIC_DUNIT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) + ldr r6, = STATIC_SDRAM_ADDR_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) + ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) + ldr r6, = STATIC_SDRAM_TIME_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) + ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) + ldr r6, = STATIC_SDRAM_ODT_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) + ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) + ldr r6, = STATIC_SDRAM_EXT_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) + + mov sp, #0 + bl _mvDramIfConfig +1: + mov r2, r10 + mov PC, r11 /* r11 is saved link register */ + +#else /* #if !defined(MV_INC_BOARD_DDIM) */ + +.globl dramBoot1 +dramBoot1: + .word 0 + +/******************************************************************************* +* mvDramIfBasicInit - Basic initialization of DRAM interface +* +* DESCRIPTION: +* The function will initialize the DRAM for basic usage. The function +* will use the TWSI assembly API to extract DIMM parameters according +* to which DRAM interface will be initialized. +* The function referes to the following DRAM parameters: +* 1) DIMM is registered or not. +* 2) DIMM width detection. +* 3) DIMM density. +* +* INPUT: +* r3 - required size for initial DRAM. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* Note: +* r4 holds I2C EEPROM address +* r5 holds SDRAM register base address +* r7 holds returned values +* r8 holds SDRAM various configuration registers value. +* r11 holds return function address. +*******************************************************************************/ +/* Setting the offsets of the I2C registers */ +#define NUM_OF_ROWS_OFFSET 3 +#define NUM_OF_COLS_OFFSET 4 +#define NUM_OF_RANKS 5 +#define SDRAM_WIDTH_OFFSET 13 +#define NUM_OF_BANKS_OFFSET 17 +#define SUPPORTED_CL_OFFSET 18 +#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ +#define SDRAM_MODULES_ATTR_OFFSET 21 + +#define DRAM_DEV_DENSITY_128M 0x080 +#define DRAM_DEV_DENSITY_256M 0x100 +#define DRAM_DEV_DENSITY_512M 0x200 + .globl _mvDramIfBasicInit + .extern _i2cInit + +_mvDramIfBasicInit: + + mov r11, LR /* Save link register */ + + mov r5, #1 + ldr r8, =dramBoot1 + str r5, [r8] /* We started executing from DRAM */ + + /* If we boot from NAND jump to DRAM sddress */ + ldr r8, dramBoot1 + cmp r8, #0 + movne pc, r11 + + + + bl _i2cInit /* Initialize TWSI master */ + + /* Get default SDRAM Config values */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + bic r8, r8, #SDRAM_DCFG_MASK + + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r4, r5); + + /* Return if OrionN */ + ldr r5, =MV_5180_DEV_ID + cmp r4, r5 + beq cat_through_end + + /* Return if Orion1 */ + ldr r5, =MV_5181_DEV_ID + cmp r4, r5 + beq cat_through_end + + /* Return if Nas */ + ldr r5, =MV_5182_DEV_ID + cmp r4, r5 + beq cat_through_end + + /* Return if Shark */ + ldr r5, =MV_8660_DEV_ID + cmp r4, r5 + beq cat_through_end + + /* goto calcConfigReg if bigger than Orion2*/ + ldr r5, =MV_5281_DEV_ID + cmp r4, r5 + bne cat_through + +cat_through: + /* set cat through - for better performance - in orion2 b0 and higher*/ + orr r8, r8, #SDRAM_CATTHR_EN + +cat_through_end: + + + /* Get registered/non registered info from DIMM */ + bl _is_Registered + beq nonRegistered + +setRegistered: + orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ + +nonRegistered: + /* Get SDRAM width */ + bl _get_width + + orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */ + cmp r7, #16 + beq setConfigReg + + orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */ + cmp r7, #8 + beq setConfigReg + + /* This is an error. return */ + b exit_ddrAutoConfig + +setConfigReg: + mov r8, r6 + ldr r6, =SDRAM_CONFIG_DV + orr r8, r8, r6 /* Add default settings */ + mov r6, r8 /* Do not swap r8 content */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG) + + /* Set maximum CL supported by DIMM */ + bl _get_CAL + + /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ + clz r6, r7 + rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ + + /* Check the DDR version */ + tst r8, #SDRAM_DTYPE_DDR2 + bne casDdr2 + +casDdr1: + ldr r7, =3 /* stBurstDel field value */ + ldr r8, =0x52 /* Assuming MAX CL = 1.5 */ + cmp r6, #1 /* If CL = 1.5 break */ + beq setModeReg + + ldr r7, =3 /* stBurstDel field value */ + ldr r8, =0x22 /* Assuming MAX CL = 2 */ + cmp r6, #2 /* If CL = 2 break */ + beq setModeReg + + ldr r7, =4 /* stBurstDel field value */ + ldr r8, =0x62 /* Assuming MAX CL = 2.5 */ + cmp r6, #3 /* If CL = 2.5 break */ + beq setModeReg + + ldr r7, =4 /* stBurstDel field value */ + ldr r8, =0x32 /* Assuming MAX CL = 3 */ + cmp r6, #4 /* If CL = 3 break */ + beq setModeReg + + ldr r7, =5 /* stBurstDel field value */ + ldr r8, =0x42 /* Assuming MAX CL = 4 */ + cmp r6, #6 /* If CL = 4 break */ + b setModeReg + + b exit_ddrAutoConfig /* This is an error !! */ + +casDdr2: + ldr r7, =4 /* stBurstDel field value */ + ldr r8, =0x32 /* Assuming MAX CL = 3 */ + cmp r6, #3 /* If CL = 3 break */ + beq casDdr2Cont + + ldr r7, =5 /* stBurstDel field value */ + ldr r8, =0x42 /* Assuming MAX CL = 4 */ + cmp r6, #4 /* If CL = 4 break */ + beq casDdr2Cont + + /* CL 5 currently unsupported. We use CL 4 instead */ + ldr r7, =5 /* stBurstDel field value */ + ldr r8, =0x42 /* Assuming MAX CL = 5 */ + cmp r6, #5 /* If CL = 5 break */ + beq casDdr2Cont + + b exit_ddrAutoConfig /* This is an error !! */ +casDdr2Cont: + /* Write recovery for auto-precharge relevant only in DDR2 */ + orr r8, r8, #0x400 /* Default value */ + +setModeReg: + /* The CPU must not attempt to change the SDRAM Mode register setting */ + /* prior to DRAM controller completion of the DRAM initialization */ + /* sequence. To guarantee this restriction, it is recommended that */ + /* the CPU sets the SDRAM Operation register to NOP command, performs */ + /* read polling until the register is back in Normal operation value, */ + /* and then sets SDRAM Mode register to it's new value. */ + + /* write 'nop' to SDRAM operation */ + mov r6, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll1: + ldr r6, [r5] + cmp r6, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll1 + + /* Now its safe to write new value to SDRAM Mode register */ + MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG) + + /* Make the Dunit write the DRAM its new mode */ + mov r6, #0x3 /* Mode Register Set command */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll2: + ldr r6, [r5] + cmp r6, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll2 + + /* Set Dunit control register according to max CL detected */ + /* If we use registered DIMM, add 1 to stBurstDel */ + MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG) + tst r6, #SDRAM_REGISTERED + beq setDunitReg + add r7, r7, #1 + +setDunitReg: + ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV + orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS + MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) + + + /* DIMM density configuration*/ + /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ +Density: + bl _getDensity + mov r8, r7 + mov r8, r8, LSR #20 /* Move density 20 bits to the right */ + /* For example 0x10000000 --> 0x1000 */ + + mov r6, #0x00 + cmp r8, #DRAM_DEV_DENSITY_128M + beq densCont + + mov r6, #0x10 + cmp r8, #DRAM_DEV_DENSITY_256M + beq densCont + + mov r6, #0x20 + cmp r8, #DRAM_DEV_DENSITY_512M + beq densCont + + /* This is an error. return */ + b exit_ddrAutoConfig + +densCont: + MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG) + + /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + tst r8, #SDRAM_DTYPE_DDR2 + beq _extModeODTEnd + + + /* Set DDR Extended Mode register for working with CS[0] */ + /* write 'nop' to SDRAM operation */ + mov r6, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll3: + ldr r6, [r5] + cmp r6, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll3 + + /* Now its safe to write new value to SDRAM Extended Mode register */ + ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV + MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG) + + /* Make the Dunit write the DRAM its new extended mode */ + mov r6, #0x4 /* Extended Mode Register Set command */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll4: + ldr r6, [r5] + cmp r6, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll4 + + /* ODT configuration is done for single bank CS[0] only */ + /* Config DDR2 On Die Termination (ODT) registers */ + ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV + MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG) + + ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV + MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + + ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV + MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG) + + + /* we will check what device we are running and perform + Initialization according to device value */ + +_extModeODTEnd: + + /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ + /* Does Not Work for Address/Control and Data Pads. */ + /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r6, r5); + /* Read device revision */ + MV_CTRL_REV_GET_ASM(r8, r5); + + /* Continue if OrionN */ + ldr r5, =MV_5180_DEV_ID + cmp r6, r5 + bne 1f + b glMem2End +1: + + /* Continue if Orion1 and device revision B1 */ + ldr r5, =MV_5181_DEV_ID + cmp r6, r5 + bne 1f + + cmp r8, #MV_5181_B1_REV + bge glMem2End + b glMem2Start +1: + + /* Orion NAS */ + ldr r5, =MV_5182_DEV_ID + cmp r6, r5 + beq glMem2Start + + /* Orion Shark */ + ldr r5, =MV_8660_DEV_ID + cmp r6, r5 + beq glMem2Start + + b glMem2End + +glMem2Start: + + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + /* Set Bit [31] to make the register writable */ + orr r8, r6, #SDRAM_WR_EN + + MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ + bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ + bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ + bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ + + /* Get the final N locked value of driving strength [22:17] */ + mov r5, r6 + mov r5, r5, LSL #9 + mov r5, r5, LSR #26 /* r5[5:0] = r6[22:17] */ + orr r5, r5, r5, LSL #6 /* r5[11:6] = r5[5:0] */ + + /* Write to both bits [5:0] and bits [11:6] */ + orr r6, r6, r5 + + MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) + + /* Set Bit [31] to make the register writable */ + orr r8, r6, #SDRAM_WR_EN + + MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG) + + bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ + bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ + bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ + bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ + + /* Get the final N locked value of driving strength [22:17] */ + mov r5, r6 + mov r5, r5, LSL #9 + mov r5, r5, LSR #26 + orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17] */ + + /* Write to both bits [5:0] and bits [11:6] */ + orr r6, r6, r5 + + MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) + +glMem2End: + /* Implement Guideline (GL# MEM-3) Drive Strength Value */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + + /* Get SDRAM Config value */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + + /* Get DIMM type */ + tst r8, #SDRAM_DTYPE_DDR2 + beq ddr1StrengthVal + +ddr2StrengthVal: + ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV + ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV + b setDrvStrength +ddr1StrengthVal: + ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV + ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV + +setDrvStrength: + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ + + MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + HTOLL(r6,r5) + + bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ + bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK + orr r6, r4, r6 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) + + orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ + + MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) + HTOLL(r6,r5) + + bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ + bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK + orr r6, r8, r6 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) + + + /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + /* Get the "sample on reset" register for the DDR frequancy */ + +#if defined(MV_RUN_FROM_FLASH) + /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ + ldr r7, = _cpuARMDDRCLK + ldr r4, =_start + ldr r4, [r4] + sub r7, r7, r4 + ldr r4, = Lrom_start_of_data + ldr r4, [r4] + add r7, r4, r7 +#else + /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ + ldr r7, = _cpuARMDDRCLK + ldr r4, =_start + sub r7, r7, r4 + add r7, r7, #CFG_MONITOR_BASE +#endif + /* Get the "sample on reset" register for the DDR frequancy */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_ARMDDRCLCK_MASK + and r5, r4, r5 +#if 0 /* YOTAM TO BE FIX */ + mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS +#endif + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r6, r8); + + /* Continue if TC90 */ + ldr r8, =MV_1281_DEV_ID + cmp r6, r6 + beq armClkMsb + + /* Continue if Orion2 */ + ldr r8, =MV_5281_DEV_ID + cmp r6, r8 +#if 0 /* YOTAM TO BE FIX */ + bne 1f +#endif + +armClkMsb: +#if 0 /* YOTAM TO BE FIX */ + tst r4, #MSAR_ARMDDRCLCK_H_MASK + beq 1f + orr r5, r5, #BIT4 +1: + ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE + mul r5, r4, r5 + add r7, r7, r5 + add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF + ldr r5, [r7] +#endif + + /* Get SDRAM Config value */ + MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG) + + /* Get DIMM type */ + tst r8, #SDRAM_DTYPE_DDR2 + beq ddr1FtdllVal + +ddr2FtdllVal: + ldr r4, =FTDLL_DDR2_250MHZ + ldr r7, =_250MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_200MHZ + ldr r7, =_200MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_166MHZ + ldr r7, =_166MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_133MHZ + b setFtdllReg + +ddr1FtdllVal: + ldr r4, =FTDLL_DDR1_200MHZ + ldr r7, =_200MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR1_166MHZ + ldr r7, =_166MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR1_133MHZ + ldr r7, =_133MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =0 + +setFtdllReg: + +#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) + MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) + orr r8, r8, r4 + MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) + bic r8, r8, #1 + MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) +#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/ + + +setTimingReg: + /* Set default Timing parameters */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + tst r8, #SDRAM_DTYPE_DDR2 + bne ddr2TimeParam + +ddr1TimeParam: + ldr r6, =DDR1_TIMING_LOW_DV + MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) + ldr r6, =DDR1_TIMING_HIGH_DV + MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) + b timeParamDone + +ddr2TimeParam: + ldr r6, =DDR2_TIMING_LOW_DV + MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) + ldr r6, =DDR2_TIMING_HIGH_DV + MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) + +timeParamDone: + /* Open CS[0] window to requested size and enable it. Disable other */ + /* windows */ + ldr r6, =SCBAR_BASE_MASK + sub r3, r3, #1 + and r3, r3, r6 + orr r3, r3, #1 /* Enable bank */ + MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0)) + ldr r6, =0 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1)) + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2)) + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3)) + +exit_ddrAutoConfig: + mov PC, r11 /* r11 is saved link register */ + + +/***************************************************************************************/ +/* r4 holds I2C EEPROM address + * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value + * r8 holds SDRAM various configuration registers value. + * r13 holds Link register + */ +/**************************/ +_getDensity: + mov r13, LR /* Save link register */ + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ + bl _i2cRead + mov r8, r7 /* r8 save number of rows */ + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ + bl _i2cRead + add r8, r8, r7 /* r8 = number of rows + number of col */ + + mov r7, #0x1 + mov r8, r7, LSL r8 /* r8 = (1 << r8) */ + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ + bl _i2cRead + mul r8, r7, r8 + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ + bl _i2cRead + mul r7, r8, r7 + + mov PC, r13 + +/**************************/ +_get_width: + mov r13, LR /* Save link register */ + + /* Get SDRAM width (SPD offset 13) */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SDRAM_WIDTH_OFFSET + bl _i2cRead /* result in r7 */ + + mov PC, r13 + +/**************************/ +_get_CAL: + mov r13, LR /* Save link register */ + + /* Set maximum CL supported by DIMM */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ + bl _i2cRead + + mov PC, r13 + +/**************************/ +/* R8 - sdram configuration register. + * Return value in flag if no-registered then Z-flag is set + */ +_is_Registered: + mov r13, LR /* Save link register */ + + /* Get registered/non registered info from DIMM */ + tst r8, #SDRAM_DTYPE_DDR2 + bne regDdr2 + +regDdr1: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SDRAM_MODULES_ATTR_OFFSET + bl _i2cRead /* result in r7 */ + tst r7, #0x2 + b exit +regDdr2: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_TYPE_INFO_OFFSET + bl _i2cRead /* result in r7 */ + tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ + /* or Mini-RDIMM (0x10) */ +exit: + mov PC, r13 + + +#endif diff --git a/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfConfig.S b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfConfig.S new file mode 100644 index 0000000..e34ebbf --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfConfig.S @@ -0,0 +1,668 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvDramIfBasicAsm.s +* +* DESCRIPTION: +* Memory full detection and best timing configuration is done in +* C code. C runtime environment requires a stack. This module API +* initialize DRAM interface chip select 0 for basic functionality for +* the use of stack. +* The module API assumes DRAM information is stored in I2C EEPROM reside +* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM +* internal data structure is assumed to be orgenzied in common DRAM +* vendor SPD structure. +* NOTE: DFCDL values are assumed to be already initialized prior to +* this module API activity. +* +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include "mvSysHwConfig.h" +#include "mvDramIfRegs.h" +#include "mvDramIfConfig.h" +#include "mvCpuIfRegs.h" +#include "pex/mvPexRegs.h" +#include "pci/mvPciRegs.h" +#include "mvCtrlEnvSpec.h" +#include "mvCtrlEnvAsm.h" +#include "cpu/mvCpuArm.h" +#include "mvCommon.h" + +/* defines */ + +/* locals */ +.data +.globl _mvDramIfConfig + +.text + +/******************************************************************************* +* _mvDramIfConfig - Basic DRAM interface initialization. +* +* DESCRIPTION: +* The function will initialize the following DRAM parameters using the +* values prepared by mvDramIfDetect routine. Values are located +* in predefined registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ + +_mvDramIfConfig: + + /* Save register on stack */ + cmp sp, #0 + beq no_stack_s +save_on_stack: + stmdb sp!, {r1, r2, r3, r4, r7, r11} +no_stack_s: + + /* 1) Write to SDRAM coniguration register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) + str r4, [r1] + + /* 2) Write Dunit control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) + str r4, [r1] + + /* 3) Write SDRAM address control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) + str r4, [r1] + + /* 4) Write SDRAM bank 0 size register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0)) + str r4, [r1] + + /* 5) Write SDRAM open pages control register */ + ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) + ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV + str r4, [r1] + + /* 6) Write SDRAM timing Low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) + str r4, [r1] + + /* 7) Write SDRAM timing High register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) + str r4, [r1] + + /* 8) Write SDRAM mode register */ + /* The CPU must not attempt to change the SDRAM Mode register setting */ + /* prior to DRAM controller completion of the DRAM initialization */ + /* sequence. To guarantee this restriction, it is recommended that */ + /* the CPU sets the SDRAM Operation register to NOP command, performs */ + /* read polling until the register is back in Normal operation value, */ + /* and then sets SDRAM Mode register to it’s new value. */ + + /* 8.1 write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) + + /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll1: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll1 + + /* 8.3 Now its safe to write new value to SDRAM Mode register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) + str r4, [r1] + + /* 8.4 Make the Dunit write the DRAM its new mode */ + mov r4, #0x3 /* Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll2: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll2 + +#ifndef DB_FPGA + /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ + MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG) + tst r4, #SDRAM_DTYPE_DDR2 + beq _extModeODTEnd +#endif /* DB_FPGA */ + + /* 9) Write SDRAM Extended mode register This operation should be */ + /* done for each memory bank */ + /* write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll3: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll3 + + /* Now its safe to write new value to SDRAM Extended Mode register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) + str r4, [r1] + + /* Go over each of the Banks */ + ldr r3, =0 /* r3 = DRAM bank Num */ + +extModeLoop: + /* Set the SDRAM Operation Control to each of the DRAM banks */ + mov r2, r3 /* Do not swap the bank counter value */ + MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG) + + /* Make the Dunit write the DRAM its new mode */ + mov r4, #0x4 /* Extended Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll4: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll4 +#ifndef DB_FPGA + add r3, r3, #1 + cmp r3, #4 /* 4 = Number of banks */ + bne extModeLoop + +extModeEnd: + /* Config DDR2 On Die Termination (ODT) registers */ + /* Write SDRAM DDR2 ODT control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) + str r4, [r1] + + /* Write SDRAM DDR2 ODT control high register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) + str r4, [r1] + + /* Write SDRAM DDR2 Dunit ODT control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) + str r4, [r1] + +#endif /* DB_FPGA */ +_extModeODTEnd: +#ifndef DB_FPGA + /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ + /* Does Not Work for Address/Control and Data Pads. */ + /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r3, r1); + /* Read device revision */ + MV_CTRL_REV_GET_ASM(r2, r1); + + /* Continue if OrionN */ + ldr r1, =MV_5180_DEV_ID + cmp r3, r1 + bne 1f + b glMem2End +1: + /* Continue if Orion1 and device revision B1 */ + ldr r1, =MV_5181_DEV_ID + cmp r3, r1 + bne 1f + + cmp r2, #MV_5181_B1_REV + bge glMem2End + b glMem2Start +1: + + /* Orion NAS */ + ldr r1, =MV_5182_DEV_ID + cmp r3, r1 + beq glMem2Start + + /* Orion NAS */ + ldr r1, =MV_5082_DEV_ID + cmp r3, r1 + beq glMem2Start + + /* Orion Shark */ + ldr r1, =MV_8660_DEV_ID + cmp r3, r1 + beq glMem2Start + + b glMem2End + +glMem2Start: + + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + /* Set Bit [31] to make the register writable */ + orr r2, r3, #SDRAM_WR_EN + + MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ + bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ + bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ + bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ + + /* Get the final N locked value of driving strength [22:17] */ + mov r1, r3 + mov r1, r1, LSL #9 + mov r1, r1, LSR #26 /* r1[5:0] = r3[22:17] */ + orr r1, r1, r1, LSL #6 /* r1[11:6] = r1[5:0] */ + + /* Write to both bits [5:0] and bits [11:6] */ + orr r3, r3, r1 + + MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) + + /* Set Bit [31] to make the register writable */ + orr r2, r3, #SDRAM_WR_EN + + MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG) + + bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ + bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ + bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ + bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ + + /* Get the final N locked value of driving strength [22:17] */ + mov r1, r3 + mov r1, r1, LSL #9 + mov r1, r1, LSR #26 + orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17] */ + + /* Write to both bits [5:0] and bits [11:6] */ + orr r3, r3, r1 + + MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) + +glMem2End: + + + /* Implement Guideline (GL# MEM-3) Drive Strength Value */ + /* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */ + /* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */ + + /* Get SDRAM Config value */ + MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG) + + /* Get DIMM type */ + tst r2, #SDRAM_DTYPE_DDR2 + beq ddr1StrengthVal + +ddr2StrengthVal: + ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV + ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV + b setDrvStrength +ddr1StrengthVal: + ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV + ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV + +setDrvStrength: + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ + + MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + HTOLL(r3,r1) + + bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ + bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK + orr r3, r4, r3 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) + + orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ + + MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) + HTOLL(r3,r1) + + bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ + bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK + orr r3, r2, r3 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) + +#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) + /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */ + /* 88F5082, 88F5181L, 88F6082/L */ + + /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ + ldr r7, = _cpuARMDDRCLK + ldr r4, =_start + sub r7, r7, r4 + add r7, r7, #CFG_MONITOR_BASE + + /* Get the "sample on reset" register for the DDR frequancy */ + MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET) + ldr r1, =MSAR_ARMDDRCLCK_MASK + and r1, r4, r1 +#if 0 /* YOTAM TO BE FIX */ + mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS +#endif + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r3, r2); + + /* Continue if TC90 */ + ldr r2, =MV_1281_DEV_ID + cmp r3, r2 + beq armClkMsb + + /* Continue if Orion2 */ + ldr r2, =MV_5281_DEV_ID + cmp r3, r2 +#if 0 /* YOTAM TO BE FIX */ + bne 1f +#endif + +armClkMsb: +#if 0 /* YOTAM TO BE FIX */ + tst r4, #MSAR_ARMDDRCLCK_H_MASK + beq 1f + orr r1, r1, #BIT4 +1: + ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE + mul r1, r4, r1 + add r7, r7, r1 + add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF + ldr r1, [r7] +#endif + + /* Get SDRAM Config value */ + MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG) + + /* Get DIMM type */ + tst r2, #SDRAM_DTYPE_DDR2 + beq ddr1FtdllVal + +ddr2FtdllVal: + ldr r2, =MV_5281_DEV_ID + cmp r3, r2 + bne 2f + MV_CTRL_REV_GET_ASM(r3, r2) + cmp r3, #MV_5281_D0_REV + beq orin2_d0_ddr2_ftdll_val + cmp r3, #MV_5281_D1_REV + beq orin2_d1_ddr2_ftdll_val + cmp r3, #MV_5281_D2_REV + beq orin2_d1_ddr2_ftdll_val + b ddr2_default_val + +/* Set Orion 2 D1 ftdll values for DDR2 */ +orin2_d1_ddr2_ftdll_val: + ldr r4, =FTDLL_DDR2_250MHZ_5281_D1 + ldr r7, =_250MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_200MHZ_5281_D1 + ldr r7, =_200MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + b ddr2_default_val + +/* Set Orion 2 D0 ftdll values for DDR2 */ +orin2_d0_ddr2_ftdll_val: + ldr r4, =FTDLL_DDR2_250MHZ_5281_D0 + ldr r7, =_250MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_200MHZ_5281_D0 + ldr r7, =_200MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + b ddr2_default_val +2: + ldr r2, =MV_5182_DEV_ID + cmp r3, r2 + bne 3f + +/* Set Orion nas ftdll values for DDR2 */ +orin_nas_ftdll_val: + ldr r4, =FTDLL_DDR2_166MHZ_5182 + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + +/* default values for all other devices */ +3: +ddr2_default_val: + ldr r4, =FTDLL_DDR2_250MHZ + ldr r7, =_250MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_200MHZ + ldr r7, =_200MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_166MHZ + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_133MHZ + ldr r7, =_133MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =0 + b setFtdllReg + +ddr1FtdllVal: + ldr r2, =MV_5281_DEV_ID + cmp r3, r2 + bne 2f + MV_CTRL_REV_GET_ASM(r3, r2) + cmp r3, #MV_5281_D0_REV + bge orin2_ddr1_ftdll_val + b ddr1_default_val + +/* Set Orion 2 D0 and above ftdll values for DDR1 */ +orin2_ddr1_ftdll_val: + ldr r4, =FTDLL_DDR1_200MHZ_5281_D0 + ldr r7, =_200MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR1_166MHZ_5281_D0 + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + b ddr1_default_val +2: + ldr r2, =MV_5181_DEV_ID + cmp r3, r2 + bne 3f + MV_CTRL_REV_GET_ASM(r3, r2) + cmp r3, #MV_5181_B1_REV + bge orin1_ddr1_ftdll_val + b ddr1_default_val + +/* Set Orion 1 ftdll values for DDR1 */ +orin1_ddr1_ftdll_val: + ldr r4, =FTDLL_DDR1_166MHZ_5181_B1 + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg +3: +ddr1_default_val: + ldr r4, =FTDLL_DDR1_133MHZ + ldr r7, =_133MHz + cmp r1, r7 + beq setFtdllReg + + ldr r4, =FTDLL_DDR1_166MHZ + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + + ldr r4, =FTDLL_DDR1_200MHZ + ldr r7, =_200MHz + cmp r1, r7 + beq setFtdllReg + + ldr r4, =0 + +setFtdllReg: + + MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) + HTOLL(r4,r1) + bic r4, r4, #1 + MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) + +#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */ +#endif /* DB_FPGA */ + +restoreTmpRegs: + /* Restore the registers we used to save the DDR detect values */ + + ldr r4, =DRAM_BUF_REG0_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0) + + ldr r4, =DRAM_BUF_REG1_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1) + + ldr r4, =DRAM_BUF_REG2_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2) + + ldr r4, =DRAM_BUF_REG3_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3) + + ldr r4, =DRAM_BUF_REG4_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4) + + ldr r4, =DRAM_BUF_REG5_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5) + + ldr r4, =DRAM_BUF_REG6_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6) + + ldr r4, =DRAM_BUF_REG7_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7) + + ldr r4, =DRAM_BUF_REG8_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8) + + ldr r4, =DRAM_BUF_REG9_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9) + + ldr r4, =DRAM_BUF_REG10_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10) + + + /* Restore registers */ + /* Save register on stack */ + cmp sp, #0 + beq no_stack_l +load_from_stack: + ldmia sp!, {r1, r2, r3, r4, r7, r11} +no_stack_l: + + mov pc, lr + diff --git a/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfConfig.h b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfConfig.h new file mode 100644 index 0000000..a7c6644 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfConfig.h @@ -0,0 +1,192 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDramIfConfigh +#define __INCmvDramIfConfigh + +/* includes */ + +/* defines */ + +/* registers defaults values */ + +#define SDRAM_CONFIG_DV \ + (SDRAM_PERR_WRITE | \ + SDRAM_SRMODE | \ + SDRAM_SRCLK_GATED) + +#define SDRAM_DUNIT_CTRL_LOW_DV \ + (SDRAM_CTRL_POS_RISE | \ + SDRAM_CLK1DRV_NORMAL | \ + SDRAM_LOCKEN_ENABLE) + +#define SDRAM_ADDR_CTRL_DV 0 + +#define SDRAM_TIMING_CTRL_LOW_REG_DV \ + ((0x2 << SDRAM_TRCD_OFFS) | \ + (0x2 << SDRAM_TRP_OFFS) | \ + (0x1 << SDRAM_TWR_OFFS) | \ + (0x0 << SDRAM_TWTR_OFFS) | \ + (0x5 << SDRAM_TRAS_OFFS) | \ + (0x1 << SDRAM_TRRD_OFFS)) +/* TRFC 0x27, TW2W 0x1 */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ + ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ + ( 0x1 << SDRAM_TW2W_OFFS)) + +#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN + +/* DDR2 ODT default register values */ + +/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ +/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ + +#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 +#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F +#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 + +#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C +#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F +#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 + + +/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ +#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ + (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) +#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + + +#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ + (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) +#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + +/* DDR SDRAM Mode Register default value */ +#define DDR1_MODE_REG_DV 0x00000000 +#define DDR2_MODE_REG_DV 0x00000400 + +/* DDR SDRAM Timing parameter default values */ +#define DDR1_TIMING_LOW_DV 0x11602220 +#define DDR1_TIMING_HIGH_DV 0x0000000d + +#define DDR2_TIMING_LOW_DV 0x11812220 +#define DDR2_TIMING_HIGH_DV 0x0000030f + +/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ +#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ + (0x7F<< 12) | \ + (0x1 << 22)) + +#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ + +#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ + (0x1 << 12) | \ + (0x3 << 14) | \ + (0x1 << 18) | \ + (0x1 << 22)) + + +#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ + (0x1 << 12) | \ + (0x1 << 14) | \ + (0x1 << 16) | \ + (0x1 << 19) | \ + (0xF << 20)) + +#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ + +#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ + (0x1 << 12) | \ + (0x1 << 14) | \ + (0x1 << 16) | \ + (0x1 << 19) | \ + (0xF << 20)) + +#define FTDLL_DDR2_250MHZ 0x445001 + +/* Orion 1 B1 and above */ +#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 + +/* Orion nas */ +#define FTDLL_DDR2_166MHZ_5182 0x597001 + +/* Orion 2 D0 and above */ +#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 +#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 +#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 +#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 +#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 +#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 +#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 + +#endif /* __INCmvDramIfh */ diff --git a/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfRegs.h b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfRegs.h new file mode 100644 index 0000000..e9cd7c4 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr1_2/mvDramIfRegs.h @@ -0,0 +1,306 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDramIfRegsh +#define __INCmvDramIfRegsh + + +/* DDR SDRAM Controller Address Decode Registers */ +/* SDRAM CSn Base Address Register (SCBAR) */ +#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) +#define SCBAR_BASE_OFFS 16 +#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) +#define SCBAR_BASE_ALIGNMENT 0x10000 + +/* SDRAM CSn Size Register (SCSR) */ +#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) +#define SCSR_WIN_EN BIT0 +#define SCSR_SIZE_OFFS 16 +#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) +#define SCSR_SIZE_ALIGNMENT 0x10000 + +/* configuration register */ +#define SDRAM_CONFIG_REG 0x1400 +#define SDRAM_REFRESH_OFFS 0 +#define SDRAM_REFRESH_MAX 0x3000 +#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) +#define SDRAM_DWIDTH_OFFS 14 +#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DTYPE_OFFS 16 +#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) +#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) +#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) +#define SDRAM_REGISTERED (1 << 17) +#define SDRAM_PERR_OFFS 18 +#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) +#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) +#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) +#define SDRAM_DCFG_OFFS 20 +#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) +#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) +#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) +#define SDRAM_SRMODE (1 << 24) +#define SDRAM_SRCLK_OFFS 25 +#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_CATTH_OFFS 26 +#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) + + +/* dunit control register */ +#define SDRAM_DUNIT_CTRL_REG 0x1404 +#define SDRAM_CTRL_POS_OFFS 6 +#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CLK1DRV_OFFS 12 +#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_LOCKEN_OFFS 18 +#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) +#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) +#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) +#define SDRAM_ST_BURST_DEL_OFFS 24 +#define SDRAM_ST_BURST_DEL_MAX 0xf +#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) + { + mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); + return MV_ERROR; + } + + /* All banks must support registry in order to activate it */ + if(bankInfo[i].registeredAddrAndControlInputs != + bankInfo[0].registeredAddrAndControlInputs) + { + mvOsOutput("Dram: ERR. different Registered settings !!!\n"); + return MV_ERROR; + } + + /* All banks must support same ECC mode */ + if(bankInfo[i].errorCheckType != + bankInfo[0].errorCheckType) + { + mvOsOutput("Dram: ERR. different ECC settings !!!\n"); + return MV_ERROR; + } + + } + else + { + if( i == 0 ) /* bank 0 doesn't exist */ + { + mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); + return MV_ERROR; + } + else + { + DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); + bankInfo[i].size = 0; /* Mark this bank as non exist */ + } + } + } + +#ifdef MV_INCLUDE_SDRAM_CS2 + if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) + { + MV_DRAM_CS_order[0] = SDRAM_CS2; + MV_DRAM_CS_order[1] = SDRAM_CS3; + MV_DRAM_CS_order[2] = SDRAM_CS0; + MV_DRAM_CS_order[3] = SDRAM_CS1; + DRAM_CS_Order[0] = SDRAM_CS2; + DRAM_CS_Order[1] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS0; + DRAM_CS_Order[3] = SDRAM_CS1; + + } + else +#endif + { + MV_DRAM_CS_order[0] = SDRAM_CS0; + MV_DRAM_CS_order[1] = SDRAM_CS1; + DRAM_CS_Order[0] = SDRAM_CS0; + DRAM_CS_Order[1] = SDRAM_CS1; +#ifdef MV_INCLUDE_SDRAM_CS2 + MV_DRAM_CS_order[2] = SDRAM_CS2; + MV_DRAM_CS_order[3] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS2; + DRAM_CS_Order[3] = SDRAM_CS3; +#endif + } + + for(j = 0; j < MV_DRAM_MAX_CS; j++) + { + i = MV_DRAM_CS_order[j]; + + if (0 == bankInfo[i].size) + continue; + + /* Init the CPU window decode */ + /* Note that the Dimm width might be different then the device DRAM width */ +#ifdef MV78XX0 + temp = MV_REG_READ(SDRAM_CONFIG_REG); + deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; +#else + deviceW = 16 /* KW family */; +#endif + dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); + size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); + + /* We can not change DRAM window settings while excecuting */ + /* code from it. That is why we skip the DRAM CS[0], saving */ + /* it to the ROM configuration routine */ + + numOfAllDevices += bankInfo[i].numberOfDevices; + if (i == MV_DRAM_CS_order[0]) + { + MV_U32 sizeToReg; + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" + ,i); + return MV_BAD_PARAM; + } + + DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) + sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); + sizeToReg |= SCSR_WIN_EN; + MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); + } + else + { + dramDecWin.addrWin.baseLow = base; + dramDecWin.addrWin.size = size; + dramDecWin.enable = MV_TRUE; + DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); + + /* Check if the DRAM size is more then 3GByte */ + if (base < 0xC0000000) + { + DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); + if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) + { + mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); + return MV_ERROR; + } + } + } + + base += size; + + /* update the suportedCasLatencies mask */ + bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; + } + + /* calculate minimum CAS */ + minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); + if (0 == minCas) + { + mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", + (busClk / 1000000)); + + minCas = DDR2_CL_4; /* Continue with this CAS */ + mvOsOutput("Set default CAS latency 4\n"); + } + + /* calc SDRAM_CONFIG_REG and save it to temp register */ + temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); + return MV_ERROR; + } + + /* check if ECC is enabled by the user */ + if(eccDisable) + { + /* turn off ECC*/ + temp &= ~BIT18; + } + DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG1, temp); + + /* calc SDRAM_MODE_REG and save it to temp register */ + temp = sdramModeRegCalc(minCas); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG2, temp); + + /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ + temp = sdramExtModeRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG10, temp); + + /* calc D_UNIT_CONTROL_LOW and save it to temp register */ + TTMode = MV_FALSE; + DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) + if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) + { + if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || + (numOfAllDevices > 18) ) + { + mvOsOutput("Enable 2T "); + TTMode = MV_TRUE; + } + } + + temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG3, temp); + + /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ + temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) + /* check if ECC is enabled by the user */ + if(eccDisable) + { + /* turn off sample stage if no ecc */ + temp &= ~SDRAM__D2P_EN;; + } + MV_REG_WRITE(DRAM_BUF_REG13, temp); + + /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ + temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG4, temp); + + /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ + temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG5, temp); + + /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ + temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG6, temp); + + sdramDDr2OdtConfig(bankInfo); + + /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ + temp = sdramDdr2TimeLoRegCalc(minCas); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG11, temp); + + /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ + temp = sdramDdr2TimeHiRegCalc(minCas); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG12, temp); +#endif + + /* Note that DDR SDRAM Address/Control and Data pad calibration */ + /* settings is done in mvSdramIfConfig.s */ + + return MV_OK; +} + + +/******************************************************************************* +* mvDramIfBankBaseGet - Get DRAM interface bank base. +* +* DESCRIPTION: +* This function returns the 32 bit base address of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled or paramter is invalid, the +* function returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) +{ + DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", + bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); + return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); +} + +/******************************************************************************* +* mvDramIfBankSizeGet - Get DRAM interface bank size. +* +* DESCRIPTION: +* This function returns the size of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled the function return '0'. In case +* or paramter is invalid, the function returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) +{ + DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", + bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); + return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); +} + + +/******************************************************************************* +* mvDramIfSizeGet - Get DRAM interface total size. +* +* DESCRIPTION: +* This function get the DRAM total size. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM total size. In case or paramter is invalid, the function +* returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfSizeGet(MV_VOID) +{ + MV_U32 size = 0, i; + + for(i = 0; i < MV_DRAM_MAX_CS; i++) + size += mvDramIfBankSizeGet(i); + + DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); + return size; +} + +/******************************************************************************* +* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. +* +* DESCRIPTION: +* The ECC single bit error threshold is the number of single bit +* errors to happen before the Dunit generates an interrupt. +* This function set single bit ECC threshold. +* +* INPUT: +* threshold - threshold. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) +{ + MV_U32 regVal; + + if (threshold > SECR_THRECC_MAX) + { + return MV_BAD_PARAM; + } + + regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); + regVal &= ~SECR_THRECC_MASK; + regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); + MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); + + return MV_OK; +} + +#ifndef MV_STATIC_DRAM_ON_BOARD +/******************************************************************************* +* minCasCalc - Calculate the Minimum CAS latency which can be used. +* +* DESCRIPTION: +* Calculate the minimum CAS latency that can be used, base on the DRAM +* parameters and the SDRAM bus Clock freq. +* +* INPUT: +* busClk - the DRAM bus Clock. +* pBankInfo - bank info parameters. +* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. +* +* OUTPUT: +* None +* +* RETURN: +* The minimum CAS Latency. The function returns 0 if max CAS latency +* supported by banks is incompatible with system bus clock frequancy. +* +*******************************************************************************/ + +static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) +{ + MV_U32 count = 1, j; + MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ + MV_U32 startBit, stopBit; + MV_U32 minCas0 = 0, minCas2 = 0; + + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * + Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * + *********************************************************/ + + + /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ + if (forcedCl) + { + mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); + + if (forcedCl == 30) + pBankInfo->suportedCasLatencies = 0x08; + else if (forcedCl == 40) + pBankInfo->suportedCasLatencies = 0x10; + else if (forcedCl == 50) + pBankInfo->suportedCasLatencies = 0x20; + else if (forcedCl == 60) + pBankInfo->suportedCasLatencies = 0x40; + else + { + mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", + (forcedCl / 10), (forcedCl % 10)); + pBankInfo->suportedCasLatencies = 0x10; + } + + return pBankInfo->suportedCasLatencies; + } + + /* go over the supported cas mask from Max Cas down and check if the */ + /* SysClk stands in its time requirments. */ + + DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", + pBankInfo->suportedCasLatencies,busClkPs )); + count = 1; + for(j = 7; j > 0; j--) + { + if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) + { + /* Reset the bits for CL incompatible for the sysClk */ + switch (count) + { + case 1: + if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 2: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 3: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + default: + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + break; + } + } + } + + DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", + pBankInfo->suportedCasLatencies )); + + count = 1; + DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", + pBankInfo2->suportedCasLatencies,busClkPs )); + for(j = 7; j > 0; j--) + { + if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) + { + /* Reset the bits for CL incompatible for the sysClk */ + switch (count) + { + case 1: + if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 2: + if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 3: + if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + default: + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + break; + } + } + } + + DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", + pBankInfo2->suportedCasLatencies )); + + startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ + stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ + + for(j = startBit; j <= stopBit ; j++) + { + if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) + { + DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); + minCas0 = (BIT0 << j); + break; + } + } + + for(j = startBit; j <= stopBit ; j++) + { + if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) + { + DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); + minCas2 = (BIT0 << j); + break; + } + } + + if (minCas2 > minCas0) + return minCas2; + else + return minCas0; + + return 0; +} + +/******************************************************************************* +* sdramConfigRegCalc - Calculate sdram config register +* +* DESCRIPTION: Calculate sdram config register optimized value based +* on the bank info parameters. +* +* INPUT: +* busClk - the DRAM bus Clock. +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram config reg value. +* +*******************************************************************************/ +static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) +{ + MV_U32 sdramConfig = 0; + MV_U32 refreshPeriod; + + busClk /= 1000000; /* we work with busClk in MHz */ + + sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); + + /* figure out the memory refresh internal */ + switch (pBankInfo->refreshInterval & 0xf) + { + case 0x0: /* refresh period is 15.625 usec */ + refreshPeriod = 15625; + break; + case 0x1: /* refresh period is 3.9 usec */ + refreshPeriod = 3900; + break; + case 0x2: /* refresh period is 7.8 usec */ + refreshPeriod = 7800; + break; + case 0x3: /* refresh period is 31.3 usec */ + refreshPeriod = 31300; + break; + case 0x4: /* refresh period is 62.5 usec */ + refreshPeriod = 62500; + break; + case 0x5: /* refresh period is 125 usec */ + refreshPeriod = 125000; + break; + default: /* refresh period undefined */ + mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); + return -1; + } + + /* Now the refreshPeriod is in register format value */ + refreshPeriod = (busClk * refreshPeriod) / 1000; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", + refreshPeriod)); + + /* make sure the refresh value is only 14 bits */ + if(refreshPeriod > SDRAM_REFRESH_MAX) + { + refreshPeriod = SDRAM_REFRESH_MAX; + DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", + refreshPeriod)); + } + + /* Clear the refresh field */ + sdramConfig &= ~SDRAM_REFRESH_MASK; + + /* Set new value to refresh field */ + sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); + + /* registered DRAM ? */ + if ( pBankInfo->registeredAddrAndControlInputs ) + { + /* it's registered DRAM, so set the reg. DRAM bit */ + sdramConfig |= SDRAM_REGISTERED; + DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) + } + + /* ECC and IERR support */ + sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ + sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ + + if ( pBankInfo->errorCheckType ) + { + sdramConfig |= SDRAM_ECC_EN; + sdramConfig |= SDRAM_IERR_REPORTE; + DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); + } + else + { + sdramConfig |= SDRAM_ECC_DIS; + sdramConfig |= SDRAM_IERR_IGNORE; + DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); + } + /* Set static default settings */ + sdramConfig |= SDRAM_CONFIG_DV; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", + sdramConfig)); + + return sdramConfig; +} + +/******************************************************************************* +* sdramModeRegCalc - Calculate sdram mode register +* +* DESCRIPTION: Calculate sdram mode register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramModeRegCalc(MV_U32 minCas) +{ + MV_U32 sdramMode; + + sdramMode = MV_REG_READ(SDRAM_MODE_REG); + + /* Clear CAS Latency field */ + sdramMode &= ~SDRAM_CL_MASK; + + DB(mvOsPrintf("DRAM CAS Latency ");) + + switch (minCas) + { + case DDR2_CL_3: + sdramMode |= SDRAM_DDR2_CL_3; + DB(mvOsPrintf("3.\n");) + break; + case DDR2_CL_4: + sdramMode |= SDRAM_DDR2_CL_4; + DB(mvOsPrintf("4.\n");) + break; + case DDR2_CL_5: + sdramMode |= SDRAM_DDR2_CL_5; + DB(mvOsPrintf("5.\n");) + break; + case DDR2_CL_6: + sdramMode |= SDRAM_DDR2_CL_6; + DB(mvOsPrintf("6.\n");) + break; + default: + mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); + return -1; + } + + DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); + + return sdramMode; +} +/******************************************************************************* +* sdramExtModeRegCalc - Calculate sdram Extended mode register +* +* DESCRIPTION: +* Return sdram Extended mode register value based +* on the bank info parameters and bank presence. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - DRAM frequency +* +* OUTPUT: +* None +* +* RETURN: +* sdram Extended mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 populateBanks = 0; + int bankNum; + + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + { + populateBanks |= (1 << bankNum); + } + } + + switch(populateBanks) + { + case(BANK_PRESENT_CS0): + case(BANK_PRESENT_CS0_CS1): + return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; + + case(BANK_PRESENT_CS0_CS2): + case(BANK_PRESENT_CS0_CS1_CS2): + case(BANK_PRESENT_CS0_CS2_CS3): + case(BANK_PRESENT_CS0_CS2_CS3_CS4): + if (busClk >= MV_BOARD_SYSCLK_267MHZ) + return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; + else + return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; + + default: + mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); + return -1; + } + return 0; +} + +/******************************************************************************* +* dunitCtrlLowRegCalc - Calculate sdram dunit control low register +* +* DESCRIPTION: Calculate sdram dunit control low register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram dunit control low reg value. +* +*******************************************************************************/ +static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) +{ + MV_U32 dunitCtrlLow, cl; + MV_U32 sbOutR[4]={3,5,7,9} ; + MV_U32 sbOutU[4]={1,3,5,7} ; + + dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); + + DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); + + /* Clear StBurstOutDel field */ + dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; + + /* Clear StBurstInDel field */ + dunitCtrlLow &= ~SDRAM_SB_IN_MASK; + + /* Clear CtrlPos field */ + dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; + + /* Clear 2T field */ + dunitCtrlLow &= ~SDRAM_2T_MASK; + if (TTMode == MV_TRUE) + { + dunitCtrlLow |= SDRAM_2T_MODE; + } + + /* For proper sample of read data set the Dunit Control register's */ + /* stBurstInDel bits [27:24] */ + /* 200MHz - 267MHz None reg = CL + 1 */ + /* 200MHz - 267MHz reg = CL + 2 */ + /* > 267MHz None reg = CL + 2 */ + /* > 267MHz reg = CL + 3 */ + + /* For proper sample of read data set the Dunit Control register's */ + /* stBurstOutDel bits [23:20] */ + /********-********-********-********- + * CL=3 | CL=4 | CL=5 | CL=6 | + *********-********-********-********- + Not Reg. * 0001 | 0011 | 0101 | 0111 | + *********-********-********-********- + Registered * 0011 | 0101 | 0111 | 1001 | + *********-********-********-********/ + + /* Set Dunit Control low default value */ + dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; + + switch (minCas) + { + case DDR2_CL_3: cl = 3; break; + case DDR2_CL_4: cl = 4; break; + case DDR2_CL_5: cl = 5; break; + case DDR2_CL_6: cl = 6; break; + default: + mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); + return -1; + } + + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + { + dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; + } + else + { + dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; + } + + DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); + + if (busClk <= MV_BOARD_SYSCLK_267MHZ) + { + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + cl = cl + 2; + else + cl = cl + 1; + } + else + { + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + cl = cl + 3; + else + cl = cl + 2; + } + + DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); + dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; + + DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); + + return dunitCtrlLow; +} + +/******************************************************************************* +* dunitCtrlHighRegCalc - Calculate sdram dunit control high register +* +* DESCRIPTION: Calculate sdram dunit control high register optimized value based +* on the bus clock. +* +* INPUT: +* busClk - DRAM frequency. +* +* OUTPUT: +* None +* +* RETURN: +* sdram dunit control high reg value. +* +*******************************************************************************/ +static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 dunitCtrlHigh; + dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); + if(busClk > MV_BOARD_SYSCLK_300MHZ) + dunitCtrlHigh |= SDRAM__P2D_EN; + else + dunitCtrlHigh &= ~SDRAM__P2D_EN; + + if(busClk > MV_BOARD_SYSCLK_267MHZ) + dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); + + /* If ECC support we turn on D2P sample */ + dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ + if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) + dunitCtrlHigh |= SDRAM__D2P_EN; + + return dunitCtrlHigh; +} + +/******************************************************************************* +* sdramAddrCtrlRegCalc - Calculate sdram address control register +* +* DESCRIPTION: Calculate sdram address control register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram address control reg value. +* +*******************************************************************************/ +static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) +{ + MV_U32 addrCtrl = 0; + + if (pBankInfoDIMM1->size) + { + switch (pBankInfoDIMM1->sdramWidth) + { + case 4: /* memory is x4 */ + mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); + return -1; + break; + case 8: /* memory is x8 */ + addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); + break; + case 16: + addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); + break; + default: /* memory width unsupported */ + mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); + return -1; + } + } + + switch (pBankInfo->sdramWidth) + { + case 4: /* memory is x4 */ + mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); + return -1; + break; + case 8: /* memory is x8 */ + addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); + break; + case 16: + addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); + break; + default: /* memory width unsupported */ + mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); + return -1; + } + + /* Note that density is in MB units */ + switch (pBankInfo->deviceDensity) + { + case 256: /* 256 Mbit */ + DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); + addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); + break; + case 512: /* 512 Mbit */ + DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); + addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); + break; + case 1024: /* 1 Gbit */ + DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); + addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); + break; + case 2048: /* 2 Gbit */ + DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); + addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); + break; + default: + mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", + pBankInfo->deviceDensity); + return -1; + } + + if (pBankInfoDIMM1->size) + { + switch (pBankInfoDIMM1->deviceDensity) + { + case 256: /* 256 Mbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); + addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); + break; + case 512: /* 512 Mbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); + addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); + break; + case 1024: /* 1 Gbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); + addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); + break; + case 2048: /* 2 Gbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); + addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); + break; + default: + mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", + pBankInfoDIMM1->deviceDensity); + return -1; + } + } + /* SDRAM address control */ + DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); + + return addrCtrl; +} + +/******************************************************************************* +* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register +* +* DESCRIPTION: +* This function calculates sdram timing control low register +* optimized value based on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* minCas - minimum CAS supported. +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timing control low reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) +{ + MV_U32 tRp = 0; + MV_U32 tRrd = 0; + MV_U32 tRcd = 0; + MV_U32 tRas = 0; + MV_U32 tWr = 0; + MV_U32 tWtr = 0; + MV_U32 tRtp = 0; + MV_U32 timeCtrlLow = 0; + + MV_U32 bankNum; + + busClk = busClk / 1000000; /* In MHz */ + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); + tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); + tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); + tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ + /* by shifting the data two bits right. */ + tRp = tRp >> 2; /* For example 0x50 -> 20ns */ + tRrd = tRrd >> 2; + tRcd = tRcd >> 2; + + /* Extract clock cycles from time parameter. We need to round up */ + tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); + DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); + tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRrd = 2 */ + if (tRrd < 2) + tRrd = 2; + DB(mvOsPrintf("tRrd = %d ", tRrd)); + tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRcd = %d ", tRcd)); + tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRas = %d ", tRas)); + + /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); + tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); + tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ + /* part by shifting the data two bits right. */ + tWr = tWr >> 2; /* For example 0x50 -> 20ns */ + tWtr = tWtr >> 2; + tRtp = tRtp >> 2; + /* Extract clock cycles from time parameter. We need to round up */ + tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); + DB(mvOsPrintf("tWr = %d ", tWr)); + tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tWtr = 2 */ + if (tWtr < 2) + tWtr = 2; + DB(mvOsPrintf("tWtr = %d ", tWtr)); + tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRtp = 2 */ + if (tRtp < 2) + tRtp = 2; + DB(mvOsPrintf("tRtp = %d ", tRtp)); + + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | + ((tRrd - 1) << SDRAM_TRRD_OFFS) | + ((tRcd - 1) << SDRAM_TRCD_OFFS) | + (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| + ((tWr - 1) << SDRAM_TWR_OFFS) | + ((tWtr - 1) << SDRAM_TWTR_OFFS) | + ((tRtp - 1) << SDRAM_TRTP_OFFS)); + + /* Check extended tRas bit */ + if ((tRas - 1) & BIT4) + timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); + + return timeCtrlLow; +} + +/******************************************************************************* +* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register +* +* DESCRIPTION: +* This function calculates sdram timing control high register +* optimized value based on the bank info parameters and the bus clock. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timing control high reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 tRfc; + MV_U32 timingHigh; + MV_U32 timeNs = 0; + MV_U32 bankNum; + + busClk = busClk / 1000000; /* In MHz */ + + /* Set DDR timing high register static configuration bits */ + timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); + + /* Set DDR timing high register default value */ + timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; + + /* Clear tRfc field */ + timingHigh &= ~SDRAM_TRFC_MASK; + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); + DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", + pBankInfo[bankNum].minRefreshToActiveCmd)); + } + if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) + { + timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; + } + + tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); + timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); + DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); + + /* SDRAM timing high */ + DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); + + return timingHigh; +} +/******************************************************************************* +* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. +* +* DESCRIPTION: +* This function config DDR2 On Die Termination (ODT) registers. +* +* INPUT: +* pBankInfo - bank info parameters. +* +* OUTPUT: +* None +* +* RETURN: +* None +*******************************************************************************/ +static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_U32 populateBanks = 0; + MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; + int bankNum; + + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + { + populateBanks |= (1 << bankNum); + } + } + + switch(populateBanks) + { + case(BANK_PRESENT_CS0): + case(BANK_PRESENT_CS0_CS1): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; + break; + case(BANK_PRESENT_CS0_CS2): + case(BANK_PRESENT_CS0_CS1_CS2): + case(BANK_PRESENT_CS0_CS2_CS3): + case(BANK_PRESENT_CS0_CS2_CS3_CS4): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; + break; + default: + DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); + return; + } + /* DDR2 SDRAM ODT ctrl low */ + DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); + MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); + + /* DDR2 SDRAM ODT ctrl high */ + DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); + MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); + + /* DDR2 DUNIT ODT ctrl */ + if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || + (mvCtrlModelGet() == MV_76100_DEV_ID) || + (mvCtrlModelGet() == MV_78100_DEV_ID) || + (mvCtrlModelGet() == MV_78200_DEV_ID) || + (mvCtrlModelGet() == MV_6321_DEV_ID) || + (mvCtrlModelGet() == MV_6322_DEV_ID) || + (mvCtrlModelGet() == MV_6323_DEV_ID)) + dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ + + DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); + MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); + return; +} +/******************************************************************************* +* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. +* +* DESCRIPTION: +* This function config DDR2 DRAM Timing low registers. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* DDR2 sdram timing low reg value. +*******************************************************************************/ +static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) +{ + MV_U8 cl = -1; + MV_U32 ddr2TimeLoReg; + + /* read and clear the feilds we are going to set */ + ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); + ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | + SD2TLR_TODT_OFF_RD_MASK | + SD2TLR_TODT_ON_CTRL_RD_MASK | + SD2TLR_TODT_OFF_CTRL_RD_MASK); + + if( minCas == DDR2_CL_3 ) + { + cl = 3; + } + else if( minCas == DDR2_CL_4 ) + { + cl = 4; + } + else if( minCas == DDR2_CL_5 ) + { + cl = 5; + } + else if( minCas == DDR2_CL_6 ) + { + cl = 6; + } + else + { + DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", + minCas)); + cl = 4; + } + + ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); + ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); + ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); + ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); + + /* DDR2 SDRAM timing low */ + DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); + + return ddr2TimeLoReg; +} + +/******************************************************************************* +* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. +* +* DESCRIPTION: +* This function config DDR2 DRAM Timing high registers. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* DDR2 sdram timing high reg value. +*******************************************************************************/ +static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) +{ + MV_U8 cl = -1; + MV_U32 ddr2TimeHiReg; + + /* read and clear the feilds we are going to set */ + ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); + ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | + SD2THR_TODT_OFF_WR_MASK | + SD2THR_TODT_ON_CTRL_WR_MASK | + SD2THR_TODT_OFF_CTRL_WR_MASK); + + if( minCas == DDR2_CL_3 ) + { + cl = 3; + } + else if( minCas == DDR2_CL_4 ) + { + cl = 4; + } + else if( minCas == DDR2_CL_5 ) + { + cl = 5; + } + else if( minCas == DDR2_CL_6 ) + { + cl = 6; + } + else + { + mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", + minCas); + cl = 4; + } + + ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); + ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); + ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); + ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); + + /* DDR2 SDRAM timin high */ + DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); + + return ddr2TimeHiReg; +} +#endif + +/******************************************************************************* +* mvDramIfCalGet - Get CAS Latency +* +* DESCRIPTION: +* This function get the CAS Latency. +* +* INPUT: +* None +* +* OUTPUT: +* None +* +* RETURN: +* CAS latency times 10 (to avoid using floating point). +* +*******************************************************************************/ +MV_U32 mvDramIfCalGet(void) +{ + MV_U32 sdramCasLat, casLatMask; + + casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); + + switch (casLatMask) + { + case SDRAM_DDR2_CL_3: + sdramCasLat = 30; + break; + case SDRAM_DDR2_CL_4: + sdramCasLat = 40; + break; + case SDRAM_DDR2_CL_5: + sdramCasLat = 50; + break; + case SDRAM_DDR2_CL_6: + sdramCasLat = 60; + break; + default: + mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); + return -1; + } + + return sdramCasLat; +} + + +/******************************************************************************* +* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - +* +* DESCRIPTION: +* add support in power management. +* +* +* INPUT: +* None +* +* OUTPUT: +* None +* +* RETURN: +* None +* +*******************************************************************************/ + +MV_VOID mvDramIfSelfRefreshSet() +{ + MV_U32 operReg; + + operReg = MV_REG_READ(SDRAM_OPERATION_REG); + MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); + /* Read until register is reset to 0 */ + while(MV_REG_READ(SDRAM_OPERATION_REG)); +} +/******************************************************************************* +* mvDramIfDimGetSPDversion - return DIMM SPD version. +* +* DESCRIPTION: +* This function prints the DRAM controller information. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) +{ + MV_DIMM_INFO dimmInfo; + if (bankNum >= MV_DRAM_MAX_CS ) + { + DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); + return ; + } + memset(&dimmInfo,0,sizeof(dimmInfo)); + if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); + return ; + } + *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; + *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; +} +/******************************************************************************* +* mvDramIfShow - Show DRAM controller information. +* +* DESCRIPTION: +* This function prints the DRAM controller information. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvDramIfShow(void) +{ + int i, sdramCasLat, sdramCsSize; + MV_U32 Major=0, Minor=0; + + mvOsOutput("DRAM Controller info:\n"); + + mvOsOutput("Total DRAM "); + mvSizePrint(mvDramIfSizeGet()); + mvOsOutput("\n"); + + for(i = 0; i < MV_DRAM_MAX_CS; i++) + { + sdramCsSize = mvDramIfBankSizeGet(i); + if (sdramCsSize) + { + if (0 == (i & 1)) + { + mvDramIfDimGetSPDversion(&Major, &Minor,i); + mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); + } + mvOsOutput("\tDRAM CS[%d] ", i); + mvSizePrint(sdramCsSize); + mvOsOutput("\n"); + } + } + sdramCasLat = mvDramIfCalGet(); + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) + { + mvOsOutput("ECC enabled, "); + } + else + { + mvOsOutput("ECC Disabled, "); + } + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) + { + mvOsOutput("Registered DIMM\n"); + } + else + { + mvOsOutput("Non registered DIMM\n"); + } + + mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); +} +/******************************************************************************* +* mvDramIfGetFirstCS - find the DRAM bank on the lower address +* +* +* DESCRIPTION: +* This function return the fisrt CS on address 0 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* SDRAM_CS0 or SDRAM_CS2 +* +*******************************************************************************/ +MV_U32 mvDramIfGetFirstCS(void) +{ + MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; + + if (DRAM_CS_Order[0] == N_A) + { + mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); +#ifdef MV_INCLUDE_SDRAM_CS2 + mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); +#endif + +#ifdef MV_INCLUDE_SDRAM_CS2 + if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) + { + DRAM_CS_Order[0] = SDRAM_CS2; + DRAM_CS_Order[1] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS0; + DRAM_CS_Order[3] = SDRAM_CS1; + + return SDRAM_CS2; + } +#endif + DRAM_CS_Order[0] = SDRAM_CS0; + DRAM_CS_Order[1] = SDRAM_CS1; +#ifdef MV_INCLUDE_SDRAM_CS2 + DRAM_CS_Order[2] = SDRAM_CS2; + DRAM_CS_Order[3] = SDRAM_CS3; +#endif + return SDRAM_CS0; + } + return DRAM_CS_Order[0]; +} +/******************************************************************************* +* mvDramIfGetCSorder - +* +* +* DESCRIPTION: +* This function return the fisrt CS on address 0 +* +* INPUT: +* CS number. +* +* OUTPUT: +* CS order. +* +* RETURN: +* SDRAM_CS0 or SDRAM_CS2 +* +* NOTE: mvDramIfGetFirstCS must be caled before this subroutine +*******************************************************************************/ +MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) +{ + return DRAM_CS_Order[csOrder]; +} + diff --git a/board/mv_feroceon/mv_hal/ddr2/mvDramIf.h b/board/mv_feroceon/mv_hal/ddr2/mvDramIf.h new file mode 100644 index 0000000..23f2e54 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr2/mvDramIf.h @@ -0,0 +1,172 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDramIfh +#define __INCmvDramIfh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ +#include "ddr2/mvDramIfRegs.h" +#include "ddr2/mvDramIfConfig.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +/* defines */ +/* DRAM Timing parameters */ +#define SDRAM_TWR 15 /* ns tWr */ +#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ +#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ +#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ +#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ + +#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ +#define ECC_DISABLE 1 /* Force ECC to Disable */ +#define ECC_ENABLE 0 /* Force ECC to ENABLE */ +/* typedefs */ + +/* enumeration for memory types */ +typedef enum _mvMemoryType +{ + MEM_TYPE_SDRAM, + MEM_TYPE_DDR1, + MEM_TYPE_DDR2 +}MV_MEMORY_TYPE; + +/* enumeration for DDR2 supported CAS Latencies */ +typedef enum _mvDimmDdr2Cas +{ + DDR2_CL_3 = 0x08, + DDR2_CL_4 = 0x10, + DDR2_CL_5 = 0x20, + DDR2_CL_6 = 0x40, + DDR2_CL_FAULT +} MV_DIMM_DDR2_CAS; + + +typedef struct _mvDramBankInfo +{ + MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY..*/ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ + MV_U32 numberOfDevices; + + /* DIMM attributes (MV_TRUE for yes) */ + MV_BOOL registeredAddrAndControlInputs; + MV_BOOL registeredDQMBinputs; + +}MV_DRAM_BANK_INFO; + +#include "ddr2/spd/mvSpd.h" + +/* mvDramIf.h API list */ +MV_VOID mvDramIfBasicAsmInit(MV_VOID); +MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); +MV_VOID _mvDramIfConfig(int entryNum); + +MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); +MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); +MV_U32 mvDramIfSizeGet(MV_VOID); +MV_U32 mvDramIfCalGet(void); +MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); +MV_VOID mvDramIfSelfRefreshSet(void); +void mvDramIfShow(void); +MV_U32 mvDramIfGetFirstCS(void); +MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); +MV_U32 mvDramCsSizeGet(MV_U32 csNum); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvDramIfh */ diff --git a/board/mv_feroceon/mv_hal/ddr2/mvDramIfBasicInit.S b/board/mv_feroceon/mv_hal/ddr2/mvDramIfBasicInit.S new file mode 100644 index 0000000..830830a --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr2/mvDramIfBasicInit.S @@ -0,0 +1,1042 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define _ASMLANGUAGE +#define MV_ASMLANGUAGE +#include "mvSysHwConfig.h" +#include "mvOsAsm.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "mvDramIfConfig.h" +#include "mvDramIfRegs.h" +#include "pex/mvPexRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvAsm.h" +#include "mvCommon.h" + +/* defines */ +#if defined(MV_STATIC_DRAM_ON_BOARD) +/****************************************************************************** +* static definitions for several dimms +*******************************************************************************/ +#if defined(DB_MV78XX0) || defined(MV78200) +#if defined(MV78100) +/* DDR2 boards 512MB 333MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ +#elif defined(MV78200) +/* 512MB per CD, 800Mhz cl5 */ +#define STATIC_DRAM_BANK_CS0 +#define STATIC_DRAM_BANK_CS2 + +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM1_BANK0_SIZE 0x1ffffff9 /* 0x1514 */ +#define STATIC_SDRAM1_BANK0_BASE 0x20000000 /* 0x1510 */ + + +#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ +#define STATIC_DUNIT_CTRL_LOW 0x37543010 /* 0x1404 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ + +#define STATIC_SDRAM_ADDR_CTRL 0x00008888 /* 0x1410 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ + +#define STATIC_SDRAM_EXT_MODE 0x00000044 /* 0x1420 */ +#define STATIC_DUNIT_CTRL_HI 0x0000FF7F /* 0x1424 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ + +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#define STATIC_SDRAM_ODT_CTRL_LOW 0x030C030C /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F40F /* 0x149c */ + +#endif +#elif defined(DB_MV88F632X) +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43040C30 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + + +#elif defined(RD_MV78XX0_AMC) +/* On board DDR2 512MB 400MHz CL5 */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#define STATIC_SDRAM1_BANK0_SIZE 0x0FFFFFF1 /* 0x1514 */ +#define STATIC_SDRAM1_BANK0_BASE 0x10000000 /* 0x1510 */ + +#elif defined(RD_MV78XX0_H3C) +/* DDR2 boards 512MB 333MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ + +#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#elif defined(RD_MV78XX0_PCAC) +/* DDR2 boards 256MB 200MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#else +/* DDR2 MV88F6281 boards 256MB 400MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ +#endif /* MV78XX0 */ + +#endif /* MV_STATIC_DRAM_ON_BOARD */ + +.globl dramBoot1 +dramBoot1: + .word 0 +/************************************************************* +* basic timing init +**************************************************************/ + .globl _mvDramInitTiming +_mvDramInitTiming: + /* Set Dunit high control register */ + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ + orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ +#ifdef MV78XX0 + orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ + orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ + orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ +#endif + MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) + orr r6, r6, #BIT4 /* Enable 2T mode */ + bic r6, r6, #BIT6 /* clear ctrlPos */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) +#endif + + + /*DDR SDRAM Initialization Control */ + ldr r6, =DSICR_INIT_EN + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + and r6, r6, #DSICR_INIT_EN + cmp r6, #0 + bne 2b + mov pc, lr + + +#if defined(MV_STATIC_DRAM_ON_BOARD) +/************************************************************* +* basic init for static DRAM (on board dram no SPD) +**************************************************************/ + + .globl _mvDramIfStaticInit +_mvDramIfStaticInit: + + mov r11, LR /* Save link register */ + mov r10, r2 + bl _mvDramInitTiming + + /* If we boot from NAND jump to DRAM address */ + mov r5, #1 + ldr r6, =dramBoot1 + str r5, [r6] /* We started executing from DRAM */ + + ldr r6, dramBoot1 + cmp r6, #0 + bne 1f + + /* set all dram windows to 0 */ + mov r6, #0 + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3)) + ldr r6, = STATIC_SDRAM0_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) + +#ifdef STATIC_DRAM_BANK_CS2 + ldr r6, = STATIC_SDRAM1_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) + ldr r6, = STATIC_SDRAM1_BANK0_BASE + MV_REG_WRITE_ASM(r6, r5, SDRAM_BASE_ADDR_REG (0,2)) +#endif + + + /* set all dram configuration in temp registers */ + ldr r6, = STATIC_SDRAM0_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) + ldr r6, = STATIC_SDRAM_CONFIG + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) + ldr r6, = STATIC_SDRAM_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) + ldr r6, = STATIC_DUNIT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) + ldr r6, = STATIC_SDRAM_ADDR_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) + ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) + ldr r6, = STATIC_SDRAM_TIME_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) + ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) + ldr r6, = STATIC_SDRAM_ODT_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) + ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) + ldr r6, = STATIC_SDRAM_EXT_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) + ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11) + ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12) +#ifndef MV_NAND_BOOT + ldr r6, = STATIC_DUNIT_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13) +#endif + + ldr sp,=0 + bl _mvDramIfConfig + ldr r0, =0 +#ifdef MV78XX0 + bl _mvDramIfEccMemInit +#ifdef STATIC_DRAM_BANK_CS2 + ldr r0, =2 + bl _mvDramIfEccMemInit +#endif + ldr r0, =0 +#endif +1: + mov r2, r10 + mov PC, r11 /* r11 is saved link register */ + +#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */ + +/******************************************************************************* +* mvDramIfBasicInit - Basic initialization of DRAM interface +* +* DESCRIPTION: +* The function will initialize the DRAM for basic usage. The function +* will use the TWSI assembly API to extract DIMM parameters according +* to which DRAM interface will be initialized. +* The function referes to the following DRAM parameters: +* 1) DIMM is registered or not. +* 2) DIMM width detection. +* 3) DIMM density. +* +* INPUT: +* r3 - required size for initial DRAM. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* Note: +* r4 holds I2C EEPROM address +* r5 holds SDRAM register base address +* r7 holds returned values +* r8 holds SDRAM various configuration registers value. +* r11 holds return function address. +*******************************************************************************/ +/* Setting the offsets of the I2C registers */ +#define DIMM_TYPE_OFFSET 2 +#define NUM_OF_ROWS_OFFSET 3 +#define NUM_OF_COLS_OFFSET 4 +#define NUM_OF_RANKS 5 +#define DIMM_CONFIG_TYPE 11 +#define SDRAM_WIDTH_OFFSET 13 +#define NUM_OF_BANKS_OFFSET 17 +#define SUPPORTED_CL_OFFSET 18 +#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ +#define SDRAM_MODULES_ATTR_OFFSET 21 +#define RANK_SIZE_OFFSET 31 + +#define DRAM_DEV_DENSITY_128M 128 +#define DRAM_DEV_DENSITY_256M 256 +#define DRAM_DEV_DENSITY_512M 512 +#define DRAM_DEV_DENSITY_1G 1024 +#define DRAM_DEV_DENSITY_2G 2048 + +#define DRAM_RANK_DENSITY_128M 0x20 +#define DRAM_RANK_DENSITY_256M 0x40 +#define DRAM_RANK_DENSITY_512M 0x80 +#define DRAM_RANK_DENSITY_1G 0x1 +#define DRAM_RANK_DENSITY_2G 0x2 + + .globl _mvDramIfBasicInit + .extern _i2cInit +_mvDramIfBasicInit: + + mov r11, LR /* Save link register */ + + bl _mvDramInitTiming + + mov r5, #1 + ldr r8, =dramBoot1 + str r5, [r8] /* We started executing from DRAM */ + + /* If we boot from NAND jump to DRAM address */ + ldr r8, dramBoot1 + cmp r8, #0 + movne pc, r11 + + bl _i2cInit /* Initialize TWSI master */ + + /* Check if we have more then 1 dimm */ + ldr r6, =0 + MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) +#ifdef MV78XX0 + bl _is_Second_Dimm_Exist + beq single_dimm + ldr r6, =1 + MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) +single_dimm: + bl _i2cInit /* Initialize TWSI master */ +#endif + + /* Get default SDRAM Config values */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + + /* Get registered/non registered info from DIMM */ + bl _is_Registered + beq nonRegistered + +setRegistered: + orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ +nonRegistered: +#if defined(MV78XX0) && !defined(MV632X) + /* Get ECC/non ECC info from DIMM */ + bl _is_Ecc + beq setConfigReg + +setEcc: + orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */ +#endif +setConfigReg: + MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1) + + /* Set maximum CL supported by DIMM */ + bl _get_CAL + + /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ + clz r6, r7 + rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ + +casDdr2: + ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x32 /* Assuming MAX CL = 3 */ + cmp r6, #3 /* If CL = 3 break */ + beq casDdr2Cont + + ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x42 /* Assuming MAX CL = 4 */ + cmp r6, #4 /* If CL = 4 break */ + beq casDdr2Cont + + ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x52 /* Assuming MAX CL = 5 */ + cmp r6, #5 /* If CL = 5 break */ + beq casDdr2Cont + + ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x62 /* Assuming MAX CL = 6 */ + cmp r6, #6 /* If CL = 5 break */ + beq casDdr2Cont + + /* This is an error. return */ + b exit_ddrAutoConfig /* This is an error !! */ +casDdr2Cont: + + /* Get default SDRAM Mode values */ + MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG) + bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */ + orr r6, r6, r8 + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2) + + /* Set Dunit control register according to max CL detected */ + MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1) + tst r6, #SDRAM_REGISTERED + beq setDunitReg + mov r7, r3 + +setDunitReg: +#ifdef MV78XX0 + /* Set SDRAM Extended Mode register for double DIMM */ + /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + ble Clock333 + add r7, r7, #0x10 +Clock333: +#endif + + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) + bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */ + orr r6, r6, #BIT4 /* Enable 2T mode */ + bic r6, r6, #BIT6 /* clear ctrlPos */ + orr r6, r6, r7, LSL #20 + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3) + + /* Set Dunit high control register */ + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ + orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ +#ifdef MV78XX0 + orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ + orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ + orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ +#endif + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13) + + /* DIMM density configuration*/ + /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ +Density: + /* Get bank 0 and 1 density */ + ldr r6, =0 + bl _getDensity + + mov r8, r7 + mov r8, r8, LSR #20 /* Move density 20 bits to the right */ + /* For example 0x10000000 --> 0x1000 */ + + mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1)) + cmp r8, #DRAM_DEV_DENSITY_256M + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1)) + cmp r8, #DRAM_DEV_DENSITY_512M + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1)) + cmp r8, #DRAM_DEV_DENSITY_1G + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1)) + cmp r8, #DRAM_DEV_DENSITY_2G + beq get_bank_2_density + + /* This is an error. return */ + b exit_ddrAutoConfig + +get_bank_2_density: + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne get_width + + /* Get bank 2 and 3 density */ + ldr r6, =2 + bl _getDensity + + mov r8, r7 + mov r8, r8, LSR #20 /* Move density 20 bits to the right */ + /* For example 0x10000000 --> 0x1000 */ + + orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3)) + cmp r8, #DRAM_DEV_DENSITY_256M + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3)) + cmp r8, #DRAM_DEV_DENSITY_512M + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3)) + cmp r8, #DRAM_DEV_DENSITY_1G + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3)) + cmp r8, #DRAM_DEV_DENSITY_2G + beq get_width + + /* This is an error. return */ + b exit_ddrAutoConfig + + /* Get SDRAM width */ +get_width: + /* Get bank 0 and 1 width */ + ldr r6, =0 + bl _get_width + + cmp r7, #8 /* x8 devices */ + beq get_bank_2_width + + orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */ + cmp r7, #16 + beq get_bank_2_width + + /* This is an error. return */ + b exit_ddrAutoConfig + +get_bank_2_width: + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne densCont + + /* Get bank 2 and 3 width */ + ldr r6, =2 + bl _get_width + + cmp r7, #8 /* x8 devices */ + beq densCont + + orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */ + cmp r7, #16 + beq densCont + + /* This is an error. return */ + b exit_ddrAutoConfig + +densCont: + MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4) + + /* Set SDRAM timing control low register */ + ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT + /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */ + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5) + + /* Set SDRAM timing control high register */ + ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + blt timingHighClock333 + orr r6, r6, #BIT9 + +timingHighClock333: + /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */ + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) + + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne single_dimm_odt + + /* Set SDRAM ODT control low register for double DIMM*/ + ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) + + /* Set DUNIT ODT control register for double DIMM */ + ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) + +#ifdef MV78XX0 + /* Set SDRAM Extended Mode register for double DIMM */ + /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_267 + cmp r4, r5 + beq slow_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_300 + cmp r4, r5 + beq slow_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + beq fast_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_400 + cmp r4, r5 + beq fast_dram_clock_rtt + + b slow_dram_clock_rtt + +fast_dram_clock_rtt: + ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + b odt_config_end +#endif +slow_dram_clock_rtt: + ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + b odt_config_end + +single_dimm_odt: + /* Set SDRAM ODT control low register */ + ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) + + /* Set DUNIT ODT control register */ + ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) + + /* Set SDRAM Extended Mode register */ + ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + +odt_config_end: + /* SDRAM ODT control high register is left as default */ + MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8) + + /*Read CL and set the DDR2 registers accordingly */ + MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2) + and r6, r6, #SDRAM_CL_MASK + mov r4, r6 + orr r4, r4, r6, LSL #4 + orr r4, r4, r6, LSL #8 + orr r4, r4, r6, LSL #12 + mov r5, #0x30000 + add r4, r4, r5 + sub r4, r4, #0x30 + /* Set SDRAM Ddr2 Timing Low register */ + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11) + + /* Set SDRAM Ddr2 Timing High register */ + mov r4, r4, LSR #4 + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12) + +timeParamDone: + /* Close all windows */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + + /* Set sdram bank 0 size and enable it */ + ldr r6, =0 + bl _mvDramIfGetDimmSizeFromSpd +#ifdef MV78XX0 + /* Check DRAM width */ + MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) + ldr r5, =SDRAM_DWIDTH_MASK + and r4, r4, r5 + ldr r5, =SDRAM_DWIDTH_64BIT + cmp r4, r5 + beq dram_64bit_width + /* Utilize only 32bit width */ + mov r8, r8, LSR #1 +#else + /* Utilize only 16bit width */ + mov r8, r8, LSR #2 +#endif +dram_64bit_width: + /* Update first dimm size return value R8 */ + MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0)) + ldr r6, =~SCSR_SIZE_MASK + and r5, r5, r6 + orr r5, r5, r8 + MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0)) + + /* Clear bank 2 size */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#~SCSR_SIZE_MASK + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne defualt_order + + /* Set sdram bank 2 size */ + ldr r6, =2 + bl _mvDramIfGetDimmSizeFromSpd +#ifdef MV78XX0 + /* Check DRAM width */ + MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) + ldr r5, =SDRAM_DWIDTH_MASK + and r4, r4, r5 + ldr r5, =SDRAM_DWIDTH_64BIT + cmp r4, r5 + beq dram_64bit_width2 + /* Utilize only 32bit width */ + mov r8, r8, LSR #1 +#else + /* Utilize only 16bit width */ + mov r8, r8, LSR #2 +#endif +dram_64bit_width2: + /* Update first dimm size return value R8 */ + MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2)) + ldr r6, =~SCSR_SIZE_MASK + and r5, r5, r6 + orr r5, r5, r8 + MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2)) + + /* Close windows 1 and 3 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + + /* Check dimm size for setting dram bank order */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#SCSR_SIZE_MASK + and r4, r4,#SCSR_SIZE_MASK + cmp r6, r4 + bge defualt_order + + /* Bank 2 is biger then bank 0 */ + ldr r6,=0 + MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2)) + + /* Open win 2 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + orr r6, r6,#1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + + ldr sp,=0 + bl _mvDramIfConfig +#ifdef MV78XX0 + /* Init ECC on CS 2 */ + ldr r0, =2 + bl _mvDramIfEccMemInit +#endif + mov PC, r11 /* r11 is saved link register */ + +defualt_order: + + /* Open win 0 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + orr r6, r6,#1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + + ldr sp,=0 + bl _mvDramIfConfig +#ifdef MV78XX0 + /* Init ECC on CS 0 */ + ldr r0, =0 + bl _mvDramIfEccMemInit +#endif +exit_ddrAutoConfig: + mov PC, r11 /* r11 is saved link register */ + + +/***************************************************************************************/ +/* r4 holds I2C EEPROM address + * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value + * r8 holds SDRAM various configuration registers value. + * r13 holds Link register + */ +/**************************/ +_getDensity: + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ + bl _i2cRead + mov r8, r7 /* r8 save number of rows */ + + mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ + bl _i2cRead + add r8, r8, r7 /* r8 = number of rows + number of col */ + + mov r7, #0x1 + mov r8, r7, LSL r8 /* r8 = (1 << r8) */ + + mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ + bl _i2cRead + mul r8, r7, r8 + + mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ + bl _i2cRead + mul r7, r8, r7 + + mov PC, r13 + +/**************************/ +_get_width: + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + /* Get SDRAM width (SPD offset 13) */ + mov r7, #SDRAM_WIDTH_OFFSET + bl _i2cRead /* result in r7 */ + + mov PC, r13 + +/**************************/ +_get_CAL: + mov r13, LR /* Save link register */ + + /* Set maximum CL supported by DIMM */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ + bl _i2cRead + + mov PC, r13 + +/**************************/ +/* R8 - sdram configuration register. + * Return value in flag if no-registered then Z-flag is set + */ +_is_Registered: + mov r13, LR /* Save link register */ +#if defined(MV645xx) + /* Get registered/non registered info from DIMM */ + tst r8, #SDRAM_DTYPE_DDR2 + bne regDdr2 + +regDdr1: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SDRAM_MODULES_ATTR_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x2 + b exit +#endif +regDdr2: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_TYPE_INFO_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ + /* or Mini-RDIMM (0x10) */ +exit: + mov PC, r13 + + +/**************************/ +/* Return value in flag if no-Ecc then Z-flag is set */ +_is_Ecc: + mov r13, LR /* Save link register */ + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_CONFIG_TYPE + bl _i2cRead /* result in r7 */ + + tst r7, #0x2 /* bit 1 -> Data ECC */ + mov PC, r13 + +/**************************/ +/* Return value in flag if no second DIMM then Z-flag is set */ +_is_Second_Dimm_Exist: + mov r13, LR /* Save link register */ + + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_TYPE_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x8 /* bit3 is '1' -> DDR 2 */ + mov PC, r13 + +/******************************************************************************* +* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size +* +* DESCRIPTION: +* The function will read the bank 0 dram size(SPD version 1.0 and above ) +* +* INPUT: +* r6 - dram bank number. +* +* OUTPUT: +* none +*/ +_mvDramIfGetDimmSizeFromSpd: + + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + mov r7, #RANK_SIZE_OFFSET /* offset 31 */ + bl _i2cRead + +pass_read: + ldr r8, =(0x7 << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_128M + beq endDimmSize + + ldr r8, =(0xf << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_256M + beq endDimmSize + + ldr r8, =(0x1f << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_512M + beq endDimmSize + + ldr r8, =(0x3f << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_1G + beq endDimmSize + + ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */ +endDimmSize: + mov PC, r13 +#endif diff --git a/board/mv_feroceon/mv_hal/ddr2/mvDramIfConfig.S b/board/mv_feroceon/mv_hal/ddr2/mvDramIfConfig.S new file mode 100644 index 0000000..fd01644 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr2/mvDramIfConfig.S @@ -0,0 +1,529 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvDramIfBasicAsm.s +* +* DESCRIPTION: +* Memory full detection and best timing configuration is done in +* C code. C runtime environment requires a stack. This module API +* initialize DRAM interface chip select 0 for basic functionality for +* the use of stack. +* The module API assumes DRAM information is stored in I2C EEPROM reside +* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM +* internal data structure is assumed to be orgenzied in common DRAM +* vendor SPD structure. +* NOTE: DFCDL values are assumed to be already initialized prior to +* this module API activity. +* +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#define _ASMLANGUAGE +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include "mvSysHwConfig.h" +#include "mvDramIfRegs.h" +#include "mvDramIfConfig.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "pex/mvPexRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvCommon.h" + +/* defines */ + +/* locals */ +.data +.globl _mvDramIfConfig +.text +.globl _mvDramIfMemInit + +/******************************************************************************* +* _mvDramIfConfig - Basic DRAM interface initialization. +* +* DESCRIPTION: +* The function will initialize the following DRAM parameters using the +* values prepared by mvDramIfDetect routine. Values are located +* in predefined registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ + +_mvDramIfConfig: + + /* Save register on stack */ + cmp sp, #0 + beq no_stack_s +save_on_stack: + stmdb sp!, {r1, r2, r3, r4} +no_stack_s: + + /* Dunit FTDLL Configuration Register */ + /* 0) Write to SDRAM FTDLL coniguration register */ + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG) + str r4, [r1] + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG) + str r4, [r1] + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG) + str r4, [r1] + + /* 1) Write to SDRAM coniguration register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) + str r4, [r1] + + /* 2) Write Dunit control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) + str r4, [r1] + + /* 2) Write Dunit control high register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG) + str r4, [r1] + + /* 3) Write SDRAM address control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) + str r4, [r1] +#if defined(MV_STATIC_DRAM_ON_BOARD) + /* 4) Write SDRAM bank 0 size register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0)) + str r4, [r1] +#endif + + /* 5) Write SDRAM open pages control register */ + ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) + ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV + str r4, [r1] + + /* 6) Write SDRAM timing Low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) + str r4, [r1] + + /* 7) Write SDRAM timing High register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) + str r4, [r1] + + /* Config DDR2 On Die Termination (ODT) registers */ + /* Write SDRAM DDR2 ODT control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) + str r4, [r1] + + /* Write SDRAM DDR2 ODT control high register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) + str r4, [r1] + + /* Write SDRAM DDR2 Dunit ODT control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) + str r4, [r1] + + /* Write DDR2 SDRAM timing Low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG) + str r4, [r1] + + /* Write DDR2 SDRAM timing High register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG) + str r4, [r1] + + /* 8) Write SDRAM mode register */ + /* The CPU must not attempt to change the SDRAM Mode register setting */ + /* prior to DRAM controller completion of the DRAM initialization */ + /* sequence. To guarantee this restriction, it is recommended that */ + /* the CPU sets the SDRAM Operation register to NOP command, performs */ + /* read polling until the register is back in Normal operation value, */ + /* and then sets SDRAM Mode register to its new value. */ + + /* 8.1 write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) + + /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll1: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll1 + + /* 8.3 Now its safe to write new value to SDRAM Mode register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) + str r4, [r1] + + /* 8.4 Make the Dunit write the DRAM its new mode */ + mov r4, #0x3 /* Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll2: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll2 + + /* Now its safe to write new value to SDRAM Extended Mode regist */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) + str r4, [r1] + + /* 9) Write SDRAM Extended mode register This operation should be */ + /* done for each memory bank */ + /* write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll3: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll3 + /* Go over each of the Banks */ + ldr r3, =0 /* r3 = DRAM bank Num */ + +extModeLoop: + /* Set the SDRAM Operation Control to each of the DRAM banks */ + mov r4, r3 /* Do not swap the bank counter value */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG) + + /* Make the Dunit write the DRAM its new mode */ + mov r4, #0x4 /* Extended Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll4: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll4 + + add r3, r3, #1 + cmp r3, #4 /* 4 = Number of banks */ + bne extModeLoop + +extModeEnd: +cmp sp, #0 + beq no_stack_l + mov r1, LR /* Save link register */ +#if defined(MV78XX0) + bl _mvDramIfMemInit +#endif + mov LR,r1 /* restore link register */ +load_from_stack: + /* Restore registers */ + ldmia sp!, {r1, r2, r3, r4} +no_stack_l: + + mov pc, lr + + +/******************************************************************************* +* _mvDramIfEccMemInit - Basic DRAM ECC initialization. +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */ +#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */ +#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */ +/* XOR engine register offsets macros */ +#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4)) +#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4)) +#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30) +#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50) +#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60) +#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0) +#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4) +#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4)) +#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4)) + +/* XOR Engine Address Decoding Register Map */ +#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) +#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) +#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) + +.globl _mvDramIfEccMemInit +/******************************************************************************* +* _mvDramIfEccMemInit - mem init for dram cs +* +* DESCRIPTION: +* This function will clean the cs by ussing the XOR mem init. +* +* INPUT: +* r0 - dram bank number. +* +* OUTPUT: +* none +*/ +_mvDramIfEccMemInit: + + /* Save register on stack */ + cmp sp, #0 + beq no_stack_s1 +save_on_stack1: + stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} +no_stack_s1: + + ldr r1, = 0 + + /* Disable all XOR address decode windows to avoid possible overlap */ + MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))) + + /* Init r5 to first XOR_SIZE_MASK_REG */ + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#0x04 + add r5, r5,#(INTER_REGS_BASE) + ldr r6, [r5] + HTOLL(r6,r5) + MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) + + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#(INTER_REGS_BASE) + ldr r6, [r5] + HTOLL(r6,r5) + /* Update destination & size */ + MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0)) + HTOLL(r6,r5) + /* Init r6 to first XOR_BASE_ADDR_REG */ + ldr r4, = 0xf + ldr r5, = 0x1 + mov r5, r5, LSL r0 + bic r4, r4, r5 + mov r4, r4, LSL #8 + + orr r6, r6, r4 + MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) + + ldr r6, = 0xff0001 + MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)) + + /* Configure XOR engine for memory init function. */ + MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) + and r6, r6, #~0x7 /* Clear operation mode field */ + orr r6, r6, #0x4 /* Set operation to memory init */ + MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) + + /* Set initVal in the XOR Engine Initial Value Registers */ + ldr r6, = 0xfeedfeed + MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG) + ldr r6, = 0xfeedfeed + MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG) + + /* Set block size using DRAM bank size */ + + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#0x04 + add r5, r5,#(INTER_REGS_BASE) + + ldr r6, [r5] + HTOLL(r6,r5) + and r6, r6, #SCSR_SIZE_MASK + mov r5, r6, LSR #SCSR_SIZE_OFFS + add r5, r5, #1 + mov r6, r5, LSL #SCSR_SIZE_OFFS + MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0)) + + /* Clean interrupt cause*/ + MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG) + + /* Clean error interrupt cause*/ + MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG) + MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG) + + /* Start transfer */ + MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) + orr r6, r6, #0x1 /* Preform start command */ + MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) + + /* Wait for engine to finish */ +waitForComplete: + MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG) + and r6, r6, #2 + cmp r6, #0 + beq waitForComplete + + /* Clear all error report registers */ + MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG) + MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG) + + MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG) + + cmp sp, #0 + beq no_stack_l1 +load_from_stack1: + ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} +no_stack_l1: + mov pc, lr + + +/******************************************************************************* +* mvDramIfMemInit - Use XOR to clear all memory. +* +* DESCRIPTION: +* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern. +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#if defined(MV78XX0) + +_mvDramIfMemInit: + stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} + mov r6, LR /* Save link register */ + /* Check if dram bank 0 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0)) + and r3, r0, #SCSR_WIN_EN + cmp r3, #0 + beq no_bank_0 + MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0)) + cmp r0, #0 + beq no_bank_0 + mov r0,#0 + bl _mvDramIfEccMemInit + +no_bank_0: + /* Check if dram bank 1 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_1 + mov r0,#1 + bl _mvDramIfEccMemInit +no_bank_1: + /* Check if dram bank 2 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_2 + MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2)) + cmp r0, #0 + beq no_bank_2 + mov r0,#2 + bl _mvDramIfEccMemInit + +no_bank_2: + /* Check if dram bank 3 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_3 + mov r0,#3 + bl _mvDramIfEccMemInit +no_bank_3: + mov LR ,r6 /* restore link register */ + ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} + mov pc, lr +#endif + diff --git a/board/mv_feroceon/mv_hal/ddr2/mvDramIfConfig.h b/board/mv_feroceon/mv_hal/ddr2/mvDramIfConfig.h new file mode 100644 index 0000000..6141c46 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr2/mvDramIfConfig.h @@ -0,0 +1,157 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDramIfConfigh +#define __INCmvDramIfConfigh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ + +/* defines */ + +/* registers defaults values */ + +#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) + +#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ + (SDRAM_SRCLK_KEPT | \ + SDRAM_CLK1DRV_NORMAL | \ + (BIT28 | BIT29)) + +#define SDRAM_ADDR_CTRL_DV 2 + +#define SDRAM_TIMING_CTRL_LOW_REG_DV \ + ((0x2 << SDRAM_TRCD_OFFS) | \ + (0x2 << SDRAM_TRP_OFFS) | \ + (0x1 << SDRAM_TWR_OFFS) | \ + (0x0 << SDRAM_TWTR_OFFS) | \ + (0x5 << SDRAM_TRAS_OFFS) | \ + (0x1 << SDRAM_TRRD_OFFS)) + +/* Note: value of 0 in register means one cycle, 1 means two and so on */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ + ((0x0 << SDRAM_TR2R_OFFS) | \ + (0x0 << SDRAM_TR2W_W2R_OFFS) | \ + (0x1 << SDRAM_TW2W_OFFS)) + +#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN + +/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ +/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ + +#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 +#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F +#ifdef MV78XX0 +#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 +#else +#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 +#endif + +#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C +#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F +#ifdef MV78XX0 +#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 +#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 +#else +#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 +#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 +#endif + +/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ +#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + +#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + +/* DDR SDRAM Mode Register default value */ +#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) +/* DDR SDRAM Timing parameter default values */ +#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 +#define SDRAM_TRFC_DEFAULT_VALUE 0x34 +#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE +#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) + +#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) + +#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 +#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 +#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvDramIfh */ diff --git a/board/mv_feroceon/mv_hal/ddr2/mvDramIfRegs.h b/board/mv_feroceon/mv_hal/ddr2/mvDramIfRegs.h new file mode 100644 index 0000000..369eda6 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr2/mvDramIfRegs.h @@ -0,0 +1,423 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDramIfRegsh +#define __INCmvDramIfRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* DDR SDRAM Controller Address Decode Registers */ + /* SDRAM CSn Base Address Register (SCBAR) */ +#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) +#define SCBAR_BASE_OFFS 16 +#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) +#define SCBAR_BASE_ALIGNMENT 0x10000 + +/* SDRAM CSn Size Register (SCSR) */ +#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) +#define SCSR_SIZE_OFFS 24 +#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) +#define SCSR_SIZE_ALIGNMENT 0x1000000 +#define SCSR_WIN_EN BIT0 + +/* configuration register */ +#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) +#define SDRAM_REFRESH_OFFS 0 +#define SDRAM_REFRESH_MAX 0x3FFF +#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) +#define SDRAM_DWIDTH_OFFS 15 +#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) +#define SDRAM_REGISTERED (1 << 17) +#define SDRAM_ECC_OFFS 18 +#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) +#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) +#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) +#define SDRAM_IERR_OFFS 19 +#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) +#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) +#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) +#define SDRAM_SRMODE_OFFS 24 +#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) +#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) +#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) + +/* dunit control low register */ +#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) +#define SDRAM_2T_OFFS 4 +#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) +#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) + +#define SDRAM_SRCLK_OFFS 5 +#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_CTRL_POS_OFFS 6 +#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CLK1DRV_OFFS 12 +#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK2DRV_OFFS 13 +#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_SB_OUT_DEL_OFFS 20 +#define SDRAM_SB_OUT_DEL_MAX 0xf +#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) + { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + memset(pBankInfo, 0, sizeof(*pBankInfo)); + + if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); + return MV_FAIL; + } + if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); + return MV_FAIL; + } + /* convert Dimm info to Bank info */ + cpyDimm2BankInfo(&dimmInfo, pBankInfo); + return MV_OK; +} + +/******************************************************************************* +* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. +* +* DESCRIPTION: +* Convert a Dimm info struct into a bank info struct. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* pBankInfo - DRAM bank information struct. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, + MV_DRAM_BANK_INFO *pBankInfo) +{ + pBankInfo->memoryType = pDimmInfo->memoryType; + + /* DIMM dimensions */ + pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; + pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; + pBankInfo->dataWidth = pDimmInfo->dataWidth; + pBankInfo->errorCheckType = pDimmInfo->errorCheckType; + pBankInfo->sdramWidth = pDimmInfo->sdramWidth; + pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; + pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; + pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; + pBankInfo->refreshInterval = pDimmInfo->refreshInterval; + + /* DIMM timing parameters */ + pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; + pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = + pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; + pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = + pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; + + pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; + pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; + pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; + pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; + pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; + pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; + pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; + pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; + + /* Parameters calculated from the extracted DIMM information */ + pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; + pBankInfo->deviceDensity = pDimmInfo->deviceDensity; + pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / + pDimmInfo->numOfModuleBanks; + + /* DIMM attributes (MV_TRUE for yes) */ + + if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || + (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) + { + if (pDimmInfo->dimmAttributes & BIT1) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } + else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ + { + if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } + + return; +} +/******************************************************************************* +* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. +* +* DESCRIPTION: +* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdCpy(MV_VOID) +{ + MV_U32 i; + MV_U32 spdChecksum; + + MV_TWSI_SLAVE twsiSlave; + MV_U8 data[SPD_SIZE]; + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) + { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); + return MV_FAIL; + } + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for(i = 0 ; i <= 62 ; i++) + { + spdChecksum += data[i]; + } + + if ((spdChecksum & 0xff) != data[63]) + { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32)(spdChecksum & 0xff), data[63])); + } + else + { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the DIMM 1 SPD */ + twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + for(i = 0 ; i < SPD_SIZE ; i++) + { + twsiSlave.offset = i; + if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) + { + mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); + return MV_FAIL; + } + mvOsDelay(5); + } + + DB(puts("DRAM: Reading dimm info succeded.\n")); + return MV_OK; +} + +/******************************************************************************* +* dimmSpdGet - Get the SPD parameters. +* +* DESCRIPTION: +* Read the DIMM SPD parameters into given struct parameter. +* +* INPUT: +* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. +* +* OUTPUT: +* pDimmInfo - DIMM information structure. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) +{ + MV_U32 i; + MV_U32 density = 1; + MV_U32 spdChecksum; + + MV_TWSI_SLAVE twsiSlave; + MV_U8 data[SPD_SIZE]; + + if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) + { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + twsiSlave.slaveAddr.address = (dimmNum == 0) ? + MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) + { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); + return MV_FAIL; + } + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for(i = 0 ; i <= 62 ; i++) + { + spdChecksum += data[i]; + } + + if ((spdChecksum & 0xff) != data[63]) + { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32)(spdChecksum & 0xff), data[63])); + } + else + { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the dimmInfo structure*/ + for(i = 0 ; i < SPD_SIZE ; i++) + { + pDimmInfo->spdRawData[i] = data[i]; + DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); + } + + DB(mvOsPrintf("DRAM SPD Information:\n")); + + /* Memory type (DDR / SDRAM) */ + switch (data[DIMM_MEM_TYPE]) + { + case (DIMM_MEM_TYPE_SDRAM): + pDimmInfo->memoryType = MEM_TYPE_SDRAM; + DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); + break; + case (DIMM_MEM_TYPE_DDR1): + pDimmInfo->memoryType = MEM_TYPE_DDR1; + DB(mvOsPrintf("DRAM Memeory type DDR1\n")); + break; + case (DIMM_MEM_TYPE_DDR2): + pDimmInfo->memoryType = MEM_TYPE_DDR2; + DB(mvOsPrintf("DRAM Memeory type DDR2\n")); + break; + default: + mvOsPrintf("ERROR: Undefined memory type!\n"); + return MV_ERROR; + } + + + /* Number Of Row Addresses */ + pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; + DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); + + /* Number Of Column Addresses */ + pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; + DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); + + /* Number Of Module Banks */ + pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", + pDimmInfo->numOfModuleBanks)); + + /* Number of module banks encoded differently for DDR2 */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) + pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; + + /* Data Width */ + pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; + DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); + + /* Minimum Cycle Time At Max CasLatancy */ + pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); + + /* Error Check Type */ + pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; + DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", + pDimmInfo->errorCheckType)); + + /* Refresh Interval */ + pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; + DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", + pDimmInfo->refreshInterval)); + + /* Sdram Width */ + pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; + DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); + + /* Error Check Data Width */ + pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; + DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", + pDimmInfo->errorCheckDataWidth)); + + /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + + pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; + DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", + pDimmInfo->burstLengthSupported)); + + /* Number Of Banks On Each Device */ + pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", + pDimmInfo->numOfBanksOnEachDevice)); + + /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; + DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", + pDimmInfo->suportedCasLatencies)); + + /* For DDR2 only, get the DIMM type information */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) + { + pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; + DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", + pDimmInfo->dimmTypeInfo)); + } + + /* SDRAM Modules Attributes */ + pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; + DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", + pDimmInfo->dimmAttributes)); + + /* Minimum Cycle Time At Max CasLatancy Minus 1*/ + pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = + cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); + + /* Minimum Cycle Time At Max CasLatancy Minus 2*/ + pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = + cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); + + pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; + DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", + pDimmInfo->minRowPrechargeTime)); + pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; + DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", + pDimmInfo->minRowActiveToRowActive)); + pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; + DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", + pDimmInfo->minRasToCasDelay)); + pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; + DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", + pDimmInfo->minRasPulseWidth)); + + /* DIMM Bank Density */ + pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; + DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", + pDimmInfo->dimmBankDensity)); + + /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ + pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; + DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", + pDimmInfo->minWriteRecoveryTime)); + + /* Only DDR2 includes Internal Write To Read Command Delay field. */ + pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; + DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", + pDimmInfo->minWriteToReadCmdDelay)); + + /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ + pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; + DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", + pDimmInfo->minReadToPrechCmdDelay)); + + /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ + pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; + DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", + pDimmInfo->minRefreshToActiveCmd)); + + /* calculating the sdram density. Representing device density from */ + /* bit 20 to allow representation of 4GB and above. */ + /* For example, if density is 512Mbit 0x20000000, will be represent in */ + /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ + /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ + density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); + pDimmInfo->deviceDensity = density * + pDimmInfo->numOfBanksOnEachDevice * + pDimmInfo->sdramWidth; + DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); + + /* Number of devices includeing Error correction */ + pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * + pDimmInfo->numOfModuleBanks; + DB(mvOsPrintf("DRAM numberOfDevices %d\n", + pDimmInfo->numberOfDevices)); + + pDimmInfo->size = 0; + + /* Note that pDimmInfo->size is in MB units */ + if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 8; /* Equal to 8MB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 4096; /* Equal to 4GB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 8192; /* Equal to 8GB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 16384; /* Equal to 16GB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + + pDimmInfo->size *= pDimmInfo->numOfModuleBanks; + + DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); + + return MV_OK; +} + +/******************************************************************************* +* dimmSpdPrint - Print the SPD parameters. +* +* DESCRIPTION: +* Print the Dimm SPD parameters. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID dimmSpdPrint(MV_U32 dimmNum) +{ + MV_DIMM_INFO dimmInfo; + MV_U32 i, temp = 0; + MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; + MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; + MV_U32 busClkPs; + MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, + temp_buf[40], *spdRawData; + + busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ + + spdRawData = dimmInfo.spdRawData; + + if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) + { + mvOsOutput("ERROR: Could not read SPD information!\n"); + return; + } + + /* find Manufactura of Dimm Module */ + mvOsOutput("\nManufacturer's JEDEC ID Code: "); + for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) + { + mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); + } + mvOsOutput("\n"); + + /* Manufacturer's Specific Data */ + for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) + { + temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; + } + mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); + + /* Module Part Number */ + for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) + { + temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; + } + mvOsOutput("Module Part Number: %s\n", temp_buf); + + /* Module Serial Number */ + for(i = 0; i < sizeof(MV_U32); i++) + { + temp |= spdRawData[95+i] << 8*i; + } + mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, + (long)temp); + + /* find Manufac-Data of Dimm Module */ + mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", + ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), + ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); + /* find modul_revision of Dimm Module */ + mvOsOutput("Module Revision: %d.%d\n", + spdRawData[62]/10, spdRawData[62]%10); + + /* find manufac_place of Dimm Module */ + mvOsOutput("manufac_place: %d\n", spdRawData[72]); + + /* go over the first 35 I2C data bytes */ + for(i = 2 ; i <= 35 ; i++) + switch(i) + { + case 2: /* Memory type (DDR1/2 / SDRAM) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + mvOsOutput("Dram Type is: SDRAM\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + mvOsOutput("Dram Type is: SDRAM DDR1\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + mvOsOutput("Dram Type is: SDRAM DDR2\n"); + else + mvOsOutput("Dram Type unknown\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 3: /* Number Of Row Addresses */ + mvOsOutput("Module Number of row addresses: %d\n", + dimmInfo.numOfRowAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 4: /* Number Of Column Addresses */ + mvOsOutput("Module Number of col addresses: %d\n", + dimmInfo.numOfColAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 5: /* Number Of Module Banks */ + mvOsOutput("Number of Banks on Mod.: %d\n", + dimmInfo.numOfModuleBanks); + break; +/*----------------------------------------------------------------------------*/ + + case 6: /* Data Width */ + mvOsOutput("Module Data Width: %d bit\n", + dimmInfo.dataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 8: /* Voltage Interface */ + switch(spdRawData[i]) + { + case 0x0: + mvOsOutput("Module is TTL_5V_TOLERANT\n"); + break; + case 0x1: + mvOsOutput("Module is LVTTL\n"); + break; + case 0x2: + mvOsOutput("Module is HSTL_1_5V\n"); + break; + case 0x3: + mvOsOutput("Module is SSTL_3_3V\n"); + break; + case 0x4: + mvOsOutput("Module is SSTL_2_5V\n"); + break; + case 0x5: + if (dimmInfo.memoryType != MEM_TYPE_SDRAM) + { + mvOsOutput("Module is SSTL_1_8V\n"); + break; + } + default: + mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); + break; + } + break; +/*----------------------------------------------------------------------------*/ + + case 9: /* Minimum Cycle Time At Max CasLatancy */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 10: /* Clock To Data Out */ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 11: /* Error Check Type */ + mvOsOutput("Error Check Type (0=NONE): %d\n", + dimmInfo.errorCheckType); + break; +/*----------------------------------------------------------------------------*/ + + case 12: /* Refresh Interval */ + mvOsOutput("Refresh Rate: %x\n", + dimmInfo.refreshInterval); + break; +/*----------------------------------------------------------------------------*/ + + case 13: /* Sdram Width */ + mvOsOutput("Sdram Width: %d bits\n", + dimmInfo.sdramWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 14: /* Error Check Data Width */ + mvOsOutput("Error Check Data Width: %d bits\n", + dimmInfo.errorCheckDataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 15: /* Minimum Clock Delay is unsupported */ + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || + (dimmInfo.memoryType == MEM_TYPE_DDR1)) + { + mvOsOutput("Minimum Clk Delay back to back: %d\n", + spdRawData[i]); + } + break; +/*----------------------------------------------------------------------------*/ + + case 16: /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + mvOsOutput("Burst Length Supported: "); + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || + (dimmInfo.memoryType == MEM_TYPE_DDR1)) + { + if (dimmInfo.burstLengthSupported & BIT0) + mvOsOutput("1, "); + if (dimmInfo.burstLengthSupported & BIT1) + mvOsOutput("2, "); + } + if (dimmInfo.burstLengthSupported & BIT2) + mvOsOutput("4, "); + if (dimmInfo.burstLengthSupported & BIT3) + mvOsOutput("8, "); + + mvOsOutput(" Bit \n"); + break; +/*----------------------------------------------------------------------------*/ + + case 17: /* Number Of Banks On Each Device */ + mvOsOutput("Number Of Banks On Each Chip: %d\n", + dimmInfo.numOfBanksOnEachDevice); + break; +/*----------------------------------------------------------------------------*/ + + case 18: /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + mvOsOutput("Suported Cas Latencies: (CL) "); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + for (k = 0; k <=7; k++) + { + if (dimmInfo.suportedCasLatencies & (1 << k)) + mvOsOutput("%d, ", k+1); + } + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.suportedCasLatencies & BIT0) + mvOsOutput("1, "); + if (dimmInfo.suportedCasLatencies & BIT1) + mvOsOutput("1.5, "); + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("2.5, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("3.5, "); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("4, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("5, "); + } + else + mvOsOutput("?.?, "); + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 20: /* DDR2 DIMM type info */ + if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) + mvOsOutput("Registered DIMM (RDIMM)\n"); + else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) + mvOsOutput("Unbuffered DIMM (UDIMM)\n"); + else + mvOsOutput("Unknown DIMM type.\n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 21: /* SDRAM Modules Attributes */ + mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" Bufferd DQMB Input: Yes \n"); + else + mvOsOutput(" Bufferd DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" Registered DQMB Inputs: Yes \n"); + else + mvOsOutput(" Registered DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" redundant Row Addressing: Yes \n"); + else + mvOsOutput(" redundant Row Addressing: No \n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); + else + mvOsOutput(" FET Switch On-Card Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + mvOsOutput(" Number of Active Registers on the DIMM: %d\n", + (dimmInfo.dimmAttributes & 0x3) + 1); + + mvOsOutput(" Number of PLLs on the DIMM: %d\n", + ((dimmInfo.dimmAttributes) >> 2) & 0x3); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" Analysis probe installed: Yes \n"); + else + mvOsOutput(" Analysis probe installed: No \n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 22: /* Suported AutoPreCharge */ + mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Early Ras Precharge: Yes \n"); + else + mvOsOutput(" Early Ras Precharge: No \n"); + + if ( spdRawData[i] & BIT1 ) + mvOsOutput(" AutoPreCharge: Yes \n"); + else + mvOsOutput(" AutoPreCharge: No \n"); + + if ( spdRawData[i] & BIT2 ) + mvOsOutput(" Precharge All: Yes \n"); + else + mvOsOutput(" Precharge All: No \n"); + + if ( spdRawData[i] & BIT3 ) + mvOsOutput(" Write 1/ReadBurst: Yes \n"); + else + mvOsOutput(" Write 1/ReadBurst: No \n"); + + if ( spdRawData[i] & BIT4 ) + mvOsOutput(" lower VCC tolerance: 5%%\n"); + else + mvOsOutput(" lower VCC tolerance: 10%%\n"); + + if ( spdRawData[i] & BIT5 ) + mvOsOutput(" upper VCC tolerance: 5%%\n"); + else + mvOsOutput(" upper VCC tolerance: 10%%\n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + + if ( !(spdRawData[i] & BIT4) ) + mvOsOutput(" lower VCC tolerance: 0.2V\n"); + + if ( !(spdRawData[i] & BIT5) ) + mvOsOutput(" upper VCC tolerance: 0.2V\n"); + + if ( spdRawData[i] & BIT6 ) + mvOsOutput(" Concurrent Auto Preharge: Yes \n"); + else + mvOsOutput(" Concurrent Auto Preharge: No \n"); + + if ( spdRawData[i] & BIT7 ) + mvOsOutput(" Supports Fast AP: Yes \n"); + else + mvOsOutput(" Supports Fast AP: No \n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + } + break; +/*----------------------------------------------------------------------------*/ + + case 23: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + + mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 25: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } + else /* DDR1 or DDR2 */ + { + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + } + mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = 0; + rightOfPoint = time_tmp; + } + mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 27: /* Minimum Row Precharge Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ + trp_clocks = (temp + (busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " + "in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 28: /* Minimum Row Active to Row Active Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ + trrd_clocks = (temp + (busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " + "%d.%d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 29: /* Minimum Ras-To-Cas Delay */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ + trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; + mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " + "in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 30: /* Minimum Ras Pulse Width */ + tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " + "in Clk cycles %d\n", spdRawData[i], tras_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 31: /* Module Bank Density */ + mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("8MB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("4GB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("8GB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("16GB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 32: /* Address And Command Setup Time (measured in ns/1000) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 33: /* Address And Command Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 34: /* Data Input Setup Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 35: /* Data Input Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 36: /* Relevant for DDR2 only: Write Recovery Time */ + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); + rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; + mvOsOutput("Write Recovery Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + } + +} + + +/* + * translate ns.ns/10 coding of SPD timing values + * into ps unit values + */ +/******************************************************************************* +* cas2ps - Translate x.y ns parameter to pico-seconds values +* +* DESCRIPTION: +* This function translates x.y nano seconds to its value in pico seconds. +* For example 3.75ns will return 3750. +* +* INPUT: +* spd_byte - DIMM SPD byte. +* +* OUTPUT: +* None. +* +* RETURN: +* value in pico seconds. +* +*******************************************************************************/ +static MV_U32 cas2ps(MV_U8 spd_byte) +{ + MV_U32 ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + if( ns10 < 10 ) { + ns10 *= 10; + } + else if( ns10 == 10 ) + ns10 = 25; + else if( ns10 == 11 ) + ns10 = 33; + else if( ns10 == 12 ) + ns10 = 66; + else if( ns10 == 13 ) + ns10 = 75; + else + { + mvOsOutput("cas2ps Err. unsupported cycle time.\n"); + } + + return (ns*1000 + ns10*10); +} + diff --git a/board/mv_feroceon/mv_hal/ddr2/spd/mvSpd.h b/board/mv_feroceon/mv_hal/ddr2/spd/mvSpd.h new file mode 100644 index 0000000..f955466 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ddr2/spd/mvSpd.h @@ -0,0 +1,192 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDram +#define __INCmvDram + +#include "ddr2/mvDramIf.h" +#include "twsi/mvTwsi.h" + +#define MAX_DIMM_NUM 2 +#define SPD_SIZE 128 + +/* Dimm spd offsets */ +#define DIMM_MEM_TYPE 2 +#define DIMM_ROW_NUM 3 +#define DIMM_COL_NUM 4 +#define DIMM_MODULE_BANK_NUM 5 +#define DIMM_DATA_WIDTH 6 +#define DIMM_VOLT_IF 8 +#define DIMM_MIN_CC_AT_MAX_CAS 9 +#define DIMM_ERR_CHECK_TYPE 11 +#define DIMM_REFRESH_INTERVAL 12 +#define DIMM_SDRAM_WIDTH 13 +#define DIMM_ERR_CHECK_DATA_WIDTH 14 +#define DIMM_MIN_CLK_DEL 15 +#define DIMM_BURST_LEN_SUP 16 +#define DIMM_DEV_BANK_NUM 17 +#define DIMM_SUP_CAL 18 +#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ +#define DIMM_BUF_ADDR_CONT_IN 21 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 +#define DIMM_MIN_ROW_PRECHARGE_TIME 27 +#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 +#define DIMM_MIN_RAS_TO_CAS_DELAY 29 +#define DIMM_MIN_RAS_PULSE_WIDTH 30 +#define DIMM_BANK_DENSITY 31 +#define DIMM_MIN_WRITE_RECOVERY_TIME 36 +#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 +#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 +#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 +#define DIMM_SPD_VERSION 62 + +/* Dimm Memory Type values */ +#define DIMM_MEM_TYPE_SDRAM 0x4 +#define DIMM_MEM_TYPE_DDR1 0x7 +#define DIMM_MEM_TYPE_DDR2 0x8 + +#define DIMM_MODULE_MANU_OFFS 64 +#define DIMM_MODULE_MANU_SIZE 8 +#define DIMM_MODULE_VEN_OFFS 73 +#define DIMM_MODULE_VEN_SIZE 25 +#define DIMM_MODULE_ID_OFFS 99 +#define DIMM_MODULE_ID_SIZE 18 + +/* enumeration for voltage levels. */ +typedef enum _mvDimmVoltageIf +{ + TTL_5V_TOLERANT, + LVTTL, + HSTL_1_5V, + SSTL_3_3V, + SSTL_2_5V, + VOLTAGE_UNKNOWN, +} MV_DIMM_VOLTAGE_IF; + + +/* enumaration for SDRAM CAS Latencies. */ +typedef enum _mvDimmSdramCas +{ + SD_CL_1 =1, + SD_CL_2, + SD_CL_3, + SD_CL_4, + SD_CL_5, + SD_CL_6, + SD_CL_7, + SD_FAULT +}MV_DIMM_SDRAM_CAS; + + +/* DIMM information structure */ +typedef struct _mvDimmInfo +{ + MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ + + MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 numOfModuleBanks; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY..*/ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + MV_U32 dimmBankDensity; + MV_U32 dimmTypeInfo; /* DDR2 only */ + MV_U32 dimmAttributes; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ + MV_U32 numberOfDevices; + +} MV_DIMM_INFO; + + +MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); +MV_VOID dimmSpdPrint(MV_U32 dimmNum); +MV_STATUS dimmSpdCpy(MV_VOID); + +#endif /* __INCmvDram */ diff --git a/board/mv_feroceon/mv_hal/eth-phy/mvCompVer.txt b/board/mv_feroceon/mv_hal/eth-phy/mvCompVer.txt new file mode 100644 index 0000000..c6e1229 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth-phy/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_2 +Unit HAL Version: 3.1.0 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/eth-phy/mvEthPhy.c b/board/mv_feroceon/mv_hal/eth-phy/mvEthPhy.c new file mode 100644 index 0000000..b2a3ae5 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth-phy/mvEthPhy.c @@ -0,0 +1,1295 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "eth-phy/mvEthPhy.h" +#include "eth/gbe/mvEthRegs.h" +#include "boardEnv/mvBoardEnvLib.h" + +static MV_VOID mvEthPhyPower(MV_U32 ethPortNum, MV_BOOL enable); +void rdPhy(MV_U32 phyAddr, MV_U32 regOffs); + + +void rdPhy(MV_U32 phyAddr, MV_U32 regOffs) +{ + MV_U16 data; + MV_STATUS status; + + status = mvEthPhyRegRead(phyAddr, regOffs, &data); + if(status == MV_OK) + mvOsPrintf("reg=%d: 0x%04x\n", regOffs, data); + else + mvOsPrintf("Read failed\n"); +} + + +/******************************************************************************* +* mvEthPhyRegRead - Read from ethernet phy register. +* +* DESCRIPTION: +* This function reads ethernet phy register. +* +* INPUT: +* phyAddr - Phy address. +* regOffs - Phy register offset. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit phy register value, or 0xffff on error +* +*******************************************************************************/ +MV_STATUS mvEthPhyRegRead(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 *data) +{ + MV_U32 smiReg; + volatile MV_U32 timeout; + + /* check parameters */ + if ((phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) & ~ETH_PHY_SMI_DEV_ADDR_MASK) + { + mvOsPrintf("mvEthPhyRegRead: Err. Illegal PHY device address %d\n", + phyAddr); + return MV_FAIL; + } + if ((regOffs << ETH_PHY_SMI_REG_ADDR_OFFS) & ~ETH_PHY_SMI_REG_ADDR_MASK) + { + mvOsPrintf("mvEthPhyRegRead: Err. Illegal PHY register offset %d\n", + regOffs); + return MV_FAIL; + } + + timeout = ETH_PHY_TIMEOUT; + /* wait till the SMI is not busy*/ + do + { + /* read smi register */ + smiReg = MV_REG_READ(ETH_PHY_SMI_REG); + if (timeout-- == 0) + { + mvOsPrintf("mvEthPhyRegRead: SMI busy timeout\n"); + return MV_FAIL; + } + }while (smiReg & ETH_PHY_SMI_BUSY_MASK); + + /* fill the phy address and regiser offset and read opcode */ + smiReg = (phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) | (regOffs << ETH_PHY_SMI_REG_ADDR_OFFS )| + ETH_PHY_SMI_OPCODE_READ; + + /* write the smi register */ + MV_REG_WRITE(ETH_PHY_SMI_REG, smiReg); + + timeout=ETH_PHY_TIMEOUT; + + /*wait till readed value is ready */ + do + { + /* read smi register */ + smiReg=MV_REG_READ(ETH_PHY_SMI_REG); + + if (timeout-- == 0) { + mvOsPrintf("mvEthPhyRegRead: SMI read-valid timeout\n"); + return MV_FAIL; + } + }while (!(smiReg & ETH_PHY_SMI_READ_VALID_MASK)); + + /* Wait for the data to update in the SMI register */ + for(timeout = 0 ; timeout < ETH_PHY_TIMEOUT ; timeout++); + + *data = (MV_U16)( MV_REG_READ(ETH_PHY_SMI_REG) & ETH_PHY_SMI_DATA_MASK); + + return MV_OK; +} + +/******************************************************************************* +* mvEthPhyRegWrite - Write to ethernet phy register. +* +* DESCRIPTION: +* This function write to ethernet phy register. +* +* INPUT: +* phyAddr - Phy address. +* regOffs - Phy register offset. +* data - 16bit data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if write succeed, MV_BAD_PARAM on bad parameters , MV_ERROR on error . +* MV_TIMEOUT on timeout +* +*******************************************************************************/ +MV_STATUS mvEthPhyRegWrite(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 data) +{ + MV_U32 smiReg; + volatile MV_U32 timeout; + + /* check parameters */ + if ((phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) & ~ETH_PHY_SMI_DEV_ADDR_MASK) + { + mvOsPrintf("mvEthPhyRegWrite: Err. Illegal phy address \n"); + return MV_BAD_PARAM; + } + if ((regOffs << ETH_PHY_SMI_REG_ADDR_OFFS) & ~ETH_PHY_SMI_REG_ADDR_MASK) + { + mvOsPrintf("mvEthPhyRegWrite: Err. Illegal register offset \n"); + return MV_BAD_PARAM; + } + + timeout=ETH_PHY_TIMEOUT; + + /* wait till the SMI is not busy*/ + do + { + /* read smi register */ + smiReg=MV_REG_READ(ETH_PHY_SMI_REG); + if (timeout-- == 0) { + mvOsPrintf("mvEthPhyRegWrite: SMI busy timeout\n"); + return MV_TIMEOUT; + } + }while (smiReg & ETH_PHY_SMI_BUSY_MASK); + + /* fill the phy address and regiser offset and write opcode and data*/ + smiReg = (data << ETH_PHY_SMI_DATA_OFFS); + smiReg |= (phyAddr << ETH_PHY_SMI_DEV_ADDR_OFFS) | (regOffs << ETH_PHY_SMI_REG_ADDR_OFFS ); + smiReg &= ~ETH_PHY_SMI_OPCODE_READ; + + /* write the smi register */ + MV_REG_WRITE(ETH_PHY_SMI_REG, smiReg); + + return MV_OK; + + +} + +/******************************************************************************* +* mvEthPhyReset - Reset ethernet Phy. +* +* DESCRIPTION: +* This function resets a given ethernet Phy. +* +* INPUT: +* phyAddr - Phy address. +* timeout - in millisec +* +* OUTPUT: +* None. +* +* RETURN: MV_OK - Success +* MV_TIMEOUT - Timeout +* +*******************************************************************************/ +MV_STATUS mvEthPhyReset(MV_U32 phyAddr, int timeout) +{ + MV_U16 phyRegData; + + /* Reset the PHY */ + if(mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK) + return MV_FAIL; + + /* Set bit 15 to reset the PHY */ + phyRegData |= ETH_PHY_CTRL_RESET_MASK; + mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData); + + /* Wait untill Reset completed */ + while(timeout > 0) + { + mvOsSleep(100); + timeout -= 100; + + if( mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK) + return MV_FAIL; + + if( (phyRegData & ETH_PHY_CTRL_RESET_MASK) == 0) + return MV_OK; + } + return MV_TIMEOUT; +} + + +/******************************************************************************* +* mvEthPhyRestartAN - Restart ethernet Phy Auto-Negotiation. +* +* DESCRIPTION: +* This function resets a given ethernet Phy. +* +* INPUT: +* phyAddr - Phy address. +* timeout - in millisec; 0 - no timeout (don't wait) +* +* OUTPUT: +* None. +* +* RETURN: MV_OK - Success +* MV_TIMEOUT - Timeout +* +*******************************************************************************/ +MV_STATUS mvEthPhyRestartAN(MV_U32 phyAddr, int timeout) +{ + MV_U16 phyRegData; + + /* Reset the PHY */ + if(mvEthPhyRegRead (phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK) + return MV_FAIL; + + /* Set bit 12 to Enable autonegotiation of the PHY */ + phyRegData |= ETH_PHY_CTRL_AN_ENABLE_MASK; + + /* Set bit 9 to Restart autonegotiation of the PHY */ + phyRegData |= ETH_PHY_CTRL_AN_RESTART_MASK; + mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData); + + if (timeout == 0) + return MV_OK; + + /* Wait untill Auotonegotiation completed */ + while(timeout > 0) + { + mvOsSleep(100); + timeout -= 100; + + if( mvEthPhyRegRead(phyAddr, ETH_PHY_STATUS_REG, &phyRegData) != MV_OK) + return MV_FAIL; + + if(phyRegData & ETH_PHY_STATUS_AN_DONE_MASK) + return MV_OK; + } + return MV_TIMEOUT; +} + + +/******************************************************************************* +* mvEthPhyDisableAN - Disable Phy Auto-Negotiation and set forced Speed and Duplex +* +* DESCRIPTION: +* This function disable AN and set duplex and speed. +* +* INPUT: +* phyAddr - Phy address. +* speed - port speed. 0 - 10 Mbps, 1-100 Mbps, 2 - 1000 Mbps +* duplex - port duplex. 0 - Half duplex, 1 - Full duplex +* +* OUTPUT: +* None. +* +* RETURN: MV_OK - Success +* MV_FAIL - Failure +* +*******************************************************************************/ +MV_STATUS mvEthPhyDisableAN(MV_U32 phyAddr, int speed, int duplex) +{ + MV_U16 phyRegData; + + if(mvEthPhyRegRead (phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK) + return MV_FAIL; + + switch(speed) + { + case 0: /* 10 Mbps */ + phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK; + phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK; + break; + + case 1: /* 100 Mbps */ + phyRegData |= ETH_PHY_CTRL_SPEED_LSB_MASK; + phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK; + break; + + case 2: /* 1000 Mbps */ + phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK; + phyRegData |= ETH_PHY_CTRL_SPEED_MSB_MASK; + break; + + default: + mvOsOutput("Unexpected speed = %d\n", speed); + return MV_FAIL; + } + + switch(duplex) + { + case 0: /* half duplex */ + phyRegData &= ~ETH_PHY_CTRL_DUPLEX_MASK; + break; + + case 1: /* full duplex */ + phyRegData |= ETH_PHY_CTRL_DUPLEX_MASK; + break; + + default: + mvOsOutput("Unexpected duplex = %d\n", duplex); + } + /* Clear bit 12 to Disable autonegotiation of the PHY */ + phyRegData &= ~ETH_PHY_CTRL_AN_ENABLE_MASK; + + /* Clear bit 9 to DISABLE, Restart autonegotiation of the PHY */ + phyRegData &= ~ETH_PHY_CTRL_AN_RESTART_MASK; + mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData); + + return MV_OK; +} + +MV_STATUS mvEthPhyLoopback(MV_U32 phyAddr, MV_BOOL isEnable) +{ + MV_U16 regVal, ctrlVal; + MV_STATUS status; + + /* Set loopback speed and duplex accordingly with current */ + /* Bits: 6, 8, 13 */ + if(mvEthPhyRegRead (phyAddr, ETH_PHY_CTRL_REG, &ctrlVal) != MV_OK) + return MV_FAIL; + + if(isEnable) + { + /* Select page 2 */ + mvEthPhyRegWrite(phyAddr, 22, 2); + + mvEthPhyRegRead (phyAddr, 21, ®Val); + regVal &= ~(ETH_PHY_CTRL_DUPLEX_MASK | ETH_PHY_CTRL_SPEED_LSB_MASK | + ETH_PHY_CTRL_SPEED_MSB_MASK | ETH_PHY_CTRL_AN_ENABLE_MASK); + regVal |= (ctrlVal & (ETH_PHY_CTRL_DUPLEX_MASK | ETH_PHY_CTRL_SPEED_LSB_MASK | + ETH_PHY_CTRL_SPEED_MSB_MASK | ETH_PHY_CTRL_AN_ENABLE_MASK) ); + mvEthPhyRegWrite(phyAddr, 21, regVal); + + /* Select page 0 */ + mvEthPhyRegWrite(phyAddr, 22, 0); + + /* Disable Energy detection R16[9:8] = 00 */ + /* Disable MDI/MDIX crossover R16[6:5] = 00 */ + mvEthPhyRegRead (phyAddr, ETH_PHY_SPEC_CTRL_REG, ®Val); + regVal &= ~(BIT5 | BIT6 | BIT8 | BIT9); + mvEthPhyRegWrite (phyAddr, ETH_PHY_SPEC_CTRL_REG, regVal); + + status = mvEthPhyReset(phyAddr, 1000); + if(status != MV_OK) + { + mvOsPrintf("mvEthPhyReset failed: status=0x%x\n", status); + return status; + } + + /* Set loopback */ + ctrlVal |= ETH_PHY_CTRL_LOOPBACK_MASK; + mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, ctrlVal); + } + else + { + /* Cancel Loopback */ + ctrlVal &= ~ETH_PHY_CTRL_LOOPBACK_MASK; + mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, ctrlVal); + + status = mvEthPhyReset(phyAddr, 1000); + if(status != MV_OK) + { + mvOsPrintf("mvEthPhyReset failed: status=0x%x\n", status); + return status; + } + + /* Enable Energy detection R16[9:8] = 11 */ + /* Enable MDI/MDIX crossover R16[6:5] = 11 */ + mvEthPhyRegRead (phyAddr, ETH_PHY_SPEC_CTRL_REG, ®Val); + regVal |= (BIT5 | BIT6 | BIT8 | BIT9); + mvEthPhyRegWrite (phyAddr, ETH_PHY_SPEC_CTRL_REG, regVal); + + status = mvEthPhyReset(phyAddr, 1000); + if(status != MV_OK) + { + mvOsPrintf("mvEthPhyReset failed: status=0x%x\n", status); + return status; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvEthPhyCheckLink - +* +* DESCRIPTION: +* check link in phy port +* +* INPUT: +* phyAddr - Phy address. +* +* OUTPUT: +* None. +* +* RETURN: MV_TRUE if link is up, MV_FALSE if down +* +*******************************************************************************/ +MV_BOOL mvEthPhyCheckLink( MV_U32 phyAddr ) +{ + MV_U16 val_st, val_ctrl, val_spec_st; + + /* read status reg */ + if( mvEthPhyRegRead( phyAddr, ETH_PHY_STATUS_REG, &val_st) != MV_OK ) + return MV_FALSE; + + /* read control reg */ + if( mvEthPhyRegRead( phyAddr, ETH_PHY_CTRL_REG, &val_ctrl) != MV_OK ) + return MV_FALSE; + + /* read special status reg */ + if( mvEthPhyRegRead( phyAddr, ETH_PHY_SPEC_STATUS_REG, &val_spec_st) != MV_OK ) + return MV_FALSE; + + /* Check for PHY exist */ + if((val_ctrl == ETH_PHY_SMI_DATA_MASK) && (val_st & ETH_PHY_SMI_DATA_MASK)) + return MV_FALSE; + + + if(val_ctrl & ETH_PHY_CTRL_AN_ENABLE_MASK) + { + if(val_st & ETH_PHY_STATUS_AN_DONE_MASK) + return MV_TRUE; + else + return MV_FALSE; + } + else + { + if(val_spec_st & ETH_PHY_SPEC_STATUS_LINK_MASK) + return MV_TRUE; + } + return MV_FALSE; +} + +/******************************************************************************* +* mvEthPhyPrintStatus - +* +* DESCRIPTION: +* print port Speed, Duplex, Auto-negotiation, Link. +* +* INPUT: +* phyAddr - Phy address. +* +* OUTPUT: +* None. +* +* RETURN: 16bit phy register value, or 0xffff on error +* +*******************************************************************************/ +MV_STATUS mvEthPhyPrintStatus( MV_U32 phyAddr ) +{ + MV_U16 val; + + /* read control reg */ + if( mvEthPhyRegRead( phyAddr, ETH_PHY_CTRL_REG, &val) != MV_OK ) + return MV_ERROR; + + if( val & ETH_PHY_CTRL_AN_ENABLE_MASK ) + mvOsOutput( "Auto negotiation: Enabled\n" ); + else + mvOsOutput( "Auto negotiation: Disabled\n" ); + + + /* read specific status reg */ + if( mvEthPhyRegRead( phyAddr, ETH_PHY_SPEC_STATUS_REG, &val) != MV_OK ) + return MV_ERROR; + + switch (val & ETH_PHY_SPEC_STATUS_SPEED_MASK) + { + case ETH_PHY_SPEC_STATUS_SPEED_1000MBPS: + mvOsOutput( "Speed: 1000 Mbps\n" ); + break; + case ETH_PHY_SPEC_STATUS_SPEED_100MBPS: + mvOsOutput( "Speed: 100 Mbps\n" ); + break; + case ETH_PHY_SPEC_STATUS_SPEED_10MBPS: + mvOsOutput( "Speed: 10 Mbps\n" ); + default: + mvOsOutput( "Speed: Uknown\n" ); + break; + + } + + if( val & ETH_PHY_SPEC_STATUS_DUPLEX_MASK ) + mvOsOutput( "Duplex: Full\n" ); + else + mvOsOutput( "Duplex: Half\n" ); + + + if( val & ETH_PHY_SPEC_STATUS_LINK_MASK ) + mvOsOutput("Link: up\n"); + else + mvOsOutput("Link: down\n"); + + return MV_OK; +} + +/******************************************************************************* +* mvEthE1111PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1111PhyBasicInit(MV_U32 ethPortNum) +{ + MV_U16 reg; + MV_U32 regOff, data; + + /* Phy recv and tx delay */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),20,®); + reg |= BIT1 | BIT7; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),20,reg); + + /* Leds link and activity*/ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,0x4111); + + /* reset the phy */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®); + reg |= BIT15; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg); + + if(mvBoardSpecInitGet(®Off, &data) == MV_TRUE) + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),regOff , data); + +} + +/******************************************************************************* +* mvEthE1112PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1112PhyBasicInit(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /* Set phy address */ + /*MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));*/ + + /* Implement PHY errata */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,0x140); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,0x8140); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0); + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,3); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x103); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0); + + /* reset the phy */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®); + reg |= BIT15; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg); + +} + +/******************************************************************************* +* mvEthE1116PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1116PhyBasicInit(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /* Set phy address */ + MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum)); + + /* Leds link and activity*/ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x3); + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®); + reg &= ~0xf; + reg |= 0x1; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0); + + /* Set RGMII delay */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2); + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),21,®); + reg |= (BIT5 | BIT4); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),21,reg); + + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),24,®); + reg |= (BIT6 | BIT0 | BIT8); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,reg); + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0); + + /* reset the phy */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®); + reg |= BIT15; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg); +} + + +/******************************************************************************* +* mvEthE3016PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE3016PhyBasicInit(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /* Set phy address */ + MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum)); + + /* Leds link and activity*/ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),22,®); + reg &= ~0xf; + reg |= 0xa; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,reg); + + /* Set RGMII (RX) delay and copper mode */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),28,®); + reg &= ~(BIT3 | BIT10 | BIT11); + reg |= (BIT10); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),28,reg); + + /* reset the phy */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®); + reg |= BIT15; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg); +} + + +/******************************************************************************* +* mvEthE1011PhyBasicInit - +* +* DESCRIPTION: +* Do a basic Init to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1011PhyBasicInit(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /* Phy recv and tx delay */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),20,®); + reg &= ~(BIT1 | BIT7); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),20,reg); + + /* Leds link and activity*/ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,0x4111); + + /* reset the phy */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0, ®); + reg |= BIT15; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg); + +} + +/******************************************************************************* +* mvEthE1112PhyPowerDown - +* +* DESCRIPTION: +* Power down the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1112PhyPowerDown(MV_U32 ethPortNum) +{ + mvEthPhyPower(ethPortNum, MV_FALSE); +} + +/******************************************************************************* +* mvEthE1112PhyPowerUp - +* +* DESCRIPTION: +* Power up the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +MV_VOID mvEthE1112PhyPowerUp(MV_U32 ethPortNum) +{ + mvEthPhyPower(ethPortNum, MV_TRUE); +} + +/******************************************************************************* +* mvEthPhyPower - +* +* DESCRIPTION: +* Do a basic power down/up to the Phy , including reset +* +* INPUT: +* ethPortNum - Ethernet port number +* enable - MV_TRUE - power up +* MV_FALSE - power down +* +* OUTPUT: +* None. +* +* RETURN: None +* +*******************************************************************************/ +static MV_VOID mvEthPhyPower(MV_U32 ethPortNum, MV_BOOL enable) +{ + MV_U16 reg; + if (enable == MV_FALSE) + { + /* Power down command */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2); /* select page 2 */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®); + reg |= BIT3; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg); /* select to disable the SERDES */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0); /* select page 0 */ + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,3); /* Power off LED's */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x88); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0); + + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®); + reg |= ETH_PHY_CTRL_RESET_BIT; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* software reset */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®); + reg |= ETH_PHY_CTRL_POWER_DOWN_BIT; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* power down the PHY */ + } + else + { + /* Power up command */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2); /* select page 2 */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®); + reg &= ~BIT3; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg); /* select to enable the SERDES */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0); /* select page 0 */ + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,3); /* Power on LED's */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x03); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0); + + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®); + reg |= ETH_PHY_CTRL_RESET_BIT; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* software reset */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®); + reg &= ~ETH_PHY_CTRL_POWER_DOWN_BIT; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* power up the PHY */ + } +} + + +/******************************************************************************* +* mvEth1145PhyInit - Initialize MARVELL 1145 Phy +* +* DESCRIPTION: +* +* INPUT: +* phyAddr - Phy address. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvEth1145PhyBasicInit(MV_U32 port) +{ + MV_U16 value; + + /* Set phy address for each port */ + MV_REG_WRITE(ETH_PHY_ADDR_REG(port), mvBoardPhyAddrGet(port)); + /* Set Link1000 output pin to be link indication, set Tx output pin to be activity */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x18, ETH_PHY_LED_ACT_LNK_DV); + mvOsDelay(10); + + /* Add delay to RGMII Tx and Rx */ + mvEthPhyRegRead(mvBoardPhyAddrGet(port), 0x14, &value); + mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x14,(value | BIT1 | BIT7)); + mvOsDelay(10); +#if 0 /* Fix by yotam */ + if (boardId != RD_78XX0_AMC_ID && + boardId != RD_78XX0_H3C_ID) { + /* Set port 2 - Phy addr 9 to RGMII */ + if (port == 2) + { + mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x1b, 0x808b); + mvOsDelay(10); + } + + /* Set port 1 - Phy addr a to SGMII */ + if (port == 1) + { + mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x1b, 0x8084); + mvOsDelay(10); + + /* Reset Phy */ + mvEthPhyRegRead( mvBoardPhyAddrGet(port), 0x00, &value); + mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x00, (value | BIT15)); + mvOsDelay(10); + #if defined(SGMII_OUTBAND_AN) + /* Set port 1 - Phy addr A Page 1 */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x16, 0x1); + mvOsDelay(10); + + /* Set port 1 - Phy addr A disable A.N. */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x0, 0x140); + mvOsDelay(10); + + /* Set port 1 - Phy addr A reset */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x0, 0x8140); + mvOsDelay(10); + + mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x16, 0x0); + mvOsDelay(10); + #endif + } + } +#endif + + /* Set Phy TPVL to 0 */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x10, 0x60); + mvOsDelay(10); + + /* Reset Phy */ + mvEthPhyRegRead(mvBoardPhyAddrGet(port), 0x00, &value); + mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x00, (value | BIT15)); + mvOsDelay(10); + + return; +} + + +/******************************************************************************* +* mvEthSgmiiToCopperPhyInit - Initialize Test board 1112 Phy +* +* DESCRIPTION: +* +* INPUT: +* phyAddr - Phy address. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvEthSgmiiToCopperPhyBasicInit(MV_U32 port) +{ + MV_U16 value; + MV_U16 phyAddr = 0xC; + + /* Port 0 phyAdd c */ + /* Port 1 phyAdd d */ + mvEthPhyRegWrite(phyAddr + port,22,3); + mvEthPhyRegWrite(phyAddr + port,16,0x103); + mvEthPhyRegWrite(phyAddr + port,22,0); + + /* reset the phy */ + mvEthPhyRegRead(phyAddr + port,0,&value); + value |= BIT15; + mvEthPhyRegWrite(phyAddr + port,0,value); +} + + +MV_VOID mvEth1121PhyBasicInit(MV_U32 port) +{ + MV_U16 value; + MV_U16 phyAddr = mvBoardPhyAddrGet(port); + + MV_REG_WRITE(ETH_PHY_ADDR_REG(port), phyAddr); + + /* Change page select to 2 */ + value = 2; + mvEthPhyRegWrite(phyAddr, 22, value); + mvOsDelay(10); + + /* Set RGMII rx delay */ + mvEthPhyRegRead(phyAddr, 21, &value); + value |= BIT5; + mvEthPhyRegWrite(phyAddr, 21, value); + mvOsDelay(10); + + /* Change page select to 0 */ + value = 0; + mvEthPhyRegWrite(phyAddr, 22, value); + mvOsDelay(10); + + /* reset the phy */ + mvEthPhyRegRead(phyAddr, 0, &value); + value |= BIT15; + mvEthPhyRegWrite(phyAddr, 0, value); + mvOsDelay(10); +} + +#if defined(CONFIG_BUFFALO_PLATFORM) +MV_VOID mvEthE111xPhyBasicInit_internal(MV_U32 ethPortNum, MV_U32 flag_PolarityChange) +{ + MV_U16 reg; + + /*read PHY Ident2*/ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 3, ®); + reg &= 0x03f0 ; + + if(reg == 0x00c0) + { + /* Phy recv and tx delay */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),20,®); + reg |= BIT1 | BIT7; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),20,reg); + + /* Leds link and activity*/ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,0x4111); + + /* reset the phy */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®); + reg |= BIT15; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg); + } + else + { + /* Added by Hiroshi Tokoyo */ + MV_REG_WRITE(0xf1072000, mvBoardPhyAddrGet(ethPortNum)); + /* Access Page 3*/ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x3); + reg = 0x0911; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg); + + if(flag_PolarityChange) + { + // led polarity setting. + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 17, ®); + reg &= ~0x003f; + reg |= 0x0005; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 17, reg); + } + + /* change to Page 0*/ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0); + /* Added by Hiroshi */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®); + reg |= 0x8000; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg); + } + + return; +} + +/******************************************************************************* +* bfPhyPowerUp +* +* DESCRIPTION: +* Power up specified phy. +* +* INPUT: +* ethPortNum : No. of target ethernet port. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void +bfPhyPowerUp(MV_U32 ethPortNum) +{ + MV_U16 reg; + int i; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 0x2); /* change to Page 2 */ + reg = 0x044E ; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 2, reg); + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 0x0); /* change to Page 0 */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 0, 0x1340); + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 0, ®); + reg |= 0x8000; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 0, reg); + + /* RGMII Caribrate */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22, 0x2); /* change to Page 2 */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 24, ®); + reg = 0x8000; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 24, reg); + + for(i = 0; i < 0xFFFF; i++) + { + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 24, ®); + if(reg & BIT14) + break ; + } + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 0x0); /* change to Page 0 */ + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 0, 0x1340); + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 0, ®); + reg |= 0x8000 ; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 0, reg ); + for(i = 0; i < 0xFFFF; i++) + { + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 24, ®); + if(!(reg & BIT15)) + break ; + } +} + +/******************************************************************************* +* mvEthE1111PhyBasicTest - +* +* DESCRIPTION: +* +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* . +* +* RETURN: None +* +*******************************************************************************/ +MV_STATUS Is_mvEthE111xPhy(MV_U32 ethPortNum) +{ + MV_U16 reg; + + /* Phy recv and tx delay */ + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),2,®); + /*Check EthE1111PhyID */ + if(reg == 0x141) /*Identify Bit*/ + { + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),3,®); + reg &= 0x03f0 ; + if(reg == 0x00c0) + { + return 0x1111 ; + }else + if(reg == 0x0210) + { + return 0x1118 ; + } + return MV_OK ; + } + else + { + return MV_FAIL; + } + +} +/******************************************************************************* +* mvEthE1111PhyBasicTest - +* +* DESCRIPTION: +* +* +* INPUT: +* ethPortNum - Ethernet port number +* +* OUTPUT: +* . +* +* RETURN: None +* +*******************************************************************************/ +MV_STATUS Is_link_mvEthE1111Phy(MV_U32 ethPortNum) +{ + MV_U16 val; + + /* Phy recv and tx delay */ + if( mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), ETH_PHY_SPEC_STATUS_REG, &val) != MV_OK ) +/* return MV_ERROR;*/ + { + printf("phy return NG \n"); + } + + if((val & 0x0400) == 0x0400 ) /*is LINK UP ?*/ + { + return MV_OK; + } + else + { + return MV_FAIL; + } +} + +// 1112, 1118 common. +MV_VOID +buffalo_link_led_off_mvEthE111xPhy(MV_U32 ethPortNum) +{ + MV_U16 reg; + + MV_U32 CurrentPageBackup = mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, 0); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 3); + + // led work mode setting. + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 16, ®); + reg &= 0xF000; + reg |= 0x0888; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, reg); + + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, CurrentPageBackup); +} + +// 1112, 1118 common. +MV_VOID +buffalo_link_led_on_mvEthE111xPhy(MV_U32 ethPortNum) +{ + MV_U16 reg; + + MV_U32 CurrentPageBackup = mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 22, 0); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, 3); + mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum), 16, ®); + reg &= 0xF000; + reg |= 0x0111; + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 16, reg); + mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum), 22, CurrentPageBackup); +} + +MV_VOID +buffalo_link_led_off(MV_U32 ethPortNum) +{ + buffalo_link_led_off_mvEthE111xPhy(ethPortNum); +} + +MV_VOID +buffalo_link_led_on(MV_U32 ethPortNum) +{ + buffalo_link_led_on_mvEthE111xPhy(ethPortNum); +} + +#include "boardEnv/mvBoardEnvSpec.h" +extern MV_BOARD_INFO* boardInfoTbl[]; +#define BOARD_INFO(boardId) boardInfoTbl[boardId - BUFFALO_BOARD_ID_BASE] + +MV_VOID +buffalo_all_link_led_off() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + for (i = 0; i < BOARD_INFO(boardId)->numBoardMacInfo; i++) { + buffalo_link_led_off_mvEthE111xPhy(i); + } +} + +MV_VOID +buffalo_all_link_led_on() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + for (i = 0; i < BOARD_INFO(boardId)->numBoardMacInfo; i++) { + buffalo_link_led_on_mvEthE111xPhy(i); + } +} + +MV_VOID +buffalo_print_phy_addr(MV_VOID) +{ + MV_U32 port; + + for(port = 0; port < mvCtrlEthMaxPortGet(); port++){ + printf("PHY %d :0x%08x\n", port, mvBoardPhyAddrGet(port)); + mvEthPhyPrintStatus(mvBoardPhyAddrGet(port)); + printf("\n"); + } +} + +#endif // of (CONFIG_BUFFALO_PLATFORM) diff --git a/board/mv_feroceon/mv_hal/eth-phy/mvEthPhy.h b/board/mv_feroceon/mv_hal/eth-phy/mvEthPhy.h new file mode 100644 index 0000000..25a69c8 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth-phy/mvEthPhy.h @@ -0,0 +1,117 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCETHPHYH +#define __INCETHPHYH + +#include "mvCommon.h" +#include "mvOs.h" +#include "mvEthPhyRegs.h" + + +MV_STATUS mvEthPhyRegRead(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 *data); +MV_STATUS mvEthPhyRegWrite(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 data); +MV_STATUS mvEthPhyReset(MV_U32 phyAddr, int timeout); +MV_STATUS mvEthPhyRestartAN(MV_U32 phyAddr, int timeout); +MV_STATUS mvEthPhyDisableAN(MV_U32 phyAddr, int speed, int duplex); +MV_STATUS mvEthPhyLoopback(MV_U32 phyAddr, MV_BOOL isEnable); +MV_BOOL mvEthPhyCheckLink(MV_U32 phyAddr); +MV_STATUS mvEthPhyPrintStatus(MV_U32 phyAddr); +MV_VOID mvEthE1111PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE1112PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE1112PhyPowerDown(MV_U32 ethPortNum); +MV_VOID mvEthE1112PhyPowerUp(MV_U32 ethPortNum); +MV_VOID mvEthE1116PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE3016PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthE1011PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEthSgmiiToCopperPhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEth1145PhyBasicInit(MV_U32 ethPortNum); +MV_VOID mvEth1121PhyBasicInit(MV_U32 ethPortNum); + +#if defined(CONFIG_BUFFALO_PLATFORM) +MV_VOID mvEthE111xPhyBasicInit_internal(MV_U32 ethPortNum, MV_U32 flag_PolarityChange); +#define mvEthE111xPhyBasicInit(x) mvEthE111xPhyBasicInit_internal(x, 0) +#define mvEthE111xPhyBasicInitLedPolarityChange(x) mvEthE111xPhyBasicInit_internal(x, 1) + +MV_STATUS Is_mvEthE111xPhy(MV_U32 ethPortNum) ; +MV_STATUS Is_link_mvEthE1111Phy(MV_U32 ethPortNum) ; +MV_VOID buffalo_all_link_led_off(MV_VOID); +MV_VOID buffalo_all_link_led_on(MV_VOID); + +#if 0 +#define FLAG_BUFFALO_WOL_INTERRUPT_ENABLE 1 +#define FLAG_BUFFALO_WOL_INTERRUPT_DISABLE 0 + +void bfResetEthPhy(MV_U32 ethPortNum); +void bfControlWolInterrupt(MV_U32 ethPortNum, MV_U8 ope); +MV_BOOL bfIsSupportWol(MV_U32 ethPortNum); +MV_BOOL bfSetWolMagicWaitMode(MV_U32 ethPortNum, MV_U8 *pMacAddr); +MV_BOOL bfSetWolFrameWaitMode(MV_U32 ethPortNum, MV_U8 *pMacAddr, int debug); +MV_U16 bfGetWolInterruptStatus(MV_U32 ethPortNum, int debug); +void bfPhyPowerUp(MV_U32 ethPortNum); +char *bfGetWolPatternString(MV_U16 wol_stat); +#endif +#endif // defined(CONFIG_BUFFALO_PLATFORM) + +#endif /* #ifndef __INCETHPHYH */ diff --git a/board/mv_feroceon/mv_hal/eth-phy/mvEthPhyRegs.h b/board/mv_feroceon/mv_hal/eth-phy/mvEthPhyRegs.h new file mode 100644 index 0000000..24a2ef3 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth-phy/mvEthPhyRegs.h @@ -0,0 +1,167 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCethphyregsh +#define __INCethphyregsh + +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* defines */ +#define ETH_PHY_TIMEOUT 10000 + +/* registers offsetes defines */ +#ifdef MV_88W8660 +#define ETH_PHY_SMI_REG (MV_ETH_REG_BASE(0) + 0x6010) +#else +#define ETH_PHY_SMI_REG (MV_ETH_REG_BASE(0) + 0x004) +#endif + +/* SMI register fields (ETH_PHY_SMI_REG) */ + +#define ETH_PHY_SMI_DATA_OFFS 0 /* Data */ +#define ETH_PHY_SMI_DATA_MASK (0xffff << ETH_PHY_SMI_DATA_OFFS) + +#define ETH_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ +#define ETH_PHY_SMI_DEV_ADDR_MASK (0x1f << ETH_PHY_SMI_DEV_ADDR_OFFS) + +#define ETH_PHY_SMI_REG_ADDR_OFFS 21 /* PHY device register address */ +#define ETH_PHY_SMI_REG_ADDR_MASK (0x1f << ETH_PHY_SMI_REG_ADDR_OFFS) + +#define ETH_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ +#define ETH_PHY_SMI_OPCODE_MASK (3 << ETH_PHY_SMI_OPCODE_OFFS) +#define ETH_PHY_SMI_OPCODE_WRITE (0 << ETH_PHY_SMI_OPCODE_OFFS) +#define ETH_PHY_SMI_OPCODE_READ (1 << ETH_PHY_SMI_OPCODE_OFFS) + +#define ETH_PHY_SMI_READ_VALID_BIT 27 /* Read Valid */ +#define ETH_PHY_SMI_READ_VALID_MASK (1 << ETH_PHY_SMI_READ_VALID_BIT) + +#define ETH_PHY_SMI_BUSY_BIT 28 /* Busy */ +#define ETH_PHY_SMI_BUSY_MASK (1 << ETH_PHY_SMI_BUSY_BIT) + +/* PHY registers and bits */ +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_STATUS_REG 1 +#define ETH_PHY_AUTONEGO_AD_REG 4 +#define ETH_PHY_1000BASE_T_CTRL_REG 9 +#define ETH_PHY_SPEC_CTRL_REG 16 +#define ETH_PHY_SPEC_STATUS_REG 17 + +/* ETH_PHY_CTRL_REG bits */ +#define ETH_PHY_CTRL_SPEED_MSB_BIT 6 +#define ETH_PHY_CTRL_SPEED_MSB_MASK (1 << ETH_PHY_CTRL_SPEED_MSB_BIT) + +#define ETH_PHY_CTRL_COLISION_TEST_BIT 7 +#define ETH_PHY_CTRL_COLISION_TEST_MASK (1 << ETH_PHY_CTRL_COLISION_TEST_BIT) + +#define ETH_PHY_CTRL_DUPLEX_BIT 8 +#define ETH_PHY_CTRL_DUPLEX_MASK (1 << ETH_PHY_CTRL_DUPLEX_BIT) + +#define ETH_PHY_CTRL_AN_RESTART_BIT 9 +#define ETH_PHY_CTRL_AN_RESTART_MASK (1 << ETH_PHY_CTRL_AN_RESTART_BIT) + +#define ETH_PHY_CTRL_ISOLATE_BIT 10 +#define ETH_PHY_CTRL_ISOLATE_MASK (1 << ETH_PHY_CTRL_ISOLATE_BIT) + +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) + +#define ETH_PHY_CTRL_AN_ENABLE_BIT 12 +#define ETH_PHY_CTRL_AN_ENABLE_MASK (1 << ETH_PHY_CTRL_AN_ENABLE_BIT) + +#define ETH_PHY_CTRL_SPEED_LSB_BIT 13 +#define ETH_PHY_CTRL_SPEED_LSB_MASK (1 << ETH_PHY_CTRL_SPEED_LSB_BIT) + +#define ETH_PHY_CTRL_LOOPBACK_BIT 14 +#define ETH_PHY_CTRL_LOOPBACK_MASK (1 << ETH_PHY_CTRL_LOOPBACK_BIT) + +#define ETH_PHY_CTRL_RESET_BIT 15 +#define ETH_PHY_CTRL_RESET_MASK (1 << ETH_PHY_CTRL_RESET_BIT) + +/* ETH_PHY_STATUS_REG bits */ +#define ETH_PHY_STATUS_AN_DONE_BIT 5 +#define ETH_PHY_STATUS_AN_DONE_MASK (1 << ETH_PHY_STATUS_AN_DONE_BIT) + +/* ETH_PHY_1000BASE_T_CTRL_REG bits */ +#define ETH_PHY_1000BASE_ADVERTISE_OFFSET 8 +#define ETH_PHY_1000BASE_ADVERTISE_MASK (0x3 << ETH_PHY_1000BASE_ADVERTISE_OFFSET) + +/* ETH_PHY_SPEC_STATUS_REG bits */ +#define ETH_PHY_SPEC_STATUS_SPEED_OFFS 14 +#define ETH_PHY_SPEC_STATUS_SPEED_MASK (0x3 << ETH_PHY_SPEC_STATUS_SPEED_OFFS) + +#define ETH_PHY_SPEC_STATUS_SPEED_10MBPS (0x0 << ETH_PHY_SPEC_STATUS_SPEED_OFFS) +#define ETH_PHY_SPEC_STATUS_SPEED_100MBPS (0x1 << ETH_PHY_SPEC_STATUS_SPEED_OFFS) +#define ETH_PHY_SPEC_STATUS_SPEED_1000MBPS (0x2 << ETH_PHY_SPEC_STATUS_SPEED_OFFS) + + +#define ETH_PHY_SPEC_STATUS_DUPLEX_BIT 13 +#define ETH_PHY_SPEC_STATUS_DUPLEX_MASK (0x1 << ETH_PHY_SPEC_STATUS_DUPLEX_BIT) + +#define ETH_PHY_SPEC_STATUS_LINK_BIT 10 +#define ETH_PHY_SPEC_STATUS_LINK_MASK (0x1 << ETH_PHY_SPEC_STATUS_LINK_BIT) + +/* ETH_PHY_SPEC_STATUS_REG bits */ +#define ETH_PHY_LED_ACT_LNK_DV 0x4109 + +#endif /* __INCethphyregsh */ diff --git a/board/mv_feroceon/mv_hal/eth/gbe/mvEth.c b/board/mv_feroceon/mv_hal/eth/gbe/mvEth.c new file mode 100644 index 0000000..d8ac566 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/gbe/mvEth.c @@ -0,0 +1,2948 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEth.c - Marvell's Gigabit Ethernet controller low level driver +* +* DESCRIPTION: +* This file introduce OS independent APIs to Marvell's Gigabit Ethernet +* controller. This Gigabit Ethernet Controller driver API controls +* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). +* 2) Data flow (i.e. port Send, Receive etc'). +* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) +* 4) MIB counters support (ethReadMibCounter) +* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) +* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. +* This struct includes configuration information as well as driver +* internal data needed for its operations. +* +* Supported Features: +* - OS independent. All required OS services are implemented via external +* OS dependent components (like osLayer or ethOsg) +* - The user is free from Rx/Tx queue managing. +* - Simple Gigabit Ethernet port operation API. +* - Simple Gigabit Ethernet port data flow API. +* - Data flow and operation API support per queue functionality. +* - Support cached descriptors for better performance. +* - PHY access and control API. +* - Port Configuration API. +* - Full control over Special and Other Multicast MAC tables. +* +*******************************************************************************/ +/* includes */ +#include "mvTypes.h" +#include "mv802_3.h" +#include "mvDebug.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "eth-phy/mvEthPhy.h" +#include "eth/mvEth.h" +#include "eth/gbe/mvEthGbe.h" +#include "cpu/mvCpu.h" + +#ifdef INCLUDE_SYNC_BARR +#include "sys/mvCpuIf.h" +#endif + +#ifdef MV_RT_DEBUG +# define ETH_DEBUG +#endif + + +/* locals */ +MV_BOOL ethDescInSram; +MV_BOOL ethDescSwCoher; + +/* This array holds the control structure of each port */ +ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; + +/* Ethernet Port Local routines */ + +static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); + +static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); + +static void ethSetUcastTable(int portNo, int queue); + +static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); +static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); +static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); + +static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); +static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, + MV_ULONG* pPhysAddr, MV_U32 *memHandle); + +static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); + +static void mvEthPortSgmiiConfig(int port); + + + +/******************************************************************************/ +/* EthDrv Initialization functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthHalInit - Initialize the Giga Ethernet unit +* +* DESCRIPTION: +* This function initialize the Giga Ethernet unit. +* 1) Configure Address decode windows of the unit +* 2) Set registers to HW default values. +* 3) Clear and Disable interrupts +* +* INPUT: NONE +* +* RETURN: NONE +* +* NOTE: this function is called once in the boot process. +*******************************************************************************/ +void mvEthHalInit(void) +{ + int port; + + /* Init static data structures */ + for (port=0; port 0) + { + isSram = MV_TRUE; + #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) + isSwCoher = MV_TRUE; + #else + isSwCoher = MV_FALSE; + #endif + } +#endif /* ETH_DESCR_IN_SRAM */ + + if(pIsSram != NULL) + *pIsSram = isSram; + + if(pIsSwCoher != NULL) + *pIsSwCoher = isSwCoher; +} + + + +/******************************************************************************/ +/* Port Initialization functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthPortInit - Initialize the Ethernet port driver +* +* DESCRIPTION: +* This function initialize the ethernet port. +* 1) Allocate and initialize internal port Control structure. +* 2) Create RX and TX descriptor rings for default RX and TX queues +* 3) Disable RX and TX operations, clear cause registers and +* mask all interrupts. +* 4) Set all registers to default values and clean all MAC tables. +* +* INPUT: +* int portNo - Ethernet port number +* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure +* +* RETURN: +* void* - ethernet port handler, that should be passed to the most other +* functions dealing with this port. +* +* NOTE: This function is called once per port when loading the eth module. +*******************************************************************************/ +void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) +{ + int queue, descSize; + ETH_PORT_CTRL* pPortCtrl; + + /* Check validity of parameters */ + if( (portNo >= (int)mvCtrlEthMaxPortGet()) || + (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) ) + { + mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); + return NULL; + } + if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) + { + mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", + portNo, pEthPortInit->rxDefQ); + return NULL; + } + + pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); + if(pPortCtrl == NULL) + { + mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", + (int)sizeof(ETH_PORT_CTRL), portNo); + return NULL; + } + + memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); + ethPortCtrl[portNo] = pPortCtrl; + + pPortCtrl->portState = MV_UNDEFINED_STATE; + + pPortCtrl->portNo = portNo; + + pPortCtrl->osHandle = pEthPortInit->osHandle; + + /* Copy Configuration parameters */ + pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; + pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; + pPortCtrl->portConfig.ejpMode = 0; + + for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; + } + for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; + } + + mvEthPortDisable(pPortCtrl); + + /* Set the board information regarding PHY address */ + mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); + + /* Create all requested RX queues */ + for(queue=0; queuerxQueueConfig[queue].descrNum == 0) + continue; + + /* Allocate memory for RX descriptors */ + descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + + CPU_D_CACHE_LINE_SIZE); + + pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = + ethAllocDescrMemory(pPortCtrl, descSize, + &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, + &pPortCtrl->rxQueue[queue].descBuf.memHandle); + pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; + if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) + { + mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", + pPortCtrl->portNo, queue, descSize, + ethDescInSram ? "SRAM" : "DRAM", + pPortCtrl->rxQueueConfig[queue].descrNum); + return NULL; + } + + ethInitRxDescRing(pPortCtrl, queue); + } + /* Create TX queues */ + for(queue=0; queuetxQueueConfig[queue].descrNum == 0) + continue; + + /* Allocate memory for TX descriptors */ + descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + + CPU_D_CACHE_LINE_SIZE); + + pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = + ethAllocDescrMemory(pPortCtrl, descSize, + &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, + &pPortCtrl->txQueue[queue].descBuf.memHandle); + pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; + if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) + { + mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", + pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", + pPortCtrl->txQueueConfig[queue].descrNum); + return NULL; + } + + ethInitTxDescRing(pPortCtrl, queue); + } + mvEthDefaultsSet(pPortCtrl); + + pPortCtrl->portState = MV_IDLE; + return pPortCtrl; +} + +/******************************************************************************* +* ethPortFinish - Finish the Ethernet port driver +* +* DESCRIPTION: +* This function finish the ethernet port. +* 1) Down ethernet port if needed. +* 2) Delete RX and TX descriptor rings for all created RX and TX queues +* 3) Free internal port Control structure. +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: NONE. +* +*******************************************************************************/ +void mvEthPortFinish(void* pPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + int queue, portNo = pPortCtrl->portNo; + + if(pPortCtrl->portState == MV_ACTIVE) + { + mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", + portNo); + mvEthPortDisable(pPortHndl); + } + + /* Free all allocated RX queues */ + for(queue=0; queuerxQueue[queue].descBuf); + } + + /* Free all allocated TX queues */ + for(queue=0; queuetxQueue[queue].descBuf); + } + + /* Free port control structure */ + mvOsFree(pPortCtrl); + + ethPortCtrl[portNo] = NULL; +} + +/******************************************************************************* +* mvEthDefaultsSet - Set defaults to the ethernet port +* +* DESCRIPTION: +* This function set default values to the ethernet port. +* 1) Clear Cause registers and Mask all interrupts +* 2) Clear all MAC tables +* 3) Set defaults to all registers +* 4) Reset all created RX and TX descriptors ring +* 5) Reset PHY +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure +* NOTE: +* This function update all the port configuration except those set +* Initialy by the OsGlue by MV_ETH_PORT_INIT. +* This function can be called after portDown to return the port setting +* to defaults. +*******************************************************************************/ +MV_STATUS mvEthDefaultsSet(void* pPortHndl) +{ + int ethPortNo, queue; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + MV_U32 txPrio; + MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; + MV_BOARD_MAC_SPEED boardMacCfg; + + ethPortNo = pPortCtrl->portNo; + + /* Clear Cause registers */ + MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); + MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); + + /* Mask all interrupts */ + MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); + MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); + + portCfgReg = PORT_CONFIG_VALUE; + portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; + + boardMacCfg = mvBoardMacSpeedGet(ethPortNo); + + if(boardMacCfg == BOARD_MAC_SPEED_100M) + { + portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; + } + else if(boardMacCfg == BOARD_MAC_SPEED_1000M) + { + portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; + } + else + { + portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; + } + + /* build PORT_SDMA_CONFIG_REG */ + portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); + portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); + +#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ + (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) + /* some devices have restricted RX burst size when using HW coherency */ + portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); +#else + portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); +#endif + +#if defined(MV_CPU_BE) + /* big endian */ +# if defined(MV_ARM) + portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | + ETH_TX_NO_DATA_SWAP_MASK | + ETH_DESC_SWAP_MASK); +# elif defined(MV_PPC) + portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | + ETH_TX_DATA_SWAP_MASK | + ETH_NO_DESC_SWAP_MASK); +# else +# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" +# endif /* MV_ARM / MV_PPC */ + +#else /* MV_CPU_LE */ + /* little endian */ + portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | + ETH_TX_NO_DATA_SWAP_MASK | + ETH_NO_DESC_SWAP_MASK); +#endif /* MV_CPU_BE / MV_CPU_LE */ + + pPortCtrl->portRxQueueCmdReg = 0; + pPortCtrl->portTxQueueCmdReg = 0; + +#if (MV_ETH_VERSION >= 4) + if(pPortCtrl->portConfig.ejpMode == MV_TRUE) + { + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); + } + else + { + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) + } +#endif /* (MV_ETH_VERSION >= 4) */ + + ethSetUcastTable(ethPortNo, -1); + mvEthSetSpecialMcastTable(ethPortNo, -1); + mvEthSetOtherMcastTable(ethPortNo, -1); + + portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; + + portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); + + /* Update value of PortConfig register accordingly with all RxQueue types */ + pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; + + portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); + + portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); + + portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); + + portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); + + portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); + + /* Assignment of Tx CTRP of given queue */ + txPrio = 0; + + for(queue=0; queuetxQueue[queue]; + + if(pQueueCtrl->pFirstDescr != NULL) + { + ethResetTxDescRing(pPortCtrl, queue); + + MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), + 0x3fffffff); + MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), + 0x03ffffff); + } + else + { + MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); + MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); + } + } + + /* Assignment of Rx CRDP of given queue */ + for(queue=0; queueportNo; + + if( (pPortCtrl->portState != MV_ACTIVE) && + (pPortCtrl->portState != MV_PAUSED) ) + { + mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", + ethPortNo, pPortCtrl->portState); + return MV_BAD_STATE; + } + + ethPortNo = pPortCtrl->portNo; + + /* Enable port RX. */ + MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); + + /* Enable port TX. */ + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; + + pPortCtrl->portState = MV_ACTIVE; + + return MV_OK; +} + +/******************************************************************************* +* ethPortDown - Stop the Ethernet port activity. +* +* DESCRIPTION: +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE : used for port link down. +*******************************************************************************/ +MV_STATUS mvEthPortDown(void* pEthPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + int ethPortNum = pPortCtrl->portNo; + unsigned int regData; + volatile int uDelay, mDelay; + + /* Stop Rx port activity. Check port Rx activity. */ + regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; + if(regData != 0) + { + /* Issue stop command for active channels only */ + MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); + } + + /* Stop Tx port activity. Check port Tx activity. */ + regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; + if(regData != 0) + { + /* Issue stop command for active channels only */ + MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), + (regData << ETH_TXQ_DISABLE_OFFSET) ); + } + + /* Force link down */ +/* + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); +*/ + /* Wait for all Rx activity to terminate. */ + mDelay = 0; + do + { + if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) + { + mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", + ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + /* Check port RX Command register that all Rx queues are stopped */ + regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); + } + while(regData & 0xFF); + + /* Wait for all Tx activity to terminate. */ + mDelay = 0; + do + { + if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) + { + mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", + ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + /* Check port TX Command register that all Tx queues are stopped */ + regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); + } + while(regData & 0xFF); + + /* Double check to Verify that TX FIFO is Empty */ + mDelay = 0; + while(MV_TRUE) + { + do + { + if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) + { + mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", + ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); + } + while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || + ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); + + if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) + break; + + /* Double check */ + regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); + if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && + ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) + { + break; + } + else + mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", + ethPortNum, mDelay, regData); + } + + /* Do NOT force link down */ +/* + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); +*/ + /* Wait about 2500 tclk cycles */ + uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); + mvOsUDelay(uDelay); + + pPortCtrl->portState = MV_PAUSED; + + return MV_OK; +} + + +/******************************************************************************* +* ethPortEnable - Enable the Ethernet port and Start RX and TX. +* +* DESCRIPTION: +* This routine enable the Ethernet port and Rx and Tx activity: +* +* Note: Each Rx and Tx queue descriptor's list must be initialized prior +* to calling this function (use etherInitTxDescRing for Tx queues and +* etherInitRxDescRing for Rx queues). +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE: main usage is to enable the port after ifconfig up. +*******************************************************************************/ +MV_STATUS mvEthPortEnable(void* pEthPortHndl) +{ + int ethPortNo; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + MV_U32 portSerialCtrlReg; + + ethPortNo = pPortCtrl->portNo; + + /* Enable port */ + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); + portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); + + mvEthMibCountersClear(pEthPortHndl); + + pPortCtrl->portState = MV_PAUSED; + + /* If Link is UP, Start RX and TX traffic */ + if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) + return( mvEthPortUp(pEthPortHndl) ); + + return MV_NOT_READY; +} + + +/******************************************************************************* +* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. +* +* DESCRIPTION: +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE: main usage is to disable the port after ifconfig down. +*******************************************************************************/ +MV_STATUS mvEthPortDisable(void* pEthPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + int ethPortNum = pPortCtrl->portNo; + unsigned int regData; + volatile int mvDelay; + + if(pPortCtrl->portState == MV_ACTIVE) + { + /* Stop RX and TX activities */ + mvEthPortDown(pEthPortHndl); + } + + /* Reset the Enable bit in the Serial Control Register */ + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData &= ~(ETH_PORT_ENABLE_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); + + /* Wait about 2500 tclk cycles */ + mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); + for(mvDelay; mvDelay>0; mvDelay--); + + pPortCtrl->portState = MV_IDLE; + return MV_OK; +} + +/******************************************************************************* +* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. +* +* DESCRIPTION: +* This routine used to free buffers attached to the Tx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of TX queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. +* +* RETURN: +* MV_EMPTY - There is no more buffers in this queue. +* MV_OK - Buffer detached from the queue and pPktInfo structure +* filled with relevant information. +* +*******************************************************************************/ +MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + MV_PKT_INFO* pPktInfo; + ETH_TX_DESC* pTxDesc; + int port = pPortCtrl->portNo; + + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || + (pQueueCtrl->resource == 0) ) + { + /* Free next descriptor */ + pQueueCtrl->resource++; + pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; + + /* pPktInfo is available only in descriptors which are last descriptors */ + pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; + if (pPktInfo) + pPktInfo->status = pTxDesc->cmdSts; + + pTxDesc->cmdSts = 0x0; + pTxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); + + pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); + + if (pPktInfo) + if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) + return pPktInfo; + } + MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + return NULL; +} + + + +/******************************************************************************* +* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. +* +* DESCRIPTION: +* This routine used to free buffers attached to the Rx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_EMPTY - There is no more buffers in this queue. +* MV_OK - Buffer detached from the queue and pBufInfo structure +* filled with relevant information. +* +*******************************************************************************/ +MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_RX_DESC* pRxDesc; + MV_PKT_INFO* pPktInfo; + int port = pPortCtrl->portNo; + + pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + if(pQueueCtrl->resource == 0) + { + MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + + return NULL; + } + /* Free next descriptor */ + pQueueCtrl->resource--; + pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; + pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; + + pPktInfo->status = pRxDesc->cmdSts; + pRxDesc->cmdSts = 0x0; + pRxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); + + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); + return pPktInfo; +} + + +/******************************************************************************/ +/* Port Configuration functions */ +/******************************************************************************/ +/******************************************************************************* +* mvEthMruGet - Get MRU configuration for Max Rx packet size. +* +* INPUT: +* MV_U32 maxRxPktSize - max packet size. +* +* RETURN: MV_U32 - MRU configuration. +* +*******************************************************************************/ +static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) +{ + MV_U32 portSerialCtrlReg = 0; + + if(maxRxPktSize > 9192) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; + else if(maxRxPktSize > 9022) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; + else if(maxRxPktSize > 1552) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; + else if(maxRxPktSize > 1522) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; + else if(maxRxPktSize > 1518) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; + else + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; + + return portSerialCtrlReg; +} + +/******************************************************************************* +* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path +* +* DESCRIPTION: +* This routine sets the RX coalescing interrupt mechanism parameter. +* This parameter is a timeout counter, that counts in 64 tClk +* chunks, that when timeout event occurs a maskable interrupt occurs. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the required number is in micro seconds. +* +* INPUT: +* void* pPortHndl - Ethernet Port handler. +* MV_U32 uSec - Number of micro seconds between +* RX interrupts +* +* RETURN: +* None. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); + MV_U32 portSdmaCfgReg; + + portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); + portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; + + portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); + +#if (MV_ETH_VERSION >= 2) + /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ + if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) + portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; +#endif /* MV_ETH_VERSION >= 2 */ + + MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); + return coal; +} + +/******************************************************************************* +* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path +* +* DESCRIPTION: +* This routine sets the TX coalescing interrupt mechanism parameter. +* This parameter is a timeout counter, that counts in 64 tClk +* chunks, that when timeout event occurs a maskable interrupt +* occurs. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the required number is in micro seconds. +* +* INPUT: +* void* pPortHndl - Ethernet Port handler. +* MV_U32 uSec - Number of micro seconds between +* RX interrupts +* +* RETURN: +* None. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +*******************************************************************************/ +MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); + MV_U32 regVal; + + regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); + regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; + regVal |= ETH_TX_INTR_COAL_MASK(coal); + + /* Set TX Coalescing mechanism */ + MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); + return coal; +} + +/******************************************************************************* +* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds +* +* DESCRIPTION: +* This routine gets the RX and TX coalescing interrupt values. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the returned numbers are in micro seconds. +* +* INPUTs: +* void* pPortHndl - Ethernet Port handler. +* +* OUTPUTs: +* MV_U32* pRxCoal - Number of micro seconds between RX interrupts +* MV_U32* pTxCoal - Number of micro seconds between TX interrupts +* +* RETURN: +* MV_STATUS MV_OK - success +* Others - failure. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +*******************************************************************************/ +MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) +{ + MV_U32 regVal, coal, usec; + + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + /* get TX Coalescing */ + regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); + coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); + + usec = (coal * 64) / (mvBoardTclkGet() / 1000000); + if(pTxCoal != NULL) + *pTxCoal = usec; + + /* Get RX Coalescing */ + regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); + coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); + +#if (MV_ETH_VERSION >= 2) + if(regVal & ETH_RX_INTR_COAL_MSB_MASK) + { + /* Add MSB */ + coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); + } +#endif /* MV_ETH_VERSION >= 2 */ + + usec = (coal * 64) / (mvBoardTclkGet() / 1000000); + if(pRxCoal != NULL) + *pRxCoal = usec; + + return MV_OK; +} + +/******************************************************************************* +* mvEthMaxRxSizeSet - +* +* DESCRIPTION: +* Change maximum receive size of the port. This configuration will take place +* after next call of ethPortSetDefaults() function. +* +* INPUT: +* +* RETURN: +*******************************************************************************/ +MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + MV_U32 portSerialCtrlReg; + + pPortCtrl->portConfig.maxRxPktSize = maxRxSize; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); + portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; + portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); + + return MV_OK; +} + + +/******************************************************************************/ +/* MAC Filtering functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port +* +* DESCRIPTION: +* This routine used to free buffers attached to the Rx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* MV_BOOL isPromisc - Promiscous mode +* MV_TRUE - accept all Broadcast, Multicast +* and Unicast packets +* MV_FALSE - accept all Broadcast, +* specially added Multicast and +* single Unicast packets +* +* RETURN: MV_STATUS MV_OK - Success, Other - Failure +* +*******************************************************************************/ +MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + int queue; + MV_U32 portCfgReg; + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + /* Set / Clear UPM bit in port configuration register */ + if(isPromisc) + { + /* Accept all multicast packets to RX default queue */ + queue = pPortCtrl->portConfig.rxDefQ; + portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; + memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); + MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); + MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); + } + else + { + /* Reject all Multicast addresses */ + queue = -1; + portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; + /* Clear all mcastCount */ + memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); + } + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + /* Set Special Multicast and Other Multicast tables */ + mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); + mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); + ethSetUcastTable(pPortCtrl->portNo, queue); + + return MV_OK; +} + +/******************************************************************************* +* mvEthMacAddrSet - This function Set the port Unicast address. +* +* DESCRIPTION: +* This function Set the port Ethernet MAC address. This address +* will be used to send Pause frames if enabled. Packets with this +* address will be accepted and dispatched to default RX queue +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler. +* char* pAddr - Address to be set +* +* RETURN: MV_STATUS +* MV_OK - Success, Other - Faulure +* +*******************************************************************************/ +MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + unsigned int macH; + unsigned int macL; + + if(queue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); + return MV_BAD_PARAM; + } + + if(queue != -1) + { + macL = (pAddr[4] << 8) | (pAddr[5]); + macH = (pAddr[0] << 24)| (pAddr[1] << 16) | + (pAddr[2] << 8) | (pAddr[3] << 0); + + MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); + MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); + } + + /* Accept frames of this address */ + ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); + + return MV_OK; +} + +/******************************************************************************* +* mvEthMacAddrGet - This function returns the port Unicast address. +* +* DESCRIPTION: +* This function returns the port Ethernet MAC address. +* +* INPUT: +* int portNo - Ethernet port number. +* char* pAddr - Pointer where address will be written to +* +* RETURN: MV_STATUS +* MV_OK - Success, Other - Faulure +* +*******************************************************************************/ +MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) +{ + unsigned int macH; + unsigned int macL; + + if(pAddr == NULL) + { + mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); + return MV_BAD_PARAM; + } + + macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); + macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); + pAddr[0] = (macH >> 24) & 0xff; + pAddr[1] = (macH >> 16) & 0xff; + pAddr[2] = (macH >> 8) & 0xff; + pAddr[3] = macH & 0xff; + pAddr[4] = (macL >> 8) & 0xff; + pAddr[5] = macL & 0xff; + + return MV_OK; +} + +/******************************************************************************* +* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. +* +* DESCRIPTION: +* +* INPUT: +* MV_U8* pAddr - Address to calculate CRC-8 +* +* RETURN: MV_U8 - CRC-8 of this MAC address +* +*******************************************************************************/ +MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) +{ + unsigned int macH; + unsigned int macL; + int macArray[48]; + int crc[8]; + int i; + unsigned char crcResult = 0; + + /* Calculate CRC-8 out of the given address */ + macH = (pAddr[0] << 8) | (pAddr[1]); + macL = (pAddr[2] << 24)| (pAddr[3] << 16) | + (pAddr[4] << 8) | (pAddr[5] << 0); + + for(i=0; i<32; i++) + macArray[i] = (macL >> i) & 0x1; + + for(i=32; i<48; i++) + macArray[i] = (macH >> (i - 32)) & 0x1; + + crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ + macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ + macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ + macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ + macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; + + crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ + macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ + macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ + macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ + macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ + macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ + macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; + + crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ + macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ + macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ + macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ + macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ + macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; + + crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ + macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ + macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ + macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ + macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ + macArray[3] ^ macArray[2] ^ macArray[1]; + + crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ + macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ + macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ + macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ + macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ + macArray[3] ^ macArray[2]; + + crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ + macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ + macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ + macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ + macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ + macArray[4] ^ macArray[3]; + + crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ + macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ + macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ + macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ + macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ + macArray[4]; + + crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ + macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ + macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ + macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ + macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; + + for(i=0; i<8; i++) + crcResult = crcResult | (crc[i] << i); + + return crcResult; +} +/******************************************************************************* +* mvEthMcastAddrSet - Multicast address settings. +* +* DESCRIPTION: +* This API controls the MV device MAC multicast support. +* The MV device supports multicast using two tables: +* 1) Special Multicast Table for MAC addresses of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* In this case, the function calls ethPortSmcAddr() routine to set the +* Special Multicast Table. +* 2) Other Multicast Table for multicast of another type. A CRC-8bit +* is used as an index to the Other Multicast Table entries in the +* DA-Filter table. +* In this case, the function calculates the CRC-8bit value and calls +* ethPortOmcAddr() routine to set the Other Multicast Table. +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler. +* MV_U8* pAddr - Address to be set +* int queue - RX queue to capture all packets with this +* Multicast MAC address. +* -1 means delete this Multicast address. +* +* RETURN: MV_STATUS +* MV_TRUE - Success, Other - Failure +* +*******************************************************************************/ +MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + unsigned char crcResult = 0; + + if(queue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", + pPortCtrl->portNo, queue); + return MV_BAD_PARAM; + } + + if((pAddr[0] == 0x01) && + (pAddr[1] == 0x00) && + (pAddr[2] == 0x5E) && + (pAddr[3] == 0x00) && + (pAddr[4] == 0x00)) + { + ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); + } + else + { + crcResult = mvEthMcastCrc8Get(pAddr); + + /* Check Add counter for this CRC value */ + if(queue == -1) + { + if(pPortCtrl->mcastCount[crcResult] == 0) + { + mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", + pPortCtrl->portNo, (unsigned)crcResult); + return MV_NO_SUCH; + } + + pPortCtrl->mcastCount[crcResult]--; + if(pPortCtrl->mcastCount[crcResult] != 0) + { + mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", + pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], + (unsigned)crcResult); + return MV_NO_CHANGE; + } + } + else + { + pPortCtrl->mcastCount[crcResult]++; + if(pPortCtrl->mcastCount[crcResult] > 1) + { + mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", + pPortCtrl->portNo, (unsigned)crcResult); + return MV_NO_CHANGE; + } + } + ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); + } + return MV_OK; +} + +/******************************************************************************* +* ethSetUcastTable - Unicast address settings. +* +* DESCRIPTION: +* Set all entries in the Unicast MAC Table queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +static void ethSetUcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if(queue == -1) + { + regValue = 0; + } + else + { + regValue = (((0x01 | (queue<<1)) << 0) | + ((0x01 | (queue<<1)) << 8) | + ((0x01 | (queue<<1)) << 16) | + ((0x01 | (queue<<1)) << 24)); + } + + for (offset=0; offset<=0xC; offset+=4) + MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); +} + +/******************************************************************************* +* mvEthSetSpecialMcastTable - Special Multicast address settings. +* +* DESCRIPTION: +* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if(queue == -1) + { + regValue = 0; + } + else + { + regValue = (((0x01 | (queue<<1)) << 0) | + ((0x01 | (queue<<1)) << 8) | + ((0x01 | (queue<<1)) << 16) | + ((0x01 | (queue<<1)) << 24)); + } + + for (offset=0; offset<=0xFC; offset+=4) + { + MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + + offset), regValue); + } +} + +/******************************************************************************* +* mvEthSetOtherMcastTable - Other Multicast address settings. +* +* DESCRIPTION: +* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if(queue == -1) + { + regValue = 0; + } + else + { + regValue = (((0x01 | (queue<<1)) << 0) | + ((0x01 | (queue<<1)) << 8) | + ((0x01 | (queue<<1)) << 16) | + ((0x01 | (queue<<1)) << 24)); + } + + for (offset=0; offset<=0xFC; offset+=4) + { + MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + + offset), regValue); + } +} + +/******************************************************************************* +* ethSetUcastAddr - This function Set the port unicast address table +* +* DESCRIPTION: +* This function locates the proper entry in the Unicast table for the +* specified MAC nibble and sets its properties according to function +* parameters. +* +* INPUT: +* int ethPortNum - Port number. +* MV_U8 lastNibble - Unicast MAC Address last nibble. +* int queue - Rx queue number for this MAC address. +* value "-1" means remove address +* +* OUTPUT: +* This function add/removes MAC addresses from the port unicast address +* table. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) +{ + unsigned int unicastReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the Unicast table entry */ + lastNibble = (0xf & lastNibble); + tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ + regOffset = lastNibble % 4; /* Entry offset within the above register */ + + + unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + + tblOffset)); + + + if(queue == -1) + { + /* Clear accepts frame bit at specified unicast DA table entry */ + unicastReg &= ~(0xFF << (8*regOffset)); + } + else + { + unicastReg &= ~(0xFF << (8*regOffset)); + unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); + } + MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), + unicastReg); + + return MV_TRUE; +} + +/******************************************************************************* +* ethSetSpecialMcastAddr - Special Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device special MAC multicast support. +* The Special Multicast Table for MAC addresses supports MAC of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* This function set the Special Multicast Table appropriate entry +* according to the argument given. +* +* INPUT: +* int ethPortNum Port number. +* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). +* int queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) +{ + unsigned int smcTableReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the SMC table entry */ + tblOffset = (lastByte / 4); /* Register offset from SMC table base */ + regOffset = lastByte % 4; /* Entry offset within the above register */ + + smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); + + if(queue == -1) + { + /* Clear accepts frame bit at specified Special DA table entry */ + smcTableReg &= ~(0xFF << (8 * regOffset)); + } + else + { + smcTableReg &= ~(0xFF << (8 * regOffset)); + smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); + } + MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + + tblOffset*4), smcTableReg); + + return MV_TRUE; +} + +/******************************************************************************* +* ethSetOtherMcastAddr - Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device Other MAC multicast support. +* The Other Multicast Table is used for multicast of another type. +* A CRC-8bit is used as an index to the Other Multicast Table entries +* in the DA-Filter table. +* The function gets the CRC-8bit value from the calling routine and +* set the Other Multicast Table appropriate entry according to the +* CRC-8 argument given. +* +* INPUT: +* int ethPortNum Port number. +* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). +* int queue Rx queue number for this MAC address. +* +* OUTPUT: +* See description. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) +{ + unsigned int omcTableReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the OMC table entry */ + tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ + regOffset = crc8 % 4; /* Entry offset within the above register */ + + omcTableReg = MV_REG_READ( + (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); + + if(queue == -1) + { + /* Clear accepts frame bit at specified Other DA table entry */ + omcTableReg &= ~(0xFF << (8 * regOffset)); + } + else + { + omcTableReg &= ~(0xFF << (8 * regOffset)); + omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); + } + + MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), + omcTableReg); + + return MV_TRUE; +} + + +/******************************************************************************/ +/* MIB Counters functions */ +/******************************************************************************/ + + +/******************************************************************************* +* mvEthMibCounterRead - Read a MIB counter +* +* DESCRIPTION: +* This function reads a MIB counter of a specific ethernet port. +* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or +* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, +* so pHigh32 pointer should not be NULL in this case. +* +* INPUT: +* int ethPortNum - Ethernet Port number. +* unsigned int mibOffset - MIB counter offset. +* +* OUTPUT: +* MV_U32* pHigh32 - pointer to place where 32 most significant bits +* of the counter will be stored. +* +* RETURN: +* 32 low sgnificant bits of MIB counter value. +* +*******************************************************************************/ +MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, + MV_U32* pHigh32) +{ + int portNo; + MV_U32 valLow32, valHigh32; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + + portNo = pPortCtrl->portNo; + + valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); + + /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ + /* of a 64-bit MIB Counter. */ + if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || + (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) + { + valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); + if(pHigh32 != NULL) + *pHigh32 = valHigh32; + } + return valLow32; +} + +/******************************************************************************* +* mvEthMibCountersClear - Clear all MIB counters +* +* DESCRIPTION: +* This function clears all MIB counters +* +* INPUT: +* int ethPortNum - Ethernet Port number. +* +* +* RETURN: void +* +*******************************************************************************/ +void mvEthMibCountersClear(void* pPortHandle) +{ + int i, portNo; + unsigned int dummy; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + + portNo = pPortCtrl->portNo; + + /* Perform dummy reads from MIB counters */ + for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) + { + mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); + return -1; + } + regIdx = mvOsDivide(tos>>2, 10); + regOffs = mvOsReminder(tos>>2, 10); + + regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); + rxq = (regValue >> (regOffs*3)); + rxq &= 0x7; + + return rxq; +} + +/******************************************************************************* +* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue +* +* DESCRIPTION: +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int tos - TOS value in the IP header of the packet +* int rxq - RX Queue for packets with the configured TOS value +* Negative value (-1) means no special processing for these packets, +* so they will be processed as regular packets. +* +* RETURN: MV_STATUS +*******************************************************************************/ +MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) +{ + MV_U32 regValue; + int regIdx, regOffs; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + + if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) + { + mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); + return MV_BAD_PARAM; + } + if(tos > 0xFF) + { + mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); + return MV_BAD_PARAM; + } + regIdx = mvOsDivide(tos>>2, 10); + regOffs = mvOsReminder(tos>>2, 10); + + regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); + regValue &= ~(0x7 << (regOffs*3)); + regValue |= (rxq << (regOffs*3)); + + MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); + return MV_OK; +} + +/******************************************************************************* +* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with +* special priority bits [0-2] +* +* DESCRIPTION: +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int bpduQueue - Special queue to capture VLAN tagged packets with special +* priority. +* Negative value (-1) means no special processing for these packets, +* so they will be processed as regular packets. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 vlanPrioReg; + + if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); + return MV_BAD_PARAM; + } + if(vlanPrio >= 8) + { + mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); + return MV_BAD_PARAM; + } + + vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); + vlanPrioReg &= ~(0x7 << (vlanPrio*3)); + vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); + MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. +* +* DESCRIPTION: +* This function defines processing of BPDU packets. +* BPDU packets can be accepted and captured to one of RX queues +* or can be processing as regular Multicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int bpduQueue - Special queue to capture BPDU packets (DA is equal to +* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, +* except for the Flow-Control Pause packets). +* Negative value (-1) means no special processing for BPDU, +* packets so they will be processed as regular Multicast packets. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + MV_U32 portCfgExtReg; + + if(bpduQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); + return MV_BAD_PARAM; + } + + portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + if(bpduQueue >= 0) + { + pPortCtrl->portConfig.rxBpduQ = bpduQueue; + + portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; + } + else + { + pPortCtrl->portConfig.rxBpduQ = -1; + /* no special processing for BPDU packets */ + portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); + } + + MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthArpRxQueue - Configure RX queue to capture ARP packets. +* +* DESCRIPTION: +* This function defines processing of ARP (type=0x0806) packets. +* ARP packets can be accepted and captured to one of RX queues +* or can be processed as other Broadcast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int arpQueue - Special queue to capture ARP packets (type=0x806). +* Negative value (-1) means discard ARP packets +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + + if(arpQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); + return MV_BAD_PARAM; + } + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if(arpQueue >= 0) + { + pPortCtrl->portConfig.rxArpQ = arpQueue; + portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); + + portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); + } + else + { + pPortCtrl->portConfig.rxArpQ = -1; + portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. +* +* DESCRIPTION: +* This function defines processing of TCP packets. +* TCP packets can be accepted and captured to one of RX queues +* or can be processed as regular Unicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int tcpQueue - Special queue to capture TCP packets. Value "-1" +* means no special processing for TCP packets, +* so they will be processed as regular +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + + if(tcpQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); + return MV_BAD_PARAM; + } + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if(tcpQueue >= 0) + { + pPortCtrl->portConfig.rxTcpQ = tcpQueue; + portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); + + portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; + } + else + { + pPortCtrl->portConfig.rxTcpQ = -1; + portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. +* +* DESCRIPTION: +* This function defines processing of UDP packets. +* TCP packets can be accepted and captured to one of RX queues +* or can be processed as regular Unicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int udpQueue - Special queue to capture UDP packets. Value "-1" +* means no special processing for UDP packets, +* so they will be processed as regular +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + + if(udpQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); + return MV_BAD_PARAM; + } + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if(udpQueue >= 0) + { + pPortCtrl->portConfig.rxUdpQ = udpQueue; + portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); + + portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; + } + else + { + pPortCtrl->portConfig.rxUdpQ = -1; + portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + + +/******************************************************************************/ +/* Speed, Duplex, FlowControl routines */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. +* +* DESCRIPTION: +* This function configure the port to work with desirable Duplex and Speed. +* Changing of these parameters are allowed only when port is disabled. +* This function disable the port if was enabled, change duplex and speed +* and, enable the port back if needed. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* ETH_PORT_SPEED speed - Speed of the port. +* ETH_PORT_SPEED duplex - Duplex of the port. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. +* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) +* is not valid +* +*******************************************************************************/ +MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, + MV_ETH_PORT_DUPLEX duplex) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 portSerialCtrlReg; + + if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + /* Check validity */ + if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) + return MV_BAD_PARAM; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + /* Set Speed */ + switch(speed) + { + case MV_ETH_SPEED_AN: + portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; + break; + + case MV_ETH_SPEED_10: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; + portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; + break; + + case MV_ETH_SPEED_100: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; + portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; + break; + + case MV_ETH_SPEED_1000: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); + return MV_BAD_VALUE; + } + /* Set duplex */ + switch(duplex) + { + case MV_ETH_DUPLEX_AN: + portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + break; + + case MV_ETH_DUPLEX_HALF: + portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; + break; + + case MV_ETH_DUPLEX_FULL: + portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); + return MV_BAD_VALUE; + } + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthFlowCtrlSet - Set Flow Control of the port. +* +* DESCRIPTION: +* This function configure the port to work with desirable Duplex and +* Speed. Changing of these parameters are allowed only when port is +* disabled. This function disable the port if was enabled, change +* duplex and speed and, enable the port back if needed. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_ETH_PORT_FC flowControl - Flow control of the port. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_VALUE - Value flowControl parameters is not valid +* +*******************************************************************************/ +MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 portSerialCtrlReg; + + if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + switch(flowControl) + { + case MV_ETH_FC_AN_ADV_DIS: + portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; + break; + + case MV_ETH_FC_AN_ADV_SYM: + portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; + break; + + case MV_ETH_FC_DISABLE: + portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; + break; + + case MV_ETH_FC_ENABLE: + portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); + return MV_BAD_VALUE; + } + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthHeaderModeSet - Set port header mode. +* +* DESCRIPTION: +* This function configures the port to work in Marvell-Header mode. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_NOT_SUPPORTED- Feature not supported. +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. +* +*******************************************************************************/ +MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 mvHeaderReg; + MV_U32 numRxQ = MV_ETH_RX_Q_NUM; + + if((port < 0) || (port >= mvCtrlEthMaxPortGet())) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); + /* Disable header mode. */ + mvHeaderReg &= ~ETH_MVHDR_EN_MASK; + + if(headerMode != MV_ETH_DISABLE_HEADER_MODE) + { + /* Enable Header mode. */ + mvHeaderReg |= ETH_MVHDR_EN_MASK; + + /* Clear DA-Prefix & MHMask fields.*/ + mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); + + if(numRxQ > 1) + { + switch (headerMode) + { + case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; + break; + case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; + break; + case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; + break; + default: + break; + } + + switch (numRxQ) + { + case (4): + mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; + break; + case (8): + mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; + break; + default: + break; + } + } + } + + MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); + + return MV_OK; +} + +#if (MV_ETH_VERSION >= 4) +/******************************************************************************* +* mvEthEjpModeSet - Enable / Disable EJP policy for TX. +* +* DESCRIPTION: +* This function +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_BOOL TRUE - enable EJP mode +* FALSE - disable EJP mode +* +* OUTPUT: MV_STATUS +* MV_OK - Success +* Other - Failure +* +* RETURN: None. +* +*******************************************************************************/ +MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + + if((port < 0) || (port >= mvCtrlEthMaxPortGet())) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + pPortCtrl->portConfig.ejpMode = mode; + if(mode) + { + /* EJP enabled */ + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); + } + else + { + /* EJP disabled */ + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); + } + mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", + port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), + MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); + + return MV_OK; +} +#endif /* MV_ETH_VERSION >= 4 */ + +/******************************************************************************* +* mvEthStatusGet - Get major properties of the port . +* +* DESCRIPTION: +* This function get major properties of the port (link, speed, duplex, +* flowControl, etc) and return them using the single structure. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* +* OUTPUT: +* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status +* will be placed. +* +* RETURN: None. +* +*******************************************************************************/ +void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + + MV_U32 regValue; + + regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); + + if(regValue & ETH_GMII_SPEED_1000_MASK) + pStatus->speed = MV_ETH_SPEED_1000; + else if(regValue & ETH_MII_SPEED_100_MASK) + pStatus->speed = MV_ETH_SPEED_100; + else + pStatus->speed = MV_ETH_SPEED_10; + + if(regValue & ETH_LINK_UP_MASK) + pStatus->isLinkUp = MV_TRUE; + else + pStatus->isLinkUp = MV_FALSE; + + if(regValue & ETH_FULL_DUPLEX_MASK) + pStatus->duplex = MV_ETH_DUPLEX_FULL; + else + pStatus->duplex = MV_ETH_DUPLEX_HALF; + + + if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) + pStatus->flowControl = MV_ETH_FC_ENABLE; + else + pStatus->flowControl = MV_ETH_FC_DISABLE; +} + + +/******************************************************************************/ +/* PHY Control Functions */ +/******************************************************************************/ + + +/******************************************************************************* +* mvEthPhyAddrSet - Set the ethernet port PHY address. +* +* DESCRIPTION: +* This routine set the ethernet port PHY address according to given +* parameter. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int phyAddr - PHY address +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + unsigned int regData; + + regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); + + regData &= ~ETH_PHY_ADDR_MASK; + regData |= phyAddr; + + MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); + + return; +} + +/******************************************************************************* +* mvEthPhyAddrGet - Get the ethernet port PHY address. +* +* DESCRIPTION: +* This routine returns the given ethernet port PHY address. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* +* +* RETURN: int - PHY address. +* +*******************************************************************************/ +int mvEthPhyAddrGet(void* pPortHandle) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + unsigned int regData; + + regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); + + return ((regData >> (5 * port)) & 0x1f); +} + +/******************************************************************************/ +/* Descriptor handling Functions */ +/******************************************************************************/ + +/******************************************************************************* +* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. +* +* DESCRIPTION: +* This function prepares a Rx chained list of descriptors and packet +* buffers in a form of a ring. The routine must be called after port +* initialization routine and before port start routine. +* The Ethernet SDMA engine uses CPU bus addresses to access the various +* devices in the system (i.e. DRAM). This function uses the ethernet +* struct 'virtual to physical' routine (set by the user) to set the ring +* with physical addresses. +* +* INPUT: +* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. +* int rxQueue Number of Rx queue. +* int rxDescNum Number of Rx descriptors +* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. +* +* OUTPUT: +* The routine updates the Ethernet port control struct with information +* regarding the Rx descriptors and buffers. +* +* RETURN: None +* +*******************************************************************************/ +static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) +{ + ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; + int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; + ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; + + /* Make sure descriptor address is cache line size aligned */ + pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + pRxDesc = (ETH_RX_DESC*)pRxDescBase; + pRxPrevDesc = pRxDesc; + + /* initialize the Rx descriptors ring */ + for (ix=0; ixbufSize = 0x0; + pRxDesc->byteCnt = 0x0; + pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pRxDesc->bufPtr = 0x0; + pRxDesc->returnInfo = 0x0; + pRxPrevDesc = pRxDesc; + if(ix == (rxDescNum-1)) + { + /* Closing Rx descriptors ring */ + pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); + } + else + { + pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); + pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); + } + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); + } + + pQueueCtrl->pCurrentDescr = pRxDescBase; + pQueueCtrl->pUsedDescr = pRxDescBase; + + pQueueCtrl->pFirstDescr = pRxDescBase; + pQueueCtrl->pLastDescr = pRxDesc; + pQueueCtrl->resource = 0; +} + +void ethResetRxDescRing(void* pPortHndl, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; + ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; + + pQueueCtrl->resource = 0; + if(pQueueCtrl->pFirstDescr != NULL) + { + while(MV_TRUE) + { + pRxDesc->bufSize = 0x0; + pRxDesc->byteCnt = 0x0; + pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pRxDesc->bufPtr = 0x0; + pRxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); + if( (void*)pRxDesc == pQueueCtrl->pLastDescr) + break; + pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); + } + pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; + pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; + + /* Update RX Command register */ + pPortCtrl->portRxQueueCmdReg |= (1 << queue); + + /* update HW */ + MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + } + else + { + /* Update RX Command register */ + pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); + + /* update HW */ + MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); + } +} + +/******************************************************************************* +* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. +* +* DESCRIPTION: +* This function prepares a Tx chained list of descriptors and packet +* buffers in a form of a ring. The routine must be called after port +* initialization routine and before port start routine. +* The Ethernet SDMA engine uses CPU bus addresses to access the various +* devices in the system (i.e. DRAM). This function uses the ethernet +* struct 'virtual to physical' routine (set by the user) to set the ring +* with physical addresses. +* +* INPUT: +* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. +* int txQueue Number of Tx queue. +* int txDescNum Number of Tx descriptors +* int txBuffSize Size of Tx buffer +* MV_U8* pTxDescBase Tx descriptors memory area base addr. +* +* OUTPUT: +* The routine updates the Ethernet port control struct with information +* regarding the Tx descriptors and buffers. +* +* RETURN: None. +* +*******************************************************************************/ +static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) +{ + ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; + int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; + ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; + + /* Make sure descriptor address is cache line size aligned */ + pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + pTxDesc = (ETH_TX_DESC*)pTxDescBase; + pTxPrevDesc = pTxDesc; + + /* initialize the Tx descriptors ring */ + for (ix=0; ixbyteCnt = 0x0000; + pTxDesc->L4iChk = 0x0000; + pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pTxDesc->bufPtr = 0x0; + pTxDesc->returnInfo = 0x0; + + pTxPrevDesc = pTxDesc; + + if(ix == (txDescNum-1)) + { + /* Closing Tx descriptors ring */ + pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); + } + else + { + pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); + pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); + } + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); + } + + pQueueCtrl->pCurrentDescr = pTxDescBase; + pQueueCtrl->pUsedDescr = pTxDescBase; + + pQueueCtrl->pFirstDescr = pTxDescBase; + pQueueCtrl->pLastDescr = pTxDesc; + /* Leave one TX descriptor out of use */ + pQueueCtrl->resource = txDescNum - 1; +} + +void ethResetTxDescRing(void* pPortHndl, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; + ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; + + pQueueCtrl->resource = 0; + if(pQueueCtrl->pFirstDescr != NULL) + { + while(MV_TRUE) + { + pTxDesc->byteCnt = 0x0000; + pTxDesc->L4iChk = 0x0000; + pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pTxDesc->bufPtr = 0x0; + pTxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); + pQueueCtrl->resource++; + if( (void*)pTxDesc == pQueueCtrl->pLastDescr) + break; + pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); + } + /* Leave one TX descriptor out of use */ + pQueueCtrl->resource--; + pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; + pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; + + /* Update TX Command register */ + pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); + /* update HW */ + MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + } + else + { + /* Update TX Command register */ + pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); + /* update HW */ + MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); + } +} + +/******************************************************************************* +* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. +* +* DESCRIPTION: +* This function allocates memory for RX and TX descriptors. +* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. +* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. +* +* INPUT: +* int size - size of memory should be allocated. +* +* RETURN: None +* +*******************************************************************************/ +static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, + MV_ULONG* pPhysAddr, MV_U32 *memHandle) +{ + MV_U8* pVirt; + +#if defined(ETH_DESCR_IN_SRAM) + if(ethDescInSram == MV_TRUE) + pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); + else +#endif /* ETH_DESCR_IN_SRAM */ + { +#ifdef ETH_DESCR_UNCACHED + pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, + pPhysAddr,memHandle); +#else + pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, + pPhysAddr, memHandle); +#endif /* ETH_DESCR_UNCACHED */ + } + memset(pVirt, 0, descSize); + + return pVirt; +} + +/******************************************************************************* +* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. +* +* DESCRIPTION: +* This function frees memory allocated for RX and TX descriptors. +* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. +* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. +* +* INPUT: +* void* pVirtAddr - virtual pointer to memory allocated for RX and TX +* desriptors. +* +* RETURN: None +* +*******************************************************************************/ +void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) +{ + if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) + return; + +#if defined(ETH_DESCR_IN_SRAM) + if( ethDescInSram ) + { + mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); + return; + } +#endif /* ETH_DESCR_IN_SRAM */ + +#ifdef ETH_DESCR_UNCACHED + mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, + pDescBuf->bufVirtPtr,pDescBuf->memHandle); +#else + mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, + pDescBuf->bufVirtPtr,pDescBuf->memHandle); +#endif /* ETH_DESCR_UNCACHED */ +} + +/******************************************************************************/ +/* Other Functions */ +/******************************************************************************/ + +void mvEthPortPowerUp(int port) +{ + MV_U32 regVal; + + /* MAC Cause register should be cleared */ + MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); + + if (mvBoardIsPortInSgmii(port)) + mvEthPortSgmiiConfig(port); + + /* Cancel Port Reset */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + regVal &= (~ETH_PORT_RESET_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); + while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); +} + +void mvEthPortPowerDown(int port) +{ + MV_U32 regVal; + + /* Port must be DISABLED */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + if( (regVal & ETH_PORT_ENABLE_MASK) != 0) + { + mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", + port, regVal); + return; + } + + /* Port Reset (Read after write the register as a precaution) */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); + while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); +} + +static void mvEthPortSgmiiConfig(int port) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + + regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); + regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); +} + + + + + + + + + diff --git a/board/mv_feroceon/mv_hal/eth/gbe/mvEthDebug.c b/board/mv_feroceon/mv_hal/eth/gbe/mvEthDebug.c new file mode 100644 index 0000000..f533475 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/gbe/mvEthDebug.c @@ -0,0 +1,748 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEthDebug.c - Source file for user friendly debug functions +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvOs.h" +#include "mvCommon.h" +#include "mvTypes.h" +#include "mv802_3.h" +#include "mvDebug.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "eth-phy/mvEthPhy.h" +#include "eth/mvEth.h" +#include "eth/gbe/mvEthDebug.h" + +/* #define mvOsPrintf printf */ + +void mvEthPortShow(void* pHndl); +void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); + +/******************************************************************************/ +/* Debug functions */ +/******************************************************************************/ +void ethRxCoal(int port, int usec) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthRxCoalSet(pHndl, usec); + } +} + +void ethTxCoal(int port, int usec) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthTxCoalSet(pHndl, usec); + } +} + +#if (MV_ETH_VERSION >= 4) +void ethEjpModeSet(int port, int mode) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthEjpModeSet(pHndl, mode); + } +} +#endif /* (MV_ETH_VERSION >= 4) */ + +void ethBpduRxQ(int port, int bpduQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthBpduRxQueue(pHndl, bpduQueue); + } +} + +void ethArpRxQ(int port, int arpQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthArpRxQueue(pHndl, arpQueue); + } +} + +void ethTcpRxQ(int port, int tcpQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthTcpRxQueue(pHndl, tcpQueue); + } +} + +void ethUdpRxQ(int port, int udpQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthUdpRxQueue(pHndl, udpQueue); + } +} + +void ethTxPolicyRegs(int port) +{ + int queue; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); + + if(pPortCtrl == NULL) + { + return; + } + mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", + port, pPortCtrl->portConfig.ejpMode); + for(queue=0; queuetxQueueConfig[queue].descrNum > 0) + mvOsPrintf("%d, ", queue); + } + mvOsPrintf("\n"); + + mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); + + mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", + ETH_TX_QUEUE_COMMAND_REG(port), + MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); + + mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", + ETH_TX_FIXED_PRIO_CFG_REG(port), + MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); + + mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_RATE_CFG_REG(port), + MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); + + mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", + ETH_MAX_TRANSMIT_UNIT_REG(port), + MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); + + mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_BUCKET_SIZE_REG(port), + MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); + + mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_BUCKET_COUNT_REG(port), + MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); + + for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), + ((macH >> 8) & 0xff), (macH & 0xff), + ((macL >> 8) & 0xff), (macL & 0xff) ); + + for (i=0; i<4; i++) + { + unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); + for(j=0; j<4; j++) + { + MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; + + mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, + (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); + } + } +} + +void ethMcastAdd(int port, char* macStr, int queue) +{ + void* pHndl; + MV_U8 macAddr[MV_MAC_ADDR_SIZE]; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvMacStrToHex(macStr, macAddr); + mvEthMcastAddrSet(pHndl, macAddr, queue); + } +} + +void ethPortMcast(int port) +{ + int tblIdx, regIdx; + MV_U32 regVal; + + mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", + port); + + for(tblIdx=0; tblIdx<(256/4); tblIdx++) + { + regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); + for(regIdx=0; regIdx<4; regIdx++) + { + if((regVal & (0x01 << (regIdx*8))) != 0) + { + mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", + tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); + } + } + } + mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); + for(tblIdx=0; tblIdx<(256/4); tblIdx++) + { + regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); + for(regIdx=0; regIdx<4; regIdx++) + { + if((regVal & (0x01 << (regIdx*8))) != 0) + { + mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", + tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); + } + } + } +} + + +/* Print status of Ethernet port */ +void mvEthPortShow(void* pHndl) +{ + MV_U32 regValue, rxCoal, txCoal; + int speed, queue, port; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; + + port = pPortCtrl->portNo; + + regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); + + mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", + port, ETH_PORT_STATUS_REG(port), regValue); + + mvOsPrintf("descInSram=%d, descSwCoher=%d\n", + ethDescInSram, ethDescSwCoher); + + if(regValue & ETH_GMII_SPEED_1000_MASK) + speed = 1000; + else if(regValue & ETH_MII_SPEED_100_MASK) + speed = 100; + else + speed = 10; + + mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); + + /* Link, Speed, Duplex, FlowControl */ + mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", + (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", + speed, + (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", + (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); + + mvOsPrintf("\n"); + + mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", + rxCoal, txCoal); + + mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", + pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, + pPortCtrl->portConfig.rxBpduQ, + pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); + + /* Print all RX and TX queues */ + for(queue=0; queuerxQueue[queue].pFirstDescr, + mvEthRxResourceGet(pPortCtrl, queue) ); + } + mvOsPrintf("\n"); + for(queue=0; queuetxQueue[queue].pFirstDescr, + mvEthTxResourceGet(pPortCtrl, queue) ); + } +} + +/* Print RX and TX queue of the Ethernet port */ +void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; + ETH_QUEUE_CTRL *pQueueCtrl; + MV_U32 regValue; + ETH_RX_DESC *pRxDescr; + ETH_TX_DESC *pTxDescr; + int i, port = pPortCtrl->portNo; + + if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) + { + pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); + mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); + + mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", + ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), + MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); + + + if(pQueueCtrl->pFirstDescr != NULL) + { + mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", + (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, + pQueueCtrl->resource); + mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", + (MV_ULONG)pQueueCtrl->pCurrentDescr, + (MV_ULONG)pQueueCtrl->pUsedDescr); + + if(mode == 1) + { + pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; + i = 0; + do + { + mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", + i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), + pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, + (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, + ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); + + ETH_DESCR_INV(pPortCtrl, pRxDescr); + pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); + i++; + } while (pRxDescr != pQueueCtrl->pFirstDescr); + } + } + else + mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); + } + + if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) + { + pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); + mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); + + regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); + mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", + ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); + + if(pQueueCtrl->pFirstDescr != NULL) + { + mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", + (MV_ULONG)pQueueCtrl->pFirstDescr, + (MV_ULONG)pQueueCtrl->pLastDescr, + pQueueCtrl->resource); + mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", + (MV_ULONG)pQueueCtrl->pCurrentDescr, + (MV_ULONG)pQueueCtrl->pUsedDescr); + + if(mode == 1) + { + pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; + i = 0; + do + { + mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", + i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), + pTxDescr->cmdSts, pTxDescr->byteCnt, + (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, + pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); + + ETH_DESCR_INV(pPortCtrl, pTxDescr); + pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); + i++; + } while (pTxDescr != pQueueCtrl->pFirstDescr); + } + } + else + mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); + } +} diff --git a/board/mv_feroceon/mv_hal/eth/gbe/mvEthDebug.h b/board/mv_feroceon/mv_hal/eth/gbe/mvEthDebug.h new file mode 100644 index 0000000..f026f96 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/gbe/mvEthDebug.h @@ -0,0 +1,146 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __MV_ETH_DEBUG_H__ +#define __MV_ETH_DEBUG_H__ + +#if 0 +/* + ** Externs + */ +void ethBpduRxQ(int port, int bpduQueue); +void ethArpRxQ(int port, int bpduQueue); +void ethTcpRxQ(int port, int bpduQueue); +void ethUdpRxQ(int port, int bpduQueue); +void ethMcastAdd(int port, char* macStr, int queue); + +#ifdef INCLUDE_MULTI_QUEUE +void ethRxPolicy( int port); +void ethTxPolicy( int port); +void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); +void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); +void ethRxPolQ(int port, int rxQueue, int rxQuota); +#endif /* INCLUDE_MULTI_QUEUE */ + +void print_egiga_stat(void *sc, unsigned int port); +void ethPortStatus (int port); +void ethPortQueues( int port, int rxQueue, int txQueue, int mode); +void ethPortMcast(int port); +void ethPortRegs(int port); +void ethPortCounters(int port); +void ethPortRmonCounters(int port); +void ethRxCoal(int port, int usec); +void ethTxCoal(int port, int usec); + +void ethRegs(int port); +void ethClearCounters(int port); +void ethUcastSet(int port, char* macStr, int queue); +void ethPortUcastShow(int port); + +#ifdef CONFIG_MV_ETH_HEADER +void run_com_header(const char *buffer); +#endif + +#ifdef INCLUDE_MULTI_QUEUE +void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); +void ethRxPolQ(int port, int queue, int quota); +void ethRxPolicy(int port); +void ethTxPolDef(int port, int txQ, char* headerHexStr); +void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); +void ethTxPolicy(int port); +#endif /* INCLUDE_MULTI_QUEUE */ + +#if (MV_ETH_VERSION >= 4) +void ethEjpModeSet(int port, int mode) +#endif +#endif /* 0 */ + + + + +void ethRxCoal(int port, int usec); +void ethTxCoal(int port, int usec); +#if (MV_ETH_VERSION >= 4) +void ethEjpModeSet(int port, int mode); +#endif /* (MV_ETH_VERSION >= 4) */ + +void ethBpduRxQ(int port, int bpduQueue); +void ethArpRxQ(int port, int arpQueue); +void ethTcpRxQ(int port, int tcpQueue); +void ethUdpRxQ(int port, int udpQueue); +void ethTxPolicyRegs(int port); +void ethPortRegs(int port); +void ethRegs(int port); +void ethClearCounters(int port); +void ethPortCounters(int port); +void ethPortRmonCounters(int port); +void ethPortStatus(int port); +void ethPortQueues(int port, int rxQueue, int txQueue, int mode); +void ethUcastSet(int port, char* macStr, int queue); +void ethPortUcastShow(int port); +void ethMcastAdd(int port, char* macStr, int queue); +void ethPortMcast(int port); +void mvEthPortShow(void* pHndl); +void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); + +#endif diff --git a/board/mv_feroceon/mv_hal/eth/gbe/mvEthGbe.h b/board/mv_feroceon/mv_hal/eth/gbe/mvEthGbe.h new file mode 100644 index 0000000..2feb868 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/gbe/mvEthGbe.h @@ -0,0 +1,777 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller +* +* DESCRIPTION: +* This header file contains macros typedefs and function declaration specific to +* the Marvell Gigabit Ethernet Controller. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvEthGbe_h__ +#define __mvEthGbe_h__ + +extern MV_BOOL ethDescInSram; +extern MV_BOOL ethDescSwCoher; +extern ETH_PORT_CTRL* ethPortCtrl[]; + +static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) +{ +#if defined (ETH_DESCR_IN_SRAM) + if( ethDescInSram ) + return mvSramVirtToPhy(pDesc); + else +#endif /* ETH_DESCR_IN_SRAM */ + return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); +} +/* Return port handler */ +#define mvEthPortHndlGet(port) ethPortCtrl[port] + +/* Used as WA for HW/SW race on TX */ +static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) +{ + int deep = 0; + MV_U32 txCurrReg, txEnReg; + ETH_TX_DESC* pTxLastDesc; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); + if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) + { + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; + return 0; + } + + pQueueCtrl = &pPortCtrl->txQueue[queue]; + pTxLastDesc = pQueueCtrl->pCurrentDescr; + txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); + if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) + { + /* All descriptors are processed, no chance for race */ + return 0; + } + + /* Check distance betwee HW and SW location: */ + /* If distance between HW and SW pointers is less than max_deep descriptors */ + /* Race condition is possible, so wait end of TX and restart TXQ */ + while(deep < max_deep) + { + pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); + if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) + { + int count = 0; + + while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) + { + count++; + if(count > 10000) + { + mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", + MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); + break; + } + txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); + } + + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; + return count; + } + deep++; + } + /* Distance between HW and SW pointers is more than max_deep descriptors, */ + /* So NO race condition - do nothing */ + return -1; +} + + +/* defines */ +#define ETH_CSUM_MIN_BYTE_COUNT 72 + +/* Tailgate and Kirwood have only 2K TX FIFO */ +#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) +#define ETH_CSUM_MAX_BYTE_COUNT 1600 +#else +#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 +#endif /* MV_ETH_VERSION */ + +#define ETH_MV_HEADER_SIZE 2 +#define ETH_MV_TX_EN + +/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ +#define MIN_TX_BUFF_LOAD 8 +#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) + +/* Default port configuration value */ +#define PORT_CONFIG_VALUE \ + ETH_DEF_RX_QUEUE_MASK(0) | \ + ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ + ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ + ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ + ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ + ETH_RX_CHECKSUM_WITH_PSEUDO_HDR + +/* Default port extend configuration value */ +#define PORT_CONFIG_EXTEND_VALUE 0 + +#define PORT_SERIAL_CONTROL_VALUE \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE | \ + ETH_SET_FULL_DUPLEX_MASK + +#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ + ETH_FORCE_LINK_PASS_MASK | \ + ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ + ETH_SET_FULL_DUPLEX_MASK | \ + ETH_SET_MII_SPEED_100_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE + + +#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ + ETH_FORCE_LINK_PASS_MASK | \ + ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ + ETH_SET_FULL_DUPLEX_MASK | \ + ETH_SET_GMII_SPEED_1000_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE + +#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_IN_BAND_AN_EN_MASK | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE + +/* Function headers: */ +MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); +MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); +MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); +MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); +MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); +MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); +MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); +/* Interrupt Coalesting functions */ +MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); +MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); +MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); + +/******************************************************************************/ +/* Data Flow functions */ +/******************************************************************************/ +static INLINE void mvEthPortTxRestart(void* pPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; +} + +/* Get number of Free resources in specific TX queue */ +static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + return (pPortCtrl->txQueue[txQueue].resource); +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + return (pPortCtrl->rxQueue[rxQueue].resource); +} + +static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + if(pPortCtrl->txQueue[txQueue].resource == 0) + return MV_TRUE; + + return MV_FALSE; +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && + (pQueueCtrl->resource != 0) ) + return MV_TRUE; + + return MV_FALSE; +} + +static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && + (pQueueCtrl->resource != 0) ) + { + return MV_TRUE; + } + return MV_FALSE; +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + if(pPortCtrl->rxQueue[rxQueue].resource == 0) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvEthPortTx - Send an Ethernet packet +* +* DESCRIPTION: +* This routine send a given packet described by pPktInfo parameter. +* Single buffer only. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* MV_PKT_INFO *pPktInfo - User packet to send. +* +* RETURN: +* MV_NO_RESOURCE - No enough resources to send this packet. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - Packet send successfully. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) +{ + ETH_TX_DESC* pTxCurrDesc; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + int portNo; + MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; + +#ifdef ETH_DEBUG + if(pPortCtrl->portState != MV_ACTIVE) + return MV_BAD_STATE; +#endif /* ETH_DEBUG */ + + portNo = pPortCtrl->portNo; + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + /* Get the Tx Desc ring indexes */ + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + /* Check if there is enough resources to send the packet */ + if(pQueueCtrl->resource == 0) + return MV_NO_RESOURCE; + + pTxCurrDesc->byteCnt = pBufInfo->dataSize; + + /* Flash Buffer */ + if(pPktInfo->pktSize != 0) + { +#ifdef MV_NETBSD + pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; + ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); +#else + pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); +#endif + pPktInfo->pktSize = 0; + } + else + pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; + + pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; + + /* There is only one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxCurrDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_GENERATE_CRC_MASK | + ETH_TX_ENABLE_INTERRUPT_MASK | + ETH_TX_ZERO_PADDING_MASK | + ETH_TX_FIRST_DESC_MASK | + ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + + pQueueCtrl->resource--; + pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + + /* Apply send command */ + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; + + return MV_OK; +} + + +/******************************************************************************* +* mvEthPortSgTx - Send an Ethernet packet +* +* DESCRIPTION: +* This routine send a given packet described by pBufInfo parameter. It +* supports transmitting of a packet spaned over multiple buffers. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* MV_PKT_INFO *pPktInfo - User packet to send. +* +* RETURN: +* MV_NO_RESOURCE - No enough resources to send this packet. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - Packet send successfully. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) +{ + ETH_TX_DESC* pTxFirstDesc; + ETH_TX_DESC* pTxCurrDesc; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + int portNo, bufCount; + MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; + MV_U8* pTxBuf; + +#ifdef ETH_DEBUG + if(pPortCtrl->portState != MV_ACTIVE) + return MV_BAD_STATE; +#endif /* ETH_DEBUG */ + + portNo = pPortCtrl->portNo; + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + /* Get the Tx Desc ring indexes */ + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + /* Check if there is enough resources to send the packet */ + if(pQueueCtrl->resource < pPktInfo->numFrags) + return MV_NO_RESOURCE; + + /* Remember first desc */ + pTxFirstDesc = pTxCurrDesc; + + bufCount = 0; + while(MV_TRUE) + { + if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) + { + /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ + /* to 64-bit boundary. Two options here: */ + /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ + /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ + /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ + pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; + mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); + pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); + } + else + { + /* Flash Buffer */ +#ifdef MV_NETBSD + pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; + ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); +#else + pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); +#endif + } + + pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; + bufCount++; + + if(bufCount >= pPktInfo->numFrags) + break; + + if(bufCount > 1) + { + /* There is middle buffer of the packet Not First and Not Last */ + pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + } + /* Go to next descriptor and next buffer */ + pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + } + /* Set last desc with DMA ownership and interrupt enable. */ + pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; + if(bufCount == 1) + { + /* There is only one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxCurrDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_GENERATE_CRC_MASK | + ETH_TX_ENABLE_INTERRUPT_MASK | + ETH_TX_ZERO_PADDING_MASK | + ETH_TX_FIRST_DESC_MASK | + ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + } + else + { + /* Last but not First */ + pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_ENABLE_INTERRUPT_MASK | + ETH_TX_ZERO_PADDING_MASK | + ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + + /* Update First when more than one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxFirstDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_GENERATE_CRC_MASK | + ETH_TX_FIRST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); + } + /* Update txQueue state */ + pQueueCtrl->resource -= bufCount; + pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + + /* Apply send command */ + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; + + return MV_OK; +} + +/******************************************************************************* +* mvEthPortTxDone - Free all used Tx descriptors and mBlks. +* +* DESCRIPTION: +* This routine returns the transmitted packet information to the caller. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. +* +* RETURN: +* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. +* MV_EMPTY - No transmitted packets to return. TX Queue is empty. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - There is transmitted packet in the queue, +* 'pPktInfo' filled with relevant information. +* +*******************************************************************************/ +static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) +{ + ETH_TX_DESC* pTxCurrDesc; + ETH_TX_DESC* pTxUsedDesc; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + MV_PKT_INFO* pPktInfo; + MV_U32 commandStatus; + + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + pTxUsedDesc = pQueueCtrl->pUsedDescr; + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + while(MV_TRUE) + { + /* No more used descriptors */ + commandStatus = pTxUsedDesc->cmdSts; + if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) + { + ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); + return NULL; + } + if( (pTxUsedDesc == pTxCurrDesc) && + (pQueueCtrl->resource != 0) ) + { + return NULL; + } + pQueueCtrl->resource++; + pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); + if(commandStatus & (ETH_TX_LAST_DESC_MASK)) + { + pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; + pPktInfo->status = commandStatus; + return pPktInfo; + } + pTxUsedDesc = pQueueCtrl->pUsedDescr; + } +} + +/******************************************************************************* +* mvEthPortRx - Get new received packets from Rx queue. +* +* DESCRIPTION: +* This routine returns the received data to the caller. There is no +* data copying during routine operation. All information is returned +* using pointer to packet information struct passed from the caller. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_NO_RESOURCE - No free resources in RX queue. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - New packet received and 'pBufInfo' structure filled +* with relevant information. +* +*******************************************************************************/ +static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) +{ + ETH_RX_DESC *pRxCurrDesc; + MV_U32 commandStatus; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + MV_PKT_INFO* pPktInfo; + + pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); + + /* Check resources */ + if(pQueueCtrl->resource == 0) + { + mvOsPrintf("ethPortRx: no more resources\n"); + return NULL; + } + while(MV_TRUE) + { + /* Get the Rx Desc ring 'curr and 'used' indexes */ + pRxCurrDesc = pQueueCtrl->pCurrentDescr; + + commandStatus = pRxCurrDesc->cmdSts; + if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) + { + /* Nothing to receive... */ + ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); + return NULL; + } + + /* Valid RX only if FIRST and LAST bits are set */ + if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == + (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) + { + pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; + pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; + pPktInfo->status = commandStatus; + pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; + + pQueueCtrl->resource--; + /* Update 'curr' in data structure */ + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); + +#ifdef INCLUDE_SYNC_BARR + mvCpuIfSyncBarr(DRAM_TARGET); +#endif + return pPktInfo; + } + else + { + ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; + +#ifdef ETH_DEBUG + mvOsPrintf("ethDrv: Unexpected Jumbo frame: " + "status=0x%08x, byteCnt=%d, pData=0x%x\n", + commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); +#endif /* ETH_DEBUG */ + + /* move buffer from pCurrentDescr position to pUsedDescr position */ + pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; + pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; + pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; + + /* Return the descriptor to DMA ownership */ + pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | + ETH_RX_ENABLE_INTERRUPT_MASK; + + /* Flush descriptor and CPU pipe */ + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); + + /* Move the used descriptor pointer to the next descriptor */ + pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); + } + } +} + +/******************************************************************************* +* mvEthPortRxDoneTest - Returns a Rx buffer back to the Rx ring. +* +* DESCRIPTION: +* This routine performs a diagnostic for Rx buffer +* +*******************************************************************************/ +static INLINE void mvEthRxDoneTest(MV_BUF_INFO *pBuf, MV_U32 alignment) +{ + MV_U32 va = (MV_U32) pBuf->bufVirtPtr; + MV_U32 pa = (MV_U32) pBuf->bufPhysAddr; + + /* + * Check the manipulation of pBuf is properly done prior to RxDone + */ + if (((va & 0xFF) != alignment) || ((pa & 0xFF) != alignment) || pBuf->bufAddrShift) + { + mvOsPrintf("mvRxDoneTest: pBuf=%p va=%x pa=%x shift=%d\n", pBuf, va, pa, pBuf->bufAddrShift); + /* dump_stack() */ + } +} + +/******************************************************************************* +* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. +* +* DESCRIPTION: +* This routine returns a Rx buffer back to the Rx ring. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_ERROR - Unexpected Fatal error. +* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be +* returned to this queue. +* MV_FULL - Buffer returned successfully and RX queue became full. +* More buffers should not be returned at the time. +* MV_OK - Buffer returned successfully and there are more free +* places in the queue. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) +{ + ETH_RX_DESC* pRxUsedDesc; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + +/* + // for debug: + mvEthRxDoneTest(pPktInfo->pFrags, CONFIG_NET_SKB_HEADROOM); +*/ + pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + /* Get 'used' Rx descriptor */ + pRxUsedDesc = pQueueCtrl->pUsedDescr; + + /* Check that ring is not FULL */ + if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && + (pQueueCtrl->resource != 0) ) + { + mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", + __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, + pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); + return MV_OUT_OF_RANGE; + } + + pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; + pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; + pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; + + /* Invalidate data buffer accordingly with pktSize */ + if(pPktInfo->pktSize != 0) + { + ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); + pPktInfo->pktSize = 0; + } + + /* Return the descriptor to DMA ownership */ + pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; + + /* Flush descriptor and CPU pipe */ + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); + + pQueueCtrl->resource++; + + /* Move the used descriptor pointer to the next descriptor */ + pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); + + /* If ring became Full return MV_FULL */ + if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) + return MV_FULL; + + return MV_OK; +} + + +#endif /* __mvEthGbe_h__ */ + + diff --git a/board/mv_feroceon/mv_hal/eth/gbe/mvEthRegs.h b/board/mv_feroceon/mv_hal/eth/gbe/mvEthRegs.h new file mode 100644 index 0000000..7b9f052 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/gbe/mvEthRegs.h @@ -0,0 +1,700 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvEthRegsh +#define __INCmvEthRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/****************************************/ +/* Ethernet Unit Registers */ +/****************************************/ +#define ETH_REG_BASE MV_ETH_REG_BASE + +#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) +#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) +#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) +#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) +#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) +#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) +#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) + + +#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) +#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) +#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) + +#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) +#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) +#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) +#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) +#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) +#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) +#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) +#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) +#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) +#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) +#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) +#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) + +#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) +#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) + +#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) +#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) +#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) +#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) +#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) +#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) +#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) +#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) +#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) +#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) +#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) +#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) +#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) +#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) +#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) +#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) +#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) +#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) +#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) +#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) +#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) +#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) +#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) +#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) +#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) + +#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) +#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) +#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) + +#if (MV_ETH_VERSION >= 4) +#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) +#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) +#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) +#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) +#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) +#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) +#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) +#endif /* MV_ETH_VERSION >= 4 */ + +#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) +#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) +#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) +#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) + +/* Phy address register definitions */ +#define ETH_PHY_ADDR_OFFS 0 +#define ETH_PHY_ADDR_MASK (0x1f <= 4) +#define ETH_TX_EJP_RESET_BIT 0 +#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) + +#define ETH_TX_EJP_ENABLE_BIT 2 +#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) + +#define ETH_TX_LEGACY_WRR_BIT 3 +#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) +#endif /* (MV_ETH_VERSION >= 4) */ + +/***** BITs of Ethernet Port Status reg (PSR) *****/ +#define ETH_LINK_UP_BIT 1 +#define ETH_LINK_UP_MASK (1<= 4) +MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); +#endif /* (MV_ETH_VERSION >= 4) */ + +void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); + +/* Marvell Header control */ +MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); + +/* PHY routines */ +void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); +int mvEthPhyAddrGet(void* pPortHandle); + +/* Power management routines */ +void mvEthPortPowerDown(int port); +void mvEthPortPowerUp(int port); + +/******************** ETH PRIVATE ************************/ + +/*#define UNCACHED_TX_BUFFERS*/ +/*#define UNCACHED_RX_BUFFERS*/ + + +/* Port attributes */ +/* Size of a Tx/Rx descriptor used in chain list data structure */ +#define ETH_RX_DESC_ALIGNED_SIZE 32 +#define ETH_TX_DESC_ALIGNED_SIZE 32 + +#define TX_DISABLE_TIMEOUT_MSEC 1000 +#define RX_DISABLE_TIMEOUT_MSEC 1000 +#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 +#define PORT_DISABLE_WAIT_TCLOCKS 5000 + +/* Macros that save access to desc in order to find next desc pointer */ +#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ + ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ + (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ + (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) + +#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ + ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ + (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ + (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) + +#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ + ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ + (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ + (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) + +#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ + ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ + (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ + (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) + + +/* Queue specific information */ +typedef struct +{ + void* pFirstDescr; + void* pLastDescr; + void* pCurrentDescr; + void* pUsedDescr; + int resource; + MV_BUF_INFO descBuf; +} ETH_QUEUE_CTRL; + + +/* Ethernet port specific infomation */ +typedef struct _ethPortCtrl +{ + int portNo; + ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ + ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ + + MV_ETH_PORT_CFG portConfig; + MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; + MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; + + /* Register images - For DP */ + MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ + MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ + + MV_STATE portState; + + MV_U8 mcastCount[256]; + MV_U32* hashPtr; + void *osHandle; +} ETH_PORT_CTRL; + +/************** MACROs ****************/ + +/* MACROs to Flush / Invalidate TX / RX Buffers */ +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) +# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ + mvOsCacheClear(NULL, (pAddr), (size)); \ + /*CPU_PIPE_FLUSH;*/ +#else +# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ + mvOsIoVirtToPhy(NULL, (pAddr)); +#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ + +#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) +# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ + mvOsCacheInvalidate (NULL, (pAddr), (size)); \ + /*CPU_PIPE_FLUSH;*/ +#else +# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) +#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ + +#ifdef ETH_DESCR_UNCACHED + +#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) +#define ETH_DESCR_INV(pPortCtrl, pDescr) + +#else + +#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ + mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) + +#define ETH_DESCR_INV(pPortCtrl, pDescr) \ + mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) + +#endif /* ETH_DESCR_UNCACHED */ + +#include "eth/gbe/mvEthGbe.h" + +#endif /* __mvEth_h__ */ + + diff --git a/board/mv_feroceon/mv_hal/eth/nfp/mvNfp.c b/board/mv_feroceon/mv_hal/eth/nfp/mvNfp.c new file mode 100644 index 0000000..a03457f --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/nfp/mvNfp.c @@ -0,0 +1,1109 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfp.c - Marvell Network Fast Processing (Routing and NAT) +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mvDebug.h" +#include "eth/nfp/mvNfp.h" +#include "eth/nfp/mvNfpSec.h" +#include "eth/mvEth.h" + +static struct ruleHashBucket *ruleDb; +static MV_U32 ruleDbSize; + +static MV_U32 nfpHashMaxDepth; +static MV_U32 nfpRuleSetCount; +static MV_U32 nfpRuleUpdateCount; +static MV_U32 nfpRuleDeleteCount; + +MV_U32 fp_ip_jhash_iv = 0; + + +MV_STATUS mvFpInit(void) +{ + fp_ip_jhash_iv = mvOsRand(); + + return MV_OK; +} + + +/* Initialize NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbInit(MV_U32 dbSize) +{ + ruleDb = (struct ruleHashBucket *)mvOsMalloc(sizeof(struct ruleHashBucket)*dbSize); + if (ruleDb == NULL) { + mvOsPrintf("NFP Rule DB: Not Enough Memory\n"); + return MV_NO_RESOURCE; + } + ruleDbSize = dbSize; + memset(ruleDb, 0, sizeof(struct ruleHashBucket)*ruleDbSize); + nfpRuleSetCount = nfpRuleUpdateCount = nfpRuleDeleteCount = 0; + + mvOsPrintf("mvFpRuleDb (%p): %d entries, %d bytes\n", + ruleDb, ruleDbSize, sizeof(struct ruleHashBucket)*ruleDbSize); + + return MV_OK; +} + +/* Clear NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbClear(void) +{ + MV_U32 i = 0; + MV_FP_RULE *currRule; + MV_FP_RULE *tmpRule; + + if (ruleDb == NULL) + return MV_NOT_INITIALIZED; + + for (i = 0; i < ruleDbSize; i++) { + currRule = ruleDb[i].ruleChain; + while (currRule != NULL) { + tmpRule = currRule; + currRule = currRule->next; + mvOsFree(tmpRule); + } + ruleDb[i].ruleChain = NULL; + } + return MV_OK; +} + + +/* Free Rule Database memory */ +void mvFpRuleDbDestroy(void) +{ + if (ruleDb != NULL) + mvOsFree(ruleDb); +} + +/* Print rule action type. Assume rule is not NULL. */ +static void mvFpActionTypePrint(const MV_FP_RULE *rule) +{ + switch(rule->mgmtInfo.actionType) { + case MV_FP_ROUTE_CMD: + mvOsPrintf("A=Route, "); + break; + case MV_FP_DROP_CMD: + mvOsPrintf("A=Drop, "); + break; + case MV_FP_TO_STACK_CMD: + mvOsPrintf("A=Stack, "); + break; + default: + mvOsPrintf("A=Unknown (%d), ", rule->mgmtInfo.actionType); + break; + } +} + +/* Print rule type (static or dynamic). Assume rule is not NULL. */ +static void mvFpRuleTypePrint(const MV_FP_RULE *rule) +{ + switch(rule->mgmtInfo.ruleType) { + case MV_FP_STATIC_RULE: + mvOsPrintf("T=Static"); + break; + case MV_FP_DYNAMIC_RULE: + mvOsPrintf("T=Dynamic"); + break; + default: + mvOsPrintf("T=Unknown"); + break; + } +} + +/* Print a NFP Rule */ +void mvFpRulePrint(const MV_FP_RULE *rule) +{ + mvFpActionTypePrint(rule); + mvFpRuleTypePrint(rule); + mvOsPrintf(", SIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->routingInfo.srcIp)); + mvOsPrintf(", DIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->routingInfo.dstIp)); + mvOsPrintf(", GTW="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->routingInfo.defGtwIp)); + mvOsPrintf(", DA="); + mvDebugPrintMacAddr(rule->routingInfo.dstMac); + mvOsPrintf(", SA="); + mvDebugPrintMacAddr(rule->routingInfo.srcMac); + mvOsPrintf(", inIf=%d", rule->routingInfo.inIfIndex); + mvOsPrintf(", outIf=%d", rule->routingInfo.outIfIndex); + mvOsPrintf(", ToS=0x%x", rule->routingInfo.dscp); + mvOsPrintf(", TxQ=%d", rule->routingInfo.txq); + + mvOsPrintf(", count=%d, aware_flags=0x%X", rule->mgmtInfo.new_count, rule->routingInfo.aware_flags); + mvOsPrintf("\n"); +} + +/* Print NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbPrint(void) +{ + MV_U32 count, i; + MV_FP_RULE *currRule; + + mvOsPrintf("\nPrinting NFP Rule Database\n"); + count = 0; + + for(i=0; inext; + count++; + } + } + return MV_OK; +} + + +/* Copy all the information from src_rule to new_rule */ +/* Warning - doesn't perform any checks on memory, just copies */ +/* count is set to zero in new_rule */ +/* Note: the next pointer is not updated . */ +void mvFpRuleCopy(MV_FP_RULE *dstRule, const MV_FP_RULE *srcRule) +{ + dstRule->mgmtInfo.actionType = srcRule->mgmtInfo.actionType; + dstRule->mgmtInfo.new_count = srcRule->mgmtInfo.new_count; + dstRule->mgmtInfo.old_count = srcRule->mgmtInfo.old_count; + dstRule->mgmtInfo.ruleType = srcRule->mgmtInfo.ruleType; + dstRule->mgmtInfo.snat_aware_refcnt = srcRule->mgmtInfo.snat_aware_refcnt; + dstRule->mgmtInfo.dnat_aware_refcnt = srcRule->mgmtInfo.dnat_aware_refcnt; + + dstRule->routingInfo.aware_flags = srcRule->routingInfo.aware_flags; + dstRule->routingInfo.srcIp = srcRule->routingInfo.srcIp; + dstRule->routingInfo.dstIp = srcRule->routingInfo.dstIp; + dstRule->routingInfo.defGtwIp = srcRule->routingInfo.defGtwIp; + memcpy(dstRule->routingInfo.srcMac, srcRule->routingInfo.srcMac, MV_MAC_ADDR_SIZE); + memcpy(dstRule->routingInfo.dstMac, srcRule->routingInfo.dstMac, MV_MAC_ADDR_SIZE); + dstRule->routingInfo.inIfIndex = srcRule->routingInfo.inIfIndex; + dstRule->routingInfo.outIfIndex = srcRule->routingInfo.outIfIndex; + dstRule->routingInfo.txq = srcRule->routingInfo.txq; + dstRule->routingInfo.dscp = srcRule->routingInfo.dscp; +} + +/* Get the count value for a rule that matches the given SIP, DIP */ +MV_U32 mvFpRouteCountGet(MV_U32 srcIp, MV_U32 dstIp) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *pRule; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32)0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + while(pRule) + { + /* look for a matching rule */ + if( (pRule->routingInfo.dstIp == dstIp) && + (pRule->routingInfo.srcIp == srcIp) ) + { + return pRule->mgmtInfo.new_count; + } + pRule = pRule->next; + } + return 0; +} + +MV_STATUS mvFpRuleAwareSet(MV_FP_RULE *pSetRule) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *pRule; + + hash = mv_jhash_3words(pSetRule->routingInfo.dstIp, pSetRule->routingInfo.srcIp, + (MV_U32)0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + while(pRule) + { + if( (pRule->routingInfo.srcIp == pSetRule->routingInfo.srcIp) && + (pRule->routingInfo.dstIp == pSetRule->routingInfo.dstIp) ) { + + + pRule->routingInfo.aware_flags = pSetRule->routingInfo.aware_flags; +#ifdef MV_FP_DEBUG + mvOsPrintf("Update FP aware: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash0x%x, flags=0x%x\n", + MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), + hash_tr, pSetRule->routingInfo.aware_flags); +#endif + return MV_OK; + } + pRule = pRule->next; + } +#ifdef MV_FP_DEBUG + mvOsPrintf("FP aware NOT found: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%x, flags=0x%x\n", + MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), + hash_tr, pSetRule->routingInfo.aware_flags); +#endif + return MV_NOT_FOUND; +} +/* Set a Routing ToS Rule: update an existing rule */ +#ifdef CONFIG_MV_ETH_NFP_TOS +MV_STATUS mvFpToSSet(MV_FP_RULE *pSetRule) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *pRule; + + hash = mv_jhash_3words(pSetRule->routingInfo.dstIp, pSetRule->routingInfo.srcIp, + (MV_U32)0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + while(pRule) + { + if( (pRule->routingInfo.srcIp == pSetRule->routingInfo.srcIp && + pRule->routingInfo.dstIp == pSetRule->routingInfo.dstIp) ) { + pRule->routingInfo.txq = pSetRule->routingInfo.txq; + pRule->routingInfo.dscp = pSetRule->routingInfo.dscp; + nfpRuleUpdateCount++; +#ifdef MV_FP_DEBUG + mvOsPrintf("ToSNFP_%03u: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%04x TOS=0x%x TxQ=%d\n", + nfpRuleUpdateCount, MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), hash_tr, + pRule->routingInfo.dscp, pRule->routingInfo.txq); +#endif + return MV_OK; + } + pRule = pRule->next; + } + return MV_NOT_FOUND; +} +#endif +/* Set a Routing Rule: create a new rule or update an existing rule */ +/* in the Routing + ARP information table */ +MV_STATUS mvFpRuleSet(MV_FP_RULE *pSetRule) +{ + MV_U32 hash, hash_tr; + int depth = 0; + MV_FP_RULE *pRule, *pNewRule; + + hash = mv_jhash_3words(pSetRule->routingInfo.dstIp, pSetRule->routingInfo.srcIp, + (MV_U32)0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + while(pRule) + { + if( (pRule->routingInfo.srcIp == pSetRule->routingInfo.srcIp && + pRule->routingInfo.dstIp == pSetRule->routingInfo.dstIp) ) { + + mvFpRuleCopy(pRule, pSetRule); + nfpRuleUpdateCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf("UpdNFP_%03u: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%04x TOS=0x%x TxQ=%d\n", + nfpRuleUpdateCount, MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), hash_tr, + pRule->routingInfo.dscp, pRule->routingInfo.txq); +#endif + return MV_OK; + } + pRule = pRule->next; + } + + /* Allocate new entry */ + pNewRule = mvOsMalloc(sizeof(MV_FP_RULE)); + if(pNewRule == NULL) + { + mvOsPrintf("mvFpRuleSet: Can't allocate new rule\n"); + return MV_FAIL; + } + mvFpRuleCopy(pNewRule, pSetRule); + pNewRule->next = NULL; + + if(ruleDb[hash_tr].ruleChain == NULL) + ruleDb[hash_tr].ruleChain = pNewRule; + else { + pRule = ruleDb[hash_tr].ruleChain; + while (pRule->next != NULL) + { + depth++; + pRule = pRule->next; + } + pRule->next = pNewRule; + } + if(depth > nfpHashMaxDepth) + nfpHashMaxDepth = depth; + nfpRuleSetCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf("SetNFP_%03u: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%04x, aware=0x%02x\n", + nfpRuleSetCount, MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), + hash_tr, pSetRule->routingInfo.aware_flags); +#endif + return MV_OK; +} + +/* Delete a specified rule from the Routing + ARP information table */ +MV_STATUS mvFpRuleDelete(MV_FP_RULE *rule) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *currRule, *prevRule; + + nfpRuleDeleteCount++; + hash = mv_jhash_3words(rule->routingInfo.dstIp, rule->routingInfo.srcIp, + (MV_U32)0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + prevRule = NULL; + for (currRule = ruleDb[hash_tr].ruleChain; + currRule != NULL; + prevRule = currRule, currRule = currRule->next) + { + if( (currRule->routingInfo.srcIp == rule->routingInfo.srcIp) && + (currRule->routingInfo.dstIp == rule->routingInfo.dstIp) ) + { + if (prevRule == NULL) + ruleDb[hash_tr].ruleChain = currRule->next; + else + prevRule->next = currRule->next; +#ifdef MV_FP_DEBUG + mvOsPrintf("DelNFP_%03u: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%04x\n", + nfpRuleDeleteCount, MV_IP_QUAD(currRule->routingInfo.dstIp), + MV_IP_QUAD(currRule->routingInfo.srcIp), hash_tr); +#endif + mvOsFree(currRule); + return MV_OK; + } + } + return MV_NOT_FOUND; +} + +/* Find and return the first matching rule in the Routing + ARP information table */ +static INLINE MV_FP_RULE* mvFpRuleFind(MV_U32 dstIp, MV_U32 srcIp) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE* pRule; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32)0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + + while(pRule) + { + /* look for a matching rule */ + if( (pRule->routingInfo.dstIp == dstIp) && + (pRule->routingInfo.srcIp == srcIp) ) + { + pRule->mgmtInfo.new_count++; + return pRule; + } + pRule = pRule->next; + } + return NULL; +} + +#ifdef CONFIG_MV_ETH_NFP_FDB_SUPPORT +static INLINE MV_U32 mvFpFdbMember(MV_U32 ifIndex) +{ + return (ifIndex < ETH_FP_IFINDEX_MAX) ? fdbMember[ifIndex] : 0; +} + +static MV_FP_FDB_RULE* mvFpFdbLookup(MV_U32 ifIndex, MV_U8* pDA) +{ + MV_U32 hash, hash_tr; + MV_FP_FDB_RULE* pRule; + MV_U32 bridgeId; + + if (ifIndex >= ETH_FP_IFINDEX_MAX) + return NULL; + + if (!(bridgeId = fdbMember[ifIndex])) + return NULL; + + hash = mv_jhash_3words(bridgeId, 0, *(MV_U32*)(pDA+2), fp_ip_jhash_iv); + hash_tr = hash & (fdbRuleDbSize - 1); + + pRule = fdbRuleDb[hash_tr].ruleChain; + + while (pRule) { +/* + MV_NFP_DBG("%s: looking %d %02x:%02x:%02x:%02x:%02x:%02x\n", + __FUNCTION__, bridgeId, + pRule->fdbInfo.mac[0], + pRule->fdbInfo.mac[1], + pRule->fdbInfo.mac[2], + pRule->fdbInfo.mac[3], + pRule->fdbInfo.mac[4], + pRule->fdbInfo.mac[5]); +*/ + if ((bridgeId == pRule->fdbInfo.bridge) && + (*((MV_U16*)(pDA+0)) == *(MV_U16*)(&pRule->fdbInfo.mac[0])) && + (*((MV_U16*)(pDA+2)) == *(MV_U16*)(&pRule->fdbInfo.mac[2])) && + (*((MV_U16*)(pDA+4)) == *(MV_U16*)(&pRule->fdbInfo.mac[4]))) + { + pRule->mgmtInfo.new_count++; + break; + } + pRule = pRule->next; + } +/* + if (pRule) + MV_NFP_DBG("%s: lookup bridge=%d %02x:%02x:%02x:%02x:%02x:%02x => if=%d flags=%x\n", + __FUNCTION__, bridgeId, pDA[0],pDA[1],pDA[2],pDA[3],pDA[4],pDA[5], + pRule->fdbInfo.ifIndex, pRule->fdbInfo.flags); + else + MV_NFP_DBG("%s: lookup bridge=%d %02x:%02x:%02x:%02x:%02x:%02x => unknown\n", + __FUNCTION__, bridgeId, pDA[0],pDA[1],pDA[2],pDA[3],pDA[4],pDA[5]); + +*/ + return pRule; +} +#endif /* CONFIG_MV_ETH_NFP_FDB_SUPPORT */ + +/* + * PPPoE Support + */ +#ifdef CONFIG_MV_ETH_NFP_PPP +static INLINE void mvFpDecTTL(MV_IP_HEADER* pIpHdr) +{ + MV_U32 check = (MV_U32)pIpHdr->checksum; + check += (MV_U32)htons(0x0100); + pIpHdr->checksum = (MV_U16)(check + (check>=0xFFFF)); + pIpHdr->ttl--; +} +static INLINE __wsum csum_unfold(__sum16 n) +{ + return (__force __wsum)n; +} + +static INLINE __sum16 csum_fold(__wsum sum) +{ + __asm__( + "add %0, %1, %1, ror #16 @ csum_fold" + : "=r" (sum) + : "r" (sum) + : "cc"); + return (__force __sum16)(~(__force u32)sum >> 16); +} + +__u32 csum_partial(const char *src, int len, __u32 sum); + +static INLINE void mvFpCSumInc(MV_IP_HEADER* pIpHdr, MV_U32 srcIp, MV_U32 newIp) +{ + MV_TCP_HEADER *pTcpHdr; + MV_UDP_HEADER *pUdpHdr; + __be32 diff[] = { ~srcIp, newIp }; + + pIpHdr->checksum = csum_fold(csum_partial((char *)diff, sizeof(diff), ~csum_unfold(pIpHdr->checksum))); + + switch(pIpHdr->protocol) + { + case MV_IP_PROTO_TCP: + pTcpHdr = (MV_TCP_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + pTcpHdr->chksum = csum_fold(csum_partial((char *)diff, sizeof(diff), ~csum_unfold(pTcpHdr->chksum))); + break; + case MV_IP_PROTO_UDP: + pUdpHdr = (MV_UDP_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + pUdpHdr->check = csum_fold(csum_partial((char *)diff, sizeof(diff), ~csum_unfold(pUdpHdr->check))); + break; + } +} + +static INLINE MV_U32 mvFpPppLookup(MV_U32 ifIndex) +{ + return pppOpen[ifIndex].pppInfo.if_ppp; +} +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +/* Check that protocol supported for FP NAT and extract srcPort and dstPort + * (or their equivalents) from the packet. + */ +static INLINE MV_U8 mvFpPortsGet(MV_IP_HEADER* pIpHdr, MV_U16* pDstPort, MV_U16* pSrcPort) +{ + MV_U8 proto = pIpHdr->protocol; + MV_UDP_HEADER *pUdpHdr; + MV_TCP_HEADER *pTcpHdr; + + switch(proto) + { + case MV_IP_PROTO_TCP: + pTcpHdr = (MV_TCP_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + *pDstPort = pTcpHdr->dest; + *pSrcPort = pTcpHdr->source; + break; + + case MV_IP_PROTO_UDP: + pUdpHdr = (MV_UDP_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + *pDstPort = pUdpHdr->dest; + *pSrcPort = pUdpHdr->source; + break; + + /* Other protocols supporting NAT only without ports + * case ???????: + * case ???????: + * *pDstPort = 0; + * *pSrcPort = 0; + * break + * + */ + + default: + /* Skip NAT processing at all */ + proto = MV_IP_PROTO_NULL; + } + return proto; +} + +int mvFpProcess(MV_U32 ifIndex, MV_PKT_INFO* pPkt, MV_FP_STATS* pFpStats) +{ + MV_FP_RULE *pRt; + MV_U32 dip, sip; + MV_U8 proto; + MV_U16 srcPort, dstPort; + MV_U8* pEth = pPkt->pFrags->bufVirtPtr; + MV_IP_HEADER* pIpHdr; +#ifdef CONFIG_MV_ETH_NFP_NAT_SUPPORT + MV_FP_NAT_RULE *pDnatRule, *pSnatRule; +#endif /* CONFIG_MV_ETH_NFP_NAT_SUPPORT */ +#ifdef CONFIG_MV_ETH_NFP_FDB_SUPPORT + MV_FP_FDB_RULE *pFdb; +#endif +#ifdef CONFIG_MV_ETH_NFP_PPP + MV_PPPoE_HEADER *pPPP = (MV_PPPoE_HEADER*)pEth; + MV_BUF_INFO *pBuf = pPkt->pFrags; +#endif +#ifdef CONFIG_MV_ETH_NFP_SEC + MV_NFP_SEC_SPD_RULE *pSpd; + MV_NFP_SEC_SA_ENTRY* pSAEntry; + MV_ESP_HEADER* pEspHdr; +#endif + + MV_NFP_STAT( pFpStats->process++ ); + + /* Check MAC address: + * WAN - non-promiscous mode. + * Unicast packets - NFP, + * Multicast, Broadcast - Linux + * LAN - Promiscous mode. + * LAN Unicast MAC - NFP, + * Multicast, Broadcast, Unknown Unicast - Linux + */ + if (pEth[ETH_MV_HEADER_SIZE] == 0x01) + { + MV_NFP_STAT( pFpStats->multicast++); + return -1; + } + +#ifdef CONFIG_MV_ETH_NFP_FDB_SUPPORT + if (mvFpFdbMember(ifIndex)) + { + pFdb = mvFpFdbLookup(ifIndex, pEth + ETH_MV_HEADER_SIZE); + if (!pFdb) { + MV_NFP_STAT( pFpStats->fdb_rx_unknown++ ); + return -1; + } + if (pFdb->fdbInfo.flags & MV_FP_FDB_IS_LOCAL) { + /* DA is local, continue with routing */ + MV_NFP_STAT( pFpStats->fdb_rx_local++ ); + } + else { + /* perform bridging */ + MV_NFP_STAT( pFpStats->fdb_bridged++ ); + return pFdb->fdbInfo.ifIndex; + } + } +#endif /* CONFIG_MV_ETH_NFP_FDB_SUPPORT */ + + /* Check LLC/SNAP and IP header */ + if( ((pPkt->status & ETH_RX_NOT_LLC_SNAP_FORMAT_MASK) == 0) || + ((pPkt->status & ETH_RX_IP_HEADER_OK_MASK) == 0)) + { + /* Non IP packet: go to Linux IP stack */ + MV_NFP_STAT( pFpStats->non_ip++ ); + pIpHdr = NULL; + } + else + { + MV_U32 tx_status; + + if (pPkt->fragIP) + { + MV_NFP_STAT( pFpStats->ip_frag++ ); + return -1; + } + tx_status = ( ETH_TX_GENERATE_IP_CHKSUM_MASK + | ETH_TX_IP_NO_FRAG + | (5 << ETH_TX_IP_HEADER_LEN_OFFSET) ); + + /* Calculate start of IP header */ + if( (pPkt->status & ETH_RX_VLAN_TAGGED_FRAME_MASK) ) + { + MV_NFP_STAT(pFpStats->vlan_tagged++); + pIpHdr = (MV_IP_HEADER*)(pEth + ETH_MV_HEADER_SIZE + sizeof(MV_802_3_HEADER) + MV_VLAN_HLEN); + tx_status |= ETH_TX_VLAN_TAGGED_FRAME_MASK; + } + else + { + pIpHdr = (MV_IP_HEADER*)(pEth + ETH_MV_HEADER_SIZE + sizeof(MV_802_3_HEADER)); + } + + if( (pPkt->status & ETH_RX_L4_TYPE_MASK) == ETH_RX_L4_TCP_TYPE ) + { + tx_status |= (ETH_TX_L4_TCP_TYPE | ETH_TX_GENERATE_L4_CHKSUM_MASK); + } + else if( (pPkt->status & ETH_RX_L4_TYPE_MASK) == ETH_RX_L4_UDP_TYPE ) + { + tx_status |= (ETH_TX_L4_UDP_TYPE | ETH_TX_GENERATE_L4_CHKSUM_MASK); + } + pPkt->status = tx_status; + } + +#ifdef CONFIG_MV_ETH_NFP_PPP + /* Decapsulate PPPoE */ + if (!pIpHdr) { + if ((pPPP->ethertype == 0x6488) && (pPPP->proto == 0x2100)) + { + pIpHdr = (MV_IP_HEADER*)(pEth + ETH_MV_HEADER_SIZE + + sizeof(MV_802_3_HEADER) + + ETH_FP_PPPOE_HDR); + + /* do not process fragments */ + if (pIpHdr->fragmentCtrl & 0xFF3F) { + MV_NFP_STAT(pFpStats->ppp_rx_frag++); + goto out; + } + + pBuf->bufAddrShift -= ETH_FP_PPPOE_HDR; + pBuf->bufPhysAddr += ETH_FP_PPPOE_HDR; + pBuf->bufVirtPtr += ETH_FP_PPPOE_HDR; + pBuf->dataSize -= ETH_FP_PPPOE_HDR; + pEth += ETH_FP_PPPOE_HDR; + + pPkt->status = ETH_TX_IP_NO_FRAG | ETH_TX_GENERATE_IP_CHKSUM_MASK | + (0x5 << ETH_TX_IP_HEADER_LEN_OFFSET); + + switch (pIpHdr->protocol) { + case MV_IP_PROTO_TCP: + pPkt->status |= ETH_TX_L4_TCP_TYPE|ETH_TX_GENERATE_L4_CHKSUM_MASK; + break; + case MV_IP_PROTO_UDP: + pPkt->status |= ETH_TX_L4_UDP_TYPE|ETH_TX_GENERATE_L4_CHKSUM_MASK; + break; + } + + //printk("Rx (pppoe) " NIPQUAD_FMT " " NIPQUAD_FMT "\n", NIPQUAD(pIpHdr->srcIP), NIPQUAD(pIpHdr->dstIP)); + MV_NFP_STAT(pFpStats->ppp_rx++); + } + } + +#endif /* CONFIG_MV_ETH_NFP_PPP */ + + if (!pIpHdr) + goto out; + + /* Check TTL value */ + if(pIpHdr->ttl <= 1) + { + /* TTL expired */ + MV_NFP_STAT( pFpStats->ip_ttl_expired++ ); + goto out; + } + + dip = pIpHdr->dstIP; + sip = pIpHdr->srcIP; + +#ifdef CONFIG_MV_ETH_NFP_SEC + /* TBD - Add statistics counters */ + /* inbound ipsec traffic */ + if( pIpHdr->protocol == MV_IP_PROTO_ESP ) { + + /* extract esp header */ + pEspHdr = (MV_ESP_HEADER*)((MV_U8*)pIpHdr + sizeof(MV_IP_HEADER)); + + /* extract SA according to packet spi */ + pSAEntry = mvNfpSecSARuleFind(pEspHdr->spi); + if(pSAEntry != NULL) { + if(MV_OK == mvNfpSecIncoming(pPkt, pSAEntry)) + { + MV_NFP_STAT( pFpStats->sec_in++ ); + return MV_NFP_STOLEN; + } + else + { + /* TDB- handle pkt gracefully */ + MV_NFP_STAT( pFpStats->sec_in_drop++ ); + return MV_NFP_DROP; + + } + } + mvOsPrintf("mvFpProcess: no SA found for ESP packet(spi=0x%x)\n",pEspHdr->spi); + } + else { + /* outbound */ + proto = mvFpPortsGet(pIpHdr, &dstPort, &srcPort); + + pSpd = mvNfpSecSPDRuleFind(dip, sip, proto, dstPort, srcPort, MV_NFP_SEC_RULE_DB_OUT); + if(pSpd != NULL) + { + switch(pSpd->actionType) + { + case (MV_NFP_SEC_FWD): + break; + case (MV_NFP_SEC_SECURE): + status = mvNfpSecOutgoing(pPkt, pSpd->pSAEntry); + if (status == MV_OK) + { + /* handled by cesa */ + MV_NFP_STAT( pFpStats->sec_out++ ); + return MV_NFP_STOLEN; + } + else if (status == MV_OUT_OF_RANGE) + { + /* slow path */ + MV_NFP_STAT( pFpStats->sec_out_slow++ ); + return MV_NFP_NONE; + } + else + { + /* drop packet */ + MV_NFP_STAT( pFpStats->sec_out_drop++ ); + return MV_NFP_DROP; + } + break; + case (MV_NFP_SEC_DROP): + MV_NFP_STAT( pFpStats->sec_out_drop++ ); + return MV_NFP_DROP; + break; + } + } + } +#endif + +#ifdef CONFIG_MV_ETH_NFP_NAT_SUPPORT + proto = mvFpPortsGet(pIpHdr, &dstPort, &srcPort); + if(proto == MV_IP_PROTO_NULL) + { + /* NAT not supported for this protocol */ + MV_NFP_STAT( pFpStats->nat_bad_proto++ ); + pDnatRule = NULL; + } + else + { + /* Lookup NAT database accordingly with 5 tuple key */ + pDnatRule = mvFpNatRuleFind(dip, sip, proto, dstPort, srcPort); + } + if(pDnatRule != NULL) + { + if(pDnatRule->flags & MV_FP_DIP_CMD_MAP) + { + dip = pDnatRule->newIp; + } + if(pDnatRule->flags & MV_FP_DPORT_CMD_MAP) + { + dstPort = pDnatRule->newPort; + } + } + else + { + MV_NFP_STAT( pFpStats->dnat_not_found++ ); + } + +#endif /* CONFIG_MV_ETH_NFP_NAT_SUPPORT */ + + pRt = mvFpRuleFind(dip, sip); + if(pRt == NULL) + { + /* IP Routing rule is not found: go to Linux IP stack */ + MV_NFP_STAT( pFpStats->route_miss++ ); + goto out; + } + + MV_NFP_STAT(pFpStats->route_hit++); + +#ifdef CONFIG_MV_ETH_NFP_NAT_SUPPORT + if( (pDnatRule != NULL) && (pDnatRule->flags & MV_FP_DNAT_CMD_MAP) ) + { + MV_NFP_STAT( pFpStats->dnat_found++ ); + pSnatRule = mvFpNatRuleFind(dip, sip, proto, dstPort, srcPort); + } + else + { + pSnatRule = pDnatRule; + } + + if( (pSnatRule != NULL) && (pSnatRule->flags & MV_FP_SNAT_CMD_MAP) ) + { + MV_NFP_STAT( pFpStats->snat_found++ ); + } + else + { + MV_NFP_STAT( pFpStats->snat_not_found++ ); + } + + /* Check IP awareness */ + if( (pRt->routingInfo.aware_flags & MV_FP_DIP_CMD_MAP) && + (pDnatRule == NULL) ) + { + MV_NFP_STAT( pFpStats->dnat_aware++ ); + goto out; + } + + if( (pRt->routingInfo.aware_flags & MV_FP_SIP_CMD_MAP) && + (pSnatRule == NULL) ) + { + MV_NFP_STAT( pFpStats->snat_aware++ ); + goto out; + } + + /* Update packet accordingly with NAT rules */ + if( (pDnatRule != NULL) || (pSnatRule != NULL) ) + { + mvFpNatPktUpdate(pIpHdr, pDnatRule, pSnatRule); + } +#endif /* CONFIG_MV_ETH_NFP_NAT_SUPPORT */ + + + ifIndex = pRt->routingInfo.outIfIndex; + +#ifdef CONFIG_MV_ETH_NFP_PPP + /* Encapsulate PPPoE on Tx */ + if (mvFpPppLookup(ifIndex)) + { + if (pBuf->dataSize > 1514 + ETH_MV_HEADER_SIZE - ETH_FP_PPPOE_HDR) + { + MV_NFP_STAT(pFpStats->ppp_tx_slow++); + goto out; + } + + MV_NFP_STAT(pFpStats->ppp_tx++); + + /* FIXME: pktSize is left unchanged */ + pBuf->bufAddrShift += ETH_FP_PPPOE_HDR; + pBuf->bufPhysAddr -= ETH_FP_PPPOE_HDR; + pBuf->bufVirtPtr -= ETH_FP_PPPOE_HDR; + pBuf->dataSize += ETH_FP_PPPOE_HDR; + pEth -= ETH_FP_PPPOE_HDR; + + + /* -6B aligment from 32B boundary */ + { + MV_U32* d = (MV_U32*)pEth; + MV_U32* s = pppOpen[ifIndex].pppInfo.u.u32; + + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + } + + /* update payload len */ + *(MV_U16*)(pEth+20) = htons(pBuf->dataSize - 14 - ETH_FP_PPPOE_HDR); + + mvFpDecTTL(pIpHdr); +#ifdef CONFIG_MV_ETH_NFP_NAT_SUPPORT + if (pSnatRule) + mvFpCSumInc(pIpHdr, pSnatRule->srcIp, pSnatRule->newIp); +#endif + pPkt->status = 0; + ifIndex = pppOpen[ifIndex].pppInfo.if_eth; + + /* invalidate 3rd cacheline */ + pEth = (MV_U32)pEth & ~(CPU_D_CACHE_LINE_SIZE - 1); + pEth += CPU_D_CACHE_LINE_SIZE * 2; + mvOsCacheLineFlushInv(NULL, pEth); + goto end; + } +#endif /* CONFIG_MV_ETH_NFP_PPP */ + + *(MV_U16*)(pEth + 2) = *(MV_U16*)(&pRt->routingInfo.dstMac[0]); + *(MV_U32*)(pEth + 4) = *(MV_U32*)(&pRt->routingInfo.dstMac[2]); + *(MV_U32*)(pEth + 8) = *(MV_U32*)(&pRt->routingInfo.srcMac[0]); + *(MV_U16*)(pEth + 12) = *(MV_U16*)(&pRt->routingInfo.srcMac[4]); +#ifdef CONFIG_MV_ETH_NFP_PPP + *(MV_U16*)(pEth + 14) = 0x0008; +#endif + + pIpHdr->ttl--; + +#ifdef CONFIG_MV_ETH_NFP_TOS + pIpHdr->tos = pRt->routingInfo.dscp; + pPkt->txq = pRt->routingInfo.txq; +#endif + +#ifdef CONFIG_MV_ETH_NFP_FDB_SUPPORT + /* find actual port inside bridge, otherwise br->xmit is called */ + if (mvFpFdbMember(ifIndex)) { + pFdb = mvFpFdbLookup(ifIndex, pEth+ETH_MV_HEADER_SIZE); + if (pFdb) { + MV_NFP_STAT( pFpStats->fdb_tx_found++ ); + return pFdb->fdbInfo.ifIndex; + } + } +#endif /* CONFIG_MV_ETH_NFP_FDB_SUPPORT */ + +end: + return ifIndex; +out: +#ifdef CONFIG_MV_ETH_NFP_PPP + /* restore original packet */ + if (pBuf->bufAddrShift) { + pBuf->bufPhysAddr += pBuf->bufAddrShift; + pBuf->bufVirtPtr += pBuf->bufAddrShift; + pBuf->dataSize -= pBuf->bufAddrShift; + pBuf->bufAddrShift = 0; + MV_NFP_STAT(pFpStats->ppp_rx_slow++); + } +#endif + MV_NFP_STAT(pFpStats->slowpath++); + return -1; +} + +void mvFpStatsPrint(MV_FP_STATS *pFpStats) +{ +#ifdef MV_FP_STATISTICS + mvOsPrintf( "\n====================================================\n" ); + mvOsPrintf( " NFP statistics"); + mvOsPrintf( "\n-------------------------------\n" ); + + mvOsPrintf( "nfp_process....................%10u\n", pFpStats->process ); + mvOsPrintf( "nfp_route_hit..................%10u\n", pFpStats->route_hit ); + mvOsPrintf( "nfp_route_miss.................%10u\n", pFpStats->route_miss ); + mvOsPrintf( "nfp_non_ip.....................%10u\n", pFpStats->non_ip ); + mvOsPrintf( "nfp_ip_frag....................%10u\n", pFpStats->ip_frag ); + mvOsPrintf( "nfp_slowpath...................%10u\n", pFpStats->slowpath); + mvOsPrintf( "nfp_multicast..................%10u\n", pFpStats->multicast ); + mvOsPrintf( "nfp_vlan_tagged................%10u\n", pFpStats->vlan_tagged ); + mvOsPrintf( "nfp_ttl_expired................%10u\n", pFpStats->ip_ttl_expired ); + +#ifdef CONFIG_MV_ETH_NFP_NAT_SUPPORT + mvOsPrintf( "nfp_nat_bad_proto..............%10u\n", pFpStats->nat_bad_proto); + mvOsPrintf( "nfp_nat_dnat_found.............%10u\n", pFpStats->dnat_found); + mvOsPrintf( "nfp_nat_snat_found.............%10u\n", pFpStats->snat_found); + mvOsPrintf( "nfp_nat_dnat_not_found.........%10u\n", pFpStats->dnat_not_found); + mvOsPrintf( "nfp_nat_snat_not_found.........%10u\n", pFpStats->snat_not_found); + mvOsPrintf( "nfp_nat_dnat_aware.............%10u\n", pFpStats->dnat_aware); + mvOsPrintf( "nfp_nat_snat_aware.............%10u\n", pFpStats->snat_aware); +#endif /* CONFIG_MV_ETH_NFP_NAT_SUPPORT */ + +#ifdef CONFIG_MV_ETH_NFP_FDB_SUPPORT + mvOsPrintf( "nfp_fdb_rx_local...............%10u\n", pFpStats->fdb_rx_local); + mvOsPrintf( "nfp_fdb_rx_unknown.............%10u\n", pFpStats->fdb_rx_unknown); + mvOsPrintf( "nfp_fdb_tx_found...............%10u\n", pFpStats->fdb_tx_found); + mvOsPrintf( "nfp_fdb_bridged................%10u\n", pFpStats->fdb_bridged); +#endif /* CONFIG_MV_ETH_NFP_FDB_SUPPORT */ + +#ifdef CONFIG_MV_ETH_NFP_PPP + mvOsPrintf( "nfp_ppp_rx.....................%10u\n", pFpStats->ppp_rx); + mvOsPrintf( "nfp_ppp_tx.....................%10u\n", pFpStats->ppp_tx); + mvOsPrintf( "nfp_ppp_err....................%10u\n", pFpStats->ppp_err); + mvOsPrintf( "nfp_ppp_rx_slow................%10u\n", pFpStats->ppp_rx_slow); + mvOsPrintf( "nfp_ppp_tx_slow................%10u\n", pFpStats->ppp_tx_slow); + mvOsPrintf( "nfp_ppp_rx_frag................%10u\n", pFpStats->ppp_rx_frag); + mvOsPrintf( "nfp_ppp_tx_esp.................%10u\n", pFpStats->ppp_tx_esp); + +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +#ifdef CONFIG_MV_ETH_NFP_SEC + mvOsPrintf( "nfp_sec_in.....................%10u\n", pFpStats->sec_in); + mvOsPrintf( "nfp_sec_in_drop................%10u\n", pFpStats->sec_in_drop); + mvOsPrintf( "nfp_sec_out....................%10u\n", pFpStats->sec_out); + mvOsPrintf( "nfp_sec_out_drop...............%10u\n", pFpStats->sec_out_drop); + mvOsPrintf( "nfp_sec_out_slow...............%10u\n", pFpStats->sec_out_slow); +#endif /* CONFIG_MV_ETH_NFP_SEC */ + + memset(pFpStats, 0, sizeof(MV_FP_STATS)); +#endif /* MV_FP_STATISTICS */ + + mvOsPrintf("\n"); + mvOsPrintf("Routing rules: Set=%u, Update=%u, Delete=%u, maxDepth=%u\n", + nfpRuleSetCount, nfpRuleUpdateCount, nfpRuleDeleteCount, + nfpHashMaxDepth); + +#ifdef CONFIG_MV_ETH_NFP_NAT_SUPPORT + mvOsPrintf("\n"); + mvOsPrintf("NAT rules: Set=%u, Update=%u, Delete=%u, maxDepth=%u\n", + natRuleSetCount, natRuleUpdateCount, natRuleDeleteCount, + natHashMaxDepth); +#endif /* CONFIG_MV_ETH_NFP_NAT_SUPPORT */ + +#ifdef CONFIG_MV_ETH_NFP_FDB_SUPPORT + mvOsPrintf("\n"); + mvOsPrintf("FDB rules: Set=%u, Update=%u, Delete=%u, maxDepth=%u\n", + fdbRuleSetCount, fdbRuleUpdateCount, fdbRuleDeleteCount, + fdbHashMaxDepth); +#endif /* CONFIG_MV_ETH_NFP_FDB_SUPPORT */ +} + diff --git a/board/mv_feroceon/mv_hal/eth/nfp/mvNfp.h b/board/mv_feroceon/mv_hal/eth/nfp/mvNfp.h new file mode 100644 index 0000000..a96d2b9 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/nfp/mvNfp.h @@ -0,0 +1,537 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfp.h - Header File for Marvell NFP (Routing and NAT) +* +* DESCRIPTION: +* This header file contains macros, typedefs and function declarations +* specific to the Marvell Network Fast Processing (Routing and NAT). +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvNfp_h__ +#define __mvNfp_h__ + +/* includes */ +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvStack.h" +#include "mv802_3.h" +#include "eth/mvEth.h" +#include "mvSysHwConfig.h" + +/* defines */ +#define ETH_FP_IFINDEX_MAX 128 +#define ETH_FP_PPPOE_HDR 8 /* PPP header is 6, PPPoE header is 2 */ +#define ETH_FP_MTU 1518 + ETH_MV_HEADER_SIZE /* maximum frame size incluing MH */ +#define ETH_FP_PPPOE_MTU (ETH_FP_MTU - ETH_FP_PPPOE_HDR) /* maximum frame size for PPPoE */ + + +/* uncomment to open some debug prints on adding and updating NFP rules */ +#define MV_FP_DEBUG +#undef MV_FP_DEBUG + +#ifdef MV_FP_DEBUG +# define MV_NFP_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) +#else +# define MV_NFP_DBG(fmt, arg...) +#endif + +#ifdef MV_FP_STATISTICS +# define MV_NFP_STAT(CODE) CODE; +#else +# define MV_NFP_STAT(CODE) +#endif + +/* enumerations */ +typedef enum { + MV_FP_ROUTE_CMD, /* perform NFP routing */ + MV_FP_DROP_CMD, /* drop packet */ + MV_FP_TO_STACK_CMD, /* pass packet to linux stack */ + MV_FP_DIP_CMD, /* replace DIP */ + MV_FP_SIP_CMD, /* replace SIP */ + MV_FP_DPORT_CMD, /* replace DPORT */ + MV_FP_SPORT_CMD, /* replace SPORT */ + MV_FP_BRIDGE_CMD, /* perform fast path bridging */ + MV_FP_PPP_CMD, /* perform fast path pppoe */ +} MV_FP_CMD_TYPE; + +typedef enum { + MV_NFP_DROP = -3, + MV_NFP_STOLEN = -2, + MV_NFP_NONE = -1, + /* positive values are valid */ +} MV_NFP_IF_INDEX; + +#define MV_FP_DIP_CMD_MAP (1 << MV_FP_DIP_CMD) +#define MV_FP_DPORT_CMD_MAP (1 << MV_FP_DPORT_CMD) +#define MV_FP_DNAT_CMD_MAP (MV_FP_DIP_CMD_MAP | MV_FP_DPORT_CMD_MAP) + +#define MV_FP_SIP_CMD_MAP (1 << MV_FP_SIP_CMD) +#define MV_FP_SPORT_CMD_MAP (1 << MV_FP_SPORT_CMD) +#define MV_FP_SNAT_CMD_MAP (MV_FP_SIP_CMD_MAP | MV_FP_SPORT_CMD_MAP) + +typedef enum { + MV_FP_STATIC_RULE, /* a static rule created by the user */ + MV_FP_DYNAMIC_RULE /* a dynamic rule */ + +} MV_FP_RULE_TYPE; + +/* structure definitions (used by the NFP Manager and the NFP Database)*/ +typedef struct { + MV_FP_CMD_TYPE actionType; + MV_U32 old_count; + MV_U32 new_count; + MV_FP_RULE_TYPE ruleType; + int dnat_aware_refcnt; + int snat_aware_refcnt; + +} MV_FP_RULE_MGMT_INFO; + +typedef struct { + MV_U32 dstIp; + MV_U32 srcIp; + MV_U32 defGtwIp; + MV_U8 dscp; + MV_U8 txq; + MV_U16 reserved1; + MV_U8 reserved2; + MV_U8 aware_flags; + /* dstMac should be 2 byte aligned */ + MV_U8 dstMac[MV_MAC_ADDR_SIZE]; + MV_U8 srcMac[MV_MAC_ADDR_SIZE]; + MV_U8 inIfIndex; /* Linux interface index */ + MV_U8 outIfIndex; /* Linux interface index */ +} MV_FP_RULE_ROUTING_INFO; + +typedef struct _mv_fp_rule { + struct _mv_fp_rule *next; + + MV_FP_RULE_MGMT_INFO mgmtInfo; + MV_FP_RULE_ROUTING_INFO routingInfo; + +} MV_FP_RULE; + +struct ruleHashBucket { + MV_FP_RULE *ruleChain; /* This is an entry in the rule hash table. */ + + /* Add additional fields (such as a lock) here if required */ +}; + +#define MV_JHASH_MIX(a, b, c) \ +{ \ + a -= b; a -= c; a ^= (c>>13); \ + b -= c; b -= a; b ^= (a<<8); \ + c -= a; c -= b; c ^= (b>>13); \ + a -= b; a -= c; a ^= (c>>12); \ + b -= c; b -= a; b ^= (a<<16); \ + c -= a; c -= b; c ^= (b>>5); \ + a -= b; a -= c; a ^= (c>>3); \ + b -= c; b -= a; b ^= (a<<10); \ + c -= a; c -= b; c ^= (b>>15); \ +} + +/* The golden ration: an arbitrary value */ +#define MV_JHASH_GOLDEN_RATIO 0x9e3779b9 + +extern MV_U32 fp_ip_jhash_iv; + +static INLINE MV_U32 mv_jhash_3words(MV_U32 a, MV_U32 b, MV_U32 c, MV_U32 initval) +{ + a += MV_JHASH_GOLDEN_RATIO; + b += MV_JHASH_GOLDEN_RATIO; + c += initval; + MV_JHASH_MIX(a, b, c); + + return c; +} +#ifdef CONFIG_MV_ETH_NFP_NAT_SUPPORT + +typedef struct _mv_fp_nat_rule { + struct _mv_fp_nat_rule *next; + MV_U32 count; + MV_U32 new_count; + + /* Original packet information */ + /* Fields will contain invalid values if they are irrelevant */ + MV_U32 srcIp; + MV_U32 dstIp; + MV_U16 srcPort; + MV_U16 dstPort; + MV_U8 proto; + + /* NAT information */ + MV_U8 flags; + MV_U32 newIp; + MV_U16 newPort; + +} MV_FP_NAT_RULE; + +struct natRuleHashBucket { + MV_FP_NAT_RULE *natRuleChain; /* This is an entry in the NAT rule hash table. */ + + /* Add additional fields (such as a lock) here if required */ +}; + +extern struct natRuleHashBucket *natRuleDb; +extern MV_U32 natRuleDbSize; +extern MV_U32 natRuleUpdateCount, natRuleSetCount, natRuleDeleteCount; +extern MV_U32 natHashMaxDepth; + +#endif /* CONFIG_MV_ETH_NFP_NAT_SUPPORT */ + +/* + * PPPoE Support + */ +#ifdef CONFIG_MV_ETH_NFP_PPP + +typedef struct +{ + MV_U16 tag; + MV_U8 da[MV_MAC_ADDR_SIZE]; + MV_U8 sa[MV_MAC_ADDR_SIZE]; + MV_U16 ethertype; + MV_U8 version; + MV_U8 code; + MV_U16 session; + MV_U16 len; + MV_U16 proto; +} __attribute__((packed)) MV_PPPoE_HEADER; + +typedef struct { + union { + MV_PPPoE_HEADER ppp; + MV_U32 u32[6]; + } u; + MV_U32 if_ppp; /* e.g. ppp0 */ + MV_U32 if_eth; /* e.g. eth0 */ + MV_U32 channel; +} MV_FP_RULE_PPP_INFO; + +typedef struct _mv_fp_ppp_rule { + struct _mv_fp_ppp_rule *next; + + MV_FP_RULE_MGMT_INFO mgmtInfo; + MV_FP_RULE_PPP_INFO pppInfo; + +} MV_FP_PPP_RULE; + +extern MV_FP_PPP_RULE pppOpen[]; + +#endif /* CONFIG_MV_ETH_NFP_PPP */ + + +/* + * 802.1D Support + */ +#ifdef CONFIG_MV_ETH_NFP_FDB_SUPPORT + +#define MV_FP_FDB_IS_LOCAL 1 + +typedef struct { + MV_U16 flags; + MV_U8 mac[6]; + MV_U32 ifIndex; + MV_U32 bridge; +} MV_FP_RULE_FDB_INFO; + +typedef struct _mv_fp_fdb_rule { + struct _mv_fp_fdb_rule *next; + + MV_FP_RULE_MGMT_INFO mgmtInfo; + MV_FP_RULE_FDB_INFO fdbInfo; + +} MV_FP_FDB_RULE; + +struct fdbRuleHashBucket { + MV_FP_FDB_RULE *ruleChain; +}; + +extern struct fdbRuleHashBucket *fdbRuleDb; +extern MV_U32 fdbRuleDbSize; +extern MV_U32 fdbMember[]; +extern MV_U32 fdbRuleUpdateCount, fdbRuleSetCount, fdbRuleDeleteCount; +extern MV_U32 fdbHashMaxDepth; + +#endif /* CONFIG_MV_ETH_NFP_FDB_SUPPORT */ + +typedef struct +{ + MV_U32 process; + MV_U32 route_miss; + MV_U32 route_hit; + MV_U32 ip_ttl_expired; + MV_U32 slowpath; + MV_U32 multicast; + MV_U32 non_ip; + MV_U32 ip_frag; + MV_U32 vlan_tagged; + +#ifdef CONFIG_MV_ETH_NFP_NAT_SUPPORT + MV_U32 nat_bad_proto; + MV_U32 dnat_aware; + MV_U32 snat_aware; + MV_U32 dnat_found; + MV_U32 snat_found; + MV_U32 dnat_not_found; + MV_U32 snat_not_found; +#endif /* CONFIG_MV_ETH_NFP_NAT_SUPPORT */ + +#ifdef CONFIG_MV_ETH_NFP_FDB_SUPPORT + MV_U32 fdb_rx_local; + MV_U32 fdb_rx_unknown; + MV_U32 fdb_tx_found; + MV_U32 fdb_bridged; +#endif /* CONFIG_MV_ETH_NFP_FDB_SUPPORT */ + +#ifdef CONFIG_MV_ETH_NFP_PPP + MV_U32 ppp_rx; + MV_U32 ppp_rx_slow; + MV_U32 ppp_rx_frag; + MV_U32 ppp_tx; + MV_U32 ppp_tx_slow; + MV_U32 ppp_tx_esp; + MV_U32 ppp_err; +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +#ifdef CONFIG_MV_ETH_NFP_SEC + MV_U32 sec_in; + MV_U32 sec_in_drop; + MV_U32 sec_out; + MV_U32 sec_out_drop; + MV_U32 sec_out_slow; +#endif /* CONFIG_MV_ETH_NFP_SEC */ + +} MV_FP_STATS; + + +/* Initialize NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbInit(MV_U32 dbSize); +/* Clear NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbClear(void); +/* Free Rule Database memory */ +void mvFpRuleDbDestroy(void); +/* Print NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbPrint(void); +/* Copy all the information from src_rule to new_rule */ +/* Warning - doesn't perform any checks on memory, just copies */ +/* count is set to zero in new_rule */ +/* Note: the next pointer is not updated . */ +void mvFpRuleCopy(MV_FP_RULE *newRule, const MV_FP_RULE *srcRule); +/* Get the maximum count value for a rule with srcIp == given ip */ +MV_U32 mvFpMaxArpCountGet(MV_U32 ip); +/* Get the count value for a rule that matches the given SIP, DIP */ +MV_U32 mvFpRouteCountGet(MV_U32 srcIp, MV_U32 dstIp); +/* Set a Routing Rule: create a new rule or update an existing rule */ +/* in the Routing + ARP information table */ +MV_STATUS mvFpRuleSet(MV_FP_RULE *rule); +/* Delete a specified rule from the Routing + ARP information table */ +MV_STATUS mvFpRuleDelete(MV_FP_RULE *rule); +/* Set a Routing ToS Rule */ +MV_STATUS mvFpToSSet(MV_FP_RULE *rule); +/* Print a Rule */ +void mvFpRulePrint(const MV_FP_RULE *rule); +/* Enable NFP */ +void mvFpEnable(void); +/* Give all packets to Linux IP stack */ +void mvFpDisable(void); +MV_STATUS mvFpInit(void); +int mvFpProcess(MV_U32 ifIndex, MV_PKT_INFO* pPkt, MV_FP_STATS* pFpStats); +void mvFpStatsPrint(MV_FP_STATS *pFpStats); + +/* NAT SUPPORT Functions */ + +#ifdef CONFIG_MV_ETH_NFP_NAT_SUPPORT +/* Find and return the first matching rule */ +static INLINE MV_FP_NAT_RULE* mvFpNatRuleFind(MV_U32 dstIp, MV_U32 srcIp, + MV_U8 proto, MV_U16 dport, MV_U16 sport) +{ + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE* pNatRule; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32)((dport << 16) | sport), + (MV_U32)((fp_ip_jhash_iv << 8) | proto)); + hash_tr = hash & (natRuleDbSize - 1); +/* + mvOsPrintf("mvFpNatRuleFind: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%08x (0x%x)\n", + dstIp, srcIp, proto, dport, sport, hash, hash_tr); +*/ + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while(pNatRule) + { + /* look for a matching rule */ + if( (pNatRule->dstIp == dstIp) && + (pNatRule->srcIp == srcIp) && + (pNatRule->proto == proto) && + (pNatRule->dstPort == dport) && + (pNatRule->srcPort == sport) ) + { + pNatRule->new_count++; + return pNatRule; + } + pNatRule = pNatRule->next; + } + return NULL; +} + +/* Initialize NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbInit(MV_U32 dbSize); + +/* Clear NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbClear(void); + +/* Free NAT Database memory */ +void mvFpNatDbDestroy(void); + +/* Set a NAT rule: create a new rule or update an existing rule in the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleSet(MV_FP_NAT_RULE *natRule); + +MV_STATUS mvFpRuleAwareSet(MV_FP_RULE *pSetRule); + +/* Delete a specified NAT rule from the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleDelete(MV_FP_NAT_RULE *natRule); + +/* Get the count value for a NAT rule */ +MV_U32 mvFpNatCountGet(MV_U32 srcIp, MV_U32 dstIp, MV_U16 srcPort, MV_U16 dstPort, MV_U8 proto); + +/* Print NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbPrint(void); + +/* Print a NAT Rule */ +void mvFpNatRulePrint(const MV_FP_NAT_RULE *rule); + +/* Extract dstPort and srcPort values from the packet */ +MV_U8 mvFpNatPortsGet(MV_IP_HEADER* pIpHdr, MV_U16* pDstPort, MV_U16* pSrcPort); + +int mvFpNatPktUpdate(MV_IP_HEADER* pIpHdr, MV_FP_NAT_RULE* pDnatRule, MV_FP_NAT_RULE* pSnatRule); + +#endif /* CONFIG_MV_ETH_NFP_NAT_SUPPORT */ + + +#ifdef CONFIG_MV_ETH_NFP_FDB_SUPPORT + +/* Init NFP Bridge Rule Database */ +MV_STATUS mvFpFdbInit(MV_U32 dbSize); + +/* Clear NFP Bridge Rule Database */ +MV_STATUS mvFpFdbClear(void); + +/* Destroy NFP Bridge Rule Database */ +void mvFpFdbDestroy(void); + +/* Add NFP Bridge Rule */ +MV_STATUS mvFpFdbRuleSet(MV_FP_FDB_RULE *rule); + +/* Delete NFP Bridge Rule Database */ +MV_STATUS mvFpFdbRuleDel(MV_FP_FDB_RULE *rule); + +/* Aging NFP Bridge Rule Database */ +MV_U32 mvFpFdbRuleAge(MV_FP_FDB_RULE *rule); + +/* Print NFP Bridge Rule Database */ +MV_STATUS mvFpFdbPrint(void); + +#endif /* CONFIG_MV_ETH_NFP_FDB_SUPPORT */ + +#ifdef CONFIG_MV_ETH_NFP_PPP + +/* Init NFP PPPoE Rule Database */ +MV_STATUS mvFpPppInit(void); + +/* Clear NFP PPPoE Rule Database */ +MV_STATUS mvFpPppClear(void); + +/* Destroy NFP PPPoE Rule Database */ +void mvFpPppDestroy(void); + +/* Add NFP PPPoE Rule */ +MV_STATUS mvFpPppRuleSet(MV_FP_PPP_RULE *rule); + +/* Delete NFP PPPoE Rule Database */ +MV_STATUS mvFpPppRuleDel(MV_FP_PPP_RULE *rule); + +/* Aging NFP PPPoE Rule Database */ +MV_U32 mvFpPppRuleAge(MV_FP_PPP_RULE *rule); + +/* Print NFP PPPoE Rule Database */ +MV_STATUS mvFpPppPrint(void); + +/* Add PPPoE header */ +int mvFpPPPoE(MV_U32 ifIndex, MV_PKT_INFO* pPkt, MV_FP_STATS* pFpStats); + +/* Get physical interface the PPP runs over */ +MV_U32 mvFpPppPhyIf(MV_U32 ifIndex); + +#endif /* CONFIG_MV_ETH_NFP_PPP */ + +#ifdef CONFIG_MV_ETH_NFP_SEC +MV_VOID mvNfpSecDbPrint(MV_VOID); +#endif /* CONFIG_MV_ETH_NFP_SEC */ + +#endif /* __mvNfp_h__ */ diff --git a/board/mv_feroceon/mv_hal/eth/nfp/mvNfpFdb.c b/board/mv_feroceon/mv_hal/eth/nfp/mvNfpFdb.c new file mode 100644 index 0000000..8d94c62 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/nfp/mvNfpFdb.c @@ -0,0 +1,317 @@ +/******************************************************************************* +Copyright (C) Marvell Interfdbional Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +Interfdbional Ltd. and/or its affiliates ("Marvell") under the following +alterfdbive licensing terms. Once you have made an election to distribute the +File under one of the following license alterfdbives, please (i) delete this +introductory statement regarding license alterfdbives, (ii) delete the two +license alterfdbives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvFastPath.c - Marvell Fast Route Routing and Bridge +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mvDebug.h" +#include "eth/nfp/mvNfp.h" +#include "eth/mvEth.h" + + +struct fdbRuleHashBucket *fdbRuleDb; +MV_U32 fdbRuleDbSize; +MV_U32 fdbMember[ETH_FP_IFINDEX_MAX]; +MV_U32 fdbRuleUpdateCount = 0; +MV_U32 fdbRuleSetCount = 0; +MV_U32 fdbRuleDeleteCount = 0; +MV_U32 fdbHashMaxDepth; + + +MV_STATUS mvFpFdbInit(MV_U32 dbSize) +{ + fdbRuleDb = (struct fdbRuleHashBucket *)mvOsMalloc(sizeof(struct fdbRuleHashBucket)*dbSize); + if (fdbRuleDb == NULL) { + mvOsPrintf("NFP (fdb): not enough memory\n"); + return MV_NO_RESOURCE; + } + fdbRuleDbSize = dbSize; + memset(fdbRuleDb, 0, sizeof(struct fdbRuleHashBucket)*fdbRuleDbSize); + memset(fdbMember, 0, sizeof(fdbMember)); + + mvOsPrintf("NFP (fdb) init %d entries, %d bytes\n", + fdbRuleDbSize, sizeof(struct fdbRuleHashBucket)*fdbRuleDbSize); + return MV_OK; +} + +/* Clear Fast Route Bridge Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpFdbClear(void) +{ + MV_U32 i = fdbRuleDbSize; + MV_FP_FDB_RULE *rule, *tmp; + + if (fdbRuleDb != NULL) + return MV_NOT_INITIALIZED; + + while (i--) { + rule = fdbRuleDb[i].ruleChain; + while (rule) { + tmp = rule; + rule = rule->next; + mvOsFree(tmp); + } + fdbRuleDb[i].ruleChain = NULL; + } + return MV_OK; +} + +void mvFpFdbDestroy(void) +{ + if (fdbRuleDb != NULL) + mvOsFree(fdbRuleDb); +} + +static INLINE int mvFpFdbRuleCmp(MV_FP_RULE_FDB_INFO *rule1, MV_FP_RULE_FDB_INFO *rule2) +{ + return !((rule1->bridge == rule2->bridge) && + (rule1->ifIndex == rule2->ifIndex) && + !memcmp(rule1->mac, rule2->mac, 6)); +} + +static INLINE MV_U32 mvFpFdbRuleHash(MV_FP_FDB_RULE *rule) +{ + return mv_jhash_3words( rule->fdbInfo.bridge, + 0,*(MV_U32*)(rule->fdbInfo.mac+2), fp_ip_jhash_iv); +} + +MV_STATUS mvFpFdbRuleSet(MV_FP_FDB_RULE *newrule) +{ + int depth = 0; + MV_U32 hash; + MV_FP_FDB_RULE* rule; + + /* ignore foreign ifindex */ + if (newrule->fdbInfo.ifIndex >= ETH_FP_IFINDEX_MAX) + return MV_OUT_OF_RANGE; + + hash = mvFpFdbRuleHash(newrule); + hash &= (fdbRuleDbSize - 1); + + rule = fdbRuleDb[hash].ruleChain; + while (rule) { + if (!mvFpFdbRuleCmp(&rule->fdbInfo, &newrule->fdbInfo)) + { + fdbRuleUpdateCount++; + goto out; + } + depth++; + rule = rule->next; + } + fdbRuleSetCount++; + if(depth > fdbHashMaxDepth) + fdbHashMaxDepth = depth; + + rule = mvOsMalloc(sizeof(MV_FP_FDB_RULE)); + + if (!rule) { + mvOsPrintf("NFP (fdb): can't allocate new rule\n"); + return MV_FAIL; + } + + /* FIXME: No spinlocks */ + rule->next = fdbRuleDb[hash].ruleChain; + fdbRuleDb[hash].ruleChain = rule; +out: + mvOsMemcpy(rule, newrule, sizeof(MV_FP_FDB_RULE)); + + if (rule->fdbInfo.flags & MV_FP_FDB_IS_LOCAL) { + fdbMember[rule->fdbInfo.ifIndex] = rule->fdbInfo.bridge; + fdbMember[rule->fdbInfo.bridge] = rule->fdbInfo.bridge; + } + + MV_NFP_DBG("NFP (fdb): new bridge=%d ifIndex=%d %02X:%02X:%02X:%02X:%02X:%02X flags=%x\n", + rule->fdbInfo.bridge, rule->fdbInfo.ifIndex, + rule->fdbInfo.mac[0], rule->fdbInfo.mac[1], rule->fdbInfo.mac[2], + rule->fdbInfo.mac[3], rule->fdbInfo.mac[4], rule->fdbInfo.mac[5], + rule->fdbInfo.flags); + + return MV_OK; +} + +MV_STATUS mvFpFdbRuleDel(MV_FP_FDB_RULE *oldrule) +{ + MV_U32 hash; + MV_FP_FDB_RULE* rule, *prev; + + /* ignore foreign ifindex */ + if (oldrule->fdbInfo.ifIndex >= ETH_FP_IFINDEX_MAX) + return MV_OUT_OF_RANGE; + + if (oldrule->fdbInfo.flags & MV_FP_FDB_IS_LOCAL) { + fdbMember[oldrule->fdbInfo.ifIndex] = 0; + fdbMember[oldrule->fdbInfo.bridge] = 0; + MV_NFP_DBG("NFP (fdb): del member bridge=%d ifIndex=%d\n", + oldrule->fdbInfo.bridge, oldrule->fdbInfo.ifIndex); + } + + hash = mvFpFdbRuleHash(oldrule); + hash &= (fdbRuleDbSize - 1); + + rule = fdbRuleDb[hash].ruleChain; + prev = NULL; + + while (rule) { + if (!mvFpFdbRuleCmp(&rule->fdbInfo, &oldrule->fdbInfo)) { + + if (prev) + prev->next = rule->next; + else + fdbRuleDb[hash].ruleChain = rule->next; + + fdbRuleDeleteCount++; + MV_NFP_DBG("NFP (fdb): del bridge=%d ifIndex=%d %02X:%02X:%02X:%02X:%02X:%02X flags=%x count=%d\n", + rule->fdbInfo.bridge, rule->fdbInfo.ifIndex, + rule->fdbInfo.mac[0], rule->fdbInfo.mac[1], rule->fdbInfo.mac[2], + rule->fdbInfo.mac[3], rule->fdbInfo.mac[4], rule->fdbInfo.mac[5], + rule->fdbInfo.flags, rule->mgmtInfo.new_count); + + mvOsFree(rule); + return MV_OK; + } + + prev = rule; + rule = rule->next; + } + + return MV_NOT_FOUND; +} + +MV_U32 mvFpFdbRuleAge(MV_FP_FDB_RULE *oldrule) +{ + MV_U32 hash, age; + MV_FP_FDB_RULE* rule, *prev; + + /* ignore foreign ifindex */ + if (oldrule->fdbInfo.ifIndex >= ETH_FP_IFINDEX_MAX) + return 0; + + hash = mvFpFdbRuleHash(oldrule); + hash &= (fdbRuleDbSize - 1); + + rule = fdbRuleDb[hash].ruleChain; + prev = NULL; + + while (rule) { + if (!mvFpFdbRuleCmp(&rule->fdbInfo, &oldrule->fdbInfo)) { + + MV_NFP_DBG("NFP (fdb): age bridge=%d ifIndex=%d %02X:%02X:%02X:%02X:%02X:%02X flags=%x age=%d\n", + rule->fdbInfo.bridge, rule->fdbInfo.ifIndex, + rule->fdbInfo.mac[0], rule->fdbInfo.mac[1], rule->fdbInfo.mac[2], + rule->fdbInfo.mac[3], rule->fdbInfo.mac[4], rule->fdbInfo.mac[5], + rule->fdbInfo.flags, rule->mgmtInfo.new_count); + + age = rule->mgmtInfo.new_count; + rule->mgmtInfo.new_count = 0; + return age; + + } + + prev = rule; + rule = rule->next; + } + + return 0; +} + +static void mvFpFdbRulePrint(MV_FP_FDB_RULE *rule, MV_U32 hash) +{ + mvOsPrintf("NFP (fdb): 0x%x bridge=%d ifIndex=%d %02X:%02X:%02X:%02X:%02X:%02X flags=%x count=%d\n", + mvFpFdbRuleHash((MV_FP_FDB_RULE*)rule), + rule->fdbInfo.bridge, rule->fdbInfo.ifIndex, + rule->fdbInfo.mac[0], rule->fdbInfo.mac[1], rule->fdbInfo.mac[2], + rule->fdbInfo.mac[3], rule->fdbInfo.mac[4], rule->fdbInfo.mac[5], + rule->fdbInfo.flags, rule->mgmtInfo.new_count); +} + +MV_STATUS mvFpFdbPrint(void) +{ + MV_U32 i = fdbRuleDbSize; + MV_FP_FDB_RULE *rule; + + for (i=0; inext; + } + } + return MV_OK; +} + + diff --git a/board/mv_feroceon/mv_hal/eth/nfp/mvNfpNat.c b/board/mv_feroceon/mv_hal/eth/nfp/mvNfpNat.c new file mode 100644 index 0000000..ab881a5 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/nfp/mvNfpNat.c @@ -0,0 +1,399 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "mvTypes.h" +#include "mvOs.h" +#include "mvStack.h" +#include "mvDebug.h" +#include "eth/nfp/mvNfp.h" +#include "eth/mvEth.h" + + +struct natRuleHashBucket *natRuleDb; +MV_U32 natRuleDbSize; + +MV_U32 natRuleUpdateCount = 0; +MV_U32 natRuleSetCount = 0; +MV_U32 natRuleDeleteCount = 0; +MV_U32 natHashMaxDepth = 0; + +/* Initialize NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbInit(MV_U32 dbSize) +{ + natRuleDb = (struct natRuleHashBucket *)mvOsMalloc(sizeof(struct natRuleHashBucket)*dbSize); + if (natRuleDb == NULL) { + mvOsPrintf("NFP NAT Rule DB: Not Enough Memory\n"); + return MV_NO_RESOURCE; + } + natRuleDbSize = dbSize; + memset(natRuleDb, 0, sizeof(struct natRuleHashBucket)*natRuleDbSize); + + natRuleSetCount = natRuleDeleteCount = natRuleUpdateCount = 0; + + mvOsPrintf("mvFpNatDb (%p): %d entries, %d bytes\n", + natRuleDb, natRuleDbSize, sizeof(struct natRuleHashBucket)*natRuleDbSize); + + return MV_OK; +} + +/* Clear NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbClear(void) +{ + MV_U32 i = 0; + MV_FP_NAT_RULE *currRule; + MV_FP_NAT_RULE *tmpRule; + + if (natRuleDb == NULL) + return MV_NOT_INITIALIZED; + + for (i = 0; i < natRuleDbSize; i++) { + currRule = natRuleDb[i].natRuleChain; + while (currRule != NULL) { + tmpRule = currRule; + currRule = currRule->next; + mvOsFree(tmpRule); + } + natRuleDb[i].natRuleChain = NULL; + } + return MV_OK; +} + +/* Free NAT Database memory */ +void mvFpNatDbDestroy(void) +{ + if (natRuleDb != NULL) + mvOsFree(natRuleDb); +} + +static void mvFpNatRuleUpdate(MV_FP_NAT_RULE *dstRule, const MV_FP_NAT_RULE *srcRule) +{ + dstRule->flags = srcRule->flags; + dstRule->newIp = srcRule->newIp; + dstRule->newPort = srcRule->newPort; + dstRule->new_count = srcRule->new_count; +} + +/* Set a NAT rule: create a new rule or update an existing rule in the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleSet(MV_FP_NAT_RULE *pSetRule) +{ + int depth = 0; + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE *pNatRule, *pNewRule; + + hash = mv_jhash_3words(pSetRule->dstIp, pSetRule->srcIp, + (MV_U32)((pSetRule->dstPort << 16) | pSetRule->srcPort), + (MV_U32)((fp_ip_jhash_iv << 8) | pSetRule->proto)); + hash_tr = hash & (natRuleDbSize - 1); + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while(pNatRule) + { + /* look for a matching rule */ + if( (pNatRule->dstIp == pSetRule->dstIp) && + (pNatRule->srcIp == pSetRule->srcIp) && + (pNatRule->proto == pSetRule->proto) && + (pNatRule->dstPort == pSetRule->dstPort) && + (pNatRule->srcPort == pSetRule->srcPort) ) + { + /* update rule */ + mvFpNatRuleUpdate(pNatRule, pSetRule); + natRuleUpdateCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf("UpdNAT_%03u: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%04x, flags=0x%02x\n", + natRuleUpdateCount, pNatRule->dstIp, pNatRule->srcIp, pNatRule->proto, + MV_16BIT_BE(pNatRule->dstPort), MV_16BIT_BE(pNatRule->srcPort), hash_tr, pNatRule->flags); +#endif + return MV_OK; + } + pNatRule = pNatRule->next; + } + /* Allocate new entry */ + pNewRule = mvOsMalloc(sizeof(MV_FP_NAT_RULE)); + if(pNewRule == NULL) + { + mvOsPrintf("mvFpNatRuleSet: Can't allocate new rule\n"); + return MV_FAIL; + } + + memcpy(pNewRule, pSetRule, sizeof(*pNewRule)); + pNewRule->next = NULL; + + if(natRuleDb[hash_tr].natRuleChain == NULL) + { + natRuleDb[hash_tr].natRuleChain = pNewRule; + } + else + { + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while (pNatRule->next != NULL) + { + depth++; + pNatRule = pNatRule->next; + } + + pNatRule->next = pNewRule; + } + if(depth > natHashMaxDepth) + natHashMaxDepth = depth; + + natRuleSetCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf("SetNAT_%03u: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%04x, flags=0x%02x\n", + natRuleSetCount, pNewRule->dstIp, pNewRule->srcIp, pNewRule->proto, + MV_16BIT_BE(pNewRule->dstPort), MV_16BIT_BE(pNewRule->srcPort), hash_tr, pNewRule->flags); +#endif + return MV_OK; +} + +/* Delete a specified NAT rule from the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleDelete(MV_FP_NAT_RULE *natRule) +{ + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE *currRule, *prevRule; + + natRuleDeleteCount++; + + hash = mv_jhash_3words(natRule->dstIp, natRule->srcIp, + (MV_U32)((natRule->dstPort << 16) | natRule->srcPort), + (MV_U32)((fp_ip_jhash_iv << 8) | natRule->proto)); + hash_tr = hash & (natRuleDbSize - 1); + + prevRule = NULL; + for (currRule = natRuleDb[hash_tr].natRuleChain; + currRule != NULL; + prevRule = currRule, currRule = currRule->next) + { + if (currRule->srcIp == natRule->srcIp && + currRule->dstIp == natRule->dstIp && + currRule->srcPort == natRule->srcPort && + currRule->dstPort == natRule->dstPort && + currRule->proto == natRule->proto ) + { + if (prevRule == NULL) + natRuleDb[hash_tr].natRuleChain = currRule->next; + else + prevRule->next = currRule->next; + +#ifdef MV_FP_DEBUG + mvOsPrintf("DelNAT_%03u: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%04x\n", + natRuleDeleteCount, currRule->dstIp, currRule->srcIp, currRule->proto, + MV_16BIT_BE(currRule->dstPort), MV_16BIT_BE(currRule->srcPort), hash_tr); +#endif + mvOsFree(currRule); + return MV_OK; + } + } + return MV_NOT_FOUND; +} + +int mvFpNatPktUpdate(MV_IP_HEADER* pIpHdr, MV_FP_NAT_RULE* pDnatRule, MV_FP_NAT_RULE* pSnatRule) +{ + MV_UDP_HEADER *pUdpHdr; + MV_TCP_HEADER *pTcpHdr; + MV_ICMP_ECHO_HEADER *pIcmpHdr; + int hdr_size = 0; + MV_U16 *pDstPort=NULL, *pSrcPort=NULL; + + switch(pIpHdr->protocol) + { + case MV_IP_PROTO_TCP: + pTcpHdr = (MV_TCP_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + pDstPort = &pTcpHdr->dest; + pSrcPort = &pTcpHdr->source; + hdr_size = sizeof(MV_TCP_HEADER); + break; + + case MV_IP_PROTO_UDP: + pUdpHdr = (MV_UDP_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + pDstPort = &pUdpHdr->dest; + pSrcPort = &pUdpHdr->source; + hdr_size = sizeof(MV_UDP_HEADER); + break; + + case MV_IP_PROTO_ICMP: + pIcmpHdr = (MV_ICMP_ECHO_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + if( (pIcmpHdr->type == MV_ICMP_ECHO) || (pIcmpHdr->type == MV_ICMP_ECHOREPLY) ) + { + pDstPort = &pIcmpHdr->id; + pSrcPort = &pIcmpHdr->id; + hdr_size = sizeof(MV_ICMP_ECHO_HEADER); + } + else + { + mvOsPrintf("Wrong ICMP type: 0x%x\n", pIcmpHdr->type & 0xFF); + } + break; + + case MV_IP_PROTO_ZERO_HOP: + /* Do nothing - only IP addresses are updated for this protocol */ + break; + + default: + mvOsPrintf("Unexpected IP protocol: 0x%x\n", + pIpHdr->protocol); + } + if(pDnatRule != NULL) + { + if(pDnatRule->flags & MV_FP_DIP_CMD_MAP) + pIpHdr->dstIP = pDnatRule->newIp; + if( (pDnatRule->flags & MV_FP_DPORT_CMD_MAP) && + (pDstPort != NULL) ) + *pDstPort = pDnatRule->newPort; + } + + if(pSnatRule != NULL) + { + if(pSnatRule->flags & MV_FP_SIP_CMD_MAP) + pIpHdr->srcIP = pSnatRule->newIp; + + if( (pSnatRule->flags & MV_FP_SPORT_CMD_MAP) && + (pSrcPort != NULL) ) + *pSrcPort = pSnatRule->newPort; + } + return hdr_size; +} + +/* Print a NFP NAT Rule */ +void mvFpNatRulePrint(const MV_FP_NAT_RULE *rule) +{ + /* Note: some of the fields in the NAT rule may contain invalid values */ + mvOsPrintf("Original packet: "); + mvOsPrintf("SIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->srcIp)), + mvOsPrintf(", DIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->dstIp)), + mvOsPrintf(", SPort=%d", MV_16BIT_BE(rule->srcPort)); + mvOsPrintf(", DPort=%d", MV_16BIT_BE(rule->dstPort)); + mvOsPrintf("\nNAT Info: "); + mvOsPrintf("count=%u, new_count=%u, flags=0x%x", rule->count, rule->new_count, rule->flags); + mvOsPrintf(", newIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->newIp)); + mvOsPrintf(", newPort=%d", MV_16BIT_BE(rule->newPort)); + mvOsPrintf("\n"); +} + +/* Print NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbPrint(void) +{ + MV_U32 count, i = 0; + MV_FP_NAT_RULE *currRule; + + mvOsPrintf("\nPrinting NFP NAT Rule Database: \n"); + count = 0; + for (i=0; iflags != 0) || (currRule->new_count > 0) ) + { + mvOsPrintf("%03u: Rule=%p, Next=%p\n", count, currRule, currRule->next); + mvFpNatRulePrint(currRule); + } + currRule = currRule->next; + count++; + } + } + return MV_OK; +} + +/* Get the count value for a NAT rule */ +MV_U32 mvFpNatCountGet(MV_U32 srcIp, MV_U32 dstIp, MV_U16 srcPort, MV_U16 dstPort, MV_U8 proto) +{ + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE *pNatRule; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32)((dstPort << 16) | srcPort), + (MV_U32)((fp_ip_jhash_iv << 8) | proto)); + hash_tr = hash & (natRuleDbSize - 1); + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while(pNatRule) + { + /* look for a matching rule */ + if( (pNatRule->dstIp == dstIp) && + (pNatRule->srcIp == srcIp) && + (pNatRule->proto == proto) && + (pNatRule->dstPort == dstPort) && + (pNatRule->srcPort == srcPort) ) + { + int count = pNatRule->new_count; + pNatRule->count += count; + pNatRule->new_count = 0; + return count; + } + pNatRule = pNatRule->next; + } + return 0; +} + diff --git a/board/mv_feroceon/mv_hal/eth/nfp/mvNfpPpp.c b/board/mv_feroceon/mv_hal/eth/nfp/mvNfpPpp.c new file mode 100644 index 0000000..eed8530 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/nfp/mvNfpPpp.c @@ -0,0 +1,323 @@ +/******************************************************************************* +Copyright (C) Marvell Interpppional Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +Interpppional Ltd. and/or its affiliates ("Marvell") under the following +alterpppive licensing terms. Once you have made an election to distribute the +File under one of the following license alterpppives, please (i) delete this +introductory statement regarding license alterpppives, (ii) delete the two +license alterpppives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvPPP.c - Marvell Fast Route PPP Processing +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + + +/* includes */ +#include "mvTypes.h" +#include "mvOs.h" +#include "mvStack.h" +#include "mvDebug.h" +#include "eth/nfp/mvNfp.h" +#include "eth/mvEth.h" + +#define MACFMT "%02X:%02X:%02X:%02X:%02X:%02X" +#define MACSTR(m) m[0],m[1],m[2],m[3],m[4],m[5] + +MV_FP_PPP_RULE pppOpen[ETH_FP_IFINDEX_MAX]; /* connected pppoe sessions */ +MV_FP_PPP_RULE pppHalf[ETH_FP_IFINDEX_MAX]; /* half-open pppoe connections */ + + +MV_STATUS mvFpPppInit(void) +{ + memset(pppOpen, 0, sizeof(MV_FP_PPP_RULE) * ETH_FP_IFINDEX_MAX); + memset(pppHalf, 0, sizeof(MV_FP_PPP_RULE) * ETH_FP_IFINDEX_MAX); + + mvOsPrintf("NFP (pppoe) init %d entries, %d bytes\n", ETH_FP_IFINDEX_MAX, + 2 * sizeof(MV_FP_PPP_RULE) * ETH_FP_IFINDEX_MAX); + return MV_OK; +} + +MV_STATUS mvFpPppClear(void) +{ + memset(pppOpen, 0, sizeof(MV_FP_PPP_RULE) * ETH_FP_IFINDEX_MAX); + return MV_OK; +} + +void mvFpPppDestroy(void) +{ + mvFpPppClear(); +} + +void mvFpPppRulePrint(char* text, MV_FP_PPP_RULE *rule) +{ + mvOsPrintf("NFP (pppoe): ppp %s (%s) if_ppp=%u if_eth=%u session=%u DA=" MACFMT " SA=" MACFMT " %x\n", + text, rule->pppInfo.if_ppp ? "open":"half", + rule->pppInfo.if_ppp, + rule->pppInfo.if_eth, + rule->pppInfo.u.ppp.session, + MACSTR(rule->pppInfo.u.ppp.da), + MACSTR(rule->pppInfo.u.ppp.sa), + rule->pppInfo.channel); +} + +MV_STATUS mvFpPppRuleSet(MV_FP_PPP_RULE *rule) +{ + int if_ppp = rule->pppInfo.if_ppp; + int i = ETH_FP_IFINDEX_MAX; + +#ifdef MV_FP_DEBUG + mvFpPppRulePrint("new", rule); +#endif + + /* half open */ + if (!if_ppp) { + memcpy(&pppHalf[rule->pppInfo.if_eth], rule, sizeof(MV_FP_PPP_RULE)); + } + else while(i--) { + /* look for channel id match */ + if (pppHalf[i].pppInfo.channel == rule->pppInfo.channel) { + memcpy(&pppOpen[if_ppp], &pppHalf[i], sizeof(MV_FP_PPP_RULE)); + memset(&pppHalf[i], 0, sizeof(MV_FP_PPP_RULE)); + pppOpen[if_ppp].pppInfo.if_ppp = if_ppp; + break; + } + } + + return MV_OK; +} + +MV_STATUS mvFpPppRuleDel(MV_FP_PPP_RULE *rule) +{ + int i = ETH_FP_IFINDEX_MAX; + +#ifdef MV_FP_DEBUG + mvOsPrintf("NFP (pppoe): del ppp channel %x\n", rule->pppInfo.channel); +#endif + + while(i--) { + if (pppOpen[i].pppInfo.channel == rule->pppInfo.channel) { + mvFpPppRulePrint("del", &pppOpen[i]); + pppOpen[i].pppInfo.if_ppp = 0; + memset(&pppOpen[i], 0, sizeof(MV_FP_PPP_RULE)); + break; + } + } + + return MV_OK; +} + +MV_U32 mvFpPppRuleAge(MV_FP_PPP_RULE *rule) +{ + return MV_OK; +} + +MV_STATUS mvFpPppPrint(void) +{ + int i = ETH_FP_IFINDEX_MAX; + + while(i--) { + if (pppOpen[i].pppInfo.if_eth) + mvFpPppRulePrint("", &pppOpen[i]); + + if (pppHalf[i].pppInfo.if_eth) + mvFpPppRulePrint("", &pppHalf[i]); + + } + + return MV_OK; +} + +MV_U32 mvFpPppPhyIf(MV_U32 ifIndex) +{ + if (pppOpen[ifIndex].pppInfo.if_ppp) + return pppOpen[ifIndex].pppInfo.if_eth; + return ETH_FP_IFINDEX_MAX; +} + +/* IP header csum calculation */ +static inline unsigned short from32to16(unsigned long x) +{ + /* add up 16-bit and 16-bit for 16+c bit */ + x = (x & 0xffff) + (x >> 16); + /* add up carry.. */ + x = (x & 0xffff) + (x >> 16); + return x; +} + +static unsigned long do_csum(char* buff, int len) +{ + int odd, count; + unsigned long result = 0; + + if (len <= 0) + goto out; + odd = 1 & (unsigned long) buff; + if (odd) { + result = *buff; + len--; + buff++; + } + count = len >> 1; /* nr of 16-bit words.. */ + if (count) { + if (2 & (unsigned long) buff) { + result += *(unsigned short *) buff; + count--; + len -= 2; + buff += 2; + } + count >>= 1; /* nr of 32-bit words.. */ + if (count) { + unsigned long carry = 0; + do { + unsigned long w = *(unsigned long *) buff; + count--; + buff += 4; + result += carry; + result += w; + carry = (w > result); + } while (count); + result += carry; + result = (result & 0xffff) + (result >> 16); + } + if (len & 2) { + result += *(unsigned short *) buff; + buff += 2; + } + } + if (len & 1) + result += (*buff << 8); + result = from32to16(result); + if (odd) + result = ((result >> 8) & 0xff) | ((result & 0xff) << 8); +out: + return result; +} + +static INLINE void mvFpCSumIP(MV_IP_HEADER* pIpHdr) +{ + pIpHdr->checksum = 0; + pIpHdr->checksum = ~do_csum((char*)pIpHdr, 20 /*iph->ihl*/); +} + +static INLINE MV_U32 mvFpPppLookup(MV_U32 ifIndex) +{ + return pppOpen[ifIndex].pppInfo.if_ppp; +} + +/* NFP bottom half */ +int mvFpPPPoE(MV_U32 ifIndex, MV_PKT_INFO* pPkt, MV_FP_STATS* pFpStats) +{ + MV_U8* pEth = pPkt->pFrags->bufVirtPtr; + MV_BUF_INFO* pBuf = pPkt->pFrags; + + MV_NFP_STAT(pFpStats->ppp_tx_esp++); + + /* Encapsulate PPPoE on Tx */ + if (!mvFpPppLookup(ifIndex)) + { + MV_NFP_STAT(pFpStats->ppp_err++); + return MV_FAIL; + } + + if (pBuf->dataSize > ETH_FP_PPPOE_MTU) + { + /* Bad, we check size in the mvNfpSecOutgoing() --BK */ + mvOsPrintf("PPPoE oversize %d > %d\n", pBuf->dataSize, ETH_FP_PPPOE_MTU); + MV_NFP_STAT(pFpStats->ppp_err++); + return MV_FAIL; + } + + pBuf->bufAddrShift += ETH_FP_PPPOE_HDR; + pBuf->bufPhysAddr -= ETH_FP_PPPOE_HDR; + pBuf->bufVirtPtr -= ETH_FP_PPPOE_HDR; + pBuf->dataSize += ETH_FP_PPPOE_HDR; + pEth -= ETH_FP_PPPOE_HDR; + + /* -6B aligment from 32B boundary */ + { + MV_U32* d = (MV_U32*)pEth; + MV_U32* s = pppOpen[ifIndex].pppInfo.u.u32; + + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + *(d++) = *(s++); + } + + /* update payload len */ + *(MV_U16*)(pEth+20) = htons(pBuf->dataSize - 14 - ETH_FP_PPPOE_HDR); + + /* recalculate IP csum in sw */ + mvFpCSumIP((MV_IP_HEADER*)(pEth+24)); + pPkt->status = 0; + + /* flush two cachelines */ + mvOsCacheLineFlushInv(NULL, pEth); + mvOsCacheLineFlushInv(NULL, pEth+32); + + return MV_OK; +} + diff --git a/board/mv_feroceon/mv_hal/eth/nfp/mvNfpSec.c b/board/mv_feroceon/mv_hal/eth/nfp/mvNfpSec.c new file mode 100644 index 0000000..9aa0da2 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/nfp/mvNfpSec.c @@ -0,0 +1,599 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfpSec.c - Marvell Network Fast Processing with IPSec(Routing only) +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mvDebug.h" +#include "eth/nfp/mvNfp.h" +#include "eth/mvEth.h" +#include "eth/nfp/mvNfpSec.h" +#include "cesa/mvCesa.h" + +/* IPSec SA & SPD DBs */ +MV_NFP_SEC_SPD_RULE* spdInDb; +MV_NFP_SEC_SPD_RULE* spdOutDb; +MV_NFP_SEC_SA_ENTRY* saInDb; +MV_NFP_SEC_SA_ENTRY* saOutDb; + +static MV_CESA_MBUF cesaMbufArray[MV_NFP_SEC_Q_SIZE]; +static MV_CESA_COMMAND cesaCmdArray[MV_NFP_SEC_Q_SIZE]; +static MV_NFP_SEC_CESA_PRIV cesaPrivArray[MV_NFP_SEC_Q_SIZE + MV_NFP_SEC_REQ_Q_SIZE]; +static int cesaCmdIndx = 0; +static int cesaPrivIndx = 0; + +static MV_U32 spdInRuleCount; +static MV_U32 spdOutRuleCount; +static MV_U32 saInEntryCount; +static MV_U32 saOutEntryCount; +static MV_U32 secDbSize; + +extern int cesaReqResources; + +MV_STATUS mvNfpSecInit(MV_U32 dbSize) +{ + if(dbSize == 0) + return MV_BAD_PARAM; + + spdInDb = (struct _mv_nfp_sec_spd_rule*)mvOsMalloc(dbSize * (sizeof(struct _mv_nfp_sec_spd_rule))); + spdOutDb = (struct _mv_nfp_sec_spd_rule*)mvOsMalloc(dbSize * (sizeof(struct _mv_nfp_sec_spd_rule))); + saInDb = (struct _mv_nfp_sec_sa_entry*)mvOsMalloc(dbSize * (sizeof(struct _mv_nfp_sec_sa_entry))); + saOutDb = (struct _mv_nfp_sec_sa_entry*)mvOsMalloc(dbSize * (sizeof(struct _mv_nfp_sec_sa_entry))); + + if((spdInDb == NULL) || (spdOutDb== NULL) || (saInDb == NULL) || (saOutDb == NULL)) { + mvOsPrintf("NFP-IPSec Rules DB: Not Enough Memory\n"); + return MV_NO_RESOURCE; + } + + secDbSize = dbSize; + spdInRuleCount = spdOutRuleCount = saInEntryCount = saOutEntryCount = 0; + + memset(spdInDb, 0, (dbSize * sizeof(struct _mv_nfp_sec_spd_rule))); + memset(spdOutDb, 0, (dbSize * sizeof(struct _mv_nfp_sec_spd_rule))); + memset(saInDb, 0, (dbSize * sizeof(struct _mv_nfp_sec_sa_entry))); + memset(saOutDb, 0, (dbSize * sizeof(struct _mv_nfp_sec_sa_entry))); + + return MV_OK; + +} + +MV_STATUS mvNfpSecDbClear(MV_VOID) +{ + MV_U32 i; + MV_NFP_SEC_SPD_RULE *pCurrSpdInRule, *pCurrSpdOutRule; + MV_NFP_SEC_SA_ENTRY *pCurrSAInEntery, *pCurrSAOutEntery; + + if((spdInDb == NULL) && (spdOutDb == NULL) && (saInDb == NULL) && (saOutDb == NULL)) + return MV_NOT_INITIALIZED; + + /* assume all 4 DBs are initialized */ + for(i = 0; i < secDbSize; i++) { + pCurrSpdInRule = (spdInDb + i); + pCurrSpdOutRule = (spdOutDb + i); + pCurrSAInEntery = (saInDb + i); + pCurrSAOutEntery = (saOutDb + i); + mvOsFree(pCurrSpdInRule); + mvOsFree(pCurrSpdOutRule); + mvOsFree(pCurrSAInEntery); + mvOsFree(pCurrSAOutEntery); + } + + spdInDb = spdOutDb = NULL; + saInDb = saOutDb = NULL; + + return MV_OK; +} + + +static INLINE MV_VOID mvNfpSecClearRange(MV_U8* addr, MV_U32 size) +{ + MV_U32 i; + MV_U8 *align; + + align = (MV_U8*)((MV_U32)addr & ~0x1f); + + for(i = 0; align <= (addr+size); align += CPU_D_CACHE_LINE_SIZE) + mvOsCacheLineFlushInv(NULL, align); +} + +static INLINE MV_VOID mvNfpSecInvRange(MV_U8* addr, MV_U32 size) +{ + MV_U32 i; + MV_U8 *align; + + align = (MV_U8*)((MV_U32)addr & ~0x1f); + + for(i = 0; align <= (addr+size); align += CPU_D_CACHE_LINE_SIZE) + mvOsCacheLineInv(NULL, align); +} + + +/****************************************************/ +/* warning: need to replace DB list with hash table */ +/****************************************************/ +MV_NFP_SEC_SPD_RULE* mvNfpSecSPDRuleSet(MV_NFP_SEC_SPD_RULE* pSpdRule, MV_NFP_SEC_RULE_DB_DIR inOut) +{ + MV_NFP_SEC_SPD_RULE* pCurrSpdRule; + MV_U32 currRuleIndex = 0, spdRuleCount; + + pCurrSpdRule = (inOut ? spdOutDb : spdInDb); + spdRuleCount = (inOut ? spdOutRuleCount : spdInRuleCount); + + if(spdRuleCount >= secDbSize) + return NULL; + + /* search if rule already exists */ + while(currRuleIndex < spdRuleCount) { + if((pCurrSpdRule->sIp == pSpdRule->sIp) && + (pCurrSpdRule->dIp == pSpdRule->dIp) +#ifdef MV_NFP_SEC_5TUPLE_KEY_SUPPORT + && (pCurrSpdRule->proto == pSpdRule->proto) && + (pCurrSpdRule->srcPort == pSpdRule->srcPort) && + (pCurrSpdRule->dstPort == pSpdRule->dstPort) +#endif + ) { + /* rule exists - return */ + return pCurrSpdRule; + } + currRuleIndex++; + pCurrSpdRule++; + } + + pCurrSpdRule = (inOut ? (spdOutDb+spdRuleCount) : (spdInDb+spdRuleCount));; + memcpy(pCurrSpdRule, pSpdRule, sizeof(struct _mv_nfp_sec_spd_rule)); + inOut ? spdOutRuleCount++ : spdInRuleCount++ ; + + return pCurrSpdRule; + +} + +MV_NFP_SEC_SA_ENTRY* mvNfpSecSAEntrySet(MV_NFP_SEC_SA_ENTRY* pSAEntry, MV_NFP_SEC_RULE_DB_DIR inOut) +{ + + MV_NFP_SEC_SA_ENTRY* pCurrSAEntery; + MV_U32 currEntryIndex = 0, saEntryCount; + + pCurrSAEntery = (inOut ? saOutDb : saInDb); + saEntryCount = (inOut ? saOutEntryCount : saInEntryCount); + + if(saEntryCount >= secDbSize) + return NULL; + + /* search if rule already exists */ + while(currEntryIndex < saEntryCount) { + if(pCurrSAEntery->spi == pSAEntry->spi) { + /* rule exists - return */ + return pCurrSAEntery; + } + currEntryIndex++; + pCurrSAEntery++; + } + + + pCurrSAEntery = (inOut ? (saOutDb+saEntryCount) : (saInDb+saEntryCount)); + memcpy(pCurrSAEntery, pSAEntry, sizeof(struct _mv_nfp_sec_sa_entry)); + inOut ? saOutEntryCount++ : saInEntryCount++ ; + + return pCurrSAEntery; + + +} + +MV_STATUS mvNfpSecOutCheck(MV_PKT_INFO *pPktInfo) +{ + if(pPktInfo->pFrags->dataSize > MV_NFP_SEC_MAX_PACKET) + return MV_OUT_OF_RANGE; + return MV_OK; +} + +INLINE MV_STATUS mvNfpSecInCheck(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY* pSAEntry) +{ + /* TBD - sequence number */ + return MV_OK; +} + +MV_NFP_SEC_SPD_RULE* mvNfpSecSPDRuleFind(MV_U32 dstIp, MV_U32 srcIp, + MV_U8 proto, MV_U16 dport, MV_U16 sport, MV_NFP_SEC_RULE_DB_DIR inOut) +{ + MV_NFP_SEC_SPD_RULE* pCurrSpdRule; + MV_U32 currRuleIndex = 0, spdRuleCount; + + pCurrSpdRule = (inOut ? spdOutDb : spdInDb); + spdRuleCount = (inOut ? spdOutRuleCount : spdInRuleCount); + + /* SPD DB is empty */ + if(!spdRuleCount) + return NULL; + + /* scan IN/OUT SPD database for matching rule */ + while(currRuleIndex < spdRuleCount) { + if((pCurrSpdRule->sIp == srcIp) && + (pCurrSpdRule->dIp == dstIp) +#ifdef MV_NFP_SEC_5TUPLE_KEY_SUPPORT + && (pCurrSpdRule->proto == proto) + (pCurrSpdRule->srcPort == sport) && + (pCurrSpdRule->dstPort == dport) +#endif + ) { + /* rule found - return */ + return pCurrSpdRule; + } + currRuleIndex++; + pCurrSpdRule++; + } + + + return NULL; + +} + +INLINE MV_VOID mvNfpSecBuildMac(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY* pSAEntry) +{ + MV_802_3_HEADER *pMacHdr; + + pMacHdr = (MV_802_3_HEADER*)((MV_U8 *)(pPktInfo->pFrags[0].bufVirtPtr)); + memcpy(pMacHdr, &pSAEntry->tunnelHdr.dstMac, 12); + pMacHdr->typeOrLen = 0x08; /* stands for IP protocol code 16bit swapped */ + return; +} + +INLINE MV_VOID mvNfpSecBuildIPTunnel(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY* pSAEntry) +{ + MV_IP_HEADER *pIpHdr, *pIntIpHdr; + MV_U16 newIpTotalLength; + + newIpTotalLength = pPktInfo->pFrags[0].dataSize - sizeof(MV_802_3_HEADER); + + pIpHdr = (MV_IP_HEADER*)(pPktInfo->pFrags[0].bufVirtPtr + + sizeof(MV_802_3_HEADER)); + pIntIpHdr = (MV_IP_HEADER*)((MV_U8*)(pIpHdr) + sizeof(MV_IP_HEADER) + sizeof(MV_ESP_HEADER) + + pSAEntry->ivSize); + + /* TBD - review below settings in RFC */ + pIpHdr->version = 0x45; + pIpHdr->tos = 0; + pIpHdr->checksum = 0; + pIpHdr->totalLength = MV_16BIT_BE(newIpTotalLength); + pIpHdr->identifier = 0; + pIpHdr->fragmentCtrl = 0; + pIpHdr->ttl = pIntIpHdr->ttl -1 ; + pIpHdr->protocol = MV_IP_PROTO_ESP; + pIpHdr->srcIP = pSAEntry->tunnelHdr.sIp; + pIpHdr->dstIP = pSAEntry->tunnelHdr.dIp; + + pPktInfo->status = ETH_TX_IP_NO_FRAG | ETH_TX_GENERATE_IP_CHKSUM_MASK | + (0x5 << ETH_TX_IP_HEADER_LEN_OFFSET); + + return; +} + +/* Append sequence number and spi, save some space for IV */ +INLINE MV_VOID mvNfpSecBuildEspHdr(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY* pSAEntry) +{ + MV_ESP_HEADER *pEspHdr; + + pEspHdr = (MV_ESP_HEADER*)(pPktInfo->pFrags[0].bufVirtPtr + + sizeof(MV_802_3_HEADER) + sizeof(MV_IP_HEADER)); + pEspHdr->spi = pSAEntry->spi; + pSAEntry->seqNum = (pSAEntry->seqNum++); + pEspHdr->seqNum = MV_32BIT_BE(pSAEntry->seqNum); +} + +MV_STATUS mvNfpSecEspProcess(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY* pSAEntry) +{ + MV_CESA_COMMAND *pCesaCmd; + MV_CESA_MBUF *pCesaMbuf; + MV_NFP_SEC_CESA_PRIV *pCesaPriv; + MV_STATUS status; + MV_IP_HEADER *pIpHdr; + MV_BUF_INFO *pBuf; + + pCesaCmd = &cesaCmdArray[cesaCmdIndx]; + pCesaMbuf = &cesaMbufArray[cesaCmdIndx]; + cesaCmdIndx++; + cesaCmdIndx %= MV_NFP_SEC_Q_SIZE; + pCesaPriv = &cesaPrivArray[cesaPrivIndx++]; + cesaPrivIndx = cesaPrivIndx%(MV_NFP_SEC_Q_SIZE + MV_NFP_SEC_REQ_Q_SIZE); + + pCesaPriv->pPktInfo = pPktInfo; + pCesaPriv->pSaEntry = pSAEntry; + pCesaPriv->pCesaCmd = pCesaCmd; + + /* + * Fix, encrypt/decrypt the IP payload only, --BK 20091027 + */ + pBuf = pPktInfo->pFrags; + pIpHdr = (MV_IP_HEADER*)(pBuf->bufVirtPtr + sizeof(MV_802_3_HEADER)); + pBuf->dataSize = MV_16BIT_BE(pIpHdr->totalLength) + sizeof(MV_802_3_HEADER); + + pBuf->bufVirtPtr += MV_NFP_SEC_ESP_OFFSET; + pBuf->bufPhysAddr += MV_NFP_SEC_ESP_OFFSET; + pBuf->dataSize -= MV_NFP_SEC_ESP_OFFSET; + pBuf->bufAddrShift -= MV_NFP_SEC_ESP_OFFSET; + + pCesaMbuf->pFrags = pPktInfo->pFrags; + pCesaMbuf->numFrags = 1; + pCesaMbuf->mbufSize = pBuf->dataSize; + + pCesaCmd->pReqPrv = (MV_VOID*)pCesaPriv; + pCesaCmd->sessionId = pSAEntry->sid; + pCesaCmd->pSrc = pCesaMbuf; + pCesaCmd->pDst = pCesaMbuf; + pCesaCmd->skipFlush = MV_TRUE; + + /* Assume ESP */ + pCesaCmd->cryptoOffset = sizeof(MV_ESP_HEADER) + pSAEntry->ivSize; + pCesaCmd->cryptoLength = pBuf->dataSize - (sizeof(MV_ESP_HEADER) + + pSAEntry->ivSize + pSAEntry->digestSize); + pCesaCmd->ivFromUser = 0; /* relevant for encode only */ + pCesaCmd->ivOffset = sizeof(MV_ESP_HEADER); + pCesaCmd->macOffset = 0; + pCesaCmd->macLength = pBuf->dataSize - pSAEntry->digestSize; + pCesaCmd->digestOffset = pBuf->dataSize - pSAEntry->digestSize ; + + /* save original digest in case of decrypt+auth */ + if(pSAEntry->secOp == MV_NFP_SEC_DECRYPT) { + memcpy(pCesaPriv->orgDigest,(pBuf->bufVirtPtr + pCesaCmd->digestOffset), + pSAEntry->digestSize); + mvNfpSecInvRange((pBuf->bufVirtPtr + pCesaCmd->digestOffset), + pSAEntry->digestSize); + } + + pSAEntry->stats.bytes += pBuf->dataSize; + if (pSAEntry->secOp == MV_NFP_SEC_DECRYPT) + pSAEntry->stats.decrypt++; + else + pSAEntry->stats.encrypt++; + + disable_irq(CESA_IRQ); + status = mvCesaAction(pCesaCmd); + enable_irq(CESA_IRQ); + if(status != MV_OK) { + pSAEntry->stats.rejected++; + mvOsPrintf("%s: mvCesaAction failed %d\n", __FUNCTION__, status); + } + + return status; +} + +MV_STATUS mvNfpSecOutgoing(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY* pSAEntry) +{ + MV_U8* pTmp; + MV_U32 cryptoSize, encBlockMod, dSize; + MV_BUF_INFO* pBuf = pPktInfo->pFrags; + + /* CESA Q is full drop. */ + if (cesaReqResources <= 1) + { + pSAEntry->stats.rejected++; + return MV_NO_RESOURCE; + } + + /* encrypt payload */ + cryptoSize = pBuf->dataSize - sizeof(MV_802_3_HEADER) - ETH_MV_HEADER_SIZE; + + /* ignore Marvell header */ + pBuf->dataSize -= ETH_MV_HEADER_SIZE; + pBuf->bufVirtPtr += ETH_MV_HEADER_SIZE; + pBuf->bufPhysAddr += ETH_MV_HEADER_SIZE; + pBuf->bufAddrShift -= ETH_MV_HEADER_SIZE; + + /* Align buffer address to beginning of new packet - TBD handle VLAN tag, LLC */ + dSize = pSAEntry->ivSize + sizeof(MV_ESP_HEADER) + sizeof(MV_IP_HEADER); + pBuf->bufVirtPtr -= dSize; + pBuf->bufPhysAddr -= dSize; + pBuf->dataSize += dSize; + pBuf->bufAddrShift += dSize; + + encBlockMod = (cryptoSize % MV_NFP_SEC_ENC_BLOCK_SIZE); + /* leave space for padLen + Protocol */ + if(encBlockMod > 14 ) { + encBlockMod = MV_NFP_SEC_ENC_BLOCK_SIZE - encBlockMod; + encBlockMod += MV_NFP_SEC_ENC_BLOCK_SIZE; + } + else + encBlockMod = MV_NFP_SEC_ENC_BLOCK_SIZE - encBlockMod; + + /* expected frame size */ + dSize = pBuf->dataSize + encBlockMod + pSAEntry->digestSize; + +#ifdef CONFIG_MV_ETH_NFP_PPP + /* keep enough room for PPPoE header */ + if (ETH_FP_IFINDEX_MAX != mvFpPppPhyIf(pSAEntry->tunnelHdr.outIfIndex)) + dSize += ETH_FP_PPPOE_HDR; +#endif + + if (dSize > ETH_FP_MTU - ETH_MV_HEADER_SIZE) + goto rollback; + + pBuf->dataSize += encBlockMod; + pTmp = pBuf->bufVirtPtr + pBuf->dataSize; + memset(pTmp - encBlockMod, 0, encBlockMod - 2); + *((MV_U8*)(pTmp-2)) = (MV_U8)(encBlockMod-2); + *((MV_U8*)(pTmp-1)) = (MV_U8)4; + mvNfpSecClearRange(pTmp - encBlockMod, encBlockMod); + + pBuf->dataSize += pSAEntry->digestSize; + mvNfpSecBuildEspHdr(pPktInfo, pSAEntry); + mvNfpSecBuildIPTunnel(pPktInfo, pSAEntry); + mvNfpSecBuildMac(pPktInfo, pSAEntry); + + /* flush & invalidate new MAC, IP, & ESP headers + old ip*/ + dSize = pBuf->bufAddrShift + sizeof(MV_IP_HEADER) + sizeof(MV_802_3_HEADER); + mvNfpSecClearRange(pBuf->bufVirtPtr, dSize); + + return mvNfpSecEspProcess(pPktInfo, pSAEntry); + +rollback: + /* slow path */ + pBuf->bufPhysAddr += pBuf->bufAddrShift; + pBuf->bufVirtPtr += pBuf->bufAddrShift; + pBuf->dataSize -= pBuf->bufAddrShift; + pBuf->bufAddrShift = 0; + + pSAEntry->stats.rejected++; + return MV_OUT_OF_RANGE; +} + +MV_STATUS mvNfpSecIncoming(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY* pSAEntry) +{ + + MV_BUF_INFO* pBuf = pPktInfo->pFrags; + MV_U32 invSize; + + /* CESA Q is full drop. */ + if(cesaReqResources <= 1) + { + pSAEntry->stats.rejected++; + return MV_NO_RESOURCE; + } + + /* TBD - duplicate invalidatation */ + if(MV_OK != mvNfpSecInCheck(pPktInfo, pSAEntry)) + { + pSAEntry->stats.rejected++; + return MV_ERROR; + } + + /* ignore Marvell header */ + pBuf->dataSize -= ETH_MV_HEADER_SIZE; + pBuf->bufVirtPtr += ETH_MV_HEADER_SIZE; + pBuf->bufPhysAddr += ETH_MV_HEADER_SIZE; + pBuf->bufAddrShift -= ETH_MV_HEADER_SIZE; + + /* update buffer address shift value */ + /* tracked by bufAddrShift, --BK 091022 */ + /* pBuf->bufAddrShift -= (pSAEntry->ivSize + sizeof(MV_ESP_HEADER) + sizeof(MV_IP_HEADER));*/ + + /* invalidate MAC, IP & ESP headers */ + invSize = sizeof(MV_802_3_HEADER) + sizeof(MV_IP_HEADER) + sizeof(MV_ESP_HEADER); + mvNfpSecInvRange(pBuf->bufVirtPtr, invSize); + + return mvNfpSecEspProcess(pPktInfo, pSAEntry); +} + +MV_NFP_SEC_SA_ENTRY* mvNfpSecSARuleFind(MV_U32 spiPkt) +{ + MV_NFP_SEC_SA_ENTRY* pCurrSAEntery = saInDb; + MV_U32 currEntryIndex = 0; + + while(currEntryIndex < saInEntryCount) { + if(pCurrSAEntery->spi == spiPkt) + return pCurrSAEntery; + currEntryIndex++; + pCurrSAEntery++; + } + + return NULL; + +} +MV_VOID mvNfpSecSaPrint(MV_NFP_SEC_SA_ENTRY *pSAEntry) +{ + mvDebugPrintIpAddr(MV_32BIT_BE(pSAEntry->tunnelHdr.sIp)); + mvOsPrintf("->"); + mvDebugPrintIpAddr(MV_32BIT_BE(pSAEntry->tunnelHdr.dIp)); + mvOsPrintf(" out_if=%d da=", pSAEntry->tunnelHdr.outIfIndex); + mvDebugPrintMacAddr(pSAEntry->tunnelHdr.dstMac); + mvOsPrintf(" spi=0x%x", MV_32BIT_BE(pSAEntry->spi)); + + if (pSAEntry) + mvOsPrintf("\tstats: encrypt:%d decrypt:%d reject:%d drop:%d bytes:%d", + pSAEntry->stats.encrypt, pSAEntry->stats.decrypt, + pSAEntry->stats.rejected, pSAEntry->stats.dropped, + pSAEntry->stats.bytes); + mvOsPrintf("\n"); +} + +MV_VOID mvNfpSecDbPrint(MV_VOID) +{ + MV_U32 i; + + mvOsPrintf("NFP IPSec:\n"); + + for(i = 0; i < spdInRuleCount; i++) { + mvOsPrintf("inbound[%d] ", i); + mvDebugPrintIpAddr(MV_32BIT_BE(spdInDb[i].sIp)); + mvOsPrintf("->"); + mvDebugPrintIpAddr(MV_32BIT_BE(spdInDb[i].dIp)); + mvOsPrintf(" "); + mvNfpSecSaPrint(spdInDb[i].pSAEntry); + } + for(i = 0; i < spdOutRuleCount; i++) { + mvOsPrintf("outbound[%d] ", i); + mvDebugPrintIpAddr(MV_32BIT_BE(spdOutDb[i].sIp)); + mvOsPrintf("->"); + mvDebugPrintIpAddr(MV_32BIT_BE(spdOutDb[i].dIp)); + mvOsPrintf(" "); + mvNfpSecSaPrint(spdOutDb[i].pSAEntry); + } +} diff --git a/board/mv_feroceon/mv_hal/eth/nfp/mvNfpSec.h b/board/mv_feroceon/mv_hal/eth/nfp/mvNfpSec.h new file mode 100644 index 0000000..273c235 --- /dev/null +++ b/board/mv_feroceon/mv_hal/eth/nfp/mvNfpSec.h @@ -0,0 +1,193 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvNfpSec.h - Header File for Marvell NFP IPSec (Routing only) +* +* DESCRIPTION: +* This header file contains macros, typedefs and function declarations +* specific to the Marvell Network Fast Processing with IPSec(Routing only). +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvNfpSec_h__ +#define __mvNfpSec_h__ + +#ifdef CONFIG_MV_ETH_NFP_SEC + +#include "mvCommon.h" +#include "cesa/mvCesa.h" + +/* IPSec defines */ +#define MV_NFP_SEC_MAX_PACKET 1540 +#define MV_NFP_SEC_ENC_BLOCK_SIZE 16 + +#define MV_NFP_SEC_ESP_OFFSET 34 + +/* IPSec Enumerators */ +typedef enum { + MV_NFP_SEC_TUNNEL = 0, + MV_NFP_SEC_TRANSPORT, +} MV_NFP_SEC_PROT; + +typedef enum { + MV_NFP_SEC_ESP = 0, + MV_NFP_SEC_AH, +} MV_NFP_SEC_ENCAP; + +typedef enum { + MV_NFP_SEC_RULE_DB_IN = 0, + MV_NFP_SEC_RULE_DB_OUT, +} MV_NFP_SEC_RULE_DB_DIR; + +typedef enum { + MV_NFP_SEC_DROP = 0, + MV_NFP_SEC_FWD, + MV_NFP_SEC_SECURE +} MV_NFP_SEC_ACTION; + +typedef enum { + MV_NFP_SEC_ENCRYPT = 0, + MV_NFP_SEC_DECRYPT, +} MV_NFP_SEC_OP; + +typedef struct _mv_nfp_sa_stats { + MV_U32 encrypt; + MV_U32 decrypt; + MV_U32 rejected; /* slow path */ + MV_U32 dropped; /* packet drop */ + MV_U32 bytes; +} MV_NFP_SA_STATS; + +/* IPSec Structures */ +typedef struct _mv_nfp_sec_tunnel_hdr { + MV_U32 sIp; // BE + MV_U32 dIp; //BE + /* dstMac should be 2 byte aligned */ + MV_U8 dstMac[MV_MAC_ADDR_SIZE]; //BE + MV_U8 srcMac[MV_MAC_ADDR_SIZE]; //BE + MV_U8 outIfIndex; +} MV_NFP_SEC_TUNNEL_HDR; + +typedef struct _mv_nfp_sec_sa_entry { + MV_U32 spi; //BE + MV_NFP_SEC_PROT tunProt; + MV_NFP_SEC_ENCAP encap; + MV_U16 sid; + MV_U32 seqNum; //LE + MV_NFP_SEC_TUNNEL_HDR tunnelHdr; + MV_U32 lifeTime; + MV_U8 ivSize; + MV_U8 cipherBlockSize; + MV_U8 digestSize; + MV_NFP_SEC_OP secOp; + MV_NFP_SA_STATS stats; +} MV_NFP_SEC_SA_ENTRY; + +typedef struct _mv_nfp_sec_spd_rule { + MV_U32 sIp; //BE + MV_U32 dIp; //BE + MV_U8 proto; + MV_U16 dstPort; //BE + MV_U16 srcPort; //BE + MV_NFP_SEC_ACTION actionType; + MV_NFP_SEC_SA_ENTRY* pSAEntry; +} MV_NFP_SEC_SPD_RULE; + +typedef struct _mv_nfp_sec_cesa_priv { + MV_NFP_SEC_SA_ENTRY *pSaEntry; + MV_PKT_INFO *pPktInfo; + MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; + MV_CESA_COMMAND *pCesaCmd; +} MV_NFP_SEC_CESA_PRIV; + + +MV_NFP_SEC_SPD_RULE* mvNfpSecSPDRuleFind(MV_U32 dstIp, MV_U32 srcIp, + MV_U8 proto, MV_U16 dport, MV_U16 sport, MV_NFP_SEC_RULE_DB_DIR inOut); + +MV_STATUS mvNfpSecOutCheck(MV_PKT_INFO *pPktInfo); + +MV_STATUS mvNfpSecOutgoing(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY* pSAEntry); + +MV_STATUS mvNfpSecEspProcess(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY* pSAEntry); + +MV_NFP_SEC_SA_ENTRY* mvNfpSecSARuleFind(MV_U32 spiPkt); + +MV_STATUS mvNfpSecIncoming(MV_PKT_INFO *pPktInfo, MV_NFP_SEC_SA_ENTRY* pSAEntry); + +MV_NFP_SEC_SPD_RULE* mvNfpSecSPDRuleSet(MV_NFP_SEC_SPD_RULE* pSpdRule, MV_NFP_SEC_RULE_DB_DIR inOut); + +MV_NFP_SEC_SA_ENTRY* mvNfpSecSAEntrySet(MV_NFP_SEC_SA_ENTRY* pSAEntry, MV_NFP_SEC_RULE_DB_DIR inOut); + +MV_STATUS mvNfpSecInit(MV_U32 dbSize); // global init + +MV_VOID mvNfpSecDbPrint(MV_VOID); + +#endif /* CONFIG_MV_ETH_NFP_SEC */ + +#endif /* __mvNfpSec_h__ */ + diff --git a/board/mv_feroceon/mv_hal/ethfp/fast_path/mvFastPath.c b/board/mv_feroceon/mv_hal/ethfp/fast_path/mvFastPath.c new file mode 100644 index 0000000..0c3129b --- /dev/null +++ b/board/mv_feroceon/mv_hal/ethfp/fast_path/mvFastPath.c @@ -0,0 +1,655 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvFastPath.c - Marvell Network Fast Processing (Routing and NAT) +* +* DESCRIPTION: +* +* Supported Features: +* - OS independent. +* +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mvDebug.h" +#include "ethfp/fast_path/mvFastPath.h" +#include "ethfp/mvEth.h" + +MV_U32 ip_hash_depth[ETH_FP_MAX_HASH_DEPTH+1]; +MV_U32 nat_hash_depth[ETH_FP_MAX_HASH_DEPTH+1]; + + +static struct ruleHashBucket *ruleDb; +static MV_U32 ruleDbSize; + +static MV_U32 nfpRuleSetCount; +static MV_U32 nfpRuleUpdateCount; +static MV_U32 nfpRuleDeleteCount; + +MV_U32 fp_ip_jhash_iv = 0; + + +MV_STATUS mvFpInit(void) +{ + memset(nat_hash_depth, 0, (ETH_FP_MAX_HASH_DEPTH+1)*sizeof(MV_U32)); + memset(ip_hash_depth, 0, (ETH_FP_MAX_HASH_DEPTH+1)*sizeof(MV_U32)); + fp_ip_jhash_iv = mvOsRand(); + + return MV_OK; +} + + +/* Initialize NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbInit(MV_U32 dbSize) +{ + ruleDb = (struct ruleHashBucket *)mvOsMalloc(sizeof(struct ruleHashBucket)*dbSize); + if (ruleDb == NULL) { + mvOsPrintf("NFP Rule DB: Not Enough Memory\n"); + return MV_NO_RESOURCE; + } + ruleDbSize = dbSize; + memset(ruleDb, 0, sizeof(struct ruleHashBucket)*ruleDbSize); + nfpRuleSetCount = nfpRuleUpdateCount = nfpRuleDeleteCount = 0; + + mvOsPrintf("mvFpRuleDb (%p): %d entries, %d bytes\n", + ruleDb, ruleDbSize, sizeof(struct ruleHashBucket)*ruleDbSize); + + return MV_OK; +} + +/* Clear NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbClear(void) +{ + MV_U32 i = 0; + MV_FP_RULE *currRule; + MV_FP_RULE *tmpRule; + + if (ruleDb == NULL) + return MV_NOT_INITIALIZED; + + for (i = 0; i < ruleDbSize; i++) { + currRule = ruleDb[i].ruleChain; + while (currRule != NULL) { + tmpRule = currRule; + currRule = currRule->next; + mvOsFree(tmpRule); + } + ruleDb[i].ruleChain = NULL; + } + return MV_OK; +} + + +/* Free Rule Database memory */ +void mvFpRuleDbDestroy(void) +{ + if (ruleDb != NULL) + mvOsFree(ruleDb); +} + +/* Print rule action type. Assume rule is not NULL. */ +static void mvFpActionTypePrint(const MV_FP_RULE *rule) +{ + switch(rule->mgmtInfo.actionType) { + case MV_FP_ROUTE_CMD: + mvOsPrintf("A=Route, "); + break; + case MV_FP_DROP_CMD: + mvOsPrintf("A=Drop, "); + break; + case MV_FP_TO_STACK_CMD: + mvOsPrintf("A=Stack, "); + break; + default: + mvOsPrintf("A=Unknown (%d), ", rule->mgmtInfo.actionType); + break; + } +} + +/* Print rule type (static or dynamic). Assume rule is not NULL. */ +static void mvFpRuleTypePrint(const MV_FP_RULE *rule) +{ + switch(rule->mgmtInfo.ruleType) { + case MV_FP_STATIC_RULE: + mvOsPrintf("T=Static"); + break; + case MV_FP_DYNAMIC_RULE: + mvOsPrintf("T=Dynamic"); + break; + default: + mvOsPrintf("T=Unknown"); + break; + } +} + +/* Print a NFP Rule */ +void mvFpRulePrint(const MV_FP_RULE *rule) +{ + mvFpActionTypePrint(rule); + mvFpRuleTypePrint(rule); + mvOsPrintf(", SIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->routingInfo.srcIp)); + mvOsPrintf(", DIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->routingInfo.dstIp)); + mvOsPrintf(", GTW="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->routingInfo.defGtwIp)); + mvOsPrintf(", DA="); + mvDebugPrintMacAddr(rule->routingInfo.dstMac); + mvOsPrintf(", SA="); + mvDebugPrintMacAddr(rule->routingInfo.srcMac); + mvOsPrintf(", inIf=%d", rule->routingInfo.inIfIndex); + mvOsPrintf(", outIf=%d", rule->routingInfo.outIfIndex); + +#if defined(CONFIG_MV_GTW_HEADER_MODE) + mvOsPrintf(", mvHeader=0x%X", rule->routingInfo.pktHdr.mvHeader.header); +#elif defined (CONFIG_MV_GTW_DSA_TAG_MODE) + mvOsPrintf(", dsaTag=0x%X", rule->routingInfo.pktHdr.dsaTag); +#endif /* CONFIG_MV_GTW_HEADER_MODE || CONFIG_MV_GTW_EXT_DSA_TAG_MODE || CONFIG_MV_GTW_EXT_DSA_TAG_MODE */ + + mvOsPrintf(", count=%d, aware_flags=0x%X", rule->mgmtInfo.new_count, rule->routingInfo.aware_flags); + mvOsPrintf("\n"); +} + +/* Print NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbPrint(void) +{ + MV_U32 count, i; + MV_FP_RULE *currRule; + + mvOsPrintf("\nPrinting NFP Rule Database\n"); + count = 0; + + for(i=0; inext; + count++; + } + } + return MV_OK; +} + + +/* Copy all the information from src_rule to new_rule */ +/* Warning - doesn't perform any checks on memory, just copies */ +/* count is set to zero in new_rule */ +/* Note: the next pointer is not updated . */ +void mvFpRuleCopy(MV_FP_RULE *dstRule, const MV_FP_RULE *srcRule) +{ + dstRule->mgmtInfo.actionType = srcRule->mgmtInfo.actionType; + dstRule->mgmtInfo.new_count = srcRule->mgmtInfo.new_count; + dstRule->mgmtInfo.old_count = srcRule->mgmtInfo.old_count; + dstRule->mgmtInfo.ruleType = srcRule->mgmtInfo.ruleType; + dstRule->mgmtInfo.snat_aware_refcnt = srcRule->mgmtInfo.snat_aware_refcnt; + dstRule->mgmtInfo.dnat_aware_refcnt = srcRule->mgmtInfo.dnat_aware_refcnt; + + dstRule->routingInfo.aware_flags = srcRule->routingInfo.aware_flags; + dstRule->routingInfo.srcIp = srcRule->routingInfo.srcIp; + dstRule->routingInfo.dstIp = srcRule->routingInfo.dstIp; + dstRule->routingInfo.defGtwIp = srcRule->routingInfo.defGtwIp; + memcpy(dstRule->routingInfo.srcMac, srcRule->routingInfo.srcMac, MV_MAC_ADDR_SIZE); + memcpy(dstRule->routingInfo.dstMac, srcRule->routingInfo.dstMac, MV_MAC_ADDR_SIZE); + dstRule->routingInfo.inIfIndex = srcRule->routingInfo.inIfIndex; + dstRule->routingInfo.outIfIndex = srcRule->routingInfo.outIfIndex; +#ifdef CONFIG_MV_GATEWAY + dstRule->routingInfo.pktHdr = srcRule->routingInfo.pktHdr; +#endif /* CONFIG_MV_GATEWAY */ + +} + +/* Get the count value for a rule that matches the given SIP, DIP */ +MV_U32 mvFpRouteCountGet(MV_U32 srcIp, MV_U32 dstIp) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *pRule; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32)0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + while(pRule) + { + /* look for a matching rule */ + if( (pRule->routingInfo.dstIp == dstIp) && + (pRule->routingInfo.srcIp == srcIp) ) + { + return pRule->mgmtInfo.new_count; + } + pRule = pRule->next; + } + return 0; +} + +MV_STATUS mvFpRuleAwareSet(MV_FP_RULE *pSetRule) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *pRule; + + hash = mv_jhash_3words(pSetRule->routingInfo.dstIp, pSetRule->routingInfo.srcIp, + (MV_U32)0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + while(pRule) + { + if( (pRule->routingInfo.srcIp == pSetRule->routingInfo.srcIp) && + (pRule->routingInfo.dstIp == pSetRule->routingInfo.dstIp) ) { + + + pRule->routingInfo.aware_flags = pSetRule->routingInfo.aware_flags; +#ifdef MV_FP_DEBUG + mvOsPrintf("Update FP aware: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash0x%x, flags=0x%x\n", + MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), + hash_tr, pSetRule->routingInfo.aware_flags); +#endif + return MV_OK; + } + pRule = pRule->next; + } +#ifdef MV_FP_DEBUG + mvOsPrintf("FP aware NOT found: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%x, flags=0x%x\n", + MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), + hash_tr, pSetRule->routingInfo.aware_flags); +#endif + return MV_NOT_FOUND; +} + +/* Set a Routing Rule: create a new rule or update an existing rule */ +/* in the Routing + ARP information table */ +MV_STATUS mvFpRuleSet(MV_FP_RULE *pSetRule) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *pRule, *pNewRule; + + hash = mv_jhash_3words(pSetRule->routingInfo.dstIp, pSetRule->routingInfo.srcIp, + (MV_U32)0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + while(pRule) + { + if( (pRule->routingInfo.srcIp == pSetRule->routingInfo.srcIp && + pRule->routingInfo.dstIp == pSetRule->routingInfo.dstIp) ) { + + mvFpRuleCopy(pRule, pSetRule); + nfpRuleUpdateCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf("UpdNFP_%03u: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%04x\n", + nfpRuleUpdateCount, MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), hash_tr); +#endif + return MV_OK; + } + pRule = pRule->next; + } + + /* Allocate new entry */ + pNewRule = mvOsMalloc(sizeof(MV_FP_RULE)); + if(pNewRule == NULL) + { + mvOsPrintf("mvFpRuleSet: Can't allocate new rule\n"); + return MV_FAIL; + } + + mvFpRuleCopy(pNewRule, pSetRule); + pNewRule->next = NULL; + + if(ruleDb[hash_tr].ruleChain == NULL) + ruleDb[hash_tr].ruleChain = pNewRule; + else { + pRule = ruleDb[hash_tr].ruleChain; + while (pRule->next != NULL) + pRule = pRule->next; + pRule->next = pNewRule; + } + nfpRuleSetCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf("SetNFP_%03u: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%04x, aware=0x%02x\n", + nfpRuleSetCount, MV_IP_QUAD(pSetRule->routingInfo.dstIp), + MV_IP_QUAD(pSetRule->routingInfo.srcIp), + hash_tr, pSetRule->routingInfo.aware_flags); +#endif + return MV_OK; +} + +/* Delete a specified rule from the Routing + ARP information table */ +MV_STATUS mvFpRuleDelete(MV_FP_RULE *rule) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE *currRule, *prevRule; + + nfpRuleDeleteCount++; + hash = mv_jhash_3words(rule->routingInfo.dstIp, rule->routingInfo.srcIp, + (MV_U32)0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + prevRule = NULL; + for (currRule = ruleDb[hash_tr].ruleChain; + currRule != NULL; + prevRule = currRule, currRule = currRule->next) + { + if( (currRule->routingInfo.srcIp == rule->routingInfo.srcIp) && + (currRule->routingInfo.dstIp == rule->routingInfo.dstIp) ) + { + if (prevRule == NULL) + ruleDb[hash_tr].ruleChain = currRule->next; + else + prevRule->next = currRule->next; +#ifdef MV_FP_DEBUG + mvOsPrintf("DelNFP_%03u: DIP=%u.%u.%u.%u, SIP=%u.%u.%u.%u, hash=0x%04x\n", + nfpRuleDeleteCount, MV_IP_QUAD(currRule->routingInfo.dstIp), + MV_IP_QUAD(currRule->routingInfo.srcIp), hash_tr); +#endif + mvOsFree(currRule); + return MV_OK; + } + } + return MV_NOT_FOUND; +} + +/* Find and return the first matching rule in the Routing + ARP information table */ +static INLINE MV_FP_RULE* mvFpRuleFind(MV_U32 dstIp, MV_U32 srcIp) +{ + MV_U32 hash, hash_tr; + MV_FP_RULE* pRule; + int count = 0; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32)0, fp_ip_jhash_iv); + hash_tr = hash & (ruleDbSize - 1); + + pRule = ruleDb[hash_tr].ruleChain; + + while(pRule) + { + /* look for a matching rule */ + if( (pRule->routingInfo.dstIp == dstIp) && + (pRule->routingInfo.srcIp == srcIp) ) + { + FASTPATH_STAT( ip_hash_depth[count]++); + pRule->mgmtInfo.new_count++; + return pRule; + } + pRule = pRule->next; + count++; + } + return NULL; +} + +int mvFpProcess(MV_U8* pData, MV_IP_HEADER* pIpHdr, MV_FP_STATS* pFpStats) +{ + MV_FP_RULE *pFpRoute; + MV_U32 dip, sip; +#ifdef CONFIG_MV_ETH_FP_NAT_SUPPORT + MV_U8 proto; + MV_U16 srcPort, dstPort; + MV_FP_NAT_RULE *pDnatRule, *pSnatRule; +#endif + MV_U8* pEthHeader = pData + ETH_MV_HEADER_SIZE; + + FASTPATH_STAT( pFpStats->process++ ); + + /* Check MAC address: + * WAN - non-promiscous mode. + * Unicast packets - NFP, + * Multicast, Broadcast - Linux + * LAN - Promiscous mode. + * LAN Unicast MAC - NFP, + * Multicast, Broadcast, Unknown Unicast - Linux + */ + if(pEthHeader[0] & 0x1) + { + /* Go to Linux IP stack */ + FASTPATH_STAT( pFpStats->multicast++); + return -1; + } + + /* Check TTL value */ + if(pIpHdr->ttl <= 1) + { + /* TTL expired */ + FASTPATH_STAT( pFpStats->ip_ttl_expired++ ); + return -1; + } + + dip = pIpHdr->dstIP; + sip = pIpHdr->srcIP; +#ifdef CONFIG_MV_ETH_FP_NAT_SUPPORT + proto = mvFpNatPortsGet(pIpHdr, &dstPort, &srcPort); + if(proto == MV_IP_PROTO_NULL) + { + /* NAT not supported for this protocol */ + FASTPATH_STAT( pFpStats->nat_bad_proto++ ); + pDnatRule = NULL; + } + else + { + /* Lookup NAT database accordingly with 5 tuple key */ + pDnatRule = mvFpNatRuleFind(dip, sip, proto, dstPort, srcPort); + } + if(pDnatRule != NULL) + { + if(pDnatRule->flags & MV_FP_DIP_CMD_MAP) + { + dip = pDnatRule->newIp; + } + if(pDnatRule->flags & MV_FP_DPORT_CMD_MAP) + { + dstPort = pDnatRule->newPort; + } + } + else + { + FASTPATH_STAT( pFpStats->dnat_not_found++ ); + } + +#endif /* CONFIG_MV_ETH_FP_NAT_SUPPORT */ + + pFpRoute = mvFpRuleFind(dip, sip); + if(pFpRoute == NULL) + { + /* IP Routing rule is not found: go to Linux IP stack */ + FASTPATH_STAT( pFpStats->ip_not_found++ ); + return -1; + } + FASTPATH_STAT(pFpStats->ip_found++); + +#ifdef CONFIG_MV_ETH_FP_NAT_SUPPORT + if( (pDnatRule != NULL) && (pDnatRule->flags & MV_FP_DNAT_CMD_MAP) ) + { + FASTPATH_STAT( pFpStats->dnat_found++ ); + pSnatRule = mvFpNatRuleFind(dip, sip, proto, dstPort, srcPort); + } + else + { + pSnatRule = pDnatRule; + } + + if( (pSnatRule != NULL) && (pSnatRule->flags & MV_FP_SNAT_CMD_MAP) ) + { + FASTPATH_STAT( pFpStats->snat_found++ ); + } + else + { + FASTPATH_STAT( pFpStats->snat_not_found++ ); + } + + /* Check IP awareness */ + if( (pFpRoute->routingInfo.aware_flags & MV_FP_DIP_CMD_MAP) && + (pDnatRule == NULL) ) + { + FASTPATH_STAT( pFpStats->dnat_aware++ ); + return -1; + } + + if( (pFpRoute->routingInfo.aware_flags & MV_FP_SIP_CMD_MAP) && + (pSnatRule == NULL) ) + { + FASTPATH_STAT( pFpStats->snat_aware++ ); + return -1; + } + + /* Update packet accordingly with NAT rules */ + if( (pDnatRule != NULL) || (pSnatRule != NULL) ) + { + mvFpNatPktUpdate(pIpHdr, pDnatRule, pSnatRule); + } +#endif /* CONFIG_MV_ETH_FP_NAT_SUPPORT */ + + if( (unsigned int)pEthHeader & 0x2) + { + *((MV_U16*)(pEthHeader)) = *(MV_U16*)(&pFpRoute->routingInfo.dstMac[0]); + *((MV_U32*)(pEthHeader + 2)) = *(MV_U32*)(&pFpRoute->routingInfo.dstMac[2]); + *((MV_U32*)(pEthHeader + 2 + 4)) = *(MV_U32*)(&pFpRoute->routingInfo.srcMac[0]); + *((MV_U16*)(pEthHeader + 2 + 4 + 4)) = *(MV_U16*)(&pFpRoute->routingInfo.srcMac[4]); + } + else + { + memcpy(pEthHeader, pFpRoute->routingInfo.dstMac, MV_MAC_ADDR_SIZE*2); + } + pIpHdr->ttl--; +#if defined(CONFIG_MV_GTW_HEADER_MODE) + memcpy(pData, &(pFpRoute->routingInfo.pktHdr.mvHeader.header), ETH_MV_HEADER_SIZE); +#endif + mvOsCacheLineFlushInv(pPortCtrl->osHandle, pData); + mvOsCacheLineFlushInv(pPortCtrl->osHandle, pData + CPU_D_CACHE_LINE_SIZE); + + return pFpRoute->routingInfo.outIfIndex; +} + +void mvFpStatsPrint(MV_FP_STATS *pFpStats) +{ +#ifdef MV_FP_STATISTICS + int i = 0; + + mvOsPrintf( "\n====================================================\n" ); + mvOsPrintf( "fast path statistics"); + mvOsPrintf( "\n-------------------------------\n" ); + + mvOsPrintf( "fast_path_parsing.............%10u\n", pFpStats->parsing ); + mvOsPrintf( "fast_path_process.............%10u\n", pFpStats->process ); + mvOsPrintf( "fast_path_multicast...........%10u\n", pFpStats->multicast ); + mvOsPrintf( "fast_path_non_ip..............%10u\n", pFpStats->non_ip ); + mvOsPrintf( "fast_path_vlan_tagged.........%10u\n", pFpStats->vlan_tagged ); + mvOsPrintf( "fast_path_ip_not_found........%10u\n", pFpStats->ip_not_found ); + mvOsPrintf( "fast_path_ttl_expired.........%10u\n", pFpStats->ip_ttl_expired ); + mvOsPrintf( "fast_path_ip_found............%10u\n", pFpStats->ip_found ); + +#ifdef CONFIG_MV_ETH_FP_NAT_SUPPORT + mvOsPrintf( "fp_nat_bad_proto..............%10u\n", pFpStats->nat_bad_proto); + mvOsPrintf( "fp_nat_dnat_found.............%10u\n", pFpStats->dnat_found); + mvOsPrintf( "fp_nat_snat_found.............%10u\n", pFpStats->snat_found); + mvOsPrintf( "fp_nat_dnat_not_found.........%10u\n", pFpStats->dnat_not_found); + mvOsPrintf( "fp_nat_snat_not_found.........%10u\n", pFpStats->snat_not_found); + mvOsPrintf( "fp_nat_dnat_aware.............%10u\n", pFpStats->dnat_aware); + mvOsPrintf( "fp_nat_snat_aware.............%10u\n", pFpStats->snat_aware); +#endif /* CONFIG_MV_ETH_FP_NAT_SUPPORT */ + + mvOsPrintf("\nHASH Depth IP stats\n"); + for(i=0; i<=ETH_FP_MAX_HASH_DEPTH; i++) + { + if(ip_hash_depth[i] != 0) + { + mvOsPrintf("%d depth - %u times\n", i, ip_hash_depth[i]); + ip_hash_depth[i] = 0; + } + } + +#ifdef CONFIG_MV_ETH_FP_NAT_SUPPORT + mvOsPrintf("\nHASH Depth NAT stats\n"); + for(i=0; i<=ETH_FP_MAX_HASH_DEPTH; i++) + { + if(nat_hash_depth[i] != 0) + { + mvOsPrintf("%d depth - %u times\n", i, nat_hash_depth[i]); + nat_hash_depth[i] = 0; + } + } +#endif /* CONFIG_MV_ETH_FP_NAT_SUPPORT */ + + memset(pFpStats, 0, sizeof(MV_FP_STATS)); +#endif /* MV_FP_STATISTICS */ + mvOsPrintf("\n"); + mvOsPrintf("nfpRuleSetCount=%u, nfpRuleUpdateCount=%u, nfpRuleDeleteCount=%u\n", + nfpRuleSetCount, nfpRuleUpdateCount, nfpRuleDeleteCount); + +#ifdef CONFIG_MV_ETH_FP_NAT_SUPPORT + mvOsPrintf("\n"); + mvOsPrintf("natRuleSetCount=%u, natRuleUpdateCount=%u, natRuleDeleteCount=%u\n", + natRuleSetCount, natRuleUpdateCount, natRuleDeleteCount); +#endif /* CONFIG_MV_ETH_FP_NAT_SUPPORT */ +} + diff --git a/board/mv_feroceon/mv_hal/ethfp/fast_path/mvFastPath.h b/board/mv_feroceon/mv_hal/ethfp/fast_path/mvFastPath.h new file mode 100644 index 0000000..6e47286 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ethfp/fast_path/mvFastPath.h @@ -0,0 +1,415 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvFastPath.h - Header File for Marvell NFP (Routing and NAT) +* +* DESCRIPTION: +* This header file contains macros, typedefs and function declarations +* specific to the Marvell Network Fast Processing (Routing and NAT). +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvFastPath_h__ +#define __mvFastPath_h__ + +/* includes */ +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvStack.h" +#include "mv802_3.h" +#include "mvSysHwConfig.h" +#include "ethfp/mvEth.h" + +/* defines */ +#define ETH_FP_MAX_HASH_DEPTH 8 + +/* uncomment to open some debug prints on adding and updating Fast Path rules */ +/* #define MV_FP_DEBUG */ + +#ifdef MV_FP_STATISTICS +# define FASTPATH_STAT(CODE) CODE; +#else +# define FASTPATH_STAT(CODE) +#endif + +/* enumerations */ +typedef enum { + MV_FP_ROUTE_CMD, /* perform fast path routing */ + MV_FP_DROP_CMD, /* drop packet */ + MV_FP_TO_STACK_CMD, /* pass packet to linux stack */ + MV_FP_DIP_CMD, /* replace DIP */ + MV_FP_SIP_CMD, /* replace SIP */ + MV_FP_DPORT_CMD, /* replace DPORT */ + MV_FP_SPORT_CMD, /* replace SPORT */ + +} MV_FP_CMD_TYPE; + +#define MV_FP_NULL_BINDING 0 +#define MV_FP_NULL_BINDING_SET (1 << MV_FP_ROUTE_CMD) + +#define MV_FP_DIP_CMD_MAP (1 << MV_FP_DIP_CMD) +#define MV_FP_DPORT_CMD_MAP (1 << MV_FP_DPORT_CMD) +#define MV_FP_DNAT_CMD_MAP (MV_FP_DIP_CMD_MAP | MV_FP_DPORT_CMD_MAP) + +#define MV_FP_SIP_CMD_MAP (1 << MV_FP_SIP_CMD) +#define MV_FP_SPORT_CMD_MAP (1 << MV_FP_SPORT_CMD) +#define MV_FP_SNAT_CMD_MAP (MV_FP_SIP_CMD_MAP | MV_FP_SPORT_CMD_MAP) + +typedef enum { + MV_FP_STATIC_RULE, /* a static rule created by the user */ + MV_FP_DYNAMIC_RULE /* a dynamic rule */ + +} MV_FP_RULE_TYPE; + +/* structure definitions (used by the NFP Manager and the NFP Database)*/ +typedef struct { + MV_FP_CMD_TYPE actionType; + MV_U32 old_count; + int new_count; + MV_FP_RULE_TYPE ruleType; + int dnat_aware_refcnt; + int snat_aware_refcnt; + +} MV_FP_RULE_MGMT_INFO; + +typedef struct { + MV_U32 dstIp; + MV_U32 srcIp; + MV_U32 defGtwIp; + +#ifdef CONFIG_MV_GATEWAY + MV_ETH_PKT_HDR pktHdr; +#endif /* CONFIG_MV_GATEWAY */ + + MV_U8 reserved; + MV_U8 aware_flags; + /* dstMac should be 2 byte aligned */ + MV_U8 dstMac[MV_MAC_ADDR_SIZE]; + MV_U8 srcMac[MV_MAC_ADDR_SIZE]; + MV_U8 inIfIndex; /* Linux interface index */ + MV_U8 outIfIndex; /* Linux interface index */ + +} MV_FP_RULE_ROUTING_INFO; + +typedef struct _mv_fp_rule { + struct _mv_fp_rule *next; + + MV_FP_RULE_MGMT_INFO mgmtInfo; + MV_FP_RULE_ROUTING_INFO routingInfo; + +} MV_FP_RULE; + +struct ruleHashBucket { + MV_FP_RULE *ruleChain; /* This is an entry in the rule hash table. */ + + /* Add additional fields (such as a lock) here if required */ +}; + +#define MV_JHASH_MIX(a, b, c) \ +{ \ + a -= b; a -= c; a ^= (c>>13); \ + b -= c; b -= a; b ^= (a<<8); \ + c -= a; c -= b; c ^= (b>>13); \ + a -= b; a -= c; a ^= (c>>12); \ + b -= c; b -= a; b ^= (a<<16); \ + c -= a; c -= b; c ^= (b>>5); \ + a -= b; a -= c; a ^= (c>>3); \ + b -= c; b -= a; b ^= (a<<10); \ + c -= a; c -= b; c ^= (b>>15); \ +} + +/* The golden ration: an arbitrary value */ +#define MV_JHASH_GOLDEN_RATIO 0x9e3779b9 + +extern MV_U32 fp_ip_jhash_iv; +extern MV_U32 natRuleUpdateCount, natRuleSetCount, natRuleDeleteCount; + +static INLINE MV_U32 mv_jhash_3words(MV_U32 a, MV_U32 b, MV_U32 c, MV_U32 initval) +{ + a += MV_JHASH_GOLDEN_RATIO; + b += MV_JHASH_GOLDEN_RATIO; + c += initval; + MV_JHASH_MIX(a, b, c); + + return c; +} + +typedef struct _mv_fp_nat_rule { + struct _mv_fp_nat_rule *next; + MV_U32 old_count; + MV_U32 new_count; + + /* Original packet information */ + /* Fields will contain invalid values if they are irrelevant */ + MV_U32 srcIp; + MV_U32 dstIp; + MV_U16 srcPort; + MV_U16 dstPort; + MV_U8 proto; + + /* NAT information */ + MV_U8 flags; + MV_U32 newIp; + MV_U16 newPort; + +} MV_FP_NAT_RULE; + +struct natRuleHashBucket { + MV_FP_NAT_RULE *natRuleChain; /* This is an entry in the NAT rule hash table. */ + + /* Add additional fields (such as a lock) here if required */ +}; + +extern MV_U32 nat_hash_depth[]; + +extern struct natRuleHashBucket *natRuleDb; +extern MV_U32 natRuleDbSize; + +typedef struct +{ + MV_U32 parsing, process, multicast, non_ip, vlan_tagged; + MV_U32 ip_not_found, ip_ttl_expired, ip_found; + +#ifdef CONFIG_MV_ETH_FP_NAT_SUPPORT + MV_U32 nat_bad_proto; + MV_U32 dnat_aware; + MV_U32 snat_aware; + MV_U32 dnat_found; + MV_U32 snat_found; + MV_U32 dnat_not_found; + MV_U32 snat_not_found; +#endif + +} MV_FP_STATS; + +static INLINE MV_IP_HEADER* mvFpParsing(MV_PKT_INFO *pPktInfo, MV_FP_STATS* pFpStats) +{ + MV_U8 *pData; + MV_IP_HEADER *pIpHdr; + MV_U32 tx_status; + + pData = (MV_U8*)pPktInfo->pFrags[0].bufVirtPtr + ETH_MV_HEADER_SIZE; + + FASTPATH_STAT( pFpStats->parsing++ ); + + /* Check LLC/SNAP and IP header */ + if( ((pPktInfo->status & ETH_RX_NOT_LLC_SNAP_FORMAT_MASK) == 0) || + ((pPktInfo->status & ETH_RX_IP_HEADER_OK_MASK) == 0) || + (pPktInfo->fragIP) ) + { + /* Non IP packet: go to Linux IP stack */ + FASTPATH_STAT( pFpStats->non_ip++ ); + return NULL; + } + tx_status = ( ETH_TX_GENERATE_IP_CHKSUM_MASK + | ETH_TX_IP_NO_FRAG + | (5 << ETH_TX_IP_HEADER_LEN_OFFSET) ); + + /* Calculate start of IP header */ + if( (pPktInfo->status & ETH_RX_VLAN_TAGGED_FRAME_MASK) ) + { + FASTPATH_STAT(pFpStats->vlan_tagged++); + pIpHdr = (MV_IP_HEADER*)(pData + sizeof(MV_802_3_HEADER) + MV_VLAN_HLEN); + tx_status |= ETH_TX_VLAN_TAGGED_FRAME_MASK; + } + else + { + pIpHdr = (MV_IP_HEADER*)(pData + sizeof(MV_802_3_HEADER)); + } + + if( (pPktInfo->status & ETH_RX_L4_TYPE_MASK) == ETH_RX_L4_TCP_TYPE ) + { + tx_status |= (ETH_TX_L4_TCP_TYPE | ETH_TX_GENERATE_L4_CHKSUM_MASK); + } + else if( (pPktInfo->status & ETH_RX_L4_TYPE_MASK) == ETH_RX_L4_UDP_TYPE ) + { + tx_status |= (ETH_TX_L4_UDP_TYPE | ETH_TX_GENERATE_L4_CHKSUM_MASK); + } + + pPktInfo->status = tx_status; + + return pIpHdr; +} + +/* Find and return the first matching rule */ +static INLINE MV_FP_NAT_RULE* mvFpNatRuleFind(MV_U32 dstIp, MV_U32 srcIp, + MV_U8 proto, MV_U16 dport, MV_U16 sport) +{ + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE* pNatRule; + int count = 0; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32)((dport << 16) | sport), + (MV_U32)((fp_ip_jhash_iv << 8) | proto)); + hash_tr = hash & (natRuleDbSize - 1); +/* + mvOsPrintf("mvFpNatRuleFind: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%08x (0x%x)\n", + dstIp, srcIp, proto, dport, sport, hash, hash_tr); +*/ + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while(pNatRule) + { + /* look for a matching rule */ + if( (pNatRule->dstIp == dstIp) && + (pNatRule->srcIp == srcIp) && + (pNatRule->proto == proto) && + (pNatRule->dstPort == dport) && + (pNatRule->srcPort == sport) ) + { + FASTPATH_STAT( nat_hash_depth[count]++); + pNatRule->new_count++; + return pNatRule; + } + pNatRule = pNatRule->next; + count++; + } + return NULL; +} + + +/* function headers: */ + +/* Initialize NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbInit(MV_U32 dbSize); + +/* Clear NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbClear(void); + +/* Free Rule Database memory */ +void mvFpRuleDbDestroy(void); + +/* Print NFP Rule Database (Routing + ARP information table) */ +MV_STATUS mvFpRuleDbPrint(void); + +/* Copy all the information from src_rule to new_rule */ +/* Warning - doesn't perform any checks on memory, just copies */ +/* count is set to zero in new_rule */ +/* Note: the next pointer is not updated . */ +void mvFpRuleCopy(MV_FP_RULE *newRule, const MV_FP_RULE *srcRule); + +/* Get the maximum count value for a rule with srcIp == given ip */ +MV_U32 mvFpMaxArpCountGet(MV_U32 ip); + +/* Get the count value for a rule that matches the given SIP, DIP */ +MV_U32 mvFpRouteCountGet(MV_U32 srcIp, MV_U32 dstIp); + +/* Set a Routing Rule: create a new rule or update an existing rule */ +/* in the Routing + ARP information table */ +MV_STATUS mvFpRuleSet(MV_FP_RULE *rule); + +/* Delete a specified rule from the Routing + ARP information table */ +MV_STATUS mvFpRuleDelete(MV_FP_RULE *rule); + +/* Print a Rule */ +void mvFpRulePrint(const MV_FP_RULE *rule); + +/* Enable NFP */ +void mvFpEnable(void); + +/* Give all packets to Linux IP stack */ +void mvFpDisable(void); + +MV_STATUS mvFpInit(void); +int mvFpProcess(MV_U8* pData, MV_IP_HEADER* pIpHdr, MV_FP_STATS* pFpStats); +void mvFpStatsPrint(MV_FP_STATS *pFpStats); + +/* Initialize NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbInit(MV_U32 dbSize); + +/* Clear NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbClear(void); + +/* Free NAT Database memory */ +void mvFpNatDbDestroy(void); + +/* Set a NAT rule: create a new rule or update an existing rule in the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleSet(MV_FP_NAT_RULE *natRule); + +MV_STATUS mvFpRuleAwareSet(MV_FP_RULE *pSetRule); + +/* Delete a specified NAT rule from the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleDelete(MV_FP_NAT_RULE *natRule); + +/* Get the count value for a NAT rule */ +MV_U32 mvFpNatCountGet(MV_U32 srcIp, MV_U32 dstIp, MV_U16 srcPort, MV_U16 dstPort, MV_U8 proto); + +/* Print NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbPrint(void); + +/* Print a NAT Rule */ +void mvFpNatRulePrint(const MV_FP_NAT_RULE *rule); + +/* Extract dstPort and srcPort values from the packet */ +MV_U8 mvFpNatPortsGet(MV_IP_HEADER* pIpHdr, MV_U16* pDstPort, MV_U16* pSrcPort); + +int mvFpNatPktUpdate(MV_IP_HEADER* pIpHdr, MV_FP_NAT_RULE* pDnatRule, MV_FP_NAT_RULE* pSnatRule); + +#endif /* __mvFastPath_h__ */ + + diff --git a/board/mv_feroceon/mv_hal/ethfp/fast_path/mvFpNat.c b/board/mv_feroceon/mv_hal/ethfp/fast_path/mvFpNat.c new file mode 100644 index 0000000..d10ab4e --- /dev/null +++ b/board/mv_feroceon/mv_hal/ethfp/fast_path/mvFpNat.c @@ -0,0 +1,450 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "mvTypes.h" +#include "mvOs.h" +#include "mvStack.h" +#include "mvDebug.h" +#include "ethfp/fast_path/mvFastPath.h" +#include "ethfp/mvEth.h" + + +struct natRuleHashBucket *natRuleDb; +MV_U32 natRuleDbSize; + +MV_U32 natRuleUpdateCount = 0; +MV_U32 natRuleSetCount = 0; +MV_U32 natRuleDeleteCount = 0; + +/* Initialize NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbInit(MV_U32 dbSize) +{ + natRuleDb = (struct natRuleHashBucket *)mvOsMalloc(sizeof(struct natRuleHashBucket)*dbSize); + if (natRuleDb == NULL) { + mvOsPrintf("NFP NAT Rule DB: Not Enough Memory\n"); + return MV_NO_RESOURCE; + } + natRuleDbSize = dbSize; + memset(natRuleDb, 0, sizeof(struct natRuleHashBucket)*natRuleDbSize); + + natRuleSetCount = natRuleDeleteCount = natRuleUpdateCount = 0; + + mvOsPrintf("mvFpNatDb (%p): %d entries, %d bytes\n", + natRuleDb, natRuleDbSize, sizeof(struct natRuleHashBucket)*natRuleDbSize); + + return MV_OK; +} + +/* Clear NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbClear(void) +{ + MV_U32 i = 0; + MV_FP_NAT_RULE *currRule; + MV_FP_NAT_RULE *tmpRule; + + if (natRuleDb == NULL) + return MV_NOT_INITIALIZED; + + for (i = 0; i < natRuleDbSize; i++) { + currRule = natRuleDb[i].natRuleChain; + while (currRule != NULL) { + tmpRule = currRule; + currRule = currRule->next; + mvOsFree(tmpRule); + } + natRuleDb[i].natRuleChain = NULL; + } + return MV_OK; +} + +/* Free NAT Database memory */ +void mvFpNatDbDestroy(void) +{ + if (natRuleDb != NULL) + mvOsFree(natRuleDb); +} + +static void mvFpNatRuleUpdate(MV_FP_NAT_RULE *dstRule, const MV_FP_NAT_RULE *srcRule) +{ + dstRule->flags = srcRule->flags; + dstRule->newIp = srcRule->newIp; + dstRule->newPort = srcRule->newPort; + dstRule->new_count = srcRule->new_count; + dstRule->old_count = srcRule->old_count; +} + +/* Set a NAT rule: create a new rule or update an existing rule in the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleSet(MV_FP_NAT_RULE *pSetRule) +{ + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE *pNatRule, *pNewRule; + + hash = mv_jhash_3words(pSetRule->dstIp, pSetRule->srcIp, + (MV_U32)((pSetRule->dstPort << 16) | pSetRule->srcPort), + (MV_U32)((fp_ip_jhash_iv << 8) | pSetRule->proto)); + hash_tr = hash & (natRuleDbSize - 1); + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while(pNatRule) + { + /* look for a matching rule */ + if( (pNatRule->dstIp == pSetRule->dstIp) && + (pNatRule->srcIp == pSetRule->srcIp) && + (pNatRule->proto == pSetRule->proto) && + (pNatRule->dstPort == pSetRule->dstPort) && + (pNatRule->srcPort == pSetRule->srcPort) ) + { + /* update rule */ + mvFpNatRuleUpdate(pNatRule, pSetRule); + natRuleUpdateCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf("UpdNAT_%03u: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%04x, flags=0x%02x\n", + natRuleUpdateCount, pNatRule->dstIp, pNatRule->srcIp, pNatRule->proto, + MV_16BIT_BE(pNatRule->dstPort), MV_16BIT_BE(pNatRule->srcPort), hash_tr, pNatRule->flags); +#endif + return MV_OK; + } + pNatRule = pNatRule->next; + } + /* Allocate new entry */ + pNewRule = mvOsMalloc(sizeof(MV_FP_NAT_RULE)); + if(pNewRule == NULL) + { + mvOsPrintf("mvFpNatRuleSet: Can't allocate new rule\n"); + return MV_FAIL; + } + + memcpy(pNewRule, pSetRule, sizeof(*pNewRule)); + pNewRule->next = NULL; + + if(natRuleDb[hash_tr].natRuleChain == NULL) + { + natRuleDb[hash_tr].natRuleChain = pNewRule; + } + else + { + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while (pNatRule->next != NULL) + pNatRule = pNatRule->next; + + pNatRule->next = pNewRule; + } + natRuleSetCount++; + +#ifdef MV_FP_DEBUG + mvOsPrintf("SetNAT_%03u: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%04x, flags=0x%02x\n", + natRuleSetCount, pNewRule->dstIp, pNewRule->srcIp, pNewRule->proto, + MV_16BIT_BE(pNewRule->dstPort), MV_16BIT_BE(pNewRule->srcPort), hash_tr, pNewRule->flags); +#endif + return MV_OK; +} + +/* Delete a specified NAT rule from the SNAT + DNAT table */ +MV_STATUS mvFpNatRuleDelete(MV_FP_NAT_RULE *natRule) +{ + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE *currRule, *prevRule; + + natRuleDeleteCount++; + + hash = mv_jhash_3words(natRule->dstIp, natRule->srcIp, + (MV_U32)((natRule->dstPort << 16) | natRule->srcPort), + (MV_U32)((fp_ip_jhash_iv << 8) | natRule->proto)); + hash_tr = hash & (natRuleDbSize - 1); + + prevRule = NULL; + for (currRule = natRuleDb[hash_tr].natRuleChain; + currRule != NULL; + prevRule = currRule, currRule = currRule->next) + { + if (currRule->srcIp == natRule->srcIp && + currRule->dstIp == natRule->dstIp && + currRule->srcPort == natRule->srcPort && + currRule->dstPort == natRule->dstPort && + currRule->proto == natRule->proto ) + { + if (prevRule == NULL) + natRuleDb[hash_tr].natRuleChain = currRule->next; + else + prevRule->next = currRule->next; + +#ifdef MV_FP_DEBUG + mvOsPrintf("DelNAT_%03u: DIP=0x%08x, SIP=0x%08x, proto=%d, DPort=%d, SPort=%d, hash=0x%04x\n", + natRuleDeleteCount, currRule->dstIp, currRule->srcIp, currRule->proto, + MV_16BIT_BE(currRule->dstPort), MV_16BIT_BE(currRule->srcPort), hash_tr); +#endif + mvOsFree(currRule); + return MV_OK; + } + } + return MV_NOT_FOUND; +} + +/* Check that protocol supported for FP NAT and extract srcPort and dstPort + * (or their equivalents) from the packet. + */ +MV_U8 mvFpNatPortsGet(MV_IP_HEADER* pIpHdr, MV_U16* pDstPort, MV_U16* pSrcPort) +{ + MV_U8 proto = pIpHdr->protocol; + MV_UDP_HEADER *pUdpHdr; + MV_TCP_HEADER *pTcpHdr; + MV_ICMP_ECHO_HEADER *pIcmpHdr; + + switch(proto) + { + case MV_IP_PROTO_TCP: + pTcpHdr = (MV_TCP_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + *pDstPort = pTcpHdr->dest; + *pSrcPort = pTcpHdr->source; + break; + + case MV_IP_PROTO_UDP: + pUdpHdr = (MV_UDP_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + *pDstPort = pUdpHdr->dest; + *pSrcPort = pUdpHdr->source; + break; + + case MV_IP_PROTO_ICMP: + pIcmpHdr = (MV_ICMP_ECHO_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + if( (pIcmpHdr->type == MV_ICMP_ECHO) || (pIcmpHdr->type == MV_ICMP_ECHOREPLY) ) + { + *pDstPort = (pIcmpHdr->code << 8) | (pIcmpHdr->type); + *pSrcPort = pIcmpHdr->id; + } + else + { + /* Do NAT for IP + protocol only (without ports) */ + *pDstPort = 0; + *pSrcPort = 0; + } + break; + + case MV_IP_PROTO_ZERO_HOP: + /* Do NAT for IP + protocol only (without ports) */ + *pDstPort = 0; + *pSrcPort = 0; + break; + + /* Other protocols supporting NAT only without ports + * case ???????: + * case ???????: + * *pDstPort = 0; + * *pSrcPort = 0; + * break + * + */ + + default: + /* Skip NAT processing at all */ + proto = MV_IP_PROTO_NULL; + } + return proto; +} + +int mvFpNatPktUpdate(MV_IP_HEADER* pIpHdr, MV_FP_NAT_RULE* pDnatRule, MV_FP_NAT_RULE* pSnatRule) +{ + MV_UDP_HEADER *pUdpHdr; + MV_TCP_HEADER *pTcpHdr; + MV_ICMP_ECHO_HEADER *pIcmpHdr; + int hdr_size = 0; + MV_U16 *pDstPort=NULL, *pSrcPort=NULL; + + switch(pIpHdr->protocol) + { + case MV_IP_PROTO_TCP: + pTcpHdr = (MV_TCP_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + pDstPort = &pTcpHdr->dest; + pSrcPort = &pTcpHdr->source; + hdr_size = sizeof(MV_TCP_HEADER); + break; + + case MV_IP_PROTO_UDP: + pUdpHdr = (MV_UDP_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + pDstPort = &pUdpHdr->dest; + pSrcPort = &pUdpHdr->source; + hdr_size = sizeof(MV_UDP_HEADER); + break; + + case MV_IP_PROTO_ICMP: + pIcmpHdr = (MV_ICMP_ECHO_HEADER*)((unsigned)pIpHdr + sizeof(MV_IP_HEADER)); + if( (pIcmpHdr->type == MV_ICMP_ECHO) || (pIcmpHdr->type == MV_ICMP_ECHOREPLY) ) + { + pDstPort = &pIcmpHdr->id; + pSrcPort = &pIcmpHdr->id; + hdr_size = sizeof(MV_ICMP_ECHO_HEADER); + } + else + { + mvOsPrintf("Wrong ICMP type: 0x%x\n", pIcmpHdr->type & 0xFF); + } + break; + + case MV_IP_PROTO_ZERO_HOP: + /* Do nothing - only IP addresses are updated for this protocol */ + break; + + default: + mvOsPrintf("Unexpected IP protocol: 0x%x\n", + pIpHdr->protocol); + } + if(pDnatRule != NULL) + { + if(pDnatRule->flags & MV_FP_DIP_CMD_MAP) + pIpHdr->dstIP = pDnatRule->newIp; + if( (pDnatRule->flags & MV_FP_DPORT_CMD_MAP) && + (pDstPort != NULL) ) + *pDstPort = pDnatRule->newPort; + } + + if(pSnatRule != NULL) + { + if(pSnatRule->flags & MV_FP_SIP_CMD_MAP) + pIpHdr->srcIP = pSnatRule->newIp; + + if( (pSnatRule->flags & MV_FP_SPORT_CMD_MAP) && + (pSrcPort != NULL) ) + *pSrcPort = pSnatRule->newPort; + } + return hdr_size; +} + +/* Print a NFP NAT Rule */ +void mvFpNatRulePrint(const MV_FP_NAT_RULE *rule) +{ + /* Note: some of the fields in the NAT rule may contain invalid values */ + mvOsPrintf("Original packet: "); + mvOsPrintf("SIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->srcIp)), + mvOsPrintf(", DIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->dstIp)), + mvOsPrintf(", SPort=%d", MV_16BIT_BE(rule->srcPort)); + mvOsPrintf(", DPort=%d", MV_16BIT_BE(rule->dstPort)); + mvOsPrintf("\nNAT Info: "); + mvOsPrintf("count=%u, flags=0x%x", rule->new_count, rule->flags); + mvOsPrintf(", newIP="); + mvDebugPrintIpAddr(MV_32BIT_BE(rule->newIp)); + mvOsPrintf(", newPort=%d", MV_16BIT_BE(rule->newPort)); + mvOsPrintf("\n"); +} + +/* Print NFP NAT Rule Database (SNAT + DNAT table) */ +MV_STATUS mvFpNatDbPrint(void) +{ + MV_U32 count, i = 0; + MV_FP_NAT_RULE *currRule; + + mvOsPrintf("\nPrinting NFP NAT Rule Database: \n"); + count = 0; + for (i=0; iflags != MV_FP_NULL_BINDING) || (currRule->new_count > 0) ) + { + mvOsPrintf("%03u: Rule=%p, Next=%p\n", count, currRule, currRule->next); + mvFpNatRulePrint(currRule); + } + currRule = currRule->next; + count++; + } + } + return MV_OK; +} + +/* Get the count value for a NAT rule */ +MV_U32 mvFpNatCountGet(MV_U32 srcIp, MV_U32 dstIp, MV_U16 srcPort, MV_U16 dstPort, MV_U8 proto) +{ + MV_U32 hash, hash_tr; + MV_FP_NAT_RULE *pNatRule; + + hash = mv_jhash_3words(dstIp, srcIp, (MV_U32)((dstPort << 16) | srcPort), + (MV_U32)((fp_ip_jhash_iv << 8) | proto)); + hash_tr = hash & (natRuleDbSize - 1); + pNatRule = natRuleDb[hash_tr].natRuleChain; + + while(pNatRule) + { + /* look for a matching rule */ + if( (pNatRule->dstIp == dstIp) && + (pNatRule->srcIp == srcIp) && + (pNatRule->proto == proto) && + (pNatRule->dstPort == dstPort) && + (pNatRule->srcPort == srcPort) ) + { + return pNatRule->new_count; + } + pNatRule = pNatRule->next; + } + return 0; +} + diff --git a/board/mv_feroceon/mv_hal/ethfp/gbe/mvEth.c b/board/mv_feroceon/mv_hal/ethfp/gbe/mvEth.c new file mode 100644 index 0000000..c488ddc --- /dev/null +++ b/board/mv_feroceon/mv_hal/ethfp/gbe/mvEth.c @@ -0,0 +1,2944 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEth.c - Marvell's Gigabit Ethernet controller low level driver +* +* DESCRIPTION: +* This file introduce OS independent APIs to Marvell's Gigabit Ethernet +* controller. This Gigabit Ethernet Controller driver API controls +* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). +* 2) Data flow (i.e. port Send, Receive etc'). +* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) +* 4) MIB counters support (ethReadMibCounter) +* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) +* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. +* This struct includes configuration information as well as driver +* internal data needed for its operations. +* +* Supported Features: +* - OS independent. All required OS services are implemented via external +* OS dependent components (like osLayer or ethOsg) +* - The user is free from Rx/Tx queue managing. +* - Simple Gigabit Ethernet port operation API. +* - Simple Gigabit Ethernet port data flow API. +* - Data flow and operation API support per queue functionality. +* - Support cached descriptors for better performance. +* - PHY access and control API. +* - Port Configuration API. +* - Full control over Special and Other Multicast MAC tables. +* +*******************************************************************************/ +/* includes */ +#include "mvTypes.h" +#include "mv802_3.h" +#include "mvDebug.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "eth-phy/mvEthPhy.h" +#include "ethfp/mvEth.h" +#include "ethfp/gbe/mvEthGbe.h" +#include "cpu/mvCpu.h" + +#ifdef INCLUDE_SYNC_BARR +#include "sys/mvCpuIf.h" +#endif + +#ifdef MV_RT_DEBUG +# define ETH_DEBUG +#endif + + +/* locals */ +MV_BOOL ethDescInSram; +MV_BOOL ethDescSwCoher; + +/* This array holds the control structure of each port */ +ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; + +/* Ethernet Port Local routines */ + +static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); + +static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); + +static void ethSetUcastTable(int portNo, int queue); + +static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); +static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); +static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); + +static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); +static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, + MV_ULONG* pPhysAddr, MV_U32 *memHandle); + +static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); +#if 0 +static void mvEthPortSgmiiConfig(int port); +#endif /* 0 */ + + +/******************************************************************************/ +/* EthDrv Initialization functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthInit - Initialize the Giga Ethernet unit +* +* DESCRIPTION: +* This function initialize the Giga Ethernet unit. +* 1) Configure Address decode windows of the unit +* 2) Set registers to HW default values. +* 3) Clear and Disable interrupts +* +* INPUT: NONE +* +* RETURN: NONE +* +* NOTE: this function is called once in the boot process. +*******************************************************************************/ +void mvEthHalInit(void) +{ + int port; + + /* Init static data structures */ + for (port=0; port 0) + { + isSram = MV_TRUE; + #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) + isSwCoher = MV_TRUE; + #else + isSwCoher = MV_FALSE; + #endif + } +#endif /* ETH_DESCR_IN_SRAM */ + + if(pIsSram != NULL) + *pIsSram = isSram; + + if(pIsSwCoher != NULL) + *pIsSwCoher = isSwCoher; +} + + + +/******************************************************************************/ +/* Port Initialization functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthPortInit - Initialize the Ethernet port driver +* +* DESCRIPTION: +* This function initialize the ethernet port. +* 1) Allocate and initialize internal port Control structure. +* 2) Create RX and TX descriptor rings for default RX and TX queues +* 3) Disable RX and TX operations, clear cause registers and +* mask all interrupts. +* 4) Set all registers to default values and clean all MAC tables. +* +* INPUT: +* int portNo - Ethernet port number +* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure +* +* RETURN: +* void* - ethernet port handler, that should be passed to the most other +* functions dealing with this port. +* +* NOTE: This function is called once per port when loading the eth module. +*******************************************************************************/ +void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) +{ + int queue, descSize; + ETH_PORT_CTRL* pPortCtrl; + + /* Check validity of parameters */ + if( (portNo >= (int)mvCtrlEthMaxPortGet()) || + (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || + (pEthPortInit->maxRxPktSize < 1518) ) + { + mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); + return NULL; + } + if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) + { + mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", + portNo, pEthPortInit->rxDefQ); + return NULL; + } + + pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); + if(pPortCtrl == NULL) + { + mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", + (int)sizeof(ETH_PORT_CTRL), portNo); + return NULL; + } + + memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); + ethPortCtrl[portNo] = pPortCtrl; + + pPortCtrl->portState = MV_UNDEFINED_STATE; + + pPortCtrl->portNo = portNo; + + pPortCtrl->osHandle = pEthPortInit->osHandle; + + /* Copy Configuration parameters */ + pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; + pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; + pPortCtrl->portConfig.ejpMode = 0; + + for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; + } + for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; + } + + mvEthPortDisable(pPortCtrl); + + /* Set the board information regarding PHY address */ + mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); + + /* Create all requested RX queues */ + for(queue=0; queuerxQueueConfig[queue].descrNum == 0) + continue; + + /* Allocate memory for RX descriptors */ + descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + + CPU_D_CACHE_LINE_SIZE); + + pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = + ethAllocDescrMemory(pPortCtrl, descSize, + &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, + &pPortCtrl->rxQueue[queue].descBuf.memHandle); + pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; + if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) + { + mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", + pPortCtrl->portNo, queue, descSize, + ethDescInSram ? "SRAM" : "DRAM", + pPortCtrl->rxQueueConfig[queue].descrNum); + return NULL; + } + + ethInitRxDescRing(pPortCtrl, queue); + } + /* Create TX queues */ + for(queue=0; queuetxQueueConfig[queue].descrNum == 0) + continue; + + /* Allocate memory for TX descriptors */ + descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + + CPU_D_CACHE_LINE_SIZE); + + pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = + ethAllocDescrMemory(pPortCtrl, descSize, + &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, + &pPortCtrl->txQueue[queue].descBuf.memHandle); + pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; + if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) + { + mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", + pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", + pPortCtrl->txQueueConfig[queue].descrNum); + return NULL; + } + + ethInitTxDescRing(pPortCtrl, queue); + } + mvEthDefaultsSet(pPortCtrl); + + pPortCtrl->portState = MV_IDLE; + return pPortCtrl; +} + +/******************************************************************************* +* ethPortFinish - Finish the Ethernet port driver +* +* DESCRIPTION: +* This function finish the ethernet port. +* 1) Down ethernet port if needed. +* 2) Delete RX and TX descriptor rings for all created RX and TX queues +* 3) Free internal port Control structure. +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: NONE. +* +*******************************************************************************/ +void mvEthPortFinish(void* pPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + int queue, portNo = pPortCtrl->portNo; + + if(pPortCtrl->portState == MV_ACTIVE) + { + mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", + portNo); + mvEthPortDisable(pPortHndl); + } + + /* Free all allocated RX queues */ + for(queue=0; queuerxQueue[queue].descBuf); + } + + /* Free all allocated TX queues */ + for(queue=0; queuetxQueue[queue].descBuf); + } + + /* Free port control structure */ + mvOsFree(pPortCtrl); + + ethPortCtrl[portNo] = NULL; +} + +/******************************************************************************* +* mvEthDefaultsSet - Set defaults to the ethernet port +* +* DESCRIPTION: +* This function set default values to the ethernet port. +* 1) Clear Cause registers and Mask all interrupts +* 2) Clear all MAC tables +* 3) Set defaults to all registers +* 4) Reset all created RX and TX descriptors ring +* 5) Reset PHY +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure +* NOTE: +* This function update all the port configuration except those set +* Initialy by the OsGlue by MV_ETH_PORT_INIT. +* This function can be called after portDown to return the port setting +* to defaults. +*******************************************************************************/ +MV_STATUS mvEthDefaultsSet(void* pPortHndl) +{ + int ethPortNo, queue; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + MV_U32 txPrio; + MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; + MV_BOARD_MAC_SPEED boardMacCfg; + + ethPortNo = pPortCtrl->portNo; + + /* Clear Cause registers */ + MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); + MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); + + /* Mask all interrupts */ + MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); + MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); + + portCfgReg = PORT_CONFIG_VALUE; + portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; + + boardMacCfg = mvBoardMacSpeedGet(ethPortNo); + + if(boardMacCfg == BOARD_MAC_SPEED_100M) + { + portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; + } + else if(boardMacCfg == BOARD_MAC_SPEED_1000M) + { + portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; + } + else + { + portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; + } + + /* build PORT_SDMA_CONFIG_REG */ + portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); + portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); + +#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ + (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) + /* some devices have restricted RX burst size when using HW coherency */ + portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); +#else + portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); +#endif + +#if defined(MV_CPU_BE) + /* big endian */ +# if defined(MV_ARM) + portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | + ETH_TX_NO_DATA_SWAP_MASK | + ETH_DESC_SWAP_MASK); +# elif defined(MV_PPC) + portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | + ETH_TX_DATA_SWAP_MASK | + ETH_NO_DESC_SWAP_MASK); +# else +# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" +# endif /* MV_ARM / MV_PPC */ + +#else /* MV_CPU_LE */ + /* little endian */ + portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | + ETH_TX_NO_DATA_SWAP_MASK | + ETH_NO_DESC_SWAP_MASK); +#endif /* MV_CPU_BE / MV_CPU_LE */ + + pPortCtrl->portRxQueueCmdReg = 0; + pPortCtrl->portTxQueueCmdReg = 0; + +#if (MV_ETH_VERSION >= 4) + if(pPortCtrl->portConfig.ejpMode == MV_FALSE) + pPortCtrl->portTxQueueCmdReg = MV_32BIT_LE_FAST(ETH_TX_LEGACY_WRR_MASK); +#endif /* (MV_ETH_VERSION >= 4) */ + + ethSetUcastTable(ethPortNo, -1); + mvEthSetSpecialMcastTable(ethPortNo, -1); + mvEthSetOtherMcastTable(ethPortNo, -1); + + portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; + + portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); + + /* Update value of PortConfig register accordingly with all RxQueue types */ + pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; + + portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); + + portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); + + portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); + + portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); + + portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); + + /* Assignment of Tx CTRP of given queue */ + txPrio = 0; + + for(queue=0; queuetxQueue[queue]; + + if(pQueueCtrl->pFirstDescr != NULL) + { + ethResetTxDescRing(pPortCtrl, queue); + + MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), + 0x3fffffff); + MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), + 0x03ffffff); + } + else + { + MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); + MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); + } + } + + /* Assignment of Rx CRDP of given queue */ + for(queue=0; queueportNo; + + if( (pPortCtrl->portState != MV_ACTIVE) && + (pPortCtrl->portState != MV_PAUSED) ) + { + mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", + ethPortNo, pPortCtrl->portState); + return MV_BAD_STATE; + } + + ethPortNo = pPortCtrl->portNo; + + /* Enable port RX. */ + MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); + + /* Enable port TX. */ + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; + + pPortCtrl->portState = MV_ACTIVE; + + return MV_OK; +} + +/******************************************************************************* +* ethPortDown - Stop the Ethernet port activity. +* +* DESCRIPTION: +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE : used for port link down. +*******************************************************************************/ +MV_STATUS mvEthPortDown(void* pEthPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + int ethPortNum = pPortCtrl->portNo; + unsigned int regData; + volatile int uDelay, mDelay; + + /* Stop Rx port activity. Check port Rx activity. */ + regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; + if(regData != 0) + { + /* Issue stop command for active channels only */ + MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); + } + + /* Stop Tx port activity. Check port Tx activity. */ + regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; + if(regData != 0) + { + MV_U32 val; + + /* Issue stop command for active channels only */ + val = (regData << ETH_TXQ_DISABLE_OFFSET); + +#if (MV_ETH_VERSION >= 4) + if(pPortCtrl->portConfig.ejpMode == MV_FALSE) + val |= ETH_TX_LEGACY_WRR_MASK; + else + val |= ETH_TX_EJP_ENABLE_MASK; +#endif /* MV_ETH_VERSION >= 4 */ + + MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), val); + /* Writing 1 to Bit 19 is required for KW and OK for other SoCs */ + } + + /* Force link down */ +/* + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); +*/ + /* Wait for all Rx activity to terminate. */ + mDelay = 0; + do + { + if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) + { + mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", + ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + /* Check port RX Command register that all Rx queues are stopped */ + regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); + } + while(regData & 0xFF); + + /* Wait for all Tx activity to terminate. */ + mDelay = 0; + do + { + if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) + { + mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", + ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + /* Check port TX Command register that all Tx queues are stopped */ + regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); + } + while(regData & 0xFF); + + /* Double check to Verify that TX FIFO is Empty */ + mDelay = 0; + while(MV_TRUE) + { + do + { + if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) + { + mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", + ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); + } + while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || + ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); + + if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) + break; + + /* Double check */ + regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); + if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && + ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) + { + break; + } + else + mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", + ethPortNum, mDelay, regData); + } + + /* Do NOT force link down */ +/* + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); +*/ + /* Wait about 2500 tclk cycles */ + uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); + mvOsUDelay(uDelay); + + pPortCtrl->portState = MV_PAUSED; + + return MV_OK; +} + + +/******************************************************************************* +* ethPortEnable - Enable the Ethernet port and Start RX and TX. +* +* DESCRIPTION: +* This routine enable the Ethernet port and Rx and Tx activity: +* +* Note: Each Rx and Tx queue descriptor's list must be initialized prior +* to calling this function (use etherInitTxDescRing for Tx queues and +* etherInitRxDescRing for Rx queues). +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE: main usage is to enable the port after ifconfig up. +*******************************************************************************/ +MV_STATUS mvEthPortEnable(void* pEthPortHndl) +{ + int ethPortNo; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + MV_U32 portSerialCtrlReg; + + ethPortNo = pPortCtrl->portNo; + + /* Enable port */ + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); + portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); + + mvEthMibCountersClear(pEthPortHndl); + + pPortCtrl->portState = MV_PAUSED; + + /* If Link is UP, Start RX and TX traffic */ + if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) + return( mvEthPortUp(pEthPortHndl) ); + + return MV_NOT_READY; +} + + +/******************************************************************************* +* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. +* +* DESCRIPTION: +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE: main usage is to disable the port after ifconfig down. +*******************************************************************************/ +MV_STATUS mvEthPortDisable(void* pEthPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + int ethPortNum = pPortCtrl->portNo; + unsigned int regData; + volatile int mvDelay; + + if(pPortCtrl->portState == MV_ACTIVE) + { + /* Stop RX and TX activities */ + mvEthPortDown(pEthPortHndl); + } + + /* Reset the Enable bit in the Serial Control Register */ + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData &= ~(ETH_PORT_ENABLE_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); + + /* Wait about 2500 tclk cycles */ + mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); + for(mvDelay; mvDelay>0; mvDelay--); + + pPortCtrl->portState = MV_IDLE; + return MV_OK; +} + +/******************************************************************************* +* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. +* +* DESCRIPTION: +* This routine used to free buffers attached to the Tx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of TX queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. +* +* RETURN: +* MV_EMPTY - There is no more buffers in this queue. +* MV_OK - Buffer detached from the queue and pPktInfo structure +* filled with relevant information. +* +*******************************************************************************/ +MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + MV_PKT_INFO* pPktInfo; + ETH_TX_DESC* pTxDesc; + int port = pPortCtrl->portNo; + + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || + (pQueueCtrl->resource == 0) ) + { + /* Free next descriptor */ + pQueueCtrl->resource++; + pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; + pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; + pPktInfo->status = pTxDesc->cmdSts; + pTxDesc->cmdSts = 0x0; + pTxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); + + pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); + + if(pPktInfo->status & ETH_TX_LAST_DESC_MASK) + return pPktInfo; + } + MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + return NULL; +} + + + +/******************************************************************************* +* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. +* +* DESCRIPTION: +* This routine used to free buffers attached to the Rx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_EMPTY - There is no more buffers in this queue. +* MV_OK - Buffer detached from the queue and pBufInfo structure +* filled with relevant information. +* +*******************************************************************************/ +MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_RX_DESC* pRxDesc; + MV_PKT_INFO* pPktInfo; + int port = pPortCtrl->portNo; + + pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + if(pQueueCtrl->resource == 0) + { + MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + + return NULL; + } + /* Free next descriptor */ + pQueueCtrl->resource--; + pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; + pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; + + pPktInfo->status = pRxDesc->cmdSts; + pRxDesc->cmdSts = 0x0; + pRxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); + + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); + return pPktInfo; +} + + +/******************************************************************************/ +/* Port Configuration functions */ +/******************************************************************************/ +/******************************************************************************* +* mvEthMruGet - Get MRU configuration for Max Rx packet size. +* +* INPUT: +* MV_U32 maxRxPktSize - max packet size. +* +* RETURN: MV_U32 - MRU configuration. +* +*******************************************************************************/ +static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) +{ + MV_U32 portSerialCtrlReg = 0; + + if(maxRxPktSize > 9192) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; + else if(maxRxPktSize > 9022) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; + else if(maxRxPktSize > 1552) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; + else if(maxRxPktSize > 1522) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; + else if(maxRxPktSize > 1518) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; + else + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; + + return portSerialCtrlReg; +} + +/******************************************************************************* +* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path +* +* DESCRIPTION: +* This routine sets the RX coalescing interrupt mechanism parameter. +* This parameter is a timeout counter, that counts in 64 tClk +* chunks, that when timeout event occurs a maskable interrupt occurs. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the required number is in micro seconds. +* +* INPUT: +* void* pPortHndl - Ethernet Port handler. +* MV_U32 uSec - Number of micro seconds between +* RX interrupts +* +* RETURN: +* None. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); + MV_U32 portSdmaCfgReg; + + portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); + portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; + + portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); + +#if (MV_ETH_VERSION >= 2) + /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ + if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) + portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; +#endif /* MV_ETH_VERSION >= 2 */ + + MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); + return coal; +} + +/******************************************************************************* +* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path +* +* DESCRIPTION: +* This routine sets the TX coalescing interrupt mechanism parameter. +* This parameter is a timeout counter, that counts in 64 tClk +* chunks, that when timeout event occurs a maskable interrupt +* occurs. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the required number is in micro seconds. +* +* INPUT: +* void* pPortHndl - Ethernet Port handler. +* MV_U32 uSec - Number of micro seconds between +* RX interrupts +* +* RETURN: +* None. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +*******************************************************************************/ +MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); + MV_U32 regVal; + + regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); + regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; + regVal |= ETH_TX_INTR_COAL_MASK(coal); + + /* Set TX Coalescing mechanism */ + MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); + return coal; +} + +/******************************************************************************* +* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds +* +* DESCRIPTION: +* This routine gets the RX and TX coalescing interrupt values. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the returned numbers are in micro seconds. +* +* INPUTs: +* void* pPortHndl - Ethernet Port handler. +* +* OUTPUTs: +* MV_U32* pRxCoal - Number of micro seconds between RX interrupts +* MV_U32* pTxCoal - Number of micro seconds between TX interrupts +* +* RETURN: +* MV_STATUS MV_OK - success +* Others - failure. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +*******************************************************************************/ +MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) +{ + MV_U32 regVal, coal, usec; + + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + /* get TX Coalescing */ + regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); + coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); + + usec = (coal * 64) / (mvBoardTclkGet() / 1000000); + if(pTxCoal != NULL) + *pTxCoal = usec; + + /* Get RX Coalescing */ + regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); + coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); + +#if (MV_ETH_VERSION >= 2) + if(regVal & ETH_RX_INTR_COAL_MSB_MASK) + { + /* Add MSB */ + coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); + } +#endif /* MV_ETH_VERSION >= 2 */ + + usec = (coal * 64) / (mvBoardTclkGet() / 1000000); + if(pRxCoal != NULL) + *pRxCoal = usec; + + return MV_OK; +} + +/******************************************************************************* +* mvEthMaxRxSizeSet - +* +* DESCRIPTION: +* Change maximum receive size of the port. This configuration will take place +* after next call of ethPortSetDefaults() function. +* +* INPUT: +* +* RETURN: +*******************************************************************************/ +MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + MV_U32 portSerialCtrlReg; + + if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) + return MV_BAD_PARAM; + + pPortCtrl->portConfig.maxRxPktSize = maxRxSize; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); + portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; + portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); + + return MV_OK; +} + + +/******************************************************************************/ +/* MAC Filtering functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port +* +* DESCRIPTION: +* This routine used to free buffers attached to the Rx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* MV_BOOL isPromisc - Promiscous mode +* MV_TRUE - accept all Broadcast, Multicast +* and Unicast packets +* MV_FALSE - accept all Broadcast, +* specially added Multicast and +* single Unicast packets +* +* RETURN: MV_STATUS MV_OK - Success, Other - Failure +* +*******************************************************************************/ +MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + int queue; + MV_U32 portCfgReg; + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + /* Set / Clear UPM bit in port configuration register */ + if(isPromisc) + { + /* Accept all multicast packets to RX default queue */ + queue = pPortCtrl->portConfig.rxDefQ; + portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; + memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); + MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); + MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); + } + else + { + /* Reject all Multicast addresses */ + queue = -1; + portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; + /* Clear all mcastCount */ + memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); + } + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + /* Set Special Multicast and Other Multicast tables */ + mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); + mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); + ethSetUcastTable(pPortCtrl->portNo, queue); + + return MV_OK; +} + +/******************************************************************************* +* mvEthMacAddrSet - This function Set the port Unicast address. +* +* DESCRIPTION: +* This function Set the port Ethernet MAC address. This address +* will be used to send Pause frames if enabled. Packets with this +* address will be accepted and dispatched to default RX queue +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler. +* char* pAddr - Address to be set +* +* RETURN: MV_STATUS +* MV_OK - Success, Other - Faulure +* +*******************************************************************************/ +MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + unsigned int macH; + unsigned int macL; + + if(queue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); + return MV_BAD_PARAM; + } + + if(queue != -1) + { + macL = (pAddr[4] << 8) | (pAddr[5]); + macH = (pAddr[0] << 24)| (pAddr[1] << 16) | + (pAddr[2] << 8) | (pAddr[3] << 0); + + MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); + MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); + } + + /* Accept frames of this address */ + ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); + + return MV_OK; +} + +/******************************************************************************* +* mvEthMacAddrGet - This function returns the port Unicast address. +* +* DESCRIPTION: +* This function returns the port Ethernet MAC address. +* +* INPUT: +* int portNo - Ethernet port number. +* char* pAddr - Pointer where address will be written to +* +* RETURN: MV_STATUS +* MV_OK - Success, Other - Faulure +* +*******************************************************************************/ +MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) +{ + unsigned int macH; + unsigned int macL; + + if(pAddr == NULL) + { + mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); + return MV_BAD_PARAM; + } + + macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); + macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); + pAddr[0] = (macH >> 24) & 0xff; + pAddr[1] = (macH >> 16) & 0xff; + pAddr[2] = (macH >> 8) & 0xff; + pAddr[3] = macH & 0xff; + pAddr[4] = (macL >> 8) & 0xff; + pAddr[5] = macL & 0xff; + + return MV_OK; +} + +/******************************************************************************* +* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. +* +* DESCRIPTION: +* +* INPUT: +* MV_U8* pAddr - Address to calculate CRC-8 +* +* RETURN: MV_U8 - CRC-8 of this MAC address +* +*******************************************************************************/ +MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) +{ + unsigned int macH; + unsigned int macL; + int macArray[48]; + int crc[8]; + int i; + unsigned char crcResult = 0; + + /* Calculate CRC-8 out of the given address */ + macH = (pAddr[0] << 8) | (pAddr[1]); + macL = (pAddr[2] << 24)| (pAddr[3] << 16) | + (pAddr[4] << 8) | (pAddr[5] << 0); + + for(i=0; i<32; i++) + macArray[i] = (macL >> i) & 0x1; + + for(i=32; i<48; i++) + macArray[i] = (macH >> (i - 32)) & 0x1; + + crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ + macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ + macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ + macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ + macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; + + crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ + macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ + macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ + macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ + macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ + macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ + macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; + + crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ + macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ + macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ + macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ + macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ + macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; + + crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ + macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ + macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ + macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ + macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ + macArray[3] ^ macArray[2] ^ macArray[1]; + + crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ + macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ + macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ + macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ + macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ + macArray[3] ^ macArray[2]; + + crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ + macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ + macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ + macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ + macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ + macArray[4] ^ macArray[3]; + + crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ + macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ + macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ + macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ + macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ + macArray[4]; + + crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ + macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ + macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ + macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ + macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; + + for(i=0; i<8; i++) + crcResult = crcResult | (crc[i] << i); + + return crcResult; +} +/******************************************************************************* +* mvEthMcastAddrSet - Multicast address settings. +* +* DESCRIPTION: +* This API controls the MV device MAC multicast support. +* The MV device supports multicast using two tables: +* 1) Special Multicast Table for MAC addresses of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* In this case, the function calls ethPortSmcAddr() routine to set the +* Special Multicast Table. +* 2) Other Multicast Table for multicast of another type. A CRC-8bit +* is used as an index to the Other Multicast Table entries in the +* DA-Filter table. +* In this case, the function calculates the CRC-8bit value and calls +* ethPortOmcAddr() routine to set the Other Multicast Table. +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler. +* MV_U8* pAddr - Address to be set +* int queue - RX queue to capture all packets with this +* Multicast MAC address. +* -1 means delete this Multicast address. +* +* RETURN: MV_STATUS +* MV_TRUE - Success, Other - Failure +* +*******************************************************************************/ +MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + unsigned char crcResult = 0; + + if(queue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", + pPortCtrl->portNo, queue); + return MV_BAD_PARAM; + } + + if((pAddr[0] == 0x01) && + (pAddr[1] == 0x00) && + (pAddr[2] == 0x5E) && + (pAddr[3] == 0x00) && + (pAddr[4] == 0x00)) + { + ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); + } + else + { + crcResult = mvEthMcastCrc8Get(pAddr); + + /* Check Add counter for this CRC value */ + if(queue == -1) + { + if(pPortCtrl->mcastCount[crcResult] == 0) + { + mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", + pPortCtrl->portNo, (unsigned)crcResult); + return MV_NO_SUCH; + } + + pPortCtrl->mcastCount[crcResult]--; + if(pPortCtrl->mcastCount[crcResult] != 0) + { + mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", + pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], + (unsigned)crcResult); + return MV_NO_CHANGE; + } + } + else + { + pPortCtrl->mcastCount[crcResult]++; + if(pPortCtrl->mcastCount[crcResult] > 1) + { + mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", + pPortCtrl->portNo, (unsigned)crcResult); + return MV_NO_CHANGE; + } + } + ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); + } + return MV_OK; +} + +/******************************************************************************* +* ethSetUcastTable - Unicast address settings. +* +* DESCRIPTION: +* Set all entries in the Unicast MAC Table queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +static void ethSetUcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if(queue == -1) + { + regValue = 0; + } + else + { + regValue = (((0x01 | (queue<<1)) << 0) | + ((0x01 | (queue<<1)) << 8) | + ((0x01 | (queue<<1)) << 16) | + ((0x01 | (queue<<1)) << 24)); + } + + for (offset=0; offset<=0xC; offset+=4) + MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); +} + +/******************************************************************************* +* mvEthSetSpecialMcastTable - Special Multicast address settings. +* +* DESCRIPTION: +* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if(queue == -1) + { + regValue = 0; + } + else + { + regValue = (((0x01 | (queue<<1)) << 0) | + ((0x01 | (queue<<1)) << 8) | + ((0x01 | (queue<<1)) << 16) | + ((0x01 | (queue<<1)) << 24)); + } + + for (offset=0; offset<=0xFC; offset+=4) + { + MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + + offset), regValue); + } +} + +/******************************************************************************* +* mvEthSetOtherMcastTable - Other Multicast address settings. +* +* DESCRIPTION: +* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if(queue == -1) + { + regValue = 0; + } + else + { + regValue = (((0x01 | (queue<<1)) << 0) | + ((0x01 | (queue<<1)) << 8) | + ((0x01 | (queue<<1)) << 16) | + ((0x01 | (queue<<1)) << 24)); + } + + for (offset=0; offset<=0xFC; offset+=4) + { + MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + + offset), regValue); + } +} + +/******************************************************************************* +* ethSetUcastAddr - This function Set the port unicast address table +* +* DESCRIPTION: +* This function locates the proper entry in the Unicast table for the +* specified MAC nibble and sets its properties according to function +* parameters. +* +* INPUT: +* int ethPortNum - Port number. +* MV_U8 lastNibble - Unicast MAC Address last nibble. +* int queue - Rx queue number for this MAC address. +* value "-1" means remove address +* +* OUTPUT: +* This function add/removes MAC addresses from the port unicast address +* table. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) +{ + unsigned int unicastReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the Unicast table entry */ + lastNibble = (0xf & lastNibble); + tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ + regOffset = lastNibble % 4; /* Entry offset within the above register */ + + + unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + + tblOffset)); + + + if(queue == -1) + { + /* Clear accepts frame bit at specified unicast DA table entry */ + unicastReg &= ~(0xFF << (8*regOffset)); + } + else + { + unicastReg &= ~(0xFF << (8*regOffset)); + unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); + } + MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), + unicastReg); + + return MV_TRUE; +} + +/******************************************************************************* +* ethSetSpecialMcastAddr - Special Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device special MAC multicast support. +* The Special Multicast Table for MAC addresses supports MAC of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* This function set the Special Multicast Table appropriate entry +* according to the argument given. +* +* INPUT: +* int ethPortNum Port number. +* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). +* int queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) +{ + unsigned int smcTableReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the SMC table entry */ + tblOffset = (lastByte / 4); /* Register offset from SMC table base */ + regOffset = lastByte % 4; /* Entry offset within the above register */ + + smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); + + if(queue == -1) + { + /* Clear accepts frame bit at specified Special DA table entry */ + smcTableReg &= ~(0xFF << (8 * regOffset)); + } + else + { + smcTableReg &= ~(0xFF << (8 * regOffset)); + smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); + } + MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + + tblOffset*4), smcTableReg); + + return MV_TRUE; +} + +/******************************************************************************* +* ethSetOtherMcastAddr - Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device Other MAC multicast support. +* The Other Multicast Table is used for multicast of another type. +* A CRC-8bit is used as an index to the Other Multicast Table entries +* in the DA-Filter table. +* The function gets the CRC-8bit value from the calling routine and +* set the Other Multicast Table appropriate entry according to the +* CRC-8 argument given. +* +* INPUT: +* int ethPortNum Port number. +* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). +* int queue Rx queue number for this MAC address. +* +* OUTPUT: +* See description. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) +{ + unsigned int omcTableReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the OMC table entry */ + tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ + regOffset = crc8 % 4; /* Entry offset within the above register */ + + omcTableReg = MV_REG_READ( + (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); + + if(queue == -1) + { + /* Clear accepts frame bit at specified Other DA table entry */ + omcTableReg &= ~(0xFF << (8 * regOffset)); + } + else + { + omcTableReg &= ~(0xFF << (8 * regOffset)); + omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); + } + + MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), + omcTableReg); + + return MV_TRUE; +} + + +/******************************************************************************/ +/* MIB Counters functions */ +/******************************************************************************/ + + +/******************************************************************************* +* mvEthMibCounterRead - Read a MIB counter +* +* DESCRIPTION: +* This function reads a MIB counter of a specific ethernet port. +* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or +* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, +* so pHigh32 pointer should not be NULL in this case. +* +* INPUT: +* int ethPortNum - Ethernet Port number. +* unsigned int mibOffset - MIB counter offset. +* +* OUTPUT: +* MV_U32* pHigh32 - pointer to place where 32 most significant bits +* of the counter will be stored. +* +* RETURN: +* 32 low sgnificant bits of MIB counter value. +* +*******************************************************************************/ +MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, + MV_U32* pHigh32) +{ + int portNo; + MV_U32 valLow32, valHigh32; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + + portNo = pPortCtrl->portNo; + + valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); + + /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ + /* of a 64-bit MIB Counter. */ + if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || + (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) + { + valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); + if(pHigh32 != NULL) + *pHigh32 = valHigh32; + } + return valLow32; +} + +/******************************************************************************* +* mvEthMibCountersClear - Clear all MIB counters +* +* DESCRIPTION: +* This function clears all MIB counters +* +* INPUT: +* int ethPortNum - Ethernet Port number. +* +* +* RETURN: void +* +*******************************************************************************/ +void mvEthMibCountersClear(void* pPortHandle) +{ + int i, portNo; + unsigned int dummy; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + + portNo = pPortCtrl->portNo; + + /* Perform dummy reads from MIB counters */ + for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); + return MV_BAD_PARAM; + } + if(vlanPrio >= 8) + { + mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); + return MV_BAD_PARAM; + } + + vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); + vlanPrioReg &= ~(0x7 << (vlanPrio*3)); + vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); + MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. +* +* DESCRIPTION: +* This function defines processing of BPDU packets. +* BPDU packets can be accepted and captured to one of RX queues +* or can be processing as regular Multicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int bpduQueue - Special queue to capture BPDU packets (DA is equal to +* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, +* except for the Flow-Control Pause packets). +* Negative value (-1) means no special processing for BPDU, +* packets so they will be processed as regular Multicast packets. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + MV_U32 portCfgExtReg; + + if(bpduQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); + return MV_BAD_PARAM; + } + + portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + if(bpduQueue >= 0) + { + pPortCtrl->portConfig.rxBpduQ = bpduQueue; + + portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; + } + else + { + pPortCtrl->portConfig.rxBpduQ = -1; + /* no special processing for BPDU packets */ + portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); + } + + MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthArpRxQueue - Configure RX queue to capture ARP packets. +* +* DESCRIPTION: +* This function defines processing of ARP (type=0x0806) packets. +* ARP packets can be accepted and captured to one of RX queues +* or can be processed as other Broadcast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int arpQueue - Special queue to capture ARP packets (type=0x806). +* Negative value (-1) means discard ARP packets +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + + if(arpQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); + return MV_BAD_PARAM; + } + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if(arpQueue >= 0) + { + pPortCtrl->portConfig.rxArpQ = arpQueue; + portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); + + portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); + } + else + { + pPortCtrl->portConfig.rxArpQ = -1; + portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. +* +* DESCRIPTION: +* This function defines processing of TCP packets. +* TCP packets can be accepted and captured to one of RX queues +* or can be processed as regular Unicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int tcpQueue - Special queue to capture TCP packets. Value "-1" +* means no special processing for TCP packets, +* so they will be processed as regular +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + + if(tcpQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); + return MV_BAD_PARAM; + } + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if(tcpQueue >= 0) + { + pPortCtrl->portConfig.rxTcpQ = tcpQueue; + portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); + + portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; + } + else + { + pPortCtrl->portConfig.rxTcpQ = -1; + portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. +* +* DESCRIPTION: +* This function defines processing of UDP packets. +* TCP packets can be accepted and captured to one of RX queues +* or can be processed as regular Unicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int udpQueue - Special queue to capture UDP packets. Value "-1" +* means no special processing for UDP packets, +* so they will be processed as regular +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + + if(udpQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); + return MV_BAD_PARAM; + } + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if(udpQueue >= 0) + { + pPortCtrl->portConfig.rxUdpQ = udpQueue; + portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); + + portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; + } + else + { + pPortCtrl->portConfig.rxUdpQ = -1; + portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + + +/******************************************************************************/ +/* Speed, Duplex, FlowControl routines */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. +* +* DESCRIPTION: +* This function configure the port to work with desirable Duplex and Speed. +* Changing of these parameters are allowed only when port is disabled. +* This function disable the port if was enabled, change duplex and speed +* and, enable the port back if needed. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* ETH_PORT_SPEED speed - Speed of the port. +* ETH_PORT_SPEED duplex - Duplex of the port. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. +* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) +* is not valid +* +*******************************************************************************/ +MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, + MV_ETH_PORT_DUPLEX duplex) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 portSerialCtrlReg; + + if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + /* Check validity */ + if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) + return MV_BAD_PARAM; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + /* Set Speed */ + switch(speed) + { + case MV_ETH_SPEED_AN: + portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; + break; + + case MV_ETH_SPEED_10: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; + portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; + break; + + case MV_ETH_SPEED_100: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; + portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; + break; + + case MV_ETH_SPEED_1000: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); + return MV_BAD_VALUE; + } + /* Set duplex */ + switch(duplex) + { + case MV_ETH_DUPLEX_AN: + portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + break; + + case MV_ETH_DUPLEX_HALF: + portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; + break; + + case MV_ETH_DUPLEX_FULL: + portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); + return MV_BAD_VALUE; + } + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthFlowCtrlSet - Set Flow Control of the port. +* +* DESCRIPTION: +* This function configure the port to work with desirable Duplex and +* Speed. Changing of these parameters are allowed only when port is +* disabled. This function disable the port if was enabled, change +* duplex and speed and, enable the port back if needed. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_ETH_PORT_FC flowControl - Flow control of the port. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_VALUE - Value flowControl parameters is not valid +* +*******************************************************************************/ +MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 portSerialCtrlReg; + + if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + switch(flowControl) + { + case MV_ETH_FC_AN_ADV_DIS: + portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; + break; + + case MV_ETH_FC_AN_ADV_SYM: + portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; + break; + + case MV_ETH_FC_DISABLE: + portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; + break; + + case MV_ETH_FC_ENABLE: + portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); + return MV_BAD_VALUE; + } + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthHeaderModeSet - Set port header mode. +* +* DESCRIPTION: +* This function configures the port to work in Marvell-Header mode. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_NOT_SUPPORTED- Feature not supported. +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. +* +*******************************************************************************/ +MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 mvHeaderReg; + MV_U32 numRxQ = MV_ETH_RX_Q_NUM; + + if((port < 0) || (port >= mvCtrlEthMaxPortGet())) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); + /* Disable header mode. */ + mvHeaderReg &= ~ETH_MVHDR_EN_MASK; + + if(headerMode != MV_ETH_DISABLE_HEADER_MODE) + { + /* Enable Header mode. */ + mvHeaderReg |= ETH_MVHDR_EN_MASK; + + /* Clear DA-Prefix & MHMask fields.*/ + mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); + + if(numRxQ > 1) + { + switch (headerMode) + { + case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; + break; + case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; + break; + case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; + break; + default: + break; + } + + switch (numRxQ) + { + case (4): + mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; + break; + case (8): + mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; + break; + default: + break; + } + } + } + + MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); + + return MV_OK; +} + +#if (MV_ETH_VERSION >= 4) +/******************************************************************************* +* mvEthEjpModeSet - Enable / Disable EJP policy for TX. +* +* DESCRIPTION: +* This function +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_BOOL TRUE - enable EJP mode +* FALSE - disable EJP mode +* +* OUTPUT: MV_STATUS +* MV_OK - Success +* Other - Failure +* +* RETURN: None. +* +*******************************************************************************/ +MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + + if((port < 0) || (port >= mvCtrlEthMaxPortGet())) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + pPortCtrl->portConfig.ejpMode = mode; + if(mode) + { + /* EJP enabled - bit[18]=1, bit[19]=0 */ + pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(ETH_TX_EJP_ENABLE_MASK); + pPortCtrl->portTxQueueCmdReg &= ~MV_32BIT_LE_FAST(ETH_TX_LEGACY_WRR_MASK); + mvOsPrintf("EJP Enabled: portTxQueueCmdReg=0x%x\n", pPortCtrl->portTxQueueCmdReg); + } + else + { + /* EJP disabled - bit[18]=0, bit[19]=1 */ + pPortCtrl->portTxQueueCmdReg &= ~MV_32BIT_LE_FAST(ETH_TX_EJP_ENABLE_MASK); + pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(ETH_TX_LEGACY_WRR_MASK); + mvOsPrintf("EJP Disabled: portTxQueueCmdReg=0x%x\n", pPortCtrl->portTxQueueCmdReg); + } + + return MV_OK; +} +#endif /* MV_ETH_VERSION >= 4 */ + +/******************************************************************************* +* mvEthEjpModeSet - Enable / Disable EJP policy for TX. +* +* DESCRIPTION: +* This function +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_BOOL TRUE - enable EJP mode +* FALSE - disable EJP mode +* +* OUTPUT: MV_STATUS +* MV_OK - Success +* Other - Failure +* +* RETURN: None. +* +*******************************************************************************/ +MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + + if((port < 0) || (port >= mvCtrlEthMaxPortGet())) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + pPortCtrl->portConfig.ejpMode = mode; + if(mode) + { + /* EJP enabled - bit[18]=1, bit[19]=0 */ + pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(BIT18); + pPortCtrl->portTxQueueCmdReg &= ~MV_32BIT_LE_FAST(BIT19); + mvOsPrintf("EJP Enabled: portTxQueueCmdReg=0x%x\n", pPortCtrl->portTxQueueCmdReg); + } + else + { + /* EJP disabled - bit[18]=0, bit[19]=1 */ + pPortCtrl->portTxQueueCmdReg &= ~MV_32BIT_LE_FAST(BIT18); + pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(BIT19); + mvOsPrintf("EJP Disabled: portTxQueueCmdReg=0x%x\n", pPortCtrl->portTxQueueCmdReg); + } + + return MV_OK; +} + +/******************************************************************************* +* mvEthStatusGet - Get major properties of the port . +* +* DESCRIPTION: +* This function get major properties of the port (link, speed, duplex, +* flowControl, etc) and return them using the single structure. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* +* OUTPUT: +* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status +* will be placed. +* +* RETURN: None. +* +*******************************************************************************/ +void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + + MV_U32 regValue; + + regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); + + if(regValue & ETH_GMII_SPEED_1000_MASK) + pStatus->speed = MV_ETH_SPEED_1000; + else if(regValue & ETH_MII_SPEED_100_MASK) + pStatus->speed = MV_ETH_SPEED_100; + else + pStatus->speed = MV_ETH_SPEED_10; + + if(regValue & ETH_LINK_UP_MASK) + pStatus->isLinkUp = MV_TRUE; + else + pStatus->isLinkUp = MV_FALSE; + + if(regValue & ETH_FULL_DUPLEX_MASK) + pStatus->duplex = MV_ETH_DUPLEX_FULL; + else + pStatus->duplex = MV_ETH_DUPLEX_HALF; + + + if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) + pStatus->flowControl = MV_ETH_FC_ENABLE; + else + pStatus->flowControl = MV_ETH_FC_DISABLE; +} + + +/******************************************************************************/ +/* PHY Control Functions */ +/******************************************************************************/ + + +/******************************************************************************* +* mvEthPhyAddrSet - Set the ethernet port PHY address. +* +* DESCRIPTION: +* This routine set the ethernet port PHY address according to given +* parameter. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int phyAddr - PHY address +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + unsigned int regData; + + regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); + + regData &= ~ETH_PHY_ADDR_MASK; + regData |= phyAddr; + + MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); + + return; +} + +/******************************************************************************* +* mvEthPhyAddrGet - Get the ethernet port PHY address. +* +* DESCRIPTION: +* This routine returns the given ethernet port PHY address. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* +* +* RETURN: int - PHY address. +* +*******************************************************************************/ +int mvEthPhyAddrGet(void* pPortHandle) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + unsigned int regData; + + regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); + + return ((regData >> (5 * port)) & 0x1f); +} + +/******************************************************************************/ +/* Descriptor handling Functions */ +/******************************************************************************/ + +/******************************************************************************* +* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. +* +* DESCRIPTION: +* This function prepares a Rx chained list of descriptors and packet +* buffers in a form of a ring. The routine must be called after port +* initialization routine and before port start routine. +* The Ethernet SDMA engine uses CPU bus addresses to access the various +* devices in the system (i.e. DRAM). This function uses the ethernet +* struct 'virtual to physical' routine (set by the user) to set the ring +* with physical addresses. +* +* INPUT: +* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. +* int rxQueue Number of Rx queue. +* int rxDescNum Number of Rx descriptors +* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. +* +* OUTPUT: +* The routine updates the Ethernet port control struct with information +* regarding the Rx descriptors and buffers. +* +* RETURN: None +* +*******************************************************************************/ +static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) +{ + ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; + int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; + ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; + + /* Make sure descriptor address is cache line size aligned */ + pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + pRxDesc = (ETH_RX_DESC*)pRxDescBase; + pRxPrevDesc = pRxDesc; + + /* initialize the Rx descriptors ring */ + for (ix=0; ixbufSize = 0x0; + pRxDesc->byteCnt = 0x0; + pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pRxDesc->bufPtr = 0x0; + pRxDesc->returnInfo = 0x0; + pRxPrevDesc = pRxDesc; + if(ix == (rxDescNum-1)) + { + /* Closing Rx descriptors ring */ + pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); + } + else + { + pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); + pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); + } + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); + } + + pQueueCtrl->pCurrentDescr = pRxDescBase; + pQueueCtrl->pUsedDescr = pRxDescBase; + + pQueueCtrl->pFirstDescr = pRxDescBase; + pQueueCtrl->pLastDescr = pRxDesc; + pQueueCtrl->resource = 0; +} + +void ethResetRxDescRing(void* pPortHndl, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; + ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; + + pQueueCtrl->resource = 0; + if(pQueueCtrl->pFirstDescr != NULL) + { + while(MV_TRUE) + { + pRxDesc->bufSize = 0x0; + pRxDesc->byteCnt = 0x0; + pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pRxDesc->bufPtr = 0x0; + pRxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); + if( (void*)pRxDesc == pQueueCtrl->pLastDescr) + break; + pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); + } + pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; + pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; + + /* Update RX Command register */ + pPortCtrl->portRxQueueCmdReg |= (1 << queue); + + /* update HW */ + MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + } + else + { + /* Update RX Command register */ + pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); + + /* update HW */ + MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); + } +} + +/******************************************************************************* +* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. +* +* DESCRIPTION: +* This function prepares a Tx chained list of descriptors and packet +* buffers in a form of a ring. The routine must be called after port +* initialization routine and before port start routine. +* The Ethernet SDMA engine uses CPU bus addresses to access the various +* devices in the system (i.e. DRAM). This function uses the ethernet +* struct 'virtual to physical' routine (set by the user) to set the ring +* with physical addresses. +* +* INPUT: +* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. +* int txQueue Number of Tx queue. +* int txDescNum Number of Tx descriptors +* int txBuffSize Size of Tx buffer +* MV_U8* pTxDescBase Tx descriptors memory area base addr. +* +* OUTPUT: +* The routine updates the Ethernet port control struct with information +* regarding the Tx descriptors and buffers. +* +* RETURN: None. +* +*******************************************************************************/ +static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) +{ + ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; + int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; + ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; + + /* Make sure descriptor address is cache line size aligned */ + pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + pTxDesc = (ETH_TX_DESC*)pTxDescBase; + pTxPrevDesc = pTxDesc; + + /* initialize the Tx descriptors ring */ + for (ix=0; ixbyteCnt = 0x0000; + pTxDesc->L4iChk = 0x0000; + pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pTxDesc->bufPtr = 0x0; + pTxDesc->returnInfo = 0x0; + + pTxPrevDesc = pTxDesc; + + if(ix == (txDescNum-1)) + { + /* Closing Tx descriptors ring */ + pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); + } + else + { + pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); + pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); + } + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); + } + + pQueueCtrl->pCurrentDescr = pTxDescBase; + pQueueCtrl->pUsedDescr = pTxDescBase; + + pQueueCtrl->pFirstDescr = pTxDescBase; + pQueueCtrl->pLastDescr = pTxDesc; + /* Leave one TX descriptor out of use */ + pQueueCtrl->resource = txDescNum - 1; +} + +void ethResetTxDescRing(void* pPortHndl, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; + ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; + + pQueueCtrl->resource = 0; + if(pQueueCtrl->pFirstDescr != NULL) + { + while(MV_TRUE) + { + pTxDesc->byteCnt = 0x0000; + pTxDesc->L4iChk = 0x0000; + pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pTxDesc->bufPtr = 0x0; + pTxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); + pQueueCtrl->resource++; + if( (void*)pTxDesc == pQueueCtrl->pLastDescr) + break; + pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); + } + /* Leave one TX descriptor out of use */ + pQueueCtrl->resource--; + pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; + pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; + + /* Update TX Command register */ + pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); + /* update HW */ + MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + } + else + { + /* Update TX Command register */ + pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); + /* update HW */ + MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); + } +} + +/******************************************************************************* +* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. +* +* DESCRIPTION: +* This function allocates memory for RX and TX descriptors. +* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. +* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. +* +* INPUT: +* int size - size of memory should be allocated. +* +* RETURN: None +* +*******************************************************************************/ +static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, + MV_ULONG* pPhysAddr, MV_U32 *memHandle) +{ + MV_U8* pVirt; + +#if defined(ETH_DESCR_IN_SRAM) + if(ethDescInSram == MV_TRUE) + pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); + else +#endif /* ETH_DESCR_IN_SRAM */ + { +#ifdef ETH_DESCR_UNCACHED + pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, + pPhysAddr,memHandle); +#else + pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, + pPhysAddr, memHandle); +#endif /* ETH_DESCR_UNCACHED */ + } + memset(pVirt, 0, descSize); + + return pVirt; +} + +/******************************************************************************* +* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. +* +* DESCRIPTION: +* This function frees memory allocated for RX and TX descriptors. +* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. +* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. +* +* INPUT: +* void* pVirtAddr - virtual pointer to memory allocated for RX and TX +* desriptors. +* +* RETURN: None +* +*******************************************************************************/ +void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) +{ + if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) + return; + +#if defined(ETH_DESCR_IN_SRAM) + if( ethDescInSram ) + { + mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); + return; + } +#endif /* ETH_DESCR_IN_SRAM */ + +#ifdef ETH_DESCR_UNCACHED + mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, + pDescBuf->bufVirtPtr,pDescBuf->memHandle); +#else + mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, + pDescBuf->bufVirtPtr,pDescBuf->memHandle); +#endif /* ETH_DESCR_UNCACHED */ +} + +/******************************************************************************/ +/* Other Functions */ +/******************************************************************************/ + +void mvEthPortPowerUp(int port) +{ + MV_U32 regVal; + + if (mvBoardIsPortInSgmii(port)) + mvEthPortSgmiiConfig(port); + + /* Cancel Port Reset */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + regVal &= (~ETH_PORT_RESET_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); + while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); +} + +void mvEthPortPowerDown(int port) +{ +#if 0 + MV_U32 regVal; + + /* Port must be DISABLED */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + if( (regVal & ETH_PORT_ENABLE_MASK) != 0) + { + mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", + port, regVal); + return; + } + + /* Port Reset (Read after write the register as a precaution) */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); + while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); + + /* SERDES Reset (SERDES Config 0 Register bit0 ) */ + regVal = MV_REG_READ(ETH_SERDES_CFG_0_REG(port)); + MV_REG_WRITE(ETH_SERDES_CFG_0_REG(port), (regVal | ETH_SERDES_RST_MASK)); + /* (Wait several miliseconds as a precaution) */ + mvOsDelay(5); + + /* SERDESS Power Down (SERDES Config 0 Register bits 1-4) */ + regVal = MV_REG_READ(ETH_SERDES_CFG_0_REG(port)); + regVal &= ~(ETH_SERDES_TX_POWER_MASK | ETH_SERDES_RX_POWER_MASK | + ETH_SERDES_PLL_POWER_MASK | ETH_SERDES_IVREF_POWER_MASK); + MV_REG_WRITE(ETH_SERDES_CFG_0_REG(port), regVal); +#endif +} + +#if 0 +static void mvEthPortSgmiiConfig(int port) +{ + MV_U32 regVal; + + /* Enable working in INBAND_AUTO_NEG */ +/* if (mvCtrlModelGet() == MV_6082_DEV_ID) + { + regVal = MV_REG_READ(ETH_1MS_CLOCK_DIV_REG(port)); + regVal |= BIT31; + MV_REG_WRITE(ETH_1MS_CLOCK_DIV_REG(port), regVal); + } +*/ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + + regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); + regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); +} + +#endif /* 0 */ diff --git a/board/mv_feroceon/mv_hal/ethfp/gbe/mvEthDebug.c b/board/mv_feroceon/mv_hal/ethfp/gbe/mvEthDebug.c new file mode 100644 index 0000000..fa8165a --- /dev/null +++ b/board/mv_feroceon/mv_hal/ethfp/gbe/mvEthDebug.c @@ -0,0 +1,895 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEthDebug.c - Source file for user friendly debug functions +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvOs.h" +#include "mvCommon.h" +#include "mvTypes.h" +#include "mv802_3.h" +#include "mvDebug.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "eth-phy/mvEthPhy.h" +#include "ethfp/mvEth.h" +#include "ethfp/mvEthPolicy.h" +#include "ethfp/mvEthDebug.h" + +/* #define mvOsPrintf printf */ + +void mvEthPortShow(void* pHndl); +void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); +/******************************************************************************/ +/* Debug functions */ +/******************************************************************************/ +void ethRxCoal(int port, int usec) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthRxCoalSet(pHndl, usec); + } +} + +void ethTxCoal(int port, int usec) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthTxCoalSet(pHndl, usec); + } +} + +void ethEjpModeSet(int port, int mode) +{ +#if (MV_ETH_VERSION >= 4) + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthEjpModeSet(pHndl, mode); + } +#else + mvOsPrintf("Not supported\n"); +#endif /* (MV_ETH_VERSION >= 4) */ +} + +void ethBpduRxQ(int port, int bpduQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthBpduRxQueue(pHndl, bpduQueue); + } +} + +void ethArpRxQ(int port, int arpQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthArpRxQueue(pHndl, arpQueue); + } +} + +void ethTcpRxQ(int port, int tcpQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthTcpRxQueue(pHndl, tcpQueue); + } +} + +void ethUdpRxQ(int port, int udpQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthUdpRxQueue(pHndl, udpQueue); + } +} + +#ifdef INCLUDE_MULTI_QUEUE +void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode) +{ + void* pHndl; + + pHndl = mvEthRxPolicyHndlGet(port); + if(pHndl != NULL) + { + mvEthRxPolicyModeSet(pHndl, prioMode); + } +} + +void ethRxPolQ(int port, int queue, int quota) +{ + void* pHndl; + + pHndl = mvEthRxPolicyHndlGet(port); + if(pHndl != NULL) + { + mvEthRxPolicyQueueCfg(pHndl, queue, quota); + } +} + +void ethRxPolicy(int port) +{ + int queue; + ETH_RX_POLICY* pRxPolicy = (ETH_RX_POLICY*)mvEthRxPolicyHndlGet(port); + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); + + if( (pPortCtrl == NULL) || (pRxPolicy == NULL) ) + { + return; + } + + mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", + pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, + pPortCtrl->portConfig.rxBpduQ, + pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); + + mvOsPrintf("ethRxPolicy #%d: hndl=%p, mode=%s, curQ=%d, curQuota=%d\n", + pRxPolicy->port, pRxPolicy, + (pRxPolicy->rxPrioMode == MV_ETH_PRIO_FIXED) ? "FIXED" : "WRR", + pRxPolicy->rxCurQ, pRxPolicy->rxCurQuota); + + for(queue=0; queuerxQuota[queue]); + } +} + + +void ethTxPolDef(int port, int txQ, char* headerHexStr) +{ + void* pHndl; + MV_ETH_TX_POLICY_ENTRY polEntry; + + pHndl = mvEthTxPolicyHndlGet(port); + if(pHndl != NULL) + { + polEntry.txQ = txQ; + polEntry.pHeader = (MV_U8*)headerHexStr; + if(headerHexStr != NULL) + polEntry.headerSize = strlen(headerHexStr); + else + polEntry.headerSize = 0; + mvEthTxPolicyDef(pHndl, &polEntry); + } +} + + +#define MV_MAX_HEADER_LEN 64 +void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr) +{ + void* pHndl; + MV_ETH_TX_POLICY_MACDA daPolicy; + MV_U8 header[MV_MAX_HEADER_LEN]; + + pHndl = mvEthTxPolicyHndlGet(port); + if(pHndl == NULL) + return; + + mvMacStrToHex(macStr, daPolicy.macDa); + if(txQ > 0) + { + daPolicy.policy.txQ = txQ; + if(headerHexStr != NULL) + { + /* each two char are one byte '55'-> 0x55 */ + daPolicy.policy.headerSize = strlen(headerHexStr)/2; + if(daPolicy.policy.headerSize > MV_MAX_HEADER_LEN) + return; + + mvAsciiToHex(headerHexStr, (char*)header); + daPolicy.policy.pHeader = header; + } + else + daPolicy.policy.headerSize = 0; + + mvEthTxPolicyAdd(pHndl, &daPolicy); + } + else + { + mvEthTxPolicyDel(pHndl, daPolicy.macDa); + } +} + +void ethTxPolicy(int port) +{ + ETH_TX_POLICY* pTxPolicy = (ETH_TX_POLICY*) mvEthTxPolicyHndlGet(port); + int idx, i, queue; + char macStr[MV_MAC_STR_SIZE]; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); + + if((pPortCtrl == NULL) || (pTxPolicy == NULL)) + { + return; + } + mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", + port, pPortCtrl->portConfig.ejpMode); + + for(queue=0; queuetxQueueConfig[queue].descrNum > 0) + mvOsPrintf("%d, ", queue); + } + mvOsPrintf("\n"); + + mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); + + mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", + ETH_TX_FIXED_PRIO_CFG_REG(port), + MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); + + mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_RATE_CFG_REG(port), + MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); + + mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", + ETH_MAX_TRANSMIT_UNIT_REG(port), + MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); + + mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_BUCKET_SIZE_REG(port), + MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); + + mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_BUCKET_COUNT_REG(port), + MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); + + for(queue=0; queuetxQueueConfig[queue].prioMode == MV_ETH_PRIO_FIXED) ? "FIXED" : "WRR", + pPortCtrl->txQueueConfig[queue].quota ); + } + mvOsPrintf("\n"); + + mvOsPrintf("\nethDefTxPolicy : hndl=%p, defQ=%d, defHeader=%p, defSize=%d, maxDa=%d\n\n", + pTxPolicy, pTxPolicy->txPolDef.txQ, + pTxPolicy->txPolDef.pHeader, pTxPolicy->txPolDef.headerSize, + pTxPolicy->txPolMaxDa); + if(pTxPolicy->txPolDef.headerSize != 0) + { + for(i = 0; i < pTxPolicy->txPolDef.headerSize; i++) { + mvOsPrintf(" %02x",pTxPolicy->txPolDef.pHeader[i]); + if( (i & 0xf) == 0xf ) + mvOsPrintf("\n"); + } + mvOsPrintf("\n"); + } + + for(idx=0; idxtxPolMaxDa; idx++) + { + if(pTxPolicy->txPolDa[idx].policy.txQ == MV_INVALID) + continue; + + mvMacHexToStr(pTxPolicy->txPolDa[idx].macDa, macStr); + mvOsPrintf("%d. MAC = %s, txQ=%d, pHeader=%p, headerSize=%d\n", + idx, macStr, pTxPolicy->txPolDa[idx].policy.txQ, + pTxPolicy->txPolDa[idx].policy.pHeader, + pTxPolicy->txPolDa[idx].policy.headerSize); + if(pTxPolicy->txPolDa[idx].policy.headerSize != 0) + { + for(i = 0; i < pTxPolicy->txPolDa[idx].policy.headerSize; i++) + { + mvOsPrintf(" %02x",pTxPolicy->txPolDa[idx].policy.pHeader[i]); + if( (i & 0xf) == 0xf ) + mvOsPrintf("\n"); + } + mvOsPrintf("\n"); + } + } +} +#endif /* INCLUDE_MULTI_QUEUE */ + +/* Print important registers of Ethernet port */ +void ethPortRegs(int port) +{ + mvOsPrintf("\n\t ethGiga #%d port Registers:\n", port); + + mvOsPrintf("ETH_PORT_STATUS_REG : 0x%X = 0x%08x\n", + ETH_PORT_STATUS_REG(port), + MV_REG_READ( ETH_PORT_STATUS_REG(port) ) ); + + mvOsPrintf("ETH_PORT_SERIAL_CTRL_REG : 0x%X = 0x%08x\n", + ETH_PORT_SERIAL_CTRL_REG(port), + MV_REG_READ( ETH_PORT_SERIAL_CTRL_REG(port) ) ); + + mvOsPrintf("ETH_PORT_CONFIG_REG : 0x%X = 0x%08x\n", + ETH_PORT_CONFIG_REG(port), + MV_REG_READ( ETH_PORT_CONFIG_REG(port) ) ); + + mvOsPrintf("ETH_PORT_CONFIG_EXTEND_REG : 0x%X = 0x%08x\n", + ETH_PORT_CONFIG_EXTEND_REG(port), + MV_REG_READ( ETH_PORT_CONFIG_EXTEND_REG(port) ) ); + + mvOsPrintf("ETH_SDMA_CONFIG_REG : 0x%X = 0x%08x\n", + ETH_SDMA_CONFIG_REG(port), + MV_REG_READ( ETH_SDMA_CONFIG_REG(port) ) ); + + mvOsPrintf("ETH_TX_FIFO_URGENT_THRESH_REG : 0x%X = 0x%08x\n", + ETH_TX_FIFO_URGENT_THRESH_REG(port), + MV_REG_READ( ETH_TX_FIFO_URGENT_THRESH_REG(port) ) ); + + mvOsPrintf("ETH_RX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", + ETH_RX_QUEUE_COMMAND_REG(port), + MV_REG_READ( ETH_RX_QUEUE_COMMAND_REG(port) ) ); + + mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", + ETH_TX_QUEUE_COMMAND_REG(port), + MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); + + mvOsPrintf("ETH_INTR_CAUSE_REG : 0x%X = 0x%08x\n", + ETH_INTR_CAUSE_REG(port), + MV_REG_READ( ETH_INTR_CAUSE_REG(port) ) ); + + mvOsPrintf("ETH_INTR_EXTEND_CAUSE_REG : 0x%X = 0x%08x\n", + ETH_INTR_CAUSE_EXT_REG(port), + MV_REG_READ( ETH_INTR_CAUSE_EXT_REG(port) ) ); + + mvOsPrintf("ETH_INTR_MASK_REG : 0x%X = 0x%08x\n", + ETH_INTR_MASK_REG(port), + MV_REG_READ( ETH_INTR_MASK_REG(port) ) ); + + mvOsPrintf("ETH_INTR_EXTEND_MASK_REG : 0x%X = 0x%08x\n", + ETH_INTR_MASK_EXT_REG(port), + MV_REG_READ( ETH_INTR_MASK_EXT_REG(port) ) ); + + mvOsPrintf("ETH_RX_DESCR_STAT_CMD_REG : 0x%X = 0x%08x\n", + ETH_RX_DESCR_STAT_CMD_REG(port, 0), + MV_REG_READ( ETH_RX_DESCR_STAT_CMD_REG(port, 0) ) ); + + mvOsPrintf("ETH_RX_BYTE_COUNT_REG : 0x%X = 0x%08x\n", + ETH_RX_BYTE_COUNT_REG(port, 0), + MV_REG_READ( ETH_RX_BYTE_COUNT_REG(port, 0) ) ); + + mvOsPrintf("ETH_RX_BUF_PTR_REG : 0x%X = 0x%08x\n", + ETH_RX_BUF_PTR_REG(port, 0), + MV_REG_READ( ETH_RX_BUF_PTR_REG(port, 0) ) ); + + mvOsPrintf("ETH_RX_CUR_DESC_PTR_REG : 0x%X = 0x%08x\n", + ETH_RX_CUR_DESC_PTR_REG(port, 0), + MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, 0) ) ); +} + + +/* Print Giga Ethernet UNIT registers */ +void ethRegs(int port) +{ + mvOsPrintf("ETH_PHY_ADDR_REG : 0x%X = 0x%08x\n", + ETH_PHY_ADDR_REG(port), + MV_REG_READ(ETH_PHY_ADDR_REG(port)) ); + + mvOsPrintf("ETH_UNIT_INTR_CAUSE_REG : 0x%X = 0x%08x\n", + ETH_UNIT_INTR_CAUSE_REG(port), + MV_REG_READ( ETH_UNIT_INTR_CAUSE_REG(port)) ); + + mvOsPrintf("ETH_UNIT_INTR_MASK_REG : 0x%X = 0x%08x\n", + ETH_UNIT_INTR_MASK_REG(port), + MV_REG_READ( ETH_UNIT_INTR_MASK_REG(port)) ); + + mvOsPrintf("ETH_UNIT_ERROR_ADDR_REG : 0x%X = 0x%08x\n", + ETH_UNIT_ERROR_ADDR_REG(port), + MV_REG_READ(ETH_UNIT_ERROR_ADDR_REG(port)) ); + + mvOsPrintf("ETH_UNIT_INT_ADDR_ERROR_REG : 0x%X = 0x%08x\n", + ETH_UNIT_INT_ADDR_ERROR_REG(port), + MV_REG_READ(ETH_UNIT_INT_ADDR_ERROR_REG(port)) ); + +} + +/******************************************************************************/ +/* MIB Counters functions */ +/******************************************************************************/ + +/******************************************************************************* +* ethClearMibCounters - Clear all MIB counters +* +* DESCRIPTION: +* This function clears all MIB counters of a specific ethernet port. +* A read from the MIB counter will reset the counter. +* +* INPUT: +* int port - Ethernet Port number. +* +* RETURN: None +* +*******************************************************************************/ +void ethClearCounters(int port) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + mvEthMibCountersClear(pHndl); + + return; +} + + +/* Print counters of the Ethernet port */ +void ethPortCounters(int port) +{ + MV_U32 regValue, regValHigh; + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl == NULL) + return; + + mvOsPrintf("\n\t Port #%d MIB Counters\n\n", port); + + mvOsPrintf("GoodFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FRAMES_RECEIVED, NULL)); + mvOsPrintf("BadFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_BAD_FRAMES_RECEIVED, NULL)); + mvOsPrintf("BroadcastFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_BROADCAST_FRAMES_RECEIVED, NULL)); + mvOsPrintf("MulticastFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_MULTICAST_FRAMES_RECEIVED, NULL)); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, + ®ValHigh); + mvOsPrintf("GoodOctetsReceived = 0x%08x%08x\n", + regValHigh, regValue); + + mvOsPrintf("\n"); + mvOsPrintf("GoodFramesSent = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FRAMES_SENT, NULL)); + mvOsPrintf("BroadcastFramesSent = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_BROADCAST_FRAMES_SENT, NULL)); + mvOsPrintf("MulticastFramesSent = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_MULTICAST_FRAMES_SENT, NULL)); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_OCTETS_SENT_LOW, + ®ValHigh); + mvOsPrintf("GoodOctetsSent = 0x%08x%08x\n", regValHigh, regValue); + + + mvOsPrintf("\n\t FC Control Counters\n"); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_UNREC_MAC_CONTROL_RECEIVED, NULL); + mvOsPrintf("UnrecogMacControlReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_GOOD_FC_RECEIVED, NULL); + mvOsPrintf("GoodFCFramesReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_FC_RECEIVED, NULL); + mvOsPrintf("BadFCFramesReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_FC_SENT, NULL); + mvOsPrintf("FCFramesSent = %u\n", regValue); + + + mvOsPrintf("\n\t RX Errors\n"); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_OCTETS_RECEIVED, NULL); + mvOsPrintf("BadOctetsReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_UNDERSIZE_RECEIVED, NULL); + mvOsPrintf("UndersizeFramesReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_FRAGMENTS_RECEIVED, NULL); + mvOsPrintf("FragmentsReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_OVERSIZE_RECEIVED, NULL); + mvOsPrintf("OversizeFramesReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_JABBER_RECEIVED, NULL); + mvOsPrintf("JabbersReceived = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_MAC_RECEIVE_ERROR, NULL); + mvOsPrintf("MacReceiveErrors = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_BAD_CRC_EVENT, NULL); + mvOsPrintf("BadCrcReceived = %u\n", regValue); + + mvOsPrintf("\n\t TX Errors\n"); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR, NULL); + mvOsPrintf("TxMacErrors = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_EXCESSIVE_COLLISION, NULL); + mvOsPrintf("TxExcessiveCollisions = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_COLLISION, NULL); + mvOsPrintf("TxCollisions = %u\n", regValue); + + regValue = mvEthMibCounterRead(pHndl, ETH_MIB_LATE_COLLISION, NULL); + mvOsPrintf("TxLateCollisions = %u\n", regValue); + + + mvOsPrintf("\n"); + regValue = MV_REG_READ( ETH_RX_DISCARD_PKTS_CNTR_REG(port)); + mvOsPrintf("Rx Discard packets counter = %u\n", regValue); + + regValue = MV_REG_READ(ETH_RX_OVERRUN_PKTS_CNTR_REG(port)); + mvOsPrintf("Rx Overrun packets counter = %u\n", regValue); +} + +/* Print RMON counters of the Ethernet port */ +void ethPortRmonCounters(int port) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl == NULL) + return; + + mvOsPrintf("\n\t Port #%d RMON MIB Counters\n\n", port); + + mvOsPrintf("64 ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_64_OCTETS, NULL)); + mvOsPrintf("65...127 ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_65_TO_127_OCTETS, NULL)); + mvOsPrintf("128...255 ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_128_TO_255_OCTETS, NULL)); + mvOsPrintf("256...511 ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_256_TO_511_OCTETS, NULL)); + mvOsPrintf("512...1023 ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_512_TO_1023_OCTETS, NULL)); + mvOsPrintf("1024...Max ByteFramesReceived = %u\n", + mvEthMibCounterRead(pHndl, ETH_MIB_FRAMES_1024_TO_MAX_OCTETS, NULL)); +} + +/* Print port information */ +void ethPortStatus(int port) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthPortShow(pHndl); + } +} + +/* Print port queues information */ +void ethPortQueues(int port, int rxQueue, int txQueue, int mode) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthQueuesShow(pHndl, rxQueue, txQueue, mode); + } +} + +void ethUcastSet(int port, char* macStr, int queue) +{ + void* pHndl; + MV_U8 macAddr[MV_MAC_ADDR_SIZE]; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvMacStrToHex(macStr, macAddr); + mvEthMacAddrSet(pHndl, macAddr, queue); + } +} + + +void ethPortUcastShow(int port) +{ + MV_U32 unicastReg, macL, macH; + int i, j; + + macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(port)); + macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(port)); + + mvOsPrintf("\n\t Port #%d Unicast MAC table: %02x:%02x:%02x:%02x:%02x:%02x\n\n", + port, ((macH >> 24) & 0xff), ((macH >> 16) & 0xff), + ((macH >> 8) & 0xff), (macH & 0xff), + ((macL >> 8) & 0xff), (macL & 0xff) ); + + for (i=0; i<4; i++) + { + unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); + for(j=0; j<4; j++) + { + MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; + + mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, + (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); + } + } +} + +void ethMcastAdd(int port, char* macStr, int queue) +{ + void* pHndl; + MV_U8 macAddr[MV_MAC_ADDR_SIZE]; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvMacStrToHex(macStr, macAddr); + mvEthMcastAddrSet(pHndl, macAddr, queue); + } +} + +void ethPortMcast(int port) +{ + int tblIdx, regIdx; + MV_U32 regVal; + + mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", + port); + + for(tblIdx=0; tblIdx<(256/4); tblIdx++) + { + regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); + for(regIdx=0; regIdx<4; regIdx++) + { + if((regVal & (0x01 << (regIdx*8))) != 0) + { + mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", + tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); + } + } + } + mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); + for(tblIdx=0; tblIdx<(256/4); tblIdx++) + { + regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); + for(regIdx=0; regIdx<4; regIdx++) + { + if((regVal & (0x01 << (regIdx*8))) != 0) + { + mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", + tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); + } + } + } +} + + +/* Print status of Ethernet port */ +void mvEthPortShow(void* pHndl) +{ + MV_U32 regValue, rxCoal, txCoal; + int speed, queue, port; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; + + port = pPortCtrl->portNo; + + regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); + + mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", + port, ETH_PORT_STATUS_REG(port), regValue); + + mvOsPrintf("descInSram=%d, descSwCoher=%d\n", + ethDescInSram, ethDescSwCoher); + + if(regValue & ETH_GMII_SPEED_1000_MASK) + speed = 1000; + else if(regValue & ETH_MII_SPEED_100_MASK) + speed = 100; + else + speed = 10; + + mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); + + /* Link, Speed, Duplex, FlowControl */ + mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", + (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", + speed, + (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", + (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); + + mvOsPrintf("\n"); + + mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", + rxCoal, txCoal); + + /* Print all RX and TX queues */ + for(queue=0; queuerxQueue[queue].pFirstDescr, + mvEthRxResourceGet(pPortCtrl, queue) ); + } + mvOsPrintf("\n"); + for(queue=0; queuetxQueue[queue].pFirstDescr, + mvEthTxResourceGet(pPortCtrl, queue) ); + } +} + +/* Print RX and TX queue of the Ethernet port */ +void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; + ETH_QUEUE_CTRL *pQueueCtrl; + MV_U32 regValue; + ETH_RX_DESC *pRxDescr; + ETH_TX_DESC *pTxDescr; + int i, port = pPortCtrl->portNo; + + if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) + { + pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); + mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); + + mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", + ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), + MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); + + + if(pQueueCtrl->pFirstDescr != NULL) + { + mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", + (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, + pQueueCtrl->resource); + mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", + (MV_ULONG)pQueueCtrl->pCurrentDescr, + (MV_ULONG)pQueueCtrl->pUsedDescr); + + if(mode == 1) + { + pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; + i = 0; + do + { + mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", + i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), + pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, + (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, + ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); + + ETH_DESCR_INV(pPortCtrl, pRxDescr); + pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); + i++; + } while (pRxDescr != pQueueCtrl->pFirstDescr); + } + } + else + mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); + } + + if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) + { + pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); + mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); + + regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); + mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", + ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); + + if(pQueueCtrl->pFirstDescr != NULL) + { + mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", + (MV_ULONG)pQueueCtrl->pFirstDescr, + (MV_ULONG)pQueueCtrl->pLastDescr, + pQueueCtrl->resource); + mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", + (MV_ULONG)pQueueCtrl->pCurrentDescr, + (MV_ULONG)pQueueCtrl->pUsedDescr); + + if(mode == 1) + { + pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; + i = 0; + do + { + mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", + i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), + pTxDescr->cmdSts, pTxDescr->byteCnt, + (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, + pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); + + ETH_DESCR_INV(pPortCtrl, pTxDescr); + pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); + i++; + } while (pTxDescr != pQueueCtrl->pFirstDescr); + } + } + else + mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); + } +} diff --git a/board/mv_feroceon/mv_hal/ethfp/gbe/mvEthGbe.h b/board/mv_feroceon/mv_hal/ethfp/gbe/mvEthGbe.h new file mode 100644 index 0000000..229245f --- /dev/null +++ b/board/mv_feroceon/mv_hal/ethfp/gbe/mvEthGbe.h @@ -0,0 +1,741 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller +* +* DESCRIPTION: +* This header file contains macros typedefs and function declaration specific to +* the Marvell Gigabit Ethernet Controller. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvEthGbe_h__ +#define __mvEthGbe_h__ + +extern MV_BOOL ethDescInSram; +extern MV_BOOL ethDescSwCoher; +extern ETH_PORT_CTRL* ethPortCtrl[]; + +static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) +{ +#if defined (ETH_DESCR_IN_SRAM) + if( ethDescInSram ) + return mvSramVirtToPhy(pDesc); + else +#endif /* ETH_DESCR_IN_SRAM */ + return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); +} +/* Return port handler */ +#define mvEthPortHndlGet(port) ethPortCtrl[port] + +/* Used as WA for HW/SW race on TX */ +static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) +{ + int deep = 0; + MV_U32 txCurrReg, txEnReg; + ETH_TX_DESC* pTxLastDesc; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); + if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) + { + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; + return 0; + } + + pQueueCtrl = &pPortCtrl->txQueue[queue]; + pTxLastDesc = pQueueCtrl->pCurrentDescr; + txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); + if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) + { + /* All descriptors are processed, no chance for race */ + return 0; + } + + /* Check distance betwee HW and SW location: */ + /* If distance between HW and SW pointers is less than mvEthTxEnDeep descriptors */ + /* Race condition is possible, so wait end of TX and restart TXQ */ + while(deep < max_deep) + { + pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); + if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) + { + int count = 0; + + while( (txEnReg & MV_32BIT_LE_FAST(0x000000FF)) != 0) + { + count++; + if(count > 10000) + { + mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", + MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); + break; + } + txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); + } + + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; + return count; + } + deep++; + } + /* Distance between HW and SW pointers is more than mvEthTxEnDeep descriptors, */ + /* So NO race condition - do nothing */ + return -1; +} + + +/* defines */ +#define ETH_CSUM_MIN_BYTE_COUNT 72 + +/* Tailgate and Kirwood have only 2K TX FIFO */ +#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) +#define ETH_CSUM_MAX_BYTE_COUNT 1600 +#else +#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 +#endif /* MV_ETH_VERSION */ + +#define ETH_MV_HEADER_SIZE 2 +#define ETH_MV_TX_EN + +/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ +#define MIN_TX_BUFF_LOAD 8 +#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) + +/* Default port configuration value */ +#define PORT_CONFIG_VALUE \ + ETH_DEF_RX_QUEUE_MASK(0) | \ + ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ + ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ + ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ + ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ + ETH_RX_CHECKSUM_WITH_PSEUDO_HDR + +/* Default port extend configuration value */ +#define PORT_CONFIG_EXTEND_VALUE 0 + +#define PORT_SERIAL_CONTROL_VALUE \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE | \ + ETH_SET_FULL_DUPLEX_MASK + +#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ + ETH_FORCE_LINK_PASS_MASK | \ + ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ + ETH_SET_FULL_DUPLEX_MASK | \ + ETH_SET_MII_SPEED_100_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE + + +#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ + ETH_FORCE_LINK_PASS_MASK | \ + ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ + ETH_SET_FULL_DUPLEX_MASK | \ + ETH_SET_GMII_SPEED_1000_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE + +#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_IN_BAND_AN_EN_MASK | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE + +/* Function headers: */ +MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); +MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); +MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); +MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); +MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); +MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); +MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); +/* Interrupt Coalesting functions */ +MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); +MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); +MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); + +/******************************************************************************/ +/* Data Flow functions */ +/******************************************************************************/ +static INLINE void mvEthPortTxRestart(void* pPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; +} + +/* Get number of Free resources in specific TX queue */ +static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + return (pPortCtrl->txQueue[txQueue].resource); +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + return (pPortCtrl->rxQueue[rxQueue].resource); +} + +static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + if(pPortCtrl->txQueue[txQueue].resource == 0) + return MV_TRUE; + + return MV_FALSE; +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && + (pQueueCtrl->resource != 0) ) + return MV_TRUE; + + return MV_FALSE; +} + +static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && + (pQueueCtrl->resource != 0) ) + { + return MV_TRUE; + } + return MV_FALSE; +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + if(pPortCtrl->rxQueue[rxQueue].resource == 0) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvEthPortTx - Send an Ethernet packet +* +* DESCRIPTION: +* This routine send a given packet described by pPktInfo parameter. +* Single buffer only. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* MV_PKT_INFO *pPktInfo - User packet to send. +* +* RETURN: +* MV_NO_RESOURCE - No enough resources to send this packet. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - Packet send successfully. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) +{ + ETH_TX_DESC* pTxCurrDesc; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + int portNo; + MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; + +#ifdef ETH_DEBUG + if(pPortCtrl->portState != MV_ACTIVE) + return MV_BAD_STATE; +#endif /* ETH_DEBUG */ + + portNo = pPortCtrl->portNo; + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + /* Get the Tx Desc ring indexes */ + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + /* Check if there is enough resources to send the packet */ + if(pQueueCtrl->resource == 0) + return MV_NO_RESOURCE; + + pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; + pTxCurrDesc->byteCnt = pBufInfo->dataSize; + + /* Flash Buffer */ + if(pPktInfo->pktSize != 0) + { + ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); + pPktInfo->pktSize = 0; + } + + pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; + + /* There is only one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxCurrDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_GENERATE_CRC_MASK | + ETH_TX_ENABLE_INTERRUPT_MASK | + ETH_TX_ZERO_PADDING_MASK | + ETH_TX_FIRST_DESC_MASK | + ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + + pQueueCtrl->resource--; + pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + + /* Apply send command */ + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; + + return MV_OK; +} + + +/******************************************************************************* +* mvEthPortSgTx - Send an Ethernet packet +* +* DESCRIPTION: +* This routine send a given packet described by pBufInfo parameter. It +* supports transmitting of a packet spaned over multiple buffers. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* MV_PKT_INFO *pPktInfo - User packet to send. +* +* RETURN: +* MV_NO_RESOURCE - No enough resources to send this packet. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - Packet send successfully. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) +{ + ETH_TX_DESC* pTxFirstDesc; + ETH_TX_DESC* pTxCurrDesc; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + int portNo, bufCount; + MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; + MV_U8* pTxBuf; + +#ifdef ETH_DEBUG + if(pPortCtrl->portState != MV_ACTIVE) + return MV_BAD_STATE; +#endif /* ETH_DEBUG */ + + portNo = pPortCtrl->portNo; + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + /* Get the Tx Desc ring indexes */ + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + /* Check if there is enough resources to send the packet */ + if(pQueueCtrl->resource < pPktInfo->numFrags) + return MV_NO_RESOURCE; + + /* Remember first desc */ + pTxFirstDesc = pTxCurrDesc; + + bufCount = 0; + while(MV_TRUE) + { + if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) + { + /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ + /* to 64-bit boundary. Two options here: */ + /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ + /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ + /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ + pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; + mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); + pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); + } + else + { + pTxCurrDesc->bufPtr = mvOsIoVirtToPhy(NULL, pBufInfo[bufCount].bufVirtPtr); + /* Flash Buffer */ + ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); + } + + pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; + bufCount++; + + if(bufCount >= pPktInfo->numFrags) + break; + + if(bufCount > 1) + { + /* There is middle buffer of the packet Not First and Not Last */ + pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + } + /* Go to next descriptor and next buffer */ + pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + } + /* Set last desc with DMA ownership and interrupt enable. */ + pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; + if(bufCount == 1) + { + /* There is only one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxCurrDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_GENERATE_CRC_MASK | + ETH_TX_ENABLE_INTERRUPT_MASK | + ETH_TX_ZERO_PADDING_MASK | + ETH_TX_FIRST_DESC_MASK | + ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + } + else + { + /* Last but not First */ + pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_ENABLE_INTERRUPT_MASK | + ETH_TX_ZERO_PADDING_MASK | + ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + + /* Update First when more than one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxFirstDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_GENERATE_CRC_MASK | + ETH_TX_FIRST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); + } + /* Update txQueue state */ + pQueueCtrl->resource -= bufCount; + pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + + /* Apply send command */ + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; + + return MV_OK; +} + +/******************************************************************************* +* mvEthPortTxDone - Free all used Tx descriptors and mBlks. +* +* DESCRIPTION: +* This routine returns the transmitted packet information to the caller. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. +* +* RETURN: +* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. +* MV_EMPTY - No transmitted packets to return. TX Queue is empty. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - There is transmitted packet in the queue, +* 'pPktInfo' filled with relevant information. +* +*******************************************************************************/ +static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) +{ + ETH_TX_DESC* pTxCurrDesc; + ETH_TX_DESC* pTxUsedDesc; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + MV_PKT_INFO* pPktInfo; + MV_U32 commandStatus; + + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + pTxUsedDesc = pQueueCtrl->pUsedDescr; + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + while(MV_TRUE) + { + /* No more used descriptors */ + commandStatus = pTxUsedDesc->cmdSts; + if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) + { + ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); + return NULL; + } + if( (pTxUsedDesc == pTxCurrDesc) && + (pQueueCtrl->resource != 0) ) + { + return NULL; + } + pQueueCtrl->resource++; + pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); + if(commandStatus & (ETH_TX_LAST_DESC_MASK)) + { + pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; + pPktInfo->status = commandStatus; + return pPktInfo; + } + pTxUsedDesc = pQueueCtrl->pUsedDescr; + } +} + +/******************************************************************************* +* mvEthPortRx - Get new received packets from Rx queue. +* +* DESCRIPTION: +* This routine returns the received data to the caller. There is no +* data copying during routine operation. All information is returned +* using pointer to packet information struct passed from the caller. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_NO_RESOURCE - No free resources in RX queue. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - New packet received and 'pBufInfo' structure filled +* with relevant information. +* +*******************************************************************************/ +static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) +{ + ETH_RX_DESC *pRxCurrDesc; + MV_U32 commandStatus; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + MV_PKT_INFO* pPktInfo; + + pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); + + /* Check resources */ + if(pQueueCtrl->resource == 0) + { + mvOsPrintf("ethPortRx: no more resources\n"); + return NULL; + } + while(MV_TRUE) + { + /* Get the Rx Desc ring 'curr and 'used' indexes */ + pRxCurrDesc = pQueueCtrl->pCurrentDescr; + + commandStatus = pRxCurrDesc->cmdSts; + if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) + { + /* Nothing to receive... */ + ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); + return NULL; + } + + /* Valid RX only if FIRST and LAST bits are set */ + if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == + (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) + { + pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; + pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; + pPktInfo->status = commandStatus; + pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; + + pQueueCtrl->resource--; + /* Update 'curr' in data structure */ + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); + +#ifdef INCLUDE_SYNC_BARR + mvCpuIfSyncBarr(DRAM_TARGET); +#endif + return pPktInfo; + } + else + { + ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; + +#ifdef ETH_DEBUG + mvOsPrintf("ethDrv: Unexpected Jumbo frame: " + "status=0x%08x, byteCnt=%d, pData=0x%x\n", + commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); +#endif /* ETH_DEBUG */ + + /* move buffer from pCurrentDescr position to pUsedDescr position */ + pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; + pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; + pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; + + /* Return the descriptor to DMA ownership */ + pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | + ETH_RX_ENABLE_INTERRUPT_MASK; + + /* Flush descriptor and CPU pipe */ + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); + + /* Move the used descriptor pointer to the next descriptor */ + pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); + } + } +} + +/******************************************************************************* +* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. +* +* DESCRIPTION: +* This routine returns a Rx buffer back to the Rx ring. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_ERROR - Unexpected Fatal error. +* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be +* returned to this queue. +* MV_FULL - Buffer returned successfully and RX queue became full. +* More buffers should not be returned at the time. +* MV_OK - Buffer returned successfully and there are more free +* places in the queue. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) +{ + ETH_RX_DESC* pRxUsedDesc; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + + pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + /* Get 'used' Rx descriptor */ + pRxUsedDesc = pQueueCtrl->pUsedDescr; + + /* Check that ring is not FULL */ + if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && + (pQueueCtrl->resource != 0) ) + { + mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", + __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, + pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); + return MV_OUT_OF_RANGE; + } + + pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; + pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; + pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; + + /* Invalidate data buffer accordingly with pktSize */ + if(pPktInfo->pktSize != 0) + { + ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); + pPktInfo->pktSize = 0; + } + + /* Return the descriptor to DMA ownership */ + pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; + + /* Flush descriptor and CPU pipe */ + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); + + pQueueCtrl->resource++; + + /* Move the used descriptor pointer to the next descriptor */ + pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); + + /* If ring became Full return MV_FULL */ + if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) + return MV_FULL; + + return MV_OK; +} + + +#endif /* __mvEthGbe_h__ */ + + diff --git a/board/mv_feroceon/mv_hal/ethfp/gbe/mvEthRegs.h b/board/mv_feroceon/mv_hal/ethfp/gbe/mvEthRegs.h new file mode 100644 index 0000000..5865fa6 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ethfp/gbe/mvEthRegs.h @@ -0,0 +1,695 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvEthRegsh +#define __INCmvEthRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/****************************************/ +/* Ethernet Unit Registers */ +/****************************************/ +#define ETH_REG_BASE MV_ETH_REG_BASE + +#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) +#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) +#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) +#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) +#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) +#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) +#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) + + +#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) +#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) +#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) + +#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) +#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) +#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) +#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) +#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) +#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) +#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) +#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) +#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) +#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) +#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) +#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) + +#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) +#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) + +#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) +#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) +#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) +#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) +#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) +#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) +#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) +#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) +#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) +#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) +#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) +#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) +#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) +#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) +#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) +#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) +#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) +#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) +#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) +#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) +#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) +#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) +#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) +#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) + +#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) +#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) +#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) + +#if (MV_ETH_VERSION >= 4) +#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) +#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) +#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) +#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) +#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) +#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) +#endif /* MV_ETH_VERSION >= 4 */ + +#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) +#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) +#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) +#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) + +/* Phy address register definitions */ +#define ETH_PHY_ADDR_OFFS 0 +#define ETH_PHY_ADDR_MASK (0x1f <= 4) +#define ETH_TX_EJP_ENABLE_BIT 18 +#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) + +#define ETH_TX_LEGACY_WRR_BIT 19 +#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) +#endif /* (MV_ETH_VERSION >= 4) */ + +/***** BITs of Ethernet Port Status reg (PSR) *****/ +#define ETH_LINK_UP_BIT 1 +#define ETH_LINK_UP_MASK (1<pLastDescr) ? \ + (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ + (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) + +#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ + ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ + (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ + (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) + +#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ + ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ + (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ + (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) + +#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ + ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ + (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ + (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) + + +/* Queue specific information */ +typedef struct +{ + void* pFirstDescr; + void* pLastDescr; + void* pCurrentDescr; + void* pUsedDescr; + int resource; + MV_BUF_INFO descBuf; +} ETH_QUEUE_CTRL; + + +/* Ethernet port specific infomation */ +typedef struct _ethPortCtrl +{ + int portNo; + ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ + ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ + + MV_ETH_PORT_CFG portConfig; + MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; + MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; + + /* Register images - For DP */ + MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ + MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ + + MV_STATE portState; + + MV_U8 mcastCount[256]; + MV_U32* hashPtr; + void *osHandle; +} ETH_PORT_CTRL; + +/************** MACROs ****************/ + +/* MACROs to Flush / Invalidate TX / RX Buffers */ +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) +# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ + mvOsCacheClear(NULL, (pAddr), (size)); \ + /*CPU_PIPE_FLUSH;*/ +#else +# define ETH_PACKET_CACHE_FLUSH(pAddr, size) +#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ + +#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) +# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ + mvOsCacheInvalidate (NULL, (pAddr), (size)); \ + /*CPU_PIPE_FLUSH;*/ +#else +# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) +#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ + +#ifdef ETH_DESCR_UNCACHED + +#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) +#define ETH_DESCR_INV(pPortCtrl, pDescr) + +#else + +#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ + mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) + +#define ETH_DESCR_INV(pPortCtrl, pDescr) \ + mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) + +#endif /* ETH_DESCR_UNCACHED */ + +#include "ethfp/gbe/mvEthGbe.h" + +#endif /* __mvEth_h__ */ + + diff --git a/board/mv_feroceon/mv_hal/ethfp/mvEthDebug.h b/board/mv_feroceon/mv_hal/ethfp/mvEthDebug.h new file mode 100644 index 0000000..f7b1ba1 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ethfp/mvEthDebug.h @@ -0,0 +1,113 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __MV_ETH_DEBUG_H__ +#define __MV_ETH_DEBUG_H__ + +/* + ** Externs + */ +void ethBpduRxQ(int port, int bpduQueue); +void ethArpRxQ(int port, int bpduQueue); +void ethTcpRxQ(int port, int bpduQueue); +void ethUdpRxQ(int port, int bpduQueue); +void ethMcastAdd(int port, char* macStr, int queue); + +#ifdef INCLUDE_MULTI_QUEUE +void ethRxPolicy( int port); +void ethTxPolicy( int port); +void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); +void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); +void ethRxPolQ(int port, int rxQueue, int rxQuota); +#endif /* INCLUDE_MULTI_QUEUE */ + +void print_egiga_stat(void *sc, unsigned int port); +void ethPortStatus (int port); +void ethPortQueues( int port, int rxQueue, int txQueue, int mode); +void ethPortMcast(int port); +void ethPortRegs(int port); +void ethPortCounters(int port); +void ethPortRmonCounters(int port); +void ethRxCoal(int port, int usec); +void ethTxCoal(int port, int usec); + +void ethRegs(int port); +void ethClearCounters(int port); +void ethUcastSet(int port, char* macStr, int queue); +void ethPortUcastShow(int port); + +#ifdef CONFIG_MV_ETH_HEADER +void run_com_header(const char *buffer); +#endif + +#ifdef INCLUDE_MULTI_QUEUE +void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); +void ethRxPolQ(int port, int queue, int quota); +void ethRxPolicy(int port); +void ethTxPolDef(int port, int txQ, char* headerHexStr); +void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); +void ethTxPolicy(int port); +#endif /* INCLUDE_MULTI_QUEUE */ + + +#endif diff --git a/board/mv_feroceon/mv_hal/ethfp/mvEthPolicy.c b/board/mv_feroceon/mv_hal/ethfp/mvEthPolicy.c new file mode 100644 index 0000000..18fa1ff --- /dev/null +++ b/board/mv_feroceon/mv_hal/ethfp/mvEthPolicy.c @@ -0,0 +1,572 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEthPolicy.c - Source file for RX and TX policy of Giga Ethernet driver +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + + +#include "mvEthPolicy.h" + +/*****************************************************************************/ +/**************************** RX Policy **************************************/ +/*****************************************************************************/ + +ETH_RX_POLICY* rxPolicy[MV_ETH_MAX_PORTS]; + + +/******************************************************************************* +* mvEthRxPolicyInit - Initialize RX policy component. +* +* DESCRIPTION: +* Create RX policy database for ethernet port, set to it to default +* (FIXED mode) and return port handle. +* +* INPUT: +* int port - Ethernet port number +* +* +* RETURN: +* void* pRxPolicyHndl - RX Policy component handler; +* +*******************************************************************************/ +void* mvEthRxPolicyInit(int port, int defQuota, MV_ETH_PRIO_MODE defMode) +{ + int queue; + + if( (port < 0) || (port >= mvCtrlEthMaxPortGet()) ) + { + mvOsPrintf("ethRxPolicy: port #%d is not exist\n", port); + return NULL; + } + rxPolicy[port] = mvOsMalloc(sizeof(ETH_RX_POLICY)); + if(rxPolicy[port] == NULL) + { + mvOsPrintf("ethRxPolicy: Port #%d, Can't allocate %lu bytes\n", + port, sizeof(ETH_RX_POLICY)); + return NULL; + } + /* Set defaults */ + memset(rxPolicy[port], 0, sizeof(ETH_RX_POLICY)); + + for(queue=0; queuerxQuota[queue] = defQuota; + } + rxPolicy[port]->port = port; + rxPolicy[port]->rxPrioMode = defMode; + rxPolicy[port]->rxCurQ = MV_ETH_RX_Q_NUM-1; + rxPolicy[port]->rxCurQuota = rxPolicy[port]->rxQuota[rxPolicy[port]->rxCurQ]; + + return rxPolicy[port]; +} + +/* Get RX policy handler for specific port */ +void* mvEthRxPolicyHndlGet(int port) +{ + return rxPolicy[port]; +} + +/******************************************************************************* +* mvEthRxPolicyModeSet - Set receive priority policy. +* +* DESCRIPTION: +* This function configures priority mode for processing received packets. +* +* INPUT: +* void* pRxPolHndl - RX Policy component handler +* MV_ETH_PRIO_MODE prioMode - RX priority mode (FIXED or WRR) +* +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthRxPolicyModeSet(void* pRxPolHndl, MV_ETH_PRIO_MODE prioMode) +{ + ETH_RX_POLICY* pRxPolicy = (ETH_RX_POLICY*)pRxPolHndl; + + pRxPolicy->rxPrioMode = prioMode; + + return MV_OK; +} + +/******************************************************************************* +* mvEthRxPolicyQueueCfg - Set quota for RX queue in WRR receive priority mode. +* +* DESCRIPTION: +* This function configures packet based quota for each RX queue, +* when WRR priority mode is chosen for processing received packets. +* +* INPUT: +* void* pRxPolHndl - RX Policy component handler +* int rxQueue - RX priority mode (FIXED or WRR) +* int rxQuota - packet based quota for RX queue (only in WRR mode) +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthRxPolicyQueueCfg(void* pRxPolHndl, int rxQueue, int rxQuota) +{ + ETH_RX_POLICY* pRxPolicy = (ETH_RX_POLICY*)pRxPolHndl; + + pRxPolicy->rxQuota[rxQueue] = rxQuota; + + return MV_OK; +} + +/******************************************************************************* +* mvEthRxPolicyGet - Get RX policy of ethernet port. +* +* DESCRIPTION: +* This function choose which RX queue will be processed next +* +* INPUT: +* void* pRxPolHndl - RX Policy component handler +* MV_U32 cause - value of cause register, indicating +* which RX queues received packets. +* +* RETURN: +* int rxQueue - The RX queue number that will be processed next. +* -1 means error +* +*******************************************************************************/ +int mvEthRxPolicyGet(void* pRxPolHndl, MV_U32 cause) +{ + int queue; + ETH_RX_POLICY* pRxPolicy = (ETH_RX_POLICY*)pRxPolHndl; + +#ifdef MV_RT_DEBUG + if(cause == 0) + { + mvOsPrintf("EthRxPolicy: port #%d, unexpected cause=0x%x\n", pRxPolicy->port, cause); + return MV_INVALID; + } +#endif /* MV_RT_DEBUG */ + + if(pRxPolicy->rxPrioMode == MV_ETH_PRIO_FIXED) + { + for(queue=(MV_ETH_RX_Q_NUM-1); queue>=0; queue--) + { + if(cause & (ETH_CAUSE_RX_READY_MASK(queue))) + return queue; + } + } + else + { + /* Check Current RX queue */ + if(cause & ETH_CAUSE_RX_READY_MASK(pRxPolicy->rxCurQ)) + { + if(pRxPolicy->rxCurQuota > 0) + { + pRxPolicy->rxCurQuota -= 1; + return pRxPolicy->rxCurQ; + } + } + /* Look for next RX Queue */ + while(MV_TRUE) + { + if(pRxPolicy->rxCurQ == 0) + pRxPolicy->rxCurQ = MV_ETH_RX_Q_NUM-1; + else + pRxPolicy->rxCurQ -= 1; + + if( ((cause & ETH_CAUSE_RX_READY_MASK(pRxPolicy->rxCurQ)) != 0) && + (pRxPolicy->rxQuota[pRxPolicy->rxCurQ] != 0) ) + { + pRxPolicy->rxCurQuota = pRxPolicy->rxQuota[pRxPolicy->rxCurQ]-1; + return pRxPolicy->rxCurQ; + } + } + } + return MV_INVALID; +} + +/*****************************************************************************/ +/**************************** TX Policy **************************************/ +/*****************************************************************************/ + + +ETH_TX_POLICY* txPolicy[MV_ETH_MAX_PORTS]; + +/******************************************************************************* +* mvEthTxPolicyInit - Initialize TX policy component. +* +* DESCRIPTION: +* Create TX policy database for ethernet port, set to it to default +* values and return port handle. +* +* INPUT: +* int port - Ethernet port number +* +* +* RETURN: +* void* pTxPolHndl - TX Policy component handler +* +*******************************************************************************/ +void* mvEthTxPolicyInit(int port, MV_ETH_TX_POLICY_ENTRY* pDefPolicy) +{ + int daIdx; + + if( (port < 0) || (port >= mvCtrlEthMaxPortGet()) ) + { + mvOsPrintf("ethTxPolicy: port #%d is not exist\n", port); + return NULL; + } + txPolicy[port] = mvOsMalloc(sizeof(ETH_TX_POLICY)); + if(txPolicy[port] == NULL) + { + mvOsPrintf("ethTxPolicy: Port #%d, Can't allocate %lu bytes\n", + port, sizeof(ETH_TX_POLICY)); + return NULL; + } + /* Set defaults */ + memset(txPolicy[port], 0, sizeof(ETH_TX_POLICY)); + txPolicy[port]->port = port; + mvEthTxPolicyDef(txPolicy[port],pDefPolicy); + + /* Invalidate all entries */ + txPolicy[port]->txPolMaxDa = 0; + for(daIdx=0; daIdxtxPolDa[daIdx].policy.txQ = MV_INVALID; + + return txPolicy[port]; +} + +/* Get TX policy handler for specific port */ +void* mvEthTxPolicyHndlGet(int port) +{ + return txPolicy[port]; +} + + +/******************************************************************************* +* mvEthTxPolicyDef - Set TX default policy. +* +* DESCRIPTION: +* This function configures TX default policy for packets that +* there is no information for them +* +* INPUT: +* void* pTxPolHndl - TX Policy component handler +* MV_ETH_TX_POLICY_ENTRY policy - Default TX policy +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthTxPolicyDef(void* pTxPolHndl, MV_ETH_TX_POLICY_ENTRY* pPolicy) +{ + ETH_TX_POLICY* pTxPolicy = (ETH_TX_POLICY*)pTxPolHndl; + + /* if Tx header exist */ + if(pPolicy->pHeader != NULL) + { + /* allocate memory for header */ + pTxPolicy->txPolDef.pHeader = mvOsMalloc(pPolicy->headerSize ); + if(pTxPolicy->txPolDef.pHeader == NULL) + { + mvOsPrintf("mvEthTxPolicyDef: Alloc failed \n"); + return MV_FAIL; + } + /* copy header */ + memcpy(pTxPolicy->txPolDef.pHeader, pPolicy->pHeader , pPolicy->headerSize ); + pTxPolicy->txPolDef.headerSize = pPolicy->headerSize; + } + else + { + pTxPolicy->txPolDef.pHeader = NULL; + pTxPolicy->txPolDef.headerSize = 0; + } + pTxPolicy->txPolDef.txQ = pPolicy->txQ; + + return MV_OK; +} + +/******************************************************************************* +* mvEthTxPolicyAdd - Add TX policy for packets with special MAC DA. +* +* DESCRIPTION: +* This function adds TX policy for outgoing packets with special MAC DAs. +* Support up to 16 entries. +* +* INPUT: +* void* pTxPolHndl - TX Policy component handler +* MV_ETH_TX_POLICY_MACDA daPolicy - TX policy for outgoing packets +* with specific MACDA +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthTxPolicyAdd(void* pTxPolHndl, MV_ETH_TX_POLICY_MACDA* pDaPolicy) +{ + int idx, firstEmptyIdx = MV_INVALID; + ETH_TX_POLICY* pTxPolicy = (ETH_TX_POLICY*)pTxPolHndl; + + for(idx=0; idxtxPolDa[idx].policy.txQ != MV_INVALID) && + ( memcmp(pTxPolicy->txPolDa[idx].macDa, pDaPolicy->macDa, + MV_MAC_ADDR_SIZE) == 0) ) + { + /* entry already exist - so replace */ + firstEmptyIdx = idx; + break; + } + if( (firstEmptyIdx == MV_INVALID) && + (pTxPolicy->txPolDa[idx].policy.txQ == MV_INVALID) ) + { + firstEmptyIdx = idx; + } + } + if(firstEmptyIdx != MV_INVALID) + { + memcpy(pTxPolicy->txPolDa[firstEmptyIdx].macDa, + pDaPolicy->macDa, MV_MAC_ADDR_SIZE); + + /* if Tx header exist */ + if(pDaPolicy->policy.pHeader != NULL) + { + /* allocate memory for header */ + pTxPolicy->txPolDa[firstEmptyIdx].policy.pHeader = mvOsMalloc(pDaPolicy->policy.headerSize ); + if(pTxPolicy->txPolDa[firstEmptyIdx].policy.pHeader == NULL) + { + mvOsPrintf("ethTxPolicy: Alloc failed \n"); + return MV_FAIL; + } + /* copy header */ + memcpy(pTxPolicy->txPolDa[firstEmptyIdx].policy.pHeader , + pDaPolicy->policy.pHeader , pDaPolicy->policy.headerSize ); + pTxPolicy->txPolDa[firstEmptyIdx].policy.headerSize = pDaPolicy->policy.headerSize; + } + else + { + pTxPolicy->txPolDa[firstEmptyIdx].policy.pHeader = NULL; + pTxPolicy->txPolDa[firstEmptyIdx].policy.headerSize = 0; + } + pTxPolicy->txPolDa[firstEmptyIdx].policy.txQ = pDaPolicy->policy.txQ; + if(firstEmptyIdx >= pTxPolicy->txPolMaxDa) + pTxPolicy->txPolMaxDa = firstEmptyIdx + 1; + + return MV_OK; + } + mvOsPrintf("ethTxPolicy: Can't add more MACDA entries\n"); + return MV_FULL; +} + +/******************************************************************************* +* mvEthTxPolicyDel - Delete TX policy for packets with special MACDA. +* +* DESCRIPTION: +* This function deletes existing TX policy for outgoing packets with +* special MAC DAs.. +* +* INPUT: +* void* pTxPolHndl - TX Policy component handler +* MV_U8* pMacAddr - Pointer to MACDA for the entry will be deleted. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthTxPolicyDel(void* pTxPolHndl, MV_U8* pMacAddr) +{ + int idx; + ETH_TX_POLICY* pTxPolicy = (ETH_TX_POLICY*)pTxPolHndl; + + for(idx=0; idxtxPolMaxDa; idx++) + { + if( (pTxPolicy->txPolDa[idx].policy.txQ != MV_INVALID) && + (memcmp(pTxPolicy->txPolDa[idx].macDa, pMacAddr, + MV_MAC_ADDR_SIZE) == 0) ) + { + /* Entry found */ + pTxPolicy->txPolDa[idx].policy.txQ = MV_INVALID; + if(pTxPolicy->txPolDa[idx].policy.pHeader != NULL) + { + mvOsFree(pTxPolicy->txPolDa[idx].policy.pHeader); + pTxPolicy->txPolDa[idx].policy.pHeader = NULL; + pTxPolicy->txPolDa[idx].policy.headerSize = 0; + } + + if(idx == (pTxPolicy->txPolMaxDa - 1)) + pTxPolicy->txPolMaxDa--; + + /* Decrease table */ + while( (pTxPolicy->txPolMaxDa > 0) && + (pTxPolicy->txPolDa[pTxPolicy->txPolMaxDa-1].policy.txQ == MV_INVALID) ) + pTxPolicy->txPolMaxDa--; + + return MV_OK; + } + } + mvOsPrintf("ethTxPolicy: Can't delete the MACDA entry\n"); + return MV_NO_SUCH; +} + + + +/******************************************************************************* +* mvEthDATxPolicyGet - Get TX policy of ethernet port for the outgoing packet, +* base on the DA. +* +* DESCRIPTION: +* This function return an existing TX policy for specific MACs. +* +* INPUT: +* void* pPortHndl - Pointer to port specific handler +* MV_U8* MAC - Pointer to DA MAC. +* +* OUTPUT: +* MV_ETH_TX_POLICY_ENTRY* pTxPolEntry - pointer to TX policy entry for +* this packet +* +* RETURN: +* int txQ - TX queue to place the outgoing packet. +* +*******************************************************************************/ +static int mvEthDATxPolicyGet(void* pTxPolicyHndl, MV_U8* pDA, + MV_ETH_TX_POLICY_ENTRY* pTxPolicyEntry) +{ + int idx=0; + ETH_TX_POLICY* pTxPolicy = (ETH_TX_POLICY*)pTxPolicyHndl; + MV_ETH_TX_POLICY_ENTRY* pPolicy = &pTxPolicy->txPolDef; + + while(idx < pTxPolicy->txPolMaxDa) + { + if( (pTxPolicy->txPolDa[idx].policy.txQ != MV_INVALID) && + (memcmp(pDA, pTxPolicy->txPolDa[idx].macDa, + MV_MAC_ADDR_SIZE) == 0) ) + { + pPolicy = &pTxPolicy->txPolDa[idx].policy; + break; + } + idx++; + } + + /* if valid entry found */ + if(idx < pTxPolicy->txPolMaxDa) + { + if(pTxPolicyEntry != NULL) + { + pTxPolicyEntry->pHeader = pPolicy->pHeader; + pTxPolicyEntry->headerSize = pPolicy->headerSize; + pTxPolicyEntry->txQ = pPolicy->txQ; + } + return pPolicy->txQ; + } + else /* if no entry found - use defaults*/ + { + if(pTxPolicyEntry != NULL) + { + pTxPolicyEntry->pHeader = pTxPolicy->txPolDef.pHeader; + pTxPolicyEntry->headerSize = pTxPolicy->txPolDef.headerSize; + pTxPolicyEntry->txQ = pTxPolicy->txPolDef.txQ; + } + return pTxPolicy->txPolDef.txQ; + } + + return 0; +} + +/******************************************************************************* +* mvEthTxPolicyGet - Get TX policy of ethernet port for the outgoing packet. +* +* DESCRIPTION: +* This function gets existing TX policy for outgoing packets. +* +* INPUT: +* void* pPortHndl - Pointer to port specific handler +* MV_U8* pPktInfo - Pointer to outgoing packet +* +* OUTPUT: +* MV_ETH_TX_POLICY_ENTRY* pTxPolEntry - pointer to TX policy entry for +* this packet +* +* RETURN: +* int txQ - TX queue to place the outgoing packet. +* +*******************************************************************************/ +int mvEthTxPolicyGet(void* pTxPolicyHndl, MV_U8* pData, + MV_ETH_TX_POLICY_ENTRY* pTxPolicyEntry) +{ + /* extract the destination MAC address */ + return mvEthDATxPolicyGet(pTxPolicyHndl, pData, pTxPolicyEntry); +} + + + diff --git a/board/mv_feroceon/mv_hal/ethfp/mvEthPolicy.h b/board/mv_feroceon/mv_hal/ethfp/mvEthPolicy.h new file mode 100644 index 0000000..e1e2c41 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ethfp/mvEthPolicy.h @@ -0,0 +1,139 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEthPolicy.h - Header File for RX and TX policy of Giga Ethernet driver +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvEthPolicy_h__ +#define __mvEthPolicy_h__ + +#include "mvOs.h" +#include "mvEth.h" + +#define MV_ETH_TX_POLICY_MAX_MACDA 16 + +typedef struct +{ + MV_U8* pHeader; + int headerSize; + int txQ; + +} MV_ETH_TX_POLICY_ENTRY; + +typedef struct +{ + MV_U8 macDa[MV_MAC_ADDR_SIZE]; + MV_ETH_TX_POLICY_ENTRY policy; +}MV_ETH_TX_POLICY_MACDA; + +/* Rx policy struct */ +typedef struct +{ + int port; + MV_ETH_PRIO_MODE rxPrioMode; + int rxQuota[MV_ETH_RX_Q_NUM]; + int rxCurQ; + int rxCurQuota; +}ETH_RX_POLICY; + +/* Tx policy struct */ +typedef struct +{ + int port; + MV_ETH_TX_POLICY_ENTRY txPolDef; + int txPolMaxDa; + MV_ETH_TX_POLICY_MACDA txPolDa[MV_ETH_TX_POLICY_MAX_MACDA]; +}ETH_TX_POLICY; + +/* RX Policy */ +void* mvEthRxPolicyInit(int port, int defQuota, MV_ETH_PRIO_MODE defMode); +void* mvEthRxPolicyHndlGet(int port); + +MV_STATUS mvEthRxPolicyModeSet(void* pPortHndl, MV_ETH_PRIO_MODE prioMode); +MV_STATUS mvEthRxPolicyQueueCfg(void* pPortHndl, int rxQueue, int rxQuota); +int mvEthRxPolicyGet(void* pPolicyHndl, MV_U32 cause); +void mvEthRxPolicyShow(void* pPolicyHndl); + +/* TX Policy */ +void* mvEthTxPolicyInit(int port, MV_ETH_TX_POLICY_ENTRY* pDefPolicy); +void* mvEthTxPolicyHndlGet(int port); + +MV_STATUS mvEthTxPolicyDef(void* pTxPolHndl, MV_ETH_TX_POLICY_ENTRY* pPolicy); +MV_STATUS mvEthTxPolicyAdd(void* pTxPolHndl, MV_ETH_TX_POLICY_MACDA* pDaPolicy); +MV_STATUS mvEthTxPolicyDel(void* pTxPolHndl, MV_U8* pMacAddr); + +int mvEthTxPolicyGet(void* pTxPolicyHndl, MV_U8* pData, + MV_ETH_TX_POLICY_ENTRY* pTxPolicyEntry); + +void mvEthTxPolicyShow(void* pPolicyHndl); + +#endif /* __mvEthPolicy_h__ */ + diff --git a/board/mv_feroceon/mv_hal/gpp/mvCompVer.txt b/board/mv_feroceon/mv_hal/gpp/mvCompVer.txt new file mode 100644 index 0000000..c6e1229 --- /dev/null +++ b/board/mv_feroceon/mv_hal/gpp/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_2 +Unit HAL Version: 3.1.0 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/gpp/mvGpp.c b/board/mv_feroceon/mv_hal/gpp/mvGpp.c new file mode 100644 index 0000000..d69c9c6 --- /dev/null +++ b/board/mv_feroceon/mv_hal/gpp/mvGpp.c @@ -0,0 +1,550 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "gpp/mvGpp.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); + +/******************************************************************************* +* mvGppTypeSet - Enable a GPP (OUT) pin +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the type +* of corresponding GPP will be set. Other GPPs are ignored. +* value - 32bit value that describes GPP type per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 to input and GPP15 to output. +* mvGppTypeSet(0, (GPP8 | GPP15), +* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) +{ + if (group >= MV_GPP_MAX_GROUP) + { + DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); + return MV_BAD_PARAM; + } + + gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); + + /* Workaround for Erratum FE-MISC-70*/ + if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) + { + mask &= 0x2; + gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); + } /*End of WA*/ + + return MV_OK; + +} + +/******************************************************************************* +* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the type +* of corresponding GPP will be set. Other GPPs are ignored. +* value - 32bit value that describes GPP blink per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 to be static and GPP15 to be blinking. +* mvGppBlinkEn(0, (GPP8 | GPP15), +* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) +{ + if (group >= MV_GPP_MAX_GROUP) + { + DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); + return MV_BAD_PARAM; + } + + gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); + + return MV_OK; + +} +/******************************************************************************* +* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the type +* of corresponding GPP will be set. Other GPPs are ignored. +* value - 32bit value that describes GPP polarity per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 to the actual pin value and GPP15 to be inverted. +* mvGppPolaritySet(0, (GPP8 | GPP15), +* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) +{ + if (group >= MV_GPP_MAX_GROUP) + { + DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); + return MV_BAD_PARAM; + } + + gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); + + return MV_OK; + +} + +/******************************************************************************* +* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* returned value is valid for it. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Get GPP8 and GPP15 value. +* mvGppPolarityGet(0, (GPP8 | GPP15)); +* +* RETURN: +* 32bit value that describes GPP polatity mode per pin. +* +*******************************************************************************/ +MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) +{ + MV_U32 regVal; + + if (group >= MV_GPP_MAX_GROUP) + { + DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); + return MV_ERROR; + } + regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); + + return (regVal & mask); +} + +/******************************************************************************* +* mvGppValueGet - Get a GPP Pin list value. +* +* DESCRIPTION: +* This function get GPP value. +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* returned value is valid for it. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Get GPP8 and GPP15 value. +* mvGppValueGet(0, (GPP8 | GPP15)); +* +* RETURN: +* 32bit value that describes GPP activity mode per pin. +* +*******************************************************************************/ +MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) +{ + MV_U32 gppData; + + gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); + + gppData &= mask; + + return gppData; + +} + +/******************************************************************************* +* mvGppValueSet - Set a GPP Pin list value. +* +* DESCRIPTION: +* This function set value for given GPP pin list. +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* value of corresponding GPP will be set accordingly. Other GPP +* are not affected. +* value - 32bit value that describes GPP value per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 value of '0' and GPP15 value of '1'. +* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) +{ + MV_U32 outEnable, tmp; + MV_U32 i; + + if (group >= MV_GPP_MAX_GROUP) + { + DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); + return MV_BAD_PARAM; + } + + /* verify that the gpp pin is configured as output */ + /* Note that in the register out enabled -> bit = '0'. */ + outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); + + /* Workaround for Erratum FE-MISC-70*/ + if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) + { + tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); + outEnable &= 0xfffffffd; + outEnable |= (tmp & 0x2); + } /*End of WA*/ + + for (i = 0 ; i < 32 ;i++) + { + if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) + { + mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ + "value to GPP %d in input mode.\n", i); + return MV_ERROR; + } + } + + gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); + + return MV_OK; + +} +/******************************************************************************* +* gppRegSet - Set a specific GPP pin on a specific GPP register +* +* DESCRIPTION: +* This function set a specific GPP pin on a specific GPP register +* +* INPUT: +* regOffs - GPP Register offset +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* value of corresponding GPP will be set accordingly. Other GPP +* are not affected. +* value - 32bit value that describes GPP value per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 value of '0' and GPP15 value of '1'. +* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) +{ + MV_U32 gppData; + + gppData = MV_REG_READ(regOffs); + + gppData &= ~mask; + + gppData |= (value & mask); + + MV_REG_WRITE(regOffs, gppData); +} + + +#if defined(CONFIG_BUFFALO_PLATFORM) +#define BIT(x) (1<<(x)) + +MV_BOOL bfGppInRegBitTest(MV_32 bit) +{ + if (bit < 0) + return MV_FALSE; + + if (bit < 32) + return mvGppValueGet(0, BIT(bit)) ? MV_TRUE : MV_FALSE; + else + return mvGppValueGet(1, BIT(bit - 32)) ? MV_TRUE : MV_FALSE; +} + +MV_BOOL bfGppOutRegBitTest(MV_32 bit) +{ + if (bit < 0) + return MV_FALSE; + + if (bit < 32) + return MV_REG_READ(GPP_DATA_OUT_REG(0)) & BIT(bit) ? MV_TRUE : MV_FALSE; + else + return MV_REG_READ(GPP_DATA_OUT_REG(1)) & BIT(bit - 32) ? MV_TRUE : MV_FALSE; +} + +MV_VOID bfGppOutRegBitSet(MV_32 bit) +{ + if (bit < 0) + return; + + if (bit < 32) + mvGppValueSet(0, BIT(bit), 0xffffffff); + else + mvGppValueSet(1, BIT(bit - 32), 0xffffffff); +} + +MV_VOID bfGppOutRegBitClr(MV_32 bit) +{ + if (bit < 0) + return; + + if (bit < 32) + mvGppValueSet(0, BIT(bit), 0x0); + else + mvGppValueSet(1, BIT(bit - 32), 0x0); +} + +MV_VOID bfGppOutRegBitInv(MV_32 bit) +{ + if (bit < 0) + return; + + if (bit < 32) + MV_REG_READ(GPP_BLINK_EN_REG(0)) & BIT(bit) ? MV_TRUE : MV_FALSE; + else + MV_REG_READ(GPP_BLINK_EN_REG(1)) & BIT(bit - 32) ? MV_TRUE : MV_FALSE; +} + +MV_BOOL bfGppBlinkRegBitTest(MV_32 bit) +{ + if (bit < 0) + return MV_FALSE; + + if (bit < 32) + return MV_REG_READ(GPP_BLINK_EN_REG(0)) & BIT(bit) ? MV_TRUE : MV_FALSE; + else + return MV_REG_READ(GPP_BLINK_EN_REG(1)) & BIT(bit - 32) ? MV_TRUE : MV_FALSE; +} + +MV_VOID bfGppBlinkRegBitSet(MV_32 bit) +{ + if (bit < 0) + return; + + if (bit < 32) + mvGppBlinkEn(0, BIT(bit), 0xffffffff); + else + mvGppBlinkEn(1, BIT(bit - 32), 0xffffffff); +} + +MV_VOID bfGppBlinkRegBitClr(MV_32 bit) +{ + if (bit < 0) + return; + + if (bit < 32) + mvGppBlinkEn(0, BIT(bit), 0x0); + else + mvGppBlinkEn(1, BIT(bit - 32), 0x0); +} + +MV_BOOL bfGppOutEnableRegBitTest(MV_32 bit) +{ + if (bit < 0) + return MV_FALSE; + + if (bit < 32) + return MV_REG_READ(GPP_DATA_OUT_EN_REG(0)) & BIT(bit) ? MV_TRUE : MV_FALSE; + else + return MV_REG_READ(GPP_DATA_OUT_EN_REG(1)) & BIT(bit - 32) ? MV_TRUE : MV_FALSE; +} + +MV_VOID bfGppOutEnableRegBitSet(MV_32 bit) +{ + if (bit < 0) + return; + + if (bit < 32) + mvGppTypeSet(0, BIT(bit), 0xffffffff); + else + mvGppTypeSet(1, BIT(bit - 32), 0xffffffff); +} + +MV_VOID bfGppOutEnableRegBitClr(MV_32 bit) +{ + if (bit < 0) + return; + + if (bit < 32) + mvGppTypeSet(0, BIT(bit), 0x0); + else + mvGppTypeSet(1, BIT(bit - 32), 0x0); +} + +MV_BOOL bfGppDataInPolRegBitTest(MV_32 bit) +{ + if (bit < 0) + return MV_FALSE; + + if (bit < 32) + return MV_REG_READ(GPP_DATA_IN_POL_REG(0)) & BIT(bit) ? MV_TRUE : MV_FALSE; + else + return MV_REG_READ(GPP_DATA_IN_POL_REG(1)) & BIT(bit - 32) ? MV_TRUE : MV_FALSE; +} + +MV_VOID bfGppOutRegBitAssert(MV_32 bit) +{ + MV_U32 group; + MV_U32 mask; + MV_U32 value; + + if (bit < 0) + return; + + if (bit < 32) { + mask = BIT(bit); + group = 0; + } + else { + mask = BIT(bit - 32); + group = 1; + } + + if (bfGppDataInPolRegBitTest(bit)) + value = 0x0; + else + value = 0xffffffff; + + mvGppValueSet(group, mask, value); +} + +MV_VOID bfGppOutRegBitNagate(MV_32 bit) +{ + MV_U32 group; + MV_U32 mask; + MV_U32 value; + + if (bit < 0) + return; + + if (bit < 32) { + mask = BIT(bit); + group = 0; + } + else { + mask = BIT(bit - 32); + group = 1; + } + + if (bfGppDataInPolRegBitTest(bit)) + value = 0xffffffff; + else + value = 0x0; + + mvGppValueSet(group, mask, value); +} + +#endif // CONFIG_BUFFALO_PLATFORM diff --git a/board/mv_feroceon/mv_hal/gpp/mvGpp.h b/board/mv_feroceon/mv_hal/gpp/mvGpp.h new file mode 100644 index 0000000..438e545 --- /dev/null +++ b/board/mv_feroceon/mv_hal/gpp/mvGpp.h @@ -0,0 +1,135 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvGppH +#define __INCmvGppH + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "gpp/mvGppRegs.h" + +/* These macros describes the GPP type. Each of the GPPs pins can */ +/* be assigned to act as a general purpose input or output pin. */ +#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ +#define MV_GPP_OUT 0 /* GPP output */ + + +/* These macros describes the GPP Out Enable. */ +#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ +#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ + +/* These macros describes the GPP Out Blinking. */ +/* When set and the corresponding bit in GPIO Data Out Enable Control */ +/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ +/* 2^24 TCLK clocks). */ +#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ +#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ + + +/* These macros describes the GPP Polarity. */ +/* When set to 1 GPIO Data In Register reflects the inverted value of the */ +/* corresponding pin. */ + +#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ +#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ + +/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ +MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); + +/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ +MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); + +/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ +MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); + +/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ +MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); + +/* mvGppValueGet - Get a GPP Pin list value.*/ +MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); + + +/* mvGppValueSet - Set a GPP Pin list value. */ +MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); + +#if defined(CONFIG_BUFFALO_PLATFORM) +MV_BOOL bfGppInRegBitTest(MV_32 bit); +MV_BOOL bfGppOutRegBitTest(MV_32 bit); +MV_VOID bfGppOutRegBitSet(MV_32 bit); +MV_VOID bfGppOutRegBitClr(MV_32 bit); +MV_VOID bfGppOutRegBitInv(MV_32 bit); +MV_BOOL bfGppBlinkRegBitTest(MV_32 bit); +MV_VOID bfGppBlinkRegBitSet(MV_32 bit); +MV_VOID bfGppBlinkRegBitClr(MV_32 bit); +MV_BOOL bfGppOutEnableRegBitTest(MV_32 bit); +MV_VOID bfGppOutEnableRegBitSet(MV_32 bit); +MV_VOID bfGppOutEnableRegBitClr(MV_32 bit); +MV_VOID bfGppOutRegBitAssert(MV_32 bit); +MV_VOID bfGppOutRegBitNagate(MV_32 bit); +#endif // CONFIG_BUFFALO_PLATFORM + +#endif /* #ifndef __INCmvGppH */ + diff --git a/board/mv_feroceon/mv_hal/gpp/mvGppRegs.h b/board/mv_feroceon/mv_hal/gpp/mvGppRegs.h new file mode 100644 index 0000000..b6fec34 --- /dev/null +++ b/board/mv_feroceon/mv_hal/gpp/mvGppRegs.h @@ -0,0 +1,116 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvGppRegsH +#define __INCmvGppRegsH + +#define MV_GPP0 BIT0 +#define MV_GPP1 BIT1 +#define MV_GPP2 BIT2 +#define MV_GPP3 BIT3 +#define MV_GPP4 BIT4 +#define MV_GPP5 BIT5 +#define MV_GPP6 BIT6 +#define MV_GPP7 BIT7 +#define MV_GPP8 BIT8 +#define MV_GPP9 BIT9 +#define MV_GPP10 BIT10 +#define MV_GPP11 BIT11 +#define MV_GPP12 BIT12 +#define MV_GPP13 BIT13 +#define MV_GPP14 BIT14 +#define MV_GPP15 BIT15 +#define MV_GPP16 BIT16 +#define MV_GPP17 BIT17 +#define MV_GPP18 BIT18 +#define MV_GPP19 BIT19 +#define MV_GPP20 BIT20 +#define MV_GPP21 BIT21 +#define MV_GPP22 BIT22 +#define MV_GPP23 BIT23 +#define MV_GPP24 BIT24 +#define MV_GPP25 BIT25 +#define MV_GPP26 BIT26 +#define MV_GPP27 BIT27 +#define MV_GPP28 BIT28 +#define MV_GPP29 BIT29 +#define MV_GPP30 BIT30 +#define MV_GPP31 BIT31 + + +/* registers offsets */ + +#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) +#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) +#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) +#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) +#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) +#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) +#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) +#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) + +#define GPP_DATA_OUT_SET_REG 0x10120 +#define GPP_DATA_OUT_CLEAR_REG 0x10124 + +#endif /* #ifndef __INCmvGppRegsH */ diff --git a/board/mv_feroceon/mv_hal/idma/mvCompVer.txt b/board/mv_feroceon/mv_hal/idma/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/idma/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/idma/mvIdma.c b/board/mv_feroceon/mv_hal/idma/mvIdma.c new file mode 100644 index 0000000..8877c99 --- /dev/null +++ b/board/mv_feroceon/mv_hal/idma/mvIdma.c @@ -0,0 +1,458 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/******************************************************************************* +* mvIdma.c - Implementation file for IDMA HW library +* +* DESCRIPTION: +* This file contains Marvell Controller IDMA HW library API +* implementation. +* NOTE: +* 1) This HW library API assumes IDMA source, destination and +* descriptors are cache coherent. +* 2) In order to gain high performance, the API does not parform +* API parameter checking. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "idma/mvIdma.h" + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/******************************************************************************* +* mvDmaInit - Initialize IDMA engine +* +* DESCRIPTION: +* This function initialize IDMA unit. +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if setting fail. +*******************************************************************************/ +MV_VOID mvDmaHalInit(MV_U32 dmaChanNum) +{ + MV_U32 i; + + /* Abort any DMA activity */ + for(i = 0; i < dmaChanNum; i++) + { + mvDmaCommandSet(i, MV_STOP); + +#if defined(MV_CPU_LE) || defined(MV78XX0) + /* The following must be set */ + mvDmaCtrlHighSet(i, (ICCHR_ENDIAN_LITTLE +#if defined(MV_CPU_LE) + | ICCHR_DESC_BYTE_SWAP_EN +#endif /* MV_CPU_LE */ + )); +#endif /* MV_CPU_LE || MV78XX0 */ + } + MV_REG_WRITE( IDMA_CAUSE_REG, 0); +} + +/******************************************************************************* +* mvDmaCtrlLowSet - Set IDMA channel control low register +* +* DESCRIPTION: +* Each IDMA Channel has its own unique control registers (high and low) +* where certain IDMA modes are programmed. +* This function writes 32bit word to IDMA control low register. +* +* !!!!!! WARNING !!!!!! +* If system uses the IDMA DRAM HW cache coherency the source and +* destination maximum DTL size must be cache line size. +* +* INPUT: +* chan - DMA channel number. See MV_DMA_CHANNEL enumerator. +* ctrlWord - Channel control word for low register. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK +* +* NOTE: This function can modified the Override attribute that mvDmaOverrideSet +* configured. +*******************************************************************************/ +MV_STATUS mvDmaCtrlLowSet(MV_U32 chan, MV_U32 ctrlWord) +{ + MV_REG_WRITE(IDMA_CTRL_LOW_REG(chan), ctrlWord); + return MV_OK; +} + + +/******************************************************************************* +* mvDmaCtrlHighSet - Set IDMA channel control high register +* +* DESCRIPTION: +* Each IDMA Channel has its own unique control registers (high and low) +* where certain IDMA modes are programmed. +* This function writes 32bit word to IDMA control high register. +* +* INPUT: +* chan - DMA channel number. See MV_DMA_CHANNEL enumerator. +* ctrlWord - Channel control word for high register. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK. +* +*******************************************************************************/ +MV_STATUS mvDmaCtrlHighSet(MV_U32 chan, MV_U32 ctrlWord) +{ + MV_REG_WRITE(IDMA_CTRL_HIGH_REG(chan), ctrlWord); + return MV_OK; +} + +/******************************************************************************* +* mvDmaTransfer - Transfer data from source to destination +* +* DESCRIPTION: +* This function initiates IDMA channel, according to function parameters, +* in order to perform DMA transaction. +* This routine supports both chain and none chained DMA modes. +* To use the function in chain mode just set phyNextDesc parameter with +* chain second descriptor address (the first one is given in other +* function paarameters). Otherwise (none chain mode) set it to NULL. +* To gain maximum performance the user is asked to keep the following +* restrictions: +* 1) Selected engine is available (not busy). +* 1) This module does not take into consideration CPU MMU issues. +* In order for the IDMA engine to access the appropreate source +* and destination, address parameters must be given in system +* physical mode. +* 2) This API does not take care of cache coherency issues. The source, +* destination and in case of chain the descriptor list are assumed +* to be cache coherent. +* 3) In case of chain mode, the API does not align the user descriptor +* chain. Instead, the user must make sure the descriptor chain is +* aligned according to IDMA rquirements. +* 4) Parameters validity. For example, does size parameter exceeds +* maximum byte count of descriptor mode (16M or 64K). +* +* INPUT: +* chan - DMA channel number. See MV_DMA_CHANNEL enumerator. +* phySrc - Physical source address. +* phyDst - Physical destination address. +* size - The total number of bytes to transfer. +* *pPhyNextDesc - Physical address pointer to 2nd descriptor in chain. +* In case of none chain mode set it to NULL. +* +* OUTPUT: +* None. +* +* RETURS: +* MV_OK. +* +*******************************************************************************/ +MV_STATUS mvDmaTransfer(MV_U32 chan, MV_U32 phySrc, MV_U32 phyDst, MV_U32 size, + MV_U32 phyNextDescPtr) +{ + /* Set byte count register */ + MV_REG_WRITE(IDMA_BYTE_COUNT_REG(chan), size); + /* Set source address register */ + MV_REG_WRITE(IDMA_SRC_ADDR_REG(chan), phySrc); + /* Set destination address register */ + MV_REG_WRITE(IDMA_DST_ADDR_REG(chan), phyDst); + /* UnLock the Source address in dma operation */ + MV_REG_BIT_RESET(IDMA_CTRL_LOW_REG(chan), ICCLR_SRC_HOLD); + + if (0 != phyNextDescPtr) + { /* Chain mode. Set next descriptor register */ + MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(chan), phyNextDescPtr); + } + + /* Start DMA */ + MV_REG_BIT_SET(IDMA_CTRL_LOW_REG(chan), ICCLR_CHAN_ENABLE); + + return MV_OK; +} + +/******************************************************************************* +* mvDmaMemInit - Initialize a memory buffer with a given 64bit value pattern +* +* DESCRIPTION: +* This function initiates IDMA channel, according to function parameters, +* in order to perform DMA transaction for the purpose of initializing a +* memory buffer with a user supplied pattern. +* This routine supports both chain and none chained DMA modes. +* To use the function in chain mode just set phyNextDesc parameter with +* chain second descriptor address (the first one is given in other +* function paarameters). Otherwise (none chain mode) set it to NULL. +* To gain maximum performance the user is asked to keep the following +* restrictions: +* 1) Selected engine is available (not busy). +* 1) This module does not take into consideration CPU MMU issues. +* In order for the IDMA engine to access the appropreate source +* and destination, address parameters must be given in system +* physical mode. +* 2) This API does not take care of cache coherency issues. The source, +* destination and in case of chain the descriptor list are assumed +* to be cache coherent. +* 3) No chain mode support. +* 4) Parameters validity. For example, does size parameter exceeds +* maximum byte count of descriptor mode (16M or 64K). +* +* INPUT: +* chan - DMA channel number. See MV_DMA_CHANNEL enumerator. +* ptrnPtr - Physical source address of the 64bit pattern +* startPtr - Physical destinaation address to start with +* size - The total number of bytes to transfer. +* +* OUTPUT: +* None. +* +* RETURS: +* MV_OK. +* +*******************************************************************************/ +MV_STATUS mvDmaMemInit(MV_U32 chan, MV_U32 ptrnPtr, MV_U32 startPtr, MV_U32 size) +{ + /* Set byte count register */ + MV_REG_WRITE(IDMA_BYTE_COUNT_REG(chan), size); + /* Set source address register */ + MV_REG_WRITE(IDMA_SRC_ADDR_REG(chan), ptrnPtr); + /* Set destination address register */ + MV_REG_WRITE(IDMA_DST_ADDR_REG(chan), startPtr); + /* Lock the Source address in dma operation */ + MV_REG_BIT_SET(IDMA_CTRL_LOW_REG(chan), ICCLR_SRC_HOLD); + + /* Start DMA */ + MV_REG_BIT_SET(IDMA_CTRL_LOW_REG(chan), ICCLR_CHAN_ENABLE); + + return MV_OK; +} + +/******************************************************************************* +* mvDmaStateGet - Get IDMA channel status. +* +* DESCRIPTION: +* DMA channel status can be active, stopped, paused. +* This function retrunes the channel status. +* +* INPUT: +* chan - IDMA channel number. See MV_DMA_CHANNEL enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* One of MV_STATE enumerator values. +* +*******************************************************************************/ +MV_STATE mvDmaStateGet(MV_U32 chan) +{ + MV_U32 ctrlLow; + + /* Read control low register */ + ctrlLow = MV_REG_READ(IDMA_CTRL_LOW_REG(chan)); + + /* Leave only enable/active bits */ + ctrlLow &= (ICCLR_CHAN_ENABLE | ICCLR_CHAN_ACTIVE); + + /* If channel is enabled and active then its running */ + if (ctrlLow == (ICCLR_CHAN_ENABLE | ICCLR_CHAN_ACTIVE)) + { + return MV_ACTIVE; + } + /* If channel is disabled but active then its paused */ + else if (ctrlLow == ICCLR_CHAN_ACTIVE) + { + return MV_PAUSED; + } + else + { + return MV_IDLE; + } +} + +/******************************************************************************* +* mvDmaCommandSet - Set command to DMA channel +* +* DESCRIPTION: +* DMA channel can be started, idel, paused and restarted. +* Paused can be set only if channel is active. +* Start can be set only if channel is idle. +* Restart can be set only if channel is paused. +* Stop activate the channel abort which cause the DMA to aborts in the +* middle of a transaction. +* +* INPUT: +* chan - IDMA channel number. See MV_DMA_CHANNEL enumerator. +* command - Requested command. See MV_COMMAND enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if requested command can not be set. +* +*******************************************************************************/ +MV_STATUS mvDmaCommandSet(MV_U32 chan, MV_COMMAND command) +{ + MV_U32 ctrlLow; + MV_U32 dmaStatus; + + /* Read control low register */ + ctrlLow = MV_REG_READ(IDMA_CTRL_LOW_REG(chan)); + + /* Get current DMA status */ + dmaStatus = mvDmaStateGet(chan); + + if ((command == MV_START) && (dmaStatus == MV_IDLE)) + { + /* To start, set DMA channel enable bit */ + ctrlLow |= ICCLR_CHAN_ENABLE; + } + else if ((command == MV_PAUSE) && (dmaStatus == MV_ACTIVE)) + { + /* To pause, reset DMA channel enable bit */ + ctrlLow &= ~ICCLR_CHAN_ENABLE; + } + else if ((command == MV_RESTART) && (dmaStatus == MV_PAUSED)) + { + /* To restart, set DMA channel enable bit */ + ctrlLow |= ICCLR_CHAN_ENABLE; + } + else if (command == MV_STOP) + { + /* To stop, set DMA channel abort bit */ + ctrlLow |= ICCLR_CHANNEL_ABORT; + } + else + { + DB(mvOsPrintf("mvDmaCommandSet: ERR. Can not set command %d in \ + status %d\n", command, dmaStatus)); + return MV_ERROR; + } + + /* Write control word to register */ + MV_REG_WRITE(IDMA_CTRL_LOW_REG(chan), ctrlLow); + + /* If comman is stop, ensure channel is stopped */ + if (command == MV_STOP) + { + while(MV_IDLE != mvDmaStateGet(chan)); + } + + return MV_OK; +} + + +/************ DEBUG ***********/ +MV_VOID mvIdmaRegs(MV_U32 chan) +{ + mvOsPrintf("\t IDMA #%d Registers:\n", chan); + + mvOsPrintf("IDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", + IDMA_BYTE_COUNT_REG(chan), + MV_REG_READ( IDMA_BYTE_COUNT_REG(chan) ) ); + + mvOsPrintf("IDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", + IDMA_SRC_ADDR_REG(chan), + MV_REG_READ( IDMA_SRC_ADDR_REG(chan) ) ); + + mvOsPrintf("IDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", + IDMA_DST_ADDR_REG(chan), + MV_REG_READ( IDMA_DST_ADDR_REG(chan) ) ); + + mvOsPrintf("IDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", + IDMA_NEXT_DESC_PTR_REG(chan), + MV_REG_READ( IDMA_NEXT_DESC_PTR_REG(chan) ) ); + + mvOsPrintf("IDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", + IDMA_CURR_DESC_PTR_REG(chan), + MV_REG_READ( IDMA_CURR_DESC_PTR_REG(chan) ) ); + + mvOsPrintf("IDMA_CTRL_LOW_REG : 0x%X = 0x%08x\n", + IDMA_CTRL_LOW_REG(chan), + MV_REG_READ( IDMA_CTRL_LOW_REG(chan) ) ); + + mvOsPrintf("IDMA_CTRL_HIGH_REG : 0x%X = 0x%08x\n", + IDMA_CTRL_HIGH_REG(chan), + MV_REG_READ( IDMA_CTRL_HIGH_REG(chan) ) ); + + mvOsPrintf("IDMA_CAUSE_REG : 0x%X = 0x%08x\n", + IDMA_CAUSE_REG, + MV_REG_READ( IDMA_CAUSE_REG ) ); + + mvOsPrintf("IDMA_MASK_REG : 0x%X = 0x%08x\n", + IDMA_MASK_REG, + MV_REG_READ( IDMA_MASK_REG ) ); +} + diff --git a/board/mv_feroceon/mv_hal/idma/mvIdma.h b/board/mv_feroceon/mv_hal/idma/mvIdma.h new file mode 100644 index 0000000..c2cfd9b --- /dev/null +++ b/board/mv_feroceon/mv_hal/idma/mvIdma.h @@ -0,0 +1,120 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvIdma.h - Header File for : +* +* DESCRIPTION: +* This file contains Marvell Controller IDMA HW library API. +* NOTE: This HW library API assumes IDMA source, destination and +* descriptors are cache coherent. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + + +#ifndef __INCmvIdmah +#define __INCmvIdmah + +#include "mvCommon.h" +#include "mvOs.h" +#include "idma/mvIdmaRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* defines */ +#define MV_IDMA_DESC_ALIGNMENT 0x10 /* 16bytes aligment restriction */ + +/* typedefs */ + + +/* This struct describes IDMA descriptor structure */ +typedef struct _mvDmaDesc +{ + MV_U32 byteCnt; /* The total number of bytes to transfer */ + MV_U32 phySrcAdd; /* The physical source address */ + MV_U32 phyDestAdd; /* The physical destination address */ + MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ + /* then this pointer should point to the */ + /* physical address of the next descriptor, */ + /* otherwise it should be NULL. */ +}MV_DMA_DESC; + + +/* mvIdma.h API list */ +MV_VOID mvDmaHalInit (MV_U32); +MV_STATUS mvDmaCtrlLowSet (MV_U32 chan, MV_U32 ctrlWord); +MV_STATUS mvDmaCtrlHighSet(MV_U32 chan, MV_U32 ctrlWord); +MV_STATUS mvDmaTransfer(MV_U32 chan, MV_U32 phySrc, MV_U32 phyDst, MV_U32 size, + MV_U32 phyNextDescPtr); +MV_STATUS mvDmaMemInit(MV_U32 chan, MV_U32 ptrnPtr, MV_U32 startPtr, MV_U32 size); +MV_STATE mvDmaStateGet(MV_U32 chan); +MV_STATUS mvDmaCommandSet(MV_U32 chan, MV_COMMAND command); + +MV_VOID mvIdmaRegs(MV_U32 chan); + +#endif /* __INCmvIdmah */ + + diff --git a/board/mv_feroceon/mv_hal/idma/mvIdmaRegs.h b/board/mv_feroceon/mv_hal/idma/mvIdmaRegs.h new file mode 100644 index 0000000..575acf2 --- /dev/null +++ b/board/mv_feroceon/mv_hal/idma/mvIdmaRegs.h @@ -0,0 +1,210 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvIdmaSpech +#define __INCmvIdmaSpech + + +/* defines */ + + +/* IDMA channel rgisters */ +#define IDMA_BYTE_COUNT_REG(chan) (IDMA_UNIT_BASE + 0x0 + ((chan) * 4)) +#define IDMA_SRC_ADDR_REG(chan) (IDMA_UNIT_BASE + 0x10 + ((chan) * 4)) +#define IDMA_DST_ADDR_REG(chan) (IDMA_UNIT_BASE + 0x20 + ((chan) * 4)) +#define IDMA_NEXT_DESC_PTR_REG(chan) (IDMA_UNIT_BASE + 0x30 + ((chan) * 4)) +#define IDMA_CURR_DESC_PTR_REG(chan) (IDMA_UNIT_BASE + 0x70 + ((chan) * 4)) + +/* IDMA Channel Control */ +#define IDMA_CTRL_LOW_REG(chan) (IDMA_UNIT_BASE + 0x40 + ((chan) * 4)) +#define IDMA_CTRL_HIGH_REG(chan) (IDMA_UNIT_BASE + 0x80 + ((chan) * 4)) + + /* IDMA Interrupt Register */ +#define IDMA_CAUSE_REG (IDMA_UNIT_BASE + 0xc0) +#define IDMA_MASK_REG (IDMA_UNIT_BASE + 0xc4) +#define IDMA_ERROR_ADDR_REG (IDMA_UNIT_BASE + 0xc8) +#define IDMA_ERROR_SELECT_REG (IDMA_UNIT_BASE + 0xcc) + + +/* DMA register fileds */ + + +/* IDMA Channel Byte Count Register (ICBCR) */ +#define ICBCR_BYTECNT_OFFS 0 /* Byte count field offset */ +#define ICBCR_BYTECNT_MASK_64K 0xFFFF /* Maximum Byte count for 64K */ +#define ICBCR_BYTECNT_MASK_16M 0xFFFFFF/* Maximum Byte count for 16M */ +#define ICBCR_BYTECNT_LEFT_OFFS 30 /* Applicable for 16M mode */ +#define ICBCR_BYTECNT_LEFT (1 << ICBCR_BYTECNT_LEFT_OFFS) +#define ICBCR_DESC_OWNER_OFFS 31 /* Descriptor owned by DMA/CPU */ +#define ICBCR_DESC_OWNER_MASK (1 << ICBCR_DESC_OWNER_OFFS) +#define ICBCR_DESC_OWNER_BY_DMA (0 << ICBCR_DESC_OWNER_OFFS) +#define ICBCR_DESC_OWNED_BY_CPU (1 << ICBCR_DESC_OWNER_OFFS) + + +/* IDMA Channel Control Low Register (ICCLR) */ +/* Data Transfer Limit Note: If an IDMA accesses a cache coherent DRAM */ +/* region, the burst limit must not exceed 32 bytes. */ +#define B_8BYTE 0 +#define B_16BYTE 1 +#define B_32BYTE 3 +#define B_64BYTE 7 +#define B_128BYTE 4 + +#define ICCLR_DST_BURST_LIM_OFFS 0 +#define ICCLR_DST_BURST_LIM_MASK (0x7 << ICCLR_DST_BURST_LIM_OFFS) +#define ICCLR_DST_BURST_LIM_8BYTE (B_8BYTE << ICCLR_DST_BURST_LIM_OFFS) +#define ICCLR_DST_BURST_LIM_16BYTE (B_16BYTE << ICCLR_DST_BURST_LIM_OFFS) +#define ICCLR_DST_BURST_LIM_32BYTE (B_32BYTE << ICCLR_DST_BURST_LIM_OFFS) +#define ICCLR_DST_BURST_LIM_64BYTE (B_64BYTE << ICCLR_DST_BURST_LIM_OFFS) +#define ICCLR_DST_BURST_LIM_128BYTE (B_128BYTE << ICCLR_DST_BURST_LIM_OFFS) +#define ICCLR_SRC_HOLD_OFFS 3 /* Hold/increment source address*/ +#define ICCLR_SRC_HOLD_MASK (1 << ICCLR_SRC_HOLD_OFFS) +#define ICCLR_SRC_INC (0 << ICCLR_SRC_HOLD_OFFS) +#define ICCLR_SRC_HOLD (1 << ICCLR_SRC_HOLD_OFFS) +#define ICCLR_ACK_WIDTH_OFFS 4 /* Asserted for one/two TCLK cycle */ +#define ICCLR_ACK_WIDTH_MASK (1 << ICCLR_ACK_WIDTH_OFFS) +#define ICCLR_ACK_WIDTH_ONE_TCLK (0 << ICCLR_ACK_WIDTH_OFFS) +#define ICCLR_ACK_WIDTH_TWO_TCLK (1 << ICCLR_ACK_WIDTH_OFFS) +#define ICCLR_DST_HOLD_OFFS 5 /* Hold/increment source address*/ +#define ICCLR_DST_HOLD_MASK (1 << ICCLR_DST_HOLD_OFFS) +#define ICCLR_DST_INC (0 << ICCLR_DST_HOLD_OFFS) +#define ICCLR_DST_HOLD (1 << ICCLR_DST_HOLD_OFFS) +#define ICCLR_SRC_BURST_LIM_OFFS 6 +#define ICCLR_SRC_BURST_LIM_MASK (0x7 << ICCLR_SRC_BURST_LIM_OFFS) +#define ICCLR_SRC_BURST_LIM_8BYTE (B_8BYTE << ICCLR_SRC_BURST_LIM_OFFS) +#define ICCLR_SRC_BURST_LIM_16BYTE (B_16BYTE << ICCLR_SRC_BURST_LIM_OFFS) +#define ICCLR_SRC_BURST_LIM_32BYTE (B_32BYTE << ICCLR_SRC_BURST_LIM_OFFS) +#define ICCLR_SRC_BURST_LIM_64BYTE (B_64BYTE << ICCLR_SRC_BURST_LIM_OFFS) +#define ICCLR_SRC_BURST_LIM_128BYTE (B_128BYTE << ICCLR_SRC_BURST_LIM_OFFS) +#define ICCLR_CHAIN_MODE_OFFS 9 +#define ICCLR_NON_CHAIN_MODE (1 << ICCLR_CHAIN_MODE_OFFS) +#define ICCLR_INT_MODE_OFFS 10 /* Interrupt mode */ +#define ICCLR_INT_MODE_MASK (1 << ICCLR_INT_MODE_OFFS) +#define ICCLR_INT_BYTE_CNT_ZERO (0 << ICCLR_INT_MODE_OFFS) +#define ICCLR_INT_EVERY_NULL_PTR (1 << ICCLR_INT_MODE_OFFS) +#define ICCLR_DEMAND_MODE_OFFS 11 /* Demand/Block transfer mode */ +#define ICCLR_DEMAND_MODE_MASK (1 << ICCLR_DEMAND_MODE_OFFS) +#define ICCLR_DEMAND_MODE (0 << ICCLR_DEMAND_MODE_OFFS) +#define ICCLR_BLOCK_MODE (1 << ICCLR_DEMAND_MODE_OFFS) +#define ICCLR_CHAN_ENABLE BIT12 /* Channel enable */ +#define ICCLR_FETCH_NEXT_DESC BIT13 /* Fetch next descriptor */ +#define ICCLR_CHAN_ACTIVE BIT14 /* Channel active */ +#define ICCLR_REQ_DIR_OFFS 15 /* Request generated by src/dst */ +#define ICCLR_REQ_DIR_MASK (1 << ICCLR_REQ_DIR_OFFS) +#define ICCLR_REQ_DIR_SRC (0 << ICCLR_REQ_DIR_OFFS) +#define ICCLR_REQ_DIR_DST (1 << ICCLR_REQ_DIR_OFFS) +#define ICCLR_REQ_MODE_OFFS 16 /* DMAReqn is level/edge input */ +#define ICCLR_REQ_MODE_MASK (1 << ICCLR_REQ_MODE_OFFS) +#define ICCLR_REQ_MODE_LEVEL (0 << ICCLR_REQ_MODE_OFFS) +#define ICCLR_REQ_MODE_EDGE (1 << ICCLR_REQ_MODE_OFFS) +#define ICCLR_CLOSE_DESC_ENABLE BIT17 /* Close descriptor enable */ +#define ICCLR_EOT_ENABLE BIT18 /* End Of Tarnsfer (EOT) enable */ +#define ICCLR_EOT_AFFECT_OFFS 19 /* EOT -> Fetch next descriptor/halt */ +#define ICCLR_EOT_AFFECT_MASK (1 << ICCLR_EOT_AFFECT_OFFS) +#define ICCLR_EOT_FETCH_NEXT (0 << ICCLR_EOT_AFFECT_OFFS) +#define ICCLR_EOT_FETCH_HALT (1 << ICCLR_EOT_AFFECT_OFFS) +#define ICCLR_CHANNEL_ABORT BIT20 /* Abort DMA transfer */ + +#define ICCLR_OVRRD_SRC_OFFS 21 +#define ICCLR_OVRRD_SRC_MASK (0x3 << ICCLR_OVRRD_SRC_OFFS) +#define ICCLR_OVRRD_SRC_BAR(barNo) ((barNo) << ICCLR_OVRRD_SRC_OFFS) + +#define ICCLR_OVRRD_DST_OFFS 23 +#define ICCLR_OVRRD_DST_MASK (0x3 << ICCLR_OVRRD_DST_OFFS) +#define ICCLR_OVRRD_DST_BAR(barNo) ((barNo) << ICCLR_OVRRD_DST_OFFS) + +#define ICCLR_OVRRD_NDSC_OFFS 25 +#define ICCLR_OVRRD_NDSC_MASK (0x3 << ICCLR_OVRRD_NDSC_OFFS) +#define ICCLR_OVRRD_NDSC_BAR(barNo) ((barNo) << ICCLR_OVRRD_NDSC_OFFS) + +#define ICCLR_DESC_MODE_OFFS 31 /* Descriptor mode 64KB/16M */ +#define ICCLR_DESC_MODE_MASK (1 << ICCLR_DESC_MODE_OFFS) +#define ICCLR_DESC_MODE_64K (0 << ICCLR_DESC_MODE_OFFS) +#define ICCLR_DESC_MODE_16M (1 << ICCLR_DESC_MODE_OFFS) + +/* IDMA Channel Control High Register (ICCHR) */ +#define ICCHR_ENDIANESS_OFFS 0 +#define ICCHR_ENDIANESS_MASK (1 << ICCHR_ENDIANESS_OFFS) +#define ICCHR_ENDIAN_BIG (0 << ICCHR_ENDIANESS_OFFS) +#define ICCHR_ENDIAN_LITTLE (1 << ICCHR_ENDIANESS_OFFS) +#define ICCHR_DESC_BYTE_SWAP_EN BIT1 /* swap the bytes of 64-bit */ + /* dword during descriptor fetch*/ +#define ICCHR_DESC_DEMAND_ENABLE BIT2 /* Descriptor Demand Mode en */ + +/* IDMA Channel Interrupt Cause Register (ICICR) */ +#define ICICR_CHAN_OFFS 8 +#define ICICR_CAUSE_OFFS(chan) (chan * ICICR_CHAN_OFFS) +#define ICICR_CAUSE_MASK_ALL(chan) (0xFF << ICICR_CAUSE_OFFS(chan)) +#define ICICR_CAUSE_MASK(chan, cause) (1 << (cause + ICICR_CAUSE_OFFS(chan))) +#define ICICR_COMP_MASK 0x01010101 +#define ICICR_ERR_MASK 0x3e3e3e3e + +/* IDMA Error Select Register (IESR) */ +#define IESR_ERR_TYPE_OFFS 0 +#define IESR_ERR_TYPE_MASK (0x1f << IESR_ERR_TYPE_OFFS) + + + +#endif /* __INCmvIdmaSpech */ + diff --git a/board/mv_feroceon/mv_hal/lcd/mvCompVer.txt b/board/mv_feroceon/mv_hal/lcd/mvCompVer.txt new file mode 100644 index 0000000..c6e1229 --- /dev/null +++ b/board/mv_feroceon/mv_hal/lcd/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_2 +Unit HAL Version: 3.1.0 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/lcd/mvLcd.c b/board/mv_feroceon/mv_hal/lcd/mvLcd.c new file mode 100644 index 0000000..2bbe1c3 --- /dev/null +++ b/board/mv_feroceon/mv_hal/lcd/mvLcd.c @@ -0,0 +1,90 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "lcd/mvLcd.h" +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif +/******************************************************************************* +* mvLcdrHalInit - Initialize LCD engine +* +* DESCRIPTION: +* This function initialize LCD unit. +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +*******************************************************************************/ +MV_VOID mvLcdHalInit (void) +{ +} + diff --git a/board/mv_feroceon/mv_hal/lcd/mvLcd.h b/board/mv_feroceon/mv_hal/lcd/mvLcd.h new file mode 100644 index 0000000..8a5f47f --- /dev/null +++ b/board/mv_feroceon/mv_hal/lcd/mvLcd.h @@ -0,0 +1,97 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvXor.h - Header File for : +* +* DESCRIPTION: +* This file contains Marvell Controller XOR HW library API. +* NOTE: This HW library API assumes XOR source, destination and +* descriptors are cache coherent. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCMVlcdh +#define __INCMVlcdh + +#include "mvCommon.h" +#include "mvOs.h" +#include "lcd/mvLcdRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* typedefs */ + +MV_VOID mvLcdHalInit (void); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/board/mv_feroceon/mv_hal/lcd/mvLcdRegs.h b/board/mv_feroceon/mv_hal/lcd/mvLcdRegs.h new file mode 100644 index 0000000..f128fe9 --- /dev/null +++ b/board/mv_feroceon/mv_hal/lcd/mvLcdRegs.h @@ -0,0 +1,78 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvLcdSpech +#define __INCmvLcdSpech + +#ifdef __cplusplus +extern "C" { +#endif + +/* defines */ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/board/mv_feroceon/mv_hal/mflash/mvCompVer.txt b/board/mv_feroceon/mv_hal/mflash/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/mflash/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/mflash/mvMFlash.c b/board/mv_feroceon/mv_hal/mflash/mvMFlash.c new file mode 100644 index 0000000..266dc37 --- /dev/null +++ b/board/mv_feroceon/mv_hal/mflash/mvMFlash.c @@ -0,0 +1,1320 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mflash/mvMFlash.h" +#include "mflash/mvPMFlash.h" +#include "mflash/mvSMFlash.h" +#include "mflash/mvMFlashSpec.h" +#include "mflash/mvPMFlashSpec.h" +#include "mflash/mvSMFlashSpec.h" + +/*#define MV_DEBUG*/ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* Static Functions */ +static MV_STATUS mvMFlashBlockByRegionWr(MV_MFLASH_INFO *pFlash, MV_U32 offset, \ + MV_U32 blockSize, MV_U8 *pBlock, MV_BOOL verify, \ + MV_BOOL main); +static MV_STATUS mvMFlash64bInfWr (MV_MFLASH_INFO *pFlash, MV_U32 offset, \ + MV_U8 *pBuff, MV_BOOL verify); +static MV_STATUS mvMFlash64bWr (MV_MFLASH_INFO *pFlash, MV_U32 offset, \ + MV_U8 *pBuff, MV_BOOL verify); + +/******************************************************************************* +* mvMFlashInit - Initialize a Marvell Flash device +* +* DESCRIPTION: +* This function performs the necessary initialization for a Marvell +* Sunol flash. +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* pFlash->baseAddr: flash base address. +* pFlash->ifMode: The mode used SPI or Parallel. +* +* OUTPUT: +* pFlash: pointer to the tructure with Marvell Flash information detected +* pFlash->flashModel: flash model deteced +* pFlash->sectorSize: Size of each sector (unified sector size) +* pFlash->sectorNumber: Number of sectors in the flash +* pFlash->infoSize: Size of the Information region. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashInit (MV_MFLASH_INFO *pFlash) +{ + MV_U32 manufId; + MV_U16 devId; + MV_U8 reg; + MV_STATUS ret; + + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + { + /* perform the basic initialization */ + if ((ret = mvPMFlashInit(pFlash)) != MV_OK) + return ret; + + /* Try to read the device ID and decide the device model */ + if ((ret = mvPMFlashIdGet(pFlash, &manufId, &devId)) != MV_OK) + return ret; + + /* Get the Serial interface configuration register to check sector size */ + if ((ret = mvPMFlashReadConfig4(pFlash, ®)) != MV_OK) + return ret; + } + else if (pFlash->ifMode == MV_MFLASH_SPI) + { + /* perform the basic initialization */ + if ((ret = mvSMFlashInit(pFlash)) != MV_OK) + return ret; + + /* Try to read the device ID and decide the device model */ + if ((ret = mvSMFlashIdGet(pFlash, &manufId, &devId)) != MV_OK) + return ret; + + /* Get the Serial interface configuration register to check sector size */ + if ((ret = mvSMFlashReadConfig4(pFlash, ®)) != MV_OK) + return ret; + } + else + { + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* check the manufacturer Id to be the same as MARVELL */ + if (manufId != MV_MFLASH_MANUFACTURER_ID) + { + mvOsPrintf("%s ERROR: Flash unknown manufacturer ID!\n", __FUNCTION__); + return MV_NOT_SUPPORTED; + } + + /* based on device ID and the PAGE4K bit fill model, sector size and number */ + switch (devId & MV_MFLASH_DEVICE_ID_MASK) + { + case MV_MFLASH_DEVICE_ID_SUNOL_1: + pFlash->flashModel = MV_MFLASH_SUNOL_1; + pFlash->infoSize = MV_MFLASH_INF_MEM_SZ_SUNOL_1; + if (reg & MV_SMFLASH_SRL_CFG4_PG_SIZE_MASK) /* 1 - page is 4K */ + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_SMALL; + pFlash->sectorNumber = MV_MFLASH_SMALL_SEC_NUM_SUNOL_1; + } + else /* 0 - page is 32K */ + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_BIG; + pFlash->sectorNumber = MV_MFLASH_BIG_SEC_NUM_SUNOL_1; + } + break; + + case MV_MFLASH_DEVICE_ID_SUNOL_2: + pFlash->flashModel = MV_MFLASH_SUNOL_2; + pFlash->infoSize = MV_MFLASH_INF_MEM_SZ_SUNOL_2_3; + if (reg & MV_SMFLASH_SRL_CFG4_PG_SIZE_MASK) /* 1 - page is 4K */ + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_SMALL; + pFlash->sectorNumber = MV_MFLASH_SMALL_SEC_NUM_SUNOL_2; + } + else /* 0 - page is 32K */ + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_BIG; + pFlash->sectorNumber = MV_MFLASH_BIG_SEC_NUM_SUNOL_2; + } + break; + + case MV_MFLASH_DEVICE_ID_SUNOL_3: + pFlash->flashModel = MV_MFLASH_SUNOL_3; + pFlash->infoSize = MV_MFLASH_INF_MEM_SZ_SUNOL_2_3; + if (reg & MV_SMFLASH_SRL_CFG4_PG_SIZE_MASK) /* 1 - page is 4K */ + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_SMALL; + pFlash->sectorNumber = MV_MFLASH_SMALL_SEC_NUM_SUNOL_3; + } + else /* 0 - page is 32K */ + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_BIG; + pFlash->sectorNumber = MV_MFLASH_BIG_SEC_NUM_SUNOL_3; + } + break; + + default: + mvOsPrintf("%s ERROR: Unknown Flash Device ID!\n", __FUNCTION__); + pFlash->flashModel = MV_MFLASH_MODEL_UNKNOWN; + return MV_NOT_SUPPORTED; + } + + return MV_OK; +} + + +/******************************************************************************* +* mvMFlashChipErase - Erase the whole flash +* +* DESCRIPTION: +* Erase the whole flash (both the Main and Information region) +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashChipErase (MV_MFLASH_INFO *pFlash) +{ + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + return mvPMFlashChipErase(pFlash); + else if (pFlash->ifMode == MV_MFLASH_SPI) + return mvSMFlashChipErase(pFlash); + + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvMFlashMainErase - Erase the main flash region only +* +* DESCRIPTION: +* Erase the Main flash region +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashMainErase (MV_MFLASH_INFO *pFlash) +{ + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + return mvPMFlashMainErase(pFlash); + else if (pFlash->ifMode == MV_MFLASH_SPI) + return mvSMFlashMainErase(pFlash); + + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvMFlashInfErase - Erase the information flash region only +* +* DESCRIPTION: +* Erase the information flash region +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashInfErase (MV_MFLASH_INFO *pFlash) +{ + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + return mvPMFlashInfErase(pFlash); + else if (pFlash->ifMode == MV_MFLASH_SPI) + return mvSMFlashInfErase(pFlash); + + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; +} + + +/******************************************************************************* +* mvMFlashSecErase - Erase the single sector of the main flash region +* +* DESCRIPTION: +* Erase one sector of the main flash region +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* secOffset: sector offset within the MFlash +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashSecErase (MV_MFLASH_INFO *pFlash, MV_U32 secNumber) +{ + MV_U32 i; + MV_U32 * pW = (MV_U32*) ((secNumber * pFlash->sectorSize) + pFlash->baseAddr); + MV_U32 erasedWord = 0xFFFFFFFF; + MV_U32 wordsPerSector = (pFlash->sectorSize / sizeof(MV_U32)); + MV_BOOL eraseNeeded = MV_FALSE; + + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* First compare to FF and check if erase is needed */ + for (i=0; iifMode == MV_MFLASH_PARALLEL) + return mvPMFlashSecErase(pFlash, secNumber); + else if (pFlash->ifMode == MV_MFLASH_SPI) + return mvSMFlashSecErase(pFlash, secNumber); + + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvMFlash64bWr - Perform the alligned write according to the SPI mode and verify +* type. +* +* DESCRIPTION: +* Select the appropriate write api according to the SPI mode and the +* verify flag. +* +*******************************************************************************/ +static MV_STATUS mvMFlash64bWr (MV_MFLASH_INFO *pFlash, MV_U32 offset, + MV_U8 *pBuff, MV_BOOL verify) +{ + MV_STATUS ret; + + /* check for NULL pointer */ +#ifndef CONFIG_MARVELL + if(NULL == pBuff) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } +#endif + + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* call the api based on the SPI mode and the verify option */ + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + { + if (verify) + { + if ((ret = mvPMFlash64bWrVerify(pFlash, offset, pBuff)) != MV_OK) + return ret; + } + else + { + if ((ret = mvPMFlash64bWr(pFlash, offset, pBuff)) != MV_OK) + return ret; + } + } + else if (pFlash->ifMode == MV_MFLASH_SPI) + { + if (verify) + { + if ((ret = mvSMFlash64bWrVerify(pFlash, offset, pBuff)) != MV_OK) + return ret; + } + else + { + if ((ret = mvSMFlash64bWr(pFlash, offset, pBuff)) != MV_OK) + return ret; + } + } + else + { + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return MV_OK; +} + +/******************************************************************************* +* mvMFlash64bInfWr - Perform the alligned write to the information region based +* on the SPI mode and verify type. +* +* DESCRIPTION: +* Select the appropriate write api according to the SPI mode and the +* verify flag. +* +*******************************************************************************/ +static MV_STATUS mvMFlash64bInfWr (MV_MFLASH_INFO *pFlash, MV_U32 offset, + MV_U8 *pBuff, MV_BOOL verify) +{ + MV_STATUS ret; + + /* check for NULL pointer */ +#ifndef CONFIG_MARVELL + if(NULL == pBuff) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } +#endif + + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* call the api based on the SPI mode and the verify option */ + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + { + if (verify) + { + if ((ret = mvPMFlash64bInfWrVerify(pFlash, offset, pBuff)) != MV_OK) + return ret; + } + else + { + if ((ret = mvPMFlash64bInfWr(pFlash, offset, pBuff)) != MV_OK) + return ret; + } + } + else if (pFlash->ifMode == MV_MFLASH_SPI) + { + if (verify) + { + if ((ret = mvSMFlash64bInfWrVerify(pFlash, offset, pBuff)) != MV_OK) + return ret; + + } + else + { + if ((ret = mvSMFlash64bInfWr(pFlash, offset, pBuff)) != MV_OK) + return ret; + } + } + else + { + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return MV_OK; +} + + + +/******************************************************************************* +* mvMFlashBlockByRegionWr - Write a buffer with a custom length and allignment +* based on the region (main or information) +* +* DESCRIPTION: +* Program a varient sized block in the selected region of the MFlash +* and perform the verify based on flag. +* +*******************************************************************************/ +static MV_STATUS mvMFlashBlockByRegionWr(MV_MFLASH_INFO *pFlash, MV_U32 offset, + MV_U32 blockSize, MV_U8 *pBlock, MV_BOOL verify, MV_BOOL main) +{ + MV_U8 tempBuff[MV_MFLASH_PROG_CHUNK_SIZE]; + MV_U32 data2write = blockSize; + MV_U32 preAllOfst = (offset & MV_MFLASH_PROG_ALIGN_MASK); + MV_U32 preAllSz = (preAllOfst ? (MV_MFLASH_PROG_CHUNK_SIZE - preAllOfst) : 0); + MV_U32 writeOffset = (offset & ~MV_MFLASH_PROG_ALIGN_MASK); + MV_STATUS ret; + + /* check for NULL pointer */ +#ifndef CONFIG_MARVELL + if(NULL == pBlock) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } +#endif + + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* verify that the write commands does not exceed the size */ + if ((offset + blockSize) > (pFlash->sectorNumber * pFlash->sectorSize)) + { + DB(mvOsPrintf("%s WARNING: Exceeded flash size!!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* check if the total block size is less than the first chunk remainder */ + if (data2write < preAllSz) + preAllSz = data2write; + + /* check if programing does not start at a 64byte alligned offset */ + if (preAllSz) + { + /* first copy the original data */ + if (main) + { + if ((ret = mvMFlashBlockRd(pFlash, writeOffset, MV_MFLASH_PROG_CHUNK_SIZE, tempBuff)) != MV_OK) + return ret; + } + else + { + if ((ret = mvMFlashBlockInfRd(pFlash, writeOffset, MV_MFLASH_PROG_CHUNK_SIZE, tempBuff)) != MV_OK) + return ret; + } + + /* overwrite the data to be changed */ + mvOsMemcpy((MV_VOID*)&tempBuff[preAllOfst], pBlock, preAllSz); + + /* Perform the 64 bytes write based on the mode and verify type */ + if (main) + { + if ((ret = mvMFlash64bWr(pFlash, writeOffset, tempBuff, verify)) != MV_OK) + return ret; + } + else + { + if ((ret = mvMFlash64bInfWr(pFlash, writeOffset, tempBuff, verify)) != MV_OK) + return ret; + } + + /* increment pointers and counters */ + writeOffset += MV_MFLASH_PROG_CHUNK_SIZE; + data2write -= preAllSz; + pBlock += preAllSz; + } + + /* program the data that fits in complete 64bytes chunks */ + while (data2write >= MV_MFLASH_PROG_CHUNK_SIZE) + { + /* Perform the 64 bytes write based on the mode and verify type */ + if (main) + { + if ((ret = mvMFlash64bWr(pFlash, writeOffset, pBlock, verify)) != MV_OK) + return ret; + } + else + { + if ((ret = mvMFlash64bInfWr(pFlash, writeOffset, pBlock, verify)) != MV_OK) + return ret; + } + + /* increment pointers and counters */ + writeOffset += MV_MFLASH_PROG_CHUNK_SIZE; + data2write -= MV_MFLASH_PROG_CHUNK_SIZE; + pBlock += MV_MFLASH_PROG_CHUNK_SIZE; + } + + /* program the last partial chunk */ + if (data2write) + { + /* first copy the original data */ + if (main) + { + if ((ret = mvMFlashBlockRd(pFlash, writeOffset, MV_MFLASH_PROG_CHUNK_SIZE, tempBuff)) != MV_OK) + return ret; + } + else + { + if ((ret = mvMFlashBlockInfRd(pFlash, writeOffset, MV_MFLASH_PROG_CHUNK_SIZE, tempBuff)) != MV_OK) + return ret; + } + + /* overwrite the data to be changed */ + mvOsMemcpy(tempBuff, pBlock, data2write); + + /* Perform the 64 bytes write based on the mode and verify type */ + if (main) + { + if ((ret = mvMFlash64bWr(pFlash, writeOffset, tempBuff, verify)) != MV_OK) + return ret; + } + else + { + if ((ret = mvMFlash64bInfWr(pFlash, writeOffset, tempBuff, verify)) != MV_OK) + return ret; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvMFlashBlockWr - Write a buffer with a custom length and allignment +* +* DESCRIPTION: +* Program a varient sized block in the Main region of the MFlash. +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* offset: offset within the Information region (limited to 1024) +* blockSize: size in bytes of the buffer to be programmed. +* pBlock: pointer to the 64 bytes buffer to be programed +* verify: bollean flag controlling the compare after program feature +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashBlockWr(MV_MFLASH_INFO *pFlash, MV_U32 offset, + MV_U32 blockSize, MV_U8 *pBlock, MV_BOOL verify) +{ + /* check for NULL pointers */ +#ifndef CONFIG_MARVELL + if(NULL == pBlock) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } +#endif + + if (NULL == pFlash) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvMFlashBlockByRegionWr(pFlash, offset, blockSize, pBlock, verify, MV_TRUE /* main region */); +} + + +/******************************************************************************* +* mvMFlashInfBlockWr - Write a buffer with a custom length and allignment to +* the information region of the flash +* +* DESCRIPTION: +* Program a varient sized block in the Information region of the MFlash. +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* offset: offset within the Information region (limited to 1024) +* blockSize: size in bytes of the buffer to be programmed. +* pBlock: pointer to the 64 bytes buffer to be programed +* verify: bollean flag controlling the compare after program feature +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashInfBlockWr(MV_MFLASH_INFO *pFlash, MV_U32 offset, + MV_U32 blockSize, MV_U8 *pBlock, MV_BOOL verify) +{ + /* check for NULL pointers */ + if ((pFlash == NULL) || (pBlock == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvMFlashBlockByRegionWr(pFlash, offset, blockSize, pBlock, verify, MV_FALSE /* info region */); +} + +/******************************************************************************* +* mvMFlashBlockRd - Read a block of Memory from the Main Flash +* +* DESCRIPTION: +* Read a block of Memory from the Main Flash region +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* offset: offset to read from the main region of the MFlash +* blockSize: number of bytes to read from the offset +* pBlock: pointer of the buffer to fill +* +* OUTPUT: +* pBlock: pointer of the buffer holding the data read from flash. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashBlockRd (MV_MFLASH_INFO *pFlash, MV_U32 offset, + MV_U32 blockSize, MV_U8 *pBlock) +{ + /* check for NULL pointers */ + if ((pFlash == NULL) || (pBlock == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + return mvPMFlashBlockRd(pFlash, offset, blockSize, pBlock); + else if (pFlash->ifMode == MV_MFLASH_SPI) + return mvSMFlashBlockRd(pFlash, offset, blockSize, pBlock); + + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvMFlashSecErase - Erase the single sector of the main flash region +* +* DESCRIPTION: +* Erase one sector of the main flash region +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* secOffset: sector offset within the MFlash +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashBlockInfRd (MV_MFLASH_INFO *pFlash, MV_U32 offset, + MV_U32 blockSize, MV_U8 *pBlock) +{ + /* check for NULL pointers */ + if ((pFlash == NULL) || (pBlock == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + return mvPMFlashBlockInfRd(pFlash, offset, blockSize, pBlock); + else if (pFlash->ifMode == MV_MFLASH_SPI) + return mvSMFlashBlockInfRd(pFlash, offset, blockSize, pBlock); + + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvMFlashReadConfig - Read the Configuration register +* +* DESCRIPTION: +* Perform the Read CONFIGx register RAB +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* regNum: register number to read (1-4 in parallel and 3-4 in spi) +* pConfigReg: pointer to read in the configuration register +* +* OUTPUT: +* pConfigReg: pointer with the data read from the configuration register +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashReadConfig (MV_MFLASH_INFO *pFlash, MV_U32 regNum, MV_U8 * pConfigReg) +{ + /* check for NULL pointer */ + if ((pFlash == NULL) || (pConfigReg == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + { + switch (regNum) + { + case 1: + return mvPMFlashReadConfig1(pFlash, pConfigReg); + + case 2: + return mvPMFlashReadConfig2(pFlash, pConfigReg); + + case 3: + return mvPMFlashReadConfig3(pFlash, pConfigReg); + + case 4: + return mvPMFlashReadConfig4(pFlash, pConfigReg); + + default: + DB(mvOsPrintf("%s WARNING: Not supported in parallel mode!!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + } + } + else if (pFlash->ifMode == MV_MFLASH_SPI) + { + switch (regNum) + { + case 3: + return mvSMFlashReadConfig3(pFlash, pConfigReg); + + case 4: + return mvSMFlashReadConfig4(pFlash, pConfigReg); + + default: + DB(mvOsPrintf("%s WARNING: Not supported in SPI mode!!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + } + } + + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvMFlashSetConfig - Write to the Configuration register +* +* DESCRIPTION: +* Perform the write CONFIGx register RAB +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* regNum: register number to write (1-4 in parallel and 3-4 in spi) +* configReg: Data to write in the configuration register +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashSetConfig (MV_MFLASH_INFO *pFlash, MV_U32 regNum, MV_U8 configReg) +{ + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + { + switch (regNum) + { + case 1: + return mvPMFlashSetConfig1(pFlash, configReg); + + case 2: + return mvPMFlashSetConfig2(pFlash, configReg); + + case 3: + return mvPMFlashSetConfig3(pFlash, configReg); + + case 4: + return mvPMFlashSetConfig4(pFlash, configReg); + + default: + DB(mvOsPrintf("%s WARNING: Not supported in parallel mode!!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + } + } + else if (pFlash->ifMode == MV_MFLASH_SPI) + { + switch (regNum) + { + case 3: + return mvSMFlashSetConfig3(pFlash, configReg); + + case 4: + return mvSMFlashSetConfig4(pFlash, configReg); + + default: + DB(mvOsPrintf("%s WARNING: Not supported in SPI mode!!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + } + } + + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvMFlashSetSlewRate - Set the slew rate for parallel interface +* +* DESCRIPTION: +* Perform the set slew rate register RAB +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* configReg: Data to write in the slew rate register +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashSetSlewRate (MV_MFLASH_INFO *pFlash, MV_U8 configReg) +{ + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + return mvPMFlashSetSlewRate(pFlash, configReg); + + DB(mvOsPrintf("%s WARNING: Invalid interface mode!\n", __FUNCTION__);) + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvMFlashWriteProtectSet - Set the write protection feature status +* +* DESCRIPTION: +* Enable or disable the write protection +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* wp: write protection status (enable = MV_TRUE, disable = MVFALSE) +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashWriteProtectSet (MV_MFLASH_INFO *pFlash, MV_BOOL wp) +{ + MV_U32 reg; + + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* read, modify then write the register */ + reg = MV_REG_READ(MV_PMFLASH_IF_CFG_REG); + if (wp) /* active low */ + reg &= ~MV_PMFLASH_WP_PROTECT_MASK; + else + reg |= MV_PMFLASH_WP_PROTECT_MASK; + + MV_REG_WRITE(MV_PMFLASH_IF_CFG_REG, reg); + + return MV_OK; + +#if 0 + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + return mvPMFlashWriteProtectSet(pFlash, wp); + else if (pFlash->ifMode == MV_MFLASH_SPI) + return mvSMFlashWriteProtectSet(pFlash, wp); + + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; +#endif +} + +/******************************************************************************* +* mvMFlashWriteProtectGet - Get the write protection feature status +* +* DESCRIPTION: +* Retreive the write protection status from the hardware (from the MFlash +* controller and not from the flash device configuration register) +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* wp: pointer to the variable to retreive the write protection status in +* +* OUTPUT: +* None. +* wp: pointer to the variable holding the write protection status +* (enable = MV_TRUE, disable = MVFALSE) +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashWriteProtectGet(MV_MFLASH_INFO *pFlash, MV_BOOL * pWp) +{ + MV_U32 reg; + + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* read the register and check the bit status */ + reg = MV_REG_READ(MV_PMFLASH_IF_CFG_REG); + if (reg & MV_PMFLASH_WP_PROTECT_MASK) + *pWp = MV_FALSE; + else + *pWp = MV_TRUE; + + return MV_OK; +} + +/******************************************************************************* +* mvMFlashSectorSizeSet - Set the sector size +* +* DESCRIPTION: +* Set the sector size of the MFLASH main region +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* secSize: size of sector in bytes (either 4K or 32K) +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashSectorSizeSet (MV_MFLASH_INFO *pFlash, MV_U32 secSize) +{ + MV_STATUS ret; + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + ret = mvPMFlashSectorSizeSet(pFlash, secSize); + else if (pFlash->ifMode == MV_MFLASH_SPI) + ret = mvSMFlashSectorSizeSet(pFlash, secSize); + else + { + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (ret != MV_OK) + return ret; + + /* update the sector size and number in the structure */ + switch (pFlash->flashModel) + { + case MV_MFLASH_SUNOL_1: + if (secSize == MV_MFLASH_SECTOR_SIZE_SMALL) + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_SMALL; + pFlash->sectorNumber = MV_MFLASH_SMALL_SEC_NUM_SUNOL_1; + } + else + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_BIG; + pFlash->sectorNumber = MV_MFLASH_BIG_SEC_NUM_SUNOL_1; + } + break; + + case MV_MFLASH_SUNOL_2: + if (secSize == MV_MFLASH_SECTOR_SIZE_SMALL) + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_SMALL; + pFlash->sectorNumber = MV_MFLASH_SMALL_SEC_NUM_SUNOL_2; + } + else + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_BIG; + pFlash->sectorNumber = MV_MFLASH_BIG_SEC_NUM_SUNOL_2; + } + break; + + case MV_MFLASH_SUNOL_3: + if (secSize == MV_MFLASH_SECTOR_SIZE_SMALL) + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_SMALL; + pFlash->sectorNumber = MV_MFLASH_SMALL_SEC_NUM_SUNOL_3; + } + else + { + pFlash->sectorSize = MV_MFLASH_SECTOR_SIZE_BIG; + pFlash->sectorNumber = MV_MFLASH_BIG_SEC_NUM_SUNOL_3; + } + break; + + default: + mvOsPrintf("%s ERROR: Unknown Flash Type!\n", __FUNCTION__); + return MV_NOT_SUPPORTED; + } + + return MV_OK; +} + + +/******************************************************************************* +* mvMFlashPrefetchSet - Set the Prefetch mode enable/disable +* +* DESCRIPTION: +* Enable (MV_TRUE) or Disable (MV_FALSE) the prefetch mode +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* prefetch: enable/disable (MV_TRUE/MV_FALSE) +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashPrefetchSet (MV_MFLASH_INFO *pFlash, MV_BOOL prefetch) +{ + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + return mvPMFlashPrefetchSet(pFlash, prefetch); + + DB(mvOsPrintf("%s WARNING: Invalid interface mode!\n", __FUNCTION__);) + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvMFlashShutdownSet - Shutdown the voltage regulator in the flash device +* +* DESCRIPTION: +* Causes the device to enter in a power save mode untill the next access +* to the flash. +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashShutdownSet(MV_MFLASH_INFO *pFlash) +{ + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + return mvPMFlashShutdownSet(pFlash); + else if (pFlash->ifMode == MV_MFLASH_SPI) + return mvSMFlashShutdownSet(pFlash); + + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvMFlashIdGet - Retreive the MFlash's manufacturer and device IDs +* +* DESCRIPTION: +* Read from the flash the 32bit manufacturer Id and the 16bit device ID +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* pManfId: pointer to the 32bit variable to read the manufacturer ID in +* pDevId: pointer to the 16bit variable to read the device ID in +* +* OUTPUT: +* pManfId: pointer to the 32bit variable holding the manufacturer ID +* pDevId: pointer to the 16bit variable holding the device ID +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashIdGet (MV_MFLASH_INFO *pFlash, MV_U32 * pManfId, MV_U16 * pDevId) +{ + /* check for NULL pointer */ + if ((pFlash == NULL) || (pManfId == NULL) || (pDevId == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlash->ifMode == MV_MFLASH_PARALLEL) + return mvPMFlashIdGet(pFlash, pManfId, pDevId); + else if (pFlash->ifMode == MV_MFLASH_SPI) + return mvSMFlashIdGet(pFlash, pManfId, pDevId); + + mvOsPrintf("%s ERROR: Invalid interface mode!\n", __FUNCTION__); + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvMFlashReset - Reset the flash device and the MFlash glue logic +* +* DESCRIPTION: +* Perfom a hard reset for the Marvell Flash and the controller interface +* +* INPUT: +* pFlash: pointer to the MFlash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvMFlashReset(MV_MFLASH_INFO *pFlash) +{ + MV_U32 reg; + + /* check for NULL pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* set both bits 4 and 5 */ + reg = MV_REG_READ(MV_PMFLASH_IF_CFG_REG); + reg |= (MV_PMFLASH_RESET_MASK | MV_PMFLASH_IF_RESET_MASK); + MV_REG_WRITE(MV_PMFLASH_IF_CFG_REG, reg); + + /* Insert a short delay */ + mvOsDelay(1); /* 1ms */ + + /* reset both bits 4 and 5 */ + reg = MV_REG_READ(MV_PMFLASH_IF_CFG_REG); + reg &= ~(MV_PMFLASH_RESET_MASK | MV_PMFLASH_IF_RESET_MASK); + MV_REG_WRITE(MV_PMFLASH_IF_CFG_REG, reg); + + return MV_OK; +} + + + diff --git a/board/mv_feroceon/mv_hal/mflash/mvMFlash.h b/board/mv_feroceon/mv_hal/mflash/mvMFlash.h new file mode 100644 index 0000000..3fdc265 --- /dev/null +++ b/board/mv_feroceon/mv_hal/mflash/mvMFlash.h @@ -0,0 +1,141 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvMFlashH +#define __INCmvMFlashH + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* enumerations */ +typedef enum +{ + MV_MFLASH_MODEL_UNKNOWN = 0, + MV_MFLASH_SUNOL_1 = 1, + MV_MFLASH_SUNOL_2 = 2, + MV_MFLASH_SUNOL_3 = 3 +} MV_MFLASH_MODEL; + +typedef enum +{ + MV_MFLASH_SPI, + MV_MFLASH_PARALLEL +} MV_MFLASH_MODE; + +/* Type Definitions */ +typedef struct +{ + MV_MFLASH_MODE ifMode; /* Interface mode to the MFlash chip */ + MV_U32 baseAddr; /* Flash Base Address */ + MV_MFLASH_MODEL flashModel; /* Marvell flash model enumeration */ + MV_U32 sectorSize; /* Size of each sector in the main region */ + MV_U32 sectorNumber; /* Number of sectors in Main region */ + MV_U32 infoSize; /* Size of the Information region */ +} MV_MFLASH_INFO; + +/* Function Prototypes */ + +/* Init */ +MV_STATUS mvMFlashInit (MV_MFLASH_INFO *pFlash); + +/* Erase */ +MV_STATUS mvMFlashChipErase (MV_MFLASH_INFO *pFlash); /* Erase the whole chip */ +MV_STATUS mvMFlashMainErase (MV_MFLASH_INFO *pFlash); /* Erase the whole main region */ +MV_STATUS mvMFlashInfErase (MV_MFLASH_INFO *pFlash); /* Erase the whole information region */ +MV_STATUS mvMFlashSecErase (MV_MFLASH_INFO *pFlash, MV_U32 secNumber); /* Single Main sector erase */ + +/* write to main and information regions regardless of allignment */ +MV_STATUS mvMFlashBlockWr (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, MV_U8 *pBlock, MV_BOOL verify); +MV_STATUS mvMFlashInfBlockWr (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, MV_U8 *pBlock, MV_BOOL verify); + +/* read from main and information regions */ +MV_STATUS mvMFlashBlockRd (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, MV_U8 *pBlock); +MV_STATUS mvMFlashBlockInfRd (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, MV_U8 *pBlock); + +/* Configuration registers Read/Write */ +MV_STATUS mvMFlashReadConfig (MV_MFLASH_INFO *pFlash, MV_U32 regNum, MV_U8 * pConfigReg); +MV_STATUS mvMFlashSetConfig (MV_MFLASH_INFO *pFlash, MV_U32 regNum, MV_U8 configReg); +MV_STATUS mvMFlashSetSlewRate (MV_MFLASH_INFO *pFlash, MV_U8 configReg); + +/* write protection */ +MV_STATUS mvMFlashWriteProtectSet (MV_MFLASH_INFO *pFlash, MV_BOOL wp); +MV_STATUS mvMFlashWriteProtectGet (MV_MFLASH_INFO *pFlash, MV_BOOL * pWp); + +/* Set the Sector Size option */ +MV_STATUS mvMFlashSectorSizeSet (MV_MFLASH_INFO *pFlash, MV_U32 secSize); + +/* Prefetch Operation Set */ +MV_STATUS mvMFlashPrefetchSet (MV_MFLASH_INFO *pFlash, MV_BOOL prefetch); + +/* Shutdown/operate (true/false) the device */ +MV_STATUS mvMFlashShutdownSet (MV_MFLASH_INFO *pFlash); + +/* Retreive the Flash ID */ +MV_STATUS mvMFlashIdGet (MV_MFLASH_INFO *pFlash, MV_U32 * pManfId, MV_U16 * pDevId); + +/* Peform a hard reset to the MFlash and Interface glue */ +MV_STATUS mvMFlashReset (MV_MFLASH_INFO *pFlash); + +#endif /* __INCmvPMFlashH */ diff --git a/board/mv_feroceon/mv_hal/mflash/mvMFlashSpec.h b/board/mv_feroceon/mv_hal/mflash/mvMFlashSpec.h new file mode 100644 index 0000000..de4ea9c --- /dev/null +++ b/board/mv_feroceon/mv_hal/mflash/mvMFlashSpec.h @@ -0,0 +1,103 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvMFlashSpecH +#define __INCmvMFlashSpecH + +/* Information and Main region sizes per sunol model */ +#define MV_MFLASH_INF_MEM_SZ_SUNOL_1 0x400 /* 1Kbyte */ +#define MV_MFLASH_INF_MEM_SZ_SUNOL_2_3 0x800 /* 2Kbyte */ +#define MV_MFLASH_MAIN_MEM_SZ_SUNOL_1 0x30000 /* 192 Kbyte */ +#define MV_MFLASH_MAIN_MEM_SZ_SUNOL_2 0x40000 /* 256 KByte */ +#define MV_MFLASH_MAIN_MEM_SZ_SUNOL_3 0x60000 /* 384 KByte */ + +/* maunfacturer and Device IDs */ +#define MV_MFLASH_MANUFACTURER_ID 0x7F7F7FE9 /* Marvell Semiconductors Manufacturer ID */ +#define MV_MFLASH_DEVICE_ID_SUNOL_1 0x0290 /* LS nibble is the revision */ +#define MV_MFLASH_DEVICE_ID_SUNOL_2 0x02A0 /* LS nibble is the revision */ +#define MV_MFLASH_DEVICE_ID_SUNOL_3 0x02D0 /* LS nibble is the revision */ +#define MV_MFLASH_DEVICE_ID_MASK 0xFFF0 /* mask for the device ID */ +#define MV_MFLASH_DEVICE_ID_REV_MASK 0x000F /* revision part of the device ID */ + +/* SUNOL sector Sizes */ +#define MV_MFLASH_SECTOR_SIZE_SMALL 0x1000 /* 4KByte */ +#define MV_MFLASH_SECTOR_SIZE_BIG 0x8000 /* 32KByte */ + +/* SUNOL sectors number */ +#define MV_MFLASH_SMALL_SEC_NUM_SUNOL_1 (MV_MFLASH_MAIN_MEM_SZ_SUNOL_1 / MV_MFLASH_SECTOR_SIZE_SMALL) /* 48 */ +#define MV_MFLASH_SMALL_SEC_NUM_SUNOL_2 (MV_MFLASH_MAIN_MEM_SZ_SUNOL_2 / MV_MFLASH_SECTOR_SIZE_SMALL) /* 64 */ +#define MV_MFLASH_SMALL_SEC_NUM_SUNOL_3 (MV_MFLASH_MAIN_MEM_SZ_SUNOL_3 / MV_MFLASH_SECTOR_SIZE_SMALL) /* 96 */ +#define MV_MFLASH_BIG_SEC_NUM_SUNOL_1 (MV_MFLASH_MAIN_MEM_SZ_SUNOL_1 / MV_MFLASH_SECTOR_SIZE_BIG) /* 6 */ +#define MV_MFLASH_BIG_SEC_NUM_SUNOL_2 (MV_MFLASH_MAIN_MEM_SZ_SUNOL_2 / MV_MFLASH_SECTOR_SIZE_BIG) /* 8 */ +#define MV_MFLASH_BIG_SEC_NUM_SUNOL_3 (MV_MFLASH_MAIN_MEM_SZ_SUNOL_3 / MV_MFLASH_SECTOR_SIZE_BIG) /* 12 */ + +/* Loops Timeouts */ +#define MV_MFLASH_MAX_CMD_DONE_LOOP 1000000 /* max poll times to wait for the comamnd done */ +#define MV_MFLASH_MAX_PRG_LOOP 1000000 /* max poll times to wait for programming to be completed */ + +/* Page allignment and Mask */ +#define MV_MFLASH_PROG_ALIGN_MASK 0x3f /* PROG should be alligned to 64 bytes */ +#define MV_MFLASH_PROG_CHUNK_SIZE (MV_MFLASH_PROG_ALIGN_MASK + 1) + +#endif /* __INCmvMFlashSpecH */ diff --git a/board/mv_feroceon/mv_hal/mflash/mvPMFlash.c b/board/mv_feroceon/mv_hal/mflash/mvPMFlash.c new file mode 100644 index 0000000..c795161 --- /dev/null +++ b/board/mv_feroceon/mv_hal/mflash/mvPMFlash.c @@ -0,0 +1,1426 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mflash/mvMFlash.h" +#include "mflash/mvMFlashSpec.h" +#include "mflash/mvPMFlash.h" +#include "mflash/mvPMFlashSpec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +/*#define MV_DEBUG*/ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* MACROS */ + +/* Static Functions */ +static MV_STATUS waitOnCmdDone (MV_VOID); +static MV_STATUS waitOnEraseBitClear (MV_VOID); +static MV_STATUS waitOnInfReadBitClear (MV_VOID); +static MV_STATUS mvPMFlashReadSR (MV_U8 * pStatusReg); +static MV_STATUS mvPMFlashReadRegSeq (MV_U32 prgCmnd, MV_U8 * pStatusReg); +static MV_STATUS mvPMFlashWriteRegSeq (MV_U32 prgCmnd, MV_U32 reg); +static MV_STATUS mvPMFlashProgSeq (MV_MFLASH_INFO *pFlash, MV_U32 prgCmnd, MV_U32 offset, MV_U8 *pBlock); +static MV_STATUS mvPMFlashEraseSeq (MV_MFLASH_INFO *pFlash, MV_U32 eraseCmnd); +static MV_STATUS mvPMFlashIndirectReadSeq (MV_MFLASH_INFO *pFlash, MV_U32 readCmnd, MV_U8* p8Bytes); + +/******************************************************************************* +* waitOnCmdDone - Wait for command done bit +* +* DESCRIPTION: +* Block waiting for command done. Returns Error Status +* +********************************************************************************/ +static MV_STATUS waitOnCmdDone(MV_VOID) +{ + MV_U32 i; + /* loop over waiting for the command done bit to be set */ + for (i=0; i> 16) & 0xFFFF)); + + /* set commnand opcode = prgCmnd */ + temp = MV_REG_READ(MV_PMFLASH_CMD_OPCODE_REG); + temp = ((temp & ~MV_PMFLASH_CMD_OPCD_MASK) | prgCmnd | MV_PMFLASH_EAD9_8_MASK); + MV_REG_WRITE(MV_PMFLASH_CMD_OPCODE_REG, temp); + + /* start the programming operation - set bit 12 to 1 */ + MV_REG_BIT_SET(MV_PMFLASH_CMD_OPCODE_REG, MV_PMFLASH_WR_OPER_STRT_MASK); + + /* serialize the whole 64 byte buffer */ + pBuff = (MV_U16*)pBlock; + for (i=0; i (pFlash->sectorNumber * pFlash->sectorSize)) + { + DB(mvOsPrintf("%s WARNING: Read allignment problem!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* Read using direct access */ + mvOsMemcpy(pBlock, (MV_VOID*)(pFlash->baseAddr + offset), blockSize); + + return MV_OK; +} + +/******************************************************************************* +* mvPMFlashBlockInfRd - Read a block of Memory from the Information region +* +* DESCRIPTION: +* Read a block of Memory from the information region +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* offset: offset to read from the main region of the MFlash +* blockSize: number of bytes to read from the offset +* +* OUTPUT: +* pBlock: pointer of the buffer to fill +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvPMFlashBlockInfRd (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, + MV_U8 *pBlock) +{ + MV_STATUS ret; + MV_U8 tempBuff[MV_PMFLASH_IREAD_CHUNK_SIZE]; + MV_U32 data2read = blockSize; + MV_U32 preAllOfst = (offset & MV_PMFLASH_IREAD_ALIGN_MASK); + MV_U32 preAllSz = (preAllOfst ? (MV_PMFLASH_IREAD_CHUNK_SIZE - preAllOfst) : 0); + MV_U32 readOffset = (offset & ~MV_PMFLASH_IREAD_ALIGN_MASK); + + /* Check for null pointer */ + if ((pFlash == NULL) || (pBlock == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* sanity check on sizes and offsets based on chip model */ + if ((offset + blockSize) > pFlash->infoSize) + { + DB(mvOsPrintf("%s WARNING: Read exceeds flash size!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* set the ADDDRESS HI to zero - since only the low address is needed */ + MV_REG_WRITE(MV_PMFLASH_ADDR_HI_REG, 0); /* only low address is needed */ + + /* check if the total block size is less than the first chunk remainder */ + if (data2read < preAllSz) + preAllSz = data2read; + + /* Check if read offset is not alligned to 8bytes; then perform a read alligned + to 8 bytes and copy only the necessary data */ + if (preAllOfst) + { + /* set the read offset address in the flash address Low */ + MV_REG_WRITE(MV_PMFLASH_ADDR_LOW_REG, readOffset); + if ((ret = mvPMFlashIndirectReadSeq(pFlash, MV_PMFLASH_OPCD_IREAD, tempBuff)) != MV_OK) + return ret; + + /* copy to the buffer only the needed data */ + mvOsMemcpy (pBlock, &tempBuff[preAllOfst], preAllSz); + + /* increment the pointers and offsets */ + data2read -= preAllSz; + readOffset += MV_PMFLASH_IREAD_CHUNK_SIZE; + pBlock += preAllSz; + } + + /* perform all reads that are alligned to 8bytes and full 8bytes */ + while (data2read >= MV_PMFLASH_IREAD_CHUNK_SIZE) + { + /* set the read offset address in the flash address Low */ + MV_REG_WRITE(MV_PMFLASH_ADDR_LOW_REG, readOffset); + if ((ret = mvPMFlashIndirectReadSeq(pFlash, MV_PMFLASH_OPCD_IREAD, pBlock)) != MV_OK) + return ret; + + /* increment the pointers and offsets */ + data2read -= MV_PMFLASH_IREAD_CHUNK_SIZE; + readOffset += MV_PMFLASH_IREAD_CHUNK_SIZE; + pBlock += MV_PMFLASH_IREAD_CHUNK_SIZE; + } + + /* check if we need to perform a partial read at the end */ + if (data2read) + { + /* set the read offset address in the flash address Low */ + MV_REG_WRITE(MV_PMFLASH_ADDR_LOW_REG, readOffset); + if ((ret = mvPMFlashIndirectReadSeq(pFlash, MV_PMFLASH_OPCD_IREAD, tempBuff)) != MV_OK) + return ret; + + /* copy to the buffer only the needed data */ + mvOsMemcpy (pBlock, tempBuff, data2read); + } + + return MV_OK; +} + +/******************************************************************************* +* mvPMFlashReadConfig1 - Read the Configuration register +* +* DESCRIPTION: +* Perform the Read CONFIG1 register RAB +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* pConfigReg: pointer to the variable to fill +* +* OUTPUT: +* pConfigReg: pointer to the variable holding the register value +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_STATUS mvPMFlashReadConfig1(MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg) +{ + if ((pFlash == NULL) || (pConfigReg == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvPMFlashReadRegSeq(MV_PMFLASH_OPCD_READ_CFG1, pConfigReg); +} + +/******************************************************************************* +* mvPMFlashReadConfig2 - Read the Configuration register +* +* DESCRIPTION: +* Perform the Read CONFIG2 register RAB +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* pConfigReg: pointer to the variable to fill +* +* OUTPUT: +* pConfigReg: pointer to the variable holding the register value +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_STATUS mvPMFlashReadConfig2(MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg) +{ + if ((pFlash == NULL) || (pConfigReg == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvPMFlashReadRegSeq(MV_PMFLASH_OPCD_READ_CFG2, pConfigReg); +} + +/******************************************************************************* +* mvPMFlashReadConfig3 - Read the Configuration register +* +* DESCRIPTION: +* Perform the Read CONFIG3 register RAB +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* pConfigReg: pointer to the variable to fill +* +* OUTPUT: +* pConfigReg: pointer to the variable holding the register value +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_STATUS mvPMFlashReadConfig3(MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg) +{ + if ((pFlash == NULL) || (pConfigReg == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvPMFlashReadRegSeq(MV_PMFLASH_OPCD_READ_CFG3, pConfigReg); +} + +/******************************************************************************* +* mvPMFlashReadConfig4 - Read the Configuration register +* +* DESCRIPTION: +* Perform the Read CONFIG4 register RAB +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* pConfigReg: pointer to the variable to fill +* +* OUTPUT: +* pConfigReg: pointer to the variable holding the register value +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_STATUS mvPMFlashReadConfig4(MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg) +{ + if ((pFlash == NULL) || (pConfigReg == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvPMFlashReadRegSeq(MV_PMFLASH_OPCD_READ_CFG4, pConfigReg); +} + +/******************************************************************************* +* mvPMFlashSetConfig1 - Write the Configuration register +* +* DESCRIPTION: +* Perform the SET CONFIG1 register RAB +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* configReg: value to set in the configuration register +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_STATUS mvPMFlashSetConfig1(MV_MFLASH_INFO *pFlash, MV_U8 configReg) +{ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvPMFlashWriteRegSeq(MV_PMFLASH_OPCD_SET_CFG1, configReg); +} + +/******************************************************************************* +* mvPMFlashSetConfig2 - Write the Configuration register +* +* DESCRIPTION: +* Perform the SET CONFIG2 register RAB +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* configReg: value to set in the configuration register +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_STATUS mvPMFlashSetConfig2(MV_MFLASH_INFO *pFlash, MV_U8 configReg) +{ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvPMFlashWriteRegSeq(MV_PMFLASH_OPCD_SET_CFG2, configReg); +} + +/******************************************************************************* +* mvPMFlashSetConfig3 - Write the Configuration register +* +* DESCRIPTION: +* Perform the SET CONFIG3 register RAB +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* configReg: value to set in the configuration register +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_STATUS mvPMFlashSetConfig3(MV_MFLASH_INFO *pFlash, MV_U8 configReg) +{ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvPMFlashWriteRegSeq(MV_PMFLASH_OPCD_SET_CFG3, configReg); +} + +/******************************************************************************* +* mvPMFlashSetConfig4 - Write the Configuration register +* +* DESCRIPTION: +* Perform the SET CONFIG4 register RAB +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* configReg: value to set in the configuration register +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_STATUS mvPMFlashSetConfig4(MV_MFLASH_INFO *pFlash, MV_U8 configReg) +{ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvPMFlashWriteRegSeq(MV_PMFLASH_OPCD_SET_CFG4, configReg); +} +/******************************************************************************* +* mvPMFlashSetConfig4 - Write the Configuration register +* +* DESCRIPTION: +* Perform the SET CONFIG4 register RAB +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* configReg: value to set in the configuration register +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_STATUS mvPMFlashSetSlewRate (MV_MFLASH_INFO *pFlash, MV_U8 configReg) +{ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvPMFlashWriteRegSeq(MV_PMFLASH_OPCD_SET_SLEW, configReg); +} + +/******************************************************************************* +* mvPMFlashWriteProtectSet - Set the write protection feature status +* +* DESCRIPTION: +* Enable or disable the write protection +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* wp: write protection status (enable = MV_TRUE, disable = MVFALSE) +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvPMFlashWriteProtectSet (MV_MFLASH_INFO *pFlash, MV_BOOL wp) +{ + MV_STATUS ret; + MV_U8 tempReg; + + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Read the original value */ + if ((ret = mvPMFlashReadConfig4(pFlash, &tempReg)) != MV_OK) + { + DB(mvOsPrintf("%s WARNING: Failed to read Config register!\n", __FUNCTION__);) + return ret; + } + + /* set the WP bit */ + if (wp) /* write protect active hi */ + tempReg |= MV_PMFLASH_CFG4_WP_MASK; + else + tempReg &= ~MV_PMFLASH_CFG4_WP_MASK; + + /* write the new register value */ + if ((ret = mvPMFlashSetConfig4(pFlash, tempReg)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvPMFlashWriteProtectGet - Get the write protection feature status +* +* DESCRIPTION: +* Read from the h/w the write protection status +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* pWp: pointer to the variable to read in the write protection status +* +* OUTPUT: +* pWp: pointer to the variable holding the write protection status +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvPMFlashWriteProtectGet(MV_MFLASH_INFO *pFlash, MV_BOOL * pWp) +{ + MV_STATUS ret; + MV_U8 tempReg; + + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Read the original value */ + if ((ret = mvPMFlashReadConfig4(pFlash, &tempReg)) != MV_OK) + { + DB(mvOsPrintf("%s WARNING: Failed to read Config register!\n", __FUNCTION__);) + return ret; + } + + /* Read the WP bit */ + if (tempReg &= ~MV_PMFLASH_CFG4_WP_MASK) + *pWp = MV_TRUE; + else + *pWp = MV_FALSE; + + return MV_OK; +} + +/******************************************************************************* +* mvPMFlashSectorSizeSet - Set the sector size (4K or 32K) +* +* DESCRIPTION: +* Set the sector size of the MFLASH main region +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* secSize: size of sector in bytes (either 4K or 32K) +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvPMFlashSectorSizeSet (MV_MFLASH_INFO *pFlash, MV_U32 secSize) +{ + MV_STATUS ret; + MV_U8 tempReg; + + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Read the original value */ + if ((ret = mvPMFlashReadConfig4(pFlash, &tempReg)) != MV_OK) + return ret; + + /* set the sector size bit */ + switch (secSize) + { + case MV_MFLASH_SECTOR_SIZE_SMALL: + tempReg |= MV_PMFLASH_CFG4_PG_SZ_MASK; /* 1 - 4K */ + break; + + case MV_MFLASH_SECTOR_SIZE_BIG: + tempReg &= ~MV_PMFLASH_CFG4_PG_SZ_MASK; /* 0 - 32K */ + break; + + default: + DB(mvOsPrintf("%s WARNING: Invalid parameter sector size!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* write the new register value */ + if ((ret = mvPMFlashSetConfig4(pFlash, tempReg)) != MV_OK) + return ret; + + return MV_OK; +} + + +/******************************************************************************* +* mvPMFlashPrefetchSet - Set the Prefetch mode enable/disable +* +* DESCRIPTION: +* Enable (MV_TRUE) or Disable (MV_FALSE) the prefetch mode +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* prefetch: enable/disable (true/false) +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvPMFlashPrefetchSet (MV_MFLASH_INFO *pFlash, MV_BOOL prefetch) +{ + MV_STATUS ret; + MV_U8 tempReg; + + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Read the original value */ + if ((ret = mvPMFlashReadConfig2(pFlash, &tempReg)) != MV_OK) + return ret; + + /* set the prefetch enable bit */ + if (prefetch) + tempReg |= MV_PMFLASH_CFG2_PRFTCH_MASK; /* prefetch mode active HI */ + else + tempReg &= ~MV_PMFLASH_CFG2_PRFTCH_MASK; + + /* write the new register value */ + if ((ret = mvPMFlashSetConfig2(pFlash, tempReg)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvPMFlashShutdownSet - Shutdown the voltage regulator in the flash device +* +* DESCRIPTION: +* Causes the device to enter in a power save mode untill the next access +* to the flash. +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvPMFlashShutdownSet(MV_MFLASH_INFO *pFlash) +{ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvPMFlashEraseSeq(pFlash, MV_PMFLASH_OPCD_SHUTDOWN); +} + +/******************************************************************************* +* mvPMFlashIdGet - Retreive the MFlash manufacturer and device IDs +* +* DESCRIPTION: +* Read from the Mflash the 32bit manufacturer ID and the 16bit devide Id. +* +* INPUT: +* pFlash: Structure with Marvell Flash information +* pManfCode: pointer to the 32bit to fill the manufacturer Id +* pDevCode: pointer to the 16bit to fill the device Id +* +* OUTPUT: +* pManfCode: pointer to the 32bit holding the manufacturer Id +* pDevCode: pointer to the 16bit holding the device Id +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvPMFlashIdGet (MV_MFLASH_INFO *pFlash, MV_U32 * pManfCode, MV_U16 * pDevCode) +{ + MV_U32 temp; + MV_STATUS ret; + + if ((pFlash == NULL) || (pManfCode == NULL) || (pDevCode == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* first confiure the Inf Read Data length = 3 (i.e 3*16bit = 6bytes) + This is because we need to read 6 bytes (4bytes Manuf. ID and 2 bytes Dev ID) */ + MV_REG_WRITE(MV_PMFLASH_IF_CTRL_REG, MV_PMFLASH_READ_ID_16BIT_COUNT); + + /* set commnand opcode = prgCmnd */ + temp = MV_REG_READ(MV_PMFLASH_CMD_OPCODE_REG); + temp = ((temp & ~MV_PMFLASH_CMD_OPCD_MASK) | MV_PMFLASH_OPCD_READ_ID | MV_PMFLASH_EAD9_8_MASK); + MV_REG_WRITE(MV_PMFLASH_CMD_OPCODE_REG, temp); + + /* Trigger the erase operation - set bit 13 to 1 */ + MV_REG_BIT_SET(MV_PMFLASH_CMD_OPCODE_REG, MV_PMFLASH_INF_READ_STRT_MASK); + + /* block waiting for bit to be cleared by hardware */ + if ((ret = waitOnInfReadBitClear()) != MV_OK) + return ret; + + /* read the 6bytes from the Data register into the buffer in 3 iterations */ + /* First re-organize the Manufacturer ID */ + *pManfCode = 0; + temp = MV_REG_READ(MV_PMFLASH_DATA_REG); /* First 16bit */ + *pManfCode |= ((temp << 24) & 0xFF000000); + *pManfCode |= ((temp << 8) & 0x00FF0000); + temp = MV_REG_READ(MV_PMFLASH_DATA_REG); /* Second 16bit */ + *pManfCode |= ((temp << 8) & 0x0000FF00); + *pManfCode |= ((temp >> 8) & 0x000000FF); + + /* Then re-organize the Device ID */ + *pDevCode = 0; + temp = MV_REG_READ(MV_PMFLASH_DATA_REG); /* Third 16bit */ + *pDevCode |= ((temp << 8) & 0x0000FF00); + *pDevCode |= ((temp >> 8) & 0x000000FF); + + /* Set the word count back to the defualt for IREAD commands = 4*16bit */ + MV_REG_WRITE(MV_PMFLASH_IF_CTRL_REG, MV_PMFLASH_IREAD_16BIT_COUNT); + + return MV_OK; +} + + diff --git a/board/mv_feroceon/mv_hal/mflash/mvPMFlash.h b/board/mv_feroceon/mv_hal/mflash/mvPMFlash.h new file mode 100644 index 0000000..33d0aec --- /dev/null +++ b/board/mv_feroceon/mv_hal/mflash/mvPMFlash.h @@ -0,0 +1,120 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvPMFlashH +#define __INCmvPMFlashH + +#include "mvMFlash.h" + +/* Parallel mode function prototypes */ + +/* Init */ +MV_STATUS mvPMFlashInit (MV_MFLASH_INFO *pFlash); + +/* Erase */ +MV_STATUS mvPMFlashChipErase (MV_MFLASH_INFO *pFlash); /* Erase the whole chip */ +MV_STATUS mvPMFlashMainErase (MV_MFLASH_INFO *pFlash); /* Erase the whole main region */ +MV_STATUS mvPMFlashInfErase (MV_MFLASH_INFO *pFlash); /* Erase the whole information region */ +MV_STATUS mvPMFlashSecErase (MV_MFLASH_INFO *pFlash, MV_U32 secNumber); /* Single Main sector erase */ + +/* write */ +MV_STATUS mvPMFlash64bWr (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock); +MV_STATUS mvPMFlash64bWrVerify (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock); +MV_STATUS mvPMFlash64bInfWr (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock); +MV_STATUS mvPMFlash64bInfWrVerify (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock); + +/* Read */ +MV_STATUS mvPMFlashBlockRd (MV_MFLASH_INFO *pFlash, MV_U32 offset, \ + MV_U32 blockSize, MV_U8 *pBlock); +MV_STATUS mvPMFlashBlockInfRd (MV_MFLASH_INFO *pFlash, MV_U32 offset, \ + MV_U32 blockSize, MV_U8 *pBlock); + +/* Configuration registers Read/Write */ +MV_STATUS mvPMFlashReadConfig1 (MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg); +MV_STATUS mvPMFlashReadConfig2 (MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg); +MV_STATUS mvPMFlashReadConfig3 (MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg); +MV_STATUS mvPMFlashReadConfig4 (MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg); +MV_STATUS mvPMFlashSetConfig1 (MV_MFLASH_INFO *pFlash, MV_U8 configReg); +MV_STATUS mvPMFlashSetConfig2 (MV_MFLASH_INFO *pFlash, MV_U8 configReg); +MV_STATUS mvPMFlashSetConfig3 (MV_MFLASH_INFO *pFlash, MV_U8 configReg); +MV_STATUS mvPMFlashSetConfig4 (MV_MFLASH_INFO *pFlash, MV_U8 configReg); +MV_STATUS mvPMFlashSetSlewRate (MV_MFLASH_INFO *pFlash, MV_U8 configReg); + +/* write protection */ +MV_STATUS mvPMFlashWriteProtectSet(MV_MFLASH_INFO *pFlash, MV_BOOL wp); +MV_STATUS mvPMFlashWriteProtectGet(MV_MFLASH_INFO *pFlash, MV_BOOL * pWp); + +/* Set the Sector Size option */ +MV_STATUS mvPMFlashSectorSizeSet (MV_MFLASH_INFO *pFlash, MV_U32 secSize); + +/* Prefetch Operation Set */ +MV_STATUS mvPMFlashPrefetchSet (MV_MFLASH_INFO *pFlash, MV_BOOL prefetch); + +/* Shutdown/operate (true/false) the device */ +MV_STATUS mvPMFlashShutdownSet (MV_MFLASH_INFO *pFlash); + +/* Retreive the Flash ID */ +MV_STATUS mvPMFlashIdGet (MV_MFLASH_INFO *pFlash, MV_U32 * pManfCode, MV_U16 * pDevCode); + +#endif /* __INCmvPMFlashH */ diff --git a/board/mv_feroceon/mv_hal/mflash/mvPMFlashSpec.h b/board/mv_feroceon/mv_hal/mflash/mvPMFlashSpec.h new file mode 100644 index 0000000..5bdb145 --- /dev/null +++ b/board/mv_feroceon/mv_hal/mflash/mvPMFlashSpec.h @@ -0,0 +1,178 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvPMFlashSpecH +#define __INCmvPMFlashSpecH + +#include "mvMFlashSpec.h" + +/* default values for the timing registers */ +#define MV_PMFLASH_T1 0x7 /* Read Access Time T1 – sunol2 default */ +#define MV_PMFLASH_T2 0x7 /* Read Access Time T2 – sunol2 default */ +#define MV_PMFLASH_T7 0x29 /* Divider Number for T7 – sunol2 default */ +#define MV_PMFLASH_PCLK_OUT 0x0 /* Hold Time between reference clock and PCLK */ +#define MV_PMFLASH_SLEW_0_1 0x2 /* slew rate for PCLK_OUT bits 0-1 */ +#define MV_PMFLASH_SLEW_2_3 0x3 /* slew rate for PCLK_OUT bits 2-3 */ + +/* Programming allignment mask */ +#define MV_PMFLASH_PROG_WORDS_PER_CHUNK (MV_MFLASH_PROG_CHUNK_SIZE / 2) + +/* IRead Allignmet definitions */ +#define MV_PMFLASH_IREAD_ALIGN_MASK 0x0007 /* IREAD should be alligned to 8bytes */ +#define MV_PMFLASH_IREAD_CHUNK_SIZE (MV_PMFLASH_IREAD_ALIGN_MASK + 1) + +/* wrod count for the Indirect read commands (IREAD and READ ID) */ +#define MV_PMFLASH_IREAD_16BIT_COUNT 0x4 /* 8 bytes per IREAD command */ +#define MV_PMFLASH_READ_ID_16BIT_COUNT 0x3 /* 6 bytes = 4 manf ID + 2 Dev ID */ + +/* MFlash command opcodes */ +#define MV_PMFLASH_OPCD_PROGRAM 0x02 +#define MV_PMFLASH_OPCD_PRG_CMP 0x07 +#define MV_PMFLASH_OPCD_IPROGRAM 0x82 +#define MV_PMFLASH_OPCD_IPRG_CMP 0x87 +#define MV_PMFLASH_OPCD_PAGE_ERASE 0x52 +#define MV_PMFLASH_OPCD_IPAGE_ERASE 0xD2 +#define MV_PMFLASH_OPCD_CHIP_ERASE 0xE2 +#define MV_PMFLASH_OPCD_MAIN_ERASE 0x62 +#define MV_PMFLASH_OPCD_RDSR 0x05 +#define MV_PMFLASH_OPCD_IREAD 0x83 +#define MV_PMFLASH_OPCD_SET_CFG1 0xB0 +#define MV_PMFLASH_OPCD_SET_CFG2 0xB1 +#define MV_PMFLASH_OPCD_SET_CFG3 0xB2 +#define MV_PMFLASH_OPCD_SET_CFG4 0xB3 +#define MV_PMFLASH_OPCD_READ_CFG1 0xB4 +#define MV_PMFLASH_OPCD_READ_CFG2 0xB5 +#define MV_PMFLASH_OPCD_READ_CFG3 0xB6 +#define MV_PMFLASH_OPCD_READ_CFG4 0xB7 +#define MV_PMFLASH_OPCD_SHUTDOWN 0xA4 +#define MV_PMFLASH_OPCD_SET_SLEW 0xA5 +#define MV_PMFLASH_OPCD_READ_ID 0x15 + +/* Marvell Flash Device Controller Registers */ +#define MV_PMFLASH_CTRLR_OFST 0x10500 +#define MV_PMFLASH_IF_CTRL_REG (MV_PMFLASH_CTRLR_OFST + 0x00) +#define MV_PMFLASH_IF_CFG_REG (MV_PMFLASH_CTRLR_OFST + 0x04) +#define MV_PMFLASH_ADDR_LOW_REG (MV_PMFLASH_CTRLR_OFST + 0x08) +#define MV_PMFLASH_ADDR_HI_REG (MV_PMFLASH_CTRLR_OFST + 0x0c) +#define MV_PMFLASH_CMD_OPCODE_REG (MV_PMFLASH_CTRLR_OFST + 0x10) +#define MV_PMFLASH_IF_STATUS_REG (MV_PMFLASH_CTRLR_OFST + 0x14) +#define MV_PMFLASH_STATUS_REG (MV_PMFLASH_CTRLR_OFST + 0x18) +#define MV_PMFLASH_DATA_REG (MV_PMFLASH_CTRLR_OFST + 0x20) + +/* Flash Interface configuration */ +#define MV_PMFLASH_SERIAL_MODE_OFFSET 0 /* bit 0 */ +#define MV_PMFLASH_RESET_OFFSET 4 /* bit 4 */ +#define MV_PMFLASH_IF_RESET_OFFSET 5 /* bit 5 */ +#define MV_PMFLASH_WP_PROTECT_OFFSET 6 /* bit 6 */ +#define MV_PMFLASH_EXT_FLASH_OFFSET 12 /* bit 12 */ +#define MV_PMFLASH_EXT_PROGRAMMER_OFFSET 13 /* bit 13 */ +#define MV_PMFLASH_SERIAL_MODE_MASK (0x1 << MV_PMFLASH_SERIAL_MODE_OFFSET) +#define MV_PMFLASH_RESET_MASK (0x1 << MV_PMFLASH_RESET_OFFSET) +#define MV_PMFLASH_IF_RESET_MASK (0x1 << MV_PMFLASH_IF_RESET_OFFSET) +#define MV_PMFLASH_WP_PROTECT_MASK (0x1 << MV_PMFLASH_WP_PROTECT_OFFSET) +#define MV_PMFLASH_EXT_FLASH_MASK (0x1 << MV_PMFLASH_EXT_FLASH_OFFSET) +#define MV_PMFLASH_EXT_PROGRAMMER_MASK (0x1 << MV_PMFLASH_EXT_PROGRAMMER_OFFSET) + +#define MV_PMFLASH_SPI_BUS_MODE_MASK (MV_PMFLASH_SERIAL_MODE_MASK | MV_PMFLASH_EXT_FLASH_MASK | MV_PMFLASH_EXT_PROGRAMMER_MASK) +#define MV_PMFLASH_SPI_BUS_TO_MFLASH 0x1001 +#define MV_PMFLASH_SPI_BUS_TO_EXT_SFLASH 0x0000 +#define MV_PMFLASH_SPI_BUS_EXT_PROGRAMER 0x2001 + +/* Command Opcode Register Masks */ +#define MV_PMFLASH_CMD_OPCD_OFFSET 0 /* bits 0-7 */ +#define MV_PMFLASH_EAD9_8_OFFSET 8 /* bit 8 */ +#define MV_PMFLASH_WR_OPER_STRT_OFFSET 12 /* bit 12 */ +#define MV_PMFLASH_ERASE_STRT_OFFSET 13 /* bit 13 */ +#define MV_PMFLASH_RDSR_SET_OFFSET 14 /* bit 14 */ +#define MV_PMFLASH_INF_READ_STRT_OFFSET 15 /* bit 15 */ +#define MV_PMFLASH_EAD9_8_MASK (0x3 << MV_PMFLASH_EAD9_8_OFFSET) +#define MV_PMFLASH_CMD_OPCD_MASK (0xFF << MV_PMFLASH_CMD_OPCD_OFFSET) +#define MV_PMFLASH_WR_OPER_STRT_MASK (0x1 << MV_PMFLASH_WR_OPER_STRT_OFFSET) +#define MV_PMFLASH_ERASE_STRT_MASK (0x1 << MV_PMFLASH_ERASE_STRT_OFFSET) +#define MV_PMFLASH_RDSR_SET_MASK (0x1 << MV_PMFLASH_RDSR_SET_OFFSET) +#define MV_PMFLASH_INF_READ_STRT_MASK (0x1 << MV_PMFLASH_INF_READ_STRT_OFFSET) + +/* Flash Interface Status Register Masks */ +#define MV_PMFLASH_CMD_DONE_OFFSET 0 /* bit 0 */ +#define MV_PMFLASH_CMD_DONE_MASK (0x1 << MV_PMFLASH_CMD_DONE_OFFSET) + +/* Flash Status Register Masks */ +#define MV_PMFLASH_STATUS_OFFSET 0 /* bits 0-7 */ +#define MV_PMFLASH_STAT_WIP_OFFSET 0 /* bit 0 */ +#define MV_PMFLASH_STAT_CMP_OFFSET 6 /* bit 6 */ +#define MV_PMFLASH_STATUS_MASK (0xFF << MV_PMFLASH_STATUS_OFFSET) +#define MV_PMFLASH_STAT_WIP_MASK (0x1 << MV_PMFLASH_STAT_WIP_OFFSET) +#define MV_PMFLASH_STAT_CMP_MASK (0x1 << MV_PMFLASH_STAT_CMP_OFFSET) + +/* MFlash CONFIG4 register bit Masks */ +#define MV_PMFLASH_CFG4_PG_SZ_OFFSET 0 /* bit 0 */ +#define MV_PMFLASH_CFG4_WP_OFFSET 7 /* bit 7 */ +#define MV_PMFLASH_CFG4_PG_SZ_MASK (0x1 << MV_PMFLASH_CFG4_PG_SZ_OFFSET) +#define MV_PMFLASH_CFG4_WP_MASK (0x1 << MV_PMFLASH_CFG4_WP_OFFSET) + +/* MFlash CONFIG2 register bit Masks */ +#define MV_PMFLASH_CFG2_PRFTCH_OFFSET 7 /* bit 7 */ +#define MV_PMFLASH_CFG2_PRFTCH_MASK (0x1 << MV_PMFLASH_CFG2_PRFTCH_OFFSET) + +#endif /* __INCmvPMFlashSpecH */ diff --git a/board/mv_feroceon/mv_hal/mflash/mvSMFlash.c b/board/mv_feroceon/mv_hal/mflash/mvSMFlash.c new file mode 100644 index 0000000..9ac4eea --- /dev/null +++ b/board/mv_feroceon/mv_hal/mflash/mvSMFlash.c @@ -0,0 +1,1076 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mflash/mvSMFlash.h" +#include "mflash/mvSMFlashSpec.h" +#include "mflash/mvMFlash.h" +#include "mflash/mvMFlashSpec.h" +#include "spi/mvSpi.h" +#include "spi/mvSpiCmnd.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +/*#define MV_DEBUG*/ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* Static Functions */ +static MV_STATUS mvSingleByteCmnd (MV_U8 opcode); +static MV_STATUS mvSingleByteRead (MV_U8 opcode, MV_U8* pData); +static MV_STATUS mvSingleByteWrite (MV_U8 opcode, MV_U8 data); +static MV_STATUS mvWriteEnable (MV_VOID); +static MV_STATUS mvStatusRegGet (MV_U8* pStatus); +static MV_STATUS mvWaitOnWipClear (MV_VOID); + +/******************************************************************************* +* mvSingleByteCmnd - Issue an 8bit commmand +* +* DESCRIPTION: +* serialize an 8bit command without any data +* +********************************************************************************/ +static MV_STATUS mvSingleByteCmnd(MV_U8 opcode) +{ + MV_U8 cmd[1]; + cmd[0] = opcode; + return mvSpiWriteThenRead(cmd, 1, NULL, 0,0); +} + +/******************************************************************************* +* mvSingleByteCmnd - Issue an 8bit Read +* +* DESCRIPTION: +* serialize an 8bit command and read 8bits of data +* +********************************************************************************/ +static MV_STATUS mvSingleByteRead(MV_U8 opcode, MV_U8* pData) +{ + MV_U8 cmd[1]; + cmd[0] = opcode; + return mvSpiWriteThenRead(cmd, 1, pData, 1,0); +} + +/******************************************************************************* +* mvSingleByteWrite - Issue an 8bit Write +* +* DESCRIPTION: +* serialize an 8bit command and 8bits of data +* +********************************************************************************/ +static MV_STATUS mvSingleByteWrite(MV_U8 opcode, MV_U8 data) +{ + return mvSpiWriteThenWrite(&opcode, 1, &data, 1); +} + +/******************************************************************************* +* mvWriteEnable - Perform the write enable sequence +* +* DESCRIPTION: +* Writa enable sequence needed before program and erase commands +* +********************************************************************************/ +static MV_STATUS mvWriteEnable(MV_VOID) +{ + return mvSingleByteCmnd(MV_SMFLASH_WREN_CMND_OPCD); +} + +/******************************************************************************* +* mvStatusRegGet - Retreiv the value of the status register +* +* DESCRIPTION: +* perform the RDSR sequence to get the 8bit status register +* +********************************************************************************/ +static MV_STATUS mvStatusRegGet(MV_U8* pStatus) +{ + return mvSingleByteRead(MV_SMFLASH_RDSR_CMND_OPCD, pStatus); +} + +/******************************************************************************* +* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared +* +* DESCRIPTION: +* Block waiting for the WIP (write in progress) to be cleared +* +********************************************************************************/ +static MV_STATUS mvWaitOnWipClear(MV_VOID) +{ + MV_STATUS ret; + MV_U32 i; + MV_U8 status; + + for (i=0; i> 16) & 0xFF); /* address bits 16 - 23 */ + cmd[2] = ((secAddr >> 8) & 0xFF); /* address bits 8 - 15 */ + cmd[3] = (secAddr & 0xFF); /* address bits 0 - 7 */ + + /* Perform the write enable sequence */ + if ((ret = mvWriteEnable()) != MV_OK) + return ret; + + if ((ret = mvSpiWriteThenRead(cmd, MV_SMFLASH_PAGE_ERASE_CMND_LEN, NULL, 0, 0)) != MV_OK) + return ret; + + /* wait for the write in progress bit to be cleared in the status register */ + if ((ret = mvWaitOnWipClear()) != MV_OK) + return ret; + + return ret; +} + + + +/******************************************************************************* +* mvSMFlash64bWr - Program 64 bytes of Data alligned to 64 boundaries +* +* DESCRIPTION: +* Program to main region 64 bytes of Data alligned to 64 boundaries +* +* INPUT: +* pFlash: Flash information structure +* offset: address to start the programming from (alligned to 64 bytes) +* pBlock: pointer to the 64 bytes to program +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlash64bWr(MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SMFLASH_PRGRM_CMND_LEN]; + + /* Check for null pointer */ +#ifndef CONFIG_MARVELL + if(NULL == pBlock) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } +#endif + + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* check allignment */ + if (offset & MV_SMFLASH_PAGE_ALLIGN_MASK) + { + DB(mvOsPrintf("%s WARNING: Allignment error!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* encode the command to send */ + cmd[0] = MV_SMFLASH_PRGRM_CMND_OPCD; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + /* Perform the write enable sequence */ + if ((ret = mvWriteEnable()) != MV_OK) + return ret; + + /* serialize the command and then followed by the data to program */ + if ((ret = mvSpiWriteThenWrite(cmd, MV_SMFLASH_PRGRM_CMND_LEN, pBlock, MV_SMFLASH_PAGE_SIZE)) != MV_OK) + return ret; + + /* wait for the write in progress bit to be cleared in the status register */ + if ((ret = mvWaitOnWipClear()) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSMFlash64bWrVerify - Program and verify 64 bytes of Data alligned to +* 64 bytes boundaries +* +* DESCRIPTION: +* Program and verifyto main region 64 bytes of Data alligned to 64 +* bytes boundaries +* +* INPUT: +* pFlash: Flash information structure +* offset: address to start the programming from (alligned to 64 bytes) +* pBlock: pointer to the 64 bytes to program +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlash64bWrVerify(MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SMFLASH_PRGRM_CMP_CMND_LEN]; + MV_U8 status; + + /* Check for null pointer */ + if ((pFlash == NULL) || (pBlock == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* check allignment */ + if (offset & MV_SMFLASH_PAGE_ALLIGN_MASK) + { + DB(mvOsPrintf("%s WARNING: Allignment error!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* encode the command to send */ + cmd[0] = MV_SMFLASH_PRGRM_CMP_CMND_OPCD; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + /* Perform the write enable sequence */ + if ((ret = mvWriteEnable()) != MV_OK) + return ret; + + /* serialize the command and then followed by the data to program */ + if ((ret = mvSpiWriteThenWrite(cmd, MV_SMFLASH_PRGRM_CMP_CMND_LEN, pBlock, MV_SMFLASH_PAGE_SIZE)) != MV_OK) + return ret; + + /* wait for the write in progress bit to be cleared in the status register */ + if ((ret = mvWaitOnWipClear()) != MV_OK) + return ret; + + /* Read the status register */ + if ((ret = mvStatusRegGet(&status)) != MV_OK) + return ret; + + /* check if result of the compare operartion */ + if (status & MV_SMFLASH_STATUS_REG_CMP_MASK) + { + DB(mvOsPrintf("%s WARNING: Compare after write error!\n", __FUNCTION__);) + return MV_FAIL; + } + + return MV_OK; +} + +/******************************************************************************* +* mvSMFlash64bInfWr - Information region program 64 bytes of Data alligned +* to 64 bytes boundaries +* +* DESCRIPTION: +* Program to information region 64 bytes of Data alligned to 64 boundaries +* +* INPUT: +* pFlash: Flash information structure +* offset: address to start the programming from (alligned to 64 bytes) +* pBlock: pointer to the 64 bytes to program +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlash64bInfWr(MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SMFLASH_IPRGRM_CMND_LEN]; + + /* Check for null pointer */ + if ((pFlash == NULL) || (pBlock == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* check allignment */ + if (offset & MV_SMFLASH_PAGE_ALLIGN_MASK) + { + DB(mvOsPrintf("%s WARNING: Allignment error!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* encode the command to send */ + cmd[0] = MV_SMFLASH_IPRGRM_CMND_OPCD; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + /* Perform the write enable sequence */ + if ((ret = mvWriteEnable()) != MV_OK) + return ret; + + /* serialize the command and then followed by the data to program */ + if ((ret = mvSpiWriteThenWrite(cmd, MV_SMFLASH_IPRGRM_CMND_LEN, pBlock, MV_SMFLASH_PAGE_SIZE)) != MV_OK) + return ret; + + /* wait for the write in progress bit to be cleared in the status register */ + if ((ret = mvWaitOnWipClear()) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSMFlash64bInfWrVerify - Program and verify 64 bytes of Data ti the +* information region alligned to 64 boundaries +* +* DESCRIPTION: +* Program and then verify to the information region 64 bytes of Data +* alligned to 64 boundaries +* +* INPUT: +* pFlash: Flash information structure +* offset: address to start the programming from (alligned to 64 bytes) +* pBlock: pointer to the 64 bytes to program +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlash64bInfWrVerify(MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SMFLASH_IPRGRM_CMP_CMND_LEN]; + MV_U8 status; + + /* Check for null pointer */ + if ((pFlash == NULL) || (pBlock == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* check allignment */ + if (offset & MV_SMFLASH_PAGE_ALLIGN_MASK) + { + DB(mvOsPrintf("%s WARNING: Allignment error!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* encode the command to send */ + cmd[0] = MV_SMFLASH_IPRGRM_CMP_CMND_OPCD; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + /* Perform the write enable sequence */ + if ((ret = mvWriteEnable()) != MV_OK) + return ret; + + /* serialize the command and then followed by the data to program */ + if ((ret = mvSpiWriteThenWrite(cmd, MV_SMFLASH_IPRGRM_CMP_CMND_LEN, pBlock, MV_SMFLASH_PAGE_SIZE)) != MV_OK) + return ret; + + /* wait for the write in progress bit to be cleared in the status register */ + if ((ret = mvWaitOnWipClear()) != MV_OK) + return ret; + + /* Read the status register */ + if ((ret = mvStatusRegGet(&status)) != MV_OK) + return ret; + + /* check if result of the compare operartion */ + if (status & MV_SMFLASH_STATUS_REG_CMP_MASK) + { + DB(mvOsPrintf("%s WARNING: Compare after information region write error!\n", __FUNCTION__);) + return MV_FAIL; + } + + return MV_OK; +} + +/******************************************************************************* +* mvSMFlashBlockRd - Read from the main region into a buffer +* +* DESCRIPTION: +* Issue the main region read sequence. Size and offset are not limited +* except to the size of the flash. +* +* INPUT: +* pFlash: Flash information structure +* offset: address in the main region to start the reading from. +* blockSize: size of the buffer to be read +* pBlock: pointer to the buffer to hold the data read from the flash +* +* OUTPUT: +* pBlock: pointer to the buffer holding the data from the flash +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlashBlockRd(MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, + MV_U8 *pBlock) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SMFLASH_READ_CMND_LEN]; + + /* Check for null pointer */ + if ((pFlash == NULL) || (pBlock == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* check that requested data is in the region */ + if ((offset + blockSize) > (pFlash->sectorNumber * pFlash->sectorSize)) + { + DB(mvOsPrintf("%s WARNING: Read exceeds flash size!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* encode the command to send */ + cmd[0] = MV_SMFLASH_READ_CMND_OPCD; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + /* Perform the write enable sequence */ + if ((ret = mvWriteEnable()) != MV_OK) + return ret; + + /* serialize the command and then followed by the data to program */ + if ((ret = mvSpiWriteThenRead(cmd, MV_SMFLASH_READ_CMND_LEN, pBlock, blockSize, 0)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSMFlashBlockInfRd - Read from the information region into a buffer +* +* DESCRIPTION: +* Issue the information region read sequence. Size and offset are not +* limited except to the size of the information region. +* +* INPUT: +* pFlash: Flash information structure +* offset: address in the information region to start the reading from. +* blockSize: size of the buffer to be read +* pBlock: pointer to the buffer to hold the data read from the flash +* +* OUTPUT: +* pBlock: pointer to the buffer holding the data from the flash +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlashBlockInfRd(MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, + MV_U8 *pBlock) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SMFLASH_IREAD_CMND_LEN]; + + /* Check for null pointer */ + if ((pFlash == NULL) || (pBlock == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* check that requested data is in the region */ + if ((offset + blockSize) > pFlash->infoSize) + { + DB(mvOsPrintf("%s WARNING: Read exceeds information region size!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* encode the command to send */ + cmd[0] = MV_SMFLASH_IREAD_CMND_OPCD; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + /* Perform the write enable sequence */ + if ((ret = mvWriteEnable()) != MV_OK) + return ret; + + /* serialize the command and then followed by the data to program */ + if ((ret = mvSpiWriteThenRead(cmd, MV_SMFLASH_IREAD_CMND_LEN, pBlock, blockSize, 0)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSMFlashReadConfig3 - Read the value of the configuration register +* +* DESCRIPTION: +* Read the value of the configuration register #3 +* +* INPUT: +* pFlash: Flash information structure +* configReg: pointer to the 8bit variable to read in the config register +* +* OUTPUT: +* configReg: pointer to the 8bit varable holding the config register +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlashReadConfig3(MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg) +{ + /* Check for null pointer */ + if ((pFlash == NULL) || (pConfigReg == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvSingleByteRead(MV_SMFLASH_READ_CFG_3_CMND_OPCD, pConfigReg); +} + +/******************************************************************************* +* mvSMFlashReadConfig4 - Read the value of the configuration register +* +* DESCRIPTION: +* Read the value of the configuration register #4 +* +* INPUT: +* pFlash: Flash information structure +* configReg: pointer to the 8bit variable to read in the config register +* +* OUTPUT: +* configReg: pointer to the 8bit varable holding the config register +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlashReadConfig4(MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg) +{ + /* Check for null pointer */ + if ((pFlash == NULL) || (pConfigReg == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvSingleByteRead(MV_SMFLASH_READ_CFG_4_CMND_OPCD, pConfigReg); +} + +/******************************************************************************* +* mvSMFlashSetConfig3 - Set the value of the configuration register +* +* DESCRIPTION: +* Set the value of the configuration register #3 +* +* INPUT: +* pFlash: Flash information structure +* configReg: 8bit variable to be written to the config register +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlashSetConfig3(MV_MFLASH_INFO *pFlash, MV_U8 configReg) +{ + /* Check for null pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvSingleByteWrite(MV_SMFLASH_SET_CFG_3_CMND_OPCD, configReg); +} + +/******************************************************************************* +* mvSMFlashSetConfig4 - Set the value of the configuration register +* +* DESCRIPTION: +* Set the value of the configuration register #4 +* +* INPUT: +* pFlash: Flash information structure +* configReg: 8bit variable to be written to the config register +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlashSetConfig4(MV_MFLASH_INFO *pFlash, MV_U8 configReg) +{ + /* Check for null pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvSingleByteWrite(MV_SMFLASH_SET_CFG_4_CMND_OPCD, configReg); +} + +/******************************************************************************* +* mvSMFlashWriteProtectSet - Write protect the whole flash device +* +* DESCRIPTION: +* Enable/Disable the write protection on the whole flash device. +* +* INPUT: +* pFlash: Flash information structure +* wp: enable/disable (MV_TRUE/MV_FALSE) write protection +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlashWriteProtectSet(MV_MFLASH_INFO *pFlash, MV_BOOL wp) +{ + MV_STATUS ret; + MV_U8 reg; + + /* Check for null pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Read the serial configuration register #4 */ + if ((ret = mvSMFlashReadConfig4(pFlash, ®)) != MV_OK) + return ret; + + /* set the WP bit according to the wp input */ + if (wp) + reg &= ~MV_SMFLASH_SRL_CFG4_WP_MASK; + else + reg |= MV_SMFLASH_SRL_CFG4_WP_MASK; + + /* write back the serial configuration register #4 */ + if ((ret = mvSMFlashSetConfig4(pFlash, reg)) != MV_OK) + return ret; + + return MV_OK; +} + + +/******************************************************************************* +* mvSMFlashSectorSizeSet - Set the sector size +* +* DESCRIPTION: +* Set the sector size (4K or 32K) +* +* INPUT: +* pFlash: Flash information structure +* secSize: requested sector size +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlashSectorSizeSet(MV_MFLASH_INFO *pFlash, MV_U32 secSize) +{ + MV_STATUS ret; + MV_U8 reg; + + /* Check for null pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Read the serial configuration register #4 */ + if ((ret = mvSMFlashReadConfig4(pFlash, ®)) != MV_OK) + return ret; + + /* set the PAGE4K bit according to the secSize input */ + switch (secSize) + { + case MV_MFLASH_SECTOR_SIZE_BIG: + reg &= ~MV_SMFLASH_SRL_CFG4_PG_SIZE_MASK; /* 32K sectors */ + break; + + case MV_MFLASH_SECTOR_SIZE_SMALL: + reg |= MV_SMFLASH_SRL_CFG4_PG_SIZE_MASK; /* 4K sectors */ + break; + + default: + DB(mvOsPrintf("%s WARNING: Invalid parameter sector size!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* write back the serial configuration register #4 */ + if ((ret = mvSMFlashSetConfig4(pFlash, reg)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSMFlashShutdownSet - Put the flash device in power save mode +* +* DESCRIPTION: +* Put the flash device in power save mode +* +* INPUT: +* pFlash: Flash information structure +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlashShutdownSet(MV_MFLASH_INFO *pFlash) +{ + /* Check for null pointer */ + if (pFlash == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + return mvSingleByteCmnd(MV_SMFLASH_SHUTDOWN_CMND_OPCD); +} + +/******************************************************************************* +* mvSMFlashIdGet - Retreive the Manufacturer ID and Device ID +* +* DESCRIPTION: +* Read from the flash device the +* +* INPUT: +* pFlash: Flash information structure +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSMFlashIdGet(MV_MFLASH_INFO *pFlash, MV_U32 * pManfCode, MV_U16 * pDevCode) +{ + MV_STATUS ret = MV_OK; + MV_U8 cmd[MV_SMFLASH_RDID_CMND_LEN]; + MV_U8 id[MV_SMFLASH_RDID_RPLY_LEN]; + + /* Check for null pointer */ + if ((pFlash == NULL) || (pManfCode == NULL) || (pDevCode == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + cmd[0] = MV_SMFLASH_RDID_CMND_OPCD; + + if ((ret = mvSpiWriteThenRead(cmd, MV_SMFLASH_RDID_CMND_LEN, id, MV_SMFLASH_RDID_RPLY_LEN, 0)) != MV_OK) + return ret; + + *pManfCode = ((id[0] << 24) | (id[1] << 16) | (id[2] << 8) | (id[3])); + *pDevCode = ((id[4] << 8) | (id[5])); + + return ret; +} + + + diff --git a/board/mv_feroceon/mv_hal/mflash/mvSMFlash.h b/board/mv_feroceon/mv_hal/mflash/mvSMFlash.h new file mode 100644 index 0000000..a5be79c --- /dev/null +++ b/board/mv_feroceon/mv_hal/mflash/mvSMFlash.h @@ -0,0 +1,111 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSMFlashH +#define __INCmvSMFlashH + +#include "mvMFlash.h" + +/* Function Prototypes */ + +/* Init */ +MV_STATUS mvSMFlashInit (MV_MFLASH_INFO *pFlash); + +/* Erase */ +MV_STATUS mvSMFlashChipErase (MV_MFLASH_INFO *pFlash); /* Erase the whole chip */ +MV_STATUS mvSMFlashMainErase (MV_MFLASH_INFO *pFlash); /* Erase the whole main region */ +MV_STATUS mvSMFlashInfErase (MV_MFLASH_INFO *pFlash); /* Erase the whole information region */ +MV_STATUS mvSMFlashSecErase (MV_MFLASH_INFO *pFlash, MV_U32 secAddr); /* Single Main sector erase */ + +/* Read */ +MV_STATUS mvSMFlashBlockRd (MV_MFLASH_INFO *pFlash, MV_U32 offset, + MV_U32 blockSize, MV_U8 *pBlock); +MV_STATUS mvSMFlashBlockInfRd (MV_MFLASH_INFO *pFlash, MV_U32 offset, + MV_U32 blockSize, MV_U8 *pBlock); + +/* write - 64 bytes aliigned to 64 edges */ +MV_STATUS mvSMFlash64bWr (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock); +MV_STATUS mvSMFlash64bWrVerify (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock); +MV_STATUS mvSMFlash64bInfWr (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock); +MV_STATUS mvSMFlash64bInfWrVerify (MV_MFLASH_INFO *pFlash, MV_U32 offset, MV_U8 *pBlock); + +/* Configuration registers Read/Write */ +MV_STATUS mvSMFlashReadConfig3 (MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg); +MV_STATUS mvSMFlashReadConfig4 (MV_MFLASH_INFO *pFlash, MV_U8 * pConfigReg); +MV_STATUS mvSMFlashSetConfig3 (MV_MFLASH_INFO *pFlash, MV_U8 configReg); +MV_STATUS mvSMFlashSetConfig4 (MV_MFLASH_INFO *pFlash, MV_U8 configReg); + +/* write protection */ +MV_STATUS mvSMFlashWriteProtectSet(MV_MFLASH_INFO *pFlash, MV_BOOL wp); + +/* Set the Sector Size option */ +MV_STATUS mvSMFlashSectorSizeSet (MV_MFLASH_INFO *pFlash, MV_U32 secSize); + +/* Shutdown/operate (true/false) the device */ +MV_STATUS mvSMFlashShutdownSet (MV_MFLASH_INFO *pFlash); + +/* Retreive the Flash ID */ +MV_STATUS mvSMFlashIdGet (MV_MFLASH_INFO *pFlash, MV_U32 * pManfCode, MV_U16 * pDevCode); + +#endif /* __INCmvSMFlashH */ diff --git a/board/mv_feroceon/mv_hal/mflash/mvSMFlashSpec.h b/board/mv_feroceon/mv_hal/mflash/mvSMFlashSpec.h new file mode 100644 index 0000000..680c1bc --- /dev/null +++ b/board/mv_feroceon/mv_hal/mflash/mvSMFlashSpec.h @@ -0,0 +1,119 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSMFlashSpecH +#define __INCmvSMFlashSpecH + +/* Constants */ +#define MV_SMFLASH_PAGE_ALLIGN_MASK 0x3F +#define MV_SMFLASH_PAGE_SIZE (MV_SMFLASH_PAGE_ALLIGN_MASK+1) /* 64 byte */ + +#define MV_SMFLASH_WREN_CMND_OPCD 0x06 /* Write Enable */ +#define MV_SMFLASH_WRDI_CMND_OPCD 0x04 /* Write Disable */ +#define MV_SMFLASH_RDSR_CMND_OPCD 0x05 /* Read Status Register */ +#define MV_SMFLASH_READ_CMND_OPCD 0x03 /* Sequential Read */ +#define MV_SMFLASH_PRGRM_CMND_OPCD 0x02 /* Page Program */ +#define MV_SMFLASH_PRGRM_CMP_CMND_OPCD 0x07 /* Page Program and compare */ +#define MV_SMFLASH_PAGE_ERASE_CMND_OPCD 0x42 /* Sector Erase */ +#define MV_SMFLASH_MAIN_ERASE_CMND_OPCD 0x62 /* Main region Erase */ +#define MV_SMFLASH_RDID_CMND_OPCD 0x15 /* Read ID */ +#define MV_SMFLASH_IREAD_CMND_OPCD 0x83 /* Read from Information region */ +#define MV_SMFLASH_IPRGRM_CMND_OPCD 0x82 /* Program the information region */ +#define MV_SMFLASH_IPRGRM_CMP_CMND_OPCD 0x87 /* Program and compare information region */ +#define MV_SMFLASH_SET_CFG_3_CMND_OPCD 0xB2 /* Set configuration register 3 */ +#define MV_SMFLASH_SET_CFG_4_CMND_OPCD 0xB3 /* Set configuration register 4 */ +#define MV_SMFLASH_READ_CFG_3_CMND_OPCD 0xB6 /* Read configuration register 3 */ +#define MV_SMFLASH_READ_CFG_4_CMND_OPCD 0xB7 /* Read configuration register 4 */ +#define MV_SMFLASH_IPG_ERASE_CMND_OPCD 0xC2 /* Erase the information page */ +#define MV_SMFLASH_CHIP_ERASE_CMND_OPCD 0xE2 /* Chip erase (main + information) */ +#define MV_SMFLASH_SHUTDOWN_CMND_OPCD 0xF0 /* Set flash in power down mode */ + +#define MV_SMFLASH_PAGE_ERASE_CMND_LEN 4 /* 1B opcode + 3B address */ +#define MV_SMFLASH_PRGRM_CMND_LEN 4 /* 1B opcode + 3B address */ +#define MV_SMFLASH_PRGRM_CMP_CMND_LEN 4 /* 1B opcode + 3B address */ +#define MV_SMFLASH_IPRGRM_CMND_LEN 4 /* 1B opcode + 3B address */ +#define MV_SMFLASH_IPRGRM_CMP_CMND_LEN 4 /* 1B opcode + 3B address */ +#define MV_SMFLASH_READ_CMND_LEN 4 /* 1B opcode + 3B address */ +#define MV_SMFLASH_IREAD_CMND_LEN 4 /* 1B opcode + 3B address */ +#define MV_SMFLASH_RDID_CMND_LEN 1 /* 1B opcode */ +#define MV_SMFLASH_RDID_RPLY_LEN 6 /* 4B manuf ID + 2B device ID */ + +/* Status Register Bit Masks */ +#define MV_SMFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0 - Write in Progress */ +#define MV_SMFLASH_STATUS_REG_WEL_OFFSET 1 /* bit 1 - Write enable Latch */ +#define MV_SMFLASH_STATUS_REG_CMP_OFFSET 6 /* bit 6 - Compare status */ +#define MV_SMFLASH_STATUS_REG_WP_OFFSET 7 /* bit 7 - Write protect status */ +#define MV_SMFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SMFLASH_STATUS_REG_WIP_OFFSET) +#define MV_SMFLASH_STATUS_REG_WEL_MASK (0x1 << MV_SMFLASH_STATUS_REG_WEL_OFFSET) +#define MV_SMFLASH_STATUS_REG_CMP_MASK (0x1 << MV_SMFLASH_STATUS_REG_CMP_OFFSET) +#define MV_SMFLASH_STATUS_REG_WP_MASK (0x1 << MV_SMFLASH_STATUS_REG_WP_OFFSET) + +/* Serial Interface Configuration 4 Masks */ +#define MV_SMFLASH_SRL_CFG4_PG_SIZE_OFFSET 0 /* bit 0 - Page size */ +#define MV_SMFLASH_SRL_CFG4_WP_OFFSET 7 /* bit 7 - Write protection */ +#define MV_SMFLASH_SRL_CFG4_PG_SIZE_MASK (0x1 << MV_SMFLASH_SRL_CFG4_PG_SIZE_OFFSET) +#define MV_SMFLASH_SRL_CFG4_WP_MASK (0x1 << MV_SMFLASH_SRL_CFG4_WP_OFFSET) + +#endif /* __INCmvSMFlashSpecH */ + diff --git a/board/mv_feroceon/mv_hal/norflash/mvAmdFlash.c b/board/mv_feroceon/mv_hal/norflash/mvAmdFlash.c new file mode 100644 index 0000000..9666b4d --- /dev/null +++ b/board/mv_feroceon/mv_hal/norflash/mvAmdFlash.c @@ -0,0 +1,279 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvFlash.h" + +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_BOOL amdFlashStsIsRdy(MV_FLASH_INFO *pFlash, MV_U32 offset, + MV_U32 excepted); +static MV_VOID amdFlashUnlock(MV_FLASH_INFO *pFlash); + +/******************************************************************************* +* reset the flash +*******************************************************************************/ +MV_VOID amdFlashReset(MV_FLASH_INFO *pFlash) +{ + flashCmdSet(pFlash, 0, 0, AMD_CHIP_CMD_RST); + return; +} + +/******************************************************************************* +* amdFlashSecErase - Erase a sector. +* +* DESCRIPTION: +* Erase a Flash sector. +* +* INPUT: +* secNum - sector Number. +* pFlash - flash information. +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK if program completed successfully, +* MV_TIMEOUT if timeout reached, +* MV_FAIL otherwise. +* +*******************************************************************************/ +MV_STATUS amdFlashSecErase(MV_FLASH_INFO *pFlash, MV_U32 secNum) +{ + MV_U32 i; + + DB(mvOsPrintf("Flash: amdFlashSecErase\n")); + + /* erase sequence */ + amdFlashUnlock(pFlash); + + switch (pFlash->flashSpec.flashVen) + { + case AMD_MANUF: + case STM_MANUF: + flashCmdSet(pFlash, AMD_CHIP_ADDR_ERASE1, 0, AMD_CHIP_CMD_ERASE1); + flashCmdSet(pFlash, AMD_CHIP_ADDR_ERASE2, 0, AMD_CHIP_CMD_ERASE2); + flashCmdSet(pFlash, AMD_CHIP_ADDR_ERASE3, 0, AMD_CHIP_CMD_ERASE3); + flashCmdSet(pFlash, 0, secNum, AMD_CHIP_CMD_ERASE4); + break; + case SST_MANUF: + flashCmdSet(pFlash, SST_CHIP_ADDR_ERASE1, 0, AMD_CHIP_CMD_ERASE1); + flashCmdSet(pFlash, SST_CHIP_ADDR_ERASE2, 0, AMD_CHIP_CMD_ERASE2); + flashCmdSet(pFlash, SST_CHIP_ADDR_ERASE3, 0, AMD_CHIP_CMD_ERASE3); + flashCmdSet(pFlash, 0, secNum, AMD_CHIP_CMD_ERASE4); + break; + + } + + + + /* wait for erase to complete */ + for(i = 0; i < AMD_EARASE_MILI_TIMEOUT; i++) + { + mvOsDelay(1); + if(MV_TRUE == amdFlashStsIsRdy(pFlash, mvFlashSecOffsGet(pFlash,secNum) + + mvFlashBaseAddrGet(pFlash), AMD_CHIP_STAT_DQ7_MASK)) + { + DB(mvOsPrintf("Flash: amdFlashSecErase erase PASS !!\n")); + return MV_OK; + } + } + mvOsPrintf("Flash: ERROR amdFlashSecErase timeout \n"); + + return MV_TIMEOUT; +} + + +/******************************************************************************* +* amdFlashProg - Prog busWidth Bits into the address offest in the flash. +* +* DESCRIPTION: +* This function writes busWidth data to a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* data - 32bit data to be written to flash. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if program completed successfully, +* MV_TIMEOUT otherwise. +* +*******************************************************************************/ +MV_STATUS amdFlashProg(MV_FLASH_INFO *pFlash,MV_U32 offset, MV_U32 data) +{ + MV_U32 i; + MV_U32 statusExpectedData; + + DB(mvOsPrintf("Flash: amdFlashProg offset %x data %x\n",offset,data)); + + /* write sequence */ + amdFlashUnlock(pFlash); + + switch (pFlash->flashSpec.flashVen) + { + case AMD_MANUF: + case STM_MANUF: + flashCmdSet(pFlash, AMD_CHIP_ADDR_PROG, 0, AMD_CHIP_CMD_PROG); + break; + case SST_MANUF: + flashCmdSet(pFlash, SST_CHIP_ADDR_PROG, 0, AMD_CHIP_CMD_PROG); + break; + + } + flashBusWidthDataWr(pFlash, offset + mvFlashBaseAddrGet(pFlash), data); + + /* To check status we need to be sure that the data is in the same endianess + of the status, the status is always little endian and the data is big endian + , so we will convert the data to little endian before calling the amdFlashStsIsRdy + function*/ + + switch(pFlash->busWidth) + { + case 1: + statusExpectedData = data; + break; + case 2: + statusExpectedData = MV_16BIT_LE(data); + break; + case 4: + statusExpectedData = MV_32BIT_LE(data); + break; + default: + mvOsPrintf("%s ERROR: Bus Width %d Bytes isn't supported.\n", + __FUNCTION__, pFlash->busWidth); + return MV_TIMEOUT; + } + + + /* wait for write to complete */ + for(i = 0; i < AMD_PROG_TIMEOUT; i++) + { + if(MV_TRUE == amdFlashStsIsRdy(pFlash,offset + + mvFlashBaseAddrGet(pFlash), + statusExpectedData)) + { + DB(mvOsPrintf("Flash: amdFlashProg prog PASS !!\n")); + return MV_OK; + } + } + + mvOsPrintf("Flash: ERROR amdFlashSecErase timeout \n"); + + return MV_TIMEOUT; +} + +/******************************************************************************* +* There are few ways to check if the AMD flash is busy or not: +* 1) by checking DQ7 [and 5 - optional ] +* 2) by checking toggle bit DQ7 (linux implementation) +* here we used the first option: +* after write/erase the flash push not(DQ7) until the opertion is completed. +*******************************************************************************/ +static MV_BOOL amdFlashStsIsRdy(MV_FLASH_INFO *pFlash, MV_U32 addr, + MV_U32 expected) +{ + MV_U32 status; + + status = flashBusWidthRd(pFlash, addr); + /* if DQ7 == Datum 7 */ + if((status & flashDataExt(pFlash, AMD_CHIP_STAT_DQ7_MASK )) == + (flashDataExt(pFlash,expected) & + flashDataExt(pFlash, AMD_CHIP_STAT_DQ7_MASK))) + { + DB(mvOsPrintf("Flash: amdFlashStatusChk value is ready \n")); + return MV_TRUE; + } + DB(mvOsPrintf("Flash: amdFlashStatusChk staus not ready \n")); + return MV_FALSE; +} + +/******************************************************************************* +* Sequence for Unlocking the flash before accessing the flash. +*******************************************************************************/ +static MV_VOID amdFlashUnlock(MV_FLASH_INFO *pFlash) +{ + switch (pFlash->flashSpec.flashVen) + { + case AMD_MANUF: + case STM_MANUF: + flashCmdSet(pFlash, AMD_CHIP_UNLOCK_ADDR1, 0, AMD_CHIP_UNLOCK_CMD1); + flashCmdSet(pFlash, AMD_CHIP_UNLOCK_ADDR2, 0, AMD_CHIP_UNLOCK_CMD2); + break; + case SST_MANUF: + flashCmdSet(pFlash, SST_CHIP_UNLOCK_ADDR1, 0, AMD_CHIP_UNLOCK_CMD1); + flashCmdSet(pFlash, SST_CHIP_UNLOCK_ADDR2, 0, AMD_CHIP_UNLOCK_CMD2); + break; + } + return; +} + + + diff --git a/board/mv_feroceon/mv_hal/norflash/mvAmdFlash.h b/board/mv_feroceon/mv_hal/norflash/mvAmdFlash.h new file mode 100644 index 0000000..791db1b --- /dev/null +++ b/board/mv_feroceon/mv_hal/norflash/mvAmdFlash.h @@ -0,0 +1,168 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvAmdFlashH +#define __INCmvAmdFlashH + +#include "mvFlashCom.h" + + +/* AMD Flash IDs */ +#define AMD_FID_LV040B 0x4F /* 29LV040B ID */ + /* 4 Mbit, 512K x 8, */ + /* 8 64K x 8 uniform sectors */ + +#define AMD_FID_F040B 0xA4 /* 29F040B ID */ + /* 4 Mbit, 512K x 8, */ + /* 8 64K x 8 uniform sectors */ +#define STM_FID_M29W040B 0xE3 /* M29W040B ID */ + /* 4 Mbit, 512K x 8, */ + /* 8 64K x 8 uniform sectors */ +#define AMD_FID_F080B 0xD5 /* 29F080 ID ( 1 M) */ + /* 8 Mbit, 512K x 16, */ + /* 8 64K x 16 uniform sectors */ +#define AMD_FID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */ +#define AMD_FID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */ +#define AMD_FID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect)*/ +#define AMD_FID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */ + +#define AMD_FID_LV400T 0x22B9 /* 29LV400T ID ( 4 M, top boot sector) */ +#define AMD_FID_LV400B 0x22BA /* 29LV400B ID ( 4 M, bottom boot sect) */ + +#define AMD_FID_LV033C 0xA3 /* 29LV033C ID ( 4 M x 8) */ +#define AMD_FID_LV065D 0x93 /* 29LV065D ID ( 8 M x 8) */ + +#define AMD_FID_LV800T 0x22DA /* 29LV800T ID ( 8 M, top boot sector) */ +#define AMD_FID_LV800B 0x225B /* 29LV800B ID ( 8 M, bottom boot sect) */ + +#define AMD_FID_LV160T 0x22C4 /* 29LV160T ID (16 M, top boot sector) */ +#define AMD_FID_LV160B 0x2249 /* 29LV160B ID (16 M, bottom boot sect) */ + +#define AMD_FID_LV320T 0x22F6 /* 29LV320T ID (32 M, top boot sector) */ +#define AMD_FID_LV320B 0x22F9 /* 29LV320B ID (32 M, bottom boot sect) */ + +#define AMD_FID_DL322T 0x2255 /* 29DL322T ID (32 M, top boot sector) */ +#define AMD_FID_DL322B 0x2256 /* 29DL322B ID (32 M, bottom boot sect) */ +#define AMD_FID_DL323T 0x2250 /* 29DL323T ID (32 M, top boot sector) */ +#define AMD_FID_DL323B 0x2253 /* 29DL323B ID (32 M, bottom boot sect) */ +#define AMD_FID_DL324T 0x225C /* 29DL324T ID (32 M, top boot sector) */ +#define AMD_FID_DL324B 0x225F /* 29DL324B ID (32 M, bottom boot sect) */ + +#define AMD_S29GL128N 0x227E /* S29GL128N spansion 128Mbit flash */ +#define AMD_FID_DL640 0x227E /* 29DL640D ID (64 M, dual boot sectors)*/ +#define AMD_FID_MIRROR 0x227E /* 1st ID word for MirrorBit family */ +#define AMD_FID_LV640U_2 0x220C /* 2d ID word for AM29LV640M at 0x38 */ +#define AMD_FID_LV640U_3 0x2201 /* 3d ID word for AM29LV640M at 0x3c */ +#define AMD_FID_LV128U_2 0x2212 /* 2d ID word for AM29LV128M at 0x38 */ +#define AMD_FID_LV128U_3 0x2200 /* 3d ID word for AM29LV128M at 0x3c */ + +#define AMD_FID_LV640U 0x22D7 /* 29LV640U ID (64 M, uniform sectors) */ + +#define STM_FID_29W040B 0xE3 /* M29W040B ID (4M = 512K x 8) */ + +/* SST Flash IDs */ +#define SST_39VF_020 0xD6 /* SST39VF020 (256KB = 4K * 64) */ + + +/* Amd Flash APIs */ +#define AMD_EARASE_MILI_TIMEOUT 8000 /* mili seconds */ +#define AMD_PROG_TIMEOUT 0xA0000 /* number of loops */ + +/* Commands */ +#define AMD_CHIP_CMD_RST 0xF0 /* reset flash */ +#define AMD_CHIP_UNLOCK_CMD1 0xAA /* 1st data for unlock */ +#define AMD_CHIP_UNLOCK_ADDR1 0x555 /* 1st addr for unlock */ +#define SST_CHIP_UNLOCK_ADDR1 0x5555 /* 1st addr for unlock */ +#define AMD_CHIP_UNLOCK_CMD2 0x55 /* 2nd data for unlock */ +#define AMD_CHIP_UNLOCK_ADDR2 0x2AA /* 2nd addr for unlock */ +#define SST_CHIP_UNLOCK_ADDR2 0x2AAA /* 2nd addr for unlock */ +#define AMD_CHIP_CMD_PROG 0xA0 /* 1st data for program command */ +#define AMD_CHIP_ADDR_PROG 0x555 /* 1st addr for program command */ +#define SST_CHIP_ADDR_PROG 0x5555 /* 1st addr for program command */ +#define AMD_CHIP_CMD_ERASE1 0x80 /* 1st data for erase command */ +#define AMD_CHIP_ADDR_ERASE1 0x555 /* 1st addr for erase command */ +#define SST_CHIP_ADDR_ERASE1 0x5555 /* 1st addr for erase command */ +#define AMD_CHIP_CMD_ERASE2 0xAA /* 2nd data for erase command */ +#define AMD_CHIP_ADDR_ERASE2 0x555 /* 2nd addr for erase command */ +#define SST_CHIP_ADDR_ERASE2 0x5555 /* 2nd addr for erase command */ +#define AMD_CHIP_CMD_ERASE3 0x55 /* 3rd data for erase command */ +#define AMD_CHIP_ADDR_ERASE3 0x2AA /* 3rd addr for erase command */ +#define SST_CHIP_ADDR_ERASE3 0x2AAA /* 3rd addr for erase command */ +#define AMD_CHIP_CMD_ERASE4 0x30 /* 4rd data for erase command */ + +/* there are few ways to check if the AMD flash is busy or not: */ +/* 1) by checking DQ7 [and 5 - optional ] */ +/* 2) by checking toggle bit DQ7 (linux) */ +/* here we used the first option. */ +/* status register bits */ +#define AMD_CHIP_STAT_DQ7_MASK 0x80 /* Device is ready */ + +/* ID and Lock Configuration */ +#define AMD_CHIP_RD_ID_MAN 0x01 /* Manufacturer code = 0x89 */ + +MV_STATUS amdFlashSecErase(MV_FLASH_INFO *pFlash, MV_U32 secNum); +MV_VOID amdFlashReset(MV_FLASH_INFO *pFlash); +MV_STATUS amdFlashProg(MV_FLASH_INFO *pFlash,MV_U32 offset, MV_U32 data); + +#endif /* __INCmvAmdFlashH */ diff --git a/board/mv_feroceon/mv_hal/norflash/mvCompVer.txt b/board/mv_feroceon/mv_hal/norflash/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/norflash/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/norflash/mvFlash.c b/board/mv_feroceon/mv_hal/norflash/mvFlash.c new file mode 100644 index 0000000..026eb0f --- /dev/null +++ b/board/mv_feroceon/mv_hal/norflash/mvFlash.c @@ -0,0 +1,1412 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvFlash.h" + + +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +#define LAST_FLASH 0xFFFFFFFF +/* When inserting a bottom/top flash number of sectors should be the number */ +/* of all sector including the "fragmented" sectors. */ +/* */ +/* Size of the flash must be as spesified in Spec, in case there are 2 dev */ +/* in a row the driver will recognize it according to bus and dev width. */ +/* */ +/* In case of using Bottom flash it should look like this: */ +/* MV_U32 IntelSecFrag[]= {_8K, _8K, _8K, _8K, _8K, _8K, _8K, _8K}; */ +/* FLASH_STRUCT supFlashAry[]= */ +/* { */ +/* { */ +/* INTEL_MANUF, flash Vendor */ +/* INTEL_FID_28F640J3A, flash ID */ +/* _4M, flash size */ +/* 71, flash secotor number */ +/* BOTTOM, flash sector structure (top, bottom, regular) */ +/* 8, Number of sector fragments */ +/* IntelSecFrag, pointer to sector size fragment list */ +/* MV_FALSE Support of HW protection */ +/* }, */ +/* ....... */ +/* } */ +/* */ + +MV_U32 IntelSecFrag[]= {_32K, _32K, _32K, _32K}; +FLASH_STRUCT supFlashAry[]= +{ +/* flashVen flashId size #sec secType #Frag pFragList HWprot HwWrBuff */ +{INTEL_MANUF, INTEL_FID_28F256P30B, _32M, 259, BOTTOM, 4, IntelSecFrag, MV_TRUE, 64 }, +{INTEL_MANUF, INTEL_FID_28F640J3A, _8M, 64, REGULAR, 0, NULL, MV_TRUE, 32 }, +{INTEL_MANUF, INTEL_FID_28F128J3A, _16M, 128, REGULAR, 0, NULL, MV_TRUE, 32 }, +{SST_MANUF, SST_39VF_020, _256K, 64, REGULAR, 0, NULL, MV_FALSE, 0 }, +{AMD_MANUF, AMD_FID_LV040B, _512K, 8, REGULAR, 0, NULL, MV_FALSE, 0 }, +{STM_MANUF, STM_FID_29W040B, _512K, 8, REGULAR, 0, NULL, MV_FALSE, 0 }, +{AMD_MANUF, AMD_S29GL128N, _16M, 128, REGULAR, 0, NULL, MV_FALSE}, +{MX_MANUF, AMD_FID_MIRROR, _16M, 256, REGULAR, 0, NULL, MV_FALSE}, +{STM_MANUF, AMD_FID_MIRROR, _16M, 256, REGULAR, 0, NULL, MV_FALSE}, +{LAST_FLASH, LAST_FLASH, 0, 0, REGULAR, 0, NULL, MV_FALSE, 0 } +}; + +static MV_STATUS flashReset(MV_FLASH_INFO *pFlash); +static MV_STATUS flashStructGet(MV_FLASH_INFO *pFlash, MV_U32 manu, MV_U32 id); +static MV_STATUS flashSecsInit(MV_FLASH_INFO *pFlash); +static MV_BOOL flashSecLockGet(MV_FLASH_INFO *pBlock,MV_U32 secNum); +static MV_STATUS mvFlashProg(MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U32 data); +static MV_U32 flashGetHwBuffSize(MV_FLASH_INFO *pFlash); +static MV_STATUS flashHwBufferProg(MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U32 byteCount, + MV_U8 *pData); + +/******************************************************************************* +* mvFlashInit - Initialize a flash descriptor structure. +* +* DESCRIPTION: +* This function intialize flash info struct with specified flash +* parameters. This structure is used to identify the target flash the +* function refers to. This allow the use of the same API for multiple +* flash devices. +* +* +* INPUT: +* pFlash->baseAddr - Flash base address. +* pFlash->busWidth - Flash bus width (8, 16, 32 bit). +* pFlash->devWidth - Flash device width (8 or 16 bit). +* +* OUTPUT: +* pFlash - Flash identifier structure. +* +* RETURN: +* 32bit describing flash size. +* In case of any error, it returns 0. +* +*******************************************************************************/ +MV_U32 mvFlashInit(MV_FLASH_INFO *pFlash) +{ + MV_U32 manu = 0, id = 0; + + if(NULL == pFlash) + return 0; + + DB(mvOsOutput("Flash: mvFlashInit base 0x%x devW %d busW %d\n", + pFlash->baseAddr, pFlash->devWidth, pFlash->busWidth)); + + /* must init first sector base, before calling flashCmdSet */ + pFlash->sector[0].baseOffs = 0; + /* reset flash 0xf0(AMD) 0xff (Intel) */ + flashCmdSet(pFlash, 0, 0, 0xf0); + flashCmdSet(pFlash, 0, 0, 0xff); + + /* Write auto select command: read Manufacturer ID */ + /* AMD seq is: 0x555 0xAA -> 0x2AA 0x55 -> 0x555 0x90 */ + /* INTEL seq is dc 0x90 */ + flashCmdSet(pFlash, 0x555, 0, 0xAA); + flashCmdSet(pFlash, 0x2AA, 0, 0x55); + flashCmdSet(pFlash, 0x555, 0, 0x90); + + + /* Write auto select command: read Manufacturer ID */ + /* SST seq is: 0x5555 0xAA -> 0x2AAA 0x55 -> 0x5555 0x90 */ + flashCmdSet(pFlash, 0x5555, 0, 0xAA); + flashCmdSet(pFlash, 0x2AAA, 0, 0x55); + flashCmdSet(pFlash, 0x5555, 0, 0x90); + + DB(mvOsOutput("Flash: mvFlashInit base 0x%x devW %d busW %d\n", + pFlash->baseAddr, pFlash->devWidth, pFlash->busWidth)); + + + /* get flash Manufactor and Id */ + manu = flashBusWidthRd(pFlash, mvFlashBaseAddrGet(pFlash)); + DB(mvOsOutput("Flash: mvFlashInit base 0x%x devW %d busW %d\n", + pFlash->baseAddr, pFlash->devWidth, pFlash->busWidth)); + + + /* Some Micron flashes don't use A0 address for Identifier and + Lock information, so in order to read Identifier and lock information + properly we will do the following workarround: + If our device width is 1 (x8) then if address 0 equal to address 1 + and address 2 equal to address 3 ,then we have this case (A0 is not used) + and then we will issue the address without A0 to read the Identifier and + lock information properly*/ + DB(mvOsOutput("Flash: mvFlashInit base 0x%x devW %d busW %d\n", + pFlash->baseAddr, pFlash->devWidth, pFlash->busWidth)); + + + if ((pFlash->devWidth == 1) && + ((flashBusWidthRd(pFlash, flashAddrExt(pFlash, 0, 0)) == + flashBusWidthRd(pFlash, flashAddrExt(pFlash, 1, 0)))&& + (flashBusWidthRd(pFlash, flashAddrExt(pFlash, 2, 0)) == + flashBusWidthRd(pFlash, flashAddrExt(pFlash, 3, 0))))) + { + id = flashBusWidthRd(pFlash, flashAddrExt(pFlash, 2, 0)); + + } else id = flashBusWidthRd(pFlash, flashAddrExt(pFlash, 1, 0)); + + + /* check if this flash is Supported, and Init the pFlash flash feild */ + if( MV_OK != flashStructGet(pFlash, manu, id ) ) + { + mvOsPrintf("%s: Flash ISN'T supported: manufactor-0x%x, id-0x%x\n", + __FUNCTION__, manu, id); + return 0; + } + DB(mvOsOutput("Flash: mvFlashInit base 0x%x devW %d busW %d\n", + pFlash->baseAddr, pFlash->devWidth, pFlash->busWidth)); + + + /* Init pFlash sectors */ + if(MV_OK != flashSecsInit(pFlash)) + { + mvOsPrintf("Flash: ERROR mvFlashInit flashSecsInit failed \n"); + return 0; + } + + DB(mvOsOutput("Flash: mvFlashInit base 0x%x devW %d busW %d\n", + pFlash->baseAddr, pFlash->devWidth, pFlash->busWidth)); + + + /* print all flash information */ + DB(flashPrint(pFlash)); + + /* reset the Flash */ + flashReset(pFlash); + DB(mvOsOutput("Flash: mvFlashInit base 0x%x devW %d busW %d\n", + pFlash->baseAddr, pFlash->devWidth, pFlash->busWidth)); + + + return mvFlashSizeGet(pFlash); +} + + +/* erase */ +/******************************************************************************* +* mvFlashErase - Completly Erase a flash. +* +* DESCRIPTION: +* This function completly erase the given flash, by erasing all the +* flash sectors one by one (Currently there is no support for HW +* flash erase). +* +* INPUT: +* pFlash - Flash identifier structure. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if pFlash is NULL, +* MV_OK if erased completed successfully, +* MV_FAIL otherwise. +* +*******************************************************************************/ +MV_STATUS mvFlashErase(MV_FLASH_INFO *pFlash) +{ + MV_U32 i; + + if(NULL == pFlash) + return MV_BAD_PARAM; + + DB(mvOsPrintf("Flash: mvFlashErase \n")); + /* erase all sectors in the flash one by one */ + for(i = 0; i < mvFlashNumOfSecsGet(pFlash); i++) + { + if( MV_OK != mvFlashSecErase(pFlash,i) ) + return MV_FAIL; + } + + return MV_OK; +} + +/******************************************************************************* +* flashIsSecErased - Check if a given Sector is erased. +* +* DESCRIPTION: +* Go over the sector and check if its entire data is 0xFF. +* INPUT: +* secNum - sector Number. +* pFlash - flash information. +* +* OUTPUT: +* None +* +* RETURN: +* MV_BAD_PARAM if one of the inputs values is illegal, +* MV_TRUE if sector is already erased, +* MV_FALSE otherwise. +* +*******************************************************************************/ +MV_BOOL flashIsSecErased(MV_FLASH_INFO *pFlash, MV_U32 secNum) +{ + MV_U32 i; + + DB(mvOsPrintf("Flash: flashIsSecErased. \n")); + if((NULL == pFlash) || (secNum >= mvFlashNumOfSecsGet(pFlash)) ) + return MV_BAD_PARAM; + + /* reset the flash */ + flashReset(pFlash); + + /* go over the sector */ + for(i = mvFlashSecOffsGet(pFlash,secNum); + i < mvFlashSecOffsGet(pFlash,secNum) + mvFlashSecSizeGet(pFlash,secNum); + i+= 4) + { + if(mvFlash32Rd(pFlash,i) != FLASH_WR_ERASED ) + { + DB(mvOsPrintf("Flash: Not erased addr %x is %x \n", + i ,mvFlash32Rd(pFlash,i))); + return MV_FALSE; + } + } + return MV_TRUE; +} + + +/******************************************************************************* +* mvFlashSecErase - Erase a flash sector. +* +* DESCRIPTION: +* This function checks if the sector isn't protected and if the sector +* isn't already erased. +* +* INPUT: +* pFlash - Flash identifier structure. +* sectorNum - secrot number to erase. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if one of the inputs values is illegal, +* MV_OK if erased completed successfully, +* MV_FAIL otherwise (e.g. sector protected). +* +*******************************************************************************/ +MV_STATUS mvFlashSecErase(MV_FLASH_INFO *pFlash, MV_U32 sectorNum) +{ + MV_U32 status; + DB(mvOsPrintf("Flash: mvFlashSecErase \n")); + + /* check parametrs values */ + if((NULL == pFlash) || (sectorNum >= mvFlashNumOfSecsGet(pFlash)) ) { + return MV_BAD_PARAM; + } + + /* check if sector is locked */ + if(MV_TRUE == mvFlashSecLockGet(pFlash, sectorNum)) + { + mvOsPrintf("Flash: ERROR mvFlashSecErase protected sector.\n"); + return MV_FAIL; + } + /* check if already erased */ + if(MV_TRUE == flashIsSecErased(pFlash,sectorNum)) + { + DB(mvOsPrintf("Flash: FlashSecErase sector already erased \n")); + return MV_OK; + } + + /* erase sector using the Flash Ven Alg. */ + switch(mvFlashVenIdGet(pFlash)) + { + case INTEL_MANUF: /* INTEL/MT */ + status = intelFlashSecErase(pFlash,sectorNum); + break; + case AMD_MANUF: + case STM_MANUF: + case SST_MANUF: + case MX_MANUF: + status = amdFlashSecErase(pFlash,sectorNum); + break; + default: + mvOsPrintf("Flash: ERROR mvFlashErase. unsupported flash vendor\n"); + return MV_FAIL; + } + /* reset the flash */ + flashReset(pFlash); + + return status; +} + +/* write */ +/******************************************************************************* +* mvFlash32Wr - Write 32bit (word) to flash. +* +* DESCRIPTION: +* This function writes 32bit data to a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* data - 32bit data to be written to flash. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if one of the inputs values is illegal, +* MV_OK if write completed successfully, +* MV_FAIL otherwise (e.g. sector protected). +* +*******************************************************************************/ +MV_STATUS mvFlash32Wr(MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U32 data) +{ + MV_U32 i, status = MV_OK, temp,secNum; + + DB(mvOsPrintf("Flash: mvFlash32Wr offset %x data %x \n",offset,data)); + + /* check that the offset is aligned to 32 bit */ + if((NULL == pFlash) || (offset % 4)) + return MV_BAD_PARAM; + + secNum = mvFlashInWhichSec(pFlash,offset); + + DB(mvOsPrintf("Flash: mvFlashProg \n")); + /* check if offset is in flash range */ + if( secNum >= mvFlashNumOfSecsGet(pFlash)) + { + DB(mvOsPrintf("Flash: mvFlashProg offset out of flash range \n")); + return MV_BAD_PARAM; + } + + /* check if sector is locked */ + if(MV_TRUE == mvFlashSecLockGet(pFlash, secNum) ) + { + mvOsPrintf("Flash: ERROR mvFlashProg protected sector.\n"); + return MV_FAIL; + } + + /* check if offset is erased enough */ + if((mvFlash32Rd(pFlash, offset) & data) != data ) + { + mvOsPrintf("%s ERROR: offset 0x%x (sector %d) isn't erased !!!.\n", + __FUNCTION__, offset, secNum); + return MV_FAIL; + } + + + /* bus width is 32 bit */ + if(mvFlashBusWidthGet(pFlash) == 4) + { + data = MV_32BIT_BE(data); + status = mvFlashProg(pFlash, offset,data); + if (status != MV_OK ) + { + mvOsPrintf("%s ERROR: mvFlashProg() status %x \n", + __FUNCTION__, status); + } + } + + /* bus width is 16 bit */ + else if(mvFlashBusWidthGet(pFlash) == 2) + { + for(i = 0; i < 2; i++) + { + /* 0x44556677 -> [44][55][66][77] */ + temp = MV_16BIT_BE(((data >> (16*(1-i))) & FLASH_MASK_16BIT)); + if(MV_OK != mvFlashProg(pFlash, offset + (i*2), temp) ) + { + status = MV_FAIL; + break; + } + } + } + /* bus width is 8 bit */ + else if(mvFlashBusWidthGet(pFlash) == 1) + { + for(i = 0; i < 4; i++) + { + /* 0x44556677 -> [44][55][66][77] */ + temp = ((data >> (8*(3-i))) & FLASH_MASK_8BIT); + if(MV_OK != mvFlashProg(pFlash, offset + i, temp )) + { + status = MV_FAIL; + } + } + } + /* bus width isn't 8/16/32 */ + else + { + DB(mvOsPrintf("Flash: mvFlashWordWr no support for for bus width %d \n", + mvFlashBusWidthGet(pFlash) )); + status = MV_FAIL; + } + /* reset the flash */ + flashReset(pFlash); + + if (status != MV_OK ) + { + mvOsPrintf("mvFlash32Wr: ERROR #### status %x \n", status ); + } + + return status; +} + +/******************************************************************************* +* mvFlash16Wr - Write 16bit (short) to flash. +* +* DESCRIPTION: +* This function writes 16bit data to a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* sdata - 16bit data to be written to flash. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if one of the inputs values is illegal, +* MV_OK if write completed successfully, +* MV_FAIL otherwise (e.g. sector protected). +* +*******************************************************************************/ +MV_STATUS mvFlash16Wr(MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U16 sdata) +{ + MV_U32 temp,shiftSdata; + + DB(mvOsPrintf("Flash: mvFlash16Wr\n")); + + /* check that the offset is aligned to 16 bit */ + if((NULL == pFlash) || (offset % 2)) + return MV_BAD_PARAM; + + /* sdata shift in 32 bit aligned. i.e. */ + /* wr 0x9922 to 0xf4000002 -> 0xf4000000: qqqq9999 */ + shiftSdata = (1 - ((offset & 0x2)>>1) ) * 16; + /* read 32 bit aligned */ + temp = mvFlash32Rd(pFlash, MV_ALIGN_DOWN(offset,4)); /* aligned to 32 bit */ + /* write 16 bit sdata into 32 bit */ + temp &= temp & ~(0xffff << shiftSdata); + temp |= sdata << shiftSdata; + + /* write 32 bit */ + return mvFlash32Wr(pFlash,MV_ALIGN_DOWN(offset,4),temp); +} + +/******************************************************************************* +* mvFlash8Wr - Write 8bit (char) to flash. +* +* DESCRIPTION: +* This function writes 8bit data to a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* cdata - 8bit data to be written to flash. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if one of the inputs values is illegal, +* MV_OK if write completed successfully, +* MV_FAIL otherwise (e.g. sector protected). +* +*******************************************************************************/ +MV_STATUS mvFlash8Wr(MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U8 cdata) +{ + MV_U32 temp, shiftCdata; + + DB(mvOsPrintf("Flash: mvFlash8Wr\n")); + /* check that the offset is aligned to 16 bit */ + if(NULL == pFlash) + return MV_BAD_PARAM; + + /* cdata shift in 32 bit aligned. i.e. */ + /* wr 0x99 to 0xf4000003 -> 0xf4000000: qqqqqq99 */ + shiftCdata = (3 - (offset & 0x3)) * 8; + /* read 32 bit aligned */ + temp = mvFlash32Rd(pFlash, MV_ALIGN_DOWN(offset,4)); /* aligned to 32 bit */ + /* write 16 bit sdata into 32 bit */ + temp &= temp & ~(0xff << shiftCdata); + temp |= cdata << shiftCdata; + /* write 32 bit */ + return mvFlash32Wr(pFlash,MV_ALIGN_DOWN(offset,4),temp); +} + +/******************************************************************************* +* mvFlashBlockUnbufWr - Write a block to flash. Unbuffered +* +* DESCRIPTION: +* This function writes a block of data to a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* blockSize - Size of block in bytes. +* pBlock - Pointer to data block to be written to flash. +* +* OUTPUT: +* None. +* +* RETURN: +* The number of bytes written to flash. +* +*******************************************************************************/ +MV_U32 mvFlashBlockUnbufWr(MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, + MV_U8 *pBlock) +{ + MV_U32 i, j, temp = 0; + + DB(mvOsPrintf("Flash: mvFlashBlockWr\n")); + if(NULL == pFlash) + return 0; + +#ifndef CONFIG_MARVELL + if(NULL == pBlock) + return 0; +#endif + + for(i = 0; i < blockSize; ) + { + if( ((offset + i) % 4) || ((blockSize - i) < 4) )/* unaligned to 32 bit*/ + { + DB(mvOsPrintf("Flash: mvFlashBlockWr not aligned\n")); + if(MV_OK != mvFlash8Wr(pFlash, offset + i, pBlock[i]) ) + { + DB(mvOsPrintf("Flash: mvFlashBlockWr failed in writing char\n")); + return i; + } + i++; + } + else /* aligned to 32 bit */ + { + temp = 0; + /* to make sure we don't write to un aligned address */ + for(j = 0; j < 4; j++) + { + /* [44][55][66][77] -> 0x44556677 */ + temp |= (pBlock[i+j] & FLASH_MASK_8BIT ) << (8*(3-j)) ; + } + if( MV_OK != mvFlash32Wr(pFlash, offset + i, temp)) + { + DB(mvOsPrintf("Flash: mvFlashBlockWr failed in writing word\n")); + return i; + } + i += 4; + } + } + + return i; +} + + +/******************************************************************************* +* mvFlashBlockWr - Write a block to flash. +* +* DESCRIPTION: +* This function writes a block of data to a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* blockSize - Size of block in bytes. +* pBlock - Pointer to data block to be written to flash. +* +* OUTPUT: +* None. +* +* RETURN: +* The number of bytes written to flash. +* +*******************************************************************************/ +MV_U32 mvFlashBlockWr(MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, + MV_U8 *pBlock) +{ + MV_U32 numOfBytesWritten = 0; + MV_U32 secNum; /* lastOffset;*/ + MV_U32 i; + MV_U32 hwBuffSize, sizeToWrite; + MV_U32 unBufWritten= 0; + MV_U8 *pTmpBlock = NULL; + + DB(mvOsPrintf("Flash: mvFlashBlockWr\n")); + if(NULL == pFlash) + return 0; + +#ifndef CONFIG_MARVELL + if(NULL == pBlock) + return 0; +#endif + + /* check if any of the dest sectors is protected */ + /*lastOffset = ((MV_U32)pBlock) + blockSize;*/ + secNum = mvFlashInWhichSec(pFlash,offset); + do + { + if( MV_TRUE == mvFlashSecLockGet(pFlash, secNum) ) + { + mvOsPrintf("Flash: ERROR mvFlashProg protected sector.\n"); + return 0; + } + + /* next sec base offset */ + i = mvFlashSecOffsGet(pFlash, secNum) + + mvFlashSecSizeGet(pFlash, secNum); + secNum++; + + } while (i < blockSize); + + hwBuffSize = flashGetHwBuffSize(pFlash); + + /* if no HW buffer support, then call unbuffer routine*/ + if (hwBuffSize == 0) + { + return mvFlashBlockUnbufWr(pFlash, offset, blockSize, + pBlock); + + } + + flashReset(pFlash); + + + /* now write unbuffered the unaligned data*/ + while (((offset % hwBuffSize) || (blockSize < hwBuffSize))&&(blockSize)) + { + DB(mvOsPrintf("if I: offset = 0x%x, blockSize= 0x%x\n", + offset,blockSize)); + + if ((blockSize < hwBuffSize)|| + ((offset + blockSize) < (offset + (2*hwBuffSize + (offset / hwBuffSize))))) + { + sizeToWrite = blockSize; + } + else sizeToWrite = hwBuffSize - (offset % hwBuffSize); + + + unBufWritten = mvFlashBlockUnbufWr(pFlash, offset, sizeToWrite, + pBlock); + + flashReset(pFlash); + + blockSize -= unBufWritten; + offset += unBufWritten; + pBlock += unBufWritten; + numOfBytesWritten += unBufWritten; + + if (unBufWritten != sizeToWrite) return numOfBytesWritten; + + + } + + if (blockSize) + { + /* now write buffered the aligned data*/ + sizeToWrite = blockSize - (blockSize % hwBuffSize); + + /* Check source addr, in case source is in the FLASH */ + /* First copy the data to a temporary container in the SDRAM */ + /* and only then copy the data from the SDRAM to the FLASH */ + if (((MV_U32)pBlock >= mvFlashBaseAddrGet(pFlash)) && + ((MV_U32)pBlock < (mvFlashBaseAddrGet(pFlash) + mvFlashSizeGet(pFlash)))) + { + /* Malloc memory */ + if (NULL == (pTmpBlock=mvOsMalloc(sizeToWrite))) + { + DB(mvOsPrintf("mvFlashBlockWr: Malloc temporary container failed\n")); + flashReset(pFlash); + return numOfBytesWritten; + } + /* Copy data to SDRAM */ + memcpy(pTmpBlock, pBlock, sizeToWrite); + /* Change source pointer to SDRAM */ + } + else + /* Source address is not in flash */ + pTmpBlock = pBlock; + + /* Write data to flash */ + if ( MV_OK != flashHwBufferProg(pFlash, offset, + sizeToWrite, pTmpBlock) ) + { + DB(mvOsPrintf("mvFlashBlockWr: flashHwBufferProg failed\n")); + flashReset(pFlash); + return numOfBytesWritten; + } + /* Free memory only if used SDRAM container */ + if (pTmpBlock != pBlock) + mvOsFree(pTmpBlock); + + flashReset(pFlash); + + blockSize -= sizeToWrite; + offset += sizeToWrite; + pBlock += sizeToWrite; + numOfBytesWritten += sizeToWrite; + + } + + + /* now write unbuffered the rest*/ + if (blockSize) + { + unBufWritten = mvFlashBlockUnbufWr(pFlash, offset, blockSize, + pBlock); + + flashReset(pFlash); + + blockSize -= unBufWritten; + offset += unBufWritten; + pBlock += unBufWritten; + numOfBytesWritten += unBufWritten; + + } + + + return numOfBytesWritten; +} + + +/* read */ +/******************************************************************************* +* mvFlash32Rd - Read a 32bit (word) from flash. +* +* DESCRIPTION: +* This function reads 32bit (word) data from a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit data read from flash. +* +*******************************************************************************/ +MV_U32 mvFlash32Rd(MV_FLASH_INFO *pFlash, MV_U32 offset) +{ + MV_U32 val; + + DB(mvOsPrintf("Flash: mvFlashWordRd %x\n",offset)); + if(NULL == pFlash) + return 0; + + val = MV_FL_32_DATA_READ(offset + mvFlashBaseAddrGet(pFlash)); + + return MV_32BIT_BE(val); +} + +/******************************************************************************* +* mvFlash16Rd - Read a 16bit (short) from flash. +* +* DESCRIPTION: +* This function reads 16bit (short) data from a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit data read from flash. +* +*******************************************************************************/ +MV_U16 mvFlash16Rd (MV_FLASH_INFO *pFlash,MV_U32 offset) +{ + MV_U32 val; + + if(NULL == pFlash) + return 0; + + val = MV_FL_16_DATA_READ(offset + mvFlashBaseAddrGet(pFlash)); + + return MV_16BIT_BE(val); +} + +/******************************************************************************* +* mvFlash8Rd - Read a 8bit (char) from flash. +* +* DESCRIPTION: +* This function reads 8bit (char) data from a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* +* OUTPUT: +* None. +* +* RETURN: +* 8bit data read from flash. +* 0 if pflash is NULL. +* +*******************************************************************************/ +MV_U8 mvFlash8Rd (MV_FLASH_INFO *pFlash, MV_U32 offset) +{ + if(NULL == pFlash) + return 0; + + return MV_FL_8_DATA_READ(offset + mvFlashBaseAddrGet(pFlash)); +} + +/******************************************************************************* +* mvFlashBlockRd - Read a block of data from flash. +* +* DESCRIPTION: +* This function reads a block of data from given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* blockSize - Size of block in bytes. +* +* OUTPUT: +* pBlock - Pointer to data block to be read from flash. +* +* RETURN: +* The number of bytes read from flash. +* +*******************************************************************************/ +MV_U32 mvFlashBlockRd (MV_FLASH_INFO *pFlash, MV_U32 offset,MV_U32 blockSize, + MV_U8 *pBlock) +{ + MV_U32 i, j, temp; + + if((NULL == pFlash) || (NULL == pBlock)) + return 0; + + for(i = 0; i < blockSize; ) + { + if( ((offset + i) % 4) || ((blockSize - i) < 4) )/* unaligned to 32 bit*/ + { + DB(mvOsPrintf("Flash: mvFlashBlockRd not aligned\n")); + pBlock[i] = mvFlash8Rd(pFlash, offset + i); + i++; + } + else /* aligned to 32 bit */ + { + temp = mvFlash32Rd(pFlash, offset + i); + /* to make sure we don't write to un aligned address */ + for(j = 0; j < 4; j++) + { + /* 0x44556677 -> [44][55][66][77] */ + pBlock[i+j] = (MV_U8)((temp >> (8*(3-j))) & FLASH_MASK_8BIT); + } + i += 4; + } + } + + return i; +} + +/******************************************************************************* +* mvFlashSecLockSet - Lock/Unlock a Sector in the flash for Writing. +* +* DESCRIPTION: +* Lock/Unlock a Sector in the flash for Writing. +* +* INPUT: +* pFlash - Flash identifier structure. +* secNum - Sector Number. +* enable - MV_TRUE for Lock MV_FALSE for un-lock. +* +* OUTPUT: +* None +* +* RETURN: +* MV_BAD_PARAM if pFlash is NULL, +* MV_OK if operation completed successfully, +* MV_FAIL otherwise +* +*******************************************************************************/ +MV_STATUS mvFlashSecLockSet(MV_FLASH_INFO *pFlash, MV_U32 secNum, MV_BOOL enable) +{ + MV_U32 status = MV_FAIL; + + DB(mvOsPrintf("Flash: mvFlashSecLockSet\n")); + if( (NULL == pFlash) || (secNum > mvFlashNumOfSecsGet(pFlash)) ) + return MV_BAD_PARAM; + + /* check if sector is locked */ + if(enable == mvFlashSecLockGet(pFlash, secNum) ) + { + DB(mvOsPrintf("already un/locked\n")); + return MV_OK; + } + + /* SW Lock */ + if( mvFlashIsHwLock(pFlash) == MV_FALSE) + { + pFlash->sector[secNum].protect = enable; + status = MV_OK; + } + else /* HW Lock */ + { + switch(mvFlashVenIdGet(pFlash)) + { + case INTEL_MANUF: /* INTEL / MT */ + status = intelFlashSecLock(pFlash,secNum,enable); + break; + default: + mvOsPrintf("%s ERROR: No support for flash vendor id=0x%x\n", + __FUNCTION__, mvFlashVenIdGet(pFlash)); + return MV_FAIL; + } + /* if completed successfully, updated SW structure */ + if( MV_OK == status ) + { + pFlash->sector[secNum].protect = enable; + } + + /* reset the flash */ + flashReset(pFlash); + } + + return status; +} + +/********************** statics APIs *******************************************/ +/******************************************************************************* +* flashReset - Reset the Flash. +* DESCRIPTION: +* Reset the flash (Inset it into read mode). +* +* INPUT: +* pFlash - flash information. +* +* OUTPUT: +* None +* +* RETURN: +* MV_FAIL - if flash Vendor isn't supported MV_OK otherwise. +* +*******************************************************************************/ +static MV_STATUS flashReset(MV_FLASH_INFO *pFlash) +{ + switch(mvFlashVenIdGet(pFlash)) + { + case INTEL_MANUF: /* INTEL/MT */ + intelFlashReset(pFlash); + break; + case AMD_MANUF: + case STM_MANUF: + case SST_MANUF: + amdFlashReset(pFlash); + break; + default: + mvOsPrintf("Flash: ERROR mvFlashErase unsupported flash vendor\n"); + return MV_FAIL; + } + return MV_OK; +} + +/******************************************************************************* +* flashStructGet - return flash structure information. +* +* DESCRIPTION: +* This function goes over the supported flash list and look for a flash +* with manufactor code = manu and id code = id if found it return the flash +* structure. +* +* INPUT: +* manu - Flash Manufactor. +* id - Flash ID. +* +* OUTPUT: +* pFlash - Flash structure. +* +* RETURN: +* MV_BAD_PARAM if pFlash is NULL, +* MV_OK if manufactor and id were found, +* MV_FAIL otherwise +* +*******************************************************************************/ +static MV_STATUS flashStructGet(MV_FLASH_INFO *pFlash, MV_U32 manu, MV_U32 id) +{ + MV_U32 i= 0; + + if(NULL == pFlash) + return MV_BAD_PARAM; + + DB(mvOsPrintf("Flash: flashStructGet manu 0x%x id 0x%x \n",manu,id)); + /* while its not the last supported flash */ + while((supFlashAry[i].flashVen != LAST_FLASH) || + (supFlashAry[i].flashId != LAST_FLASH)) + { + /* if supported flash manufactor and Id equal to manu and id break */ + if( (flashDataExt(pFlash, supFlashAry[i].flashVen) == manu) && + (flashDataExt(pFlash, supFlashAry[i].flashId) == id) ) + { + DB(mvOsPrintf("Flash: flashStructGet flash is supported.\n")); + pFlash->flashSpec = supFlashAry[i]; + return MV_OK; + } + i++; + } + + /* manu and id are not supported! */ + DB(mvOsPrintf("Flash: flashStructGet flash is not supported.\n")); + return MV_FAIL; +} + + +/******************************************************************************* +* flashSecsInit - Init the flash sector array in pFlash. +* +* DESCRIPTION: +* Init the sector array based on the sector type. +* +* INPUT: +* +* OUTPUT: +* pFlash - Flash sectors information. +* +* RETURN: +* MV_BAD_PARAM if pFlash or frag sector struct(if needed) are NULL, +* MV_OK otherwise +* +*******************************************************************************/ +static MV_STATUS flashSecsInit(MV_FLASH_INFO *pFlash) +{ + MV_U32 i, temp, base = 0; + MV_U32 restSecSize, initSize = 0; + MV_U32 *pSecFrag, numSecFrag, firstSec, lastSec , flashDevNum; + + if(NULL == pFlash) + return MV_BAD_PARAM; + + /* first Init the bottom or top sectors */ + if( mvFlashSecTypeGet(pFlash) != REGULAR ) /* BOTTOM or TOP */ + { + /* init sectors fragments parameters */ + numSecFrag = pFlash->flashSpec.secFragNum; + pSecFrag = pFlash->flashSpec.pSecSizeFragList; + if(NULL == pSecFrag) + { + mvOsPrintf("Flash: flashSecsInit missing frag sector list.\n"); + return MV_BAD_PARAM; + } + + /* In case we got more then one flash in parallel then each */ + /* fragment size will be "duplicated" */ + flashDevNum = mvFlashNumOfDevGet(pFlash); + + /* caculate the size of each sector in the rest of the flash sector */ + temp = 0; + for(i = 0; i < numSecFrag; i++) + { + temp += pSecFrag[i] * flashDevNum; + } + restSecSize = (mvFlashSizeGet(pFlash) - temp) / + (mvFlashNumOfSecsGet(pFlash) - numSecFrag); + + + if(mvFlashSecTypeGet(pFlash) == TOP) /* TOP */ + { + /* if TOP sec type the the last sector is fragmented */ + DB(mvOsPrintf("FLASH: initFlashSecs TOP Sector Type \n")); + base = mvFlashSizeGet(pFlash) - restSecSize; + temp = mvFlashNumOfSecsGet(pFlash) - numSecFrag; + + for(i = 0; i < numSecFrag; i++) + { + pFlash->sector[temp + i].baseOffs = base; + pFlash->sector[temp + i].size = + pSecFrag[(numSecFrag - 1)- i] * flashDevNum; + /* Init Protect feild */ + if(pFlash->flashSpec.HwProtect == MV_FALSE) /* SW Protect */ + { + pFlash->sector[i].protect = MV_FALSE; + } + else/* HW protect */ + { + pFlash->sector[i].protect=flashSecLockGet(pFlash, temp + i); + } + /*increment base and size of initialized sectors */ + base += pSecFrag[(numSecFrag - 1) - i] * flashDevNum; + initSize += pSecFrag[(numSecFrag - 1) - i] * flashDevNum; + } + /* prepare for rest of sector init */ + firstSec = 0; + lastSec = mvFlashNumOfSecsGet(pFlash) - numSecFrag; + base = 0; + + } + else if(mvFlashSecTypeGet(pFlash) == BOTTOM)/* BOTTOM */ + { + /* if BOTTOM sec type the the first sector is fragmented */ + DB(mvOsPrintf("FLASH: initFlashSecs BOTTOM Sector Type \n")); + + for(i = 0; i < numSecFrag; i++) + { + pFlash->sector[i].baseOffs = base; + pFlash->sector[i].size = pSecFrag[i] * flashDevNum; + /* Init Protect feild */ + if(pFlash->flashSpec.HwProtect == MV_FALSE) /* SW Protect */ + { + pFlash->sector[i].protect = MV_FALSE; + } + else/* HW protect */ + { + pFlash->sector[i].protect = flashSecLockGet(pFlash, i); + } + /*increment base and size of initialized sectors */ + base += pSecFrag[i] * flashDevNum; + initSize += pSecFrag[i] * flashDevNum; + } + /* prepare for rest of sector init */ + firstSec = numSecFrag; + lastSec = mvFlashNumOfSecsGet(pFlash); + } + else /* unknown Type */ + { + mvOsPrintf("FLASH: initFlashSecs Sector Type %d is unsupported\n.", + pFlash->flashSpec.secType); + return MV_BAD_PARAM; + } + + } + else /* REGULAR */ + { + DB(mvOsPrintf("FLASH: initFlashSecs REGULAR Sector Type \n")); + restSecSize = mvFlashSizeGet(pFlash) / mvFlashNumOfSecsGet(pFlash); + firstSec = 0; + lastSec = mvFlashNumOfSecsGet(pFlash); + } + + /* init the rest of the sectors */ + DB(mvOsPrintf("Flash: flashSecsInit main sector loop %d - %d \n", + firstSec,lastSec)); + for(i = firstSec; i < lastSec; i++) + { + pFlash->sector[i].baseOffs = base; + pFlash->sector[i].size = restSecSize; + /* Init Protect feild */ + if(pFlash->flashSpec.HwProtect == MV_FALSE) /* SW Protect */ + { + pFlash->sector[i].protect = MV_FALSE; + } + else/* HW protect */ + { + pFlash->sector[i].protect = flashSecLockGet(pFlash, i); + } + /*increment base */ + base += restSecSize; + } + + return MV_OK; +} + +/******************************************************************************* +* flashSecLockGet - Return a sector Lock Bit status. +* +* DESCRIPTION: +* Return a sector Lock Bit status. +* +* +* INPUT: +* pFlash - Flash structure. +* secNum - Sector Number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if lock is set +* MV_FALSE if lock isn't set +* +*******************************************************************************/ +static MV_BOOL flashSecLockGet(MV_FLASH_INFO *pFlash, MV_U32 secNum) +{ + MV_U32 status; + + /* check if sector is locked */ + if( ( NULL == pFlash) || (secNum >= mvFlashNumOfSecsGet(pFlash)) ) + return MV_BAD_PARAM; + + switch(mvFlashVenIdGet(pFlash)) + { + case INTEL_MANUF: /* INTEL / MT */ + status = intelFlashSecLockGet(pFlash,secNum); + break; + default: + mvOsPrintf("Flash: ERROR flashSecLockGet unsupported vendor\n"); + return MV_FAIL; + } + /* reset the flash */ + flashReset(pFlash); + + return status; + +} + +/******************************************************************************* +* mvFlashProg - Prog busWidth Bits into the address offest in the flash. +* +* DESCRIPTION: +* This function writes busWidth data to a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* data - 32bit data to be written to flash. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if one of the inputs values is illegal, +* MV_OK if program completed successfully, +* MV_FAIL otherwise (e.g. sector protected). +* +*******************************************************************************/ +static MV_STATUS mvFlashProg(MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U32 data) +{ + MV_U32 status; + + + switch(mvFlashVenIdGet(pFlash)) + { + case INTEL_MANUF: /* INTEL / MT */ + status = intelFlashProg(pFlash,offset,data); + break; + case AMD_MANUF: + case STM_MANUF: + case SST_MANUF: + status = amdFlashProg(pFlash,offset,data); + break; + default: + mvOsPrintf("Flash: ERROR mvFlashProg unsupported flash vendor\n"); + return MV_FAIL; + } + + return status; + +} + + +/******************************************************************************* +* flashHwBufferProg - Prog flash via hw flash hw buffer +* +* DESCRIPTION: +* This function writes to a given flash offset using flash hw buffer. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* data - 32bit data to be written to flash. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if one of the inputs values is illegal, +* MV_OK if program completed successfully, +* MV_FAIL otherwise (e.g. sector protected). +* +*******************************************************************************/ +static MV_STATUS flashHwBufferProg(MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U32 byteCount, + MV_U8 *pData) +{ + MV_U32 status; + + + switch(mvFlashVenIdGet(pFlash)) + { + case INTEL_MANUF: /* INTEL / MT */ + status = intelFlashHwBufferProg(pFlash, offset, byteCount, pData); + break; + default: + mvOsPrintf("Flash: ERROR flashHwBufferProg unsupported flash vendor\n"); + return MV_FAIL; + } + + return status; +} + + +/******************************************************************************* +* flashGetHwBuffSize - get supported flash write buffer size. +* DESCRIPTION: +* Returns supported flash write buffer size. +* +* INPUT: +* pFlash - flash information. +* +* OUTPUT: +* None +* +* RETURN: +* MV_U32 - supported buffer size +* +*******************************************************************************/ +static MV_U32 flashGetHwBuffSize(MV_FLASH_INFO *pFlash) +{ + + switch(mvFlashVenIdGet(pFlash)) + { + case INTEL_MANUF: /* INTEL / MT */ + return intelFlashGetHwBuffSize(pFlash); + break; + default: + return 0; + } +} diff --git a/board/mv_feroceon/mv_hal/norflash/mvFlash.h b/board/mv_feroceon/mv_hal/norflash/mvFlash.h new file mode 100644 index 0000000..c09768f --- /dev/null +++ b/board/mv_feroceon/mv_hal/norflash/mvFlash.h @@ -0,0 +1,96 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvFlashH +#define __INCmvFlashH + +#include "mvFlashCom.h" +#include "mvIntelFlash.h" +#include "mvAmdFlash.h" + +/** APIs **/ +/* Init */ +MV_U32 mvFlashInit (MV_FLASH_INFO *pFlash); +/* Erase */ +MV_STATUS mvFlashErase (MV_FLASH_INFO *pFlash); +MV_BOOL flashIsSecErased(MV_FLASH_INFO *pFlash, MV_U32 secNum); +MV_STATUS mvFlashSecErase (MV_FLASH_INFO *pFlash, MV_U32 sectorNum); +/* write */ +MV_STATUS mvFlash32Wr (MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U32 data); +MV_STATUS mvFlash16Wr (MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U16 sdata); +MV_STATUS mvFlash8Wr (MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U8 cdata); +MV_U32 mvFlashBlockWr (MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, MV_U8 *pBlock); +MV_U32 mvFlashBlockUnbufWr(MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, MV_U8 *pBlock); +/* read */ +MV_U32 mvFlash32Rd (MV_FLASH_INFO *pFlash, MV_U32 offset); +MV_U16 mvFlash16Rd (MV_FLASH_INFO *pFlash, MV_U32 offset); +MV_U8 mvFlash8Rd (MV_FLASH_INFO *pFlash, MV_U32 offset); +MV_U32 mvFlashBlockRd (MV_FLASH_INFO *pFlash, MV_U32 offset, MV_U32 blockSize, + MV_U8 *pBlock); +/* protection */ +MV_STATUS mvFlashSecLockSet(MV_FLASH_INFO *pFlash, MV_U32 secNum, + MV_BOOL enable); + + +#endif /* __INCmvFlashH */ diff --git a/board/mv_feroceon/mv_hal/norflash/mvFlashCom.c b/board/mv_feroceon/mv_hal/norflash/mvFlashCom.c new file mode 100644 index 0000000..f1142f7 --- /dev/null +++ b/board/mv_feroceon/mv_hal/norflash/mvFlashCom.c @@ -0,0 +1,650 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvFlashCom.h" +#include "mvIntelFlash.h" +#include "mvAmdFlash.h" + +#undef MV_DEBUG + +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + + +static MV_VOID sizePrint (MV_U32 size, MV_U8 *s); + +/******************************************************************************* +* mvFlashInWhichSec - Return which Sector rap the offset address. +* +* DESCRIPTION: +* +* INPUT: +* pFlash - Flash identifier structure. +* offset - offset address. +* +* OUTPUT: +* None +* +* RETURN: +* MV_U32 - The Sector Number that the offset sits in. +* BAD_SEC_NUM if not found. +* +*******************************************************************************/ +MV_U32 mvFlashInWhichSec(MV_FLASH_INFO *pFlash, MV_U32 offset) +{ + MV_U32 secNum; + if(NULL == pFlash) + return 0; + + for( secNum = 0; secNum < mvFlashNumOfSecsGet(pFlash); secNum++){ + if((offset >= mvFlashSecOffsGet(pFlash, secNum)) && + (offset < mvFlashSecOffsGet(pFlash, secNum) + + mvFlashSecSizeGet(pFlash, secNum)) ) + { + return secNum; + } + } + /* return illegal sector Number */ + return FLASH_BAD_SEC_NUM; +} + + +/**************************************************/ +/* get information from the MV_FLASH_INFO struct */ +/**************************************************/ +/* get the Number of Device which sits in parallel on the bus */ +MV_U32 mvFlashNumOfDevGet(MV_FLASH_INFO *pFlash) +{ + if(NULL == pFlash) + return 0; + if(mvFlashBusWidthGet(pFlash) >= mvFlashDevWidthGet(pFlash)) + return mvFlashBusWidthGet(pFlash) / mvFlashDevWidthGet(pFlash); + return 1; +} +/* get the Flash Lock type HW/SW */ +MV_BOOL mvFlashIsHwLock(MV_FLASH_INFO *pFlash) +{ + if(NULL == pFlash) + return MV_FALSE; + + return pFlash->flashSpec.HwProtect; +} +/* get the lock status of a sector in the flash */ +MV_BOOL mvFlashSecLockGet(MV_FLASH_INFO *pFlash, MV_U32 secNum) +{ + if((NULL == pFlash)|| (secNum > mvFlashNumOfSecsGet(pFlash)) ) + return MV_FALSE; + + return pFlash->sector[secNum].protect; +} +/* get the size of a sector in the flash */ +MV_U32 mvFlashSecSizeGet(MV_FLASH_INFO *pFlash, MV_U32 secNum) +{ + if((NULL == pFlash) || (secNum > mvFlashNumOfSecsGet(pFlash))) + return 0; + + return pFlash->sector[secNum].size; +} +/* get the num of sectors in the flash */ +MV_U32 mvFlashNumOfSecsGet(MV_FLASH_INFO *pFlash) +{ + if(NULL == pFlash) + return 0; + + return pFlash->flashSpec.sectorNum; +} +/* get the flash size */ +MV_U32 mvFlashSizeGet(MV_FLASH_INFO *pFlash) +{ + if(NULL == pFlash) + return 0; + + return pFlash->flashSpec.size * mvFlashNumOfDevGet(pFlash); +} +/* get the sector offset */ +MV_U32 mvFlashSecOffsGet(MV_FLASH_INFO *pFlash, MV_U32 secNum) +{ + if((NULL == pFlash)|| (secNum > mvFlashNumOfSecsGet(pFlash))) + return 0; + + return pFlash->sector[secNum].baseOffs; +} +/* get the sector types TOP/BOT/REG */ +FLASH_SEC_TYPE mvFlashSecTypeGet(MV_FLASH_INFO *pFlash) +{ + if(NULL == pFlash) + return 0; + + return pFlash->flashSpec.secType; +} +/* get the flash Vendor ID */ +MV_U32 mvFlashVenIdGet(MV_FLASH_INFO *pFlash) +{ + if(NULL == pFlash) + return 0; + + return pFlash->flashSpec.flashVen; +} +/* get the flash device id */ +MV_U32 mvFlashDevIdGet(MV_FLASH_INFO *pFlash) +{ + if(NULL == pFlash) + return 0; + + return pFlash->flashSpec.flashId; +} +/* get the flash base address */ +MV_U32 mvFlashBaseAddrGet(MV_FLASH_INFO *pFlash) +{ + if(NULL == pFlash) + return 0; + + return pFlash->baseAddr; +} +/* get the flash bus width */ +MV_U32 mvFlashBusWidthGet(MV_FLASH_INFO *pFlash) +{ + if(NULL == pFlash) + return 0; + + return pFlash->busWidth; +} +/* get the flash device width */ +MV_U32 mvFlashDevWidthGet(MV_FLASH_INFO *pFlash) +{ + if(NULL == pFlash) + return 0; + + return pFlash->devWidth; +} + + +/******************************************************************************* +* flashDataExt - Extend Data. +* DESCRIPTION: +* Should be used only for FLASH CFI command sequence. +* +* Prepare the Data according to the Flash Width and Bus Width. +* If flash width = 2 and bus width = 1 data = 0x55 -> data = 0x55 +* If flash width = 2 and bus width = 4 data = 0x55 -> data = 0x550055 +* If flash width = 1 and bus width = 4 data = 0x55 -> data = 0x55555555 +* +* INPUT: +* data - Data to be expended. +* pFlash - flash information. +* +* OUTPUT: +* None +* +* RETURN: +* MV_U32 - Data after extension. +* OxFFFFFFFF if pFlash is Null +* +*******************************************************************************/ +MV_U32 flashDataExt( MV_FLASH_INFO *pFlash, MV_U32 data) +{ + MV_U32 i; + if(NULL == pFlash) + return 0xFFFFFFFF; + + for(i = 0; i < pFlash->busWidth ; i+= pFlash->devWidth) + { + data |= data << 8*i; + } + return data; +} +/****************************************************************************** +* flashAddrExt - Extend Addr. +* DESCRIPTION: +* Should be used only for FLASH CFI command sequence. +* +* Prepare the Addr according to the Flash width and the bus width, +* and add the sector offset. +* If flash width = 2 and bus width = 1 then it means we are using 16 Bit +* flash in 8 Bit mode, we should make sure that we shift the addr in 1 bit +* since in 16 Bit flash A0 isn't connected. and A1 of the MV dev address will +* go to A1 of the Flash. +* If flash width = 2 and bus width = 4 then it means we are using 2 16 Bit +* flash, (for the 16 Bit flash A0 isn't connected) and since when we refer to +* address 0x4 we actually want to refer to 0x2 of each device, then we will +* connect A2 of the MV Dev addres to A1 of the flash. +* +* INPUT: +* addr - Addr to be expended. +* pFlash - flash information. +* secNum - Sector Number. +* +* OUTPUT: +* None +* +* RETURN: +* MV_U32 - Data after extension. +* 0 if pFlash is Null. +* +*******************************************************************************/ +MV_U32 flashAddrExt(MV_FLASH_INFO *pFlash, MV_U32 addr, MV_U32 secNum ) +{ + MV_U32 shift; + if(NULL == pFlash) + return 0; + + shift = (pFlash->busWidth > pFlash->devWidth ) ? + pFlash->busWidth : pFlash->devWidth; + addr = addr * shift; + + /* Add flash sector Offset.*/ + addr += (mvFlashSecOffsGet(pFlash,secNum) + mvFlashBaseAddrGet(pFlash)); + + return addr; +} + +/******************************************************************************* +* flashCmdSet - Write converted data to the flash converted address+sector base. +* +* DESCRIPTION: +* Convert data based on the bus width and the flash device width +* and write it to secoffset + converted address. +* Should be used only for FLASH command sequence. +* +* INPUT: +* addr - Address offset. +* secNum - In which sector the address is sitting. +* data - Data to be written. +* pFlash - flash information. +* +* OUTPUT: +* None +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID flashCmdSet(MV_FLASH_INFO *pFlash, MV_U32 addr, MV_U32 secNum, + MV_U32 data) +{ + if(NULL == pFlash) + return; + + /* prepare the Data according to the Flash Width and Bus Width. */ + data = flashDataExt(pFlash, data); + addr = flashAddrExt(pFlash, addr, secNum); + + flashBusWidthWr(pFlash,addr,data); + + return; +} + +/******************************************************************************* +* flashBusWidthRd - read BusWidth Bits from address. +* +* DESCRIPTION: +* read BusWidth Bits from address. Note that access to Flash registers +* is always in LE mode as the Flash registers are in LE mode. +* +* INPUT: +* addr - Address offset. +* pFlash - flash information. +* +* OUTPUT: +* None +* +* RETURN: +* MV_U32 - contain the Bus Width Bits read from the address. +* +*******************************************************************************/ +MV_U32 flashBusWidthRd(MV_FLASH_INFO *pFlash, MV_U32 addr) +{ + MV_U32 val; + + switch(pFlash->busWidth) + { + case 1: + val = (MV_U32)MV_FL_8_READ(addr); + break; + case 2: + val = (MV_U32)MV_FL_16_READ(addr); + break; + case 4: + val = MV_FL_32_READ(addr); + break; + default: + mvOsPrintf("%s ERROR: Bus Width %d Bytes isn't supported.\n", + __FUNCTION__, pFlash->busWidth); + return 0; + } + /* mvOsPrintf("Addr = 0x%x, val = 0x%x, width %d\n", addr, val, pFlash->busWidth); */ + + return val; +} + +/******************************************************************************* +* flashBusWidthWr - write BusWidth Bits from address. +* +* DESCRIPTION: +* write BusWidth Bits to address. Note that access to Flash registers +* is always in LE mode as the Flash registers are in LE mode. +* +* INPUT: +* addr - Address offset. +* data - data to be written. +* pFlash - flash information. +* +* OUTPUT: +* None +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID flashBusWidthWr(MV_FLASH_INFO *pFlash, MV_U32 addr, MV_U32 data) +{ + /* mvOsPrintf("Addr = 0x%x, data = 0x%x, width %d\n", addr, data, pFlash->busWidth); */ + switch(pFlash->busWidth) + { + case 1: + MV_FL_8_WRITE(addr,(MV_U8)data); + break; + case 2: + MV_FL_16_WRITE(addr,(MV_U16)data); + break; + case 4: + MV_FL_32_WRITE(addr,data); + break; + default: + mvOsPrintf("%s ERROR: Bus Width %d Bytes isn't supported.\n", + __FUNCTION__, pFlash->busWidth); + return; + } + + return ; +} + +/******************************************************************************* +* flashBusWidthDataWr - write BusWidth Bits of data from address. +* +* DESCRIPTION: +* This function is used to perform data write to Flash, not like +* flashBusWidthWr which is used for commands. +* +* INPUT: +* addr - Address offset. +* data - data to be written. +* pFlash - flash information. +* +* OUTPUT: +* None +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID flashBusWidthDataWr(MV_FLASH_INFO *pFlash, MV_U32 addr, MV_U32 data) +{ + /*mvOsPrintf("Addr = 0x%x, data = 0x%x, width %d\n", addr, data, pFlash->busWidth);*/ + switch(pFlash->busWidth) + { + case 1: + MV_FL_8_DATA_WRITE(addr,(MV_U8)data); + break; + case 2: + MV_FL_16_DATA_WRITE(addr,(MV_U16)data); + break; + case 4: + MV_FL_32_DATA_WRITE(addr,data); + break; + default: + mvOsPrintf("%s ERROR: Bus Width %d Bytes isn't supported.\n", + __FUNCTION__, pFlash->busWidth); + return; + } + + return ; +} + + +/******************************************************************************* +* flashPrint - Print flash information structure. +* +* DESCRIPTION: +* Prints all the feilds in the flash info structure. +* +* INPUT: +* pFlash - Flash information. +* +* OUTPUT: +* None +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID flashPrint(MV_FLASH_INFO *pFlash) +{ + MV_U32 i; + + + if ((NULL == pFlash) || (mvFlashVenIdGet(pFlash) == 0)) + { + mvOsOutput ("missing or unknown FLASH type\n"); + return; + } + + switch (mvFlashVenIdGet(pFlash)) { + case STM_MANUF: + mvOsOutput ("STM "); + break; + case AMD_MANUF: + mvOsOutput ("AMD "); + break; + case FUJ_MANUF: + mvOsOutput ("FUJITSU "); + break; + case INTEL_MANUF: + mvOsOutput ("INTEL "); + break; + case SST_MANUF: + mvOsOutput ("SST "); + break; + case MX_MANUF: + mvOsOutput ("MX "); + break; + default: + mvOsOutput ("Unknown Vendor 0x%x",mvFlashVenIdGet(pFlash)); + break; + } + + switch (mvFlashDevIdGet(pFlash)) { + case AMD_FID_LV040B: + mvOsOutput ("AM29LV040B (4 Mbit, bottom boot sect)"); + break; + case AMD_FID_LV400B: + mvOsOutput ("AM29LV400B (4 Mbit, bottom boot sect)"); + break; + case AMD_FID_LV400T: + mvOsOutput ("AM29LV400T (4 Mbit, top boot sector)"); + break; + case AMD_FID_LV800B: + mvOsOutput ("AM29LV800B (8 Mbit, bottom boot sect)"); + break; + case AMD_FID_LV800T: + mvOsOutput ("AM29LV800T (8 Mbit, top boot sector)"); + break; + case AMD_FID_LV160B: + mvOsOutput ("AM29LV160B (16 Mbit, bottom boot sect)"); + break; + case AMD_FID_LV160T: + mvOsOutput ("AM29LV160T (16 Mbit, top boot sector)"); + break; + case AMD_FID_LV320B: + mvOsOutput ("AM29LV320B (32 Mbit, bottom boot sect)"); + break; + case AMD_FID_LV320T: + mvOsOutput ("AM29LV320T (32 Mbit, top boot sector)"); + break; + case AMD_S29GL128N: + mvOsOutput ("SPANSION S29GL128N (128 Mbit) - AMD MirrorBit-compat"); + break; + case STM_FID_29W040B: + mvOsOutput ("M29W040B (4Mbit = 512K x 8) "); + break; + case INTEL_FID_28F320J3A: + mvOsOutput ("28F320J3A (32 Mbit)"); + break; + case INTEL_FID_28F640J3A: + mvOsOutput ("28F640J3A (64 Mbit)"); + break; + case INTEL_FID_28F128J3A: + mvOsOutput ("28F128J3A (128 Mbit)"); + break; + case INTEL_FID_28F128P30T: + mvOsOutput ("28F128P30 TOP (128 Mbit)"); + break; + case INTEL_FID_28F128P30B: + mvOsOutput ("28F128P30 BOTTOM (128 Mbit)"); + break; + case INTEL_FID_28F256P30T: + mvOsOutput ("28F256P30 TOP (256 Mbit)"); + break; +#if defined (DB_88F1281) + case INTEL_FID_28F256P30B: + mvOsOutput ("28F256P30 BOTTOM (128 Mbit)"); + break; +#else + case INTEL_FID_28F256P30B: + mvOsOutput ("28F256P30 BOTTOM (256 Mbit)"); + break; +#endif + case SST_39VF_020: + mvOsOutput ("SST39VF020 (2 Mbit)"); + break; + default: + mvOsOutput ("Unknown Chip Type id 0x%x",mvFlashDevIdGet(pFlash)); + break; + } + if(mvFlashNumOfDevGet(pFlash) > 1) + mvOsOutput(" X %d",mvFlashNumOfDevGet(pFlash)); + + mvOsOutput("\nSize: "); + sizePrint(mvFlashSizeGet(pFlash),(MV_U8*)" in "); + mvOsOutput("%d Sectors\n",mvFlashNumOfSecsGet(pFlash)); + mvOsOutput("Bus Width: %dbit, device Width: %dbit, type: ", + (8 * mvFlashBusWidthGet(pFlash)), (8 * mvFlashDevWidthGet(pFlash))); + + switch (mvFlashSecTypeGet(pFlash)) { + case TOP: mvOsOutput ("TOP"); break; + case BOTTOM: mvOsOutput ("BOTTOM"); break; + case REGULAR: mvOsOutput ("REGULAR"); break; + default: mvOsOutput ("Unknown Type"); break; + } + mvOsOutput(".\n"); + + + mvOsOutput (" Sector Start Addresses:"); + for (i=0; i= 10) { + m -= 10; + n += 1; + } + + mvOsOutput ("%2d", n); + if (m) { + mvOsOutput (".%d", m); + } + mvOsOutput (" %cB%s", c, s); +} + diff --git a/board/mv_feroceon/mv_hal/norflash/mvFlashCom.h b/board/mv_feroceon/mv_hal/norflash/mvFlashCom.h new file mode 100644 index 0000000..79c168f --- /dev/null +++ b/board/mv_feroceon/mv_hal/norflash/mvFlashCom.h @@ -0,0 +1,164 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvFlashComH +#define __INCmvFlashComH + +#include "ctrlEnv/mvCtrlEnvLib.h" + + +/* Vendor Ids */ +#define AMD_MANUF 0x01 /* AMD manuf. ID in D23..D16, D7..D0 */ +#define FUJ_MANUF 0x04 /* FUJITSU manuf. ID in D23..D16, D7..D0 */ +#define ATM_MANUF 0x1F /* ATMEL */ +#define STM_MANUF 0x20 /* STM (Thomson) manuf. ID in D23.. -"- */ +#define SST_MANUF 0xBF /* SST manuf. ID in D23..D16, D7..D0 */ +#define MT_MANUF 0x89 /* MT manuf. ID in D23..D16, D7..D0 */ +#define INTEL_MANUF 0x89 /* INTEL manuf. ID in D23..D16, D7..D0 */ +#define INTEL_ALT_MANUF 0xB0 /* alternate INTEL namufacturer ID */ +#define MX_MANUF 0xC2 /* MXIC manuf. ID in D23..D16, D7..D0 */ +#define TOSH_MANUF 0x98 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */ + + +#define MAX_SECTOR_NUM 300 + +#define FLASH_BAD_SEC_NUM 0xFFFFFFFF +#define FLASH_WR_ERASED 0xFFFFFFFF +#define FLASH_MASK_16BIT 0xFFFF +#define FLASH_MASK_8BIT 0xFF +/* typedefs */ + +/* This structure describes a flash sector */ +typedef struct _mvFlashSector +{ + MV_U32 baseOffs; /* Sector base offset related to flash base. */ + MV_U32 size; /* sector size in bytes */ + MV_BOOL protect; /* Sector write protect indicator */ +}MV_FLASH_SECTOR; + +/* This structures describes a flash Sectors structure type */ +typedef enum flashSecType +{ + REGULAR, + BOTTOM, + TOP +}FLASH_SEC_TYPE; + +typedef struct flashStruct +{ + MV_U32 flashVen; /* AMD/Intel/... */ + MV_U32 flashId; /* Combined device & vendor ID */ + MV_U32 size; /* Total Flash size in bytes */ + MV_U32 sectorNum; /* Flash total sector number */ + FLASH_SEC_TYPE secType; /* Sector structure type */ + MV_U32 secFragNum; /* In case B/T flash then this is the Number */ + /* of Sector defined in the Frag list. */ + MV_U32 *pSecSizeFragList; /* a list of the sectors' sizes in the */ + /* B/T sector part. */ + MV_BOOL HwProtect; /* HW protection is supported */ + MV_U32 HwBuffLen; /* support for hw buffering (0 - not, */ + /* > 0 - hw buff length). */ +}FLASH_STRUCT; + +/* This struct describes a Flash device */ +typedef struct _mvFlashInfo +{ + FLASH_STRUCT flashSpec; + MV_U32 baseAddr; /* Flash base address */ + MV_FLASH_SECTOR sector[MAX_SECTOR_NUM]; /* Flash sector list */ + MV_U32 busWidth; /* Width of the Flash bus */ + MV_U32 devWidth; /* Width of single Flash device */ + +} MV_FLASH_INFO; + + + + +/* get info */ +MV_U32 mvFlashNumOfDevGet (MV_FLASH_INFO *pFlash); +MV_BOOL mvFlashIsHwLock (MV_FLASH_INFO *pFlash); +MV_BOOL mvFlashSecLockGet (MV_FLASH_INFO *pFlash, MV_U32 secNum); +MV_U32 mvFlashInWhichSec (MV_FLASH_INFO *pFlash, MV_U32 offset); +MV_U32 mvFlashSecSizeGet (MV_FLASH_INFO *pFlash, MV_U32 sectorNumber); +MV_U32 mvFlashNumOfSecsGet (MV_FLASH_INFO *pFlash); +MV_U32 mvFlashSizeGet (MV_FLASH_INFO *pFlash); +MV_U32 mvFlashSecOffsGet (MV_FLASH_INFO *pFlash, MV_U32 sectorNum); +MV_U32 mvFlashVenIdGet (MV_FLASH_INFO *pFlash); +MV_U32 mvFlashDevIdGet (MV_FLASH_INFO *pFlash); +MV_U32 mvFlashBaseAddrGet (MV_FLASH_INFO *pFlash); +MV_U32 mvFlashBusWidthGet (MV_FLASH_INFO *pFlash); +MV_U32 mvFlashDevWidthGet (MV_FLASH_INFO *pFlash); +FLASH_SEC_TYPE mvFlashSecTypeGet(MV_FLASH_INFO *pFlash); + +/* flash Utils */ +MV_U32 flashDataExt(MV_FLASH_INFO *pFlash, MV_U32 data); +MV_U32 flashAddrExt(MV_FLASH_INFO *pFlash, MV_U32 data, MV_U32 secNum); +MV_VOID flashCmdSet (MV_FLASH_INFO *pFlash, MV_U32 addr, MV_U32 secNum, + MV_U32 data); +MV_VOID flashPrint (MV_FLASH_INFO *pFlash); +MV_VOID flashBusWidthWr(MV_FLASH_INFO *pFlash, MV_U32 addr, MV_U32 data); +MV_VOID flashBusWidthDataWr(MV_FLASH_INFO *pFlash, MV_U32 addr, MV_U32 data); +MV_U32 flashBusWidthRd(MV_FLASH_INFO *pFlash, MV_U32 addr); + +#endif /* __INCmvFlashComH */ diff --git a/board/mv_feroceon/mv_hal/norflash/mvIntelFlash.c b/board/mv_feroceon/mv_hal/norflash/mvIntelFlash.c new file mode 100644 index 0000000..0b48bcb --- /dev/null +++ b/board/mv_feroceon/mv_hal/norflash/mvIntelFlash.c @@ -0,0 +1,518 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvFlash.h" + +#undef MV_DEBUG + +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_STATUS intelFlashStsGet(MV_FLASH_INFO *pFlash, MV_U32 sec, + MV_BOOL enableReadCommand, MV_U32* flashStatus); +static MV_VOID intelFlashStatusClr(MV_FLASH_INFO *pFlash); + +/******************************************************************************* +* reset the flash +*******************************************************************************/ +MV_VOID intelFlashReset(MV_FLASH_INFO *pFlash) +{ + flashCmdSet(pFlash, 0, 0, INTEL_CHIP_CMD_RST); + return; +} + +/******************************************************************************* +* intelFlashSecErase - Erase a sector. +* +* DESCRIPTION: +* Erase a Flash sector. +* +* INPUT: +* secNum - sector Number. +* pFlash - flash information. +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK if program completed successfully, +* MV_TIMEOUT if timeout reached, +* MV_FAIL otherwise. +* +*******************************************************************************/ +MV_STATUS intelFlashSecErase(MV_FLASH_INFO *pFlash, MV_U32 secNum) +{ + MV_U32 i, status, flashStatus; + + DB(mvOsPrintf("Flash: intelFlashSecErase\n")); + + /* clear status */ + intelFlashStatusClr(pFlash); + + /* erase sequence */ + flashCmdSet(pFlash, 0, secNum, INTEL_CHIP_CMD_ERASE1); + flashCmdSet(pFlash, 0, secNum, INTEL_CHIP_CMD_ERASE2); + + /* wait for erase to complete */ + for(i = 0; i < INTEL_EARASE_MILI_TIMEOUT; i++) + { + mvOsDelay(1); + status = intelFlashStsGet(pFlash, 0, MV_TRUE, &flashStatus); + if( MV_NOT_READY != status ) + return status; + } + mvOsPrintf("Flash: ERROR intelFlashSecErase timeout \n"); + + return MV_TIMEOUT; +} + +/******************************************************************************* +* intelFlashProg - Prog busWidth Bits into the address offest in the flash. +* +* DESCRIPTION: +* This function writes busWidth data to a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* data - 32bit data to be written to flash. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if program completed successfully, +* MV_TIMEOUT if timeout reached, +* MV_FAIL otherwise. +* +*******************************************************************************/ +MV_STATUS intelFlashProg(MV_FLASH_INFO *pFlash,MV_U32 offset, MV_U32 data) +{ + MV_U32 i, status, flashStatus; + + DB(mvOsPrintf("Flash: mvIntelFlashWr\n")); + + /* clear status */ + intelFlashStatusClr(pFlash); + + /* write sequence */ + flashCmdSet(pFlash, 0, 0, INTEL_CHIP_CMD_PROG); + flashBusWidthDataWr(pFlash, offset + mvFlashBaseAddrGet(pFlash), data); + + /* wait for write to complete */ + for(i = 0; i < INTEL_PROG_TIMEOUT; i++) + { + status = intelFlashStsGet(pFlash, 0, MV_TRUE, &flashStatus); + if( MV_NOT_READY != status ) + return status; + } + mvOsPrintf("Flash: ERROR intelFlashSecErase timeout \n"); + + return MV_TIMEOUT; +} + + +MV_U32 intelFlashGetHwBuffSize(MV_FLASH_INFO *pFlash) +{ + MV_U32 buffSize; + + buffSize = mvFlashNumOfDevGet(pFlash) * pFlash->flashSpec.HwBuffLen ; + return buffSize; +} + +/******************************************************************************* +* intelFlashBufferProg - Prog hw buff into the address offest in the flash. +* +* DESCRIPTION: +* This function writes busWidth data to a given flash offset. +* +* INPUT: +* pFlash - Flash identifier structure (flash cockie). +* offset - Offset from flash base address. +* pData - buffer (32 byte) data to be written to flash. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if program completed successfully, +* MV_BAD_PARAM illegal param +* MV_TIMEOUT if timeout reached, +* MV_FAIL otherwise. +* +*******************************************************************************/ +MV_STATUS intelFlashHwBufferProg(MV_FLASH_INFO *pFlash,MV_U32 offset, + MV_U32 byteCount, MV_U8* pData) +{ + MV_U32 i, status, flashStatus; + MV_U32 buffSize, sec, wordCount, busWidth; + MV_U32 offInBuff, absOffInFlash; + MV_U32 data, j; + + DB(mvOsPrintf("Flash: intelFlashBufferProg\n")); + + if ((buffSize = (intelFlashGetHwBuffSize(pFlash) )) == 0) + { + return MV_BAD_PARAM; + } + + if (0 != (byteCount % buffSize)) + { + return MV_BAD_PARAM; + } + + + + /* has to be aligned */ + if ((offset % buffSize) != 0) + { + return MV_BAD_PARAM; + } + +#ifndef CONFIG_MARVELL + if (pData == NULL) + { + return MV_BAD_PARAM; + } +#endif + + busWidth = mvFlashBusWidthGet(pFlash); + wordCount = (pFlash->flashSpec.HwBuffLen / mvFlashDevWidthGet(pFlash)); + absOffInFlash = mvFlashBaseAddrGet(pFlash) + offset; + offInBuff = 0; + + /* clear status */ + intelFlashStatusClr(pFlash); + + do + { + + /* Start the 'write to buffer' sequence */ + sec = mvFlashInWhichSec(pFlash,offset); + + i=0; + do + { + flashCmdSet(pFlash, 0, sec, INTEL_CHIP_CMD_WR_BUF); + + status = intelFlashStsGet(pFlash, sec, MV_FALSE, &flashStatus); + + if((i++ > INTEL_PROG_TIMEOUT)&&(status != MV_OK)) + { + DB(printf("intelFlashHwBufferProg1: Timeout:offset = 0x%x flashStatus =0x%x\n", + offset,flashStatus)); + return status; + } + + }while (status != MV_OK); + + + /* write num of words to write minus 1 */ + flashCmdSet(pFlash, 0, sec, wordCount - 1); + + for (i = 0; i < wordCount * mvFlashNumOfDevGet(pFlash); i += mvFlashNumOfDevGet(pFlash)) + { + data = 0; + switch (busWidth) + { + case 4: + for(j = 0; j < 4; j++) + { + /* [44][55][66][77] -> 0x44556677 */ + data |= (pData[offInBuff+j] & FLASH_MASK_8BIT ) << (8*(3-j)) ; + } + data = MV_32BIT_BE(data); + break; + case 2: + for(j = 0; j < 2; j++) + { + /* [44][55] -> 0x4455 */ + data |= (pData[offInBuff+j] & FLASH_MASK_8BIT ) << (8*(1-j)) ; + } + data = MV_16BIT_BE(data); + break; + case 1: + data = *(MV_U8*)(((MV_U32)pData) + offInBuff); + break; + } + flashBusWidthDataWr(pFlash, absOffInFlash, data); + + offInBuff += busWidth; + absOffInFlash += busWidth; + } + + flashCmdSet(pFlash, 0, sec, INTEL_CHIP_CMD_CONFIRM_BUF); + + /* check status */ + for(i = 0; i < INTEL_PROG_TIMEOUT; i++) + { + status = intelFlashStsGet(pFlash, sec, MV_FALSE, &flashStatus); + if ( status == MV_OK ) + break; + } + + if ( status != MV_OK ) break; + + byteCount -= buffSize; + }while(byteCount); + + + if ( status != MV_OK ) + { + + DB(printf("intelFlashHwBufferProg2: Timeout:offset = 0x%x flashStatus =0x%x\n", + offset,flashStatus)); + + return status; + } + + + return MV_OK; +} + + +/******************************************************************************* +* intelSecLockGet - Return a sector Lock Bit status. +* +* DESCRIPTION: +* Return a sector Lock Bit status. +* +* +* INPUT: +* pFlash - Flash structure. +* secNum - Sector Number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if lock is set +* MV_FALSE if lock isn't set +* +*******************************************************************************/ +MV_BOOL intelFlashSecLockGet(MV_FLASH_INFO *pFlash,MV_U32 secNum) +{ + MV_U32 status; + + DB(mvOsPrintf("Flash: intelSecLockGet sector %d\n",secNum)); + + /* clear status */ + intelFlashStatusClr(pFlash); + + /* Some Micron flashes don't use A0 address for Identifier and + Lock information, so in order to read Identifier and lock information + properly we will do the following workarround: + If our device width is 1 (x8) then if address 0 equal to address 1 + and address 2 equal to address 3 ,then we have this case (A0 is not used) + and then we will issue the address without A0 to read the Identifier and + lock information properly*/ + + /* read Query sequence */ + flashCmdSet(pFlash, 0, 0, INTEL_CHIP_CMD_RD_QUERY); + + if ((pFlash->devWidth == 1) && + ((flashBusWidthRd(pFlash, flashAddrExt(pFlash, 0, 0)) == + flashBusWidthRd(pFlash, flashAddrExt(pFlash, 1, 0)))&& + (flashBusWidthRd(pFlash, flashAddrExt(pFlash, 2, 0)) == + flashBusWidthRd(pFlash, flashAddrExt(pFlash, 3, 0))))) + { + status = flashBusWidthRd(pFlash, flashAddrExt(pFlash, 4, secNum)); + + } else status = flashBusWidthRd(pFlash, flashAddrExt(pFlash, 2, secNum)); + + + if((status & flashDataExt(pFlash,INTEL_CHIP_RD_ID_LOCK)) != 0) + { + DB(mvOsPrintf("Flash: intelSecLockGet sector %d is locked \n",secNum)); + return MV_TRUE; + } + + return MV_FALSE; +} +/******************************************************************************* +* intelSecLock - Lock/Unlock a Sector in the flash for Writing. +* +* DESCRIPTION: +* Lock/Unlock a Sector in the flash for Writing. +* +* INPUT: +* pFlash - Flash identifier structure. +* secNum - Sector Number. +* enable - MV_TRUE for Lock MV_FALSE for un-lock. +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK if program completed successfully, +* MV_TIMEOUT if timeout reached, +* MV_FAIL otherwise. +* +*******************************************************************************/ +MV_STATUS intelFlashSecLock(MV_FLASH_INFO *pFlash, MV_U32 secNum, MV_BOOL enable) +{ + MV_U32 status, intelLockEna, i, flashStatus; + + status = MV_ERROR; + + DB(mvOsPrintf("Flash: intelSecLock")); + + /* lock */ + if(enable == MV_TRUE) + { + DB(mvOsPrintf("Flash: intelSecLock Lock sector %d \n", secNum)); + intelLockEna = INTEL_CHIP_CMD_SET_LOCK_BLK; + } + else{ /* unlock */ + DB(mvOsPrintf("Flash: intelSecLock Unlock sector %d \n", secNum)); + intelLockEna = INTEL_CHIP_CMD_CLR_LOCK_BLK; + } + + /* clear status */ + intelFlashStatusClr(pFlash); + + /* Un/lock sequence */ + flashCmdSet(pFlash, 0, 0, INTEL_CHIP_CMD_LOCK); + flashCmdSet(pFlash, 0, secNum, intelLockEna); + + /* wait for write to complete */ + for(i = 0; i < INTEL_LOCK_MILI_TIMEOUT; i++) + { + mvOsDelay(1); + status = intelFlashStsGet(pFlash, 0, MV_TRUE, &flashStatus); + if(status != MV_NOT_READY) + break; + } + /* if timeout */ + if(i >= INTEL_LOCK_MILI_TIMEOUT) + { + mvOsPrintf("Flash: ERROR intelSecLock timeout \n"); + return MV_TIMEOUT; + } + /* if completed successfully */ + if( MV_OK == status ) + { + /* Unprotect one sector, which means unprotect all flash + * and reprotect the other protected sectors. + */ + if(enable == MV_FALSE) + { + for(i = 0; i < mvFlashNumOfSecsGet(pFlash); i++) + if((i != secNum) && (MV_TRUE == mvFlashSecLockGet(pFlash,i))) + if(MV_OK != intelFlashSecLock(pFlash,i,MV_TRUE)) + return MV_FAIL; + } + return MV_OK; + } + /* otherwise FAIL */ + return MV_FAIL; +} + +/******************************************************************************* +* Check the Flash Status and return: +* MV_OK if status is ready and there isn't any error. +* MV_FAIL if status is ready and there is an error. +* MV_NOT_READY if status isn't ready. +*******************************************************************************/ +static MV_STATUS intelFlashStsGet(MV_FLASH_INFO *pFlash ,MV_U32 sec, + MV_BOOL enableReadCommand, MV_U32* flashStatus) +{ + MV_U32 status; + + if ( enableReadCommand ) + flashCmdSet(pFlash, 0, 0, INTEL_CHIP_CMD_RD_STAT); + status = flashBusWidthRd(pFlash, pFlash->baseAddr + mvFlashSecOffsGet(pFlash,sec)); + + *flashStatus = status; + + if((status & flashDataExt(pFlash,INTEL_CHIP_STAT_RDY)) == + flashDataExt(pFlash,INTEL_CHIP_STAT_RDY)) + { + DB(mvOsPrintf("Flash: intelFlashStatusChk value is ready \n")); + if( (status & flashDataExt(pFlash,INTEL_CHIP_STAT_ERR)) != 0) + { + mvOsPrintf("Flash: intelFlashStatusChk value has ERROR %x \n", + status); + return MV_FAIL; + } + return MV_OK; + } + + DB(mvOsPrintf("Flash: intelFlashStatusChk staus is %x and should %x \n", + status,flashDataExt(pFlash,INTEL_CHIP_STAT_RDY))); + return MV_NOT_READY; +} + +/******************************************************************************* +* Clear the Flash Status. +*******************************************************************************/ +static MV_VOID intelFlashStatusClr(MV_FLASH_INFO *pFlash) +{ + flashCmdSet(pFlash, 0, 0, INTEL_CHIP_CMD_CLR_STAT); + return; +} + diff --git a/board/mv_feroceon/mv_hal/norflash/mvIntelFlash.h b/board/mv_feroceon/mv_hal/norflash/mvIntelFlash.h new file mode 100644 index 0000000..dbd413e --- /dev/null +++ b/board/mv_feroceon/mv_hal/norflash/mvIntelFlash.h @@ -0,0 +1,165 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvIntelFlashH +#define __INCmvIntelFlashH + +#include "mvFlashCom.h" + + +/* Mt Flash IDs */ +#define MT_FID_28F400_T 0x4470 /* 28F400B3 ID ( 4 M, top boot sector) */ +#define MT_FID_28F400_B 0x4471 /* 28F400B3 ID ( 4 M, bottom boot sect) */ + + +/* Intel Flash IDs */ +#define INTEL_FID_28F016S 0x66a0 /* 28F016S[VS] ID (16M = 512k x 16) */ +#define INTEL_FID_28F800B3T 0x8892 /* 8M = 512K x 16 top boot sector */ +#define INTEL_FID_28F800B3B 0x8893 /* 8M = 512K x 16 bottom boot sector */ +#define INTEL_FID_28F160B3T 0x8890 /* 16M = 1M x 16 top boot sector */ +#define INTEL_FID_28F160B3B 0x8891 /* 16M = 1M x 16 bottom boot sector */ +#define INTEL_FID_28F320B3T 0x8896 /* 32M = 2M x 16 top boot sector */ +#define INTEL_FID_28F320B3B 0x8897 /* 32M = 2M x 16 bottom boot sector */ +#define INTEL_FID_28F640B3T 0x8898 /* 64M = 4M x 16 top boot sector */ +#define INTEL_FID_28F640B3B 0x8899 /* 64M = 4M x 16 bottom boot sector */ +#define INTEL_FID_28F160F3B 0x88F4 /* 16M = 1M x 16 bottom boot sector */ + +#define INTEL_FID_28F800C3T 0x88C0 /* 8M = 512K x 16 top boot sector */ +#define INTEL_FID_28F800C3B 0x88C1 /* 8M = 512K x 16 bottom boot sector */ +#define INTEL_FID_28F160C3T 0x88C2 /* 16M = 1M x 16 top boot sector */ +#define INTEL_FID_28F160C3B 0x88C3 /* 16M = 1M x 16 bottom boot sector */ +#define INTEL_FID_28F320C3T 0x88C4 /* 32M = 2M x 16 top boot sector */ +#define INTEL_FID_28F320C3B 0x88C5 /* 32M = 2M x 16 bottom boot sector */ +#define INTEL_FID_28F640C3T 0x88CC /* 64M = 4M x 16 top boot sector */ +#define INTEL_FID_28F640C3B 0x88CD /* 64M = 4M x 16 bottom boot sector */ + +#define INTEL_FID_28F128J3 0x8918 /* 16M = 8M x 16 x 128 */ +#define INTEL_FID_28F320J5 0x0014 /* 32M = 128K x 32 */ +#define INTEL_FID_28F640J5 0x0015 /* 64M = 128K x 64 */ +#define INTEL_FID_28F320J3A 0x0016 /* 32M = 128K x 32 */ +#define INTEL_FID_28F640J3A 0x0017 /* 64M = 128K x 64 */ +#define INTEL_FID_28F128J3A 0x0018 /* 128M = 128K x 128 */ +#define INTEL_FID_28F256L18T 0x880D /* 256M = 128K x 255 + 32k x 4 */ + +#define INTEL_FID_28F160S3 0x00D0 /* 16M = 512K x 32 (64kB x 32) */ +#define INTEL_FID_28F320S3 0x00D4 /* 32M = 512K x 64 (64kB x 64) */ +#define INTEL_FID_28F128P30T 0x8818 /* 16M = 128K x 127 (32kB x 4) top boot sector */ +#define INTEL_FID_28F128P30B 0x881B /* 16M = 128K x 127 (32kB x 4) bottom boot sector */ +#define INTEL_FID_28F256P30T 0x8919 /* 32M = 128K x 255 (32kB x 4) top boot sector */ +#if defined (DB_88F1281) +#define INTEL_FID_28F256P30B 0x1C /* 16M = 64K x 255 (16kB x 4) bottom boot sector */ +#else +#define INTEL_FID_28F256P30B 0x891C /* 32M = 128K x 255 (32kB x 4) bottom boot sector */ +#endif + + +/* Intel Flash APIs timeouts*/ +#define INTEL_EARASE_MILI_TIMEOUT (8000*10) /* mili Sec */ +#define INTEL_PROG_TIMEOUT (0xA0000*10) /* number of loops */ +#define INTEL_LOCK_MILI_TIMEOUT (8000*10) /* mili Sec */ + +/* Commands */ +#define INTEL_CHIP_CMD_RST 0xFF /* reset flash */ +#define INTEL_CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */ +#define INTEL_CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */ +#define INTEL_CHIP_CMD_RD_STAT 0x70 /* read the status register */ +#define INTEL_CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */ +#define INTEL_CHIP_CMD_WR_BUF 0xE8 /* write buffer command */ +#define INTEL_CHIP_CMD_CONFIRM_BUF 0xD0 /* write buffer command */ +#define INTEL_CHIP_CMD_PROG 0x40 /* program word command */ +#define INTEL_CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */ +#define INTEL_CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */ +#define INTEL_CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ +#define INTEL_CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */ +#define INTEL_CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ +#define INTEL_CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ +#define INTEL_CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ + + + +/* status register bits */ +#define INTEL_CHIP_STAT_DPS 0x02 /* Device Protect Status */ +#define INTEL_CHIP_STAT_VPPS 0x08 /* VPP Status */ +#define INTEL_CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ +#define INTEL_CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ +#define INTEL_CHIP_STAT_ESS 0x40 /* Erase Suspend Status */ +#define INTEL_CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ + +#define INTEL_CHIP_STAT_ERR (INTEL_CHIP_STAT_VPPS | INTEL_CHIP_STAT_DPS | \ + INTEL_CHIP_STAT_ECLBS | INTEL_CHIP_STAT_PSLBS) + +/* Lock Configuration */ +#define INTEL_CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ + +MV_STATUS intelFlashSecErase(MV_FLASH_INFO *pFlash, MV_U32 secNum); +MV_VOID intelFlashReset(MV_FLASH_INFO *pFlash); +MV_STATUS intelFlashProg(MV_FLASH_INFO *pFlash,MV_U32 offset, MV_U32 data); +MV_BOOL intelFlashSecLockGet(MV_FLASH_INFO *pFlash,MV_U32 secNum); +MV_STATUS intelFlashSecLock(MV_FLASH_INFO *pFlash, MV_U32 secNum, + MV_BOOL enable); +MV_U32 intelFlashGetHwBuffSize(MV_FLASH_INFO *pFlash); +MV_STATUS intelFlashHwBufferProg(MV_FLASH_INFO *pFlash,MV_U32 offset, MV_U32 byteCount, + MV_U8* pData); + +#endif /* __INCmvIntelFlashH */ diff --git a/board/mv_feroceon/mv_hal/pci-if/mvCompVer.txt b/board/mv_feroceon/mv_hal/pci-if/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/pci-if/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/pci-if/mvPciIf.c b/board/mv_feroceon/mv_hal/pci-if/mvPciIf.c new file mode 100644 index 0000000..f249222 --- /dev/null +++ b/board/mv_feroceon/mv_hal/pci-if/mvPciIf.c @@ -0,0 +1,669 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvPciIf.h" +#include "ctrlEnv/sys/mvSysPex.h" + +#if defined(MV_INCLUDE_PCI) +#include "ctrlEnv/sys/mvSysPci.h" +#endif + + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + + +/******************************************************************************* +* mvPciInit - Initialize PCI interfaces +* +* DESCRIPTION: +* +* INPUT: +* +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM +* +*******************************************************************************/ + + +MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + + MV_PCI_MOD pciMod; + + if (PCI_IF_MODE_HOST == pciIfmode) + { + pciMod = MV_PCI_MOD_HOST; + } + else if (PCI_IF_MODE_DEVICE == pciIfmode) + { + pciMod = MV_PCI_MOD_DEVICE; + } + else + { + mvOsPrintf("%s: ERROR!!! Bus %d mode %d neither host nor device!\n", + __FUNCTION__, pciIf, pciIfmode); + return MV_FAIL; + } + + return mvPciInit(pciIf - MV_PCI_START_IF, pciMod); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + + MV_PEX_TYPE pexType; + + if (PCI_IF_MODE_HOST == pciIfmode) + { + pexType = MV_PEX_ROOT_COMPLEX; + } + else if (PCI_IF_MODE_DEVICE == pciIfmode) + { + pexType = MV_PEX_END_POINT; + } + else + { + mvOsPrintf("%s: ERROR!!! Bus %d type %d neither root complex nor" \ + " end point\n", __FUNCTION__, pciIf, pciIfmode); + return MV_FAIL; + } + return mvPexInit(pciIf - MV_PEX_START_IF, pexType); + + #else + return MV_OK; + #endif + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + +/* PCI configuration space read write */ + +/******************************************************************************* +* mvPciConfigRead - Read from configuration space +* +* DESCRIPTION: +* This function performs a 32 bit read from PCI configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to read from local bus segment, use +* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pciIf - PCI interface number. +* bus - PCI segment bus number. +* dev - PCI device number. +* func - Function number. +* regOffs - Register offset. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit register data, 0xffffffff on error +* +*******************************************************************************/ +MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciConfigRead(pciIf - MV_PCI_START_IF, + bus, + dev, + func, + regOff); + #else + return 0xffffffff; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexConfigRead(pciIf - MV_PEX_START_IF, + bus, + dev, + func, + regOff); + #else + return 0xffffffff; + #endif + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return 0; + +} + +/******************************************************************************* +* mvPciConfigWrite - Write to configuration space +* +* DESCRIPTION: +* This function performs a 32 bit write to PCI configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to write to local bus segment, use +* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pciIf - PCI interface number. +* bus - PCI segment bus number. +* dev - PCI device number. +* func - Function number. +* regOffs - Register offset. +* data - 32bit data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciConfigWrite(pciIf - MV_PCI_START_IF, + bus, + dev, + func, + regOff, + data); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexConfigWrite(pciIf - MV_PEX_START_IF, + bus, + dev, + func, + regOff, + data); + #else + return MV_OK; + #endif + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + +/******************************************************************************* +* mvPciMasterEnable - Enable/disale PCI interface master transactions. +* +* DESCRIPTION: +* This function performs read modified write to PCI command status +* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI +* master is allowed to gain ownership on the bus, otherwise it is +* incapable to do so. +* +* INPUT: +* pciIf - PCI interface number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable) +{ + + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciMasterEnable(pciIf - MV_PCI_START_IF, + enable); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexMasterEnable(pciIf - MV_PEX_START_IF, + enable); + #else + return MV_OK; + #endif + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + + +/******************************************************************************* +* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. +* +* DESCRIPTION: +* This function performs read modified write to PCI command status +* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, +* the PCI slave is allowed to respond to PCI IO space access (bit 0) +* and PCI memory space access (bit 1). +* +* INPUT: +* pciIf - PCI interface number. +* dev - PCI device number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, MV_BOOL enable) +{ + + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciSlaveEnable(pciIf - MV_PCI_START_IF,bus,dev, + enable); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexSlaveEnable(pciIf - MV_PEX_START_IF,bus,dev, + enable); + #else + return MV_OK; + #endif + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + +/******************************************************************************* +* mvPciLocalBusNumSet - Set PCI interface local bus number. +* +* DESCRIPTION: +* This function sets given PCI interface its local bus number. +* Note: In case the PCI interface is PCI-X, the information is read-only. +* +* INPUT: +* pciIf - PCI interface number. +* busNum - Bus number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PCI interface is PCI-X. +* MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciLocalBusNumSet(pciIf - MV_PCI_START_IF, + busNum); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexLocalBusNumSet(pciIf - MV_PEX_START_IF, + busNum); + #else + return MV_OK; + #endif + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + +/******************************************************************************* +* mvPciLocalBusNumGet - Get PCI interface local bus number. +* +* DESCRIPTION: +* This function gets the local bus number of a given PCI interface. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local bus number.0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciLocalBusNumGet(pciIf - MV_PCI_START_IF); + #else + return 0xFFFFFFFF; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexLocalBusNumGet(pciIf - MV_PEX_START_IF); + #else + return 0xFFFFFFFF; + #endif + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n",__FUNCTION__, pciIf); + } + + return 0; + +} + + +/******************************************************************************* +* mvPciLocalDevNumSet - Set PCI interface local device number. +* +* DESCRIPTION: +* This function sets given PCI interface its local device number. +* Note: In case the PCI interface is PCI-X, the information is read-only. +* +* INPUT: +* pciIf - PCI interface number. +* devNum - Device number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciLocalDevNumSet(pciIf - MV_PCI_START_IF, + devNum); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexLocalDevNumSet(pciIf - MV_PEX_START_IF, + devNum); + #else + return MV_OK; + #endif + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + +/******************************************************************************* +* mvPciLocalDevNumGet - Get PCI interface local device number. +* +* DESCRIPTION: +* This function gets the local device number of a given PCI interface. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local device number. 0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciLocalDevNumGet(pciIf - MV_PCI_START_IF); + #else + return 0xFFFFFFFF; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexLocalDevNumGet(pciIf - MV_PEX_START_IF); + #else + return 0xFFFFFFFF; + #endif + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return 0; + +} + +/******************************************************************************* +* mvPciIfTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ + +PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf) +{ + + if ((pciIf >= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) + { + return PCI_IF_TYPE_CONVEN_PCIX; + } + else if ((pciIf >= MV_PEX_START_IF) && + (pciIf < mvCtrlPexMaxIfGet() + MV_PEX_START_IF)) + { + return PCI_IF_TYPE_PEX; + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return 0xffffffff; + +} + +/******************************************************************************* +* mvPciIfTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ + +MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) +{ + + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + return (pciIf - MV_PCI_START_IF); + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + return (pciIf - MV_PEX_START_IF); + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return 0xffffffff; + +} + + + diff --git a/board/mv_feroceon/mv_hal/pci-if/mvPciIf.h b/board/mv_feroceon/mv_hal/pci-if/mvPciIf.h new file mode 100644 index 0000000..9c2d160 --- /dev/null +++ b/board/mv_feroceon/mv_hal/pci-if/mvPciIf.h @@ -0,0 +1,134 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPCIIFH +#define __INCPCIIFH + +#include "mvSysHwConfig.h" +#include "pci-if/mvPciIfRegs.h" +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif +#if defined(MV_INCLUDE_PCI) +#include "pci/mvPci.h" +#endif +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +typedef enum _mvPCIIfType +{ + PCI_IF_TYPE_CONVEN_PCIX, + PCI_IF_TYPE_PEX + +}PCI_IF_TYPE; + +typedef enum _mvPCIIfMode +{ + PCI_IF_MODE_HOST, + PCI_IF_MODE_DEVICE +}PCI_IF_MODE; + + +/* Global Functions prototypes */ + +/* mvPciIfInit - Initialize PCI interfaces*/ +MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); + +/* mvPciIfConfigRead - Read from configuration space */ +MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func,MV_U32 regOff); + +/* mvPciIfConfigWrite - Write to configuration space */ +MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data); + +/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ +MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); + +/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ +MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, + MV_BOOL enable); + +/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ +MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); + +/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ +MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); + +/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ +MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); + +/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ +MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); + +/* mvPciIfTypeGet - Get PCI If type*/ +PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); + +MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); + +/* mvPciIfAddrDecShow - Display address decode windows attributes */ +MV_VOID mvPciIfAddrDecShow(MV_VOID); + +#endif /* #ifndef __INCPCIIFH */ + diff --git a/board/mv_feroceon/mv_hal/pci-if/mvPciIfRegs.h b/board/mv_feroceon/mv_hal/pci-if/mvPciIfRegs.h new file mode 100644 index 0000000..08d4d2d --- /dev/null +++ b/board/mv_feroceon/mv_hal/pci-if/mvPciIfRegs.h @@ -0,0 +1,245 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPCIIFREGSH +#define __INCPCIIFREGSH + + +/* defines */ +#define MAX_PCI_DEVICES 32 +#define MAX_PCI_FUNCS 8 +#define MAX_PCI_BUSSES 128 + +/***************************************/ +/* PCI Configuration registers */ +/***************************************/ + +/*********************************************/ +/* PCI Configuration, Function 0, Registers */ +/*********************************************/ + + +/* Standard registers */ +#define PCI_DEVICE_AND_VENDOR_ID 0x000 +#define PCI_STATUS_AND_COMMAND 0x004 +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C +#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) +#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C +#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 +#define PCI_CAPABILTY_LIST_POINTER 0x034 +#define PCI_INTERRUPT_PIN_AND_LINE 0x03C + + +/* PCI Device and Vendor ID Register (PDVIR) */ +#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ +#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) + +#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ +#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) + +/* PCI Status and Command Register (PSCR) */ +#define PSCR_IO_EN BIT0 /* IO Enable */ +#define PSCR_MEM_EN BIT1 /* Memory Enable */ +#define PSCR_MASTER_EN BIT2 /* Master Enable */ +#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ +#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ +#define PSCR_VGA BIT5 /* VGA Palette Snoops */ +#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ +#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ +#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ +#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ +#define PSCR_CAP_LIST BIT20 /* Capability List Support */ +#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ +#define PSCR_UDF_EN BIT22 /* User definable features */ +#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ +#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ + +#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ +#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) +#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) +#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) +#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) + +#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ +#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ +#define PSCR_MABORT BIT29 /* Recieved Master Abort */ +#define PSCR_SYSERR BIT30 /* Signalled system error */ +#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ + +/* PCI configuration register offset=0x08 fields + (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ + +#define PCCRIR_REVID_OFFS 0 /* Revision ID */ +#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) + +#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ +#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) + +#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ +#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) + +#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ +#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) + +#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ +#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) + +/* PCI configuration register offset=0x0C fields + (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ + +#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ +#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) + +#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ +#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) + +#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ +#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) + +#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ + +#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ +#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) +#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) +#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) + + +#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ +#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) + +#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ +#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ + + +/* PCI Bar Base Low Register (PBBLR) */ +#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ + +#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) +#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) +#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) + +#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ + + +#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to + address bits [31:4] */ +#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) + +#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to + address bits [31:2] */ +#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) + + +#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ +#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) +#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) + + +/* PCI Bar Base High Fegister (PBBHR) */ +#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ +#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) + + +/* PCI configuration register offset=0x2C fields + (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ + +#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ +#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) + +#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ +#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) + +/* PCI configuration register offset=0x30 fields + (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ + +#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ + +#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ +#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) + +/* PCI configuration register offset=0x34 fields + (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ + +#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ +#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) + +/* PCI configuration register offset=0x3C fields + (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ + +#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ +#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) + +#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ +#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) + +#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ +#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) + +#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ +#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) + +#endif /* #ifndef __INCPCIIFREGSH */ + diff --git a/board/mv_feroceon/mv_hal/pci-if/pci_util/mvPciUtils.c b/board/mv_feroceon/mv_hal/pci-if/pci_util/mvPciUtils.c new file mode 100644 index 0000000..f216979 --- /dev/null +++ b/board/mv_feroceon/mv_hal/pci-if/pci_util/mvPciUtils.c @@ -0,0 +1,1006 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "mvPciUtils.h" + +#include "ctrlEnv/mvCtrlEnvLib.h" + +/* #define MV_DEBUG */ +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x + #define mvOsPrintf printf +#else + #define DB(x) +#endif + +/* +This module only support scanning of Header type 00h of pci devices +There is no suppotr for Header type 01h of pci devices ( PCI bridges ) +*/ + + +static MV_STATUS pciDetectDevice(MV_U32 pciIf, + MV_U32 bus, + MV_U32 dev, + MV_U32 func, + MV_PCI_DEVICE *pPciAgent); + +static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, + MV_U32 bus, + MV_U32 dev, + MV_U32 func, + MV_PCI_DEVICE *pPciAgent); + + + + + + +/******************************************************************************* +* mvPciScan - Scan a PCI interface bus +* +* DESCRIPTION: +* Performs a full scan on a PCI interface and returns all possible details +* on the agents found on the bus. +* +* INPUT: +* pciIf - PCI Interface +* pPciAgents - Pointer to an Array of the pci agents to be detected +* pPciAgentsNum - pPciAgents array maximum number of elements +* +* OUTPUT: +* pPciAgents - Array of the pci agents detected on the bus +* pPciAgentsNum - Number of pci agents detected on the bus +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + +MV_STATUS mvPciScan(MV_U32 pciIf, + MV_PCI_DEVICE *pPciAgents, + MV_U32 *pPciAgentsNum) +{ + + MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; + MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); + MV_PCI_DEVICE *pPciDevice; + MV_PCI_DEVICE *pMainDevice; + + DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); + /* Parameter checking */ + if (pciIf >= mvCtrlPexMaxIfGet()) + { + DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); + return MV_BAD_PARAM; + } + if (NULL == pPciAgents) + { + DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); + return MV_BAD_PARAM; + } + if (NULL == pPciAgentsNum) + { + DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); + return MV_BAD_PARAM; + } + + + DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); + /* Master enable the MV PCI master */ + if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) + { + DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); + return MV_ERROR; + + } + + DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); + + /* go through all busses */ + for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) + { + /* go through all possible devices on the local bus */ + for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) + { + /* always start with function equal to zero */ + funcIndex=0; + + pPciDevice=&pPciAgents[detectedDevNum]; + DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); + + if (MV_ERROR == pciDetectDevice(pciIf, + busIndex, + devIndex, + funcIndex, + pPciDevice)) + { + /* no device detected , try the next address */ + continue; + } + + /* We are here ! means we have detected a device*/ + /* always we start with only one function per device */ + pMainDevice = pPciDevice; + pPciDevice->funtionsNum = 1; + + + /* move on */ + detectedDevNum++; + + + /* check if we have no more room for a new device */ + if (detectedDevNum == *pPciAgentsNum) + { + DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); + return MV_ERROR; + } + + /* check the detected device if it is a multi functional device then + scan all device functions*/ + if (pPciDevice->isMultiFunction == MV_TRUE) + { + /* start with function number 1 because we have already detected + function 0 */ + for (funcIndex=1; funcIndexfuntionsNum++; + detectedDevNum++; + + /* check if we have no more room for a new device */ + if (detectedDevNum == *pPciAgentsNum) + { + DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); + return MV_ERROR; + } + + + } + } + + } + + } + + /* return the number of devices actually detected on the bus ! */ + *pPciAgentsNum = detectedDevNum; + + return MV_OK; + +} + + +/******************************************************************************* +* pciDetectDevice - Detect a pci device parameters +* +* DESCRIPTION: +* This function detect if a pci agent exist on certain address ! +* and if exists then it fills all possible information on the +* agent +* +* INPUT: +* pciIf - PCI Interface +* bus - Bus number +* dev - Device number +* func - Function number +* +* +* +* OUTPUT: +* pPciAgent - pointer to the pci agent filled with its information +* +* RETURN: +* MV_ERROR if no device , MV_OK otherwise +* +*******************************************************************************/ + +static MV_STATUS pciDetectDevice(MV_U32 pciIf, + MV_U32 bus, + MV_U32 dev, + MV_U32 func, + MV_PCI_DEVICE *pPciAgent) +{ + MV_U32 pciData; + + /* no Parameters checking ! because it is static function and it is assumed + that all parameters were checked in the calling function */ + + + /* Try read the PCI Vendor ID and Device ID */ + + /* We will scan only ourselves and the PCI slots that exist on the + board, because we may have a case that we have one slot that has + a Cardbus connector, and because CardBus answers all IDsels we want + to scan only this slot and ourseleves. + + */ + #if defined(MV_INCLUDE_PCI) + if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && + (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && + (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && + (DB_88F5181_DDR1_MNG != mvBoardIdGet())) + { + + if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) + { + return MV_ERROR; + } + } + #endif /* defined(MV_INCLUDE_PCI) */ + + pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); + + if (PCI_ERROR_CODE == pciData) + { + /* no device exist */ + return MV_ERROR; + } + + /* we are here ! means a device is detected */ + + /* fill basic information */ + pPciAgent->busNumber=bus; + pPciAgent->deviceNum=dev; + pPciAgent->function=func; + + /* Fill the PCI Vendor ID and Device ID */ + + pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; + pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; + + /* Read Status and command */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_STATUS_AND_COMMAND); + + + /* Fill related Status and Command information*/ + + if (pciData & PSCR_TAR_FAST_BB) + { + pPciAgent->isFastB2BCapable = MV_TRUE; + } + else + { + pPciAgent->isFastB2BCapable = MV_FALSE; + } + + if (pciData & PSCR_CAP_LIST) + { + pPciAgent->isCapListSupport=MV_TRUE; + } + else + { + pPciAgent->isCapListSupport=MV_FALSE; + } + + if (pciData & PSCR_66MHZ_EN) + { + pPciAgent->is66MHZCapable=MV_TRUE; + } + else + { + pPciAgent->is66MHZCapable=MV_FALSE; + } + + /* Read Class Code and Revision */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_CLASS_CODE_AND_REVISION_ID); + + + pPciAgent->baseClassCode = + (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; + + pPciAgent->subClassCode = + (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; + + pPciAgent->progIf = + (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; + + pPciAgent->revisionID = + (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; + + /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); + + + + pPciAgent->pciCacheLine= + (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; + pPciAgent->pciLatencyTimer= + (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; + + switch (pciData & PBHTLTCLR_HEADER_MASK) + { + case PBHTLTCLR_HEADER_STANDARD: + + pPciAgent->pciHeader=MV_PCI_STANDARD; + break; + case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: + + pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; + break; + + } + + if (pciData & PBHTLTCLR_MULTI_FUNC) + { + pPciAgent->isMultiFunction=MV_TRUE; + } + else + { + pPciAgent->isMultiFunction=MV_FALSE; + } + + if (pciData & PBHTLTCLR_BISTCAP) + { + pPciAgent->isBISTCapable=MV_TRUE; + } + else + { + pPciAgent->isBISTCapable=MV_FALSE; + } + + + /* read this device pci bars */ + + pciDetectDeviceBars(pciIf, + bus,dev,func, + pPciAgent); + + + /* check if we are bridge*/ + if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& + (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) + { + + /* Read P2P_BUSSES_NUM */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_BUSSES_NUM); + + pPciAgent->p2pPrimBusNum = + (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; + + pPciAgent->p2pSecBusNum = + (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; + + pPciAgent->p2pSubBusNum = + (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; + + pPciAgent->p2pSecLatencyTimer = + (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; + + /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_IO_BASE_LIMIT_SEC_STATUS); + + pPciAgent->p2pSecStatus = + (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; + + + pPciAgent->p2pIObase = + (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; + + /* clear low address (should be zero)*/ + pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; + + pPciAgent->p2pIOLimit = + (pciData & PIBLSS_IO_LIMIT_MASK); + + /* fill low address with 0xfff */ + pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; + + + switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) + { + case PIBLSS_ADD_CAP_16BIT: + + pPciAgent->bIO32 = MV_FALSE; + + break; + case PIBLSS_ADD_CAP_32BIT: + + pPciAgent->bIO32 = MV_TRUE; + + /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_IO_BASE_LIMIT_UPPER_16); + + pPciAgent->p2pIObase |= + (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; + + + pPciAgent->p2pIOLimit |= + (pciData & PRBU_IO_UPP_LIMIT_MASK); + + break; + + } + + + /* Read P2P_MEM_BASE_LIMIT */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_MEM_BASE_LIMIT); + + pPciAgent->p2pMemBase = + (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; + + /* clear low address */ + pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; + + pPciAgent->p2pMemLimit = + (pciData & PMBL_MEM_LIMIT_MASK); + + /* add 0xfffff */ + pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; + + + /* Read P2P_PREF_MEM_BASE_LIMIT */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_PREF_MEM_BASE_LIMIT); + + + pPciAgent->p2pPrefMemBase = + (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; + + /* get high address only */ + pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; + + + + pPciAgent->p2pPrefMemLimit = + (pciData & PRMBL_PREF_MEM_LIMIT_MASK); + + /* add 0xfffff */ + pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; + + switch (pciData & PRMBL_ADD_CAP_MASK) + { + case PRMBL_ADD_CAP_32BIT: + + pPciAgent->bPrefMem64 = MV_FALSE; + + /* Read P2P_PREF_BASE_UPPER_32 */ + pPciAgent->p2pPrefBaseUpper32Bits = 0; + + /* Read P2P_PREF_LIMIT_UPPER_32 */ + pPciAgent->p2pPrefLimitUpper32Bits = 0; + + break; + case PRMBL_ADD_CAP_64BIT: + + pPciAgent->bPrefMem64 = MV_TRUE; + + /* Read P2P_PREF_BASE_UPPER_32 */ + pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_PREF_BASE_UPPER_32); + + /* Read P2P_PREF_LIMIT_UPPER_32 */ + pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_PREF_LIMIT_UPPER_32); + + break; + + } + + } + else /* no bridge */ + { + /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); + + + pPciAgent->subSysVenID = + (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; + pPciAgent->subSysID = + (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; + + + /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_EXPANSION_ROM_BASE_ADDR_REG); + + + if (pciData & PERBAR_EXPROMEN) + { + pPciAgent->isExpRom = MV_TRUE; + } + else + { + pPciAgent->isExpRom = MV_FALSE; + } + + pPciAgent->expRomAddr = + (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; + + } + + + if (MV_TRUE == pPciAgent->isCapListSupport) + { + /* Read PCI_CAPABILTY_LIST_POINTER */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_CAPABILTY_LIST_POINTER); + + pPciAgent->capListPointer = + (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; + + } + + /* Read PCI_INTERRUPT_PIN_AND_LINE */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_INTERRUPT_PIN_AND_LINE); + + + pPciAgent->irqLine= + (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; + + pPciAgent->intPin= + (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; + + pPciAgent->minGrant= + (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; + pPciAgent->maxLatency= + (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; + + mvPciClassNameGet(pPciAgent->baseClassCode, + (MV_8 *)pPciAgent->type); + + return MV_OK; + + +} + +/******************************************************************************* +* pciDetectDeviceBars - Detect a pci device bars +* +* DESCRIPTION: +* This function detects all pci agent bars +* +* INPUT: +* pciIf - PCI Interface +* bus - Bus number +* dev - Device number +* func - Function number +* +* +* +* OUTPUT: +* pPciAgent - pointer to the pci agent filled with its information +* +* RETURN: +* detected bars number +* +*******************************************************************************/ +static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, + MV_U32 bus, + MV_U32 dev, + MV_U32 func, + MV_PCI_DEVICE *pPciAgent) +{ + MV_U32 pciData,barIndex,detectedBar=0; + MV_U32 tmpBaseHigh=0,tmpBaseLow=0; + MV_U32 pciMaxBars=0; + + pPciAgent->barsNum=0; + + /* check if we are bridge*/ + if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& + (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) + { + pciMaxBars = 2; + } + else /* no bridge */ + { + pciMaxBars = 6; + } + + /* read this device pci bars */ + for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) + { + /* Read PCI_MEMORY_BAR_BASE_ADDR */ + tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + + pPciAgent->pciBar[detectedBar].barOffset = + PCI_MEMORY_BAR_BASE_ADDR(barIndex); + + /* check if the bar is 32bit or 64bit bar */ + switch (pciData & PBBLR_TYPE_MASK) + { + case PBBLR_TYPE_32BIT_ADDR: + pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; + break; + case PBBLR_TYPE_64BIT_ADDR: + pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; + break; + + } + + /* check if it is memory or IO bar */ + if (pciData & PBBLR_IOSPACE) + { + pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; + } + else + { + pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; + } + + /* if it is memory bar then check if it is prefetchable */ + if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) + { + if (pciData & PBBLR_PREFETCH_EN) + { + pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; + } + else + { + pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; + } + + pPciAgent->pciBar[detectedBar].barBaseLow = + pciData & PBBLR_MEM_BASE_MASK; + + + } + else /* IO Bar */ + { + pPciAgent->pciBar[detectedBar].barBaseLow = + pciData & PBBLR_IO_BASE_MASK; + + } + + pPciAgent->pciBar[detectedBar].barBaseHigh=0; + + if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) + { + barIndex++; + + tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = + mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + + + } + + /* calculating full base address (64bit) */ + pPciAgent->pciBar[detectedBar].barBaseAddr = + (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; + + pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; + + pPciAgent->pciBar[detectedBar].barBaseAddr |= + (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; + + + + /* get the sizes of the the bar */ + + pPciAgent->pciBar[detectedBar].barSizeHigh=0; + + if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && + (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) + + { + /* write oxffffffff to the bar to get the size */ + /* start with sizelow ( original value was saved in tmpBaseLow ) */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), + 0xffffffff); + + /* read size */ + pPciAgent->pciBar[detectedBar].barSizeLow = + mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); + + + + /* restore original value */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), + tmpBaseLow); + + + /* now do the same for BaseHigh */ + + /* write oxffffffff to the bar to get the size */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex), + 0xffffffff); + + /* read size */ + pPciAgent->pciBar[detectedBar].barSizeHigh = + mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + + /* restore original value */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex), + tmpBaseHigh); + + if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& + (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) + { + /* this bar is not applicable for this device, + ignore all previous settings and check the next bar*/ + + /* we though this was a 64bit bar , and it seems this + was wrong ! so decrement barIndex */ + barIndex--; + continue; + } + + /* calculate the full 64 bit size */ + + if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) + { + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; + + pPciAgent->pciBar[detectedBar].barSizeLow = + ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; + + pPciAgent->pciBar[detectedBar].barSizeHigh = 0; + + } + else + { + + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; + + pPciAgent->pciBar[detectedBar].barSizeLow = + ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; + + pPciAgent->pciBar[detectedBar].barSizeHigh = 0; + + } + + + + } + else /* 32bit bar */ + { + /* write oxffffffff to the bar to get the size */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex), + 0xffffffff); + + /* read size */ + pPciAgent->pciBar[detectedBar].barSizeLow = + mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + + if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) + { + /* this bar is not applicable for this device, + ignore all previous settings and check the next bar*/ + continue; + } + + + /* restore original value */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex), + tmpBaseLow); + + /* calculate size low */ + + if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) + { + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; + } + else + { + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; + } + + pPciAgent->pciBar[detectedBar].barSizeLow = + ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; + + pPciAgent->pciBar[detectedBar].barSizeHigh = 0; + pPciAgent->pciBar[detectedBar].barSize = + (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; + + + } + + /* we are here ! this means we have already detected a bar for + this device , now move on */ + + detectedBar++; + pPciAgent->barsNum++; + } + + return detectedBar; +} + + +/******************************************************************************* +* mvPciClassNameGet - get PCI class name +* +* DESCRIPTION: +* This function returns the PCI class name +* +* INPUT: +* baseClassCode - Base Class Code. +* +* OUTPUT: +* pType - the class name +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) +{ + + switch(baseClassCode) + { + case 0x0: + strcpy(pType,"Old generation device"); + break; + case 0x1: + strcpy(pType,"Mass storage controller"); + break; + case 0x2: + strcpy(pType,"Network controller"); + break; + case 0x3: + strcpy(pType,"Display controller"); + break; + case 0x4: + strcpy(pType,"Multimedia device"); + break; + case 0x5: + strcpy(pType,"Memory controller"); + break; + case 0x6: + strcpy(pType,"Bridge Device"); + break; + case 0x7: + strcpy(pType,"Simple Communication controllers"); + break; + case 0x8: + strcpy(pType,"Base system peripherals"); + break; + case 0x9: + strcpy(pType,"Input Devices"); + break; + case 0xa: + strcpy(pType,"Docking stations"); + break; + case 0xb: + strcpy(pType,"Processors"); + break; + case 0xc: + strcpy(pType,"Serial bus controllers"); + break; + case 0xd: + strcpy(pType,"Wireless controllers"); + break; + case 0xe: + strcpy(pType,"Intelligent I/O controllers"); + break; + case 0xf: + strcpy(pType,"Satellite communication controllers"); + break; + case 0x10: + strcpy(pType,"Encryption/Decryption controllers"); + break; + case 0x11: + strcpy(pType,"Data acquisition and signal processing controllers"); + break; + default: + strcpy(pType,"Unknown device"); + break; + } + + return MV_OK; + +} + + + diff --git a/board/mv_feroceon/mv_hal/pci-if/pci_util/mvPciUtils.h b/board/mv_feroceon/mv_hal/pci-if/pci_util/mvPciUtils.h new file mode 100644 index 0000000..2ee0b17 --- /dev/null +++ b/board/mv_feroceon/mv_hal/pci-if/pci_util/mvPciUtils.h @@ -0,0 +1,323 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvPciUtilsh +#define __INCmvPciUtilsh + +/* +This module only support scanning of Header type 00h of pci devices +There is no suppotr for Header type 01h of pci devices ( PCI bridges ) +*/ + +/* includes */ +#include "mvSysHwConfig.h" +#include "pci-if/mvPciIf.h" +#include "pci/mvPciRegs.h" + + + +/* PCI base address low bar mask */ +#define PCI_ERROR_CODE 0xffffffff + +#define PCI_BRIDGE_CLASS 0x6 +#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 + + +#define P2P_BUSSES_NUM 0x18 +#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C +#define P2P_MEM_BASE_LIMIT 0x20 +#define P2P_PREF_MEM_BASE_LIMIT 0x24 +#define P2P_PREF_BASE_UPPER_32 0x28 +#define P2P_PREF_LIMIT_UPPER_32 0x2C +#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 +#define P2P_EXP_ROM 0x38 + +/* P2P_BUSSES_NUM (PBM) */ + +#define PBM_PRIME_BUS_NUM_OFFS 0 +#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) + +#define PBM_SEC_BUS_NUM_OFFS 8 +#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) + +#define PBM_SUB_BUS_NUM_OFFS 16 +#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) + +#define PBM_SEC_LAT_TMR_OFFS 24 +#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) + +/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ + +#define PIBLSS_IO_BASE_OFFS 0 +#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) + +#define PIBLSS_ADD_CAP_OFFS 0 +#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) +#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) +#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) + +#define PIBLSS_LOW_ADDR_OFFS 0 +#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) + +#define PIBLSS_HIGH_ADDR_OFFS 12 +#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) + +#define PIBLSS_IO_LIMIT_OFFS 8 +#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) + +#define PIBLSS_SEC_STATUS_OFFS 16 +#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) + + +/* P2P_MEM_BASE_LIMIT (PMBL)*/ + +#define PMBL_MEM_BASE_OFFS 0 +#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) + +#define PMBL_MEM_LIMIT_OFFS 16 +#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) + + +#define PMBL_LOW_ADDR_OFFS 0 +#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) + +#define PMBL_HIGH_ADDR_OFFS 20 +#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) + + +/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ + +#define PRMBL_PREF_MEM_BASE_OFFS 0 +#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) + +#define PRMBL_PREF_MEM_LIMIT_OFFS 16 +#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); + return MV_BAD_PARAM; + } + + /* Set command register */ + MV_REG_WRITE(PCI_CMD_REG(pciIf), command); + + /* Upodate device max outstanding split tarnsaction */ + if ((command & PCR_CPU_TO_PCI_ORDER_EN) && + (command & PCR_PCI_TO_CPU_ORDER_EN)) + { + /* Read PCI-X command register */ + regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); + + /* clear bits 22:20 */ + regVal &= 0xff8fffff; + + /* set reset value */ + regVal |= (0x3 << 20); + + /* Write back the value */ + mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); + } + + return MV_OK; + + +} + + +/******************************************************************************* +* mvPciModeGet - Get PCI interface mode. +* +* DESCRIPTION: +* This function returns the given PCI interface mode. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* pPciMode - Pointer to PCI mode structure. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) +{ + MV_U32 pciMode; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + if (NULL == pPciMode) + { + mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); + return MV_BAD_PARAM; + } + + /* Read pci mode register */ + pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); + + switch (pciMode & PMR_PCI_MODE_MASK) + { + case PMR_PCI_MODE_CONV: + pPciMode->pciType = MV_PCI_CONV; + + if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) + { + pPciMode->pciSpeed = 66000000; /* 66MHZ */ + } + else + { + pPciMode->pciSpeed = 33000000; /* 33MHZ */ + } + + break; + + case PMR_PCI_MODE_PCIX_66MHZ: + pPciMode->pciType = MV_PCIX; + pPciMode->pciSpeed = 66000000; /* 66MHZ */ + break; + + case PMR_PCI_MODE_PCIX_100MHZ: + pPciMode->pciType = MV_PCIX; + pPciMode->pciSpeed = 100000000; /* 100MHZ */ + break; + + case PMR_PCI_MODE_PCIX_133MHZ: + pPciMode->pciType = MV_PCIX; + pPciMode->pciSpeed = 133000000; /* 133MHZ */ + break; + + default: + { + mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); + return MV_ERROR; + } + } + + switch (pciMode & PMR_PCI_64_MASK) + { + case PMR_PCI_64_64BIT: + pPciMode->pciWidth = MV_PCI_64; + break; + + case PMR_PCI_64_32BIT: + pPciMode->pciWidth = MV_PCI_32; + break; + + default: + { + mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); + return MV_ERROR; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvPciRetrySet - Set PCI retry counters +* +* DESCRIPTION: +* This function specifies the number of times the PCI controller +* retries a transaction before it quits. +* Applies to the PCI Master when acting as a requester. +* Applies to the PCI slave when acting as a completer (PCI-X mode). +* A 0x00 value means a "retry forever". +* +* INPUT: +* pciIf - PCI interface number. +* counter - Number of times PCI controller retry. Use counter value +* up to PRR_RETRY_CNTR_MAX. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) +{ + MV_U32 pciRetry; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + + if (counter >= PRR_RETRY_CNTR_MAX) + { + mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); + return MV_BAD_PARAM; + + } + + /* Reading PCI retry register */ + pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); + + pciRetry &= ~PRR_RETRY_CNTR_MASK; + + pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); + + /* write new value */ + MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); + + return MV_OK; +} + + +/******************************************************************************* +* mvPciDiscardTimerSet - Set PCI discard timer +* +* DESCRIPTION: +* This function set PCI discard timer. +* In conventional PCI mode: +* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed +* read buffers (non-completed delayed read) before invalidate the buffer. +* Set to '0' to disable the timer. The PCI slave waits for delayed +* read completion forever. +* In PCI-X mode: +* Specifies the number of PCLK cycles the PCI master waits for split +* completion transaction, before it invalidates the pre-allocated read +* buffer. +* Set to '0' to disable the timer. The PCI master waits for split +* completion forever. +* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, +* unless using the "wait for ever" setting 0x0. +* NOTE: Must not be updated while there are pending read requests. +* +* INPUT: +* pciIf - PCI interface number. +* pClkCycles - Number of PCI clock cycles. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) +{ + MV_U32 pciDiscardTimer; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", + pciIf); + return MV_BAD_PARAM; + } + + if (pClkCycles >= PDTR_TIMER_MIN) + { + mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", + pClkCycles); + return MV_BAD_PARAM; + + } + + /* Read PCI Discard Timer */ + pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); + + pciDiscardTimer &= ~PDTR_TIMER_MASK; + + pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); + + /* Write new value */ + MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); + + return MV_OK; + +} + +/* PCI Arbiter routines */ + +/******************************************************************************* +* mvPciArbEnable - PCI arbiter enable/disable +* +* DESCRIPTION: +* This fuction enable/disables a given PCI interface arbiter. +* NOTE: Arbiter setting can not be changed while in work. It should only +* be set once. +* INPUT: +* pciIf - PCI interface number. +* enable - Enable/disable parameter. If enable = MV_TRUE then enable. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) +{ + MV_U32 regVal; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); + return MV_ERROR; + } + + /* Set PCI Arbiter Control register according to default configuration */ + regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); + + /* Make sure arbiter disabled before changing its values */ + MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); + + regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; + + regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ + + if (MV_TRUE == enable) + { + regVal |= PACR_ARB_ENABLE; + } + else + { + regVal &= ~PACR_ARB_ENABLE; + } + + /* Write to register */ + MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); + + return MV_OK; +} + + +/******************************************************************************* +* mvPciArbParkDis - Disable arbiter parking on agent +* +* DESCRIPTION: +* This function disables the PCI arbiter from parking on the given agent +* list. +* +* INPUT: +* pciIf - PCI interface number. +* pciAgentMask - When a bit in the mask is set to '1', parking on +* the associated PCI master is disabled. Mask bit +* refers to bit 0 - 6. For example disable parking on PCI +* agent 3 set pciAgentMask 0x4 (bit 3 is set). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) +{ + MV_U32 pciArbiterCtrl; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); + return MV_ERROR; + } + + /* Reading Arbiter Control register */ + pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); + + /* Arbiter must be disabled before changing parking */ + MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); + + /* do the change */ + pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; + pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); + + /* writing new value ( if th earbiter was enabled before the change */ + /* here it will be reenabled */ + MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); + + return MV_OK; +} + + +/******************************************************************************* +* mvPciArbBrokDetectSet - Set PCI arbiter broken detection +* +* DESCRIPTION: +* This function sets the maximum number of cycles that the arbiter +* waits for a PCI master to respond to its grant assertion. If a +* PCI agent fails to respond within this time, the PCI arbiter aborts +* the transaction and performs a new arbitration cycle. +* NOTE: Value must be greater than '1' for conventional PCI and +* greater than '5' for PCI-X. +* +* INPUT: +* pciIf - PCI interface number. +* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken +* master detection is disabled. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) +{ + MV_U32 pciArbiterCtrl; + MV_U32 pciMode; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", + pciIf); + return MV_BAD_PARAM; + } + + /* Checking PCI mode and if pClkCycles is legal value */ + pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); + pciMode &= PMR_PCI_MODE_MASK; + + if (PMR_PCI_MODE_CONV == pciMode) + { + if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) + return MV_ERROR; + } + else + { + if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) + return MV_ERROR; + } + + pClkCycles <<= PACR_BROKEN_VAL_OFFS; + + /* Reading Arbiter Control register */ + pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); + pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; + pciArbiterCtrl |= pClkCycles; + + /* Arbiter must be disabled before changing broken detection */ + MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); + + /* writing new value ( if th earbiter was enabled before the change */ + /* here it will be reenabled */ + + MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); + + return MV_OK; +} + +/* PCI configuration space read write */ + +/******************************************************************************* +* mvPciConfigRead - Read from configuration space +* +* DESCRIPTION: +* This function performs a 32 bit read from PCI configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to read from local bus segment, use +* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pciIf - PCI interface number. +* bus - PCI segment bus number. +* dev - PCI device number. +* func - Function number. +* regOffs - Register offset. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit register data, 0xffffffff on error +* +*******************************************************************************/ +MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff) +{ + MV_U32 pciData = 0; + + /* Parameter checking */ + if (PCI_DEFAULT_IF != pciIf) + { + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); + return 0xFFFFFFFF; + } + } + + if (dev >= MAX_PCI_DEVICES) + { + DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); + return 0xFFFFFFFF; + } + + if (func >= MAX_PCI_FUNCS) + { + DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); + return 0xFFFFFFFF; + } + + if (bus >= MAX_PCI_BUSSES) + { + DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); + return MV_ERROR; + } + + + /* Creating PCI address to be passed */ + pciData |= (bus << PCAR_BUS_NUM_OFFS); + pciData |= (dev << PCAR_DEVICE_NUM_OFFS); + pciData |= (func << PCAR_FUNC_NUM_OFFS); + pciData |= (regOff & PCAR_REG_NUM_MASK); + + pciData |= PCAR_CONFIG_EN; + + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); + + /* In order to let the PCI controller absorbed the address of the read */ + /* transaction we perform a validity check that the address was written */ + if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) + { + return MV_ERROR; + } + /* Read the Data returned in the PCI Data register */ + pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); + + return pciData; +} + +/******************************************************************************* +* mvPciConfigWrite - Write to configuration space +* +* DESCRIPTION: +* This function performs a 32 bit write to PCI configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to write to local bus segment, use +* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pciIf - PCI interface number. +* bus - PCI segment bus number. +* dev - PCI device number. +* func - Function number. +* regOffs - Register offset. +* data - 32bit data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data) +{ + MV_U32 pciData = 0; + + /* Parameter checking */ + if (PCI_DEFAULT_IF != pciIf) + { + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", + pciIf); + return 0xFFFFFFFF; + } + } + + if (dev >= MAX_PCI_DEVICES) + { + mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); + return MV_BAD_PARAM; + } + + if (func >= MAX_PCI_FUNCS) + { + mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); + return MV_ERROR; + } + + if (bus >= MAX_PCI_BUSSES) + { + mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); + return MV_ERROR; + } + + /* Creating PCI address to be passed */ + pciData |= (bus << PCAR_BUS_NUM_OFFS); + pciData |= (dev << PCAR_DEVICE_NUM_OFFS); + pciData |= (func << PCAR_FUNC_NUM_OFFS); + pciData |= (regOff & PCAR_REG_NUM_MASK); + + pciData |= PCAR_CONFIG_EN; + + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); + + /* In order to let the PCI controller absorbed the address of the read */ + /* transaction we perform a validity check that the address was written */ + if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) + { + return MV_ERROR; + } + + /* Write the Data passed to the PCI Data register */ + MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); + + return MV_OK; +} + +/******************************************************************************* +* mvPciMasterEnable - Enable/disale PCI interface master transactions. +* +* DESCRIPTION: +* This function performs read modified write to PCI command status +* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI +* master is allowed to gain ownership on the bus, otherwise it is +* incapable to do so. +* +* INPUT: +* pciIf - PCI interface number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) +{ + MV_U32 pciCommandStatus; + MV_U32 RegOffs; + MV_U32 localBus; + MV_U32 localDev; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); + return MV_ERROR; + } + + localBus = mvPciLocalBusNumGet(pciIf); + localDev = mvPciLocalDevNumGet(pciIf); + + RegOffs = PCI_STATUS_AND_COMMAND; + + pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); + + if (MV_TRUE == enable) + { + pciCommandStatus |= PSCR_MASTER_EN; + } + else + { + pciCommandStatus &= ~PSCR_MASTER_EN; + } + + mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); + + return MV_OK; +} + + +/******************************************************************************* +* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. +* +* DESCRIPTION: +* This function performs read modified write to PCI command status +* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, +* the PCI slave is allowed to respond to PCI IO space access (bit 0) +* and PCI memory space access (bit 1). +* +* INPUT: +* pciIf - PCI interface number. +* dev - PCI device number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) +{ + MV_U32 pciCommandStatus; + MV_U32 RegOffs; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + if (dev >= MAX_PCI_DEVICES) + { + mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); + return MV_BAD_PARAM; + + } + + RegOffs = PCI_STATUS_AND_COMMAND; + + pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); + + if (MV_TRUE == enable) + { + pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); + } + else + { + pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); + } + + mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); + + return MV_OK; +} + +/******************************************************************************* +* mvPciLocalBusNumSet - Set PCI interface local bus number. +* +* DESCRIPTION: +* This function sets given PCI interface its local bus number. +* Note: In case the PCI interface is PCI-X, the information is read-only. +* +* INPUT: +* pciIf - PCI interface number. +* busNum - Bus number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PCI interface is PCI-X. +* MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) +{ + MV_U32 pciP2PConfig; + MV_PCI_MODE pciMode; + MV_U32 localBus; + MV_U32 localDev; + + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); + return MV_BAD_PARAM; + } + if (busNum >= MAX_PCI_BUSSES) + { + mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); + return MV_ERROR; + + } + + localBus = mvPciLocalBusNumGet(pciIf); + localDev = mvPciLocalDevNumGet(pciIf); + + + /* PCI interface mode */ + mvPciModeGet(pciIf, &pciMode); + + /* if PCI type is PCI-X then it is not allowed to change the dev number */ + if (MV_PCIX == pciMode.pciType) + { + pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); + + pciP2PConfig &= ~PXS_BN_MASK; + + pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; + + mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); + + } + else + { + pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); + + pciP2PConfig &= ~PPCR_BUS_NUM_MASK; + + pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; + + MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); + + } + + + return MV_OK; +} + + +/******************************************************************************* +* mvPciLocalBusNumGet - Get PCI interface local bus number. +* +* DESCRIPTION: +* This function gets the local bus number of a given PCI interface. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local bus number.0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) +{ + MV_U32 pciP2PConfig; + + /* Parameter checking */ + if (PCI_DEFAULT_IF != pciIf) + { + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", + pciIf); + return 0xFFFFFFFF; + } + } + + pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); + pciP2PConfig &= PPCR_BUS_NUM_MASK; + return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); +} + + +/******************************************************************************* +* mvPciLocalDevNumSet - Set PCI interface local device number. +* +* DESCRIPTION: +* This function sets given PCI interface its local device number. +* Note: In case the PCI interface is PCI-X, the information is read-only. +* +* INPUT: +* pciIf - PCI interface number. +* devNum - Device number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) +{ + MV_U32 pciP2PConfig; + MV_PCI_MODE pciMode; + MV_U32 localBus; + MV_U32 localDev; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); + return MV_BAD_PARAM; + } + if (devNum >= MAX_PCI_DEVICES) + { + mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", + devNum); + return MV_BAD_PARAM; + + } + + localBus = mvPciLocalBusNumGet(pciIf); + localDev = mvPciLocalDevNumGet(pciIf); + + /* PCI interface mode */ + mvPciModeGet(pciIf, &pciMode); + + /* if PCI type is PCIX then it is not allowed to change the dev number */ + if (MV_PCIX == pciMode.pciType) + { + pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); + + pciP2PConfig &= ~PXS_DN_MASK; + + pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; + + mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); + } + else + { + pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); + + pciP2PConfig &= ~PPCR_DEV_NUM_MASK; + + pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; + + MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); + } + + return MV_OK; +} + +/******************************************************************************* +* mvPciLocalDevNumGet - Get PCI interface local device number. +* +* DESCRIPTION: +* This function gets the local device number of a given PCI interface. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local device number. 0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) +{ + MV_U32 pciP2PConfig; + + /* Parameter checking */ + + if (PCI_DEFAULT_IF != pciIf) + { + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", + pciIf); + return 0xFFFFFFFF; + } + } + + pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); + + pciP2PConfig &= PPCR_DEV_NUM_MASK; + + return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); +} + + + + diff --git a/board/mv_feroceon/mv_hal/pci/mvPci.h b/board/mv_feroceon/mv_hal/pci/mvPci.h new file mode 100644 index 0000000..4746336 --- /dev/null +++ b/board/mv_feroceon/mv_hal/pci/mvPci.h @@ -0,0 +1,185 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCPCIH +#define __INCPCIH + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "pci/mvPciRegs.h" + + +/* NOTE not supported in this driver: + + Built In Self Test (BIST) + Vital Product Data (VPD) + Message Signaled Interrupt (MSI) + Power Management + Compact PCI Hot Swap + Header retarget + +Registers not supported: +1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) +2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) +*/ + +/* defines */ +/* The number of supported PCI interfaces depend on Marvell controller */ +/* device number. This device number ID is located on the PCI unit */ +/* configuration header. This creates a loop where calling PCI */ +/* configuration read/write routine results a call to get PCI configuration */ +/* information etc. This macro defines a default PCI interface. This PCI */ +/* interface is sure to exist. */ +#define PCI_DEFAULT_IF 0 + + +/* typedefs */ +/* The Marvell controller supports both conventional PCI and PCI-X. */ +/* This enumeration describes the PCI type. */ +typedef enum _mvPciType +{ + MV_PCI_CONV, /* Conventional PCI */ + MV_PCIX /* PCI-X */ +}MV_PCI_TYPE; + +typedef enum _mvPciMod +{ + MV_PCI_MOD_HOST, + MV_PCI_MOD_DEVICE +}MV_PCI_MOD; + + +/* The Marvell controller supports both PCI width of 32 and 64 bit. */ +/* This enumerator describes PCI width */ +typedef enum _mvPciWidth +{ + MV_PCI_32, /* PCI width 32bit */ + MV_PCI_64 /* PCI width 64bit */ +}MV_PCI_WIDTH; + +/* This structure describes the PCI unit configured type, speed and width. */ +typedef struct _mvPciMode +{ + MV_PCI_TYPE pciType; /* PCI type */ + MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ + MV_PCI_WIDTH pciWidth; /* PCI bus width */ +}MV_PCI_MODE; + +/* mvPciInit - Initialize PCI interfaces*/ +MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); + +/* mvPciCommandSet - Set PCI comman register value.*/ +MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); + +/* mvPciModeGet - Get PCI interface mode.*/ +MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); + +/* mvPciRetrySet - Set PCI retry counters*/ +MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); + +/* mvPciDiscardTimerSet - Set PCI discard timer*/ +MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); + +/* mvPciArbEnable - PCI arbiter enable/disable*/ +MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); + +/* mvPciArbParkDis - Disable arbiter parking on agent */ +MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); + +/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ +MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); + +/* mvPciConfigRead - Read from configuration space */ +MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func,MV_U32 regOff); + +/* mvPciConfigWrite - Write to configuration space */ +MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data); + +/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ +MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); + +/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ +MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); + +/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ +MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); + +/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ +MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); + +/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ +MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); + +/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ +MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); + + +#endif /* #ifndef __INCPCIH */ + + + diff --git a/board/mv_feroceon/mv_hal/pci/mvPciRegs.h b/board/mv_feroceon/mv_hal/pci/mvPciRegs.h new file mode 100644 index 0000000..89d0ef1 --- /dev/null +++ b/board/mv_feroceon/mv_hal/pci/mvPciRegs.h @@ -0,0 +1,411 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPCIREGSH +#define __INCPCIREGSH + + +#include "pci-if/mvPciIfRegs.h" +/* defines */ +#define MAX_PCI_DEVICES 32 +#define MAX_PCI_FUNCS 8 +#define MAX_PCI_BUSSES 128 + +/* enumerators */ + +/* This enumerator described the possible PCI slave targets. */ +/* PCI slave targets are designated memory/IO address spaces that the */ +/* PCI slave targets can access. They are also refered as "targets" */ +/* this enumeratoe order is determined by the content of : + PCI_BASE_ADDR_ENABLE_REG */ + + +/* registers offsetes defines */ + + + +/*************************/ +/* PCI control registers */ +/*************************/ +/* maen : should add new registers */ +#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) +#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) +#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) +#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) +#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) +#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) +#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ + (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) +#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ + (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) +#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ + (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) + +#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) + +/* PCI Dll Control (PDC)*/ +#define PDC_DLL_EN BIT0 + + +/* PCI Command Register (PCR) */ +#define PCR_MASTER_BYTE_SWAP_EN BIT0 +#define PCR_MASTER_WR_COMBINE_EN BIT4 +#define PCR_MASTER_RD_COMBINE_EN BIT5 +#define PCR_MASTER_WR_TRIG_WHOLE BIT6 +#define PCR_MASTER_RD_TRIG_WHOLE BIT7 +#define PCR_MASTER_MEM_RD_LINE_EN BIT8 +#define PCR_MASTER_MEM_RD_MULT_EN BIT9 +#define PCR_MASTER_WORD_SWAP_EN BIT10 +#define PCR_SLAVE_WORD_SWAP_EN BIT11 +#define PCR_NS_ACCORDING_RCV_TRANS BIT14 +#define PCR_MASTER_PCIX_REQ64N_EN BIT15 +#define PCR_SLAVE_BYTE_SWAP_EN BIT16 +#define PCR_MASTER_DAC_EN BIT17 +#define PCR_MASTER_M64_ALLIGN BIT18 +#define PCR_ERRORS_PROPAGATION_EN BIT19 +#define PCR_SLAVE_SWAP_ENABLE BIT20 +#define PCR_MASTER_SWAP_ENABLE BIT21 +#define PCR_MASTER_INT_SWAP_EN BIT22 +#define PCR_LOOP_BACK_ENABLE BIT23 +#define PCR_SLAVE_INTREG_SWAP_OFFS 24 +#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 +#define PCR_SLAVE_INTREG_BYTE_SWAP \ + (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) +#define PCR_SLAVE_INTREG_NO_SWAP \ + (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) +#define PCR_SLAVE_INTREG_BYTE_WORD \ + (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) +#define PCR_SLAVE_INTREG_WORD_SWAP \ + (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) +#define PCR_RESET_REASSERTION_EN BIT26 +#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 +#define PCR_CPU_TO_PCI_ORDER_EN BIT29 +#define PCR_PCI_TO_CPU_ORDER_EN BIT30 + +/* PCI Mode Register (PMR) */ +#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ +#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) +#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) + +#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ +#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) +#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) +#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) + +#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ +#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) +#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) +#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) +#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) +#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) + +#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ + +#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ +#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) +#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) + + +/* PCI Retry Register (PRR) */ +#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ +#define PRR_RETRY_CNTR_MAX 0xff +#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) + + +/* PCI Discard Timer Register (PDTR) */ +#define PDTR_TIMER_OFFS 0 /* Timer */ +#define PDTR_TIMER_MAX 0xffff +#define PDTR_TIMER_MIN 0x7F +#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) + + +/* PCI Arbiter Control Register (PACR) */ +#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ + +#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ +#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) +#define PACR_BROKEN_VAL_CONV_MIN 0x2 +#define PACR_BROKEN_VAL_PCIX_MIN 0x6 + +#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ +#define PACR_PARK_DIS_MAX_AGENT 0x3f +#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); + return MV_ERROR; + } + } + + pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); + + switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) + { + case PXCR_DEV_TYPE_CTRL_CMPLX: + pexMode->pexType = MV_PEX_ROOT_COMPLEX; + break; + case PXCR_DEV_TYPE_CTRL_POINT: + pexMode->pexType = MV_PEX_END_POINT; + break; + + } + + /* Check if we have link */ + if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) + { + pexMode->pexLinkUp = MV_FALSE; + + /* If there is no link, the auto negotiation data is worthless */ + pexMode->pexWidth = MV_PEX_WITDH_INVALID; + } + else + { + pexMode->pexLinkUp = MV_TRUE; + + /* We have link. The link width is now valid */ + pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); + pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> + PXLCSR_NEG_LNK_WDTH_OFFS); + } + + return MV_OK; +} + + +/* PEX configuration space read write */ + +/******************************************************************************* +* mvPexConfigRead - Read from configuration space +* +* DESCRIPTION: +* This function performs a 32 bit read from PEX configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to read from local bus segment, use +* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pexIf - PEX interface number. +* bus - PEX segment bus number. +* dev - PEX device number. +* func - Function number. +* regOffs - Register offset. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit register data, 0xffffffff on error +* +*******************************************************************************/ +MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff) +{ +#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) + return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); +} + +MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff) +{ +#endif + MV_U32 pexData = 0; + MV_U32 localDev,localBus; + + /* Parameter checking */ + if (PEX_DEFAULT_IF != pexIf) + { + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); + return 0xFFFFFFFF; + } + } + + if (dev >= MAX_PEX_DEVICES) + { + DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); + return 0xFFFFFFFF; + } + + if (func >= MAX_PEX_FUNCS) + { + DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); + return 0xFFFFFFFF; + } + + if (bus >= MAX_PEX_BUSSES) + { + DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); + return MV_ERROR; + } + + DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", + pexIf, bus, dev, func, regOff)); + + localDev = mvPexLocalDevNumGet(pexIf); + localBus = mvPexLocalBusNumGet(pexIf); + + /* Speed up the process. In case on no link, return MV_ERROR */ + if ((dev != localDev) || (bus != localBus)) + { + pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + if ((pexData & PXSR_DL_DOWN)) + { + return MV_ERROR; + } + } + + /* in PCI Express we have only one device number */ + /* and this number is the first number we encounter + else that the localDev*/ + /* spec pex define return on config read/write on any device */ + if (bus == localBus) + { + if (localDev == 0) + { + /* if local dev is 0 then the first number we encounter + after 0 is 1 */ + if ((dev != 1)&&(dev != localDev)) + { + return MV_ERROR; + } + } + else + { + /* if local dev is not 0 then the first number we encounter + is 0 */ + + if ((dev != 0)&&(dev != localDev)) + { + return MV_ERROR; + } + } + if(func != 0 ) /* i.e bridge */ + { + return MV_ERROR; + } + } + + + /* Creating PEX address to be passed */ + pexData = (bus << PXCAR_BUS_NUM_OFFS); + pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); + pexData |= (func << PXCAR_FUNC_NUM_OFFS); + pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ + /* extended register space */ + pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> + PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); + + pexData |= PXCAR_CONFIG_EN; + + /* Write the address to the PEX configuration address register */ + MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); + + DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); + + + /* In order to let the PEX controller absorbed the address of the read */ + /* transaction we perform a validity check that the address was written */ + if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) + { + return MV_ERROR; + } + + /* cleaning Master Abort */ + MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), + PXSAC_MABORT); +#if 0 + /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ + /* This guideline is relevant for all devices except of the following devices: + 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above + 88F6183 A0 and above, 88F6183L */ + if ( ( (dev != localDev) || (bus != localBus) ) && + ( + !(MV_5281_DEV_ID == mvCtrlModelGet())&& + !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& + !(MV_1281_DEV_ID == mvCtrlModelGet())&& + !(MV_6183_DEV_ID == mvCtrlModelGet())&& + !(MV_6183L_DEV_ID == mvCtrlModelGet())&& + !(MV_6281_DEV_ID == mvCtrlModelGet())&& + !(MV_6282_DEV_ID == mvCtrlModelGet())&& + !(MV_6192_DEV_ID == mvCtrlModelGet())&& + !(MV_6190_DEV_ID == mvCtrlModelGet())&& + !(MV_6180_DEV_ID == mvCtrlModelGet())&& + !(MV_6280_DEV_ID == mvCtrlModelGet())&& + !(MV_78XX0_DEV_ID == mvCtrlModelGet()) + )) + { + + /* PCI-Express configuration read work-around */ + + /* we will use one of the Punit (AHBToMbus) windows to access the xbar + and read the data from there */ + /* + Need to configure the 2 free Punit (AHB to MBus bridge) + address decoding windows: + Configure the flash Window to handle Configuration space requests + for PEX0/1: + 1. write 0x7931/0x7941 to the flash window and the size, + 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn + 2. write base to flash window + + Configuration transactions from the CPU should write/read the data + to/from address of the form: + addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) + addr[27:24] = extended register number + addr[23:16] = bus number + addr[15:11] = device number + addr[10:8] = function number + addr[7:0] = register number + */ + + #include "ctrlEnv/sys/mvAhbToMbus.h" + { + MV_U32 winNum; + MV_AHB_TO_MBUS_DEC_WIN originWin; + MV_U32 pciAddr=0; + MV_U32 remapLow=0,remapHigh=0; + + /* + We will use DEV_CS2\Flash window for this workarround + */ + + winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); + + /* save remap values if exist */ + if ((1 == winNum)||(0 == winNum)) + { + remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); + remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); + + } + + + /* save the original window values */ + mvAhbToMbusWinGet(winNum,&originWin); + + if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) + { + /* set the window as xbar window */ + if (pexIf) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); + } + else + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); + } + + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), + originWin.addrWin.baseLow); + + /*pciAddr = originWin.addrWin.baseLow;*/ + pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( + (MV_U32)originWin.addrWin.baseLow); + + } + else + { + /* set the window as xbar window */ + if (pexIf) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); + } + else + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); + } + + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), + PEX_CONFIG_RW_WA_BASE); + + pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); + } + + + /* remap should be as base */ + if ((1 == winNum)||(0 == winNum)) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); + + } + + /* extended register space */ + pciAddr |= (bus << 16); + pciAddr |= (dev << 11); + pciAddr |= (func << 8); + pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ + + pexData = *(MV_U32*)pciAddr; + pexData = MV_32BIT_LE(pexData); /* Data always in LE */ + + /* restore the original window values */ + mvAhbToMbusWinSet(winNum,&originWin); + + /* restore original remap values*/ + if ((1 == winNum)||(0 == winNum)) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); + + } + } + } + else +#endif + { + /* Read the Data returned in the PEX Data register */ + pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); + + } + + DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); + + return pexData; + +} + +/******************************************************************************* +* mvPexConfigWrite - Write to configuration space +* +* DESCRIPTION: +* This function performs a 32 bit write to PEX configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to write to local bus segment, use +* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pexIf - PEX interface number. +* bus - PEX segment bus number. +* dev - PEX device number. +* func - Function number. +* regOffs - Register offset. +* data - 32bit data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data) +{ +#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) + return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); +} + +MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data) +{ +#endif + MV_U32 pexData = 0; + MV_U32 localDev,localBus; + + /* Parameter checking */ + if (PEX_DEFAULT_IF != pexIf) + { + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", + pexIf); + return MV_ERROR; + } + } + + if (dev >= MAX_PEX_DEVICES) + { + mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); + return MV_BAD_PARAM; + } + + if (func >= MAX_PEX_FUNCS) + { + mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); + return MV_ERROR; + } + + if (bus >= MAX_PEX_BUSSES) + { + mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); + return MV_ERROR; + } + + + + localDev = mvPexLocalDevNumGet(pexIf); + localBus = mvPexLocalBusNumGet(pexIf); + + + /* in PCI Express we have only one device number other than ourselves*/ + /* and this number is the first number we encounter + else than the localDev that can be any valid dev number*/ + /* pex spec define return on config read/write on any device */ + if (bus == localBus) + { + + if (localDev == 0) + { + /* if local dev is 0 then the first number we encounter + after 0 is 1 */ + if ((dev != 1)&&(dev != localDev)) + { + return MV_ERROR; + } + + } + else + { + /* if local dev is not 0 then the first number we encounter + is 0 */ + + if ((dev != 0)&&(dev != localDev)) + { + return MV_ERROR; + } + } + + + } + + /* if we are not accessing ourselves , then check the link */ + if ((dev != localDev) || (bus != localBus) ) + { + /* workarround */ + /* when no link return MV_ERROR */ + + pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + if ((pexData & PXSR_DL_DOWN)) + { + return MV_ERROR; + } + + } + + pexData =0; + + /* Creating PEX address to be passed */ + pexData |= (bus << PXCAR_BUS_NUM_OFFS); + pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); + pexData |= (func << PXCAR_FUNC_NUM_OFFS); + pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ + /* extended register space */ + pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> + PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); + pexData |= PXCAR_CONFIG_EN; + + DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", + pexIf,bus,func,dev,regOff,data,pexData) ); + + /* Write the address to the PEX configuration address register */ + MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); + + /* Clear CPU pipe. Important where CPU can perform OOO execution */ + CPU_PIPE_FLUSH; + + /* In order to let the PEX controller absorbed the address of the read */ + /* transaction we perform a validity check that the address was written */ + if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) + { + return MV_ERROR; + } + + /* Write the Data passed to the PEX Data register */ + MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); + + return MV_OK; + +} + +/******************************************************************************* +* mvPexMasterEnable - Enable/disale PEX interface master transactions. +* +* DESCRIPTION: +* This function performs read modified write to PEX command status +* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX +* master is allowed to gain ownership on the bus, otherwise it is +* incapable to do so. +* +* INPUT: +* pexIf - PEX interface number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) +{ + MV_U32 pexCommandStatus; + MV_U32 localBus; + MV_U32 localDev; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_ERROR; + } + + localBus = mvPexLocalBusNumGet(pexIf); + localDev = mvPexLocalDevNumGet(pexIf); + + pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, + PEX_STATUS_AND_COMMAND)); + + + if (MV_TRUE == enable) + { + pexCommandStatus |= PXSAC_MASTER_EN; + } + else + { + pexCommandStatus &= ~PXSAC_MASTER_EN; + } + + + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), + pexCommandStatus); + + return MV_OK; +} + + +/******************************************************************************* +* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. +* +* DESCRIPTION: +* This function performs read modified write to PEX command status +* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, +* the PEX slave is allowed to respond to PEX IO space access (bit 0) +* and PEX memory space access (bit 1). +* +* INPUT: +* pexIf - PEX interface number. +* dev - PEX device number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) +{ + MV_U32 pexCommandStatus; + MV_U32 RegOffs; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + if (dev >= MAX_PEX_DEVICES) + { + mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); + return MV_BAD_PARAM; + + } + + + RegOffs = PEX_STATUS_AND_COMMAND; + + pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); + + if (MV_TRUE == enable) + { + pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); + } + else + { + pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); + } + + mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); + + return MV_OK; + +} + +/******************************************************************************* +* mvPexLocalBusNumSet - Set PEX interface local bus number. +* +* DESCRIPTION: +* This function sets given PEX interface its local bus number. +* Note: In case the PEX interface is PEX-X, the information is read-only. +* +* INPUT: +* pexIf - PEX interface number. +* busNum - Bus number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PEX interface is PEX-X. +* MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) +{ + MV_U32 pexStatus; + MV_U32 localBus; + MV_U32 localDev; + + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); + return MV_BAD_PARAM; + } + if (busNum >= MAX_PEX_BUSSES) + { + mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); + return MV_ERROR; + + } + + localBus = mvPexLocalBusNumGet(pexIf); + localDev = mvPexLocalDevNumGet(pexIf); + + + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; + + pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; + + MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); + + + return MV_OK; +} + + +/******************************************************************************* +* mvPexLocalBusNumGet - Get PEX interface local bus number. +* +* DESCRIPTION: +* This function gets the local bus number of a given PEX interface. +* +* INPUT: +* pexIf - PEX interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local bus number.0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) +{ + MV_U32 pexStatus; + + /* Parameter checking */ + if (PEX_DEFAULT_IF != pexIf) + { + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); + return 0xFFFFFFFF; + } + } + + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= PXSR_PEX_BUS_NUM_MASK; + + return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); + +} + + +/******************************************************************************* +* mvPexLocalDevNumSet - Set PEX interface local device number. +* +* DESCRIPTION: +* This function sets given PEX interface its local device number. +* Note: In case the PEX interface is PEX-X, the information is read-only. +* +* INPUT: +* pexIf - PEX interface number. +* devNum - Device number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PEX interface is PEX-X. +* MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) +{ + MV_U32 pexStatus; + MV_U32 localBus; + MV_U32 localDev; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); + return MV_BAD_PARAM; + } + if (devNum >= MAX_PEX_DEVICES) + { + mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", + devNum); + return MV_BAD_PARAM; + + } + + localBus = mvPexLocalBusNumGet(pexIf); + localDev = mvPexLocalDevNumGet(pexIf); + + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; + + pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; + + MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); + + + return MV_OK; +} + +/******************************************************************************* +* mvPexLocalDevNumGet - Get PEX interface local device number. +* +* DESCRIPTION: +* This function gets the local device number of a given PEX interface. +* +* INPUT: +* pexIf - PEX interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local device number. 0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) +{ + MV_U32 pexStatus; + + /* Parameter checking */ + + if (PEX_DEFAULT_IF != pexIf) + { + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", + pexIf); + return 0xFFFFFFFF; + } + } + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= PXSR_PEX_DEV_NUM_MASK; + + return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); +} + +MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) +{ + + MV_U32 regAddr; + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); + return; + } + regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); + *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); +} + + +MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) +{ + + MV_U32 regAddr; + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); + return; + } + regAddr = (((regOffset & 0x3fff) << 16) | value); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); +} + + +/******************************************************************************* +* mvPexActiveStateLinkPMEnable +* +* DESCRIPTION: +* Enable Active Link State Power Management +* +* INPUT: +* pexIf - PEX interface number. +* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK on success , MV_ERROR otherwise +* +*******************************************************************************/ +MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) +{ + MV_U32 reg; + + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_ERROR; + } + + reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; + if(enable == MV_TRUE) + reg |= PXPMER_L1_ASPM_EN_MASK; + MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); + + /* Enable / Disable L0/1 entry */ + reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) + & ~PXLCSR_ASPM_CNT_MASK; + if(enable == MV_TRUE) + reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); + + return MV_OK; +} + + +/******************************************************************************* +* mvPexForceX1 +* +* DESCRIPTION: +* shut down lanes 1-3 if recognize that attached to an x1 end-point +* INPUT: +* pexIf - PEX interface number. +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK on success , MV_ERROR otherwise +* +*******************************************************************************/ +MV_U32 mvPexForceX1(MV_U32 pexIf) +{ + MV_U32 regData = 0; + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; + regData |= PXCR_CONF_LINK_X1; + + MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); + return MV_OK; +} + +MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) +{ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); + return MV_FALSE; + } + return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); +} + + +MV_VOID mvPexPowerDown(MV_U32 pexIf) +{ + if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || + (mvCtrlModelGet() == MV_76100_DEV_ID) || + (mvCtrlModelGet() == MV_78100_DEV_ID) || + (mvCtrlModelGet() == MV_78200_DEV_ID) || + (mvCtrlModelGet() == MV_6321_DEV_ID) || + (mvCtrlModelGet() == MV_6322_DEV_ID) || + (mvCtrlModelGet() == MV_6323_DEV_ID)) + { + mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); + } + else + { + MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); + } +} + + + diff --git a/board/mv_feroceon/mv_hal/pex/mvPex.h b/board/mv_feroceon/mv_hal/pex/mvPex.h new file mode 100644 index 0000000..d8f1cdd --- /dev/null +++ b/board/mv_feroceon/mv_hal/pex/mvPex.h @@ -0,0 +1,168 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPEXH +#define __INCPEXH + +#include "mvCommon.h" +#include "mvOs.h" +#include "pex/mvPexRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + + + +/* NOTE not supported in this driver:*/ + + +/* defines */ +/* The number of supported PEX interfaces depend on Marvell controller */ +/* device number. This device number ID is located on the PEX unit */ +/* configuration header. This creates a loop where calling PEX */ +/* configuration read/write routine results a call to get PEX configuration */ +/* information etc. This macro defines a default PEX interface. This PEX */ +/* interface is sure to exist. */ +#define PEX_DEFAULT_IF 0 + + +/* typedefs */ +/* The Marvell controller supports both root complex and end point devices */ +/* This enumeration describes the PEX type. */ +typedef enum _mvPexType +{ + MV_PEX_ROOT_COMPLEX, /* root complex device */ + MV_PEX_END_POINT /* end point device */ +}MV_PEX_TYPE; + +typedef enum _mvPexWidth +{ + MV_PEX_WITDH_X1 = 1, + MV_PEX_WITDH_X2, + MV_PEX_WITDH_X3, + MV_PEX_WITDH_X4, + MV_PEX_WITDH_INVALID +}MV_PEX_WIDTH; + +/* PEX Bar attributes */ +typedef struct _mvPexMode +{ + MV_PEX_TYPE pexType; + MV_PEX_WIDTH pexWidth; + MV_BOOL pexLinkUp; +}MV_PEX_MODE; + + + +/* Global Functions prototypes */ +/* mvPexInit - Initialize PEX interfaces*/ +MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); + +/* mvPexModeGet - Get Pex If mode */ +MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); + +/* mvPexConfigRead - Read from configuration space */ +MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func,MV_U32 regOff); + +/* mvPexConfigWrite - Write to configuration space */ +MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data); + +/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ +MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); + +/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ +MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); + +/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ +MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); + +/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ +MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); + +/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ +MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); + +/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ +MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); +/* mvPexForceX1 - Force PEX interface to X1 mode. */ +MV_U32 mvPexForceX1(MV_U32 pexIf); + +/* mvPexIsPowerUp - Is PEX interface Power up? */ +MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); + +/* mvPexPowerDown - Power Down */ +MV_VOID mvPexPowerDown(MV_U32 pexIf); + +/* mvPexPowerUp - Power Up */ +MV_VOID mvPexPowerUp(MV_U32 pexIf); + +/* mvPexPhyRegRead - Pex phy read */ +MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); + +/* mvPexPhyRegWrite - Pex phy write */ +MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); + +MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); + +#endif /* #ifndef __INCPEXH */ diff --git a/board/mv_feroceon/mv_hal/pex/mvPexRegs.h b/board/mv_feroceon/mv_hal/pex/mvPexRegs.h new file mode 100644 index 0000000..8ac1698 --- /dev/null +++ b/board/mv_feroceon/mv_hal/pex/mvPexRegs.h @@ -0,0 +1,751 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPEXREGSH +#define __INCPEXREGSH + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ +#define MAX_PEX_DEVICES 32 +#define MAX_PEX_FUNCS 8 +#define MAX_PEX_BUSSES 256 + + + +/*********************************************************/ +/* PCI Express Configuration Cycles Generation Registers */ +/*********************************************************/ + +#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) +#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) +#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) +/* PCI Express Configuration Address Register */ +/* PEX_CFG_ADDR_REG (PXCAR)*/ + +#define PXCAR_REG_NUM_OFFS 2 +#define PXCAR_REG_NUM_MAX 0x3F +#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) +#define PXCAR_FUNC_NUM_OFFS 8 +#define PXCAR_FUNC_NUM_MAX 0x7 +#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) +#define PXCAR_DEVICE_NUM_OFFS 11 +#define PXCAR_DEVICE_NUM_MAX 0x1F +#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) +#define PXCAR_BUS_NUM_OFFS 16 +#define PXCAR_BUS_NUM_MAX 0xFF +#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) +#define PXCAR_EXT_REG_NUM_OFFS 24 +#define PXCAR_EXT_REG_NUM_MAX 0xF + +/* in pci express register address is now the legacy register address (8 bits) +with the new extended register address (more 4 bits) , below is the mask of +the upper 4 bits of the full register address */ + +#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 +#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) +#define PXCAR_CONFIG_EN BIT31 + +#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 +#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) + +/* The traditional PCI spec defined 6-bit field to describe register offset.*/ +/* The new PCI Express extend the register offset by an extra 4-bits. */ +/* The below macro assign 10-bit register offset into the apprpreate */ +/* fields in the CFG_ADDR_REG */ +#define PXCAR_REG_OFFS_SET(regOffs) \ + ( (regOff & PXCAR_REG_NUM_MASK) | \ + ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) + +/***********************************/ +/* PCI Express Interrupt registers */ +/***********************************/ +#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) +#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) + +#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ + /* of the PCI Express */ +/* PCI Express Interrupt Cause */ +/* PEX_INT_CAUSE_REG (PXICR)*/ +/* PEX_INT_MASK_REG*/ +/* +NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets +upon an error event occurrence. A write of 0 clears the bit. A write of 1 has +no affect. Bits[24:27} are set and cleared upon reception of interrupt +emulation messages. + +Mask bit per cause bit. If a bit is set to 1, the corresponding event is +enabled. Mask does not affect setting of the Interrupt Cause register bits; +it only affects the assertion of the interrupt .*/ + + +#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction + while master is disabled */ +#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to + PCI Express internal register*/ +#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ +#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ +#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ +#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ +#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ +#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ +#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ +#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ +#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ + +#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ +#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ +#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ +#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ +#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ +#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ +#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ +#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ +#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ +#define PXICR_RCV_INTA BIT24 /* IntA status.*/ +#define PXICR_RCV_INTB BIT25 /* IntB status.*/ +#define PXICR_RCV_INTC BIT26 /* IntC status.*/ +#define PXICR_RCV_INTD BIT27 /* IntD status.*/ +#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ + + +/********************************************/ +/* PCI Express Control and Status Registers */ +/********************************************/ +#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) +#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) +#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) +#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) +#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) +#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) +#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) +#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) + + +#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) +/* PCI Express Control Register */ +/* PEX_CTRL_REG (PXCR) */ + +#define PXCR_CONF_LINK_OFFS 0 +#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) +#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) +#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) +#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ +#define PXCR_DEV_TYPE_CTRL_MASK BIT1 +#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) +#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) +#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping + to Memory Space Enable */ + +#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping + to Memory Space Enable*/ + +#define PXCR_RSRV1_OFFS 5 +#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) +#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) + +#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ +#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) + + +#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ +#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) + +#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ +#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ +#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ +#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ + +/* PCI Express Status Register */ +/* PEX_STATUS_REG (PXSR) */ + +#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ + +#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ +#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) + +#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ +#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) + +#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ +#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ +#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ +#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ + + +/* PCI Express Completion Timeout Register */ +/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ + +#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ +#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) + +/* PCI Express Power Management Extended Register */ +/* PEX_PWR_MNG_EXT_REG (PXPMER) */ + +#define PXPMER_L1_ASPM_EN_OFFS 1 +#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) + +/* PCI Express Flow Control Register */ +/* PEX_FLOW_CTRL_REG (PXFCR)*/ + +#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit + Initial Value.*/ +#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) + + +#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers + Flow Control Credit Initial Value*/ +#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) + +#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control + Credit Initial Value Infinite*/ + +#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) + +#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ +#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) + +/* PCI Express Acknowledge Timers (4X) Register */ +/* PEX_ACK_TMR_4X_REG (PXAT4R) */ +#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ +#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) +#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ +#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) + +/* PCI Express Acknowledge Timers (1X) Register */ +/* PEX_ACK_TMR_1X_REG (PXAT1R) */ + +#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout + Value for 1X Link*/ +#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) + +#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout + Value for 1X*/ +#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) + + +/* PCI Express TL Control Register */ +/* PEX_TL_CTRL_REG (PXTCR) */ + +#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ +#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) + +/* PCI Express Debug MAC Control Register */ +/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ + +#define PXDMCR_LINKUP BIT4 + + + +/**********************************************/ +/* PCI Express Configuration Header Registers */ +/**********************************************/ +#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) + +#define PEX_DEVICE_AND_VENDOR_ID 0x000 +#define PEX_STATUS_AND_COMMAND 0x004 +#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 +#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C +#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) +#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) +#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) +#define PEX_BAR0_INTER_REG 0x010 +#define PEX_BAR0_INTER_REG_HIGH 0x014 +#define PEX_BAR1_REG 0x018 +#define PEX_BAR1_REG_HIGH 0x01C +#define PEX_BAR2_REG 0x020 +#define PEX_BAR2_REG_HIGH 0x024 + +#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C +#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 +#define PEX_CAPABILTY_LIST_POINTER 0x034 +#define PEX_INTERRUPT_PIN_AND_LINE 0x03C + +/* capability list */ +#define PEX_POWER_MNG_CAPABILITY 0x040 +#define PEX_POWER_MNG_STATUS_CONTROL 0x044 + +#define PEX_MSI_MESSAGE_CONTROL 0x050 +#define PEX_MSI_MESSAGE_ADDR 0x054 +#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 +#define PEX_MSI_MESSAGE_DATA 0x05C + +#define PEX_CAPABILITY_REG 0x60 +#define PEX_DEV_CAPABILITY_REG 0x64 +#define PEX_DEV_CTRL_STAT_REG 0x68 +#define PEX_LINK_CAPABILITY_REG 0x6C +#define PEX_LINK_CTRL_STAT_REG 0x70 + +#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 +#define PEX_UNCORRECT_ERR_STAT_REG 0x104 +#define PEX_UNCORRECT_ERR_MASK_REG 0x108 +#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C +#define PEX_CORRECT_ERR_STAT_REG 0x110 +#define PEX_CORRECT_ERR_MASK_REG 0x114 +#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 +#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C +#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 +#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 +#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 + + + +/* PCI Express Device and Vendor ID Register*/ +/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ + +#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ +#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) + +#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ +#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) + + +/* PCI Express Command and Status Register*/ +/*PEX_STATUS_AND_COMMAND (PXSAC)*/ + +#define PXSAC_IO_EN BIT0 /* IO Enable */ +#define PXSAC_MEM_EN BIT1 /* Memory Enable */ +#define PXSAC_MASTER_EN BIT2 /* Master Enable */ +#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ +#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ +#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ +#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ +#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ +#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ +#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ +#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ +#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ +#define PXSAC_SYSERR BIT30 /* Signalled system error */ +#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ + + +/* PCI Express Class Code and Revision ID Register*/ +/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ + +#define PXCCARI_REVID_OFFS 0 /* Revision ID */ +#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) + +#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ +#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) + +#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ +#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) + +#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ +#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) + +#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ +#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) + + +/* PCI Express BIST, Header Type and Cache Line Size Register*/ +/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ + +#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ +#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) + +#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ +#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) + +#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ + +#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ +#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) +#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) +#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) + + +#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ +#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) + +#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ +#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ +#define PXBHTLTCL_BISTCAP_OFFS 31 +#define PXBHTLTCL_BISTCAP_MASK BIT31 +#define PXBHTLTCL_BISTCAP_VAL 0 + + +/* PCI Express Subsystem Device and Vendor ID */ +/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ + +#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ +#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) + +#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ +#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) + + +/* PCI Express Capability List Pointer Register*/ +/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ + +#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ +#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) + +/* PCI Express Interrupt Pin and Line Register */ +/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ + +#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ +#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) + +#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ +#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) + + +/* PCI Express Power Management Capability Header Register*/ +/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ + +#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ +#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) + +#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ +#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) + +#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ +#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) + +#define PXPMC_DSI BIT21/* Device Specific Initialization */ + +#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ +#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) + +#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ + +#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ + +#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ +#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) + +/* PCI Express Power Management Control and Status Register*/ +/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ + +#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ +#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) + +#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ + +#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ +#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) + +#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ +#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) + +#define PXPMSC_PME_STAT BIT15/* PME Status */ + +#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ +#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) + + +/* PCI Express MSI Message Control Register*/ +/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ + +#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ +#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) + +#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ +#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) + +#define PXMMC_MSI_EN BIT18 /* MSI Enable */ + +#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ +#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) + +#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ +#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) + +#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ + + +/* PCI Express MSI Message Address Register*/ +/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ + +#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to + Address[31:2] of the MSI MWr TLP*/ +#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) + + +/* PCI Express MSI Message Address (High) Register */ +/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ + +#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to + Address[63:32] of the MSI MWr TLP*/ +#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) + + +/* PCI Express MSI Message Data Register*/ +/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ + +#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ +#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) + + +/* PCI Express Capability Register*/ +/*PEX_CAPABILITY_REG (PXCR)*/ + +#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ +#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) + +#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ +#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) + +#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ +#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) + +#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ +#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) + +#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ + +#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ +#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) + + +/* PCI Express Device Capabilities Register */ +/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ + +#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ +#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) + +#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ +#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) + +#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ +#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) + + +#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ +#define PXDCR_ATT_BUT_PRS_MASK BIT12 +#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 + +#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ +#define PXDCR_ATT_IND_PRS_MASK BIT13 +#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 + +#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ +#define PXDCR_PWR_IND_PRS_MASK BIT14 +#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 + +#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit + Value*/ +#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) + +#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit + Scale */ +#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) + +/* PCI Express Device Control Status Register */ +/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ + +#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ +#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ +#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ +#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) + Reporting Enable*/ +#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ + +#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ +#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) +#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) +#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ + +#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ +#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) + +#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ +#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ +#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ +#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ +#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ + +#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ +#define PXDCSR_TRANS_PEND_MASK BIT21 +#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) + + +/* PCI Express Link Capabilities Register*/ +/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ + +#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ +#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) + +#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ +#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) + +#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ +#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) + +#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ +#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) + +#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ +#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) + +/* PCI Express Link Control Status Register */ +/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ + +#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ +#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) + +#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ +#define PXLCSR_RCB_MASK BIT3 +#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) +#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) + +#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ +#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ +#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ +#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ + +#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ +#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) + +#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ +#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) +#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) + +#define PXLCSR_LNK_TRN BIT27 /* Link Training */ + +#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ +#define PXLCSR_SLT_CLK_CFG_MASK BIT28 +#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) +#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) + +/* PCI Express Advanced Error Report Header Register */ +/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ + +/* PCI Express Uncorrectable Error Status Register*/ +/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ + +/* PCI Express Uncorrectable Error Mask Register */ +/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ + +/* PCI Express Uncorrectable Error Severity Register */ +/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ + +/* PCI Express Correctable Error Status Register */ +/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ + +/* PCI Express Correctable Error Mask Register */ +/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ + +/* PCI Express Advanced Error Capability and Control Register*/ +/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ + +/* PCI Express Header Log First DWORD Register*/ +/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ + +/* PCI Express Header Log Second DWORD Register*/ +/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ + +/* PCI Express Header Log Third DWORD Register*/ +/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ + +/* PCI Express Header Log Fourth DWORD Register*/ +/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* #ifndef __INCPEXREGSH */ + + diff --git a/board/mv_feroceon/mv_hal/pex/mvVrtBrgPex.c b/board/mv_feroceon/mv_hal/pex/mvVrtBrgPex.c new file mode 100644 index 0000000..19c871a --- /dev/null +++ b/board/mv_feroceon/mv_hal/pex/mvVrtBrgPex.c @@ -0,0 +1,313 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvPex.h" + +//#define MV_DEBUG +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* locals */ +typedef struct +{ + MV_U32 data; + MV_U32 mask; +}PEX_HEADER_DATA; + +/* local function forwad decleration */ +MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff); +MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data); +void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); + + +PEX_HEADER_DATA configHdr[16] = +{ +{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ +{0x00100007, 0x0000ffff}, /*[status register, command register] */ +{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ +{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ +{0x00000000, 0x00000000}, /*[base address 0] */ +{0x00000000, 0x00000000}, /*[base address 1] */ +{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ +{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ +{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ +{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ +{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ +{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ +{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ +{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ +{0x00000000, 0x00000000}, /*[expansion ROM base address] */ +{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ +}; + + +#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ + (data & configHdr[offset/4].mask)) +#define HEADER_READ(offset) configHdr[offset/4].data + +/******************************************************************************* +* mvVrtBrgPexInit - Initialize PEX interfaces +* +* DESCRIPTION: +* +* This function is responsible of intialization of the Pex Interface , It +* configure the Pex Bars and Windows in the following manner: +* +* Assumptions : +* Bar0 is always internal registers bar +* Bar1 is always the DRAM bar +* Bar2 is always the Device bar +* +* 1) Sets the Internal registers bar base by obtaining the base from +* the CPU Interface +* 2) Sets the DRAM bar base and size by getting the base and size from +* the CPU Interface when the size is the sum of all enabled DRAM +* chip selects and the base is the base of CS0 . +* 3) Sets the Device bar base and size by getting these values from the +* CPU Interface when the base is the base of the lowest base of the +* Device chip selects, and the +* +* +* INPUT: +* +* pexIf - PEX interface number. +* +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM +* +*******************************************************************************/ +MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) +{ + /* reset PEX tree to recover previous U-boot/Boot configurations */ + MV_U32 localBus = mvPexLocalBusNumGet(pexIf); + + + resetPexConfig(pexIf, localBus, 1); + return MV_OK; +} + + +MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff) +{ + + MV_U32 localBus = mvPexLocalBusNumGet(pexIf); + MV_U32 localDev = mvPexLocalDevNumGet(pexIf); + MV_U32 val; + if(bus == localBus) + { + if(dev > 1) + { +/* on the local device allow only device #0 & #1 */ + return 0xffffffff; + } + else + if (dev == localDev) + { + /* read the memory controller registers */ + return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); + } + else + { + /* access the virtual brg header */ + return HEADER_READ(regOff); + } + } + else + if(bus == (localBus + 1)) + { + /* access the device behind the virtual bridge */ + if((dev == localDev) || (dev > 1)) + { + return 0xffffffff; + } + else + { + /* access the device behind the virtual bridge, in this case + * change the bus number to the local bus number in order to + * generate type 0 config cycle + */ + mvPexLocalBusNumSet(pexIf, bus); + mvPexLocalDevNumSet(pexIf, 1); + val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); + mvPexLocalBusNumSet(pexIf, localBus); + mvPexLocalDevNumSet(pexIf, localDev); + return val; + } + } + /* for all other devices use the HW function to get the + * requested registers + */ + mvPexLocalDevNumSet(pexIf, 1); + val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); + mvPexLocalDevNumSet(pexIf, localDev); + return val; +} + + +MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data) +{ + MV_U32 localBus = mvPexLocalBusNumGet(pexIf); + MV_U32 localDev = mvPexLocalDevNumGet(pexIf); + MV_STATUS status; + + if(bus == localBus) + { + if(dev > 1) + { + /* on the local device allow only device #0 & #1 */ + return MV_ERROR; + } + else + if (dev == localDev) + { + /* read the memory controller registers */ + return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); + } + else + { + /* access the virtual brg header */ + HEADER_WRITE(data, regOff); + return MV_OK; + } + } + else + if(bus == (localBus + 1)) + { + /* access the device behind the virtual bridge */ + if((dev == localDev) || (dev > 1)) + { + return MV_ERROR; + } + else + { + /* access the device behind the virtual bridge, in this case + * change the bus number to the local bus number in order to + * generate type 0 config cycle + */ + //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); + mvPexLocalBusNumSet(pexIf, bus); + mvPexLocalDevNumSet(pexIf, 1); + status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); + mvPexLocalBusNumSet(pexIf, localBus); + mvPexLocalDevNumSet(pexIf, localDev); + return status; + + } + } + /* for all other devices use the HW function to get the + * requested registers + */ + mvPexLocalDevNumSet(pexIf, 1); + status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); + mvPexLocalDevNumSet(pexIf, localDev); + return status; +} + + + + +void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) +{ + MV_U32 tData; + MV_U32 i; + + /* restore the PEX configuration to initialization state */ + /* in case PEX P2P call recursive and reset config */ + tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); + if(tData != 0xffffffff) + { + /* agent had been found - check whether P2P */ + tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); + if((tData & 0xffff0000) == 0x06040000) + {/* P2P */ + /* get the sec bus and the subordinate */ + MV_U32 secBus; + tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); + secBus = ((tData >> 8) & 0xff); + /* now scan on sec bus */ + for(i = 0;i < 0xff;i++) + { + resetPexConfig(pexIf, secBus, i); + } + /* now reset this device */ + DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); + mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); + DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); + } + } +} + + diff --git a/board/mv_feroceon/mv_hal/pex/mvVrtBrgPex.h b/board/mv_feroceon/mv_hal/pex/mvVrtBrgPex.h new file mode 100644 index 0000000..82eb72d --- /dev/null +++ b/board/mv_feroceon/mv_hal/pex/mvVrtBrgPex.h @@ -0,0 +1,82 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCVRTBRGPEXH +#define __INCVRTBRGPEXH + + +/* Global Functions prototypes */ +/* mvPexInit - Initialize PEX interfaces*/ +MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); + +/* mvPexConfigRead - Read from configuration space */ +MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func,MV_U32 regOff); + +/* mvPexConfigWrite - Write to configuration space */ +MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data); + + +#endif /* #ifndef __INCPEXH */ diff --git a/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS1339.c b/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS1339.c new file mode 100644 index 0000000..cb08bc5 --- /dev/null +++ b/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS1339.c @@ -0,0 +1,321 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "rtc/ext_rtc/mvDS1339.h" +#include "rtc/ext_rtc/mvDS1339Reg.h" + +static MV_VOID mvRtcCharWrite(MV_U32 offset, MV_U8 data); +static MV_VOID mvRtcCharRead(MV_U32 offset, MV_U8 *data); + + +/******************************************************************************* +* mvRtcDS1339TimeSet - Set the Alarm of the Real time clock +* +* DESCRIPTION: +* +* INPUT: +* time - A pointer to a structure RTC_TIME (defined in mvDS1339.h). +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvRtcDS1339AlarmSet(MV_RTC_TIME* mvTime) +{ + return; +} +/******************************************************************************* +* mvRtcDS1339TimeSet - Update the Real Time Clock. +* +* DESCRIPTION: +* This function sets a new time and date to the RTC from the given +* structure RTC_TIME . All fields within the structure must be assigned +* with a value prior to the use of this function. +* +* INPUT: +* time - A pointer to a structure RTC_TIME (defined in mvDS1339.h). +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvRtcDS1339TimeSet(MV_RTC_TIME* mvTime) +{ + MV_U8 tempValue; + MV_U8 tens; + MV_U8 single; + + /* seconds */ + tens = mvTime->seconds / 10; + single = mvTime->seconds % 10; + tempValue = ((tens << RTC_CLOCK_10SECONDS_SHF )& RTC_CLOCK_10SECONDS_MSK )| + (( single << RTC_CLOCK_SECONDS_SHF)&RTC_CLOCK_SECONDS_MSK) ; + mvRtcCharWrite(RTC_CLOCK_SECONDS,tempValue); + + /* minutes */ + tens = mvTime->minutes / 10; + single = mvTime->minutes % 10; + tempValue = ((tens << RTC_CLOCK_10MINUTES_SHF )& RTC_CLOCK_10MINUTES_MSK )| + (( single << RTC_CLOCK_MINUTES_SHF)& RTC_CLOCK_MINUTES_MSK) ; + mvRtcCharWrite(RTC_CLOCK_MINUTES,tempValue); + + /* hours (24) */ + tens = mvTime->hours / 10; + single = mvTime->hours % 10; + tempValue = ((tens << RTC_CLOCK_10HOURS_SHF) & RTC_CLOCK_10HOURS_MSK2 )| + (( single << RTC_CLOCK_HOURS_SHF ) & RTC_CLOCK_HOURS_MSK); + mvRtcCharWrite(RTC_CLOCK_HOUR,tempValue); + + /* day */ + single = mvTime->day; + tempValue = ((single << RTC_CLOCK_DAY_SHF ) & RTC_CLOCK_DAY_MSK) ; + mvRtcCharWrite(RTC_CLOCK_DAY,tempValue); + + /* date */ + tens = mvTime->date / 10; + single = mvTime->date % 10; + tempValue = ((tens << RTC_CLOCK_10DATE_SHF ) & RTC_CLOCK_10DATE_MSK )| + ((single << RTC_CLOCK_DATE_SHF )& RTC_CLOCK_DATE_MSK) ; + + /* month */ + mvRtcCharWrite( RTC_CLOCK_DATE,tempValue); + tens = mvTime->month / 10; + single = mvTime->month % 10; + tempValue = ((tens << RTC_CLOCK_10MONTH_SHF ) & RTC_CLOCK_10MONTH_MSK )| + ((single << RTC_CLOCK_MONTH_SHF)& RTC_CLOCK_MONTH_MSK); + mvRtcCharWrite( RTC_CLOCK_MONTH_CENTURY,tempValue); + + /* year */ + tens = mvTime->year / 10; + single = mvTime->year % 10; + tempValue = ((tens << RTC_CLOCK_10YEAR_SHF) & RTC_CLOCK_10YEAR_MSK )| + ((single << RTC_CLOCK_YEAR_SHF) & RTC_CLOCK_YEAR_MSK); + mvRtcCharWrite(RTC_CLOCK_YEAR,tempValue); + + return; +} + +/******************************************************************************* +* mvRtcDS1339TimeGet - Read the time from the RTC. +* +* DESCRIPTION: +* This function reads the current time and date from the RTC into the +* structure RTC_TIME (defined in mvDS1339.h). +* +* INPUT: +* time - A pointer to a structure TIME (defined in mvDS1339.h). +* +* OUTPUT: +* The structure RTC_TIME is updated with the time read from the RTC. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvRtcDS1339TimeGet(MV_RTC_TIME* mvTime) +{ + MV_U8 tempValue; + MV_U32 tens; + MV_U32 single; + + /* seconds */ + mvRtcCharRead(RTC_CLOCK_SECONDS,&tempValue); + tens = ( tempValue & RTC_CLOCK_10SECONDS_MSK) >> RTC_CLOCK_10SECONDS_SHF; + single = (tempValue & RTC_CLOCK_SECONDS_MSK) >> RTC_CLOCK_SECONDS_SHF ; + mvTime->seconds = 10*tens + single; + + /* minutes */ + mvRtcCharRead(RTC_CLOCK_MINUTES,&tempValue); + tens = (tempValue & RTC_CLOCK_10MINUTES_MSK) >> RTC_CLOCK_10MINUTES_SHF; + single = (tempValue & RTC_CLOCK_MINUTES_MSK) >> RTC_CLOCK_MINUTES_SHF; + mvTime->minutes = 10*tens + single; + + /* hours */ + mvRtcCharRead(RTC_CLOCK_HOUR,&tempValue); + tens = (tempValue & RTC_CLOCK_10HOURS_MSK2) >> RTC_CLOCK_10HOURS_SHF; + single = (tempValue & RTC_CLOCK_HOURS_MSK) >> RTC_CLOCK_HOURS_SHF; + mvTime->hours = 10*tens + single; + + /* day */ + mvRtcCharRead(RTC_CLOCK_DAY,&tempValue); + mvTime->day = (tempValue & RTC_CLOCK_DAY_MSK) >> RTC_CLOCK_DAY_SHF ; + + /* date */ + mvRtcCharRead(RTC_CLOCK_DATE,&tempValue); + tens = (tempValue & RTC_CLOCK_10DATE_MSK) >> RTC_CLOCK_10DATE_SHF; + single = (tempValue & RTC_CLOCK_DATE_MSK) >> RTC_CLOCK_DATE_SHF; + mvTime->date = 10*tens + single; + + /* century/ month */ + mvRtcCharRead(RTC_CLOCK_MONTH_CENTURY,&tempValue); + tens = (tempValue & RTC_CLOCK_10MONTH_MSK) >> RTC_CLOCK_10MONTH_SHF; + single = (tempValue & RTC_CLOCK_MONTH_MSK) >> RTC_CLOCK_MONTH_SHF; + mvTime->month = 10*tens + single; + mvTime->century = (tempValue & RTC_CLOCK_CENTURY_MSK)>>RTC_CLOCK_CENTURY_SHF; + + /* year */ + mvRtcCharRead(RTC_CLOCK_YEAR,&tempValue); + tens = (tempValue & RTC_CLOCK_10YEAR_MSK) >> RTC_CLOCK_10YEAR_SHF; + single = (tempValue & RTC_CLOCK_YEAR_MSK) >> RTC_CLOCK_YEAR_SHF; + mvTime->year = 10*tens + single; + + return; +} + +/******************************************************************************* +* mvRtcDS1339Init - Initialize the clock. +* +* DESCRIPTION: +* This function initialize the clock registers and read\write functions +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvRtcDS1339Init(MV_VOID) +{ + MV_U8 ucTemp; + + /* We will disable interrupts as default .*/ + mvRtcCharRead(RTC_CONTROL,&ucTemp); + ucTemp|=RTC_CONTROL_INTCN_BIT; + mvRtcCharWrite(RTC_CONTROL,ucTemp); + + /* disable trickle */ + mvRtcCharWrite(RTC_TRICKLE_CHARGE,0); + + return; +} + + +/* assumption twsi is initialized !!! */ +/******************************************************************************* +* mvRtcCharRead - Read a char from the RTC. +* +* DESCRIPTION: +* This function reads a char from the RTC offset. +* +* INPUT: +* offset - offset +* +* OUTPUT: +* data - char read from offset offset. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID mvRtcCharRead(MV_U32 offset, MV_U8 *data) +{ + MV_TWSI_SLAVE twsiSlave; + + twsiSlave.slaveAddr.type = mvBoardRtcTwsiAddrTypeGet(); + twsiSlave.slaveAddr.address = mvBoardRtcTwsiAddrGet(); + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = offset; + twsiSlave.moreThen256 = MV_FALSE; + mvTwsiRead (MV_BOARD_RTC_I2C_CHANNEL, &twsiSlave, data, 1); + return; +} + +/******************************************************************************* +* mvRtcCharWrite - Write a char from the RTC. +* +* DESCRIPTION: +* This function writes a char to the RTC offset. +* +* INPUT: +* offset - offset +* +* OUTPUT: +* data - char write to addr address. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID mvRtcCharWrite(MV_U32 offset, MV_U8 data) +{ + MV_TWSI_SLAVE twsiSlave; + + twsiSlave.slaveAddr.type = mvBoardRtcTwsiAddrTypeGet(); + twsiSlave.slaveAddr.address = mvBoardRtcTwsiAddrGet(); + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = offset; + twsiSlave.moreThen256 = MV_FALSE; + mvTwsiWrite (MV_BOARD_RTC_I2C_CHANNEL, &twsiSlave, &data, 1); + return; +} diff --git a/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS1339.h b/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS1339.h new file mode 100644 index 0000000..e2f9761 --- /dev/null +++ b/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS1339.h @@ -0,0 +1,96 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDS1339h +#define __INCmvDS1339h + +#include "mvTypes.h" +#include "twsi/mvTwsi.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "boardEnv/mvBoardEnvSpec.h" + +typedef struct time +{ + MV_U8 seconds; + MV_U8 minutes; + MV_U8 hours; + MV_U8 day; + MV_U8 date; + MV_U8 month; + MV_U8 century; + MV_U8 year; +} MV_RTC_TIME; + +MV_VOID mvRtcDS1339Init(MV_VOID); + +MV_VOID mvRtcDS1339TimeSet(MV_RTC_TIME* time); + +MV_VOID mvRtcDS1339TimeGet(MV_RTC_TIME* time); + +MV_VOID mvRtcDS1339AlarmSet(MV_RTC_TIME* time); + + +#endif /* __INCmvDS1511h */ + diff --git a/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS1339Reg.h b/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS1339Reg.h new file mode 100644 index 0000000..a9975a3 --- /dev/null +++ b/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS1339Reg.h @@ -0,0 +1,368 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDS1339Regh +#define __INCmvDS1339Regh + +#ifndef MSK +#define MSK(n) ((1 << (n)) - 1) +#endif + +#define RTC_CLOCK_SECONDS 0x0 +#define RTC_CLOCK_MINUTES 0x1 +#define RTC_CLOCK_HOUR 0x2 +#define RTC_CLOCK_DAY 0x3 +#define RTC_CLOCK_DATE 0x4 +#define RTC_CLOCK_MONTH_CENTURY 0x5 +#define RTC_CLOCK_YEAR 0x6 +#define RTC_ALARM_SECONDS 0x7 +#define RTC_ALARM_MINUTES 0x8 +#define RTC_ALARM_HOUR 0x9 +#define RTC_ALARM_DAY_DATE 0xa +#define RTC_ALARM2_MINUTES 0xb +#define RTC_ALARM2_HOUR 0xc +#define RTC_ALARM2_DAY_DATE 0xd +#define RTC_CONTROL 0xe +#define RTC_STATUS 0xf +#define RTC_TRICKLE_CHARGE 0x10 + +#define FIRST_REG_OFF RTC_CLOCK_SECONDS +#define LAST_REG_OFF RTC_TRICKLE_CHARGE + + +/* RTC_CLOCK_SECONDS 0x0*/ + +#define RTC_CLOCK_SECONDS_SHF 0 +#define RTC_CLOCK_SECONDS_MSK (MSK(4)<seconds / 10; + single = time->seconds % 10; + tempValue = ((tens << RTC_CLOCK_10SECONDS_SHF )& RTC_CLOCK_10SECONDS_MSK )| + (( single << RTC_CLOCK_SECONDS_SHF)&RTC_CLOCK_SECONDS_MSK) ; + mvRtcCharWrite(RTC_CLOCK_SECONDS,tempValue); + + /* minutes */ + tens = time->minutes / 10; + single = time->minutes % 10; + tempValue = ((tens << RTC_CLOCK_10MINUTES_SHF )& RTC_CLOCK_10MINUTES_MSK )| + (( single << RTC_CLOCK_MINUTES_SHF)& RTC_CLOCK_MINUTES_MSK) ; + mvRtcCharWrite(RTC_CLOCK_MINUTES,tempValue); + + /* hours (24) */ + tens = time->hours / 10; + single = time->hours % 10; + tempValue = ((tens << RTC_CLOCK_10HOURS_SHF) & RTC_CLOCK_10HOURS_MSK2 )| + (( single << RTC_CLOCK_HOURS_SHF ) & RTC_CLOCK_HOURS_MSK); + mvRtcCharWrite(RTC_CLOCK_HOUR,tempValue); + + /* day */ + single = ++(time->day); + tempValue = ((single << RTC_CLOCK_DAY_SHF ) & RTC_CLOCK_DAY_MSK) ; + mvRtcCharWrite(RTC_CLOCK_DAY,tempValue); + + /* date */ + tens = time->date / 10; + single = time->date % 10; + tempValue = ((tens << RTC_CLOCK_10DATE_SHF ) & RTC_CLOCK_10DATE_MSK )| + ((single << RTC_CLOCK_DATE_SHF )& RTC_CLOCK_DATE_MSK) ; + + /* month */ + mvRtcCharWrite( RTC_CLOCK_DATE,tempValue); + tens = time->month / 10; + single = time->month % 10; + tempValue = ((tens << RTC_CLOCK_10MONTH_SHF ) & RTC_CLOCK_10MONTH_MSK )| + ((single << RTC_CLOCK_MONTH_SHF)& RTC_CLOCK_MONTH_MSK); + mvRtcCharWrite( RTC_CLOCK_MONTH_CENTURY,tempValue); + + /* year */ + tens = time->year / 10; + single = time->year % 10; + tempValue = ((tens << RTC_CLOCK_10YEAR_SHF) & RTC_CLOCK_10YEAR_MSK )| + ((single << RTC_CLOCK_YEAR_SHF) & RTC_CLOCK_YEAR_MSK); + mvRtcCharWrite(RTC_CLOCK_YEAR,tempValue); + + return; +} + +/******************************************************************************* +* mvRtcDS133xTimeGet - Read the time from the RTC. +* +* DESCRIPTION: +* This function reads the current time and date from the RTC into the +* structure RTC_TIME (defined in mvDS133x.h). +* +* INPUT: +* time - A pointer to a structure TIME (defined in mvDS133x.h). +* +* OUTPUT: +* The structure RTC_TIME is updated with the time read from the RTC. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvRtcDS133xTimeGet(MV_RTC_TIME* time) +{ + MV_U8 tempValue; + MV_U32 tens; + MV_U32 single; + + /* seconds */ + mvRtcCharRead(RTC_CLOCK_SECONDS,&tempValue); + tens = ( tempValue & RTC_CLOCK_10SECONDS_MSK) >> RTC_CLOCK_10SECONDS_SHF; + single = (tempValue & RTC_CLOCK_SECONDS_MSK) >> RTC_CLOCK_SECONDS_SHF ; + time->seconds = 10*tens + single; + + /* minutes */ + mvRtcCharRead(RTC_CLOCK_MINUTES,&tempValue); + tens = (tempValue & RTC_CLOCK_10MINUTES_MSK) >> RTC_CLOCK_10MINUTES_SHF; + single = (tempValue & RTC_CLOCK_MINUTES_MSK) >> RTC_CLOCK_MINUTES_SHF; + time->minutes = 10*tens + single; + + /* hours */ + mvRtcCharRead(RTC_CLOCK_HOUR,&tempValue); + tens = (tempValue & RTC_CLOCK_10HOURS_MSK2) >> RTC_CLOCK_10HOURS_SHF; + single = (tempValue & RTC_CLOCK_HOURS_MSK) >> RTC_CLOCK_HOURS_SHF; + time->hours = 10*tens + single; + + /* day */ + mvRtcCharRead(RTC_CLOCK_DAY,&tempValue); + time->day = (tempValue & RTC_CLOCK_DAY_MSK) >> RTC_CLOCK_DAY_SHF ; + time->day--; + + /* date */ + mvRtcCharRead(RTC_CLOCK_DATE,&tempValue); + tens = (tempValue & RTC_CLOCK_10DATE_MSK) >> RTC_CLOCK_10DATE_SHF; + single = (tempValue & RTC_CLOCK_DATE_MSK) >> RTC_CLOCK_DATE_SHF; + time->date = 10*tens + single; + + /* century/ month */ + mvRtcCharRead(RTC_CLOCK_MONTH_CENTURY,&tempValue); + tens = (tempValue & RTC_CLOCK_10MONTH_MSK) >> RTC_CLOCK_10MONTH_SHF; + single = (tempValue & RTC_CLOCK_MONTH_MSK) >> RTC_CLOCK_MONTH_SHF; + time->month = 10*tens + single; + time->century = (tempValue & RTC_CLOCK_CENTURY_MSK)>>RTC_CLOCK_CENTURY_SHF; + + /* year */ + mvRtcCharRead(RTC_CLOCK_YEAR,&tempValue); + tens = (tempValue & RTC_CLOCK_10YEAR_MSK) >> RTC_CLOCK_10YEAR_SHF; + single = (tempValue & RTC_CLOCK_YEAR_MSK) >> RTC_CLOCK_YEAR_SHF; + time->year = 10*tens + single; + + return; +} + +/******************************************************************************* +* mvRtcDS1339Init - Initialize the clock. +* +* DESCRIPTION: +* This function initialize the clock registers and read\write functions +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvRtcDS1339Init(MV_VOID) +{ + MV_U8 ucTemp; + + /* We will disable interrupts as default .*/ + mvRtcCharRead(RTC1339_CONTROL,&ucTemp); + ucTemp|=RTC_CONTROL_INTCN_BIT; + mvRtcCharWrite(RTC1339_CONTROL,ucTemp); + + /* disable trickle */ + mvRtcCharWrite(RTC_TRICKLE_CHARGE,0); + + return; +} + + +/******************************************************************************* +* mvRtcDS1338Init - Initialize the clock. +* +* DESCRIPTION: +* This function initialize the clock registers and read\write functions +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvRtcDS1338Init(MV_VOID) +{ + MV_U8 ucTemp; + + /* We will enable OSC .*/ + mvRtcCharRead(RTC_CLOCK_SECONDS,&ucTemp); + ucTemp &=~RTC_CONTROL_EOSC_MSK; + mvRtcCharWrite(RTC_CLOCK_SECONDS,ucTemp); + + return; +} + +/* assumption twsi is initialized !!! */ +/******************************************************************************* +* mvRtcCharRead - Read a char from the RTC. +* +* DESCRIPTION: +* This function reads a char from the RTC offset. +* +* INPUT: +* offset - offset +* +* OUTPUT: +* data - char read from offset offset. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID mvRtcCharRead(MV_U32 offset, MV_U8 *data) +{ + MV_TWSI_SLAVE twsiSlave; + + twsiSlave.slaveAddr.type = mvBoardRtcTwsiAddrTypeGet(); + twsiSlave.slaveAddr.address = mvBoardRtcTwsiAddrGet(); + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = offset; + twsiSlave.moreThen256 = MV_FALSE; + mvTwsiRead (RTC_I2C_CH, &twsiSlave, data, 1); + + return; +} + +/******************************************************************************* +* mvRtcCharWrite - Write a char from the RTC. +* +* DESCRIPTION: +* This function writes a char to the RTC offset. +* +* INPUT: +* offset - offset +* +* OUTPUT: +* data - char write to addr address. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID mvRtcCharWrite(MV_U32 offset, MV_U8 data) +{ + MV_TWSI_SLAVE twsiSlave; + + twsiSlave.slaveAddr.type = mvBoardRtcTwsiAddrTypeGet(); + twsiSlave.slaveAddr.address = mvBoardRtcTwsiAddrGet(); + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = offset; + twsiSlave.moreThen256 = MV_FALSE; + mvTwsiWrite (RTC_I2C_CH, &twsiSlave, &data, 1); + + return; +} diff --git a/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS133x.h b/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS133x.h new file mode 100644 index 0000000..e73f310 --- /dev/null +++ b/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS133x.h @@ -0,0 +1,100 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDS133xh +#define __INCmvDS133xh + +#include "mvTypes.h" +#include "twsi/mvTwsi.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvSpec.h" + +/*******************************************************************************/ +/* Support: DS1338 and DS1339 */ +/*******************************************************************************/ +typedef struct time +{ + MV_U8 seconds; + MV_U8 minutes; + MV_U8 hours; + MV_U8 day; + MV_U8 date; + MV_U8 month; + MV_U8 century; + MV_U8 year; +} MV_RTC_TIME; + +MV_VOID mvRtcDS1339Init(MV_VOID); +MV_VOID mvRtcDS1338Init(MV_VOID); + +MV_VOID mvRtcDS133xTimeSet(MV_RTC_TIME* time); + +MV_VOID mvRtcDS133xTimeGet(MV_RTC_TIME* time); + +MV_VOID mvRtcDS133xAlarmSet(MV_RTC_TIME* time); + + +#endif /* __INCmvDS133xh */ + diff --git a/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS133xReg.h b/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS133xReg.h new file mode 100644 index 0000000..59b6251 --- /dev/null +++ b/board/mv_feroceon/mv_hal/rtc/ext_rtc/mvDS133xReg.h @@ -0,0 +1,369 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDS133xRegh +#define __INCmvDS133xRegh + +#ifndef MSK +#define MSK(n) ((1 << (n)) - 1) +#endif + +#define RTC_CLOCK_SECONDS 0x0 +#define RTC_CLOCK_MINUTES 0x1 +#define RTC_CLOCK_HOUR 0x2 +#define RTC_CLOCK_DAY 0x3 +#define RTC_CLOCK_DATE 0x4 +#define RTC_CLOCK_MONTH_CENTURY 0x5 +#define RTC_CLOCK_YEAR 0x6 +#define RTC_ALARM_SECONDS 0x7 +#define RTC_ALARM_MINUTES 0x8 +#define RTC_ALARM_HOUR 0x9 +#define RTC_ALARM_DAY_DATE 0xa +#define RTC_ALARM2_MINUTES 0xb +#define RTC_ALARM2_HOUR 0xc +#define RTC_ALARM2_DAY_DATE 0xd +#define RTC1339_CONTROL 0xe +#define RTC1338_CONTROL 0x7 +#define RTC_STATUS 0xf +#define RTC_TRICKLE_CHARGE 0x10 + +#define FIRST_REG_OFF RTC_CLOCK_SECONDS +#define LAST_REG_OFF RTC_TRICKLE_CHARGE + + +/* RTC_CLOCK_SECONDS 0x0*/ + +#define RTC_CLOCK_SECONDS_SHF 0 +#define RTC_CLOCK_SECONDS_MSK (MSK(4)<seconds / 10; + single = mvTime->seconds % 10; + timeVal |= ((tens << RTC_TIME_10SECONDS_SHF) & RTC_TIME_10SECONDS_MSK) | + (( single << RTC_TIME_SECONDS_SHF) & RTC_TIME_SECONDS_MSK); + + /* minutes */ + tens = mvTime->minutes / 10; + single = mvTime->minutes % 10; + timeVal |= ((tens << RTC_TIME_10MINUTES_SHF) & RTC_TIME_10MINUTES_MSK) | + (( single << RTC_TIME_MINUTES_SHF) & RTC_TIME_MINUTES_MSK); + + /* hours (24) */ + tens = mvTime->hours / 10; + single = mvTime->hours % 10; + timeVal |= ((tens << RTC_TIME_10HOUR_SHF) & RTC_TIME_10HOUR_MSK) | + (( single << RTC_TIME_HOUR_SHF) & RTC_TIME_HOUR_MSK); + + /* day */ + single = ++(mvTime->day); + timeVal |= ((single << RTC_TIME_DAY_SHF ) & RTC_TIME_DAY_MSK); + + /* Update RTC Time Register */ + MV_REG_WRITE(RTC_TIME_REG, timeVal); + + /* date */ + tens = mvTime->date / 10; + single = mvTime->date % 10; + dateVal = ((tens << RTC_DATE_10DAY_SHF) & RTC_DATE_10DAY_MSK) | + (( single << RTC_DATE_DAY_SHF) & RTC_DATE_DAY_MSK); + + /* month */ + tens = mvTime->month / 10; + single = mvTime->month % 10; + dateVal |= ((tens << RTC_DATE_10MONTH_SHF) & RTC_DATE_10MONTH_MSK) | + (( single << RTC_DATE_MONTH_SHF) & RTC_DATE_MONTH_MSK); + + /* year */ + tens = mvTime->year / 10; + single = mvTime->year % 10; + dateVal |= ((tens << RTC_DATE_10YEAR_SHF) & RTC_DATE_10YEAR_MSK) | + (( single << RTC_DATE_YEAR_SHF) & RTC_DATE_YEAR_MSK); + + /* Update RTC Date Register */ + MV_REG_WRITE(RTC_DATE_REG, dateVal); + + + return; +} + +/******************************************************************************* +* mvRtcTimeGet - Read the time from the RTC. +* +* DESCRIPTION: +* This function reads the current time and date from the RTC into the +* structure RTC_TIME (defined in mv.h). +* +* INPUT: +* time - A pointer to a structure TIME (defined in mv.h). +* +* OUTPUT: +* The structure RTC_TIME is updated with the time read from the RTC. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvRtcTimeGet(MV_RTC_TIME* mvTime) +{ + MV_U32 timeVal; + MV_U32 dateVal; + MV_U8 tens; + MV_U8 single; + + /* read Time register */ + timeVal = MV_REG_READ(RTC_TIME_REG); + + /* seconds */ + tens = ((timeVal & RTC_TIME_10SECONDS_MSK) >> RTC_TIME_10SECONDS_SHF); + single = ((timeVal & RTC_TIME_SECONDS_MSK) >> RTC_TIME_SECONDS_SHF); + mvTime->seconds = 10*tens + single; + + /* minutes */ + tens = ((timeVal & RTC_TIME_10MINUTES_MSK) >> RTC_TIME_10MINUTES_SHF); + single = ((timeVal & RTC_TIME_MINUTES_MSK) >> RTC_TIME_MINUTES_SHF); + mvTime->minutes = 10*tens + single; + + /* hours */ + tens = ((timeVal & RTC_TIME_10HOUR_MSK) >> RTC_TIME_10HOUR_SHF); + single = ((timeVal & RTC_TIME_HOUR_MSK) >> RTC_TIME_HOUR_SHF); + mvTime->hours = 10*tens + single; + + /* day */ + mvTime->day = ((timeVal & RTC_TIME_DAY_MSK) >> RTC_TIME_DAY_SHF); + mvTime->day--; + + /* read Date register */ + dateVal = MV_REG_READ(RTC_DATE_REG); + + /* day */ + tens = ((dateVal & RTC_DATE_10DAY_MSK) >> RTC_DATE_10DAY_SHF); + single = ((dateVal & RTC_DATE_DAY_MSK) >> RTC_DATE_DAY_SHF); + mvTime->date = 10*tens + single; + + /* month */ + tens = ((dateVal & RTC_DATE_10MONTH_MSK) >> RTC_DATE_10MONTH_SHF); + single = ((dateVal & RTC_DATE_MONTH_MSK) >> RTC_DATE_MONTH_SHF); + mvTime->month = 10*tens + single; + + /* year */ + tens = ((dateVal & RTC_DATE_10YEAR_MSK) >> RTC_DATE_10YEAR_SHF); + single = ((dateVal & RTC_DATE_YEAR_MSK) >> RTC_DATE_YEAR_SHF); + mvTime->year = 10*tens + single; + + return; +} + +/******************************************************************************* +* mvRtcInit - Initialize the clock. +* +* DESCRIPTION: +* This function initialize the RTC integrated unit. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvRtcInit(MV_VOID) +{ + return; +} + +#if defined(CONFIG_BUFFALO_PLATFORM) +MV_VOID mvRtcAlarmSet(MV_RTC_TIME* time) +{ + MV_U32 timeVal = 0; + MV_U32 dateVal = 0; + MV_U32 tens; + MV_U32 single; + + /* seconds */ + tens = time->seconds / 10; + single = time->seconds % 10; + timeVal |= ((tens << RTC_TIME_10SECONDS_SHF) & RTC_TIME_10SECONDS_MSK) | + (( single << RTC_TIME_SECONDS_SHF) & RTC_TIME_SECONDS_MSK); + + /* minutes */ + tens = time->minutes / 10; + single = time->minutes % 10; + timeVal |= ((tens << RTC_TIME_10MINUTES_SHF) & RTC_TIME_10MINUTES_MSK) | + (( single << RTC_TIME_MINUTES_SHF) & RTC_TIME_MINUTES_MSK); + + /* hours (24) */ + tens = time->hours / 10; + single = time->hours % 10; + timeVal |= ((tens << RTC_TIME_10HOUR_SHF) & RTC_TIME_10HOUR_MSK) | + (( single << RTC_TIME_HOUR_SHF) & RTC_TIME_HOUR_MSK); + + /* day */ + single = ++(time->day); + timeVal |= ((single << RTC_TIME_DAY_SHF ) & RTC_TIME_DAY_MSK); + + /* Update RTC Time Register */ + MV_REG_WRITE(RTC_ALARM_TIME_REG, timeVal); + + /* date */ + tens = time->date / 10; + single = time->date % 10; + dateVal = ((tens << RTC_DATE_10DAY_SHF) & RTC_DATE_10DAY_MSK) | + (( single << RTC_DATE_DAY_SHF) & RTC_DATE_DAY_MSK); + + /* month */ + tens = time->month / 10; + single = time->month % 10; + dateVal |= ((tens << RTC_DATE_10MONTH_SHF) & RTC_DATE_10MONTH_MSK) | + (( single << RTC_DATE_MONTH_SHF) & RTC_DATE_MONTH_MSK); + + /* year */ + tens = time->year / 10; + single = time->year % 10; + dateVal |= ((tens << RTC_DATE_10YEAR_SHF) & RTC_DATE_10YEAR_MSK) | + (( single << RTC_DATE_YEAR_SHF) & RTC_DATE_YEAR_MSK); + + /* Update RTC Date Register */ + MV_REG_WRITE(RTC_ALARM_DATE_REG, dateVal); + + + return; +} + + +MV_VOID mvRtcAlarmGet(MV_RTC_TIME* time) +{ + MV_U32 timeVal; + MV_U32 dateVal; + MV_U8 tens; + MV_U8 single; + + /* read Time register */ + timeVal = MV_REG_READ(RTC_ALARM_TIME_REG); + + /* seconds */ + tens = ((timeVal & RTC_TIME_10SECONDS_MSK) >> RTC_TIME_10SECONDS_SHF); + single = ((timeVal & RTC_TIME_SECONDS_MSK) >> RTC_TIME_SECONDS_SHF); + time->seconds = 10*tens + single; + + /* minutes */ + tens = ((timeVal & RTC_TIME_10MINUTES_MSK) >> RTC_TIME_10MINUTES_SHF); + single = ((timeVal & RTC_TIME_MINUTES_MSK) >> RTC_TIME_MINUTES_SHF); + time->minutes = 10*tens + single; + + /* hours */ + tens = ((timeVal & RTC_TIME_10HOUR_MSK) >> RTC_TIME_10HOUR_SHF); + single = ((timeVal & RTC_TIME_HOUR_MSK) >> RTC_TIME_HOUR_SHF); + time->hours = 10*tens + single; + + /* day */ + time->day = ((timeVal & RTC_TIME_DAY_MSK) >> RTC_TIME_DAY_SHF); + time->day--; + + /* read Date register */ + dateVal = MV_REG_READ(RTC_ALARM_DATE_REG); + + /* day */ + tens = ((dateVal & RTC_DATE_10DAY_MSK) >> RTC_DATE_10DAY_SHF); + single = ((dateVal & RTC_DATE_DAY_MSK) >> RTC_DATE_DAY_SHF); + time->date = 10*tens + single; + + /* month */ + tens = ((dateVal & RTC_DATE_10MONTH_MSK) >> RTC_DATE_10MONTH_SHF); + single = ((dateVal & RTC_DATE_MONTH_MSK) >> RTC_DATE_MONTH_SHF); + time->month = 10*tens + single; + + /* year */ + tens = ((dateVal & RTC_DATE_10YEAR_MSK) >> RTC_DATE_10YEAR_SHF); + single = ((dateVal & RTC_DATE_YEAR_MSK) >> RTC_DATE_YEAR_SHF); + time->year = 10*tens + single; + + return; +} + +MV_VOID bfSetMagicKey(MV_U32 key) +{ + printf("%s > Changed to 0x%02x from 0x%02x\n", __FUNCTION__, key, bfGetMagicKey()); + MV_REG_WRITE(RTC_ALARM_TIME_REG, key); +} + +MV_U32 bfGetMagicKey(MV_VOID) +{ + return MV_REG_READ(RTC_ALARM_TIME_REG); +} + +MV_BOOL +buffalo_IsStopAtUbootStatus(MV_VOID) +{ + printf("%s > MagicKey = 0x%02x\n", __FUNCTION__, bfGetMagicKey()); + + switch(bfGetMagicKey()) { + case MagicKeyReboot: + case MagicKeyRebootReachedHalt: + case MagicKeyUpsShutdown: + return MV_FALSE; + break; + case MagicKeyRebootUbootPassed: + case MagicKeyNormalState: + case MagicKeyHwPoff: + case MagicKeySwPoff: + case MagicKeySwPoffReachedHalt: + case MagicKeySwPoffUbootPassed: + case MagicKeyFwUpdating: + case MagicKeyUpsShutdownReachedHalt: + return MV_TRUE; + break; + } + return MV_TRUE; +} + +#endif // defined(CONFIG_BUFFALO_PLATFORM) diff --git a/board/mv_feroceon/mv_hal/rtc/integ_rtc/mvRtc.h b/board/mv_feroceon/mv_hal/rtc/integ_rtc/mvRtc.h new file mode 100644 index 0000000..10f6891 --- /dev/null +++ b/board/mv_feroceon/mv_hal/rtc/integ_rtc/mvRtc.h @@ -0,0 +1,110 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvRtch +#define __INCmvRtch + +#include "mvTypes.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +typedef struct time +{ + MV_U8 seconds; + MV_U8 minutes; + MV_U8 hours; + MV_U8 day; + MV_U8 date; + MV_U8 month; + MV_U8 century; + MV_U8 year; +} MV_RTC_TIME; + +MV_VOID mvRtcInit(MV_VOID); + +MV_VOID mvRtcTimeSet(MV_RTC_TIME* time); + +MV_VOID mvRtcTimeGet(MV_RTC_TIME* time); + +MV_VOID mvRtcAlarmSet(MV_RTC_TIME* time); +#if defined(CONFIG_BUFFALO_PLATFORM) +#define MagicKeyReboot 0x18 +#define MagicKeyRebootUbootPassed 0x3a +#define MagicKeyNormalState 0x71 +#define MagicKeyHwPoff 0x43 +#define MagicKeySwPoff 0x02 +#define MagicKeySwPoffUbootPassed 0x5c +#define MagicKeyFwUpdating 0x6f +#define MagicKeyRebootReachedHalt 0x2b +#define MagicKeySwPoffReachedHalt 0x7a +#define MagicKeyUpsShutdown 0x21 +#define MagicKeyUpsShutdownReachedHalt 0x32 + +MV_VOID mvRtcAlarmGet(MV_RTC_TIME* time); +MV_VOID bfSetMagicKey(MV_U32 key); +MV_U32 bfGetMagicKey(MV_VOID); +#endif + +#endif /* __INCmvRtch */ + diff --git a/board/mv_feroceon/mv_hal/rtc/integ_rtc/mvRtcReg.h b/board/mv_feroceon/mv_hal/rtc/integ_rtc/mvRtcReg.h new file mode 100644 index 0000000..3980a3b --- /dev/null +++ b/board/mv_feroceon/mv_hal/rtc/integ_rtc/mvRtcReg.h @@ -0,0 +1,122 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvRtcRegh +#define __INCmvRtcRegh + + +/* RTC Time Register */ +#define RTC_TIME_REG 0x10300 + +/* RTC Date Register */ +#define RTC_DATE_REG 0x10304 + +#if defined(CONFIG_BUFFALO_PLATFORM) +#define RTC_ALARM_TIME_REG 0x10308 +#define RTC_ALARM_DATE_REG 0x1030C +#endif + +/* RTC Time Bit Definitions */ +#define RTC_TIME_SECONDS_SHF 0 +#define RTC_TIME_SECONDS_MSK (0xF << RTC_TIME_SECONDS_SHF) +#define RTC_TIME_10SECONDS_SHF 4 +#define RTC_TIME_10SECONDS_MSK (0x7 << RTC_TIME_10SECONDS_SHF) + +#define RTC_TIME_MINUTES_SHF 8 +#define RTC_TIME_MINUTES_MSK (0xF << RTC_TIME_MINUTES_SHF) +#define RTC_TIME_10MINUTES_SHF 12 +#define RTC_TIME_10MINUTES_MSK (0x7 << RTC_TIME_10MINUTES_SHF) + +#define RTC_TIME_HOUR_SHF 16 +#define RTC_TIME_HOUR_MSK (0xF << RTC_TIME_HOUR_SHF) +#define RTC_TIME_10HOUR_SHF 20 +#define RTC_TIME_10HOUR_MSK (0x3 << RTC_TIME_10HOUR_SHF) + + +#define RTC_TIME_HOUR_FORMAT_SHF 22 +#define RTC_TIME_HOUR_FORMAT_12_MSK (1 << RTC_TIME_HOUR_FORMAT_SHF) +#define RTC_TIME_HOUR_FORMAT_24_MSK (0 << RTC_TIME_HOUR_FORMAT_SHF) + +#define RTC_TIME_DAY_SHF 24 +#define RTC_TIME_DAY_MSK (0x7 << RTC_TIME_DAY_SHF) + +/* RTC Date Bit Definitions */ +#define RTC_DATE_DAY_SHF 0 +#define RTC_DATE_DAY_MSK (0xF << RTC_DATE_DAY_SHF) +#define RTC_DATE_10DAY_SHF 4 +#define RTC_DATE_10DAY_MSK (0x3 << RTC_DATE_10DAY_SHF) + +#define RTC_DATE_MONTH_SHF 8 +#define RTC_DATE_MONTH_MSK (0xF << RTC_DATE_MONTH_SHF) +#define RTC_DATE_10MONTH_SHF 12 +#define RTC_DATE_10MONTH_MSK (0x1 << RTC_DATE_10MONTH_SHF) + +#define RTC_DATE_YEAR_SHF 16 +#define RTC_DATE_YEAR_MSK (0xF << RTC_DATE_YEAR_SHF) +#define RTC_DATE_10YEAR_SHF 20 +#define RTC_DATE_10YEAR_MSK (0xF << RTC_DATE_10YEAR_SHF) + +#endif /* __INCmvRtcRegh */ + diff --git a/board/mv_feroceon/mv_hal/rtc/mvCompVer.txt b/board/mv_feroceon/mv_hal/rtc/mvCompVer.txt new file mode 100644 index 0000000..c6e1229 --- /dev/null +++ b/board/mv_feroceon/mv_hal/rtc/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_2 +Unit HAL Version: 3.1.0 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/sata/CoreDriver/mvLog.c b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvLog.c new file mode 100644 index 0000000..8c9db03 --- /dev/null +++ b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvLog.c @@ -0,0 +1,194 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvLog - C File for implementation of the core driver logger +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* +*******************************************************************************/ +#include "mvOsS.h" + + +#if defined (MV_LOG_DEBUG) || defined (MV_LOG_ERROR) + +const char* mvLogMsgType[MV_MAX_MESSAGE_TYPE] = { + " (FATAL_ERROR) ", + " (ERROR) ", + " (DEBUG INIT) ", + " (DEBUG INTERRUPTS) ", + " (DEBUG SATA LINK) ", + " (DEBUG UDMA COMMAND) ", + " (DEBUG NON UDMA COMMAND) ", + " (DEBUG PM) ", + " (DEBUG) ", + " (INFO) ", +}; + +static MV_LOG_FILTER_HEADER mvLogInstance[MV_MAX_LOG_MODULES] = +{ + {MV_FALSE, 0, NULL}, + {MV_FALSE, 0, NULL}, + {MV_FALSE, 0, NULL}, + {MV_FALSE, 0, NULL}, + {MV_FALSE, 0, NULL}, + {MV_FALSE, 0, NULL}, + {MV_FALSE, 0, NULL}, + {MV_FALSE, 0, NULL}, +}; + +static char szMessageBuffer[1024]; + + +MV_BOOLEAN mvLogRegisterModule(MV_U8 moduleId, MV_U32 filterMask, const char* name) +{ + if (moduleId >= MV_MAX_LOG_MODULES) + { + return MV_FALSE; + } + if (mvLogInstance[moduleId].used == MV_TRUE) + { + return MV_FALSE; + } + if (name == NULL) + { + return MV_FALSE; + } + mvLogInstance[moduleId].filterMask = filterMask; + mvLogInstance[moduleId].name = name; + mvLogInstance[moduleId].used = MV_TRUE; + return MV_TRUE; +} + +MV_BOOLEAN mvLogSetModuleFilter(MV_U8 moduleId, MV_U32 filterMask) +{ + if (moduleId >= MV_MAX_LOG_MODULES) + { + return MV_FALSE; + } + if (mvLogInstance[moduleId].used == MV_FALSE) + { + return MV_FALSE; + } + mvLogInstance[moduleId].filterMask = filterMask; + return MV_TRUE; +} + + +MV_U32 mvLogGetModuleFilter(MV_U8 moduleId) +{ + if (moduleId >= MV_MAX_LOG_MODULES) + { + return 0; + } + if (mvLogInstance[moduleId].used == MV_FALSE) + { + return 0; + } + return mvLogInstance[moduleId].filterMask; +} + +void mvLogMsg(MV_U8 moduleId, MV_U32 type, const char* format, ...) +{ + int len; + va_list args; + + if (moduleId >= MV_MAX_LOG_MODULES) + { + return; + } + if ((moduleId != MV_RAW_MSG_ID) && + ((mvLogInstance[moduleId].used == MV_FALSE) || + ((mvLogInstance[moduleId].filterMask & type) == 0))) + { + return; + } + if ((moduleId != MV_RAW_MSG_ID) && (type & 0x1ff)) + { + MV_U8 msgType = 0; + /* find least significant 1*/ + while (msgType < MV_MAX_MESSAGE_TYPE) + { + if (type & ( 1 << msgType)) + { + break; + } + msgType++; + } + len = sprintf(szMessageBuffer, "%s%s", + mvLogInstance[moduleId].name, mvLogMsgType[msgType]); + } + else + { + len = 0; + } + va_start(args, format); + vsprintf(&szMessageBuffer[len], format, args); + va_end(args); + MV_LOG_PRINT("%s", szMessageBuffer); +} +#endif diff --git a/board/mv_feroceon/mv_hal/sata/CoreDriver/mvLog.h b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvLog.h new file mode 100644 index 0000000..e94806d --- /dev/null +++ b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvLog.h @@ -0,0 +1,187 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/******************************************************************************* +* mvLog.h - Header File for CORE driver logger +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* +*******************************************************************************/ +#ifndef __INCmvLogh +#define __INCmvLogh + +#ifdef __cplusplus +extern "C" /*{*/ +#endif /* __cplusplus */ + +#include "mvOsS.h" + +/*-------------H file-----------------------------*/ +#define MV_DEBUG_FATAL_ERROR 0x01 +#define MV_DEBUG_ERROR 0x02 +#define MV_DEBUG_INIT 0x04 +#define MV_DEBUG_INTERRUPTS 0x08 +#define MV_DEBUG_SATA_LINK 0x10 +#define MV_DEBUG_UDMA_COMMAND 0x20 +#define MV_DEBUG_NON_UDMA_COMMAND 0x40 +#define MV_DEBUG_PM 0x80 +#define MV_DEBUG 0x100 +#define MV_DEBUG_INFO 0x200 + +#define MV_DEBUG_ENABLE_ALL 0x3FF + +#define MV_MAX_LOG_MODULES 16 +#define MV_MAX_MESSAGE_TYPE 10 +#define MV_RAW_MSG_ID 0xF + +typedef struct +{ + MV_BOOLEAN used; + MV_U32 filterMask; + const char *name; + char *filters; +} MV_LOG_FILTER_HEADER; + + +#if defined (MV_LOG_DEBUG) || defined (MV_LOG_ERROR) + #define MV_LOGGER 1 + #if defined (WIN32) +ULONG +_cdecl +DbgPrint( + PCH Format, + ... + ); + #define MV_LOG_PRINT DbgPrint + #elif defined (LINUX) + #define MV_LOG_PRINT printk + #elif defined __DOS__ + #define MV_LOG_PRINT printf + #elif defined __UBOOT__ + #define MV_LOG_PRINT printf + #else + #define MV_LOG_PRINT printf + #endif + + +MV_BOOLEAN mvLogRegisterModule(MV_U8 moduleId, MV_U32 filterMask, const char* name); +MV_BOOLEAN mvLogSetModuleFilter(MV_U8 moduleId, MV_U32 filterMask); +MV_U32 mvLogGetModuleFilter(MV_U8 moduleId); +void mvLogMsg(MV_U8 moduleId, MV_U32 type, const char* format, ...); + +#else /*defined (MV_LOG_DEBUG) || defined (MV_LOG_ERROR)*/ + + #undef MV_LOGGER + + #if defined (WIN32) + #define MV_LOG_PRINT + #define mvLogRegisterModule + #define mvLogGetModuleFilter + #define mvLogRegisterAllModules + #define mvLogMsg + + #elif defined (MV_LINUX) + #define MV_LOG_PRINT(x...) + #define mvLogRegisterModule(x...) + #define mvLogSetModuleFilter(x...) + #define mvLogGetModuleFilter(x...) + #define mvLogRegisterAllModules(x...) + #define mvLogMsg(x...) + + #elif defined (MV_UBOOT) + #define MV_LOG_PRINT(x...) + #define mvLogRegisterModule(x...) + #define mvLogSetModuleFilter(x...) + #define mvLogGetModuleFilter(x...) + #define mvLogRegisterAllModules(x...) + #define mvLogMsg(x...) + + #elif defined (__DOS__) + #define MV_LOG_PRINT() + #define mvLogRegisterModule() + #define mvLogSetModuleFilter() + #define mvLogGetModuleFilter() + #define mvLogRegisterAllModules() + #define mvLogMsg() + + #else + #define MV_LOG_PRINT + #define mvLogRegisterModule + #define mvLogSetModuleFilter + #define mvLogGetModuleFilter + #define mvLogRegisterAllModules + #define mvLogMsg + #endif + +#endif /*!defined (MV_LOG_DEBUG) && !defined (MV_LOG_ERROR)*/ + +#ifdef __cplusplus + +/*}*/ +#endif /* __cplusplus */ + +#endif + diff --git a/board/mv_feroceon/mv_hal/sata/CoreDriver/mvOsS.h b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvOsS.h new file mode 100644 index 0000000..faa8963 --- /dev/null +++ b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvOsS.h @@ -0,0 +1,90 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvOsSh +#define __INCmvOsSh + +#include "mvSysHwConfig.h" +/* Includes */ +#include "mvOs.h" + +#if defined(MV_LINUX) + +#include "mvOsSata.h" + +#elif defined(MV_UBOOT) + +#include "mvOsSata.h" + +#elif defined(MV_VXWORKS) + +#include "mvOsSVxw.h" + +#elif defined(MV_NETBSD) + +#include "mvOsSata.h" + +#endif + +#endif /* __INCmvOsSh */ diff --git a/board/mv_feroceon/mv_hal/sata/CoreDriver/mvRegs.h b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvRegs.h new file mode 100644 index 0000000..4722636 --- /dev/null +++ b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvRegs.h @@ -0,0 +1,413 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/******************************************************************************* +* mvRegs.h - Header file that includes the regs addresses +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmvRegs +#define __INCmvRegs +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* General Definitions */ +#define MV_BIT0 0x00000001 +#define MV_BIT1 0x00000002 +#define MV_BIT2 0x00000004 +#define MV_BIT3 0x00000008 +#define MV_BIT4 0x00000010 +#define MV_BIT5 0x00000020 +#define MV_BIT6 0x00000040 +#define MV_BIT7 0x00000080 +#define MV_BIT8 0x00000100 +#define MV_BIT9 0x00000200 +#define MV_BIT10 0x00000400 +#define MV_BIT11 0x00000800 +#define MV_BIT12 0x00001000 +#define MV_BIT13 0x00002000 +#define MV_BIT14 0x00004000 +#define MV_BIT15 0x00008000 +#define MV_BIT16 0x00010000 +#define MV_BIT17 0x00020000 +#define MV_BIT18 0x00040000 +#define MV_BIT19 0x00080000 +#define MV_BIT20 0x00100000 +#define MV_BIT21 0x00200000 +#define MV_BIT22 0x00400000 +#define MV_BIT23 0x00800000 +#define MV_BIT24 0x01000000 +#define MV_BIT25 0x02000000 +#define MV_BIT26 0x04000000 +#define MV_BIT27 0x08000000 +#define MV_BIT28 0x10000000 +#define MV_BIT29 0x20000000 +#define MV_BIT30 0x40000000 +#define MV_BIT31 0x80000000 + + +#define MV_PCI_REGS_OFFSET 0x0 + +/* PCI registers */ + +#define MV_MAIN_INTERRUPT_CAUSE_REG_OFFSET 0x1d60 + +#define MV_MAIN_INTERRUPT_MASK_REG_OFFSET 0x1d64 +#define MV_MAIN_INTERRUPT_MASK_REG_ALL_BITS 0x7ffff +#define MV_MAIN_INTERRUPT_MASK_REG_PCIERR_BIT MV_BIT18 +#define MV_MAIN_INTERRUPT_HOST_SELF_INT_BIT MV_BIT23 + +#define MV_PCI_CONTROL_REG_OFFSET 0x1d68 +#define MV_PCI_CONTROL_REG_H2H_INT_BIT MV_BIT1 + +/* enable ports error, coalescing done and pci error*/ +#define MV_MAIN_INTERRUPT_MASK_ENABLE_ALL 0x6ab55 + +#define MV_PCI_DLL_STATUS_CONTROL_REG_OFFSET 0x1d20 +#define MV_PCI_COMMAND_REG_OFFSET 0xc00 +#define MV_PCI_COMMAND_REG_DEFAULT 0x0107E371 +#define MV_PCI_COMMAND_PCI_CONVENTIONAL_ONLY \ + (MV_BIT5|MV_BIT6|MV_BIT7|MV_BIT8|MV_BIT9|MV_BIT31) +#define MV_PCI_MWRITE_COMBINE_BIT MV_BIT4 +#define MV_PCI_MREAD_COMBINE_BIT MV_BIT5 + +#define MV_PCI_MODE_REG_OFFSET 0xd00 +#define MV_PCI_MODE_MASK 0x30 +#define MV_PCI_MODE_OFFSET 4 + +#define MV_PCI_DISCARD_TIMER_REG_OFFSET 0xd04 + +#define MV_PCI_MSI_TRIGGER_REG_OFFSET 0xc38 + +#define MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET 0xd2c + +#define MV_PCI_XBAR_IF_TIMEOUT_REG_OFFSET 0x1d04 + +#define MV_PCI_SERR_MASK_REG_OFFSET 0xc28 +#define MV_PCI_SERR_MASK_REG_ENABLE_ALL 0xd77fe6 + +#define MV_PCI_INTERRUPT_CAUSE_REG_OFFSET 0x1d58 + +#define MV_PCI_INTERRUPT_MASK_REG_OFFSET 0x1d5c + +#define MV_PCI_INTERRUPT_MASK_REG_ENABLE_ALL MV_PCI_SERR_MASK_REG_ENABLE_ALL + +#define MV_PCI_ERROR_LOW_ADDRESS_REG_OFFSET 0x1d40 + +#define MV_PCI_ERROR_HIGH_ADDRESS_REG_OFFSET 0x1d44 + +#define MV_PCI_ERROR_ATTRIBUTE_REG_OFFSET 0x1d48 + +#define MV_PCI_ERROR_COMMAND_REG_OFFSET 0x1d50 + +#define MV_PCI_MAIN_COMMAND_STATUS_REG_OFFSET 0xd30 /*Relevant for 60x1 only*/ +#define MV_PCI_MAIN_COMMAND_DIS_CORE_CLK_MASK MV_BIT0 +#define MV_PCI_MAIN_COMMAND_DIS_SHC1_CLK_MASK MV_BIT0 +#define MV_PCI_MAIN_COMMAND_STOP_MASTER_MASK MV_BIT2 +#define MV_PCI_MAIN_COMMAND_MASTER_EMPTY_MASK MV_BIT3 +#define MV_PCI_MAIN_COMMAND_GLOBAL_RESET_MASK MV_BIT4 + +/*PEX (PCI-Express registers*/ +#define MV_PCI_E_INTERRUPT_CAUSE_REG_OFFSET 0x1900 +#define MV_PCI_E_INTERRUPT_MASK_REG_OFFSET 0x1910 +#define MV_PCI_E_ERROR_MASK_VALUE (MV_BIT10|MV_BIT9|MV_BIT8|MV_BIT3|MV_BIT1) +/* Flash interface registers */ +#define MV_FLASH_PARAMS_REG_OFFSET 0x1046c + +#define MV_FLASH_GPIO_PORT_CONTROL_OFFSET 0x104f0 + +#define MV_RESET_CONFIG_REG_OFFSET 0x180d8 +#define MV_RESET_CONFIG_TWSI_INIT_MASK MV_BIT0 +#define MV_SATA_II_ALL_PORTS_INT_COAL_CMND_THR_REG_OFFSET 0x180cc + +#define MV_SATA_II_ALL_PORTS_INT_COAL_TIME_THR_REG_OFFSET 0x180d0 + +#define MV_SATA_II_ALL_PORTS_INT_CAUSE_REG_OFFSET 0x18008 + +/* SATAHC registers*/ +#define MV_SATAHC_0_REGS_BASE_OFFSET 0x20000 /* 128KByte offset */ + +#define MV_SATAHC_1_REGS_BASE_OFFSET 0x30000 /* 192KByte offset */ + +#define MV_SATAHC_REGS_BASE_OFFSET(unit) ((unit)?(MV_SATAHC_1_REGS_BASE_OFFSET):(MV_SATAHC_0_REGS_BASE_OFFSET)) + +#define MV_SATAHC_XBAR_CONF_REG_OFFSET 0x000 + +#define MV_SATAHC_RESPONSE_Q_IN_POINTER_OFFSET 0x008 + +#define MV_SATAHC_INT_COAL_THRE_REG_OFFSET 0x00c + +#define MV_SATAHC_INT_TIME_THRE_REG_OFFSET 0x010 + +#define MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET 0x014 + +#define MV_SATA_I_HC_BRIDGES_TEST_CONTROL_REG_OFFSET 0x018 +#define MV_SATA_I_TEST_CONTROL_PATTERN_MASK 0x7 +#define MV_SATA_I_TEST_CONTROL_PATTERN_OFFSET 10 +#define MV_SATA_I_TEST_CONTROL_PORT_MASK 0x3 +#define MV_SATA_I_TEST_CONTROL_PORT_OFFSET 13 +#define MV_SATA_I_TEST_CONTROL_PHY_SHUTDOWN_MASK(port) ((MV_U32)1 << (24 + (port))) + +#define MV_SATA_I_HC_BRIDGES_TEST_STATUS_REG_OFFSET 0x01c +#define MV_SATA_I_TEST_STATUS_LOOPBACK_PASS_BIT MV_BIT8 + +#define MV_SATA_I_HC_BRIDGES_PINS_CONFIG_REG_OFFSET 0x020 + +#define MV_SATA_I_HC_R00_STATUS_BRIDGE_PORT_OFFSET(port) \ + (0x100 + (port)*0x100) + +#define MV_SATA_I_HC_R00_STATUS_BRIDGE_DET_OFFSET 0x0 +#define MV_SATA_I_HC_R00_STATUS_BRIDGE_DET_MASK 0xf + +#define MV_SATA_I_HC_R02_STATUS_BRIDGE_PORT_OFFSET(port) \ + (0x108 + (port)*0x100) + +#define MV_SATA_I_HC_PHY_CONTROL_BRIDGE_PORT_OFFSET(port) \ + (0x10C + (port)*0x100) + +#define MV_SATA_I_HC_R04_STATUS_BRIDGE_PORT_OFFSET(port) \ + (0x110 + (port)*0x100) +#define MV_SATA_I_HC_R05_STATUS_BRIDGE_PORT_OFFSET(port) \ + (0x114 + (port)*0x100) +#define MV_SATA_I_HC_R06_STATUS_BRIDGE_PORT_OFFSET(port) \ + (0x118 + (port)*0x100) +#define MV_SATA_I_HC_R0F_STATUS_BRIDGE_PORT_OFFSET(port) \ + (0x13c + (port)*0x100) +#define MV_SATA_I_HC_LT_MODES_PORT_REG_OFFSET(port) \ + (0x130 + ((port) * 0x100)) +#define MV_SATA_I_HC_PHY_MODE_BRIDGE_PORT_REG_OFFSET(port) \ + (0x174 + ((port) * 0x100)) +#define MV_SATA_I_PHY_MODE_AMP_MASK 0xe0 +#define MV_SATA_I_PHY_MODE_AMP_OFFSET 5 +#define MV_SATA_I_PHY_MODE_PRE_MASK 0x1800 +#define MV_SATA_I_PHY_MODE_PRE_OFFSET 11 + +#define MV_SATA_II_PHY_MODE_1_REG_OFFSET 0x32c + +#define MV_SATA_II_PHY_MODE_2_REG_OFFSET 0x330 +#define MV_SATA_II_PHY_MODE_2_AMP_MASK 0x700 +#define MV_SATA_II_PHY_MODE_2_AMP_OFFSET 8 +#define MV_SATA_II_PHY_MODE_2_PRE_MASK 0xe0 +#define MV_SATA_II_PHY_MODE_2_PRE_OFFSET 5 + +#define MV_SATA_II_PHY_MODE_3_REG_OFFSET 0x310 + +#define MV_SATA_II_PHY_MODE_4_REG_OFFSET 0x314 + +#define MV_SATA_II_IF_CONTROL_REG_OFFSET 0x344 +#define MV_SATA_II_IF_CONTROL_PMTX_OFFSET 0 +#define MV_SATA_II_IF_CONTROL_PMTX_MASK 0xf + +#define MV_SATA_II_IF_TEST_CTRL_REG_OFFSET 0x348 + +#define MV_SATA_II_IF_STATUS_REG_OFFSET 0x34c +#define MV_SATA_II_IF_STATUS_VUQ_DONE_MASK MV_BIT12 +#define MV_SATA_II_IF_STATUS_VUQ_ERR_MASK MV_BIT13 +#define MV_SATA_II_IF_STATUS_FSM_STATUS_MASK 0x3f000000 + + +#define MV_SATA_II_VENDOR_UQ_REG_OFFSET 0x35c + +#define MV_SATA_II_S_STATUS_REG_OFFSET 0x300 + +#define MV_SATA_II_S_ERROR_REG_OFFSET 0x304 + +#define MV_SATA_II_S_CONTROL_REG_OFFSET 0x308 + +#define MV_SATA_II_SATA_CONFIG_REG_OFFSET 0x50 + +#define MV_SATA_II_PHY_MODE_9_GEN1_REG_OFFSET 0x39c +#define MV_SATA_II_PHY_MODE_9_GEN2_REG_OFFSET 0x398 +/* EDMA registers */ + +#define MV_EDMA_PORT_BASE_OFFSET(port) ( 0x2000UL * ((port) + 1)) + +#define MV_EDMA_CONFIG_REG_OFFSET 0x000 +#define MV_EDMA_CONFIG_Q_DEPTH_MASK 0x1f +#define MV_EDMA_CONFIG_NATIVE_QUEUING_MASK MV_BIT5 /* Relevant for 60x1 */ +#define MV_EDMA_CONFIG_BURST_SIZE_MASK MV_BIT8 +#define MV_EDMA_CONFIG_EQUEUE_ENABLED_MASK MV_BIT9 +#define MV_EDMA_CONFIG_STOP_ON_ERROR_MASK MV_BIT10 +#define MV_EDMA_CONFIG_BURST_SIZE_EXT_MASK MV_BIT11 +#define MV_EDMA_CONFIG_CONONDEVERR_MASK MV_BIT14 + +#define MV_EDMA_TIMER_REG_OFFSET 0x004 + +#define MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET 0x008 + +#define MV_EDMA_INTERRUPT_ERROR_MASK_REG_OFFSET 0x00c + +/* unrecoverable EDMA errors*/ +#define MV_EDMA_GEN_I_UNRECOVERABLE_EDMA_ERROR 0x00001E6B +#define MV_EDMA_GEN_I_RECOVERABLE_EDMA_ERROR 0x00000000 +#define MV_EDMA_GEN_I_ERROR_MASK 0x00001118 + +#define MV_EDMA_GEN_II_UNRECOVERABLE_EDMA_ERROR 0xFC1E9E0B +#define MV_EDMA_GEN_II_RECOVERABLE_EDMA_ERROR 0x03E16020 +#define MV_EDMA_GEN_II_NORMAL_RCVRBL_EDMA_ERROR 0x02200000 + +/*don't enable rcvrbl errors that occur too often*/ +#define MV_EDMA_GEN_II_ERROR_MASK 0xFDDFF198 + + +#define MV_EDMA_REQUEST_Q_BAH_REG_OFFSET 0x010 + +#define MV_EDMA_REQUEST_Q_INP_REG_OFFSET 0x014 +#define MV_EDMA_REQUEST_Q_INP_MASK 0x000003e0 +#define MV_EDMA_REQUEST_Q_INP_OFFSET 5 +#define MV_EDMA_REQUEST_Q_BA_MASK 0xfffffc00 + +#define MV_EDMA_GEN2E_REQUEST_Q_INP_MASK 0x00000fe0 +#define MV_EDMA_GEN2E_REQUEST_Q_BA_MASK 0xfffff000 + +#define MV_EDMA_REQUEST_Q_OUTP_REG_OFFSET 0x018 +#define MV_EDMA_REQUEST_Q_OUTP_MASK 0x000003e0 + +#define MV_EDMA_RESPONSE_Q_BAH_REG_OFFSET 0x01c + +#define MV_EDMA_RESPONSE_Q_INP_REG_OFFSET 0x020 +#define MV_EDMA_RESPONSE_Q_INP_MASK 0x000000f8 + +#define MV_EDMA_RESPONSE_Q_OUTP_REG_OFFSET 0x024 +#define MV_EDMA_RESPONSE_Q_OUTP_MASK 0x000000f8 +#define MV_EDMA_RESPONSE_Q_OUTP_OFFSET 3 + +#define MV_EDMA_RESPONSE_Q_BA_MASK 0xffffff00 + + +#define MV_EDMA_COMMAND_REG_OFFSET 0x028 +#define MV_EDMA_COMMAND_ENABLE_MASK MV_BIT0 +#define MV_EDMA_COMMAND_DISABLE_MASK MV_BIT1 +#define MV_EDMA_COMMAND_HARD_RST_MASK MV_BIT2 + +#define MV_EDMA_TEST_CONTROL_REG_OFFSET 0x02c +#define MV_EDMA_LOOPBACK_MODE_BIT MV_BIT1 + +#define MV_EDMA_STATUS_REG_OFFSET 0x030 +#define MV_EDMA_STATUS_TAG_MASK 0x1f +#define MV_EDMA_STATUS_TAG_OFFSET 0 +#define MV_EDMA_STATUS_ECACHE_EMPTY_BIT MV_BIT6 +#define MV_EDMA_STATUS_EDMA_IDLE_BIT MV_BIT7 + + +#define MV_EDMA_IORDY_TIMEOUT_REG_OFFSET 0x034 + +#define MV_EDMA_ARBITER_CNFG_REG_OFFSET 0x038 +#define MV_EDMA_NO_SNOOP_BIT MV_BIT6 + +#define MV_EDMA_CMD_DELAY_THRE_REG_OFFSET 0x040 + +#define MV_EDMA_HALT_CONDITIONS_REG_OFFSET 0x060 + +#define MV_EDMA_TCQ_STATUS_REG_OFFSET 0x08c + +#define MV_EDMA_NCQTCQ0_OUTSTANDING_REG_OFFSET 0x094 +#define MV_EDMA_NCQTCQ1_OUTSTANDING_REG_OFFSET 0x098 +#define MV_EDMA_NCQTCQ2_OUTSTANDING_REG_OFFSET 0x09c +#define MV_EDMA_NCQTCQ3_OUTSTANDING_REG_OFFSET 0x0a0 + +#define MV_EDMA_FIS_CONFIGURATION_REG_OFFSET 0x360 +#define MV_EDMA_FIS_INTERRUPT_CAUSE_REG_OFFSET 0x364 +#define MV_EDMA_FIS_INTERRUPT_MASK_REG_OFFSET 0x368 +/* C2C */ +/* BM DMA */ +#define MV_BMDMA_COMMAND_OFFSET 0x224 +#define MV_BMDMA_STATUS_OFFSET 0x228 +#define MV_BMDMA_PRD_TABLE_LOW_ADDRESS_OFFSET 0x22c +#define MV_BMDMA_PRD_TABLE_HIGH_ADDRESS_OFFSET 0x230 + +/* storage device registers*/ + +#define MV_ATA_DEVICE_PIO_DATA_REG_OFFSET 0x100 +#define MV_ATA_DEVICE_FEATURES_REG_OFFSET 0x104 +#define MV_ATA_DEVICE_ERROR_REG_OFFSET MV_ATA_DEVICE_FEATURES_REG_OFFSET +#define MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET 0x108 +#define MV_ATA_DEVICE_LBA_LOW_REG_OFFSET 0x10c +#define MV_ATA_DEVICE_LBA_MID_REG_OFFSET 0x110 +#define MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET 0x114 +#define MV_ATA_DEVICE_HEAD_REG_OFFSET 0x118 +#define MV_ATA_DEVICE_COMMAND_REG_OFFSET 0x11c +#define MV_ATA_DEVICE_STATUS_REG_OFFSET MV_ATA_DEVICE_COMMAND_REG_OFFSET +#define MV_ATA_DEVICE_CONTROL_REG_OFFSET 0x120 +#define MV_ATA_DEVICE_ALTERNATE_REG_OFFSET MV_ATA_DEVICE_CONTROL_REG_OFFSET + +#define MV_IOG_TRANS_LOW_BIT (MV_BIT19) +#define MV_IOG_TRANS_HIGH_BIT (MV_BIT20) +#define MV_IOG_TRANS_INT_MASK (MV_IOG_TRANS_LOW_BIT | MV_IOG_TRANS_HIGH_BIT) +#define MV_IOG_TRANS_LOW_REG_OFFSET 0x18088 +#define MV_IOG_TRANS_HIGH_REG_OFFSET 0x1808C +#define MV_IOG_TRANS_CTRL_REG_OFFSET 0x18048 + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvRegs */ diff --git a/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSata.c b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSata.c new file mode 100644 index 0000000..a61f466 --- /dev/null +++ b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSata.c @@ -0,0 +1,10186 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/******************************************************************************* +* mvSata - C File for implementation of the core driver for Marvell's Sata +* Adapters. +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* mvOs.h +* mvSata.h. +* mvStorageDev.h +* mvRegs.h +* +*******************************************************************************/ +#include "mvOsS.h" +#include "mvSata.h" +#include "mvStorageDev.h" +#include "mvRegs.h" + +/* Defines */ +#define MV_SATA_PORT_PER_UNIT 4 + +#define MV_PHY_DET_STATE_NO_DEVICE 0 +#define MV_PHY_DET_STATE_DEVICE_NO_PHY_COM 1 +#define MV_PHY_DET_STATE_DEVICE_AND_PHY_COM 3 +#define MV_PHY_DET_STATE_PHY_OFFLINE 4 +#define MV_PHY_DET_CONTROL_START_NEGOTIATION 1 +#define MV_PHY_DET_CONTROL_SHUTDOWN 4 +#define MV_NEAR_END_LOOPBACK_TEST_WAIT_TIME 100 /* 100 uSec */ +#define MV_FAR_END_LOOPBACK_TEST_WAIT_TIME 5 /* 5 uSec */ +#define MV_PHY_COM_SETUP_WAIT 5000 /* 5 mili seconds */ +#define MV_HARD_RESET_WAIT_ASSERT 25 /* 25 uSec */ +#define MV_HARD_RESET_WAIT_NEGATE 1000 /* 1 mSec*/ +#define MV_HARD_RESET_WAIT_READY 2000 /* ms to wait after HR*/ +/* before disk access */ +#define MV_HARD_RESET_WAIT_FOR_BUSY_LOOPS 10000 +#define MV_HARD_RESET_WAIT_FOR_BUSY_LOOP_DELAY 1000 + +/* for the command result */ +#define MV_EDMA_REQUEST_COMMANDS_NUM 11 + + +/* Fix the watermark to the following default value */ +#define MV_WATER_MARK_FIX 29 /* write 5'b11101 to bits 12:8*/ + +extern MV_BOOLEAN waitWhileStorageDevIsBusy(MV_SATA_ADAPTER *pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 eDmaRegsOffset, MV_U32 loops, + MV_U32 delay); + +extern void dumpAtaDeviceRegisters(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, MV_BOOLEAN isEXT, + MV_STORAGE_DEVICE_REGISTERS *pRegisters); + +extern MV_BOOLEAN _doSoftReset(MV_SATA_CHANNEL *pSataChannel); + +MV_BOOLEAN isStorageDevReadyForPIO(MV_SATA_CHANNEL *pSataChannel); + +extern MV_BOOLEAN executeNonUDMACommand(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_NON_UDMA_PROTOCOL protocolType, + MV_BOOLEAN isEXT, + MV_U16_PTR bufPtr, MV_U32 count, + MV_U16 features, + MV_U16 sectorCount, + MV_U16 lbaLow, MV_U16 lbaMid, + MV_U16 lbaHigh, MV_U8 device, + MV_U8 command); + +extern MV_BOOLEAN waitForDRQ(MV_SATA_ADAPTER* pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 eDmaRegsOffset, MV_U32 loops, + MV_U32 delay); + +static void _setRegBits(MV_BUS_ADDR_T ioBaseAddr, MV_U32 offset, + MV_U32 bits) +{ + MV_U32 regVal = MV_REG_READ_DWORD(ioBaseAddr, offset); + regVal |= bits; + MV_REG_WRITE_DWORD(ioBaseAddr, offset, regVal); +} + +static void _clearRegBits(MV_BUS_ADDR_T ioBaseAddr, MV_U32 offset, + MV_U32 bits) +{ + MV_U32 regVal = MV_REG_READ_DWORD(ioBaseAddr, offset); + regVal &= ~bits; + MV_REG_WRITE_DWORD(ioBaseAddr, offset, regVal); +} + +static MV_U32 getRegField(MV_U32 regVal, MV_U32 fieldOff, MV_U32 bitsNum); + +static MV_BOOLEAN _checkSStatusAfterHReset(MV_SATA_ADAPTER* pAdapter, + MV_U8 channelIndex); +#ifdef MV_LOGGER + +void _dumpPCIRegs(MV_SATA_ADAPTER *pAdapter); +void _dumpEDMARegs(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); +void _dumpChannelQueues(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); +void _dumpSataRegs(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); +void _printATARegs(MV_STORAGE_DEVICE_REGISTERS *pDeviceRegs); + +#else + + #define _dumpPCIRegs(p) + #define _dumpEDMARegs(p,i) + #define _dumpChannelQueues(p,i) + #define _dumpSataRegs(p,i) + #define _printATARegs(p) + +#endif + +/* write ATA command register entry in a request entry */ +#define WRITE_ATA_COMMAND_REG(addr, data, reg, isLast) \ +do{ \ + *(addr) = MV_CPU_TO_LE16((((MV_U8)(data)) & 0xff) | ((reg) << 8) | (isLast)); \ +} while(0) + +#define MV_CHANNEL_INDEX(unit, port) (((unit) << 2) | (port)) + + +/* Typedefs */ + +typedef struct mvDmaRequestQueueEntry +{ + /* Fields set by CORE driver */ + volatile MV_U32 prdLowAddr; + volatile MV_U32 prdHighAddr; + volatile MV_U16 controlFlags; + volatile MV_U16 command[MV_EDMA_REQUEST_COMMANDS_NUM]; + +} MV_DMA_REQUEST_QUEUE_ENTRY; + +/*CRQP Data structure of the fourth generation devices*/ +typedef struct mvGen2EEdmaRequestQueueEntry +{ + /* Fields set by CORE driver */ + volatile MV_U32 prdLowAddr; + volatile MV_U32 prdHighAddr; + volatile MV_U32 controlFlags; + volatile MV_U16 dataRegionByteCount; + volatile MV_U16 reserved[2]; + volatile MV_U8 ATACommand; + volatile MV_U8 ATAFeatures; + volatile MV_U8 ATALBALow; + volatile MV_U8 ATALBAMid; + volatile MV_U8 ATALBAHigh; + volatile MV_U8 ATADevice; + volatile MV_U8 ATALBALowExp; + volatile MV_U8 ATALBAMidExp; + volatile MV_U8 ATALBAHighExp; + volatile MV_U8 ATAFeaturesExp; + volatile MV_U8 ATASectorCount; + volatile MV_U8 ATASectorCountExp; + volatile MV_U16 reserved2; +} MV_GEN2E_EDMA_REQUEST_QUEUE_ENTRY; + +typedef struct mvDmaResponseQueueEntry +{ + /* Fields set by hardware */ + volatile MV_U16 id; + volatile MV_U16 responseFlags; + volatile MV_U32 timeStamp; +} MV_DMA_RESPONSE_QUEUE_ENTRY; + + +/* local functions */ + +/*static*/ MV_BOOLEAN waitForBusyAfterHReset(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + +static void unmaskEdmaInterrupts(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +static void maskEdmaInterrupts(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +static void setupEdmaDeviceErrorHandlingConfiguration(MV_SATA_CHANNEL *pSataChannel); + +static void writeEdmaRequestEntry(MV_DMA_REQUEST_QUEUE_ENTRY *pReqEntry, + MV_SATA_CHANNEL *mvSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_UDMA_COMMAND_PARAMS *pUdmaParams); + +static void writeGen2EEdmaRequestEntry(MV_DMA_REQUEST_QUEUE_ENTRY *pReqEntry, + MV_SATA_CHANNEL *mvSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_UDMA_COMMAND_PARAMS *pUdmaParams); + +static void handleEdmaFailedCommand(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, MV_U16 eDmaErrorCause); + +static void handleEdmaResponse(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_DMA_RESPONSE_QUEUE_ENTRY *eDmaResponse); + +#ifdef MV_SATA_C2C_COMM +static void handleBmDMAInterrupt(MV_SATA_ADAPTER *pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_SATA_CHANNEL *pSataChannel, + MV_U8 channelIndex, + MV_U32 edmaError); +#endif + +static void handleEdmaInterrupt(MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit, + MV_U8 port, MV_U8 rspInPtr,MV_U32 responseDone, + MV_U32 edmaError, MV_U32 unitCause); + +static void handleDeviceInterrupt(MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit, + MV_U8 port); + +static void handleEdmaError(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +static MV_VOID handleDisconnect(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +static MV_VOID handleConnect(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +static MV_BOOLEAN handleUnrecoverableError(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 eDmaErrorCause); + +static MV_BOOLEAN handleRecoverableError(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 eDmaErrorCause); + +static MV_BOOLEAN handleAsyncNotify(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 eDmaErrorCause); + +static MV_BOOLEAN handleSelfDisable(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 eDmaErrorCause); + +static MV_BOOLEAN handleDevErr(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 eDmaErrorCause); + +#ifdef MV_SATA_C2C_COMM +static void handleC2CInterrupt(MV_SATA_CHANNEL *pSataChannel); +#endif +static MV_BOOLEAN sendVendorUniqueFIS(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 *vendorUniqueBuffer, + MV_U8 numOfDWords); + +static void handlePIOInterrupt(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry); + +static MV_BOOLEAN transferPIOData(MV_SATA_CHANNEL *pSataChannel, + MV_NONE_UDMA_COMMAND_PARAMS *pNoneUdmaCommandParams); + +#ifdef MV_SUPPORT_ATAPI +static MV_BOOLEAN transferPacketData(MV_SATA_CHANNEL *pSataChannel, + MV_PACKET_COMMAND_PARAMS *pPacketCommandParams, + MV_U16 byteCount); + +static void completePacketCommand(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_BOOLEAN failed); +#endif +static void completePIOCommand(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_BOOLEAN failed); + +static MV_BOOLEAN _resetEdmaQPointers(MV_SATA_CHANNEL *pSataChannel); + +static MV_BOOLEAN resetEdmaChannel(MV_SATA_CHANNEL *pSataChannel); + +static void flushDmaQueue(MV_SATA_CHANNEL *pSataChannel, + MV_FLUSH_TYPE flushType, MV_COMPLETION_TYPE, MV_U16); + +static void _fixPhyParams(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channelIndex); + +static void _channelHardReset(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +static void _establishSataComm(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +static void _establishSataCommAll(MV_SATA_ADAPTER *pAdapter); + +void _setActivePMPort(MV_SATA_CHANNEL *pSataChannel, MV_U8 PMPort); + +static void revertSataHCRegs (MV_SATA_ADAPTER *pAdapter); + +static void revertFlashInterfaceRegs (MV_SATA_ADAPTER *pAdapter); + +static void revertPCIInterfaceRegs (MV_SATA_ADAPTER *pAdapter); + +static void revertPEXInterfaceRegs (MV_SATA_ADAPTER *pAdapter); + +static void commandsQueueAddTail(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry); + +static void commandsQueueRemove(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry); + +static void addCommand(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_QUEUE_COMMAND_INFO *pCommandInfo); + +static void removeCommand(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry); + +static void enableSaDevInterrupts(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +void disableSaDevInterrupts(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +static void _checkATAStatus(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +static void activateEdma(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +static void deactivateEdma(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +static void EdmaReqQueueInsert(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_UDMA_COMMAND_PARAMS *pUdmaParams); + +static MV_BOOLEAN sendNoneUdmaCommand(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry); + +static MV_BOOLEAN isGoodCompletionsExpected(MV_SATA_CHANNEL *pSataChannel); + +static MV_VOID updatePortsWithErrors(MV_SATA_CHANNEL *pSataChannel); + +static MV_VOID setAbortedCommands(MV_SATA_CHANNEL *pSataChannel); + +static MV_VOID enterRequestSenseState(MV_SATA_CHANNEL *pSataChannel); + +static MV_BOOLEAN _getHostTagByDeviceTag(MV_SATA_CHANNEL *pSataChannel, + MV_U8 deviceTag, + MV_U8 PMPort, + MV_U8 *pHostTag); + +static MV_BOOLEAN parseReadLogExtOutPut(MV_SATA_CHANNEL *pSataChannel); + +static MV_BOOLEAN +ReadLogExtCompletionCB(MV_SATA_ADAPTER *pSataAdapter, + MV_U8 channelNum, + MV_COMPLETION_TYPE comp_type, + MV_VOID_PTR commandId, + MV_U16 responseFlags, + MV_U32 timeStamp, + MV_STORAGE_DEVICE_REGISTERS *registerStruct); + +static MV_VOID setReadLogExtCmndPointers(MV_SATA_CHANNEL *pSataChannel); + +static MV_VOID insertReadLogExtCmnd(MV_SATA_CHANNEL *pSataChannel); + +static MV_VOID handlePortError(MV_SATA_CHANNEL *pSataChannel); + +static MV_VOID softResetErringPorts(MV_SATA_CHANNEL *pSataChannel); + +static MV_VOID _insertQCommandsIntoEdma(MV_SATA_CHANNEL *pSataChannel); + +static MV_BOOLEAN _doDevErrorRecovery(MV_SATA_CHANNEL *pSataChannel); + +#if defined (MV_SUPPORT_ATAPI) || defined (MV_SATA_C2C_COMM) +static void activateBMDmaMode(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_U32 prdTableHi, MV_U32 prdTableLow, + MV_UDMA_TYPE dmaType); +#endif +static void _resetBmDma(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +#ifdef MV_SATA_C2C_COMM + +/* Channel 2 Channel */ +static MV_BOOLEAN sendVendorUniqueFIS(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 *vendorUniqueBuffer, + MV_U8 numOfDWords); + +#endif + +#ifdef MV_SATA_IO_GRANULARITY + +static void setIoGranularityCount(MV_SATA_ADAPTER *pAdapter, + MV_U8 transId, + MV_U8 counter); +static MV_U8 readIoGranularityCount(MV_SATA_ADAPTER *pAdapter, + MV_U8 transId); +static void iogInterrupt(MV_SATA_ADAPTER *pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 mainCause); +static void checkIogCompletion(MV_SATA_ADAPTER *pAdapter, + MV_U32 iogCause, MV_U8 offset); +static void checkIogBit(MV_SATA_ADAPTER *pAdapter, + MV_U8 bitOffset, + MV_U8 value); + +static MV_BOOLEAN iogReset(MV_SATA_ADAPTER *pAdapter); +#endif + + +/* Calculate the base address of the registers for a SATA channel */ +MV_U32 edmaRegOffst[MV_SATA_CHANNELS_NUM] = {0x22000, 0x24000, 0x26000, 0x28000, +0x32000, 0x34000, 0x36000, 0x38000}; + +#define getEdmaRegOffset(x) edmaRegOffst[(x)] + + + + +MV_BOOLEAN waitForBusyAfterHReset(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + MV_U32 i; + MV_U8 ATAstatus; + mvMicroSecondsDelay(pAdapter, MV_HARD_RESET_WAIT_READY); + for (i = MV_HARD_RESET_WAIT_READY; i < 5000000; i+= 10000) + { + ATAstatus = MV_REG_READ_BYTE(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if ((ATAstatus & MV_ATA_BUSY_STATUS) == 0) + { + return MV_TRUE; + } + mvMicroSecondsDelay(pAdapter, 10000); + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: in Channel " + "Hard Reset wait for busy, ATA STATUS=0x%02x\n", + pAdapter->adapterId, + channelIndex, ATAstatus); + return MV_FALSE; +} + +static void unmaskEdmaInterrupts(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + + + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + /*clear SError */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegOffst[ channelIndex] + + MV_SATA_II_S_ERROR_REG_OFFSET, 0xFFFFFFFF); + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_IIE) + { + /* clear FIS Interrupt cause register*/ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegOffst[ channelIndex] + + MV_EDMA_FIS_INTERRUPT_CAUSE_REG_OFFSET, 0); + } + } + + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET, + 0); + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + /* Unmask EDMA self disable (bit 8), mask errors that cause self disable */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_MASK_REG_OFFSET, + MV_EDMA_GEN_I_ERROR_MASK); + } + else + { + /* Unmask EDMA self disable (bit 7), mask errors that cause self disable */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_MASK_REG_OFFSET, + MV_EDMA_GEN_II_ERROR_MASK); + } +} + +static void maskEdmaInterrupts(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_MASK_REG_OFFSET, + 0); +} + +/******************************************************************************* +* writeEdmaRequestEntry - Write a CRQB (COMMAND REQUEST QUEUE BLOCK) +* +* DESCRIPTION: +* write one CRQB for an EDMA request queue. +* +* INPUT: +* pReqEntry - pointer to the CRQB area on the system memory +* (HW reqeust Queue). +* mvSataChannel - pointer to the channel data structure +* pCommandEntry - pointer to the command entry data structure +* (SW request Queue). +* +* RETURN: +* None +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static void writeEdmaRequestEntry(MV_DMA_REQUEST_QUEUE_ENTRY *pReqEntry, + MV_SATA_CHANNEL *mvSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_UDMA_COMMAND_PARAMS *pUdmaParams) +{ + MV_U16 ControlFlags = 0; + volatile MV_U16 *pCommand = &pReqEntry->command[0]; + MV_U8 ATACommand = 0; + + pReqEntry->prdLowAddr = MV_CPU_TO_LE32(pUdmaParams->prdLowAddr); + pReqEntry->prdHighAddr = MV_CPU_TO_LE32(pUdmaParams->prdHighAddr); + + /* Set the direction of the transaction (read/write) */ + if (pUdmaParams->readWrite == MV_UDMA_TYPE_READ) + { + ControlFlags |= 0x1; /* Device to system memory */ + } + ControlFlags |= (pCommandEntry->hostTag << 1); /* the tag will be used also */ +#ifdef MV_SATA_IO_GRANULARITY + + /*If valid IO Granularity transaction Id*/ + if (pUdmaParams->iogCurrentTransId < MV_IOG_INVALID_COMMAND_ID) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG | MV_DEBUG_UDMA_COMMAND, "%d %d: " + "Edma request with IO granularity Id = 0x%x\n", + mvSataChannel->mvSataAdapter->adapterId, + mvSataChannel->channelNumber, pUdmaParams->iogCurrentTransId); + ControlFlags |= (((MV_U16)pUdmaParams->iogCurrentTransId) << 6); + } +#endif + /* in Non-queue EDMA mode */ + ControlFlags |= (pCommandEntry->pCommandInfo->PMPort << 12); + + pReqEntry->controlFlags = MV_CPU_TO_LE16(ControlFlags); + + if ((mvSataChannel->queuedDMA == MV_EDMA_MODE_QUEUED) || + (mvSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING)) + { + if (pUdmaParams->isEXT == MV_TRUE) /* Read/Write DMA QUEUED EXT */ + { + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->numOfSectors & 0xFF00) >> 8, + MV_EDMA_ATA_FEATURES_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->numOfSectors) & 0xFF, + MV_EDMA_ATA_FEATURES_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pCommandEntry->deviceTag << 3) & 0xF8, + MV_EDMA_ATA_SECTOR_COUNT_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress & 0xFF000000) + >> 24, MV_EDMA_ATA_LBA_LOW_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress) & 0xFF, + MV_EDMA_ATA_LBA_LOW_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++,(pUdmaParams->highLBAAddress & + 0xFF), + MV_EDMA_ATA_LBA_MID_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress & 0xFF00) >> 8, + MV_EDMA_ATA_LBA_MID_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->highLBAAddress & 0xFF00) >> 8, + MV_EDMA_ATA_LBA_HIGH_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress & 0xFF0000) >> + 16, MV_EDMA_ATA_LBA_HIGH_ADDR, 0); + + if ((mvSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) && + (pUdmaParams->FUA == MV_TRUE)) + { + WRITE_ATA_COMMAND_REG(pCommand++, MV_BIT7 | MV_BIT6 , + MV_EDMA_ATA_DEVICE_ADDR,0); + } + else + { + WRITE_ATA_COMMAND_REG(pCommand++, MV_BIT6 , + MV_EDMA_ATA_DEVICE_ADDR,0); + } + + if (pUdmaParams->readWrite == MV_UDMA_TYPE_READ) + { + if (mvSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) + { + ATACommand = MV_ATA_COMMAND_READ_FPDMA_QUEUED_EXT; + } + else + { + ATACommand = MV_ATA_COMMAND_READ_DMA_QUEUED_EXT; + } + } + else + { + if (mvSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) + { + ATACommand = MV_ATA_COMMAND_WRITE_FPDMA_QUEUED_EXT; + } + else + { + ATACommand = MV_ATA_COMMAND_WRITE_DMA_QUEUED_EXT; + } + } + } + else /* Read/Write DMA QUEUED */ + { + WRITE_ATA_COMMAND_REG(pCommand++, (pUdmaParams->numOfSectors) & + 0xFF, MV_EDMA_ATA_FEATURES_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pCommandEntry->deviceTag << 3) & 0xF8, + MV_EDMA_ATA_SECTOR_COUNT_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress) & 0xFF, + MV_EDMA_ATA_LBA_LOW_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress & 0xFF00) >> 8, + MV_EDMA_ATA_LBA_MID_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress & 0xFF0000) + >> 16, MV_EDMA_ATA_LBA_HIGH_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, MV_BIT6 | + (MV_U8)((pUdmaParams->lowLBAAddress & 0xF000000) + >> 24), MV_EDMA_ATA_DEVICE_ADDR, 0); + + if (pUdmaParams->readWrite == MV_UDMA_TYPE_READ) + { + ATACommand = MV_ATA_COMMAND_READ_DMA_QUEUED; + } + else + { + ATACommand = MV_ATA_COMMAND_WRITE_DMA_QUEUED; + } + } + } + else + { + if (pUdmaParams->isEXT == MV_TRUE) + { /* READ/WRITE DMA EXT */ + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->numOfSectors & 0xFF00) >> 8, + MV_EDMA_ATA_SECTOR_COUNT_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->numOfSectors) & 0xFF, + MV_EDMA_ATA_SECTOR_COUNT_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress & 0xFF000000) + >> 24, + MV_EDMA_ATA_LBA_LOW_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress) &0xFF, + MV_EDMA_ATA_LBA_LOW_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->highLBAAddress & 0xFF), + MV_EDMA_ATA_LBA_MID_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress & 0xFF00) >> 8, + MV_EDMA_ATA_LBA_MID_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->highLBAAddress & 0xFF00) >> 8, + MV_EDMA_ATA_LBA_HIGH_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress & 0xFF0000) + >> 16, + MV_EDMA_ATA_LBA_HIGH_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, MV_BIT6, MV_EDMA_ATA_DEVICE_ADDR, + 0); + + if (pUdmaParams->readWrite == MV_UDMA_TYPE_READ) + { + ATACommand = MV_ATA_COMMAND_READ_DMA_EXT; + } + else + { + ATACommand = MV_ATA_COMMAND_WRITE_DMA_EXT; + } + } + else /* READ/WRITE DMA */ + { + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->numOfSectors) & 0xFF, + MV_EDMA_ATA_SECTOR_COUNT_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress) & 0xFF, + MV_EDMA_ATA_LBA_LOW_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress & 0xFF00) >> 8, + MV_EDMA_ATA_LBA_MID_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + (pUdmaParams->lowLBAAddress & 0xFF0000) + >> 16, + MV_EDMA_ATA_LBA_HIGH_ADDR, 0); + + WRITE_ATA_COMMAND_REG(pCommand++, + MV_BIT6 | (MV_U8)((pUdmaParams->lowLBAAddress & + 0xF000000) >> 24), + MV_EDMA_ATA_DEVICE_ADDR, 0); + + if (pUdmaParams->readWrite == MV_UDMA_TYPE_READ) + { + ATACommand = MV_ATA_COMMAND_READ_DMA; + } + else + { + ATACommand = MV_ATA_COMMAND_WRITE_DMA; + } + } + } + WRITE_ATA_COMMAND_REG(pCommand++, ATACommand, MV_EDMA_ATA_COMMAND_ADDR, + MV_BIT15); +} +/******************************************************************************* +* writeGen2EEdmaRequestEntry - Write a Gen2E CRQB (COMMAND REQUEST QUEUE BLOCK) +* +* DESCRIPTION: +* write one CRQB for an EDMA request queue. +* +* INPUT: +* pReqEntry - pointer to the CRQB area on the system memory +* (HW reqeust Queue). +* mvSataChannel - pointer to the channel data structure +* pCommandEntry - pointer to the command entry data structure +* (SW request Queue). +* pUdmaParams - pointer to the UDMA command parameters data structure. +* +* RETURN: +* None +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static void writeGen2EEdmaRequestEntry(MV_DMA_REQUEST_QUEUE_ENTRY *pReqEntry, + MV_SATA_CHANNEL *mvSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_UDMA_COMMAND_PARAMS *pUdmaParams) +{ + MV_GEN2E_EDMA_REQUEST_QUEUE_ENTRY *pGen2EReqEntry = (MV_GEN2E_EDMA_REQUEST_QUEUE_ENTRY *)pReqEntry; + MV_U32 ControlFlags = 0; + MV_U8 ATACommand = 0; + + pGen2EReqEntry->prdLowAddr = MV_CPU_TO_LE32(pUdmaParams->prdLowAddr); + pGen2EReqEntry->prdHighAddr = MV_CPU_TO_LE32(pUdmaParams->prdHighAddr); + + /* Set the direction of the transaction (read/write) */ + if (pUdmaParams->readWrite == MV_UDMA_TYPE_READ) + { + ControlFlags |= 0x1; /* Device to system memory */ + } +#ifdef MV_SATA_IO_GRANULARITY + + /*If valid IO Granularity transaction Id*/ + if (pUdmaParams->iogCurrentTransId < MV_IOG_INVALID_COMMAND_ID) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG | MV_DEBUG_UDMA_COMMAND, "%d %d: " + "Edma request with IO granularity Id = 0x%x\n", + mvSataChannel->mvSataAdapter->adapterId, + mvSataChannel->channelNumber, pUdmaParams->iogCurrentTransId); + ControlFlags |= (((MV_U16)pUdmaParams->iogCurrentTransId) << 6); + } +#endif + /* the tag will be used also in Non-queue EDMA mode */ + ControlFlags |= (pCommandEntry->deviceTag << 1); + ControlFlags |= (pCommandEntry->pCommandInfo->PMPort << 12); + ControlFlags |= (pCommandEntry->hostTag << 17); +#ifdef MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION + if (pUdmaParams->singleDataRegion == MV_TRUE) + { + ControlFlags |= MV_BIT16; + pGen2EReqEntry->dataRegionByteCount = MV_CPU_TO_LE16(pUdmaParams->byteCount); + } +#endif + + pGen2EReqEntry->controlFlags = MV_CPU_TO_LE32(ControlFlags); + if ((mvSataChannel->queuedDMA == MV_EDMA_MODE_QUEUED) || + (mvSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING)) + { + if (pUdmaParams->isEXT == MV_TRUE) /* Read/Write DMA QUEUED EXT */ + { + pGen2EReqEntry->ATAFeaturesExp = (MV_U8)((pUdmaParams->numOfSectors & 0xFF00) >> 8); + pGen2EReqEntry->ATAFeatures = (MV_U8)((pUdmaParams->numOfSectors) & 0xFF); + pGen2EReqEntry->ATASectorCount = (MV_U8)((pCommandEntry->deviceTag << 3) & 0xF8); + pGen2EReqEntry->ATALBALowExp = (MV_U8)((pUdmaParams->lowLBAAddress & 0xFF000000) >> 24); + pGen2EReqEntry->ATALBALow = (MV_U8)((pUdmaParams->lowLBAAddress) & 0xFF); + pGen2EReqEntry->ATALBAMidExp = (MV_U8)(pUdmaParams->highLBAAddress & 0xFF); + pGen2EReqEntry->ATALBAMid = (MV_U8)((pUdmaParams->lowLBAAddress & 0xFF00) >> 8); + pGen2EReqEntry->ATALBAHighExp = (MV_U8)((pUdmaParams->highLBAAddress & 0xFF00) >> 8); + pGen2EReqEntry->ATALBAHigh = (MV_U8)((pUdmaParams->lowLBAAddress & 0xFF0000) >> 16); + if ((mvSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) && + (pUdmaParams->FUA == MV_TRUE)) + { + pGen2EReqEntry->ATADevice = MV_BIT7 | MV_BIT6; + + } + else + { + pGen2EReqEntry->ATADevice = MV_BIT6; + + } + + if (pUdmaParams->readWrite == MV_UDMA_TYPE_READ) + { + if (mvSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) + { + ATACommand = MV_ATA_COMMAND_READ_FPDMA_QUEUED_EXT; + } + else + { + ATACommand = MV_ATA_COMMAND_READ_DMA_QUEUED_EXT; + } + } + else + { + if (mvSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) + { + ATACommand = MV_ATA_COMMAND_WRITE_FPDMA_QUEUED_EXT; + } + else + { + ATACommand = MV_ATA_COMMAND_WRITE_DMA_QUEUED_EXT; + } + } + } + else /* Read/Write DMA QUEUED */ + { + pGen2EReqEntry->ATAFeatures = (MV_U8)((pUdmaParams->numOfSectors) & 0xFF); + pGen2EReqEntry->ATASectorCount = (MV_U8)((pCommandEntry->deviceTag << 3) & 0xF8); + pGen2EReqEntry->ATALBALow = (MV_U8)((pUdmaParams->lowLBAAddress) & 0xFF); + pGen2EReqEntry->ATALBAMid = (MV_U8)((pUdmaParams->lowLBAAddress & 0xFF00) >> 8); + pGen2EReqEntry->ATALBAHigh = (MV_U8)((pUdmaParams->lowLBAAddress & 0xFF0000) >> 16); + pGen2EReqEntry->ATADevice = MV_BIT6 | + (MV_U8)((pUdmaParams->lowLBAAddress & 0xF000000) >> 24); + + if (pUdmaParams->readWrite == MV_UDMA_TYPE_READ) + { + ATACommand = MV_ATA_COMMAND_READ_DMA_QUEUED; + } + else + { + ATACommand = MV_ATA_COMMAND_WRITE_DMA_QUEUED; + } + } + } + else + { + if (pUdmaParams->isEXT == MV_TRUE) + { /* READ/WRITE DMA EXT */ + pGen2EReqEntry->ATASectorCountExp = (MV_U8)((pUdmaParams->numOfSectors & 0xFF00) >> 8); + pGen2EReqEntry->ATASectorCount = (MV_U8)((pUdmaParams->numOfSectors) & 0xFF); + pGen2EReqEntry->ATALBALowExp = (MV_U8)((pUdmaParams->lowLBAAddress & 0xFF000000) >> 24); + pGen2EReqEntry->ATALBALow = (MV_U8)((pUdmaParams->lowLBAAddress) & 0xFF); + pGen2EReqEntry->ATALBAMidExp = (MV_U8)(pUdmaParams->highLBAAddress & 0xFF); + pGen2EReqEntry->ATALBAMid = (MV_U8)((pUdmaParams->lowLBAAddress & 0xFF00) >> 8); + pGen2EReqEntry->ATALBAHighExp = (MV_U8)((pUdmaParams->highLBAAddress & 0xFF00) >> 8); + pGen2EReqEntry->ATALBAHigh = (MV_U8)((pUdmaParams->lowLBAAddress & 0xFF0000) >> 16); + pGen2EReqEntry->ATADevice = MV_BIT6; + + if (pUdmaParams->readWrite == MV_UDMA_TYPE_READ) + { + ATACommand = MV_ATA_COMMAND_READ_DMA_EXT; + } + else + { + ATACommand = MV_ATA_COMMAND_WRITE_DMA_EXT; + } + } + else /* READ/WRITE DMA */ + { + pGen2EReqEntry->ATASectorCount = (MV_U8)((pUdmaParams->numOfSectors) & 0xFF); + pGen2EReqEntry->ATALBALow = (MV_U8)((pUdmaParams->lowLBAAddress) & 0xFF); + pGen2EReqEntry->ATALBAMid = (MV_U8)((pUdmaParams->lowLBAAddress & 0xFF00) >> 8); + pGen2EReqEntry->ATALBAHigh = (MV_U8)((pUdmaParams->lowLBAAddress & 0xFF0000) >> 16); + pGen2EReqEntry->ATADevice = MV_BIT6 | + (MV_U8)((pUdmaParams->lowLBAAddress & 0xF000000) >> 24); + + if (pUdmaParams->readWrite == MV_UDMA_TYPE_READ) + { + ATACommand = MV_ATA_COMMAND_READ_DMA; + } + else + { + ATACommand = MV_ATA_COMMAND_WRITE_DMA; + } + } + } + pGen2EReqEntry->ATACommand = ATACommand; +} + +/******************************************************************************* +* handleEdmaFailedCommand - Handle failed EDMA command which didn't commpleted. +* +* DESCRIPTION: +* This function handles the completion of failed EDMA command when no +* response received for that command. +* +* INPUT: +* pAdapter - Pointer to the MV88SX50XX adapter data structure. +* channelIndex - The index of the channel where the response received. +* eDmaErrorCause - the value of the channel EDMA error cause register. +* +* RETURN: +* None +* +* COMMENTS: +* This function assumes that the channel semaphore is locked. +* +*******************************************************************************/ +static void handleEdmaFailedCommand(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, MV_U16 eDmaErrorCause) +{ + MV_QUEUED_COMMAND_ENTRY *pCommandEntry; + MV_UDMA_COMMAND_PARAMS *pUdmaCommandParams; + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + MV_STORAGE_DEVICE_REGISTERS deviceRegs; + MV_U32 eDmaStatus; + MV_U8 deviceTag = 0xFF; + MV_U8 hostTag; + MV_U8 PMPort = 0; + + if (pSataChannel->PMSupported == MV_TRUE) + { + MV_U32 regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_SATA_II_IF_STATUS_REG_OFFSET); + PMPort = (MV_U8)getRegField(regVal, 8, 4); + } + eDmaStatus = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_STATUS_REG_OFFSET); + + switch (pSataChannel->queuedDMA) + { + case MV_EDMA_MODE_QUEUED: + /* if only one command is queued*/ + if (pSataChannel->portQueuedCommands[PMPort] == 1) + { + MV_QUEUED_COMMAND_ENTRY *pEntry = pSataChannel->commandsQueueHead; + while (pEntry != NULL) + { + if (pEntry->isCommandInEdma == MV_TRUE) + { + if (pEntry->pCommandInfo->PMPort == PMPort) + { + deviceTag = pEntry->deviceTag; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d %d: handleEdmaFailedCommand, found " + "single erring command in TCQ mode " + "deviceTag(0x%02x)\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + PMPort, + deviceTag); + break; + } + } + else + { + /* stop once reached a command that has not been inserted into the + EDMA since the next commands also must be outside the EDMA + */ + break; + } + pEntry = pEntry->next; + } + if (deviceTag == 0xFF) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, + "%d %d %d: handleEdmaFailedCommand, failed to find " + "device tag of single erring command in TCQ mode\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + PMPort); + return; + } + } + else + { + /*multiple commands are queued, take the tag from the disk*/ + deviceTag = MV_REG_READ_BYTE(pAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET); + deviceTag >>= 3; + deviceTag &= 0x1F; + } + break; + case MV_EDMA_MODE_NOT_QUEUED: + deviceTag = (MV_U8)getRegField(eDmaStatus, 0, 5); + break; + default: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: " + "handleEdmaFailedCommand: called with wrong mode %d\n", + pAdapter->adapterId, + channelIndex, + pSataChannel->queuedDMA); + return; + } + + if (_getHostTagByDeviceTag(pSataChannel, + deviceTag, + PMPort, + &hostTag) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d %d: " + "handleEdmaFailedCommand: " + "Error - None Valid device tag (0x%02x)\n", + pAdapter->adapterId, + channelIndex, + PMPort, + deviceTag); + return; + } + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: Handle failed command," + "host tag 0x%02x, error cause 0x%02x (eStatus Tag 0x%02x)\n", + pAdapter->adapterId, channelIndex, hostTag, + eDmaErrorCause, (eDmaStatus & MV_EDMA_STATUS_TAG_MASK) >> + MV_EDMA_STATUS_TAG_OFFSET); + /* this function called only if FBS mode disable, then device tag equals to*/ + /* host tag*/ + pCommandEntry = &(pSataChannel->commandsQueue[hostTag]); + if (pCommandEntry->isFreeEntry == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, "%d %d %d:" + " Received response on a non-valid tag (0x%x)," + " device Tag (0x%x)\n", + pAdapter->adapterId, + channelIndex, + PMPort, + hostTag, + deviceTag); + + _dumpSataRegs(pAdapter,channelIndex); + dumpAtaDeviceRegisters(pAdapter, channelIndex, MV_TRUE, &deviceRegs); + _printATARegs(&deviceRegs); + return; + } + if (pSataChannel->PMSupported == MV_TRUE) + { + _setActivePMPort(pSataChannel, pCommandEntry->pCommandInfo->PMPort); + } + pUdmaCommandParams = &pCommandEntry->pCommandInfo->commandParams.udmaCommand; + dumpAtaDeviceRegisters(pAdapter, channelIndex, pUdmaCommandParams->isEXT, + &deviceRegs); + + pSataChannel->EdmaQueuedCommands--; + pUdmaCommandParams->callBack(pSataChannel->mvSataAdapter, channelIndex, + MV_COMPLETION_TYPE_ERROR, + pUdmaCommandParams->commandId, eDmaErrorCause, + 0, &deviceRegs); + removeCommand(pSataChannel,pCommandEntry); +} + +/******************************************************************************* +* handleEdmaResponse - Handle an EDMA response queue entry. +* +* DESCRIPTION: +* This function handles the completion of EDMA command when a response +* entry is received. +* +* INPUT: +* pAdapter - Pointer to the MV88SX50XX adapter data structure. +* channelIndex - The index of the channel where the response received. +* response - Pointer to the received EDMA response block structure. +* +* RETURN: +* None +* +* COMMENTS: +* This function assumes that the channel semaphore is locked. +* +*******************************************************************************/ +static void handleEdmaResponse(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_DMA_RESPONSE_QUEUE_ENTRY *eDmaResponse) +{ + MV_QUEUED_COMMAND_ENTRY *pCommandEntry; + MV_UDMA_COMMAND_PARAMS *pUdmaCommandParams; + MV_STORAGE_DEVICE_REGISTERS deviceRegs; + MV_COMPLETION_TYPE compType = MV_COMPLETION_TYPE_NORMAL; + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + MV_DMA_RESPONSE_QUEUE_ENTRY response; + MV_U16 eDmaCause = 0; + + response.id = MV_LE16_TO_CPU(eDmaResponse->id); + response.responseFlags = MV_LE16_TO_CPU(eDmaResponse->responseFlags); + response.timeStamp = MV_LE32_TO_CPU(eDmaResponse->timeStamp); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, "%d %d: New Response Received. ptr %p, " + "id 0x%02x, flags 0x%x ts 0x%08x\n", pAdapter->adapterId, + channelIndex, eDmaResponse, response.id, + response.responseFlags, response.timeStamp); + + eDmaCause = (response.responseFlags & 0xff); + pCommandEntry = &(pSataChannel->commandsQueue[response.id & pSataChannel->EDMAQueuePtrMask]); + if (response.responseFlags & 0xFF) + { + MV_BOOLEAN ignoreErrorInFlags = MV_FALSE; + + /* response with errors, ignore SErrors since they are recoverable*/ + if ((pAdapter->sataAdapterGeneration != MV_SATA_GEN_I) && + (response.responseFlags & MV_BIT5) && + ((response.responseFlags & 0xDF) == 0)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Ignore Serror in response flags\n", + pAdapter->adapterId, channelIndex); + ignoreErrorInFlags = MV_TRUE; + /* SError in EDMA error cause is masked. so we need to handle it here*/ + pSataChannel->recoveredErrorsCounter = 0; + handleRecoverableError(pAdapter, channelIndex, MV_BIT5); + /* clear SError bit in EDMA error cause*/ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET, + ~MV_BIT5); + + } + /* in NCQ mode, Device error doesn't halt the EDMA operation. since the*/ + /* response flags are a snapshot of the EDMA error cause, then this */ + /* error (Device error) is ignored */ + if ((pSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) && + (response.responseFlags & MV_BIT2) && + ((response.responseFlags & 0xDB) == 0)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Ignore Device Error in response flags.\n", + pAdapter->adapterId, channelIndex); + ignoreErrorInFlags = MV_TRUE; + } + + if ((pSataChannel->queuedDMA != MV_EDMA_MODE_NATIVE_QUEUING) && + (pSataChannel->FBSEnabled == MV_TRUE) && + (response.responseFlags & MV_BIT2) && + ((response.responseFlags & 0xDB) == 0)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Device Error in response flags in FBS none NCQ mode." + "outstanding commands %d \n", + pAdapter->adapterId, channelIndex, + pSataChannel->outstandingCommands); + ignoreErrorInFlags = MV_TRUE; + compType = MV_COMPLETION_TYPE_ERROR; + } + + if (ignoreErrorInFlags == MV_FALSE) + { + pSataChannel->queueCommandsEnabled = MV_FALSE; + pSataChannel->EdmaActive = MV_FALSE; + compType = MV_COMPLETION_TYPE_ERROR; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Response with Error. outstanding commands %d, " + "response flags 0x%x\n", + pAdapter->adapterId, channelIndex, + pSataChannel->outstandingCommands, response.responseFlags); + + /* + * link & phy layers unrecoverable errors may be the reason for a + * device errors, so we first check if any unrecoverable errors occured, + * except PCI/internal parity, if yes then we don't count this response + * the PCI/internal parity errors excluded since we want to complete + * the commands with error indication so higher layers can receive it + */ + { + MV_U32 edmaErrorCause = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET); + MV_U32 unrecoverableErrorMask; + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + unrecoverableErrorMask = MV_EDMA_GEN_I_UNRECOVERABLE_EDMA_ERROR; + } + else + { + unrecoverableErrorMask = MV_EDMA_GEN_II_UNRECOVERABLE_EDMA_ERROR; + } + unrecoverableErrorMask &= ~(MV_BIT1|MV_BIT0); + if (edmaErrorCause & unrecoverableErrorMask) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Response ignored due to unrecoverable error," + " EDMA Error Cause: 0x%08x\n", + pAdapter->adapterId, channelIndex, + edmaErrorCause); + return; + } + } + + /* + * responseFlags will hold the low 8 bit of the EDMA error cause + * regiter. For 88SX50XX set bit 8 sence each error causes to + * eDmaSelfDisable. + */ + eDmaCause = (response.responseFlags & 0xff); + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + eDmaCause |= MV_BIT8; + } + else + { + eDmaCause |= MV_BIT7; + } + if (pSataChannel->PMSupported == MV_TRUE) + { + _setActivePMPort(pSataChannel, pCommandEntry->pCommandInfo->PMPort); + } + } + } + pUdmaCommandParams = &pCommandEntry->pCommandInfo->commandParams.udmaCommand; + if (response.responseFlags & MV_BIT2) /*device error */ + { + if (pSataChannel->queuedDMA != MV_EDMA_MODE_NATIVE_QUEUING) + { + dumpAtaDeviceRegisters(pAdapter, channelIndex, MV_TRUE, &deviceRegs); + + if (pSataChannel->FBSEnabled == MV_TRUE) + { + if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED) + { + if (pSataChannel->ErrorHandlingInfo.state == MV_ERROR_HANDLING_STATE_IDLE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: First error\n", pAdapter->adapterId, + channelIndex); + pSataChannel->ErrorHandlingInfo.state = MV_ERROR_HANDLING_STATE_WAIT_FOR_COMPLETIONS; + } + /*let transport layer resume*/ + setAbortedCommands(pSataChannel); + } + else + { + /*in TCQ/FBS mode, ignore responses with device error*/ + return; + } + + } + } + } + + if (pCommandEntry->isFreeEntry == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, + "%d %d: Received response on a non-valid tag (%x), ts 0x%08x," + " address %p\n", pAdapter->adapterId, channelIndex, + response.id, response.timeStamp, eDmaResponse); + _dumpEDMARegs(pAdapter, channelIndex); + _dumpChannelQueues(pAdapter, channelIndex); + } + else + { + pSataChannel->EdmaQueuedCommands--; + + pUdmaCommandParams->callBack(pSataChannel->mvSataAdapter, channelIndex, + compType, pUdmaCommandParams->commandId, + eDmaCause, response.timeStamp, &deviceRegs); + removeCommand(pSataChannel,pCommandEntry); + + if (pSataChannel->queueCommandsEnabled == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_UDMA_COMMAND, + "%d %d: Commands queuing is disabled\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + return; + } + + if (pSataChannel->ErrorHandlingInfo.state != MV_ERROR_HANDLING_STATE_IDLE) + { + if (compType == MV_COMPLETION_TYPE_NORMAL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Commands with Tag 0x%x completed successfly\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, response.id & 0x1f); + } + if (pSataChannel->ErrorHandlingInfo.state == + MV_ERROR_HANDLING_STATE_WAIT_FOR_COMPLETIONS) + { + if (isGoodCompletionsExpected(pSataChannel) == MV_FALSE) + { + enterRequestSenseState(pSataChannel); + return; + } + } + } + if (pSataChannel->commandsQueueHead == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_UDMA_COMMAND, + "%d %d: Commands queue is empty\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + return; + } + if (pSataChannel->commandsQueueHead->pCommandInfo->type != + MV_QUEUED_COMMAND_TYPE_UDMA) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_UDMA_COMMAND, + "%d %d: Next Command isn't DMA\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + deactivateEdma(pAdapter,channelIndex); + if (pSataChannel->PMSupported == MV_TRUE) + { + _setActivePMPort(pSataChannel, + pSataChannel->commandsQueueHead->pCommandInfo->PMPort); + } + if (sendNoneUdmaCommand(pSataChannel, + pSataChannel->commandsQueueHead) == MV_FALSE) + { + completePIOCommand(pSataChannel, pSataChannel->commandsQueueHead, + MV_TRUE); + } + + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_UDMA_COMMAND, + "%d %d: Next Command is UDMA nothing to do\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + + } + } +} + + +#ifdef MV_SATA_C2C_COMM +/******************************************************************************* +* handleBmDmaInterrupt - handle DMA interrupt received for a given channel +* +* DESCRIPTION: +* This function is called when response interrupt is issued when C2C DMA +* completion event occurs. +* +* INPUT: +* pAdapter - pointer to the MV88SX50XX adapter data structure +* ioBaseAddr - adapter rbase address +* pSataChannel - SATA channel structure +* channelIndex - SATA channel index +* edmaError - if != zero then EDMA error happened. +* +* RETURN: +* None. +* +* COMMENTS: +* None +* +*******************************************************************************/ + +static void handleBmDMAInterrupt(MV_SATA_ADAPTER *pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_SATA_CHANNEL *pSataChannel, + MV_U8 channelIndex, + MV_U32 edmaError) +{ + MV_U32 val; + MV_U32 eDmaErrorCause = 0; + mvOsSemTake(&pSataChannel->semaphore); + /*Reset BM dma*/ + _clearRegBits(ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_BMDMA_COMMAND_OFFSET, MV_BIT0); + + MV_REG_WRITE_DWORD(ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_SATA_II_IF_CONTROL_REG_OFFSET, + 0); + if (edmaError) + { + eDmaErrorCause = (MV_U16)MV_REG_READ_DWORD(ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET); + } + mvOsSemRelease(&pSataChannel->semaphore); + if (pSataChannel->C2CCallback) + { + if (!edmaError) + { + pSataChannel->C2CCallback(pAdapter, + pSataChannel, + MV_C2C_BM_DMA_DONE, + 0, + NULL); + } + else + { + if (eDmaErrorCause & (MV_BIT17 | MV_BIT26)) + { + pSataChannel->C2CCallback(pAdapter, + pSataChannel, + MV_C2C_BM_DMA_ERROR, + 0, + NULL); + } + if (eDmaErrorCause & (MV_BIT13 | MV_BIT21)) + { + pSataChannel->C2CCallback(pAdapter, + pSataChannel, + MV_C2C_REGISTER_DEVICE_TO_HOST_FIS_ERROR, + 0, + NULL); + } + } + } +} +#endif + + +/******************************************************************************* +* handleEdmaInterrupt - handle EDMA interrupt receivd for a given channel +* +* DESCRIPTION: +* this function called when response interrupt issuesed for a channel and it +* handles all EDMA responses. +* +* INPUT: +* *pAdapter - pointer to the MV88SX50XX adapter data structure +* sataUnit - the SATAHC unit this channel belongs to +* port - the port number of the channel +* rspInPtr - the value of eRPQIP of the channel +* responseDone - if != zero then responses received on this channel +* edmaError - if != zero then EDMA error happened. +* +* RETURN: +* None. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +static void handleEdmaInterrupt(MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit, + MV_U8 port,MV_U8 rspInPtr, MV_U32 responseDone, + MV_U32 edmaError, MV_U32 unitCause) +{ + MV_U8 rspOutPtr; + MV_U8 channelIndex; + MV_BUS_ADDR_T ioBaseAddr = pAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset; + MV_SATA_CHANNEL *pSataChannel; + MV_BOOLEAN responseWithErr = MV_FALSE; + + channelIndex = MV_CHANNEL_INDEX(sataUnit, port); + pSataChannel = pAdapter->sataChannel[channelIndex]; + + if (responseDone && (pSataChannel != NULL))/* port Done*/ + { + mvOsSemTake(&pSataChannel->semaphore); + pSataChannel->recoveredErrorsCounter = 0; +#ifdef MV_SATA_C2C_COMM + if (MV_FALSE == pSataChannel->C2CmodeEnabled) + { +#endif +#ifdef MV_SUPPORT_ATAPI + if ((pSataChannel->commandsQueueHead) && (pSataChannel->commandsQueueHead->pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_PACKET)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + "%d %d: Basic DMA Interrupt\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + " BMDMA status 0x%08x\n", + MV_REG_READ_DWORD (ioBaseAddr, + getEdmaRegOffset(pSataChannel->channelNumber) + + MV_BMDMA_STATUS_OFFSET)); + if( pSataChannel->waitForBMDMA == MV_TRUE) + { + completePacketCommand(pSataChannel, pSataChannel->commandsQueueHead, MV_FALSE); + } + } + else + { +#endif + eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + rspOutPtr = pSataChannel->rspOutPtr; + rspInPtr &= pSataChannel->EDMAQueuePtrMask; + /* here we should update the response out pointer though we didn't*/ + /* handled the new responses, these response entries will not be */ + /* accessed again by the EDMA sinse the number of queued commands */ + /* (outstandingCommands) will be updated only after we handle each*/ + /* response entry */ + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_RESPONSE_Q_OUTP_REG_OFFSET, + pSataChannel->responseQueuePciLowAddress | + (rspInPtr << MV_EDMA_RESPONSE_Q_OUTP_OFFSET)); + + while (rspOutPtr != rspInPtr) + { + /*handleEdmaResponse may change the channel rspOutPtr due to */ + /*device error in NCQ mode or FBS*/ + pSataChannel->rspOutPtr = (rspOutPtr + 1) & pSataChannel->EDMAQueuePtrMask; + handleEdmaResponse(pAdapter, channelIndex, + &(pSataChannel->responseQueue[rspOutPtr])); + rspOutPtr++; + rspOutPtr &= pSataChannel->EDMAQueuePtrMask; + } +#ifdef MV_SUPPORT_ATAPI + } +#endif + /* + * Check if queueCommandsEnabled flag is disabled. + * If so, then an error has occured and auto flush must be triggered. + * Basically it is enough to trigger auto flush upon edmaError flag, + * but since edmaError is set before handleEdmaResponse is called + * there could be a racing condition between the time edmaError is checked + * and the response queue is checked. + * The racing condition is that an error does not occur when setting + * edmaError to MV_FALSE, but in handlEdmaResponse, the hardware + * has completed a command with error. + * The racing condition will complete the error command (through callback) + * but will prevent the auto flush of all outstanding commands. + */ + if (pSataChannel->queueCommandsEnabled == MV_FALSE) + { + responseWithErr = MV_TRUE; + } + mvOsSemRelease(&pSataChannel->semaphore); +#ifdef MV_SATA_C2C_COMM + } + else + { + mvOsSemRelease(&pSataChannel->semaphore); + handleBmDMAInterrupt(pAdapter, + ioBaseAddr, + pSataChannel, + channelIndex, + edmaError); + } +#endif + } + + if ((edmaError) || (responseWithErr == MV_TRUE)) /* EDMA error interrupt*/ + { + handleEdmaError(pAdapter,channelIndex ); + } +} + +static void handleEdmaError(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_U32 eDmaErrorCause = 0; + MV_BUS_ADDR_T ioBaseAddr = pAdapter->adapterIoBaseAddress; + + pSataChannel = pAdapter->sataChannel[channelIndex]; + + eDmaErrorCause = MV_REG_READ_DWORD(ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Edma Error Reg 0x%x\n", pAdapter->adapterId, + channelIndex, MV_REG_READ_DWORD(ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET)); + /* clear the channel's error cause register */ + MV_REG_WRITE_DWORD(ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET, + ~eDmaErrorCause); + /*if PM connected, connect/disconnect interrupts storm could happen*/ + if (MV_REG_READ_DWORD(ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET) & + (MV_BIT3 & MV_BIT4)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Edma Error Reg 0x%x still set!!!!!!!!\n", + pAdapter->adapterId, channelIndex, + MV_REG_READ_DWORD(ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET)); + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + /*wait 20ms till diconnect/connect interrupts finish*/ + mvMicroSecondsDelay(pAdapter, 20000); + eDmaErrorCause |= MV_REG_READ_DWORD(ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET); + MV_REG_WRITE_DWORD(ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET, + ~eDmaErrorCause); + } + } + /* dump in case any kind of parity error*/ + if (eDmaErrorCause & (MV_BIT11 | MV_BIT10 | MV_BIT9 | MV_BIT1 | MV_BIT0)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR," PARITY ERROR Detected\n"); + _dumpPCIRegs(pAdapter); + _dumpEDMARegs(pAdapter,channelIndex); + _dumpChannelQueues(pAdapter,channelIndex); + } + if (eDmaErrorCause & MV_BIT3) /*device disconneted*/ + { + handleDisconnect(pAdapter, channelIndex); + if (mvSataIsStorageDeviceConnected(pAdapter,channelIndex, NULL) == MV_FALSE) + { + pAdapter->mvSataEventNotify(pAdapter, + MV_EVENT_TYPE_SATA_CABLE, + MV_SATA_CABLE_EVENT_DISCONNECT, + channelIndex); + return; + } + } + if (eDmaErrorCause & MV_BIT4) /*device conneted*/ + { + handleConnect(pAdapter, channelIndex); + return; + } + /* unrecoverable error*/ + if (handleUnrecoverableError(pAdapter,channelIndex ,eDmaErrorCause ) == MV_TRUE) + { + return; + } + + /*PM hot plug*/ + if (handleAsyncNotify(pAdapter,channelIndex ,eDmaErrorCause ) == MV_TRUE) + { + return; + } + /* device errors in none NCQ mode generate self disable interrupt*/ + if (handleSelfDisable(pAdapter,channelIndex ,eDmaErrorCause ) == MV_TRUE) + { + return; + } + /* Neither device error without completion nor self disable must be in NCQ + * mode and Port multiplier connected + */ + if (handleDevErr(pAdapter,channelIndex ,eDmaErrorCause ) == MV_TRUE) + { + return; + } + /* recoverable error*/ + if (handleRecoverableError(pAdapter,channelIndex ,eDmaErrorCause) == MV_TRUE) + { + return; + } +} +static MV_VOID handleDisconnect(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + + if (pSataChannel) + { + mvOsSemTake(&pSataChannel->semaphore); + pSataChannel->queueCommandsEnabled = MV_FALSE; + pSataChannel->EdmaActive = MV_FALSE; + } + /* If disk is disconnected, then disable the activity LED */ + if (pAdapter->chipIs50XXB2 == MV_TRUE) + { + MV_U32 regVal1, regVal2; + /* First enable flash controller clocks*/ + regVal1 = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET); + + regVal1 |= (MV_BIT0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET, + regVal1); + regVal1 = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET); + /* Disable activity LEDs */ + regVal2 = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET); + regVal2 |= (MV_BIT8 << channelIndex); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET, + regVal2); + regVal2 = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET); + /* Disable flash controller clocks */ + regVal1 &= ~(MV_BIT0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET, + regVal1); + } + /* Fix for 88SX50XX FEr SATA#2 */ + if ((pAdapter->chipIs50XXB0 == MV_TRUE)|| + (pAdapter->chipIs50XXB2 == MV_TRUE)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_INTERRUPTS, + "%d %d: Before Hard RESET Main Cause %x\n", + pAdapter->adapterId, channelIndex, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainCauseOffset)); + /* Hard Reset the channel so we can do re-connect*/ + _channelHardReset(pAdapter, channelIndex); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_INTERRUPTS, + "%d %d: After Hard RESET Main Cause %x\n", + pAdapter->adapterId, channelIndex, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainCauseOffset)); + } + else + { + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + +#ifdef MV_SATA_C2C_COMM + if (pSataChannel->C2CmodeEnabled == MV_FALSE) + { +#endif + _channelHardReset(pAdapter, channelIndex); + _establishSataComm(pAdapter, channelIndex); +#ifdef MV_SATA_C2C_COMM + } +#endif + } + } + /* after calling mvSataNotify we can not be sure that the channel*/ + /* data structure is still available so first we release the */ + /* semaphore, after notifying the upper-layer with the disconnect*/ + /* event, nothing else is done with that channel */ + if (pSataChannel) + { + mvOsSemRelease(&pSataChannel->semaphore); + } + +} +static MV_VOID handleConnect(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + /* Fix for 88SX50xx FEr SATA#2 */ + if ((pAdapter->chipIs50XXB0 == MV_TRUE) || + (pAdapter->chipIs50XXB2 == MV_TRUE)) + { + _fixPhyParams(pAdapter, channelIndex);/*TBD*/ + /* The following link re-establishment is due to non */ + /* Marvell driven hard drives */ + _establishSataComm(pAdapter, channelIndex); + _establishSataComm(pAdapter, channelIndex); + } + + /* If disk is connected, then enable the activity LED */ + if (pAdapter->chipIs50XXB2 == MV_TRUE) + { + MV_U32 regVal1, regVal2; + /* First enable flash controller clocks*/ + regVal1 = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET); + + regVal1 |= (MV_BIT0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET, + regVal1); + regVal1 = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET); + /* Enable activity LEDs */ + regVal2 = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET); + regVal2 &= ~(MV_BIT8 << channelIndex); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET, + regVal2); + regVal2 = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET); + /* Disable flash controller clocks */ + regVal1 &= ~(MV_BIT0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET, + regVal1); + } + if (mvSataIsStorageDeviceConnected(pAdapter,channelIndex, NULL) == MV_TRUE) + { + pAdapter->mvSataEventNotify(pAdapter, MV_EVENT_TYPE_SATA_CABLE, + MV_SATA_CABLE_EVENT_CONNECT, + channelIndex); + } +} +static MV_BOOLEAN handleUnrecoverableError(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 eDmaErrorCause) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + + if (((pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) && + (eDmaErrorCause & MV_EDMA_GEN_I_UNRECOVERABLE_EDMA_ERROR)) || + ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && + (eDmaErrorCause & MV_EDMA_GEN_II_UNRECOVERABLE_EDMA_ERROR))) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: Unrecoverable" + " HW error detected.\n", pAdapter->adapterId, channelIndex); +#ifdef MV_LOGGER + if (eDmaErrorCause & MV_BIT0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: ePrtDataErr" + "UnrecoverableHW error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & MV_BIT1) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: ePrtPRDErr" + "UnrecoverableHW error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & MV_BIT3) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: eDevDis" + "UnrecoverableHW error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & MV_BIT9) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: ePrtCRQBErr" + "UnrecoverableHW error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & MV_BIT10) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: ePrtCRPBErr" + "UnrecoverableHW error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & MV_BIT11) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: ePrtIntErr" + "UnrecoverableHW error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & MV_BIT12) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: eIORdyErr" + "UnrecoverableHW error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & MV_BIT15) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: LinkCtlRxErr[2]" + "UnrecoverableHW error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & (MV_BIT17 | MV_BIT18 | MV_BIT19 | MV_BIT20)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: LinkDataRxErr" + "UnrecoverableHW error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & (MV_BIT26 | MV_BIT27 | MV_BIT28 | MV_BIT29 | MV_BIT30)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: LinkDataTxErr" + "UnrecoverableHW error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & MV_BIT31) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: TransProtErr" + "UnrecoverableHW error detected.\n", pAdapter->adapterId, channelIndex); + } +#endif + if (pSataChannel) + { + mvOsSemTake(&pSataChannel->semaphore); + pSataChannel->queueCommandsEnabled = MV_FALSE; + pSataChannel->EdmaActive = MV_FALSE; + deactivateEdma(pAdapter, channelIndex); + disableSaDevInterrupts(pAdapter, channelIndex); + flushDmaQueue (pSataChannel, MV_FLUSH_TYPE_CALLBACK, + MV_COMPLETION_TYPE_ABORT, (MV_U16)eDmaErrorCause); + resetEdmaChannel(pSataChannel); + mvOsSemRelease(&pSataChannel->semaphore); + } + if ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_IIE) || + (eDmaErrorCause & MV_BIT12) == 0) + { + _dumpSataRegs(pAdapter, channelIndex); + } + pAdapter->mvSataEventNotify(pAdapter, MV_EVENT_TYPE_SATA_ERROR, + MV_SATA_UNRECOVERABLE_COMMUNICATION_ERROR, + channelIndex); + return MV_TRUE; + } + return MV_FALSE; +} +static MV_BOOLEAN handleRecoverableError(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 eDmaErrorCause) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + + if (((pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) && + (eDmaErrorCause & MV_EDMA_GEN_I_RECOVERABLE_EDMA_ERROR)) || + ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && + (eDmaErrorCause & MV_EDMA_GEN_II_RECOVERABLE_EDMA_ERROR))) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: Recoverable" + " HW error detected.\n", pAdapter->adapterId, channelIndex); +#ifdef MV_LOGGER + if (eDmaErrorCause & MV_BIT5) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: SerrInt" + "Recoverable error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & (MV_BIT13 | MV_BIT14 | MV_BIT16)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: LinkCtlRxErr" + "Recoverable error detected.\n", pAdapter->adapterId, channelIndex); + } + if (eDmaErrorCause & (MV_BIT21 | MV_BIT22 | MV_BIT23 | MV_BIT24 | MV_BIT25)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: LinkCtlTxErr" + "Recoverable error detected.\n", pAdapter->adapterId, channelIndex); + } +#endif + _dumpSataRegs(pAdapter, channelIndex); + if ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && + (eDmaErrorCause & MV_BIT5)) + { + MV_U32 regVal; + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegOffst[ channelIndex] + + MV_SATA_II_S_ERROR_REG_OFFSET); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: Clear " + " Serror register(0x%02x).\n", pAdapter->adapterId, + channelIndex, regVal); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegOffst[ channelIndex] + + MV_SATA_II_S_ERROR_REG_OFFSET, regVal); + /* clear the channel's error cause register */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET, + ~MV_BIT5); + } + pAdapter->mvSataEventNotify(pAdapter, MV_EVENT_TYPE_SATA_ERROR, + MV_SATA_RECOVERABLE_COMMUNICATION_ERROR, + channelIndex); + if (pSataChannel) + { + mvOsSemTake(&pSataChannel->semaphore); + if (pSataChannel->recoveredErrorsCounter++ > 10) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Reached %d Recoverable errors " + "notify unrecoverable error\n", + pAdapter->adapterId, channelIndex, + pSataChannel->recoveredErrorsCounter); + pSataChannel->queueCommandsEnabled = MV_FALSE; + pSataChannel->EdmaActive = MV_FALSE; + deactivateEdma(pAdapter, channelIndex); + disableSaDevInterrupts(pAdapter, channelIndex); + flushDmaQueue (pSataChannel, MV_FLUSH_TYPE_CALLBACK, + MV_COMPLETION_TYPE_ABORT, (MV_U16)eDmaErrorCause); + resetEdmaChannel(pSataChannel); + mvOsSemRelease(&pSataChannel->semaphore); + pAdapter->mvSataEventNotify(pAdapter, MV_EVENT_TYPE_SATA_ERROR, + MV_SATA_UNRECOVERABLE_COMMUNICATION_ERROR, + channelIndex); + } + else + { + mvOsSemRelease(&pSataChannel->semaphore); + return MV_TRUE; + } + } + return MV_TRUE; + } + return MV_FALSE; +} + +static MV_BOOLEAN handleAsyncNotify(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 eDmaErrorCause) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + if ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && + (eDmaErrorCause & MV_BIT8)) + { + MV_U32 regVal1; + if (pSataChannel != NULL) + { + mvOsSemTake(&pSataChannel->semaphore); + } + regVal1 = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_SATA_II_IF_STATUS_REG_OFFSET); + /*Clear status*/ + if (regVal1 & (MV_BIT31 | MV_BIT30)) + { + MV_U32 regVal2 = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_SATA_II_IF_CONTROL_REG_OFFSET); + regVal2 |= MV_BIT24; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_SATA_II_IF_CONTROL_REG_OFFSET, regVal2); + } + if (pSataChannel != NULL) + { + mvOsSemRelease(&pSataChannel->semaphore); + } + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_IIE) + { + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: PM asynchronous notification interrupt. FIS Cause %x\n", + pAdapter->adapterId, channelIndex, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_EDMA_FIS_INTERRUPT_CAUSE_REG_OFFSET)); + + /* clear FIS Interrupt cause register*/ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_EDMA_FIS_INTERRUPT_CAUSE_REG_OFFSET, + ~0xA00); + /* clear the channel's error cause register */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET, + ~MV_BIT8); + } + if (((regVal1 & MV_BIT30) == 0) && + ((regVal1 & MV_BIT31) == MV_BIT31)) + { + + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_INTERRUPTS, + "%d %d: PM asynchronous notification interrupt.\n", + pAdapter->adapterId, channelIndex); + + pAdapter->mvSataEventNotify(pAdapter, MV_EVENT_TYPE_SATA_CABLE, + MV_SATA_CABLE_EVENT_PM_HOT_PLUG, + channelIndex); + } + return MV_TRUE; + } + return MV_FALSE; +} + +static MV_BOOLEAN handleSelfDisable(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 eDmaErrorCause) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + + if ((((pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) && (eDmaErrorCause & MV_BIT8)) || + ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && (eDmaErrorCause & MV_BIT7))) + && + (pSataChannel != NULL)) /* edma self disable */ + { + mvOsSemTake(&pSataChannel->semaphore); + if (pSataChannel->EdmaActive == MV_TRUE) + { + pSataChannel->queueCommandsEnabled = MV_FALSE; + pSataChannel->EdmaActive = MV_FALSE; + + if (eDmaErrorCause & MV_BIT2) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Edma Self disabled due to device error" + " without completion\n", pAdapter->adapterId, + channelIndex); + switch (pSataChannel->queuedDMA) + { + case MV_EDMA_MODE_NOT_QUEUED: + case MV_EDMA_MODE_QUEUED: + handleEdmaFailedCommand(pAdapter, channelIndex, + (MV_U16)eDmaErrorCause); + break; + case MV_EDMA_MODE_NATIVE_QUEUING: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, + "%d %d: Edma Self disabled due to device " + "error in NCQ mode!!!!\n", + pAdapter->adapterId, channelIndex); + + break; + default: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, + "%d %d: Unknown EDMA mode (%d)\n", + pAdapter->adapterId, channelIndex, + pSataChannel->queuedDMA); + break; + + } + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR | MV_DEBUG_INTERRUPTS, + "%d %d: Edma Self disable received without reason!!!\n", + pAdapter->adapterId, channelIndex); + + } + } + pAdapter->mvSataEventNotify(pAdapter, MV_EVENT_TYPE_SATA_ERROR, + MV_SATA_DEVICE_ERROR, channelIndex); + if (_doDevErrorRecovery(pSataChannel) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR | MV_DEBUG_INTERRUPTS, + "%d %d: Error Recovery Fails!!!\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_TRUE; + } + mvOsSemRelease(&pSataChannel->semaphore); + return MV_TRUE; + } + return MV_FALSE; +} +static MV_BOOLEAN handleDevErr(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 eDmaErrorCause) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + if ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && + (eDmaErrorCause & MV_BIT2) && (pSataChannel != NULL)) + { + mvOsSemTake(&pSataChannel->semaphore); + if (pSataChannel->EdmaActive == MV_TRUE) + { + if (pSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: EDMA device error in NCQ mode\n", + pAdapter->adapterId, channelIndex); + if (pSataChannel->ErrorHandlingInfo.state == MV_ERROR_HANDLING_STATE_IDLE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: First error\n", pAdapter->adapterId, + channelIndex); + pSataChannel->ErrorHandlingInfo.state = MV_ERROR_HANDLING_STATE_WAIT_FOR_COMPLETIONS; + } + + updatePortsWithErrors(pSataChannel); + setAbortedCommands(pSataChannel); + if (isGoodCompletionsExpected(pSataChannel) == MV_FALSE) + { + enterRequestSenseState(pSataChannel); + } + + } + else if (pSataChannel->FBSEnabled == MV_TRUE) + { + if (pSataChannel->queuedDMA == MV_EDMA_MODE_QUEUED) + { + if (pSataChannel->ErrorHandlingInfo.state == MV_ERROR_HANDLING_STATE_IDLE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: First error\n", pAdapter->adapterId, + channelIndex); + pSataChannel->ErrorHandlingInfo.state = MV_ERROR_HANDLING_STATE_WAIT_FOR_COMPLETIONS; + } + /*get the Device tag from the EDMA's internal memory then*/ + /*complete the failed command*/ + handleEdmaFailedCommand(pAdapter, channelIndex, MV_BIT2); + updatePortsWithErrors(pSataChannel); + setAbortedCommands(pSataChannel); + if (isGoodCompletionsExpected(pSataChannel) == MV_FALSE) + { + enterRequestSenseState(pSataChannel); + } + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: EDMA device error in FBS none NCQ mode\n", + pAdapter->adapterId, channelIndex); + } + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR | MV_DEBUG_INTERRUPTS, + "%d %d: EDMA device error must be handled" + "previously!!!\n", pAdapter->adapterId, + channelIndex); + } + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR | MV_DEBUG_INTERRUPTS, + "%d %d: EDMA device error while EDMA not active!!!\n", + pAdapter->adapterId, channelIndex); + } + pAdapter->mvSataEventNotify(pAdapter, MV_EVENT_TYPE_SATA_ERROR, + MV_SATA_DEVICE_ERROR, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_TRUE; + } + return MV_FALSE; +} +static MV_VOID handlePCIErrorInterrupt(MV_SATA_ADAPTER *pAdapter) +{ + MV_U32 errorCause = 0; + if (pAdapter->hostInterface == MV_HOST_IF_PEX) + { + errorCause = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + + MV_PCI_E_INTERRUPT_CAUSE_REG_OFFSET); + } + else if (pAdapter->hostInterface == MV_HOST_IF_PCI) + { + errorCause = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + + MV_PCI_INTERRUPT_CAUSE_REG_OFFSET); + _dumpPCIRegs(pAdapter); + } + + + { + MV_U8 i; + + for (i = 0; i < pAdapter->numberOfChannels;i++) + { + _dumpEDMARegs(pAdapter, i); + _dumpChannelQueues(pAdapter, i); + } + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR | MV_DEBUG_INTERRUPTS, + " %d : PCI error, pci interrupt cause register=%08x\n", + pAdapter->adapterId, errorCause); + /* clear cause register */ + if (pAdapter->hostInterface == MV_HOST_IF_PEX) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + + MV_PCI_E_INTERRUPT_CAUSE_REG_OFFSET, + ~errorCause); + } + else if (pAdapter->hostInterface == MV_HOST_IF_PCI) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + + MV_PCI_INTERRUPT_CAUSE_REG_OFFSET, + ~errorCause); + } + pAdapter->mvSataEventNotify(pAdapter, MV_EVENT_TYPE_ADAPTER_ERROR, + errorCause, 0); +} +#ifdef MV_SATA_C2C_COMM +/******************************************************************************* +* handleC2CInterrupt - channel 2 channel interrupt handler +* +* +* DESCRIPTION: +* Handles channel 2 channel interrupt (register device 2 host FIS) and +* convert ATA registers values to user specific 10 bytes message +* +* INPUT: +* pSataChannel - pointer to the Sata channel data structure +* +* RETURN: +* None +* +* COMMENTS: +* None +* +*******************************************************************************/ +static void handleC2CInterrupt(MV_SATA_CHANNEL *pSataChannel) +{ + MV_BUS_ADDR_T ioBaseAddr = + pSataChannel->mvSataAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + MV_U8 port = pSataChannel->channelNumber & (MV_BIT0 | MV_BIT1); + MV_U8 sataUnit = (pSataChannel->channelNumber & MV_BIT2) >> 2; + MV_U8 ATAstatus; + MV_STORAGE_DEVICE_REGISTERS deviceRegs; + + mvOsSemTake(&pSataChannel->semaphore); + + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_ALTERNATE_REG_OFFSET); + + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + /* clear DevInterrupt*/ + MV_REG_WRITE_DWORD(ioBaseAddr, MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET, ~(MV_BIT8 << port)); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: C2C Interrupt: status 0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus); + + dumpAtaDeviceRegisters(pSataChannel->mvSataAdapter, + pSataChannel->channelNumber, + MV_TRUE, + &deviceRegs); + mvOsSemRelease(&pSataChannel->semaphore); + if (pSataChannel->C2CCallback) + { + MV_U8 msg[MV_C2C_MESSAGE_SIZE]; + msg[0] = deviceRegs.errorRegister; + msg[1] = deviceRegs.lbaLowRegister & 0xFF; + msg[2] = deviceRegs.lbaMidRegister & 0xFF; + msg[3] = deviceRegs.lbaHighRegister & 0xFF; + msg[4] = deviceRegs.deviceRegister; + msg[5] = deviceRegs.lbaLowRegister >> 8; + msg[6] = deviceRegs.lbaMidRegister >> 8; + msg[7] = deviceRegs.lbaHighRegister >> 8; + msg[8] = deviceRegs.sectorCountRegister & 0xFF; + msg[9] = deviceRegs.sectorCountRegister >> 8; + pSataChannel->C2CCallback(pSataChannel->mvSataAdapter, + pSataChannel, + MV_C2C_REGISTER_DEVICE_TO_HOST_FIS_DONE, + MV_C2C_MESSAGE_SIZE, + msg); + } +} +#endif + + + +static void handleDeviceInterrupt(MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit, + MV_U8 port) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_QUEUED_COMMAND_ENTRY *pCommandEntry; + MV_U8 channelIndex; + + channelIndex = MV_CHANNEL_INDEX(sataUnit, port); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: SaDevInterrupt Received\n", pAdapter->adapterId, + channelIndex); + + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: SaDevInterrupt Received for disconnected channel\n", + pAdapter->adapterId, channelIndex); + /* disable SaDevInterrupts from this channel */ + disableSaDevInterrupts(pAdapter,channelIndex); + return; + } +#ifdef MV_SATA_C2C_COMM + /*handle channel 2 channel communication mode*/ + if (pSataChannel->C2CmodeEnabled == MV_TRUE) + { + handleC2CInterrupt(pSataChannel); + return; + } +#endif + + mvOsSemTake(&pSataChannel->semaphore); + if (pSataChannel->ErrorHandlingInfo.state == MV_ERROR_HANDLING_STATE_WAIT_FOR_BUSY) + { + MV_U8 ATAstatus; + + ATAstatus = MV_REG_READ_BYTE(pAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + /* clear DevInterrupt*/ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET, + ~(MV_BIT8 << port)); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: enter NCQ error handling request sense state\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + pSataChannel->ErrorHandlingInfo.state = MV_ERROR_HANDLING_STATE_REQUEST_SENSE; + pSataChannel->ErrorHandlingInfo.CurrPort = 0; + setReadLogExtCmndPointers(pSataChannel); + handlePortError(pSataChannel); + mvOsSemRelease(&pSataChannel->semaphore); + return; + } + + /* clear interrupt */ + + pCommandEntry = pSataChannel->commandsQueueHead; + if (pCommandEntry == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: SaDevInterrupt: No command is running!!!\n", + pAdapter->adapterId, channelIndex); + _dumpSataRegs(pAdapter, channelIndex); + /* disable SaDevInterrupts from this channel */ + disableSaDevInterrupts(pAdapter,channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return; + } + if ((pCommandEntry->isFreeEntry == MV_TRUE) || + (pCommandEntry->pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_UDMA)) + { + if (pCommandEntry->isFreeEntry == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: SaDevInterrupt: current command is free ???\n", + pAdapter->adapterId, channelIndex); + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: SaDevInterrupt: current command is Not PIO ???\n", + pAdapter->adapterId, channelIndex); + } + /* disable SaDevInterrupts from this channel */ + disableSaDevInterrupts(pAdapter,channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return; + } + handlePIOInterrupt(pSataChannel, pCommandEntry); + mvOsSemRelease(&pSataChannel->semaphore); +} + +static void handlePIOInterrupt(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry) +{ + MV_BUS_ADDR_T ioBaseAddr = pSataChannel->mvSataAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + MV_U8 port = pSataChannel->channelNumber & (MV_BIT0 | MV_BIT1); + MV_U8 sataUnit = (pSataChannel->channelNumber & MV_BIT2) >> 2; + MV_U8 ATAstatus; + MV_NON_UDMA_PROTOCOL protocolType; + + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_ALTERNATE_REG_OFFSET); + + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + /* clear DevInterrupt*/ + MV_REG_WRITE_DWORD(ioBaseAddr, MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET, ~(MV_BIT8 << port)); + + if(pCommandEntry->pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_PACKET) + { + protocolType = pCommandEntry->pCommandInfo->commandParams.packetCommand.protocolType; + } + else + { + protocolType = pCommandEntry->pCommandInfo->commandParams.NoneUdmaCommand.protocolType; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: PIO Interrupt: cmd 0x%02X, type %d. status 0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pCommandEntry->pCommandInfo->commandParams.NoneUdmaCommand.command, + protocolType, + ATAstatus); + if (ATAstatus & MV_ATA_BUSY_STATUS) + { + if (pSataChannel->mvSataAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, "%d %d: " + "PIO Interrupt: drive is BUSY!!!! status 0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus); + } + return; + } + if (ATAstatus & MV_ATA_ERROR_STATUS) + { + if (pSataChannel->FBSEnabled == MV_TRUE) + { + /*clear interrupt cause to resume the transport layer operation*/ + MV_REG_WRITE_DWORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_FIS_INTERRUPT_CAUSE_REG_OFFSET, + ~MV_BIT8); + } + if (pCommandEntry->pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_NONE_UDMA) + { + completePIOCommand(pSataChannel, pCommandEntry, MV_TRUE); + return; + } + } + switch (protocolType) + { + case MV_NON_UDMA_PROTOCOL_NON_DATA: + /* command is successfully completed*/ + completePIOCommand(pSataChannel, pCommandEntry, MV_FALSE); + break; + case MV_NON_UDMA_PROTOCOL_PIO_DATA_IN: + if (ATAstatus & MV_ATA_READY_STATUS) + { + if (transferPIOData(pSataChannel, + &pCommandEntry->pCommandInfo->commandParams.NoneUdmaCommand) == MV_TRUE) + { + if (pCommandEntry->pCommandInfo->commandParams.NoneUdmaCommand.count == 0) + { + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if (ATAstatus & MV_ATA_DATA_REQUEST_STATUS) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: PIO Interrupt: DRQ still set. ATA status 0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus); + return; + } + completePIOCommand(pSataChannel, pCommandEntry, MV_FALSE); + return; + } +#ifdef MV_SATA_SUPPORT_READ_WRITE_LONG + + /* for Read long only*/ + if (pCommandEntry->pCommandInfo->commandParams.NoneUdmaCommand.count == 4) + { + if (transferPIOData(pSataChannel, + &pCommandEntry->pCommandInfo->commandParams.NoneUdmaCommand) == MV_TRUE) + { + completePIOCommand(pSataChannel, pCommandEntry, MV_FALSE); + } + else + { + completePIOCommand(pSataChannel, pCommandEntry, MV_TRUE); + } + } +#endif /*MV_SATA_SUPPORT_READ_WRITE_LONG*/ + + } + else + { + completePIOCommand(pSataChannel, pCommandEntry, MV_TRUE); + } + } + else /* when BUSY and DRQ cleared to zero then the device has*/ + { + /* completed the command with error */ + completePIOCommand(pSataChannel, pCommandEntry, MV_TRUE); + return; + } + break; + case MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT: + if ((ATAstatus & MV_ATA_READY_STATUS) && + !(ATAstatus & MV_ATA_DEVICE_FAULT_STATUS)) + { + if (pCommandEntry->pCommandInfo->commandParams.NoneUdmaCommand.count == 0) + { + completePIOCommand(pSataChannel, pCommandEntry, MV_FALSE); + } + else + { + if (transferPIOData(pSataChannel, + &pCommandEntry->pCommandInfo->commandParams.NoneUdmaCommand) == MV_FALSE) + { + completePIOCommand(pSataChannel, pCommandEntry, MV_TRUE); + } + } + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: PIO Interrupt: PIO" + " Data Out command failed status 0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus); + completePIOCommand(pSataChannel, pCommandEntry, MV_TRUE); + } + break; +#ifdef MV_SUPPORT_ATAPI + case MV_NON_UDMA_PROTOCOL_PACKET_PIO_NON_DATA: + completePacketCommand(pSataChannel, pCommandEntry, MV_FALSE); + break; + case MV_NON_UDMA_PROTOCOL_PACKET_PIO_DATA_IN: + case MV_NON_UDMA_PROTOCOL_PACKET_PIO_DATA_OUT: + { + MV_U8 ATASectorCount = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET); + + if ((ATAstatus & MV_ATA_ERROR_STATUS) || (ATAstatus & MV_ATA_DEVICE_FAULT_STATUS)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Packet Interrupt: Command completed with error: ATA status 0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus); + completePacketCommand(pSataChannel, pCommandEntry, MV_TRUE); + return; + } + if ((ATAstatus & MV_ATA_DATA_REQUEST_STATUS) == 0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + "%d %d: Packet Interrupt: Command completed ATA status 0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus); + completePacketCommand(pSataChannel, pCommandEntry, MV_FALSE); + return; + } + if (((ATAstatus & MV_ATA_READY_STATUS) != MV_ATA_READY_STATUS) || + (((ATASectorCount & 0x3) != MV_BIT1) && (protocolType == MV_NON_UDMA_PROTOCOL_PACKET_PIO_DATA_IN)) || + (((ATASectorCount & 0x3) != 0) && (protocolType == MV_NON_UDMA_PROTOCOL_PACKET_PIO_DATA_OUT)) + ) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Packet Interrupt: unexpected ATA regs: ATA status 0x%02x," + " ATA SectorCount 0x%02x protocol %d\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus, ATASectorCount, + protocolType); + + /* completed the command with error */ + completePacketCommand(pSataChannel, pCommandEntry, MV_TRUE); + return; + } + else + { + MV_U8 LBAMid = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_MID_REG_OFFSET); + MV_U8 LBAHigh = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET); + MV_U16 byteCount = (LBAHigh << 8) | LBAMid; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " Packet with Data: LBA Mid %x, LBA High %x\n", + LBAMid, LBAHigh); + if (transferPacketData(pSataChannel, + &pCommandEntry->pCommandInfo->commandParams.packetCommand, + byteCount) != MV_TRUE) + { + completePacketCommand(pSataChannel, pCommandEntry, MV_TRUE); + } + } + } + break; + case MV_NON_UDMA_PROTOCOL_PACKET_DMA: + { + MV_U32 BMDMA_status = MV_REG_READ_DWORD (ioBaseAddr, + getEdmaRegOffset(pSataChannel->channelNumber) + + MV_BMDMA_STATUS_OFFSET); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + "%d %d: Packet Interrupt: in ATAPI DMA command ATA status 0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + "Packet Interrupt: BMDMA status 0x%08x\n", BMDMA_status); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + " Packet Interrupt: EDMA Error cause 0x%08x\n", + MV_REG_READ_DWORD (ioBaseAddr, + getEdmaRegOffset(pSataChannel->channelNumber) + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET)); + if(ATAstatus & MV_ATA_ERROR_STATUS) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "Packet Interrupt: DMA command completed with error BMDMA " + "status 0x%08x, ATA status 0x%02x\n", BMDMA_status, ATAstatus); + _resetBmDma(pSataChannel->mvSataAdapter, pSataChannel->channelNumber); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + ": BMDMA status(2) 0x%08x\n", + MV_REG_READ_DWORD (ioBaseAddr, + getEdmaRegOffset(pSataChannel->channelNumber) +MV_BMDMA_STATUS_OFFSET)); + + pCommandEntry->pCommandInfo->commandParams.packetCommand.transfered_data = 0; + } + else + { + pCommandEntry->pCommandInfo->commandParams.packetCommand.transfered_data = + pCommandEntry->pCommandInfo->commandParams.packetCommand.buffer_len; + +#if 0 + /* chech if the BMDMA still active*/ + if (BMDMA_status & MV_BIT0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + "Packet Interrupt: BMDMA not finished yet. " + "status 0x%08x, ATA status 0x%02x\n", BMDMA_status, ATAstatus); + /* wait for BMDMA done interrrupt*/ + pSataChannel->waitForBMDMA = MV_TRUE; + return; + } +#endif + /* if BMDMA finished, call _resetBmDma to clear the Done interrupt*/ + _resetBmDma(pSataChannel->mvSataAdapter, pSataChannel->channelNumber); + /* chech if the BMDMA completed with errors*/ + if (BMDMA_status & MV_BIT1) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + "Packet Interrupt: BMDMA completed with error. " + "status 0x%08x, ATA status 0x%02x\n", BMDMA_status, ATAstatus); + completePacketCommand(pSataChannel, pCommandEntry, MV_TRUE); + return; + } + } + completePacketCommand(pSataChannel, pCommandEntry, MV_FALSE); + return; + } + break; +#endif + default: /* never reached */ + break; + } +} +static MV_BOOLEAN transferPIOData(MV_SATA_CHANNEL *pSataChannel, + MV_NONE_UDMA_COMMAND_PARAMS *pNoneUdmaCommandParams) +{ + MV_U32 i; + MV_U32 dataBlockWords = pSataChannel->DRQDataBlockSize * ATA_SECTOR_SIZE_IN_WORDS; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: xfer data for PIO Data command.count %d\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, pNoneUdmaCommandParams->count); + + switch (pNoneUdmaCommandParams->protocolType) + { + case MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT: + for (i = 0; i < dataBlockWords; i++) + { + if (pNoneUdmaCommandParams->count == 0) + { + return MV_TRUE; + } + pNoneUdmaCommandParams->count--; + MV_REG_WRITE_WORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET, + *pNoneUdmaCommandParams->bufPtr++); + } + break; + case MV_NON_UDMA_PROTOCOL_PIO_DATA_IN: + for (i = 0; i < dataBlockWords; i++) + { + MV_U16 data; + if (pNoneUdmaCommandParams->count == 0) + { + return MV_TRUE; + } + pNoneUdmaCommandParams->count--; + data = MV_REG_READ_WORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET); +#if defined(MV_NETBSD) + /* identify data is in big endian */ + if((pNoneUdmaCommandParams->command == MV_ATA_COMMAND_IDENTIFY) || + (pNoneUdmaCommandParams->command == MV_ATA_COMMAND_ATAPI_IDENTIFY)) + data = MV_BE16_TO_CPU(data); + else + data = MV_CPU_TO_LE16(data); /*should be LE16 TO CPU */ +#endif + *pNoneUdmaCommandParams->bufPtr++ = data; + + } + break; + default: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, "%d %d: in xfer data " + "PIO: command protocol is not Data in/out\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + return MV_FALSE; + } + return MV_TRUE; +} +#ifdef MV_SUPPORT_ATAPI +static MV_BOOLEAN transferPacketData(MV_SATA_CHANNEL *pSataChannel, + MV_PACKET_COMMAND_PARAMS *pPacketCommandParams, + MV_U16 byteCount) +{ + MV_U32 i; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: xfer data for Packet command.count %d\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, byteCount); + byteCount >>= 1; + switch (pPacketCommandParams->protocolType) + { + case MV_NON_UDMA_PROTOCOL_PACKET_PIO_DATA_IN: + for (i = 0; i < byteCount; i++) + { + MV_U16 data; + if (pPacketCommandParams->transfered_data == pPacketCommandParams->buffer_len) + { + return MV_TRUE; + } + pPacketCommandParams->transfered_data += 2; + data = MV_REG_READ_WORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET); + *pPacketCommandParams->bufPtr++ = MV_CPU_TO_LE16(data); + } + break; + case MV_NON_UDMA_PROTOCOL_PACKET_PIO_DATA_OUT: + for (i = 0; i < byteCount; i++) + { + if (pPacketCommandParams->transfered_data == pPacketCommandParams->buffer_len) + { + return MV_TRUE; + } + pPacketCommandParams->transfered_data += 2; + MV_REG_WRITE_WORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_CPU_TO_LE16(MV_ATA_DEVICE_PIO_DATA_REG_OFFSET), + *pPacketCommandParams->bufPtr++); + } + break; + default: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, "%d %d: in xfer data " + "Packet command: non valid protocol type (%d)\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber,pPacketCommandParams->protocolType ); + return MV_FALSE; + } + return MV_TRUE; +} +#endif + +static void completePIOCommand(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_BOOLEAN failed) +{ + MV_COMPLETION_TYPE compType = MV_COMPLETION_TYPE_NORMAL; + MV_STORAGE_DEVICE_REGISTERS deviceRegs; + MV_U8 hostTag; + MV_NONE_UDMA_COMMAND_PARAMS *pParams = + &pCommandEntry->pCommandInfo->commandParams.NoneUdmaCommand; + + if (pCommandEntry->pCommandInfo->type != MV_QUEUED_COMMAND_TYPE_NONE_UDMA) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, "%d %d: completePIOCommand called for" + " wrong command\n",pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber ); + } + dumpAtaDeviceRegisters(pSataChannel->mvSataAdapter, + pSataChannel->channelNumber, pParams->isEXT, + &deviceRegs); + if (failed == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: PIO Command completed " + "with error\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + + compType = MV_COMPLETION_TYPE_ERROR; + pSataChannel->queueCommandsEnabled = MV_FALSE; + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: PIO Command completed successfully\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + pSataChannel->recoveredErrorsCounter = 0; + } + /* pCommandEntry is invalid after calling the callback function + so we cache the tag to be used later*/ + + hostTag = pCommandEntry->hostTag; + if (hostTag == 0xFF)/*NCQ Error handling ReadLogExt command*/ + { + /*sanity check*/ + if (pCommandEntry != pSataChannel->ErrorHandlingInfo.pReadLogExtEntry) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, + "%d %d: in completePIOCommand, command is ReadLogExt" + ", pointers mismatch \n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + } + commandsQueueRemove(pSataChannel,pCommandEntry); + } + else + { + removeCommand(pSataChannel,pCommandEntry); + } + + pParams->callBack(pSataChannel->mvSataAdapter, pSataChannel->channelNumber, + compType, pParams->commandId, 0, 0, &deviceRegs); + + if (hostTag != 0xFF)/*if not NCQ Error handling ReadLogExt command*/ + { + if (failed == MV_TRUE) + { + _doDevErrorRecovery(pSataChannel); + } + else + { + _insertQCommandsIntoEdma(pSataChannel); + } + } +} +#ifdef MV_SUPPORT_ATAPI +static void completePacketCommand(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_BOOLEAN failed) +{ + MV_COMPLETION_TYPE compType = MV_COMPLETION_TYPE_NORMAL; + MV_STORAGE_DEVICE_REGISTERS deviceRegs; + MV_PACKET_COMMAND_PARAMS *pParams = + &pCommandEntry->pCommandInfo->commandParams.packetCommand; + MV_U32 transfered_data = pParams->transfered_data; + + dumpAtaDeviceRegisters(pSataChannel->mvSataAdapter, + pSataChannel->channelNumber, MV_FALSE, + &deviceRegs); + if (failed == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: Packet Command completed " + "with error\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: Packet Command completed successfully\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + } + pSataChannel->recoveredErrorsCounter = 0; + + + removeCommand(pSataChannel,pCommandEntry); + + pParams->callBack(pSataChannel->mvSataAdapter, pSataChannel->channelNumber, + compType, pParams->commandId, 0, transfered_data, &deviceRegs); + + _insertQCommandsIntoEdma(pSataChannel); +} +#endif +static MV_VOID initTagsStack(struct _mvTagsStack *pTagsStack, + MV_U8 *pTagsArray, MV_U8 size); + +static MV_U8 popTag(struct _mvTagsStack *pTagsStack); + +static MV_VOID pushTag(struct _mvTagsStack *pTagsStack, MV_U8 tag); + +static MV_BOOLEAN isEmpty(struct _mvTagsStack *pTagsStack); + +static MV_VOID initChannelTags(MV_SATA_CHANNEL *pSataChannel); +static MV_BOOLEAN getTag(MV_SATA_CHANNEL *pSataChannel, MV_U8 PMPort, + MV_U8 *pHostTag,MV_U8 *pDeviceTag); +static MV_VOID releaseTag(MV_SATA_CHANNEL *pSataChannel, MV_U8 PMPort, + MV_U8 hostTag,MV_U8 deviceTag); + +static MV_VOID initTagsStack(struct _mvTagsStack *pTagsStack, + MV_U8 *pTagsArray, MV_U8 size) +{ + MV_U8 i; + pTagsStack->pTagsArray = pTagsArray; + pTagsStack->top = size; + for (i = 0; i < size; i++) + { + pTagsStack->pTagsArray[i] = size - 1 - i; + } +} + +static MV_U8 popTag(struct _mvTagsStack *pTagsStack) +{ + return pTagsStack->pTagsArray[--pTagsStack->top]; +} + +static MV_VOID pushTag(struct _mvTagsStack *pTagsStack, MV_U8 tag) +{ + pTagsStack->pTagsArray[pTagsStack->top++] = tag; +} + +static MV_BOOLEAN isEmpty(struct _mvTagsStack *pTagsStack) +{ + if (pTagsStack->top == 0) + { + return MV_TRUE; + } + return MV_FALSE; +} + +static MV_VOID initChannelTags(MV_SATA_CHANNEL *pSataChannel) +{ + MV_U8 i; + for (i = 0; i < MV_SATA_GEN2E_TAG_POOLS_NUM; i++) + { + initTagsStack(&pSataChannel->Tags.DeviceTagsPool[i], + pSataChannel->Tags.DeviceTags[i], + MV_SATA_TAGS_PER_POOL); + } + if (pSataChannel->use128Entries == MV_TRUE) + { + initTagsStack(&pSataChannel->Tags.HostTagsPool, + pSataChannel->Tags.HostTags, + MV_SATA_GEN2E_SW_QUEUE_SIZE); + } + else + { + initTagsStack(&pSataChannel->Tags.HostTagsPool, + pSataChannel->Tags.HostTags, + MV_SATA_SW_QUEUE_SIZE); + } +} +static MV_BOOLEAN getTag(MV_SATA_CHANNEL *pSataChannel, MV_U8 PMPort, + MV_U8 *pHostTag,MV_U8 *pDeviceTag) +{ + MV_U8 pool = 0;/*for Gen1-2 devices host tag must be equal to device tag*/ + if (pSataChannel->mvSataAdapter->sataAdapterGeneration >= MV_SATA_GEN_IIE) + { + pool = PMPort & MV_SATA_GEN2E_TAG_PMPORT_MASK; + } + if ((MV_TRUE == isEmpty(&pSataChannel->Tags.HostTagsPool)) || + (MV_TRUE == isEmpty(&pSataChannel->Tags.DeviceTagsPool[pool]))) + { + return MV_FALSE; + } + *pHostTag = popTag(&pSataChannel->Tags.HostTagsPool); + *pDeviceTag = popTag(&pSataChannel->Tags.DeviceTagsPool[pool]); + return MV_TRUE; +} +static MV_VOID releaseTag(MV_SATA_CHANNEL *pSataChannel, MV_U8 PMPort, + MV_U8 hostTag,MV_U8 deviceTag) +{ + MV_U8 pool = 0;/*for Gen1-2 devices host tag must be equal to device tag*/ + if (pSataChannel->mvSataAdapter->sataAdapterGeneration >= MV_SATA_GEN_IIE) + { + pool = PMPort & MV_SATA_GEN2E_TAG_PMPORT_MASK; + } + pushTag(&pSataChannel->Tags.HostTagsPool, hostTag); + pushTag(&pSataChannel->Tags.DeviceTagsPool[pool], deviceTag); +} + +/******************************************************************************* +* _resetEdmaQPointers - resets EDMA's Queues Pointers +* +* +* DESCRIPTION: +* +* INPUT: +* *pSataChannel - pointer to the Sata channel data structure +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* +* COMMENTS: +* this function assumes that the channel semaphore is locked +* +*******************************************************************************/ +static MV_BOOLEAN _resetEdmaQPointers(MV_SATA_CHANNEL *pSataChannel) +{ + MV_BUS_ADDR_T ioBaseAddr = + pSataChannel->mvSataAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, "%d %d: _resetEdmaQPointers\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + + pSataChannel->EdmaQueuedCommands = 0; + pSataChannel->reqInPtr = 0; + pSataChannel->rspOutPtr = 0; + + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_REQUEST_Q_BAH_REG_OFFSET, + pSataChannel->requestQueuePciHiAddress); + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_REQUEST_Q_INP_REG_OFFSET, + pSataChannel->requestQueuePciLowAddress & + MV_EDMA_REQUEST_Q_BA_MASK); + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_REQUEST_Q_OUTP_REG_OFFSET, 0); + + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_RESPONSE_Q_BAH_REG_OFFSET, + pSataChannel->responseQueuePciHiAddress); + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_RESPONSE_Q_INP_REG_OFFSET, 0); + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_RESPONSE_Q_OUTP_REG_OFFSET, + pSataChannel->responseQueuePciLowAddress); + + return MV_TRUE; +} +static void setupEdmaDeviceErrorHandlingConfiguration(MV_SATA_CHANNEL *pSataChannel) +{ + MV_BUS_ADDR_T ioBaseAddr = pSataChannel->mvSataAdapter->adapterIoBaseAddress; + + if (pSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) + { + _setRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_INTERRUPT_ERROR_MASK_REG_OFFSET, MV_BIT2); + + if (pSataChannel->mvSataAdapter->sataAdapterGeneration == MV_SATA_GEN_IIE) + { + _clearRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_HALT_CONDITIONS_REG_OFFSET, MV_BIT2); + _clearRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_FIS_CONFIGURATION_REG_OFFSET, MV_BIT10 | MV_BIT8); + } + else + { + _setRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_CONFIG_REG_OFFSET, MV_EDMA_CONFIG_CONONDEVERR_MASK); + /* Fix for 88SX60x1 FEr SATA#25 */ + _setRegBits(ioBaseAddr, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET, MV_BIT22); + } + } + else + { + + _clearRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_CONFIG_REG_OFFSET, MV_EDMA_CONFIG_CONONDEVERR_MASK); + if (pSataChannel->mvSataAdapter->sataAdapterGeneration == MV_SATA_GEN_II) + { + _clearRegBits(ioBaseAddr, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET, MV_BIT22); + } + + if (pSataChannel->FBSEnabled == MV_TRUE) + { + if (pSataChannel->queuedDMA == MV_EDMA_MODE_QUEUED) + { + _setRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_INTERRUPT_ERROR_MASK_REG_OFFSET, MV_BIT2); + } + else + { + _clearRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_INTERRUPT_ERROR_MASK_REG_OFFSET, MV_BIT2); + } + _clearRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_HALT_CONDITIONS_REG_OFFSET, MV_BIT2); + _setRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_FIS_CONFIGURATION_REG_OFFSET, MV_BIT8); + _clearRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_FIS_CONFIGURATION_REG_OFFSET, MV_BIT10); + + } + else + { + _clearRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_INTERRUPT_ERROR_MASK_REG_OFFSET, MV_BIT2); + if (pSataChannel->mvSataAdapter->sataAdapterGeneration == MV_SATA_GEN_IIE) + { + _setRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_HALT_CONDITIONS_REG_OFFSET, MV_BIT2); + _clearRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_FIS_CONFIGURATION_REG_OFFSET, MV_BIT10 | MV_BIT8); + } + } + } +} + +/******************************************************************************* +* resetEdmaChannel - resets the channel data stucture and EDMA registers +* +* +* DESCRIPTION: +* this function resets the low level EDMA fields of Sata channel data +* structure and initialize the EDMA register accourdingly +* +* INPUT: +* *pSataChannel - pointer to the Sata channel data structure +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* +* COMMENTS: +* this function assumes that the channel semaphore is locked +* +*******************************************************************************/ +static MV_BOOLEAN resetEdmaChannel(MV_SATA_CHANNEL *pSataChannel) +{ + MV_BUS_ADDR_T ioBaseAddr = + pSataChannel->mvSataAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + int i; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, "%d %d: resetEdmaChannel\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + + if (MV_REG_READ_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_COMMAND_REG_OFFSET) & + MV_EDMA_COMMAND_HARD_RST_MASK) + { + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_COMMAND_REG_OFFSET, + MV_EDMA_COMMAND_DISABLE_MASK); + + MV_REG_READ_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_COMMAND_REG_OFFSET); + mvMicroSecondsDelay(pSataChannel->mvSataAdapter, + MV_HARD_RESET_WAIT_NEGATE); + _fixPhyParams(pSataChannel->mvSataAdapter, pSataChannel->channelNumber); + } + else + { + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_COMMAND_REG_OFFSET, + MV_EDMA_COMMAND_DISABLE_MASK); + } + + pSataChannel->outstandingCommands = 0; + for (i = 0; i <= MV_SATA_PM_MAX_PORTS; i++) + { + pSataChannel->portQueuedCommands[i] = 0; + } + pSataChannel->noneUdmaOutstandingCommands = 0; +#ifdef MV_SUPPORT_ATAPI + pSataChannel->packetOutstandingCommands = 0; +#endif + pSataChannel->EdmaActive = MV_FALSE; + + /* init free entries stack*/ + initChannelTags(pSataChannel); + for (i = 0; i < pSataChannel->commandsQueueSize; i++) + { + pSataChannel->commandsQueue[i].isFreeEntry = MV_TRUE; + } + + pSataChannel->commandsQueueHead = NULL; + pSataChannel->commandsQueueTail = NULL; + pSataChannel->queueCommandsEnabled = MV_FALSE; +#ifdef MV_SATA_C2C_COMM + + /* C2C */ + pSataChannel->C2CmodeEnabled = MV_FALSE; +#endif + pSataChannel->ErrorHandlingInfo.CurrPort = 0; + pSataChannel->ErrorHandlingInfo.state = MV_ERROR_HANDLING_STATE_IDLE; + pSataChannel->ErrorHandlingInfo.PortsWithErrors = 0; + pSataChannel->ErrorHandlingInfo.useVendorUniqGen2WA = MV_FALSE; + pSataChannel->recoveredErrorsCounter = 0; + _resetEdmaQPointers(pSataChannel); + return MV_TRUE; +} + +static void flushDmaQueue(MV_SATA_CHANNEL *pSataChannel,MV_FLUSH_TYPE flushType, + MV_COMPLETION_TYPE completionType, MV_U16 eDmaCause) +{ + mvSataCommandCompletionCallBack_t callBackFunc; + int i; + + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d: Flush DMA, type=%s, commands" + " %d (on EDMA %d)\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + (flushType==MV_FLUSH_TYPE_CALLBACK)?"CALLBACK":"NONE", + pSataChannel->outstandingCommands,pSataChannel->EdmaQueuedCommands); + + if (flushType == MV_FLUSH_TYPE_CALLBACK) + { + for (i = 0; i < pSataChannel->commandsQueueSize; i++) + { + if (pSataChannel->commandsQueue[i].isFreeEntry == MV_FALSE) + { + MV_STORAGE_DEVICE_REGISTERS deviceRegisters; + MV_BOOLEAN isEXT; + MV_VOID_PTR commandId; + switch (pSataChannel->commandsQueue[i].pCommandInfo->type) + { + case MV_QUEUED_COMMAND_TYPE_NONE_UDMA: + isEXT = pSataChannel->commandsQueue[i].pCommandInfo->commandParams.NoneUdmaCommand.isEXT; + commandId = pSataChannel->commandsQueue[i].pCommandInfo->commandParams.NoneUdmaCommand.commandId; + callBackFunc = pSataChannel->commandsQueue[i].pCommandInfo->commandParams.NoneUdmaCommand.callBack; + break; + case MV_QUEUED_COMMAND_TYPE_UDMA: + isEXT = pSataChannel->commandsQueue[i].pCommandInfo->commandParams.udmaCommand.isEXT; + commandId = pSataChannel->commandsQueue[i].pCommandInfo->commandParams.udmaCommand.commandId; + callBackFunc = pSataChannel->commandsQueue[i].pCommandInfo->commandParams.udmaCommand.callBack; + break; + default: + /* MV_QUEUED_COMMAND_TYPE_PACKET:*/ + isEXT = MV_FALSE; + commandId = pSataChannel->commandsQueue[i].pCommandInfo->commandParams.packetCommand.commandId; + callBackFunc = pSataChannel->commandsQueue[i].pCommandInfo->commandParams.packetCommand.callBack; + break; + } + + dumpAtaDeviceRegisters(pSataChannel->mvSataAdapter, + pSataChannel->channelNumber, isEXT, + &deviceRegisters); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Calling callBackFunc - host tag 0x%x (device tag 0x%x) at %p," + " next %p, prev %p, PMPort 0x%x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + i, + pSataChannel->commandsQueue[i].deviceTag, + &pSataChannel->commandsQueue[i], + pSataChannel->commandsQueue[i].next, + pSataChannel->commandsQueue[i].prev, + pSataChannel->commandsQueue[i].pCommandInfo->PMPort); + callBackFunc(pSataChannel->mvSataAdapter, + pSataChannel->channelNumber, completionType, + commandId, eDmaCause, 0, &deviceRegisters); + } + } + } +} + +static void _fixPhyParams(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + /* Set unit 0 or 1 */ + MV_U8 sataUnit = (channelIndex & MV_BIT2) >> 2; + /* Set port 0-3 */ + MV_U8 port = channelIndex & (MV_BIT0 | MV_BIT1); + MV_U32 regVal; + + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + + if (pAdapter->chipIs50XXB0 == MV_TRUE) + { + /* Fix for 88SX50xx FEr SATA#12 */ + /* Disable auto-power management*/ + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_LT_MODES_PORT_REG_OFFSET(port)); + regVal |= MV_BIT19; /* disbale auto-power management*/ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_LT_MODES_PORT_REG_OFFSET(port), + regVal); + /* 88SX50xx FEr SATA#9*/ + /*Fix squelch threshold*/ + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_PHY_CONTROL_BRIDGE_PORT_OFFSET(port)); + + regVal &= ~0x3; + regVal |= 0x1; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_PHY_CONTROL_BRIDGE_PORT_OFFSET(port), + regVal); + } + /* Revert values of pre-emphasis and signal amps to the saved ones */ + { + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_PHY_MODE_BRIDGE_PORT_REG_OFFSET(port)); + regVal &= ~MV_SATA_I_PHY_MODE_AMP_MASK; + regVal |= (pAdapter->signalAmps[channelIndex] << MV_SATA_I_PHY_MODE_AMP_OFFSET) & + MV_SATA_I_PHY_MODE_AMP_MASK; + regVal &= ~MV_SATA_I_PHY_MODE_PRE_MASK; + regVal |= (pAdapter->pre[channelIndex] << MV_SATA_I_PHY_MODE_PRE_OFFSET) & + MV_SATA_I_PHY_MODE_PRE_MASK; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_PHY_MODE_BRIDGE_PORT_REG_OFFSET(port), + regVal); + } + } + if ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && + (pAdapter->chipIs62X1Z0 == MV_FALSE)) + { + MV_U32 phyMode2Offset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_PHY_MODE_2_REG_OFFSET; + if ((pAdapter->chipIs60X1B2 == MV_TRUE) || + (pAdapter->chipIs60X1C0 == MV_TRUE)) + { + /* Fix for 88SX60X1 FEr SATA #23 */ + /* 88SX6042/88SX7042 FEr SATA #23 */ + /* 88F5182 FEr #SATA-S13 */ + /* 88F5082 FEr #SATA-S13 */ + MV_U32 regVal2; + regVal2 = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_2_REG_OFFSET); + regVal2 |= MV_BIT31; + regVal2 &= ~MV_BIT16; + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_2_REG_OFFSET, + regVal2); + mvMicroSecondsDelay (pAdapter, 200); /* Wait 200uSec */ + regVal2 = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_2_REG_OFFSET); + regVal2 &= ~MV_BIT31; + regVal2 &= ~MV_BIT16; + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_2_REG_OFFSET, + regVal2); + mvMicroSecondsDelay (pAdapter, 200); /* Wait 200uSec */ + } + /* Fix values in phyMode 3 register.*/ + { + MV_U32 regVal2 = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_3_REG_OFFSET); + regVal2 &= ~0x7F900000; + regVal2 |= 0x2A800000; + + /* Implement Guidline 88F5182, 88F5082, 88F6082 (GL# SATA-S11) */ + if((pAdapter->pciConfigDeviceId == MV_SATA_DEVICE_ID_5182) || + (pAdapter->pciConfigDeviceId == MV_SATA_DEVICE_ID_5082) || + (pAdapter->pciConfigDeviceId == MV_SATA_DEVICE_ID_6082)) + { + regVal2 &= ~0x1C; + } + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_3_REG_OFFSET, + regVal2); + } + /* Fix values in phyMode 4 register.*/ + /* 88SX60x1 FEr SATA#10 */ + /* 88F5182 GL #SATA-S10 */ + /* 88F5082 GL #SATA-S10 */ + if ((pAdapter->chipIs60X1B2 == MV_TRUE) || + (pAdapter->chipIs60X1C0 == MV_TRUE)) + { + MV_U32 phyMode4Value; + MV_U32 tempRegOffset, tempRegValue = 0; + MV_U32 phyMode4Offset = getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_4_REG_OFFSET; + tempRegOffset = getEdmaRegOffset (channelIndex) + 0x310; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_SATA_LINK, + "%d %d: PHY mode4 reg value before fix is %x\n", + pAdapter->adapterId, channelIndex, + MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + phyMode4Offset)); + phyMode4Value = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + phyMode4Offset); + /* 88SX60x1 FEr SATA #13 */ + if (pAdapter->chipIs60X1B2 == MV_TRUE) + { + tempRegValue = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + tempRegOffset); + } + + phyMode4Value |= MV_BIT0; + phyMode4Value &= ~MV_BIT1; + /* phy mode 4 register of Gen IIE devices has some restriction */ + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_IIE) + { + phyMode4Value &= ~0x5DE3FFFC; + phyMode4Value |= MV_BIT2; + + } + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + phyMode4Offset, phyMode4Value); + /* 88SX60x1 FEr SATA #13 */ + if (pAdapter->chipIs60X1B2 == MV_TRUE) + { + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + tempRegOffset, tempRegValue); + } + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_SATA_LINK, + "%d %d: PHY mode4 reg value after fix is %x\n", + pAdapter->adapterId, channelIndex, + MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + phyMode4Offset)); + } + + /* Revert values of pre-emphasis and signal amps to the saved ones */ + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + phyMode2Offset); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, "%d %d: PHY mode2 " + "reg = %x (Before AMP/PRE modification)\n", + pAdapter->adapterId, channelIndex, regVal); + + regVal &= ~MV_SATA_II_PHY_MODE_2_AMP_MASK; + regVal |= (pAdapter->signalAmps[channelIndex] << MV_SATA_II_PHY_MODE_2_AMP_OFFSET) & + MV_SATA_II_PHY_MODE_2_AMP_MASK; + regVal &= ~MV_SATA_II_PHY_MODE_2_PRE_MASK; + regVal |= (pAdapter->pre[channelIndex] << MV_SATA_II_PHY_MODE_2_PRE_OFFSET) & + MV_SATA_II_PHY_MODE_2_PRE_MASK; + regVal &= ~MV_BIT16; /* Should always write 0 to bit 16 in phymode 2 */ + + /*some reserved fields must be written with fixed values */ + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_IIE) + { + regVal &= ~0xC30FF01F; + regVal |= 0x0000900F; + } + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + phyMode2Offset, regVal); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, "%d %d: PHY mode2 " + "reg = %x (After AMP/PRE modification)\n", + pAdapter->adapterId, channelIndex, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + phyMode2Offset)); + } + if(pAdapter->chipIs62X1Z0 == MV_TRUE) + { + + regVal = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_3_REG_OFFSET); + + regVal &= ~0x78100000; + regVal |= 0x28000000; + + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_3_REG_OFFSET, + regVal); + + regVal = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_4_REG_OFFSET); + regVal &= ~0x1; + regVal |= MV_BIT16; /* must write 1 to this bit */ + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_4_REG_OFFSET, + regVal); + + regVal = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_9_GEN2_REG_OFFSET); + regVal &= ~0x400F; + regVal |= 0x00008; + + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_9_GEN2_REG_OFFSET, + regVal); + + regVal = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_9_GEN1_REG_OFFSET); + regVal &= ~0x400F; + regVal |= 0x00008; + + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_PHY_MODE_9_GEN1_REG_OFFSET, + regVal); + } +} + +static void _channelHardReset(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_U32 EdmaCommandOffset = getEdmaRegOffset(channelIndex) + + MV_EDMA_COMMAND_REG_OFFSET; + + maskEdmaInterrupts(pAdapter, channelIndex); + /* 1. Set ATA reset bit*/ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, EdmaCommandOffset, + MV_EDMA_COMMAND_HARD_RST_MASK); + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, EdmaCommandOffset); + + /* 2. Wait 25uSeconds*/ + mvMicroSecondsDelay(pAdapter, MV_HARD_RESET_WAIT_ASSERT); + + + /* 3. Clear ATA reset bit*/ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, EdmaCommandOffset, 0); + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, EdmaCommandOffset); + + /* 4. Change phy params (watermark + squelch) */ + _fixPhyParams(pAdapter, channelIndex); + /* For Gen 1 devices, time delay is needed after resetingt the SATA bridge*/ + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + mvMicroSecondsDelay(pAdapter, MV_HARD_RESET_WAIT_NEGATE); + } + unmaskEdmaInterrupts(pAdapter, channelIndex); + +} +static void _establishSataComm(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_U32 SControlOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_CONTROL_REG_OFFSET; + MV_U32 SStatusOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_STATUS_REG_OFFSET; + MV_U32 SStatus; + MV_U8 retryCount, commRetryCount = 5, retryWithGen1 = 0; + + maskEdmaInterrupts(pAdapter, channelIndex); + + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + /* Set DET field in SControl register to 1 */ + MV_U8 port = channelIndex & (MV_BIT0 | MV_BIT1); + MV_U8 sataUnit = (channelIndex & MV_BIT2) >> 2; + SControlOffset = MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R02_STATUS_BRIDGE_PORT_OFFSET(port); + SStatusOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_STATUS_REG_OFFSET; + } + + while (1) + { + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, SControlOffset, 0x301); + MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, SControlOffset); + MV_CPU_WRITE_BUFFER_FLUSH(); + mvMicroSecondsDelay(pAdapter, MV_SATA_COMM_INIT_DELAY); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, SControlOffset, 0x300); + MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, SControlOffset); + MV_CPU_WRITE_BUFFER_FLUSH(); + mvMicroSecondsDelay(pAdapter, MV_SATA_COMM_INIT_WAIT_DELAY); + unmaskEdmaInterrupts(pAdapter, channelIndex); + /*Wait 200 msec for PHY to become ready*/ + for (retryCount = 0; retryCount < 200; retryCount++) + { + if (_checkSStatusAfterHReset(pAdapter, channelIndex) == MV_FALSE) + { + mvMicroSecondsDelay(pAdapter, 1000); + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_SATA_LINK, "%d %d: SATA PHY ready " + "after %d msec\n", pAdapter->adapterId, channelIndex, + retryCount); + + break; + } + } + if (retryCount == 200) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_SATA_LINK, + "%d %d: SATA PHY not ready after 200 msec\n", + pAdapter->adapterId, channelIndex); + } + SStatus = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + SStatusOffset); + /* Fix for 88SX60X1 FEr #10 - retry SATA communication if failed 5 times */ + /* this workaround applied for all devices for simplicity and robustness */ + if ((SStatus == 0x0) || (SStatus == 0x113) || (SStatus == 0x123)) + { + break; + } + commRetryCount --; + if (commRetryCount == 0) + { + MV_U32 regVal; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_FATAL_ERROR, + "%d %d: Failed OOB sequence 5 times !!!\n", + pAdapter->adapterId, channelIndex); + if ((SStatus != 0x121) || (retryWithGen1 == 1) || (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I)) + { + break; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_FATAL_ERROR, + "%d %d: SStatus is 0x121, Retry OOB sequence with Gen1 \n", + pAdapter->adapterId, channelIndex); + retryWithGen1 = 1; + commRetryCount = 5; + /* set the phy in offline mode */ + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, SControlOffset, 0x304); + + /* force Sata speed to Gen1*/ + regVal = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET); + /* according to the spec, bits [31:12] must be set to 0x009B1 */ + /* Fix for 88SX60x1 FEr SATA#8*/ + regVal &= 0x00000FFF; + /* regVal |= MV_BIT12;*/ + regVal |= 0x009B1000; + regVal &= ~MV_BIT7; /* Disable GEn II */ + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET, + regVal); + + _channelHardReset(pAdapter, channelIndex); + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d: Retrying OOB sequnce",pAdapter->adapterId, + channelIndex); + } +} + +static void _establishSataCommAll(MV_SATA_ADAPTER *pAdapter) +{ + MV_U8 channelIndex; + MV_U32 SControlOffset; + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + for (channelIndex = 0 ; channelIndex < pAdapter->numberOfChannels ; + channelIndex ++) + { + maskEdmaInterrupts(pAdapter, channelIndex); + SControlOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_CONTROL_REG_OFFSET; + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, SControlOffset, + 0x301); + + } + /* Wait for 1mSecond for COMRESET for all drives */ + mvMicroSecondsDelay(pAdapter, MV_SATA_COMM_INIT_DELAY); + for (channelIndex = 0 ; channelIndex < pAdapter->numberOfChannels ; + channelIndex ++) + { + SControlOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_CONTROL_REG_OFFSET; + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, SControlOffset, + 0x300); + } + mvMicroSecondsDelay(pAdapter, MV_SATA_COMM_INIT_WAIT_DELAY); + for (channelIndex = 0 ; channelIndex < pAdapter->numberOfChannels ; + channelIndex ++) + { + unmaskEdmaInterrupts(pAdapter, channelIndex); + } + } +} + + + + + +void _setActivePMPort(MV_SATA_CHANNEL *pSataChannel, MV_U8 PMPort) +{ + MV_BUS_ADDR_T ioBaseAddr = pSataChannel->mvSataAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + MV_U32 regVal; + + if (pSataChannel->PMSupported == MV_FALSE) + { + return; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG | MV_DEBUG_PM, "%d %d: Set TX PM" + " Port to %x\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, PMPort); + + regVal = MV_REG_READ_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_SATA_II_IF_CONTROL_REG_OFFSET); + + regVal &= ~MV_SATA_II_IF_CONTROL_PMTX_MASK; + regVal |= (PMPort << MV_SATA_II_IF_CONTROL_PMTX_OFFSET) & + MV_SATA_II_IF_CONTROL_PMTX_MASK; + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_SATA_II_IF_CONTROL_REG_OFFSET, regVal); + MV_REG_READ_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_SATA_II_IF_CONTROL_REG_OFFSET); + +} +static void revertSataHCRegs (MV_SATA_ADAPTER *pAdapter) +{ + MV_U8 channelIndex; + MV_U8 temp; + MV_U32 edmaRegsOffset; + MV_U32 sataHcRegsOffset; + MV_U32 regTemp; + MV_U8 sataUnit; + + if ((pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) || + (pAdapter->hostInterface == MV_HOST_IF_INTEGRATED)) + { + for (sataUnit = 0 ; sataUnit < pAdapter->numberOfUnits ; sataUnit ++) + { + for (temp = 0 ; temp < pAdapter->portsPerUnit ; temp ++) + { + channelIndex = temp + sataUnit * pAdapter->portsPerUnit; + edmaRegsOffset = getEdmaRegOffset(channelIndex); + + /* Disable EDMA */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_COMMAND_REG_OFFSET, + MV_EDMA_COMMAND_DISABLE_MASK); + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_COMMAND_REG_OFFSET); + + /* Reset SATA bridge */ + _channelHardReset(pAdapter, channelIndex); + + /* Zero EDMA registersr */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_COMMAND_REG_OFFSET, 0); + + if(pAdapter->hostInterface == MV_HOST_IF_INTEGRATED) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_CONFIG_REG_OFFSET, 0x101f); + } + else + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_CONFIG_REG_OFFSET, 0x11f); + } + + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_TIMER_REG_OFFSET, 0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET, 0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_INTERRUPT_ERROR_MASK_REG_OFFSET, 0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_REQUEST_Q_BAH_REG_OFFSET, 0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_REQUEST_Q_INP_REG_OFFSET, 0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_REQUEST_Q_OUTP_REG_OFFSET,0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_RESPONSE_Q_BAH_REG_OFFSET, 0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_RESPONSE_Q_OUTP_REG_OFFSET, 0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_RESPONSE_Q_INP_REG_OFFSET, 0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_TEST_CONTROL_REG_OFFSET, 0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegsOffset + MV_EDMA_IORDY_TIMEOUT_REG_OFFSET, 0x800); + } + + /* Revert values of SATA HC regs (few registers are READ-ONLY ) */ + if(pAdapter->hostInterface != MV_HOST_IF_INTEGRATED) + { + sataHcRegsOffset = MV_SATAHC_REGS_BASE_OFFSET(sataUnit); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + sataHcRegsOffset + MV_SATAHC_INT_COAL_THRE_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + sataHcRegsOffset + MV_SATAHC_INT_TIME_THRE_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + sataHcRegsOffset + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + sataHcRegsOffset + MV_SATA_I_HC_BRIDGES_TEST_CONTROL_REG_OFFSET, 0); + regTemp = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + sataHcRegsOffset + + MV_SATA_I_HC_BRIDGES_PINS_CONFIG_REG_OFFSET); + /* Keep the SS during power on and the reference clock bits (reset sample )*/ + regTemp &= 0x1c1c1c1c; + regTemp |= 0x03030303; + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + sataHcRegsOffset + MV_SATA_I_HC_BRIDGES_PINS_CONFIG_REG_OFFSET, + regTemp); + } + } + } + + if ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && + (pAdapter->hostInterface != MV_HOST_IF_INTEGRATED)) + { + MV_U32 timeout; + /* Use global reset feature */ + /* Empty PCI master */ + + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_MAIN_COMMAND_STATUS_REG_OFFSET, + MV_PCI_MAIN_COMMAND_STOP_MASTER_MASK); + MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_MAIN_COMMAND_STATUS_REG_OFFSET); + timeout = 1000; + while (timeout) + { + if (MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_MAIN_COMMAND_STATUS_REG_OFFSET) & + MV_PCI_MAIN_COMMAND_MASTER_EMPTY_MASK) + { + break; + } + + mvMicroSecondsDelay (pAdapter, 1); + timeout --; + } + if (timeout == 0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d: Global reset timeout when" + " trying to flush PCI master - discarding the master flush" + , pAdapter->adapterId); + } + /* Issue global reset - this will reset both SATAHC */ + regTemp = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_MAIN_COMMAND_STATUS_REG_OFFSET); + regTemp |= MV_PCI_MAIN_COMMAND_GLOBAL_RESET_MASK; + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_MAIN_COMMAND_STATUS_REG_OFFSET, regTemp); + regTemp = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_MAIN_COMMAND_STATUS_REG_OFFSET); + if (!(regTemp & MV_PCI_MAIN_COMMAND_GLOBAL_RESET_MASK)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d: Global reset error while " + "writing '1' to the global reset bit",pAdapter->adapterId); + } + mvMicroSecondsDelay (pAdapter, 5); + regTemp &= ~(MV_PCI_MAIN_COMMAND_GLOBAL_RESET_MASK | MV_PCI_MAIN_COMMAND_STOP_MASTER_MASK); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_MAIN_COMMAND_STATUS_REG_OFFSET, regTemp); + regTemp = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_MAIN_COMMAND_STATUS_REG_OFFSET); + if (regTemp & MV_PCI_MAIN_COMMAND_GLOBAL_RESET_MASK) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d: Global reset error while " + "writing '1' to the global reset bit",pAdapter->adapterId); + } + mvMicroSecondsDelay (pAdapter, 5); + } +} + +static void revertFlashInterfaceRegs (MV_SATA_ADAPTER *pAdapter) +{ + MV_U32 regTemp; + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_FLASH_PARAMS_REG_OFFSET, 0x0fcfffff); + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + regTemp = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET); + regTemp &= 0x3; + regTemp |= (MV_BIT5 | MV_BIT6); + + + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET, regTemp); + } +} + +static void revertPCIInterfaceRegs (MV_SATA_ADAPTER *pAdapter) +{ + MV_U32 regTemp; + if ((pAdapter->sataAdapterGeneration == MV_SATA_GEN_I)) + { + if (!((pAdapter->pciConfigDeviceId == MV_SATA_DEVICE_ID_5080) && + (pAdapter->pciConfigRevisionId == 0x0))) + { + regTemp = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET); + regTemp |= MV_BIT0; + + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET, regTemp); + } + } + + regTemp = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_MODE_REG_OFFSET); + regTemp &= 0xff00ffff; + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_MODE_REG_OFFSET, regTemp); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_DISCARD_TIMER_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_MSI_TRIGGER_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_XBAR_IF_TIMEOUT_REG_OFFSET, 0x000100ff); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_SERR_MASK_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_INTERRUPT_CAUSE_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_INTERRUPT_MASK_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_ERROR_LOW_ADDRESS_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_ERROR_HIGH_ADDRESS_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_ERROR_ATTRIBUTE_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_ERROR_COMMAND_REG_OFFSET, 0); +} + +static void revertPEXInterfaceRegs (MV_SATA_ADAPTER *pAdapter) +{ + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_E_INTERRUPT_CAUSE_REG_OFFSET, 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_PCI_E_INTERRUPT_MASK_REG_OFFSET, 0); +} +static void commandsQueueAddTail(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry) +{ + pCommandEntry->next = NULL; + pCommandEntry->prev = pSataChannel->commandsQueueTail; + if (pSataChannel->commandsQueueTail != NULL) + { + pSataChannel->commandsQueueTail->next = pCommandEntry; + } + pSataChannel->commandsQueueTail = pCommandEntry; + + if (pSataChannel->commandsQueueHead == NULL) + { + pSataChannel->commandsQueueHead = pCommandEntry; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: command queued. Head:%p Tail:%p " + "command :%p\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, pSataChannel->commandsQueueHead, + pSataChannel->commandsQueueTail, pCommandEntry); +} + +static void commandsQueueAddHead(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry) +{ + pCommandEntry->next = pSataChannel->commandsQueueHead; + pCommandEntry->prev = NULL; + if (pSataChannel->commandsQueueHead != NULL) + { + pSataChannel->commandsQueueHead->prev = pCommandEntry; + } + pSataChannel->commandsQueueHead = pCommandEntry; + + if (pSataChannel->commandsQueueTail == NULL) + { + pSataChannel->commandsQueueTail = pCommandEntry; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: command queued. Head:%p Tail:%p " + "command :%p\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, pSataChannel->commandsQueueHead, + pSataChannel->commandsQueueTail, pCommandEntry); +} + +static void commandsQueueRemove(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry) +{ + if (pCommandEntry->next == NULL) /* last */ + { + pSataChannel->commandsQueueTail = pCommandEntry->prev; + if (pSataChannel->commandsQueueTail != NULL) + { + pSataChannel->commandsQueueTail->next = NULL; + } + } + else + { + pCommandEntry->next->prev = pCommandEntry->prev; + } + + if (pCommandEntry->prev == NULL) /* head*/ + { + pSataChannel->commandsQueueHead = pCommandEntry->next; + if (pSataChannel->commandsQueueHead != NULL) + { + pSataChannel->commandsQueueHead->prev = NULL; + } + } + else + { + pCommandEntry->prev->next = pCommandEntry->next; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: command removed. Head:%p Tail:%p " + "command :%p\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, pSataChannel->commandsQueueHead, + pSataChannel->commandsQueueTail, pCommandEntry); + pCommandEntry->next = NULL; + pCommandEntry->prev = NULL; +} +static void addCommand(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_QUEUE_COMMAND_INFO *pCommandInfo) +{ +#ifndef MV_SATA_STORE_COMMANDS_INFO_ON_IAL_STACK + pCommandEntry->pCommandInfo = &pCommandEntry->commandInfo; + switch (pCommandInfo->type) + { + case MV_QUEUED_COMMAND_TYPE_UDMA: + memcpy(&pCommandEntry->pCommandInfo->commandParams.udmaCommand, + &pCommandInfo->commandParams.udmaCommand, + sizeof(MV_UDMA_COMMAND_PARAMS)); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: queue Udma command.\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + break; + case MV_QUEUED_COMMAND_TYPE_NONE_UDMA: + memcpy(&pCommandEntry->pCommandInfo->commandParams.NoneUdmaCommand, + &pCommandInfo->commandParams.NoneUdmaCommand, + sizeof(MV_NONE_UDMA_COMMAND_PARAMS)); + pSataChannel->noneUdmaOutstandingCommands++; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: queue Non Udma command.[%d]\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pSataChannel->noneUdmaOutstandingCommands); + break; +#ifdef MV_SUPPORT_ATAPI + case MV_QUEUED_COMMAND_TYPE_PACKET: + memcpy(&pCommandEntry->pCommandInfo->commandParams.packetCommand, + &pCommandInfo->commandParams.packetCommand, + sizeof(MV_PACKET_COMMAND_PARAMS)); + pSataChannel->packetOutstandingCommands++; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: queue Packet command.[%d]\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pSataChannel->packetOutstandingCommands); + break; +#endif + default: + break; + } + pCommandEntry->pCommandInfo->type = pCommandInfo->type; + pCommandEntry->pCommandInfo->PMPort = pCommandInfo->PMPort; +#else + if (pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_NONE_UDMA) + { + pSataChannel->noneUdmaOutstandingCommands++; + } + else if (pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_PACKET) + { + pSataChannel->packetOutstandingCommands++; + } + + pCommandEntry->pCommandInfo = pCommandInfo; +#endif + commandsQueueAddTail(pSataChannel, pCommandEntry); + /* pCommandEntry->commandTag = ?*/ + pCommandEntry->isFreeEntry = MV_FALSE; + pSataChannel->outstandingCommands++; + pSataChannel->portQueuedCommands[pCommandInfo->PMPort]++; +} + +static void removeCommand(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry) +{ + if (pCommandEntry->pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_UDMA) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: remove Udma command.\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + } + else if (pCommandEntry->pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_NONE_UDMA) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: remove Non Udma command.[%d]\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pSataChannel->noneUdmaOutstandingCommands); + + pSataChannel->noneUdmaOutstandingCommands--; + } +#ifdef MV_SUPPORT_ATAPI + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: remove Packet command.[%d]\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pSataChannel->packetOutstandingCommands); + + pSataChannel->packetOutstandingCommands--; + } +#endif + commandsQueueRemove(pSataChannel,pCommandEntry); + releaseTag(pSataChannel, pCommandEntry->pCommandInfo->PMPort, + pCommandEntry->hostTag,pCommandEntry->deviceTag); + pCommandEntry->isFreeEntry = MV_TRUE; + pSataChannel->outstandingCommands--; + pSataChannel->portQueuedCommands[pCommandEntry->pCommandInfo->PMPort]--; +} + +static MV_U32 SaDevInterrutpBit(MV_U8 channelIndex) +{ + MV_U32 maskBit = 0; + + if (channelIndex >= MV_SATA_PORT_PER_UNIT) + { + maskBit = (1 << ((channelIndex << 1) + 2)); + } + else + { + maskBit = (1 << ((channelIndex << 1) + 1)); + } + return maskBit; +} +static void enableSaDevInterrupts(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_U32 maskBit = 0; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: enable SaDevInterrupts.\n", + pAdapter->adapterId, channelIndex); + maskBit = SaDevInterrutpBit(channelIndex); + mvOsSemTake(&pAdapter->interruptsMaskSem); + + pAdapter->mainMask |= maskBit; + + /*clear disk interrupt */ + MV_REG_READ_BYTE(pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + /* clear DevInterrupt*/ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET((channelIndex & MV_BIT2) >> 2) + + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET, + ~(MV_BIT8 << (channelIndex & (MV_BIT0 | MV_BIT1)))); + + /* unmask*/ + if (pAdapter->interruptsAreMasked == MV_FALSE) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, + pAdapter->mainMask); + + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset); + + } + mvOsSemRelease(&pAdapter->interruptsMaskSem); +} + +void disableSaDevInterrupts(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_U32 maskBit = 0; + + + maskBit = SaDevInterrutpBit(channelIndex); + mvOsSemTake(&pAdapter->interruptsMaskSem); + pAdapter->mainMask &= ~maskBit; + if (pAdapter->interruptsAreMasked == MV_FALSE) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, + pAdapter->mainMask); + + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset); + + } + mvOsSemRelease(&pAdapter->interruptsMaskSem); +} +static void _checkATAStatus(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + MV_U8 ATAstatus = MV_REG_READ_BYTE(pAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + if ((ATAstatus & (MV_ATA_BUSY_STATUS|MV_ATA_DATA_REQUEST_STATUS| + MV_ATA_READY_STATUS|MV_ATA_DEVICE_FAULT_STATUS| + MV_ATA_ERROR_STATUS)) == MV_ATA_READY_STATUS) + { + return; + } + } + else + { + if ((ATAstatus & (MV_ATA_BUSY_STATUS|MV_ATA_DATA_REQUEST_STATUS| + MV_ATA_READY_STATUS)) == MV_ATA_READY_STATUS) + { + return; + } + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: _checkATAStatus " + "EDMA can't be enabled with ATA status (0x%02x), do SW reset\n", + pAdapter->adapterId, channelIndex, ATAstatus); + if (pSataChannel->PMSupported == MV_TRUE) + { + _setActivePMPort(pSataChannel, MV_SATA_PM_CONTROL_PORT); + } + _doSoftReset(pSataChannel); +} +static void activateEdma(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_U32 eDmaRegsOffset; + MV_U8 sataUnit; + MV_U8 port; + + ioBaseAddr = pAdapter->adapterIoBaseAddress; + pSataChannel = pAdapter->sataChannel[channelIndex]; + eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: activateEdma\n", pAdapter->adapterId, + channelIndex); + pSataChannel->EdmaActive = MV_TRUE; + sataUnit = (channelIndex & MV_BIT2) >> 2; + port = channelIndex & (MV_BIT0 | MV_BIT1); + /* clear Device interrupt */ + MV_REG_WRITE_DWORD(ioBaseAddr, MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET, + ~((MV_BIT8 | MV_BIT0) << port)); + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + MV_REG_WRITE_DWORD(ioBaseAddr, + pSataChannel->eDmaRegsOffset + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET, 0); + } + else + { + MV_REG_WRITE_DWORD(ioBaseAddr, + pSataChannel->eDmaRegsOffset + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET, MV_BIT8); + } + + if (pSataChannel->FBSEnabled == MV_TRUE) + { + _setRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_CONFIG_REG_OFFSET, MV_BIT16); + } + + /* disable sata device interrupts */ + disableSaDevInterrupts(pAdapter, channelIndex); + + MV_CPU_WRITE_BUFFER_FLUSH(); + + _checkATAStatus(pAdapter, channelIndex); + + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + MV_EDMA_COMMAND_REG_OFFSET, + MV_EDMA_COMMAND_ENABLE_MASK); +} + +static void deactivateEdma(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_U32 eDmaRegsOffset; + MV_U32 counter = 0; + ioBaseAddr = pAdapter->adapterIoBaseAddress; + pSataChannel = pAdapter->sataChannel[channelIndex]; + eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: deactivateEdma\n", pAdapter->adapterId, + channelIndex); + pSataChannel->EdmaActive = MV_FALSE; + + MV_CPU_WRITE_BUFFER_FLUSH(); + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + MV_EDMA_COMMAND_REG_OFFSET, + MV_EDMA_COMMAND_DISABLE_MASK); + while (counter < 1000) + { + if (MV_REG_READ_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_COMMAND_REG_OFFSET) & MV_BIT0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: deactivateEdma: " + "Edma still active. elapsed time %d us\n", pAdapter->adapterId, + channelIndex, counter * 1000); + mvMicroSecondsDelay(pAdapter, 1000); + } + else + { + break; + } + counter++; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: deactivateEdma: " + "Edma status reg 0x%08x\n", pAdapter->adapterId, + channelIndex, MV_REG_READ_DWORD(ioBaseAddr, + eDmaRegsOffset + + MV_EDMA_STATUS_REG_OFFSET)); + if (counter >= 1000) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, + " %d %d: deactivateEdma: Edma Failed (EDMA status = %x)\n", + pAdapter->adapterId, channelIndex, + MV_REG_READ_DWORD(ioBaseAddr, + eDmaRegsOffset + MV_EDMA_STATUS_REG_OFFSET)); + pSataChannel->queueCommandsEnabled = MV_FALSE; + flushDmaQueue (pSataChannel, MV_FLUSH_TYPE_CALLBACK, + MV_COMPLETION_TYPE_ABORT, 0); + resetEdmaChannel(pSataChannel); + mvOsSemRelease(&pSataChannel->semaphore); + pAdapter->mvSataEventNotify(pAdapter, MV_EVENT_TYPE_SATA_ERROR, + MV_SATA_UNRECOVERABLE_COMMUNICATION_ERROR, + channelIndex); + mvOsSemTake(&pSataChannel->semaphore); + } + if (pSataChannel->FBSEnabled == MV_TRUE) + { + _clearRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_CONFIG_REG_OFFSET, MV_BIT16); + } + /*_dumpSataRegs(pAdapter, channelIndex);*/ + enableSaDevInterrupts(pAdapter, channelIndex); +} + +static void EdmaReqQueueInsert(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry, + MV_UDMA_COMMAND_PARAMS *pUdmaParams) +{ + MV_BUS_ADDR_T ioBaseAddr = pSataChannel->mvSataAdapter->adapterIoBaseAddress; + + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_UDMA_COMMAND, " %d %d: Insert Edma " + "Request. PMPort %x host tag = 0x%x device tag = 0x%x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, pCommandEntry->pCommandInfo->PMPort, + pCommandEntry->hostTag, pCommandEntry->deviceTag); + + /* insert the last commmand into the Edma queue */ + if (pSataChannel->mvSataAdapter->sataAdapterGeneration == MV_SATA_GEN_IIE) + { + writeGen2EEdmaRequestEntry (&pSataChannel->requestQueue[pSataChannel->reqInPtr], + pSataChannel, pCommandEntry, pUdmaParams); + } + else + { + writeEdmaRequestEntry (&pSataChannel->requestQueue[pSataChannel->reqInPtr], + pSataChannel, pCommandEntry, pUdmaParams); + } + pSataChannel->reqInPtr++; + pSataChannel->reqInPtr &= pSataChannel->EDMAQueuePtrMask; + pSataChannel->EdmaQueuedCommands++; + pCommandEntry->isCommandInEdma = MV_TRUE; + pCommandEntry->commandAborted = MV_FALSE; + + MV_CPU_WRITE_BUFFER_FLUSH(); + MV_REG_WRITE_DWORD(ioBaseAddr, + pSataChannel->eDmaRegsOffset + + MV_EDMA_REQUEST_Q_INP_REG_OFFSET, + pSataChannel->requestQueuePciLowAddress | + ((pSataChannel->reqInPtr << MV_EDMA_REQUEST_Q_INP_OFFSET) + & pSataChannel->EDMARequestInpMask)); +} + +static MV_VOID _insertQCommandsIntoEdma(MV_SATA_CHANNEL *pSataChannel) +{ + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: _insert" + "QCommandsIntoEdma\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + + if (pSataChannel->commandsQueueHead == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: Commands queue is empty\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + return; + } + if (pSataChannel->commandsQueueHead->pCommandInfo->type == + MV_QUEUED_COMMAND_TYPE_NONE_UDMA) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: Next Command is PIO\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + if (pSataChannel->PMSupported == MV_TRUE) + { + _setActivePMPort(pSataChannel, + pSataChannel->commandsQueueHead->pCommandInfo->PMPort); + } + if (sendNoneUdmaCommand(pSataChannel, + pSataChannel->commandsQueueHead) == MV_FALSE) + { + completePIOCommand(pSataChannel, pSataChannel->commandsQueueHead, + MV_TRUE); + } + + } +#ifdef MV_SUPPORT_ATAPI + + else if (pSataChannel->commandsQueueHead->pCommandInfo->type == + MV_QUEUED_COMMAND_TYPE_PACKET) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: Next Command is Packet\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + if (pSataChannel->PMSupported == MV_TRUE) + { + _setActivePMPort(pSataChannel, + pSataChannel->commandsQueueHead->pCommandInfo->PMPort); + } + if (sendNoneUdmaCommand(pSataChannel, + pSataChannel->commandsQueueHead) == MV_FALSE) + { + completePacketCommand(pSataChannel, pSataChannel->commandsQueueHead, + MV_TRUE); + } + + } +#endif /* MV_SUPPORT_ATAPI */ + else + { + MV_QUEUED_COMMAND_ENTRY *pEntry; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "%d %d: Next Command is UDMA\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + activateEdma(pSataChannel->mvSataAdapter,pSataChannel->channelNumber); + pEntry = pSataChannel->commandsQueueHead; + while ((pEntry != NULL) && + (pEntry->pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_UDMA)) + { + EdmaReqQueueInsert(pSataChannel, pEntry, + &pEntry->pCommandInfo->commandParams.udmaCommand); + pEntry = pEntry->next; + } + + } + +} +/* do device error recovery for PIO, DMA and QUEUED DMA commands (not NCQ)*/ +static MV_BOOLEAN _doDevErrorRecovery(MV_SATA_CHANNEL *pSataChannel) +{ + if ((pSataChannel->mvSataAdapter->sataAdapterGeneration == MV_SATA_GEN_I) || + (pSataChannel->queuedDMA == MV_EDMA_MODE_QUEUED)) + { + if (_doSoftReset(pSataChannel) == MV_FALSE) + { + return MV_FALSE; + } + } + pSataChannel->queueCommandsEnabled = MV_TRUE; + /* Enable the storage device interrupts */ + enableSaDevInterrupts(pSataChannel->mvSataAdapter, + pSataChannel->channelNumber); + _resetEdmaQPointers(pSataChannel); + _insertQCommandsIntoEdma(pSataChannel); + return MV_TRUE; +} +/* this function used for NCQ error handling or FBS mode, it cheks if further commands + expected to be completed successfully (from drives without errors in PM)*/ +static MV_BOOLEAN isGoodCompletionsExpected(MV_SATA_CHANNEL *pSataChannel) +{ + MV_QUEUED_COMMAND_ENTRY *pEntry; + + pEntry = pSataChannel->commandsQueueHead; + while (pEntry != NULL) + { + if (pEntry->isCommandInEdma == MV_TRUE) + { + if (pEntry->commandAborted == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: isGoodCompletionsExpected: command (host tag 0x%02x)" + "(device tag 0x%02x) expected with good completion from port 0x%02x. " + "PortsWithErros= 0x%04x \n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, pEntry->hostTag, + pEntry->deviceTag, + pEntry->pCommandInfo->PMPort, + pSataChannel->ErrorHandlingInfo.PortsWithErrors); + return MV_TRUE; + } + } + else + { + /* stop once reached a command that has not been inserted into the + EDMA since the next commands also must be outside the EDMA + */ + break; + } + pEntry = pEntry->next; + } + + if (pSataChannel->mvSataAdapter->sataAdapterGeneration == MV_SATA_GEN_IIE) + { + if (pSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) + { + MV_U32 EDMAStatus = MV_REG_READ_DWORD( + pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_STATUS_REG_OFFSET); + + /*wait for internal commands cache to be empty */ + if ((EDMAStatus & MV_EDMA_STATUS_ECACHE_EMPTY_BIT) == 0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: isGoodCompletionsExpected: eCache not empty," + " wait for completions with errors\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + return MV_TRUE; + } + if ((EDMAStatus & MV_EDMA_STATUS_EDMA_IDLE_BIT) == 0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: isGoodCompletionsExpected: EDMA is not Idle\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + return MV_TRUE; + } + } + } + /* check for responses*/ + if (pSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) + { + MV_U32 rspInReg = MV_REG_READ_DWORD( + pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_RESPONSE_Q_INP_REG_OFFSET); + MV_U32 rspInPtr = 0; + if (pSataChannel->use128Entries == MV_TRUE) + { + rspInPtr = getRegField(rspInReg, 3, 7); + } + else + { + rspInPtr = getRegField(rspInReg, 3, 5); + } + + + if (pSataChannel->rspOutPtr != rspInPtr) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: isGoodCompletionsExpected: More responses need to be " + "handled, Response In Ptr 0x%x, SW Response Out Ptr 0x%x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + rspInPtr, pSataChannel->rspOutPtr); + return MV_TRUE; + } + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: isGoodCompletionsExpected: No commands expected to be " + "completed. PortrNumDevError 0x%04x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pSataChannel->ErrorHandlingInfo.PortsWithErrors); + return MV_FALSE; +} +/* this function used for NCQ error handling, this function called wheb DevErr + interrupt receivedm it checks which PM ports repored device error and updates + PortsWithErrors varibles +*/ + +static MV_VOID updatePortsWithErrors(MV_SATA_CHANNEL *pSataChannel) +{ + MV_U32 testCtrlReg = MV_REG_READ_DWORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_SATA_II_IF_TEST_CTRL_REG_OFFSET); + testCtrlReg &= 0xFFFF0000; + testCtrlReg = testCtrlReg >> 16; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: updatePortsWithErrors: old val 0x%04x, new 0x%04x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pSataChannel->ErrorHandlingInfo.PortsWithErrors, + pSataChannel->ErrorHandlingInfo.PortsWithErrors | testCtrlReg); + + pSataChannel->ErrorHandlingInfo.PortsWithErrors |= (MV_U16)testCtrlReg; +} +/* this function called when Device Error occures in NCQ mode or FBS mode*/ +/* is detects which outstanding commands (command in the EDMA) are aborted by*/ +/* the drive due to the error, also it resumes the transport layer*/ +static MV_VOID setAbortedCommands(MV_SATA_CHANNEL *pSataChannel) +{ + MV_QUEUED_COMMAND_ENTRY *pEntry; + MV_U32 TCQOutStandingStatus[4] = {0,0,0,0}; + MV_U8 TCQPortWithError = 0; + /*sanity checks*/ + if ((pSataChannel == NULL) || (pSataChannel->EdmaActive == MV_FALSE)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID,MV_DEBUG_FATAL_ERROR, + "setAbortedCommands called in wrong context\n"); + return; + } + if (pSataChannel->FBSEnabled == MV_TRUE) + { + MV_U32 TCQStatus = MV_REG_READ_DWORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_TCQ_STATUS_REG_OFFSET); + + TCQOutStandingStatus[0] = MV_REG_READ_DWORD( + pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_NCQTCQ0_OUTSTANDING_REG_OFFSET); + TCQOutStandingStatus[1] = MV_REG_READ_DWORD( + pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_NCQTCQ1_OUTSTANDING_REG_OFFSET); + TCQOutStandingStatus[2] = MV_REG_READ_DWORD( + pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_NCQTCQ2_OUTSTANDING_REG_OFFSET); + TCQOutStandingStatus[3] = MV_REG_READ_DWORD( + pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_NCQTCQ3_OUTSTANDING_REG_OFFSET); + + { + MV_U32 regVal = MV_REG_READ_DWORD( + pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_SATA_II_IF_STATUS_REG_OFFSET); + + TCQPortWithError = (MV_U8)getRegField(regVal, 8, 4); + } + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: setAbortedCommands: \n" + "TCQPortWithError = 0x%04x \n" + "TCQStatus = 0x%04x \n" + "TCQ0OutStandingStatus = 0x%04x \n" + "TCQ1OutStandingStatus = 0x%04x \n" + "TCQ2OutStandingStatus = 0x%04x \n" + "TCQ3OutStandingStatus = 0x%04x \n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + TCQPortWithError, + TCQStatus, + TCQOutStandingStatus[0], + TCQOutStandingStatus[1], + TCQOutStandingStatus[2], + TCQOutStandingStatus[3]); + /* clear DRQ bit */ + if (TCQStatus & (MV_BIT0 << TCQPortWithError)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: setAbortedCommands Clear TCQ DRQ\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + TCQStatus &= ~(MV_BIT0 << TCQPortWithError); + MV_REG_WRITE_DWORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_TCQ_STATUS_REG_OFFSET, TCQStatus); + } + /* clear SERVICE bit */ + if (TCQStatus & (MV_BIT16 << TCQPortWithError)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: setAbortedCommands Clear TCQ Service\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + TCQStatus &= ~(MV_BIT16 << TCQPortWithError); + MV_REG_WRITE_DWORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_TCQ_STATUS_REG_OFFSET, TCQStatus); + } + /* clear Device errors in EDMA error cause register */ + MV_REG_WRITE_DWORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET,~MV_BIT2); + + /*clear interrupt cause to resume the transport layer operation*/ + MV_REG_WRITE_DWORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_FIS_INTERRUPT_CAUSE_REG_OFFSET, + ~MV_BIT8); + } + pEntry = pSataChannel->commandsQueueHead; + while (pEntry != NULL) + { + if (pEntry->isCommandInEdma == MV_TRUE) + { + if (pSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) + { + if ((((MV_U16)(1 << pEntry->pCommandInfo->PMPort)) & + pSataChannel->ErrorHandlingInfo.PortsWithErrors) != 0) + { + pEntry->commandAborted = MV_TRUE; + } + } + else /*FBS*/ + { + if (pSataChannel->queuedDMA == MV_EDMA_MODE_QUEUED) + { + if (pEntry->pCommandInfo->PMPort == TCQPortWithError) + { + MV_U32 bitmap = (1 << ((MV_U32)pEntry->hostTag)); + MV_U8 reg = (pEntry->hostTag >> 5) & 0x3; + if ((bitmap & TCQOutStandingStatus[reg]) != 0) + { + pEntry->commandAborted = MV_TRUE; + } + } + } + } + if (pEntry->commandAborted == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: command (host tag 0x%02x)" + "(device tag 0x%02x) not expected, port 0x%02x. \n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, pEntry->hostTag, + pEntry->deviceTag, + pEntry->pCommandInfo->PMPort); + } + } + else + { + /* stop once reached a command that has not been inserted into the + EDMA since the next commands also must be outside the EDMA + */ + break; + } + pEntry = pEntry->next; + } +} +/* this function used for NCQ error handling, called when device error received + and no further good complitions expected. it stops the EDMA and starts the + process if sending ReadLogExt commands to the drives that reported device + errors +*/ +static MV_VOID enterRequestSenseState(MV_SATA_CHANNEL *pSataChannel) +{ + MV_U8 ATAstatus; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: enterRequestSenseState: PortsWithErrors 0x%04x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pSataChannel->ErrorHandlingInfo.PortsWithErrors); + /* Fix for 88SX60x1 FEr SATA#25 */ + { + pSataChannel->ErrorHandlingInfo.useVendorUniqGen2WA = MV_FALSE; + if (pSataChannel->mvSataAdapter->sataAdapterGeneration == MV_SATA_GEN_II) + { + MV_U32 EDMAStatus = MV_REG_READ_DWORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_STATUS_REG_OFFSET); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: EDMA state is %x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, EDMAStatus); + + if (getRegField(EDMAStatus, 8, 8) == 0x70) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: EDMA state is 0x70 do WA\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + pSataChannel->ErrorHandlingInfo.useVendorUniqGen2WA = MV_TRUE; + } + } + } + deactivateEdma(pSataChannel->mvSataAdapter, pSataChannel->channelNumber); + if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED) + { + if (pSataChannel->FBSEnabled != MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID,MV_DEBUG_FATAL_ERROR, + "enterRequestSenseState called in wrong context\n"); + return; + } + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: enterRequestSenseState: Finished All erring ports\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + pSataChannel->ErrorHandlingInfo.state = MV_ERROR_HANDLING_STATE_IDLE; + pSataChannel->ErrorHandlingInfo.PortsWithErrors = 0; + _resetEdmaQPointers(pSataChannel); + _insertQCommandsIntoEdma(pSataChannel); + return; + } + + /* clear Device errors in EDMA error cause register due to the aborted + commands*/ + MV_REG_WRITE_DWORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET,~MV_BIT2); + /* the EDMA may be disabled after FPDMA commands issued and before */ + /* receiving response from the drive (D2H Fis), in this case the ATA */ + /* busy bit will be set, so we wait for this bit to be cleared by the */ + /* drive when is sends D2H registers Fis and SaDevInterrupt will be issued*/ + + /* clear SaDevInterrupt if already received*/ + { + MV_U8 port = pSataChannel->channelNumber & (MV_BIT0 | MV_BIT1); + MV_U8 sataUnit = (pSataChannel->channelNumber & MV_BIT2) >> 2; + + MV_REG_WRITE_DWORD(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET, ~(MV_BIT8 << port)); + } + + ATAstatus = MV_REG_READ_BYTE(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + + if (ATAstatus & MV_ATA_BUSY_STATUS) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: ATA Busy" + "bit is set after disabling EDMA, wait for SaDevInterrupt\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + pSataChannel->ErrorHandlingInfo.state = MV_ERROR_HANDLING_STATE_WAIT_FOR_BUSY; + return; + } + pSataChannel->ErrorHandlingInfo.state = MV_ERROR_HANDLING_STATE_REQUEST_SENSE; + pSataChannel->ErrorHandlingInfo.CurrPort = 0; + if (pSataChannel->queuedDMA == MV_EDMA_MODE_QUEUED)/*TCQ*/ + { + softResetErringPorts(pSataChannel); + } + else + { + setReadLogExtCmndPointers(pSataChannel); + handlePortError(pSataChannel); + } +} + + + +/* this function used for NCQ error handling, called from the ReadLogExt command + callback function, it makes sanity checks for the command output and + completes the erring command with the ATA registers values, finally it calls + handlePortError to handle NCQ errors from the next drive if any*/ +static MV_BOOLEAN parseReadLogExtOutPut(MV_SATA_CHANNEL *pSataChannel) +{ + MV_U32 count; + MV_U8 tag; + MV_STORAGE_DEVICE_REGISTERS registerStruct; + MV_QUEUED_COMMAND_ENTRY *pCommandEntry; + + MV_U8_PTR ReadLogExtBuffer = (MV_U8_PTR)pSataChannel->ErrorHandlingInfo.ReadLogExtBuffer; + /* chack CRC*/ + { + MV_U8 crc = 0; + for (count = 0 ; count < ATA_SECTOR_SIZE ; count ++) + { + crc += ReadLogExtBuffer[count]; + } + if (crc != 0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: parseReadLogExtOutPut " + "ATA Command failed due to wrong CRC checksum (%02x)\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber,crc); + return MV_FALSE; + } + } + /* Swap to little endianess */ + for (count = 0 ; count < ATA_SECTOR_SIZE_IN_WORDS; count++) + { + /* CPU to little*/ + pSataChannel->ErrorHandlingInfo.ReadLogExtBuffer[count] = + MV_LE16_TO_CPU(pSataChannel->ErrorHandlingInfo.ReadLogExtBuffer[count]); + } + + for (count = 0; count < 3; count++) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " ReadLogExt: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", + ReadLogExtBuffer[(count * 6) + 0], + ReadLogExtBuffer[(count * 6) + 1], + ReadLogExtBuffer[(count * 6) + 2], + ReadLogExtBuffer[(count * 6) + 3], + ReadLogExtBuffer[(count * 6) + 4], + ReadLogExtBuffer[(count * 6) + 5]); + } + /* check NQ bit*/ + if (ReadLogExtBuffer[0] & MV_BIT7) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: parseReadLogExtOutPut: " + "Error - NQ is set\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + return MV_FALSE; + } + + if (_getHostTagByDeviceTag(pSataChannel, + 0x1F & ReadLogExtBuffer[0], + pSataChannel->ErrorHandlingInfo.CurrPort, + &tag) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d %d: " + "parseReadLogExtOutPut: " + "Error - None Valid device tag (0x%02x)\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pSataChannel->ErrorHandlingInfo.CurrPort, + 0x1F & ReadLogExtBuffer[0]); + return MV_FALSE; + } + pCommandEntry = &pSataChannel->commandsQueue[tag]; + if (pCommandEntry->isFreeEntry == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: parseReadLogExtOutPut: " + "Error - No command with tag (0x%02x) has been issued\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, tag); + return MV_FALSE; + } + if (pCommandEntry->pCommandInfo->PMPort != pSataChannel->ErrorHandlingInfo.CurrPort) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: parseReadLogExtOutPut: " + "Error - command PM Port (0x%02x) and CurrPort (0x%02x) doesn't match\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, pCommandEntry->pCommandInfo->PMPort, + pSataChannel->ErrorHandlingInfo.CurrPort); + return MV_FALSE; + } + if (pCommandEntry->pCommandInfo->type != MV_QUEUED_COMMAND_TYPE_UDMA) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: parseReadLogExtOutPut: " + "Error - command with tag (0x%02x) isn't UDMA command\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, tag); + return MV_FALSE; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: parseReadLogExtOutPut: " + " command tag (0x%02x)\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, tag); + registerStruct.statusRegister = ReadLogExtBuffer[2]; + registerStruct.deviceRegister = ReadLogExtBuffer[7]; + registerStruct.errorRegister = ReadLogExtBuffer[3]; + registerStruct.lbaLowRegister = (ReadLogExtBuffer[8] << 8) | ReadLogExtBuffer[4]; + registerStruct.lbaMidRegister = (ReadLogExtBuffer[9] << 8) | ReadLogExtBuffer[5]; + registerStruct.lbaHighRegister = (ReadLogExtBuffer[10] << 8) | ReadLogExtBuffer[6]; + registerStruct.sectorCountRegister = (ReadLogExtBuffer[13] << 8) | ReadLogExtBuffer[12]; + + _printATARegs(®isterStruct); + + pSataChannel->EdmaQueuedCommands--; + pCommandEntry->pCommandInfo->commandParams.udmaCommand.callBack(pSataChannel->mvSataAdapter, + pSataChannel->channelNumber, + MV_COMPLETION_TYPE_ERROR, + pCommandEntry->pCommandInfo->commandParams.udmaCommand.commandId, + 0x04, + 0, ®isterStruct); + removeCommand(pSataChannel,pCommandEntry); + return MV_TRUE; +} +static MV_BOOLEAN _getHostTagByDeviceTag(MV_SATA_CHANNEL *pSataChannel, + MV_U8 deviceTag, + MV_U8 PMPort, + MV_U8 *pHostTag) +{ + MV_QUEUED_COMMAND_ENTRY *pEntry = pSataChannel->commandsQueueHead; + while (pEntry != NULL) + { + if (pEntry->isCommandInEdma == MV_TRUE) + { + if ((pEntry->deviceTag == deviceTag) && + (pEntry->pCommandInfo->PMPort == PMPort)) + { + *pHostTag = pEntry->hostTag; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%d %d %d: _getHostTagByDeviceTag, command entry found, " + "host tag = 0x%02x, deviceTag(0x%02x)\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + PMPort, + *pHostTag, + deviceTag); + return MV_TRUE; + } + } + else + { + /* stop once reached a command that has not been inserted into the + EDMA since the next commands also must be outside the EDMA + */ + break; + } + pEntry = pEntry->next; + } + return MV_FALSE; +} +/* this function used for NCQ error handling, it's the callback function of the + ReadLogExt command with issued by adding command entry to the channel's + commands queue */ +static MV_BOOLEAN +ReadLogExtCompletionCB(MV_SATA_ADAPTER *pSataAdapter, + MV_U8 channelNum, + MV_COMPLETION_TYPE comp_type, + MV_VOID_PTR commandId, + MV_U16 responseFlags, + MV_U32 timeStamp, + MV_STORAGE_DEVICE_REGISTERS *registerStruct) +{ + MV_SATA_CHANNEL *pSataChannel = pSataAdapter->sataChannel[channelNum]; + + switch (comp_type) + { + case MV_COMPLETION_TYPE_NORMAL: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: ReadLogExtCompletionCB: Normal completion. Port 0x%02x\n", + pSataAdapter->adapterId, channelNum, + pSataChannel->ErrorHandlingInfo.CurrPort); + if (parseReadLogExtOutPut(pSataChannel) == MV_TRUE) + { + /* Fix for 88SX60x1 FEr SATA#25 */ + { + if (pSataChannel->ErrorHandlingInfo.useVendorUniqGen2WA == MV_TRUE) + { + MV_U32 i; + MV_U8 ATAstatus; + _doSoftReset(pSataChannel); + for (i = 0;i < 31000; i++) + { + ATAstatus = MV_REG_READ_BYTE(pSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if ((ATAstatus & MV_ATA_BUSY_STATUS) == 0) + { + break; + } + mvMicroSecondsDelay(pSataChannel->mvSataAdapter, 1000); + } + } + } + pSataChannel->ErrorHandlingInfo.CurrPort++; + handlePortError(pSataChannel); + } + break; + default: + /* when ReadLogExt fails or parseReaDLogExtOutPut fails do nothing*/ + /* the higher layers will not have the queued commands completed so it*/ + /* should recover this situation by it's timeout error recovery*/ + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: ReadLogExtCompletionCB: Bad completion. Port 0x%02x\n", + pSataAdapter->adapterId, channelNum, + pSataChannel->ErrorHandlingInfo.CurrPort); + _printATARegs(registerStruct); + _dumpSataRegs(pSataAdapter, channelNum); + break; + } + return MV_TRUE; +} +/* this function used for NCQ error handling, it "allocates" command entry of the + ReadLogExt command and data buffer used for that command from the EDMA + requests queue which is not used meanwhile since the EDMA disabled*/ +static MV_VOID setReadLogExtCmndPointers(MV_SATA_CHANNEL *pSataChannel) +{ + struct ReadLogExtBuffers + { + MV_QUEUED_COMMAND_ENTRY entry; +#ifdef MV_SATA_STORE_COMMANDS_INFO_ON_IAL_STACK + MV_QUEUE_COMMAND_INFO commandInfo; +#endif + MV_U16 pioBuffer[ATA_SECTOR_SIZE_IN_WORDS]; + }; + /* EDMA is not active, so we use the request queue buffer for Read Log Ext + command data */ + struct ReadLogExtBuffers *pReadLogExtBuffers = + (struct ReadLogExtBuffers *)pSataChannel->requestQueue; + pSataChannel->ErrorHandlingInfo.pReadLogExtEntry = &pReadLogExtBuffers->entry; + pSataChannel->ErrorHandlingInfo.ReadLogExtBuffer = pReadLogExtBuffers->pioBuffer; + +#ifdef MV_SATA_STORE_COMMANDS_INFO_ON_IAL_STACK + pSataChannel->ErrorHandlingInfo.pReadLogExtEntry->pCommandInfo = + &pReadLogExtBuffers->commandInfo; +#else + pSataChannel->ErrorHandlingInfo.pReadLogExtEntry->pCommandInfo = + &pReadLogExtBuffers->entry.commandInfo; +#endif +} +/* this function used for NCQ error handling, it sets the ReadLogExt command + entry, then issues the command to the CuttPort*/ +static MV_VOID insertReadLogExtCmnd(MV_SATA_CHANNEL *pSataChannel) +{ + MV_QUEUED_COMMAND_ENTRY *pEntry = pSataChannel->ErrorHandlingInfo.pReadLogExtEntry; + MV_NONE_UDMA_COMMAND_PARAMS *pReadLogExtPIOParams = + &pEntry->pCommandInfo->commandParams.NoneUdmaCommand; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: insertReadLogExtCmnd: Port 0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pSataChannel->ErrorHandlingInfo.CurrPort); + + pReadLogExtPIOParams->bufPtr = pSataChannel->ErrorHandlingInfo.ReadLogExtBuffer; + pReadLogExtPIOParams->callBack = ReadLogExtCompletionCB; + pReadLogExtPIOParams->command = MV_ATA_COMMAND_READ_LOG_EXT; + pReadLogExtPIOParams->commandId = NULL; + pReadLogExtPIOParams->count = ATA_SECTOR_SIZE_IN_WORDS; + pReadLogExtPIOParams->device = 0; + pReadLogExtPIOParams->features = 0; + pReadLogExtPIOParams->isEXT = MV_TRUE; + pReadLogExtPIOParams->lbaHigh = 0; + pReadLogExtPIOParams->lbaLow = 0x10; + pReadLogExtPIOParams->lbaMid = 0; + pReadLogExtPIOParams->protocolType = MV_NON_UDMA_PROTOCOL_PIO_DATA_IN; + pReadLogExtPIOParams->sectorCount = 1; + pEntry->pCommandInfo->type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; + pEntry->pCommandInfo->PMPort = pSataChannel->ErrorHandlingInfo.CurrPort; + pEntry->isCommandInEdma = MV_FALSE; + pEntry->commandAborted = MV_FALSE; + pEntry->isFreeEntry = MV_FALSE; + pEntry->hostTag = 0xFF; + pEntry->deviceTag = 0xFF; + commandsQueueAddHead(pSataChannel, pEntry); + if (pSataChannel->PMSupported == MV_TRUE) + { + _setActivePMPort(pSataChannel, pEntry->pCommandInfo->PMPort); + + } + /* Fix for 88SX60x1 FEr SATA#25 */ + if (pSataChannel->ErrorHandlingInfo.useVendorUniqGen2WA == MV_TRUE) + { + MV_U32 FISBuffer[5]; + FISBuffer[0] = ((MV_ATA_COMMAND_READ_LOG_EXT << 16)& 0xFF0000) | + MV_BIT15 | 0x27; + FISBuffer[1] = 0x10; + FISBuffer[2] = 0; + FISBuffer[3] = 1; + FISBuffer[4] = 0; + + sendVendorUniqueFIS(pSataChannel->mvSataAdapter, + pSataChannel->channelNumber, + FISBuffer, 5); + + return; + } + + if (sendNoneUdmaCommand(pSataChannel, pEntry) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: Failed to " + "Issue ReadLogExt PIO command\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + completePIOCommand(pSataChannel, pSataChannel->commandsQueueHead, + MV_TRUE); + } +} +/* this function used for NCQ error handling, it checks the comming port + that experienced NCQ device error starting from CurrPort, if no port found, + it sets the NCQ error handling state to the Idle state and re-queues the + outstanding commands*/ +static MV_VOID handlePortError(MV_SATA_CHANNEL *pSataChannel) +{ + while (pSataChannel->ErrorHandlingInfo.CurrPort <= MV_SATA_PM_MAX_PORTS) + { + if (((MV_U16)( 1 << pSataChannel->ErrorHandlingInfo.CurrPort)) & pSataChannel->ErrorHandlingInfo.PortsWithErrors) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: handlePortError: Device Error found on Port " + "0x%02x\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pSataChannel->ErrorHandlingInfo.CurrPort); + break; + } + pSataChannel->ErrorHandlingInfo.CurrPort++; + } + if (pSataChannel->ErrorHandlingInfo.CurrPort > MV_SATA_PM_MAX_PORTS) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: handlePortError: Finished All erring ports\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + pSataChannel->ErrorHandlingInfo.state = MV_ERROR_HANDLING_STATE_IDLE; + pSataChannel->ErrorHandlingInfo.PortsWithErrors = 0; + _resetEdmaQPointers(pSataChannel); + _insertQCommandsIntoEdma(pSataChannel); + return; + } + insertReadLogExtCmnd(pSataChannel); +} +static MV_VOID softResetErringPorts(MV_SATA_CHANNEL *pSataChannel) +{ + while (pSataChannel->ErrorHandlingInfo.CurrPort <= MV_SATA_PM_MAX_PORTS) + { + if (((MV_U16)( 1 << pSataChannel->ErrorHandlingInfo.CurrPort)) & pSataChannel->ErrorHandlingInfo.PortsWithErrors) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: softResetErringPorts: Device Error found on Port " + "0x%02x\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + pSataChannel->ErrorHandlingInfo.CurrPort); + if (pSataChannel->PMSupported == MV_TRUE) + { + _setActivePMPort(pSataChannel, + pSataChannel->ErrorHandlingInfo.CurrPort); + + } + _doSoftReset(pSataChannel); + } + pSataChannel->ErrorHandlingInfo.CurrPort++; + } + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: softResetErringPorts: Finished All erring ports\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + pSataChannel->ErrorHandlingInfo.state = MV_ERROR_HANDLING_STATE_IDLE; + pSataChannel->ErrorHandlingInfo.PortsWithErrors = 0; + _resetEdmaQPointers(pSataChannel); + _insertQCommandsIntoEdma(pSataChannel); + return; +} +static MV_BOOLEAN sendNoneUdmaCommand(MV_SATA_CHANNEL *pSataChannel, + MV_QUEUED_COMMAND_ENTRY *pCommandEntry) +{ + MV_NONE_UDMA_COMMAND_PARAMS *pParams = + &pCommandEntry->pCommandInfo->commandParams.NoneUdmaCommand; + MV_BUS_ADDR_T ioBaseAddr = pSataChannel->mvSataAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset; + MV_U8 ATAstatus; + unsigned int i; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + " %d %d Issue NON UDMA command: protocol(%d) buff %p , words %x ," + " features %x , sector count %x , lba %x.%x.%x device %x " + "command=%x\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, pParams->protocolType, + pParams->bufPtr, pParams->count, + pParams->features, pParams->sectorCount, + pParams->lbaLow, pParams->lbaMid, + pParams->lbaHigh, pParams->device, + pParams->command); + + eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if ((ATAstatus & (MV_ATA_READY_STATUS | MV_ATA_BUSY_STATUS)) != + MV_ATA_READY_STATUS) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: storage drive is not" + " ready, ATA STATUS=0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus); + return MV_FALSE; + } + + if(pCommandEntry->pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_PACKET) + { + if(pParams->protocolType == MV_NON_UDMA_PROTOCOL_PACKET_DMA) + { + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_FEATURES_REG_OFFSET, MV_BIT0); + } + else + { + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_FEATURES_REG_OFFSET, 0); + } + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET, 0); + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_LOW_REG_OFFSET, 0); + + /* set byte count limit to 8KB (0x2000)*/ + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_MID_REG_OFFSET, 0x00); + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET, 0x20); + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_HEAD_REG_OFFSET, 0); + MV_CPU_WRITE_BUFFER_FLUSH(); + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_COMMAND_REG_OFFSET,MV_ATA_COMMAND_PACKET ); + + } + else + { + if (pParams->isEXT == MV_TRUE) + { + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_FEATURES_REG_OFFSET, + (pParams->features & 0xff00) >> 8); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET, + (pParams->sectorCount & 0xff00) >> 8); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_LOW_REG_OFFSET, + (pParams->lbaLow & 0xff00) >> 8); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_MID_REG_OFFSET, + (pParams->lbaMid & 0xff00) >> 8); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET, + (pParams->lbaHigh & 0xff00) >> 8); + } + else + { + if ((pParams->features & 0xff00) || + (pParams->sectorCount & 0xff00) || + (pParams->lbaLow & 0xff00) || + (pParams->lbaMid & 0xff00) || + (pParams->lbaHigh & 0xff00)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR | MV_DEBUG_NON_UDMA_COMMAND, + " %d %d :in Issue NON UDMA command:" + " bits[15:8] of register values should be reserved" + " Features 0x%02x, SectorCount 0x%02x, LBA Low 0x%02x," + " LBA Mid 0x%02x, LBA High 0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, pParams->features, + pParams->sectorCount, pParams->lbaLow, + pParams->lbaMid, pParams->lbaHigh); + return MV_FALSE; + } + } + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_FEATURES_REG_OFFSET, pParams->features & 0xff); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET, pParams->sectorCount & 0xff); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_LOW_REG_OFFSET, pParams->lbaLow & 0xff); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_MID_REG_OFFSET, pParams->lbaMid & 0xff); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET, pParams->lbaHigh & 0xff); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_HEAD_REG_OFFSET, pParams->device); + + MV_CPU_WRITE_BUFFER_FLUSH(); + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_COMMAND_REG_OFFSET, pParams->command); + } + if ((pParams->protocolType == MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT) || + (pCommandEntry->pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_PACKET)) + { + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_ALTERNATE_REG_OFFSET); + + /* Wait for the command to complete */ + if (waitWhileStorageDevIsBusy(pSataChannel->mvSataAdapter, + ioBaseAddr, eDmaRegsOffset, 10000, 100) == + MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: in Issue PIO " + "DATA-OUT command: disk not ready.\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + return MV_FALSE; + } + + if (pSataChannel->mvSataAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + + if (waitForDRQ(pSataChannel->mvSataAdapter, ioBaseAddr, eDmaRegsOffset, 500, 10000) + == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: DRQ bit in ATA STATUS" + " register is not set\n", pSataChannel->mvSataAdapter->adapterId, pSataChannel->channelNumber); + return MV_FALSE; + } + } + /* Check the status register on DATA request commands */ + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if ((ATAstatus & (MV_ATA_DATA_REQUEST_STATUS | MV_ATA_BUSY_STATUS | MV_ATA_ERROR_STATUS)) != + MV_ATA_DATA_REQUEST_STATUS) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: in Issue PIO " + "DATA-OUT command: Bad ATA STATUS:0x%02x.\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus); + return MV_FALSE; + } + + if (pSataChannel->mvSataAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + /* Perform a dummy read */ + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + mvMicroSecondsDelay (pSataChannel->mvSataAdapter, 1); + } +#ifdef MV_SUPPORT_ATAPI + if(pCommandEntry->pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_PACKET) + { + MV_PACKET_COMMAND_PARAMS *pParams = + &pCommandEntry->pCommandInfo->commandParams.packetCommand; + for (i = 0; i < pParams->cdb_len ; i++) + { + MV_REG_WRITE_WORD(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET, + MV_CPU_TO_LE16(pParams->cdb_buffer[i])); + } + for(; i < 6; i++) + { + MV_REG_WRITE_WORD(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET, + 0); + + } + MV_CPU_WRITE_BUFFER_FLUSH(); + pSataChannel->waitForBMDMA = MV_FALSE; + if(pParams->protocolType == MV_NON_UDMA_PROTOCOL_PACKET_DMA) + { + activateBMDmaMode(pSataChannel->mvSataAdapter, + pSataChannel->channelNumber, + pParams->prdHighAddr, + pParams->prdLowAddr, + (pParams->flags & MV_BIT0) ? MV_UDMA_TYPE_WRITE: MV_UDMA_TYPE_READ); + + } + return MV_TRUE; + } +#endif + for (i = 0; i < ATA_SECTOR_SIZE_IN_WORDS; i++) + { + MV_REG_WRITE_WORD(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET, + *pParams->bufPtr++); + MV_CPU_WRITE_BUFFER_FLUSH(); + } + pParams->count -= ATA_SECTOR_SIZE_IN_WORDS; +#ifdef MV_SATA_SUPPORT_READ_WRITE_LONG + + /* for Write long only*/ + if (pParams->count == 4) + { + if (pSataChannel->mvSataAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + /* Perform a dummy read */ + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + mvMicroSecondsDelay (pSataChannel->mvSataAdapter, 1); + } + if (waitWhileStorageDevIsBusy(pSataChannel->mvSataAdapter, + ioBaseAddr, eDmaRegsOffset, + 50000, 100) == MV_FALSE) + { + return MV_FALSE; + } + if (pSataChannel->mvSataAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + if (waitForDRQ(pSataChannel->mvSataAdapter, ioBaseAddr, eDmaRegsOffset, 50000, 100) + == MV_FALSE) + { + return MV_FALSE; + } + } + for (i = 0; i < 4; i++) + { + MV_REG_WRITE_WORD(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET, + *pParams->bufPtr++); + MV_CPU_WRITE_BUFFER_FLUSH(); + + + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: Write Long ECC data" + " xfered. ATA STATUS:0x%02x.\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus); + } + pParams->count -= 4; + } +#endif /*MV_SATA_SUPPORT_READ_WRITE_LONG*/ + } + return MV_TRUE; +} + +/* SATA Core API functions */ + +/******************************************************************************* +* mvSataInitAdapter - initialize MV88SX50XX adapter +* +* DESCRIPTION: +* this function initializes glabal registers that concerns PCI access +* and Interrupts. +* +* INPUT: +* *pAdapter - pointer to the adapter data structure. +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* +* COMMENTS: +* The adapter will not be able yet to generate interrupts +* +*******************************************************************************/ +MV_BOOLEAN mvSataInitAdapter (MV_SATA_ADAPTER *pAdapter) +{ + MV_U8 sataUnit; + MV_U8 channelIndex; + MV_U32 regVal; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " : mvSataInitAdapter" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + + if (mvOsSemInit(&pAdapter->semaphore) == MV_FALSE) + { + return MV_FALSE; + } + + if (mvOsSemInit(&pAdapter->interruptsMaskSem) == MV_FALSE) + { + return MV_FALSE; + } +#ifdef MV_SATA_IO_GRANULARITY + if (mvOsSemInit(&pAdapter->iogSemaphore) == MV_FALSE) + { + return MV_FALSE; + } +#endif + + if (pAdapter->mvSataEventNotify == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d : Bad pointer for " + "mvSataEventNotify function\n", pAdapter->adapterId); + return MV_FALSE; + } + + /* Initialize the hardware workarounds to false, and to 8 channels */ + pAdapter->chipIs50XXB0 = MV_FALSE; + pAdapter->chipIs50XXB2 = MV_FALSE; + pAdapter->chipIs60X1B2 = MV_FALSE; + pAdapter->chipIs60X1C0 = MV_FALSE; + pAdapter->chipIs62X1Z0 = MV_FALSE; + pAdapter->numberOfChannels = MV_SATA_CHANNELS_NUM; + pAdapter->numberOfUnits = MV_SATA_UNITS_NUM; + pAdapter->portsPerUnit = MV_SATA_PORT_PER_UNIT; + pAdapter->hostInterface = MV_HOST_IF_PCI; + pAdapter->mainMaskOffset = MV_MAIN_INTERRUPT_MASK_REG_OFFSET; + pAdapter->mainCauseOffset = MV_MAIN_INTERRUPT_CAUSE_REG_OFFSET; + switch (pAdapter->pciConfigDeviceId) + { + case MV_SATA_DEVICE_ID_5080 : + pAdapter->sataAdapterGeneration = MV_SATA_GEN_I; + switch (pAdapter->pciConfigRevisionId) + { + case 0x1: + pAdapter->chipIs50XXB0 = MV_TRUE; + break; + case 0x3: + pAdapter->chipIs50XXB2 = MV_TRUE; + break; + default: + if (pAdapter->pciConfigRevisionId > 0x3) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d : Warning: Future revision ID %02x for Device " + "ID %02x. Implementing latest workarounds\n", + pAdapter->adapterId, pAdapter->pciConfigRevisionId, + pAdapter->pciConfigDeviceId); + pAdapter->chipIs50XXB2 = MV_TRUE; + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d : Bad revision ID %02x for Device ID %02x\n", + pAdapter->adapterId, pAdapter->pciConfigRevisionId, + pAdapter->pciConfigDeviceId); + return MV_FALSE; + } + } + break; + case MV_SATA_DEVICE_ID_5041 : + case MV_SATA_DEVICE_ID_5040 : + pAdapter->numberOfChannels = MV_SATA_PORT_PER_UNIT; + pAdapter->numberOfUnits = 1; + case MV_SATA_DEVICE_ID_5081 : + pAdapter->sataAdapterGeneration = MV_SATA_GEN_I; + switch (pAdapter->pciConfigRevisionId) + { + case 0x0: + pAdapter->chipIs50XXB0 = MV_TRUE; + break; + case 0x3: + pAdapter->chipIs50XXB2 = MV_TRUE; + break; + default: + if (pAdapter->pciConfigRevisionId > 0x3) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d : Warning: Future revis" + "ion ID %02x. Implementing latest workarounds\n", + pAdapter->adapterId, pAdapter->pciConfigRevisionId); + pAdapter->chipIs50XXB2 = MV_TRUE; + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d : Bad revisi" + "on ID %02x\n", pAdapter->adapterId, + pAdapter->pciConfigRevisionId); + return MV_FALSE; + } + } + break; + case MV_SATA_DEVICE_ID_6041 : + pAdapter->numberOfChannels = MV_SATA_PORT_PER_UNIT; + pAdapter->numberOfUnits = 1; + case MV_SATA_DEVICE_ID_6081 : + pAdapter->sataAdapterGeneration = MV_SATA_GEN_II; + switch (pAdapter->pciConfigRevisionId) + { + case 0x7:/*B2*/ + pAdapter->chipIs60X1B2 = MV_TRUE; + break; + case 0x9:/*C0*/ + pAdapter->chipIs60X1C0 = MV_TRUE; + break; + default: + if (pAdapter->pciConfigRevisionId > 0x9) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d : Warning:" + " Future revision ID %02x. Implementing latest " + "workarounds\n", pAdapter->adapterId, + pAdapter->pciConfigRevisionId); + pAdapter->chipIs60X1C0 = MV_TRUE; + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d : Device %02x Bad revision ID %02x\n", + pAdapter->adapterId, + pAdapter->pciConfigDeviceId, + pAdapter->pciConfigRevisionId); + return MV_FALSE; + } + } + break; + case MV_SATA_DEVICE_ID_7042 : + pAdapter->hostInterface = MV_HOST_IF_PEX; + case MV_SATA_DEVICE_ID_6042 : + pAdapter->numberOfChannels = MV_SATA_PORT_PER_UNIT; + pAdapter->numberOfUnits = 1; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + switch (pAdapter->pciConfigRevisionId) + { + case 0x2:/*B0*/ + pAdapter->chipIs60X1C0 = MV_TRUE; + break; + default: + if (pAdapter->pciConfigRevisionId > 0x2) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d : Warning:" + " Future revision ID %02x for Device %02x." + " Implementing latest workarounds\n", + pAdapter->adapterId, + pAdapter->pciConfigRevisionId, + pAdapter->pciConfigDeviceId); + pAdapter->chipIs60X1C0 = MV_TRUE; + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d : Device %02x Bad revision ID %02x\n", + pAdapter->adapterId, + pAdapter->pciConfigDeviceId, + pAdapter->pciConfigRevisionId); + return MV_FALSE; + } + } + break; + + case MV_SATA_DEVICE_ID_5182: + pAdapter->numberOfChannels = MV_SATA_5182_PORT_NUM; + pAdapter->numberOfUnits = 1; + pAdapter->portsPerUnit = MV_SATA_5182_PORT_NUM; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + /*The integrated sata core chip based on 60x1 C0*/ + pAdapter->chipIs60X1C0 = MV_TRUE; + pAdapter->hostInterface = MV_HOST_IF_INTEGRATED; + pAdapter->mainMaskOffset = 0x20024; /*the iobaseaddress is 0x60000*/ + pAdapter->mainCauseOffset = 0x20020; + break; + + case MV_SATA_DEVICE_ID_5082: + pAdapter->numberOfChannels = MV_SATA_5082_PORT_NUM; + pAdapter->numberOfUnits = 1; + pAdapter->portsPerUnit = MV_SATA_5082_PORT_NUM; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + /*The integrated sata core chip based on 60x1 C0*/ + pAdapter->chipIs60X1C0 = MV_TRUE; + pAdapter->hostInterface = MV_HOST_IF_INTEGRATED; + pAdapter->mainMaskOffset = 0x20024; /*the iobaseaddress is 0x60000*/ + pAdapter->mainCauseOffset = 0x20020; + mvSataChannelPhyShutdown(pAdapter, 1); + break; + + case MV_SATA_DEVICE_ID_6082: + pAdapter->numberOfChannels = MV_SATA_6082_PORT_NUM; + pAdapter->numberOfUnits = 1; + pAdapter->portsPerUnit = MV_SATA_6082_PORT_NUM; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + /*The integrated sata core chip based on 60x1 C0*/ + pAdapter->chipIs60X1C0 = MV_TRUE; + pAdapter->hostInterface = MV_HOST_IF_INTEGRATED; + pAdapter->mainMaskOffset = 0x20024; /*the iobaseaddress is 0x40000*/ + pAdapter->mainCauseOffset = 0x20020; + break; + + case MV_SATA_DEVICE_ID_6490: + pAdapter->numberOfChannels = MV_SATA_6490_PORT_NUM; + pAdapter->numberOfUnits = 1; + pAdapter->portsPerUnit = MV_SATA_6490_PORT_NUM; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + /*The integrated sata core chip based on 60x1 C0*/ + pAdapter->chipIs60X1C0 = MV_TRUE; + pAdapter->hostInterface = MV_HOST_IF_INTEGRATED; + pAdapter->mainMaskOffset = 0x20024; + pAdapter->mainCauseOffset = 0x20020; + + /* enable swap DMA Data, EDMA descriptors and PRD tables to keep the data layout + * as in the PCI adapters + */ + _clearRegBits(pAdapter->adapterIoBaseAddress, + MV_SATAHC_0_REGS_BASE_OFFSET, + MV_BIT10 | MV_BIT9 | MV_BIT8); + + break; + case MV_SATA_DEVICE_ID_78XX0: + case MV_SATA_DEVICE_ID_78100: + case MV_SATA_DEVICE_ID_78200: + pAdapter->numberOfChannels = MV_SATA_78XX0_PORT_NUM; + pAdapter->numberOfUnits = 1; + pAdapter->portsPerUnit = MV_SATA_78XX0_PORT_NUM; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + /*The integrated sata core chip based on 60x1 C0*/ + pAdapter->hostInterface = MV_HOST_IF_INTEGRATED; + pAdapter->mainMaskOffset = 0x20024; + pAdapter->mainCauseOffset = 0x20020; + pAdapter->chipIs62X1Z0 = MV_TRUE; + break; + case MV_SATA_DEVICE_ID_76100: + pAdapter->numberOfChannels = MV_SATA_76100_PORT_NUM; + pAdapter->numberOfUnits = 1; + pAdapter->portsPerUnit = MV_SATA_76100_PORT_NUM; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + /*The integrated sata core chip based on 60x1 C0*/ + pAdapter->hostInterface = MV_HOST_IF_INTEGRATED; + pAdapter->mainMaskOffset = 0x20024; + pAdapter->mainCauseOffset = 0x20020; + pAdapter->chipIs62X1Z0 = MV_TRUE; + break; + case MV_SATA_DEVICE_ID_6323: + pAdapter->numberOfChannels = MV_SATA_6323_PORT_NUM; + pAdapter->numberOfUnits = 1; + pAdapter->portsPerUnit = MV_SATA_6323_PORT_NUM; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + /*The integrated sata core chip based on 60x1 C0*/ + pAdapter->hostInterface = MV_HOST_IF_INTEGRATED; + pAdapter->mainMaskOffset = 0x20024; + pAdapter->mainCauseOffset = 0x20020; + pAdapter->chipIs62X1Z0 = MV_TRUE; + break; + + case MV_SATA_DEVICE_ID_6281: + pAdapter->numberOfChannels = MV_SATA_6281_PORT_NUM; + pAdapter->numberOfUnits = 1; + pAdapter->portsPerUnit = MV_SATA_6281_PORT_NUM; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + /*The integrated sata core chip based on 60x1 C0*/ + pAdapter->hostInterface = MV_HOST_IF_INTEGRATED; + pAdapter->mainMaskOffset = 0x20024; + pAdapter->mainCauseOffset = 0x20020; + pAdapter->chipIs62X1Z0 = MV_TRUE; + break; + case MV_SATA_DEVICE_ID_6282: + pAdapter->numberOfChannels = MV_SATA_6282_PORT_NUM; + pAdapter->numberOfUnits = 1; + pAdapter->portsPerUnit = MV_SATA_6282_PORT_NUM; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + /*The integrated sata core chip based on 60x1 C0*/ + pAdapter->hostInterface = MV_HOST_IF_INTEGRATED; + pAdapter->mainMaskOffset = 0x20024; + pAdapter->mainCauseOffset = 0x20020; + pAdapter->chipIs62X1Z0 = MV_TRUE; + break; + case MV_SATA_DEVICE_ID_6192: + pAdapter->numberOfChannels = MV_SATA_6192_PORT_NUM; + pAdapter->numberOfUnits = 1; + pAdapter->portsPerUnit = MV_SATA_6192_PORT_NUM; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + /*The integrated sata core chip based on 60x1 C0*/ + pAdapter->hostInterface = MV_HOST_IF_INTEGRATED; + pAdapter->mainMaskOffset = 0x20024; + pAdapter->mainCauseOffset = 0x20020; + pAdapter->chipIs62X1Z0 = MV_TRUE; + break; + case MV_SATA_DEVICE_ID_6190: + pAdapter->numberOfChannels = MV_SATA_6190_PORT_NUM; + pAdapter->numberOfUnits = 1; + pAdapter->portsPerUnit = MV_SATA_6190_PORT_NUM; + pAdapter->sataAdapterGeneration = MV_SATA_GEN_IIE; + /*The integrated sata core chip based on 60x1 C0*/ + pAdapter->hostInterface = MV_HOST_IF_INTEGRATED; + pAdapter->mainMaskOffset = 0x20024; + pAdapter->mainCauseOffset = 0x20020; + pAdapter->chipIs62X1Z0 = MV_TRUE; + break; + + default: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d : Bad device ID" + " 0x%04x\n", pAdapter->adapterId, + pAdapter->pciConfigDeviceId); + return MV_FALSE; + } + + /* Clear main mask register to prevent adapter from generating interrupts */ + pAdapter->mainMask = 0; + pAdapter->interruptsAreMasked = MV_TRUE; + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, pAdapter->mainMask); + + /* + * Save the PRE and AMP in the adapter. Also set staggared spin up to be + * disabled on default (60x1 only). + */ + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d : Saving PRE and AMP values\n", + pAdapter->adapterId); + for (channelIndex = 0; channelIndex < pAdapter->numberOfChannels; channelIndex++) + { + MV_U32 PHYModeRegister; + pAdapter->staggaredSpinup[channelIndex] = MV_FALSE; + pAdapter->ifSpeed[channelIndex] = MV_SATA_IF_SPEED_NO_LIMIT; + pAdapter->ifPowerState[channelIndex] = MV_SATA_IF_POWER_PHY_READY; + pAdapter->limitInterfaceSpeed[channelIndex] = MV_FALSE; + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + PHYModeRegister = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET((channelIndex & MV_BIT2) >> 2) + + MV_SATA_I_HC_PHY_MODE_BRIDGE_PORT_REG_OFFSET(channelIndex & (MV_BIT0 | MV_BIT1))); + pAdapter->signalAmps[channelIndex] = (MV_U8)((PHYModeRegister & MV_SATA_I_PHY_MODE_AMP_MASK) >> MV_SATA_I_PHY_MODE_AMP_OFFSET); + pAdapter->pre[channelIndex] = (MV_U8)((PHYModeRegister & MV_SATA_I_PHY_MODE_PRE_MASK) >> MV_SATA_I_PHY_MODE_PRE_OFFSET); + } + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + /* + * Check if TWSI serial ROM initialization was triggered. + * If so, then PRE/AMP configuration probably are set after + * reset by serial ROM. If not then override the PRE/AMP + * values. + */ + if ((pAdapter->hostInterface != MV_HOST_IF_INTEGRATED) && + ((MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, MV_RESET_CONFIG_REG_OFFSET)) + & MV_RESET_CONFIG_TWSI_INIT_MASK)) + { + + MV_U32 phyMode2Offset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_PHY_MODE_2_REG_OFFSET; + /* Make sure EDMA is off */ + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_EDMA_COMMAND_REG_OFFSET, + MV_EDMA_COMMAND_DISABLE_MASK); + MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_EDMA_COMMAND_REG_OFFSET); + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + phyMode2Offset); + pAdapter->signalAmps[channelIndex] = + (MV_U8)((regVal & MV_SATA_II_PHY_MODE_2_AMP_MASK) >> + MV_SATA_II_PHY_MODE_2_AMP_OFFSET); + pAdapter->pre[channelIndex] = + (MV_U8)((regVal & MV_SATA_II_PHY_MODE_2_PRE_MASK) >> + MV_SATA_II_PHY_MODE_2_PRE_OFFSET); + } + else + { + pAdapter->signalAmps[channelIndex] = 0x7; + pAdapter->pre[channelIndex] = 0x1; + } + } + } +#ifndef MV_NO_SW_RESET_FOR_THE_ADAPTER + /* Revert the registers to it's default value (software reset) */ + revertSataHCRegs (pAdapter); + + if (pAdapter->hostInterface != MV_HOST_IF_INTEGRATED) + { + revertFlashInterfaceRegs (pAdapter); + } + + if (pAdapter->hostInterface == MV_HOST_IF_PEX) + { + revertPEXInterfaceRegs(pAdapter); + } + else if (pAdapter->hostInterface == MV_HOST_IF_PCI) + { + revertPCIInterfaceRegs(pAdapter); + } +#endif + + /* Enable the SATA LEDs if the silicon revision is B0 */ + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d : Enabling SATA LEDS\n", + pAdapter->adapterId); + /* Enable the SATA leds */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET, 0x0); + if (pAdapter->chipIs50XXB2 == MV_TRUE) + { + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET); + for (channelIndex = 0 ; channelIndex < pAdapter->numberOfChannels ; + channelIndex ++) + { + if (mvSataIsStorageDeviceConnected (pAdapter,channelIndex, NULL) == MV_FALSE) + { + regVal |= (MV_BIT8 << channelIndex); + } + } + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET, + regVal); + } + /* disable Flash controller clock*/ + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET); + + regVal &= ~(MV_BIT0); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + MV_PCI_EXPANSION_ROM_CONTROL_REG_OFFSET, + regVal); + } + + /* Enable the SATA LEDs for 88SX60X1 devices */ + if ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && + (pAdapter->hostInterface != MV_HOST_IF_INTEGRATED)) + + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d : Enabling SATA LEDS\n", + pAdapter->adapterId); + /* Enable the SATA leds */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_FLASH_GPIO_PORT_CONTROL_OFFSET, 0x00000060); + + } + + /* Check if working in PCI-X mode, then disable all conventional PCI */ + /* features */ + if (pAdapter->hostInterface == MV_HOST_IF_PCI) + { + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + MV_PCI_MODE_REG_OFFSET); + if (((regVal & MV_PCI_MODE_MASK) >> MV_PCI_MODE_OFFSET) != 0) /* PCI-X */ + { + if (pAdapter->pciCommand & MV_PCI_COMMAND_PCI_CONVENTIONAL_ONLY) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d : disable pci conventio" + "nal features when working in PCI-X. pciCommand origin" + "al value:0x%08x. new value: 0x%08x.\n", + pAdapter->adapterId, + pAdapter->pciCommand, pAdapter->pciCommand & + (~MV_PCI_COMMAND_PCI_CONVENTIONAL_ONLY)); + pAdapter->pciCommand &= ~MV_PCI_COMMAND_PCI_CONVENTIONAL_ONLY; + } + if ((pAdapter->chipIs50XXB0 == MV_TRUE) || + (pAdapter->chipIs50XXB2 == MV_TRUE) || + (pAdapter->chipIs60X1B2 == MV_TRUE)) + { + /* Fix for 88SX50xx FEr PCI#1*/ + /* Fix for 88SX60x1 FEr PCI#7*/ + if (pAdapter->pciCommand & MV_PCI_MWRITE_COMBINE_BIT) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d : PCI-X Master" + " Write combine enable rejected\n", + pAdapter->adapterId); + pAdapter->pciCommand &= ~MV_PCI_MWRITE_COMBINE_BIT; + } + } + } + else + { + if ((pAdapter->chipIs50XXB0 == MV_TRUE) || + (pAdapter->chipIs50XXB2 == MV_TRUE)) + { + /* Fix for 88SX50xx FEr PCI#2*/ + if (pAdapter->pciCommand & MV_PCI_MWRITE_COMBINE_BIT) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d : PCI Master" + " Write combine enable rejected\n", + pAdapter->adapterId); + pAdapter->pciCommand &= ~MV_PCI_MWRITE_COMBINE_BIT; + } + if (pAdapter->pciCommand & MV_PCI_MREAD_COMBINE_BIT) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d : PCI Master" + " Read combine enable rejected\n", + pAdapter->adapterId); + pAdapter->pciCommand &= ~MV_PCI_MREAD_COMBINE_BIT; + } + } + } + } +#if 0 + /* Fix for 88SX60x1 FEr SATA#8*/ + for (channelIndex = 0; channelIndex < pAdapter->numberOfChannels; channelIndex++) + { + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + regVal = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET); + /* Fix for 88SX60x1 FEr SATA#8*/ + /* according to the spec, bits [31:12] must be set to 0x009B1 */ + regVal &= 0x00000FFF; + /* regVal |= MV_BIT12;*/ + regVal |= 0x009B1000; + + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET, + regVal); + /* _channelHardReset(pAdapter, channelIndex);*/ + } + + _fixPhyParams(pAdapter, channelIndex); + } +#endif + if (pAdapter->hostInterface == MV_HOST_IF_PCI) + { + + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + MV_PCI_COMMAND_REG_OFFSET, + pAdapter->pciCommand); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + MV_PCI_SERR_MASK_REG_OFFSET, + pAdapter->pciSerrMask); + + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + MV_PCI_INTERRUPT_MASK_REG_OFFSET, + pAdapter->pciInterruptMask); + } + else if (pAdapter->hostInterface == MV_HOST_IF_PEX) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + MV_PCI_E_INTERRUPT_MASK_REG_OFFSET, + MV_PCI_E_ERROR_MASK_VALUE); + } + for (sataUnit = 0; sataUnit < pAdapter->numberOfUnits; sataUnit++) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INT_COAL_THRE_REG_OFFSET, + pAdapter->intCoalThre[sataUnit]); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INT_TIME_THRE_REG_OFFSET, + pAdapter->intTimeThre[sataUnit]); + + } + if (pAdapter->hostInterface == MV_HOST_IF_INTEGRATED) + { + pAdapter->mainMask = MV_BIT8|MV_BIT2|MV_BIT0; + } + else + { + pAdapter->mainMask = MV_MAIN_INTERRUPT_MASK_ENABLE_ALL; + } + pAdapter->interruptsScheme = MV_SATA_INTERRUPT_HANDLING_IN_ISR; + + for (channelIndex = 0; channelIndex < pAdapter->numberOfChannels; channelIndex++) + { + unmaskEdmaInterrupts(pAdapter, channelIndex); + } + return MV_TRUE; +} + +/******************************************************************************* +* mvSataShutDownAdapter - Shuts down adapter. +* +* DESCRIPTION: Shuts down a specific 88SX50xx adapter. +* +* INPUT: +* *pAdapter - pointer to the adapter data structure. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE on success, MV_FALSE on failure +* +* COMMENTS: +* None. +* +*******************************************************************************/ + +MV_BOOLEAN mvSataShutdownAdapter(MV_SATA_ADAPTER *pAdapter) +{ + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataShutdownAdapter Failed, Bad adapter data structure " + "pointer\n"); + return MV_FALSE; + } + pAdapter->interruptsAreMasked = MV_TRUE; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, 0); + return MV_TRUE; +} + +/******************************************************************************* +* mvSataReadReg - return the value of register. +* +* DESCRIPTION: +* return the value of a register, which have the offset regOffset, in a +* MV88SX50XX adapter. +* Note that if reading from storage device's internal registers and EDMA +* is enabled, then the read transaction will never complete and possibly +* cause system hang. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* regOffset - offset of the register +* +* RETURN: +* the register value in 32 bit. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_U32 mvSataReadReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset) +{ + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataReadReg Failed," + " Bad adapter data structure pointer\n"); + return 0; + } + + return MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, regOffset); +} + +/******************************************************************************* +* mvSataWriteReg - return the value of register. +* +* DESCRIPTION: +* write the regValue to a register, which have the offset regOffset, in a +* MV88SX50XX adapter. +* Note that if writing to storage device's internal registers and EDMA +* is enabled, then the write transaction will never complete and possibly +* cause system hang. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* regOffset - offset of the register +* regValue - the value to write to the register +* +* RETURN: +* None. +* COMMENTS: +* for 8 or 16 bit registers the low bits of the regValue should hold the +* requested value to be written. +* +*******************************************************************************/ +MV_VOID mvSataWriteReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset, + MV_U32 regValue) +{ + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataWriteReg Failed," + " Bad adapter data structure pointer\n"); + return; + } + + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, regOffset, regValue); +} +/******************************************************************************* +* mvSataConfigureChannel - configure Sata channel +* +* +* DESCRIPTION: +* this function configures SATA channel by resetting the low level fields +* of the channel data structure and configures EDMA regs accourdingly +* +* INPUT: +* pAdapter - pointer to the MV88SX50XX adapter data structure +* channelIndex - the index of the channel where the response received +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +MV_BOOLEAN mvSataConfigureChannel(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BOOLEAN result; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataConfigureChannel" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataConfigureChann" + "el Failed, channel data structure not allocated\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + if (pAdapter->numberOfChannels <= channelIndex) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataConfigureChann" + "el Failed - requsted to configure a non-valid channel\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + pSataChannel->eDmaRegsOffset = getEdmaRegOffset(channelIndex); + pSataChannel->mvSataAdapter = pAdapter; + + if (mvOsSemInit(&pSataChannel->semaphore)==MV_FALSE) + { + return MV_FALSE; + } + mvOsSemTake(&pSataChannel->semaphore); + + /* Sets the request and response queues base addresses */ + pSataChannel->queueCommandsEnabled = MV_FALSE; + pSataChannel->EdmaActive = MV_FALSE; + pSataChannel->deviceType = MV_SATA_DEVICE_TYPE_UNKNOWN; + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + pSataChannel->PMSupported = MV_TRUE; + } + else + { + pSataChannel->PMSupported = MV_FALSE; + } + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_IIE) + { + pSataChannel->commandsQueue = pAdapter->adapterCommands + + (MV_SATA_GEN2E_SW_QUEUE_SIZE * channelIndex); + pSataChannel->commandsQueueSize = MV_SATA_GEN2E_SW_QUEUE_SIZE; + } + else + { + pSataChannel->commandsQueue = pAdapter->adapterCommands + + (MV_SATA_SW_QUEUE_SIZE * channelIndex); + pSataChannel->commandsQueueSize = MV_SATA_SW_QUEUE_SIZE; + } + pSataChannel->DRQDataBlockSize = 1; + pSataChannel->FBSEnabled = MV_FALSE; + pSataChannel->use128Entries = MV_FALSE; + pSataChannel->EDMAQueuePtrMask = MV_EDMA_QUEUE_MASK; + pSataChannel->EDMARequestInpMask = MV_EDMA_REQUEST_Q_INP_MASK; + result = resetEdmaChannel(pSataChannel); + disableSaDevInterrupts(pAdapter, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return result; +} + +/******************************************************************************* +* mvSataRemoveChannel - +* +* DESCRIPTION: Removes data structures and other parameters used for the +* specific SATA channel that is indicated by pAdapter and channelIndex. +* +* INPUT: +* pAdapter - A pointer to an MV_SATA_ADAPTER data structure that holds +* information to access the 88SX50xx device. +* channelIndex - An index to a specific 88SX50xx channel. +* OUTPUT: +* None. +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* +*******************************************************************************/ + +MV_BOOLEAN mvSataRemoveChannel(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataRemoveChannel" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + mvOsSemTake(&pAdapter->semaphore); + pSataChannel = pAdapter->sataChannel[channelIndex]; + + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataRemoveChannel" + " Failed, channel data structure not allocated\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pAdapter->semaphore); + return MV_FALSE; + } + mvOsSemTake(&pSataChannel->semaphore); + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvSataRemoveChannel " + "failed, DMA is enabled\n", pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + mvOsSemRelease(&pAdapter->semaphore); + return MV_FALSE; + } + mvOsSemRelease(&pSataChannel->semaphore); + mvOsSemRelease(&pAdapter->semaphore); + return MV_TRUE; +} + +/******************************************************************************* +* mvSataIsStorageDeviceConnected - Check if storage device is connected to a +* SATA channel. +* +* DESCRIPTION: +* This function reads the DET field from the R00 status bridge register +* of the corresponding channel. +* +* INPUT: +* pAdapter - Pointer to the device data structure. +* channelIndex - Index of the required channel +* OUTPU: +* SStatus - Pointer to SATA status reg value +* +* RETURN: +* MV_TRUE when storage device is connected, MV_FALSE otherwise( also when +* loopback mode is used). +* +* COMMENTS: +* None +* +*******************************************************************************/ +MV_BOOLEAN mvSataIsStorageDeviceConnected(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 *SStatus) +{ + MV_U32 SStatusOffset = 0; + MV_U32 det; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," : " + "mvSataIsStorageDeviceConnected Failed, Bad adapter data" + " structure pointer\n"); + return MV_FALSE; + } + + if (pAdapter->numberOfChannels <= channelIndex) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: " + "mvSataIsStorageDeviceConnected Failed, Bad channelIndex " + " input on a 0x%x adapterstructure pointer\n", + pAdapter->adapterId,channelIndex,pAdapter->pciConfigDeviceId); + return MV_FALSE; + } + + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + MV_U8 sataUnit = (channelIndex & MV_BIT2) >> 2; + MV_U8 port = channelIndex & (MV_BIT0 | MV_BIT1); + SStatusOffset = MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R00_STATUS_BRIDGE_PORT_OFFSET(port); + } + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + SStatusOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_STATUS_REG_OFFSET; + if (pAdapter->staggaredSpinup[channelIndex] == MV_FALSE) + { + return MV_FALSE; + } + } + + det = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + SStatusOffset) & 0xf; + + switch (det) + { + case MV_PHY_DET_STATE_NO_DEVICE: + break; + case MV_PHY_DET_STATE_DEVICE_NO_PHY_COM: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: Detection value is 1\n", pAdapter->adapterId, + channelIndex); + + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + SStatusOffset); + mvMicroSecondsDelay(pAdapter, MV_PHY_COM_SETUP_WAIT); + det = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + SStatusOffset) & 0xf; + if (det != MV_PHY_DET_STATE_DEVICE_AND_PHY_COM) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: Failed to" + " establish SATA PHY communication\n", + pAdapter->adapterId, channelIndex); + break; + } + case MV_PHY_DET_STATE_DEVICE_AND_PHY_COM: + return MV_TRUE; + case MV_PHY_DET_STATE_PHY_OFFLINE: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: WARNING: SATA PHY is " + "offline\n", pAdapter->adapterId, channelIndex); + break; + default: + return MV_FALSE; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: unknow value for\ + R00 Status Bridge reg bits[3:0] (0x%02x)\n", + pAdapter->adapterId, channelIndex, det); + } + return MV_FALSE; +} + +static MV_BOOLEAN _checkSStatusAfterHReset(MV_SATA_ADAPTER* pAdapter, + MV_U8 channelIndex) +{ + MV_U32 SStatusOffset; + MV_U32 SStatus; + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + /* Get DET field in SControl register to 1 */ + MV_U8 port = channelIndex & (MV_BIT0 | MV_BIT1); + MV_U8 sataUnit = (channelIndex & MV_BIT2) >> 2; + SStatusOffset = MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R00_STATUS_BRIDGE_PORT_OFFSET(port); + } + else + { + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + SStatusOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_STATUS_REG_OFFSET; + } + else + { + return MV_TRUE; + } + } + SStatus = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + SStatusOffset); + SStatus &= (MV_BIT0 | MV_BIT1); + if ((SStatus == (MV_BIT0 | MV_BIT1)) || (SStatus == 0)) + { + return MV_TRUE; + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: in Channel Hard " + "Reset SATA communication not established.\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } +} + + +/******************************************************************************* +* mvSataChannelHardReset - issue channel SATA HARD reset. +* +* DESCRIPTION: +* perform HARDWARE RESET to the connected device by asserting the RESET +* signal, this is done by setting the hardware reset bit of the EDMA +* command register +* +* INPUT: +* pAdapter - pointer to the device data structure. +* channelIndex - index of the required channel +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_BOOLEAN mvSataChannelHardReset(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_U32 count = 0; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataChannelHardReset" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + ioBaseAddr = pAdapter->adapterIoBaseAddress; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: " + "mvSataChannelHardReset Failed, channel data structure not " + "allocated\n", pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + if(pSataChannel) + mvOsSemTake(&pSataChannel->semaphore); + + if (pSataChannel && pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: Error:\ + mvSataIChannelHardReset called while EDMA is active\n", + pAdapter->adapterId,channelIndex); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: Issue HRST\n", pAdapter->adapterId, + channelIndex); + + + _channelHardReset(pAdapter, channelIndex); + _resetBmDma(pAdapter, channelIndex); + if ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && + (pAdapter->staggaredSpinup[channelIndex] == MV_FALSE)) + { + if(pSataChannel) + mvOsSemRelease( &pSataChannel->semaphore); + return MV_TRUE; + } + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + while (1) + { + _establishSataComm(pAdapter, channelIndex); + + /* try the DET fix 3 times */ + if (_checkSStatusAfterHReset(pAdapter, channelIndex) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: in Channel Hard " + "Reset storage drive is not ready, try fix #%d\n", + pAdapter->adapterId, channelIndex, count); + + count++; + if (count == 3) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: in Channel H" + "ard Reset storage drive is not ready after 3 tries\n", + pAdapter->adapterId, channelIndex); + if(pSataChannel) + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_SATA_LINK, " %d %d: Disk is Ready After" + " Hard Reset\n", pAdapter->adapterId, channelIndex); + break; + } + } + } + + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + _establishSataComm(pAdapter, channelIndex); + } + if(pSataChannel) + mvOsSemRelease( &pSataChannel->semaphore); + return MV_TRUE; +} +/******************************************************************************* +* mvSataSetFBSMode - set FIS based switching mode. +* +* DESCRIPTION: +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - index of the required channel +* enableFBS - if true then enable FBS mode. +* useQueueLen128 - if true then enable the 128 EDMA queue length. +* +* RETURN: +* MV_FALSE if +* 1. the FBS feature set to be enable for an adapter that doesn't support this +* feature, or: +* 2. the function called while EDMA is enabled. +* 3. useQueueLen128 is true and enableFBS is false. +* +* COMMENTS: +* This function only sets the sw configuration, the harware is configured +* accordingly by mvSataConfigEdmaMode() +*******************************************************************************/ +MV_BOOLEAN mvSataSetFBSMode(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_BOOLEAN enableFBS, MV_BOOLEAN useQueueLen128) +{ + MV_SATA_CHANNEL *pSataChannel; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataSetFBSMode" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataSetFBSMode" + " Failed, channel data structure not allocated\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + + mvOsSemTake(&pSataChannel->semaphore); + + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: mvSataSetFBSMode failed, EDMA is enabled\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + if (enableFBS == MV_FALSE) + { + pSataChannel->FBSEnabled = MV_FALSE; + pSataChannel->use128Entries = MV_FALSE; + mvOsSemRelease(&pSataChannel->semaphore); + if (useQueueLen128 == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: mvSataSetFBSMode failed, 128 entries queue len is set" + "while FBS mode is disabled\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + return MV_TRUE; + } + + if (pAdapter->sataAdapterGeneration < MV_SATA_GEN_IIE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," %d %d: mvSataSetFBSMode failed," + " Feature not supported by the adapter\n", + pAdapter->adapterId, channelIndex); + pSataChannel->FBSEnabled = MV_FALSE; + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + pSataChannel->FBSEnabled = MV_TRUE; + pSataChannel->use128Entries = useQueueLen128; + mvOsSemRelease(&pSataChannel->semaphore); + return MV_TRUE; +} + +/******************************************************************************* +* mvSataConfigEdmaMode - set EDMA operating mode. +* +* DESCRIPTION: +* Set the EDMA operating mode - MV_EDMA_MODE_NOT_QUEUED, +* MV_EDMA_MODE_QUEUED or MV_EDMA_MODE_NATIVE_QUEUING. +* When set toe MV_EDMA_MODE_QUEUED or MV_EDMA_MODE_NATIVE_QUEUING then +* the maxQueueDepth should be valud. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - index of the required channel +* eDmaMode - the selected mode +* maxQueueDepth - the maximum depth of the queue +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +MV_BOOLEAN mvSataConfigEdmaMode(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_EDMA_MODE eDmaMode, MV_U8 maxQueueDepth) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_U32 eDmaRegsOffset; + MV_U32 val; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataConfigEdmaMode" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataConfigEdmaMode" + " Failed, channel data structure not allocated\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + ioBaseAddr = pAdapter->adapterIoBaseAddress; + mvOsSemTake(&pSataChannel->semaphore); + eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," %d %d: mvSataConfigEdmaMode failed," + " EDMA is enabled\n", pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + + val = MV_REG_READ_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_CONFIG_REG_OFFSET); + if (eDmaMode == MV_EDMA_MODE_NATIVE_QUEUING) + { + if ((maxQueueDepth > MV_EDMA_QUEUE_LENGTH) || (maxQueueDepth == 0)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR," %d %d: mvSataConfigEdmaMode " + "failed, Bad queue depth(%d)\n", pAdapter->adapterId, + channelIndex, maxQueueDepth); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + if (pAdapter->sataAdapterGeneration < MV_SATA_GEN_II) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: Trying to configure " + "EDMA to NCQ on a non NCQ enabled EDMA\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + val &= ~MV_EDMA_CONFIG_Q_DEPTH_MASK; /* clear queue depth */ + /* set the NCQ enable mode bit, and the queue depth bits*/ + val |= MV_EDMA_CONFIG_NATIVE_QUEUING_MASK | (maxQueueDepth - 1); + } + if (eDmaMode == MV_EDMA_MODE_QUEUED) + { + if ((maxQueueDepth > MV_EDMA_QUEUE_LENGTH) || (maxQueueDepth == 0)) + { + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + val &= ~MV_EDMA_CONFIG_Q_DEPTH_MASK; /* clear queue depth */ + val &= ~MV_EDMA_CONFIG_NATIVE_QUEUING_MASK; /* clear NCQ mode*/ + /* set the queue enable mode bit, and the queue depth bits*/ + val |= MV_EDMA_CONFIG_EQUEUE_ENABLED_MASK | (maxQueueDepth - 1); + } + + if (eDmaMode == MV_EDMA_MODE_NOT_QUEUED) + { + val &= ~MV_EDMA_CONFIG_Q_DEPTH_MASK; /* clear queue depth */ + val &= ~MV_EDMA_CONFIG_NATIVE_QUEUING_MASK; /* clear NCQ mode*/ + val &= ~MV_EDMA_CONFIG_EQUEUE_ENABLED_MASK; + } + pSataChannel->queuedDMA = eDmaMode; + + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + val |= MV_EDMA_CONFIG_BURST_SIZE_MASK; + } + if ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + && (pAdapter->hostInterface != MV_HOST_IF_INTEGRATED)) + + { + val |= (MV_EDMA_CONFIG_BURST_SIZE_EXT_MASK | MV_BIT13); + } + + + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_IIE) + { + /* disable RX PM port mask, required for PM*/ + val |= MV_BIT23; + + if (pSataChannel->FBSEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + " %d %d: Enable FBS feature\n", + pAdapter->adapterId, channelIndex); +/* val |= MV_BIT16;*/ + /* Set bit 16 at FISDMAActiveSyncResp */ + _setRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_EDMA_FIS_CONFIGURATION_REG_OFFSET, MV_BIT16); + /* Set bit 8 at SingleSync */ + _setRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + 0x30C, MV_BIT8); + } + else + { + val &= ~MV_BIT16; + } + + if (pSataChannel->use128Entries == MV_TRUE) + { + val |= MV_BIT19; + pSataChannel->EDMAQueuePtrMask = MV_EDMA_GEN2E_QUEUE_MASK; + pSataChannel->EDMARequestInpMask = MV_EDMA_GEN2E_REQUEST_Q_INP_MASK; + } + else + { + val &= ~MV_BIT19; + pSataChannel->EDMAQueuePtrMask = MV_EDMA_QUEUE_MASK; + pSataChannel->EDMARequestInpMask = MV_EDMA_REQUEST_Q_INP_MASK; + } + if(pAdapter->hostInterface != MV_HOST_IF_INTEGRATED) + { + /*enable cutthrough*/ + val |= MV_BIT17; +#ifdef MV_SUPPORT_ATAPI + /*enable early completion*/ + val |= MV_BIT18; +#endif + } + /*enable host queue cache*/ + val |= MV_BIT22; + + if (pAdapter->hostInterface == MV_HOST_IF_PCI) + { + MV_U32 pciMode = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + + MV_PCI_MODE_REG_OFFSET); + + if (getRegField(pciMode, MV_PCI_MODE_OFFSET, 2) == 0) /* PCI*/ + { + if (MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_PCI_REGS_OFFSET + + MV_PCI_COMMAND_REG_OFFSET) & MV_BIT7) + { + /*in this case disable cut through*/ + val &= ~MV_BIT17; + } + } + } + } + /* by defualt, the tags data srutcure initialized in mvSataConfigureChannel*/ + /* for 32 host commands, so we call it again since use128Entries could be */ + /* changed */ + initChannelTags(pSataChannel); + MV_REG_WRITE_DWORD(ioBaseAddr, eDmaRegsOffset + MV_EDMA_CONFIG_REG_OFFSET, + val); + setupEdmaDeviceErrorHandlingConfiguration(pSataChannel); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG," %d %d: Edma Configuration Reg Value: 0x%08x\n", + pAdapter->adapterId, channelIndex, + MV_REG_READ_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_CONFIG_REG_OFFSET)); + + mvOsSemRelease(&pSataChannel->semaphore); + return MV_TRUE; +} + +/******************************************************************************* +* mvSataEnableChannelDma - enable EDMA engine +* +* DESCRIPTION: +* enable the EDMA engine for the given channel +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - index of the required channel +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_BOOLEAN mvSataEnableChannelDma(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataEnableChannelDma" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + ioBaseAddr = pAdapter->adapterIoBaseAddress; + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataEnableChannelD" + "ma Failed, channel data structure not allocated\n", + pAdapter->adapterId, channelIndex ); + return MV_FALSE; + } + mvOsSemTake(&pSataChannel->semaphore); + + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvSataEnableChannelDma " + "failed, DMA is enabled\n", pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } +#ifdef MV_SATA_C2C_COMM + /* C2C */ + if (pSataChannel->C2CmodeEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvSataEnableChannelDma " + "failed, C2C mode is enabled\n", pAdapter->adapterId, + channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } +#endif + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: mvSataEnableChannelDma\n", + pAdapter->adapterId, channelIndex); + pSataChannel->queueCommandsEnabled = MV_TRUE; + activateEdma(pAdapter,channelIndex); + + mvOsSemRelease(&pSataChannel->semaphore); + return MV_TRUE; +} + +/******************************************************************************* +* mvSataDisableChannelDma - disable EDMA engine +* +* DESCRIPTION: +* disable the EDMA engine for the given channel +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - index of the required channel +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_BOOLEAN mvSataDisableChannelDma(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + MV_BUS_ADDR_T ioBaseAddr; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataDisableChannelDma" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + ioBaseAddr = pAdapter->adapterIoBaseAddress; + if (pAdapter->sataChannel[channelIndex] == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataDisableChannel" + "Dma Failed, channel data structure is not allocated\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: mvSataDisableChannel\n", + pAdapter->adapterId, channelIndex); + /* if this function called while commands still not finished, then it's */ + /* probably timeout*/ + if (pAdapter->sataChannel[channelIndex]->outstandingCommands) + { + _dumpSataRegs(pAdapter, channelIndex); + _dumpEDMARegs(pAdapter, channelIndex); + _dumpChannelQueues(pAdapter, channelIndex); + } + + mvOsSemTake(&pAdapter->sataChannel[channelIndex]->semaphore); + pAdapter->sataChannel[channelIndex]->queueCommandsEnabled = MV_FALSE; + deactivateEdma(pAdapter,channelIndex); + mvOsSemRelease(&pAdapter->sataChannel[channelIndex]->semaphore); + return MV_TRUE; +} + +/******************************************************************************* +* mvSataFlushDmaQueue - flush the outstanding UDMA commands +* +* DESCRIPTION: +* flush posted UDMA ATA commands on a certain MV88SX50XX SATA channel. if +* the flush type is MV_FLUSH_TYPE_CALLBACK then all call back functions of +* the UDMA commands are called with a flush indication. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - index of the required channel +* flushType - indicates wheather to call the callBack function or not. +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_BOOLEAN mvSataFlushDmaQueue(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_FLUSH_TYPE flushType) +{ + MV_SATA_CHANNEL *pSataChannel; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataFlushDmaQueue" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataFlushDmaQueue " + "Failed, channel data structure not allocated\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + mvOsSemTake(&pSataChannel->semaphore); + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvSataFlushDmaQueue " + "Failed, EDMA not disabled\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + flushDmaQueue(pSataChannel, flushType, MV_COMPLETION_TYPE_ABORT, 0); + resetEdmaChannel(pSataChannel); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_TRUE; +} + +/******************************************************************************* +* mvSataNumOfDmaCommands - get the number of the outstanding commmands for the +* given channel +* +* DESCRIPTION: +* return the number of posted ATA commands on an EDMA engine for a +* specific SATA channel. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - index of the required channel +* +* RETURN: +* num of queue commands. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_U8 mvSataNumOfDmaCommands(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_U8 result; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataNumOfDmaCommands" + " Failed, Bad adapter data structure pointer\n"); + return 0xFF; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataNumOfDmaComman" + "ds Failed, channel data structure not allocated\n", + pAdapter->adapterId, channelIndex); + return 0xFF; + } + mvOsSemTake(&pSataChannel->semaphore); + result = pSataChannel->outstandingCommands; + mvOsSemRelease(&pSataChannel->semaphore); + + return result; +} +/******************************************************************************* +* mvSataGetNumOfPortQueuedCommands - get the number of the outstanding commmands for +* the given port +* +* DESCRIPTION: +* return the number of posted ATA commands on an EDMA engine for a +* specific SATA port. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - index of the required channel +* PMPort - port number +* pCommandsPerChannel - if not null, gets the total number of outstanding +* command for the given channel +* +* RETURN: +* num of queue commands, 0xFF if error detected. +* COMMENTS: +* +* +*******************************************************************************/ +MV_U8 mvSataGetNumOfPortQueuedCommands(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_U8 *pCommandsPerChannel) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_U8 result; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataGetNumOfPortQueuedCommands" + " Failed, Bad adapter data structure pointer\n"); + return 0xFF; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d %d: mvSataGetNumOfPortQueuedCommands" + "ds Failed, channel data structure not allocated\n", + pAdapter->adapterId, channelIndex, PMPort); + return 0xFF; + } + if (PMPort > MV_SATA_PM_MAX_PORTS) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d %d: mvSataGetNumOfPortQueuedCommands" + "ds Failed, non valid port\n", + pAdapter->adapterId, channelIndex, PMPort); + return 0xFF; + } + mvOsSemTake(&pSataChannel->semaphore); + result = pSataChannel->portQueuedCommands[PMPort]; + if (pCommandsPerChannel) + { + *pCommandsPerChannel = pSataChannel->outstandingCommands; + } + mvOsSemRelease(&pSataChannel->semaphore); + + return result; +} + +/******************************************************************************* +* mvSataSetIntCoalParams - update the interrupt Coalescing registers +* +* DESCRIPTION: Sets the interrupt coalescing for a specific SATA unit +* (each SATA unit contains quad SATA channels). +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* sataUnit - which SATA unit to be changed (0xff for all SATA ports) +* intCoalThre - the value to be written to the Coalescing threshold register +* intTimeThre - the value to be written to the Time threshold register +* +* OUTPUT: +* None. +* RETURN: +* MV_TRUE +* COMMENTS: +* None. +* +*******************************************************************************/ +MV_BOOLEAN mvSataSetIntCoalParams (MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit, + MV_U32 intCoalThre, MV_U32 intTimeThre) +{ + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataSetIntCoalParams" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + + if ((sataUnit != 0) && (sataUnit != 1) && (sataUnit != 0xff)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d : %d Bad" + " unit number\n", pAdapter->adapterId, sataUnit); + return MV_FALSE; + } + + mvOsSemTake(&pAdapter->semaphore); + if (sataUnit == 0xff) + { + if ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && + (pAdapter->hostInterface != MV_HOST_IF_INTEGRATED)) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATA_II_ALL_PORTS_INT_COAL_CMND_THR_REG_OFFSET, + intCoalThre); + + pAdapter->intCoalThre[0] = intCoalThre; + pAdapter->intCoalThre[1] = intCoalThre; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATA_II_ALL_PORTS_INT_COAL_TIME_THR_REG_OFFSET, + intTimeThre); + pAdapter->intTimeThre[0] = intTimeThre; + pAdapter->intTimeThre[1] = intTimeThre; + pAdapter->mainMask |= MV_BIT21; + pAdapter->mainMask &= ~(MV_BIT17 | MV_BIT8); + } + else + { + MV_U8 count; + for (count = 0 ; count < pAdapter->numberOfUnits ; count ++) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(count) + + MV_SATAHC_INT_COAL_THRE_REG_OFFSET, + intCoalThre); + + pAdapter->intCoalThre[count] = intCoalThre; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(count) + + MV_SATAHC_INT_TIME_THRE_REG_OFFSET, + intTimeThre); + pAdapter->intTimeThre[count] = intTimeThre; + } + } + } + else + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INT_COAL_THRE_REG_OFFSET, + intCoalThre); + + pAdapter->intCoalThre[sataUnit] = intCoalThre; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INT_TIME_THRE_REG_OFFSET, + intTimeThre); + pAdapter->intTimeThre[sataUnit] = intTimeThre; + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + pAdapter->mainMask |= (MV_BIT17 | MV_BIT8); + pAdapter->mainMask &= ~MV_BIT21; + } + } + if (pAdapter->interruptsAreMasked == MV_FALSE) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, + pAdapter->mainMask); + + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset); + + } + mvOsSemRelease(&pAdapter->semaphore); + + return MV_TRUE; +} + +/******************************************************************************* +* mvSataSetChannelPhyParams - update the channel's Sata Phy params +* +* DESCRIPTION: This functoin changes the Sata Phy params such as the AMP and +* PRE by updating the PHY Mode register. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex- index of the Edma channel number. +* signalAmps - three bits value to be written to the Phy Mode register at +* bits[7:5] +* pre - two bits value to be written to the Phy Mode register at +* bits[12:11] +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE on success, MV_FASLE otherwisw +* +* +*******************************************************************************/ +MV_BOOLEAN mvSataSetChannelPhyParams(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 signalAmps, MV_U8 pre) +{ + MV_U32 regAddr; + MV_U32 val; + MV_U8 port = channelIndex & (MV_BIT0 | MV_BIT1); + MV_U8 unit = (channelIndex & MV_BIT2) >> 2; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataSetChannelPhyParam" + "s Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + + if (pAdapter->chipIs62X1Z0 == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, "%d : mvSataSetChannelPhyPara\ +m" + "s Failed, This function not supported for this adapter\n", + pAdapter->adapterId); + return MV_FALSE; + } + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + if ((signalAmps & 0xf8) || (pre & 0xfc)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: " + "mvSataSetChannelPhyParams Failed. Bad params\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + + regAddr = MV_SATAHC_REGS_BASE_OFFSET(unit) + + MV_SATA_I_HC_PHY_MODE_BRIDGE_PORT_REG_OFFSET(port); + + val = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, regAddr); + + val &= ~MV_SATA_I_PHY_MODE_AMP_MASK; + val |= (signalAmps << MV_SATA_I_PHY_MODE_AMP_OFFSET) & + MV_SATA_I_PHY_MODE_AMP_MASK; + + val &= ~MV_SATA_I_PHY_MODE_PRE_MASK; + val |= (pre << MV_SATA_I_PHY_MODE_PRE_OFFSET) & + MV_SATA_I_PHY_MODE_PRE_MASK; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, regAddr, val); + pAdapter->pre[channelIndex] = pre; + pAdapter->signalAmps[channelIndex] = signalAmps; + } + + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + if ((signalAmps & 0xf8) || (pre & 0xf8)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: " + "mvSataSetChannelPhyParams Failed. Bad params\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + + + pAdapter->pre[channelIndex] = pre; + pAdapter->signalAmps[channelIndex] = signalAmps; + regAddr = getEdmaRegOffset(channelIndex) + + MV_SATA_II_PHY_MODE_2_REG_OFFSET; + val = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, regAddr); + + val &= ~MV_SATA_II_PHY_MODE_2_AMP_MASK; + val |= (signalAmps << MV_SATA_II_PHY_MODE_2_AMP_OFFSET) & + MV_SATA_II_PHY_MODE_2_AMP_MASK; + val &= ~MV_SATA_II_PHY_MODE_2_PRE_MASK; + val |= (pre << MV_SATA_II_PHY_MODE_2_PRE_OFFSET) & + MV_SATA_II_PHY_MODE_2_PRE_MASK; + val &= ~MV_BIT16; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, regAddr, val); + } + + return MV_TRUE; +} +/******************************************************************************* +* mvSataChannelPhyShutdown - +* +* DESCRIPTION: Shutdown the sata Phy of the given channel. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - index of the required channel +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise +* +* COMMENTS: +* After shutdown no connect / disconnect indication will be available. +* +*******************************************************************************/ + +MV_BOOLEAN mvSataChannelPhyShutdown(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + MV_U32 regVal; + MV_U8 port = channelIndex & (MV_BIT0 | MV_BIT1); + MV_U8 sataUnit = (channelIndex & MV_BIT2) >> 2; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataChannelPhyShutdown" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + regVal = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET); + /* Fix for 88SX60x1 FEr SATA#8*/ + /* according to the spec, bits [31:12] must be set to 0x009B1 */ + regVal &= 0x00000FFF; + /* regVal |= MV_BIT12;*/ + regVal |= 0x009B1000; + + regVal |= MV_BIT9; + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET, + regVal); + return MV_TRUE; + } + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_BRIDGES_TEST_CONTROL_REG_OFFSET); + regVal |= MV_SATA_I_TEST_CONTROL_PHY_SHUTDOWN_MASK(port); + + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_BRIDGES_TEST_CONTROL_REG_OFFSET, regVal); + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_BRIDGES_TEST_CONTROL_REG_OFFSET); + return MV_TRUE; +} +/******************************************************************************* +* mvSataChannelPhyPowerOn - +* +* DESCRIPTION: power on the sata Phy of the given channel. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - index of the required channel +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise +* +* COMMENTS: +* None. +* +*******************************************************************************/ + +MV_BOOLEAN mvSataChannelPhyPowerOn(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + MV_U32 regVal; + MV_U8 port = channelIndex & (MV_BIT0 | MV_BIT1); + MV_U8 sataUnit = (channelIndex & MV_BIT2) >> 2; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataChannelPhyPowerOn" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + regVal = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET); + /* Fix for 88SX60x1 FEr SATA#8*/ + /* according to the spec, bits [31:12] must be set to 0x009B1 */ + regVal &= 0x00000FFF; + /* regVal |= MV_BIT12;*/ + regVal |= 0x009B1000; + + + regVal &= ~(MV_BIT9); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET, + regVal); + _channelHardReset(pAdapter, channelIndex); + return MV_TRUE; + } + _fixPhyParams(pAdapter, channelIndex); + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_BRIDGES_TEST_CONTROL_REG_OFFSET); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " : %d %d %d mvSataChannelPhyPowerOn" + " reg[%x] = 0x%x -> 0x%x\n", pAdapter->adapterId, sataUnit, port, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_BRIDGES_TEST_CONTROL_REG_OFFSET, regVal, + regVal & ~(MV_SATA_I_TEST_CONTROL_PHY_SHUTDOWN_MASK(port))); + regVal &= ~(MV_SATA_I_TEST_CONTROL_PHY_SHUTDOWN_MASK(port)); + + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_BRIDGES_TEST_CONTROL_REG_OFFSET, regVal); + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_BRIDGES_TEST_CONTROL_REG_OFFSET);{ + MV_U32 temp = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R02_STATUS_BRIDGE_PORT_OFFSET(port)); + temp &= ~0xf; + temp |= MV_BIT0; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R02_STATUS_BRIDGE_PORT_OFFSET(port), temp); + } + _fixPhyParams(pAdapter, channelIndex); + return MV_TRUE; +} + +/******************************************************************************* +* mvSataChannelFarLoopbackDiagnostic - do far end loopback +* +* DESCRIPTION: operate the far-end LB mode on the bridge +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - index of the required channel +* +* OUTPUT: +* None. +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise +* COMMENTS: +* None. +*******************************************************************************/ + +MV_BOOLEAN mvSataChannelFarLoopbackDiagnostic(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + MV_U8 sataUnit = (channelIndex & MV_BIT2) >> 2; + MV_U8 port = channelIndex & (MV_BIT0 | MV_BIT1); + MV_U32 regVal = 0, temp; + MV_U32 tryCount, pollCount; + MV_BOOLEAN result = MV_TRUE; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataChannelFarLoopback" + "Diagnostic Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + /* TODO - Add support for far end loopback */ + return MV_TRUE; + } + + for (tryCount = 0; tryCount < 5; tryCount++) + { + + /* Set Far-end loopback */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R04_STATUS_BRIDGE_PORT_OFFSET(port), + 0x00100000); + /* BIST pattern */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R05_STATUS_BRIDGE_PORT_OFFSET(port), + 0xb5b5b5b5); + /* BIST pattern */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R06_STATUS_BRIDGE_PORT_OFFSET(port), + 0xb5b5b5b5); + /* enable BIST */ + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R0F_STATUS_BRIDGE_PORT_OFFSET(port), + 0x00200000); + + mvMicroSecondsDelay(pAdapter, MV_FAR_END_LOOPBACK_TEST_WAIT_TIME); + + /* poll bit 20 of register 0F(bist finish) for 50 times*/ + for (pollCount = 0; pollCount < 50; pollCount++) + { + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R0F_STATUS_BRIDGE_PORT_OFFSET(port)); + + if (regVal & MV_BIT20) + { + break; + } + } + + if (regVal & MV_BIT20) + { + break; + }/*if bit 20 still 0, then try the bist sequence again for 5 times*/ + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: Warning: FarEnd LoopBack " + "- bit 20 still not set try again, tryCount %d\n",pAdapter->adapterId, + channelIndex, tryCount); + temp = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R02_STATUS_BRIDGE_PORT_OFFSET(port)); + temp &= 0xff0; + temp |= MV_BIT0; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R02_STATUS_BRIDGE_PORT_OFFSET(port), temp); + + if (waitForBusyAfterHReset(pAdapter, channelIndex) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: in Channel Hard Rese" + "t storage drive is not ready\n",pAdapter->adapterId, + channelIndex); + + result = MV_FALSE; + } + _fixPhyParams(pAdapter, channelIndex); + + + + + + + + } + } + if (tryCount == 5) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: FarEnd LoopBack Failed" + "- the test doesn't finish\n",pAdapter->adapterId, + channelIndex); + result = MV_FALSE; + } + else + { + if (((regVal & MV_BIT20) == 0) && (regVal & MV_BIT19)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: FarEnd LoopBack" + " finished with error, 0F regVal= %x\n",pAdapter->adapterId, + channelIndex, regVal); + result = MV_FALSE; + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: FarEnd LoopBack finished " + "successfuly, 0F regVal= %x\n",pAdapter->adapterId, + channelIndex, regVal); + } + } + /* disable BIST and start phy communication */ + temp = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R02_STATUS_BRIDGE_PORT_OFFSET(port)); + temp &= 0xff0; + temp |= MV_BIT0; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATA_I_HC_R02_STATUS_BRIDGE_PORT_OFFSET(port), temp); + + if (waitForBusyAfterHReset(pAdapter, channelIndex) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: in Channel Hard Rese" + "t storage drive is not ready\n",pAdapter->adapterId, + channelIndex); + + result = MV_FALSE; + } + _fixPhyParams(pAdapter, channelIndex); + + return result; +} + +/******************************************************************************* +* mvSataQueueCommand - Execute ATA command (PIO or UDMA) +* +* DESCRIPTION: +* adds ATA PIO or UDMA request to a MV88SX50XX specific sata channel +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific EDMA channel +* pCommandInfo - Pointer to the PIO or UDMA command +* +* RETURN: +* MV_DMA_QUEUE_RESULT_OK - Command queuing is successfull +* MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED - when trying to add command + while command queuing is disabled +* MV_QUEUE_COMMAND_RESULT_FULL - Command queue is full +* MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS - when the connected device doesn't +* support 48 bit addressing but the new command need's to use 48bit +* addressing. +* MV_QUEUE_RESULT_BAD_PARAMS - When bad parameters are received +* +* COMMENTS: +* None. +* +*******************************************************************************/ +MV_QUEUE_COMMAND_RESULT mvSataQueueCommand(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_QUEUE_COMMAND_INFO *pCommandInfo) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + MV_QUEUED_COMMAND_ENTRY *pCommandEntry; + MV_U32 eDmaRegsOffset; + MV_U8 hostTag; + MV_U8 deviceTag; + +#ifdef MV_SATA_IO_GRANULARITY + MV_U8 nextTransId; +#endif + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataQueueCommand" + " Failed, Bad adapter data structure pointer\n"); + return MV_QUEUE_COMMAND_RESULT_BAD_PARAMS; + } + + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataQueueCommand" + " Failed, channel data structure not allocated\n", + pAdapter->adapterId, channelIndex); + return MV_QUEUE_COMMAND_RESULT_BAD_PARAMS; + } + mvOsSemTake(&pSataChannel->semaphore); +#ifdef MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION + if ((pAdapter->sataAdapterGeneration < MV_SATA_GEN_IIE) && + (MV_QUEUED_COMMAND_TYPE_UDMA == pCommandInfo->type) && + (pCommandInfo->commandParams.udmaCommand.singleDataRegion == MV_TRUE)) + { + mvOsSemRelease(&pSataChannel->semaphore); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: " + "mvSataQueueCommand single Data region not supported\n", + pAdapter->adapterId, channelIndex); + return MV_QUEUE_COMMAND_RESULT_BAD_PARAMS; + } +#endif + eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + if (pSataChannel->queueCommandsEnabled == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: queued commands mode" + " is disabled\n", pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED; + } + + if (getTag(pSataChannel, pCommandInfo->PMPort, &hostTag, &deviceTag) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: queue is full\n", + pAdapter->adapterId, channelIndex ); + + mvOsSemRelease(&pSataChannel->semaphore); + return MV_QUEUE_COMMAND_RESULT_FULL; + } +#ifdef MV_SATA_IO_GRANULARITY + if ((MV_QUEUED_COMMAND_TYPE_UDMA == pCommandInfo->type) && + (MV_TRUE == + pCommandInfo->commandParams.udmaCommand.ioGranularityEnabled)) + { + + if (MV_FALSE == pAdapter->iogEnabled) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d: IO granularity is " + "disabled for the adapter\n", + pAdapter->adapterId, channelIndex ); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_QUEUE_COMMAND_RESULT_BAD_PARAMS; + } + else + { + if (pAdapter->iogFreeIdsNum <= 0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d: IO granularity " + "queue is full\n", + pAdapter->adapterId); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_QUEUE_COMMAND_RESULT_FULL; + } + } + } +#endif + pCommandEntry = &(pSataChannel->commandsQueue[hostTag]); + pCommandEntry->hostTag = hostTag; + pCommandEntry->deviceTag = deviceTag; + pCommandEntry->isCommandInEdma = MV_FALSE; + pCommandEntry->commandAborted = MV_FALSE; + if (pCommandInfo->type == MV_QUEUED_COMMAND_TYPE_UDMA) + { + MV_UDMA_COMMAND_PARAMS *pUdmaCommand = &pCommandInfo->commandParams.udmaCommand; + if (pSataChannel->queuedDMA == MV_EDMA_MODE_NATIVE_QUEUING) + { + pUdmaCommand->isEXT = MV_TRUE; + } +#ifdef MV_SATA_IO_GRANULARITY + pUdmaCommand->iogCurrentTransId = MV_IOG_INVALID_COMMAND_ID; + if ((MV_TRUE == pAdapter->iogEnabled) && + (MV_TRUE == pUdmaCommand->ioGranularityEnabled)) + { + if (pUdmaCommand->iogCommandType == MV_IOG_COMMAND_TYPE_FIRST) + { + mvOsSemTake(&pAdapter->iogSemaphore); + nextTransId = + pAdapter->iogFreeIdsStack[--(pAdapter->iogFreeIdsNum)]; + setIoGranularityCount(pAdapter, + nextTransId, + pUdmaCommand->ioGranularityCommandParam.transCount); + mvOsSemRelease(&pAdapter->iogSemaphore); + } + else + { + nextTransId = + pUdmaCommand->ioGranularityCommandParam.transId; + } + pUdmaCommand->iogCurrentTransId = nextTransId; + } +#endif + if ((pSataChannel->noneUdmaOutstandingCommands == 0) && +#ifdef MV_SUPPORT_ATAPI + (pSataChannel->packetOutstandingCommands == 0) && +#endif + (pSataChannel->ErrorHandlingInfo.state == MV_ERROR_HANDLING_STATE_IDLE)) + { + if (pSataChannel->EdmaActive == MV_FALSE) + { + disableSaDevInterrupts(pAdapter,channelIndex); + activateEdma(pAdapter,channelIndex); + } + addCommand(pSataChannel, pCommandEntry, pCommandInfo); + EdmaReqQueueInsert(pSataChannel, pCommandEntry, + &pCommandInfo->commandParams.udmaCommand); + } + else + { + addCommand(pSataChannel, pCommandEntry, pCommandInfo); + } + } + else + { + addCommand(pSataChannel, pCommandEntry, pCommandInfo); + if (pSataChannel->outstandingCommands == 1) + { + if (pSataChannel->EdmaActive == MV_TRUE) + { + deactivateEdma(pAdapter,channelIndex); + } + if (pSataChannel->PMSupported == MV_TRUE) + { + _setActivePMPort(pSataChannel, pCommandInfo->PMPort); + } + if (sendNoneUdmaCommand(pSataChannel, pCommandEntry) == MV_FALSE) + { + removeCommand(pSataChannel,pCommandEntry); + _doSoftReset(pSataChannel); + mvOsSemRelease(&pSataChannel->semaphore); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: Failed to " + "Issue PIO command\n", pAdapter->adapterId, + channelIndex); + return MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED; + } + } + } + + mvOsSemRelease(&pSataChannel->semaphore); + return MV_QUEUE_COMMAND_RESULT_OK; + + + + + + + +} +/******************************************************************************* +* mvSataSetInterruptsScheme - Modify interrupt scheme +* +* DESCRIPTION: +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* interruptScheme = A parameter containing the rquired interrupt scheme +* +* RETURN: +* MV_TRUE on success, otherwise MV_FALSE. +* COMMENTS: This function doesn't modify the HW main mask register +* +*******************************************************************************/ +MV_BOOLEAN mvSataSetInterruptsScheme(MV_SATA_ADAPTER *pAdapter, + MV_SATA_INTERRUPT_SCHEME interruptScheme) +{ + mvOsSemTake(&pAdapter->semaphore); + switch (interruptScheme) + { + case MV_SATA_INTERRUPT_HANDLING_IN_ISR: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_INTERRUPTS, " %d : Interrupts" + " scheme set to Handling in ISR\n", pAdapter->adapterId); + break; + case MV_SATA_INTERRUPT_HANDLING_IN_TASK: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_INTERRUPTS, " %d : Interrupts" + " scheme set to Handling in TASK\n", pAdapter->adapterId); + break; + case MV_SATA_INTERRUPTS_DISABLED: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_INTERRUPTS, " %d : Interrupts" + " scheme set to interrupts Disabled\n", pAdapter->adapterId); + break; + default: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d : in mvSataSet" + "InterruptsScheme: Invalid Interrup scheme (%d)\n", + pAdapter->adapterId, interruptScheme); + mvOsSemRelease(&pAdapter->semaphore); + return MV_FALSE; + } + pAdapter->interruptsScheme = interruptScheme; + mvOsSemRelease(&pAdapter->semaphore); + return MV_TRUE; +} + +/******************************************************************************* +* mvSataCheckPendingInterrupt - Check and mask interrupts +* +* DESCRIPTION: +* Check if an interrupt is pending, If there is a pending interrupt then +* this function masks the adapter's interrupts and returns MV_TRUE +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* +* RETURN: +* MV_TRUE if the interrupt issued by mv adapter, otherwise MV_FALSE. +* COMMENTS: +* this function must be used only when interrupt scheme is set to +* MV_SATA_INTERRUPT_IN_TASK +* +*******************************************************************************/ +MV_BOOLEAN mvSataCheckPendingInterrupt(MV_SATA_ADAPTER *pAdapter) +{ + MV_U32 mainMask; + MV_BUS_ADDR_T ioBaseAddr = pAdapter->adapterIoBaseAddress; + + /*mvOsSemTake(&pAdapter->interruptsMaskSem);*/ + mainMask = pAdapter->mainMask; + /*mvOsSemRelease(&pAdapter->interruptsMaskSem);*/ + /* if the interrupt it ours*/ + if (MV_REG_READ_DWORD(ioBaseAddr,pAdapter->mainCauseOffset) & + mainMask) + { + /*clear mainMask, the ISR enables the interrupt once served*/ + MV_REG_WRITE_DWORD(ioBaseAddr, pAdapter->mainMaskOffset, 0); + return MV_TRUE; + } + /*bogus interrupt*/ + return MV_FALSE; +} +/******************************************************************************* +* mvSataInterruptServiceRoutine - Interrupt service routine +* +* DESCRIPTION: +* this function is an interrupt service routine that is called upon +* reception of an interrupt from a MV88SX50XX adapter. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* +* RETURN: +* MV_TRUE if the interrupt issued by mv adapter, otherwise MV_FALSE. +* COMMENTS: +* this function handles all the events that generate interrupts incuding +* calling the upper layer call back functions. +* +*******************************************************************************/ +MV_BOOLEAN mvSataInterruptServiceRoutine(MV_SATA_ADAPTER *pAdapter) +{ + MV_U32 mainCause; + MV_U32 mainMask; + MV_U32 unitCause = 0; + MV_U32 responseDone; + MV_U32 edmaError; + MV_U32 deviceInterrupt; + MV_U8 sataUnit; + MV_U8 port; + MV_BUS_ADDR_T ioBaseAddr = pAdapter->adapterIoBaseAddress; + mvOsSemTake(&pAdapter->semaphore); + mainCause = MV_REG_READ_DWORD(ioBaseAddr, + pAdapter->mainCauseOffset); + + /* Check if the interrupt is ours */ + mvOsSemTake(&pAdapter->interruptsMaskSem); + mainMask = pAdapter->mainMask; + mvOsSemRelease(&pAdapter->interruptsMaskSem); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG | MV_DEBUG_INTERRUPTS, + " %d : Interrupt. Cause = 0x%08x, mask 0x%08x\n", + pAdapter->adapterId, mainCause, mainMask); + + /* + * Check if interrupt is our or interrupts are masked. + * in interrupts disaled scheme, the main mask register is cleared but the + * mainMask variable will hold the bits where interrupts expected, this why + * the sheme is not checked + */ + if ((0 == (mainCause & mainMask)) || + ((pAdapter->interruptsAreMasked == MV_TRUE) && + (pAdapter->interruptsScheme != MV_SATA_INTERRUPTS_DISABLED))) + { + /* when interrupts handled in task, we expect to find interrupts here*/ + if (pAdapter->interruptsScheme == MV_SATA_INTERRUPT_HANDLING_IN_TASK) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," %d : ISR called " + "but no interrutps are found in interrupts handle in task" + "scheme!\n", pAdapter->adapterId); + /*anyway unmask interrupts*/ + mvOsSemTake(&pAdapter->interruptsMaskSem); + if (pAdapter->interruptsAreMasked == MV_FALSE) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, + pAdapter->mainMask); + } + mvOsSemRelease(&pAdapter->interruptsMaskSem); + } + mvOsSemRelease(&pAdapter->semaphore); + return MV_FALSE; + } + + if (mainCause & MV_MAIN_INTERRUPT_MASK_REG_PCIERR_BIT) + { + handlePCIErrorInterrupt(pAdapter); + } +#ifdef MV_SATA_IO_GRANULARITY + /*IO Granularity interrupt*/ + if (mainCause & MV_IOG_TRANS_INT_MASK) + { + mvOsSemTake(&pAdapter->iogSemaphore); + iogInterrupt(pAdapter, ioBaseAddr, mainCause); + mvOsSemRelease(&pAdapter->iogSemaphore); + } +#endif + for (sataUnit = 0; sataUnit < pAdapter->numberOfUnits; sataUnit++) + { + if ((pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) && + (pAdapter->hostInterface != MV_HOST_IF_INTEGRATED)) + { + /* Clear the all ports interrupt coalescing cause register */ + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_SATA_II_ALL_PORTS_INT_CAUSE_REG_OFFSET, + 0); + } + + if (mainCause & 0x1ff) + { + MV_U32 unitCauseAddr = MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET; + MV_U32 unitRspInPtr; + + /* clear the cause bit of the Coalescing interrupt*/ + MV_REG_WRITE_DWORD(ioBaseAddr, unitCauseAddr, ~MV_BIT4); + unitCause = MV_REG_READ_DWORD(ioBaseAddr, unitCauseAddr); + /* clear the cause register of the current unit */ + MV_REG_WRITE_DWORD(ioBaseAddr, unitCauseAddr, ~unitCause | MV_BIT4); + + unitRspInPtr = MV_REG_READ_DWORD(ioBaseAddr, + MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_RESPONSE_Q_IN_POINTER_OFFSET); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d unit %d : unitCause = 0x%08x," + " unitRspInPtr 0x%08x\n", pAdapter->adapterId, sataUnit, + unitCause, unitRspInPtr); + + for (port = 0; port < pAdapter->portsPerUnit; port++) + { + deviceInterrupt = unitCause & (MV_BIT8 << port); + responseDone = unitCause & (1 << port); + edmaError = (mainCause & MV_BIT0) ; + + if (responseDone || edmaError) + { + handleEdmaInterrupt(pAdapter, sataUnit, port, + (MV_U8)(unitRspInPtr), + responseDone, + edmaError, unitCause); + } + if (deviceInterrupt && + (SaDevInterrutpBit((MV_U8)MV_CHANNEL_INDEX(sataUnit, port)) & mainMask)) + { + handleDeviceInterrupt(pAdapter, sataUnit, port); + } + + + mainCause >>= 2; + unitRspInPtr >>= 8; + } + } + else + { + mainCause >>=8; + } + mainCause >>= 1; /* this is for the coalescing 0-3 bit*/ + } + if (pAdapter->interruptsScheme == MV_SATA_INTERRUPT_HANDLING_IN_TASK) + { + if (pAdapter->interruptsAreMasked == MV_FALSE) + { + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, + pAdapter->mainMask); + } + } + mvOsSemRelease(&pAdapter->semaphore); + return MV_TRUE; +} +/******************************************************************************* +* mvSataMaskAdapterInterrupt - mask any interrupts can be generated from a +* MV88SX50XX adapter +* +* DESCRIPTION: +* mask all the interrupts that could occur from the adapter. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* Before masking the interrupts, the value of the interrupt maks register +* will be stored in the adapter data structure. +* +*******************************************************************************/ +MV_BOOLEAN mvSataMaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter) +{ + pAdapter->interruptsAreMasked = MV_TRUE; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, 0); + return MV_TRUE; +} + +/******************************************************************************* +* mvSataUnmaskAdapterInterrupt - unmask interrupts can be generated from a +* MV88SX50XX adapter +* +* DESCRIPTION: +* Restore a previous value in the MV88SX50XX interrupt maks register by +* writing the previously stored value in the interruptMaskRegister field +* in the adapter data structure to the MV88SX50XX adapter main interrupt +* mask register +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* +*******************************************************************************/ +MV_BOOLEAN mvSataUnmaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter) +{ + mvOsSemTake(&pAdapter->interruptsMaskSem); + pAdapter->interruptsAreMasked = MV_FALSE; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, + pAdapter->mainMask); + mvOsSemRelease(&pAdapter->interruptsMaskSem); + return MV_TRUE; +} + + +/******************************************************************************* +* mvSataEnableStaggeredSpinUpAll - Enables staggared spin-up of all SATA channels +* +* DESCRIPTION: +* Enables staggared spin-up of all SATA II chnannel. This function is not +* relevant for SATA I. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* +*******************************************************************************/ +MV_BOOLEAN mvSataEnableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter) +{ + MV_U8 channelIndex; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataEnableStaggeredSpinUp Failed, Bad adapter data structure" + " pointer\n"); + return MV_FALSE; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d : Staggered spin-up called for all " + "SATA channels\n",pAdapter->adapterId); + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + + mvOsSemTake(&pAdapter->semaphore); + _establishSataCommAll(pAdapter); + for (channelIndex = 0 ; channelIndex < pAdapter->numberOfChannels ; + channelIndex ++) + { + MV_U32 SStatusReg; + SStatusReg = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_STATUS_REG_OFFSET); + + /* + * Fix for 88SX60X1 FEr #10 + */ + + if ((SStatusReg != 0x0) && (SStatusReg != 0x113) && (SStatusReg != 0x123)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: SStatusRegs = %x ; " + "retrying communication...", + pAdapter->adapterId, channelIndex, SStatusReg); + _establishSataComm(pAdapter,channelIndex); + SStatusReg = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_STATUS_REG_OFFSET); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: New SStatus is %x\n", + pAdapter->adapterId, channelIndex, SStatusReg); + + } + if ( ((SStatusReg & 0xf) == MV_PHY_DET_STATE_DEVICE_NO_PHY_COM) || + ((SStatusReg & 0xf) == MV_PHY_DET_STATE_PHY_OFFLINE)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: " + "Error - failed to establish SATA link after staggered " + "spin up (S Status = %08x)\n", pAdapter->adapterId, + channelIndex, SStatusReg); + } + pAdapter->staggaredSpinup[channelIndex] = MV_TRUE; + } + mvOsSemRelease(&pAdapter->semaphore); + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_SATA_LINK | MV_DEBUG, " %d : " + "Finished staggered spin-up\n", pAdapter->adapterId); + + return MV_TRUE; +} + +/******************************************************************************* +* mvSataEnableStaggeredSpinUp - Enables staggared spin-up. +* +* DESCRIPTION: +* Enables staggared spin-up of SATA II chnannel. This function is not +* relevant for SATA I. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific EDMA channel +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* +*******************************************************************************/ +MV_BOOLEAN mvSataEnableStaggeredSpinUp (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataEnableStaggeredSpinUp Failed, Bad adapter data structure" + " pointer\n"); + return MV_FALSE; + } + if (channelIndex >= pAdapter->numberOfChannels) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataEnableStaggeredSpinUp Failed, bad channel index\n"); + return MV_FALSE; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: Staggered spin-up called\n", + pAdapter->adapterId, channelIndex); + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + MV_U32 SStatusReg; + + mvOsSemTake(&pAdapter->semaphore); + _establishSataComm(pAdapter, channelIndex); + SStatusReg = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_STATUS_REG_OFFSET); + if ( ((SStatusReg & 0xf) == MV_PHY_DET_STATE_DEVICE_NO_PHY_COM) || + ((SStatusReg & 0xf) == MV_PHY_DET_STATE_PHY_OFFLINE)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: " + "Error - failed to establish SATA link after staggered " + "spin up (S Status = %08x)\n", pAdapter->adapterId, + channelIndex, SStatusReg); + } + pAdapter->staggaredSpinup[channelIndex] = MV_TRUE; + mvOsSemRelease(&pAdapter->semaphore); + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_SATA_LINK | MV_DEBUG, " %d %d: " + "Finished staggered spin-up\n", pAdapter->adapterId, + channelIndex); + + return MV_TRUE; +} + +/******************************************************************************* +* mvSataDisableStaggeredSpinUpAll - Disables staggared spin-up on all channels +* +* DESCRIPTION: +* Disables staggared spin-up of all SATA II chnannel. This function is not +* relevant for SATA I. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* +*******************************************************************************/ +MV_BOOLEAN mvSataDisableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter) +{ + MV_U8 channelIndex; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataDisableStaggeredSpinUp Failed, Bad adapter data structure" + " pointer\n"); + return MV_FALSE; + } + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + /* OK to use mvSataDisableStaggeredSpinUp since it's fast enough */ + for (channelIndex = 0 ; channelIndex < pAdapter->numberOfChannels ; + channelIndex ++) + { + mvSataDisableStaggeredSpinUp(pAdapter,channelIndex); + } + } + return MV_TRUE; +} + +/******************************************************************************* +* mvSataDisableStaggeredSpinUp - Disables staggared spin-up. +* +* DESCRIPTION: +* Disables staggared spin-up of SATA II chnannel. This function is not +* relevant for SATA I. +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific EDMA channel +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* +*******************************************************************************/ +MV_BOOLEAN mvSataDisableStaggeredSpinUp (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + MV_U32 SControlOffset, regVal; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataDisableStaggeredSpinUp Failed, Bad adapter data structure" + " pointer\n"); + return MV_FALSE; + } + if (channelIndex >= pAdapter->numberOfChannels) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataDisableStaggeredSpinUp Failed, bad channel index\n"); + return MV_FALSE; + } + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + mvOsSemTake(&pAdapter->semaphore); + SControlOffset = getEdmaRegOffset( channelIndex) + + MV_SATA_II_S_CONTROL_REG_OFFSET; + regVal = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, SControlOffset); + regVal &= ~0xf; + regVal |= MV_PHY_DET_CONTROL_SHUTDOWN; + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, SControlOffset, + regVal); + pAdapter->staggaredSpinup[channelIndex] = MV_FALSE; + mvOsSemRelease(&pAdapter->semaphore); + } + return MV_TRUE; +} + +/******************************************************************************* +* mvSataSetInterfaceSpeed - Sets the interface speed of a specific SATA channel +* +* DESCRIPTION: +* Sets the interface speed of a specific SATA channel (1.5/3 Gbps) +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific EDMA channel +* +* RETURN: +* MV_SATA_IF_SPEED_1_5 for 1.5 Gbps +* MV_SATA_IF_SPEED_3 for 3 Gbps +* MV_SATA_IF_SPEED_INVALID if no speed is negotiated +* +* COMMENTS: +* +*******************************************************************************/ + +MV_BOOLEAN mvSataSetInterfaceSpeed (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_SATA_IF_SPEED ifSpeed) +{ + MV_U32 SStatusOffset; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataSetInterfaceSpeed Failed, Bad adapter data structure" + " pointer\n"); + return MV_FALSE; + } + if (channelIndex >= pAdapter->numberOfChannels) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataSetInterfaceSpeed Failed, bad channel index\n"); + return MV_FALSE; + } + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + MV_SATA_CHANNEL *pSataChannel; + + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel != NULL) + { + mvOsSemTake(&pSataChannel->semaphore); + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: Error:" + "mvSataSetInterfaceSpeed called while EDMA is active\n", + pAdapter->adapterId,channelIndex); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + mvOsSemRelease(&pSataChannel->semaphore); + } + + SStatusOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_STATUS_REG_OFFSET; + + if (ifSpeed == MV_SATA_IF_SPEED_1_5_GBPS) + { + pAdapter->limitInterfaceSpeed[channelIndex] = MV_TRUE; + pAdapter->ifSpeed[channelIndex] = MV_SATA_IF_SPEED_1_5_GBPS; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_SATA_LINK, " %d %d: Set Sata speed to " + "1.5Gbps\n", pAdapter->adapterId,channelIndex); + } + else if (ifSpeed == MV_SATA_IF_SPEED_3_GBPS) + { + pAdapter->limitInterfaceSpeed[channelIndex] = MV_TRUE; + pAdapter->ifSpeed[channelIndex] = MV_SATA_IF_SPEED_3_GBPS; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_SATA_LINK, " %d %d: Set Sata speed to " + "3Gbps\n", pAdapter->adapterId,channelIndex); + } + else if (ifSpeed == MV_SATA_IF_SPEED_NO_LIMIT) + { + pAdapter->limitInterfaceSpeed[channelIndex] = MV_FALSE; + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_SATA_LINK, " %d %d: don't limit Sata" + " speed \n", pAdapter->adapterId,channelIndex); + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataSetInterfaceSpeed Failed, bad IF speed\n"); + return MV_FALSE; + } + + mvOsSemTake(&pAdapter->semaphore); + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + MV_U32 regVal; + + regVal = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET); + /* according to the spec, bits [31:12] must be set to 0x009B1 */ + regVal &= 0x00000FFF; + /* regVal |= MV_BIT12;*/ + regVal |= 0x009B1000; + + if ((pAdapter->limitInterfaceSpeed[channelIndex] == MV_TRUE) && + (pAdapter->ifSpeed[channelIndex] == MV_SATA_IF_SPEED_1_5_GBPS)) + { + regVal &= ~MV_BIT7; /* Disable GEn II */ + } + else + { + regVal |= MV_BIT7; /* Enable GEn II */ + + } + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + getEdmaRegOffset (channelIndex) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET, + regVal); + } + + _channelHardReset(pAdapter, channelIndex); + /* If interface is already active, then device detection is needed */ + if (pAdapter->staggaredSpinup[channelIndex] == MV_TRUE) + { + _establishSataComm(pAdapter, channelIndex); + } + mvOsSemRelease(&pAdapter->semaphore); + return MV_TRUE; + } + if ((pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) && + ((ifSpeed == MV_SATA_IF_SPEED_NO_LIMIT) || + (ifSpeed == MV_SATA_IF_SPEED_1_5_GBPS))) + { + return MV_TRUE; + } + return MV_FALSE; +} + +/******************************************************************************* +* mvSataGetInterfaceSpeed - Gets the interface speed of a specific SATA channel +* +* DESCRIPTION: +* Gets the interface speed of a specific SATA channel (1.5/3 Gbps) +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific EDMA channel +* +* RETURN: +* MV_SATA_IF_SPEED_1_5 for 1.5 Gbps +* MV_SATA_IF_SPEED_3 for 3 Gbps +* MV_SATA_IF_SPEED_INVALID if no speed is negotiated +* +* COMMENTS: +* +*******************************************************************************/ +MV_SATA_IF_SPEED mvSataGetInterfaceSpeed (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + MV_U32 SStatusOffset, regVal; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataGetInterfaceSpeed Failed, Bad adapter data structure" + " pointer\n"); + return MV_SATA_IF_SPEED_INVALID; + } + if (channelIndex >= pAdapter->numberOfChannels) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataGetInterfaceSpeed Failed, bad channel index\n"); + return MV_SATA_IF_SPEED_INVALID; + } + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + if (pAdapter->staggaredSpinup[channelIndex] == MV_TRUE) + { + SStatusOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_STATUS_REG_OFFSET; + regVal = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, SStatusOffset); + if (regVal & MV_BIT4) + { + return MV_SATA_IF_SPEED_1_5_GBPS; + } + if (regVal & MV_BIT5) + { + return MV_SATA_IF_SPEED_3_GBPS; + } + } + return MV_SATA_IF_SPEED_INVALID; + } + return MV_SATA_IF_SPEED_1_5_GBPS;/*TBD*/ +} + +/******************************************************************************* +* mvSataSetInterfacePowerState - Sets the sata interface power state of a +* specific SATA channel +* +* DESCRIPTION: +* Sets the interface power state of a specific SATA channel +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific EDMA channel +* ifPowerState - sata interface power state +* +* RETURN: +* MV_TRUE if the desired power state entered successfully. +* MV_FALSE otherwise +* COMMENTS: +* +*******************************************************************************/ +MV_BOOLEAN mvSataSetInterfacePowerState (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_SATA_IF_POWER_STATE ifPowerState) +{ + MV_U32 SControlOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_CONTROL_REG_OFFSET; + MV_U32 SStatusOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_STATUS_REG_OFFSET; + MV_U32 SControl; + MV_U32 SStatus; + MV_U32 IPM; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataSetInterfacePowerState Failed, Bad adapter data structure" + " pointer\n"); + return MV_FALSE; + } + if (channelIndex >= pAdapter->numberOfChannels) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataSetInterfacePowerState Failed, bad channel index\n"); + return MV_FALSE; + } + if (pAdapter->sataAdapterGeneration < MV_SATA_GEN_II) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: " + "mvSataSetInterfacePowerState Failed, adapter not supported\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + if (pAdapter->staggaredSpinup[channelIndex] == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: " + "mvSataSetInterfacePowerState Failed, sata link not established yet\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + + switch (ifPowerState) + { + case MV_SATA_IF_POWER_PHY_READY: + SControl = 0x4300; + break; + case MV_SATA_IF_POWER_PARTIAL: + SControl = 0x1300; + break; + case MV_SATA_IF_POWER_SLUMBER: + SControl = 0x2300; + break; + default: + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: " + "mvSataSetInterfacePowerState Failed, unkniwn state (0x%x)\n", + pAdapter->adapterId, channelIndex, ifPowerState); + return MV_FALSE; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: " + "mvSataSetInterfacePowerState: enter state 0x%x (prev 0x%x)\n", + pAdapter->adapterId, channelIndex, ifPowerState, + pAdapter->ifPowerState[channelIndex]); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, SControlOffset, SControl); + MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, SControlOffset); + if (pAdapter->ifPowerState[channelIndex] == MV_SATA_IF_POWER_SLUMBER) + { + mvMicroSecondsDelay(pAdapter, 10000); + } + else + { + mvMicroSecondsDelay(pAdapter, 10); + } + SStatus = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, SStatusOffset); + IPM = getRegField(SStatus, 8, 4); + if (IPM != ifPowerState) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: " + "mvSataSetInterfacePowerState: IPM (0x%x) doesn't match the " + "requested state 0x%x (prev 0x%x)\n", + pAdapter->adapterId, channelIndex, IPM, ifPowerState, + pAdapter->ifPowerState[channelIndex]); + pAdapter->ifPowerState[channelIndex] = MV_SATA_IF_POWER_SLUMBER; + return MV_FALSE; + } + pAdapter->ifPowerState[channelIndex] = ifPowerState; + return MV_TRUE; +} +/******************************************************************************* +* mvSataGetInterfacePowerState - Gets the sata interface power state of a +* specific SATA channel +* +* DESCRIPTION: +* Gets the interface power state of a specific SATA channel from the HW +* registers (SStatus) +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific EDMA channel +* ifPowerState - sata interface power state +* +* RETURN: +* ifPowerState - sata interface power state +* COMMENTS: +* +*******************************************************************************/ +MV_BOOLEAN mvSataGetInterfacePowerState (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_SATA_IF_POWER_STATE *ifPowerState) +{ + MV_U32 SStatusOffset = getEdmaRegOffset(channelIndex) + + MV_SATA_II_S_STATUS_REG_OFFSET; + + MV_U32 SStatus; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataGetInterfacePowerState Failed, Bad adapter data structure" + " pointer\n"); + return MV_FALSE; + } + if (channelIndex >= pAdapter->numberOfChannels) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + "mvSataGetInterfacePowerState Failed, bad channel index\n"); + return MV_FALSE; + } + if (pAdapter->sataAdapterGeneration < MV_SATA_GEN_II) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: " + "mvSataGetInterfacePowerState Failed, adapter not supported\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + if (pAdapter->staggaredSpinup[channelIndex] == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: " + "mvSataGetInterfacePowerState Failed, sata link not established yet\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + + SStatus = MV_REG_READ_DWORD (pAdapter->adapterIoBaseAddress, SStatusOffset); + *ifPowerState = getRegField(SStatus, 8, 4); + return MV_TRUE; +} +#if defined (MV_SUPPORT_ATAPI) || defined (MV_SATA_C2C_COMM) +static void activateBMDmaMode(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 prdTableHi, + MV_U32 prdTableLow, + MV_UDMA_TYPE dmaType) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + MV_BUS_ADDR_T ioBaseAddr = pAdapter->adapterIoBaseAddress; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + " activateBMDmaMode: BMDMA status(1) 0x%08x\n", + MV_REG_READ_DWORD (ioBaseAddr, + getEdmaRegOffset(pSataChannel->channelNumber) +MV_BMDMA_STATUS_OFFSET) + ); + if(pAdapter->hostInterface == MV_HOST_IF_INTEGRATED) + { + _setRegBits(ioBaseAddr, pSataChannel->eDmaRegsOffset + 0x6C, MV_BIT0); + } + + + MV_REG_WRITE_DWORD (ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_BMDMA_COMMAND_OFFSET, 0); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + " activateBMDmaMode: BMDMA status(2) 0x%08x\n", + MV_REG_READ_DWORD (ioBaseAddr, + getEdmaRegOffset(pSataChannel->channelNumber) +MV_BMDMA_STATUS_OFFSET) + ); + + MV_REG_WRITE_DWORD (ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_BMDMA_PRD_TABLE_LOW_ADDRESS_OFFSET, prdTableLow); + MV_REG_WRITE_DWORD (ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_BMDMA_PRD_TABLE_HIGH_ADDRESS_OFFSET, prdTableHi); + + if (dmaType == MV_UDMA_TYPE_READ) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: Activate BM-DMA in write Mode" + " (Read from disk)\n", pAdapter->adapterId, channelIndex); + MV_REG_WRITE_DWORD (ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_BMDMA_COMMAND_OFFSET, MV_BIT3 | MV_BIT0); + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: Activate BM-DMA in read Mode" + " (Writes to disk)\n", pAdapter->adapterId, channelIndex); + MV_REG_WRITE_DWORD (ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_BMDMA_COMMAND_OFFSET, MV_BIT0); + } +} +#endif +/*================C2C functions==========================================*/ +#ifdef MV_SATA_C2C_COMM +/******************************************************************************* +* mvSataC2CInit - setup channel-to-channel communication mode on +* specific SATA channel +* +* DESCRIPTION: +* Initializes channel for channel-to-channel communication mode +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific SATA channel +* mvSataC2CMode - Comunication mode for the channel: +* target or initiator +* +* mvSataC2CCallBack - callback function called on channel 2 channel +* communication event +* +* RETURN: +* MV_TRUE on success +* MV_FALSE on error +* +* COMMENTS: +* +*******************************************************************************/ + +MV_BOOLEAN mvSataC2CInit (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_SATA_C2C_MODE mvSataC2CMode, + C2CCallBack_t mvSataC2CCallBack) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_U32 regVal; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataC2CInit" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + ioBaseAddr = pAdapter->adapterIoBaseAddress; + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataC2CInit Failed" + ", channel data structure not allocated\n", + pAdapter->adapterId, channelIndex ); + return MV_FALSE; + } + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvSataC2CInit " + "failed, DMA is enabled\n", pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvSataC2CInit " + "failed, Feature not supported by this HW\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + + regVal = MV_REG_READ_DWORD (ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_SATA_CONFIG_REG_OFFSET); + /* Enable communication mode */ + regVal |= MV_BIT11; + /* Fix for 88SX60xx FEr SATA#8*/ + /* according to the spec, bits [31:12] must be set to 0x009B1 */ + regVal &= 0x00000FFF; + /* regVal |= MV_BIT12;*/ + regVal |= 0x009B1000; + + + if (mvSataC2CMode == MV_SATA_C2C_MODE_INITIATOR) + { + regVal |= MV_BIT10; /* Initiator */ + } + else + { + regVal &= ~MV_BIT10; /* Target */ + } + + maskEdmaInterrupts(pAdapter, channelIndex); + + MV_REG_WRITE_DWORD (ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_SATA_CONFIG_REG_OFFSET, regVal); + + _channelHardReset(pAdapter, channelIndex); + + pSataChannel->C2CmodeEnabled = MV_TRUE; + pSataChannel->C2CMode = mvSataC2CMode; + pSataChannel->C2CCallback = mvSataC2CCallBack; + + mvSataMaskAdapterInterrupt(pAdapter); + pAdapter->mainMask |= SaDevInterrutpBit(channelIndex); + mvSataUnmaskAdapterInterrupt(pAdapter); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: mvSataC2CInit %s mode\n", + pAdapter->adapterId, channelIndex, + (mvSataC2CMode == MV_SATA_C2C_MODE_INITIATOR) ? "Initiator" : + "Target"); + + mvOsSemRelease(&pSataChannel->semaphore); + return MV_TRUE; +} + + +/******************************************************************************* +* mvSataC2CStop - Stop channel to channel communication mode +* +* DESCRIPTION: +* Stop channel to channel communication mode on +* specific SATA channel +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific SATA channel +* +* RETURN: +* MV_TRUE on success +* MV_FALSE on error +* +* COMMENTS: +* +*******************************************************************************/ + +MV_BOOLEAN mvSataC2CStop (MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_U32 regVal; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvSataC2CStop" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + ioBaseAddr = pAdapter->adapterIoBaseAddress; + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvSataC2CStop Failed" + ", channel data structure not allocated\n", + pAdapter->adapterId, channelIndex ); + return MV_FALSE; + } + mvOsSemTake(&pSataChannel->semaphore); + + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvSataC2CStop " + "failed, DMA is enabled\n", pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + + regVal = MV_REG_READ_DWORD (ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_SATA_CONFIG_REG_OFFSET); + regVal &= ~MV_BIT11; /* Disable communication mode */ + /* Fix for 88SX60xx FEr SATA#8*/ + /* according to the spec, bits [31:12] must be set to 0x009B1 */ + regVal &= 0x00000FFF; + /* regVal |= MV_BIT12;*/ + regVal |= 0x009B1000; + + MV_REG_WRITE_DWORD (ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_SATA_CONFIG_REG_OFFSET, regVal); + MV_REG_READ_DWORD (ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_SATA_CONFIG_REG_OFFSET); + mvSataMaskAdapterInterrupt(pAdapter); + pAdapter->mainMask &= ~SaDevInterrutpBit(channelIndex); + mvSataUnmaskAdapterInterrupt(pAdapter); + + _channelHardReset(pAdapter, channelIndex); + pSataChannel->C2CmodeEnabled = MV_FALSE; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: mvSataC2CStop\n", + pAdapter->adapterId, channelIndex); + + mvOsSemRelease(&pSataChannel->semaphore); + return MV_TRUE; +} + + + +/******************************************************************************* +* mvSataC2CSendRegisterDeviceToHostFIS - sends Register device to host FIS +* +* DESCRIPTION: +* Sends Register device to host FIS +* used for channel-to-channel communication mode on +* specific SATA channel +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific SATA channel +* pmPort - port multiplier port +* bInterrupt - determine whether the interrupt is being generated on +* the receiver side +* msg - message containing 10 bytes of user data +* +* RETURN: +* MV_TRUE on success +* MV_FALSE on error +* +* COMMENTS: +* +*******************************************************************************/ + +MV_BOOLEAN mvSataC2CSendRegisterDeviceToHostFIS( + MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 pmPort, + MV_BOOLEAN bInterrupt, + MV_U8 msg[MV_C2C_MESSAGE_SIZE]) + +{ + + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_U32 buffer[5]; + MV_BOOLEAN res; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d " + "mvSataC2CSendRegisterDeviceToHostFIS failed - " + "Bad adapter data structure pointer.\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + + ioBaseAddr = pAdapter->adapterIoBaseAddress; + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d " + "mvSataC2CSendRegisterDeviceToHostFIS failed - " + "channel data structure not allocated.\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + mvOsSemTake(&pSataChannel->semaphore); + + if (pSataChannel->C2CmodeEnabled == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvSataC2CInitiator" + "mvSataC2CSendRegisterDeviceToHostFIS failed - " + "Bad C2C configuration.\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + + buffer[0] = MV_SATA_REGISTER_HOST_2_DEVICE_FIS; + buffer[0] |= ((MV_U32)(pmPort & 0xF)) << 8; + if (MV_TRUE == bInterrupt) + { + buffer[0] |= 1 << 14; + } + buffer[0] |= ((MV_U32)msg[0]) << 24; + buffer[1] = msg[1] | + ((MV_U32)msg[2]) << 8 | + ((MV_U32)msg[3]) << 16 | + ((MV_U32)msg[4]) << 24; + buffer[2] = msg[5] | + ((MV_U32)msg[6]) << 8 | + ((MV_U32)msg[7]) << 16; + buffer[3] = msg[8] | + ((MV_U32)msg[9]) << 8; + buffer[4] = 0; + res = sendVendorUniqueFIS(pAdapter, + channelIndex, + (MV_U32*)buffer, + 5); + mvOsSemRelease(&pSataChannel->semaphore); + return res; +} + + + +/******************************************************************************* +* mvSataC2CActivateBmDma - activate B-M DMA +* +* DESCRIPTION: +* Activates Bus Master DMA for the specific SATA channel +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific EDMA channel +* pmPort - port multiplier port +* prdTableHi - upper 32 bits of PRD table address +* prdTableHi - lower 32 bits of PRD table address +* dmaType - DMA type (read o write) from the initiator point + of view +* +* RETURN: +* MV_TRUE on success +* MV_FALSE on error +* +* COMMENTS: +* +*******************************************************************************/ + +MV_BOOLEAN mvSataC2CActivateBmDma(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 pmPort, + MV_U32 prdTableHi, + MV_U32 prdTableLow, + MV_UDMA_TYPE dmaType) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_BOOLEAN res = MV_TRUE; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d " + "mvSataC2CActivateBmDma failed - " + "Bad adapter data structure pointer.\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + ioBaseAddr = pAdapter->adapterIoBaseAddress; + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d " + "mvSataC2CActivateBmDma failed - " + "channel data structure not allocated\n", + pAdapter->adapterId, channelIndex ); + return MV_FALSE; + } + mvOsSemTake(&pSataChannel->semaphore); + if (pSataChannel->C2CmodeEnabled == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d " + "mvSataC2CActivateBmDma failed - " + "bad C2C configuration.\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + if (pSataChannel->C2CMode == MV_SATA_C2C_MODE_TARGET) + { + activateBMDmaMode(pAdapter, channelIndex, + prdTableHi, prdTableLow, + (dmaType == MV_UDMA_TYPE_WRITE) ? + MV_UDMA_TYPE_READ : MV_UDMA_TYPE_WRITE); + if (dmaType == MV_UDMA_TYPE_WRITE) + { + MV_U32 buffer[1] = {MV_SATA_DMA_ACTIVATE_FIS}; + + buffer[0] |= ((MV_U32)(pmPort & 0xF)) << 8; + res = sendVendorUniqueFIS(pAdapter, + channelIndex, + (MV_U32*)buffer, + 1); + } + else + { + MV_U32 val = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->sataChannel[channelIndex]->eDmaRegsOffset + + MV_SATA_II_IF_CONTROL_REG_OFFSET); + val |= MV_BIT16; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->sataChannel[channelIndex]->eDmaRegsOffset + + MV_SATA_II_IF_CONTROL_REG_OFFSET, + val); + } + } + else + { + activateBMDmaMode(pAdapter, channelIndex, prdTableHi, prdTableLow, + dmaType); + } + mvOsSemRelease(&pSataChannel->semaphore); + return res; +} + + +/******************************************************************************* +* mvSataC2CResetBmDma - reset B-M DMA +* +* DESCRIPTION: +* Reset Bus Master DMA for the specific SATA channel +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific EDMA channel +* +* RETURN: +* MV_TRUE on success +* MV_FALSE on error +* +* COMMENTS: +* +*******************************************************************************/ + +MV_BOOLEAN mvSataC2CResetBmDma(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d " + "mvSataC2CResetBmDma failed - " + "Bad adapter data structure pointer.\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel) + { + + mvOsSemTake(&pSataChannel->semaphore); + } + + _resetBmDma(pAdapter, channelIndex); + + if (pSataChannel) + { + mvOsSemRelease(&pSataChannel->semaphore); + } + return MV_TRUE; +} +#endif +void _resetBmDma(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_BUS_ADDR_T ioBaseAddr = pAdapter->adapterIoBaseAddress; + MV_U32 val; + MV_U8 port = channelIndex & (MV_BIT0 | MV_BIT1); + MV_U8 sataUnit = (channelIndex & MV_BIT2) >> 2; + MV_U32 unitCauseAddr = MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET; + + /*Reset bm dma*/ + val = MV_REG_READ_DWORD (ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_BMDMA_COMMAND_OFFSET); + /*The DMA direction must be preserved*/ + val &= ~MV_BIT0; + MV_REG_WRITE_DWORD (ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_BMDMA_COMMAND_OFFSET, val); + + MV_REG_WRITE_DWORD(ioBaseAddr, + getEdmaRegOffset(channelIndex) + + MV_SATA_II_IF_CONTROL_REG_OFFSET, + 0); + /*clear BM Done interrupt*/ + MV_REG_WRITE_DWORD(ioBaseAddr, unitCauseAddr, ~(1 << port)); +} +/******************************************************************************* +* sendVendorUniqueFIS - send vendor unique FIS +* +* DESCRIPTION: +* Performs vendor unique FIS transmission +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific SATA channel +* vendorUniqueBuffer - data buffer to transmit +* numOfDWords - number of double words in the buffer +* +* RETURN: +* MV_TRUE on success +* MV_FALSE on error +* +* COMMENTS: +* +* 1. Verify the Transport Layer is in idle, field TransFsmSts in +* Serial-ATA Interface Status Register is cleared. +* 2. Set Vendor Unique Mode. Write 1 to bit VendorUqMd in register +* Serial-ATA Interface Control Register. +* 3. Insert data into Vendor Unique Register. +* 4. Repeat steps 3 until all data except last Dword in the vendor unique +* FIS is transferred. Note that according to Serial-ATA protocol the +* FIS length is limited to 8 KB. +* 5. Write 1 to bit VendorUqSend in register Serial-ATA Interface Control +* Register. +* 6. Write last Dword in the FIS to Complete FIS transmission. +* 7. Wait for transmission completion. Bit VendorUqDn or bit VendorUqErr +* in Serial-ATA Interface Status Register is set to 1. +* 8. Verify successful transmission of the FIS. Bit VendorUqErr in +* Serial-ATA Interface Status Register is cleared. +* 9. Clear Vendor Unique Mode. Write 0 to bit VendorUqMd in register +* Serial-ATA Interface Control Register. +*******************************************************************************/ +static MV_BOOLEAN sendVendorUniqueFIS(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U32 *vendorUniqueBuffer, + MV_U8 numOfDWords) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + MV_BUS_ADDR_T ioBaseAddr = pAdapter->adapterIoBaseAddress; + MV_U32 regVal; + MV_U8 i; + MV_BOOLEAN res = MV_FALSE; + + regVal = MV_REG_READ_DWORD(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_IF_STATUS_REG_OFFSET); + + if (regVal & MV_SATA_II_IF_STATUS_FSM_STATUS_MASK) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: ERROR : sendVendorUniqueFIS" + " Transport Layer is not in Idle status\n", pAdapter->adapterId, + channelIndex); + return MV_FALSE; + } + + /* Set Vendor Unique Mode */ + MV_REG_WRITE_DWORD(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_IF_CONTROL_REG_OFFSET, MV_BIT8); + + for (i = 1; i < numOfDWords; i++) + { + MV_REG_WRITE_DWORD(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_VENDOR_UQ_REG_OFFSET, + vendorUniqueBuffer[i - 1]); + } + + /* Write 1 to bit VendorUqSend */ + MV_REG_WRITE_DWORD(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_IF_CONTROL_REG_OFFSET, MV_BIT9|MV_BIT8); + + MV_REG_WRITE_DWORD(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_VENDOR_UQ_REG_OFFSET, + vendorUniqueBuffer[i - 1]); + + + /* polling with timeout*/ + for (i = 0; i < 200; i++) + { + regVal = MV_REG_READ_DWORD(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_IF_STATUS_REG_OFFSET); + + if (regVal & (MV_SATA_II_IF_STATUS_VUQ_DONE_MASK | + MV_SATA_II_IF_STATUS_VUQ_ERR_MASK)) + { + if (regVal & MV_SATA_II_IF_STATUS_VUQ_DONE_MASK) + { + res = MV_TRUE; + break; + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: ERROR" + "sendVendorUniqueFIS operation failed. " + "regVal = 0x%08x\n", + pAdapter->adapterId, channelIndex, regVal); + break; + } + } + mvMicroSecondsDelay(pAdapter, 1); + } + /* Clear Vendor Unique Mode */ + MV_REG_WRITE_DWORD(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_SATA_II_IF_CONTROL_REG_OFFSET, 0); + + if (res != MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: ERROR in sendVendorUniqueFI" + "S operation didn't finish. regVal = 0x%08x\n", + pAdapter->adapterId, channelIndex, regVal); + } + return res; +} + +/******************************************************************************* +* mvSata60X1B2CheckDevError - check if device errors occurred +* +* DESCRIPTION: +* This function checks if the drive reported device errors, the 60X1 B2 +* may not issue error interrupt when the device error reported after +* transferring part of the data, this function need to be called every +* period of time(e.g 0.5 seconds). +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - the index of the specific SATA channel +* +* RETURN: +* MV_TRUE if device error is reported +* MV_FALSE otherwise +* +* COMMENTS: +*******************************************************************************/ +MV_BOOLEAN mvSata60X1B2CheckDevError(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_U32 testCtrlReg; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, + " : mvSata60X1B2CheckDevError Failed, Bad adapter " + "data structure pointer\n"); + return MV_FALSE; + } + ioBaseAddr = pAdapter->adapterIoBaseAddress; + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, + " %d %d: mvSata60X1B2CheckDevError Failed, channel " + "data structure not allocated\n", pAdapter->adapterId, + channelIndex ); + return MV_FALSE; + } + mvOsSemTake(&pSataChannel->semaphore); + + if ((pAdapter->chipIs60X1B2 == MV_FALSE) || + (pSataChannel->queueCommandsEnabled == MV_FALSE) || + (pSataChannel->EdmaActive == MV_FALSE) || + (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED)) + { + mvOsSemRelease(&pSataChannel->semaphore); + return MV_FALSE; + } + mvOsSemRelease(&pSataChannel->semaphore); + + testCtrlReg = MV_REG_READ_DWORD (ioBaseAddr, + pSataChannel->eDmaRegsOffset + + MV_SATA_II_IF_TEST_CTRL_REG_OFFSET); + if (testCtrlReg & 0xFFFF0000) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d: PortNumDevErr is set 0x%04x\n", + pAdapter->adapterId, + channelIndex, + (testCtrlReg >> 16) & 0xFFFF); + MV_REG_WRITE_DWORD (ioBaseAddr, + pSataChannel->eDmaRegsOffset + + MV_EDMA_COMMAND_REG_OFFSET, + MV_EDMA_COMMAND_DISABLE_MASK); + handleSelfDisable(pAdapter, channelIndex, MV_BIT7|MV_BIT2); + return MV_TRUE; + } + return MV_FALSE; +} + +MV_BOOLEAN mvSataIfD2HReceived(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 port) +{ + MV_U32 regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegOffst[ channelIndex] + + MV_SATA_II_IF_STATUS_REG_OFFSET); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + " %d %d: mvSataIfD2HReceived: if status reg %08x\n", + pAdapter->adapterId, + channelIndex, + regVal); + if(((regVal & 0xFF) == 0x34) && (((regVal >> 8) & 0xF) == port)) + return MV_TRUE; + + return MV_FALSE; +} + +#ifdef MV_SATA_IO_GRANULARITY + +/*Public functions*/ + +/******************************************************************************* +* mvSataEnableIoGranularity - Enable/disable I/O granularity for the specific +* SATA adapter +* +* DESCRIPTION: +* Enable/disable I/O granularity for the specific +* SATA adapter. if IO/granularity is enabled, the function masks +* all channel's and channel coalescing interrupts and enables +* I/O granularity coalescing interupts +* INPUT: +* pAdapter - pointer to the adapter data structure. +* enable - MV_TRUE to enable I/O granularity +* MV_FALSE to disable I/O granularity +* +* RETURN: +* MV_TRUE if succeed +* MV_FALSE otherwise +* +* COMMENTS: +* +*******************************************************************************/ + +MV_BOOLEAN mvSataEnableIoGranularity(MV_SATA_ADAPTER *pAdapter, + MV_BOOLEAN enable) +{ + MV_U32 i; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d: " + "mvSataEnableIoGranularity Failed, Bad adapter data structure" + " pointer\n", pAdapter->adapterId); + return MV_FALSE; + } + if (pAdapter->sataAdapterGeneration < MV_SATA_GEN_II) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d: " + "mvSataEnableIoGranularity Failed, Feature is not supported by HW\n", + pAdapter->adapterId); + return MV_FALSE; + } + if (enable) + { + if (MV_TRUE == pAdapter->iogEnabled) + { + return MV_TRUE; + } + mvOsSemTake(&pAdapter->iogSemaphore); + for (i = 0; i < MV_IOG_QUEUE_SIZE; i++) + { + pAdapter->iogFreeIdsStack[i] = i; + + } + pAdapter->iogFreeIdsNum = MV_IOG_QUEUE_SIZE; + pAdapter->iogEnabled = MV_TRUE; + mvOsSemRelease(&pAdapter->iogSemaphore); + + mvOsSemTake(&pAdapter->interruptsMaskSem); + pAdapter->mainMask &= ~(MV_BIT1 | MV_BIT3 | MV_BIT5 | MV_BIT7 | + MV_BIT10 | MV_BIT12 | MV_BIT14 | MV_BIT16 | + MV_BIT17 | MV_BIT8); + pAdapter->mainMask |= MV_IOG_TRANS_INT_MASK; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, + pAdapter->mainMask); + mvOsSemRelease(&pAdapter->interruptsMaskSem); + + } + else + { + if (MV_FALSE == pAdapter->iogEnabled) + { + return MV_TRUE; + } + + mvOsSemTake(&pAdapter->interruptsMaskSem); + pAdapter->mainMask &= ~MV_IOG_TRANS_INT_MASK; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, + pAdapter->mainMask); + mvOsSemRelease(&pAdapter->interruptsMaskSem); + + mvOsSemTake(&pAdapter->iogSemaphore); + pAdapter->iogFreeIdsNum = 0; + pAdapter->iogEnabled = MV_FALSE; + mvOsSemRelease(&pAdapter->iogSemaphore); + } + return MV_TRUE; +} +/*Static functions*/ + +/******************************************************************************* +* setIoGranularityCount - Set I/O granularity transaction control register. +* +* DESCRIPTION: +* This function Sets I/O granularity transaction control register for +* specific transaction ID +* +* INPUT: +* pAdapter - Pointer to the MV88SX60XX adapter data structure. +* transId - transaction ID +* counter - I/O granularity counter transaction for current +* transaction Id +* +* RETURN: +* None +* +* COMMENTS: +* This function assumes that the channel semaphore is locked. +* +*******************************************************************************/ + +static void setIoGranularityCount(MV_SATA_ADAPTER *pAdapter, + MV_U8 transId, + MV_U8 counter) +{ + MV_U32 offset = MV_IOG_TRANS_CTRL_REG_OFFSET + transId; + MV_U8 value = (counter & 0x1F); + MV_REG_WRITE_BYTE(pAdapter->adapterIoBaseAddress, offset, value); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG | MV_DEBUG_UDMA_COMMAND, + " %d : setIoGranularityCount " + "writing 0x%X to 0x%X, transId = 0x%X\n", + pAdapter->adapterId, value, offset, transId); +} + +/******************************************************************************* +* readIoGranularityCount - Read I/O granularity transaction control register. +* +* DESCRIPTION: +* This function reads I/O granularity transaction control register for +* specific transaction ID +* +* INPUT: +* pAdapter - Pointer to the MV88SX60XX adapter data structure. +* transId - transaction ID +* +* +* RETURN: +* I/O granularity counter for transaction Id +* +* COMMENTS: +* This function assumes that the channel semaphore is locked. +* +*******************************************************************************/ +static MV_U8 readIoGranularityCount(MV_SATA_ADAPTER *pAdapter, + MV_U8 transId) +{ + MV_U32 offset = MV_IOG_TRANS_CTRL_REG_OFFSET + transId; + MV_U8 value = MV_REG_READ_BYTE(pAdapter->adapterIoBaseAddress, offset); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_INTERRUPTS, " %d : readIoGranularityCount " + "reading 0x%X from 0x%X, transId = 0x%X\n", + pAdapter->adapterId, value, offset, transId); + return value; +} + + +/******************************************************************************* +* checkIogBit - Check bit of I/O granularity cause register. +* +* DESCRIPTION: +* Checks bits in I/O granularity cause register for completion +* +* INPUT: +* pAdapter - Pointer to the MV88SX60XX adapter data structure. +* bitOffset - bit offset in register for current transaction id +* value - register value +* +* RETURN: +* None +* +* COMMENTS: +* Assume that is function is called while IO granularity semaphore is +* locked +*******************************************************************************/ + +static void checkIogBit(MV_SATA_ADAPTER *pAdapter, + MV_U8 bitOffset, + MV_U8 value) +{ + MV_U32 i; + MV_U8 id = 0x40; + for (i = 0; i < 8; i++) + { + if ((value >> i) & 0x1) + { + MV_U8 iogCount; + id = bitOffset + i; + iogCount = readIoGranularityCount(pAdapter, id); + if (iogCount > 0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_INTERRUPTS, + " %d: unexpected IO granularity " + "transaction counter = %d > 0\n", + pAdapter->adapterId, iogCount); + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_INTERRUPTS, + " %d: IO granularity transaction Id 0x%X done.\n", + pAdapter->adapterId, id); + } + pAdapter->iogFreeIdsStack[pAdapter->iogFreeIdsNum++] = id; + } + } +} + +/******************************************************************************* +* checkIogCompletion - Check bit of I/O granularity cause register. +* +* DESCRIPTION: +* Checks I/O granularity completion +* +* INPUT: +* pAdapter - Pointer to the MV88SX60XX adapter data structure. +* iogCause - I/O granularity cause register value +* Offset - 0 if transaction Id is 0-31, 32 if transaction Id 32-63 +* +* RETURN: +* None +* +* COMMENTS: +* +*******************************************************************************/ + +static void checkIogCompletion(MV_SATA_ADAPTER *pAdapter, + MV_U32 iogCause, MV_U8 offset) +{ + MV_U32 id; + MV_U8 byte; + + if (iogCause & 0xFFFF0000) + { + byte = (MV_U8)(iogCause >> 24); + if (byte) + { + checkIogBit(pAdapter, (offset) + 24, byte); + } + byte = (MV_U8)((iogCause >> 16) & 0xFF); + if (byte) + { + checkIogBit(pAdapter, (offset) + 16, byte); + } + } + if (iogCause & 0x0000FFFF) + { + byte = (MV_U8)(iogCause >> 8); + if (byte) + { + checkIogBit(pAdapter, (offset) + 8, byte); + } + byte = (MV_U8)(iogCause & 0xFF); + if (byte) + { + checkIogBit(pAdapter, (offset), byte); + } + } +} + +/******************************************************************************* +* iogInterrupt - I/O granularity ISR. +* +* DESCRIPTION: +* Checks bit of I/O granularity cause register for +* specific transaction ID +* +* INPUT: +* pAdapter - Pointer to the MV88SX60XX adapter data structure. +* ioBaseAddr - SATA Adapter base address +* mainCause - interrupt cause register +* +* RETURN: +* None +* +* COMMENTS: +* +*******************************************************************************/ + +static void iogInterrupt(MV_SATA_ADAPTER *pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 mainCause) +{ + MV_U32 iogCauseRegister; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG | MV_DEBUG_INTERRUPTS, + " %d: IO Granularity Interrupt." + "Cause = 0x%08x", pAdapter->adapterId, mainCause); + if (mainCause & MV_IOG_TRANS_LOW_BIT) + { + + iogCauseRegister = MV_REG_READ_DWORD(ioBaseAddr, + MV_IOG_TRANS_LOW_REG_OFFSET); + MV_REG_WRITE_DWORD (ioBaseAddr, + MV_IOG_TRANS_LOW_REG_OFFSET, + ~iogCauseRegister); + if (MV_TRUE == pAdapter->iogEnabled) + checkIogCompletion(pAdapter, iogCauseRegister, 0); + } + if (mainCause & MV_IOG_TRANS_HIGH_BIT) + { + iogCauseRegister = MV_REG_READ_DWORD(ioBaseAddr, + MV_IOG_TRANS_HIGH_REG_OFFSET); + MV_REG_WRITE_DWORD (ioBaseAddr, + MV_IOG_TRANS_HIGH_REG_OFFSET, + ~iogCauseRegister); + if (MV_TRUE == pAdapter->iogEnabled) + checkIogCompletion(pAdapter, iogCauseRegister, 32); + } +} + + +/******************************************************************************* +* iogReset - reset all settings in HW related to I/O granularity. +* +* DESCRIPTION: +* The function is executed when the error is occured and IO granularity +* is enabled for the adapter. The function performs the following +* operations +* 1. IO granularity interrupts are masked +* 2. Clear IO granularity cause registers +* 3. Reset all IO granularity transcation counters +* +* INPUT: +* pAdapter - Pointer to the MV88SX60XX adapter data structure. +* +* RETURN: +* None +* +* COMMENTS: +* +*******************************************************************************/ + +static MV_BOOLEAN iogReset(MV_SATA_ADAPTER *pAdapter) +{ + MV_U32 i; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d: IO Granularity error handler is executed.\n.", + pAdapter->adapterId); + /*Mask IO Granularity interrupt*/ + mvOsSemTake(&pAdapter->interruptsMaskSem); + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset, + (pAdapter->mainMask & (~MV_IOG_TRANS_INT_MASK))); + mvOsSemRelease(&pAdapter->interruptsMaskSem); + + mvOsSemTake(&pAdapter->iogSemaphore); + /*Clear IO Granularity cause registers*/ + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_IOG_TRANS_LOW_REG_OFFSET, + 0); + MV_REG_WRITE_DWORD (pAdapter->adapterIoBaseAddress, + MV_IOG_TRANS_HIGH_REG_OFFSET, + 0); + + /*Set all transaction counters to zero*/ + for (i = 0; i < MV_IOG_QUEUE_SIZE; i += 4) + { + MV_U32 offset = MV_IOG_TRANS_CTRL_REG_OFFSET + i; + MV_REG_WRITE_DWORD(pAdapter->adapterIoBaseAddress, offset, 0); + } + mvOsSemRelease(&pAdapter->iogSemaphore); +} + + + +#endif +static MV_U32 getRegField(MV_U32 regVal, MV_U32 fieldOff, MV_U32 bitsNum) +{ + MV_U32 mask = ((1 << bitsNum) - 1); + return(regVal >> fieldOff) & mask; +} + +#ifdef MV_LOGGER +void _dumpPCIRegs(MV_SATA_ADAPTER *pAdapter) +{ + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d " + "_dumpPCIRegs failed - " + "Bad adapter data structure pointer.\n", + pAdapter->adapterId); + return ; + } + if (pAdapter->hostInterface == MV_HOST_IF_INTEGRATED) + { + /* no pci interface*/ + return; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d :Dump PCI Regs\n", + pAdapter->adapterId); + + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%-25s %04x %08x\n", + "Main interrupt Cause",pAdapter->mainCauseOffset, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainCauseOffset)); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%-25s %04x %08x\n", + "Main interrupt Mask",pAdapter->mainMaskOffset, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + pAdapter->mainMaskOffset)); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%-25s %04x %08x\n", + "SErr Mask",0xC28, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, 0xc28)); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%-25s %04x %08x\n", + "Error Addr Low",0x1d40, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, 0x1d40)); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%-25s %04x %08x\n", + "Error Addr High",0x1d44, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, 0x1d44)); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%-25s %04x %08x\n", + "Error Attr",0x1d48, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, 0x1d48)); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%-25s %04x %08x\n", + "Error Command",0x1d50, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, 0x1d50)); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%-25s %04x %08x\n", + "Intr Cause",0x1d58, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, 0x1d58)); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%-25s %04x %08x\n", + "Intr Mask",0x1d5c, + MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, 0x1d5c)); +} + +void _dumpEDMARegs(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channelIndex) +{ + MV_U32 regVal, regOff; + + if (pMvSataAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d " + "_dumpEDMARegs failed - " + "Bad adapter data structure pointer.\n", + pMvSataAdapter->adapterId, channelIndex); + return; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d:Dump Edma HW Regs\n", + pMvSataAdapter->adapterId, channelIndex); + + regOff = edmaRegOffst[ channelIndex] + MV_EDMA_CONFIG_REG_OFFSET; + regVal = mvSataReadReg(pMvSataAdapter, regOff); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " EMDA CFG off 0x%08x val 0x%08x: depth 0x%x NCQ %x BURST SIZE %x " + "eQueue %x Stop On Err %x BURST EXT %x WRITE BURST SIZE %x\n", + regOff, regVal, + getRegField(regVal, 0, 5), + getRegField(regVal, 5, 1), + getRegField(regVal, 8, 1), + getRegField(regVal, 9, 1), + getRegField(regVal, 10, 1), + getRegField(regVal, 11, 1), + getRegField(regVal, 13, 1)); + + regOff = edmaRegOffst[ channelIndex] + MV_EDMA_INTERRUPT_ERROR_CAUSE_REG_OFFSET; + regVal = mvSataReadReg(pMvSataAdapter, regOff); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," Intr Cause off 0x%08x val 0x%08x\n", regOff, regVal); + + regOff = edmaRegOffst[ channelIndex] + MV_EDMA_INTERRUPT_ERROR_MASK_REG_OFFSET; + regVal = mvSataReadReg(pMvSataAdapter, regOff); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," Intr Mask off 0x%08x val 0x%08x\n", regOff, regVal); + + regOff = edmaRegOffst[ channelIndex] + MV_EDMA_REQUEST_Q_BAH_REG_OFFSET; + regVal = mvSataReadReg(pMvSataAdapter, regOff); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," Req AddrHi off 0x%08x val 0x%08x\n", regOff, regVal); + + regOff = edmaRegOffst[ channelIndex] + MV_EDMA_REQUEST_Q_INP_REG_OFFSET; + regVal = mvSataReadReg(pMvSataAdapter, regOff); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," Req INP off 0x%08x val 0x%08x: INP 0x%x BA 0x%x\n", + regOff, regVal, + getRegField(regVal, 5, 5), + getRegField(regVal, 10, 22)); + + regOff = edmaRegOffst[ channelIndex] + MV_EDMA_REQUEST_Q_OUTP_REG_OFFSET; + regVal = mvSataReadReg(pMvSataAdapter, regOff); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," Req OUTP off 0x%08x val 0x%08x: OUT 0x%x\n", + regOff, regVal, + getRegField(regVal, 5, 5)); + + regOff = edmaRegOffst[ channelIndex] + MV_EDMA_RESPONSE_Q_BAH_REG_OFFSET; + regVal = mvSataReadReg(pMvSataAdapter, regOff); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," Res AddrHi off 0x%08x val 0x%08x\n", + regOff, regVal); + + regOff = edmaRegOffst[ channelIndex] + MV_EDMA_RESPONSE_Q_INP_REG_OFFSET; + regVal = mvSataReadReg(pMvSataAdapter, regOff); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," Res INP off 0x%08x val 0x%08x: INP 0x%x\n", + regOff, regVal, + getRegField(regVal, 3, 5)); + + regOff = edmaRegOffst[ channelIndex] + MV_EDMA_RESPONSE_Q_OUTP_REG_OFFSET; + regVal = mvSataReadReg(pMvSataAdapter, regOff); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," Res OUTP off 0x%08x val 0x%08x: OUTP 0x%x BA 0x%x\n", + regOff, regVal, + getRegField(regVal, 3, 5), + getRegField(regVal, 8, 24)); + + regOff = edmaRegOffst[ channelIndex] + MV_EDMA_COMMAND_REG_OFFSET; + regVal = mvSataReadReg(pMvSataAdapter, regOff); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," Command off 0x%08x val 0x%08x: EN %x DIS %x HW RESET %x\n", + regOff, regVal, + getRegField(regVal, 0, 1), + getRegField(regVal, 1, 1), + getRegField(regVal, 2, 1)); + + regOff = edmaRegOffst[ channelIndex] + MV_EDMA_STATUS_REG_OFFSET; + regVal = mvSataReadReg(pMvSataAdapter, regOff); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR," Status off 0x%08x val 0x%08x: TAG 0x%x\n", + regOff, regVal, + getRegField(regVal, 0, 5)); + + if (pMvSataAdapter->sataAdapterGeneration == MV_SATA_GEN_IIE) + { +#define PRINT_REG(name, offset)\ + {\ + regOff = edmaRegOffst[ channelIndex] + (offset);\ + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR,"%s off 0x%08x val 0x%08x\n",\ + name, regOff, mvSataReadReg(pMvSataAdapter, regOff));\ + } + PRINT_REG("EDMA Halt Conditions Register", 0x60); + PRINT_REG("EDMA FSM Debug Status Register", 0x084); + PRINT_REG("EDMA Busy Status Register", 0x88); + PRINT_REG("EDMA TCQ Status Register", 0x08c); + PRINT_REG("EDMA Rx FIS Parser Register", 0x090); + PRINT_REG("EDMA NCQ0 Done/TCQ0 Outstanding Status Register", 0x098); + PRINT_REG("EDMA NCQ1 Done/TCQ1 Outstanding Status Register", 0x09c); + PRINT_REG("EDMA NCQ2 Done/TCQ2 Outstanding Status Register", 0x0a0); + PRINT_REG("EDMA NCQ3 Done/TCQ3 Outstanding Status Register", 0x0a4); + PRINT_REG("EDMA Interrupt Error 2 Cause Register", 0x064); + PRINT_REG("FIS Interrupt Cause Register", 0x364); + PRINT_REG("FIS Interrupt Mask Register", 0x368); + PRINT_REG("FIS DW0 Register", 0x370); + PRINT_REG("FIS DW1 Register", 0x374); + PRINT_REG("FIS DW2 Register", 0x378); + PRINT_REG("FIS DW3 Register", 0x37c); + PRINT_REG("FIS DW4 Register", 0x380); + PRINT_REG("FIS DW5 Register", 0x384); + PRINT_REG("FIS DW6 Register", 0x388); + + } + + + + + +} + +void _dumpChannelQueues(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_U32 i; + MV_U32 entries = MV_EDMA_QUEUE_LENGTH; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d " + "_dumpChannelQueues failed - " + "Bad adapter data structure pointer.\n", + pAdapter->adapterId, channelIndex); + return ; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "%d %d:Dump Channel Queues\n", + pAdapter->adapterId, channelIndex); + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: _dumpChannelQueues" + "el Failed, channel data structure not allocated\n", + pAdapter->adapterId, channelIndex); + return ; + } + + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "Request Qeueu Info:\n"); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " virt addr %p:\n", + pSataChannel->requestQueue); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " phy low addr %08x:\n", + pSataChannel->requestQueuePciLowAddress); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " phy high addr %08x:\n", + pSataChannel->requestQueuePciHiAddress); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " SW IN pointer %x:\n", + pSataChannel->reqInPtr); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "Request Qeueu Entries:\n"); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "Index [3:0] [7:4] [11:8] [15:12]\n"); + if (pSataChannel->use128Entries == MV_TRUE) + { + entries = MV_EDMA_GEN2E_QUEUE_LENGTH; + } + for (i = 0; i < entries; i++) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "[%2d] 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",i, + *((MV_U32 *)(pSataChannel->requestQueue + i)), + *(((MV_U32 *)(pSataChannel->requestQueue + i)) + 1), + *(((MV_U32 *)(pSataChannel->requestQueue + i)) + 2), + *(((MV_U32 *)(pSataChannel->requestQueue + i)) + 3), + *(((MV_U32 *)(pSataChannel->requestQueue + i)) + 4), + *(((MV_U32 *)(pSataChannel->requestQueue + i)) + 5), + *(((MV_U32 *)(pSataChannel->requestQueue + i)) + 6), + *(((MV_U32 *)(pSataChannel->requestQueue + i)) + 7)); + } + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "Responset Qeueu Info:\n"); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " virt addr %p:\n", + pSataChannel->responseQueue); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " phy low addr %08x:\n", + pSataChannel->responseQueuePciLowAddress); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " phy high addr %08x:\n", + pSataChannel->responseQueuePciHiAddress); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " SW OUT pointer %x:\n", + pSataChannel->rspOutPtr); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "Response Qeueu Entries:\n"); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "Index [1:0] [3:2] [7:4]\n"); + for (i = 0; i < entries; i++) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "[%2d] 0x%04x 0x%04x 0x%08x\n",i, + *((MV_U16 *)(pSataChannel->responseQueue + i)), + *(((MV_U16 *)(pSataChannel->responseQueue + i)) + 1), + *(((MV_U32 *)(pSataChannel->responseQueue + i)) + 1)); + } +} +void _dumpSataRegs(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_U32 regVal; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d " + "_dumpSataRegs failed - " + "Bad adapter data structure pointer.\n", + pAdapter->adapterId, channelIndex); + return; + } + + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegOffst[ channelIndex] + + MV_SATA_II_S_STATUS_REG_OFFSET); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " SStatus 0x%08x:\n", regVal); + + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegOffst[ channelIndex] + + MV_SATA_II_S_CONTROL_REG_OFFSET); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " SControl 0x%08x:\n", regVal); + + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegOffst[ channelIndex] + + MV_SATA_II_S_ERROR_REG_OFFSET); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " SError 0x%08x:\n", regVal); + + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegOffst[ channelIndex] + + MV_SATA_II_IF_CONTROL_REG_OFFSET); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " IF Ctrl 0x%08x: TXPort 0x%x\n", regVal, + getRegField(regVal, 0, 4)); + regVal = MV_REG_READ_DWORD(pAdapter->adapterIoBaseAddress, + edmaRegOffst[ channelIndex] + + MV_SATA_II_IF_STATUS_REG_OFFSET); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " IF status 0x%08x: RXFIS 0x%x RXPort 0x%x\n", regVal, + getRegField(regVal, 0, 8), + getRegField(regVal, 8, 4)); + } +} +void _printATARegs(MV_STORAGE_DEVICE_REGISTERS *pDeviceRegs) +{ + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " ATA Drive Registers:\n"); + if (pDeviceRegs == NULL) + { + return; + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%20s : %04x\n","Error", pDeviceRegs->errorRegister); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%20s : %04x\n","SectorCount", pDeviceRegs->sectorCountRegister); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%20s : %04x\n","LBA Low", pDeviceRegs->lbaLowRegister); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%20s : %04x\n","LBA Mid", pDeviceRegs->lbaMidRegister); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%20s : %04x\n","LBA High", pDeviceRegs->lbaHighRegister); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%20s : %04x\n","Device", pDeviceRegs->deviceRegister); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "%20s : %04x\n","Status", pDeviceRegs->statusRegister); +} + +#endif /*MV_LOGGER*/ + + + + + + diff --git a/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSata.h b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSata.h new file mode 100644 index 0000000..834c3d8 --- /dev/null +++ b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSata.h @@ -0,0 +1,781 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/******************************************************************************* +* mvSata.h - Header File for mvSata.c. +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* mvOs.h +* ATA/ATAPI-6 standard +* +*******************************************************************************/ +#ifndef __INCmvSatah +#define __INCmvSatah +#ifdef __cplusplus +extern "C" /*{*/ +#endif /* __cplusplus */ + +/* Includes */ +#include "mvOsS.h" +#include "mvRegs.h" + +/* Definitions */ +#define MV_CORE_DRIVER_LOG_ID 0 + + + +/* MV88SX50XX specific defines */ +#define MV_SATA_VENDOR_ID 0x11AB +#define MV_SATA_DEVICE_ID_5080 0x5080 +#define MV_SATA_DEVICE_ID_5081 0x5081 +#define MV_SATA_DEVICE_ID_5040 0x5040 +#define MV_SATA_DEVICE_ID_5041 0x5041 +#define MV_SATA_DEVICE_ID_6041 0x6041 +#define MV_SATA_DEVICE_ID_6081 0x6081 +#define MV_SATA_DEVICE_ID_6042 0x6042 +#define MV_SATA_DEVICE_ID_7042 0x7042 +#define MV_SATA_DEVICE_ID_5182 0x5182 /*88F5182 integrated sata*/ +#define MV_SATA_DEVICE_ID_5082 0x5082 /*88F5082 integrated sata*/ +#define MV_SATA_DEVICE_ID_6082 0x6082 /* Same device ID for 6082L */ +#define MV_SATA_DEVICE_ID_6490 0x6490 /*64660 integrated sata*/ + +#define MV_SATA_DEVICE_ID_78XX0 0x7800 /*78x00 Z0/Y0 integrated sata*/ +#define MV_SATA_DEVICE_ID_78100 0x7810 /*78100 integrated sata*/ +#define MV_SATA_DEVICE_ID_78200 0x7820 /*78200 integrated sata*/ +#define MV_SATA_DEVICE_ID_76100 0x7610 /*76100 integrated sata*/ +#define MV_SATA_DEVICE_ID_6323 0x6323 /*6323 integrated sata*/ + +#define MV_SATA_DEVICE_ID_6281 0x6281 /*88f6281 integrated sata*/ +#define MV_SATA_DEVICE_ID_6282 0x6282 /*88f6282 integrated sata*/ +#define MV_SATA_DEVICE_ID_6192 0x6192 /*88f6192 integrated sata*/ +#define MV_SATA_DEVICE_ID_6190 0x6190 /*88f6190 integrated sata*/ + +#define MV_SATA_CHANNELS_NUM 8 +#define MV_SATA_UNITS_NUM 2 + +#define MV_SATA_5082_PORT_NUM 1 +#define MV_SATA_5182_PORT_NUM 2 +#define MV_SATA_6082_PORT_NUM 1 +#define MV_SATA_6490_PORT_NUM 1 +#define MV_SATA_6281_PORT_NUM 2 +#define MV_SATA_6282_PORT_NUM 2 +#define MV_SATA_6192_PORT_NUM 2 +#define MV_SATA_6190_PORT_NUM 1 +#define MV_SATA_78XX0_PORT_NUM 2 +#define MV_SATA_76100_PORT_NUM 1 +#define MV_SATA_6323_PORT_NUM 1 + +#define MV_SATA_PM_MAX_PORTS 15 +#define MV_SATA_PM_CONTROL_PORT 15 + +#define MV_EDMA_QUEUE_LENGTH 32 /* Up to 32 outstanding */ +#define MV_EDMA_GEN2E_QUEUE_LENGTH 128 + +/* commands per SATA channel*/ +#ifndef MV_SATA_OVERRIDE_SW_QUEUE_SIZE + #define MV_SATA_SW_QUEUE_SIZE (MV_EDMA_QUEUE_LENGTH -1) +#else + #define MV_SATA_SW_QUEUE_SIZE MV_SATA_REQUESTED_SW_QUEUE_SIZE +#endif + +#ifdef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN + #ifndef MV_SATA_OVERRIDE_GEN2E_SW_QUEUE_SIZE + #define MV_SATA_GEN2E_SW_QUEUE_SIZE (MV_EDMA_GEN2E_QUEUE_LENGTH -1) + #else + #define MV_SATA_GEN2E_SW_QUEUE_SIZE MV_SATA_REQUESTED_GEN2E_SW_QUEUE_SIZE + #endif +#else + #define MV_SATA_GEN2E_SW_QUEUE_SIZE (MV_SATA_SW_QUEUE_SIZE) +#endif + +#if ((MV_SATA_SW_QUEUE_SIZE) >= (MV_EDMA_QUEUE_LENGTH)) +#error "FATAL ERROR: Bad Value for MV_SATA_SW_QUEUE_SIZE " +#endif +#if ((MV_SATA_GEN2E_SW_QUEUE_SIZE) >= (MV_EDMA_GEN2E_QUEUE_LENGTH)) +#error "FATAL ERROR: Bad Value for MV_EDMA_GEN2E_QUEUE_LENGTH " +#endif +#if ((MV_SATA_SW_QUEUE_SIZE) > (MV_SATA_GEN2E_SW_QUEUE_SIZE)) +#error "FATAL ERROR: MV_SATA_SW_QUEUE_SIZE bigger than MV_EDMA_GEN2E_QUEUE_LENGTH" +#endif + +#if (((MV_SATA_GEN2E_SW_QUEUE_SIZE) * 4) > ((MV_SATA_SW_QUEUE_SIZE) * 8)) +#define _MV_SATA_COMMANDS_PER_ADAPTER ((MV_SATA_GEN2E_SW_QUEUE_SIZE) * 4) +#else +#define _MV_SATA_COMMANDS_PER_ADAPTER ((MV_SATA_SW_QUEUE_SIZE) * 8) +#endif + +#define MV_EDMA_QUEUE_MASK 0x1F +#define MV_EDMA_REQUEST_ENTRY_SIZE 32 +#define MV_EDMA_RESPONSE_ENTRY_SIZE 8 +#define MV_EDMA_REQUEST_QUEUE_SIZE 1024 /* 32*32 = 1KBytes */ +#define MV_EDMA_RESPONSE_QUEUE_SIZE 256 /* 32*8 = 256 Bytes */ + +#define MV_EDMA_GEN2E_QUEUE_MASK 0x7F +#define MV_EDMA_GEN2E_REQUEST_QUEUE_SIZE 4096 /* 128*32 = 4KBytes */ +#define MV_EDMA_GEN2E_RESPONSE_QUEUE_SIZE 1024 /* 128*8 = 1KBytes */ + +#define MV_EDMA_PRD_ENTRY_SIZE 16 /* 16Bytes*/ +#define MV_EDMA_PRD_NO_SNOOP_FLAG MV_BIT0 +#define MV_EDMA_PRD_EOT_FLAG MV_BIT15 + +#define MV_ATA_IDENTIFY_DEV_DATA_LENGTH 256 /* number of words(2 byte)*/ +#define MV_ATA_MODEL_NUMBER_LEN 40 +#define ATA_SECTOR_SIZE 512 +#define ATA_SECTOR_SIZE_IN_WORDS 256 + +#define MV_SATA_COMM_INIT_DELAY 1000 /*1000 us*/ +#define MV_SATA_COMM_INIT_WAIT_DELAY 20000 /*20 ms*/ + +/*Channel to Channel*/ +#ifdef MV_SATA_C2C_COMM + #define MV_SATA_REGISTER_HOST_2_DEVICE_FIS 0x00000034 + #define MV_SATA_DMA_ACTIVATE_FIS 0x00000039 + #define MV_C2C_MESSAGE_SIZE 10 + +#endif + +#ifdef MV_SATA_IO_GRANULARITY + #define MV_IOG_QUEUE_SIZE 0x40 + #define MV_IOG_INVALID_COMMAND_ID MV_IOG_QUEUE_SIZE +#endif + +/* Typedefs */ +typedef enum mvUdmaType +{ + MV_UDMA_TYPE_READ, MV_UDMA_TYPE_WRITE +} MV_UDMA_TYPE; + +typedef enum mvFlushType +{ + MV_FLUSH_TYPE_CALLBACK, MV_FLUSH_TYPE_NONE +} MV_FLUSH_TYPE; + +typedef enum mvCompletionType +{ + MV_COMPLETION_TYPE_NORMAL, MV_COMPLETION_TYPE_ERROR, + MV_COMPLETION_TYPE_ABORT +} MV_COMPLETION_TYPE; + +typedef enum mvEventType +{ + MV_EVENT_TYPE_ADAPTER_ERROR, MV_EVENT_TYPE_SATA_CABLE, + MV_EVENT_TYPE_SATA_ERROR +} MV_EVENT_TYPE; + +typedef enum mvSataCableEvent +{ + MV_SATA_CABLE_EVENT_DISCONNECT = 0, + MV_SATA_CABLE_EVENT_CONNECT, + MV_SATA_CABLE_EVENT_PM_HOT_PLUG +} MV_SATA_CABLE_EVENT; + +typedef enum mvSataErrorEvent +{ + MV_SATA_RECOVERABLE_COMMUNICATION_ERROR = 0, + MV_SATA_UNRECOVERABLE_COMMUNICATION_ERROR, + MV_SATA_DEVICE_ERROR +} MV_SATA_ERROR_EVENT; + +#ifdef MV_SATA_C2C_COMM +typedef enum mvC2CEventType +{ + MV_C2C_REGISTER_DEVICE_TO_HOST_FIS_DONE, + MV_C2C_REGISTER_DEVICE_TO_HOST_FIS_ERROR, + MV_C2C_BM_DMA_DONE, + MV_C2C_BM_DMA_ERROR, +} MV_C2C_EVENT_TYPE; +#endif + +typedef enum mvEdmaMode +{ + MV_EDMA_MODE_QUEUED, + MV_EDMA_MODE_NOT_QUEUED, + MV_EDMA_MODE_NATIVE_QUEUING +} MV_EDMA_MODE; + +typedef enum mvQueueCommandResult +{ + MV_QUEUE_COMMAND_RESULT_OK = 0, + MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED, + MV_QUEUE_COMMAND_RESULT_FULL, + MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS, + MV_QUEUE_COMMAND_RESULT_BAD_PARAMS +} MV_QUEUE_COMMAND_RESULT; + +typedef enum mvNonUdmaProtocol +{ + MV_NON_UDMA_PROTOCOL_NON_DATA, + MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, + MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT, + MV_NON_UDMA_PROTOCOL_PACKET_PIO_NON_DATA, + MV_NON_UDMA_PROTOCOL_PACKET_PIO_DATA_IN, + MV_NON_UDMA_PROTOCOL_PACKET_PIO_DATA_OUT, + MV_NON_UDMA_PROTOCOL_PACKET_DMA, + MV_NON_UDMA_PROTOCOL_UNKNOWN +} MV_NON_UDMA_PROTOCOL; + +typedef enum mvSataGeneration +{ + MV_SATA_GEN_I, MV_SATA_GEN_II, MV_SATA_GEN_IIE +} MV_SATA_GEN; + +typedef enum mvSataInterfaceSpeed +{ + MV_SATA_IF_SPEED_1_5_GBPS, MV_SATA_IF_SPEED_3_GBPS, + MV_SATA_IF_SPEED_NO_LIMIT, MV_SATA_IF_SPEED_INVALID +} MV_SATA_IF_SPEED; + +typedef enum mvSataInterfacePowerState +{ + MV_SATA_IF_POWER_PHY_READY = 1, MV_SATA_IF_POWER_PARTIAL = 2, + MV_SATA_IF_POWER_SLUMBER = 6 +} MV_SATA_IF_POWER_STATE; + +#ifdef MV_SATA_C2C_COMM +typedef enum mvSataC2CMode +{ + MV_SATA_C2C_MODE_INITIATOR, MV_SATA_C2C_MODE_TARGET +} MV_SATA_C2C_MODE; +#endif + +typedef enum mvSataDeviceType +{ + MV_SATA_DEVICE_TYPE_UNKNOWN = 0, + MV_SATA_DEVICE_TYPE_ATA_DISK, + MV_SATA_DEVICE_TYPE_ATAPI_DEVICE, + MV_SATA_DEVICE_TYPE_PM +} MV_SATA_DEVICE_TYPE; + +typedef enum mvPMSwitchingmode +{ + MV_SATA_SWITCHING_MODE_NONE = 0, + MV_SATA_SWITCHING_MODE_CBS, + MV_SATA_SWITCHING_MODE_QCBS, + MV_SATA_SWITCHING_MODE_FBS, +}MV_SATA_SWITCHING_MODE; + +struct mvDmaRequestQueueEntry; +struct mvDmaResponseQueueEntry; +struct mvDmaCommandEntry; + +struct mvSataAdapter; +struct mvStorageDevRegisters; +struct mvSataChannel; + +typedef MV_BOOLEAN (* mvSataCommandCompletionCallBack_t)(struct mvSataAdapter *, + MV_U8, + MV_COMPLETION_TYPE, + MV_VOID_PTR, MV_U16, + MV_U32, + struct mvStorageDevRegisters *); +#ifdef MV_SATA_C2C_COMM +typedef MV_BOOLEAN (*C2CCallBack_t)(struct mvSataAdapter *, + struct mvSataChannel *, + MV_C2C_EVENT_TYPE event, + MV_U32 msgSize, + MV_U8* msg); + +#endif + +typedef enum mvQueuedCommandType +{ + MV_QUEUED_COMMAND_TYPE_UDMA, + MV_QUEUED_COMMAND_TYPE_NONE_UDMA, + MV_QUEUED_COMMAND_TYPE_PACKET +} MV_QUEUED_COMMAND_TYPE; + +#ifdef MV_SATA_IO_GRANULARITY +typedef enum mvIogQueuedCommandType +{ + MV_IOG_COMMAND_TYPE_FIRST, + MV_IOG_COMMAND_TYPE_NEXT +} MV_IOG_COMMAND_TYPE; +#endif + +typedef enum mvSataInterruptScheme +{ + MV_SATA_INTERRUPT_HANDLING_IN_ISR, + MV_SATA_INTERRUPT_HANDLING_IN_TASK, + MV_SATA_INTERRUPTS_DISABLED +}MV_SATA_INTERRUPT_SCHEME; + +typedef struct mvUdmaCommandParams +{ + MV_UDMA_TYPE readWrite; + MV_BOOLEAN isEXT; + MV_BOOLEAN FUA; + MV_U32 lowLBAAddress; + MV_U16 highLBAAddress; + MV_U16 numOfSectors; + MV_U32 prdLowAddr; + MV_U32 prdHighAddr; +#ifdef MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION + MV_BOOLEAN singleDataRegion; + MV_U16 byteCount; +#endif + mvSataCommandCompletionCallBack_t callBack; + MV_VOID_PTR commandId; +#ifdef MV_SATA_IO_GRANULARITY + MV_BOOLEAN ioGranularityEnabled; + MV_IOG_COMMAND_TYPE iogCommandType; + union + { + MV_U8 transId; + MV_U8 transCount; + } ioGranularityCommandParam; + MV_U8 iogCurrentTransId; +#endif +} MV_UDMA_COMMAND_PARAMS; + +typedef struct mvNoneUdmaCommandParams +{ + MV_NON_UDMA_PROTOCOL protocolType; + MV_BOOLEAN isEXT; + MV_U16_PTR bufPtr; + MV_U32 count; + MV_U16 features; + MV_U16 sectorCount; + MV_U16 lbaLow; + MV_U16 lbaMid; + MV_U16 lbaHigh; + MV_U8 device; + MV_U8 command; + mvSataCommandCompletionCallBack_t callBack; + MV_VOID_PTR commandId; +} MV_NONE_UDMA_COMMAND_PARAMS; + +typedef struct mvPacketCommandParams +{ + MV_NON_UDMA_PROTOCOL protocolType; + MV_U16_PTR bufPtr; + MV_U32 buffer_len; + MV_U32 transfered_data; + MV_U8 cdb_len; + MV_U16_PTR cdb_buffer; /*SCSI command desciptor block*/ + MV_U8 flags;/* bit 0:1-> DMA write*/ + /* bit 1:1-> single Data Region*/ + MV_U32 prdLowAddr; + MV_U32 prdHighAddr; + mvSataCommandCompletionCallBack_t callBack; + MV_VOID_PTR commandId; +} MV_PACKET_COMMAND_PARAMS; + +typedef struct mvQueueCommandInfo +{ + MV_QUEUED_COMMAND_TYPE type; + MV_U8 PMPort; + union + { + MV_UDMA_COMMAND_PARAMS udmaCommand; + MV_NONE_UDMA_COMMAND_PARAMS NoneUdmaCommand; + MV_PACKET_COMMAND_PARAMS packetCommand; + } commandParams; +} MV_QUEUE_COMMAND_INFO; + +/* The following structure is for the Core Driver internal usage */ +typedef struct mvQueuedCommandEntry +{ + MV_BOOLEAN isFreeEntry; + /*MV_U8 commandTag;*/ + MV_U8 hostTag; + MV_U8 deviceTag; + MV_BOOLEAN isCommandInEdma:1; + MV_BOOLEAN commandAborted:1; + struct mvQueuedCommandEntry *next; + struct mvQueuedCommandEntry *prev; + MV_QUEUE_COMMAND_INFO *pCommandInfo; +#ifndef MV_SATA_STORE_COMMANDS_INFO_ON_IAL_STACK + MV_QUEUE_COMMAND_INFO commandInfo; +#endif +} MV_QUEUED_COMMAND_ENTRY; + + +typedef enum mvErrorHandlingState +{ + MV_ERROR_HANDLING_STATE_IDLE, + MV_ERROR_HANDLING_STATE_WAIT_FOR_COMPLETIONS, + MV_ERROR_HANDLING_STATE_WAIT_FOR_BUSY, + MV_ERROR_HANDLING_STATE_REQUEST_SENSE +}MV_ERROR_HANDLING_STATE; + +typedef struct +{ + MV_ERROR_HANDLING_STATE state; + MV_U16 PortsWithErrors;/*which ports reported errors*/ + MV_U8 CurrPort; + MV_QUEUED_COMMAND_ENTRY *pReadLogExtEntry; + MV_U16_PTR ReadLogExtBuffer; + MV_BOOLEAN useVendorUniqGen2WA; +}MV_ERROR_HANDLING_INFO; + +/*for internal usage*/ +#define MV_SATA_TAGS_PER_POOL 32 +#ifdef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN + #define MV_SATA_GEN2E_TAG_POOLS_NUM (MV_SATA_PM_MAX_PORTS + 1) + #define MV_SATA_GEN2E_TAG_PMPORT_MASK 0x0F +#else + #define MV_SATA_GEN2E_TAG_POOLS_NUM 1 + #define MV_SATA_GEN2E_TAG_PMPORT_MASK 0x00 +#endif + +struct _mvTagsStack +{ + MV_U8 *pTagsArray; + MV_U8 top; +}; +struct _mvChannelTags +{ + struct _mvTagsStack HostTagsPool; + struct _mvTagsStack DeviceTagsPool[MV_SATA_GEN2E_TAG_POOLS_NUM]; + MV_U8 HostTags[MV_SATA_GEN2E_SW_QUEUE_SIZE]; + MV_U8 DeviceTags[MV_SATA_GEN2E_TAG_POOLS_NUM][MV_SATA_TAGS_PER_POOL]; +}; + +typedef enum mvHostInterfase +{ + MV_HOST_IF_INTEGRATED, /*as in 5182*/ + MV_HOST_IF_PEX, + MV_HOST_IF_PCI /*PCI/PCI-X*/ +}MV_HOST_IF; + +/* The following structures are part of the Core Driver API */ +typedef struct mvSataChannel +{ + /* Fields set by Intermediate Application Layer */ + MV_U8 channelNumber; + struct mvDmaRequestQueueEntry *requestQueue; + struct mvDmaResponseQueueEntry *responseQueue; + MV_U32 requestQueuePciHiAddress; + MV_U32 requestQueuePciLowAddress; + MV_U32 responseQueuePciHiAddress; + MV_U32 responseQueuePciLowAddress; + /* DRQ Data Block size in sectors, Core Driver sets a default value of 1 */ + /* sector in mvSataConfigureChannel*/ + MV_U8 DRQDataBlockSize; + /* Fields set by CORE driver */ + struct mvSataAdapter *mvSataAdapter; + MV_OS_SEMAPHORE semaphore; + MV_U32 eDmaRegsOffset; + MV_BOOLEAN EdmaActive; + MV_EDMA_MODE queuedDMA; + MV_U8 outstandingCommands; + MV_U8 portQueuedCommands[MV_SATA_PM_MAX_PORTS + 1]; + struct mvQueuedCommandEntry *commandsQueue; + struct mvQueuedCommandEntry *commandsQueueHead; + struct mvQueuedCommandEntry *commandsQueueTail; + MV_BOOLEAN queueCommandsEnabled; + MV_U8 noneUdmaOutstandingCommands; +#ifdef MV_SUPPORT_ATAPI + MV_U8 packetOutstandingCommands; + MV_BOOLEAN waitForBMDMA; +#endif + MV_U8 EdmaQueuedCommands; + MV_U8 commandsQueueSize; + struct _mvChannelTags Tags; + MV_U8 reqInPtr; + MV_U8 rspOutPtr; + MV_U8 EDMAQueuePtrMask; + MV_U32 EDMARequestInpMask; + /* Port Multiplier fiels*/ + MV_BOOLEAN PMSupported; + MV_SATA_DEVICE_TYPE deviceType; + MV_BOOLEAN FBSEnabled; + MV_BOOLEAN use128Entries; +#ifdef MV_SATA_C2C_COMM + + /* Channel 2 Channel*/ + MV_BOOLEAN C2CmodeEnabled; + MV_SATA_C2C_MODE C2CMode; + C2CCallBack_t C2CCallback; +#endif + MV_U8 recoveredErrorsCounter; + /* NCQ error handling*/ + MV_ERROR_HANDLING_INFO ErrorHandlingInfo; +} MV_SATA_CHANNEL; + + + +typedef struct mvSataAdapter +{ + /* Fields set by Intermediate Application Layer */ + MV_U32 adapterId; + MV_VOID_PTR IALData; + MV_U8 pciConfigRevisionId; + MV_U16 pciConfigDeviceId; + MV_BUS_ADDR_T adapterIoBaseAddress; + MV_U32 intCoalThre[MV_SATA_UNITS_NUM]; + MV_U32 intTimeThre[MV_SATA_UNITS_NUM]; + MV_BOOLEAN (*mvSataEventNotify)(struct mvSataAdapter *, + MV_EVENT_TYPE, + MV_U32, MV_U32); + MV_SATA_CHANNEL *sataChannel[MV_SATA_CHANNELS_NUM]; + MV_U32 pciCommand; + MV_U32 pciSerrMask; + MV_U32 pciInterruptMask; + + + /* Fields set by CORE driver */ + MV_SATA_GEN sataAdapterGeneration; + MV_BOOLEAN staggaredSpinup[MV_SATA_CHANNELS_NUM]; /* For 60x1 only */ + MV_BOOLEAN limitInterfaceSpeed[MV_SATA_CHANNELS_NUM]; /* For 60x1 only */ + MV_SATA_IF_SPEED ifSpeed[MV_SATA_CHANNELS_NUM]; /* For 60x1 only */ + MV_SATA_IF_POWER_STATE ifPowerState[MV_SATA_CHANNELS_NUM]; + MV_U8 numberOfChannels;/* 4 channels for 504x, 8 for 508x*/ + MV_U8 numberOfUnits;/* 1 for 504x, 2 for 508x*/ + MV_U8 portsPerUnit; + MV_OS_SEMAPHORE semaphore; + MV_U32 mainMask; + MV_U32 mainMaskOffset; + MV_U32 mainCauseOffset; + MV_HOST_IF hostInterface; + MV_BOOLEAN interruptsAreMasked; + MV_SATA_INTERRUPT_SCHEME interruptsScheme; + MV_OS_SEMAPHORE interruptsMaskSem; + MV_BOOLEAN chipIs50XXB0; + MV_BOOLEAN chipIs50XXB2; + MV_BOOLEAN chipIs60X1B2; + MV_BOOLEAN chipIs60X1C0; + MV_BOOLEAN chipIs62X1Z0; + MV_U8 signalAmps[MV_SATA_CHANNELS_NUM]; + MV_U8 pre[MV_SATA_CHANNELS_NUM]; + struct mvQueuedCommandEntry adapterCommands[_MV_SATA_COMMANDS_PER_ADAPTER]; +#ifdef MV_SATA_IO_GRANULARITY + MV_BOOLEAN iogEnabled; + MV_U8 iogFreeIdsStack[MV_IOG_QUEUE_SIZE]; + MV_U8 iogFreeIdsNum; + MV_OS_SEMAPHORE iogSemaphore; +#endif +} MV_SATA_ADAPTER; + +/* this structure used by the IAL defines the PRD entries used by the EDMA HW */ +typedef struct mvSataEdmaPRDEntry +{ + volatile MV_U32 lowBaseAddr; + volatile MV_U16 byteCount; + volatile MV_U16 flags; + volatile MV_U32 highBaseAddr; + volatile MV_U32 reserved; +}MV_SATA_EDMA_PRD_ENTRY; + +/* API Functions */ + +/* CORE driver Adapter Management */ +MV_BOOLEAN mvSataInitAdapter(MV_SATA_ADAPTER *pAdapter); + +MV_BOOLEAN mvSataShutdownAdapter(MV_SATA_ADAPTER *pAdapter); + +MV_U32 mvSataReadReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset); + +MV_VOID mvSataWriteReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset, + MV_U32 regValue); + +/* CORE driver SATA Channel Management */ +MV_BOOLEAN mvSataConfigureChannel(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + +MV_BOOLEAN mvSataRemoveChannel(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +MV_BOOLEAN mvSataIsStorageDeviceConnected(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, MV_U32 *SStatus); + +MV_BOOLEAN mvSataIfD2HReceived(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 port); + +MV_BOOLEAN mvSataChannelHardReset(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + +MV_BOOLEAN mvSataSetFBSMode(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_BOOLEAN enableFBS, MV_BOOLEAN useQueueLen128); + +MV_BOOLEAN mvSataConfigEdmaMode(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_EDMA_MODE eDmaMode, MV_U8 maxQueueDepth); + +MV_BOOLEAN mvSataEnableChannelDma(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + +MV_BOOLEAN mvSataDisableChannelDma(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + +MV_BOOLEAN mvSataFlushDmaQueue(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_FLUSH_TYPE flushType); + +MV_U8 mvSataNumOfDmaCommands(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +MV_U8 mvSataGetNumOfPortQueuedCommands(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_U8 *pCommandsPerChannel); + +MV_BOOLEAN mvSataSetIntCoalParams (MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit, + MV_U32 intCoalThre, MV_U32 intTimeThre); + +MV_BOOLEAN mvSataSetChannelPhyParams(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 signalAmps, MV_U8 pre); + +MV_BOOLEAN mvSataChannelPhyShutdown(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + +MV_BOOLEAN mvSataChannelPhyPowerOn(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + +MV_BOOLEAN mvSataChannelFarLoopbackDiagnostic(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); +/* Queue ATA command */ +MV_QUEUE_COMMAND_RESULT mvSataQueueCommand(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_QUEUE_COMMAND_INFO *pCommandParams); + + +/* Interrupt Service Routine */ +MV_BOOLEAN mvSataInterruptServiceRoutine(MV_SATA_ADAPTER *pAdapter); + +MV_BOOLEAN mvSataMaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter); + +MV_BOOLEAN mvSataUnmaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter); + +MV_BOOLEAN mvSataCheckPendingInterrupt(MV_SATA_ADAPTER *pAdapter); + +MV_BOOLEAN mvSataSetInterruptsScheme(MV_SATA_ADAPTER *pAdapter, + MV_SATA_INTERRUPT_SCHEME interruptScheme); + +/* + * Staggered spin-ip support and SATA interface speed control + * (relevant for 60x1 adapters) + */ +MV_BOOLEAN mvSataEnableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter); + +MV_BOOLEAN mvSataEnableStaggeredSpinUp (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + +MV_BOOLEAN mvSataDisableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter); + +MV_BOOLEAN mvSataDisableStaggeredSpinUp (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + + +MV_BOOLEAN mvSataSetInterfaceSpeed (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_SATA_IF_SPEED ifSpeed); + +MV_SATA_IF_SPEED mvSataGetInterfaceSpeed (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + +MV_BOOLEAN mvSataSetInterfacePowerState (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_SATA_IF_POWER_STATE ifPowerState); + +MV_BOOLEAN mvSataGetInterfacePowerState (MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_SATA_IF_POWER_STATE *ifPowerState); + +/* Command Completion and Event Notification (user implemented) */ +MV_BOOLEAN mvSataEventNotify(MV_SATA_ADAPTER *, MV_EVENT_TYPE , + MV_U32, MV_U32); +#ifdef MV_SATA_C2C_COMM + +/* Channel 2 Channel communication */ +MV_BOOLEAN mvSataC2CInit (MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_SATA_C2C_MODE mvSataC2CMode, + C2CCallBack_t mvSataC2CCallBack); + +MV_BOOLEAN mvSataC2CStop (MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + + +MV_BOOLEAN mvSataC2CSendRegisterDeviceToHostFIS( + MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 pmPort, + MV_BOOLEAN bInterrupt, + MV_U8 message[MV_C2C_MESSAGE_SIZE]); + +MV_BOOLEAN mvSataC2CActivateBmDma(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 pmPort, + MV_U32 prdTableHi, + MV_U32 prdTableLow, + MV_UDMA_TYPE dmaType); + +MV_BOOLEAN mvSataC2CResetBmDma(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + +#endif + +#ifdef MV_SATA_IO_GRANULARITY + +MV_BOOLEAN mvSataEnableIoGranularity(MV_SATA_ADAPTER *pAdapter, + MV_BOOLEAN enable); + +#endif +MV_BOOLEAN mvSata60X1B2CheckDevError(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); +#ifdef __cplusplus + +/*}*/ +#endif /* __cplusplus */ + +#endif /* __INCmvSatah */ diff --git a/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSataSoc.c b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSataSoc.c new file mode 100644 index 0000000..caa972a --- /dev/null +++ b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSataSoc.c @@ -0,0 +1,114 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvSataSoc.h" + +/* Calculate the base address of the registers for a SATA channel */ +static MV_U32 edmaRegOffst[8] = {0x22000, 0x24000, 0x26000, 0x28000, +0x32000, 0x34000, 0x36000, 0x38000}; +#define getEdmaRegOffset(x) edmaRegOffst[(x)] + +MV_BOOL mvSataPhyShutdown(MV_U8 port) +{ + MV_U32 regVal; + MV_U32 adapterIoBaseAddress = SATA_REG_BASE - 0x20000; + + regVal = MV_REG_READ (adapterIoBaseAddress + + getEdmaRegOffset (port) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET); + /* Fix for 88SX60x1 FEr SATA#8*/ + /* according to the spec, bits [31:12] must be set to 0x009B1 */ + regVal &= 0x00000FFF; + /* regVal |= MV_BIT12;*/ + regVal |= 0x009B1000; + + regVal |= BIT9; + MV_REG_WRITE (adapterIoBaseAddress + + getEdmaRegOffset (port) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET, + regVal); + return MV_TRUE; +} +MV_BOOL mvSataPhyPowerOn(MV_U8 port) +{ + MV_U32 adapterIoBaseAddress = SATA_REG_BASE - 0x20000; + + MV_U32 regVal = MV_REG_READ (adapterIoBaseAddress + + getEdmaRegOffset (port) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET); + /* Fix for 88SX60x1 FEr SATA#8*/ + /* according to the spec, bits [31:12] must be set to 0x009B1 */ + regVal &= 0x00000FFF; + /* regVal |= MV_BIT12;*/ + regVal |= 0x009B1000; + + + regVal &= ~(BIT9); + MV_REG_WRITE (adapterIoBaseAddress + + getEdmaRegOffset (port) + + MV_SATA_II_SATA_CONFIG_REG_OFFSET, + regVal); + return MV_TRUE; +} + diff --git a/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSataSoc.h b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSataSoc.h new file mode 100644 index 0000000..3768ba3 --- /dev/null +++ b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvSataSoc.h @@ -0,0 +1,86 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvSataSoch +#define __INCmvSataSoch +#ifdef __cplusplus +extern "C" /*{*/ +#endif /* __cplusplus */ + +#include "mvCommon.h" +#include "mvRegs.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + + +MV_BOOL mvSataPhyShutdown(MV_U8 port); +MV_BOOL mvSataPhyPowerOn(MV_U8 port); + + +#ifdef __cplusplus + +/*}*/ +#endif /* __cplusplus */ + +#endif /* __INCmvSatah */ + diff --git a/board/mv_feroceon/mv_hal/sata/CoreDriver/mvStorageDev.c b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvStorageDev.c new file mode 100644 index 0000000..1ce4b5a --- /dev/null +++ b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvStorageDev.c @@ -0,0 +1,2183 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/******************************************************************************* +* mvStorageDev.c - C File for implementation of the core driver. +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* mvOs.h +* mvSata.h. +* mvStorageDev.h +* mvRegs.h +* +*******************************************************************************/ +#include "mvOsS.h" +#include "mvSata.h" +#include "mvStorageDev.h" +#include "mvRegs.h" + +/* Defines */ + +/* functions for internal driver use */ +MV_BOOLEAN waitWhileStorageDevIsBusy(MV_SATA_ADAPTER* pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 eDmaRegsOffset, MV_U32 loops, + MV_U32 delayParam); +MV_BOOLEAN waitForDRQToClear(MV_SATA_ADAPTER* pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 eDmaRegsOffset, MV_U32 loops, + MV_U32 delayParam); + +void enableStorageDevInterrupt (MV_SATA_CHANNEL *pSataChannel); +void disableStorageDevInterrupt(MV_SATA_CHANNEL *pSataChannel); +static MV_BOOLEAN isStorageDevReadyForPIO(MV_SATA_CHANNEL *pSataChannel); +void dumpAtaDeviceRegisters(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, MV_BOOLEAN isEXT, + MV_STORAGE_DEVICE_REGISTERS *pRegisters); +MV_BOOLEAN _doSoftReset(MV_SATA_CHANNEL *pSataChannel); +extern void _setActivePMPort(MV_SATA_CHANNEL *pSataChannel, MV_U8 PMPort); +extern void disableSaDevInterrupts(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); + +MV_BOOLEAN _PMAccessReg(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_U8 PMPort, MV_U8 PMReg, MV_U32 *pValue, + MV_STORAGE_DEVICE_REGISTERS *registerStruct, + MV_BOOLEAN isRead); + +MV_BOOLEAN executeNonUDMACommand(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_NON_UDMA_PROTOCOL protocolType, + MV_BOOLEAN isEXT, + MV_U16_PTR bufPtr, MV_U32 count, + MV_U16 features, + MV_U16 sectorCount, + MV_U16 lbaLow, MV_U16 lbaMid, + MV_U16 lbaHigh, MV_U8 device, + MV_U8 command); + +MV_BOOLEAN waitWhileStorageDevIsBusy_88SX60X1(MV_SATA_ADAPTER* pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 eDmaRegsOffset, MV_U8 channelIndex, + MV_U32 loops, + MV_U32 delayParam); + +MV_BOOLEAN waitForDRQ(MV_SATA_ADAPTER* pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 eDmaRegsOffset, MV_U32 loops, + MV_U32 delayParam); + +void _startSoftResetDevice(MV_SATA_CHANNEL *pSataChannel); +MV_BOOLEAN _isDeviceBsyBitOff(MV_SATA_CHANNEL *pSataChannel); +/******************************************************************************* +* waitWhileStorageDevIsBusy - Wait for the storage device to be released from +* busy state. +* +* DESCRIPTION: +* The busy bit is set to one to indicate that the storage device is busy. The +* busy bit shall be set to one by the device only when one of the following +* events occurs: +* +* 1) after either the negation of RESET- or the setting of the SRST bit to one +* in the Device Control register. +* 2) after writing the Command register if the DRQ bit is not set to one. +* 3) between blocks of a data transfer during PIO data-in commands before the +* DRQ bit is cleared to zero. +* 4) after the transfer of a data block during PIO data-out commands before +* the DRQ bit is cleared to zero. +* 5) during the data transfer of DMA commands either the BSY bit, the DRQ bit, +* or both shall be set to one. +* 6) after the command packet is received during the execution of a PACKET +* command. +* +* INPUT: +* ioBaseAddr - The PCI I/O window base address of the adapter. +* eDmaRegsOffset - The EDMA register's offset of the relevant SATA channel. +* loops - max number of times to pool the status register. +* delay - number of u seconds to wait each loop. +* +* RETURN: +* MV_TRUE if the device is released from busy state, MV_FALSE otherwise. +* COMMENTS: +* None. +* +*******************************************************************************/ +MV_BOOLEAN waitWhileStorageDevIsBusy(MV_SATA_ADAPTER* pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 eDmaRegsOffset, MV_U32 loops, + MV_U32 delayParam) +{ + MV_U8 ATAstatus = 0; + MV_U32 i; + + for (i = 0;i < loops; i++) + { + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if ((ATAstatus & MV_ATA_BUSY_STATUS) == 0) + { + + if ((ATAstatus & MV_ATA_ERROR_STATUS) == 0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, "waitWhileStorageDevIsBusy: %d loops *" + "%d usecs\n", i, delayParam); + return MV_TRUE; + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "waitWhileStorageDevIsBusy: Device ERROR" + " Status: 0x%02x\n", ATAstatus); + return MV_FALSE; + } + } + mvMicroSecondsDelay(pAdapter, delayParam); + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, "waitWhileStorageDevIsBusy: Time out - Device ERROR" + " Status: 0x%02x. loops %d, delay %d\n", ATAstatus, loops, delayParam); + + return MV_FALSE; +} + + +MV_BOOLEAN waitWhileStorageDevIsBusy_88SX60X1(MV_SATA_ADAPTER* pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 eDmaRegsOffset, MV_U8 channelIndex, + MV_U32 loops, + MV_U32 delayParam) +{ + MV_U8 ATAstatus = 0; + MV_U32 i,intReg; + MV_U8 sataUnit = channelIndex >> 2, portNum = (channelIndex & 0x3); + + + for (i = 0;i < loops; i++) + { + intReg = MV_REG_READ_DWORD (ioBaseAddr, MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET); + + if (intReg & (1 << (8 + portNum))) + { + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + MV_REG_WRITE_DWORD (ioBaseAddr, MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET, + ~(1 << (8 + portNum))); + if ((ATAstatus & MV_ATA_ERROR_STATUS) == 0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID,MV_DEBUG, "waitWhileStorageDevIsBusy: %d loops *" + "%d usecs\n", i, delayParam); + return MV_TRUE; + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID,MV_DEBUG_ERROR, "waitWhileStorageDevIsBusy: Device ERROR" + " Status: 0x%02x\n", ATAstatus); + return MV_FALSE; + } + } + mvMicroSecondsDelay(pAdapter, delayParam); + } + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "waitWhileStorageDevIsBusy: Time out - Device ERROR" + " Status: 0x%02x. loops %d, delay %d\n", ATAstatus, loops, delayParam); + return MV_FALSE; +} + +MV_BOOLEAN waitForDRQ(MV_SATA_ADAPTER* pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 eDmaRegsOffset, MV_U32 loops, + MV_U32 delayParam) +{ + MV_U8 ATAstatus = 0; + MV_U32 i; + + for (i = 0;i < loops; i++) + { + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if ((ATAstatus & MV_ATA_BUSY_STATUS) == 0) + { + if (ATAstatus & MV_ATA_DATA_REQUEST_STATUS) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, "waitWhileStorageDevIsBusy: %d loops *" + "%d usecs\n", i, delayParam); + return MV_TRUE; + } + } + mvMicroSecondsDelay(pAdapter, delayParam); + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, "waitWhileStorageDevIsBusy: Time out - Device ERROR" + " Status: 0x%02x. loops %d, delay %d\n", ATAstatus, loops, delayParam); + + return MV_FALSE; +} +/******************************************************************************* +* enableStorageDevInterrupt - Enable the storage device to be able to issue +* interrupt. +* +* DESCRIPTION: +* Enable the connected storage device to the given channel to assert INTRQ by +* clearing nIEN bit in the Device Control register. +* +* INPUT: +* pSataChannel - Pointer to the Sata channel data structure. +* +* RETURN: +* None. +* +* COMMENTS: +* this function also clears the SRST bit in the Device Control register. +* +*******************************************************************************/ +void enableStorageDevInterrupt(MV_SATA_CHANNEL *pSataChannel) +{ + + MV_REG_WRITE_BYTE(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_CONTROL_REG_OFFSET,0); + MV_REG_READ_BYTE(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_CONTROL_REG_OFFSET); +} + +/******************************************************************************* +* disableStorageDevInterrupt - Disable the storage device to be able to issue +* interrupt. +* +* DESCRIPTION: +* This function disable the connected storage device to the given channel to +* assert INTRQ by setting nIEN bit in the Device Control register. +* +* INPUT: +* pSataChannel - Pointer to the Sata channel data structure. +* +* RETURN: +* None. +* +* COMMENTS: +* this function also clears the SRST bit +* +*******************************************************************************/ +void disableStorageDevInterrupt(MV_SATA_CHANNEL *pSataChannel) +{ + + + MV_REG_WRITE_BYTE(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_CONTROL_REG_OFFSET, MV_BIT1); + MV_REG_READ_BYTE(pSataChannel->mvSataAdapter->adapterIoBaseAddress, + pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); +} + +/******************************************************************************* +* isStorageDevReadyForPIO - Check that the storage device connected to the given +* channel and the channel itself are ready to perform +* PIO commands. +* +* DESCRIPTION: +* Check if the device connected to the given channel and the channel itself +* are ready for PIO commands. +* +* INPUT: +* pSataChannel - Pointer to the SATA channel data structure. +* +* RETURN: +* MV_TRUE if the channel and the connected device ready to do PIO, +* MV_FALSE otherwise. +* +* COMMENTS: +* If the adapter's eEnEDMA bit in the EDMA Command Register is set, PIO +* commands cannot be issued. The eEnEDMA bit cannot be reset by the CPU. +* Only the EDMA resets it, when bit eDsEDMA is set or when an error +* condition occurs. +* +*******************************************************************************/ +static MV_BOOLEAN isStorageDevReadyForPIO(MV_SATA_CHANNEL *pSataChannel) +{ + MV_BUS_ADDR_T ioBaseAddr =pSataChannel->mvSataAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + MV_U8 ATAcontrolRegValue; + + /* If the adapter's eEnEDMA bit in the EDMA Command Register is set */ + /* PIO commands cannot be issued. */ + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: PIO command failed:" + "EDMA is active\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + return MV_FALSE; + } + /* Check if BUSY bit is '0' */ + + /* Reading the Control register actually gives us the Alternate Status */ + /* register content (ATA protocol). If the busy bit is set in the */ + /* Alternate Status register, we wait for 50 mili-sec and try again, if */ + /* the busy bit is still set, we return false indicating that the */ + /* device is not ready for PIO commands. */ + ATAcontrolRegValue = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_CONTROL_REG_OFFSET); + if ((ATAcontrolRegValue & MV_ATA_BUSY_STATUS)!= 0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: control regiser is " + "0x%02x\n",pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber,ATAcontrolRegValue); + return MV_FALSE; + } + if ( (pSataChannel->deviceType != MV_SATA_DEVICE_TYPE_ATAPI_DEVICE) && + ((ATAcontrolRegValue & MV_ATA_READY_STATUS) != MV_ATA_READY_STATUS)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: storage drive is not" + " ready, ATA STATUS=0x%02x\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAcontrolRegValue); + return MV_FALSE; + } + /* The device is ready for PIO commands */ + return MV_TRUE; +} + +MV_BOOLEAN mvStorageDevATAIdleImmediate(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_U32 eDmaRegsOffset; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvStorageDevATAIdentif" + "yDevice failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { /* If the pointer do not exists, retrun false */ + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: channel data " + "structure is not allocated\n", pAdapter->adapterId, + channelIndex); + return MV_FALSE; + } + + ioBaseAddr =pSataChannel->mvSataAdapter->adapterIoBaseAddress; + + mvOsSemTake(&pSataChannel->semaphore); + eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvStorageDevATAIdle" + "Immediate command failed: EDMA is active\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "Issue IDLE IMMEDIATE COMMAND\n"); + disableStorageDevInterrupt(pSataChannel); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + MV_ATA_DEVICE_COMMAND_REG_OFFSET, + MV_ATA_COMMAND_IDLE_IMMEDIATE); + + if (waitWhileStorageDevIsBusy(pAdapter, + ioBaseAddr, eDmaRegsOffset, 10000, 100) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: Idle Immediate failed\n", + pSataChannel->mvSataAdapter->adapterId, pSataChannel->channelNumber); + + enableStorageDevInterrupt(pSataChannel); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + + enableStorageDevInterrupt(pSataChannel); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_TRUE; +} + +/******************************************************************************* +* mvStorageDevATAIdentifyDevice - Perform an ATA IDENTIFY device command. +* +* DESCRIPTION: +* This function issues an IDENTIFY command to the connected device, and +* stores all the information in the identifyDevice buffer of the channel. +* +* INPUT: +* pAdapter - Pointer to the device data structure. +* channelIndex - The index of the channel where the storage device +* connected to. +* PMPort - index of the required destination port multipliers +* device Port (0 if no PM available). +* identifyDeviceResult - a buffer that is allocated by IAL that will hold +* the IDENTIFY DEIVICE command result. +* +* RETURN: +* MV_TRUE on success, MV_FALSE on failure. +* +* COMMENTS: +* None. +* +*******************************************************************************/ +MV_BOOLEAN mvStorageDevATAIdentifyDevice(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_U16_PTR identifyDeviceResult + ) +{ + MV_BOOLEAN result; + /* Get the pointer to the relevant channel. */ + MV_SATA_CHANNEL *pSataChannel; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvStorageDevATAIdentif" + "yDevice failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { /* If the pointer do not exists, retrun false */ + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: channel data " + "structure is not allocated\n", pAdapter->adapterId, + channelIndex); + return MV_FALSE; + } + if (identifyDeviceResult == NULL) + { /* If the pointer do not exists, retrun false */ + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: identify data buffer" + " is not allocated\n", pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + result = mvStorageDevATAExecuteNonUDMACommand(pAdapter, channelIndex, + PMPort, + MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, + MV_FALSE, + /* pBuffer */ + identifyDeviceResult, + 256, /* count */ + 0, /* features */ + 0, /* sectorCount */ + 0, /* lbaLow */ + 0, /* lbaMid */ + 0, /* lbaHigh */ + 0, /* device */ + /* The command */ + MV_ATA_COMMAND_IDENTIFY); + if (result == MV_FALSE) + { + return MV_FALSE; + } + if (identifyDeviceResult[IDEN_ATA_VERSION] & (MV_BIT7 | MV_BIT6 | MV_BIT5)) + { + /* if ATA 5/6/7 then check CRC of Identify command result */ + MV_U8 crc = 0; + MV_U16 count; + MV_U8_PTR pointer = (MV_U8_PTR)identifyDeviceResult; + /* If no 0xa5 signature valid, then don't check CRC */ + if (pointer[510] != 0xa5) + { + return MV_TRUE; + } + for (count = 0 ; count < ATA_SECTOR_SIZE ; count ++) + { + crc += pointer[count]; + } + if (crc != 0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: IDENTIFY DEVICE " + "ATA Command failed due to wrong CRC checksum (%02x)\n", + pAdapter->adapterId, channelIndex,crc); + return MV_FALSE; + } + + } + return MV_TRUE; +} + +/******************************************************************************* +* mvStorageDevATASoftResetDevice - Issue SATA SOFTWARE reset to device. +* +* DESCRIPTION: +* Perform SOFTWARE RESET to the connected storage device by setting the +* SRST bit of the ATA device COMMAND +* +* INPUT: +* pAdapter - Pointer to the device data structure. +* channelIndex - Index of the required channel. +* PMPort - index of the required destination port multipliers +* device port (0 if no PM available). +* registerStruct - Pointer to ATA registers data structure +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_BOOLEAN mvStorageDevATASoftResetDevice(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_STORAGE_DEVICE_REGISTERS *registerStruct + ) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_U32 eDmaRegsOffset; + MV_BOOLEAN result; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvStorageDevATASoftRes" + "etDevice Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + ioBaseAddr = pAdapter->adapterIoBaseAddress; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: channel data structu" + "re is not allocated\n", pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + + mvOsSemTake(&pSataChannel->semaphore); + eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvStorageDevATASoft" + "ResetDevice command failed: EDMA is active\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + _setActivePMPort(pSataChannel, PMPort); + result = _doSoftReset(pSataChannel); + if (registerStruct) + { + dumpAtaDeviceRegisters(pAdapter, channelIndex, MV_FALSE, + registerStruct); + } + mvOsSemRelease( &pSataChannel->semaphore); + return result; +} + + + +void _startSoftResetDevice(MV_SATA_CHANNEL *pSataChannel) +{ + MV_BUS_ADDR_T ioBaseAddr = + pSataChannel->mvSataAdapter->adapterIoBaseAddress; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_NON_UDMA_COMMAND | MV_DEBUG, "Issue SRST COMMAND\n"); + +/* Write to the Device Control register, bits 1,2: */ +/* - bit 1 (nIEN): is the enable bit for the device assertion of INTRQ */ +/* to the host. When the nIEN bit is set to one, or the device is not */ +/* selected, the device shall release the INTRQ signal. */ +/* - bit 2 (SRST): is the host software reset bit. */ + MV_REG_WRITE_BYTE(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_CONTROL_REG_OFFSET, MV_BIT2|MV_BIT1); + MV_REG_READ_BYTE(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_CONTROL_REG_OFFSET); + mvMicroSecondsDelay(pSataChannel->mvSataAdapter, 10); + /* enableStorageDevInterrupt will clear the SRST bit*/ + enableStorageDevInterrupt(pSataChannel); +} + +MV_BOOLEAN _isDeviceBsyBitOff(MV_SATA_CHANNEL *pSataChannel) +{ + MV_BUS_ADDR_T ioBaseAddr = + pSataChannel->mvSataAdapter->adapterIoBaseAddress; + MV_U8 ATAstatus; + MV_U32 eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if ((ATAstatus & MV_ATA_BUSY_STATUS) == 0) + { + return MV_TRUE; + } + else + { +#ifdef MV_LOGGER + if (pSataChannel->mvSataAdapter->sataAdapterGeneration >= + MV_SATA_GEN_II) + { + MV_U32 ifStatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_SATA_II_IF_STATUS_REG_OFFSET); + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + "[%d %d] SATA interface status register = 0x%X\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, + ifStatus); + } +#endif + return MV_FALSE; + } +} + + +/******************************************************************************* +* mvStorageDevATAStartSoftResetDevice - +* begins device software reset +* +* DESCRIPTION: +* +* Submits SRST for channel connected device and exit. The IAL must call the +* mvStorageIsDeviceBsyBitOff later on to check whether the device is +* ready +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - channel number +* PMPort - port multiplier port +* +* OUTPUT: +* None +* RETURN: +* MV_TRUE on success, +* MV_FALSE otherwise. +* COMMENTS: +* +*******************************************************************************/ +MV_BOOLEAN mvStorageDevATAStartSoftResetDevice(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort + ) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvStorageDevATASoftRes" + "etDevice Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + ioBaseAddr = pAdapter->adapterIoBaseAddress; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: channel data structu" + "re is not allocated\n", pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + + mvOsSemTake(&pSataChannel->semaphore); + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvStorageDevATASoft" + "ResetDevice command failed: EDMA is active\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + _setActivePMPort(pSataChannel, PMPort); + _startSoftResetDevice(pSataChannel); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_TRUE; +} + +/******************************************************************************* +* mvStorageIsDeviceBsyBitOff - +* check if device is BUSY bit cleared after SRST +* +* DESCRIPTION: +* +* Checks the if BSY bit in ATA status is on/off +* +* INPUT: +* pAdapter - pointer to the adapter data structure. +* channelIndex - channel number +* registerStruct - If non-zero then this function dumps ATA registers +* to this data structure before exit. +* +* OUTPUT: +* None +* RETURN: +* MV_TRUE if BSY bit is off +* MV_FALSE if BSY bit is on (or on failure) +* COMMENTS: +* +*******************************************************************************/ +MV_BOOLEAN mvStorageIsDeviceBsyBitOff(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_STORAGE_DEVICE_REGISTERS *registerStruct + ) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BUS_ADDR_T ioBaseAddr; + MV_BOOLEAN result; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvStorageDevATASoftRes" + "etDevice Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + ioBaseAddr = pAdapter->adapterIoBaseAddress; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: channel data structu" + "re is not allocated\n", pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + mvOsSemTake(&pSataChannel->semaphore); + result = _isDeviceBsyBitOff(pSataChannel); + if (registerStruct) + { + dumpAtaDeviceRegisters(pAdapter, channelIndex, MV_FALSE, + registerStruct); + } + mvOsSemRelease( &pSataChannel->semaphore); + return result; +} + + +/******************************************************************************* +* mvStorageDevATASetFeatures - Perform ATA SET FEATURES command. +* +* DESCRIPTION: +* Perform ATA SET FEATURES command to the ATA device connected to the +* given channel. This command is used by the host to establish parameters +* that affect the execution of certain device features (Table 44 in the +* ATA protocol document defines these features). +* +* INPUT: +* pAdapter - Pointer to the device data structure. +* channelIndex - Index of the required channel +* PMPort - index of the required destination port multipliers +* device Port (0 if no PM available). +* subCommand - Sub command for the SET FEATURES ATA command +* subCommandSpecific1 - First parameter to the sub command. +* subCommandSpecific2 - Second parameter to the sub command. +* subCommandSpecific3 - Third parameter to the sub command. +* subCommandSpecific4 - Fourth parameter to the sub command. +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_BOOLEAN mvStorageDevATASetFeatures(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_U8 subCommand, + MV_U8 subCommandSpecific1, + MV_U8 subCommandSpecific2, + MV_U8 subCommandSpecific3, + MV_U8 subCommandSpecific4) +{ + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, + "ATA Set Features: %x , %x , %x , %x , %x\n", subCommand, + subCommandSpecific1, subCommandSpecific2, subCommandSpecific3, + subCommandSpecific4); + return mvStorageDevATAExecuteNonUDMACommand(pAdapter, channelIndex, + PMPort, + MV_NON_UDMA_PROTOCOL_NON_DATA, + MV_FALSE, + NULL, /* pBuffer*/ + 0, /* count */ + subCommand, /*features*/ + /* sectorCount */ + subCommandSpecific1, + subCommandSpecific2, /* lbaLow */ + subCommandSpecific3, /* lbaMid */ + /* lbaHigh */ + subCommandSpecific4, + 0, /* device */ + /* command */ + MV_ATA_COMMAND_SET_FEATURES); +} + + +/******************************************************************************* +* mvStorageDevATAExecuteNonUdmaCommand - perform ATA non udma command. +* +* DESCRIPTION: +* perform ATA non UDMA command to the ATA device connected to the given +* channel +* +* INPUT: +* pAdapter - pointer to the device data structure. +* channelIndex - index of the required channel +* PMPort - index of the required destination port multipliers +* device Port (0 if no PM available). +* protocolType - protocol type of the command +* isEXT - true when the given command is the EXTENDED +* bufPtr - pointer to the buffer to write/read to/from +* count - number of words to transfer +* features - the value to be written to the FEATURES register +* sectorCount - the value to be written to the SECTOR COUNT register +* lbaLow - the value to be written to the LBA LOW register +* lbaMid - the value to be written to the LBA MID register +* lbaHigh - the value to be written to the LBA HIGH register +* device - the value to be written to the DEVICE register +* command - the value to be written to the COMMAND register +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* when the command is EXTENDED, then the high 8 bits of the 16 bits values +* will be written first, so they should hold the previous value as defined in +* the ATA 6 standard +* +*******************************************************************************/ +MV_BOOLEAN mvStorageDevATAExecuteNonUDMACommand(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_NON_UDMA_PROTOCOL protocolType, + MV_BOOLEAN isEXT, + MV_U16_PTR bufPtr, MV_U32 count, + MV_U16 features, + MV_U16 sectorCount, + MV_U16 lbaLow, MV_U16 lbaMid, + MV_U16 lbaHigh, MV_U8 device, + MV_U8 command) +{ + MV_BOOLEAN result; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvStorageDevATAExecute" + "NonUDMACommand Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + if (pAdapter->sataChannel[channelIndex] == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvStorageDevATAExecu" + "teNonUDMACommand Failed, channel data structure not allocated" + "\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + mvOsSemTake(&pAdapter->sataChannel[channelIndex]->semaphore); + result = executeNonUDMACommand(pAdapter, channelIndex, PMPort, protocolType, + isEXT, bufPtr, count, features, sectorCount, + lbaLow, lbaMid, lbaHigh, device, command); + mvOsSemRelease(&pAdapter->sataChannel[channelIndex]->semaphore); + return result; +} +#if 0 +MV_BOOLEAN executePacketCommand(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_NON_UDMA_PROTOCOL protocolType, + MV_U8 PMPort, + MV_U16_PTR cdb, + MV_U8 cdb_len, + MV_U16_PTR dataBufPtr + ) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + MV_BUS_ADDR_T ioBaseAddr = pAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset; + MV_U32 i; + MV_U32 count; + MV_U8 ATAstatus; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, " %d %d send PACKET " + " command: protocol(%d) cdb %p cdb len %p buffer %p \n", pAdapter->adapterId, + channelIndex, protocolType, cdb, cdb_len, dataBufPtr); + + eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + if ((PMPort) && ((pSataChannel->PMSupported == MV_FALSE) || + (pSataChannel->deviceType != MV_SATA_DEVICE_TYPE_PM))) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: executePacketCommand" + " failed PM not supported for this channel\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + { + if (isStorageDevReadyForPIO(pSataChannel) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d : Error in Issue NON UDMA command:" + " isStorageDevReadyForPIO failed\n", + pAdapter->adapterId, channelIndex); + + return MV_FALSE; + } + } + _setActivePMPort(pSataChannel, PMPort); + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: PIO command failed:" + "EDMA is active\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + return MV_FALSE; + } + + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + disableStorageDevInterrupt(pSataChannel); + } + + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_FEATURES_REG_OFFSET, 0); + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET, 0); + + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_LOW_REG_OFFSET, 0); + + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_MID_REG_OFFSET, 0); + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET, 0x20); + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_HEAD_REG_OFFSET, 0); + MV_CPU_WRITE_BUFFER_FLUSH(); + + /* 88SX60X1 FEr SATA #16 */ + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + enableStorageDevInterrupt(pSataChannel); + } + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_COMMAND_REG_OFFSET,MV_ATA_COMMAND_PACKET ); + + /* Wait for PIO Setup or completion*/ + if (waitWhileStorageDevIsBusy(pAdapter, ioBaseAddr, eDmaRegsOffset, 3100, 10000) == + MV_FALSE) + { + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + if (protocolType == MV_NON_UDMA_PROTOCOL_PACKET_PIO_NON_DATA) + { + enableStorageDevInterrupt(pSataChannel); + pSataChannel->recoveredErrorsCounter = 0; + return MV_TRUE; + } + + + /* Check the status register on DATA request commands */ + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + if (!(ATAstatus & MV_ATA_DATA_REQUEST_STATUS)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: DRQ bit in ATA STATUS" + " register is not set\n", pAdapter->adapterId, channelIndex); + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + } + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + + if (waitForDRQ(pAdapter, ioBaseAddr, eDmaRegsOffset, 500, 10000) + == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: DRQ bit in ATA STATUS" + " register is not set\n", pAdapter->adapterId, channelIndex); + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + } + for (i = 0; i < cdb_len; i++) + { + MV_REG_WRITE_WORD(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET, cdb[i]); + MV_CPU_WRITE_BUFFER_FLUSH(); + } + + if (waitForDRQ(pAdapter, ioBaseAddr, eDmaRegsOffset, 500, 10000) + == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: DRQ bit in ATA STATUS" + " register is not set\n", pAdapter->adapterId, channelIndex); + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " Status: %x\n", + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + MV_ATA_DEVICE_STATUS_REG_OFFSET)); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " Sector Count: %x\n", + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET)); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " LBA Mid: %x\n", + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + MV_ATA_DEVICE_LBA_MID_REG_OFFSET)); + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " LBA High: %x\n", + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET)); + + count = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + MV_ATA_DEVICE_LBA_MID_REG_OFFSET) + + (MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET) << 8); + count >>= 1; + for ( i = 0 ; i < count; i++) + { + if(protocolType == MV_NON_UDMA_PROTOCOL_PACKET_PIO_DATA_IN) + { + dataBufPtr[i] = MV_REG_READ_WORD(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET); + } + else + { + MV_REG_WRITE_WORD(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET, dataBufPtr[i]); + + } + } + + /* Wait for the storage device to be available */ + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: on non-UDMA sequence - checking if" + " device is has finished the command\n", + pAdapter->adapterId, channelIndex); + + if (waitWhileStorageDevIsBusy(pAdapter, + ioBaseAddr, eDmaRegsOffset, 50000, 100) == + MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " Status: %x\n", + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + MV_ATA_DEVICE_STATUS_REG_OFFSET)); + + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + + if (waitForDRQToClear(pAdapter, ioBaseAddr, eDmaRegsOffset, 50000, 100) + == MV_FALSE) + { + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + } + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: Finish NonUdma Command. Status=0x%02x" + "\n", pAdapter->adapterId, channelIndex, + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET)); + enableStorageDevInterrupt(pSataChannel); + pSataChannel->recoveredErrorsCounter = 0; + return MV_TRUE; +} +#endif /* 0 */ +MV_BOOLEAN executeNonUDMACommand(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_NON_UDMA_PROTOCOL protocolType, + MV_BOOLEAN isEXT, + MV_U16_PTR bufPtr, MV_U32 count, + MV_U16 features, + MV_U16 sectorCount, + MV_U16 lbaLow, MV_U16 lbaMid, + MV_U16 lbaHigh, MV_U8 device, + MV_U8 command) +{ + MV_SATA_CHANNEL *pSataChannel = pAdapter->sataChannel[channelIndex]; + MV_BUS_ADDR_T ioBaseAddr = pAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset; + MV_U32 i; + MV_U8 ATAstatus; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_NON_UDMA_COMMAND, " %d %d Issue NON " + "UDMA command: protocol(%d) %p , %x , %x , %x , %x.%x.%x %x " + "command=%x\n", pAdapter->adapterId, channelIndex, protocolType, + bufPtr, count, features, sectorCount, lbaLow, lbaMid, + lbaHigh, device, command); + + eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + if ((PMPort) && ((pSataChannel->PMSupported == MV_FALSE) || + (pSataChannel->deviceType != MV_SATA_DEVICE_TYPE_PM))) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: executeNonUDMACommand" + " failed PM not supported for this channel\n", + pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + if (command != MV_ATA_COMMAND_PM_READ_REG && + command != MV_ATA_COMMAND_PM_WRITE_REG) + { + if (isStorageDevReadyForPIO(pSataChannel) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d : Error in Issue NON UDMA command:" + " isStorageDevReadyForPIO failed\n", + pAdapter->adapterId, channelIndex); + + return MV_FALSE; + } + } + _setActivePMPort(pSataChannel, PMPort); + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: PIO command failed:" + "EDMA is active\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber); + return MV_FALSE; + } + + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + disableStorageDevInterrupt(pSataChannel); + } + + if (isEXT == MV_TRUE) + { + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_FEATURES_REG_OFFSET, + (features & 0xff00) >> 8); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET, + (sectorCount & 0xff00) >> 8); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_LOW_REG_OFFSET, + (lbaLow & 0xff00) >> 8); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_MID_REG_OFFSET, + (lbaMid & 0xff00) >> 8); + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET, + (lbaHigh & 0xff00) >> 8); + } + else + { + if ((features & 0xff00) || (sectorCount & 0xff00) || (lbaLow & 0xff00) || + (lbaMid & 0xff00) || (lbaHigh & 0xff00)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + " %d %d : Error in Issue NON UDMA command:" + " bits[15:8] of register values should be reserved" + " Features 0x%02x, SectorCount 0x%02x, LBA Low 0x%02x," + " LBA Mid 0x%02x, LBA High 0x%02x\n", + pAdapter->adapterId, channelIndex, features, + sectorCount, lbaLow, lbaMid, lbaHigh); + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + } + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_FEATURES_REG_OFFSET, features & 0xff); + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET, sectorCount & 0xff); + + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_LOW_REG_OFFSET, lbaLow & 0xff); + + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_MID_REG_OFFSET, lbaMid & 0xff); + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET, lbaHigh & 0xff); + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_HEAD_REG_OFFSET, device); + MV_CPU_WRITE_BUFFER_FLUSH(); + + /* 88SX60X1 FEr SATA #16 */ + /* 88SX6042/88SX7042 FEr SATA #16 */ + /* 88F5182 FEr #SATA-S11 */ + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + enableStorageDevInterrupt(pSataChannel); + } + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_COMMAND_REG_OFFSET, command); + + if (protocolType == MV_NON_UDMA_PROTOCOL_NON_DATA) + { + /* Wait for the command to complete */ + if (waitWhileStorageDevIsBusy(pAdapter, ioBaseAddr, eDmaRegsOffset, 3100, 10000) == + MV_FALSE) + { + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + enableStorageDevInterrupt(pSataChannel); + pSataChannel->recoveredErrorsCounter = 0; + return MV_TRUE; + } + /* Wait for the command to complete */ + if (waitWhileStorageDevIsBusy(pAdapter, ioBaseAddr, eDmaRegsOffset, 3100, 10000) == + MV_FALSE) + { + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + /* Check the status register on DATA request commands */ + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + if (!(ATAstatus & MV_ATA_DATA_REQUEST_STATUS)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: DRQ bit in ATA STATUS" + " register is not set\n", pAdapter->adapterId, channelIndex); + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + } + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + + if (waitForDRQ(pAdapter, ioBaseAddr, eDmaRegsOffset, 500, 10000) + == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: DRQ bit in ATA STATUS" + " register is not set\n", pAdapter->adapterId, channelIndex); + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + } + for (i = 0; i < count; i++) + { + /* Every DRQ data block we have to check the BUSY bit to verify that + the Disk is ready for next block transfer */ + if ((i & (((MV_U32)pSataChannel->DRQDataBlockSize * ATA_SECTOR_SIZE_IN_WORDS) - 1)) == 0) + { + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + /* Perform a dummy read */ + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_ALTERNATE_REG_OFFSET); + /* 88SX60X1 FEr SATA #16 */ + /* 88SX6042/88SX7042 FEr SATA #16 */ + /* 88F5182 FEr #SATA-S11 */ + if (i != 0) + { + if (waitWhileStorageDevIsBusy_88SX60X1(pAdapter, + ioBaseAddr, eDmaRegsOffset, channelIndex, + 50000, 100) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "Sata device interrupt timeout...i = %d\n",i); + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + } + else + { + MV_U8 sataUnit = channelIndex >> 2,portNum = channelIndex & 3; + + if (waitWhileStorageDevIsBusy(pAdapter,ioBaseAddr, + eDmaRegsOffset, 50000, 100) == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "Busy bit timeout...i = %d\n",i); + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + MV_REG_WRITE_DWORD (ioBaseAddr, MV_SATAHC_REGS_BASE_OFFSET(sataUnit) + + MV_SATAHC_INTERRUPT_CAUSE_REG_OFFSET, + ~(1 << (8 + portNum))); + } + if (waitForDRQ(pAdapter, ioBaseAddr, eDmaRegsOffset, 50000, 100) + == MV_FALSE) + { + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + } + else if (pAdapter->sataAdapterGeneration == MV_SATA_GEN_I) + { + if (waitWhileStorageDevIsBusy(pAdapter, + ioBaseAddr, eDmaRegsOffset, + 50000, 100) == MV_FALSE) + { + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + } + } + if (protocolType == MV_NON_UDMA_PROTOCOL_PIO_DATA_IN) + { + bufPtr[i] = MV_REG_READ_WORD(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET); + } + else + { + MV_REG_WRITE_WORD(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_PIO_DATA_REG_OFFSET, bufPtr[i]); + MV_CPU_WRITE_BUFFER_FLUSH(); + } + } + + + /* Wait for the storage device to be available */ + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: on non-UDMA sequence - checking if" + " device is has finished the command\n", + pAdapter->adapterId, channelIndex); + + if (waitWhileStorageDevIsBusy(pAdapter, + ioBaseAddr, eDmaRegsOffset, 50000, 100) == + MV_FALSE) + { + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + + if (pAdapter->sataAdapterGeneration >= MV_SATA_GEN_II) + { + + if (waitForDRQToClear(pAdapter, ioBaseAddr, eDmaRegsOffset, 50000, 100) + == MV_FALSE) + { + enableStorageDevInterrupt(pSataChannel); + return MV_FALSE; + } + } + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, " %d %d: Finish NonUdma Command. Status=0x%02x" + "\n", pAdapter->adapterId, channelIndex, + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET)); + enableStorageDevInterrupt(pSataChannel); + pSataChannel->recoveredErrorsCounter = 0; + return MV_TRUE; +} +MV_BOOLEAN _PMAccessReg(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_U8 PMPort, MV_U8 PMReg, MV_U32 *pValue, + MV_STORAGE_DEVICE_REGISTERS *registerStruct, + MV_BOOLEAN isRead) +{ + MV_BOOLEAN result; + + if (isRead == MV_TRUE) + { + result = executeNonUDMACommand(pAdapter, channelIndex, + MV_SATA_PM_CONTROL_PORT, + MV_NON_UDMA_PROTOCOL_NON_DATA, + MV_TRUE/*isEXT*/, + NULL/*bufPtr*/, + 0/*count*/, + PMReg /*features*/, 0/*sectorCount*/, + 0 /*lbaLow*/, 0 /*lbaMid*/, 0 /*lbaHigh*/, + PMPort/*device*/, + MV_ATA_COMMAND_PM_READ_REG/*command*/); + if (result == MV_TRUE) + { + MV_BUS_ADDR_T ioBaseAddr = pAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset = pAdapter->sataChannel[channelIndex]->eDmaRegsOffset; + + *pValue = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET); + *pValue |= MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_LOW_REG_OFFSET) << 8; + *pValue |= MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_MID_REG_OFFSET) << 16; + *pValue |= MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET) << 24; + } + } + else + { + result = executeNonUDMACommand(pAdapter, channelIndex, + MV_SATA_PM_CONTROL_PORT, + MV_NON_UDMA_PROTOCOL_NON_DATA, + MV_TRUE/*isEXT*/, + NULL/*bufPtr*/, + 0/*count*/, + PMReg /*features*/, + (MV_U16)((*pValue) & 0xff)/*sectorCount*/, + (MV_U16)(((*pValue) & 0xff00) >> 8) /*lbaLow*/, + (MV_U16)(((*pValue) & 0xff0000) >> 16) /*lbaMid*/, + (MV_U16)(((*pValue) & 0xff000000) >> 24) /*lbaHigh*/, + PMPort/*device*/, + MV_ATA_COMMAND_PM_WRITE_REG/*command*/); + } + if (registerStruct) + { + dumpAtaDeviceRegisters(pAdapter, channelIndex, MV_FALSE, + registerStruct); + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG|MV_DEBUG_PM, " %d %d: %s PM Reg %s: PM Port %x" + ", PM Reg %d, value %x\n", pAdapter->adapterId, channelIndex, + (isRead == MV_TRUE) ? "Read" : "Write", + (result == MV_TRUE) ? "Succeeded" : "Failed", + PMPort, PMReg, *pValue); + + return result; +} + +MV_BOOLEAN waitForDRQToClear(MV_SATA_ADAPTER* pAdapter, + MV_BUS_ADDR_T ioBaseAddr, + MV_U32 eDmaRegsOffset, MV_U32 loops, + MV_U32 delayParam) +{ + MV_U8 ATAstatus = 0; + MV_U32 i; + + for (i = 0;i < loops; i++) + { + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if ((ATAstatus & MV_ATA_BUSY_STATUS) == 0) + { + if (!(ATAstatus & MV_ATA_DATA_REQUEST_STATUS)) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, "waitWhileStorageDevIsBusy: %d loops *" + "%d usecs\n", i, delayParam); + return MV_TRUE; + } + } + mvMicroSecondsDelay(pAdapter, delayParam); + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, "waitWhileStorageDevIsBusy: Time out - Device ERROR" + " Status: 0x%02x. loops %d, delay %d\n", ATAstatus, loops, delayParam); + + return MV_FALSE; +} + +void dumpAtaDeviceRegisters(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, MV_BOOLEAN isEXT, + MV_STORAGE_DEVICE_REGISTERS *pRegisters) +{ + MV_BUS_ADDR_T ioBaseAddr = pAdapter->adapterIoBaseAddress; + MV_U32 eDmaRegsOffset = pAdapter->sataChannel[channelIndex]->eDmaRegsOffset; + + if (pAdapter->sataAdapterGeneration < MV_SATA_GEN_IIE) + { + if (MV_REG_READ_DWORD(ioBaseAddr, eDmaRegsOffset + + MV_EDMA_COMMAND_REG_OFFSET) & MV_BIT0) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, + " %d %d: dumpAtaDeviceRegisters: Edma is active!!!\n", + pAdapter->adapterId, channelIndex); + return; + } + } + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_CONTROL_REG_OFFSET, 0); + + pRegisters->errorRegister = + MV_REG_READ_BYTE(ioBaseAddr, + eDmaRegsOffset + MV_ATA_DEVICE_ERROR_REG_OFFSET); + + pRegisters->sectorCountRegister = + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET) & 0x00ff; + pRegisters->lbaLowRegister = + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_LOW_REG_OFFSET) & 0x00ff; + + pRegisters->lbaMidRegister = + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_MID_REG_OFFSET) & 0x00ff; + + pRegisters->lbaHighRegister = + MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET) & 0x00ff; + + if (isEXT == MV_TRUE) + { + /*set the HOB bit of DEVICE CONTROL REGISTER */ + + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_CONTROL_REG_OFFSET, MV_BIT7); + + pRegisters->sectorCountRegister |= (MV_REG_READ_BYTE(ioBaseAddr, + eDmaRegsOffset + + MV_ATA_DEVICE_SECTOR_COUNT_REG_OFFSET) << 8) & 0xff00; + + pRegisters->lbaLowRegister |= (MV_REG_READ_BYTE(ioBaseAddr, + eDmaRegsOffset + MV_ATA_DEVICE_LBA_LOW_REG_OFFSET) << 8) + & 0xff00; + + pRegisters->lbaMidRegister |= (MV_REG_READ_BYTE(ioBaseAddr, + eDmaRegsOffset + MV_ATA_DEVICE_LBA_MID_REG_OFFSET) << 8) + & 0xff00; + + pRegisters->lbaHighRegister |= (MV_REG_READ_BYTE(ioBaseAddr, + eDmaRegsOffset + MV_ATA_DEVICE_LBA_HIGH_REG_OFFSET) << 8) + & 0xff00; + MV_REG_WRITE_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_CONTROL_REG_OFFSET, 0); + + } + + pRegisters->deviceRegister = MV_REG_READ_BYTE(ioBaseAddr, + eDmaRegsOffset + MV_ATA_DEVICE_HEAD_REG_OFFSET); + + pRegisters->statusRegister = MV_REG_READ_BYTE(ioBaseAddr, + eDmaRegsOffset + MV_ATA_DEVICE_STATUS_REG_OFFSET); + + +} + + +MV_BOOLEAN _doSoftReset(MV_SATA_CHANNEL *pSataChannel) +{ + MV_BUS_ADDR_T ioBaseAddr = pSataChannel->mvSataAdapter->adapterIoBaseAddress; + MV_U32 i; + MV_U8 ATAstatus; + MV_U32 eDmaRegsOffset = pSataChannel->eDmaRegsOffset; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_NON_UDMA_COMMAND | MV_DEBUG, "Issue SRST COMMAND\n"); + +/* Write to the Device Control register, bits 1,2: */ +/* - bit 1 (nIEN): is the enable bit for the device assertion of INTRQ */ +/* to the host. When the nIEN bit is set to one, or the device is not */ +/* selected, the device shall release the INTRQ signal. */ +/* - bit 2 (SRST): is the host software reset bit. */ + MV_REG_WRITE_BYTE(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_CONTROL_REG_OFFSET, MV_BIT2|MV_BIT1); + MV_REG_READ_BYTE(ioBaseAddr, pSataChannel->eDmaRegsOffset + + MV_ATA_DEVICE_CONTROL_REG_OFFSET); + mvMicroSecondsDelay(pSataChannel->mvSataAdapter, 10); + +/* enableStorageDevInterrupt will clear the SRST bit*/ + enableStorageDevInterrupt(pSataChannel); + + mvMicroSecondsDelay(pSataChannel->mvSataAdapter, 500); + mvMicroSecondsDelay(pSataChannel->mvSataAdapter, 500); + mvMicroSecondsDelay(pSataChannel->mvSataAdapter, 500); + mvMicroSecondsDelay(pSataChannel->mvSataAdapter, 500); + + for (i = 0;i < 31000; i++) + { + ATAstatus = MV_REG_READ_BYTE(ioBaseAddr, eDmaRegsOffset + + MV_ATA_DEVICE_STATUS_REG_OFFSET); + if ((ATAstatus & MV_ATA_BUSY_STATUS) == 0) + { + return MV_TRUE; + } + mvMicroSecondsDelay(pSataChannel->mvSataAdapter, 1000); + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: Software reset failed " + "Status=0x%02x\n", pSataChannel->mvSataAdapter->adapterId, + pSataChannel->channelNumber, ATAstatus); + + return MV_FALSE; +} + +/******************************************************************************* +* mvPMDevReadReg - Reads port multiplier's internal register +* +* +* DESCRIPTION: +* Performs PIO non-data command for reading port multiplier's internal +* register. +* +* INPUT: +* pAdapter - Pointer to the device data structure. +* channelIndex - Index of the required channel +* PMPort - This should be port 0xf +* PMReg - The required register to be read +* pValue - A pointer to 32bit data container that holds +* the result. +* registerStruct - A pointer to ATA register data structure. This +* holds the ATA registers dump after command +* is executed. +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_BOOLEAN mvPMDevReadReg(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_U8 PMPort, MV_U8 PMReg, MV_U32 *pValue, + MV_STORAGE_DEVICE_REGISTERS *registerStruct) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BOOLEAN result; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvStorageDevPMReadReg" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: channel data structu" + "re is not allocated\n", pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + + mvOsSemTake(&pSataChannel->semaphore); + if (pSataChannel->PMSupported == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvStorageDevPMReadReg" + " failed PM not supported for this channel\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvStorageDevPMReadReg" + " command failed: EDMA is active\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + + result = _PMAccessReg(pAdapter, channelIndex, PMPort, PMReg, pValue, + registerStruct, MV_TRUE); + + mvOsSemRelease( &pSataChannel->semaphore); + return result; +} + + + +/******************************************************************************* +* mvPMDevWriteReg - Writes to port multiplier's internal register +* +* +* DESCRIPTION: +* Performs PIO non-data command for writing to port multiplier's internal +* register. +* +* INPUT: +* pAdapter - Pointer to the device data structure. +* channelIndex - Index of the required channel +* PMPort - This should be port 0xf +* PMReg - The required register to be read +* value - Holds 32bit of the value to be written +* registerStruct - A pointer to ATA register data structure. This +* holds the ATA registers dump after command +* is executed. +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_BOOLEAN mvPMDevWriteReg(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_U8 PMPort, MV_U8 PMReg, MV_U32 value, + MV_STORAGE_DEVICE_REGISTERS *registerStruct) +{ + MV_SATA_CHANNEL *pSataChannel; + MV_BOOLEAN result; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvStorageDevPMWriteReg" + " Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: channel data structu" + "re is not allocated\n", pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + + mvOsSemTake(&pSataChannel->semaphore); + if (pSataChannel->PMSupported == MV_FALSE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvStorageDevPMWriteReg" + " failed PM not supported for this channel\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + if (pSataChannel->queueCommandsEnabled == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, " %d %d: mvStorageDevPMWriteReg" + " command failed: EDMA is active\n", + pAdapter->adapterId, channelIndex); + mvOsSemRelease( &pSataChannel->semaphore); + return MV_FALSE; + } + + result = _PMAccessReg(pAdapter, channelIndex, PMPort, PMReg, &value, + registerStruct, MV_FALSE); + + mvOsSemRelease( &pSataChannel->semaphore); + return result; +} + +static MV_BOOLEAN _checkPMPortSStatus(MV_SATA_ADAPTER* pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_BOOLEAN *error) +{ + MV_BOOLEAN result; + MV_U32 SStatus; + + result = mvPMDevReadReg(pAdapter, channelIndex, PMPort, + MV_SATA_PSCR_SSTATUS_REG_NUM, &SStatus, NULL); + + if (result == MV_FALSE) + { + *error = MV_TRUE; + return result; + } + *error = MV_FALSE; + SStatus &= (MV_BIT0 | MV_BIT1 | MV_BIT2); + if ((SStatus == (MV_BIT0 | MV_BIT1)) || (SStatus == 0)) + { + return MV_TRUE; + } + return MV_FALSE; +} + +MV_BOOLEAN mvPMLinkUp(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, MV_U8 PMPort, + MV_BOOLEAN force_gen1) +{ + MV_BOOLEAN result; + MV_U32 speed_force = 0; + + if(force_gen1 == MV_TRUE) + speed_force = 0x10; + + result = mvPMDevWriteReg(pAdapter, channelIndex, PMPort, + MV_SATA_PSCR_SCONTROL_REG_NUM, 0x301 | speed_force, NULL); + if (result == MV_FALSE) + { + return result; + } + mvMicroSecondsDelay(pAdapter, MV_SATA_COMM_INIT_DELAY); + result = mvPMDevWriteReg(pAdapter, channelIndex, PMPort, + MV_SATA_PSCR_SCONTROL_REG_NUM, 0x300 | speed_force, NULL); + return result; +} + +/******************************************************************************* +* mvPMDevEnableStaggeredSpinUp - +* +* +* DESCRIPTION: +* Enables commnucation on a port multiplier's device SATA channel +* +* INPUT: +* pAdapter - Pointer to the device data structure. +* channelIndex - Index of the required channel +* PMPort - Required device SATA channel on port multiplier +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_BOOLEAN mvPMDevEnableStaggeredSpinUp(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, MV_U8 PMPort) +{ + return mvPMLinkUp(pAdapter, channelIndex, PMPort, MV_FALSE); +} + + +/******************************************************************************* +* mvPMDevEnableStaggeredSpinUpAll - +* +* +* DESCRIPTION: +* Enables commnucation on all port multiplier's device SATA channels +* +* INPUT: +* pAdapter - Pointer to the device data structure. +* channelIndex - Index of the required channel +* PMNumOfPorts - Number of device SATA channel the port multiplier +* has. +* bitmask - A pointer to 16bit data container that holds +* a bitmask of '1' when the relevant port multiplier's +* device port staggered spinup operation is success. +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ + +MV_BOOLEAN mvPMDevEnableStaggeredSpinUpAll(MV_SATA_ADAPTER *pSataAdapter, + MV_U8 channelIndex, + MV_U8 PMNumOfPorts, + MV_U16 *bitmask) +{ + MV_U8 PMPort; + MV_U8 retryCount; + MV_U8 tmpBitmask = 1; + if (bitmask == NULL) + { + return MV_FALSE; + } + /*Do not issue staggered spinup for port 0 - already done because of + legacy port mode*/ + *bitmask = 1; + for (PMPort = 0; PMPort < PMNumOfPorts; PMPort++) + { + MV_BOOLEAN error; + /* if sata communication already done(No staggered spin-up)*/ + if (_checkPMPortSStatus(pSataAdapter, channelIndex, PMPort, &error) == + MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + "[%d %d %d]: sata communication already established.\n", + pSataAdapter->adapterId, channelIndex, PMPort); + tmpBitmask |= (1 << PMPort); + continue; + } + if (mvPMDevEnableStaggeredSpinUp(pSataAdapter, + channelIndex, + PMPort) == MV_TRUE) + { + tmpBitmask |= (1 << PMPort); + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "Error [%d %d %d]: " + "PM enable staggered spin-up failed.\n", + pSataAdapter->adapterId, channelIndex, PMPort); + return MV_FALSE; + } + } + mvMicroSecondsDelay(pSataAdapter, MV_SATA_COMM_INIT_WAIT_DELAY); + for (retryCount = 0; retryCount < 200; retryCount++) + { + for (PMPort = 0; PMPort < PMNumOfPorts; PMPort++) + { + MV_BOOLEAN error; + if ((*bitmask) & (1 << PMPort)) + { + continue; + } + if (_checkPMPortSStatus(pSataAdapter, + channelIndex, PMPort, &error) == MV_FALSE) + { + if (error == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "[%d %d %d]: " + "Fatal error - cannot read PM port SStatus.\n", + pSataAdapter->adapterId, channelIndex, PMPort); + break; + } + mvMicroSecondsDelay(pSataAdapter, 1000); + } + else + { + if (bitmask != NULL) + { + *bitmask |= (1 << PMPort); + } + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + "[%d %d %d] PM SATA PHY ready after %d msec\n", + pSataAdapter->adapterId, channelIndex, + PMPort, retryCount); + } + } + if (tmpBitmask == *bitmask) + { + break; + } + } + if (tmpBitmask != *bitmask) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "[%d %d %d]: " + "Some of PM ports PHY are not initialized.\n", + pSataAdapter->adapterId, channelIndex, PMPort); + + } + return MV_TRUE; +} + +/******************************************************************************* +* mvPMDevEnableStaggeredSpinUpPort - +* +* +* DESCRIPTION: +* Enables commnucation on port multiplier's device SATA port +* +* INPUT: +* pAdapter - Pointer to the device data structure. +* channelIndex - Index of the required channel +* PMPort - the port number +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_BOOLEAN mvPMDevEnableStaggeredSpinUpPort(MV_SATA_ADAPTER *pSataAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_BOOLEAN force_speed_gen1) + +{ + MV_U8 retryCount; + + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + "[%d %d %d]: init sata communication.\n", + pSataAdapter->adapterId, channelIndex, PMPort); + + if (mvPMLinkUp(pSataAdapter, channelIndex, PMPort, + force_speed_gen1) != MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "Error [%d %d %d]: " + "PM enable staggered spin-up failed.\n", + pSataAdapter->adapterId, channelIndex, PMPort); + return MV_FALSE; + } + mvMicroSecondsDelay(pSataAdapter, MV_SATA_COMM_INIT_WAIT_DELAY); + for (retryCount = 0; retryCount < 200; retryCount++) + { + MV_BOOLEAN error; + + if (_checkPMPortSStatus(pSataAdapter, + channelIndex, PMPort, &error) == MV_FALSE) + { + if (error == MV_TRUE) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_ERROR, + "[%d %d %d]: " + "Fatal error - cannot read PM port SStatus.\n", + pSataAdapter->adapterId, channelIndex, PMPort); + return MV_FALSE; + } + mvMicroSecondsDelay(pSataAdapter, 1000); + } + else + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG, + "[%d %d %d] PM SATA PHY ready after %d msec\n", + pSataAdapter->adapterId, channelIndex, + PMPort, retryCount); + break; + } + + } + + return MV_TRUE; +} + +/******************************************************************************* +* mvStorageDevExecutePIO - +* +* +* DESCRIPTION: +* Sends custom PIO command (polling driven) +* +* INPUT: +* pAdapter - pointer to the device data structure. +* channelIndex - index of the required channel +* PMPort - index of the required destination port multipliers +* device Port (0 if no PM available). +* protocolType - protocol type of the command +* isEXT - true when the given command is the EXTENDED +* bufPtr - pointer to the buffer to write/read to/from +* pInATARegs - Holds ATA registers for the command +* pOutATARegs - Holds ATA registers after the command completed +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* when the command is EXTENDED, then the high 8 bits of the 16 bits values +* will be written first, so they should hold the previous value as defined in +* the ATA 6 standard +*******************************************************************************/ +MV_BOOLEAN mvStorageDevExecutePIO(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_NON_UDMA_PROTOCOL protocolType, + MV_BOOLEAN isEXT, MV_U16_PTR bufPtr, + MV_U32 count, + MV_STORAGE_DEVICE_REGISTERS *pInATARegs, + MV_STORAGE_DEVICE_REGISTERS *pOutATARegs) +{ + MV_BOOLEAN result; + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : mvPMDevExecutePIO" + "Command Failed, Bad adapter data structure pointer\n"); + return MV_FALSE; + } + if (pAdapter->sataChannel[channelIndex] == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: mvPMDevExecutePIO" + "Command Failed, channel data structure not allocated\n", + pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + mvOsSemTake(&pAdapter->sataChannel[channelIndex]->semaphore); + result = executeNonUDMACommand(pAdapter, channelIndex, PMPort, + protocolType, isEXT, + bufPtr, count, pInATARegs->featuresRegister, + pInATARegs->sectorCountRegister, + pInATARegs->lbaLowRegister, + pInATARegs->lbaMidRegister, + pInATARegs->lbaHighRegister, + pInATARegs->deviceRegister, + pInATARegs->commandRegister); + if (pOutATARegs) + { + dumpAtaDeviceRegisters(pAdapter, channelIndex, isEXT, pOutATARegs); + } + mvOsSemRelease(&pAdapter->sataChannel[channelIndex]->semaphore); + return result; +} + +/******************************************************************************* +* mvStorageDevSetDeviceType - +* +* +* DESCRIPTION: +* Sets the device type connected directly to the specific adapter's +* SATA channel. +* +* INPUT: +* pAdapter - Pointer to the device data structure. +* channelIndex - Index of the required channel +* deviceType - Type of device +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_BOOLEAN mvStorageDevSetDeviceType(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_SATA_DEVICE_TYPE deviceType) +{ + MV_SATA_CHANNEL *pSataChannel; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + " mvStorageDevSetDeviceType Failed, Bad adapter data structure " + "pointer\n"); + return MV_SATA_DEVICE_TYPE_UNKNOWN; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: channel data structu" + "re is not allocated\n", pAdapter->adapterId, channelIndex); + return MV_FALSE; + } + + pSataChannel->deviceType = deviceType; + + return MV_TRUE; +} + +/******************************************************************************* +* mvStorageDevGetDeviceType - +* +* +* DESCRIPTION: +* Gets the device type connected directly to the specific adapter's +* SATA channel. +* +* INPUT: +* pAdapter - Pointer to the device data structure. +* channelIndex - Index of the required channel +* +* RETURN: +* MV_TRUE on success, MV_FALSE otherwise. +* COMMENTS: +* NONE +* +*******************************************************************************/ +MV_SATA_DEVICE_TYPE mvStorageDevGetDeviceType(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex) +{ + MV_SATA_CHANNEL *pSataChannel; + + if (pAdapter == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " : " + " mvStorageDevGetDeviceType Failed, Bad adapter data structure " + "pointer\n"); + return MV_SATA_DEVICE_TYPE_UNKNOWN; + } + pSataChannel = pAdapter->sataChannel[channelIndex]; + if (pSataChannel == NULL) + { + mvLogMsg(MV_CORE_DRIVER_LOG_ID, MV_DEBUG_FATAL_ERROR, " %d %d: " + "channel data structure is not allocated\n", + pAdapter->adapterId, channelIndex); + return MV_SATA_DEVICE_TYPE_UNKNOWN; + } + + return pSataChannel->deviceType; +} + diff --git a/board/mv_feroceon/mv_hal/sata/CoreDriver/mvStorageDev.h b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvStorageDev.h new file mode 100644 index 0000000..44e3d71 --- /dev/null +++ b/board/mv_feroceon/mv_hal/sata/CoreDriver/mvStorageDev.h @@ -0,0 +1,355 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/******************************************************************************* +* mvStorageDev.h - Header File for mvStorageDev.c. +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* mvSata.h. +* mvOs.h. +* ATA/ATAPI-6 standard +* +*******************************************************************************/ +#ifndef __INCmvStorageDevh +#define __INCmvStorageDevh +#ifdef __cplusplus + +extern "C" { +#endif /* __cplusplus */ + +/* Includes */ +#include "mvOsS.h" +#include "mvSata.h" +#include "mvRegs.h" + +/* Definitions */ + +/* ATA register on the ATA drive*/ + +#define MV_EDMA_ATA_FEATURES_ADDR 0x11 +#define MV_EDMA_ATA_SECTOR_COUNT_ADDR 0x12 +#define MV_EDMA_ATA_LBA_LOW_ADDR 0x13 +#define MV_EDMA_ATA_LBA_MID_ADDR 0x14 +#define MV_EDMA_ATA_LBA_HIGH_ADDR 0x15 +#define MV_EDMA_ATA_DEVICE_ADDR 0x16 +#define MV_EDMA_ATA_COMMAND_ADDR 0x17 + +#define MV_ATA_ERROR_STATUS MV_BIT0 +#define MV_ATA_DATA_REQUEST_STATUS MV_BIT3 +#define MV_ATA_SERVICE_STATUS MV_BIT4 +#define MV_ATA_DEVICE_FAULT_STATUS MV_BIT5 +#define MV_ATA_READY_STATUS MV_BIT6 +#define MV_ATA_BUSY_STATUS MV_BIT7 + + +#define MV_ATA_COMMAND_READ_SECTORS 0x20 +#define MV_ATA_COMMAND_READ_SECTORS_EXT 0x24 +#define MV_ATA_COMMAND_READ_LOG_EXT 0x2F +#define MV_ATA_COMMAND_READ_VERIFY_SECTORS 0x40 +#define MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT 0x42 +#define MV_ATA_COMMAND_READ_BUFFER 0xE4 +#define MV_ATA_COMMAND_WRITE_BUFFER 0xE8 +#define MV_ATA_COMMAND_WRITE_SECTORS 0x30 +#define MV_ATA_COMMAND_WRITE_SECTORS_EXT 0x34 +#define MV_ATA_COMMAND_DIAGNOSTIC 0x90 +#define MV_ATA_COMMAND_SMART 0xb0 +#define MV_ATA_COMMAND_READ_MULTIPLE 0xc4 +#define MV_ATA_COMMAND_WRITE_MULTIPLE 0xc5 +#define MV_ATA_COMMAND_STANDBY_IMMEDIATE 0xe0 +#define MV_ATA_COMMAND_IDLE_IMMEDIATE 0xe1 +#define MV_ATA_COMMAND_STANDBY 0xe2 +#define MV_ATA_COMMAND_IDLE 0xe3 +#define MV_ATA_COMMAND_SLEEP 0xe6 +#define MV_ATA_COMMAND_IDENTIFY 0xec +#define MV_ATA_COMMAND_ATAPI_IDENTIFY 0xa1 +#define MV_ATA_COMMAND_PACKET 0xa0 +#define MV_ATA_COMMAND_DEVICE_CONFIG 0xb1 +#define MV_ATA_COMMAND_SET_FEATURES 0xef +#define MV_ATA_COMMAND_WRITE_DMA 0xca +#define MV_ATA_COMMAND_WRITE_DMA_EXT 0x35 +#define MV_ATA_COMMAND_WRITE_DMA_QUEUED 0xcc +#define MV_ATA_COMMAND_WRITE_DMA_QUEUED_EXT 0x36 +#define MV_ATA_COMMAND_WRITE_FPDMA_QUEUED_EXT 0x61 +#define MV_ATA_COMMAND_READ_DMA 0xc8 +#define MV_ATA_COMMAND_READ_DMA_EXT 0x25 +#define MV_ATA_COMMAND_READ_DMA_QUEUED 0xc7 +#define MV_ATA_COMMAND_READ_DMA_QUEUED_EXT 0x26 +#define MV_ATA_COMMAND_READ_FPDMA_QUEUED_EXT 0x60 +#define MV_ATA_COMMAND_FLUSH_CACHE 0xe7 +#define MV_ATA_COMMAND_FLUSH_CACHE_EXT 0xea + +#define MV_ATA_COMMAND_PM_READ_REG 0xe4 +#define MV_ATA_COMMAND_PM_WRITE_REG 0xe8 + +#define MV_SATA_GSCR_ID_REG_NUM 0 +#define MV_SATA_GSCR_REVISION_REG_NUM 1 +#define MV_SATA_GSCR_INFO_REG_NUM 2 +#define MV_SATA_GSCR_ERROR_REG_NUM 32 +#define MV_SATA_GSCR_ERROR_ENABLE_REG_NUM 33 +#define MV_SATA_GSCR_FEATURES_REG_NUM 64 +#define MV_SATA_GSCR_FEATURES_ENABLE_REG_NUM 96 + + +#define MV_SATA_PSCR_SSTATUS_REG_NUM 0 +#define MV_SATA_PSCR_SERROR_REG_NUM 1 +#define MV_SATA_PSCR_SCONTROL_REG_NUM 2 +#define MV_SATA_PSCR_SACTIVE_REG_NUM 3 + + + +#define MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO 0x01 +#define MV_ATA_SET_FEATURES_ENABLE_WCACHE 0x02 /* Enable write cache */ +#define MV_ATA_SET_FEATURES_TRANSFER 0x03 /* Set transfer mode */ +#define MV_ATA_TRANSFER_UDMA_0 0x40 +#define MV_ATA_TRANSFER_UDMA_1 0x41 +#define MV_ATA_TRANSFER_UDMA_2 0x42 +#define MV_ATA_TRANSFER_UDMA_3 0x43 +#define MV_ATA_TRANSFER_UDMA_4 0x44 +#define MV_ATA_TRANSFER_UDMA_5 0x45 +#define MV_ATA_TRANSFER_UDMA_6 0x46 +#define MV_ATA_TRANSFER_UDMA_7 0x47 +#define MV_ATA_TRANSFER_PIO_SLOW 0x00 +#define MV_ATA_TRANSFER_PIO_0 0x08 +#define MV_ATA_TRANSFER_PIO_1 0x09 +#define MV_ATA_TRANSFER_PIO_2 0x0A +#define MV_ATA_TRANSFER_PIO_3 0x0B +#define MV_ATA_TRANSFER_PIO_4 0x0C + +/* Enable advanced power management */ +#define MV_ATA_SET_FEATURES_ENABLE_APM 0x05 + +/* Disable media status notification*/ +#define MV_ATA_SET_FEATURES_DISABLE_MSN 0x31 + +/* Disable read look-ahead */ +#define MV_ATA_SET_FEATURES_DISABLE_RLA 0x55 + +/* Enable release interrupt */ +#define MV_ATA_SET_FEATURES_ENABLE_RI 0x5D + +/* Enable SERVICE interrupt */ +#define MV_ATA_SET_FEATURES_ENABLE_SI 0x5E + +/* Disable revert power-on defaults */ +#define MV_ATA_SET_FEATURES_DISABLE_RPOD 0x66 + +/* Disable write cache */ +#define MV_ATA_SET_FEATURES_DISABLE_WCACHE 0x82 + +/* Disable advanced power management*/ +#define MV_ATA_SET_FEATURES_DISABLE_APM 0x85 + +/* Enable media status notification */ +#define MV_ATA_SET_FEATURES_ENABLE_MSN 0x95 + +/* Enable read look-ahead */ +#define MV_ATA_SET_FEATURES_ENABLE_RLA 0xAA + +/* Enable revert power-on defaults */ +#define MV_ATA_SET_FEATURES_ENABLE_RPOD 0xCC + +/* Disable release interrupt */ +#define MV_ATA_SET_FEATURES_DISABLE_RI 0xDD + +/* Disable SERVICE interrupt */ +#define MV_ATA_SET_FEATURES_DISABLE_SI 0xDE + +/* Defines for parsing the IDENTIFY command results*/ +#define IDEN_SERIAL_NUM_OFFSET 10 +#define IDEN_SERIAL_NUM_SIZE (20-10) +#define IDEN_FIRMWARE_OFFSET 23 +#define IDEN_FIRMWARE_SIZE (27-23) +#define IDEN_MODEL_OFFSET 27 +#define IDEN_MODEL_SIZE (47-27) +#define IDEN_CAPACITY_1_OFFSET 49 +#define IDEN_VALID 53 +#define IDEN_NUM_OF_ADDRESSABLE_SECTORS 60 +#define IDEN_PIO_MODE_SPPORTED 64 +#define IDEN_QUEUE_DEPTH 75 +#define IDEN_SATA_CAPABILITIES 76 +#define IDEN_SATA_FEATURES_SUPPORTED 78 +#define IDEN_SATA_FEATURES_ENABLED 79 +#define IDEN_ATA_VERSION 80 +#define IDEN_SUPPORTED_COMMANDS1 82 +#define IDEN_SUPPORTED_COMMANDS2 83 +#define IDEN_ENABLED_COMMANDS1 85 +#define IDEN_ENABLED_COMMANDS2 86 +#define IDEN_UDMA_MODE 88 + +/* Typedefs */ + +/* Structures */ + + typedef struct mvStorageDevRegisters + { +/* Fields set by CORE driver */ + MV_U8 errorRegister; + MV_U16 featuresRegister;/*input only*/ + MV_U8 commandRegister;/*input only*/ + MV_U16 sectorCountRegister; + MV_U16 lbaLowRegister; + MV_U16 lbaMidRegister; + MV_U16 lbaHighRegister; + MV_U8 deviceRegister; + MV_U8 statusRegister; + } MV_STORAGE_DEVICE_REGISTERS; + +/* Function */ + + MV_BOOLEAN mvStorageDevATAExecuteNonUDMACommand(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_NON_UDMA_PROTOCOL protocolType, + MV_BOOLEAN isEXT, + MV_U16_PTR bufPtr, MV_U32 count, + MV_U16 features, + MV_U16 sectorCount, + MV_U16 lbaLow, MV_U16 lbaMid, + MV_U16 lbaHigh, MV_U8 device, + MV_U8 command); + + MV_BOOLEAN mvStorageDevATAIdentifyDevice(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_U16_PTR identifyDeviceResult + ); + + MV_BOOLEAN mvStorageDevATASetFeatures(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_U8 subCommand, + MV_U8 subCommandSpecific1, + MV_U8 subCommandSpecific2, + MV_U8 subCommandSpecific3, + MV_U8 subCommandSpecific4); + + MV_BOOLEAN mvStorageDevATAIdleImmediate(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + + MV_BOOLEAN mvStorageDevATASoftResetDevice(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_STORAGE_DEVICE_REGISTERS *registerStruct + ); + +/*PM*/ + + MV_BOOLEAN mvPMDevReadReg(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_U8 PMPort, MV_U8 PMReg, MV_U32 *pValue, + MV_STORAGE_DEVICE_REGISTERS *registerStruct); + + MV_BOOLEAN mvPMDevWriteReg(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_U8 PMPort, MV_U8 PMReg, MV_U32 value, + MV_STORAGE_DEVICE_REGISTERS *registerStruct); + + MV_BOOLEAN mvPMDevEnableStaggeredSpinUp(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, MV_U8 PMPort); + + MV_BOOLEAN mvPMDevEnableStaggeredSpinUpAll(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMNumOfPorts, + MV_U16 *bitmask); + + MV_BOOLEAN mvPMDevEnableStaggeredSpinUpPort(MV_SATA_ADAPTER *pSataAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_BOOLEAN force_gen1); + + MV_BOOLEAN mvPMLinkUp(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, MV_U8 PMPort, + MV_BOOLEAN force_gen1); + + MV_BOOLEAN mvStorageDevExecutePIO(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort, + MV_NON_UDMA_PROTOCOL protocolType, + MV_BOOLEAN isEXT, MV_U16_PTR bufPtr, + MV_U32 count, + MV_STORAGE_DEVICE_REGISTERS *pInATARegs, + MV_STORAGE_DEVICE_REGISTERS *pOutATARegs); + + + MV_BOOLEAN mvStorageDevATAStartSoftResetDevice(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_U8 PMPort); + + MV_BOOLEAN mvStorageIsDeviceBsyBitOff(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex, + MV_STORAGE_DEVICE_REGISTERS *registerStruct + ); + + MV_BOOLEAN mvStorageDevSetDeviceType(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, + MV_SATA_DEVICE_TYPE deviceType); + + MV_SATA_DEVICE_TYPE mvStorageDevGetDeviceType(MV_SATA_ADAPTER *pAdapter, + MV_U8 channelIndex); + + +#ifdef __cplusplus + +} +#endif /* __cplusplus */ + +#endif /* __INCmvStorageDevh */ diff --git a/board/mv_feroceon/mv_hal/sata/mvCompVer.txt b/board/mv_feroceon/mv_hal/sata/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/sata/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/sflash/mvCompVer.txt b/board/mv_feroceon/mv_hal/sflash/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/sflash/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/sflash/mvSFlash.c b/board/mv_feroceon/mv_hal/sflash/mvSFlash.c new file mode 100644 index 0000000..4da1070 --- /dev/null +++ b/board/mv_feroceon/mv_hal/sflash/mvSFlash.c @@ -0,0 +1,1852 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvOs.h" +#include "sflash/mvSFlash.h" +#include "sflash/mvSFlashSpec.h" +#include "spi/mvSpi.h" +#include "spi/mvSpiCmnd.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +/*#define MV_DEBUG*/ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* Globals */ +static MV_SFLASH_DEVICE_PARAMS sflash[] = { + /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ + { + MV_M25P_WREN_CMND_OPCD, + MV_M25P_WRDI_CMND_OPCD, + MV_M25P_RDID_CMND_OPCD, + MV_M25P_RDSR_CMND_OPCD, + MV_M25P_WRSR_CMND_OPCD, + MV_M25P_READ_CMND_OPCD, + MV_M25P_FAST_RD_CMND_OPCD, + MV_M25P_PP_CMND_OPCD, + MV_M25P_SE_CMND_OPCD, + MV_M25P_BE_CMND_OPCD, + MV_M25P_RES_CMND_OPCD, + MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ + MV_M25P32_SECTOR_SIZE, + MV_M25P32_SECTOR_NUMBER, + MV_M25P_PAGE_SIZE, + "ST M25P32", + MV_M25PXXX_ST_MANF_ID, + MV_M25P32_DEVICE_ID, + MV_M25P32_MAX_SPI_FREQ, + MV_M25P32_MAX_FAST_SPI_FREQ, + MV_M25P32_FAST_READ_DUMMY_BYTES + }, + /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ + { + MV_M25P_WREN_CMND_OPCD, + MV_M25P_WRDI_CMND_OPCD, + MV_M25P_RDID_CMND_OPCD, + MV_M25P_RDSR_CMND_OPCD, + MV_M25P_WRSR_CMND_OPCD, + MV_M25P_READ_CMND_OPCD, + MV_M25P_FAST_RD_CMND_OPCD, + MV_M25P_PP_CMND_OPCD, + MV_M25P_SE_CMND_OPCD, + MV_M25P_BE_CMND_OPCD, + MV_M25P_RES_CMND_OPCD, + MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ + MV_M25P64_SECTOR_SIZE, + MV_M25P64_SECTOR_NUMBER, + MV_M25P_PAGE_SIZE, + "ST M25P64", + MV_M25PXXX_ST_MANF_ID, + MV_M25P64_DEVICE_ID, + MV_M25P64_MAX_SPI_FREQ, + MV_M25P64_MAX_FAST_SPI_FREQ, + MV_M25P64_FAST_READ_DUMMY_BYTES + }, + /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ + { + MV_M25P_WREN_CMND_OPCD, + MV_M25P_WRDI_CMND_OPCD, + MV_M25P_RDID_CMND_OPCD, + MV_M25P_RDSR_CMND_OPCD, + MV_M25P_WRSR_CMND_OPCD, + MV_M25P_READ_CMND_OPCD, + MV_M25P_FAST_RD_CMND_OPCD, + MV_M25P_PP_CMND_OPCD, + MV_M25P_SE_CMND_OPCD, + MV_M25P_BE_CMND_OPCD, + MV_M25P_RES_CMND_OPCD, + MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ + MV_M25P128_SECTOR_SIZE, + MV_M25P128_SECTOR_NUMBER, + MV_M25P_PAGE_SIZE, + "ST M25P128", + MV_M25PXXX_ST_MANF_ID, + MV_M25P128_DEVICE_ID, + MV_M25P128_MAX_SPI_FREQ, + MV_M25P128_MAX_FAST_SPI_FREQ, + MV_M25P128_FAST_READ_DUMMY_BYTES + }, + /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ + { + MV_MX25L_WREN_CMND_OPCD, + MV_MX25L_WRDI_CMND_OPCD, + MV_MX25L_RDID_CMND_OPCD, + MV_MX25L_RDSR_CMND_OPCD, + MV_MX25L_WRSR_CMND_OPCD, + MV_MX25L_READ_CMND_OPCD, + MV_MX25L_FAST_RD_CMND_OPCD, + MV_MX25L_PP_CMND_OPCD, + MV_MX25L_SE_CMND_OPCD, + MV_MX25L_BE_CMND_OPCD, + MV_MX25L_RES_CMND_OPCD, + MV_MX25L_DP_CMND_OPCD, + MV_MX25L6405_SECTOR_SIZE, + MV_MX25L6405_SECTOR_NUMBER, + MV_MXIC_PAGE_SIZE, + "MXIC MX25L6405", + MV_MXIC_MANF_ID, + MV_MX25L6405_DEVICE_ID, + MV_MX25L6405_MAX_SPI_FREQ, + MV_MX25L6405_MAX_FAST_SPI_FREQ, + MV_MX25L6405_FAST_READ_DUMMY_BYTES + }, + /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ + { + MV_S25FL_WREN_CMND_OPCD, + MV_S25FL_WRDI_CMND_OPCD, + MV_S25FL_RDID_CMND_OPCD, + MV_S25FL_RDSR_CMND_OPCD, + MV_S25FL_WRSR_CMND_OPCD, + MV_S25FL_READ_CMND_OPCD, + MV_S25FL_FAST_RD_CMND_OPCD, + MV_S25FL_PP_CMND_OPCD, + MV_S25FL_SE_CMND_OPCD, + MV_S25FL_BE_CMND_OPCD, + MV_S25FL_RES_CMND_OPCD, + MV_S25FL_DP_CMND_OPCD, + MV_S25FL128_SECTOR_SIZE, + MV_S25FL128_SECTOR_NUMBER, + MV_S25FL_PAGE_SIZE, + "SPANSION S25FL128", + MV_SPANSION_MANF_ID, + MV_S25FL128_DEVICE_ID, + MV_S25FL128_MAX_SPI_FREQ, + MV_M25P128_MAX_FAST_SPI_FREQ, + MV_M25P128_FAST_READ_DUMMY_BYTES + }, +#if defined(CONFIG_BUFFALO_PLATFORM) + /* SST 25VF040 SPI flash, 4MB, 64 sectors of 64K each */ + { + MV_25VF_WREN_CMND_OPCD, + MV_25VF_WRDI_CMND_OPCD, + MV_25VF_RDID_CMND_OPCD, + MV_25VF_RDSR_CMND_OPCD, + MV_25VF_WRSR_CMND_OPCD, + MV_25VF_READ_CMND_OPCD, + MV_25VF_FAST_RD_CMND_OPCD, + MV_25VF_PP_CMND_OPCD, + MV_25VF_SE_CMND_OPCD, + MV_25VF_BE_CMND_OPCD, + MV_25VF_RES_CMND_OPCD, + MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ + MV_25VF040_SECTOR_SIZE, + MV_25VF040_SECTOR_NUMBER, + MV_25VF_PAGE_SIZE, + "SST 25VF040", + MV_25VFXXX_ST_MANF_ID, + MV_25VF040_DEVICE_ID, + MV_25VF040_MAX_SPI_FREQ, + MV_25VF040_MAX_FAST_SPI_FREQ, + MV_25VF040_FAST_READ_DUMMY_BYTES + }, + /* ST M25P40 SPI flash, 512B, 8 sectors of 64K each */ + { + MV_M25P_WREN_CMND_OPCD, + MV_M25P_WRDI_CMND_OPCD, + MV_M25P_RDID_CMND_OPCD, + MV_M25P_RDSR_CMND_OPCD, + MV_M25P_WRSR_CMND_OPCD, + MV_M25P_READ_CMND_OPCD, + MV_M25P_FAST_RD_CMND_OPCD, + MV_M25P_PP_CMND_OPCD, + MV_M25P_SE_CMND_OPCD, + MV_M25P_BE_CMND_OPCD, + MV_M25P_RES_CMND_OPCD, + MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ + MV_M25P40_SECTOR_SIZE, + MV_M25P40_SECTOR_NUMBER, + MV_M25P_PAGE_SIZE, + "ST M25P40", + MV_M25PXXX_ST_MANF_ID, + MV_M25P40_DEVICE_ID, + MV_M25P40_MAX_SPI_FREQ, + MV_M25P40_MAX_FAST_SPI_FREQ, + MV_M25P40_FAST_READ_DUMMY_BYTES + }, + /* Macronix MXIC MX25L4006E SPI flash, 4Mbit, 128 sectors of 4K each */ + { + MV_MX25L_WREN_CMND_OPCD, + MV_MX25L_WRDI_CMND_OPCD, + MV_MX25L_RDID_CMND_OPCD, + MV_MX25L_RDSR_CMND_OPCD, + MV_MX25L_WRSR_CMND_OPCD, + MV_MX25L_READ_CMND_OPCD, + MV_MX25L_FAST_RD_CMND_OPCD, + MV_MX25L_PP_CMND_OPCD, + MV_MX25L_SE_CMND_OPCD, + MV_MX25L_BE_CMND_OPCD, + MV_MX25L_RES_CMND_OPCD, + MV_MX25L_DP_CMND_OPCD, + MV_MX25L4006E_SECTOR_SIZE, + MV_MX25L4006E_SECTOR_NUMBER, + MV_MXIC_PAGE_SIZE, + "MXIC MX25L4006E", + MV_MXIC_MANF_ID, + MV_MX25L4006E_DEVICE_ID, + MV_MX25L4006E_MAX_SPI_FREQ, + MV_MX25L4006E_MAX_FAST_SPI_FREQ, + MV_MX25L4006E_FAST_READ_DUMMY_BYTES + }, + /* Macronix MXIC MX25L1606E SPI flash, 16Mbit, 512 sectors of 4K each */ + { + MV_MX25L_WREN_CMND_OPCD, + MV_MX25L_WRDI_CMND_OPCD, + MV_MX25L_RDID_CMND_OPCD, + MV_MX25L_RDSR_CMND_OPCD, + MV_MX25L_WRSR_CMND_OPCD, + MV_MX25L_READ_CMND_OPCD, + MV_MX25L_FAST_RD_CMND_OPCD, + MV_MX25L_PP_CMND_OPCD, + MV_MX25L_SE_CMND_OPCD, + MV_MX25L_BE_CMND_OPCD, + MV_MX25L_RES_CMND_OPCD, + MV_MX25L_DP_CMND_OPCD, + MV_MX25L1606E_SECTOR_SIZE, + MV_MX25L1606E_SECTOR_NUMBER, + MV_MXIC_PAGE_SIZE, + "MXIC MX25L1606E", + MV_MXIC_MANF_ID, + MV_MX25L1606E_DEVICE_ID, + MV_MX25L1606E_MAX_SPI_FREQ, + MV_MX25L1606E_MAX_FAST_SPI_FREQ, + MV_MX25L1606E_FAST_READ_DUMMY_BYTES + }, + /* Winbond SPI flash, 4Mbit, 128 sectors of 4K each */ + { + MV_WINBOND_WREN_CMND_OPCD, + MV_WINBOND_WRDI_CMND_OPCD, + MV_WINBOND_RDID_CMND_OPCD, + MV_WINBOND_RDSR_CMND_OPCD, + MV_WINBOND_WRSR_CMND_OPCD, + MV_WINBOND_READ_CMND_OPCD, + MV_WINBOND_FAST_RD_CMND_OPCD, + MV_WINBOND_PP_CMND_OPCD, + MV_WINBOND_SE_CMND_OPCD, + MV_WINBOND_BE_CMND_OPCD, + MV_WINBOND_RES_CMND_OPCD, + MV_WINBOND_DP_CMND_OPCD, + MV_WINBOND_SECTOR_SIZE, + MV_WINBOND_SECTOR_NUMBER, + MV_WINBOND_PAGE_SIZE, + "WINBOND 25X40BVNIG", + MV_WINBOND_MANF_ID, + MV_WINBOND_DEVICE_ID, + MV_WINBOND_MAX_SPI_FREQ, + MV_WINBOND_MAX_FAST_SPI_FREQ, + MV_WINBOND_FAST_READ_DUMMY_BYTES + }, + /* ESMT SPI flash, 4Mbit, 128 sectors of 4K each */ + { + MV_ESMT_WREN_CMND_OPCD, + MV_ESMT_WRDI_CMND_OPCD, + MV_ESMT_RDID_CMND_OPCD, + MV_ESMT_RDSR_CMND_OPCD, + MV_ESMT_WRSR_CMND_OPCD, + MV_ESMT_READ_CMND_OPCD, + MV_ESMT_FAST_RD_CMND_OPCD, + MV_ESMT_PP_CMND_OPCD, + MV_ESMT_SE_CMND_OPCD, + MV_ESMT_BE_CMND_OPCD, + MV_ESMT_RES_CMND_OPCD, + MV_ESMT_DP_CMND_OPCD, + MV_ESMT_SECTOR_SIZE, + MV_ESMT_SECTOR_NUMBER, + MV_ESMT_PAGE_SIZE, + "ESMT F25L04PA(2D)", + MV_ESMT_MANF_ID, + MV_ESMT_DEVICE_ID, + MV_ESMT_MAX_SPI_FREQ, + MV_ESMT_MAX_FAST_SPI_FREQ, + MV_ESMT_FAST_READ_DUMMY_BYTES + }, +#endif // CONFIG_BUFFALO_PLATFORM +}; + +/* Static Functions */ +static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); +static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); +static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); +static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); +static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ + MV_U8* pPageBuff, MV_U32 buffSize); +static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ + MV_U8* manId, MV_U16* devId); + +/******************************************************************************* +* mvWriteEnable - serialize the write enable sequence +* +* DESCRIPTION: +* transmit the sequence for write enable +* +********************************************************************************/ +static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) +{ + MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; + + + cmd[0] = sflash[pFlinfo->index].opcdWREN; + + return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); +} + +/******************************************************************************* +* mvStatusRegGet - Retrieve the value of the status register +* +* DESCRIPTION: +* perform the RDSR sequence to get the 8bit status register +* +********************************************************************************/ +static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; + MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; + + + + + cmd[0] = sflash[pFlinfo->index].opcdRDSR; + + if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, + MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) + return ret; + + *pStatReg = sr[0]; + + return MV_OK; +} + +/******************************************************************************* +* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared +* +* DESCRIPTION: +* Block waiting for the WIP (write in progress) to be cleared +* +********************************************************************************/ +static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) +{ + MV_STATUS ret; + MV_U32 i; + MV_U8 stat; + + for (i=0; iindex].opcdWRSR; + cmd[1] = sr; + + if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) + return ret; + + if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) + return ret; + + mvOsDelay(1); + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashPageWr - Write up to 256 Bytes in the same page +* +* DESCRIPTION: +* Write a buffer up to the page size in length provided that the whole address +* range is within the same page (alligned to page bounderies) +* +*******************************************************************************/ +static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pPageBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; + + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* check that we do not cross the page bounderies */ + if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > + sflash[pFlinfo->index].pageSize) + { + DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) + return MV_OUT_OF_RANGE; + } + + /* Issue the Write enable command prior the page program command */ + if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) + return ret; + + cmd[0] = sflash[pFlinfo->index].opcdPP; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) + return ret; + + if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from +* the device using the default RDID opcode and the default WREN opcode. +* +* DESCRIPTION: +* This is used to detect a generic device that uses the default opcodes +* for the WREN and RDID. +* +********************************************************************************/ +static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) +{ + MV_STATUS ret; + MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; + MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; + + + + /* Use the default RDID opcode to read the IDs */ + cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ + if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) + return ret; + + *manId = id[0]; + *devId = 0; + *devId |= (id[1] << 8); + *devId |= id[2]; + + return MV_OK; +} + +/* +##################################################################################### +##################################################################################### +*/ + +/******************************************************************************* +* mvSFlashInit - Initialize the serial flash device +* +* DESCRIPTION: +* Perform the neccessary initialization and configuration +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* pFlinfo->baseAddr: base address in fast mode. +* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI +* flash device does not support read Id command with +* the standard opcode, then the user should supply this +* as an input to skip the autodetection process!!!! +* +* OUTPUT: +* pFlinfo: pointer to the Flash information structure after detection +* pFlinfo->manufacturerId: Manufacturer ID +* pFlinfo->deviceId: Device ID +* pFlinfo->sectorSize: size of the sector (all sectors are the same). +* pFlinfo->sectorNumber: number of sectors. +* pFlinfo->pageSize: size of the page. +* pFlinfo->index: Index of the detected flash in the sflash tabel +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) +{ + MV_STATUS ret; + MV_U8 manf; + MV_U16 dev; + MV_U32 indx; + MV_BOOL detectFlag = MV_FALSE; + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ + if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) + { + mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); + return ret; + } + + /* First try to read the Manufacturer and Device IDs */ + if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) + { + mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); + return ret; + } + + /* loop over the whole table and look for the appropriate SFLASH */ + for (indx=0; indxmanufacturerId = manf; + pFlinfo->deviceId = dev; + pFlinfo->index = indx; + detectFlag = MV_TRUE; + } + } + + if(!detectFlag) + { + mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); + return MV_FAIL; + } + + /* fill the info based on the model detected */ + pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; + pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; + pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; + + /* Set the SPI frequency to the MAX allowed for the device for best performance */ + if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) + { + mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); + return ret; + } + + /* As default lock the SR */ + if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashSectorErase - Erasse a single sector of the serial flash +* +* DESCRIPTION: +* Issue the erase sector command and address +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* secNumber: sector Number to erase (0 -> (sectorNumber-1)) +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; + + MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); +#if 0 + MV_U32 i; + MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); + MV_U32 erasedWord = 0xFFFFFFFF; + MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); + MV_BOOL eraseNeeded = MV_FALSE; +#endif + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* check that the sector number is valid */ + if (secNumber >= pFlinfo->sectorNumber) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* we don't want to access SPI in direct mode from in-direct API, + becasue of timing issue between CS asserts. */ +#if 0 + /* First compare to FF and check if erase is needed */ + for (i=0; iindex].opcdSE; + cmd[1] = ((secAddr >> 16) & 0xFF); + cmd[2] = ((secAddr >> 8) & 0xFF); + cmd[3] = (secAddr & 0xFF); + + /* Issue the Write enable command prior the sector erase command */ + if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) + return ret; + + if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) + return ret; + + if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashChipErase - Erasse the whole serial flash +* +* DESCRIPTION: +* Issue the bulk (chip) erase command +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; + + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + cmd[0] = sflash[pFlinfo->index].opcdBE; + + /* Issue the Write enable command prior the Bulk erase command */ + if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) + return ret; + + if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) + return ret; + + if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashBlockRd - Read from the serial flash +* +* DESCRIPTION: +* Issue the read command and address then perfom the needed read +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* offset: byte offset with the flash to start reading from +* pReadBuff: pointer to the buffer to read the data in +* buffSize: size of the buffer to read. +* +* OUTPUT: +* pReadBuff: pointer to the buffer containing the read data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pReadBuff, MV_U32 buffSize) +{ + MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; + + + /* check for NULL pointer */ + if ((pFlinfo == NULL) || (pReadBuff == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + cmd[0] = sflash[pFlinfo->index].opcdREAD; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); +} + +/******************************************************************************* +* mvSFlashFastBlockRd - Fast read from the serial flash +* +* DESCRIPTION: +* Issue the fast read command and address then perfom the needed read +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* offset: byte offset with the flash to start reading from +* pReadBuff: pointer to the buffer to read the data in +* buffSize: size of the buffer to read. +* +* OUTPUT: +* pReadBuff: pointer to the buffer containing the read data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pReadBuff, MV_U32 buffSize) +{ + MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; + MV_STATUS ret; + + /* check for NULL pointer */ + if ((pFlinfo == NULL) || (pReadBuff == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* Set the SPI frequency to the MAX allowed for fast-read operations */ + mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); + if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) + { + mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); + return ret; + } + + cmd[0] = sflash[pFlinfo->index].opcdFSTRD; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + + ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, + sflash[pFlinfo->index].spiFastRdDummyBytes); + + /* Reset the SPI frequency to the MAX allowed for the device for best performance */ + if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) + { + mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); + return ret; + } + + return ret; +} + + +/******************************************************************************* +* mvSFlashBlockWr - Write a buffer with any size +* +* DESCRIPTION: +* write regardless of the page boundaries and size limit per Page +* program command +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* offset: byte offset within the flash region +* pWriteBuff: pointer to the buffer holding the data to program +* buffSize: size of the buffer to write +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pWriteBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + MV_U32 data2write = buffSize; + MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); + MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); + MV_U32 writeOffset = offset; + + /* check for NULL pointer */ +#ifndef CONFIG_MARVELL + if(NULL == pWriteBuff) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } +#endif + + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* check that the buffer size does not exceed the flash size */ + if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) + { + DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) + return MV_OUT_OF_RANGE; + } + + /* check if the total block size is less than the first chunk remainder */ + if (data2write < preAllSz) + preAllSz = data2write; + + /* check if programing does not start at a 64byte alligned offset */ + if (preAllSz) + { + if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) + return ret; + + /* increment pointers and counters */ + writeOffset += preAllSz; + data2write -= preAllSz; + pWriteBuff += preAllSz; + } + + /* program the data that fits in complete page chunks */ + while (data2write >= sflash[pFlinfo->index].pageSize) + { + if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) + return ret; + + /* increment pointers and counters */ + writeOffset += sflash[pFlinfo->index].pageSize; + data2write -= sflash[pFlinfo->index].pageSize; + pWriteBuff += sflash[pFlinfo->index].pageSize; + } + + /* program the last partial chunk */ + if (data2write) + { + if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) + return ret; + } + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashIdGet - Get the manufacturer and device IDs. +* +* DESCRIPTION: +* Get the Manufacturer and device IDs from the serial flash through +* writing the RDID command then reading 3 bytes of data. In case that +* this command was called for the first time in order to detect the +* manufacturer and device IDs, then the default RDID opcode will be used +* unless the device index is indicated by the user (in case the SPI flash +* does not use the default RDID opcode). +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* pManId: pointer to the 8bit variable to hold the manufacturing ID +* pDevId: pointer to the 16bit variable to hold the device ID +* +* OUTPUT: +* pManId: pointer to the 8bit variable holding the manufacturing ID +* pDevId: pointer to the 16bit variable holding the device ID +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; + MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; + + + + /* check for NULL pointer */ + if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); + else + cmd[0] = sflash[pFlinfo->index].opcdRDID; + + if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) + return ret; + + *pManId = id[0]; + *pDevId = 0; + *pDevId |= (id[1] << 8); + *pDevId |= id[2]; + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashWpRegionSet - Set the Write-Protected region +* +* DESCRIPTION: +* Set the Write-Protected region +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* wpRegion: which region will be protected +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) +{ + MV_U8 wpMask; + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* Check if the chip is an ST flash; then WP supports only 3 bits */ + if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) + { + switch (wpRegion) + { + case MV_WP_NONE: + wpMask = MV_M25P_STATUS_BP_NONE; + break; + + case MV_WP_UPR_1OF128: + DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + + case MV_WP_UPR_1OF64: + wpMask = MV_M25P_STATUS_BP_1_OF_64; + break; + + case MV_WP_UPR_1OF32: + wpMask = MV_M25P_STATUS_BP_1_OF_32; + break; + + case MV_WP_UPR_1OF16: + wpMask = MV_M25P_STATUS_BP_1_OF_16; + break; + + case MV_WP_UPR_1OF8: + wpMask = MV_M25P_STATUS_BP_1_OF_8; + break; + + case MV_WP_UPR_1OF4: + wpMask = MV_M25P_STATUS_BP_1_OF_4; + break; + + case MV_WP_UPR_1OF2: + wpMask = MV_M25P_STATUS_BP_1_OF_2; + break; + + case MV_WP_ALL: + wpMask = MV_M25P_STATUS_BP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + } + /* check if the manufacturer is MXIC then the WP is 4bits */ + else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) + { + switch (wpRegion) + { + case MV_WP_NONE: + wpMask = MV_MX25L_STATUS_BP_NONE; + break; + + case MV_WP_UPR_1OF128: + wpMask = MV_MX25L_STATUS_BP_1_OF_128; + break; + + case MV_WP_UPR_1OF64: + wpMask = MV_MX25L_STATUS_BP_1_OF_64; + break; + + case MV_WP_UPR_1OF32: + wpMask = MV_MX25L_STATUS_BP_1_OF_32; + break; + + case MV_WP_UPR_1OF16: + wpMask = MV_MX25L_STATUS_BP_1_OF_16; + break; + + case MV_WP_UPR_1OF8: + wpMask = MV_MX25L_STATUS_BP_1_OF_8; + break; + + case MV_WP_UPR_1OF4: + wpMask = MV_MX25L_STATUS_BP_1_OF_4; + break; + + case MV_WP_UPR_1OF2: + wpMask = MV_MX25L_STATUS_BP_1_OF_2; + break; + + case MV_WP_ALL: + wpMask = MV_MX25L_STATUS_BP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + } + /* check if the manufacturer is SPANSION then the WP is 4bits */ + else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) + { + switch (wpRegion) + { + case MV_WP_NONE: + wpMask = MV_S25FL_STATUS_BP_NONE; + break; + + case MV_WP_UPR_1OF128: + DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + + case MV_WP_UPR_1OF64: + wpMask = MV_S25FL_STATUS_BP_1_OF_64; + break; + + case MV_WP_UPR_1OF32: + wpMask = MV_S25FL_STATUS_BP_1_OF_32; + break; + + case MV_WP_UPR_1OF16: + wpMask = MV_S25FL_STATUS_BP_1_OF_16; + break; + + case MV_WP_UPR_1OF8: + wpMask = MV_S25FL_STATUS_BP_1_OF_8; + break; + + case MV_WP_UPR_1OF4: + wpMask = MV_S25FL_STATUS_BP_1_OF_4; + break; + + case MV_WP_UPR_1OF2: + wpMask = MV_S25FL_STATUS_BP_1_OF_2; + break; + + case MV_WP_ALL: + wpMask = MV_S25FL_STATUS_BP_ALL; + break; + + + default: + DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + } + else if (pFlinfo->manufacturerId == MV_WINBOND_MANF_ID) + { + switch (wpRegion) + { + case MV_WP_NONE: + wpMask = MV_WINBOND_STATUS_BP_NONE; + break; + /* + case MV_WP_UPR_1OF128: + wpMask = MV_WINBOND_STATUS_BP_1_OF_128; + break; + */ + case MV_WP_UPR_1OF64: + wpMask = MV_WINBOND_STATUS_BP_1_OF_64; + break; + + case MV_WP_UPR_1OF32: + wpMask = MV_WINBOND_STATUS_BP_1_OF_32; + break; + + case MV_WP_UPR_1OF16: + wpMask = MV_WINBOND_STATUS_BP_1_OF_16; + break; + + case MV_WP_UPR_1OF8: + wpMask = MV_WINBOND_STATUS_BP_1_OF_8; + break; + + case MV_WP_UPR_1OF4: + wpMask = MV_WINBOND_STATUS_BP_1_OF_4; + break; + + case MV_WP_UPR_1OF2: + wpMask = MV_WINBOND_STATUS_BP_1_OF_2; + break; + + case MV_WP_ALL: + wpMask = MV_WINBOND_STATUS_BP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + } + else if (pFlinfo->manufacturerId == MV_ESMT_MANF_ID) + { + switch (wpRegion) + { + case MV_WP_NONE: + wpMask = MV_ESMT_STATUS_BP_NONE; + break; + /* + case MV_WP_UPR_1OF128: + wpMask = MV_WINBOND_STATUS_BP_1_OF_128; + break; + */ + case MV_WP_UPR_1OF64: + wpMask = MV_ESMT_STATUS_BP_1_OF_64; + break; + + case MV_WP_UPR_1OF32: + wpMask = MV_ESMT_STATUS_BP_1_OF_32; + break; + + case MV_WP_UPR_1OF16: + wpMask = MV_ESMT_STATUS_BP_1_OF_16; + break; + + case MV_WP_UPR_1OF8: + wpMask = MV_ESMT_STATUS_BP_1_OF_8; + break; + + case MV_WP_UPR_1OF4: + wpMask = MV_ESMT_STATUS_BP_1_OF_4; + break; + + case MV_WP_UPR_1OF2: + wpMask = MV_ESMT_STATUS_BP_1_OF_2; + break; + + case MV_WP_ALL: + wpMask = MV_ESMT_STATUS_BP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + } + else + { + DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* Verify that the SRWD bit is always set - register is s/w locked */ + wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; + + return mvStatusRegSet(pFlinfo, wpMask); +} + +/******************************************************************************* +* mvSFlashWpRegionGet - Get the Write-Protected region configured +* +* DESCRIPTION: +* Get from the chip the Write-Protected region configured +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* pWpRegion: pointer to the variable to return the WP region in +* +* OUTPUT: +* wpRegion: pointer to the variable holding the WP region configured +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) +{ + MV_STATUS ret; + MV_U8 reg; + + /* check for NULL pointer */ + if ((pFlinfo == NULL) || (pWpRegion == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) + return ret; + + /* Check if the chip is an ST flash; then WP supports only 3 bits */ + if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) + { + switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) + { + case MV_M25P_STATUS_BP_NONE: + *pWpRegion = MV_WP_NONE; + break; + + case MV_M25P_STATUS_BP_1_OF_64: + *pWpRegion = MV_WP_UPR_1OF64; + break; + + case MV_M25P_STATUS_BP_1_OF_32: + *pWpRegion = MV_WP_UPR_1OF32; + break; + + case MV_M25P_STATUS_BP_1_OF_16: + *pWpRegion = MV_WP_UPR_1OF16; + break; + + case MV_M25P_STATUS_BP_1_OF_8: + *pWpRegion = MV_WP_UPR_1OF8; + break; + + case MV_M25P_STATUS_BP_1_OF_4: + *pWpRegion = MV_WP_UPR_1OF4; + break; + + case MV_M25P_STATUS_BP_1_OF_2: + *pWpRegion = MV_WP_UPR_1OF2; + break; + + case MV_M25P_STATUS_BP_ALL: + *pWpRegion = MV_WP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) + return MV_BAD_VALUE; + } + } + /* check if the manufacturer is MXIC then the WP is 4bits */ + else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) + { + switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) + { + case MV_MX25L_STATUS_BP_NONE: + *pWpRegion = MV_WP_NONE; + break; + + case MV_MX25L_STATUS_BP_1_OF_128: + *pWpRegion = MV_WP_UPR_1OF128; + break; + + case MV_MX25L_STATUS_BP_1_OF_64: + *pWpRegion = MV_WP_UPR_1OF64; + break; + + case MV_MX25L_STATUS_BP_1_OF_32: + *pWpRegion = MV_WP_UPR_1OF32; + break; + + case MV_MX25L_STATUS_BP_1_OF_16: + *pWpRegion = MV_WP_UPR_1OF16; + break; + + case MV_MX25L_STATUS_BP_1_OF_8: + *pWpRegion = MV_WP_UPR_1OF8; + break; + + case MV_MX25L_STATUS_BP_1_OF_4: + *pWpRegion = MV_WP_UPR_1OF4; + break; + + case MV_MX25L_STATUS_BP_1_OF_2: + *pWpRegion = MV_WP_UPR_1OF2; + break; + + case MV_MX25L_STATUS_BP_ALL: + *pWpRegion = MV_WP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) + return MV_BAD_VALUE; + } + } + else if (pFlinfo->manufacturerId == MV_WINBOND_MANF_ID) + { + switch ((reg & MV_WINBOND_STATUS_REG_WP_MASK)) + { + + case MV_WINBOND_STATUS_BP_NONE: + *pWpRegion = MV_WP_NONE; + break; + /* + case MV_WP_UPR_1OF128: + *pWpRegion = MV_WINBOND_STATUS_BP_1_OF_128; + break; + */ + case MV_WINBOND_STATUS_BP_1_OF_64: + *pWpRegion =MV_WP_UPR_1OF64; + break; + + case MV_WINBOND_STATUS_BP_1_OF_32: + *pWpRegion = MV_WP_UPR_1OF32; + break; + + case MV_WINBOND_STATUS_BP_1_OF_16: + *pWpRegion = MV_WP_UPR_1OF16; + break; + + case MV_WINBOND_STATUS_BP_1_OF_8: + *pWpRegion = MV_WP_UPR_1OF8; + break; + + case MV_WINBOND_STATUS_BP_1_OF_4: + *pWpRegion = MV_WP_UPR_1OF4; + break; + + case MV_WP_UPR_1OF2: + *pWpRegion = MV_WP_UPR_1OF2; + break; + + case MV_WINBOND_STATUS_BP_ALL : + + *pWpRegion = MV_WP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + } + else if (pFlinfo->manufacturerId == MV_ESMT_MANF_ID) + { + switch ((reg & MV_ESMT_STATUS_REG_WP_MASK)) + { + + case MV_ESMT_STATUS_BP_NONE: + *pWpRegion = MV_WP_NONE; + break; + /* + case MV_WP_UPR_1OF128: + *pWpRegion = MV_WINBOND_STATUS_BP_1_OF_128; + break; + */ + case MV_ESMT_STATUS_BP_1_OF_64: + *pWpRegion =MV_WP_UPR_1OF64; + break; + + case MV_ESMT_STATUS_BP_1_OF_32: + *pWpRegion = MV_WP_UPR_1OF32; + break; + + case MV_ESMT_STATUS_BP_1_OF_16: + *pWpRegion = MV_WP_UPR_1OF16; + break; + + case MV_ESMT_STATUS_BP_1_OF_8: + *pWpRegion = MV_WP_UPR_1OF8; + break; + + case MV_ESMT_STATUS_BP_1_OF_4: + *pWpRegion = MV_WP_UPR_1OF4; + break; + + case MV_WP_UPR_1OF2: + *pWpRegion = MV_WP_UPR_1OF2; + break; + + case MV_ESMT_STATUS_BP_ALL : + + *pWpRegion = MV_WP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + } + /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ + else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) + { + switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) + { + case MV_S25FL_STATUS_BP_NONE: + *pWpRegion = MV_WP_NONE; + break; + + case MV_S25FL_STATUS_BP_1_OF_64: + *pWpRegion = MV_WP_UPR_1OF64; + break; + + case MV_S25FL_STATUS_BP_1_OF_32: + *pWpRegion = MV_WP_UPR_1OF32; + break; + + case MV_S25FL_STATUS_BP_1_OF_16: + *pWpRegion = MV_WP_UPR_1OF16; + break; + + case MV_S25FL_STATUS_BP_1_OF_8: + *pWpRegion = MV_WP_UPR_1OF8; + break; + + case MV_S25FL_STATUS_BP_1_OF_4: + *pWpRegion = MV_WP_UPR_1OF4; + break; + + case MV_S25FL_STATUS_BP_1_OF_2: + *pWpRegion = MV_WP_UPR_1OF2; + break; + + case MV_S25FL_STATUS_BP_ALL: + *pWpRegion = MV_WP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) + return MV_BAD_VALUE; + } + } + else + { + DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp +* pin should be low to take effect +* +* DESCRIPTION: +* Lock the access to the Status Register for writing. This will +* cause the flash to enter the hardware protection mode if the W/Vpp +* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but +* the register will continue to be writable if WREN sequence was used. +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) +{ + MV_STATUS ret; + MV_U8 reg; + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) + return ret; + + if (srLock) + reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; + else + reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; + + return mvStatusRegSet(pFlinfo, reg); +} + +/******************************************************************************* +* mvSFlashSizeGet - Get the size of the SPI flash +* +* DESCRIPTION: +* based on the sector number and size of each sector calculate the total +* size of the flash memory. +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* Size of the flash in bytes. +* +* +*******************************************************************************/ +MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) +{ + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return 0; + } + + return (pFlinfo->sectorSize * pFlinfo->sectorNumber); +} + +/******************************************************************************* +* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode +* +* DESCRIPTION: +* Enter a special power save mode. +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* Size of the flash in bytes. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; + + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return 0; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* check that power save mode is supported in the specific device */ + if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) + { + DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + } + + cmd[0] = sflash[pFlinfo->index].opcdPwrSave; + + if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) + return ret; + + return MV_OK; + +} + +/******************************************************************************* +* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode +* +* DESCRIPTION: +* Exit the deep power save mode. +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* Size of the flash in bytes. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; + + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return 0; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* check that power save mode is supported in the specific device */ + if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) + { + DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + } + + cmd[0] = sflash[pFlinfo->index].opcdRES; + + if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) + return ret; + + /* add the delay needed for the device to wake up */ + mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ + + return MV_OK; + +} + +/******************************************************************************* +* mvSFlashModelGet - Retreive the string with the device manufacturer and model +* +* DESCRIPTION: +* Retreive the string with the device manufacturer and model +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* pointer to the string indicating the device manufacturer and model +* +* +*******************************************************************************/ +const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) +{ + static const MV_8 * unknModel = (const MV_8 *)"Unknown"; + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return 0; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return unknModel; + } + + return sflash[pFlinfo->index].deviceModel; +} + diff --git a/board/mv_feroceon/mv_hal/sflash/mvSFlash.h b/board/mv_feroceon/mv_hal/sflash/mvSFlash.h new file mode 100644 index 0000000..f441a5c --- /dev/null +++ b/board/mv_feroceon/mv_hal/sflash/mvSFlash.h @@ -0,0 +1,166 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSFlashH +#define __INCmvSFlashH + +#include "mvTypes.h" + +/* MCAROS */ +#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) +#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) + +/* Constants */ +#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF +/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ +#define MV_SFLASH_BASIC_SPI_FREQ 10000000 +/* enumerations */ +typedef enum +{ + MV_WP_NONE, /* Unprotect the whole chip */ + MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ + MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ + MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ + MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ + MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ + MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ + MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ + MV_WP_ALL /* Write protect the whole chip */ +} MV_SFLASH_WP_REGION; + +/* Type Definitions */ +typedef struct +{ + MV_U8 opcdWREN; /* Write enable opcode */ + MV_U8 opcdWRDI; /* Write disable opcode */ + MV_U8 opcdRDID; /* Read ID opcode */ + MV_U8 opcdRDSR; /* Read Status Register opcode */ + MV_U8 opcdWRSR; /* Write Status register opcode */ + MV_U8 opcdREAD; /* Read opcode */ + MV_U8 opcdFSTRD; /* Fast Read opcode */ + MV_U8 opcdPP; /* Page program opcode */ + MV_U8 opcdSE; /* Sector erase opcode */ + MV_U8 opcdBE; /* Bulk erase opcode */ + MV_U8 opcdRES; /* Read electronic signature */ + MV_U8 opcdPwrSave; /* Go into power save mode */ + MV_U32 sectorSize; /* Size of each sector */ + MV_U32 sectorNumber; /* Number of sectors */ + MV_U32 pageSize; /* size of each page */ + const char * deviceModel; /* string with the device model */ + MV_U32 manufacturerId; /* The manufacturer ID */ + MV_U32 deviceId; /* Device ID */ + MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ + MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ + MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ +} MV_SFLASH_DEVICE_PARAMS; + +typedef struct +{ + MV_U32 baseAddr; /* Flash Base Address used in fast mode */ + MV_U8 manufacturerId; /* Manufacturer ID */ + MV_U16 deviceId; /* Device ID */ + MV_U32 sectorSize; /* Size of each sector - all the same */ + MV_U32 sectorNumber; /* Number of sectors */ + MV_U32 pageSize; /* Page size - affect allignment */ + MV_U32 index; /* index of the device in the sflash table (internal parameter) */ +} MV_SFLASH_INFO; + +/* Function Prototypes */ +/* Init */ +MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); + +/* erase */ +MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); +MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); + +/* Read */ +MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pReadBuff, MV_U32 buffSize); +MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pReadBuff, MV_U32 buffSize); + +/* write regardless of the page boundaries and size limit per Page program command */ +MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pWriteBuff, MV_U32 buffSize); +/* Get IDs */ +MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); + +/* Set and Get the Write Protection region - if the Status register is not locked */ +MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); +MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); + +/* Lock the status register for writing - W/Vpp pin should be low to take effect */ +MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); + +/* Get the regions sizes */ +MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); + +/* Cause the falsh device to go into power save mode */ +MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); +MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); + +/* Retreive the string with the device manufacturer and model */ +const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); + +#endif /* __INCmvSFlashH */ diff --git a/board/mv_feroceon/mv_hal/sflash/mvSFlashSpec.h b/board/mv_feroceon/mv_hal/sflash/mvSFlashSpec.h new file mode 100644 index 0000000..e7b9f3b --- /dev/null +++ b/board/mv_feroceon/mv_hal/sflash/mvSFlashSpec.h @@ -0,0 +1,390 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSFlashSpecH +#define __INCmvSFlashSpecH + +/* Constants */ +#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ +#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ +#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ +#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ +#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ +#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ +#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ + +/* Status Register Bit Masks */ +#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ +#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ +#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ +#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) +#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) + +#define MV_SFLASH_MAX_WAIT_LOOP 1000000 +#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 + +#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ +#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ +#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 + +/********************************/ +/* ST M25Pxxx Device Specific */ +/********************************/ + +/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ +#define MV_M25PXXX_ST_MANF_ID 0x20 +#define MV_M25P32_DEVICE_ID 0x2016 +#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 +#define MV_M25P64_DEVICE_ID 0x2017 +#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 +#define MV_M25P128_DEVICE_ID 0x2018 +#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 +#if defined(CONFIG_BUFFALO_PLATFORM) +#define MV_M25P40_DEVICE_ID 0x2013 +#define MV_M25P40_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_M25P40_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_M25P40_FAST_READ_DUMMY_BYTES 1 +#endif + + +/* Sector Sizes and population per device model*/ +#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ +#define MV_M25P40_SECTOR_SIZE 0x10000 /* 64K */ +#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ +#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ +#define MV_M25P32_SECTOR_NUMBER 64 +#define MV_M25P40_SECTOR_NUMBER 8 +#define MV_M25P64_SECTOR_NUMBER 128 +#define MV_M25P128_SECTOR_NUMBER 64 +#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ + +#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ +#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ +#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ +#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ +#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ +#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ +#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ +#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ +#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ +#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ +#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ + +/* Status Register Write Protect Bit Masks - 3bits */ +#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) + +/************************************/ +/* MXIC MX25L6405 Device Specific */ +/************************************/ + +/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ +#define MV_MXIC_MANF_ID 0xC2 +#define MV_MX25L6405_DEVICE_ID 0x2017 +#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 +#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ + +/* Sector Sizes and population per device model*/ +#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ +#define MV_MX25L6405_SECTOR_NUMBER 128 +#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ + +#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ +#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ +#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ +#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ +#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ +#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ +#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ +#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ +#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ +#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ +#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ +#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ + +/* Status Register Write Protect Bit Masks - 4bits */ +#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) + +#if defined(CONFIG_BUFFALO_PLATFORM) +/************************************/ +/* MXIC MX25L4006E Device Specific total size: 128*4(kb) = 4Mbit = 0.5MB*/ +/************************************/ +#define MV_MX25L4006E_DEVICE_ID 0x2013 +#define MV_MX25L4006E_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_MX25L4006E_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_MX25L4006E_FAST_READ_DUMMY_BYTES 1 +/* Sector Sizes and population per device model*/ +//#define MV_MX25L4006E_SECTOR_SIZE 0x1000 /* 4K */ +//#define MV_MX25L4006E_SECTOR_NUMBER 128 +#define MV_MX25L4006E_SECTOR_SIZE 0x10000 /* 64K */ +#define MV_MX25L4006E_SECTOR_NUMBER 8 + +/************************************/ +/* MXIC MX25L1606E Device Specific total size: 512*4(kb) = 2MB*/ +/************************************/ +#define MV_MX25L1606E_DEVICE_ID 0x2015 +#define MV_MX25L1606E_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_MX25L1606E_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_MX25L1606E_FAST_READ_DUMMY_BYTES 1 +/* Sector Sizes and population per device model*/ +#define MV_MX25L1606E_SECTOR_SIZE 0x1000 /* 4K for each sector */ +#define MV_MX25L1606E_SECTOR_NUMBER 512 /*number of sectors*/ + +/************************************ + Winbond 4Mbit Spi flash +************************************/ +#define MV_WINBOND_WREN_CMND_OPCD 0x06 /* Write Enable */ +#define MV_WINBOND_WRDI_CMND_OPCD 0x04 /* Write Disable */ +#define MV_WINBOND_RDID_CMND_OPCD 0x9F /* Read ID */ +#define MV_WINBOND_RDSR_CMND_OPCD 0x05 /* Read Status Register */ +#define MV_WINBOND_WRSR_CMND_OPCD 0x01 /* Write Status Register */ +#define MV_WINBOND_READ_CMND_OPCD 0x03 /* Sequential Read */ +#define MV_WINBOND_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ +#define MV_WINBOND_PP_CMND_OPCD 0x02 /* Page Program */ +#define MV_WINBOND_SE_CMND_OPCD 0x20 /* Sector Erase */ +#define MV_WINBOND_BE_CMND_OPCD 0xC7 /* Bulk Erase */ +#define MV_WINBOND_DP_CMND_OPCD 0xB9 /* Deep Power Down */ +#define MV_WINBOND_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ + +#define MV_WINBOND_MANF_ID 0xEF /* Manufacture ID */ +#define MV_WINBOND_DEVICE_ID 0x3013 /* Winbond device ID */ +#define MV_WINBOND_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_WINBOND_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_WINBOND_FAST_READ_DUMMY_BYTES 1 + +/* Sector Sizes and population per device model*/ +/* #define MV_WINBOND_SECTOR_SIZE 0x1000 /\* 4K *\/ */ +/* #define MV_WINBOND_SECTOR_NUMBER 128 */ +#define MV_WINBOND_SECTOR_SIZE 0x10000 /* 64K */ +#define MV_WINBOND_SECTOR_NUMBER 8 +#define MV_WINBOND_PAGE_SIZE 0x100 /*256 bytes*/ + +#define MV_WINBOND_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_WINBOND_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_WINBOND_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_WINBOND_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_WINBOND_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_WINBOND_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_WINBOND_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_WINBOND_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_WINBOND_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) + +/************************************ + ESMT 4Mbit Spi flash +************************************/ +#define MV_ESMT_WREN_CMND_OPCD 0x06 /* Write Enable */ +#define MV_ESMT_WRDI_CMND_OPCD 0x04 /* Write Disable */ +#define MV_ESMT_RDID_CMND_OPCD 0x9F /* Read ID */ +#define MV_ESMT_RDSR_CMND_OPCD 0x05 /* Read Status Register */ +#define MV_ESMT_WRSR_CMND_OPCD 0x01 /* Write Status Register */ +#define MV_ESMT_READ_CMND_OPCD 0x03 /* Sequential Read */ +#define MV_ESMT_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ +#define MV_ESMT_PP_CMND_OPCD 0x02 /* Page Program */ +#define MV_ESMT_SE_CMND_OPCD 0x20 /* Sector Erase */ +#define MV_ESMT_BE_CMND_OPCD 0xC7 /* Bulk Erase */ +#define MV_ESMT_DP_CMND_OPCD 0xB9 /* Deep Power Down */ +#define MV_ESMT_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ + +#define MV_ESMT_MANF_ID 0x8C /*Manufacture ID */ +#define MV_ESMT_DEVICE_ID 0x3013 /*Winbond device ID */ + +#define MV_ESMT_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_ESMT_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_ESMT_FAST_READ_DUMMY_BYTES 1 + +#define MV_ESMT_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_ESMT_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_ESMT_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_ESMT_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_ESMT_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_ESMT_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_ESMT_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_ESMT_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_ESMT_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) + +/* Sector Sizes and population per device model*/ +/* #define MV_ESMT_SECTOR_SIZE 0x1000 /\* 4K *\/ */ +/* #define MV_ESMT_SECTOR_NUMBER 128 */ +#define MV_ESMT_SECTOR_SIZE 0x10000 /* 64K */ +#define MV_ESMT_SECTOR_NUMBER 8 +#define MV_ESMT_PAGE_SIZE 0x100 /*256 bytes*/ + +#endif // CONFIG_BUFFALO_PLATFORM + +/************************************/ +/* SPANSION S25FL128P Device Specific */ +/************************************/ + +/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ +#define MV_SPANSION_MANF_ID 0x01 +#define MV_S25FL128_DEVICE_ID 0x2018 +#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ +#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ +#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 + +/* Sector Sizes and population per device model*/ +#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ +#define MV_S25FL128_SECTOR_NUMBER 64 +#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ + +#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ +#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ +#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ +#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ +#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ +#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ +#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ +#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ +#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ +#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ +#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ +#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ + +/* Status Register Write Protect Bit Masks - 4bits */ +#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) + +#if defined(CONFIG_BUFFALO_PLATFORM) +/********************************/ +/* SST 25VFxxx Device Specific */ +/********************************/ +/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ +#define MV_25VFXXX_ST_MANF_ID 0xbf + +#define MV_25VF040_DEVICE_ID 0x258d +#define MV_25VF040_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_25VF040_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_25VF040_FAST_READ_DUMMY_BYTES 1 +/* Sector Sizes and population per device model*/ +#define MV_25VF040_SECTOR_SIZE 0x1000 /* 4K */ + +#define MV_25VF040_SECTOR_NUMBER 128 + +#define MV_25VF_PAGE_SIZE 0x1 /* 1 byte */ + +#define MV_25VF_WREN_CMND_OPCD 0x06 /* Write Enable */ +#define MV_25VF_WRDI_CMND_OPCD 0x04 /* Write Disable */ +#define MV_25VF_RDID_CMND_OPCD 0x90 /* Read ID */ +#define MV_25VF_RDSR_CMND_OPCD 0x05 /* Read Status Register */ +#define MV_25VF_WRSR_CMND_OPCD 0x01 /* Write Status Register */ +#define MV_25VF_READ_CMND_OPCD 0x03 /* Sequential Read */ +#define MV_25VF_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ +#define MV_25VF_PP_CMND_OPCD 0x02 /* Page Program */ +#define MV_25VF_SE_CMND_OPCD 0x20 /* Sector Erase */ +#define MV_25VF_BE_CMND_OPCD 0xC7 /* Bulk Erase */ +#define MV_25VF_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ + +/* Status Register Write Protect Bit Masks - 3bits */ +#define MV_25VF_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_25VF_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_25VF_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_25VF_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_25VF_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_25VF_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_25VF_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_25VF_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_25VF_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) + +#endif /* CONFIG_BUFFALO_PLATFORM */ + +#endif /* __INCmvSFlashSpecH */ + diff --git a/board/mv_feroceon/mv_hal/spi/mvCompVer.txt b/board/mv_feroceon/mv_hal/spi/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/spi/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/spi/mvSpi.c b/board/mv_feroceon/mv_hal/spi/mvSpi.c new file mode 100644 index 0000000..ed33265 --- /dev/null +++ b/board/mv_feroceon/mv_hal/spi/mvSpi.c @@ -0,0 +1,579 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "spi/mvSpi.h" +#include "spi/mvSpiSpec.h" + +#include "ctrlEnv/mvCtrlEnvLib.h" + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#define mvOsPrintf printf +#else +#define DB(x) +#endif + + +/******************************************************************************* +* mvSpi16bitDataTxRx - Transmt and receive data +* +* DESCRIPTION: +* Tx data and block waiting for data to be transmitted +* +********************************************************************************/ +static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) +{ + MV_U32 i; + MV_BOOL ready = MV_FALSE; + + /* First clear the bit in the interrupt cause register */ + MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); + + /* Transmit data */ + MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); + + /* wait with timeout for memory ready */ + for (i=0; i> 8) & 0xFF); + +#elif defined(MV_CPU_BE) + + /* perform the data write to the buffer in two stages with 8bit each */ + MV_U8 * bptr = (MV_U8 *)pRxData; + MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); + *bptr = ((data >> 8) & 0xFF); + ++bptr; + *bptr = (data & 0xFF); + +#else + #error "CPU endianess isn't defined!\n" +#endif + + } + else + *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvSpi8bitDataTxRx - Transmt and receive data (8bits) +* +* DESCRIPTION: +* Tx data and block waiting for data to be transmitted +* +********************************************************************************/ +static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) +{ + MV_U32 i; + MV_BOOL ready = MV_FALSE; + + /* First clear the bit in the interrupt cause register */ + MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); + + /* Transmit data */ + MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); + + /* wait with timeout for memory ready */ + for (i=0; i serialBaudRate) + continue; + + /* check for exact fit */ + if ((cpuClk / preScale[i]) == serialBaudRate) + { + bestPrescaleIndx = i; + break; + } + + /* check if this is better than the previous one */ + if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) + { + minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); + bestPrescaleIndx = i; + } + } + + if (bestPrescaleIndx > 14) + { + mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); + return MV_OUT_OF_RANGE; + } + + /* configure the Prescale */ + tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); + tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); + MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); + + return MV_OK; +} + +/******************************************************************************* +* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer +* +* DESCRIPTION: +* Assert The chip select - used to select an external SPI device +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_VOID mvSpiCsAssert(MV_VOID) +{ + /* For devices in which the SPI is muxed on the MPP with other interfaces*/ + mvMPPConfigToSPI(); + mvOsUDelay(1); + MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); +} + +/******************************************************************************* +* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a +* SPI transfer sequence +* +* DESCRIPTION: +* DeAssert the chip select pin +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_VOID mvSpiCsDeassert(MV_VOID) +{ + MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); + + /* For devices in which the SPI is muxed on the MPP with other interfaces*/ + mvMPPConfigToDefault(); +} + +/******************************************************************************* +* mvSpiRead - Read a buffer over the SPI interface +* +* DESCRIPTION: +* Receive (read) a buffer over the SPI interface in 16bit chunks. If the +* buffer size is odd, then the last chunk will be 8bits. Chip select is not +* handled at this level. +* +* INPUT: +* pRxBuff: Pointer to the buffer to hold the received data +* buffSize: length of the pRxBuff +* +* OUTPUT: +* pRxBuff: Pointer to the buffer with the received data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + MV_U32 bytesLeft = buffSize; + MV_U16* rxPtr = (MV_U16*)pRxBuff; + + /* check for null parameters */ + if (pRxBuff == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Check that the buffer pointer and the buffer size are 16bit aligned */ + if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) + { + /* Verify that the SPI mode is in 16bit mode */ + MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX as long we have complete 16bit chunks */ + while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) + { + /* Transmitted and wait for the transfer to be completed */ + if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) + return ret; + + /* increment the pointers */ + rxPtr++; + bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; + } + + } + else + { + /* Verify that the SPI mode is in 8bit mode */ + MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX in 8bit chanks */ + while (bytesLeft > 0) + { + /* Transmitted and wait for the transfer to be completed */ + if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) + return ret; + /* increment the pointers */ + pRxBuff++; + bytesLeft--; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvSpiWrite - Transmit a buffer over the SPI interface +* +* DESCRIPTION: +* Transmit a buffer over the SPI interface in 16bit chunks. If the +* buffer size is odd, then the last chunk will be 8bits. No chip select +* action is taken. +* +* INPUT: +* pTxBuff: Pointer to the buffer holding the TX data +* buffSize: length of the pTxBuff +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + MV_U32 bytesLeft = buffSize; + MV_U16* txPtr = (MV_U16*)pTxBuff; + + /* check for null parameters */ + if (pTxBuff == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Check that the buffer pointer and the buffer size are 16bit aligned */ + if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) + { + /* Verify that the SPI mode is in 16bit mode */ + MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX as long we have complete 16bit chunks */ + while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) + { + /* Transmitted and wait for the transfer to be completed */ + if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) + return ret; + + /* increment the pointers */ + txPtr++; + bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; + } + } + else + { + + /* Verify that the SPI mode is in 8bit mode */ + MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX in 8bit chanks */ + while (bytesLeft > 0) + { + /* Transmitted and wait for the transfer to be completed */ + if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) + return ret; + + /* increment the pointers */ + pTxBuff++; + bytesLeft--; + } + } + + return MV_OK; +} + + +/******************************************************************************* +* mvSpiReadWrite - Read and Write a buffer simultanuosely +* +* DESCRIPTION: +* Transmit and receive a buffer over the SPI in 16bit chunks. If the +* buffer size is odd, then the last chunk will be 8bits. The SPI chip +* select is not handled implicitely. +* +* INPUT: +* pRxBuff: Pointer to the buffer to write the RX info in +* pTxBuff: Pointer to the buffer holding the TX info +* buffSize: length of both the pTxBuff and pRxBuff +* +* OUTPUT: +* pRxBuff: Pointer of the buffer holding the RX data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + MV_U32 bytesLeft = buffSize; + MV_U16* txPtr = (MV_U16*)pTxBuff; + MV_U16* rxPtr = (MV_U16*)pRxBuff; + + /* check for null parameters */ + if ((pRxBuff == NULL) || (pTxBuff == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Check that the buffer pointer and the buffer size are 16bit aligned */ + if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) + { + /* Verify that the SPI mode is in 16bit mode */ + MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX as long we have complete 16bit chunks */ + while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) + { + /* Transmitted and wait for the transfer to be completed */ + if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) + return ret; + + /* increment the pointers */ + txPtr++; + rxPtr++; + bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; + } + } + else + { + /* Verify that the SPI mode is in 8bit mode */ + MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX in 8bit chanks */ + while (bytesLeft > 0) + { + /* Transmitted and wait for the transfer to be completed */ + if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) + return ret; + pRxBuff++; + pTxBuff++; + bytesLeft--; + } + } + + return MV_OK; +} + + diff --git a/board/mv_feroceon/mv_hal/spi/mvSpi.h b/board/mv_feroceon/mv_hal/spi/mvSpi.h new file mode 100644 index 0000000..74859f0 --- /dev/null +++ b/board/mv_feroceon/mv_hal/spi/mvSpi.h @@ -0,0 +1,94 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSpihH +#define __INCmvSpihH + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* Function Prototypes */ +/* Init */ +MV_STATUS mvSpiInit (MV_U32 serialBaudRate); + +/* Set the Frequency of the Spi clock */ +MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); + +/* Assert the SPI chip select */ +MV_VOID mvSpiCsAssert (MV_VOID); + +/* De-assert the SPI chip select */ +MV_VOID mvSpiCsDeassert (MV_VOID); + +/* Simultanuous Read and write */ +MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); + +/* serialize a buffer on the TX line - Rx is ignored */ +MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); + +/* read from the RX line by writing dummy values to the TX line */ +MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); + +#endif /* __INCmvSpihH */ diff --git a/board/mv_feroceon/mv_hal/spi/mvSpiCmnd.c b/board/mv_feroceon/mv_hal/spi/mvSpiCmnd.c new file mode 100644 index 0000000..a5d5a64 --- /dev/null +++ b/board/mv_feroceon/mv_hal/spi/mvSpiCmnd.c @@ -0,0 +1,249 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "spi/mvSpi.h" +#include "spi/mvSpiSpec.h" + +/*#define MV_DEBUG*/ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + + +/******************************************************************************* +* mvSpiReadAndWrite - Read and Write a buffer simultanuousely +* +* DESCRIPTION: +* Transmit and receive a buffer over the SPI in 16bit chunks. If the +* buffer size is odd, then the last chunk will be 8bits. +* +* INPUT: +* pRxBuff: Pointer to the buffer to write the RX info in +* pTxBuff: Pointer to the buffer holding the TX info +* buffSize: length of both the pTxBuff and pRxBuff +* +* OUTPUT: +* pRxBuff: Pointer of the buffer holding the RX data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + + /* check for null parameters */ + if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* First assert the chip select */ + mvSpiCsAssert(); + + ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); + + /* Finally deassert the chip select */ + mvSpiCsDeassert(); + + return ret; +} + +/******************************************************************************* +* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line +* +* DESCRIPTION: +* Assert the chip select line. Transmit the command buffer followed by +* the data buffer. Then deassert the CS line. +* +* INPUT: +* pCmndBuff: Pointer to the command buffer to transmit +* cmndSize: length of the command size +* pTxDataBuff: Pointer to the data buffer to transmit +* txDataSize: length of the data buffer +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, + MV_U32 txDataSize) +{ + MV_STATUS ret = MV_OK, tempRet; + + /* check for null parameters */ +#ifndef CONFIG_MARVELL + if(NULL == pTxDataBuff) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } +#endif + + if (pCmndBuff == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* First assert the chip select */ + mvSpiCsAssert(); + + /* first write the command */ + if ((cmndSize) && (pCmndBuff != NULL)) + { + if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) + ret = tempRet; + } + + /* Then write the data buffer */ +#ifndef CONFIG_MARVELL + if (txDataSize) +#else + if ((txDataSize) && (pTxDataBuff != NULL)) +#endif + { + if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) + ret = tempRet; + } + + /* Finally deassert the chip select */ + mvSpiCsDeassert(); + + return ret; +} + +/******************************************************************************* +* mvSpiWriteThenRead - Serialize a command then read a data buffer +* +* DESCRIPTION: +* Assert the chip select line. Transmit the command buffer then read +* the data buffer. Then deassert the CS line. +* +* INPUT: +* pCmndBuff: Pointer to the command buffer to transmit +* cmndSize: length of the command size +* pRxDataBuff: Pointer to the buffer to read the data in +* txDataSize: length of the data buffer +* +* OUTPUT: +* pRxDataBuff: Pointer to the buffer holding the data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, + MV_U32 rxDataSize,MV_U32 dummyBytesToRead) +{ + MV_STATUS ret = MV_OK, tempRet; + MV_U8 dummyByte; + + /* check for null parameters */ + if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* First assert the chip select */ + mvSpiCsAssert(); + + /* first write the command */ + if ((cmndSize) && (pCmndBuff != NULL)) + { + if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) + ret = tempRet; + } + + /* Read dummy bytes before real data. */ + while(dummyBytesToRead) + { + mvSpiRead(&dummyByte,1); + dummyBytesToRead--; + } + + /* Then write the data buffer */ + if ((rxDataSize) && (pRxDataBuff != NULL)) + { + if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) + ret = tempRet; + } + + /* Finally deassert the chip select */ + mvSpiCsDeassert(); + + return ret; +} + diff --git a/board/mv_feroceon/mv_hal/spi/mvSpiCmnd.h b/board/mv_feroceon/mv_hal/spi/mvSpiCmnd.h new file mode 100644 index 0000000..329e26b --- /dev/null +++ b/board/mv_feroceon/mv_hal/spi/mvSpiCmnd.h @@ -0,0 +1,82 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSpiCmndhH +#define __INCmvSpiCmndhH + +#include "mvTypes.h" + +/* Function Prototypes */ + +/* Simultanuous Read and write */ +MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); + +/* write command - write a command and then write data */ +MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); + +/* read command - write a command and then read data by writing dummy data */ +MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, + MV_U32 rxDataSize,MV_U32 dummyBytesToRead); + +#endif /* __INCmvSpiCmndhH */ diff --git a/board/mv_feroceon/mv_hal/spi/mvSpiSpec.h b/board/mv_feroceon/mv_hal/spi/mvSpiSpec.h new file mode 100644 index 0000000..658159a --- /dev/null +++ b/board/mv_feroceon/mv_hal/spi/mvSpiSpec.h @@ -0,0 +1,98 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSpiSpecH +#define __INCmvSpiSpecH + +/* Constants */ +#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 +#define MV_SPI_16_BIT_CHUNK_SIZE 2 +#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF +#define MV_SPI_DUMMY_WRITE_8BITS 0xFF + +/* Marvell Flash Device Controller Registers */ +#define MV_SPI_CTRLR_OFST 0x10600 +#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) +#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) +#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) +#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) +#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) +#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) + +/* Serial Memory Interface Control Register Masks */ +#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ +#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ +#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) +#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) + +/* Serial Memory Interface Configuration Register Masks */ +#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ +#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ +#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ +#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) +#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) +#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) + +#endif /* __INCmvSpiSpecH */ + diff --git a/board/mv_feroceon/mv_hal/ts/mvCompVer.txt b/board/mv_feroceon/mv_hal/ts/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ts/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/ts/mvTsu.c b/board/mv_feroceon/mv_hal/ts/mvTsu.c new file mode 100644 index 0000000..4cfbbea --- /dev/null +++ b/board/mv_feroceon/mv_hal/ts/mvTsu.c @@ -0,0 +1,1729 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvTsu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +/********************************/ +/* Local enums and structures */ +/********************************/ +#define TSU_MIN_PKT_SIZE 188 +#define TSU_MAX_PKT_SIZE 256 +#define TSU_NUM_CLOCK_DIVIDERS 6 + +typedef struct +{ + MV_U32 aggrMode; + MV_U16 pktSize; + MV_TSU_PORT_DIRECTION portDir; + MV_ULONG descPhyAddr; + MV_U32 *descVirtAddr; + MV_U32 descMemHandle; + MV_U32 numTsDesc; + MV_U32 numDoneQEntry; + MV_U32 aggrNumPckts; + MV_U32 *tsDataBuff; + MV_U32 *tsDoneBuff; + MV_U32 dataBlockSize; + MV_U32 dataReadIdx; + MV_U32 statReadIdx; + MV_U32 cpuRollBit; + MV_U32 descSize; + MV_U32 queueMask; + MV_U32 queueDescSize; + MV_BOOL enableTimer; +}MV_TSU_PORT_CTRL; + +typedef struct +{ + MV_U32 numActPorts; + MV_TSU_PORTS_MODE mode; + MV_TSU_CORE_CLOCK coreClock; + void *osHandle; +}MV_TSU_CTRL; + +/********************************/ +/* Local Macros */ +/********************************/ +#define TS_SIGNAL_PARAMS_CONFIG(cfg,usedMask,polMask,reg) \ + { \ + if(cfg != TSU_SIGNAL_KEEP_DEF) \ + { \ + reg &= ~(usedMask | polMask); \ + if(cfg != TSU_SIGNAL_DIS) \ + { \ + reg |= usedMask; \ + if(cfg == TSU_SIGNAL_EN_ACT_HIGH) \ + reg |= polMask; \ + } \ + } \ + } + +#define TS_SIGNAL_PARAMS_GET(cfg,usedMask,polMask,reg) \ + { \ + if(reg & usedMask) \ + { \ + if(reg & polMask) \ + cfg = TSU_SIGNAL_EN_ACT_HIGH; \ + else \ + cfg = TSU_SIGNAL_EN_ACT_LOW; \ + } \ + else \ + { \ + cfg = TSU_SIGNAL_DIS; \ + } \ + } + + + +#define TSU_SET_DESC_BUFF_PTR(desc,addr) (*(MV_U32*)desc) = addr +#define TSU_SET_OUT_DESC_TMSTMP(desc,tms,err) \ + (*((MV_U32*)desc + 1)) = (tms | (err << 28)) + +#define TSU_BUFF_HNDL(d, s) (MV_U32) ((d & 0xFFFF) | ((s & 0xFFFF) << 16)) +#define TSU_BUFF_HNDL_2_DATA_IDX(h) (MV_U32)(h & 0xFFFF) +#define TSU_BUFF_HNDL_2_STAT_IDX(h) (MV_U32)((h >> 16) & 0xFFFF) + +/********************************/ +/* Control variables. */ +/********************************/ +MV_U32 mvTsuCoreClock2Val[] = { + 83 * _1M, /* TSU_CORE_CLK_83_MHZ */ + 71 * _1M, /* TSU_CORE_CLK_71_MHZ */ + 91 * _1M, /* TSU_CORE_CLK_91_MHZ */ + 100 * _1M /* TSU_CORE_CLK_100_MHZ */ +}; +MV_TSU_CTRL mvTsuCtrl; +MV_TSU_PORT_CTRL mvTsuPortCtrl[MV_TSU_NUM_PORTS]; + + +/********************************/ +/* Forward functions declaration*/ +/********************************/ +inline static MV_STATUS mvTsuOperationModeSet(MV_U8 port, MV_BOOL enable); +static MV_STATUS mvTsuReadyBuffCountGet(MV_U8 port, MV_U32 *numBlocks, + MV_U32 *numBuffers); +static MV_STATUS mvTsuPortEnable(MV_U8 port,MV_BOOL enable); + +/********************************/ +/* Functions Implementation */ +/********************************/ + + +/******************************************************************************* +* mvTsuHalInit +* +* DESCRIPTION: +* Initialize the TSU unit, and get unit out of reset. +* +* INPUT: +* coreClock - The core clock at which the TSU should operate. +* mode - The mode on configure the unit into (serial/parallel). +* osHandle - Memory handle used for memory allocations. +* OUTPUT: +* None. +* RETURN: +* MV_OK - on success, +* +*******************************************************************************/ +MV_STATUS mvTsuHalInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, + void *osHandle) +{ + MV_U32 reg; + MV_U32 port; + + /* Setup the core clock. */ + reg = MV_REG_READ(MV_TSU_MODES_REG); + reg &= TSU_MODES_TSCK_MASK; + reg |= (coreClock << TSU_MODES_TSCK_OFF); + + /* Configure the mode */ + reg &= ~TSU_MODES_PAR_MODE_MASK; + if(mode == TSU_MODE_SERIAL) { + reg |= TSU_MODES_PAR_MODE_SER; + mvTsuCtrl.numActPorts = 2; + } else { + reg |= TSU_MODES_PAR_MODE_PAR; + mvTsuCtrl.numActPorts = 1; + } + MV_REG_WRITE(MV_TSU_MODES_REG,reg); + + /* Get ports out of reset. */ + for(port = 0; port < MV_TSU_NUM_PORTS; port++) + mvTsuPortReset(port); + + /* Setup control veraibles. */ + mvTsuCtrl.coreClock = coreClock; + mvTsuCtrl.osHandle = osHandle; + mvTsuCtrl.mode = mode; + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuShutdown +* +* DESCRIPTION: +* Shutdown the TS unit, and put into reset state. +* +* INPUT: +* None. +* OUTPUT: +* None. +* RETURN: +* MV_OK - on success, +* +*******************************************************************************/ +MV_STATUS mvTsuShutdown(void) +{ + //... + // Check if it's possible to put the module back into reset mode. + return MV_NOT_IMPLEMENTED; +} + + +/******************************************************************************* +* mvTsuPortReset +* +* DESCRIPTION: +* Perform a SW reset on a given port. +* +* INPUT: +* port - The port number to reset. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_BAD_VALUE - Bad port configuration option. +* MV_BAD_SIZE - Illegal number of ports. +* +*******************************************************************************/ +MV_STATUS mvTsuPortReset(MV_U8 port) +{ + MV_U32 reg; + + /* Check the correctness of parameters. */ + if(port >= MV_TSU_NUM_PORTS) + return MV_BAD_SIZE; + + /* First, set in reset mode, then get out of reset. */ + reg = MV_REG_READ(MV_TSU_CONFIG_REG(port)); + reg &= ~TSU_CFG_RESET_MASK; + reg |= TSU_CFG_RESET_SET; + MV_REG_WRITE(MV_TSU_CONFIG_REG(port),reg); + reg &= ~TSU_CFG_RESET_MASK; + reg |= TSU_CFG_RESET_CLEAR; + MV_REG_WRITE(MV_TSU_CONFIG_REG(port),reg); + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuPortInit +* +* DESCRIPTION: +* Initialize the TSU ports. +* +* INPUT: +* port - The port number to configure. +* portCfg - Port configurations parameters. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_BAD_VALUE - Bad port configuration option. +* MV_BAD_SIZE - Illegal number of ports. +* +*******************************************************************************/ +MV_STATUS mvTsuPortInit(MV_U8 port, MV_TSU_PORT_CONFIG *portCfg) +{ + MV_U32 reg; + + /* Check the correctness of parameters. */ + if(((mvTsuCtrl.mode == TSU_MODE_SERIAL) && (port >= MV_TSU_NUM_PORTS))|| + ((mvTsuCtrl.mode == TSU_MODE_PARALLEL) && (port >= 1))) + return MV_BAD_SIZE; + + if((portCfg->pktSize < TSU_MIN_PKT_SIZE) || + (portCfg->pktSize > TSU_MAX_PKT_SIZE)) + return MV_BAD_VALUE; + + /* configure the port parameters */ + /* Disable operation mode. */ + mvTsuOperationModeSet(port,MV_FALSE); + + reg = MV_REG_READ(MV_TSU_CONFIG_REG(port)); + + /* Setup packet size. */ + reg &= ~TSU_CFG_PKT_SIZE_MASK; + reg |= (((portCfg->pktSize - 1) & 0xFF) << TSU_CFG_PKT_SIZE_OFFS); + + /* Setup data direction. */ + reg &= ~TSU_CFG_DATA_DIR_MASK; + if(portCfg->portDir == TSU_PORT_INPUT) + reg |= TSU_CFG_DATA_DIR_IN; + else + reg |= TSU_CFG_DATA_DIR_OUT; + + /* Setup serial / parallel mode. */ + reg &= ~TSU_CFG_DATA_MODE_MASK; + if(mvTsuCtrl.mode == TSU_MODE_SERIAL) + reg |= TSU_CFG_DATA_MODE_SER; + else + reg |= TSU_CFG_DATA_MODE_PAR; + + MV_REG_WRITE(MV_TSU_CONFIG_REG(port),reg); + + /* Setup DMA packet size. */ + reg = MV_REG_READ(MV_TSU_DMA_PARAMS_REG(port)); + reg &= ~TSU_DMAP_DMA_LEN_MASK; + reg |= portCfg->pktSize; + MV_REG_WRITE(MV_TSU_DMA_PARAMS_REG(port),reg); + + /* Setup timestamp auto adjust. */ + if(portCfg->portDir == TSU_PORT_OUTPUT) + { + reg = MV_REG_READ(MV_TSU_TIMESTAMP_CTRL_REG(port)); + reg &= ~TSU_TMS_CTRL_AUTO_ADJ_MASK; + reg |= TSU_TMS_CTRL_AUTO_ADJ_ON; + MV_REG_WRITE(MV_TSU_TIMESTAMP_CTRL_REG(port),reg); + } + + /* Enable operation mode. */ + mvTsuOperationModeSet(port,MV_TRUE); + + /* Update global control vars. */ + mvTsuPortCtrl[port].pktSize = portCfg->pktSize; + mvTsuPortCtrl[port].portDir = portCfg->portDir; + + MV_REG_BIT_SET(MV_TSU_CONFIG_REG(port),(1 << 17)); + return MV_OK; +} + + +/******************************************************************************* +* mvTsuPortSignalCfgSet +* +* DESCRIPTION: +* Configure port signals parameters. +* +* INPUT: +* port - The port to configure. +* signalCfg - Signal configuration options. +* serialflags - Serial signal configuration options (valid only if the +* port is working in serial mode). +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_BAD_VALUE - Bad port configuration option. +* MV_BAD_SIZE - Illegal number of ports. +* +*******************************************************************************/ +MV_STATUS mvTsuPortSignalCfgSet(MV_U8 port, MV_TSU_SIGNAL_CONFIG *signalCfg, + MV_U32 serialFlags) +{ + MV_U32 reg; + + if(port >= MV_TSU_NUM_PORTS) + return MV_OUT_OF_RANGE; + + /* Disable operation mode. */ + mvTsuOperationModeSet(port,MV_FALSE); + + reg = MV_REG_READ(MV_TSU_CONFIG_REG(port)); + + /* Setup signal related options. */ + TS_SIGNAL_PARAMS_CONFIG(signalCfg->tsSync, + TSU_CFG_SYNC_USED_MASK, + TSU_CFG_SYNC_POL_MASK,reg); + TS_SIGNAL_PARAMS_CONFIG(signalCfg->tsValid, + TSU_CFG_VAL_USED_MASK, + TSU_CFG_VAL_POL_MASK,reg); + TS_SIGNAL_PARAMS_CONFIG(signalCfg->tsError, + TSU_CFG_ERR_USED_MASK, + TSU_CFG_ERR_POL_MASK,reg); + + if(signalCfg->tsDataEdge != TSU_SIGNAL_EDGE_KEEP_DEF) + { + if(signalCfg->tsDataEdge == TSU_SIGNAL_EDGE_FALL) + reg |= TSU_CFG_TX_EDGE_MASK; + else + reg &= ~TSU_CFG_TX_EDGE_MASK; + } + + /* Setup serial mode related configurations. */ + if(mvTsuCtrl.mode == TSU_MODE_SERIAL) + { + if(serialFlags & MV_TSU_SER_DATA_ORDER_MASK) + { + reg &= ~TSU_CFG_DATA_ORD_MASK; + if(serialFlags & MV_TSU_SER_DATA_ORDER_MSB) + reg |= TSU_CFG_DATA_ORD_MSB; + else if(serialFlags & MV_TSU_SER_DATA_ORDER_LSB) + reg |= TSU_CFG_DATA_ORD_LSB; + } + + if(serialFlags & MV_TSU_SER_SYNC_ACT_LEN_MASK) + { + reg &= ~TSU_CFG_TS_SYNC_MASK; + if(serialFlags & MV_TSU_SER_SYNC_ACT_1_BIT) + reg |= TSU_CFG_TS_SYNC_1BIT; + else if(serialFlags & MV_TSU_SER_SYNC_ACT_8_BIT) + reg |= TSU_CFG_TS_SYNC_8BIT; + } + + if(serialFlags & MV_TSU_SER_TX_CLK_MODE_MASK) + { + reg &= ~TSU_CFG_CLK_MODE_MASK; + if(serialFlags & MV_TSU_SER_TX_CLK_MODE_GAPPED) + reg |= TSU_CFG_CLK_MODE_GAPPED; + else if(serialFlags & MV_TSU_SER_TX_CLK_MODE_CONT) + reg |= TSU_CFG_CLK_MODE_CONT; + } + } + + MV_REG_WRITE(MV_TSU_CONFIG_REG(port),reg); + + /* Enable operation mode. */ + mvTsuOperationModeSet(port,MV_TRUE); + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuPortSignalCfgGet +* +* DESCRIPTION: +* Get port signals parameters. +* +* INPUT: +* port - The port to configure. +* OUTPUT: +* signalCfg - Signal configuration options. +* serialflags - Serial signal configuration options (valid only if the +* port is working in serial mode). +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Illegal port number. +* MV_BAD_PARAM - Bad pointers. +* +*******************************************************************************/ +MV_STATUS mvTsuPortSignalCfgGet(MV_U8 port, MV_TSU_SIGNAL_CONFIG *signalCfg, + MV_U32* serialFlags) +{ + MV_U32 reg; + + if(port >= MV_TSU_NUM_PORTS) + return MV_OUT_OF_RANGE; + + if((signalCfg == NULL) || + ( (mvTsuCtrl.mode == TSU_MODE_SERIAL) && (serialFlags == NULL))) + return MV_BAD_PARAM; + + reg = MV_REG_READ(MV_TSU_CONFIG_REG(port)); + + /* Setup signal related options. */ + TS_SIGNAL_PARAMS_GET(signalCfg->tsSync,TSU_CFG_SYNC_USED_MASK, + TSU_CFG_SYNC_POL_MASK,reg); + TS_SIGNAL_PARAMS_GET(signalCfg->tsValid,TSU_CFG_VAL_USED_MASK, + TSU_CFG_VAL_POL_MASK,reg); + TS_SIGNAL_PARAMS_GET(signalCfg->tsError,TSU_CFG_ERR_USED_MASK, + TSU_CFG_ERR_POL_MASK,reg); + + if(reg & TSU_CFG_TX_EDGE_MASK) + signalCfg->tsDataEdge = TSU_SIGNAL_EDGE_FALL; + else + signalCfg->tsDataEdge = TSU_SIGNAL_EDGE_RISE; + + /* Setup serial mode related configurations. */ + if(mvTsuCtrl.mode == TSU_MODE_SERIAL) + { + *serialFlags = 0; + + if((reg & TSU_CFG_DATA_ORD_MASK) == TSU_CFG_DATA_ORD_LSB) + *serialFlags |= MV_TSU_SER_DATA_ORDER_LSB; + else + *serialFlags |= MV_TSU_SER_DATA_ORDER_MSB; + + if((reg & TSU_CFG_TS_SYNC_MASK) == TSU_CFG_TS_SYNC_1BIT) + *serialFlags |= MV_TSU_SER_SYNC_ACT_1_BIT; + else + *serialFlags |= MV_TSU_SER_SYNC_ACT_8_BIT; + + if((reg & TSU_CFG_CLK_MODE_MASK) == MV_TSU_SER_TX_CLK_MODE_GAPPED) + *serialFlags |= TSU_CFG_CLK_MODE_GAPPED; + else + *serialFlags |= TSU_CFG_CLK_MODE_CONT; + } + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuStatusGet +* +* DESCRIPTION: +* Get the TSU port status for a given port. +* +* INPUT: +* port - The port number to configure. +* OUTPUT: +* status - Bitmask representing the TSU port status (a bitwise or +* between the MV_TSU_STATUS_* macros. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* +*******************************************************************************/ +MV_STATUS mvTsuStatusGet(MV_U8 port, MV_U32 *status) +{ + MV_U32 reg; + + if(port >= mvTsuCtrl.numActPorts) + { + return MV_OUT_OF_RANGE; + } + + reg = MV_REG_READ(MV_TSU_STATUS_REG(port)); + reg &= TSU_STATUS_MASK; + + *status = 0; + if(reg & TSU_STATUS_IF_ERR) + *status |= MV_TSU_STATUS_TSIF_ERROR; + if(reg & TSU_STATUS_FIFO_OVFL_ERR) + *status |= MV_TSU_STATUS_OVFL_ERROR; + if(reg & TSU_STATUS_CONN_ERR) + *status |= MV_TSU_STATUS_CONN_ERROR; + return MV_OK; +} + + +/******************************************************************************* +* mvTsuBuffersInit +* +* DESCRIPTION: +* Initialize the TSU unit buffers. +* This function is used to initialize both Rx or Tx buffers according to +* the port mode configured in mvTsuPortsInit(). +* +* INPUT: +* port - The port number to configure. +* buffInfo- TSU buffer information. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad buffer configuration options. +* MV_NOT_ALIGNED - Bad data buffer alignemed. +* +*******************************************************************************/ +MV_STATUS mvTsuBuffersInit(MV_U8 port, MV_TSU_BUFF_INFO *buffInfo) +{ + MV_U32 reg; + MV_U32 descSize; + MV_U32 i; + MV_U8 *tsDataBuff; + MV_U32 *descEntry; + MV_U32 phyAddr; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + + if( ( (buffInfo->aggrMode != MV_TSU_AGGR_MODE_DISABLED) && + ( (buffInfo->aggrMode2TmstmpOff > 0xF ) || + (buffInfo->aggrMode2TmstmpOff < 4 ) || + (buffInfo->aggrNumPackets <= 1) || + (buffInfo->numDoneQEntry < buffInfo->aggrNumPackets) ) ) || + (!MV_IS_POWER_OF_2(buffInfo->numTsDesc) ) || + (!MV_IS_POWER_OF_2(buffInfo->numDoneQEntry) ) || + (buffInfo->numTsDesc == 0) || + (buffInfo->numDoneQEntry == 0) || + (buffInfo->numDoneQEntry > MV_TSU_MAX_DONEQ_LEN) || + ( (mvTsuPortCtrl[port].portDir == TSU_PORT_INPUT) && + (buffInfo->numTsDesc > MV_TSU_MAX_IN_QUEUE_LEN) ) || + ( (mvTsuPortCtrl[port].portDir == TSU_PORT_OUTPUT) && + (buffInfo->numTsDesc > MV_TSU_MAX_OUT_QUEUE_LEN) ) ) + { + return MV_BAD_PARAM; + } + + /* Check buffer alignment. */ + if( ( (buffInfo->aggrMode == MV_TSU_AGGR_MODE_2) && + (((buffInfo->tsDataBuffPhys + buffInfo->aggrMode2TmstmpOff) & + (TSU_DMA_ALIGN - 1)) != 0) ) || + ( (buffInfo->aggrMode == MV_TSU_AGGR_MODE_DISABLED) && + (buffInfo->tsDataBuffPhys & (TSU_DMA_ALIGN - 1)) != 0 ) ) + { + return MV_NOT_ALIGNED; + } + + /* Disable operation mode. */ + mvTsuOperationModeSet(port,MV_FALSE); + + /* Setup aggregation mode. */ + reg = MV_REG_READ(MV_TSU_AGGREGATION_CTRL_REG(port)); + reg &= ~TSU_AGGR_ENABLE_MASK; + if(buffInfo->aggrMode == MV_TSU_AGGR_MODE_DISABLED) + { + reg |= TSU_AGGR_DISABLE; + mvTsuPortCtrl[port].aggrNumPckts = 1; + } + else + { + reg |= TSU_AGGR_ENABLE; + + reg &= ~TSU_AGGR_TMSTMP_OFF_MASK; + if(buffInfo->aggrMode == MV_TSU_AGGR_MODE_2) + { + reg |= (buffInfo->aggrMode2TmstmpOff << + TSU_AGGR_TMSTMP_OFF_OFFS); + reg &= ~TSU_AGGR_TMSTMP_MODE_MASK; + reg |= TSU_AGGR_TMSTMP_TO_PCKT; + } + + reg &= ~TSU_AGGR_PCKT_NUM_MASK; + reg |= (buffInfo->aggrNumPackets << TSU_AGGR_PCKT_NUM_OFFS); + + MV_REG_WRITE(MV_TSU_AGGREGATION_CTRL_REG(port),reg); + mvTsuPortCtrl[port].aggrNumPckts = buffInfo->aggrNumPackets; + } + + mvTsuPortCtrl[port].aggrMode = buffInfo->aggrMode; + if(mvTsuPortCtrl[port].portDir == TSU_PORT_INPUT) { + descSize = TSU_INPUT_DESC_ENTRY_SIZE; + mvTsuPortCtrl[port].queueDescSize = 4; + } else { + descSize = TSU_OUTPUT_DESC_ENTRY_SIZE(buffInfo->aggrMode); + mvTsuPortCtrl[port].queueDescSize = 8; + } + + /* Initialize descriptor data. */ + mvTsuPortCtrl[port].descVirtAddr = mvOsIoUncachedMalloc( + mvTsuCtrl.osHandle,descSize * buffInfo->numTsDesc, + &(mvTsuPortCtrl[port].descPhyAddr), + &(mvTsuPortCtrl[port].descMemHandle)); + + /* Initialize the descriptors list with buffer pointers. */ + descEntry = (MV_U32*)mvTsuPortCtrl[port].descVirtAddr; + tsDataBuff = (MV_U8*)buffInfo->tsDataBuff; + phyAddr = buffInfo->tsDataBuffPhys; + for(i = 0; i < buffInfo->numTsDesc; i++) + { + TSU_SET_DESC_BUFF_PTR(descEntry,phyAddr); + descEntry += (descSize >> 2); + tsDataBuff += buffInfo->dataBlockSize; + phyAddr += buffInfo->dataBlockSize; + } + + mvTsuPortCtrl[port].queueMask = + ~(0xFFFFFFFF << mvLog2(buffInfo->numTsDesc * descSize)); + + if(mvTsuPortCtrl[port].portDir == TSU_PORT_INPUT) + mvTsuPortCtrl[port].cpuRollBit = + mvTsuPortCtrl[port].queueMask + 1; + else + mvTsuPortCtrl[port].cpuRollBit = 0; + + /* Write the read / write pointers for data & status buffers. */ + + /* Desc start pointer. */ + phyAddr = mvTsuPortCtrl[port].descPhyAddr; + MV_REG_WRITE(MV_TSU_DESC_QUEUE_BASE_REG(port),phyAddr); + + /* Desc read pointer. */ + MV_REG_WRITE(MV_TSU_DESC_QUEUE_READ_PTR_REG(port), + 0 << TSU_DESC_READ_PTR_OFFS); + + /* Desc write pointer. */ + MV_REG_WRITE(MV_TSU_DESC_QUEUE_WRITE_PTR_REG(port), + mvTsuPortCtrl[port].cpuRollBit); + + /* Done start pointer. */ + phyAddr = buffInfo->tsDoneBuffPhys; + MV_REG_WRITE(MV_TSU_DONE_QUEUE_BASE_REG(port),phyAddr); + + /* Done read pointer. */ + MV_REG_WRITE(MV_TSU_DONE_QUEUE_READ_PTR_REG(port), + 0 << TSU_DONE_READ_PTR_OFFS); + + /* Done write pointer. */ + MV_REG_WRITE(MV_TSU_DONE_QUEUE_WRITE_PTR_REG(port), + mvTsuPortCtrl[port].cpuRollBit);//0 << TSU_DONE_WRITE_PTR_OFFS); + + /* Done & Data queues size. */ + reg = MV_REG_READ(MV_TSU_DMA_PARAMS_REG(port)); + reg &= ~(TSU_DMAP_DESC_Q_SIZE_MASK | TSU_DMAP_DONE_Q_SIZE_MASK); + + i = mvLog2((buffInfo->numTsDesc * descSize) >> 2); + reg |= (i << TSU_DMAP_DESC_Q_SIZE_OFFS); + + i = mvLog2((buffInfo->numDoneQEntry * TSU_DONE_STATUS_ENTRY_SIZE) >> 2); + reg |= (i << TSU_DMAP_DONE_Q_SIZE_OFFS); + + MV_REG_WRITE(MV_TSU_DMA_PARAMS_REG(port),reg); + + mvTsuPortCtrl[port].descSize = descSize; + mvTsuPortCtrl[port].numTsDesc = buffInfo->numTsDesc; + mvTsuPortCtrl[port].numDoneQEntry = buffInfo->numDoneQEntry; + mvTsuPortCtrl[port].tsDataBuff = buffInfo->tsDataBuff; + mvTsuPortCtrl[port].tsDoneBuff = buffInfo->tsDoneBuff; + mvTsuPortCtrl[port].dataBlockSize = buffInfo->dataBlockSize; + mvTsuPortCtrl[port].dataReadIdx = 0; + mvTsuPortCtrl[port].statReadIdx = 0; + mvTsuPortCtrl[port].enableTimer = MV_FALSE; + + mvTsuPortEnable(port,MV_TRUE); + + /* Enable operation mode. */ + mvTsuOperationModeSet(port,MV_TRUE); + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuPortShutdown +* +* DESCRIPTION: +* Shutdown the port, this will release any previously allocated port +* memory, and set the port to disable state. +* +* INPUT: +* port - The port number to shutdown. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad buffer configuration options. +* +*******************************************************************************/ +MV_STATUS mvTsuPortShutdown(MV_U8 port) +{ + MV_TSU_PORT_CTRL *portCtrl; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + + /* Disable operation mode. */ + mvTsuOperationModeSet(port,MV_FALSE); + + /* Disable the port. */ + mvTsuPortEnable(port,MV_FALSE); + + /* Free descriptors buffer. */ + portCtrl = &mvTsuPortCtrl[port]; + mvOsIoUncachedFree(mvTsuCtrl.osHandle, + portCtrl->descSize * portCtrl->numTsDesc, + portCtrl->descPhyAddr,portCtrl->descVirtAddr, + portCtrl->descMemHandle); + return MV_OK; +} + + +/******************************************************************************* +* mvTsuDmaWatermarkSet +* +* DESCRIPTION: +* Set the watermark for starting a DMA transfer from / to the TSU +* internal FIFO to the CPU memory. +* +* INPUT: +* port - The port number to configure. +* watermark - The watermark to configure (in DWORD units). +* For Rx: Number of data DWORDS in FIFO to start DMA. +* For Tx: Number of free DWORDS in FIFO to start DMA. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad watermark value.. +* +*******************************************************************************/ +MV_STATUS mvTsuDmaWatermarkSet(MV_U8 port, MV_U32 watermark) +{ + MV_U32 reg; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + if(watermark > TSU_DMAP_DATA_WTRMK_MAX) + return MV_BAD_PARAM; + + /* Disable operation mode. */ + mvTsuOperationModeSet(port,MV_FALSE); + + reg = MV_REG_READ(MV_TSU_DMA_PARAMS_REG(port)); + reg &= ~TSU_DMAP_DATA_WTRMK_MASK; + reg |= (watermark << TSU_DMAP_DATA_WTRMK_OFFS); + MV_REG_WRITE(MV_TSU_DMA_PARAMS_REG(port),reg); + + /* Enable operation mode. */ + mvTsuOperationModeSet(port,MV_TRUE); + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuAggrMode1TmsOnPcktEn +* +* DESCRIPTION: +* Set the TSU unit to add the timestamp to the packet buffer when working +* in aggregation mode-1. +* +* INPUT: +* port - The port number to configure. +* enable - When True, enables the placement of timestamp data in the +* packet buffer. +* When False, the timestamp is placed in the Done-Queue. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* +*******************************************************************************/ +MV_STATUS mvTsuAggrMode1TmsOnPcktEn(MV_U8 port, MV_BOOL enable) +{ + MV_U32 reg; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + + /* Disable operation mode. */ + mvTsuOperationModeSet(port,MV_FALSE); + + reg = MV_REG_READ(MV_TSU_AGGREGATION_CTRL_REG(port)); + reg &= ~TSU_AGGR_TMSTMP_MODE_MASK; + if(enable == MV_TRUE) + reg |= TSU_AGGR_TMSTMP_TO_PCKT; + else + reg |= TSU_AGGR_TMSTMP_TO_DONE_Q; + MV_REG_WRITE(MV_TSU_AGGREGATION_CTRL_REG(port),reg); + + /* Enable operation mode. */ + mvTsuOperationModeSet(port,MV_TRUE); + + return MV_OK; +} + + +/********************************/ +/* Rx related APIs */ +/********************************/ + + +/******************************************************************************* +* mvTsuRxSyncDetectionSet +* +* DESCRIPTION: +* Set TS synchronization parameters for Rx data. +* +* INPUT: +* port - The port number to configure. +* syncDetect - Number of TS sync matches to lock signal. +* syncLoss - Number of TS sync losses to unlock signal. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad sync values configuration. +* +*******************************************************************************/ +MV_STATUS mvTsuRxSyncDetectionSet(MV_U8 port, MV_U8 syncDetect, MV_U8 syncLoss) +{ + MV_U32 reg; + MV_U8 maxVal; + + if(port >= MV_TSU_NUM_PORTS) + return MV_OUT_OF_RANGE; + + maxVal = TSU_SYNC_LOSS_CNT_MASK >> TSU_SYNC_LOSS_CNT_OFFS; + if((syncDetect > maxVal) || (syncLoss > maxVal)) + return MV_BAD_PARAM; + + /* Disable operation mode. */ + mvTsuOperationModeSet(port,MV_FALSE); + + reg = MV_REG_READ(MV_TSU_SYNCBYTE_DETECT_REG(port)); + reg &= ~(TSU_SYNC_LOSS_CNT_MASK | TSU_SYNC_DETECT_CNT_MASK); + reg |= ((syncDetect << TSU_SYNC_DETECT_CNT_OFFS) | + (syncLoss << TSU_SYNC_LOSS_CNT_OFFS)); + MV_REG_WRITE(MV_TSU_SYNCBYTE_DETECT_REG(port),reg); + + /* Enable operation mode. */ + mvTsuOperationModeSet(port,MV_TRUE); + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuRxSyncDetectionGet +* +* DESCRIPTION: +* Get TS synchronization parameters for Rx data. +* +* INPUT: +* port - The port number. +* OUTPUT: +* syncDetect - Number of TS sync matches to lock signal. +* syncLoss - Number of TS sync losses to unlock signal. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad pointers. +* +*******************************************************************************/ +MV_STATUS mvTsuRxSyncDetectionGet(MV_U8 port, MV_U8 *syncDetect, MV_U8 *syncLoss) +{ + MV_U32 reg; + + if(port >= MV_TSU_NUM_PORTS) + return MV_OUT_OF_RANGE; + + if((syncDetect == NULL) || (syncLoss == NULL)) + return MV_BAD_PARAM; + + reg = MV_REG_READ(MV_TSU_SYNCBYTE_DETECT_REG(port)); + + *syncDetect = (reg & TSU_SYNC_DETECT_CNT_MASK) >> TSU_SYNC_DETECT_CNT_OFFS; + *syncLoss = (reg & TSU_SYNC_LOSS_CNT_MASK) >> TSU_SYNC_LOSS_CNT_OFFS; + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuRxFullBuffCountGet +* +* DESCRIPTION: +* Get number of Rx packets ready for CPU processing. +* +* INPUT: +* port - TSU port number. +* OUTPUT: +* numBlocks - Number of data blocks ready for CPU processing +* (already have data for processing). +* numBuffers - Number of buffers ready for CPU processing (already +* have data for processing). +* In non-aggreagtion mode numBlocks == numBuffers. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_NOT_SUPPORTED- If the port is not configured in input mode. +* +*******************************************************************************/ +MV_STATUS mvTsuRxFullBuffCountGet(MV_U8 port, MV_U32 *numBlocks, + MV_U32 *numBuffers) +{ + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + if(mvTsuPortCtrl[port].portDir != TSU_PORT_INPUT) + return MV_NOT_SUPPORTED; + return mvTsuReadyBuffCountGet(port,numBlocks,numBuffers); +} + +/******************************************************************************* +* mvTsuRxNextBuffGet +* +* DESCRIPTION: +* Get a pointer to the next available Rx data & status buffers from the Rx +* queue. +* +* INPUT: +* port - TSU port number. +* dataBuff - Pointer to return the address of the next data buffer. +* statBuff - Pointer to return the address of the next status +* buffer. +* OUTPUT: +* buffsHandle - A handle returned to the user to be used when freeing +* the buffers in mvTsuRxBuffFree(). +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad parameters. +* MV_NOT_SUPPORTED- Functionality not supported by the port configuration. +* MV_NO_MORE - No Rx data is available for copy. +* NOTE: +* When working in Aggregation mode, the buffer will point to the +* beggining of the aggregation buffer and not to a single packet inside +* the buffer. +* +*******************************************************************************/ +MV_STATUS mvTsuRxNextBuffGet(MV_U8 port,MV_U32 **dataBuff, MV_U32 **statBuff, + MV_U32 *buffsHandle) +{ + MV_TSU_PORT_CTRL *portCtrl; + MV_U32 numBlocks; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + if(mvTsuPortCtrl[port].portDir != TSU_PORT_INPUT) + return MV_NOT_SUPPORTED; + if((dataBuff == NULL) || (statBuff == NULL) || (buffsHandle == NULL)) + return MV_BAD_PARAM; + + mvTsuReadyBuffCountGet(port,&numBlocks,NULL); + if(numBlocks <= 2) + return MV_NO_MORE; + + portCtrl = &mvTsuPortCtrl[port]; + + /* Get read pointer. */ + *dataBuff = (MV_U32*)(((MV_U32)portCtrl->tsDataBuff) + + (portCtrl->dataBlockSize * portCtrl->dataReadIdx)); + *statBuff = + (MV_U32*)(((MV_U32)portCtrl->tsDoneBuff) + + (TSU_DONE_STATUS_ENTRY_SIZE * portCtrl->statReadIdx)); + *buffsHandle = TSU_BUFF_HNDL(portCtrl->dataReadIdx, + portCtrl->statReadIdx); + return MV_OK; +} + + +/******************************************************************************* +* mvTsuRxTimestampCntEn +* +* DESCRIPTION: +* Enable / Disable the timestamp counter for Rx direction. +* +* INPUT: +* port - TSU port number. +* enable - MV_TRUE to enable the timestamp counter. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad parameters. +* NOTE: +* +*******************************************************************************/ +MV_STATUS mvTsuRxTimestampCntEn(MV_U8 port,MV_BOOL enable) +{ + MV_U32 reg; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + if(mvTsuPortCtrl[port].portDir != TSU_PORT_INPUT) + return MV_NOT_SUPPORTED; + + reg = MV_REG_READ(MV_TSU_TIMESTAMP_CTRL_REG(port)); + reg &= ~TSU_TMS_CTRL_TIMER_MASK; + + if(enable == MV_TRUE) + reg |= TSU_TMS_CTRL_TIMER_EN; + else + reg |= TSU_TMS_CTRL_TIMER_DIS; + + MV_REG_WRITE(MV_TSU_TIMESTAMP_CTRL_REG(port),reg); + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuRxBuffFree +* +* DESCRIPTION: +* Mark a given set of buffers to be free (ready for new data Rx). +* +* INPUT: +* port - TSU port number. +* dataBuff - Pointer to the start of data buffer to return. +* statBuff - Pointer to the start of status buffer to return. +* buffsHandle - The buffers handle as returned by mvTsuRxNextBuffGet() +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_NO_MORE - No Rx data is available for copy. +* MV_BAD_PARAM - Bad parameters. +* MV_BAD_STATE - Bad buffer free order, attempting to free a buffer +* before all previous buffers where freed. +* NOTE: +* When working in Aggregation mode, the buffer will point to the +* beggining of the aggregation buffer and not to a single packet inside +* the buffer. +* +*******************************************************************************/ +MV_STATUS mvTsuRxBuffFree(MV_U8 port,MV_U32 *dataBuff, MV_U32 *statBuff, + MV_U32 buffsHandle) +{ + MV_TSU_PORT_CTRL *portCtrl; + MV_U32 ptr; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + if(mvTsuPortCtrl[port].portDir != TSU_PORT_INPUT) + return MV_NOT_SUPPORTED; + if((dataBuff == NULL) || (statBuff == NULL)) + return MV_BAD_PARAM; + + portCtrl = &mvTsuPortCtrl[port]; + + if(buffsHandle != + TSU_BUFF_HNDL(portCtrl->dataReadIdx,portCtrl->statReadIdx)){ + mvOsPrintf("Bad state..........................\n"); + return MV_BAD_STATE; + } + + portCtrl->dataReadIdx = + (portCtrl->dataReadIdx + 1) & (portCtrl->numTsDesc - 1); + if(portCtrl->dataReadIdx == 0) + portCtrl->cpuRollBit ^= (portCtrl->queueMask + 1); + + portCtrl->statReadIdx = + ((portCtrl->statReadIdx + portCtrl->aggrNumPckts) & + (portCtrl->numDoneQEntry - 1)); + + /* Update the desc queue write pointer. */ + ptr = (portCtrl->dataReadIdx << 2) | portCtrl->cpuRollBit; + + MV_REG_WRITE(MV_TSU_DESC_QUEUE_WRITE_PTR_REG(port),ptr); + + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuRxFlushErrorPackets +* +* DESCRIPTION: +* Enable / Disable flushing of received erroneous packets. +* +* INPUT: +* port - TSU port number. +* enableFlush - MV_TRUE to flush recieved erroneous packets. +* MV_FALSE to copy erroneous packets to Rx buffers. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* +*******************************************************************************/ +MV_STATUS mvTsuRxFlushErrorPackets(MV_U8 port, MV_BOOL enableFlush) +{ + MV_U32 reg; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + + /* Disable operation mode. */ + mvTsuOperationModeSet(port,MV_FALSE); + + reg = MV_REG_READ(MV_TSU_AGGREGATION_CTRL_REG(port)); + reg &= ~TSU_AGGR_FLUSH_ERR_MASK; + if(enableFlush == MV_TRUE) + reg |= TSU_AGGR_FLUSH_ERR_ENABLE; + else + reg |= TSU_AGGR_FLUSH_ERR_DISABLE; + MV_REG_WRITE(MV_TSU_AGGREGATION_CTRL_REG(port),reg); + + /* Enable operation mode. */ + mvTsuOperationModeSet(port,MV_TRUE); + return MV_OK; +} + + +/********************************/ +/* Tx related APIs */ +/********************************/ + +/******************************************************************************* +* mvTsuTxClockFreqSet +* +* DESCRIPTION: +* Configure the transmit clock frequency and parameters. +* +* INPUT: +* port - TSU port number. +* freq - The frequency to configure in Hz. +* autoAdjust - Whether to adjust the Tx frequency according to the +* next packet timestamp. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_VALUE - Bad Tx frequency value. +* +*******************************************************************************/ +MV_STATUS mvTsuTxClockFreqSet(MV_U8 port, MV_U32 freq, MV_BOOL autoAdjust) +{ + MV_U32 reg; + MV_U32 clockVal; + MV_U32 divider; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + clockVal = mvTsuCoreClock2Val[mvTsuCtrl.coreClock]; + if(freq > clockVal) + return MV_BAD_VALUE; + + /* Disable operation mode. */ + mvTsuOperationModeSet(port,MV_FALSE); + + /* Find the correct divider that satisfies: freq <= (core_clock / div)*/ + divider = TSU_NUM_CLOCK_DIVIDERS - 1; + while(divider != 0) + { + if(freq <= (clockVal >> divider)) + break; + divider--; + } + + /* Now, bestDev holds the best divider value. */ + reg = MV_REG_READ(MV_TSU_CONFIG_REG(port)); + reg &= ~(TSU_CFG_OUT_CLOCK_MASK | TSU_CFG_FREQ_MODE_MASK); + switch(divider) + { + case(0): /* 1 */ + reg |= (1 << TSU_CFG_FREQ_MODE_OFFS); + /* Fall through */ + case(3): /* 8 */ + reg |= TSU_CFG_OUT_CLOCK_1_8; + break; + case(1): /* 2 */ + reg |= (1 << TSU_CFG_FREQ_MODE_OFFS); + /* Fall through */ + case(4): /* 16 */ + reg |= TSU_CFG_OUT_CLOCK_2_16; + break; + case(2): /* 4 */ + reg |= (1 << TSU_CFG_FREQ_MODE_OFFS); + /* Fall through */ + case(5): /* 32 */ + reg |= TSU_CFG_OUT_CLOCK_4_32; + break; + default: + break; + } + MV_REG_WRITE(MV_TSU_CONFIG_REG(port),reg); + + /* Setup auto adjust. */ + reg = MV_REG_READ(MV_TSU_TIMESTAMP_CTRL_REG(port)); + reg &= ~TSU_TMS_CTRL_AUTO_ADJ_MASK; + if(autoAdjust == MV_TRUE) + reg |= TSU_TMS_CTRL_AUTO_ADJ_ON; + else + reg |= TSU_TMS_CTRL_AUTO_ADJ_OFF; + MV_REG_WRITE(MV_TSU_TIMESTAMP_CTRL_REG(port),reg); + + /* Enable operation mode. */ + mvTsuOperationModeSet(port,MV_TRUE); + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuTxFreeBuffCountGet +* +* DESCRIPTION: +* Get the number of free packets ready to be transmitted in the TX +* descriptor list. +* +* INPUT: +* port - TSU port number. +* OUTPUT: +* numBlocks - Number of data blocks ready for CPU processing +* (does not have data for transmit). +* numBuffers - Number of buffers ready for CPU processing (does not +* have data for transmit). +* In non-aggreagtion mode numBlocks == numBuffers. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_NOT_SUPPORTED- If the port is not configured in output mode. +* +*******************************************************************************/ +MV_STATUS mvTsuTxFreeBuffCountGet(MV_U8 port, MV_U32 *numBlocks, + MV_U32 *numBuffers) +{ + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + if(mvTsuPortCtrl[port].portDir != TSU_PORT_OUTPUT) + return MV_NOT_SUPPORTED; + return mvTsuReadyBuffCountGet(port,numBlocks,numBuffers); +} + + +/******************************************************************************* +* mvTsuRxNextBuffGet +* +* DESCRIPTION: +* Get a pointer to the next available Tx data & status buffers from the Tx +* queue. +* +* INPUT: +* port - TSU port number. +* dataBuff - Pointer to return the address of the next data buffer. +* statBuff - Pointer to return the address of the next status +* buffer. +* OUTPUT: +* buffsHandle - A handle returned to the user to be used when freeing +* the buffers in mvTsuTxBuffPut(). +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad parameters. +* MV_NOT_SUPPORTED- Functionality not supported by the port configuration. +* MV_NO_MORE - No free Tx data is available. +* NOTE: +* When working in Aggregation mode, the buffer will point to the +* beggining of the aggregation buffer and not to a single packet inside +* the buffer. +* +*******************************************************************************/ +MV_STATUS mvTsuTxNextBuffGet(MV_U8 port,MV_U32 **dataBuff,MV_U32 *buffsHandle) +{ + MV_TSU_PORT_CTRL *portCtrl; + MV_U32 numBlocks; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + if(mvTsuPortCtrl[port].portDir != TSU_PORT_OUTPUT) + return MV_NOT_SUPPORTED; + if((dataBuff == NULL) || (buffsHandle == NULL)) + return MV_BAD_PARAM; + + mvTsuTxFreeBuffCountGet(port,&numBlocks,NULL); + if(numBlocks <= 2) + return MV_NO_MORE; + +// if(numBlocks == 0) +// return MV_NO_MORE; + + portCtrl = &mvTsuPortCtrl[port]; + + if(dataBuff != NULL) { + *dataBuff = (MV_U32*)(((MV_U32)portCtrl->tsDataBuff) + + (portCtrl->dataBlockSize * portCtrl->dataReadIdx)); + *buffsHandle = TSU_BUFF_HNDL(portCtrl->dataReadIdx,portCtrl->statReadIdx); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuTxBuffPut +* +* DESCRIPTION: +* Mark a given set of buffers to be ready for transmission. +* +* INPUT: +* port - TSU port number. +* dataBuff - Pointer to the start of data buffer to put. +* tmsValue - The timestamp to associate with the buffer. +* This parameter is applicable only when working in +* non-aggregation mode. +* tsErr - Indicates if the TS packet should be sent as an +* erroneous packet. +* This parameter is applicable only when working in +* non-aggregation mode. +* buffsHandle - The buffer handle as returned by mvTsuTxNextBuffGet() +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad function parameters. +* NOTE: +* When working in Aggregation mode, the buffer will point to the +* beggining of the aggregation buffer and not to a single packet inside +* the buffer. +* +*******************************************************************************/ +MV_STATUS mvTsuTxBuffPut(MV_U8 port, MV_U32 *dataBuff, MV_U32 tmsValue, + MV_BOOL tsErr, MV_U32 buffsHandle) +{ + MV_TSU_PORT_CTRL *portCtrl; + MV_U32 *descEntry; + MV_U32 ptr; + MV_U32 reg; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + if(mvTsuPortCtrl[port].portDir != TSU_PORT_OUTPUT) + return MV_NOT_SUPPORTED; + if(dataBuff == NULL) + return MV_BAD_PARAM; + + portCtrl = &mvTsuPortCtrl[port]; + if(TSU_BUFF_HNDL_2_DATA_IDX(buffsHandle) != portCtrl->dataReadIdx) + return MV_BAD_STATE; + + if(portCtrl->aggrMode == MV_TSU_AGGR_MODE_DISABLED) { + /* Write the timestamp value. */ + descEntry = (MV_U32*)(((MV_U32)portCtrl->descVirtAddr) + + (portCtrl->dataReadIdx << 3)); + TSU_SET_OUT_DESC_TMSTMP(descEntry,tmsValue,tsErr); + } + + portCtrl->dataReadIdx = + (portCtrl->dataReadIdx + 1) & (portCtrl->numTsDesc - 1); + if(portCtrl->dataReadIdx == 0) + portCtrl->cpuRollBit ^= (portCtrl->queueMask + 1); + + /* Update the desc queue write pointer. */ + ptr = (portCtrl->dataReadIdx << 3) | portCtrl->cpuRollBit; + MV_REG_WRITE(MV_TSU_DESC_QUEUE_WRITE_PTR_REG(port),ptr); + + if(portCtrl->enableTimer) { + /* Enable the timestamp counter. */ + reg = MV_REG_READ(MV_TSU_TIMESTAMP_CTRL_REG(port)); + reg &= ~TSU_TMS_CTRL_TIMER_MASK; + reg |= TSU_TMS_CTRL_TIMER_EN; + MV_REG_WRITE(MV_TSU_TIMESTAMP_CTRL_REG(port),reg); + portCtrl->enableTimer = MV_FALSE; + } + return MV_OK; +} + + +/******************************************************************************* +* mvTsuTxStatusGet +* +* DESCRIPTION: +* Get the next TX done buffer from the TX done queue. +* +* INPUT: +* port - TSU port number. +* doneBuff - Pointer to return the address of the next done buffer. +* buffsHandle - The buffer handle as returned by mvTsuTxNextBuffGet() +* OUTPUT: +* numBuffs - Number of returned buffers. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_NO_MORE - No free Tx buffers are avilable. +* NOTE: +* +*******************************************************************************/ +MV_STATUS mvTsuTxStatusGet(MV_U8 port, MV_U32 **doneBuff, MV_U32 buffsHandle) +{ + MV_TSU_PORT_CTRL *portCtrl; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + if(mvTsuPortCtrl[port].portDir != TSU_PORT_OUTPUT) + return MV_NOT_SUPPORTED; + if(doneBuff == NULL) + return MV_BAD_PARAM; + + portCtrl = &mvTsuPortCtrl[port]; + if(TSU_BUFF_HNDL_2_STAT_IDX(buffsHandle) != portCtrl->statReadIdx) + return MV_BAD_STATE; + + *doneBuff = (MV_U32*)(portCtrl->tsDoneBuff + portCtrl->statReadIdx); + + portCtrl->statReadIdx = + ((portCtrl->statReadIdx + portCtrl->aggrNumPckts)& + (portCtrl->numDoneQEntry - 1)); + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuTxInitTimeStampSet +* +* DESCRIPTION: +* Set the initial timestamp value for TX operations. +* This function must be called before each transmit session. +* +* INPUT: +* port - TSU port number. +* enableTmstmp - Enable the timestamp mechanism for packet transmit. +* When false, the TSU will transmit packets back-to-back +* initTimestamp - (Valid only if enableTs == MV_TRUE) +* The initial timestamp to set. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad timestamp value. +* +*******************************************************************************/ +MV_STATUS mvTsuTxInitTimeStampSet(MV_U8 port, MV_BOOL enableTmstmp, + MV_U32 initTimestamp) +{ + MV_U32 reg; + MV_U32 tsReg; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + if(mvTsuPortCtrl[port].portDir != TSU_PORT_OUTPUT) + return MV_NOT_SUPPORTED; + + /* Disable operation mode. */ + mvTsuOperationModeSet(port,MV_FALSE); + + reg = MV_REG_READ(MV_TSU_TIMESTAMP_CTRL_REG(port)); + if(enableTmstmp == MV_TRUE) + { + /* Setup timestamp initial value. */ + tsReg = MV_REG_READ(MV_TSU_TIMESTAMP_REG(port)); + tsReg &= ~TSU_TMSTMP_TIMESTAMP_MASK; + tsReg |= (initTimestamp & + (TSU_TMSTMP_TIMESTAMP_MASK >> TSU_TMSTMP_TIMESTAMP_OFFS)); + MV_REG_WRITE(MV_TSU_TIMESTAMP_REG(port),tsReg); + + /* Trigger the TSU to read the timestamp. */ + reg |= (1 << TSU_TMS_CTRL_READ_TIMER_OFFS); + } + + /* Disable the timestamp counter (Will be enabled on */ + /* the first packet Tx */ + reg &= ~TSU_TMS_CTRL_TIMER_MASK; + reg |= TSU_TMS_CTRL_TIMER_DIS; + MV_REG_WRITE(MV_TSU_TIMESTAMP_CTRL_REG(port),reg); + mvTsuPortCtrl[port].enableTimer = enableTmstmp; + + /* Enable operation mode. */ + mvTsuOperationModeSet(port,MV_TRUE); + return MV_OK; +} + + +/******************************************************************************* +* mvTsuTxDone +* +* DESCRIPTION: +* Inform the TS unit that the current transmission session is over. +* This will stop the internal timestamp counters held by the unit. +* +* INPUT: +* port - TSU port number. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* +*******************************************************************************/ +MV_STATUS mvTsuTxDone(MV_U8 port) +{ + MV_U32 reg; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + if(mvTsuPortCtrl[port].portDir != TSU_PORT_OUTPUT) + return MV_NOT_SUPPORTED; + + /* Disable operation mode. */ + mvTsuOperationModeSet(port,MV_FALSE); + + reg = MV_REG_READ(MV_TSU_TIMESTAMP_CTRL_REG(port)); + + /* Disable the timestamp counter. */ + reg &= ~TSU_TMS_CTRL_TIMER_MASK; + reg |= TSU_TMS_CTRL_TIMER_DIS; + MV_REG_WRITE(MV_TSU_TIMESTAMP_CTRL_REG(port),reg); + + /* Enable operation mode. */ + mvTsuOperationModeSet(port,MV_TRUE); + return MV_OK; +} + + +/******************************************************************************* +* mvTsuOperationModeSet +* +* DESCRIPTION: +* Set the given TS port into operaion mode. +* +* INPUT: +* port - TSU port number. +* enable - MV_TRUE: enable operation mode. +* MV_FALSE: disable operation mode. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* +*******************************************************************************/ +inline static MV_STATUS mvTsuOperationModeSet(MV_U8 port, MV_BOOL enable) +{ + MV_U32 reg; + + reg = MV_REG_READ(MV_TSU_CONFIG_REG(port)); + reg &= ~TSU_CFG_OPER_MASK; + if(enable) + reg |= TSU_CFG_OPER_ENABLE; + else + reg |= TSU_CFG_OPER_DISABLE; + MV_REG_WRITE(MV_TSU_CONFIG_REG(port),reg); + return MV_OK; +} + + +/******************************************************************************* +* mvTsuReadyBuffCountGet +* +* DESCRIPTION: +* Get number of packets ready for CPU processing. +* In Rx direction, this is the number of packets ready to be rpocessed by +* CPU. For Tx direction, this is the number of free buffers ready for data +* transmission. +* +* INPUT: +* port - TSU port number. +* OUTPUT: +* numBlocks - Number of data blocks ready for CPU processing +* (already have data for processing). +* numBuffers - Number of buffers ready for CPU processing (already +* have data for processing). +* In non-aggreagtion mode numBlocks == numBuffers. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* +*******************************************************************************/ +static MV_STATUS mvTsuReadyBuffCountGet(MV_U8 port, MV_U32 *numBlocks, + MV_U32 *numBuffers) +{ + MV_U32 cpuPtr; + MV_U32 tsuPtr; + MV_U32 result = 0; + MV_U32 tsuRollBit; + MV_TSU_PORT_CTRL *portCtrl = &mvTsuPortCtrl[port]; + + /* Get CPU pointer. */ + cpuPtr = portCtrl->dataReadIdx; + + /* Get TSU pointer. */ + tsuPtr = MV_REG_READ(MV_TSU_DESC_QUEUE_READ_PTR_REG(port)); + + tsuRollBit = tsuPtr & (portCtrl->queueMask + 1); + tsuPtr &= portCtrl->queueMask; + tsuPtr /= portCtrl->queueDescSize; + + if(tsuPtr > cpuPtr) { + result = tsuPtr - cpuPtr; + } else if(tsuPtr < cpuPtr) { + result = tsuPtr + portCtrl->numTsDesc - cpuPtr; + } else if( (tsuPtr == cpuPtr) && (portCtrl->cpuRollBit == tsuRollBit) ) { + result = portCtrl->numTsDesc; + } + + if(numBuffers) + *numBuffers = result * portCtrl->aggrNumPckts; + if(numBlocks) + *numBlocks = result; + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuPortEnable +* +* DESCRIPTION: +* Enable port for receiving & transmitting data after it has been +* configured. +* +* INPUT: +* port - The port number to configure. +* enable - MV_TRUE to enable port. +* MV_FALSE to disable it. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* +*******************************************************************************/ +static MV_STATUS mvTsuPortEnable(MV_U8 port,MV_BOOL enable) +{ + MV_U32 reg; + + if(port >= mvTsuCtrl.numActPorts) + return MV_OUT_OF_RANGE; + + if(enable == MV_TRUE) + reg = 0xFFFFFFFF; + else + reg = 0x04040404; + + reg = MV_REG_WRITE(MV_TSU_ENABLE_ACCESS_REG(port),reg); + return MV_OK; +} + diff --git a/board/mv_feroceon/mv_hal/ts/mvTsu.h b/board/mv_feroceon/mv_hal/ts/mvTsu.h new file mode 100644 index 0000000..de0cd55 --- /dev/null +++ b/board/mv_feroceon/mv_hal/ts/mvTsu.h @@ -0,0 +1,830 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INC_MV_TSU_H__ +#define __INC_MV_TSU_H__ + +#include "ts/mvTsuRegs.h" +#include "mvCommon.h" + +/********************************/ +/* General enums and structures */ +/********************************/ + +#define MV_TSU_NUM_PORTS (2) + +#define MV_TSU_STATUS_CONN_ERROR (0x1) +#define MV_TSU_STATUS_OVFL_ERROR (0x2) +#define MV_TSU_STATUS_TSIF_ERROR (0x4) + +#define TSU_DONE_STATUS_ENTRY_SIZE (4) +#define TSU_INPUT_DESC_ENTRY_SIZE (4) +#define TSU_OUTPUT_DESC_ENTRY_SIZE(agrMode) ((agrMode == MV_TSU_AGGR_MODE_DISABLED) ? (8) : (4)) +#define TSU_MODE1_OUT_TMS_SIZE (8) +#define MV_TSU_MAX_IN_QUEUE_LEN (1024) +#define MV_TSU_MAX_OUT_QUEUE_LEN (512) +#define MV_TSU_MAX_DONEQ_LEN (1024) +#define TSU_DMA_ALIGN (32) + +#define MV_TSU_TX_CLOCK_EXTERNAL (0xFFFFFFFF) + +typedef enum +{ + TSU_CORE_CLK_83_MHZ = 0, + TSU_CORE_CLK_71_MHZ, + TSU_CORE_CLK_91_MHZ, + TSU_CORE_CLK_100_MHZ +}MV_TSU_CORE_CLOCK; + +typedef enum +{ + TSU_MODE_SERIAL, + TSU_MODE_PARALLEL +}MV_TSU_PORTS_MODE; + +typedef enum +{ + TSU_SIGNAL_KEEP_DEF, /* Keep default. */ + TSU_SIGNAL_DIS, + TSU_SIGNAL_EN_ACT_LOW, + TSU_SIGNAL_EN_ACT_HIGH +}MV_TSU_SIGNAL_MODE; + + +typedef enum +{ + TSU_SIGNAL_EDGE_KEEP_DEF, /* Keep default. */ + TSU_SIGNAL_EDGE_FALL, + TSU_SIGNAL_EDGE_RISE +}MV_TSU_SIGNAL_EDGE; + + +typedef enum +{ + TSU_PORT_INPUT, + TSU_PORT_OUTPUT +}MV_TSU_PORT_DIRECTION; + + +typedef struct +{ + MV_TSU_SIGNAL_MODE tsSync; + MV_TSU_SIGNAL_MODE tsValid; + MV_TSU_SIGNAL_MODE tsError; + MV_TSU_SIGNAL_EDGE tsDataEdge; +}MV_TSU_SIGNAL_CONFIG; + + +/* Serial data bits order, only one option can be selected. */ +#define MV_TSU_SER_DATA_ORDER_MSB (0x0001) +#define MV_TSU_SER_DATA_ORDER_LSB (0x0002) +#define MV_TSU_SER_DATA_ORDER_MASK \ + (MV_TSU_SER_DATA_ORDER_MSB | MV_TSU_SER_DATA_ORDER_LSB) + + +/* Serial sync signal active length in bits, only one option */ +/* can be selected. */ +#define MV_TSU_SER_SYNC_ACT_1_BIT (0x0004) +#define MV_TSU_SER_SYNC_ACT_8_BIT (0x0008) +#define MV_TSU_SER_SYNC_ACT_LEN_MASK \ + (MV_TSU_SER_SYNC_ACT_1_BIT | MV_TSU_SER_SYNC_ACT_8_BIT) + +/* Serial Tx signal mode, continuous or gapped, only one option */ +/* can be selected. */ +#define MV_TSU_SER_TX_CLK_MODE_CONT (0x0010) +#define MV_TSU_SER_TX_CLK_MODE_GAPPED (0x0020) +#define MV_TSU_SER_TX_CLK_MODE_MASK \ + (MV_TSU_SER_TX_CLK_MODE_CONT | MV_TSU_SER_TX_CLK_MODE_GAPPED) + + +typedef struct +{ + MV_TSU_PORT_DIRECTION portDir; + MV_U16 pktSize; /* 188 to 256 */ +}MV_TSU_PORT_CONFIG; + + +#define MV_TSU_AGGR_MODE_DISABLED (1) +#define MV_TSU_AGGR_MODE_1 (2) +#define MV_TSU_AGGR_MODE_2 (3) + +/* + * MV_TSU_BUFF_INFO: + * + * aggrMode: Aggregation mode MV_TSU_AGGR_MODE_X + * aggrMode2TmstmpOff: Timestamp offset in case of aggr mode 2. + * aggrNumPackets: Number of packets in each aggregation. + * numTsDesc: Number of descriptors (Power of 2). + * numDoneQEntry: Number of done queue entries (Power of 2). + * tsDataBuff: Pointer to the data buffers list, the user must ensure + * DMA coherency for these buffers. The content of these + * buffers is never accessed by the HAL. + * tsDoneBuff: Pointer to the data status list, the user must ensure + * DMA coherency for these buffers. The content of these + * buffers is never accessed by the HAL. + * dataBlockSize: the size of a single data block, this can be larger than + * the amount of memory needed to hold TS packets in order + * to insure a certain alignment of the buffers. + * + * Guidelines for calculating the data & status buffers length: + * + * data-buff-len = dataBlockSize * numTsDesc + * In normal mode: + * dataBlockSize = + alignment_space + * done-buff-len= numDoneQEntry * TSU_DONE_STATUS_ENTRY_SIZE + * + * In aggregation mode 1: + * dataBlockSize = * aggrNumPackets + alignment_space + * done-buff-len= numDoneQEntry * TSU_DONE_STATUS_ENTRY_SIZE + * + * In aggregation mode 2: + * dataBlockSize = (( + aggrMode2TmstmpOff)* + * aggrNumPackets) + alignment_space + * done-buff-len= numDoneQEntry * TSU_DONE_STATUS_ENTRY_SIZE + */ +typedef struct +{ + MV_U8 aggrMode; + MV_U8 aggrMode2TmstmpOff; + MV_U8 aggrNumPackets; + + MV_U32 numTsDesc; + MV_U32 numDoneQEntry; + MV_U32 *tsDataBuff; + MV_U32 tsDataBuffPhys; + MV_U32 *tsDoneBuff; + MV_U32 tsDoneBuffPhys; + MV_U32 dataBlockSize; +}MV_TSU_BUFF_INFO; + + +/********************************/ +/* Macros */ +/********************************/ +#define MV_TSU_STATUS_ENTRY_TMS_GET(stat) (MV_U32)(stat & 0xFFFFFFF) + + +/********************************/ +/* Functions API */ +/********************************/ + +/******************************************************************************* +* mvTsuHalInit +* +* DESCRIPTION: +* Initialize the TSU unit, and get unit out of reset. +* +* INPUT: +* coreClock - The core clock at which the TSU should operate. +* mode - The mode on configure the unit into (serial/parallel). +* osHandle - Memory handle used for memory allocations. +* OUTPUT: +* None. +* RETURN: +* MV_OK - on success, +* +*******************************************************************************/ +MV_STATUS mvTsuHalInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, + void *osHandle); + + +/******************************************************************************* +* mvTsuShutdown +* +* DESCRIPTION: +* Shutdown the TS unit, and put into reset state. +* +* INPUT: +* None. +* OUTPUT: +* None. +* RETURN: +* MV_OK - on success, +* +*******************************************************************************/ +MV_STATUS mvTsuShutdown(void); + + +/******************************************************************************* +* mvTsuPortReset +* +* DESCRIPTION: +* Perform a SW reset on a given port. +* +* INPUT: +* port - The port number to reset. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_BAD_VALUE - Bad port configuration option. +* MV_BAD_SIZE - Illegal number of ports. +* +*******************************************************************************/ +MV_STATUS mvTsuPortReset(MV_U8 port); + + +/******************************************************************************* +* mvTsuWinInit +* +* DESCRIPTION: +* Initialize the TSU unit access windows mapping. +* +* INPUT: +* None. +* OUTPUT: +* None. +* RETURN: +* MV_OK - on success, +* +*******************************************************************************/ +MV_STATUS mvTsuWinInit(void); + + +/******************************************************************************* +* mvTsuPortInit +* +* DESCRIPTION: +* Initialize the TSU ports. +* +* INPUT: +* port - The port number to configure. +* portCfg - Port configurations parameters. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_BAD_VALUE - Bad port configuration option. +* MV_BAD_SIZE - Illegal number of ports. +* +*******************************************************************************/ +MV_STATUS mvTsuPortInit(MV_U8 port, MV_TSU_PORT_CONFIG *portCfg); + + +/******************************************************************************* +* mvTsuPortSignalCfgSet +* +* DESCRIPTION: +* Configure port signals parameters. +* +* INPUT: +* port - The port to configure. +* signalCfg - Signal configuration options. +* serialflags - Serial signal configuration options (valid only if the +* port is working in serial mode). +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_BAD_VALUE - Bad port configuration option. +* MV_BAD_SIZE - Illegal number of ports. +* +*******************************************************************************/ +MV_STATUS mvTsuPortSignalCfgSet(MV_U8 port, MV_TSU_SIGNAL_CONFIG *signalCfg, + MV_U32 serialFlags); + + +/******************************************************************************* +* mvTsuPortSignalCfgGet +* +* DESCRIPTION: +* Get port signals parameters. +* +* INPUT: +* port - The port to configure. +* OUTPUT: +* signalCfg - Signal configuration options. +* serialflags - Serial signal configuration options (valid only if the +* port is working in serial mode). +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Illegal port number. +* MV_BAD_PARAM - Bad pointers. +* +*******************************************************************************/ +MV_STATUS mvTsuPortSignalCfgGet(MV_U8 port, MV_TSU_SIGNAL_CONFIG *signalCfg, + MV_U32* serialFlags); + + +/******************************************************************************* +* mvTsuStatusGet +* +* DESCRIPTION: +* Get the TSU port status for a given port. +* +* INPUT: +* port - The port number to configure. +* OUTPUT: +* status - Bitmask representing the TSU port status (a bitwise or +* between the MV_TSU_STATUS_* macros. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* +*******************************************************************************/ +MV_STATUS mvTsuStatusGet(MV_U8 port, MV_U32 *status); + + +/******************************************************************************* +* mvTsuBuffersInit +* +* DESCRIPTION: +* Initialize the TSU unit buffers. +* This function is used to initialize both Rx or Tx buffers according to +* the port mode configured in mvTsuPortsInit(). +* +* INPUT: +* port - The port number to configure. +* buffInfo- TSU buffer information. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad buffer configuration options. +* MV_NOT_ALIGNED - Bad data buffer alignemed. +* +*******************************************************************************/ +MV_STATUS mvTsuBuffersInit(MV_U8 port, MV_TSU_BUFF_INFO *buffInfo); + + +/******************************************************************************* +* mvTsuPortShutdown +* +* DESCRIPTION: +* Shutdown the port, this will release any previously allocated port +* memory, and set the port to disable state. +* +* INPUT: +* port - The port number to shutdown. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad buffer configuration options. +* +*******************************************************************************/ +MV_STATUS mvTsuPortShutdown(MV_U8 port); + + +/******************************************************************************* +* mvTsuDmaWatermarkSet +* +* DESCRIPTION: +* Set the watermark for starting a DMA transfer from / to the TSU +* internal FIFO to the CPU memory. +* +* INPUT: +* port - The port number to configure. +* watermark - The watermark to configure (in DWORD units). +* For Rx: Number of data DWORDS in FIFO to start DMA. +* For Tx: Number of free DWORDS in FIFO to start DMA. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad watermark value.. +* +*******************************************************************************/ +MV_STATUS mvTsuDmaWatermarkSet(MV_U8 port, MV_U32 watermark); + + +/******************************************************************************* +* mvTsuAggrMode1TmsOnPcktEn +* +* DESCRIPTION: +* Set the TSU unit to add the timestamp to the packet buffer when working +* in aggregation mode-1. +* +* INPUT: +* port - The port number to configure. +* enable - When True, enables the placement of timestamp data in the +* packet buffer. +* When False, the timestamp is placed in the Done-Queue. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* +*******************************************************************************/ +MV_STATUS mvTsuAggrMode1TmsOnPcktEn(MV_U8 port, MV_BOOL enable); + + +/********************************/ +/* Rx related APIs */ +/********************************/ + + +/******************************************************************************* +* mvTsuRxSyncDetectionSet +* +* DESCRIPTION: +* Set TS synchronization parameters for Rx data. +* +* INPUT: +* port - The port number to configure. +* syncDetect - Number of TS sync matches to lock signal. +* syncLoss - Number of TS sync losses to unlock signal. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad sync values configuration. +* +*******************************************************************************/ +MV_STATUS mvTsuRxSyncDetectionSet(MV_U8 port, MV_U8 syncDetect, MV_U8 syncLoss); + + +/******************************************************************************* +* mvTsuRxSyncDetectionGet +* +* DESCRIPTION: +* Get TS synchronization parameters for Rx data. +* +* INPUT: +* port - The port number. +* OUTPUT: +* syncDetect - Number of TS sync matches to lock signal. +* syncLoss - Number of TS sync losses to unlock signal. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad pointers. +* +*******************************************************************************/ +MV_STATUS mvTsuRxSyncDetectionGet(MV_U8 port, MV_U8 *syncDetect, MV_U8 *syncLoss); + + +/******************************************************************************* +* mvTsuRxFullBuffCountGet +* +* DESCRIPTION: +* Get number of Rx packets ready for CPU processing. +* +* INPUT: +* port - TSU port number. +* OUTPUT: +* numBlocks - Number of data blocks ready for CPU processing +* (already have data for processing). +* numBuffers - Number of buffers ready for CPU processing (already +* have data for processing). +* In non-aggreagtion mode numBlocks == numBuffers. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_NOT_SUPPORTED- If the port is not configured in input mode. +* +*******************************************************************************/ +MV_STATUS mvTsuRxFullBuffCountGet(MV_U8 port, MV_U32 *numBlocks, + MV_U32 *numBuffers); + + +/******************************************************************************* +* mvTsuRxNextBuffGet +* +* DESCRIPTION: +* Get a pointer to the next available Rx data & status buffers from the Rx +* queue. +* +* INPUT: +* port - TSU port number. +* dataBuff - Pointer to return the address of the next data buffer. +* statBuff - Pointer to return the address of the next status buffer. +* OUTPUT: +* buffsHandle - A handle returned to the user to be used when freeing +* the buffers in mvTsuRxBuffFree(). +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad parameters. +* MV_NOT_SUPPORTED- Functionality not supported by the port configuration. +* MV_NO_MORE - No Rx data is available for copy. +* NOTE: +* When working in Aggregation mode, the buffer will point to the +* beggining of the aggregation buffer and not to a single packet inside +* the buffer. +* +*******************************************************************************/ +MV_STATUS mvTsuRxNextBuffGet(MV_U8 port,MV_U32 **dataBuff, MV_U32 **statBuff, + MV_U32 *buffsHandle); + + +/******************************************************************************* +* mvTsuRxTimestampCntEn +* +* DESCRIPTION: +* Enable / Disable the timestamp counter for Rx direction. +* +* INPUT: +* port - TSU port number. +* enable - MV_TRUE to enable the timestamp counter. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad parameters. +* NOTE: +* +*******************************************************************************/ +MV_STATUS mvTsuRxTimestampCntEn(MV_U8 port,MV_BOOL enable); + + +/******************************************************************************* +* mvTsuRxBuffFree +* +* DESCRIPTION: +* Mark a given set of buffers to be free (ready for new data Rx). +* +* INPUT: +* port - TSU port number. +* dataBuff - Pointer to the start of data buffer to return. +* statBuff - Pointer to the start of status buffer to return. +* buffsHandle - The buffers handle as returned by mvTsuRxNextBuffGet() +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_NO_MORE - No Rx data is available for copy. +* MV_BAD_PARAM - Bad parameters. +* MV_BAD_STATE - Bad buffer free order, attempting to free a buffer +* before all previous buffers where freed. +* NOTE: +* When working in Aggregation mode, the buffer will point to the +* beggining of the aggregation buffer and not to a single packet inside +* the buffer. +* The numBuffs represents the number of aggregation buffers and not to the +* number of packets. +* +*******************************************************************************/ +MV_STATUS mvTsuRxBuffFree(MV_U8 port,MV_U32 *dataBuff, MV_U32 *statBuff, + MV_U32 buffsHandle); + + +/******************************************************************************* +* mvTsuRxFlushErrorPackets +* +* DESCRIPTION: +* Enable / Disable flushing of received erroneous packets. +* +* INPUT: +* port - TSU port number. +* enableFlush - MV_TRUE to flush recieved erroneous packets. +* MV_FALSE to copy erroneous packets to Rx buffers. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* +*******************************************************************************/ +MV_STATUS mvTsuRxFlushErrorPackets(MV_U8 port, MV_BOOL enableFlush); + + +/********************************/ +/* Tx related APIs */ +/********************************/ + + +/******************************************************************************* +* mvTsuTxClockFreqSet +* +* DESCRIPTION: +* Configure the transmit clock frequency and parameters. +* +* INPUT: +* port - TSU port number. +* freq - The frequency to configure in Hz. +* range is 2500000 (2.5MHz) to 80000000 (80MHz). +* autoAdjust - Whether to adjust the Tx frequency according to the +* next packet timestamp. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_VALUE - Bad Tx frequency value. +* +*******************************************************************************/ +MV_STATUS mvTsuTxClockFreqSet(MV_U8 port, MV_U32 freq, MV_BOOL autoAdjust); + + +/******************************************************************************* +* mvTsuTxFreeBuffCountGet +* +* DESCRIPTION: +* Get the number of free packets ready to be transmitted in the TX +* descriptor list. +* +* INPUT: +* port - TSU port number. +* OUTPUT: +* numBlocks - Number of data blocks ready for CPU processing +* (does not have data for transmit). +* numBuffers - Number of buffers ready for CPU processing (does not +* have data for transmit). +* In non-aggreagtion mode numBlocks == numBuffers. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_NOT_SUPPORTED- If the port is not configured in input mode. +* +*******************************************************************************/ +MV_STATUS mvTsuTxFreeBuffCountGet(MV_U8 port, MV_U32 *numBlocks, + MV_U32 *numBuffers); + + +/******************************************************************************* +* mvTsuRxNextBuffGet +* +* DESCRIPTION: +* Get a pointer to the next available Tx data & status buffers from the Tx +* queue. +* +* INPUT: +* port - TSU port number. +* dataBuff - Pointer to return the address of the next data buffer. +* numBuffs - Pointer to the maximum number of buffers to return. +* OUTPUT: +* numBuffs - Number of data / status buffers that where returned. +* buffsHandle - A handle returned to the user to be used when freeing +* the buffers in mvTsuRxBuffFree(). +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_NO_MORE - No Rx data is available for copy. +* NOTE: +* When working in Aggregation mode, the buffer will point to the +* beggining of the aggregation buffer and not to a single packet inside +* the buffer. +* The numBuffs represents the number of aggregation buffers and not to the +* number of packets. +* +*******************************************************************************/ +MV_STATUS mvTsuTxNextBuffGet(MV_U8 port,MV_U32 **dataBuff,MV_U32 *buffsHandle); + + +/******************************************************************************* +* mvTsuTxBuffPut +* +* DESCRIPTION: +* Mark a given set of buffers to be ready for transmission. +* +* INPUT: +* port - TSU port number. +* dataBuff - Pointer to the start of data buffer to put. +* tmsValue - The timestamp to associate with the buffer. +* This parameter is applicable only when working in +* non-aggregation mode. +* tsErr - Indicates if the TS packet should be sent as an +* erroneous packet. +* buffsHandle - The buffer handle as returned by mvTsuTxNextBuffGet() +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad function parameters. +* NOTE: +* When working in Aggregation mode, the buffer will point to the +* beggining of the aggregation buffer and not to a single packet inside +* the buffer. +* +*******************************************************************************/ +MV_STATUS mvTsuTxBuffPut(MV_U8 port, MV_U32 *dataBuff, MV_U32 tmsValue, + MV_BOOL tsErr, MV_U32 buffsHandle); + + +/******************************************************************************* +* mvTsuTxStatusGet +* +* DESCRIPTION: +* Get the next TX done buffer from the TX done queue. +* +* INPUT: +* port - TSU port number. +* doneBuff - Pointer to return the address of the next done buffer. +* buffsHandle - The buffer handle as returned by mvTsuTxNextBuffGet() +* OUTPUT: +* numBuffs - Number of returned buffers. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_NO_MORE - No free Tx buffers are avilable. +* NOTE: +* +*******************************************************************************/ +MV_STATUS mvTsuTxStatusGet(MV_U8 port, MV_U32 **doneBuff, MV_U32 buffsHandle); + + +/******************************************************************************* +* mvTsuTxInitTimeStampSet +* +* DESCRIPTION: +* Set the initial timestamp value for TX operations. +* This function must be called before each transmit session. +* +* INPUT: +* port - TSU port number. +* enableTmstmp - Enable the timestamp mechanism for packet transmit. +* When false, the TSU will transmit packets back-to-back +* initTimestamp - (Valid only if enableTs == MV_TRUE) +* The initial timestamp to set. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* MV_BAD_PARAM - Bad timestamp value. +* +*******************************************************************************/ +MV_STATUS mvTsuTxInitTimeStampSet(MV_U8 port, MV_BOOL enableTmstmp, + MV_U32 initTimestamp); + + +/******************************************************************************* +* mvTsuTxDone +* +* DESCRIPTION: +* Inform the TS unit that the current transmission session is over. +* This will stop the internal timestamp counters held by the unit. +* +* INPUT: +* port - TSU port number. +* OUTPUT: +* None. +* RETURN: +* MV_OK - On success, +* MV_OUT_OF_RANGE - Unsupported port number. +* +*******************************************************************************/ +MV_STATUS mvTsuTxDone(MV_U8 port); + + +#endif /* __INC_MV_TSU__H__ */ + diff --git a/board/mv_feroceon/mv_hal/ts/mvTsuRegs.h b/board/mv_feroceon/mv_hal/ts/mvTsuRegs.h new file mode 100644 index 0000000..69c9adb --- /dev/null +++ b/board/mv_feroceon/mv_hal/ts/mvTsuRegs.h @@ -0,0 +1,267 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INC_MV_TSU_REGS_H__ +#define __INC_MV_TSU_REGS_H__ + +#define TSU_MAX_DECODE_WIN 4 + +#define TSU_GLOBAL_REG_BASE 0xB4000 +#define TSU_REG_BASE(port) (0xB8000 + (port * 0x800)) + +#define MV_TSU_MODES_REG (TSU_GLOBAL_REG_BASE + 0x00) + + +#define MV_TSU_CONFIG_REG(port) (TSU_REG_BASE(port) + 0x00) +#define MV_TSU_DMA_PARAMS_REG(port) (TSU_REG_BASE(port) + 0x04) +#define MV_TSU_DONE_QUEUE_BASE_REG(port) (TSU_REG_BASE(port) + 0x08) +#define MV_TSU_DESC_QUEUE_BASE_REG(port) (TSU_REG_BASE(port) + 0x0C) +#define MV_TSU_DONE_QUEUE_WRITE_PTR_REG(port) (TSU_REG_BASE(port) + 0x10) +#define MV_TSU_DONE_QUEUE_READ_PTR_REG(port) (TSU_REG_BASE(port) + 0x14) +#define MV_TSU_DESC_QUEUE_WRITE_PTR_REG(port) (TSU_REG_BASE(port) + 0x18) +#define MV_TSU_DESC_QUEUE_READ_PTR_REG(port) (TSU_REG_BASE(port) + 0x1C) +#define MV_TSU_ENABLE_ACCESS_REG(port) (TSU_REG_BASE(port) + 0x2C) +#define MV_TSU_TIMESTAMP_REG(port) (TSU_REG_BASE(port) + 0x30) +#define MV_TSU_STATUS_REG(port) (TSU_REG_BASE(port) + 0x34) +#define MV_TSU_TIMESTAMP_CTRL_REG(port) (TSU_REG_BASE(port) + 0x38) +#define MV_TSU_TEST_REG(port) (TSU_REG_BASE(port) + 0x3C) +#define MV_TSU_INTERRUPT_SRC_REG(port) (TSU_REG_BASE(port) + 0x40) +#define MV_TSU_INTERRUPT_MASK_REG(port) (TSU_REG_BASE(port) + 0x44) +#define MV_TSU_IRQ_PARAM_REG(port) (TSU_REG_BASE(port) + 0x48) +#define MV_TSU_DEBUG_REG(port) (TSU_REG_BASE(port) + 0x4C) +#define MV_TSU_NEXT_DESC_1_REG(port) (TSU_REG_BASE(port) + 0x50) +#define MV_TSU_NEXT_DESC_2_REG(port) (TSU_REG_BASE(port) + 0x54) +#define MV_TSU_SYNCBYTE_DETECT_REG(port) (TSU_REG_BASE(port) + 0x58) +#define MV_TSU_AGGREGATION_CTRL_REG(port) (TSU_REG_BASE(port) + 0x60) +#define MV_TSU_TIMESTAMP_INTERVAL_REG(port) (TSU_REG_BASE(port) + 0x64) +#define MV_TSU_CONFIG_2_REG(port) (TSU_REG_BASE(port) + 0x68) + + +/* TSU Modes register. */ +#define TSU_MODES_PAR_MODE_OFFS 14 +#define TSU_MODES_PAR_MODE_MASK (0x1 << TSU_MODES_PAR_MODE_OFFS) +#define TSU_MODES_PAR_MODE_SER (0x0 << TSU_MODES_PAR_MODE_OFFS) +#define TSU_MODES_PAR_MODE_PAR (0x1 << TSU_MODES_PAR_MODE_OFFS) +#define TSU_MODES_TSCK_OFF 15 +#define TSU_MODES_TSCK_MASK (0x3 << TSU_MODES_TSCK_OFF) + + +/* TSU config register. */ +#define TSU_CFG_RESET_OFFS 0 +#define TSU_CFG_RESET_MASK (0x3 << TSU_CFG_RESET_OFFS) +#define TSU_CFG_RESET_SET (0x1 << TSU_CFG_RESET_OFFS) +#define TSU_CFG_RESET_CLEAR (0x2 << TSU_CFG_RESET_OFFS) +#define TSU_CFG_OPER_OFFS 2 +#define TSU_CFG_OPER_MASK (0x3 << TSU_CFG_OPER_OFFS) +#define TSU_CFG_OPER_DISABLE (0x1 << TSU_CFG_OPER_OFFS) +#define TSU_CFG_OPER_ENABLE (0x2 << TSU_CFG_OPER_OFFS) +#define TSU_CFG_DATA_DIR_OFFS 8 +#define TSU_CFG_DATA_DIR_MASK (0x1 << TSU_CFG_DATA_DIR_OFFS) +#define TSU_CFG_DATA_DIR_IN (0x0 << TSU_CFG_DATA_DIR_OFFS) +#define TSU_CFG_DATA_DIR_OUT (0x1 << TSU_CFG_DATA_DIR_OFFS) +#define TSU_CFG_DATA_MODE_OFFS 9 +#define TSU_CFG_DATA_MODE_MASK (0x1 << TSU_CFG_DATA_MODE_OFFS) +#define TSU_CFG_DATA_MODE_SER (0x0 << TSU_CFG_DATA_MODE_OFFS) +#define TSU_CFG_DATA_MODE_PAR (0x1 << TSU_CFG_DATA_MODE_OFFS) +#define TSU_CFG_OUT_CLOCK_OFFS 10 +#define TSU_CFG_OUT_CLOCK_MASK (0x3 << TSU_CFG_OUT_CLOCK_OFFS) +#define TSU_CFG_OUT_CLOCK_4_32 (0x0 << TSU_CFG_OUT_CLOCK_OFFS) +#define TSU_CFG_OUT_CLOCK_2_16 (0x1 << TSU_CFG_OUT_CLOCK_OFFS) +#define TSU_CFG_OUT_CLOCK_1_8 (0x2 << TSU_CFG_OUT_CLOCK_OFFS) +#define TSU_CFG_OUT_CLOCK_EXT (0x3 << TSU_CFG_OUT_CLOCK_OFFS) +#define TSU_CFG_CLK_MODE_OFFS 12 +#define TSU_CFG_CLK_MODE_MASK (0x1 << TSU_CFG_CLK_MODE_OFFS) +#define TSU_CFG_CLK_MODE_CONT (0x0 << TSU_CFG_CLK_MODE_OFFS) +#define TSU_CFG_CLK_MODE_GAPPED (0x1 << TSU_CFG_CLK_MODE_OFFS) +#define TSU_CFG_TS_SYNC_OFFS 13 +#define TSU_CFG_TS_SYNC_MASK (0x1 << TSU_CFG_TS_SYNC_OFFS) +#define TSU_CFG_TS_SYNC_8BIT (0x0 << TSU_CFG_TS_SYNC_OFFS) +#define TSU_CFG_TS_SYNC_1BIT (0x1 << TSU_CFG_TS_SYNC_OFFS) +#define TSU_CFG_DATA_ORD_OFFS 14 +#define TSU_CFG_DATA_ORD_MASK (0x1 << TSU_CFG_DATA_ORD_OFFS) +#define TSU_CFG_DATA_ORD_MSB (0x0 << TSU_CFG_DATA_ORD_OFFS) +#define TSU_CFG_DATA_ORD_LSB (0x1 << TSU_CFG_DATA_ORD_OFFS) +#define TSU_CFG_TX_EDGE_OFFS 15 +#define TSU_CFG_TX_EDGE_MASK (0x1 << TSU_CFG_TX_EDGE_OFFS) +#define TSU_CFG_FREQ_MODE_OFFS 16 +#define TSU_CFG_FREQ_MODE_MASK (0x1 << TSU_CFG_FREQ_MODE_OFFS) +#define TSU_CFG_ERR_POL_OFFS 18 +#define TSU_CFG_ERR_POL_MASK (0x1 << TSU_CFG_ERR_POL_OFFS) +#define TSU_CFG_ERR_USED_OFFS 19 +#define TSU_CFG_ERR_USED_MASK (0x1 << TSU_CFG_ERR_USED_OFFS) +#define TSU_CFG_VAL_POL_OFFS 20 +#define TSU_CFG_VAL_POL_MASK (0x1 << TSU_CFG_VAL_POL_OFFS) +#define TSU_CFG_VAL_USED_OFFS 21 +#define TSU_CFG_VAL_USED_MASK (0x1 << TSU_CFG_VAL_USED_OFFS) +#define TSU_CFG_SYNC_POL_OFFS 22 +#define TSU_CFG_SYNC_POL_MASK (0x1 << TSU_CFG_SYNC_POL_OFFS) +#define TSU_CFG_SYNC_USED_OFFS 23 +#define TSU_CFG_SYNC_USED_MASK (0x1 << TSU_CFG_SYNC_USED_OFFS) +#define TSU_CFG_RESET_SET (0x1 << TSU_CFG_RESET_OFFS) +#define TSU_CFG_PKT_SIZE_OFFS 24 +#define TSU_CFG_PKT_SIZE_MASK (0xFF << TSU_CFG_PKT_SIZE_OFFS) + +/* TSU DMA parameters register. */ +#define TSU_DMAP_DMA_LEN_OFFS 0 +#define TSU_DMAP_DMA_LEN_MASK (0xFFFF << TSU_DMAP_DMA_LEN_OFFS) +#define TSU_DMAP_DATA_WTRMK_OFFS 16 +#define TSU_DMAP_DATA_WTRMK_MASK (0xFF << TSU_DMAP_DATA_WTRMK_OFFS) +#define TSU_DMAP_DATA_WTRMK_MAX 0xFF +#define TSU_DMAP_DESC_Q_SIZE_OFFS 24 +#define TSU_DMAP_DESC_Q_SIZE_MASK (0xF << TSU_DMAP_DESC_Q_SIZE_OFFS) +#define TSU_DMAP_DONE_Q_SIZE_OFFS 28 +#define TSU_DMAP_DONE_Q_SIZE_MASK (0xF << TSU_DMAP_DONE_Q_SIZE_OFFS) + +/* TSU Done queue base register. */ +#define TSU_DONE_PTR_BASE_OFFS 2 +#define TSU_DONE_PTR_BASE_MASK (0x3FFFFFFF << TSU_DONE_PTR_BASE_OFFS) + +/* TSU Desc queue base register. */ +#define TSU_DESC_PTR_BASE_OFFS 2 +#define TSU_DESC_PTR_BASE_MASK (0x3FFFFFFF << TSU_DESC_PTR_BASE_OFFS) + +/* TSU Done queue write pointer register. */ +#define TSU_DONE_WRITE_PTR_OFFS 0 +#define TSU_DONE_WRITE_PTR_MASK (0xFFF << TSU_DONE_WRITE_PTR_OFFS) + +/* TSU Done queue read pointer register. */ +#define TSU_DONE_READ_PTR_OFFS 0 +#define TSU_DONE_READ_PTR_MASK (0xFFF << TSU_DONE_READ_PTR_OFFS) + +/* TSU Desc queue write pointer register. */ +#define TSU_DESC_WRITE_PTR_OFFS 0 +#define TSU_DESC_WRITE_PTR_MASK (0xFFF << TSU_DESC_WRITE_PTR_OFFS) + +/* TSU Desc queue read pointer register. */ +#define TSU_DESC_READ_PTR_OFFS 0 +#define TSU_DESC_READ_PTR_MASK (0xFFF << TSU_DESC_READ_PTR_OFFS) + +/* TSU access enable reg. */ +#define TSU_ENACC_TS_READ_OFFS 0 +#define TSU_ENACC_TS_WRITE_OFFS 8 +#define TSU_ENACC_DESC_WRITE_OFFS 16 +#define TSU_ENACC_DESC_READ_OFFS 24 + +/* TSU Timestamp register. */ +#define TSU_TMSTMP_TIMESTAMP_OFFS 0 +#define TSU_TMSTMP_TIMESTAMP_MASK (0xFFFFFFF << TSU_TMSTMP_TIMESTAMP_OFFS) + +/* TSU status register. */ +#define TSU_STATUS_OFFS 0 +#define TSU_STATUS_MASK (0x7FF << TSU_STATUS_OFFS) +#define TSU_STATUS_IF_ERR (0x100 << TSU_STATUS_OFFS) +#define TSU_STATUS_FIFO_OVFL_ERR (0x200 << TSU_STATUS_OFFS) +#define TSU_STATUS_CONN_ERR (0x400 << TSU_STATUS_OFFS) + +/* TSU interrupt source register. */ +#define TSU_INT_TS_IF_ERROR (1 << 3) +#define TSU_INT_FIFO_OVFL_ERROR (1 << 4) +#define TSU_INT_TS_CONN_ERROR (1 << 5) +#define TSU_INT_CLOCK_SYNC_EXP (1 << 6) + +/* TSU SyncByte detect register. */ +#define TSU_SYNC_DETECT_CNT_OFFS 0 +#define TSU_SYNC_DETECT_CNT_MASK (0xF << TSU_SYNC_DETECT_CNT_OFFS) +#define TSU_SYNC_LOSS_CNT_OFFS 4 +#define TSU_SYNC_LOSS_CNT_MASK (0xF << TSU_SYNC_LOSS_CNT_OFFS) + +/* TSU Aggregation control register. */ +#define TSU_AGGR_PCKT_NUM_OFFS 0 +#define TSU_AGGR_PCKT_NUM_MASK (0xFF << TSU_AGGR_PCKT_NUM_OFFS) +#define TSU_AGGR_TMSTMP_OFF_OFFS 8 +#define TSU_AGGR_TMSTMP_OFF_MASK (0xF << TSU_AGGR_TMSTMP_OFF_OFFS) +#define TSU_AGGR_FLUSH_ERR_OFFS 26 +#define TSU_AGGR_FLUSH_ERR_MASK (0x3 << TSU_AGGR_FLUSH_ERR_OFFS) +#define TSU_AGGR_FLUSH_ERR_DISABLE (0x1 << TSU_AGGR_FLUSH_ERR_OFFS) +#define TSU_AGGR_FLUSH_ERR_ENABLE (0x2 << TSU_AGGR_FLUSH_ERR_OFFS) +#define TSU_AGGR_TMSTMP_MODE_OFFS 28 +#define TSU_AGGR_TMSTMP_MODE_MASK (0x3 << TSU_AGGR_TMSTMP_MODE_OFFS) +#define TSU_AGGR_TMSTMP_TO_DONE_Q (0x1 << TSU_AGGR_TMSTMP_MODE_OFFS) +#define TSU_AGGR_TMSTMP_TO_PCKT (0x2 << TSU_AGGR_TMSTMP_MODE_OFFS) +#define TSU_AGGR_ENABLE_OFFS 30 +#define TSU_AGGR_ENABLE_MASK (0x3 << TSU_AGGR_ENABLE_OFFS) +#define TSU_AGGR_DISABLE (0x1 << TSU_AGGR_ENABLE_OFFS) +#define TSU_AGGR_ENABLE (0x2 << TSU_AGGR_ENABLE_OFFS) + + +/* TSU timestamp interval register. */ +#define TSU_TMSTP_INTRVL_OFFS 0 +#define TSU_TMSTP_INTRVL_MASK (0xFFFFFFF << TSU_TMSTP_INTRVL_OFFS) + +/* TSU timestamp control register. */ +#define TSU_TMS_CTRL_TIMER_OFFS 0 +#define TSU_TMS_CTRL_TIMER_MASK (0x3 << TSU_TMS_CTRL_TIMER_OFFS) +#define TSU_TMS_CTRL_TIMER_DIS (0x1 << TSU_TMS_CTRL_TIMER_OFFS) +#define TSU_TMS_CTRL_TIMER_EN (0x2 << TSU_TMS_CTRL_TIMER_OFFS) +#define TSU_TMS_CTRL_AUTO_ADJ_OFFS 2 +#define TSU_TMS_CTRL_AUTO_ADJ_MASK (0x3 << TSU_TMS_CTRL_AUTO_ADJ_OFFS) +#define TSU_TMS_CTRL_AUTO_ADJ_OFF (0x1 << TSU_TMS_CTRL_AUTO_ADJ_OFFS) +#define TSU_TMS_CTRL_AUTO_ADJ_ON (0x2 << TSU_TMS_CTRL_AUTO_ADJ_OFFS) +#define TSU_TMS_CTRL_READ_TIMER_OFFS 4 +#define TSU_TMS_CTRL_READ_TIMER_MASK (0x1 << TSU_TMS_CTRL_READ_TIMER_OFFS) + + + + +#endif /* __INC_MV_TSU_REGS_H__ */ + diff --git a/board/mv_feroceon/mv_hal/twsi/mvCompVer.txt b/board/mv_feroceon/mv_hal/twsi/mvCompVer.txt new file mode 100644 index 0000000..4053116 --- /dev/null +++ b/board/mv_feroceon/mv_hal/twsi/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.5 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/twsi/mvTwsi.c b/board/mv_feroceon/mv_hal/twsi/mvTwsi.c new file mode 100644 index 0000000..d304b9c --- /dev/null +++ b/board/mv_feroceon/mv_hal/twsi/mvTwsi.c @@ -0,0 +1,1023 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "mvTwsi.h" +#include "mvTwsiSpec.h" +#include "cpu/mvCpu.h" + + +/*#define MV_DEBUG*/ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_VOID twsiIntFlgClr(MV_U8 chanNum); +static MV_BOOL twsiMainIntGet(MV_U8 chanNum); +static MV_VOID twsiAckBitSet(MV_U8 chanNum); +static MV_U32 twsiStsGet(MV_U8 chanNum); +static MV_VOID twsiReset(MV_U8 chanNum); +static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); +static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); +static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); +static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); +static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); + + +static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) +{ + if(timeout >= TWSI_TIMEOUT_VALUE) + { + DB(mvOsPrintf("%s",pString)); + return MV_TRUE; + } + return MV_FALSE; + +} +/******************************************************************************* +* mvTwsiStartBitSet - Set start bit on the bus +* +* DESCRIPTION: +* This routine sets the start bit on the TWSI bus. +* The routine first checks for interrupt flag condition, then it sets +* the start bit in the TWSI Control register. +* If the interrupt flag condition check previously was set, the function +* will clear it. +* The function then wait for the start bit to be cleared by the HW. +* Then it waits for the interrupt flag to be set and eventually, the +* TWSI status is checked to be 0x8 or 0x10(repeated start bit). +* +* INPUT: +* chanNum - TWSI channel. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK is start bit was set successfuly on the bus. +* MV_FAIL if interrupt flag was set before setting start bit. +* +*******************************************************************************/ +MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) +{ + MV_BOOL isIntFlag = MV_FALSE; + MV_U32 timeout, temp; + + DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); + /* check Int flag */ + if(twsiMainIntGet(chanNum)) + isIntFlag = MV_TRUE; + /* set start Bit */ + temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); + + /* in case that the int flag was set before i.e. repeated start bit */ + if(isIntFlag){ + DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); + twsiIntFlgClr(chanNum); + } + + /* wait for interrupt */ + timeout = 0; + while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) + return MV_TIMEOUT; + + + /* check that start bit went down */ + if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) + { + mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); + return MV_FAIL; + } + + /* check the status */ + temp = twsiStsGet(chanNum); + if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) + { + mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); + return MV_FAIL; + } + + return MV_OK; + +} + +/******************************************************************************* +* mvTwsiStopBitSet - Set stop bit on the bus +* +* DESCRIPTION: +* This routine set the stop bit on the TWSI bus. +* The function then wait for the stop bit to be cleared by the HW. +* Finally the function checks for status of 0xF8. +* +* INPUT: +* chanNum - TWSI channel +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE is stop bit was set successfuly on the bus. +* +*******************************************************************************/ +MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) +{ + MV_U32 timeout, temp; + + /* Generate stop bit */ + temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); + + twsiIntFlgClr(chanNum); + + /* wait for stop bit to come down */ + timeout = 0; + while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) + return MV_TIMEOUT; + + /* check that the stop bit went down */ + if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) + { + mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); + return MV_FAIL; + } + + /* check the status */ + temp = twsiStsGet(chanNum); + if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ + mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); + return MV_FAIL; + } + + return MV_OK; +} + +/******************************************************************************* +* twsiMainIntGet - Get twsi bit from main Interrupt cause. +* +* DESCRIPTION: +* This routine returns the twsi interrupt flag value. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL twsiMainIntGet(MV_U8 chanNum) +{ + MV_U32 temp; + + /* get the int flag bit */ + + temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG(chanNum)); + if (temp & (TWSI_CPU_MAIN_INT_BIT(chanNum))) + return MV_TRUE; + + return MV_FALSE; +} +/******************************************************************************* +* twsiIntFlgClr - Clear Interrupt flag. +* +* DESCRIPTION: +* This routine clears the interrupt flag. It does NOT poll the interrupt +* to make sure the clear. After clearing the interrupt, it waits for at +* least 1 miliseconds. +* +* INPUT: +* chanNum - TWSI channel +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID twsiIntFlgClr(MV_U8 chanNum) +{ + MV_U32 temp; + + /* wait for 1 mili to prevent TWSI register write after write problems */ + mvOsDelay(1); + /* clear the int flag bit */ + temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); + + /* wait for 1 mili sec for the clear to take effect */ + mvOsDelay(1); + + return; +} + + +/******************************************************************************* +* twsiAckBitSet - Set acknowledge bit on the bus +* +* DESCRIPTION: +* This routine set the acknowledge bit on the TWSI bus. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID twsiAckBitSet(MV_U8 chanNum) +{ + MV_U32 temp; + + /*Set the Ack bit */ + temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); + + /* Add delay of 1ms */ + mvOsDelay(1); + return; +} + + +/******************************************************************************* +* twsiInit - Initialize TWSI interface +* +* DESCRIPTION: +* This routine: +* -Reset the TWSI. +* -Initialize the TWSI clock baud rate according to given frequancy +* parameter based on Tclk frequancy and enables TWSI slave. +* -Set the ack bit. +* -Assign the TWSI slave address according to the TWSI address Type. +* +* +* INPUT: +* chanNum - TWSI channel +* frequancy - TWSI frequancy in KHz. (up to 100KHZ) +* +* OUTPUT: +* None. +* +* RETURN: +* Actual frequancy. +* +*******************************************************************************/ +MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) +{ + MV_U32 n,m,freq,margin,minMargin = 0xffffffff; + MV_U32 power; + MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; + + if(frequancy > 100000) + { + mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); + } + + DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); + /* Calucalte N and M for the TWSI clock baud rate */ + for(n = 0 ; n < 8 ; n++) + { + for(m = 0 ; m < 16 ; m++) + { + power = 2 << n; /* power = 2^(n+1) */ + freq = Tclk/(10*(m+1)*power); + margin = MV_ABS(frequancy - freq); + if(margin < minMargin) + { + minMargin = margin; + actualFreq = freq; + actualN = n; + actualM = m; + } + } + } + DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); + /* Reset the TWSI logic */ + twsiReset(chanNum); + + /* Set the baud rate */ + val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); + MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); + + /* Enable the TWSI and slave */ + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); + + /* set the TWSI slave address */ + if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ + { + /* writing the 2 most significant bits of the 10 bit address*/ + val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); + /* bits 7:3 must be 0x11110 */ + val |= TWSI_SLAVE_ADDR_10BIT_CONST; + /* set GCE bit */ + if(generalCallEnable) + val |= TWSI_SLAVE_ADDR_GCE_ENA; + /* write slave address */ + MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); + + /* writing the 8 least significant bits of the 10 bit address*/ + val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; + MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); + } + else /*7 bit address*/ + { + /* set the 7 Bits address */ + MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); + val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; + MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); + } + + /* unmask twsi int */ + val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); + /* Add delay of 1ms */ + mvOsDelay(1); + + return actualFreq; +} + + +/******************************************************************************* +* twsiStsGet - Get the TWSI status value. +* +* DESCRIPTION: +* This routine returns the TWSI status value. +* +* INPUT: +* chanNum - TWSI channel +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 - the TWSI status. +* +*******************************************************************************/ +static MV_U32 twsiStsGet(MV_U8 chanNum) +{ + return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); + +} + +/******************************************************************************* +* twsiReset - Reset the TWSI. +* +* DESCRIPTION: +* Resets the TWSI logic and sets all TWSI registers to their reset values. +* +* INPUT: +* chanNum - TWSI channel +* +* OUTPUT: +* None. +* +* RETURN: +* None +* +*******************************************************************************/ +static MV_VOID twsiReset(MV_U8 chanNum) +{ + /* Reset the TWSI logic */ + MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); + + /* wait for 2 mili sec */ + mvOsDelay(2); + + return; +} + + + + +/******************************* POLICY ****************************************/ + + + +/******************************************************************************* +* mvTwsiAddrSet - Set address on TWSI bus. +* +* DESCRIPTION: +* This function Set address (7 or 10 Bit address) on the Twsi Bus. +* +* INPUT: +* chanNum - TWSI channel +* pTwsiAddr - twsi address. +* command - read / write . +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - if setting the address completed succesfully. +* MV_FAIL otherwmise. +* +*******************************************************************************/ +MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) +{ + DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ + pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); + /* 10 Bit address */ + if(pTwsiAddr->type == ADDR10_BIT) + { + return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); + } + /* 7 Bit address */ + else + { + return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); + } + +} + +/******************************************************************************* +* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. +* +* DESCRIPTION: +* There are two address phases: +* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB +* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit +* to the Data register. Then it clears interrupt flag which drive +* the address on the TWSI bus. The function then waits for interrupt +* flag to be active and status 0x18 (write) or 0x40 (read) to be set. +* 2) write the rest of 10-bit address to data register and clears +* interrupt flag which drive the address on the TWSI bus. The +* function then waits for interrupt flag to be active and status +* 0xD0 (write) or 0xE0 (read) to be set. +* +* INPUT: +* chanNum - TWSI channel +* deviceAddress - twsi address. +* command - read / write . +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - if setting the address completed succesfully. +* MV_FAIL otherwmise. +* +*******************************************************************************/ +static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) +{ + MV_U32 val,timeout; + + /* writing the 2 most significant bits of the 10 bit address*/ + val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); + /* bits 7:3 must be 0x11110 */ + val |= TWSI_DATA_ADDR_10BIT_CONST; + /* set command */ + val |= command; + MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); + /* WA add a delay */ + mvOsDelay(1); + + /* clear Int flag */ + twsiIntFlgClr(chanNum); + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) + return MV_TIMEOUT; + + /* check the status */ + val = twsiStsGet(chanNum); + if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || + ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) + { + mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ + ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); + return MV_FAIL; + } + + /* set 8 LSB of the address */ + val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; + MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); + + /* clear Int flag */ + twsiIntFlgClr(chanNum); + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) + return MV_TIMEOUT; + + /* check the status */ + val = twsiStsGet(chanNum); + if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || + ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) + { + mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ + ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); + return MV_FAIL; + } + + return MV_OK; +} + +/******************************************************************************* +* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. +* +* DESCRIPTION: +* This function writes 7 bit address plus a write or read bit to the +* Data register. Then it clears interrupt flag which drive the address on +* the TWSI bus. The function then waits for interrupt flag to be active +* and status 0x18 (write) or 0x40 (read) to be set. +* +* INPUT: +* chanNum - TWSI channel +* deviceAddress - twsi address. +* command - read / write . +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - if setting the address completed succesfully. +* MV_FAIL otherwmise. +* +*******************************************************************************/ +static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) +{ + MV_U32 val,timeout; + + /* set the address */ + val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; + /* set command */ + val |= command; + MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); + /* WA add a delay */ + mvOsDelay(1); + + /* clear Int flag */ + twsiIntFlgClr(chanNum); + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) + return MV_TIMEOUT; + + /* check the status */ + val = twsiStsGet(chanNum); + if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || + ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) + { + /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't + want error messeges in case DIMM doesn't exist. */ + DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ + ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); + return MV_FAIL; + } + + return MV_OK; +} + +/******************************************************************************* +* twsiDataWrite - Trnasmit a data block over TWSI bus. +* +* DESCRIPTION: +* This function writes a given data block to TWSI bus in 8 bit granularity. +* first The function waits for interrupt flag to be active then +* For each 8-bit data: +* The function writes data to data register. It then clears +* interrupt flag which drives the data on the TWSI bus. +* The function then waits for interrupt flag to be active and status +* 0x28 to be set. +* +* +* INPUT: +* chanNum - TWSI channel +* pBlock - Data block. +* blockSize - number of chars in pBlock. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - if transmiting the block completed succesfully, +* MV_BAD_PARAM - if pBlock is NULL, +* MV_FAIL otherwmise. +* +*******************************************************************************/ +static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) +{ + MV_U32 timeout, temp, blockSizeWr = blockSize; + + if(NULL == pBlock) + return MV_BAD_PARAM; + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) + return MV_TIMEOUT; + + while(blockSizeWr) + { + /* write the data*/ + MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); + DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ + blockSize - blockSizeWr, *pBlock)); + pBlock++; + blockSizeWr--; + + twsiIntFlgClr(chanNum); + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) + return MV_TIMEOUT; + + /* check the status */ + temp = twsiStsGet(chanNum); + if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) + { + mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); + return MV_FAIL; + } + + } + + return MV_OK; +} + +/******************************************************************************* +* twsiDataReceive - Receive data block from TWSI bus. +* +* DESCRIPTION: +* This function receive data block from TWSI bus in 8bit granularity +* into pBlock buffer. +* first The function waits for interrupt flag to be active then +* For each 8-bit data: +* It clears the interrupt flag which allows the next data to be +* received from TWSI bus. +* The function waits for interrupt flag to be active, +* and status reg is 0x50. +* Then the function reads data from data register, and copies it to +* the given buffer. +* +* INPUT: +* chanNum - TWSI channel +* blockSize - number of bytes to read. +* +* OUTPUT: +* pBlock - Data block. +* +* RETURN: +* MV_OK - if receive transaction completed succesfully, +* MV_BAD_PARAM - if pBlock is NULL, +* MV_FAIL otherwmise. +* +*******************************************************************************/ +static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) +{ + MV_U32 timeout, temp, blockSizeRd = blockSize; + if(NULL == pBlock) + return MV_BAD_PARAM; + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) + return MV_TIMEOUT; + + while(blockSizeRd) + { + if(blockSizeRd == 1) + { + /* clear ack and Int flag */ + temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + temp &= ~(TWSI_CONTROL_ACK); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); + } + twsiIntFlgClr(chanNum); + /* wait for Int to be Set */ + timeout = 0; + while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) + return MV_TIMEOUT; + + /* check the status */ + temp = twsiStsGet(chanNum); + if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) + { + mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); + return MV_FAIL; + } + else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) + { + mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); + return MV_FAIL; + } + + /* read the data*/ + *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); + DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ + blockSize - blockSizeRd,*pBlock)); + pBlock++; + blockSizeRd--; + } + + return MV_OK; +} + + + +/******************************************************************************* +* twsiTargetOffsSet - Set TWST target offset on TWSI bus. +* +* DESCRIPTION: +* The function support TWSI targets that have inside address space (for +* example EEPROMs). The function: +* 1) Convert the given offset into pBlock and size. +* in case the offset should be set to a TWSI slave which support +* more then 256 bytes offset, the offset setting will be done +* in 2 transactions. +* 2) Use twsiDataTransmit to place those on the bus. +* +* INPUT: +* chanNum - TWSI channel +* offset - offset to be set on the EEPROM device. +* moreThen256 - whether the EEPROM device support more then 256 byte offset. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - if setting the offset completed succesfully. +* MV_FAIL otherwmise. +* +*******************************************************************************/ +static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) +{ + MV_U8 offBlock[2]; + MV_U32 offSize; + + if(moreThen256 == MV_TRUE) + { + offBlock[0] = (offset >> 8) & 0xff; + offBlock[1] = offset & 0xff; + offSize = 2; + } + else + { + offBlock[0] = offset & 0xff; + offSize = 1; + } + DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ + offSize,offBlock[0],offBlock[1])); + return twsiDataTransmit(chanNum, offBlock, offSize); + +} + +/******************************************************************************* +* mvTwsiRead - Read data block from a TWSI Slave. +* +* DESCRIPTION: +* The function calls the following functions: +* -) mvTwsiStartBitSet(); +* if(EEPROM device) +* -) mvTwsiAddrSet(w); +* -) twsiTargetOffsSet(); +* -) mvTwsiStartBitSet(); +* -) mvTwsiAddrSet(r); +* -) twsiDataReceive(); +* -) mvTwsiStopBitSet(); +* +* INPUT: +* chanNum - TWSI channel +* pTwsiSlave - Twsi Slave structure. +* blockSize - number of bytes to read. +* +* OUTPUT: +* pBlock - Data block. +* +* RETURN: +* MV_OK - if EEPROM read transaction completed succesfully, +* MV_BAD_PARAM - if pBlock is NULL, +* MV_FAIL otherwmise. +* +*******************************************************************************/ +MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) +{ + if((NULL == pBlock) || (NULL == pTwsiSlave)) + return MV_BAD_PARAM; + if(MV_OK != mvTwsiStartBitSet(chanNum)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); + + /* in case offset exsist (i.e. eeprom ) */ + if(MV_TRUE == pTwsiSlave->validOffset) + { + if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); + if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); + if(MV_OK != mvTwsiStartBitSet(chanNum)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); + } + if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); + if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); + + if(MV_OK != mvTwsiStopBitSet(chanNum)) + { + return MV_FAIL; + } + + twsiAckBitSet(chanNum); + + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); + + return MV_OK; +} + +/******************************************************************************* +* mvTwsiWrite - Write data block to a TWSI Slave. +* +* DESCRIPTION: +* The function calls the following functions: +* -) mvTwsiStartBitSet(); +* -) mvTwsiAddrSet(); +* -)if(EEPROM device) +* -) twsiTargetOffsSet(); +* -) twsiDataTransmit(); +* -) mvTwsiStopBitSet(); +* +* INPUT: +* chanNum - TWSI channel +* eepromAddress - eeprom address. +* blockSize - number of bytes to write. +* pBlock - Data block. +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK - if EEPROM read transaction completed succesfully. +* MV_BAD_PARAM - if pBlock is NULL, +* MV_FAIL otherwmise. +* +* NOTE: Part of the EEPROM, required that the offset will be aligned to the +* max write burst supported. +*******************************************************************************/ +MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) +{ + if((NULL == pBlock) || (NULL == pTwsiSlave)) + return MV_BAD_PARAM; + + if(MV_OK != mvTwsiStartBitSet(chanNum)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + + DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); + if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); + + /* in case offset exsist (i.e. eeprom ) */ + if(MV_TRUE == pTwsiSlave->validOffset) + { + if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); + } + if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); + if(MV_OK != mvTwsiStopBitSet(chanNum)) + { + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); + + return MV_OK; +} diff --git a/board/mv_feroceon/mv_hal/twsi/mvTwsi.h b/board/mv_feroceon/mv_hal/twsi/mvTwsi.h new file mode 100644 index 0000000..bd5b6d0 --- /dev/null +++ b/board/mv_feroceon/mv_hal/twsi/mvTwsi.h @@ -0,0 +1,121 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvTwsiH +#define __INCmvTwsiH + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* need to update this includes */ +#include "twsi/mvTwsiSpec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + + +/* The TWSI interface supports both 7-bit and 10-bit addressing. */ +/* This enumerator describes addressing type. */ +typedef enum _mvTwsiAddrType +{ + ADDR7_BIT, /* 7 bit address */ + ADDR10_BIT /* 10 bit address */ +}MV_TWSI_ADDR_TYPE; + +/* This structure describes TWSI address. */ +typedef struct _mvTwsiAddr +{ + MV_U32 address; /* address */ + MV_TWSI_ADDR_TYPE type; /* Address type */ +}MV_TWSI_ADDR; + +/* This structure describes a TWSI slave. */ +typedef struct _mvTwsiSlave +{ + MV_TWSI_ADDR slaveAddr; + MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ + MV_U32 offset; /* offset in the slave. */ + MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ +}MV_TWSI_SLAVE; + +/* This enumerator describes TWSI protocol commands. */ +typedef enum _mvTwsiCmd +{ + MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ + MV_TWSI_READ /* TWSI read command - 1 according to spec */ +}MV_TWSI_CMD; + +MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); +MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); +MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); + +MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); +MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); +MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvTwsiH */ + diff --git a/board/mv_feroceon/mv_hal/twsi/mvTwsiEeprom.S b/board/mv_feroceon/mv_hal/twsi/mvTwsiEeprom.S new file mode 100644 index 0000000..9d81ef2 --- /dev/null +++ b/board/mv_feroceon/mv_hal/twsi/mvTwsiEeprom.S @@ -0,0 +1,457 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#define MV_ASMLANGUAGE +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "mvOsAsm.h" +#include "mvTwsiSpec.h" +#include "mvSysHwConfig.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "mvCommon.h" + +#define I2C_CH MV_BOARD_DIMM_I2C_CHANNEL + +/* defines */ +/* defines */ + + + .data + .global _i2cInit + .global _i2cRead + + .text + +/******************************************************************************* +* _i2cInit - Initialize TWSI interface +* +* DESCRIPTION: +* The function performs TWSI interface initialization. It resets the +* TWSI state machine and initialize its clock to 100KHz assuming Tclock +* of 133MHz. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +_i2cInit: + mov r9, LR /* Save link register */ + mov r0, #0 /* Make sure r0 is zero */ + + /* Reset the i2c Mechanism first */ + MV_REG_WRITE_ASM (r0, r1, TWSI_SOFT_RESET_REG(I2C_CH)) + + bl _twsiDelay + bl _twsiDelay + + /* Initializing the I2C mechanism. Assuming Tclock frequency */ + /* of 166MHz. The I2C frequency in that case will be 100KHz. */ + /* For this settings, M = 9 and N = 3. Set the baud-rate with the */ + /* value of 0x2b (freq of ==> 100KHz */ + /* see spec for more details about the calculation of this value) */ + mov r6, #(9 << 3 | 3) + MV_REG_WRITE_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + + /* Enable the I2C master */ + /* Enable TWSI interrupt in main mask reg */ + mov r6, #0xC4 + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + + /* Let the slow TWSI machine get used to the idea that it is enabled */ + bl _twsiDelay + + + mov PC, r9 /* r9 is saved link register */ + +/******************************************************************************* +* _twsiDelay - Perform delay. +* +* DESCRIPTION: +* The function performs a delay to enable TWSI logic to stable. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +_twsiDelay: + mov r10, #0x100000 /*was 0x400*/ + +_twsiDelayLoop: + subs r10, r10, #1 + bne _twsiDelayLoop + + mov PC, LR + +/******************************************************************************* +* _i2cRead - Read byte from I2C EEPROM device. +* +* DESCRIPTION: +* The function returns a byte from I2C EEPROM device. +* The EEPROM device is 7-bit address type. +* +* INPUT: +* r4 has the DIMM0 base address with shift 1 bit to the left +* r7 has the EEPROM offset +* +* OUTPUT: +* None. +* +* RETURN: +* r4 returns '0' if address can not be read. +* r7 has byte value in case read is successful. +* +*******************************************************************************/ +_i2cRead: + mov r9, LR /* Save link register */ + + /* Transmit the device address and desired offset within the EEPROM. */ + + /* Generate Start Bit */ + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + orr r6, r6, #TWSI_CONTROL_START_BIT + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + + /* Wait for the interrupt flag (bit3) to be set */ + mov r10, #0x50000 +loop_1: + subs r10, r10, #1 + beq loop_1_timeout +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_1 + +loop_1_timeout: + + /* Wait for the start bit to be reset by HW */ + mov r10, #0x50000 +loop_2: + subs r10, r10, #1 + beq loop_2_timeout + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + tst r6, #TWSI_CONTROL_START_BIT + bne loop_2 + +loop_2_timeout: + + /* Wait for the status TWSI_START_CONDITION_TRA = 0x8 */ + mov r10, #0x50000 +loop_3: + subs r10, r10, #1 + beq loop_3_timeout + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x08 + bne loop_3 + +loop_3_timeout: + + /* writing the address of (DIMM0/1 << 1) with write indication */ + mov r6, r4, LSL #1 /* Write operation address bit 0 must be 0 */ + MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) + + bl _twsiDelay + /* Clear the interrupt flag */ + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Waiting for the interrupt flag to be set which means that the + address has been transmitted */ +loop_4: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_4 /* if tst = 0, then the bit is not set yet */ + + /* Wait for status TWSI_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC = 0x18 */ + mov r10, #0x50000 /* Set r10 to 0x50000 =~ 328,000 */ + +loop_5: + subs r10, r10, #1 /* timeout count down */ + bne testStatus + mov r4, #0 /* r4 = 0 -> operation failed */ + b exit_i2cRead /* Exit if timeout (No DIMM) */ + +testStatus: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x18 + bne loop_5 + + + /* check if the offset is bigger than 256 byte*/ + tst r7, #0x80000000 + bne great_than_256 + + /* Write the offset to be read from the DIMM EEPROM */ + MV_REG_WRITE_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) + + b after_offset + +great_than_256: + mov r10, r7, LSR #8 + and r10, r10, #0xff + /* Write the offset0 to be read from the EEPROM */ + MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) + + /* Clear the interrupt flag ==> signaling that the address can now + be transmited */ + + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the interrupt to be set again ==> address has transmited */ +loop_6_1: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_6_1 + + /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ +loop_7_1: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x28 + bne loop_7_1 + + + mov r10, r7 + and r10, r10, #0xff + /* Write the offset1 to be read from the EEPROM */ + MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) + + + +after_offset: + + /* Clear the interrupt flag ==> signaling that the address can now + be transmited */ + + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the interrupt to be set again ==> address has transmited */ +loop_6: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_6 + + /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ +loop_7: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x28 + bne loop_7 + + /* Retransmit the device address with read indication to get the data */ + + /* generate a repeated start bit */ + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + orr r6, r6, #TWSI_CONTROL_START_BIT + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + + + /* Clear the interrupt flag ==> the start bit will be transmitted. */ + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the interrupt flag (bit3) to be set */ +loop_9: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_9 + + /* Wait for the start bit to be reset by HW */ +loop_8: + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + tst r6, #TWSI_CONTROL_START_BIT + bne loop_8 + + /* Wait for status TWSI_REPEATED_START_CONDITION_TRA = 0x10 */ +loop_10: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x10 + bne loop_10 + + /* Writing the address of (DIMM0<<1) with read indication (bit0 is 1) */ + mov r6, r4, LSL #1 + orr r6, r6, #1 /* Read operation address bit 0 must be 1 */ + MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) + + /* Clear the interrupt flag ==> the address will be transmitted */ + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the interrupt flag (bit3) to be set as a result of + transmitting the address. */ +loop_11: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_11 + + /* Wait for status TWSI_ADDR_PLUS_READ_BIT_TRA_ACK_REC = 0x40 */ +loop_12: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x40 + bne loop_12 + + /* Clear the interrupt flag and the Acknoledge bit */ + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #(TWSI_CONTROL_INT_FLAG_SET | TWSI_CONTROL_ACK) + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the interrupt flag (bit3) to be set */ +loop_14: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_14 + + /* Wait for status TWSI_MAS_REC_READ_DATA_ACK_NOT_TRA = 0x58 */ +loop_15: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x58 + bne loop_15 + + /* Store the data in r7. */ + MV_REG_READ_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) + + /* Generate stop bit */ + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + orr r6, r6, #TWSI_CONTROL_STOP_BIT + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + + + /* Clear the interrupt flag */ + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the stop bit to be reset by HW */ +loop_16: + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + tst r6, #TWSI_CONTROL_INT_FLAG_SET + bne loop_16 + +exit_i2cRead: + mov PC, r9 /* r9 is saved link register */ diff --git a/board/mv_feroceon/mv_hal/twsi/mvTwsiSpec.h b/board/mv_feroceon/mv_hal/twsi/mvTwsiSpec.h new file mode 100644 index 0000000..d0c2b9e --- /dev/null +++ b/board/mv_feroceon/mv_hal/twsi/mvTwsiSpec.h @@ -0,0 +1,160 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/****************************************/ +/* TWSI Registers */ +/****************************************/ +#ifndef __INCmvTwsiSpech +#define __INCmvTwsiSpech + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ +#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) + +#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 +#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 +#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) +#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 +#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 +#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 + + +#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) +#define TWSI_EXTENDED_SLAVE_OFFS 0 +#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) + + +#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) +#define TWSI_DATA_COMMAND_OFFS 0x0 +#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) +#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) +#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) +#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 +#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) +#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 +#define TWSI_DATA_ADDR_10BIT_MASK 0x300 +#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 + + +#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) +#define TWSI_CONTROL_ACK BIT2 +#define TWSI_CONTROL_INT_FLAG_SET BIT3 +#define TWSI_CONTROL_STOP_BIT BIT4 +#define TWSI_CONTROL_START_BIT BIT5 +#define TWSI_CONTROL_ENA BIT6 +#define TWSI_CONTROL_INT_ENA BIT7 + + +#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) +#define TWSI_BAUD_RATE_N_OFFS 0 +#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) +#define TWSI_BAUD_RATE_M_OFFS 3 +#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) + +#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) + +/* defines */ +#define TWSI_TIMEOUT_VALUE 0x500 + +/* TWSI status codes */ +#define TWSI_BUS_ERROR 0x00 +#define TWSI_START_CON_TRA 0x08 +#define TWSI_REPEATED_START_CON_TRA 0x10 +#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 +#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 +#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 +#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 +#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 +#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 +#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 +#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 +#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 +#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 +#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 +#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 +#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 +#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 +#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 +#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 +#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 +#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 +#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 +#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 +#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 +#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 +#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 +#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 +#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 +#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 +#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 +#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvTwsiSpech */ diff --git a/board/mv_feroceon/mv_hal/uart/mvCompVer.txt b/board/mv_feroceon/mv_hal/uart/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/uart/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/uart/mvUart.c b/board/mv_feroceon/mv_hal/uart/mvUart.c new file mode 100644 index 0000000..98c4b57 --- /dev/null +++ b/board/mv_feroceon/mv_hal/uart/mvUart.c @@ -0,0 +1,332 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + + +#include "mvUart.h" +#include "mvBoardEnvLib.h" +#include "gpp/mvGpp.h" + + +/* static variables */ +static volatile MV_UART_PORT* uartBase[MV_UART_MAX_CHAN]; +static int uart_off; + + +/******************************************************************************* +* mvUartInit - Init a uart port. +* +* DESCRIPTION: +* This routine Initialize one of the uarts ports (channels). +* It initialize the baudrate, stop bit,parity bit etc. +* +* INPUT: +* port - uart port number. +* baudDivisor - baud divisior to use for the uart port. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvUartInit(MV_U32 port, MV_U32 baudDivisor, MV_UART_PORT* base) +{ + volatile MV_UART_PORT *pUartPort; + +#if defined(MV_UART_OVER_PEX_WA) || defined(MV_UART_OVER_PCI_WA) + uartBase[port] = pUartPort = (volatile MV_UART_PORT *)(base); + return; +#else + uartBase[port] = pUartPort = (volatile MV_UART_PORT *)base; + + pUartPort->ier = 0x00; + pUartPort->lcr = LCR_DIVL_EN; /* Access baud rate */ + pUartPort->dll = baudDivisor & 0xff; /* 9600 baud */ + pUartPort->dlm = (baudDivisor >> 8) & 0xff; + pUartPort->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ + + /* Clear & enable FIFOs */ + pUartPort->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; + return; +#endif +} + +#ifdef MV78XX0 +#define UART_EXTERNAL_CONTROL_REG 0x10700 +/******************************************************************************* +* mvUartDmaInit - Init a uart port in DMA mode. +* +* DESCRIPTION: +* This routine Initialize one of the uart ports (channels) to use DMA mode +* for transmission. It initialize the baudrate, stop bit,parity bit etc. +* It also initializes IDMA channel 0 for UART transmission. +* Once DMA based UART is configured IDMA channel 0 must not be used elsewhere. +* +* INPUT: +* port - uart port number. +* baudDivisor - baud divisior to use for the uart port. +* idmaWinNum - The IDMA BAR to use for UART transfer (must be 1-3) +* srcBurstSize - the IDMA source burst size (8,16,32,64,128) +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvUartDmaInit(MV_U32 port, MV_U32 baudDivisor, MV_UART_PORT* base, + MV_U32 idmaWinNum, MV_U32 srcBurstSize) +{ + volatile MV_UART_PORT *pUartPort; + MV_U32 srcBurstLim; + + /*set the UART channel to use the IDMA*/ + MV_REG_BIT_SET(UART_EXTERNAL_CONTROL_REG, BIT0 | (BIT8 << port)); + + uartBase[port] = pUartPort = (volatile MV_UART_PORT *)base; + mvUartInit(port, baudDivisor, base); + + pUartPort->mcr = MCR_AFCE; /* Enable Auto flow control */ + /* Set IDMA BAR target to UART*/ + MV_REG_BIT_RESET(IDMA_BASE_ADDR_REG(idmaWinNum), 0xffff); + MV_REG_BIT_SET(IDMA_BASE_ADDR_REG(idmaWinNum), 0x0101); /*Set BAR to UART*/ + + /* Set IDMA0 channel to UART mode*/ + switch (srcBurstSize) + { + case 8: + srcBurstLim = ICCLR_SRC_BURST_LIM_8BYTE; + break; + case 16: + srcBurstLim = ICCLR_SRC_BURST_LIM_16BYTE; + break; + case 32: + srcBurstLim = ICCLR_SRC_BURST_LIM_32BYTE; + break; + case 64: + srcBurstLim = ICCLR_SRC_BURST_LIM_64BYTE; + break; + case 128: + srcBurstLim = ICCLR_SRC_BURST_LIM_128BYTE; + break; + default: + mvOsPrintf("mvUartDmaInit:ERR. Illegal source burst limit, \ + setting to 128B default\n"); + srcBurstLim = ICCLR_SRC_BURST_LIM_128BYTE; + break; + } + mvDmaCtrlLowSet(0, 0x18220 | srcBurstLim); /*channel control low according FS*/ + mvDmaOverrideSet(0, idmaWinNum, DMA_DST_ADDR); + return; +} + + +/******************************************************************************* +* mvUartDmaTransmit - Transmit a buffer over the UART using the IDMA. +* +* DESCRIPTION: +* This routine transmits a buffer over the UART port using IDMA0. +* +* INPUT: +* port - uart port number. +* byteCount - The total number of bytes to be transferred to the UART. +* srcAddr - The source address of the buffer to be transferred. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK. +* +*******************************************************************************/ +MV_STATUS mvUartDmaTransmit(MV_U32 port, MV_U32 byteCount, MV_U32 srcAddr) +{ + MV_U32 dstAddr, tmp; + + /* Verify IDMA 0 is not busy */ + if(mvDmaStateGet(port) != MV_IDLE) + { + mvOsPrintf("mvUartDmaTransmit: ERR. IDMA 0 busy.\n"); + return MV_ERROR; + } + + /* Verify byte count is legal, and choose either 64K mode or 16M mode */ + if(byteCount >= 0x1000000) + { + mvOsPrintf("mvUartDmaTransmit: ERR. Illegal Byte count.\n"); + return MV_ERROR; + } + else if (byteCount >= 0x10000) + { + byteCount |= BIT31; + MV_REG_BIT_SET(IDMA_CTRL_LOW_REG(0), BIT31); + } + else + MV_REG_BIT_RESET(IDMA_CTRL_LOW_REG(0), BIT31); + + /* Calculate UART destination address from assigned BAR*/ + tmp = MV_REG_READ(IDMA_CTRL_LOW_REG(0)); + tmp = (tmp >> 23) & 0x3; /* Extract the destination override window number*/ + + /* Check that destination BAR is configured and calculate destination address*/ + if((MV_REG_READ(IDMA_BASE_ADDR_REG(tmp)) & 0xffff) != 0x0101) + { + mvOsPrintf("mvUartDmaTransmit: ERR. IDMA UART BAR isn't configured.\n"); + return MV_ERROR; + } + else + dstAddr = (MV_REG_READ(IDMA_BASE_ADDR_REG(tmp)) & 0xffff0000) | (port << 8); + + /* Start transfer */ + if(mvDmaTransfer(0, srcAddr, dstAddr, byteCount, 0x0) == MV_OK) + return MV_OK; + else + return MV_ERROR; +} +#endif // MV78XX0 +/******************************************************************************* +* mvUartPutc - Send char to the uart port. +* +* DESCRIPTION: +* This routine puts one charachetr on one of the uart ports. +* +* INPUT: +* port - uart port number. +* c - character. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvUartPutc(MV_U32 port, MV_U8 c) +{ + volatile MV_UART_PORT *pUartPort = uartBase[port]; + +#if defined(CONFIG_BUFFALO_PLATFORM) + if (uart_off && port == 0) + return; +#endif + + while ((pUartPort->lsr & LSR_THRE) == 0) ; + pUartPort->thr = c; + return; +} + +/******************************************************************************* +* mvUartGetc - Get char from uart port. +* +* DESCRIPTION: +* This routine gets one charachetr from one of the uart ports. +* +* INPUT: +* port - uart port number. +* +* OUTPUT: +* None. +* +* RETURN: +* carachter from the uart port. +* +*******************************************************************************/ +MV_U8 mvUartGetc(MV_U32 port) +{ + volatile MV_UART_PORT *pUartPort = uartBase[port]; + +#if defined(CONFIG_BUFFALO_PLATFORM) + if (uart_off && port == 0) + return 0; +#endif + + while ((pUartPort->lsr & LSR_DR) == 0) ; + return (pUartPort->rbr); +} + +/******************************************************************************* +* mvUartTstc - test for char in uart port. +* +* DESCRIPTION: +* This routine heck if a charachter is ready to be read from one of the +* the uart ports. +* +* INPUT: +* port - uart port number. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_BOOL mvUartTstc(MV_U32 port) +{ + volatile MV_UART_PORT *pUartPort = uartBase[port]; + return ((pUartPort->lsr & LSR_DR) != 0); +} diff --git a/board/mv_feroceon/mv_hal/uart/mvUart.h b/board/mv_feroceon/mv_hal/uart/mvUart.h new file mode 100644 index 0000000..39f9e40 --- /dev/null +++ b/board/mv_feroceon/mv_hal/uart/mvUart.h @@ -0,0 +1,164 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __NS16550_H__ +#define __NS16550_H__ + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#ifdef MV78XX0 +#include "idma/mvIdma.h" +#include "ctrlEnv/sys/mvSysIdma.h" +#endif +/* This structure describes the registers offsets for one UART port(channel) */ +typedef struct mvUartPort +{ + MV_U8 rbr; /* 0 = 0-3*/ + MV_U8 pad1[3]; + + MV_U8 ier; /* 1 = 4-7*/ + MV_U8 pad2[3]; + + MV_U8 fcr; /* 2 = 8-b*/ + MV_U8 pad3[3]; + + MV_U8 lcr; /* 3 = c-f*/ + MV_U8 pad4[3]; + + MV_U8 mcr; /* 4 = 10-13*/ + MV_U8 pad5[3]; + + MV_U8 lsr; /* 5 = 14-17*/ + MV_U8 pad6[3]; + + MV_U8 msr; /* 6 =18-1b*/ + MV_U8 pad7[3]; + + MV_U8 scr; /* 7 =1c-1f*/ + MV_U8 pad8[3]; +} MV_UART_PORT; + +#if defined(MV_UART_OVER_PEX_WA) || defined(MV_UART_OVER_PCI_WA) +#define mvUartBase(port) \ + ((MV_UART_PORT *)(0xF2000000 + MV_UART_CHAN_BASE(port))) +#else +#define mvUartBase(port) \ + ((MV_UART_PORT *)(INTER_REGS_BASE + MV_UART_CHAN_BASE(port))) +#endif + +/* aliases - for registers which has the same offsets */ +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +/* registers feilds */ +#define FCR_FIFO_EN BIT0 /* fifo enable*/ +#define FCR_RXSR BIT1 /* reciever soft reset*/ +#define FCR_TXSR BIT2 /* transmitter soft reset*/ + +#define MCR_RTS BIT1 /* ready to send */ +#define MCR_AFCE BIT5 /* Auto Flow Control Enable */ + +#define LCR_WLS_OFFS 0 +#define LCR_WLS_MASK 0x3 << LCR_WLS_OFFS /* character length mask */ +#define LCR_WLS_5 0x0 << LCR_WLS_OFFS /* 5 bit character length */ +#define LCR_WLS_6 0x1 << LCR_WLS_OFFS /* 6 bit character length */ +#define LCR_WLS_7 0x2 << LCR_WLS_OFFS /* 7 bit character length */ +#define LCR_WLS_8 0x3 << LCR_WLS_OFFS /* 8 bit character length */ +#define LCR_STP_OFFS 2 +#define LCR_1_STB 0x0 << LCR_STP_OFFS /* Number of stop Bits */ +#define LCR_2_STB 0x1 << LCR_STP_OFFS /* Number of stop Bits */ +#define LCR_PEN 0x8 /* Parity eneble*/ +#define LCR_PS_OFFS 4 +#define LCR_EPS 0x1 << LCR_PS_OFFS /* Even Parity Select*/ +#define LCR_OPS 0x0 << LCR_PS_OFFS /* Odd Parity Select*/ +#define LCR_SBRK_OFFS 0x6 +#define LCR_SBRK 0x1 << LCR_SBRK_OFFS /* Set Break*/ +#define LCR_DIVL_OFFS 7 +#define LCR_DIVL_EN 0x1 << LCR_DIVL_OFFS /* Divisior latch enable*/ + +#define LSR_DR BIT0 /* Data ready */ +#define LSR_OE BIT1 /* Overrun */ +#define LSR_PE BIT2 /* Parity error */ +#define LSR_FE BIT3 /* Framing error */ +#define LSR_BI BIT4 /* Break */ +#define LSR_THRE BIT5 /* Xmit holding register empty */ +#define LSR_TEMT BIT6 /* Xmitter empty */ +#define LSR_ERR BIT7 /* Error */ + +/* useful defaults for LCR*/ +#define LCR_8N1 LCR_WLS_8 | LCR_1_STB + + +/* APIs */ +MV_VOID mvUartPutc(MV_U32 port, MV_U8 c); +MV_U8 mvUartGetc(MV_U32 port); +MV_BOOL mvUartTstc(MV_U32 port); +MV_VOID mvUartInit(MV_U32 port, MV_U32 baudDivisor, MV_UART_PORT* base); + +#endif + diff --git a/board/mv_feroceon/mv_hal/uart/mvUartRegs.h b/board/mv_feroceon/mv_hal/uart/mvUartRegs.h new file mode 100644 index 0000000..0574410 --- /dev/null +++ b/board/mv_feroceon/mv_hal/uart/mvUartRegs.h @@ -0,0 +1,72 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvUartRegsH +#define __INCmvUartRegsH + +/* registers offsets */ + +#define UART_EXTERNAL_CONTROL_REG 0x10700 + +#endif /* #ifndef __INCmvUartRegsH */ diff --git a/board/mv_feroceon/mv_hal/usb/api/mvUsbCh9.h b/board/mv_feroceon/mv_hal/usb/api/mvUsbCh9.h new file mode 100644 index 0000000..8d4d263 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/api/mvUsbCh9.h @@ -0,0 +1,124 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#ifndef __mvUsbCh9_h__ +#define __mvUsbCh9_h__ + +#include "usb/api/mvUsbTypes.h" +/*----------------------------------------------------------------** +** Chapter 9.4 Standard Device Requests -- all devices ** +** See Table 9-3 p. 250 of USB 2.0 spec for combinations ** +** of request type bitfields with requests, WVALUE, WINDEX etc. ** +**----------------------------------------------------------------*/ +#define REQ_RECIP_MASK 0x1f +#define REQ_RECIP_DEVICE 0x00 +#define REQ_RECIP_INTERFACE 0x01 +#define REQ_RECIP_ENDPOINT 0x02 +#define REQ_RECIP_OTHER 0x03 + +/* Also for class requests set the following bit */ +#define REQ_TYPE_OFFSET 5 +#define REQ_TYPE_MASK (0x03 << REQ_TYPE_OFFSET) +#define REQ_TYPE_STANDARD (0x00 << REQ_TYPE_OFFSET) +#define REQ_TYPE_CLASS (0x01 << REQ_TYPE_OFFSET) +#define REQ_TYPE_VENDOR (0x02 << REQ_TYPE_OFFSET) +#define REQ_TYPE_RESERVED (0x03 << REQ_TYPE_OFFSET) + +/* Combine one of the 3 above with one of the following 2 */ +#define REQ_DIR_OFFSET 7 +#define REQ_DIR_IN (1 << REQ_DIR_OFFSET) +#define REQ_DIR_OUT (0 << REQ_DIR_OFFSET) + +/* Standard USB requests, see Chapter 9 */ +#define REQ_GET_STATUS 0 +#define REQ_CLEAR_FEATURE 1 +#define REQ_SET_FEATURE 3 +#define REQ_SET_ADDRESS 5 +#define REQ_GET_DESCRIPTOR 6 +#define REQ_SET_DESCRIPTOR 7 +#define REQ_GET_CONFIGURATION 8 +#define REQ_SET_CONFIGURATION 9 +#define REQ_GET_INTERFACE 10 +#define REQ_SET_INTERFACE 11 +#define REQ_SYNCH_FRAME 12 + +#define DESC_TYPE_DEVICE 0x1 +#define DESC_TYPE_CONFIG 0x2 +#define DESC_TYPE_STRING 0x3 +#define DESC_TYPE_INTERFACE 0x4 +#define DESC_TYPE_ENDPOINT 0x5 +#define DESC_TYPE_QUALIFIER 0x6 +#define DESC_TYPE_OTHER_SPEED 0x7 +#define DESC_TYPE_INTF_POWER 0x8 +#define DESC_TYPE_OTG 0x9 + +/******************************************************************* +** +** Values specific to CLEAR FEATURE commands (must go to common.h later) +*/ + +#define ENDPOINT_HALT 0 +#define DEVICE_SELF_POWERED 0 +#define DEVICE_REMOTE_WAKEUP 1 +#define DEVICE_TEST_MODE 2 + + +/* States of device instances on the device list */ + +/* initial device state */ +#define DEVSTATE_INITIAL 0x00 + +/* device descriptor [0..7]*/ +#define DEVSTATE_DEVDESC8 0x01 + +/* address set */ +#define DEVSTATE_ADDR_SET 0x02 + +/* full device descriptor */ +#define DEVSTATE_DEV_DESC 0x03 + +/* config descriptor [0..7] */ +#define DEVSTATE_GET_CFG9 0x04 + +/* config set */ +#define DEVSTATE_SET_CFG 0x05 + +/* full config desc. read in */ +#define DEVSTATE_CFG_READ 0x06 + +/* application callbacks */ +#define DEVSTATE_APP_CALL 0x07 + +/* Select interface done */ +#define DEVSTATE_SET_INTF 0x08 + +#define DEVSTATE_ENUM_OK 0x09 + +#define DEVSTATE_CHK_OTG 0x0A + +/* Event codes for attach/detach etc. callback */ +#define USB_ATTACH_EVENT 1 /* device attach */ +#define USB_DETACH_EVENT 2 /* device detach */ +#define USB_CONFIG_EVENT 3 /* device reconfigured */ +#define USB_INTF_EVENT 4 /* device interface selected */ + +#endif /* __mvUsbCh9_h__ */ + +/* EOF */ diff --git a/board/mv_feroceon/mv_hal/usb/api/mvUsbDebug.h b/board/mv_feroceon/mv_hal/usb/api/mvUsbDebug.h new file mode 100644 index 0000000..e663b45 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/api/mvUsbDebug.h @@ -0,0 +1,109 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#ifndef __mvUsbDebug_h__ +#define __mvUsbDebug_h__ + +#include "mvUsbTypes.h" + +#define MV_USB_RT_DEBUG + +/************************************************************ +The following array is used to make a run time trace route +inside the USB stack. +*************************************************************/ + +#define ARC_DEBUG_FLAG_ANY 0x00000000 + +#define ARC_DEBUG_FLAG_TRACE 0x00000001 +#define ARC_DEBUG_FLAG_CTRL 0x00000002 +#define ARC_DEBUG_FLAG_RX 0x00000004 +#define ARC_DEBUG_FLAG_TX 0x00000008 +#define ARC_DEBUG_FLAG_STALL 0x00000010 +#define ARC_DEBUG_FLAG_STATUS 0x00000020 +#define ARC_DEBUG_FLAG_TRANSFER 0x00000040 +#define ARC_DEBUG_FLAG_INIT 0x00000080 +#define ARC_DEBUG_FLAG_ISR 0x00000100 +#define ARC_DEBUG_FLAG_ERROR 0x00000200 +#define ARC_DEBUG_FLAG_ADDR 0x00000400 +#define ARC_DEBUG_FLAG_DUMP 0x00000800 +#define ARC_DEBUG_FLAG_SETUP 0x00001000 +#define ARC_DEBUG_FLAG_CLASS 0x00002000 +#define ARC_DEBUG_FLAG_SPEED 0x00004000 +#define ARC_DEBUG_FLAG_RESET 0x00008000 +#define ARC_DEBUG_FLAG_SUSPEND 0x00010000 +#define ARC_DEBUG_FLAG_RESUME 0x00020000 +#define ARC_DEBUG_FLAG_EP0 0x00040000 +#define ARC_DEBUG_FLAG_EP1 0x00080000 +#define ARC_DEBUG_FLAG_STATS 0x00100000 + + +#define ARC_DEBUG_FLAG_ALL 0xffffffff + +extern uint_32 usbDebugFlags; + +#ifdef MV_USB_RT_DEBUG +# define ARC_DEBUG_CODE(flags, code) \ + if( (usbDebugFlags & (flags)) == (flags) ) \ + code +#else +# define ARC_DEBUG_CODE(flags, code) +#endif + +#if defined(MV_USB_TRACE_LOG) + +#define TRACE_ARRAY_SIZE 400 +#define MAX_STRING_SIZE 132 + +extern uint_16 DEBUG_TRACE_ARRAY_COUNTER; +extern char DEBUG_TRACE_ARRAY[TRACE_ARRAY_SIZE][MAX_STRING_SIZE]; + +#define ARC_DEBUG_TRACE(flags, format, x...) \ +{ \ + if( (usbDebugFlags & (flags)) == (flags)) \ + { \ + USB_sprintf(DEBUG_TRACE_ARRAY[DEBUG_TRACE_ARRAY_COUNTER], format, ##x); \ + DEBUG_TRACE_ARRAY_COUNTER++; \ + if(DEBUG_TRACE_ARRAY_COUNTER >= TRACE_ARRAY_SIZE) \ + {DEBUG_TRACE_ARRAY_COUNTER = 0;} \ + } \ +} + +#elif defined(MV_USB_TRACE_PRINT) + +# define ARC_DEBUG_TRACE(flags, format, x...) \ + if((usbDebugFlags & (flags)) == (flags)) \ + USB_printf(format, ##x) + +/*if trace switch is not enabled define debug log trace to empty*/ +#else +# define ARC_DEBUG_TRACE(flags, fromat, x...) +#endif + + +/************************************************************ +The following are global data structures that can be used +to copy data from stack on run time. This structure can +be analyzed at run time to see the state of various other +data structures in the memory. +*************************************************************/ + +#endif /* __mvUsbDebug_h__ */ +/* EOF */ diff --git a/board/mv_feroceon/mv_hal/usb/api/mvUsbDefs.h b/board/mv_feroceon/mv_hal/usb/api/mvUsbDefs.h new file mode 100644 index 0000000..66e2812 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/api/mvUsbDefs.h @@ -0,0 +1,139 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#ifndef __mvUsbDefs_h__ +#define __mvUsbDefs_h__ + +#include "mvUsbTypes.h" + +/* Host specific */ +#define USB_DEBOUNCE_DELAY (101) +#define USB_RESET_RECOVERY_DELAY (11) +#define USB_RESET_DELAY (60) + +/* Error codes */ +#define USB_OK (0x00) +#define USBERR_ALLOC (0x81) +#define USBERR_BAD_STATUS (0x82) +#define USBERR_CLOSED_SERVICE (0x83) +#define USBERR_OPEN_SERVICE (0x84) +#define USBERR_TRANSFER_IN_PROGRESS (0x85) +#define USBERR_ENDPOINT_STALLED (0x86) +#define USBERR_ALLOC_STATE (0x87) +#define USBERR_DRIVER_INSTALL_FAILED (0x88) +#define USBERR_DRIVER_NOT_INSTALLED (0x89) +#define USBERR_INSTALL_ISR (0x8A) +#define USBERR_INVALID_DEVICE_NUM (0x8B) +#define USBERR_ALLOC_SERVICE (0x8C) +#define USBERR_INIT_FAILED (0x8D) +#define USBERR_SHUTDOWN (0x8E) +#define USBERR_INVALID_PIPE_HANDLE (0x8F) +#define USBERR_OPEN_PIPE_FAILED (0x90) +#define USBERR_INIT_DATA (0x91) +#define USBERR_SRP_REQ_INVALID_STATE (0x92) +#define USBERR_TX_FAILED (0x93) +#define USBERR_RX_FAILED (0x94) +#define USBERR_EP_INIT_FAILED (0x95) +#define USBERR_EP_DEINIT_FAILED (0x96) +#define USBERR_TR_FAILED (0x97) +#define USBERR_BANDWIDTH_ALLOC_FAILED (0x98) +#define USBERR_INVALID_NUM_OF_ENDPOINTS (0x99) + +#define USBERR_DEVICE_NOT_FOUND (0xC0) +#define USBERR_DEVICE_BUSY (0xC1) +#define USBERR_NO_DEVICE_CLASS (0xC3) +#define USBERR_UNKNOWN_ERROR (0xC4) +#define USBERR_INVALID_BMREQ_TYPE (0xC5) +#define USBERR_GET_MEMORY_FAILED (0xC6) +#define USBERR_INVALID_MEM_TYPE (0xC7) +#define USBERR_NO_DESCRIPTOR (0xC8) +#define USBERR_NULL_CALLBACK (0xC9) +#define USBERR_NO_INTERFACE (0xCA) +#define USBERR_INVALID_CFIG_NUM (0xCB) +#define USBERR_INVALID_ANCHOR (0xCC) +#define USBERR_INVALID_REQ_TYPE (0xCD) + +/* Error Codes for lower-layer */ +#define USBERR_ALLOC_EP_QUEUE_HEAD (0xA8) +#define USBERR_ALLOC_TR (0xA9) +#define USBERR_ALLOC_DTD_BASE (0xAA) +#define USBERR_CLASS_DRIVER_INSTALL (0xAB) + + +/* Pipe Types */ +#define USB_ISOCHRONOUS_PIPE (0x01) +#define USB_INTERRUPT_PIPE (0x02) +#define USB_CONTROL_PIPE (0x03) +#define USB_BULK_PIPE (0x04) + +#define ARC_USB_STATE_UNKNOWN (0xff) +#define ARC_USB_STATE_POWERED (0x03) +#define ARC_USB_STATE_DEFAULT (0x02) +#define ARC_USB_STATE_ADDRESS (0x01) +#define ARC_USB_STATE_CONFIG (0x00) +#define ARC_USB_STATE_SUSPEND (0x80) + +#define ARC_USB_SELF_POWERED (0x01) +#define ARC_USB_REMOTE_WAKEUP (0x02) + +/* Bus Control values */ +#define ARC_USB_NO_OPERATION (0x00) +#define ARC_USB_ASSERT_BUS_RESET (0x01) +#define ARC_USB_DEASSERT_BUS_RESET (0x02) +#define ARC_USB_ASSERT_RESUME (0x03) +#define ARC_USB_DEASSERT_RESUME (0x04) +#define ARC_USB_SUSPEND_SOF (0x05) +#define ARC_USB_RESUME_SOF (0x06) + +/* possible values of XD->bStatus */ +#define ARC_USB_STATUS_IDLE (0) +#define ARC_USB_STATUS_TRANSFER_ACCEPTED (1) +#define ARC_USB_STATUS_TRANSFER_PENDING (2) +#define ARC_USB_STATUS_TRANSFER_IN_PROGRESS (3) +#define ARC_USB_STATUS_ERROR (4) +#define ARC_USB_STATUS_DISABLED (5) +#define ARC_USB_STATUS_STALLED (6) +#define ARC_USB_STATUS_TRANSFER_QUEUED (7) + +#define ARC_USB_RECV (0) +#define ARC_USB_SEND (1) + +#define ARC_USB_DEVICE_DONT_ZERO_TERMINATE (0x1) + +#define ARC_USB_SETUP_DATA_XFER_DIRECTION (0x80) + +#define ARC_USB_SPEED_FULL (0) +#define ARC_USB_SPEED_LOW (1) +#define ARC_USB_SPEED_HIGH (2) + +#define ARC_USB_MAX_PKTS_PER_UFRAME (0x6) + +/* USB 1.1 Setup Packet */ +typedef struct setup_struct { + uint_8 REQUESTTYPE; + uint_8 REQUEST; + uint_16 VALUE; + uint_16 INDEX; + uint_16 LENGTH; +} SETUP_STRUCT, _PTR_ SETUP_STRUCT_PTR; + +#endif /* __mvUsbDefs_h__ */ + +/* EOF */ diff --git a/board/mv_feroceon/mv_hal/usb/api/mvUsbDevApi.h b/board/mv_feroceon/mv_hal/usb/api/mvUsbDevApi.h new file mode 100644 index 0000000..1db2369 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/api/mvUsbDevApi.h @@ -0,0 +1,159 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#ifndef __mvUsbDevApi_h__ +#define __mvUsbDevApi_h__ + +#include "mvUsbTypes.h" +#include "mvUsbDebug.h" +#include "mvUsbDefs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + + +#define ARC_USB_MAX_ENDPOINTS (16) + +#define MAX_EP_TR_DESCRS (48) +#define MAX_XDS_FOR_TR_CALLS (32) +#define MAX_USB_DEVICES MV_USB_MAX_PORTS + +/*Assumption here is that all control endpoints are sequential 0,1,.. +if they are not you need to modify the tr_complete routine to handle that */ +#define USB_MAX_CONTROL_ENDPOINTS (1) + +#define USB_MAX_CTRL_PAYLOAD (64) + + +/* Endpoint types */ +#define ARC_USB_CONTROL_ENDPOINT (0) +#define ARC_USB_ISOCHRONOUS_ENDPOINT (1) +#define ARC_USB_BULK_ENDPOINT (2) +#define ARC_USB_INTERRUPT_ENDPOINT (3) + +/* Informational Request/Set Types */ +#define ARC_USB_STATUS_DEVICE_STATE (0x01) +#define ARC_USB_STATUS_INTERFACE (0x02) +#define ARC_USB_STATUS_ADDRESS (0x03) +#define ARC_USB_STATUS_CURRENT_CONFIG (0x04) +#define ARC_USB_STATUS_SOF_COUNT (0x05) +#define ARC_USB_STATUS_DEVICE (0x06) +#define ARC_USB_STATUS_TEST_MODE (0x07) +#define ARC_USB_FORCE_FULL_SPEED (0x08) +#define ARC_USB_PHY_LOW_POWER_SUSPEND (0x09) + +#define ARC_USB_STATUS_ENDPOINT_NUMBER_MASK (0x000F) +#define ARC_USB_STATUS_ENDPOINT_DIR_MASK (0x0080) + +#define ARC_USB_TEST_MODE_TEST_PACKET (0x0400) + +/* Available service types */ +/* Services 0 through 15 are reserved for endpoints */ +#define ARC_USB_SERVICE_EP0 (0x00) +#define ARC_USB_SERVICE_EP1 (0x01) +#define ARC_USB_SERVICE_EP2 (0x02) +#define ARC_USB_SERVICE_EP3 (0x03) +#define ARC_USB_SERVICE_BUS_RESET (0x10) +#define ARC_USB_SERVICE_SUSPEND (0x11) +#define ARC_USB_SERVICE_SOF (0x12) +#define ARC_USB_SERVICE_RESUME (0x13) +#define ARC_USB_SERVICE_SLEEP (0x14) +#define ARC_USB_SERVICE_SPEED_DETECTION (0x15) +#define ARC_USB_SERVICE_ERROR (0x16) +#define ARC_USB_SERVICE_STALL (0x17) + +typedef pointer _usb_device_handle; +typedef void (*USB_SERVICE_FUNC)(void* handle, uint_8, boolean, uint_8, + uint_8_ptr, uint_32, uint_8); + +#ifdef __cplusplus +extern "C" { +#endif + +void _usb_dci_vusb20_isr(void* handle); + +void _usb_device_set_bsp_funcs(USB_IMPORT_FUNCS* pBspFuncs); + +uint_8 _usb_device_init(uint_8 devNo, void** pHandle); + +uint_8 _usb_device_get_max_endpoint(void* handle); + +uint_8 _usb_device_get_dev_num(void* handle); + +void _usb_device_shutdown(void* handle); + +void _usb_device_stop(void* handle); +void _usb_device_start(void* handle); + +uint_8 _usb_device_init_endpoint(void* handle, uint_8 ep_num, uint_16 max_pkt_size, + uint_8 direction, uint_8 type, uint_8 flag); +uint_8 _usb_device_deinit_endpoint(void* handle, uint_8 ep_num, uint_8 direction); + +uint_8 _usb_device_recv_data(void* handle, uint_8 ep_num, uint_8* buf_ptr, uint_32 size); +uint_8 _usb_device_send_data(void* handle, uint_8 ep_num, uint_8* buf_ptr, uint_32 size); +uint_8 _usb_device_cancel_transfer(void* handle, uint_8 ep_num, uint_8 direction); +uint_8 _usb_device_get_transfer_status(void* handle, uint_8 ep_num, uint_8 direction); +void _usb_device_stall_endpoint(void* handle, uint_8 ep_num, uint_8 direction); +void _usb_device_unstall_endpoint(void* handle, uint_8 ep_num, uint_8 direction); +uint_8 _usb_device_is_endpoint_stalled(void* handle, uint_8 ep_num, uint_8 direction); +void _usb_device_assert_resume(void* handle); +uint_8 _usb_device_get_status(void* handle, uint_8 component, uint_16* status_ptr); +uint_8 _usb_device_set_status(void* handle, uint_8 component, uint_16 setting); +void _usb_device_read_setup_data(void* handle, uint_8 ep_num, uint_8* buf_ptr); + +uint_8 _usb_device_register_service(void* handle, uint_8 type, USB_SERVICE_FUNC serviceFunc); + +uint_8 _usb_device_unregister_service(void* handle, uint_8 type); + + + +/* These functions that implement USB 2.0 standard Chapter 9 Setup requests */ +void mvUsbCh9GetStatus(void* handle, boolean setup, + SETUP_STRUCT* ctrl_req); + +void mvUsbCh9ClearFeature(void* handle, boolean setup, + SETUP_STRUCT* setup_ptr); + +void mvUsbCh9SetFeature(void* handle, boolean setup, + SETUP_STRUCT* setup_ptr); + +void mvUsbCh9SetAddress(void* handle, boolean setup, + SETUP_STRUCT* setup_ptr); + +/* DEBUG Functions */ +void _usb_dci_vusb20_set_test_mode(void* handle, uint_16 testMode); + +void _usb_debug_set_flags(uint_32 flags); +uint_32 _usb_debug_get_flags(void); + +void _usb_debug_init_trace_log(void); +void _usb_debug_print_trace_log(void); + +void _usb_regs(void* usbHandle); +void _usb_status(void* usbHandle); +void _usb_stats(void* usbHandle); +void _usb_clear_stats(void* usbHandle); +void _usb_ep_status(void* usbHandle, int ep_num, int direction); + +#ifdef __cplusplus +} +#endif + +#endif /* __mvUsbDevApi_h__ */ +/* EOF */ + diff --git a/board/mv_feroceon/mv_hal/usb/api/mvUsbTypes.h b/board/mv_feroceon/mv_hal/usb/api/mvUsbTypes.h new file mode 100644 index 0000000..e99a94d --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/api/mvUsbTypes.h @@ -0,0 +1,238 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#ifndef __mvUsbTypes_h__ +#define __mvUsbTypes_h__ + +#define _PTR_ * +#define _CODE_PTR_ * + +typedef char _PTR_ char_ptr; /* signed character */ + +typedef signed char int_8, _PTR_ int_8_ptr; /* 8-bit signed integer */ +typedef unsigned char uint_8, _PTR_ uint_8_ptr; /* 8-bit signed integer */ + +typedef short int_16, _PTR_ int_16_ptr; /* 16-bit signed integer */ +typedef unsigned short uint_16, _PTR_ uint_16_ptr; /* 16-bit unsigned integer*/ + +typedef int int_32, _PTR_ int_32_ptr; /* 32-bit signed integer */ +typedef unsigned int uint_32, _PTR_ uint_32_ptr; /* 32-bit unsigned integer*/ + +typedef unsigned long boolean; /* Machine representation of a boolean */ + +typedef void _PTR_ pointer; /* Machine representation of a pointer */ + +/*--------------------------------------------------------------------------*/ +/* +** STANDARD CONSTANTS +** +** Note that if standard 'C' library files are included after types.h, +** the defines of TRUE, FALSE and NULL may sometimes conflict, as most +** standard library files do not check for previous definitions. +*/ + +#ifndef FALSE +# define FALSE ((boolean)0) +#endif + +#ifndef TRUE +# define TRUE ((boolean)!FALSE) +#endif + +#ifndef NULL +# ifdef __cplusplus +# define NULL (0) +# else +# define NULL ((pointer)0) +# endif +#endif + +#ifndef _ASSERT_ + #define ASSERT(X,Y) +#else + #define ASSERT(X,Y) if(Y) { USB_printf(X); exit(1);} +#endif + +#ifndef MIN +# define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif + +#define USB_MEM_ALIGN(n, align) ((n) + (-(n) & (align-1))) + +/* Macro for aligning the EP queue head to 32 byte boundary */ +#define USB_MEM32_ALIGN(n) USB_MEM_ALIGN(n, 32) + +/* Macro for aligning the EP queue head to 1024 byte boundary */ +#define USB_MEM1024_ALIGN(n) USB_MEM_ALIGN(n, 1024) + +/* Macro for aligning the EP queue head to 1024 byte boundary */ +#define USB_MEM2048_ALIGN(n) USB_MEM_ALIGN(n, 2048) + +#define PSP_CACHE_LINE_SIZE 32 + +#define USB_uint_16_low(x) ((x) & 0xFF) +#define USB_uint_16_high(x) (((x) >> 8) & 0xFF) + +#define USB_CACHE_ALIGN(n) USB_MEM_ALIGN(n, PSP_CACHE_LINE_SIZE) + +#ifndef INLINE +# if defined(MV_VXWORKS) +# define INLINE __inline +# else +# define INLINE inline +# endif /* MV_VXWORKS */ +#endif /* INLINE */ + +/* 16bit byte swap. For example 0x1122 -> 0x2211 */ +static INLINE uint_16 USB_BYTE_SWAP_16BIT(uint_16 value) +{ + return ( ((value & 0x00ff) << 8) | + ((value & 0xff00) >> 8) ); +} + +/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ +static INLINE uint_32 USB_BYTE_SWAP_32BIT(uint_32 value) +{ + return ( ((value & 0x000000ff) << 24) | + ((value & 0x0000ff00) << 8) | + ((value & 0x00ff0000) >> 8) | + ((value & 0xff000000) >> 24)); +} + + +/* Endianess macros. */ +#if defined(MV_CPU_LE) +# define USB_16BIT_LE(X) (X) +# define USB_32BIT_LE(X) (X) +# define USB_16BIT_BE(X) USB_BYTE_SWAP_16BIT(X) +# define USB_32BIT_BE(X) USB_BYTE_SWAP_32BIT(X) +#elif defined(MV_CPU_BE) +# define USB_16BIT_LE(X) USB_BYTE_SWAP_16BIT(X) +# define USB_32BIT_LE(X) USB_BYTE_SWAP_32BIT(X) +# define USB_16BIT_BE(X) (X) +# define USB_32BIT_BE(X) (X) +#else + #error "CPU endianess isn't defined!\n" +#endif + +typedef struct +{ + void (*bspPrintf) (const char * fmt, ...); + int (*bspSprintf) (char* buffer, const char * fmt, ...); + void* (*bspUncachedMalloc) (void* pDev, uint_32 size, uint_32 align, + unsigned long* pPhyAddr); + void (*bspUncachedFree) (void* pDev, uint_32 size, unsigned long phyAddr, + void* pVirtAddr); + void* (*bspMalloc) (unsigned int size); + void (*bspFree) (void* ptr); + void* (*bspMemset) (void* ptr, int val, unsigned int size); + void* (*bspMemcpy) (void* dst, const void* src, unsigned int size); + unsigned long (*bspCacheFlush) (void* pDev, void* pVirtAddr, int size); + unsigned long (*bspCacheInv) (void* pDev, void* pVirtAddr, int size); + unsigned long (*bspVirtToPhys) (void* pDev, void* pVirtAddr); + int (*bspLock) (void); + void (*bspUnlock) (int lockKey); + uint_32 (*bspGetCapRegAddr) (int devNo); + void (*bspResetComplete) (int devNo); + +} USB_IMPORT_FUNCS; + +extern USB_IMPORT_FUNCS* global_import_funcs; + +#define USB_sprintf(frmt, x...) if( (global_import_funcs != NULL) && \ + global_import_funcs->bspSprintf != NULL) \ + global_import_funcs->bspSprintf(frmt, ##x) + +#define USB_printf(frmt, x...) if( (global_import_funcs != NULL) && \ + (global_import_funcs->bspPrintf != NULL) ) \ + global_import_funcs->bspPrintf(frmt, ##x) + + +#define USB_virt_to_phys(pVirt) (global_import_funcs->bspVirtToPhys == NULL) ? \ + (uint_32)(pVirt) : global_import_funcs->bspVirtToPhys(NULL, pVirt) + +#define USB_get_cap_reg_addr(dev) global_import_funcs->bspGetCapRegAddr(dev) + +static INLINE void* USB_uncached_memalloc(uint_32 size, uint_32 align, unsigned long* pPhyAddr) +{ + /*USB_printf("**** USB_uncached_memalloc: size=%d\n", (size)); */ + return global_import_funcs->bspUncachedMalloc(NULL, size, align, pPhyAddr); +} + +static INLINE void* USB_memalloc(uint_32 size) +{ + /*USB_printf("**** USB_memalloc: size=%d\n", (size)); */ + return global_import_funcs->bspMalloc(size); +} + +#define USB_uncached_memfree(pVirt, size, physAddr) \ + /*USB_printf("#### USB_uncached_memfree: pVirt=0x%x\n", (pVirt)); */\ + global_import_funcs->bspUncachedFree(NULL, size, physAddr, pVirt); + +#define USB_memfree(ptr) \ + /*USB_printf("#### USB_memfree: ptr=0x%x\n", (ptr));*/ \ + global_import_funcs->bspFree(ptr); + +#define USB_memzero(ptr, n) global_import_funcs->bspMemset(ptr, 0, n) +#define USB_memcopy(src, dst, n) global_import_funcs->bspMemcpy(dst, src, n) + +#define USB_dcache_inv(ptr, size) if(global_import_funcs->bspCacheInv != NULL) \ + global_import_funcs->bspCacheInv(NULL, ptr, size) + +#define USB_dcache_flush(ptr, size) if(global_import_funcs->bspCacheFlush != NULL) \ + global_import_funcs->bspCacheFlush(NULL, ptr, size) + +#define USB_lock() (global_import_funcs->bspLock == NULL) ? \ + 0 : global_import_funcs->bspLock() + +#define USB_unlock(key) if(global_import_funcs->bspUnlock != NULL) \ + global_import_funcs->bspUnlock(key) + +#define USB_reset_complete(dev) if(global_import_funcs->bspResetComplete) \ + global_import_funcs->bspResetComplete(dev) + + +#if defined(USB_UNDERRUN_WA) + +#define USB_SRAM_MAX_PARTS 16 + +typedef struct +{ + uint_32 (*bspGetSramAddr) (uint_32* pSize); + void (*bspIdmaCopy) (void* dst, void* src, unsigned int size); + +} USB_WA_FUNCS; + +extern USB_WA_FUNCS* global_wa_funcs; +extern int global_wa_sram_parts; +extern int global_wa_threshold; + +#define USB_get_sram_addr(pSize) global_wa_funcs->bspGetSramAddr(pSize) + +#define USB_idma_copy(dst, src, size) \ + if(global_wa_funcs->bspIdmaCopy != NULL) \ + global_wa_funcs->bspIdmaCopy(dst, src, size) + +#endif /* USB_UNDERRUN_WA */ + +#endif /* __mvUsbTypes_h__ */ + +/* EOF */ + diff --git a/board/mv_feroceon/mv_hal/usb/common/mvUsbCore.h b/board/mv_feroceon/mv_hal/usb/common/mvUsbCore.h new file mode 100644 index 0000000..c6af8e8 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/common/mvUsbCore.h @@ -0,0 +1,720 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#ifndef __mvUsbCore_h__ +#define __mvUsbCore_h__ + +#include "usb/api/mvUsbTypes.h" + +/* VUSBHS specific defines */ +#define VUSBHS_MAX_PORTS (8) +#define EHCI_CAP_LEN_MASK (0x000000FF) +#define EHCI_DATA_STRUCTURE_BASE_ADDRESS (0) + +/* Command Register Bit Masks */ +#define EHCI_CMD_RUN_STOP (0x00000001) +#define EHCI_CMD_CTRL_RESET (0x00000002) +#define EHCI_CMD_SETUP_TRIPWIRE_SET (0x00002000) +#define EHCI_CMD_SETUP_TRIPWIRE_CLEAR ~EHCI_CMD_SETUP_TRIPWIRE_SET + +#define EHCI_CMD_ATDTW_TRIPWIRE_SET (0x00004000) +#define EHCI_CMD_ATDTW_TRIPWIRE_CLEAR ~EHCI_CMD_ATDTW_TRIPWIRE_SET + +/*bit 15,3,2 are for frame list size */ +#define EHCI_CMD_FRAME_SIZE_1024 (0x00000000) /* 000 */ +#define EHCI_CMD_FRAME_SIZE_512 (0x00000004) /* 001 */ +#define EHCI_CMD_FRAME_SIZE_256 (0x00000008) /* 010 */ +#define EHCI_CMD_FRAME_SIZE_128 (0x0000000C) /* 011 */ +#define EHCI_CMD_FRAME_SIZE_64 (0x00008000) /* 100 */ +#define EHCI_CMD_FRAME_SIZE_32 (0x00008004) /* 101 */ +#define EHCI_CMD_FRAME_SIZE_16 (0x00008008) /* 110 */ +#define EHCI_CMD_FRAME_SIZE_8 (0x0000800C) /* 111 */ + +/* Hardware Rev 4.0 related change */ +/* Mode Register Bit Masks */ +#define VUSBHS_MODE_CTRL_MODE_IDLE (0x00000000) +#define VUSBHS_MODE_CTRL_MODE_DEV (0x00000002) +#define VUSBHS_MODE_CTRL_MODE_HOST (0x00000003) +#define VUSBHS_MODE_BIG_ENDIAN (0x00000004) +#define VUSBHS_MODE_SETUP_LOCK_DISABLE (0x00000008) +#define VUSBHS_MODE_STREAM_DISABLE (0x00000010) + +/* Interrupt Enable Register Bit Masks */ +#define EHCI_INTR_INT_EN (0x00000001) +#define EHCI_INTR_ERR_INT_EN (0x00000002) +#define EHCI_INTR_PORT_CHANGE_DETECT_EN (0x00000004) + +#define EHCI_INTR_ASYNC_ADV_AAE (0x00000020) +#define EHCI_INTR_ASYNC_ADV_AAE_ENABLE (0x00000020) /* | with this to enable */ +#define EHCI_INTR_ASYNC_ADV_AAE_DISABLE (0xFFFFFFDF) /* & with this to disable */ + +#define EHCI_INTR_RESET_EN (0x00000040) +#define EHCI_INTR_SOF_UFRAME_EN (0x00000080) +#define EHCI_INTR_DEVICE_SUSPEND (0x00000100) + +/* Interrupt Status Register Masks */ +#define EHCI_STS_SOF (0x00000080) +#define EHCI_STS_RESET (0x00000040) +#define EHCI_STS_PORT_CHANGE (0x00000004) +#define EHCI_STS_ERR (0x00000002) +#define EHCI_STS_INT (0x00000001) +#define EHCI_STS_SUSPEND (0x00000100) +#define EHCI_STS_HC_HALTED (0x00001000) + +/* Endpoint Queue Head Bit Masks */ +#define VUSB_EP_QUEUE_HEAD_IOS (0x00008000) +#define VUSB_EP_QUEUE_HEAD_IOC (0x00008000) +#define VUSB_EP_QUEUE_HEAD_INT (0x00000100) +#define VUSB_EP_QUEUE_HEAD_NEXT_TERMINATE (0x00000001) +#define VUSB_EP_QUEUE_HEAD_MAX_PKT_LEN_POS (16) +#define VUSB_EP_QUEUE_HEAD_ZERO_LEN_TER_SEL (0x20000000) +#define VUSB_EP_QUEUE_HEAD_MULT_POS (30) +#define VUSB_EP_MAX_LENGTH_TRANSFER (0x4000) + +#define VUSB_EP_QUEUE_HEAD_STATUS_ACTIVE (0x00000080) + +#define VUSBHS_TD_NEXT_TERMINATE (0x00000001) +#define VUSBHS_TD_IOC (0x00008000) +#define VUSBHS_TD_STATUS_ACTIVE (0x00000080) +#define VUSBHS_TD_STATUS_HALTED (0x00000040) +#define VUSBHS_TD_RESERVED_FIELDS (0x00007F00) +#define VUSBHS_TD_ERROR_MASK (0x68) +#define VUSBHS_TD_ADDR_MASK (0xFFFFFFE0) +#define VUSBHS_TD_LENGTH_BIT_POS (16) + +#define EHCI_EPCTRL_TX_ALL_MASK (0xFFFF0000) +#define EHCI_EPCTRL_RX_ALL_MASK (0x0000FFFF) + +#define EHCI_EPCTRL_TX_DATA_TOGGLE_RST (0x00400000) +#define EHCI_EPCTRL_TX_EP_STALL (0x00010000) +#define EHCI_EPCTRL_RX_EP_STALL (0x00000001) +#define EHCI_EPCTRL_RX_DATA_TOGGLE_RST (0x00000040) +#define EHCI_EPCTRL_RX_ENABLE (0x00000080) +#define EHCI_EPCTRL_TX_ENABLE (0x00800000) +#define EHCI_EPCTRL_CONTROL (0x00000000) +#define EHCI_EPCTRL_ISOCHRONOUS (0x00040000) +#define EHCI_EPCTRL_BULK (0x00080000) +#define EHCI_EPCTRL_INT (0x000C0000) +#define EHCI_EPCTRL_TX_TYPE (0x000C0000) +#define EHCI_EPCTRL_RX_TYPE (0x0000000C) +#define EHCI_EPCTRL_DATA_TOGGLE_INHIBIT (0x00000020) +#define EHCI_EPCTRL_TX_EP_TYPE_SHIFT (18) +#define EHCI_EPCTRL_RX_EP_TYPE_SHIFT (2) + +/* set bit 24 (PFSC) in PORTSCX register */ +#define EHCI_PORTSCX_FORCE_FULL_SPEED_CONNECT (0x01000000) +/* set bit 23 (PHCD) in PORTSCX register */ +#define EHCI_PORTSCX_PHY_CLOCK_DISABLE (0x00800000) + +#define EHCI_PORTSCX_PORT_POWER (0x00001000) +#define EHCI_PORTSCX_LINE_STATUS_BITS (0x00000C00) +#define EHCI_PORTSCX_LINE_STATUS_SE0 (0x00000000) +#define EHCI_PORTSCX_LINE_STATUS_KSTATE (0x00000400) +#define EHCI_PORTSCX_LINE_STATUS_JSTATE (0x00000800) +#define EHCI_PORTSCX_PORT_HIGH_SPEED (0x00000200) +#define EHCI_PORTSCX_PORT_RESET (0x00000100) +#define EHCI_PORTSCX_PORT_SUSPEND (0x00000080) +#define EHCI_PORTSCX_PORT_FORCE_RESUME (0x00000040) +#define EHCI_PORTSCX_PORT_EN_DIS_CHANGE (0x00000008) +#define EHCI_PORTSCX_PORT_ENABLE (0x00000004) +#define EHCI_PORTSCX_CONNECT_STATUS_CHANGE (0x00000002) +#define EHCI_PORTSCX_CURRENT_CONNECT_STATUS (0x00000001) + +#define VUSBHS_PORTSCX_PORT_SPEED_FULL (0x00000000) +#define VUSBHS_PORTSCX_PORT_SPEED_LOW (0x04000000) +#define VUSBHS_PORTSCX_PORT_SPEED_HIGH (0x08000000) +#define VUSBHS_SPEED_MASK (0x0C000000) +#define VUSBHS_SPEED_BIT_POS (26) + +#define EHCI_PORTSCX_W1C_BITS (0x2A) +#define VUSB_EP_QH_PACKET_SIZE (0x3FFF0000) +#define VUSB_EP_TR_PACKET_SIZE (0x7FFF0000) + +#define VUSBHS_FRINDEX_MS_MASK (0xFFFFFFF8) +#define VUSBHS_ADDRESS_BIT_SHIFT (25) + +#define VUSB20_DCC_MAX_ENDPTS_SUPPORTED (0x1F) +#define VUSB20_DCC_HOST_MODE_MASK (1 << 8) +#define VUSB20_DCC_DEVICE_MODE_MASK (1 << 7) + +#define EHCI_HCC_PARAMS_64_BIT_ADDR_CAP (0x01) +#define EHCI_HCC_PARAMS_PGM_FRM_LIST_FLAG (0x02) +#define EHCI_HCC_PARAMS_ASYNC_PARK_CAP (0x04) +#define EHCI_HCC_PARAMS_ISOCH_SCHED_THRESHOLD (0xF0) +#define EHCI_HCC_PARAMS_ISOCH_FRAME_CACHED (0x80) + +#define VUSB20_HCS_PARAMS_PORT_POWER_CONTROL_FLAG (0x10) + +#define VUSB20_HOST_INTR_EN_BITS (0x37) + +#define VUSB20_DEFAULT_PERIODIC_FRAME_LIST_SIZE (1024) +#define VUSB20_NEW_PERIODIC_FRAME_LIST_BITS (2) +#define EHCI_FRAME_LIST_ELEMENT_POINTER_T_BIT (0x01) +#define EHCI_ITD_T_BIT (0x01) +#define EHCI_SITD_T_BIT (0x01) +#define EHCI_QUEUE_HEAD_POINTER_T_BIT (0x01) + + +/************************************************************ +Split transatcions specific defines +************************************************************/ +#define EHCI_START_SPLIT_MAX_BUDGET 188 + +#define EHCI_ELEMENT_TYPE_ITD (0x00) +#define EHCI_ELEMENT_TYPE_QH (0x02) +#define EHCI_ELEMENT_TYPE_SITD (0x04) +#define EHCI_ELEMENT_TYPE_FSTN (0x06) +#define EHCI_ELEMENT_TYPE_MASK (0x06) + +#define EHCI_FRAME_LIST_ELEMENT_TYPE_ITD (0x00) +#define EHCI_FRAME_LIST_ELEMENT_TYPE_QH (0x01) +#define EHCI_FRAME_LIST_ELEMENT_TYPE_SITD (0x02) +#define EHCI_FRAME_LIST_ELEMENT_TYPE_FSTN (0x03) +#define EHCI_FRAME_LIST_ELEMENT_TYPE_BIT_POS (1) + + +#define EHCI_QH_ELEMENT_TYPE_ITD (0x00) +#define EHCI_QH_ELEMENT_TYPE_QH (0x01) +#define EHCI_QH_ELEMENT_TYPE_SITD (0x02) +#define EHCI_QH_ELEMENT_TYPE_FSTN (0x03) + +#define EHCI_QH_ELEMENT_TYPE_BIT_POS (1) + +#define EHCI_QTD_PID_OUT_TOKEN (0x000) +#define EHCI_QTD_PID_IN_TOKEN (0x100) +#define EHCI_QTD_PID_SETUP_TOKEN (0x200) +#define EHCI_QTD_IOC (0x8000) +#define EHCI_QTD_STATUS_ACTIVE (0x0080) +#define EHCI_QTD_STATUS_HALTED (0x0040) +#define EHCI_QTD_PID_SETUP (0x0200) +#define EHCI_QTD_PID_IN (0x0100) +#define EHCI_QTD_PID_OUT (0x0000) +#define EHCI_QTD_LENGTH_BIT_POS (16) +#define EHCI_QTD_DATA_TOGGLE (0x80000000) +#define EHCI_QTD_DATA_TOGGLE_BIT_POS (31) +#define EHCI_QTD_LENGTH_BIT_MASK (0x7FFF0000) +#define EHCI_QTD_ERROR_BITS_MASK (0x0000003E) +#define EHCI_QTD_DEFAULT_CERR_VALUE (0xC00) + +#define EHCI_SETUP_TOKEN (2) +#define EHCI_OUT_TOKEN (0) +#define EHCI_IN_TOKEN (1) + +#define EHCI_QTD_T_BIT (0x01) + +#define EHCI_QH_ENDPOINT_SPEED_FULL (0x00) +#define EHCI_QH_ENDPOINT_SPEED_LOW (0x01) +#define EHCI_QH_ENDPOINT_SPEED_HIGH (0x02) +#define EHCI_QH_ENDPOINT_SPEED_RESERVED (0x03) + +#define EHCI_ITD_LENGTH_BIT_POS (16) +#define EHCI_ITD_IOC_BIT (0x00008000) +#define EHCI_ITD_ACTIVE_BIT (0x80000000) +#define EHCI_ITD_PG_SELECT_BIT_POS (12) +#define EHCI_ITD_DIRECTION_BIT_POS (11) +#define EHCI_ITD_EP_BIT_POS (8) +#define EHCI_ITD_STATUS (0xF0000000) +#define EHCI_ITD_STATUS_ACTIVE (0x80000000) /*bit 4 = 1000*/ +#define EHCI_ITD_STATUS_DATA_BUFFER_ERR (0x40000000) /*bit 3 = 0100*/ +#define EHCI_ITD_STATUS_BABBLE_ERROR (0x20000000) /*bit 2 = 0010*/ +#define EHCI_ITD_STATUS_TRANSACTION_ERR (0x10000000) /*bit 4 = 0001*/ + +#define EHCI_ITD_LENGTH_TRANSMITTED (0x0FFF0000) +#define EHCI_ITD_BUFFER_OFFSET (0x00000FFF) +#define EHCI_ITD_PAGE_NUMBER (0x00007000) +#define EHCI_ITD_BUFFER_POINTER (0xFFFFF000) +#define EHCI_ITD_MULTI_TRANSACTION_BITS (0x00000003) + + + +/* SITD position bits */ +#define EHCI_SITD_DIRECTION_BIT_POS (31) +#define EHCI_SITD_PORT_NUMBER_BIT_POS (24) +#define EHCI_SITD_HUB_ADDR_BIT_POS (16) +#define EHCI_SITD_EP_ADDR_BIT_POS (8) + +#define EHCI_SITD_COMPLETE_SPLIT_MASK_BIT_POS (8) + +#define EHCI_SITD_IOC_BIT_SET (0x80000000) +#define EHCI_SITD_PAGE_SELECT_BIT_POS (30) +#define EHCI_SITD_TRANSFER_LENGTH_BIT_POS (16) +#define EHCI_SITD_STATUS_ACTIVE (0x80) + +#define EHCI_SITD_STATUS (0xFF) +#define EHCI_SITD_LENGTH_TRANSMITTED (0x03FF0000) +#define EHCI_SITD_BUFFER_OFFSET (0x00000FFF) +#define EHCI_SITD_PAGE_NUMBER (0x40000000) +#define EHCI_SITD_BUFFER_POINTER (0xFFFFF000) + + + +#define EHCI_SITD_BUFFER_PTR_BIT_POS (12) +#define EHCI_SITD_TP_BIT_POS (3) +#define EHCI_SITD_TP_ALL (0) +#define EHCI_SITD_TP_BEGIN (1) +#define EHCI_SITD_TP_MID (2) +#define EHCI_SITD_TP_END (3) + + + +/* Interrupt enable bit masks */ +#define EHCI_IER_ASYNCH_ADVANCE (0x00000020) +#define EHCI_IER_HOST_SYS_ERROR (0x00000010) +#define EHCI_IER_FRAME_LIST_ROLLOVER (0x00000008) +#define EHCI_IER_PORT_CHANGE (0x00000004) +#define EHCI_IER_USB_ERROR (0x00000002) +#define EHCI_IER_USB_INTERRUPT (0x00000001) + +/* Interrupt status bit masks */ +#define EHCI_STS_RECLAIMATION (0x00002000) +#define EHCI_STS_SOF_COUNT (0x00000080) +#define EHCI_STS_ASYNCH_ADVANCE (0x00000020) +#define EHCI_STS_HOST_SYS_ERROR (0x00000010) +#define EHCI_STS_FRAME_LIST_ROLLOVER (0x00000008) +#define EHCI_STS_PORT_CHANGE (0x00000004) +#define EHCI_STS_USB_ERROR (0x00000002) +#define EHCI_STS_USB_INTERRUPT (0x00000001) + +/* Status bit masks */ +#define EHCI_STS_ASYNCH_SCHEDULE (0x00008000) +#define EHCI_STS_PERIODIC_SCHEDULE (0x00004000) +#define EHCI_STS_RECLAMATION (0x00002000) +#define EHCI_STS_HC_HALTED (0x00001000) + +/* USB command bit masks */ +#define EHCI_USBCMD_ASYNC_SCHED_ENABLE (0x00000020) +#define EHCI_USBCMD_PERIODIC_SCHED_ENABLE (0x00000010) + +#define EHCI_HCS_PARAMS_N_PORTS (0x0F) + +#define VUSB_HS_DELAY (3500) + +#define EHCI_QH_EP_NUM_MASK (0x0F00) +#define EHCI_QH_EP_NUM_BITS_POS (8) +#define EHCI_QH_DEVICE_ADDRESS_MASK (0x7F) +#define EHCI_QH_SPEED_BITS_POS (12) +#define EHCI_QH_MAX_PKT_SIZE_BITS_POS (16) +#define EHCI_QH_NAK_COUNT_RL_BITS_POS (28) +#define EHCI_QH_EP_CTRL_FLAG_BIT_POS (27) +#define EHCI_QH_HEAD_RECLAMATION_BIT_POS (15) +#define EHCI_QH_DTC_BIT_POS (14) +#define EHCI_QH_HIGH_BW_MULT_BIT_POS (30) +#define EHCI_QH_HUB_PORT_NUM_BITS_POS (23) +#define EHCI_QH_HUB_ADDR_BITS_POS (16) +#define EHCI_QH_SPLIT_COMPLETION_MASK_BITS_POS (8) +#define EHCI_QH_SPLIT_COMPLETION_MASK (0xFF00) +#define EHCI_QH_INTR_SCHED_MASK (0xFF) +#define EHCI_QH_INACTIVATE_NEXT_TR_BIT_POS (7) +#define EHCI_QH_HORIZ_PHY_ADDRESS_MASK (0xFFFFFFE0) +#define EHCI_QH_TR_OVERLAY_DT_BIT (0x80000000) + +#define EHCI_SITD_SPLIT_COMPLETION_MASK_BITS_POS (8) + +#define EHCI_INTR_NO_THRESHOLD_IMMEDIATE (0x00010000) +#define EHCI_NEW_PERIODIC_FRAME_LIST_SIZE (1024) +#define EHCI_FRAME_LIST_SIZE_BITS_POS (2) +#define EHCI_HORIZ_PHY_ADDRESS_MASK (0xFFFFFFE0) + +#define DEFAULT_MAX_NAK_COUNT (15) + +/* OTG Status and control register bit masks */ + +/* OTG interrupt enable bit masks */ +#define VUSBHS_OTGSC_INTERRUPT_ENABLE_BITS_MASK (0x5F000000) +#define VUSBHS_OTGSC_DPIE (0x40000000) /* Data-line pulsing IE */ +#define VUSBHS_OTGSC_1MSIE (0x20000000) +#define VUSBHS_OTGSC_BSEIE (0x10000000) /* B-session end IE */ +#define VUSBHS_OTGSC_BSVIE (0x08000000) /* B-session valid IE */ +#define VUSBHS_OTGSC_ASVIE (0x04000000) /* A-session valid IE */ +#define VUSBHS_OTGSC_AVVIE (0x02000000) /* A-V-bus valid IE */ +#define VUSBHS_OTGSC_IDIE (0x01000000) /* OTG ID IE */ + +/* OTG interrupt status bit masks */ +#define VUSBHS_OTGSC_INTERRUPT_STATUS_BITS_MASK (0x005F0000) +#define VUSBHS_OTGSC_DPIS (0x00400000) /* Data-line pulsing IS */ +#define VUSBHS_OTGSC_1MSIS (0x00200000) +#define VUSBHS_OTGSC_BSEIS (0x00100000) /* B-session end IS */ +#define VUSBHS_OTGSC_BSVIS (0x00080000) /* B-session valid IS */ +#define VUSBHS_OTGSC_ASVIS (0x00040000) /* A-session valid IS */ +#define VUSBHS_OTGSC_AVVIS (0x00020000) /* A-Vbus valid IS */ +#define VUSBHS_OTGSC_IDIS (0x00010000) /* OTG ID IS */ + +/* OTG status bit masks */ +#define VUSBHS_OTGSC_DPS (0x00004000) +#define VUSBHS_OTGSC_BSE (0x00001000) /* B-session end */ +#define VUSBHS_OTGSC_BSV (0x00000800) /* B-session valid */ +#define VUSBHS_OTGSC_ASV (0x00000400) /* A-session valid */ +#define VUSBHS_OTGSC_AVV (0x00000200) /* A-Vbus Valid */ +#define VUSBHS_OTGSC_ID (0x00000100) /* OTG ID */ + +/* OTG control bit masks */ +#define VUSBHS_OTGSC_CTL_BITS (0x2F) +#define VUSBHS_OTGSC_HABA (0x00000080) /* hardware assisted data pulse bits*/ +#define VUSBHS_OTGSC_HADP (0x00000040) /* hardware assisted data pulse bits*/ + +#ifdef PATCH_3 +/* the following change is to be compatable with 4.0 revision of +hardware. Enable the following switch in config.mk to enable the +changes. */ + + /* WEB20040409 below line changed from VUSBHS_OTGSC_B_HOST_EN to VUSBHS_OTGSC_IDPU + to reflect change in usbhs4.0 B_HOST_EN has not been used quite some time */ + #define VUSBHS_OTGSC_IDPU (0x00000020) /* ID pull enable */ +#else + #define VUSBHS_OTGSC_B_HOST_EN (0x00000020) /* B_host_enable */ +#endif + +#define VUSBHS_OTGSC_DP (0x00000010) /* Data-pulsing */ +#define VUSBHS_OTGSC_OT (0x00000008) /* OTG termination */ +#if 0 + #define VUSBHS_OTGSC_VO (0x00000004) /* Vbus on */ +#endif + +#define VUSBHS_OTGSC_HAAR (0x00000004) /* Auto reset bit*/ + +#define VUSBHS_OTGSC_VC (0x00000002) /* Vbus charge */ +#define VUSBHS_OTGSC_VD (0x00000001) /* Vbus discharge */ + +typedef uint_32 USB_REGISTER, _PTR_ USB_REGISTER_PTR; + +/* The VUSB register structure */ +typedef struct { + union { + struct { + volatile USB_REGISTER CAPLENGTH_HCIVER; + volatile USB_REGISTER HCS_PARAMS; /* HC structural parameters */ + volatile USB_REGISTER HCC_PARAMS; /* HC Capability Parameters*/ + volatile USB_REGISTER RESERVED1[5]; + volatile USB_REGISTER DCI_VERSION; /* DC version number and reserved 16 bits */ + volatile USB_REGISTER DCC_PARAMS; /* DC Capability Parameters */ + } CAPABILITY_REGISTERS; + + struct { + volatile USB_REGISTER USB_CMD; /* Command register */ + volatile USB_REGISTER USB_STS; /* Status register */ + volatile USB_REGISTER USB_INTR; /* Interrupt enable */ + volatile USB_REGISTER USB_FRINDEX; /* Frame index */ + volatile USB_REGISTER CTRLDSSEGMENT; /* 4G segment selector */ + volatile USB_REGISTER DEVICE_ADDR; /* Device Address */ + volatile USB_REGISTER EP_LIST_ADDR; /* Endpoint List Address */ + volatile USB_REGISTER RESERVED0[9]; + volatile USB_REGISTER CONFIG_FLAG; /* Configured Flag register */ + volatile USB_REGISTER PORTSCX[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */ + volatile USB_REGISTER OTGSC; + volatile USB_REGISTER USB_MODE; /* USB Host/Device mode */ + volatile USB_REGISTER ENDPT_SETUP_STAT; /* Endpoint Setup Status */ + volatile USB_REGISTER ENDPTPRIME; /* Endpoint Initialize */ + volatile USB_REGISTER ENDPTFLUSH; /* Endpoint De-initialize */ + volatile USB_REGISTER ENDPTSTATUS; /* Endpoint Status */ + volatile USB_REGISTER ENDPTCOMPLETE; /* Endpoint Interrupt On Complete */ + volatile USB_REGISTER ENDPTCTRLX[16]; /* Endpoint Control, where x = 0.. 15 */ + } OPERATIONAL_DEVICE_REGISTERS; + + struct { + volatile USB_REGISTER USB_CMD; /* Command register */ + volatile USB_REGISTER USB_STS; /* Status register */ + volatile USB_REGISTER USB_INTR; /* Interrupt enable */ + volatile USB_REGISTER USB_FRINDEX; /* Frame index */ + volatile USB_REGISTER CTRLDSSEGMENT; /* 4G segment selector */ + volatile USB_REGISTER PERIODIC_LIST_BASE_ADDR; /* Periodic schedule list */ + volatile USB_REGISTER CURR_ASYNC_LIST_ADDR; /* Current Asynch schedule list */ + volatile USB_REGISTER ASYNCTTSTS; /* Async buffer in embedded TT control */ + volatile USB_REGISTER RESERVED0[8]; + volatile USB_REGISTER CONFIG_FLAG; /* Configured Flag register */ + volatile USB_REGISTER PORTSCX[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */ + volatile USB_REGISTER OTGSC; /* OTG status and control register */ + volatile USB_REGISTER USB_MODE; /* USB Host/Device mode */ + } OPERATIONAL_HOST_REGISTERS; + } REGISTERS; +} VUSB20_REG_STRUCT, _PTR_ VUSB20_REG_STRUCT_PTR; + +typedef struct { + volatile uint_32 MAX_PKT_LENGTH; /* Bits 16..26 Bit 15 is Interrupt + ** On Setup + */ + volatile uint_32 CURR_DTD_PTR; /* Current dTD Pointer */ + volatile uint_32 NEXT_DTD_PTR; /* Next dTD Pointer */ + volatile uint_32 SIZE_IOC_INT_STS; /* Total bytes (16..30), IOC (15), + ** INT (8), STS (0-7) + */ + volatile uint_32 BUFF_PTR0; /* Buffer pointer Page 0 (12-31) */ + volatile uint_32 BUFF_PTR1; /* Buffer pointer Page 1 (12-31) */ + volatile uint_32 BUFF_PTR2; /* Buffer pointer Page 2 (12-31) */ + volatile uint_32 BUFF_PTR3; /* Buffer pointer Page 3 (12-31) */ + volatile uint_32 BUFF_PTR4; /* Buffer pointer Page 4 (12-31) */ + volatile uint_32 RESERVED1; + volatile uint_8 SETUP_BUFFER[8]; /* 8 bytes of setup data that follows + ** the Setup PID + */ + volatile uint_32 RESERVED2[4]; +} VUSB20_EP_QUEUE_HEAD_STRUCT, _PTR_ VUSB20_EP_QUEUE_HEAD_STRUCT_PTR; + +typedef struct { + pointer PRIVATE; + void (_CODE_PTR_ FREE)(pointer); + pointer XD_FOR_THIS_DTD; +} SCRATCH_STRUCT, _PTR_ SCRATCH_STRUCT_PTR; + +typedef struct ep_tr_struct { + volatile uint_32 NEXT_TR_ELEM_PTR; /* Memory address of next + ** dTD to be processed (5-31) + ** and the T (bit 0) indicating + ** pointer validity + */ + volatile uint_32 SIZE_IOC_STS; /* total bytes (16-30), + ** IOC (15), Status (0-7) + */ + volatile uint_32 BUFF_PTR0; /* Buffer pointer Page 0 */ + volatile uint_32 BUFF_PTR1; /* Buffer pointer Page 1 */ + volatile uint_32 BUFF_PTR2; /* Buffer pointer Page 2 */ + volatile uint_32 BUFF_PTR3; /* Buffer pointer Page 3 */ + volatile uint_32 BUFF_PTR4; /* Buffer pointer Page 4 */ + volatile SCRATCH_STRUCT_PTR SCRATCH_PTR; +} VUSB20_EP_TR_STRUCT, _PTR_ VUSB20_EP_TR_STRUCT_PTR; + +typedef struct { + uint_32 NEXT_LINK_PTR; /* (5-31) Memory address of + ** next schedule data structure + ** item Type (1..2 ) and the + ** T (bit 0) indicating pointer + ** validity + */ + uint_32 TR_STATUS_CTL_LIST[8]; /* bits 31-28: Status, + ** bits 27-16: Tr X length + ** bit 15: Int on complete + ** bits 14-12: Page Select + ** bits 11-0: Tr X offset + */ + uint_32 BUFFER_PAGE_PTR_LIST[7]; /* bits 31-12 4K aligned pointer + ** to physical memory + ** bits 11-8 endpoint no. + ** bit 7: reserved + ** bits 6-0 device address*/ + SCRATCH_STRUCT_PTR SCRATCH_PTR; + pointer PIPE_DESCR_FOR_THIS_ITD; + pointer PIPE_TR_DESCR_FOR_THIS_ITD; + uint_32_ptr frame_list_ptr; + uint_32 number_of_transactions; + /* 32-byte aligned structures */ + uint_32 RESERVED[11]; +} EHCI_ITD_STRUCT, _PTR_ EHCI_ITD_STRUCT_PTR; + +typedef struct { + uint_32 NEXT_LINK_PTR; /* (5-31) Memory address of + ** next schedule data structure + ** item Type (1..2 ) and the + ** T (bit 0) indicating pointer + ** validity + */ + uint_32 EP_CAPAB_CHARAC; /* bits 31: Direction (I/O), + ** bits 30-24: Port number + ** bit 23: reserved + ** bits 22-16: Hub address + ** bits 15-12: Reserved + ** bits 11-8: Endpoint number + ** bit 7: reserved + ** bits 6-0: device address + */ + uint_32 UFRAME_SCHED_CTL; /* bits 31-16: reserved + ** bits 15-8: Split completion mask + ** bits 7-0: Split start mask + */ + uint_32 TRANSFER_STATE; /* bit 31: int on complete + ** bit 30: Page Select + ** bits 29-26: Reserved + ** bits 25-16: total bytes to + ** transfer + ** bits 15-8: uframe + ** complete-split progress mask + ** bits 7-0: status + */ + uint_32 BUFFER_PTR_0; /* bits 31-12: 4K aligned pointer + ** to physical memory + ** bits 11-0: Current offset + */ + uint_32 BUFFER_PTR_1; /* bits 31-12: 4K aligned pointer + ** to physical memory + ** bits 11-5 reserved + ** bits 4-3 tr position + ** bits 2-0 tr count + */ + uint_32 BACK_LINK_PTR; /* bits 31-5 back pointer points to sITD + ** bits 4-1: reserved + ** bit 0: terminate + */ + SCRATCH_STRUCT_PTR SCRATCH_PTR; + pointer PIPE_DESCR_FOR_THIS_SITD; + pointer PIPE_TR_DESCR_FOR_THIS_SITD; + uint_32_ptr frame_list_ptr; + + /* align to 16 word boundry */ + uint_32 RESERVED[5]; + +} EHCI_SITD_STRUCT, _PTR_ EHCI_SITD_STRUCT_PTR; + +typedef struct { + uint_32 NEXT_QTD_PTR; /* (5-31) Memory address of + ** next qTD to be processed + ** (4..1) reserved + ** T (bit 0) indicating pointer + ** validity + */ + uint_32 ALT_NEXT_QTD_PTR; /* bits 31-5: alternate next + ** qTD if the above one encounters + ** a short packet + ** (4..1) reserved + ** T (bit 0) indicating pointer + ** validity + */ + uint_32 TOKEN; /* bits 31: data toggle + ** bits 30-16: Total bytes to transfer + ** bit 15: Interrupt on Complete + ** bits 14-12: Current page + ** bits 11-10: Error Counter + ** bits 9-8: PID code + ** bits 7-0: status + */ + uint_32 BUFFER_PTR_0; /* bit 31-12: 4K-page aligned + ** physical memory address + ** bit 11-0: Current Offset + */ + uint_32 BUFFER_PTR_1; /* bit 31-12: 4K-page aligned + ** physical memory address + ** bit 11-0: reserved + */ + uint_32 BUFFER_PTR_2; /* bit 31-12: 4K-page aligned + ** physical memory address + ** bit 11-0: reserved + */ + uint_32 BUFFER_PTR_3; /* bit 31-12: 4K-page aligned + ** physical memory address + ** bit 11-0: reserved + */ + uint_32 BUFFER_PTR_4; /* bit 31-12: 4K-page aligned + ** physical memory address + ** bit 11-0: reserved + */ + SCRATCH_STRUCT_PTR SCRATCH_PTR; + pointer PIPE_DESCR_FOR_THIS_QTD; + pointer TR_FOR_THIS_QTD; + uint_32 RESERVED[5]; +} EHCI_QTD_STRUCT, _PTR_ EHCI_QTD_STRUCT_PTR; + +typedef struct { + uint_32 HORIZ_LINK_PTR; /* (5-31) Memory address of + ** next data object to be processed + ** (4..3) reserved + ** (2..1) type of the item + ** T (bit 0) indicating pointer + ** validity + */ + uint_32 EP_CAPAB_CHARAC1; /* bits 31-28: NAK count reload, + ** bit 27: Control endpoint flag + ** bit 26-16: Maximum packet length + ** bit 15: Head of reclamation + ** list flag + ** bit 14: data toggle control + ** bits 13-12: endpoint speed + ** bit 11-8: endpoint number + ** bits 7: Inactivate on next tr + ** bits 6-0: Device address + */ + uint_32 EP_CAPAB_CHARAC2; /* bits 31-30: High-BW pipe + ** Multiplier, + ** bit 29-23: Port number + ** bit 22-16: Hub address + ** bit 15-8: Split completion mask + ** bit 7-0: Interrupt schedule mask + */ + uint_32 CURR_QTD_LINK_PTR;/* bits 31-5: physical memory address + ** of the current xaction processed + */ + uint_32 NEXT_QTD_LINK_PTR;/* bits 31-5: physical memory address + ** of the current xaction processed + ** bit 0: Terminate bit + */ + uint_32 ALT_NEXT_QTD_LINK_PTR; /* bits 31-5: physical memory address + ** of the current xaction processed + ** bits 4-1: NAK counter + ** bit 0: Terminate bit + */ + uint_32 STATUS; /* bit 31: data-toggle + ** bits 30-16: total bytes to transfer + ** bit 15: Interrupt on complete + ** bits 11-10: Error counter + ** bit 0: Ping state/Err + ** physical memory address + ** bit 11-0: reserved + */ + uint_32 BUFFER_PTR_0; /* bit 31-12: 4K-page aligned + ** physical memory address + ** bit 11-0: reserved + */ + uint_32 BUFFER_PTR_1; /* bit 31-12: 4K-page aligned + ** physical memory address + ** bit 7-0: Split-transaction, + ** complete-split progress + */ + uint_32 BUFFER_PTR_2; /* bits 31-12: 4K-page aligned + ** physical memory address + ** bits 11-5: S-bytes + ** bits 4-0: Split-transaction + ** frame tag + */ + uint_32 BUFFER_PTR_3; /* bit 31-12: 4K-page aligned + ** physical memory address + ** bit 11-0: reserved + */ + uint_32 BUFFER_PTR_4; /* bit 31-12: 4K-page aligned + ** physical memory address + ** bit 11-0: reserved + */ + SCRATCH_STRUCT_PTR SCRATCH_PTR; + pointer PIPE_DESCR_FOR_THIS_QH; + uint_32 RESERVED[18]; +} EHCI_QH_STRUCT, _PTR_ EHCI_QH_STRUCT_PTR; + +typedef struct { + uint_32 NORMAL_PATH_LINK_PTR; /* (5-31) Memory address of + ** next data object to be processed + ** in the periodic list + ** bits 4-3: reserved + ** (2..1) type of the item + ** T (bit 0) indicating pointer + ** validity + */ + uint_32 BACK_PATH_LINK_PTR; /* bits 31-5: Memory address of + ** the queue head, + ** bit 4-3: reserved + ** (2..1) type of the item + ** T (bit 0) indicating pointer + ** validity + */ + SCRATCH_STRUCT_PTR SCRATCH_PTR; + /* 32-bytes aligned */ + uint_32 RESERVED[6]; +} EHCI_FSTN_STRUCT, _PTR_ EHCI_FSTN_STRUCT_PTR; + +typedef uint_32 EHCI_FRAME_LIST_ELEMENT_POINTER; + +#endif /* __mvUsbCore_h__ */ +/* EOF */ + + diff --git a/board/mv_feroceon/mv_hal/usb/common/mvUsbDesc.h b/board/mv_feroceon/mv_hal/usb/common/mvUsbDesc.h new file mode 100644 index 0000000..1a95297 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/common/mvUsbDesc.h @@ -0,0 +1,162 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#ifndef __mvUsbDesc_h__ +#define __mvUsbDesc_h__ + +#include "mvUsbTypes.h" + +typedef struct usb_device_descriptor +{ + uint_8 bLength; /* Descriptor size in bytes = 18 */ + uint_8 bDescriptorType; /* DEVICE descriptor type = 1 */ + uint_8 bcdUSD[2]; /* USB spec in BCD, e.g. 0x0200 */ + uint_8 bDeviceClass; /* Class code, if 0 see interface */ + uint_8 bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint_8 bDeviceProtocol; /* Protocol, if 0 see interface */ + uint_8 bMaxPacketSize; /* Endpoint 0 max. size */ + uint_8 idVendor[2]; /* Vendor ID per USB-IF */ + uint_8 idProduct[2]; /* Product ID per manufacturer */ + uint_8 bcdDevice[2]; /* Device release # in BCD */ + uint_8 iManufacturer; /* Index to manufacturer string */ + uint_8 iProduct; /* Index to product string */ + uint_8 iSerialNumber; /* Index to serial number string */ + uint_8 bNumConfigurations; /* Number of possible configurations */ +} DEVICE_DESCRIPTOR, _PTR_ DEVICE_DESCRIPTOR_PTR; + +typedef struct usb_configuration_descriptor +{ + uint_8 bLength; /* Descriptor size in bytes = 9 */ + uint_8 bDescriptorType; /* CONFIGURATION type = 2 or 7 */ + uint_8 wTotalLength[2]; /* Length of concatenated descriptors */ + uint_8 bNumInterfaces; /* Number of interfaces, this config. */ + uint_8 bConfigurationValue; /* Value to set this config. */ + uint_8 iConfig; /* Index to configuration string */ + uint_8 bmAttributes; /* Config. characteristics */ + #define CONFIG_RES7 (0x80) /* Reserved, always = 1 */ + #define CONFIG_SELF_PWR (0x40) /* Self-powered device */ + #define CONFIG_WAKEUP (0x20) /* Remote wakeup */ + uint_8 bMaxPower; /* Max.power from bus, 2mA units */ +} CONFIGURATION_DESCRIPTOR, _PTR_ CONFIGURATION_DESCRIPTOR_PTR; + +typedef struct usb_interface_descriptor +{ + uint_8 bLength; /* Descriptor size in bytes = 9 */ + uint_8 bDescriptorType; /* INTERFACE descriptor type = 4 */ + uint_8 bInterfaceNumber; /* Interface no.*/ + uint_8 bAlternateSetting; /* Value to select this IF */ + uint_8 bNumEndpoints; /* Number of endpoints excluding 0 */ + uint_8 bInterfaceClass; /* Class code, 0xFF = vendor */ + uint_8 bInterfaceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint_8 bInterfaceProtocol; /* Protocol, 0xFF = vendor */ + uint_8 iInterface; /* Index to interface string */ +} INTERFACE_DESCRIPTOR, _PTR_ INTERFACE_DESCRIPTOR_PTR; + +typedef struct usb_endpoint_descriptor +{ + uint_8 bLength; /* Descriptor size in bytes = 7 */ + uint_8 bDescriptorType; /* ENDPOINT descriptor type = 5 */ + uint_8 bEndpointAddress; /* Endpoint # 0 - 15 | IN/OUT */ + #define IN_ENDPOINT (0x80) /* IN endpoint, device to host */ + #define OUT_ENDPOINT (0x00) /* OUT endpoint, host to device */ + #define ENDPOINT_MASK (0x0F) /* Mask endpoint # */ + uint_8 bmAttributes; /* Transfer type */ + #define CONTROL_ENDPOINT (0x00) /* Control transfers */ + #define ISOCH_ENDPOINT (0x01) /* Isochronous transfers */ + #define BULK_ENDPOINT (0x02) /* Bulk transfers */ + #define IRRPT_ENDPOINT (0x03) /* Interrupt transfers */ + #define EP_TYPE_MASK (0x03) /* Mask type bits */ + /* Following must be zero except for isochronous endpoints */ + #define ISOCH_NOSYNC (0x00) /* No synchronization */ + #define ISOCH_ASYNC (0x04) /* Asynchronous */ + #define ISOCH_ADAPT (0x08) /* Adaptive */ + #define ISOCH_SYNCH (0x0C) /* Synchrounous */ + #define ISOCH_DATA (0x00) /* Data endpoint */ + #define ISOCH_FEEDBACK (0x10) /* Feedback endpoint */ + #define ISOCH_IMPLICIT (0x20) /* Implicit feedback */ + #define ISOCH_RESERVED (0x30) /* Reserved */ + uint_8 wMaxPacketSize[2]; /* Bits 10:0 = max. packet size */ + /* For high-speed interrupt or isochronous only, additional + ** transaction opportunities per microframe follow.*/ + #define PACKET_SIZE_MASK (0x7FF) /* packet size bits */ + #define NO_ADDITONAL (0x0000) /* 1 / microframe */ + #define ONE_ADDITIONAL (0x0800) /* 2 / microframe */ + #define TWO_ADDITIONAL (0x1000) /* 3 / microframe */ + #define ADDITIONAL_MASK (ONE_ADDITIONAL | TWO_ADDITIONAL) + uint_8 iInterval; /* Polling interval in (micro) frames */ +} ENDPOINT_DESCRIPTOR, _PTR_ ENDPOINT_DESCRIPTOR_PTR; + +typedef struct usb_qualifier_descriptor +{ + uint_8 bLength; /* Descriptor size in bytes = 10 */ + uint_8 bDescriptorType; /* DEVICE QUALIFIER type = 6 */ + uint_8 bcdUSD[2]; /* USB spec in BCD, e.g. 0x0200 */ + uint_8 bDeviceClass; /* Class code, if 0 see interface */ + uint_8 bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint_8 bDeviceProtocol; /* Protocol, if 0 see interface */ + uint_8 bMaxPacketSize; /* Endpoint 0 max. size */ + uint_8 bNumConfigurations; /* Number of possible configurations */ + uint_8 bReserved; /* Reserved = 0 */ +} QUALIFIER_DESCRIPTOR, _PTR_ QUALIFIER_DESCRIPTOR_PTR; + +/* Other-Config type 7 fields are identical to type 2 above */ + +/* Interface-Power descriptor type 8 not used in this version */ + +typedef struct usb_otg_descriptor +{ + uint_8 bLength; /* Descriptor size in bytes = 9 */ + uint_8 bDescriptorType; /* CONFIGURATION type = 2 or 7 */ + uint_8 bmAttributes; /* OTG characteristics */ + #define OTG_SRP_SUPPORT (0x01) /* Supports SRP */ + #define OTG_HNP_SUPPORT (0x02) /* Supports HNP */ +} OTG_DESCRIPTOR, _PTR_ OTG_DESCRIPTOR_PTR; + +typedef union descriptor_union +{ + uint_32 word; + uint_8_ptr bufr; + pointer pntr; + DEVICE_DESCRIPTOR_PTR dvic; + CONFIGURATION_DESCRIPTOR_PTR cfig; + INTERFACE_DESCRIPTOR_PTR intf; + ENDPOINT_DESCRIPTOR_PTR ndpt; + QUALIFIER_DESCRIPTOR_PTR qual; + OTG_DESCRIPTOR_PTR otg; +} DESCRIPTOR_UNION, _PTR_ DESCRIPTOR_UNION_PTR; + +/* Prototypes */ + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint_32 usb_host_init(uint_8, uint_32, + _usb_host_handle _PTR_); +extern uint_32 _usb_host_open_pipe(_usb_host_handle, + PIPE_INIT_PARAM_STRUCT_PTR, _usb_pipe_handle _PTR_ ); + +#ifdef __cplusplus +} +#endif + +#endif /* __mvUsbDesc_h__ */ + +/* EOF */ diff --git a/board/mv_feroceon/mv_hal/usb/device/mvUsbDevCh9.c b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevCh9.c new file mode 100644 index 0000000..4e46477 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevCh9.c @@ -0,0 +1,301 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#include "usb/api/mvUsbDevApi.h" +#include "usb/device/mvUsbDevPrv.h" +#include "usb/api/mvUsbCh9.h" + +static volatile boolean ENTER_TEST_MODE = FALSE; +static volatile uint_16 test_mode_index = 0; + + +void mvUsbCh9GetStatus(_usb_device_handle handle, boolean setup, + SETUP_STRUCT* ctrl_req) +{ /* Body */ + uint_8 endpoint, direction; + uint_16 usb_status; + USB_DEV_STATE_STRUCT* usb_dev_ptr = (USB_DEV_STATE_STRUCT*)handle; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, "%s: setup=%d\n", __FUNCTION__, (int)setup); + + if(!setup) + return; + + switch (ctrl_req->REQUESTTYPE) + { + case (REQ_DIR_IN | REQ_RECIP_DEVICE): + /* Device request */ + _usb_device_get_status(handle, ARC_USB_STATUS_DEVICE, &usb_status); + break; + + case (REQ_DIR_IN | REQ_RECIP_INTERFACE): + /* Interface request */ + _usb_device_get_status(handle, ARC_USB_STATUS_INTERFACE, &usb_status); + break; + + case (REQ_DIR_IN | REQ_RECIP_ENDPOINT): + /* Endpoint request */ + endpoint = ctrl_req->INDEX & ARC_USB_STATUS_ENDPOINT_NUMBER_MASK; + if( (ctrl_req->INDEX & (1 << REQ_DIR_OFFSET)) == REQ_DIR_IN) + direction = ARC_USB_SEND; + else + direction = ARC_USB_RECV; + + usb_status = _usb_device_is_endpoint_stalled(handle, endpoint, direction); + break; + + default: + /* Unknown request */ + USB_printf("GetStatus: Unknown request type 0x%x\n", ctrl_req->REQUESTTYPE); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endswitch */ + + /* Send the requested data */ + *usb_dev_ptr->STATUS_PTR = USB_16BIT_LE(usb_status); + _usb_device_send_data(handle, 0, (uint_8_ptr)usb_dev_ptr->STATUS_PTR, sizeof(uint_16)); + + /* status phase */ + _usb_device_recv_data(handle, 0, NULL, 0); + + return; +} /* Endbody */ + +void mvUsbCh9ClearFeature(_usb_device_handle handle, boolean setup, + SETUP_STRUCT* setup_ptr) +{ /* Body */ + uint_8 endpoint, direction; + uint_16 usb_status; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, "%s: setup=%d\n", __FUNCTION__, (int)setup); + + _usb_device_get_status(handle, ARC_USB_STATUS_DEVICE_STATE, &usb_status); + if ((usb_status != ARC_USB_STATE_CONFIG) && (usb_status != ARC_USB_STATE_ADDRESS)) + { + USB_printf("ClearFeature: Wrong USB state %d\n", usb_status); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endif */ + + if(!setup) + return; + + switch (setup_ptr->REQUESTTYPE) + { + case (REQ_DIR_OUT | REQ_RECIP_DEVICE): + /* DEVICE */ + switch(setup_ptr->VALUE) + { + case DEVICE_REMOTE_WAKEUP: + /* clear remote wakeup */ + _usb_device_get_status(handle, ARC_USB_STATUS_DEVICE, &usb_status); + usb_status &= ~ARC_USB_REMOTE_WAKEUP; + _usb_device_set_status(handle, ARC_USB_STATUS_DEVICE, usb_status); + USB_printf("Clear REMOTE_WAKEUP feature\n"); + break; + + case DEVICE_TEST_MODE: + /* Exit Test Mode */ + _usb_device_set_status(handle, ARC_USB_STATUS_TEST_MODE, 0); + break; + + default: + USB_printf("ClearFeature: Unknown Device feature %d\n", + setup_ptr->VALUE); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endif */ + break; + + case (REQ_DIR_OUT | REQ_RECIP_ENDPOINT): + /* ENDPOINT */ + if (setup_ptr->VALUE != ENDPOINT_HALT) + { + USB_printf("ClearFeature: Wrong Endpoint feature %d\n", + setup_ptr->VALUE); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endif */ + + endpoint = setup_ptr->INDEX & ARC_USB_STATUS_ENDPOINT_NUMBER_MASK; + if( (setup_ptr->INDEX & (1 << REQ_DIR_OFFSET)) == REQ_DIR_IN) + direction = ARC_USB_SEND; + else + direction = ARC_USB_RECV; + + _usb_device_unstall_endpoint(handle, endpoint, direction); + break; + + default: + USB_printf("ClearFeature: Unknown REQUEST_TYPE %d\n", + setup_ptr->REQUESTTYPE); + + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endswitch */ + + /* status phase */ + _usb_device_send_data(handle, 0, 0, 0); +} + +void mvUsbCh9SetFeature(_usb_device_handle handle, boolean setup, + SETUP_STRUCT* setup_ptr) +{ + uint_16 usb_status; + uint_8 endpoint, direction; + USB_DEV_STATE_STRUCT* usb_dev_ptr = (USB_DEV_STATE_STRUCT*)handle; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, "%s: setup=%d\n", __FUNCTION__, (int)setup); + + if (setup) + { + switch (setup_ptr->REQUESTTYPE) + { + case (REQ_DIR_OUT | REQ_RECIP_DEVICE): + /* DEVICE */ + switch (setup_ptr->VALUE) + { + case DEVICE_REMOTE_WAKEUP: + /* set remote wakeup */ + _usb_device_get_status(handle, ARC_USB_STATUS_DEVICE, &usb_status); + usb_status |= ARC_USB_REMOTE_WAKEUP; + _usb_device_set_status(handle, ARC_USB_STATUS_DEVICE, usb_status); + USB_printf("Set REMOTE_WAKEUP feature\n"); + break; + + case DEVICE_TEST_MODE: + /* Test Mode */ + if( (setup_ptr->INDEX & 0x00FF) || (usb_dev_ptr->SPEED != ARC_USB_SPEED_HIGH) ) + { + USB_printf("SetFeature: Wrong Test mode parameters: mode=%d, speed=%d\n", + (setup_ptr->INDEX & 0x00FF), usb_dev_ptr->SPEED); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endif */ + + _usb_device_get_status(handle, ARC_USB_STATUS_DEVICE_STATE, &usb_status); + if( (usb_status == ARC_USB_STATE_CONFIG) || + (usb_status == ARC_USB_STATE_ADDRESS) || + (usb_status == ARC_USB_STATE_DEFAULT)) + { + /* wait with Set Test mode */ + ENTER_TEST_MODE = TRUE; + test_mode_index = (setup_ptr->INDEX & 0xFF00); + USB_printf("SetFeature: Prepare for Test mode 0x%x\n", test_mode_index); + } + else + { + USB_printf("SetFeature: Wrong USB state for Test mode: state=%d\n", + usb_status); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endif */ + break; + + default: + USB_printf("SetFeature: Unknown Device feature %d\n", + setup_ptr->VALUE); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endswitch */ + break; + + case (REQ_DIR_OUT | REQ_RECIP_ENDPOINT): + /* ENDPOINT */ + if (setup_ptr->VALUE != ENDPOINT_HALT) + { + USB_printf("SetFeature: Unknown Endpoint feature %d\n", + setup_ptr->VALUE); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endif */ + + endpoint = setup_ptr->INDEX & ARC_USB_STATUS_ENDPOINT_NUMBER_MASK; + if( (setup_ptr->INDEX & (1 << REQ_DIR_OFFSET)) == REQ_DIR_IN) + direction = ARC_USB_SEND; + else + direction = ARC_USB_RECV; + + _usb_device_stall_endpoint(handle, endpoint, direction); + break; + + default: + USB_printf("SetFeature: Unknown REQUEST_TYPE %d\n", + setup_ptr->REQUESTTYPE); + + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endswitch */ + + /* status phase */ + _usb_device_send_data(handle, 0, 0, 0); + } + else + { + if (ENTER_TEST_MODE) + { + /* Enter Test Mode */ + USB_printf("SetFeature: Activate Test mode 0x%x\n", test_mode_index); + _usb_device_set_status(handle, ARC_USB_STATUS_TEST_MODE, test_mode_index); + } /* Endif */ + } /* Endif */ +} + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9SetAddress +* Returned Value : None +* Comments : +* Chapter 9 SetAddress command +* We setup a TX packet of 0 length ready for the IN token +* Once we get the TOK_DNE interrupt for the IN token, then +* we change the ADDR register and go to the ADDRESS state. +* +*END*--------------------------------------------------------------------*/ +void mvUsbCh9SetAddress(_usb_device_handle handle, + boolean setup, SETUP_STRUCT* setup_ptr) +{ /* Body */ + static uint_8 new_address; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_ADDR, "usbDisk %s: setup=%d, address=%d\n", + __FUNCTION__, (int)setup, setup_ptr->VALUE); + + if (setup) + { + new_address = setup_ptr->VALUE; + /******************************************************* + * if hardware assitance is enabled for set_address (see + * hardware rev for details) we need to do the set_address + * before queuing the status phase. + *******************************************************/ +#ifdef SET_ADDRESS_HARDWARE_ASSISTANCE + _usb_device_set_status(handle, ARC_USB_STATUS_ADDRESS, new_address); +#endif + /* ack */ + _usb_device_send_data(handle, 0, 0, 0); + } + else + { +#ifndef SET_ADDRESS_HARDWARE_ASSISTANCE + _usb_device_set_status(handle, ARC_USB_STATUS_ADDRESS, new_address); +#endif + _usb_device_set_status(handle, ARC_USB_STATUS_DEVICE_STATE, ARC_USB_STATE_ADDRESS); + } +} diff --git a/board/mv_feroceon/mv_hal/usb/device/mvUsbDevMain.c b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevMain.c new file mode 100644 index 0000000..8ba6fdc --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevMain.c @@ -0,0 +1,773 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "usb/api/mvUsbDevApi.h" +#include "usb/device/mvUsbDevPrv.h" + +USB_IMPORT_FUNCS* global_import_funcs = NULL; + +#ifdef USB_UNDERRUN_WA +USB_WA_FUNCS* global_wa_funcs = NULL; +int global_wa_threshold = 64; +int global_wa_sram_parts = 2; +#endif /* USB_UNDERRUN_WA */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_cleanup +* Returned Value : void +* Comments : +* Cleanup allocated structures. +* +*END*-----------------------------------------------------------------*/ + +static void _usb_device_cleanup(USB_DEV_STATE_STRUCT_PTR usb_dev_ptr) +{ + /* Free all internal transfer descriptors */ + if(usb_dev_ptr->XD_BASE != NULL) + { + USB_memfree((pointer)usb_dev_ptr->XD_BASE); + } + + /* Free all XD scratch memory */ + if(usb_dev_ptr->XD_SCRATCH_STRUCT_BASE != NULL) + { + USB_memfree((pointer)usb_dev_ptr->XD_SCRATCH_STRUCT_BASE); + } + /* Free the temp ep init XD */ + if(usb_dev_ptr->TEMP_XD_PTR != NULL) + { + USB_memfree((pointer)usb_dev_ptr->TEMP_XD_PTR); + } + + if(usb_dev_ptr->STATUS_UNAIGNED_PTR != NULL) + USB_memfree((pointer)usb_dev_ptr->STATUS_UNAIGNED_PTR); + + if(usb_dev_ptr->TEST_PKT_UNAIGNED_PTR != NULL) + USB_memfree((pointer)usb_dev_ptr->TEST_PKT_UNAIGNED_PTR); + + /* Free the USB state structure */ + USB_memfree((pointer)usb_dev_ptr); +} + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_free_XD +* Returned Value : void +* Comments : +* Enqueues a XD onto the free XD ring. +* +*END*-----------------------------------------------------------------*/ + +void _usb_device_free_XD + ( + /* [IN] the dTD to enqueue */ + pointer xd_ptr + ) +{ /* Body */ + int lockKey; + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)(((XD_STRUCT_PTR)xd_ptr)->SCRATCH_PTR->PRIVATE); + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_TRACE, "free_XD: xd_ptr=0x%x\n", (unsigned)xd_ptr); + + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.free_XD_count++)); + + /* + ** This function can be called from any context, and it needs mutual + ** exclusion with itself. + */ + + lockKey = USB_lock(); + + /* + ** Add the XD to the free XD queue (linked via PRIVATE) and + ** increment the tail to the next descriptor + */ + USB_XD_QADD(usb_dev_ptr->XD_HEAD, usb_dev_ptr->XD_TAIL, (XD_STRUCT_PTR)xd_ptr); + usb_dev_ptr->XD_ENTRIES++; + + USB_unlock(lockKey); + +} /* Endbody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_set_bsp_funcs +* Returned Value : NONE +* Comments : +* Set pointer to structure of imported BSP functions +* +*END*-----------------------------------------------------------------*/ +void _usb_device_set_bsp_funcs(USB_IMPORT_FUNCS* pBspFuncs) +{ + static boolean isFirst = TRUE; + + if(isFirst) + { + global_import_funcs = pBspFuncs; + _usb_debug_init_trace_log(); + isFirst = FALSE; + } +} + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_get_max_endpoint +* Returned Value : handle or NULL +* Comments : +* Return maximum number of endpoints supportedby USB device +* (for DEBUG only) +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_device_get_max_endpoint(_usb_device_handle handle) +{ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + return usb_dev_ptr->MAX_ENDPOINTS; +} + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_get_dev_num +* Returned Value : handle or NULL +* Comments : +* Return unique USB device number +* (for DEBUG only) +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_device_get_dev_num(_usb_device_handle handle) +{ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + return usb_dev_ptr->DEV_NUM; +} + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_init +* Returned Value : USB_OK or error code +* Comments : +* Initializes the USB device specific data structures and calls +* the low-level device controller chip initialization routine. +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_device_init + ( + /* [IN] the USB device controller to initialize */ + uint_8 devnum, + + /* [OUT] the USB_USB_dev_initialize state structure */ + _usb_device_handle* handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + XD_STRUCT_PTR xd_ptr; + uint_8 i, error; + SCRATCH_STRUCT_PTR temp_scratch_ptr; + + /* global_import_funcs must be initailized before */ + if(global_import_funcs == NULL) + return USBERR_INIT_FAILED; + + if (devnum > MAX_USB_DEVICES) + { + USB_printf("_usb_device_init, error invalid device number"); + return USBERR_INVALID_DEVICE_NUM; + } /* Endif */ + + /* Allocate memory for the state structure */ + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)USB_memalloc(sizeof(USB_DEV_STATE_STRUCT)); + if (usb_dev_ptr == NULL) + { + USB_printf("_usb_device_init, malloc of %d bytes for USB_DEV_STATE_STRUCT failed\n", + sizeof(USB_DEV_STATE_STRUCT)); + return USBERR_ALLOC_STATE; + } /* Endif */ + + /* Zero out the internal USB state structure */ + USB_memzero(usb_dev_ptr, sizeof(USB_DEV_STATE_STRUCT)); + + usb_dev_ptr->DEV_NUM = devnum; + + /* Multiple devices will have different base addresses and + ** interrupt vectors (For future) + */ + usb_dev_ptr->USB_STATE = ARC_USB_STATE_UNKNOWN; + + /* Allocate MAX_XDS_FOR_TR_CALLS */ + xd_ptr = (XD_STRUCT_PTR)USB_memalloc(sizeof(XD_STRUCT) * MAX_XDS_FOR_TR_CALLS); + if (xd_ptr == NULL) + { + _usb_device_cleanup(usb_dev_ptr); + USB_printf("_usb_device_init, malloc of %d bytes for %d XD_STRUCT failed\n", + sizeof(XD_STRUCT) * MAX_XDS_FOR_TR_CALLS, MAX_XDS_FOR_TR_CALLS); + return USBERR_ALLOC_TR; + } /* Endif */ + + usb_dev_ptr->XD_BASE = xd_ptr; + + _usb_clear_stats(usb_dev_ptr); + + USB_memzero(xd_ptr, sizeof(XD_STRUCT) * MAX_XDS_FOR_TR_CALLS); + + /* Allocate memory for internal scratch structure */ + usb_dev_ptr->XD_SCRATCH_STRUCT_BASE = (SCRATCH_STRUCT_PTR) + USB_memalloc(sizeof(SCRATCH_STRUCT) * MAX_XDS_FOR_TR_CALLS); + if (usb_dev_ptr->XD_SCRATCH_STRUCT_BASE == NULL) + { + _usb_device_cleanup(usb_dev_ptr); + USB_printf("_usb_device_init, malloc of %d bytes for %d XD_STRUCT failed\n", + sizeof(SCRATCH_STRUCT) * MAX_XDS_FOR_TR_CALLS, MAX_XDS_FOR_TR_CALLS); + return USBERR_ALLOC; + } /* Endif */ + + temp_scratch_ptr = usb_dev_ptr->XD_SCRATCH_STRUCT_BASE; + usb_dev_ptr->XD_HEAD = NULL; + usb_dev_ptr->XD_TAIL = NULL; + usb_dev_ptr->XD_ENTRIES = 0; + + /* Enqueue all the XDs */ + for (i=0;iSCRATCH_PTR = temp_scratch_ptr; + xd_ptr->SCRATCH_PTR->FREE = _usb_device_free_XD; + xd_ptr->SCRATCH_PTR->PRIVATE = (pointer)usb_dev_ptr; + _usb_device_free_XD((pointer)xd_ptr); + xd_ptr++; + temp_scratch_ptr++; + } /* Endfor */ + + usb_dev_ptr->TEMP_XD_PTR = (XD_STRUCT_PTR)USB_memalloc(sizeof(XD_STRUCT)); + if(usb_dev_ptr->TEMP_XD_PTR == NULL) + { + USB_printf("_usb_device_init, malloc of %d bytes for TEMP_XD_STRUCT failed\n", + sizeof(XD_STRUCT)); + _usb_device_cleanup(usb_dev_ptr); + return USBERR_ALLOC; + } + USB_memzero(usb_dev_ptr->TEMP_XD_PTR, sizeof(XD_STRUCT)); + + /* Allocate 2 bytes for USB_STATUS to be sent over USB, so Cache line aligned */ + usb_dev_ptr->STATUS_UNAIGNED_PTR = (uint_8*)USB_memalloc(sizeof(uint_16) + PSP_CACHE_LINE_SIZE); + if(usb_dev_ptr->STATUS_UNAIGNED_PTR == NULL) + { + USB_printf("_usb_device_init, malloc of %d bytes for USB_STATUS failed\n", + sizeof(uint_16) + PSP_CACHE_LINE_SIZE); + _usb_device_cleanup(usb_dev_ptr); + return USBERR_ALLOC; + } + USB_memzero(usb_dev_ptr->STATUS_UNAIGNED_PTR, sizeof(uint_16) + PSP_CACHE_LINE_SIZE); + usb_dev_ptr->STATUS_PTR = (uint_16*)USB_CACHE_ALIGN((uint_32)usb_dev_ptr->STATUS_UNAIGNED_PTR); + + /* Allocate 53 bytes for USB Test packet to be sent over USB, so Cache line aligned */ + usb_dev_ptr->TEST_PKT_UNAIGNED_PTR = (uint_8*)USB_memalloc(USB_TEST_MODE_TEST_PACKET_LENGTH + PSP_CACHE_LINE_SIZE); + if(usb_dev_ptr->TEST_PKT_UNAIGNED_PTR == NULL) + { + USB_printf("_usb_device_init, malloc of %d bytes for USB Test packet failed\n", + USB_TEST_MODE_TEST_PACKET_LENGTH + PSP_CACHE_LINE_SIZE); + _usb_device_cleanup(usb_dev_ptr); + return USBERR_ALLOC; + } + USB_memzero(usb_dev_ptr->TEST_PKT_UNAIGNED_PTR, USB_TEST_MODE_TEST_PACKET_LENGTH + PSP_CACHE_LINE_SIZE); + usb_dev_ptr->TEST_PKT_PTR = (uint_8*)USB_CACHE_ALIGN((uint_32)usb_dev_ptr->TEST_PKT_UNAIGNED_PTR); + + /* Initialize the USB controller chip */ + error = _usb_dci_vusb20_init(devnum, usb_dev_ptr); + if (error) + { + _usb_device_cleanup(usb_dev_ptr); + USB_printf("_usb_device_init, init failed"); + return USBERR_INIT_FAILED; + } /* Endif */ + + USB_printf("device_init: pDev=0x%x, pXD(%d)=0x%x, pSCRATCH(%d)=0x%x, pTempXD=0x%x\n", + (unsigned)usb_dev_ptr, MAX_XDS_FOR_TR_CALLS, (unsigned)usb_dev_ptr->XD_BASE, + MAX_XDS_FOR_TR_CALLS, (unsigned)usb_dev_ptr->XD_SCRATCH_STRUCT_BASE, + (unsigned)usb_dev_ptr->TEMP_XD_PTR); + + *handle = usb_dev_ptr; + return USB_OK; +} /* EndBody */ + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_shutdown +* Returned Value : USB_OK or error code +* Comments : +* Shutdown an initialized USB device +* +*END*-----------------------------------------------------------------*/ +void _usb_device_shutdown(_usb_device_handle handle) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + SERVICE_STRUCT_PTR service_ptr; + int ep; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_CTRL, "shutdown\n"); + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + for(ep=0; ep<(usb_dev_ptr->MAX_ENDPOINTS); ep++) + { + /* Cancel all transfers on all endpoints */ + while(_usb_device_get_transfer_status(handle, ep, ARC_USB_RECV) != + ARC_USB_STATUS_IDLE) + { + _usb_device_cancel_transfer(handle, ep, ARC_USB_RECV); + } + while(_usb_device_get_transfer_status(handle, ep, ARC_USB_SEND) != + ARC_USB_STATUS_IDLE) + { + _usb_device_cancel_transfer(handle, ep, ARC_USB_SEND); + } + } + _usb_dci_vusb20_shutdown(usb_dev_ptr); + + /* Free all the Callback function structure memory */ + for( service_ptr = usb_dev_ptr->SERVICE_HEAD_PTR; service_ptr; + service_ptr = service_ptr->NEXT) + { + USB_printf("_usb_device_shutdown: free service_ptr = 0x%x\n", + service_ptr); + USB_memfree(service_ptr); + } + usb_dev_ptr->SERVICE_HEAD_PTR = NULL; + + _usb_device_cleanup(usb_dev_ptr); +} /* EndBody */ + + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _usb_device_register_service +* Returned Value : USB_OK or error code +* Comments : +* Registers a callback routine for a specified event or endpoint. +* +*END*--------------------------------------------------------------------*/ +uint_8 _usb_device_register_service + ( + /* [IN] Handle to the USB device */ + _usb_device_handle handle, + + /* [IN] type of event or endpoint number to service */ + uint_8 type, + + /* [IN] Pointer to the service's callback function */ + void(_CODE_PTR_ service)(pointer, uint_8, boolean, uint_8, uint_8_ptr, uint_32, uint_8) + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + SERVICE_STRUCT_PTR service_ptr; + SERVICE_STRUCT_PTR _PTR_ search_ptr; + int lockKey; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + /* Needs mutual exclusion */ + lockKey = USB_lock(); + + /* Search for an existing entry for type */ + for (search_ptr = &usb_dev_ptr->SERVICE_HEAD_PTR; + *search_ptr; + search_ptr = &(*search_ptr)->NEXT) + { + if ((*search_ptr)->TYPE == type) + { + /* Found an existing entry */ + USB_unlock(lockKey); + USB_printf("_usb_device_register_service, service %d already opened\n"); + return USBERR_OPEN_SERVICE; + } /* Endif */ + } /* Endfor */ + + /* No existing entry found - create a new one */ + service_ptr = (SERVICE_STRUCT_PTR)USB_memalloc(sizeof(SERVICE_STRUCT)); + if (!service_ptr) + { + USB_unlock(lockKey); + USB_printf("_usb_device_register_service, malloc for %d bytes failed\n", + sizeof(SERVICE_STRUCT)); + return USBERR_ALLOC; + } /* Endif */ + + service_ptr->TYPE = type; + service_ptr->SERVICE = service; + service_ptr->NEXT = NULL; + *search_ptr = service_ptr; + + USB_unlock(lockKey); + + return USB_OK; +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _usb_device_unregister_service +* Returned Value : USB_OK or error code +* Comments : +* Unregisters a callback routine for a specified event or endpoint. +* +*END*--------------------------------------------------------------------*/ +uint_8 _usb_device_unregister_service + ( + /* [IN] Handle to the USB device */ + _usb_device_handle handle, + + /* [IN] type of event or endpoint number to service */ + uint_8 type + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + SERVICE_STRUCT_PTR service_ptr; + SERVICE_STRUCT_PTR _PTR_ search_ptr; + int lockKey; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + /* Needs mutual exclusion */ + lockKey = USB_lock(); + + /* Search for an existing entry for type */ + for (search_ptr = &usb_dev_ptr->SERVICE_HEAD_PTR; + *search_ptr; + search_ptr = &(*search_ptr)->NEXT) + { + if ((*search_ptr)->TYPE == type) { + /* Found an existing entry - delete it */ + break; + } /* Endif */ + } /* Endfor */ + + /* No existing entry found */ + if (!*search_ptr) + { + USB_unlock(lockKey); + USB_printf("_usb_device_unregister_service, no service found\n"); + return USBERR_CLOSED_SERVICE; + } /* Endif */ + + service_ptr = *search_ptr; + *search_ptr = service_ptr->NEXT; + + USB_memfree((pointer)service_ptr); + + USB_unlock(lockKey); + + return USB_OK; + +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _usb_device_call_service +* Returned Value : USB_OK or error code +* Comments : +* Calls the appropriate service for the specified type, if one is +* registered. Used internally only. +* +*END*--------------------------------------------------------------------*/ +uint_8 _usb_device_call_service + ( + /* [IN] Handle to the USB device */ + _usb_device_handle handle, + + /* [OUT] Type of service or endpoint */ + uint_8 type, + + /* [OUT] Is it a Setup transfer? */ + boolean setup, + + /* [OUT] Direction of transmission; is it a Transmit? */ + boolean direction, + + /* [OUT] Pointer to the data */ + uint_8_ptr buffer_ptr, + + /* [OUT] Number of bytes in transmission */ + uint_32 length, + + /* [OUT] Any errors */ + uint_8 errors + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + SERVICE_STRUCT _PTR_ service_ptr; + int lockKey; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + /* Needs mutual exclusion */ + lockKey = USB_lock(); + + /* Search for an existing entry for type */ + for (service_ptr = usb_dev_ptr->SERVICE_HEAD_PTR; + service_ptr; + service_ptr = service_ptr->NEXT) + { + if (service_ptr->TYPE == type) + { +#ifdef CONFIG_MV_SP_I_FTCH_DB_INV + if( (direction == ARC_USB_RECV) && (buffer_ptr != NULL) && (length > 0) ) + USB_dcache_inv( buffer_ptr, length); +#endif /* CONFIG_MV_SP_I_FTCH_DB_INV */ + + service_ptr->SERVICE(handle, type, setup, direction, buffer_ptr, length, errors); + USB_unlock(lockKey); + + return USB_OK; + } /* Endif */ + + } /* Endfor */ + + USB_unlock(lockKey); + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_CTRL, "_usb_device_call_service, service %d is closed\n", type); + + return USBERR_CLOSED_SERVICE; +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_init_endpoint +* Returned Value : USB_OK or error code +* Comments : +* Initializes the endpoint and the data structures associated with the +* endpoint +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_device_init_endpoint + ( + /* [IN] the USB_USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] MAX Packet size for this endpoint */ + uint_16 max_pkt_size, + + /* [IN] Direction */ + uint_8 direction, + + /* [IN] Type of Endpoint */ + uint_8 type, + + /* [IN] After all data is transfered, should we terminate the transfer + ** with a zero length packet if the last packet size == MAX_PACKET_SIZE? + */ + uint_8 flag + ) +{ /* Body */ + + int lockKey; + uint_8 error = 0; + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + /* Initialize the transfer descriptor */ + usb_dev_ptr->TEMP_XD_PTR->EP_NUM = ep_num; + usb_dev_ptr->TEMP_XD_PTR->BDIRECTION = direction; + usb_dev_ptr->TEMP_XD_PTR->WMAXPACKETSIZE = max_pkt_size; + usb_dev_ptr->TEMP_XD_PTR->EP_TYPE = type; + usb_dev_ptr->TEMP_XD_PTR->DONT_ZERO_TERMINATE = flag; + usb_dev_ptr->TEMP_XD_PTR->MAX_PKTS_PER_UFRAME = + ((flag & ARC_USB_MAX_PKTS_PER_UFRAME) >> 1); + + lockKey = USB_lock(); + error = _usb_dci_vusb20_init_endpoint(handle, usb_dev_ptr->TEMP_XD_PTR); + USB_unlock(lockKey); + + return error; + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_deinit_endpoint +* Returned Value : USB_OK or error code +* Comments : +* Disables the endpoint and the data structures associated with the +* endpoint +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_device_deinit_endpoint + ( + /* [IN] the USB_USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] Direction */ + uint_8 direction + ) +{ /* Body */ + int lockKey; + uint_8 error = 0; + lockKey = USB_lock(); + + error = _usb_dci_vusb20_deinit_endpoint(handle, ep_num, direction); + + USB_unlock(lockKey); + + return error; +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_get_transfer_status +* Returned Value : Status of the transfer +* Comments : +* returns the status of the transaction on the specified endpoint. +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_device_get_transfer_status + ( + /* [IN] the USB_USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] direction */ + uint_8 direction + ) +{ /* Body */ + uint_8 status; + int lockKey; + + lockKey = USB_lock(); + + status = _usb_dci_vusb20_get_transfer_status(handle, ep_num, direction); + + USB_unlock(lockKey); + + /* Return the status of the last queued transfer */ + return (status); + +} /* EndBody */ + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_read_setup_data +* Returned Value : USB_OK or error code +* Comments : +* Reads the setup data from the hardware +* +*END*-----------------------------------------------------------------*/ +void _usb_device_read_setup_data + ( + /* [IN] the USB_USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] buffer for receiving Setup packet */ + uint_8_ptr buff_ptr + ) +{ /* Body */ + int lockKey; + + lockKey = USB_lock(); + + _usb_dci_vusb20_get_setup_data(handle, ep_num, buff_ptr); + + USB_unlock(lockKey); + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_cancel_transfer +* Returned Value : USB_OK or error code +* Comments : +* returns the status of the transaction on the specified endpoint. +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_device_cancel_transfer + ( + /* [IN] the USB_USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] direction */ + uint_8 direction + ) +{ /* Body */ + uint_8 error = USB_OK; + int lockKey; + + lockKey = USB_lock(); + + /* Cancel transfer on the specified endpoint for the specified + ** direction + */ + error = _usb_dci_vusb20_cancel_transfer(handle, ep_num, direction); + + USB_unlock(lockKey); + + return error; +} /* EndBody */ + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_stop +* Returned Value : None +* Comments : +* Stop USB device +* +*END*-----------------------------------------------------------------*/ +void _usb_device_stop(_usb_device_handle handle) +{ + int lockKey; + + lockKey = USB_lock(); + _usb_dci_vusb20_stop(handle); + USB_unlock(lockKey); +} + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_start +* Returned Value : None +* Comments : +* Start USB device +* +*END*-----------------------------------------------------------------*/ +void _usb_device_start(_usb_device_handle handle) +{ + int lockKey; + + lockKey = USB_lock(); + _usb_dci_vusb20_start(handle); + USB_unlock(lockKey); +} diff --git a/board/mv_feroceon/mv_hal/usb/device/mvUsbDevPrv.h b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevPrv.h new file mode 100644 index 0000000..597bdcf --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevPrv.h @@ -0,0 +1,267 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#ifndef __mvUsbDevPrv_h__ +#define __mvUsbDevPrv_h__ + +#include "usb/common/mvUsbCore.h" + + +#define USB_TEST_MODE_TEST_PACKET_LENGTH (53) + + +#define USB_XD_QADD(head,tail,XD) \ + if ((head) == NULL) { \ + (head) = (XD); \ + } else { \ + (tail)->SCRATCH_PTR->PRIVATE = (XD); \ + } /* Endif */ \ + (tail) = (XD); \ + (XD)->SCRATCH_PTR->PRIVATE = NULL + +#define USB_XD_QGET(head,tail,XD) \ + (XD) = (head); \ + if (head) { \ + (head) = (XD_STRUCT_PTR)((head)->SCRATCH_PTR->PRIVATE); \ + if ((head) == NULL) { \ + (tail) = NULL; \ + } /* Endif */ \ + } /* Endif */ + +#define EHCI_DTD_QADD(head,tail,dTD) \ + if ((head) == NULL) { \ + (head) = (dTD); \ + } else { \ + (tail)->SCRATCH_PTR->PRIVATE = (void *) (dTD); \ + } /* Endif */ \ + (tail) = (dTD); \ + (dTD)->SCRATCH_PTR->PRIVATE = NULL + +#define EHCI_DTD_QGET(head,tail,dTD) \ + (dTD) = (head); \ + if (head) { \ + (head) = (head)->SCRATCH_PTR->PRIVATE; \ + if ((head) == NULL) { \ + (tail) = NULL; \ + } /* Endif */ \ + } /* Endif */ + +/*************************************** +** +** Data structures +** +*/ + +typedef struct +{ + uint_32 usb_isr_count; + uint_32 usb_reset_count; + uint_32 usb_send_count; + uint_32 usb_recv_count; + uint_32 usb_setup_count; + uint_32 free_XD_count; + uint_32 free_dTD_count; + uint_32 usb_cancel_count; + uint_32 usb_add_count; + uint_32 usb_add_not_empty_count; + uint_32 usb_empty_isr_count; + uint_32 usb_empty_complete_count; + uint_32 usb_read_setup_count; + uint_32 usb_complete_isr_count; + uint_32 usb_complete_count; + uint_32 usb_complete_max_count; + uint_32 usb_port_change_count; + uint_32 usb_suspend_count; + uint_32 usb_complete_ep_count[ARC_USB_MAX_ENDPOINTS*2]; + +} USB_STATS; + + + +/* Callback function storage structure */ +typedef struct service_struct +{ + uint_8 TYPE; + void (_CODE_PTR_ SERVICE)(pointer, uint_8, boolean, uint_8, uint_8_ptr, uint_32, uint_8); + struct service_struct _PTR_ NEXT; + +} SERVICE_STRUCT, _PTR_ SERVICE_STRUCT_PTR; + +typedef struct xd_struct +{ + uint_8 EP_NUM; /* Endpoint number */ + uint_8 BDIRECTION; /* Direction : Send/Receive */ + uint_8 EP_TYPE; /* Type of the endpoint: Ctrl, Isoch, Bulk, Int */ + uint_8 BSTATUS; /* Current transfer status */ + uint_8_ptr WSTARTADDRESS; /* Address of first byte */ + uint_32 WTOTALLENGTH; /* Number of bytes to send/recv */ + uint_32 WSOFAR; /* Number of bytes recv'd so far */ + uint_16 WMAXPACKETSIZE; /* Max Packet size */ + boolean DONT_ZERO_TERMINATE; + uint_8 MAX_PKTS_PER_UFRAME; + SCRATCH_STRUCT *SCRATCH_PTR; +} XD_STRUCT, _PTR_ XD_STRUCT_PTR; + +/* The USB Device State Structure */ +typedef struct +{ + boolean BUS_RESETTING; /* Device is + ** being reset */ + volatile VUSB20_REG_STRUCT_PTR CAP_REGS_PTR; /* Capabilities registers */ + + volatile VUSB20_REG_STRUCT_PTR DEV_PTR; /* Device Controller + ** Register base + ** address */ + + SERVICE_STRUCT_PTR SERVICE_HEAD_PTR; /* Head struct + ** address of + ** registered services + */ + XD_STRUCT_PTR TEMP_XD_PTR; /* Temp xd for ep init */ + XD_STRUCT_PTR XD_BASE; + XD_STRUCT_PTR XD_HEAD; /* Head Transaction + ** descriptors + */ + XD_STRUCT_PTR XD_TAIL; /* Tail Transaction + ** descriptors + */ + uint_32 XD_ENTRIES; + uint_8* EP_QUEUE_HEAD_BASE; + uint_32 EP_QUEUE_HEAD_PHYS; + uint_32 EP_QUEUE_HEAD_SIZE; + VUSB20_EP_QUEUE_HEAD_STRUCT_PTR EP_QUEUE_HEAD_PTR; /* Endpoint Queue head */ + + uint_8* DTD_BASE_PTR; /* Device transfer descriptor pool address */ + uint_32 DTD_BASE_PHYS; + uint_32 DTD_SIZE; + VUSB20_EP_TR_STRUCT_PTR DTD_ALIGNED_BASE_PTR;/* Aligned transfer descriptor pool address */ + + VUSB20_EP_TR_STRUCT_PTR DTD_HEAD; + VUSB20_EP_TR_STRUCT_PTR DTD_TAIL; + VUSB20_EP_TR_STRUCT_PTR EP_DTD_HEADS[ARC_USB_MAX_ENDPOINTS * 2]; + VUSB20_EP_TR_STRUCT_PTR EP_DTD_TAILS[ARC_USB_MAX_ENDPOINTS * 2]; + SCRATCH_STRUCT_PTR XD_SCRATCH_STRUCT_BASE; + + + SCRATCH_STRUCT_PTR SCRATCH_STRUCT_BASE; + + uint_16 USB_STATE; + uint_16 USB_DEVICE_STATE; + uint_16 USB_SOF_COUNT; + uint_16 DTD_ENTRIES; + uint_16 ERRORS; + uint_16 ERROR_STATE; + uint_16 USB_DEV_STATE_B4_SUSPEND; + uint_8 DEV_NUM; /* USB device number + ** on the board + */ + uint_8 SPEED; /* Low Speed, + ** High Speed, + ** Full Speed + */ + uint_8 MAX_ENDPOINTS; /* Max endpoints + ** supported by this + ** device + */ + + uint_8 USB_CURR_CONFIG; + uint_8 DEVICE_ADDRESS; + uint_8 FORCE_FS; + USB_STATS STATS; + + uint_8* STATUS_UNAIGNED_PTR; + uint_16* STATUS_PTR; + + uint_8* TEST_PKT_UNAIGNED_PTR; + uint_8* TEST_PKT_PTR; + +} USB_DEV_STATE_STRUCT, _PTR_ USB_DEV_STATE_STRUCT_PTR; + +/* ONLY For data bases allocated by the driver (when PHYS and VIRT bases are known) */ +#define USB_EP_QH_VIRT_TO_PHYS(handle, virtAddr) \ + (((virtAddr) == NULL) ? 0 : ((handle)->EP_QUEUE_HEAD_PHYS + \ + ((uint_32)(virtAddr) - (uint_32)(handle)->EP_QUEUE_HEAD_BASE))) + +#define USB_DTD_VIRT_TO_PHYS(handle, virtAddr) \ + (((virtAddr) == NULL) ? 0 : ((handle)->DTD_BASE_PHYS + \ + ((uint_32)(virtAddr) - (uint_32)(handle)->DTD_BASE_PTR))) + +#define USB_DTD_PHYS_TO_VIRT(handle, physAddr) \ + (((physAddr) == 0) ? NULL : ((handle)->DTD_BASE_PTR + \ + ((physAddr) - (handle)->DTD_BASE_PHYS))) + + +/*************************************** +** +** Prototypes +** +*/ +#ifdef __cplusplus +extern "C" { +#endif + +extern uint_8 _usb_device_call_service(void* handle, uint_8, boolean, + boolean, uint_8_ptr, uint_32, uint_8); + +extern uint_8 _usb_dci_vusb20_init(uint_8, _usb_device_handle); +extern void _usb_device_free_XD(pointer); +extern void _usb_dci_vusb20_free_dTD(pointer); +extern uint_8 _usb_dci_vusb20_add_dTD(_usb_device_handle, XD_STRUCT_PTR); +extern uint_8 _usb_dci_vusb20_cancel_transfer(_usb_device_handle, uint_8, uint_8); +extern uint_8 _usb_dci_vusb20_get_transfer_status(_usb_device_handle, uint_8, uint_8); +extern XD_STRUCT_PTR _usb_dci_vusb20_get_transfer_details(_usb_device_handle, uint_8, uint_8); +extern void _usb_dci_vusb20_process_tr_complete(_usb_device_handle); +extern void _usb_dci_vusb20_process_reset(_usb_device_handle); +extern void _usb_dci_vusb20_process_tr_complete(_usb_device_handle); +extern void _usb_dci_vusb20_process_suspend(_usb_device_handle); +extern void _usb_dci_vusb20_process_SOF(_usb_device_handle); +extern void _usb_dci_vusb20_process_port_change(_usb_device_handle); +extern void _usb_dci_vusb20_process_error(_usb_device_handle); +extern void _usb_dci_vusb20_shutdown(_usb_device_handle); +extern void _usb_dci_vusb20_set_speed_full(_usb_device_handle, uint_8); +extern void _usb_dci_vusb20_suspend_phy(_usb_device_handle, uint_8); +extern void _usb_dci_vusb20_hnp_shutdown(void); +extern void _usb_dci_vusb20_set_address(_usb_device_handle, uint_8); +extern void _usb_dci_vusb20_get_setup_data(_usb_device_handle, uint_8, uint_8_ptr); +extern void _usb_dci_vusb20_assert_resume(_usb_device_handle); +extern uint_8 _usb_dci_vusb20_init_endpoint(_usb_device_handle, XD_STRUCT_PTR); +extern void _usb_dci_vusb20_stall_endpoint(_usb_device_handle, uint_8, uint_8); +extern void _usb_dci_vusb20_unstall_endpoint(_usb_device_handle, uint_8, uint_8); +extern uint_8 _usb_dci_vusb20_is_endpoint_stalled(_usb_device_handle, uint_8, uint_8); +extern uint_8 _usb_dci_vusb20_deinit_endpoint(_usb_device_handle, uint_8, uint_8); +extern void _usb_dci_vusb20_chip_initialize(_usb_device_handle); +extern void _usb_dci_vusb20_stop(_usb_device_handle handle); +extern void _usb_dci_vusb20_start(_usb_device_handle handle); + +#if defined(USB_UNDERRUN_WA) + +extern uint_8* usbSramBase; +extern int usbSramSize; + +void _usb_reset_send_queue(void); +void usbSendComplete(void* handle, uint_8 type, boolean setup, uint_8 dir, + uint_8_ptr buffer, uint_32 length, uint_8 error); +#endif /* USB_UNDERRUN_WA */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/board/mv_feroceon/mv_hal/usb/device/mvUsbDevRecv.c b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevRecv.c new file mode 100644 index 0000000..15f8dac --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevRecv.c @@ -0,0 +1,99 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#include "usb/api/mvUsbDevApi.h" +#include "usb/device/mvUsbDevPrv.h" + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_recv_data +* Returned Value : USB_OK or error code +* Comments : +* Receives data on a specified endpoint. +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_device_recv_data + ( + /* [IN] the USB_USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] buffer to receive data */ + uint_8_ptr buff_ptr, + + /* [IN] length of the transfer */ + uint_32 size + ) +{ /* Body */ + int lockKey; + uint_8 error = USB_OK; + XD_STRUCT_PTR xd_ptr; + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_RX, "recv_data: ep=%d, buf_ptr=0x%x, size=%d\n", + ep_num, (unsigned)buff_ptr, (int)size); + + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_recv_count++)); + + if(buff_ptr != NULL) + USB_dcache_inv((pointer)buff_ptr,size); + + lockKey = USB_lock(); + + if (!usb_dev_ptr->XD_ENTRIES) + { + USB_unlock(lockKey); + USB_printf("_usb_device_recv_data, transfer in progress\n"); + return ARC_USB_STATUS_TRANSFER_IN_PROGRESS; + } /* Endif */ + + /* Get a transfer descriptor for the specified endpoint + ** and direction + */ + USB_XD_QGET(usb_dev_ptr->XD_HEAD, usb_dev_ptr->XD_TAIL, xd_ptr); + + usb_dev_ptr->XD_ENTRIES--; + + /* Initialize the new transfer descriptor */ + xd_ptr->EP_NUM = ep_num; + xd_ptr->BDIRECTION = ARC_USB_RECV; + xd_ptr->WTOTALLENGTH = size; + xd_ptr->WSOFAR = 0; + xd_ptr->WSTARTADDRESS = buff_ptr; + + xd_ptr->BSTATUS = ARC_USB_STATUS_TRANSFER_ACCEPTED; + + error = _usb_dci_vusb20_add_dTD(handle, xd_ptr); + + USB_unlock(lockKey); + + if (error) + { + USB_printf("_usb_device_recv_data, receive failed\n"); + return USBERR_RX_FAILED; + } /* Endif */ + + return error; + +} /* EndBody */ diff --git a/board/mv_feroceon/mv_hal/usb/device/mvUsbDevSend.c b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevSend.c new file mode 100644 index 0000000..3481e30 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevSend.c @@ -0,0 +1,373 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#include "usb/api/mvUsbDevApi.h" +#include "usb/device/mvUsbDevPrv.h" + +#if defined(USB_UNDERRUN_WA) + +typedef struct +{ + uint_8* buff_ptr[MAX_XDS_FOR_TR_CALLS]; + uint_32 size[MAX_XDS_FOR_TR_CALLS]; + uint_8 ep_num[MAX_XDS_FOR_TR_CALLS]; + int head; + int tail; + int tail_dma; + int num; + int num_dma; + +} USB_SEND_QUEUE; + +uint_8* usbSramBase; +int usbSramSize; +int usbSramPartSize; +USB_SEND_QUEUE usbSendQueue; + +uint_32 usbSentSize = 0; +uint_32 usbDmaSize = 0; + +#define S_FREE 0 +#define S_BUSY 1 + +uint_32 dma_index = 0; +uint_32 sent_index = 0; +uint_32 sram_parts[USB_SRAM_MAX_PARTS]; + + +void _usb_reset_send_queue(void) +{ + int i; + + usbSendQueue.num = 0; + usbSendQueue.num_dma = 0; + usbSendQueue.head = 0; + usbSendQueue.tail = 0; + usbSendQueue.tail_dma = 0; + for(i=0; i= usbSendQueue.size[tail_dma]) + { + /* Remove from the usbSendQueues */ + num_dma--; + tail_dma++; + if(tail_dma == MAX_XDS_FOR_TR_CALLS) + tail_dma = 0; + + usbSendQueue.tail_dma = tail_dma; + usbSendQueue.num_dma = num_dma; + usbDmaSize = 0; + + if(num_dma == 0) + break; + } + + buff_ptr = usbSendQueue.buff_ptr[tail_dma] + usbDmaSize; + size = MIN(usbSramPartSize, (usbSendQueue.size[tail_dma] - usbDmaSize) ); + + usbDmaSize += size; + + if(size > global_wa_threshold) + { + tmp_buff = buff_ptr; + buff_ptr = (uint_8*)((int)usbSramBase + (dma_index * usbSramPartSize)); + USB_idma_copy(buff_ptr, tmp_buff, size); + + sram_parts[dma_index] = S_BUSY; + dma_index++; + if(dma_index == global_wa_sram_parts) + dma_index = 0; + } + + + /* Get a transfer descriptor */ + USB_XD_QGET(usb_dev_ptr->XD_HEAD, usb_dev_ptr->XD_TAIL, xd_ptr); + + usb_dev_ptr->XD_ENTRIES--; + USB_dcache_flush((pointer)buff_ptr, size); + + /* Initialize the new transfer descriptor */ + xd_ptr->EP_NUM = usbSendQueue.ep_num[tail_dma]; + xd_ptr->BDIRECTION = ARC_USB_SEND; + xd_ptr->WTOTALLENGTH = size; + xd_ptr->WSOFAR = 0; + xd_ptr->WSTARTADDRESS = buff_ptr; + xd_ptr->BSTATUS = ARC_USB_STATUS_TRANSFER_ACCEPTED; + + error = _usb_dci_vusb20_add_dTD(handle, xd_ptr); + + if(error) + break; + } + + return error; +} + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : usbSendComplete +* Returned Value : None +* Comments : +* Callback for send transfer complete event. +* +*END*-----------------------------------------------------------------*/ +void usbSendComplete(void* handle, uint_8 type, boolean setup, uint_8 dir, + uint_8_ptr buffer, uint_32 length, uint_8 error) +{ + /* Check if this complete is one from the sendQueue */ + if( (usbSendQueue.ep_num[usbSendQueue.tail] == type) && + (usbSendQueue.num > 0) ) + { + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + uint_8* buff_ptr; + uint_32 size; + int num, tail; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + tail = usbSendQueue.tail; + num = usbSendQueue.num; + buff_ptr = usbSendQueue.buff_ptr[tail]; + size = usbSendQueue.size[tail]; +/* + USB_printf("usbSendComplete: num=%d, tail=%d, usbSentSize=%d, type=%d, length=%d (%d), buff=%p (%p)\n", + num, tail, usbSentSize, type, length, usbSendQueue.size[tail], + buffer, usbSendQueue.buff_ptr[tail]); +*/ + usbSentSize += length; + + /* if the buffer was on the SRAM */ + if( ((unsigned)buffer >= (unsigned)usbSramBase) && + ((unsigned)buffer < ((unsigned)usbSramBase + (usbSramPartSize * global_wa_sram_parts))) ) + { + sram_parts[sent_index] = S_FREE; + sent_index++; + if(sent_index == global_wa_sram_parts) + sent_index = 0; + } + + if(usbSentSize >= usbSendQueue.size[tail]) + { + /* Remove from the usbSendQueues */ + num--; + tail++; + if(tail == MAX_XDS_FOR_TR_CALLS) + tail = 0; + + usbSendQueue.tail = tail; + usbSendQueue.num = num; + usbSentSize = 0; + + /* Call complete callback */ + _usb_device_call_service(handle, type, setup, dir, + buff_ptr, size, error); + + if(num == 0) + return; + } + + error = _usb_prepare_to_send(handle); + if (error) + { + USB_printf("usbSendComplete, add_dTD failed\n"); + } + + } + else + { + /* Call complete callback */ + _usb_device_call_service(handle, type, setup, dir, + buffer, length, error); + } +} +#endif /* USB_UNDERRUN_WA */ + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_send_data +* Returned Value : USB_OK or error code +* Comments : +* Sends data on a specified endpoint. +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_device_send_data + ( + /* [IN] the USB_USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] buffer to send */ + uint_8_ptr buff_ptr, + + /* [IN] length of the transfer */ + uint_32 size + ) +{ /* Body */ + int lockKey; + uint_8 error = 0; + XD_STRUCT_PTR xd_ptr; + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + boolean toSend = TRUE; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_TX, + "send_data: handle=%p, ep=%d, pBuf=0x%x, size=%d, EP_QH=%p\n", + handle, ep_num, (unsigned)buff_ptr, (int)size, usb_dev_ptr->EP_QUEUE_HEAD_PTR); + + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_send_count++)); + + lockKey = USB_lock(); + + if (!usb_dev_ptr->XD_ENTRIES) + { + USB_unlock(lockKey); + USB_printf("_usb_device_send_data, transfer in progress\n"); + return ARC_USB_STATUS_TRANSFER_IN_PROGRESS; + } /* Endif */ + +#if defined(USB_UNDERRUN_WA) + { + int head; + VUSB20_EP_QUEUE_HEAD_STRUCT* ep_queue_head_ptr; + + ep_queue_head_ptr = (VUSB20_EP_QUEUE_HEAD_STRUCT_PTR)usb_dev_ptr->EP_QUEUE_HEAD_PTR + + 2*ep_num + ARC_USB_SEND; + + if( ((ep_queue_head_ptr->MAX_PKT_LENGTH >> 16) & 0x7FF) > global_wa_threshold) + { + /* Only Endpoints with maxPktSize more than 128 bytes need special processing */ + if( (size > global_wa_threshold) || + (usbSendQueue.num != 0) ) + { +/* + USB_printf("_usb_device_send_data: ep_num=%d, maxPktSize=%d, size=%d\n", + ep_num, (ep_queue_head_ptr->MAX_PKT_LENGTH >> 16) & 0x7FF, size); +*/ + /* Check if usbSendQueue is not Full */ + if(usbSendQueue.num == MAX_XDS_FOR_TR_CALLS) + { + USB_printf("ep=%d: usbSendQueue is FULL\n", ep_num); + USB_unlock(lockKey); + return USBERR_TX_FAILED; + } + + /* Add to usbSendQueu */ + head = usbSendQueue.head; + + usbSendQueue.num++; + usbSendQueue.num_dma++; + usbSendQueue.size[head] = size; + usbSendQueue.buff_ptr[head] = buff_ptr; + usbSendQueue.ep_num[head] = ep_num; + + head++; + if(head == MAX_XDS_FOR_TR_CALLS) + head = 0; + + usbSendQueue.head = head; + + /* Process first usbSendQueue element if possible */ + if(usbSendQueue.num == 1) + { + error = _usb_prepare_to_send(handle); + } + toSend = FALSE; + } + } + } +#endif /* USB_UNDERRUN_WA */ + + if(toSend == TRUE) + { + /* Get a transfer descriptor */ + USB_XD_QGET(usb_dev_ptr->XD_HEAD, usb_dev_ptr->XD_TAIL, xd_ptr); + + usb_dev_ptr->XD_ENTRIES--; + + if(buff_ptr != NULL) + USB_dcache_flush((pointer)buff_ptr, size); + + /* Initialize the new transfer descriptor */ + xd_ptr->EP_NUM = ep_num; + xd_ptr->BDIRECTION = ARC_USB_SEND; + xd_ptr->WTOTALLENGTH = size; + xd_ptr->WSOFAR = 0; + xd_ptr->WSTARTADDRESS = buff_ptr; + xd_ptr->BSTATUS = ARC_USB_STATUS_TRANSFER_ACCEPTED; + + error = _usb_dci_vusb20_add_dTD(handle, xd_ptr); + } + USB_unlock(lockKey); + + if (error) + { + USB_printf("_usb_device_send_data, transfer failed\n"); + return USBERR_TX_FAILED; + } /* Endif */ + return error; + +} /* EndBody */ + diff --git a/board/mv_feroceon/mv_hal/usb/device/mvUsbDevUtl.c b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevUtl.c new file mode 100644 index 0000000..7238d57 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/device/mvUsbDevUtl.c @@ -0,0 +1,635 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#include "usb/api/mvUsbDevApi.h" +#include "usb/device/mvUsbDevPrv.h" + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_unstall_endpoint +* Returned Value : USB_OK or error code +* Comments : +* Unstalls the endpoint in specified direction +* +*END*-----------------------------------------------------------------*/ +void _usb_device_unstall_endpoint + ( + /* [IN] the USB_USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] direction */ + uint_8 direction + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + int lockKey; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + lockKey = USB_lock(); + + _usb_dci_vusb20_unstall_endpoint(handle, ep_num, direction); + + USB_unlock(lockKey); + +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _usb_device_get_status +* Returned Value : USB_OK or error code +* Comments : +* Provides API to access the USB internal state. +* +*END*--------------------------------------------------------------------*/ +uint_8 _usb_device_get_status + ( + /* [IN] Handle to the USB device */ + _usb_device_handle handle, + + /* [IN] What to get the status of */ + uint_8 component, + + /* [OUT] The requested status */ + uint_16_ptr status + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + int lockKey; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + lockKey = USB_lock(); + + switch (component) + { + case ARC_USB_STATUS_DEVICE_STATE: + *status = usb_dev_ptr->USB_STATE; + break; + + case ARC_USB_STATUS_DEVICE: + *status = usb_dev_ptr->USB_DEVICE_STATE; + break; + + case ARC_USB_STATUS_INTERFACE: + *status = 0; + break; + + case ARC_USB_STATUS_ADDRESS: + *status = usb_dev_ptr->DEVICE_ADDRESS; + break; + + case ARC_USB_STATUS_CURRENT_CONFIG: + *status = usb_dev_ptr->USB_CURR_CONFIG; + break; + + case ARC_USB_STATUS_SOF_COUNT: + *status = usb_dev_ptr->USB_SOF_COUNT; + break; + + default: + USB_unlock(lockKey); + USB_printf("_usb_device_get_status, bad status\n"); + return USBERR_BAD_STATUS; + + } /* Endswitch */ + USB_unlock(lockKey); + + return USB_OK; +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _usb_device_set_status +* Returned Value : USB_OK or error code +* Comments : +* Provides API to set internal state +* +*END*--------------------------------------------------------------------*/ +uint_8 _usb_device_set_status + ( + /* [IN] Handle to the usb device */ + _usb_device_handle handle, + + /* [IN] What to set the status of */ + uint_8 component, + + /* [IN] What to set the status to */ + uint_16 setting + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + int lockKey; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_STATUS, + "set_status: component=0x%x, value=0x%x\n", component, setting); + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + lockKey = USB_lock(); + + switch (component) + { + case ARC_USB_STATUS_DEVICE_STATE: + usb_dev_ptr->USB_STATE = setting; + break; + + case ARC_USB_STATUS_DEVICE: + usb_dev_ptr->USB_DEVICE_STATE = setting; + break; + + case ARC_USB_STATUS_INTERFACE: + break; + + case ARC_USB_STATUS_CURRENT_CONFIG: + usb_dev_ptr->USB_CURR_CONFIG = setting; + break; + + case ARC_USB_STATUS_SOF_COUNT: + usb_dev_ptr->USB_SOF_COUNT = setting; + break; + + case ARC_USB_FORCE_FULL_SPEED: + _usb_dci_vusb20_set_speed_full((pointer)usb_dev_ptr, setting); + break; + + case ARC_USB_PHY_LOW_POWER_SUSPEND: + _usb_dci_vusb20_suspend_phy((pointer)usb_dev_ptr, setting); + break; + + case ARC_USB_STATUS_ADDRESS: + usb_dev_ptr->DEVICE_ADDRESS = setting; + + _usb_dci_vusb20_set_address((pointer)usb_dev_ptr, setting); + break; + + case ARC_USB_STATUS_TEST_MODE: + _usb_dci_vusb20_set_test_mode(handle, setting); + break; + + default: + USB_unlock(lockKey); + USB_printf("_usb_device_set_status, bad status\n"); + return USBERR_BAD_STATUS; + + } /* Endswitch */ + + USB_unlock(lockKey); + + return USB_OK; +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_stall_endpoint +* Returned Value : USB_OK or error code +* Comments : +* Stalls the endpoint. +* +*END*-----------------------------------------------------------------*/ +void _usb_device_stall_endpoint + ( + /* [IN] the USB_USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] direction */ + uint_8 direction + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + int lockKey; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + lockKey = USB_lock(); + + _usb_dci_vusb20_stall_endpoint(handle, ep_num, direction); + + USB_unlock(lockKey); + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_is_endpoint_stalled +* Returned Value : USB_OK or error code +* Comments : +* Stalls the endpoint. +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_device_is_endpoint_stalled + ( + /* [IN] the USB_USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] direction */ + uint_8 direction + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + uint_8 val; + int lockKey; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + lockKey = USB_lock(); + + val = _usb_dci_vusb20_is_endpoint_stalled(handle, ep_num, direction); + + USB_unlock(lockKey); + + return val; + +} /* EndBody */ + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_device_process_resume +* Returned Value : USB_OK or error code +* Comments : +* Process Resume event +* +*END*-----------------------------------------------------------------*/ +void _usb_device_assert_resume + ( + /* [IN] the USB_USB_dev_initialize state structure */ + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + _usb_dci_vusb20_assert_resume(handle); + +} /* EndBody */ + + +/***************************/ +/* ARC USB Debug functions */ +/***************************/ +void _usb_status(void* usbHandle) +{ + USB_DEV_STATE_STRUCT* pUsbDev = (USB_DEV_STATE_STRUCT*)usbHandle; + + if(pUsbDev == NULL) + { + USB_printf("USB Device core is not initialized\n"); + return; + } + + USB_printf("\n\tUSB Status\n\n"); + + USB_printf("DEV_NUM=%d, DEV_ADDR=%d, CAP_REGS=0x%x, DEV_REGS=0x%x, MAX_EP=%d\n", + pUsbDev->DEV_NUM, + pUsbDev->DEVICE_ADDRESS, + (unsigned)pUsbDev->CAP_REGS_PTR, + (unsigned)pUsbDev->DEV_PTR, + pUsbDev->MAX_ENDPOINTS); + + USB_printf("BUS_RESET=%s, STATE=0x%02x, DEV_STATE=0x%02x, SPEED=%d, ERRORS=%d, ERROR_STATE=0x%04x\n", + pUsbDev->BUS_RESETTING ? "Yes" : "No", + pUsbDev->USB_STATE, + pUsbDev->USB_DEVICE_STATE, + pUsbDev->SPEED, + pUsbDev->ERRORS, + pUsbDev->ERROR_STATE); + + USB_printf("EP_QUEUE_HEAD: SIZE=%d, BASE=%p (0x%08x), ALIGNED=%p, SERVICE_HEAD=%p\n", + pUsbDev->EP_QUEUE_HEAD_SIZE, + pUsbDev->EP_QUEUE_HEAD_BASE, + pUsbDev->EP_QUEUE_HEAD_PHYS, + pUsbDev->EP_QUEUE_HEAD_PTR, + pUsbDev->SERVICE_HEAD_PTR); + + USB_printf("XD: BASE=%p, HEAD=%p, TAIL=%p, ENTRIES=%d, SCRATCH=%p, TEMP=%p\n", + pUsbDev->XD_BASE, + pUsbDev->XD_HEAD, + pUsbDev->XD_TAIL, + pUsbDev->XD_ENTRIES, + pUsbDev->XD_SCRATCH_STRUCT_BASE, + pUsbDev->TEMP_XD_PTR); + + USB_printf("DTD: SIZE=%d, BASE=%p (0x%08x), ALIGNED=%p, HEAD=0x%08x, TAIL=0x%08x, ENTRIES=%d, SCRATCH=%p\n", + pUsbDev->DTD_SIZE, + pUsbDev->DTD_BASE_PTR, + pUsbDev->DTD_BASE_PHYS, + pUsbDev->DTD_ALIGNED_BASE_PTR, + pUsbDev->DTD_HEAD, + pUsbDev->DTD_TAIL, + pUsbDev->DTD_ENTRIES, + pUsbDev->SCRATCH_STRUCT_BASE); +} + +void _usb_stats(void* usbHandle) +{ + USB_DEV_STATE_STRUCT* pUsbDev = (USB_DEV_STATE_STRUCT*)usbHandle; + USB_STATS* pUsbStats = &pUsbDev->STATS; + int i; + + USB_printf("\n\tUSB Statistics\n\n"); + + USB_printf("isr=%u, empty_isr=%u, reset=%u, setup=%u, read_setup=%u\n", + pUsbStats->usb_isr_count, pUsbStats->usb_empty_isr_count, + pUsbStats->usb_reset_count, pUsbStats->usb_setup_count, + pUsbStats->usb_read_setup_count); + + USB_printf("recv=%u, send=%u, add=%u (%u), cancel=%u\n", + pUsbStats->usb_recv_count, pUsbStats->usb_send_count, + pUsbStats->usb_add_count, pUsbStats->usb_add_not_empty_count, + pUsbStats->usb_cancel_count); + + USB_printf("free_XD=%u, free_dTD=%u\n", + pUsbStats->free_XD_count, pUsbStats->free_dTD_count); + + USB_printf("complete_isr=%u, complete=%u, empty_complete=%u, max_complete=%u\n", + pUsbStats->usb_complete_isr_count, pUsbStats->usb_complete_count, + pUsbStats->usb_empty_complete_count, pUsbStats->usb_complete_max_count); + + USB_printf("port_change=%u, suspend=%u\n", + pUsbStats->usb_port_change_count, pUsbStats->usb_suspend_count); + for(i=0; i<(pUsbDev->MAX_ENDPOINTS); i++) + { + if( (pUsbStats->usb_complete_ep_count[i*2] == 0) && + (pUsbStats->usb_complete_ep_count[i*2+1] == 0) ) + continue; + + USB_printf("EP #%d: RECV (OUT) = %3u, \tSEND (IN) = %u\n", i, + pUsbStats->usb_complete_ep_count[i*2], + pUsbStats->usb_complete_ep_count[i*2+1]); + } + USB_printf("\n"); +} + +void _usb_clear_stats(void* usbHandle) +{ + USB_DEV_STATE_STRUCT* pUsbDev = (USB_DEV_STATE_STRUCT*)usbHandle; + + USB_memzero(&pUsbDev->STATS, sizeof(pUsbDev->STATS)); +} + +void _usb_regs(void* usbHandle) +{ + USB_DEV_STATE_STRUCT* pUsbDev = (USB_DEV_STATE_STRUCT*)usbHandle; + VUSB20_REG_STRUCT* cap_regs, *dev_regs; + int dev_num; + + if(pUsbDev == NULL) + { + USB_printf("USB Device core is not initialized\n"); + return; + } + USB_printf("\n\tUSB Capability Registers\n\n"); + + cap_regs = pUsbDev->CAP_REGS_PTR; + USB_printf("CAPLENGTH_HCIVER (0x%08x) = 0x%08x\n", + (unsigned)&cap_regs->REGISTERS.CAPABILITY_REGISTERS.CAPLENGTH_HCIVER, + (unsigned)USB_32BIT_LE(cap_regs->REGISTERS.CAPABILITY_REGISTERS.CAPLENGTH_HCIVER)); + + USB_printf("DCI_VERSION (0x%08x) = 0x%08x\n", + (unsigned)&cap_regs->REGISTERS.CAPABILITY_REGISTERS.DCI_VERSION, + (unsigned)USB_32BIT_LE(cap_regs->REGISTERS.CAPABILITY_REGISTERS.DCI_VERSION)); + + USB_printf("DCC_PARAMS (0x%08x) = 0x%08x\n", + (unsigned)&cap_regs->REGISTERS.CAPABILITY_REGISTERS.DCC_PARAMS, + (unsigned)USB_32BIT_LE(cap_regs->REGISTERS.CAPABILITY_REGISTERS.DCC_PARAMS)); + + dev_regs = pUsbDev->DEV_PTR; + dev_num = pUsbDev->DEV_NUM; + USB_printf("\n\tUSB Device Operational Registers\n\n"); + + USB_printf("USB_CMD (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD)); + + USB_printf("USB_STS (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_STS, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_STS)); + + USB_printf("USB_INTR (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_INTR, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_INTR)); + + USB_printf("USB_FRINDEX (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_FRINDEX, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_FRINDEX)); + + /* Skip CTRLDSSEGMENT register */ + USB_printf("DEVICE_ADDR (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.DEVICE_ADDR, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.DEVICE_ADDR)); + + USB_printf("EP_LIST_ADDR (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.EP_LIST_ADDR, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.EP_LIST_ADDR)); + + /* Skip CONFIG_FLAG register */ + + /* Skip PORTSCX[0..15] registers*/ + USB_printf("PORTSCX[0] (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0], + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0])); + + /* Skip OTGSC register */ + + USB_printf("USB_MODE (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_MODE, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_MODE)); + + USB_printf("ENDPT_SETUP_STAT (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPT_SETUP_STAT, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPT_SETUP_STAT)); + + USB_printf("ENDPTPRIME (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME)); + + USB_printf("ENDPTFLUSH (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTFLUSH, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTFLUSH)); + + USB_printf("ENDPTSTATUS (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS)); + + USB_printf("ENDPTCOMPLETE (0x%08x) = 0x%08x\n", + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCOMPLETE, + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCOMPLETE)); +} + + +void _usb_ep_status(void* usbHandle, int ep_num, int direction) +{ + USB_DEV_STATE_STRUCT* pUsbDev = (USB_DEV_STATE_STRUCT*)usbHandle; + int i, ep_idx; + VUSB20_EP_QUEUE_HEAD_STRUCT_PTR ep_queue_head_ptr; + VUSB20_EP_TR_STRUCT_PTR dTD_ptr, head_dTD_ptr, tail_dTD_ptr, next_dTD_ptr; + XD_STRUCT_PTR xd_ptr, next_xd_ptr; + VUSB20_REG_STRUCT_PTR dev_regs; + + if(pUsbDev == NULL) + { + USB_printf("USB Device core is not initialized\n"); + return; + } + + USB_printf("\n\tUSB Endpoint #%d - %s status\n\n", ep_num, + (direction == ARC_USB_SEND) ? "SEND (IN)" : "RECV (OUT)" ); + + ep_idx = ep_num*2 + direction; + dev_regs = pUsbDev->DEV_PTR; + + USB_printf("ENDPTCTRLX[%d] (0x%08x) = 0x%08x\n", ep_num, + (unsigned)&dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num], + (unsigned)USB_32BIT_LE(dev_regs->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num])); + + ep_queue_head_ptr = (VUSB20_EP_QUEUE_HEAD_STRUCT_PTR)pUsbDev->EP_QUEUE_HEAD_PTR + ep_idx; + + head_dTD_ptr = pUsbDev->EP_DTD_HEADS[ep_idx]; + tail_dTD_ptr = pUsbDev->EP_DTD_TAILS[ep_idx]; + + USB_printf("EP_QH=0x%08x: MAX_PKT=0x%x, SIZE_IOC_INT_STS=0x%x, CURR_DTD=0x%x, NEXT_DTD=0x%x\n", + (unsigned)ep_queue_head_ptr, (unsigned)USB_32BIT_LE(ep_queue_head_ptr->MAX_PKT_LENGTH), + (unsigned)USB_32BIT_LE(ep_queue_head_ptr->SIZE_IOC_INT_STS), + (unsigned)USB_32BIT_LE(ep_queue_head_ptr->CURR_DTD_PTR), + (unsigned)USB_32BIT_LE(ep_queue_head_ptr->NEXT_DTD_PTR)); + + USB_printf("\tBUF_0=0x%08x, BUF_1=0x%08x, BUF_2=0x%08x, BUF_3=0x%08x, BUF_4=0x%08x\n", + (unsigned)USB_32BIT_LE(ep_queue_head_ptr->BUFF_PTR0), + (unsigned)USB_32BIT_LE(ep_queue_head_ptr->BUFF_PTR1), + (unsigned)USB_32BIT_LE(ep_queue_head_ptr->BUFF_PTR2), + (unsigned)USB_32BIT_LE(ep_queue_head_ptr->BUFF_PTR3), + (unsigned)USB_32BIT_LE(ep_queue_head_ptr->BUFF_PTR4)); + + USB_printf("\tSETUP_BUFFER (%p): ", ep_queue_head_ptr->SETUP_BUFFER); + for(i=0; iSETUP_BUFFER); i++) + USB_printf("%02x", ep_queue_head_ptr->SETUP_BUFFER[i] & 0xFF); + USB_printf("\n"); + + USB_printf("\ndTD_HEAD=0x%08x, dTD_TAIL=0x%08x\n", + (unsigned)head_dTD_ptr, (unsigned)tail_dTD_ptr); + + dTD_ptr = head_dTD_ptr; + i = 0; + while(dTD_ptr != NULL) + { + USB_printf("%d. dTD=0x%08x (0x%08x), SIZE_IOC_STS=0x%08x, BUF_0=0x%08x, NEXT=0x%08x\n", + i, (unsigned)dTD_ptr, USB_DTD_VIRT_TO_PHYS(pUsbDev, dTD_ptr), + (unsigned)USB_32BIT_LE(dTD_ptr->SIZE_IOC_STS), + (unsigned)USB_32BIT_LE(dTD_ptr->BUFF_PTR0), + (unsigned)USB_32BIT_LE(dTD_ptr->NEXT_TR_ELEM_PTR)); + + xd_ptr = dTD_ptr->SCRATCH_PTR->XD_FOR_THIS_DTD; + + next_dTD_ptr = (VUSB20_EP_TR_STRUCT_PTR)USB_DTD_PHYS_TO_VIRT(pUsbDev, + (uint_32)(USB_32BIT_LE(dTD_ptr->NEXT_TR_ELEM_PTR) & VUSBHS_TD_ADDR_MASK)); + if(next_dTD_ptr != NULL) + next_xd_ptr = next_dTD_ptr->SCRATCH_PTR->XD_FOR_THIS_DTD; + else + next_xd_ptr = NULL; + + if(next_xd_ptr != xd_ptr) + { + USB_printf("\tXD=0x%08x, ADDR=0x%08x, SIZE=%u, STATUS=0x%02x\n", + (unsigned)xd_ptr, (unsigned)xd_ptr->WSTARTADDRESS, + (unsigned)xd_ptr->WTOTALLENGTH, xd_ptr->BSTATUS); + } + i++; + dTD_ptr = next_dTD_ptr; + } +} + + +/* DEBUG */ +uint_32 usbDebugFlags = ARC_DEBUG_FLAG_STATS + | ARC_DEBUG_FLAG_INIT + | ARC_DEBUG_FLAG_ERROR + | ARC_DEBUG_FLAG_STALL + | ARC_DEBUG_FLAG_RESET; + /*| ARC_DEBUG_FLAG_TRANSFER;*/ + +void _usb_debug_set_flags(uint_32 flags) +{ + usbDebugFlags = (flags); +} + +uint_32 _usb_debug_get_flags(void) +{ + return usbDebugFlags; +} + +#if defined(MV_USB_TRACE_LOG) + +uint_16 DEBUG_TRACE_ARRAY_COUNTER = 0; +char DEBUG_TRACE_ARRAY[TRACE_ARRAY_SIZE][MAX_STRING_SIZE]; + +void _usb_debug_init_trace_log(void) +{ + USB_memzero(DEBUG_TRACE_ARRAY, TRACE_ARRAY_SIZE*MAX_STRING_SIZE); + DEBUG_TRACE_ARRAY_COUNTER =0; +} + +void _usb_debug_print_trace_log(void) +{ + int i; + + USB_printf("USB Trace log: start=0x%x, end=0x%x, idx=%d, flags=0x%x\n\n", + &DEBUG_TRACE_ARRAY[0][0], &DEBUG_TRACE_ARRAY[TRACE_ARRAY_SIZE-1][0], + DEBUG_TRACE_ARRAY_COUNTER, usbDebugFlags); + + for(i=DEBUG_TRACE_ARRAY_COUNTER; iDEV_PTR; + + bit_pos = (1 << (16 * direction + ep_num)); + temp = (2*ep_num + direction); + + ep_queue_head_ptr = (VUSB20_EP_QUEUE_HEAD_STRUCT_PTR)usb_dev_ptr->EP_QUEUE_HEAD_PTR + temp; + + /* Unlink the dTD */ + dTD_ptr = usb_dev_ptr->EP_DTD_HEADS[temp]; + + if (dTD_ptr) + { + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_cancel_count++)); + + check_dTD_ptr = (VUSB20_EP_TR_STRUCT_PTR)USB_DTD_PHYS_TO_VIRT(usb_dev_ptr, + ((uint_32)USB_32BIT_LE(dTD_ptr->NEXT_TR_ELEM_PTR) & VUSBHS_TD_ADDR_MASK)); + + if (USB_32BIT_LE(dTD_ptr->SIZE_IOC_STS) & VUSBHS_TD_STATUS_ACTIVE) + { + /* Flushing will halt the pipe */ + /* Write 1 to the Flush register */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTFLUSH = USB_32BIT_LE(bit_pos); + + /* Wait until flushing completed */ + timeout = 0x1000000; + while (USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTFLUSH) & bit_pos) + { + /* ENDPTFLUSH bit should be cleared to indicate this operation is complete */ + timeout--; + if(timeout == 0) + { + USB_printf("USB Cancel: - TIMEOUT for ENDPTFLUSH=0x%x, bit_pos=0x%x \n", + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTFLUSH), + (unsigned)bit_pos); + break; + } + } /* EndWhile */ + status_timeout = 0x100000; + while (USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS) & bit_pos) + { + status_timeout--; + if(status_timeout == 0) + { + USB_printf("USB Cancel: - TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n", + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS), + (unsigned)bit_pos); + break; + } + + /* Write 1 to the Flush register */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTFLUSH = USB_32BIT_LE(bit_pos); + + /* Wait until flushing completed */ + timeout = 0x1000000; + while (USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTFLUSH) & bit_pos) + { + /* ENDPTFLUSH bit should be cleared to indicate this operation is complete */ + timeout--; + if(timeout == 0) + { + USB_printf("USB Cancel: - TIMEOUT for ENDPTFLUSH=0x%x, ENDPTSTATUS=0x%x, bit_pos=0x%x\n", + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTFLUSH), + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS), + (unsigned)bit_pos); + break; + } + } /* EndWhile */ + } /* EndWhile */ + } /* Endif */ + + /* Retire the current dTD */ + dTD_ptr->SIZE_IOC_STS = 0; + dTD_ptr->NEXT_TR_ELEM_PTR = USB_32BIT_LE(VUSBHS_TD_NEXT_TERMINATE); + + /* The transfer descriptor for this dTD */ + xd_ptr = (XD_STRUCT_PTR)dTD_ptr->SCRATCH_PTR->XD_FOR_THIS_DTD; + dTD_ptr->SCRATCH_PTR->PRIVATE = (pointer)usb_dev_ptr; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_TRANSFER, + "cncl_%d: fri=0x%x, ep=%d%s, buf=%p, size=%d, xd=%p, dTD=%p %p, bit=0x%x\n", + usb_dev_ptr->STATS.usb_cancel_count & 0xFFFF, + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_FRINDEX), + ep_num, direction ? "in" : "out", + xd_ptr->WSTARTADDRESS, xd_ptr->WTOTALLENGTH, xd_ptr, + dTD_ptr, check_dTD_ptr, bit_pos); + + /* Free the dTD */ + _usb_dci_vusb20_free_dTD((pointer)dTD_ptr); + + /* Update the dTD head and tail for specific endpoint/direction */ + if (!check_dTD_ptr) + { + usb_dev_ptr->EP_DTD_HEADS[temp] = NULL; + usb_dev_ptr->EP_DTD_TAILS[temp] = NULL; + if (xd_ptr) + { + xd_ptr->SCRATCH_PTR->PRIVATE = (pointer)usb_dev_ptr; + /* Free the transfer descriptor */ + _usb_device_free_XD((pointer)xd_ptr); + } /* Endif */ + /* No other transfers on the queue */ + ep_queue_head_ptr->NEXT_DTD_PTR = USB_32BIT_LE(VUSB_EP_QUEUE_HEAD_NEXT_TERMINATE); + ep_queue_head_ptr->SIZE_IOC_INT_STS = 0; + } + else + { + usb_dev_ptr->EP_DTD_HEADS[temp] = check_dTD_ptr; + + if (xd_ptr) + { + if ((uint_32)check_dTD_ptr->SCRATCH_PTR->XD_FOR_THIS_DTD != (uint_32)xd_ptr) + { + xd_ptr->SCRATCH_PTR->PRIVATE = (pointer)usb_dev_ptr; + /* Free the transfer descriptor */ + _usb_device_free_XD((pointer)xd_ptr); + } /* Endif */ + } /* Endif */ + + if (USB_32BIT_LE(check_dTD_ptr->SIZE_IOC_STS) & VUSBHS_TD_STATUS_ACTIVE) + { + /* Start CR 1015 */ + /* Prime the Endpoint */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME = USB_32BIT_LE(bit_pos); + + if (!(USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS) & bit_pos)) + { + timeout = 0x100000; + while (USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME) & bit_pos) + { + /* Wait for the ENDPTPRIME to go to zero */ + timeout--; + if(timeout == 0) + { + USB_printf("USB Cancel: - TIMEOUT for ENDPTPRIME=0x%x, bit_pos=0x%x\n", + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME), + (unsigned)bit_pos); + break; + } + } /* EndWhile */ + + if (USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS) & bit_pos) + { + /* The endpoint was not not primed so no other transfers on + ** the queue + */ + goto done; + } /* Endif */ + } + else + { + goto done; + } /* Endif */ + + /* No other transfers on the queue */ + ep_queue_head_ptr->NEXT_DTD_PTR = (uint_32)USB_32BIT_LE((uint_32)check_dTD_ptr); + ep_queue_head_ptr->SIZE_IOC_INT_STS = 0; + + /* Prime the Endpoint */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME = USB_32BIT_LE(bit_pos); + } /* Endif */ + } /* Endif */ + } /* Endif */ + +done: + + /* End CR 1015 */ + return USB_OK; +} /* EndBody */ + +/* EOF */ diff --git a/board/mv_feroceon/mv_hal/usb/device/mvUsbHsDevMain.c b/board/mv_feroceon/mv_hal/usb/device/mvUsbHsDevMain.c new file mode 100644 index 0000000..b030ac7 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/device/mvUsbHsDevMain.c @@ -0,0 +1,1868 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#include "usb/api/mvUsbDevApi.h" +#include "usb/device/mvUsbDevPrv.h" + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_init +* Returned Value : USB_OK or error code +* Comments : +* Initializes the USB device controller. +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_dci_vusb20_init + ( + /* [IN] the USB device controller to initialize */ + uint_8 devnum, + + /* [OUT] the USB_dev_initialize state structure */ + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + uint_32 temp; + uint_8* pBuf; + unsigned long phyAddr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + usb_dev_ptr->CAP_REGS_PTR = + (VUSB20_REG_STRUCT_PTR)USB_get_cap_reg_addr(devnum); + + /* Get the base address of the VUSB_HS registers */ + usb_dev_ptr->DEV_PTR = + (VUSB20_REG_STRUCT_PTR)(((uint_32)usb_dev_ptr->CAP_REGS_PTR) + + (USB_32BIT_LE(usb_dev_ptr->CAP_REGS_PTR->REGISTERS.CAPABILITY_REGISTERS.CAPLENGTH_HCIVER) & + EHCI_CAP_LEN_MASK)); + + /* Get the maximum number of endpoints supported by this USB controller */ + usb_dev_ptr->MAX_ENDPOINTS = + (USB_32BIT_LE(usb_dev_ptr->CAP_REGS_PTR->REGISTERS.CAPABILITY_REGISTERS.DCC_PARAMS) & + VUSB20_DCC_MAX_ENDPTS_SUPPORTED); + + USB_printf("USB init: CAP_REGS=0x%x, DEV_REGS=0x%x, MAX_EP=%d\n", + (unsigned)usb_dev_ptr->CAP_REGS_PTR, (unsigned)usb_dev_ptr->DEV_PTR, + usb_dev_ptr->MAX_ENDPOINTS); + + temp = (usb_dev_ptr->MAX_ENDPOINTS * 2); + + pBuf = (uint_8*)USB_uncached_memalloc(temp*sizeof(VUSB20_EP_QUEUE_HEAD_STRUCT), + 2048, &phyAddr); + if (pBuf == NULL) + { + USB_printf("_usb_dci_vusb20_init, malloc of %d bytes in Uncached area failed\n", + temp*sizeof(VUSB20_EP_QUEUE_HEAD_STRUCT)); + return USBERR_ALLOC; + } + + /**************************************************************** + Assign QH base + ****************************************************************/ + usb_dev_ptr->EP_QUEUE_HEAD_BASE = pBuf; + usb_dev_ptr->EP_QUEUE_HEAD_PHYS = (uint_32)phyAddr; + + /* Align the endpoint queue head to 2K boundary */ + usb_dev_ptr->EP_QUEUE_HEAD_PTR = (VUSB20_EP_QUEUE_HEAD_STRUCT_PTR) + USB_MEM2048_ALIGN((uint_32)usb_dev_ptr->EP_QUEUE_HEAD_BASE); + + usb_dev_ptr->EP_QUEUE_HEAD_SIZE = temp*sizeof(VUSB20_EP_QUEUE_HEAD_STRUCT) + + ((uint_32)usb_dev_ptr->EP_QUEUE_HEAD_PTR - + (uint_32)usb_dev_ptr->EP_QUEUE_HEAD_BASE); + + /**************************************************************** + Zero out the memory allocated + ****************************************************************/ + USB_memzero( (void*)usb_dev_ptr->EP_QUEUE_HEAD_PTR, + temp*sizeof(VUSB20_EP_QUEUE_HEAD_STRUCT)); + + USB_printf("USB EP_QH: Base=%p (0x%x), Aligned(%d)=%p, Size=%d\n", + usb_dev_ptr->EP_QUEUE_HEAD_BASE, usb_dev_ptr->EP_QUEUE_HEAD_PHYS, + 2048, usb_dev_ptr->EP_QUEUE_HEAD_PTR, usb_dev_ptr->EP_QUEUE_HEAD_SIZE); + + /**************************************************************** + Assign DTD base + ****************************************************************/ + pBuf = (uint_8*)USB_uncached_memalloc(MAX_EP_TR_DESCRS*sizeof(VUSB20_EP_TR_STRUCT), + 32, &phyAddr); + if (pBuf == NULL) + { + USB_printf("_usb_dci_vusb20_init, malloc of %d bytes in Uncached area failed\n", + MAX_EP_TR_DESCRS*sizeof(VUSB20_EP_TR_STRUCT)); + return USBERR_ALLOC; + } + + usb_dev_ptr->DTD_BASE_PTR = pBuf; + usb_dev_ptr->DTD_BASE_PHYS = (uint_32)phyAddr; + + /* Align the dTD base to 32 byte boundary */ + usb_dev_ptr->DTD_ALIGNED_BASE_PTR = (VUSB20_EP_TR_STRUCT_PTR) + USB_MEM32_ALIGN((uint_32)usb_dev_ptr->DTD_BASE_PTR); + + usb_dev_ptr->DTD_SIZE = MAX_EP_TR_DESCRS*sizeof(VUSB20_EP_TR_STRUCT) + + ((uint_32)usb_dev_ptr->EP_QUEUE_HEAD_PTR - + (uint_32)usb_dev_ptr->EP_QUEUE_HEAD_BASE); + + /**************************************************************** + Zero out the memory allocated + ****************************************************************/ + USB_memzero((void*)usb_dev_ptr->DTD_ALIGNED_BASE_PTR, + MAX_EP_TR_DESCRS*sizeof(VUSB20_EP_TR_STRUCT)); + + /**************************************************************** + Assign SCRATCH Structure base + ****************************************************************/ + /* Allocate memory for internal scratch structure */ + pBuf = USB_memalloc(MAX_EP_TR_DESCRS*sizeof(SCRATCH_STRUCT)); + if (pBuf == NULL) + { + USB_printf("_usb_dci_vusb20_init, malloc of %d bytes failed\n", + MAX_EP_TR_DESCRS*sizeof(SCRATCH_STRUCT)); + return USBERR_ALLOC; + } + usb_dev_ptr->SCRATCH_STRUCT_BASE = (SCRATCH_STRUCT_PTR)pBuf; + USB_memzero(usb_dev_ptr->SCRATCH_STRUCT_BASE, + MAX_EP_TR_DESCRS*sizeof(SCRATCH_STRUCT)); + + USB_printf("USB dTD(%d): Base=%p (0x%x), Aligned(%d)=%p, Size=%d, Scratch=%p\n", + MAX_EP_TR_DESCRS, usb_dev_ptr->DTD_BASE_PTR, usb_dev_ptr->DTD_BASE_PHYS, + 32, usb_dev_ptr->DTD_ALIGNED_BASE_PTR, usb_dev_ptr->DTD_SIZE, + usb_dev_ptr->SCRATCH_STRUCT_BASE); + +#ifdef USB_UNDERRUN_WA + usbSramBase = (uint_8*)USB_get_sram_addr(&usbSramSize); + if (usbSramBase == NULL) + { + USB_printf("_usb_dci_vusb20_init, SRAM is not available\n"); + return USBERR_ALLOC; + } + USB_memzero(usbSramBase, usbSramSize); + USB_printf("USB WA_Queue: base=%p, size=%d, parts=%d\n", + usbSramBase, usbSramSize, global_wa_sram_parts); +#endif /* USB_UNDERRUN_WA */ + + usb_dev_ptr->USB_STATE = ARC_USB_STATE_UNKNOWN; + + /* Initialize the VUSB_HS controller */ + _usb_dci_vusb20_chip_initialize((pointer)usb_dev_ptr); + + return USB_OK; +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_chip_initialize +* Returned Value : USB_OK or error code +* Comments : +* Initializes the USB device controller. +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_chip_initialize + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + VUSB20_EP_QUEUE_HEAD_STRUCT_PTR ep_queue_head_ptr; + VUSB20_EP_TR_STRUCT_PTR dTD_ptr; + uint_32 i, port_control; + SCRATCH_STRUCT_PTR temp_scratch_ptr; + volatile unsigned long delay; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_INIT, "chip_initialize\n"); + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Stop the controller */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD &= ~(USB_32BIT_LE(EHCI_CMD_RUN_STOP)); + + /* Reset the controller to get default values */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD = USB_32BIT_LE(EHCI_CMD_CTRL_RESET); + + USB_printf("USB Init: Wait for RESET completed\n"); + + delay = 0x100000; + while (dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD & + (USB_32BIT_LE(EHCI_CMD_CTRL_RESET))) + { + /* Wait for the controller reset to complete */ + delay--; + if(delay == 0) + break; + } /* EndWhile */ + + if(delay == 0) + { + USB_printf("USB Init: Wait for RESET completed TIMEOUT\n"); + } + else + { + USB_printf("USB Init: RESET completed\n"); + } + /* Call BSP callback to complete reset process */ + USB_reset_complete(usb_dev_ptr->DEV_NUM); + + /* Initialize the internal dTD head and tail to NULL */ + usb_dev_ptr->DTD_HEAD = NULL; + usb_dev_ptr->DTD_TAIL = NULL; + usb_dev_ptr->DTD_ENTRIES = 0; + usb_dev_ptr->ERROR_STATE = 0; + + /* Make sure the 16 MSBs of this register are 0s */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPT_SETUP_STAT = USB_32BIT_LE(0); + + ep_queue_head_ptr = usb_dev_ptr->EP_QUEUE_HEAD_PTR; + + /* Initialize all device queue heads */ + for (i=0; i<(usb_dev_ptr->MAX_ENDPOINTS*2); i++) + { + /* Interrupt on Setup packet */ + (ep_queue_head_ptr + i)->MAX_PKT_LENGTH = (USB_32BIT_LE( + ((uint_32)USB_MAX_CTRL_PAYLOAD << VUSB_EP_QUEUE_HEAD_MAX_PKT_LEN_POS) | + VUSB_EP_QUEUE_HEAD_IOS)); + + (ep_queue_head_ptr + i)->NEXT_DTD_PTR = (USB_32BIT_LE(VUSB_EP_QUEUE_HEAD_NEXT_TERMINATE)); + } /* Endfor */ + + /* Configure the Endpoint List Address */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.EP_LIST_ADDR = + USB_32BIT_LE(USB_EP_QH_VIRT_TO_PHYS(usb_dev_ptr, ep_queue_head_ptr)); + + port_control = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]); + if (usb_dev_ptr->CAP_REGS_PTR->REGISTERS.CAPABILITY_REGISTERS.HCS_PARAMS & + USB_32BIT_LE(VUSB20_HCS_PARAMS_PORT_POWER_CONTROL_FLAG)) + { + port_control &= (~EHCI_PORTSCX_W1C_BITS | ~EHCI_PORTSCX_PORT_POWER); + } /* Endif */ + + if(usb_dev_ptr->FORCE_FS == TRUE) + { + port_control |= EHCI_PORTSCX_FORCE_FULL_SPEED_CONNECT; + } + else + { + port_control &= (~EHCI_PORTSCX_FORCE_FULL_SPEED_CONNECT); + } + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0] = USB_32BIT_LE(port_control); + + dTD_ptr = usb_dev_ptr->DTD_ALIGNED_BASE_PTR; + + temp_scratch_ptr = usb_dev_ptr->SCRATCH_STRUCT_BASE; + + /* Enqueue all the dTDs */ + for (i=0; iSCRATCH_PTR = temp_scratch_ptr; + dTD_ptr->SCRATCH_PTR->FREE = _usb_dci_vusb20_free_dTD; + /* Set the dTD to be invalid */ + dTD_ptr->NEXT_TR_ELEM_PTR = USB_32BIT_LE(VUSBHS_TD_NEXT_TERMINATE); + /* Set the Reserved fields to 0 */ + dTD_ptr->SIZE_IOC_STS &= ~(USB_32BIT_LE(VUSBHS_TD_RESERVED_FIELDS)); + dTD_ptr->SCRATCH_PTR->PRIVATE = (pointer)usb_dev_ptr; + _usb_dci_vusb20_free_dTD((pointer)dTD_ptr); + dTD_ptr++; + temp_scratch_ptr++; + } /* Endfor */ +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_free_dTD +* Returned Value : void +* Comments : +* Enqueues a dTD onto the free DTD ring. +* +*END*-----------------------------------------------------------------*/ + +void _usb_dci_vusb20_free_dTD + ( + /* [IN] the dTD to enqueue */ + pointer dTD_ptr + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + int lockKey; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)(((VUSB20_EP_TR_STRUCT_PTR)dTD_ptr)->SCRATCH_PTR->PRIVATE); + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_TRACE, "free_dTD: dTD_ptr=0x%x\n", (unsigned)dTD_ptr); + + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.free_dTD_count++)); + + + /* + ** This function can be called from any context, and it needs mutual + ** exclusion with itself. + */ + lockKey = USB_lock(); + + /* + ** Add the dTD to the free dTD queue (linked via PRIVATE) and + ** increment the tail to the next descriptor + */ + EHCI_DTD_QADD(usb_dev_ptr->DTD_HEAD, usb_dev_ptr->DTD_TAIL, (VUSB20_EP_TR_STRUCT_PTR)dTD_ptr); + usb_dev_ptr->DTD_ENTRIES++; + + USB_unlock(lockKey); + +} /* Endbody */ + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_add_dTD +* Returned Value : USB_OK or error code +* Comments : +* Adds a device transfer desriptor(s) to the queue. +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_dci_vusb20_add_dTD + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] The transfer descriptor address */ + XD_STRUCT_PTR xd_ptr + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + VUSB20_EP_TR_STRUCT_PTR dTD_ptr, temp_dTD_ptr, first_dTD_ptr = NULL; + VUSB20_EP_QUEUE_HEAD_STRUCT_PTR ep_queue_head_ptr; + uint_32 curr_pkt_len, remaining_len; + uint_32 curr_offset, temp, bit_pos; + volatile unsigned long timeout; + + /********************************************************************* + For a optimal implementation, we need to detect the fact that + we are adding DTD to an empty list. If list is empty, we can + actually skip several programming steps esp. those for ensuring + that there is no race condition.The following boolean will be useful + in skipping some code here. + *********************************************************************/ + boolean list_empty = FALSE; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + remaining_len = xd_ptr->WTOTALLENGTH; + + curr_offset = 0; + temp = (2*xd_ptr->EP_NUM + xd_ptr->BDIRECTION); + bit_pos = (1 << (16 * xd_ptr->BDIRECTION + xd_ptr->EP_NUM)); + + ep_queue_head_ptr = (VUSB20_EP_QUEUE_HEAD_STRUCT_PTR)usb_dev_ptr->EP_QUEUE_HEAD_PTR + temp; + + /********************************************************************* + This loops iterates through the length of the transfer and divides + the data in to DTDs each handling the a max of 0x4000 bytes of data. + The first DTD in the list is stored in a pointer called first_dTD_ptr. + This pointer is later linked in to QH for processing by the hardware. + *********************************************************************/ + + do + { + /* Check if we need to split the transfer into multiple dTDs */ + if (remaining_len > VUSB_EP_MAX_LENGTH_TRANSFER) + { + curr_pkt_len = VUSB_EP_MAX_LENGTH_TRANSFER; + } + else + { + curr_pkt_len = remaining_len; + } /* Endif */ + + /* Get a dTD from the queue */ + EHCI_DTD_QGET(usb_dev_ptr->DTD_HEAD, usb_dev_ptr->DTD_TAIL, dTD_ptr); + + if (!dTD_ptr) + { + USB_printf("Error: Can't get dTD\n"); + return USBERR_TR_FAILED; + } /* Endif */ + + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_add_count++)); + + remaining_len -= curr_pkt_len; + + usb_dev_ptr->DTD_ENTRIES--; + + if (curr_offset == 0) + { + first_dTD_ptr = dTD_ptr; + } /* Endif */ + + /* Zero the dTD. Leave the last 4 bytes as that is the scratch pointer */ + USB_memzero((void *) dTD_ptr,(sizeof(VUSB20_EP_TR_STRUCT) - 4)); + + /* Initialize the dTD */ + dTD_ptr->SCRATCH_PTR->PRIVATE = handle; + + /* Set the Terminate bit */ + dTD_ptr->NEXT_TR_ELEM_PTR = USB_32BIT_LE(VUSB_EP_QUEUE_HEAD_NEXT_TERMINATE); + + /************************************************************* + FIX ME: For hig-speed and high-bandwidth ISO IN endpoints, + we must initialize the multiplied field so that Host can issues + multiple IN transactions on the endpoint. See the DTD data + structure for MultiIO field. + + S Garg 11/06/2003 + *************************************************************/ + + /* Fill in the transfer size */ + if (!remaining_len) + { + dTD_ptr->SIZE_IOC_STS = USB_32BIT_LE((curr_pkt_len << + VUSBHS_TD_LENGTH_BIT_POS) | (VUSBHS_TD_IOC) | (VUSBHS_TD_STATUS_ACTIVE)); + } + else + { + dTD_ptr->SIZE_IOC_STS = USB_32BIT_LE((curr_pkt_len << VUSBHS_TD_LENGTH_BIT_POS) + | VUSBHS_TD_STATUS_ACTIVE); + } /* Endif */ + + /* Set the reserved field to 0 */ + dTD_ptr->SIZE_IOC_STS &= ~USB_32BIT_LE(VUSBHS_TD_RESERVED_FIELDS); + + /* 4K apart buffer page pointers */ + if(xd_ptr->WSTARTADDRESS != NULL) + { + uint_32 physAddr = USB_virt_to_phys((uint_8*)xd_ptr->WSTARTADDRESS + curr_offset); + + dTD_ptr->BUFF_PTR0 = USB_32BIT_LE(physAddr); + + physAddr += 4096; + dTD_ptr->BUFF_PTR1 = USB_32BIT_LE(physAddr); + + physAddr += 4096; + dTD_ptr->BUFF_PTR2 = USB_32BIT_LE(physAddr); + + physAddr += 4096; + dTD_ptr->BUFF_PTR3 = USB_32BIT_LE(physAddr); + + physAddr += 4096; + dTD_ptr->BUFF_PTR4 = USB_32BIT_LE(physAddr); + } + else + { + dTD_ptr->BUFF_PTR0 = dTD_ptr->BUFF_PTR1 = dTD_ptr->BUFF_PTR2 = 0; + dTD_ptr->BUFF_PTR3 = dTD_ptr->BUFF_PTR4 = 0; + } + curr_offset += curr_pkt_len; + + /* Maintain the first and last device transfer descriptor per + ** endpoint and direction + */ + if (!usb_dev_ptr->EP_DTD_HEADS[temp]) + { + usb_dev_ptr->EP_DTD_HEADS[temp] = dTD_ptr; + /*********************************************** + If list does not have a head, it means that list + is empty. An empty condition is detected. + ***********************************************/ + list_empty = TRUE; + } /* Endif */ + + /* Check if the transfer is to be queued at the end or beginning */ + temp_dTD_ptr = usb_dev_ptr->EP_DTD_TAILS[temp]; + + /* Remember which XD to use for this dTD */ + dTD_ptr->SCRATCH_PTR->XD_FOR_THIS_DTD = (pointer)xd_ptr; + + /* New tail */ + usb_dev_ptr->EP_DTD_TAILS[temp] = dTD_ptr; + if (temp_dTD_ptr) + { + /* Should not do |=. The Terminate bit should be zero */ + temp_dTD_ptr->NEXT_TR_ELEM_PTR = USB_32BIT_LE(USB_DTD_VIRT_TO_PHYS(usb_dev_ptr, dTD_ptr)); + } /* Endif */ + } while (remaining_len); /* EndWhile */ + + + /************************************************************** + In the loop above DTD has already been added to the list + However endpoint has not been primed yet. If list is not empty + we need safter ways to add DTD to the existing list. + Else we just skip to adding DTD to QH safely. + **************************************************************/ + + if(list_empty == FALSE) + { + volatile boolean read_safe = FALSE; + uint_32 prime, temp_ep_stat=0; + + /********************************************************* + Hardware v3.2+ require the use of semaphore to ensure that + QH is safely updated. + *********************************************************/ + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_add_not_empty_count++)); + + /********************************************************* + Check the prime bit. If set goto done + *********************************************************/ + prime = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME); +/* + USB_printf("%03d: Add not empty: bit_pos=%x, prime=0x%x, status=0x%x\n", + usb_dev_ptr->STATS.usb_add_not_empty_count, prime, bit_pos, + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS), + USB_32BIT_LE(ep_queue_head_ptr->SIZE_IOC_INT_STS) ); +*/ + if(prime & bit_pos) + { + timeout = 0x1000; + while( dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME + & USB_32BIT_LE(bit_pos) ) + { + /* Wait for the ENDPTPRIME to go to zero */ + timeout--; + if(timeout <= 0) + { + USB_printf( + "timeout: CTRL=%x, PRIME=%x, STAT=%x, INTR=%x, ADDR=%x, PORTSC=%x, dTD=%p, temp_dTD=%p\n", + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[0]), + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME), + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS), + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_STS), + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.DEVICE_ADDR), + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]), + first_dTD_ptr, temp_dTD_ptr); + + _usb_ep_status(handle, xd_ptr->EP_NUM, xd_ptr->BDIRECTION); + + return USBERR_TR_FAILED; + } + } /* EndWhile */ + + /*ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_TRANSFER,*/ + if(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS & USB_32BIT_LE(bit_pos)) + { + goto done; + } + } + + read_safe = FALSE; + timeout = 1000000; + while(read_safe == FALSE) + { + timeout--; + if(timeout <= 0) + { + USB_printf("%s: Timeout for ATDTW_TRIPWIRE reg = 0x%x\n", __FUNCTION__, + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD)); + return USBERR_TR_FAILED; + } + + /********************************************************* + start with setting the semaphores + *********************************************************/ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD |= + USB_32BIT_LE(EHCI_CMD_ATDTW_TRIPWIRE_SET); + + /********************************************************* + Read the endpoint status + *********************************************************/ + temp_ep_stat = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS) + & bit_pos; + + /********************************************************* + Reread the ATDTW semaphore bit to check if it is cleared. + When hardware see a hazard, it will clear the bit or + else we remain set to 1 and we can proceed with priming + of endpoint if not already primed. + *********************************************************/ + if( dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD & + USB_32BIT_LE(EHCI_CMD_ATDTW_TRIPWIRE_SET)) + { + read_safe = TRUE; + } + + }/*end while loop */ + + /********************************************************* + Clear the semaphore + *********************************************************/ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD &= + USB_32BIT_LE(EHCI_CMD_ATDTW_TRIPWIRE_CLEAR); + + /********************************************************* + * If endpoint is not active, we activate it now. + *********************************************************/ + if(!temp_ep_stat) + { + /* No other transfers on the queue */ + ep_queue_head_ptr->NEXT_DTD_PTR = USB_32BIT_LE( + USB_DTD_VIRT_TO_PHYS(usb_dev_ptr, first_dTD_ptr)); + ep_queue_head_ptr->SIZE_IOC_INT_STS = 0; + + /* Prime the Endpoint */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME = USB_32BIT_LE(bit_pos); + } + } + else + { + /* No other transfers on the queue */ + ep_queue_head_ptr->NEXT_DTD_PTR = USB_32BIT_LE( + USB_DTD_VIRT_TO_PHYS(usb_dev_ptr, first_dTD_ptr)); + ep_queue_head_ptr->SIZE_IOC_INT_STS = 0; + + /* Prime the Endpoint */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME = USB_32BIT_LE(bit_pos); + /* delay */ + timeout = 0x100; + while(timeout > 0) + timeout--; + + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME = USB_32BIT_LE(bit_pos); + } + +done: + if(first_dTD_ptr == NULL) + USB_printf("ERROR !!!! first_dTD_ptr=NULL\n"); + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_TRANSFER, + " add_%d: fri=0x%x, ep=%d%s, buf=%p, size=%d, xd=%p, dTD=%p %p, empty=%d\n", + usb_dev_ptr->STATS.usb_add_count & 0xFFFF, + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_FRINDEX), + xd_ptr->EP_NUM, xd_ptr->BDIRECTION ? "in" : "out", + xd_ptr->WSTARTADDRESS, (int)xd_ptr->WTOTALLENGTH, + xd_ptr, (unsigned)first_dTD_ptr, + usb_dev_ptr->EP_DTD_HEADS[temp], list_empty); + + + return USB_OK; + /* End CR 1015 */ +} /* EndBody */ + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_process_tr_complete +* Returned Value : None +* Comments : +* Services transaction complete interrupt +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_process_tr_complete + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + volatile VUSB20_REG_STRUCT_PTR dev_ptr; + volatile VUSB20_EP_TR_STRUCT_PTR dTD_ptr; + VUSB20_EP_TR_STRUCT_PTR temp_dTD_ptr; + VUSB20_EP_QUEUE_HEAD_STRUCT_PTR ep_queue_head_ptr; + uint_32 temp, i, ep_num = 0, direction = 0, bit_pos; + uint_32 remaining_length = 0; + uint_32 actual_transfer_length = 0; + uint_32 counter, errors = 0; + XD_STRUCT_PTR xd_ptr; + XD_STRUCT_PTR temp_xd_ptr = NULL; + uint_8_ptr buff_start_address = NULL; + boolean endpoint_detected = FALSE; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_complete_isr_count++)); + + /* We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE because the + ** setup packets are to be read ASAP + */ + + /* Process all Setup packet received interrupts */ + bit_pos = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPT_SETUP_STAT); + + if (bit_pos) + { + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, "setup_isr: bit_pos=0x%x\n", (unsigned)bit_pos); + for(i=0; iSTATS.usb_setup_count++)); + _usb_device_call_service(handle, i, TRUE, 0, 0, 8, 0); + } /* Endif */ + } /* Endfor */ + } /* Endif */ + + /* Don't clear the endpoint setup status register here. It is cleared as a + ** setup packet is read out of the buffer + */ + + /* Process non-setup transaction complete interrupts */ + bit_pos = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCOMPLETE); + + /* Clear the bits in the register */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCOMPLETE = USB_32BIT_LE(bit_pos); + + if (bit_pos) + { + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_complete_count++)); + + /* Get the endpoint number and the direction of transfer */ + counter = 0; + for (i=0; i<(ARC_USB_MAX_ENDPOINTS*2); i++) + { + endpoint_detected = FALSE; + if ((i < ARC_USB_MAX_ENDPOINTS) && (bit_pos & (1 << i))) + { + ep_num = i; + direction = ARC_USB_RECV; + endpoint_detected = TRUE; + } + else + { + if( (i >= ARC_USB_MAX_ENDPOINTS) && + (bit_pos & (1 << (i+16-ARC_USB_MAX_ENDPOINTS)))) + { + ep_num = (i - ARC_USB_MAX_ENDPOINTS); + direction = ARC_USB_SEND; + endpoint_detected = TRUE; + } + } + + if(endpoint_detected) + { + temp = (2*ep_num + direction); + + /* Get the first dTD */ + dTD_ptr = usb_dev_ptr->EP_DTD_HEADS[temp]; + + ep_queue_head_ptr = (VUSB20_EP_QUEUE_HEAD_STRUCT_PTR)usb_dev_ptr->EP_QUEUE_HEAD_PTR + temp; + + /* Process all the dTDs for respective transfers */ + while (dTD_ptr) + { + if (USB_32BIT_LE(dTD_ptr->SIZE_IOC_STS) & VUSBHS_TD_STATUS_ACTIVE) + { + /* No more dTDs to process. Next one is owned by VUSB */ + if(counter == 0) + { + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_ISR, "tr_complete - break: ep=%d %s, bit_pos=0x%x\n", + (unsigned)ep_num, direction ? "SEND" : "RECV", (unsigned)bit_pos); + + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_empty_complete_count++)); + } + break; + } /* Endif */ + + /* Get the correct internal transfer descriptor */ + xd_ptr = (XD_STRUCT_PTR)dTD_ptr->SCRATCH_PTR->XD_FOR_THIS_DTD; + if (xd_ptr) + { + buff_start_address = xd_ptr->WSTARTADDRESS; + actual_transfer_length = xd_ptr->WTOTALLENGTH; + temp_xd_ptr = xd_ptr; + } /* Endif */ + + /* Get the address of the next dTD */ + temp_dTD_ptr = (VUSB20_EP_TR_STRUCT_PTR)USB_DTD_PHYS_TO_VIRT(usb_dev_ptr, + (uint_32)(USB_32BIT_LE(dTD_ptr->NEXT_TR_ELEM_PTR) & VUSBHS_TD_ADDR_MASK) ); + + /* Read the errors */ + errors = (USB_32BIT_LE(dTD_ptr->SIZE_IOC_STS) & VUSBHS_TD_ERROR_MASK); + if (!errors) + { + /* No errors */ + /* Get the length of transfer from the current dTD */ + remaining_length += ((USB_32BIT_LE(dTD_ptr->SIZE_IOC_STS) & VUSB_EP_TR_PACKET_SIZE) >> 16); + actual_transfer_length -= remaining_length; + } + else + { + if (errors & VUSBHS_TD_STATUS_HALTED) + { + /* Clear the errors and Halt condition */ + ep_queue_head_ptr->SIZE_IOC_INT_STS &= USB_32BIT_LE(~errors); + } /* Endif */ + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_ERROR, + "complete_tr ERROR: ep=%d %s: STS=0x%x, dTD=%p, dTD_next=%p, xd=%p, qh->sts=0x%x\n", + (unsigned)ep_num, direction ? "SEND" : "RECV", + (unsigned)dTD_ptr->SIZE_IOC_STS, dTD_ptr, temp_dTD_ptr, + xd_ptr, ep_queue_head_ptr->SIZE_IOC_INT_STS); + } /* Endif */ + + /* Retire the processed dTD */ + counter++; + _usb_dci_vusb20_cancel_transfer(handle, ep_num, direction); + if( (temp_dTD_ptr == NULL) || + (temp_dTD_ptr->SCRATCH_PTR->XD_FOR_THIS_DTD != temp_xd_ptr) ) + { + /* Transfer complete. Call the register service function for the endpoint */ + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_complete_ep_count[temp]++)); + +#if defined(USB_UNDERRUN_WA) + if( (direction == ARC_USB_SEND) && + (((ep_queue_head_ptr->MAX_PKT_LENGTH >> 16) & 0x7FF) > global_wa_threshold) ) + usbSendComplete(handle, ep_num, FALSE, direction, + buff_start_address, actual_transfer_length, errors); + else +#endif /* USB_UNDERRUN_WA */ + _usb_device_call_service(handle, ep_num, FALSE, direction, + buff_start_address, actual_transfer_length, errors); + remaining_length = 0; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_TRANSFER, + "comp_%d: fri=0x%x, ep=%d%s, buf=%p, size=%d, xd=%p, dTD=%p %p %p, COMP=0x%x\n", + usb_dev_ptr->STATS.usb_complete_count & 0xFFFF, + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_FRINDEX), + (unsigned)ep_num, direction ? "in" : "out", + buff_start_address, actual_transfer_length, + temp_xd_ptr, dTD_ptr, temp_dTD_ptr, usb_dev_ptr->EP_DTD_HEADS[temp], (unsigned)bit_pos); + + } /* Endif */ + else + { + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_TRANSFER, "tr_complete not completed: ep=%d %s\n", + (unsigned)ep_num, direction ? "SEND" : "RECV"); + } + if( (temp_dTD_ptr == NULL) && (usb_dev_ptr->EP_DTD_HEADS[temp] != NULL) ) + { +/* + USB_printf("tr_complete: ep=%d, temp_dTD=%p, dTD_ptr=%p (%p), DTD_HEADS=%p, remain=%d\n", + temp, temp_dTD_ptr, dTD_ptr, + USB_DTD_PHYS_TO_VIRT(usb_dev_ptr, (uint_32)(USB_32BIT_LE(dTD_ptr->NEXT_TR_ELEM_PTR) & VUSBHS_TD_ADDR_MASK) ), + usb_dev_ptr->EP_DTD_HEADS[temp], remaining_length); +*/ + dTD_ptr = usb_dev_ptr->EP_DTD_HEADS[temp]; + } + else + { + dTD_ptr = temp_dTD_ptr; + } + errors = 0; + } /* Endwhile */ + } /* Endif */ + } /* Endfor */ + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, + ( {if(usb_dev_ptr->STATS.usb_complete_max_count < counter) + usb_dev_ptr->STATS.usb_complete_max_count = counter;})); + } /* Endif */ +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_isr +* Returned Value : None +* Comments : +* Services all the VUSB_HS interrupt sources +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_isr + ( + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + uint_32 status; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_isr_count++)); + + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + status = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_STS); + + status &= USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_INTR); + + if(status == 0) + { + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_empty_isr_count++)); + return; + } /* Endif */ +/* + USB_printf("USB_ISR: FRINDEX=0x%x, status=0x%x, PORTSC=0x%x, EP_SETUP=0x%x, EP_COMPLETE=0x%x\n", + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_FRINDEX), + status, + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]), + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPT_SETUP_STAT), + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCOMPLETE) ); +*/ + /* Clear all the interrupts occured */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_STS = USB_32BIT_LE(status); + + if (status & EHCI_STS_ERR) + { + usb_dev_ptr->ERROR_STATE = (status & 0xFFFF); + + _usb_dci_vusb20_process_error((pointer)usb_dev_ptr); + /* do tr_complete if no STS_INT set */ + if( (status & EHCI_STS_INT) == 0) + _usb_dci_vusb20_process_tr_complete((pointer)usb_dev_ptr); + + /*USB_printf("USB process error: status=0x%x\n", status);*/ + } /* Endif */ + + if (status & EHCI_STS_RESET) + { + _usb_dci_vusb20_process_reset((pointer)usb_dev_ptr); + } /* Endif */ + + if (status & EHCI_STS_PORT_CHANGE) + { + _usb_dci_vusb20_process_port_change((pointer)usb_dev_ptr); + } /* Endif */ + + if (status & EHCI_STS_SOF) + { + _usb_dci_vusb20_process_SOF((pointer)usb_dev_ptr); + } /* Endif */ + + if (status & EHCI_STS_INT) + { + _usb_dci_vusb20_process_tr_complete((pointer)usb_dev_ptr); + } /* Endif */ + + if (status & EHCI_STS_SUSPEND) + { + _usb_dci_vusb20_process_suspend((pointer)usb_dev_ptr); + } /* Endif */ + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_process_reset +* Returned Value : None +* Comments : +* Services reset interrupt +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_process_reset + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + uint_32 temp; + volatile unsigned long timeout; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_ISR, "process_reset\n"); + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_reset_count++)); + + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Inform the application so that it can cancel all previously queued transfers */ + _usb_device_call_service(usb_dev_ptr, ARC_USB_SERVICE_BUS_RESET, 0, 0, 0, 0, 0); + +#if defined(USB_UNDERRUN_WA) + _usb_reset_send_queue(); +#endif /* USB_UNDERRUN_WA */ + + /* The address bits are past bit 25-31. Set the address */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.DEVICE_ADDR &= ~USB_32BIT_LE(0xFE000000); + + /* Clear all the setup token semaphores */ + temp = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPT_SETUP_STAT); + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPT_SETUP_STAT = USB_32BIT_LE(temp); + + /* Clear all the endpoint complete status bits */ + temp = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCOMPLETE); + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCOMPLETE = USB_32BIT_LE(temp); + + timeout = 0x10000; + while (USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME) & 0xFFFFFFFF) + { + timeout--; + if(timeout <= 0) + { + USB_printf("%s: Timeout for ENDPTPRIME = 0x%x\n", __FUNCTION__, + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME)); + break; + } + + /* Wait until all ENDPTPRIME bits cleared */ + } /* Endif */ + + /* Write 1s to the Flush register */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTFLUSH = USB_32BIT_LE(0xFFFFFFFF); + + if( (usb_dev_ptr->ERROR_STATE == 0x0) && + (USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]) & + EHCI_PORTSCX_PORT_RESET) ) + { + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_RESET, + "USB Bus Reset: fri=0x%x, dev_ptr=%p, STATE=%d, PORTSC=0x%x, CMD=0x%x, ENDPT[0]=0x%x\n", + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_FRINDEX), + usb_dev_ptr, usb_dev_ptr->USB_STATE, + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]), + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD), + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[0])); + + usb_dev_ptr->BUS_RESETTING = TRUE; + usb_dev_ptr->USB_STATE = ARC_USB_STATE_POWERED; + } + else + { + USB_printf("USB Chip reinit: PORTSC=0x%x\n", + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0])); + + /* re-initialize */ + _usb_dci_vusb20_chip_initialize((pointer)usb_dev_ptr); + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_INIT, "process_reset, Chip reinit hw\n"); + } /* Endif */ + + _usb_device_call_service(usb_dev_ptr, ARC_USB_SERVICE_BUS_RESET, 1, 0, 0, 0, 0); + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_process_suspend +* Returned Value : None +* Comments : +* Services suspend interrupt +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_process_suspend + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_ISR, "process_suspend\n"); + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_suspend_count++)); + + usb_dev_ptr->USB_DEV_STATE_B4_SUSPEND = usb_dev_ptr->USB_STATE; + + usb_dev_ptr->USB_STATE = ARC_USB_STATE_SUSPEND; + + /* Inform the upper layers */ + _usb_device_call_service(usb_dev_ptr, ARC_USB_SERVICE_SLEEP, 0, 0, 0, 0, 0); + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_process_SOF +* Returned Value : None +* Comments : +* Services SOF interrupt +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_process_SOF + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_ISR, "process_SOF\n"); + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Inform the upper layer */ + _usb_device_call_service(usb_dev_ptr, ARC_USB_SERVICE_SOF, 0, 0, 0, + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_FRINDEX), 0); + +} /* EndBody */ + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_process_port_change +* Returned Value : None +* Comments : +* Services port change detect interrupt +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_process_port_change + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_ISR, "process_port_change\n"); + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_port_change_count++)); + + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; +/* + USB_printf("port_change: PORTSC=0x%x, DTD_ENTRIES=%d, XD_ENTRIES=%d\n", + USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]), + usb_dev_ptr->DTD_ENTRIES, usb_dev_ptr->XD_ENTRIES); +*/ + if (usb_dev_ptr->BUS_RESETTING) + { + /* Bus reset operation complete */ + usb_dev_ptr->BUS_RESETTING = FALSE; + } /* Endif */ + + if (!(USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]) & + EHCI_PORTSCX_PORT_RESET)) + { + /* Get the speed */ + if (USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]) & + EHCI_PORTSCX_PORT_HIGH_SPEED) + { + usb_dev_ptr->SPEED = ARC_USB_SPEED_HIGH; + } + else + { + usb_dev_ptr->SPEED = ARC_USB_SPEED_FULL; + } /* Endif */ +/* + USB_printf("USB %s speed device detected\n", + (usb_dev_ptr->SPEED == ARC_USB_SPEED_HIGH) ? "High" : "Full"); +*/ + /* Inform the upper layers of the speed of operation */ + _usb_device_call_service(usb_dev_ptr, ARC_USB_SERVICE_SPEED_DETECTION, 0, 0, + 0, usb_dev_ptr->SPEED, 0); + } /* Endif */ + + if (USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]) & + EHCI_PORTSCX_PORT_SUSPEND) + { + usb_dev_ptr->USB_DEV_STATE_B4_SUSPEND = usb_dev_ptr->USB_STATE; + usb_dev_ptr->USB_STATE = ARC_USB_STATE_SUSPEND; + + /* Inform the upper layers */ + USB_printf("USB suspend\n"); + _usb_device_call_service(usb_dev_ptr, ARC_USB_SERVICE_SUSPEND, 0, 0, 0, 0, 0); + } /* Endif */ + + if (!(USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]) & EHCI_PORTSCX_PORT_SUSPEND) + && (usb_dev_ptr->USB_STATE == ARC_USB_STATE_SUSPEND)) + { + USB_printf("USB resume\n"); + usb_dev_ptr->USB_STATE = usb_dev_ptr->USB_DEV_STATE_B4_SUSPEND; + /* Inform the upper layers */ + _usb_device_call_service(usb_dev_ptr, ARC_USB_SERVICE_RESUME, 0, 0, 0, 0, 0); + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SUSPEND, "process_port_change, SUCCESSFUL, resumed\n"); + return; + } /* Endif */ + + usb_dev_ptr->USB_STATE = ARC_USB_STATE_DEFAULT; + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_process_error +* Returned Value : None +* Comments : +* Services error interrupt +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_process_error + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + /* Increment the error count */ + usb_dev_ptr->ERRORS++; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_ERROR, + "process_error_%d: state=0x%x\n", + usb_dev_ptr->ERRORS, usb_dev_ptr->ERROR_STATE); +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_set_speed_full +* Returned Value : None +* Comments : +* Force the controller port in full speed mode. +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_set_speed_full + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* The port number on the device */ + uint_8 port_number + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + uint_32 port_control; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_ANY, "FORCE set_speed_full\n"); + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + port_control = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[port_number]); + port_control |= EHCI_PORTSCX_FORCE_FULL_SPEED_CONNECT; + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[port_number] = USB_32BIT_LE(port_control); + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_suspend_phy +* Returned Value : None +* Comments : +* Suspends the PHY in low power mode +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_suspend_phy + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* The port number on the device */ + uint_8 port_number + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + uint_32 port_control; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SUSPEND, "set_suspend_phy\n"); + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + port_control = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[port_number]); + port_control |= EHCI_PORTSCX_PHY_CLOCK_DISABLE; + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[port_number] = USB_32BIT_LE(port_control); + +} /* EndBody */ + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_set_address +* Returned Value : None +* Comments : +* Sets the newly assigned device address +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_set_address + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* Address of the device assigned by the host */ + uint_8 address + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_ADDR, "set_address: address=%d\n",address); + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + +#ifdef SET_ADDRESS_HARDWARE_ASSISTANCE + /*********************************************************** + Hardware Rev 4.0 onwards have special assistance built in + for handling the set_address command. As per the USB specs + a device should be able to receive the response on a new + address, within 2 msecs after status phase of set_address is + completed. Since 2 mili second may be a very small time window + (on high interrupt latency systems) before software could + come to the code below and write the device register, + this routine will be called in advance when status phase of + set_address is still not finished. The following line in the + code will set the bit 24 to '1' and hardware will take + the address and queue it in an internal buffer. From which + it will use it to decode the next USB token. Please look + at hardware rev details for the implementation of this + assistance. + + Also note that writing bit 24 to 0x01 will not break + any old hardware revs because it was an unused bit. + ***********************************************************/ + /* The address bits are past bit 25-31. Set the address + also set the bit 24 to 0x01 to start hardware assitance*/ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.DEVICE_ADDR = + USB_32BIT_LE((uint_32)address << VUSBHS_ADDRESS_BIT_SHIFT) | + (0x01 << (VUSBHS_ADDRESS_BIT_SHIFT -1)); +#else + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.DEVICE_ADDR = + USB_32BIT_LE((uint_32)address << VUSBHS_ADDRESS_BIT_SHIFT); +#endif /* SET_ADDRESS_HARDWARE_ASSISTANCE */ + + usb_dev_ptr->USB_STATE = ARC_USB_STATE_ADDRESS; + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_get_setup_data +* Returned Value : None +* Comments : +* Reads the Setup data from the 8-byte setup buffer +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_get_setup_data + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [OUT] address of the buffer to read the setup data into */ + uint_8_ptr buffer_ptr + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + volatile VUSB20_REG_STRUCT_PTR dev_ptr; + volatile VUSB20_EP_QUEUE_HEAD_STRUCT_PTR ep_queue_head_ptr; + volatile boolean read_safe = FALSE; + volatile unsigned long timeout; + + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Get the endpoint queue head */ + ep_queue_head_ptr = (VUSB20_EP_QUEUE_HEAD_STRUCT_PTR)usb_dev_ptr->EP_QUEUE_HEAD_PTR + + 2*ep_num + ARC_USB_RECV; + + /******************************************************************** + CR 1219. Hardware versions 2.3+ have a implementation of tripwire + semaphore mechanism that requires that we read the contents of + QH safely by using the semaphore. Read the USBHS document to under + stand how the code uses the semaphore mechanism. The following are + the steps in brief + + 1. USBCMD Write ‘1’ to Setup Tripwire in register. + 2. Duplicate contents of dQH.StatusBuffer into local software byte + array. + 3 Read Setup TripWire in register. (if set - continue; if + cleared goto 1.) + 4. Write '0' to clear Setup Tripwire in register. + 5. Process setup packet using local software byte array copy and + execute status/handshake phases. + + + ********************************************************************/ + timeout = 0x100000; + while(!read_safe) + { + /********************************************************* + start with setting the semaphores + *********************************************************/ + + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD |= + USB_32BIT_LE(EHCI_CMD_SETUP_TRIPWIRE_SET); + + /* Copy the setup packet to private buffer */ + USB_memcopy((uint_8_ptr)ep_queue_head_ptr->SETUP_BUFFER, buffer_ptr, 8); + + /********************************************************* + If setup tripwire semaphore is cleared by hardware it means + that we have a danger and we need to restart. + else we can exit out of loop safely. + *********************************************************/ + if(USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD) & + EHCI_CMD_SETUP_TRIPWIRE_SET) + { + read_safe = TRUE; /* we can proceed exiting out of loop*/ + } + if(timeout <= 0) + { + USB_printf("%s: Timeout for SETUP_TRIPWIRE = 0x%x\n", __FUNCTION__, + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD)); + break; + } + } + ARC_DEBUG_CODE(ARC_DEBUG_FLAG_STATS, (usb_dev_ptr->STATS.usb_read_setup_count++)); + + /********************************************************* + Clear the semaphore bit now + *********************************************************/ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD &= + USB_32BIT_LE(EHCI_CMD_SETUP_TRIPWIRE_CLEAR); + + /* Clear the bit in the ENDPTSETUPSTAT */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPT_SETUP_STAT = USB_32BIT_LE(1 << ep_num); + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_init_endpoint +* Returned Value : None +* Comments : +* Initializes the specified endpoint and the endpoint queue head +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_dci_vusb20_init_endpoint + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the transaction descriptor address */ + XD_STRUCT_PTR xd_ptr + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + VUSB20_EP_QUEUE_HEAD_STRUCT _PTR_ ep_queue_head_ptr; + uint_32 val, bit_pos; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Get the endpoint queue head address */ + ep_queue_head_ptr = (VUSB20_EP_QUEUE_HEAD_STRUCT_PTR)usb_dev_ptr->EP_QUEUE_HEAD_PTR + + 2*xd_ptr->EP_NUM + xd_ptr->BDIRECTION; + + bit_pos = (1 << (16 * xd_ptr->BDIRECTION + xd_ptr->EP_NUM)); + + /* Check if the Endpoint is Primed */ + if ((!(USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME) & bit_pos)) && + (!(USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS) & bit_pos))) + { + /* Set the max packet length, interrupt on Setup and Mult fields */ + if (xd_ptr->EP_TYPE == ARC_USB_ISOCHRONOUS_ENDPOINT) + { + /* Mult bit should be set for isochronous endpoints */ + ep_queue_head_ptr->MAX_PKT_LENGTH = USB_32BIT_LE((xd_ptr->WMAXPACKETSIZE << 16) | + ((xd_ptr->MAX_PKTS_PER_UFRAME ? xd_ptr->MAX_PKTS_PER_UFRAME : 1) << + VUSB_EP_QUEUE_HEAD_MULT_POS)); + } + else + { + if (xd_ptr->EP_TYPE != ARC_USB_CONTROL_ENDPOINT) + { + /* BULK or INTERRUPT */ + ep_queue_head_ptr->MAX_PKT_LENGTH = USB_32BIT_LE((xd_ptr->WMAXPACKETSIZE << 16) | + (xd_ptr->DONT_ZERO_TERMINATE ? VUSB_EP_QUEUE_HEAD_ZERO_LEN_TER_SEL : 0)); + } + else + { + /* CONTROL */ + ep_queue_head_ptr->MAX_PKT_LENGTH = USB_32BIT_LE((xd_ptr->WMAXPACKETSIZE << 16) | + VUSB_EP_QUEUE_HEAD_IOS); + } /* Endif */ + } /* Endif */ + + /* Enable the endpoint for Rx or Tx and set the endpoint type */ + val = dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[xd_ptr->EP_NUM]; + if(xd_ptr->BDIRECTION == ARC_USB_SEND) + { + val &= ~(USB_32BIT_LE(EHCI_EPCTRL_TX_ALL_MASK)); + val |= USB_32BIT_LE((EHCI_EPCTRL_TX_ENABLE | EHCI_EPCTRL_TX_DATA_TOGGLE_RST) | + (xd_ptr->EP_TYPE << EHCI_EPCTRL_TX_EP_TYPE_SHIFT)); + } + else + { + val &= ~(USB_32BIT_LE(EHCI_EPCTRL_RX_ALL_MASK)); + val |= USB_32BIT_LE((EHCI_EPCTRL_RX_ENABLE | EHCI_EPCTRL_RX_DATA_TOGGLE_RST) | + (xd_ptr->EP_TYPE << EHCI_EPCTRL_RX_EP_TYPE_SHIFT)); + } + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[xd_ptr->EP_NUM] = val; + + /* Implement Guideline (GL# USB-7) The unused endpoint type must */ + /* be programmed to bulk. */ + if( (dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[xd_ptr->EP_NUM] & + USB_32BIT_LE(EHCI_EPCTRL_RX_ENABLE)) == 0) + { + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[xd_ptr->EP_NUM] |= + USB_32BIT_LE(ARC_USB_BULK_ENDPOINT << EHCI_EPCTRL_RX_EP_TYPE_SHIFT); + } + + if( (dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[xd_ptr->EP_NUM] & + USB_32BIT_LE(EHCI_EPCTRL_TX_ENABLE)) == 0) + { + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[xd_ptr->EP_NUM] |= + USB_32BIT_LE(ARC_USB_BULK_ENDPOINT << EHCI_EPCTRL_TX_EP_TYPE_SHIFT); + } + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_INIT, + "init ep #%d %s: type=0x%x, EPCTRLX=0x%x, SETUP=0x%x, PRIME=0x%x, STATUS=0x%x, COMPL=0x%x\n", + xd_ptr->EP_NUM, xd_ptr->BDIRECTION ? "SEND" : "RECV", xd_ptr->EP_TYPE, + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[xd_ptr->EP_NUM]), + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPT_SETUP_STAT), + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME), + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS), + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCOMPLETE) ); + } + else + { + USB_printf("ep=%d %s: Init ERROR: ENDPTPRIME=0x%x, ENDPTSTATUS=0x%x, bit_pos=0x%x\n", + (unsigned)xd_ptr->EP_NUM, xd_ptr->BDIRECTION ? "SEND" : "RECV", + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME), + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS), + (unsigned)bit_pos); + return USBERR_EP_INIT_FAILED; + } /* Endif */ + + return USB_OK; + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_get_transfer_status +* Returned Value : USB_OK or error code +* Comments : +* Gets the status of a transfer +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_dci_vusb20_get_transfer_status + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] direction */ + uint_8 direction + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_EP_TR_STRUCT_PTR dTD_ptr; + XD_STRUCT_PTR xd_ptr; + uint_8 status; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + + /* Unlink the dTD */ + dTD_ptr = usb_dev_ptr->EP_DTD_HEADS[2*ep_num + direction]; + + if (dTD_ptr) + { + /* Get the transfer descriptor for the dTD */ + xd_ptr = (XD_STRUCT_PTR)dTD_ptr->SCRATCH_PTR->XD_FOR_THIS_DTD; + status = xd_ptr->BSTATUS; + } + else + { + status = ARC_USB_STATUS_IDLE; + } /* Endif */ + + return (status); + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_get_transfer_details +* Returned Value : pointer to structure that has details for transfer +* Gets the status of a transfer +* +*END*-----------------------------------------------------------------*/ +XD_STRUCT_PTR _usb_dci_vusb20_get_transfer_details + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] direction */ + uint_8 direction + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + VUSB20_EP_TR_STRUCT_PTR dTD_ptr, temp_dTD_ptr; + XD_STRUCT_PTR xd_ptr; + uint_32 temp, remaining_bytes; + VUSB20_EP_QUEUE_HEAD_STRUCT_PTR ep_queue_head_ptr; + + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + temp = (2*ep_num + direction); + + /* get a pointer to QH for this endpoint */ + ep_queue_head_ptr = (VUSB20_EP_QUEUE_HEAD_STRUCT_PTR)usb_dev_ptr->EP_QUEUE_HEAD_PTR + temp; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_TRACE, "get_transfer_details\n"); + + /* Unlink the dTD */ + dTD_ptr = usb_dev_ptr->EP_DTD_HEADS[2*ep_num + direction]; + + if (dTD_ptr) + { + /* Get the transfer descriptor for the dTD */ + xd_ptr = (XD_STRUCT_PTR)dTD_ptr->SCRATCH_PTR->XD_FOR_THIS_DTD; + if(!xd_ptr) return NULL; + + /* Initialize the transfer length field */ + xd_ptr->WSOFAR =0; + remaining_bytes =0; + + /*if length of this transfer is greater than 20K + we have multiple DTDs to count */ + if(xd_ptr->WTOTALLENGTH > VUSB_EP_MAX_LENGTH_TRANSFER) + { + /* it is a valid DTD. We should parse all DTDs for this XD + and find the total bytes used so far */ + temp_dTD_ptr = dTD_ptr; + + /*loop through the list of DTDS until an active DTD is found + or list has finished */ + while(!(USB_32BIT_LE(dTD_ptr->NEXT_TR_ELEM_PTR) & VUSBHS_TD_NEXT_TERMINATE)) + { + + /********************************************************** + If this DTD has been overlayed, we take the actual length + from QH. + **********************************************************/ + + if ((uint_32)(USB_32BIT_LE(ep_queue_head_ptr->CURR_DTD_PTR) & VUSBHS_TD_ADDR_MASK) == + USB_DTD_VIRT_TO_PHYS(usb_dev_ptr, temp_dTD_ptr) ) + { + remaining_bytes += + ((USB_32BIT_LE(ep_queue_head_ptr->SIZE_IOC_INT_STS) & VUSB_EP_TR_PACKET_SIZE) >> 16); + } + else + { + /* take the length from DTD itself */ + remaining_bytes += + ((USB_32BIT_LE(temp_dTD_ptr->SIZE_IOC_STS) & VUSB_EP_TR_PACKET_SIZE) >> 16); + } + + dTD_ptr = temp_dTD_ptr; + + /* Get the address of the next dTD */ + temp_dTD_ptr = (VUSB20_EP_TR_STRUCT_PTR)USB_DTD_PHYS_TO_VIRT(usb_dev_ptr, + (uint_32)(USB_32BIT_LE(temp_dTD_ptr->NEXT_TR_ELEM_PTR) & VUSBHS_TD_ADDR_MASK) ); + } + xd_ptr->WSOFAR = xd_ptr->WTOTALLENGTH - remaining_bytes; + } + else + { + /*look at actual length from QH*/ + xd_ptr->WSOFAR = xd_ptr->WTOTALLENGTH - + ((USB_32BIT_LE(ep_queue_head_ptr->SIZE_IOC_INT_STS) & VUSB_EP_TR_PACKET_SIZE) >> 16); + } + } + else + { + xd_ptr = NULL; + } /* Endif */ + + return (xd_ptr); + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_deinit_endpoint +* Returned Value : None +* Comments : +* Disables the specified endpoint and the endpoint queue head +* +*END*-----------------------------------------------------------------*/ +uint_8 _usb_dci_vusb20_deinit_endpoint + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] direction */ + uint_8 direction + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + VUSB20_EP_QUEUE_HEAD_STRUCT* ep_queue_head_ptr; + uint_32 bit_pos; + uint_8 status = USB_OK; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Get the endpoint queue head address */ + ep_queue_head_ptr = (VUSB20_EP_QUEUE_HEAD_STRUCT_PTR)usb_dev_ptr->EP_QUEUE_HEAD_PTR + + (2*ep_num + direction); + + bit_pos = (1 << (16 * direction + ep_num)); + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_INIT, + "deinit ep #%d-%s: bit_pos=0x%x, EPCTRLX=0x%x, SETUP=0x%x, PRIME=0x%x, STATUS=0x%x, COMPL=0x%x\n", + ep_num, direction ? "SEND" : "RECV", bit_pos, + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num]), + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPT_SETUP_STAT), + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME), + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS), + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCOMPLETE) ); + + /* Check if the Endpoint is Primed */ + if( ((USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME) & bit_pos)) || + ((USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS) & bit_pos)) ) + { + USB_printf("ep=%d %s: Deinit ERROR: ENDPTPRIME=0x%x, ENDPTSTATUS=0x%x, bit_pos=0x%x\n", + (unsigned)ep_num, direction ? "SEND" : "RECV", + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTPRIME), + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTSTATUS), + (unsigned)bit_pos); + status = USBERR_EP_DEINIT_FAILED; + } + + /* Reset the max packet length and the interrupt on Setup */ + ep_queue_head_ptr->MAX_PKT_LENGTH = 0; + + /* Disable the endpoint for Rx or Tx and reset the endpoint type */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num] &= + USB_32BIT_LE( ~((direction ? EHCI_EPCTRL_TX_ENABLE : EHCI_EPCTRL_RX_ENABLE) | + (direction ? EHCI_EPCTRL_TX_TYPE : EHCI_EPCTRL_RX_TYPE))); + + return status; +} + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_shutdown +* Returned Value : None +* Comments : +* Shuts down the VUSB_HS Device +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_shutdown + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Disable interrupts */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_INTR &= + ~(USB_32BIT_LE(EHCI_INTR_INT_EN | EHCI_INTR_ERR_INT_EN | + EHCI_INTR_PORT_CHANGE_DETECT_EN | EHCI_INTR_RESET_EN)); + + USB_uncached_memfree(usb_dev_ptr->EP_QUEUE_HEAD_BASE, + usb_dev_ptr->EP_QUEUE_HEAD_SIZE, + usb_dev_ptr->EP_QUEUE_HEAD_PHYS); + + USB_uncached_memfree(usb_dev_ptr->DTD_BASE_PTR, + usb_dev_ptr->DTD_SIZE, + usb_dev_ptr->DTD_BASE_PHYS); + + USB_memfree(usb_dev_ptr->SCRATCH_STRUCT_BASE); + + USB_printf("USB shutdown: usb_dev_ptr=%p\n", usb_dev_ptr); + + /* Reset the Run the bit in the command register to stop VUSB */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD &= ~USB_32BIT_LE(EHCI_CMD_RUN_STOP); + + /* Reset the controller to get default values */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD = USB_32BIT_LE(EHCI_CMD_CTRL_RESET); + +} /* EndBody */ +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_stop +* Returned Value : None +* Comments : +* Stop USB device controller +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_stop(_usb_device_handle handle) +{ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Disable interrupts */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_INTR &= + ~(USB_32BIT_LE(EHCI_INTR_INT_EN | EHCI_INTR_ERR_INT_EN | + EHCI_INTR_PORT_CHANGE_DETECT_EN | EHCI_INTR_RESET_EN)); + + /* Reset the Run the bit in the command register to stop VUSB */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD &= ~USB_32BIT_LE(EHCI_CMD_RUN_STOP); +} + + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_start +* Returned Value : None +* Comments : +* Start USB device controller +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_start(_usb_device_handle handle) +{ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Enable interrupts */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_INTR = USB_32BIT_LE( + EHCI_INTR_INT_EN + | EHCI_INTR_ERR_INT_EN + | EHCI_INTR_PORT_CHANGE_DETECT_EN + | EHCI_INTR_RESET_EN + | EHCI_INTR_DEVICE_SUSPEND + /* + | EHCI_INTR_SOF_UFRAME_EN + */ + ); + + usb_dev_ptr->USB_STATE = ARC_USB_STATE_UNKNOWN; + + /* Set the Run bit in the command register */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.USB_CMD = USB_32BIT_LE(EHCI_CMD_RUN_STOP); +} + +/* EOF */ + diff --git a/board/mv_feroceon/mv_hal/usb/device/mvUsbHsDevUtl.c b/board/mv_feroceon/mv_hal/usb/device/mvUsbHsDevUtl.c new file mode 100644 index 0000000..3cfb91c --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/device/mvUsbHsDevUtl.c @@ -0,0 +1,271 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#include "usb/api/mvUsbDevApi.h" +#include "usb/device/mvUsbDevPrv.h" +#include "usb/api/mvUsbDefs.h" + +/* Test packet for Test Mode : TEST_PACKET. USB 2.0 Specification section 7.1.20 */ +uint_8 test_packet[USB_TEST_MODE_TEST_PACKET_LENGTH] = +{ + /* Synch */ + /* DATA 0 PID */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, + 0xEE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xBF, 0xDF, + 0xEF, 0xF7, 0xFB, 0xFD, 0xFC, 0x7E, 0xBF, 0xDF, + 0xEF, 0xF7, 0xFB, 0xFD, 0x7E +}; + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_assert_resume +* Returned Value : None +* Comments : +* Resume signalling for remote wakeup +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_assert_resume + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + uint_32 temp; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Assert the Resume signal */ + temp = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]); + temp &= ~EHCI_PORTSCX_W1C_BITS; + temp |= EHCI_PORTSCX_PORT_FORCE_RESUME; + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0] = USB_32BIT_LE(temp); + + /* Port change interrupt will be asserted at the end of resume + ** operation + */ + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_stall_endpoint +* Returned Value : None +* Comments : +* Stalls the specified endpoint +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_stall_endpoint + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] direction */ + uint_8 direction + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + VUSB20_EP_QUEUE_HEAD_STRUCT _PTR_ ep_queue_head_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Get the endpoint queue head address */ + ep_queue_head_ptr = (VUSB20_EP_QUEUE_HEAD_STRUCT_PTR)usb_dev_ptr->EP_QUEUE_HEAD_PTR + + 2*ep_num + direction; + /* Stall the endpoint for Rx or Tx and set the endpoint type */ + if (ep_queue_head_ptr->MAX_PKT_LENGTH & USB_32BIT_LE(VUSB_EP_QUEUE_HEAD_IOS)) + { + /* This is a control endpoint so STALL both directions */ + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num] |= + USB_32BIT_LE((EHCI_EPCTRL_TX_EP_STALL | EHCI_EPCTRL_RX_EP_STALL)); + } + else + { + if(direction) + { + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num] |= + USB_32BIT_LE(EHCI_EPCTRL_TX_EP_STALL); + } + else { + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num] |= + USB_32BIT_LE(EHCI_EPCTRL_RX_EP_STALL); + } + } /* Endif */ + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_STALL, + "STALL ep=%d %s: EPCTRLX=0x%x, CURR_dTD=0x%x, NEXT_dTD=0x%x, SIZE=0x%x\n", + ep_num, direction ? "SEND" : "RECV", + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num]), + (unsigned)USB_32BIT_LE(ep_queue_head_ptr->CURR_DTD_PTR), + (unsigned)USB_32BIT_LE(ep_queue_head_ptr->NEXT_DTD_PTR), + (unsigned)USB_32BIT_LE(ep_queue_head_ptr->SIZE_IOC_INT_STS)); + +} /* EndBody */ + +/*FUNCTION*------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_unstall_endpoint +* Returned Value : None +* Comments : +* Unstall the specified endpoint in the specified direction +* +*END*-----------------------------------------------------------------*/ +void _usb_dci_vusb20_unstall_endpoint + ( + /* [IN] the USB_dev_initialize state structure */ + _usb_device_handle handle, + + /* [IN] the Endpoint number */ + uint_8 ep_num, + + /* [IN] direction */ + uint_8 direction + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + /* Enable the endpoint for Rx or Tx and set the endpoint type */ + if(direction) + { + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num] |= + USB_32BIT_LE(EHCI_EPCTRL_TX_DATA_TOGGLE_RST); + + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num] &= + ~(USB_32BIT_LE(EHCI_EPCTRL_TX_EP_STALL)); + } + else + { + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num] |= + USB_32BIT_LE(EHCI_EPCTRL_RX_DATA_TOGGLE_RST); + + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num] &= + ~(USB_32BIT_LE(EHCI_EPCTRL_RX_EP_STALL)); + } + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_STALL, + "UNSTALL ep=%d %s: EPCTRLX=0x%x\n", + ep_num, direction ? "SEND" : "RECV", + (unsigned)USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep_num])); + + +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_is_endpoint_stalled +* Returned Value : None +* Comments : +* Gets the endpoint status +* +*END*--------------------------------------------------------------------*/ +uint_8 _usb_dci_vusb20_is_endpoint_stalled + ( + /* [IN] Handle to the USB device */ + _usb_device_handle handle, + + /* [IN] Endpoint number */ + uint_8 ep, + + /* [IN] Endpoint direction */ + uint_8 dir + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + uint_32 value; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_TRACE, "is_endpoint_stalled\n"); + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + if(dir) + { + value = dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep] & + (USB_32BIT_LE(EHCI_EPCTRL_TX_EP_STALL)); + } + else + { + value = dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[ep] & + (USB_32BIT_LE(EHCI_EPCTRL_RX_EP_STALL)); + } + return (value) ? 1 : 0; +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _usb_dci_vusb20_set_test_mode +* Returned Value : None +* Comments : +* sets/resets the test mode +* +*END*--------------------------------------------------------------------*/ +void _usb_dci_vusb20_set_test_mode + ( + /* [IN] Handle to the USB device */ + _usb_device_handle handle, + + /* [IN] Test mode */ + uint_16 test_mode + ) +{ /* Body */ + USB_DEV_STATE_STRUCT_PTR usb_dev_ptr; + VUSB20_REG_STRUCT_PTR dev_ptr; + uint_32 temp; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_ANY, "set_test_mode\n"); + + usb_dev_ptr = (USB_DEV_STATE_STRUCT_PTR)handle; + dev_ptr = (VUSB20_REG_STRUCT_PTR)usb_dev_ptr->DEV_PTR; + + temp = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[0]); + + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.ENDPTCTRLX[0] = + USB_32BIT_LE((temp | EHCI_EPCTRL_TX_DATA_TOGGLE_RST)); + + if (test_mode == ARC_USB_TEST_MODE_TEST_PACKET) + { + USB_memcopy(test_packet, usb_dev_ptr->TEST_PKT_PTR, USB_TEST_MODE_TEST_PACKET_LENGTH); + _usb_device_send_data(handle, 0, usb_dev_ptr->TEST_PKT_PTR, USB_TEST_MODE_TEST_PACKET_LENGTH); + + } /* Endif */ + + temp = USB_32BIT_LE(dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0]); + temp &= ~EHCI_PORTSCX_W1C_BITS; + + dev_ptr->REGISTERS.OPERATIONAL_DEVICE_REGISTERS.PORTSCX[0] = + USB_32BIT_LE(temp | ((uint_32)test_mode << 8)); + +} /* EndBody */ + diff --git a/board/mv_feroceon/mv_hal/usb/examples/disk.c b/board/mv_feroceon/mv_hal/usb/examples/disk.c new file mode 100644 index 0000000..6876c12 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/examples/disk.c @@ -0,0 +1,2296 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +/************************************************************************** +Include the USB stack and local header files. +**************************************************************************/ + +#include "usb/api/mvUsbDefs.h" +#include "usb/api/mvUsbCh9.h" +#include "usb/api/mvUsbDebug.h" +#include "usb/api/mvUsbDevApi.h" +#include "usb/examples/disk.h" + +/* MSB of debug flags for USB device usage */ +#define ARC_DEBUG_FLAG_DISK 0x01000000 +#define ARC_DEBUG_FLAG_DISK_READ 0x02000000 +#define ARC_DEBUG_FLAG_DISK_WRITE 0x04000000 +#define ARC_DEBUG_FLAG_DISK_CAP 0x08000000 +#define ARC_DEBUG_FLAG_DISK_DATA 0x10000000 +#define ARC_DEBUG_FLAG_DISK_DUMP 0x20000000 + + +/************************************************************************** +Include the OS and BSP dependent files that define IO functions and +basic types. You may like to change these files for your board and RTOS +**************************************************************************/ + + +/************************************************************************** +Global variables and some defines for device. +**************************************************************************/ + +#define BUFFERSIZE (2048) + +#define EP_TEMP_BUFFERSIZE (32) +#define MASS_STORAGE_INTERFACE (0) + +#define APP_CONTROL_MAX_PKT_SIZE (64) +#define DEV_DESC_MAX_PACKET_SIZE (7) +#define DISK_FS_MAX_PACKET_SIZE (64) +#define DISK_HS_MAX_PACKET_SIZE (512) + +#define CFG_DESC_EP_IN_TYPE_OFFSET (21) +#define CFG_DESC_EP_IN_MAX_PACKET_SIZE_OFFSET (22) +#define CFG_DESC_EP_OUT_TYPE_OFFSET (28) +#define CFG_DESC_EP_OUT_MAX_PACKET_SIZE_OFFSET (29) + +#define TOTAL_LOGICAL_ADDRESS_BLOCKS (4096) +#define LENGTH_OF_EACH_LAB (512) + +#define DISK_IN_EP_NO 1 +#define DISK_OUT_EP_NO 2 + +#define DISK_IN_EP_TYPE 2 /* Bulk */ +#define DISK_OUT_EP_TYPE 2 /* Bulk */ + +typedef struct +{ + _usb_device_handle usbDevHandle; /* Must be first field */ + uint_32 devNo; + uint_8_ptr Send_Buffer_Unaligned; + + uint_8_ptr DevDesc; + uint_8_ptr DevQualifierDesc; + uint_8_ptr ConfigDesc; + uint_8_ptr other_speed_config; + uint_8_ptr ep1_buf; + uint_8_ptr epTemp_buf; + DISK_READ_CAPACITY* pReadCapacity; + CSW_STRUCT* pCSW; + uint_8_ptr MASS_STORAGE_DISK; + + SETUP_STRUCT local_setup_packet; + + volatile boolean TEST_ENABLED; + volatile boolean ENTER_TEST_MODE; + volatile uint_16 test_mode_index; + volatile uint_8 speed; + uint_16 logicalBlocks; + uint_32 hsMaxPktSize; + uint_32 fsMaxPktSize; + + uint_32 inEpType; + uint_32 outEpType; + + uint_32 inEpNo; + uint_32 outEpNo; + boolean CBW_PROCESSED; + boolean ZERO_TERMINATE; + +} USB_DISK_STRUCT; + +uint_32 diskHsMaxPktSize = DISK_HS_MAX_PACKET_SIZE; +uint_32 diskFsMaxPktSize = DISK_FS_MAX_PACKET_SIZE; + +uint_32 diskInEpType = DISK_IN_EP_TYPE; +uint_32 diskOutEpType = DISK_OUT_EP_TYPE; + +uint_32 diskInEpNo = DISK_IN_EP_NO; +uint_32 diskOutEpNo = DISK_OUT_EP_NO; + +static USB_DISK_STRUCT* usbDisksPtr[MAX_USB_DEVICES] = { NULL, NULL }; + +/************************************************************************** +DESCRIPTORS DESCRIPTORS DESCRIPTORS DESCRIPTORS DESCRIPTORS DESCRIPTORS +**************************************************************************/ + +#define DEVICE_DESCRIPTOR_SIZE 18 +static const uint_8 DevDescData[DEVICE_DESCRIPTOR_SIZE] = +{ + /* Length of DevDesc */ + DEVICE_DESCRIPTOR_SIZE, + /* "Device" Type of descriptor */ + 1, + /* BCD USB version */ + 0, 2, + /* Device Class is indicated in the interface descriptors */ + 0x00, + /* Device Subclass is indicated in the interface descriptors */ + 0x00, + /* Mass storage devices do not use class-specific protocols */ + 0x00, + /* Max packet size */ + APP_CONTROL_MAX_PKT_SIZE, + /* Vendor ID */ + USB_uint_16_low(0x1286), USB_uint_16_high(0x1286), + /* Product ID */ + USB_uint_16_low(0x1), USB_uint_16_high(0x1), + /* BCD Device version */ + USB_uint_16_low(0x0002), USB_uint_16_high(0x0002), + /* Manufacturer string index */ + 0x1, + /* Product string index */ + 0x2, + /* Serial number string index */ + 0x6, + /* Number of configurations available */ + 0x1 +}; + +/* USB 2.0 specific descriptor */ +#define DEVICE_QUALIFIER_DESCRIPTOR_SIZE 10 +static const uint_8 DevQualifierDescData[DEVICE_QUALIFIER_DESCRIPTOR_SIZE] = +{ + DEVICE_QUALIFIER_DESCRIPTOR_SIZE, /* bLength Length of this descriptor */ + 6, /* bDescType This is a DEVICE Qualifier descr */ + 0,2, /* bcdUSB USB revision 2.0 */ + 0, /* bDeviceClass */ + 0, /* bDeviceSubClass */ + 0, /* bDeviceProtocol */ + APP_CONTROL_MAX_PKT_SIZE, /* bMaxPacketSize0 */ + 0x01, /* bNumConfigurations */ + 0 +}; + +#define CONFIG_DESC_NUM_INTERFACES (4) +/* This must be counted manually and updated with the descriptor */ +/* 1*Config(9) + 1*Interface(9) + 2*Endpoint(7) = 32 bytes */ +#define CONFIG_DESC_SIZE (32) + +/************************************************************** +we declare the config desc as USB_Uncached because this descriptor +is updated on the fly for max packet size during enumeration. Making +it uncached ensures that main memory is updated whenever this +descriptor pointer is used. +**************************************************************/ +static const uint_8 ConfigDescData[CONFIG_DESC_SIZE] = +{ + /* Configuration Descriptor - always 9 bytes */ + 9, + /* "Configuration" type of descriptor */ + 2, + /* Total length of the Configuration descriptor */ + USB_uint_16_low(CONFIG_DESC_SIZE), + USB_uint_16_high(CONFIG_DESC_SIZE), + /* NumInterfaces */ + 1, + /* Configuration Value */ + 1, + /* Configuration Description String Index*/ + 4, + /* Attributes. Self-powered. */ + 0xc0, + /* Current draw from bus */ + 0, + /* Interface 0 Descriptor - always 9 bytes */ + 9, + /* "Interface" type of descriptor */ + 4, + /* Number of this interface */ + MASS_STORAGE_INTERFACE, + /* Alternate Setting */ + 0, + /* Number of endpoints on this interface */ + 2, + /* Interface Class */ + 0x08, + /* Interface Subclass: SCSI transparent command set */ + 0x06, + /* Interface Protocol: Bulk only protocol */ + 0x50, + /* Interface Description String Index */ + 0, + /* Endpoint 1 (Bulk In Endpoint), Interface 0 Descriptor - always 7 bytes*/ + 7, + /* "Endpoint" type of descriptor */ + 5, + /* + ** Endpoint address. The low nibble contains the endpoint number and the + ** high bit indicates TX(1) or RX(0). + */ + ((ARC_USB_SEND<<7) | DISK_IN_EP_NO) /*0x81*/, + /* Attributes. 0=Control 1=Isochronous 2=Bulk 3=Interrupt */ + DISK_IN_EP_TYPE, + /* Max Packet Size for this endpoint */ + USB_uint_16_low(DISK_FS_MAX_PACKET_SIZE), + USB_uint_16_high(DISK_FS_MAX_PACKET_SIZE), + /* Polling Interval (ms) */ + 0, + /* Endpoint 2 (Bulk Out Endpoint), Interface 0 Descriptor - always 7 bytes*/ + 7, + /* "Endpoint" type of descriptor */ + 5, + /* + ** Endpoint address. The low nibble contains the endpoint number and the + ** high bit indicates TX(1) or RX(0). + */ + ((ARC_USB_RECV<<7) | DISK_OUT_EP_NO), /*0x02*/ + /* Attributes. 0=Control 1=Isochronous 2=Bulk 3=Interrupt */ + DISK_OUT_EP_TYPE, + /* Max Packet Size for this endpoint */ + USB_uint_16_low(DISK_FS_MAX_PACKET_SIZE), + USB_uint_16_high(DISK_FS_MAX_PACKET_SIZE), + /* Polling Interval (ms) */ + 0 +}; + +#define OTHER_SPEED_CONFIG_DESC_SIZE CONFIG_DESC_SIZE +static const uint_8 other_speed_config_data[CONFIG_DESC_SIZE] = +{ + 9, /* bLength Length of this descriptor */ + 7, /* bDescType This is a Other speed config descr */ + USB_uint_16_low(OTHER_SPEED_CONFIG_DESC_SIZE), + USB_uint_16_high(OTHER_SPEED_CONFIG_DESC_SIZE), + 1, + 1, + 4, + 0xc0, + 0, + /* Interface 0 Descriptor - always 9 bytes */ + 9, + /* "Interface" type of descriptor */ + 4, + /* Number of this interface */ + MASS_STORAGE_INTERFACE, + /* Alternate Setting */ + 0, + /* Number of endpoints on this interface */ + 2, + /* Interface Class */ + 0x08, + /* Interface Subclass: SCSI transparent command set */ + 0x06, + /* Interface Protocol: Bulk only protocol */ + 0x50, + /* Interface Description String Index */ + 0, + /* Endpoint 1 (Bulk In Endpoint), Interface 0 Descriptor - always 7 bytes*/ + 7, + /* "Endpoint" type of descriptor */ + 5, + /* + ** Endpoint address. The low nibble contains the endpoint number and the + ** high bit indicates TX(1) or RX(0). + */ + ((ARC_USB_SEND<<7) | DISK_IN_EP_NO), /*0x81*/ + /* Attributes. 0=Control 1=Isochronous 2=Bulk 3=Interrupt */ + DISK_IN_EP_TYPE, + /* Max Packet Size for this endpoint */ + USB_uint_16_low(DISK_HS_MAX_PACKET_SIZE), + USB_uint_16_high(DISK_HS_MAX_PACKET_SIZE), + /* Polling Interval (ms) */ + 0, + /* Endpoint 2 (Bulk Out Endpoint), Interface 0 Descriptor - always 7 bytes*/ + 7, + /* "Endpoint" type of descriptor */ + 5, + /* + ** Endpoint address. The low nibble contains the endpoint number and the + ** high bit indicates TX(1) or RX(0). + */ + ((ARC_USB_RECV<<7) | DISK_OUT_EP_NO), /*0x02*/ + + /* Attributes. 0=Control 1=Isochronous 2=Bulk 3=Interrupt */ + DISK_OUT_EP_TYPE, + /* Max Packet Size for this endpoint */ + USB_uint_16_low(DISK_HS_MAX_PACKET_SIZE), + USB_uint_16_high(DISK_HS_MAX_PACKET_SIZE), + /* Polling Interval (ms) */ + 0 +}; + +static uint_8 USB_IF_ALT[4] = { 0, 0, 0, 0}; + +/* number of strings in the table not including 0 or n. */ +static const uint_8 USB_STR_NUM = 7; + +/* +** if the number of strings changes, look for USB_STR_0 everywhere and make +** the obvious changes. It should be found in 3 places. +*/ + +static uint_16 USB_STR_0[ 2] = {(0x300 + sizeof(USB_STR_0)),(0x0409)}; +static uint_16 USB_STR_1[26] = {(0x300 + sizeof(USB_STR_1)), + 'M','a','r','v','e','l','l',' ','S','e','m','i','c','o','n','d','u','c','t','o','r',' ','L','t','d'}; +static uint_16 USB_STR_2[28] = {(0x300 + sizeof(USB_STR_2)), + 'M','A','R','V','E','L','L',' ','M','a','s','s',' ','S','t','o','r','a','g','e',' ',\ + 'D','e','v','i','c','e'}; +static uint_16 USB_STR_3[ 5] = {(0x300 + sizeof(USB_STR_3)), + 'B','E','T','A'}; +static uint_16 USB_STR_4[ 4] = {(0x300 + sizeof(USB_STR_4)), + '#','0','2'}; +static uint_16 USB_STR_5[ 4] = {(0x300 + sizeof(USB_STR_5)), + '_','A','1'}; + /* Serial number has to be at least 12 bytes */ +static uint_16 USB_STR_6[ 13] = {(0x300 + sizeof(USB_STR_6)), + '0','0','0','0','0','0','0','0','0','0','0','1'}; +static uint_16 USB_STR_7[15] = {(0x300 + sizeof(USB_STR_7)), + 'Y','o','u','r',' ','n','a','m','e',' ','h','e','r','e'}; +static uint_16 USB_STR_n[17] = {(0x300 + sizeof(USB_STR_n)), + 'B','A','D',' ','S','T','R','I','N','G',' ','I','n','d','e','x'}; + +#define USB_STRING_ARRAY_SIZE 9 +static uint_8_ptr USB_STRING_DESC[USB_STRING_ARRAY_SIZE] = +{ + (uint_8_ptr)((pointer)USB_STR_0), + (uint_8_ptr)((pointer)USB_STR_1), + (uint_8_ptr)((pointer)USB_STR_2), + (uint_8_ptr)((pointer)USB_STR_3), + (uint_8_ptr)((pointer)USB_STR_4), + (uint_8_ptr)((pointer)USB_STR_5), + (uint_8_ptr)((pointer)USB_STR_6), + (uint_8_ptr)((pointer)USB_STR_7), + (uint_8_ptr)((pointer)USB_STR_n) +}; + +/***************************************************************** +MASS STORAGE SPECIFIC GLOBALS +*****************************************************************/ + +static const DISK_DEVICE_INFO device_information_data = +{ + 0, 0x80, 0, 0x01, 0x1F, + /* Reserved */ + {0, 0, 0}, + /* Vendor information: "MARVELL " */ + {0x4D, 0x41, 0x52, 0x56, 0x45, 0x4C, 0x4C, 0x20,}, + /* Product information: "Disk " */ + {0x44, 0x69, 0x73, 0x6B, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20}, + /* Product Revision level: "Demo" */ + {0x44, 0x65, 0x6D, 0x6F} +}; + +static const DISK_READ_CAPACITY read_capacity = +{ + /* Data for the capacity */ + { + 0x00, 0x00, USB_uint_16_high(TOTAL_LOGICAL_ADDRESS_BLOCKS-14), + USB_uint_16_low(TOTAL_LOGICAL_ADDRESS_BLOCKS-14) + }, + { + 0x00, 0x00, USB_uint_16_high(LENGTH_OF_EACH_LAB), + USB_uint_16_low(LENGTH_OF_EACH_LAB) + } +}; + +static const uint_8 BOOT_SECTOR_AREA[512] = +{ + /* Block 0 is the boot sector. Following is the data in the boot sector */ + /* 80x86 "short: jump instruction, indicating that the disk is formatted */ + 0xEB, + /* 8-bit displacement */ + 0x3C, + /* NOP OPCode */ + 0x90, + /* 8-bytes for OEM identification: "ARC 4.3 " */ + 0x41, 0x52, 0x43, 0x20, 0x34, 0x2E, 0x33, 0x20, + /* bytes/sector: 512 bytes (0x0200) */ + 0x00, 0x02, + /* Sectors/allocation unit */ + 0x01, + /* Reserved sectors: 0x0001 */ + 0x01, 0x00, + /* Number of File Allocation Tables (FATs): 2 */ + 0x02, + /* Number of root directory entries */ + 0x00, 0x02, + /* Total Small sectors in logical volume */ + USB_uint_16_low(TOTAL_LOGICAL_ADDRESS_BLOCKS), + USB_uint_16_high(TOTAL_LOGICAL_ADDRESS_BLOCKS), + /* Media descriptor byte: 0xF8: Fixed disk */ + 0xF8, + /* Sectors/FAT: 3 (Each FAT starts at a new sector) */ + 0x80, 0x00, + /* Sectors/track: 9 */ + 0x09, 0x00, + /* Number of heads */ + 0x02, 0x00, + /* Number of hidden sectors: 0 */ + 0x00, 0x00, 0x00, 0x00, + /* Total Large sectors in logical volume */ + 0x00, 0x00, 0x00, 0x00, + /* Physical drive number */ + 0x00, + /* Reserved */ + 0x00, + /* Extended boot signature record: 0x29 */ + 0x29, + /* 32-bit binary volume ID */ + 0x01, 0x02, 0x03, 0x04, + /* Volume label */ + 0x53, 0x54, 0x55, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + /* Reserved FAT-16*/ + 0x46, 0x41, 0x54, 0x31, 0x36, 0x00, 0x00, 0x00, + /* Bootstrap */ + 0x33, 0xC0, 0x8E, 0xD0, 0xBC, 0x00, 0x7C, 0xFC, 0xE8, 0x45, 0x00, + /* String: \r\nNon-System disk\r\nPress any key to reboot\r\n" */ + 0x0D, 0x0A, 0x4E, 0x6F, 0x6E, 0x2D, 0x53, 0x79, 0x73, 0x74, 0x65, + 0x6D, 0x20, 0x64, 0x69, 0x73, 0x6B, 0x0D, 0x0A, 0x50, 0x72, 0x65, + 0x73, 0x73, 0x20, 0x61, 0x6E, 0x79, 0x20, 0x6B, 0x65, 0x79, 0x20, + 0x74, 0x6F, 0x20, 0x72, 0x65, 0x62, 0x6F, 0x6F, 0x74, 0x0D, 0x0A, + 0x5E, 0xEB, 0x02, 0xCD, 0x10, 0xB4, 0x0E, 0xBB, 0x07, 0x00, 0x2E, + 0xAC, 0x84, 0xC0, 0x75, 0xF3, 0x98, 0xCD, 0x16, 0xCD, 0x19, 0xEB, + 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* Partition descriptors */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xAA +}; + + +static const uint_8 FAT16_SPECIAL_BYTES[3] = +{ + /* FAT ID: Same as Media descriptor */ + 0xF8, 0xFF, 0xFF +}; + + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9GetDescription +* Returned Value : None +* Comments : +* Chapter 9 GetDescription command +* The Device Request can ask for Device/Config/string/interface/endpoint +* descriptors (via wValue). We then post an IN response to return the +* requested descriptor. +* And then wait for the OUT which terminates the control transfer. +* +*END*--------------------------------------------------------------------*/ +static void ch9GetDescription + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + uint_32 max_pkt_size; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, "usbDisk %s: setup=%d, value=0x%x, length=%d\n", + __FUNCTION__, (int)setup, setup_ptr->VALUE, setup_ptr->LENGTH); + + if (setup) + { + /* Load the appropriate string depending on the descriptor requested.*/ + switch (setup_ptr->VALUE & 0xFF00) + { + case 0x0100: + _usb_device_send_data(handle, 0, pDiskCtrl->DevDesc, + MIN(setup_ptr->LENGTH, DEVICE_DESCRIPTOR_SIZE)); + break; + + case 0x0200: + /* Set the Max Packet Size in the config and other speed config */ + if(pDiskCtrl->speed == ARC_USB_SPEED_HIGH) + { + max_pkt_size = pDiskCtrl->hsMaxPktSize; + } + else + { + max_pkt_size = pDiskCtrl->fsMaxPktSize; + } /* Endif */ + + *(pDiskCtrl->ConfigDesc + CFG_DESC_EP_IN_TYPE_OFFSET) = (uint_8)pDiskCtrl->inEpType; + + *(pDiskCtrl->ConfigDesc + CFG_DESC_EP_IN_MAX_PACKET_SIZE_OFFSET) = + USB_uint_16_low(max_pkt_size); + *(pDiskCtrl->ConfigDesc + CFG_DESC_EP_IN_MAX_PACKET_SIZE_OFFSET+1) = + USB_uint_16_high(max_pkt_size); + + *(pDiskCtrl->ConfigDesc + CFG_DESC_EP_OUT_TYPE_OFFSET) = (uint_8)pDiskCtrl->outEpType; + + *(pDiskCtrl->ConfigDesc + CFG_DESC_EP_OUT_MAX_PACKET_SIZE_OFFSET) = + USB_uint_16_low(max_pkt_size); + *(pDiskCtrl->ConfigDesc + CFG_DESC_EP_OUT_MAX_PACKET_SIZE_OFFSET+1) = + USB_uint_16_high(max_pkt_size); + + _usb_device_send_data(handle, 0, pDiskCtrl->ConfigDesc, + MIN(setup_ptr->LENGTH, CONFIG_DESC_SIZE)); + break; + + case 0x0300: + if ((setup_ptr->VALUE & 0x00FF) > USB_STR_NUM) { + _usb_device_send_data(handle, 0, USB_STRING_DESC[USB_STR_NUM+1], + MIN(setup_ptr->LENGTH, USB_STRING_DESC[USB_STR_NUM+1][0])); + } + else + { + _usb_device_send_data(handle, 0, USB_STRING_DESC[setup_ptr->VALUE & 0x00FF], + MIN(setup_ptr->LENGTH, USB_STRING_DESC[setup_ptr->VALUE & 0x00FF][0])); + } /* Endif */ + break; + + case 0x600: + _usb_device_send_data(handle, 0, (uint_8_ptr)pDiskCtrl->DevQualifierDesc, + MIN(setup_ptr->LENGTH, DEVICE_QUALIFIER_DESCRIPTOR_SIZE)); + break; + + case 0x700: + if(pDiskCtrl->speed == ARC_USB_SPEED_HIGH) + { + max_pkt_size = pDiskCtrl->fsMaxPktSize; + } + else + { + max_pkt_size = pDiskCtrl->hsMaxPktSize; + } /* Endif */ + + *(pDiskCtrl->other_speed_config + CFG_DESC_EP_IN_TYPE_OFFSET) = (uint_8)pDiskCtrl->inEpType; + + *(pDiskCtrl->other_speed_config + CFG_DESC_EP_IN_MAX_PACKET_SIZE_OFFSET) = + USB_uint_16_low(max_pkt_size); + *(pDiskCtrl->other_speed_config + CFG_DESC_EP_IN_MAX_PACKET_SIZE_OFFSET+1) = + USB_uint_16_high(max_pkt_size); + + *(pDiskCtrl->other_speed_config + CFG_DESC_EP_OUT_TYPE_OFFSET) = (uint_8)pDiskCtrl->outEpType; + + *(pDiskCtrl->other_speed_config + CFG_DESC_EP_OUT_MAX_PACKET_SIZE_OFFSET) = + USB_uint_16_low(max_pkt_size); + *(pDiskCtrl->other_speed_config + CFG_DESC_EP_OUT_MAX_PACKET_SIZE_OFFSET+1) = + USB_uint_16_high(max_pkt_size); + + _usb_device_send_data(handle, 0, (uint_8_ptr)pDiskCtrl->other_speed_config, + MIN(setup_ptr->LENGTH, OTHER_SPEED_CONFIG_DESC_SIZE)); + + break; + + default: + USB_printf("usbDisk_%d, %s: Unexpected VALUE=0x%04x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, setup_ptr->VALUE); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endswitch */ + /* status phase */ + _usb_device_recv_data(handle, 0, NULL, 0); + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9SetDescription +* Returned Value : None +* Comments : +* Chapter 9 SetDescription command +* +*END*--------------------------------------------------------------------*/ +static void ch9SetDescription + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + USB_printf("usbDisk_%d, %s: setup=%d\n", + _usb_device_get_dev_num(handle), __FUNCTION__, (int)setup); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9GetConfig +* Returned Value : None +* Comments : +* Chapter 9 GetConfig command +* +*END*--------------------------------------------------------------------*/ +static void ch9GetConfig + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + uint_16 current_config; + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, "usbDisk %s: setup=%d\n", __FUNCTION__, (int)setup); + + /* Return the currently selected configuration */ + if (setup) + { + _usb_device_get_status(handle, ARC_USB_STATUS_CURRENT_CONFIG, + ¤t_config); + *pDiskCtrl->epTemp_buf = (current_config & 0xFF); + _usb_device_send_data(handle, 0, pDiskCtrl->epTemp_buf, sizeof(uint_8)); + /* status phase */ + _usb_device_recv_data(handle, 0, NULL, 0); + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9SetConfig +* Returned Value : None +* Comments : +* Chapter 9 SetConfig command +* +*END*--------------------------------------------------------------------*/ +static void ch9SetConfig + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + uint_16 usb_state; + uint_32 max_pkt_size; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, "usbDisk %s: setup=%d, value=0x%x\n", + __FUNCTION__, (int)setup, setup_ptr->VALUE); + + if (setup) + { + if ((setup_ptr->VALUE & 0x00FF) > 1) + { + /* generate stall */ + USB_printf("usbDisk_%d, %s: Wrong VALUE=0x%04x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, setup_ptr->VALUE); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endif */ + + /* 0 indicates return to unconfigured state */ + if ((setup_ptr->VALUE & 0x00FF) == 0) + { + _usb_device_get_status(handle, ARC_USB_STATUS_DEVICE_STATE, &usb_state); + if( (usb_state == ARC_USB_STATE_CONFIG) || + (usb_state == ARC_USB_STATE_ADDRESS) ) + { + /* clear the currently selected config value */ + _usb_device_set_status(handle, ARC_USB_STATUS_CURRENT_CONFIG, 0); + _usb_device_set_status(handle, ARC_USB_STATUS_DEVICE_STATE, + ARC_USB_STATE_ADDRESS); + /* status phase */ + _usb_device_send_data(handle, 0, 0, 0); + } + else + { + USB_printf("usbDisk_%d, %s: Wrong usb_state=%d\n", + _usb_device_get_dev_num(handle), __FUNCTION__, usb_state); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + } /* Endif */ + return; + } /* Endif */ + + /* + ** If the configuration value (setup_ptr->VALUE & 0x00FF) differs + ** from the current configuration value, then endpoints must be + ** reconfigured to match the new device configuration + */ + _usb_device_get_status(handle, ARC_USB_STATUS_CURRENT_CONFIG, + &usb_state); + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, "usbDisk: Set configuration: old=%d, new=%d\n", + usb_state, setup_ptr->VALUE & 0x00FF); + + if (usb_state != (setup_ptr->VALUE & 0x00FF)) + { + /* Reconfigure endpoints here */ + switch (setup_ptr->VALUE & 0x00FF) + { + default: + break; + } /* Endswitch */ + + _usb_device_set_status(handle, ARC_USB_STATUS_CURRENT_CONFIG, + setup_ptr->VALUE & 0x00FF); + } /* Endif */ + + if (pDiskCtrl->speed == ARC_USB_SPEED_HIGH) + { + max_pkt_size = pDiskCtrl->hsMaxPktSize; + } + else + { + max_pkt_size = pDiskCtrl->fsMaxPktSize; + } /* Endif */ + + _usb_device_init_endpoint(handle, pDiskCtrl->outEpNo, max_pkt_size, + ARC_USB_RECV, ARC_USB_BULK_ENDPOINT, ARC_USB_DEVICE_DONT_ZERO_TERMINATE); + _usb_device_init_endpoint(handle, pDiskCtrl->inEpNo, max_pkt_size, + ARC_USB_SEND, ARC_USB_BULK_ENDPOINT, ARC_USB_DEVICE_DONT_ZERO_TERMINATE); + + if (_usb_device_get_transfer_status(handle, pDiskCtrl->outEpNo, ARC_USB_RECV) == USB_OK) + { + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, 31); + } /* Endif */ + + pDiskCtrl->TEST_ENABLED = TRUE; + + _usb_device_set_status(handle, ARC_USB_STATUS_DEVICE_STATE, + ARC_USB_STATE_CONFIG); + /* status phase */ + _usb_device_send_data(handle, 0, 0, 0); + + USB_printf("USB %s speed disk: config = %d\n", + (pDiskCtrl->speed == ARC_USB_SPEED_HIGH) ? "High" : "Full", + setup_ptr->VALUE & 0x00FF); + + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9GetInterface +* Returned Value : None +* Comments : +* Chapter 9 GetInterface command +* +*END*--------------------------------------------------------------------*/ +static void ch9GetInterface + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + uint_16 usb_state; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, "usbDisk %s: setup=%d\n", __FUNCTION__, (int)setup); + + _usb_device_get_status(handle, ARC_USB_STATUS_DEVICE_STATE, &usb_state); + if (usb_state != ARC_USB_STATE_CONFIG) + { + USB_printf("usbDisk_%d, %s: Wrong usb_state=%d\n", + _usb_device_get_dev_num(handle), __FUNCTION__, usb_state); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endif */ + + if (setup) + { + _usb_device_send_data(handle, 0, &USB_IF_ALT[setup_ptr->INDEX & 0x00FF], + MIN(setup_ptr->LENGTH, sizeof(uint_8))); + /* status phase */ + _usb_device_recv_data(handle, 0, NULL, 0); + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9SetInterface +* Returned Value : None +* Comments : +* Chapter 9 SetInterface command +* +*END*--------------------------------------------------------------------*/ +static void ch9SetInterface + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, "usbDisk %s: setup=%d\n", __FUNCTION__, (int)setup); + + if (setup) + { + if (setup_ptr->REQUESTTYPE != 0x01) + { + USB_printf("usbDisk_%d, %s: Wrong REQUESTTYPE=0x%02x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, + setup_ptr->REQUESTTYPE); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endif */ + + /* + ** If the alternate value (setup_ptr->VALUE & 0x00FF) differs + ** from the current alternate value for the specified interface, + ** then endpoints must be reconfigured to match the new alternate + */ + if (USB_IF_ALT[setup_ptr->INDEX & 0x00FF] + != (setup_ptr->VALUE & 0x00FF)) + { + USB_IF_ALT[setup_ptr->INDEX & 0x00FF] = (setup_ptr->VALUE & 0x00FF); + /* Reconfigure endpoints here. */ + + } /* Endif */ + + /* status phase */ + _usb_device_send_data(handle, 0, 0, 0); + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9SynchFrame +* Returned Value : +* Comments : +* Chapter 9 SynchFrame command +* +*END*--------------------------------------------------------------------*/ +static void ch9SynchFrame + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + + uint_16 usbStatus; + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, "usbDisk %s: setup=%d\n", + __FUNCTION__, (int)setup); + + if (setup) + { + if (setup_ptr->REQUESTTYPE != (REQ_RECIP_ENDPOINT | REQ_TYPE_STANDARD | REQ_DIR_OUT) ) + { + USB_printf("usbDisk_%d, %s: Wrong REQUESTTYPE=0x%02x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, + setup_ptr->REQUESTTYPE); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endif */ + + if ((setup_ptr->INDEX & 0x00FF) >= + pDiskCtrl->ConfigDesc[CONFIG_DESC_NUM_INTERFACES]) + { + USB_printf("usbDisk_%d, %s: Wrong INDEX=0x%02x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, setup_ptr->INDEX); + _usb_device_stall_endpoint(handle, 0, ARC_USB_RECV); + return; + } /* Endif */ + + _usb_device_get_status(handle, ARC_USB_STATUS_SOF_COUNT, &usbStatus); + pDiskCtrl->epTemp_buf[0] = USB_uint_16_low(usbStatus); + pDiskCtrl->epTemp_buf[1] = USB_uint_16_high(usbStatus); + _usb_device_send_data(handle, 0, pDiskCtrl->epTemp_buf, MIN(setup_ptr->LENGTH, sizeof(uint_16))); + /* status phase */ + _usb_device_recv_data(handle, 0, NULL, 0); + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9Class +* Returned Value : +* Comments : +* Chapter 9 Class specific request +* See section 9.4.11 (page 195) of the USB 1.1 Specification. +* +*END*--------------------------------------------------------------------*/ +static void ch9Class + ( + _usb_device_handle handle, + boolean setup, + uint_8 direction, + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_CLASS, + "usbDisk %s: setup=%d, request=0x%x, value=%d, index=%d, size=%d\n", + __FUNCTION__, (int)setup, setup_ptr->REQUEST, + setup_ptr->VALUE, setup_ptr->INDEX, setup_ptr->LENGTH); + + if (setup) + { + switch (setup_ptr->REQUEST) + { + case 0xFF: + /* Bulk-Only Mass Storage Reset: Ready the device for the next + ** CBW from the host + */ + if ((setup_ptr->VALUE != 0) || + (setup_ptr->INDEX != MASS_STORAGE_INTERFACE) || + (setup_ptr->LENGTH != 0)) + { + USB_printf("usbDisk_%d, %s: Wrong Setup: VALUE=%d, INDEX=%d, LENGTH=%d\n", + _usb_device_get_dev_num(handle), __FUNCTION__, setup_ptr->VALUE, + setup_ptr->INDEX, setup_ptr->LENGTH); + + _usb_device_stall_endpoint(handle, 0, 0); + } + else + { /* Body */ + pDiskCtrl->CBW_PROCESSED = FALSE; + pDiskCtrl->ZERO_TERMINATE = FALSE; + _usb_device_cancel_transfer(handle, pDiskCtrl->outEpNo, ARC_USB_RECV); + _usb_device_cancel_transfer(handle, pDiskCtrl->inEpNo, ARC_USB_SEND); + + /* unstall bulk endpoint */ + _usb_device_unstall_endpoint(handle, pDiskCtrl->outEpNo, ARC_USB_RECV); + _usb_device_unstall_endpoint(handle, pDiskCtrl->inEpNo, ARC_USB_SEND); + + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, 31); + /* send zero packet to control pipe */ + _usb_device_send_data(handle, 0, NULL, 0); + } /* Endbody */ + break; + + case 0xFE: + /* For Get Max LUN use any of these responses*/ + if (setup_ptr->LENGTH == 0) + { /* Body */ + + USB_printf("usbDisk_%d, %s: Wrong Length: LENGTH=%d\n", + _usb_device_get_dev_num(handle), __FUNCTION__, setup_ptr->LENGTH); + + _usb_device_stall_endpoint(handle, 0, 0); + } + else + { + if ((setup_ptr->VALUE != 0) || + (setup_ptr->INDEX != MASS_STORAGE_INTERFACE) || + (setup_ptr->LENGTH != 1)) + { /* Body */ + USB_printf("usbDisk_%d, %s: Wrong Setup: VALUE=%d, INDEX=%d, LENGTH=%d\n", + _usb_device_get_dev_num(handle), __FUNCTION__, setup_ptr->VALUE, + setup_ptr->INDEX, setup_ptr->LENGTH); + _usb_device_stall_endpoint(handle, 0, 0); + } + else + { /* Body */ + /* Send Max LUN = 0 to the the control pipe */ + *pDiskCtrl->epTemp_buf = 0; + _usb_device_send_data(handle, 0, pDiskCtrl->epTemp_buf, 1); + /* status phase */ + _usb_device_recv_data(handle, 0, 0, 0); + } /* Endbody */ + } + break; + + default : + USB_printf("usbDisk_%d, %s: Wrong REQUEST=0x%02x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, setup_ptr->REQUEST); + _usb_device_stall_endpoint(handle, 0, 0); + return; + } /* EndSwitch */ + } + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : service_ep0 +* Returned Value : None +* Comments : +* Called upon a completed endpoint 0 (USB 1.1 Chapter 9) transfer +* +*END*--------------------------------------------------------------------*/ +static void service_ep0 + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] request type as registered */ + uint_8 type, + + /* [IN] Is it a setup packet? */ + boolean setup, + + /* [IN] Direction of the transfer. Is it transmit? */ + uint_8 direction, + + /* [IN] Pointer to the data buffer */ + uint_8_ptr buffer, + + /* [IN] Length of the transfer */ + uint_32 length, + + /* [IN] Error, if any */ + uint_8 error + + ) +{ /* Body */ + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + SETUP_STRUCT* pSetupPacket = &pDiskCtrl->local_setup_packet; + + if (setup) + { + _usb_device_read_setup_data(handle, 0, (uint_8_ptr)pSetupPacket); + pSetupPacket->VALUE = USB_16BIT_LE(pSetupPacket->VALUE); + pSetupPacket->INDEX = USB_16BIT_LE(pSetupPacket->INDEX); + pSetupPacket->LENGTH = USB_16BIT_LE(pSetupPacket->LENGTH); + } + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_EP0, + "disk %s: setup=%s, dir=%s, pBuf=0x%x, length=%d, reqType=0x%x, req=0x%x\n", + __FUNCTION__, (setup ? "YES" : "NO"), + (direction == ARC_USB_RECV) ? "RECV" : "SEND", + (unsigned)buffer, (int)length, pSetupPacket->REQUESTTYPE, + pSetupPacket->REQUEST); + + switch (pSetupPacket->REQUESTTYPE & REQ_TYPE_MASK) + { + case REQ_TYPE_STANDARD: + switch (pSetupPacket->REQUEST) + { + case REQ_GET_STATUS: + mvUsbCh9GetStatus(handle, setup, pSetupPacket); + break; + + case REQ_CLEAR_FEATURE: + mvUsbCh9ClearFeature(handle, setup, pSetupPacket); + break; + + case REQ_SET_FEATURE: + mvUsbCh9SetFeature(handle, setup, pSetupPacket); + break; + + case REQ_SET_ADDRESS: + mvUsbCh9SetAddress(handle, setup, pSetupPacket); + break; + + case REQ_GET_DESCRIPTOR: + ch9GetDescription(handle, setup, pSetupPacket); + break; + + case REQ_SET_DESCRIPTOR: + ch9SetDescription(handle, setup, pSetupPacket); + break; + + case REQ_GET_CONFIGURATION: + ch9GetConfig(handle, setup, pSetupPacket); + break; + + case REQ_SET_CONFIGURATION: + ch9SetConfig(handle, setup, pSetupPacket); + break; + + case REQ_GET_INTERFACE: + ch9GetInterface(handle, setup, pSetupPacket); + break; + + case REQ_SET_INTERFACE: + ch9SetInterface(handle, setup, pSetupPacket); + break; + + case REQ_SYNCH_FRAME: + ch9SynchFrame(handle, setup, pSetupPacket); + break; + + default: + USB_printf("usbDisk_%d, %s: Wrong REQUEST = 0x%02x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, pSetupPacket->REQUEST); + _usb_device_stall_endpoint(handle, 0, 0); + break; + + } /* Endswitch */ + + break; + + case REQ_TYPE_CLASS: + /* class specific request */ + ch9Class(handle, setup, direction, pSetupPacket); + return; + + case REQ_TYPE_VENDOR: + /* vendor specific request can be handled here*/ + USB_printf("usbDisk_%d, %s: Vendor REQUESTTYPE (%d) not supported\n", + _usb_device_get_dev_num(handle), __FUNCTION__, REQ_TYPE_VENDOR); + + _usb_device_stall_endpoint(handle, 0, 0); + break; + + default: + USB_printf("usbDisk_%d, %s: Unexpected REQUESTTYPE = 0x%x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, + pSetupPacket->REQUESTTYPE); + + _usb_device_stall_endpoint(handle, 0, 0); + break; + + } /* Endswitch */ + + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _process_inquiry_command +* Returned Value : None +* Comments : +* Process a Mass storage class Inquiry command +* +*END*--------------------------------------------------------------------*/ +void _process_inquiry_command + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] Endpoint number */ + uint_8 ep_num, + + /* [IN] Pointer to the data buffer */ + CBW_STRUCT_PTR cbw_ptr + ) +{ /* Body */ + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + if (cbw_ptr->DCBWDATALENGTH) + { + if (cbw_ptr->BMCBWFLAGS & USB_CBW_DIRECTION_BIT) + { + /* Send the device information */ + _usb_device_send_data(handle, pDiskCtrl->inEpNo, (uint_8_ptr)&device_information_data, 36); + } /* Endif */ + } /* Endif */ + + /* The actual length will never exceed the DCBWDATALENGTH */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = USB_32BIT_LE(cbw_ptr->DCBWDATALENGTH - 36); + pDiskCtrl->pCSW->BCSWSTATUS = 0; + +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _process_unsupported_command +* Returned Value : None +* Comments : +* Responds appropriately to unsupported commands +* +*END*--------------------------------------------------------------------*/ +void _process_unsupported_command + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] Endpoint number */ + uint_8 ep_num, + + /* [IN] Pointer to the data buffer */ + CBW_STRUCT_PTR cbw_ptr + ) +{ /* Body */ + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_DISK, + "disk unsupported command: BMCBWFLAGS = 0x%02x\n", cbw_ptr->BMCBWFLAGS); + + /* The actual length will never exceed the DCBWDATALENGTH */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = 0; + pDiskCtrl->pCSW->BCSWSTATUS = 0; + + if (cbw_ptr->BMCBWFLAGS & USB_CBW_DIRECTION_BIT) + { + /* Send a zero-length packet */ + _usb_device_send_data(handle, pDiskCtrl->inEpNo, (uint_8_ptr)NULL, 0); + } + else + { + pDiskCtrl->CBW_PROCESSED = FALSE; + /* Send the command status information */ + _usb_device_send_data(handle, pDiskCtrl->inEpNo, (uint_8_ptr)pDiskCtrl->pCSW, 13); + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, 31); + } /* Endif */ + +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _process_report_capacity +* Returned Value : None +* Comments : +* Reports the media capacity as a response to READ CAPACITY Command. +* +*END*--------------------------------------------------------------------*/ +void _process_report_capacity + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] Endpoint number */ + uint_8 ep_num, + + /* [IN] Pointer to the data buffer */ + CBW_STRUCT_PTR cbw_ptr + ) +{ /* Body */ + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_DISK_CAP, + "disk read_capacity: BMCBWFLAGS = 0x%02x\n", cbw_ptr->BMCBWFLAGS); + + if (cbw_ptr->BMCBWFLAGS & USB_CBW_DIRECTION_BIT) + { + /* Send a zero-length packet */ + _usb_device_send_data(handle, pDiskCtrl->inEpNo, (uint_8_ptr)pDiskCtrl->pReadCapacity, 8); + + } /* Endif */ + + /* The actual length will never exceed the DCBWDATALENGTH */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = 0; + pDiskCtrl->pCSW->BCSWSTATUS = 0; + +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _process_read_command +* Returned Value : None +* Comments : +* Sends data as a response to READ Command. +* +*END*--------------------------------------------------------------------*/ +void _process_read_command + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] Endpoint number */ + uint_8 ep_num, + + /* [IN] Pointer to the data buffer */ + CBW_STRUCT_PTR cbw_ptr + ) +{ /* Body */ + uint_32 index1 = 0, index2 = 0; + uint_32 max_pkt_size, byteSize; + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + if (cbw_ptr->BMCBWFLAGS & USB_CBW_DIRECTION_BIT) + { + /* Send a zero-length packet */ + index1 = ((uint_32)cbw_ptr->CBWCB[4] << 8); + index1 |= cbw_ptr->CBWCB[5]; + index2 = ((uint_32)cbw_ptr->CBWCB[7] << 8); + index2 |= (uint_32)cbw_ptr->CBWCB[8]; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_DISK_READ, + "disk read: FLAGS=0x%02x, LENGTH=0x%x, index1=0x%x, index2=0x%x\n", + cbw_ptr->BMCBWFLAGS, cbw_ptr->DCBWDATALENGTH, index1, index2); + + if(cbw_ptr->CBWCB[0] != 0x3E) + { + byteSize = index2 * LENGTH_OF_EACH_LAB; + } + else + { + byteSize = index2; + index2 = (USB_MEM_ALIGN(byteSize, LENGTH_OF_EACH_LAB) / LENGTH_OF_EACH_LAB); + } + + /* Check index validities */ + if( (index1 + index2) >= pDiskCtrl->logicalBlocks) + { + USB_printf("USB disk read: invalid indexes - addr=%d, size=%d\n", + index1, index2); + pDiskCtrl->pCSW->DCSWDATARESIDUE = USB_32BIT_LE(cbw_ptr->DCBWDATALENGTH); + pDiskCtrl->pCSW->BCSWSTATUS = 1; + /* Send zero size packet */ + _usb_device_send_data(handle, pDiskCtrl->inEpNo, (uint_8_ptr)NULL, 0); + return; + } + + if (cbw_ptr->DCBWDATALENGTH == 0) + { /* Body */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = 0; + pDiskCtrl->pCSW->BCSWSTATUS = 2; + pDiskCtrl->CBW_PROCESSED = FALSE; + /* Send the command status information */ + _usb_device_send_data(handle, pDiskCtrl->inEpNo, (uint_8_ptr)pDiskCtrl->pCSW, 13); + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, 31); + return; + } + else + { /* Body */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = 0; + pDiskCtrl->pCSW->BCSWSTATUS = 0; + if (byteSize > cbw_ptr->DCBWDATALENGTH) + { /* Body */ + byteSize = cbw_ptr->DCBWDATALENGTH; + pDiskCtrl->pCSW->DCSWDATARESIDUE = USB_32BIT_LE(cbw_ptr->DCBWDATALENGTH); + pDiskCtrl->pCSW->BCSWSTATUS = 2; + } + else + { + if (byteSize < cbw_ptr->DCBWDATALENGTH) + { /* Body */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = USB_32BIT_LE(cbw_ptr->DCBWDATALENGTH - index2); + if (byteSize > 0) + { /* Body */ + if (pDiskCtrl->speed == ARC_USB_SPEED_HIGH) + { + max_pkt_size = pDiskCtrl->hsMaxPktSize; + } + else + { + max_pkt_size = pDiskCtrl->fsMaxPktSize; + } + + if( (byteSize % max_pkt_size) == 0) + { /* Body */ + /* Need send a zero terminate packet to host */ + pDiskCtrl->ZERO_TERMINATE = TRUE; + } /* Endbody */ + } /* Endbody */ + } /* Endbody */ + } + + _usb_device_send_data(handle, pDiskCtrl->inEpNo, + pDiskCtrl->MASS_STORAGE_DISK + (index1*LENGTH_OF_EACH_LAB), byteSize); + } /* Endbody */ + } + else + { /* Body */ + USB_printf("disk read incorrect: FLAGS=0x%02x, LENGTH=0x%x\n", + cbw_ptr->BMCBWFLAGS, cbw_ptr->DCBWDATALENGTH); + + /* Incorrect but valid CBW */ + if (cbw_ptr->DCBWDATALENGTH > BUFFERSIZE) + byteSize = BUFFERSIZE; + else + byteSize = cbw_ptr->DCBWDATALENGTH; + + pDiskCtrl->pCSW->DCSWDATARESIDUE = USB_32BIT_LE(cbw_ptr->DCBWDATALENGTH); + pDiskCtrl->pCSW->BCSWSTATUS = 2; + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, index2); + } /* Endbody */ +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _process_write_command +* Returned Value : None +* Comments : +* Sends data as a response to WRITE Command. +* +*END*--------------------------------------------------------------------*/ +void _process_write_command + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] Endpoint number */ + uint_8 ep_num, + + /* [IN] Pointer to the data buffer */ + CBW_STRUCT_PTR cbw_ptr + ) +{ /* Body */ + uint_32 index1 = 0, index2 = 0; + uint_32 byteSize; + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + if (!(cbw_ptr->BMCBWFLAGS & USB_CBW_DIRECTION_BIT)) + { + index1 = ((uint_32)cbw_ptr->CBWCB[4] << 8); + index1 |= cbw_ptr->CBWCB[5]; + index2 = ((uint_32)cbw_ptr->CBWCB[7] << 8); + index2 |= (uint_32)cbw_ptr->CBWCB[8]; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_DISK_WRITE, + "disk write: FLAGS=0x%02x, LENGTH=0x%x, index1=0x%x, index2=0x%x\n", + cbw_ptr->BMCBWFLAGS, cbw_ptr->DCBWDATALENGTH, index1, index2); + + if(cbw_ptr->CBWCB[0] != 0x3F) + { + byteSize = index2 * LENGTH_OF_EACH_LAB; + } + else + { + byteSize = index2; + index2 = (USB_MEM_ALIGN(byteSize, LENGTH_OF_EACH_LAB) / LENGTH_OF_EACH_LAB); + } + + /* Check index validities */ + if( (index1 + index2) >= pDiskCtrl->logicalBlocks) + { + USB_printf("USB disk write: invalid indexes - addr=%d, size=%d\n", + index1, index2); + pDiskCtrl->pCSW->DCSWDATARESIDUE = 0; + pDiskCtrl->pCSW->BCSWSTATUS = 1; + pDiskCtrl->CBW_PROCESSED = FALSE; + /* Send the command status information */ + _usb_device_send_data(handle, pDiskCtrl->inEpNo, (uint_8_ptr)pDiskCtrl->pCSW, 13); + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, 31); + return; + } + + if (cbw_ptr->DCBWDATALENGTH == 0) + { /* Body */ + /* Zero transfer length */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = 0; + pDiskCtrl->pCSW->BCSWSTATUS = 2; + pDiskCtrl->CBW_PROCESSED = FALSE; + + /* Send the command status information */ + _usb_device_send_data(handle, pDiskCtrl->inEpNo, (uint_8_ptr)pDiskCtrl->pCSW, 13); + + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, 31); + return; + } + else + { /* Body */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = 0; + pDiskCtrl->pCSW->BCSWSTATUS = 0; + + if (byteSize < cbw_ptr->DCBWDATALENGTH) + { /* Body */ + /* The actual length will never exceed the DCBWDATALENGTH */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = USB_32BIT_LE(cbw_ptr->DCBWDATALENGTH - byteSize); + byteSize = cbw_ptr->DCBWDATALENGTH; + } + else if (byteSize > cbw_ptr->DCBWDATALENGTH) + { /* Body */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = USB_32BIT_LE(cbw_ptr->DCBWDATALENGTH); + pDiskCtrl->pCSW->BCSWSTATUS = 2; + byteSize = cbw_ptr->DCBWDATALENGTH; + } /* Endbody */ + + if (_usb_device_get_transfer_status(handle, pDiskCtrl->outEpNo, ARC_USB_RECV) != USB_OK) + { + _usb_device_cancel_transfer(handle, ep_num, ARC_USB_RECV); + } /* Endif */ + + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, + pDiskCtrl->MASS_STORAGE_DISK + (index1*LENGTH_OF_EACH_LAB), byteSize); + } + } + else + { /* Body */ + USB_printf("disk write incorrect: FLAGS=0x%02x, LENGTH=0x%x\n", + cbw_ptr->BMCBWFLAGS, cbw_ptr->DCBWDATALENGTH); + + /* Incorrect but valid CBW */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = USB_32BIT_LE(cbw_ptr->DCBWDATALENGTH); + pDiskCtrl->pCSW->BCSWSTATUS = 2; + _usb_device_send_data(handle, pDiskCtrl->inEpNo, 0, 0); + return; + } /* Endbody */ + +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _process_test_unit_ready +* Returned Value : None +* Comments : +* Responds appropriately to unit ready query +* +*END*--------------------------------------------------------------------*/ +void _process_test_unit_ready + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] Endpoint number */ + uint_8 ep_num, + + /* [IN] Pointer to the data buffer */ + CBW_STRUCT_PTR cbw_ptr + ) +{ /* Body */ + uint_32 bufSize; + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + if ((cbw_ptr->BMCBWFLAGS & USB_CBW_DIRECTION_BIT) || + (cbw_ptr->DCBWDATALENGTH == 0)) + { + /* The actual length will never exceed the DCBWDATALENGTH */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = 0; + pDiskCtrl->pCSW->BCSWSTATUS = 0; + + pDiskCtrl->CBW_PROCESSED = FALSE; + + /* Send the command status information */ + _usb_device_send_data(handle, pDiskCtrl->inEpNo, (uint_8_ptr)pDiskCtrl->pCSW, 13); + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, 31); + } + else + { /* Body */ + /* Incorrect but valid CBW */ + if (cbw_ptr->DCBWDATALENGTH > BUFFERSIZE) + bufSize = BUFFERSIZE; + else + bufSize = cbw_ptr->DCBWDATALENGTH; + + pDiskCtrl->pCSW->DCSWDATARESIDUE = USB_32BIT_LE(cbw_ptr->DCBWDATALENGTH); + pDiskCtrl->pCSW->BCSWSTATUS = 1; + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, bufSize); + } /* Endbody */ + +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _process_prevent_allow_medium_removal +* Returned Value : None +* Comments : +* Responds appropriately to unit ready query +* +*END*--------------------------------------------------------------------*/ +void _process_prevent_allow_medium_removal + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] Endpoint number */ + uint_8 ep_num, + + /* [IN] Pointer to the data buffer */ + CBW_STRUCT_PTR cbw_ptr + ) +{ /* Body */ + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + /* The actual length will never exceed the DCBWDATALENGTH */ + pDiskCtrl->pCSW->DCSWDATARESIDUE = 0; + pDiskCtrl->pCSW->BCSWSTATUS = 0; + + pDiskCtrl->CBW_PROCESSED = FALSE; + + /* Send the command status information */ + _usb_device_send_data(handle, pDiskCtrl->inEpNo, (uint_8_ptr)pDiskCtrl->pCSW, 13); + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, 31); + +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : _process_mass_storage_command +* Returned Value : None +* Comments : +* Process a Mass storage class command +* +*END*--------------------------------------------------------------------*/ +void _process_mass_storage_command + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] Endpoint number */ + uint_8 ep_num, + + /* [IN] Pointer to the data buffer */ + CBW_STRUCT_PTR cbw_ptr + ) +{ /* Body */ + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_DISK, + "disk command: CBWCB[0]=0x%02x, FLAGS=0x%02x, LENGTH=0x%x\n", + cbw_ptr->CBWCB[0], cbw_ptr->BMCBWFLAGS, cbw_ptr->DCBWDATALENGTH); + + switch (cbw_ptr->CBWCB[0]) + { + case 0x00: /* Request the device to report if it is ready */ + _process_test_unit_ready(handle, ep_num, cbw_ptr); + break; + + case 0x12: /* Inquity command. Get device information */ + _process_inquiry_command(handle, ep_num, cbw_ptr); + break; + + case 0x1A: + _process_unsupported_command(handle, ep_num, cbw_ptr); + break; + + case 0x1E: /* Prevent or allow the removal of media from a removable media device */ + _process_prevent_allow_medium_removal(handle, ep_num, cbw_ptr); + break; + + case 0x23: /* Read Format Capacities. Report current media capacity and + ** formattable capacities supported by media + */ + /* We bahave like already installed medium. No need to send any data */ + _process_unsupported_command(handle, ep_num, cbw_ptr); + break; + + case 0x25: /* Report current media capacity */ + _process_report_capacity(handle, ep_num, cbw_ptr); + break; + + case 0x28: /* Read (10) Transfer binary data from media to the host */ + case 0x3E: + _process_read_command(handle, ep_num, cbw_ptr); + break; + + case 0x2A: /* Write (10) Transfer binary data from the host to the media */ + case 0x3F: + _process_write_command(handle, ep_num, cbw_ptr); + break; + + case 0x01: /* Position a head of the drive to zero track */ + case 0x03: /* Transfer status sense data to the host */ + case 0x04: /* Format unformatted media */ + case 0x1B: /* Request a request a removable-media device to load or + ** unload its media + */ + case 0x1D: /* Perform a hard reset and execute diagnostics */ + case 0x2B: /* Seek the device to a specified address */ + case 0x2E: /* Transfer binary data from the host to the media and + ** verify data + */ + case 0x2F: /* Verify data on the media */ + case 0x55: /* Allow the host to set parameters in a peripheral */ + case 0x5A: /* Report parameters to the host */ + case 0xA8: /* Read (12) Transfer binary data from the media to the host */ + case 0xAA: /* Write (12) Transfer binary data from the host to the + ** media + */ + default: + _process_unsupported_command(handle, ep_num, cbw_ptr); + break; + } /* Endswitch */ + +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : service_ep1 +* Returned Value : None +* Comments : +* Called upon a completed endpoint 1 (USB 1.1 Chapter 9) transfer +* +*END*--------------------------------------------------------------------*/ +static void service_ep1 + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] Service type as registered */ + uint_8 type, + + /* [IN] Is it a setup packet? */ + boolean setup, + + /* [IN] Direction of the transfer. Is it transmit? */ + uint_8 direction, + + /* [IN] Pointer to the data buffer */ + uint_8_ptr buffer, + + /* [IN] Length of the transfer */ + uint_32 length, + + /* [IN] Error, if any */ + uint_8 error + + ) +{ /* Body */ + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + CBW_STRUCT_PTR cbw_ptr = (CBW_STRUCT_PTR)((pointer)buffer); + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_EP1, + "disk %s: ep=%d, dir=%s, pBuf=0x%x, length=%d, error=0x%x\n", + __FUNCTION__, type, (direction == ARC_USB_RECV) ? "RECV" : "SEND", + (unsigned)buffer, (int)length, error); + + if ((!direction) && (!pDiskCtrl->CBW_PROCESSED) && (length == 31) && + (cbw_ptr->DCBWSIGNATURE == USB_32BIT_LE(USB_DCBWSIGNATURE))) + { + /* A valid CBW was received */ + pDiskCtrl->pCSW->DCSWSIGNATURE = USB_32BIT_LE(USB_DCSWSIGNATURE); + pDiskCtrl->pCSW->DCSWTAG = cbw_ptr->DCBWTAG; + pDiskCtrl->CBW_PROCESSED = TRUE; + + /* Swap 32 bit fields if neccessary */ + cbw_ptr->DCBWDATALENGTH = USB_32BIT_LE(cbw_ptr->DCBWDATALENGTH); + + /* Process the command */ + _process_mass_storage_command(handle, type, cbw_ptr); + } + else + { + /* If a CBW was processed then send the status information and + ** queue another cbw receive request, else just queue another CBW receive + ** request if we received an invalid CBW + */ + if (pDiskCtrl->CBW_PROCESSED) + { + int i; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_DISK_DATA, + "disk %s: ep=%d, dir=%s, pBuf=0x%x, length=%d, error=0x%x\n", + __FUNCTION__, type, (direction == ARC_USB_RECV) ? "RECV" : "SEND", + (unsigned)buffer, (int)length, error); + + for(i=0; i<64; i++) + { + if( (i % 16) == 0) + { + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_DISK_DUMP, "\n0x%08x: ", &buffer[i]); + } + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_DISK_DUMP, "%02x ", buffer[i]); + if( (i % 3) == 0) + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_DISK_DUMP, " "); + } + + if (pDiskCtrl->ZERO_TERMINATE) + { /* Body */ + pDiskCtrl->ZERO_TERMINATE = FALSE; + _usb_device_send_data(handle, pDiskCtrl->inEpNo, 0, 0); + } + else + { /* Body */ + pDiskCtrl->CBW_PROCESSED = FALSE; + + /* Send the command status information */ + _usb_device_send_data(handle, pDiskCtrl->inEpNo, (uint_8_ptr)pDiskCtrl->pCSW, 13); + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, 31); + } + } + else + { + if (!direction) + { + USB_printf("usbDisk_%d, %s: Wrong direction = %d\n", + _usb_device_get_dev_num(handle), __FUNCTION__, direction); + _usb_device_stall_endpoint(handle, pDiskCtrl->outEpNo, ARC_USB_RECV); + _usb_device_stall_endpoint(handle, pDiskCtrl->inEpNo, ARC_USB_SEND); + + /* Invalid CBW received. Queue another receive buffer */ + _usb_device_recv_data(handle, pDiskCtrl->outEpNo, pDiskCtrl->ep1_buf, 31); + } + } /* Endif */ + } /* Endif */ + + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : service_speed +* Returned Value : None +* Comments : +* Called upon a speed detection event. +* +*END*--------------------------------------------------------------------*/ +static void service_speed + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] request type as registered */ + uint_8 type, + + /* [IN] Unused */ + boolean setup, + + /* [IN] Unused */ + uint_8 direction, + + /* [IN] Unused */ + uint_8_ptr buffer, + + /* [IN] Unused */ + uint_32 length, + + /* [IN] Error, if any */ + uint_8 error + + ) +{ /* EndBody */ + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SPEED, "disk %s: speed = %d\n", __FUNCTION__, (unsigned)length); + + pDiskCtrl->speed = length; + return; +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : reset_ep0 +* Returned Value : None +* Comments : +* Called upon a bus reset event. Initialises the control endpoint. +* +*END*--------------------------------------------------------------------*/ +static void reset_ep0 + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] request type as registered */ + uint_8 type, + + /* [IN] Unused */ + boolean setup, + + /* [IN] Unused */ + uint_8 direction, + + /* [IN] Unused */ + uint_8_ptr buffer, + + /* [IN] Unused */ + uint_32 length, + + /* [IN] Error, if any */ + uint_8 error + + ) +{ /* Body */ + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_RESET, "disk-%d %s: pDiskCtrl=%p, handle=%p\n", + devNo, __FUNCTION__, pDiskCtrl, handle); + + /* on a reset always ensure all transfers are cancelled on control EP*/ + _usb_device_cancel_transfer(handle, 0, ARC_USB_RECV); + _usb_device_cancel_transfer(handle, 0, ARC_USB_SEND); + + _usb_device_start(handle); + /* Initialize the endpoint 0 in both directions */ + _usb_device_init_endpoint(handle, 0, pDiskCtrl->DevDesc[DEV_DESC_MAX_PACKET_SIZE], + ARC_USB_RECV, ARC_USB_CONTROL_ENDPOINT, 0); + _usb_device_init_endpoint(handle, 0, pDiskCtrl->DevDesc[DEV_DESC_MAX_PACKET_SIZE], + ARC_USB_SEND, ARC_USB_CONTROL_ENDPOINT, 0); + + + if (pDiskCtrl->TEST_ENABLED) + { + int out_ep_count=0, in_ep_count=0; + + while(_usb_device_get_transfer_status(handle, pDiskCtrl->outEpNo, ARC_USB_RECV) != + ARC_USB_STATUS_IDLE) + { + out_ep_count++; + _usb_device_cancel_transfer(handle, pDiskCtrl->outEpNo, ARC_USB_RECV); + } + while(_usb_device_get_transfer_status(handle, pDiskCtrl->inEpNo, ARC_USB_SEND) != + ARC_USB_STATUS_IDLE) + { + in_ep_count++; + _usb_device_cancel_transfer(handle, pDiskCtrl->inEpNo, ARC_USB_SEND); + } + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_RESET, "disk %s: out_ep_count=%d, in_ep_count=%d\n", + __FUNCTION__, out_ep_count, in_ep_count); + } /* Endif */ + + pDiskCtrl->TEST_ENABLED = FALSE; + + return; +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : usbDiskLoad - main task +* Inputs: +* int diskSize - size of created disk in KBytes +* Returned Value : None +* Comments : +* First function called. Initialises the USB and registers Chapter 9 +* callback functions. +* +*END*--------------------------------------------------------------------*/ +_usb_device_handle usbDiskLoad(int devNo, int diskSize) +{ /* Body */ + _usb_device_handle handle; + USB_DISK_STRUCT* pDiskCtrl; + uint_8_ptr Send_Buffer_aligned; + uint_8 error; + uint_32 send_data_buffer_size=0; + uint_8_ptr temp; + int lockKey, i, j; + static boolean isFirst = TRUE; + + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_INIT, "%s: devNo=%d, diskSize=%d\n", + __FUNCTION__, devNo, diskSize); + + if(devNo >= MAX_USB_DEVICES) + { + USB_printf("USB disk: devNo=%d too large\n", devNo); + return NULL; + } + + /*lock interrupts */ + lockKey = USB_lock(); + + if(isFirst) + { + for(i=0; ilogicalBlocks = TOTAL_LOGICAL_ADDRESS_BLOCKS; + else + pDiskCtrl->logicalBlocks = (diskSize*1024)/LENGTH_OF_EACH_LAB; + + if(pDiskCtrl->logicalBlocks < 16) + { + USB_printf("USB disk size (%d) is too small. Minimum is 8 Kbytes\n", + diskSize); + USB_unlock(lockKey); + return NULL; + } + + pDiskCtrl->devNo = devNo; + pDiskCtrl->hsMaxPktSize = diskHsMaxPktSize; + pDiskCtrl->fsMaxPktSize = diskFsMaxPktSize; + + pDiskCtrl->inEpType = diskInEpType; + pDiskCtrl->outEpType = diskOutEpType; + + pDiskCtrl->inEpNo = diskInEpNo; + pDiskCtrl->outEpNo = diskOutEpNo; + + /* Initialize the USB interface */ + error = _usb_device_init(devNo, &handle); + if (error != USB_OK) + { + USB_unlock(lockKey); + USB_printf("\nUSB Initialization failed. Error: %x", error); + return NULL; + } /* Endif */ + + /* Self Power, Remote wakeup disable */ + _usb_device_set_status(handle, ARC_USB_STATUS_DEVICE, (1 << DEVICE_SELF_POWERED)); + + error = _usb_device_register_service(handle, ARC_USB_SERVICE_EP0, service_ep0); + if (error != USB_OK) + { + USB_unlock(lockKey); + USB_printf("\nUSB Service Registration failed. Error: %x", error); + return NULL; + } /* Endif */ + + error = _usb_device_register_service(handle, ARC_USB_SERVICE_BUS_RESET, reset_ep0); + if (error != USB_OK) + { + USB_unlock(lockKey); + USB_printf("\nUSB Service Registration failed. Error: %x", error); + return NULL; + } /* Endif */ + + error = _usb_device_register_service(handle, ARC_USB_SERVICE_SPEED_DETECTION, + service_speed); + if (error != USB_OK) + { + USB_unlock(lockKey); + USB_printf("\nUSB Service Registration failed. Error: %x", error); + return NULL; + } /* Endif */ + + error = _usb_device_register_service(handle, pDiskCtrl->outEpNo, service_ep1); + if (error != USB_OK) + { + USB_unlock(lockKey); + USB_printf("\nUSB Service Registration failed. Error: %x", error); + return NULL; + } /* Endif */ + + if(pDiskCtrl->outEpNo != pDiskCtrl->inEpNo) + { + error = _usb_device_register_service(handle, pDiskCtrl->inEpNo, service_ep1); + if (error != USB_OK) + { + USB_unlock(lockKey); + USB_printf("\nUSB Service Registration failed. Error: %x", error); + return NULL; + } /* Endif */ + } + + /************************************************************************** + Best way to handle the Data cache is to allocate a large buffer that is + cache aligned and keep all data inside it. Flush the line of the cache + that you have changed. In this program, we have static data such as + descriptors which never changes. Such data can be kept in this buffer + and flushed only once. Note that you can reduce the size of this buffer + by aligning the addresses in a different way. + ***************************************************************************/ + send_data_buffer_size = (DEVICE_DESCRIPTOR_SIZE + PSP_CACHE_LINE_SIZE) + + (CONFIG_DESC_SIZE + PSP_CACHE_LINE_SIZE) + + (DEVICE_QUALIFIER_DESCRIPTOR_SIZE + PSP_CACHE_LINE_SIZE) + + (OTHER_SPEED_CONFIG_DESC_SIZE + PSP_CACHE_LINE_SIZE) + + (BUFFERSIZE + PSP_CACHE_LINE_SIZE) + + (EP_TEMP_BUFFERSIZE + PSP_CACHE_LINE_SIZE) + + (sizeof(DISK_READ_CAPACITY) + PSP_CACHE_LINE_SIZE) + + (sizeof(CSW_STRUCT) + PSP_CACHE_LINE_SIZE) + + (pDiskCtrl->logicalBlocks*LENGTH_OF_EACH_LAB + PSP_CACHE_LINE_SIZE); + + pDiskCtrl->Send_Buffer_Unaligned = (uint_8_ptr) USB_memalloc(send_data_buffer_size); + if (pDiskCtrl->Send_Buffer_Unaligned == NULL) + { + USB_unlock(lockKey); + USB_printf("diskLoad: Buffer allocation of %d bytes is failed\n", + (unsigned)send_data_buffer_size); + return NULL; + } + + Send_Buffer_aligned = (uint_8_ptr) USB_CACHE_ALIGN((uint_32)pDiskCtrl->Send_Buffer_Unaligned); + /* keep a temporary copy of the aligned address */ + temp = Send_Buffer_aligned; + + /************************************************************************** + Assign pointers to different buffers from it and copy data inside. + ***************************************************************************/ + pDiskCtrl->DevDesc = (uint_8_ptr) Send_Buffer_aligned; + USB_memcopy(DevDescData, pDiskCtrl->DevDesc, DEVICE_DESCRIPTOR_SIZE); + Send_Buffer_aligned += ((DEVICE_DESCRIPTOR_SIZE/PSP_CACHE_LINE_SIZE) + 1)* PSP_CACHE_LINE_SIZE; + + pDiskCtrl->ConfigDesc = (uint_8_ptr) Send_Buffer_aligned; + USB_memcopy(ConfigDescData, pDiskCtrl->ConfigDesc, CONFIG_DESC_SIZE); + Send_Buffer_aligned += ((CONFIG_DESC_SIZE/PSP_CACHE_LINE_SIZE) + 1)* PSP_CACHE_LINE_SIZE; + + pDiskCtrl->DevQualifierDesc = (uint_8_ptr) Send_Buffer_aligned; + USB_memcopy(DevQualifierDescData, pDiskCtrl->DevQualifierDesc, DEVICE_QUALIFIER_DESCRIPTOR_SIZE); + Send_Buffer_aligned += ((DEVICE_QUALIFIER_DESCRIPTOR_SIZE/PSP_CACHE_LINE_SIZE) + 1) * PSP_CACHE_LINE_SIZE; + + pDiskCtrl->other_speed_config = (uint_8_ptr) Send_Buffer_aligned; + USB_memcopy(other_speed_config_data, pDiskCtrl->other_speed_config, OTHER_SPEED_CONFIG_DESC_SIZE); + Send_Buffer_aligned += ((OTHER_SPEED_CONFIG_DESC_SIZE/PSP_CACHE_LINE_SIZE) + 1)* PSP_CACHE_LINE_SIZE; + + /*buffer to receive data from Bulk OUT */ + pDiskCtrl->ep1_buf = (uint_8_ptr) Send_Buffer_aligned; + USB_memzero(pDiskCtrl->ep1_buf, BUFFERSIZE); + Send_Buffer_aligned += ((BUFFERSIZE/PSP_CACHE_LINE_SIZE) + 1)* PSP_CACHE_LINE_SIZE; + + /*buffer for control endpoint to send data */ + pDiskCtrl->epTemp_buf = (uint_8_ptr) Send_Buffer_aligned; + USB_memzero(pDiskCtrl->epTemp_buf, EP_TEMP_BUFFERSIZE); + + Send_Buffer_aligned += ((EP_TEMP_BUFFERSIZE/PSP_CACHE_LINE_SIZE) + 1)* PSP_CACHE_LINE_SIZE; + + /* Buffer for read Capacity message */ + pDiskCtrl->pReadCapacity = (DISK_READ_CAPACITY*)Send_Buffer_aligned; + USB_memcopy((void*)&read_capacity, pDiskCtrl->pReadCapacity, sizeof(DISK_READ_CAPACITY)); + + /* Update read_capacity */ + pDiskCtrl->pReadCapacity->LAST_LOGICAL_BLOCK_ADDRESS[2] = + USB_uint_16_high(pDiskCtrl->logicalBlocks-14); + pDiskCtrl->pReadCapacity->LAST_LOGICAL_BLOCK_ADDRESS[3] = + USB_uint_16_low(pDiskCtrl->logicalBlocks-14); + + Send_Buffer_aligned += ((sizeof(DISK_READ_CAPACITY)/PSP_CACHE_LINE_SIZE) + 1) * PSP_CACHE_LINE_SIZE; + + /* Buffer for CSW message */ + pDiskCtrl->pCSW = (CSW_STRUCT*)Send_Buffer_aligned; + USB_memzero(pDiskCtrl->pCSW , sizeof(CSW_STRUCT)); + + Send_Buffer_aligned += ((sizeof(CSW_STRUCT)/PSP_CACHE_LINE_SIZE) + 1) * PSP_CACHE_LINE_SIZE; + + /*buffer for storage disk */ + pDiskCtrl->MASS_STORAGE_DISK = (uint_8_ptr)Send_Buffer_aligned; + + USB_printf("usbDisk-%d: pDiskCtrl=%p, %d bytes allocated addr=0x%x\n", + devNo, pDiskCtrl, (unsigned)send_data_buffer_size, + (unsigned)pDiskCtrl->Send_Buffer_Unaligned); + USB_printf("usbDisk-%d: DevDesc=0x%x, ConfigDesc=0x%x, QualifierDesc=0x%x, otherSpeedDesc=0x%x\n", + devNo, (unsigned)pDiskCtrl->DevDesc, (unsigned)pDiskCtrl->ConfigDesc, + (unsigned)pDiskCtrl->DevQualifierDesc, (unsigned)pDiskCtrl->other_speed_config); + USB_printf("usbDisk-%d: ep1_buf=0x%x, epTemp_buf=0x%x, MASS_STORAGE_DISK=0x%x\n", + devNo, (unsigned)pDiskCtrl->ep1_buf, (unsigned)pDiskCtrl->epTemp_buf, + (unsigned)pDiskCtrl->MASS_STORAGE_DISK); + + USB_memzero(pDiskCtrl->MASS_STORAGE_DISK, (pDiskCtrl->logicalBlocks*LENGTH_OF_EACH_LAB)); + + /* Format the "disk" */ + USB_memcopy(BOOT_SECTOR_AREA, pDiskCtrl->MASS_STORAGE_DISK, 512); + + /* Update BOOT Sector "Total Small sectors" field */ + pDiskCtrl->MASS_STORAGE_DISK[19] = USB_uint_16_low(pDiskCtrl->logicalBlocks); + pDiskCtrl->MASS_STORAGE_DISK[20] = USB_uint_16_high(pDiskCtrl->logicalBlocks); + + USB_memcopy((void *)FAT16_SPECIAL_BYTES, pDiskCtrl->MASS_STORAGE_DISK + 512, 3); + USB_memcopy((void *)FAT16_SPECIAL_BYTES, pDiskCtrl->MASS_STORAGE_DISK + 512*4, 3); + + /************************************************************************** + Flush the cache to ensure main memory is updated. + ***************************************************************************/ + USB_dcache_flush(temp, send_data_buffer_size); + + pDiskCtrl->usbDevHandle = handle; + usbDisksPtr[devNo] = pDiskCtrl; + + USB_unlock(lockKey); + + USB_printf("USB Disk is READY: diskSize=%d KBytes, blockSize=%d Bytes, numBlocks=%d\n", + diskSize, LENGTH_OF_EACH_LAB, pDiskCtrl->logicalBlocks); + + return pDiskCtrl->usbDevHandle; +} /* Endbody */ + +void usbDiskUnload(_usb_device_handle handle) +{ + int lockKey; + int devNo = _usb_device_get_dev_num(handle); + USB_DISK_STRUCT* pDiskCtrl = usbDisksPtr[devNo]; + + if(pDiskCtrl == NULL) + { + USB_printf("USB disk #%d: Disk is not loaded\n", pDiskCtrl->devNo); + return; + } + /*lock interrupts */ + lockKey = USB_lock(); + + /* ensure all transfers are cancelled */ + _usb_device_cancel_transfer(handle, pDiskCtrl->outEpNo, ARC_USB_RECV); + _usb_device_cancel_transfer(handle, pDiskCtrl->inEpNo, ARC_USB_SEND); + + /* Stop Endpoints */ + _usb_device_deinit_endpoint(handle, pDiskCtrl->outEpNo, ARC_USB_RECV); + _usb_device_deinit_endpoint(handle, pDiskCtrl->inEpNo, ARC_USB_SEND); + + _usb_device_deinit_endpoint(handle, 0, ARC_USB_RECV); + _usb_device_deinit_endpoint(handle, 0, ARC_USB_SEND); + + _usb_device_stop(handle); + + /* Deregister all services */ + _usb_device_unregister_service(handle, ARC_USB_SERVICE_EP0); + _usb_device_unregister_service(handle, ARC_USB_SERVICE_BUS_RESET); + _usb_device_unregister_service(handle, ARC_USB_SERVICE_SPEED_DETECTION); + _usb_device_unregister_service(handle, pDiskCtrl->outEpNo); + if(pDiskCtrl->outEpNo != pDiskCtrl->inEpNo) + { + _usb_device_unregister_service(handle, pDiskCtrl->inEpNo); + } + + _usb_device_shutdown(handle); + + /* Free memory allocated for Disk device */ + if(pDiskCtrl->Send_Buffer_Unaligned != NULL) + { + USB_memfree(pDiskCtrl->Send_Buffer_Unaligned); + } + + /* Free Control structure */ + USB_memfree(pDiskCtrl); + usbDisksPtr[devNo] = NULL; + + USB_unlock(lockKey); +} + +/* EOF */ + diff --git a/board/mv_feroceon/mv_hal/usb/examples/disk.h b/board/mv_feroceon/mv_hal/usb/examples/disk.h new file mode 100644 index 0000000..d01dc4e --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/examples/disk.h @@ -0,0 +1,86 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +#ifndef __disk_h__ +#define __disk_h__ + +#define USB_DCBWSIGNATURE (0x43425355) +#define USB_DCSWSIGNATURE (0x53425355) +#define USB_CBW_DIRECTION_BIT (0x80) + +/* USB Command Block Wrapper */ +typedef struct cbw_struct { + uint_32 DCBWSIGNATURE; + uint_32 DCBWTAG; + uint_32 DCBWDATALENGTH; + uint_8 BMCBWFLAGS; + /* 4 MSBs bits reserved */ + uint_8 BCBWCBLUN; + /* 3 MSB reserved */ + uint_8 BCBWCBLENGTH; + uint_8 CBWCB[16]; +} CBW_STRUCT, _PTR_ CBW_STRUCT_PTR; + +/* USB Command Status Wrapper */ +typedef struct csw_struct { + uint_32 DCSWSIGNATURE; + uint_32 DCSWTAG; + uint_32 DCSWDATARESIDUE; + uint_8 BCSWSTATUS; +} CSW_STRUCT, _PTR_ CSW_STRUCT_PTR; + +/* USB Mass storage Inquiry Command */ +typedef struct mass_storage_inquiry { + uint_8 OPCODE; + uint_8 LUN; + uint_8 PAGE_CODE; + uint_8 RESERVED1; + uint_8 ALLOCATION_LENGTH; + uint_8 RESERVED2[7]; +} DISK_INQUIRY, _PTR_ DISK_INQUIRY_PTR; + +/* USB Mass storage READ CAPACITY Data */ +typedef struct mass_storage_read_capacity { + uint_8 LAST_LOGICAL_BLOCK_ADDRESS[4]; + uint_8 BLOCK_LENGTH_IN_BYTES[4]; +} DISK_READ_CAPACITY, _PTR_ DISK_READ_CAPACITY_PTR; + +/* USB Mass storage Device information */ +typedef struct mass_storage_device_info { + uint_8 PERIPHERAL_DEVICE_TYPE; /* Bits 0-4. All other bits reserved */ + uint_8 RMB; /* Bit 7. All other bits reserved */ + uint_8 ANSI_ECMA_ISO_VERSION; /* ANSI: bits 0-2, ECMA: bits 3-5, + ** ISO: bits 6-7 + */ + uint_8 RESPONSE_DATA_FORMAT; /* bits 0-3. All other bits reserved */ + uint_8 ADDITIONAL_LENGTH; /* For UFI device: always set to 0x1F */ + uint_8 RESERVED1[3]; + uint_8 VENDOR_INFORMATION[8]; + uint_8 PRODUCT_ID[16]; + uint_8 PRODUCT_REVISION_LEVEL[4]; +} DISK_DEVICE_INFO, _PTR_ DISK_DEVICE_INFO_PTR; + + +extern _usb_device_handle usbDiskLoad(int devNo, int diskSize); +extern void usbDiskUnload(_usb_device_handle handle); + +#endif /* __disk_h__ */ + +/* EOF */ diff --git a/board/mv_feroceon/mv_hal/usb/examples/mouse.c b/board/mv_feroceon/mv_hal/usb/examples/mouse.c new file mode 100644 index 0000000..fdcdc42 --- /dev/null +++ b/board/mv_feroceon/mv_hal/usb/examples/mouse.c @@ -0,0 +1,1708 @@ +/******************************************************************************* + +This software file (the "File") is distributed by Marvell International Ltd. +or its affiliate(s) under the terms of the GNU General Public License Version 2, +June 1991 (the "License"). You may use, redistribute and/or modify this File +in accordance with the terms and conditions of the License, a copy of which +is available along with the File in the license.txt file or by writing to the +Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +or on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +(C) Copyright 2004 - 2007 Marvell Semiconductor Israel Ltd. All Rights Reserved. +(C) Copyright 1999 - 2004 Chipidea Microelectronica, S.A. All Rights Reserved. + +*******************************************************************************/ + +/************************************************************************** +Include the USB stack header files. +**************************************************************************/ +#include "usb/api/mvUsbDefs.h" +#include "usb/api/mvUsbDebug.h" +#include "usb/api/mvUsbCh9.h" +#include "usb/api/mvUsbDevApi.h" + +#include "usb/examples/mouse.h" + +/************************************************************************** +global variables and some defines for device. +**************************************************************************/ + +#define CONTROL_MAX_PACKET_SIZE (64) +#define INTERRUPT_MAX_PACKET_SIZE (0x0008) +#define DEV_DESC_MAX_PACKET_SIZE (7) +#define INTERRUPT_EP (1) +#define FRAME_INTERVAL (15) + +/************************************************************************** +Include the OS and BSP dependent files that define IO functions and +basic types. You may like to change these files for your board and RTOS +**************************************************************************/ + +int frame_interval = FRAME_INTERVAL; +int mouseCntr = 0; +int mouseDelay = 2; + +static volatile boolean TEST_ENABLED = FALSE; +static volatile boolean USB_SUSPENDED = FALSE; + +#define EP1_RECV_BUFFER_SIZE 10 +static uint_8_ptr hid_test_rep_data; +static uint_8_ptr hid_test_rep_data_unaligned; + +/******************************** +Buffers for sending data to stack +********************************/ +#define EP0_SEND_BUFFER_SIZE 200 +static uint_8_ptr Send_Buffer_Unaligned; +static uint_8_ptr Send_Buffer_aligned; + +static uint_8 data_to_send; +static uint_16 sof_count; +static SETUP_STRUCT local_setup_packet; + + +/************************************************************************* +Device descriptors are always 18 bytes + +Offset| Field | Value | Description +------|--------------------|-------|-------------------- + 0 | bLength | 0x12 |The size of this + | | |descriptor is 18 bytes +------|--------------------|-------|-------------------- + 1 | bDescriptorType | 0x01 |DEVICE Descriptor Type +------|--------------------|-------|-------------------- + 2 | bcdUSB | 0x0100|Device compliant to + | | |the USB + | | |specification + | | |version 1.00 +------|--------------------|-------|-------------------- + 4 | bDeviceClass | 0x00 |Each interface + | | |specifies its own + | | |class information +------|--------------------|-------|-------------------- + 5 | bDeviceSubClass | 0x00 |Each interface + | | |specifies its own + | | |subclass information +------|--------------------|-------|-------------------- + 6 | bDeviceProtocol | 0x00 |No protocols on the + | | |device basis +------|--------------------|-------|-------------------- + 7 | bMaxPacketSize0 | 0x08 |Maximum packet size + | | |for endpoint zero is 8 +------|--------------------|-------|-------------------- + 8 | idVendor | 0x0261|Vendor ID is 609: + | | +------|--------------------|-------|-------------------- + 10 | idProduct | 0x4D03|The Product ID is 0x4D03 +------|--------------------|-------|-------------------- + 12 | bcdDevice | 0x0441|The device release + | | |number is 4.41 +------|--------------------|-------|-------------------- + 14 | iManufacturer | 0x00 |The device doesn't + | | |have the string + | | |descriptor + | | |describing the manufacturer +------|--------------------|-------|-------------------- + 15 | iProduct | 0x00 |The device doesn't + | | |have the string + | | |descriptor + | | |describing the product +------|--------------------|-------|-------------------- + 16 | iSerialNumber | 0x00 | +------|--------------------|-------|-------------------- + 17 | bNumConfigurations | 0x01 | +------|--------------------|-------|-------------------- +*************************************************************************/ +#define DEVICE_DESCRIPTOR_SIZE 18 +static uint_8_ptr DevDesc; +static uint_8 DevDescData[DEVICE_DESCRIPTOR_SIZE] = +{ + DEVICE_DESCRIPTOR_SIZE, + 0x01, + 0x0,2, + + 0x00, + 0x00, + 0x00, + CONTROL_MAX_PACKET_SIZE, + /* Vendor ID = MARVELL */ + USB_uint_16_low(0x1286), USB_uint_16_high(0x1286), + /* Product ID */ + USB_uint_16_low(0x1), USB_uint_16_high(0x1), + /* BCD Device version */ + USB_uint_16_low(0x0002), USB_uint_16_high(0x0002), + + 0x01, /* iManufacturer */ + 0x02, /* iProduct */ + 0x00, /* iSerialNumber */ + 0x01 /* bNumConfigurations */ + +}; + +/* USB 2.0 specific descriptor */ +#define DEVICE_QUALIFIER_DESCRIPTOR_SIZE 10 +static uint_8_ptr DevQualifierDesc; +static uint_8 DevQualifierDescData[DEVICE_QUALIFIER_DESCRIPTOR_SIZE] = +{ + DEVICE_QUALIFIER_DESCRIPTOR_SIZE, /* bLength Length of this descriptor */ + 6, /* bDescType This is a DEVICE Qualifier descr */ + 0,2, /* bcdUSB USB revision 2.0 */ + 0, /* bDeviceClass */ + 0, /* bDeviceSubClass */ + 0, /* bDeviceProtocol */ + CONTROL_MAX_PACKET_SIZE, /* bMaxPacketSize0 */ + 0x01, /* bNumConfigurations */ + 0 +}; + + +/******************************************************************* + CONFIG DESCRIPTOR + +Data stage (34 bytes) : +------------------------------------ + + CONFIGURATION Descriptor + ------------------------ +Offset| Field | Value | Description +------|---------------------|-------|-------------------- + 0 | bLength | 0x09 |The size of this + | | |descriptor is 9 bytes +------|---------------------|-------|-------------------- + 1 | bDescriptorType | 0x02 |CONFIGURATION + | | |Descriptor Type +------|---------------------|-------|-------------------- + 2 | wTotalLength | 0x0022|The total length of + | | |data for this + | | |configuration is 34. + | | |This includes the + | | |combined length of + | | |all the descriptors returned +------|---------------------|-------|-------------------- + 4 | bNumInterfaces | 0x01 |This configuration + | | |supports 1 interfaces +------|---------------------|-------|-------------------- + 5 | bConfigurationValue | 0x01 |The value 1 should + | | |be used to select + | | |this configuration +------|---------------------|-------|-------------------- + 6 | iConfiguration | 0x00 |The device doesn't + | | |have the string + | | |descriptor + | | |describing this configuration +------|---------------------|-------|-------------------- + 7 | bmAttributes | 0x80 |Configuration characteristics : + | | |Bit 7: Reserved (set to one) 1 + | | |Bit 6: Self-powered 0 + | | |Bit 5: Remote Wakeup 1 +------|---------------------|-------|-------------------- + 8 | MaxPower | 0x32 |Maximum power + | | |consumption of the + | | |device in this + | | |configuration is 100 mA +------|---------------------|-------|-------------------- + + INTERFACE Descriptor + -------------------- +Offset| Field | Value | Description +------|--------------------|-------|-------------------- + 0 | bLength | 0x09 |The size of this + | | |descriptor is 9 bytes +------|--------------------|-------|-------------------- + 1 | bDescriptorType | 0x04 |INTERFACE Descriptor Type +------|--------------------|-------|-------------------- + 2 | bInterfaceNumber | 0x00 |The number of this + | | |interface is 0 +------|--------------------|-------|-------------------- + 3 | bAlternateSetting | 0x00 |The value used to + | | |select alternate + | | |setting for this + | | |interface is 0 +------|--------------------|-------|-------------------- + 4 | bNumEndpoints | 0x01 |The number of + | | |endpoints used by + | | |this interface is 1 + | | |(excluding endpoint zero) +------|--------------------|-------|-------------------- + 5 | bInterfaceClass | 0x03 |The interface + | | |implements HID class +------|--------------------|-------|-------------------- + 6 | bInterfaceSubClass | 0x01 |The subclass code is 0x01 +------|--------------------|-------|-------------------- + 7 | bInterfaceProtocol | 0x02 |The protocol code is 0x02 +------|--------------------|-------|-------------------- + 8 | iInterface | 0x00 |The device doesn't + | | |have the string + | | |descriptor + | | |describing this interface +------|--------------------|-------|-------------------- + + HID Descriptor + -------------- +Offset| Field | Value | Description +------|-------------------|-------|-------------------- + 0 | bLength | 0x09 |The size of this + | | |descriptor is 9 bytes +------|-------------------|-------|-------------------- + 1 | bDescriptorType | 0x21 |HID Descriptor Type +------|-------------------|-------|-------------------- + 2 | bcdHID | 0x0100|Device compliant to + | | |the HID + | | |specification + | | |version 1.00 +------|-------------------|-------|-------------------- + 4 | bCountryCode | 0x00 |The country code is 0x00 +------|-------------------|-------|-------------------- + 5 | bNumDescriptors | 0x01 |The number of class + | | |descriptors is 1 +------|-------------------|-------|-------------------- + 6 | bDescriptorType | 0x22 |The class descriptor + | | |is Report descriptor +------|-------------------|-------|-------------------- + 7 | wDescriptorlength | 0x0034|The total size of + | | |the class descriptor + | | |is 52 +------|-------------------|-------|-------------------- + + ENDPOINT Descriptor + ------------------- +Offset| Field | Value | Description +------|------------------|-------|-------------------- + 0 | bLength | 0x07 |The size of this + | | |descriptor is 7 bytes +------|------------------|-------|-------------------- + 1 | bDescriptorType | 0x05 |ENDPOINT Descriptor Type +------|------------------|-------|-------------------- + 2 | bEndpointAddress | 0x81 |This is an IN + | | |endpoint with + | | |address (endpoint + | | |number) 1 +------|------------------|-------|-------------------- + 3 | bmAttributes | 0x03 |Types - + | | |Transfer:INTERRUPT + | | |Sync:No Sync + | | |Usage:Data EP +------|------------------|-------|-------------------- + 4 | wMaxPacketSize | 0x0004|Maximum packet size + | | |value for this + | | |endpoint is 0x4 + | | |(Bits 12-11: Addtl. Transactions/frame) +------|------------------|-------|-------------------- + 6 | bInterval | 0x0A |bInterval:10. The + | | |polling interval + | | |value is bInterval + | | |or 2**(bInterval-1) +------|------------------|-------|-------------------- + +*******************************************************************/ + + +#define CONFIG_DESC_NUM_INTERFACES (4) + +/* This must be counted manually and updated with the descriptor */ +/* 1*Config(9) + 1*Interface(9) + 1*HID(9) + 1* Endpoint (7)= 34 bytes */ +#define CONFIG_DESC_SIZE (34) + +static uint_8_ptr ConfigDesc; + +static uint_8 ConfigDescData[CONFIG_DESC_SIZE] = +{ + /*Config Descriptor */ + 0x09, + 0x02, + USB_uint_16_low(CONFIG_DESC_SIZE), + USB_uint_16_high(CONFIG_DESC_SIZE), + 0x01, + 0x01, + 0x00, + 0xE0, /* 0x80, */ + 0x0, + /* Interface Descriptor */ + 0x09, + 0x04, + 0x00, + 0x00, + 0x01, + 0x03, + 0x01, + 0x02, + 0x00, + + /* HID descriptor */ + 0x09, + 0x21, + USB_uint_16_low(0x0100), + USB_uint_16_high(0x0100), + 0x00, + 0x01, + 0x22, + USB_uint_16_low(0x0034), + USB_uint_16_high(0x0034), + + /*Endpoint descriptor */ + 0x07, + 0x05, + (0x80+INTERRUPT_EP), + 0x03, + USB_uint_16_low(INTERRUPT_MAX_PACKET_SIZE), + USB_uint_16_high(INTERRUPT_MAX_PACKET_SIZE), + FRAME_INTERVAL +}; + +#define OTHER_SPEED_CONFIG_DESC_SIZE CONFIG_DESC_SIZE +static uint_8_ptr other_speed_config; +static uint_8 other_speed_config_data[CONFIG_DESC_SIZE] = +{ + /*Config Descriptor */ + 0x09, + 0x07, + USB_uint_16_low(CONFIG_DESC_SIZE), + USB_uint_16_high(CONFIG_DESC_SIZE), + 0x01, + 0x01, + 0x00, + 0xE0, /* 0x80, */ + 0x0, + /* Interface Descriptor */ + 0x09, + 0x04, + 0x00, + 0x00, + 0x01, + 0x03, + 0x01, + 0x02, + 0x00, + + /* HID descriptor */ + 0x09, + 0x21, + USB_uint_16_low(0x0100), + USB_uint_16_high(0x0100), + 0x00, + 0x01, + 0x22, + USB_uint_16_low(0x0034), + USB_uint_16_high(0x0034), + + /*Endpoint descriptor */ + 0x07, + 0x05, + (0x80+INTERRUPT_EP), + 0x03, + USB_uint_16_low(INTERRUPT_MAX_PACKET_SIZE), + USB_uint_16_high(INTERRUPT_MAX_PACKET_SIZE), + FRAME_INTERVAL + +}; +/************************************************************************ + +HID Class Report Descriptor : + +Item Value(Hex) +------------------------------------------------------------------------------------------------------------ +Usage Page (Generic Desktop Control) 05 01 +Usage (Mouse) 09 02 +Collection (Application) A1 01 + Usage (Pointer) 09 01 + Collection (Physical) A1 00 + Usage Page (Button) 05 09 + Usage Minimum (1) 19 01 + Usage Maximum (3) 29 03 + Logical Minimum (0) 15 00 + Logical Maximum (1) 25 01 + Report Count (3) 95 03 + Report Size (1) 75 01 + Input (Data, Variable, Absolute) 81 02 + Report Count (1) 95 01 + Report Size (5) 75 05 + Input (Constant) 81 01 + Usage Page (Generic Desktop Control) 05 01 + Usage (X) 09 30 + Usage (Y) 09 31 + Usage (Wheel) 09 38 + Logical Minimum (-127) 15 81 + Logical Maximum (127) 25 7F + Report Size (8) 75 08 + Report Count (3) 95 03 + Input (Data, Variable, Relative) 81 06 + End Collection C0 +End Collection C0 + + +************************************************************************/ + +#define REPORT_DESC_SIZE (52) +static uint_8_ptr ReportDesc; + +static uint_8 ReportDescData[REPORT_DESC_SIZE] = +{ + 0x05, + 0x01, + 0x09, + 0x02, + 0xA1, + 0x01, + 0x09, + 0x01, + + 0xA1, + 0x00, + 0x05, + 0x09, + 0x19, + 0x01, + 0x29, + 0x03, + + 0x15, + 0x00, + 0x25, + 0x01, + 0x95, + 0x03, + 0x75, + 0x01, + + 0x81, + 0x02, + 0x95, + 0x01, + 0x75, + 0x05, + 0x81, + 0x01, + + 0x05, + 0x01, + 0x09, + 0x30, + 0x09, + 0x31, + 0x09, + 0x38, + + 0x15, + 0x81, + 0x25, + 0x7F, + 0x75, + 0x08, + 0x95, + 0x03, + + 0x81, + 0x06, + 0xC0, + 0xC0 +}; + +/************************************************************** +This report descriptor can be used to report the set_report +and get_report capability to host. When this is used, modify +the config descriptor to reflect the size of report descriptor. +The following lines should be changed, + +USB_uint_16_low(0x0038), // Changed from USB_uint_16_low(0x0034), +USB_uint_16_high(0x0038), // Changed from USB_uint_16_high(0x0034), + + + + +uint_8 ReportDesc[56] = { + 0x06, 0x00, 0xff, // USAGE_PAGE (Generic Desktop) + 0x09, 0x01, // USAGE (Vendor Usage 1) + 0xa1, 0x01, // COLLECTION (Application) + + 0x09, 0x02, // USAGE (Vendor Usage 2) + 0x15, 0x80, // LOGICAL_MINIMUM (-128) + 0x25, 0x7f, // LOGICAL_MAXIMUM (127) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0xb1, 0x02, // FEATURE (Data,Var,Abs) + + 0x09, 0x03, // USAGE (Vendor Usage 3) + 0x15, 0x80, // LOGICAL_MINIMUM (-128) + 0x25, 0x7f, // LOGICAL_MAXIMUM (127) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0xb1, 0x02, // FEATURE (Data,Var,Abs) + + 0x09, 0x04, // USAGE (Vendor Usage 4) + 0x15, 0x80, // LOGICAL_MINIMUM (-128) + 0x25, 0x7f, // LOGICAL_MAXIMUM (127) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0xb1, 0x02, // FEATURE (Data,Var,Abs) + + 0x09, 0x05, // USAGE (Vendor Usage 5) + 0x15, 0x80, // LOGICAL_MINIMUM (-128) + 0x25, 0x7f, // LOGICAL_MAXIMUM (127) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0xb1, 0x02, // FEATURE (Data,Var,Abs) + + 0xc0 // END_COLLECTION +}; +***************************************************************/ + +/********************************************************************** +Mouse data (this structure is used to send mouse movement information) +**********************************************************************/ +typedef struct _MOUSE_DATA { + char a; + char b; + char c; + char d; + +} MOUSE_DATA_STRUCT; + +static MOUSE_DATA_STRUCT mouse_data = {0,0,0,0}; + +static uint_8 USB_IF_ALT[4] = { 0, 0, 0, 0}; + +/* number of strings in the table not including 0 or n. */ +static const uint_8 USB_STR_NUM = 6; + +/* +** if the number of strings changes, look for USB_STR_0 everywhere and make +** the obvious changes. It should be found in 3 places. +*/ + +static const uint_16 USB_STR_0[ 2] = {0x0300 + sizeof(USB_STR_0),0x0409}; +static const uint_16 USB_STR_1[26] = {0x0300 + sizeof(USB_STR_1), + 'M','a','r','v','e','l','l',' ','S','e','m','i','c','o','n','d','u','c','t','o','r',' ','L','t','d'}; +static const uint_16 USB_STR_2[28] = {0x0300 + sizeof(USB_STR_2), + 'M','A','R','V','E','L','L',' ','U','S','B',' ','h','i','d','m','o','u','s','e',' ',\ + 'D','e','v','i','c','e'}; +static const uint_16 USB_STR_3[ 5] = {0x0300 + sizeof(USB_STR_3), + 'B','E','T','A'}; +static const uint_16 USB_STR_4[ 4] = {0x0300 + sizeof(USB_STR_4), + '#','0','2'}; +static const uint_16 USB_STR_5[ 4] = {0x0300 + sizeof(USB_STR_5), + '_','A','1'}; +static const uint_16 USB_STR_6[15] = {0x0300 + sizeof(USB_STR_6), + 'Y','o','u','r',' ','n','a','m','e',' ','h','e','r','e'}; +static const uint_16 USB_STR_n[17] = {0x0300 + sizeof(USB_STR_n), + 'B','A','D',' ','S','T','R','I','N','G',' ','I','n','d','e','x'}; + +#define USB_STRING_ARRAY_SIZE 8 +static const uint_8_ptr USB_STRING_DESC[USB_STRING_ARRAY_SIZE] = +{ + (uint_8_ptr)USB_STR_0, + (uint_8_ptr)USB_STR_1, + (uint_8_ptr)USB_STR_2, + (uint_8_ptr)USB_STR_3, + (uint_8_ptr)USB_STR_4, + (uint_8_ptr)USB_STR_5, + (uint_8_ptr)USB_STR_6, + (uint_8_ptr)USB_STR_n +}; + + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9GetDescription +* Returned Value : None +* Comments : +* Chapter 9 GetDescription command +* The Device Request can ask for Device/Config/string/interface/endpoint +* descriptors (via wValue). We then post an IN response to return the +* requested descriptor. +* And then wait for the OUT which terminates the control transfer. +* See section 9.4.3 (page 189) of the USB 1.1 Specification. +* +*END*--------------------------------------------------------------------*/ +static void ch9GetDescription + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + if (setup) { + /* Load the appropriate string depending on the descriptor requested.*/ + switch (setup_ptr->VALUE & 0xFF00) { + + case 0x0100: + _usb_device_send_data(handle, 0, DevDesc, + MIN(setup_ptr->LENGTH, DEVICE_DESCRIPTOR_SIZE)); + + break; + + case 0x0200: + *(ConfigDesc + 33) = frame_interval; + _usb_device_send_data(handle, 0, ConfigDesc, + MIN(setup_ptr->LENGTH, CONFIG_DESC_SIZE)); + + break; + + case 0x2200: + _usb_device_send_data(handle, 0, ReportDesc, + MIN(setup_ptr->LENGTH, REPORT_DESC_SIZE)); + + /*send some data for the mouse in the interrupt pipe queue */ + _usb_device_send_data(handle, INTERRUPT_EP, (uint_8_ptr)((pointer)&mouse_data), + sizeof(MOUSE_DATA_STRUCT)); + + break; + + case 0x0300: + if ((setup_ptr->VALUE & 0x00FF) > USB_STR_NUM) { + _usb_device_send_data(handle, 0, USB_STRING_DESC[USB_STR_NUM+1], + MIN(setup_ptr->LENGTH, USB_STRING_DESC[USB_STR_NUM+1][0])); + } else { + _usb_device_send_data(handle, 0, + USB_STRING_DESC[setup_ptr->VALUE & 0x00FF], + MIN(setup_ptr->LENGTH, USB_STRING_DESC[setup_ptr->VALUE & 0x00FF][0])); + } /* Endif */ + break; + + case 0x600: + _usb_device_send_data(handle, 0, (uint_8_ptr)DevQualifierDesc, + MIN(setup_ptr->LENGTH, DEVICE_QUALIFIER_DESCRIPTOR_SIZE)); + break; + + case 0x700: + *(other_speed_config + 33) = frame_interval; + + _usb_device_send_data(handle, 0, (uint_8_ptr)other_speed_config, + MIN(setup_ptr->LENGTH, OTHER_SPEED_CONFIG_DESC_SIZE)); + break; + + default: + USB_printf("usbMouse_%d, %s: Unexpected VALUE=0x%04x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, setup_ptr->VALUE); + _usb_device_stall_endpoint(handle, 0, 0); + return; + } /* Endswitch */ + /* status phase */ + _usb_device_recv_data(handle, 0, 0, 0); + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9SetDescription +* Returned Value : None +* Comments : +* Chapter 9 SetDescription command +* See section 9.4.8 (page 193) of the USB 1.1 Specification. +* +*END*--------------------------------------------------------------------*/ +static void ch9SetDescription + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + USB_printf("usbMouse_%d, %s: setup=%d\n", + _usb_device_get_dev_num(handle), __FUNCTION__, (int)setup); + _usb_device_stall_endpoint(handle, 0, 0); + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9GetConfig +* Returned Value : None +* Comments : +* Chapter 9 GetConfig command +* See section 9.4.2 (page 189) of the USB 1.1 Specification. +* +*END*--------------------------------------------------------------------*/ +static void ch9GetConfig + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + uint_16 current_config; + /* Return the currently selected configuration */ + if (setup){ + _usb_device_get_status(handle, ARC_USB_STATUS_CURRENT_CONFIG, + ¤t_config); + data_to_send = (uint_8)current_config; + _usb_device_send_data(handle, 0, (pointer) &data_to_send, sizeof(data_to_send)); + /* status phase */ + _usb_device_recv_data(handle, 0, 0, 0); + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9SetConfig +* Returned Value : None +* Comments : +* Chapter 9 SetConfig command +* +*END*--------------------------------------------------------------------*/ +static void ch9SetConfig + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + uint_16 usb_state; + + if (setup) + { + if ((setup_ptr->VALUE & 0x00FF) > 1) + { + /* generate stall */ + USB_printf("usbMouse_%d, %s: Wrong VALUE=0x%04x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, setup_ptr->VALUE); + _usb_device_stall_endpoint(handle, 0, 0); + return; + } /* Endif */ + + /* 0 indicates return to unconfigured state */ + if ((setup_ptr->VALUE & 0x00FF) == 0) + { + _usb_device_get_status(handle, ARC_USB_STATUS_DEVICE_STATE, &usb_state); + if ((usb_state == ARC_USB_STATE_CONFIG) || + (usb_state == ARC_USB_STATE_ADDRESS)) + { + /* clear the currently selected config value */ + _usb_device_set_status(handle, ARC_USB_STATUS_CURRENT_CONFIG, 0); + _usb_device_set_status(handle, ARC_USB_STATUS_DEVICE_STATE, + ARC_USB_STATE_ADDRESS); + /* status phase */ + _usb_device_send_data(handle, 0, 0, 0); + } + else + { + USB_printf("usbMouse_%d, %s: Wrong usb_state=%d\n", + _usb_device_get_dev_num(handle), __FUNCTION__, usb_state); + + _usb_device_stall_endpoint(handle, 0, 0); + } /* Endif */ + return; + } /* Endif */ + + /* + ** If the configuration value (setup_ptr->VALUE & 0x00FF) differs + ** from the current configuration value, then endpoints must be + ** reconfigured to match the new device configuration + */ + _usb_device_get_status(handle, ARC_USB_STATUS_CURRENT_CONFIG, &usb_state); + ARC_DEBUG_TRACE(ARC_DEBUG_FLAG_SETUP, + "usbMouse: Set configuration: old=%d, new=%d\n", + usb_state, setup_ptr->VALUE & 0x00FF); + + if (usb_state != (setup_ptr->VALUE & 0x00FF)) + { + /* Reconfigure endpoints here */ + switch (setup_ptr->VALUE & 0x00FF) + { + default: + break; + } /* Endswitch */ + _usb_device_set_status(handle, ARC_USB_STATUS_CURRENT_CONFIG, + setup_ptr->VALUE & 0x00FF); + } /* Endif */ + /* Init Interrupt endpoint */ + _usb_device_init_endpoint(handle,INTERRUPT_EP, INTERRUPT_MAX_PACKET_SIZE, + ARC_USB_SEND, ARC_USB_INTERRUPT_ENDPOINT, + ARC_USB_DEVICE_DONT_ZERO_TERMINATE); + + TEST_ENABLED = TRUE; + + _usb_device_set_status(handle, ARC_USB_STATUS_DEVICE_STATE, + ARC_USB_STATE_CONFIG); + /* status phase */ + _usb_device_send_data(handle, 0, 0, 0); + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9GetInterface +* Returned Value : None +* Comments : +* Chapter 9 GetInterface command +* See section 9.4.4 (page 190) of the USB 1.1 Specification. +* +*END*--------------------------------------------------------------------*/ +static void ch9GetInterface + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + uint_16 usb_state; + + _usb_device_get_status(handle, ARC_USB_STATUS_DEVICE_STATE, &usb_state); + if (usb_state != ARC_USB_STATE_CONFIG) + { + USB_printf("usbMouse_%d, %s: Wrong usb_state=%d\n", + _usb_device_get_dev_num(handle), __FUNCTION__, usb_state); + _usb_device_stall_endpoint(handle, 0, 0); + return; + } /* Endif */ + + if (setup) + { + _usb_device_send_data(handle, 0, &USB_IF_ALT[setup_ptr->INDEX & 0x00FF], + MIN(setup_ptr->LENGTH, sizeof(uint_8))); + /* status phase */ + _usb_device_recv_data(handle, 0, 0, 0); + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9SetInterface +* Returned Value : None +* Comments : +* Chapter 9 SetInterface command +* See section 9.4.10 (page 195) of the USB 1.1 Specification. +* +*END*--------------------------------------------------------------------*/ +static void ch9SetInterface + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + if (setup) + { + if (setup_ptr->REQUESTTYPE != 0x01) + { + USB_printf("usbDisk_%d, %s: Wrong REQUESTTYPE=0x%02x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, + setup_ptr->REQUESTTYPE); + + _usb_device_stall_endpoint(handle, 0, 0); + return; + } /* Endif */ + + /* + ** If the alternate value (setup_ptr->VALUE & 0x00FF) differs + ** from the current alternate value for the specified interface, + ** then endpoints must be reconfigured to match the new alternate + */ + if (USB_IF_ALT[setup_ptr->INDEX & 0x00FF] + != (setup_ptr->VALUE & 0x00FF)) + { + USB_IF_ALT[setup_ptr->INDEX & 0x00FF] = (setup_ptr->VALUE & 0x00FF); + /* Reconfigure endpoints here. */ + + } /* Endif */ + + /* status phase */ + _usb_device_send_data(handle, 0, 0, 0); + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9SynchFrame +* Returned Value : +* Comments : +* Chapter 9 SynchFrame command +* See section 9.4.11 (page 195) of the USB 1.1 Specification. +* +*END*--------------------------------------------------------------------*/ +static void ch9SynchFrame + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + + if (setup) + { + if (setup_ptr->REQUESTTYPE != 0x02) + { + USB_printf("usbMouse_%d, %s: Wrong REQUESTTYPE=0x%02x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, + setup_ptr->REQUESTTYPE); + _usb_device_stall_endpoint(handle, 0, 0); + return; + } /* Endif */ + + if ((setup_ptr->INDEX & 0x00FF) >= + ConfigDesc[CONFIG_DESC_NUM_INTERFACES]) + { + USB_printf("usbMouse_%d, %s: Wrong INDEX=0x%04x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, setup_ptr->INDEX); + _usb_device_stall_endpoint(handle, 0, 0); + return; + } /* Endif */ + + _usb_device_get_status(handle, ARC_USB_STATUS_SOF_COUNT, &sof_count); + + sof_count = USB_16BIT_LE(sof_count); + _usb_device_send_data(handle, 0, (uint_8_ptr)&sof_count, + MIN(setup_ptr->LENGTH, sizeof(sof_count))); + /* status phase */ + _usb_device_recv_data(handle, 0, 0, 0); + } /* Endif */ + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : get_report +* Returned Value : +* Comments : +* Chapter 9 Class specific request +* See section 9.4.11 (page 195) of the USB 1.1 Specification. +* +*END*--------------------------------------------------------------------*/ + +void get_report + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* [IN] Direction of the transfer. (1 for USB IN token)*/ + uint_8 direction, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + + ) +{ + int i; + + for(i=0;i<10;i++) + { + hid_test_rep_data[i] = (uint_8) i; + } + + if (setup) + { + _usb_device_send_data(handle, 0, (uint_8_ptr)hid_test_rep_data, MIN(setup_ptr->LENGTH,4)); + } + + _usb_device_recv_data(handle, 0, 0, 0); + + + return; +} + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : set_report +* Returned Value : +* Comments : +* Chapter 9 Class specific request +* See section 9.4.11 (page 195) of the USB 1.1 Specification. +* +*END*--------------------------------------------------------------------*/ + +void set_report + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* [IN] Direction of the transfer. (1 for USB IN token)*/ + uint_8 direction, + + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ + if (setup) /*on a SetUP packet*/ + { + _usb_device_recv_data(handle, 0, (uint_8_ptr)hid_test_rep_data, MIN(setup_ptr->LENGTH,4)); + + } + else if(direction == ARC_USB_RECV) /*on a OUT packet*/ + { + _usb_device_recv_data(handle, 0, (uint_8_ptr)hid_test_rep_data, MIN(setup_ptr->LENGTH,4)); + _usb_device_send_data(handle, 0, 0, 0); + } + + return; +} + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : set_idle +* Returned Value : +* Comments : +* Chapter 9 Class specific request +* See section 9.4.11 (page 195) of the USB 1.1 Specification. +* +*END*--------------------------------------------------------------------*/ + +void set_idle + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* [IN] Direction of the transfer. (1 for USB IN token)*/ + uint_8 direction, + + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ + /* SET_IDLE is a No data phase transaction from HID class. All it needs + is a terminating IN token */ + if (setup) /*on a SetUP packet*/ + { + _usb_device_send_data(handle, 0, 0, 0); + } + return; +} + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : ch9Class +* Returned Value : +* Comments : +* Chapter 9 Class specific request +* See section 9.4.11 (page 195) of the USB 1.1 Specification. +* +*END*--------------------------------------------------------------------*/ +static void ch9Class + ( + /* USB handle */ + _usb_device_handle handle, + + /* Is it a Setup phase? */ + boolean setup, + + /* [IN] Direction of the transfer. (1 for USB IN token)*/ + uint_8 direction, + + /* The setup packet pointer */ + SETUP_STRUCT_PTR setup_ptr + ) +{ /* Body */ + + switch (setup_ptr->REQUEST) + { + + case 0x01: + get_report(handle, setup, direction, setup_ptr); + break; + + case 0x09: + set_report(handle, setup, direction, setup_ptr); + break; + + case 0x0A: + set_idle(handle, setup, direction, setup_ptr); + break; + + default: + USB_printf("usbMouse_%d, %s: Wrong REQUEST=0x%02x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, setup_ptr->REQUEST); + + _usb_device_stall_endpoint(handle, 0, 0); + break; + + } /* EndSwitch */ + +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : service_ep0 +* Returned Value : None +* Comments : +* Called upon a completed endpoint 0 (USB 1.1 Chapter 9) transfer +* +*END*--------------------------------------------------------------------*/ +static void service_ep0 + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] request type as registered */ + uint_8 type, + + /* [IN] Is it a setup packet? */ + boolean setup, + + /* [IN] Direction of the transfer. Is it transmit? */ + uint_8 direction, + + /* [IN] Pointer to the data buffer */ + uint_8_ptr buffer, + + /* [IN] Length of the transfer */ + uint_32 length, + + /* [IN] Error, if any */ + uint_8 error + + + ) +{ /* Body */ + boolean class_request = FALSE; + + if (setup) + { + _usb_device_read_setup_data(handle, 0, (uint_8_ptr)&local_setup_packet); + local_setup_packet.VALUE = USB_16BIT_LE(local_setup_packet.VALUE); + local_setup_packet.INDEX = USB_16BIT_LE(local_setup_packet.INDEX); + local_setup_packet.LENGTH = USB_16BIT_LE(local_setup_packet.LENGTH); + } + else if (class_request) { + class_request = FALSE; + /* Finish your class or vendor request here */ + + return; + } /* Endif */ + + switch (local_setup_packet.REQUESTTYPE & 0x60) { + + case 0x00: + switch (local_setup_packet.REQUEST) { + + case 0x0: + mvUsbCh9GetStatus(handle, setup, &local_setup_packet); + break; + + case 0x1: + mvUsbCh9ClearFeature(handle, setup, &local_setup_packet); + break; + + case 0x3: + mvUsbCh9SetFeature(handle, setup, &local_setup_packet); + break; + + case 0x5: + mvUsbCh9SetAddress(handle, setup, &local_setup_packet); + break; + + case 0x6: + ch9GetDescription(handle, setup, &local_setup_packet); + break; + + case 0x7: + ch9SetDescription(handle, setup, &local_setup_packet); + break; + + case 0x8: + ch9GetConfig(handle, setup, &local_setup_packet); + break; + + case 0x9: + ch9SetConfig(handle, setup, &local_setup_packet); + break; + + case 0xa: + ch9GetInterface(handle, setup, &local_setup_packet); + break; + + case 0xb: + ch9SetInterface(handle, setup, &local_setup_packet); + break; + + case 0xc: + ch9SynchFrame(handle, setup, &local_setup_packet); + break; + + default: + USB_printf("usbMouse_%d, %s: Wrong REQUEST = 0x%02x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, local_setup_packet.REQUEST); + _usb_device_stall_endpoint(handle, 0, 0); + break; + + } /* Endswitch */ + + break; + + case 0x20: + ch9Class(handle, setup, direction, &local_setup_packet); + + break; + + case 0x40: + /* vendor specific request */ + break; + + default: + USB_printf("usbMouse_%d, %s: Unexpected REQUESTTYPE = 0x%x\n", + _usb_device_get_dev_num(handle), __FUNCTION__, + local_setup_packet.REQUESTTYPE); + + _usb_device_stall_endpoint(handle, 0, 0); + break; + + } /* Endswitch */ + + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : service_ep1 +* Returned Value : None +* Comments : +* Called upon a completed endpoint 1 (USB 1.1 Chapter 9) transfer +* +*END*--------------------------------------------------------------------*/ +static void service_ep1 + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] request type as registered */ + uint_8 type, + + /* [IN] Is it a setup packet? */ + boolean setup, + + /* [IN] Direction of the transfer. Is it transmit? */ + uint_8 direction, + + /* [IN] Pointer to the data buffer */ + uint_8_ptr buffer, + + /* [IN] Length of the transfer */ + uint_32 length, + + /* [IN] Error, if any */ + uint_8 error + + + ) +{ /* Body */ + +/******************************************************************** + The following code will move the mouse right and left on the screen. + Comment this out if this behaviour is not desired. +********************************************************************/ + + static int x = 0; + static boolean right = FALSE; + static int wait = 0; + + mouseCntr++; + if(wait == 0) + { + if (right == FALSE) + { + mouse_data.b = 1; + x++; + right = (x > 200) ? TRUE : FALSE; + } + + if (right == TRUE) + { + mouse_data.b = -1; + x--; + right = (x < 0) ? FALSE : TRUE; + } + wait = mouseDelay; + } + else + { + wait--; + mouse_data.b = 0; + } + + _usb_device_send_data(handle, INTERRUPT_EP, (uint_8_ptr)((pointer)&mouse_data), + sizeof(MOUSE_DATA_STRUCT)); + + return; +} /* Endbody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : reset_ep0 +* Returned Value : None +* Comments : +* Called upon a bus reset event. Initialises the control endpoint. +* +*END*--------------------------------------------------------------------*/ +static void reset_ep0 + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] request type as registered */ + uint_8 type, + + /* [IN] Unused */ + boolean setup, + + /* [IN] Unused */ + uint_8 direction, + + /* [IN] Unused */ + uint_8_ptr buffer, + + /* [IN] Unused */ + uint_32 length, + + /* [IN] Error, if any */ + uint_8 error + + + ) +{ /* Body */ + + /*on a reset always cancel all transfers all EP 0 */ + _usb_device_cancel_transfer(handle, 0, ARC_USB_RECV); + _usb_device_cancel_transfer(handle, 0, ARC_USB_SEND); + + _usb_device_start(handle); + + /* Initialize the endpoint 0 in both directions */ + _usb_device_init_endpoint(handle, 0, DevDesc[DEV_DESC_MAX_PACKET_SIZE], 0, + ARC_USB_CONTROL_ENDPOINT, 0); + _usb_device_init_endpoint(handle, 0, DevDesc[DEV_DESC_MAX_PACKET_SIZE], 1, + ARC_USB_CONTROL_ENDPOINT, 0); + + if (TEST_ENABLED) + { + _usb_device_cancel_transfer(handle, INTERRUPT_EP, ARC_USB_SEND); + } /* Endif */ + + TEST_ENABLED = FALSE; + mouseCntr = 0; + + return; +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : service_suspend +* Returned Value : None +* Comments : +* Called when host suspend the USB port. Do remote wake up if desired. +* +*END*--------------------------------------------------------------------*/ +static void service_suspend + ( + /* [IN] Handle of the USB device */ + _usb_device_handle handle, + + /* [IN] request type as registered */ + uint_8 type, + + /* [IN] Unused */ + boolean setup, + + /* [IN] Unused */ + uint_8 direction, + + /* [IN] Unused */ + uint_8_ptr buffer, + + /* [IN] Unused */ + uint_32 length, + + /* [IN] Error, if any */ + uint_8 error + ) +{ /* Body */ + uint_16 usb_status; + int lockKey; + + _usb_device_get_status(handle, ARC_USB_STATUS_DEVICE, &usb_status); + if (usb_status & ARC_USB_REMOTE_WAKEUP) + { + lockKey = USB_lock(); + + USB_printf("Mouse Suspended: type=%d, usbStatus=0x%x\n", type, usb_status); + USB_SUSPENDED = TRUE; + + USB_unlock(lockKey); + } + + return; +} /* EndBody */ + +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : usbMouseLoad +* Returned Value : None +* Comments : +* First function called. Initialises the USB and registers Chapter 9 +* callback functions. +* +*END*--------------------------------------------------------------------*/ +_usb_device_handle usbMouseLoad(int devNo) +{ /* Body */ + _usb_device_handle handle; + uint_8 error; + uint_32 send_data_buffer_size=0; + uint_8_ptr temp; + int lockKey, i, j; + static boolean isFirst = TRUE; + + if(isFirst) + { + /* Swap all USB_STRING_DESC */ + for(i=0; i<(sizeof(USB_STRING_DESC)/sizeof(USB_STRING_DESC[0])); i++) + { + uint_16* usbStr = (uint_16*)(USB_STRING_DESC[i]); + uint_16 size = (usbStr[0]-0x300)/sizeof(uint_16); + + for(j=0; j gpp5, DDR2 => gpp1 */ + if(gppNo != (MV_U8)N_A) + { + /*mvOsPrintf("mvUsbGppInit: gppNo=%d\n", gppNo);*/ + + /* MPP Control Register - set to GPP*/ + regVal = MV_REG_READ(mvCtrlMppRegGet((unsigned int)(gppNo/8))); + regVal &= ~(0xf << ((gppNo%8)*4)); + MV_REG_WRITE(mvCtrlMppRegGet((unsigned int)(gppNo/8)), regVal); + + + if(gppNo < 32) + { + /* GPIO Data Out Enable Control Register - set to input*/ + mvGppTypeSet(0, (1< bits[17:16] = 0x1 */ + if( (mvCtrlModelGet() == MV64560_DEV_ID) || + (mvCtrlModelGet() == MV64660_DEV_ID)) + { + regVal &= ~(0x3 << 16); + regVal |= (0x1 << 16); + } + + /* bits[19:18] = 0x2 */ + regVal &= ~(0x3 << 18); + regVal |= (0x2 << 18); + + /* bit[20] = 0x0 */ + regVal &= ~(0x1 << 20); + + /* bit[21] = 0x1 */ + regVal |= (0x1 << 21); + + MV_REG_WRITE(MV_USB_PHY_IVREF_CTRL_REG(dev), regVal); + + /***** USB PHY TEST GROUP CONTROL Register: 0x450 *****/ + regVal = MV_REG_READ(MV_USB_PHY_TEST_GROUP_CTRL_REG_0(dev)); + + /* bit[15] = 0 (REG_FIFO_SQ_RST = 0). */ + regVal &= ~(1 << 15); + + /* bit[17] = 0x1 */ + if( (mvCtrlModelGet() == MV64560_DEV_ID) || + (mvCtrlModelGet() == MV64660_DEV_ID)) + { + regVal |= (1 << 17); + } + + MV_REG_WRITE(MV_USB_PHY_TEST_GROUP_CTRL_REG_0(dev), regVal); +} + +/******************************************************************************* +* mvUsbHalInit - Initialize USB engine +* +* DESCRIPTION: +* This function initialize USB unit. It set the default address decode +* windows of the unit. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if setting fail. +*******************************************************************************/ +MV_STATUS mvUsbHalInit(int dev, MV_BOOL isHost) +{ + MV_U32 regVal; + + /* Wait 100 usec */ + mvOsUDelay(100); + + /* Clear Interrupt Cause and Mask registers */ + MV_REG_WRITE(MV_USB_BRIDGE_INTR_CAUSE_REG(dev), 0); + MV_REG_WRITE(MV_USB_BRIDGE_INTR_MASK_REG(dev), 0); + + /* Reset controller */ + regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev)); + MV_REG_WRITE(MV_USB_CORE_CMD_REG(dev), regVal | MV_USB_CORE_CMD_RESET_MASK); + while( MV_REG_READ(MV_USB_CORE_CMD_REG(dev)) & MV_USB_CORE_CMD_RESET_MASK); + + /* Clear bit 4 in USB bridge control register for enableing core byte swap */ + if((mvCtrlModelGet() == MV64560_DEV_ID) || (mvCtrlModelGet() == MV64660_DEV_ID)) + { + MV_REG_WRITE(MV_USB_BRIDGE_CTRL_REG(dev),(MV_REG_READ(MV_USB_BRIDGE_CTRL_REG(dev)) + & ~MV_USB_BRIDGE_CORE_BYTE_SWAP_MASK)); + } + + /* GL# USB-10 */ + /* The new register 0x360 USB 2.0 IPG Metal Fix Register + * dont' exists in the following chip revisions: + * OrionN B1 (id=0x5180, rev 3) + * Orion1 B1 (id=0x5181, rev=3) and before + * Orion1-VoIP A0 (id=0x5181, rev=8) + * Orion1-NAS A1 (id=0x5182, rev=1) and before + * Orion2 B0 (id=0x5281, rev=1) and before + */ + if( ((mvCtrlModelGet() == MV_5181_DEV_ID) && + ((mvCtrlRevGet() <= MV_5181_B1_REV) || (mvCtrlRevGet() == MV_5181L_A0_REV))) || + ((mvCtrlModelGet() == MV_5182_DEV_ID) && + (mvCtrlRevGet() <= MV_5182_A1_REV)) || + ((mvCtrlModelGet() == MV_5180_DEV_ID) && + (mvCtrlRevGet() <= MV_5180N_B1_REV)) ) + { + /* Do nothing */ + } + else + { + /* Change value of new register 0x360 */ + regVal = MV_REG_READ(MV_USB_BRIDGE_IPG_REG(dev)); + + /* Change bits[14:8] - IPG for non Start of Frame Packets + * from 0x9(default) to 0xD + */ + regVal &= ~(0x7F << 8); + regVal |= (0xD << 8); + + MV_REG_WRITE(MV_USB_BRIDGE_IPG_REG(dev), regVal); + } +#ifndef MV_USB_PHY_DONT_OVERRIDE + /********* Update USB PHY configuration **********/ + if( (mvCtrlModelGet() == MV_78100_DEV_ID) || + (mvCtrlModelGet() == MV_78200_DEV_ID) || + (mvCtrlModelGet() == MV_76100_DEV_ID) || + (mvCtrlModelGet() == MV_6281_DEV_ID) || + (mvCtrlModelGet() == MV_6282_DEV_ID) || + (mvCtrlModelGet() == MV_6280_DEV_ID) || + (mvCtrlModelGet() == MV_6192_DEV_ID) || + (mvCtrlModelGet() == MV_6190_DEV_ID) || + (mvCtrlModelGet() == MV_6180_DEV_ID) || + (mvCtrlModelGet() == MV_6321_DEV_ID) || + (mvCtrlModelGet() == MV_6322_DEV_ID) || + (mvCtrlModelGet() == MV_6323_DEV_ID)) + { + mvUsbPhy65nmNewInit(dev); + } + else if((mvCtrlModelGet() == MV_78XX0_DEV_ID)) + { + mvUsbPhy65nmInit(dev); + } + else if( mvCtrlModelGet() == MV_6183_DEV_ID ) + { + mvUsbPhy90nmInit(dev); + } + else + { + mvUsbPhyInit(dev); + } +#endif + /* Set Mode register (Stop and Reset USB Core before) */ + /* Stop the controller */ + regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev)); + regVal &= ~MV_USB_CORE_CMD_RUN_MASK; + MV_REG_WRITE(MV_USB_CORE_CMD_REG(dev), regVal); + + /* Reset the controller to get default values */ + regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev)); + regVal |= MV_USB_CORE_CMD_RESET_MASK; + MV_REG_WRITE(MV_USB_CORE_CMD_REG(dev), regVal); + + /* Wait for the controller reset to complete */ + do + { + regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev)); + } while (regVal & MV_USB_CORE_CMD_RESET_MASK); + + /* Set USB_MODE register */ + if(isHost) + { + regVal = MV_USB_CORE_MODE_HOST; + } + else + { + regVal = MV_USB_CORE_MODE_DEVICE | MV_USB_CORE_SETUP_LOCK_DISABLE_MASK; + } + +#if (MV_USB_VERSION == 0) + regVal |= MV_USB_CORE_STREAM_DISABLE_MASK; +#endif + + MV_REG_WRITE(MV_USB_CORE_MODE_REG(dev), regVal); + + return MV_OK; +} + + +void mvUsbPowerDown(int dev) +{ + MV_U32 regVal; + + /* Stop USB Controller core */ + regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev)); + if(regVal & MV_USB_CORE_CMD_RUN_MASK) + { + mvOsPrintf("USB #%d: Warning USB core was not disabled\n", dev); + regVal &= ~MV_USB_CORE_CMD_RUN_MASK; + MV_REG_WRITE(MV_USB_CORE_CMD_REG(dev), regVal); + } + + /* Power Down USB PHY */ + regVal = MV_REG_READ(MV_USB_PHY_POWER_CTRL_REG(dev)); + regVal &= ~(MV_USB_PHY_POWER_UP_MASK | MV_USB_PHY_PLL_POWER_UP_MASK); + + MV_REG_WRITE(MV_USB_PHY_POWER_CTRL_REG(dev), regVal); +} + +void mvUsbPowerUp(int dev) +{ + MV_U32 regVal; + + /* Power Up USB PHY */ + regVal = MV_REG_READ(MV_USB_PHY_POWER_CTRL_REG(dev)); + regVal |= (MV_USB_PHY_POWER_UP_MASK | MV_USB_PHY_PLL_POWER_UP_MASK); + + MV_REG_WRITE(MV_USB_PHY_POWER_CTRL_REG(dev), regVal); + + /* Start USB core */ + regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev)); + if(regVal & MV_USB_CORE_CMD_RUN_MASK) + { + mvOsPrintf("USB #%d: Warning USB core is enabled\n", dev); + } + else + { + regVal |= MV_USB_CORE_CMD_RUN_MASK; + MV_REG_WRITE(MV_USB_CORE_CMD_REG(dev), regVal); + } +} + + +void mvUsbRegs(int dev) +{ + mvOsPrintf("\n\tUSB-%d Bridge Registers\n\n", dev); + + mvOsPrintf("MV_USB_BRIDGE_CTRL_REG : 0x%X = 0x%08x\n", + MV_USB_BRIDGE_CTRL_REG(dev), + MV_REG_READ(MV_USB_BRIDGE_CTRL_REG(dev)) ); + + mvOsPrintf("MV_USB_BRIDGE_INTR_MASK_REG : 0x%X = 0x%08x\n", + MV_USB_BRIDGE_INTR_MASK_REG(dev), + MV_REG_READ(MV_USB_BRIDGE_INTR_MASK_REG(dev))); + + mvOsPrintf("MV_USB_BRIDGE_INTR_CAUSE_REG : 0x%X = 0x%08x\n", + MV_USB_BRIDGE_INTR_CAUSE_REG(dev), + MV_REG_READ(MV_USB_BRIDGE_INTR_CAUSE_REG(dev))); + + mvOsPrintf("MV_USB_BRIDGE_ERROR_ADDR_REG : 0x%X = 0x%08x\n", + MV_USB_BRIDGE_ERROR_ADDR_REG(dev), + MV_REG_READ(MV_USB_BRIDGE_ERROR_ADDR_REG(dev))); + + mvOsPrintf("\n\tUSB-%d PHY Registers\n\n", dev); + + mvOsPrintf("MV_USB_PHY_POWER_CTRL_REG : 0x%X = 0x%08x\n", + MV_USB_PHY_POWER_CTRL_REG(dev), + MV_REG_READ(MV_USB_PHY_POWER_CTRL_REG(dev)) ); + + mvOsPrintf("MV_USB_PHY_TX_CTRL_REG : 0x%X = 0x%08x\n", + MV_USB_PHY_TX_CTRL_REG(dev), + MV_REG_READ(MV_USB_PHY_TX_CTRL_REG(dev)) ); + mvOsPrintf("MV_USB_PHY_RX_CTRL_REG : 0x%X = 0x%08x\n", + MV_USB_PHY_RX_CTRL_REG(dev), + MV_REG_READ(MV_USB_PHY_RX_CTRL_REG(dev)) ); + mvOsPrintf("MV_USB_PHY_IVREF_CTRL_REG : 0x%X = 0x%08x\n", + MV_USB_PHY_IVREF_CTRL_REG(dev), + MV_REG_READ(MV_USB_PHY_IVREF_CTRL_REG(dev)) ); + + mvOsPrintf("\n"); + +} + +void mvUsbCoreRegs(int dev, MV_BOOL isHost) +{ + mvOsPrintf("\n\t USB-%d Core %s Registers\n\n", + dev, isHost ? "HOST" : "DEVICE"); + + mvOsPrintf("MV_USB_CORE_ID_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_ID_REG(dev), + MV_REG_READ(MV_USB_CORE_ID_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_GENERAL_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_GENERAL_REG(dev), + MV_REG_READ(MV_USB_CORE_GENERAL_REG(dev)) ); + + if(isHost) + { + mvOsPrintf("MV_USB_CORE_HOST_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_HOST_REG(dev), + MV_REG_READ(MV_USB_CORE_HOST_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_TTTX_BUF_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_TTTX_BUF_REG(dev), + MV_REG_READ(MV_USB_CORE_TTTX_BUF_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_TTRX_BUF_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_TTRX_BUF_REG(dev), + MV_REG_READ(MV_USB_CORE_TTRX_BUF_REG(dev)) ); + } + else + { + mvOsPrintf("MV_USB_CORE_DEVICE_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_DEVICE_REG(dev), + MV_REG_READ(MV_USB_CORE_DEVICE_REG(dev)) ); + } + + mvOsPrintf("MV_USB_CORE_TX_BUF_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_TX_BUF_REG(dev), + MV_REG_READ(MV_USB_CORE_TX_BUF_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_RX_BUF_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_RX_BUF_REG(dev), + MV_REG_READ(MV_USB_CORE_RX_BUF_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_CAP_LENGTH_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_CAP_LENGTH_REG(dev), + MV_REG_READ(MV_USB_CORE_CAP_LENGTH_REG(dev)) ); + + if(isHost) + { + mvOsPrintf("MV_USB_CORE_CAP_HCS_PARAMS_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_CAP_HCS_PARAMS_REG(dev), + MV_REG_READ(MV_USB_CORE_CAP_HCS_PARAMS_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_CAP_HCC_PARAMS_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_CAP_HCC_PARAMS_REG(dev), + MV_REG_READ(MV_USB_CORE_CAP_HCC_PARAMS_REG(dev)) ); + } + else + { + mvOsPrintf("MV_USB_CORE_CAP_DCI_VERSION_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_CAP_DCI_VERSION_REG(dev), + MV_REG_READ(MV_USB_CORE_CAP_DCI_VERSION_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_CAP_DCC_PARAMS_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_CAP_DCC_PARAMS_REG(dev), + MV_REG_READ(MV_USB_CORE_CAP_DCC_PARAMS_REG(dev)) ); + } + + mvOsPrintf("MV_USB_CORE_CMD_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_CMD_REG(dev), + MV_REG_READ(MV_USB_CORE_CMD_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_STATUS_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_STATUS_REG(dev), + MV_REG_READ(MV_USB_CORE_STATUS_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_INTR_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_INTR_REG(dev), + MV_REG_READ(MV_USB_CORE_INTR_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_FRAME_INDEX_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_FRAME_INDEX_REG(dev), + MV_REG_READ(MV_USB_CORE_FRAME_INDEX_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_MODE_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_MODE_REG(dev), + MV_REG_READ(MV_USB_CORE_MODE_REG(dev)) ); + + if(isHost) + { + mvOsPrintf("MV_USB_CORE_PERIODIC_LIST_BASE_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_PERIODIC_LIST_BASE_REG(dev), + MV_REG_READ(MV_USB_CORE_PERIODIC_LIST_BASE_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_ASYNC_LIST_ADDR_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_ASYNC_LIST_ADDR_REG(dev), + MV_REG_READ(MV_USB_CORE_ASYNC_LIST_ADDR_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_CONFIG_FLAG_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_CONFIG_FLAG_REG(dev), + MV_REG_READ(MV_USB_CORE_CONFIG_FLAG_REG(dev)) ); + } + else + { + int numEp, ep; + MV_U32 epCtrlVal; + + mvOsPrintf("MV_USB_CORE_DEV_ADDR_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_DEV_ADDR_REG(dev), + MV_REG_READ(MV_USB_CORE_DEV_ADDR_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_ENDPOINT_LIST_ADDR_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_ENDPOINT_LIST_ADDR_REG(dev), + MV_REG_READ(MV_USB_CORE_ENDPOINT_LIST_ADDR_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_ENDPT_SETUP_STAT_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_ENDPT_SETUP_STAT_REG(dev), + MV_REG_READ(MV_USB_CORE_ENDPT_SETUP_STAT_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_ENDPT_PRIME_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_ENDPT_PRIME_REG(dev), + MV_REG_READ(MV_USB_CORE_ENDPT_PRIME_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_ENDPT_FLUSH_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_ENDPT_FLUSH_REG(dev), + MV_REG_READ(MV_USB_CORE_ENDPT_FLUSH_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_ENDPT_STATUS_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_ENDPT_STATUS_REG(dev), + MV_REG_READ(MV_USB_CORE_ENDPT_STATUS_REG(dev)) ); + + mvOsPrintf("MV_USB_CORE_ENDPT_COMPLETE_REG : 0x%X = 0x%08x\n", + MV_USB_CORE_ENDPT_COMPLETE_REG(dev), + MV_REG_READ(MV_USB_CORE_ENDPT_COMPLETE_REG(dev)) ); + + numEp = MV_REG_READ(MV_USB_CORE_CAP_DCC_PARAMS_REG(dev)) & 0x1F; + + for(ep=0; ep= 20ma */ + { "MALTA", 0, 0, 0, 0, 1, 0x3, 0, 0x2, }, + { "MEXICO", 0, 0, 0, 0, 0, 0x3, 0, 0, }, + { "MOROCCO", 0, 0, 0, 0, 1, 0x3, 0, 0x2, }, + { "NETHERLANDS", 0, 1, 0, 0, 1, 0x3, 0, 0x2, }, + { "NEWZEALAND", 0, 0, 0, 0, 0, 0x3, 0, 0x4, }, + { "NIGERIA", 0, 0, 0, 0, 0x1, 0x3, 0, 0x2, }, + { "NORWAY", 0, 1, 0, 0, 1, 0x3, 0, 0x2, }, + { "OMAN", 0, 0, 0, 0, 0, 0, 0x3, 0, }, + { "PAKISTAN", 0, 0, 0, 0, 0, 0, 0x3, 0, }, + { "PERU", 0, 0, 0, 0, 0, 0x3, 0, 0, }, + { "PHILIPPINES", 0, 0, 0, 0, 0, 0, 0x3, 0, }, + { "POLAND", 0, 0, 1, 1, 0, 0x3, 0, 0, }, + { "PORTUGAL", 0, 1, 0, 0, 1, 0x3, 0, 0x2, }, + { "ROMANIA", 0, 0, 0, 0, 0, 3, 0, 0, }, + { "RUSSIA", 0, 0, 0, 0, 0, 0, 0x3, 0, }, + { "SAUDIARABIA", 0, 0, 0, 0, 0, 0x3, 0, 0, }, + { "SINGAPORE", 0, 0, 0, 0, 0, 0x3, 0, 0, }, + { "SLOVAKIA", 0, 0, 0, 0, 0, 0x3, 0, 0x3, }, + { "SLOVENIA", 0, 0, 0, 0, 0, 0x3, 0, 0x2, }, + { "SOUTHAFRICA", 1, 0, 1, 0, 0, 0x3, 0, 0x3, }, + { "SOUTHKOREA", 0, 0, 0, 0, 0, 0x3, 0, 0, }, + { "SPAIN", 0, 1, 0, 0, 1, 0x3, 0, 0x2, }, + { "SWEDEN", 0, 1, 0, 0, 1, 0x3, 0, 0x2, }, + { "SWITZERLAND", 0, 1, 0, 0, 1, 0x3, 0, 0x2, }, + { "TAIWAN", 0, 0, 0, 0, 0, 0, 0x3, 0, }, + { "TBR21", 0, 0, 0, 0, 1, 0x3, 0, 0x2/*, 0x7e6c, 0x023a, */}, + /* Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, + Norway, Portugal, Spain, Sweden, Switzerland, and UK */ + { "THAILAND", 0, 0, 0, 0, 0, 0, 0x3, 0, }, + { "UAE", 0, 0, 0, 0, 0, 0x3, 0, 0, }, + { "UK", 0, 1, 0, 0, 1, 0x3, 0, 0x5, }, + { "USA", 0, 0, 0, 0, 0, 0x3, 0, 0, }, + { "YEMEN", 0, 0, 0, 0, 0, 0x3, 0, 0, }, + { "FCC", 0, 0, 0, 1, 0, 0x3, 0, 0, }, /* US, Canada */ + +}; + + +static unsigned char mvDaaDirectRegRead(unsigned int lineId, unsigned char address) +{ + unsigned char data; + + mvVbSpiRead(lineId, address, MV_LINE_FXO, &data); + return data; +} + +static void mvDaaDirectRegWrite(unsigned int lineId, unsigned char address, unsigned char data) +{ + mvVbSpiWrite(lineId, address, MV_LINE_FXO, data); +} + +static void mvDaaPrintInfo(unsigned int lineId) +{ + unsigned char reg11; + + reg11 = mvDaaDirectRegRead(lineId, DAA_SYSTEM_AND_LINE_SIDE_REV_REG); + if(reg11) + { + DBG("DAA Si3050 Detected.\n"); + + switch((reg11 & DAA_LINE_SIDE_ID_MASK)) + { + case DAA_SI3018 : DBG("Line Side ID: Si3018\n"); + break; + + case DAA_SI3019 : DBG("Line Side ID: Si3019\n"); + break; + + default: DBG("Unkown Line Side ID\n"); + break; + } + + switch((reg11 & DAA_SYSTEM_SIDE_REVISION_MASK)) + { + case DAA_SYSTEM_SIDE_REV_A: DBG("System Side Revision: A\n"); + break; + + case DAA_SYSTEM_SIDE_REV_B: DBG("System Side Revision: B\n"); + break; + + case DAA_SYSTEM_SIDE_REV_C: DBG("System Side Revision: C\n"); + break; + + case DAA_SYSTEM_SIDE_REV_D: DBG("System Side Revision: D\n"); + break; + + default: DBG("Unkonwn System Side Revision\n"); + break; + } + + DBG("DAA Country Settings: %s\n",daaModes[COUNTRY_INDEX].name); + } + else + mvOsPrintf("Error, unable to communicate with DAA\n"); + +} + +MV_STATUS mvDaaInit(unsigned short first, unsigned short last, unsigned short pSlotInfo[][2], + unsigned short lines, mv_band_mode_t bandMode, mv_pcm_format_t pcmFormat) +{ + unsigned char reg2 = 0, reg24 = 0, reg33 = 0; + unsigned short newDelay, lineId; + MV_DAA_LINE_INFO *pDaaLineInfo; + int lineSideId; + + MV_TRC_REC("->%s\n", __FUNCTION__); + + /* Save parameters */ + firstDaa = first; + lastDaa = last; + mvBandMode = bandMode; + mvPcmFormat = pcmFormat; + totalDAAs = last -first + 1; + spiMode = mvBoardTdmSpiModeGet(); + + /* Allocate MV_DAA_LINE_INFO array */ + daaLineInfo = (MV_DAA_LINE_INFO*)mvOsMalloc(sizeof(MV_DAA_LINE_INFO) * lines); + if(!daaLineInfo) + { + mvOsPrintf("%s: allocation failed(daaLineInfo) !!!\n",__FUNCTION__); + return MV_ERROR; + } + + pDaaLineInfo = (MV_DAA_LINE_INFO*)(daaLineInfo + first); + + mvOsPrintf("Start initialization for DAA modules %u to %u...",first, last); + + for(lineId = first; lineId < (last+1); lineId++) + { + pDaaLineInfo->lineId = lineId; + pDaaLineInfo->hook = 0; + pDaaLineInfo->ring = 0; + pDaaLineInfo->reverse_polarity = 0; + pDaaLineInfo->drop_out = 0; + + /* Software reset */ + mvDaaDirectRegWrite(lineId, 1, 0x80); + + /* Wait just a bit */ + mvOsDelay(100); + + mvDaaDigitalHybridSet(COUNTRY_INDEX, lineId); + + /* Configure tx/rx sample in DAA */ + pDaaLineInfo->rxSample = pSlotInfo[lineId][0]; + pDaaLineInfo->txSample = pSlotInfo[lineId][0]; + DBG("Rx sample %d, Tx sample %d\n",pDaaLineInfo->rxSample, pDaaLineInfo->txSample); + pDaaLineInfo->txSample *= 8; + pDaaLineInfo->rxSample *= 8; + + mvDaaPcmStartCountRegsSet(lineId); + + /* Enable PCM & linear 16-bit/a-Law 8-bit/u-Law 8-bit */ + switch(pcmFormat) + { + case MV_PCM_FORMAT_ALAW: + case MV_PCM_FORMAT_ULAW: + case MV_PCM_FORMAT_LINEAR: + reg33 = (0x20 | (pcmFormat << 3)); + mvDaaDirectRegWrite(lineId, 33, reg33); + break; + default: + mvOsPrintf("Error, wrong pcm format(%d)\n", pcmFormat); + break; + } + + /* Enable full wave rectifier */ + mvDaaDirectRegWrite(lineId, DAA_INTERNATIONAL_CONTROL_3, DAA_RFWE); + + /* Disable interrupts */ + mvDaaIntDisable(lineId); + + /* Set AOUT/INT pin as hardware interrupt */ + reg2 = mvDaaDirectRegRead(lineId, DAA_CONTROL_2_REG); + mvDaaDirectRegWrite(lineId, DAA_CONTROL_2_REG, (reg2 | DAA_INTE)); + + /* Enable ISO-Cap */ + mvDaaDirectRegWrite(lineId, DAA_DAA_CONTROL_2, 0); + + /* Wait 2000ms for ISO-cap to come up */ + newDelay = 2000; + while(newDelay > 0 && !(mvDaaDirectRegRead(lineId, DAA_SYSTEM_AND_LINE_SIDE_REV_REG) & 0xf0)) + { + mvOsDelay(100); + newDelay -= 100; + } + + lineSideId = mvDaaDirectRegRead(lineId, DAA_SYSTEM_AND_LINE_SIDE_REV_REG); + + if (!(lineSideId & 0xf0)) + { + mvOsPrintf("Error: DAA did not bring up ISO link properly!\n"); + return 1; + } + + /* Perform ADC manual calibration */ + mvDaaCalibrate(lineId); + + /* Enable Ring Validation */ + reg24 = mvDaaDirectRegRead(lineId, DAA_RING_VALIDATION_CONTROL_3); + + mvDaaDirectRegWrite(lineId, DAA_RING_VALIDATION_CONTROL_3 , reg24 | DAA_RNGV); + + + /* Print DAA info */ + mvDaaPrintInfo(lineId); + + MV_TRC_REC("ISO-Cap is now up, line side: %02x rev %02x\n", + mvDaaDirectRegRead(lineId, 11) >> 4, + ( mvDaaDirectRegRead(lineId, 13) >> 2) & 0xf); + + + /* raise tx gain by 7 dB for NEWZEALAND */ + if (!strcmp(daaModes[COUNTRY_INDEX].name, "NEWZEALAND")) + { + MV_TRC_REC("Adjusting gain\n"); + mvDaaDirectRegWrite(lineId, 38, 0x7); + } + /* enable interrupts */ + mvDaaIntEnable(lineId); + + /* Goto next DAA module */ + pDaaLineInfo++; + } + + mvOsPrintf("Done\n"); + MV_TRC_REC("<-%s\n", __FUNCTION__); + + return MV_OK; +} + +static void mvDaaIntEnable(unsigned int lineId) +{ + MV_TRC_REC("enable daa-%d interrupts\n", lineId); + + /* first, clear source register */ + mvDaaDirectRegWrite(lineId, DAA_INTERRUPT_SOURCE_REG, 0); + /* enable interrupts in mask register */ + mvDaaDirectRegWrite(lineId, DAA_INTERRUPT_MASK_REG, (DAA_DODM | DAA_RDTM)); +} + +static void mvDaaIntDisable(unsigned int lineId) +{ + MV_TRC_REC("disable daa-%d interrupts\n", lineId); + mvDaaDirectRegWrite(lineId, DAA_INTERRUPT_MASK_REG, 0); +} + +static void mvDaaPcmStartCountRegsSet(unsigned int lineId) +{ + MV_DAA_LINE_INFO *pDaaLineInfo = (MV_DAA_LINE_INFO*)(daaLineInfo + lineId); + mvDaaDirectRegWrite(lineId, 34 , pDaaLineInfo->txSample&0xff); + mvDaaDirectRegWrite(lineId, 35 , (pDaaLineInfo->txSample>>8)&0x3); + mvDaaDirectRegWrite(lineId, 36 , pDaaLineInfo->rxSample&0xff); + mvDaaDirectRegWrite(lineId, 37 , (pDaaLineInfo->rxSample>>8)&0x3); + +} + +static int mvDaaIntCheck(unsigned int lineId) +{ + unsigned char cause , mask, control, cause_and_mask; + MV_DAA_LINE_INFO *pDaaLineInfo = (MV_DAA_LINE_INFO*)(daaLineInfo + lineId); + + cause = mvDaaDirectRegRead(lineId, DAA_INTERRUPT_SOURCE_REG); + mask = mvDaaDirectRegRead(lineId, DAA_INTERRUPT_MASK_REG); + cause_and_mask = cause & mask; + + /* check ring */ + if(cause_and_mask & DAA_RDTI) + { + MV_TRC_REC("Ring Detected\n"); + pDaaLineInfo->ring = 1; + mvDaaDirectRegWrite(lineId, DAA_INTERRUPT_MASK_REG, (mask & ~DAA_POLM)); + control = mvDaaDirectRegRead(lineId, DAA_DAA_CONTROL_2); + mvDaaDirectRegWrite(lineId, DAA_DAA_CONTROL_2, (control & (~DAA_PDL))); + } + + /* check parallel phone detection */ + if(cause_and_mask & DAA_DODI) + { + MV_TRC_REC("Drop Out Detected\n"); + pDaaLineInfo->drop_out = 1; + control = mvDaaDirectRegRead(lineId, DAA_DAA_CONTROL_2); + mvDaaDirectRegWrite(lineId, DAA_DAA_CONTROL_2, (control & (~DAA_PDL))); + } + /* check reverse polarity */ + if(cause_and_mask & DAA_POLI) + { + MV_TRC_REC("Reverse Polarity Detected\n"); + pDaaLineInfo->reverse_polarity = 1; + } + + /* clear interrupts */ + mvDaaDirectRegWrite(lineId, DAA_INTERRUPT_SOURCE_REG, (~cause_and_mask)); + + + if(cause_and_mask) + return 1; + else + return 0; +} + +unsigned int mvDaaIntGet(unsigned short lineId) +{ + unsigned char event = 0; + + if(!mvDaaIntCheck(lineId)) + return 0; + + mvDaaEventGet(&event, lineId); + + return event; +} + +void mvDaaPstnStateSet(mv_hook_t hookstate, unsigned short lineId) +{ + MV_DAA_LINE_INFO *pDaaLineInfo = (MV_DAA_LINE_INFO*)(daaLineInfo + lineId); + unsigned char reg3, reg5; + + if(hookstate == MV_OFF_HOOK) + { + /* Set OFFHOOK */ + MV_TRC_REC("DAA goes off-hook\n"); + reg5 = mvDaaDirectRegRead(lineId, DAA_DAA_CONTROL_1); + mvDaaDirectRegWrite(lineId, DAA_DAA_CONTROL_1,(reg5 | DAA_OH)); + pDaaLineInfo->hook = 1; + } + else if(hookstate == MV_ON_HOOK) + { + MV_TRC_REC("DAA goes on-hook\n"); + /* First disable Drop Out interrupt */ + reg3 = mvDaaDirectRegRead(lineId, DAA_INTERRUPT_MASK_REG); + mvDaaDirectRegWrite(lineId, DAA_INTERRUPT_MASK_REG, (reg3 & ~DAA_DODM)); + /* Set ONHOOK */ + reg5 = mvDaaDirectRegRead(lineId, DAA_DAA_CONTROL_1); + mvDaaDirectRegWrite(lineId, DAA_DAA_CONTROL_1, (reg5 & ~DAA_OH)); + /* Enable Drop Out interrupt */ + mvDaaDirectRegWrite(lineId, DAA_INTERRUPT_MASK_REG, reg3); + pDaaLineInfo->hook = 0; + } + else + mvOsPrintf("Unknown PSTN state\n"); +} + +static void mvDaaCalibrate(unsigned int lineId) +{ + unsigned char reg17; + + DBG("Start ADC calibration\n"); + + /* Set CALD bit */ + reg17 = mvDaaDirectRegRead(lineId, DAA_INTERNATIONAL_CONTROL_2); + mvDaaDirectRegWrite(lineId, DAA_INTERNATIONAL_CONTROL_2, (reg17 | DAA_CALD)); + + /* Set MCAL bit */ + reg17 = mvDaaDirectRegRead(lineId, DAA_INTERNATIONAL_CONTROL_2); + mvDaaDirectRegWrite(lineId, DAA_INTERNATIONAL_CONTROL_2, (reg17 | DAA_MCAL)); + + /* Reset MCAL bit - start ADC calibration */ + reg17 = mvDaaDirectRegRead(lineId, DAA_INTERNATIONAL_CONTROL_2); + mvDaaDirectRegWrite(lineId, DAA_INTERNATIONAL_CONTROL_2, (reg17 & ~DAA_MCAL)); + + /* Must wait at least 256 ms */ + mvOsDelay(256); + + DBG("ADC calibration completed\n"); +} + +void mvDaaCidStateSet(cid_state_t cid_state, unsigned short lineId) +{ + unsigned char reg5; + + if(cid_state == CID_ON) + { + /* Enable on-hook line monitor */ + mvDaaDirectRegWrite(lineId, DAA_DAA_CONTROL_1, DAA_ONHM); + } + else if(cid_state == CID_OFF) + { + reg5 = mvDaaDirectRegRead(lineId, DAA_DAA_CONTROL_1); + mvDaaDirectRegWrite(lineId, DAA_DAA_CONTROL_1,(reg5 & ~DAA_ONHM)); + } + else + mvOsPrintf("%s: Unknown CID state\n",__FUNCTION__); + +} + +void mvDaaReversePolaritySet(long enable, unsigned int lineId) +{ + unsigned char mask; + + if(enable) + { + mask = mvDaaDirectRegRead(lineId, DAA_INTERRUPT_MASK_REG); + mvDaaDirectRegWrite(lineId, DAA_INTERRUPT_MASK_REG, (mask | DAA_POLM)); + } + else + { + mask = mvDaaDirectRegRead(lineId, DAA_INTERRUPT_MASK_REG); + mvDaaDirectRegWrite(lineId, DAA_INTERRUPT_MASK_REG, (mask & ~DAA_POLM)); + + } + +} + +void mvDaaEventGet(unsigned char *eventType, unsigned int lineId) +{ + MV_DAA_LINE_INFO *pDaaLineInfo = (MV_DAA_LINE_INFO*)(daaLineInfo + lineId); + + if(pDaaLineInfo->ring) + { + *eventType |= DAA_RDTI; + pDaaLineInfo->ring = 0; + } + + if(pDaaLineInfo->reverse_polarity) + { + *eventType |= DAA_POLI; + pDaaLineInfo->reverse_polarity = 0; + } + + if(pDaaLineInfo->drop_out) + { + *eventType |= DAA_DODI; + pDaaLineInfo->drop_out = 0; + } + + return; +} + + +static void mvDaaDigitalHybridSet(unsigned int index, unsigned int lineId) +{ + unsigned char reg16 = 0, reg26 = 0, reg30 = 0, reg31 = 0; + + /* Set On-hook speed, Ringer impedence, and ringer threshold */ + reg16 |= (daaModes[index].ohs << 6); + reg16 |= (daaModes[index].rz << 1); + reg16 |= (daaModes[index].rt); + mvDaaDirectRegWrite(lineId, 16, reg16); + + /* Set DC Termination: + Tip/Ring voltage adjust, minimum operational current, current limitation */ + reg26 |= (daaModes[index].dcv << 6); + reg26 |= (daaModes[index].mini << 4); + reg26 |= (daaModes[index].ilim << 1); + mvDaaDirectRegWrite(lineId, 26, reg26); + + /* Set AC Impedence */ + reg30 = (daaModes[index].acim); + mvDaaDirectRegWrite(lineId, 30, reg30); + + /* Misc. DAA parameters */ + reg31 = 0xa3; + reg31 |= (daaModes[index].ohs2 << 3); + mvDaaDirectRegWrite(lineId, 31, reg31); + +} + + +int mvDaaLineVoltageGet(unsigned int lineId) +{ + return (int)(mvDaaDirectRegRead(lineId, DAA_LINE_VOLTAGE_STATUS)); + +} + +void mvDaaRelease(void) +{ + if(daaLineInfo) + mvOsFree(daaLineInfo); +} + +void mvDaaRegsDump(unsigned int lineId) +{ + int i; + + for(i=1; i < NUM_OF_REGS; i++) + MV_TRC_REC("Register %d: 0x%x\n",i, mvDaaDirectRegRead(lineId, i)); +} + diff --git a/board/mv_feroceon/mv_hal/voiceband/daa/daa.h b/board/mv_feroceon/mv_hal/voiceband/daa/daa.h new file mode 100644 index 0000000..1cfa18d --- /dev/null +++ b/board/mv_feroceon/mv_hal/voiceband/daa/daa.h @@ -0,0 +1,91 @@ +/************************************ DAA.H *************************************************/ +#ifndef _DAA_H_ +#define _DAA_H_ + +#include "voiceband/voiceband.h" + +/* Defines */ +/* General */ +#define PSTN_ON_HOOK 0 +#define PSTN_OFF_HOOK 1 + +/* Registers */ +#define DAA_CONTROL_1_REG 1 +#define DAA_CONTROL_2_REG 2 +#define DAA_INTERRUPT_MASK_REG 3 +#define DAA_INTERRUPT_SOURCE_REG 4 +#define DAA_DAA_CONTROL_1 5 +#define DAA_DAA_CONTROL_2 6 +#define DAA_CONTROL_3_REG 10 +#define DAA_SYSTEM_AND_LINE_SIDE_REV_REG 11 +#define DAA_INTERNATIONAL_CONTROL_2 17 +#define DAA_INTERNATIONAL_CONTROL_3 18 +#define DAA_RING_VALIDATION_CONTROL_3 24 +#define DAA_LINE_VOLTAGE_STATUS 29 + +/* Bits */ +/* Register 11*/ +#define DAA_SYSTEM_SIDE_REVISION_MASK 0xF +#define DAA_LINE_SIDE_ID_MASK 0xF0 +#define DAA_SYSTEM_SIDE_REV_A 0 +#define DAA_SYSTEM_SIDE_REV_B 0x2 +#define DAA_SYSTEM_SIDE_REV_C 0x3 +#define DAA_SYSTEM_SIDE_REV_D 0x4 +#define DAA_SI3018 0x10 +#define DAA_SI3019 0x30 + +/* Register 2 */ +#define DAA_INTE 1 << 7 +#define DAA_INTP 1 << 6 + +/* Register 3 */ +#define DAA_POLM 1 << 0 +#define DAA_DODM 1 << 3 +#define DAA_RDTM 1 << 7 + +/* Register 4 */ +#define DAA_POLI 1 << 0 +#define DAA_DODI 1 << 3 +#define DAA_RDTI 1 << 7 + +/* Register 5 */ +#define DAA_ONHM 1 << 3 +#define DAA_OH 1 << 0 +#define DAA_RDT 1 << 2 +#define DAA_RDTP 1 << 5 +#define DAA_RDTN 1 << 6 + +/* Register 6 */ +#define DAA_PDL 1 << 4 + +/* Register 17 */ +#define DAA_CALD 1 << 5 +#define DAA_MCAL 1 << 6 + +/* Register 18 */ +#define DAA_RFWE 1 << 1 + +/* Register 24 */ +#define DAA_RNGV 1 << 7 + +/* Enumerators */ +typedef enum { + CID_OFF = 0, + CID_ON +} cid_state_t; + + +/* APIs */ +MV_STATUS mvDaaInit(unsigned short first, unsigned short last, unsigned short pSlotInfo[][2], + unsigned short lines, mv_band_mode_t bandMode, mv_pcm_format_t pcmFormat); +void mvDaaCidStateSet(cid_state_t cid_state, unsigned short lineId); +void mvDaaRegsDump(unsigned int lineId); +void mvDaaPstnStateSet(mv_hook_t hookstate, unsigned short lineId); +void mvDaaEventGet(unsigned char *eventType, unsigned int lineId); +void mvDaaRelease(void); +unsigned int mvDaaIntGet(unsigned short lineId); +void mvDaaReversePolaritySet(long enable, unsigned int lineId); +int mvDaaLineVoltageGet(unsigned int lineId); + + +#endif /*_DAA_H_*/ diff --git a/board/mv_feroceon/mv_hal/voiceband/mvCompVer.txt b/board/mv_feroceon/mv_hal/voiceband/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/board/mv_feroceon/mv_hal/voiceband/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_hal/voiceband/slic/proslic.c b/board/mv_feroceon/mv_hal/voiceband/slic/proslic.c new file mode 100644 index 0000000..ac1a1b1 --- /dev/null +++ b/board/mv_feroceon/mv_hal/voiceband/slic/proslic.c @@ -0,0 +1,1559 @@ + +#include "voiceband/slic/proslic.h" +#include "voiceband/tdm/mvTdm.h" + +#undef DEBUG +#ifdef DEBUG +#define DBG(fmt, arg...) mvOsPrintf(KERN_INFO fmt, ##arg) +#else +#define DBG(fmt, arg...) +#endif + +/* Static APIs */ +static unsigned char mvSlicFamily(unsigned int lineId); +static int mvSlicStart(unsigned int lineId); +static void mvSlicStart2(unsigned int lineId); +static void mvSlicGoActive(unsigned int lineId); +static int mvSlicCalibrate(unsigned int lineId); +static unsigned char mvSlicPowerUp(unsigned int lineId); +static void mvSlicInitializeDirectRegisters(unsigned int lineId); +static void mvSlicClearInterrupts(unsigned int lineId); +static void mvSlicEnablePCMhighway(unsigned int lineId); +static void mvSlicDisableOscillators(unsigned int lineId); +static void mvSlicInitializeIndirectRegisters(unsigned int lineId); +#ifdef DEBUG +static int mvSlicVerifyIndirectRegisters(unsigned int lineId); +#endif +static unsigned char mvSlicDirectRegRead(unsigned int lineId, unsigned char address); +static void mvSlicDirectRegWrite(unsigned int lineId, unsigned char address, unsigned char data); +static void mvSlicIndirectRegWrite(unsigned int lineId, unsigned char address, unsigned short data); +static unsigned short mvSlicIndirectRegRead(unsigned int lineId, unsigned char address); +static void mvSlicManualCalibrate(unsigned int lineId); +static void mvSlicClearAlarmBits(unsigned int lineId); +static unsigned char mvSlicChipType (unsigned int lineId); +static unsigned char mvSlicLoopStatus(unsigned int lineId); +static unsigned char mvSlicVersion(unsigned int lineId); +#ifdef SLIC_TEST_LOOPSTATUS_AND_DIGIT_DETECTION +static unsigned char mvSlicDigit(unsigned int lineId); +#endif +static void mvSlicPrintFreqRevision(unsigned int lineId); +static MV_STATUS mvSlicPrintInfo(unsigned int lineId); +static void mvSlicIntEnable(unsigned int lineId); +static void mvSlicIntDisable(unsigned int lineId); +static void mvSlicPcmFormatSet(unsigned int lineId, mv_pcm_format_t pcmFormat); +static int mvSlicDaisyChainGet(unsigned int lineId); +static void mvSlicPcmStartCountRegsSet(unsigned int lineId); +static int mvSlicIntCheck(unsigned int lineId); + +char * exceptionStrings[] = +{ "ProSLIC not communicating", + "Time out durring Power Up", + "Time out durring Power Down", + "Power is Leaking; might be a short", + "Tip or Ring Ground Short", + "Too Many Q1 Power Alarms", + "Too Many Q2 Power Alarms", + "Too Many Q3 Power Alarms", + "Too Many Q4 Power Alarms", + "Too Many Q5 Power Alarms", + "Too Many Q6 Power Alarms" +}; + +typedef struct { + unsigned int lineId; + unsigned short txSample; + unsigned short rxSample; +}MV_SLIC_LINE_INFO; + +static MV_SLIC_LINE_INFO *slicLineInfo = NULL; +static int totalSLICs = 0; +static unsigned char spiMode; +static mv_band_mode_t mvBandMode; +static mv_pcm_format_t mvPcmFormat; +static unsigned short firstSlic = 0; +static unsigned short lastSlic = 0; +static int calibrated = 0; + +void exception (enum exceptions e) +{ + mvOsPrintf( "\n\tE X C E P T I O N: %s\n",exceptionStrings[e] ); + mvOsPrintf( " SLIC Interface Error\n"); +} + + +int Si3215_Flag = 0; +int TestForSi3215(unsigned int lineId) +{ + return ((mvSlicDirectRegRead(lineId, 1) & 0x80)==0x80); +} + +static unsigned char mvSlicDirectRegRead(unsigned int lineId, unsigned char address) +{ + unsigned char data; + + mvVbSpiRead(lineId, address, MV_LINE_FXS, &data); + return data; +} + +static void mvSlicDirectRegWrite(unsigned int lineId, unsigned char address, unsigned char data) +{ + mvVbSpiWrite(lineId, address, MV_LINE_FXS, data); +} + +static void waitForIndirectReg(unsigned int lineId) +{ + while(mvSlicDirectRegRead(lineId, I_STATUS)); + if(mvBoardIdGet() == RD_88F6281A_ID) + mvOsDelay(10); +} + +static unsigned short mvSlicIndirectRegRead(unsigned int lineId, unsigned char address) +{ + unsigned short res; + + if (Si3215_Flag) + { + /* + ** re-map the indirect registers for Si3215. + */ + if (address < 13 ) return 0; + if ((address >= 13) && (address <= 40)) + address -= 13; + else if ((address == 41) || (address == 43)) + address += 23; + else if ((address >= 99) && (address <= 104)) + address -= 30; + } + + mvSlicDirectRegWrite(lineId, IAA,address); + waitForIndirectReg(lineId); + res = ( mvSlicDirectRegRead(lineId, IDA_LO) | (mvSlicDirectRegRead (lineId, IDA_HI))<<8); + waitForIndirectReg(lineId); + return res; +} + +static void mvSlicIndirectRegWrite(unsigned int lineId, unsigned char address, unsigned short data) +{ + + if (Si3215_Flag) + { + /* + ** re-map the indirect registers for Si3215. + */ + if (address < 13 ) return; + if ((address >= 13) && (address <= 40)) + address -= 13; + else if ((address == 41) || (address == 43)) + address += 23; + else if ((address >= 99) && (address <= 104)) + address -= 30; + } + + mvSlicDirectRegWrite(lineId, IDA_LO,(unsigned char)(data & 0xFF)); + mvSlicDirectRegWrite(lineId, IDA_HI,(unsigned char)((data & 0xFF00)>>8)); + mvSlicDirectRegWrite(lineId, IAA,address); + waitForIndirectReg(lineId); +} + + +/* +The following Array contains: +*/ +indirectRegister indirectRegisters[] = +{ +/* Reg# Label Initial Value */ + +{ 0, "DTMF_ROW_0_PEAK", 0x55C2 }, +{ 1, "DTMF_ROW_1_PEAK", 0x51E6 }, +{ 2, "DTMF_ROW2_PEAK", 0x4B85 }, +{ 3, "DTMF_ROW3_PEAK", 0x4937 }, +{ 4, "DTMF_COL1_PEAK", 0x3333 }, +{ 5, "DTMF_FWD_TWIST", 0x0202 }, +{ 6, "DTMF_RVS_TWIST", 0x0202 }, +{ 7, "DTMF_ROW_RATIO", 0x0198 }, +{ 8, "DTMF_COL_RATIO", 0x0198 }, +{ 9, "DTMF_ROW_2ND_ARM", 0x0611 }, +{ 10, "DTMF_COL_2ND_ARM", 0x0202 }, +{ 11, "DTMF_PWR_MIN_", 0x00E5 }, +{ 12, "DTMF_OT_LIM_TRES", 0x0A1C }, +{ 13, "OSC1_COEF", 0x7b30 }, +{ 14, "OSC1X", 0x0063 }, +{ 15, "OSC1Y", 0x0000 }, +{ 16, "OSC2_COEF", 0x7870 }, +{ 17, "OSC2X", 0x007d }, +{ 18, "OSC2Y", 0x0000 }, +{ 19, "RING_V_OFF", 0x0000 }, +{ 20, "RING_OSC", 0x7EF0 }, +{ 21, "RING_X", 0x0160 }, +{ 22, "RING_Y", 0x0000 }, +{ 23, "PULSE_ENVEL", 0x2000 }, +{ 24, "PULSE_X", 0x2000 }, +{ 25, "PULSE_Y", 0x0000 }, +{ 26, "RECV_DIGITAL_GAIN",0x4000 }, +{ 27, "XMIT_DIGITAL_GAIN",0x4000 }, +{ 28, "LOOP_CLOSE_TRES", 0x1000 }, +{ 29, "RING_TRIP_TRES", 0x3600 }, +{ 30, "COMMON_MIN_TRES", 0x1000 }, +{ 31, "COMMON_MAX_TRES", 0x0200 }, +{ 32, "PWR_ALARM_Q1Q2", 0x7c0 }, +{ 33, "PWR_ALARM_Q3Q4", 0x2600 }, +{ 34, "PWR_ALARM_Q5Q6", 0x1B80 }, +{ 35, "LOOP_CLSRE_FlTER", 0x8000 }, +{ 36, "RING_TRIP_FILTER", 0x0320 }, +{ 37, "TERM_LP_POLE_Q1Q2",0x08c }, +{ 38, "TERM_LP_POLE_Q3Q4",0x0100 }, +{ 39, "TERM_LP_POLE_Q5Q6",0x0010 }, +{ 40, "CM_BIAS_RINGING", 0x0C00 }, +{ 41, "DCDC_MIN_V", 0x0C00 }, +{ 43, "LOOP_CLOSE_TRES Low", 0x1000 }, +{ 99, "FSK 0 FREQ PARAM", 0x00DA }, +{ 100,"FSK 0 AMPL PARAM", 0x6B60 }, +{ 101,"FSK 1 FREQ PARAM", 0x0074 }, +{ 102,"FSK 1 AMPl PARAM", 0x79C0 }, +{ 103,"FSK 0to1 SCALER", 0x1120 }, +{ 104,"FSK 1to0 SCALER", 0x3BE0 }, +{ 97, "RCV_FLTR", 0}, +{ 0,"",0}, +}; + + +void mvSlicStopTone(unsigned int lineId) +{ + mvSlicDirectRegWrite(lineId, 32, INIT_DR32 );//0x00 Oper. Oscillator 1 Controltone generation + mvSlicDirectRegWrite(lineId, 33, INIT_DR33 );//0x00 Oper. Oscillator 2 Controltone generation + + mvSlicIndirectRegWrite(lineId, 13,INIT_IR13); + mvSlicIndirectRegWrite(lineId, 14,INIT_IR14); + mvSlicIndirectRegWrite(lineId, 16,INIT_IR16); + mvSlicIndirectRegWrite(lineId, 17,INIT_IR17); + mvSlicDirectRegWrite(lineId, 36, INIT_DR36); + mvSlicDirectRegWrite(lineId, 37, INIT_DR37); + mvSlicDirectRegWrite(lineId, 38, INIT_DR38); + mvSlicDirectRegWrite(lineId, 39, INIT_DR39); + mvSlicDirectRegWrite(lineId, 40, INIT_DR40); + mvSlicDirectRegWrite(lineId, 41, INIT_DR41); + mvSlicDirectRegWrite(lineId, 42, INIT_DR42); + mvSlicDirectRegWrite(lineId, 43, INIT_DR43); + +// mvSlicDirectRegWrite(lineId, 32, INIT_DR32 );//0x00 Oper. Oscillator 1 Controltone generation +// mvSlicDirectRegWrite(lineId, 33, INIT_DR33 );//0x00 Oper. Oscillator 2 Controltone generation +} + +void genTone(tone_struct tone, unsigned int lineId) +{ + // Uber function to extract values for oscillators from tone_struct + // place them in the registers, and enable the oscillators. + unsigned char osc1_ontimer_enable=0, osc1_offtimer_enable=0,osc2_ontimer_enable=0,osc2_offtimer_enable=0; + int enable_osc2=0; + + //loopBackOff(); + mvSlicDisableOscillators(lineId); // Make sure the oscillators are not already on. + + if (tone.osc1.coeff == 0 || tone.osc1.x == 0) { + // Error! + mvOsPrintf("You passed me a invalid struct!\n"); + return; + } + // Setup osc 1 + mvSlicIndirectRegWrite(lineId, OSC1_COEF, tone.osc1.coeff); + mvSlicIndirectRegWrite(lineId, OSC1X, tone.osc1.x); + mvSlicIndirectRegWrite(lineId, OSC1Y, tone.osc1.y); + //mvOsPrintf("OUt-> 0x%04x\n",tone.osc1.coeff); + // Active Timer + + + if (tone.osc1.on_hi_byte != 0) { + mvSlicDirectRegWrite(lineId, OSC1_ON__LO, tone.osc1.on_low_byte); + mvSlicDirectRegWrite(lineId, OSC1_ON_HI, tone.osc1.on_hi_byte); + osc1_ontimer_enable = 0x10; + } + // Inactive Timer + if (tone.osc1.off_hi_byte != 0) { + mvSlicDirectRegWrite(lineId, OSC1_OFF_LO, tone.osc1.off_low_byte); + mvSlicDirectRegWrite(lineId, OSC1_OFF_HI, tone.osc1.off_hi_byte); + osc1_offtimer_enable = 0x08; + } + + if (tone.osc2.coeff != 0) { + // Setup OSC 2 + mvSlicIndirectRegWrite(lineId, OSC2_COEF, tone.osc2.coeff); + mvSlicIndirectRegWrite(lineId, OSC2X, tone.osc2.x); + mvSlicIndirectRegWrite(lineId, OSC2Y, tone.osc2.y); + + // Active Timer + if (tone.osc1.on_hi_byte != 0) { + mvSlicDirectRegWrite(lineId, OSC2_ON__LO, tone.osc2.on_low_byte); + mvSlicDirectRegWrite(lineId, OSC2_ON_HI, tone.osc2.on_hi_byte); + osc2_ontimer_enable = 0x10; + } + // Inactive Timer + if (tone.osc1.off_hi_byte != 0) { + mvSlicDirectRegWrite(lineId, OSC2_OFF_LO, tone.osc2.off_low_byte); + mvSlicDirectRegWrite(lineId, OSC2_OFF_HI, tone.osc2.off_hi_byte); + osc2_offtimer_enable = 0x08; + } + enable_osc2 = 1; + } + + mvSlicDirectRegWrite(lineId, OSC1, (unsigned char)(0x06 | osc1_ontimer_enable | osc1_offtimer_enable)); + if (enable_osc2) + mvSlicDirectRegWrite(lineId, OSC2, (unsigned char)(0x06 | osc2_ontimer_enable | osc2_offtimer_enable)); + return; +} + + +void mvSlicDialTone(unsigned int lineId) +{ + if (Si3215_Flag) + { + mvSlicIndirectRegWrite(lineId, 13,SI3215_DIALTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3215_DIALTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3215_DIALTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3215_DIALTONE_IR17); + } + else + { + mvSlicIndirectRegWrite(lineId, 13,SI3210_DIALTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3210_DIALTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3210_DIALTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3210_DIALTONE_IR17); + } + + mvSlicDirectRegWrite(lineId, 36, DIALTONE_DR36); + mvSlicDirectRegWrite(lineId, 37, DIALTONE_DR37); + mvSlicDirectRegWrite(lineId, 38, DIALTONE_DR38); + mvSlicDirectRegWrite(lineId, 39, DIALTONE_DR39); + mvSlicDirectRegWrite(lineId, 40, DIALTONE_DR40); + mvSlicDirectRegWrite(lineId, 41, DIALTONE_DR41); + mvSlicDirectRegWrite(lineId, 42, DIALTONE_DR42); + mvSlicDirectRegWrite(lineId, 43, DIALTONE_DR43); + + mvSlicDirectRegWrite(lineId, 32, DIALTONE_DR32); + mvSlicDirectRegWrite(lineId, 33, DIALTONE_DR33); +} + + +void mvSlicBusyTone(unsigned int lineId) +{ + if (Si3215_Flag) + { + mvSlicIndirectRegWrite(lineId, 13,SI3215_BUSYTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3215_BUSYTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3215_BUSYTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3215_BUSYTONE_IR17); + } + else + { + mvSlicIndirectRegWrite(lineId, 13,SI3210_BUSYTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3210_BUSYTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3210_BUSYTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3210_BUSYTONE_IR17); + } + mvSlicDirectRegWrite(lineId, 36, BUSYTONE_DR36); + mvSlicDirectRegWrite(lineId, 37, BUSYTONE_DR37); + mvSlicDirectRegWrite(lineId, 38, BUSYTONE_DR38); + mvSlicDirectRegWrite(lineId, 39, BUSYTONE_DR39); + mvSlicDirectRegWrite(lineId, 40, BUSYTONE_DR40); + mvSlicDirectRegWrite(lineId, 41, BUSYTONE_DR41); + mvSlicDirectRegWrite(lineId, 42, BUSYTONE_DR42); + mvSlicDirectRegWrite(lineId, 43, BUSYTONE_DR43); + + mvSlicDirectRegWrite(lineId, 32, BUSYTONE_DR32); + mvSlicDirectRegWrite(lineId, 33, BUSYTONE_DR33); +} + +void mvSlicReorderTone(unsigned int lineId) +{ + if (Si3215_Flag) + { + mvSlicIndirectRegWrite(lineId, 13,SI3215_REORDERTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3215_REORDERTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3215_REORDERTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3215_REORDERTONE_IR17); + } + else { + mvSlicIndirectRegWrite(lineId, 13,SI3210_REORDERTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3210_REORDERTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3210_REORDERTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3210_REORDERTONE_IR17); + } + + mvSlicDirectRegWrite(lineId, 36, REORDERTONE_DR36); + mvSlicDirectRegWrite(lineId, 37, REORDERTONE_DR37); + mvSlicDirectRegWrite(lineId, 38, REORDERTONE_DR38); + mvSlicDirectRegWrite(lineId, 39, REORDERTONE_DR39); + mvSlicDirectRegWrite(lineId, 40, REORDERTONE_DR40); + mvSlicDirectRegWrite(lineId, 41, REORDERTONE_DR41); + mvSlicDirectRegWrite(lineId, 42, REORDERTONE_DR42); + mvSlicDirectRegWrite(lineId, 43, REORDERTONE_DR43); + + mvSlicDirectRegWrite(lineId, 32, REORDERTONE_DR32); + mvSlicDirectRegWrite(lineId, 33, REORDERTONE_DR33); + +} + +void mvSlicCongestionTone(unsigned int lineId) +{ + if (Si3215_Flag) + { + mvSlicIndirectRegWrite(lineId, 13,SI3215_CONGESTIONTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3215_CONGESTIONTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3215_CONGESTIONTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3215_CONGESTIONTONE_IR17); + } + else { + mvSlicIndirectRegWrite(lineId, 13,SI3210_CONGESTIONTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3210_CONGESTIONTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3210_CONGESTIONTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3210_CONGESTIONTONE_IR17); + } + + mvSlicDirectRegWrite(lineId, 36, CONGESTIONTONE_DR36); + mvSlicDirectRegWrite(lineId, 37, CONGESTIONTONE_DR37); + mvSlicDirectRegWrite(lineId, 38, CONGESTIONTONE_DR38); + mvSlicDirectRegWrite(lineId, 39, CONGESTIONTONE_DR39); + mvSlicDirectRegWrite(lineId, 40, CONGESTIONTONE_DR40); + mvSlicDirectRegWrite(lineId, 41, CONGESTIONTONE_DR41); + mvSlicDirectRegWrite(lineId, 42, CONGESTIONTONE_DR42); + mvSlicDirectRegWrite(lineId, 43, CONGESTIONTONE_DR43); + + mvSlicDirectRegWrite(lineId, 32, CONGESTIONTONE_DR32); + mvSlicDirectRegWrite(lineId, 33, CONGESTIONTONE_DR33); + +} + +void mvSlicRingbackPbxTone(unsigned int lineId) +{ + if (Si3215_Flag) + { + mvSlicIndirectRegWrite(lineId, 13,SI3215_RINGBACKPBXTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3215_RINGBACKPBXTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3215_RINGBACKPBXTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3215_RINGBACKPBXTONE_IR17); + } + else { + mvSlicIndirectRegWrite(lineId, 13,SI3210_RINGBACKPBXTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3210_RINGBACKPBXTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3210_RINGBACKPBXTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3210_RINGBACKPBXTONE_IR17); + } + + mvSlicDirectRegWrite(lineId, 36, RINGBACKPBXTONE_DR36); + mvSlicDirectRegWrite(lineId, 37, RINGBACKPBXTONE_DR37); + mvSlicDirectRegWrite(lineId, 38, RINGBACKPBXTONE_DR38); + mvSlicDirectRegWrite(lineId, 39, RINGBACKPBXTONE_DR39); + mvSlicDirectRegWrite(lineId, 40, RINGBACKPBXTONE_DR40); + mvSlicDirectRegWrite(lineId, 41, RINGBACKPBXTONE_DR41); + mvSlicDirectRegWrite(lineId, 42, RINGBACKPBXTONE_DR42); + mvSlicDirectRegWrite(lineId, 43, RINGBACKPBXTONE_DR43); + + mvSlicDirectRegWrite(lineId, 32, RINGBACKPBXTONE_DR32); + mvSlicDirectRegWrite(lineId, 33, RINGBACKPBXTONE_DR33); + +} + + +void mvSlicRingBackTone(unsigned int lineId) +{ + if (Si3215_Flag) + { + mvSlicIndirectRegWrite(lineId, 13,SI3215_RINGBACKTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3215_RINGBACKTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3215_RINGBACKTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3215_RINGBACKTONE_IR17); + } + else { + mvSlicIndirectRegWrite(lineId, 13,SI3210_RINGBACKTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3210_RINGBACKTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3210_RINGBACKTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3210_RINGBACKTONE_IR17); + } + + mvSlicDirectRegWrite(lineId, 36, RINGBACKTONE_DR36); + mvSlicDirectRegWrite(lineId, 37, RINGBACKTONE_DR37); + mvSlicDirectRegWrite(lineId, 38, RINGBACKTONE_DR38); + mvSlicDirectRegWrite(lineId, 39, RINGBACKTONE_DR39); + mvSlicDirectRegWrite(lineId, 40, RINGBACKTONE_DR40); + mvSlicDirectRegWrite(lineId, 41, RINGBACKTONE_DR41); + mvSlicDirectRegWrite(lineId, 42, RINGBACKTONE_DR42); + mvSlicDirectRegWrite(lineId, 43, RINGBACKTONE_DR43); + + mvSlicDirectRegWrite(lineId, 32, RINGBACKTONE_DR32); + mvSlicDirectRegWrite(lineId, 33, RINGBACKTONE_DR33); + +} + +void ringBackToneSi3216(unsigned int lineId) +{ + mvSlicIndirectRegWrite(lineId, 13,RINGBACKTONE_SI3216_IR13); + mvSlicIndirectRegWrite(lineId, 14,RINGBACKTONE_SI3216_IR14); + mvSlicIndirectRegWrite(lineId, 16,RINGBACKTONE_SI3216_IR16); + mvSlicIndirectRegWrite(lineId, 17,RINGBACKTONE_SI3216_IR17); + mvSlicDirectRegWrite(lineId, 36, RINGBACKTONE_SI3216_DR36); + mvSlicDirectRegWrite(lineId, 37, RINGBACKTONE_SI3216_DR37); + mvSlicDirectRegWrite(lineId, 38, RINGBACKTONE_SI3216_DR38); + mvSlicDirectRegWrite(lineId, 39, RINGBACKTONE_SI3216_DR39); + mvSlicDirectRegWrite(lineId, 40, RINGBACKTONE_SI3216_DR40); + mvSlicDirectRegWrite(lineId, 41, RINGBACKTONE_SI3216_DR41); + mvSlicDirectRegWrite(lineId, 42, RINGBACKTONE_SI3216_DR42); + mvSlicDirectRegWrite(lineId, 43, RINGBACKTONE_SI3216_DR43); + + mvSlicDirectRegWrite(lineId, 32, RINGBACKTONE_SI3216_DR32); + mvSlicDirectRegWrite(lineId, 33, RINGBACKTONE_SI3216_DR33); + +} + + +void mvSlicRingBackJapan(unsigned int lineId) +{ + if (Si3215_Flag) + { + mvSlicIndirectRegWrite(lineId, 13,SI3215_RINGBACKJAPANTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3215_RINGBACKJAPANTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3215_RINGBACKJAPANTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3215_RINGBACKJAPANTONE_IR17); + } + else { + mvSlicIndirectRegWrite(lineId, 13,SI3210_RINGBACKJAPANTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3210_RINGBACKJAPANTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3210_RINGBACKJAPANTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3210_RINGBACKJAPANTONE_IR17); + } + + mvSlicDirectRegWrite(lineId, 36, RINGBACKJAPANTONE_DR36); + mvSlicDirectRegWrite(lineId, 37, RINGBACKJAPANTONE_DR37); + mvSlicDirectRegWrite(lineId, 38, RINGBACKJAPANTONE_DR38); + mvSlicDirectRegWrite(lineId, 39, RINGBACKJAPANTONE_DR39); + mvSlicDirectRegWrite(lineId, 40, RINGBACKJAPANTONE_DR40); + mvSlicDirectRegWrite(lineId, 41, RINGBACKJAPANTONE_DR41); + mvSlicDirectRegWrite(lineId, 42, RINGBACKJAPANTONE_DR42); + mvSlicDirectRegWrite(lineId, 43, RINGBACKJAPANTONE_DR43); + + mvSlicDirectRegWrite(lineId, 32, RINGBACKJAPANTONE_DR32); + mvSlicDirectRegWrite(lineId, 33, RINGBACKJAPANTONE_DR33); + +} + + +void mvSlicBusyJapanTone(unsigned int lineId) +{ + if (Si3215_Flag) + { + mvSlicIndirectRegWrite(lineId, 13,SI3215_BUSYJAPANTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3215_BUSYJAPANTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3215_BUSYJAPANTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3215_BUSYJAPANTONE_IR17); + } + else { + mvSlicIndirectRegWrite(lineId, 13,SI3210_BUSYJAPANTONE_IR13); + mvSlicIndirectRegWrite(lineId, 14,SI3210_BUSYJAPANTONE_IR14); + mvSlicIndirectRegWrite(lineId, 16,SI3210_BUSYJAPANTONE_IR16); + mvSlicIndirectRegWrite(lineId, 17,SI3210_BUSYJAPANTONE_IR17); + } + + mvSlicDirectRegWrite(lineId, 36, BUSYJAPANTONE_DR36); + mvSlicDirectRegWrite(lineId, 37, BUSYJAPANTONE_DR37); + mvSlicDirectRegWrite(lineId, 38, BUSYJAPANTONE_DR38); + mvSlicDirectRegWrite(lineId, 39, BUSYJAPANTONE_DR39); + mvSlicDirectRegWrite(lineId, 40, BUSYJAPANTONE_DR40); + mvSlicDirectRegWrite(lineId, 41, BUSYJAPANTONE_DR41); + mvSlicDirectRegWrite(lineId, 42, BUSYJAPANTONE_DR42); + mvSlicDirectRegWrite(lineId, 43, BUSYJAPANTONE_DR43); + + mvSlicDirectRegWrite(lineId, 32, BUSYJAPANTONE_DR32); + mvSlicDirectRegWrite(lineId, 33, BUSYJAPANTONE_DR33); + +} + + +static unsigned char mvSlicPowerUp(unsigned int lineId) +{ + unsigned char vBat ; + int i=0; + + + if (mvSlicChipType(lineId) == 3) // M version correction + { + mvSlicDirectRegWrite(lineId, 92,INIT_SI3210M_DR92);// M version + mvSlicDirectRegWrite(lineId, 93,INIT_SI3210M_DR93);// M version + } + else + { + /* MA */ + mvSlicDirectRegWrite(lineId, 93, 12); + mvSlicDirectRegWrite(lineId, 92, 0xff); /* set the period of the DC-DC converter to 1/64 kHz START OUT SLOW*/ + + } + + mvSlicDirectRegWrite(lineId, 14, 0); /* Engage the DC-DC converter */ + + while ((vBat=mvSlicDirectRegRead(lineId, 82)) < 0xc0) + { + mvOsUDelay (100); + ++i; + if (i > 5000) return 0; + } + + if (mvSlicChipType(lineId) == 3) // M version correction + { + mvSlicDirectRegWrite(lineId, 92,0x80 +INIT_SI3210M_DR92);// M version + } + else + mvSlicDirectRegWrite(lineId, 93, 0x8c); /* DC-DC Calibration */ /* MA */ + + while(0x80 & mvSlicDirectRegRead(lineId, 93)); // Wait for DC-DC Calibration to complete + + return vBat; +} + +void xcalibrate(unsigned int lineId) +{ unsigned char i ; + + mvSlicDirectRegWrite(lineId, 97, 0x1e); /* Do all of the Calibarations */ + mvSlicDirectRegWrite(lineId, 96, 0x47); /* Start the calibration No Speed Up */ + + mvSlicManualCalibrate(lineId); + + mvSlicDirectRegWrite(lineId, 23,4); // enable interrupt for the balance Cal + mvSlicDirectRegWrite(lineId, 97,0x1); + mvSlicDirectRegWrite(lineId, 96,0x40); + + + while (mvSlicDirectRegRead(lineId, 96) != 0 ); + mvOsPrintf("\nCalibration Vector Registers 98 - 107: "); + + for (i=98; i < 107; i++) mvOsPrintf( "%X.", mvSlicDirectRegRead(lineId, i)); + mvOsPrintf("%X \n\n",mvSlicDirectRegRead(lineId, 107)); + +} + +static void mvSlicGoActive(unsigned int lineId) + +{ + mvSlicDirectRegWrite(lineId, 64,1); /* LOOP STATE REGISTER SET TO ACTIVE */ + /* Active works for on-hook and off-hook see spec. */ + /* The phone hook-switch sets the off-hook and on-hook substate*/ +} + + +static unsigned char mvSlicVersion(unsigned int lineId) +{ + return 0xf & mvSlicDirectRegRead(lineId, 0); +} + +static unsigned char mvSlicChipType (unsigned int lineId) +{ + return (0x30 & mvSlicDirectRegRead(lineId, 0)) >> 4; +} + +static unsigned char mvSlicFamily (unsigned int lineId) +{ + return (mvSlicDirectRegRead (lineId, 1) & 0x80); +} + +static int selfTest(unsigned int lineId) +{ + /* Begin Sanity check Optional */ + if (mvSlicDirectRegRead(lineId, 8) !=2) {exception(PROSLICiNSANE); return 0;} + if (mvSlicDirectRegRead(lineId, 64) !=0) {exception(PROSLICiNSANE); return 0;} + if (mvSlicDirectRegRead(lineId, 11) !=0x33) {exception(PROSLICiNSANE); return 0;} + /* End Sanity check */ + return 1; +} + +int mvSlicStart(unsigned int lineId) +{ + volatile unsigned char t,v; +#ifdef DEBUG + volatile unsigned short i; +#endif + + // Test if Si3210 or Si3215 is used. + Si3215_Flag = TestForSi3215(lineId); + + if (Si3215_Flag) + DBG("Proslic Si3215 Detected.\n"); + else + DBG("Proslic Si3210 detected.\n"); + + /* Another Quarter of a Second */ + if (!selfTest(lineId)) + { + mvOsPrintf("self test failed !!!\n"); + return 0; + } + + v = mvSlicVersion(lineId); + DBG("Si321x Version = %x\n", v); + + t = mvSlicChipType(lineId); + DBG("chip Type t=%d\n", t); + + mvSlicInitializeIndirectRegisters(lineId); +#ifdef DEBUG + i=mvSlicVerifyIndirectRegisters (lineId); + if (i != 0) { + mvOsPrintf ("verifyIndirect failed\n"); + return 0; + } +#endif + mvSlicDirectRegWrite (lineId, 8, 0); + if (v == 5) + mvSlicDirectRegWrite (lineId, 108, 0xeb); /* turn on Rev E features. */ + + + if ( t == 0 ) // Si3210 not the Si3211 or Si3212 + { + mvSlicDirectRegWrite(lineId, 67,0x17); // Make VBat switch not automatic + // The above is a saftey measure to prevent Q7 from accidentaly turning on and burning out. + // It works in combination with the statement below. Pin 34 DCDRV which is used for the battery switch on the + // Si3211 & Si3212 + + mvSlicDirectRegWrite(lineId, 66,1); // Q7 should be set to OFF for si3210 + } + + if (v <=2 ) { // REVISION B + mvSlicDirectRegWrite(lineId, 73,4); // set common mode voltage to 6 volts + } + + // PCm Start Count. + mvSlicDirectRegWrite (lineId, 2, 0); + mvSlicDirectRegWrite (lineId, 4, 0); + + + /* Do Flush durring powerUp and calibrate */ + if (t == 0 || t==3) // Si3210 + { + DBG("Powerup the Slic\n"); + + // Turn on the DC-DC converter and verify voltage. + if (!mvSlicPowerUp(lineId)) + return 0; + } + + mvSlicInitializeDirectRegisters(lineId); + + if (!mvSlicCalibrate(lineId)) { + mvOsPrintf("calibrate failed\n"); + return 0; + } + + + return 1; +} + +static void mvSlicStart2(unsigned int lineId) +{ + if(!calibrated) + { + /* Perform manual calibration anyway */ + mvSlicManualCalibrate (lineId); + calibrated = 1; + DBG("Caliberation done\n"); + } + + DBG("Register 98 = %x\n", mvSlicDirectRegRead(lineId, 98)); + DBG("Register 99 = %x\n", mvSlicDirectRegRead(lineId, 99)); + + DBG("Slic is Active\n"); + mvSlicGoActive(lineId); +} + +void mvSlicStopRinging(unsigned int lineId) +{ + + if ((0xf & mvSlicDirectRegRead(lineId, 0))<=2 ) // if REVISION B + mvSlicDirectRegWrite(lineId, 69,10); // Loop Debounce Register = initial value + + mvSlicGoActive(lineId); + +} + +#if 0 +static void mvSlicManualCalibrate(unsigned int lineId) +{ +unsigned char x,y,i,progress=0; // progress contains individual bits for the Tip and Ring Calibrations + + //Initialized DR 98 and 99 to get consistant results. + // 98 and 99 are the results registers and the search should have same intial conditions. + mvSlicDirectRegWrite(lineId, 98,0x10); // This is necessary if the calibration occurs other than at reset time + mvSlicDirectRegWrite(lineId, 99,0x10); + + for ( i=0x16; i>0; i--) + { + mvSlicDirectRegWrite(lineId, 98,i); + mvOsDelay(50); /* need to wait 40 ms according to An35 */ + if((mvSlicDirectRegRead(lineId, 88)) == 0) + { progress|=1; + x=i; + break; + } + } // for + + for ( i=0x16; i>0; i--) + { + mvSlicDirectRegWrite(lineId, 99,i); + mvOsDelay(50); /* need to wait 40 ms according to An35 */ + if((mvSlicDirectRegRead(lineId, 89)) == 0){ + progress|=2; + y=i; + break; + } + + }//for + + //return progress; +} +#endif +static void mvSlicManualCalibrate(unsigned int lineId) +{ + unsigned char i,sum = 0; + unsigned short line; + unsigned long progress = 0; + + for(line = firstSlic; line < (lastSlic+1); line++) + { + //Initialized DR 98 and 99 to get consistant results. + // 98 and 99 are the results registers and the search should have same intial conditions. + mvSlicDirectRegWrite(line, 98,0x10); // necessary if the calibration occurs other than at reset time + mvSlicDirectRegWrite(line, 99,0x10); + } + + + for ( i=0x16; i>0; i--) + { + if(sum == totalSLICs) + break; + + for(line = firstSlic; line < (lastSlic+1); line++) + { + if(!(progress & (1 << line))) + mvSlicDirectRegWrite(line, 98,i); + } + + mvOsDelay(40); /* need to wait 40 ms according to An35 */ + + for(line = firstSlic; line < (lastSlic+1); line++) + { + if(!(progress & (1 << line))) + { + if((mvSlicDirectRegRead(lineId, 88)) == 0) + { + progress |= (1 << line); + sum++; + } } + } + } // for + + + sum = 0; + + + for ( i=0x16; i>0; i--) + { + if(sum == totalSLICs) + break; + + for(line = firstSlic; line < (lastSlic+1); line++) + { + if(!(progress & (1 << line))) + mvSlicDirectRegWrite(line, 99,i); + } + + mvOsDelay(40); /* need to wait 40 ms according to An35 */ + + for(line = firstSlic; line < (lastSlic+1); line++) + { + if(!(progress & (1 << line))) + { + if((mvSlicDirectRegRead(lineId, 89)) == 0) + { + progress |= (1 << line); + sum++; + } } + } + } // for + + return; +} + +static void mvSlicClearAlarmBits(unsigned int lineId) +{ + mvSlicDirectRegWrite(lineId, 19,0xFC); //Clear Alarm bits +} + +void mvSlicActivateRinging(unsigned int lineId) +{ + mvSlicDirectRegWrite(lineId, LINE_STATE, RING_LINE); // REG 64,4 +} + + +static void mvSlicDisableOscillators(unsigned int lineId) +{ + // Turns of OSC1 and OSC2 + unsigned char i; + + //mvOsPrintf("Disabling Oscillators!!!\n"); + for ( i=32; i<=45; i++) + if (i !=34) // Don't write to the ringing oscillator control + mvSlicDirectRegWrite(lineId, i,0); +} + + +static unsigned char mvSlicLoopStatus(unsigned int lineId) +{ +static int ReadBack; + + // check for power alarms + if ((mvSlicDirectRegRead(lineId, 19) & 0xfc) != 0) { + mvOsPrintf ("Power alarm = %x\n",(mvSlicDirectRegRead(lineId, 19) & 0xfc)); + mvSlicClearAlarmBits (lineId); + } + ReadBack = mvSlicDirectRegRead (lineId, 68); + return (ReadBack & 0x3); + +} + +#ifdef SLIC_TEST_LOOPSTATUS_AND_DIGIT_DETECTION +static unsigned char mvSlicDigit(unsigned int lineId) +{ + return mvSlicDirectRegRead(lineId, 24) & 0x1f; +} +#endif + +static void mvSlicPrintFreqRevision(unsigned int lineId) +{ + + int freq; +#ifdef DEBUG + char* freqs[ ] = {"8192","4096","2048","1024","512","256","1536","768","32768"}; +#endif + // Turn on all interrupts + freq=mvSlicDirectRegRead(lineId, 13)>>4; /* Read the frequency */ + DBG("PCM clock = %s KHz Rev %c \n", freqs[freq], 'A'-1 + mvSlicVersion(lineId)); +} + +int mvSlicCalibrate(unsigned int lineId) +{ + unsigned short i=0; + volatile unsigned char DRvalue; + int timeOut,nCalComplete; + + /* Do Flush durring powerUp and calibrate */ + /*mvSlicDirectRegWrite(lineId, 21,DISABLE_ALL_DR21);//(0) Disable all interupts in DR21 + mvSlicDirectRegWrite(lineId, 22,DISABLE_ALL_DR22);//(0) Disable all interupts in DR21 + mvSlicDirectRegWrite(lineId, 23,DISABLE_ALL_DR23);//(0) Disabel all interupts in DR21 */ + mvSlicDirectRegWrite(lineId, 64,OPEN_DR64);//(0) + + mvSlicDirectRegWrite(lineId, 97,0x1e); //(0x18)Calibrations without the ADC and DAC offset and without common mode calibration. + mvSlicDirectRegWrite(lineId, 96,0x47); //(0x47) Calibrate common mode and differential DAC mode DAC + ILIM + + DBG("Start Calibration(vBat = %x)\n", mvSlicDirectRegRead(lineId, 82)); + + i=0; + do + { + DRvalue = mvSlicDirectRegRead(lineId, 96); + nCalComplete = DRvalue==CAL_COMPLETE_DR96;// (0) When Calibration completes DR 96 will be zero + timeOut= i++>MAX_CAL_PERIOD; + mvOsDelay(1); + } + while (!nCalComplete&&!timeOut); + + if (timeOut) { + mvOsPrintf ("Error in Caliberatation: timeOut\n"); + return 0; + } + + +/*Initialized DR 98 and 99 to get consistant results.*/ +/* 98 and 99 are the results registers and the search should have same intial conditions.*/ +/*******The following is the manual gain mismatch calibration******/ +/*******This is also available as a function **********************/ + // Wait for any power alarms to settle. + //mvOsDelay(100); /* is it enough ? */ + + mvSlicIndirectRegWrite(lineId, 88,0); + mvSlicIndirectRegWrite(lineId, 89,0); + mvSlicIndirectRegWrite(lineId, 90,0); + mvSlicIndirectRegWrite(lineId, 91,0); + mvSlicIndirectRegWrite(lineId, 92,0); + mvSlicIndirectRegWrite(lineId, 93,0); + + + mvSlicGoActive(lineId); + + if (mvSlicLoopStatus(lineId) & 4) { + mvOsPrintf ("Error in Caliberate: ERRORCODE_LONGBALCAL\n"); + return 0 ; + } + + mvSlicDirectRegWrite(lineId, 64,OPEN_DR64); + + mvSlicDirectRegWrite(lineId, 23,ENB2_DR23); // enable interrupt for the balance Cal + mvSlicDirectRegWrite(lineId, 97,BIT_CALCM_DR97); // this is a singular calibration bit for longitudinal calibration + mvSlicDirectRegWrite(lineId, 96,0x40); + + DRvalue = mvSlicDirectRegRead(lineId, 96); + i=0; + do + { + DRvalue = mvSlicDirectRegRead(lineId, 96); + nCalComplete = DRvalue==CAL_COMPLETE_DR96;// (0) When Calibration completes DR 96 will be zero + timeOut= i++>MAX_CAL_PERIOD;// (800) MS + mvOsDelay(1); + } + while (!nCalComplete&&!timeOut); + + if (timeOut) { + mvOsPrintf ("Error in Caliberate: timeOut\n"); + return 0; + } + + //mvOsDelay(100); /* is it enough ? */ + + for (i=88; i<=95; i++) { + mvSlicIndirectRegWrite (lineId, i, 0); + } + mvSlicIndirectRegWrite (lineId, 97, 0); + + for (i=193; i<=211; i++) { + mvSlicIndirectRegWrite (lineId, i, 0); + } + + return(1); + +}// End of first calibration + +static void mvSlicInitializeIndirectRegisters(unsigned int lineId) +{ +if (!Si3215_Flag) +{ + mvSlicIndirectRegWrite(lineId, 0 , INIT_IR0 ); // 0x55C2 DTMF_ROW_0_PEAK + mvSlicIndirectRegWrite(lineId, 1 , INIT_IR1 ); // 0x51E6 DTMF_ROW_1_PEAK + mvSlicIndirectRegWrite(lineId, 2 , INIT_IR2 ); // 0x4B85 DTMF_ROW2_PEAK + mvSlicIndirectRegWrite(lineId, 3 , INIT_IR3 ); // 0x4937 DTMF_ROW3_PEAK + mvSlicIndirectRegWrite(lineId, 4 , INIT_IR4 ); // 0x3333 DTMF_COL1_PEAK + mvSlicIndirectRegWrite(lineId, 5 , INIT_IR5 ); // 0x0202 DTMF_FWD_TWIST + mvSlicIndirectRegWrite(lineId, 6 , INIT_IR6 ); // 0x0202 DTMF_RVS_TWIST + mvSlicIndirectRegWrite(lineId, 7 , INIT_IR7 ); // 0x0198 DTMF_ROW_RATIO + mvSlicIndirectRegWrite(lineId, 8 , INIT_IR8 ); // 0x0198 DTMF_COL_RATIO + mvSlicIndirectRegWrite(lineId, 9 , INIT_IR9 ); // 0x0611 DTMF_ROW_2ND_ARM + mvSlicIndirectRegWrite(lineId, 10 , INIT_IR10 ); // 0x0202 DTMF_COL_2ND_ARM + mvSlicIndirectRegWrite(lineId, 11 , INIT_IR11 ); // 0x00E5 DTMF_PWR_MIN_ + mvSlicIndirectRegWrite(lineId, 12 , INIT_IR12 ); // 0x0A1C DTMF_OT_LIM_TRES +} + + mvSlicIndirectRegWrite(lineId, 13 , INIT_IR13 ); // 0x7b30 OSC1_COEF + mvSlicIndirectRegWrite(lineId, 14 , INIT_IR14 ); // 0x0063 OSC1X + mvSlicIndirectRegWrite(lineId, 15 , INIT_IR15 ); // 0x0000 OSC1Y + mvSlicIndirectRegWrite(lineId, 16 , INIT_IR16 ); // 0x7870 OSC2_COEF + mvSlicIndirectRegWrite(lineId, 17 , INIT_IR17 ); // 0x007d OSC2X + mvSlicIndirectRegWrite(lineId, 18 , INIT_IR18 ); // 0x0000 OSC2Y + mvSlicIndirectRegWrite(lineId, 19 , INIT_IR19 ); // 0x0000 RING_V_OFF + mvSlicIndirectRegWrite(lineId, 20 , INIT_IR20 ); // 0x7EF0 RING_OSC + mvSlicIndirectRegWrite(lineId, 21 , INIT_IR21 ); // 0x0160 RING_X + mvSlicIndirectRegWrite(lineId, 22 , INIT_IR22 ); // 0x0000 RING_Y + mvSlicIndirectRegWrite(lineId, 23 , INIT_IR23 ); // 0x2000 PULSE_ENVEL + mvSlicIndirectRegWrite(lineId, 24 , INIT_IR24 ); // 0x2000 PULSE_X + mvSlicIndirectRegWrite(lineId, 25 , INIT_IR25 ); // 0x0000 PULSE_Y + mvSlicIndirectRegWrite(lineId, 26 , INIT_IR26 ); // 0x4000 RECV_DIGITAL_GAIN + mvSlicIndirectRegWrite(lineId, 27 , INIT_IR27 ); // 0x4000 XMIT_DIGITAL_GAIN + mvSlicIndirectRegWrite(lineId, 28 , INIT_IR28 ); // 0x1000 LOOP_CLOSE_TRES + mvSlicIndirectRegWrite(lineId, 29 , INIT_IR29 ); // 0x3600 RING_TRIP_TRES + mvSlicIndirectRegWrite(lineId, 30 , INIT_IR30 ); // 0x1000 COMMON_MIN_TRES + mvSlicIndirectRegWrite(lineId, 31 , INIT_IR31 ); // 0x0200 COMMON_MAX_TRES + mvSlicIndirectRegWrite(lineId, 32 , INIT_IR32 ); // 0x7c0 PWR_ALARM_Q1Q2 + mvSlicIndirectRegWrite(lineId, 33 , INIT_IR33 ); // 0x2600 PWR_ALARM_Q3Q4 + mvSlicIndirectRegWrite(lineId, 34 , INIT_IR34 ); // 0x1B80 PWR_ALARM_Q5Q6 + mvSlicIndirectRegWrite(lineId, 35 , INIT_IR35 ); // 0x8000 LOOP_CLSRE_FlTER + mvSlicIndirectRegWrite(lineId, 36 , INIT_IR36 ); // 0x0320 RING_TRIP_FILTER + mvSlicIndirectRegWrite(lineId, 37 , INIT_IR37 ); // 0x08c TERM_LP_POLE_Q1Q2 + mvSlicIndirectRegWrite(lineId, 38 , INIT_IR38 ); // 0x0100 TERM_LP_POLE_Q3Q4 + mvSlicIndirectRegWrite(lineId, 39 , INIT_IR39 ); // 0x0010 TERM_LP_POLE_Q5Q6 + mvSlicIndirectRegWrite(lineId, 40 , INIT_IR40 ); // 0x0C00 CM_BIAS_RINGING + mvSlicIndirectRegWrite(lineId, 41 , INIT_IR41 ); // 0x0C00 DCDC_MIN_V + mvSlicIndirectRegWrite(lineId, 43 , INIT_IR43 ); // 0x1000 LOOP_CLOSE_TRES Low + mvSlicIndirectRegWrite(lineId, 99 , INIT_IR99 ); // 0x00DA FSK 0 FREQ PARAM + mvSlicIndirectRegWrite(lineId, 100 , INIT_IR100 ); // 0x6B60 FSK 0 AMPL PARAM + mvSlicIndirectRegWrite(lineId, 101 , INIT_IR101 ); // 0x0074 FSK 1 FREQ PARAM + mvSlicIndirectRegWrite(lineId, 102 , INIT_IR102 ); // 0x79C0 FSK 1 AMPl PARAM + mvSlicIndirectRegWrite(lineId, 103 , INIT_IR103 ); // 0x1120 FSK 0to1 SCALER + mvSlicIndirectRegWrite(lineId, 104 , INIT_IR104 ); // 0x3BE0 FSK 1to0 SCALER + mvSlicIndirectRegWrite(lineId, 97 , INIT_IR97 ); // 0x0000 TRASMIT_FILTER +} + + + +static void mvSlicInitializeDirectRegisters(unsigned int lineId) +{ + +if(spiMode) + mvSlicDirectRegWrite(lineId, 0, INIT_DR0_DC );//0X00 Serial Interface +else + mvSlicDirectRegWrite(lineId, 0, INIT_DR0 );//0X00 Serial Interface + +mvSlicDirectRegWrite(lineId, 1, INIT_DR1 );//0X08 PCM Mode - INIT TO disable +mvSlicDirectRegWrite(lineId, 2, INIT_DR2 );//0X00 PCM TX Clock Slot Low Byte (1 PCLK cycle/LSB) +mvSlicDirectRegWrite(lineId, 3, INIT_DR3 );//0x00 PCM TX Clock Slot High Byte +mvSlicDirectRegWrite(lineId, 4, INIT_DR4 );//0x00 PCM RX Clock Slot Low Byte (1 PCLK cycle/LSB) +mvSlicDirectRegWrite(lineId, 5, INIT_DR5 );//0x00 PCM RX Clock Slot High Byte +mvSlicDirectRegWrite(lineId, 8, INIT_DR8 );//0X00 Loopbacks (digital loopback default) +mvSlicDirectRegWrite(lineId, 9, INIT_DR9 );//0x00 Transmit and receive path gain and control +mvSlicDirectRegWrite(lineId, 10, INIT_DR10 );//0X28 Initialization Two-wire impedance (600 and enabled) +mvSlicDirectRegWrite(lineId, 11, INIT_DR11 );//0x33 Transhybrid Balance/Four-wire Return Loss +mvSlicDirectRegWrite(lineId, 18, INIT_DR18 );//0xff Normal Oper. Interrupt Register 1 (clear with 0xFF) +mvSlicDirectRegWrite(lineId, 19, INIT_DR19 );//0xff Normal Oper. Interrupt Register 2 (clear with 0xFF) +mvSlicDirectRegWrite(lineId, 20, INIT_DR20 );//0xff Normal Oper. Interrupt Register 3 (clear with 0xFF) +/*mvSlicDirectRegWrite(lineId, 21, INIT_DR21 );//0xff Interrupt Mask 1 +mvSlicDirectRegWrite(lineId, 22, INIT_DR22 );//0xff Initialization Interrupt Mask 2 +mvSlicDirectRegWrite(lineId, 23, INIT_DR23 );//0xff Initialization Interrupt Mask 3 */ +mvSlicDirectRegWrite(lineId, 32, INIT_DR32 );//0x00 Oper. Oscillator 1 Controltone generation +mvSlicDirectRegWrite(lineId, 33, INIT_DR33 );//0x00 Oper. Oscillator 2 Controltone generation +mvSlicDirectRegWrite(lineId, 34, INIT_DR34 );//0X18 34 0x22 0x00 Initialization Ringing Oscillator Control +mvSlicDirectRegWrite(lineId, 35, INIT_DR35 );//0x00 Oper. Pulse Metering Oscillator Control +mvSlicDirectRegWrite(lineId, 36, INIT_DR36 );//0x00 36 0x24 0x00 Initialization OSC1 Active Low Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 37, INIT_DR37 );//0x00 37 0x25 0x00 Initialization OSC1 Active High Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 38, INIT_DR38 );//0x00 38 0x26 0x00 Initialization OSC1 Inactive Low Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 39, INIT_DR39 );//0x00 39 0x27 0x00 Initialization OSC1 Inactive High Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 40, INIT_DR40 );//0x00 40 0x28 0x00 Initialization OSC2 Active Low Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 41, INIT_DR41 );//0x00 41 0x29 0x00 Initialization OSC2 Active High Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 42, INIT_DR42 );//0x00 42 0x2A 0x00 Initialization OSC2 Inactive Low Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 43, INIT_DR43 );//0x00 43 0x2B 0x00 Initialization OSC2 Inactive High Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 44, INIT_DR44 );//0x00 44 0x2C 0x00 Initialization Pulse Metering Active Low Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 45, INIT_DR45 );//0x00 45 0x2D 0x00 Initialization Pulse Metering Active High Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 46, INIT_DR46 );//0x00 46 0x2E 0x00 Initialization Pulse Metering Inactive Low Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 47, INIT_DR47 );//0x00 47 0x2F 0x00 Initialization Pulse Metering Inactive High Byte (125 µs/LSB) +mvSlicDirectRegWrite(lineId, 48, INIT_DR48 );//0X80 48 0x30 0x00 0x80 Initialization Ringing Osc. Active Timer Low Byte (2 s,125 µs/LSB) +mvSlicDirectRegWrite(lineId, 49, INIT_DR49 );//0X3E 49 0x31 0x00 0x3E Initialization Ringing Osc. Active Timer High Byte (2 s,125 µs/LSB) +mvSlicDirectRegWrite(lineId, 50, INIT_DR50 );//0X00 50 0x32 0x00 0x00 Initialization Ringing Osc. Inactive Timer Low Byte (4 s, 125 µs/LSB) +mvSlicDirectRegWrite(lineId, 51, INIT_DR51 );//0X7D 51 0x33 0x00 0x7D Initialization Ringing Osc. Inactive Timer High Byte (4 s, 125 µs/LSB) +mvSlicDirectRegWrite(lineId, 52, INIT_DR52 );//0X00 52 0x34 0x00 Normal Oper. FSK Data Bit +mvSlicDirectRegWrite(lineId, 63, INIT_DR63 );//0X54 63 0x3F 0x54 Initialization Ringing Mode Loop Closure Debounce Interval +mvSlicDirectRegWrite(lineId, 64, INIT_DR64 );//0x00 64 0x40 0x00 Normal Oper. Mode Byte—primary control +mvSlicDirectRegWrite(lineId, 65, INIT_DR65 );//0X61 65 0x41 0x61 Initialization External Bipolar Transistor Settings +mvSlicDirectRegWrite(lineId, 66, INIT_DR66 );//0X03 66 0x42 0x03 Initialization Battery Control +mvSlicDirectRegWrite(lineId, 67, INIT_DR67 );//0X1F 67 0x43 0x1F Initialization Automatic/Manual Control +mvSlicDirectRegWrite(lineId, 69, INIT_DR69 );//0X0C 69 0x45 0x0A 0x0C Initialization Loop Closure Debounce Interval (1.25 ms/LSB) +mvSlicDirectRegWrite(lineId, 70, INIT_DR70 );//0X0A 70 0x46 0x0A Initialization Ring Trip Debounce Interval (1.25 ms/LSB) +mvSlicDirectRegWrite(lineId, 71, INIT_DR71 );//0X01 71 0x47 0x00 0x01 Initialization Off-Hook Loop Current Limit (20 mA + 3 mA/LSB) +mvSlicDirectRegWrite(lineId, 72, INIT_DR72 );//0X20 72 0x48 0x20 Initialization On-Hook Voltage (open circuit voltage) = 48 V(1.5 V/LSB) +mvSlicDirectRegWrite(lineId, 73, INIT_DR73 );//0X02 73 0x49 0x02 Initialization Common Mode VoltageVCM = 3 V(1.5 V/LSB) +mvSlicDirectRegWrite(lineId, 74, INIT_DR74 );//0X32 74 0x4A 0x32 Initialization VBATH (ringing) = 75 V (1.5 V/LSB) +mvSlicDirectRegWrite(lineId, 75, INIT_DR75 );//0X10 75 0x4B 0x10 Initialization VBATL (off-hook) = 24 V (TRACK = 0)(1.5 V/LSB) +if (mvSlicChipType(lineId) != 3) +mvSlicDirectRegWrite(lineId, 92, INIT_DR92 );//0x7f 92 0x5C 0xFF 7F Initialization DCDC Converter PWM Period (61.035 ns/LSB) +else +mvSlicDirectRegWrite(lineId, 92, INIT_SI3210M_DR92 );//0x7f 92 0x5C 0xFF 7F Initialization DCDC Converter PWM Period (61.035 ns/LSB) + + +mvSlicDirectRegWrite(lineId, 93, INIT_DR93 );//0x14 93 0x5D 0x14 0x19 Initialization DCDC Converter Min. Off Time (61.035 ns/LSB) +mvSlicDirectRegWrite(lineId, 96, INIT_DR96 );//0x00 96 0x60 0x1F Initialization Calibration Control Register 1(written second and starts calibration) +mvSlicDirectRegWrite(lineId, 97, INIT_DR97 );//0X1F 97 0x61 0x1F Initialization Calibration Control Register 2(written before Register 96) +mvSlicDirectRegWrite(lineId, 98, INIT_DR98 );//0X10 98 0x62 0x10 Informative Calibration result (see data sheet) +mvSlicDirectRegWrite(lineId, 99, INIT_DR99 );//0X10 99 0x63 0x10 Informative Calibration result (see data sheet) +mvSlicDirectRegWrite(lineId, 100, INIT_DR100 );//0X11 100 0x64 0x11 Informative Calibration result (see data sheet) +mvSlicDirectRegWrite(lineId, 101, INIT_DR101 );//0X11 101 0x65 0x11 Informative Calibration result (see data sheet) +mvSlicDirectRegWrite(lineId, 102, INIT_DR102 );//0x08 102 0x66 0x08 Informative Calibration result (see data sheet) +mvSlicDirectRegWrite(lineId, 103, INIT_DR103 );//0x88 103 0x67 0x88 Informative Calibration result (see data sheet) +mvSlicDirectRegWrite(lineId, 104, INIT_DR104 );//0x00 104 0x68 0x00 Informative Calibration result (see data sheet) +mvSlicDirectRegWrite(lineId, 105, INIT_DR105 );//0x00 105 0x69 0x00 Informative Calibration result (see data sheet) +mvSlicDirectRegWrite(lineId, 106, INIT_DR106 );//0x20 106 0x6A 0x20 Informative Calibration result (see data sheet) +mvSlicDirectRegWrite(lineId, 107, INIT_DR107 );//0x08 107 0x6B 0x08 Informative Calibration result (see data sheet) +mvSlicDirectRegWrite(lineId, 108, INIT_DR108 );//0xEB 108 0x63 0x00 0xEB Initialization Feature enhancement register +} + + +static void mvSlicClearInterrupts(unsigned int lineId) +{ + mvSlicDirectRegWrite(lineId, 18 , INIT_DR18 );//0xff Normal Oper. Interrupt Register 1 (clear with 0xFF) + mvSlicDirectRegWrite(lineId, 19 , INIT_DR19 );//0xff Normal Oper. Interrupt Register 2 (clear with 0xFF) + mvSlicDirectRegWrite(lineId, 20 , INIT_DR20 );//0xff Normal Oper. Interrupt Register 3 (clear with 0xFF) +} + +int verifyIndirectReg(unsigned int lineId, unsigned char address, unsigned short should_be_value) +{ + int error_flag ; + unsigned short value; + + value = mvSlicIndirectRegRead(lineId, address); + error_flag = (should_be_value != value); + + if ( error_flag ) + { + mvOsPrintf("\n iREG %d = %X should be %X ",address,value,should_be_value ); + } + return error_flag; +} + +#ifdef DEBUG + +static int mvSlicVerifyIndirectRegisters(unsigned int lineId) +{ + int error=0; + + if (!Si3215_Flag) + { + + error |= verifyIndirectReg(lineId , 0 , INIT_IR0 ); // 0x55C2 DTMF_ROW_0_PEAK + error |= verifyIndirectReg(lineId , 1 , INIT_IR1 ); // 0x51E6 DTMF_ROW_1_PEAK + error |= verifyIndirectReg(lineId , 2 , INIT_IR2 ); // 0x4B85 DTMF_ROW2_PEAK + error |= verifyIndirectReg(lineId , 3 , INIT_IR3 ); // 0x4937 DTMF_ROW3_PEAK + error |= verifyIndirectReg(lineId , 4 , INIT_IR4 ); // 0x3333 DTMF_COL1_PEAK + error |= verifyIndirectReg(lineId , 5 , INIT_IR5 ); // 0x0202 DTMF_FWD_TWIST + error |= verifyIndirectReg(lineId , 6 , INIT_IR6 ); // 0x0202 DTMF_RVS_TWIST + error |= verifyIndirectReg(lineId , 7 , INIT_IR7 ); // 0x0198 DTMF_ROW_RATIO + error |= verifyIndirectReg(lineId , 8 , INIT_IR8 ); // 0x0198 DTMF_COL_RATIO + error |= verifyIndirectReg(lineId , 9 , INIT_IR9 ); // 0x0611 DTMF_ROW_2ND_ARM + error |= verifyIndirectReg(lineId , 10 , INIT_IR10 ); // 0x0202 DTMF_COL_2ND_ARM + error |= verifyIndirectReg(lineId , 11 , INIT_IR11 ); // 0x00E5 DTMF_PWR_MIN_ + error |= verifyIndirectReg(lineId , 12 , INIT_IR12 ); // 0x0A1C DTMF_OT_LIM_TRES + } + error |= verifyIndirectReg(lineId , 13 , INIT_IR13 ); // 0x7b30 OSC1_COEF + error |= verifyIndirectReg(lineId , 14 , INIT_IR14 ); // 0x0063 OSC1X + error |= verifyIndirectReg(lineId , 15 , INIT_IR15 ); // 0x0000 OSC1Y + error |= verifyIndirectReg(lineId , 16 , INIT_IR16 ); // 0x7870 OSC2_COEF + error |= verifyIndirectReg(lineId , 17 , INIT_IR17 ); // 0x007d OSC2X + error |= verifyIndirectReg(lineId , 18 , INIT_IR18 ); // 0x0000 OSC2Y + error |= verifyIndirectReg(lineId , 19 , INIT_IR19 ); // 0x0000 RING_V_OFF + error |= verifyIndirectReg(lineId , 20 , INIT_IR20 ); // 0x7EF0 RING_OSC + error |= verifyIndirectReg(lineId , 21 , INIT_IR21 ); // 0x0160 RING_X + error |= verifyIndirectReg(lineId , 22 , INIT_IR22 ); // 0x0000 RING_Y + error |= verifyIndirectReg(lineId , 23 , INIT_IR23 ); // 0x2000 PULSE_ENVEL + error |= verifyIndirectReg(lineId , 24 , INIT_IR24 ); // 0x2000 PULSE_X + error |= verifyIndirectReg(lineId , 25 , INIT_IR25 ); // 0x0000 PULSE_Y + error |= verifyIndirectReg(lineId , 26 , INIT_IR26 ); // 0x4000 RECV_DIGITAL_GAIN + error |= verifyIndirectReg(lineId , 27 , INIT_IR27 ); // 0x4000 XMIT_DIGITAL_GAIN + error |= verifyIndirectReg(lineId , 28 , INIT_IR28 ); // 0x1000 LOOP_CLOSE_TRES + error |= verifyIndirectReg(lineId , 29 , INIT_IR29 ); // 0x3600 RING_TRIP_TRES + error |= verifyIndirectReg(lineId , 30 , INIT_IR30 ); // 0x1000 COMMON_MIN_TRES + error |= verifyIndirectReg(lineId , 31 , INIT_IR31 ); // 0x0200 COMMON_MAX_TRES + error |= verifyIndirectReg(lineId , 32 , INIT_IR32 ); // 0x7c0 PWR_ALARM_Q1Q2 + error |= verifyIndirectReg(lineId , 33 , INIT_IR33 ); // 0x2600 PWR_ALARM_Q3Q4 + error |= verifyIndirectReg(lineId , 34 , INIT_IR34 ); // 0x1B80 PWR_ALARM_Q5Q6 + error |= verifyIndirectReg(lineId , 35 , INIT_IR35 ); // 0x8000 LOOP_CLSRE_FlTER + error |= verifyIndirectReg(lineId , 36 , INIT_IR36 ); // 0x0320 RING_TRIP_FILTER + error |= verifyIndirectReg(lineId , 37 , INIT_IR37 ); // 0x08c TERM_LP_POLE_Q1Q2 + error |= verifyIndirectReg(lineId , 38 , INIT_IR38 ); // 0x0100 TERM_LP_POLE_Q3Q4 + error |= verifyIndirectReg(lineId , 39 , INIT_IR39 ); // 0x0010 TERM_LP_POLE_Q5Q6 + error |= verifyIndirectReg(lineId , 40 , INIT_IR40 ); // 0x0C00 CM_BIAS_RINGING + error |= verifyIndirectReg(lineId , 41 , INIT_IR41 ); // 0x0C00 DCDC_MIN_V + error |= verifyIndirectReg(lineId , 43 , INIT_IR43 ); // 0x1000 LOOP_CLOSE_TRES Low + error |= verifyIndirectReg(lineId , 99 , INIT_IR99 ); // 0x00DA FSK 0 FREQ PARAM + error |= verifyIndirectReg(lineId , 100 , INIT_IR100 ); // 0x6B60 FSK 0 AMPL PARAM + error |= verifyIndirectReg(lineId , 101 , INIT_IR101 ); // 0x0074 FSK 1 FREQ PARAM + error |= verifyIndirectReg(lineId , 102 , INIT_IR102 ); // 0x79C0 FSK 1 AMPl PARAM + error |= verifyIndirectReg(lineId , 103 , INIT_IR103 ); // 0x1120 FSK 0to1 SCALER + error |= verifyIndirectReg(lineId , 104 , INIT_IR104 ); // 0x3BE0 FSK 1to0 SCALER + + return error; +} + +#endif /* DEBUG */ + +static void mvSlicEnablePCMhighway(unsigned int lineId) +{ + /* pcm Mode Select */ + /* + ** Bit 0: tri-State on Positive edge of Pclk + ** Bit 1: GCI Clock Format, 1 PCLK per data bit + ** Bit 2: PCM Transfer size (8 bt transfer) + ** Bit 3-4: PCM Format mu-law + ** Bit 5: PCM Enable + */ + mvSlicDirectRegWrite(lineId, 1,0x28); +} + + +/* New Functions */ +static MV_STATUS mvSlicPrintInfo(unsigned int lineId) +{ + unsigned int type; + unsigned char fm; + char name[10]; + + + fm = mvSlicFamily(lineId); + type = mvSlicChipType(lineId); + + if(fm == MV_SI3210_FAMILY) + { + if(type == MV_SI3210) + strcpy(name, "SI3210"); + else if(type == MV_SI3211) + strcpy(name, "SI3211"); + else if(type == MV_SI3210M) + strcpy(name, "SI3210M"); + else + strcpy(name, "UNKNOWN"); + } + else if(fm == MV_SI3215_FAMILY) + { + if(type == MV_SI3215) + strcpy(name, "SI3215"); + else if(type == MV_SI3215M) + strcpy(name, "SI3215M"); + else + strcpy(name, "UNKNOWN"); + + } + strcat(name, "\0"); + //mvOsPrintf("FXS type : %s\n",name); + + if(strcmp(name,"UNKNOWN")) + return MV_OK; + else + return MV_NOT_SUPPORTED; + +} +MV_STATUS mvSlicInit(unsigned short first, unsigned short last, unsigned short pSlotInfo[][2], + unsigned short lines, mv_band_mode_t bandMode, mv_pcm_format_t pcmFormat) +{ + MV_SLIC_LINE_INFO *pSlicLineInfo; + unsigned int lineId; + + MV_TRC_REC("->%s\n", __FUNCTION__); + + /* Save parameters */ + firstSlic = first; + lastSlic = last; + mvBandMode = bandMode; + mvPcmFormat = pcmFormat; + totalSLICs = last -first + 1; + spiMode = mvBoardTdmSpiModeGet(); + calibrated = 0; + + slicLineInfo = (MV_SLIC_LINE_INFO*)mvOsMalloc(sizeof(MV_SLIC_LINE_INFO) * totalSLICs); + if(!slicLineInfo) + { + mvOsPrintf("%s:Error, allocation failed(slicLineInfo) !!!\n",__FUNCTION__); + return MV_ERROR; + } + + /* Set pointer to first SLIC */ + pSlicLineInfo = (MV_SLIC_LINE_INFO*)(slicLineInfo + firstSlic); + + mvOsPrintf("Start initialization for SLIC modules %u to %u...",firstSlic, lastSlic); + + for(lineId = firstSlic; lineId < (lastSlic+1); lineId++) + { + pSlicLineInfo->lineId = lineId; + + if(!mvSlicStart(lineId)) + return MV_ERROR; + + /* Goto next SLIC module */ + pSlicLineInfo++; + } + + /* Set pointer to first SLIC */ + pSlicLineInfo = (MV_SLIC_LINE_INFO*)(slicLineInfo + firstSlic); + + for(lineId = firstSlic; lineId < (lastSlic+1); lineId++) + { + /* Complete starting phase */ + mvSlicStart2(lineId); + + mvSlicEnablePCMhighway(lineId); + + /* print slic info */ + if(mvSlicPrintInfo(lineId) == MV_OK) + { + if(spiMode) + { + if(!mvSlicDaisyChainGet(lineId)) + { + mvOsPrintf("error, line %d is not in daisy chain mode\n",lineId); + return MV_ERROR; + } + } + + mvSlicIntDisable(lineId); + + switch(pcmFormat) + { + case MV_PCM_FORMAT_ALAW: + case MV_PCM_FORMAT_ULAW: + case MV_PCM_FORMAT_LINEAR: + mvSlicPcmFormatSet(lineId, pcmFormat); + break; + default: + mvOsPrintf("Error, wrong pcm format(%d)\n", pcmFormat); + break; + } + + /* Configure tx/rx sample in SLIC */ + pSlicLineInfo->rxSample = pSlotInfo[lineId][0]; + pSlicLineInfo->txSample = pSlotInfo[lineId][1]; + DBG("Rx sample %d, Tx sample %d\n", pSlicLineInfo->rxSample, pSlicLineInfo->txSample); + pSlicLineInfo->txSample *= 8; + pSlicLineInfo->rxSample *= 8; + mvSlicPcmStartCountRegsSet(lineId); + } + else + { + mvOsPrintf("%s: error, unknown slic type\n",__FUNCTION__); + return MV_ERROR; + } + + /* enable interrupts */ + mvSlicIntEnable(lineId); + + /* Goto next SLIC module */ + pSlicLineInfo++; + + mvSlicPrintFreqRevision(lineId); + } + + mvOsPrintf("Done\n"); + MV_TRC_REC("<-%s\n", __FUNCTION__); + return MV_OK; +} + +static void mvSlicIntEnable(unsigned int lineId) +{ + MV_TRC_REC("enable slic-%d interrupts\n", lineId); + mvSlicDirectRegWrite(lineId, INTRPT_MASK1, 0x10); + mvSlicDirectRegWrite(lineId, INTRPT_MASK2, 2); + mvSlicDirectRegWrite(lineId, INTRPT_MASK3, 0); + +} + +static void mvSlicIntDisable(unsigned int lineId) +{ + MV_TRC_REC("disable slic-%d interrupts\n", lineId); + mvSlicDirectRegWrite(lineId, INTRPT_MASK1, 0); + mvSlicDirectRegWrite(lineId, INTRPT_MASK2, 0); + mvSlicDirectRegWrite(lineId, INTRPT_MASK3, 0); + mvSlicClearInterrupts(lineId); +} + + + +static int mvSlicDaisyChainGet(unsigned int lineId) +{ + int val; + + val = mvSlicDirectRegRead(lineId, 0); + + return (val & 0x80); + +} + +static void mvSlicPcmFormatSet(unsigned int lineId, mv_pcm_format_t pcmFormat) +{ + int val; + + val = mvSlicDirectRegRead(lineId, PCM_MODE); + + if(pcmFormat == MV_PCM_FORMAT_LINEAR) + val = val | BIT2; /* set 16-bit transfer */ + else + val = val & ~BIT2; /* set 8-bit transfer */ + + mvSlicDirectRegWrite(lineId, PCM_MODE, (val | (pcmFormat<<3))); +} + +static void mvSlicPcmStartCountRegsSet(unsigned int lineId) +{ + MV_SLIC_LINE_INFO *pSlicLineInfo = (MV_SLIC_LINE_INFO*)(slicLineInfo + lineId); + + mvSlicDirectRegWrite(lineId, PCM_XMIT_START_COUNT_LSB, pSlicLineInfo->txSample&0xff); + mvSlicDirectRegWrite(lineId, PCM_XMIT_START_COUNT_MSB, (pSlicLineInfo->txSample>>8)&0x3); + mvSlicDirectRegWrite(lineId, PCM_RCV_START_COUNT_LSB, pSlicLineInfo->rxSample&0xff); + mvSlicDirectRegWrite(lineId, PCM_RCV_START_COUNT_MSB, (pSlicLineInfo->rxSample>>8)&0x3); + +} + +static int mvSlicIntCheck(unsigned int lineId) +{ + union { + unsigned char reg_data[3]; + long interrupt_bits; + } u ; + u.interrupt_bits=0; + + + u.reg_data[0] = mvSlicDirectRegRead(lineId, 18); + mvSlicDirectRegWrite(lineId, 18, u.reg_data[0]); + + u.reg_data[1] = mvSlicDirectRegRead(lineId, 19); + if ((u.reg_data[1] & 0xfc) != 0) { + mvSlicClearAlarmBits (lineId); + } + mvSlicDirectRegWrite(lineId, 19, u.reg_data[1] ); + + u.reg_data[2] = mvSlicDirectRegRead(lineId, 20); + mvSlicDirectRegWrite(lineId, 20, u.reg_data[2]); + + if((u.reg_data[0] & 0x10) && (0x04 == mvSlicDirectRegRead(lineId, 68))) + { + return 0; + } + + return (u.interrupt_bits)? 1 : 0; + +} + +unsigned char mvSlicIntGet(unsigned int lineId) +{ + unsigned char state; + + if(!mvSlicIntCheck(lineId)) + return 0; + + mvSlicHookStateGet(lineId, &state); + + return state; + +} + + +void mvSlicHookStateGet(unsigned short lineId, unsigned char* hookstate) +{ + MV_U8 reg68; + + reg68 = mvSlicDirectRegRead(lineId, 68); + + if((reg68 & 4)) + { + *hookstate = ON_HOOK; + } + else + { + *hookstate = OFF_HOOK; + } + + return; +} + +void mvSlicReverseDcPolarity(unsigned char lineId) +{ + MV_U8 data; + + /* read value of On-Hook Line Voltage register */ + data = mvSlicDirectRegRead(lineId, OFF_HOOK_V); + /* toggle the VSGN bit - VTIP–VRING polarity */ + mvSlicDirectRegWrite(lineId, OFF_HOOK_V, data^0x40); + + return; +} + +void mvSlicLinefeedControlSet(unsigned char lineId, mv_linefeed_t lfState) +{ + mvSlicDirectRegWrite(lineId, LINE_STATE, lfState); + return; +} + +void mvSlicLinefeedControlGet(unsigned char lineId, mv_linefeed_t* lfState) +{ + *lfState = ((mvSlicDirectRegRead(lineId, LINE_STATE) & 0x70) >> 4); + return; +} + + +void mvSlicRelease(void) +{ + if(slicLineInfo) + mvOsFree(slicLineInfo); +} diff --git a/board/mv_feroceon/mv_hal/voiceband/slic/proslic.h b/board/mv_feroceon/mv_hal/voiceband/slic/proslic.h new file mode 100644 index 0000000..f5a4b8a --- /dev/null +++ b/board/mv_feroceon/mv_hal/voiceband/slic/proslic.h @@ -0,0 +1,1387 @@ +/************************************ PROSLIC.H *************************************************/ +#ifndef _PROSLIC_H_ +#define _PROSLIC_H_ + +#include "voiceband/voiceband.h" + +typedef enum { + LF_OPEN = 0, + LF_FORWARD_ACTIVE, + LF_FORWARD_ON_HOOK_TRANSMISSION, + LF_TIP_OPEN, + LF_RINGING, + LF_REVERESE_ACTIVE, + LF_REVERSE_ON_HOOK_TRANSMISSION, + LF_RING_OPEN +} mv_linefeed_t; + +/* APIs */ +void mvSlicDialTone(unsigned int lineId); +void mvSlicStopTone(unsigned int lineId); +void mvSlicBusyTone(unsigned int lineId); +void mvSlicReorderTone(unsigned int lineId); +void mvSlicCongestionTone(unsigned int lineId); +void mvSlicRingbackPbxTone(unsigned int lineId); +void mvSlicRingBackTone(unsigned int lineId); +void mvSlicRingBackJapan(unsigned int lineId); +void mvSlicBusyJapanTone(unsigned int lineId); +void mvSlicStopRinging(unsigned int lineId); +void mvSlicActivateRinging(unsigned int lineId); +void mvSlicHookStateGet(unsigned short lineId, unsigned char* hookstate); +void mvSlicLinefeedControlSet(unsigned char lineId, mv_linefeed_t lfState); +void mvSlicLinefeedControlGet(unsigned char lineId, mv_linefeed_t* lfState); +MV_STATUS mvSlicInit(unsigned short first, unsigned short last, unsigned short pSlotInfo[][2], + unsigned short lines, mv_band_mode_t bandMode, mv_pcm_format_t pcmFormat); +void mvSlicRelease(void); +unsigned char mvSlicIntGet(unsigned int lineId); +void mvSlicReverseDcPolarity(unsigned char lineId); + +/********************************************STRUCTURES***********************************************/ + +/* STRUCTURES */ +typedef struct { + unsigned char address; + char *name; + unsigned short initial; +} indirectRegister; + +// enum state_type { BUSY, CALL_BACK, CALLING_BACK }; +typedef struct { + //unsigned char chip_number; + enum{ MAKEbUSY, STATEcHANGE,DIALtONE,INITIALIZING,POWERuP,CALIBRATE,PROGRAMMEDrING,POWERdOWN,POWERlEAKtEST, + MAKErINGbACKjAPAN, MAKEbUSYjAPAN, RINGbACKjAPAN, MAKErINGbACK,RINGbACK,MAKErEORDER,REORDER,MAKEcONGESTION,CONGESTION,PRENEON,NEON, + CALLBACKpROGRAMMED, BUSY, CALLBACK, CALLING, MAKEoFFHOOK,ONHOOK, OFFHOOK, DIGITDECODING, + LOOPtRANSITION, FIRSTrING, DEFEREDcALLBACKpROGRAMMED,CALLERiD,RINGING,DTMFtRANISTION} state,newState,previousState; + int digit_count; + char DTMF_digits[20]; + unsigned long interrupt; + unsigned char eventEnable; + unsigned char hook_status; + unsigned long On_Hook_time; + unsigned long Off_Hook_time; + char version,type; + struct{ enum { TYPE1, TYPE2, TYPE3 } ringType; + int nextCadenceEntryIndex; + } ringCadenceCordinates; + unsigned char ringCount; + int qLog[6]; + unsigned long eventNumber; +} chipStruct; + + +typedef struct { + unsigned short coeff; + unsigned short x; + unsigned short y; + union { + unsigned short onTime; + struct {unsigned char onLowByte;unsigned char onHiByte;} s1 ; + + } u1 ; + + union { + unsigned short offTime; + struct {unsigned char offLowByte;unsigned char offHiByte;} s2; + } u2 ; + + } ringStruct; + + +typedef struct { + unsigned short coeff; + unsigned short x; + unsigned short y; + unsigned char on_hi_byte; + unsigned char on_low_byte; + unsigned char off_hi_byte; + unsigned char off_low_byte; +} Oscillator; + + + + +typedef struct { + Oscillator osc1; + Oscillator osc2; +} tone_struct; + +typedef struct { +unsigned short frequency; +unsigned short coeff; +unsigned short x; +unsigned short y; +} coeffData; +void genTone(tone_struct tone, unsigned int lineId) ; + +typedef unsigned char DRDATA; + +/*#define $VERSION "PreRelease 2.0 ProSLIC Driver"*/ + +/* CONSTANTS */ + +#define LPT 0x378 + +#define IDA_LO 28 +#define IDA_HI 29 + +#define IAA 30 +#define CLOCK_MASK 0x04 +#define ID_ACCES_STATUS 31 +#define IAS_BIT 1 + +#define I_STATUS 31 + +#define SPI_MODE 0 +#define PCM_MODE 1 +#define PCM_XMIT_START_COUNT_LSB 2 +#define PCM_XMIT_START_COUNT_MSB 3 +#define PCM_RCV_START_COUNT_LSB 4 +#define PCM_RCV_START_COUNT_MSB 5 +#define DIO 6 + +#define AUDIO_LOOPBACK 8 +#define AUDIO_GAIN 9 +#define LINE_IMPEDANCE 10 +#define HYBRID 11 +#define RESERVED12 12 +#define RESERVED13 13 +#define PWR_DOWN1 14 +#define PWR_DOWN2 15 +#define RESERVED16 16 +#define RESERVED17 17 +#define INTRPT_STATUS1 18 +#define INTRPT_STATUS2 19 +#define INTRPT_STATUS3 20 +#define INTRPT_MASK1 21 +#define INTRPT_MASK2 22 +#define INTRPT_MASK3 23 +#define DTMF_DIGIT 24 +#define RESERVED25 25 +#define RESERVED26 26 +#define RESERVED27 27 +#define I_DATA_LOW 28 +#define I_DATA_HIGH 29 +#define I_ADDRESS 30 +#define I_STATUS 31 +#define OSC1 32 +#define OSC2 33 +#define RING_OSC_CTL 34 +#define PULSE_OSC 35 +#define OSC1_ON__LO 36 +#define OSC1_ON_HI 37 +#define OSC1_OFF_LO 38 +#define OSC1_OFF_HI 39 +#define OSC2_ON__LO 40 +#define OSC2_ON_HI 41 +#define OSC2_OFF_LO 42 +#define OSC2_OFF_HI 43 +#define PULSE_ON__LO 44 +#define PULSE_ON_HI 45 +#define PULSE_OFF_LO 46 +#define PULSE_OFF_HI 47 +#define RING_ON__LO 48 +#define RING_ON_HI 49 +#define RING_OFF_LO 50 +#define RING_OFF_HI 51 +#define FSK_DATA 52 /* 0 fsk_data */ +#define RESERVED53 53 +#define RESERVED54 54 +#define RESERVED55 55 +#define RESERVED56 56 +#define RESERVED57 57 +#define RESERVED58 58 +#define RESERVED59 59 +#define RESERVED60 60 +#define RESERVED61 61 +#define RESERVED62 62 +#define RESERVED63 63 +#define LINE_STATE 64 +#define ACTIVATE_LINE 0x11 +#define RING_LINE 0x44 +#define BIAS_SQUELCH 65 +#define BAT_FEED 66 +#define AUTO_STATE 67 +#define LOOP_STAT 68 +#define LOOP_DEBOUCE 69 +#define RT_DEBOUCE 70 +#define LOOP_I_LIMIT 71 +#define OFF_HOOK_V 72 +#define COMMON_V 73 +#define BAT_V_HI 74 +#define BAT_V_LO 75 +#define PWR_STAT_DEV 76 +#define PWR_STAT 77 +#define LOOP_V_SENSE 78 +#define LOOP_I_SENSE 79 +#define TIP_V_SENSE 80 +#define RING_V_SENSE 81 +#define BAT_V_HI_SENSE 82 +#define BAT_V_LO_SENSE 83 +#define IQ1 84 +#define IQ2 85 +#define IQ3 86 +#define IQ4 87 +#define IQ5 88 +#define IQ6 89 +#define RESERVED90 90 +#define RESERVED91 91 +#define DCDC_PWM_OFF 92 +#define DCDC 93 +#define DCDC_PW_OFF 94 +#define RESERVED95 95 +#define CALIBR1 96 +#define CALIBRATE_LINE 0x78 +#define NORMAL_CALIBRATION_COMPLETE 0x20 +#define CALIBR2 97 +#define RING_GAIN_CAL 98 +#define TIP_GAIN_CAL 99 +#define DIFF_I_CAL 100 +#define COMMON_I_CAL 101 +#define I_LIMIT_GAIN_CAL 102 +#define ADC_OFFSET_CAL 103 +#define DAC_ADC_OFFSET 104 +#define DAC_OFFSET_CAL 105 +#define COMMON_BAL_CAL 106 +#define DC_PEAK_CAL 107 + +// Indirect Register (decimal) +#define DTMF_ROW_0_PEAK 0 +#define DTMF_ROW_1_PEAK 1 +#define DTMF_ROW2_PEAK 2 +#define DTMF_ROW3_PEAK 3 +#define DTMF_COL1_PEAK 4 +#define DTMF_FWD_TWIST 5 +#define DTMF_RVS_TWIST 6 +#define DTMF_ROW_RATIO_THRESH 7 +#define DTMF_COL_RATIO_THRESH 8 +#define DTMF_ROW_2ND_HARM 9 +#define DTMF_COL_2ND_HARM 10 +#define DTMF_PWR_MIN_THRESH 11 +#define DTMF_HOT_LIM_THRESH 12 +#define OSC1_COEF 13 +#define OSC1X 14 +#define OSC1Y 15 +#define OSC2_COEF 16 +#define OSC2X 17 +#define OSC2Y 18 +#define RING_V_OFF 19 +#define RING_OSC_COEF 20 +#define RING_X 21 +#define RING_Y 22 +#define PULSE_ENVEL 23 +#define PULSE_X 24 +#define PULSE_Y 25 +#define RECV_DIGITAL_GAIN 26 +#define XMIT_DIGITAL_GAIN 27 +#define LOOP_CLOSE_THRESH 28 +#define RING_TRIP_THRESH 29 +#define COMMON_MIN_THRESH 30 +#define COMMON_MAX_THRESH 31 +#define PWR_ALARM_Q1Q2 32 +#define PWR_ALARM_Q3Q4 33 +#define PWR_ALARM_Q5Q6 34 +#define LOOP_CLOSURE_FILTER 35 +#define RING_TRIP_FILTER 36 +#define THERM_LP_POLE_Q1Q2 37 +#define THERM_LP_POLE_Q3Q4 38 +#define THERM_LP_POLE_Q5Q6 39 +#define CM_BIAS_RINGING 40 +#define DCDC_MIN_V 41 +#define DCDC_XTRA 42 +#define ALL_CHIPS 0x09 +#define NO_CHIPS 0 +#define REVC 108 /* 0 ilim_max fsk_revc dc_err_en zs_ext batsel_pd lcr_sense en_subtr hyst_en */ +#define FSK_X_0 99 /* x sign fsk_x_0[15:0] */ +#define FSK_COEFF_0 100 /* x sign fsk_coeff_0[15:0] */ +#define FSK_X_1 101 /* x sign fsk_x_1[15:0] */ +#define FSK_COEFF_1 102 /* x sign fsk_coeff_1[15:0] */ +#define FSK_X_01 103 /* x sign fsk_x_01[15:0] */ +#define FSK_X_10 104 /* x sign fsk_x_10[15:0] */ + +#ifdef REALNAMES + + +/* OPTIONAL CONSTANTS */ + +/**********************SETUP*****************************************/ +#define SPI_MODE 0 /* b00xxxxxx daisy_chn spi_mode part_num[1:0] revision[3:0] */ +#define PCM_MODE 1 /* 8 pcm_en pcm_fmt[1:0] pcm_size pcm_gci pcm_tri_0 */ +#define TX_START_LO 2 /* 0 tx_start[7:0] */ +#define TX_START_HI 3 /* 0 tx_start[9:8] */ +#define RX_START_LO 4 /* 0 rx_start[7:0] */ +#define RX_START_HI 5 /* 0 rx_start[9:8] */ +//#define GPIO 6 /* 0 relay_drv gpio1_dir gpio0_dir gpio1 gpio0 */ + // /* */ +///***********************AUDIO****************************************/ */ +#define LOOPBACK 8 /* 2 ana_lpbk2 dig_lpbk ana_lpbk */ +#define AUD_GAIN 9 /* 0 rx_hpf_dis tx_hpf_dis adc_mute dac_mute atx[1:0] arx[1:0] */ +#define ZSYNTH 10 /* 8 clcomp[1:0] zsynth_en zsynth[2:0] */ +#define HYBRID_CNTL 11 /* h44 hybp[2:0] hyba[2:0] */ +#define POWER DOWN /* */ +#define PDN1 14 /* b010000 pm_on dc_off mon_off pll_off bias_off slic_off */ +#define PDN2 15 /* 0 adc_man a_on_offb dac_man d_on_offb gm_man g_on_offb */ + + + +/***********************INTERRUPTS***********************************/ +#define IRQ_VEC1 18 /* 0 pulse_t2 pulse_t1 ring_t2 ring_t1 osc2_t2 osc2_t1 osc1_t2 osc1_t1 */ +#define IRQ_VEC2 19 /* 0 pq6 pq5 pq4 pq3 pq2 pq1 loop_stat ring_trip */ +#define IRQ_VEC3 20 /* 0 cal_cm_bal indirect dtmf */ +#define IRQ_MASK1 21 /* 0 pulse_t2 pulse_t1 ring_t2 ring_t1 osc2_t2 osc2_t1 osc1_t2 osc1_t1 */ +#define IRQ_MASK2 22 /* 0 pq6 pq5 pq4 pq3 pq2 pq1 loop_stat ring_trip */ +#define IRQ_MASK3 23 /* 0 cal_cm_bal indirect dtmf */ +#define DTMF 24 /* 0 valid dtmf_digit[3:0] */ +#define PASS_LO 25 /* 0 dtmf_pass[7:0] */ +#define PASS_HI 26 /* 0 dtmf_pass[9:8] */ + +/******************INDIRECT REGISTER ACCESS ***************************/ +#define IND_DATA_LO 28 /* 0 ind_data[7:0] */ +#define IND_DATA_HI 29 /* 0 ind_data[15:8] */ +#define IND_ADDR 30 /* 0 ind_add[7:0] */ +#define IND_STAT 31 /* 0 ind_add[8] ind_stat */ + + +/**************************OSCILLATORS**********************************/ +#define OSC1_CNTL 32 /* 0 en_sync reload zero_en t1_en t2_en enable routing[1:0] */ +#define OSC2_CNTL 33 /* 0 en_sync zero_en t1_en t2_en enable routing[1:0] */ +#define RING_CNTL 34 /* 0 en_sync ring_dac t1_en t2_en ring_en offset trap */ +#define PULSE_CNTL 35 /* 0 en_sync zero_en t1_en t2_en enable env_en */ +#define OSC1_T1_LO 36 /* 0 osc1_t1[7:0] */ +#define OSC1_T1_HI 37 /* 0 osc1_t1[15:8] */ +#define OSC1_T2_LO 38 /* 0 osc1_t2[7:0] */ +#define OSC1_T2_HI 39 /* 0 osc1_t2[15:8] */ +#define OSC2_T1_LO 40 /* 0 osc2_t1[7:0] */ +#define OSC2_T1_HI 41 /* 0 osc2_t1[15:8] */ +#define OSC2_T2_LO 42 /* 0 osc2_t2[7:0] */ +#define OSC2_T2_HI 43 /* 0 osc2_t2[15:8] */ +#define PULSE_T1_LO 44 /* 0 pulse_t1[7:0] */ +#define PULSE_T1_HI 45 /* 0 pulse_t1[15:8] */ +#define PULSE_T2_LO 46 /* 0 pulse_t2[7:0] */ +#define PULSE_T2_HI 47 /* 0 pulse_t2[15:8] */ +#define RING_T1_LO 48 /* 0 ring_t1[7:0] */ +#define RING_T1_HI 49 /* 0 ring_t1[15:8] */ +#define RING_T2_LO 50 /* 0 ring_t2[7:0] */ +#define RING_T2_HI 51 /* 0 ring_t2[15:8] */ +#define FSK_DATA 52 /* 0 fsk_data */ + +/***************************** SLIC *********************************************/ + +#define DBI_LCR_RING 63 /* 52 dbi_lcr_ring[6:0] */ +#define LINEFEED 64 /* 0 linefeed_shadow[2:0] linefeed[2:0] */ +#define BJTBIAS 65 /* b1100001 squelch cap_bypass en_bjtbias bjtbias_oht[1:0] bjtbias_act[1:0] */ +#define BAT_CNTL 66 /* b1011 vov_1p5 set_vreg extbat batsel track */ +#define AUTO 67 /* b0011111 mancm mandiff en_speedup autobat autord autold autoopen */ +#define LCR_RTP 68 /* 0 dbi_raw rtp lcr */ +#define DBI_LCR 69 /* 10 dbi_lcr[6:0] */ +#define DBI_RTP 70 /* 10 dbi_rtp[6:0] */ +#define ILIM 71 /* 0 ilim[2:0] */ +#define VOC 72 /* 32 vocsgn voc[5:0] */ +#define VCM 73 /* 2 vcm[5:0] */ +#define VBATH 74 /* 50 vbath[5:0] */ +#define VBATL 75 /* 16 vbatl[5:0] */ +#define PWR_PTR 76 /* 0 pwr_ptr[2:0] */ +#define PWR_OUT 77 /* 0 pwr_out[7:0] */ +#define LVS 78 /* 0 lvs[6:0] */ +#define LCS 79 /* 0 lcs[6:0] */ +#define VTIP 80 /* 0 vtip[7:0] */ +#define VRING 81 /* 0 vring[7:0] */ +#define VREG1 82 /* 0 vreg1[7:0] */ +#define VREG2 83 /* 0 vreg2[7:0] */ +#define IQ1 84 /* 0 iq1[7:0] */ +#define IQ2 85 /* 0 iq2[7:0] */ +#define IQ3 86 /* 0 iq3[7:0] */ +#define IQ4 87 /* 0 iq4[7:0] */ +#define IQ5 88 /* 0 iq5[7:0] */ +#define IQ6 89 /* 0 iq6[7:0] */ + +/********************** DC/DC************************************************/ +#define DC_N 92 /* 255 dc_n[7:0] */ +#define DC_S_DELAY 93 /* 20 dcdc_cal dc_ff dc_s_delay[4:0] */ +#define DC_X 94 /* 0 dc_x[7:0] */ +#define DC_ERR 95 /* x dc_err[2:0] */ + +/************************CALIBRATION****************************************/ +#define CAL_R1 96 /* h1f cal cal_spdup cal_gmisr cal_gmist cal_ding cal_cing cal_ilim */ +#define CAL_R2 97 /* h1f cal_madc1 cal_madc2 cal_dac_o cal_adc_o cal_cm_bal */ +#define CAL_GMIS_ICR 98 /* 16 cal_gmis_icr[4:0] */ +#define CAL_GMIS_ICT 99 /* 16 cal_gmis_ict[4:0] */ +#define CAL_DIN_GAIN 100 /* 17 cal_din_gain[4:0] */ +#define CAL_CIN_GAIN 101 /* 17 cal_cin_gain[4:0] */ +#define CAL_ILIM 102 /* 8 cal_ilim[3:0] */ +#define CAL_MADC 103 /* h88 cal_madc_gm2[3:0] cal_madc_gm1[3:0] */ +#define CAL_DAC_O_A 104 /* 0 dac_os_p dac_os_n adc_os_p adc_os_n */ +#define CAL_DAC_O_D 105 /* 0 dac_offset[7:0] */ +#define CAL_CM_BAL 106 /* h20 cm_bal[5:0] */ +#define CAL_DCPK 107 /* 8 cal_dcpk[3:0] */ + + +#define REVC 108 /* 0 ilim_max fsk_revc dc_err_en zs_ext batsel_pd lcr_sense en_subtr hyst_en */ + + +/* INDIRECT REGISTERS */ + +/* Name # D b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 */ + +/* DTMF (Constant values provided by Silabs after DTMF performance evaluation) */ +#define ROW0_THR 0 /* x sign row0_thr[11:0] */ +#define ROW1_THR 1 /* x sign row1_thr[11:0] */ +#define ROW2_THR 2 /* x sign row2_thr[11:0] */ +#define ROW3_THR 3 /* x sign row3_thr[11:0] */ +#define COL_THR 4 /* x sign col_thr[11:0] */ +#define FWD_TW_THR 5 /* x sign fwd_tw_thr[7:0] */ +#define REV_TW_THR 6 /* x sign rev_tw_thr[7:0] */ +#define ROW_REL_THR 7 /* x sign row_rel_thr[7:0] */ +#define COL_REL_THR 8 /* x sign col_rel_thr[7:0] */ +#define ROW_2ND_THR 9 /* x sign row_2nd_thr[7:0] */ +#define COL_2ND_THR 10 /* x sign col_2nd_thr[7:0] */ +#define PWR_MIN_THR 11 /* x sign pwr_min_thr[15:0] */ +#define HOT_LIMIT 12 /* x sign hot_limit[15:0] */ + +/* OSCILLATORS (See descriptions of tone generation, ringing and pulse metering for quidelines on computing register values) */ +#define OSC1_COEFF 13 /* x sign osc1_coeff[15:0] */ +#define OSC1_X_REG 14 /* x sign osc1_x_reg[15:0] */ +#define OSC1_Y_REG 15 /* x sign osc1_y_reg[15:0] */ +#define OSC2_COEFF 16 /* x sign osc2_coeff[15:0] */ +#define OSC2_X_REG 17 /* x sign osc2_x_reg[15:0] */ +#define OSC2_Y_REG 18 /* x sign osc2_y_reg[15:0] */ +#define RING_OFFSET 19 /* x sign ring_offset[15:0] */ +#define RING_COEFF 20 /* x sign ring_coeff[15:0] */ +#define RING_X_REG 21 /* x sign ring_x_reg[15:0] */ +#define RING_Y_REG 22 /* x sign ring_y_reg[15:0] */ +#define PULSE_DELTA 23 /* x sign pulse_delta[15:0] */ +#define PULSE_X_REG 24 /* x sign pulse_x_reg[15:0] */ +#define PULSE_COEFF 25 /* x sign pulse_coeff[15:0] */ + +/* PGAs (See description of PGA for quidelines on computing register values) */ +#define DAC_GAIN 26 /* x sign dac_gain[11:0] */ +#define ADC_GAIN 27 /* x sign adc_gain[11:0] */ + +/* SLIC CONTROL */ +#define LCR_THR 28 /* 0 lcr_thr_high[5:0] */ +#define RTP_THR 29 /* 0 rtp_thr[5:0] */ +#define CM_LOW_THR 30 /* 0 0 0 cm_low_thr[5:0] */ +#define CM_HIGH_THR 31 /* 0 0 0 cm_high_thr[5:0] */ +#define PPTHR12 32 /* 0 ppthr12[7:0] */ +#define PPTHR34 33 /* 0 ppthr34[7:0] */ +#define NPTHR56 34 /* 0 npthr56[7:0] */ +#define NLCR 35 /* nclr[12:0] */ +#define NRTP 36 /* nrtp[12:0] */ +#define NQ12 37 /* nq12[12:0] */ +#define NQ34 38 /* nq34[12:0] */ +#define NQ56 39 /* nq56[12:0] */ +#define VCM_RING_DELTA 40 /* 0 0 0 vcm_ring_delta[3:0] */ +#define VMIN_DELTA 41 /* 0 0 0 vmin_delta[3:0] */ +#define VXTRA_DELTA 42 /* 0 0 0 vxtra_delta[3:0] */ +#define LCR_THR2 43 /* 0 lcr_thr_low[5:0] */ + +#define FSK_X_0 99 /* x sign fsk_x_0[15:0] */ +#define FSK_COEFF_0 100 /* x sign fsk_coeff_0[15:0] */ +#define FSK_X_1 101 /* x sign fsk_x_1[15:0] */ +#define FSK_COEFF_1 102 /* x sign fsk_coeff_1[15:0] */ +#define FSK_X_01 103 /* x sign fsk_x_01[15:0] */ +#define FSK_X_10 104 /* x sign fsk_x_10[15:0] */ + + + + + +#endif /* REAL NAMES */ + + +enum exceptions { + PROSLICiNSANE, + TIMEoUTpOWERuP, + TIMEoUTpOWERdOWN, + POWERlEAK, + TIPoRrINGgROUNDsHORT, + POWERaLARMQ1, + POWERaLARMQ2, + POWERaLARMQ3, + POWERaLARMQ4, + POWERaLARMQ5, + POWERaLARMQ6 +}; + + + +#define SI3210_DIALTONE_IR13 0x7b30 //tone_struct DialTone = { /* OSC1= 350 Hz OSC2= 440 Hz .0975 Volts -18 dBm */ +#define SI3210_DIALTONE_IR14 0x0063 +#define SI3210_DIALTONE_IR16 0x7870 +#define SI3210_DIALTONE_IR17 0x007d + +#define SI3215_DIALTONE_IR13 0x7eca //tone_struct DialTone = { /* OSC1= 350 Hz OSC2= 440 Hz .0975 Volts -18 dBm */ +#define SI3215_DIALTONE_IR14 0x0031 +#define SI3215_DIALTONE_IR16 0x7e18 +#define SI3215_DIALTONE_IR17 0x003e + +#define DIALTONE_DR32 6 +#define DIALTONE_DR33 6 +#define DIALTONE_DR36 0 +#define DIALTONE_DR37 0 +#define DIALTONE_DR38 0 +#define DIALTONE_DR39 0 +#define DIALTONE_DR40 0 +#define DIALTONE_DR41 0 +#define DIALTONE_DR42 0 +#define DIALTONE_DR43 0 + + + +#define SI3210_REORDERTONE_IR13 0x7700 //"//tone_struct ReorderTone = { /* OSC1= 480 Hz OSC2 = 620 .0975 Volts -18 dBm */" +#define SI3210_REORDERTONE_IR14 0x0089 +#define SI3210_REORDERTONE_IR16 0x7120 +#define SI3210_REORDERTONE_IR17 0x00B2 + +#define SI3215_REORDERTONE_IR13 0x7DBB //"//tone_struct ReorderTone = { /* OSC1= 480 Hz OSC2 = 620 .0975 Volts -18 dBm */" +#define SI3215_REORDERTONE_IR14 0x0044 +#define SI3215_REORDERTONE_IR16 0x7C39 +#define SI3215_REORDERTONE_IR17 0x0058 + + +#define REORDERTONE_DR32 0x1E +#define REORDERTONE_DR33 0x1E +#define REORDERTONE_DR36 0x60 +#define REORDERTONE_DR37 0x09 +#define REORDERTONE_DR38 0x40 +#define REORDERTONE_DR39 0x06 +#define REORDERTONE_DR40 0x60 +#define REORDERTONE_DR41 0x09 +#define REORDERTONE_DR42 0x40 +#define REORDERTONE_DR43 0x06 + + +//one_struct BusySignal = { /* OSC1= 480 OSC2 = 620 .0975 Voltz -18 dBm 8*/ +// {0x7700,0x0089,0,0x0f,0xa0,0x0f,0xa0},{0x7120,0x00b2,0,0x0f,0xa0,0x0f,0xa0} +//}; +#define SI3210_BUSYTONE_IR13 0x7700 //tone_struct BusySignal = { /* OSC1= 480 OSC2 = 620 .0975 Voltz -18 dBm 8*/ +#define SI3210_BUSYTONE_IR14 0x0089 +#define SI3210_BUSYTONE_IR16 0x7120 +#define SI3210_BUSYTONE_IR17 0x00B2 + +#define SI3215_BUSYTONE_IR13 0x7DBB //tone_struct BusySignal = { /* OSC1= 480 OSC2 = 620 .0975 Voltz -18 dBm 8*/ +#define SI3215_BUSYTONE_IR14 0x0044 +#define SI3215_BUSYTONE_IR16 0x7C39 +#define SI3215_BUSYTONE_IR17 0x0058 + +#define BUSYTONE_DR32 0x1E +#define BUSYTONE_DR33 0x1E +#define BUSYTONE_DR36 0xa0 +#define BUSYTONE_DR37 0x0f +#define BUSYTONE_DR38 0xa0 +#define BUSYTONE_DR39 0x0f +#define BUSYTONE_DR40 0xa0 +#define BUSYTONE_DR41 0x0f +#define BUSYTONE_DR42 0xa0 +#define BUSYTONE_DR43 0x0f + +//tone_struct RingbackNormal = { /* OSC1 = 440 Hz OSC2 = 480 .0975 Volts -18 dBm */ +#define SI3210_RINGBACKTONE_IR13 0x7870 +#define SI3210_RINGBACKTONE_IR14 0x007D +#define SI3210_RINGBACKTONE_IR16 0x7700 +#define SI3210_RINGBACKTONE_IR17 0x0089 + +#define SI3215_RINGBACKTONE_IR13 0x7E18 +#define SI3215_RINGBACKTONE_IR14 0x003E +#define SI3215_RINGBACKTONE_IR16 0x7DBB +#define SI3215_RINGBACKTONE_IR17 0x0044 + +#define RINGBACKTONE_DR32 0x1E +#define RINGBACKTONE_DR33 0x1E +#define RINGBACKTONE_DR36 0x80 +#define RINGBACKTONE_DR37 0x3E +#define RINGBACKTONE_DR38 0x0 +#define RINGBACKTONE_DR39 0x7d +#define RINGBACKTONE_DR40 0x80 +#define RINGBACKTONE_DR41 0x3E +#define RINGBACKTONE_DR42 0x0 +#define RINGBACKTONE_DR43 0x7d + +#define SI3210_RINGBACKPBXTONE_IR13 0x7870 // "//tone_struct RingbackPBX = { /* OSC1 = 440 Hz OSC2= 480 .0975 Volts -18 dBM */" +#define SI3210_RINGBACKPBXTONE_IR14 0x007D +#define SI3210_RINGBACKPBXTONE_IR16 0x7700 +#define SI3210_RINGBACKPBXTONE_IR17 0x0089 + +#define SI3215_RINGBACKPBXTONE_IR13 0x7E18 // "//tone_struct RingbackPBX = { /* OSC1 = 440 Hz OSC2= 480 .0975 Volts -18 dBM */" +#define SI3215_RINGBACKPBXTONE_IR14 0x003E +#define SI3215_RINGBACKPBXTONE_IR16 0x7DBB +#define SI3215_RINGBACKPBXTONE_IR17 0x0044 + +#define RINGBACKPBXTONE_DR32 0x1E +#define RINGBACKPBXTONE_DR33 0x1E +#define RINGBACKPBXTONE_DR36 0x40 +#define RINGBACKPBXTONE_DR37 0x1f +#define RINGBACKPBXTONE_DR38 0xc0 +#define RINGBACKPBXTONE_DR39 0x5d +#define RINGBACKPBXTONE_DR40 0x40 +#define RINGBACKPBXTONE_DR41 0x1f +#define RINGBACKPBXTONE_DR42 0xc0 +#define RINGBACKPBXTONE_DR43 0x5d + +#define SI3210_CONGESTIONTONE_IR13 0x7700 //tone_struct CongestionTone = { /* OSC1= 480 Hz OSC2 = 620 .0975 Volts -18 dBM */ +#define SI3210_CONGESTIONTONE_IR14 0x0089 +#define SI3210_CONGESTIONTONE_IR16 0x7120 +#define SI3210_CONGESTIONTONE_IR17 0x00B2 + +#define SI3215_CONGESTIONTONE_IR13 0x7DBB //tone_struct CongestionTone = { /* OSC1= 480 Hz OSC2 = 620 .0975 Volts -18 dBM */ +#define SI3215_CONGESTIONTONE_IR14 0x0044 +#define SI3215_CONGESTIONTONE_IR16 0x7C39 +#define SI3215_CONGESTIONTONE_IR17 0x0058 + +#define CONGESTIONTONE_DR32 0x1E +#define CONGESTIONTONE_DR33 0x1E +#define CONGESTIONTONE_DR36 0x40 +#define CONGESTIONTONE_DR37 0x06 +#define CONGESTIONTONE_DR38 0x60 +#define CONGESTIONTONE_DR39 0x09 +#define CONGESTIONTONE_DR40 0x40 +#define CONGESTIONTONE_DR41 0x06 +#define CONGESTIONTONE_DR42 0x60 +#define CONGESTIONTONE_DR43 0x09 + + +#define HZ350_IR13 0x7b30 //350 /* HERTZ */, 0x7b30, 0x0063, +#define HZ350_IR14 0x0063 + +#define HZ440_IR13 0x7870 //440 /* HERTZ */ ,0x7870, 0x007d, +#define HZ440_IR14 0x007d + +#define HZ480_IR13 0x7700 //480 /* HERTZ */, 0x7700, 0x0089, +#define HZ480_IR14 0x0089 + +#define HZ620_IR13 0x7120 //620 /* HERTZ */, 0x7120, 0x00b2, +#define HZ620_IR14 0x00b2 + +#define HZ200_IR13 0x7e70 //200 /* HERTZ */, 0x7e70, 0x0038, +#define HZ200_IR14 0x0038 + +#define HZ300_IR13 0x7c70 //300 /* HERTZ */, 0x7c70, 0x0055, +#define HZ300_IR14 0x0055 + +#define HZ400_IR13 0x79c0 //400 /* HERTZ */, 0x79c0, 0x0071 +#define HZ400_IR14 0x0071 + + +#define DTMF0_IR13 0x5ea0 "// {{0x5ea0,0x08a5,0,0x03,0x20,0,0}, {0x3fc0,0x0cec,0,0x03,0x20,0,0}}, // DTMF 0" +#define DTMF0_IR14 0x08a5 +#define DTMF0_IR16 0x3fc0 +#define DTMF0_IR17 0x0cec +#define DTMF0_DR32 0x1E +#define DTMF0_DR33 0x1E +#define DTMF0_DR36 0x03 +#define DTMF0_DR37 0x20 +#define DTMF0_DR38 0x03 +#define DTMF0_DR39 0x60 +#define DTMF0_DR40 0x40 +#define DTMF0_DR41 0x20 +#define DTMF0_DR42 0x60 +#define DTMF0_DR43 0x09 + +#define DTMF1_IR13 0x6d50 "// {{0x6d50,0x0643,0,0x03,0x20,0,0}, {0x4a80,0x0b79,0,0x03,0x20,0,0}}, // DTMF 1" +#define DTMF1_IR14 0x0643 +#define DTMF1_IR16 0x4a80 +#define DTMF1_IR17 0x0b79 +#define DTMF1_DR32 0x1E +#define DTMF1_DR33 0x1E +#define DTMF1_DR36 0x20 +#define DTMF1_DR37 0x03 +#define DTMF1_DR38 0 +#define DTMF1_DR39 0 +#define DTMF1_DR40 0x20 +#define DTMF1_DR41 0x03 +#define DTMF1_DR42 0 +#define DTMF1_DR43 0 + +#define DTMF2_IR13 0x6d50 "// {{0x6d50,0x0643,0,0x03,0x20,0,0}, {0x3fc0,0x0cec,0,0x03,0x20,0,0}}, // DTMF 2" +#define DTMF2_IR14 0x0643 +#define DTMF2_IR16 0x3fc0 +#define DTMF2_IR17 0x0cec +#define DTMF2_DR32 0x1E +#define DTMF2_DR33 0x1E +#define DTMF2_DR36 0x20 +#define DTMF2_DR37 0x03 +#define DTMF2_DR38 0 +#define DTMF2_DR39 0 +#define DTMF2_DR40 0x20 +#define DTMF2_DR41 0x03 +#define DTMF2_DR42 0 +#define DTMF2_DR43 0 + +#define DTMF3_IR13 0x6d50 "// {{0x6d50,0x0643,0,0x03,0x20,0,0}, {0x3320,0x0ea0,0,0x03,0x20,0,0}}, // DTMF 3" +#define DTMF3_IR14 0x0643 +#define DTMF3_IR16 0x3320 +#define DTMF3_IR17 0x0ea0 +#define DTMF3_DR32 0x1E +#define DTMF3_DR33 0x1E +#define DTMF3_DR36 0x20 +#define DTMF3_DR37 0x03 +#define DTMF3_DR38 0 +#define DTMF3_DR39 0 +#define DTMF3_DR40 0x20 +#define DTMF3_DR41 0x03 +#define DTMF3_DR42 0 +#define DTMF3_DR43 0 + +#define DTMF4_IR13 0x6950 "// {{0x6950,0x06f6,0,0x03,0x20,0,0}, {0x4a80,0x0b79,0,0x03,0x20,0,0}}, // DTMF 4" +#define DTMF4_IR14 0x0616 +#define DTMF4_IR16 0x4a80 +#define DTMF4_IR17 0x0b79 +#define DTMF4_DR32 0x1E +#define DTMF4_DR33 0x1E +#define DTMF4_DR36 0x20 +#define DTMF4_DR37 0x03 +#define DTMF4_DR38 0 +#define DTMF4_DR39 0 +#define DTMF4_DR40 0x20 +#define DTMF4_DR41 0x03 +#define DTMF4_DR42 0 +#define DTMF4_DR43 0 + +#define DTMF5_IR13 0x6950 "// {{0x6950,0x06f6,0,0x03,0x20,0,0}, {0x3fc0,0x0cec,0,0x03,0x20,0,0}}, // DTMF 5" +#define DTMF5_IR14 0x0616 +#define DTMF5_IR16 0x3fc0 +#define DTMF5_IR17 0x0cec +#define DTMF5_DR32 0x1E +#define DTMF5_DR33 0x1E +#define DTMF5_DR36 0x20 +#define DTMF5_DR37 0x03 +#define DTMF5_DR38 0 +#define DTMF5_DR39 0 +#define DTMF5_DR40 0x20 +#define DTMF5_DR41 0x03 +#define DTMF5_DR42 0 +#define DTMF5_DR43 0 + +#define DTMF6_IR13 0x6950 "// {{0x6950,0x06f6,0,0x03,0x20,0,0}, {0x3320,0x0ea0,0,0x03,0x20,0,0}}, // DTMF 6" +#define DTMF6_IR14 0x0616 +#define DTMF6_IR16 0x3320 +#define DTMF6_IR17 0xea0 +#define DTMF6_DR32 0x1E +#define DTMF6_DR33 0x1E +#define DTMF6_DR36 0x20 +#define DTMF6_DR37 0x03 +#define DTMF6_DR38 0 +#define DTMF6_DR39 0 +#define DTMF6_DR40 0x20 +#define DTMF6_DR41 0x03 +#define DTMF6_DR42 0 +#define DTMF6_DR43 0 + +#define DTMF7_IR13 0x6460 "// {{0x6460,0x07c3,0,0x03,0x20,0,0}, {0x4a80,0x0b79,0,0x03,0x20,0,0}}, // DTMF 7" +#define DTMF7_IR14 0x07c3 +#define DTMF7_IR16 0x4a80 +#define DTMF7_IR17 0x0b79 +#define DTMF7_DR32 0x1E +#define DTMF7_DR33 0x1E +#define DTMF7_DR36 0x20 +#define DTMF7_DR37 0x03 +#define DTMF7_DR38 0 +#define DTMF7_DR39 0 +#define DTMF7_DR40 0x20 +#define DTMF7_DR41 0x03 +#define DTMF7_DR42 0 +#define DTMF7_DR43 0 + +#define DTMF8_IR13 0x6460 "// {{0x6460,0x07c3,0,0x03,0x20,0,0}, {0x3fc0,0x0cec,0,0x03,0x20,0,0}}, // DTMF 8" +#define DTMF8_IR14 0x07c3 +#define DTMF8_IR16 0x3fc0 +#define DTMF8_IR17 0x0cec +#define DTMF8_DR32 0x1E +#define DTMF8_DR33 0x1E +#define DTMF8_DR36 0x20 +#define DTMF8_DR37 0x03 +#define DTMF8_DR38 0 +#define DTMF8_DR39 0 +#define DTMF8_DR40 0x20 +#define DTMF8_DR41 0x03 +#define DTMF8_DR42 0 +#define DTMF8_DR43 0 + +#define DTMF9_IR13 0x6460 "// {{0x6460,0x07c3,0,0x03,0x20,0,0}, {0x3320,0x0ea0,0,0x03,0x20,0,0}}, // DTMF 9" +#define DTMF9_IR14 0x07c3 +#define DTMF9_IR16 0x3320 +#define DTMF9_IR17 0x0ea0 +#define DTMF9_DR32 0x1E +#define DTMF9_DR33 0x1E +#define DTMF9_DR36 0x20 +#define DTMF9_DR37 0x03 +#define DTMF9_DR38 0 +#define DTMF9_DR39 0 +#define DTMF9_DR40 0x20 +#define DTMF9_DR41 0x03 +#define DTMF9_DR42 0 +#define DTMF9_DR43 0 + +#define DTMFA_IR13 0x6d50 "// {{0x6d50,0x0643,0,0x03,0x20,0,0}, {0x2460,0x10ab,0,0x03,0x20,0,0}}, // DTMF A" +#define DTMFA_IR14 0x0643 +#define DTMFA_IR16 0x2460 +#define DTMFA_IR17 0x10ab +#define DTMFA_DR32 0x1E +#define DTMFA_DR33 0x1E +#define DTMFA_DR36 0x20 +#define DTMFA_DR37 0x03 +#define DTMFA_DR38 0 +#define DTMFA_DR39 0 +#define DTMFA_DR40 0x20 +#define DTMFA_DR41 0x03 +#define DTMFA_DR42 0 +#define DTMFA_DR43 0 + +#define DTMFB_IR13 0x6950 "// {{0x6950,0x06f6,0,0x03,0x20,0,0}, {0x2460,0x10ab,0,0x03,0x20,0,0}}, // DTMF B" +#define DTMFB_IR14 0x0616 +#define DTMFB_IR16 0x2460 +#define DTMFB_IR17 0x10ab +#define DTMFB_DR32 0x1E +#define DTMFB_DR33 0x1E +#define DTMFB_DR36 0x20 +#define DTMFB_DR37 0x03 +#define DTMFB_DR38 0 +#define DTMFB_DR39 0 +#define DTMFB_DR40 0x20 +#define DTMFB_DR41 0x03 +#define DTMFB_DR42 0 +#define DTMFB_DR43 0 + +#define DTMFC_IR13 0x6460 "// {{0x6460,0x07c3,0,0x03,0x20,0,0}, {0x2460,0x10ab,0,0x03,0x20,0,0}}, // DTMF C" +#define DTMFC_IR14 0x07c3 +#define DTMFC_IR16 0x2460 +#define DTMFC_IR17 0x10ab +#define DTMFC_DR32 0x1E +#define DTMFC_DR33 0x1E +#define DTMFC_DR36 0x20 +#define DTMFC_DR37 0x03 +#define DTMFC_DR38 0 +#define DTMFC_DR39 0 +#define DTMFC_DR40 0x20 +#define DTMFC_DR41 0x03 +#define DTMFC_DR42 0 +#define DTMFC_DR43 0 + +#define DTMFD_IR13 0x5ea0 "// {{0x5ea0,0x08a5,0,0x03,0x20,0,0}, {0x2460,0x10ab,0,0x03,0x20,0,0}} // DTMF D" +#define DTMFD_IR14 0x08a5 +#define DTMFD_IR16 0x2460 +#define DTMFD_IR17 0x10ab +#define DTMFD_DR32 0x1E +#define DTMFD_DR33 0x1E +#define DTMFD_DR36 0x20 +#define DTMFD_DR37 0x03 +#define DTMFD_DR38 0 +#define DTMFD_DR39 0 +#define DTMFD_DR40 0x20 +#define DTMFD_DR41 0x03 +#define DTMFD_DR42 0 +#define DTMFD_DR43 0 + +#define DTMFstar_IR13 0x5ea0 "// {{0x5ea0,0x08a5,0,0x03,0x20,0,0}, {0x4a80,0x0b79,0,0x03,0x20,0,0}}, // DTMF star" +#define DTMFstar_IR14 0x8a50 +#define DTMFstar_IR16 0x4a80 +#define DTMFstar_IR17 0x0b79 +#define DTMFstar_DR32 0x1E +#define DTMFstar_DR33 0x1E +#define DTMFstar_DR36 0x20 +#define DTMFstar_DR37 0x03 +#define DTMFstar_DR38 0 +#define DTMFstar_DR39 0 +#define DTMFstar_DR40 0x20 +#define DTMFstar_DR41 0x03 +#define DTMFstar_DR42 0 +#define DTMFstar_DR43 0 + +#define DTMFhash_IR13 0x5ae0 "// {{0x5ea0,0x08a5,0,0x03,0x20,0,0}, {0x3320,0x0ea0,0,0x03,0x20,0,0}}, // DTMF #" +#define DTMFhash_IR14 0x08a5 +#define DTMFhash_IR16 0x3320 +#define DTMFhash_IR17 0x0ea0 +#define DTMFhash_DR32 0x1E +#define DTMFhash_DR33 0x1E +#define DTMFhash_DR36 0x20 +#define DTMFhash_DR37 0x03 +#define DTMFhash_DR38 0 +#define DTMFhash_DR39 0 +#define DTMFhash_DR40 0x20 +#define DTMFhash_DR41 0x03 +#define DTMFhash_DR42 0 +#define DTMFhash_DR43 0 + + +#define PULSE_METERING_IR24 0x3190 +#define PULSE_METERING_IR25 0x4FF +#define PULSE_METERING_DR35 0x10 +#define PULSE_METERING_DR44 0x60 0x04 +#define PULSE_METERING_DR45 0x04 0x60 +#define PULSE_METERING_DR46 0x60 0x04 +#define PULSE_METERING_DR47 0x04 0x60 + +#define RINGING_20HZ_IR19 0 //offset voltage +#define RINGING_20HZ_IR20 0x7F00 +#define RINGING_20HZ_IR21 0x013D +#define RINGING_20HZ_DR34 0X18 +#define RINGING_20HZ_DR48 0x80 +#define RINGING_20HZ_DR49 0x3e +#define RINGING_20HZ_DR50 0x7d +#define RINGING_20HZ_DR51 0 + + + + + + +//tone_struct DialTone = { /* OSC1= 350 Hz OSC2= 440 Hz .0975 Volts -18 dBm */ +// {0x7ed0,0x0031,0,0,0,0,0},{0x7e20,0x003d,0,0,0,0,0} +//}; + +#define DIALTONE_SI3216_IR13 0x7ed0 +#define DIALTONE_SI3216_IR14 0x0031 +#define DIALTONE_SI3216_IR16 0x7e20 +#define DIALTONE_SI3216_IR17 0x003d +#define DIALTONE_SI3216_DR32 6 +#define DIALTONE_SI3216_DR33 6 +#define DIALTONE_SI3216_DR36 0 +#define DIALTONE_SI3216_DR37 0 +#define DIALTONE_SI3216_DR38 0 +#define DIALTONE_SI3216_DR39 0 +#define DIALTONE_SI3216_DR40 0 +#define DIALTONE_SI3216_DR41 0 +#define DIALTONE_SI3216_DR42 0 +#define DIALTONE_SI3216_DR43 0 + +//tone_struct ReorderTone = { /* OSC1= 480 Hz OSC2 = 620 .0975 Volts -18 dBm */ +// {0x7dc0,0x0043,0,0x09,0x60,0x06,0x40},{0x7c40,0x0057,0,0x09,0x60,0x06,0x40} +//}; + +#define REORDERTONE_SI3216_IR13 0x7dc0 +#define REORDERTONE_SI3216_IR14 0x0043 +#define REORDERTONE_SI3216_IR16 0x7c40 +#define REORDERTONE_SI3216_IR17 0x0057 +#define REORDERTONE_SI3216_DR32 0x1E +#define REORDERTONE_SI3216_DR33 0x1E +#define REORDERTONE_SI3216_DR36 0x60 +#define REORDERTONE_SI3216_DR37 0x09 +#define REORDERTONE_SI3216_DR38 0x40 +#define REORDERTONE_SI3216_DR39 0x06 +#define REORDERTONE_SI3216_DR40 0x60 +#define REORDERTONE_SI3216_DR41 0x09 +#define REORDERTONE_SI3216_DR42 0x40 +#define REORDERTONE_SI3216_DR43 0x06 + +//tone_struct CongestionTone = { /* OSC1= 480 Hz OSC2 = 620 .0975 Volts -18 dBM */ +// {0x7dc0,0x0043,0,0x06,0x40,0x09,0x60},{0x7c40,0x0057,0,0x06,0x40,0x09,0x60} +//}; + + +#define BUSYTONE_SI3216_IR13 0x7dc0 +#define BUSYTONE_SI3216_IR14 0x0043 +#define BUSYTONE_SI3216_IR16 0x7c40 +#define BUSYTONE_SI3216_IR17 0x0057 +#define BUSYTONE_SI3216_DR32 0x1E +#define BUSYTONE_SI3216_DR33 0x1E +#define BUSYTONE_SI3216_DR36 0xa0 +#define BUSYTONE_SI3216_DR37 0x0f +#define BUSYTONE_SI3216_DR38 0xa0 +#define BUSYTONE_SI3216_DR39 0x0f +#define BUSYTONE_SI3216_DR40 0xa0 +#define BUSYTONE_SI3216_DR41 0x0f +#define BUSYTONE_SI3216_DR42 0xa0 +#define BUSYTONE_SI3216_DR43 0x0f + + +//tone_struct RingbackPBX = { /* OSC1 = 440 Hz OSC2= 480 .0975 Volts -18 dBM */ +// {0x7e20,0x003d,0,0x1f,0x40,0x5d,0xc0},{0x7dc0,0x0043,0,0x1f,0x40,0x5d,0xc0} + +#define RINGBACKTONE_SI3216_IR13 0x7e20 +#define RINGBACKTONE_SI3216_IR14 0x003d +#define RINGBACKTONE_SI3216_IR16 0x7dc0 +#define RINGBACKTONE_SI3216_IR17 0x0043 +#define RINGBACKTONE_SI3216_DR32 0x1E +#define RINGBACKTONE_SI3216_DR33 0x1E +#define RINGBACKTONE_SI3216_DR36 0x80 +#define RINGBACKTONE_SI3216_DR37 0x3E +#define RINGBACKTONE_SI3216_DR38 0x0 +#define RINGBACKTONE_SI3216_DR39 0x7d +#define RINGBACKTONE_SI3216_DR40 0x80 +#define RINGBACKTONE_SI3216_DR41 0x3E +#define RINGBACKTONE_SI3216_DR42 0x0 +#define RINGBACKTONE_SI3216_DR43 0x7d + + +//tone_struct RingbackPBX = { /* OSC1 = 440 Hz OSC2= 480 .0975 Volts -18 dBM */ +// {0x7e20,0x003d,0,0x1f,0x40,0x5d,0xc0},{0x7dc0,0x0043,0,0x1f,0x40,0x5d,0xc0} +//}; + + +#define RINGBACKPBXTONE_SI3216_IR13 0x7e20 +#define RINGBACKPBXTONE_SI3216_IR14 0x003d +#define RINGBACKPBXTONE_SI3216_IR16 0x7dc0 +#define RINGBACKPBXTONE_SI3216_IR17 0x0043 +#define RINGBACKPBXTONE_SI3216_DR32 0x1E +#define RINGBACKPBXTONE_SI3216_DR33 0x1E +#define RINGBACKPBXTONE_SI3216_DR36 0x40 +#define RINGBACKPBXTONE_SI3216_DR37 0x1f +#define RINGBACKPBXTONE_SI3216_DR38 0xc0 +#define RINGBACKPBXTONE_SI3216_DR39 0x5d +#define RINGBACKPBXTONE_SI3216_DR40 0x40 +#define RINGBACKPBXTONE_SI3216_DR41 0x1f +#define RINGBACKPBXTONE_SI3216_DR42 0xc0 +#define RINGBACKPBXTONE_SI3216_DR43 0x5d + + +//tone_struct CongestionTone = { /* OSC1= 480 Hz OSC2 = 620 .0975 Volts -18 dBM */ +// {0x7dc0,0x0043,0,0x06,0x40,0x09,0x60},{0x7c40,0x0057,0,0x06,0x40,0x09,0x60} +//}; + + +#define CONGESTIONTONE_SI3216_IR13 0x7dc0 +#define CONGESTIONTONE_SI3216_IR14 0x0043 +#define CONGESTIONTONE_SI3216_IR16 0x7c40 +#define CONGESTIONTONE_SI3216_IR17 0x0057 +#define CONGESTIONTONE_SI3216_DR32 0x1E +#define CONGESTIONTONE_SI3216_DR33 0x1E +#define CONGESTIONTONE_SI3216_DR36 0x40 +#define CONGESTIONTONE_SI3216_DR37 0x06 +#define CONGESTIONTONE_SI3216_DR38 0x60 +#define CONGESTIONTONE_SI3216_DR39 0x09 +#define CONGESTIONTONE_SI3216_DR40 0x40 +#define CONGESTIONTONE_SI3216_DR41 0x06 +#define CONGESTIONTONE_SI3216_DR42 0x60 +#define CONGESTIONTONE_SI3216_DR43 0x09 + + +//tone_struct RingbackJapan = { /* OSC1 = 400 Hz OSC2 = 435 .0975 Volts -18 dBm */ +// {0x79c0,0x00e9,0,0x1f,0x40,0x3e,0x80},{0x7940,0x00f2,0,0x1f,0x40,0x3e,0x80} + +//}; + +#define SI3210_RINGBACKJAPANTONE_IR13 0x79C0 +#define SI3210_RINGBACKJAPANTONE_IR14 0xe9 +#define SI3210_RINGBACKJAPANTONE_IR16 0x7940 +#define SI3210_RINGBACKJAPANTONE_IR17 0xf2 + +#define SI3215_RINGBACKJAPANTONE_IR13 0x7E6C +#define SI3215_RINGBACKJAPANTONE_IR14 0x38 +#define SI3215_RINGBACKJAPANTONE_IR16 0x7E23 +#define SI3215_RINGBACKJAPANTONE_IR17 0x3D + +#define RINGBACKJAPANTONE_DR32 0x1E +#define RINGBACKJAPANTONE_DR33 0x1E +#define RINGBACKJAPANTONE_DR36 0x40 +#define RINGBACKJAPANTONE_DR37 0x1f +#define RINGBACKJAPANTONE_DR38 0x80 +#define RINGBACKJAPANTONE_DR39 0x3e +#define RINGBACKJAPANTONE_DR40 0x40 +#define RINGBACKJAPANTONE_DR41 0x1f +#define RINGBACKJAPANTONE_DR42 0x80 +#define RINGBACKJAPANTONE_DR43 0x3e + + + +//tone_struct BusyJapan = { /* OSC1 = 400 Hz OSC2 = 435 .0975 Volts -18 dBm */ +// {0x79c0,0x00e9,0,0x0f,0xa0,0x0f,0xa0},{0,0,0,0,0,0,0} + +//}; + +#define SI3210_BUSYJAPANTONE_IR13 0x79c0 +#define SI3210_BUSYJAPANTONE_IR14 0x00e9 +#define SI3210_BUSYJAPANTONE_IR16 0 +#define SI3210_BUSYJAPANTONE_IR17 0 + +#define SI3215_BUSYJAPANTONE_IR13 0x7E6C +#define SI3215_BUSYJAPANTONE_IR14 0x0038 +#define SI3215_BUSYJAPANTONE_IR16 0 +#define SI3215_BUSYJAPANTONE_IR17 0 + +#define BUSYJAPANTONE_DR32 0x1E +#define BUSYJAPANTONE_DR33 0 +#define BUSYJAPANTONE_DR36 0xa0 +#define BUSYJAPANTONE_DR37 0x0f +#define BUSYJAPANTONE_DR38 0xa0 +#define BUSYJAPANTONE_DR39 0x0f +#define BUSYJAPANTONE_DR40 0 +#define BUSYJAPANTONE_DR41 0 +#define BUSYJAPANTONE_DR42 0 +#define BUSYJAPANTONE_DR43 0 + + + + + + + + +#define FLUSH_USING_IR34 0x8000 // By seting this value to 0x8000 it accelearates data through Filter +#define FLUSH_USING_IR35 0x8000 // By seting this value to 0x8000 it accelearates data through Filter +#define FLUSH_USING_IR36 0x8000 // By seting this value to 0x8000 it accelearates data through Filter +#define FLUSH_USING_IR37 0x8000 // By seting this value to 0x8000 it accelearates data through Filter +#define FLUSH_USING_IR38 0x8000 // By seting this value to 0x8000 it accelearates data through Filter +#define FLUSH_USING_IR39 0x8000 // By seting this value to 0x8000 it accelearates data through Filter + +#define FLUSH_IR89 0x0000 // Clear value in power accumulator for Q1 +#define FLUSH_IR90 0x0000 // Clear value in power accumulator for Q2 +#define FLUSH_IR91 0x0000 // Clear value in power accumulator for Q3 +#define FLUSH_IR92 0x0000 // Clear value in power accumulator for Q4 +#define FLUSH_IR93 0x0000 // Clear value in power accumulator for Q5 +#define FLUSH_IR94 0x0000 // Clear value in power accumulator for Q6 + + + + +#define BIT_CALM1_DR97 0x10 // CALM1 Monitor ADC Calibration 1. +#define BIT_CALM2_DR97 0x08 // CALM2 Monitor ADC Calibration 2. +#define BIT_CALDAC_DR97 0x04 // CALDAC DAC Calibration. +#define BIT_ADC_DR97 0x02 // CALADC ADC Calibration. +#define BIT_CALCM_DR97 0x01 // CALCM Common Mode Balance Calibration. +#define STANDARD_CAL_DR97 0x18 // Calibrations without the ADC and DAC offset and without common mode calibration. +#define MASK_CAL_DR96 0x40 // CAL Calibration Status Bit. +#define BIT_CAL_DR96 0x40 // CAL Calibration Control +#define BIT_CALR_DR96 0x10 // CALR RING Gain Mismatch Calibration. +#define BIT_CALT_DR96 0x08 // CALT TIP Gain Mismatch Calibration. +#define BIT_CALD_DR96 0x04 // CALD Differential DAC Gain Calibration. +#define BIT_CALC_DR96 0x02 // CALC Common Mode DAC Gain Calibration. +#define BIT_CALIL_DR96 0x01 // CALIL ILIM Calibration. +#define STANDARD_CAL_DR96 0x47 // Calibrate common mode and differential DAC mode DAC + ILIM +#define BIT_IRQE_CMCE 0x04 // Calibrate common mode and differential mode DAC + ILIM +#define CAL_COMPLETE_DR96 0 // Value in dr96 after calibration is completed +#define MAX_CAL_PERIOD 800 // The longest period in ms. for a calibration to complete. + +#define OPEN_DR64 0 // +#define FORWARD_ACTIVE_DR64 1 // +#define OHT_DR64 2 // +#define TIP_OPEN_DR64 3 // +#define RINGING_DR64 4 // +#define REVERSE_ACTIVE_DR64 5 // +#define REVERSE_OHT_DR64 6 // +#define RING_OPEN_DR64 7 // + +#define GROUND_THRESHOLD_DR80 2 // .75 volts +#define GROUND_THRESHOLD_DR81 2 // .75 volts + + +#define ENB2_DR23 1<<2 // enable interrupt for the balance Cal + + + +#define RESET_VALUE_DR8 2 // This is the value at reset of DR8 +#define RESET_VALUE_DR64 0 // This is the value at reset of DR64 +#define RESET_VALUE_DR11 0x33 // This is the value at reset of DR11 + +#define FLUSHING_DR35 0x8000 +#define FLUSHING_DR36 0x8000 +#define FLUSHING_DR37 0x8000 +#define FLUSHING_DR38 0x8000 +#define FLUSHING_DR39 0x8000 + + +#define DISABLE_ALL_DR21 0 +#define DISABLE_ALL_DR22 0 +#define DISABLE_ALL_DR23 0 + +#define PULSE_METERING_IR24 0x3190 +#define PULSE_METERING_IR25 0x4FF +#define PULSE_METERING_DR35 0x10 +#define PULSE_METERING_DR44 0x60 0x04 +#define PULSE_METERING_DR45 0x04 0x60 +#define PULSE_METERING_DR46 0x60 0x04 +#define PULSE_METERING_DR47 0x04 0x60 + +#define RINGING_20HZ_IR19 0 //offset voltage +#define RINGING_20HZ_IR20 0x7F00 +#define RINGING_20HZ_IR21 0x013D +#define RINGING_20HZ_DR34 0X18 +#define RINGING_20HZ_DR48 0x80 +#define RINGING_20HZ_DR49 0x3e +#define RINGING_20HZ_DR50 0x7d +#define RINGING_20HZ_DR51 0 + + + +#define INIT_IR0 0x55C2 // DTMF_ROW_0_PEAK +#define INIT_IR1 0x51E6 // DTMF_ROW_0_PEAK, +#define INIT_IR2 0x4B85 // DTMF_ROW_1_PEAK, +#define INIT_IR3 0x4937 // DTMF_ROW2_PEAK, +#define INIT_IR4 0x3333 // DTMF_ROW3_PEAK, +#define INIT_IR5 0x0202 // DTMF_COL1_PEAK, +#define INIT_IR6 0x0202 // DTMF_FWD_TWIST, +#define INIT_IR7 0x0198 // DTMF_RVS_TWIST, +#define INIT_IR8 0x0198 // DTMF_ROW_RATIO, +#define INIT_IR9 0x0611 // DTMF_COL_RATIO, +#define INIT_IR10 0x0202 // DTMF_ROW_2ND_ARM, +#define INIT_IR11 0x00E5 // DTMF_COL_2ND_ARM, +#define INIT_IR12 0x0A1C // DTMF_PWR_MIN_, +#define INIT_IR13 0x7b30 // DTMF_OT_LIM_TRES, +#define INIT_IR14 0x0063 // OSC1_COEF, +#define INIT_IR15 0x0000 // OSC1X, +#define INIT_IR16 0x7870 // OSC1Y, +#define INIT_IR17 0x007d // OSC2_COEF, +#define INIT_IR18 0x0000 // OSC2X, +#define INIT_IR19 0x0000 // OSC2Y, +#define INIT_IR20 0x7EF0 // RING_V_OFF, +#define INIT_IR21 0x0160 // RING_OSC, +#define INIT_IR22 0x0000 // RING_X, +#define INIT_IR23 0x2000 // RING_Y, +#define INIT_IR24 0x2000 // PULSE_ENVEL, +#define INIT_IR25 0x0000 // PULSE_X, +#define INIT_IR26 0x4000 // PULSE_Y, +#define INIT_IR27 0x4000 // RECV_DIGITAL_GAIN, +#define INIT_IR28 0x1000 // XMIT_DIGITAL_GAIN, +#define INIT_IR29 0x3600 // LOOP_CLOSE_TRES, +#define INIT_IR30 0x1000 // RING_TRIP_TRES, +#define INIT_IR31 0x0200 // COMMON_MIN_TRES, +#define INIT_IR32 0x7c0 // COMMON_MAX_TRES, +#define INIT_IR33 0x2600 // PWR_ALARM_Q1Q2, +#define INIT_IR34 0x1B80 // PWR_ALARM_Q3Q4, +#define INIT_IR35 0x8000 // PWR_ALARM_Q5Q6, +#define INIT_IR36 0x0320 // LOOP_CLSRE_FlTER, +#define INIT_IR37 0x08c // RING_TRIP_FILTER, +#define INIT_IR38 0x0100 // TERM_LP_POLE_Q1Q2, +#define INIT_IR39 0x010 // TERM_LP_POLE_Q3Q4, +#define INIT_IR40 0x0001 // MA 0x0C00 // TERM_LP_POLE_Q5Q6, +#define INIT_IR41 0x0C00 // CM_BIAS_RINGING, +#define INIT_IR42 0x1000 // DCDC_MIN_V, +#define INIT_IR43 0x00DA // "LOOP_CLOSE_TRES Low +#define INIT_IR99 0x00DA // FSK 0 FREQ PARAM +#define INIT_IR100 0x6B60 // FSK 0 AMPL PARAM +#define INIT_IR101 0x0074 // FSK 1 FREQ PARAM +#define INIT_IR102 0x79C0 // FSK 1 AMPl PARAM +#define INIT_IR103 0x1120 // FSK 0to1 SCALER +#define INIT_IR104 0x3BE0 // FSK 1to0 SCALER +#define INIT_IR97 0x0000 // TRASMIT_FILTER + + + +#define STARDARD_IR_INIT_ARRAY unsigned short ir[] =\ +{\ +\ +INIT_IR0 ,\ +INIT_IR1 ,\ +INIT_IR2 ,\ +INIT_IR3 ,\ +INIT_IR4 ,\ +INIT_IR5 ,\ +INIT_IR6 ,\ +INIT_IR7 ,\ +INIT_IR8 ,\ +INIT_IR9 ,\ +INIT_IR10 ,\ +INIT_IR11 ,\ +INIT_IR12 ,\ +INIT_IR13 ,\ +INIT_IR14 ,\ +INIT_IR15 ,\ +INIT_IR16 ,\ +INIT_IR17 ,\ +INIT_IR18 ,\ +INIT_IR19 ,\ +INIT_IR20 ,\ +INIT_IR21 ,\ +INIT_IR22 ,\ +INIT_IR23 ,\ +INIT_IR24 ,\ +INIT_IR25 ,\ +INIT_IR26 ,\ +INIT_IR27 ,\ +INIT_IR28 ,\ +INIT_IR29 ,\ +INIT_IR30 ,\ +INIT_IR31 ,\ +INIT_IR32 ,\ +INIT_IR33 ,\ +INIT_IR34 ,\ +INIT_IR35 ,\ +INIT_IR36 ,\ +INIT_IR37 ,\ +INIT_IR38 ,\ +INIT_IR39 ,\ +INIT_IR40 ,\ +INIT_IR41 ,\ +INIT_IR42 ,\ +INIT_IR43 \ +}; + + + + +#define ERRORCODE_LONGBALCAL -2; + + +#define INIT_DR0_DC 0x80 // Serial Interface +#define INIT_DR0 0x00 // Serial Interface +#define INIT_DR1 0x08 // PCM Mode +#define INIT_DR2 0x00 // PCM TX Clock Slot Low Byte (1 PCLK cycle/LSB) +#define INIT_DR3 0x00 // PCM TX Clock Slot High Byte +#define INIT_DR4 0x00 // PCM RX Clock Slot Low Byte (1 PCLK cycle/LSB) +#define INIT_DR5 0x00 // PCM RX Clock Slot High Byte +#define INIT_DR6 0x00 // DIO Control (external battery operation, Si3211/12) +#define INIT_DR8 0x00 // Loopbacks (digital loopback default) +#define INIT_DR9 0x04/*0x00*/ // Transmit and receive path gain and control +#define INIT_DR10 0x28 // Initialization Two-wire impedance (600 and enabled) +#define INIT_DR11 0x33 // Transhybrid Balance/Four-wire Return Loss +#define INIT_DR14 0x10 // Powerdown Control 1 +#define INIT_DR15 0x00 // Initialization Powerdown Control 2 +#define INIT_DR18 0xff // Normal Oper. Interrupt Register 1 (clear with 0xFF) +#define INIT_DR19 0xff // Normal Oper. Interrupt Register 2 (clear with 0xFF) +#define INIT_DR20 0xff // Normal Oper. Interrupt Register 3 (clear with 0xFF) +#define INIT_DR21 0xff // Interrupt Mask 1 +#define INIT_DR22 0xff // Initialization Interrupt Mask 2 +#define INIT_DR23 0xff // Initialization Interrupt Mask 3 +#define INIT_DR32 0x00 // Oper. Oscillator 1 Control—tone generation +#define INIT_DR33 0x00 // Oper. Oscillator 2 Control—tone generation +#define INIT_DR34 0x18 // 34 0x22 0x00 Initialization Ringing Oscillator Control +#define INIT_DR35 0x00 // Oper. Pulse Metering Oscillator Control +#define INIT_DR36 0x00 // 36 0x24 0x00 Initialization OSC1 Active Low Byte (125 µs/LSB) +#define INIT_DR37 0x00 // 37 0x25 0x00 Initialization OSC1 Active High Byte (125 µs/LSB) +#define INIT_DR38 0x00 // 38 0x26 0x00 Initialization OSC1 Inactive Low Byte (125 µs/LSB) +#define INIT_DR39 0x00 // 39 0x27 0x00 Initialization OSC1 Inactive High Byte (125 µs/LSB) +#define INIT_DR40 0x00 // 40 0x28 0x00 Initialization OSC2 Active Low Byte (125 µs/LSB) +#define INIT_DR41 0x00 // 41 0x29 0x00 Initialization OSC2 Active High Byte (125 µs/LSB) +#define INIT_DR42 0x00 // 42 0x2A 0x00 Initialization OSC2 Inactive Low Byte (125 µs/LSB) +#define INIT_DR43 0x00 // 43 0x2B 0x00 Initialization OSC2 Inactive High Byte (125 µs/LSB) +#define INIT_DR44 0x00 // 44 0x2C 0x00 Initialization Pulse Metering Active Low Byte (125 µs/LSB) +#define INIT_DR45 0x00 // 45 0x2D 0x00 Initialization Pulse Metering Active High Byte (125 µs/LSB) +#define INIT_DR46 0x00 // 46 0x2E 0x00 Initialization Pulse Metering Inactive Low Byte (125 µs/LSB) +#define INIT_DR47 0x00 // 47 0x2F 0x00 Initialization Pulse Metering Inactive High Byte (125 µs/LSB) +#define INIT_DR48 0x80 // 48 0x30 0x00 0x80 Initialization Ringing Osc. Active Timer Low Byte (2 s,125 µs/LSB) +#define INIT_DR49 0x3E // 49 0x31 0x00 0x3E Initialization Ringing Osc. Active Timer High Byte (2 s,125 µs/LSB) +#define INIT_DR50 0x00 // 50 0x32 0x00 0x00 Initialization Ringing Osc. Inactive Timer Low Byte (4 s, 125 µs/LSB) +#define INIT_DR51 0x7D // 51 0x33 0x00 0x7D Initialization Ringing Osc. Inactive Timer High Byte (4 s, 125 µs/LSB) +#define INIT_DR52 0x00 // 52 0x34 0x00 Normal Oper. FSK Data Bit +#define INIT_DR63 0x54 // 63 0x3F 0x54 Initialization Ringing Mode Loop Closure Debounce Interval +#define INIT_DR64 0x00 // 64 0x40 0x00 Normal Oper. Mode Byte—primary control +#define INIT_DR65 0x61 // 65 0x41 0x61 Initialization External Bipolar Transistor Settings +#define INIT_DR66 0x03 // 66 0x42 0x03 Initialization Battery Control +#define INIT_DR67 0x1F // 67 0x43 0x1F Initialization Automatic/Manual Control +#define INIT_DR69 0x0C // 69 0x45 0x0A 0x0C Initialization Loop Closure Debounce Interval (1.25 ms/LSB) +#define INIT_DR70 0x0A // 70 0x46 0x0A Initialization Ring Trip Debounce Interval (1.25 ms/LSB) +#define INIT_DR71 0x01 // 71 0x47 0x00 0x01 Initialization Off-Hook Loop Current Limit (20 mA + 3 mA/LSB) +#define INIT_DR72 0x20 // 72 0x48 0x20 Initialization On-Hook Voltage (open circuit voltage) = 48 V(1.5 V/LSB) +#define INIT_DR73 0x02 // 73 0x49 0x02 Initialization Common Mode Voltage—VCM = –3 V(–1.5 V/LSB) +#define INIT_DR74 0x2f // MA 0x32 // 74 0x4A 0x32 Initialization VBATH (ringing) = –75 V (–1.5 V/LSB) +#define INIT_DR75 0x10 // 75 0x4B 0x10 Initialization VBATL (off-hook) = –24 V (TRACK = 0)(–1.5 V/LSB) +#define INIT_DR92 0xff // MA 0x7f // 92 0x5C 7F Initialization DC–DC Converter PWM Period (61.035 ns/LSB) +#define INIT_DR93 0x0c // MA 0x14 // 93 0x5D 0x14 0x19 Initialization DC–DC Converter Min. Off Time (61.035 ns/LSB) +#define INIT_DR96 0x00 // 96 0x60 0x1F Initialization Calibration Control Register 1(written second and starts calibration) +#define INIT_DR97 0x1F // 97 0x61 0x1F Initialization Calibration Control Register 2(written before Register 96) +#define INIT_DR98 0x10 // 98 0x62 0x10 Informative Calibration result (see data sheet) +#define INIT_DR99 0x10 // 99 0x63 0x10 Informative Calibration result (see data sheet) +#define INIT_DR100 0x11 // 100 0x64 0x11 Informative Calibration result (see data sheet) +#define INIT_DR101 0x11 // 101 0x65 0x11 Informative Calibration result (see data sheet) +#define INIT_DR102 0x08 // 102 0x66 0x08 Informative Calibration result (see data sheet) +#define INIT_DR103 0x88 // 103 0x67 0x88 Informative Calibration result (see data sheet) +#define INIT_DR104 0x00 // 104 0x68 0x00 Informative Calibration result (see data sheet) +#define INIT_DR105 0x00 // 105 0x69 0x00 Informative Calibration result (see data sheet) +#define INIT_DR106 0x20 // 106 0x6A 0x20 Informative Calibration result (see data sheet) +#define INIT_DR107 0x08 // 107 0x6B 0x08 Informative Calibration result (see data sheet) +#define INIT_DR108 0xEB // 108 0x63 0x00 0xEB Initialization Feature enhancement register +#define INIT_SI3210M_DR92 0x60 // 92 0x60 Initialization DC–DC Converter PWM Period (61.035 ns/LSB) +#define INIT_SI3210M_DR93 0x38 // 92 0x60 Initialization DC–DC Converter PWM Period (61.035 ns/LSB) + +/* New Defines */ +#define MV_SI3210_FAMILY 0 +#define MV_SI3210 0 +#define MV_SI3211 1 +#define MV_SI3210M 3 +#define MV_SI3215_FAMILY (1<<7) +#define MV_SI3215 0 +#define MV_SI3215M 3 + +/**************************************OS.h****************************************************/ + +void exception (enum exceptions e); + +#endif /*_PROSLIC_H_*/ diff --git a/board/mv_feroceon/mv_hal/voiceband/tdm/mvTdm.c b/board/mv_feroceon/mv_hal/voiceband/tdm/mvTdm.c new file mode 100644 index 0000000..d7bc66d --- /dev/null +++ b/board/mv_feroceon/mv_hal/voiceband/tdm/mvTdm.c @@ -0,0 +1,872 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "voiceband/tdm/mvTdm.h" + +/* defines */ +#define INT_SAMPLE 2 +#define BUFF_IS_FULL 1 +#define BUFF_IS_EMPTY 0 +#define FIRST_INT 1 +#define TOTAL_BUFFERS 2 +#define MV_TDM_NEXT_BUFFER(buf) ((buf + 1) % TOTAL_BUFFERS) +#define MV_TDM_PREV_BUFFER(buf, step) ((TOTAL_BUFFERS + buf - step) % TOTAL_BUFFERS) + +/* static APIs */ +static MV_STATUS mvTdmChInit(MV_U8 ch); +static MV_STATUS mvTdmChRemove(MV_U8 ch); +static MV_VOID mvTdmReset(MV_VOID); +static MV_VOID mvTdmDaisyChainModeSet(MV_VOID); +static MV_VOID mvTdmShowProperties(MV_VOID); +/* Tx */ +static INLINE MV_STATUS mvTdmChTxLow(MV_U8 ch); +/* Rx */ +static INLINE MV_STATUS mvTdmChRxLow(MV_U8 ch); + +/* TDM channel info structure */ +typedef struct _mv_tdm_ch_info +{ + MV_U8 ch; + MV_U8 *rxBuffVirt[TOTAL_BUFFERS], *txBuffVirt[TOTAL_BUFFERS]; + MV_ULONG rxBuffPhys[TOTAL_BUFFERS], txBuffPhys[TOTAL_BUFFERS]; + MV_U8 rxBuffFull[TOTAL_BUFFERS], txBuffFull[TOTAL_BUFFERS]; + volatile MV_U8 rxCurrBuff, txCurrBuff; + MV_U8 rxFirst; +} MV_TDM_CH_INFO; + +/* globals */ +static MV_U8 *rxAggrBuffVirt, *txAggrBuffVirt; +static MV_ULONG rxAggrBuffPhys, txAggrBuffPhys; +static MV_U8 rxInt, txInt; +static MV_U8 tdmEnable; +static MV_U8 spiMode; +static MV_U8 factor; +static mv_pcm_format_t pcmFormat; +static mv_band_mode_t tdmBandMode; +static MV_TDM_CH_INFO *tdmChInfo[MV_TDM_TOTAL_CHANNELS] = {NULL, NULL}; + +MV_U16 tdmSlotInfo[MV_TDM_TOTAL_CHANNELS][2] = { + {CH0_RX_SLOT, CH0_TX_SLOT}, + {CH1_RX_SLOT, CH1_TX_SLOT} +}; + + +MV_STATUS mvTdmInit(mv_tdm_params_t* tdmParams) +{ + MV_U8 ch, sample; + MV_U32 pcmCtrlReg; + + MV_TRC_REC("->%s\n",__FUNCTION__); + mvTdmShowProperties(); + + /* Init TDM windows address decoding */ + if (mvTdmWinInit() != MV_OK) + { + return MV_ERROR; + } + + /* Init globals */ + rxInt = txInt = 0; + tdmEnable = 0; + spiMode = mvBoardTdmSpiModeGet(); + tdmBandMode = tdmParams->bandMode; + pcmFormat = tdmParams->pcmFormat; + + if((tdmParams->samplePeriod < MV_TDM_BASE_SAMPLE_PERIOD) || + (tdmParams->samplePeriod > MV_TDM_MAX_SAMPLE_PERIOD)) + { + factor = 1; /* use base sample period(10ms) */ + } + else + { + factor = (tdmParams->samplePeriod / MV_TDM_BASE_SAMPLE_PERIOD); + } + + /* Set sample size for further TDM configuration */ + sample = (pcmFormat == MV_PCM_FORMAT_LINEAR ? 2 : 1); + + /* Allocate aggregated buffers for data transport */ + MV_TRC_REC("allocate %d bytes for aggregated buffer\n", MV_TDM_AGGR_BUFF_SIZE(pcmFormat, tdmBandMode, factor)); + rxAggrBuffVirt = (MV_U8*)mvOsIoCachedMalloc(NULL, MV_TDM_AGGR_BUFF_SIZE(pcmFormat, tdmBandMode, factor), + &rxAggrBuffPhys,NULL); + txAggrBuffVirt = (MV_U8*)mvOsIoCachedMalloc(NULL, MV_TDM_AGGR_BUFF_SIZE(pcmFormat, tdmBandMode, factor), + &txAggrBuffPhys,NULL); + if(!rxAggrBuffVirt || !txAggrBuffVirt) + { + mvOsPrintf("%s: error malloc failed\n",__FUNCTION__); + return MV_NO_RESOURCE; + } + + /* Config TDM */ + MV_REG_BIT_RESET(TDM_SPI_MUX_REG, 1); /* enable TDM/SPI interface */ + MV_REG_BIT_SET(TDM_MISC_REG, BIT0); /* sw reset to TDM for 5181L-A1 & up */ + MV_REG_WRITE(INT_RESET_SELECT_REG,CLEAR_ON_ZERO); /* int cause is not clear on read */ + MV_REG_WRITE(INT_EVENT_MASK_REG,0x3ffff); /* all interrupt bits latched in status */ + MV_REG_WRITE(INT_STATUS_MASK_REG,0); /* disable interrupts */ + MV_REG_WRITE(INT_STATUS_REG,0); /* clear int status register */ + MV_REG_WRITE(PCM_CLK_RATE_DIV_REG, PCM_8192KHZ); /* PCM PCLK freq */ + MV_REG_WRITE(DUMMY_RX_WRITE_DATA_REG,0); /* Padding on Rx completion */ + MV_REG_BYTE_WRITE(SPI_GLOBAL_CTRL_REG, MV_REG_READ(SPI_GLOBAL_CTRL_REG) | SPI_GLOBAL_ENABLE); + MV_REG_BYTE_WRITE(SPI_CLK_PRESCALAR_REG, SPI_CLK_8MHZ); /* SPI SCLK freq */ + MV_REG_WRITE(FRAME_TIMESLOT_REG, TIMESLOTS128_8192KHZ); /* Number of timeslots (PCLK) */ + + if(tdmBandMode == MV_NARROW_BAND) + { + pcmCtrlReg = (CONFIG_PCM_CRTL | ((sample-1)<%s ch%d\n",__FUNCTION__,ch); + + if(ch >= MV_TDM_TOTAL_CHANNELS) + { + mvOsPrintf("%s: error, channel(%d) exceeds maximum(%d)\n",__FUNCTION__, ch, MV_TDM_TOTAL_CHANNELS); + return MV_BAD_PARAM; + } + + tdmChInfo[ch] = chInfo = (MV_TDM_CH_INFO *)mvOsMalloc(sizeof(MV_TDM_CH_INFO)); + if(!chInfo) + { + mvOsPrintf("%s: error malloc failed\n",__FUNCTION__); + return MV_NO_RESOURCE; + } + + chInfo->ch = ch; + + /* Per channel TDM init */ + MV_REG_WRITE(CH_ENABLE_REG(ch),CH_DISABLE); /* disable channel (enable in pcm start) */ + MV_REG_WRITE(CH_SAMPLE_REG(ch),CONFIG_CH_SAMPLE(tdmBandMode, factor)); /* set total samples and int sample */ + + for(buff = 0; buff < TOTAL_BUFFERS; buff++) + { + /* Buffers must be 32B aligned */ + chInfo->rxBuffVirt[buff] = (MV_U8*)mvOsIoUncachedMalloc(NULL, MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor), + &(chInfo->rxBuffPhys[buff]),NULL); + chInfo->rxBuffFull[buff] = BUFF_IS_EMPTY; + + chInfo->txBuffVirt[buff] = (MV_U8*)mvOsIoUncachedMalloc(NULL, MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor), + &(chInfo->txBuffPhys[buff]),NULL); + chInfo->txBuffFull[buff] = BUFF_IS_FULL; + + memset(chInfo->txBuffVirt[buff], 0, MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor)); + + if(((MV_ULONG)chInfo->rxBuffVirt[buff] | chInfo->rxBuffPhys[buff] | + (MV_ULONG)chInfo->txBuffVirt[buff] | chInfo->txBuffPhys[buff]) & 0x1f) { + mvOsPrintf("%s: error, unaligned buffer allocation\n", __FUNCTION__); + } + } + + MV_TRC_REC("<-%s\n",__FUNCTION__); + return MV_OK; +} + +MV_VOID mvTdmRelease(MV_VOID) +{ + MV_U8 ch; + + MV_TRC_REC("->%s\n",__FUNCTION__); + + /* Free Rx/Tx aggregated buffers */ + mvOsIoCachedFree(NULL, MV_TDM_AGGR_BUFF_SIZE(pcmFormat, tdmBandMode, factor), rxAggrBuffPhys, + rxAggrBuffVirt ,0); + mvOsIoCachedFree(NULL, MV_TDM_AGGR_BUFF_SIZE(pcmFormat, tdmBandMode, factor), txAggrBuffPhys, + txAggrBuffVirt ,0); + + /* Release HW channel resources */ + for(ch = 0; ch < MV_TDM_TOTAL_CHANNELS; ch++) + mvTdmChRemove(ch); + + MV_TRC_REC("<-%s\n",__FUNCTION__); +} + +static MV_STATUS mvTdmChRemove(MV_U8 ch) +{ + MV_TDM_CH_INFO *chInfo; + MV_U8 buff; + + MV_TRC_REC("->%s ch%d\n",__FUNCTION__,ch); + + if(ch >= MV_TDM_TOTAL_CHANNELS) + { + mvOsPrintf("%s: error, channel(%d) exceeds maximum(%d)\n",__FUNCTION__, ch, MV_TDM_TOTAL_CHANNELS); + return MV_BAD_PARAM; + } + + chInfo = tdmChInfo[ch]; + + for(buff = 0; buff < TOTAL_BUFFERS; buff++) + { + mvOsIoUncachedFree(NULL, MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor), chInfo->rxBuffPhys[buff], + chInfo->rxBuffVirt[buff],0); + mvOsIoUncachedFree(NULL, MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor), chInfo->txBuffPhys[buff], + chInfo->txBuffVirt[buff],0); + } + + mvOsFree(chInfo); + + MV_TRC_REC("<-%s ch%d\n",__FUNCTION__,ch); + return MV_OK; +} + +static MV_VOID mvTdmReset(MV_VOID) +{ + MV_TDM_CH_INFO *chInfo; + MV_U8 buff, ch; + + MV_TRC_REC("->%s\n",__FUNCTION__); + + /* Reset irq counter */ + rxInt = txInt = 0; + + for(ch = 0; ch < MV_TDM_TOTAL_CHANNELS; ch++) + { + chInfo = tdmChInfo[ch]; + chInfo->rxFirst = FIRST_INT; + chInfo->txCurrBuff = chInfo->rxCurrBuff = 0; + for(buff = 0; buff < TOTAL_BUFFERS; buff++) + { + chInfo->rxBuffFull[buff] = BUFF_IS_EMPTY; + chInfo->txBuffFull[buff] = BUFF_IS_FULL; + + } + } + + MV_TRC_REC("<-%s\n",__FUNCTION__); + return; +} + +MV_VOID mvTdmPcmStart(MV_VOID) +{ + MV_TDM_CH_INFO *chInfo; + MV_U8 ch; + + MV_TRC_REC("->%s\n",__FUNCTION__); + + tdmEnable = 1; /* TDM is enabled */ + mvTdmReset(); + + for(ch = 0; ch < MV_TDM_TOTAL_CHANNELS; ch++) + { + chInfo = tdmChInfo[ch]; + + /* Set Tx buff */ + MV_REG_WRITE(CH_TX_ADDR_REG(ch),chInfo->txBuffPhys[chInfo->txCurrBuff]); + MV_REG_BYTE_WRITE(CH_BUFF_OWN_REG(ch)+TX_OWN_BYTE_OFFS, OWN_BY_HW); + + /* Set Rx buff */ + MV_REG_WRITE(CH_RX_ADDR_REG(ch),chInfo->rxBuffPhys[chInfo->rxCurrBuff]); + MV_REG_BYTE_WRITE(CH_BUFF_OWN_REG(ch)+RX_OWN_BYTE_OFFS, OWN_BY_HW); + + } + + /* Enable Tx */ + MV_REG_BYTE_WRITE(CH_ENABLE_REG(0)+TX_ENABLE_BYTE_OFFS, CH_ENABLE); + MV_REG_BYTE_WRITE(CH_ENABLE_REG(1)+TX_ENABLE_BYTE_OFFS, CH_ENABLE); + + /* Enable Rx */ + MV_REG_BYTE_WRITE(CH_ENABLE_REG(0)+RX_ENABLE_BYTE_OFFS, CH_ENABLE); + MV_REG_BYTE_WRITE(CH_ENABLE_REG(1)+RX_ENABLE_BYTE_OFFS, CH_ENABLE); + + /* Enable Tx interrupts */ + MV_REG_WRITE( INT_STATUS_REG, MV_REG_READ(INT_STATUS_REG) & (~(TDM_INT_TX(0) | TDM_INT_TX(1)))); + MV_REG_WRITE(INT_STATUS_MASK_REG, (MV_REG_READ(INT_STATUS_MASK_REG) | TDM_INT_TX(0) | TDM_INT_TX(1))); + + /* Enable Rx interrupts */ + MV_REG_WRITE(INT_STATUS_REG, (MV_REG_READ(INT_STATUS_REG) & (~(TDM_INT_RX(0) | TDM_INT_RX(1))))); + MV_REG_WRITE(INT_STATUS_MASK_REG, (MV_REG_READ(INT_STATUS_MASK_REG) | TDM_INT_RX(0) | TDM_INT_RX(1))); + + MV_TRC_REC("<-%s\n",__FUNCTION__); +} + +MV_VOID mvTdmPcmStop(MV_VOID) +{ + MV_TRC_REC("->%s\n",__FUNCTION__); + + tdmEnable = 0; + mvTdmReset(); + + /* Mask all interrpts except SLIC/DAA */ + MV_REG_WRITE(INT_STATUS_MASK_REG, (MV_U32)TDM_INT_SLIC); + + MV_TRC_REC("<-%s\n",__FUNCTION__); +} + +MV_STATUS mvTdmTx(MV_U8 *tdmTxBuff) +{ + MV_TDM_CH_INFO *chInfo; + MV_U8 nextBuff, ch; + MV_U8 *pTdmTxBuff; + + MV_TRC_REC("->%s\n",__FUNCTION__); + + /* Sanity check */ + if(tdmTxBuff != txAggrBuffVirt) + { + mvOsPrintf("%s: Error, invalid Tx buffer !!!\n", __FUNCTION__); + return MV_ERROR; + } + + if(!tdmEnable) + { + mvOsPrintf("%s: Error, no active Tx channels are available\n", __FUNCTION__); + return MV_ERROR; + } + + for(ch = 0; ch < MV_TDM_TOTAL_CHANNELS; ch++) + { + chInfo = tdmChInfo[ch]; + nextBuff = chInfo->txCurrBuff; + MV_TRC_REC("ch%d: fill buf %d with %d bytes\n", ch, nextBuff, MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor)); + if(chInfo->txBuffFull[nextBuff] == BUFF_IS_FULL) + { + mvOsPrintf("%s: Error, Tx buffer already full for channel %d\n", __FUNCTION__, ch); + return MV_NOT_READY; + } + chInfo->txBuffFull[nextBuff] = BUFF_IS_FULL; + pTdmTxBuff = tdmTxBuff + (ch * MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor)); + /* Copy data from voice engine buffer to DMA buffer */ + mvOsMemcpy(chInfo->txBuffVirt[nextBuff], pTdmTxBuff , MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor)); + } + + MV_TRC_REC("<-%s\n",__FUNCTION__); + return MV_OK; +} + +MV_STATUS mvTdmRx(MV_U8 *tdmRxBuff) +{ + MV_TDM_CH_INFO *chInfo; + MV_U8 ch, lastBuff; + MV_U8* pTdmRxBuff; + + MV_TRC_REC("->%s\n",__FUNCTION__); + + /* Sanity check */ + if(tdmRxBuff != rxAggrBuffVirt) + { + mvOsPrintf("%s: invalid Rx buffer !!!\n", __FUNCTION__); + return MV_ERROR; + } + + if(!tdmEnable) + { + mvOsPrintf("%s: Error, no active Rx channels are available\n", __FUNCTION__); + return MV_ERROR; + } + + for(ch = 0; ch < MV_TDM_TOTAL_CHANNELS; ch++) + { + chInfo = tdmChInfo[ch]; + lastBuff = MV_TDM_PREV_BUFFER(chInfo->rxCurrBuff, 2); + if(chInfo->rxBuffFull[lastBuff] == BUFF_IS_EMPTY) + { + mvOsPrintf("%s: Error, Rx buffer is already empty for channel %d\n", __FUNCTION__, ch); + return MV_NOT_READY; + } + chInfo->rxBuffFull[lastBuff] = BUFF_IS_EMPTY; + MV_TRC_REC("%s get Rx buffer(%d) for channel(%d)\n",__FUNCTION__, lastBuff, ch); + pTdmRxBuff = tdmRxBuff + (ch * MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor)); + /* Copy data from DMA buffer to voice engine buffer */ + mvOsMemcpy(pTdmRxBuff, chInfo->rxBuffVirt[lastBuff] , MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor)); + } + + MV_TRC_REC("<-%s\n",__FUNCTION__); + return MV_OK; +} + +/* Low level TDM interrupt service routine */ +MV_VOID mvTdmIntLow(mv_tdm_int_info_t* tdmIntInfo) +{ + MV_U32 statusReg, maskReg, statusAndMask; + MV_U8 ch; + + MV_TRC_REC("->%s\n",__FUNCTION__); + + /* Read Status & mask registers */ + statusReg = MV_REG_READ(INT_STATUS_REG); + maskReg = MV_REG_READ(INT_EVENT_MASK_REG); + MV_TRC_REC("CAUSE(0x%x), MASK(0x%x)\n", statusReg, maskReg); + + /* Refer only to unmasked bits */ + statusAndMask = statusReg & maskReg; + + /* Reset params */ + tdmIntInfo->tdmRxBuff = NULL; + tdmIntInfo->tdmTxBuff = NULL; + tdmIntInfo->intType = MV_EMPTY_INT; + + /* Handle SLIC/DAA int */ + if(statusAndMask & SLIC_INT_BIT) + { + MV_TRC_REC("Phone interrupt !!!\n"); + tdmIntInfo->intType |= MV_PHONE_INT; + } + + /* Return in case TDM is disabled */ + if(!tdmEnable) + { + MV_TRC_REC("TDM is disabled - quit low level ISR\n"); + MV_REG_WRITE(INT_STATUS_REG, ~statusReg); + return; + } + + if(statusAndMask & DMA_ABORT_BIT) + { + mvOsPrintf("DMA data abort. Address: 0x%08x, Info: 0x%08x\n", + MV_REG_READ(DMA_ABORT_ADDR_REG), MV_REG_READ(DMA_ABORT_INFO_REG)); + tdmIntInfo->intType |= MV_ERROR_INT; + } + + for(ch = 0; ch < MV_TDM_TOTAL_CHANNELS; ch++) + { + if (statusAndMask & TDM_INT_TX(ch)) + { + /* Give next buff to TDM and set curr buff as empty */ + if (statusAndMask & TX_BIT(ch)) + { + MV_TRC_REC("Tx interrupt(ch%d) !!!\n", ch); + + /* MV_OK -> Tx is done for both channels */ + if(mvTdmChTxLow(ch) == MV_OK) + { + MV_TRC_REC("Assign Tx aggregate buffer for further processing\n"); + tdmIntInfo->tdmTxBuff = txAggrBuffVirt; + tdmIntInfo->intType |= MV_TX_INT; + } + } + + if(statusAndMask & TX_UNDERFLOW_BIT(ch)) + { + mvOsPrintf("Tx underflow, disable interrupts for channel %d !!!\n", ch); + tdmIntInfo->intType |= MV_ERROR_INT; + MV_REG_WRITE(INT_EVENT_MASK_REG, (maskReg & (~(TDM_INT_TX(ch))))); + } + } + + if (statusAndMask & TDM_INT_RX(ch)) + { + if (statusAndMask & RX_BIT(ch)) + { + MV_TRC_REC("Rx interrupt(ch%d) !!!\n", ch); + + /* MV_OK -> Tx is done for both channels */ + if(mvTdmChRxLow(ch) == MV_OK) + { + MV_TRC_REC("Assign Rx aggregate buffer for further processing\n"); + tdmIntInfo->tdmRxBuff = rxAggrBuffVirt; + tdmIntInfo->intType |= MV_RX_INT; + } + } + + if (statusAndMask & RX_OVERFLOW_BIT(ch)) + { + mvOsPrintf("Rx overflow, disable interrupts for channel %d !!!\n", ch); + tdmIntInfo->intType |= MV_ERROR_INT; + MV_REG_WRITE(INT_EVENT_MASK_REG, (maskReg & (~(TDM_INT_RX(ch))))); + } + } + } + + /* clear TDM interrupts */ + MV_REG_WRITE(INT_STATUS_REG, ~statusReg); + + TRC_REC("<-%s\n",__FUNCTION__); + return; +} + +static INLINE MV_STATUS mvTdmChTxLow(MV_U8 ch) +{ + MV_U32 max_poll = 0; + MV_TDM_CH_INFO *chInfo = tdmChInfo[ch]; + + MV_TRC_REC("->%s ch%d\n",__FUNCTION__,ch); + + /* count tx interrupts */ + txInt++; + MV_TRC_REC("txInt(%d)\n", txInt); + + if(chInfo->txBuffFull[chInfo->txCurrBuff] == BUFF_IS_FULL) + { + MV_TRC_REC("curr buff full for hw [MMP ok]\n"); + } + else + { + MV_TRC_REC("curr buf is empty [MMP miss write]\n"); + } + + /* Change buffers */ + chInfo->txCurrBuff = MV_TDM_NEXT_BUFFER(chInfo->txCurrBuff); + + /* Mark next buff to be transmitted by HW as empty. Give it to the HW + for next frame. The app need to write the data before HW takes it. */ + chInfo->txBuffFull[chInfo->txCurrBuff] = BUFF_IS_EMPTY; + MV_TRC_REC("->%s clear buf(%d) for channel(%d)\n",__FUNCTION__, chInfo->txCurrBuff, ch); + + /* Poll on SW ownership (single check) */ + MV_TRC_REC("start poll for SW ownership\n"); + while( ((MV_REG_BYTE_READ(CH_BUFF_OWN_REG(chInfo->ch)+TX_OWN_BYTE_OFFS) & OWNER_MASK) == OWN_BY_HW) + && (max_poll < 2000) ) + { + mvOsUDelay(1); + max_poll++; + } + if(max_poll == 2000) + { + MV_TRC_REC("poll timeout (~2ms)\n"); + return MV_TIMEOUT; + } + else + { + MV_TRC_REC("tx-low poll stop ok\n"); + } + MV_TRC_REC("ch%d, start tx buff %d\n", ch, chInfo->txCurrBuff); + + /*Set TX buff address (must be 32 byte aligned) */ + MV_REG_WRITE(CH_TX_ADDR_REG(chInfo->ch),chInfo->txBuffPhys[chInfo->txCurrBuff]); + + /* Set HW ownership */ + MV_REG_BYTE_WRITE(CH_BUFF_OWN_REG(chInfo->ch)+TX_OWN_BYTE_OFFS, OWN_BY_HW); + + /* Enable Tx */ + MV_REG_BYTE_WRITE(CH_ENABLE_REG(chInfo->ch)+TX_ENABLE_BYTE_OFFS, CH_ENABLE); + + MV_TRC_REC("<-%s\n",__FUNCTION__); + + /* Did we get the required amount of irqs for Tx wakeup ? */ + if(txInt < MV_TDM_INT_COUNTER) + { + return MV_NOT_READY; + } + else + { + txInt = 0; + return MV_OK; + } +} + +static INLINE MV_STATUS mvTdmChRxLow(MV_U8 ch) +{ + MV_U32 max_poll = 0; + MV_TDM_CH_INFO *chInfo = tdmChInfo[ch]; + + MV_TRC_REC("->%s ch%d\n",__FUNCTION__,ch); + + if(chInfo->rxFirst) + chInfo->rxFirst = !FIRST_INT; + else + rxInt++; + + MV_TRC_REC("rxInt(%d)\n", rxInt); + + if(chInfo->rxBuffFull[chInfo->rxCurrBuff] == BUFF_IS_EMPTY) + { + MV_TRC_REC("curr buff empty for hw [MMP ok]\n"); + } + else + { + MV_TRC_REC("curr buf is full [MMP miss read]\n"); + } + + /* Mark last buff that was received by HW as full. Give next buff to HW for */ + /* next frame. The app need to read the data before next irq */ + chInfo->rxBuffFull[chInfo->rxCurrBuff] = BUFF_IS_FULL; + MV_TRC_REC("buff %d is FULL for ch%d\n", chInfo->rxCurrBuff, ch); + + /* Change buffers */ + chInfo->rxCurrBuff = MV_TDM_NEXT_BUFFER(chInfo->rxCurrBuff); + + /* Poll on SW ownership (single check) */ + MV_TRC_REC("start poll for ownership\n"); + while( ((MV_REG_BYTE_READ(CH_BUFF_OWN_REG(chInfo->ch)+RX_OWN_BYTE_OFFS) & OWNER_MASK) == OWN_BY_HW) + && (max_poll < 2000) ) + { + mvOsUDelay(1); + max_poll++; + } + if(max_poll == 2000) + { + MV_TRC_REC("poll timeout (~2ms)\n"); + return MV_TIMEOUT; + } + else + { + MV_TRC_REC("poll stop ok\n"); + } + MV_TRC_REC("%s ch%d, start rx buff %d\n",__FUNCTION__, ch, chInfo->rxCurrBuff); + + /* Set RX buff address (must be 32 byte aligned) */ + MV_REG_WRITE(CH_RX_ADDR_REG(chInfo->ch),chInfo->rxBuffPhys[chInfo->rxCurrBuff]); + + /* Set HW ownership */ + MV_REG_BYTE_WRITE(CH_BUFF_OWN_REG(chInfo->ch)+RX_OWN_BYTE_OFFS, OWN_BY_HW); + + /* Enable Rx */ + MV_REG_BYTE_WRITE(CH_ENABLE_REG(chInfo->ch)+RX_ENABLE_BYTE_OFFS, CH_ENABLE); + + MV_TRC_REC("<-%s\n",__FUNCTION__); + + /* Did we get the required amount of irqs for Rx wakeup ? */ + if(rxInt < MV_TDM_INT_COUNTER) + { + return MV_NOT_READY; + } + else + { + rxInt = 0; + return MV_OK; + } +} + +/**************************** +** SPI Stuff ** +****************************/ + +static MV_VOID mvTdmSetCurrentUnit(MV_32 cs) +{ + if(!spiMode) + { + if(!cs) + { + MV_REG_WRITE(PCM_CTRL_REG, (MV_REG_READ(PCM_CTRL_REG) & ~CS_CTRL)); + } + else + { + MV_REG_WRITE(PCM_CTRL_REG, (MV_REG_READ(PCM_CTRL_REG) | CS_CTRL)); + } + } + else + MV_REG_WRITE(PCM_CTRL_REG, (MV_REG_READ(PCM_CTRL_REG) & ~CS_CTRL)); +} + + +static MV_VOID mvTdmDaisyChainModeSet(MV_VOID) +{ + mvOsPrintf("Setting Daisy Chain Mode\n"); + while( (MV_REG_READ(SPI_CTRL_REG) & SPI_STAT_MASK) == SPI_ACTIVE); + MV_REG_WRITE(SPI_CODEC_CMD_LO_REG, (0x80<<8) | 0); + MV_REG_WRITE(SPI_CODEC_CTRL_REG, TRANSFER_BYTES(2) | ENDIANESS_MSB_MODE | WR_MODE | CLK_SPEED_LO_DIV); + MV_REG_WRITE(SPI_CTRL_REG, MV_REG_READ(SPI_CTRL_REG) | SPI_ACTIVE); + /* Poll for ready indication */ + while( (MV_REG_READ(SPI_CTRL_REG) & SPI_STAT_MASK) == SPI_ACTIVE); +} + + +MV_STATUS mvTdmSpiWrite(MV_U32 val1, MV_U32 val2, MV_U32 cmd, MV_U8 cs) +{ + /*MV_TRC_REC("%s: cs = %d val1 = 0x%x val2 = 0x%x\n",__FUNCTION__,cs, val1, val2);*/ + + /* Poll for ready indication */ + while( (MV_REG_READ(SPI_CTRL_REG) & SPI_STAT_MASK) == SPI_ACTIVE); + + mvTdmSetCurrentUnit(cs); + + MV_REG_WRITE(SPI_CODEC_CMD_LO_REG, val1); + MV_REG_WRITE(SPI_CODEC_CMD_HI_REG, val2); + MV_REG_WRITE(SPI_CODEC_CTRL_REG, cmd); + + /* Activate */ + MV_REG_WRITE(SPI_CTRL_REG, MV_REG_READ(SPI_CTRL_REG) | SPI_ACTIVE); + + /* Poll for ready indication */ + while( (MV_REG_READ(SPI_CTRL_REG) & SPI_STAT_MASK) == SPI_ACTIVE); + + return MV_OK; +} + +MV_STATUS mvTdmSpiRead(MV_U32 val1, MV_U32 val2, MV_U32 cmd, MV_U8 cs, MV_U8 *data) +{ + /*MV_TRC_REC("%s: cs = %d val1 = 0x%x val2 = 0x%x\n",__FUNCTION__,cs, val1, val2);*/ + + /* Poll for ready indication */ + while( (MV_REG_READ(SPI_CTRL_REG) & SPI_STAT_MASK) == SPI_ACTIVE); + + mvTdmSetCurrentUnit(cs); + + MV_REG_WRITE(SPI_CODEC_CMD_LO_REG, val1); + MV_REG_WRITE(SPI_CODEC_CMD_HI_REG, val2); + MV_REG_WRITE(SPI_CODEC_CTRL_REG, cmd); + + /* Activate */ + MV_REG_WRITE(SPI_CTRL_REG, MV_REG_READ(SPI_CTRL_REG) | SPI_ACTIVE); + + /* Poll for ready indication */ + while( (MV_REG_READ(SPI_CTRL_REG) & SPI_STAT_MASK) == SPI_ACTIVE); + + *data = MV_REG_BYTE_READ(SPI_CODEC_READ_DATA_REG); + + /*MV_TRC_REC(" data=0x%x\n",*data);*/ + return MV_OK; +} + +/****************** +** Debug Display ** +******************/ +MV_VOID mvOsRegDump(MV_U32 reg) +{ + mvOsPrintf("0x%05x: %08x\n",reg,MV_REG_READ(reg)); +} + +MV_VOID mvTdmRegsDump(MV_VOID) +{ + MV_U8 i; + MV_TDM_CH_INFO *chInfo; + + mvOsPrintf("TDM Control:\n"); + mvOsRegDump(TDM_SPI_MUX_REG); + mvOsRegDump(INT_RESET_SELECT_REG); + mvOsRegDump(INT_STATUS_MASK_REG); + mvOsRegDump(INT_STATUS_REG); + mvOsRegDump(INT_EVENT_MASK_REG); + mvOsRegDump(PCM_CTRL_REG); + mvOsRegDump(TIMESLOT_CTRL_REG); + mvOsRegDump(PCM_CLK_RATE_DIV_REG); + mvOsRegDump(FRAME_TIMESLOT_REG); + mvOsRegDump(DUMMY_RX_WRITE_DATA_REG); + mvOsRegDump(MISC_CTRL_REG); + mvOsPrintf("TDM Channel Control:\n"); + for(i = 0; i < MV_TDM_TOTAL_CHANNELS; i++) + { + mvOsRegDump(CH_DELAY_CTRL_REG(i)); + mvOsRegDump(CH_SAMPLE_REG(i)); + mvOsRegDump(CH_DBG_REG(i)); + mvOsRegDump(CH_TX_CUR_ADDR_REG(i)); + mvOsRegDump(CH_RX_CUR_ADDR_REG(i)); + mvOsRegDump(CH_ENABLE_REG(i)); + mvOsRegDump(CH_BUFF_OWN_REG(i)); + mvOsRegDump(CH_TX_ADDR_REG(i)); + mvOsRegDump(CH_RX_ADDR_REG(i)); + } + mvOsPrintf("TDM interrupts:\n"); + mvOsRegDump(INT_EVENT_MASK_REG); + mvOsRegDump(INT_STATUS_MASK_REG); + mvOsRegDump(INT_STATUS_REG); + for(i = 0; i < MV_TDM_TOTAL_CHANNELS; i++) + { + mvOsPrintf("ch%d info:\n",i); + chInfo = tdmChInfo[i]; + mvOsPrintf("RX buffs:\n"); + mvOsPrintf("buff0: virt=%p phys=%p\n",chInfo->rxBuffVirt[0],(MV_U32*)(chInfo->rxBuffPhys[0])); + mvOsPrintf("buff1: virt=%p phys=%p\n",chInfo->rxBuffVirt[1],(MV_U32*)(chInfo->rxBuffPhys[1])); + mvOsPrintf("TX buffs:\n"); + mvOsPrintf("buff0: virt=%p phys=%p\n",chInfo->txBuffVirt[0],(MV_U32*)(chInfo->txBuffPhys[0])); + mvOsPrintf("buff1: virt=%p phys=%p\n",chInfo->txBuffVirt[1],(MV_U32*)(chInfo->txBuffPhys[1])); + } +} + +static MV_VOID mvTdmShowProperties(MV_VOID) +{ + mvOsPrintf("TDM dual channel device rev 0x%x\n", MV_REG_READ(TDM_REV_REG)); +} + + +MV_U8 currRxSampleGet(MV_U8 ch) +{ + return( MV_REG_BYTE_READ(CH_DBG_REG(ch)+1) ); +} +MV_U8 currTxSampleGet(MV_U8 ch) +{ + return( MV_REG_BYTE_READ(CH_DBG_REG(ch)+3) ); +} diff --git a/board/mv_feroceon/mv_hal/voiceband/tdm/mvTdm.h b/board/mv_feroceon/mv_hal/voiceband/tdm/mvTdm.h new file mode 100644 index 0000000..7dee6a9 --- /dev/null +++ b/board/mv_feroceon/mv_hal/voiceband/tdm/mvTdm.h @@ -0,0 +1,203 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvTdmh +#define __INCmvTdmh + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "voiceband/tdm/mvTdmRegs.h" +#include "ctrlEnv/sys/mvSysTdm.h" +#include "voiceband/voiceband.h" + +/* Defines */ +#define SAMPLES_BUFF_SIZE(bandMode, factor) \ + ((bandMode == MV_NARROW_BAND) ? (factor * 80) : (factor * 160)) + +#define MV_TDM_CH_BUFF_SIZE(pcmFormat, bandMode, factor) \ + (pcmFormat == MV_PCM_FORMAT_LINEAR ? (2 * SAMPLES_BUFF_SIZE(bandMode, factor)) : \ + SAMPLES_BUFF_SIZE(bandMode, factor)) + +#define MV_TDM_AGGR_BUFF_SIZE(pcmFormat, bandMode, factor) (2 * MV_TDM_CH_BUFF_SIZE(pcmFormat, bandMode, factor)) +#define MV_TDM_TOTAL_CHANNELS 2 +#define MV_TDM_2CHANNELS_SUPPORT 2 +#define MV_TDM_INT_COUNTER 2 +#define MV_TDM_MAX_SAMPLE_PERIOD 30 /* ms */ +#define MV_TDM_BASE_SAMPLE_PERIOD 10 /* ms */ + +/* TDM IRQ types */ +#define MV_EMPTY_INT 0 +#define MV_RX_INT BIT0 +#define MV_TX_INT BIT1 +#define MV_PHONE_INT BIT2 +#define MV_ERROR_INT BIT3 + +/* PCM SLOT configuration */ +/* Assume Rx & Tx have the same slots always */ +#define PCM_SLOT_PCLK 8 +#define CH0_RX_SLOT 2 +#define CH0_TX_SLOT 2 +#define CH1_RX_SLOT 10 +#define CH1_TX_SLOT 10 + +/* WB Mode */ +#define CH0_RX_DELAY (2 * PCM_SLOT_PCLK) +#define CH0_TX_DELAY (0 * PCM_SLOT_PCLK) +#define CH1_RX_DELAY (14 * PCM_SLOT_PCLK) +#define CH1_TX_DELAY (14 * PCM_SLOT_PCLK) + +#define CH0_WB_RX_DELAY (10 * PCM_SLOT_PCLK) +#define CH0_WB_TX_DELAY (10 * PCM_SLOT_PCLK) +#define CH1_WB_RX_DELAY (18 * PCM_SLOT_PCLK) +#define CH1_WB_TX_DELAY (18 * PCM_SLOT_PCLK) + +#define TDM_INT_SLIC (DMA_ABORT_BIT|SLIC_INT_BIT) +#define TDM_INT_TX(ch) (TX_UNDERFLOW_BIT(ch)|TX_BIT(ch)|TX_IDLE_BIT(ch)) +#define TDM_INT_RX(ch) (RX_OVERFLOW_BIT(ch)|RX_BIT(ch)|RX_IDLE_BIT(ch)) + +/* TDM Registers Configuration */ +#if defined(MV_TDM_USE_EXTERNAL_PCLK_SOURCE) +#define CONFIG_PCM_CRTL (MASTER_PCLK_EXTERNAL | MASTER_FS_TDM |DATA_POLAR_NEG | \ + FS_POLAR_NEG | INVERT_FS_HI | FS_TYPE_SHORT | \ + CH_DELAY_DISABLE | \ + CH_QUALITY_DISABLE | QUALITY_POLARITY_NEG | \ + QUALITY_TYPE_TIME_SLOT | CS_CTRL_DONT_CARE | \ + WIDEBAND_OFF | PERF_GBUS_TWO_ACCESS) + +#else +#define CONFIG_PCM_CRTL (MASTER_PCLK_TDM | MASTER_FS_TDM |DATA_POLAR_NEG | \ + FS_POLAR_NEG | INVERT_FS_HI | FS_TYPE_SHORT | \ + CH_DELAY_DISABLE | \ + CH_QUALITY_DISABLE | QUALITY_POLARITY_NEG | \ + QUALITY_TYPE_TIME_SLOT | CS_CTRL_DONT_CARE | \ + WIDEBAND_OFF | PERF_GBUS_TWO_ACCESS) +#endif + +#if defined(MV_TDM_USE_EXTERNAL_PCLK_SOURCE) +#define CONFIG_WB_PCM_CRTL (MASTER_PCLK_EXTERNAL | MASTER_FS_TDM |DATA_POLAR_NEG | \ + FS_POLAR_NEG | INVERT_FS_HI | FS_TYPE_SHORT | \ + CH_DELAY_ENABLE | \ + CH_QUALITY_DISABLE | QUALITY_POLARITY_NEG | \ + QUALITY_TYPE_TIME_SLOT | CS_CTRL_DONT_CARE | \ + WIDEBAND_ON | PERF_GBUS_TWO_ACCESS) +#else +#define CONFIG_WB_PCM_CRTL (MASTER_PCLK_TDM | MASTER_FS_TDM |DATA_POLAR_NEG | \ + FS_POLAR_NEG | INVERT_FS_HI | FS_TYPE_SHORT | \ + CH_DELAY_ENABLE | \ + CH_QUALITY_DISABLE | QUALITY_POLARITY_NEG | \ + QUALITY_TYPE_TIME_SLOT | CS_CTRL_DONT_CARE | \ + WIDEBAND_ON | PERF_GBUS_TWO_ACCESS) +#endif + +#define CONFIG_TIMESLOT_CTRL ((CH0_RX_SLOT<= MV_XOR_MAX_CHAN) + { + DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n",__FUNCTION__ ,chan)); + return MV_BAD_PARAM; + } + if (NULL == pXorEccConfig) + { + DB(mvOsPrintf("%s: ERR. pXorEccConfig is NULL pointer\n", + __FUNCTION__ )); + return MV_BAD_PTR; + } + if (MV_ACTIVE == mvXorStateGet(chan)) + { + DB(mvOsPrintf("%s: ERR. Channel is already active\n", __FUNCTION__ )); + return MV_BUSY; + } + if ((pXorEccConfig->sectorSize < XETMCR_SECTION_SIZE_MIN_VALUE) || + (pXorEccConfig->sectorSize > XETMCR_SECTION_SIZE_MAX_VALUE)) + { + DB(mvOsPrintf("%s: ERR. sectorSize must be between %d to %d\n", + __FUNCTION__,XETMCR_SECTION_SIZE_MIN_VALUE, + XETMCR_SECTION_SIZE_MAX_VALUE)); + return MV_BAD_PARAM; + } + if ((pXorEccConfig->blockSize < XEXBSR_BLOCK_SIZE_MIN_VALUE) || + (pXorEccConfig->blockSize > XEXBSR_BLOCK_SIZE_MAX_VALUE)) + { + DB(mvOsPrintf("%s: ERR. Block size must be between %d to %ul\n", + __FUNCTION__,XEXBSR_BLOCK_SIZE_MIN_VALUE, + XEXBSR_BLOCK_SIZE_MAX_VALUE)); + return MV_BAD_PARAM; + } + if (0x0 == pXorEccConfig->destPtr) + { + DB(mvOsPrintf("%s: ERR. destPtr is NULL pointer\n",__FUNCTION__ )); + return MV_BAD_PARAM; + } + + /* set the operation mode to ECC */ + temp = MV_REG_READ(XOR_CONFIG_REG(XOR_UNIT(chan),XOR_CHAN(chan))); + temp &= ~XEXCR_OPERATION_MODE_MASK; + temp |= XEXCR_OPERATION_MODE_ECC; + MV_REG_WRITE(XOR_CONFIG_REG(XOR_UNIT(chan),XOR_CHAN(chan)), temp); + + /* update the TimerEn bit in the XOR Engine Timer Mode + Control Register (XETMCR) */ + if (pXorEccConfig->periodicEnable) + { + MV_REG_BIT_SET(XOR_TIMER_MODE_CTRL_REG(XOR_UNIT(chan)),XETMCR_TIMER_EN_MASK); + } + else + { + MV_REG_BIT_RESET(XOR_TIMER_MODE_CTRL_REG(XOR_UNIT(chan)),XETMCR_TIMER_EN_MASK); + } + + /* update the SectionSizeCtrl bit in the XOR Engine Timer Mode Control + Register (XETMCR) */ + temp = MV_REG_READ(XOR_TIMER_MODE_CTRL_REG(XOR_UNIT(chan))); + temp &= ~XETMCR_SECTION_SIZE_CTRL_MASK; + temp |= (pXorEccConfig->sectorSize << XETMCR_SECTION_SIZE_CTRL_OFFS); + MV_REG_WRITE(XOR_TIMER_MODE_CTRL_REG(XOR_UNIT(chan)), temp); + + /* update the DstPtr field in the XOR Engine [0..1] Destination Pointer + Register (XExDPR0) */ + MV_REG_WRITE(XOR_DST_PTR_REG(XOR_UNIT(chan),XOR_CHAN(chan)), pXorEccConfig->destPtr); + + /* update the BlockSize field in the XOR Engine[0..1] Block Size + Registers (XExBSR) */ + MV_REG_WRITE(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan),XOR_CHAN(chan)), + pXorEccConfig->blockSize); + + /* update the XOR Engine Timer Mode Initial Value Register (XETMIVR) */ + tClkCycles = pXorEccConfig->tClkTicks; + MV_REG_WRITE(XOR_TIMER_MODE_INIT_VAL_REG(XOR_UNIT(chan)), tClkCycles); + + /* start transfer */ + MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan),XOR_CHAN(chan)), + XEXACTR_XESTART_MASK); + + return MV_OK; +} + +/******************************************************************************* +* mvXorEccCurrTimerGet - Return ECC timer current value. +* +* DESCRIPTION: +* Return the ECC timer mode Current value. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Timer ticks (in Tclk frequancy). +* +*******************************************************************************/ +MV_U32 mvXorEccCurrTimerGet(MV_U32 chan, MV_U32 tClk) +{ + /* read the current Tclk */ + return (MV_REG_READ(XOR_TIMER_MODE_CURR_VAL_REG(XOR_UNIT(chan)))); +} + +/******************************************************************************* +* mvXorMemInit - +* +* DESCRIPTION: +* +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_STATUS mvXorMemInit(MV_U32 chan, MV_U32 startPtr, MV_U32 blockSize, + MV_U32 initValHigh, MV_U32 initValLow) +{ + MV_U32 temp; + + /* Parameter checking */ + if (chan >= MV_XOR_MAX_CHAN) + { + mvOsPrintf("%s: ERR. Invalid chan num %d\n",__FUNCTION__ , chan); + return MV_BAD_PARAM; + } + if (MV_ACTIVE == mvXorStateGet(chan)) + { + mvOsPrintf("%s: ERR. Channel is already active\n", __FUNCTION__ ); + return MV_BUSY; + } + if ((blockSize < XEXBSR_BLOCK_SIZE_MIN_VALUE) || + (blockSize > XEXBSR_BLOCK_SIZE_MAX_VALUE)) + { + mvOsPrintf("%s: ERR. Block size must be between %d to %ul\n", + __FUNCTION__,XEXBSR_BLOCK_SIZE_MIN_VALUE, + XEXBSR_BLOCK_SIZE_MAX_VALUE); + return MV_BAD_PARAM; + } +#if 0 +/* tzachi - this is done purposely by u-boot */ + if (0x0 == startPtr) + { + mvOsPrintf("%s: ERR. startPtr is NULL pointer\n", __FUNCTION__ ); + return MV_BAD_PARAM; + } +#endif + + /* set the operation mode to Memory Init */ + temp = MV_REG_READ(XOR_CONFIG_REG(XOR_UNIT(chan),XOR_CHAN(chan))); + temp &= ~XEXCR_OPERATION_MODE_MASK; + temp |= XEXCR_OPERATION_MODE_MEM_INIT; + MV_REG_WRITE(XOR_CONFIG_REG(XOR_UNIT(chan),XOR_CHAN(chan)), temp); + + /* update the startPtr field in XOR Engine [0..1] Destination Pointer + Register (XExDPR0) */ + MV_REG_WRITE(XOR_DST_PTR_REG(XOR_UNIT(chan),XOR_CHAN(chan)), startPtr); + + /* update the BlockSize field in the XOR Engine[0..1] Block Size + Registers (XExBSR) */ + MV_REG_WRITE(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan),XOR_CHAN(chan)), blockSize); + + /* update the field InitValL in the XOR Engine Initial Value Register + Low (XEIVRL) */ + MV_REG_WRITE(XOR_INIT_VAL_LOW_REG(XOR_UNIT(chan)), initValLow); + + /* update the field InitValH in the XOR Engine Initial Value Register + High (XEIVRH) */ + MV_REG_WRITE(XOR_INIT_VAL_HIGH_REG(XOR_UNIT(chan)), initValHigh); + + /* start transfer */ + MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan),XOR_CHAN(chan)), + XEXACTR_XESTART_MASK); + + return MV_OK; +} + +/******************************************************************************* +* mvXorTransfer - Transfer data from source to destination on one of +* three modes (XOR,CRC32,DMA) +* +* DESCRIPTION: +* This function initiates XOR channel, according to function parameters, +* in order to perform XOR or CRC32 or DMA transaction. +* To gain maximum performance the user is asked to keep the following +* restrictions: +* 1) Selected engine is available (not busy). +* 1) This module does not take into consideration CPU MMU issues. +* In order for the XOR engine to access the appropreate source +* and destination, address parameters must be given in system +* physical mode. +* 2) This API does not take care of cache coherency issues. The source, +* destination and in case of chain the descriptor list are assumed +* to be cache coherent. +* 4) Parameters validity. For example, does size parameter exceeds +* maximum byte count of descriptor mode (16M or 64K). +* +* INPUT: +* chan - XOR channel number. See MV_XOR_CHANNEL enumerator. +* xorType - One of three: XOR, CRC32 and DMA operations. +* xorChainPtr - address of chain pointer +* +* OUTPUT: +* None. +* +* RETURS: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorTransfer(MV_U32 chan, MV_XOR_TYPE xorType, MV_U32 xorChainPtr) +{ + MV_U32 temp; + + /* Parameter checking */ + if (chan >= MV_XOR_MAX_CHAN) + { + DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n",__FUNCTION__ , chan)); + return MV_BAD_PARAM; + } + if (MV_ACTIVE == mvXorStateGet(chan)) + { + DB(mvOsPrintf("%s: ERR. Channel is already active\n", __FUNCTION__ )); + return MV_BUSY; + } + if (0x0 == xorChainPtr) + { + DB(mvOsPrintf("%s: ERR. xorChainPtr is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PARAM; + } + + /* read configuration register and mask the operation mode field */ + temp = MV_REG_READ(XOR_CONFIG_REG(XOR_UNIT(chan),XOR_CHAN(chan))); + temp &= ~XEXCR_OPERATION_MODE_MASK; + + switch (xorType) + { + case MV_XOR: + if (0 != (xorChainPtr & XEXDPR_DST_PTR_XOR_MASK)) + { + DB(mvOsPrintf("%s: ERR. Invalid chain pointer (bits [5:0] must " + "be cleared)\n",__FUNCTION__ )); + return MV_BAD_PARAM; + } + /* set the operation mode to XOR */ + temp |= XEXCR_OPERATION_MODE_XOR; + break; + + case MV_DMA: + if (0 != (xorChainPtr & XEXDPR_DST_PTR_DMA_MASK)) + { + DB(mvOsPrintf("%s: ERR. Invalid chain pointer (bits [4:0] must " + "be cleared)\n",__FUNCTION__ )); + return MV_BAD_PARAM; + } + /* set the operation mode to DMA */ + temp |= XEXCR_OPERATION_MODE_DMA; + break; + + case MV_CRC32: + if (0 != (xorChainPtr & XEXDPR_DST_PTR_CRC_MASK)) + { + DB(mvOsPrintf("%s: ERR. Invalid chain pointer (bits [4:0] must " + "be cleared)\n",__FUNCTION__ )); + return MV_BAD_PARAM; + } + /* set the operation mode to CRC32 */ + temp |= XEXCR_OPERATION_MODE_CRC; + break; + + default: + return MV_BAD_PARAM; + } + + /* write the operation mode to the register */ + MV_REG_WRITE(XOR_CONFIG_REG(XOR_UNIT(chan),XOR_CHAN(chan)), temp); + /* update the NextDescPtr field in the XOR Engine [0..1] Next Descriptor + Pointer Register (XExNDPR) */ + MV_REG_WRITE(XOR_NEXT_DESC_PTR_REG(XOR_UNIT(chan),XOR_CHAN(chan)), + xorChainPtr); + + /* start transfer */ + MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan),XOR_CHAN(chan)), + XEXACTR_XESTART_MASK); + + return MV_OK; +} + +/******************************************************************************* +* mvXorStateGet - Get XOR channel state. +* +* DESCRIPTION: +* XOR channel activity state can be active, idle, paused. +* This function retrunes the channel activity state. +* +* INPUT: +* chan - the channel number +* +* OUTPUT: +* None. +* +* RETURN: +* XOR_CHANNEL_IDLE - If the engine is idle. +* XOR_CHANNEL_ACTIVE - If the engine is busy. +* XOR_CHANNEL_PAUSED - If the engine is paused. +* MV_UNDEFINED_STATE - If the engine state is undefind or there is no +* such engine +* +*******************************************************************************/ +MV_STATE mvXorStateGet(MV_U32 chan) +{ + MV_U32 state; + + /* Parameter checking */ + if (chan >= MV_XOR_MAX_CHAN) + { + DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n",__FUNCTION__ , chan)); + return MV_UNDEFINED_STATE; + } + + /* read the current state */ + state = MV_REG_READ(XOR_ACTIVATION_REG(XOR_UNIT(chan),XOR_CHAN(chan))); + state &= XEXACTR_XESTATUS_MASK; + + /* return the state */ + switch (state) + { + case XEXACTR_XESTATUS_IDLE: + return MV_IDLE; + case XEXACTR_XESTATUS_ACTIVE: + return MV_ACTIVE; + case XEXACTR_XESTATUS_PAUSED: + return MV_PAUSED; + } + return MV_UNDEFINED_STATE; +} + +/******************************************************************************* +* mvXorCommandSet - Set command of XOR channel +* +* DESCRIPTION: +* XOR channel can be started, idle, paused and restarted. +* Paused can be set only if channel is active. +* Start can be set only if channel is idle or paused. +* Restart can be set only if channel is paused. +* Stop can be set only if channel is active. +* +* INPUT: +* chan - The channel number +* command - The command type (start, stop, restart, pause) +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK on success , MV_BAD_PARAM on erroneous parameter, MV_ERROR on +* undefind XOR engine mode +* +*******************************************************************************/ +MV_STATUS mvXorCommandSet(MV_U32 chan, MV_COMMAND command) +{ + MV_STATE state; + + /* Parameter checking */ + if (chan >= MV_XOR_MAX_CHAN) + { + DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n",__FUNCTION__ , chan)); + return MV_BAD_PARAM; + } + + /* get the current state */ + state = mvXorStateGet(chan); + + /* command is start and current state is idle */ + if ((command == MV_START) && (state == MV_IDLE)) + { + MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan),XOR_CHAN(chan)), + XEXACTR_XESTART_MASK); + return MV_OK; + } + /* command is stop and current state is active*/ + else if ((command == MV_STOP) && (state == MV_ACTIVE)) + { + MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan),XOR_CHAN(chan)), + XEXACTR_XESTOP_MASK); + return MV_OK; + } + /* command is paused and current state is active */ + else if ((command == MV_PAUSED) && (state == MV_ACTIVE)) + { + MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan),XOR_CHAN(chan)), + XEXACTR_XEPAUSE_MASK); + return MV_OK; + } + /* command is restart and current state is paused*/ + else if ((command == MV_RESTART) && (state == MV_PAUSED)) + { + MV_REG_BIT_SET(XOR_ACTIVATION_REG(XOR_UNIT(chan),XOR_CHAN(chan)), + XEXACTR_XERESTART_MASK); + return MV_OK; + } + + /* command is stop and current state is active*/ + else if ((command == MV_STOP) && (state == MV_IDLE)) + { + return MV_OK; + } + + /* illegal command */ + DB(mvOsPrintf("%s: ERR. Illegal command\n", __FUNCTION__)); + + return MV_BAD_PARAM; +} + +/******************************************************************************* +* mvXorOverrideSet - Set XOR target window override +* +* DESCRIPTION: +* The address override feature enables additional address decoupling. +* For example, it allows the use of the same source and destination +* addresses while the source is targeted to one interface and +* destination to a second interface. +* XOR source/destination/next descriptor addresses can be override per +* address decode windows 0,1,2 and 3 only. +* This function set override parameters per XOR channel. It access +* XOR control register low. +* +* INPUT: +* chan - XOR channel number. See MV_XOR_CHANNEL enumerator. +* winNum - Override window number. +* Note: Not all windows can override. +* override - Type of override. See MV_XOR_OVERRIDE enumerator. +* enable - Window override is enabled or disabled +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ + +MV_STATUS mvXorOverrideSet(MV_U32 chan, MV_XOR_OVERRIDE_TARGET target, + MV_U32 winNum, MV_BOOL enable) +{ + MV_U32 temp; + + /* Parameter checking */ + if (chan >= MV_XOR_MAX_CHAN) + { + + DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__, chan)); + return MV_BAD_PARAM; + } + if (winNum >= XOR_MAX_OVERRIDE_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + + /* set the enable bit */ + if (enable) + { + MV_REG_BIT_SET(XOR_OVERRIDE_CTRL_REG(chan),XEXAOCR_OVR_EN_MASK(target)); + } + else + { + MV_REG_BIT_RESET(XOR_OVERRIDE_CTRL_REG(chan), + XEXAOCR_OVR_EN_MASK(target)); + } + + /* read the override control register */ + temp = MV_REG_READ(XOR_OVERRIDE_CTRL_REG(chan)); + temp &= ~XEXAOCR_OVR_PTR_MASK(target); + temp |= (winNum << XEXAOCR_OVR_PTR_OFFS(target)); + MV_REG_WRITE(XOR_OVERRIDE_CTRL_REG(chan), temp); + return MV_OK; +} + + diff --git a/board/mv_feroceon/mv_hal/xor/mvXor.h b/board/mv_feroceon/mv_hal/xor/mvXor.h new file mode 100644 index 0000000..1ab3208 --- /dev/null +++ b/board/mv_feroceon/mv_hal/xor/mvXor.h @@ -0,0 +1,230 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvXor.h - Header File for : +* +* DESCRIPTION: +* This file contains Marvell Controller XOR HW library API. +* NOTE: This HW library API assumes XOR source, destination and +* descriptors are cache coherent. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCMVxorh +#define __INCMVxorh + +#include "mvCommon.h" +#include "mvOs.h" +#include "xor/mvXorRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* typedefs */ + +/* This enumerator describes the type of functionality the XOR channel */ +/* can have while using the same data structures. */ +typedef enum _mvXorType +{ + MV_XOR, /* XOR channel functions as XOR accelerator */ + MV_DMA, /* XOR channel functions as IDMA channel */ + MV_CRC32 /* XOR channel functions as CRC 32 calculator */ +}MV_XOR_TYPE; + +#if defined(MV_CPU_LE) + /* This structure describes XOR descriptor size 64bytes */ +typedef struct _mvXorDesc +{ + MV_U32 status; /* Successful descriptor execution indication */ + MV_U32 crc32Result; /* Result of CRC-32 calculation */ + MV_U32 descCommand; /* type of operation to be carried out on the data */ + MV_U32 phyNextDescPtr;/* Next descriptor address pointer */ + MV_U32 byteCnt; /* Size of source and destination blocks in bytes */ + MV_U32 phyDestAdd; /* Destination Block address pointer */ + MV_U32 srcAdd0; /* source block #0 address pointer */ + MV_U32 srcAdd1; /* source block #1 address pointer */ + MV_U32 srcAdd2; /* source block #2 address pointer */ + MV_U32 srcAdd3; /* source block #3 address pointer */ + MV_U32 srcAdd4; /* source block #4 address pointer */ + MV_U32 srcAdd5; /* source block #6 address pointer */ + MV_U32 srcAdd6; /* source block #6 address pointer */ + MV_U32 srcAdd7; /* source block #7 address pointer */ + MV_U32 reserved0; + MV_U32 reserved1; +} MV_XOR_DESC; + + +/* XOR descriptor structure for CRC and DMA descriptor */ +typedef struct _mvCrcDmaDesc +{ + MV_U32 status; /* Successful descriptor execution indication */ + MV_U32 crc32Result; /* Result of CRC-32 calculation */ + MV_U32 descCommand; /* type of operation to be carried out on the data */ + MV_U32 nextDescPtr; /* Next descriptor address pointer */ + MV_U32 byteCnt; /* Size of source block part represented by the descriptor */ + MV_U32 destAdd; /* Destination Block address pointer (not used in CRC32 */ + MV_U32 srcAdd0; /* Mode: Source Block address pointer */ + MV_U32 srcAdd1; /* Mode: Source Block address pointer */ +} MV_CRC_DMA_DESC; + +#elif defined(MV_CPU_BE) +/* This structure describes XOR descriptor size 64bytes */ +typedef struct _mvXorDesc +{ + MV_U32 crc32Result; /* Result of CRC-32 calculation */ + MV_U32 status; /* Successful descriptor execution indication */ + MV_U32 phyNextDescPtr; /* Next descriptor address pointer */ + MV_U32 descCommand; /* type of operation to be carried out on the data */ + MV_U32 phyDestAdd; /* Destination Block address pointer */ + MV_U32 byteCnt; /* Size of source and destination blocks in bytes */ + MV_U32 srcAdd1; /* source block #1 address pointer */ + MV_U32 srcAdd0; /* source block #0 address pointer */ + MV_U32 srcAdd3; /* source block #3 address pointer */ + MV_U32 srcAdd2; /* source block #2 address pointer */ + MV_U32 srcAdd5; /* source block #5 address pointer */ + MV_U32 srcAdd4; /* source block #4 address pointer */ + MV_U32 srcAdd7; /* source block #7 address pointer */ + MV_U32 srcAdd6; /* source block #6 address pointer */ + MV_U32 reserved0; + MV_U32 reserved1; +} MV_XOR_DESC; + + +/* XOR descriptor structure for CRC and DMA descriptor */ +typedef struct _mvCrcDmaDesc +{ + MV_U32 crc32Result; /* Result of CRC-32 calculation */ + MV_U32 status; /* Successful descriptor execution indication */ + MV_U32 nextDescPtr; /* Next descriptor address pointer */ + MV_U32 descCommand; /* type of operation to be carried out on the data */ + MV_U32 destAdd; /* Destination Block address pointer (not used in CRC32 */ + MV_U32 byteCnt; /* Size of source block part represented by the descriptor */ + MV_U32 srcAdd1; /* Mode: Source Block address pointer */ + MV_U32 srcAdd0; /* Mode: Source Block address pointer */ +} MV_CRC_DMA_DESC; + +#endif + +typedef struct _mvXorEcc +{ + MV_U32 destPtr; /* Target block pointer to ECC/MemInit operation */ + MV_U32 blockSize; /* Block size in bytes for ECC/MemInit operation */ + MV_BOOL periodicEnable; /* Enable Timer Mode */ + MV_U32 tClkTicks; /* ECC timer mode initial count - down value */ + MV_U32 sectorSize; /* section size for ECC timer mode operation */ +}MV_XOR_ECC; + +typedef enum _mvXorOverrideTarget +{ + SRC_ADDR0, /* Source Address #0 Control */ + SRC_ADDR1, /* Source Address #1 Control */ + SRC_ADDR2, /* Source Address #2 Control */ + SRC_ADDR3, /* Source Address #3 Control */ + SRC_ADDR4, /* Source Address #4 Control */ + SRC_ADDR5, /* Source Address #5 Control */ + SRC_ADDR6, /* Source Address #6 Control */ + SRC_ADDR7, /* Source Address #7 Control */ + XOR_DST_ADDR, /* Destination Address Control */ + XOR_NEXT_DESC /* Next Descriptor Address Control */ + +}MV_XOR_OVERRIDE_TARGET; + +#define XOR_MAX_OVERRIDE_WIN 4 /* Maximum address override windows */ + +#define XOR_OVERRIDE_CTRL_REG(chan) (XOR_UNIT_BASE(XOR_UNIT(chan))+(0x2A0 + ((XOR_CHAN(chan)) * 4))) +/* XOR Engine [0..1] Address Override Control Register (XExAOCR) */ +#define XEXAOCR_OVR_EN_OFFS(target) (3 * target) +#define XEXAOCR_OVR_EN_MASK(target) (1 << (XEXAOCR_OVR_EN_OFFS(target))) +#define XEXAOCR_OVR_PTR_OFFS(target) ((3 * target) + 1) +#define XEXAOCR_OVR_PTR_MASK(target) (3 << (XEXAOCR_OVR_PTR_OFFS(target))) +#define XEXAOCR_OVR_BAR(winNum,target) (winNum << (XEXAOCR_OVR_PTR_OFFS(target))) + +/* for controllers that have two XOR units, then chans 2 & 3 will be mapped*/ +/* to channels 0 & 1 of unit 1 */ +#define XOR_UNIT(chan) ((chan) >> 1) +#define XOR_CHAN(chan) ((chan) & 1) + +MV_VOID mvXorHalInit (MV_U32 xorChanNum); +MV_STATUS mvXorCtrlSet(MV_U32 chan, MV_U32 xorCtrl); +MV_STATUS mvXorEccClean(MV_U32 chan, MV_XOR_ECC *pXorEccConfig); +MV_U32 mvXorEccCurrTimerGet(MV_U32 chan, MV_U32 tClk); +MV_STATUS mvXorMemInit(MV_U32 chan, MV_U32 startPtr, MV_U32 blockSize, + MV_U32 initValHigh, MV_U32 initValLow); +MV_STATUS mvXorTransfer(MV_U32 chan, MV_XOR_TYPE xorType, MV_U32 xorChainPtr); +MV_STATE mvXorStateGet(MV_U32 chan); +MV_STATUS mvXorCommandSet(MV_U32 chan, MV_COMMAND command); +MV_STATUS mvXorOverrideSet(MV_U32 chan, MV_XOR_OVERRIDE_TARGET target, + MV_U32 winNum, MV_BOOL enable); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/board/mv_feroceon/mv_hal/xor/mvXorRegs.h b/board/mv_feroceon/mv_hal/xor/mvXorRegs.h new file mode 100644 index 0000000..b81f347 --- /dev/null +++ b/board/mv_feroceon/mv_hal/xor/mvXorRegs.h @@ -0,0 +1,225 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvXorSpech +#define __INCmvXorSpech + +#ifdef __cplusplus +extern "C" { +#endif + +/* defines */ + +/* XOR Engine Control Register Map */ +#define XOR_CHANNEL_ARBITER_REG(unit) (XOR_UNIT_BASE(unit)) +#define XOR_CONFIG_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x10 + ((chan) * 4))) +#define XOR_ACTIVATION_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x20 + ((chan) * 4))) + +/* XOR Engine Interrupt Register Map */ +#define XOR_CAUSE_REG(unit) (XOR_UNIT_BASE(unit)+(0x30)) +#define XOR_MASK_REG(unit) (XOR_UNIT_BASE(unit)+(0x40)) +#define XOR_ERROR_CAUSE_REG(unit) (XOR_UNIT_BASE(unit)+(0x50)) +#define XOR_ERROR_ADDR_REG(unit) (XOR_UNIT_BASE(unit)+(0x60)) + +/* XOR Engine Descriptor Register Map */ +#define XOR_NEXT_DESC_PTR_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x200 + ((chan) * 4))) +#define XOR_CURR_DESC_PTR_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x210 + ((chan) * 4))) +#define XOR_BYTE_COUNT_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x220 + ((chan) * 4))) + +/* XOR Engine ECC/MemInit Register Map */ +#define XOR_DST_PTR_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x2B0 + ((chan) * 4))) +#define XOR_BLOCK_SIZE_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x2C0 + ((chan) * 4))) +#define XOR_TIMER_MODE_CTRL_REG(unit) (XOR_UNIT_BASE(unit)+(0x2D0)) +#define XOR_TIMER_MODE_INIT_VAL_REG(unit) (XOR_UNIT_BASE(unit)+(0x2D4)) +#define XOR_TIMER_MODE_CURR_VAL_REG(unit) (XOR_UNIT_BASE(unit)+(0x2D8)) +#define XOR_INIT_VAL_LOW_REG(unit) (XOR_UNIT_BASE(unit)+(0x2E0)) +#define XOR_INIT_VAL_HIGH_REG(unit) (XOR_UNIT_BASE(unit)+(0x2E4)) + +/* XOR Engine Debug Register Map */ +#define XOR_DEBUG_REG(unit) (XOR_UNIT_BASE(unit)+(0x70)) + + +/* XOR register fileds */ + + +/* XOR Engine Channel Arbiter Register */ +#define XECAR_SLICE_OFFS(sliceNum) (sliceNum) +#define XECAR_SLICE_MASK(sliceNum) (1 << (XECAR_SLICE_OFFS(sliceNum))) + +/* XOR Engine [0..1] Configuration Registers (XExCR) */ +#define XEXCR_OPERATION_MODE_OFFS (0) +#define XEXCR_OPERATION_MODE_MASK (7 << XEXCR_OPERATION_MODE_OFFS) +#define XEXCR_OPERATION_MODE_XOR (0 << XEXCR_OPERATION_MODE_OFFS) +#define XEXCR_OPERATION_MODE_CRC (1 << XEXCR_OPERATION_MODE_OFFS) +#define XEXCR_OPERATION_MODE_DMA (2 << XEXCR_OPERATION_MODE_OFFS) +#define XEXCR_OPERATION_MODE_ECC (3 << XEXCR_OPERATION_MODE_OFFS) +#define XEXCR_OPERATION_MODE_MEM_INIT (4 << XEXCR_OPERATION_MODE_OFFS) + +#define XEXCR_SRC_BURST_LIMIT_OFFS (4) +#define XEXCR_SRC_BURST_LIMIT_MASK (7 << XEXCR_SRC_BURST_LIMIT_OFFS) +#define XEXCR_DST_BURST_LIMIT_OFFS (8) +#define XEXCR_DST_BURST_LIMIT_MASK (7 << XEXCR_DST_BURST_LIMIT_OFFS) +#define XEXCR_DRD_RES_SWP_OFFS (12) +#define XEXCR_DRD_RES_SWP_MASK (1 << XEXCR_DRD_RES_SWP_OFFS) +#define XEXCR_DWR_REQ_SWP_OFFS (13) +#define XEXCR_DWR_REQ_SWP_MASK (1 << XEXCR_DWR_REQ_SWP_OFFS) +#define XEXCR_DES_SWP_OFFS (14) +#define XEXCR_DES_SWP_MASK (1 << XEXCR_DES_SWP_OFFS) +#define XEXCR_REG_ACC_PROTECT_OFFS (15) +#define XEXCR_REG_ACC_PROTECT_MASK (1 << XEXCR_REG_ACC_PROTECT_OFFS) + + +/* XOR Engine [0..1] Activation Registers (XExACTR) */ +#define XEXACTR_XESTART_OFFS (0) +#define XEXACTR_XESTART_MASK (1 << XEXACTR_XESTART_OFFS) +#define XEXACTR_XESTOP_OFFS (1) +#define XEXACTR_XESTOP_MASK (1 << XEXACTR_XESTOP_OFFS) +#define XEXACTR_XEPAUSE_OFFS (2) +#define XEXACTR_XEPAUSE_MASK (1 << XEXACTR_XEPAUSE_OFFS) +#define XEXACTR_XERESTART_OFFS (3) +#define XEXACTR_XERESTART_MASK (1 << XEXACTR_XERESTART_OFFS) +#define XEXACTR_XESTATUS_OFFS (4) +#define XEXACTR_XESTATUS_MASK (3 << XEXACTR_XESTATUS_OFFS) +#define XEXACTR_XESTATUS_IDLE (0 << XEXACTR_XESTATUS_OFFS) +#define XEXACTR_XESTATUS_ACTIVE (1 << XEXACTR_XESTATUS_OFFS) +#define XEXACTR_XESTATUS_PAUSED (2 << XEXACTR_XESTATUS_OFFS) + +/* XOR Engine Interrupt Cause Register (XEICR) */ +#define XEICR_CHAN_OFFS 16 +#define XEICR_CAUSE_OFFS(chan) (chan * XEICR_CHAN_OFFS) +#define XEICR_CAUSE_MASK(chan, cause) (1 << (cause + XEICR_CAUSE_OFFS(chan))) +#define XEICR_COMP_MASK_ALL 0x000f000f +#define XEICR_COMP_MASK(chan) (0x000f << XEICR_CAUSE_OFFS(chan)) +#define XEICR_ERR_MASK 0x03800380 + +/* XOR Engine Error Cause Register (XEECR) */ +#define XEECR_ERR_TYPE_OFFS 0 +#define XEECR_ERR_TYPE_MASK (0x1f << XEECR_ERR_TYPE_OFFS) + +/* XOR Engine Error Address Register (XEEAR) */ +#define XEEAR_ERR_ADDR_OFFS (0) +#define XEEAR_ERR_ADDR_MASK (0xFFFFFFFF << XEEAR_ERR_ADDR_OFFS) + +/* XOR Engine [0..1] Next Descriptor Pointer Register (XExNDPR) */ +#define XEXNDPR_NEXT_DESC_PTR_OFFS (0) +#define XEXNDPR_NEXT_DESC_PTR_MASK (0xFFFFFFFF << XEXNDPR_NEXT_DESC_PTR_OFFS) + +/* XOR Engine [0..1] Current Descriptor Pointer Register (XExCDPR) */ +#define XEXCDPR_CURRENT_DESC_PTR_OFFS (0) +#define XEXCDPR_CURRENT_DESC_PTR_MASK (0xFFFFFFFF << XEXCDPR_CURRENT_DESC_PTR_OFFS) + +/* XOR Engine [0..1] Byte Count Register (XExBCR) */ +#define XEXBCR_BYTE_CNT_OFFS (0) +#define XEXBCR_BYTE_CNT_MASK (0xFFFFFFFF << XEXBCR_BYTE_CNT_OFFS) + +/* XOR Engine [0..1] Destination Pointer Register (XExDPR0) */ +#define XEXDPR_DST_PTR_OFFS (0) +#define XEXDPR_DST_PTR_MASK (0xFFFFFFFF << XEXDPR_DST_PTR_OFFS) +#define XEXDPR_DST_PTR_XOR_MASK (0x3F) +#define XEXDPR_DST_PTR_DMA_MASK (0x1F) +#define XEXDPR_DST_PTR_CRC_MASK (0x1F) + +/* XOR Engine[0..1] Block Size Registers (XExBSR) */ +#define XEXBSR_BLOCK_SIZE_OFFS (0) +#define XEXBSR_BLOCK_SIZE_MASK (0xFFFFFFFF << XEXBSR_BLOCK_SIZE_OFFS) +#define XEXBSR_BLOCK_SIZE_MIN_VALUE (128) +#define XEXBSR_BLOCK_SIZE_MAX_VALUE (0xFFFFFFFF) + +/* XOR Engine Timer Mode Control Register (XETMCR) */ +#define XETMCR_TIMER_EN_OFFS (0) +#define XETMCR_TIMER_EN_MASK (1 << XETMCR_TIMER_EN_OFFS) +#define XETMCR_TIMER_EN_ENABLE (1 << XETMCR_TIMER_EN_OFFS) +#define XETMCR_TIMER_EN_DISABLE (0 << XETMCR_TIMER_EN_OFFS) +#define XETMCR_SECTION_SIZE_CTRL_OFFS (8) +#define XETMCR_SECTION_SIZE_CTRL_MASK (0x1F << XETMCR_SECTION_SIZE_CTRL_OFFS) +#define XETMCR_SECTION_SIZE_MIN_VALUE (7) +#define XETMCR_SECTION_SIZE_MAX_VALUE (31) + +/* XOR Engine Timer Mode Initial Value Register (XETMIVR) */ +#define XETMIVR_TIMER_INIT_VAL_OFFS (0) +#define XETMIVR_TIMER_INIT_VAL_MASK (0xFFFFFFFF << XETMIVR_TIMER_INIT_VAL_OFFS) + +/* XOR Engine Timer Mode Current Value Register (XETMCVR) */ +#define XETMCVR_TIMER_CRNT_VAL_OFFS (0) +#define XETMCVR_TIMER_CRNT_VAL_MASK (0xFFFFFFFF << XETMCVR_TIMER_CRNT_VAL_OFFS) + +/* XOR Engine Initial Value Register Low (XEIVRL) */ +#define XEIVRL_INIT_VAL_L_OFFS (0) +#define XEIVRL_INIT_VAL_L_MASK (0xFFFFFFFF << XEIVRL_INIT_VAL_L_OFFS) + +/* XOR Engine Initial Value Register High (XEIVRH) */ +#define XEIVRH_INIT_VAL_H_OFFS (0) +#define XEIVRH_INIT_VAL_H_MASK (0xFFFFFFFF << XEIVRH_INIT_VAL_H_OFFS) + +/* XOR Engine Debug Register (XEDBR) */ +#define XEDBR_PARITY_ERR_INSR_OFFS (0) +#define XEDBR_PARITY_ERR_INSR_MASK (1 << XEDBR_PARITY_ERR_INSR_OFFS) +#define XEDBR_XBAR_ERR_INSR_OFFS (1) +#define XEDBR_XBAR_ERR_INSR_MASK (1 << XEDBR_XBAR_ERR_INSR_OFFS) + + +#ifdef __cplusplus +} +#endif + +#endif /* __INCmvXorSpech */ diff --git a/board/mv_feroceon/mv_kw/bootstrap_def.h b/board/mv_feroceon/mv_kw/bootstrap_def.h new file mode 100644 index 0000000..cacd288 --- /dev/null +++ b/board/mv_feroceon/mv_kw/bootstrap_def.h @@ -0,0 +1,121 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef _INC_BOOTSTRAP__DEF_H +#define _INC_BOOTSTRAP__DEF_H + +#ifndef MV_ASMLANGUAGE + +typedef struct BHR_t +{ +// type name byte order + MV_U8 blockID; //0 + MV_U8 rsvd0; //1 + MV_U16 nandPageSize; //2-3 + MV_U32 blockSize; //4-7 + MV_U32 rsvd1; //8-11 + MV_U32 sourceAddr; //12-15 + MV_U32 destinationAddr; //16-19 + MV_U32 executionAddr; //20-23 + MV_U8 sataPioMode; //24 + MV_U8 rsvd3; //25 + MV_U16 ddrInitDelay; //26-27 + MV_U16 rsvd2; //28-29 + MV_U8 ext; //30 + MV_U8 checkSum; //31 +} BHR_t, * pBHR_t; + + +typedef struct ExtBHR_t +{ +// type name byte order + MV_U32 dramRegsOffs; //0-3 + MV_U32 rsrvd1; //4-7 + MV_U32 rsrvd2; //8-11 + MV_U32 rsrvd3; //12-15 + MV_U32 rsrvd4; //16-19 + MV_U32 rsrvd5; //20-23 + MV_U32 rsrvd6; //24-27 + MV_U16 rsrvd7; //28-29 + MV_U8 rsrvd8; //30 + MV_U8 checkSum; //31 +}ExtBHR_t, *pExtBHR_t; + +#define BOOTROM_SIZE (12 * 1024) +#define HEADER_SIZE 512 +#define BHR_HDR_SIZE 0x20 +#define EXT_HEADER_SIZE (HEADER_SIZE - BHR_HDR_SIZE) + +/* Boot Type - block ID */ +#define IBR_HDR_I2C_ID 0x4D +#define IBR_HDR_SPI_ID 0x5A +#define IBR_HDR_NAND_ID 0x8B +#define IBR_HDR_SATA_ID 0x78 +#define IBR_HDR_PEX_ID 0x9C +#define IBR_HDR_UART_ID 0x69 +#define IBR_DEF_ATTRIB 0x00 + +#endif /* MV_ASMLANGUAGE */ +#endif /* _INC_BOOTSTRAP_H */ + diff --git a/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvLib.c b/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvLib.c new file mode 100644 index 0000000..db906d7 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvLib.c @@ -0,0 +1,2666 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "cntmr/mvCntmr.h" +#include "gpp/mvGpp.h" +#include "twsi/mvTwsi.h" +#include "pex/mvPex.h" +#include "device/mvDevice.h" +#include "eth/gbe/mvEthRegs.h" +#include "eth-phy/mvEthPhy.h" + +/* defines */ +/* #define MV_DEBUG */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; + +#define CODE_IN_ROM MV_FALSE +#define CODE_IN_RAM MV_TRUE + +extern MV_BOARD_INFO* boardInfoTbl[]; +#if defined(CONFIG_BUFFALO_PLATFORM) + #define BOARD_INFO(boardId) boardInfoTbl[boardId - BUFFALO_BOARD_ID_BASE] +#else + #define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] +#endif + +/* Locals */ +static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +MV_U32 tClkRate = -1; + + +/******************************************************************************* +* mvBoardEnvInit - Init board +* +* DESCRIPTION: +* In this function the board environment take care of device bank +* initialization. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardEnvInit(MV_VOID) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); + return; + + } + /* Set NAND interface access parameters */ + MV_REG_WRITE(NAND_READ_PARAMS_REG, BOARD_INFO(boardId)->nandFlashReadParams); + MV_REG_WRITE(NAND_WRITE_PARAMS_REG, BOARD_INFO(boardId)->nandFlashWriteParams); + MV_REG_WRITE(NAND_CTRL_REG, BOARD_INFO(boardId)->nandFlashControl); + + /* Set GPP Out value */ + MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); + MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); + + /* set GPP polarity */ + mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); + mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); + + /* Workaround for Erratum FE-MISC-70*/ + if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) + { + BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; + BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; + } /*End of WA*/ + + /* Set GPP Out Enable*/ + mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); + mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); + + /* Nand CE */ + MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); +} + +/******************************************************************************* +* mvBoardModelGet - Get Board model +* +* DESCRIPTION: +* This function returns 16bit describing board model. +* Board model is constructed of one byte major and minor numbers in the +* following manner: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardModelGet(MV_VOID) +{ + return (mvBoardIdGet() >> 16); +} + +/******************************************************************************* +* mbBoardRevlGet - Get Board revision +* +* DESCRIPTION: +* This function returns a 32bit describing the board revision. +* Board revision is constructed of 4bytes. 2bytes describes major number +* and the other 2bytes describes minor munber. +* For example for board revision 3.4 the function will return +* 0x00030004. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardRevGet(MV_VOID) +{ + return (mvBoardIdGet() & 0xFFFF); +} + +/******************************************************************************* +* mvBoardNameGet - Get Board name +* +* DESCRIPTION: +* This function returns a string describing the board model and revision. +* String is extracted from board I2C EEPROM. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvBoardNameGet(char *pNameBuff) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsSPrintf (pNameBuff, "Board unknown.\n"); + return MV_ERROR; + + } + + mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); + + return MV_OK; +} + +/******************************************************************************* +* mvBoardIsPortInSgmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE +* For all other options. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in SGMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) +{ + MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; + + if(ethPortNum >= BOARD_ETH_PORT_NUM) + { + mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); + return MV_FALSE; + } + return ethPortSgmiiSupport[ethPortNum]; +} + +/******************************************************************************* +* mvBoardIsPortInGmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in GMII or MV_FALSE +* For all other options. +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in GMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInGmii(MV_VOID) +{ + MV_U32 devClassId, devClass = 0; + if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) + { + /* Get MPP module ID */ + devClassId = mvBoarModuleTypeGet(devClass); + if (MV_BOARD_MODULE_GMII_ID == devClassId) + return MV_TRUE; + } + else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) + return MV_TRUE; + + return MV_FALSE; +} +/******************************************************************************* +* mvBoardPhyAddrGet - Get the phy address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; +} + +/******************************************************************************* +* mvBoardMacSpeedGet - Get the Mac speed +* +* DESCRIPTION: +* This routine returns the Mac speed if pre define of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; +} + +/******************************************************************************* +* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication +* +* DESCRIPTION: +* This routine returns the IRQ number for the link status indication. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* the number of the IRQ for the link status indication, -1 if the port +* number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; +} + +/******************************************************************************* +* mvBoardSwitchPortGet - Get the mapping between the board connector and the +* Ethernet Switch port +* +* DESCRIPTION: +* This routine returns the matching Switch port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* boardPortNum - logical number of the connector on the board +* +* OUTPUT: +* None. +* +* RETURN: +* the matching Switch port, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); + return MV_ERROR; + } + if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) + { + mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; +} + +/******************************************************************************* +* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port +* +* DESCRIPTION: +* This routine returns the Switch CPU port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* the Switch CPU port, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; +} + +/******************************************************************************* +* mvBoardIsSwitchConnected - Get switch connection status +* DESCRIPTION: +* This routine returns port's connection status +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 1 - if ethPortNum is connected to switch, 0 otherwise +* +*******************************************************************************/ +MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); + return MV_ERROR; + } + + if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) + { + mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); + return MV_ERROR; + } + + if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) + return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); + else + return 0; +} +/******************************************************************************* +* mvBoardSmiScanModeGet - Get Switch SMI scan mode +* +* DESCRIPTION: +* This routine returns Switch SMI scan mode. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; +} +/******************************************************************************* +* mvBoardSpecInitGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, +* otherwise return MV_FALSE. +* +* +*******************************************************************************/ + +MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) +{ + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardTclkGet - Get the board Tclk (Controller clock) +* +* DESCRIPTION: +* This routine extract the controller core clock. +* This function uses the controller counters to make identification. +* Note: In order to avoid interference, make sure task context switch +* and interrupts will not occure during this function operation +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardTclkGet(MV_VOID) +{ + if(mvCtrlModelGet()==MV_6281_DEV_ID || mvCtrlModelGet()==MV_6282_DEV_ID) + { +#if defined(TCLK_AUTO_DETECT) + MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; + + tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); + tmpTClkRate &= MSAR_TCLCK_MASK; + + switch (tmpTClkRate) + { + case MSAR_TCLCK_166: + return MV_BOARD_TCLK_166MHZ; + break; + case MSAR_TCLCK_200: + return MV_BOARD_TCLK_200MHZ; + break; + } +#else + return MV_BOARD_TCLK_200MHZ; +#endif + } + + return MV_BOARD_TCLK_166MHZ; + +} +/******************************************************************************* +* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) +* +* DESCRIPTION: +* This routine extract the CPU bus clock. +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +static MV_U32 mvBoard6180SysClkGet(MV_VOID) +{ + MV_U32 sysClkRate=0; + MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; + + sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); + sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; + sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; + + sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; + + return sysClkRate; + +} + +MV_U32 mvBoardSysClkGet(MV_VOID) +{ +#ifdef SYSCLK_AUTO_DETECT + MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; + MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; + MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; + + if(mvCtrlModelGet() == MV_6180_DEV_ID || mvCtrlModelGet() == MV_6280_DEV_ID) + return mvBoard6180SysClkGet(); + + tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); + pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); + pClkRate = cpuCLK[pClkRate]; + + indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; + indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; + if(ddrRtio[indexDdrRtio][0] != 0) + sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); + else + sysClkRate = 0; + + return sysClkRate; +#else + return MV_BOARD_DEFAULT_SYSCLK; +#endif +} + + +/******************************************************************************* +* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number +* +* DESCRIPTION: +* Multi-ported PCI Express bridges that is implemented on the board +* collapse interrupts across multiple conventional PCI/PCI-X buses. +* A dual-headed PCI Express bridge would map (or "swizzle") the +* interrupts per the following table (in accordance with the respective +* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# +* signals from its two logical PCI/PCI-X bridges, collapse the +* INTA#-INTD# signals from any internal sources, and convert the +* signals to in-band PCI Express messages. 10 +* This function returns the upstream interrupt as it was converted by +* the bridge, according to board configuration and the following table: +* PCI dev num +* Interrupt pin 7, 8, 9 +* A -> A D C +* B -> B A D +* C -> C B A +* D -> D C B +* +* +* INPUT: +* devNum - PCI/PCIX device number. +* intPin - PCI Int pin +* +* OUTPUT: +* None. +* +* RETURN: +* Int pin connected to the Interrupt controller +* +*******************************************************************************/ +MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) +{ + MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); + + if (realIntPin == 0) return 4; + else return realIntPin; + +} + +/******************************************************************************* +* mvBoardDebugLedNumGet - Get number of debug Leds +* +* DESCRIPTION: +* INPUT: +* boardId +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) +{ + return BOARD_INFO(boardId)->activeLedsNumber; +} + +/******************************************************************************* +* mvBoardDebugLeg - Set the board debug Leds +* +* DESCRIPTION: turn on/off status leds. +* Note: assume MPP leds are part of group 0 only. +* +* INPUT: +* hexNum - Number to be displied in hex by Leds. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardDebugLed(MV_U32 hexNum) +{ + MV_U32 val = 0,totalMask, currentBitMask = 1,i; + MV_U32 boardId= mvBoardIdGet(); + + if (BOARD_INFO(boardId)->pLedGppPin == NULL) + return; + + totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; + hexNum &= totalMask; + totalMask = 0; + + for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) + { + if (hexNum & currentBitMask) + { + val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); + } + + totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); + + currentBitMask = (currentBitMask << 1); + } + + if (BOARD_INFO(boardId)->ledsPolarity) + { + mvGppValueSet(0, totalMask, val); + } + else + { + mvGppValueSet(0, totalMask, ~val); + } +} + + +/******************************************************************************* +* mvBoarGpioPinGet - mvBoarGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* class - MV_BOARD_GPP_CLASS enum. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) +{ + MV_U32 boardId, i; + MV_U32 indexFound = 0; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); + return MV_ERROR; + + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { + if (indexFound == index) + return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + else + indexFound++; + + } + + return MV_ERROR; +} + + +/******************************************************************************* +* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardRTCGpioPinGet(MV_VOID) +{ + return mvBoardGpioPinNumGet(BOARD_GPP_RTC, 0); +} + + +/******************************************************************************* +* mvBoardReset - mvBoardReset +* +* DESCRIPTION: +* Reset the board +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvBoardReset(MV_VOID) +{ + MV_32 resetPin; + + /* Get gpp reset pin if define */ + resetPin = mvBoardResetGpioPinGet(); + if (resetPin != MV_ERROR) + { + MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); + MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); + + } + else + { + /* No gpp reset pin was found, try to reset ussing + system reset out */ + MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); + MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); + } +} + +/******************************************************************************* +* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardResetGpioPinGet(MV_VOID) +{ + return mvBoardGpioPinNumGet(BOARD_GPP_RESET, 0); +} +/******************************************************************************* +* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet +* +* DESCRIPTION: +* used for hotswap detection +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardSDIOGpioPinGet(MV_VOID) +{ + return mvBoardGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); +} + +/******************************************************************************* +* mvBoardUSBVbusGpioPinGet - return Vbus input GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) +{ + return mvBoardGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); +} + +/******************************************************************************* +* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) +{ + return mvBoardGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); +} + + +/******************************************************************************* +* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins +* +* DESCRIPTION: +* This function returns a 32-bit mask of GPP pins that connected to +* interrupt generating sources on board. +* For example if UART channel A is hardwired to GPP pin 8 and +* UART channel B is hardwired to GPP pin 4 the fuinction will return +* the value 0x000000110 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* See description. The function return -1 if board is not identified. +* +*******************************************************************************/ +MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); + return MV_ERROR; + + } + + return BOARD_INFO(boardId)->intsGppMaskLow; +} +MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); + return MV_ERROR; + + } + + return BOARD_INFO(boardId)->intsGppMaskHigh; +} + + +/******************************************************************************* +* mvBoardMppGet - Get board dependent MPP register value +* +* DESCRIPTION: +* MPP settings are derived from board design. +* MPP group consist of 8 MPPs. An MPP group represent MPP +* control register. +* This function retrieves board dependend MPP register value. +* +* INPUT: +* mppGroupNum - MPP group number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit value describing MPP control register value. +* +*******************************************************************************/ +MV_32 mvBoardMppGet(MV_U32 mppGroupNum) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + return MV_ERROR; + + } + + return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; +} + + +/******************************************************************************* +* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MODULE_ID_CLASS devClassId; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U32 maxMppGrp = 1; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6282_DEV_ID: + maxMppGrp = MV_6282_MPP_MAX_MODULE; + break; + case MV_6280_DEV_ID: + maxMppGrp = MV_6280_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + /* Set SYS_RST_OUTn to GPIO level '1' */ + MV_REG_BIT_SET(GPP_DATA_OUT_REG(0),BIT6); + /* Set SYS_RST_OUTn to GPIO out */ + MV_REG_BIT_RESET(GPP_DATA_OUT_EN_REG(0),BIT6); + /* Set MPP6 from SYS_RST_OUTn to GPIO */ + MV_REG_BIT_RESET(MPP_CONTROL_REG0,BIT24); + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + /* If MPP group can be defined by the module connected to it */ + if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) + { + /* Get MPP module ID */ + devClassId = mvBoarModuleTypeGet(devClass); + if (MV_ERROR != devClassId) + { + switch(devClassId) + { + case MV_BOARD_MODULE_TDM_ID: + case MV_BOARD_MODULE_TDM_5CHAN_ID: + mppGroupType = MV_BOARD_TDM; + break; + case MV_BOARD_MODULE_AUDIO_ID: + mppGroupType = MV_BOARD_AUDIO; + break; + case MV_BOARD_MODULE_RGMII_ID: + mppGroupType = MV_BOARD_RGMII; + break; + case MV_BOARD_MODULE_GMII_ID: + mppGroupType = MV_BOARD_GMII; + break; + case MV_BOARD_MODULE_TS_ID: + mppGroupType = MV_BOARD_TS; + break; + case MV_BOARD_MODULE_MII_ID: + mppGroupType = MV_BOARD_MII; + break; + case MV_BOARD_MODULE_LCD_ID: + mppGroupType = MV_BOARD_LCD; + break; + default: + mppGroupType = MV_BOARD_OTHER; + break; + } + } + else + /* The module bay is empty */ + mppGroupType = MV_BOARD_OTHER; + + /* Update MPP group type */ + mvBoardMppGroupTypeSet(devClass, mppGroupType); + } + + + /* Update MPP output voltage for RGMII 1.8V. */ + if (mvBoardMppVoltageLevelGet(devClass) == MV_BOARD_1_8V) + MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,(MPP_1_8_RGMII_OUTPUT_DRIVE << MPP_RGMII_OUTPUT_DRIVE_OFFS(devClass))); + if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) + { + /* MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); */ + MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); + MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); + } + else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) + { + /* Assumption that only ETH1 can be MII when using modules on DB */ + MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); + } + } + + /* 25mSec delay to prevent glitch */ + mvOsDelay(25); + /* Set MPP6 back to SYS_RST_OUTn */ + MV_REG_BIT_SET(MPP_CONTROL_REG0,BIT24); + + /* Update MPP when module is LCD to override both group */ + devId = mvCtrlModelGet(); + mppGroupType = mvBoardMppGroupTypeGet(0); + if ((devId == MV_6282_DEV_ID) && (mppGroupType == MV_BOARD_LCD)) + { + /* LCD module include AUDIO intrface over NAND ctrl lines */ + MV_REG_BIT_SET(NAND_AUDIO_PIN_MUX, NAND_AUDIO_PIN_MUX_SELECT_AUDIO_MODE); + + /* Override MPP group 1 type to LCD to update all MPP for LCD */ + mvBoardMppGroupTypeSet(1, MV_BOARD_LCD); + } +} + + /******************************************************************************* +* mvBoardMppVoltageLevelGet +* +* DESCRIPTION: +* +* INPUT: +* mppGroupVoltageLevel - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_BOARD_MPP_VOLTAGE_LEVEL mvBoardMppVoltageLevelGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + return MV_ERROR; + + } + + if (mppGroupClass == MV_BOARD_MPP_GROUP_1) + return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1Voltage; + else + return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2Voltage; +} + +/******************************************************************************* +* mvBoardMppGroupTypeGet +* +* DESCRIPTION: +* +* INPUT: +* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + return MV_ERROR; + + } + + if (mppGroupClass == MV_BOARD_MPP_GROUP_1) + return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; + else + return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; +} + +/******************************************************************************* +* mvBoardMppGroupTypeSet +* +* DESCRIPTION: +* +* INPUT: +* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. +* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, + MV_BOARD_MPP_TYPE_CLASS mppGroupType) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + } + + if (mppGroupClass == MV_BOARD_MPP_GROUP_1) + BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; + else + BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; + +} + +/******************************************************************************* +* mvBoardMppMuxSet - Update MPP mux +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardMppMuxSet(MV_VOID) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U8 muxVal = 0xf; + MV_U32 maxMppGrp = 1; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6282_DEV_ID: + maxMppGrp = MV_6282_MPP_MAX_MODULE; + break; + case MV_6280_DEV_ID: + maxMppGrp = MV_6280_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + mppGroupType = mvBoardMppGroupTypeGet(devClass); + + switch(mppGroupType) + { + case MV_BOARD_TDM: + muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); + break; + case MV_BOARD_AUDIO: + muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ + break; + case MV_BOARD_TS: + muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); + break; + case MV_BOARD_LCD: + muxVal = 0x0; + break; + default: + muxVal |= (devClass ? 0xf : 0); + break; + } + } + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: twsi exp set\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); + twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 2; + twsiSlave.moreThen256 = MV_FALSE; + + + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + DB(mvOsPrintf("Board: twsi exp out val fail\n")); + return; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + /* Change twsi exp to output */ + twsiSlave.offset = 6; + muxVal = 0; + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + DB(mvOsPrintf("Board: twsi exp change to out fail\n")); + return; + } + DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); + +} + +/******************************************************************************* +* mvBoardTdmMppSet - set MPPs in TDM module +* +* DESCRIPTION: +* +* INPUT: type of second telephony device +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardTdmMppSet(MV_32 chType) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U8 muxVal = 1; + MV_U8 muxValMask = 1; + MV_U8 twsiVal; + MV_U32 maxMppGrp = 1; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + devId = mvCtrlModelGet(); + + switch(devId) + { + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6282_DEV_ID: + maxMppGrp = MV_6282_MPP_MAX_MODULE; + break; + case MV_6280_DEV_ID: + maxMppGrp = MV_6280_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + mppGroupType = mvBoardMppGroupTypeGet(devClass); + if(mppGroupType == MV_BOARD_TDM) + break; + } + + if(devClass == maxMppGrp) + return; /* TDM module not found */ + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: twsi exp set\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 3; + twsiSlave.moreThen256 = MV_FALSE; + + if(mvBoardIdGet() == RD_88F6281A_ID) + { + muxVal = 0xc; + muxValMask = 0xf3; + } + + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + muxVal = (twsiVal & muxValMask) | muxVal; + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + mvOsPrintf("Board(1): twsi exp out val fail\n"); + return; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + /* Change twsi exp to output */ + twsiSlave.offset = 7; + muxVal = 0xfe; + if(mvBoardIdGet() == RD_88F6281A_ID) + muxVal = 0xf3; + + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + muxVal = (twsiVal & muxVal); + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + mvOsPrintf("Board: twsi exp change to out fail\n"); + return; + } + DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); + /* reset the line to 0 */ + twsiSlave.offset = 3; + muxVal = 0; + muxValMask = 1; + + if(mvBoardIdGet() == RD_88F6281A_ID) + { + muxVal = 0x0; + muxValMask = 0xf3; + } + + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + muxVal = (twsiVal & muxValMask) | muxVal; + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + mvOsPrintf("Board(2): twsi exp out val fail\n"); + return; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + mvOsDelay(20); + + /* set the line to 1 */ + twsiSlave.offset = 3; + muxVal = 1; + muxValMask = 1; + + if(mvBoardIdGet() == RD_88F6281A_ID) + { + muxVal = 0xc; + muxValMask = 0xf3; + if(chType) /* FXS - issue reset properly */ + { + MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); + mvOsDelay(50); + MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); + } + else /* FXO - issue reset via TDM_CODEC_RST*/ + { + /* change MPP44 type to TDM_CODEC_RST(0x2) */ + MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); + } + } + + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + muxVal = (twsiVal & muxValMask) | muxVal; + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + mvOsPrintf("Board: twsi exp out val fail\n"); + return; + } + + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); +} + +/******************************************************************************* +* mvBoardTdmSpiModeGet - return SLIC/DAA connection +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_32 mvBoardTdmSpiModeGet(MV_VOID) +{ + switch(mvBoardIdGet()) + { + case RD_88F6281A_ID: + return DAISY_CHAIN_MODE; + case DB_88F6281A_BP_ID: + case RD_88F6192A_ID: + case DB_88F6192A_BP_ID: + case DB_88F6282A_BP_ID: + return DUAL_CHIP_SELECT_MODE; + default: + mvOsPrintf("%s: unknown boardId(0x%x)\n",__FUNCTION__, mvBoardIdGet()); + return DUAL_CHIP_SELECT_MODE; + } +} + +/******************************************************************************* +* mvBoardMppModuleTypePrint - print module detect +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardMppModuleTypePrint(MV_VOID) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U32 maxMppGrp = 1; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6282_DEV_ID: + maxMppGrp = MV_6282_MPP_MAX_MODULE; + break; + case MV_6280_DEV_ID: + maxMppGrp = MV_6280_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + mppGroupType = mvBoardMppGroupTypeGet(devClass); + + switch(mppGroupType) + { + case MV_BOARD_TDM: + if(devId != MV_6190_DEV_ID) + mvOsPrintf("Module %d is TDM\n", devClass); + break; + case MV_BOARD_AUDIO: + if(devId != MV_6190_DEV_ID) + mvOsPrintf("Module %d is AUDIO\n", devClass); + break; + case MV_BOARD_RGMII: + if(devId != MV_6190_DEV_ID) + mvOsPrintf("Module %d is RGMII\n", devClass); + break; + case MV_BOARD_GMII: + if(devId != MV_6190_DEV_ID) + mvOsPrintf("Module %d is GMII\n", devClass); + break; + case MV_BOARD_TS: + if(devId != MV_6190_DEV_ID) + mvOsPrintf("Module %d is TS\n", devClass); + break; + default: + break; + } + } +} + +/* Board devices API managments */ + +/******************************************************************************* +* mvBoardGetDeviceNumber - Get number of device of some type on the board +* +* DESCRIPTION: +* +* INPUT: +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* number of those devices else the function returns 0 +* +* +*******************************************************************************/ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex=0,devNum; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); + return 0xFFFFFFFF; + + } + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) + { + if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) + { + foundIndex++; + } + } + + return foundIndex; + +} + +/******************************************************************************* +* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Base address else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); + + } + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Bus width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return 8; + } + + return 0xFFFFFFFF; + +} + +/******************************************************************************* +* mvBoardGetDeviceWidth - Get dev width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + return devEntry->devWidth; + + return MV_ERROR; + +} + +/******************************************************************************* +* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* window size else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); + } + + return 0xFFFFFFFF; +} + + +/******************************************************************************* +* boardGetDevEntry - returns the entry pointer of a device on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +* +*******************************************************************************/ +static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex=0,devIndex; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("boardGetDevEntry: Board unknown.\n"); + return NULL; + + } + + for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) + { + /* TBR */ + /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) + continue;*/ + + if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) + { + if (foundIndex == devNum) + { + return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); + } + foundIndex++; + } + } + + /* device not found */ + return NULL; +} + +/* Get device CS number */ + +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + + } + + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + return devEntry->deviceCS; + + return 0xFFFFFFFF; + +} + +/******************************************************************************* +* mvBoardRtcTwsiAddrTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardRtcTwsiAddrTypeGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardRtcTwsiAddrGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardRtcTwsiAddrGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + return (0xFF); +} + +/******************************************************************************* +* mvBoardA2DTwsiAddrTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardA2DTwsiAddrTypeGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardA2DTwsiAddrGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardA2DTwsiAddrGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + return (0xFF); +} + +/******************************************************************************* +* mvBoardTwsiExpAddrTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) + { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + else + indexFound++; + } + + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardTwsiExpAddrGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) + { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + else + indexFound++; + } + + return (0xFF); +} + + +/******************************************************************************* +* mvBoardTwsiSatRAddrTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) + { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + else + indexFound++; + } + + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardTwsiSatRAddrGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) + { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + else + indexFound++; + } + + return (0xFF); +} + +/******************************************************************************* +* mvBoardNandWidthGet - +* +* DESCRIPTION: Get the width of the first NAND device in byte. +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: 1, 2, 4 or MV_ERROR +* +* +*******************************************************************************/ +/* */ +MV_32 mvBoardNandWidthGet(void) +{ + MV_U32 devNum; + MV_U32 devWidth; + MV_U32 boardId= mvBoardIdGet(); + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) + { + devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); + if (devWidth != MV_ERROR) + return (devWidth / 8); + } + + /* NAND wasn't found */ + return MV_ERROR; +} + +MV_U32 gBoardId = -1; + +/******************************************************************************* +* mvBoardIdGet - Get Board model +* +* DESCRIPTION: +* This function returns board ID. +* Board ID is 32bit word constructed of board model (16bit) and +* board revision (16bit) in the following way: 0xMMMMRRRR. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit board ID number, '-1' if board is undefined. +* +*******************************************************************************/ +#if defined(CONFIG_BUFFALO_PLATFORM) +#define BID_PIN_NUM 8 + +MV_U32 mvBoardIdGet(MV_VOID) +{ + MV_U32 mask_low = 0; + MV_U32 mask_high = 0; + MV_U32 gpp_low; + MV_U32 gpp_high; + int i; + int shift; + MV_U32 tmpBoardId = 0; + MV_32 *pin_num = NULL; + + if(gBoardId != -1) + return gBoardId; + + struct board_id_pin_tab { + MV_U16 model; + MV_32 pin_num[BID_PIN_NUM]; + } bipt[] = { + {MV_6281_DEV_ID, {45, 44, 35, 34, 29, 28, -1, -1}}, + {MV_6282_DEV_ID, {28, 29, 36, 37, 38, 39, -1, -1}}, + {MV_6192_DEV_ID, { 8, 9, 15, 16, 13, 23, 24, 25}}, + }; + + for (i=0; i<(sizeof(bipt)/sizeof(struct board_id_pin_tab)); i++) { + if (mvCtrlModelGet() == bipt[i].model) { + pin_num = bipt[i].pin_num; + } + } + + if (pin_num == NULL) { + gBoardId = BUFFALO_BOARD_ID_BASE; + return gBoardId; + } + + for (i=0; i= 0) + tmpBoardId |= (gpp_low & BIT(pin_num[i])) >> shift; + else + tmpBoardId |= (gpp_low & BIT(pin_num[i])) << -shift; + } + else if (32 <= pin_num[i] && pin_num[i] < 50) { + shift = pin_num[i] - 32 - i; + if (shift >= 0) + tmpBoardId |= (gpp_high & BIT(pin_num[i] - 32)) >> shift; + else + tmpBoardId |= (gpp_high & BIT(pin_num[i] - 32)) << -shift; + } + } + + tmpBoardId += BUFFALO_BOARD_ID_BASE; + + if (!(BUFFALO_BOARD_ID_BASE <= tmpBoardId && tmpBoardId < MV_MAX_BOARD_ID)) { + tmpBoardId = BUFFALO_BOARD_ID_BASE; // for avoid segmentation fault + } + + gBoardId = tmpBoardId; + return gBoardId; +} + +MV_BOOL bfIsPWR_or_PWRAUTO_SignalAsserted(void) +{ + if (mvBoardIdGet() == BF_MVLSQV_ID) { + return MV_TRUE; + } + else { + return (((bfGppInRegBitTest(BIT_PWR_SW)) || bfGppInRegBitTest(BIT_PWRAUTO_SW))); + } +} + +#else // !defined(CONFIG_BUFFALO_PLATFORM) +MV_U32 mvBoardIdGet(MV_VOID) +{ + MV_U32 tmpBoardId = -1; + + if(gBoardId == -1) + { + #if defined(DB_88F6281A) + tmpBoardId = DB_88F6281A_BP_ID; + #elif defined(DB_88F6282A) + tmpBoardId = DB_88F6282A_BP_ID; + #elif defined(DB_88F6280A) + tmpBoardId = DB_88F6280A_BP_ID; + #elif defined(RD_88F6281A) + tmpBoardId = RD_88F6281A_ID; + #elif defined(DB_88F6192A) + tmpBoardId = DB_88F6192A_BP_ID; + #elif defined(DB_88F6190A) + tmpBoardId = DB_88F6190A_BP_ID; + #elif defined(RD_88F6192A) + tmpBoardId = RD_88F6192A_ID; + #elif defined(RD_88F6190A) + tmpBoardId = RD_88F6190A_ID; + #elif defined(DB_88F6180A) + tmpBoardId = DB_88F6180A_BP_ID; + #elif defined(RD_88F6281A_PCAC) + tmpBoardId = RD_88F6281A_PCAC_ID; + #elif defined(RD_88F6281A_SHEEVA_PLUG) + tmpBoardId = SHEEVA_PLUG_ID; + #elif defined(DB_CUSTOMER) + tmpBoardId = DB_CUSTOMER_ID; + #endif + gBoardId = tmpBoardId; + } + + return gBoardId; +} +#endif // defined(CONFIG_BUFFALO_PLATFORM) + +/******************************************************************************* +* mvBoarModuleTypeGet - mvBoarModuleTypeGet +* +* DESCRIPTION: +* +* INPUT: +* group num - MV_BOARD_MPP_GROUP_CLASS enum +* +* OUTPUT: +* None. +* +* RETURN: +* module num - MV_BOARD_MODULE_CLASS enum +* +*******************************************************************************/ +MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + MV_U8 data; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: Read MPP module ID\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); + twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + + + if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) + { + DB(mvOsPrintf("Board: Read MPP module ID fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); + + return data; +} + +/******************************************************************************* +* mvBoarTwsiSatRGet - +* +* DESCRIPTION: +* +* INPUT: +* device num - one of three devices +* reg num - 0 or 1 +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + MV_U8 data; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: Read S@R device read\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); + twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); + twsiSlave.validOffset = MV_TRUE; + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + + if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) + { + DB(mvOsPrintf("Board: Read S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Read S@R succeded\n")); + + return data; +} + +/******************************************************************************* +* mvBoarTwsiSatRSet - +* +* DESCRIPTION: +* +* INPUT: +* devNum - one of three devices +* regNum - 0 or 1 +* regVal - value +* +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); + twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); + twsiSlave.validOffset = MV_TRUE; + DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ + twsiSlave.slaveAddr.type, regVal)); + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) + { + DB(mvOsPrintf("Board: Write S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Write S@R succeded\n")); + + return MV_OK; +} + +/******************************************************************************* +* mvBoardSlicGpioPinGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) +{ + MV_U32 boardId; + boardId = mvBoardIdGet(); + + switch (boardId) + { + case DB_88F6281A_BP_ID: + case DB_88F6282A_BP_ID: + case RD_88F6281A_ID: + default: + return MV_ERROR; + break; + + } +} + +/******************************************************************************* +* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A +* +* DESCRIPTION: +* +* INPUT: +* mode - MV_TRUE = on ; MV_FALSE = off +* +* OUTPUT: +* MV_STATUS - MV_OK , MV_ERROR. +* +* RETURN: +* +*******************************************************************************/ +#if !defined(CONFIG_BUFFALO_PLATFORM) +MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) +{ + + MV_U8 val = 1, twsiVal; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + if(mvBoardIdGet() != RD_88F6281A_ID) + return MV_ERROR; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: twsi exp set\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 3; + twsiSlave.moreThen256 = MV_FALSE; + if(mode == MV_TRUE) + val = 0x1; + else + val = 0; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xfe) | val; + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp out val fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + /* Change twsi exp to output */ + twsiSlave.offset = 7; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xfe); + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp change to out fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); + return MV_OK; +} +#endif + +/******************************************************************************* +* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A +* +* DESCRIPTION: +* +* INPUT: +* mode - MV_TRUE = on ; MV_FALSE = off +* +* OUTPUT: +* MV_STATUS - MV_OK , MV_ERROR. +* +* RETURN: +* +*******************************************************************************/ +#if !defined(CONFIG_BUFFALO_PLATFORM) +MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) +{ + + MV_U8 val = 1, twsiVal; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + if(mvBoardIdGet() != RD_88F6281A_ID) + return MV_ERROR; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: twsi exp set\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 3; + twsiSlave.moreThen256 = MV_FALSE; + if(mode == MV_TRUE) + val = 0x2; + else + val = 0; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xfd) | val; + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp out val fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + /* Change twsi exp to output */ + twsiSlave.offset = 7; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xfd); + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp change to out fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); + return MV_OK; +} +#endif + +/******************************************************************************* +* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A +* +* DESCRIPTION: +* +* INPUT: +* mode - MV_TRUE = on ; MV_FALSE = off +* +* OUTPUT: +* MV_STATUS - MV_OK , MV_ERROR. +* +* RETURN: +* +*******************************************************************************/ +#if !defined(CONFIG_BUFFALO_PLATFORM) +MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) +{ + + MV_U8 val = 1, twsiVal; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + if(mvBoardIdGet() != RD_88F6281A_ID) + return MV_ERROR; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: twsi exp set\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 3; + twsiSlave.moreThen256 = MV_FALSE; + if(mode == MV_TRUE) + val = 0x10; + else + val = 0; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xef) | val; + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp out val fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + /* Change twsi exp to output */ + twsiSlave.offset = 7; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xef); + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp change to out fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); + return MV_OK; +} +#endif + diff --git a/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvLib.h b/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvLib.h new file mode 100644 index 0000000..33a105e --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvLib.h @@ -0,0 +1,434 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvBoardEnvLibh +#define __INCmvBoardEnvLibh + +/* defines */ +/* The below constant macros defines the board I2C EEPROM data offsets */ + + + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "boardEnv/mvBoardEnvSpec.h" + + +/* DUART stuff for Tclk detection only */ +#define DUART_BAUD_RATE 115200 +#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ + +/* Voice devices assembly modes */ +#define DAISY_CHAIN_MODE 1 +#define DUAL_CHIP_SELECT_MODE 0 +#define INTERRUPT_TO_MPP 1 +#define INTERRUPT_TO_TDM 0 + + +#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS +#define BOARD_ETH_SWITCH_PORT_NUM 5 + +#define MV_BOARD_MAX_USB_IF 1 +#define MV_BOARD_MAX_MPP 7 +#define MV_BOARD_NAME_LEN 0x20 + +typedef struct _boardData +{ + MV_U32 magic; + MV_U16 boardId; + MV_U8 boardVer; + MV_U8 boardRev; + MV_U32 reserved1; + MV_U32 reserved2; + +}BOARD_DATA; + +typedef enum _devBoardMppGroupClass +{ + MV_BOARD_MPP_GROUP_1, + MV_BOARD_MPP_GROUP_2, + MV_BOARD_MAX_MPP_GROUP +}MV_BOARD_MPP_GROUP_CLASS; + +typedef enum _devBoardMppTypeClass +{ + MV_BOARD_AUTO, + MV_BOARD_TDM, + MV_BOARD_AUDIO, + MV_BOARD_RGMII, + MV_BOARD_GMII, + MV_BOARD_TS, + MV_BOARD_MII, + RSRVD0, + MV_BOARD_LCD, + MV_BOARD_OTHER +}MV_BOARD_MPP_TYPE_CLASS; + +typedef enum _devBoardMppVoltageLevelClass +{ + MV_BOARD_1_8V, + MV_BOARD_2_5V, + MV_BOARD_3_3V +}MV_BOARD_MPP_VOLTAGE_LEVEL; + +typedef enum _devBoardModuleIdClass +{ + MV_BOARD_MODULE_TDM_ID = 1, + MV_BOARD_MODULE_AUDIO_ID, + MV_BOARD_MODULE_RGMII_ID, + MV_BOARD_MODULE_GMII_ID, + MV_BOARD_MODULE_TS_ID, + MV_BOARD_MODULE_MII_ID, + MV_BOARD_MODULE_TDM_5CHAN_ID, + MV_BOARD_MODULE_LCD_ID = 9, + MV_BOARD_MODULE_OTHER_ID +}MV_BOARD_MODULE_ID_CLASS; + +typedef struct _boardMppTypeInfo +{ + MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; + MV_BOARD_MPP_VOLTAGE_LEVEL boardMppGroup1Voltage; + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; + MV_BOARD_MPP_VOLTAGE_LEVEL boardMppGroup2Voltage; +}MV_BOARD_MPP_TYPE_INFO; + + +typedef enum _devBoardClass +{ + BOARD_DEV_NOR_FLASH, + BOARD_DEV_NAND_FLASH, + BOARD_DEV_SEVEN_SEG, + BOARD_DEV_FPGA, + BOARD_DEV_SRAM, + BOARD_DEV_SPI_FLASH, + BOARD_DEV_OTHER, +}MV_BOARD_DEV_CLASS; + +typedef enum _devTwsiBoardClass +{ + BOARD_TWSI_RTC, + BOARD_DEV_TWSI_EXP, + BOARD_DEV_TWSI_SATR, + BOARD_TWSI_AUDIO_DEC, + BOARD_TWSI_OTHER +}MV_BOARD_TWSI_CLASS; + +typedef enum _devGppBoardClass +{ + BOARD_GPP_RTC, + BOARD_GPP_MV_SWITCH, + BOARD_GPP_USB_VBUS, + BOARD_GPP_USB_VBUS_EN, + BOARD_GPP_USB_OC, + BOARD_GPP_USB_HOST_DEVICE, + BOARD_GPP_REF_CLCK, + BOARD_GPP_VOIP_SLIC, + BOARD_GPP_LIFELINE, + BOARD_GPP_BUTTON, + BOARD_GPP_TS_BUTTON_C, + BOARD_GPP_TS_BUTTON_U, + BOARD_GPP_TS_BUTTON_D, + BOARD_GPP_TS_BUTTON_L, + BOARD_GPP_TS_BUTTON_R, + BOARD_GPP_POWER_BUTTON, + BOARD_GPP_RESTOR_BUTTON, + BOARD_GPP_WPS_BUTTON, + BOARD_GPP_HDD0_POWER, + BOARD_GPP_HDD1_POWER, + BOARD_GPP_FAN_POWER, + BOARD_GPP_RESET, + BOARD_GPP_POWER_ON_LED, + BOARD_GPP_HDD_POWER, + BOARD_GPP_SDIO_POWER, + BOARD_GPP_SDIO_DETECT, + BOARD_GPP_SDIO_WP, + BOARD_GPP_SWITCH_PHY_INT, + BOARD_GPP_TSU_DIRCTION, + BOARD_GPP_OTHER, +#if defined(CONFIG_BUFFALO_PLATFORM) + BOARD_GPP_BOARD_ID, + BOARD_GPP_FAN_LOW, + BOARD_GPP_FAN_HIGH, + BOARD_GPP_FAN_LOCK, + BOARD_GPP_FUNC_LED, + BOARD_GPP_ALARM_LED, + BOARD_GPP_INFO_LED, + BOARD_GPP_PWR_LED, + BOARD_GPP_FUNC_RED_LED, + BOARD_GPP_FUNC_SW, + BOARD_GPP_PWR_SW, + BOARD_GPP_PWRAUTO_SW, + BOARD_GPP_INIT_SW, + BOARD_GPP_UART_EN, + BOARD_GPP_HDD_ERR_LED, + BOARD_GPP_DAS_PWR_LED, +#endif +}MV_BOARD_GPP_CLASS; + + +typedef struct _devCsInfo +{ + MV_U8 deviceCS; + MV_U32 params; + MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ + MV_U8 devWidth; + +}MV_DEV_CS_INFO; + + +#define MV_BOARD_PHY_FORCE_10MB 0x0 +#define MV_BOARD_PHY_FORCE_100MB 0x1 +#define MV_BOARD_PHY_FORCE_1000MB 0x2 +#define MV_BOARD_PHY_SPEED_AUTO 0x3 + +typedef struct _boardSwitchInfo +{ + MV_32 linkStatusIrq; + MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; + MV_32 qdCpuPort; + MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ + MV_32 switchOnPort; + +}MV_BOARD_SWITCH_INFO; + +typedef struct _boardLedInfo +{ + MV_U8 activeLedsNumber; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + MV_U8* gppPinNum; /* Pointer to GPP values */ + +}MV_BOARD_LED_INFO; + +typedef struct _boardGppInfo +{ + MV_BOARD_GPP_CLASS devClass; + MV_U8 gppPinNum; + +}MV_BOARD_GPP_INFO; + + +typedef struct _boardTwsiInfo +{ + MV_BOARD_TWSI_CLASS devClass; + MV_U8 twsiDevAddr; + MV_U8 twsiDevAddrType; + +}MV_BOARD_TWSI_INFO; + + +typedef enum _boardMacSpeed +{ + BOARD_MAC_SPEED_10M, + BOARD_MAC_SPEED_100M, + BOARD_MAC_SPEED_1000M, + BOARD_MAC_SPEED_AUTO, + +}MV_BOARD_MAC_SPEED; + +typedef struct _boardMacInfo +{ + MV_BOARD_MAC_SPEED boardMacSpeed; + MV_U8 boardEthSmiAddr; + +}MV_BOARD_MAC_INFO; + +typedef struct _boardMppInfo +{ + MV_U32 mppGroup[MV_BOARD_MAX_MPP]; + +}MV_BOARD_MPP_INFO; + +typedef struct _boardInfo +{ + char boardName[MV_BOARD_NAME_LEN]; + MV_U8 numBoardMppTypeValue; + MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; + MV_U8 numBoardMppConfigValue; + MV_BOARD_MPP_INFO* pBoardMppConfigValue; + MV_U32 intsGppMaskLow; + MV_U32 intsGppMaskHigh; + MV_U8 numBoardDeviceIf; + MV_DEV_CS_INFO* pDevCsInfo; + MV_U8 numBoardTwsiDev; + MV_BOARD_TWSI_INFO* pBoardTwsiDev; + MV_U8 numBoardMacInfo; + MV_BOARD_MAC_INFO* pBoardMacInfo; + MV_U8 numBoardGppInfo; + MV_BOARD_GPP_INFO* pBoardGppInfo; + MV_U8 activeLedsNumber; + MV_U8* pLedGppPin; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + /* GPP values */ + MV_U32 gppOutEnValLow; + MV_U32 gppOutEnValHigh; + MV_U32 gppOutValLow; + MV_U32 gppOutValHigh; + MV_U32 gppPolarityValLow; + MV_U32 gppPolarityValHigh; + + /* Switch Configuration */ + MV_BOARD_SWITCH_INFO* pSwitchInfo; + MV_U32 nandFlashReadParams; + MV_U32 nandFlashWriteParams; + MV_U32 nandFlashControl; +}MV_BOARD_INFO; + + + +MV_VOID mvBoardEnvInit(MV_VOID); +MV_U32 mvBoardIdGet(MV_VOID); +MV_U16 mvBoardModelGet(MV_VOID); +MV_U16 mvBoardRevGet(MV_VOID); +MV_STATUS mvBoardNameGet(char *pNameBuff); +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); +MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); +MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); +MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); +MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); +MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); +MV_BOOL mvBoardIsPortInGmii(MV_VOID); +MV_U32 mvBoardTclkGet(MV_VOID); +MV_U32 mvBoardSysClkGet(MV_VOID); +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); +MV_VOID mvBoardDebugLed(MV_U32 hexNum); +MV_32 mvBoardMppGet(MV_U32 mppGroupNum); + +MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); +MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); + +MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); +MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); + +MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); +MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); +MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); +MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); +MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); +MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); +MV_BOARD_MPP_VOLTAGE_LEVEL mvBoardMppVoltageLevelGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); +MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, + MV_BOARD_MPP_TYPE_CLASS mppGroupType); +MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); +MV_VOID mvBoardMppMuxSet(MV_VOID); +MV_VOID mvBoardTdmMppSet(MV_32 chType); +MV_32 mvBoardTdmSpiModeGet(MV_VOID); + +MV_VOID mvBoardMppModuleTypePrint(MV_VOID); +MV_VOID mvBoardReset(MV_VOID); +MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); +MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); +MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); +/* Board devices API managments */ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +/* Gpio Pin Connections API */ +MV_32 mvBoardUSBVbusGpioPinGet(int devId); +MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); +MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); + +MV_32 mvBoardResetGpioPinGet(MV_VOID); +MV_32 mvBoardRTCGpioPinGet(MV_VOID); +MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); +MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); +MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); + +MV_32 mvBoardSDIOGpioPinGet(MV_VOID); +MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); +MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); + +MV_32 mvBoardNandWidthGet(void); +MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); +MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); + +#if defined (CONFIG_BUFFALO_PLATFORM) +#undef BIT +#define BIT(x) (1 << (x)) + +#define BIT_PWR_LED mvBoardGpioPinNumGet(BOARD_GPP_PWR_LED, 0) +#define BIT_INFO_LED mvBoardGpioPinNumGet(BOARD_GPP_INFO_LED, 0) +#define BIT_ALARM_LED mvBoardGpioPinNumGet(BOARD_GPP_ALARM_LED, 0) +#define BIT_FUNC_LED mvBoardGpioPinNumGet(BOARD_GPP_FUNC_LED, 0) +#define BIT_FUNC_RED_LED mvBoardGpioPinNumGet(BOARD_GPP_FUNC_RED_LED, 0) +#define BIT_FAN_LOW mvBoardGpioPinNumGet(BOARD_GPP_FAN_LOW, 0) +#define BIT_FAN_HIGH mvBoardGpioPinNumGet(BOARD_GPP_FAN_HIGH, 0) +#define BIT_FAN_LOCK mvBoardGpioPinNumGet(BOARD_GPP_FAN_LOCK, 0) +#define BIT_PWR_SW mvBoardGpioPinNumGet(BOARD_GPP_PWR_SW, 0) +#define BIT_PWRAUTO_SW mvBoardGpioPinNumGet(BOARD_GPP_PWRAUTO_SW, 0) +#define BIT_FUNC_SW mvBoardGpioPinNumGet(BOARD_GPP_FUNC_SW, 0) +#define BIT_INIT_SW mvBoardGpioPinNumGet(BOARD_GPP_INIT_SW, 0) +#define BIT_UART_EN mvBoardGpioPinNumGet(BOARD_GPP_UART_EN, 0) +#define BIT_HDD_ERROR0 mvBoardGpioPinNumGet(BOARD_GPP_HDD_ERR_LED, 0) +#define BIT_HDD_ERROR1 mvBoardGpioPinNumGet(BOARD_GPP_HDD_ERR_LED, 1) + +MV_BOOL bfIsPWR_or_PWRAUTO_SignalAsserted(void); + +#endif + +#endif /* __INCmvBoardEnvLibh */ diff --git a/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvSpec.c b/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvSpec.c new file mode 100644 index 0000000..35ffc9e --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvSpec.c @@ -0,0 +1,1791 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvCommon.h" +#include "mvBoardEnvLib.h" +#include "mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" + +#if !defined(CONFIG_BUFFALO_PLATFORM) +#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 +#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 +#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x1 +#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 +#else + #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif +#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88F6281A_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_88F6281A_BOARD_NAND_WRITE_PARAMS 0x00010305 +#define DB_88F6281A_BOARD_NAND_CONTROL 0x01c00541 + + +MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} + }; + +MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + { + {BOARD_MAC_SPEED_AUTO, 0x8}, + {BOARD_MAC_SPEED_AUTO, 0x9} + }; + +MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = + /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, + MV_BOARD_MPP_VOLTAGE_LEVEL boardMppGroup1Voltage, + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2, + MV_BOARD_MPP_VOLTAGE_LEVEL boardMppGroup2Voltage}} */ + {{MV_BOARD_AUTO, MV_BOARD_1_8V, MV_BOARD_AUTO, MV_BOARD_1_8V} + }; + +MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_TSU_DIRCTION, 33} + /*muxed with TDM/Audio module via IOexpender + {BOARD_GPP_SDIO_DETECT, 38}, + {BOARD_GPP_USB_VBUS, 49}*/ + }; + +MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = + {{{ + DB_88F6281A_MPP0_7, + DB_88F6281A_MPP8_15, + DB_88F6281A_MPP16_23, + DB_88F6281A_MPP24_31, + DB_88F6281A_MPP32_39, + DB_88F6281A_MPP40_47, + DB_88F6281A_MPP48_55 + }}}; + + +MV_BOARD_INFO db88f6281AInfo = { + "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + db88f6281AInfoBoardMppTypeInfo, + DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6281AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6281AInfoBoardDeCsInfo, + DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6281AInfoBoardTwsiDev, + DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6281AInfoBoardMacInfo, + DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f6281AInfoBoardGppInfo, + DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_88F6281A_OE_LOW, /* gppOutEnLow */ + DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ + DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ + DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + BIT6, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + DB_88F6281A_BOARD_NAND_READ_PARAMS, + DB_88F6281A_BOARD_NAND_WRITE_PARAMS, + DB_88F6281A_BOARD_NAND_CONTROL +}; + + +#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 +#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 +#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 +#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 +#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 +#else + #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif +#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 +#define RD_88F6281A_BOARD_NAND_READ_PARAMS 0x000C0282 +#define RD_88F6281A_BOARD_NAND_WRITE_PARAMS 0x00010305 +#define RD_88F6281A_BOARD_NAND_CONTROL 0x01c00541 + +MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_1000M, 0xa}, + {BOARD_MAC_SPEED_AUTO, 0xb} + }; + +MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = + /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, + MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ + {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, + {-1, {-1}, -1, -1, -1}}; + +MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ + {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} + }; + +MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = + {{MV_BOARD_RGMII, MV_BOARD_1_8V, MV_BOARD_TDM, MV_BOARD_3_3V} + }; + +MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_GPP_SDIO_DETECT, 28}, + {BOARD_GPP_USB_OC, 29}, + {BOARD_GPP_WPS_BUTTON, 35}, + {BOARD_GPP_MV_SWITCH, 38}, + {BOARD_GPP_USB_VBUS, 49} + }; + +MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = + {{{ + RD_88F6281A_MPP0_7, + RD_88F6281A_MPP8_15, + RD_88F6281A_MPP16_23, + RD_88F6281A_MPP24_31, + RD_88F6281A_MPP32_39, + RD_88F6281A_MPP40_47, + RD_88F6281A_MPP48_55 + }}}; + +MV_BOARD_INFO rd88f6281AInfo = { + "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + rd88f6281AInfoBoardMppTypeInfo, + RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6281AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6281AInfoBoardDeCsInfo, + RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f6281AInfoBoardTwsiDev, + RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6281AInfoBoardMacInfo, + RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f6281AInfoBoardGppInfo, + RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + RD_88F6281A_OE_LOW, /* gppOutEnLow */ + RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ + RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ + RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + BIT6, /* gppPolarityValHigh */ + rd88f6281AInfoBoardSwitchInfo, /* pSwitchInfo */ + RD_88F6281A_BOARD_NAND_READ_PARAMS, + RD_88F6281A_BOARD_NAND_WRITE_PARAMS, + RD_88F6281A_BOARD_NAND_CONTROL +}; + + +#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 +#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 +#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 +#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 +#else + #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif +#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88F6192A_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_88F6192A_BOARD_NAND_WRITE_PARAMS 0x00010305 +#define DB_88F6192A_BOARD_NAND_CONTROL 0x01c00541 + +MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} + }; + +MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + { + {BOARD_MAC_SPEED_AUTO, 0x8}, + {BOARD_MAC_SPEED_AUTO, 0x9} + }; + +MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = + {{MV_BOARD_AUTO, MV_BOARD_1_8V, MV_BOARD_OTHER, MV_BOARD_3_3V} + }; + +MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_SDIO_WP, 20}, + {BOARD_GPP_USB_VBUS, 22}, + {BOARD_GPP_SDIO_DETECT, 23}, + }; + +MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = + {{{ + DB_88F6192A_MPP0_7, + DB_88F6192A_MPP8_15, + DB_88F6192A_MPP16_23, + DB_88F6192A_MPP24_31, + DB_88F6192A_MPP32_35 + }}}; + +MV_BOARD_INFO db88f6192AInfo = { + "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + db88f6192AInfoBoardMppTypeInfo, + DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6192AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6192AInfoBoardDeCsInfo, + DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6192AInfoBoardTwsiDev, + DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6192AInfoBoardMacInfo, + DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f6192AInfoBoardGppInfo, + DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_88F6192A_OE_LOW, /* gppOutEnLow */ + DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ + DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ + DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + DB_88F6192A_BOARD_NAND_READ_PARAMS, + DB_88F6192A_BOARD_NAND_WRITE_PARAMS, + DB_88F6192A_BOARD_NAND_CONTROL +}; + +#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 + +MV_BOARD_INFO db88f6190AInfo = { + "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + db88f6192AInfoBoardMppTypeInfo, + DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6192AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6192AInfoBoardDeCsInfo, + DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6192AInfoBoardTwsiDev, + DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6192AInfoBoardMacInfo, + DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f6192AInfoBoardGppInfo, + DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_88F6192A_OE_LOW, /* gppOutEnLow */ + DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ + DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ + DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + DB_88F6192A_BOARD_NAND_READ_PARAMS, + DB_88F6192A_BOARD_NAND_WRITE_PARAMS, + DB_88F6192A_BOARD_NAND_CONTROL +}; + +#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 +#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 +#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE +#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 +#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 +#define RD_88F6192A_BOARD_NAND_READ_PARAMS 0x000C0282 +#define RD_88F6192A_BOARD_NAND_WRITE_PARAMS 0x00010305 +#define RD_88F6192A_BOARD_NAND_CONTROL 0x01c00541 + +MV_U8 rd88f6192AInfoBoardDebugLedIf[] = + {17, 28, 29}; + +MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8} + }; + +MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = + {{MV_BOARD_OTHER, MV_BOARD_1_8V, MV_BOARD_OTHER, MV_BOARD_3_3V} + }; + +MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ + +MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_USB_VBUS_EN, 10}, + {BOARD_GPP_USB_HOST_DEVICE, 11}, + {BOARD_GPP_RESET, 14}, + {BOARD_GPP_POWER_ON_LED, 15}, + {BOARD_GPP_HDD_POWER, 16}, + {BOARD_GPP_WPS_BUTTON, 24}, + {BOARD_GPP_TS_BUTTON_C, 25}, + {BOARD_GPP_USB_VBUS, 26}, + {BOARD_GPP_USB_OC, 27}, + {BOARD_GPP_TS_BUTTON_U, 30}, + {BOARD_GPP_TS_BUTTON_R, 31}, + {BOARD_GPP_TS_BUTTON_L, 32}, + {BOARD_GPP_TS_BUTTON_D, 34}, + {BOARD_GPP_FAN_POWER, 35} + }; + +MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = + {{{ + RD_88F6192A_MPP0_7, + RD_88F6192A_MPP8_15, + RD_88F6192A_MPP16_23, + RD_88F6192A_MPP24_31, + RD_88F6192A_MPP32_35 + }}}; + +MV_BOARD_INFO rd88f6192AInfo = { + "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + rd88f6192AInfoBoardMppTypeInfo, + RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6192AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6192AInfoBoardDeCsInfo, + RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, + RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6192AInfoBoardMacInfo, + RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f6192AInfoBoardGppInfo, + RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f6192AInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F6192A_OE_LOW, /* gppOutEnLow */ + RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ + RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ + RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + RD_88F6192A_BOARD_NAND_READ_PARAMS, + RD_88F6192A_BOARD_NAND_WRITE_PARAMS, + RD_88F6192A_BOARD_NAND_CONTROL +}; + +MV_BOARD_INFO rd88f6190AInfo = { + "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + rd88f6192AInfoBoardMppTypeInfo, + RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6192AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6192AInfoBoardDeCsInfo, + RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, + RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6192AInfoBoardMacInfo, + RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f6192AInfoBoardGppInfo, + RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f6192AInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F6192A_OE_LOW, /* gppOutEnLow */ + RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ + RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ + RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + RD_88F6192A_BOARD_NAND_READ_PARAMS, + RD_88F6192A_BOARD_NAND_WRITE_PARAMS, + RD_88F6192A_BOARD_NAND_CONTROL +}; + +#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 +#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 +#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 +#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 +#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88F6180A_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_88F6180A_BOARD_NAND_WRITE_PARAMS 0x00010305 +#define DB_88F6180A_BOARD_NAND_CONTROL 0x01c00541 + +MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} + }; + +MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8} + }; + +MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + /* Muxed with TDM/Audio module via IOexpender + {BOARD_GPP_USB_VBUS, 6} */ + }; + +MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = + {{MV_BOARD_OTHER, MV_BOARD_3_3V, MV_BOARD_AUTO, MV_BOARD_3_3V} + }; + +MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#else + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = + {{{ + DB_88F6180A_MPP0_7, + DB_88F6180A_MPP8_15, + DB_88F6180A_MPP16_23, + DB_88F6180A_MPP24_31, + DB_88F6180A_MPP32_39, + DB_88F6180A_MPP40_44 + }}}; + +MV_BOARD_INFO db88f6180AInfo = { + "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + db88f6180AInfoBoardMppTypeInfo, + DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6180AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6180AInfoBoardDeCsInfo, + DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6180AInfoBoardTwsiDev, + DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6180AInfoBoardMacInfo, + DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + NULL, + DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_88F6180A_OE_LOW, /* gppOutEnLow */ + DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ + DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ + DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + DB_88F6180A_BOARD_NAND_READ_PARAMS, + DB_88F6180A_BOARD_NAND_WRITE_PARAMS, + DB_88F6180A_BOARD_NAND_CONTROL +}; + + +#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 +#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 +#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 +#else + #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif +#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 +#define RD_88F6281A_PCAC_BOARD_NAND_READ_PARAMS 0x000C0282 +#define RD_88F6281A_PCAC_BOARD_NAND_WRITE_PARAMS 0x00010305 +#define RD_88F6281A_PCAC_BOARD_NAND_CONTROL 0x01c00541 + +MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = + {38, 39, 40, 41}; + +MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8} + }; + +MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} + }; + +MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = + {{MV_BOARD_OTHER, MV_BOARD_3_3V, MV_BOARD_OTHER, MV_BOARD_3_3V} + }; + +MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = + {{{ + RD_88F6281A_PCAC_MPP0_7, + RD_88F6281A_PCAC_MPP8_15, + RD_88F6281A_PCAC_MPP16_23, + RD_88F6281A_PCAC_MPP24_31, + RD_88F6281A_PCAC_MPP32_39, + RD_88F6281A_PCAC_MPP40_47, + RD_88F6281A_PCAC_MPP48_55 + }}}; + +MV_BOARD_INFO rd88f6281APcacInfo = { + "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + rd88f6281APcacInfoBoardMppTypeInfo, + RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6281APcacInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6281APcacInfoBoardDeCsInfo, + RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f6281APcacInfoBoardTwsiDev, + RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6281APcacInfoBoardMacInfo, + RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + 0, + RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ + RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ + RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ + RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + RD_88F6281A_PCAC_BOARD_NAND_READ_PARAMS, + RD_88F6281A_PCAC_BOARD_NAND_WRITE_PARAMS, + RD_88F6281A_PCAC_BOARD_NAND_CONTROL +}; + + +#define DB_88F6280A_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6280A_BOARD_TWSI_DEF_NUM 0x7 +#define DB_88F6280A_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F6280A_BOARD_GPP_INFO_NUM 0x0 +#define DB_88F6280A_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F6280A_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define DB_88F6280A_BOARD_DEVICE_CONFIG_NUM 0x1 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define DB_88F6280A_BOARD_DEVICE_CONFIG_NUM 0x2 +#else + #define DB_88F6280A_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif +#define DB_88F6280A_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88F6280A_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_88F6280A_BOARD_NAND_WRITE_PARAMS 0x00010305 +#define DB_88F6280A_BOARD_NAND_CONTROL 0x01c00541 + + +MV_BOARD_TWSI_INFO db88f6280AInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} + }; + +MV_BOARD_MAC_INFO db88f6280AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + { + {BOARD_MAC_SPEED_AUTO, 0x8} + }; + +MV_BOARD_MPP_TYPE_INFO db88f6280AInfoBoardMppTypeInfo[] = + {{MV_BOARD_AUTO, MV_BOARD_1_8V, MV_BOARD_OTHER, MV_BOARD_3_3V} + }; + +MV_DEV_CS_INFO db88f6280AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{0, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_MPP_INFO db88f6280AInfoBoardMppConfigValue[] = + {{{ + DB_88F6280A_MPP0_7, + DB_88F6280A_MPP8_15, + DB_88F6280A_MPP16_23, + DB_88F6280A_MPP24_31, + DB_88F6280A_MPP32_39, + DB_88F6280A_MPP40_47, + DB_88F6280A_MPP48_55 + }}}; + + +MV_BOARD_INFO db88f6280AInfo = { + "DB-88F6280A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6280A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + db88f6280AInfoBoardMppTypeInfo, + DB_88F6280A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6280AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + DB_88F6280A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6280AInfoBoardDeCsInfo, + DB_88F6280A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6280AInfoBoardTwsiDev, + DB_88F6280A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6280AInfoBoardMacInfo, + DB_88F6280A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + NULL, + DB_88F6280A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_88F6280A_OE_LOW, /* gppOutEnLow */ + DB_88F6280A_OE_HIGH, /* gppOutEnHigh */ + DB_88F6280A_OE_VAL_LOW, /* gppOutValLow */ + DB_88F6280A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + BIT6, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + DB_88F6280A_BOARD_NAND_READ_PARAMS, + DB_88F6280A_BOARD_NAND_WRITE_PARAMS, + DB_88F6280A_BOARD_NAND_CONTROL +}; + + +#define DB_88F6282A_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6282A_BOARD_TWSI_DEF_NUM 0x7 +#define DB_88F6282A_BOARD_MAC_INFO_NUM 0x2 +#define DB_88F6282A_BOARD_GPP_INFO_NUM 0x1 +#define DB_88F6282A_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F6282A_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define DB_88F6282A_BOARD_DEVICE_CONFIG_NUM 0x1 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define DB_88F6282A_BOARD_DEVICE_CONFIG_NUM 0x2 +#else + #define DB_88F6282A_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif +#define DB_88F6282A_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88F6282A_BOARD_NAND_READ_PARAMS 0x000C0282 +#define DB_88F6282A_BOARD_NAND_WRITE_PARAMS 0x00010305 +#define DB_88F6282A_BOARD_NAND_CONTROL 0x01c00541 + + +MV_BOARD_TWSI_INFO db88f6282AInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} + }; + +MV_BOARD_MAC_INFO db88f6282AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + { + {BOARD_MAC_SPEED_AUTO, 0x8}, + {BOARD_MAC_SPEED_AUTO, 0x9} + }; + +MV_BOARD_MPP_TYPE_INFO db88f6282AInfoBoardMppTypeInfo[] = + /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ + {{MV_BOARD_AUTO, MV_BOARD_AUTO} + }; + +MV_BOARD_GPP_INFO db88f6282AInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_TSU_DIRCTION, 33} + /*muxed with TDM/Audio module via IOexpender + {BOARD_GPP_SDIO_DETECT, 38}, + {BOARD_GPP_USB_VBUS, 49}*/ + }; + +MV_DEV_CS_INFO db88f6282AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_MPP_INFO db88f6282AInfoBoardMppConfigValue[] = + {{{ + DB_88F6282A_MPP0_7, + DB_88F6282A_MPP8_15, + DB_88F6282A_MPP16_23, + DB_88F6282A_MPP24_31, + DB_88F6282A_MPP32_39, + DB_88F6282A_MPP40_47, + DB_88F6282A_MPP48_55 + }}}; + + +MV_BOARD_INFO db88f6282AInfo = { + "DB-88F6282A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6282A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + db88f6282AInfoBoardMppTypeInfo, + DB_88F6282A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6282AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + DB_88F6282A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6282AInfoBoardDeCsInfo, + DB_88F6282A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6282AInfoBoardTwsiDev, + DB_88F6282A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6282AInfoBoardMacInfo, + DB_88F6282A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f6282AInfoBoardGppInfo, + DB_88F6282A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_88F6282A_OE_LOW, /* gppOutEnLow */ + DB_88F6282A_OE_HIGH, /* gppOutEnHigh */ + DB_88F6282A_OE_VAL_LOW, /* gppOutValLow */ + DB_88F6282A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + BIT6, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + DB_88F6282A_BOARD_NAND_READ_PARAMS, + DB_88F6282A_BOARD_NAND_WRITE_PARAMS, + DB_88F6282A_BOARD_NAND_CONTROL +}; + + +/* 6281 Sheeva Plug*/ + +#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 +#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 +#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 +#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 +#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 +#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 +#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 +#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 +#define SHEEVA_PLUG_BOARD_NAND_READ_PARAMS 0x000E02C2 +#define SHEEVA_PLUG_BOARD_NAND_WRITE_PARAMS 0x00010305 +#define SHEEVA_PLUG_BOARD_NAND_CONTROL 0x01c00541 + +MV_U8 sheevaPlugInfoBoardDebugLedIf[] = + {49}; + +MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x0}}; + +MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; + +MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = + {{MV_BOARD_OTHER, MV_BOARD_OTHER} + }; + +MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ + +MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = + {{{ + RD_SHEEVA_PLUG_MPP0_7, + RD_SHEEVA_PLUG_MPP8_15, + RD_SHEEVA_PLUG_MPP16_23, + RD_SHEEVA_PLUG_MPP24_31, + RD_SHEEVA_PLUG_MPP32_39, + RD_SHEEVA_PLUG_MPP40_47, + RD_SHEEVA_PLUG_MPP48_55 + }}}; + +MV_BOARD_INFO sheevaPlugInfo = { + "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ + SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ + sheevaPlugInfoBoardMppTypeInfo, + SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + sheevaPlugInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + sheevaPlugInfoBoardDeCsInfo, + SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + sheevaPlugInfoBoardTwsiDev, + SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + sheevaPlugInfoBoardMacInfo, + SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + 0, + SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + sheevaPlugInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ + RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ + RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ + RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + SHEEVA_PLUG_BOARD_NAND_READ_PARAMS, + SHEEVA_PLUG_BOARD_NAND_WRITE_PARAMS, + SHEEVA_PLUG_BOARD_NAND_CONTROL +}; + +/* Customer specific board place holder*/ + +#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 +#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 +#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 +#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 +#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 +#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 +#else + #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 +#endif +#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 +#define DB_CUSTOMER_BOARD_NAND_READ_PARAMS 0x000E02C2 +#define DB_CUSTOMER_BOARD_NAND_WRITE_PARAMS 0x00010305 +#define DB_CUSTOMER_BOARD_NAND_CONTROL 0x01c00541 + +MV_U8 dbCustomerInfoBoardDebugLedIf[] = + {0}; + +MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x0}}; + +MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; + +MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = + {{MV_BOARD_OTHER, MV_BOARD_1_8V, MV_BOARD_OTHER, MV_BOARD_1_8V} + }; + +MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = + {{{ + DB_CUSTOMER_MPP0_7, + DB_CUSTOMER_MPP8_15, + DB_CUSTOMER_MPP16_23, + DB_CUSTOMER_MPP24_31, + DB_CUSTOMER_MPP32_39, + DB_CUSTOMER_MPP40_47, + DB_CUSTOMER_MPP48_55 + }}}; + +MV_BOARD_INFO dbCustomerInfo = { + "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ + dbCustomerInfoBoardMppTypeInfo, + DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + dbCustomerInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + dbCustomerInfoBoardDeCsInfo, + DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + dbCustomerInfoBoardTwsiDev, + DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + dbCustomerInfoBoardMacInfo, + DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + 0, + DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ + DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ + DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ + DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + DB_CUSTOMER_BOARD_NAND_READ_PARAMS, + DB_CUSTOMER_BOARD_NAND_WRITE_PARAMS, + DB_CUSTOMER_BOARD_NAND_CONTROL +}; + +MV_BOARD_INFO* boardInfoTbl[] = { + &db88f6281AInfo, + &rd88f6281AInfo, + &db88f6192AInfo, + &rd88f6192AInfo, + &db88f6180AInfo, + &db88f6190AInfo, + &rd88f6190AInfo, + &rd88f6281APcacInfo, + &dbCustomerInfo, + &sheevaPlugInfo, + &db88f6280AInfo, + &db88f6282AInfo + }; + + +//////////////////////////////////////////////////////////////////////////////// + +#else // defined(CONFIG_BUFFALO_PLATFORM) + +/****************************** MVLSXH ******************************/ +MV_BOARD_MAC_INFO mvlsxhInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + { + {BOARD_MAC_SPEED_AUTO, 0x0}, + {BOARD_MAC_SPEED_AUTO, 0x8} + }; + +MV_BOARD_GPP_INFO mvlsxhInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_HDD_POWER, 10}, + {BOARD_GPP_USB_VBUS_EN, 11}, + {BOARD_GPP_FAN_LOW, 18}, + {BOARD_GPP_FAN_HIGH, 19}, + {BOARD_GPP_FUNC_LED, 36}, + {BOARD_GPP_ALARM_LED, 37}, + {BOARD_GPP_INFO_LED, 38}, + {BOARD_GPP_PWR_LED, 39}, + {BOARD_GPP_FAN_LOCK, 40}, + {BOARD_GPP_FUNC_SW, 41}, + {BOARD_GPP_PWR_SW, 42}, + {BOARD_GPP_PWRAUTO_SW, 43}, + {BOARD_GPP_FUNC_RED_LED, 48}, + {BOARD_GPP_UART_EN, 49}, + }; + +MV_BOARD_MPP_TYPE_INFO mvlsxhInfoBoardMppTypeInfo[] = + /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ + {{MV_BOARD_OTHER,MV_BOARD_RGMII} + }; + +MV_BOARD_MPP_INFO mvlsxhInfoBoardMppConfigValue[] = + {{{ + MVLSXH_MPP0_7, + MVLSXH_MPP8_15, + MVLSXH_MPP16_23, + MVLSXH_MPP24_31, + MVLSXH_MPP32_39, + MVLSXH_MPP40_47, + MVLSXH_MPP48_55 + }}}; + +MV_DEV_CS_INFO mvlsxhInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ + +#define MVLSXH_BOARD_PCI_IF_NUM 0x0 +#define MVLSXH_BOARD_TWSI_DEF_NUM 0x0 +#define MVLSXH_BOARD_MAC_INFO_NUM 0x2 +#define MVLSXH_BOARD_GPP_INFO_NUM (sizeof(mvlsxhInfoBoardGppInfo)/sizeof(MV_BOARD_GPP_INFO)) +#define MVLSXH_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define MVLSXH_BOARD_MPP_CONFIG_NUM 0x1 +#define MVLSXH_BOARD_DEVICE_CONFIG_NUM 0x1 +#define MVLSXH_BOARD_NAND_READ_PARAMS 0x003E07CF +#define MVLSXH_BOARD_NAND_WRITE_PARAMS 0x000F0F0F +#define MVLSXH_BOARD_NAND_CONTROL 0x01c7D943 + +MV_BOARD_INFO mvlsxhInfo = { + "MVLSXH", /* boardName[MAX_BOARD_NAME_LEN] */ + MVLSXH_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppTypeValue */ + mvlsxhInfoBoardMppTypeInfo, /* pBoardMppTypeValue */ + MVLSXH_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfigValue */ + mvlsxhInfoBoardMppConfigValue, /* pBoardMppConfigValue */ + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + MVLSXH_BOARD_DEVICE_CONFIG_NUM, /* numBoardDeviceIf */ + mvlsxhInfoBoardDeCsInfo, /* pDevCsInfo */ + MVLSXH_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, /* pBoardTwsiDev */ + MVLSXH_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + mvlsxhInfoBoardMacInfo, /* pBoardMacInfo */ + MVLSXH_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + mvlsxhInfoBoardGppInfo, /* pBoardGppInfo */ + 0, /* activeLedsNumber */ + NULL, /* pLedGppPin */ + 0, /* ledsPolarity */ + MVLSXH_OE_LOW, /* gppOutEnLow */ + MVLSXH_OE_HIGH, /* gppOutEnHigh */ + MVLSXH_OE_VAL_LOW, /* gppOutValLow */ + MVLSXH_OE_VAL_HIGH, /* gppOutValHigh */ + MVLSXH_POLARITY_VAL_LOW, /* gppPolarityValLow */ + MVLSXH_POLARITY_VAL_HIGH, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + MVLSXH_BOARD_NAND_READ_PARAMS, /* nandFlashReadParams */ + MVLSXH_BOARD_NAND_WRITE_PARAMS, /* nandFlashWriteParams */ + MVLSXH_BOARD_NAND_CONTROL, /* nandFlashControl */ +}; + +MV_BOARD_INFO mvlsxlInfo = { + "MVLSXL", /* boardName[MAX_BOARD_NAME_LEN] */ + MVLSXH_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppTypeValue */ + mvlsxhInfoBoardMppTypeInfo, /* pBoardMppTypeValue */ + MVLSXH_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfigValue */ + mvlsxhInfoBoardMppConfigValue, /* pBoardMppConfigValue */ + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + MVLSXH_BOARD_DEVICE_CONFIG_NUM, /* numBoardDeviceIf */ + mvlsxhInfoBoardDeCsInfo, /* pDevCsInfo */ + MVLSXH_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, /* pBoardTwsiDev */ + MVLSXH_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + mvlsxhInfoBoardMacInfo, /* pBoardMacInfo */ + MVLSXH_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + mvlsxhInfoBoardGppInfo, /* pBoardGppInfo */ + 0, /* activeLedsNumber */ + NULL, /* pLedGppPin */ + 0, /* ledsPolarity */ + MVLSXH_OE_LOW, /* gppOutEnLow */ + MVLSXH_OE_HIGH, /* gppOutEnHigh */ + MVLSXH_OE_VAL_LOW, /* gppOutValLow */ + MVLSXH_OE_VAL_HIGH, /* gppOutValHigh */ + MVLSXH_POLARITY_VAL_LOW, /* gppPolarityValLow */ + MVLSXH_POLARITY_VAL_HIGH, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + MVLSXH_BOARD_NAND_READ_PARAMS, /* nandFlashReadParams */ + MVLSXH_BOARD_NAND_WRITE_PARAMS, /* nandFlashWriteParams */ + MVLSXH_BOARD_NAND_CONTROL, /* nandFlashControl */ +}; + +/****************************** LS-XL-V2 ******************************/ +MV_BOARD_MAC_INFO mvlsxlGeV2InfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + { + {BOARD_MAC_SPEED_AUTO, 0x0}, + }; + +MV_BOARD_GPP_INFO mvlsxlGeV2InfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_PWR_LED, 17}, + {BOARD_GPP_HDD_POWER, 14}, + {BOARD_GPP_ALARM_LED, 26}, + {BOARD_GPP_INFO_LED, 27}, + }; + +MV_BOARD_MPP_INFO mvlsxlGeV2InfoBoardMppConfigValue[] = + {{{ + MVLSXL_GE_V2_MPP0_7, + MVLSXL_GE_V2_MPP8_15, + MVLSXL_GE_V2_MPP16_23, + MVLSXL_GE_V2_MPP24_31, + MVLSXL_GE_V2_MPP32_35 + }}}; + +MV_DEV_CS_INFO mvlsxlGeV2InfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; + +#define MVLSXL_GE_V2_BOARD_PCI_IF_NUM 0x0 +#define MVLSXL_GE_V2_BOARD_TWSI_DEF_NUM 0x0 +#define MVLSXL_GE_V2_BOARD_MAC_INFO_NUM 0x1 +#define MVLSXL_GE_V2_BOARD_GPP_INFO_NUM (sizeof(mvlsxlGeV2InfoBoardGppInfo)/sizeof(MV_BOARD_GPP_INFO)) +#define MVLSXL_GE_V2_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define MVLSXL_GE_V2_BOARD_MPP_CONFIG_NUM 0x1 +#define MVLSXL_GE_V2_BOARD_DEVICE_CONFIG_NUM 0x2 +#define MVLSXL_GE_V2_BOARD_NAND_READ_PARAMS 0x003E07CF +#define MVLSXL_GE_V2_BOARD_NAND_WRITE_PARAMS 0x000F0F0F +#define MVLSXL_GE_V2_BOARD_NAND_CONTROL 0x01c7D943 + +MV_BOARD_MPP_TYPE_INFO mvlsxlv2InfoBoardMppTypeInfo[] = + {{MV_BOARD_AUTO, MV_BOARD_1_8V, MV_BOARD_OTHER, MV_BOARD_3_3V} + }; + +MV_BOARD_INFO mvlsxlGeV2Info = { + "MVLSXL-GE-V2", /* boardName[MAX_BOARD_NAME_LEN] */ + MVLSXH_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppTypeValue */ + mvlsxlv2InfoBoardMppTypeInfo, /* pBoardMppTypeValue */ + /* mvlsxhInfoBoardMppTypeInfo, */ /* pBoardMppTypeValue */ + MVLSXL_GE_V2_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfigValue */ + mvlsxlGeV2InfoBoardMppConfigValue, /* pBoardMppConfigValue */ + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + MVLSXL_GE_V2_BOARD_DEVICE_CONFIG_NUM, /* numBoardDeviceIf */ + mvlsxlGeV2InfoBoardDeCsInfo, /* pDevCsInfo */ + MVLSXH_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, /* pBoardTwsiDev */ + MVLSXL_GE_V2_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + mvlsxlGeV2InfoBoardMacInfo, /* pBoardMacInfo */ + MVLSXL_GE_V2_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + mvlsxlGeV2InfoBoardGppInfo, /* pBoardGppInfo */ + 0, /* activeLedsNumber */ + NULL, /* pLedGppPin */ + 0, /* ledsPolarity */ + MVLSXL_GE_V2_OE_LOW, /* gppOutEnLow */ + MVLSXL_GE_V2_OE_HIGH, /* gppOutEnHigh */ + MVLSXL_GE_V2_OE_VAL_LOW, /* gppOutValLow */ + MVLSXL_GE_V2_OE_VAL_HIGH, /* gppOutValHigh */ + MVLSXL_GE_V2_POLARITY_VAL_LOW, /* gppPolarityValLow */ + MVLSXL_GE_V2_POLARITY_VAL_HIGH, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + MVLSXL_GE_V2_BOARD_NAND_READ_PARAMS, /* nandFlashReadParams */ + MVLSXL_GE_V2_BOARD_NAND_WRITE_PARAMS, /* nandFlashWriteParams */ + MVLSXL_GE_V2_BOARD_NAND_CONTROL, /* nandFlashControl */ +}; + +/****************************** LS-WXL ******************************/ +MV_BOARD_GPP_INFO mvwxlInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_HDD_ERR_LED, 8}, + {BOARD_GPP_HDD_POWER, 28}, + {BOARD_GPP_HDD_POWER, 29}, + {BOARD_GPP_FUNC_RED_LED,34}, + {BOARD_GPP_FUNC_LED, 36}, + {BOARD_GPP_USB_VBUS_EN, 37}, + {BOARD_GPP_INFO_LED, 38}, + {BOARD_GPP_PWR_LED, 39}, + {BOARD_GPP_FAN_LOCK, 40}, + {BOARD_GPP_FUNC_SW, 41}, + {BOARD_GPP_PWR_SW, 42}, + {BOARD_GPP_PWRAUTO_SW, 43}, + {BOARD_GPP_HDD_ERR_LED, 46}, + {BOARD_GPP_FAN_LOW, 47}, + {BOARD_GPP_FAN_HIGH, 48}, + {BOARD_GPP_ALARM_LED, 49}, + {BOARD_GPP_UART_EN, 49}, + }; + +MV_BOARD_MPP_INFO mvwxlInfoBoardMppConfigValue[] = + {{{ + MVWXL_MPP0_7, + MVWXL_MPP8_15, + MVWXL_MPP16_23, + MVWXL_MPP24_31, + MVWXL_MPP32_39, + MVWXL_MPP40_47, + MVWXL_MPP48_55 + }}}; + +MV_DEV_CS_INFO mvwxlInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + { +#if defined(MV_NAND) + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ +#endif +#if defined(MV_SPI) + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ +#endif + }; + + +#define MVWXL_BOARD_PCI_IF_NUM 0x0 +#define MVWXL_BOARD_TWSI_DEF_NUM 0x0 +#define MVWXL_BOARD_MAC_INFO_NUM 0x2 +#define MVWXL_BOARD_GPP_INFO_NUM (sizeof(mvwxlInfoBoardGppInfo)/sizeof(MV_BOARD_GPP_INFO)) +#define MVWXL_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define MVWXL_BOARD_MPP_CONFIG_NUM 0x1 +#define MVWXL_BOARD_DEVICE_CONFIG_NUM (sizeof(mvwxlInfoBoardDeCsInfo)/sizeof(MV_DEV_CS_INFO)) +#define MVWXL_BOARD_NAND_READ_PARAMS 0x003E07CF +//#define MVWXL_BOARD_NAND_READ_PARAMS 0x000C0282 +#define MVWXL_BOARD_NAND_WRITE_PARAMS 0x000F0F0F +//#define MVWXL_BOARD_NAND_WRITE_PARAMS 0x00010305 +#define MVWXL_BOARD_NAND_CONTROL 0x01c7D943 +//#define MVWXL_BOARD_NAND_CONTROL 0x01c00541 + +MV_BOARD_INFO mvwxlInfo = { + "MVWXL", /* boardName[MAX_BOARD_NAME_LEN] */ + MVWXL_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppTypeValue */ + mvlsxhInfoBoardMppTypeInfo, /* pBoardMppTypeValue */ + MVWXL_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfigValue */ + mvwxlInfoBoardMppConfigValue, /* pBoardMppConfigValue */ + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + MVWXL_BOARD_DEVICE_CONFIG_NUM, /* numBoardDeviceIf */ + mvwxlInfoBoardDeCsInfo, /* pDevCsInfo */ + MVWXL_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, /* pBoardTwsiDev */ + MVWXL_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + mvlsxhInfoBoardMacInfo, /* pBoardMacInfo */ + MVWXL_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + mvwxlInfoBoardGppInfo, /* pBoardGppInfo */ + 0, /* activeLedsNumber */ + NULL, /* pLedGppPin */ + 0, /* ledsPolarity */ + MVWXL_OE_LOW, /* gppOutEnLow */ + MVWXL_OE_HIGH, /* gppOutEnHigh */ + MVWXL_OE_VAL_LOW, /* gppOutValLow */ + MVWXL_OE_VAL_HIGH, /* gppOutValHigh */ + MVWXL_POLARITY_VAL_LOW, /* gppPolarityValLow */ + MVWXL_POLARITY_VAL_HIGH, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + MVWXL_BOARD_NAND_READ_PARAMS, /* nandFlashReadParams */ + MVWXL_BOARD_NAND_WRITE_PARAMS, /* nandFlashWriteParams */ + MVWXL_BOARD_NAND_CONTROL, /* nandFlashControl */ +}; + +/****************************** LS-WSX ******************************/ +MV_BOARD_GPP_INFO mvwssxInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_HDD_POWER, 28}, + {BOARD_GPP_HDD_POWER, 35}, + {BOARD_GPP_FUNC_RED_LED, 34}, + {BOARD_GPP_FUNC_LED, 36}, + {BOARD_GPP_USB_VBUS_EN, 37}, + {BOARD_GPP_INFO_LED, 38}, + {BOARD_GPP_PWR_LED, 39}, + {BOARD_GPP_FAN_LOCK, 40}, + {BOARD_GPP_FUNC_SW, 41}, + {BOARD_GPP_PWR_SW, 42}, + {BOARD_GPP_PWRAUTO_SW, 43}, + {BOARD_GPP_DAS_PWR_LED, 46}, + {BOARD_GPP_USB_HOST_DEVICE, 47}, + {BOARD_GPP_ALARM_LED, 49}, + {BOARD_GPP_UART_EN, 49}, + }; + +MV_BOARD_MPP_INFO mvwssxInfoBoardMppConfigValue[] = + {{{ + MVWSSX_MPP0_7, + MVWSSX_MPP8_15, + MVWSSX_MPP16_23, + MVWSSX_MPP24_31, + MVWSSX_MPP32_39, + MVWSSX_MPP40_47, + MVWSSX_MPP48_55 + }}}; + +MV_DEV_CS_INFO mvwssxInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; + + +#define MVWSSX_BOARD_PCI_IF_NUM 0x0 +#define MVWSSX_BOARD_TWSI_DEF_NUM 0x0 +#define MVWSSX_BOARD_MAC_INFO_NUM 0x2 +#define MVWSSX_BOARD_GPP_INFO_NUM (sizeof(mvwssxInfoBoardGppInfo)/sizeof(MV_BOARD_GPP_INFO)) +#define MVWSSX_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define MVWSSX_BOARD_MPP_CONFIG_NUM 0x1 +#define MVWSSX_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_BOARD_INFO mvwssxInfo = { + "MVWSSX", /* boardName[MAX_BOARD_NAME_LEN] */ + MVWSSX_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppTypeValue */ + mvlsxhInfoBoardMppTypeInfo, /* pBoardMppTypeValue */ + MVWSSX_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfigValue */ + mvwssxInfoBoardMppConfigValue, /* pBoardMppConfigValue */ + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + MVWSSX_BOARD_DEVICE_CONFIG_NUM, /* numBoardDeviceIf */ + mvwssxInfoBoardDeCsInfo, /* pDevCsInfo */ + MVWSSX_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, /* pBoardTwsiDev */ + MVWSSX_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + mvlsxhInfoBoardMacInfo, /* pBoardMacInfo */ + MVWSSX_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + mvwssxInfoBoardGppInfo, /* pBoardGppInfo */ + 0, /* activeLedsNumber */ + NULL, /* pLedGppPin */ + 0, /* ledsPolarity */ + MVWSSX_OE_LOW, /* gppOutEnLow */ + MVWSSX_OE_HIGH, /* gppOutEnHigh */ + MVWSSX_OE_VAL_LOW, /* gppOutValLow */ + MVWSSX_OE_VAL_HIGH, /* gppOutValHigh */ + MVWSSX_POLARITY_VAL_LOW, /* gppPolarityValLow */ + MVWSSX_POLARITY_VAL_HIGH, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + MVWXL_BOARD_NAND_READ_PARAMS, /* nandFlashReadParams */ + MVWXL_BOARD_NAND_WRITE_PARAMS, /* nandFlashWriteParams */ + MVWXL_BOARD_NAND_CONTROL, /* nandFlashControl */ +}; + +/****************************** MVLSVL ******************************/ +MV_BOARD_MAC_INFO mvlsvlInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + { + {BOARD_MAC_SPEED_AUTO, 0x0} + }; + +MV_BOARD_GPP_INFO mvlsvlInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_HDD_POWER, 8}, + {BOARD_GPP_USB_VBUS_EN, 12}, + {BOARD_GPP_FAN_LOW, 16}, + {BOARD_GPP_FAN_HIGH, 17}, + {BOARD_GPP_FUNC_LED, 39}, + {BOARD_GPP_ALARM_LED, 36}, + {BOARD_GPP_INFO_LED, 38}, + {BOARD_GPP_PWR_LED, 40}, + {BOARD_GPP_FAN_LOCK, 43}, + {BOARD_GPP_FUNC_SW, 45}, + {BOARD_GPP_PWR_SW, 46}, + {BOARD_GPP_PWRAUTO_SW, 47}, + {BOARD_GPP_FUNC_RED_LED, 37}, + {BOARD_GPP_UART_EN, 48}, + }; + +MV_BOARD_MPP_TYPE_INFO mvlsvlInfoBoardMppTypeInfo[] = + /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ + { + {MV_BOARD_OTHER, MV_BOARD_OTHER} + //{MV_BOARD_OTHER,MV_BOARD_RGMII} + }; + +MV_BOARD_MPP_INFO mvlsvlInfoBoardMppConfigValue[] = + {{{ + MVLSVL_MPP0_7, + MVLSVL_MPP8_15, + MVLSVL_MPP16_23, + MVLSVL_MPP24_31, + MVLSVL_MPP32_39, + MVLSVL_MPP40_47, + MVLSVL_MPP48_55 + }}}; + +MV_DEV_CS_INFO mvlsvlInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ + +#define MVLSVL_BOARD_PCI_IF_NUM 0x0 +#define MVLSVL_BOARD_TWSI_DEF_NUM 0x0 +#define MVLSVL_BOARD_MAC_INFO_NUM 0x1 +#define MVLSVL_BOARD_GPP_INFO_NUM (sizeof(mvlsvlInfoBoardGppInfo)/sizeof(MV_BOARD_GPP_INFO)) +#define MVLSVL_BOARD_MPP_GROUP_TYPE_NUM 0x0 +#define MVLSVL_BOARD_MPP_CONFIG_NUM 0x1 +#define MVLSVL_BOARD_DEVICE_CONFIG_NUM 0x1 +#define MVLSVL_BOARD_NAND_READ_PARAMS 0x003E07CF +#define MVLSVL_BOARD_NAND_WRITE_PARAMS 0x000F0F0F +#define MVLSVL_BOARD_NAND_CONTROL 0x01c7D943 + +MV_BOARD_INFO mvlsvlInfo = { + "MVLSVL", /* boardName[MAX_BOARD_NAME_LEN] */ + MVLSVL_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppTypeValue */ + mvlsvlInfoBoardMppTypeInfo, /* pBoardMppTypeValue */ + MVLSVL_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfigValue */ + mvlsvlInfoBoardMppConfigValue, /* pBoardMppConfigValue */ + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + MVLSVL_BOARD_DEVICE_CONFIG_NUM, /* numBoardDeviceIf */ + mvlsxhInfoBoardDeCsInfo, /* pDevCsInfo */ + MVLSVL_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, /* pBoardTwsiDev */ + MVLSVL_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + mvlsvlInfoBoardMacInfo, /* pBoardMacInfo */ + MVLSVL_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + mvlsvlInfoBoardGppInfo, /* pBoardGppInfo */ + 0, /* activeLedsNumber */ + NULL, /* pLedGppPin */ + 0, /* ledsPolarity */ + MVLSVL_OE_LOW, /* gppOutEnLow */ + MVLSVL_OE_HIGH, /* gppOutEnHigh */ + MVLSVL_OE_VAL_LOW, /* gppOutValLow */ + MVLSVL_OE_VAL_HIGH, /* gppOutValHigh */ + MVLSVL_POLARITY_VAL_LOW, /* gppPolarityValLow */ + MVLSVL_POLARITY_VAL_HIGH, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + MVLSVL_BOARD_NAND_READ_PARAMS, /* nandFlashReadParams */ + MVLSVL_BOARD_NAND_WRITE_PARAMS, /* nandFlashWriteParams */ + MVLSVL_BOARD_NAND_CONTROL, /* nandFlashControl */ +}; + +/****************************** MVLSWV ******************************/ +MV_BOARD_MAC_INFO mvlswvInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + { + {BOARD_MAC_SPEED_AUTO, 0x0} + }; + +MV_BOARD_GPP_INFO mvlswvInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_HDD_POWER, 8}, + {BOARD_GPP_HDD_POWER, 9}, + {BOARD_GPP_USB_VBUS_EN, 12}, + {BOARD_GPP_FAN_LOW, 16}, + {BOARD_GPP_FAN_HIGH, 17}, + {BOARD_GPP_FUNC_LED, 39}, + {BOARD_GPP_ALARM_LED, 36}, + {BOARD_GPP_INFO_LED, 38}, + {BOARD_GPP_PWR_LED, 40}, + {BOARD_GPP_FAN_LOCK, 43}, + {BOARD_GPP_FUNC_SW, 45}, + {BOARD_GPP_PWR_SW, 46}, + {BOARD_GPP_PWRAUTO_SW, 47}, + {BOARD_GPP_FUNC_RED_LED, 37}, + {BOARD_GPP_UART_EN, 48}, + }; + +MV_BOARD_MPP_TYPE_INFO mvlswvInfoBoardMppTypeInfo[] = + /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ + { + {MV_BOARD_OTHER, MV_BOARD_OTHER} + //{MV_BOARD_OTHER,MV_BOARD_RGMII} + }; + +MV_BOARD_MPP_INFO mvlswvInfoBoardMppConfigValue[] = + {{{ + MVLSWV_MPP0_7, + MVLSWV_MPP8_15, + MVLSWV_MPP16_23, + MVLSWV_MPP24_31, + MVLSWV_MPP32_39, + MVLSWV_MPP40_47, + MVLSWV_MPP48_55 + }}}; + +MV_DEV_CS_INFO mvlswvInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8} /* SPI DEV */ + }; + +#define MVLSWV_BOARD_PCI_IF_NUM 0x0 +#define MVLSWV_BOARD_TWSI_DEF_NUM 0x0 +#define MVLSWV_BOARD_MAC_INFO_NUM 0x1 +#define MVLSWV_BOARD_GPP_INFO_NUM (sizeof(mvlswvInfoBoardGppInfo)/sizeof(MV_BOARD_GPP_INFO)) +#define MVLSWV_BOARD_MPP_GROUP_TYPE_NUM 0x0 +#define MVLSWV_BOARD_MPP_CONFIG_NUM 0x1 +#define MVLSWV_BOARD_DEVICE_CONFIG_NUM 0x2 +#define MVLSWV_BOARD_NAND_READ_PARAMS 0x003E07CF +#define MVLSWV_BOARD_NAND_WRITE_PARAMS 0x000F0F0F +#define MVLSWV_BOARD_NAND_CONTROL 0x01c7D943 + +MV_BOARD_INFO mvlswvInfo = { + "MVLSWV", /* boardName[MAX_BOARD_NAME_LEN] */ + MVLSWV_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppTypeValue */ + mvlswvInfoBoardMppTypeInfo, /* pBoardMppTypeValue */ + MVLSWV_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfigValue */ + mvlswvInfoBoardMppConfigValue, /* pBoardMppConfigValue */ + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + MVLSWV_BOARD_DEVICE_CONFIG_NUM, /* numBoardDeviceIf */ + mvlsxhInfoBoardDeCsInfo, /* pDevCsInfo */ + MVLSWV_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, /* pBoardTwsiDev */ + MVLSWV_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + mvlswvInfoBoardMacInfo, /* pBoardMacInfo */ + MVLSWV_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + mvlswvInfoBoardGppInfo, /* pBoardGppInfo */ + 0, /* activeLedsNumber */ + NULL, /* pLedGppPin */ + 0, /* ledsPolarity */ + MVLSWV_OE_LOW, /* gppOutEnLow */ + MVLSWV_OE_HIGH, /* gppOutEnHigh */ + MVLSWV_OE_VAL_LOW, /* gppOutValLow */ + MVLSWV_OE_VAL_HIGH, /* gppOutValHigh */ + MVLSWV_POLARITY_VAL_LOW, /* gppPolarityValLow */ + MVLSWV_POLARITY_VAL_HIGH, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + MVLSWV_BOARD_NAND_READ_PARAMS, /* nandFlashReadParams */ + MVLSWV_BOARD_NAND_WRITE_PARAMS, /* nandFlashWriteParams */ + MVLSWV_BOARD_NAND_CONTROL, /* nandFlashControl */ +}; + +/****************************** MVLSQV ******************************/ +MV_BOARD_MAC_INFO mvlsqvInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + { + {BOARD_MAC_SPEED_AUTO, 0x0} + }; + +MV_BOARD_GPP_INFO mvlsqvInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_HDD_POWER, 8}, // HDDPWR_0 + {BOARD_GPP_HDD_POWER, 9}, // HDDPWR_1 + {BOARD_GPP_HDD_POWER, 22}, // HDDPWR_2 + {BOARD_GPP_HDD_POWER, 23}, // HDDPWR_3 + {BOARD_GPP_USB_VBUS_EN, 12}, + {BOARD_GPP_FAN_HIGH, 16}, + {BOARD_GPP_FAN_LOW, 17}, + {BOARD_GPP_HDD_ERR_LED, 34}, // HDD_ERROR_0# + {BOARD_GPP_HDD_ERR_LED, 35}, // HDD_ERROR_1# + {BOARD_GPP_HDD_ERR_LED, 24}, // HDD_ERROR_2# + {BOARD_GPP_HDD_ERR_LED, 25}, // HDD_ERROR_3# + {BOARD_GPP_FUNC_LED, 39}, + {BOARD_GPP_ALARM_LED, 36}, + {BOARD_GPP_INFO_LED, 38}, + {BOARD_GPP_PWR_LED, 40}, + {BOARD_GPP_FAN_LOCK, 43}, + {BOARD_GPP_FUNC_SW, 45}, + {BOARD_GPP_PWR_SW, 46}, + {BOARD_GPP_PWRAUTO_SW, 47}, + {BOARD_GPP_FUNC_RED_LED,37}, + {BOARD_GPP_UART_EN, 48}, + }; + +MV_BOARD_MPP_TYPE_INFO mvlsqvInfoBoardMppTypeInfo[] = + /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ + { + {MV_BOARD_OTHER, MV_BOARD_OTHER} + //{MV_BOARD_OTHER,MV_BOARD_RGMII} + }; + +MV_BOARD_MPP_INFO mvlsqvInfoBoardMppConfigValue[] = + {{{ + MVLSQV_MPP0_7, + MVLSQV_MPP8_15, + MVLSQV_MPP16_23, + MVLSQV_MPP24_31, + MVLSQV_MPP32_39, + MVLSQV_MPP40_47, + MVLSQV_MPP48_55 + }}}; + +MV_DEV_CS_INFO mvlsqvInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; + +#define MVLSQV_BOARD_PCI_IF_NUM 0x0 +#define MVLSQV_BOARD_TWSI_DEF_NUM 0x0 +#define MVLSQV_BOARD_MAC_INFO_NUM 0x1 +#define MVLSQV_BOARD_GPP_INFO_NUM (sizeof(mvlsqvInfoBoardGppInfo)/sizeof(MV_BOARD_GPP_INFO)) +#define MVLSQV_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define MVLSQV_BOARD_MPP_CONFIG_NUM 0x1 +#define MVLSQV_BOARD_DEVICE_CONFIG_NUM 0x2 +#define MVLSQV_BOARD_NAND_READ_PARAMS 0x003E07CF +#define MVLSQV_BOARD_NAND_WRITE_PARAMS 0x000F0F0F +#define MVLSQV_BOARD_NAND_CONTROL 0x01c7D943 + +MV_BOARD_INFO mvlsqvInfo = { + "MVLSQV", /* boardName[MAX_BOARD_NAME_LEN] */ + MVLSQV_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppTypeValue */ + mvlsqvInfoBoardMppTypeInfo, /* pBoardMppTypeValue */ + MVLSQV_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfigValue */ + mvlsqvInfoBoardMppConfigValue, /* pBoardMppConfigValue */ + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + MVLSQV_BOARD_DEVICE_CONFIG_NUM, /* numBoardDeviceIf */ + mvlsqvInfoBoardDeCsInfo, /* pDevCsInfo */ + MVLSQV_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, /* pBoardTwsiDev */ + MVLSQV_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + mvlsqvInfoBoardMacInfo, /* pBoardMacInfo */ + MVLSQV_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + mvlsqvInfoBoardGppInfo, /* pBoardGppInfo */ + 0, /* activeLedsNumber */ + NULL, /* pLedGppPin */ + 0, /* ledsPolarity */ + MVLSQV_OE_LOW, /* gppOutEnLow */ + MVLSQV_OE_HIGH, /* gppOutEnHigh */ + MVLSQV_OE_VAL_LOW, /* gppOutValLow */ + MVLSQV_OE_VAL_HIGH, /* gppOutValHigh */ + MVLSQV_POLARITY_VAL_LOW, /* gppPolarityValLow */ + MVLSQV_POLARITY_VAL_HIGH, /* gppPolarityValHigh */ + NULL, /* pSwitchInfo */ + MVLSQV_BOARD_NAND_READ_PARAMS, /* nandFlashReadParams */ + MVLSQV_BOARD_NAND_WRITE_PARAMS, /* nandFlashWriteParams */ + MVLSQV_BOARD_NAND_CONTROL, /* nandFlashControl */ +}; + +MV_BOARD_INFO* boardInfoTbl[] = { + &mvlsxhInfo, /* 0x00: MVLSXH */ + &mvlsvlInfo, /* 0x01: MVLSVL */ + &mvlswvInfo, /* 0x02: MVLSWV */ + &mvlsqvInfo, /* 0x03: MVLSQV */ + &mvlsxlInfo, /* 0x04: MVLSXL */ + &mvlsxhInfo, /* 0x05: dummy */ + &mvlsxlGeV2Info, /* 0x06: MVLSXL-V2 */ + &mvlsxhInfo, /* 0x07: dummy */ + &mvwxlInfo, /* 0x08: MVWXL */ + &mvlsxhInfo, /* 0x09: dummy */ + &mvlsxhInfo, /* 0x0a: dummy */ + &mvlsxhInfo, /* 0x0b: dummy */ + &mvlsxhInfo, /* 0x0c: dummy */ + &mvlsxhInfo, /* 0x0d: dummy */ + &mvlsxhInfo, /* 0x0e: dummy */ + &mvlsxhInfo, /* 0x0f: dummy */ + &mvwssxInfo, /* 0x10: MVWSSX */ +}; + +#endif // CONFIG_BUFFALO_PLATFORM diff --git a/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvSpec.h b/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvSpec.h new file mode 100644 index 0000000..4b93896 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/boardEnv/mvBoardEnvSpec.h @@ -0,0 +1,428 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoardEnvSpech +#define __INCmvBoardEnvSpech + +#include "mvSysHwConfig.h" + + +/* For future use */ +#define BD_ID_DATA_START_OFFS 0x0 +#define BD_DETECT_SEQ_OFFS 0x0 +#define BD_SYS_NUM_OFFS 0x4 +#define BD_NAME_OFFS 0x8 + +/* I2C bus addresses */ +#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ +#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM0_I2C_ADDR 0x56 +#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM1_I2C_ADDR 0x54 +#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_EEPROM_I2C_ADDR 0x51 +#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 +#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 +#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 + +#define BOOT_FLASH_INDEX 0 +#define MAIN_FLASH_INDEX 1 + +#define BOARD_ETH_START_PORT_NUM 0 + +/* Supported clocks */ +#define MV_BOARD_TCLK_100MHZ 100000000 +#define MV_BOARD_TCLK_125MHZ 125000000 +#define MV_BOARD_TCLK_133MHZ 133333333 +#define MV_BOARD_TCLK_150MHZ 150000000 +#define MV_BOARD_TCLK_166MHZ 166666667 +#define MV_BOARD_TCLK_200MHZ 200000000 + +#define MV_BOARD_SYSCLK_100MHZ 100000000 +#define MV_BOARD_SYSCLK_125MHZ 125000000 +#define MV_BOARD_SYSCLK_133MHZ 133333333 +#define MV_BOARD_SYSCLK_150MHZ 150000000 +#define MV_BOARD_SYSCLK_166MHZ 166666667 +#define MV_BOARD_SYSCLK_200MHZ 200000000 +#define MV_BOARD_SYSCLK_233MHZ 233333333 +#define MV_BOARD_SYSCLK_250MHZ 250000000 +#define MV_BOARD_SYSCLK_267MHZ 266666667 +#define MV_BOARD_SYSCLK_300MHZ 300000000 +#define MV_BOARD_SYSCLK_333MHZ 333333334 +#define MV_BOARD_SYSCLK_400MHZ 400000000 + +#define MV_BOARD_REFCLK_25MHZ 25000000 + +/* Board specific */ +/* =============================== */ + +/* boards ID numbers */ + +#define BOARD_ID_BASE 0x0 + +/* New board ID numbers */ +#define DB_88F6281A_BP_ID (BOARD_ID_BASE) +#define DB_88F6281_BP_MLL_ID 1680 +#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) +#define RD_88F6281_MLL_ID 1682 +#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) +#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) +#define RD_88F6192_MLL_ID 1681 +#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) +#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) +#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) +#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) +#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) +#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) +#define DB_88F6280A_BP_ID (BOARD_ID_BASE+0xA) +#define DB_88F6282A_BP_ID (BOARD_ID_BASE+0xB) +#define MV_MAX_BOARD_ID (DB_88F6282A_BP_ID + 1) + +/* BUFFALO board ID numbers */ +#if defined(CONFIG_BUFFALO_PLATFORM) + #define BUFFALO_BOARD_ID_BASE 0x80 + #define BF_MVLSXH_ID (BUFFALO_BOARD_ID_BASE) + #define BF_MVLSVL_ID (BUFFALO_BOARD_ID_BASE + 0x01) + #define BF_MVLSWV_ID (BUFFALO_BOARD_ID_BASE + 0x02) + #define BF_MVLSQV_ID (BUFFALO_BOARD_ID_BASE + 0x03) + #define BF_MVLSXL_ID (BUFFALO_BOARD_ID_BASE + 0x04) + #define BF_MVLSXL_GE_ID (BUFFALO_BOARD_ID_BASE + 0x05) + #define BF_MVLSXL_GE_V2_ID (BUFFALO_BOARD_ID_BASE + 0x06) + #define BF_MVWXL_ID (BUFFALO_BOARD_ID_BASE + 0x08) + #define BF_MVWSSX_ID (BUFFALO_BOARD_ID_BASE + 0x10) + #undef MV_MAX_BOARD_ID + #define MV_MAX_BOARD_ID (BF_MVWSSX_ID + 1) +#endif // defined(CONFIG_BUFFALO_PLATFORM) + +/* DB-88F6281A-BP */ +#if defined(MV_NAND) + #define DB_88F6281A_MPP0_7 0x21111111 +#else + #define DB_88F6281A_MPP0_7 0x21112220 +#endif +#define DB_88F6281A_MPP8_15 0x11113311 +#define DB_88F6281A_MPP16_23 0x00551111 +#define DB_88F6281A_MPP24_31 0x00000000 +#define DB_88F6281A_MPP32_39 0x00000000 +#define DB_88F6281A_MPP40_47 0x00000000 +#define DB_88F6281A_MPP48_55 0x00000000 +#define DB_88F6281A_OE_LOW 0x0 +#if defined(MV_TDM_5CHANNELS) + #define DB_88F6281A_OE_HIGH (BIT6) +#else +#define DB_88F6281A_OE_HIGH 0x0 +#endif +#define DB_88F6281A_OE_VAL_LOW 0x0 +#define DB_88F6281A_OE_VAL_HIGH 0x0 + + +/* DB-88F6282A-BP */ +#if defined(MV_NAND) + #define DB_88F6282A_MPP0_7 0x21111111 +#else + #define DB_88F6282A_MPP0_7 0x21112220 +#endif +#define DB_88F6282A_MPP8_15 0x11113311 +#define DB_88F6282A_MPP16_23 0x00551111 +#define DB_88F6282A_MPP24_31 0x00000000 +#define DB_88F6282A_MPP32_39 0x00000000 +#define DB_88F6282A_MPP40_47 0x00000000 +#define DB_88F6282A_MPP48_55 0x00000000 +#define DB_88F6282A_OE_LOW 0x0 +#if defined(MV_TDM_5CHANNELS) + #define DB_88F6282A_OE_HIGH (BIT6) +#else +#define DB_88F6282A_OE_HIGH 0x0 +#endif +#define DB_88F6282A_OE_VAL_LOW 0x0 +#define DB_88F6282A_OE_VAL_HIGH 0x0 + + +/* RD-88F6281A */ +#if defined(MV_NAND) + #define RD_88F6281A_MPP0_7 0x21111111 +#else + #define RD_88F6281A_MPP0_7 0x21112220 +#endif +#define RD_88F6281A_MPP8_15 0x11113311 +#define RD_88F6281A_MPP16_23 0x33331111 +#define RD_88F6281A_MPP24_31 0x33003333 +#define RD_88F6281A_MPP32_39 0x20440533 +#define RD_88F6281A_MPP40_47 0x22202222 +#define RD_88F6281A_MPP48_55 0x00000002 +#define RD_88F6281A_OE_LOW (BIT28 | BIT29) +#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) +#define RD_88F6281A_OE_VAL_LOW 0x0 +#define RD_88F6281A_OE_VAL_HIGH 0x0 + +/* DB-88F6192A-BP */ +#if defined(MV_NAND) + #define DB_88F6192A_MPP0_7 0x21111111 +#else + #define DB_88F6192A_MPP0_7 0x21112220 +#endif +#define DB_88F6192A_MPP8_15 0x11113311 +#define DB_88F6192A_MPP16_23 0x00501111 +#define DB_88F6192A_MPP24_31 0x00000000 +#define DB_88F6192A_MPP32_35 0x00000000 +#define DB_88F6192A_OE_LOW (BIT22 | BIT23) +#define DB_88F6192A_OE_HIGH 0x0 +#define DB_88F6192A_OE_VAL_LOW 0x0 +#define DB_88F6192A_OE_VAL_HIGH 0x0 + +/* RD-88F6192A */ +#define RD_88F6192A_MPP0_7 0x01222222 +#define RD_88F6192A_MPP8_15 0x00000011 +#define RD_88F6192A_MPP16_23 0x05550000 +#define RD_88F6192A_MPP24_31 0x0 +#define RD_88F6192A_MPP32_35 0x0 +#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) +#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) +#define RD_88F6192A_OE_VAL_LOW 0x18400 +#define RD_88F6192A_OE_VAL_HIGH 0x8 + +/* DB-88F6180A-BP */ +#if defined(MV_NAND) + #define DB_88F6180A_MPP0_7 0x21111111 +#else + #define DB_88F6180A_MPP0_7 0x01112222 +#endif +#define DB_88F6180A_MPP8_15 0x11113311 +#define DB_88F6180A_MPP16_23 0x00001111 +#define DB_88F6180A_MPP24_31 0x0 +#define DB_88F6180A_MPP32_39 0x4444c000 +#define DB_88F6180A_MPP40_44 0x00044444 +#define DB_88F6180A_OE_LOW 0x0 +#define DB_88F6180A_OE_HIGH 0x0 +#define DB_88F6180A_OE_VAL_LOW 0x0 +#define DB_88F6180A_OE_VAL_HIGH 0x0 + +/* RD-88F6281A_PCAC */ +#define RD_88F6281A_PCAC_MPP0_7 0x21111111 +#define RD_88F6281A_PCAC_MPP8_15 0x00003311 +#define RD_88F6281A_PCAC_MPP16_23 0x00001100 +#define RD_88F6281A_PCAC_MPP24_31 0x00000000 +#define RD_88F6281A_PCAC_MPP32_39 0x00000000 +#define RD_88F6281A_PCAC_MPP40_47 0x00000000 +#define RD_88F6281A_PCAC_MPP48_55 0x00000000 +#define RD_88F6281A_PCAC_OE_LOW 0x0 +#define RD_88F6281A_PCAC_OE_HIGH 0x0 +#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 +#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 + +/* DB-88F6280A-BP */ +#if defined(MV_NAND) + #define DB_88F6280A_MPP0_7 0x01111111 +#else + #define DB_88F6280A_MPP0_7 0x01222222 +#endif +#define DB_88F6280A_MPP8_15 0x00300011 +#define DB_88F6280A_MPP16_23 0x00001103 +#define DB_88F6280A_MPP24_31 0x00000000 +#define DB_88F6280A_MPP32_39 0x00000000 +#define DB_88F6280A_MPP40_47 0x00000000 +#define DB_88F6280A_MPP48_55 0x00000000 +#define DB_88F6280A_OE_LOW (0xffffffff) +#define DB_88F6280A_OE_HIGH 0x0 +#define DB_88F6280A_OE_VAL_LOW 0x0 +#define DB_88F6280A_OE_VAL_HIGH 0x0 + + +/* SHEEVA PLUG */ +#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 +#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 +#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 +#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 +#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 +#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 +#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 +#define RD_SHEEVA_PLUG_OE_LOW 0x0 +#define RD_SHEEVA_PLUG_OE_HIGH 0x0 +#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) +#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) + +/* DB-CUSTOMER */ +#define DB_CUSTOMER_MPP0_7 0x21111111 +#define DB_CUSTOMER_MPP8_15 0x00003311 +#define DB_CUSTOMER_MPP16_23 0x00001100 +#define DB_CUSTOMER_MPP24_31 0x00000000 +#define DB_CUSTOMER_MPP32_39 0x00000000 +#define DB_CUSTOMER_MPP40_47 0x00000000 +#define DB_CUSTOMER_MPP48_55 0x00000000 +#define DB_CUSTOMER_OE_LOW 0x0 +#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) +#define DB_CUSTOMER_OE_VAL_LOW 0x0 +#define DB_CUSTOMER_OE_VAL_HIGH 0x0 + +#if defined(CONFIG_BUFFALO_PLATFORM) +/* MVLSXH/MVLSXL */ +#define MVLSXH_MPP0_7 0x01222222 +#define MVLSXH_MPP8_15 0x11110000 +#define MVLSXH_MPP16_23 0x33330011 +#define MVLSXH_MPP24_31 0x33003333 +#define MVLSXH_MPP32_39 0x00000033 +#define MVLSXH_MPP40_47 0x00000000 +#define MVLSXH_MPP48_55 0x00000000 +#define MVLSXH_OE_LOW (~((BIT7)|(BIT8)|(BIT10)|(BIT11)|(BIT18)|(BIT19))) +#define MVLSXH_OE_HIGH (~((BIT4)|(BIT5)|(BIT6)|(BIT7)|(BIT16))) +#define MVLSXH_OE_VAL_LOW ((BIT7)|(BIT8)|(BIT18)|(BIT19)) +#define MVLSXH_OE_VAL_HIGH ((BIT4)|(BIT5)|(BIT6)|(BIT7)|(BIT16)) +#define MVLSXH_POLARITY_VAL_LOW ((BIT18)|(BIT19)) +#define MVLSXH_POLARITY_VAL_HIGH ((BIT4)|(BIT5)|(BIT6)|(BIT7)|(BIT9)|(BIT10)|(BIT11)|(BIT14)|(BIT16)|(BIT17)) + +/* MVLSXL-GE-V2 */ +#define MVLSXL_GE_V2_MPP0_7 0x21111111 +#define MVLSXL_GE_V2_MPP8_15 0x00003300 +#define MVLSXL_GE_V2_MPP16_23 0x00501100 +#define MVLSXL_GE_V2_MPP24_31 0x00000000 +#define MVLSXL_GE_V2_MPP32_35 0x00000000 +#define MVLSXL_GE_V2_OE_LOW (~((BIT14)|(BIT17)|(BIT26)|(BIT27))) +#define MVLSXL_GE_V2_OE_HIGH 0x0 +#define MVLSXL_GE_V2_OE_VAL_LOW ((BIT14)|(BIT17)|(BIT26)|(BIT27)) +#define MVLSXL_GE_V2_OE_VAL_HIGH 0x0 +#define MVLSXL_GE_V2_POLARITY_VAL_LOW ((BIT17)|(BIT26)|(BIT27)) +#define MVLSXL_GE_V2_POLARITY_VAL_HIGH 0x0 + + +/* MVWXL */ +#define MVWXL_MPP0_7 0x21111111 +#define MVWXL_MPP8_15 0x11113300 +#define MVWXL_MPP16_23 0x33331111 +#define MVWXL_MPP24_31 0x33003333 +#define MVWXL_MPP32_39 0x00000033 +#define MVWXL_MPP40_47 0x00000000 +#define MVWXL_MPP48_55 0x00000000 +#define MVWXL_OE_LOW (~((BIT8)|(BIT28)|(BIT29))) +#define MVWXL_OE_HIGH (~((BIT2)|(BIT4)|(BIT5)|(BIT6)|(BIT7)|(BIT14)|(BIT15)|(BIT16)|(BIT17))) +#define MVWXL_OE_VAL_LOW (0) +#define MVWXL_OE_VAL_HIGH ((BIT4)|(BIT6)|(BIT15)|(BIT16)|(BIT17)) +#define MVWXL_POLARITY_VAL_LOW (0) +#define MVWXL_POLARITY_VAL_HIGH ((BIT4)|(BIT6)|(BIT9)|(BIT10)|(BIT11)|(BIT15)|(BIT16)|(BIT17)) + +/* MVWSSX */ +#define MVWSSX_MPP0_7 0x21111111 +#define MVWSSX_MPP8_15 0x11113300 +#define MVWSSX_MPP16_23 0x33331111 +#define MVWSSX_MPP24_31 0x33003333 +#define MVWSSX_MPP32_39 0x00000033 +#define MVWSSX_MPP40_47 0x00000000 +#define MVWSSX_MPP48_55 0x00000000 +#define MVWSSX_OE_LOW (~((BIT28))) +#define MVWSSX_OE_HIGH (~((BIT2)|(BIT3)|(BIT4)|(BIT5)|(BIT6)|(BIT7)|(BIT14)|(BIT17))) +#define MVWSSX_OE_VAL_LOW 0 +#define MVWSSX_OE_VAL_HIGH ((BIT4)|(BIT6)|(BIT17)) +#define MVWSSX_POLARITY_VAL_LOW 0 +#define MVWSSX_POLARITY_VAL_HIGH ((BIT4)|(BIT6)|(BIT9)|(BIT10)|(BIT11)|(BIT15)|(BIT16)|(BIT17)) + +/* MVLSVL */ +#define MVLSVL_MPP0_7 0x21111111 +#define MVLSVL_MPP8_15 0x00003300 +#define MVLSVL_MPP16_23 0x00001100 +#define MVLSVL_MPP24_31 0x00000000 +#define MVLSVL_MPP32_39 0x00000000 +#define MVLSVL_MPP40_47 0x00000000 +#define MVLSVL_MPP48_55 0x00000000 +#define MVLSVL_OE_LOW (~((BIT8)|(BIT9)|(BIT12)|(BIT16)|(BIT17))) +#define MVLSVL_OE_HIGH (~((BIT4)|(BIT5)|(BIT6)|(BIT7)|(BIT8))) +#define MVLSVL_OE_VAL_LOW ((BIT16)|(BIT17)) +#define MVLSVL_OE_VAL_HIGH ((BIT8)) +#define MVLSVL_POLARITY_VAL_LOW ((BIT16)|(BIT17)) +#define MVLSVL_POLARITY_VAL_HIGH ((BIT8)|(BIT12)|(BIT13)|(BIT14)|(BIT15)|(BIT16)) + +/* MVLSWV */ +#define MVLSWV_MPP0_7 0x21111111 +#define MVLSWV_MPP8_15 0x00003300 +#define MVLSWV_MPP16_23 0x00001100 +#define MVLSWV_MPP24_31 0x00000000 +#define MVLSWV_MPP32_39 0x00000000 +#define MVLSWV_MPP40_47 0x00000000 +#define MVLSWV_MPP48_55 0x00000000 +#define MVLSWV_OE_LOW (~((BIT8)|(BIT9)|(BIT12)|(BIT16)|(BIT17))) +#define MVLSWV_OE_HIGH (~((BIT2)|(BIT3)|(BIT4)|(BIT5)|(BIT6)|(BIT7)|(BIT8))) +#define MVLSWV_OE_VAL_LOW ((BIT16)|(BIT17)) +#define MVLSWV_OE_VAL_HIGH ((BIT8)) +#define MVLSWV_POLARITY_VAL_LOW ((BIT16)|(BIT17)) +#define MVLSWV_POLARITY_VAL_HIGH ((BIT8)|(BIT12)|(BIT13)|(BIT14)|(BIT15)|(BIT16)) + +/* MVLSQV */ +#define MVLSQV_MPP0_7 0x21111111 +#define MVLSQV_MPP8_15 0x00003300 +#define MVLSQV_MPP16_23 0x00001100 +#define MVLSQV_MPP24_31 0x00000000 +#define MVLSQV_MPP32_39 0x00000000 +#define MVLSQV_MPP40_47 0x00000000 +#define MVLSQV_MPP48_55 0x00000000 +#define MVLSQV_OE_LOW (~((BIT8)|(BIT9)|(BIT12)|(BIT16)|(BIT17)|(BIT22)|(BIT23)|(BIT24)|(BIT25))) +#define MVLSQV_OE_HIGH (~((BIT2)|(BIT3)|(BIT4)|(BIT5)|(BIT6)|(BIT7)|(BIT8))) +#define MVLSQV_OE_VAL_LOW ((BIT16)|(BIT17)|(BIT24)|(BIT25)) +#define MVLSQV_OE_VAL_HIGH ((BIT2)|(BIT3)|(BIT8)) +#define MVLSQV_POLARITY_VAL_LOW ((BIT16)|(BIT17)|(BIT24)|(BIT25)) +#define MVLSQV_POLARITY_VAL_HIGH ((BIT2)|(BIT3)|(BIT8)|(BIT12)|(BIT13)|(BIT14)|(BIT16)) + +#endif // CONFIG_BUFFALO_PLATFORM + +#endif /* __INCmvBoardEnvSpech */ diff --git a/board/mv_feroceon/mv_kw/kw_family/cpu/mvCpu.c b/board/mv_feroceon/mv_kw/kw_family/cpu/mvCpu.c new file mode 100644 index 0000000..a2b517a --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/cpu/mvCpu.c @@ -0,0 +1,319 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* locals */ + +/******************************************************************************* +* mvCpuPclkGet - Get the CPU pClk (pipe clock) +* +* DESCRIPTION: +* This routine extract the CPU core clock. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in MHertz. +* +*******************************************************************************/ +/* 6180 have different clk reset sampling */ + +static MV_U32 mvCpu6180PclkGet(MV_VOID) +{ + MV_U32 tmpPClkRate=0; + MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; + + tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); + tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; + tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; + + tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; + + return tmpPClkRate; +} + + +MV_U32 mvCpuPclkGet(MV_VOID) +{ +#if defined(PCLCK_AUTO_DETECT) + MV_U32 tmpPClkRate=0; + MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; + + if(mvCtrlModelGet() == MV_6180_DEV_ID || mvCtrlModelGet() == MV_6280_DEV_ID) + return mvCpu6180PclkGet(); + + tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); + tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); + tmpPClkRate = cpuCLK[tmpPClkRate]; + + return tmpPClkRate; +#else + return MV_DEFAULT_PCLK +#endif +} + +/******************************************************************************* +* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) +* +* DESCRIPTION: +* This routine extract the CPU L2 clock. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +static MV_U32 mvCpu6180L2ClkGet(MV_VOID) +{ + MV_U32 L2ClkRate=0; + MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; + + L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); + L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; + L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; + + L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; + + return L2ClkRate; + +} + +MV_U32 mvCpuL2ClkGet(MV_VOID) +{ +#ifdef L2CLK_AUTO_DETECT + MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; + MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; + + if(mvCtrlModelGet() == MV_6180_DEV_ID || mvCtrlModelGet() == MV_6280_DEV_ID) + return mvCpu6180L2ClkGet(); + + pClkRate = mvCpuPclkGet(); + + tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); + indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); + + L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); + return L2ClkRate; +#else + return MV_BOARD_DEFAULT_L2CLK; +#endif +} + + +/******************************************************************************* +* mvCpuNameGet - Get CPU name +* +* DESCRIPTION: +* This function returns a string describing the CPU model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* None. +*******************************************************************************/ +MV_VOID mvCpuNameGet(char *pNameBuff) +{ + MV_U32 cpuModel; + + cpuModel = mvOsCpuPartGet(); + + /* The CPU module is indicated in the Processor Version Register (PVR) */ + switch(cpuModel) + { + case CPU_PART_MRVL131: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); + break; + case CPU_PART_ARM926: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); + break; + case CPU_PART_ARM946: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); + break; + default: + mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); + break; + } /* switch */ + + return; +} + + +#define MV_PROC_STR_SIZE 50 + +static void mvCpuIfGetL2EccMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); + if (regVal & BIT2) + mvOsSPrintf(buf, "L2 ECC Enabled"); + else + mvOsSPrintf(buf, "L2 ECC Disabled"); +} + +static void mvCpuIfGetL2Mode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT22) + mvOsSPrintf(buf, "L2 Enabled"); + else + mvOsSPrintf(buf, "L2 Disabled"); +} + +static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT24) + mvOsSPrintf(buf, "L2 Prefetch Disabled"); + else + mvOsSPrintf(buf, "L2 Prefetch Enabled"); +} + +static void mvCpuIfGetWriteAllocMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT28) + mvOsSPrintf(buf, "Write Allocate Enabled"); + else + mvOsSPrintf(buf, "Write Allocate Disabled"); +} + +static void mvCpuIfGetCpuStreamMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT29) + mvOsSPrintf(buf, "CPU Streaming Enabled"); + else + mvOsSPrintf(buf, "CPU Streaming Disabled"); +} + +static void mvCpuIfPrintCpuRegs(void) +{ + MV_U32 regVal = 0; + + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); + + __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ + mvOsPrintf("Control Reg = 0x%x\n",regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ + mvOsPrintf("ID Code Reg = 0x%x\n",regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ + mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); + +} + +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) +{ + MV_U32 count = 0; + + MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; + MV_8 L2_En_str[MV_PROC_STR_SIZE]; + MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; + MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; + MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; + + mvCpuIfGetL2Mode(L2_En_str); + mvCpuIfGetL2EccMode(L2_ECC_str); + mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); + mvCpuIfGetWriteAllocMode(Write_Alloc_str); + mvCpuIfGetCpuStreamMode(Cpu_Stream_str); + mvCpuIfPrintCpuRegs(); + + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); + return count; +} + +MV_U32 whoAmI(MV_VOID) +{ + return 0; +} + diff --git a/board/mv_feroceon/mv_kw/kw_family/cpu/mvCpu.h b/board/mv_feroceon/mv_kw/kw_family/cpu/mvCpu.h new file mode 100644 index 0000000..7f58b03 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/cpu/mvCpu.h @@ -0,0 +1,99 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuh +#define __INCmvCpuh + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* defines */ +#define CPU_PART_MRVL131 0x131 +#define CPU_PART_ARM926 0x926 +#define CPU_PART_ARM946 0x946 +#define MV_CPU_ARM_CLK_ELM_SIZE 12 +#define MV_CPU_ARM_CLK_RATIO_OFF 8 +#define MV_CPU_ARM_CLK_DDR_OFF 4 + +#ifndef MV_ASMLANGUAGE +typedef struct _mvCpuArmClk +{ + MV_U32 cpuClk; /* CPU clock in MHz */ + MV_U32 ddrClk; /* DDR clock in MHz */ + MV_U32 l2Clk; /* CPU DDR clock ratio */ + +}MV_CPU_ARM_CLK; + +MV_U32 mvCpuPclkGet(MV_VOID); +MV_VOID mvCpuNameGet(char *pNameBuff); +MV_U32 mvCpuL2ClkGet(MV_VOID); +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); +MV_U32 whoAmI(MV_VOID); + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __INCmvCpuh */ diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c new file mode 100644 index 0000000..fbe7c56 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c @@ -0,0 +1,296 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvCtrlEnvAddrDec.h - Marvell controller address decode library +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "ddr2/mvDramIfRegs.h" +#include "pex/mvPexRegs.h" + +#define MV_DEBUG + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* Default Attributes array */ +MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; +extern MV_TARGET *sampleAtResetTargetArray; +/* Dram\AHBToMbus\PEX share regsiter */ + +#define CTRL_DEC_BASE_OFFS 16 +#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) +#define CTRL_DEC_BASE_ALIGNMENT 0x10000 + +#define CTRL_DEC_SIZE_OFFS 16 +#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) +#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 + +#define CTRL_DEC_WIN_EN BIT0 + + + +/******************************************************************************* +* mvCtrlAddrDecToReg - Get address decode register format values +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) +{ + + MV_U32 baseToReg=0 , sizeToReg=0; + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; + + /* Write to address decode Base Address Register */ + pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; + pAddrDecRegs->baseReg |= baseToReg; + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + return MV_BAD_PARAM; + } + + /* set size */ + pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; + pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); + + + return MV_OK; + +} + +/******************************************************************************* +* mvCtrlRegToAddrDec - Extract address decode struct from registers. +* +* DESCRIPTION: +* This function extract address decode struct from address decode +* registers given as parameters. +* +* INPUT: +* pAddrDecRegs - Address decode register struct. +* +* OUTPUT: +* pAddrDecWin - Target window data structure. +* +* RETURN: +* MV_BAD_PARAM if address decode registers data is invalid. +* +*******************************************************************************/ +MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 sizeRegVal; + + sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> + CTRL_DEC_SIZE_OFFS; + + pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); + + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; + + pAddrDecWin->baseHigh = 0; + + return MV_OK; + +} + +/******************************************************************************* +* mvCtrlAttribGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ + +MV_STATUS mvCtrlAttribGet(MV_TARGET target, + MV_TARGET_ATTRIB *targetAttrib) +{ + + targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; + targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; + + return MV_OK; + +} + +/******************************************************************************* +* mvCtrlGetAttrib - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) +{ + MV_TARGET target; + MV_TARGET x; + for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) + { + x = MV_CHANGE_BOOT_CS(target); + if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && + (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) + { + /* found it */ + break; + } + } + + return target; +} + +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, + MV_DEC_WIN_PARAMS *pWinParam) +{ + MV_U32 baseToReg=0, sizeToReg=0; + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; + + /* Write to address decode Base Address Register */ + pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; + pWinParam->baseAddr |= baseToReg; + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); + return MV_BAD_PARAM; + } + pWinParam->size = sizeToReg; + + pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; + pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; + + return MV_OK; +} + +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, + MV_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttrib; + + pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; + + /* Upper 32bit address base is supported under PCI High Address remap */ + pAddrDecWin->addrWin.baseHigh = 0; + + /* Prepare sizeReg to ctrlRegToSize function */ + pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); + + if (-1 == pAddrDecWin->addrWin.size) + { + DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); + return MV_BAD_PARAM; + } + targetAttrib.targetId = pWinParam->targetId; + targetAttrib.attrib = pWinParam->attrib; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; +} + + + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h new file mode 100644 index 0000000..946737f --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h @@ -0,0 +1,203 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAddrDech +#define __INCmvCtrlEnvAddrDech + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" + + +/* defines */ +/* DUnit attributes */ +#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 +#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 +#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) + +#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 +#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 +#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) + +#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 +#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 +#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) + +#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 +#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 +#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) + +/* RUnit (Device) attributes */ +#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 +#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 +#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 +#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 +#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 +#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 +#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) + +#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 +#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 +#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) + +/* LMaster (PCI) attributes */ +#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) + + +#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 +#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 +#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) + +#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 + +#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 +#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 +#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) +#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) + +#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 +#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 +#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 +#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 +#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +/* PEX Attributes */ +#define ATMWCR_WIN_PEX_TYPE_OFFS 3 +#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 +#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) +#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) + +/* typedefs */ + +/* Unsupported attributes for address decode: */ +/* 2) PCI0/1_REQ64n control */ + +typedef struct _mvDecRegs +{ + MV_U32 baseReg; + MV_U32 baseRegHigh; + MV_U32 sizeReg; + +}MV_DEC_REGS; + +typedef struct _mvTargetAttrib +{ + MV_U8 attrib; /* chip select attributes */ + MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ + +}MV_TARGET_ATTRIB; + + +/* This structure describes address decode window */ +typedef struct _mvDecWin +{ + MV_TARGET target; /* Target for addr decode window */ + MV_ADDR_WIN addrWin; /* Address window of target */ + MV_BOOL enable; /* Window enable/disable */ +}MV_DEC_WIN; + +typedef struct _mvDecWinParams +{ + MV_TARGET_ID targetId; /* Target ID field */ + MV_U8 attrib; /* Attribute field */ + MV_U32 baseAddr; /* Base address in register format */ + MV_U32 size; /* Size in register format */ +}MV_DEC_WIN_PARAMS; + + +/* mvCtrlEnvAddrDec API list */ + +MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, + MV_DEC_REGS *pAddrDecRegs); + +MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, + MV_ADDR_WIN *pAddrDecWin); + +MV_STATUS mvCtrlAttribGet(MV_TARGET target, + MV_TARGET_ATTRIB *targetAttrib); + +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); + + +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, + MV_DEC_WIN_PARAMS *pWinParam); + +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, + MV_DEC_WIN *pAddrDecWin); + + + + +#endif /* __INCmvCtrlEnvAddrDech */ diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvAsm.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvAsm.h new file mode 100644 index 0000000..6f6367a --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvAsm.h @@ -0,0 +1,98 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAsmh +#define __INCmvCtrlEnvAsmh +#include "pex/mvPexRegs.h" + +#define CHIP_BOND_REG 0x10034 +#define PCKG_OPT_MASK_AS #3 +#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK + +/* Read device ID into toReg bits 15:0 from 0xd0000000 */ +/* defines */ +#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read device ID into toReg bits 15:0 from 0xf1000000*/ +#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read Revision into toReg bits 7:0 0xd0000000*/ +#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + +/* Read Revision into toReg bits 7:0 0xf1000000*/ +#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + + +#endif /* __INCmvCtrlEnvAsmh */ diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvLib.c new file mode 100644 index 0000000..920acb8 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvLib.c @@ -0,0 +1,1911 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "mvCommon.h" +#include "mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#include "ctrlEnv/sys/mvSysPex.h" +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#include "ctrlEnv/sys/mvSysGbe.h" +#endif + +#if defined(MV_INCLUDE_XOR) +#include "ctrlEnv/sys/mvSysXor.h" +#endif + +#if defined(MV_INCLUDE_SATA) +#include "ctrlEnv/sys/mvSysSata.h" +#endif + +#if defined(MV_INCLUDE_USB) +#include "ctrlEnv/sys/mvSysUsb.h" +#endif + +#if defined(MV_INCLUDE_AUDIO) +#include "ctrlEnv/sys/mvSysAudio.h" +#endif + +#if defined(MV_INCLUDE_CESA) +#include "ctrlEnv/sys/mvSysCesa.h" +#endif + +#if defined(MV_INCLUDE_TS) +#include "ctrlEnv/sys/mvSysTs.h" +#endif + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/******************************************************************************* +* mvCtrlEnvInit - Initialize Marvell controller environment. +* +* DESCRIPTION: +* This function get environment information and initialize controller +* internal/external environment. For example +* 1) MPP settings according to board MPP macros. +* NOTE: It is the user responsibility to shut down all DMA channels +* in device and disable controller sub units interrupts during +* boot process. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCtrlEnvInit(MV_VOID) +{ + MV_U32 mppGroup; + MV_U32 devId; + MV_U32 boardId; + MV_U32 i; + MV_U32 maxMppGrp = 1; + MV_U32 mppVal = 0; + MV_U32 bootVal = 0; + MV_U32 mppGroupType = 0; + MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; + MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; + + devId = mvCtrlModelGet(); + boardId= mvBoardIdGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_GROUP; + break; + case MV_6282_DEV_ID: + maxMppGrp = MV_6282_MPP_MAX_GROUP; + break; + case MV_6280_DEV_ID: + maxMppGrp = MV_6280_MPP_MAX_GROUP; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_GROUP; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_GROUP; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_GROUP; + break; + } + + /* MPP Init */ + /* We split mpp init to 3 phases: + * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write + * in phase 2. + * 2. We detect the mpp group type and according the mpp values [35:20]. + * 3. We detect the mpp group type and according the mpp values [49:36]. + */ + /* Mpp phase 1 mpp[19:0] */ + /* Read MPP group from board level and assign to MPP register */ + for (mppGroup = 0; mppGroup < 3; mppGroup++) + { + mppVal = mvBoardMppGet(mppGroup); + if (mppGroup == 0) + { + bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); + if (mvCtrlIsBootFromSPI()) + { + mppVal &= ~0xffff; + bootVal &= 0xffff; + mppVal |= bootVal; + } + else if (mvCtrlIsBootFromSPIUseNAND()) + { + mppVal &= ~0xf0000000; + bootVal &= 0xf0000000; + mppVal |= bootVal; + } + else if (mvCtrlIsBootFromNAND()) + { + mppVal &= ~0xffffff; + bootVal &= 0xffffff; + mppVal |= bootVal; + } + } + + if (mppGroup == 2) + { + bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); + if (mvCtrlIsBootFromNAND()) + { + mppVal &= ~0xff00; + bootVal &= 0xff00; + mppVal |= bootVal; + } + } + + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); + } + + /* Identify MPPs group */ + mvBoardMppGroupIdUpdate(); + + /* Update MPPs mux relevent only on Marvell DB */ + if ((boardId == DB_88F6281A_BP_ID) || + (boardId == DB_88F6282A_BP_ID) || + (boardId == DB_88F6180A_BP_ID)) + mvBoardMppMuxSet(); + + mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); + + /* Mpp phase 2 */ + /* Read MPP group from board level and assign to MPP register */ + if (devId != MV_6180_DEV_ID && devId != MV_6280_DEV_ID) + { + i = 0; + for (mppGroup = 2; mppGroup < 5; mppGroup++) + { + if ((mppGroupType == MV_BOARD_OTHER) || + (boardId == RD_88F6281A_ID) || + (boardId == RD_88F6192A_ID) || + (boardId == RD_88F6190A_ID) || + (boardId == RD_88F6281A_PCAC_ID) || + (boardId == SHEEVA_PLUG_ID)) + mppVal = mvBoardMppGet(mppGroup); + else + { + mppVal = mppGroup1[mppGroupType][i]; + i++; + } + + /* Group 2 is shared mpp[23:16] */ + if (mppGroup == 2) + { + bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); + mppVal &= ~0xffff; + bootVal &= 0xffff; + mppVal |= bootVal; + } + + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); + } + } + + if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) + return MV_OK; + + /* Mpp phase 3 */ + mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); + /* Read MPP group from board level and assign to MPP register */ + i = 0; + for (mppGroup = 4; mppGroup < 7; mppGroup++) + { + if ((mppGroupType == MV_BOARD_OTHER) || + (boardId == RD_88F6281A_ID) || + (boardId == RD_88F6281A_PCAC_ID) || + (boardId == SHEEVA_PLUG_ID)) + mppVal = mvBoardMppGet(mppGroup); + else + { + mppVal = mppGroup2[mppGroupType][i]; + i++; + } + + /* Group 4 is shared mpp[35:32] */ + if (mppGroup == 4) + { + bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); + mppVal &= ~0xffff; + bootVal &= 0xffff; + mppVal |= bootVal; + } + + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); + } + + /* Update SSCG configuration register*/ + if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6282A_BP_ID || + mvBoardIdGet() == DB_88F6192A_BP_ID || + mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID || + mvBoardIdGet() == DB_88F6280A_BP_ID) + MV_REG_WRITE(0x100d8, 0x53); + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlMppRegGet - return reg address of mpp group +* +* DESCRIPTION: +* +* INPUT: +* mppGroup - MPP group. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 - Register address. +* +*******************************************************************************/ +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) +{ + MV_U32 ret; + + switch(mppGroup){ + case (0): ret = MPP_CONTROL_REG0; + break; + case (1): ret = MPP_CONTROL_REG1; + break; + case (2): ret = MPP_CONTROL_REG2; + break; + case (3): ret = MPP_CONTROL_REG3; + break; + case (4): ret = MPP_CONTROL_REG4; + break; + case (5): ret = MPP_CONTROL_REG5; + break; + case (6): ret = MPP_CONTROL_REG6; + break; + default: ret = MPP_CONTROL_REG0; + break; + } + return ret; +} +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxIfGet(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6280_DEV_ID: + return MV_PEX_MAX_IF_6280; + break; + case MV_6282_DEV_ID: + return MV_PEX_MAX_IF_6282; + break; + default: + return MV_PEX_MAX_IF; + break; + } +} +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +/******************************************************************************* +* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of etherent port. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of etherent port. +* +*******************************************************************************/ +MV_U32 mvCtrlEthMaxPortGet(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_ETH_MAX_PORTS; + break; + case MV_6282_DEV_ID: + return MV_6282_ETH_MAX_PORTS; + break; + case MV_6280_DEV_ID: + return MV_6280_ETH_MAX_PORTS; + break; + case MV_6192_DEV_ID: + return MV_6192_ETH_MAX_PORTS; + break; + case MV_6190_DEV_ID: + return MV_6190_ETH_MAX_PORTS; + break; + case MV_6180_DEV_ID: + return MV_6180_ETH_MAX_PORTS; + break; + } + return 0; + +} +#endif + +#if defined(MV_INCLUDE_XOR) +/******************************************************************************* +* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. +* +* DESCRIPTION: +* This function returns Marvell controller number of XOR channels. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of XOR channels. +* +*******************************************************************************/ +MV_U32 mvCtrlXorMaxChanGet(MV_VOID) +{ + return MV_XOR_MAX_CHAN; +} +#endif + +#if defined(MV_INCLUDE_USB) +/******************************************************************************* +* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* returns number of Marvell USB controllers. +* +*******************************************************************************/ +MV_U32 mvCtrlUsbMaxGet(void) +{ + return MV_USB_MAX_PORTS; +} +#endif + + +#if defined(MV_INCLUDE_NAND) +/******************************************************************************* +* mvCtrlNandSupport - Return if this controller has integrated NAND flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if NAND is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlNandSupport(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_NAND; + break; + case MV_6282_DEV_ID: + return MV_6282_NAND; + break; + case MV_6280_DEV_ID: + return MV_6280_NAND; + break; + case MV_6192_DEV_ID: + return MV_6192_NAND; + break; + case MV_6190_DEV_ID: + return MV_6190_NAND; + break; + case MV_6180_DEV_ID: + return MV_6180_NAND; + break; + } + return 0; + +} +#endif + +#if defined(MV_INCLUDE_SDIO) +/******************************************************************************* +* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if SDIO is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlSdioSupport(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_SDIO; + break; + case MV_6282_DEV_ID: + return MV_6282_SDIO; + break; + case MV_6280_DEV_ID: + return MV_6280_SDIO; + break; + case MV_6192_DEV_ID: + return MV_6192_SDIO; + break; + case MV_6190_DEV_ID: + return MV_6190_SDIO; + break; + case MV_6180_DEV_ID: + return MV_6180_SDIO; + break; + } + return 0; + +} +#endif + +#if defined(MV_INCLUDE_TS) +/******************************************************************************* +* mvCtrlTsSupport - Return if this controller has integrated TS flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if TS is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlTsSupport(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_TS; + break; + case MV_6282_DEV_ID: + return MV_6282_TS; + break; + case MV_6280_DEV_ID: + return MV_6280_TS; + break; + case MV_6192_DEV_ID: + return MV_6192_TS; + break; + case MV_6190_DEV_ID: + return MV_6190_TS; + break; + case MV_6180_DEV_ID: + return MV_6180_TS; + break; + } + return 0; +} +#endif + +#if defined(MV_INCLUDE_AUDIO) +/******************************************************************************* +* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if AUDIO is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlAudioSupport(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_AUDIO; + break; + case MV_6282_DEV_ID: + return MV_6282_AUDIO; + break; + case MV_6280_DEV_ID: + return MV_6280_AUDIO; + break; + case MV_6192_DEV_ID: + return MV_6192_AUDIO; + break; + case MV_6190_DEV_ID: + return MV_6190_AUDIO; + break; + case MV_6180_DEV_ID: + return MV_6180_AUDIO; + break; + } + return 0; + +} +#endif + +#if defined(MV_INCLUDE_TDM) +/******************************************************************************* +* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if TDM is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlTdmSupport(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_TDM; + break; + case MV_6282_DEV_ID: + return MV_6282_TDM; + break; + case MV_6280_DEV_ID: + return MV_6280_TDM; + break; + case MV_6192_DEV_ID: + return MV_6192_TDM; + break; + case MV_6190_DEV_ID: + return MV_6190_TDM; + break; + case MV_6180_DEV_ID: + return MV_6180_TDM; + break; + } + return 0; + +} +#endif + +/******************************************************************************* +* mvCtrlModelGet - Get Marvell controller device model (Id) +* +* DESCRIPTION: +* This function returns 16bit describing the device model (ID) as defined +* in PCI Device and Vendor ID configuration register offset 0x0. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit desscribing Marvell controller ID +* +*******************************************************************************/ +MV_U16 mvCtrlModelGet(MV_VOID) +{ + MV_U32 devId; + MV_U16 model = 0; + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Check pex power state */ + MV_U32 pexPower; + pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); +#endif + devId = MV_REG_READ(CHIP_BOND_REG); + devId &= PCKG_OPT_MASK; + + switch(devId){ + case 2: + if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) + == MV_6281_DEV_ID) + model = MV_6281_DEV_ID; + else + model = MV_6282_DEV_ID; + break; + case 1: + if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) + == MV_6190_DEV_ID) + model = MV_6190_DEV_ID; + else + model = MV_6192_DEV_ID; + break; + case 0: + if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) + == MV_6280_DEV_ID) + model = MV_6280_DEV_ID; + else + model = MV_6180_DEV_ID; + break; + } + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Return to power off state */ + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); +#endif + + return model; +} +/******************************************************************************* +* mvCtrlRevGet - Get Marvell controller device revision number +* +* DESCRIPTION: +* This function returns 8bit describing the device revision as defined +* in PCI Express Class Code and Revision ID Register. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 8bit desscribing Marvell controller revision number +* +*******************************************************************************/ +MV_U8 mvCtrlRevGet(MV_VOID) +{ + MV_U8 revNum; +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Check pex power state */ + MV_U32 pexPower; + pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); +#endif + revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Return to power off state */ + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); +#endif + return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); +} + +/******************************************************************************* +* mvCtrlNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlNameGet(char *pNameBuff) +{ + mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, + mvCtrlModelGet(), mvCtrlRevGet()); + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision +* +* DESCRIPTION: +* This function returns 32bit value describing both Device ID and Revision +* as defined in PCI Express Device and Vendor ID Register and device revision +* as defined in PCI Express Class Code and Revision ID Register. + +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing both controller device ID and revision number +* +*******************************************************************************/ +MV_U32 mvCtrlModelRevGet(MV_VOID) +{ + return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); +} + +/******************************************************************************* +* mvCtrlModelRevNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ + +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) +{ + + switch (mvCtrlModelRevGet()) + { + case MV_6281_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); + break; + case MV_6192_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); + break; + case MV_6180_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); + break; + case MV_6190_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); + break; + case MV_6281_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); + break; + case MV_6192_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); + break; + case MV_6180_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); + break; + case MV_6190_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); + break; + case MV_6282_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6282_A0_NAME); + break; + default: + mvCtrlNameGet(pNameBuff); + break; + } + + return MV_OK; +} + + +/******************************************************************************* +* ctrlWinOverlapTest - Test address windows for overlaping. +* +* DESCRIPTION: +* This function checks the given two address windows for overlaping. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* +* MV_TRUE if address window overlaps, MV_FALSE otherwise. +*******************************************************************************/ +MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + /* check if we have overflow than 4G*/ + if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| + ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) + { + return MV_TRUE; + } + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size-1; + winTop2 = winBase2 + pAddrWin2->size-1; + + + if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || + ((winBase1 <= winBase2) && (winBase2 <= winTop1))) + { + return MV_TRUE; + } + else + { + return MV_FALSE; + } +} + +/******************************************************************************* +* ctrlWinWithinWinTest - Test address windows for overlaping. +* +* DESCRIPTION: +* This function checks the given win1 boundries is within +* win2 boundries. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* +* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. +*******************************************************************************/ +MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size -1; + winTop2 = winBase2 + pAddrWin2->size -1; + + if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || + ((winTop1 >= winBase2) && (winTop1 <= winTop2))) + { + return MV_TRUE; + } + else + { + return MV_FALSE; + } +} + +static const char* cntrlName[] = TARGETS_NAME_ARRAY; + +/******************************************************************************* +* mvCtrlTargetNameGet - Get Marvell controller target name +* +* DESCRIPTION: +* This function convert the trget enumeration to string. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Target name (const MV_8 *) +*******************************************************************************/ +const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) +{ + + if (target >= MAX_TARGETS) + { + return "target unknown"; + } + + return cntrlName[target]; +} + +/******************************************************************************* +* mvCtrlAddrDecShow - Print the Controller units address decode map. +* +* DESCRIPTION: +* This function the Controller units address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCtrlAddrDecShow(MV_VOID) +{ + mvCpuIfAddDecShow(); + mvAhbToMbusAddDecShow(); +#if defined(MV_INCLUDE_PEX) + mvPexAddrDecShow(); +#endif +#if defined(MV_INCLUDE_USB) + mvUsbAddrDecShow(); +#endif +#if defined(MV_INCLUDE_GIG_ETH) + mvEthAddrDecShow(); +#endif +#if defined(MV_INCLUDE_XOR) + mvXorAddrDecShow(); +#endif +#if defined(MV_INCLUDE_SATA) + mvSataAddrDecShow(); +#endif +#if defined(MV_INCLUDE_AUDIO) + mvAudioAddrDecShow(); +#endif +#if defined(MV_INCLUDE_TS) + mvTsuAddrDecShow(); +#endif + if(mvCtrlModelGet() == MV_6282_DEV_ID) + mvLcdAddrDecShow(); +} + +/******************************************************************************* +* ctrlSizeToReg - Extract size value for register assignment. +* +* DESCRIPTION: +* Address decode size parameter must be programed from LSB to MSB as +* sequence of 1's followed by sequence of 0's. The number of 1's +* specifies the size of the window in 64 KB granularity (e.g. a +* value of 0x00ff specifies 256x64k = 16 MB). +* This function extract the size value from the size parameter according +* to given aligment paramter. For example for size 0x1000000 (16MB) and +* aligment 0x10000 (64KB) the function will return 0x00FF. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size register value correspond to size parameter. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) +{ + MV_U32 retVal; + + /* Check size parameter alignment */ + if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); + return -1; + } + + /* Take out the "alignment" portion out of the size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + /* and size is 0x1000000 (16MB) for example */ + while(alignment & 1) /* Check that alignmet LSB is set */ + { + size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ + alignment = (alignment >> 1); + } + + /* If after the alignment first '0' was met we still have '1' in */ + /* it then aligment is invalid (not power of 2) */ + if (alignment) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", + (MV_U32)alignment)); + return -1; + } + + /* Now the size is shifted right according to aligment: 0x0100 */ + size--; /* Now the size is a sequance of '1': 0x00ff */ + + retVal = size ; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + while(size & 1) /* Check that LSB is set */ + { + size = (size >> 1); /* If LSB is set, move one bit to the right */ + } + + if (size) /* Sequance of 1's is over. Check that we have no other 1's */ + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", + size)); + return -1; + } + + return retVal; + +} + +/******************************************************************************* +* ctrlRegToSize - Extract size value from register value. +* +* DESCRIPTION: +* This function extract a size value from the register size parameter +* according to given aligment paramter. For example for register size +* value 0xff and aligment 0x10000 the function will return 0x01000000. +* +* INPUT: +* regSize - Size as in register format. See ctrlSizeToReg. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) +{ + MV_U32 temp; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ + + while(temp & 1) /* Check that LSB is set */ + { + temp = (temp >> 1); /* If LSB is set, move one bit to the right */ + } + + if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ + { + DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", + regSize)); + return -1; + } + + + /* Check that aligment is a power of two */ + temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ + + while(temp & 1) /* Check that alignmet LSB is set */ + { + temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ + } + + /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ + /* then 'temp' is invalid (not power of 2) */ + if (temp) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", + alignment)); + return -1; + } + + regSize++; /* Now the size is 0x0100 */ + + /* Add in the "alignment" portion to the register size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + + while(alignment & 1) /* Check that alignmet LSB is set */ + { + regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ + alignment = (alignment >> 1); + } + + return regSize; +} + + +/******************************************************************************* +* ctrlSizeRegRoundUp - Round up given size +* +* DESCRIPTION: +* This function round up a given size to a size that fits the +* restrictions of size format given an aligment parameter. +* to given aligment paramter. For example for size parameter 0xa1000 and +* aligment 0x1000 the function will return 0xFF000. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size value correspond to size in register. +*******************************************************************************/ +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) +{ + MV_U32 msbBit = 0; + MV_U32 retSize; + + /* Check if size parameter is already comply with restriction */ + if (!(-1 == ctrlSizeToReg(size, alignment))) + { + return size; + } + + while(size) + { + size = (size >> 1); + msbBit++; + } + + retSize = (1 << msbBit); + + if (retSize < alignment) + { + return alignment; + } + else + { + return retSize; + } +} +/******************************************************************************* +* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button +* was pressed and clear counter +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: number of milliseconds the reset button was pressed +*******************************************************************************/ +MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) +{ + static volatile MV_U32 Count = 0; + + if(!Count) { + Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); + Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); + /* clear counter for next boot */ + MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); + } + + DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); + + return Count; +} + +MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) +{ + MV_U32 satr = 0; + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); + if(mvCtrlModelGet() == MV_6180_DEV_ID || mvCtrlModelGet() == MV_6280_DEV_ID) + { + if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) + return MV_TRUE; + else + return MV_FALSE; + } + satr = satr & MSAR_BOOT_MODE_MASK; + if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) + return MV_TRUE; + else + return MV_FALSE; +} + +MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) +{ + MV_U32 satr = 0; + if(mvCtrlModelGet() == MV_6180_DEV_ID || mvCtrlModelGet() == MV_6280_DEV_ID) + return MV_FALSE; + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); + satr = satr & MSAR_BOOT_MODE_MASK; + + if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) + return MV_TRUE; + else + return MV_FALSE; +} + +MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) +{ + MV_U32 satr = 0; + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); + if(mvCtrlModelGet() == MV_6180_DEV_ID || mvCtrlModelGet() == MV_6280_DEV_ID) + { + if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) + return MV_TRUE; + else + return MV_FALSE; + } + satr = satr & MSAR_BOOT_MODE_MASK; + if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) + return MV_TRUE; + else + return MV_FALSE; +} + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +/******************************************************************************* +* mvCtrlPwrSaveOn - Set Power save mode +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrSaveOn(MV_VOID) +{ + unsigned long old,temp; + /* Disable int */ + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + + /* Set SoC in power save */ + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); + /* Wait for int */ + __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); + + /* Enabled int */ + __asm__ __volatile__("msr cpsr_c, %0" + : + : "r" (old) + : "memory"); +} + + + +/******************************************************************************* +* mvCtrlPwrSaveOff - Go out of power save mode +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrSaveOff(MV_VOID) +{ + unsigned long old,temp; + /* Disable int */ + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + + /* Set SoC in power save */ + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); + /* Wait for int */ + __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); + + /* Enabled int */ + __asm__ __volatile__("msr cpsr_c, %0" + : + : "r" (old) + : "memory"); +} + +/******************************************************************************* +* mvCtrlPwrClckSet - Set Power State for specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK(index)); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_TS) + case TS_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_TDM) + case TDM_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + } + break; +#endif + + default: + + break; + + } +} + +/******************************************************************************* +* mvCtrlPwrClckGet - Get Power State of specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); + MV_BOOL state = MV_TRUE; + + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if ((reg & PMC_PEXSTOPCLOCK_MASK(index)) == PMC_PEXSTOPCLOCK_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_TS) + case TS_UNIT_ID: + if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_TDM) + case TDM_UNIT_ID: + if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif + + default: + state = MV_TRUE; + break; + } + + + return state; +} +/******************************************************************************* +* mvCtrlPwrMemSet - Set Power State for memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK(index)); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); + } + break; +#endif + default: + + break; + + } +} + +/******************************************************************************* +* mvCtrlPwrMemGet - Get Power State of memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); + MV_BOOL state = MV_TRUE; + + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if ((reg & PMC_PEXSTOPMEM_MASK(index)) == PMC_PEXSTOPMEM_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif + + default: + state = MV_TRUE; + break; + } + + + return state; +} +#else +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} +#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + + +/******************************************************************************* +* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_VOID mvMPPConfigToSPI(MV_VOID) +{ + MV_U32 mppVal = 0; + MV_U32 bootVal = 0; + + if(!mvCtrlIsBootFromSPIUseNAND()) + return; + mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ + bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); + bootVal &= 0xffff000f; + mppVal |= bootVal; + + MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); +} + + +/******************************************************************************* +* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_VOID mvMPPConfigToDefault(MV_VOID) +{ + MV_U32 mppVal = 0; + MV_U32 bootVal = 0; + + if(!mvCtrlIsBootFromSPIUseNAND()) + return; + mppVal = mvBoardMppGet(0); + bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); + mppVal &= ~0xffff000f; + bootVal &= 0xffff000f; + mppVal |= bootVal; + + MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); +} + + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvLib.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvLib.h new file mode 100644 index 0000000..6e2e813 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvLib.h @@ -0,0 +1,185 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvLibh +#define __INCmvCtrlEnvLibh + +/* includes */ +#include "mvSysHwConfig.h" +#include "mvCommon.h" +#include "mvTypes.h" +#include "mvOs.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + + +/* typedefs */ + +/* This enumerator describes the possible HW cache coherency policies the */ +/* controllers supports. */ +typedef enum _mvCachePolicy +{ + NO_COHERENCY, /* No HW cache coherency support */ + WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ + WB_COHERENCY /* HW cache coherency supported in Write Back policy */ +}MV_CACHE_POLICY; + + +/* The swapping is referred to a 64-bit words (as this is the controller */ +/* internal data path width). This enumerator describes the possible */ +/* data swap types. Below is an example of the data 0x0011223344556677 */ +typedef enum _mvSwapType +{ + MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ + MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ + MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ + MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ + SWAP_TYPE_MAX /* Delimiter for this enumerator */ +}MV_SWAP_TYPE; + +/* This structure describes access rights for Access protection windows */ +/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ +/* Note that the permission enumerator coresponds to its register format. */ +/* For example, Read only premission is presented as "1" in register field. */ +typedef enum _mvAccessRights +{ + NO_ACCESS_ALLOWED = 0, /* No access allowed */ + READ_ONLY = 1, /* Read only permission */ + ACC_RESERVED = 2, /* Reserved access right */ + FULL_ACCESS = 3, /* Read and Write permission */ + MAX_ACC_RIGHTS +}MV_ACCESS_RIGHTS; + + +/* mcspLib.h API list */ + +MV_STATUS mvCtrlEnvInit(MV_VOID); +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); + +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCtrlPexMaxIfGet(MV_VOID); +#else +#define mvCtrlPexMaxIfGet() (0) +#endif + +#define mvCtrlPciIfMaxIfGet() (0) + +#if defined(MV_INCLUDE_GIG_ETH) +MV_U32 mvCtrlEthMaxPortGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_XOR) +MV_U32 mvCtrlXorMaxChanGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_USB) +MV_U32 mvCtrlUsbMaxGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_NAND) +MV_U32 mvCtrlNandSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_SDIO) +MV_U32 mvCtrlSdioSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_TS) +MV_U32 mvCtrlTsSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_AUDIO) +MV_U32 mvCtrlAudioSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_TDM) +MV_U32 mvCtrlTdmSupport(MV_VOID); +#endif + +MV_U16 mvCtrlModelGet(MV_VOID); +MV_U8 mvCtrlRevGet(MV_VOID); +MV_STATUS mvCtrlNameGet(char *pNameBuff); +MV_U32 mvCtrlModelRevGet(MV_VOID); +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); +MV_VOID mvCtrlAddrDecShow(MV_VOID); +const MV_8* mvCtrlTargetNameGet(MV_TARGET target); +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); +MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); +MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); +MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); + +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); +MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); +MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +MV_VOID mvCtrlPwrSaveOn(MV_VOID); +MV_VOID mvCtrlPwrSaveOff(MV_VOID); +#endif +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); +MV_VOID mvMPPConfigToSPI(MV_VOID); +MV_VOID mvMPPConfigToDefault(MV_VOID); + + +#endif /* __INCmvCtrlEnvLibh */ diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvRegs.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvRegs.h new file mode 100644 index 0000000..833e0c1 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvRegs.h @@ -0,0 +1,432 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvRegsh +#define __INCmvCtrlEnvRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PCI0_MEM0 PEX0_MEM +#define PEX1_MEM0 PEX1_MEM +#define PCI1_MEM0 PEX1_MEM + +/* Controller revision info */ +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCCRIR_REVID_OFFS 0 /* Revision ID */ +#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) + +/* Controler environment registers offsets */ + +/* Power Managment Control */ +#define POWER_MNG_MEM_CTRL_REG 0x20118 + +#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) +#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) + +#define PMC_PEXSTOPMEM_OFFS(port) (1+(port*11)) +#define PMC_PEXSTOPMEM_MASK(port) (1 << PMC_PEXSTOPMEM_OFFS(port)) +#define PMC_PEXSTOPMEM_EN(port) (0 << PMC_PEXSTOPMEM_OFFS(port)) +#define PMC_PEXSTOPMEM_STOP(port) (1 << PMC_PEXSTOPMEM_OFFS(port)) + +#define PMC_USBSTOPMEM_OFFS 2 +#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) +#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) +#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) + +#define PMC_DUNITSTOPMEM_OFFS 3 +#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) + +#define PMC_RUNITSTOPMEM_OFFS 4 +#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) +#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) +#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) + +#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) +#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) + +#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) +#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) + +#define PMC_SESTOPMEM_OFFS 8 +#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) +#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) +#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) + +#define PMC_AUDIOSTOPMEM_OFFS 9 +#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) +#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) +#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) + +#define POWER_MNG_CTRL_REG 0x2011C + +#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) +#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) + +#define PMC_PEXPHYSTOPCLOCK_OFFS 1 +#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) +#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) +#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) + +#define PMC_PEXSTOPCLOCK_OFFS(port) (2+(port*16)) +#define PMC_PEXSTOPCLOCK_MASK(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) +#define PMC_PEXSTOPCLOCK_EN(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) +#define PMC_PEXSTOPCLOCK_STOP(port) (0 << PMC_PEXSTOPCLOCK_OFFS(port)) + +#define PMC_USBSTOPCLOCK_OFFS 3 +#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) +#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) +#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) + +#define PMC_SDIOSTOPCLOCK_OFFS 4 +#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) + +#define PMC_TSSTOPCLOCK_OFFS 5 +#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) +#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) +#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) + +#define PMC_AUDIOSTOPCLOCK_OFFS 9 +#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) +#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) +#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) + +#define PMC_POWERSAVE_OFFS 11 +#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) +#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) +#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) + +#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) +#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) +#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) +#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) + +#define PMC_SESTOPCLOCK_OFFS 17 +#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) +#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) +#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) + +#define PMC_TDMSTOPCLOCK_OFFS 20 +#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) + + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10008 +#define MPP_CONTROL_REG3 0x1000C +#define MPP_CONTROL_REG4 0x10010 +#define MPP_CONTROL_REG5 0x10014 +#define MPP_CONTROL_REG6 0x10018 +#define NAND_AUDIO_PIN_MUX 0x1002C +#define NAND_AUDIO_PIN_MUX_SELECT_AUDIO_MODE 0x1 +#define MPP_SAMPLE_AT_RESET 0x10030 +#define CHIP_BOND_REG 0x10034 +#define SYSRST_LENGTH_COUNTER_REG 0x10050 +#define SLCR_COUNT_OFFS 0 +#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) +#define SLCR_CLR_OFFS 31 +#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) +#define PCKG_OPT_MASK 0x3 +#define MPP_OUTPUT_DRIVE_REG 0x100E0 +#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 +#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) +#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) +#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 +#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) +#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) +#define MPP_1_8_RGMII_OUTPUT_DRIVE 0x1 +#define MPP_RGMII_OUTPUT_DRIVE_OFFS(grp) ((grp == 0) ? 7 : 15) + +#define MSAR_BOOT_MODE_OFFS 12 +#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) + +#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ + ((X & 0x2) << 1)) +#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 +#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 + +#define MSAR_TCLCK_OFFS 21 +#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) + + +#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ + ((X & 0x18) >> 1)) + +#define MSAR_CPUCLCK_OFFS_6180 2 +#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) + +#define MSAR_DDRCLCK_RTIO_OFFS 5 +#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) + +#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) + +#ifndef MV_ASMLANGUAGE +/* CPU clock for 6281,6192,6282 0->Resereved */ +#define MV_CPU_CLCK_TBL { 0, 400000000, 0, 0, \ + 600000000, 0, 800000000, 1000000000, \ + 0, 1200000000, 0, 0, \ + 1500000000, 1600000000, 1800000000, 2000000000} + +/* DDR clock RATIO for 6281,6192,6282 {0,0}->Reserved */ +#define MV_DDR_CLCK_RTIO_TBL {\ + {1, 1}, {0, 0}, {2, 1}, {5, 2}, \ + {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ + {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ + {0, 0}, {0, 0}, {0, 0}, {0, 0} \ +} + +/* L2 clock RATIO for 6281,6192,6282 {1,1}->Reserved */ +#define MV_L2_CLCK_RTIO_TBL {\ + {1, 1}, {2, 1}, {2, 1}, {3, 1}, \ + {0, 0}, {4, 1}, {0, 0}, {0, 0} \ +} + +/* 6180 have different clk reset sampling */ +/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ +#define MV_CPU6180_DDR_L2_CLCK_TBL { \ + {0, 0, 0 },\ + {0, 0, 0 },\ + {0, 0, 0 },\ + {0, 0, 0 },\ + {0, 0, 0 },\ + {600000000, 200000000, 300000000 },\ + {800000000, 200000000, 400000000 },\ + {1000000000, 200000000, 500000000 }\ +} + + + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + +#define MV_TARGET_IS_PEX1(target) \ + ((target >= PEX1_MEM) && (target <= PEX1_IO)) + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 + +#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ + (mvCtrlModelGet() == MV_6180_DEV_ID || mvCtrlModelGet() == MV_6280_DEV_ID)? MSAR_BOOT_MODE_6180 \ + (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ + & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) + + +#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ + sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID || mvCtrlModelGet() == MV_6280_DEV_ID)? \ + MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ + ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ + >> MSAR_BOOT_MODE_OFFS)]:(target)) + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ + +#define BOOT_TARGETS_NAME_ARRAY { \ + TBL_TERM, \ + TBL_TERM, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + TBL_TERM \ +} + +#define BOOT_TARGETS_NAME_ARRAY_6180 { \ + TBL_TERM, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + TBL_TERM \ +} + + +/* For old competability */ +#define DEVICE_CS0 NFLASH_CS +#define DEVICE_CS1 SPI_CS +#define DEVICE_CS2 BOOT_ROM_CS +#define DEVICE_CS3 DEV_BOOCS +#define MV_BOOTDEVICE_INDEX 0 + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO +#define PCI_IF1_MEM0 PEX1_MEM +#define PCI_IF1_IO PEX1_IO + + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + PEX1_TARGET_ID = 4 , /* Port 4 -> PCI Express1 */ + CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ + SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ + MAX_TARGETS_ID +}MV_TARGET_ID; + + +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + SDRAM_CS2, /* SDRAM chip select 2 */ + SDRAM_CS3, /* SDRAM chip select 3 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + PEX1_MEM, /* PCI Express 1 Memory */ + PEX1_IO, /* PCI Express 1 IO */ + INTER_REGS, /* Internal registers */ + NFLASH_CS, /* NFLASH_CS */ + SPI_CS, /* SPI_CS */ + BOOT_ROM_CS, /* BOOT_ROM_CS */ + DEV_BOOCS, /* DEV_BOOCS */ + CRYPT_ENG, /* Crypto Engine */ +#ifdef MV_INCLUDE_SAGE + SAGE_UNIT, /* SAGE Unit */ +#endif + MAX_TARGETS + +}MV_TARGET; + +#define TARGETS_DEF_ARRAY { \ + {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ + {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ + {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ + {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ + {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ + {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ + {0xD8, PEX1_TARGET_ID }, /* PEX1_MEM */ \ + {0xD0, PEX1_TARGET_ID }, /* PEX1_IO */ \ + {0xFF, 0xFF }, /* INTER_REGS */ \ + {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ + {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ + {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ + {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ + {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ + {0x00, SAGE_TARGET_ID } \ +} + + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS2 */ \ + "SDRAM_CS3", /* SDRAM_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "PEX1_MEM", /* PEX1_MEM */ \ + "PEX1_IO", /* PEX1_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "NFLASH_CS", /* NFLASH_CS */ \ + "SPI_CS", /* SPI_CS */ \ + "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ + "DEV_BOOTCS", /* DEV_BOOCS */ \ + "CRYPT_ENG", /* CRYPT_ENG */ \ + "SAGE_UNIT" /* SAGE_UNIT */ \ +} +#endif /* MV_ASMLANGUAGE */ + + +#endif diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvSpec.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvSpec.h new file mode 100644 index 0000000..bc644e1 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/mvCtrlEnvSpec.h @@ -0,0 +1,284 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvSpech +#define __INCmvCtrlEnvSpech + +#include "mvDeviceId.h" +#include "mvSysHwConfig.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + + +/* units base and port numbers */ +#ifdef MV_ASMLANGUAGE +#define XOR_UNIT_BASE(unit) 0x60800 +#else +#define MV_XOR_REG_BASE 0x60000 +#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) +#endif + +#define TDM_REG_BASE 0xD0000 +#define USB_REG_BASE(dev) 0x50000 +#define AUDIO_REG_BASE(unit) 0xA0000 +#define SATA_REG_BASE 0x80000 +#define MV_CESA_REG_BASE 0x3D000 +#define MV_CESA_TDMA_REG_BASE 0x30000 +#define MV_SDIO_REG_BASE 0x90000 +#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) +#define DRAM_BASE 0x0 +#define CNTMR_BASE 0x20300 +#define TWSI_SLAVE_BASE(chanNum) (0x11000 + (0x100 * (chanNum))) +#define PEX_IF_BASE(pexIf) (0x40000 + (0x4000 * pexIf)) +#define MPP_REG_BASE 0x10000 +#define TSU_GLOBAL_REG_BASE 0xB4000 +#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 +#define LCD_UNIT_BASE 0xCF000 + +#define INTER_REGS_SIZE _1M +/* This define describes the TWSI interrupt bit and location */ +#define TWSI_CPU_MAIN_INT_CAUSE_REG(chanNum) ((chanNum)?0x20210:0x20200) +#define TWSI_CPU_MAIN_INT_BIT(chanNum) ((chanNum)?(1<<0):(1<<29)) +#define TWSI_SPEED 100000 + +#define MV_GPP_MAX_PINS 64 +#define MV_GPP_MAX_GROUP 2 +#define MV_CNTMR_MAX_COUNTER 2 +#define MV_UART_MAX_CHAN 2 +#define MV_XOR_MAX_UNIT 2 +#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ +#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ +#define MV_SATA_MAX_CHAN 2 + +#define MV_6281_MPP_MAX_MODULE 2 +#define MV_6282_MPP_MAX_MODULE 2 +#define MV_6280_MPP_MAX_MODULE 1 +#define MV_6192_MPP_MAX_MODULE 1 +#define MV_6190_MPP_MAX_MODULE 1 +#define MV_6180_MPP_MAX_MODULE 2 +#define MV_6281_MPP_MAX_GROUP 7 +#define MV_6282_MPP_MAX_GROUP 7 +#define MV_6280_MPP_MAX_GROUP 3 +#define MV_6192_MPP_MAX_GROUP 4 +#define MV_6190_MPP_MAX_GROUP 4 +#define MV_6180_MPP_MAX_GROUP 3 + +#define MV_DRAM_MAX_CS 4 + +/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ +#define MV_PCI_MAX_IF 0 +#define MV_PCI_START_IF 0 + +/* This define describes the maximum number of supported PEX Interfaces */ +#define MV_INCLUDE_PEX0 +#define MV_DISABLE_PEX_DEVICE_BAR +#define MV_PEX_MAX_IF_6280 0 +#define MV_PEX_MAX_IF_6282 2 +#define MV_PEX_START_IF MV_PCI_MAX_IF +#define MV_PEX_MAX_IF 1 + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define MV_ETH_MAX_PORTS 2 +#define MV_6281_ETH_MAX_PORTS 2 +#define MV_6282_ETH_MAX_PORTS 2 +#define MV_6280_ETH_MAX_PORTS 1 +#define MV_6192_ETH_MAX_PORTS 2 +#define MV_6190_ETH_MAX_PORTS 1 +#define MV_6180_ETH_MAX_PORTS 1 + +#define MV_IDMA_MAX_CHAN 0 + +#define MV_USB_MAX_PORTS 1 + +#define MV_USB_VERSION 1 + + +#define MV_6281_NAND 1 +#define MV_6282_NAND 1 +#define MV_6280_NAND 1 +#define MV_6192_NAND 1 +#define MV_6190_NAND 1 +#define MV_6180_NAND 0 + +#define MV_6281_SDIO 1 +#define MV_6282_SDIO 1 +#define MV_6280_SDIO 0 +#define MV_6192_SDIO 1 +#define MV_6190_SDIO 1 +#define MV_6180_SDIO 1 + +#define MV_6281_TS 1 +#define MV_6282_TS 1 +#define MV_6280_TS 0 +#define MV_6192_TS 1 +#define MV_6190_TS 0 +#define MV_6180_TS 0 + +#define MV_6281_AUDIO 1 +#define MV_6282_AUDIO 1 +#define MV_6280_AUDIO 0 +#define MV_6192_AUDIO 1 +#define MV_6190_AUDIO 0 +#define MV_6180_AUDIO 1 + +#define MV_6281_TDM 1 +#define MV_6282_TDM 1 +#define MV_6280_TDM 0 +#define MV_6192_TDM 1 +#define MV_6190_TDM 0 +#define MV_6180_TDM 0 + +#define MV_DEVICE_MAX_CS 4 + +/* Others */ +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_IO(pciIf) (pciIf?PEX1_IO:PEX0_IO) +#define PCI_MEM(pciIf, memNum) (pciIf?PEX1_MEM0:PEX0_MEM0) + +/* CESA version #2: One channel, 2KB SRAM, TDMA */ +#if defined(MV_CESA_CHAIN_MODE_SUPPORT) + #define MV_CESA_VERSION 3 +#else +#define MV_CESA_VERSION 2 +#endif +#define MV_CESA_SRAM_SIZE 2*1024 +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_VERSION 4 +#define MV_ETH_MAX_RXQ 8 +#define MV_ETH_MAX_TXQ 8 +#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } +/* This define describes the the support of USB */ +#define MV_USB_VERSION 1 + +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 + +#define MPP_GROUP_1_TYPE {\ + {0, 0, 0}, /* Reserved for AUTO */ \ + {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ + {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ + {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ + {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ + {0x11110000, 0x11111111, 0x0001}, /* TS */ \ + {0x33330000, 0x33333333, 0x3333}, /* MII */\ + {0, 0, 0}, /* N_A */\ + {0xBBBBBBBB, 0xBBBBBBBB, 0xBBBB} /* LCD */\ +} + +#define MPP_GROUP_2_TYPE {\ + {0, 0, 0}, /* Reserved for AUTO */ \ + {0x22220000, 0x22222222, 0x22}, /* TDM */ \ + {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ + {0, 0, 0}, /* N_A */ \ + {0, 0, 0}, /* N_A */ \ + {0x11110000, 0x11111111, 0x01}, /* TS */ \ + {0, 0, 0}, /* N_A */ \ + {0, 0, 0}, /* N_A */ \ + {0xBBBBBBBB, 0xBBBBBBBB, 0xBB} /* LCD */ \ +} + +#ifndef MV_ASMLANGUAGE + +/* This enumerator defines the Marvell Units ID */ +typedef enum _mvUnitId +{ + DRAM_UNIT_ID, + PEX_UNIT_ID, + ETH_GIG_UNIT_ID, + USB_UNIT_ID, + IDMA_UNIT_ID, + XOR_UNIT_ID, + SATA_UNIT_ID, + TDM_UNIT_ID, + UART_UNIT_ID, + CESA_UNIT_ID, + SPI_UNIT_ID, + AUDIO_UNIT_ID, + SDIO_UNIT_ID, + TS_UNIT_ID, + LCD_UNIT_ID, + MAX_UNITS_ID + +}MV_UNIT_ID; + +#endif + +#endif /* __INCmvCtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvAhbToMbus.c b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvAhbToMbus.c new file mode 100644 index 0000000..e3f4158 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvAhbToMbus.c @@ -0,0 +1,1093 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#undef MV_DEBUG +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* typedefs */ + + +/* CPU address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _ahbToMbusRemapRegOffs +{ + MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ + MV_U32 highRegOffs; /* High 32 bit remap register offset */ +}AHB_TO_MBUS_REMAP_REG_OFFS; + +/* locals */ +static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, + AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); + +/******************************************************************************* +* mvAhbToMbusWinNum - Get Ahb To Mbus number of windows. +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Num of win for each device. +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinNum(MV_VOID) +{ + if (mvCtrlModelGet() == MV_6282_DEV_ID) + return MV_6282_MAX_AHB_TO_MBUS_WINS; + else + return MAX_AHB_TO_MBUS_WINS; +} +/******************************************************************************* +* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK laways. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusInit(void) +{ + return MV_OK; + +} + +/******************************************************************************* +* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* This function sets +* address window, also known as address decode window. +* A new address decode window is set for specified winNum address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the winNum window, allowing CPU to access +* the winNum window. +* +* INPUT: +* winNum - Windows number. +* pAddrDecWin - CPU winNum window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU winNum window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttribs; + MV_DEC_REGS decRegs; + + /* Parameter checking */ + if (winNum >= mvAhbToMbusWinNum()) + { + mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + + /* read base register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + } + else + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read control register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + } + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + /* enable\Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + decRegs.sizeReg |= ATMWCR_WIN_ENABLE; + } + else + { + decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; + decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; + decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; + +#if !defined(MV_RUN_FROM_FLASH) + /* To be on the safe side we disable the window before writing the */ + /* new values. */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + mvAhbToMbusWinEnable(winNum,MV_FALSE); + } +#endif + + /* 3) Write to address decode Base Address Register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); + } + else + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); + } + + + /* Internal register space have no size */ + /* register. Do not perform size register assigment for those targets */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + /* Write to address decode Size Register */ + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* Get the CPU peripheral winNum address window. +* +* INPUT: +* winNum - Peripheral winNum enumerator +* +* OUTPUT: +* pAddrDecWin - CPU winNum window information data structure. +* +* RETURN: +* MV_OK if winNum exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + + /* Parameter checking */ + if (winNum >= mvAhbToMbusWinNum()) + { + mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + + /* Internal register space size have no size register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + } + else + { + decRegs.sizeReg = 0; + } + + + /* Read base and size */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + } + else + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); + } + + + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + { + pAddrDecWin->addrWin.size = INTER_REGS_SIZE; + pAddrDecWin->target = INTER_REGS; + pAddrDecWin->enable = MV_TRUE; + + return MV_OK; + } + + + if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + + } + + + + if (-1 == pAddrDecWin->addrWin.size) + { + return MV_ERROR; + } + + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> + ATMWCR_WIN_ATTR_OFFS; + targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> + ATMWCR_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + if (INTER_REGS == target) + { + return MV_AHB_TO_MBUS_INTREG_WIN; + } + + for (winNum = 0; winNum < mvAhbToMbusWinNum() ; winNum++) + { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + + } + + if (decWin.enable == MV_TRUE) + { + if (decWin.target == target) + { + return winNum; + } + + } + + } + + return 0xFFFFFFFF; + + +} + +/******************************************************************************* +* mvAhbToMbusWinAvailGet - Get First Available window number. +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + for (winNum = 0; winNum < mvAhbToMbusWinNum() ; winNum++) + { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + + } + + if (decWin.enable == MV_FALSE) + { + return winNum; + } + + } + + return 0xFFFFFFFF; +} + + +/******************************************************************************* +* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Peripheral winNum enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other winNum window. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) +{ + + /* Parameter checking */ + if (winNum >= mvAhbToMbusWinNum()) + { + mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal registers bar can't be disable or enabled */ + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + { + return (enable ? MV_OK : MV_ERROR); + } + + if (enable == MV_TRUE) + { + /* enable the window */ + MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvAhbToMbusWinRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* After a CPU address hits one of PCI address decode windows there is an +* option to remap the address to a different one. For example, CPU +* executes a read from PCI winNum window address 0x1200.0000. This +* can be modified so the address on the PCI bus would be 0x1400.0000 +* Using the PCI address remap mechanism. +* +* INPUT: +* winNum - Peripheral winNum enumerator. Must be a PCI winNum. +* pAddrDecWin - CPU winNum window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddr; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; + + MV_U32 effectiveBaseAddress=0, + baseAddrValue=0,windowSizeValue=0; + + + /* Get registers offsets of given winNum */ + if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) + { + return 0xffffffff; + } + + /* 1) Set address remap low */ + baseAddr = pAddrWin->baseLow; + + /* Check base address aligment */ + /* + if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) + { + mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", + baseAddr); + return MV_ERROR; + } + */ + + /* BaseLow[31:16] => base register [31:16] */ + baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; + + MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); + + MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); + + + baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + + baseAddrValue &= ATMWBR_BASE_MASK; + windowSizeValue &=ATMWCR_WIN_SIZE_MASK; + + /* Start calculating the effective Base Address */ + effectiveBaseAddress = baseAddrValue ; + + /* The effective base address will be combined from the chopped (if any) + remap value (according to the size value and remap mechanism) and the + window's base address */ + effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); + /* If the effectiveBaseAddress exceed the window boundaries return an + invalid value. */ + + if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) + { + mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); + return 0xffffffff; + } + + return effectiveBaseAddress; + + +} +/******************************************************************************* +* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets +* +* DESCRIPTION: +* +* INPUT: +* target1 - CPU Interface target 1 +* target2 - CPU Interface target 2 +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if targets are illigal, or if one of the targets is not +* associated to a valid window . +* MV_OK otherwise. +* +*******************************************************************************/ + + +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) +{ + MV_U32 winNum1,winNum2; + MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; + MV_U32 remapBaseLow1=0,remapBaseLow2=0; + MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; + + + /* Check parameters */ + if (target1 >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); + return MV_ERROR; + } + + if (target2 >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); + return MV_ERROR; + } + + + /* get window associated with this target */ + winNum1 = mvAhbToMbusWinTargetGet(target1); + + if (winNum1 == 0xffffffff) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", + target1,winNum1); + return MV_ERROR; + + } + + /* get window associated with this target */ + winNum2 = mvAhbToMbusWinTargetGet(target2); + + if (winNum2 == 0xffffffff) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", + target2,winNum2); + return MV_ERROR; + + } + + /* now Get original values of both Windows */ + if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", + winNum1); + return MV_ERROR; + + } + if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", + winNum2); + return MV_ERROR; + + } + + + /* disable both windows */ + if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", + winNum1); + return MV_ERROR; + + } + if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", + winNum2); + return MV_ERROR; + + } + + + /* now swap targets */ + + /* first save winDec2 values */ + winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; + winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; + winDecTemp.addrWin.size = winDec2.addrWin.size; + winDecTemp.enable = winDec2.enable; + winDecTemp.target = winDec2.target; + + /* winDec2 = winDec1 */ + winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; + winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; + winDec2.addrWin.size = winDec1.addrWin.size; + winDec2.enable = winDec1.enable; + winDec2.target = winDec1.target; + + + /* winDec1 = winDecTemp */ + winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; + winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; + winDec1.addrWin.size = winDecTemp.addrWin.size; + winDec1.enable = winDecTemp.enable; + winDec1.target = winDecTemp.target; + + + /* now set the new values */ + + + mvAhbToMbusWinSet(winNum1,&winDec1); + mvAhbToMbusWinSet(winNum2,&winDec2); + + + + + + /* now we will treat the remap windows if exist */ + + + /* now check if one or both windows has a remap window + as well after the swap ! */ + + /* if a window had a remap value differnt than the base value + before the swap , then after the swap the remap value will be + equal to the base value unless both windows has a remap windows*/ + + /* first get old values */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) + { + remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); + remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); + + } + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) + { + remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); + remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); + + + } + + /* now do the swap */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) + { + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) + { + /* Two windows has a remap !!! so swap */ + + MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); + MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); + + MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); + MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); + + + + } + else + { + /* remap == base */ + MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); + MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); + + } + + } + else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) + { + /* remap == base */ + MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); + MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); + + } + + + + return MV_OK; + + +} + + + +#if defined(MV_88F1181) + +/******************************************************************************* +* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. +* +* DESCRIPTION: +* This function sets CPU Mbus Arbiter +* +* INPUT: +* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At +* each clock cycle, the crossbar arbiter samples all +* requests and gives the bus to the next agent according +* to the "pizza". +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if paramers to function invalid. +* +*******************************************************************************/ +MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) +{ + MV_U32 sliceNum; + MV_U32 xbarCtrl = 0; + MV_MBUS_ARB_TARGET xbarTarget; + + /* 1) Set crossbar control low register */ + for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) + { + xbarTarget = pPizzaArbArray[sliceNum]; + + /* sliceNum parameter check */ + if (xbarTarget > MAX_MBUS_ARB_TARGETS) + { + mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", + xbarTarget); + return MV_ERROR; + } + xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); + } + /* Write to crossbar control low register */ + MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); + + xbarCtrl = 0; + + /* 2) Set crossbar control high register */ + for (sliceNum = MRLR_SLICE_NUM; + sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; + sliceNum++) + { + + xbarTarget = pPizzaArbArray[sliceNum]; + + /* sliceNum parameter check */ + if (xbarTarget > MAX_MBUS_ARB_TARGETS) + { + mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", + xbarTarget); + return MV_ERROR; + } + xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); + } + /* Write to crossbar control high register */ + MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); + + return MV_OK; +} + +/******************************************************************************* +* mvMbusArbCtrlSet - Set MBus Arbiter control register +* +* DESCRIPTION: +* +* INPUT: +* ctrl - pointer to MV_MBUS_ARB_CTRL register +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if paramers to function invalid. +* +*******************************************************************************/ +MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) +{ + + if (ctrl->highPrio == MV_FALSE) + { + MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); + } + else + { + MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); + } + + if (ctrl->fixedRoundRobin == MV_FALSE) + { + MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); + } + else + { + MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); + } + + if (ctrl->starvEn == MV_FALSE) + { + MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); + } + else + { + MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* mvMbusArbCtrlGet - Get MBus Arbiter control register +* +* DESCRIPTION: +* +* INPUT: +* ctrl - pointer to MV_MBUS_ARB_CTRL register +* +* OUTPUT: +* ctrl - pointer to MV_MBUS_ARB_CTRL register +* +* RETURN: +* MV_ERROR if paramers to function invalid. +* +*******************************************************************************/ +MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) +{ + + MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); + + if (ctrlReg & MACR_ARB_ARM_TOP) + { + ctrl->highPrio = MV_TRUE; + } + else + { + ctrl->highPrio = MV_FALSE; + } + + if (ctrlReg & MACR_ARB_TARGET_FIXED) + { + ctrl->fixedRoundRobin = MV_TRUE; + } + else + { + ctrl->fixedRoundRobin = MV_FALSE; + } + + if (ctrlReg & MACR_ARB_REQ_CTRL_EN) + { + ctrl->starvEn = MV_TRUE; + } + else + { + ctrl->starvEn = MV_FALSE; + } + + + return MV_OK; +} + +#endif /* #if defined(MV_88F1181) */ + + + +/******************************************************************************* +* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets +* +* DESCRIPTION: +* CPU to PCI address remap registers offsets are inconsecutive. +* This function returns PCI address remap registers offsets. +* +* INPUT: +* winNum - Address decode window number. See MV_U32 enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one. +* +*******************************************************************************/ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, + AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) +{ + + if (mvCtrlModelGet() == MV_6282_DEV_ID) + { + if((winNum != 4) && (winNum != 5) && (winNum != 6) && (winNum != 7)) + { + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + } + else + { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", + winNum)); + return MV_NO_SUCH; + } + } + else +{ + switch (winNum) + { + case 0: + case 1: + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + case 2: + case 3: + if((mvCtrlModelGet() == MV_5281_DEV_ID) || + (mvCtrlModelGet() == MV_1281_DEV_ID) || + (mvCtrlModelGet() == MV_6183_DEV_ID) || + (mvCtrlModelGet() == MV_6183L_DEV_ID)) + { + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + } + else + { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", + winNum)); + return MV_NO_SUCH; + } + default: + { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", + winNum)); + return MV_NO_SUCH; + } + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvAhbToMbusAddDecShow(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN win; + MV_U32 winNum; + mvOsOutput( "\n" ); + mvOsOutput( "AHB To MBUS Bridge:\n" ); + mvOsOutput( "-------------------\n" ); + + for( winNum = 0; winNum < mvAhbToMbusWinNum(); winNum++ ) + { + memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); + + mvOsOutput( "win%d - ", winNum ); + + if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + + } + else + mvOsOutput( "disable\n" ); + } + } + +} + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvAhbToMbus.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvAhbToMbus.h new file mode 100644 index 0000000..c0d861d --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvAhbToMbus.h @@ -0,0 +1,131 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbush +#define __INCmvAhbToMbush + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* defines */ + +#if defined(MV_88F1181) +/* This enumerator defines the Marvell controller possible MBUS arbiter */ +/* target ports. It is used to define crossbar priority scheame (pizza) */ +typedef enum _mvMBusArbTargetId +{ + DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ + TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ + ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ + PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ + PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ + MAX_MBUS_ARB_TARGETS +}MV_MBUS_ARB_TARGET; + +typedef struct _mvMBusArbCtrl +{ + MV_BOOL starvEn; + MV_BOOL highPrio; + MV_BOOL fixedRoundRobin; + +}MV_MBUS_ARB_CTRL; + +#endif /* #if defined(MV_88F1181) */ + +typedef struct _mvAhbtoMbusDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_AHB_TO_MBUS_DEC_WIN; + +/* mvAhbToMbus.h API list */ + +MV_STATUS mvAhbToMbusInit(MV_VOID); +MV_U32 mvAhbToMbusWinNum(MV_VOID); +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); + +#if defined(MV_88F1181) + +MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); +MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); +MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); + +#endif /* #if defined(MV_88F1181) */ + + +MV_VOID mvAhbToMbusAddDecShow(MV_VOID); + + +#endif /* __INCmvAhbToMbush */ diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h new file mode 100644 index 0000000..01a89cd --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h @@ -0,0 +1,142 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbusRegsh +#define __INCmvAhbToMbusRegsh + +/******************************/ +/* ARM Address Map Registers */ +/******************************/ +#define MV_6282_MAX_AHB_TO_MBUS_WINS 11 +#define MV_AHB_TO_MBUS_INTREG_WIN 8 +#define MAX_AHB_TO_MBUS_WINS 9 + +#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 + +/* Window Control Register */ +/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ +#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ + +#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated + with this window*/ +#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) + +#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes + Associated with this window */ +#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) + + +/* +Used with the Base register to set the address window size and location +Must be programed from LSB to MSB as sequence of 1’s followed +by sequence of 0’s. The number of 1’s specifies the size of the window +in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). + +NOTE: A value of 0x0 specifies 64KB size. +*/ +#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ +#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) +#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 + +/* Window Base Register */ +/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ + +/* +Used with the size field to set the address window size and location. +Corresponds to transaction address[31:16] +*/ +#define ATMWBR_BASE_OFFS 16 /* Base Address */ +#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) +#define ATMWBR_BASE_ALIGNMENT 0x10000 + +/* Window Remap Low Register */ +/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ + +/* +Used with the size field to specifies address bits[31:0] to be driven to +the target interface.: +target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) +*/ +#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ +#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) +#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 + +/* Window Remap High Register */ +/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ + +/* +Specifies address bits[63:32] to be driven to the target interface. +target_addr[63:32] = (RemapHigh[31:0] +*/ +#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ +#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) + + +#endif /* __INCmvAhbToMbusRegsh */ + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIf.c b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIf.c new file mode 100644 index 0000000..1bae013 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIf.c @@ -0,0 +1,1048 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "mvSysDram.h" + +/*#define MV_DEBUG*/ +/* defines */ + +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* locals */ +/* static functions */ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); + +MV_TARGET * sampleAtResetTargetArray; +MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; +MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; +/******************************************************************************* +* mvCpuIfInit - Initialize Controller CPU interface +* +* DESCRIPTION: +* This function initialize Controller CPU interface: +* 1. Set CPU interface configuration registers. +* 2. Set CPU master Pizza arbiter control according to static +* configuration described in configuration file. +* 3. Opens CPU address decode windows. DRAM windows are assumed to be +* already set (auto detection). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + MV_U32 regVal; + MV_TARGET target; + MV_ADDR_WIN addrWin; + + if (cpuAddrWinMap == NULL) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); + return MV_ERROR; + } + + /*Initialize the boot target array according to device type*/ + if(mvCtrlModelGet() == MV_6180_DEV_ID || mvCtrlModelGet() == MV_6280_DEV_ID) + sampleAtResetTargetArray = sampleAtResetTargetArray6180P; + else + sampleAtResetTargetArray = sampleAtResetTargetArrayP; + + /* Set ARM Configuration register */ + regVal = MV_REG_READ(CPU_CONFIG_REG); + regVal &= ~CPU_CONFIG_DEFAULT_MASK; + regVal |= CPU_CONFIG_DEFAULT; + MV_REG_WRITE(CPU_CONFIG_REG,regVal); + + /* First disable all CPU target windows */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) + { + if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) + { + continue; + } + +#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PCI(target)) + { + continue; + } +#endif + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + { + continue; + } +#endif +#if defined(MV_RUN_FROM_FLASH) + /* Don't disable the boot device. */ + if (target == DEV_BOOCS) + { + continue; + } +#endif /* MV_RUN_FROM_FLASH */ + /* Only MV88F6282 have 2 PCIe interfaces */ + if((mvCtrlModelGet() != MV_6282_DEV_ID) && MV_TARGET_IS_PEX1(target)) + continue; + + mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); + } + +#if defined(MV_RUN_FROM_FLASH) + /* Resize the bootcs windows before other windows, because this */ + /* window is enabled and will cause an overlap if not resized. */ + target = DEV_BOOCS; + + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) + { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } + +#endif /* MV_RUN_FROM_FLASH */ + + /* Go through all targets in user table until table terminator */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) + { + +#if defined(MV_RUN_FROM_FLASH) + if (target == DEV_BOOCS) + { + continue; + } +#endif /* MV_RUN_FROM_FLASH */ + + /* if DRAM auto sizing is used do not initialized DRAM target windows, */ + /* assuming this already has been done earlier. */ +#ifdef MV_DRAM_AUTO_SIZE + if (MV_TARGET_IS_DRAM(target)) + { + continue; + } +#endif + +#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PCI(target)) + { + continue; + } +#endif + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + { + continue; + } +#endif + /* If the target attribute is the same as the boot device attribute */ + /* then it's stays disable */ + if (MV_TARGET_IS_AS_BOOT(target)) + { + continue; + } + /* Only MV88F6282 have 2 PCIe interfaces */ + if((mvCtrlModelGet() != MV_6282_DEV_ID) && MV_TARGET_IS_PEX1(target)) + continue; + + if((0 == cpuAddrWinMap[target].addrWin.size) || + (DIS == cpuAddrWinMap[target].enable)) + + { + if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); + return MV_ERROR; + } + + } + else + { + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) + { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } + + + } + } + + return MV_OK; + + +} + + +/******************************************************************************* +* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window +* +* DESCRIPTION: +* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) +* address window, also known as address decode window. +* A new address decode window is set for specified target address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the target window, allowing CPU to access +* the target window. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - CPU target window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU target window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU target window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the target is unsupported. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 existingWinNum; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); + return MV_BAD_PARAM; + } + + if (MV_TARGET_IS_DRAM(target)) + { + /* copy relevant data to MV_DRAM_DEC_WIN structure */ + addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; + addrDecWin.enable = pAddrDecWin->enable; + + + if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); + { + mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); + return MV_ERROR; + } + + } + else + { + /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ + decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + decWin.addrWin.size = pAddrDecWin->addrWin.size; + decWin.enable = pAddrDecWin->enable; + decWin.target = target; + + existingWinNum = mvAhbToMbusWinTargetGet(target); + + /* check if there is already another Window configured + for this target */ + if ((existingWinNum < mvAhbToMbusWinNum())&& + (existingWinNum != pAddrDecWin->winNum)) + { + /* if we want to enable the new winow number + passed by the user , then the old one should + be disabled */ + if (MV_TRUE == pAddrDecWin->enable) + { + /* be sure it is disabled */ + mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); + } + } + + if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); + return MV_ERROR; + } + + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window +* +* DESCRIPTION: +* Get the CPU peripheral target address window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* pAddrDecWin - CPU target window information data structure. +* +* RETURN: +* MV_OK if target exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + + MV_U32 winNum=0xffffffff; + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Only MV88F6282 have 2 PCIe interfaces */ + if((mvCtrlModelGet() != MV_6282_DEV_ID) && MV_TARGET_IS_PEX1(target)) + return MV_NO_SUCH; + + + if (MV_TARGET_IS_DRAM(target)) + { + if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", + target); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; + pAddrDecWin->enable = addrDecWin.enable; + pAddrDecWin->winNum = 0xffffffff; + + } + else + { + /* get the Window number associated with this target */ + + winNum = mvAhbToMbusWinTargetGet(target); + if (winNum >= mvAhbToMbusWinNum()) + { + return MV_NO_SUCH; + + } + + if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) + { + mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", + __FUNCTION__, winNum); + return MV_ERROR; + + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = decWin.addrWin.size; + pAddrDecWin->enable = decWin.enable; + pAddrDecWin->winNum = winNum; + + } + + + + + return MV_OK; +} + + +/******************************************************************************* +* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* target - Peripheral target enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other target window. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) +{ + MV_U32 winNum, temp; + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* get the window and check if it exist */ + temp = mvCpuIfTargetWinGet(target, &addrDecWin); + if (MV_NO_SUCH == temp) + { + return (enable? MV_ERROR: MV_OK); + } + else if( MV_OK != temp) + { + mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); + return MV_ERROR; + } + + + /* check overlap */ + + if (MV_TRUE == enable) + { + if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) + { + DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); + return MV_ERROR; + } + + } + + + if (MV_TARGET_IS_DRAM(target)) + { + if (mvDramIfWinEnable(target , enable) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); + return MV_ERROR; + + } + + } + else + { + /* get the Window number associated with this target */ + + winNum = mvAhbToMbusWinTargetGet(target); + + if (winNum >= mvAhbToMbusWinNum()) + { + return (enable? MV_ERROR: MV_OK); + } + + if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", + winNum); + return MV_ERROR; + + } + + } + + return MV_OK; +} + + +/******************************************************************************* +* mvCpuIfTargetWinSizeGet - Get CPU target address window size +* +* DESCRIPTION: +* Get the size of CPU-to-peripheral target window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit size. Function also returns '0' if window is closed. +* Function returns 0xFFFFFFFF in case of an error. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); + return 0; + } + + /* Get the winNum window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", + target); + return 0; + } + + /* Check if window is enabled */ + if (addrDecWin.enable == MV_TRUE) + { + return (addrDecWin.addrWin.size); + } + else + { + return 0; /* Window disabled. return 0 */ + } +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target low base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit low base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", + target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + { + return 0xffffffff; + } + return (addrDecWin.addrWin.baseLow); +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target high base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit high base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", + target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + { + return 0; + } + + return (addrDecWin.addrWin.baseHigh); +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCpuIfPexRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pexTarget - Peripheral target enumerator. Must be a PEX target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PEX one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* Check parameters */ + + if (mvCtrlPexMaxIfGet() > 1) + { + if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) + { + mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); + return 0xffffffff; + } + + } + else + { + if (!MV_TARGET_IS_PEX0(pexTarget)) + { + mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); + return 0xffffffff; + } + + } + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pexTarget); + + if (winNum >= mvAhbToMbusWinNum()) + { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + + } + + return mvAhbToMbusWinRemap(winNum , pAddrDecWin); +} + +#endif + +#if defined(MV_INCLUDE_PCI) +/******************************************************************************* +* mvCpuIfPciRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pciTarget - Peripheral target enumerator. Must be a PCI target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* Check parameters */ + if (!MV_TARGET_IS_PCI(pciTarget)) + { + mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); + return 0xffffffff; + } + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pciTarget); + + if (winNum >= mvAhbToMbusWinNum()) + { + mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + + } + + return mvAhbToMbusWinRemap(winNum , pAddrDecWin); +} +#endif /* MV_INCLUDE_PCI */ + + +/******************************************************************************* +* mvCpuIfPciIfRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pciTarget - Peripheral target enumerator. Must be a PCI target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) +{ +#if defined(MV_INCLUDE_PEX) + if (MV_TARGET_IS_PEX(pciIfTarget)) + { + return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); + } +#endif +#if defined(MV_INCLUDE_PCI) + + if (MV_TARGET_IS_PCI(pciIfTarget)) + { + return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); + } +#endif + return 0; +} + + + +/******************************************************************************* +* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address +* +* DESCRIPTION: +* +* INPUT: +* baseAddress - base address to be checked +* +* OUTPUT: +* None. +* +* RETURN: +* the target number that baseAddress belongs to or MAX_TARGETS is not +* found +* +*******************************************************************************/ + +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + for( target = 0; target < MAX_TARGETS; target++ ) + { + if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) + { + if( win.enable ) + { + if ((baseAddress >= win.addrWin.baseLow) && + (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; + } + } + else return MAX_TARGETS; + + } + + return target; +} +/******************************************************************************* +* cpuTargetWinOverlap - Detect CPU address decode windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case CPU address decode +* windows overlapps. +* This function detects CPU address decode windows overlapping of a +* specified target. The function does not check the target itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 targetNum; + MV_CPU_DEC_WIN addrDecWin; + MV_STATUS status; + + + for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) + { +#if defined(MV_RUN_FROM_FLASH) + if(MV_TARGET_IS_AS_BOOT(target)) + { + if (MV_CHANGE_BOOT_CS(targetNum) == target) + continue; + } +#endif /* MV_RUN_FROM_FLASH */ + + /* don't check our target or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); + if(MV_NO_SUCH == status) + { + continue; + } + if(MV_OK != status) + { + DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); + return MV_TRUE; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + DB(mvOsPrintf( + "cpuTargetWinOverlap: Required target %d overlap current %d\n", + target, targetNum)); + return MV_TRUE; + } + } + + return MV_FALSE; + +} + +/******************************************************************************* +* mvCpuIfAddDecShow - Print the CPU address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCpuIfAddDecShow(MV_VOID) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + mvOsOutput( "\n" ); + mvOsOutput( "CPU Interface\n" ); + mvOsOutput( "-------------\n" ); + + for( target = 0; target < MAX_TARGETS; target++ ) + { + + memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); + + mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); + mvOsOutput( "...." ); + + if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "base %08x, ", win.addrWin.baseLow ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + + } + else + mvOsOutput( "disable\n" ); + } + else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) + { + mvOsOutput( "no such\n" ); + } + } +} + +/******************************************************************************* +* mvCpuIfEnablePex - Enable PCI Express. +* +* DESCRIPTION: +* This function Enable PCI Express. +* +* INPUT: +* pexIf - PEX interface number. +* pexType - MV_PEX_ROOT_COMPLEX - root complex device +* MV_PEX_END_POINT - end point device +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#if defined(MV_INCLUDE_PEX) +MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) +{ + /* Set pex mode incase S@R not exist */ + if( pexType == MV_PEX_END_POINT) + { + MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); + /* Change pex mode in capability reg */ + MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); + MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); + + } + else + { + MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); + } + + /* CPU config register Pex enable */ + MV_REG_BIT_SET(CPU_CTRL_STAT_REG,(CCSR_PCI_ACCESS_MASK(pexIf))); +} +#endif + + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIf.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIf.h new file mode 100644 index 0000000..224ed07 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIf.h @@ -0,0 +1,120 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfh +#define __INCmvCpuIfh + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ddr2/mvDramIf.h" +#include "ctrlEnv/sys/mvSysDram.h" +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif + +/* defines */ + +/* typedefs */ +/* This structure describes CPU interface address decode window */ +typedef struct _mvCpuIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_CPU_DEC_WIN; + + + +/* mvCpuIfLib.h API list */ + +/* mvCpuIfLib.h API list */ + +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); +MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); +#endif +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); +#endif +MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); + +MV_VOID mvCpuIfAddDecShow(MV_VOID); + +#if defined(MV88F6281) +MV_STATUS mvCpuIfBridgeReorderWAInit(void); +#endif + +#endif /* __INCmvCpuIfh */ diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIfInit.S b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIfInit.S new file mode 100644 index 0000000..dc0df5f --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIfInit.S @@ -0,0 +1,163 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include "mvDeviceId.h" +#include "mvCtrlEnvRegs.h" +#include "mvCpuIfRegs.h" +#include "mvCtrlEnvAsm.h" + + +/******************************************************************************* +* mvCpuIfPreInit - Make early initialization of CPU interface. +* +* DESCRIPTION: +* The function will initialize the CPU interface parameters that must +* be initialize before any BUS activity towards the DDR interface, +* which means it must be executed from ROM. Because of that, the function +* is implemented in assembly code. +* The function configure the following CPU config register parameters: +* 1) CPU2MbusLTickDrv +* 2) CPU2MbusLTickSample. +* NOTE: This function must be called AFTER the internal register +* base is modified to INTER_REGS_BASE. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* r11 holds return function address. +*******************************************************************************/ +#define MV88F6281_PCKG_OPT 2 +#define MV88F6192_PCKG_OPT 1 +#define MV88F6180_PCKG_OPT 0 + + .globl _mvCpuIfPreInit +_mvCpuIfPreInit: + + mov r11, LR /* Save link register */ + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r4, r5); + + /* goto calcConfigReg if device is 6281/6282 */ + ldr r5, =MV88F6281_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* goto calcConfigReg if device is 6192/6190 */ + ldr r5, =MV88F6192_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* Else 6180 */ + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_CPUCLCK_MASK_6180 + and r5, r4, r5 + mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3_1 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4_1 + beq setConfigReg + b setConfigReg + +calcConfigReg: + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_DDRCLCK_RTIO_MASK + and r5, r4, r5 + mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4 + beq setConfigReg + + /* Else */ + ldr r4, =0 + +setConfigReg: + /* Read CPU Config register */ + MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) + ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) + and r7, r7, r5 /* Clear register fields */ + orr r7, r7, r4 /* Set the values according to the findings */ + MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) + +done: + mov PC, r11 /* r11 is saved link register */ diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIfRegs.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIfRegs.h new file mode 100644 index 0000000..bb8c8b2 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvCpuIfRegs.h @@ -0,0 +1,304 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfRegsh +#define __INCmvCpuIfRegsh + +/****************************************/ +/* ARM Control and Status Registers Map */ +/****************************************/ + +#define CPU_CONFIG_REG 0x20100 +#define CPU_CTRL_STAT_REG 0x20104 +#define CPU_RSTOUTN_MASK_REG 0x20108 +#define CPU_SYS_SOFT_RST_REG 0x2010C +#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 +#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 +#define CPU_FTDLL_CONFIG_REG 0x20120 +#define CPU_L2_CONFIG_REG 0x20128 + + + +/* ARM Configuration register */ +/* CPU_CONFIG_REG (CCR) */ + + +/* Reset vector location */ +#define CCR_VEC_INIT_LOC_OFFS 1 +#define CCR_VEC_INIT_LOC_MASK BIT1 +/* reset at 0x00000000 */ +#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0xFFFF0000 */ +#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) + + +#define CCR_AHB_ERROR_PROP_OFFS 2 +#define CCR_AHB_ERROR_PROP_MASK BIT2 +/* Erros are not propogated to AHB */ +#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) +/* Erros are propogated to AHB */ +#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) + + +#define CCR_ENDIAN_INIT_OFFS 3 +#define CCR_ENDIAN_INIT_MASK BIT3 +#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) + + +#define CCR_INCR_EN_OFFS 4 +#define CCR_INCR_EN_MASK BIT4 +#define CCR_INCR_EN BIT4 + + +#define CCR_NCB_BLOCKING_OFFS 5 +#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) +#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) +#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) + +#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 +#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) +#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 +#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) +#define CCR_ICACH_PREF_BUF_ENABLE BIT16 +#define CCR_DCACH_PREF_BUF_ENABLE BIT17 + +/* Ratio options for CPU to DDR for 6282/6281/6192/6190 */ +#define CPU_2_DDR_CLK_1x3 4 +#define CPU_2_DDR_CLK_1x4 6 + +/* Ratio options for CPU to DDR for 6282/6281 only */ +#define CPU_2_DDR_CLK_2x9 7 +#define CPU_2_DDR_CLK_1x5 8 +#define CPU_2_DDR_CLK_1x6 9 + +/* Ratio options for CPU to DDR for 6180 only */ +#define CPU_2_DDR_CLK_1x3_1 0x5 +#define CPU_2_DDR_CLK_1x4_1 0x6 + +/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ +/* CPU to Mbus-L Tick Sample fields in CPU config register */ + +#define TICK_DRV_1x1 0 +#define TICK_DRV_1x2 0 +#define TICK_DRV_1x3 1 +#define TICK_DRV_1x4 2 +#define TICK_SMPL_1x1 0 +#define TICK_SMPL_1x2 1 +#define TICK_SMPL_1x3 0 +#define TICK_SMPL_1x4 0 + +#define CPU_2_MBUSL_DDR_CLK_1x2 \ + ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) +#define CPU_2_MBUSL_DDR_CLK_1x3 \ + ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) +#define CPU_2_MBUSL_DDR_CLK_1x4 \ + ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) + +/* ARM Control and Status register */ +/* CPU_CTRL_STAT_REG (CCSR) */ + + +/* +This is used to block PCI express\PCI from access Socrates/Feroceon GP +while ARM boot is still in progress +*/ + +#define CCSR_PCI_ACCESS_OFFS(pexIf) (pexIf * 4) +#define CCSR_PCI_ACCESS_MASK(pexIf) (1 << (CCSR_PCI_ACCESS_OFFS(pexIf))) +#define CCSR_PCI_ACCESS_ENABLE(pexIf) (1 << (CCSR_PCI_ACCESS_OFFS(pexIf))) +#define CCSR_PCI_ACCESS_DISBALE(pexIf) (0 << (CCSR_PCI_ACCESS_OFFS(pexIf))) + +#define CCSR_ARM_RESET BIT1 +#define CCSR_SELF_INT BIT2 +#define CCSR_BIG_ENDIAN BIT15 + + +/* RSTOUTn Mask Register */ +/* CPU_RSTOUTN_MASK_REG (CRMR) */ + +#define CRMR_PEX_RST_OUT_OFFS 0 +#define CRMR_PEX_RST_OUT_MASK BIT0 +#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) +#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) + +#define CRMR_WD_RST_OUT_OFFS 1 +#define CRMR_WD_RST_OUT_MASK BIT1 +#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) +#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) + +#define CRMR_SOFT_RST_OUT_OFFS 2 +#define CRMR_SOFT_RST_OUT_MASK BIT2 +#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) +#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) + +/* System Software Reset Register */ +/* CPU_SYS_SOFT_RST_REG (CSSRR) */ + +#define CSSRR_SYSTEM_SOFT_RST BIT0 + +/* AHB to Mbus Bridge Interrupt Cause Register*/ +/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ + +#define CAMCIR_ARM_SELF_INT BIT0 +#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 +#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 +#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 + + +/* AHB to Mbus Bridge Interrupt Mask Register*/ +/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ + +#define CAMCIR_ARM_SELF_INT_OFFS 0 +#define CAMCIR_ARM_SELF_INT_MASK BIT0 +#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) +#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) + + +#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 +#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 +#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) +#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) + +#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 +#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 +#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) +#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) + +#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 +#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 +#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) +#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) + +/* CPU FTDLL Config register (CFCR) fields */ +#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 +#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) +#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 +#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) +#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) +/* For Orion 2 D2 only */ +#define CFCR_MRVL_CPU_ID_OFFS 16 +#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) +#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) +#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) +#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 +#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) +#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) +#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) + +/* CPU_L2_CONFIG_REG fields */ +#ifdef MV_CPU_LE +#define CL2CR_L2_ECC_EN_OFFS 2 +#define CL2CR_L2_WT_MODE_OFFS 4 +#else +#define CL2CR_L2_ECC_EN_OFFS 26 +#define CL2CR_L2_WT_MODE_OFFS 28 +#endif + +#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) +#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) + +/*******************************************/ +/* Main Interrupt Controller Registers Map */ +/*******************************************/ + +#define CPU_MAIN_INT_CAUSE_REG 0x20200 +#define CPU_MAIN_IRQ_MASK_REG 0x20204 +#define CPU_MAIN_FIQ_MASK_REG 0x20208 +#define CPU_ENPOINT_MASK_REG 0x2020C +#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 +#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 +#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 +#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C + + +/*******************************************/ +/* ARM Doorbell Registers Map */ +/*******************************************/ + +#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 +#define CPU_HOST_TO_ARM_MASK_REG 0x20404 +#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 +#define CPU_ARM_TO_HOST_MASK_REG 0x2040C + + + +/* CPU control register map */ +/* Set bits means value is about to change according to new value */ +#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) + +#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) + +/* CPU Control and status defaults */ +#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) + + +#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) + +#endif /* __INCmvCpuIfRegsh */ + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysAudio.c b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysAudio.c new file mode 100644 index 0000000..143fd9e --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysAudio.c @@ -0,0 +1,324 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvSysAudio.h" + +/******************************************************************************* +* mvAudioWinSet - Set AUDIO target address window +* +* DESCRIPTION: +* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) +* address window, also known as address decode window. +* After setting this target window, the AUDIO will be able to access the +* target within the address window. +* +* INPUT: +* winNum - AUDIO target address decode window number. +* pAddrDecWin - AUDIO target window data structure. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if address window overlapps with other address decode windows. +* MV_BAD_PARAM if base address is invalid parameter or target is +* unknown. +* +*******************************************************************************/ +MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttribs; + MV_DEC_REGS decRegs; + + /* Parameter checking */ + if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = 0; + decRegs.sizeReg = 0; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; + decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); + + /* set target ID */ + decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; + decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); + + if (pAddrDecWin->enable == MV_TRUE) + { + decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; + } + else + { + decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; + } + + MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); + MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvAudioWinGet - Get AUDIO peripheral target address window. +* +* DESCRIPTION: +* Get AUDIO peripheral target address window. +* +* INPUT: +* winNum - AUDIO target address decode window number. +* +* OUTPUT: +* pAddrDecWin - AUDIO target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s : ERR. Invalid winNum %d\n", + __FUNCTION__, winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); + decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) + { + mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> + MV_AUDIO_WIN_ATTR_OFFSET; + targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> + MV_AUDIO_WIN_TARGET_OFFSET; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + return MV_OK; +} +/******************************************************************************* +* mvAudioAddrDecShow - Print the AUDIO address decode map. +* +* DESCRIPTION: +* This function print the AUDIO address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvAudioAddrDecShow(MV_VOID) +{ + + MV_AUDIO_DEC_WIN win; + int i; + + if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) + return; + + + mvOsOutput( "\n" ); + mvOsOutput( "AUDIO:\n" ); + mvOsOutput( "----\n" ); + + for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvAudioWinGet( i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + + +/******************************************************************************* +* mvAudioWinInit - Initialize the integrated AUDIO target address window. +* +* DESCRIPTION: +* Initialize the AUDIO peripheral target address window. +* +* INPUT: +* +* +* OUTPUT: +* +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvAudioInit(MV_VOID) +{ + int winNum; + MV_AUDIO_DEC_WIN audioWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 status; + + mvAudioHalInit(0); + + /* Initiate Audio address decode */ + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); + regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; + MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); + } + + for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) + { + + /* We will set the Window to DRAM_CS0 in default */ + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(SDRAM_CS0, + &cpuAddrDecWin); + + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; + audioWin.enable = MV_TRUE; + audioWin.target = SDRAM_CS0; + + if(MV_OK != mvAudioWinSet(winNum, &audioWin)) + { + return MV_ERROR; + } + } + } + + return MV_OK; +} + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysAudio.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysAudio.h new file mode 100644 index 0000000..52ba66f --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysAudio.h @@ -0,0 +1,123 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCMVSysAudioH +#define __INCMVSysAudioH + +#include "mvCommon.h" +#include "audio/mvAudio.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +/***********************************/ +/* Audio Address Decoding registers*/ +/***********************************/ + +#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 +#define MV_AUDIO_RECORD_WIN_NUM 0 +#define MV_AUDIO_PLAYBACK_WIN_NUM 1 + +#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE(0) + 0xA04 + ((win)<<3)) +#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE(0) + 0xA00 + ((win)<<3)) + +#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) +#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) +#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) +#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) + + +/* BITs in Windows 0-3 Control and Base Registers */ +#define MV_AUDIO_WIN_ENABLE_BIT 0 +#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) +MV_TARGET tdmaAddrDecPrioTable[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif + + TBL_TERM +}; + +/******************************************************************************* +* mvCesaWinGet - Get TDMA target address window. +* +* DESCRIPTION: +* Get TDMA target address window. +* +* INPUT: +* winNum - TDMA target address decode window number. +* +* OUTPUT: +* pDecWin - TDMA target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) +{ + MV_DEC_WIN_PARAMS winParam; + MV_U32 sizeReg, baseReg; + + /* Parameter checking */ + if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) + { + mvOsPrintf("%s : ERR. Invalid winNum %d\n", + __FUNCTION__, winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); + sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); + + /* Check if window is enabled */ + if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) + { + pDecWin->enable = MV_TRUE; + + /* Extract window parameters from registers */ + winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; + winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; + winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; + winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); + + /* Translate the decode window parameters to address decode struct */ + if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) + { + mvOsPrintf("Failed to translate register parameters to CESA address" \ + " decode window structure\n"); + return MV_ERROR; + } + } + else + { + pDecWin->enable = MV_FALSE; + } + return MV_OK; +} + +/******************************************************************************* +* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case TDMA address decode +* windows overlapps. +* This function detects TDMA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - if the given address window overlap current address +* decode map, +* MV_FALSE - otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_DEC_WIN addrDecWin; + + for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) + { + mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) + { + mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pDecWin->target), + pDecWin->addrWin.baseLow, + pDecWin->addrWin.size); + return MV_ERROR; + } + + if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) + { + mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* set Size, Attributes and TargetID */ + sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | + ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | + ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); + + if (pDecWin->enable == MV_TRUE) + { + sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; + } + else + { + sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; + } + + /* Update Base value */ + baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); + + MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); + MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); + + return MV_OK; +} + + +static MV_STATUS mvCesaTdmaAddrDecInit (void) +{ + MV_U32 winNum; + MV_STATUS status; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_DEC_WIN cesaWin; + MV_U32 winPrioIndex = 0; + + /* First disable all address decode windows */ + for(winNum=0; winNum= 2 */ + + + + +MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) +{ + MV_U32 cesaCryptEngBase; + MV_CPU_DEC_WIN addrDecWin; + + if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) + { + mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", + sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); + return MV_FAIL; + } + + if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) + cesaCryptEngBase = addrDecWin.addrWin.baseLow; + else + { + mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); + return MV_ERROR; + } + +#if (MV_CESA_VERSION >= 2) + mvCesaTdmaAddrDecInit(); +#endif /* MV_CESA_VERSION >= 2 */ + + return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, + osHandle); + +} diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysCesa.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysCesa.h new file mode 100644 index 0000000..73bcdc5 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysCesa.h @@ -0,0 +1,100 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvSysCesa_h__ +#define __mvSysCesa_h__ + + +#include "mvCommon.h" +#include "cesa/mvCesa.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +/***************************** TDMA Registers *************************************/ + +#define MV_CESA_TDMA_ADDR_DEC_WIN 4 + +#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) + +#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) + +#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 +#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) + +#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 +#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) + +#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 +#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) + +#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 +#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) + +#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 +#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) + + +MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); + +#endif diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysDram.c b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysDram.c new file mode 100644 index 0000000..6f76c2c --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysDram.c @@ -0,0 +1,348 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ + +#include "ddr2/mvDramIf.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvSysDram.h" + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); + +/******************************************************************************* +* mvDramIfWinSet - Set DRAM interface address decode window +* +* DESCRIPTION: +* This function sets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* pAddrDecWin - SDRAM address window structure. +* +* OUTPUT: +* None +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg=0,sizeReg=0; + MV_U32 baseToReg=0 , sizeToReg=0; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlaps with current enabled windows */ + if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + target, + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read base register*/ + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); + + /* read size register */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; + + /* Write to address decode Base Address Register */ + baseReg &= ~SCBAR_BASE_MASK; + baseReg |= baseToReg; + + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); + return MV_BAD_PARAM; + } + + /* set size */ + sizeReg &= ~SCSR_SIZE_MASK; + /* Size is located at upper 16 bits */ + sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); + + /* enable/Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + sizeReg |= SCSR_WIN_EN; + } + else + { + sizeReg &= ~SCSR_WIN_EN; + } + + /* 3) Write to address decode Base Address Register */ + MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinGet - Get DRAM interface address decode window +* +* DESCRIPTION: +* This function gets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* pAddrDecWin - SDRAM address window structure. +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg,sizeReg; + MV_U32 sizeRegVal; + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Read base and size registers */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); + + sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; + + pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, + SCSR_SIZE_ALIGNMENT); + + /* Check if ctrlRegToSize returned OK */ + if (-1 == pAddrDecWin->addrWin.size) + { + mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; + + pAddrDecWin->addrWin.baseHigh = 0; + + + if (sizeReg & SCSR_WIN_EN) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinEnable - Enable/Disable SDRAM address decode window +* +* DESCRIPTION: +* This function enable/Disable SDRAM address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case function parameter are invalid, MV_OK otherewise. +* +*******************************************************************************/ +MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) +{ + MV_DRAM_DEC_WIN addrDecWin; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", + target); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode winNum window */ + MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); + } + else + { /* Overlap detected */ + mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", + target); + return MV_ERROR; + } + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window +* +* DESCRIPTION: +* This function scan each SDRAM address decode window to test if it +* overlapps the given address windoow +* +* INPUT: +* target - SDRAM target where the function skips checking. +* pAddrDecWin - The tested address window for overlapping with +* SDRAM windows. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps any enabled address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_TARGET targetNum; + MV_DRAM_DEC_WIN addrDecWin; + + for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) + { + /* don't check our winNum or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf( + "sdramIfWinOverlap: Required target %d overlap winNum %d\n", + target, targetNum); + return MV_TRUE; + } + } + + return MV_FALSE; +} + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysDram.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysDram.h new file mode 100644 index 0000000..7bd9c9d --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysDram.h @@ -0,0 +1,80 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __sysDram +#define __sysDram + +/* This structure describes CPU interface address decode window */ +typedef struct _mvDramIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +}MV_DRAM_DEC_WIN; + +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); + +#endif diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysGbe.c b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysGbe.c new file mode 100644 index 0000000..7f6e4a5 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysGbe.c @@ -0,0 +1,658 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "ctrlEnv/sys/mvSysGbe.h" + + + +typedef struct _mvEthDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_ETH_DEC_WIN; + +MV_TARGET ethAddrDecPrioTap[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_DEVICE_CS0) + DEVICE_CS0, +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEVICE_CS1, +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEVICE_CS2, +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEVICE_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_IO, +#endif + TBL_TERM +}; + +static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); +static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); +static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); + + +/******************************************************************************* +* mvEthWinInit - Initialize ETH address decode windows +* +* DESCRIPTION: +* This function initialize ETH window decode unit. It set the +* default address decode windows of the unit. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if setting fail. +*******************************************************************************/ +/* Configure EthDrv memory map registes. */ +MV_STATUS mvEthWinInit (int port) +{ + MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; + MV_ETH_DEC_WIN ethWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + static MV_U32 accessProtReg = 0; + +#if (MV_ETH_VERSION <= 1) + static MV_BOOL isFirst = MV_TRUE; + + if(isFirst == MV_FALSE) + { + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); + return MV_OK; + } + isFirst = MV_FALSE; +#endif /* MV_GIGA_ETH_VERSION */ + + /* Initiate Ethernet address decode */ + + /* First disable all address decode windows */ + for(winNum=0; winNum= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + + decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); + decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; + decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; + decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; + + /* for the safe side we disable the window before writing the new + values */ + mvEthWinEnable(port, winNum, MV_FALSE); + MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); + + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + { + mvEthWinEnable(port, winNum, MV_TRUE); + } + + return MV_OK; +} + +/******************************************************************************* +* mvETHWinGet - Get dma peripheral target address window. +* +* DESCRIPTION: +* Get ETH peripheral target address window. +* +* INPUT: +* winNum - ETH to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - ETH target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); + decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; + targetAttrib.targetId = + (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvEthWinEnable - Enable/disable a ETH to target address window +* +* DESCRIPTION: +* This function enable/disable a ETH to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling ETH accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - ETH to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) +{ + MV_ETH_DEC_WIN addrDecWin; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) + { + mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + } + else + { /* Overlap detected */ + mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { /* Disable address decode target window */ + MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + } + return MV_OK; +} + +/******************************************************************************* +* mvEthWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* window number +* +*******************************************************************************/ +MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) +{ + MV_ETH_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + for (winNum=0; winNum= mvCtrlEthMaxPortGet()) + { + mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); + return MV_ERROR; + } + + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) + { + mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); + return MV_ERROR; + } + /* Read current protection register */ + protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); + + /* Clear protection window field */ + protReg &= ~(ETH_PROT_WIN_MASK(winNum)); + + /* Set new protection field value */ + protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); + + /* Write protection register back */ + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); + + return MV_OK; +} + +/******************************************************************************* +* ethWinOverlapDetect - Detect ETH address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case ETH address decode +* windows overlapps. +* This function detects ETH address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex; + MV_ETH_DEC_WIN addrDecWin; + + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); + + for (winNumIndex=0; winNumIndex= LCD_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + if (pAddrDecWin == NULL) + { + DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + /* Check if the requested window overlaps with current windows */ + if (MV_TRUE == lcdWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) + { + DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); + return MV_ERROR; + } + + lcdDecRegs.baseReg = MV_REG_READ(LCD_BASE_ADDR_REG(winNum)); + lcdDecRegs.sizeReg = MV_REG_READ(LCD_WINDOW_CTRL_REG(winNum)); + + /* Get Base Address and size registers values */ + if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &lcdDecRegs)) + { + DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); + return MV_BAD_PARAM; + } + + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + lcdDecRegs.sizeReg &= ~LCDWCR_ATTR_MASK; + lcdDecRegs.sizeReg |= targetAttribs.attrib << LCDWCR_ATTR_OFFS; + /* set target ID */ + lcdDecRegs.sizeReg &= ~LCDWCR_TARGET_MASK; + lcdDecRegs.sizeReg |= targetAttribs.targetId << LCDWCR_TARGET_OFFS; + + + /* Write to address decode Base Address Register */ + MV_REG_WRITE(LCD_BASE_ADDR_REG(winNum), lcdDecRegs.baseReg); + + /* Write to Size Register */ + MV_REG_WRITE(LCD_WINDOW_CTRL_REG(winNum), lcdDecRegs.sizeReg); + + if (pAddrDecWin->enable) + { + MV_REG_BIT_SET(LCD_WINDOW_CTRL_REG(winNum), LCDWCR_WIN_EN_MASK); + } + else + { + MV_REG_BIT_RESET(LCD_WINDOW_CTRL_REG(winNum), LCDWCR_WIN_EN_MASK); + } + + return MV_OK; +} + +/******************************************************************************* +* mvLcdTargetWinGet - Get LCD peripheral target address window. +* +* DESCRIPTION: +* Get LCD peripheral target address window. +* +* INPUT: +* winNum - One of the possible LCD memory decode windows. +* +* OUTPUT: +* base - Window base address. +* size - Window size. +* enable - window enable/disable. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvLcdTargetWinGet(MV_U32 winNum, MV_LCD_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS lcdDecRegs; + MV_TARGET_ATTRIB targetAttrib; + MV_U32 winEn; + + /* Parameter checking */ + if (winNum >= LCD_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); + return MV_ERROR; + } + + if (NULL == pAddrDecWin) + { + DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + + winEn = MV_REG_READ(LCD_WINDOW_CTRL_REG(winNum)) & LCDWCR_WIN_EN_MASK; + + /* Check if enable bit is equal for all channels */ + if ((MV_REG_READ(LCD_WINDOW_CTRL_REG(winNum)) & + LCDWCR_WIN_EN_MASK) != winEn) + { + mvOsPrintf("%s: ERR. Window enable field must be equal in " + "all channels(chan=%d)\n",__FUNCTION__, chan); + return MV_ERROR; + } + + + + lcdDecRegs.baseReg = MV_REG_READ(LCD_BASE_ADDR_REG(winNum)); + lcdDecRegs.sizeReg = MV_REG_READ(LCD_WINDOW_CTRL_REG(winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&lcdDecRegs, &pAddrDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (lcdDecRegs.sizeReg & LCDWCR_ATTR_MASK) >> LCDWCR_ATTR_OFFS; + targetAttrib.targetId = + (lcdDecRegs.sizeReg & LCDWCR_TARGET_MASK) >> LCDWCR_TARGET_OFFS; + + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + if(winEn) + { + pAddrDecWin->enable = MV_TRUE; + } + else pAddrDecWin->enable = MV_FALSE; + + return MV_OK; +} + +/******************************************************************************* +* mvLcdTargetWinEnable - Enable/disable a LCD address decode window +* +* DESCRIPTION: +* This function enable/disable a LCD address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling LCD accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvLcdTargetWinEnable(MV_U32 winNum, MV_BOOL enable) +{ + MV_LCD_DEC_WIN addrDecWin; + + /* Parameter checking */ + if (winNum >= LCD_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { + /* Get current window */ + if (MV_OK != mvLcdTargetWinGet(winNum, &addrDecWin)) + { + DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); + return MV_ERROR; + } + + /* Check for overlapping */ + if (MV_TRUE == lcdWinOverlapDetect(winNum, &(addrDecWin.addrWin))) + { + /* Overlap detected */ + DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); + return MV_ERROR; + } + + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_SET(LCD_WINDOW_CTRL_REG(winNum),LCDWCR_WIN_EN_MASK); + } + else + { + /* Disable address decode target window */ + MV_REG_BIT_RESET(LCD_WINDOW_CTRL_REG(winNum),LCDWCR_WIN_EN_MASK); + } + + return MV_OK; +} + +/******************************************************************************* +* mvXorPciRemap - Set XOR remap register for PCI address windows. +* +* DESCRIPTION: +* only Windows 0-3 can be remapped. +* +* INPUT: +* winNum - window number +* pAddrDecWin - pointer to address space window structure +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvLcdPciRemap(MV_U32 winNum, MV_U32 addrHigh) +{ + /* Parameter checking */ + if (winNum >= LCD_MAX_REMAP_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + + MV_REG_WRITE(LCD_ADDR_REMAP_REG(winNum), addrHigh); + + return MV_OK; +} + +/******************************************************************************* +* lcdWinOverlapDetect - Detect LCD address windows overlaping +* +* DESCRIPTION: +* An unpredicted behaviour is expected in case LCD address decode +* windows overlaps. +* This function detects LCD address decode windows overlaping of a +* specified window. The function does not check the window itself for +* overlaping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS lcdWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex; + MV_LCD_DEC_WIN addrDecWin; + + if (pAddrWin == NULL) + { + DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + + + for (winNumIndex = 0; winNumIndex < LCD_MAX_ADDR_DEC_WIN; winNumIndex++) + { + /* Do not check window itself */ + if (winNumIndex == winNum) + { + continue; + } + + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(LCD_WINDOW_CTRL_REG(winNumIndex)); + + /* Do not check disabled windows */ + if ((baseAddrEnableReg & LCDWCR_WIN_EN_MASK) == 0) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvLcdTargetWinGet(winNumIndex, &addrDecWin)) + { + DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + + return MV_FALSE; +} + +static MV_VOID mvLcdAddrDecShowUnit(void) +{ + MV_LCD_DEC_WIN win; + int i; + + mvOsOutput( "\n" ); + mvOsOutput( "LCD:\n"); + mvOsOutput( "----\n" ); + + for( i = 0; i < LCD_MAX_ADDR_DEC_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_LCD_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvLcdTargetWinGet(i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + +/******************************************************************************* +* mvLcdAddrDecShow - Print the LCD address decode map. +* +* DESCRIPTION: +* This function print the LCD address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvLcdAddrDecShow(MV_VOID) +{ + if(mvCtrlModelGet() != MV_6282_DEV_ID) + return; + + mvLcdAddrDecShowUnit(); +} diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysLCD.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysLCD.h new file mode 100644 index 0000000..cc30ccc --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysLCD.h @@ -0,0 +1,125 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCMVSysLCDh +#define __INCMVSysLCDh + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ctrlEnv/sys/mvCpuIf.h" + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#define LCD_MAX_ADDR_DEC_WIN 5 /* Maximum address decode windows */ +#define LCD_MAX_REMAP_WIN 5 /* Maximum address arbiter windows */ + +/* LCD Engine Address Decoding Register Map */ +#define LCD_WINDOW_CTRL_REG(winNum) (LCD_UNIT_BASE+((winNum) * 0x10)) +#define LCD_BASE_ADDR_REG(winNum) (LCD_UNIT_BASE + (0x4 + ((winNum) * 0x10))) +#define LCD_ADDR_REMAP_REG(winNum) (LCD_UNIT_BASE + (0xC + ((winNum) * 0x10))) + +/* LCD Window Control Registers (LCDWCR) */ +#define LCDWCR_WIN_EN_OFFS (0) +#define LCDWCR_WIN_EN_MASK (1 << LCDWCR_WIN_EN_OFFS) +#define LCDWCR_WIN_EN_ENABLE (1 << LCDWCR_WIN_EN_OFFS) +#define LCDWCR_WIN_EN_DISABLE (0 << LCDWCR_WIN_EN_OFFS) +#define LCDWCR_TARGET_OFFS (4) +#define LCDWCR_TARGET_MASK (0xF << LCDWCR_TARGET_OFFS) +#define LCDWCR_ATTR_OFFS (8) +#define LCDWCR_ATTR_MASK (0xFF << LCDWCR_ATTR_OFFS) +#define LCDWCR_SIZE_MASK_OFFS (16) +#define LCDWCR_SIZE_MASK_MASK (0xFFFF << LCDWCR_SIZE_MASK_OFFS) + +/* LCD Base Address Registers (LCDWBR) */ +#define LCDWBR_BASE_OFFS (16) +#define LCDWBR_BASE_MASK (0xFFFF << LCDWBR_BASE_OFFS) + +/* LCD Address Remap Register (LCDARR) */ +#define LCDARR_REMAP_OFFS (0) +#define LCDARR_REMAP_MASK (0xFFFFFFFF << LCDARR_REMAP_OFFS) + +typedef struct _mvLcdDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_LCD_DEC_WIN; + +MV_STATUS mvLcdInit (MV_VOID); +MV_STATUS mvLcdTargetWinSet(MV_U32 winNum, MV_LCD_DEC_WIN *pAddrDecWin); +MV_STATUS mvLcdTargetWinGet(MV_U32 winNum, MV_LCD_DEC_WIN *pAddrDecWin); +MV_STATUS mvLcdTargetWinEnable(MV_U32 winNum, MV_BOOL enable); + +MV_VOID mvLcdAddrDecShow(MV_VOID); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysPex.c b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysPex.c new file mode 100644 index 0000000..b0cb466 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysPex.c @@ -0,0 +1,1697 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/sys/mvSysPex.h" + +/* this structure describes the mapping between a Pex Window and a CPU target*/ +typedef struct _pexWinToTarget +{ + MV_TARGET target; + MV_BOOL enable; + +}PEX_WIN_TO_TARGET; + +/* this array is a priority array that define How Pex windows should be +configured , We have only 6 Pex Windows that can be configured , but we +have maximum of 9 CPU target windows ! the following array is a priority +array where the lowest index has the highest priotiy and the highest +index has the lowest priority of being cnfigured */ + +MV_U32 pexDevBarPrioTable[] = +{ +#if defined(MV_INCLUDE_DEVICE_CS0) + DEVICE_CS0, +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEVICE_CS1, +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEVICE_CS2, +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEVICE_CS3, +#endif +/* +#if defined(MV_INCLUDE_DEVICE_CS4) + DEVICE_CS4, +#endif +*/ + TBL_TERM +}; + + +/* PEX Wins registers offsets are inconsecutive. This struct describes WIN */ +/* register offsets and its function where its is located. */ +/* Also, PEX address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _pexWinRegInfo +{ + MV_U32 baseLowRegOffs; + MV_U32 baseHighRegOffs; + MV_U32 sizeRegOffs; + MV_U32 remapLowRegOffs; + MV_U32 remapHighRegOffs; + +}PEX_WIN_REG_INFO; + +static MV_STATUS pexWinOverlapDetect(MV_U32 pexIf, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin); +static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, MV_U32 winNum, + PEX_WIN_REG_INFO *pWinRegInfo); + +static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size); + +static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf,MV_ADDR_WIN *pAddrWin); +static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf,MV_U32 barNum, + MV_ADDR_WIN *pAddrWin); +const MV_8* pexBarNameGet( MV_U32 bar ); + + +/******************************************************************************* +* mvPexInit - Initialize PEX interfaces +* +* DESCRIPTION: +* +* This function is responsible of intialization of the Pex Interface , It +* configure the Pex Bars and Windows in the following manner: +* +* Assumptions : +* Bar0 is always internal registers bar +* Bar1 is always the DRAM bar +* Bar2 is always the Device bar +* +* 1) Sets the Internal registers bar base by obtaining the base from +* the CPU Interface +* 2) Sets the DRAM bar base and size by getting the base and size from +* the CPU Interface when the size is the sum of all enabled DRAM +* chip selects and the base is the base of CS0 . +* 3) Sets the Device bar base and size by getting these values from the +* CPU Interface when the base is the base of the lowest base of the +* Device chip selects, and the +* +* +* INPUT: +* +* pexIf - PEX interface number. +* +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM +* +*******************************************************************************/ +MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType) +{ + MV_U32 bar; + MV_U32 winNum; + MV_PEX_BAR pexBar; + MV_PEX_DEC_WIN pexWin; + MV_CPU_DEC_WIN addrDecWin; + MV_TARGET target; + MV_U32 pexCurrWin=0; + MV_U32 status; + /* default and exapntion rom + are always configured */ + +#ifndef MV_DISABLE_PEX_DEVICE_BAR + MV_U32 winIndex; + MV_U32 maxBase=0, sizeOfMaxBase=0; + MV_U32 pexStartWindow; +#endif + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + /* Enabled CPU access to PCI-Express */ + mvCpuIfEnablePex(pexIf, pexType); + + /* Start with bars */ + /* First disable all PEX bars*/ + for (bar = 0; bar < PEX_MAX_BARS; bar++) + { + if (PEX_INTER_REGS_BAR != bar) + { + if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) + { + mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); + return MV_ERROR; + } + + } + + } + + /* and disable all PEX target windows */ + for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) + { + mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", + winNum); + return MV_ERROR; + + } + } + + /* Now, go through all bars*/ + + + +/******************************************************************************/ +/* Internal registers bar */ +/******************************************************************************/ + bar = PEX_INTER_REGS_BAR; + + /* we only open the bar , no need to open windows for this bar */ + + /* first get the CS attribute from the CPU Interface */ + if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) + { + mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); + return MV_ERROR; + } + + pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexBar.addrWin.size = addrDecWin.addrWin.size; + pexBar.enable = MV_TRUE; + + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + +/******************************************************************************/ +/* DRAM bar */ +/******************************************************************************/ + + bar = PEX_DRAM_BAR; + + pexBar.addrWin.size = 0; + + for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) + { + + status = mvCpuIfTargetWinGet(target,&addrDecWin); + + if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) + { + continue; + } + + /* first get attributes from CPU If */ + if (MV_OK != status) + { + mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); + return MV_ERROR; + } + if (addrDecWin.enable == MV_TRUE) + { + /* the base is the base of DRAM CS0 always */ + if (SDRAM_CS0 == target ) + { + pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + + } + + /* increment the bar size to be the sum of the size of all + DRAM chips selecs */ + pexBar.addrWin.size += addrDecWin.addrWin.size; + + /* set a Pex window for this target ! + DRAM CS always will have a Pex Window , and is not a + part of the priority table */ + pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexWin.addrWin.size = addrDecWin.addrWin.size; + + /* we disable the windows at first because we are not + sure that it is witihin bar boundries */ + pexWin.enable =MV_FALSE; + pexWin.target = target; + pexWin.targetBar = bar; + + if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) + { + mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); + return MV_ERROR; + } + } + } + + /* check if the size of the bar is illeggal */ + if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) + { + /* try to get a good size */ + pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, + PXBCR_BAR_SIZE_ALIGNMENT); + } + + /* check if the size and base are valid */ + if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) + { + mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); + mvOsPrintf("it will be disabled\n"); + mvOsPrintf("please check Pex and CPU windows configuration\n"); + } + else + { + pexBar.enable = MV_TRUE; + + /* configure the bar */ + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + + /* after the bar was configured then we enable the Pex windows*/ + for (winNum = 0;winNum < pexCurrWin ;winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) + { + mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); + return MV_ERROR; + } + + } + } + +/******************************************************************************/ +/* DEVICE bar */ +/******************************************************************************/ + +/* Open the Device BAR for non linux only */ +#ifndef MV_DISABLE_PEX_DEVICE_BAR + + /* then device bar*/ + bar = PEX_DEVICE_BAR; + + /* save the starting window */ + pexStartWindow = pexCurrWin; + pexBar.addrWin.size = 0; + pexBar.addrWin.baseLow = 0xffffffff; + pexBar.addrWin.baseHigh = 0; + maxBase = 0; + + for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) + { + status = mvCpuIfTargetWinGet(target,&addrDecWin); + + if (MV_NO_SUCH == status) + { + continue; + } + + if (MV_OK != status) + { + mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); + return MV_ERROR; + } + + if (addrDecWin.enable == MV_TRUE) + { + /* get the minimum base */ + if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) + { + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + } + + /* get the maximum base */ + if (addrDecWin.addrWin.baseLow > maxBase) + { + maxBase = addrDecWin.addrWin.baseLow; + sizeOfMaxBase = addrDecWin.addrWin.size; + } + + /* search in the priority table for this target */ + for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; + winIndex++) + { + if (pexDevBarPrioTable[winIndex] != target) + { + continue; + } + else if (pexDevBarPrioTable[winIndex] == target) + { + /*found it */ + + /* if the index of this target in the prio table is valid + then we set the Pex window for this target, a valid index is + an index that is lower than the number of the windows that + was not configured yet */ + + /* we subtract 2 always because the default and expantion + rom windows are always configured */ + if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) + { + /* set a Pex window for this target ! */ + pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexWin.addrWin.size = addrDecWin.addrWin.size; + + /* we disable the windows at first because we are not + sure that it is witihin bar boundries */ + pexWin.enable = MV_FALSE; + pexWin.target = target; + pexWin.targetBar = bar; + + if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, + &pexWin)) + { + mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); + return MV_ERROR; + } + } + } + } + } + } + + pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; + pexBar.enable = MV_TRUE; + + /* check if the size of the bar is illegal */ + if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) + { + /* try to get a good size */ + pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, + PXBCR_BAR_SIZE_ALIGNMENT); + } + + /* check if the size and base are valid */ + if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) + { + mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); + mvOsPrintf("it will be disabled\n"); + mvOsPrintf("please check Pex and CPU windows configuration\n"); + } + else + { + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + + /* now enable the windows */ + for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) + { + mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", + winNum); + return MV_ERROR; + } + } + } + +#endif + + return mvPexHalInit(pexIf, pexType); + +} + +/******************************************************************************* +* mvPexTargetWinSet - Set PEX to peripheral target address window BAR +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if PEX BAR target window was set correctly, +* MV_BAD_PARAM on bad params +* MV_ERROR otherwise +* (e.g. address window overlapps with other active PEX target window). +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin) +{ + + MV_DEC_REGS decRegs; + PEX_WIN_REG_INFO winRegInfo; + MV_TARGET_ATTRIB targetAttribs; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf,winNum,&winRegInfo); + + + if (MV_TRUE == pAddrDecWin->enable) + { + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); + return MV_BAD_PARAM; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) + { + mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", + winNum); + return MV_BAD_PARAM; + } + + } + + + + /* read base register*/ + + if (winRegInfo.baseLowRegOffs) + { + decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); + } + else + { + decRegs.baseReg = 0; + } + + if (winRegInfo.sizeRegOffs) + { + decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); + } + else + { + decRegs.sizeReg =0; + } + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + /* enable\Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + decRegs.sizeReg |= PXWCR_WIN_EN; + } + else + { + decRegs.sizeReg &= ~PXWCR_WIN_EN; + } + + + /* clear bit location */ + decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; + + /* set bar Mapping */ + if (pAddrDecWin->targetBar == 1) + { + decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; + } + else if (pAddrDecWin->targetBar == 2) + { + decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; + decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; + /* set target ID */ + decRegs.sizeReg &= ~PXWCR_TARGET_MASK; + decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; + + + /* 3) Write to address decode Base Address Register */ + + if (winRegInfo.baseLowRegOffs) + { + MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); + } + + /* write size reg */ + if (winRegInfo.sizeRegOffs) + { + if ((MV_PEX_WIN_DEFAULT == winNum)|| + (MV_PEX_WIN_EXP_ROM == winNum)) + { + /* clear size because there is no size field*/ + decRegs.sizeReg &= ~PXWCR_SIZE_MASK; + + /* clear enable because there is no enable field*/ + decRegs.sizeReg &= ~PXWCR_WIN_EN; + + } + + MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); + } + + + return MV_OK; + +} + +/******************************************************************************* +* mvPexTargetWinGet - Get PEX to peripheral target address window +* +* DESCRIPTION: +* Get the PEX to peripheral target address window BAR. +* +* INPUT: +* pexIf - PEX interface number. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* pAddrBarWin - PEX target window information data structure. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttrib; + MV_DEC_REGS decRegs; + + PEX_WIN_REG_INFO winRegInfo; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf,winNum,&winRegInfo); + + /* read base register*/ + if (winRegInfo.baseLowRegOffs) + { + decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); + } + else + { + decRegs.baseReg = 0; + } + + /* read size reg */ + if (winRegInfo.sizeRegOffs) + { + decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); + } + else + { + decRegs.sizeReg =0; + } + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + + } + + if (decRegs.sizeReg & PXWCR_WIN_EN) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + + } + + + #if 0 + if (-1 == pAddrDecWin->addrWin.size) + { + return MV_ERROR; + } + #endif + + + /* get target bar */ + if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) + { + pAddrDecWin->targetBar = 1; + } + else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == + PXWCR_WIN_BAR_MAP_BAR2 ) + { + pAddrDecWin->targetBar = 2; + } + + /* attrib and targetId */ + pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> + PXWCR_ATTRIB_OFFS; + pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> + PXWCR_TARGET_OFFS; + + targetAttrib.attrib = pAddrDecWin->attrib; + targetAttrib.targetId = pAddrDecWin->targetId; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; + +} + + +/******************************************************************************* +* mvPexTargetWinEnable - Enable/disable a PEX BAR window +* +* DESCRIPTION: +* This function enable/disable a PEX BAR window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling PEX accesses for that BAR (before enabling the +* window it is tested for overlapping). Otherwise, the window will +* be disabled. +* +* INPUT: +* pexIf - PEX interface number. +* bar - BAR to be accessed by slave. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) +{ + PEX_WIN_REG_INFO winRegInfo; + MV_PEX_DEC_WIN addrDecWin; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); + return MV_BAD_PARAM; + } + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf,winNum,&winRegInfo); + + + /* if the address windows is disabled , we only disable the appropriare + pex window and ignore other settings */ + + if (MV_FALSE == enable) + { + + /* this is not relevant to default and expantion rom + windows */ + if (winRegInfo.sizeRegOffs) + { + if ((MV_PEX_WIN_DEFAULT != winNum)&& + (MV_PEX_WIN_EXP_ROM != winNum)) + { + MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); + } + } + + } + else + { + if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) + { + mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); + return MV_ERROR; + } + + /* Check if the requested window overlaps with current windows */ + if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) + { + mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); + return MV_BAD_PARAM; + } + + if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) + { + mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", + winNum); + return MV_BAD_PARAM; + } + + + /* this is not relevant to default and expantion rom + windows */ + if (winRegInfo.sizeRegOffs) + { + if ((MV_PEX_WIN_DEFAULT != winNum)&& + (MV_PEX_WIN_EXP_ROM != winNum)) + { + MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); + } + } + + + } + + return MV_OK; + +} + + + +/******************************************************************************* +* mvPexTargetWinRemap - Set PEX to target address window remap. +* +* DESCRIPTION: +* The PEX interface supports remap of the BAR original address window. +* For each BAR it is possible to define a remap address. For example +* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified +* according to remap register but will also be targeted to the +* SDRAM CS[0]. +* +* INPUT: +* pexIf - PEX interface number. +* bar - Peripheral target enumerator accessed by slave. +* pAddrWin - Address window to be checked. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_REMAP_WIN *pAddrWin) +{ + + PEX_WIN_REG_INFO winRegInfo; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", + pexIf); + return MV_BAD_PARAM; + } + if (MV_PEX_WIN_DEFAULT == winNum) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", + winNum); + return MV_BAD_PARAM; + + } + + if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) + { + mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + pexIf, + winNum, + pAddrWin->addrWin.baseLow, + pAddrWin->addrWin.size); + + return MV_ERROR; + } + + pexWinRegInfoGet(pexIf, winNum, &winRegInfo); + + /* Set remap low register value */ + MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); + + /* Skip base high settings if the BAR has only base low (32-bit) */ + if (0 != winRegInfo.remapHighRegOffs) + { + MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); + } + + + if (pAddrWin->enable == MV_TRUE) + { + MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + else + { + MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* mvPexTargetWinRemapEnable - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + +MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, + MV_BOOL enable) +{ + PEX_WIN_REG_INFO winRegInfo; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", + pexIf); + return MV_BAD_PARAM; + } + if (MV_PEX_WIN_DEFAULT == winNum) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", + winNum); + return MV_BAD_PARAM; + + } + + + pexWinRegInfoGet(pexIf, winNum, &winRegInfo); + + if (enable == MV_TRUE) + { + MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + else + { + MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + + return MV_OK; + +} + +/******************************************************************************* +* mvPexBarSet - Set PEX bar address and size +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexBarSet(MV_U32 pexIf, + MV_U32 barNum, + MV_PEX_BAR *pAddrWin) +{ + MV_U32 regBaseLow; + MV_U32 regSize,sizeToReg; + + + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + + if (pAddrWin->addrWin.size == 0) + { + mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); + return MV_BAD_PARAM; + } + + + /* Check if the window complies with PEX spec */ + if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, + pAddrWin->addrWin.size)) + { + mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); + return MV_BAD_PARAM; + } + + /* 2) Check if the requested bar overlaps with current bars */ + if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) + { + mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); + return MV_BAD_PARAM; + } + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); + + /* Read bar size */ + if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ + { + regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); + return MV_BAD_PARAM; + } + + regSize &= ~PXBCR_BAR_SIZE_MASK; + regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; + + MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); + + } + + /* set size */ + + + + /* Read base address low */ + regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, + PEX_MV_BAR_BASE(barNum))); + + /* clear current base */ + if (PEX_INTER_REGS_BAR == barNum) + { + regBaseLow &= ~PXBIR_BASE_MASK; + regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); + } + else + { + regBaseLow &= ~PXBR_BASE_MASK; + regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); + } + + /* if we had a previous value that contain the bar type (MeM\IO), we want to + restore it */ + regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; + + + + /* write base low */ + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), + regBaseLow); + + if (pAddrWin->addrWin.baseHigh != 0) + { + /* Read base address high */ + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), + pAddrWin->addrWin.baseHigh); + + } + + /* lastly enable the Bar */ + if (pAddrWin->enable == MV_TRUE) + { + if (PEX_INTER_REGS_BAR != barNum) /* internal registers + are enabled always */ + { + MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + } + } + else if (MV_FALSE == pAddrWin->enable) + { + if (PEX_INTER_REGS_BAR != barNum) /* internal registers + are enabled always */ + { + MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + } + + } + + + + return MV_OK; +} + + +/******************************************************************************* +* mvPexBarGet - Get PEX bar address and size +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + +MV_STATUS mvPexBarGet(MV_U32 pexIf, + MV_U32 barNum, + MV_PEX_BAR *pAddrWin) +{ + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + /* read base low */ + pAddrWin->addrWin.baseLow = + MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); + + + if (PEX_INTER_REGS_BAR == barNum) + { + pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; + } + else + { + pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; + } + + + /* read base high */ + pAddrWin->addrWin.baseHigh = + MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); + + + /* Read bar size */ + if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ + { + pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); + + /* check if enable or not */ + if (pAddrWin->addrWin.size & PXBCR_BAR_EN) + { + pAddrWin->enable = MV_TRUE; + } + else + { + pAddrWin->enable = MV_FALSE; + } + + /* now get the size */ + pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; + pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; + + pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, + PXBCR_BAR_SIZE_ALIGNMENT); + + } + else /* PEX_INTER_REGS_BAR */ + { + pAddrWin->addrWin.size = INTER_REGS_SIZE; + pAddrWin->enable = MV_TRUE; + } + + + return MV_OK; +} + +/******************************************************************************* +* mvPexBarEnable - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + + +MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) +{ + + MV_PEX_BAR pexBar; + + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + if (PEX_INTER_REGS_BAR == barNum) + { + if (MV_TRUE == enable) + { + return MV_OK; + } + else + { + return MV_ERROR; + } + } + + + if (MV_FALSE == enable) + { + /* disable bar and quit */ + MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + return MV_OK; + } + + /* else */ + + if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) + { + mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); + return MV_ERROR; + + } + + if (MV_TRUE == pexBar.enable) + { + /* it is already enabled !!! */ + return MV_OK; + } + + /* else enable the bar*/ + + pexBar.enable = MV_TRUE; + + if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) + { + mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); + return MV_ERROR; + + } + + return MV_OK; +} + + +/******************************************************************************* +* pexWinOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PEX BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, + MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 win; + MV_PEX_DEC_WIN addrDecWin; + + + for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) + { + /* don't check our target or illegal targets */ + if (winNum == win) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) + { + mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", + win); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", + winNum, win); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* pexIsWinWithinBar - Detect if address is within PEX bar boundries +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 bar; + MV_PEX_BAR addrDecWin; + + for(bar = 0; bar < PEX_MAX_BARS; bar++) + { + + /* Get window parameters */ + if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) + { + mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled bars */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + + if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) + { + return MV_TRUE; + } + } + + return MV_FALSE; + +} + +/******************************************************************************* +* pexBarOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PEX BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, + MV_U32 barNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 bar; + MV_PEX_BAR barDecWin; + + + for(bar = 0; bar < PEX_MAX_BARS; bar++) + { + /* don't check our target or illegal targets */ + if (barNum == bar) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) + { + mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* don'nt check disabled bars */ + if (barDecWin.enable == MV_FALSE) + { + continue; + } + + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) + { + mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", + barNum, bar); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* pexBarIsValid - Check if the given address window is valid +* +* DESCRIPTION: +* PEX spec restrict BAR base to be aligned to BAR size. +* This function checks if the given address window is valid. +* +* INPUT: +* baseLow - 32bit low base address. +* size - Window size. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the address window is valid, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) +{ + + /* PCI spec restrict BAR base to be aligned to BAR size */ + if(MV_IS_NOT_ALIGN(baseLow, size)) + { + return MV_ERROR; + } + else + { + return MV_TRUE; + } + + return MV_TRUE; +} + +/******************************************************************************* +* pexBarRegInfoGet - Get BAR register information +* +* DESCRIPTION: +* PEX BARs registers offsets are inconsecutive. +* This function gets a PEX BAR register information like register offsets +* and function location of the BAR. +* +* INPUT: +* pexIf - PEX interface number. +* bar - The PEX BAR in question. +* +* OUTPUT: +* pBarRegInfo - BAR register info struct. +* +* RETURN: +* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK +* +*******************************************************************************/ +static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, + MV_U32 winNum, + PEX_WIN_REG_INFO *pWinRegInfo) +{ + + if ((winNum >= 0)&&(winNum <=3)) + { + pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); + pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); + pWinRegInfo->remapHighRegOffs = 0; + } + else if ((winNum >= 4)&&(winNum <=5)) + { + pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); + pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); + pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); + + } + else if (MV_PEX_WIN_DEFAULT == winNum) + { + pWinRegInfo->baseLowRegOffs = 0; + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); + pWinRegInfo->remapLowRegOffs = 0; + pWinRegInfo->remapHighRegOffs = 0; + } + else if (MV_PEX_WIN_EXP_ROM == winNum) + { + pWinRegInfo->baseLowRegOffs = 0; + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); + pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); + pWinRegInfo->remapHighRegOffs = 0; + + } + + return MV_OK; +} + +/******************************************************************************* +* pexBarNameGet - Get the string name of PEX BAR. +* +* DESCRIPTION: +* This function get the string name of PEX BAR. +* +* INPUT: +* bar - PEX bar number. +* +* OUTPUT: +* None. +* +* RETURN: +* pointer to the string name of PEX BAR. +* +*******************************************************************************/ +const MV_8* pexBarNameGet( MV_U32 bar ) +{ + switch( bar ) + { + case PEX_INTER_REGS_BAR: + return "Internal Regs Bar0...."; + case PEX_DRAM_BAR: + return "DRAM Bar1............."; + case PEX_DEVICE_BAR: + return "Devices Bar2.........."; + default: + return "Bar unknown"; + } +} +/******************************************************************************* +* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). +* +* DESCRIPTION: +* This function print the PEX address decode map (BARs and windows). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvPexAddrDecShow(MV_VOID) +{ + MV_PEX_BAR pexBar; + MV_PEX_DEC_WIN win; + MV_U32 pexIf; + MV_U32 bar,winNum; + + for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) + { + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; + mvOsOutput( "\n" ); + mvOsOutput( "PEX%d:\n", pexIf ); + mvOsOutput( "-----\n" ); + + mvOsOutput( "\nPex Bars \n\n"); + + for( bar = 0; bar < PEX_MAX_BARS; bar++ ) + { + memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); + + mvOsOutput( "%s ", pexBarNameGet(bar) ); + + if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) + { + if( pexBar.enable ) + { + mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); + mvSizePrint( pexBar.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } + mvOsOutput( "\nPex Decode Windows\n\n"); + + for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) + { + memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "win%d - ", winNum ); + + if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) + { + if (win.enable) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + + + } + } + + memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "default win - " ); + + if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) + { + mvOsOutput( "%s ", + mvCtrlTargetNameGet(win.target) ); + mvOsOutput( "\n" ); + } + memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "Expansion ROM - " ); + + if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) + { + mvOsOutput( "%s ", + mvCtrlTargetNameGet(win.target) ); + mvOsOutput( "\n" ); + } + + } +} + + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysPex.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysPex.h new file mode 100644 index 0000000..0455be8 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysPex.h @@ -0,0 +1,348 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCSysPEXH +#define __INCSysPEXH + +#include "mvCommon.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* 4KB granularity */ +#define MINIMUM_WINDOW_SIZE 0x1000 +#define MINIMUM_BAR_SIZE 0x1000 +#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 +#define BAR_SIZE_OFFS 12 +#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) + + + +#define MV_PEX_WIN_DEFAULT 6 +#define MV_PEX_WIN_EXP_ROM 7 +#define PEX_MAX_TARGET_WIN 8 + + +#define PEX_MAX_BARS 3 +#define PEX_INTER_REGS_BAR 0 +#define PEX_DRAM_BAR 1 +#define PEX_DEVICE_BAR 2 + +/*************************************/ +/* PCI Express BAR Control Registers */ +/*************************************/ +#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4 + (pexIf)*0x4000) +#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C + (pexIf)*0x4000) + + +/* PCI Express BAR Control Register */ +/* PEX_BAR_CTRL_REG (PXBCR) */ + +#define PXBCR_BAR_EN BIT0 +#define PXBCR_BAR_SIZE_OFFS 16 +#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) +#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 + + + +/* PCI Express Expansion ROM BAR Control Register */ +/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ + +#define PXERBCR_EXPROM_EN BIT0 +#define PXERBCR_EXPROMSZ_OFFS 19 +#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) + +/************************************************/ +/* PCI Express Address Window Control Registers */ +/************************************************/ +#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ + (0x41820 + (winNum) * 0x10 + (pexIf) * 0x4000) +#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ + (0x41824 + (winNum) * 0x10 + (pexIf) * 0x4000) +#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ + (0x4182C + (winNum) * 0x10 + (pexIf) * 0x4000) +#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ + (0x41860 + (winNum - 4) * 0x20 + (pexIf) * 0x4000) +#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ + (0x41864 + (winNum - 4) * 0x20 + (pexIf) * 0x4000) +#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ + (0x4186C + (winNum - 4) * 0x20 + (pexIf) * 0x4000) +#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ + (0x41870 + (winNum - 4) * 0x20 + (pexIf) * 0x4000) + +#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 + (pexIf) * 0x4000) +#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 + (pexIf) * 0x4000) +#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 + (pexIf) * 0x4000) + +/* PCI Express Window Control Register */ +/* PEX_WIN_CTRL_REG (PXWCR) */ + +#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ + +#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ +#define PXWCR_WIN_BAR_MAP_MASK BIT1 +#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) +#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) + +#define PXWCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) + +#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) + +#define PXWCR_SIZE_OFFS 16 /* size */ +#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) +#define PXWCR_SIZE_ALIGNMENT 0x10000 + +/* PCI Express Window Base Register */ +/* PEX_WIN_BASE_REG (PXWBR)*/ + +#define PXWBR_BASE_OFFS 16 /* address[31:16] */ +#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) +#define PXWBR_BASE_ALIGNMENT 0x10000 + +/* PCI Express Window Remap Register */ +/* PEX_WIN_REMAP_REG (PXWRR)*/ + +#define PXWRR_REMAP_EN BIT0 +#define PXWRR_REMAP_OFFS 16 +#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) +#define PXWRR_REMAP_ALIGNMENT 0x10000 + +/* PCI Express Window Remap (High) Register */ +/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ + +#define PXWRHR_REMAP_HIGH_OFFS 0 +#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) + +/* PCI Express Default Window Control Register */ +/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ + +#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) +#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) + +/* PCI Express Expansion ROM Window Control Register */ +/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ + +#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) +#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) + +/* PCI Express Expansion ROM Window Remap Register */ +/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ + +#define PXWERRR_REMAP_EN BIT0 +#define PXWERRR_REMAP_OFFS 16 +#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) +#define PXWERRR_REMAP_ALIGNMENT 0x10000 + + + +/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ +/* PCI Express BAR0 Internal Register*/ +/*PEX BAR0_INTER_REG (PXBIR)*/ + +#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ + +#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) +#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) +#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) + +#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ + +#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ +#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) +#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) + + +/* PCI Express BAR0 Internal (High) Register*/ +/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ + +#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ +#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) + + +#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ +#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB +#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB +#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB + + +/* PCI Express BAR1 Register */ +/* PCI Express BAR2 Register*/ +/*PEX BAR1_REG (PXBR)*/ +/*PEX BAR2_REG (PXBR)*/ + +#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ + +#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) +#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) +#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) + +#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ + +#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ +#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) +#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) + + +/* PCI Express BAR1 (High) Register*/ +/* PCI Express BAR2 (High) Register*/ +/*PEX BAR1_REG_HIGH (PXBRH)*/ +/*PEX BAR2_REG_HIGH (PXBRH)*/ + +#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ +#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) + +/* PCI Express Expansion ROM BAR Register*/ +/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ + +#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ + +#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) + +#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) + +#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) + +#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) + +/* PEX Bar attributes */ +typedef struct _mvPexBar +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_PEX_BAR; + +/* PEX Remap Window attributes */ +typedef struct _mvPexRemapWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_PEX_REMAP_WIN; + +/* PEX Remap Window attributes */ +typedef struct _mvPexDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_U32 targetBar; + MV_U8 attrib; /* chip select attributes */ + MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_PEX_DEC_WIN; + +/* Global Functions prototypes */ +/* mvPexHalInit - Initialize PEX interfaces*/ +MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); + + +/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ +MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin); + +/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ +MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin); + +/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ +MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); + +/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ +MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_REMAP_WIN *pAddrWin); + +/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ +MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, + MV_BOOL enable); + +/* mvPexBarSet - Set PEX bar address and size */ +MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); + +/* mvPexBarGet - Get PEX bar address and size */ +MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); + +/* mvPexBarEnable - enable\disable a PEX bar*/ +MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); + +/* mvPexAddrDecShow - Display address decode windows attributes */ +MV_VOID mvPexAddrDecShow(MV_VOID); + +#endif diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysSata.c b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysSata.c new file mode 100644 index 0000000..f100a12 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysSata.c @@ -0,0 +1,430 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "sata/CoreDriver/mvRegs.h" +#include "ctrlEnv/sys/mvSysSata.h" + +MV_TARGET sataAddrDecPrioTab[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif + TBL_TERM +}; + + +/******************************************************************************* +* sataWinOverlapDetect - Detect SATA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case SATA address decode +* windows overlapps. +* This function detects SATA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_SATA_DEC_WIN addrDecWin; + + for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = 0; + decRegs.sizeReg = 0; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; + decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); + + /* set target ID */ + decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; + decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); + + if (pAddrDecWin->enable == MV_TRUE) + { + decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; + } + else + { + decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; + } + + MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); + MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvSataWinGet - Get SATA peripheral target address window. +* +* DESCRIPTION: +* Get SATA peripheral target address window. +* +* INPUT: +* winNum - SATA target address decode window number. +* +* OUTPUT: +* pAddrDecWin - SATA target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", + __FUNCTION__, dev, winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); + decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) + { + mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> + MV_SATA_WIN_ATTR_OFFSET; + targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> + MV_SATA_WIN_TARGET_OFFSET; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + return MV_OK; +} +/******************************************************************************* +* mvSataAddrDecShow - Print the SATA address decode map. +* +* DESCRIPTION: +* This function print the SATA address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvSataAddrDecShow(MV_VOID) +{ + + MV_SATA_DEC_WIN win; + int i,j; + + + + for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) + { + if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) + return; + + mvOsOutput( "\n" ); + mvOsOutput( "SATA %d:\n", j ); + mvOsOutput( "----\n" ); + + for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvSataWinGet(j, i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } + } +} + + +/******************************************************************************* +* mvSataWinInit - Initialize the integrated SATA target address window. +* +* DESCRIPTION: +* Initialize the SATA peripheral target address window. +* +* INPUT: +* +* +* OUTPUT: +* +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSataWinInit(MV_VOID) +{ + int winNum; + MV_SATA_DEC_WIN sataWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 status, winPrioIndex = 0; + + /* Initiate Sata address decode */ + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); + regVal &= ~MV_SATA_WIN_ENABLE_MASK; + MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); + } + + winNum = 0; + while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && + (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) + { + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], + &cpuAddrDecWin); + + if(MV_NO_SUCH == status) + { + winPrioIndex++; + continue; + } + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; + sataWin.enable = MV_TRUE; + sataWin.target = sataAddrDecPrioTab[winPrioIndex]; + + if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) + { + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} + + + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysSata.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysSata.h new file mode 100644 index 0000000..325fb8d --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysSata.h @@ -0,0 +1,128 @@ + +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCMVSysSataAddrDech +#define __INCMVSysSataAddrDech + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct _mvSataDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +} MV_SATA_DEC_WIN; + + +#define MV_SATA_MAX_ADDR_DECODE_WIN 4 + +#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) +#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) + +/* BITs in Bridge Interrupt Cause and Mask registers */ +#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 +#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = 0; + decRegs.sizeReg = 0; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; + decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); + + /* set target ID */ + decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; + decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); + + if (pAddrDecWin->enable == MV_TRUE) + { + decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; + } + else + { + decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; + } + + MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); + MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvSdmmcWinGet - Get SDMMC peripheral target address window. +* +* DESCRIPTION: +* Get SDMMC peripheral target address window. +* +* INPUT: +* winNum - SDMMC target address decode window number. +*d +* OUTPUT: +* pAddrDecWin - SDMMC target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", + __FUNCTION__, dev, winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); + decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) + { + mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> + MV_SDMMC_WIN_ATTR_OFFSET; + targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> + MV_SDMMC_WIN_TARGET_OFFSET; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + return MV_OK; +} +/******************************************************************************* +* mvSdmmcAddrDecShow - Print the SDMMC address decode map. +* +* DESCRIPTION: +* This function print the SDMMC address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvSdmmcAddrDecShow(MV_VOID) +{ + + MV_SDMMC_DEC_WIN win; + int i,j=0; + + + + if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) + return; + + mvOsOutput( "\n" ); + mvOsOutput( "SDMMC %d:\n", j ); + mvOsOutput( "----\n" ); + + for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + + +/******************************************************************************* +* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. +* +* DESCRIPTION: +* Initialize the SDMMC peripheral target address window. +* +* INPUT: +* +* +* OUTPUT: +* +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSdmmcWinInit(MV_VOID) +{ + int winNum; + MV_SDMMC_DEC_WIN sdmmcWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 status, winPrioIndex = 0; + + /* Initiate Sdmmc address decode */ + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); + regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; + MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); + } + + winNum = 0; + while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && + (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) + { + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], + &cpuAddrDecWin); + + if(MV_NO_SUCH == status) + { + winPrioIndex++; + continue; + } + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; + sdmmcWin.enable = MV_TRUE; + sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; + + if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) + { + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} + + + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysSdmmc.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysSdmmc.h new file mode 100644 index 0000000..4c50a2b --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysSdmmc.h @@ -0,0 +1,125 @@ + +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCMVSysSdmmcAddrDech +#define __INCMVSysSdmmcAddrDech + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct _mvSdmmcDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +} MV_SDMMC_DEC_WIN; + + +#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 + +#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) +#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) + + +/* BITs in Windows 0-3 Control and Base Registers */ +#define MV_SDMMC_WIN_ENABLE_BIT 0 +#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = 0; + decRegs.sizeReg = 0; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* for the safe side we disable the window before writing the new + values */ + mvTdmWinEnable(winNum, MV_FALSE); + + ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); + ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); + ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); + + /* Write to address base and control registers */ + MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); + MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + { + mvTdmWinEnable(winNum, MV_TRUE); + } + return MV_OK; +} + +/******************************************************************************* +* mvTdmWinGet - Get peripheral target address window. +* +* DESCRIPTION: +* Get TDM peripheral target address window. +* +* INPUT: +* winNum - TDM to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - TDM target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ + +MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) +{ + + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); + decRegs.sizeReg = MV_REG_READ(TDM_WIN_CTRL_REG(winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; + targetAttrib.targetId = + (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvTdmWinEnable - Enable/disable a TDM to target address window +* +* DESCRIPTION: +* This function enable/disable a TDM to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling TDM accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - TDM to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) +{ + MV_TDM_DEC_WIN addrDecWin; + + if (MV_TRUE == enable) + { + if (winNum >= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) + { + mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); + } + else + { /* Overlap detected */ + mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { + MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); + } + return MV_OK; +} + + +/******************************************************************************* +* tdmWinOverlapDetect - Detect TDM address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviour is expected in case TDM address decode +* windows overlapps. +* This function detects TDM address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_TDM_DEC_WIN addrDecWin; + + for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) + { + /* Do not check window itself */ + if (winNumIndex == winNum) + { + continue; + } + /* Do not check disabled windows */ + if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) + { + /* Get window parameters */ + if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) + { + DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + } + return MV_FALSE; +} + +/******************************************************************************* +* mvTdmAddrDecShow - Print the TDM address decode map. +* +* DESCRIPTION: +* This function print the TDM address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvTdmAddrDecShow(MV_VOID) +{ + MV_TDM_DEC_WIN win; + int i; + + mvOsOutput( "\n" ); + mvOsOutput( "TDM:\n" ); + mvOsOutput( "----\n" ); + + for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if (mvTdmWinGet(i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); + mvOsOutput( "...." ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysTdm.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysTdm.h new file mode 100644 index 0000000..0d3140f --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysTdm.h @@ -0,0 +1,106 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSysTdmh +#define __INCmvSysTdmh + +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +typedef struct _mvTdmDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +} MV_TDM_DEC_WIN; + +MV_STATUS mvTdmWinInit(MV_VOID); +MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); +MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); +MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); +MV_VOID mvTdmAddrDecShow(MV_VOID); + + +#define TDM_MBUS_MAX_WIN 4 +#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) +#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) + +/* TDM_WIN_CTRL_REG bits */ +#define TDM_WIN_ENABLE_OFFS 0 +#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) + { + mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " + "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); + decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); + + if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; + decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; + /* set target ID */ + decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; + decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; + + /* for the safe side we disable the window before writing the new */ + /* values */ + mvTsuWinEnable(winNum, MV_FALSE); + MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); + + /* Enable address decode target window */ + if(pAddrDecWin->enable == MV_TRUE) + { + mvTsuWinEnable(winNum,MV_TRUE); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuWinGet +* +* DESCRIPTION: +* Get TSU peripheral target address window. +* +* INPUT: +* winNum - TSU to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - TSU target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if(winNum >= TSU_MAX_DECODE_WIN) + { + mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); + decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); + + if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; + targetAttrib.targetId = + (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuWinEnable +* +* DESCRIPTION: +* This function enable/disable a TSU to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling TSU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - TSU to target address decode window number. +* enable - Enable / disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) +{ + MV_TSU_DEC_WIN addrDecWin; + + /* Parameter checking */ + if(winNum >= TSU_MAX_DECODE_WIN) + { + mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if(enable == MV_TRUE) + { + /* First check for overlap with other enabled windows */ + /* Get current window. */ + if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) + { + mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping. */ + if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), + TSU_WIN_CTRL_EN_MASK); + } + else + { + /* Overlap detected */ + mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { + /* Disable address decode target window */ + MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), + TSU_WIN_CTRL_EN_MASK); + } + return MV_OK; +} + +/******************************************************************************* +* mvTsuWinTargetGet +* +* DESCRIPTION: +* Get Window number associated with target +* +* INPUT: +* target - Target ID to get the window number for. +* OUTPUT: +* +* RETURN: +* window number or 0xFFFFFFFF on error. +* +*******************************************************************************/ +MV_U32 mvTsuWinTargetGet(MV_TARGET target) +{ + MV_TSU_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if(target >= MAX_TARGETS) + { + mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) + { + if(mvTsuWinGet(winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvTsuWinGet: window returned error\n"); + return 0xffffffff; + } + + if (decWin.enable == MV_TRUE) + { + if(decWin.target == target) + { + return winNum; + } + } + } + return 0xFFFFFFFF; +} + + +/******************************************************************************* +* tsuWinOverlapDetect +* +* DESCRIPTION: +* Detect TSU address windows overlapping +* An unpredicted behaviur is expected in case TSU address decode +* windows overlapps. +* This function detects TSU address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 ctrlReg; + MV_U32 winNumIndex; + MV_TSU_DEC_WIN addrDecWin; + + for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) + { + /* Do not check window itself */ + if(winNumIndex == winNum) + { + continue; + } + + /* Do not check disabled windows */ + ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); + if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) + { + mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + return MV_FALSE; +} + + +/******************************************************************************* +* mvTsuAddrDecShow +* +* DESCRIPTION: +* Print the TSU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvTsuAddrDecShow(void) +{ + MV_TSU_DEC_WIN win; + int i; + + if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) + return; + + mvOsOutput( "\n" ); + mvOsOutput( "TSU:\n"); + mvOsOutput( "----\n" ); + + for(i = 0; i < TSU_MAX_DECODE_WIN; i++) + { + memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); + mvOsOutput( "win%d - ", i ); + + if(mvTsuWinGet(i, &win ) == MV_OK ) + { + if(win.enable == MV_TRUE) + { + mvOsOutput("%s base %08x, ", + mvCtrlTargetNameGet(win.target), + win.addrWin.baseLow); + mvOsOutput( "...." ); + mvSizePrint(win.addrWin.size ); + mvOsOutput( "\n" ); + } + else + { + mvOsOutput( "disable\n" ); + } + } + } + return; +} + + +/******************************************************************************* +* mvTsuInit +* +* DESCRIPTION: +* Initialize the TSU unit, and get unit out of reset. +* +* INPUT: +* coreClock - The core clock at which the TSU should operate. +* mode - The mode on configure the unit into (serial/parallel). +* memHandle - Memory handle used for memory allocations. +* OUTPUT: +* None. +* RETURN: +* MV_OK - on success, +* +*******************************************************************************/ +MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, + void *osHandle) +{ + MV_STATUS status; + + status = mvTsuWinInit(); + if(status == MV_OK) + status = mvTsuHalInit(coreClock,mode,osHandle); + + return status; +} diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysTs.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysTs.h new file mode 100644 index 0000000..4282589 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysTs.h @@ -0,0 +1,110 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSysTsh +#define __INCmvSysTsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ +#include "ts/mvTsu.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#define TSU_MAX_DECODE_WIN 4 + + +/*******************************************/ +/* TSU Windows Registers */ +/*******************************************/ +#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) +#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) + +/* TSU windows control register. */ +#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) +#define TSU_WIN_CTRL_TARGET_OFFS 4 +#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) +#define TSU_WIN_CTRL_ATTR_OFFS 8 +#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) +#define TSU_WIN_CTRL_SIZE_OFFS 16 +#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) + +/* TSU windows base register. */ +#define TSU_WIN_BASE_OFFS 16 +#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) + +MV_STATUS mvTsuWinInit(void); + +void mvTsuAddrDecShow(void); +MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, + void *osHandle); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvTsh */ diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysUsb.c b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysUsb.c new file mode 100644 index 0000000..195b5e1 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysUsb.c @@ -0,0 +1,497 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/sys/mvSysUsb.h" + +MV_TARGET usbAddrDecPrioTab[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) + CRYPT_ENG, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif + TBL_TERM +}; + + + +MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) +{ + MV_STATUS status; + + status = mvUsbWinInit(dev); + if(status != MV_OK) + return status; + + return mvUsbHalInit(dev, isHost); +} + + +/******************************************************************************* +* usbWinOverlapDetect - Detect USB address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case USB address decode +* windows overlapps. +* This function detects USB address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_DEC_WIN addrDecWin; + + for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) + { + mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pDecWin->target), + pDecWin->addrWin.baseLow, + pDecWin->addrWin.size); + return MV_ERROR; + } + + if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) + { + mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* set Size, Attributes and TargetID */ + sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | + ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | + ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); + +#if defined(MV645xx) || defined(MV646xx) + /* If window is DRAM with HW cache coherency, make sure bit2 is set */ + sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; + + if((MV_TARGET_IS_DRAM(pDecWin->target)) && + (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) + { + sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; + } + else + { + sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; + } +#endif /* MV645xx || MV646xx */ + + if (pDecWin->enable == MV_TRUE) + { + sizeReg |= MV_USB_WIN_ENABLE_MASK; + } + else + { + sizeReg &= ~MV_USB_WIN_ENABLE_MASK; + } + + /* Update Base value */ + baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); + + MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); + MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvUsbWinGet - Get USB peripheral target address window. +* +* DESCRIPTION: +* Get USB peripheral target address window. +* +* INPUT: +* winNum - USB target address decode window number. +* +* OUTPUT: +* pDecWin - USB target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) +{ + MV_DEC_WIN_PARAMS winParam; + MV_U32 sizeReg, baseReg; + + /* Parameter checking */ + if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", + __FUNCTION__, dev, winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); + sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); + + /* Check if window is enabled */ + if(sizeReg & MV_USB_WIN_ENABLE_MASK) + { + pDecWin->enable = MV_TRUE; + + /* Extract window parameters from registers */ + winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; + winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; + winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; + winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); + + /* Translate the decode window parameters to address decode struct */ + if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) + { + mvOsPrintf("Failed to translate register parameters to USB address" \ + " decode window structure\n"); + return MV_ERROR; + } + } + else + { + pDecWin->enable = MV_FALSE; + } + return MV_OK; +} + +/******************************************************************************* +* mvUsbWinInit - +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvUsbWinInit(int dev) +{ + MV_STATUS status; + MV_DEC_WIN usbWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + int winNum; + MV_U32 winPrioIndex = 0; + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); + } + + /* Go through all windows in user table until table terminator */ + winNum = 0; + while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && + (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) + { + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], + &cpuAddrDecWin); + + if(MV_NO_SUCH == status) + { + winPrioIndex++; + continue; + } + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; + usbWin.enable = MV_TRUE; + usbWin.target = usbAddrDecPrioTab[winPrioIndex]; + +#if defined(MV645xx) || defined(MV646xx) + /* Get the default attributes for that target window */ + mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); +#endif /* MV645xx || MV646xx */ + + if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) + { + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} + +/******************************************************************************* +* mvUsbAddrDecShow - Print the USB address decode map. +* +* DESCRIPTION: +* This function print the USB address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvUsbAddrDecShow(MV_VOID) +{ + MV_DEC_WIN addrDecWin; + int i, winNum; + + mvOsOutput( "\n" ); + mvOsOutput( "USB:\n" ); + mvOsOutput( "----\n" ); + + for(i=0; i= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + if (pAddrDecWin == NULL) + { + DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + /* Check if the requested window overlaps with current windows */ + if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) + { + DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); + return MV_ERROR; + } + + xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); + xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); + + /* Get Base Address and size registers values */ + if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) + { + DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); + return MV_BAD_PARAM; + } + + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; + xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; + /* set target ID */ + xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; + xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; + + + /* Write to address decode Base Address Register */ + MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); + + /* Write to Size Register */ + MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + if (pAddrDecWin->enable) + { + MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + else + { + MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + } + return MV_OK; +} + +/******************************************************************************* +* mvXorTargetWinGet - Get xor peripheral target address window. +* +* DESCRIPTION: +* Get xor peripheral target address window. +* +* INPUT: +* winNum - One of the possible XOR memory decode windows. +* +* OUTPUT: +* base - Window base address. +* size - Window size. +* enable - window enable/disable. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS xorDecRegs; + MV_TARGET_ATTRIB targetAttrib; + MV_U32 chan=0,chanWinEn; + + /* Parameter checking */ + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); + return MV_ERROR; + } + + if (NULL == pAddrDecWin) + { + DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + + chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ + { + /* Check if enable bit is equal for all channels */ + if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & + XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) + { + mvOsPrintf("%s: ERR. Window enable field must be equal in " + "all channels(chan=%d)\n",__FUNCTION__, chan); + return MV_ERROR; + } + } + + + + xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); + xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; + targetAttrib.targetId = + (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; + + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + if(chanWinEn) + { + pAddrDecWin->enable = MV_TRUE; + } + else pAddrDecWin->enable = MV_FALSE; + + return MV_OK; +} + +/******************************************************************************* +* mvXorTargetWinEnable - Enable/disable a Xor address decode window +* +* DESCRIPTION: +* This function enable/disable a XOR address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling XOR accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) +{ + MV_XOR_DEC_WIN addrDecWin; + MV_U32 chan; + + /* Parameter checking */ + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { + /* Get current window */ + if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) + { + DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); + return MV_ERROR; + } + + /* Check for overlapping */ + if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) + { + /* Overlap detected */ + DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); + return MV_ERROR; + } + + /* No Overlap. Enable address decode target window */ + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + + } + else + { + /* Disable address decode target window */ + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + + } + + return MV_OK; +} + +/******************************************************************************* +* mvXorSetProtWinSet - Configure access attributes of a XOR engine +* to one of the XOR memory windows. +* +* DESCRIPTION: +* Each engine can be configured with access attributes for each of the +* memory spaces. This function sets access attributes +* to a given window for the given engine +* +* INPUTS: +* chan - One of the possible engines. +* winNum - One of the possible XOR memory spaces. +* access - Protection access rights. +* write - Write rights. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, + MV_BOOL write) +{ + MV_U32 temp; + + /* Parameter checking */ + if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) + { + DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); + return MV_BAD_PARAM; + } + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + + temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & + (~XEXWCR_WIN_ACC_MASK(winNum)); + + /* if access is disable */ + if (!access) + { + /* disable access */ + temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); + } + /* if access is enable */ + else + { + /* if write is enable */ + if (write) + { + /* enable write */ + temp |= XEXWCR_WIN_ACC_RW(winNum); + } + /* if write is disable */ + else + { + /* disable write */ + temp |= XEXWCR_WIN_ACC_RO(winNum); + } + } + MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); + return MV_OK; +} + +/******************************************************************************* +* mvXorPciRemap - Set XOR remap register for PCI address windows. +* +* DESCRIPTION: +* only Windows 0-3 can be remapped. +* +* INPUT: +* winNum - window number +* pAddrDecWin - pointer to address space window structure +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) +{ + /* Parameter checking */ + if (winNum >= XOR_MAX_REMAP_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + + MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); + + return MV_OK; +} + +/******************************************************************************* +* xorWinOverlapDetect - Detect XOR address windows overlaping +* +* DESCRIPTION: +* An unpredicted behaviour is expected in case XOR address decode +* windows overlaps. +* This function detects XOR address decode windows overlaping of a +* specified window. The function does not check the window itself for +* overlaping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex,chan; + MV_XOR_DEC_WIN addrDecWin; + + if (pAddrWin == NULL) + { + DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); + + for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) + { + /* Do not check window itself */ + if (winNumIndex == winNum) + { + continue; + } + + /* Do not check disabled windows */ + if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) + { + DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + } + + return MV_FALSE; +} + +static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) +{ + MV_XOR_DEC_WIN win; + int i; + + mvOsOutput( "\n" ); + mvOsOutput( "XOR %d:\n", unit ); + mvOsOutput( "----\n" ); + + for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + +/******************************************************************************* +* mvXorAddrDecShow - Print the XOR address decode map. +* +* DESCRIPTION: +* This function print the XOR address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvXorAddrDecShow(MV_VOID) +{ + int i; + + for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) + mvXorAddrDecShowUnit(i); + +} diff --git a/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysXor.h b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysXor.h new file mode 100644 index 0000000..73b2d9e --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/ctrlEnv/sys/mvSysXor.h @@ -0,0 +1,140 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCMVSysXorh +#define __INCMVSysXorh + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ctrlEnv/sys/mvCpuIf.h" + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ +#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ + +/* XOR Engine Address Decoding Register Map */ +#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) +#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) +#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) +#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) + +/* XOR Engine [0..1] Window Control Registers (XExWCR) */ +#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) +#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) +#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) +#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) + +#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) +#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) + +/* XOR Engine Base Address Registers (XEBARx) */ +#define XEBARX_TARGET_OFFS (0) +#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) +#define XEBARX_ATTR_OFFS (8) +#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) +#define XEBARX_BASE_OFFS (16) +#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) + +/* XOR Engine Size Mask Registers (XESMRx) */ +#define XESMRX_SIZE_MASK_OFFS (16) +#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) + +/* XOR Engine High Address Remap Register (XEHARRx1) */ +#define XEHARRX_REMAP_OFFS (0) +#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) + +typedef struct _mvXorDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_XOR_DEC_WIN; + +MV_STATUS mvXorInit (MV_VOID); +MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, + MV_XOR_DEC_WIN *pAddrDecWin); +MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, + MV_XOR_DEC_WIN *pAddrDecWin); +MV_STATUS mvXorTargetWinEnable(MV_U32 unit, + MV_U32 winNum, MV_BOOL enable); +MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, + MV_BOOL write); +MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); + +MV_VOID mvXorAddrDecShow(MV_VOID); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/board/mv_feroceon/mv_kw/kw_family/device/mvDevice.c b/board/mv_feroceon/mv_kw/kw_family/device/mvDevice.c new file mode 100644 index 0000000..80325fc --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/device/mvDevice.c @@ -0,0 +1,75 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "device/mvDevice.h" + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + + + diff --git a/board/mv_feroceon/mv_kw/kw_family/device/mvDevice.h b/board/mv_feroceon/mv_kw/kw_family/device/mvDevice.h new file mode 100644 index 0000000..9350779 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/device/mvDevice.h @@ -0,0 +1,74 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDeviceH +#define __INCmvDeviceH + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "device/mvDeviceRegs.h" + + +#endif /* #ifndef __INCmvDeviceH */ diff --git a/board/mv_feroceon/mv_kw/kw_family/device/mvDeviceRegs.h b/board/mv_feroceon/mv_kw/kw_family/device/mvDeviceRegs.h new file mode 100644 index 0000000..70a12df --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/device/mvDeviceRegs.h @@ -0,0 +1,103 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDeviceRegsH +#define __INCmvDeviceRegsH + +#ifndef MV_ASMLANGUAGE +#include "ctrlEnv/mvCtrlEnvLib.h" +/* This enumerator describes the Marvell controller possible devices that */ +/* can be connected to its device interface. */ +typedef enum _mvDevice +{ +#if defined(MV_INCLUDE_DEVICE_CS0) + DEV_CS0 = 0, /* Device connected to dev CS[0] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEV_CS1 = 1, /* Device connected to dev CS[1] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEV_CS2 = 2, /* Device connected to dev CS[2] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEV_CS3 = 3, /* Device connected to dev CS[2] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS4) + DEV_CS4 = 4, /* Device connected to BOOT dev */ +#endif + MV_DEV_MAX_CS = MV_DEVICE_MAX_CS +}MV_DEVICE; + + +#endif /* MV_ASMLANGUAGE */ + + +#define NAND_READ_PARAMS_REG 0x10418 +#define NAND_WRITE_PARAMS_REG 0x1041c +#define NAND_CTRL_REG 0x10470 + +#define NAND_ACTCEBOOT_BIT BIT1 + + +#endif /* #ifndef __INCmvDeviceRegsH */ diff --git a/board/mv_feroceon/mv_kw/kw_family/mvCompVer.txt b/board/mv_feroceon/mv_kw/kw_family/mvCompVer.txt new file mode 100644 index 0000000..4053116 --- /dev/null +++ b/board/mv_feroceon/mv_kw/kw_family/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.5 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_kw/mvSysHwConfig.h b/board/mv_feroceon/mv_kw/mvSysHwConfig.h new file mode 100644 index 0000000..2a36de2 --- /dev/null +++ b/board/mv_feroceon/mv_kw/mvSysHwConfig.h @@ -0,0 +1,359 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmvSysHwConfigh +#define __INCmvSysHwConfigh + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ +#undef MV_MEM_OVER_PEX_WA + +#define MV_INCLUDE_PEX +#define MV_INCLUDE_GIG_ETH +#define MV_INCLUDE_CESA +#define MV_INCLUDE_USB +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART +#define MV_INCLUDE_SPI +#define MV_INCLUDE_TDM +#define MV_INCLUDE_XOR +#define MV_INCLUDE_TS +#define MV_INCLUDE_AUDIO +#define MV_INCLUDE_RTC +#define MV_INCLUDE_SATA +#define MV_INCLUDE_INTEG_SATA +#define MV_INCLUDE_CLK_PWR_CNTRL + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board SPI Flash support */ +#define MV_INC_BOARD_SPI_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + +/************************************************/ +/* U-Boot Specific */ +/************************************************/ +#define MV_INCLUDE_MONT_EXT + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#endif + + +/************************************************/ +/* RD boards specifics */ +/************************************************/ + +#undef MV_INC_BOARD_DDIM + +#ifndef MV_BOOTROM +#define MV_STATIC_DRAM_ON_BOARD +#endif + +#if defined(RD_88F6281) +#define MV_INC_BOARD_QD_SWITCH +#endif + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M + +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _16M + +/* PEX1 for 6282 only */ +#define PEX1_MEM_BASE 0x98000000 +#define PEX1_MEM_SIZE _128M + +#define PEX1_IO_BASE 0xf2000000 +#define PEX1_IO_SIZE _16M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + +/* Device: CS0 - NAND, CS1 - SPI, CS2 - Boot ROM, CS3 - Boot device */ + +#define DEVICE_CS0_BASE 0xf9000000 +#define DEVICE_CS0_SIZE _8M + +#define DEVICE_SPI_BASE 0xf8000000 +#define DEVICE_CS1_BASE DEVICE_SPI_BASE +#define DEVICE_CS1_SIZE _16M + +#define DEVICE_CS2_BASE 0xf4000000 +#define DEVICE_CS2_SIZE _1M + +#define DEVICE_CS3_BASE BOOTDEV_CS_BASE +#define DEVICE_CS3_SIZE BOOTDEV_CS_SIZE + +#if !defined(MV_BOOTROM) && defined(MV_NAND_BOOT) +#define CFG_NAND_BASE BOOTDEV_CS_BASE +#else +#define CFG_NAND_BASE DEVICE_CS0_BASE +#endif + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + + +#define CRYPT_ENG_BASE 0xFB000000 +#define CRYPT_ENG_SIZE _64K + + +#if defined (MV_INCLUDE_PEX) +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PEX1_MEM_BASE +#define PCI_IF1_MEM0_SIZE PEX1_MEM_SIZE +#define PCI_IF1_IO_BASE PEX1_IO_BASE +#define PCI_IF1_IO_SIZE PEX1_IO_SIZE +#endif +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + +/* Board clock detection */ +//#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ +#define L2CLK_AUTO_DETECT /* Use L2 Clk auto detection */ + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +/* HW cache coherency configuration */ +#define DMA_RAM_COHER NO_COHERENCY +#define ETHER_DRAM_COHER MV_UNCACHED +#define INTEG_SRAM_COHER MV_UNCACHED /* Where integrated SRAM available */ + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" +#endif /* ETHER_DRAM_COHER */ + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE} ,0xFFFFFFFF,DIS}, \ + {{PEX0_MEM_BASE , 0, PEX0_MEM_SIZE } ,0x0 ,EN}, \ + {{PEX0_IO_BASE , 0, PEX0_IO_SIZE } ,0x2 ,EN}, \ + {{PEX1_MEM_BASE , 0, PEX1_MEM_SIZE } ,0x1 ,EN}, \ + {{PEX1_IO_BASE , 0, PEX1_IO_SIZE } ,0x3 ,EN}, \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE},0x8 ,EN}, \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE},0x4 ,EN}, \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE},0x5 ,EN}, \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE},0x9 ,DIS}, \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE},0xA ,DIS}, \ + {{CRYPT_ENG_BASE, 0, CRYPT_ENG_SIZE} ,0x7 ,EN}, \ + /* Table terminator */\ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM,TBL_TERM} \ +}; + +#define MV_CACHEABLE(address) ((address) | 0x80000000) + +/* includes */ +#define _1K 0x00000400 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + + +#if defined(MV_BOOTSIZE_256K) + +#define BOOTDEV_CS_SIZE _256K + +#elif defined(MV_BOOTSIZE_512K) + +#define BOOTDEV_CS_SIZE _512K + +#elif defined(MV_BOOTSIZE_4M) + +#define BOOTDEV_CS_SIZE _4M + +#elif defined(MV_BOOTSIZE_8M) + +#define BOOTDEV_CS_SIZE _8M + +#elif defined(MV_BOOTSIZE_16M) + +#define BOOTDEV_CS_SIZE _16M + +#elif defined(MV_BOOTSIZE_32M) + +#define BOOTDEV_CS_SIZE _32M + +#elif defined(MV_BOOTSIZE_64M) + +#define BOOTDEV_CS_SIZE _64M + +#elif defined(MV_NAND_BOOT) + +#define BOOTDEV_CS_SIZE _512K + +#else + +#error "MV_BOOTSIZE undefined" + +#endif + +#define BOOTDEV_CS_BASE ((0xFFFFFFFF - BOOTDEV_CS_SIZE) + 1) + +/* We use the following registers to store DRAM interface pre configuration */ +/* auto-detection results */ +/* IMPORTANT: We are using mask register for that purpose. Before writing */ +/* to units mask register, make sure main maks register is set to disable */ +/* all interrupts. */ +#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ +#define DRAM_BUF_REG1 0x30820 /* sdram config */ +#define DRAM_BUF_REG2 0x30830 /* sdram mode */ +#define DRAM_BUF_REG3 0x60bb0 /* dunit control low */ +#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ +#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ +#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ +#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ +#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ +#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ +#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ +#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ +#define DRAM_BUF_REG12 0x60bb4 /* sdram Ddr2 Time High Reg */ +#define DRAM_BUF_REG13 0x60ab0 /* dunit Ctrl High */ +#define DRAM_BUF_REG14 0x60ab4 /* sdram second DIMM exist */ + +/* Following the pre-configuration registers default values restored after */ +/* auto-detection is done */ +#define DRAM_BUF_REG_DV 0 + +#define ETH_DEF_TXQ 0 +#define ETH_DEF_RXQ 0 +#define MV_ETH_TX_Q_NUM 1 +#define MV_ETH_RX_Q_NUM 1 +#define ETH_NUM_OF_RX_DESCR 64 +#define ETH_NUM_OF_TX_DESCR ETH_NUM_OF_RX_DESCR*2 + +#define MV_CESA_MAX_BUF_SIZE 1600 + +#endif /* __INCmvSysHwConfigh */ diff --git a/board/mv_feroceon/mv_kw/mv_cmd.c b/board/mv_feroceon/mv_kw/mv_cmd.c new file mode 100644 index 0000000..34fd47e --- /dev/null +++ b/board/mv_feroceon/mv_kw/mv_cmd.c @@ -0,0 +1,1840 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include +#include + +#include "mvTypes.h" +#include "mvCtrlEnvLib.h" + +#if defined(MV_INC_BOARD_NOR_FLASH) +#include "norflash/mvFlash.h" +#endif + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) +#include "eth-phy/mvEthPhy.h" +#if defined(CONFIG_BUFFALO_PLATFORM) +#include "buffalo/BuffaloWol.h" +#endif // CONFIG_BUFFALO_PLATFORM +#include "../USP/ethSwitch/mvSwitch.h" +#endif + +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif + +#if defined(MV_INCLUDE_IDMA) +#include "idma/mvIdma.h" +#include "sys/mvSysIdma.h" +#endif + +#if defined(CFG_NAND_BOOT) || defined(CFG_CMD_NAND) +#include + +/* references to names in cmd_nand.c */ +#define NANDRW_READ 0x01 +#define NANDRW_WRITE 0x00 +#define NANDRW_JFFS2 0x02 +//extern struct nand_chip nand_dev_desc[]; +extern nand_info_t nand_info[]; /* info for NAND chips */ +/* int nand_rw (struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf); + int nand_erase(struct nand_chip* nand, size_t ofs, + size_t len, int clean); +*/ +extern int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); +extern int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts); + + +#endif /* CFG_NAND_BOOT */ + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) +#if !defined(CFG_NAND_BOOT) +static unsigned int flash_in_which_sec(flash_info_t *fl,unsigned int offset) +{ + unsigned int sec_num; + if(NULL == fl) + return 0xFFFFFFFF; + + for( sec_num = 0; sec_num < fl->sector_count ; sec_num++){ + /* If last sector*/ + if (sec_num == fl->sector_count -1) + { + if((offset >= fl->start[sec_num]) && + (offset <= (fl->size + fl->start[0] - 1)) ) + { + return sec_num; + } + + } + else + { + if((offset >= fl->start[sec_num]) && + (offset < fl->start[sec_num + 1]) ) + { + return sec_num; + } + + } + } + /* return illegal sector Number */ + return 0xFFFFFFFF; + +} + +#endif /* !defined(CFG_NAND_BOOT) */ + + +/******************************************************************************* +burn a u-boot.bin on the Boot Flash +********************************************************************************/ +extern flash_info_t flash_info[]; /* info for FLASH chips */ +#include +#include "bootstrap_def.h" +#if (CONFIG_COMMANDS & CFG_CMD_NET) +/* + * 8 bit checksum + */ +static u8 checksum8(u32 start, u32 len,u8 csum) +{ + register u8 sum = csum; + volatile u8* startp = (volatile u8*)start; + + if (len == 0) + return csum; + + do{ + sum += *startp; + startp++; + }while(--len); + + return (sum); +} + +/* + * Check the extended header and execute the image + */ +static MV_U32 verify_extheader(ExtBHR_t *extBHR) +{ + MV_U8 chksum; + + + /* Caclulate abd check the checksum to valid */ + chksum = checksum8((MV_U32)extBHR , EXT_HEADER_SIZE -1, 0); + if (chksum != (*(MV_U8*)((MV_U32)extBHR + EXT_HEADER_SIZE - 1))) + { + printf("Error! invalid extende header checksum\n"); + return MV_FAIL; + } + + return MV_OK; +} +/* + * Check the CSUM8 on the main header + */ +static MV_U32 verify_main_header(BHR_t *pBHR, MV_U8 headerID) +{ + MV_U8 chksum; + + /* Verify Checksum */ + chksum = checksum8((MV_U32)pBHR, sizeof(BHR_t) -1, 0); + + if (chksum != pBHR->checkSum) + { + printf("Error! invalid image header checksum\n"); + return MV_FAIL; + } + + /* Verify Header */ + if (pBHR->blockID != headerID) + { + printf("Error! invalid image header ID\n"); + return MV_FAIL; + } + + /* Verify Alignment */ + if (pBHR->blockSize & 0x3) + { + printf("Error! invalid image header alignment\n"); + return MV_FAIL; + } + + if ((cpu_to_le32(pBHR->destinationAddr) & 0x3) && (cpu_to_le32(pBHR->destinationAddr) != 0xffffffff)) + { + printf("Error! invalid image header destination\n"); + return MV_FAIL; + } + + if ((cpu_to_le32(pBHR->sourceAddr) & 0x3) && (pBHR->blockID != IBR_HDR_SATA_ID)) + { + printf("Error! invalid image header source\n"); + return MV_FAIL; + } + + return MV_OK; +} + +int nandenvECC = 0; +#if defined(CFG_NAND_BOOT) +/* Boot from NAND flash */ +/* Write u-boot image into the nand flash */ +int nand_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize, eccEnv = 0; + MV_U32 ret = 0; + extern char console_buffer[]; + nand_info_t *nand = &nand_info[0]; + nand_erase_options_t er_opts; + nand_write_options_t wr_opts; + + load_addr = CFG_LOAD_ADDR; + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "u-boot.bin", sizeof(BootFile)); + printf("using default file \"u-boot.bin\" \n"); + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + +#ifdef MV_BOOTROM + BHR_t* tmpBHR = (BHR_t*)load_addr; + ExtBHR_t* extBHR = (ExtBHR_t*)(load_addr + BHR_HDR_SIZE); + MV_U32 errCode=0; + + /* Verify Main header checksum */ + errCode = verify_main_header(tmpBHR, IBR_HDR_NAND_ID); + if (errCode) + return 0; + + /* Verify that the extended header is valid */ + errCode = verify_extheader(extBHR); + if (errCode) + return 0; +#endif + /* The environment has Reed-Solomon ECC protection in the NAND */ + nandenvECC = 1; + + printf("\n**Warning**\n"); + printf("If U-Boot Endiannes is going to change (LE->BE or BE->LE), Then Env parameters should be overriden..\n"); + printf("Override Env parameters? (y/n)"); + readline(" "); + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + printf("Erase Env parameters sector %d... ",CFG_ENV_OFFSET); + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_ENV_OFFSET; + er_opts.length = CFG_ENV_SECT_SIZE; + er_opts.quiet = 1; + + nand_erase_opts(nand, &er_opts); + //nand_erase(nand_dev_desc + 0, CFG_ENV_OFFSET, CFG_ENV_SECT_SIZE, 0); + printf("\n"); + } + + printf("Erase %d - %d ... ",CFG_MONITOR_BASE, CFG_MONITOR_LEN); + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_MONITOR_BASE; + er_opts.length = CFG_MONITOR_LEN; + er_opts.quiet = 1; + nand_erase_opts(nand, &er_opts); + //nand_erase(nand_dev_desc + 0, CFG_MONITOR_BASE, CFG_MONITOR_LEN, 0); + + printf("\nCopy to Nand Flash... "); + memset(&wr_opts, 0, sizeof(wr_opts)); + wr_opts.buffer = (u_char*) load_addr; + wr_opts.length = CFG_MONITOR_LEN; + wr_opts.offset = CFG_MONITOR_BASE; + /* opts.forcejffs2 = 1; */ + wr_opts.pad = 1; + wr_opts.blockalign = 1; + wr_opts.quiet = 1; + ret = nand_write_opts(nand, &wr_opts); + /* ret = nand_rw(nand_dev_desc + 0, + NANDRW_WRITE | NANDRW_JFFS2, CFG_MONITOR_BASE, CFG_MONITOR_LEN, + &total, (u_char*)0x100000 + CFG_MONITOR_IMAGE_OFFSET); + */ + if (ret) + printf("Error - NAND burn faild!\n"); + else + printf("\ndone\n"); + + /* The environment has Reed-Solomon ECC protection in the NAND */ + nandenvECC = 0; + + return 1; +} + +U_BOOT_CMD( + bubt, 2, 1, nand_burn_uboot_cmd, + "bubt - Burn an image on the Boot Nand Flash.\n", + " file-name \n" + "\tBurn a binary image on the Boot Nand Flash, default file-name is u-boot.bin .\n" +); + +/* Write nboot loader image into the nand flash */ +int nand_burn_nboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 ret = 0; + extern char console_buffer[]; + nand_info_t *nand = &nand_info[0]; + nand_erase_options_t er_opts; + nand_write_options_t wr_opts; + + + load_addr = CFG_LOAD_ADDR; + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "nboot.bin", sizeof(BootFile)); + printf("using default file \"nboot.bin\" \n"); + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + + printf("Erase %d - %d ... ",CFG_NBOOT_BASE, CFG_NBOOT_LEN); + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_NBOOT_BASE; + er_opts.length = CFG_NBOOT_LEN; + er_opts.quiet = 1; + + nand_erase_opts(nand, &er_opts); + //nand_erase(nand_dev_desc + 0, CFG_NBOOT_BASE, CFG_NBOOT_LEN , 0); + + printf("\nCopy to Nand Flash... "); + memset(&wr_opts, 0, sizeof(wr_opts)); + wr_opts.buffer = (u_char*) load_addr; + wr_opts.length = CFG_NBOOT_LEN; + wr_opts.offset = CFG_NBOOT_BASE; + /* opts.forcejffs2 = 1; */ + wr_opts.pad = 1; + wr_opts.blockalign = 1; + wr_opts.quiet = 1; + ret = nand_write_opts(nand, &wr_opts); + /* ret = nand_rw(nand_dev_desc + 0, + NANDRW_WRITE | NANDRW_JFFS2, CFG_NBOOT_BASE, CFG_NBOOT_LEN, + &total, (u_char*)0x100000); + */ + if (ret) + printf("Error - NAND burn faild!\n"); + else + printf("\ndone\n"); + + return 1; +} + +U_BOOT_CMD( + nbubt, 2, 1, nand_burn_nboot_cmd, + "nbubt - Burn a boot loader image on the Boot Nand Flash.\n", + " file-name \n" + "\tBurn a binary boot loader image on the Boot Nand Flash, default file-name is nboot.bin .\n" +); + +#else +/* Boot from Nor flash */ +int nor_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 s_first,s_end,env_sec; + extern char console_buffer[]; + + + s_first = flash_in_which_sec(&flash_info[BOOT_FLASH_INDEX], CFG_MONITOR_BASE); + s_end = flash_in_which_sec(&flash_info[BOOT_FLASH_INDEX], CFG_MONITOR_BASE + CFG_MONITOR_LEN -1); + + env_sec = flash_in_which_sec(&flash_info[BOOT_FLASH_INDEX], CFG_ENV_ADDR); + + + load_addr = CFG_LOAD_ADDR; + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "u-boot.bin", sizeof(BootFile)); + printf("using default file \"u-boot.bin\" \n"); + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + +#ifdef MV_BOOTROM + BHR_t* tmpBHR = (BHR_t*)load_addr; + ExtBHR_t* extBHR = (ExtBHR_t*)(load_addr + BHR_HDR_SIZE); + MV_U32 errCode=0; + + /* Verify Main header checksum */ + errCode = verify_main_header(tmpBHR, IBR_HDR_SPI_ID); + if (errCode) + return 0; + + /* Verify that the extended header is valid */ + errCode = verify_extheader(extBHR); + if (errCode) + return 0; +#endif + + printf("Un-Protect Flash Monitor space\n"); + flash_protect (FLAG_PROTECT_CLEAR, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[BOOT_FLASH_INDEX]); + + printf("\n**Warning**\n"); + printf("If U-Boot Endiannes is going to change (LE->BE or BE->LE), Then Env parameters should be overriden..\n"); + printf("Override Env parameters? (y/n)"); + readline(" "); + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + flash_protect (FLAG_PROTECT_CLEAR, + flash_info[BOOT_FLASH_INDEX].start[env_sec], + flash_info[BOOT_FLASH_INDEX].start[env_sec] + CFG_ENV_SECT_SIZE - 1, + &flash_info[BOOT_FLASH_INDEX]); + + printf("Erase Env parameters sector %d... ",env_sec); + flash_erase(&flash_info[BOOT_FLASH_INDEX], env_sec, env_sec); + + if ((mvCtrlModelGet() != MV_6082_DEV_ID) && + (mvCtrlModelGet() != MV_6183_DEV_ID) && + (mvCtrlModelGet() != MV_6183L_DEV_ID) && + (mvCtrlModelGet() != MV_6281_DEV_ID) && + (mvCtrlModelGet() != MV_6282_DEV_ID) && + (mvCtrlModelGet() != MV_6280_DEV_ID) && + (mvCtrlModelGet() != MV_6192_DEV_ID) && + (mvCtrlModelGet() != MV_6190_DEV_ID) && + (mvCtrlModelGet() != MV_6180_DEV_ID)) + flash_protect (FLAG_PROTECT_SET, + flash_info[BOOT_FLASH_INDEX].start[env_sec], + flash_info[BOOT_FLASH_INDEX].start[env_sec] + CFG_ENV_SECT_SIZE - 1, + &flash_info[BOOT_FLASH_INDEX]); + + } + + printf("Erase %d - %d sectors... ",s_first,s_end); + flash_erase(&flash_info[BOOT_FLASH_INDEX], s_first, s_end); + + printf("Copy to Flash... "); + + flash_write ( (uchar *)(CFG_LOAD_ADDR + CFG_MONITOR_IMAGE_OFFSET), + (ulong)CFG_MONITOR_BASE, + (ulong)(filesize - CFG_MONITOR_IMAGE_OFFSET)); + + printf("done\nProtect Flash Monitor space\n"); + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[BOOT_FLASH_INDEX]); + + return 1; +} + +U_BOOT_CMD( + bubt, 2, 1, nor_burn_uboot_cmd, + "bubt - Burn an image on the Boot Flash.\n", + " file-name \n" + "\tBurn a binary image on the Boot Flash, default file-name is u-boot.bin .\n" +); +#endif /* defined(CFG_NAND_BOOT) */ +#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */ + + + +/******************************************************************************* +Reset environment variables. +********************************************************************************/ +extern flash_info_t flash_info[]; /* info for FLASH chips */ +int resetenv_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CFG_NAND_BOOT) + printf("Erase Env parameters offset 0x%x... ",CFG_ENV_OFFSET); + nand_info_t *nand = &nand_info[0]; + nand_erase_options_t er_opts; + int i = 0, goodBlockCounter = 0; + + while(i * nand_info[0].erasesize < nand_info[0].size) + { + if(nand_info[0].block_isbad(&nand_info[0], i * nand_info[0].erasesize) == 0) + goodBlockCounter++; + if((goodBlockCounter * nand_info[0].erasesize) >= CFG_ENV_OFFSET + CFG_ENV_SECT_SIZE) + break; + i++; + } + + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_ENV_OFFSET + (1 + i - goodBlockCounter) * nand_info[0].erasesize; + er_opts.length = CFG_ENV_SECT_SIZE; + er_opts.quiet = 1; + + nand_erase_opts(nand, &er_opts); + //nand_erase(nand_dev_desc + 0, CFG_ENV_OFFSET, CFG_ENV_SECT_SIZE, 0); + printf("done"); +#else + MV_U32 env_sec = flash_in_which_sec(&flash_info[0], CFG_ENV_ADDR); + + if (env_sec == -1) + { + printf("Could not find ENV Sector\n"); + return 0; + } + + printf("Un-Protect ENV Sector\n"); + + flash_protect(FLAG_PROTECT_CLEAR, + CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + + printf("Erase sector %d ... ",env_sec); + flash_erase(&flash_info[0], env_sec, env_sec); + printf("done\nProtect ENV Sector\n"); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + +#endif /* defined(CFG_NAND_BOOT) */ + printf("\nWarning: Default Environment Variables will take effect Only after RESET \n\n"); + +#if defined(CONFIG_BUFFALO_PLATFORM) + extern void bfKeepEthAddr(void); + bfKeepEthAddr(); +#endif + + return 1; +} + +U_BOOT_CMD( + resetenv, 1, 1, resetenv_cmd, + "resetenv - Return all environment variable to default.\n", + " \n" + "\t Erase the environemnt variable sector.\n" +); + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FLASH) */ +#if CONFIG_COMMANDS & CFG_CMD_BSP + +/****************************************************************************** +* Category - General +* Functionality- The commands allows the user to view the contents of the MV +* internal registers and modify them. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int ir_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_U32 regNum = 0x0, regVal, regValTmp, res; + MV_8 regValBin[40]; + MV_8 cmd[40]; + int i,j = 0, flagm = 0; + extern MV_8 console_buffer[]; + + if( argc == 2 ) { + regNum = simple_strtoul( argv[1], NULL, 16 ); + } + else { + printf( "Usage:\n%s\n", cmdtp->usage ); + return 0; + } + + regVal = MV_REG_READ( regNum ); + regValTmp = regVal; + printf( "Internal register 0x%x value : 0x%x\n ",regNum, regVal ); + printf( "\n 31 24 16 8 0" ); + printf( "\n | | | | |\nOLD: " ); + + for( i = 31 ; i >= 0 ; i-- ) { + if( regValTmp > 0 ) { + res = regValTmp % 2; + regValTmp = (regValTmp - res) / 2; + if( res == 0 ) + regValBin[i] = '0'; + else + regValBin[i] = '1'; + } + else + regValBin[i] = '0'; + } + + for( i = 0 ; i < 32 ; i++ ) { + printf( "%c", regValBin[i] ); + if( (((i+1) % 4) == 0) && (i > 1) && (i < 31) ) + printf( "-" ); + } + + readline( "\nNEW: " ); + strcpy(cmd, console_buffer); + if( (cmd[0] == '0') && (cmd[1] == 'x') ) { + regVal = simple_strtoul( cmd, NULL, 16 ); + flagm=1; + } + else { + for( i = 0 ; i < 40 ; i++ ) { + if(cmd[i] == '\0') + break; + if( i == 4 || i == 9 || i == 14 || i == 19 || i == 24 || i == 29 || i == 34 ) + continue; + if( cmd[i] == '1' ) { + regVal = regVal | (0x80000000 >> j); + flagm = 1; + } + else if( cmd[i] == '0' ) { + regVal = regVal & (~(0x80000000 >> j)); + flagm = 1; + } + j++; + } + } + + if( flagm == 1 ) { + MV_REG_WRITE( regNum, regVal ); + printf( "\nNew value = 0x%x\n\n", MV_REG_READ(regNum) ); + } + return 1; +} + +U_BOOT_CMD( + ir, 2, 1, ir_cmd, + "ir - reading and changing MV internal register values.\n", + " address\n" + "\tDisplays the contents of the internal register in 2 forms, hex and binary.\n" + "\tIt's possible to change the value by writing a hex value beginning with \n" + "\t0x or by writing 0 or 1 in the required place. \n" + "\tPressing enter without any value keeps the value unchanged.\n" +); + +/****************************************************************************** +* Category - General +* Functionality- Display the auto detect values of the TCLK and SYSCLK. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int clk_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf( "TCLK %dMhz, SYSCLK %dMhz (UART baudrate %d)\n", + mvTclkGet()/1000000, mvSysClkGet()/1000000, CONFIG_BAUDRATE); + return 1; +} + +U_BOOT_CMD( + dclk, 1, 1, clk_cmd, + "dclk - Display the MV device CLKs.\n", + " \n" + "\tDisplay the auto detect values of the TCLK and SYSCLK.\n" +); + +/****************************************************************************** +* Functional only when using Lauterbach to load image into DRAM +* Category - DEBUG +* Functionality- Display the array of registers the u-boot write to. +* +*****************************************************************************/ +#if defined(REG_DEBUG) +int reg_arry[REG_ARRAY_SIZE][2]; +int reg_arry_index = 0; +int print_registers( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + printf("Register display\n"); + + for (i=0; i < reg_arry_index; i++) + printf("Index %d 0x%x=0x%08x\n", i, (reg_arry[i][0] & 0x000fffff), reg_arry[i][1]); + + /* Print DRAM registers */ + printf("Index %d 0x%x=0x%08x\n", i++, 0x1500, MV_REG_READ(0x1500)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1504, MV_REG_READ(0x1504)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1508, MV_REG_READ(0x1508)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x150c, MV_REG_READ(0x150c)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1510, MV_REG_READ(0x1510)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1514, MV_REG_READ(0x1514)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1518, MV_REG_READ(0x1518)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x151c, MV_REG_READ(0x151c)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1400, MV_REG_READ(0x1400)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1404, MV_REG_READ(0x1404)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1408, MV_REG_READ(0x1408)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x140c, MV_REG_READ(0x140c)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1410, MV_REG_READ(0x1410)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x141c, MV_REG_READ(0x141c)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1420, MV_REG_READ(0x1420)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1424, MV_REG_READ(0x1424)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1428, MV_REG_READ(0x1428)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x147c, MV_REG_READ(0x147c)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1494, MV_REG_READ(0x1494)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x1498, MV_REG_READ(0x1498)); + printf("Index %d 0x%x=0x%08x\n", i++, 0x149c, MV_REG_READ(0x149c)); + + printf("Number of Reg %d \n", i); + + return 1; +} + +U_BOOT_CMD( + printreg, 1, 1, print_registers, + "printreg - Display the register array the u-boot write to.\n", + " \n" + "\tDisplay the register array the u-boot write to.\n" +); +#endif + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) +/****************************************************************************** +* Category - Etherent +* Functionality- Display PHY ports status (using SMI access). +* Need modifications (Yes/No) - No +*****************************************************************************/ +int sg_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(MV_INC_BOARD_QD_SWITCH) + printf( "Switch status not supported\n"); +#else + MV_U32 port; + for( port = 0 ; port < mvCtrlEthMaxPortGet(); port++ ) { + + printf( "PHY %d :\n", port ); + printf( "---------\n" ); + + mvEthPhyPrintStatus( mvBoardPhyAddrGet(port) ); + + printf("\n"); + } +#endif + return 1; +} + +U_BOOT_CMD( + sg, 1, 1, sg_cmd, + "sg - scanning the PHYs status\n", + " \n" + "\tScan all the Gig port PHYs and display their Duplex, Link, Speed and AN status.\n" +); +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + +#if defined(MV_INCLUDE_IDMA) + +/****************************************************************************** +* Category - DMA +* Functionality- Perform a DMA transaction +* Need modifications (Yes/No) - No +*****************************************************************************/ +int mvDma_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_8 cmd[20], c; + extern MV_8 console_buffer[]; + MV_U32 chan, src, dst, byteCount, ctrlLo; + MV_DMA_DEC_WIN win; + MV_BOOL err; + + /* IDMA channel */ + if( argc == 2 ) + chan = simple_strtoul( argv[1], NULL, 16 ); + else + chan = 0; + + /* source address */ + while(1) { + readline( "Source Address: " ); + strcpy( cmd, console_buffer ); + src = simple_strtoul( cmd, NULL, 16 ); + if( src == 0xffffffff ) printf( "Bad address !!!\n" ); + else break; + } + + /* desctination address */ + while(1) { + readline( "Destination Address: " ); + strcpy(cmd, console_buffer); + dst = simple_strtoul( cmd, NULL, 16 ); + if( dst == 0xffffffff ) printf("Bad address !!!\n"); + else break; + } + + /* byte count */ + while(1) { + readline( "Byte Count (up to 16M (0xffffff-1)): " ); + strcpy( cmd, console_buffer ); + byteCount = simple_strtoul( cmd, NULL, 16 ); + if( (byteCount > 0xffffff) || (byteCount == 0) ) printf("Bad value !!!\n"); + else break; + } + + /* compose the command */ + ctrlLo = ICCLR_BLOCK_MODE | ICCLR_NON_CHAIN_MODE | ICCLR_SRC_INC | ICCLR_DST_INC; + + + if (byteCount > _64K) + { + ctrlLo |= ICCLR_DESC_MODE_16M; + } + + /* set data transfer limit */ + while(1) { + printf( "Data transfer limit:\n" ); + printf( "(1) 8 bytes at a time.\n" ); + printf( "(2) 16 bytes at a time.\n" ); + printf( "(3) 32 bytes at a time.\n" ); + printf( "(4) 64 bytes at a time.\n" ); + printf( "(5) 128 bytes at a time.\n" ); + + c = getc(); + printf( "%c\n", c ); + + err = MV_FALSE; + + switch( c ) { + case 13: /* Enter */ + ctrlLo |= (ICCLR_DST_BURST_LIM_32BYTE | ICCLR_SRC_BURST_LIM_32BYTE); + printf( "32 bytes at a time.\n" ); + break; + case '1': + ctrlLo |= (ICCLR_DST_BURST_LIM_8BYTE | ICCLR_SRC_BURST_LIM_8BYTE); + break; + case '2': + ctrlLo |= (ICCLR_DST_BURST_LIM_16BYTE | ICCLR_SRC_BURST_LIM_16BYTE); + break; + case '3': + ctrlLo |= (ICCLR_DST_BURST_LIM_32BYTE | ICCLR_SRC_BURST_LIM_32BYTE); + break; + case '4': + ctrlLo |= (ICCLR_DST_BURST_LIM_64BYTE | ICCLR_SRC_BURST_LIM_64BYTE); + break; + case '5': + ctrlLo |= (ICCLR_DST_BURST_LIM_128BYTE | ICCLR_SRC_BURST_LIM_128BYTE); + break; + default: + printf( "Bad value !!!\n" ); + err = MV_TRUE; + } + + if( !err ) break; + } + + /* set ovveride source option */ + while(1) { + printf( "Override Source:\n" ); + printf( "(0) - no override\n" ); + mvDmaWinGet( 1, &win ); + printf( "(1) - use Win1 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 2, &win ); + printf( "(2) - use Win2 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 3, &win ); + printf( "(3) - use Win3 (%s)\n",mvCtrlTargetNameGet(win.target)); + + c = getc(); + printf( "%c\n", c ); + + err = MV_FALSE; + + switch( c ) { + case 13: /* Enter */ + case '0': + printf( "No override\n" ); + break; + case '1': + ctrlLo |= ICCLR_OVRRD_SRC_BAR(1); + break; + case '2': + ctrlLo |= ICCLR_OVRRD_SRC_BAR(2); + break; + case '3': + ctrlLo |= ICCLR_OVRRD_SRC_BAR(3); + break; + default: + printf("Bad value !!!\n"); + err = MV_TRUE; + } + + if( !err ) break; + } + + /* set override destination option */ + while(1) { + printf( "Override Destination:\n" ); + printf( "(0) - no override\n" ); + mvDmaWinGet( 1, &win ); + printf( "(1) - use Win1 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 2, &win ); + printf( "(2) - use Win2 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 3, &win ); + printf( "(3) - use Win3 (%s)\n",mvCtrlTargetNameGet(win.target)); + + c = getc(); + printf( "%c\n", c ); + + err = MV_FALSE; + + switch( c ) { + case 13: /* Enter */ + case '0': + printf( "No override\n" ); + break; + case '1': + ctrlLo |= ICCLR_OVRRD_DST_BAR(1); + break; + case '2': + ctrlLo |= ICCLR_OVRRD_DST_BAR(2); + break; + case '3': + ctrlLo |= ICCLR_OVRRD_DST_BAR(3); + break; + default: + printf("Bad value !!!\n"); + err = MV_TRUE; + } + + if( !err ) break; + } + + /* wait for previous transfer completion */ + while( mvDmaStateGet(chan) != MV_IDLE ); + + /* issue the transfer */ + mvDmaCtrlLowSet( chan, ctrlLo ); + mvDmaTransfer( chan, src, dst, byteCount, 0 ); + + /* wait for completion */ + while( mvDmaStateGet(chan) != MV_IDLE ); + + printf( "Done...\n" ); + return 1; +} + +U_BOOT_CMD( + dma, 2, 1, mvDma_cmd, + "dma - Perform DMA\n", + " \n" + "\tPerform DMA transaction with the parameters given by the user.\n" +); + +#endif /* #if defined(MV_INCLUDE_IDMA) */ + +/****************************************************************************** +* Category - Memory +* Functionality- Displays the MV's Memory map +* Need modifications (Yes/No) - Yes +*****************************************************************************/ +int displayMemoryMap_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvCtrlAddrDecShow(); + return 1; +} + +U_BOOT_CMD( + map, 1, 1, displayMemoryMap_cmd, + "map - Diasplay address decode windows\n", + " \n" + "\tDisplay controller address decode windows: CPU, PCI, Gig, DMA, XOR and COMM\n" +); + + + +#include "ddr2/spd/mvSpd.h" +#if defined(MV_INC_BOARD_DDIM) + +/****************************************************************************** +* Category - Memory +* Functionality- Displays the SPD information for a givven dimm +* Need modifications (Yes/No) - +*****************************************************************************/ + +int dimminfo_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int num = 0; + + if (argc > 1) { + num = simple_strtoul (argv[1], NULL, 10); + } + + printf("*********************** DIMM%d *****************************\n",num); + + dimmSpdPrint(num); + + printf("************************************************************\n"); + + return 1; +} + +U_BOOT_CMD( + ddimm, 2, 1, dimminfo_cmd, + "ddimm - Display SPD Dimm Info\n", + " [0/1]\n" + "\tDisplay Dimm 0/1 SPD information.\n" +); + +/****************************************************************************** +* Category - Memory +* Functionality- Copy the SPD information of dimm 0 to dimm 1 +* Need modifications (Yes/No) - +*****************************************************************************/ + +int spdcpy_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + printf("Copy DIMM 0 SPD data into DIMM 1 SPD..."); + + if (MV_OK != dimmSpdCpy()) + printf("\nDIMM SPD copy fail!\n"); + else + printf("Done\n"); + + return 1; +} + +U_BOOT_CMD( + spdcpy, 2, 1, spdcpy_cmd, + "spdcpy - Copy Dimm 0 SPD to Dimm 1 SPD \n", + "" + "" +); +#endif /* #if defined(MV_INC_BOARD_DDIM) */ + +/****************************************************************************** +* Functionality- Go to an address and execute the code there and return, +* defualt address is 0x40004 +*****************************************************************************/ +extern void cpu_dcache_flush_all(void); +extern void cpu_icache_flush_invalidate_all(void); + +void mv_go(unsigned long addr,int argc, char *argv[]) +{ + int rc; + addr = MV_CACHEABLE(addr); + char* envCacheMode = getenv("cacheMode"); + + /* + * pass address parameter as argv[0] (aka command name), + * and all remaining args + */ + + if(envCacheMode && (strcmp(envCacheMode,"write-through") == 0)) + { + int i=0; + + /* Flush Invalidate I-Cache */ + cpu_icache_flush_invalidate_all(); + + /* Drain write buffer */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); + + + } + else /*"write-back"*/ + { + int i=0; + + /* Flush Invalidate I-Cache */ + cpu_icache_flush_invalidate_all(); + + /* Drain write buffer */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); + + + /* Flush invalidate D-cache */ + cpu_dcache_flush_all(); + + + } + + + rc = ((ulong (*)(int, char *[]))addr) (--argc, &argv[1]); + + return; +} + +int g_cmd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0; + } + + addr = 0x40000; + + if (argc > 1) { + addr = simple_strtoul(argv[1], NULL, 16); + } + mv_go(addr,argc,&argv[0]); + return 1; +} + +U_BOOT_CMD( + g, CFG_MAXARGS, 1, g_cmd, + "g - start application at cached address 'addr'(default addr 0x40000)\n", + " addr [arg ...] \n" + "\tStart application at address 'addr'cachable!!!(default addr 0x40004/0x240004)\n" + "\tpassing 'arg' as arguments\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/****************************************************************************** +* Functionality- Searches for a value +*****************************************************************************/ +int fi_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 s_address,e_address,value,i,tempData; + MV_BOOL error = MV_FALSE; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 4){ + value = simple_strtoul(argv[1], NULL, 16); + s_address = simple_strtoul(argv[2], NULL, 16); + e_address = simple_strtoul(argv[3], NULL, 16); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + if(s_address == 0xffffffff || e_address == 0xffffffff) error = MV_TRUE; + if(s_address%4 != 0 || e_address%4 != 0) error = MV_TRUE; + if(s_address > e_address) error = MV_TRUE; + if(error) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + for(i = s_address; i < e_address ; i+=4) + { + tempData = (*((volatile unsigned int *)i)); + if(tempData == value) + { + printf("Value: %x found at ",value); + printf("address: %x\n",i); + return 1; + } + } + printf("Value not found!!\n"); + return 1; +} + +U_BOOT_CMD( + fi, 4, 1, fi_cmd, + "fi - Find value in the memory.\n", + " value start_address end_address\n" + "\tSearch for a value 'value' in the memory from address 'start_address to\n" + "\taddress 'end_address'.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/****************************************************************************** +* Functionality- Compare the memory with Value. +*****************************************************************************/ +int cmpm_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 s_address,e_address,value,i,tempData; + MV_BOOL error = MV_FALSE; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 4){ + value = simple_strtoul(argv[1], NULL, 16); + s_address = simple_strtoul(argv[2], NULL, 16); + e_address = simple_strtoul(argv[3], NULL, 16); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + if(s_address == 0xffffffff || e_address == 0xffffffff) error = MV_TRUE; + if(s_address%4 != 0 || e_address%4 != 0) error = MV_TRUE; + if(s_address > e_address) error = MV_TRUE; + if(error) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + for(i = s_address; i < e_address ; i+=4) + { + tempData = (*((volatile unsigned int *)i)); + if(tempData != value) + { + printf("Value: %x found at address: %x\n",tempData,i); + } + } + return 1; +} + +U_BOOT_CMD( + cmpm, 4, 1, cmpm_cmd, + "cmpm - Compare Memory\n", + " value start_address end_address.\n" + "\tCompare the memory from address 'start_address to address 'end_address'.\n" + "\twith value 'value'\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + + + +#if 0 +/****************************************************************************** +* Category - Etherent +* Functionality- Display PHY ports status (using SMI access). +* Need modifications (Yes/No) - No +*****************************************************************************/ +int eth_show_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ethRegs(argv[1]); + ethPortRegs(argv[1]); + ethPortStatus(argv[1]); + ethPortQueues(argv[1],0,0,1); + return 1; +} + +U_BOOT_CMD( + ethShow, 2, 2, eth_show_cmd, + "ethShow - scanning the PHYs status\n", + " \n" + "\tScan all the Gig port PHYs and display their Duplex, Link, Speed and AN status.\n" +); +#endif + +#if defined(MV_INCLUDE_PEX) + +#include "pci/mvPci.h" + +int pcie_phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvPexPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + pciePhyRead, 3, 3, pcie_phy_read_cmd, + "phyRead - Read PCI-E Phy register\n", + " PCI-E_interface Phy_offset. \n" + "\tRead the PCI-E Phy register. \n" +); + + +int pcie_phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvPexPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + pciePhyWrite, 4, 4, pcie_phy_write_cmd, + "pciePhyWrite - Write PCI-E Phy register\n", + " PCI-E_interface Phy_offset value.\n" + "\tWrite to the PCI-E Phy register.\n" +); + +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) + +#include "eth-phy/mvEthPhy.h" + +int phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvEthPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + phyRead, 3, 3, phy_read_cmd, + "phyRead - Read Phy register\n", + " Phy_address Phy_offset. \n" + "\tRead the Phy register. \n" +); + + +int phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvEthPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + phyWrite, 4, 4, phy_write_cmd, + "phyWrite - Write Phy register\n", + " Phy_address Phy_offset value.\n" + "\tWrite to the Phy register.\n" +); + + +int switch_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvEthSwitchRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), simple_strtoul( argv[3], NULL, 16 ), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + switchRegRead, 4, 4, switch_read_cmd, + "switchRegRead - Read switch register\n", + " Port_number Phy_address Phy_offset. \n" + "\tRead the switch register. \n" +); + + +int switch_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvEthSwitchRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 ), + simple_strtoul( argv[4], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + switchRegWrite, 4, 4, switch_write_cmd, + "switchRegWrite - Write switch register\n", + " Port_number Phy_address Phy_offset value.\n" + "\tWrite to the switch register.\n" +); +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + +#endif /* MV_TINY */ + +int _4BitSwapArry[] = {0,8,4,0xc,2,0xa,6,0xe,1,9,5,0xd,3,0xb,7,0xf}; +int _3BitSwapArry[] = {0,4,2,6,1,5,3,7}; + +int do_satr(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char *cmd, *s; + MV_U8 data0=0, data1=0, devNum0=0, devNum1=0; + MV_U8 moreThenOneDev=0, regNum = 0; + MV_U8 mask0=0, mask1=0, shift0=0, shift1=0; + MV_U8 val=0, width=0; + + /* at least two arguments please */ + if (argc < 2) + goto usage; + + cmd = argv[1]; + + if (strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0) + goto usage; + + /* read write */ + if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) { + int read; + + + read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ + + /* In write mode we have additional value */ + if (!read) + { + if (argc < 3) + goto usage; + else + /* Value for write */ + val = (ulong)simple_strtoul(argv[2], NULL, 16); + } + + printf("\nS@R %s: ", read ? "read" : "write"); + s = strchr(cmd, '.'); + if ((s != NULL) && (strcmp(s, ".cpu") == 0)) + { +#if defined(DB_88F6180A) || defined(DB_88F6280A) + moreThenOneDev = 0; + regNum = 0; + devNum0 = 0; + mask0 = 0x7; + shift0 = 0; + mask1 = 0x0; + shift1 = 0; + width = 3; +#else + moreThenOneDev = 0; + regNum = 0; + devNum0 = 0; + mask0 = 0xf; + shift0 = 0; + mask1 = 0x0; + shift1 = 0; + width = 4; +#endif + } + + if ((s != NULL) && (strcmp(s, ".cpu2ddr") == 0)) + { + moreThenOneDev = 1; + regNum = 0; + devNum0 = 0; + devNum1 = 1; + mask0 = 0x10; + shift0 = 4; + mask1 = 0x7; + shift1 = 1; + width = 4; + } + + if ((s != NULL) && (strcmp(s, ".cpu2L2") == 0)) + { + moreThenOneDev = 1; + regNum = 0; + devNum0 = 1; + devNum1 = 2; + mask0 = 0x18; + shift0 = 3; + mask1 = 0x1; + shift1 = 2; + width = 3; + } + + if ((s != NULL) && (strcmp(s, ".SSCG") == 0)) + { +#ifdef DB_88F6180A + moreThenOneDev = 0; + regNum = 0; + devNum0 = 0; + mask0 = 0x8; + shift0 = 3; + mask1 = 0x0; + shift1 = 0; +#else + moreThenOneDev = 0; + regNum = 0; + devNum0 = 2; + mask0 = 0x4; + shift0 = 2; + mask1 = 0x0; + shift1 = 0; +#endif + } + +#ifdef DB_88F6282A + if ((s != NULL) && (strcmp(s, ".PEXCLK0") == 0)) + { + moreThenOneDev = 0; + regNum = 0; + devNum0 = 2; + mask0 = 0x10; + shift0 = 4; + mask1 = 0x0; + shift1 = 0; + } + + if ((s != NULL) && (strcmp(s, ".PEXCLK1") == 0)) + { + moreThenOneDev = 0; + regNum = 0; + devNum0 = 2; + mask0 = 0x2; + shift0 = 1; + mask1 = 0x0; + shift1 = 0; + } +#else + if ((s != NULL) && (strcmp(s, ".PEXCLK") == 0)) + { + moreThenOneDev = 0; + regNum = 0; + devNum0 = 2; + mask0 = 0x10; + shift0 = 4; + mask1 = 0x0; + shift1 = 0; + } +#endif + + if ((s != NULL) && ((strcmp(s, ".MPP18") == 0) || (strcmp(s, ".TCLK") == 0)) ) + { + +#ifdef DB_88F6180A + moreThenOneDev = 0; + regNum = 0; + devNum0 = 0; + mask0 = 0x10; + shift0 = 4; + mask1 = 0x0; + shift1 = 0; +#else + moreThenOneDev = 0; + regNum = 0; + devNum0 = 2; + mask0 = 0x8; + shift0 = 3; + mask1 = 0x0; + shift1 = 0; +#endif + } + + if (read) { + /* read */ + data0 = mvBoarTwsiSatRGet(devNum0, regNum); + if (moreThenOneDev) + data1 = mvBoarTwsiSatRGet(devNum1, regNum); + + data0 = ((data0 & mask0) >> shift0); + + if (moreThenOneDev) + { + data1 = ((data1 & mask1) << shift1); + data0 |= data1; + } + + /* Swap value */ + switch(width) + { + case 4: + data0 = _4BitSwapArry[data0]; + break; + case 3: + data0 = _3BitSwapArry[data0]; + break; + case 2: + data0 = (((data0 & 0x1) << 0x1) | ((data0 & 0x2) >> 0x1)); + break; + } + + printf("Read S@R val %x\n", data0); + + } else { + + /* Swap value */ + switch(width) + { + case 4: + val = _4BitSwapArry[val]; + break; + case 3: + val = _3BitSwapArry[val]; + break; + case 2: + val = (((val & 0x1) << 0x1) | ((val & 0x2) >> 0x1)); + break; + } + + /* read modify write */ + data0 = mvBoarTwsiSatRGet(devNum0, regNum); + data0 = (data0 & ~mask0); + data0 |= ((val << shift0) & mask0); + if (mvBoarTwsiSatRSet(devNum0, regNum, data0) != MV_OK) + { + printf("Write S@R first device val %x fail\n", data0); + return 1; + } + printf("Write S@R first device val %x succeded\n", data0); + + if (moreThenOneDev) + { + data1 = mvBoarTwsiSatRGet(devNum1, regNum); + data1 = (data1 & ~mask1); + data1 |= ((val >> shift1) & mask1); + if (mvBoarTwsiSatRSet(devNum1, regNum, data1) != MV_OK) + { + printf("Write S@R second device val %x fail\n", data1); + return 1; + } + printf("Write S@R second device val %x succeded\n", data1); + } + } + + return 0; + } + +usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +#ifdef DB_88F6180A +U_BOOT_CMD(SatR, 5, 1, do_satr, + "SatR - sample at reset sub-system, relevent for DB only\n", + "SatR read.cpu - read cpu/L2/DDR clock from S@R devices\n" + "SatR read.SSCG - read SSCG state from S@R devices [0 ~ en]\n" + "SatR read.MPP18 - reserved\n" + "SatR write.cpu val - write cpu/L2/DDR clock val to S@R devices [0,1,..,7]\n" + "SatR write.SSCG val - write SSCG state val to S@R devices [0 ~ en]\n" + "SatR write.MPP18 - reserved\n" +); +#elif defined(DB_88F6280A) +U_BOOT_CMD(SatR, 5, 1, do_satr, + "SatR - sample at reset sub-system, relevent for DB only\n", + "SatR read.cpu - read cpu/L2/DDR clock from S@R devices\n" +); + +#elif defined(DB_88F6192A) || defined(DB_88F6281A) || defined(DB_88F6282A) +U_BOOT_CMD(SatR, 5, 1, do_satr, + "SatR - sample at reset sub-system, relevent for DB only\n", + "SatR read.cpu - read cpu clock from S@R devices\n" + "SatR read.cpu2ddr - read cpu2ddr clock ratio from S@R devices\n" + "SatR read.cpu2L2 - read cpu2L2 clock ratio from S@R devices\n" + "SatR read.SSCG - read SSCG state from S@R devices [0 ~ en]\n" +#ifdef DB_88F6282A + "SatR read.PEXCLK[0/1] - read PCI-E [0/1] clock state from S@R devices [0 ~ input]\n" +#else + "SatR read.PEXCLK - read PCI-E clock state from S@R devices [0 ~ input]\n" +#endif +#if defined(DB_88F6281A) || defined(DB_88F6282A) + "SatR read.TCLK - read TCLK value (0 = 200MHz, 1 = 166MHz)\n" +#else + "SatR read.MPP18 - reserved\n" +#endif + "SatR write.cpu val - write cpu clock val to S@R devices [0,1,..,F]\n" + "SatR write.cpu2ddr val - write cpu2ddr clock ratio val to S@R devices [0,1,..,F]\n" + "SatR write.cpu2L2 val - write cpu2L2 clock ratio val to S@R devices [0,1,..,7]\n" + "SatR write.SSCG val - write SSCG state val to S@R devices [0 ~ en]\n" +#ifdef DB_88F6282A + "SatR write.PEXCLK[0/1] - write PCI-E [0/1] clock state from S@R devices [0 ~ input]\n" +#else + "SatR write.PEXCLK - write PCI-E clock state from S@R devices [0 ~ input]\n" +#endif +#if defined(DB_88F6281A) || defined(DB_88F6282A) + "SatR write.TCLK - write TCLK value (0 = 200MHz, 1 = 166MHz)\n" +#else + "SatR write.MPP18 - reserved\n" +#endif +); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) +extern void recoveryHandle(void); +int do_rcvr (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + recoveryHandle(); + return 1; +} + +U_BOOT_CMD( + rcvr, 3, 1, do_rcvr, + "rcvr\t- Satrt recovery process (Distress Beacon with TFTP server)\n", + "\n" +); +#endif /* CFG_CMD_RCVR */ + +#ifdef CFG_DIAG + +#include "../diag/diag.h" +extern diag_func_t *diag_sequence[]; + +int mv_diag (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int test_no = 0, no_of_tests = 0; + diag_func_t **diag_func_ptr; + + + for (diag_func_ptr = diag_sequence; *diag_func_ptr; ++diag_func_ptr) + no_of_tests++; + + if (argc > 1) + { + test_no = simple_strtoul(argv[1], NULL, 10); + if (test_no > no_of_tests) + { + printf("There are only %d tests\n", no_of_tests); + printf("Usage: %s\n", cmdtp->help); + return 0; + } + + test_no--; + (*diag_sequence[test_no])(); + return 0; + } + + for (diag_func_ptr = diag_sequence; *diag_func_ptr; ++diag_func_ptr) + { + printf("\n"); + if((*diag_func_ptr)()) + break; + } + + if(*diag_func_ptr == NULL) + printf("\nDiag completed\n"); + else + printf("\nDiag FAILED\n"); + + return 0; +} + +U_BOOT_CMD( + mv_diag, 2, 0, mv_diag, + "mv_diag - perform board diagnostics\n" + "mv_diag - run all available tests\n" + "mv_diag [1|2|...]\n" + " - run specified test number\n", + "mv_diag - perform board diagnostics\n" + "mv_diag - run all available tests\n" + "mv_diag [1|2|...]\n" + " - run specified test number\n" +); +#endif /*CFG_DIAG*/ + +#if defined(CONFIG_BUFFALO_PLATFORM) +int bfTestWol(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + MV_U8 mac[6]; + char env_ethaddr[16]; + char *env; + char *end; + int i = 0; + int target_eth = 0; + int verbose = 0; + int gmagic_wait = 0; /* generic magic wait flag. using bfSetWolMagicWaitMode*/ + int flag_ope_disable = 0; + + for(i = 1; i < argc; i++) + { + if((strlen(argv[i]) == 1) && (argv[i][0] >= '0' && argv[i][0] <= '9')) + { + target_eth = simple_strtoul(argv[i], &end, 10); + } + else if(strncmp(argv[i], "v", 1) == 0) + { + verbose = 1; + } + else if(strncmp(argv[i], "m", 1) == 0) + { + gmagic_wait = 1; + } + else if(strncmp(argv[i], "d", 1) == 0) + { + flag_ope_disable = 1; + } + } + + memset(env_ethaddr, 0, sizeof(env_ethaddr)); + if(target_eth == 0) + { + sprintf(env_ethaddr, "ethaddr"); + } + else + { + if(target_eth >= 2) + return -1; + sprintf(env_ethaddr, "eth%daddr", target_eth); + } + + printf("target is eth%d\n", target_eth); + + if(flag_ope_disable == 1) + { + bfControlWolInterrupt(target_eth, FLAG_BUFFALO_WOL_INTERRUPT_DISABLE); + } + else + { + if(gmagic_wait == 1) + bfSetWolMagicWaitMode(target_eth); + else + bfSetWolFrameWaitMode(target_eth, verbose); + } +} + +U_BOOT_CMD( + test_wol, 4, 0, bfTestWol, + "test_wol- wol test suite.\n", + "test_wol\n" + "test_wol v - test WOL mode by verbose mode. default is non verbose mode.\n" + "test_wol m - test magic patern mode(not a frame matching). default is frame patern matching.\n" + "test_wol d - disable WOL mode.\n" + "test_wol 1 - test WOL by port 1. default is 0.\n" +); + +int bfGetWolStatus(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U8 i = 0; + int target_eth = 0; + int loop = 0; + int flag_reset = 0; + MV_U8 disp_interval = 100; + char *end; + MV_U16 wol_stat = 0; + + for(i = 1; i < argc; i++) + { + if((strlen(argv[i]) == 1) && (argv[i][0] >= '0' && argv[i][0] <= '9')) + { + target_eth = simple_strtoul(argv[i], &end, 10); + } + else if(strncmp(argv[i], "l", 1) == 0) + { + loop = 1; + } + else if(strncmp(argv[i], "r", 1) == 0) + { + flag_reset = 1; + } + } + if(loop == 1) + { + while (1) + { + wol_stat = bfGetWolInterruptStatus(target_eth, 0); + if(wol_stat) + { + printf("I've received WOL packet!(0x%04x : %s)\n", wol_stat, bfGetWolPatternString(wol_stat)); + break; + } + if(disp_interval > 0) + disp_interval--; + else + { + disp_interval = 100; + printf("I'm waiting WOL packet...(0x%04x)\n", wol_stat); + } + mvOsDelay(100); + } + } + else if(flag_reset == 1) + { + do_reset(NULL, 0, 0, NULL); + } + else + { + bfGetWolInterruptStatus(target_eth, 1); + } +} + +U_BOOT_CMD( + chk_wol, 3, 0, bfGetWolStatus, + "chk_wol - wol test suite.\n", + "chk_wol\n" + "chk_wol l - check wol status as a daemon mode.\n" + "chk_wol r - reset cpu.\n" +); +#endif /* CONFIG_BUFFALO_PLATFORM) */ diff --git a/board/mv_feroceon/mv_kw/mv_dram.c b/board/mv_feroceon/mv_kw/mv_dram.c new file mode 100644 index 0000000..c22a115 --- /dev/null +++ b/board/mv_feroceon/mv_kw/mv_dram.c @@ -0,0 +1,341 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "ddr2/mvDramIf.h" +#include "mvOs.h" +#include "mvBoardEnvLib.h" +#include "ddr2/mvDramIfRegs.h" +#include "mvCpuIfRegs.h" + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +extern void i2c_init(int speed, int slaveaddr); +extern void _start(void); +extern unsigned int mvCpuPclkGet(void); +extern void reset_cpu(void); +extern int dramBoot; + + +#ifdef MV_INC_DRAM_MFG_TEST +static MV_VOID mvDramMfgTrst(void); +static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count); +static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count); +#endif + +MV_VOID mvIntrfaceWidthPrint(MV_VOID) +{ + printf(" 16bit width"); +} + +MV_VOID mvIntrfaceParamPrint(MV_VOID) +{ + MV_U32 temp; + + printf("DRAM"); + temp = MV_REG_READ(0x1400); + if (temp & BIT14) + { + printf(" (DDR3)"); + switch((MV_REG_READ(0x15D0) >> 2) & 0xd) + { + case 0x4: printf(" CAS Latency = 5"); + break; + case 0x8: printf(" CAS Latency = 6"); + break; + case 0xC: printf(" CAS Latency = 7"); + break; + default: printf(" unknown CAL "); + break; + } + } + else + { + printf(" (DDR2)"); + switch((MV_REG_READ(0x141c) >> 4) & 0x7) + { + case 0x3: printf(" CAS Latency = 3"); + break; + case 0x4: printf(" CAS Latency = 4"); + break; + case 0x5: printf(" CAS Latency = 5"); + break; + case 0x6: printf(" CAS Latency = 6"); + break; + default: printf(" unknown CAL "); + break; + } + } + + temp = MV_REG_READ(0x1408); + printf(" tRP = %d tRAS = %d tRCD=%d\n", + ((temp >> 8) & 0xf) + 1, ((temp >> 16) & 0x10) + (temp & 0xf) + 1, ((temp >> 4) & 0xf) + 1); +} + +int dram_init (void) +{ + + DECLARE_GLOBAL_DATA_PTR; + unsigned int i, dramTotalSize=0; + char name[20]; + MV_32 memBase, temp; + + mvCtrlModelRevNameGet(name); + printf("\nSoc: %s", name); + + printf("CPU running @ %dMhz L2 running @ %dMhz\n", mvCpuPclkGet()/1000000, mvCpuL2ClkGet()/1000000); +#ifdef MV_TCLK_CALC + printf("SysClock = %dMhz , Calc TClock = %dMhz \n\n", CFG_BUS_CLK/1000000, CFG_TCLK/1000000); +#else + printf("SysClock = %dMhz , TClock = %dMhz \n\n", CFG_BUS_CLK/1000000, CFG_TCLK/1000000); +#endif +#if defined(MV_INC_BOARD_DDIM) + /* Call dramInit */ + if (0 == (dramTotalSize = initdram(0))) + { + printf("DRAM Initialization Failed\n"); + reset_cpu(); + return (1); + } +#endif + + mvIntrfaceParamPrint(); + + for(i = 0; i< MV_DRAM_MAX_CS; i++) + { +#if !defined(MV_88F6082L) && defined(MV_88F6082) + if (mvCtrlModelRevGet() == MV_6082_A0_ID) + { + gd->bd->bi_dram[i].start = (i)?_16M:0; + gd->bd->bi_dram[i].size = _8M; + } + else + { + memBase = mvDramIfBankBaseGet(i); + if (MV_ERROR == memBase) + gd->bd->bi_dram[i].start = 0; + else + gd->bd->bi_dram[i].start = memBase; + + gd->bd->bi_dram[i].size = mvDramIfBankSizeGet(i); + } +#else + memBase = mvDramIfBankBaseGet(i); + if (MV_ERROR == memBase) + gd->bd->bi_dram[i].start = 0; + else + gd->bd->bi_dram[i].start = memBase; + + gd->bd->bi_dram[i].size = mvDramIfBankSizeGet(i); +#endif + dramTotalSize += gd->bd->bi_dram[i].size; + if (gd->bd->bi_dram[i].size) + { + printf("DRAM CS[%d] base 0x%08x ",i, gd->bd->bi_dram[i].start); + mvSizePrint(gd->bd->bi_dram[i].size); + printf("\n"); + } + } + + printf("DRAM Total "); + mvSizePrint(dramTotalSize); + mvIntrfaceWidthPrint(); + printf("\n"); +#ifdef MV_INC_DRAM_MFG_TEST + mvDramMfgTrst(); +#endif + return 0; +} + +#if defined(MV_INC_BOARD_DDIM) + +/* u-boot interface function to SDRAM init - this is where all the + * controlling logic happens */ +long int initdram(int board_type) +{ + MV_VOIDFUNCPTR pRom; + MV_U32 forcedCl; /* Forced CAS Latency */ + MV_U32 totalSize; + char * env; + MV_TWSI_ADDR slave; + + /* r0 <- current position of code */ + /* test if we run from flash or RAM */ + if(dramBoot != 1) + { + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(CFG_I2C_SPEED, CFG_TCLK, &slave, 0); + + /* Calculating MIN/MAX CAS latency according to user settings */ + env = getenv("CASset"); + + if(env && (strcmp(env,"1.5") == 0)) + { + forcedCl = 15; + } + else if(env && (strcmp(env,"2") == 0)) + { + forcedCl = 20; + } + else if(env && (strcmp(env,"2.5") == 0)) + { + forcedCl = 25; + } + else if(env && (strcmp(env,"3") == 0)) + { + forcedCl = 30; + } + else if(env && (strcmp(env,"4") == 0)) + { + forcedCl = 40; + } + else if(env && (strcmp(env,"5") == 0)) + { + forcedCl = 50; + } + else if(env && (strcmp(env,"6") == 0)) + { + forcedCl = 60; + } + else + { + forcedCl = 0; + } + + /* detect the dram configuartion parameters */ + if (MV_OK != mvDramIfDetect(forcedCl,1)) + { + printf("DRAM Auto Detection Failed! System Halt!\n"); + return 0; + } + + /* set the dram configuration */ + /* Calculate jump address of _mvDramIfConfig() */ + +#if defined(MV_BOOTROM) + pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) + + (MV_VOIDFUNCPTR)CFG_MONITOR_BASE + (MV_VOIDFUNCPTR)MONITOR_HEADER_LEN); +#else + pRom = (MV_VOIDFUNCPTR)(((MV_VOIDFUNCPTR)_mvDramIfConfig - (MV_VOIDFUNCPTR)_start) + + (MV_VOIDFUNCPTR)CFG_MONITOR_BASE); +#endif + + + (*pRom) (); /* Jump to _mvDramIfConfig*/ + } + + totalSize = mvDramIfSizeGet(); + + + return(totalSize); +} + +#endif /* #if defined(MV_INC_BOARD_DDIM) */ + +#ifdef MV_INC_DRAM_MFG_TEST +static MV_VOID mvDramMfgTrst(void) +{ + + /* Memory test */ + DECLARE_GLOBAL_DATA_PTR; + unsigned int mem_len,i,j, pattern; + unsigned int *mem_start; + char *env; + + env = getenv("enaPost"); + if(!env || ( (strcmp(env,"Yes") == 0) || (strcmp(env,"yes") == 0) ) ) + { + printf("Memory test pattern: "); + + for (j = 0 ; j<2 ; j++) + { + + switch(j){ + case 0: + pattern=0x55555555; + printf("0x%X, ",pattern); + break; + case 1: + pattern=0xAAAAAAAA; + printf("0x%X, ",pattern); + break; + default: + pattern=0x0; + printf("0x%X, ",pattern); + break; + } + + for(i = 0; i< MV_DRAM_MAX_CS; i++) + { + mem_start = (unsigned int *)gd->bd->bi_dram[i].start; + mem_len = gd->bd->bi_dram[i].size; + if (i == 0) + { + mem_start+= _4M; + mem_len-= _4M; + } + mem_len/=4; + if (MV_OK != mv_mem_test(mem_start, pattern, mem_len)) + { + printf(" Fail!\n"); + while(1); + } + } + } + printf(" Pass\n"); + } +} + + +static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count) +{ + int i; + for (i=0 ; i< count ; i+=1) + *(pMem + i) = pattern; + + if (MV_OK != mv_mem_cmp(pMem, pattern, count)) + { + return MV_ERROR; + } + return MV_OK; +} + +static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count) +{ + int i; + for (i=0 ; i< count ; i+=1) + { + if (*(pMem + i) != pattern) + { + printf("Fail\n"); + printf("Test failed at 0x%x\n",(pMem + i)); + return MV_ERROR; + } + } + + return MV_OK; +} +#endif /* MV_INC_DRAM_MFG_TEST */ diff --git a/board/mv_feroceon/mv_kw/mv_main.c b/board/mv_feroceon/mv_kw/mv_main.c new file mode 100644 index 0000000..10b09d9 --- /dev/null +++ b/board/mv_feroceon/mv_kw/mv_main.c @@ -0,0 +1,2208 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include "mvTypes.h" +#include "mvBoardEnvLib.h" +#include "mvCpuIf.h" +#include "mvCtrlEnvLib.h" +#include "mv_mon_init.h" +#include "mvDebug.h" +#include "device/mvDevice.h" +#include "twsi/mvTwsi.h" +#include "eth/mvEth.h" +#include "pex/mvPex.h" +#include "gpp/mvGpp.h" +#include "sys/mvSysUsb.h" +#include "mv_service.h" + +#ifdef MV_INCLUDE_RTC +#include "rtc/integ_rtc/mvRtc.h" +#include "rtc.h" +#elif CONFIG_RTC_DS1338_DS1339 +#include "rtc/ext_rtc/mvDS133x.h" +#endif + +#if defined(MV_INCLUDE_XOR) +#include "xor/mvXor.h" +#endif +#include "lcd/mvLcd.h" +#if defined(MV_INCLUDE_IDMA) +#include "sys/mvSysIdma.h" +#include "idma/mvIdma.h" +#endif +#if defined(MV_INCLUDE_USB) +#include "usb/mvUsb.h" +#endif + +#include "cpu/mvCpu.h" +#include "nand.h" +#ifdef CONFIG_PCI +# include +#endif +#include "pci/mvPciRegs.h" + +#include +#include + +#include "net.h" +#include +#include + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +#ifdef CONFIG_BUFFALO_PLATFORM +#include "eth-phy/mvEthPhy.h" +#include "buffalo/BuffaloWol.h" +#include +#include + #define SWAP_LONG(x) \ + ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) +#endif + +extern int ext2fs_devread (int sector, int log2blksize, int byte_offset, int byte_len, + char *buf); + +/* CPU address decode table. */ +MV_CPU_DEC_WIN mvCpuAddrWinMap[] = MV_CPU_IF_ADDR_WIN_MAP_TBL; + +static void mvHddPowerCtrl(void); + +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) +static void recoveryDetection(void); +void recoveryHandle(void); +static u32 rcvrflag = 0; +#endif +void mv_cpu_init(void); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +int mv_set_power_scheme(void); +#endif + +#ifdef CFG_FLASH_CFI_DRIVER +MV_VOID mvUpdateNorFlashBaseAddrBank(MV_VOID); +int mv_board_num_flash_banks; +extern flash_info_t flash_info[]; /* info for FLASH chips */ +extern unsigned long flash_add_base_addr (uint flash_index, ulong flash_base_addr); +#endif /* CFG_FLASH_CFI_DRIVER */ + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) +extern MV_VOID mvBoardEgigaPhySwitchInit(void); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +/* Define for SDK 2.0 */ +int __aeabi_unwind_cpp_pr0(int a,int b,int c) {return 0;} +int __aeabi_unwind_cpp_pr1(int a,int b,int c) {return 0;} +#endif + +extern nand_info_t nand_info[]; /* info for NAND chips */ +MV_VOID mvMppModuleTypePrint(MV_VOID); + +#ifdef MV_NAND_BOOT +extern MV_U32 nandEnvBase; +#endif + +/* Define for SDK 2.0 */ +int raise(void) {return 0;} + +#if defined(CONFIG_BUFFALO_PLATFORM) +MV_VOID bfEthPhyPolaritySet(void); +MV_BOOL bfIsStartBootProcess(void); +void bfErrorCodeDisp(MV_32 gppbit, int code); +/*cmd_boot.c*/ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +static block_dev_desc_t *get_dev (char* ifname, int dev) +{ + if (strncmp(ifname,"ide",3)==0) { + extern block_dev_desc_t * ide_get_dev(int dev); + return((dev >= CFG_IDE_MAXDEVICE) ? NULL : ide_get_dev(dev)); + } +} + +MV_BOOL isValidMacAddr(const char *macAddr) +{ + int i; + + for (i = 0; i < 17; i++) { + if ((i+1) % 3) { + if (!isxdigit(*macAddr)) return MV_FALSE; + } + else { + if (*macAddr != ':') return MV_FALSE; + } + macAddr++; + } + + return MV_TRUE; +} + +MV_BOOL isMyDisk(int dev, const char *macAddr) +{ + block_dev_desc_t *dev_desc; + ulong part_length; + char macAddrOnDisk[] = "00:00:00:00:00:00"; + MV_BOOL ret = MV_FALSE; + + if (!macAddr) + goto _isMyDisk_end; + + dev_desc = get_dev("ide", dev); + if (!dev_desc) { + printf ("\n** Block device %d not supported\n", dev); + goto _isMyDisk_end; + } + + if ((part_length = ext2fs_set_blk_dev(dev_desc, 0)) == 0) { + printf("** Bad partition - %d:%d **\n", dev, 0); + goto _isMyDisk_end; + } + + if (!ext2fs_devread(0, 0, 6, 17, macAddrOnDisk)) { + printf("** Bad ext2 partition or disk - %d:%d **\n", dev, 0); + goto _isMyDisk_end; + } + + if (!isValidMacAddr(macAddrOnDisk)) { + if (!ext2fs_devread(0, 0, 0x28, 17, macAddrOnDisk)) { + printf ("** Bad ext2 partition or disk - %d:%d **\n", dev, 0); + goto _isMyDisk_end; + } + } + + printf("MAC Address read from block device %d : %s\n", dev, macAddrOnDisk); + + if (!isValidMacAddr(macAddrOnDisk)) + goto _isMyDisk_end; + + if (strnicmp(macAddrOnDisk, macAddr, 17) == 0) + ret = MV_TRUE; + + _isMyDisk_end: + ext2fs_close(); + return ret; +} + + +#define KERNEL_LOAD_ADDR 0x00100000 +#define INITRD_LOAD_ADDR 0x00800000 + +MV_STATUS serch_boot_drv(char max_disk) +{ + image_header_t header; + ulong data, len, checksum, newest_disk_ihtime=0; + int i ; + char init_argv[5][120] = {"ext2load","ide","0:1","",""}; + + char *init_p[5]; + int newest_fw_dev = -1 ; /*NG*/ + char bootcmd[256] = ""; + char tmpbuf[256]; + char *env; + char *pAddr; + char macAddr[] = "00:00:00:00:00:00"; + MV_BOOL my_disk = MV_FALSE; + MV_BOOL my_disk_found = MV_FALSE; + + env = getenv("initrd"); + if (!env) { + printf("Getting environment variable 'initrd' failed.\n"); + return MV_FAIL; + } + + sprintf(init_argv[3], "0x%08x", INITRD_LOAD_ADDR); + sprintf(init_argv[4], "/%s", env); + + for (i=0; i < 5; i++) { + init_p[i] = init_argv[i]; + } + + pAddr = getenv("ethaddr"); + if (!pAddr) { + pAddr = getenv("eth1addr"); + if (!pAddr) { + pAddr = macAddr; + } + } + + printf("MAC Address : %s\n", pAddr); + + for (i = 0 ;i < max_disk ; i++) { + if (isMyDisk(i, pAddr)) { + my_disk = MV_TRUE; + } + else if (!my_disk_found) { + my_disk = MV_FALSE; + } + else { + printf("SKIP Loading kernel and initrd\n" + "This HDD [block device %d] does not seem to contain my system.\n", + i); + continue; + } + + sprintf(init_argv[2], "%d:1", i); + if(do_ext2load(0, 0, 5 , init_p) == 1) { + DB(printf ("%s (%d)>No init_file %x \n", + __FUNCTION__, __LINE__, i)); + continue; + } + + memmove (&header, (char *)INITRD_LOAD_ADDR, sizeof(image_header_t)); + DB(print_image_hdr((image_header_t *)INITRD_LOAD_ADDR)); + + if (header.ih_magic != SWAP_LONG(IH_MAGIC)) { + DB(printf ("%s (%d)>Bad majic No. %x \n", + __FUNCTION__, __LINE__, i)); + continue; + } + + data = (ulong)&header; + len = sizeof(image_header_t); + + checksum = SWAP_LONG(header.ih_hcrc); + header.ih_hcrc = 0; + if (crc32 (0, (char *)data, len) != checksum) { + DB(printf("%s (%d)>Bad Header Checksum\n", + __FUNCTION__, __LINE__)); + continue; + } + + data = INITRD_LOAD_ADDR + sizeof(image_header_t); + len = SWAP_LONG(header.ih_size); + + if (crc32 (0, (char *)data, len) != SWAP_LONG(header.ih_dcrc)) { + DB(printf("%s (%d)>Bad Data CRC\n", + __FUNCTION__, __LINE__)); + continue; + } + + if (newest_disk_ihtime < SWAP_LONG(header.ih_time)) { + if (my_disk) { + newest_fw_dev = i; + newest_disk_ihtime = SWAP_LONG(header.ih_time); + my_disk_found = MV_TRUE; + } + else if (!my_disk && !my_disk_found) { + newest_fw_dev = i; + newest_disk_ihtime = SWAP_LONG(header.ih_time); + } + } + else { + if (my_disk && !my_disk_found) { + newest_fw_dev = i; + newest_disk_ihtime = SWAP_LONG(header.ih_time); + my_disk_found = MV_TRUE; + } + } + } + + if (newest_fw_dev == -1) + return MV_FAIL; + + printf("Booting from Device %d\n", newest_fw_dev); + + env = getenv("initrd"); + if (!env) + return MV_FAIL; + + sprintf(init_argv[2], "%d:1", newest_fw_dev); + sprintf(init_argv[3], "0x%08x", INITRD_LOAD_ADDR); + sprintf(init_argv[4], "/%s", env); + + sprintf(bootcmd, "%s %s %s %s %s; ", + init_argv[0], + init_argv[1], + init_argv[2], + init_argv[3], + init_argv[4]); + + env = getenv("kernel"); + if (!env) + return MV_FAIL; + + sprintf(init_argv[2], "%d:1", newest_fw_dev); + sprintf(init_argv[3], "0x%08x", KERNEL_LOAD_ADDR); + sprintf(init_argv[4], "/%s", env); + + sprintf(tmpbuf, "%s %s %s %s %s; ", + init_argv[0], + init_argv[1], + init_argv[2], + init_argv[3], + init_argv[4]); + + strcat(bootcmd, tmpbuf); + + strcat(bootcmd, getenv("bootcommon")); + setenv("idebootcmd", bootcmd); + DB(printf("** idebootcmd = %s\n", getenv("idebootcmd"))); + + return MV_OK ; +} +#endif + +void print_mvBanner(void) +{ +#ifdef CONFIG_SILENT_CONSOLE + DECLARE_GLOBAL_DATA_PTR; + gd->flags |= GD_FLG_SILENT; +#endif +#if defined(CONFIG_BUFFALO_PLATFORM) +#else + printf("\n"); + printf(" __ __ _ _\n"); + printf(" | \\/ | __ _ _ ____ _____| | |\n"); + printf(" | |\\/| |/ _` | '__\\ \\ / / _ \\ | |\n"); + printf(" | | | | (_| | | \\ V / __/ | |\n"); + printf(" |_| |_|\\__,_|_| \\_/ \\___|_|_|\n"); + printf(" _ _ ____ _\n"); + printf("| | | | | __ ) ___ ___ | |_ \n"); + printf("| | | |___| _ \\ / _ \\ / _ \\| __| \n"); + printf("| |_| |___| |_) | (_) | (_) | |_ \n"); + printf(" \\___/ |____/ \\___/ \\___/ \\__| "); +#endif +#if !defined(MV_NAND_BOOT) +#if defined(MV_INCLUDE_MONT_EXT) + mvMPPConfigToSPI(); + if(!enaMonExt()) + printf(" ** LOADER **"); + else + printf(" ** MONITOR **"); + mvMPPConfigToDefault(); +#else + printf(" ** Forcing LOADER mode only **"); +#endif /* MV_INCLUDE_MONT_EXT */ +#endif + return; +} + +void print_dev_id(void){ + static char boardName[30]; + + mvBoardNameGet(boardName); + +#if defined(CONFIG_BUFFALO_PLATFORM) + #if defined(MV_CPU_BE) + printf("\n ** BUFFALO BOARD: %s BE ",boardName); + #else + printf("\n ** BUFFALO BOARD: %s LE ",boardName); + #endif + printf("\n ** Board ID: 0x%X", mvBoardIdGet()); +#else + #if defined(MV_CPU_BE) + printf("\n ** MARVELL BOARD: %s BE ",boardName); + #else + printf("\n ** MARVELL BOARD: %s LE ",boardName); + #endif +#endif + return; +} + + +void maskAllInt(void) +{ + /* mask all external interrupt sources */ + MV_REG_WRITE(CPU_MAIN_IRQ_MASK_REG, 0); + MV_REG_WRITE(CPU_MAIN_FIQ_MASK_REG, 0); + MV_REG_WRITE(CPU_ENPOINT_MASK_REG, 0); + MV_REG_WRITE(CPU_MAIN_IRQ_MASK_HIGH_REG, 0); + MV_REG_WRITE(CPU_MAIN_FIQ_MASK_HIGH_REG, 0); + MV_REG_WRITE(CPU_ENPOINT_MASK_HIGH_REG, 0); +} + +/* init for the Master*/ +void misc_init_r_dec_win(void) +{ +#if defined(MV_INCLUDE_USB) + { + char *env; + + env = getenv("usb0Mode"); + if((!env) || (strcmp(env,"device") == 0) || (strcmp(env,"Device") == 0) ) + { + printf("USB 0: device mode\n"); + mvUsbInit(0, MV_FALSE); + } + else + { + printf("USB 0: host mode\n"); + mvUsbInit(0, MV_TRUE); + } + } +#endif/* #if defined(MV_INCLUDE_USB) */ + +#if defined(MV_INCLUDE_XOR) + mvXorInit(); +#endif + mvLcdInit(); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + mv_set_power_scheme(); +#endif + + return; +} + + +/* + * Miscellaneous platform dependent initialisations + */ + +extern MV_STATUS mvEthPhyRegRead(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 *data); +extern MV_STATUS mvEthPhyRegWrite(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 data); + +/* golabal mac address for yukon EC */ +unsigned char yuk_enetaddr[6]; +extern int interrupt_init (void); +extern void i2c_init(int speed, int slaveaddr); + + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; +#if defined(MV_INCLUDE_TWSI) + MV_TWSI_ADDR slave; +#endif + unsigned int i; + + maskAllInt(); + + /* must initialize the int in order for udelay to work */ + interrupt_init(); + +#if defined(MV_INCLUDE_TWSI) + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, CFG_I2C_SPEED, CFG_TCLK, &slave, 0); +#endif + + /* Init the Board environment module (device bank params init) */ + mvBoardEnvInit(); + + /* Init the Controlloer environment module (MPP init) */ + mvCtrlEnvInit(); + + mvBoardDebugLed(3); + + /* Init the Controller CPU interface */ + mvCpuIfInit(mvCpuAddrWinMap); + + /* arch number of Integrator Board */ + gd->bd->bi_arch_number = 527; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + /* relocate the exception vectors */ + /* U-Boot is running from DRAM at this stage */ + for(i = 0; i < 0x100; i+=4) + { + *(unsigned int *)(0x0 + i) = *(unsigned int*)(TEXT_BASE + i); + } + + /* Update NOR flash base address bank for CFI driver */ +#ifdef CFG_FLASH_CFI_DRIVER + mvUpdateNorFlashBaseAddrBank(); +#endif /* CFG_FLASH_CFI_DRIVER */ + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) + /* Init the PHY or Switch of the board */ + mvBoardEgigaPhySwitchInit(); +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + + mvBoardDebugLed(4); + + return 0; +} + +void misc_init_r_env(void){ + char *env; + char tmp_buf[10]; + unsigned int malloc_len; + DECLARE_GLOBAL_DATA_PTR; + + unsigned int flashSize =0 , secSize =0, ubootSize =0; + char buff[256]; + int need_saveenv=0; + +#if defined(MV_BOOTSIZE_4M) + flashSize = _4M; +#elif defined(MV_BOOTSIZE_8M) + flashSize = _8M; +#elif defined(MV_BOOTSIZE_16M) + flashSize = _16M; +#elif defined(MV_BOOTSIZE_32M) + flashSize = _32M; +#elif defined(MV_BOOTSIZE_64M) + flashSize = _64M; +#endif + +#if defined(MV_SEC_64K) + secSize = _64K; +#if defined(MV_TINY_IMAGE) + ubootSize = _256K; +#else + ubootSize = _512K; +#endif +#elif defined(MV_SEC_128K) + secSize = _128K; +#if defined(MV_TINY_IMAGE) + ubootSize = _128K * 3; +#else + ubootSize = _128K * 5; +#endif +#elif defined(MV_SEC_256K) + secSize = _256K; +#if defined(MV_TINY_IMAGE) + ubootSize = _256K * 3; +#else + ubootSize = _256K * 3; +#endif +#endif + if ((0 == flashSize) || (0 == secSize) || (0 == ubootSize)) + { + env = getenv("console"); + if(!env) + setenv("console","console=ttyS0,115200"); + } + else +#if defined(MV_SPI_BOOT) + { + sprintf(buff,"console=ttyS0,115200 mtdparts=spi_flash:0x%x@0(uboot)ro,0x%x@0x%x(root)", + ubootSize, flashSize - 0x100000, 0x100000); + env = getenv("console"); + if(!env) + setenv("console",buff); + } +#elif defined(MV_NAND_BOOT) + { + sprintf(buff,"console=ttyS0,115200 mtdparts=nand_mtd:0x%x@0(uboot)ro,0x%x@0x%x(root)", + ubootSize, nand_info[0].size - 0x100000, 0x100000); + env = getenv("console"); + if(!env) + setenv("console",buff); + + env = getenv("nandEnvBase"); + strcpy(env, ""); + sprintf(env, "%x", nandEnvBase); + setenv("nandEnvBase", env); + } +#endif + + /* Linux open port support */ + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + setenv("mainlineLinux","yes"); + else + setenv("mainlineLinux","no"); + + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + /* arch number for open port Linux */ + env = getenv("arcNumber"); + if(!env ) + { + /* arch number according to board ID */ + int board_id = mvBoardIdGet(); + switch(board_id){ + case(DB_88F6281A_BP_ID): + sprintf(tmp_buf,"%d", DB_88F6281_BP_MLL_ID); + board_id = DB_88F6281_BP_MLL_ID; + break; + case(RD_88F6192A_ID): + sprintf(tmp_buf,"%d", RD_88F6192_MLL_ID); + board_id = RD_88F6192_MLL_ID; + break; + case(RD_88F6281A_ID): + sprintf(tmp_buf,"%d", RD_88F6281_MLL_ID); + board_id = RD_88F6281_MLL_ID; + break; + case(DB_CUSTOMER_ID): + break; + default: + sprintf(tmp_buf,"%d", board_id); + board_id = board_id; + break; + } + gd->bd->bi_arch_number = board_id; + setenv("arcNumber", tmp_buf); + } + else + { + gd->bd->bi_arch_number = simple_strtoul(env, NULL, 10); + } + } + + /* update the CASset env parameter */ + env = getenv("CASset"); + if(!env ) + { +#ifdef MV_MIN_CAL + setenv("CASset","min"); +#else + setenv("CASset","max"); +#endif + } + /* Monitor extension */ +#ifdef MV_INCLUDE_MONT_EXT + env = getenv("enaMonExt"); + if(/* !env || */ ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("enaMonExt","yes"); + else +#endif + setenv("enaMonExt","no"); +#if defined (MV_INC_BOARD_NOR_FLASH) + env = getenv("enaFlashBuf"); + if( ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("enaFlashBuf","no"); + else + setenv("enaFlashBuf","yes"); +#endif + + /* CPU streaming */ + env = getenv("enaCpuStream"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("enaCpuStream","no"); + else + setenv("enaCpuStream","yes"); + + /* Write allocation */ + env = getenv("enaWrAllo"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaWrAllo","no"); + else + setenv("enaWrAllo","yes"); + + /* Pex mode */ + env = getenv("pexMode"); + if( env && ( ((strcmp(env,"EP") == 0) || (strcmp(env,"ep") == 0) ))) + setenv("pexMode","EP"); + else + setenv("pexMode","RC"); + + env = getenv("disL2Cache"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("disL2Cache","no"); + else + setenv("disL2Cache","yes"); + + env = getenv("setL2CacheWT"); + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("setL2CacheWT","yes"); + else + setenv("setL2CacheWT","no"); + + env = getenv("disL2Prefetch"); + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + { + setenv("disL2Prefetch","yes"); + + /* ICache Prefetch */ + env = getenv("enaICPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaICPref","no"); + else + setenv("enaICPref","yes"); + + /* DCache Prefetch */ + env = getenv("enaDCPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaDCPref","no"); + else + setenv("enaDCPref","yes"); + } + else + { + setenv("disL2Prefetch","no"); + setenv("enaICPref","no"); + setenv("enaDCPref","no"); + } + + + env = getenv("sata_dma_mode"); + if( env && ((strcmp(env,"No") == 0) || (strcmp(env,"no") == 0) ) ) + setenv("sata_dma_mode","no"); + else + setenv("sata_dma_mode","yes"); + + + /* Malloc length */ + env = getenv("MALLOC_len"); + malloc_len = simple_strtoul(env, NULL, 10) << 20; + if(malloc_len == 0){ + sprintf(tmp_buf,"%d",CFG_MALLOC_LEN>>20); + setenv("MALLOC_len",tmp_buf); + } + + /* primary network interface */ +#if !defined(CONFIG_BUFFALO_PLATFORM) + env = getenv("ethprime"); + if(!env) + { + if(mvBoardIdGet() == RD_88F6281A_ID) + setenv("ethprime","egiga1"); + else + setenv("ethprime",ENV_ETH_PRIME); + } + + /* netbsd boot arguments */ + env = getenv("netbsd_en"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("netbsd_en","no"); + else + { + setenv("netbsd_en","yes"); + env = getenv("netbsd_gw"); + if(!env) + setenv("netbsd_gw","192.168.0.254"); + + env = getenv("netbsd_mask"); + if(!env) + setenv("netbsd_mask","255.255.255.0"); + + env = getenv("netbsd_fs"); + if(!env) + setenv("netbsd_fs","nfs"); + + env = getenv("netbsd_server"); + if(!env) + setenv("netbsd_server","192.168.0.1"); + + env = getenv("netbsd_ip"); + if(!env) + { + env = getenv("ipaddr"); + setenv("netbsd_ip",env); + } + + env = getenv("netbsd_rootdev"); + if(!env) + setenv("netbsd_rootdev","mgi0"); + + env = getenv("netbsd_add"); + if(!env) + setenv("netbsd_add","0x800000"); + + env = getenv("netbsd_get"); + if(!env) + setenv("netbsd_get","tftpboot $(netbsd_add) $(image_name)"); + +#if defined(MV_INC_BOARD_QD_SWITCH) + env = getenv("netbsd_netconfig"); + if(!env) + setenv("netbsd_netconfig","mv_net_config=<((mgi0,00:00:11:22:33:44,0)(mgi1,00:00:11:22:33:55,1:2:3:4)),mtu=1500>"); +#endif + env = getenv("netbsd_set_args"); + if(!env) + setenv("netbsd_set_args","setenv bootargs nfsroot=$(netbsd_server):$(rootpath) fs=$(netbsd_fs) \ +ip=$(netbsd_ip) serverip=$(netbsd_server) mask=$(netbsd_mask) gw=$(netbsd_gw) rootdev=$(netbsd_rootdev) \ +ethaddr=$(ethaddr) eth1addr=$(eth1addr) ethmtu=$(ethmtu) eth1mtu=$(eth1mtu) $(netbsd_netconfig)"); + + env = getenv("netbsd_boot"); + if(!env) + setenv("netbsd_boot","bootm $(netbsd_add) $(bootargs)"); + + env = getenv("netbsd_bootcmd"); + if(!env) + setenv("netbsd_bootcmd","run netbsd_get ; run netbsd_set_args ; run netbsd_boot"); + } + + /* vxWorks boot arguments */ + env = getenv("vxworks_en"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("vxworks_en","no"); + else + { + char* buff = 0x1100; + setenv("vxworks_en","yes"); + + sprintf(buff,"mgi(0,0) host:vxWorks.st"); + env = getenv("serverip"); + strcat(buff, " h="); + strcat(buff,env); + env = getenv("ipaddr"); + strcat(buff, " e="); + strcat(buff,env); + strcat(buff, ":ffff0000 u=anonymous pw=target "); + + setenv("vxWorks_bootargs",buff); + } +#endif // !defined(CONFIG_BUFFALO_PLATFORM) + /* linux boot arguments */ + env = getenv("bootargs_root"); + if(!env) +#if defined(CONFIG_BUFFALO_PLATFORM) + setenv("bootargs_root", "root=/dev/sda2 rw initrd=0x00800040,12M panic=5"); +#else + setenv("bootargs_root","root=/dev/nfs rw"); +#endif // (CONFIG_BUFFALO_PLATFORM) + + /* For open Linux we set boot args differently */ + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + env = getenv("bootargs_end"); + if(!env) + setenv("bootargs_end",":::orion:eth0:none"); + } + else + { + env = getenv("bootargs_end"); + if(!env) +#if defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootargs_end",CFG_BOOTARGS_END_SWITCH); +#else + setenv("bootargs_end",CFG_BOOTARGS_END); +#endif + } + + env = getenv("image_name"); + if(!env) + setenv("image_name","uImage"); + +#if defined(CONFIG_BUFFALO_PLATFORM) + extern char buffalo_version_string[]; + setenv("buffalo_ver", buffalo_version_string); + setenv("kernel", "uImage.buffalo"); + setenv("initrd", "initrd.buffalo"); + setenv("bootcommon", + "setenv bootargs $console $bootargs_root $bootargs_func $bootargs_wol $buffalo_ver $mtdparts $tftpboot $nandboot; " + "bootm 0x00100000 0x00800000"); + + setenv("tftpbootcmd", + "tftp 0x00100000 $kernel; tftp 0x00800000 $initrd; " + "setenv tftpboot tftpboot=yes; " + "run bootcommon"); + + setenv("idebootcmd", + "ext2load ide 0:1 0x00100000 /$kernel; " + "ext2load ide 0:1 0x00800000 /$initrd; " + "run bootcommon"); + +# if defined(MV_NAND) + setenv("mtdids", "nand0=nand_mtd"); + sprintf(buff,"mtdparts=nand_mtd:0x%x(boot),0x%x(rootfs),0x%x(reserve)", + 0x01000000, + nand_info[0].size - 0x01000000 - 0x00800000, + 0x00800000); + setenv("mtdparts", buff); + setenv("nandbootcmd", + "fsload 0x00100000 /$kernel; " + "fsload 0x00800000 /$initrd; " + "setenv nandboot nandboot=yes; " + "run bootcommon"); + + extern nand_info_t nand_info[]; + sprintf(buff, "ide"); + if (nand_info[0].name) + strcat(buff, " nand"); +# else + sprintf(buff, "ide"); +# endif // defined(MV_NAND) + + setenv("bootorder", buff); + setenv("bootcmd", + "for i in $bootorder; do run ${i}bootcmd; done"); + +#else // !defined(CONFIG_BUFFALO_PLATFORM) + +#if (CONFIG_BOOTDELAY >= 0) + env = getenv("bootcmd"); + if(!env) +#if defined(MV_INCLUDE_TDM) && defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootcmd","tftpboot 0x2000000 $(image_name); \ +setenv bootargs $(console) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig) $(mvPhoneConfig) $(lcd0_bootargs); bootm 0x2000000; "); +#elif defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootcmd","tftpboot 0x2000000 $(image_name); \ +setenv bootargs $(console) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig) $(lcd0_bootargs); bootm 0x2000000; "); +#elif defined(MV_INCLUDE_TDM) + setenv("bootcmd","tftpboot 0x2000000 $(image_name); \ +setenv bootargs $(console) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig) $(mvPhoneConfig) $(lcd0_bootargs); bootm 0x2000000; "); +#else + + setenv("bootcmd","tftpboot 0x2000000 $(image_name); \ +setenv bootargs $(console) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(lcd0_bootargs); bootm 0x2000000; "); +#endif +#endif /* (CONFIG_BOOTDELAY >= 0) */ + + env = getenv("standalone"); + if(!env) +#if defined(MV_INCLUDE_TDM) && defined(MV_INC_BOARD_QD_SWITCH) + setenv("standalone","fsload 0x2000000 $(image_name);setenv bootargs $(console) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig) $(mvPhoneConfig); bootm 0x2000000;"); +#elif defined(MV_INC_BOARD_QD_SWITCH) + setenv("standalone","fsload 0x2000000 $(image_name);setenv bootargs $(console) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig); bootm 0x2000000;"); +#elif defined(MV_INCLUDE_TDM) + setenv("standalone","fsload 0x2000000 $(image_name);setenv bootargs $(console) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvPhoneConfig); bootm 0x2000000;"); +#else + setenv("standalone","fsload 0x2000000 $(image_name);setenv bootargs $(console) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x2000000;"); +#endif +#endif // (CONFIG_BUFFALO_PLATFORM) + + + /* Add LCD param to Linux */ + if (mvCtrlModelGet() == MV_6282_DEV_ID) + { + env = getenv("lcd0_enable"); + if(!env) + setenv("lcd0_enable","0"); + + env = getenv("lcd0_params"); + if(!env) + setenv("lcd0_params",ENV_LCD0_PARAMS); + + env = getenv("lcd0_bootargs"); + if(!env) + setenv("lcd0_bootargs",ENV_LCD_BOOTARGS); + } + + + /* Set boodelay to 3 sec, if Monitor extension are disabled */ + if(!enaMonExt()){ + setenv("bootdelay","3"); + setenv("disaMvPnp","no"); + } + + /* Disable PNP config of Marvel memory controller devices. */ + env = getenv("disaMvPnp"); + if(!env) + setenv("disaMvPnp","no"); + +#if (defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH)) + /* Generate random ip and mac address */ + /* Read RTC to create pseudo-random data for enc */ + struct rtc_time tm; + unsigned int xi, xj, xk, xl, i; + char ethaddr_0[30]; + char ethaddr_1[30]; + + rtc_get(&tm); + xi = ((tm.tm_yday + tm.tm_sec)% 254); + /* No valid ip with one of the fileds has the value 0 */ + if (xi == 0) + xi+=2; + + xj = ((tm.tm_yday + tm.tm_min)%254); + /* No valid ip with one of the fileds has the value 0 */ + if (xj == 0) + xj+=2; + + /* Check if the ip address is the same as the server ip */ + if ((xj == 1) && (xi == 11)) + xi+=2; + + xk = (tm.tm_min * tm.tm_sec)%254; + xl = (tm.tm_hour * tm.tm_sec)%254; + + sprintf(ethaddr_0,"00:50:43:%02x:%02x:%02x",xk,xi,xj); + sprintf(ethaddr_1,"00:50:43:%02x:%02x:%02x",xl,xi,xj); + + /* MAC addresses */ + env = getenv("ethaddr"); + if(!env) { + setenv("ethaddr",ethaddr_0); + need_saveenv = 1; + } + + env = getenv("ethmtu"); + if(!env) + setenv("ethmtu","1500"); + +#if !defined(MV_INC_BOARD_QD_SWITCH) +/* ETH1ADDR not define in GWAP boards */ + if ((mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1) == MV_BOARD_RGMII) || + (mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2) == MV_BOARD_RGMII) || + (mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1) == MV_BOARD_MII)) + { + env = getenv("eth1addr"); + if(!env) + setenv("eth1addr",ethaddr_1); + + env = getenv("eth1mtu"); + if(!env) + setenv("eth1mtu","1500"); + } +#elif defined(MV_INC_BOARD_QD_SWITCH) && (defined(RD_88F6190A) || defined(RD_88F6192A)) + env = getenv("eth1addr"); + if(!env) + setenv("eth1addr",ethaddr_1); + + env = getenv("eth1mtu"); + if(!env) + setenv("eth1mtu","1500"); +#endif +#if defined(MV_INCLUDE_TDM) + /* Set mvPhoneConfig env parameter */ + env = getenv("mvPhoneConfig"); + if(!env ) + setenv("mvPhoneConfig","mv_phone_config=dev[0]:fxs,dev[1]:fxo"); +#endif + /* Set mvNetConfig env parameter */ + env = getenv("mvNetConfig"); + if(!env ) + setenv("mvNetConfig","mv_net_config=(00:11:88:0f:62:81,0:1:2:3),mtu=1500"); +#endif /* (MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) */ + +#if defined(MV_INCLUDE_USB) + /* USB Host */ + env = getenv("usb0Mode"); + if(!env) + setenv("usb0Mode",ENV_USB0_MODE); +#endif /* (MV_INCLUDE_USB) */ + +#if defined(YUK_ETHADDR) + env = getenv("yuk_ethaddr"); + if(!env) + setenv("yuk_ethaddr",YUK_ETHADDR); + + { + int i; + char *tmp = getenv ("yuk_ethaddr"); + char *end; + + for (i=0; i<6; i++) { + yuk_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + } +#endif /* defined(YUK_ETHADDR) */ + +#if defined(MV_NAND) + env = getenv("nandEcc"); + if(!env) + { + setenv("nandEcc", "1bit"); + } +#endif + +#if defined(RD_88F6281A) || defined(RD_88F6192A) || defined(RD_88F6190A) + mvHddPowerCtrl(); +#endif +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) + env = getenv("netretry"); + if (!env) + setenv("netretry","no"); + + env = getenv("rcvrip"); + if (!env) + setenv("rcvrip",RCVR_IP_ADDR); + + env = getenv("loadaddr"); + if (!env) + setenv("loadaddr",RCVR_LOAD_ADDR); + + env = getenv("autoload"); + if (!env) + setenv("autoload","no"); + + /* Check the recovery trigger */ + recoveryDetection(); +#endif + if (need_saveenv) + saveenv(); + + return; +} + +#ifdef BOARD_LATE_INIT +int board_late_init (void) +{ +#if defined(CONFIG_BUFFALO_PLATFORM) + bfEthPhyPolaritySet(); + while (!bfIsStartBootProcess()) + ; + + buffalo_all_link_led_on(); + bfGppBlinkRegBitSet(BIT_PWR_LED); + bfGppOutRegBitAssert(BIT_PWR_LED); + bfGppOutRegBitAssert(BIT_FAN_LOW); + bfGppOutRegBitAssert(BIT_FAN_HIGH); + + int i; + MV_32 pin; + + for (i=0; (pin = mvBoardGpioPinNumGet(BOARD_GPP_HDD_POWER, i)) != MV_ERROR; i++) { + printf("HDD%d Power ON\n", i); + bfGppOutRegBitAssert(pin); + udelay(5 * 1000 * 1000); + } + +#if 0 + for (i=0; (pin = mvBoardGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, i)) != MV_ERROR; i++) { + printf("USB%d Power ON\n", i); + bfGppOutRegBitAssert(pin); + udelay(5 * 1000 * 1000); + } + + /* Initialize USB */ + run_command("usb reset",0); + char *argv[] = {"fatinfo", "usb", "0"}; + extern int do_fat_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + if (do_fat_fsinfo(NULL, 0, 3, argv) == 0) + setenv("usbloadcmd", "fatload"); + else + setenv("usbloadcmd", "ext2load"); + + if (!getenv("usbbootcmd")) + setenv("usbbootcmd", + "$(usbloadcmd) usb 0:1 0x00100000 /$(kernel); " + "$(usbloadcmd) usb 0:1 0x00800000 /$(initrd); " + "setenv bootargs $(console) $(bootargs_root) $(buffalo_ver) ;" + "bootm 0x00100000 0x00800000"); +#endif + extern MV_BOOL hdd_found; + ide_init(); + if (hdd_found == MV_FALSE) { + printf("HDD is not found \n"); +#if defined(MV_NAND) + if (nand_info[0].size == 0) { + bfErrorCodeDisp(BIT_ALARM_LED, 7); + setenv("force_tftp", "1"); + } +#else + bfErrorCodeDisp(BIT_ALARM_LED, 7); + setenv("force_tftp", "1"); +#endif + } + else { + int max_drv; + + switch (mvBoardIdGet()) { + case BF_MVLSQV_ID: + max_drv = 4; + break; + case BF_MVWXL_ID: + case BF_MVWSSX_ID: + case BF_MVLSWV_ID: + max_drv = 2; + break; + case BF_MVLSXH_ID: + case BF_MVLSXL_ID: + case BF_MVLSVL_ID: + default: + max_drv = 1; + break; + } + + if (serch_boot_drv(max_drv) == MV_FAIL) { + } + } + + if(bfIsSupportWol(0) == MV_TRUE) + { + if (bfGppInRegBitTest(BIT_PWRAUTO_SW)) + { + MV_U16 wol_status = bfGetWolInterruptStatus(0, 0); + if(wol_status) + { + char sz_bootargs_wol[128]; + memset(sz_bootargs_wol, 0, sizeof(sz_bootargs_wol)); + + sprintf(sz_bootargs_wol, "wol_status=%s", bfGetWolPatternString(wol_status)); + setenv("bootargs_wol", sz_bootargs_wol); + } + } + bfControlWolInterrupt(0, FLAG_BUFFALO_WOL_INTERRUPT_DISABLE); + bfResetEthPhy(0); + } +#else + /* Check if to use the LED's for debug or to use single led for init and Linux heartbeat */ + mvBoardDebugLed(0); +#endif // CONFIG_BUFFALO_PLATFORM + return 0; +} +#endif // BOARD_LATE_INIT + +void pcie_tune(void) +{ + + MV_REG_WRITE(0xF1041AB0, 0x100); + MV_REG_WRITE(0xF1041A20, 0x78000801); + MV_REG_WRITE(0xF1041A00, 0x4014022F); + MV_REG_WRITE(0xF1040070, 0x18110008); + + return; + +} + +int misc_init_r (void) +{ + char name[128], *env; + + mvBoardDebugLed(5); + + mvCpuNameGet(name); + printf("\nCPU : %s\n", name); + + /* init special env variables */ + misc_init_r_env(); + + mv_cpu_init(); + +#if defined(MV_INCLUDE_MONT_EXT) + if(enaMonExt()){ + printf("\n Marvell monitor extension:\n"); + mon_extension_after_relloc(); + } + printf("\n"); +#endif /* MV_INCLUDE_MONT_EXT */ + + /* print detected modules */ + mvMppModuleTypePrint(); + + printf("\n"); + /* init the units decode windows */ + misc_init_r_dec_win(); + +#ifdef CONFIG_PCI +#if !defined(MV_MEM_OVER_PCI_WA) && !defined(MV_MEM_OVER_PEX_WA) + pci_init(); +#endif +#endif + + mvBoardDebugLed(6); + + mvBoardDebugLed(7); + + env = getenv("pcieTune"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"yes") == 0))) + pcie_tune(); + else + setenv("pcieTune","no"); + + return 0; +} + +MV_U32 mvTclkGet(void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* get it only on first time */ + if(gd->tclk == 0) + gd->tclk = mvBoardTclkGet(); + + return gd->tclk; +} + +MV_U32 mvSysClkGet(void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* get it only on first time */ + if(gd->bus_clk == 0) + gd->bus_clk = mvBoardSysClkGet(); + + return gd->bus_clk; +} + +#ifndef MV_TINY_IMAGE +/* exported for EEMBC */ +MV_U32 mvGetRtcSec(void) +{ + MV_RTC_TIME time; +#ifdef MV_INCLUDE_RTC + mvRtcTimeGet(&time); +#elif CONFIG_RTC_DS1338_DS1339 + mvRtcDS133xTimeGet(&time); +#endif + return (time.minutes * 60) + time.seconds; +} +#endif + +void reset_cpu(void) +{ + mvBoardReset(); +} + +void mv_cpu_init(void) +{ + char *env; + volatile unsigned int temp; + + /*CPU streaming & write allocate */ + env = getenv("enaWrAllo"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0" : "=r" (temp)); + temp |= BIT28; + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 0" :: "r" (temp)); + + } + else + { + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0" : "=r" (temp)); + temp &= ~BIT28; + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 0" :: "r" (temp)); + } + + env = getenv("enaCpuStream"); + if(!env || (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) + { + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0" : "=r" (temp)); + temp &= ~BIT29; + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 0" :: "r" (temp)); + } + else + { + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0" : "=r" (temp)); + temp |= BIT29; + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 0" :: "r" (temp)); + } + + /* Verifay write allocate and streaming */ + printf("\n"); + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0" : "=r" (temp)); + if (temp & BIT29) + printf("Streaming enabled \n"); + else + printf("Streaming disabled \n"); + if (temp & BIT28) + printf("Write allocate enabled\n"); + else + printf("Write allocate disabled\n"); + + /* DCache Pref */ + env = getenv("enaDCPref"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + MV_REG_BIT_SET( CPU_CONFIG_REG , CCR_DCACH_PREF_BUF_ENABLE); + } + + if(env && ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + { + MV_REG_BIT_RESET( CPU_CONFIG_REG , CCR_DCACH_PREF_BUF_ENABLE); + } + + /* ICache Pref */ + env = getenv("enaICPref"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + MV_REG_BIT_SET( CPU_CONFIG_REG , CCR_ICACH_PREF_BUF_ENABLE); + } + + if(env && ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + { + MV_REG_BIT_RESET( CPU_CONFIG_REG , CCR_ICACH_PREF_BUF_ENABLE); + } + + /* Set L2C WT mode - Set bit 4 */ + temp = MV_REG_READ(CPU_L2_CONFIG_REG); + env = getenv("setL2CacheWT"); + if(!env || ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + { + temp |= BIT4; + } + else + temp &= ~BIT4; + MV_REG_WRITE(CPU_L2_CONFIG_REG, temp); + + + /* L2Cache settings */ + asm ("mrc p15, 1, %0, c15, c1, 0":"=r" (temp)); + + /* Disable L2C pre fetch - Set bit 24 */ + env = getenv("disL2Prefetch"); + if(env && ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + temp &= ~BIT24; + else + temp |= BIT24; + + /* enable L2C - Set bit 22 */ + env = getenv("disL2Cache"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + temp |= BIT22; + else + temp &= ~BIT22; + + asm ("mcr p15, 1, %0, c15, c1, 0": :"r" (temp)); + + + /* Enable i cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (temp)); + temp |= BIT12; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (temp)); + + /* Change reset vector to address 0x0 */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (temp)); + temp &= ~BIT13; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (temp)); +} +/******************************************************************************* +* mvBoardMppModuleTypePrint - print module detect +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvMppModuleTypePrint(MV_VOID) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U32 maxMppGrp = 1; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6282_DEV_ID: + maxMppGrp = MV_6282_MPP_MAX_MODULE; + break; + case MV_6280_DEV_ID: + maxMppGrp = MV_6280_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + mppGroupType = mvBoardMppGroupTypeGet(devClass); + + /* 6282 doesn't support LCD module when booting from NAND */ + if ((mppGroupType == MV_BOARD_LCD) && (mvCtrlIsBootFromNAND())) + { + printf("Error!, MV88F6282 doesn't support LCD module when booting from NAND!\n"); + break; + } + + switch(mppGroupType) + { + case MV_BOARD_TDM: + if(devId != MV_6190_DEV_ID) + printf("Module %d is TDM\n", devClass); + break; + case MV_BOARD_AUDIO: + if(devId != MV_6190_DEV_ID) + printf("Module %d is AUDIO\n", devClass); + break; + case MV_BOARD_RGMII: + if(devId != MV_6190_DEV_ID) + printf("Module %d is RGMII\n", devClass); + break; + case MV_BOARD_GMII: + if(devId != MV_6190_DEV_ID) + printf("Module %d is GMII\n", devClass); + break; + case MV_BOARD_TS: + if(devId != MV_6190_DEV_ID) + printf("Module %d is TS\n", devClass); + break; + case MV_BOARD_MII: + if(devId != MV_6190_DEV_ID) + printf("Module %d is MII\n", devClass); + break; + case MV_BOARD_LCD: + if(devId != MV_6190_DEV_ID) + printf("Module %d is LCD\n", devClass); + break; + + default: + break; + } + } +} + +/* Set unit in power off mode acording to the detection of MPP */ +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +int mv_set_power_scheme(void) +{ + int mppGroupType1 = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); + int mppGroupType2 = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); + MV_U32 devId = mvCtrlModelGet(); + MV_U32 boardId = mvBoardIdGet(); + + if (boardId == RD_88F6192A_ID) + { + /* Sdio power down */ + mvCtrlPwrMemSet(SDIO_UNIT_ID, 0, MV_FALSE); + mvCtrlPwrClckSet(SDIO_UNIT_ID, 0, MV_FALSE); + } + + if (devId == MV_6180_DEV_ID || boardId == RD_88F6281A_PCAC_ID || devId == MV_6280_DEV_ID || boardId == SHEEVA_PLUG_ID) + { + /* Sata power down */ + mvCtrlPwrMemSet(SATA_UNIT_ID, 1, MV_FALSE); + mvCtrlPwrMemSet(SATA_UNIT_ID, 0, MV_FALSE); + mvCtrlPwrClckSet(SATA_UNIT_ID, 1, MV_FALSE); + mvCtrlPwrClckSet(SATA_UNIT_ID, 0, MV_FALSE); + /* Sdio power down */ + mvCtrlPwrMemSet(SDIO_UNIT_ID, 0, MV_FALSE); + mvCtrlPwrClckSet(SDIO_UNIT_ID, 0, MV_FALSE); + } + + if (boardId == RD_88F6281A_ID || boardId == SHEEVA_PLUG_ID || devId == MV_6280_DEV_ID) + { + DB(printf("Warning: TS is Powered Off\n")); + mvCtrlPwrClckSet(TS_UNIT_ID, 0, MV_FALSE); + } + + if (devId == MV_6280_DEV_ID) + { + DB(printf("Warning: PCI-E is Powered Off\n")); + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); + } + + /* Close egiga 1 */ + if ((mppGroupType1 != MV_BOARD_GMII) && (mppGroupType1 != MV_BOARD_RGMII) && (mppGroupType2 != MV_BOARD_RGMII) + && (mppGroupType1 != MV_BOARD_MII)) + { + DB(printf("Warning: Giga1 is Powered Off\n")); + mvCtrlPwrMemSet(ETH_GIG_UNIT_ID, 1, MV_FALSE); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 1, MV_FALSE); + } + + /* Close TDM */ + if ((mppGroupType1 != MV_BOARD_TDM) && (mppGroupType2 != MV_BOARD_TDM)) + { + DB(printf("Warning: TDM is Powered Off\n")); + mvCtrlPwrClckSet(TDM_UNIT_ID, 0, MV_FALSE); + } + + /* Close AUDIO */ + if ((mppGroupType1 != MV_BOARD_AUDIO) && (mppGroupType2 != MV_BOARD_AUDIO) && boardId != RD_88F6281A_ID) + { + DB(printf("Warning: AUDIO is Powered Off\n")); + mvCtrlPwrMemSet(AUDIO_UNIT_ID, 0, MV_FALSE); + mvCtrlPwrClckSet(AUDIO_UNIT_ID, 0, MV_FALSE); + } + + /* Close TS */ + if ((mppGroupType1 != MV_BOARD_TS) && (mppGroupType2 != MV_BOARD_TS)) + { + DB(printf("Warning: TS is Powered Off\n")); + mvCtrlPwrClckSet(TS_UNIT_ID, 0, MV_FALSE); + } + + return MV_OK; +} + +#endif /* defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + +/******************************************************************************* +* mvUpdateNorFlashBaseAddrBank - +* +* DESCRIPTION: +* This function update the CFI driver base address bank with on board NOR +* devices base address. +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* None +* +*******************************************************************************/ +#ifdef CFG_FLASH_CFI_DRIVER +MV_VOID mvUpdateNorFlashBaseAddrBank(MV_VOID) +{ + + MV_U32 devBaseAddr; + MV_U32 devNum = 0; + int i; + + /* Update NOR flash base address bank for CFI flash init driver */ + for (i = 0 ; i < CFG_MAX_FLASH_BANKS_DETECT; i++) + { + devBaseAddr = mvBoardGetDeviceBaseAddr(i,BOARD_DEV_NOR_FLASH); + if (devBaseAddr != 0xFFFFFFFF) + { + flash_add_base_addr (devNum, devBaseAddr); + devNum++; + } + } + mv_board_num_flash_banks = devNum; + + /* Update SPI flash count for CFI flash init driver */ + /* Assumption only 1 SPI flash on board */ + for (i = 0 ; i < CFG_MAX_FLASH_BANKS_DETECT; i++) + { + devBaseAddr = mvBoardGetDeviceBaseAddr(i,BOARD_DEV_SPI_FLASH); + if (devBaseAddr != 0xFFFFFFFF) + mv_board_num_flash_banks += 1; + } +} +#endif /* CFG_FLASH_CFI_DRIVER */ + + +/******************************************************************************* +* mvHddPowerCtrl - +* +* DESCRIPTION: +* This function set HDD power on/off acording to env or wait for button push +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +static void mvHddPowerCtrl(void) +{ + + MV_32 hddPowerBit; + MV_32 fanPowerBit; + MV_32 hddHigh = 0; + MV_32 fanHigh = 0; + char* env; + + if(RD_88F6281A_ID == mvBoardIdGet()) + { + hddPowerBit = mvBoarGpioPinNumGet(BOARD_GPP_HDD_POWER, 0); + fanPowerBit = mvBoarGpioPinNumGet(BOARD_GPP_FAN_POWER, 0); + if (hddPowerBit > 31) + { + hddPowerBit = hddPowerBit % 32; + hddHigh = 1; + } + + if (fanPowerBit > 31) + { + fanPowerBit = fanPowerBit % 32; + fanHigh = 1; + } + } + + if ((RD_88F6281A_ID == mvBoardIdGet()) || (RD_88F6192A_ID == mvBoardIdGet()) || + (RD_88F6190A_ID == mvBoardIdGet())) + { + env = getenv("hddPowerCtrl"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("hddPowerCtrl","no"); + else + setenv("hddPowerCtrl","yes"); + + if(RD_88F6281A_ID == mvBoardIdGet()) + { + mvBoardFanPowerControl(MV_TRUE); + mvBoardHDDPowerControl(MV_TRUE); + } + else + { + /* FAN power on */ + MV_REG_BIT_SET(GPP_DATA_OUT_REG(fanHigh),(1< 31) + { + stateButtonBit = stateButtonBit % 32; + buttonHigh = 1; + } + + /* Set state input indication pin as input */ + MV_REG_BIT_SET(GPP_DATA_OUT_EN_REG(buttonHigh),(1<= 0) + { + if(usb_stor_scan(1) >= 0) + { + netflag = 0; + usbload[0] = "usbload"; + usbload[1] = "usb"; + usbload[2] = "0:1"; + usbload[3] = getenv("loadaddr"); + if ((strcmp(multi,"yes") == 0)) + usbload[4] = "/multiware.img"; + else + usbload[4] = "/flashware.img"; + + printf("Trying to load image from USB flash drive using FAT FS\n"); + if(do_fat_fsload(0, 0, 5, usbload) == 1) + { + printf("Trying to load image from USB flash drive using ext2 FS partition 0\n"); + usbload[2] = "0:0"; + if(do_ext2load(0, 0, 5, usbload) == 1) + { + printf("Trying to load image from USB flash drive using ext2 FS partition 1\n"); + usbload[2] = "0:1"; + if(do_ext2load(0, 0, 5, usbload) == 1) + { + printf("Couldn't load recovery image from USB flash drive, Trying network interface\n"); + netflag = 1; + } + else + { + env = getenv("filesize"); + usbload[3] = getenv("loadaddr"); + imagSize = simple_strtoul(env, NULL, 16); /* get the filesize env var */ + + /* Trying to check if we forced to upgrade by placing upgrade.me */ + usbload[4] = "/upgrade.me"; + sprintf(usbload[3], "0x%x", simple_strtoul(getenv("loadaddr"), NULL, 16) + imagSize + 1); + upgrade=do_ext2load(0, 0, 5, usbload); + } + } + else + { + env = getenv("filesize"); + imagSize = simple_strtoul(env, NULL, 16); /* get the filesize env var */ + + /* Trying to check if we forced to upgrade by placing upgrade.me */ + usbload[4] = "/upgrade.me"; + sprintf(usbload[3], "0x%x", simple_strtoul(getenv("loadaddr"), NULL, 16) + imagSize + 1); + upgrade=do_ext2load(0, 0, 5, usbload); + } + } + else + { + env = getenv("filesize"); + imagSize = simple_strtoul(env, NULL, 16); /* get the filesize env var */ + + /* Trying to check if we forced to upgrade by placing upgrade.me */ + usbload[4] = "/upgrade.me"; + usbload[3] = "0x000000000"; + env=getenv("loadaddr"); + imagAddr=simple_strtoul(env, NULL, 16); + sprintf(usbload[3], "0x%x", imagAddr + imagSize + 1); + printf("dummyaddr:%s\n", usbload[3]); + upgrade=do_fat_fsload(0, 0, 5, usbload); + } + // Decide on upgrade/init mode + multi = getenv("image_multi"); + printf("Multi:%s, Upgrade:%d\n", multi, upgrade); + if ( (upgrade == 0) && (strcmp(multi,"yes") == 0) ) + sprintf(ip, "usb_upgrade"); + else + sprintf(ip, "usb"); + } + } +#endif + + if(netflag == 1) + { + /* Perform the DHCP */ + printf("Aquiring an IP address using DHCP after settling network...\n"); + mvOsDelay(netwait); + + while (netwait) + { + if (NetLoop(DHCP) == -1) + { + if (!netwait) + { + ulong tmpip; + printf("Failed to retreive an IP address, switching to static IP address (%s)!\n", getenv("rcvrip")); + tmpip = getenv_IPaddr ("rcvrip"); + NetCopyIP(&NetOurIP, &tmpip); + sprintf(ip, "static"); + } + else + { + mvOsDelay(1000); + netwait-=1000; + } + } + else + { + printf("DHCP should be ready for Recovery.\n"); + break; + } + } + + /* Perform the recovery */ + printf("Starting the Recovery process to retreive the image file...\n"); + if ((imagSize = NetLoop(RCVR)) == -1) + { + printf("Failed\n"); + return; + } + } + + /* Boot the downloaded image */ + env = getenv("loadaddr"); + if (!env) { + printf("Missing loadaddr environment variable assuming default (0x200000)!\n"); + setenv("loadaddr","0x200000"); + saveenv(); + } + else + imagAddr = simple_strtoul(env, NULL, 16); /* get the loadaddr env var */ + + /* This assignment to cmd should execute prior to the RD setenv and saveenv below*/ + printf("Update bootcmd\n"); + env = getenv("ethaddr"); + env1 = getenv("eth1addr"); + + multi = getenv("image_multi"); + if ((strcmp(multi,"yes") == 0)) + { + sprintf(cmd,"setenv bootargs $(console) root=/dev/ram0 $(mvNetConfig) recovery=%s serverip=%d.%d.%d.%d ethact=$(ethact) ethaddr=%s eth1addr=%s; bootm $(loadaddr);", ip, (NetServerIP & 0xFF), ((NetServerIP >> 8) & 0xFF), ((NetServerIP >> 16) & 0xFF), ((NetServerIP >> 24) & 0xFF),env, env1); + printf("\nbootcmd(recovery-image-multi): %s\n", cmd); + } + else + { + sprintf(cmd,"setenv bootargs $(console) root=/dev/ram0 $(mvNetConfig) rootfstype=squashfs initrd=0x%x,0x%x ramdisk_size=%d recovery=%s serverip=%d.%d.%d.%d ethact=$(ethact) ethaddr=%s eth1addr=%s; bootm $(loadaddr);", imagAddr + 0x200000, (imagSize - 0x300000), (imagSize - 0x300000)/1024, ip, (NetServerIP & 0xFF), ((NetServerIP >> 8) & 0xFF), ((NetServerIP >> 16) & 0xFF), ((NetServerIP >> 24) & 0xFF),env, env1); + printf("\nbootcmd(recovery-image-normal): %s\n", cmd); + } + + if(RD_88F6192A_ID == mvBoardIdGet()) + { + setenv("console","console=ttyS0,115200 mtdparts=spi_flash:0x100000@0x0(uboot)ro,0x200000@0x100000(uimage),0xb80000@0x300000(rootfs),0x180000@0xe80000(varfs),0xf00000@0x100000(flash) varfs=/dev/mtdblock3"); + setenv("bootcmd","setenv bootargs $(console) rootfstype=squashfs root=/dev/mtdblock2; bootm 0xf8100000;"); + saveenv(); + } + else + { + if ((strcmp(multi,"yes") == 0)) + { + setenv("bootcmd","setenv bootargs $(console) ubi.mtd=2 root=ubi0:rootfsU rootfstype=ubifs $(mvNetConfig) $(mvPhoneConfig) $(lcd0_bootargs); nand read.e $(loadaddr) 0x100000 0x300000; bootm $(loadaddr);"); + setenv("console","console=ttyS0,115200"); + saveenv(); + } + else + { + setenv("bootcmd","setenv bootargs $(console) rootfstype=squashfs root=/dev/mtdblock2 $(mvNetConfig) $(mvPhoneConfig) $(lcd0_bootargs); nand read.e $(loadaddr) 0x100000 0x200000; bootm $(loadaddr);"); + setenv("console","console=ttyS0,115200"); + saveenv(); + } + } + + printf("\nbootcmd(saved)): %s\n", getenv("bootcmd")); + printf("\nconsole(saved)): %s\n", getenv("console")); + setenv("bootcmd", cmd); + + printf("Booting the image (@ 0x%x)...\n", imagAddr); + + sprintf(cmd, "boot"); + sprintf(img, "0x%x", imagAddr); + argv[0] = cmd; + argv[1] = img; + + do_bootd(NULL, 0, 2, argv); +} + +void recoveryCheck(void) +{ + /* Start the recovery process if indicated by user */ + if (rcvrflag) + recoveryHandle(); +} +#endif + +#ifdef MV_INC_BOARD_SPI_FLASH +#include +#include "sflash/mvSFlash.h" + +void memcpyFlash(env_t *env_ptr, void* buffer, MV_U32 size) +{ + MV_SFLASH_INFO *pFlash; + pFlash = getMvFlashInfo(BOOT_FLASH_INDEX); + + mvSFlashBlockRd(pFlash,(MV_U32 *)env_ptr - mvFlashBaseAddrGet(pFlash), + (MV_U8 *)buffer, size); +} +#endif + +#if defined(CONFIG_BUFFALO_PLATFORM) +MV_VOID bfEthPhyPolaritySet(void) +{ + switch (mvBoardIdGet()) { + case BF_MVLSXH_ID: + case BF_MVLSXL_ID: + break; + case BF_MVWXL_ID: + case BF_MVWSSX_ID: + case BF_MVLSVL_ID: + case BF_MVLSWV_ID: + case BF_MVLSQV_ID: + mvEthE111xPhyBasicInitLedPolarityChange(0); + mvEthE111xPhyBasicInitLedPolarityChange(1); + break; + default: + break; + } +} + +MV_BOOL bfIsStartBootProcess(void) +{ + if (mvBoardIdGet() == BF_MVLSXL_GE_V2_ID) { + return MV_TRUE; + } + + MV_U32 magic = bfGetMagicKey(); + printf("MacicKey = 0x%02x\n", magic); + + if (buffalo_IsStopAtUbootStatus()) { + if (magic == MagicKeyUpsShutdownReachedHalt) { + bfSetMagicKey(MagicKeyUpsShutdown); + printf("Magic key condition is ups shutdown.\n" + "Indicate ups error and wait re power active.\n"); + bfErrorCodeDisp(BIT_ALARM_LED, 10); + } + else { + bfSetMagicKey(MagicKeySwPoffUbootPassed); + } + } + + buffalo_all_link_led_on(); + + if (bfGppInRegBitTest(BIT_FUNC_SW)) { + printf("Switched to func-boot mode.\n"); + printf("Now waiting for func switch release.\n"); + + bfGppBlinkRegBitSet(BIT_FUNC_LED); + while (bfGppInRegBitTest(BIT_FUNC_SW)) + udelay(1000); + + printf("The Func switch was released.\n"); + printf("Now waiting for the Func switch pushed or timeout.\n"); + + int i; + int sw_off_cnt = 0; + for (i = 0; i < 60 * 1000; i++) { + if (mvBoardIdGet() == BF_MVLSQV_ID) { + if (bfGppInRegBitTest(BIT_FUNC_SW)) { + setenv("bootargs_func", "func=1"); + return MV_TRUE; + } + if (bfGppInRegBitTest(BIT_PWR_SW)) { + sw_off_cnt++; + } + else { + sw_off_cnt = 0; + } + } + else { + if (bfIsPWR_or_PWRAUTO_SignalAsserted() && + bfGppInRegBitTest(BIT_FUNC_SW)) { + setenv("bootargs_func", "func=1"); + return MV_TRUE; + } + + if (!bfIsPWR_or_PWRAUTO_SignalAsserted()) { + sw_off_cnt++; + } + else { + sw_off_cnt = 0; + } + } + + if (sw_off_cnt > 50) { // 50ms + printf("The power switch was moved to OFF position.\n"); + do_reset(NULL, 0, 0, NULL); + return MV_FALSE; + } + + udelay(1000); + } + // time out. + } + + return MV_TRUE; +} + +void bfAllLedOff(void) +{ + bfGppOutRegBitNagate(BIT_PWR_LED); + bfGppBlinkRegBitClr(BIT_PWR_LED); + bfGppOutRegBitNagate(BIT_INFO_LED); + bfGppBlinkRegBitClr(BIT_INFO_LED); + bfGppOutRegBitNagate(BIT_ALARM_LED); + bfGppBlinkRegBitClr(BIT_ALARM_LED); + bfGppOutRegBitNagate(BIT_FUNC_LED); + bfGppBlinkRegBitClr(BIT_FUNC_LED); + bfGppOutRegBitNagate(BIT_FUNC_RED_LED); + bfGppBlinkRegBitClr(BIT_FUNC_RED_LED); + bfGppOutRegBitNagate(BIT_HDD_ERROR0); + bfGppBlinkRegBitClr(BIT_HDD_ERROR0); + bfGppOutRegBitNagate(BIT_HDD_ERROR1); + bfGppBlinkRegBitClr(BIT_HDD_ERROR1); +} + +void bfErrorCodeDisp(MV_32 gppbit, int code) +{ + int i; + int ones_place; + int tens_place; + + if (mvBoardIdGet() == BF_MVLSXL_GE_V2_ID) + return; + + bfAllLedOff(); + + if (code < 0 || gppbit < 0) + return; + + ones_place = code % 10; + tens_place = code / 10; + + for (;;) { + bfGppOutRegBitNagate(gppbit); + udelay(2 * 1000 * 1000); + for (i = tens_place; i != 0; i--) { + bfGppOutRegBitAssert(gppbit); + udelay(1000 * 1000); + bfGppOutRegBitNagate(gppbit); + udelay(300 * 1000); + // switch handle + if (!bfIsPWR_or_PWRAUTO_SignalAsserted()) + do_reset(NULL, 0, 0, NULL); + + if (bfGppInRegBitTest(BIT_FUNC_SW)) + goto disp_end; + } + + for (i = ones_place; i != 0; i--) { + bfGppOutRegBitAssert(gppbit); + udelay(200 * 1000); + bfGppOutRegBitNagate(gppbit); + udelay(300 * 1000); + // switch handle + if (!bfIsPWR_or_PWRAUTO_SignalAsserted()) + do_reset(NULL, 0, 0, NULL); + + if (bfGppInRegBitTest(BIT_FUNC_SW)) + goto disp_end; + } + } + + disp_end: + bfGppOutRegBitNagate(gppbit); + bfGppOutRegBitAssert(BIT_PWR_LED); + bfGppBlinkRegBitSet(BIT_PWR_LED); +} + +void bfDispAllInitrdError(void) +{ + bfErrorCodeDisp(BIT_ALARM_LED, 6); +} + +#endif diff --git a/board/mv_feroceon/mv_kw/mv_service.c b/board/mv_feroceon/mv_kw/mv_service.c new file mode 100644 index 0000000..611dc83 --- /dev/null +++ b/board/mv_feroceon/mv_kw/mv_service.c @@ -0,0 +1,107 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvBoardEnvSpec.h" +#include "mvBoardEnvLib.h" + +/*********************************************************** +* Init the PHY or Switch of the board * + ***********************************************************/ +void mvBoardEgigaPhySwitchInit(void) +{ + if ((DB_88F6281A_BP_ID == mvBoardIdGet()) || + (DB_88F6282A_BP_ID == mvBoardIdGet()) || + (DB_88F6192A_BP_ID == mvBoardIdGet())) + { + if ( !(mvBoardIsPortInGmii())) + { + mvEthE1116PhyBasicInit(0); + mvEthE1116PhyBasicInit(1); + } + } + else if ((DB_88F6190A_BP_ID == mvBoardIdGet()) || + (DB_88F6180A_BP_ID == mvBoardIdGet()) || + (DB_88F6280A_BP_ID == mvBoardIdGet()) || + (RD_88F6192A_ID == mvBoardIdGet()) || + (RD_88F6190A_ID == mvBoardIdGet()) || + (RD_88F6281A_PCAC_ID == mvBoardIdGet()) || + (SHEEVA_PLUG_ID == mvBoardIdGet())) + { + mvEthE1116PhyBasicInit(0); + } + else if (RD_88F6281A_ID == mvBoardIdGet()) + { + mvEthE6161SwitchBasicInit(0); + mvEthE1116PhyBasicInit(1); + } + else if (DB_CUSTOMER_ID == mvBoardIdGet()) + { + } + else if (BF_MVLSXL_GE_V2_ID == mvBoardIdGet()) + { + mvEthE1116PhyBasicInit(0); + } +} + +#include "mv_service.h" diff --git a/board/mv_feroceon/mv_kw/mv_service.h b/board/mv_feroceon/mv_kw/mv_service.h new file mode 100644 index 0000000..fc56c2b --- /dev/null +++ b/board/mv_feroceon/mv_kw/mv_service.h @@ -0,0 +1,74 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "eth-phy/mvEthPhy.h" + +void mvBoardEgigaPhySwitchInit(MV_VOID); + +void mvEthSwitchRegWrite(MV_U32 ethPortNum, MV_U32 phyAddr, + MV_U32 regOffs, MV_U16 data); + +void mvEthSwitchRegRead(MV_U32 ethPortNum, MV_U32 phyAddr, + MV_U32 regOffs, MV_U16 *data); diff --git a/board/mv_feroceon/mv_kw/nBootstrap.S b/board/mv_feroceon/mv_kw/nBootstrap.S new file mode 100644 index 0000000..dceab4c --- /dev/null +++ b/board/mv_feroceon/mv_kw/nBootstrap.S @@ -0,0 +1,20 @@ +#define MV_ASMLANGUAGE +#include "nBootstrap.h" + + +.globl nbootStart +nbootStart: + /* Enable I-Cache */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Set up the stack */ + ldr r0, =BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + + /* jump to new code */ + + ldr lr, =nand_boot + mov pc, lr diff --git a/board/mv_feroceon/mv_kw/nBootstrap.h b/board/mv_feroceon/mv_kw/nBootstrap.h new file mode 100644 index 0000000..3b42c0c --- /dev/null +++ b/board/mv_feroceon/mv_kw/nBootstrap.h @@ -0,0 +1,213 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCnBootstraph +#define __INCnBootstraph + +/* includes */ + +/* defines */ +#define _DDR2 + +#define SDRAM_CONFIG_REG_DV 0x03154400 /* 1400 */ +#define SDRAM_DUNIT_CTRL_REG_DV 0x04041040 /* 1404 */ +#define SDRAM_TIMING_CTRL_LOW_REG_DVAL 0x11712220 /* 1408 */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DVAL 0x00000104 /* 140C */ +#define SDRAM_ADDR_CTRL_REG_DV 0x00000020 /* 1410 */ +#define SDRAM_OPEN_PAGE_CTRL_REG_DV 0x00000000 /* 1414 */ +#define SDRAM_MODE_REG_DV 0x00000432 /* 141C */ +#define SDRAM_EXTENDED_MODE_REG_DV 0x00000440 /* 1420 */ +#define SDRAM_FTDLL_CONFIG_REG_DV 0x00f95000 /* 1484 */ +#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x84210000 /* 1494 */ +#define DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV 0x00000000 /* 1498 */ +#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x0000780f /* 149C */ +#define SDRAM_SIZE_REG_DV 0x07ff0001 /* 128MB */ + +/* NAND Flash access */ +#define NAND_CMD_PORT (0x1 << (NFLASH_DEV_WIDTH >> 4)) +#define NAND_ADDR_PORT (0x2 << (NFLASH_DEV_WIDTH >> 4)) + +/* NAND Flash Chip Capability */ +#ifdef MV_LARGE_PAGE +#define NUM_BLOCKS 2048 +#define PAGES_PER_BLOCK 64 +#define PAGE_SIZE 2048 /* Bytes */ +#define SPARE_SIZE 64 +#define CFG_NAND_PAGE_SIZE (2048) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (64) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (0) /* Location of bad block marker */ + +#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ + +#else /* ! LARGE PAGE NAND */ +/* NAND Flash Chip Capability */ +#define NUM_BLOCKS 2048 +#define PAGES_PER_BLOCK 32 +#define PAGE_SIZE 512 /* Bytes */ +#define SPARE_SIZE 16 +#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */ + +#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ + +#endif + +/* NAND Flash Command. This appears to be generic across all NAND flash chips */ +#define CMD_READ 0x00 /* Read */ +#define CMD_READ1 0x01 /* Read1 */ +#define CMD_READ2 0x50 /* Read2 */ +#define CMD_START_READ 0x30 /* Read command after write addr */ +#define CMD_READID 0x90 /* ReadID */ +#define CMD_READID2 0x91 /* Read extended ID */ +#define CMD_WRITE 0x80 /* Write phase 1 */ +#define CMD_WRITE2 0x10 /* Write phase 2 */ +#define CMD_ERASE 0x60 /* Erase phase 1 */ +#define CMD_ERASE2 0xd0 /* Erase phase 2 */ +#define CMD_STATUS 0x70 /* Status read */ +#define CMD_RESET 0xff /* Reset */ + +/* Status bit pattern */ +#define STATUS_READY 0x40 /* Ready */ +#define STATUS_ERROR 0x01 /* Error */ + + +#define NFLASH_DEV_WIDTH 8 +#ifdef MV_LARGE_PAGE +#define BOOTER_PAGE_NUM 2 +#define BOOTER_BASE 0x00020000 + PAGE_SIZE +#else +#define BOOTER_PAGE_NUM 5 +#define BOOTER_BASE 0x00020000 + (3 * PAGE_SIZE) +#endif /* MV_LARGE_PAGE */ +#define BOOTER_END (BOOTER_BASE + (BOOTER_PAGE_NUM * PAGE_SIZE)) + +#undef INTER_REGS_BASE +#define INTER_REGS_BASE 0xd0000000 + + +#if defined(MV_BOOTROM) +#if defined(MV_88F6082) +#define NAND_FLASH_BASE 0xD8000000 +#endif +#if defined(MV_88F5182) +#define NAND_FLASH_BASE 0xf0000000 +#endif +#else +#define NAND_FLASH_BASE 0xffff0000 +#endif /* defined(MV_BOOTROM) */ + +#if 0 +#define NBOOT_UART_CHAN 0 +#define NBOOT_BAUDRATE 115200 +#define NBOOT_TIMER_NUM 0 + + +/* CPU config register (0x20100) bit[15:8] value for CPU to DDR clock ratio */ +#define CPU_2_MBUSL_DDR_CLK 0x0000 /* clock ratio 1x2 */ +/* #define CPU_2_MBUSL_DDR_CLK 0x2100 *//* clock ratio 1x3 */ +/* #define CPU_2_MBUSL_DDR_CLK 0x2200 *//* clock ratio 1x4 */ + +/* Load General Purpose Register (GPR) with 32-bit constant value */ +#define GPR_LOAD(reg, val) \ + mov reg, $(val & 0xFF) ;\ + orr reg, reg, $(val & 0xFF00) ;\ + orr reg, reg, $(val & 0xFF0000) ;\ + orr reg, reg, $(val & 0xFF000000) + +/* Register Read/Write */ +#define MV_REG_READ_ASM(toReg, baseReg, regOffs) \ + ldr toReg, [baseReg, $(regOffs & 0xFFF)] + +#define MV_REG_WRITE_ASM(fromReg, baseReg, regOffs) \ + str fromReg, [baseReg, $(regOffs & 0xFFF)] + + +/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ +#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ + (((X)&0xff00)<<8) | \ + (((X)&0xff0000)>>8) | \ + (((X)&0xff000000)>>24)) +/* Endianess macros. */ +#if defined(MV_CPU_LE) + #define MV_32BIT_LE(X) (X) + #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) +#elif defined(MV_CPU_BE) + #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) + #define MV_32BIT_BE(X) (X) +#else + #error "CPU endianess isn't defined!\n" +#endif +#endif + +#endif /* __INCnBootstraph */ diff --git a/board/mv_feroceon/mv_kw/platform.S b/board/mv_feroceon/mv_kw/platform.S new file mode 100644 index 0000000..e04274b --- /dev/null +++ b/board/mv_feroceon/mv_kw/platform.S @@ -0,0 +1,99 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include +#include +#include "mvBoardEnvSpec.h" +#include "mvCtrlEnvSpec.h" +#include "mvCpuIfRegs.h" +#include "ddr2/mvDramIfRegs.h" +#include "mvCtrlEnvAsm.h" +#if defined(MV_INC_BOARD_SPI_FLASH) +#include "spi/mvSpiSpec.h" +#endif + + +/* + get_board_id - get board id from twsi eeprom + input : r5 - board id data start offset in the eeprom + +*/ +.globl lowlevel_init + +/************************************************/ +/* lowlevel_init * +/************************************************/ + +lowlevel_init: + + /* change reg base to 0xf1000000 */ + ldr r4, =CFG_MV_REGS + MV_DV_REG_WRITE_ASM(r4, r1, 0x20080) + + /* save Link Registers */ + mov r2, lr + + /* Change L2 cache to exist */ + MV_REG_READ_ASM(r4, r1, 0x20128) + orr r4, r4, #0x18 + MV_REG_WRITE_ASM(r4, r1, 0x20128) + /* Read operation to make sure the L2 bit is set */ + MV_REG_READ_ASM(r4, r1, 0x20128) + + /* invalidate L2 cache */ + mov r0, #0 + mcr p15, 1, r0, c15, c11, 0 + + bl _i2cInit + + /* Initialize BUS-L to DDR configuration parameters */ + /* Must be done prior to DDR operation */ +#if !defined(MV_BOOTROM) + bl _mvCpuIfPreInit +#endif + +#if defined(MV_INC_BOARD_SPI_FLASH) + /* configure the Prescale of SPI clk Tclk = 166MHz */ + MV_REG_READ_ASM (r6, r1, MV_SPI_IF_CONFIG_REG) + and r6, r6, #~MV_SPI_CLK_PRESCALE_MASK + orr r6, r6, #0x14 + MV_REG_WRITE_ASM (r6, r1, MV_SPI_IF_CONFIG_REG) +#endif + +#if !defined(MV_INC_BOARD_DDIM) +#if !defined(MV_BOOTROM) + + /* Call DRAM static initialization */ + bl _mvDramIfStaticInit +#else + b done +#endif +#else /* #if !defined(MV_INC_BOARD_DDIM) */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + + b done +#endif /* #if !defined(MV_INC_BOARD_DDIM) */ +done: + mov lr, r2 + mov pc, lr diff --git a/board/mv_feroceon/mv_orion/mv_cmd.c b/board/mv_feroceon/mv_orion/mv_cmd.c new file mode 100644 index 0000000..b446c29 --- /dev/null +++ b/board/mv_feroceon/mv_orion/mv_cmd.c @@ -0,0 +1,1162 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include +#include + +#include "mvTypes.h" +#include "mvCtrlEnvLib.h" + +#if defined(MV_INC_BOARD_NOR_FLASH) +#include "norflash/mvFlash.h" +#endif + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) +#include "eth-phy/mvEthPhy.h" +#endif + +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif + +#if defined(MV_INCLUDE_IDMA) +#include "idma/mvIdma.h" +#include "sys/mvSysIdma.h" +#endif + +#if defined(CFG_NAND_BOOT) || defined(CFG_CMD_NAND) +#include + +/* references to names in cmd_nand.c */ +#define NANDRW_READ 0x01 +#define NANDRW_WRITE 0x00 +#define NANDRW_JFFS2 0x02 +//extern struct nand_chip nand_dev_desc[]; +extern nand_info_t nand_info[]; /* info for NAND chips */ +/* int nand_rw (struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf); + int nand_erase(struct nand_chip* nand, size_t ofs, + size_t len, int clean); +*/ +extern int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); +extern int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts); + + +#endif /* CFG_NAND_BOOT */ + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) +#if !defined(CFG_NAND_BOOT) +static unsigned int flash_in_which_sec(flash_info_t *fl,unsigned int offset) +{ + unsigned int sec_num; + if(NULL == fl) + return 0xFFFFFFFF; + + for( sec_num = 0; sec_num < fl->sector_count ; sec_num++){ + /* If last sector*/ + if (sec_num == fl->sector_count -1) + { + if((offset >= fl->start[sec_num]) && + (offset <= (fl->size + fl->start[0] - 1)) ) + { + return sec_num; + } + + } + else + { + if((offset >= fl->start[sec_num]) && + (offset < fl->start[sec_num + 1]) ) + { + return sec_num; + } + + } + } + /* return illegal sector Number */ + return 0xFFFFFFFF; + +} + +#endif /* !defined(CFG_NAND_BOOT) */ + + +/******************************************************************************* +burn a u-boot.bin on the Boot Flash +********************************************************************************/ +extern flash_info_t flash_info[]; /* info for FLASH chips */ +#include +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if defined(CFG_NAND_BOOT) +/* Boot from NAND flash */ +/* Write u-boot image into the nand flash */ +int nand_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 ret = 0; + extern char console_buffer[]; + nand_info_t *nand = &nand_info[0]; + nand_erase_options_t er_opts; + nand_write_options_t wr_opts; + + load_addr = CFG_LOAD_ADDR; + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "u-boot.bin", sizeof(BootFile)); + printf("using default file \"u-boot.bin\" \n"); + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + + printf("\n**Warning**\n"); + printf("If U-Boot Endiannes is going to change (LE->BE or BE->LE), Then Env parameters should be overriden..\n"); + printf("Override Env parameters? (y/n)"); + readline(" "); + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + printf("Erase Env parameters sector %d... ",CFG_ENV_OFFSET); + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_ENV_OFFSET; + er_opts.length = CFG_ENV_SECT_SIZE; + er_opts.quiet = 1; + + nand_erase_opts(nand, &er_opts); + //nand_erase(nand_dev_desc + 0, CFG_ENV_OFFSET, CFG_ENV_SECT_SIZE, 0); + printf("\n"); + } + + printf("Erase %d - %d ... ",CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE, CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE); + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE; + er_opts.length = CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE; + er_opts.quiet = 1; + nand_erase_opts(nand, &er_opts); + //nand_erase(nand_dev_desc + 0, CFG_MONITOR_BASE, CFG_MONITOR_LEN, 0); + + printf("\nCopy to Nand Flash... "); + memset(&wr_opts, 0, sizeof(wr_opts)); + wr_opts.buffer = (u_char*) load_addr + CFG_ENV_SECT_SIZE; + wr_opts.length = CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE; + wr_opts.offset = CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE; + /* opts.forcejffs2 = 1; */ + wr_opts.pad = 1; + wr_opts.blockalign = 1; + wr_opts.quiet = 1; + ret = nand_write_opts(nand, &wr_opts); + /* ret = nand_rw(nand_dev_desc + 0, + NANDRW_WRITE | NANDRW_JFFS2, CFG_MONITOR_BASE, CFG_MONITOR_LEN, + &total, (u_char*)0x100000 + CFG_MONITOR_IMAGE_OFFSET); + */ + if (ret) + printf("Error - NAND burn faild!\n"); + else + printf("\ndone\n"); + + return 1; +} + +U_BOOT_CMD( + bubt, 2, 1, nand_burn_uboot_cmd, + "bubt - Burn an image on the Boot Nand Flash.\n", + " file-name \n" + "\tBurn a binary image on the Boot Nand Flash, default file-name is u-boot.bin .\n" +); + +/* Write nboot loader image into the nand flash */ +int nand_burn_nboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 ret = 0; + extern char console_buffer[]; + nand_info_t *nand = &nand_info[0]; + nand_erase_options_t er_opts; + nand_write_options_t wr_opts; + + + load_addr = CFG_LOAD_ADDR; + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "nboot.bin", sizeof(BootFile)); + printf("using default file \"nboot.bin\" \n"); + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + + printf("Erase %d - %d ... ",CFG_NBOOT_BASE, CFG_NBOOT_LEN); + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_NBOOT_BASE; + er_opts.length = CFG_NBOOT_LEN; + er_opts.quiet = 1; + + nand_erase_opts(nand, &er_opts); + //nand_erase(nand_dev_desc + 0, CFG_NBOOT_BASE, CFG_NBOOT_LEN , 0); + + printf("\nCopy to Nand Flash... "); + memset(&wr_opts, 0, sizeof(wr_opts)); + wr_opts.buffer = (u_char*) load_addr; + wr_opts.length = CFG_NBOOT_LEN; + wr_opts.offset = CFG_NBOOT_BASE; + /* opts.forcejffs2 = 1; */ + wr_opts.pad = 1; + wr_opts.blockalign = 1; + wr_opts.quiet = 1; + ret = nand_write_opts(nand, &wr_opts); + /* ret = nand_rw(nand_dev_desc + 0, + NANDRW_WRITE | NANDRW_JFFS2, CFG_NBOOT_BASE, CFG_NBOOT_LEN, + &total, (u_char*)0x100000); + */ + if (ret) + printf("Error - NAND burn faild!\n"); + else + printf("\ndone\n"); + + return 1; +} + +U_BOOT_CMD( + nbubt, 2, 1, nand_burn_nboot_cmd, + "nbubt - Burn a boot loader image on the Boot Nand Flash.\n", + " file-name \n" + "\tBurn a binary boot loader image on the Boot Nand Flash, default file-name is nboot.bin .\n" +); + +#else +/* Boot from Nor flash */ +int nor_burn_uboot_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int filesize; + MV_U32 s_first,s_end,env_sec; + extern char console_buffer[]; + + + s_first = flash_in_which_sec(&flash_info[BOOT_FLASH_INDEX], CFG_MONITOR_BASE); + s_end = flash_in_which_sec(&flash_info[BOOT_FLASH_INDEX], CFG_MONITOR_BASE + CFG_MONITOR_LEN -1); + + env_sec = flash_in_which_sec(&flash_info[BOOT_FLASH_INDEX], CFG_ENV_ADDR); + + + load_addr = CFG_LOAD_ADDR; + if(argc == 2) { + copy_filename (BootFile, argv[1], sizeof(BootFile)); + } + else { + copy_filename (BootFile, "u-boot.bin", sizeof(BootFile)); + printf("using default file \"u-boot.bin\" \n"); + } + + if ((filesize = NetLoop(TFTP)) < 0) + return 0; + + printf("Un-Protect Flash Monitor space\n"); + flash_protect (FLAG_PROTECT_CLEAR, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[BOOT_FLASH_INDEX]); + + printf("\n**Warning**\n"); + printf("If U-Boot Endiannes is going to change (LE->BE or BE->LE), Then Env parameters should be overriden..\n"); + printf("Override Env parameters? (y/n)"); + readline(" "); + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + flash_protect (FLAG_PROTECT_CLEAR, + flash_info[BOOT_FLASH_INDEX].start[env_sec], + flash_info[BOOT_FLASH_INDEX].start[env_sec] + CFG_ENV_SECT_SIZE - 1, + &flash_info[BOOT_FLASH_INDEX]); + + printf("Erase Env parameters sector %d... ",env_sec); + flash_erase(&flash_info[BOOT_FLASH_INDEX], env_sec, env_sec); + + if ((mvCtrlModelGet() != MV_6082_DEV_ID) && + (mvCtrlModelGet() != MV_6183_DEV_ID) && + (mvCtrlModelGet() != MV_6183L_DEV_ID)) + flash_protect (FLAG_PROTECT_SET, + flash_info[BOOT_FLASH_INDEX].start[env_sec], + flash_info[BOOT_FLASH_INDEX].start[env_sec] + CFG_ENV_SECT_SIZE - 1, + &flash_info[BOOT_FLASH_INDEX]); + + } + + printf("Erase %d - %d sectors... ",s_first,s_end); + flash_erase(&flash_info[BOOT_FLASH_INDEX], s_first, s_end); + + printf("Copy to Flash... "); + + flash_write ( (uchar *)CFG_LOAD_ADDR + CFG_MONITOR_IMAGE_OFFSET, + CFG_MONITOR_BASE, + filesize - CFG_MONITOR_IMAGE_OFFSET); + + printf("done\nProtect Flash Monitor space\n"); + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[BOOT_FLASH_INDEX]); + + return 1; +} + +U_BOOT_CMD( + bubt, 2, 1, nor_burn_uboot_cmd, + "bubt - Burn an image on the Boot Flash.\n", + " file-name \n" + "\tBurn a binary image on the Boot Flash, default file-name is u-boot.bin .\n" +); +#endif /* defined(CFG_NAND_BOOT) */ +#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */ + + + +/******************************************************************************* +Reset environment variables. +********************************************************************************/ +extern flash_info_t flash_info[]; /* info for FLASH chips */ +int resetenv_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(CFG_NAND_BOOT) + printf("Erase Env parameters offset 0x%x... ",CFG_ENV_OFFSET); + nand_info_t *nand = &nand_info[0]; + nand_erase_options_t er_opts; + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_ENV_OFFSET; + er_opts.length = CFG_ENV_SECT_SIZE; + er_opts.quiet = 1; + + nand_erase_opts(nand, &er_opts); + //nand_erase(nand_dev_desc + 0, CFG_ENV_OFFSET, CFG_ENV_SECT_SIZE, 0); + printf("done"); +#else + MV_U32 env_sec = flash_in_which_sec(&flash_info[0], CFG_ENV_ADDR); + + if (env_sec == -1) + { + printf("Could not find ENV Sector\n"); + return 0; + } + + printf("Un-Protect ENV Sector\n"); + + flash_protect(FLAG_PROTECT_CLEAR, + CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + + printf("Erase sector %d ... ",env_sec); + flash_erase(&flash_info[0], env_sec, env_sec); + printf("done\nProtect ENV Sector\n"); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + +#endif /* defined(CFG_NAND_BOOT) */ + printf("\nWarning: Default Environment Variables will take effect Only after RESET \n\n"); + return 1; +} + +U_BOOT_CMD( + resetenv, 1, 1, resetenv_cmd, + "resetenv - Return all environment variable to default.\n", + " \n" + "\t Erase the environemnt variable sector.\n" +); + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FLASH) */ +#if CONFIG_COMMANDS & CFG_CMD_BSP + +/****************************************************************************** +* Category - General +* Functionality- The commands allows the user to view the contents of the MV +* internal registers and modify them. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int ir_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_U32 regNum = 0x0, regVal, regValTmp, res; + MV_8 regValBin[40]; + MV_8 cmd[30]; + int i,j = 0, flagm = 0; + extern MV_8 console_buffer[]; + + if( argc == 2 ) { + regNum = simple_strtoul( argv[1], NULL, 16 ); + } + else { + printf( "Usage:\n%s\n", cmdtp->usage ); + return 0; + } + + regVal = MV_REG_READ( regNum ); + regValTmp = regVal; + printf( "Internal register 0x%x value : 0x%x\n ",regNum, regVal ); + printf( "\n 31 24 16 8 0" ); + printf( "\n | | | | |\nOLD: " ); + + for( i = 31 ; i >= 0 ; i-- ) { + if( regValTmp > 0 ) { + res = regValTmp % 2; + regValTmp = (regValTmp - res) / 2; + if( res == 0 ) + regValBin[i] = '0'; + else + regValBin[i] = '1'; + } + else + regValBin[i] = '0'; + } + + for( i = 0 ; i < 32 ; i++ ) { + printf( "%c", regValBin[i] ); + if( (((i+1) % 4) == 0) && (i > 1) && (i < 31) ) + printf( "-" ); + } + + readline( "\nNEW: " ); + strcpy(cmd, console_buffer); + if( (cmd[0] == '0') && (cmd[1] == 'x') ) { + regVal = simple_strtoul( cmd, NULL, 16 ); + flagm=1; + } + else { + for( i = 0 ; i < 40 ; i++ ) { + if(cmd[i] == '\0') + break; + if( i == 4 || i == 9 || i == 14 || i == 19 || i == 24 || i == 29 || i == 34 ) + continue; + if( cmd[i] == '1' ) { + regVal = regVal | (0x80000000 >> j); + flagm = 1; + } + else if( cmd[i] == '0' ) { + regVal = regVal & (~(0x80000000 >> j)); + flagm = 1; + } + j++; + } + } + + if( flagm == 1 ) { + MV_REG_WRITE( regNum, regVal ); + printf( "\nNew value = 0x%x\n\n", MV_REG_READ(regNum) ); + } + return 1; +} + +U_BOOT_CMD( + ir, 2, 1, ir_cmd, + "ir - reading and changing MV internal register values.\n", + " address\n" + "\tDisplays the contents of the internal register in 2 forms, hex and binary.\n" + "\tIt's possible to change the value by writing a hex value beginning with \n" + "\t0x or by writing 0 or 1 in the required place. \n" + "\tPressing enter without any value keeps the value unchanged.\n" +); + +/****************************************************************************** +* Category - General +* Functionality- Display the auto detect values of the TCLK and SYSCLK. +* Need modifications (Yes/No) - no +*****************************************************************************/ +int clk_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf( "TCLK %dMhz, SYSCLK %dMhz (UART baudrate %d)\n", + mvTclkGet()/1000000, mvSysClkGet()/1000000, CONFIG_BAUDRATE); + return 1; +} + +U_BOOT_CMD( + dclk, 1, 1, clk_cmd, + "dclk - Display the MV device CLKs.\n", + " \n" + "\tDisplay the auto detect values of the TCLK and SYSCLK.\n" +); + +/****************************************************************************** +* Functional only when using Lauterbach to load image into DRAM +* Category - DEBUG +* Functionality- Display the array of registers the u-boot write to. +* +*****************************************************************************/ +#if defined(REG_DEBUG) +int reg_arry[4096][2]; +int reg_arry_index = 0; +int print_registers( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + printf("Register display\n"); + + for (i=0; i < reg_arry_index; i++) + printf("Reg no %d addr 0x%x = 0x%08x\n", i, reg_arry[i][0], reg_arry[i][1]); + + return 1; +} + +U_BOOT_CMD( + printreg, 1, 1, print_registers, + "printreg - Display the register array the u-boot write to.\n", + " \n" + "\tDisplay the register array the u-boot write to.\n" +); +#endif + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) +/****************************************************************************** +* Category - Etherent +* Functionality- Display PHY ports status (using SMI access). +* Need modifications (Yes/No) - No +*****************************************************************************/ +int sg_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#if defined(MV_INC_BOARD_QD_SWITCH) + printf( "Switch status not supported\n"); +#else + MV_U32 port; + for( port = 0 ; port < mvCtrlEthMaxPortGet(); port++ ) { + + printf( "PHY %d :\n", port ); + printf( "---------\n" ); + + mvEthPhyPrintStatus( mvBoardPhyAddrGet(port) ); + + printf("\n"); + } +#endif + return 1; +} + +U_BOOT_CMD( + sg, 1, 1, sg_cmd, + "sg - scanning the PHYs status\n", + " \n" + "\tScan all the Gig port PHYs and display their Duplex, Link, Speed and AN status.\n" +); +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + +#if defined(MV_INCLUDE_IDMA) + +/****************************************************************************** +* Category - DMA +* Functionality- Perform a DMA transaction +* Need modifications (Yes/No) - No +*****************************************************************************/ +int mvDma_cmd( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + MV_8 cmd[20], c; + extern MV_8 console_buffer[]; + MV_U32 chan, src, dst, byteCount, ctrlLo; + MV_DMA_DEC_WIN win; + MV_BOOL err; + + /* IDMA channel */ + if( argc == 2 ) + chan = simple_strtoul( argv[1], NULL, 16 ); + else + chan = 0; + + /* source address */ + while(1) { + readline( "Source Address: " ); + strcpy( cmd, console_buffer ); + src = simple_strtoul( cmd, NULL, 16 ); + if( src == 0xffffffff ) printf( "Bad address !!!\n" ); + else break; + } + + /* desctination address */ + while(1) { + readline( "Destination Address: " ); + strcpy(cmd, console_buffer); + dst = simple_strtoul( cmd, NULL, 16 ); + if( dst == 0xffffffff ) printf("Bad address !!!\n"); + else break; + } + + /* byte count */ + while(1) { + readline( "Byte Count (up to 16M (0xffffff-1)): " ); + strcpy( cmd, console_buffer ); + byteCount = simple_strtoul( cmd, NULL, 16 ); + if( (byteCount > 0xffffff) || (byteCount == 0) ) printf("Bad value !!!\n"); + else break; + } + + /* compose the command */ + ctrlLo = ICCLR_BLOCK_MODE | ICCLR_NON_CHAIN_MODE | ICCLR_SRC_INC | ICCLR_DST_INC; + + + if (byteCount > _64K) + { + ctrlLo |= ICCLR_DESC_MODE_16M; + } + + /* set data transfer limit */ + while(1) { + printf( "Data transfer limit:\n" ); + printf( "(1) 8 bytes at a time.\n" ); + printf( "(2) 16 bytes at a time.\n" ); + printf( "(3) 32 bytes at a time.\n" ); + printf( "(4) 64 bytes at a time.\n" ); + printf( "(5) 128 bytes at a time.\n" ); + + c = getc(); + printf( "%c\n", c ); + + err = MV_FALSE; + + switch( c ) { + case 13: /* Enter */ + ctrlLo |= (ICCLR_DST_BURST_LIM_32BYTE | ICCLR_SRC_BURST_LIM_32BYTE); + printf( "32 bytes at a time.\n" ); + break; + case '1': + ctrlLo |= (ICCLR_DST_BURST_LIM_8BYTE | ICCLR_SRC_BURST_LIM_8BYTE); + break; + case '2': + ctrlLo |= (ICCLR_DST_BURST_LIM_16BYTE | ICCLR_SRC_BURST_LIM_16BYTE); + break; + case '3': + ctrlLo |= (ICCLR_DST_BURST_LIM_32BYTE | ICCLR_SRC_BURST_LIM_32BYTE); + break; + case '4': + ctrlLo |= (ICCLR_DST_BURST_LIM_64BYTE | ICCLR_SRC_BURST_LIM_64BYTE); + break; + case '5': + ctrlLo |= (ICCLR_DST_BURST_LIM_128BYTE | ICCLR_SRC_BURST_LIM_128BYTE); + break; + default: + printf( "Bad value !!!\n" ); + err = MV_TRUE; + } + + if( !err ) break; + } + + /* set ovveride source option */ + while(1) { + printf( "Override Source:\n" ); + printf( "(0) - no override\n" ); + mvDmaWinGet( 1, &win ); + printf( "(1) - use Win1 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 2, &win ); + printf( "(2) - use Win2 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 3, &win ); + printf( "(3) - use Win3 (%s)\n",mvCtrlTargetNameGet(win.target)); + + c = getc(); + printf( "%c\n", c ); + + err = MV_FALSE; + + switch( c ) { + case 13: /* Enter */ + case '0': + printf( "No override\n" ); + break; + case '1': + ctrlLo |= ICCLR_OVRRD_SRC_BAR(1); + break; + case '2': + ctrlLo |= ICCLR_OVRRD_SRC_BAR(2); + break; + case '3': + ctrlLo |= ICCLR_OVRRD_SRC_BAR(3); + break; + default: + printf("Bad value !!!\n"); + err = MV_TRUE; + } + + if( !err ) break; + } + + /* set override destination option */ + while(1) { + printf( "Override Destination:\n" ); + printf( "(0) - no override\n" ); + mvDmaWinGet( 1, &win ); + printf( "(1) - use Win1 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 2, &win ); + printf( "(2) - use Win2 (%s)\n",mvCtrlTargetNameGet(win.target)); + mvDmaWinGet( 3, &win ); + printf( "(3) - use Win3 (%s)\n",mvCtrlTargetNameGet(win.target)); + + c = getc(); + printf( "%c\n", c ); + + err = MV_FALSE; + + switch( c ) { + case 13: /* Enter */ + case '0': + printf( "No override\n" ); + break; + case '1': + ctrlLo |= ICCLR_OVRRD_DST_BAR(1); + break; + case '2': + ctrlLo |= ICCLR_OVRRD_DST_BAR(2); + break; + case '3': + ctrlLo |= ICCLR_OVRRD_DST_BAR(3); + break; + default: + printf("Bad value !!!\n"); + err = MV_TRUE; + } + + if( !err ) break; + } + + /* wait for previous transfer completion */ + while( mvDmaStateGet(chan) != MV_IDLE ); + + /* issue the transfer */ + mvDmaCtrlLowSet( chan, ctrlLo ); + mvDmaTransfer( chan, src, dst, byteCount, 0 ); + + /* wait for completion */ + while( mvDmaStateGet(chan) != MV_IDLE ); + + printf( "Done...\n" ); + return 1; +} + +U_BOOT_CMD( + dma, 2, 1, mvDma_cmd, + "dma - Perform DMA\n", + " \n" + "\tPerform DMA transaction with the parameters given by the user.\n" +); + +#endif /* #if defined(MV_INCLUDE_IDMA) */ + +/****************************************************************************** +* Category - Memory +* Functionality- Displays the MV's Memory map +* Need modifications (Yes/No) - Yes +*****************************************************************************/ +int displayMemoryMap_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvCtrlAddrDecShow(); + return 1; +} + +U_BOOT_CMD( + map, 1, 1, displayMemoryMap_cmd, + "map - Diasplay address decode windows\n", + " \n" + "\tDisplay controller address decode windows: CPU, PCI, Gig, DMA, XOR and COMM\n" +); + + + +#include "ddr1_2/mvDram.h" +#if defined(MV_INC_BOARD_DDIM) + +/****************************************************************************** +* Category - Memory +* Functionality- Displays the SPD information for a givven dimm +* Need modifications (Yes/No) - +*****************************************************************************/ + +int dimminfo_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int num = 0; + + if (argc > 1) { + num = simple_strtoul (argv[1], NULL, 10); + } + + printf("*********************** DIMM%d *****************************\n",num); + + dimmSpdPrint(num); + + printf("************************************************************\n"); + + return 1; +} + +U_BOOT_CMD( + ddimm, 2, 1, dimminfo_cmd, + "ddimm - Display SPD Dimm Info\n", + " [0/1]\n" + "\tDisplay Dimm 0/1 SPD information.\n" +); + +/****************************************************************************** +* Category - Memory +* Functionality- Copy the SPD information of dimm 0 to dimm 1 +* Need modifications (Yes/No) - +*****************************************************************************/ + +int spdcpy_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + printf("Copy DIMM 0 SPD data into DIMM 1 SPD..."); + + if (MV_OK != dimmSpdCpy()) + printf("\nDIMM SPD copy fail!\n"); + else + printf("Done\n"); + + return 1; +} + +U_BOOT_CMD( + spdcpy, 2, 1, spdcpy_cmd, + "spdcpy - Copy Dimm 0 SPD to Dimm 1 SPD \n", + "" + "" +); +#endif /* #if defined(MV_INC_BOARD_DDIM) */ + +/****************************************************************************** +* Functionality- Go to an address and execute the code there and return, +* defualt address is 0x40004 +*****************************************************************************/ +extern void cpu_dcache_flush_all(void); +extern void cpu_icache_flush_invalidate_all(void); + +void mv_go(unsigned long addr,int argc, char *argv[]) +{ + int rc; + addr = MV_CACHEABLE(addr); + char* envCacheMode = getenv("cacheMode"); + + /* + * pass address parameter as argv[0] (aka command name), + * and all remaining args + */ + + if(envCacheMode && (strcmp(envCacheMode,"write-through") == 0)) + { + int i=0; + + /* Flush Invalidate I-Cache */ + cpu_icache_flush_invalidate_all(); + + /* Drain write buffer */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); + + + } + else /*"write-back"*/ + { + int i=0; + + /* Flush Invalidate I-Cache */ + cpu_icache_flush_invalidate_all(); + + /* Drain write buffer */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); + + + /* Flush invalidate D-cache */ + cpu_dcache_flush_all(); + + + } + + + rc = ((ulong (*)(int, char *[]))addr) (--argc, &argv[1]); + + return; +} + +int g_cmd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong addr; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0; + } + + addr = 0x40000; + + if (argc > 1) { + addr = simple_strtoul(argv[1], NULL, 16); + } + mv_go(addr,argc,&argv[0]); + return 1; +} + +U_BOOT_CMD( + g, CFG_MAXARGS, 1, g_cmd, + "g - start application at cached address 'addr'(default addr 0x40000)\n", + " addr [arg ...] \n" + "\tStart application at address 'addr'cachable!!!(default addr 0x40004/0x240004)\n" + "\tpassing 'arg' as arguments\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/****************************************************************************** +* Functionality- Searches for a value +*****************************************************************************/ +int fi_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 s_address,e_address,value,i,tempData; + MV_BOOL error = MV_FALSE; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 4){ + value = simple_strtoul(argv[1], NULL, 16); + s_address = simple_strtoul(argv[2], NULL, 16); + e_address = simple_strtoul(argv[3], NULL, 16); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + if(s_address == 0xffffffff || e_address == 0xffffffff) error = MV_TRUE; + if(s_address%4 != 0 || e_address%4 != 0) error = MV_TRUE; + if(s_address > e_address) error = MV_TRUE; + if(error) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + for(i = s_address; i < e_address ; i+=4) + { + tempData = (*((volatile unsigned int *)i)); + if(tempData == value) + { + printf("Value: %x found at ",value); + printf("address: %x\n",i); + return 1; + } + } + printf("Value not found!!\n"); + return 1; +} + +U_BOOT_CMD( + fi, 4, 1, fi_cmd, + "fi - Find value in the memory.\n", + " value start_address end_address\n" + "\tSearch for a value 'value' in the memory from address 'start_address to\n" + "\taddress 'end_address'.\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + +/****************************************************************************** +* Functionality- Compare the memory with Value. +*****************************************************************************/ +int cmpm_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U32 s_address,e_address,value,i,tempData; + MV_BOOL error = MV_FALSE; + + if(!enaMonExt()){ + printf("This command can be used only if enaMonExt is set!\n"); + return 0;} + + if(argc == 4){ + value = simple_strtoul(argv[1], NULL, 16); + s_address = simple_strtoul(argv[2], NULL, 16); + e_address = simple_strtoul(argv[3], NULL, 16); + }else{ printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + + if(s_address == 0xffffffff || e_address == 0xffffffff) error = MV_TRUE; + if(s_address%4 != 0 || e_address%4 != 0) error = MV_TRUE; + if(s_address > e_address) error = MV_TRUE; + if(error) + { + printf ("Usage:\n%s\n", cmdtp->usage); + return 0; + } + for(i = s_address; i < e_address ; i+=4) + { + tempData = (*((volatile unsigned int *)i)); + if(tempData != value) + { + printf("Value: %x found at address: %x\n",tempData,i); + } + } + return 1; +} + +U_BOOT_CMD( + cmpm, 4, 1, cmpm_cmd, + "cmpm - Compare Memory\n", + " value start_address end_address.\n" + "\tCompare the memory from address 'start_address to address 'end_address'.\n" + "\twith value 'value'\n" + "\t(This command can be used only if enaMonExt is set!)\n" +); + + + +#if 0 +/****************************************************************************** +* Category - Etherent +* Functionality- Display PHY ports status (using SMI access). +* Need modifications (Yes/No) - No +*****************************************************************************/ +int eth_show_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + + ethRegs(argv[1]); + ethPortRegs(argv[1]); + ethPortStatus(argv[1]); + ethPortQueues(argv[1],0,0,1); + return 1; +} + +U_BOOT_CMD( + ethShow, 1, 1, eth_show_cmd, + "ethShow - scanning the PHYs status\n", + " \n" + "\tScan all the Gig port PHYs and display their Duplex, Link, Speed and AN status.\n" +); +#endif + +#if defined(MV_INCLUDE_PEX) + +#include "pci/mvPci.h" + +int pcie_phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvPexPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + pciePhyRead, 3, 3, pcie_phy_read_cmd, + "phyRead - Read PCI-E Phy register\n", + " PCI-E_interface Phy_offset. \n" + "\tRead the PCI-E Phy register. \n" +); + + +int pcie_phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvPexPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + pciePhyWrite, 4, 4, pcie_phy_write_cmd, + "pciePhyWrite - Write PCI-E Phy register\n", + " PCI-E_interface Phy_offset value.\n" + "\tWrite to the PCI-E Phy register.\n" +); + +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) + +#include "eth-phy/mvEthPhy.h" + +int phy_read_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + MV_U16 phyReg; + + mvEthPhyRegRead(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16), &phyReg); + + printf ("0x%x\n", phyReg); + + return 1; +} + +U_BOOT_CMD( + phyRead, 3, 3, phy_read_cmd, + "phyRead - Read Phy register\n", + " Phy_address Phy_offset. \n" + "\tRead the Phy register. \n" +); + + +int phy_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + mvEthPhyRegWrite(simple_strtoul( argv[1], NULL, 16 ), + simple_strtoul( argv[2], NULL, 16 ), + simple_strtoul( argv[3], NULL, 16 )); + + return 1; +} + +U_BOOT_CMD( + phyWrite, 4, 4, phy_write_cmd, + "phyWrite - Write Phy register\n", + " Phy_address Phy_offset value.\n" + "\tWrite to the Phy register.\n" +); + +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + +#endif /* MV_TINY */ +#if 0 +#if defined(CFG_NAND_BOOT) +extern int doNandScrub(struct nand_chip* nand, size_t ofs); + +/* Erase bad blocks - for internal use only */ +int do_nand_scrub(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern char console_buffer[]; + + printf("\n**Warning**\n"); + printf("This command will erase NAND flash bad blocks ...\n"); + printf("Are you sure ? (y/n)"); + readline(" "); + + if( strcmp(console_buffer,"Y") == 0 || + strcmp(console_buffer,"yes") == 0 || + strcmp(console_buffer,"y") == 0 ) { + + doNandScrub(nand_dev_desc + 0, 0); + } + return 1; +} + +U_BOOT_CMD( + nandScrub, 4, 4, do_nand_scrub, + "", + " " + "" +); + +#endif /* defined(CFG_NAND_BOOT) */ +#endif diff --git a/board/mv_feroceon/mv_orion/mv_dram.c b/board/mv_feroceon/mv_orion/mv_dram.c new file mode 100644 index 0000000..8fe33d1 --- /dev/null +++ b/board/mv_feroceon/mv_orion/mv_dram.c @@ -0,0 +1,395 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include "ddr1_2/mvDramIf.h" +#include "mvOs.h" +#include "mvBoardEnvLib.h" +#include "ddr1_2/mvDramIfRegs.h" +#include "mvCpuIfRegs.h" + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +extern void i2c_init(int speed, int slaveaddr); +extern void _start(void); +extern unsigned int mvCpuPclkGet(void); +extern void reset_cpu(void); +extern int dramBoot; + + +#ifdef MV_INC_DRAM_MFG_TEST +static MV_VOID mvDramMfgTrst(void); +static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count); +static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count); +#endif + +MV_VOID mvIntrfaceWidthPrint(MV_VOID) +{ + + if ((MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT) + { + printf(" 16bit width"); + } + else + { + printf(" 32bit width"); + } +} + +MV_VOID sizePrint(MV_U32 size) +{ + printf("size "); + + if(size >= _1G) + { + printf("%3dGB ", size / _1G); + size %= _1G; + if(size) + printf("+"); + } + if(size >= _1M ) + { + printf("%3dMB ", size / _1M); + size %= _1M; + if(size) + printf("+"); + } + if(size >= _1K) + { + printf("%3dKB ", size / _1K); + size %= _1K; + if(size) + printf("+"); + } + if(size > 0) + { + printf("%3dB ", size); + } +} + + +int dram_init (void) +{ + + DECLARE_GLOBAL_DATA_PTR; + unsigned int i, dramTotalSize=0; + char name[15]; + MV_32 memBase; + + mvCtrlModelRevNameGet(name); + printf("\nSoc: %s", name); + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + printf(" (DDR2)\n", name); + } + else + { + printf(" (DDR1)\n", name); + } + + printf("CPU running @ %dMhz \n", mvCpuPclkGet()/1000000); +#ifdef MV_TCLK_CALC + printf("SysClock = %dMhz , Calc TClock = %dMhz \n\n", CFG_BUS_CLK/1000000, CFG_TCLK/1000000); +#else + printf("SysClock = %dMhz , TClock = %dMhz \n\n", CFG_BUS_CLK/1000000, CFG_TCLK/1000000); +#endif + +#if defined(MV_INC_BOARD_DDIM) + /* Call dramInit */ + if (0 == (dramTotalSize = initdram(0))) + { + printf("DRAM Initialization Failed\n"); + reset_cpu(); + return (1); + } + + for(i = 0; i< MV_DRAM_MAX_CS; i++) + { + memBase = mvDramIfBankBaseGet(i); + if (MV_ERROR == memBase) + gd->bd->bi_dram[i].start = 0; + else + gd->bd->bi_dram[i].start = memBase; + + gd->bd->bi_dram[i].size = mvDramIfBankSizeGet(i); + if (gd->bd->bi_dram[i].size) + { + printf("DRAM CS[%d] base 0x%08x ",i, gd->bd->bi_dram[i].start); + mvSizePrint(gd->bd->bi_dram[i].size); + printf("\n"); + } + } + + printf("DRAM Total "); + mvSizePrint(dramTotalSize); + mvIntrfaceWidthPrint(); + printf("\n"); + +#else /* MV_INC_BOARD_DDIM */ + + for(i = 0; i< MV_DRAM_MAX_CS; i++) + { +#if !defined(MV_88F6082L) && defined(MV_88F6082) + if (mvCtrlModelRevGet() == MV_6082_A0_ID) + { + gd->bd->bi_dram[i].start = (i)?_16M:0; + gd->bd->bi_dram[i].size = _8M; + } + else + { + memBase = mvDramIfBankBaseGet(i); + if (MV_ERROR == memBase) + gd->bd->bi_dram[i].start = 0; + else + gd->bd->bi_dram[i].start = memBase; + + gd->bd->bi_dram[i].size = mvDramIfBankSizeGet(i); + } +#else + memBase = mvDramIfBankBaseGet(i); + if (MV_ERROR == memBase) + gd->bd->bi_dram[i].start = 0; + else + gd->bd->bi_dram[i].start = memBase; + + gd->bd->bi_dram[i].size = mvDramIfBankSizeGet(i); +#endif + dramTotalSize += gd->bd->bi_dram[i].size; + if (gd->bd->bi_dram[i].size) + { + printf("DRAM CS[%d] base 0x%08x ",i, gd->bd->bi_dram[i].start); + mvSizePrint(gd->bd->bi_dram[i].size); + printf("\n"); + } + } + + printf("DRAM Total "); + sizePrint(dramTotalSize); + mvIntrfaceWidthPrint(); + printf("\n"); +#ifdef MV_INC_DRAM_MFG_TEST + mvDramMfgTrst(); +#endif +#endif + return 0; +} + +#if defined(MV_INC_BOARD_DDIM) + +/* u-boot interface function to SDRAM init - this is where all the + * controlling logic happens */ +long int initdram(int board_type) +{ + MV_VOIDFUNCPTR pRom; + MV_U32 forcedCl; /* Forced CAS Latency */ + MV_U32 totalSize; + MV_U32 temp; + char * env; + MV_TWSI_ADDR slave; + + /* r0 <- current position of code */ + /* test if we run from flash or RAM */ + if(dramBoot != 1) + { + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, CFG_I2C_SPEED, CFG_TCLK, &slave, 0); + + /* Calculating MIN/MAX CAS latency according to user settings */ + env = getenv("CASset"); + + if(env && (strcmp(env,"1.5") == 0)) + { + forcedCl = 15; + } + else if(env && (strcmp(env,"2") == 0)) + { + forcedCl = 20; + } + else if(env && (strcmp(env,"2.5") == 0)) + { + forcedCl = 25; + } + else if(env && (strcmp(env,"3") == 0)) + { + forcedCl = 30; + } + else if(env && (strcmp(env,"4") == 0)) + { + forcedCl = 40; + } + else + { + forcedCl = 0; + } + + /* detect the dram configuartion parameters */ + if (MV_OK != mvDramIfDetect(forcedCl)) + { + printf("DRAM Auto Detection Failed! System Halt!\n"); + return 0; + } + + /* set the dram configuration */ + /* Calculate jump address of _mvDramIfConfig() */ +#if defined(MV_BOOTROM) + pRom = (MV_VOIDFUNCPTR)((_mvDramIfConfig - _start) + CFG_MONITOR_BASE + MONITOR_HEADER_LEN); +#else + pRom = (MV_VOIDFUNCPTR)((_mvDramIfConfig - _start) + CFG_MONITOR_BASE); +#endif + + + (*pRom) (); /* Jump to _mvDramIfConfig*/ + } + + totalSize = mvDramIfSizeGet(); + + printf("DRAM"); + if(MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + switch((MV_REG_READ(0x141c) >> 4) & 0x7) + { + case 0x3: printf(" CAS Latency = 3"); + break; + case 0x4: printf(" CAS Latency = 4"); + break; + case 0x5: printf(" CAS Latency = 1.5"); + break; + default: printf(" unknown CAL "); + break; + } + } + else + { + switch((MV_REG_READ(0x141c) >> 4) & 0x7) + { + case 0x2: printf(" CAS Latency = 2"); + break; + case 0x3: printf(" CAS Latency = 3"); + break; + case 0x4: printf(" CAS Latency = 4"); + break; + case 0x5: printf(" CAS Latency = 1.5"); + break; + case 0x6: printf(" CAS Latency = 2.5"); + break; + default: printf(" unknown CAL "); + break; + } + } + + temp = MV_REG_READ(0x1408); + printf(" tRP = %d tRAS = %d tRCD=%d\n", + ((temp >> 8) & 0xf) + 1, ((temp >> 20) & 0xf) + 1, ((temp >> 4) & 0xf) + 1); + + return(totalSize); +} + +#endif /* #if defined(MV_INC_BOARD_DDIM) */ + +#ifdef MV_INC_DRAM_MFG_TEST +static MV_VOID mvDramMfgTrst(void) +{ + + /* Memory test */ + DECLARE_GLOBAL_DATA_PTR; + unsigned int mem_len,i,j, pattern; + unsigned int *mem_start; + char *env; + + env = getenv("enaPost"); + if(!env || ( (strcmp(env,"Yes") == 0) || (strcmp(env,"yes") == 0) ) ) + { + printf("Memory test pattern: "); + + for (j = 0 ; j<2 ; j++) + { + + switch(j){ + case 0: + pattern=0x55555555; + printf("0x%X, ",pattern); + break; + case 1: + pattern=0xAAAAAAAA; + printf("0x%X, ",pattern); + break; + default: + pattern=0x0; + printf("0x%X, ",pattern); + break; + } + + for(i = 0; i< MV_DRAM_MAX_CS; i++) + { + mem_start = (unsigned int *)gd->bd->bi_dram[i].start; + mem_len = gd->bd->bi_dram[i].size; + if (i == 0) + { + mem_start+= _4M; + mem_len-= _4M; + } + mem_len/=4; + if (MV_OK != mv_mem_test(mem_start, pattern, mem_len)) + { + printf(" Fail!\n"); + while(1); + } + } + } + printf(" Pass\n"); + } +} + + +static MV_STATUS mv_mem_test(MV_U32* pMem, MV_U32 pattern, MV_U32 count) +{ + int i; + for (i=0 ; i< count ; i+=1) + *(pMem + i) = pattern; + + if (MV_OK != mv_mem_cmp(pMem, pattern, count)) + { + return MV_ERROR; + } + return MV_OK; +} + +static MV_STATUS mv_mem_cmp(MV_U32* pMem, MV_U32 pattern, MV_U32 count) +{ + int i; + for (i=0 ; i< count ; i+=1) + { + if (*(pMem + i) != pattern) + { + printf("Fail\n"); + printf("Test failed at 0x%x\n",(pMem + i)); + return MV_ERROR; + } + } + + return MV_OK; +} +#endif /* MV_INC_DRAM_MFG_TEST */ diff --git a/board/mv_feroceon/mv_orion/mv_main.c b/board/mv_feroceon/mv_orion/mv_main.c new file mode 100644 index 0000000..7d26dd8 --- /dev/null +++ b/board/mv_feroceon/mv_orion/mv_main.c @@ -0,0 +1,1816 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include "mvTypes.h" +#include "mvBoardEnvLib.h" +#include "mvCpuIf.h" +#include "mvCtrlEnvLib.h" +#include "mv_mon_init.h" +#include "rtc/ext_rtc/mvDS133x.h" +#include "mvDebug.h" +#include "cpu/mvCpuArm.h" +#include "device/mvDevice.h" +#include "twsi/mvTwsi.h" +#include "eth/mvEth.h" +#include "pex/mvPex.h" +#include "eth-phy/mvEthPhy.h" +#include "ethSwitch/mvSwitch.h" +#include "gpp/mvGpp.h" +#include "sys/mvSysUsb.h" + +#if defined(MV_INCLUDE_XOR) +#include "xor/mvXor.h" +#endif +#if defined(MV_INCLUDE_IDMA) +#include "sys/mvSysIdma.h" +#include "idma/mvIdma.h" +#endif +#if defined(MV_INCLUDE_USB) +#include "usb/mvUsb.h" +#endif + +#include "cpu/mvCpu.h" + +#ifdef CONFIG_PCI +# include +#endif +#include "pci/mvPciRegs.h" + +#include +#include + +/* CPU address decode table. */ +MV_CPU_DEC_WIN mvCpuAddrWinMap[] = MV_CPU_IF_ADDR_WIN_MAP_TBL; + +static void mvStatusDebugLeds(char num); +#if defined(RD_88F6082NAS) || defined(RD_88F6082GE_SATA) || defined(RD_88F6082DAS_PLUS) || defined(RD_88F5182_3) +static void mvHddPowerCtrl(void); +#endif +#if defined(RD_88F6082MICRO_DAS_NAS) +static void bootDetection(void); +static void mv6082uDasNasSysPower(MV_BOOL enable); +#endif +void mv_cpu_init(void); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +static int mv_set_power_scheme(void); +#endif + +#ifdef CFG_FLASH_CFI_DRIVER +MV_VOID mvUpdateNorFlashBaseAddrBank(MV_VOID); +int mv_board_num_flash_banks; +extern flash_info_t flash_info[]; /* info for FLASH chips */ +extern unsigned long flash_add_base_addr (uint flash_index, ulong flash_base_addr); +#endif /* CFG_FLASH_CFI_DRIVER */ + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) +extern MV_VOID mvEgigaPhySwitchInit(void); +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +/* Define for SDK 2.0 */ +int __aeabi_unwind_cpp_pr0(int a,int b,int c) {return 0;} +int __aeabi_unwind_cpp_pr1(int a,int b,int c) {return 0;} +#endif + +/* Define for SDK 2.0 */ +int raise(void) {return 0;} + +/* Define only for open Linux support */ +#define RD_KUROBOX_PRO 0xFE +#define RD_KUROBOX_PRO_OPEN_LINUX_ID 1509 + +void print_mvBanner(void) +{ + printf("\n"); + printf(" __ __ _ _\n"); + printf(" | \\/ | __ _ _ ____ _____| | |\n"); + printf(" | |\\/| |/ _` | '__\\ \\ / / _ \\ | |\n"); + printf(" | | | | (_| | | \\ V / __/ | |\n"); + printf(" |_| |_|\\__,_|_| \\_/ \\___|_|_|\n"); + printf(" _ _ ____ _\n"); + printf("| | | | | __ ) ___ ___ | |_ \n"); + printf("| | | |___| _ \\ / _ \\ / _ \\| __| \n"); + printf("| |_| |___| |_) | (_) | (_) | |_ \n"); + printf(" \\___/ |____/ \\___/ \\___/ \\__| "); +#ifdef MV_INCLUDE_MONT_EXT + if(!enaMonExt()) + printf(" ** LOADER **"); + else + printf(" ** MONITOR **"); +#else + + printf(" ** Forcing LOADER mode only **"); +#endif /* MV_INCLUDE_MONT_EXT */ + + + return; +} + +void print_dev_id(void){ + static char boardName[30]; + + mvBoardNameGet(boardName); + +#if defined(MV_CPU_BE) + printf("\n ** MARVELL BOARD: %s BE ",boardName); +#else + printf("\n ** MARVELL BOARD: %s LE ",boardName); +#endif + + return; +} + + +extern MV_BOOL mvSataPhyShutdown(MV_U8 port); +MV_BOOL mvSataPhyPowerOn(MV_U8 port); + +#define CPU_MAIN_IRQ_MASK 0x20204 +#define CPU_MAIN_FIQ_MASK 0x20208 +#define CPU_END_POIN_MASK 0x2020c +void maskAllInt(void) +{ + /* mask all external interrupt sources */ + MV_REG_WRITE(CPU_MAIN_IRQ_MASK, 0); + MV_REG_WRITE(CPU_MAIN_FIQ_MASK, 0); + MV_REG_WRITE(CPU_END_POIN_MASK, 0); +} + +/* init for the Master*/ +void misc_init_r_dec_win(void) +{ + /* update all the windows BARS */ +#if defined(MV_INCLUDE_IDMA) + mvDmaInit(); +#endif + +#if defined(MV_INCLUDE_USB) + { + char *env; + + env = getenv("usb0Mode"); + if((!env) || (strcmp(env,"device") == 0) || (strcmp(env,"Device") == 0) ) + { + printf("USB 0: device mode\n"); + mvUsbInit(0, MV_FALSE); + } + else + { + printf("USB 0: host mode\n"); + mvUsbInit(0, MV_TRUE); + } + + + if (mvCtrlUsbMaxGet() == 2) + { + env = getenv("usb1Mode"); + if((!env) || (strcmp(env,"device") == 0) || (strcmp(env,"Device") == 0) ) + { + printf("USB 1: device mode\n"); + mvUsbInit(1, MV_FALSE); + } + else + { + printf("USB 1: host mode\n"); + mvUsbInit(1, MV_TRUE); + } + + + } + + } +#endif/* #if defined(MV_INCLUDE_USB) */ + + +#if defined(MV_INCLUDE_XOR) + mvXorInit(); +#endif + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + mv_set_power_scheme(); +#endif + + return; +} + + +/* + * Miscellaneous platform dependent initialisations + */ + +extern MV_STATUS mvEthPhyRegRead(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 *data); +extern MV_STATUS mvEthPhyRegWrite(MV_U32 phyAddr, MV_U32 regOffs, MV_U16 data); + +/* golabal mac address for yukon EC */ +unsigned char yuk_enetaddr[6]; +extern int interrupt_init (void); +extern void i2c_init(int speed, int slaveaddr); + + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; +#if defined(MV_INCLUDE_TWSI) + MV_TWSI_ADDR slave; +#endif + unsigned int i; + + maskAllInt(); + /* must initialize the int in order for udelay to work */ + interrupt_init(); + +#if defined(MV_INCLUDE_TWSI) + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, CFG_I2C_SPEED, CFG_TCLK, &slave, 0); +#endif + + + /* Init the Board environment module (device bank params init) */ + mvBoardEnvInit(); + + /* Init the Controlloer environment module (MPP init) */ + mvCtrlEnvInit(); + +#if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) + /* Init the PHY or Switch of the board */ + mvEgigaPhySwitchInit(); +#endif /* #if defined(MV_INCLUDE_UNM_ETH) || defined(MV_INCLUDE_GIG_ETH) */ + + mvStatusDebugLeds(3); + + /* Init the Controller CPU interface */ + mvCpuIfInit(mvCpuAddrWinMap); + + /* arch number of Integrator Board */ + gd->bd->bi_arch_number = 526; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + /* relocate the exception vectors */ + /* U-Boot is running from DRAM at this stage */ + for(i = 0; i < 0x100; i+=4) + { + *(unsigned int *)(0x0 + i) = *(unsigned int*)(TEXT_BASE + i); + + } + + /* Enable i cache for DB_FPGA only */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + __asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop"); + i |= BIT12; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + __asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop"); + + /* i cache can work without MMU, + d cache can not work without MMU: + i cache already enable in start.S */ + /* Change reset vector to address 0x0 */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~BIT13; + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* Update NOR flash base address bank for CFI driver */ +#ifdef CFG_FLASH_CFI_DRIVER + mvUpdateNorFlashBaseAddrBank(); +#endif /* CFG_FLASH_CFI_DRIVER */ + + mvStatusDebugLeds(4); + + return 0; +} + +void misc_init_r_env(void){ + char *env; + char tmp_buf[10]; + unsigned int malloc_len, board_id; + DECLARE_GLOBAL_DATA_PTR; + +#if defined(RD_88F5181L_FE) || defined(RD_88F5181L_GE) || \ + defined(RD_88W8660) || defined(RD_88F5181L_FXO_GE) || \ + defined(RD_88F5181_GTWGE) || defined(RD_88F5181_GTWFE) || defined(RD_88W8660_AP82S) ||\ + defined(DB_88W8660) || defined(DB_88F5181L) + +#if defined(MV_NAND_BOOT) + env = getenv("bootargs"); + if(!env) + setenv("bootargs","console=ttyS0,115200 mtdparts=nand_mtd:1m(uboot)ro,2m(uImage),29m(rootfs)"); +#else + unsigned int flashSize =0 , secSize =0, ubootSize =0; + char buff[256]; + +#if defined(MV_BOOTSIZE_4M) + flashSize = _4M; +#elif defined(MV_BOOTSIZE_8M) + flashSize = _8M; +#elif defined(MV_BOOTSIZE_16M) + flashSize = _16M; +#elif defined(MV_BOOTSIZE_32M) + flashSize = _32M; +#elif defined(MV_BOOTSIZE_64M) + flashSize = _64M; +#endif + +#if defined(MV_SEC_64K) + secSize = _64K; +#if defined(MV_TINY_IMAGE) + ubootSize = _256K; +#else + ubootSize = _512K; +#endif +#elif defined(MV_SEC_128K) + secSize = _128K; +#if defined(MV_TINY_IMAGE) + ubootSize = _128K * 3; +#else + ubootSize = _128K * 5; +#endif +#elif defined(MV_SEC_256K) + secSize = _256K; +#if defined(MV_TINY_IMAGE) + ubootSize = _256K * 3; +#else + ubootSize = _256K * 3; +#endif +#endif + + if ((0 == flashSize) || (0 == secSize) || (0 == ubootSize)) + { + env = getenv("bootargs"); + if(!env) + setenv("bootargs","console=ttyS0,115200"); + } + else + { + sprintf(buff,"console=ttyS0,115200 mtdparts=cfi_flash:0x%x(root),0x%x(uboot)ro", + flashSize - ubootSize, ubootSize); + env = getenv("bootargs"); + if(!env) + setenv("bootargs",buff); + } +#endif /* defined(MV_NAND_BOOT) */ +#else + env = getenv("bootargs"); + if(!env) + setenv("bootargs","console=ttyS0,115200"); +#endif + + /* Check if to use the LED's for debug or to use single led for init and Linux heartbeat */ +#if defined(MV_INCLUDE_TDM) || defined(MV_INC_BOARD_QD_SWITCH) + env = getenv("enaDebugLed"); + if(!env || ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + setenv("enaDebugLed","no"); + else + setenv("enaDebugLed","yes"); +#else + env = getenv("enaDebugLed"); + if(!env || ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + setenv("enaDebugLed","yes"); + else + setenv("enaDebugLed","no"); +#endif + + /* Linux open port support */ + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + setenv("mainlineLinux","yes"); + else + setenv("mainlineLinux","no"); + + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + /* arch number for open port Linux */ + env = getenv("arcNumber"); + if(!env ) + { + /* arch number according to board ID */ + board_id = mvBoardIdGet(); + switch(board_id){ + case(DB_88F5X81_DDR2): + sprintf(tmp_buf,"%d", DB_88F5X81_DDR2_OPEN_LINUX_ID); + board_id = DB_88F5X81_DDR2_OPEN_LINUX_ID; + break; + case(RD_88F5182_2XSATA): + sprintf(tmp_buf,"%d", RD_88F5182_2XSATA_OPEN_LINUX_ID); + board_id = RD_88F5182_2XSATA_OPEN_LINUX_ID; + break; + case(RD_KUROBOX_PRO): + sprintf(tmp_buf,"%d", RD_KUROBOX_PRO_OPEN_LINUX_ID); + board_id = RD_KUROBOX_PRO_OPEN_LINUX_ID; + break; + default: + sprintf(tmp_buf,"%d", DB_88F5X81_DDR2_OPEN_LINUX_ID); + board_id = DB_88F5X81_DDR2_OPEN_LINUX_ID; + break; + } + gd->bd->bi_arch_number = board_id; + setenv("arcNumber", tmp_buf); + } + else + { + gd->bd->bi_arch_number = simple_strtoul(env, NULL, 10); + } + } + + /* update the CASset env parameter */ + env = getenv("CASset"); + if(!env ) + { +#ifdef MV_MIN_CAL + setenv("CASset","min"); +#else + setenv("CASset","max"); +#endif + } + /* Monitor extension */ +#ifdef MV_INCLUDE_MONT_EXT + env = getenv("enaMonExt"); + if(/* !env || */ ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + setenv("enaMonExt","yes"); + else +#endif + setenv("enaMonExt","no"); + + env = getenv("enaFlashBuf"); + if( ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("enaFlashBuf","no"); + else + setenv("enaFlashBuf","yes"); + + /* CPU streaming */ + env = getenv("enaCpuStream"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("enaCpuStream","no"); + else + setenv("enaCpuStream","yes"); + + if(mvCtrlModelGet() == MV_5281_DEV_ID) /* Orion 2 */ + { + /* VFP */ + env = getenv("enaVFP"); + if (mvCtrlRevGet() == MV_5281_C0_REV) /* Orion 2 == C0 */ + { + if( env && ( ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ))) + setenv("enaVFP","yes"); + else + setenv("enaVFP","no"); + } + else + { + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaVFP","no"); + else + setenv("enaVFP","yes"); + + } + + /* Orion 2 D2 VFP sub arch */ + if (mvCtrlRevGet() == MV_5281_D2_REV) /* Orion 2 == D2 */ + { + env = getenv("enaVFP"); + if( env && ( ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ))) + { + env = getenv("vfpSubArch2"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("vfpSubArch2","no"); + else + setenv("vfpSubArch2","yes"); + } + } + + /* Write allocation for all 5281 device set to no */ + env = getenv("enaWrAllo"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaWrAllo","no"); + else + setenv("enaWrAllo","yes"); + + if (mvCtrlRevGet() >= MV_5281_B0_REV) /* Orion 2 >= B0 */ + { + + /* ICache Prefetch */ + env = getenv("enaICPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaICPref","no"); + else + setenv("enaICPref","yes"); + + + /* DCache Prefetch */ + env = getenv("enaDCPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaDCPref","no"); + else + setenv("enaDCPref","yes"); + } + } + + if (mvCtrlModelGet() == MV_1281_DEV_ID) /* TC90 */ + { + /* VFP */ + env = getenv("enaVFP"); + if( env && ( ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ))) + setenv("enaVFP","yes"); + else + setenv("enaVFP","no"); + + /* Write allocation */ + env = getenv("enaWrAllo"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaWrAllo","no"); + else + { + setenv("enaWrAllo","yes"); + } + + /* ICache Prefetch */ + env = getenv("enaICPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaICPref","no"); + else + setenv("enaICPref","yes"); + + + /* DCache Prefetch */ + env = getenv("enaDCPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaDCPref","no"); + else + setenv("enaDCPref","yes"); + } + + if (mvCtrlModelGet() == MV_6183_DEV_ID || + mvCtrlModelGet() == MV_6183L_DEV_ID) /* MV88F6183 & MV88F6183L*/ + { + + /* Pex mode */ + env = getenv("pexMode"); + if( env && ( ((strcmp(env,"EP") == 0) || (strcmp(env,"ep") == 0) ))) + setenv("pexMode","EP"); + else + { + setenv("pexMode","RC"); + } + + /* Write allocation */ + env = getenv("enaWrAllo"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaWrAllo","no"); + else + { + setenv("enaWrAllo","yes"); + } + + /* ICache Prefetch */ + env = getenv("enaICPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaICPref","no"); + else + setenv("enaICPref","yes"); + + + /* DCache Prefetch */ + env = getenv("enaDCPref"); + if( env && ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("enaDCPref","no"); + else + setenv("enaDCPref","yes"); + } + + if (mvCtrlModelGet() == MV_6082_DEV_ID) /* MV88F6082 */ + { + + /* Pex mode */ + env = getenv("pexMode"); + if( env && ( ((strcmp(env,"EP") == 0) || (strcmp(env,"ep") == 0) ))) + setenv("pexMode","EP"); + else + { + setenv("pexMode","RC"); + } + } + + env = getenv("sata_dma_mode"); + if( env && ((strcmp(env,"No") == 0) || (strcmp(env,"no") == 0) ) ) + setenv("sata_dma_mode","no"); + else + setenv("sata_dma_mode","yes"); + + + /* Malloc length */ + env = getenv("MALLOC_len"); + malloc_len = simple_strtoul(env, NULL, 10) << 20; + if(malloc_len == 0){ + sprintf(tmp_buf,"%d",CFG_MALLOC_LEN>>20); + setenv("MALLOC_len",tmp_buf);} + + /* primary network interface */ + env = getenv("ethprime"); + + if(!env) + setenv("ethprime",ENV_ETH_PRIME); + + + /* netbsd boot arguments */ + env = getenv("netbsd_en"); + if( !env || ( ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ))) + setenv("netbsd_en","no"); + else + { + + setenv("netbsd_en","yes"); + env = getenv("netbsd_gw"); + if(!env) + setenv("netbsd_gw","192.168.0.254"); + + env = getenv("netbsd_mask"); + if(!env) + setenv("netbsd_mask","255.255.255.0"); + + env = getenv("netbsd_fs"); + if(!env) + setenv("netbsd_fs","nfs"); + + env = getenv("netbsd_server"); + if(!env) + setenv("netbsd_server","192.168.0.1"); + + env = getenv("netbsd_ip"); + if(!env) + { + env = getenv("ipaddr"); + setenv("netbsd_ip",env); + } + + env = getenv("netbsd_rootdev"); + if(!env) + setenv("netbsd_rootdev","mgi0"); + + env = getenv("netbsd_add"); + if(!env) + setenv("netbsd_add","0x800000"); + + env = getenv("netbsd_get"); + if(!env) + setenv("netbsd_get","tftpboot $(netbsd_add) $(image_name)"); + + env = getenv("netbsd_set_args"); + if(!env) + setenv("netbsd_set_args","setenv bootargs nfsroot=$(netbsd_server):$(rootpath) fs=$(netbsd_fs) \ +ip=$(netbsd_ip) serverip=$(netbsd_server) mask=$(netbsd_mask) gw=$(netbsd_gw) rootdev=$(netbsd_rootdev) \ +ethaddr=$(ethaddr)"); + + env = getenv("netbsd_boot"); + if(!env) + setenv("netbsd_boot","bootm $(netbsd_add) $(bootargs)"); + + env = getenv("netbsd_bootcmd"); + if(!env) + setenv("netbsd_bootcmd","run netbsd_get ; run netbsd_set_args ; run netbsd_boot"); + } + + /* linux boot arguments */ + env = getenv("bootargs_root"); + if(!env) + setenv("bootargs_root","root=/dev/nfs rw"); + + /* For open Linux we set boot args differently */ + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + env = getenv("bootargs_end"); + if(!env) + setenv("bootargs_end",":::orion:eth0:none"); + } + else + { + env = getenv("bootargs_end"); + if(!env) + setenv("bootargs_end",CFG_BOOTARGS_END); + } + + + env = getenv("image_name"); + if(!env) + setenv("image_name","uImage"); + + +#if (CONFIG_BOOTDELAY >= 0) + env = getenv("bootcmd"); + if(!env) +#if defined(MV_INCLUDE_TDM) && defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootcmd","tftpboot 0x400000 $(image_name);\ +setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig) $(mvPhoneConfig); bootm 0x400000; "); +#elif defined(MV_INC_BOARD_QD_SWITCH) + setenv("bootcmd","tftpboot 0x400000 $(image_name);\ +setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig); bootm 0x400000; "); +#elif defined(MV_INCLUDE_TDM) + setenv("bootcmd","tftpboot 0x400000 $(image_name);\ +setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvPhoneConfig); bootm 0x400000; "); +#elif defined(RD_88F6082MICRO_DAS_NAS) + setenv("bootcmd","setenv bootargs $(bootargs) temp=$(minTemp),$(maxTemp); \ +bootext2 0:1,2 0x1000000 /boot/$(image_name) /dev/sda;"); +#else + + setenv("bootcmd","tftpboot 0x400000 $(image_name);\ +setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ +ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "); +#endif +#endif /* (CONFIG_BOOTDELAY >= 0) */ + + env = getenv("standalone"); + if(!env) +#if defined(MV_INCLUDE_TDM) && defined(MV_INC_BOARD_QD_SWITCH) + setenv("standalone","fsload 0x400000 $(image_name);setenv bootargs $(bootargs) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig) $(mvPhoneConfig); bootm 0x400000;"); +#elif defined(MV_INC_BOARD_QD_SWITCH) + setenv("standalone","fsload 0x400000 $(image_name);setenv bootargs $(bootargs) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvNetConfig); bootm 0x400000;"); +#elif defined(MV_INCLUDE_TDM) + setenv("standalone","fsload 0x400000 $(image_name);setenv bootargs $(bootargs) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end) $(mvPhoneConfig); bootm 0x400000;"); +#else + setenv("standalone","fsload 0x400000 $(image_name);setenv bootargs $(bootargs) root=/dev/mtdblock0 rw \ +ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;"); +#endif + +#if defined(DB_PRPMC) || defined(DB_MNG) + env = getenv("vx_boot"); + if(!env) + setenv("vx_boot","tftpboot $(default_load_addr) $(image_name);setenv bootargs sgi(0,0) host:VxWorks h=$(serverip) \ +e=$(ipaddr):FFFF0000 u=anonymous pw=target; setenv bootaddr 0x700; bootvx $(default_load_addr);"); + + env = getenv("dhcp_boot"); + if(!env) + setenv("dhcp_boot","dhcp;setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ +ip=$(ipaddr):$(serverip)$(bootargs_end); bootm $(default_load_addr);"); +#endif /* DB_PRPMC || DB_MNG */ + + /* Set boodelay to 3 sec, if Monitor extension are disabled */ + if(!enaMonExt()){ +#if defined(RD_88F6082MICRO_DAS_NAS) + setenv("bootdelay","1"); +#else + setenv("bootdelay","3"); +#endif + setenv("disaMvPnp","no"); + } + + /* Disable PNP config of Marvel memory controller devices. */ + env = getenv("disaMvPnp"); + if(!env) + setenv("disaMvPnp","no"); + + + + +#if (defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH)) \ + && !defined(DB_PRPMC) && !defined(DB_88F1281) && !defined(DB_MNG) + + /* MAC addresses */ + env = getenv("ethaddr"); + if(!env) + setenv("ethaddr",ETHADDR); + + env = getenv("ethmtu"); + if(!env) + setenv("ethmtu","1500"); + +#if !defined(MV_INCLUDE_TDM) && !defined(MV_INC_BOARD_QD_SWITCH) +/* ETH1ADDR not define in GWAP boards */ + env = getenv("eth1addr"); + if(!env) + setenv("eth1addr",ETH1ADDR); + + env = getenv("eth1mtu"); + if(!env) + setenv("eth1mtu","1500"); +#endif + +#if defined(MV_INCLUDE_TDM) + /* Set mvPhoneConfig env parameter */ + env = getenv("mvPhoneConfig"); + if(!env ) + setenv("mvPhoneConfig","mv_phone_config=dev0:fxs,dev1:fxs"); +#endif + +#if defined(MV_INC_BOARD_QD_SWITCH) + /* Set mvNetConfig env parameter */ + env = getenv("mvNetConfig"); + if(!env ) + setenv("mvNetConfig","mv_net_config=(eth0,00:aa:bb:cc:dd:ee,0)(eth1,00:11:22:33:44:55,1:2:3:4)"); +#endif +#endif /* (MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) */ + +#if defined(MV_INCLUDE_PCI) + env = getenv("pciMode"); + if(!env) + { + setenv("pciMode",ENV_PCI_MODE); + } + + env = getenv("pciMode"); + if ( env && ( (strcmp(env,"device") == 0) || (strcmp(env,"Device") == 0) )) + MV_REG_WRITE(PCI_ARBITER_CTRL_REG(0),(MV_REG_READ(PCI_ARBITER_CTRL_REG(0) & BIT31))); + +#endif /* (MV_INCLUDE_PCI) */ + +#if defined(MV_INCLUDE_USB) + + /* USB Host */ + env = getenv("usb0Mode"); + + if(!env) + { + setenv("usb0Mode",ENV_USB0_MODE); + } + + if (mvCtrlUsbMaxGet() == 2) + { + env = getenv("usb1Mode"); + + if(!env) + { + setenv("usb1Mode",ENV_USB1_MODE); + } + + } + + +#endif /* (MV_INCLUDE_USB) */ + +#if defined(YUK_ETHADDR) + + env = getenv("yuk_ethaddr"); + if(!env) + setenv("yuk_ethaddr",YUK_ETHADDR); + + { + int i; + + char *tmp = getenv ("yuk_ethaddr"); + char *end; + + for (i=0; i<6; i++) { + yuk_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + + } + + } + + +#endif /* defined(YUK_ETHADDR) */ + +#if defined(RD_88F6082NAS) || defined(RD_88F6082GE_SATA) || defined(RD_88F6082DAS_PLUS) || defined(RD_88F5182_3) + mvHddPowerCtrl(); +#endif + +#if defined(RD_88F6082MICRO_DAS_NAS) + env = getenv("serialNo"); + if(!env) + setenv("serialNo","AS100352999999"); + + env = getenv("fanPowerCtrl"); + if(!env) + setenv("fanPowerCtrl","Yes"); + + env = getenv("minTemp"); + if(!env) + setenv("minTemp","45"); + + env = getenv("maxTemp"); + if(!env) + setenv("maxTemp","50"); + + env = getenv("enaPost"); + if(!env) + setenv("enaPost","No"); + + bootDetection(); +#endif + return; +} + +#ifdef BOARD_LATE_INIT +int board_late_init (void) +{ + /* Check if to use the LED's for debug or to use single led for init and Linux heartbeat */ + mvStatusDebugLeds(0); + + return 0; +} +#endif + +int misc_init_r (void) +{ + char name[15]; + char *env; + volatile unsigned int temp; + + mvStatusDebugLeds(5); + + /* set as 946 */ + env = getenv("cpuName"); + if(!env) + setenv("cpuName","926"); + else + { + if (strcmp(env,"946") == 0) + { + /* set as 946 */ + unsigned int regVal; + + regVal = MV_REG_READ(CPU_CONFIG_REG); + regVal |= CCR_MMU_DISABLED; + MV_REG_WRITE(CPU_CONFIG_REG, regVal); + } + + } + + mvCpuNameGet(name); + printf("\nCPU : %s\n", name); + + /* init special env variables */ + misc_init_r_env(); + + mv_cpu_init(); + +#if defined(MV_INCLUDE_MONT_EXT) + if(enaMonExt()){ + printf("\n Marvell monitor extension:\n"); + mon_extension_after_relloc(); + } + printf("\n"); +#endif /* MV_INCLUDE_MONT_EXT */ + + /* init the units decode windows */ + misc_init_r_dec_win(); + +#ifdef CONFIG_PCI +#if !defined(MV_MEM_OVER_PCI_WA) + pci_init(); +#endif +#endif + + mvStatusDebugLeds(6); + + if((mvCtrlModelGet() == MV_5281_DEV_ID) || /* Orion 2 */ + (mvCtrlModelGet() == MV_1281_DEV_ID)) /* TC90 */ + { + + __asm__ __volatile__("mrc p15, 0, %0, c14, c0, 0" : "=r" (temp):: "memory"); + if (temp & 0x10000000) + { + printf("CPU: Write allocate enabled\n"); + } + else + { + printf("CPU: Write allocate Disabled\n"); + } + } + + mvStatusDebugLeds(7); + + return 0; +} + +MV_U32 mvTclkGet(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* get it only on first time */ + if(gd->tclk == 0) + gd->tclk = mvBoardTclkGet(); + + return gd->tclk; +} + +MV_U32 mvSysClkGet(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* get it only on first time */ + if(gd->bus_clk == 0) + gd->bus_clk = mvBoardSysClkGet(); + + return gd->bus_clk; +} + +#ifndef MV_TINY_IMAGE +/* exported for EEMBC */ +MV_U32 mvGetRtcSec(void) +{ + MV_RTC_TIME time; + mvRtcDS133xTimeGet(&time); + return (time.minutes * 60) + time.seconds; +} +#endif + +void reset_cpu(void) +{ + mvBoardReset(); +} + + +void mv_cpu_init(void) +{ + char *env; + char name[20]; + volatile unsigned int temp; + + /* Invalidate and Unlock CPU L1 I-cache which was locked in jump.s */ + if(mvCtrlModelGet() == MV_6183_DEV_ID) + { + temp = 0; + __asm__ __volatile__("mcr p15, 1, %0, c7, c5, 0" : "=r" (temp)); + __asm__ __volatile__("nop"); + __asm__ __volatile__("nop"); + __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 1" : "=r" (temp)); + __asm__ __volatile__("nop"); + __asm__ __volatile__("nop"); + } + + /*CPU streaming */ + if( (mvCtrlModelGet() == MV_5181_DEV_ID) || + (mvCtrlModelGet() == MV_5182_DEV_ID) || + (mvCtrlModelGet() == MV_5180_DEV_ID) || + (mvCtrlModelGet() == MV_8660_DEV_ID) || + (mvCtrlModelGet() == MV_5082_DEV_ID) ) /* orion 1 */ + { + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0" : "=r" (temp):: "memory"); + + env = getenv("enaCpuStream"); + if(!env || (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) + { + mvCtrlModelRevNameGet(name); + printf("%s streaming disabled \n",name); + temp &= ~BIT28; + } + else + { + printf("Orion 1 streaming enabled \n"); + temp |= BIT28; + } + + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0": :"r" (temp)); + + } + else if((mvCtrlModelGet() == MV_5281_DEV_ID) || /* Orion 2 */ + (mvCtrlModelGet() == MV_6183_DEV_ID) || /* Orion 6183 */ + (mvCtrlModelGet() == MV_6183L_DEV_ID) || /* Orion 6183L */ + (mvCtrlModelGet() == MV_1281_DEV_ID)) /* TC90 */ + { + __asm__ __volatile__("mrc p15, 0, %0, c14, c0, 0" : "=r" (temp):: "memory"); + + env = getenv("enaCpuStream"); + if(!env || (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) + { + printf("Streaming disabled \n"); + temp &= ~BIT29; + } + else + { + printf("Streaming enabled \n"); + temp |= BIT29; + } + + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0" :: "r" (temp)); + } + + + if (mvCtrlModelGet() == MV_5281_DEV_ID) /* Orion 2 */ + { + + env = getenv("mainlineLinux"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + if (mvCtrlRevGet() == MV_5281_D2_REV) /* Orion 2 D2 */ + { + /* Change CPU ID to Marvell */ + MV_REG_BIT_SET(CPU_FTDLL_CONFIG_REG, CFCR_FTDLL_OVERWRITE_ENABLE); + MV_REG_BIT_SET(CPU_FTDLL_CONFIG_REG, CFCR_MRVL_CPU_ID); + MV_REG_BIT_RESET(CPU_FTDLL_CONFIG_REG, CFCR_FTDLL_OVERWRITE_ENABLE); + + /* Change VFP ID to Marvell */ + __asm__ __volatile__("mrc p15, 0, %0, c14, c0, 0" : "=r" (temp):: "memory"); + temp |= BIT31; + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0" :: "r" (temp)); + } + } + + if (mvCtrlRevGet() == MV_5281_A0_REV) /* Orion 2 A0 */ + { +#ifndef DB_FPGA + env = getenv("enaVFP"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + /* init VFP to Run Fast Mode */ + printf("VFP initialized to Run Fast Mode.\n"); + temp = fmrx(FPSCR); + temp |= (FPSCR_DEFAULT_NAN | FPSCR_FLUSHTOZERO); + fmxr(FPSCR, temp); + } + else +#endif /* DB_FPGA */ + { + printf("VFP not initialized\n"); + } + + } + else if (mvCtrlRevGet() >= MV_5281_B0_REV)/* Orion 2 >= B0 */ + { +#ifndef DB_FPGA + env = getenv("enaVFP"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + /* Orion 2 D2 has VFP sub arch */ + if (mvCtrlRevGet() >= MV_5281_D2_REV)/* Orion 2 >= D2 */ + { + env = getenv("vfpSubArch2"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + MV_REG_BIT_SET(CPU_FTDLL_CONFIG_REG, CFCR_FTDLL_OVERWRITE_ENABLE); + MV_REG_BIT_SET(CPU_FTDLL_CONFIG_REG, CFCR_VFP_SUB_ARC_NUM_2); + MV_REG_BIT_RESET(CPU_FTDLL_CONFIG_REG, CFCR_FTDLL_OVERWRITE_ENABLE); + } + } + + /* init and Enable VFP to Run Fast Mode */ + printf("VFP initialized to Run Fast Mode.\n"); + /* Enable */ + temp = FPEXC_ENABLE; + fmxr(FPEXC, temp); + /* Run Fast Mode */ + temp = fmrx(FPSCR); + temp |= (FPSCR_DEFAULT_NAN | FPSCR_FLUSHTOZERO); + fmxr(FPSCR, temp); + } + else +#endif /* DB_FPGA */ + { + printf("VFP not initialized\n"); + /* Disable */ + temp = fmrx(FPEXC); + temp &= ~FPEXC_ENABLE; + fmxr(FPEXC, temp); + } + + /* DCache Pref */ + env = getenv("enaDCPref"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + MV_REG_BIT_SET( CPU_CONFIG_REG , CCR_DCACH_PREF_BUF_ENABLE); + } + if(env && ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + { + MV_REG_BIT_RESET( CPU_CONFIG_REG , CCR_DCACH_PREF_BUF_ENABLE); + } + + /* ICache Pref */ + env = getenv("enaICPref"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + MV_REG_BIT_SET( CPU_CONFIG_REG , CCR_ICACH_PREF_BUF_ENABLE); + } + if(env && ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + { + MV_REG_BIT_RESET( CPU_CONFIG_REG , CCR_ICACH_PREF_BUF_ENABLE); + + } + + } + + /* write allocate */ + env = getenv("enaWrAllo"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + __asm__ __volatile__("mrc p15, 0, %0, c14, c0, 0" : "=r" (temp):: "memory"); + temp |= BIT28; + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0" :: "r" (temp)); + } + else + { + __asm__ __volatile__("mrc p15, 0, %0, c14, c0, 0" : "=r" (temp):: "memory"); + temp &= ~BIT28; + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0" :: "r" (temp)); + } + } + + if (mvCtrlModelGet() == MV_6183_DEV_ID || + mvCtrlModelGet() == MV_6183L_DEV_ID) /* MV88F6183 & MV88F6183L*/ + { + /* DCache Pref */ + env = getenv("enaDCPref"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + MV_REG_BIT_SET( CPU_CONFIG_REG , CCR_DCACH_PREF_BUF_ENABLE); + } + if(env && ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + { + MV_REG_BIT_RESET( CPU_CONFIG_REG , CCR_DCACH_PREF_BUF_ENABLE); + } + + /* ICache Pref */ + env = getenv("enaICPref"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + MV_REG_BIT_SET( CPU_CONFIG_REG , CCR_ICACH_PREF_BUF_ENABLE); + } + if(env && ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + { + MV_REG_BIT_RESET( CPU_CONFIG_REG , CCR_ICACH_PREF_BUF_ENABLE); + + } + + /* write allocate */ + env = getenv("enaWrAllo"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + __asm__ __volatile__("mrc p15, 0, %0, c14, c0, 0" : "=r" (temp):: "memory"); + temp |= BIT28; + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0" :: "r" (temp)); + } + else + { + __asm__ __volatile__("mrc p15, 0, %0, c14, c0, 0" : "=r" (temp):: "memory"); + temp &= ~BIT28; + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0" :: "r" (temp)); + } + } + + if (mvCtrlModelGet() == MV_1281_DEV_ID) /* TC90 */ + { + env = getenv("enaVFP"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + /* init and Enable VFP to Run Fast Mode */ + printf("VFP initialized to Run Fast Mode.\n"); + /* Enable */ + temp = FPEXC_ENABLE; + fmxr(FPEXC, temp); + + /* Run Fast Mode */ + temp = fmrx(FPSCR); + temp |= (FPSCR_DEFAULT_NAN | FPSCR_FLUSHTOZERO); + + fmxr(FPSCR, temp); + } + else + { + printf("VFP not initialized\n"); + /* Disable */ + temp = fmrx(FPEXC); + temp &= ~FPEXC_ENABLE; + fmxr(FPEXC, temp); + } + + /* DCache Pref */ + env = getenv("enaDCPref"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + MV_REG_BIT_SET( CPU_CONFIG_REG , CCR_DCACH_PREF_BUF_ENABLE); + } + if(env && ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + { + MV_REG_BIT_RESET( CPU_CONFIG_REG , CCR_DCACH_PREF_BUF_ENABLE); + } + + /* ICache Pref */ + env = getenv("enaICPref"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + MV_REG_BIT_SET( CPU_CONFIG_REG , CCR_ICACH_PREF_BUF_ENABLE); + } + if(env && ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + { + MV_REG_BIT_RESET( CPU_CONFIG_REG , CCR_ICACH_PREF_BUF_ENABLE); + } + + /* write allocate */ + env = getenv("enaWrAllo"); + if(env && ((strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0))) + { + __asm__ __volatile__("mrc p15, 0, %0, c14, c0, 0" : "=r" (temp):: "memory"); + temp |= BIT28; + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0" :: "r" (temp)); + } + else + { + __asm__ __volatile__("mrc p15, 0, %0, c14, c0, 0" : "=r" (temp):: "memory"); + temp &= ~BIT28; + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0" :: "r" (temp)); + } + } +} + +/* Set unit in power off mode acording to the env powerOffUnit */ +/* Env powerOffUnit can has the following value: giga0, giga1, */ +/* pex0, pex1, usb0, usb1, sata0, sata1, cesa, none */ +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +static int mv_set_power_scheme(void) +{ + char *env; + env = getenv("powerOffUnit"); + if(!env || (strcmp(env,"none") == 0)) + { + setenv("powerOffUnit", "none"); + return MV_OK; + } + + env = getenv("powerOffUnit"); +#if defined(MV_INCLUDE_PEX) + if (strcmp(env,"pex0") == 0) + { + printf("Warning: Pex0 is Powered Off\n"); + mvPexPowerDown(0); + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); + } + else + if (strcmp(env,"pex1") == 0) + { + printf("Warning: Pex1 is Powered Off\n"); + mvPexPowerDown(1); + mvCtrlPwrClckSet(PEX_UNIT_ID, 1, MV_FALSE); + } + else +#endif /* #if defined(MV_INCLUDE_PEX) */ +#if defined(MV_INCLUDE_INTEG_SATA) + if (strcmp(env,"sata0") == 0) + { + printf("Warning: SATA0 is Powered Off\n"); + mvSataPhyShutdown(0); + mvCtrlPwrClckSet(SATA_UNIT_ID, 0, MV_FALSE); + } + else + if (strcmp(env,"sata1") == 0) + { + printf("Warning: SATA1 is Powered Off\n"); + mvSataPhyShutdown(1); + mvCtrlPwrClckSet(SATA_UNIT_ID, 1, MV_FALSE); + } + else +#endif/*#if defined(MV_INCLUDE_SATA) */ +#if defined(MV_INCLUDE_GIG_ETH) + if (strcmp(env,"giga0") == 0) + { + printf("Warning: Giga0 and Giga1 is Powered Off\n"); + mvEthPortPowerDown(0); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 0, MV_FALSE); + mvEthPortPowerDown(1); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 1, MV_FALSE); + } + else + if (strcmp(env,"giga1") == 0) + { + printf("Warning: Giga1 is Powered Off\n"); + mvEthPortPowerDown(1); + mvCtrlPwrClckSet(ETH_GIG_UNIT_ID, 1, MV_FALSE); + } + else +#endif /* #if defined(MV_INCLUDE_GIG_ETH) */ +#if defined(MV_INCLUDE_CESA) + if (strcmp(env,"cesa") == 0) + { + printf("Warning: CESA is Powered Off\n"); + mvCtrlPwrClckSet(CESA_UNIT_ID, 1, MV_FALSE); + } + else +#endif /* if defined(MV_INCLUDE_CESA) */ +#if defined(MV_INCLUDE_USB) + if (strcmp(env,"usb0") == 0) + { + printf("Warning: USB0 is Powered Off\n"); + mvUsbPowerDown(0); + mvCtrlPwrClckSet(USB_UNIT_ID, 0, MV_FALSE); + } + else + if (strcmp(env,"usb1") == 0) + { + printf("Warning: USB1 is Powered Off\n"); + mvUsbPowerDown(1); + mvCtrlPwrClckSet(USB_UNIT_ID, 1, MV_FALSE); + } +#endif/*#if defined(MV_INCLUDE_USB)*/ + + return MV_OK; +} + +#endif /* defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + +/******************************************************************************* +* mvUpdateNorFlashBaseAddrBank - +* +* DESCRIPTION: +* This function update the CFI driver base address bank with on board NOR +* devices base address. +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* None +* +*******************************************************************************/ +#ifdef CFG_FLASH_CFI_DRIVER +MV_VOID mvUpdateNorFlashBaseAddrBank(MV_VOID) +{ + + MV_U32 devBaseAddr; + MV_U32 devNum = 0; + int i; + + /* Update NOR flash base address bank for CFI flash init driver */ + for (i = 0 ; i < CFG_MAX_FLASH_BANKS_DETECT; i++) + { + devBaseAddr = mvBoardGetDeviceBaseAddr(i,BOARD_DEV_NOR_FLASH); + if (devBaseAddr != 0xFFFFFFFF) + { + flash_add_base_addr (devNum, devBaseAddr); + devNum++; + } + } + mv_board_num_flash_banks = devNum; + + /* Update SPI flash count for CFI flash init driver */ + /* Assumption only 1 SPI flash on board */ + for (i = 0 ; i < CFG_MAX_FLASH_BANKS_DETECT; i++) + { + devBaseAddr = mvBoardGetDeviceBaseAddr(i,BOARD_DEV_SPI_FLASH); + if (devBaseAddr != 0xFFFFFFFF) + mv_board_num_flash_banks += 1; + } + + if (mvCtrlModelGet() == MV_6082_DEV_ID) + /* Add internal MFlash to NOR devices */ + mv_board_num_flash_banks += 1; + +} +#endif /* CFG_FLASH_CFI_DRIVER */ + +/******************************************************************************* +* mvStatusDebugLeds - +* +* DESCRIPTION: +* This function update the 7 segment or the debug/status LED +* +* +* INPUT: +* num - number to display over the 7 segment +* OUTPUT: +* +* RETURN: +* None +* +*******************************************************************************/ +static void mvStatusDebugLeds(char num) +{ + char* env; + + env = getenv("enaDebugLed"); + if(!env || ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + { + mvBoardStatusLed(MV_TRUE); + } + else + mvBoardDebug7Seg(num); +} + +/******************************************************************************* +* mvHddPowerCtrl - +* +* DESCRIPTION: +* This function set HDD power on/off acording to env or wait for button push +* INPUT: +* None +* OUTPUT: +* None +* RETURN: +* None +* +*******************************************************************************/ +#if defined(RD_88F6082NAS) || defined(RD_88F6082GE_SATA) || defined(RD_88F6082DAS_PLUS) || defined(RD_88F5182_3) +static void mvHddPowerCtrl(void) +{ + + MV_32 hddPowerBit = mvBoarGpioPinNumGet(BOARD_DEV_HDD0_POWER); + MV_32 extHddPowerBit = mvBoarGpioPinNumGet(BOARD_DEV_HDD1_POWER); + MV_32 hddBottenBit = mvBoarGpioPinNumGet(BOARD_DEV_POWER_BUTTON); + char* env; + + + if ((RD_88F6082_NAS == mvBoardIdGet()) || + (RD_88F5182_2XSATA3 == mvBoardIdGet())) + { + env = getenv("hddPowerCtrl"); + if(!env || ( (strcmp(env,"no") == 0) || (strcmp(env,"No") == 0) ) ) + setenv("hddPowerCtrl","no"); + else + setenv("hddPowerCtrl","yes"); + + /* #include "mvGpp.h" */ + /* GPIO / Leds / and Power button handling */ + + env = getenv("hddPowerCtrl"); + if(env && ( (strcmp(env,"yes") == 0) || (strcmp(env,"Yes") == 0) ) ) + { + /* Set HDD input indication pin as input */ + MV_REG_BIT_SET(GPP_DATA_OUT_EN_REG(0),(1< 5) break; + + }while (1); + + + /* Clear Interrupt cause */ + MV_REG_BIT_RESET(GPP_INT_CAUSE_REG(0),(1 << powerBottenBit)); + + /* Disable interrupt */ + MV_REG_BIT_RESET(GPP_INT_MASK_REG(0),(1 << powerBottenBit) ); + + + /* Call system power up */ + mv6082uDasNasSysPower(MV_TRUE); + } + } + else + { + /* U-boot is running after power-up */ + /* Check restor botten push */ + /* Set restor input indication pin as input */ + MV_REG_BIT_SET(GPP_DATA_OUT_EN_REG(0),(1< +#include "norflash/mvFlash.h" + +void memcpyFlash(env_t *env_ptr, void* buffer, MV_U32 size) +{ + MV_FLASH_INFO *pFlash; + pFlash = getMvFlashInfo(BOOT_FLASH_INDEX); + + mvFlashBlockRd(pFlash,(MV_U32 *)env_ptr - mvFlashBaseAddrGet(pFlash), + size, (MV_U8 *)buffer); +} +#endif diff --git a/board/mv_feroceon/mv_orion/mv_service.c b/board/mv_feroceon/mv_orion/mv_service.c new file mode 100644 index 0000000..b9fb2f6 --- /dev/null +++ b/board/mv_feroceon/mv_orion/mv_service.c @@ -0,0 +1,146 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mv_service.h" + +/*********************************************************** +* Init the PHY or Switch of the board * + ***********************************************************/ +MV_VOID mvEgigaPhySwitchInit(void) +{ + if (RD_88F6183_AP == mvBoardIdGet()) + { + mvEthE6161SwitchBasicInit(0); + } + else if ((DB_88F5181_5281_DDR2 == mvBoardIdGet())|| + (DB_88F5X81_DDR1 == mvBoardIdGet()) || + (DB_88F5181_DDR1_PEXPCI == mvBoardIdGet()) || + (RD_88F5181_POS_NAS == mvBoardIdGet()) || + (DB_88F5182_DDR2 == mvBoardIdGet())|| + (DB_88F5182_DDR2_A == mvBoardIdGet())|| + (DB_88F5082_DDR2 == mvBoardIdGet())|| + (RD_88F5182_2XSATA == mvBoardIdGet())|| + (DB_88F5181L_DDR2_2XTDM == mvBoardIdGet()) || + (DB_88F5180N_DDR1 == mvBoardIdGet()) || + (DB_88F5180N_DDR2 == mvBoardIdGet()) || + (DB_88W8660_DDR2 == mvBoardIdGet()) ) + { + mvEthE1111PhyBasicInit(0); + + }else if ((RD_88F5182_2XSATA3 == mvBoardIdGet()) || + (RD_88F5182_2XSATA == mvBoardIdGet()) || + (RD_88F5082_2XSATA == mvBoardIdGet()) || + (RD_88F5082_2XSATA3 == mvBoardIdGet()) || + (DB_88F5X81_DDR2 == mvBoardIdGet()) || + (RD_88F6183_GP == mvBoardIdGet()) || + (DB_88F6183_BP == mvBoardIdGet())) + { + /* 1118 is identical to 1116 */ + mvEthE1116PhyBasicInit(0); + + }else if (DB_88F5181_5281_DDR1 == mvBoardIdGet()) + { + mvEthE1011PhyBasicInit(0); + + }else if ((RD_88F5181_VOIP == mvBoardIdGet()) || (RD_88F5181L_VOIP_FE == mvBoardIdGet()) || + (RD_88F5181_GTW_FE == mvBoardIdGet())) + { + mvEthE6063SwitchBasicInit(0); + + }else if ((RD_88W8660_DDR1 == mvBoardIdGet()) || (RD_88W8660_AP82S_DDR1 == mvBoardIdGet())) + { + mvEthE6065_61SwitchBasicInit(0); + + }else if ( (RD_88F5181L_VOIP_GE == mvBoardIdGet()) || + (RD_88F5181_GTW_GE == mvBoardIdGet()) || + (RD_88F5181L_VOIP_FXO_GE == mvBoardIdGet())) + { + mvEthE6131SwitchBasicInit(0); + + }else if (RD_88F6082_MICRO_DAS_NAS == mvBoardIdGet()) + { + mvEthE1112PhyBasicInit(0); + } + else if ((DB_88F6082_BP == mvBoardIdGet()) || + (DB_88F6082L_BP == mvBoardIdGet())) + { + mvEthE1112PhyBasicInit(0); + mvEthE1112PhyBasicInit(1); + } + else if (RD_88F6082_DX243_24G == mvBoardIdGet()) + { + mvEthE1112PhyBasicInit(0); + mvEthE1111PhyBasicInit(1); + } + else if (RD_88F6082_NAS == mvBoardIdGet()) + { + /* Power down phy in case we enter power down mode */ + mvEthE1112PhyPowerDown(0); + mvEthE1112PhyPowerDown(1); + } + else if (RD_88F6183_AP == mvBoardIdGet()) + { + mvEthE6161SwitchBasicInit(0); + } +} diff --git a/board/mv_feroceon/mv_orion/mv_service.h b/board/mv_feroceon/mv_orion/mv_service.h new file mode 100644 index 0000000..dea8d11 --- /dev/null +++ b/board/mv_feroceon/mv_orion/mv_service.h @@ -0,0 +1,71 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "ethSwitch/mvSwitch.h" +#include "ethSwitch/mvSwitchRegs.h" +#include "eth-phy/mvEthPhy.h" +#include "mvCtrlEnvLib.h" + +MV_VOID mvEgigaPhySwitchInit(void); diff --git a/board/mv_feroceon/mv_orion/nBootstrap.S b/board/mv_feroceon/mv_orion/nBootstrap.S new file mode 100644 index 0000000..b6f2512 --- /dev/null +++ b/board/mv_feroceon/mv_orion/nBootstrap.S @@ -0,0 +1,411 @@ +#define MV_ASMLANGUAGE +#include "mvDramIfRegs.h" +#include "mvDramIfConfig.h" +#include "nBootstrap.h" + + +#if !defined(MV_BOOTROM) +.globl nbootStart +nbootStart: + /* + * set the cpu to SVC32 mode, I and F disabled. + */ + mov r1, #0xd3 + msr cpsr,r1 + + /* + * flush v4 I/D caches + */ + mcr p15, 0, r1, c7, c7, 0 /* invalidate v3/v4 cache */ + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r1, c1, c0, 0 + bic r1, r1, #0x00000300 /* clear bits 9:8 (--V- --RS) */ + bic r1, r1, #0x00000007 /* clear bits 2:0 (-CAM) */ + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Add nop commands for cache flush operations */ + nop + nop + nop + nop + nop + nop + + /* here. MUST BE IN THE SAME CACHE LINE */ + + mov r0, #0 /* We use r0 as always '0' */ + +#ifdef NAND_CTRL_88F528x + + /* Load CPU controller base address 0xD0020000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x20000 + + MV_REG_READ_ASM (r1, r2, 0x20120) + bic r1, r1, #MV_32BIT_LE(0x7F00) + orr r1, r1, #MV_32BIT_LE(0x8200) + bic r1, r1, #MV_32BIT_LE(0x007F) + orr r1, r1, #MV_32BIT_LE(0x001b) + MV_REG_WRITE_ASM(r1, r2, 0x20120) + + /* Set CPU to Mbus-L DDR Interface Tick Driver and Tick Sample */ + MV_REG_READ_ASM (r1, r2, 0x20100) + bic r1, r1, #MV_32BIT_LE(0xFF00) + orr r1, r1, #MV_32BIT_LE(CPU_2_MBUSL_DDR_CLK) + MV_REG_WRITE_ASM(r1, r2, 0x20100) + +#endif /* NAND_CTRL_88F528x */ + + + /* DRAM memory initialization */ + + /* Load SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + + /* Write to SDRAM coniguration register */ +#ifndef MV_88W8660 + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_CONFIG_REG_DV)) +#else + GPR_LOAD(r1, MV_32BIT_LE((SDRAM_CONFIG_REG_DV & ~(0x40)))) +#endif /* MV_88W8660 */ + MV_REG_WRITE_ASM(r1, r2, SDRAM_CONFIG_REG) + + /* Write Dunit control low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_DUNIT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_DUNIT_CTRL_REG) + + /* Write SDRAM address control register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_ADDR_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_ADDR_CTRL_REG) + + /* Write SDRAM timing Low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_LOW_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_LOW_REG) + + /* Write SDRAM timing High register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_HIGH_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_HIGH_REG) + + /* Write SDRAM mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_MODE_REG) + + /* Write SDRAM Extended mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_EXTENDED_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_EXTENDED_MODE_REG) + + /* Config DDR2 registers pad calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_CONFIG_REG) + tst r1, #SDRAM_DTYPE_DDR2 + beq ddr1PadCal + + /* Config DDR2 On Die Termination (ODT) registers */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_LOW_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_LOW_REG) + + /* Write SDRAM DDR2 ODT control high register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + + /* Write SDRAM DDR2 Dunit ODT control register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_DUNIT_ODT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_DUNIT_ODT_CONTROL_REG) + + mov r3, #MV_32BIT_LE(DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV) + mov r4, #MV_32BIT_LE(DDR2_DATA_PAD_STRENGTH_TYPICAL_DV) + b next + +ddr1PadCal: + mov r3, #MV_32BIT_LE(DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV) + mov r4, #MV_32BIT_LE(DDR1_DATA_PAD_STRENGTH_TYPICAL_DV) + +next: + /* Implement Guideline (GL# MEM-3) Drive Strength Value */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r5, r1, #MV_32BIT_LE(SDRAM_WR_EN) /* Make register writeable */ + + MV_REG_WRITE_ASM (r5, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r1, r3, r1 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r1, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_DATA_PADS_CAL_REG) + + orr r5, r1, #MV_32BIT_LE(SDRAM_WR_EN) /* Make register writeable */ + + MV_REG_WRITE_ASM (r5, r2, SDRAM_DATA_PADS_CAL_REG) + + orr r1, r4, r1 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r1, r2, SDRAM_DATA_PADS_CAL_REG) + +#ifndef MV_88W8660 + /* Write Dunit FTDLL Configuration Register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_FTDLL_CONFIG_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_FTDLL_CONFIG_REG) +#endif /* MV_88W8660 */ + + /* DDR SDRAM Initialization Control Register. Init enable */ + mov r1, #MV_32BIT_LE(DSICR_INIT_EN) + MV_REG_WRITE_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + +ddrInitLoop: + MV_REG_READ_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + cmp r1, #0 + bne ddrInitLoop + + /* Continue in next NAND page */ + + +/*****************************************************************************/ +/* This code open NAND page 1 for read and relocates the CPU to read */ +/* from that page. */ +/*****************************************************************************/ + + +/* r2 - is the page number */ +/* r5 - nand flash base */ +/* r6 - is cmd read */ +/* r0 - 0 */ +/* r9 - is cmd status */ +/* r4 - next address to jump */ + + /* Load the NAND base address */ + GPR_LOAD(r5, NAND_FLASH_BASE) + + /* init */ + mov r0, #0 + mov r2, #0x1 /* start with page 1 */ + mov r6, #CMD_READ + + mov r9, #CMD_STATUS + orr r4, r5, #0x200 + +.align 5 + b ncl +sop: + /* issue read command */ + strb r6, [r5, #NAND_CMD_PORT] + + /* issue address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r2, [r5, #NAND_ADDR_PORT] /* page address */ + strb r0, [r5, #NAND_ADDR_PORT] + + /* Check status */ + strb r9, [r5, #NAND_CMD_PORT] + b busy_loop + +.align 5 +ncl: + b ncl2 +busy_loop: + ldrb r1, [r5] + tst r1, #STATUS_READY + beq busy_loop + + /* back to read mode */ + strb r6, [r5, #NAND_CMD_PORT] + mov pc, r4 + +.align 5 +ncl2: + b sop + + +/* Next page must be in page offset - 512 bytes */ +.align 9 +page1: +/*****************************************************************************/ +/* This code extract the booter from the rest of block 1 which is known to */ +/* be error free (no need for ECC). This booter should copy the U-boot code */ +/* to DRAM */ +/*****************************************************************************/ + /* DRAM init - Cont'd */ + + /* Load back SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + /* Open SDRAM bank 0 size register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_SIZE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_SIZE_REG(0)) + + /* Close SDRAM bank 1,2,3 */ + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(1)) + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(2)) + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(3)) + + /* Prepare the address where to find the nandBoot function pointer */ + mov lr, #0x20000 + orr lr, lr, #0x600 + + /* Initialize UART 0 to 115200 bps */ + GPR_LOAD(r2, 0xd0012000) + mov r1, #0x07 + strb r1, [r2, #0x8] + + mov r1, #0x83 + strb r1, [r2, #0xC] + + mov r1, #0x5A + strb r1, [r2, #0x0] + + mov r1, #0x03 + strb r1, [r2, #0xC] + + mov r1, #'N' + strb r1, [r2] + mov r1, #'A' + strb r1, [r2] + mov r1, #'N' + strb r1, [r2] + mov r1, #'D' + strb r1, [r2] + mov r1, #' ' + strb r1, [r2] + mov r1, #'b' + strb r1, [r2] + mov r1, #'o' + strb r1, [r2] + mov r1, #'o' + strb r1, [r2] + mov r1, #'t' + strb r1, [r2] + mov r1, #'s' + strb r1, [r2] + mov r1, #'t' + strb r1, [r2] + mov r1, #'r' + strb r1, [r2] + mov r1, #'a' + strb r1, [r2] + mov r1, #'p' + strb r1, [r2] + mov r1, #10 + strb r1, [r2] + mov r1, #13 + strb r1, [r2] + + /* init */ + mov r2, #0x3 /* start with page 3 */ +// mov r3, #BOOTER_BASE /* start of DRAM buffer */ + mov r3, #0x20000 + orr r3, r3, #0x600 + +.align 5 + b ncl31 +sop1: + +cp_page_loop: + mov r0, #0 + mov r6, #CMD_READ + mov r9, #CMD_STATUS + mov r4, #PAGE_SIZE /* Byte counter */ + b startRead + +.align 5 +ncl31: + b ncl3 +startRead: + /* issue read command */ + strb r6, [r5, #NAND_CMD_PORT] + + /* issue address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r2, [r5, #NAND_ADDR_PORT] /* page address */ + strb r0, [r5, #NAND_ADDR_PORT] + + /* Check status */ + strb r9, [r5, #NAND_CMD_PORT] + b busy_loop1 + +.align 5 +ncl3: + b ncl4 + +busy_loop1: + ldrb r1, [r5] + tst r1, #STATUS_READY + beq busy_loop1 + + /* back to read mode */ + strb r6, [r5, #NAND_CMD_PORT] + + /* now perform reading */ + mov r0, r5 + b copy_loop1 + +.align 5 +ncl4: + b ncl5 + +copy_loop1: + sub r4, r4, #32 /* 8 dwords * 4 bytes */ + ldmia r0!, {r6-r13} + stmia r3!, {r6-r13} + + cmp r4, #0 /* check if we have read a full Page */ + bne copy_loop1 + b nextPage + +.align 5 +ncl5: + b ncl6 + +nextPage: + add r2, r2, #1 /* increment page number */ + cmp r2, #BOOTER_PAGE_NUM + bne cp_page_loop + b stack_setup + +.align 5 +ncl6: + b sop1 + + + /* Set up the stack */ +stack_setup: + sub sp, lr, #12 /* leave 3 words for abort-stack */ + + /* jump to new code */ + mov pc, lr + + +.align 9 + +/* This is known to be address (BOOTER_BASE + 2 * PAGE_SIZE) */ +_nandBootPtr: + .word nand_boot + +#else /* MV_BOOTROM */ + +.globl nbootStart +nbootStart: + /* Enable I-Cache */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Set up the stack */ + mov r0, #BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + + /* jump to new code */ + + ldr lr, =nand_boot + mov pc, lr +#endif /* !defined(MV_BOOTROM) */ diff --git a/board/mv_feroceon/mv_orion/nBootstrap.h b/board/mv_feroceon/mv_orion/nBootstrap.h new file mode 100644 index 0000000..c0fba78 --- /dev/null +++ b/board/mv_feroceon/mv_orion/nBootstrap.h @@ -0,0 +1,382 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCnBootstraph +#define __INCnBootstraph + +/* includes */ + +/* defines */ +#if defined(DB_88F6082BP) || defined(DB_88F6082LBP) || defined(DB_88F6082SA) || defined(DB_88W8660) ||\ + defined(RD_DB_88F5181L) || defined(DB_88F5182) || defined(DB_88F5082) || defined(DB_88F5181) ||\ + defined(DB_FPGA) || defined(DB_88F6183BP) || defined(DB_88F6183LBP) || defined(RD_88F6183GP) ||\ + defined(DB_88F5182_A) ||defined(DB_88F5181_OLD) +#define _DDR2 +#endif + +#if defined(RD_88F5181_GTWFE) || defined(RD_88F5181_GTWGE) || defined(RD_88F5182) || defined(DB_MNG)\ + || defined(RD_88F5082) || defined(RD_88F6183GP) +#define _DDR1 +#endif + +#if defined(MV_88F5281) +#define NAND_CTRL_88F528x /* NAND controller 88F528x */ +#endif /* defined(MV_88F5281) */ + +#if defined(RD_88W8660_AP82S) +#define RD_88W8660_AP82S +#endif + +#undef DEV_X8 +#undef DEV_DENS_256Mb +#define DEV_DENS_512Mb + +#if defined(RD_88W8660_AP82S) + +/* Shark RD */ +#define SDRAM_SIZE_REG_DV 0x00ff0001 +#define SDRAM_CONFIG_REG_DV 0x03144400 +#define SDRAM_MODE_REG_DV 0x62 +#define SDRAM_DUNIT_CTRL_REG_DV 0x4041000 +#define SDRAM_ADDR_CTRL_REG_DV 0x0 +#define SDRAM_TIMING_CTRL_LOW_REG_DVAL 0x11602220 +#define SDRAM_TIMING_CTRL_HIGH_REG_DVAL 0x40b +#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x0 +#define DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV 0x0 +#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x0 +#define SDRAM_EXTENDED_MODE_REG_DV 0x0 +#define SDRAM_OPEN_PAGE_CTRL_REG_DV 0x0 +#define SDRAM_FTDLL_CONFIG_REG_DV 0x0 + +#elif defined(RD_88W8660) + +/* Shark RD */ +#define SDRAM_SIZE_REG_DV 0x03ff0001 +#define SDRAM_CONFIG_REG_DV 0x03144400 +#define SDRAM_MODE_REG_DV 0x62 +#define SDRAM_DUNIT_CTRL_REG_DV 0x4041000 +#define SDRAM_ADDR_CTRL_REG_DV 0x10 +#define SDRAM_TIMING_CTRL_LOW_REG_DVAL 0x11602220 +#define SDRAM_TIMING_CTRL_HIGH_REG_DVAL 0x40b +#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x0 +#define DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV 0x0 +#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x0 +#define SDRAM_EXTENDED_MODE_REG_DV 0x0 +#define SDRAM_OPEN_PAGE_CTRL_REG_DV 0x0 +#define SDRAM_FTDLL_CONFIG_REG_DV 0x0 + +#elif defined(_DDR2) + +/* This is Uboot 1.6.4 dump of DB-88F5x81-DDR2-BP-A CPU @ 400 DDR @ 200 +with the DIMM: MT9HTF3272AY-53EB3 (256MB DDR2 533 CL4 ECC) LE mode Orion2 B0 + +f1001400: 7f258400 04041040 11812220 0000040e ..%.@... "...... +f1001410: 00000010 00000000 00000000 00000432 ............2... +f1001420: 00000440 00000000 00063305 00000003 @........3...... +f1001430: 76543210 fedcba98 000100ff 00000000 .2Tv............ +f1001440: 00000000 00000000 00000000 00000000 ................ +f1001450: 00000000 00000000 00000000 00000000 ................ +f1001460: 00000000 00000000 00000000 00000000 ................ +f1001470: 05699aa6 00000036 00000000 00006330 ..i.6.......0c.. +f1001480: 00000000 00f95001 00000102 00000001 .....P.......... +f1001490: 00000000 00010000 00000002 00000a01 ................ +f10014a0: 00000000 00000000 00000001 00000000 ................ +f10014b0: 00000000 00000000 00000000 00000000 ................ +f10014c0: 1965328a 1965328a 00000000 00000000 .2e..2e......... +f10014d0: 00000000 00000000 00000000 00000000 ................ +f10014e0: 0401a590 00000000 00000000 00000001 ................ +f10014f0: 00000000 00000000 00000000 00000000 ................ +*/ + +/* registers defaults values for a DB-88xxxxx-DDR2-BP with the DIMM: */ +/* M378T3354CZ3-CD5 0541 (256MB DDR2 533 1Rx16 CL4 ECC) */ + + +#ifndef MV_88W8660 +#ifdef DEV_X8 +#define SDRAM_CONFIG_REG_DV 0x03258400 /* 1400 */ +#else +#define SDRAM_CONFIG_REG_DV 0x03154400 /* 1400 */ +#endif /* DEV_X */ +#else +#ifdef DEV_X8 +#define SDRAM_CONFIG_REG_DV 0x03254400 /* 1400 */ +#else +#define SDRAM_CONFIG_REG_DV 0x03154400 /* 1400 */ +#endif /* DEV_X */ +#endif /* MV_88W8660 */ + +#define SDRAM_DUNIT_CTRL_REG_DV 0x04041040 /* 1404 */ +#define SDRAM_TIMING_CTRL_LOW_REG_DVAL 0x11712220 /* 1408 */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DVAL 0x00000104 /* 140C */ + +#ifdef DEV_DENS_256Mb +#define SDRAM_ADDR_CTRL_REG_DV 0x00000010 /* 1410 */ +#endif +#ifdef DEV_DENS_512Mb +#define SDRAM_ADDR_CTRL_REG_DV 0x00000020 /* 1410 */ +#endif + +#define SDRAM_OPEN_PAGE_CTRL_REG_DV 0x00000000 /* 1414 */ +#define SDRAM_MODE_REG_DV 0x00000432 /* 141C */ +#define SDRAM_EXTENDED_MODE_REG_DV 0x00000440 /* 1420 */ +#define SDRAM_FTDLL_CONFIG_REG_DV 0x00f95000 /* 1484 */ +#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x84210000 /* 1494 */ +#define DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV 0x00000000 /* 1498 */ +#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x0000780f /* 149C */ + +#if defined(MV_88F6183) || defined(MV_88F6183L) +#undef SDRAM_FTDLL_CONFIG_REG_DV +#define SDRAM_FTDLL_CONFIG_REG_DV 0 +#endif + +#if defined(MV_88W8660) || defined(MV_88F6183) defined(MV_88F6183L) +#define SDRAM_SIZE_REG_DV 0x03ff0001 /* 64MB */ +#else +#define SDRAM_SIZE_REG_DV 0x07ff0001 /* 128MB */ +#endif + + +#elif defined(_DDR1) + +/* This is Uboot 1.6.7 dump of DB-88F5281-DDR1-BP-A CPU @ 533 DDR @ 133 +with the DIMM: MT8VDDT1664AG-265A1 (128MB DDR1 266 CL2.5 no ECC) LE mode Orion2 B0 + +f1001400: 07248400 04041040 11501220 00000409 ..$.@... .P..... +f1001410: 00000000 00000000 00000000 00000062 ............b... +f1001420: 00000000 00000000 00063305 00000000 .........3...... +f1001430: 76543210 fedcba98 000100ff 00000000 .2Tv............ +f1001440: 00000000 00000000 00000000 00000000 ................ +f1001450: 00000000 00000000 00000000 00000000 ................ +f1001460: 00000000 00000000 00000000 00000000 ................ +f1001470: 06b4ea54 00000055 00000000 00006330 T...U.......0c.. +f1001480: 00000000 00e3f001 00000102 00000001 ................ +f1001490: 00000000 00000000 00000000 00000000 ................ +f10014a0: 00000000 00000000 00000001 00000000 ................ +f10014b0: 00000000 00000000 00000000 00000000 ................ +f10014c0: 14d21a69 14d21a69 00000000 00000000 i...i........... +f10014d0: 00000000 00000000 00000000 00000000 ................ +f10014e0: ba1d4858 00000000 00000000 0000000f XH.............. +f10014f0: 00000000 00000000 00000000 00000000 ................ +*/ +/* registers defaults values for DB-88F5281-DDR1-BP-A CPU @ 533 DDR @ 133 +with the DIMM: MT8VDDT1664AG-265A1 */ +#define SDRAM_CONFIG_REG_DV 0x07248400 /* 1400 */ +#define SDRAM_DUNIT_CTRL_REG_DV 0x04041040 /* 1404 */ +#define SDRAM_TIMING_CTRL_LOW_REG_DVAL 0x11501220 /* 1408 */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DVAL 0x00000409 /* 140C */ +#define SDRAM_ADDR_CTRL_REG_DV 0x00000000 /* 1410 */ +#define SDRAM_OPEN_PAGE_CTRL_REG_DV 0x00000000 /* 1414 */ +#define SDRAM_MODE_REG_DV 0x00000062 /* 141C */ +#define SDRAM_EXTENDED_MODE_REG_DV 0x00000000 /* 1420 */ +#define SDRAM_FTDLL_CONFIG_REG_DV 0x00e3f001 /* 1484 */ +#define DDR2_SDRAM_ODT_CTRL_LOW_REG_DV 0x00000000 /* 1494 */ +#define DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV 0x00000000 /* 1498 */ +#define DDR2_DUNIT_ODT_CTRL_REG_DV 0x00000000 /* 149C */ +#define SDRAM_SIZE_REG_DV 0x03ff0001 /* 64MB */ +#endif + +/* NAND Flash access */ +#define NAND_CMD_PORT (0x1 << (NFLASH_DEV_WIDTH >> 4)) +#define NAND_ADDR_PORT (0x2 << (NFLASH_DEV_WIDTH >> 4)) + +/* NAND Flash Chip Capability */ +#ifdef MV_LARGE_PAGE +#define NUM_BLOCKS 2048 +#define PAGES_PER_BLOCK 64 +#define PAGE_SIZE 2048 /* Bytes */ +#define SPARE_SIZE 64 +#define CFG_NAND_PAGE_SIZE (2048) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (64) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (0) /* Location of bad block marker */ + +#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ + +#else /* ! LARGE PAGE NAND */ +/* NAND Flash Chip Capability */ +#define NUM_BLOCKS 2048 +#define PAGES_PER_BLOCK 32 +#define PAGE_SIZE 512 /* Bytes */ +#define SPARE_SIZE 16 +#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */ + +#define CFG_NAND_U_BOOT_OFFS CFG_MONITOR_BASE /* Offset to U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE CFG_MONITOR_LEN /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_DST CFG_MONITOR_IMAGE_DST /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ + +#endif + +/* NAND Flash Command. This appears to be generic across all NAND flash chips */ +#define CMD_READ 0x00 /* Read */ +#define CMD_READ1 0x01 /* Read1 */ +#define CMD_READ2 0x50 /* Read2 */ +#define CMD_START_READ 0x30 /* Read command after write addr */ +#define CMD_READID 0x90 /* ReadID */ +#define CMD_READID2 0x91 /* Read extended ID */ +#define CMD_WRITE 0x80 /* Write phase 1 */ +#define CMD_WRITE2 0x10 /* Write phase 2 */ +#define CMD_ERASE 0x60 /* Erase phase 1 */ +#define CMD_ERASE2 0xd0 /* Erase phase 2 */ +#define CMD_STATUS 0x70 /* Status read */ +#define CMD_RESET 0xff /* Reset */ + +/* Status bit pattern */ +#define STATUS_READY 0x40 /* Ready */ +#define STATUS_ERROR 0x01 /* Error */ + + +#define NFLASH_DEV_WIDTH 8 +#ifdef MV_LARGE_PAGE +#define BOOTER_PAGE_NUM 2 +#define BOOTER_BASE 0x00020000 + PAGE_SIZE +#else +#define BOOTER_PAGE_NUM 5 +#define BOOTER_BASE 0x00020000 + (3 * PAGE_SIZE) +#endif /* MV_LARGE_PAGE */ +#define BOOTER_END (BOOTER_BASE + (BOOTER_PAGE_NUM * PAGE_SIZE)) + +#undef INTER_REGS_BASE +#define INTER_REGS_BASE 0xd0000000 + + +#if defined(MV_BOOTROM) +#if defined(MV_88F6082) +#define NAND_FLASH_BASE 0xD8000000 +#endif +#if defined(MV_88F5182) +#define NAND_FLASH_BASE 0xf0000000 +#endif +#else +#define NAND_FLASH_BASE 0xffff0000 +#endif /* defined(MV_BOOTROM) */ + +#if 0 +#if defined(MV_BOOTROM) +#define UBOOT_IMAGE_OFFS 0x4000 /* Uboot starts on block 1 */ +#define UBOOT_IMAGE_SIZE 0x80000 /* 1/2 MB of Uboot */ +#define UBOOT_IMAGE_DEST 0x200000 +#define UBOOT_IMAGE_ENV_OFFS 0x84000 /* Uboot starts on block 1 */ +#define UBOOT_IMAGE_ENV_SIZE 0x4000 +#define UBOOT_IMAGE_ENV_DEST 0x300000 - UBOOT_IMAGE_ENV_SIZE +#else +#define UBOOT_IMAGE_OFFS 0x24000 /* Uboot starts on block 1 */ +#define UBOOT_IMAGE_SIZE 0x80000 /* 1/2 MB of Uboot */ +#define UBOOT_IMAGE_DEST 0x200000 +#define UBOOT_IMAGE_ENV_OFFS UBOOT_IMAGE_OFFS - 0x20000 /* Uboot starts on block 1 */ +#define UBOOT_IMAGE_ENV_SIZE 0x4000 +#define UBOOT_IMAGE_ENV_DEST 0x300000 - UBOOT_IMAGE_ENV_SIZE +#endif /* defined(MV_BOOTROM) */ +#endif + +#define NBOOT_UART_CHAN 0 +#define NBOOT_BAUDRATE 115200 +#define NBOOT_TIMER_NUM 0 + + +/* CPU config register (0x20100) bit[15:8] value for CPU to DDR clock ratio */ +#define CPU_2_MBUSL_DDR_CLK 0x0000 /* clock ratio 1x2 */ +/* #define CPU_2_MBUSL_DDR_CLK 0x2100 *//* clock ratio 1x3 */ +/* #define CPU_2_MBUSL_DDR_CLK 0x2200 *//* clock ratio 1x4 */ + +/* Load General Purpose Register (GPR) with 32-bit constant value */ +#define GPR_LOAD(reg, val) \ + mov reg, $(val & 0xFF) ;\ + orr reg, reg, $(val & 0xFF00) ;\ + orr reg, reg, $(val & 0xFF0000) ;\ + orr reg, reg, $(val & 0xFF000000) + +/* Register Read/Write */ +#define MV_REG_READ_ASM(toReg, baseReg, regOffs) \ + ldr toReg, [baseReg, $(regOffs & 0xFFF)] + +#define MV_REG_WRITE_ASM(fromReg, baseReg, regOffs) \ + str fromReg, [baseReg, $(regOffs & 0xFFF)] + + +/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ +#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ + (((X)&0xff00)<<8) | \ + (((X)&0xff0000)>>8) | \ + (((X)&0xff000000)>>24)) +/* Endianess macros. */ +#if defined(MV_CPU_LE) + #define MV_32BIT_LE(X) (X) + #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) +#elif defined(MV_CPU_BE) + #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) + #define MV_32BIT_BE(X) (X) +#else + #error "CPU endianess isn't defined!\n" +#endif + +#endif /* __INCnBootstraph */ diff --git a/board/mv_feroceon/mv_orion/nBootstrap_LP.S b/board/mv_feroceon/mv_orion/nBootstrap_LP.S new file mode 100644 index 0000000..1769e95 --- /dev/null +++ b/board/mv_feroceon/mv_orion/nBootstrap_LP.S @@ -0,0 +1,335 @@ +#define MV_ASMLANGUAGE +#include "mvDramIfRegs.h" +#include "mvDramIfConfig.h" +#include "nBootstrap.h" + + +/* #define NAND_DEBUG */ +#if !defined(MV_BOOTROM) +.globl nbootStart +nbootStart: + /* + * set the cpu to SVC32 mode, I and F disabled. + */ + mov r1, #0xd3 + msr cpsr,r1 + + /* + * flush v4 I/D caches + */ + mcr p15, 0, r1, c7, c7, 0 /* invalidate v3/v4 cache */ + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r1, c1, c0, 0 + bic r1, r1, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r1, r1, #0x00000007 /* clear bits 2:0 (-CAM) */ + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Add nop commands for cache flush operations */ + nop + nop + nop + nop + nop + /* here. MUST BE IN THE SAME CACHE LINE */ + + mov r0, #0 /* We use r0 as always '0' */ + +#ifdef NAND_CTRL_88F528x + + /* Load CPU controller base address 0xD0020000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x20000 + + MV_REG_READ_ASM (r1, r2, 0x20120) + bic r1, r1, #MV_32BIT_LE(0x7F00) + orr r1, r1, #MV_32BIT_LE(0x8200) + bic r1, r1, #MV_32BIT_LE(0x007F) + orr r1, r1, #MV_32BIT_LE(0x001b) + MV_REG_WRITE_ASM(r1, r2, 0x20120) + + /* Set CPU to Mbus-L DDR Interface Tick Driver and Tick Sample */ + MV_REG_READ_ASM (r1, r2, 0x20100) + bic r1, r1, #MV_32BIT_LE(0xFF00) + orr r1, r1, #MV_32BIT_LE(CPU_2_MBUSL_DDR_CLK) + MV_REG_WRITE_ASM(r1, r2, 0x20100) + +#endif /* NAND_CTRL_88F528x */ + + /* lock I-Cache */ + mrc p15, 0, r8, c9, c0, 1 + orr r8, r8, #0xf + mcr p15, 0, r8, c9, c0, 1 + + /* Start load code into I-Cache */ + mov r2, #0x500 + mov r8, pc +.align 5 + bic r8, #0x1f + add r8, r8, #32 +load_loop: + mcr p15, 0, r8, c7, c13, 1 + add r8, r8, #32 /* 8 dwords * 4 bytes */ + sub r2, r2, #32 /* 8 dwords * 4 bytes */ + cmp r2, #0 /* check if we have read a full Page */ + bne load_loop + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0xf0ffffff + MV_REG_WRITE_ASM(r1, r2, 0x104) + mov r1, #0x1000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + + /* DRAM memory initialization */ + /* Load SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + /* Write to SDRAM coniguration register */ +#ifndef MV_88W8660 + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_CONFIG_REG_DV)) +#else + GPR_LOAD(r1, MV_32BIT_LE((SDRAM_CONFIG_REG_DV & ~(0x40)))) +#endif /* MV_88W8660 */ + MV_REG_WRITE_ASM(r1, r2, SDRAM_CONFIG_REG) + + /* Write Dunit control low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_DUNIT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_DUNIT_CTRL_REG) + + /* Write SDRAM address control register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_ADDR_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_ADDR_CTRL_REG) + + /* Write SDRAM timing Low register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_LOW_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_LOW_REG) + + /* Write SDRAM timing High register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_TIMING_CTRL_HIGH_REG_DVAL)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_TIMING_CTRL_HIGH_REG) + + /* Write SDRAM mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_MODE_REG) + + /* Write SDRAM Extended mode register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_EXTENDED_MODE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_EXTENDED_MODE_REG) + + /* Config DDR2 registers pad calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_CONFIG_REG) + tst r1, #SDRAM_DTYPE_DDR2 + beq ddr1PadCal + + /* Config DDR2 On Die Termination (ODT) registers */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_LOW_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_LOW_REG) + + /* Write SDRAM DDR2 ODT control high register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_SDRAM_ODT_CTRL_HIGH_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + + /* Write SDRAM DDR2 Dunit ODT control register */ + GPR_LOAD(r1, MV_32BIT_LE(DDR2_DUNIT_ODT_CTRL_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, DDR2_DUNIT_ODT_CONTROL_REG) + + mov r3, #MV_32BIT_LE(DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV) + mov r4, #MV_32BIT_LE(DDR2_DATA_PAD_STRENGTH_TYPICAL_DV) + b next + +ddr1PadCal: + mov r3, #MV_32BIT_LE(DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV) + mov r4, #MV_32BIT_LE(DDR1_DATA_PAD_STRENGTH_TYPICAL_DV) + +next: + /* Implement Guideline (GL# MEM-3) Drive Strength Value */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r5, r1, #MV_32BIT_LE(SDRAM_WR_EN) /* Make register writeable */ + + MV_REG_WRITE_ASM (r5, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r1, r3, r1 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r1, r2, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r1, r2, SDRAM_DATA_PADS_CAL_REG) + + orr r5, r1, #MV_32BIT_LE(SDRAM_WR_EN) /* Make register writeable */ + + MV_REG_WRITE_ASM (r5, r2, SDRAM_DATA_PADS_CAL_REG) + + orr r1, r4, r1 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r1, r2, SDRAM_DATA_PADS_CAL_REG) + +#ifndef MV_88W8660 + /* Write Dunit FTDLL Configuration Register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_FTDLL_CONFIG_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_FTDLL_CONFIG_REG) +#endif /* MV_88W8660 */ + + /* DDR SDRAM Initialization Control Register. Init enable */ + mov r1, #MV_32BIT_LE(DSICR_INIT_EN) + MV_REG_WRITE_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x2000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + +ddrInitLoop: + MV_REG_READ_ASM (r1, r2, DDR_SDRAM_INIT_CTRL_REG) + cmp r1, #0 + bne ddrInitLoop + + /* Load back SDRAM controller base address 0xd0001000 */ + mov r2, #0xd0000000 + orr r2, r2, #0x1000 + + /* Open SDRAM bank 0 size register */ + GPR_LOAD(r1, MV_32BIT_LE(SDRAM_SIZE_REG_DV)) + MV_REG_WRITE_ASM(r1, r2, SDRAM_SIZE_REG(0)) + + /* Close SDRAM bank 1,2,3 */ + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(1)) + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(2)) + MV_REG_WRITE_ASM(r0, r2, SDRAM_SIZE_REG(3)) + + /* Prepare the address where to find the nandBoot function pointer */ + mov lr, #BOOTER_BASE + +#ifdef DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x2000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + + /* init */ + mov r2, #0x1 /* start with page 1 */ + mov r3, #BOOTER_BASE /* start of DRAM buffer */ + GPR_LOAD(r5, NAND_FLASH_BASE) + +cp_page_loop: + mov r0, #0 + mov r6, #CMD_READ + mov r7, #CMD_START_READ + mov r9, #CMD_RESET + mov r4, #PAGE_SIZE /* Byte counter */ + + +startRead: + /* issue reset command */ + strb r9, [r5, #NAND_CMD_PORT] + + mov r9, #0x1000000 +loop_delay1: + sub r9, r9, #1 + cmp r9, #0 + bne loop_delay1 + + /* issue read command */ + strb r6, [r5, #NAND_CMD_PORT] + + /* issue address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r0, [r5, #NAND_ADDR_PORT] + strb r2, [r5, #NAND_ADDR_PORT] /* page address */ + strb r0, [r5, #NAND_ADDR_PORT] + strb r0, [r5, #NAND_ADDR_PORT] + strb r7, [r5, #NAND_CMD_PORT] + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r6, #0xd0000000 + orr r6, r6, #0x10000 + mov r1, #0x3000000 + MV_REG_WRITE_ASM(r1, r6, 0x100) +#endif + /* Delay of at least 25uSec (NAND flash tR) */ + mov r9, #0x1000000 +loop_delay3: + sub r9, r9, #1 + cmp r9, #0 + bne loop_delay3 + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r6, #0xd0000000 + orr r6, r6, #0x10000 + mov r1, #0x4000000 + MV_REG_WRITE_ASM(r1, r6, 0x100) +#endif + + /* now perform reading */ + mov r0, r5 + +copy_loop1: + sub r4, r4, #16 /* 4 dwords * 4 bytes */ + ldmia r0!, {r6-r9} + stmia r3!, {r6-r9} + + cmp r4, #0 /* check if we have read a full Page */ + bne copy_loop1 + +nextPage: + add r2, r2, #1 /* increment page number */ + cmp r2, #BOOTER_PAGE_NUM + bne cp_page_loop + +#ifdef NAND_DEBUG + /* GPP initialization */ + mov r2, #0xd0000000 + orr r2, r2, #0x10000 + mov r1, #0x5000000 + MV_REG_WRITE_ASM(r1, r2, 0x100) +#endif + + /* Set up the stack */ +stack_setup: + mov r0, #BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + /* jump to new code */ + mov pc, lr + +.align 10 +/* This is known to be address (BOOTER_BASE + 2 * PAGE_SIZE) */ +_nandBootPtr: + .word nand_boot + +#else /* MV_BOOTROM */ + +.globl nbootStart +nbootStart: + /* Enable I-Cache */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #0x00001000 /* set bit 12 (I) I-Cache */ + /* MUST BE PLACED AT END OF CACHE LINE!!!!!!!!!!!!!!! */ + mcr p15, 0, r1, c1, c0, 0 + + /* Set up the stack */ + mov r0, #BOOTER_BASE + sub sp, r0, #12 /* leave 3 words for abort-stack */ + + /* jump to new code */ + + ldr lr, =nandBoot + mov pc, lr +#endif /* !defined(MV_BOOTROM) */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F1281BoardEnv.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F1281BoardEnv.c new file mode 100644 index 0000000..a013cb8 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F1281BoardEnv.c @@ -0,0 +1,132 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#define DB_88F1281_BOARD_PCI_IF_NUM 0x0 +#define DB_88F1281_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F1281_BOARD_MAC_INFO_NUM 0x0 +#define DB_88F1281_BOARD_GPP_INFO_NUM 0x1 +#define DB_88F1281_BOARD_DEBUG_LED_NUM 0x4 +#define DB_88F1281_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F1281_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_U8 db88f1281ddr2InfoBoardDebugLedIf[DB_88F1281_BOARD_DEBUG_LED_NUM] = + {2, 3, 6, 7}; + +MV_BOARD_TWSI_INFO db88f1281ddr2InfoBoardTwsiDev[DB_88F1281_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_GPP_INFO db88f1281ddr2InfoBoardGppInfo[DB_88F1281_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 1}}; + +MV_BOARD_MPP_INFO db88f1281ddr2InfoBoardMppConfigValue[DB_88F1281_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F1281_DDR2_MPP0_7, /* mpp0_7 */ + DB_88F1281_DDR2_MPP8_15, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}} /* mppDev */ + }; + +#if defined(MV_NAND) +MV_DEV_CS_INFO db88f1281ddr2InfoBoardDeCsInfo[DB_88F1281_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{ 0, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}, /* devCs2/NandCs */ + { 1, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ +#else +MV_DEV_CS_INFO db88f1281ddr2InfoBoardDeCsInfo[DB_88F1281_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{ 0, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}, /* devCs2/flashCs */ + { 1, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ +#endif /* defined(MV_NAND) */ + +MV_BOARD_INFO db88f1281ddr2Info = { + "DB-88F1281-DDR2", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F1281_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f1281ddr2InfoBoardMppConfigValue, + ((1 << 1)), /* intsGppMask */ + DB_88F1281_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f1281ddr2InfoBoardDeCsInfo, + DB_88F1281_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + DB_88F1281_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f1281ddr2InfoBoardTwsiDev, + DB_88F1281_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + NULL, + DB_88F1281_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f1281ddr2InfoBoardGppInfo, + DB_88F1281_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + db88f1281ddr2InfoBoardDebugLedIf, + N_A, /* ledsPolarity */ + DB_88F1281_DDR2_OE, /* gppOutEnVal */ + DB_88F1281_DDR2_OE_VAL, /* gppOutVal */ + 0x1 /* gppPolarityVal */ +}; + + +MV_BOARD_INFO* boardInfoTbl[1] = {&db88f1281ddr2Info, + }; + + +#define BOARD_ID_BASE BOARD_ID_88F1281_BASE +#define MV_MAX_BOARD_ID BOARD_ID_88F1281_MAX diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F1281BoardEnv.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F1281BoardEnv.h new file mode 100644 index 0000000..28c0e80 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F1281BoardEnv.h @@ -0,0 +1,85 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoard88F1281EnvSpech +#define __INCmvBoard88F1281EnvSpech + + +/* 88F1281 based boards ID numbers */ +/* =============================== */ +#define BOARD_ID_88F1281_BASE 0x60 + +/* New board ID numbers */ +#define DB_88F1281_DDR2 (BOARD_ID_88F1281_BASE+0x0) +#define BOARD_ID_88F1281_MAX (BOARD_ID_88F1281_BASE+0x1) + + + +#define DB_88F1281_DDR2_MPP0_7 0x00110011 +#define DB_88F1281_DDR2_MPP8_15 0x11111111 +#define DB_88F1281_DDR2_OE 0xFFFFFF33 +#define DB_88F1281_DDR2_OE_VAL 0x0 + +#endif /* __INCmvBoard88F1281EnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5082BoardEnv.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5082BoardEnv.c new file mode 100644 index 0000000..372b6bd --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5082BoardEnv.c @@ -0,0 +1,272 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#define DB_88F5082_BOARD_PCI_IF_NUM 0x0 +#define DB_88F5082_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F5082_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F5082_BOARD_GPP_INFO_NUM 0x4 +#define DB_88F5082_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88F5082_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F5082_BOARD_DEVICE_CONFIG_NUM 0x4 + +MV_BOARD_TWSI_INFO db88f5082ddr2InfoBoardTwsiDev[DB_88F5082_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5082ddr2InfoBoardMacInfo[DB_88F5082_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO db88f5082ddr2InfoBoardGppInfo[DB_88F5082_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 10}, + {BOARD_DEV_USB_VBUS, 8}, + {BOARD_DEV_USB_VBUS, 9}, + {BOARD_DEV_REF_CLCK, 11}}; + +MV_BOARD_MPP_INFO db88f5082ddr2InfoBoardMppConfigValue[DB_88F5082_BOARD_MPP_CONFIG_NUM] = +#ifndef MV_NAND_BOOT + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F5082_DDR2_MPP0_7, /* mpp0_7 */ + DB_88F5082_DDR2_MPP8_15, /* mpp8_15 */ + DB_88F5082_DDR2_MPP16_23, /* mpp16_23 */ + N_A}} /* mppDev */ + }; +#else + {{DB_88F5082_DDR2_MPP0_7NB, /* mpp0_7 */ + DB_88F5082_DDR2_MPP8_15NB, /* mpp8_15 */ + DB_88F5082_DDR2_MPP16_23NB, /* mpp16_23 */ + N_A}} /* mppDev */ + }; +#endif + +MV_DEV_CS_INFO db88f5082ddr2InfoBoardDeCsInfo[DB_88F5082_BOARD_DEVICE_CONFIG_NUM] = +#ifndef MV_NAND_BOOT + /*{params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs0 */ + { 1, 0x8fdfffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + { 2, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}, /* devCs2/flashCs */ + { 3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ +#else + /*{params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs0 */ + { 1, 0x8fdfffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + { 2, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}, /* devCs2/flashCs */ + { 3, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}}; /* bootCs */ +#endif + +MV_BOARD_INFO db88f5082ddr2Info = { + "DB-88F5082-DDR2", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5082_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5082ddr2InfoBoardMppConfigValue, + (1<<10), /* intsGppMask */ + DB_88F5082_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5082ddr2InfoBoardDeCsInfo, + DB_88F5082_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + DB_88F5082_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5082ddr2InfoBoardTwsiDev, + DB_88F5082_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5082ddr2InfoBoardMacInfo, + DB_88F5082_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5082ddr2InfoBoardGppInfo, + DB_88F5082_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + DB_88F5082_DDR2_OE, /* gppOutEn */ + DB_88F5082_DDR2_OE_VAL, /* gppOutVal */ + 0x403, /* gppPolarityVal */ +}; + + + +#define RD_88F5082_2XSATA_BOARD_PCI_IF_NUM 0x0 +#define RD_88F5082_2XSATA_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F5082_2XSATA_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F5082_2XSATA_BOARD_GPP_INFO_NUM 0x1 +#define RD_88F5082_2XSATA_BOARD_DEBUG_LED_NUM 0x1 +#define RD_88F5082_2XSATA_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F5082_2XSATA_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_U8 rd88f5082sataX2InfoBoardDebugLedIf[RD_88F5082_2XSATA_BOARD_DEBUG_LED_NUM] = + {0}; + +MV_BOARD_TWSI_INFO rd88f5082sataX2InfoBoardTwsiDev[RD_88F5082_2XSATA_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f5082sataX2InfoBoardMacInfo[RD_88F5082_2XSATA_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO rd88f5082sataX2InfoBoardGppInfo[RD_88F5082_2XSATA_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 3}}; + +MV_BOARD_MPP_INFO rd88f5082sataX2InfoBoardMppConfigValue[RD_88F5082_2XSATA_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5082_2XSATA_MPP0_7, /* mpp0_7 */ + RD_88F5082_2XSATA_MPP8_15, /* mpp8_15 */ + RD_88F5082_2XSATA_MPP16_23, /* mpp16_23 */ + N_A}} /* mppDev */ + }; + +MV_DEV_CS_INFO rd88f5082sataX2InfoBoardDeCsInfo[RD_88F5082_2XSATA_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{ 1, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}, /* devCs1 */ + { 3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88f5082sataX2Info = { + "RD-88F5082-NAS-2", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F5082_2XSATA_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5082sataX2InfoBoardMppConfigValue, + ((1<<3)|(1 << 6)|(1<<7)), /* intsGppMask */ + RD_88F5082_2XSATA_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5082sataX2InfoBoardDeCsInfo, + RD_88F5082_2XSATA_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + RD_88F5082_2XSATA_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f5082sataX2InfoBoardTwsiDev, + RD_88F5082_2XSATA_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5082sataX2InfoBoardMacInfo, + RD_88F5082_2XSATA_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f5082sataX2InfoBoardGppInfo, + RD_88F5082_2XSATA_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5082sataX2InfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F5082_2XSATA_OE, /* gppOutEnVal */ + RD_88F5082_2XSATA_VAL, /* gppOutVal */ + RD_88F5082_2XSATA_POL, /* gppPolarityVal */ +}; + + + +#define RD_88F5082_2XSATA3_BOARD_PCI_IF_NUM 0x0 +#define RD_88F5082_2XSATA3_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F5082_2XSATA3_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F5082_2XSATA3_BOARD_GPP_INFO_NUM 0x1 +#define RD_88F5082_2XSATA3_BOARD_DEBUG_LED_NUM 0x2 +#define RD_88F5082_2XSATA3_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F5082_2XSATA3_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_U8 rd88f5082sataX23InfoBoardDebugLedIf[RD_88F5082_2XSATA3_BOARD_DEBUG_LED_NUM] = + {0, 7}; + +MV_BOARD_TWSI_INFO rd88f5082sataX23InfoBoardTwsiDev[RD_88F5082_2XSATA3_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f5082sataX23InfoBoardMacInfo[RD_88F5082_2XSATA3_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO rd88f5082sataX23InfoBoardGppInfo[RD_88F5082_2XSATA3_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 3}}; + +MV_BOARD_MPP_INFO rd88f5082sataX23InfoBoardMppConfigValue[RD_88F5082_2XSATA3_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5082_2XSATA3_MPP0_7, /* mpp0_7 */ + RD_88F5082_2XSATA3_MPP8_15, /* mpp8_15 */ + RD_88F5082_2XSATA3_MPP16_23, /* mpp16_23 */ + N_A}} /* mppDev */ + }; + +MV_DEV_CS_INFO rd88f5082sataX23InfoBoardDeCsInfo[RD_88F5082_2XSATA3_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{ 1, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}, /* devCs1 */ + { 3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88f5082sataX23Info = { + "RD-88F5082-NAS-3", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F5082_2XSATA3_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5082sataX23InfoBoardMppConfigValue, + ((1<<3)|(1 << 6)|(1<<7)), /* intsGppMask */ + RD_88F5082_2XSATA3_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5082sataX23InfoBoardDeCsInfo, + RD_88F5082_2XSATA3_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + RD_88F5082_2XSATA3_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f5082sataX23InfoBoardTwsiDev, + RD_88F5082_2XSATA3_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5082sataX23InfoBoardMacInfo, + RD_88F5082_2XSATA3_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f5082sataX23InfoBoardGppInfo, + RD_88F5082_2XSATA3_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5082sataX23InfoBoardDebugLedIf, + 1, /* ledsPolarity */ + RD_88F5082_2XSATA3_OE, /* gppOutEn */ + RD_88F5082_2XSATA3_VAL, /* gppOutVal */ + N_A, /* gppPolarityVal */ +}; + + +MV_BOARD_INFO* boardInfoTbl[3] = {&db88f5082ddr2Info, + &rd88f5082sataX2Info, + &rd88f5082sataX23Info + }; + +#define BOARD_ID_BASE BOARD_ID_88F5082_BASE +#define MV_MAX_BOARD_ID BOARD_ID_88F5082_MAX diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5082BoardEnv.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5082BoardEnv.h new file mode 100644 index 0000000..f479cec --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5082BoardEnv.h @@ -0,0 +1,112 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoard88F5082EnvSpech +#define __INCmvBoard88F5082EnvSpech + + +/* 88F5082 based boards ID numbers */ +/* =============================== */ +#define BOARD_ID_88F5082_BASE 0x80 + +/* Old board ID numbers for backward compatability */ +#define DB_88F5082_DDR2_OLD 0xA +#define RD_88F5082_2XSATA_OLD 0xB +#define RD_88F5082_2XSATA3_OLD 0xF + +/* New board ID numbers */ +#define DB_88F5082_DDR2 (BOARD_ID_88F5082_BASE+0x0) +#define RD_88F5082_2XSATA (BOARD_ID_88F5082_BASE+0x1) +#define RD_88F5082_2XSATA3 (BOARD_ID_88F5082_BASE+0x2) + +#define BOARD_ID_88F5082_MAX (BOARD_ID_88F5082_BASE+0x3) + + + +#define DB_88F5082_DDR2_MPP0_7 0x55222203 +#define DB_88F5082_DDR2_MPP8_15 0x44550000 +#define DB_88F5082_DDR2_MPP16_23 0x0 + +#define DB_88F5082_DDR2_MPP0_7NB 0x55442203 +#define DB_88F5082_DDR2_MPP8_15NB 0x00050000 +#define DB_88F5082_DDR2_MPP16_23NB 0x0 + +#define DB_88F5082_DDR2_OE 0xFFF5FFD7 +#define DB_88F5082_DDR2_OE_VAL 0x0 + +#define RD_88F5082_2XSATA_MPP0_7 0x00000003 +#define RD_88F5082_2XSATA_MPP8_15 0x55550000 +#define RD_88F5082_2XSATA_MPP16_23 0x5555 +#define RD_88F5082_2XSATA_OE 0xFFF0F0C8 +#define RD_88F5082_2XSATA_VAL 0x402 +#define RD_88F5082_2XSATA_POL 0xC8 + +#define RD_88F5082_2XSATA3_MPP0_7 0x00000003 +#define RD_88F5082_2XSATA3_MPP8_15 0x05050000 +#define RD_88F5082_2XSATA3_MPP16_23 0x5555 +#define RD_88F5082_2XSATA3_OE 0xFFCF0EF8 +#define RD_88F5082_2XSATA3_VAL 0x402 + +#endif /* __INCmvBoard88F5082EnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5180NBoardEnv.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5180NBoardEnv.c new file mode 100644 index 0000000..8a52097 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5180NBoardEnv.c @@ -0,0 +1,161 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#define DB_88F5180N_BOARD_PCI_IF_NUM 0x3 +#define DB_88F5180N_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F5180N_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F5180N_BOARD_GPP_INFO_NUM 0x3 +#define DB_88F5180N_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88F5180N_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F5180N_BOARD_DEVICE_CONFIG_NUM 0x4 + +MV_BOARD_PCI_IF db88f5180NddrxInfoBoardPciIf[DB_88F5180N_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {12, 12, 12, 12}}, /* pciSlot0 */ + {8, {13, 13, 13, 13}}, /* pciSlot1 */ + {9, {13, 13, 13, 13}}}; /* pciSlot2 */ + +MV_BOARD_TWSI_INFO db88f5180NddrxInfoBoardTwsiDev[DB_88F5180N_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5180NddrxInfoBoardMacInfo[DB_88F5180N_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO db88f5180NddrxInfoBoardGppInfo[DB_88F5180N_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 10}, + {BOARD_DEV_USB_VBUS, 1}, + {BOARD_DEV_REF_CLCK,11}}; + +MV_BOARD_MPP_INFO db88f5180NddrxInfoBoardMppConfigValue[DB_88F5180N_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F5180N_DDRX_MPP0_7, /* mpp0_7 */ + DB_88F5180N_DDRX_MPP8_15, /* mpp8_15 */ + DB_88F5180N_DDRX_MPP16_23, /* mpp16_23 */ + DB_88F5180N_DDRX_MPP_DEV}} /* mppDev */ + }; + +MV_DEV_CS_INFO db88f5180NddrxInfoBoardDeCsInfo[DB_88F5180N_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs0 */ + { 1, 0x8fefffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + { 2, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}, /* devCs2/flashCs */ + { 3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO db88f5180Nddr2Info = { + "DB-88F5180N-DDR2-A", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5180N_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5180NddrxInfoBoardMppConfigValue, + ((1<<10)|(1 << 12)|(1<<13)), /* intsGppMask */ + DB_88F5180N_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5180NddrxInfoBoardDeCsInfo, + DB_88F5180N_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5180NddrxInfoBoardPciIf, + DB_88F5180N_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5180NddrxInfoBoardTwsiDev, + DB_88F5180N_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5180NddrxInfoBoardMacInfo, + DB_88F5180N_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5180NddrxInfoBoardGppInfo, + DB_88F5180N_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + DB_88F5180N_DDRX_OE, /* gppOutEn */ + DB_88F5180N_DDRX_OE_VAL, /* gppOutVal */ + 0x3400 /* gppPolarityVal */ +}; + +MV_BOARD_INFO db88f5180Nddr1Info = { + "DB-88F5180N-DDR1-A", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5180N_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5180NddrxInfoBoardMppConfigValue, + ((1<<10)|(1 << 12)|(1<<13)), /* intsGppMask */ + DB_88F5180N_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5180NddrxInfoBoardDeCsInfo, + DB_88F5180N_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5180NddrxInfoBoardPciIf, + DB_88F5180N_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5180NddrxInfoBoardTwsiDev, + DB_88F5180N_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5180NddrxInfoBoardMacInfo, + DB_88F5180N_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5180NddrxInfoBoardGppInfo, + DB_88F5180N_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + N_A, /* gppOutEnVal */ + N_A /* gppPolarityVal */ +}; + + +MV_BOARD_INFO* boardInfoTbl[2] = {&db88f5180Nddr1Info, + &db88f5180Nddr2Info + }; + +#define BOARD_ID_BASE BOARD_ID_88F5180N_BASE +#define MV_MAX_BOARD_ID BOARD_ID_88F5180N_MAX + diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5180NBoardEnv.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5180NBoardEnv.h new file mode 100644 index 0000000..8ffe265 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5180NBoardEnv.h @@ -0,0 +1,87 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoard88F5180NEnvSpech +#define __INCmvBoard88F5180NEnvSpech + + + +/* 88F5180N boards ID numbers */ +/* =========================================== */ + +#define BOARD_ID_88F5180N_BASE 0x50 +/* New board ID numbers */ +#define DB_88F5180N_DDR1 (BOARD_ID_88F5180N_BASE+0x0) +#define DB_88F5180N_DDR2 (BOARD_ID_88F5180N_BASE+0x1) +#define BOARD_ID_88F5180N_MAX (BOARD_ID_88F5180N_BASE+0x2) + +#define DB_88F5180N_DDRX_MPP0_7 0x33222203 +#define DB_88F5180N_DDRX_MPP8_15 0x44000033 +#define DB_88F5180N_DDRX_MPP16_23 0x0 +#define DB_88F5180N_DDRX_MPP_DEV 0x0 +#define DB_88F5180N_DDRX_OE 0xFFFDFF17 +#define DB_88F5180N_DDRX_OE_VAL 0x0 + +#endif /* __INCmvBoard88F5180NEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181BoardEnv.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181BoardEnv.c new file mode 100644 index 0000000..b5df4f4 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181BoardEnv.c @@ -0,0 +1,858 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + + +#define DB_88F5X81_BOARD_PCI_IF_NUM 0x3 +#define DB_88F5X81_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F5X81_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F5X81_BOARD_GPP_INFO_NUM 0x3 +#define DB_88F5X81_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88F5X81_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F5X81_BOARD_DEVICE_CONFIG_NUM 0x4 + +MV_BOARD_PCI_IF db88f5x81ddr2InfoBoardPciIf[DB_88F5X81_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {12, 12, 12, 12}}, /* pciSlot0 */ + {8, {13, 13, 13, 13}}, /* pciSlot1 */ + {9, {13, 13, 13, 13}}}; /* pciSlot2 */ + +MV_BOARD_TWSI_INFO db88f5x81ddr2InfoBoardTwsiDev[DB_88F5X81_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5x81ddr2InfoBoardMacInfo[DB_88F5X81_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO db88f5x81ddr2InfoBoardGppInfo[DB_88F5X81_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 10}, + {BOARD_DEV_USB_VBUS, 1}, + {BOARD_DEV_REF_CLCK,11}}; + +MV_BOARD_MPP_INFO db88f5x81ddr2InfoBoardMppConfigValue[DB_88F5X81_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ +#ifndef MV_NAND_BOOT + {{{DB_88F5X81_DDRX_MPP0_7, /* mpp0_7 */ + DB_88F5X81_DDRX_MPP8_15, /* mpp8_15 */ + DB_88F5X81_DDRX_MPP16_23, /* mpp16_23 */ + DB_88F5X81_DDRX_MPP_DEV}} /* mppDev */ + }; +#else + {{{DB_88F5X81_DDRX_MPP0_7_NB, /* mpp0_7 */ + DB_88F5X81_DDRX_MPP8_15_NB, /* mpp8_15 */ + DB_88F5X81_DDRX_MPP16_23_NB, /* mpp16_23 */ + DB_88F5X81_DDRX_MPP_DEV_NB}} /* mppDev */ + }; +#endif + +MV_DEV_CS_INFO db88f5x81ddr2InfoBoardDeCsInfo[DB_88F5X81_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ +#ifndef MV_NAND_BOOT + {{0, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs0 */ + { 1, 0x8fefffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + { 2, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}, /* devCs2/flashCs */ + { 3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ +#else + {{0, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs0 */ + { 1, 0x8fefffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + { 2, 0x8fcfffff, BOARD_DEV_OTHER, 8}, /* devCs2/flashCs */ + { 3, 0x8fdfffff, BOARD_DEV_NAND_FLASH, 16}}; /* bootCs */ +#endif + +MV_BOARD_INFO db88f5x81ddr2Info = { + "DB-88F5X81-DDR2-A/B", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5X81_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5x81ddr2InfoBoardMppConfigValue, + ((1<<10)|(1 << 12)|(1<<13)), /* intsGppMask */ + DB_88F5X81_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5x81ddr2InfoBoardDeCsInfo, + DB_88F5X81_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5x81ddr2InfoBoardPciIf, + DB_88F5X81_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5x81ddr2InfoBoardTwsiDev, + DB_88F5X81_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5x81ddr2InfoBoardMacInfo, + DB_88F5X81_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5x81ddr2InfoBoardGppInfo, + DB_88F5X81_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + DB_88F5X81_DDRX_OE, /* gppOutEnVal */ + DB_88F5X81_DDRX_OUT_VAL, /* gppOutVal */ + 0x3400, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + +MV_BOARD_INFO db88f5x81ddr1Info = { + "DB-88F5X81-DDR1-A", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5X81_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5x81ddr2InfoBoardMppConfigValue, + ((1<<10)|(1 << 12)|(1<<13)), /* intsGppMask */ + DB_88F5X81_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5x81ddr2InfoBoardDeCsInfo, + DB_88F5X81_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5x81ddr2InfoBoardPciIf, + DB_88F5X81_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5x81ddr2InfoBoardTwsiDev, + DB_88F5X81_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5x81ddr2InfoBoardMacInfo, + DB_88F5X81_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5x81ddr2InfoBoardGppInfo, + DB_88F5X81_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + DB_88F5X81_DDRX_OE, /* gppOutEnVal */ + DB_88F5X81_DDRX_OUT_VAL, /* gppOutVal */ + 0x3400, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + +MV_BOARD_INFO db88f1181ddr1Info = { + "DB-88F1181-DDR1" /* boardName[MAX_BOARD_NAME_LEN] */ +}; + +MV_BOARD_INFO db88f1181ddr2Info = { + "DB-88F1181-DDR2" /* boardName[MAX_BOARD_NAME_LEN] */ +}; + +#define DB_PRPMC_BOARD_PCI_IF_NUM 0x1 +#define DB_PRPMC_BOARD_TWSI_DEF_NUM 0x1 +#define DB_PRPMC_BOARD_MAC_INFO_NUM 0x1 +#define DB_PRPMC_BOARD_GPP_INFO_NUM 0x1 +#define DB_PRPMC_BOARD_DEBUG_LED_NUM 0x3 +#define DB_PRPMC_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_PRPMC_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_U8 db88f5181prpmcInfoBoardDebugLedIf[DB_PRPMC_BOARD_DEBUG_LED_NUM] = + {12, 13, 14}; +MV_BOARD_PCI_IF db88f5181prpmcInfoBoardPciIf[DB_PRPMC_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{0, {12, 12, 12, 12}}}; /* pciSlot0 */ +MV_BOARD_TWSI_INFO db88f5181prpmcInfoBoardTwsiDev[DB_PRPMC_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5181prpmcInfoBoardMacInfo[DB_PRPMC_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x1F}}; + +MV_BOARD_GPP_INFO db88f5181prpmcInfoBoardGppInfo[DB_PRPMC_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_REF_CLCK, 0}}; + +MV_BOARD_MPP_INFO db88f5181prpmcInfoBoardMppConfigValue[DB_PRPMC_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F5181_DDR1_PRPMC_MPP0_7, /* mpp0_7 */ + DB_88F5181_DDR1_PRPMC_MPP8_15, /* mpp8_15 */ + DB_88F5181_DDR1_PRPMC_MPP16_23, /* mpp16_23 */ + DB_88F5181_DDR1_PRPMC_MPP_DEV}} /* mppDev */ + }; + +MV_DEV_CS_INFO db88f5181prpmcInfoBoardDeCsInfo[DB_PRPMC_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{ 1, 0x8fefffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + { 3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO db88f5181prpmcInfo = { + "DB-88F5181-DDR1-PRPMC", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_PRPMC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5181prpmcInfoBoardMppConfigValue, + ((1 << 4)|(1 << 5)|(1 << 6)|(1 << 7)), /* intsGppMask */ + DB_PRPMC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5181prpmcInfoBoardDeCsInfo, + DB_PRPMC_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5181prpmcInfoBoardPciIf, + DB_PRPMC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5181prpmcInfoBoardTwsiDev, + DB_PRPMC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5181prpmcInfoBoardMacInfo, + DB_PRPMC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5181prpmcInfoBoardGppInfo, + DB_PRPMC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + db88f5181prpmcInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + DB_88F5181_DDR1_PRPMC_OE, /* gppOutEnVal */ + DB_88F5181_DDR1_PRPMC_OUT_VAL, /* gppOutVal */ + N_A, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + +#define DB_PEXPCI_BOARD_PCI_IF_NUM 0x1 +#define DB_PEXPCI_BOARD_TWSI_DEF_NUM 0x1 +#define DB_PEXPCI_BOARD_MAC_INFO_NUM 0x1 +#define DB_PEXPCI_BOARD_GPP_INFO_NUM 0x1 +#define DB_PEXPCI_BOARD_DEBUG_LED_NUM 0x4 +#define DB_PEXPCI_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_PEXPCI_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_U8 db88f5181pexPciInfoBoardDebugLedIf[DB_PEXPCI_BOARD_DEBUG_LED_NUM] = + {12, 13, 14, 15}; + +MV_BOARD_PCI_IF db88f5181pexPciInfoBoardPciIf[DB_PEXPCI_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{0, {3, 6, 7, 7}}}; /* pciSlot0 */ + +MV_BOARD_TWSI_INFO db88f5181pexPciInfoBoardTwsiDev[DB_PEXPCI_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5181pexPciInfoBoardMacInfo[DB_PEXPCI_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO db88f5181pexPciInfoBoardGppInfo[DB_PEXPCI_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_REF_CLCK, 0}}; + +MV_BOARD_MPP_INFO db88f5181pexPciInfoBoardMppConfigValue[DB_PEXPCI_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F5181_DDR1_PRPMC_MPP0_7, /* mpp0_7 */ + DB_88F5181_DDR1_PRPMC_MPP8_15, /* mpp8_15 */ + DB_88F5181_DDR1_PRPMC_MPP16_23, /* mpp16_23 */ + DB_88F5181_DDR1_PRPMC_MPP_DEV}} /* mppDev */ + }; + +MV_DEV_CS_INFO db88f5181pexPciInfoBoardDeCsInfo[DB_PEXPCI_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{1, 0x8fefffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + { 3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO db88f5181pexPciInfo = { + "DB-88F5181-DDR1-PEX_PCI", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_PEXPCI_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5181pexPciInfoBoardMppConfigValue, + ((1 << 4)|(1 << 5)|(1 << 6)|(1 << 7)), /* intsGppMask */ + DB_PEXPCI_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5181pexPciInfoBoardDeCsInfo, + DB_PEXPCI_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5181pexPciInfoBoardPciIf, + DB_PEXPCI_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5181pexPciInfoBoardTwsiDev, + DB_PEXPCI_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5181pexPciInfoBoardMacInfo, + DB_PEXPCI_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5181pexPciInfoBoardGppInfo, + DB_PEXPCI_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + db88f5181pexPciInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + DB_88F5181_DDR1_PRPMC_OE, /* gppOutEnVal */ + DB_88F5181_DDR1_PRPMC_OUT_VAL, /* gppOutVal */ + N_A, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + +#define RD_88F5181_POS_NAS_BOARD_PCI_IF_NUM 0x1 +#define RD_88F5181_POS_NAS_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F5181_POS_NAS_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F5181_POS_NAS_BOARD_GPP_INFO_NUM 0x3 +#define RD_88F5181_POS_NAS_BOARD_DEBUG_LED_NUM 0x4 +#define RD_88F5181_POS_NAS_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F5181_POS_NAS_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_U8 rd88f5181posNasInfoBoardDebugLedIf[RD_88F5181_POS_NAS_BOARD_DEBUG_LED_NUM] = + {12, 13, 14, 15}; + +MV_BOARD_PCI_IF rd88f5181posNasInfoBoardPciIf[RD_88F5181_POS_NAS_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {6, 4, N_A, N_A}}}; /* pciSlot0 */ + +MV_BOARD_TWSI_INFO rd88f5181posNasInfoBoardTwsiDev[RD_88F5181_POS_NAS_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f5181posNasInfoBoardMacInfo[RD_88F5181_POS_NAS_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO rd88f5181posNasInfoBoardGppInfo[RD_88F5181_POS_NAS_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 8}, + {BOARD_DEV_USB_VBUS, 9}, + {BOARD_DEV_REF_CLCK,0}}; + +MV_BOARD_MPP_INFO rd88f5181posNasInfoBoardMppConfigValue[RD_88F5181_POS_NAS_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5181_POS_NAS_MPP0_7, /* mpp0_7 */ + RD_88F5181_POS_NAS_MPP8_15, /* mpp8_15 */ + RD_88F5181_POS_NAS_MPP16_23, /* mpp16_23 */ + RD_88F5181_POS_NAS_MPP_DEV}} /* mppDev */ + }; + +MV_DEV_CS_INFO rd88f5181posNasInfoBoardDeCsInfo[RD_88F5181_POS_NAS_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{1, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}, /* devCs1 */ + {3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88f5181posNasInfo = { + "RD-88F5181-88SX7042-2xSATA", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F5181_POS_NAS_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5181posNasInfoBoardMppConfigValue, + ((1 << 4)|(1 << 6)|(1 << 8)), /* intsGppMask */ + RD_88F5181_POS_NAS_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5181posNasInfoBoardDeCsInfo, + RD_88F5181_POS_NAS_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + rd88f5181posNasInfoBoardPciIf, + RD_88F5181_POS_NAS_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f5181posNasInfoBoardTwsiDev, + RD_88F5181_POS_NAS_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5181posNasInfoBoardMacInfo, + RD_88F5181_POS_NAS_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f5181posNasInfoBoardGppInfo, + RD_88F5181_POS_NAS_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5181posNasInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F5181_POS_NAS_OE, /* gppOutEnVal */ + RD_88F5181_POS_NAS_OUT_VAL, /* gppOutVal */ + N_A, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + + +#define RD_88F5181_VOIP_BOARD_PCI_IF_NUM 0x1 +#define RD_88F5181_VOIP_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F5181_VOIP_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F5181_VOIP_BOARD_GPP_INFO_NUM 0x3 +#define RD_88F5181_VOIP_BOARD_DEBUG_LED_NUM 0x3 +#define RD_88F5181_VOIP_BOARD_MPP_CONFIG_NUM 0x3 +#define RD_88F5181_VOIP_BOARD_DEVICE_CONFIG_NUM 0x4 + +MV_U8 rd88f5181voipInfoBoardDebugLedIf[RD_88F5181_VOIP_BOARD_DEBUG_LED_NUM] = + {13, 14, 15}; + +MV_BOARD_PCI_IF rd88f5181voipInfoBoardPciIf[RD_88F5181_VOIP_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{1, {4, 4, 4, 4}}}; /* pciSlot0 */ + +MV_BOARD_TWSI_INFO rd88f5181voipInfoBoardTwsiDev[RD_88F5181_VOIP_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f5181voipInfoBoardMacInfo[RD_88F5181_VOIP_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_100M, 0x0}}; + +MV_BOARD_GPP_INFO rd88f5181voipInfoBoardGppInfo[RD_88F5181_VOIP_BOARD_MPP_CONFIG_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 7}, + {BOARD_DEV_USB_VBUS, 2}, + {BOARD_DEV_MV_SWITCH,6}}; + +MV_BOARD_MPP_INFO rd88f5181voipInfoBoardMppConfigValue[RD_88F5181_VOIP_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5181_VOIP_MPP0_7, /* mpp0_7 */ + RD_88F5181_VOIP_MPP8_15}} /* mpp8_15 */ + }; + +MV_DEV_CS_INFO rd88f5181voipInfoBoardDeCsInfo[RD_88F5181_VOIP_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{ 0, 0x8fdfffff, BOARD_DEV_FPGA, N_A}, /* devCs0 */ + { 1, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}, /* devCs1 */ + { 2, 0x8fdfffff, BOARD_DEV_FPGA, N_A}, /* devCs2/flashCs */ + { 3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88f5181voipInfo = { + "RD-88F5181-VOIP-RD1", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F5181_VOIP_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5181voipInfoBoardMppConfigValue, + ((1 << 3)|(1 << 4)|(1 << 6)|(1 << 7)), /* intsGppMask */ + RD_88F5181_VOIP_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5181voipInfoBoardDeCsInfo, + RD_88F5181_VOIP_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + rd88f5181voipInfoBoardPciIf, + RD_88F5181_VOIP_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f5181voipInfoBoardTwsiDev, + RD_88F5181_VOIP_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5181voipInfoBoardMacInfo, + RD_88F5181_VOIP_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f5181voipInfoBoardGppInfo, + RD_88F5181_VOIP_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5181voipInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F5181_VOIP_OE, /* gppOutEnVal */ + RD_88F5181_VOIP_OUT_VAL, /* gppOutVal */ + N_A, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + +#define RD_88F5181_GTW_FE_BOARD_PCI_IF_NUM 0x1 +#define RD_88F5181_GTW_FE_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F5181_GTW_FE_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F5181_GTW_FE_BOARD_GPP_INFO_NUM 0x3 +#define RD_88F5181_GTW_FE_BOARD_DEBUG_LED_NUM 0x3 +#define RD_88F5181_GTW_FE_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F5181_GTW_FE_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_U8 rd88f5181GtwFeInfoBoardDebugLedIf[RD_88F5181_GTW_FE_BOARD_DEBUG_LED_NUM] = + {13, 14, 15}; + +MV_BOARD_PCI_IF rd88f5181GtwFeInfoBoardPciIf[RD_88F5181_GTW_FE_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {4, 3, N_A, N_A}}}; /* pciSlot0 */ + +MV_BOARD_TWSI_INFO rd88f5181GtwFeInfoBoardTwsiDev[RD_88F5181_GTW_FE_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f5181GtwFeInfoBoardMacInfo[RD_88F5181_GTW_FE_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_100M, 0x0}}; + +MV_BOARD_SWITCH_INFO rd88f5181GtwFeInfoBoardSwitchInfo[] = + /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, + MV_32 qdCpuPort, MV_32 smiScanMode} */ + {{-1, {0, 1, 2, 3, 4}, 5, 0}}; + +MV_BOARD_GPP_INFO rd88f5181GtwFeInfoBoardGppInfo[RD_88F5181_GTW_FE_BOARD_MPP_CONFIG_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 11} + }; + +MV_BOARD_MPP_INFO rd88f5181GtwFeInfoBoardMppConfigValue[RD_88F5181_GTW_FE_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5181_GTW_FE_MPP0_7, /* mpp0_7 */ + RD_88F5181_GTW_FE_MPP8_15}} /* mpp8_15 */ + }; + +MV_DEV_CS_INFO rd88f5181GtwFeInfoBoardDeCsInfo[RD_88F5181_GTW_FE_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{ 3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88f5181GtwFeInfo = { + "RD-88F5181-GTW-FE", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F5181_GTW_FE_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5181GtwFeInfoBoardMppConfigValue, + ((1 << 2)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 9)|(1 << 11)),/* intsGppMask */ + RD_88F5181_GTW_FE_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5181GtwFeInfoBoardDeCsInfo, + RD_88F5181_GTW_FE_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + rd88f5181GtwFeInfoBoardPciIf, + RD_88F5181_GTW_FE_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f5181GtwFeInfoBoardTwsiDev, + RD_88F5181_GTW_FE_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5181GtwFeInfoBoardMacInfo, + RD_88F5181_GTW_FE_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f5181GtwFeInfoBoardGppInfo, + RD_88F5181_GTW_FE_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5181GtwFeInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F5181_GTW_FE_OE, /* gppOutEnVal */ + RD_88F5181_GTW_FE_OUT_VAL, /* gppOutVal */ + 0xA3C, /* gppPolarity */ + rd88f5181GtwFeInfoBoardSwitchInfo /* pSwitchInfo */ + +}; + +#define RD_88F5181_GTW_GE_BOARD_PCI_IF_NUM 0x1 +#define RD_88F5181_GTW_GE_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F5181_GTW_GE_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F5181_GTW_GE_BOARD_GPP_INFO_NUM 0x3 +#define RD_88F5181_GTW_GE_BOARD_DEBUG_LED_NUM 0x4 +#define RD_88F5181_GTW_GE_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F5181_GTW_GE_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_U8 rd88f5181GtwGeInfoBoardDebugLedIf[RD_88F5181_GTW_GE_BOARD_DEBUG_LED_NUM] = + {1, 2, 3,0}; + +MV_BOARD_PCI_IF rd88f5181GtwGeInfoBoardPciIf[RD_88F5181_GTW_GE_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {4, 10, N_A, N_A}}}; /* pciSlot0 */ + +MV_BOARD_TWSI_INFO rd88f5181GtwGeInfoBoardTwsiDev[RD_88F5181_GTW_GE_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f5181GtwGeInfoBoardMacInfo[RD_88F5181_GTW_GE_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_1000M, 0x0}}; + +MV_BOARD_SWITCH_INFO rd88f5181GtwGeInfoBoardSwitchInfo[] = + /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, + MV_32 qdCpuPort, MV_32 smiScanMode} */ + {{8, {2, 1, 0, 7, 5}, 3, 1}}; + +MV_BOARD_GPP_INFO rd88f5181GtwGeInfoBoardGppInfo[RD_88F5181_GTW_GE_BOARD_MPP_CONFIG_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 7} + }; + +MV_BOARD_MPP_INFO rd88f5181GtwGeInfoBoardMppConfigValue[RD_88F5181_GTW_GE_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5181_GTW_GE_MPP0_7, /* mpp0_7 */ + RD_88F5181_GTW_GE_MPP8_15, + RD_88F5181_GTW_GE_MPP16_23}} /* mpp8_15 */ + }; + +MV_DEV_CS_INFO rd88f5181GtwGeInfoBoardDeCsInfo[RD_88F5181_GTW_GE_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{ 3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88f5181GtwGeInfo = { + "RD-88F5181-GTW-GE", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F5181_GTW_GE_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5181GtwGeInfoBoardMppConfigValue, + ((1 << 4)|(1 << 5)|(1 << 8)), /* intsGppMask */ + RD_88F5181_GTW_GE_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5181GtwGeInfoBoardDeCsInfo, + RD_88F5181_GTW_GE_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + rd88f5181GtwGeInfoBoardPciIf, + RD_88F5181_GTW_GE_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f5181GtwGeInfoBoardTwsiDev, + RD_88F5181_GTW_GE_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5181GtwGeInfoBoardMacInfo, + RD_88F5181_GTW_GE_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f5181GtwGeInfoBoardGppInfo, + RD_88F5181_GTW_GE_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5181GtwGeInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F5181_GTW_GE_OE, /* gppOutEnVal */ + RD_88F5181_GTW_GE_OUT_VAL, /* gppOutVal */ + 0x530, /* gppPolarity */ + rd88f5181GtwGeInfoBoardSwitchInfo /* pSwitchInfo */ +}; + + + + +#define DB_88F5181_5281_DDR1_BOARD_PCI_IF_NUM 0x3 +#define DB_88F5181_5281_DDR1_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F5181_5281_DDR1_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F5181_5281_DDR1_BOARD_GPP_INFO_NUM 0x1 +#define DB_88F5181_5281_DDR1_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88F5181_5281_DDR1_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F5181_5281_DDR1_BOARD_DEVICE_CONFIG_NUM 0x3 + +MV_BOARD_PCI_IF db88f5181_5281ddr1InfoBoardPciIf[DB_88F5181_5281_DDR1_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {7, 7, 7, 7}}, /* pciSlot0 */ + {8, {6, 6, 6, 6}}, /* pciSlot1 */ + {9, {6, 6, 6, 6}}}; /* pciSlot2 */ + +MV_BOARD_TWSI_INFO db88f5181_5281ddr1InfoBoardTwsiDev[DB_88F5181_5281_DDR1_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5181_5281ddr1InfoBoardMacInfo[DB_88F5181_5281_DDR1_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO db88f5181_5281ddr1InfoBoardGppInfo[DB_88F5181_5281_DDR1_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_USB_VBUS, 5}}; + +MV_BOARD_MPP_INFO db88f5181_5281ddr1InfoBoardMppConfigValue[DB_88F5181_5281_DDR1_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F5181_5281_DDR1_MPP0_7, /* mpp0_7 */ + DB_88F5181_5281_DDR1_MPP8_15, /* mpp8_15 */ + DB_88F5181_5281_DDR1_MPP16_23, /* mpp16_23 */ + DB_88F5181_5281_DDR1_MPP_DEV}}}; /* mppDev */ + +MV_DEV_CS_INFO db88f5181_5281ddr1InfoBoardDeCsInfo[DB_88F5181_5281_DDR1_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{1, 0x8fefffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + {2, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs2 */ + {3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO db88f5181_5281ddr1Info = { + "DB-88F5181-DDR1", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5181_5281_DDR1_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5181_5281ddr1InfoBoardMppConfigValue, + ((1 << 6)|(1 << 7)), /* intsGppMask */ + DB_88F5181_5281_DDR1_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5181_5281ddr1InfoBoardDeCsInfo, + DB_88F5181_5281_DDR1_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5181_5281ddr1InfoBoardPciIf, + DB_88F5181_5281_DDR1_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5181_5281ddr1InfoBoardTwsiDev, + DB_88F5181_5281_DDR1_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5181_5281ddr1InfoBoardMacInfo, + DB_88F5181_5281_DDR1_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5181_5281ddr1InfoBoardGppInfo, + DB_88F5181_5281_DDR1_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + DB_88F5181_5281_DDR1_OE, /* gppOutEnVal */ + DB_88F5181_5281_DDR1_OUT_VAL, /* gppOutVal */ + N_A, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + + + +#define DB_88F5181_5281_DDR2_BOARD_PCI_IF_NUM 0x3 +#define DB_88F5181_5281_DDR2_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F5181_5281_DDR2_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F5181_5281_DDR2_BOARD_GPP_INFO_NUM 0x3 +#define DB_88F5181_5281_DDR2_BOARD_DEBUG_LED_NUM 0x4 +#define DB_88F5181_5281_DDR2_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F5181_5281_DDR2_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_U8 db88f5181_5281ddr2InfoBoardDebugLedIf[DB_88F5181_5281_DDR2_BOARD_DEBUG_LED_NUM] = + {14, 15, 6, 7}; + +MV_BOARD_PCI_IF db88f5181_5281ddr2InfoBoardPciIf[DB_88F5181_5281_DDR2_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {12, 12, 12, 12}}, /* pciSlot0 */ + {8, {13, 13, 13, 13}}, /* pciSlot1 */ + {9, {13, 13, 13, 13}}}; /* pciSlot2 */ + +MV_BOARD_TWSI_INFO db88f5181_5281ddr2InfoBoardTwsiDev[DB_88F5181_5281_DDR2_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5181_5281ddr2InfoBoardMacInfo[DB_88F5181_5281_DDR2_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO db88f5181_5281ddr2InfoBoardGppInfo[DB_88F5181_5281_DDR2_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 10}, + {BOARD_DEV_USB_VBUS, 1}, + {BOARD_DEV_REF_CLCK,11}}; + +MV_BOARD_MPP_INFO db88f5181_5281ddr2InfoBoardMppConfigValue[DB_88F5181_5281_DDR2_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F5181_5281_DDR2_MPP0_7, /* mpp0_7 */ + DB_88F5181_5281_DDR2_MPP8_15, /* mpp8_15 */ + DB_88F5181_5281_DDR2_MPP16_23, /* mpp16_23 */ + DB_88F5181_5281_DDR2_MPP_DEV}}}; /* mppDev */ + +MV_DEV_CS_INFO db88f5181_5281ddr2InfoBoardDeCsInfo[DB_88F5181_5281_DDR2_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{1, 0x8fefffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + {3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO db88f5181_5281ddr2Info = { + "DB-88F5181-DDR2", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5181_5281_DDR2_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5181_5281ddr2InfoBoardMppConfigValue, + ((1 << 10)|(1 << 12)|(1 << 13)), /* intsGppMask */ + DB_88F5181_5281_DDR2_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5181_5281ddr2InfoBoardDeCsInfo, + DB_88F5181_5281_DDR2_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5181_5281ddr2InfoBoardPciIf, + DB_88F5181_5281_DDR2_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5181_5281ddr2InfoBoardTwsiDev, + DB_88F5181_5281_DDR2_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5181_5281ddr2InfoBoardMacInfo, + DB_88F5181_5281_DDR2_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5181_5281ddr2InfoBoardGppInfo, + DB_88F5181_5281_DDR2_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + db88f5181_5281ddr2InfoBoardDebugLedIf, + 1, /* ledsPolarity */ + DB_88F5181_5281_DDR2_OE, /* gppOutEnVal */ + DB_88F5181_5281_DDR2_OUT_VAL, /* gppOutVal */ + N_A, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + + +#define DB_88F5181_DDR1_MNG_BOARD_PCI_IF_NUM 0x1 +#define DB_88F5181_DDR1_MNG_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F5181_DDR1_MNG_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F5181_DDR1_MNG_BOARD_GPP_INFO_NUM 0x1 +#define DB_88F5181_DDR1_MNG_BOARD_DEBUG_LED_NUM 0x3 +#define DB_88F5181_DDR1_MNG_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F5181_DDR1_MNG_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_BOARD_PCI_IF db88f5181ddr1MngInfoBoardPciIf[] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{2, {7, 7, 7, 7}}}; /* pciSlot0 */ + +MV_U8 db88f5181ddr1MngInfoBoardDebugLedIf[DB_88F5181_DDR1_MNG_BOARD_DEBUG_LED_NUM] = + {12, 13, 14}; + +MV_BOARD_TWSI_INFO db88f5181ddr1MngInfoBoardTwsiDev[DB_88F5181_DDR1_MNG_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5181ddr1MngInfoBoardMacInfo[DB_88F5181_DDR1_MNG_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x1F}}; + +MV_BOARD_GPP_INFO db88f5181ddr1MngInfoBoardGppInfo[DB_88F5181_DDR1_MNG_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_REF_CLCK,0}}; + +MV_BOARD_MPP_INFO db88f5181ddr1MngInfoBoardMppConfigValue[DB_88F5181_DDR1_MNG_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F5181_DDR1_MNG_MPP0_7, /* mpp0_7 */ + DB_88F5181_DDR1_MNG_MPP8_15, /* mpp8_15 */ + DB_88F5181_DDR1_MNG_MPP16_23, /* mpp16_23 */ + DB_88F5181_DDR1_MNG_MPP_DEV}}}; /* mppDev */ + +MV_DEV_CS_INFO db88f5181ddr1MngInfoBoardDeCsInfo[DB_88F5181_DDR1_MNG_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{1, 0x8fefffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + {3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO db88f5181ddr1MngInfo = { + "DB-88F5181-DDR1-MNG", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5181_DDR1_MNG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5181ddr1MngInfoBoardMppConfigValue, + ((1 << 3)|(1 << 6)|(1 << 7)), /* intsGppMask */ + DB_88F5181_DDR1_MNG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5181ddr1MngInfoBoardDeCsInfo, + DB_88F5181_DDR1_MNG_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5181ddr1MngInfoBoardPciIf, + DB_88F5181_DDR1_MNG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5181ddr1MngInfoBoardTwsiDev, + DB_88F5181_DDR1_MNG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5181ddr1MngInfoBoardMacInfo, + DB_88F5181_DDR1_MNG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5181ddr1MngInfoBoardGppInfo, + DB_88F5181_DDR1_MNG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + db88f5181ddr1MngInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + DB_88F5181_DDR1_MNG_GPP_OE, /* gppOutEnVal */ + DB_88F5181_DDR1_MNG_GPP_OUT_VAL, /* gppOutVal */ + N_A, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + +#define DB_88F5X8X_BOARD_PCI_IF_NUM 0x0 +#define DB_88F5X8X_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F5X8X_BOARD_MAC_INFO_NUM 0x0 +#define DB_88F5X8X_BOARD_GPP_INFO_NUM 0x1 +#define DB_88F5X8X_BOARD_DEBUG_LED_NUM 0x4 +#define DB_88F5X8X_BOARD_MPP_CONFIG_NUM 0x0 +#define DB_88F5X8X_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_BOARD_PCI_IF db88f5x8xddr2InfoBoardPciIf[] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {6, 6, 6, 6}}, /* pciSlot0 */ + {8, {7, 7, 7, 7}}, /* pciSlot1 */ + {9, {7, 7, 7, 7}}}; /* pciSlot2 */ + +MV_BOARD_TWSI_INFO db88f5x8xddr2InfoBoardTwsiDev[DB_88F5X8X_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5x8xddr2InfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO db88f5x8xddr2InfoBoardGppInfo[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 10}, + {BOARD_DEV_USB_VBUS, 1}, + {BOARD_DEV_REF_CLCK,11}}; + +MV_BOARD_MPP_INFO db88f5x8xddr2InfoBoardMppConfigValue[] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F5X8X_DDRX_MPP0_7, /* mpp0_7 */ + DB_88F5X8X_DDRX_MPP8_15, /* mpp8_15 */ + DB_88F5X8X_DDRX_MPP16_23, /* mpp16_23 */ + DB_88F5X8X_DDRX_MPP_DEV}} /* mppDev */ + }; + +MV_DEV_CS_INFO db88f5x8xddr2InfoBoardDeCsInfo[DB_88F5X8X_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}, /* devCs0 */ + { 3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO db88f5x8xFpgaddr2Info = { + "DB-88F5X8X-FPGA-DDR1-A", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5X8X_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + NULL, + ((1<<6)|(1 << 7)), /* intsGppMask */ + DB_88F5X8X_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5x8xddr2InfoBoardDeCsInfo, + DB_88F5X8X_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + DB_88F5X8X_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5x8xddr2InfoBoardTwsiDev, + DB_88F5X8X_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + NULL, + DB_88F5X8X_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5x8xddr2InfoBoardGppInfo, + DB_88F5X8X_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + DB_88F5X8X_DDRX_OE, /* gppOutEnVal */ + DB_88F5X8X_DDRX_OUT_VAL, /* gppOutVal */ + N_A, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + +MV_BOARD_INFO* boardInfoTbl[] = {NULL, /* DB_88F1181_DDR1 - OBSOLETE */ + NULL, /* DB_88F1181_DDR2 - OBSOLETE */ + &db88f5181_5281ddr1Info, /* DB_88F5181_5281_DDR1 */ + &db88f5181_5281ddr2Info, /* DB_88F5181_5281_DDR2 */ + &db88f5181prpmcInfo, /* DB_88F5181_DDR1_PRPMC */ + &db88f5181pexPciInfo, /* DB_88F5181_DDR1_PEXPCI */ + &rd88f5181posNasInfo, /* RD_88F5181_POS_NAS */ + &db88f5x81ddr2Info, /* DB_88F5X81_DDR2 */ + &db88f5x81ddr1Info, /* DB_88F5X81_DDR1 */ + &rd88f5181voipInfo, /* RD_88F5181_VOIP - OBSOLETE */ + &db88f5181ddr1MngInfo, /* DB_88F5181_DDR1_MNG */ + &rd88f5181GtwFeInfo, /* RD_88F5181_GTW_FE */ + &rd88f5181GtwGeInfo, /* RD_88F5181_GTW_GE */ + &db88f5x8xFpgaddr2Info /* DB_88F5X8X_FPGA_DDR2 */ + }; + +#define BOARD_ID_BASE BOARD_ID_88F5181_5281_BASE +#define MV_MAX_BOARD_ID BOARD_ID_88F5181_5281_MAX + diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181BoardEnv.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181BoardEnv.h new file mode 100644 index 0000000..17a34a5 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181BoardEnv.h @@ -0,0 +1,182 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoard88F5181EnvSpech +#define __INCmvBoard88F5181EnvSpech + + + +/* 88F5181 and 88F5281 based boards ID numbers */ +/* =========================================== */ +#define BOARD_ID_88F5181_5281_BASE 0x0 + +#define RD_88F5181_GTW_FE_OLD 0xd +#define RD_88F5181_GTW_GE_OLD 0xe +#define RD_88F5181_POS_NAS_OLD 0xab +#define DB_88F5X81_DDR2_OLD 0xcd +#define DB_88F5X81_DDR1_OLD 0xce + +#define DB_88F1181_DDR1 (BOARD_ID_88F5181_5281_BASE+0x0) /* obsolete */ +#define DB_88F1181_DDR2 (BOARD_ID_88F5181_5281_BASE+0x1) /* obsolete */ +#define DB_88F5181_5281_DDR1 (BOARD_ID_88F5181_5281_BASE+0x2) +#define DB_88F5181_5281_DDR2 (BOARD_ID_88F5181_5281_BASE+0x3) +#define DB_88F5181_DDR1_PRPMC (BOARD_ID_88F5181_5281_BASE+0x4) +#define DB_88F5181_DDR1_PEXPCI (BOARD_ID_88F5181_5281_BASE+0x5) +#define RD_88F5181_POS_NAS (BOARD_ID_88F5181_5281_BASE+0x6) +#define DB_88F5X81_DDR2 (BOARD_ID_88F5181_5281_BASE+0x7) +#define DB_88F5X81_DDR2_OPEN_LINUX_ID 1358 +#define DB_88F5X81_DDR1 (BOARD_ID_88F5181_5281_BASE+0x8) +#define RD_88F5181_VOIP (BOARD_ID_88F5181_5281_BASE+0x9) /* obsolete */ +#define DB_88F5181_DDR1_MNG (BOARD_ID_88F5181_5281_BASE+0xA) +#define RD_88F5181_GTW_FE (BOARD_ID_88F5181_5281_BASE+0xB) +#define RD_88F5181_GTW_GE (BOARD_ID_88F5181_5281_BASE+0xC) +#define DB_88F5X8X_FPGA_DDR1 (BOARD_ID_88F5181_5281_BASE+0xD) + +#define BOARD_ID_88F5181_5281_MAX (BOARD_ID_88F5181_5281_BASE+0xE) + +#define DB_88F5181_5281_DDR1_MPP0_7 0x00032222 +#define DB_88F5181_5281_DDR1_MPP8_15 0x11111111 +#define DB_88F5181_5281_DDR1_MPP16_23 0x1111 +#define DB_88F5181_5281_DDR1_MPP_DEV 0x0 +#define DB_88F5181_5281_DDR1_OE 0xFFFFFFFF +#define DB_88F5181_5281_DDR1_OUT_VAL 0x0 + +#define DB_88F5181_5281_DDR2_MPP0_7 0x00222203 +#define DB_88F5181_5281_DDR2_MPP8_15 0x00001133 +#define DB_88F5181_5281_DDR2_MPP16_23 0x0 +#define DB_88F5181_5281_DDR2_MPP_DEV 0x0 +#define DB_88F5181_5281_DDR2_OE 0xFFFF3F17 +#define DB_88F5181_5281_DDR2_OUT_VAL BIT15 + +#define DB_88F5X81_DDRX_MPP0_7 0x33222203 +#define DB_88F5X81_DDRX_MPP8_15 0x44000033 +#define DB_88F5X81_DDRX_MPP16_23 0x0 +#define DB_88F5X81_DDRX_MPP_DEV 0x0 +#define DB_88F5X81_DDRX_OE 0xFFFDFF17 +#define DB_88F5X81_DDRX_OUT_VAL 0x0 + +#define DB_88F5181_DDR1_PRPMC_MPP0_7 0x00000003 +#define DB_88F5181_DDR1_PRPMC_MPP8_15 0x10001111 +#define DB_88F5181_DDR1_PRPMC_MPP16_23 0x00001111 +#define DB_88F5181_DDR1_PRPMC_MPP_DEV 0x0 +#define DB_88F5181_DDR1_PRPMC_OE 0xFFFF0FFF +#define DB_88F5181_DDR1_PRPMC_OUT_VAL 0x0 + +#define RD_88F5181_POS_NAS_MPP0_7 0x0 +#define RD_88F5181_POS_NAS_MPP8_15 0x0 +#define RD_88F5181_POS_NAS_MPP16_23 0x0 +#define RD_88F5181_POS_NAS_MPP_DEV 0x0 +#define RD_88F5181_POS_NAS_OE 0x00000BDF +#define RD_88F5181_POS_NAS_OUT_VAL 0x0 + +#define RD_88F5181_VOIP_MPP0_7 0x00000003 +#define RD_88F5181_VOIP_MPP8_15 0x00000101 +#define RD_88F5181_VOIP_MPP16_23 0x0 +#define RD_88F5181_VOIP_MPP_DEV 0x0 +#define RD_88F5181_VOIP_OE 0x000005F5 +#define RD_88F5181_VOIP_OUT_VAL 0x0 + + +#define DB_88F5X81_DDRX_MPP0_7_NB 0x33442203 +#define DB_88F5X81_DDRX_MPP8_15_NB 0x44000033 +#define DB_88F5X81_DDRX_MPP16_23_NB 0x0 +#define DB_88F5X81_DDRX_MPP_DEV_NB 0x0 + +#define DB_88F5181_DDR1_MNG_MPP0_7 0x00000003 +#define DB_88F5181_DDR1_MNG_MPP8_15 0x10001111 +#define DB_88F5181_DDR1_MNG_MPP16_23 0x00001111 +#define DB_88F5181_DDR1_MNG_MPP_DEV 0x0 +#define DB_88F5181_DDR1_MNG_GPP_OE 0xFFFF8FF8 +#define DB_88F5181_DDR1_MNG_GPP_OUT_VAL 0x0 + +#define DB_88F5181_DDR1_PEXPCI_MPP0_7 0x00330000 +#define DB_88F5181_DDR1_PEXPCI_MPP8_15 0x0 +#define DB_88F5181_DDR1_PEXPCI_MPP16_23 0x0 +#define DB_88F5181_DDR1_PEXPCI_MPP_DEV 0x0 +#define DB_88F5181_DDR1_PEXPCI_OE 0xFFFDFF17 +#define DB_88F5181_DDR1_PEXPCI_OUT_VAL 0x0 + +#define RD_88F5181_GTW_FE_MPP0_7 0x55000003 +#define RD_88F5181_GTW_FE_MPP8_15 0x00000101 +#define RD_88F5181_GTW_FE_MPP16_23 0x0 +#define RD_88F5181_GTW_FE_MPP_DEV 0x0 +#define RD_88F5181_GTW_FE_OE 0xFFFF0FFC +#define RD_88F5181_GTW_FE_OUT_VAL 0xF001 + +#define RD_88F5181_GTW_GE_MPP0_7 0x55000003 +#define RD_88F5181_GTW_GE_MPP8_15 0x11110010 +#define RD_88F5181_GTW_GE_MPP16_23 0x1111 +#define RD_88F5181_GTW_GE_MPP_DEV 0x0 +#define RD_88F5181_GTW_GE_OE 0xFFFF07F0 +#define RD_88F5181_GTW_GE_OUT_VAL 0x80F + +#define DB_88F5X8X_DDRX_MPP0_7 0x00222222 +#define DB_88F5X8X_DDRX_MPP8_15 0x33330000 +#define DB_88F5X8X_DDRX_MPP16_23 0x0 +#define DB_88F5X8X_DDRX_MPP_DEV 0x0 +#define DB_88F5X8X_DDRX_OE 0xFFFF0330 +#define DB_88F5X8X_DDRX_OUT_VAL 0x0 + +#endif /* __INCmvBoard88F5181EnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181LBoardEnv.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181LBoardEnv.c new file mode 100644 index 0000000..b6d3bb3 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181LBoardEnv.c @@ -0,0 +1,354 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + + + +#define DB_88F5181L_BOARD_PCI_IF_NUM 0x3 +#define DB_88F5181L_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F5181L_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F5181L_BOARD_GPP_INFO_NUM 0x3 +#define DB_88F5181L_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88F5181L_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F5181L_BOARD_DEVICE_CONFIG_NUM 0x4 + +MV_BOARD_PCI_IF db88f5181Lddr2InfoBoardPciIf[DB_88F5181L_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {12, 12, 12, 12}}, /* pciSlot0 */ + {8, {13, 13, 13, 13}}, /* pciSlot1 */ + {9, {13, 13, 13, 13}}}; /* pciSlot2 */ + +MV_BOARD_TWSI_INFO db88f5181Lddr2InfoBoardTwsiDev[DB_88F5181L_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5181Lddr2InfoBoardMacInfo[DB_88F5181L_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO db88f5181Lddr2InfoBoardGppInfo[DB_88F5181L_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 10}, + {BOARD_DEV_USB_VBUS, 1}, + {BOARD_DEV_REF_CLCK, 11}}; + +MV_BOARD_MPP_INFO db88f5181Lddr2InfoBoardMppConfigValue[DB_88F5181L_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F5181L_DDR2_2XTDM_MPP0_7, /* mpp0_7 */ + DB_88F5181L_DDR2_2XTDM_MPP8_15, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}} /* mppDev */ + }; + +MV_DEV_CS_INFO db88f5181Lddr2InfoBoardDeCsInfo[DB_88F5181L_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs0 */ + {1, 0x8fdfffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + {2, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}, /* devCs2/flashCs */ + {3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO db88f5181Lddr2Info = { + "DB-88F5181L-DDR2-2xTDM", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5181L_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5181Lddr2InfoBoardMppConfigValue, + ((1<<8)|(1 << 9)|(1<<10)|(1<<12)|(1<<13)), /* intsGppMask */ + DB_88F5181L_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5181Lddr2InfoBoardDeCsInfo, + DB_88F5181L_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5181Lddr2InfoBoardPciIf, + DB_88F5181L_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5181Lddr2InfoBoardTwsiDev, + DB_88F5181L_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5181Lddr2InfoBoardMacInfo, + DB_88F5181L_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5181Lddr2InfoBoardGppInfo, + DB_88F5181L_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + DB_88F5181L_DDR2_2XTDM_OE, /* gppOutEnVal */ + DB_88F5181L_DDR2_2XTDM_OUT_VAL, /* gppOutVal */ + 0x3700, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + + + +#define RD_88F5181L_VOIP_FE_BOARD_PCI_IF_NUM 0x1 +#define RD_88F5181L_VOIP_FE_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F5181L_VOIP_FE_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F5181L_VOIP_FE_BOARD_GPP_INFO_NUM 0x3 +#define RD_88F5181L_VOIP_FE_BOARD_DEBUG_LED_NUM 0x3 +#define RD_88F5181L_VOIP_FE_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F5181L_VOIP_FE_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_U8 rd88f5181LvoipFeInfoBoardDebugLedIf[RD_88F5181L_VOIP_FE_BOARD_DEBUG_LED_NUM] = + {13, 14, 15}; + +MV_BOARD_PCI_IF rd88f5181LvoipFeInfoBoardPciIf[RD_88F5181L_VOIP_FE_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {4, 3, N_A, N_A}}}; /* pciSlot0 */ + +MV_BOARD_TWSI_INFO rd88f5181LvoipFeInfoBoardTwsiDev[RD_88F5181L_VOIP_FE_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f5181LvoipFeInfoBoardMacInfo[RD_88F5181L_VOIP_FE_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_100M, 0x0}}; + +MV_BOARD_SWITCH_INFO rd88f5181LvoipFeInfoBoardSwitchInfo[] = + /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, + MV_32 qdCpuPort, MV_32 smiScanMode} */ + {{-1, {0, 1, 2, 3, 4}, 5, 0}}; + +MV_BOARD_GPP_INFO rd88f5181LvoipFeInfoBoardGppInfo[RD_88F5181L_VOIP_FE_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 11}}; + +MV_BOARD_MPP_INFO rd88f5181LvoipFeInfoBoardMppConfigValue[RD_88F5181L_VOIP_FE_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5181L_VOIP_FE_MPP0_7, /* mpp0_7 */ + RD_88F5181L_VOIP_FE_MPP8_15, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}} /* mppDev */ + }; + +MV_DEV_CS_INFO rd88f5181LvoipFeInfoBoardDeCsInfo[RD_88F5181L_VOIP_FE_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88f5181LvoipFeInfo = { + "RD-88F5181L-VOIP-FE", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F5181L_VOIP_FE_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5181LvoipFeInfoBoardMppConfigValue, + ((1<<2)|(1 << 3)|(1<<4)|(1<<5)|(1<<9)|(1<<11)), /* intsGppMask */ + RD_88F5181L_VOIP_FE_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5181LvoipFeInfoBoardDeCsInfo, + RD_88F5181L_VOIP_FE_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + rd88f5181LvoipFeInfoBoardPciIf, + RD_88F5181L_VOIP_FE_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f5181LvoipFeInfoBoardTwsiDev, + RD_88F5181L_VOIP_FE_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5181LvoipFeInfoBoardMacInfo, + RD_88F5181L_VOIP_FE_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f5181LvoipFeInfoBoardGppInfo, + RD_88F5181L_VOIP_FE_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5181LvoipFeInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F5181L_VOIP_FE_GPP_OE, /* gppOutEnVal */ + RD_88F5181L_VOIP_FE_GPP_IO, /* gppOutVal */ + N_A, /* gppPolarityVal */ + rd88f5181LvoipFeInfoBoardSwitchInfo /* pSwitchInfo */ +}; + + + +#define RD_88F5181L_VOIP_GE_BOARD_PCI_IF_NUM 0x1 +#define RD_88F5181L_VOIP_GE_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F5181L_VOIP_GE_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F5181L_VOIP_GE_BOARD_GPP_INFO_NUM 0x3 +#define RD_88F5181L_VOIP_GE_BOARD_DEBUG_LED_NUM 0x4 +#define RD_88F5181L_VOIP_GE_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F5181L_VOIP_GE_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_U8 rd88f5181LvoipGeInfoBoardDebugLedIf[RD_88F5181L_VOIP_GE_BOARD_DEBUG_LED_NUM] = + {1, 2, 3, 0}; + +MV_BOARD_PCI_IF rd88f5181LvoipGeInfoBoardPciIf[RD_88F5181L_VOIP_GE_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {4, 10, N_A, N_A}}}; /* pciSlot0 */ + +MV_BOARD_TWSI_INFO rd88f5181LvoipGeInfoBoardTwsiDev[RD_88F5181L_VOIP_GE_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f5181LvoipGeInfoBoardMacInfo[RD_88F5181L_VOIP_GE_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_1000M, 0x0}}; + +MV_BOARD_SWITCH_INFO rd88f5181LvoipGeInfoBoardSwitchInfo[] = + /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, + MV_32 qdCpuPort, MV_32 smiScanMode} */ + {{8, {2, 1, 0, 7, 5}, 3, 1}}; + +MV_BOARD_GPP_INFO rd88f5181LvoipGeInfoBoardGppInfo[RD_88F5181L_VOIP_GE_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 5}}; + +MV_BOARD_MPP_INFO rd88f5181LvoipGeInfoBoardMppConfigValue[RD_88F5181L_VOIP_GE_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5181L_VOIP_GE_MPP0_7, /* mpp0_7 */ + RD_88F5181L_VOIP_GE_MPP8_15, /* mpp8_15 */ + RD_88F5181L_VOIP_GE_MPP16_23, /* mpp16_23 */ + N_A}} /* mppDev */ + }; + +MV_DEV_CS_INFO rd88f5181LvoipGeInfoBoardDeCsInfo[RD_88F5181L_VOIP_GE_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88f5181LvoipGeInfo = { + "RD-88F5181L-VOIP-GE", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F5181L_VOIP_GE_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5181LvoipGeInfoBoardMppConfigValue, + ((1<<4)|(1 << 5)|(1<<8)), /* intsGppMask */ + RD_88F5181L_VOIP_GE_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5181LvoipGeInfoBoardDeCsInfo, + RD_88F5181L_VOIP_GE_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + rd88f5181LvoipGeInfoBoardPciIf, + RD_88F5181L_VOIP_GE_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f5181LvoipGeInfoBoardTwsiDev, + RD_88F5181L_VOIP_GE_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5181LvoipGeInfoBoardMacInfo, + RD_88F5181L_VOIP_GE_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f5181LvoipGeInfoBoardGppInfo, + RD_88F5181L_VOIP_GE_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5181LvoipGeInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F5181L_VOIP_GE_GPP_OE, /* gppOutEnVal */ + RD_88F5181L_VOIP_GE_GPP_IO, /* gppOutVal */ + N_A, /* gppPolarityVal */ + rd88f5181LvoipGeInfoBoardSwitchInfo /* pSwitchInfo */ +}; + + +#define RD_88F5181L_FXO_GE_BOARD_PCI_IF_NUM 0x1 +#define RD_88F5181L_FXO_GE_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F5181L_FXO_GE_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F5181L_FXO_GE_BOARD_GPP_INFO_NUM 0x3 +#define RD_88F5181L_FXO_GE_BOARD_DEBUG_LED_NUM 0x1 +#define RD_88F5181L_FXO_GE_BOARD_MPP_CONFIG_NUM 0x3 +#define RD_88F5181L_FXO_GE_BOARD_DEVICE_CONFIG_NUM 0x1 + +/* Note the last LED's will be use for init and Linux heartbeat */ +MV_U8 rd88f5181LFXOGeInfoBoardDebugLedIf[RD_88F5181L_FXO_GE_BOARD_DEBUG_LED_NUM] = + {0}; + +MV_BOARD_PCI_IF rd88f5181LFXOGeInfoBoardPciIf[RD_88F5181L_FXO_GE_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {1, 1, N_A, N_A}}}; /* pciSlot0 */ + +MV_BOARD_TWSI_INFO rd88f5181LFXOGeInfoBoardTwsiDev[RD_88F5181L_FXO_GE_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f5181LFXOGeInfoBoardMacInfo[RD_88F5181L_FXO_GE_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_1000M, 0x0}}; + +MV_BOARD_SWITCH_INFO rd88f5181LFXOGeInfoBoardSwitchInfo[] = + /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, + MV_32 qdCpuPort, MV_32 smiScanMode} */ + {{-1, {2, 1, 0, 7, 5}, 3, 1}}; + +MV_BOARD_GPP_INFO rd88f5181LFXOGeInfoBoardGppInfo[RD_88F5181L_FXO_GE_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 5}}; + +MV_BOARD_MPP_INFO rd88f5181LFXOGeInfoBoardMppConfigValue[RD_88F5181L_FXO_GE_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5181L_FXO_GE_MPP0_7, /* mpp0_7 */ + RD_88F5181L_FXO_GE_MPP8_15, /* mpp8_15 */ + RD_88F5181L_FXO_GE_MPP16_23, /* mpp16_23 */ + N_A}} /* mppDev */ + }; + +MV_DEV_CS_INFO rd88f5181LFXOGeInfoBoardDeCsInfo[RD_88F5181L_FXO_GE_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{3,0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88f5181LFXOGeInfo = { + "RD-88F5181L-VOIP-FXO-GE", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F5181L_FXO_GE_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5181LFXOGeInfoBoardMppConfigValue, + ((1 << 1)|(1 << 3)|(1 << 8)|(1 << 11)), /* intsGppMask */ + RD_88F5181L_FXO_GE_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5181LFXOGeInfoBoardDeCsInfo, + RD_88F5181L_FXO_GE_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + rd88f5181LFXOGeInfoBoardPciIf, + RD_88F5181L_FXO_GE_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f5181LFXOGeInfoBoardTwsiDev, + RD_88F5181L_FXO_GE_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5181LFXOGeInfoBoardMacInfo, + RD_88F5181L_FXO_GE_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f5181LFXOGeInfoBoardGppInfo, /* pBoardGppInfo */ + RD_88F5181L_FXO_GE_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5181LFXOGeInfoBoardDebugLedIf, /* ledsPolarity */ + 0, /* ledsPolarity */ + RD_88F5181L_FXO_GE_GPP_OE, /* gppOutEnVal */ + RD_88F5181L_FXO_GE_GPP_IO, /* gppOutVal */ + 0x2, /* gppPolarityVal */ + rd88f5181LFXOGeInfoBoardSwitchInfo /* pSwitchInfo */ +}; + +MV_BOARD_INFO* boardInfoTbl[4] = {&db88f5181Lddr2Info, + &rd88f5181LvoipFeInfo, + &rd88f5181LvoipGeInfo, + &rd88f5181LFXOGeInfo + }; + +#define BOARD_ID_BASE BOARD_ID_88F5181L_BASE +#define MV_MAX_BOARD_ID BOARD_ID_88F5181L_MAX + + diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181LBoardEnv.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181LBoardEnv.h new file mode 100644 index 0000000..ce7852a --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5181LBoardEnv.h @@ -0,0 +1,115 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoard88F5181LEnvSpech +#define __INCmvBoard88F5181LEnvSpech + + + +/* 88F5181L based boards ID numbers */ +/* =============================== */ +#define BOARD_ID_88F5181L_BASE 0x30 + +/* Old board ID numbers for backward compatability */ +#define DB_88F5181L_DDR2_2XTDM_OLD 0xC +#define RD_88F5181L_VOIP_FE_OLD 0xD +#define RD_88F5181L_VOIP_GE_OLD 0xE +/* New board ID numbers */ +#define DB_88F5181L_DDR2_2XTDM (BOARD_ID_88F5181L_BASE+0x0) +#define RD_88F5181L_VOIP_FE (BOARD_ID_88F5181L_BASE+0x1) +#define RD_88F5181L_VOIP_GE (BOARD_ID_88F5181L_BASE+0x2) +#define RD_88F5181L_VOIP_FXO_GE (BOARD_ID_88F5181L_BASE+0x3) + +#define BOARD_ID_88F5181L_MAX (BOARD_ID_88F5181L_BASE+0x4) + +#define DB_88F5181L_DDR2_2XTDM_MPP0_7 0x00222203 +#define DB_88F5181L_DDR2_2XTDM_MPP8_15 0x44000000 +#define DB_88F5181L_DDR2_2XTDM_MPP16_23 0x0 +#define DB_88F5181L_DDR2_2XTDM_MPP_DEV 0x0 +#define DB_88F5181L_DDR2_2XTDM_OE 0xFFFDFFD7 +#define DB_88F5181L_DDR2_2XTDM_OUT_VAL 0x0 + +#define RD_88F5181L_VOIP_FE_MPP0_7 0x55000003 +#define RD_88F5181L_VOIP_FE_MPP8_15 0x00000101 +#define RD_88F5181L_VOIP_FE_MPP16_23 0x0 +#define RD_88F5181L_VOIP_FE_MPP_DEV 0x0 +#define RD_88F5181L_VOIP_FE_GPP_OE 0xFFFF0FFC +#define RD_88F5181L_VOIP_FE_GPP_IO 0xF001 + +#define RD_88F5181L_VOIP_GE_MPP0_7 0x55000003 +#define RD_88F5181L_VOIP_GE_MPP8_15 0x11110010 +#define RD_88F5181L_VOIP_GE_MPP16_23 0x1111 +#define RD_88F5181L_VOIP_GE_MPP_DEV 0x0 +#define RD_88F5181L_VOIP_GE_GPP_OE 0xFFFF07F0 +#define RD_88F5181L_VOIP_GE_GPP_IO 0x80F + +#define RD_88F5181L_FXO_GE_MPP0_7 0x55000003 +#define RD_88F5181L_FXO_GE_MPP8_15 0x11110010 +#define RD_88F5181L_FXO_GE_MPP16_23 0x1111 +#define RD_88F5181L_FXO_GE_MPP_DEV 0x80000000 +#define RD_88F5181L_FXO_GE_GPP_OE 0x7FFFF2C2 +#define RD_88F5181L_FXO_GE_GPP_IO 0xBFF + +#endif /* __INCmvBoard88F5181LEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5182BoardEnv.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5182BoardEnv.c new file mode 100644 index 0000000..e0e57be --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5182BoardEnv.c @@ -0,0 +1,355 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#define DB_88F5182_BOARD_PCI_IF_NUM 0x3 +#define DB_88F5182_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F5182_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F5182_BOARD_GPP_INFO_NUM 0x4 +#define DB_88F5182_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88F5182_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F5182_BOARD_DEVICE_CONFIG_NUM 0x4 + +MV_BOARD_PCI_IF db88f5182ddr2InfoBoardPciIf[DB_88F5182_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {0, 0, 0, 0}}, /* pciSlot0 */ + {8, {1, 1, 1, 1}}, /* pciSlot1 */ + {9, {1, 1, 1, 1}}}; /* pciSlot2 */ + +MV_BOARD_TWSI_INFO db88f5182ddr2InfoBoardTwsiDev[DB_88F5182_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5182ddr2InfoBoardMacInfo[DB_88F5182_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO db88f5182ddr2InfoBoardGppInfo[DB_88F5182_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 10}, + {BOARD_DEV_USB_VBUS, 8}, + {BOARD_DEV_USB_VBUS, 9}, + {BOARD_DEV_REF_CLCK, 11}}; + +MV_BOARD_MPP_INFO db88f5182ddr2InfoBoardMppConfigValue[DB_88F5182_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F5182_DDR2_MPP0_7, /* mpp0_7 */ + DB_88F5182_DDR2_MPP8_15, /* mpp8_15 */ + DB_88F5182_DDR2_MPP16_23, /* mpp16_23 */ + N_A}} /* mppDev */ + }; + +MV_DEV_CS_INFO db88f5182ddr2InfoBoardDeCsInfo[DB_88F5182_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs0 */ + {1, 0x8fdfffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + {2, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}, /* devCs2/flashCs */ + {3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO db88f5182ddr2Info = { + "DB-88F5182-DDR2", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5182_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5182ddr2InfoBoardMppConfigValue, + ((1<<0)|(1 << 1)|(1<<10)), /* intsGppMask */ + DB_88F5182_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5182ddr2InfoBoardDeCsInfo, + DB_88F5182_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5182ddr2InfoBoardPciIf, + DB_88F5182_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5182ddr2InfoBoardTwsiDev, + DB_88F5182_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5182ddr2InfoBoardMacInfo, + DB_88F5182_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5182ddr2InfoBoardGppInfo, + DB_88F5182_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + DB_88F5182_DDR2_OE, /* gppOutEnVal */ + DB_88F5182_DDR2_OUT_VAL, /* gppOutVal */ + 0x403, /* gppPolarityVal */ +}; + +#define DB_88F5182_BOARD_A_PCI_IF_NUM 0x2 +#define DB_88F5182_BOARD_A_TWSI_DEF_NUM 0x1 +#define DB_88F5182_BOARD_A_MAC_INFO_NUM 0x1 +#define DB_88F5182_BOARD_A_GPP_INFO_NUM 0x4 +#define DB_88F5182_BOARD_A_DEBUG_LED_NUM 0x0 +#define DB_88F5182_BOARD_A_MPP_CONFIG_NUM 0x1 +#define DB_88F5182_BOARD_A_DEVICE_CONFIG_NUM 0x4 + +MV_BOARD_PCI_IF db88f5182ddr2AInfoBoardPciIf[DB_88F5182_BOARD_A_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{8, {1, 1, 1, 1}}, /* pciSlot1 */ + {9, {1, 1, 1, 1}}}; /* pciSlot2 */ + +MV_BOARD_TWSI_INFO db88f5182ddr2AInfoBoardTwsiDev[DB_88F5182_BOARD_A_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f5182ddr2AInfoBoardMacInfo[DB_88F5182_BOARD_A_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO db88f5182ddr2AInfoBoardGppInfo[DB_88F5182_BOARD_A_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 10}, + {BOARD_DEV_USB_VBUS, 8}, + {BOARD_DEV_USB_VBUS, 9}, + {BOARD_DEV_REF_CLCK, 11}}; + +MV_BOARD_MPP_INFO db88f5182ddr2AInfoBoardMppConfigValue[DB_88F5182_BOARD_A_MPP_CONFIG_NUM] = +#ifndef MV_NAND_BOOT + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F5182_DDR2_A_MPP0_7, /* mpp0_7 */ + DB_88F5182_DDR2_A_MPP8_15, /* mpp8_15 */ + DB_88F5182_DDR2_A_MPP16_23, /* mpp16_23 */ + N_A}} /* mppDev */ + }; +#else + {{{DB_88F5182_DDR2_A_MPP0_7NB, /* mpp0_7 */ + DB_88F5182_DDR2_A_MPP8_15NB, /* mpp8_15 */ + DB_88F5182_DDR2_A_MPP16_23NB, /* mpp16_23 */ + N_A}} /* mppDev */ + }; +#endif + +MV_DEV_CS_INFO db88f5182ddr2AInfoBoardDeCsInfo[DB_88F5182_BOARD_A_DEVICE_CONFIG_NUM] = +#ifndef MV_NAND_BOOT + /*{params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs0 */ + {1, 0x8fdfffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + {2, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}, /* devCs2/flashCs */ + {3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ +#else + /*{params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs0 */ + {1, 0x8fdfffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + {2, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}, /* devCs2/flashCs */ + {3, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}}; /* bootCs */ +#endif + +MV_BOARD_INFO db88f5182ddr2AInfo = { + "DB-88F5182-DDR2-NAND-SUPPORT", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F5182_BOARD_A_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f5182ddr2AInfoBoardMppConfigValue, + ((1 << 1)|(1<<10)), /* intsGppMask */ + DB_88F5182_BOARD_A_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f5182ddr2AInfoBoardDeCsInfo, + DB_88F5182_BOARD_A_PCI_IF_NUM, /* numBoardPciIf */ + db88f5182ddr2AInfoBoardPciIf, + DB_88F5182_BOARD_A_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f5182ddr2AInfoBoardTwsiDev, + DB_88F5182_BOARD_A_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f5182ddr2AInfoBoardMacInfo, + DB_88F5182_BOARD_A_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f5182ddr2AInfoBoardGppInfo, + DB_88F5182_BOARD_A_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + DB_88F5182_DDR2_A_OE, /* gppOutEnVal */ + DB_88F5182_DDR2_A_OUT_VAL, /* gppOutVal */ + 0x403, /* gppPolarityVal */ +}; + + +#define RD_88F5182_2XSATA_BOARD_PCI_IF_NUM 0x1 +#define RD_88F5182_2XSATA_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F5182_2XSATA_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F5182_2XSATA_BOARD_GPP_INFO_NUM 0x1 +#define RD_88F5182_2XSATA_BOARD_DEBUG_LED_NUM 0x1 +#define RD_88F5182_2XSATA_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F5182_2XSATA_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_U8 rd88f5182sataX2InfoBoardDebugLedIf[RD_88F5182_2XSATA_BOARD_DEBUG_LED_NUM] = + {0}; + +MV_BOARD_PCI_IF rd88f5182sataX2InfoBoardPciIf[RD_88F5182_2XSATA_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {7, 6, N_A, N_A}}}; /* pciSlot0 */ + +MV_BOARD_TWSI_INFO rd88f5182sataX2InfoBoardTwsiDev[RD_88F5182_2XSATA_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f5182sataX2InfoBoardMacInfo[RD_88F5182_2XSATA_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO rd88f5182sataX2InfoBoardGppInfo[RD_88F5182_2XSATA_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 3}}; + +MV_BOARD_MPP_INFO rd88f5182sataX2InfoBoardMppConfigValue[RD_88F5182_2XSATA_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5182_2XSATA_MPP0_7, /* mpp0_7 */ + RD_88F5182_2XSATA_MPP8_15, /* mpp8_15 */ + RD_88F5182_2XSATA_MPP16_23, /* mpp16_23 */ + N_A}} /* mppDev */ + }; + +MV_DEV_CS_INFO rd88f5182sataX2InfoBoardDeCsInfo[RD_88F5182_2XSATA_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{1, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}, /* devCs1 */ + {3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88f5182sataX2Info = { + "RD-88F5182-NAS-2", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F5182_2XSATA_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5182sataX2InfoBoardMppConfigValue, + ((1<<3)|(1 << 6)|(1<<7)), /* intsGppMask */ + RD_88F5182_2XSATA_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5182sataX2InfoBoardDeCsInfo, + RD_88F5182_2XSATA_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + rd88f5182sataX2InfoBoardPciIf, + RD_88F5182_2XSATA_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f5182sataX2InfoBoardTwsiDev, + RD_88F5182_2XSATA_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5182sataX2InfoBoardMacInfo, + RD_88F5182_2XSATA_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f5182sataX2InfoBoardGppInfo, + RD_88F5182_2XSATA_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5182sataX2InfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F5182_2XSATA_OE, /* gppOutEnVal */ + RD_88F5182_2XSATA_OUT_VAL, /* gppOutVal */ + RD_88F5182_2XSATA_POL, /* gppPolarityVal */ +}; + + +#define RD_88F5182_2XSATA3_BOARD_PCI_IF_NUM 0x1 +#define RD_88F5182_2XSATA3_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F5182_2XSATA3_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F5182_2XSATA3_BOARD_GPP_INFO_NUM 0x4 +#define RD_88F5182_2XSATA3_BOARD_DEBUG_LED_NUM 0x2 +#define RD_88F5182_2XSATA3_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F5182_2XSATA3_BOARD_DEVICE_CONFIG_NUM 0x2 + +MV_U8 rd88f5182sataX23InfoBoardDebugLedIf[RD_88F5182_2XSATA3_BOARD_DEBUG_LED_NUM] = + {0, 1}; + +MV_BOARD_PCI_IF rd88f5182sataX23InfoBoardPciIf[RD_88F5182_2XSATA3_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {7, N_A, N_A, N_A}}}; + +MV_BOARD_TWSI_INFO rd88f5182sataX23InfoBoardTwsiDev[RD_88F5182_2XSATA3_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f5182sataX23InfoBoardMacInfo[RD_88F5182_2XSATA3_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO rd88f5182sataX23InfoBoardGppInfo[RD_88F5182_2XSATA3_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 3}, + {BOARD_DEV_POWER_BUTTON, 6}, + {BOARD_DEV_HDD0_POWER, 2}, + {BOARD_DEV_HDD1_POWER, 8} + }; + +MV_BOARD_MPP_INFO rd88f5182sataX23InfoBoardMppConfigValue[RD_88F5182_2XSATA3_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5182_2XSATA3_MPP0_7, /* mpp0_7 */ + RD_88F5182_2XSATA3_MPP8_15, /* mpp8_15 */ + RD_88F5182_2XSATA3_MPP16_23, /* mpp16_23 */ + N_A}} /* mppDev */ + }; + +MV_DEV_CS_INFO rd88f5182sataX23InfoBoardDeCsInfo[RD_88F5182_2XSATA3_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{1, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}, /* devCs1 */ + {3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88f5182sataX23Info = { + "RD-88F5182-NAS-3", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F5182_2XSATA3_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5182sataX23InfoBoardMppConfigValue, + ((1<<3) | (1<<7)), /* intsGppMask */ + RD_88F5182_2XSATA3_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5182sataX23InfoBoardDeCsInfo, + RD_88F5182_2XSATA3_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + rd88f5182sataX23InfoBoardPciIf, + RD_88F5182_2XSATA3_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f5182sataX23InfoBoardTwsiDev, + RD_88F5182_2XSATA3_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5182sataX23InfoBoardMacInfo, + RD_88F5182_2XSATA3_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f5182sataX23InfoBoardGppInfo, + RD_88F5182_2XSATA3_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5182sataX23InfoBoardDebugLedIf, + 1, /* ledsPolarity */ + RD_88F5182_2XSATA3_OE, /* gppOutEnVal */ + RD_88F5182_2XSATA3_OUT_VAL, /* gppOutVal */ + N_A, /* gppPolarityVal */ +}; + +MV_BOARD_INFO* boardInfoTbl[] = {&db88f5182ddr2Info, + &rd88f5182sataX2Info, + &rd88f5182sataX23Info, + &db88f5182ddr2AInfo + }; + + +#define BOARD_ID_BASE BOARD_ID_88F5182_BASE +#define MV_MAX_BOARD_ID BOARD_ID_88F5182_MAX diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5182BoardEnv.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5182BoardEnv.h new file mode 100644 index 0000000..d833b8e --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F5182BoardEnv.h @@ -0,0 +1,117 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoard88F5182EnvSpech +#define __INCmvBoard88F5182EnvSpech + + +/* 88F5182 based boards ID numbers */ +/* =============================== */ +#define BOARD_ID_88F5182_BASE 0x20 + +/* Old board ID numbers for backward compatability */ +#define DB_88F5182_DDR2_OLD 0xA +#define RD_88F5182_2XSATA_OLD 0xB +#define RD_88F5182_2XSATA3_OLD 0xF +/* New board ID numbers */ +#define DB_88F5182_DDR2 (BOARD_ID_88F5182_BASE+0x0) +#define RD_88F5182_2XSATA (BOARD_ID_88F5182_BASE+0x1) +#define RD_88F5182_2XSATA_OPEN_LINUX_ID 1508 +#define RD_88F5182_2XSATA3 (BOARD_ID_88F5182_BASE+0x2) +#define DB_88F5182_DDR2_A (BOARD_ID_88F5182_BASE+0x3) + +#define BOARD_ID_88F5182_MAX (BOARD_ID_88F5182_BASE+0x4) + + + +#define DB_88F5182_DDR2_MPP0_7 0x55222203 +#define DB_88F5182_DDR2_MPP8_15 0x44550000 +#define DB_88F5182_DDR2_MPP16_23 0x0 +#define DB_88F5182_DDR2_OE 0xFFF5FFD7 +#define DB_88F5182_DDR2_OUT_VAL 0x0 + +#define DB_88F5182_DDR2_A_MPP0_7 0x55222203 +#define DB_88F5182_DDR2_A_MPP8_15 0x44550000 +#define DB_88F5182_DDR2_A_MPP16_23 0x0 +#define DB_88F5182_DDR2_A_MPP0_7NB 0x55442203 +#define DB_88F5182_DDR2_A_MPP8_15NB 0x44550000 +#define DB_88F5182_DDR2_A_MPP16_23NB 0x0 +#define DB_88F5182_DDR2_A_OE 0xFFF5FFD7 +#define DB_88F5182_DDR2_A_OUT_VAL 0x0 + +#define RD_88F5182_2XSATA_MPP0_7 0x00000003 +#define RD_88F5182_2XSATA_MPP8_15 0x55550000 +#define RD_88F5182_2XSATA_MPP16_23 0x5555 +#define RD_88F5182_2XSATA_OE 0xFFF0F0C8 +#define RD_88F5182_2XSATA_OUT_VAL 0x402 +#define RD_88F5182_2XSATA_POL 0xC8 + +#define RD_88F5182_2XSATA3_MPP0_7 0x00000003 +#define RD_88F5182_2XSATA3_MPP8_15 0x55550000 +#define RD_88F5182_2XSATA3_MPP16_23 0x5555 +#define RD_88F5182_2XSATA3_OE 0xFFCF0EF8 +#define RD_88F5182_2XSATA3_OUT_VAL 0x104 /* Enable the power for HD-0 on MPP_2 and HD-1 on MPP_8 */ + +#endif /* __INCmvBoard88F5182EnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6082BoardEnv.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6082BoardEnv.c new file mode 100644 index 0000000..1305252 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6082BoardEnv.c @@ -0,0 +1,441 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define DB_88F6082BP_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6082BP_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F6082BP_BOARD_MAC_INFO_NUM 0x2 +#define DB_88F6082BP_BOARD_GPP_INFO_NUM 0x1 +#define DB_88F6082BP_BOARD_DEBUG_LED_NUM 0x1 +#define DB_88F6082BP_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F6082BP_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_U8 db88f6082BpInfoBoardDebugLedIf[DB_88F6082BP_BOARD_DEBUG_LED_NUM] = + {2}; + +MV_BOARD_TWSI_INFO db88f6082BpInfoBoardTwsiDev[DB_88F6082BP_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f6082BpInfoBoardMacInfo[DB_88F6082BP_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}, + {BOARD_MAC_SPEED_AUTO, 0x9}, + }; + +MV_BOARD_GPP_INFO db88f6082BpInfoBoardGppInfo[DB_88F6082BP_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RESET, 7}}; + +MV_BOARD_MPP_INFO db88f6082BpInfoBoardMppConfigValue[DB_88F6082BP_BOARD_MPP_CONFIG_NUM] = +#if !defined(MV_NAND) && !defined(MV_NAND_BOOT) + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F6082_BP_MPP0_7, /* mpp0_7 */ + DB_88F6082_BP_MPP8_15, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}} /* mppDev */ + }; +#else + {{{DB_88F6082_BP_MPP0_7_NB, /* mpp0_7 */ + DB_88F6082_BP_MPP8_15_NB, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}} /* mppDev */ + }; +#endif + +#if defined(MV_NAND) || defined(MV_NAND_BOOT) +MV_DEV_CS_INFO db88f6082BpInfoBoardDeCsInfo[DB_88F6082BP_BOARD_DEVICE_CONFIG_NUM] = + /*{deviceCS, params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#else +MV_DEV_CS_INFO db88f6082BpInfoBoardDeCsInfo[DB_88F6082BP_BOARD_DEVICE_CONFIG_NUM] = + /*{deviceCS, params, devType, devWidth}*/ + {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_INFO db88f6082BpInfo = { + "DB-88F6082-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6082BP_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6082BpInfoBoardMppConfigValue, + 0, /* intsGppMask */ + DB_88F6082BP_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6082BpInfoBoardDeCsInfo, + DB_88F6082BP_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + DB_88F6082BP_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6082BpInfoBoardTwsiDev, + DB_88F6082BP_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6082BpInfoBoardMacInfo, + DB_88F6082BP_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f6082BpInfoBoardGppInfo, + DB_88F6082BP_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + db88f6082BpInfoBoardDebugLedIf, + N_A, /* ledsPolarity */ + DB_88F6082_BP_OE, /* gppOutEnVal */ + DB_88F6082_BP_OE_VAL, /* gppOutVal */ + 0x1 /* gppPolarityVal */ +}; + + +#define DB_88F6082LBP_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6082LBP_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88F6082LBP_BOARD_MAC_INFO_NUM 0x2 +#define DB_88F6082LBP_BOARD_GPP_INFO_NUM 0x1 +#define DB_88F6082LBP_BOARD_DEBUG_LED_NUM 0x2 +#define DB_88F6082LBP_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F6082LBP_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_U8 db88f6082LBpInfoBoardDebugLedIf[DB_88F6082LBP_BOARD_DEBUG_LED_NUM] = + {1, 2}; + +MV_BOARD_TWSI_INFO db88f6082LBpInfoBoardTwsiDev[DB_88F6082LBP_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88f6082LBpInfoBoardMacInfo[DB_88F6082LBP_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}, + {BOARD_MAC_SPEED_AUTO, 0x9}, + }; + +MV_BOARD_GPP_INFO db88f6082LBpInfoBoardGppInfo[DB_88F6082LBP_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RESET, 7}}; + +MV_BOARD_MPP_INFO db88f6082LBpInfoBoardMppConfigValue[DB_88F6082LBP_BOARD_MPP_CONFIG_NUM] = +#ifndef MV_NAND_BOOT + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F6082L_BP_MPP0_7, /* mpp0_7 */ + DB_88F6082L_BP_MPP8_15, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}} /* mppDev */ + }; +#else + {{{DB_88F6082L_BP_MPP0_7_NB, /* mpp0_7 */ + DB_88F6082L_BP_MPP8_15_NB, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}} /* mppDev */ + }; +#endif + +#if defined(MV_NAND) || defined(MV_NAND_BOOT) +MV_DEV_CS_INFO db88f6082LBpInfoBoardDeCsInfo[DB_88F6082LBP_BOARD_DEVICE_CONFIG_NUM] = + /*{deviceCS, params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#else +MV_DEV_CS_INFO db88f6082LBpInfoBoardDeCsInfo[DB_88F6082LBP_BOARD_DEVICE_CONFIG_NUM] = + /*{deviceCS, params, devType, devWidth}*/ + {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_INFO db88f6082LBpInfo = { + "DB-88F6082L-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6082LBP_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6082LBpInfoBoardMppConfigValue, + 0, /* intsGppMask */ + DB_88F6082LBP_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6082LBpInfoBoardDeCsInfo, + DB_88F6082LBP_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + DB_88F6082LBP_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6082LBpInfoBoardTwsiDev, + DB_88F6082LBP_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6082LBpInfoBoardMacInfo, + DB_88F6082LBP_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f6082LBpInfoBoardGppInfo, + DB_88F6082LBP_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + db88f6082LBpInfoBoardDebugLedIf, + N_A, /* ledsPolarity */ + DB_88F6082L_BP_OE, /* gppOutEnVal */ + DB_88F6082L_BP_OE_VAL, /* gppOutVal */ + 0x1 /* gppPolarityVal */ +}; + + +#define RD_88F6082NAS_BOARD_PCI_IF_NUM 0x0 +#define RD_88F6082NAS_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F6082NAS_BOARD_MAC_INFO_NUM 0x2 +#define RD_88F6082NAS_BOARD_GPP_INFO_NUM 0x6 +#define RD_88F6082NAS_BOARD_DEBUG_LED_NUM 0x0 +#define RD_88F6082NAS_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F6082NAS_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_BOARD_TWSI_INFO rd88f6082NasInfoBoardTwsiDev[RD_88F6082NAS_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f6082NasInfoBoardMacInfo[RD_88F6082NAS_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}, + {BOARD_MAC_SPEED_AUTO, 0x9}, + }; + +MV_BOARD_GPP_INFO rd88f6082NasInfoBoardGppInfo[RD_88F6082NAS_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RESET, 0}, + {BOARD_DEV_POWER_BUTTON, 2}, + {BOARD_DEV_RTC, 7}, + {BOARD_DEV_USB_VBUS, 10}, + {BOARD_DEV_HDD_POWER, 11}, + {BOARD_DEV_HDD0_POWER, 11} + }; + +MV_BOARD_MPP_INFO rd88f6082NasInfoBoardMppConfigValue[RD_88F6082NAS_BOARD_MPP_CONFIG_NUM] = +#ifndef MV_NAND_BOOT + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F6082_NAS_MPP0_7, /* mpp0_7 */ + RD_88F6082_NAS_MPP8_15, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}}, /* mppDev */ + }; +#else + {{{RD_88F6082_NAS_MPP0_7_NB, /* mpp0_7 */ + RD_88F6082_NAS_MPP8_15_NB, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}} /* mppDev */ + }; +#endif + +MV_DEV_CS_INFO rd88f6082NasInfoBoardDeCsInfo[RD_88F6082NAS_BOARD_DEVICE_CONFIG_NUM] = +#if defined(MV_NAND) || defined(MV_NAND_BOOT) + /*{params, devType, devWidth}*/ + {{ 0, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#else + /*{deviceCS, params, devType, devWidth}*/ + {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_INFO rd88f6082NasInfo = { + "RD-88F6082-NAS-B", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6082NAS_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6082NasInfoBoardMppConfigValue, + 0, /* intsGppMask */ + RD_88F6082NAS_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6082NasInfoBoardDeCsInfo, + RD_88F6082NAS_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + RD_88F6082NAS_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f6082NasInfoBoardTwsiDev, + RD_88F6082NAS_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6082NasInfoBoardMacInfo, + RD_88F6082NAS_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f6082NasInfoBoardGppInfo, + RD_88F6082NAS_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + RD_88F6082_NAS_OE, /* gppOutEnVal */ + RD_88F6082_NAS_OE_VAL, /* gppOutVal */ + 0x0 /* gppPolarityVal */ +}; + + +#define RD_88F6082MICRO_DAS_NAS_BOARD_PCI_IF_NUM 0x0 +#define RD_88F6082MICRO_DAS_NAS_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F6082MICRO_DAS_NAS_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F6082MICRO_DAS_NAS_BOARD_GPP_INFO_NUM 0x8 +#define RD_88F6082MICRO_DAS_NAS_BOARD_DEBUG_LED_NUM 0x0 +#define RD_88F6082MICRO_DAS_NAS_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F6082MICRO_DAS_NAS_BOARD_DEVICE_CONFIG_NUM 0x0 + +MV_BOARD_TWSI_INFO rd88f6082uDasNasInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f6082uDasNasInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8} + }; + +MV_BOARD_GPP_INFO rd88f6082uDasNasInfoBoardGppInfo[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RESET, 0}, + {BOARD_DEV_POWER_BUTTON, 15}, + {BOARD_DEV_RESTOR_BUTTON, 5}, + {BOARD_DEV_RTC, 7}, + {BOARD_DEV_USB_VBUS, 11}, + {BOARD_DEV_HDD0_POWER, 13}, + {BOARD_DEV_FAN_POWER, 12}, + {BOARD_DEV_POWER_ON_LED, 6} + }; + +MV_BOARD_MPP_INFO rd88f6082uDasNasInfoBoardMppConfigValue[] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F6082_MICRO_DAS_NAS_MPP0_7, /* mpp0_7 */ + RD_88F6082_MICRO_DAS_NAS_MPP8_15, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}} /* mppDev */ + }; + + +MV_BOARD_INFO rd88f6082uDasNasInfo = { + "RD-88F6082-MICRO-DAS-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6082MICRO_DAS_NAS_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6082uDasNasInfoBoardMppConfigValue, + 0, /* intsGppMask */ + RD_88F6082MICRO_DAS_NAS_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + NULL, + RD_88F6082MICRO_DAS_NAS_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + RD_88F6082MICRO_DAS_NAS_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f6082uDasNasInfoBoardTwsiDev, + RD_88F6082MICRO_DAS_NAS_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6082uDasNasInfoBoardMacInfo, + RD_88F6082MICRO_DAS_NAS_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f6082uDasNasInfoBoardGppInfo, + RD_88F6082MICRO_DAS_NAS_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + RD_88F6082_MICRO_DAS_NAS_OE, /* gppOutEnVal */ + RD_88F6082_MICRO_DAS_NAS_OE_VAL, /* gppOutVal */ + BIT15 /* gppPolarityVal */ +}; + +#define RD_88F6082_DX243_BOARD_PCI_IF_NUM 0x0 +#define RD_88F6082_DX243_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F6082_DX243_BOARD_MAC_INFO_NUM 0x2 +#define RD_88F6082_DX243_BOARD_GPP_INFO_NUM 0x2 +#define RD_88F6082_DX243_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F6082_DX243_BOARD_DEVICE_CONFIG_NUM 0x1 +#define RD_88F6082_DX243_BOARD_DEBUG_LED_NUM 0x2 + +MV_U8 rd88f6082Dx243InfoBoardDebugLedIf[] = + {1, 2}; + +MV_BOARD_TWSI_INFO rd88f6082Dx243InfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f6082Dx243InfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}, + {BOARD_MAC_SPEED_AUTO, 0x9} + }; + +MV_BOARD_GPP_INFO rd88f6082Dx243InfoBoardGppInfo[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RESET, 0}, + {BOARD_DEV_RTC, 7}}; + +MV_BOARD_MPP_INFO rd88f6082Dx243InfoBoardMppConfigValue[] = +#ifndef MV_NAND_BOOT + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F6082_DX243_MPP0_7, /* mpp0_7 */ + RD_88F6082_DX243_MPP8_15, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}} /* mppDev */ + }; +#else + {{{RD_88F6082_DX243_MPP0_7_NB, /* mpp0_7 */ + RD_88F6082_DX243_MPP8_15_NB, /* mpp8_15 */ + N_A, /* mpp16_23 */ + N_A}} /* mppDev */ + }; +#endif + +#if defined(MV_NAND) || defined(MV_NAND_BOOT) +MV_DEV_CS_INFO rd88f6082Dx243InfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#else +MV_DEV_CS_INFO rd88f6082Dx243InfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_INFO rd88f6082Dx243Info = { + "RD-DX243-6082-24G", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6082_DX243_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6082Dx243InfoBoardMppConfigValue, + ((1 << 10) | (1 << 11) | (1 << 7)), /* intsGppMask */ + RD_88F6082_DX243_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6082Dx243InfoBoardDeCsInfo, + RD_88F6082_DX243_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + RD_88F6082_DX243_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f6082Dx243InfoBoardTwsiDev, + RD_88F6082_DX243_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6082Dx243InfoBoardMacInfo, + RD_88F6082_DX243_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f6082Dx243InfoBoardGppInfo, + RD_88F6082_DX243_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f6082Dx243InfoBoardDebugLedIf, + N_A, /* ledsPolarity */ + RD_88F6082_DX243_OE, /* gppOutEnVal */ + RD_88F6082_DX243_OE_VAL, /* gppOutVal */ + (BIT1 | BIT2) /* gppPolarityVal */ +}; + +MV_BOARD_INFO* boardInfoTbl[] = {&db88f6082BpInfo, + NULL, + &rd88f6082NasInfo, + NULL, + &db88f6082LBpInfo, + NULL, + &rd88f6082uDasNasInfo, + &rd88f6082Dx243Info + }; + + + +#define BOARD_ID_BASE BOARD_ID_88F6082_BASE +#define MV_MAX_BOARD_ID BOARD_ID_88F6082_MAX diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6082BoardEnv.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6082BoardEnv.h new file mode 100644 index 0000000..16efb46 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6082BoardEnv.h @@ -0,0 +1,119 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoard88F6082BoardEnvSpech +#define __INCmvBoard88F6082BoardEnvSpech + + +/* 88F6082 based boards ID numbers */ +/* =============================== */ +#define BOARD_ID_88F6082_BASE 0x70 + +/* New board ID numbers */ +#define DB_88F6082_BP (BOARD_ID_88F6082_BASE+0x0) +#define RD_88F6082_NAS (BOARD_ID_88F6082_BASE+0x2) +#define DB_88F6082L_BP (BOARD_ID_88F6082_BASE+0x4) +#define RD_88F6082_MICRO_DAS_NAS (BOARD_ID_88F6082_BASE+0x6) +#define RD_88F6082_DX243_24G (BOARD_ID_88F6082_BASE+0x7) +#define BOARD_ID_88F6082_MAX (BOARD_ID_88F6082_BASE+0x8) + + +#define RD_88F6082_NAS_MPP0_7 0x01111300 +#define RD_88F6082_NAS_MPP8_15 0x11110011 +#define RD_88F6082_NAS_MPP0_7_NB 0x01111300 +#define RD_88F6082_NAS_MPP8_15_NB 0x11110011 +#define RD_88F6082_NAS_OE 0xFFFFF7FF +#define RD_88F6082_NAS_OE_VAL 0x0 + +#define DB_88F6082_BP_MPP0_7 0x01111000 +#define DB_88F6082_BP_MPP8_15 0x22221111 +#define DB_88F6082_BP_MPP0_7_NB 0x01111000 +#define DB_88F6082_BP_MPP8_15_NB 0x11111111 +#define DB_88F6082_BP_OE 0xFFFFFF79 +#define DB_88F6082_BP_OE_VAL 0x86 + +#define DB_88F6082L_BP_MPP0_7 0x01111000 +#define DB_88F6082L_BP_MPP8_15 0x22221111 +#define DB_88F6082L_BP_MPP0_7_NB 0x01111000 +#define DB_88F6082L_BP_MPP8_15_NB 0x11111111 +#define DB_88F6082L_BP_OE 0xFFFFFF79 +#define DB_88F6082L_BP_OE_VAL BIT7 + +/* The MPP config and output enable is delibarate done for input. + The change from input to output for example on the HDD power MPP + is done inside the code when setting the power enable. */ +#define RD_88F6082_MICRO_DAS_NAS_MPP0_7 0x00001000 +#define RD_88F6082_MICRO_DAS_NAS_MPP8_15 0x00000011 +#define RD_88F6082_MICRO_DAS_NAS_OE 0xFFFFFFFF +#define RD_88F6082_MICRO_DAS_NAS_OE_VAL 0x0 + +#define RD_88F6082_DX243_MPP0_7 0x01110000 +#define RD_88F6082_DX243_MPP8_15 0x22220011 +#define RD_88F6082_DX243_MPP0_7_NB 0x01110000 +#define RD_88F6082_DX243_MPP8_15_NB 0x11110011 +#define RD_88F6082_DX243_OE 0xFFFFFFF9 +#define RD_88F6082_DX243_OE_VAL 0x0 + +#endif /* __INCmvBoard88F6082EnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183BoardEnv.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183BoardEnv.c new file mode 100644 index 0000000..6004ea5 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183BoardEnv.c @@ -0,0 +1,275 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define DB_88F6183BP_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6183BP_BOARD_TWSI_DEF_NUM 0x2 +#define DB_88F6183BP_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F6183BP_BOARD_GPP_INFO_NUM 0x3 +#define DB_88F6183BP_BOARD_DEBUG_LED_NUM 0x4 +#define DB_88F6183BP_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F6183BP_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_U8 db88f6183BpInfoBoardDebugLedIf[DB_88F6183BP_BOARD_DEBUG_LED_NUM] = + {24,25,26,27}; + +MV_BOARD_TWSI_INFO db88f6183BpInfoBoardTwsiDev[DB_88F6183BP_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}, + {BOARD_DEV_AUDIO_DEC, 0x4B, ADDR7_BIT} + }; + +MV_BOARD_MAC_INFO db88f6183BpInfoBoardMacInfo[DB_88F6183BP_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}, + }; + +MV_BOARD_GPP_INFO db88f6183BpInfoBoardGppInfo[DB_88F6183BP_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_USB_VBUS, 14}, + {BOARD_DEV_RESET, 20}, + {BOARD_DEV_SDIO_DETECT, 15} + }; + +MV_BOARD_MPP_INFO db88f6183BpInfoBoardMppConfigValue[DB_88F6183BP_BOARD_MPP_CONFIG_NUM] = +#ifndef MV_NAND_BOOT + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F6183_BP_MPP0_7, /* mpp0_7 */ + DB_88F6183_BP_MPP8_15, /* mpp8_15 */ + DB_88F6183_BP_MPP16_23, /* mpp16_23 */ + DB_88F6183_BP_MPP24_31}} /* mpp24_31 */ + }; +#else + {{{DB_88F6183_BP_MPP0_7_NB, /* mpp0_7 */ + DB_88F6183_BP_MPP8_15_NB, /* mpp8_15 */ + DB_88F6183_BP_MPP16_23_NB, /* mpp16_23 */ + DB_88F6183_BP_MPP24_31_NB}} /* mpp24_31 */ + }; +#endif + +#if defined(MV_NAND) || defined(MV_NAND_BOOT) +MV_DEV_CS_INFO db88f6183BpInfoBoardDeCsInfo[DB_88F6183BP_BOARD_DEVICE_CONFIG_NUM] = + /*{deviceCS, params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#else +MV_DEV_CS_INFO db88f6183BpInfoBoardDeCsInfo[DB_88F6183BP_BOARD_DEVICE_CONFIG_NUM] = + /*{deviceCS, params, devType, devWidth}*/ + {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_INFO db88f6183BpInfo = { + "DB-88F6183-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6183BP_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6183BpInfoBoardMppConfigValue, + 0, /* intsGppMask */ + DB_88F6183BP_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6183BpInfoBoardDeCsInfo, + DB_88F6183BP_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + DB_88F6183BP_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6183BpInfoBoardTwsiDev, + DB_88F6183BP_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6183BpInfoBoardMacInfo, + DB_88F6183BP_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f6183BpInfoBoardGppInfo, + DB_88F6183BP_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + db88f6183BpInfoBoardDebugLedIf, + N_A, /* ledsPolarity */ + DB_88F6183_BP_OE, /* gppOutEnVal */ + DB_88F6183_BP_OE_VAL, /* gppOutVal */ + 0x1, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + +#define RD_88F6183GP_BOARD_PCI_IF_NUM 0x0 +#define RD_88F6183GP_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F6183GP_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F6183GP_BOARD_GPP_INFO_NUM 0x3 +#define RD_88F6183GP_BOARD_DEBUG_LED_NUM 0x0 +#define RD_88F6183GP_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F6183GP_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_BOARD_TWSI_INFO rd88f6183GpInfoBoardTwsiDev[RD_88F6183GP_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f6183GpInfoBoardMacInfo[RD_88F6183GP_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8} + }; + +MV_BOARD_GPP_INFO rd88f6183GpInfoBoardGppInfo[RD_88F6183GP_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RESET, 20}, + {BOARD_DEV_RTC, 31}, + {BOARD_DEV_SDIO_DETECT, 9} + }; + +MV_BOARD_MPP_INFO rd88f6183GpInfoBoardMppConfigValue[RD_88F6183GP_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F6183_GP_MPP0_7, /* mpp0_7 */ + RD_88F6183_GP_MPP8_15, /* mpp8_15 */ + RD_88F6183_GP_MPP16_23, /* mpp16_23 */ + RD_88F6183_GP_MPP24_31}} /* mpp24_31 */ + }; + +MV_DEV_CS_INFO rd88f6183GpInfoBoardDeCsInfo[RD_88F6183GP_BOARD_DEVICE_CONFIG_NUM] = + /*{deviceCS, params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ + +MV_BOARD_INFO rd88f6183GpInfo = { + "RD-88F6183-GP", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6183GP_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6183GpInfoBoardMppConfigValue, + 0, /* intsGppMask */ + RD_88F6183GP_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6183GpInfoBoardDeCsInfo, + RD_88F6183GP_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + RD_88F6183GP_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f6183GpInfoBoardTwsiDev, + RD_88F6183GP_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6183GpInfoBoardMacInfo, + RD_88F6183GP_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f6183GpInfoBoardGppInfo, + RD_88F6183GP_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + RD_88F6183_GP_OE, /* gppOutEnVal */ + RD_88F6183_GP_OE_VAL, /* gppOutVal */ + BIT15, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + +#define RD_88F6183AP_BOARD_PCI_IF_NUM 0x0 +#define RD_88F6183AP_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F6183AP_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F6183AP_BOARD_GPP_INFO_NUM 0x3 +#define RD_88F6183AP_BOARD_DEBUG_LED_NUM 0x0 +#define RD_88F6183AP_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F6183AP_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_BOARD_TWSI_INFO rd88f6183ApInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88f6183ApInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_1000M, 0x10} + }; + +MV_BOARD_SWITCH_INFO rd88f6183ApInfoBoardSwitchInfo[] = + /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, + MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ + {{-1, {4, 3, 2, 1, 0}, 5, 1, 0}}; + +MV_BOARD_GPP_INFO rd88f6183ApInfoBoardGppInfo[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RESET, 20}, + {BOARD_DEV_RTC, 1}, + {BOARD_DEV_SWITCH_PHY_INT, 3} + }; + +MV_BOARD_MPP_INFO rd88f6183ApInfoBoardMppConfigValue[] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F6183_AP_MPP0_7, /* mpp0_7 */ + RD_88F6183_AP_MPP8_15, /* mpp8_15 */ + RD_88F6183_AP_MPP16_23, /* mpp16_23 */ + RD_88F6183_AP_MPP24_31}} /* mpp24_31 */ + }; + +MV_DEV_CS_INFO rd88f6183ApInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ + +MV_BOARD_INFO rd88f6183ApInfo = { + "RD-88F6183-AP-GE", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6183AP_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6183ApInfoBoardMppConfigValue, + 0, /* intsGppMask */ + RD_88F6183AP_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6183ApInfoBoardDeCsInfo, + RD_88F6183AP_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + RD_88F6183AP_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f6183ApInfoBoardTwsiDev, + RD_88F6183AP_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6183ApInfoBoardMacInfo, + RD_88F6183AP_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f6183ApInfoBoardGppInfo, + RD_88F6183AP_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + RD_88F6183_AP_OE, /* gppOutEnVal */ + RD_88F6183_AP_OE_VAL, /* gppOutVal */ + BIT15, /* gppPolarityVal */ + rd88f6183ApInfoBoardSwitchInfo /* pSwitchInfo */ +}; +MV_BOARD_INFO* boardInfoTbl[] = {&db88f6183BpInfo, + &rd88f6183GpInfo, + &rd88f6183ApInfo + }; + + +#define BOARD_ID_BASE BOARD_ID_88F6183_BASE +#define MV_MAX_BOARD_ID BOARD_ID_88F6183_MAX diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183BoardEnv.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183BoardEnv.h new file mode 100644 index 0000000..c0bd490 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183BoardEnv.h @@ -0,0 +1,108 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoard88F6183BoardEnvSpech +#define __INCmvBoard88F6183BoardEnvSpech + + +/* 88F6183 based boards ID numbers */ +/* =============================== */ +#define BOARD_ID_88F6183_BASE 0x90 + +/* New board ID numbers */ +#define DB_88F6183_BP (BOARD_ID_88F6183_BASE+0x0) +#define RD_88F6183_GP (BOARD_ID_88F6183_BASE+0x1) +#define RD_88F6183_AP (BOARD_ID_88F6183_BASE+0x2) +#define BOARD_ID_88F6183_MAX (BOARD_ID_88F6183_BASE+0x3) + +#define DB_88F6183_BP_MPP0_7 0x00111111 +#define DB_88F6183_BP_MPP8_15 0x00222200 +#define DB_88F6183_BP_MPP16_23 0x00010000 +#define DB_88F6183_BP_MPP24_31 0x00000000 +#define DB_88F6183_BP_MPP0_7_NB 0x00111111 +#define DB_88F6183_BP_MPP8_15_NB 0x00111100 +#define DB_88F6183_BP_MPP16_23_NB 0x00010000 +#define DB_88F6183_BP_MPP24_31_NB 0x00000000 +#define DB_88F6183_BP_OE 0x00A0C03B +#define DB_88F6183_BP_OE_VAL 0xF2BFFFFF + +#define RD_88F6183_GP_MPP0_7 0x00111111 +#define RD_88F6183_GP_MPP8_15 0x00111100 +#define RD_88F6183_GP_MPP16_23 0x00000011 +#define RD_88F6183_GP_MPP24_31 0x00000011 +#define RD_88F6183_GP_OE 0xFFFFFFFF +#define RD_88F6183_GP_OE_VAL 0x0 + +#define RD_88F6183_AP_MPP0_7 0x00000000 +#define RD_88F6183_AP_MPP8_15 0x00222200 +#define RD_88F6183_AP_MPP16_23 0x00000000 +#define RD_88F6183_AP_MPP24_31 0x00000000 +#define RD_88F6183_AP_OE 0x00003C1F +#define RD_88F6183_AP_OE_VAL BIT20 + +#undef MV_BOARD_DEFAULT_TCLK +#define MV_BOARD_DEFAULT_TCLK MV_BOARD_TCLK_133MHZ /* Default Tclk 133MHz */ + +#endif /* __INCmvBoard88F6183EnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183LBoardEnv.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183LBoardEnv.c new file mode 100644 index 0000000..2d7c4ac --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183LBoardEnv.c @@ -0,0 +1,143 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define DB_88F6183LBP_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6183LBP_BOARD_TWSI_DEF_NUM 0x2 +#define DB_88F6183LBP_BOARD_MAC_INFO_NUM 0x0 +#define DB_88F6183LBP_BOARD_GPP_INFO_NUM 0x3 +#define DB_88F6183LBP_BOARD_DEBUG_LED_NUM 0x4 +#define DB_88F6183LBP_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F6183LBP_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_U8 db88f6183LBpInfoBoardDebugLedIf[DB_88F6183LBP_BOARD_DEBUG_LED_NUM] = + {24,25,26,27}; + +MV_BOARD_TWSI_INFO db88f6183LBpInfoBoardTwsiDev[DB_88F6183LBP_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}, + {BOARD_DEV_AUDIO_DEC, 0x4B, ADDR7_BIT} + }; + +MV_BOARD_GPP_INFO db88f6183LBpInfoBoardGppInfo[DB_88F6183LBP_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_USB_VBUS, 14}, + {BOARD_DEV_RESET, 20}, + {BOARD_DEV_SDIO_DETECT, 15} + }; + +MV_BOARD_MPP_INFO db88f6183LBpInfoBoardMppConfigValue[DB_88F6183LBP_BOARD_MPP_CONFIG_NUM] = +#ifndef MV_NAND_BOOT + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88F6183_BP_MPP0_7, /* mpp0_7 */ + DB_88F6183_BP_MPP8_15, /* mpp8_15 */ + DB_88F6183_BP_MPP16_23, /* mpp16_23 */ + DB_88F6183_BP_MPP24_31}} /* mpp24_31 */ + }; +#else + {{{DB_88F6183_BP_MPP0_7_NB, /* mpp0_7 */ + DB_88F6183_BP_MPP8_15_NB, /* mpp8_15 */ + DB_88F6183_BP_MPP16_23_NB, /* mpp16_23 */ + DB_88F6183_BP_MPP24_31_NB}} /* mpp24_31 */ + }; +#endif + +#if defined(MV_NAND) || defined(MV_NAND_BOOT) +MV_DEV_CS_INFO db88f6183LBpInfoBoardDeCsInfo[DB_88F6183LBP_BOARD_DEVICE_CONFIG_NUM] = + /*{deviceCS, params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#else +MV_DEV_CS_INFO db88f6183LBpInfoBoardDeCsInfo[DB_88F6183LBP_BOARD_DEVICE_CONFIG_NUM] = + /*{deviceCS, params, devType, devWidth}*/ + {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_INFO db88f6183LBpInfo = { + "DB-88F6183L-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6183LBP_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6183LBpInfoBoardMppConfigValue, + 0, /* intsGppMask */ + DB_88F6183LBP_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6183LBpInfoBoardDeCsInfo, + DB_88F6183LBP_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + NULL, + DB_88F6183LBP_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6183LBpInfoBoardTwsiDev, + DB_88F6183LBP_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + NULL, + DB_88F6183LBP_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f6183LBpInfoBoardGppInfo, + DB_88F6183LBP_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + db88f6183LBpInfoBoardDebugLedIf, + N_A, /* ledsPolarity */ + DB_88F6183L_BP_OE, /* gppOutEnVal */ + DB_88F6183L_BP_OE_VAL, /* gppOutVal */ + 0x1, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + +MV_BOARD_INFO* boardInfoTbl[] = {&db88f6183LBpInfo}; + + +#define BOARD_ID_BASE BOARD_ID_88F6183L_BASE +#define MV_MAX_BOARD_ID BOARD_ID_88F6183L_MAX diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183LBoardEnv.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183LBoardEnv.h new file mode 100644 index 0000000..df5475b --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88F6183LBoardEnv.h @@ -0,0 +1,88 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoard88F6183LBoardEnvSpech +#define __INCmvBoard88F6183LBoardEnvSpech + + +/* 88F6183L based boards ID numbers */ +/* =============================== */ +#define BOARD_ID_88F6183L_BASE 0xa0 + +/* New board ID numbers */ +#define DB_88F6183L_BP (BOARD_ID_88F6183L_BASE+0x0) +#define BOARD_ID_88F6183L_MAX (BOARD_ID_88F6183L_BASE+0x1) + +#define DB_88F6183L_BP_MPP0_7 0x00000000 +#define DB_88F6183L_BP_MPP8_15 0x00222200 +#define DB_88F6183L_BP_MPP16_23 0x00010000 +#define DB_88F6183L_BP_MPP24_31 0x00000000 +#define DB_88F6183L_BP_MPP0_7_NB 0x00000000 +#define DB_88F6183L_BP_MPP8_15_NB 0x00111100 +#define DB_88F6183L_BP_MPP16_23_NB 0x00010000 +#define DB_88F6183L_BP_MPP24_31_NB 0x00000000 +#define DB_88F6183L_BP_OE 0x00A0C000 +#define DB_88F6183L_BP_OE_VAL 0xF2BFFFFF +#endif /* __INCmvBoard88F6183LEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88W8660BoardEnv.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88W8660BoardEnv.c new file mode 100644 index 0000000..5b18031 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88W8660BoardEnv.c @@ -0,0 +1,297 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#define DB_88W8660_BOARD_PCI_IF_NUM 0x3 +#define DB_88W8660_BOARD_TWSI_DEF_NUM 0x1 +#define DB_88W8660_BOARD_MAC_INFO_NUM 0x1 +#define DB_88W8660_BOARD_GPP_INFO_NUM 0x1 +#define DB_88W8660_BOARD_DEBUG_LED_NUM 0x0 +#define DB_88W8660_BOARD_MPP_CONFIG_NUM 0x2 +#define DB_88W8660_BOARD_DEVICE_CONFIG_NUM 0x4 + +MV_BOARD_PCI_IF db88w8660ddr2InfoBoardPciIf[DB_88W8660_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {0, 0, 0, 0}}, /* pciSlot0 */ + {8, {9, 9, 9, 9}}, /* pciSlot1 */ + {9, {11, 11, 11, 11}}}; /* pciSlot2 */ + +MV_BOARD_TWSI_INFO db88w8660ddr2InfoBoardTwsiDev[DB_88W8660_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO db88w8660ddr2InfoBoardMacInfo[DB_88W8660_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +MV_BOARD_GPP_INFO db88w8660ddr2InfoBoardGppInfo[DB_88W8660_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 10}}; + +MV_BOARD_MPP_INFO db88w8660ddr2InfoBoardMppConfigValue[DB_88W8660_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{DB_88W8660_DDR2_MPP0_7, /* mpp0_7 */ + DB_88W8660_DDR2_MPP8_15, /* mpp8_15 */ + N_A, + N_A}}, + {{DB_88W8660_DDR2_MPP0_7NB, /* mpp0_7 */ + DB_88W8660_DDR2_MPP8_15NB, /* mpp8_15 */ + N_A, + N_A}} + }; + +MV_DEV_CS_INFO db88w8660ddr2InfoBoardDeCsInfo[DB_88W8660_BOARD_DEVICE_CONFIG_NUM] = +#if defined(MV_NAND_BOOT) + /*{params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs0 */ + {1, 0x8fdfffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + {2, N_A, N_A}, + {3,0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}}; /* bootCs */ +#else + /*{params, devType, devWidth}*/ + {{0, 0x8fcfffff, BOARD_DEV_SEVEN_SEG, N_A}, /* devCs0 */ + {1, 0x8fdfffff, BOARD_DEV_NOR_FLASH, 16}, /* devCs1 */ + {2, N_A, N_A}, /* devCs2/flashCs */ + {3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ +#endif +MV_BOARD_INFO db88w8660ddr2Info = { + "DB-88W8660-DDR2", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88W8660_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88w8660ddr2InfoBoardMppConfigValue, + ((1<<9)|(1 << 10)|(1<<11)), /* intsGppMask */ + DB_88W8660_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88w8660ddr2InfoBoardDeCsInfo, + DB_88W8660_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88w8660ddr2InfoBoardPciIf, + DB_88W8660_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88w8660ddr2InfoBoardTwsiDev, + DB_88W8660_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88w8660ddr2InfoBoardMacInfo, + DB_88W8660_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88w8660ddr2InfoBoardGppInfo, + DB_88W8660_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + N_A, /* ledsPolarity */ + DB_88W8660_DDR2_OUT_EN, /* gppOutEnVal */ + DB_88W8660_DDR2_OUT_VAL, /* gppOutVal */ + 0xA00, /* gppPolarityVal */ + NULL /* pSwitchInfo */ +}; + +#define RD_88W8660_BOARD_PCI_IF_NUM 0x1 +#define RD_88W8660_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88W8660_BOARD_MAC_INFO_NUM 0x1 +#define RD_88W8660_BOARD_GPP_INFO_NUM 0x1 +#define RD_88W8660_BOARD_DEBUG_LED_NUM 0x3 +#define RD_88W8660_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88W8660_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_U8 rd88w8660InfoBoardDebugLedIf[RD_88W8660_BOARD_DEBUG_LED_NUM] = + {6, 5, 7}; + +MV_BOARD_PCI_IF rd88w8660InfoBoardPciIf[RD_88W8660_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {4, 3, N_A, N_A}}}; /* pciSlot0 */ + +MV_BOARD_TWSI_INFO rd88w8660InfoBoardTwsiDev[RD_88W8660_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88w8660InfoBoardMacInfo[RD_88W8660_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_100M, 0x0}}; + +MV_BOARD_SWITCH_INFO rd88w8660InfoBoardSwitchInfo[] = + /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, + MV_32 qdCpuPort, MV_32 smiScanMode} */ + {{9, {0, 1, 2, 3, 4}, 5, 0}}; + +MV_BOARD_GPP_INFO rd88w8660InfoBoardGppInfo[RD_88W8660_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 11}}; + +MV_BOARD_MPP_INFO rd88w8660ddr1InfoBoardMppConfigValue[RD_88W8660_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88W8660_MPP0_7, /* mpp0_7 */ + RD_88W8660_MPP8_15, /* mpp8_15 */ + N_A, + N_A}}}; + + +MV_DEV_CS_INFO rd88w8660InfoBoardDeCsInfo[RD_88W8660_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ + +MV_BOARD_INFO rd88w8660Info = { + "RD-88W8660", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88W8660_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88w8660ddr1InfoBoardMppConfigValue, + ((1<<3)|(1<<4)|(1<<9)|(1<<11)), /* intsGppMask */ + RD_88W8660_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88w8660InfoBoardDeCsInfo, + RD_88W8660_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + rd88w8660InfoBoardPciIf, + RD_88W8660_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88w8660InfoBoardTwsiDev, + RD_88W8660_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88w8660InfoBoardMacInfo, + RD_88W8660_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88w8660InfoBoardGppInfo, + RD_88W8660_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88w8660InfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88W8660_BOARD_OUT_EN, /* gppOutEnVal */ + RD_88W8660_BOARD_OUT_VAL, /* gppOutVal */ + RD_88W8660_BOARD_MPP_POLAR, /* gppPolarityVal */ + rd88w8660InfoBoardSwitchInfo /* pSwitchInfo */ +}; + + +#define RD_88W8660_AP82S_BOARD_PCI_IF_NUM 0x1 +#define RD_88W8660_AP82S_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88W8660_AP82S_BOARD_MAC_INFO_NUM 0x1 +#define RD_88W8660_AP82S_BOARD_GPP_INFO_NUM 0x1 +#define RD_88W8660_AP82S_BOARD_DEBUG_LED_NUM 0x1 +#define RD_88W8660_AP82S_BOARD_MPP_CONFIG_NUM 0x2 +#define RD_88W8660_AP82S_BOARD_DEVICE_CONFIG_NUM 0x1 + +MV_U8 rd88w8660Ap82sInfoBoardDebugLedIf[RD_88W8660_BOARD_DEBUG_LED_NUM] = + {6}; + +MV_BOARD_PCI_IF rd88w8660Ap82sInfoBoardPciIf[RD_88W8660_AP82S_BOARD_PCI_IF_NUM] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {8, 3, 8, 8}}}; /* pciSlot0 */ + +MV_BOARD_TWSI_INFO rd88w8660Ap82sInfoBoardTwsiDev[RD_88W8660_AP82S_BOARD_TWSI_DEF_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_DEV_RTC, 0x68, ADDR7_BIT}}; + +MV_BOARD_MAC_INFO rd88w8660Ap82sInfoBoardMacInfo[RD_88W8660_AP82S_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_100M, 0x0}}; + +MV_BOARD_SWITCH_INFO rd88w8660Ap82sInfoBoardSwitchInfo[] = + /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, + MV_32 qdCpuPort, MV_32 smiScanMode} */ + {{-1, {0, 1, 2, 3, 4}, 5, 0}}; + +MV_BOARD_GPP_INFO rd88w8660Ap82sInfoBoardGppInfo[RD_88W8660_AP82S_BOARD_GPP_INFO_NUM] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_DEV_RTC, 11}}; + +MV_BOARD_MPP_INFO rd88w8660Ap82sInfoBoardMppConfigValue[RD_88W8660_AP82S_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88W8660_AP82S_MPP0_7, /* mpp0_7 */ + RD_88W8660_AP82S_MPP8_15, + N_A, + N_A}}, + {{RD_88W8660_AP82S_MPP0_7NB, /* mpp0_7 */ + N_A, + N_A, + N_A}} + }; + +MV_DEV_CS_INFO rd88w8660Ap82sInfoBoardDeCsInfo[RD_88W8660_AP82S_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ +#if defined(MV_NAND_BOOT) + {{3, 0x8fcfffff, BOARD_DEV_NAND_FLASH, 8}}; /* bootCs */ +#else + {{3, 0x8fcfffff, BOARD_DEV_NOR_FLASH, 8}}; /* bootCs */ +#endif + + +MV_BOARD_INFO rd88w8660Ap82sInfo = { + "RD-88W8660-AP82S", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88W8660_AP82S_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88w8660Ap82sInfoBoardMppConfigValue, + ((1<<2)|(1<<3)|(1<<8)|(1<<9)|(1<<11)), /* intsGppMask */ + RD_88W8660_AP82S_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88w8660Ap82sInfoBoardDeCsInfo, + RD_88W8660_AP82S_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + rd88w8660Ap82sInfoBoardPciIf, + RD_88W8660_AP82S_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88w8660Ap82sInfoBoardTwsiDev, + RD_88W8660_AP82S_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88w8660Ap82sInfoBoardMacInfo, + RD_88W8660_AP82S_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88w8660Ap82sInfoBoardGppInfo, + RD_88W8660_AP82S_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88w8660Ap82sInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88W8660_AP82S_OUT_EN, /* gppOutEnVal */ + RD_88W8660_AP82S_OUT_VAL, /* gppOutVal */ + RD_88W8660_AP82S_MPP_POLAR, /* gppPolarityVal */ + rd88w8660Ap82sInfoBoardSwitchInfo /* pSwitchInfo */ + +}; + +MV_BOARD_INFO* boardInfoTbl[3] = {&db88w8660ddr2Info, + &rd88w8660Info, + &rd88w8660Ap82sInfo + }; + + +#define BOARD_ID_BASE BOARD_ID_88W8660_BASE +#define MV_MAX_BOARD_ID BOARD_ID_88W8660_MAX + diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88W8660BoardEnv.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88W8660BoardEnv.h new file mode 100644 index 0000000..e2df113 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mv88W8660BoardEnv.h @@ -0,0 +1,106 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoard88W8660EnvSpech +#define __INCmvBoard88W8660EnvSpech + + +/* 88W8660 based boards ID numbers */ +/* =============================== */ +#define BOARD_ID_88W8660_BASE 0x40 +/* Old board ID numbers for backward compatability */ +#define DB_88W8660_DDR2_OLD 0x10 +#define RD_88W8660_DDR1_OLD 0x11 +#define RD_88W8660_AP82S_DDR1_OLD 0x12 +/* New board ID numbers */ +#define DB_88W8660_DDR2 (BOARD_ID_88W8660_BASE+0x0) +#define RD_88W8660_DDR1 (BOARD_ID_88W8660_BASE+0x1) +#define RD_88W8660_AP82S_DDR1 (BOARD_ID_88W8660_BASE+0x2) +#define BOARD_ID_88W8660_MAX (BOARD_ID_88W8660_BASE+0x3) + + + +#define RD_88W8660_MPP0_7 0x0 +#define RD_88W8660_MPP8_15 0x0 +#define RD_88W8660_BOARD_OUT_EN 0xFFF1C +#define RD_88W8660_BOARD_OUT_VAL 0xE3 +#define RD_88W8660_BOARD_MPP_POLAR 0xA18 + +#define DB_88W8660_DDR2_MPP0_7 0x00002222 +#define DB_88W8660_DDR2_MPP8_15 0x00000002 +#define DB_88W8660_DDR2_MPP0_7NB 0x00442222 +#define DB_88W8660_DDR2_MPP8_15NB 0x00000002 +#define DB_88W8660_DDR2_OUT_EN 0xFFF5 +#define DB_88W8660_DDR2_OUT_VAL 0x0 + + +#define RD_88W8660_AP82S_MPP0_7 0x22 +#define RD_88W8660_AP82S_MPP8_15 0x0 +#define RD_88W8660_AP82S_MPP0_7NB 0x440022 +#define RD_88W8660_AP82S_OUT_EN 0xBBF +#define RD_88W8660_AP82S_OUT_VAL (BIT10 | BIT7) +#define RD_88W8660_AP82S_MPP_POLAR 0xB04 + +#endif /* __INCmvBoard88W8660EnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvLib.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvLib.c new file mode 100644 index 0000000..1a6a41e --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvLib.c @@ -0,0 +1,2030 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "cntmr/mvCntmr.h" +#include "gpp/mvGpp.h" +#include "twsi/mvTwsi.h" +#include "pci-if/mvPciIf.h" +#include "device/mvDevice.h" + +#if defined(DB_CUSTOMER) +#include "boardEnv/mvCustomerBoardEnv.c" +#elif defined(MV_88F5180N) +#include "boardEnv/mv88F5180NBoardEnv.c" +#elif defined(MV_88F5181) +#include "boardEnv/mv88F5181BoardEnv.c" +#elif defined(MV_88F5181L) +#include "boardEnv/mv88F5181LBoardEnv.c" +#elif defined(MV_88F5182) +#include "boardEnv/mv88F5182BoardEnv.c" +#elif defined(MV_88F5082) +#include "boardEnv/mv88F5082BoardEnv.c" +#elif defined(MV_88W8660) +#include "boardEnv/mv88W8660BoardEnv.c" +#elif defined(MV_88F1281) +#include "boardEnv/mv88F1281BoardEnv.c" +#elif defined(MV_88F6082) +#include "boardEnv/mv88F6082BoardEnv.c" +#elif defined(MV_88F6183) +#include "boardEnv/mv88F6183BoardEnv.c" +#elif defined(MV_88F6183L) +#include "boardEnv/mv88F6183LBoardEnv.c" +#endif + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; + +#define CODE_IN_ROM MV_FALSE +#define CODE_IN_RAM MV_TRUE + +#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] + +/* Locals */ +static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +MV_U32 tClkRate = -1; + + +/******************************************************************************* +* mvBoardEnvInit - Init board +* +* DESCRIPTION: +* In this function the board environment take care of device bank +* initialization. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardEnvInit(MV_VOID) +{ + MV_U32 devNum; + MV_U32 csNum; + MV_U32 devBankParam=0; + MV_U32 boardId= mvBoardIdGet(); + +#if defined(MV_INCLUDE_GIG_ETH) + MV_U32 regVal; +#endif + + + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); + return; + + } + + /* Set GPP Out value */ + MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutVal); + + /* set GPP polarity */ + mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityVal); + + /* Set GPP Out Enable*/ + mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnVal); + + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) + { + devBankParam = BOARD_INFO(boardId)->pDevCsInfo[devNum].params; + csNum = BOARD_INFO(boardId)->pDevCsInfo[devNum].deviceCS; + + if (devBankParam == N_A) continue; + + if (devNum != MV_BOOTDEVICE_INDEX) + { + MV_REG_WRITE(DEV_BANK_PARAM_REG(csNum), devBankParam); + } + else + { + MV_U32 bootDevBankParam; + + /* for BootCS Only device width should be as in sample at + reset */ + bootDevBankParam = MV_REG_READ(DEV_BANK_PARAM_REG(devNum)); + bootDevBankParam &= DBP_DEVWIDTH_MASK; + devBankParam &= ~DBP_DEVWIDTH_MASK; + devBankParam |= bootDevBankParam; + + MV_REG_WRITE(DEV_BANK_PARAM_REG(csNum) , devBankParam); + } + } + +#if defined(MV_INCLUDE_NAND) + + if (mvCtrlNandSupport()) + { + /* If we are booting from NAND MPPs should be modified */ + /* Check NAND connected to boot device */ +#if defined(MV_88F6082) + if (((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_DBOOT_MODE_MASK) == MSAR_DBOOT_NAND) || + ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_DBOOT_MODE_MASK) == MSAR_IDBOOT_NAND)) + { + } +#else + if (MV_REG_READ(DEV_NAND_CTRL_REG) & 0x1) + { + } +#endif + else + { + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) + { + if (boardGetDevEntry(devNum, BOARD_DEV_NAND_FLASH) != NULL) + { + /* We always use don't care mode. */ + mvDevNandSet((boardGetDevEntry(devNum, BOARD_DEV_NAND_FLASH))->deviceCS, 0); + } + } + } + + } +#endif /* MV_INCLUDE_NAND */ + +#if defined(MV_INCLUDE_GIG_ETH) + + /* Guideline (GL# ETH-3) RGMII Output Delay Tuning*/ + + /* Read if we are in RGMII mode */ + regVal = MV_REG_READ(MPP_SAMPLE_AT_RESET); + + /* Check if we are in RGMII mode */ + if (MSAR_GIGA_PORT_MODE_RGMII == (regVal & MSAR_GIGA_PORT_MODE_MASK)) + { + + regVal = MV_REG_READ(DEV_RGMII_AC_TIMING_REG); + regVal &= ~0x3; + regVal |= 0x2; + MV_REG_WRITE(DEV_RGMII_AC_TIMING_REG, regVal); + } + +#endif /* MV_INCLUDE_GIG_ETH */ + +} + +/******************************************************************************* +* mvBoardModelGet - Get Board model +* +* DESCRIPTION: +* This function returns 16bit describing board model. +* Board model is constructed of one byte major and minor numbers in the +* following manner: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardModelGet(MV_VOID) +{ + return (mvBoardIdGet() >> 16); +} + +/******************************************************************************* +* mbBoardRevlGet - Get Board revision +* +* DESCRIPTION: +* This function returns a 32bit describing the board revision. +* Board revision is constructed of 4bytes. 2bytes describes major number +* and the other 2bytes describes minor munber. +* For example for board revision 3.4 the function will return +* 0x00030004. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardRevGet(MV_VOID) +{ + return (mvBoardIdGet() & 0xFFFF); +} + +/******************************************************************************* +* mvBoardNameGet - Get Board name +* +* DESCRIPTION: +* This function returns a string describing the board model and revision. +* String is extracted from board I2C EEPROM. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvBoardNameGet(char *pNameBuff) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsSPrintf (pNameBuff, "Board unknown.\n"); + return MV_ERROR; + + } + + mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); + + return MV_OK; +} +#if defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) +/******************************************************************************* +* mvBoardIsPortInSgmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE +* For all other options. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in SGMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) +{ + MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; + + if(ethPortNum >= BOARD_ETH_PORT_NUM) + { + mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); + return MV_FALSE; + } + return ethPortSgmiiSupport[ethPortNum]; +} +#endif /* MV_INCLUDE_GIG_ETH || MV_INCLUDE_UNM_ETH */ + +/******************************************************************************* +* mvBoardPhyAddrGet - Get the phy address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); + return MV_ERROR; + + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; +} + +/******************************************************************************* +* mvBoardMacSpeedGet - Get the Mac speed +* +* DESCRIPTION: +* This routine returns the Mac speed if pre define of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); + return MV_ERROR; + + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; +} + +/******************************************************************************* +* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication +* +* DESCRIPTION: +* This routine returns the IRQ number for the link status indication. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* the number of the IRQ for the link status indication, -1 if the port +* number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; +} + +/******************************************************************************* +* mvBoardSwitchPortGet - Get the mapping between the board connector and the +* Ethernet Switch port +* +* DESCRIPTION: +* This routine returns the matching Switch port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* boardPortNum - logical number of the connector on the board +* +* OUTPUT: +* None. +* +* RETURN: +* the matching Switch port, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); + return MV_ERROR; + } + if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) + { + mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; +} + +/******************************************************************************* +* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port +* +* DESCRIPTION: +* This routine returns the Switch CPU port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* the Switch CPU port, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; +} + +/******************************************************************************* +* mvBoardIsSwitchConnected - Get switch connection status +* DESCRIPTION: +* This routine returns port's connection status +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 1 - if ethPortNum is connected to switch, 0 otherwise +* +*******************************************************************************/ +MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); + return MV_ERROR; + } + + if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) + { + mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); + return MV_ERROR; + } + + if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) + return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); + else + return 0; +} + +/******************************************************************************* +* mvBoardSmiScanModeGet - Get Switch SMI scan mode +* +* DESCRIPTION: +* This routine returns Switch SMI scan mode. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; +} + +/******************************************************************************* +* mvBoardTclkGet - Get the board Tclk (Controller clock) +* +* DESCRIPTION: +* This routine extract the controller core clock. +* This function uses the controller counters to make identification. +* Note: In order to avoid interference, make sure task context switch +* and interrupts will not occure during this function operation +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardTclkGet(MV_VOID) +{ + + MV_U32 tmpTClkRate=0; + + if (-1 == tClkRate) + { + /* Auto calc Tclk using counters */ +#ifdef MV_TCLK_CALC + MV_U32 ticks; + MV_U32 refClkDevBitRate; + MV_U32 refClkDevBit; + MV_U32 countNum= MV_TCLK_CNTR; /* Counter 1 is used for Tclk measurment */ + + refClkDevBit = MV_REF_CLK_DEV_BIT; + refClkDevBitRate = MV_REF_CLK_BIT_RATE; + + /* Stop counter activity */ + mvCntmrDisable(countNum); + + /* load value onto counter\timer */ + mvCntmrLoad(countNum,0xffffffff); + + /* set the counter to load in the first time */ + mvCntmrWrite(countNum,0xffffffff); + + /* Set input indication pin as input */ + MV_REG_BIT_SET(GPP_DATA_OUT_EN_REG(0),(1 << MV_REF_CLK_INPUT_GPP)); + + /* Enable interrupt as edge */ + MV_REG_BIT_SET(GPP_INT_MASK_REG(0),(1 << MV_REF_CLK_INPUT_GPP) ); + + /* This function is blocking. It returns only when reference clock is rising */ + /* Clear Interrupt cause */ + MV_REG_WRITE(GPP_INT_CAUSE_REG(0),0); + + do + { + if ( MV_REG_READ(GPP_INT_CAUSE_REG(0)) & (1 << MV_REF_CLK_INPUT_GPP)) break; + }while (1); + + + /* set control for timer \ cunter and enable */ + mvCntmrEnable(countNum); + + /* This function is blocking. It returns only when reference clock is rising */ + /* Clear Interrupt cause */ + MV_REG_WRITE(GPP_INT_CAUSE_REG(0),0); + + do + { + do + { + if ( MV_REG_READ(GPP_INT_CAUSE_REG(0)) & (1 << MV_REF_CLK_INPUT_GPP)) break; + }while (1); + MV_REG_WRITE(GPP_INT_CAUSE_REG(0),0); + }while (refClkDevBit--); + + /* Timer counts back. We need total num of ticks from count begin */ + ticks = ~MV_REG_READ(CNTMR_VAL_REG(countNum)); + + /* Disable interrupt */ + MV_REG_BIT_RESET(GPP_INT_MASK_REG(0),(1 << MV_REF_CLK_INPUT_GPP) ); + + /* Clear Interrupt cause */ + MV_REG_BIT_RESET(GPP_INT_CAUSE_REG(0),(1 << MV_REF_CLK_INPUT_GPP)); + + /* Release the reference clock device and stop timer */ + mvCntmrDisable(countNum); + + tmpTClkRate = (ticks/MV_REF_CLK_DEV_BIT) * refClkDevBitRate; + +#elif defined(DB_FPGA) + tmpTClkRate = MV_DB_FPGA_TCLK; +#elif defined(TCLK_AUTO_DETECT) + + tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); + + tmpTClkRate &= MSAR_TCLCK_MASK; + + switch (tmpTClkRate) + { + case MSAR_TCLCK_133: + tmpTClkRate = MV_BOARD_TCLK_133MHZ; + break; +#if !defined(MV_88F6082) && !defined(MV_88F6183) && !defined(MV_88F6183L) + case MSAR_TCLCK_150: + tmpTClkRate = MV_BOARD_TCLK_150MHZ; + break; +#endif + case MSAR_TCLCK_166: + tmpTClkRate = MV_BOARD_TCLK_166MHZ; + break; + } + +#else + + tmpTClkRate = MV_BOARD_DEFAULT_TCLK; + +#endif + + tClkRate = tmpTClkRate; + } + else + tmpTClkRate = tClkRate; + + return tmpTClkRate; + +} +/******************************************************************************* +* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) +* +* DESCRIPTION: +* This routine extract the CPU bus clock. +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardSysClkGet(MV_VOID) +{ + MV_U32 tmpSysClkRate=0; +#ifndef DB_FPGA + MV_U32 tmp; +#endif + +#ifdef DB_FPGA + tmpSysClkRate = MV_DB_FPGA_CPU_CLK; +#else +#ifdef SYSCLK_AUTO_DETECT + tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); + tmpSysClkRate = tmp & MSAR_ARMDDRCLCK_MASK; + tmpSysClkRate = tmpSysClkRate >> MSAR_ARMDDRCLCK_OFFS; + if ((mvCtrlModelGet() == MV_5281_DEV_ID) || (mvCtrlModelGet() == MV_1281_DEV_ID)) + if(tmp & MSAR_ARMDDRCLCK_H_MASK) + tmpSysClkRate |= BIT4; + + tmpSysClkRate = _cpuARMDDRCLK[tmpSysClkRate].ddrClk; + +#else + tmpSysClkRate = MV_BOARD_DEFAULT_SYSCLK; +#endif +#endif /* DB_FPGA */ + return tmpSysClkRate; +} + + +/******************************************************************************* +* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number +* +* DESCRIPTION: +* Multi-ported PCI Express bridges that is implemented on the board +* collapse interrupts across multiple conventional PCI/PCI-X buses. +* A dual-headed PCI Express bridge would map (or "swizzle") the +* interrupts per the following table (in accordance with the respective +* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# +* signals from its two logical PCI/PCI-X bridges, collapse the +* INTA#-INTD# signals from any internal sources, and convert the +* signals to in-band PCI Express messages. 10 +* This function returns the upstream interrupt as it was converted by +* the bridge, according to board configuration and the following table: +* PCI dev num +* Interrupt pin 7, 8, 9 +* A -> A D C +* B -> B A D +* C -> C B A +* D -> D C B +* +* +* INPUT: +* devNum - PCI/PCIX device number. +* intPin - PCI Int pin +* +* OUTPUT: +* None. +* +* RETURN: +* Int pin connected to the Interrupt controller +* +*******************************************************************************/ +MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) +{ + MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); + + if (realIntPin == 0) return 4; + else return realIntPin; + +} + +/******************************************************************************* +* mvBoardDebug7Seg - Set the board debug 7Seg +* +* DESCRIPTION: +* +* INPUT: +* hexNum - Number to be displied in hex by 7Seg. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardDebug7Seg(MV_U32 hexNum) +{ + MV_U32 boardId, addr,val = 0,totalMask, currentBitMask = 1,i; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardDebug7Seg:Board unknown.\n"); + return; + + } + + /* Check if 7Segments is wired to CS */ + addr = mvBoardGetDeviceBaseAddr(0, BOARD_DEV_SEVEN_SEG); + + if (addr != 0xFFFFFFFF) + { + hexNum = *(volatile MV_U32*)((MV_U32)CPU_MEMIO_UNCACHED_ADDR(addr) + (MV_U32)((hexNum & 0xf) << 4)); + + return; + + } + else + { + + /* the 7seg is wired to GPPs */ + totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; + hexNum &= totalMask; + totalMask = 0; + + for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) + { + if (hexNum & currentBitMask) + { + val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); + } + + totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); + + currentBitMask = (currentBitMask << 1); + } + + if (BOARD_INFO(boardId)->ledsPolarity) + { + mvGppValueSet(0, totalMask, val); + } + else + { + mvGppValueSet(0, totalMask, ~val); + } + } +} + +#if defined(MV_INCLUDE_PCI) + +/******************************************************************************* +* mvBoardPciGpioPinGet - Get board PCI interrupt level. +* +* DESCRIPTION: +* This function returns the value of Gpp Pin that is connected +* to the specified IDSEL and interrupt pin (A,B,C,D). For example, If +* IDSEL 8 (device 8) interrupt A is connected to GPIO pin 4 the function +* will return the value 4. +* This function supports multiple PCI interfaces. +* +* INPUT: +* pciIf - PCI interface number. +* devNum - device number (IDSEL). +* intPin - Interrupt pin (A=1, B=2, C=3, D=4). +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardPciGpioPinGet(MV_U32 pciIf, MV_U32 devNum, MV_U32 intPin) +{ + int i; + MV_U32 boardId; + + /* Convert PciIf to the real PCi Interface number */ + pciIf = mvPciRealIfNumGet(pciIf); + + boardId = mvBoardIdGet(); + + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardPciGpioPinGet:Board ID %d unknown.\n", boardId); + return MV_ERROR; + + } + + if ((DB_88F5181_DDR1_PRPMC == boardId) || + (DB_88F5181_DDR1_PEXPCI == boardId) || + (DB_88F5181_DDR1_MNG == boardId)) + { + /* These boards are NOT backplans. PCI interrupt connectivity */ + /* information of a specifc user backplain, which to install */ + /* those boards, is unknown. */ + /* Marvell general HAL provides default PCI definition for */ + /* these add-in cards. Each user should modify this */ + /* configuration according to the backplain in use. */ + for (i = 0; i < BOARD_INFO(boardId)->numBoardPciIf; i++) + if (BOARD_INFO(boardId)->pBoardPciIf[i].pciDevNum == devNum) + return (MV_U32)BOARD_INFO(boardId)->pBoardPciIf[i].pciGppIntMap[intPin - 1]; + } + + if (BOARD_INFO(boardId)->pBoardPciIf[pciIf].pciDevNum == (MV_U8)N_A) + { + mvOsPrintf("mvBoardPciGpioPinGet: ERR. Could not find GPP pin " \ + "assignment for pciIf %d devNum %d intPin %d\n", + pciIf, devNum, intPin); + return N_A; + } + + + for (i = 0; i < BOARD_INFO(boardId)->numBoardPciIf; i++) + if (BOARD_INFO(boardId)->pBoardPciIf[i].pciDevNum == devNum) + return (MV_U32)BOARD_INFO(boardId)->pBoardPciIf[i].pciGppIntMap[intPin - 1]; + + mvOsPrintf("mvBoardPciGpioPinGet:Illigal device number %d\n", devNum); + return N_A; +} +#endif + +/******************************************************************************* +* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardRTCGpioPinGet(MV_VOID) +{ + MV_U32 boardId, i; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); + return MV_ERROR; + + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == BOARD_DEV_RTC) + return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + + return MV_ERROR; +} + +/******************************************************************************* +* mvBoarGpioPinGet - mvBoarGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* class - MV_BOARD_DEV_CLASS enum. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoarGpioPinNumGet(MV_BOARD_DEV_CLASS class) +{ + MV_U32 boardId, i; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); + return MV_ERROR; + + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) + return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + + return MV_ERROR; +} + + +/******************************************************************************* +* mvBoardReset - mvBoardReset +* +* DESCRIPTION: +* Reset the board +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None +* +*******************************************************************************/ +#define WAIT_DELAY \ + { volatile int dummy; int i; for (i=0; i<500; i++) dummy = i; } + +MV_VOID mvBoardReset(MV_VOID) +{ + MV_32 resetPin,boardId = mvBoardIdGet(); + + /* Get gpp reset pin if define */ + resetPin = mvBoardResetGpioPinGet(); + if (resetPin != MV_ERROR) + { + if ((boardId == RD_88F6082_NAS) + || (boardId == RD_88F6082_MICRO_DAS_NAS) + || (boardId == RD_88F6082_DX243_24G)) + { + /* Set DRAM into self refresh mode */ + MV_REG_WRITE(SDRAM_CONFIG_REG, 0xfa14410); + MV_REG_WRITE(SDRAM_OPERATION_REG, 0x7); + + /* wait 500 clock cycles */ + WAIT_DELAY + + MV_REG_BIT_SET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); + MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); + } + + MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); + MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); + + } + else + { + /* No gpp reset pin was found, try to reset ussing + system reset out */ + MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); + MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); + } + + while(1); +} + +/******************************************************************************* +* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardResetGpioPinGet(MV_VOID) +{ + MV_U32 boardId, i; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); + return MV_ERROR; + + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == BOARD_DEV_RESET) + return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + + return MV_ERROR; +} +#if defined(MV_INCLUDE_SDIO) +/******************************************************************************* +* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardSDIOGpioPinGet(MV_VOID) +{ + MV_U32 boardId, i; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); + return MV_ERROR; + + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == BOARD_DEV_SDIO_DETECT) + return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + + return MV_ERROR; +} +#endif + +/******************************************************************************* +* mvBoardUSBVbusGpioPinGet - return Vbus input GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusGpioPinGet(int devId) +{ + MV_U32 boardId, i, indexFound = 0; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardUSBVbusGpioPinGet:Board unknown.\n"); + return MV_ERROR; + + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == BOARD_DEV_USB_VBUS) + { + if (indexFound == devId) + return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + else + indexFound++; + } + + return MV_ERROR; +} + +/******************************************************************************* +* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) +{ + return MV_ERROR; +} + + +/******************************************************************************* +* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins +* +* DESCRIPTION: +* This function returns a 32-bit mask of GPP pins that connected to +* interrupt generating sources on board. +* For example if UART channel A is hardwired to GPP pin 8 and +* UART channel B is hardwired to GPP pin 4 the fuinction will return +* the value 0x000000110 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* See description. The function return -1 if board is not identified. +* +*******************************************************************************/ +MV_32 mvBoardGpioIntMaskGet(MV_VOID) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); + return MV_ERROR; + + } + + return BOARD_INFO(boardId)->intsGppMask; +} + +/******************************************************************************* +* mvBoardMppGet - Get board dependent MPP register value +* +* DESCRIPTION: +* MPP settings are derived from board design. +* MPP group consist of 8 MPPs. An MPP group represent MPP +* control register. +* This function retrieves board dependend MPP register value. +* +* INPUT: +* mppGroupNum - MPP group number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit value describing MPP control register value. +* +*******************************************************************************/ +MV_32 mvBoardMppGet(MV_U32 mppGroupNum) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + return MV_ERROR; + + } + + return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; +} + + +/* Board devices API managments */ + +/******************************************************************************* +* mvBoardGetDeviceNumber - Get number of device of some type on the board +* +* DESCRIPTION: +* +* INPUT: +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* number of those devices else the function returns 0 +* +* +*******************************************************************************/ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex=0,devNum; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); + return 0xFFFFFFFF; + + } + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) + { + if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) + { + foundIndex++; + } + } + + return foundIndex; + +} + +/******************************************************************************* +* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Base address else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); + + } + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Bus width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return mvDevWidthGet(devEntry->deviceCS); + + } + + return 0xFFFFFFFF; + +} + +/******************************************************************************* +* mvBoardGetDeviceWidth - Get dev width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + + } + + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + return devEntry->devWidth; + + return MV_ERROR; + +} + +/******************************************************************************* +* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* window size else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); + } + + return 0xFFFFFFFF; +} + + +/******************************************************************************* +* boardGetDevEntry - returns the entry pointer of a device on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +* +*******************************************************************************/ +static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex=0,devIndex; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("boardGetDevEntry: Board unknown.\n"); + return NULL; + + } + + /* because some restrictions like in U-boot that always expect the BootFlash to be + the first flash - we want always the Boot CS to be the first device of its kind , + so we always will start searching from there and then search the other */ + + for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) + { + if ((BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) && + (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX)) + { + if (foundIndex == devNum) + return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); + else + foundIndex++; + } + } + + + for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) + { + + if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) + continue; + + if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) + { + if (foundIndex == devNum) + { + return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); + } + foundIndex++; + } + } + + /* device not found */ + return NULL; +} + + +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + + } + + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + return devEntry->deviceCS; + + return 0xFFFFFFFF; + +} + +/******************************************************************************* +* mvBoardRtcTwsiAddrTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardRtcTwsiAddrTypeGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_RTC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardRtcTwsiAddrGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardRtcTwsiAddrGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_RTC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + return (0xFF); +} + +/******************************************************************************* +* mvBoardA2DTwsiAddrTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardA2DTwsiAddrTypeGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_AUDIO_DEC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardA2DTwsiAddrGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardA2DTwsiAddrGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_AUDIO_DEC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + return (0xFF); +} + + +#if defined(MV_INCLUDE_PCI) + +/******************************************************************************* +* mvBoardFirstPciSlotDevNumGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_32 mvBoardFirstPciSlotDevNumGet(MV_U32 pciIf) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + return BOARD_INFO(boardId)->pBoardPciIf[pciIf].pciDevNum; +} + +/******************************************************************************* +* mvBoardPciSlotsNumGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_32 mvBoardPciSlotsNumGet(MV_U32 pciIf) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + return BOARD_INFO(boardId)->numBoardPciIf; +} + +/******************************************************************************* +* mvBoardIsOurPciSlot - Return true for lot number which is defined under +* the bus number. +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_BOOL mvBoardIsOurPciSlot(MV_U32 busNum, MV_U32 slotNum) +{ + MV_U32 boardId= mvBoardIdGet(); + MV_U32 localBusNum= mvPciLocalBusNumGet(PCI_DEFAULT_IF); + int i; + + /* Our device number */ + if (slotNum == mvPciLocalDevNumGet(PCI_DEFAULT_IF)) + { + return MV_TRUE; + } + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardIsOurPciSlot: Board unknown.\n"); + return MV_FALSE; + } + + if (localBusNum != busNum) + { + mvOsPrintf("mvBoardIsOurPciSlot: localBusNum %x != busNum %x.\n", localBusNum, busNum); + return MV_FALSE; + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardPciIf; i++) + if (BOARD_INFO(boardId)->pBoardPciIf[i].pciDevNum == slotNum) + return MV_TRUE; + + return MV_FALSE; +} +/******************************************************************************* +* mvBoardPciIsMonarch - +* +* DESCRIPTION: +* This function is target to PRPMC type boards. In those boards there is + +* Check according to PCI arbiter control register if run with monarch +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* MV_TRUE if the PRPMC is monarch, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_BOOL mvBoardPciIsMonarch(void) +{ +#if defined(DB_MNG) + /* the u-boot set the arbitter for DB_88F5181_DDR1_MNG boards */ + if((MV_REG_READ(PCI_ARBITER_CTRL_REG(0)) & PACR_ARB_ENABLE) == 0) + return MV_TRUE; +#endif + + return MV_FALSE; +} +#endif /* #if defined(MV_INCLUDE_PCI) */ +/******************************************************************************* +* mvBoardSlicGpioPinGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) +{ + MV_U32 boardId; + boardId = mvBoardIdGet(); + + switch (boardId) + { + case DB_88F5181L_DDR2_2XTDM: + if (0 == slicNum) + { + return 8; + } + else if (1 == slicNum) + { + return 9; + } + else return MV_ERROR; + break; + case RD_88F5181L_VOIP_FE: + if (0 == slicNum) + { + return 2; + } + else if (1 == slicNum) + { + return 5; + } + else return MV_ERROR; + break; + default: + return MV_ERROR; + break; + + } +} + +/******************************************************************************* +* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) +{ + switch(mvBoardIdGet()) + { + case RD_88F5181L_VOIP_GE: + case RD_88F5181L_VOIP_FE: + *connMode = DAISY_CHAIN_MODE; + *irqMode = INTERRUPT_TO_TDM; + break; + case DB_88F5181L_DDR2_2XTDM: + *connMode = DUAL_CHIP_SELECT_MODE; + *irqMode = INTERRUPT_TO_MPP; + break; + case RD_88F5181L_VOIP_FXO_GE: + *connMode = DUAL_CHIP_SELECT_MODE; + *irqMode = INTERRUPT_TO_TDM; + break; + default: + *connMode = *irqMode = -1; + mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); + } + + return; + +} + +/******************************************************************************* +* mvBoardTdmLifeLineSet - set life line control on TDM module +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardTdmMppSet(MV_32 chType) +{ + return; +} +/******************************************************************************* +* mvBoardStatusLedPinNumGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: Return the last debug led in the board info +* +* +*******************************************************************************/ +MV_U8 mvBoardStatusLedPinNumGet(MV_VOID) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardIsOurPciSlot: Board unknown.\n"); + return MV_FALSE; + } + + return BOARD_INFO(boardId)->pLedGppPin[BOARD_INFO(boardId)->activeLedsNumber-1]; +} +/******************************************************************************* +* mvBoardSpecInitGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, +* otherwise return MV_FALSE. +* +* +*******************************************************************************/ + +MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) +{ + switch(mvBoardIdGet()) + { + case RD_88F5181_POS_NAS: + *regOff = 0x18; + *data = 0x4151; + return MV_TRUE; + + default: + return MV_FALSE; + } +} +/******************************************************************************* +* mvBoardLedNumGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: Return the last debug led in the board info +* +* +*******************************************************************************/ + +MV_U8 mvBoardLedNumGet(MV_VOID) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardIsOurPciSlot: Board unknown.\n"); + return MV_FALSE; + } + + return BOARD_INFO(boardId)->activeLedsNumber; +} + + +/******************************************************************************* +* mvBoardStatusLed - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: MV_STATUS +* +* +*******************************************************************************/ +MV_STATUS mvBoardStatusLed(MV_BOOL status) +{ + int val; + int mask; + MV_U32 boardId; + + /* Check first that there are debug leds on the board */ + if (mvBoardLedNumGet() == 0) + return MV_TRUE; + + boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardIsOurPciSlot: Board unknown.\n"); + return MV_FALSE; + } + + mask = val = (1 << mvBoardStatusLedPinNumGet()); + + if (status) + val = ~val; + + if (0 == BOARD_INFO(boardId)->ledsPolarity) + { + return mvGppValueSet(0, mask, val); + } + else + { + return mvGppValueSet(0, mask, ~val); + } + +} + + +/******************************************************************************* +* mvBoardNandWidthGet - +* +* DESCRIPTION: Get the width of the first NAND device in byte. +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: 1, 2, 4 or MV_ERROR +* +* +*******************************************************************************/ +/* */ +MV_32 mvBoardNandWidthGet(void) +{ + MV_U32 devNum; + MV_U32 devWidth; + MV_U32 boardId= mvBoardIdGet(); + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) + { + devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); + if (devWidth != MV_ERROR) + return (devWidth / 8); + } + + /* NAND wasn't found */ + return MV_ERROR; +} + diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvLib.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvLib.h new file mode 100644 index 0000000..ced7c56 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvLib.h @@ -0,0 +1,311 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvBoardEnvLibh +#define __INCmvBoardEnvLibh + +/* defines */ +/* The below constant macros defines the board I2C EEPROM data offsets */ + + + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "boardEnv/mvBoardEnvSpec.h" + + +/* DUART stuff for Tclk detection only */ +#define DUART_BAUD_RATE 115200 +#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ + +/* Voice devices assembly modes */ +#define DAISY_CHAIN_MODE 1 +#define DUAL_CHIP_SELECT_MODE 0 +#define INTERRUPT_TO_MPP 1 +#define INTERRUPT_TO_TDM 0 + + +#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS +#define BOARD_ETH_SWITCH_PORT_NUM 5 + +#define MV_BOARD_MAX_USB_IF 2 +#define MV_BOARD_MAX_MPP 4 +#define MV_BOARD_NAME_LEN 0x20 + +typedef struct _boardData +{ + MV_U32 magic; + MV_U16 boardId; + MV_U8 boardVer; + MV_U8 boardRev; + MV_U32 reserved1; + MV_U32 reserved2; + +}BOARD_DATA; + +typedef enum _devBoardClass +{ + BOARD_DEV_NOR_FLASH, + BOARD_DEV_NAND_FLASH, + BOARD_DEV_SEVEN_SEG, + BOARD_DEV_FPGA, + BOARD_DEV_SRAM, + BOARD_DEV_RTC, + BOARD_DEV_PEX_TO_PCI_BRIDGE, + BOARD_DEV_MV_SWITCH, + BOARD_DEV_USB_VBUS, + BOARD_DEV_REF_CLCK, + BOARD_DEV_VOIP_SLIC, + BOARD_DEV_BUTTON, + BOARD_DEV_POWER_BUTTON, + BOARD_DEV_RESTOR_BUTTON, + BOARD_DEV_HDD0_POWER, + BOARD_DEV_HDD1_POWER, + BOARD_DEV_FAN_POWER, + BOARD_DEV_SPI_FLASH, + BOARD_DEV_RESET, + BOARD_DEV_POWER_ON_LED, + BOARD_DEV_HDD_POWER, + BOARD_DEV_AUDIO_DEC, + BOARD_DEV_SDIO_DETECT, + BOARD_DEV_SWITCH_PHY_INT, + BOARD_DEV_OTHER, +}MV_BOARD_DEV_CLASS; + + +typedef struct _pciBoardSlot +{ + MV_U8 pciSlotGppIntMap[4]; + +}MV_BOARD_PCI_SLOT; + + +typedef struct _pciBoardIf +{ + MV_U8 pciDevNum; + MV_U8 pciGppIntMap[4]; +}MV_BOARD_PCI_IF; + + +typedef struct _devCsInfo +{ + MV_U8 deviceCS; + MV_U32 params; + MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ + MV_U8 devWidth; + +}MV_DEV_CS_INFO; + + +#define MV_BOARD_PHY_FORCE_10MB 0x0 +#define MV_BOARD_PHY_FORCE_100MB 0x1 +#define MV_BOARD_PHY_FORCE_1000MB 0x2 +#define MV_BOARD_PHY_SPEED_AUTO 0x3 + +typedef struct _boardSwitchInfo +{ + MV_32 linkStatusIrq; + MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; + MV_32 qdCpuPort; + MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ + MV_32 switchOnPort; + +}MV_BOARD_SWITCH_INFO; + +typedef struct _boardLedInfo +{ + MV_U8 activeLedsNumber; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + MV_U8* gppPinNum; /* Pointer to GPP values */ + +}MV_BOARD_LED_INFO; + +typedef struct _boardGppInfo +{ + MV_BOARD_DEV_CLASS devClass; + MV_U8 gppPinNum; + +}MV_BOARD_GPP_INFO; + + +typedef struct _boardTwsiInfo +{ + MV_BOARD_DEV_CLASS devClass; + MV_U8 twsiDevAddr; + MV_U8 twsiDevAddrType; + +}MV_BOARD_TWSI_INFO; + + +typedef enum _boardMacSpeed +{ + BOARD_MAC_SPEED_10M, + BOARD_MAC_SPEED_100M, + BOARD_MAC_SPEED_1000M, + BOARD_MAC_SPEED_AUTO, + +}MV_BOARD_MAC_SPEED; + +typedef struct _boardMacInfo +{ + MV_BOARD_MAC_SPEED boardMacSpeed; + MV_U8 boardEthSmiAddr; + +}MV_BOARD_MAC_INFO; + +typedef struct _boardMppInfo +{ + MV_U32 mppGroup[MV_BOARD_MAX_MPP]; + +}MV_BOARD_MPP_INFO; + +typedef struct _boardInfo +{ + char boardName[MV_BOARD_NAME_LEN]; + MV_U8 numBoardMppConfigValue; + MV_BOARD_MPP_INFO* pBoardMppConfigValue; + MV_U32 intsGppMask; + MV_U8 numBoardDeviceIf; + MV_DEV_CS_INFO* pDevCsInfo; + MV_U8 numBoardPciIf; + MV_BOARD_PCI_IF* pBoardPciIf; + MV_U8 numBoardTwsiDev; + MV_BOARD_TWSI_INFO* pBoardTwsiDev; + MV_U8 numBoardMacInfo; + MV_BOARD_MAC_INFO* pBoardMacInfo; + MV_U8 numBoardGppInfo; + MV_BOARD_GPP_INFO* pBoardGppInfo; + MV_U8 activeLedsNumber; + MV_U8* pLedGppPin; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + /* GPP values */ + MV_U32 gppOutEnVal; + MV_U32 gppOutVal; + MV_U32 gppPolarityVal; + /* Switch Configuration */ + MV_BOARD_SWITCH_INFO* pSwitchInfo; +}MV_BOARD_INFO; + + + +MV_VOID mvBoardEnvInit(MV_VOID); +MV_U32 mvBoardIdGet(MV_VOID); +MV_U16 mvBoardModelGet(MV_VOID); +MV_U16 mvBoardRevGet(MV_VOID); +MV_STATUS mvBoardNameGet(char *pNameBuff); +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); +MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); +MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); +MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); +MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); +MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); +MV_U32 mvBoardTclkGet(MV_VOID); +MV_U32 mvBoardSysClkGet(MV_VOID); +MV_VOID mvBoardDebug7Seg(MV_U32 hexNum); +MV_32 mvBoardMppGet(MV_U32 mppGroupNum); +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); +MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); +MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); +MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); +MV_VOID mvBoardReset(MV_VOID); +MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); +MV_U8 mvBoardLedNumGet(MV_VOID); + +/* Board devices API managments */ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +/* Gpio Pic Connections API */ +MV_32 mvBoarGpioPinNumGet(MV_BOARD_DEV_CLASS class); +MV_U8 mvBoardStatusLedPinNumGet(MV_VOID); +MV_STATUS mvBoardStatusLed(MV_BOOL status); +MV_32 mvBoardUSBVbusGpioPinGet(int devId); +MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); +MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); +MV_32 mvBoardResetGpioPinGet(MV_VOID); +MV_32 mvBoardRTCGpioPinGet(MV_VOID); +MV_32 mvBoardGpioIntMaskGet(MV_VOID); +MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); +MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); +MV_VOID mvBoardTdmMppSet(MV_32 chType); +#if defined(MV_INCLUDE_SDIO) +MV_32 mvBoardSDIOGpioPinGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_PCI) +MV_32 mvBoardPciGpioPinGet(MV_U32 pciIf, MV_U32 idSel, MV_U32 intPin); +/* Misc */ +MV_32 mvBoardFirstPciSlotDevNumGet(MV_U32 pciIf); +MV_32 mvBoardPciSlotsNumGet(MV_U32 pciIf); +MV_BOOL mvBoardIsOurPciSlot(MV_U32 busNum, MV_U32 slotNum); +MV_BOOL mvBoardPciIsMonarch(void); +#endif /* defined(MV_INCLUDE_PCI) */ +#if defined(MV_INCLUDE_NAND) +MV_32 mvBoardNandWidthGet(void); +#endif /* defined(MV_INCLUDE_NAND) */ +#endif /* __INCmvBoardEnvLibh */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvSpec.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvSpec.c new file mode 100644 index 0000000..909018d --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvSpec.c @@ -0,0 +1,502 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cntmr/mvCntmr.h" +#include "device/mvDevice.h" +#include "ddr1_2/mvDramIfRegs.h" +#include "twsi/mvTwsi.h" + + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +MV_STATUS boardEepromGet(BOARD_DATA *boardData); + +MV_U32 gBoardId = -1; + +#ifdef MV_INCLUDE_EARLY_PRINTK +extern void mv_early_printk(char *fmt,...); +#endif +/******************************************************************************* +* mvBoardIdGet - Get Board model +* +* DESCRIPTION: +* This function returns board ID. +* Board ID is 32bit word constructed of board model (16bit) and +* board revision (16bit) in the following way: 0xMMMMRRRR. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit board ID number, '-1' if board is undefined. +* +*******************************************************************************/ +MV_U32 mvBoardIdGet(MV_VOID) +{ + MV_U32 tmpBoardId = -1; + BOARD_DATA boardData; + +#if defined(DB_FPGA) + tmpBoardId = DB_88F5X8X_FPGA_DDR1; + gBoardId = tmpBoardId; + return tmpBoardId; +#endif + + if(gBoardId != -1) + { + #if defined(MV_88F5182) + switch(gBoardId) + { + case DB_88F5182_DDR2_OLD: + gBoardId = DB_88F5182_DDR2; + break; + case RD_88F5182_2XSATA_OLD: + gBoardId = RD_88F5182_2XSATA; + break; + case RD_88F5182_2XSATA3_OLD: + gBoardId = RD_88F5182_2XSATA3; + break; + default: + break; + } + #elif defined(MV_88F5082) + switch(gBoardId) + { + case DB_88F5082_DDR2_OLD: + gBoardId = DB_88F5082_DDR2; + break; + case RD_88F5082_2XSATA_OLD: + gBoardId = RD_88F5082_2XSATA; + break; + case RD_88F5082_2XSATA3_OLD: + gBoardId = RD_88F5082_2XSATA3; + break; + default: + break; + } + #elif defined(MV_88F5181L) + if (gBoardId == DB_88F5181L_DDR2_2XTDM_OLD) + { + gBoardId = DB_88F5181L_DDR2_2XTDM; + } + else if(gBoardId == RD_88F5181L_VOIP_FE_OLD) + { + gBoardId = RD_88F5181L_VOIP_FE; + } + else if(gBoardId == RD_88F5181L_VOIP_GE_OLD) + { + gBoardId = RD_88F5181L_VOIP_GE; + } + #elif defined(MV_88W8660) + if (gBoardId == DB_88W8660_DDR2_OLD) + { + gBoardId = DB_88W8660_DDR2; + } + else if (gBoardId == RD_88W8660_DDR1_OLD) + { + gBoardId = RD_88W8660_DDR1; + } + else if(gBoardId == RD_88W8660_AP82S_DDR1_OLD) + { + gBoardId = RD_88W8660_AP82S_DDR1; + } + #elif defined(MV_88F5181) + if (gBoardId == RD_88F5181_GTW_FE_OLD) + { + gBoardId = RD_88F5181_GTW_FE; + } + else if (gBoardId == RD_88F5181_GTW_GE_OLD) + { + gBoardId = RD_88F5181_GTW_GE; + } + else if (gBoardId == RD_88F5181_POS_NAS_OLD) + { + gBoardId = RD_88F5181_POS_NAS; + } + else if (gBoardId == DB_88F5X81_DDR2_OLD) + { + gBoardId = DB_88F5X81_DDR2; + } + else if (gBoardId == DB_88F5X81_DDR1_OLD) + { + gBoardId = DB_88F5X81_DDR1; + } + else if (gBoardId == 0) /* In case that the U-Boot did not pass the baord ID like in DB-88F5181-DDR1-BP */ + { + gBoardId = -1; + } + #endif + if(gBoardId != -1) + return gBoardId; + } + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + #if defined(DB_88F1281) + tmpBoardId = DB_88F1281_DDR2; + #elif defined(DB_88F6183BP) + tmpBoardId = DB_88F6183_BP; + #elif defined(RD_88F6183GP) + tmpBoardId = RD_88F6183_GP; + #elif defined(RD_88F6183AP) + tmpBoardId = RD_88F6183_AP; + #elif defined(DB_88F6183LBP) + tmpBoardId = DB_88F6183L_BP; + #elif defined(DB_88F5181L) + tmpBoardId = DB_88F5181L_DDR2_2XTDM; + #elif defined(DB_88W8660) + tmpBoardId = DB_88W8660_DDR2; + #elif defined(DB_88F5082) + tmpBoardId = DB_88F5082_DDR2; + #elif defined(DB_88F5182) + tmpBoardId = DB_88F5182_DDR2; + #elif defined(DB_88F5182_A) + tmpBoardId = DB_88F5182_DDR2_A; + #elif defined(DB_88F5181) + tmpBoardId = DB_88F5X81_DDR2; + #elif defined(DB_88F5181_OLD) + tmpBoardId = DB_88F5181_5281_DDR2; + #elif defined(DB_FPGA) + tmpBoardId = DB_88F5X8X_FPGA_DDR1; + #elif defined(DB_88F6082LBP) + tmpBoardId = DB_88F6082L_BP; + #elif defined(DB_CUSTOMER) + tmpBoardId = DB_CUSTOMER1_ID; + #endif + } + else /* DDR1 */ + { + #if defined(RD_88F5182) + tmpBoardId = RD_88F5182_2XSATA; + #elif defined(RD_88F5182_3) + tmpBoardId = RD_88F5182_2XSATA3; + #elif defined(RD_88F5082) + tmpBoardId = RD_88F5082_2XSATA; + #elif defined(RD_88F5082_3) + tmpBoardId = RD_88F5082_2XSATA3; + #elif defined(RD_88W8660) + tmpBoardId = RD_88W8660_DDR1; + #elif defined(RD_88W8660_AP82S) + tmpBoardId = RD_88W8660_AP82S_DDR1; + #elif defined(RD_88F5181L_FE) + tmpBoardId = RD_88F5181L_VOIP_FE; + #elif defined(RD_88F5181L_GE) + tmpBoardId = RD_88F5181L_VOIP_GE; + #elif defined(RD_88F5181_GTWGE) + tmpBoardId = RD_88F5181_GTW_GE; + #elif defined(RD_88F5181_GTWFE) + tmpBoardId = RD_88F5181_GTW_FE; + #elif defined(RD_88F5181L_FXO_GE) + tmpBoardId = RD_88F5181L_VOIP_FXO_GE; + #elif defined(MV_POS_NAS) + tmpBoardId = RD_88F5181_POS_NAS; + #elif defined(MV_VOIP) + tmpBoardId = RD_88F5181_VOIP; + #elif defined(DB_PRPMC) + tmpBoardId = DB_88F5181_DDR1_PRPMC; + #elif defined(DB_MNG) + tmpBoardId = DB_88F5181_DDR1_MNG; + #elif defined(DB_PEX_PCI) + tmpBoardId = DB_88F5181_DDR1_PEXPCI; + #elif defined(DB_88F6082BP) + tmpBoardId = DB_88F6082_BP; + #elif defined(DB_88F6082LBP) + tmpBoardId = DB_88F6082L_BP; + #elif defined(DB_88F6082SA) + tmpBoardId = DB_88F6082_SA; + #elif defined(RD_88F6082NAS) + tmpBoardId = RD_88F6082_NAS; + #elif defined(RD_88F6082DAS_PLUS) + tmpBoardId = RD_88F6082_DAS_PLUS; + #elif defined(RD_88F6082MICRO_DAS_NAS) + tmpBoardId = RD_88F6082_MICRO_DAS_NAS; + #elif defined(RD_88F6082GE_SATA) + tmpBoardId = RD_88F6082_GE_SATA; + #elif defined(RD_88F6082_DX243) + tmpBoardId = RD_88F6082_DX243_24G; + #elif defined(DB_88F5181) + tmpBoardId = DB_88F5X81_DDR1; + #elif defined(DB_88F5181_OLD) + tmpBoardId = DB_88F5181_5281_DDR1; + #endif + } + if(tmpBoardId != -1) { + gBoardId = tmpBoardId; + return tmpBoardId; + } + + + if(boardEepromGet(&boardData) == MV_OK) + { + tmpBoardId = (MV_U32)boardData.boardId; + } + else + { + /* until we have relevant data in twsi then we + will detect the board type from sdram config reg */ + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + if((mvCtrlModelGet() == MV_5281_DEV_ID)&& + (mvCtrlRevGet() >= MV_5281_B0_REV)) + { + tmpBoardId = DB_88F5X81_DDR2; + } + else if(mvCtrlModelGet() == MV_8660_DEV_ID) + { + tmpBoardId = DB_88W8660_DDR2; + } + else if(mvCtrlModelGet() == MV_5082_DEV_ID) + { + tmpBoardId = DB_88F5082_DDR2; + } + else if(mvCtrlModelGet() == MV_5182_DEV_ID) + { + tmpBoardId = DB_88F5182_DDR2; + } + else if(mvCtrlModelGet() == MV_5180_DEV_ID) + { + tmpBoardId = DB_88F5180N_DDR2; + } + else if(mvCtrlModelGet() == MV_6183_DEV_ID) + { + tmpBoardId = DB_88F6183_BP; + } + else if(mvCtrlModelGet() == MV_6183L_DEV_ID) + { + tmpBoardId = DB_88F6183L_BP; + } + else + { + tmpBoardId = DB_88F5181_5281_DDR2; + } + } + else /* DDR1 */ + { + if((mvCtrlModelGet() == MV_5281_DEV_ID)&& + (mvCtrlRevGet() >= MV_5281_B0_REV)) + { + tmpBoardId = DB_88F5X81_DDR1; + } + else if(mvCtrlModelGet() == MV_5180_DEV_ID) + { + tmpBoardId = DB_88F5180N_DDR1; + } + else + { + tmpBoardId = DB_88F5181_5281_DDR1; + } + } + + } + + gBoardId = tmpBoardId; + +#ifdef MV_INCLUDE_EARLY_PRINTK + if (tmpBoardId == -1) + { + mv_early_printk("%s FATAL ERROR: Failed to detect Board ID\n", __FUNCTION__); + } +#endif + + return tmpBoardId; + + +} + +/******************************************************************************* +* boardEepromGet - Get board identification from the EEPROM +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS boardEepromGet(BOARD_DATA *boardData) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + MV_U32 tclk; + + tclk = mvBoardTclkGet(); + + /* Init TWSI first */ + slave.type = ADDR7_BIT; + slave.address = 0x0; + mvTwsiInit(0, 100000, tclk, &slave, 0); + + twsiSlave.slaveAddr.address = MV_BOARD_ID_EEPROM; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = MV_BOARD_ID_EEPROM_OFFSET0; + twsiSlave.moreThen256 = MV_FALSE; + + if(MV_OK != mvTwsiRead (0, &twsiSlave, (MV_U8*)boardData, sizeof(BOARD_DATA))) + { + /*mvOsOutput("Fail to read Board EEPROM from offset0");*/ + return MV_FAIL; + } + +#if defined(MV_CPU_LE) + boardData->magic = MV_BYTE_SWAP_32BIT(boardData->magic); + boardData->boardId = MV_BYTE_SWAP_16BIT(boardData->boardId); + boardData->reserved1 = MV_BYTE_SWAP_32BIT(boardData->reserved1); + boardData->reserved2 = MV_BYTE_SWAP_32BIT(boardData->reserved2); +#endif + + if(boardData->magic == MV_BOARD_I2C_MAGIC) + { + /* Backward compatability */ + #if defined(MV_88F5182) + if (boardData->boardId == DB_88F5182_DDR2_OLD) + { + boardData->boardId = DB_88F5182_DDR2; + } + #elif defined(MV_88F5181L) + if (boardData->boardId == DB_88F5181L_DDR2_2XTDM_OLD) + { + boardData->boardId = DB_88F5181L_DDR2_2XTDM; + } + else if(boardData->boardId == RD_88F5181L_VOIP_FE_OLD) + { + boardData->boardId = RD_88F5181L_VOIP_FE; + } + + #elif defined(MV_88W8660) + if (boardData->boardId == DB_88W8660_DDR2_OLD) + { + boardData->boardId = DB_88W8660_DDR2; + } + #endif + return MV_OK; + } + + twsiSlave.offset = MV_BOARD_ID_EEPROM_OFFSET1; + twsiSlave.moreThen256 = MV_TRUE; + + if(MV_OK != mvTwsiRead (0, &twsiSlave, (MV_U8*)boardData, sizeof(BOARD_DATA))) + { + /*mvOsOutput("Fail to read Board EEPROM from offset1");*/ + return MV_FAIL; + } + + + +#if defined(MV_CPU_LE) + boardData->magic = MV_BYTE_SWAP_32BIT(boardData->magic); + boardData->boardId = MV_BYTE_SWAP_16BIT(boardData->boardId); + boardData->reserved1 = MV_BYTE_SWAP_32BIT(boardData->reserved1); + boardData->reserved2 = MV_BYTE_SWAP_32BIT(boardData->reserved2); +#endif + + if(boardData->magic == MV_BOARD_I2C_MAGIC) + { + /* Backward compatability */ + /* Backward compatability */ + #if defined(MV_88F5182) + if (boardData->boardId == DB_88F5182_DDR2_OLD) + { + boardData->boardId = DB_88F5182_DDR2; + } + #elif defined(MV_88F5181L) + if (boardData->boardId == DB_88F5181L_DDR2_2XTDM_OLD) + { + boardData->boardId = DB_88F5181L_DDR2_2XTDM; + } + else if(boardData->boardId == RD_88F5181L_VOIP_FE_OLD) + { + boardData->boardId = RD_88F5181L_VOIP_FE; + } + + #elif defined(MV_88W8660) + if (boardData->boardId == DB_88W8660_DDR2_OLD) + { + boardData->boardId = DB_88W8660_DDR2; + } + #endif + return MV_OK; + } + + return MV_FAIL; +} + + + diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvSpec.h new file mode 100644 index 0000000..c1fe47e --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvBoardEnvSpec.h @@ -0,0 +1,168 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoardEnvSpech +#define __INCmvBoardEnvSpech + +#include "mvSysHwConfig.h" + + +/* For future use */ +#define BD_ID_DATA_START_OFFS 0x0 +#define BD_DETECT_SEQ_OFFS 0x0 +#define BD_SYS_NUM_OFFS 0x4 +#define BD_NAME_OFFS 0x8 + + + +/* MPP possible values in the remarks should be updated from the board + sheet or taken from HW team */ + + +/* I2C bus addresses */ +#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ +#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM0_I2C_ADDR 0x56 +#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM1_I2C_ADDR 0x54 +#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_EEPROM_I2C_ADDR 0x51 +#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 +#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT + +/* Eeprom board data */ +#define MV_BOARD_ID_EEPROM MV_BOARD_MAIN_EEPROM_I2C_ADDR +#define MV_BOARD_ID_EEPROM_OFFSET0 0x1F0 /* last 16byte in 0.5KByte EEPROMS */ +#define MV_BOARD_ID_EEPROM_OFFSET1 0x1FF0 /* last 16byte in 8KByte EEPROMS */ +#define MV_BOARD_I2C_MAGIC 0xFEEDFEED + + +#define BOOT_FLASH_INDEX 0 +#define MAIN_FLASH_INDEX 1 + +#define BOARD_ETH_START_PORT_NUM 0 +/* Boot Flash definitions */ +#define MV_BOARD_BOOT_FLASH_BASE_ADRS mvBoardGetDeviceBaseAddr(BOOT_FLASH_INDEX, \ + BOARD_DEV_NOR_FLASH) +#define MV_BOARD_BOOT_FLASH_BUS_WIDTH mvBoardGetDeviceBusWidth(BOOT_FLASH_INDEX, \ + BOARD_DEV_NOR_FLASH) +#define MV_BOARD_BOOT_FLASH_DEVICE_WIDTH mvBoardGetDeviceWidth(BOOT_FLASH_INDEX, \ + BOARD_DEV_NOR_FLASH) + +/* Board main flash */ +#define MV_BOARD_FLASH_BASE_ADRS mvBoardGetDeviceBaseAddr(MAIN_FLASH_INDEX, \ + BOARD_DEV_NOR_FLASH) +#define MV_BOARD_FLASH_BUS_WIDTH mvBoardGetDeviceBusWidth(MAIN_FLASH_INDEX, \ + BOARD_DEV_NOR_FLASH) +#define MV_BOARD_FLASH_DEVICE_WIDTH mvBoardGetDeviceWidth(MAIN_FLASH_INDEX, \ + BOARD_DEV_NOR_FLASH) +/* Supported clocks */ +#define MV_BOARD_TCLK_100MHZ 100000000 +#define MV_BOARD_TCLK_125MHZ 125000000 +#define MV_BOARD_TCLK_133MHZ 133333333 +#define MV_BOARD_TCLK_150MHZ 150000000 +#define MV_BOARD_TCLK_166MHZ 166666667 +#define MV_BOARD_TCLK_200MHZ 200000000 + +#define MV_BOARD_SYSCLK_100MHZ 100000000 +#define MV_BOARD_SYSCLK_125MHZ 125000000 +#define MV_BOARD_SYSCLK_133MHZ 133333333 +#define MV_BOARD_SYSCLK_150MHZ 150000000 +#define MV_BOARD_SYSCLK_166MHZ 166666667 +#define MV_BOARD_SYSCLK_200MHZ 200000000 +#define MV_BOARD_SYSCLK_233MHZ 233333333 +#define MV_BOARD_SYSCLK_250MHZ 250000000 +#define MV_BOARD_SYSCLK_267MHZ 266666667 + +#define MV_BOARD_PCLK_400MHZ 400000000 + +/* Clocks stuff */ +#ifndef MV_BOARD_DEFAULT_TCLK +#define MV_BOARD_DEFAULT_TCLK MV_BOARD_TCLK_166MHZ /* Default Tclk 133MHz */ +#endif +#define MV_BOARD_DEFAULT_SYSCLK MV_BOARD_SYSCLK_200MHZ /* Default SysClk 200MHz */ +#define MV_BOARD_DEFAULT_PCLK MV_BOARD_PCLK_400MHZ /* Default Pclock 400 MHZ*/ +#define MV_DB_FPGA_CPU_CLK MV_BOARD_SYSCLK_250MHZ +#define MV_DB_FPGA_TCLK MV_BOARD_SYSCLK_250MHZ +#define MV_BOARD_REF_CLOCK 3686400 /* Refrence Clock 3.6864MHz */ + + + + +#include "mv88F1281BoardEnv.h" +#include "mv88F5082BoardEnv.h" +#include "mv88F5182BoardEnv.h" +#include "mv88F5181LBoardEnv.h" +#include "mv88W8660BoardEnv.h" +#include "mv88F5181BoardEnv.h" +#include "mv88F5180NBoardEnv.h" +#include "mv88F6082BoardEnv.h" +#include "mv88F6183BoardEnv.h" +#include "mv88F6183LBoardEnv.h" +#include "mvCustomerBoardEnv.h" + + +#endif /* __INCmvBoardEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvCustomerBoardEnv.c b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvCustomerBoardEnv.c new file mode 100644 index 0000000..1b61e2a --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvCustomerBoardEnv.c @@ -0,0 +1,132 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define DB_CUS1_BOARD_PCI_IF_NUM 0x1 +#define DB_CUS1_BOARD_TWSI_DEF_NUM 0x0 +#define DB_CUS1_BOARD_MAC_INFO_NUM 0x1 +#define DB_CUS1_BOARD_GPP_INFO_NUM 0x0 +#define DB_CUS1_BOARD_DEBUG_LED_NUM 0x2 +#define DB_CUS1_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_CUS1_BOARD_DEVICE_CONFIG_NUM 0x1 + + +MV_BOARD_PCI_IF db88f5181Cus1InfoBoardPciIf[] = + /* {pciDevNum, {intAGppPin, intBGppPin, intCGppPin, intDGppPin}} */ + {{7, {N_A, N_A, N_A, N_A}} /* pciSlot0 */ + }; + + +MV_U8 rd88f5181Cus1InfoBoardDebugLedIf[DB_CUS1_BOARD_DEBUG_LED_NUM] = + {0, 11}; + +MV_BOARD_MAC_INFO rd88f5181Cus1InfoBoardMacInfo[DB_CUS1_BOARD_MAC_INFO_NUM] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8}}; + +/*MV_BOARD_GPP_INFO rd88f5181Cus1InfoBoardGppInfo[DB_CUS1_BOARD_GPP_INFO_NUM] = +*/ + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 gppPinNum}} */ +/* {{BOARD_DEV_RTC, 8}, + {BOARD_DEV_USB_VBUS, 9}, + {BOARD_DEV_REF_CLCK,0}}; +*/ + +MV_BOARD_MPP_INFO rd88f5181Cus1InfoBoardMppConfigValue[DB_CUS1_BOARD_MPP_CONFIG_NUM] = + /* {{MV_U32 mpp0_7, MV_U32 mpp8_15, MV_U32 mpp16_23, MV_U32 mppDev}} */ + {{{RD_88F5181L_CUS1_MPP0_7, /* mpp0_7 */ + RD_88F5181L_CUS1_MPP8_15, /* mpp8_15 */ + RD_88F5181L_CUS1_MPP16_23, /* mpp16_23 */ + RD_88F5181L_CUS1_MPP_DEV}}}; /* mppDev */ + +MV_DEV_CS_INFO rd88f5181Cus1InfoBoardDeCsInfo[DB_CUS1_BOARD_DEVICE_CONFIG_NUM] = + /*{params, devType, devWidth}*/ + {{3, 0x8fdfffff, BOARD_DEV_NOR_FLASH, 16}}; /* bootCs */ + +MV_BOARD_INFO rd88f5181Cus1Info = { + "RD-88F5181L-Customer 1", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_CUS1_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f5181Cus1InfoBoardMppConfigValue, + ((1 << 4)|(1 << 6)|(1 << 8)), /* intsGppMask */ + DB_CUS1_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f5181Cus1InfoBoardDeCsInfo, + DB_CUS1_BOARD_PCI_IF_NUM, /* numBoardPciIf */ + db88f5181Cus1InfoBoardPciIf, + DB_CUS1_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, + DB_CUS1_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f5181Cus1InfoBoardMacInfo, + DB_CUS1_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + NULL, + DB_CUS1_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f5181Cus1InfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F5181L_CUS1_GPP_OE, /* gppOutEnVal */ + N_A, /* gppPolarityVal */ +}; + + +MV_BOARD_INFO* boardInfoTbl[] = {&rd88f5181Cus1Info}; + +#define BOARD_ID_BASE BOARD_ID_CUSTOMER_BASE +#define MV_MAX_BOARD_ID BOARD_ID_CUSTOMER_MAX diff --git a/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvCustomerBoardEnv.h b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvCustomerBoardEnv.h new file mode 100644 index 0000000..326ed80 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/boardEnv/mvCustomerBoardEnv.h @@ -0,0 +1,87 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoardCustomerEnvSpech +#define __INCmvBoardCustomerEnvSpech + + +/* Customer based boards ID numbers */ +/* =============================== */ + + +#define RD_88F5181L_CUS1_MPP0_7 0x55000000 +#define RD_88F5181L_CUS1_MPP8_15 0x0 +#define RD_88F5181L_CUS1_MPP16_23 0x0 +#define RD_88F5181L_CUS1_MPP_DEV 0x0 +#define RD_88F5181L_CUS1_GPP_OE 0xffff7fff +#define RD_88F5181L_CUS1_GPP_VAL 0x0 + +#define BOARD_ID_CUSTOMER_BASE 0xF0 +#define DB_CUSTOMER1_ID (BOARD_ID_CUSTOMER_BASE+0x0) + +#define BOARD_ID_CUSTOMER_MAX (BOARD_ID_CUSTOMER_BASE+0x1) + + +#endif /* __INCmvBoardCustomerEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/cpu/mvCpu.h b/board/mv_feroceon/mv_orion/orion_family/cpu/mvCpu.h new file mode 100644 index 0000000..e8021db --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/cpu/mvCpu.h @@ -0,0 +1,89 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuh +#define __INCmvCpuh + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#if defined(MV_MIPS) + #include "mvCpuMips.h" +#elif defined (MV_PPC) + #include "mvCpuPpc.h" +#elif defined (MV_ARM) + #include "mvCpuArm.h" +#else + #error "CPU type not selected" +#endif + +MV_U32 mvCpuPclkGet(MV_VOID); +MV_VOID mvCpuNameGet(char *pNameBuff); +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); + + + +#endif /* __INCmvCpuh */ diff --git a/board/mv_feroceon/mv_orion/orion_family/cpu/mvCpuArm.c b/board/mv_feroceon/mv_orion/orion_family/cpu/mvCpuArm.c new file mode 100644 index 0000000..4f38e07 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/cpu/mvCpuArm.c @@ -0,0 +1,223 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* locals */ + +/******************************************************************************* +* mvCpuPclkGet - Get the CPU pClk (pipe clock) +* +* DESCRIPTION: +* This routine extract the CPU core clock. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ + +MV_CPU_ARM_CLK _cpuARMDDRCLK[] = MV_CPU_IF_ARMDDRCLCK_TBL; + +MV_U32 mvCpuPclkGet(MV_VOID) +{ + MV_U32 tmpPClkRate=0; +#ifndef DB_FPGA + MV_U32 tmp; +#endif + +#ifdef DB_FPGA + tmpPClkRate = MV_DB_FPGA_CPU_CLK; +#else +#ifdef SYSCLK_AUTO_DETECT + tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); + tmpPClkRate = tmp & MSAR_ARMDDRCLCK_MASK; + tmpPClkRate = tmpPClkRate >> MSAR_ARMDDRCLCK_OFFS; + + if ((mvCtrlModelGet() == MV_5281_DEV_ID) || (mvCtrlModelGet() == MV_1281_DEV_ID)) + if(tmp & MSAR_ARMDDRCLCK_H_MASK) + tmpPClkRate |= BIT4; + + tmpPClkRate = _cpuARMDDRCLK[tmpPClkRate].cpuClk; + +#else + tmpPClkRate = MV_BOARD_DEFAULT_PCLK; +#endif +#endif /* DB_FPGA */ + + + return tmpPClkRate; +} + +/******************************************************************************* +* mvCpuNameGet - Get CPU name +* +* DESCRIPTION: +* This function returns a string describing the CPU model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* None. +*******************************************************************************/ +MV_VOID mvCpuNameGet(char *pNameBuff) +{ + MV_U32 cpuModel; + + cpuModel = mvOsCpuPartGet(); + + /* The CPU module is indicated in the Processor Version Register (PVR) */ + switch(cpuModel) + { + case CPU_PART_ARM926: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); + break; + case CPU_PART_ARM946: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); + break; + default: + mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); + break; + } /* switch */ + + return; +} + + +#define MV_PROC_STR_SIZE 50 + +static void mvCpuIfGetWriteAllocMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT28) + mvOsSPrintf(buf, "Write Allocate Enabled"); + else + mvOsSPrintf(buf, "Write Allocate Disabled"); +} + +static void mvCpuIfGetCpuStreamMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT29) + mvOsSPrintf(buf, "CPU Streaming Enabled"); + else + mvOsSPrintf(buf, "CPU Streaming Disabled"); +} + +static void mvCpuIfPrintCpuRegs(void) +{ + MV_U32 regVal = 0; + + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); + + __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ + mvOsPrintf("Control Reg = 0x%x\n",regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ + mvOsPrintf("ID Code Reg = 0x%x\n",regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ + mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); + +} + +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) +{ + MV_U32 count = 0; + + MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; + MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; + + mvCpuIfGetWriteAllocMode(Write_Alloc_str); + mvCpuIfGetCpuStreamMode(Cpu_Stream_str); + mvCpuIfPrintCpuRegs(); + + count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); + return count; +} + + + diff --git a/board/mv_feroceon/mv_orion/orion_family/cpu/mvCpuArm.h b/board/mv_feroceon/mv_orion/orion_family/cpu/mvCpuArm.h new file mode 100644 index 0000000..1457193 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/cpu/mvCpuArm.h @@ -0,0 +1,88 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuArmh +#define __INCmvCpuArmh + +/* defines */ + +#define CPU_PART_MRVL131 0x131 +#define CPU_PART_ARM926 0x926 +#define CPU_PART_ARM946 0x946 +#define MV_CPU_ARM_CLK_ELM_SIZE 12 +#define MV_CPU_ARM_CLK_RATIO_OFF 8 +#define MV_CPU_ARM_CLK_DDR_OFF 4 + +#ifndef MV_ASMLANGUAGE +typedef struct _mvCpuArmClk +{ + MV_U32 cpuClk; /* CPU clock in MHz */ + MV_U32 ddrClk; /* DDR clock in MHz */ + MV_U32 clkRatio; /* CPU DDR clock ratio */ + +}MV_CPU_ARM_CLK; + +#endif /* MV_ASMLANGUAGE */ +#endif /* __INCmvCpuArmh */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F1281EnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F1281EnvSpec.h new file mode 100644 index 0000000..d5f16d7 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F1281EnvSpec.h @@ -0,0 +1,326 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __IN88F1281CtrlEnvSpech +#define __IN88F1281CtrlEnvSpech + + +#define MV_ARM_SOC + +#define SOC_NAME_PREFIX "MV88F" + +#define INTER_REGS_SIZE _1M + +#define MV_ETH_REG_BASE(port) 0 +#define USB_REG_BASE(dev) 0 + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 4 +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +/* This define describes the maximum controller supported DEVICE chip select */ +/* also known as banks */ +#define MV_DEVICE_MAX_CS 2 +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_BOOTDEVICE_INDEX 1 + + + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 2 + +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ +#define MV_MPP_MAX_GROUP 2 + +/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ +#define MV_PCI_MAX_IF 0 +#define MV_PCI_START_IF 0 + +/* This define describes the maximum number of supported PEX Interfaces */ +#if defined(MV_INCLUDE_PEX) +#define MV_PEX_MAX_IF 2 +#else +#define MV_PEX_MAX_IF 0 +#endif +#define MV_PEX_START_IF MV_PCI_MAX_IF + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_HOST_BUS_NUM(pciIf) MV_PEX_MAX_IF + (pciIf) +#define PCI_HOST_DEV_NUM(pciIf) 0 + + +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_MAX_PORTS 0 +#define MV_ETH_PORT_SGMII {} + +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 0 + +/* This define describes the the support of USB */ +#define MV_USB_MAX 0 + +/* This define describes the support of the NAND -Flash */ +#define MV_NAND_MAX 1 + + +#define SATA_REG_BASE 0x80000 + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10050 +#define DEV_MULTI_CONTROL 0x10008 +#define MPP_SAMPLE_AT_RESET 0x10010 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) + +#define MSAR_TCLCK_OFFS 10 +#define MSAR_TCLCK_MASK (0x3 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_133 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_150 (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x2 << MSAR_TCLCK_OFFS) + +/* This array is beening call from several files. + mvCpuArm.c, mvBoardEnvLib.c, mvCpuIfInit.S */ +/* ARM CPU clock vs. DDR clock */ +#define MV_CPU_IF_ARMDDRCLCK_TBL {\ + /* CPU FREQ, DDR FREQ, RATIO */\ + {333333333, 166666667, 2},\ + {500000000, 166666667, 3},\ + {666666666, 166666667, 4},\ + {833333333, 166666667, 5},\ + {1000000000, 166666667, 6},\ + {1166666666, 166666667, 7},\ + {400000000, 200000000, 2},\ + {600000000, 200000000, 3},\ + {800000000, 200000000, 4},\ + {1000000000, 200000000, 5},\ + {1050000000, 150000000, 10},\ + {466666666, 233333334, 2},\ + {700000000, 233333334, 3},\ + {933333333, 233333334, 4},\ + {1166666666, 233333334, 5},\ + {500000000, 250000000, 2},\ + {750000000, 250000000, 3},\ + {1000000000, 250000000, 4},\ + {1250000000, 250000000, 5},\ + {533333333, 266666667, 2},\ + {800000000, 266666667, 3},\ + {1066666666, 266666667, 4},\ + {700000000, 100000000, 7},\ + {400000000, 133333334, 3},\ + {533333333, 133333334, 4},\ + {666666666, 133333334, 5},\ + {800000000, 133333334, 6},\ + {933333333, 133333334, 7},\ + {1, 4, 4},\ + {1, 3, 3},\ + {1, 2, 2},\ + {1, 1, 1}\ +}; + +#define MSAR_ARMDDRCLCK_OFFS 6 + +#define MSAR_ARMDDRCLCK_MASK (0xf << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_H_MASK BIT19 + + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + + + +#define MV_TARGET_IS_PEX1(target) \ + ((target >= PEX1_MEM) && (target <= PEX1_IO)) + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS1)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 + + +#define MV_TARGET_IS_AS_BOOT(target) 0 +#define BOOT_TARGETS_NAME_ARRAY {} +#define MV_CHANGE_BOOT_CS(target) (target) + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* typedefs */ + + +#ifndef MV_ASMLANGUAGE +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + SDRAM_CS2, /* SDRAM chip select 2 */ + SDRAM_CS3, /* SDRAM chip select 3 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + PEX1_MEM, /* PCI Express 1 Memory */ + PEX1_IO, /* PCI Express 1 IO */ + INTER_REGS, /* Internal registers */ + FLASH_CS, /* Flash chip select */ + DEV_BOOCS, /* Flash Boot chip select */ + MAX_TARGETS + +}MV_TARGET; + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PEX1_MEM0 PEX1_MEM + +/* For old competability */ +#define DEVICE_CS0 FLASH_CS +#define DEVICE_CS1 DEV_BOOCS + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +/* Device Interface registers offsets */ +#define DEV_BANK_PARAM_REG(num) ((num) ? 0x1046C : 0x10464) + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) (0x1 << (((csNum)+3) * 2)) +#define DINFCR_NF_ACT_CE_MASK(csNum) (0x2 << (((csNum)+3) * 2)) + + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO +#define PCI_IF1_MEM0 PEX1_MEM +#define PCI_IF1_IO PEX1_IO + + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> PCI Express */ + PEX1_TARGET_ID = 3 , /* Port 4 -> PCI Express0 */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + MAX_TARGETS_ID +}MV_TARGET_ID; + + +#define TARGETS_DEF_ARRAY { \ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ \ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ \ + {0x0B,DRAM_TARGET_ID}, /* SDRAM_CS2 */ \ + {0x07,DRAM_TARGET_ID}, /* SDRAM_CS3 */ \ + {0x59,PEX0_TARGET_ID}, /* PEX0_MEM */ \ + {0x51,PEX0_TARGET_ID}, /* PEX0_IO */ \ + {0x59,PEX1_TARGET_ID}, /* PEX1_MEM */ \ + {0x51,PEX1_TARGET_ID}, /* PEX1_IO */ \ + {0xFF, 0xFF}, /* INTER_REGS */ \ + {0x1B,DEV_TARGET_ID}, /* FLASH_CS */ \ + {0x0F,DEV_TARGET_ID} /* DEV_BOOCS*/ \ +} + + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS2 */ \ + "SDRAM_CS3", /* SDRAM_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "PEX1_MEM", /* PEX1_MEM */ \ + "PEX1_IO", /* PEX1_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "FLASH_CS", /* FLASH_CS */ \ + "DEV_BOOCS" /* DEV_BOOCS*/ \ +} + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __IN88F1281CtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F1X81EnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F1X81EnvSpec.h new file mode 100644 index 0000000..3aa732f --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F1X81EnvSpec.h @@ -0,0 +1,291 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __IN88F1X81CtrlEnvSpech +#define __IN88F1X81CtrlEnvSpech + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +#define INTER_REGS_SIZE _1M + + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 4 + + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 2 + +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ +#define MV_MPP_MAX_GROUP 2 + +/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ +#define MV_PCI_MAX_IF 0 +#define MV_PCI_START_IF 0 + +/* This define describes the maximum number of supported PEX Interfaces */ +#if defined(MV_INCLUDE_PEX) +#define MV_PEX_MAX_IF 2 +#else +#define MV_PEX_MAX_IF 0 +#endif +#define MV_PEX_START_IF MV_PCI_MAX_IF + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_HOST_BUS_NUM(pciIf) MV_PEX_MAX_IF + (pciIf) +#define PCI_HOST_DEV_NUM(pciIf) 0 + + +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_MAX_PORTS 0 +#define MV_ETH_PORT_SGMII {} + +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 0 + +/* This define describes the the support of USB */ +#define MV_USB_MAX 0 + +/* This define describes the support of the NAND -Flash */ +#define MV_NAND_MAX 0 + + +#define SATA_REG_BASE 0x80000 + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10050 +#define DEV_MULTI_CONTROL 0x10008 +#define MPP_SAMPLE_AT_RESET 0x10010 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) + +#define MSAR_TCLCK_OFFS 10 +#define MSAR_TCLCK_MASK (0x3 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_133 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_150 (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x2 << MSAR_TCLCK_OFFS) + + +#define MSAR_ARMDDRCLCK_OFFS 6 + + +#define MSAR_ARMDDRCLCK_MASK (0xf << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_H_MASK BIT23 + +#define MSAR_ARMDDRCLCK_333_167 (0x0 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_400_200 (0x1 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_400_133 (0x2 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_500_167 (0x3 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_533_133 (0x4 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_600_200 (0x5 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_667_167 (0x6 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_800_200 (0x7 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_480_160 (0xc << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_550_183 (0xd << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_525_175 (0xe << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_466_233 (0x11 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_500_250 (0x12 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_533_266 (0x13 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_600_300 (0x14 << MSAR_ARMDDRCLCK_OFFS) + +#define MSAR_ARMDDRCLCK_450_150 (0x15 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_533_178 (0x16 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_575_192 (0x17 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_700_175 (0x18 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_733_183 (0x19 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_750_187 (0x1A << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_775_194 (0x1B << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_500_125 (0x1C << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_500_100 (0x1D << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_600_150 (0x1E << MSAR_ARMDDRCLCK_OFFS) + + +#define MSAR_GIGA_PORT_MODE_OFFS 15 +#define MSAR_GIGA_PORT_MODE_MASK (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MSAR_GIGA_PORT_MODE_GMII (0x2 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_MII (0x3 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_RGMII (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MV_TARGET_IS_AS_BOOT(target) 0 + +#define BOOT_TARGETS_NAME_ARRAY {} + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + + + +#define MV_TARGET_IS_PEX1(target) \ + ((target >= PEX1_MEM) && (target <= PEX1_IO)) + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= FLASH_CS) && (target <= DEV_BOOCS)) + + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* typedefs */ + + +#ifndef MV_ASMLANGUAGE +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + SDRAM_CS2, /* SDRAM chip select 2 */ + SDRAM_CS3, /* SDRAM chip select 3 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + PEX1_MEM, /* PCI Express 1 Memory */ + PEX1_IO, /* PCI Express 1 IO */ + INTER_REGS, /* Internal registers */ + FLASH_CS, /* Flash chip select */ + DEV_BOOCS, /* Flash Boot chip select */ + MAX_TARGETS + +}MV_TARGET; + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PEX1_MEM0 PEX1_MEM + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO +#define PCI_IF1_MEM0 PEX1_MEM +#define PCI_IF1_IO PEX1_IO + + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> PCI Express */ + PEX1_TARGET_ID = 3 , /* Port 4 -> PCI Express0 */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + MAX_TARGETS_ID +}MV_TARGET_ID; + + +#define TARGETS_DEF_ARRAY { \ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ \ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ \ + {0x0B,DRAM_TARGET_ID}, /* SDRAM_CS2 */ \ + {0x07,DRAM_TARGET_ID}, /* SDRAM_CS3 */ \ + {0x59,PEX0_TARGET_ID}, /* PEX0_MEM */ \ + {0x51,PEX0_TARGET_ID}, /* PEX0_IO */ \ + {0x59,PEX1_TARGET_ID}, /* PEX1_MEM */ \ + {0x51,PEX1_TARGET_ID}, /* PEX1_IO */ \ + {0xFF, 0xFF}, /* INTER_REGS */ \ + {0x1B,DEV_TARGET_ID}, /* FLASH_CS */ \ + {0x0F,DEV_TARGET_ID} /* DEV_BOOCS*/ \ +} + + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS2 */ \ + "SDRAM_CS3", /* SDRAM_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "PEX1_MEM", /* PEX1_MEM */ \ + "PEX1_IO", /* PEX1_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "FLASH_CS", /* FLASH_CS */ \ + "DEV_BOOCS" /* DEV_BOOCS*/ \ +} + + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __IN88F1X81CtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5082EnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5082EnvSpec.h new file mode 100644 index 0000000..1e3e003 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5082EnvSpec.h @@ -0,0 +1,372 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __IN88F5082CtrlEnvSpech +#define __IN88F5082CtrlEnvSpech + + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +#define MV_ETH_REG_BASE(port) (0x72000 + ((port) << 0)) +#define USB_REG_BASE(dev) (((dev) == 0) ? 0x50000 : 0xA0000) + +#define INTER_REGS_SIZE _1M + + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 4 +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +/* This define describes the maximum controller supported DEVICE chip select */ +/* also known as banks */ +#define MV_DEVICE_MAX_CS 4 +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 +#define MV_BOOTDEVICE_INDEX 3 + + + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 2 + +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + +/* This define describes the maximum number of available SATA channels. */ +#define MV_SATA_MAX_CHAN 1 + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ + +#define MV_MPP_MAX_GROUP 3 + +/* This define describes the maximum number of supported PEX Interfaces */ +#if defined(MV_INCLUDE_PEX) +#define MV_PEX_MAX_IF 1 +#else +#define MV_PEX_MAX_IF 0 +#endif +#define MV_PEX_START_IF 0 + +/* This define describes the maximum number of supported PCI/PCIX Interfaces */ +#if defined(MV_INCLUDE_PCI) +#define MV_PCI_MAX_IF 1 +#else +#define MV_PCI_MAX_IF 0 +#endif +#define MV_PCI_START_IF MV_PEX_MAX_IF + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_HOST_BUS_NUM(pciIf) MV_PEX_MAX_IF + (pciIf) +#define PCI_HOST_DEV_NUM(pciIf) 0 + + +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_MAX_PORTS 1 +#define MV_ETH_PORT_SGMII { MV_FALSE } + +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 4 + +/* This define describes the the support of USB */ +#define MV_USB_MAX 2 +#define MV_USB_VERSION 0 + +/* This define describes the support of the NAND -Flash */ +#define MV_NAND_MAX 1 + + +#define SATA_REG_BASE 0x80000 + + +/* CESA version #2: One channel, 2KB SRAM, TDMA */ +#define MV_CESA_VERSION 0 +#define MV_CESA_REG_BASE 0x9D000 +#define MV_CESA_SRAM_SIZE 8*1024 + + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10050 +#define DEV_MULTI_CONTROL 0x10008 +#define MPP_SAMPLE_AT_RESET 0x10010 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) + +#define MSAR_TCLCK_OFFS 8 +#define MSAR_TCLCK_MASK (0x3 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_133 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_150 (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x2 << MSAR_TCLCK_OFFS) + +/* ARM CPU clock vs. DDR clock */ +/* This array is beening call from several files. + mvCpuArm.c, mvBoardEnvLib.c, mvCpuIfInit.S */ + +#define MV_CPU_IF_ARMDDRCLCK_TBL { \ + /* CPU FREQ, DDR FREQ, RATIO */ \ + {333333333, 166666667, 2}, \ + {400000000, 200000000, 2}, \ + {400000000, 133333334, 3}, \ + {500000000, 166666667, 3}, \ + {533333333, 133333334, 4}, \ + {600000000, 200000000, 3}, \ + {666666666, 166666667, 5}, \ + {800000000, 200000000, 4}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {480000000, 160000000, 3}, \ + {550000000, 183333334, 3}, \ + {525000000, 175000000, 3}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {466666666, 233333334, 2}, \ + {500000000, 250000000, 2}, \ + {533333333, 266666667, 2}, \ + {600000000, 300000000, 2}, \ + {450000000, 150000000, 3}, \ + {533333333, 178000000, 3}, \ + {575000000, 192000000, 3}, \ + {700000000, 175000000, 4}, \ + {733333333, 183333334, 4}, \ + {750000000, 187000000, 4}, \ + {775000000, 194000000, 4}, \ + {500000000, 125000000, 4}, \ + {500000000, 100000000, 5}, \ + {600000000, 150000000, 4}, \ + {1, 1, 1} \ +}; + + +#define MSAR_ARMDDRCLCK_OFFS 4 + +#define MSAR_ARMDDRCLCK_MASK (0xf << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_H_MASK BIT23 + + +#define MSAR_GIGA_PORT_MODE_OFFS 15 +#define MSAR_GIGA_PORT_MODE_MASK (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MSAR_GIGA_PORT_MODE_GMII (0x2 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_MII (0x3 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_RGMII (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + + + + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + + + +#define MV_TARGET_IS_PEX1(target) 0 + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) \ + ((MV_TARGET)((MV_U32)(bar - CS0_BAR) + (MV_U32)SDRAM_CS0)) + + +#define MV_TARGET_IS_AS_BOOT(target) 0 +#define BOOT_TARGETS_NAME_ARRAY {} +#define MV_CHANGE_BOOT_CS(target) (target) + + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* typedefs */ + + +#ifndef MV_ASMLANGUAGE +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + SDRAM_CS2, /* SDRAM chip select 2 */ + SDRAM_CS3, /* SDRAM chip select 3 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + INTER_REGS, /* Internal registers */ + DEVICE_CS0, /* Device chip select 0 */ + DEVICE_CS1, /* Device chip select 0 */ + DEVICE_CS2, /* Device chip select 0 */ + DEV_BOOCS, /* Flash Boot chip select */ + CRYPT_ENG, /* Crypto Engine */ + MAX_TARGETS + +}MV_TARGET; + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM + +/* For old competability */ +#define DEVICE_CS3 DEV_BOOCS + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +/* Device Interface registers offsets */ +#define DEV_BANK_PARAM_REG(num) (((num) == MV_BOOTDEVICE_INDEX) ? 0x1046C : (((num) * 4) + 0x1045C)) + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) (0x1 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) +#define DINFCR_NF_ACT_CE_MASK(csNum) (0x2 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) + + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO +#define PCI_IF1_MEM0 PCI0_MEM +#define PCI_IF1_IO PCI0_IO + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0 PCI0_MEM +#define PCI_IF0_IO PCI0_IO + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO + +#endif + + + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> PCI Express */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + CRYPT_TARGET_ID =9 , /* Port 9 --> Crypto Engine */ + MAX_TARGETS_ID +}MV_TARGET_ID; + + + +#define TARGETS_DEF_ARRAY { \ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ \ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ \ + {0x0B,DRAM_TARGET_ID}, /* SDRAM_CS2 */ \ + {0x07,DRAM_TARGET_ID}, /* SDRAM_CS3 */ \ + {0x59,PEX0_TARGET_ID}, /* PEX0_MEM */ \ + {0x51,PEX0_TARGET_ID}, /* PEX0_IO */ \ + {0xFF, 0xFF}, /* INTER_REGS */ \ + {0x1E,DEV_TARGET_ID}, /* DEVICE_CS0 */ \ + {0x1D,DEV_TARGET_ID}, /* DEVICE_CS1 */ \ + {0x1B,DEV_TARGET_ID}, /* DEVICE_CS2 */ \ + {0x0F,DEV_TARGET_ID}, /* DEV_BOOCS*/ \ + {0x00,CRYPT_TARGET_ID} /* CRYPT_ENG */ \ +} + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS2 */ \ + "SDRAM_CS3", /* SDRAM_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "DEVICE_CS0", /* DEVICE_CS0 */ \ + "DEVICE_CS1", /* DEVICE_CS1 */ \ + "DEVICE_CS2", /* DEVICE_CS2 */ \ + "DEV_BOOTCS", /* DEV_BOOTCS*/ \ + "CRYPT_ENG" /* CRYPT_ENG */ \ +} + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __IN88F5082CtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5180NEnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5180NEnvSpec.h new file mode 100644 index 0000000..702f521 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5180NEnvSpec.h @@ -0,0 +1,349 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __IN88F5180NCtrlEnvSpech +#define __IN88F5180NCtrlEnvSpech + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +/* includes */ + + +#define MV_ETH_REG_BASE(port) 0x72000 +#define USB_REG_BASE(dev) (((dev) == 0) ? 0x50000 : 0xA0000) + + +#define INTER_REGS_SIZE _1M + + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 4 +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +/* This define describes the maximum controller supported DEVICE chip select */ +/* also known as banks */ +#define MV_DEVICE_MAX_CS 4 +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 +#define MV_BOOTDEVICE_INDEX 3 + + + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 2 + +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ + +#define MV_MPP_MAX_GROUP 4 +/* This define describes the maximum number of supported PEX Interfaces */ +#if defined(MV_INCLUDE_PEX) +#define MV_PEX_MAX_IF 1 +#else +#define MV_PEX_MAX_IF 0 +#endif +#define MV_PEX_START_IF 0 + +/* This define describes the maximum number of supported PCI/PCIX Interfaces */ +#if defined(MV_INCLUDE_PCI) +#define MV_PCI_MAX_IF 1 +#else +#define MV_PCI_MAX_IF 0 +#endif +#define MV_PCI_START_IF MV_PEX_MAX_IF + + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_HOST_BUS_NUM(pciIf) MV_PEX_MAX_IF + (pciIf) +#define PCI_HOST_DEV_NUM(pciIf) 0 + + +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_MAX_PORTS 1 +#define MV_ETH_PORT_SGMII { MV_FALSE } + +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 4 + +/* This define describes the the support of USB */ +#define MV_USB_MAX 1 +#define MV_USB_VERSION 0 + +/* This define describes the support of the NAND -Flash */ +#define MV_NAND_MAX 1 + + +#define SATA_REG_BASE 0x80000 + + + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10050 +#define DEV_MULTI_CONTROL 0x10008 +#define MPP_SAMPLE_AT_RESET 0x10010 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) + +#define MSAR_TCLCK_OFFS 8 +#define MSAR_TCLCK_MASK (0x3 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_133 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_150 (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x2 << MSAR_TCLCK_OFFS) + +/* ARM CPU clock vs. DDR clock */ +/* This array is beening call from several files. + mvCpuArm.c, mvBoardEnvLib.c, mvCpuIfInit.S */ +#define MV_CPU_IF_ARMDDRCLCK_TBL { \ + /* CPU FREQ, DDR FREQ, RATIO */ \ + {333333333, 166666667, 2}, \ + {400000000, 200000000, 2}, \ + {400000000, 133333334, 3}, \ + {500000000, 166666667, 3}, \ + {533333333, 133333334, 4}, \ + {600000000, 200000000, 3}, \ + {666666666, 166666667, 5}, \ + {800000000, 200000000, 4}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {480000000, 160000000, 3}, \ + {550000000, 183333334, 3}, \ + {525000000, 175000000, 3}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {466666666, 233333334, 2}, \ + {500000000, 250000000, 2}, \ + {533333333, 266666667, 2}, \ + {600000000, 300000000, 2}, \ + {450000000, 150000000, 3}, \ + {533333333, 178000000, 3}, \ + {575000000, 192000000, 3}, \ + {700000000, 175000000, 4}, \ + {733333333, 183333334, 4}, \ + {750000000, 187000000, 4}, \ + {775000000, 194000000, 4}, \ + {500000000, 125000000, 4}, \ + {500000000, 100000000, 5}, \ + {600000000, 150000000, 4}, \ + {1, 1, 1} \ +}; + + +#define MSAR_ARMDDRCLCK_OFFS 4 + +#define MSAR_ARMDDRCLCK_MASK (0xf << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_H_MASK BIT23 + + + +#define MSAR_GIGA_PORT_MODE_OFFS 15 +#define MSAR_GIGA_PORT_MODE_MASK (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MSAR_GIGA_PORT_MODE_GMII (0x2 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_MII (0x3 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_RGMII (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + + + + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + +#define MV_TARGET_IS_PEX1(target) 0 + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_TARGET_IS_PCI(target) \ + ((target >= PCI0_MEM) && (target <= PCI0_IO)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) \ + ((MV_TARGET)((MV_U32)(bar - CS0_BAR) + (MV_U32)SDRAM_CS0)) + + +#define MV_TARGET_IS_AS_BOOT(target) 0 +#define BOOT_TARGETS_NAME_ARRAY {} +#define MV_CHANGE_BOOT_CS(target) (target) + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* typedefs */ + + +#ifndef MV_ASMLANGUAGE +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + SDRAM_CS2, /* SDRAM chip select 2 */ + SDRAM_CS3, /* SDRAM chip select 3 */ + PCI0_MEM, /* PCI Memory */ + PCI0_IO, /* PCI IO */ + INTER_REGS, /* Internal registers */ + DEVICE_CS0, /* Device chip select 0 */ + DEVICE_CS1, /* Device chip select 0 */ + DEVICE_CS2, /* Device chip select 0 */ + DEV_BOOCS, /* Flash Boot chip select */ + MAX_TARGETS + +}MV_TARGET; + +/* CV Support */ +#define PCI0_MEM0 PCI0_MEM + + +/* For old competability */ +#define DEVICE_CS3 DEV_BOOCS + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +/* Device Interface registers offsets */ +#define DEV_BANK_PARAM_REG(num) (((num) == MV_BOOTDEVICE_INDEX) ? 0x1046C : (((num) * 4) + 0x1045C)) + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) (0x1 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) +#define DINFCR_NF_ACT_CE_MASK(csNum) (0x2 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) + +#define PCI_IF0_MEM0 PCI0_MEM +#define PCI_IF0_IO PCI0_IO + + + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> PCI Express */ + PCI_TARGET_ID = 3 , /* Port 3 -> PCI */ + MAX_TARGETS_ID +}MV_TARGET_ID; + + + +#define TARGETS_DEF_ARRAY { \ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ \ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ \ + {0x0B,DRAM_TARGET_ID}, /* SDRAM_CS2 */ \ + {0x07,DRAM_TARGET_ID}, /* SDRAM_CS3 */ \ + {0x59,PCI_TARGET_ID}, /* PCI0_MEM */ \ + {0x51,PCI_TARGET_ID}, /* PCI0_IO */ \ + {0xFF, 0xFF}, /* INTER_REGS */ \ + {0x1E,DEV_TARGET_ID}, /* DEVICE_CS0 */ \ + {0x1D,DEV_TARGET_ID}, /* DEVICE_CS1 */ \ + {0x1B,DEV_TARGET_ID}, /* DEVICE_CS2 */ \ + {0x0F,DEV_TARGET_ID} /* DEV_BOOCS*/ \ +} + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS2 */ \ + "SDRAM_CS3", /* SDRAM_CS3 */ \ + "PCI0_MEM", /* PCI0_MEM */ \ + "PCI0_IO", /* PCI0_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "DEVICE_CS0", /* DEVICE_CS0 */ \ + "DEVICE_CS1", /* DEVICE_CS1 */ \ + "DEVICE_CS2", /* DEVICE_CS2 */ \ + "DEV_BOOCS" /* DEV_BOOCS*/ \ +} + + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __IN88F5180NCtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5181LEnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5181LEnvSpec.h new file mode 100644 index 0000000..78f956f --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5181LEnvSpec.h @@ -0,0 +1,381 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __IN88F5181LCtrlEnvSpech +#define __IN88F5181LCtrlEnvSpech + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +/* includes */ +#define MV_ETH_VERSION 0 +#define MV_ETH_MAX_PORTS 1 +#define MV_ETH_REG_BASE(port) (0x72000 + ((port) << 0)) +#define MV_ETH_PORT_SGMII { MV_FALSE } +#define USB_REG_BASE(dev) (((dev) == 0) ? 0x50000 : 0xA0000) + + +#define INTER_REGS_SIZE _1M + + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 4 +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +/* This define describes the maximum controller supported DEVICE chip select */ +/* also known as banks */ +#define MV_DEVICE_MAX_CS 4 +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 +#define MV_BOOTDEVICE_INDEX 3 + + + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 2 + +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ + +#define MV_MPP_MAX_GROUP 4 +/* This define describes the maximum number of supported PEX Interfaces */ +#if defined(MV_INCLUDE_PEX) +#define MV_PEX_MAX_IF 1 +#else +#define MV_PEX_MAX_IF 0 +#endif +#define MV_PEX_START_IF 0 + +/* This define describes the maximum number of supported PCI/PCIX Interfaces */ +#if defined(MV_INCLUDE_PCI) +#define MV_PCI_MAX_IF 1 +#else +#define MV_PCI_MAX_IF 0 +#endif +#define MV_PCI_START_IF MV_PEX_MAX_IF +#define MV_DISABLE_PEX_DEVICE_BAR + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_HOST_BUS_NUM(pciIf) MV_PEX_MAX_IF + (pciIf) +#define PCI_HOST_DEV_NUM(pciIf) 0 + + +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_MAX_PORTS 1 +#define MV_ETH_PORT_SGMII { MV_FALSE } + +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 4 + +/* This define describes the the support of USB */ +#define MV_USB_MAX 1 +#define MV_USB_VERSION 0 + +/* This define describes the support of the NAND -Flash */ +#define MV_NAND_MAX 1 + + +#define SATA_REG_BASE 0x80000 +#define TDM_REG_BASE 0xB0000 + +/* CESA version #2: One channel, 2KB SRAM, TDMA */ +#define MV_CESA_VERSION 0 +#define MV_CESA_REG_BASE 0x9D000 +#define MV_CESA_SRAM_SIZE 8*1024 + + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10050 +#define DEV_MULTI_CONTROL 0x10008 +#define MPP_SAMPLE_AT_RESET 0x10010 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) + +#define MSAR_TCLCK_OFFS 8 +#define MSAR_TCLCK_MASK (0x3 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_133 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_150 (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x2 << MSAR_TCLCK_OFFS) + +/* ARM CPU clock vs. DDR clock */ +/* This array is beening call from several files. + mvCpuArm.c, mvBoardEnvLib.c, mvCpuIfInit.S */ + +#define MV_CPU_IF_ARMDDRCLCK_TBL { \ + /* CPU FREQ, DDR FREQ, RATIO */ \ + {333333333, 166666667, 2}, \ + {400000000, 200000000, 2}, \ + {400000000, 133333334, 3}, \ + {500000000, 166666667, 3}, \ + {533333333, 133333334, 4}, \ + {600000000, 200000000, 3}, \ + {666666666, 166666667, 5}, \ + {800000000, 200000000, 4}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {480000000, 160000000, 3}, \ + {550000000, 183333334, 3}, \ + {525000000, 175000000, 3}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {466666666, 233333334, 2}, \ + {500000000, 250000000, 2}, \ + {533333333, 266666667, 2}, \ + {600000000, 300000000, 2}, \ + {450000000, 150000000, 3}, \ + {533333333, 178000000, 3}, \ + {575000000, 192000000, 3}, \ + {700000000, 175000000, 4}, \ + {733333333, 183333334, 4}, \ + {750000000, 187000000, 4}, \ + {775000000, 194000000, 4}, \ + {500000000, 125000000, 4}, \ + {500000000, 100000000, 5}, \ + {600000000, 150000000, 4}, \ + {1, 1, 1} \ +}; + +#define MSAR_ARMDDRCLCK_OFFS 4 +#define MSAR_ARMDDRCLCK_MASK (0xf << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_H_MASK BIT23 + + +#define MSAR_GIGA_PORT_MODE_OFFS 15 +#define MSAR_GIGA_PORT_MODE_MASK (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MSAR_GIGA_PORT_MODE_GMII (0x2 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_MII (0x3 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_RGMII (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + + + + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + + + +#define MV_TARGET_IS_PEX1(target) 0 + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_TARGET_IS_PCI(target) \ + ((target >= PCI0_MEM) && (target <= PCI0_IO)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) \ + ((MV_TARGET)((MV_U32)(bar - CS0_BAR) + (MV_U32)SDRAM_CS0)) + + +#define MV_TARGET_IS_AS_BOOT(target) 0 +#define BOOT_TARGETS_NAME_ARRAY {} +#define MV_CHANGE_BOOT_CS(target) (target) + + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* typedefs */ + + +#ifndef MV_ASMLANGUAGE +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + SDRAM_CS2, /* SDRAM chip select 2 */ + SDRAM_CS3, /* SDRAM chip select 3 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + PCI0_MEM, /* PCI Memory */ + PCI0_IO, /* PCI IO */ + INTER_REGS, /* Internal registers */ + DEVICE_CS0, /* Device chip select 0 */ + DEVICE_CS1, /* Device chip select 0 */ + DEVICE_CS2, /* Device chip select 0 */ + DEV_BOOCS, /* Flash Boot chip select */ + CRYPT_ENG, /* Crypto Engine */ + MAX_TARGETS + +}MV_TARGET; + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PCI0_MEM0 PCI0_MEM + + +/* For old competability */ +#define DEVICE_CS3 DEV_BOOCS + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +/* Device Interface registers offsets */ +#define DEV_BANK_PARAM_REG(num) (((num) == MV_BOOTDEVICE_INDEX) ? 0x1046C : (((num) * 4) + 0x1045C)) + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) (0x1 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) +#define DINFCR_NF_ACT_CE_MASK(csNum) (0x2 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) + + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO +#define PCI_IF1_MEM0 PCI0_MEM +#define PCI_IF1_IO PCI0_IO + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0 PCI0_MEM +#define PCI_IF0_IO PCI0_IO + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO + +#endif + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> PCI Express */ + PCI_TARGET_ID = 3 , /* Port 3 -> PCI */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + CRYPT_TARGET_ID =9 , /* Port 9 --> Crypto Engine */ + MAX_TARGETS_ID +}MV_TARGET_ID; + +#define TARGETS_DEF_ARRAY { \ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ \ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ \ + {0x0B,DRAM_TARGET_ID}, /* SDRAM_CS2 */ \ + {0x07,DRAM_TARGET_ID}, /* SDRAM_CS3 */ \ + {0x59,PEX0_TARGET_ID}, /* PEX0_MEM */ \ + {0x51,PEX0_TARGET_ID}, /* PEX0_IO */ \ + {0x59,PCI_TARGET_ID}, /* PCI0_MEM */ \ + {0x51,PCI_TARGET_ID}, /* PCI0_IO */ \ + {0xFF, 0xFF}, /* INTER_REGS */ \ + {0x1E,DEV_TARGET_ID}, /* DEVICE_CS0 */ \ + {0x1D,DEV_TARGET_ID}, /* DEVICE_CS1 */ \ + {0x1B,DEV_TARGET_ID}, /* DEVICE_CS2 */ \ + {0x0F,DEV_TARGET_ID}, /* DEV_BOOCS*/ \ + {0x00,CRYPT_TARGET_ID} /* CRYPT_ENG */ \ +} + + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS2 */ \ + "SDRAM_CS3", /* SDRAM_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "PCI0_MEM", /* PCI0_MEM */ \ + "PCI0_IO", /* PCI0_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "DEVICE_CS0", /* DEVICE_CS0 */ \ + "DEVICE_CS1", /* DEVICE_CS1 */ \ + "DEVICE_CS2", /* DEVICE_CS2 */ \ + "DEV_BOOCS", /* DEV_BOOCS*/ \ + "CRYPT_ENG" /* CRYPT_ENG */ \ +} + + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __IN88F5181LCtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5182EnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5182EnvSpec.h new file mode 100644 index 0000000..c3651b6 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5182EnvSpec.h @@ -0,0 +1,386 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __IN88F5182CtrlEnvSpech +#define __IN88F5182CtrlEnvSpech + + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +#define USB_REG_BASE(dev) (((dev) == 0) ? 0x50000 : 0xA0000) + +#define INTER_REGS_SIZE _1M + + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 4 +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +/* This define describes the maximum controller supported DEVICE chip select */ +/* also known as banks */ +#define MV_DEVICE_MAX_CS 4 +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 +#define MV_BOOTDEVICE_INDEX 3 + + + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 2 + +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + +/* This define describes the maximum number of available SATA channels. */ +#define MV_SATA_MAX_CHAN 2 + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ + +#define MV_MPP_MAX_GROUP 3 + +/* This define describes the maximum number of supported PEX Interfaces */ +#if defined(MV_INCLUDE_PEX) +#define MV_PEX_MAX_IF 1 +#else +#define MV_PEX_MAX_IF 0 +#endif +#define MV_PEX_START_IF 0 + +/* This define describes the maximum number of supported PCI/PCIX Interfaces */ +#if defined(MV_INCLUDE_PCI) +#define MV_PCI_MAX_IF 1 +#else +#define MV_PCI_MAX_IF 0 +#endif +#define MV_PCI_START_IF MV_PEX_MAX_IF + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_HOST_BUS_NUM(pciIf) MV_PEX_MAX_IF + (pciIf) +#define PCI_HOST_DEV_NUM(pciIf) 0 + + +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_VERSION 1 +#define MV_ETH_REG_BASE(port) (0x72000 + ((port) << 0)) +#define MV_ETH_MAX_PORTS 1 +#define MV_ETH_PORT_SGMII { MV_FALSE } + +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 4 + +/* This define describes the the support of USB */ +#define MV_USB_MAX 2 +#define MV_USB_VERSION 0 + + +/* This define describes the support of the NAND -Flash */ +#define MV_NAND_MAX 1 + + +#define SATA_REG_BASE 0x80000 + +/* CESA version #2: One channel, 2KB SRAM, TDMA */ +#define MV_CESA_VERSION 0 +#define MV_CESA_REG_BASE 0x9D000 +#define MV_CESA_SRAM_SIZE 8*1024 + + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10050 +#define DEV_MULTI_CONTROL 0x10008 +#define MPP_SAMPLE_AT_RESET 0x10010 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) + +#define MSAR_TCLCK_OFFS 8 +#define MSAR_TCLCK_MASK (0x3 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_133 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_150 (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x2 << MSAR_TCLCK_OFFS) + +/* ARM CPU clock vs. DDR clock */ +/* This array is beening call from several files. + mvCpuArm.c, mvBoardEnvLib.c, mvCpuIfInit.S */ + +#define MV_CPU_IF_ARMDDRCLCK_TBL { \ + /* CPU FREQ, DDR FREQ, RATIO */ \ + {333333333, 166666667, 2}, \ + {400000000, 200000000, 2}, \ + {400000000, 133333334, 3}, \ + {500000000, 166666667, 3}, \ + {533333333, 133333334, 4}, \ + {600000000, 200000000, 3}, \ + {666666666, 166666667, 5}, \ + {800000000, 200000000, 4}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {480000000, 160000000, 3}, \ + {550000000, 183333334, 3}, \ + {525000000, 175000000, 3}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {466666666, 233333334, 2}, \ + {500000000, 250000000, 2}, \ + {533333333, 266666667, 2}, \ + {600000000, 300000000, 2}, \ + {450000000, 150000000, 3}, \ + {533333333, 178000000, 3}, \ + {575000000, 192000000, 3}, \ + {700000000, 175000000, 4}, \ + {733333333, 183333334, 4}, \ + {750000000, 187000000, 4}, \ + {775000000, 194000000, 4}, \ + {500000000, 125000000, 4}, \ + {500000000, 100000000, 5}, \ + {600000000, 150000000, 4}, \ + {1, 1, 1} \ +}; + +#define MSAR_ARMDDRCLCK_OFFS 4 + +#define MSAR_ARMDDRCLCK_MASK (0xf << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_H_MASK BIT23 + + +#define MSAR_GIGA_PORT_MODE_OFFS 15 +#define MSAR_GIGA_PORT_MODE_MASK (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MSAR_GIGA_PORT_MODE_GMII (0x2 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_MII (0x3 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_RGMII (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + + + + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + + + +#define MV_TARGET_IS_PEX1(target) 0 + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_TARGET_IS_PCI(target) \ + ((target >= PCI0_MEM) && (target <= PCI0_IO)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) \ + ((MV_TARGET)((MV_U32)(bar - CS0_BAR) + (MV_U32)SDRAM_CS0)) + +#define MV_TARGET_IS_AS_BOOT(target) 0 + +#define MV_CHANGE_BOOT_CS(target) (target) + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* typedefs */ + + +#ifndef MV_ASMLANGUAGE +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + SDRAM_CS2, /* SDRAM chip select 2 */ + SDRAM_CS3, /* SDRAM chip select 3 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + PCI0_MEM, /* PCI Memory */ + PCI0_IO, /* PCI IO */ + INTER_REGS, /* Internal registers */ + DEVICE_CS0, /* Device chip select 0 */ + DEVICE_CS1, /* Device chip select 0 */ + DEVICE_CS2, /* Device chip select 0 */ + DEV_BOOCS, /* Flash Boot chip select */ + CRYPT_ENG, /* Crypto Engine */ + MAX_TARGETS + +}MV_TARGET; + + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PCI0_MEM0 PCI0_MEM + + +#define BOOT_TARGETS_NAME_ARRAY {} + +/* For old competability */ +#define DEVICE_CS3 DEV_BOOCS + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +/* Device Interface registers offsets */ +#define DEV_BANK_PARAM_REG(num) (((num) == MV_BOOTDEVICE_INDEX) ? 0x1046C : (((num) * 4) + 0x1045C)) + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) (0x1 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) +#define DINFCR_NF_ACT_CE_MASK(csNum) (0x2 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) + + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO +#define PCI_IF1_MEM0 PCI0_MEM +#define PCI_IF1_IO PCI0_IO + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0 PCI0_MEM +#define PCI_IF0_IO PCI0_IO + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO + +#endif + + + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> PCI Express */ + PCI_TARGET_ID = 3 , /* Port 3 -> PCI */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + CRYPT_TARGET_ID =9 , /* Port 9 --> Crypto Engine */ + MAX_TARGETS_ID +}MV_TARGET_ID; + + +#define TARGETS_DEF_ARRAY { \ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ \ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ \ + {0x0B,DRAM_TARGET_ID}, /* SDRAM_CS2 */ \ + {0x07,DRAM_TARGET_ID}, /* SDRAM_CS3 */ \ + {0x59,PEX0_TARGET_ID}, /* PEX0_MEM */ \ + {0x51,PEX0_TARGET_ID}, /* PEX0_IO */ \ + {0x59,PCI_TARGET_ID}, /* PCI0_MEM */ \ + {0x51,PCI_TARGET_ID}, /* PCI0_IO */ \ + {0xFF, 0xFF}, /* INTER_REGS */ \ + {0x1E,DEV_TARGET_ID}, /* DEVICE_CS0 */ \ + {0x1D,DEV_TARGET_ID}, /* DEVICE_CS1 */ \ + {0x1B,DEV_TARGET_ID}, /* DEVICE_CS2 */ \ + {0x0F,DEV_TARGET_ID}, /* DEV_BOOCS*/ \ + {0x00,CRYPT_TARGET_ID} /* CRYPT_ENG */ \ +} + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS2 */ \ + "SDRAM_CS3", /* SDRAM_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "PCI0_MEM", /* PCI0_MEM */ \ + "PCI0_IO", /* PCI0_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "DEVICE_CS0", /* DEVICE_CS0 */ \ + "DEVICE_CS1", /* DEVICE_CS1 */ \ + "DEVICE_CS2", /* DEVICE_CS2 */ \ + "DEV_BOOCS", /* DEV_BOOCS*/ \ + "CRYPT_ENG" /* CRYPT_ENG */ \ +} + + + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __IN88F5182CtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5X81EnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5X81EnvSpec.h new file mode 100644 index 0000000..95d2a91 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F5X81EnvSpec.h @@ -0,0 +1,379 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __IN88F5X81CtrlEnvSpech +#define __IN88F5X81CtrlEnvSpech + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +/* includes */ + + +#define USB_REG_BASE(dev) (((dev) == 0) ? 0x50000 : 0xA0000) + + +#define INTER_REGS_SIZE _1M + + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 4 +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +/* This define describes the maximum controller supported DEVICE chip select */ +/* also known as banks */ +#define MV_DEVICE_MAX_CS 4 +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 +#define MV_BOOTDEVICE_INDEX 3 + + + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 2 + +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ + +#define MV_MPP_MAX_GROUP 4 +/* This define describes the maximum number of supported PEX Interfaces */ +#if defined(MV_INCLUDE_PEX) +#define MV_DISABLE_PEX_DEVICE_BAR +#define MV_PEX_MAX_IF 1 +#else +#define MV_PEX_MAX_IF 0 +#endif +#define MV_PEX_START_IF 0 + +/* This define describes the maximum number of supported PCI/PCIX Interfaces */ +#if defined(MV_INCLUDE_PCI) +#define MV_PCI_MAX_IF 1 +#else +#define MV_PCI_MAX_IF 0 +#endif +#define MV_PCI_START_IF MV_PEX_MAX_IF + +#define MV_DISABLE_PEX_DEVICE_BAR + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_HOST_BUS_NUM(pciIf) MV_PEX_MAX_IF + (pciIf) +#define PCI_HOST_DEV_NUM(pciIf) 0 + + +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_VERSION 1 +#define MV_ETH_MAX_TXQ 1 +#define MV_ETH_REG_BASE(port) (0x72000 + ((port) << 0)) +#define MV_ETH_MAX_PORTS 1 +#define MV_ETH_PORT_SGMII { MV_FALSE } + +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 4 + +/* This define describes the the support of USB */ +#define MV_USB_MAX 1 +#define MV_USB_VERSION 0 + +/* This define describes the support of the NAND -Flash */ +#define MV_NAND_MAX 1 + + +#define SATA_REG_BASE 0x80000 + + + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10050 +#define DEV_MULTI_CONTROL 0x10008 +#define MPP_SAMPLE_AT_RESET 0x10010 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) + +#define MSAR_TCLCK_OFFS 8 +#define MSAR_TCLCK_MASK (0x3 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_133 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_150 (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x2 << MSAR_TCLCK_OFFS) + +/* ARM CPU clock vs. DDR clock */ +/* This array is beening call from several files. + mvCpuArm.c, mvBoardEnvLib.c, mvCpuIfInit.S */ + +#define MV_CPU_IF_ARMDDRCLCK_TBL { \ + /* CPU FREQ, DDR FREQ, RATIO */ \ + {333333333, 166666667, 2}, \ + {400000000, 200000000, 2}, \ + {400000000, 133333334, 3}, \ + {500000000, 166666667, 3}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {500000000, 250000000, 2}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0} \ +}; + +#define MSAR_ARMDDRCLCK_OFFS 4 + +#define MSAR_ARMDDRCLCK_MASK (0xf << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_H_MASK BIT23 + + +#define MSAR_GIGA_PORT_MODE_OFFS 15 +#define MSAR_GIGA_PORT_MODE_MASK (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MSAR_GIGA_PORT_MODE_GMII (0x2 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_MII (0x3 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_RGMII (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + + + + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + +#define MV_TARGET_IS_PEX1(target) 0 + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_TARGET_IS_PCI(target) \ + ((target >= PCI0_MEM) && (target <= PCI0_IO)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) \ + ((MV_TARGET)((MV_U32)(bar - CS0_BAR) + (MV_U32)SDRAM_CS0)) + + +#define MV_TARGET_IS_AS_BOOT(target) 0 +#define BOOT_TARGETS_NAME_ARRAY {} +#define MV_CHANGE_BOOT_CS(target) (target) + + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* typedefs */ + + +#ifndef MV_ASMLANGUAGE +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + SDRAM_CS2, /* SDRAM chip select 2 */ + SDRAM_CS3, /* SDRAM chip select 3 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + PCI0_MEM, /* PCI Memory */ + PCI0_IO, /* PCI IO */ + INTER_REGS, /* Internal registers */ + DEVICE_CS0, /* Device chip select 0 */ + DEVICE_CS1, /* Device chip select 0 */ + DEVICE_CS2, /* Device chip select 0 */ + DEV_BOOCS, /* Flash Boot chip select */ + MAX_TARGETS + +}MV_TARGET; + + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PCI0_MEM0 PCI0_MEM + + +/* For old competability */ +#define DEVICE_CS3 DEV_BOOCS + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +/* Device Interface registers offsets */ +#define DEV_BANK_PARAM_REG(num) (((num) == MV_BOOTDEVICE_INDEX) ? 0x1046C : (((num) * 4) + 0x1045C)) + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) (0x1 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) +#define DINFCR_NF_ACT_CE_MASK(csNum) (0x2 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) + + + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO +#define PCI_IF1_MEM0 PCI0_MEM +#define PCI_IF1_IO PCI0_IO + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0 PCI0_MEM +#define PCI_IF0_IO PCI0_IO + +#elif defined (MV_INCLUDE_PEX) + + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO + +#endif + + + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> PCI Express */ + PCI_TARGET_ID = 3 , /* Port 3 -> PCI */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + MAX_TARGETS_ID +}MV_TARGET_ID; + +#define TARGETS_DEF_ARRAY { \ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ \ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ \ + {0x0B,DRAM_TARGET_ID}, /* SDRAM_CS2 */ \ + {0x07,DRAM_TARGET_ID}, /* SDRAM_CS3 */ \ + {0x59,PEX0_TARGET_ID}, /* PEX0_MEM */ \ + {0x51,PEX0_TARGET_ID}, /* PEX0_IO */ \ + {0x59,PCI_TARGET_ID}, /* PCI0_MEM */ \ + {0x51,PCI_TARGET_ID}, /* PCI0_IO */ \ + {0xFF, 0xFF}, /* INTER_REGS */ \ + {0x1E,DEV_TARGET_ID}, /* DEVICE_CS0 */ \ + {0x1D,DEV_TARGET_ID}, /* DEVICE_CS1 */ \ + {0x1B,DEV_TARGET_ID}, /* DEVICE_CS2 */ \ + {0x0F,DEV_TARGET_ID} /* DEV_BOOCS*/ \ +} + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS2 */ \ + "SDRAM_CS3", /* SDRAM_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "PCI0_MEM", /* PCI0_MEM */ \ + "PCI0_IO", /* PCI0_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "DEVICE_CS0", /* DEVICE_CS0 */ \ + "DEVICE_CS1", /* DEVICE_CS1 */ \ + "DEVICE_CS2", /* DEVICE_CS2 */ \ + "DEV_BOOCS" /* DEV_BOOCS*/ \ +} + + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __IN88F5X81CtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F6082EnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F6082EnvSpec.h new file mode 100644 index 0000000..e021ab4 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F6082EnvSpec.h @@ -0,0 +1,394 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __IN88F6082CtrlEnvSpech +#define __IN88F6082CtrlEnvSpech + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +#define USB_REG_BASE(dev) (((dev) == 0) ? 0x50000 : 0xA0000) + +#define INTER_REGS_SIZE _1M + + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 2 +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 + +/* This define describes the maximum controller supported DEVICE chip select */ +/* also known as banks */ +#define MV_DEVICE_MAX_CS 5 +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 +#define MV_INCLUDE_DEVICE_CS4 +#define MV_BOOTDEVICE_INDEX 0 + + +#define MV_INCLUDE_CLK_PWR_CNTRL + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 2 + +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + +/* This define describes the maximum number of available SATA channels. */ +#define MV_SATA_MAX_CHAN 1 + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ +#define MV_MPP_MAX_GROUP 2 + +/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ +#define MV_PCI_MAX_IF 0 +#define MV_PCI_START_IF 0 + +/* This define describes the maximum number of supported PEX Interfaces */ +#define MV_INCLUDE_PEX0 +#if defined(MV_INCLUDE_PEX) +#define MV_PEX_MAX_IF 1 +#else +#define MV_PEX_MAX_IF 0 +#endif +#define MV_PEX_START_IF MV_PCI_MAX_IF + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_HOST_BUS_NUM(pciIf) MV_PEX_MAX_IF + (pciIf) +#define PCI_HOST_DEV_NUM(pciIf) 0 + +/* CESA version #2: One channel, 2KB SRAM, TDMA */ +#define MV_CESA_VERSION 2 +#define MV_CESA_REG_BASE 0x3D000 +#define MV_CESA_TDMA_REG_BASE 0x30000 +#define MV_CESA_SRAM_SIZE 2*1024 + + +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_VERSION 2 + +#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x82000) +#define MV_ETH_MAX_PORTS 2 +#define MV_ETH_PORT_SGMII { MV_TRUE, MV_TRUE } + +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 0 + +/* This define describes the the support of USB */ +#define MV_USB_MAX 1 +#define MV_USB_VERSION 1 + + +/* This define describes the support of the NAND -Flash */ +#define MV_NAND_MAX 1 + + +#define SATA_REG_BASE 0x60000 + +/* Controler environment registers offsets */ + +/* Power Managment Control */ +#define POWER_MNG_CTRL_REG 0x2011C + +#define PMC_GESTOPCLOCK_OFFS(port) (port) +#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_EN(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_STOP(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) + +#define PMC_PEXSTOPCLOCK_OFFS 2 +#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) +#define PMC_PEXSTOPCLOCK_EN (0 << PMC_PEXSTOPCLOCK_OFFS) +#define PMC_PEXSTOPCLOCK_STOP (1 << PMC_PEXSTOPCLOCK_OFFS) + +#define PMC_USBSTOPCLOCK_OFFS 3 +#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) +#define PMC_USBSTOPCLOCK_EN (0 << PMC_USBSTOPCLOCK_OFFS) +#define PMC_USBSTOPCLOCK_STOP (1 << PMC_USBSTOPCLOCK_OFFS) + +#define PMC_SATASTOPCLOCK_OFFS 4 +#define PMC_SATASTOPCLOCK_MASK (1 << PMC_SATASTOPCLOCK_OFFS) +#define PMC_SATASTOPCLOCK_EN (0 << PMC_SATASTOPCLOCK_OFFS) +#define PMC_SATASTOPCLOCK_STOP (1 << PMC_SATASTOPCLOCK_OFFS) + +#define PMC_SESTOPCLOCK_OFFS 5 +#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) +#define PMC_SESTOPCLOCK_EN (0 << PMC_SESTOPCLOCK_OFFS) +#define PMC_SESTOPCLOCK_STOP (1 << PMC_SESTOPCLOCK_OFFS) + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +/* #define MPP_CONTROL_REG2 0x10050 */ +/* #define DEV_MULTI_CONTROL 0x10008 */ +#define MPP_SAMPLE_AT_RESET 0x10010 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) + +#define MSAR_BOOT_MODE_OFFS 0 +#define MSAR_DBOOT_MODE_MASK (0xF << MSAR_BOOT_MODE_OFFS) +#define MSAR_DBOOT_EMB_PMFLASH (0x0 << MSAR_BOOT_MODE_OFFS) +#define MSAR_DBOOT_EMB_SMFLASH (0x1 << MSAR_BOOT_MODE_OFFS) +#define MSAR_DBOOT_EXT_SPI (0x2 << MSAR_BOOT_MODE_OFFS) +#define MSAR_CPU_RST_EXT_SPI_PROG (0x3 << MSAR_BOOT_MODE_OFFS) +#define MSAR_DBOOT_NAND (0x4 << MSAR_BOOT_MODE_OFFS) +#define MSAR_IDBOOT_EMB_PMFLASH (0x5 << MSAR_BOOT_MODE_OFFS) +#define MSAR_IDBOOT_EMB_SMFLASH (0x6 << MSAR_BOOT_MODE_OFFS) +#define MSAR_IDBOOT_EXT_SPI (0x7 << MSAR_BOOT_MODE_OFFS) +#define MSAR_IDBOOT_EXT_SPI_REG (0x8 << MSAR_BOOT_MODE_OFFS) +#define MSAR_IDBOOT_EXT_SPI_PROG (0x9 << MSAR_BOOT_MODE_OFFS) +#define MSAR_IDBOOT_UART (0xA << MSAR_BOOT_MODE_OFFS) +#define MSAR_IDBOOT_SATA (0xB << MSAR_BOOT_MODE_OFFS) +#define MSAR_IDBOOT_NAND (0xC << MSAR_BOOT_MODE_OFFS) + +#define MSAR_TCLCK_OFFS 14 +#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_133 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) + +/* This array is beening call from several files. + mvCpuArm.c, mvBoardEnvLib.c, mvCpuIfInit.S */ +/* ARM CPU clock vs. DDR clock */ +#define MV_CPU_IF_ARMDDRCLCK_TBL {\ + /* CPU FREQ, DDR FREQ, RATIO */\ + {333333333, 166666667, 2},\ + {300000000, 150000000, 2},\ + {400000000, 200000000, 2},\ + {400000000, 133333334, 3},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0}\ +}; + +/* Both giga ports actes as SGMII only */ +#define MSAR_GIGA_PORT_MODE_OFFS 0 +#define MSAR_GIGA_PORT_MODE_MASK (0x0 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MSAR_GIGA_PORT_MODE_SGMII (0x0 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_GMII (0x1 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_MII (0x1 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_RGMII (0x1 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MSAR_ARMDDRCLCK_OFFS 4 +#define MSAR_ARMDDRCLCK_MASK (0x7 << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_H_MASK BIT23 + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS1)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + +#define MV_TARGET_IS_PEX1(target) 0 + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS4)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 + +#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ + & MSAR_DBOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) + + +#define MV_CHANGE_BOOT_CS(target) ((target) == DEV_BOOCS)?\ + sampleAtResetTargetArray[((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ + & MSAR_DBOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)]\ + :(target) + + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* typedefs */ + + +#ifndef MV_ASMLANGUAGE +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + INTER_REGS, /* Internal registers */ + NFLASH_CS, /* NFLASH_CS */ + MFLASH_CS, /* MFLASH_CS */ + SPI_CS, /* SPI_CS */ + BOOT_ROM_CS, /* BOOT_ROM_CS */ + DEV_BOOCS, /* DEV_BOOCS */ + CRYPT_ENG, /* Crypto Engine */ + MAX_TARGETS + +}MV_TARGET; + + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM + + +#define BOOT_TARGETS_NAME_ARRAY { \ + MFLASH_CS, \ + MFLASH_CS, \ + SPI_CS, \ + TBL_TERM, \ + NFLASH_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS \ +} + +/* For old competability */ +#define DEVICE_CS0 NFLASH_CS +#define DEVICE_CS1 MFLASH_CS +#define DEVICE_CS2 SPI_CS +#define DEVICE_CS3 BOOT_ROM_CS +#define DEVICE_CS4 DEV_BOOCS + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +/* registers offsets */ +#define DEV_BANK_PARAM_REG(num) (((num)==0) ? 0x1046C : (((num)==1) ? 0x10500 : 0x10600)) +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) (0x1) +#define DINFCR_NF_ACT_CE_MASK(csNum) (0x2) + + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO +#define PCI_IF1_MEM0 PEX1_MEM +#define PCI_IF1_IO PEX1_IO + + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> PCI Express */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + CRYPT_TARGET_ID =3 , /* Port 3 --> Crypto Engine */ + MAX_TARGETS_ID +}MV_TARGET_ID; + + + +#define TARGETS_DEF_ARRAY { \ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ \ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ \ + {0x59,PEX0_TARGET_ID}, /* PEX0_MEM */ \ + {0x51,PEX0_TARGET_ID}, /* PEX0_IO */ \ + {0xFF, 0xFF}, /* INTER_REGS */ \ + {0x1B,DEV_TARGET_ID}, /* NFLASH_CS */ \ + {0xF,DEV_TARGET_ID}, /* MFLASH_CS */ \ + {0x1E,DEV_TARGET_ID}, /* SPI_CS */ \ + {0x1D,DEV_TARGET_ID}, /* BOOT_ROM_CS */ \ + {0xF,DEV_TARGET_ID}, /* DEV_BOOCS */ \ + {0x00,CRYPT_TARGET_ID} /* CRYPT_ENG */ \ +} + + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "NFLASH_CS", /* NFLASH_CS */ \ + "MFLASH_CS", /* MFLASH_CS */ \ + "SPI_CS", /* SPI_CS */ \ + "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ + "DEV_BOOTCS", /* DEV_BOOCS */ \ + "CRYPT_ENG" /* CRYPT_ENG */ \ +} + + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __IN88F6082CtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F6183EnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F6183EnvSpec.h new file mode 100644 index 0000000..fe896aa --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F6183EnvSpec.h @@ -0,0 +1,375 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __IN88F6183CtrlEnvSpech +#define __IN88F6183CtrlEnvSpech + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +#define USB_REG_BASE(dev) (((dev) == 0) ? 0x50000 : 0xA0000) +#define AUDIO_REG_BASE 0xB0000 + +#define INTER_REGS_SIZE _1M + + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 2 +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 + +/* This define describes the maximum controller supported DEVICE chip select */ +/* also known as banks */ +#define MV_DEVICE_MAX_CS 2 +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_BOOTDEVICE_INDEX 0 + + +#define MV_INCLUDE_CLK_PWR_CNTRL + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 2 + +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + +/* This define describes the maximum number of available SATA channels. */ +#define MV_SATA_MAX_CHAN 0 + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ +#define MV_MPP_MAX_GROUP 2 + +/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ +#define MV_PCI_MAX_IF 0 +#define MV_PCI_START_IF 0 + +/* This define describes the maximum number of supported PEX Interfaces */ +#define MV_INCLUDE_PEX0 +#if defined(MV_INCLUDE_PEX) +#define MV_PEX_MAX_IF 1 +#else +#define MV_PEX_MAX_IF 0 +#endif +#define MV_PEX_START_IF MV_PCI_MAX_IF + +#define MV_DISABLE_PEX_DEVICE_BAR +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_HOST_BUS_NUM(pciIf) MV_PEX_MAX_IF + (pciIf) +#define PCI_HOST_DEV_NUM(pciIf) 0 + +/* CESA version #2: One channel, 2KB SRAM, TDMA */ +#define MV_CESA_VERSION 2 +#define MV_CESA_REG_BASE 0x3D000 +#define MV_CESA_SRAM_SIZE 2*1024 +#define MV_CESA_TDMA_REG_BASE 0x30000 + +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_VERSION 2 +#define MV_ETH_MAX_RXQ 8 +#define MV_ETH_MAX_TXQ 1 + +#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x82000) +#define MV_ETH_MAX_PORTS 1 +#define MV_ETH_PORT_SGMII { MV_FALSE } + +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 4 + +/* This define describes the the support of USB */ +#define MV_USB_MAX_CHAN 1 +#define MV_USB_MAX 1 +#define MV_USB_VERSION 1 + + +/* This define describes the support of the NAND -Flash */ +#define MV_NAND_MAX 1 + + +#define SATA_REG_BASE 0x60000 + +/* Controler environment registers offsets */ + +/* Power Managment Control */ +#define POWER_MNG_CTRL_REG 0x2011C + +#define PMC_GESTOPCLOCK_OFFS(port) (port) +#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_EN(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_STOP(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) + +#define PMC_PEXSTOPCLOCK_OFFS 2 +#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) +#define PMC_PEXSTOPCLOCK_EN (0 << PMC_PEXSTOPCLOCK_OFFS) +#define PMC_PEXSTOPCLOCK_STOP (1 << PMC_PEXSTOPCLOCK_OFFS) + +#define PMC_USBSTOPCLOCK_OFFS 3 +#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) +#define PMC_USBSTOPCLOCK_EN (0 << PMC_USBSTOPCLOCK_OFFS) +#define PMC_USBSTOPCLOCK_STOP (1 << PMC_USBSTOPCLOCK_OFFS) + +#define PMC_SATASTOPCLOCK_OFFS 4 +#define PMC_SATASTOPCLOCK_MASK (1 << PMC_SATASTOPCLOCK_OFFS) +#define PMC_SATASTOPCLOCK_EN (0 << PMC_SATASTOPCLOCK_OFFS) +#define PMC_SATASTOPCLOCK_STOP (1 << PMC_SATASTOPCLOCK_OFFS) + +#define PMC_SESTOPCLOCK_OFFS 5 +#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) +#define PMC_SESTOPCLOCK_EN (0 << PMC_SESTOPCLOCK_OFFS) +#define PMC_SESTOPCLOCK_STOP (1 << PMC_SESTOPCLOCK_OFFS) + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10008 +#define MPP_CONTROL_REG3 0x1000C +#define MPP_SAMPLE_AT_RESET 0x10010 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) + +#define MSAR_BOOT_MODE_OFFS 0 +#define MSAR_BOOT_MODE_MASK (0x1 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_NAND (0x0 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_EXT_SPI (0x1 << MSAR_BOOT_MODE_OFFS) + +#define MSAR_TCLCK_OFFS 9 +#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_133 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) + +/* This array is beening call from several files. + mvCpuArm.c, mvBoardEnvLib.c, mvCpuIfInit.S */ +/* ARM CPU clock vs. DDR clock */ +#define MV_CPU_IF_ARMDDRCLCK_TBL {\ + /* CPU FREQ, DDR FREQ, RATIO */\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {333333333, 166666667, 2},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {400000000, 200000000, 2},\ +}; + +/* Both giga ports actes as SGMII only */ +#define MSAR_GIGA_PORT_MODE_OFFS 0 +#define MSAR_GIGA_PORT_MODE_MASK (0x0 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MSAR_GIGA_PORT_MODE_SGMII (0x0 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_GMII (0x1 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_MII (0x1 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_RGMII (0x1 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MSAR_ARMDDRCLCK_OFFS 1 +#define MSAR_ARMDDRCLCK_MASK (0x3F << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_H_MASK 0 + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS1)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + +#define MV_TARGET_IS_PEX1(target) 0 + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS1)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 + +#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ + & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) + + +#define MV_CHANGE_BOOT_CS(target) ((target) == DEV_BOOCS)?\ + sampleAtResetTargetArray[((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ + & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)]\ + :(target) + +#define MV_CPU_ADDRESS_DECODE_WA +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* typedefs */ + + +#ifndef MV_ASMLANGUAGE +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + INTER_REGS, /* Internal registers */ + NFLASH_CS, /* NFLASH_CS */ + SPI_CS, /* SPI_CS */ + DEV_BOOCS, /* DEV_BOOCS */ + CRYPT_ENG, /* Crypto Engine */ + MAX_TARGETS + +}MV_TARGET; + + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PCI0_MEM0 PEX0_MEM + + +#define BOOT_TARGETS_NAME_ARRAY { \ + NFLASH_CS, \ + SPI_CS, \ + TBL_TERM, \ +} + +/* For old competability */ +#define DEVICE_CS0 NFLASH_CS +#define DEVICE_CS1 SPI_CS + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +/* registers offsets */ +#define DEV_BANK_PARAM_REG(num) (((num)==0) ? 0x1046C : 0x10604) +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) (0x1) +#define DINFCR_NF_ACT_CE_MASK(csNum) (0x2) + + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO +#define PCI_IF1_MEM0 PEX1_MEM +#define PCI_IF1_IO PEX1_IO + +#define PCI_IO(pciIf) (PEX0_IO) +#define PCI_MEM(pciIf, memNum) (PEX0_MEM) + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> PCI Express */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + CRYPT_TARGET_ID =3 , /* Port 3 --> Crypto Engine */ + MAX_TARGETS_ID +}MV_TARGET_ID; + + + +#define TARGETS_DEF_ARRAY { \ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ \ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ \ + {0x59,PEX0_TARGET_ID}, /* PEX0_MEM */ \ + {0x51,PEX0_TARGET_ID}, /* PEX0_IO */ \ + {0xFF, 0xFF}, /* INTER_REGS */ \ + {0x1B,DEV_TARGET_ID}, /* NFLASH_CS */ \ + {0x1E,DEV_TARGET_ID}, /* SPI_CS */ \ + {0x1E,DEV_TARGET_ID}, /* DEV_BOOCS */ \ + {0x00,CRYPT_TARGET_ID} /* CRYPT_ENG */ \ +} + + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "NFLASH_CS", /* NFLASH_CS */ \ + "SPI_CS", /* SPI_CS */ \ + "DEV_BOOTCS", /* DEV_BOOCS */ \ + "CRYPT_ENG" /* CRYPT_ENG */ \ +} + + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __IN88F6183CtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F6183LEnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F6183LEnvSpec.h new file mode 100644 index 0000000..91fe710 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88F6183LEnvSpec.h @@ -0,0 +1,341 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __IN88F6183LCtrlEnvSpech +#define __IN88F6183LCtrlEnvSpech + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + +#define USB_REG_BASE(dev) (((dev) == 0) ? 0x50000 : 0xA0000) +#define AUDIO_REG_BASE 0xB0000 + +#define INTER_REGS_SIZE _1M + + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 2 +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 + +/* This define describes the maximum controller supported DEVICE chip select */ +/* also known as banks */ +#define MV_DEVICE_MAX_CS 2 +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_BOOTDEVICE_INDEX 0 + + +#define MV_INCLUDE_CLK_PWR_CNTRL + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 2 + +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + +/* This define describes the maximum number of available SATA channels. */ +#define MV_SATA_MAX_CHAN 0 + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ +#define MV_MPP_MAX_GROUP 2 + +/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ +#define MV_PCI_MAX_IF 0 +#define MV_PCI_START_IF 0 + +/* This define describes the maximum number of supported PEX Interfaces */ +#define MV_INCLUDE_PEX0 +#if defined(MV_INCLUDE_PEX) +#define MV_PEX_MAX_IF 1 +#else +#define MV_PEX_MAX_IF 0 +#endif +#define MV_PEX_START_IF MV_PCI_MAX_IF + +#define MV_DISABLE_PEX_DEVICE_BAR + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_HOST_BUS_NUM(pciIf) MV_PEX_MAX_IF + (pciIf) +#define PCI_HOST_DEV_NUM(pciIf) 0 + +/* CESA version #2: One channel, 2KB SRAM, TDMA */ +#define MV_CESA_VERSION 2 +#define MV_CESA_REG_BASE 0x3D000 +#define MV_CESA_SRAM_SIZE 2*1024 +#define MV_CESA_TDMA_REG_BASE 0x30000 +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 4 + +/* This define describes the support of the NAND -Flash */ +#define MV_NAND_MAX 1 + +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_MAX_PORTS 0 +#define MV_ETH_PORT_SGMII { MV_FALSE } + +#define SATA_REG_BASE 0x60000 + +/* Controler environment registers offsets */ + +/* Power Managment Control */ +#define POWER_MNG_CTRL_REG 0x2011C + +#define PMC_PEXSTOPCLOCK_OFFS 2 +#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) +#define PMC_PEXSTOPCLOCK_EN (0 << PMC_PEXSTOPCLOCK_OFFS) +#define PMC_PEXSTOPCLOCK_STOP (1 << PMC_PEXSTOPCLOCK_OFFS) + +#define PMC_SATASTOPCLOCK_OFFS 4 +#define PMC_SATASTOPCLOCK_MASK (1 << PMC_SATASTOPCLOCK_OFFS) +#define PMC_SATASTOPCLOCK_EN (0 << PMC_SATASTOPCLOCK_OFFS) +#define PMC_SATASTOPCLOCK_STOP (1 << PMC_SATASTOPCLOCK_OFFS) + +#define PMC_SESTOPCLOCK_OFFS 5 +#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) +#define PMC_SESTOPCLOCK_EN (0 << PMC_SESTOPCLOCK_OFFS) +#define PMC_SESTOPCLOCK_STOP (1 << PMC_SESTOPCLOCK_OFFS) + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10008 +#define MPP_CONTROL_REG3 0x1000C +#define MPP_SAMPLE_AT_RESET 0x10010 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) + +#define MSAR_BOOT_MODE_OFFS 0 +#define MSAR_BOOT_MODE_MASK (0x1 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_NAND (0x0 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_EXT_SPI (0x1 << MSAR_BOOT_MODE_OFFS) + +#define MSAR_TCLCK_OFFS 9 +#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_133 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) + +/* This array is beening call from several files. + mvCpuArm.c, mvBoardEnvLib.c, mvCpuIfInit.S */ +/* ARM CPU clock vs. DDR clock */ +#define MV_CPU_IF_ARMDDRCLCK_TBL {\ + /* CPU FREQ, DDR FREQ, RATIO */\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {333333333, 166666667, 2},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ + {0, 0, 0},\ +}; + +#define MSAR_ARMDDRCLCK_OFFS 1 +#define MSAR_ARMDDRCLCK_MASK (0x3F << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_H_MASK 0 + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS1)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + +#define MV_TARGET_IS_PEX1(target) 0 + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS1)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 + +#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ + & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) + + +#define MV_CHANGE_BOOT_CS(target) ((target) == DEV_BOOCS)?\ + sampleAtResetTargetArray[((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ + & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)]\ + :(target) + +#define MV_CPU_ADDRESS_DECODE_WA +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* typedefs */ + + +#ifndef MV_ASMLANGUAGE +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + INTER_REGS, /* Internal registers */ + NFLASH_CS, /* NFLASH_CS */ + SPI_CS, /* SPI_CS */ + DEV_BOOCS, /* DEV_BOOCS */ + CRYPT_ENG, /* Crypto Engine */ + MAX_TARGETS + +}MV_TARGET; + + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM + + +#define BOOT_TARGETS_NAME_ARRAY { \ + NFLASH_CS, \ + SPI_CS, \ + TBL_TERM, \ +} + +/* For old competability */ +#define DEVICE_CS0 NFLASH_CS +#define DEVICE_CS1 SPI_CS + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +/* registers offsets */ +#define DEV_BANK_PARAM_REG(num) (((num)==0) ? 0x1046C : 0x10604) +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) (0x1) +#define DINFCR_NF_ACT_CE_MASK(csNum) (0x2) + + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO +#define PCI_IF1_MEM0 PEX1_MEM +#define PCI_IF1_IO PEX1_IO + + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> PCI Express */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + CRYPT_TARGET_ID =3 , /* Port 3 --> Crypto Engine */ + MAX_TARGETS_ID +}MV_TARGET_ID; + + + +#define TARGETS_DEF_ARRAY { \ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ \ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ \ + {0x59,PEX0_TARGET_ID}, /* PEX0_MEM */ \ + {0x51,PEX0_TARGET_ID}, /* PEX0_IO */ \ + {0xFF, 0xFF}, /* INTER_REGS */ \ + {0x1B,DEV_TARGET_ID}, /* NFLASH_CS */ \ + {0x1E,DEV_TARGET_ID}, /* SPI_CS */ \ + {0x1E,DEV_TARGET_ID}, /* DEV_BOOCS */ \ + {0x00,CRYPT_TARGET_ID} /* CRYPT_ENG */ \ +} + + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "NFLASH_CS", /* NFLASH_CS */ \ + "SPI_CS", /* SPI_CS */ \ + "DEV_BOOTCS", /* DEV_BOOCS */ \ + "CRYPT_ENG" /* CRYPT_ENG */ \ +} + + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __IN88F6183LCtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88w8660EnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88w8660EnvSpec.h new file mode 100644 index 0000000..3978b13 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mv88w8660EnvSpec.h @@ -0,0 +1,367 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __IN88W8660CtrlEnvSpech +#define __IN88W8660CtrlEnvSpech + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88W" +/* includes */ + + +/* defines */ + + +#define MV_ETH_REG_BASE(port) 0x72000 +#define USB_REG_BASE(dev) (((dev) == 0) ? 0x50000 : 0xA0000) + + +#define INTER_REGS_SIZE _1M + + +/* This define describes the maximum controller supported DRAM chip select */ +/* also known as banks */ +#define MV_DRAM_MAX_CS 2 +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 + +/* This define describes the maximum controller supported DEVICE chip select */ +/* also known as banks */ +#define MV_DEVICE_MAX_CS 4 +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 +#define MV_BOOTDEVICE_INDEX 3 + + + +/* This define describes maximum of GPP groups supported by controller. */ +#define MV_GPP_MAX_GROUP 1 + + +/* This define describes the maximum number of available Timer/counters. */ +#define MV_CNTMR_MAX_COUNTER 2 + +/* This define describes the maximum number of available UART channels. */ +#define MV_UART_MAX_CHAN 2 + + + +/* This define describes maximum number of MPP groups. */ +/* Each group describes an MPP register. */ + +#define MV_MPP_MAX_GROUP 2 +/* This define describes the maximum number of supported PEX Interfaces */ +#if defined(MV_INCLUDE_PEX) +#define MV_PEX_MAX_IF 1 +#else +#define MV_PEX_MAX_IF 0 +#endif +#define MV_PEX_START_IF 0 + +/* This define describes the maximum number of supported PCI/PCIX Interfaces */ +#if defined(MV_INCLUDE_PCI) +#define MV_PCI_MAX_IF 1 +#else +#define MV_PCI_MAX_IF 0 +#endif +#define MV_PCI_START_IF MV_PEX_MAX_IF + + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + + +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_HOST_BUS_NUM(pciIf) MV_PEX_MAX_IF + (pciIf) +#define PCI_HOST_DEV_NUM(pciIf) 0 + + +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_MAX_PORTS 1 +#define MV_ETH_PORT_SGMII { MV_FALSE } + +/* This define describes the maximum number of supported IDMA channels. */ +#define MV_IDMA_MAX_CHAN 4 + +/* This define describes the the support of USB */ +#define MV_USB_MAX 1 +#define MV_USB_VERSION 0 + +/* This define describes the support of the NAND -Flash */ +#define MV_NAND_MAX 1 + + +#define SATA_REG_BASE 0x80000 + + + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10050 +#define DEV_MULTI_CONTROL 0x10008 +#define MPP_SAMPLE_AT_RESET 0x10010 +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) + +#define MSAR_TCLCK_OFFS 8 +#define MSAR_TCLCK_MASK (0x3 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_133 (0x0 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_150 (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x2 << MSAR_TCLCK_OFFS) + +/* ARM CPU clock vs. DDR clock */ +/* This array is beening call from several files. + mvCpuArm.c, mvBoardEnvLib.c, mvCpuIfInit.S */ + +#define MV_CPU_IF_ARMDDRCLCK_TBL { \ + /* CPU FREQ, DDR FREQ, RATIO */ \ + {333333333, 166666667, 2}, \ + {400000000, 200000000, 2}, \ + {400000000, 133333334, 3}, \ + {500000000, 166666667, 3}, \ + {533333333, 133333334, 4}, \ + {600000000, 200000000, 3}, \ + {666666666, 166666667, 5}, \ + {800000000, 200000000, 4}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {480000000, 160000000, 3}, \ + {550000000, 183333334, 3}, \ + {525000000, 175000000, 3}, \ + {0, 0, 0}, \ + {0, 0, 0}, \ + {466666666, 233333334, 2}, \ + {500000000, 250000000, 2}, \ + {533333333, 266666667, 2}, \ + {600000000, 300000000, 2}, \ + {450000000, 150000000, 3}, \ + {533333333, 178000000, 3}, \ + {575000000, 192000000, 3}, \ + {700000000, 175000000, 4}, \ + {733333333, 183333334, 4}, \ + {750000000, 187000000, 4}, \ + {775000000, 194000000, 4}, \ + {500000000, 125000000, 4}, \ + {500000000, 100000000, 5}, \ + {600000000, 150000000, 4}, \ + {1, 1, 1} \ +}; + +#define MSAR_ARMDDRCLCK_OFFS 4 + +#define MSAR_ARMDDRCLCK_MASK (0xf << MSAR_ARMDDRCLCK_OFFS) +#define MSAR_ARMDDRCLCK_H_MASK BIT23 + +#define MSAR_GIGA_PORT_MODE_OFFS 15 +#define MSAR_GIGA_PORT_MODE_MASK (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + +#define MSAR_GIGA_PORT_MODE_GMII (0x2 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_MII (0x3 << MSAR_GIGA_PORT_MODE_OFFS) +#define MSAR_GIGA_PORT_MODE_RGMII (0x7 << MSAR_GIGA_PORT_MODE_OFFS) + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS1)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + + +#define MV_TARGET_IS_PEX1(target) 0 + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_TARGET_IS_PCI(target) \ + ((target >= PCI0_MEM) && (target <= PCI0_IO)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) \ + ((MV_TARGET)((MV_U32)(bar - CS0_BAR) + (MV_U32)SDRAM_CS0)) + + +#define MV_TARGET_IS_AS_BOOT(target) 0 + +#define MV_CHANGE_BOOT_CS(target) (target) + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ +/* typedefs */ + + +#ifndef MV_ASMLANGUAGE +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + PCI0_MEM, /* PCI Memory */ + PCI0_IO, /* PCI IO */ + INTER_REGS, /* Internal registers */ + DEVICE_CS0, /* Device chip select 0 */ + DEVICE_CS1, /* Device chip select 0 */ + DEVICE_CS2, /* Device chip select 0 */ + DEV_BOOCS, /* Flash Boot chip select */ + MAX_TARGETS + +}MV_TARGET; + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PCI0_MEM0 PCI0_MEM + + +#define BOOT_TARGETS_NAME_ARRAY {} + +/* For old competability */ +#define DEVICE_CS3 DEV_BOOCS + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +/* Device Interface registers offsets */ +#define DEV_BANK_PARAM_REG(num) (((num) == MV_BOOTDEVICE_INDEX) ? 0x1046C : (((num) * 4) + 0x1045C)) + +/* Device Interface NAND Flash Control Register (DINFCR) */ +#define DINFCR_NF_CS_MASK(csNum) (0x1 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) +#define DINFCR_NF_ACT_CE_MASK(csNum) (0x2 << ((((csNum)+1) % MV_DEVICE_MAX_CS) * 2)) + + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO +#define PCI_IF1_MEM0 PCI0_MEM +#define PCI_IF1_IO PCI0_IO + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0 PCI0_MEM +#define PCI_IF0_IO PCI0_IO + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO + +#endif + + + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> PCI Express */ + PCI_TARGET_ID = 3 , /* Port 3 -> PCI */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + MAX_TARGETS_ID +}MV_TARGET_ID; + + +#define TARGETS_DEF_ARRAY { \ + {0x0E,DRAM_TARGET_ID}, /* SDRAM_CS0 */ \ + {0x0D,DRAM_TARGET_ID}, /* SDRAM_CS1 */ \ + {0x59,PEX0_TARGET_ID}, /* PEX0_MEM */ \ + {0x51,PEX0_TARGET_ID}, /* PEX0_IO */ \ + {0x59,PCI_TARGET_ID}, /* PCI0_MEM */ \ + {0x51,PCI_TARGET_ID}, /* PCI0_IO */ \ + {0xFF, 0xFF}, /* INTER_REGS */ \ + {0x1E,DEV_TARGET_ID}, /* DEVICE_CS0 */ \ + {0x1D,DEV_TARGET_ID}, /* DEVICE_CS1 */ \ + {0x1B,DEV_TARGET_ID}, /* DEVICE_CS2 */ \ + {0x0F,DEV_TARGET_ID} /* DEV_BOOCS*/ \ +} + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "PCI0_MEM", /* PCI0_MEM */ \ + "PCI0_IO", /* PCI0_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "DEVICE_CS0", /* DEVICE_CS0 */ \ + "DEVICE_CS1", /* DEVICE_CS1 */ \ + "DEVICE_CS2", /* DEVICE_CS2 */ \ + "DEV_BOOCS" /* DEV_BOOCS*/ \ +} + + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __IN88W8660CtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvAddrDec.c b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvAddrDec.c new file mode 100644 index 0000000..9325db9 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvAddrDec.c @@ -0,0 +1,296 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvCtrlEnvAddrDec.h - Marvell controller address decode library +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "ddr1_2/mvDramIfRegs.h" +#include "pex/mvPexRegs.h" + +#define MV_DEBUG + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* Default Attributes array */ +MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; +extern MV_TARGET sampleAtResetTargetArray[]; +/* Dram\AHBToMbus\PEX share regsiter */ + +#define CTRL_DEC_BASE_OFFS 16 +#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) +#define CTRL_DEC_BASE_ALIGNMENT 0x10000 + +#define CTRL_DEC_SIZE_OFFS 16 +#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) +#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 + +#define CTRL_DEC_WIN_EN BIT0 + + + +/******************************************************************************* +* mvCtrlAddrDecToReg - Get address decode register format values +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) +{ + + MV_U32 baseToReg=0 , sizeToReg=0; + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; + + /* Write to address decode Base Address Register */ + pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; + pAddrDecRegs->baseReg |= baseToReg; + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + return MV_BAD_PARAM; + } + + /* set size */ + pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; + pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); + + + return MV_OK; + +} + +/******************************************************************************* +* mvCtrlRegToAddrDec - Extract address decode struct from registers. +* +* DESCRIPTION: +* This function extract address decode struct from address decode +* registers given as parameters. +* +* INPUT: +* pAddrDecRegs - Address decode register struct. +* +* OUTPUT: +* pAddrDecWin - Target window data structure. +* +* RETURN: +* MV_BAD_PARAM if address decode registers data is invalid. +* +*******************************************************************************/ +MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 sizeRegVal; + + sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> + CTRL_DEC_SIZE_OFFS; + + pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); + + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; + + pAddrDecWin->baseHigh = 0; + + return MV_OK; + +} + +/******************************************************************************* +* mvCtrlAttribGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ + +MV_STATUS mvCtrlAttribGet(MV_TARGET target, + MV_TARGET_ATTRIB *targetAttrib) +{ + + targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; + targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; + + return MV_OK; + +} + +/******************************************************************************* +* mvCtrlGetAttrib - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) +{ + MV_TARGET target; + MV_TARGET x; + for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) + { + x = MV_CHANGE_BOOT_CS(target); + if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && + (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) + { + /* found it */ + break; + } + } + + return target; +} + +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, + MV_DEC_WIN_PARAMS *pWinParam) +{ + MV_U32 baseToReg=0, sizeToReg=0; + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; + + /* Write to address decode Base Address Register */ + pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; + pWinParam->baseAddr |= baseToReg; + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); + return MV_BAD_PARAM; + } + pWinParam->size = sizeToReg; + + pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; + pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; + + return MV_OK; +} + +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, + MV_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttrib; + + pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; + + /* Upper 32bit address base is supported under PCI High Address remap */ + pAddrDecWin->addrWin.baseHigh = 0; + + /* Prepare sizeReg to ctrlRegToSize function */ + pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); + + if (-1 == pAddrDecWin->addrWin.size) + { + DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); + return MV_BAD_PARAM; + } + targetAttrib.targetId = pWinParam->targetId; + targetAttrib.attrib = pWinParam->attrib; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; +} + + + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvAddrDec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvAddrDec.h new file mode 100644 index 0000000..54be842 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvAddrDec.h @@ -0,0 +1,201 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAddrDech +#define __INCmvCtrlEnvAddrDech + +/* includes */ +#include "mvCtrlEnvLib.h" + +/* defines */ +/* DUnit attributes */ +#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 +#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 +#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) + +#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 +#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 +#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) + +#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 +#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 +#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) + +#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 +#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 +#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) + +/* RUnit (Device) attributes */ +#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 +#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 +#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 +#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 +#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 +#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 +#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) + +#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 +#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 +#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) + +/* LMaster (PCI) attributes */ +#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) + + +#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 +#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 +#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) + +#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 + +#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 +#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 +#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) +#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) + +#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 +#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 +#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 +#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 +#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +/* PEX Attributes */ +#define ATMWCR_WIN_PEX_TYPE_OFFS 3 +#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 +#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) +#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) + +/* typedefs */ + +/* Unsupported attributes for address decode: */ +/* 2) PCI0/1_REQ64n control */ + +typedef struct _mvDecRegs +{ + MV_U32 baseReg; + MV_U32 baseRegHigh; + MV_U32 sizeReg; + +}MV_DEC_REGS; + +typedef struct _mvTargetAttrib +{ + MV_U8 attrib; /* chip select attributes */ + MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ + +}MV_TARGET_ATTRIB; + + +/* This structure describes address decode window */ +typedef struct _mvDecWin +{ + MV_TARGET target; /* Target for addr decode window */ + MV_ADDR_WIN addrWin; /* Address window of target */ + MV_BOOL enable; /* Window enable/disable */ +}MV_DEC_WIN; + +typedef struct _mvDecWinParams +{ + MV_TARGET_ID targetId; /* Target ID field */ + MV_U8 attrib; /* Attribute field */ + MV_U32 baseAddr; /* Base address in register format */ + MV_U32 size; /* Size in register format */ +}MV_DEC_WIN_PARAMS; + + +/* mvCtrlEnvAddrDec API list */ + +MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, + MV_DEC_REGS *pAddrDecRegs); + +MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, + MV_ADDR_WIN *pAddrDecWin); + +MV_STATUS mvCtrlAttribGet(MV_TARGET target, + MV_TARGET_ATTRIB *targetAttrib); + +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); + + +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, + MV_DEC_WIN_PARAMS *pWinParam); + +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, + MV_DEC_WIN *pAddrDecWin); + + + + +#endif /* __INCmvCtrlEnvAddrDech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvAsm.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvAsm.h new file mode 100644 index 0000000..4a04374 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvAsm.h @@ -0,0 +1,217 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAsmh +#define __INCmvCtrlEnvAsmh +#include "pci/mvPciRegs.h" + +/* Read device ID into toReg bits 15:0 from 0xd0000000 */ +/* defines */ +#if defined(MV_88F5180N) +#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + ldr toReg, =MV_5180_DEV_ID +#elif defined(MV_88F5082) +#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + ldr toReg, =MV_5082_DEV_ID +#else +#if defined(MV_INCLUDE_PEX) +#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID));\ + mov toReg, toReg, LSR #PXDAVI_DEV_ID_OFFS /* toReg = toReg >> 16 */ + +#elif defined(MV_INCLUDE_PCI) +#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + /* Read bus number */ \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PCI_P2P_CONFIG_REG(0));\ + mov tmpReg, toReg; \ + and toReg, toReg, #PPCR_BUS_NUM_MASK; \ + /* Read dev number */ \ + and tmpReg, tmpReg, #PPCR_DEV_NUM_MASK; \ + orr toReg, tmpReg, LSR #(PPCR_DEV_NUM_OFFS - PCAR_DEVICE_NUM_OFFS); /* toReg = toReg | (tmpReg >> 13) */\ + /* Set PCI config enable BIT31 */ \ + orr toReg, toReg, #PCAR_CONFIG_EN; \ + /* Write the address to the PCI configuration address register */\ + MV_DV_REG_WRITE_ASM(toReg, tmpReg, PCI_CONFIG_ADDR_REG(0));\ + /* In order to let the PCI controller absorbed the address of the read */\ + /* transaction we perform a validity check that the address was written */\ + MV_DV_REG_READ_ASM(toReg, tmpReg, PCI_CONFIG_ADDR_REG(0)); \ + /* Read the Data returned in the PCI Data register */\ + MV_DV_REG_READ_ASM(toReg, tmpReg, PCI_CONFIG_DATA_REG(0)); \ + mov toReg, toReg, LSR #PDVIR_DEV_ID_OFFS /* toReg = toReg >> 16 */ +#else + #error "No Way to get Device ID" +#endif /* MV_INCLUDE_PEX */ +#endif /* MV_88F5180N */ + +/* Read device ID into toReg bits 15:0 from 0xf1000000*/ + +#if defined(MV_88F5180N) +#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + ldr toReg, =MV_5180_DEV_ID +#elif defined(MV_88F5082) +#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + ldr toReg, =MV_5082_DEV_ID +#else +#if defined(MV_INCLUDE_PEX) +#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID));\ + mov toReg, toReg, LSR #PXDAVI_DEV_ID_OFFS /* toReg = toReg >> 16 */ + +#elif defined(MV_INCLUDE_PCI) +#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + /* Read bus number */ \ + MV_REG_READ_ASM(toReg, tmpReg, PCI_P2P_CONFIG_REG(0));\ + mov tmpReg, toReg; \ + and toReg, toReg, #PPCR_BUS_NUM_MASK; \ + /* Read dev number */ \ + and tmpReg, tmpReg, #PPCR_DEV_NUM_MASK; \ + orr toReg, tmpReg, LSR #(PPCR_DEV_NUM_OFFS - PCAR_DEVICE_NUM_OFFS); /* toReg = toReg | (tmpReg >> 13) */\ + /* Set PCI config enable BIT31 */ \ + orr toReg, toReg, #PCAR_CONFIG_EN; \ + /* Write the address to the PCI configuration address register */\ + MV_REG_WRITE_ASM(toReg, tmpReg, PCI_CONFIG_ADDR_REG(0));\ + /* In order to let the PCI controller absorbed the address of the read */\ + /* transaction we perform a validity check that the address was written */\ + MV_REG_READ_ASM(toReg, tmpReg, PCI_CONFIG_ADDR_REG(0)); \ + /* Read the Data returned in the PCI Data register */\ + MV_REG_READ_ASM(toReg, tmpReg, PCI_CONFIG_DATA_REG(0)); \ + mov toReg, toReg, LSR #PDVIR_DEV_ID_OFFS /* toReg = toReg >> 16 */ +#else + #error "No Way to get Device ID" +#endif /* MV_INCLUDE_PEX */ +#endif /* MV_88F5180N */ + + +/* Read Revision into toReg bits 7:0 0xd0000000*/ +#if defined(MV_88F5180N) +#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + ldr toReg, =MV_5180N_B1_REV +#else +#if defined(MV_INCLUDE_PEX) +#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, #PXCCARI_REVID_MASK /* Mask for calss ID */ +#elif defined(MV_INCLUDE_PCI) +#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read bus number */ \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PCI_P2P_CONFIG_REG(0));\ + mov tmpReg, toReg; \ + and toReg, toReg, #PPCR_BUS_NUM_MASK; \ + /* Read dev number */ \ + and tmpReg, tmpReg, #PPCR_DEV_NUM_MASK; \ + orr toReg, tmpReg, LSR #(PPCR_DEV_NUM_OFFS - PCAR_DEVICE_NUM_OFFS); /* toReg = toReg | (tmpReg >> 13) */\ + /* Set PCI config enable BIT31 */ \ + orr toReg, toReg, #PCAR_CONFIG_EN; \ + orr toReg, toReg, #(PCI_CLASS_CODE_AND_REVISION_ID);\ + /* Write the address to the PCI configuration address register */\ + MV_DV_REG_WRITE_ASM(toReg, tmpReg, PCI_CONFIG_ADDR_REG(0));\ + /* In order to let the PCI controller absorbed the address of the read */\ + /* transaction we perform a validity check that the address was written */\ + MV_DV_REG_READ_ASM(toReg, tmpReg, PCI_CONFIG_ADDR_REG(0));\ + /* Read the Data returned in the PCI Data register */\ + MV_DV_REG_READ_ASM(toReg, tmpReg, PCI_CONFIG_DATA_REG(0));\ + and toReg, toReg, #PCCRIR_REVID_MASK +#else + #error "No Way to get Revision ID" +#endif /* MV_INCLUDE_PEX */ +#endif /* MV_88F5180N */ + +/* Read Revision into toReg bits 7:0 0xf1000000*/ +#if defined(MV_88F5180N) +#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + ldr toReg, =MV_5180N_B1_REV +#else +#if defined(MV_INCLUDE_PEX) +#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, #PXCCARI_REVID_MASK /* Mask for calss ID */ +#elif defined(MV_INCLUDE_PCI) +#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read bus number */ \ + MV_REG_READ_ASM(toReg, tmpReg, PCI_P2P_CONFIG_REG(0));\ + mov tmpReg, toReg; \ + and toReg, toReg, #PPCR_BUS_NUM_MASK; \ + /* Read dev number */ \ + and tmpReg, tmpReg, #PPCR_DEV_NUM_MASK; \ + orr toReg, tmpReg, LSR #(PPCR_DEV_NUM_OFFS - PCAR_DEVICE_NUM_OFFS); /* toReg = toReg | (tmpReg >> 13) */\ + /* Set PCI config enable BIT31 */ \ + orr toReg, toReg, #PCAR_CONFIG_EN; \ + orr toReg, toReg, #(PCI_CLASS_CODE_AND_REVISION_ID);\ + /* Write the address to the PCI configuration address register */\ + MV_REG_WRITE_ASM(toReg, tmpReg, PCI_CONFIG_ADDR_REG(0));\ + /* In order to let the PCI controller absorbed the address of the read */\ + /* transaction we perform a validity check that the address was written */\ + MV_REG_READ_ASM(toReg, tmpReg, PCI_CONFIG_ADDR_REG(0));\ + /* Read the Data returned in the PCI Data register */\ + MV_REG_READ_ASM(toReg, tmpReg, PCI_CONFIG_DATA_REG(0));\ + and toReg, toReg, #PCCRIR_REVID_MASK +#else + #error "No Way to get Revision ID" +#endif /* MV_INCLUDE_PEX */ +#endif /* MV_88F5180N */ + +#endif /* __INCmvCtrlEnvAsmh */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvLib.c new file mode 100644 index 0000000..b2682f7 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvLib.c @@ -0,0 +1,1300 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "mvCommon.h" +#include "mvCtrlEnvLib.h" +#include "mvCtrlEnvPadCalibration.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +#if defined(MV_INCLUDE_PCI) || defined(MV_INCLUDE_PEX) +#include "pci-if/mvPciIf.h" +#endif + +#if defined(MV_INCLUDE_PCI) +#include "pci/mvPci.h" +#include "ctrlEnv/sys/mvSysPci.h" +#endif + +#if defined(MV_INCLUDE_PEX) +#include "ctrlEnv/sys/mvSysPex.h" +#endif + +#if defined(MV_INCLUDE_IDMA) +#include "ctrlEnv/sys/mvSysIdma.h" +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#include "ctrlEnv/sys/mvSysGbe.h" +#endif + +#if defined(MV_INCLUDE_XOR) +#include "ctrlEnv/sys/mvSysXor.h" +#endif + +#if defined (MV_INCLUDE_INTEG_MFLASH) +#include "mflash/mvPMFlashSpec.h" +#endif + +#if defined(MV_INCLUDE_SATA) +#include "ctrlEnv/sys/mvSysSata.h" +#endif + +#if defined(MV_INCLUDE_USB) +#include "ctrlEnv/sys/mvSysUsb.h" +#endif + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* Global paramters initial value '-1' to indicate they are uninitialized. */ +/* In case of data section is located in ROM, this value will not be able */ +/* to change. */ +MV_U32 ctrlDevModel = -1; +MV_U32 ctrlDevRev = -1; + + +/******************************************************************************* +* mv64xxxInit - Initialize Marvell controller environment. +* +* DESCRIPTION: +* This function get environment information and initialize controller +* internal/external environment. For example +* 1) MPP settings according to board MPP macros. +* NOTE: It is the user responsibility to shut down all DMA channels +* in device and disable controller sub units interrupts during +* boot process. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCtrlEnvInit(MV_VOID) +{ +#if defined(MV_88F6183L) + /* Updating initial value of power control register for 6183L according to FS*/ + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, (BIT0 | BIT3 | BIT4)); +#endif + MV_U32 mppGroup; + /* Read MPP group from board level and assign to MPP register */ + for (mppGroup = 0; mppGroup < MV_MPP_MAX_GROUP; mppGroup++) + { + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mvBoardMppGet(mppGroup)); + } + +#if defined(MV_88F6183) + /* Add pad calibration for 6183 & 6183L*/ + mvCtrlEnvPadCalibrationInit(); +#endif + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlMppRegGet - return reg address of mpp group +* +* DESCRIPTION: +* +* INPUT: +* mppGroup - MPP group. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 - Register address. +* +*******************************************************************************/ +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) +{ + MV_U32 ret; + + switch(mppGroup){ + case (0): ret = MPP_CONTROL_REG0; + break; + case (1): ret = MPP_CONTROL_REG1; + break; +#if !defined(MV_88F6082) + case (2): ret = MPP_CONTROL_REG2; + break; +#if defined(MV_88F6183) || defined(MV_88F6183L) + case (3): ret = MPP_CONTROL_REG3; + break; +#else + case (3): ret = DEV_MULTI_CONTROL; + break; +#endif +#endif + default: ret = MPP_CONTROL_REG0; + break; + } + return ret; +} +#if defined(MV_INCLUDE_PCI) +/******************************************************************************* +* mvCtrlPciMaxIfGet - Get Marvell controller number of PCI interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PCI interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PCI interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPciMaxIfGet(MV_VOID) +{ + + return MV_PCI_MAX_IF; +} +#endif + +#if defined(MV_INCLUDE_PCI) || defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCtrlPciIfiMaxIfGet - Get Marvell controller number of PCI interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PCI interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PCI interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPciIfMaxIfGet(MV_VOID) +{ + + return MV_PCI_IF_MAX_IF; +} +#endif + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxIfGet(MV_VOID) +{ + + return MV_PEX_MAX_IF; +} +#endif + +#if defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) +/******************************************************************************* +* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of etherent port. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of etherent port. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlEthMaxPortGet(MV_VOID) +{ + return MV_ETH_MAX_PORTS; +} +#endif + +#if defined(MV_INCLUDE_IDMA) +/******************************************************************************* +* mvCtrlIdmaMaxChanGet - Get Marvell controller number of IDMA channels. +* +* DESCRIPTION: +* This function returns Marvell controller number of IDMA channels. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of IDMA channels. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlIdmaMaxChanGet(MV_VOID) +{ + return MV_IDMA_MAX_CHAN; +} +#endif + +#if defined(MV_INCLUDE_USB) +/******************************************************************************* +* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* returns number of Marvell USB controllers. +* +*******************************************************************************/ +MV_U32 mvCtrlUsbMaxGet(void) +{ + return MV_USB_MAX; + +} +#endif + + +#if defined(MV_INCLUDE_NAND) + +/******************************************************************************* +* mvCtrlNandSupport - Return if this controller has integrated NAND flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if NAND is supported and MV_FALSE otherwise +* +*******************************************************************************/ + +MV_U32 mvCtrlNandSupport(MV_VOID) +{ +#if defined(MV_88F5181) + if (mvCtrlModelGet() == MV_5281_DEV_ID) + { + return MV_NAND_MAX; + } + else + { + return 0; + } +#else + return MV_NAND_MAX; +#endif +} +#endif + +/******************************************************************************* +* mvCtrlModelGet - Get Marvell controller device model (Id) +* +* DESCRIPTION: +* This function returns 16bit describing the device model (ID) as defined +* in PCI Device and Vendor ID configuration register offset 0x0. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit desscribing Marvell controller ID +* +*******************************************************************************/ +MV_U16 mvCtrlModelGet(MV_VOID) +{ +#if defined(MV_88F5180N) + return MV_5180_DEV_ID; +#elif defined(MV_88F5082) + return MV_5082_DEV_ID; +#else +#if defined(MV_INCLUDE_PEX) + MV_U32 devId; + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Check pex power state */ + MV_U32 pexPower; + pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); + if (pexPower == MV_FALSE) + { + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); +/* mvPexPowerUp(0); */ + } +#endif + + devId = ((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_DEVICE_AND_VENDOR_ID)) + & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS); + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Return to power off state */ + if (pexPower == MV_FALSE) + { + mvPexPowerDown(0); + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); + } +#endif + + return devId; + +#elif defined(MV_INCLUDE_PCI) + MV_U32 pciData = 0; + MV_U32 dev = mvPciIfLocalDevNumGet(0); + MV_U32 bus = mvPciIfLocalBusNumGet(0); + + pciData = mvPciIfConfigRead(0, bus, dev, 0, PCI_DEVICE_AND_VENDOR_ID); + + return ((pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS); +#else + #error "No Way to get Device ID" +#endif +#endif /* MV_88F5082 */ +} +/******************************************************************************* +* mvCtrlRevGet - Get Marvell controller device revision number +* +* DESCRIPTION: +* This function returns 8bit describing the device revision as defined +* in PCI Express Class Code and Revision ID Register. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 8bit desscribing Marvell controller revision number +* +*******************************************************************************/ +MV_U8 mvCtrlRevGet(MV_VOID) +{ + MV_U8 revNum; +#if defined(MV_INCLUDE_PEX) +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Check pex power state */ + MV_U32 pexPower; + pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); +#endif + revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Return to power off state */ + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); +#endif +#elif defined(MV_INCLUDE_PCI) + MV_U32 dev = mvPciIfLocalDevNumGet(0); + MV_U32 bus = mvPciIfLocalBusNumGet(0); + + revNum = mvPciIfConfigRead(0, bus, dev, 0, PCI_CLASS_CODE_AND_REVISION_ID); +#endif +#if defined(MV_INCLUDE_PEX) || defined(MV_INCLUDE_PCI) + return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); +#else + #error "No Way to get Revision ID" +#endif +} + +/******************************************************************************* +* mvCtrlNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlNameGet(char *pNameBuff) +{ + mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, + mvCtrlModelGet(), mvCtrlRevGet()); + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision +* +* DESCRIPTION: +* This function returns 32bit value describing both Device ID and Revision +* as defined in PCI Express Device and Vendor ID Register and device revision +* as defined in PCI Express Class Code and Revision ID Register. + +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing both controller device ID and revision number +* +*******************************************************************************/ +MV_U32 mvCtrlModelRevGet(MV_VOID) +{ + return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); +} + +/******************************************************************************* +* mvCtrlNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ + +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) +{ + + switch (mvCtrlModelRevGet()) + { + case MV_5181_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5181_A0_NAME); + break; + case MV_5181_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5181_A1_NAME); + break; + case MV_5181_B0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5181_B0_NAME); + break; + case MV_5181_B1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5181_B1_NAME); + break; + case MV_5281_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5281_A0_NAME); + break; + case MV_5281_B0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5281_B0_NAME); + break; + case MV_5281_C0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5281_C0_NAME); + break; + case MV_5281_C1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5281_C1_NAME); + break; + case MV_5281_D0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5281_D0_NAME); + break; + case MV_5281_D1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5281_D1_NAME); + break; + case MV_5281_D2_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5281_D2_NAME); + break; + case MV_5082_A2_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5082_A2_NAME); + break; + case MV_5182_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5182_A0_NAME); + break; + case MV_5182_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5182_A1_NAME); + break; + case MV_5182_A2_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5182_A2_NAME); + break; + case MV_5181L_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5181L_A0_NAME); + break; + case MV_5181L_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_5181L_A1_NAME); + break; + case MV_8660_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_8660_A0_NAME); + break; + case MV_8660_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_8660_A1_NAME); + break; + case MV_1281_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_1281_A0_NAME); + break; + case MV_6183_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6183_A0_NAME); + break; + case MV_6183_1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6183_1_NAME); + break; + case MV_6183_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6183_A1_NAME); + break; + case MV_6183_B0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6183_B0_NAME); + break; + case MV_6183L_B0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6183L_B0_NAME); + break; + case MV_6082_A0_ID: + if( (MV_REG_READ(0x10018) & BIT3) == 0) + mvOsSPrintf (pNameBuff, "%s",MV_6082_A0_NAME); + else + mvOsSPrintf (pNameBuff, "%s",MV_6082L_A0_NAME); + break; + case MV_6082_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6082_A1_NAME); + break; + default: + mvCtrlNameGet(pNameBuff); + break; + } + + + return MV_OK; +} + +/******************************************************************************* +* ctrlWinOverlapTest - Test address windows for overlaping. +* +* DESCRIPTION: +* This function checks the given two address windows for overlaping. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* +* MV_TRUE if address window overlaps, MV_FALSE otherwise. +*******************************************************************************/ +MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + /* check if we have overflow than 4G*/ + if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| + ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) + { + return MV_TRUE; + } + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size-1; + winTop2 = winBase2 + pAddrWin2->size-1; + + + if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || + ((winBase1 <= winBase2) && (winBase2 <= winTop1))) + { + return MV_TRUE; + } + else + { + return MV_FALSE; + } +} + +/******************************************************************************* +* ctrlWinWithinWinTest - Test address windows for overlaping. +* +* DESCRIPTION: +* This function checks the given win1 boundries is within +* win2 boundries. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* +* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. +*******************************************************************************/ +MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size -1; + winTop2 = winBase2 + pAddrWin2->size -1; + + if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || + ((winTop1 >= winBase2) && (winTop1 <= winTop2))) + { + return MV_TRUE; + } + else + { + return MV_FALSE; + } +} + +static const char* cntrlName[] = TARGETS_NAME_ARRAY; + +/******************************************************************************* +* mvCtrlTargetNameGet - Get Marvell controller target name +* +* DESCRIPTION: +* This function convert the trget enumeration to string. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Target name (const MV_8 *) +*******************************************************************************/ +const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) +{ + + if (target >= MAX_TARGETS) + { + return "target unknown"; + } + + return cntrlName[target]; +} + +/******************************************************************************* +* mvCtrlAddrDecShow - Print the Controller units address decode map. +* +* DESCRIPTION: +* This function the Controller units address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCtrlAddrDecShow(MV_VOID) +{ + mvCpuIfAddDecShow(); + mvAhbToMbusAddDecShow(); +#if defined(MV_INCLUDE_PEX) + mvPexAddrDecShow(); +#endif +#if defined(MV_INCLUDE_PCI) + mvPciAddrDecShow(); +#endif +#if defined(MV_INCLUDE_IDMA) + mvDmaAddrDecShow(); +#endif +#if defined(MV_INCLUDE_USB) + mvUsbAddrDecShow(); +#endif +#if defined(MV_INCLUDE_GIG_ETH) + mvEthAddrDecShow(); +#endif +#if defined(MV_INCLUDE_XOR) + mvXorAddrDecShow(); +#endif +#if defined(MV_INCLUDE_SATA) + mvSataAddrDecShow(); +#endif +} + +/******************************************************************************* +* ctrlSizeToReg - Extract size value for register assignment. +* +* DESCRIPTION: +* Address decode size parameter must be programed from LSB to MSB as +* sequence of 1's followed by sequence of 0's. The number of 1's +* specifies the size of the window in 64 KB granularity (e.g. a +* value of 0x00ff specifies 256x64k = 16 MB). +* This function extract the size value from the size parameter according +* to given aligment paramter. For example for size 0x1000000 (16MB) and +* aligment 0x10000 (64KB) the function will return 0x00FF. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size register value correspond to size parameter. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) +{ + MV_U32 retVal; + + /* Check size parameter alignment */ + if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); + return -1; + } + + /* Take out the "alignment" portion out of the size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + /* and size is 0x1000000 (16MB) for example */ + while(alignment & 1) /* Check that alignmet LSB is set */ + { + size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ + alignment = (alignment >> 1); + } + + /* If after the alignment first '0' was met we still have '1' in */ + /* it then aligment is invalid (not power of 2) */ + if (alignment) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", + (MV_U32)alignment)); + return -1; + } + + /* Now the size is shifted right according to aligment: 0x0100 */ + size--; /* Now the size is a sequance of '1': 0x00ff */ + + retVal = size ; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + while(size & 1) /* Check that LSB is set */ + { + size = (size >> 1); /* If LSB is set, move one bit to the right */ + } + + if (size) /* Sequance of 1's is over. Check that we have no other 1's */ + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", + size)); + return -1; + } + + return retVal; + +} + +/******************************************************************************* +* ctrlRegToSize - Extract size value from register value. +* +* DESCRIPTION: +* This function extract a size value from the register size parameter +* according to given aligment paramter. For example for register size +* value 0xff and aligment 0x10000 the function will return 0x01000000. +* +* INPUT: +* regSize - Size as in register format. See ctrlSizeToReg. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) +{ + MV_U32 temp; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ + + while(temp & 1) /* Check that LSB is set */ + { + temp = (temp >> 1); /* If LSB is set, move one bit to the right */ + } + + if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ + { + DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", + regSize)); + return -1; + } + + + /* Check that aligment is a power of two */ + temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ + + while(temp & 1) /* Check that alignmet LSB is set */ + { + temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ + } + + /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ + /* then 'temp' is invalid (not power of 2) */ + if (temp) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", + alignment)); + return -1; + } + + regSize++; /* Now the size is 0x0100 */ + + /* Add in the "alignment" portion to the register size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + + while(alignment & 1) /* Check that alignmet LSB is set */ + { + regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ + alignment = (alignment >> 1); + } + + return regSize; +} + + +/******************************************************************************* +* ctrlSizeRegRoundUp - Round up given size +* +* DESCRIPTION: +* This function round up a given size to a size that fits the +* restrictions of size format given an aligment parameter. +* to given aligment paramter. For example for size parameter 0xa1000 and +* aligment 0x1000 the function will return 0xFF000. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size value correspond to size in register. +*******************************************************************************/ +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) +{ + MV_U32 msbBit = 0; + MV_U32 retSize; + + /* Check if size parameter is already comply with restriction */ + if (!(-1 == ctrlSizeToReg(size, alignment))) + { + return size; + } + + while(size) + { + size = (size >> 1); + msbBit++; + } + + retSize = (1 << msbBit); + + if (retSize < alignment) + { + return alignment; + } + else + { + return retSize; + } +} + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +/******************************************************************************* +* mvCtrlPwrClckSet - Set Power State for specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); + } + break; +#endif + default: + + break; + + } +} + +/******************************************************************************* +* mvCtrlPwrClckGet - Get Power State of specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); + MV_BOOL state = MV_TRUE; + + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (reg & PMC_PEXSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (reg & PMC_GESTOPCLOCK_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + if (reg & PMC_SATASTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (reg & PMC_SESTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (reg & PMC_USBSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif + default: + state = MV_TRUE; + break; + } + + + return state; +} +#else +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} +#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + +#if defined(MV_INCLUDE_INTEG_MFLASH) || defined (MV_INCLUDE_SPI) +/******************************************************************************* +* mvCtrlSpiBusModeSet - set the connectivity of the SPI bus +* +* DESCRIPTION: +* configure the MFlash controller to one of the 4 options +* +* INPUT: +* spiMode: SPI bus mode +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvCtrlSpiBusModeSet(MV_SPI_CONN_MODE spiMode) +{ +#if defined (MV_INCLUDE_INTEG_MFLASH) && defined (MV_INCLUDE_SPI) + + /* Read and clear the 3 bits related to the SPI mode */ + MV_U32 reg = (MV_REG_READ(MV_PMFLASH_IF_CFG_REG) & ~MV_PMFLASH_SPI_BUS_MODE_MASK); + + switch (spiMode) + { + case MV_SPI_CONN_TO_MFLASH: + reg |= MV_PMFLASH_SPI_BUS_TO_MFLASH; + break; + + case MV_SPI_CONN_TO_EXT_FLASH: + reg |= MV_PMFLASH_SPI_BUS_TO_EXT_SFLASH; + break; + + case MV_SPI_CONN_MFLASH_TO_EXT_PROG: + reg |= MV_PMFLASH_SPI_BUS_EXT_PROGRAMER; + break; + + default: + return MV_BAD_PARAM; + } + + /* write back the register with the updated 3 bits */ + MV_REG_WRITE(MV_PMFLASH_IF_CFG_REG, reg); +#endif + return MV_OK; +} + +/******************************************************************************* +* mvCtrlSpiBusModeDetect - Detect the configuration of the SPI interface in the +* hardware. +* +* DESCRIPTION: +* Detect the SPI connectivity. Whether the SPI is used to access the +* internal MFlash or to access an external device. +* +* INPUT: +* None +* +* OUTPUT: +* None +* +* RETURN: +* SPI mode +* +* +*******************************************************************************/ +MV_SPI_CONN_MODE mvCtrlSpiBusModeDetect(void) +{ +#if defined (MV_INCLUDE_INTEG_MFLASH) && defined (MV_INCLUDE_SPI) + /* Read the regiater and mask away all bits except the 3 relevant bits */ + MV_U32 reg = (MV_REG_READ(MV_PMFLASH_IF_CFG_REG) & MV_PMFLASH_SPI_BUS_MODE_MASK); + + /* check all possibilities */ + switch (reg) + { + case MV_PMFLASH_SPI_BUS_TO_MFLASH: + return MV_SPI_CONN_TO_MFLASH; + + case MV_PMFLASH_SPI_BUS_TO_EXT_SFLASH: + return MV_SPI_CONN_TO_EXT_FLASH; + + case MV_PMFLASH_SPI_BUS_EXT_PROGRAMER: + return MV_SPI_CONN_MFLASH_TO_EXT_PROG; + } + + return MV_SPI_CONN_UNKNOWN; +#elif defined (MV_INCLUDE_SPI) + return MV_SPI_CONN_TO_EXT_FLASH; +#else + return MV_SPI_CONN_UNKNOWN; +#endif +} +#endif /* #if defined (MV_INCLUDE_INTEG_MFLASH) */ + +/******************************************************************************* +* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_VOID mvMPPConfigToSPI(MV_VOID) +{ + return; +} + + +/******************************************************************************* +* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_VOID mvMPPConfigToDefault(MV_VOID) +{ + return; +} + + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvLib.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvLib.h new file mode 100644 index 0000000..be465b8 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvLib.h @@ -0,0 +1,184 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvLibh +#define __INCmvCtrlEnvLibh + +/* includes */ +#include "mvCommon.h" +#include "mvTypes.h" +#include "mvOs.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + + +/* typedefs */ + +/* This enumerator describes the possible HW cache coherency policies the */ +/* controllers supports. */ +typedef enum _mvCachePolicy +{ + NO_COHERENCY, /* No HW cache coherency support */ + WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ + WB_COHERENCY /* HW cache coherency supported in Write Back policy */ +}MV_CACHE_POLICY; + + +/* The swapping is referred to a 64-bit words (as this is the controller */ +/* internal data path width). This enumerator describes the possible */ +/* data swap types. Below is an example of the data 0x0011223344556677 */ +typedef enum _mvSwapType +{ + MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ + MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ + MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ + MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ + SWAP_TYPE_MAX /* Delimiter for this enumerator */ +}MV_SWAP_TYPE; + +/* This structure describes access rights for Access protection windows */ +/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ +/* Note that the permission enumerator coresponds to its register format. */ +/* For example, Read only premission is presented as "1" in register field. */ +typedef enum _mvAccessRights +{ + NO_ACCESS_ALLOWED = 0, /* No access allowed */ + READ_ONLY = 1, /* Read only permission */ + ACC_RESERVED = 2, /* Reserved access right */ + FULL_ACCESS = 3, /* Read and Write permission */ + MAX_ACC_RIGHTS +}MV_ACCESS_RIGHTS; + +#if (defined (MV_INCLUDE_SPI) || defined (MV_INCLUDE_INTEG_MFLASH)) +typedef enum +{ + MV_SPI_CONN_UNKNOWN, /* Unknown SPI mode */ + MV_SPI_CONN_TO_MFLASH, /* spi is connected to the integrated MFlash */ + MV_SPI_CONN_TO_EXT_FLASH, /* SPI is connected to an external serial flash */ + MV_SPI_CONN_MFLASH_TO_EXT_PROG, /* SPI pins are input to the MFlash - external SPI programmer is connected */ + MV_SPI_CONN_TRI_STATE /* SPI pins are tri-stated - external flash is managed externally */ +}MV_SPI_CONN_MODE; +#endif + + +/* mcspLib.h API list */ + +MV_STATUS mvCtrlEnvInit(MV_VOID); +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); + +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCtrlPciMaxIfGet(MV_VOID); +#else +#define mvCtrlPciMaxIfGet() (0) +#endif +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCtrlPexMaxIfGet(MV_VOID); +#else +#define mvCtrlPexMaxIfGet() (0) +#endif +#if defined(MV_INCLUDE_PCI) || defined(MV_INCLUDE_PEX) +MV_U32 mvCtrlPciIfMaxIfGet(MV_VOID); +#else +#define mvCtrlPciIfMaxIfGet() (0) +#endif +#if defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) +MV_U32 mvCtrlEthMaxPortGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_IDMA) +MV_U32 mvCtrlIdmaMaxChanGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_USB) +MV_U32 mvCtrlUsbMaxGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_NAND) +MV_U32 mvCtrlNandSupport(MV_VOID); +#endif +MV_U16 mvCtrlModelGet(MV_VOID); +MV_U8 mvCtrlRevGet(MV_VOID); +MV_STATUS mvCtrlNameGet(char *pNameBuff); +MV_U32 mvCtrlModelRevGet(MV_VOID); +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); +MV_VOID mvCtrlAddrDecShow(MV_VOID); +const MV_8* mvCtrlTargetNameGet(MV_TARGET target); +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); +MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); +MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); + +#if (defined (MV_INCLUDE_SPI) || defined (MV_INCLUDE_INTEG_MFLASH)) +/* Set and Detect the SPI mode configuration inside the MFlash controller */ +MV_STATUS mvCtrlSpiBusModeSet (MV_SPI_CONN_MODE spiMode); +MV_SPI_CONN_MODE mvCtrlSpiBusModeDetect (void); +#endif + +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); + +MV_VOID mvMPPConfigToSPI(MV_VOID); +MV_VOID mvMPPConfigToDefault(MV_VOID); + +#endif /* __INCmvCtrlEnvLibh */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvPadCalibration.c b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvPadCalibration.c new file mode 100644 index 0000000..5bb0245 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvPadCalibration.c @@ -0,0 +1,463 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ddr1_2/mvDramIfRegs.h" +#include "eth/mvEth.h" +#include "ctrlEnv/mvCtrlEnvPadCalibration.h" + +#define ENABLE_ETHERNET_PAD_CALIBRATION +#undef DEBUG_ETHERNET_PAD_CALIBRATION + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +#define MAX_LockN 31 +#define R_NA 0 + + +/* Local */ + +static MV_CTRL_ENV_DEVICE_PROCESS_TYPE deviceProcessType2_5V[MAX_LockN+1]={ +{ R_NA, R_NA, R_NA }, /* LockN = 0 */ +{ R_NA, R_NA, R_NA }, /* LockN = 1 */ +{ R_NA, R_NA, R_NA }, /* LockN = 2 */ +{ R_NA, R_NA, R_NA }, /* LockN = 3 */ +{ R_NA, R_NA, R_NA }, /* LockN = 4 */ +{ R_NA, R_NA, 5447 }, /* LockN = 5 */ +{ R_NA, R_NA, 4539 }, /* LockN = 6 */ +{ 5295, R_NA, 3890 }, /* LockN = 7 */ +{ 4633, R_NA, 3404 }, /* LockN = 8 */ +{ 4118, R_NA, 3026 }, /* LockN = 9 */ +{ 3706, 5338, 2723 }, /* LockN = 10 */ +{ 3369, 4853, 2476 }, /* LockN = 11 */ +{ 3089, 4448, 2269 }, /* LockN = 12 */ +{ 2851, 4106, 2095 }, /* LockN = 13 */ +{ 2647, 3813, R_NA }, /* LockN = 14 */ +{ 2471, 3559, R_NA }, /* LockN = 15 */ +{ 2317, 3336, R_NA }, /* LockN = 16 */ +{ 2180, 3140, R_NA }, /* LockN = 17 */ +{ 2059, 2966, R_NA }, /* LockN = 18 */ +{ R_NA, 2810, -1 }, /* LockN = 19 */ +{ R_NA, 2669, -1 }, /* LockN = 20 */ +{ R_NA, 2542, -1 }, /* LockN = 21 */ +{ R_NA, 2426, -1 }, /* LockN = 22 */ +{ R_NA, 2321, -1 }, /* LockN = 23 */ +{ R_NA, 2224, -1 }, /* LockN = 24 */ +{ R_NA, 2135, -1 }, /* LockN = 25 */ +{ R_NA, R_NA, R_NA }, /* LockN = 26 */ +{ R_NA, R_NA, R_NA }, /* LockN = 27 */ +{ R_NA, R_NA, R_NA }, /* LockN = 28 */ +{ R_NA, R_NA, R_NA }, /* LockN = 29 */ +{ R_NA, R_NA, R_NA }, /* LockN = 30 */ +{ R_NA, R_NA, R_NA }, /* LockN = 31 */ +}; + +static MV_CTRL_ENV_DEVICE_PROCESS_TYPE deviceProcessType1_8V[MAX_LockN+1]={ +{ R_NA, R_NA, R_NA }, /* LockN = 0 */ +{ R_NA, R_NA, R_NA }, /* LockN = 1 */ +{ R_NA, R_NA, R_NA }, /* LockN = 2 */ +{ R_NA, R_NA, R_NA }, /* LockN = 3 */ +{ R_NA, R_NA, R_NA }, /* LockN = 4 */ +{ R_NA, R_NA, R_NA }, /* LockN = 5 */ +{ R_NA, R_NA, 5617 }, /* LockN = 6 */ +{ R_NA, R_NA, 4815 }, /* LockN = 7 */ +{ R_NA, R_NA, 4213 }, /* LockN = 8 */ +{ 5564, R_NA, 3745 }, /* LockN = 9 */ +{ 5008, R_NA, 3370 }, /* LockN = 10 */ +{ 4553, R_NA, 3064 }, /* LockN = 11 */ +{ 4173, R_NA, 2808 }, /* LockN = 12 */ +{ 3852, R_NA, 2592 }, /* LockN = 13 */ +{ 3577, 5699, 2407 }, /* LockN = 14 */ +{ 3339, 5319, 2247 }, /* LockN = 15 */ +{ 3130, 4987, 2106 }, /* LockN = 16 */ +{ 2946, 4693, R_NA }, /* LockN = 17 */ +{ 2782, 4432, R_NA }, /* LockN = 18 */ +{ 2636, 4199, -1 }, /* LockN = 19 */ +{ 2504, 3989, -1 }, /* LockN = 20 */ +{ 2385, 3799, -1 }, /* LockN = 21 */ +{ 2276, 3627, -1 }, /* LockN = 22 */ +{ 2177, 3469, -1 }, /* LockN = 23 */ +{ R_NA, 3324, -1 }, /* LockN = 24 */ +{ R_NA, 3191, -1 }, /* LockN = 25 */ +{ R_NA, 3069, R_NA }, /* LockN = 26 */ +{ R_NA, 2955, R_NA }, /* LockN = 27 */ +{ R_NA, 2849, R_NA }, /* LockN = 28 */ +{ R_NA, 2751, R_NA }, /* LockN = 29 */ +{ R_NA, 2659, R_NA }, /* LockN = 30 */ +{ R_NA, 2574, R_NA }, /* LockN = 31 */ +}; + + +static MV_CTRL_ENV_ETHERNET_PAD_CALIBRATION EthPadCalibrationTableHSTL_1_8V[]={ +{11,12}, /* type 1 */ +{18,20}, /* type 2 */ +{ 7, 8} /* type 3 */ +}; + +static MV_CTRL_ENV_ETHERNET_PAD_CALIBRATION EthPadCalibrationTable3_3V[]={ +{ 8, 9}, /* type 1 */ +{13,13}, /* type 2 */ +{ 6, 6} /* type 3 */ +}; + +static MV_CTRL_ENV_ETHERNET_PAD_CALIBRATION EthPadCalibrationTable2_5V[]={ /* Marvel RD board */ +{ 7, 7}, /* type 1 */ +{11,11}, /* type 2 */ +{ 5, 5} /* type 3 */ +}; + + + +int CpuPadCalibrationV = MV_CTRL_ENV_CPU_INTERFACE_VOLTAGE_1_8V; +int EthInterfaceDrivingStrength = MV_CTRL_ENV_INTERFACE_DRIVING_STRENGTH_2_5V; + +static void ctrlEnvEthPadCalibrationSet(int port,MV_U32 drvN, MV_U32 drvP); +static MV_STATUS ctrlEnvCalculatePadCalibration(MV_U32 *pdrvN, MV_U32 *pdrvP); + +/******************************************************************************* +* mvCtrlEnvPadCalibrationInit - Initialize the Ethernet Pad Calibration Value +* +* DESCRIPTION: +* This function is Initialize the Ethernet Pad Calibration +* +* INPUT: +* Non +* OUTPUT: +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvCtrlEnvPadCalibrationInit(void) +{ + int port; + MV_U32 drvN,drvP; + + if (MV_ERROR == ctrlEnvCalculatePadCalibration (&drvN, &drvP)) + return; + + /* Init static data structures */ + for (port=0; port>SDRAM_LOCKN_OFFS; +#ifdef DEBUG_ETHERNET_PAD_CALIBRATION + mvOsPrintf("CPU PadCalibration: LockN = 0x%X\n", LockN); +#endif + + if ((LockN < 0) || (LockN>MAX_LockN)) + { + return MV_ERROR; + } + if (CpuPadCalibrationV == MV_CTRL_ENV_CPU_INTERFACE_VOLTAGE_1_8V) + { + type1 = deviceProcessType1_8V[LockN].ResistorType1; + type2 = deviceProcessType1_8V[LockN].ResistorType2; + type3 = deviceProcessType1_8V[LockN].ResistorType3; + } + else + { + type1 = deviceProcessType2_5V[LockN].ResistorType1; + type2 = deviceProcessType2_5V[LockN].ResistorType2; + type3 = deviceProcessType2_5V[LockN].ResistorType3; + } + if ((type1 == R_NA) && (type2 == R_NA) && (type3 == R_NA)) /* all the types out of range? */ + { + return MV_ERROR; + } + /* find the lower diffrent type and Resitor */ + Difftype1 = (type1 > MV_CTRL_ENV_CPU_PAD_CALIBRATION_RESISTOR)? + type1 - MV_CTRL_ENV_CPU_PAD_CALIBRATION_RESISTOR:MV_CTRL_ENV_CPU_PAD_CALIBRATION_RESISTOR - type1; + Difftype2 = (type2 > MV_CTRL_ENV_CPU_PAD_CALIBRATION_RESISTOR)? + type2 - MV_CTRL_ENV_CPU_PAD_CALIBRATION_RESISTOR:MV_CTRL_ENV_CPU_PAD_CALIBRATION_RESISTOR - type2; + Difftype3 = (type3 > MV_CTRL_ENV_CPU_PAD_CALIBRATION_RESISTOR)? + type3 - MV_CTRL_ENV_CPU_PAD_CALIBRATION_RESISTOR:MV_CTRL_ENV_CPU_PAD_CALIBRATION_RESISTOR - type3; +#ifdef DEBUG_ETHERNET_PAD_CALIBRATION + mvOsPrintf("Ethernet Pad Calibration: type1=%d, type2=%d, type3=%d Diff1=%d, Diff2=%d, Diff3=%d \n", + type1,type2,type3,Difftype1,Difftype2,Difftype3); +#endif + /* find the minimum from Difftype1, Difftype2 and Difftype3 */ + if (Difftype1 <= Difftype2) + { + if (Difftype1 <= Difftype3) + { + SelectedType = MV_CTRL_ENV_DEVICE_PROCESS_TYPE1; + } + else + { + SelectedType = MV_CTRL_ENV_DEVICE_PROCESS_TYPE3; + + } + } + else + { + if (Difftype2 <= Difftype3) + { + SelectedType = MV_CTRL_ENV_DEVICE_PROCESS_TYPE2; + } + else + { + SelectedType = MV_CTRL_ENV_DEVICE_PROCESS_TYPE3; + + } + } + + /* load the correct drvN and drvP from the selected type table. */ + if (EthInterfaceDrivingStrength == MV_CTRL_ENV_INTERFACE_DRIVING_STRENGTH_HSTL_1_8V) + { + *pdrvN = EthPadCalibrationTableHSTL_1_8V[SelectedType].padCalibrationDrvN; + *pdrvP = EthPadCalibrationTableHSTL_1_8V[SelectedType].padCalibrationDrvP; + } + if (EthInterfaceDrivingStrength == MV_CTRL_ENV_INTERFACE_DRIVING_STRENGTH_3_3V) + { + *pdrvN = EthPadCalibrationTable3_3V[SelectedType].padCalibrationDrvN; + *pdrvP = EthPadCalibrationTable3_3V[SelectedType].padCalibrationDrvP; + } + if (EthInterfaceDrivingStrength == MV_CTRL_ENV_INTERFACE_DRIVING_STRENGTH_2_5V) + { + *pdrvN = EthPadCalibrationTable2_5V[SelectedType].padCalibrationDrvN; + *pdrvP = EthPadCalibrationTable2_5V[SelectedType].padCalibrationDrvP; + } + +#ifdef DEBUG_ETHERNET_PAD_CALIBRATION + mvOsPrintf("mvEthPadCalibration: SelectedType=%d, drvN=0x%X,drvP=0x%X, \n", + SelectedType+1,*pdrvN,*pdrvP); +#endif + return MV_OK; +#endif +} + + +/******************************************************************************* +* mvCtrlEnvEthInterfaceDrivingStrengthSet +* +* DESCRIPTION: +* This function set the interface driving strength voltage +* +* INPUT: +* None +* +* OUTPUT: +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvCtrlEnvEthInterfaceDrivingStrengthSet(int Value) +{ + if (Value >MV_CTRL_ENV_INTERFACE_DRIVING_STRENGTH_MAX) + { + return; + } + EthInterfaceDrivingStrength = Value; +} +/******************************************************************************* +* mvCtrlEnvEthInterfaceDrivingStrengthGet +* +* DESCRIPTION: +* This function replay the interface driving strength voltage +* +* INPUT: +* None +* +* OUTPUT: +* +* RETURN: +* the interface driving strength voltage +* +*******************************************************************************/ +int mvCtrlEnvEthInterfaceDrivingStrengthGet(void) +{ + return EthInterfaceDrivingStrength; +} + +/******************************************************************************* +* mvCtrlEnvEthCpuPadCalibrationVoltSet +* +* DESCRIPTION: +* This function set the ethernet cpu pad calibration voltage +* +* INPUT: +* None +* +* OUTPUT: +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvCtrlEnvEthCpuPadCalibrationVoltSet(int Value) +{ + if (Value >MV_CTRL_ENV_CPU_INTERFACE_VOLTAGE_MAX) + { + return; + } + CpuPadCalibrationV = Value; +} +/******************************************************************************* +* mvCtrlEnvEthCpuPadCalibrationVoltGet +* +* DESCRIPTION: +* This function replay the CPU pad calibration voltage +* +* INPUT: +* None +* +* OUTPUT: +* +* RETURN: +* ethernet cpu pad calibration voltage +* +*******************************************************************************/ +int mvCtrlEnvEthCpuPadCalibrationVoltGet(void) +{ + return CpuPadCalibrationV; +} + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvPadCalibration.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvPadCalibration.h new file mode 100644 index 0000000..fed094e --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvPadCalibration.h @@ -0,0 +1,162 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/****************************************************************************** +* mvcltrlEnvPadCalibration.h - Header File for : MV-MV64560 Setting the Ethernet * +* Pad Calibration Value * +* * +* DESCRIPTION: * +* This header file contains macros typedefs and the ethernet pad * +* calibration Value tables * +* * +* DEPENDENCIES: * +* None. * +* * +*******************************************************************************/ + +#ifndef __mvCtrlEnvEthPad_Calibration_h__ +#define __mvCtrlEnvEthPad_Calibration_h__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ + +/* defines */ +/* CPU interface voltage in use. */ + +typedef enum __mvethcpuinterfacevoltage__ +{ + MV_CTRL_ENV_CPU_INTERFACE_VOLTAGE_1_8V, + MV_CTRL_ENV_CPU_INTERFACE_VOLTAGE_2_5, + +}MV_CTRL_ENV_CPU_VOLTAGE; + +#define MV_ETH_CPU_INTERFACE_VOLTAGE MV_CTRL_ENV_CPU_INTERFACE_VOLTAGE_1_8V +#define MV_CTRL_ENV_CPU_INTERFACE_VOLTAGE_MAX MV_CTRL_ENV_CPU_INTERFACE_VOLTAGE_2_5 + + +/* The Ethernet interface driving strength (Table 33 in Doc. No. MV-S300848-00, Rev. A) */ +#undef MV_CTRL_ENV_ETHERNET_INTERFACE_DRIVING_STRENGTH_HSTL_1_8V +#undef MV_CTRL_ENV_ETHERNET_INTERFACE_DRIVING_STRENGTH_3_3V +#define MV_CTRL_ENV_ETHERNET_INTERFACE_DRIVING_STRENGTH_2_5V /* Marvel RD board */ + +typedef enum __mvCtrlEnvInterface_driving_strengthvoltage__ +{ + MV_CTRL_ENV_INTERFACE_DRIVING_STRENGTH_HSTL_1_8V, + MV_CTRL_ENV_INTERFACE_DRIVING_STRENGTH_3_3V, + MV_CTRL_ENV_INTERFACE_DRIVING_STRENGTH_2_5V /* Marvel RD board */ +}MV_ETH_DRIVING_STRENGTH_VOLTAGE_ENUM; + +#define MV_CTRL_ENV_INTERFACE_DRIVING_STRENGTH_MAX MV_CTRL_ENV_INTERFACE_DRIVING_STRENGTH_2_5V + +#define MV_CTRL_ENV_DRIVING_STRENGTH_VOLTAGE MV_CTRL_ENV_INTERFACE_DRIVING_STRENGTH_2_5V + +#define MV_CTRL_ENV_CPU_PAD_CALIBRATION_RESISTOR (50*100) /* 50ohm is for single CPU */ + +/* CPU INTERFACE VOLTAGE */ +typedef struct _mvEthDeviceProcessType +{ + int ResistorType1; + int ResistorType2; + int ResistorType3; +} MV_CTRL_ENV_DEVICE_PROCESS_TYPE; + + +/* The Ethernet interface driving strength table */ + +typedef struct _EthernetPadCalibration +{ + int padCalibrationDrvN; + int padCalibrationDrvP; +} MV_CTRL_ENV_ETHERNET_PAD_CALIBRATION; + + +typedef enum __mvethEthernetPadCalibrationType_ +{ + MV_CTRL_ENV_DEVICE_PROCESS_TYPE1, + MV_CTRL_ENV_DEVICE_PROCESS_TYPE2, + MV_CTRL_ENV_DEVICE_PROCESS_TYPE3, + +}MV_CTRL_ENV_ETHERNET_PAD_CALIBRATION_TYPE; + + +/* function */ + +void mvCtrlEnvPadCalibrationInit(void); +void mvCtrlEnvEthInterfaceDrivingStrengthSet(int Value); +int mvCtrlEnvEthInterfaceDrivingStrengthGet(void); +void mvCtrlEnvEthCpuPadCalibrationVoltSet(int Value); +int mvCtrlEnvEthCpuPadCalibrationVoltGet(void); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __mvCtrlEnvEthPad_Calibration_h__ */ + + + + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvSpec.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvSpec.h new file mode 100644 index 0000000..0f4632d --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/mvCtrlEnvSpec.h @@ -0,0 +1,263 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvSpech +#define __INCmvCtrlEnvSpech + +#include "mvDeviceId.h" +#include "mvSysHwConfig.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ + + +/* defines */ +/* This define describes the TWSI interrupt bit and location */ +#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 +#define TWSI0_CPU_MAIN_INT_BIT 0x20 + +#define MV_BOARD_RTC_I2C_CHANNEL 0 +#define MV_BOARD_DIMM_I2C_CHANNEL 0 + +/*#define TDM_REG_BASE 0xD0000 */ +/*#define USB_REG_BASE(dev) 0x50000 */ +/*#define AUDIO_REG_BASE 0xA0000 */ +/*#define SATA_REG_BASE 0x80000 */ +/*#define MV_CESA_REG_BASE 0x3D000 */ +/*#define MV_CESA_TDMA_REG_BASE 0x30000 */ +/*#define MV_SDIO_REG_BASE 0x90000 */ +/*#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) */ +/*#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) */ + +#define DRAM_BASE 0x0 +#define CNTMR_BASE 0x20300 +#define TWSI_SLAVE_BASE(chanNum) 0x11000 +#define PEX_IF_BASE(pexIf) 0x40000 +#define IDMA_UNIT_BASE 0x60800 + +/* 0x5181 revisions*/ +#define MV_5181_A0_REV 0x0 +#define MV_5181_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181_A0_REV) +#define MV_5181_A0_NAME "88F5181 A0" +#define MV_5181_A1_REV 0x1 +#define MV_5181_A1_ID ((MV_5181_DEV_ID << 16) | MV_5181_A1_REV) +#define MV_5181_A1_NAME "88F5181 A1" +#define MV_5181_B0_REV 0x2 +#define MV_5181_B0_ID ((MV_5181_DEV_ID << 16) | MV_5181_B0_REV) +#define MV_5181_B0_NAME "88F5181 B0" +#define MV_5181_B1_REV 0x3 +#define MV_5181_B1_ID ((MV_5181_DEV_ID << 16) | MV_5181_B1_REV) +#define MV_5181_B1_NAME "88F5181 B1" +/* 0x5281 revisions*/ +#define MV_5281_A0_REV 0x0 +#define MV_5281_A0_ID ((MV_5281_DEV_ID << 16) | MV_5281_A0_REV) +#define MV_5281_A0_NAME "88F5281 A0" +#define MV_5281_B0_REV 0x1 +#define MV_5281_B0_ID ((MV_5281_DEV_ID << 16) | MV_5281_B0_REV) +#define MV_5281_B0_NAME "88F5281 B0" +#define MV_5281_C0_REV 0x2 +#define MV_5281_C0_ID ((MV_5281_DEV_ID << 16) | MV_5281_C0_REV) +#define MV_5281_C0_NAME "88F5281 C0" +#define MV_5281_C1_REV 0x3 +#define MV_5281_C1_ID ((MV_5281_DEV_ID << 16) | MV_5281_C1_REV) +#define MV_5281_C1_NAME "88F5281 C1" +#define MV_5281_D0_REV 0x4 +#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) +#define MV_5281_D0_NAME "88F5281 D0" +#define MV_5281_D1_REV 0x5 +#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) +#define MV_5281_D1_NAME "88F5281 D1" +#define MV_5281_D2_REV 0x6 +#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) +#define MV_5281_D2_NAME "88F5281 D2" +/* 0x5182 revisions*/ +#define MV_5182_A0_REV 0x0 +#define MV_5182_A0_ID ((MV_5182_DEV_ID << 16) | MV_5182_A0_REV) +#define MV_5182_A0_NAME "88F5182 A0" +#define MV_5182_A1_REV 0x1 +#define MV_5182_A1_ID ((MV_5182_DEV_ID << 16) | MV_5182_A1_REV) +#define MV_5182_A1_NAME "88F5182 A1" +#define MV_5182_A2_REV 0x2 +#define MV_5182_A2_ID ((MV_5182_DEV_ID << 16) | MV_5182_A2_REV) +#define MV_5182_A2_NAME "88F5182 A2" +/* 0x5181L revisions*/ +#define MV_5181L_A0_REV 0x8 +#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) +#define MV_5181L_A0_NAME "88F5181L A0" +#define MV_5181L_A1_REV 0x9 +#define MV_5181L_A1_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A1_REV) +#define MV_5181L_A1_NAME "88F5181L A1" + +/* 0x8660 revisions */ +#define MV_8660_A0_REV 0x0 +#define MV_8660_A0_ID ((MV_8660_DEV_ID << 16) | MV_8660_A0_REV) +#define MV_8660_A0_NAME "88W8660 A0" +#define MV_8660_A1_REV 0x1 +#define MV_8660_A1_ID ((MV_8660_DEV_ID << 16) | MV_8660_A1_REV) +#define MV_8660_A1_NAME "88W8660 A1" + +/* 0x5180N revisions */ +#define MV_5180N_B1_REV 0x3 +#define MV_5180N_B1_ID ((MV_5180_DEV_ID << 16) | MV_5180N_B1_REV) +#define MV_5180N_B1_NAME "88F5180N B1" + +/* 0x5082 revisions*/ +#define MV_5082_A2_REV 0x2 +#define MV_5082_A2_ID ((MV_5082_DEV_ID << 16) | MV_5082_A2_REV) +#define MV_5082_A2_NAME "88F5082 A2" + +/* 0x1282 revisions*/ +#define MV_1281_A0_REV 0x0 +#define MV_1281_A0_ID ((MV_1281_DEV_ID << 16) | MV_1281_A0_REV) +#define MV_1281_A0_NAME "88F1281 A0" + +/* 0x6082 revisions*/ +#define MV_6082_A0_REV 0x0 +#define MV_6082_A0_ID ((MV_6082_DEV_ID << 16) | MV_6082_A0_REV) +#define MV_6082_A0_NAME "88F6082 A0" +#define MV_6082L_A0_NAME "88F6082L A0" +#define MV_6082_A1_REV 0x1 +#define MV_6082_A1_ID ((MV_6082_DEV_ID << 16) | MV_6082_A1_REV) +#define MV_6082_A1_NAME "88F6082 A1" + +/* 0x6183 revisions*/ +#define MV_6183_A0_REV 0x0 +#define MV_6183_A0_ID ((MV_6183_DEV_ID << 16) | MV_6183_A0_REV) +#define MV_6183_A0_NAME "88F6183 A0" +#define MV_6183_1_REV 0x1 +#define MV_6183_1_ID ((MV_6183_DEV_ID << 16) | MV_6183_1_REV) +#define MV_6183_1_NAME "88F6183 1" +#define MV_6183_A1_REV 0x2 +#define MV_6183_A1_ID ((MV_6183_DEV_ID << 16) | MV_6183_A1_REV) +#define MV_6183_A1_NAME "88F6183 A1" +#define MV_6183_B0_REV 0x3 +#define MV_6183_B0_ID ((MV_6183_DEV_ID << 16) | MV_6183_B0_REV) +#define MV_6183_B0_NAME "88F6183 B0" + +/* 0x6183L revisions*/ +#define MV_6183L_B0_REV 0x3 +#define MV_6183L_B0_ID ((MV_6183L_DEV_ID << 16) | MV_6183L_B0_REV) +#define MV_6183L_B0_NAME "88F6183L B0" + +#define XOR_UNIT_BASE(unit) 0x60900 +#define MV_XOR_MAX_UNIT 1 +#define MV_XOR_MAX_CHAN 2 /* totol channels for all units together*/ +#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ + + + +#if defined(MV_88F1181) +#include "mv88F1X81EnvSpec.h" +#elif defined(MV_88F1281) +#include "mv88F1281EnvSpec.h" +#elif defined(MV_88F5182) +#include "mv88F5182EnvSpec.h" +#elif defined(MV_88F5082) +#include "mv88F5082EnvSpec.h" +#elif defined(MV_88F5181L) +#include "mv88F5181LEnvSpec.h" +#elif defined(MV_88W8660) +#include "mv88w8660EnvSpec.h" +#elif defined(MV_88F5181) +#include "mv88F5X81EnvSpec.h" +#elif defined(MV_88F5180N) +#include "mv88F5180NEnvSpec.h" +#elif defined(MV_88F6082) +#include "mv88F6082EnvSpec.h" +#elif defined(MV_88F6183) +#include "mv88F6183EnvSpec.h" +#elif defined(MV_88F6183L) +#include "mv88F6183LEnvSpec.h" +#else +#error "No Soc defined" +#endif + +#ifndef MV_ASMLANGUAGE + +/* This enumerator defines the Marvell Units ID */ +typedef enum _mvUnitId +{ + DRAM_UNIT_ID, + PEX_UNIT_ID, + PCI_UNIT_ID, + ETH_GIG_UNIT_ID, + ETH_UNM_UNIT_ID, + USB_UNIT_ID, + IDMA_UNIT_ID, + XOR_UNIT_ID, + SATA_UNIT_ID, + TDM_UNIT_ID, + UART_UNIT_ID, + CESA_UNIT_ID, + SPI_UNIT_ID, + AUDIO_UNIT_ID, + MAX_UNITS_ID, + +}MV_UNIT_ID; + +#endif +#endif /* __INCmvCtrlEnvSpech */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbus.c b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbus.c new file mode 100644 index 0000000..759dfdb --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbus.c @@ -0,0 +1,1051 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ctrlEnv/sys/mvAhbToMbusConfig.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#undef MV_DEBUG +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* typedefs */ + + +/* CPU address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _ahbToMbusRemapRegOffs +{ + MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ + MV_U32 highRegOffs; /* High 32 bit remap register offset */ +}AHB_TO_MBUS_REMAP_REG_OFFS; + +/* locals */ +static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, + AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); + +/******************************************************************************* +* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK laways. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusInit(void) +{ + return MV_OK; + +} + +/******************************************************************************* +* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* This function sets +* address window, also known as address decode window. +* A new address decode window is set for specified winNum address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the winNum window, allowing CPU to access +* the winNum window. +* +* INPUT: +* winNum - Windows number. +* pAddrDecWin - CPU winNum window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU winNum window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttribs; + MV_DEC_REGS decRegs; + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + + /* read base register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + } + else + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read control register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + } + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + /* enable\Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + decRegs.sizeReg |= ATMWCR_WIN_ENABLE; + } + else + { + decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; + decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; + decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; + +#if !defined(MV_RUN_FROM_FLASH) + /* To be on the safe side we disable the window before writing the */ + /* new values. */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + mvAhbToMbusWinEnable(winNum,MV_FALSE); + } +#endif + + /* 3) Write to address decode Base Address Register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); + } + else + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); + } + + + /* Internal register space have no size */ + /* register. Do not perform size register assigment for those targets */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + /* Write to address decode Size Register */ + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* Get the CPU peripheral winNum address window. +* +* INPUT: +* winNum - Peripheral winNum enumerator +* +* OUTPUT: +* pAddrDecWin - CPU winNum window information data structure. +* +* RETURN: +* MV_OK if winNum exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + + /* Internal register space size have no size register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + } + else + { + decRegs.sizeReg = 0; + } + + + /* Read base and size */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + } + else + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); + } + + + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + { + pAddrDecWin->addrWin.size = INTER_REGS_SIZE; + pAddrDecWin->target = INTER_REGS; + pAddrDecWin->enable = MV_TRUE; + + return MV_OK; + } + + + if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + + } + + + + if (-1 == pAddrDecWin->addrWin.size) + { + return MV_ERROR; + } + + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> + ATMWCR_WIN_ATTR_OFFS; + targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> + ATMWCR_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + if (INTER_REGS == target) + { + return MV_AHB_TO_MBUS_INTREG_WIN; + } + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) + { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + + } + + if (decWin.enable == MV_TRUE) + { + if (decWin.target == target) + { + return winNum; + } + + } + + } + + return 0xFFFFFFFF; + + +} + +/******************************************************************************* +* mvAhbToMbusWinAvailGet - Get First Available window number. +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) + { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + + } + + if (decWin.enable == MV_FALSE) + { + return winNum; + } + + } + + return 0xFFFFFFFF; +} + + +/******************************************************************************* +* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Peripheral winNum enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other winNum window. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) +{ + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal registers bar can't be disable or enabled */ + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + { + return (enable ? MV_OK : MV_ERROR); + } + + if (enable == MV_TRUE) + { + /* enable the window */ + MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvAhbToMbusWinRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* After a CPU address hits one of PCI address decode windows there is an +* option to remap the address to a different one. For example, CPU +* executes a read from PCI winNum window address 0x1200.0000. This +* can be modified so the address on the PCI bus would be 0x1400.0000 +* Using the PCI address remap mechanism. +* +* INPUT: +* winNum - Peripheral winNum enumerator. Must be a PCI winNum. +* pAddrDecWin - CPU winNum window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddr; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; + + MV_U32 effectiveBaseAddress=0, + baseAddrValue=0,windowSizeValue=0; + + + /* Get registers offsets of given winNum */ + if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) + { + return 0xffffffff; + } + + /* 1) Set address remap low */ + baseAddr = pAddrWin->baseLow; + + /* Check base address aligment */ + /* + if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) + { + mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", + baseAddr); + return MV_ERROR; + } + */ + + /* BaseLow[31:16] => base register [31:16] */ + baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; + + MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); + + MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); + + + baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + + baseAddrValue &= ATMWBR_BASE_MASK; + windowSizeValue &=ATMWCR_WIN_SIZE_MASK; + + /* Start calculating the effective Base Address */ + effectiveBaseAddress = baseAddrValue ; + + /* The effective base address will be combined from the chopped (if any) + remap value (according to the size value and remap mechanism) and the + window's base address */ + effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); + /* If the effectiveBaseAddress exceed the window boundaries return an + invalid value. */ + + if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) + { + mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); + return 0xffffffff; + } + + return effectiveBaseAddress; + + +} +/******************************************************************************* +* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets +* +* DESCRIPTION: +* +* INPUT: +* target1 - CPU Interface target 1 +* target2 - CPU Interface target 2 +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if targets are illigal, or if one of the targets is not +* associated to a valid window . +* MV_OK otherwise. +* +*******************************************************************************/ + + +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) +{ + MV_U32 winNum1,winNum2; + MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; + MV_U32 remapBaseLow1=0,remapBaseLow2=0; + MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; + + + /* Check parameters */ + if (target1 >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); + return MV_ERROR; + } + + if (target2 >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); + return MV_ERROR; + } + + + /* get window associated with this target */ + winNum1 = mvAhbToMbusWinTargetGet(target1); + + if (winNum1 == 0xffffffff) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", + target1,winNum1); + return MV_ERROR; + + } + + /* get window associated with this target */ + winNum2 = mvAhbToMbusWinTargetGet(target2); + + if (winNum2 == 0xffffffff) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", + target2,winNum2); + return MV_ERROR; + + } + + /* now Get original values of both Windows */ + if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", + winNum1); + return MV_ERROR; + + } + if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", + winNum2); + return MV_ERROR; + + } + + + /* disable both windows */ + if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", + winNum1); + return MV_ERROR; + + } + if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", + winNum2); + return MV_ERROR; + + } + + + /* now swap targets */ + + /* first save winDec2 values */ + winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; + winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; + winDecTemp.addrWin.size = winDec2.addrWin.size; + winDecTemp.enable = winDec2.enable; + winDecTemp.target = winDec2.target; + + /* winDec2 = winDec1 */ + winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; + winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; + winDec2.addrWin.size = winDec1.addrWin.size; + winDec2.enable = winDec1.enable; + winDec2.target = winDec1.target; + + + /* winDec1 = winDecTemp */ + winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; + winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; + winDec1.addrWin.size = winDecTemp.addrWin.size; + winDec1.enable = winDecTemp.enable; + winDec1.target = winDecTemp.target; + + + /* now set the new values */ + + + mvAhbToMbusWinSet(winNum1,&winDec1); + mvAhbToMbusWinSet(winNum2,&winDec2); + + + + + + /* now we will treat the remap windows if exist */ + + + /* now check if one or both windows has a remap window + as well after the swap ! */ + + /* if a window had a remap value differnt than the base value + before the swap , then after the swap the remap value will be + equal to the base value unless both windows has a remap windows*/ + + /* first get old values */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) + { + remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); + remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); + + } + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) + { + remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); + remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); + + + } + + /* now do the swap */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) + { + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) + { + /* Two windows has a remap !!! so swap */ + + MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); + MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); + + MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); + MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); + + + + } + else + { + /* remap == base */ + MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); + MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); + + } + + } + else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) + { + /* remap == base */ + MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); + MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); + + } + + + + return MV_OK; + + +} + + + +#if defined(MV_88F1181) + +/******************************************************************************* +* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. +* +* DESCRIPTION: +* This function sets CPU Mbus Arbiter +* +* INPUT: +* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At +* each clock cycle, the crossbar arbiter samples all +* requests and gives the bus to the next agent according +* to the "pizza". +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if paramers to function invalid. +* +*******************************************************************************/ +MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) +{ + MV_U32 sliceNum; + MV_U32 xbarCtrl = 0; + MV_MBUS_ARB_TARGET xbarTarget; + + /* 1) Set crossbar control low register */ + for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) + { + xbarTarget = pPizzaArbArray[sliceNum]; + + /* sliceNum parameter check */ + if (xbarTarget > MAX_MBUS_ARB_TARGETS) + { + mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", + xbarTarget); + return MV_ERROR; + } + xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); + } + /* Write to crossbar control low register */ + MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); + + xbarCtrl = 0; + + /* 2) Set crossbar control high register */ + for (sliceNum = MRLR_SLICE_NUM; + sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; + sliceNum++) + { + + xbarTarget = pPizzaArbArray[sliceNum]; + + /* sliceNum parameter check */ + if (xbarTarget > MAX_MBUS_ARB_TARGETS) + { + mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", + xbarTarget); + return MV_ERROR; + } + xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); + } + /* Write to crossbar control high register */ + MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); + + return MV_OK; +} + +/******************************************************************************* +* mvMbusArbCtrlSet - Set MBus Arbiter control register +* +* DESCRIPTION: +* +* INPUT: +* ctrl - pointer to MV_MBUS_ARB_CTRL register +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if paramers to function invalid. +* +*******************************************************************************/ +MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) +{ + + if (ctrl->highPrio == MV_FALSE) + { + MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); + } + else + { + MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); + } + + if (ctrl->fixedRoundRobin == MV_FALSE) + { + MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); + } + else + { + MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); + } + + if (ctrl->starvEn == MV_FALSE) + { + MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); + } + else + { + MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* mvMbusArbCtrlGet - Get MBus Arbiter control register +* +* DESCRIPTION: +* +* INPUT: +* ctrl - pointer to MV_MBUS_ARB_CTRL register +* +* OUTPUT: +* ctrl - pointer to MV_MBUS_ARB_CTRL register +* +* RETURN: +* MV_ERROR if paramers to function invalid. +* +*******************************************************************************/ +MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) +{ + + MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); + + if (ctrlReg & MACR_ARB_ARM_TOP) + { + ctrl->highPrio = MV_TRUE; + } + else + { + ctrl->highPrio = MV_FALSE; + } + + if (ctrlReg & MACR_ARB_TARGET_FIXED) + { + ctrl->fixedRoundRobin = MV_TRUE; + } + else + { + ctrl->fixedRoundRobin = MV_FALSE; + } + + if (ctrlReg & MACR_ARB_REQ_CTRL_EN) + { + ctrl->starvEn = MV_TRUE; + } + else + { + ctrl->starvEn = MV_FALSE; + } + + + return MV_OK; +} + +#endif /* #if defined(MV_88F1181) */ + + + +/******************************************************************************* +* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets +* +* DESCRIPTION: +* CPU to PCI address remap registers offsets are inconsecutive. +* This function returns PCI address remap registers offsets. +* +* INPUT: +* winNum - Address decode window number. See MV_U32 enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one. +* +*******************************************************************************/ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, + AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) +{ + switch (winNum) + { + case 0: + case 1: + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + case 2: + case 3: + if((mvCtrlModelGet() == MV_5281_DEV_ID) || + (mvCtrlModelGet() == MV_1281_DEV_ID) || + (mvCtrlModelGet() == MV_6183_DEV_ID) || + (mvCtrlModelGet() == MV_6183L_DEV_ID)) + { + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + } + else + { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", + winNum)); + return MV_NO_SUCH; + } + default: + { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", + winNum)); + return MV_NO_SUCH; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvAhbToMbusAddDecShow(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN win; + MV_U32 winNum; + mvOsOutput( "\n" ); + mvOsOutput( "AHB To MBUS Bridge:\n" ); + mvOsOutput( "-------------------\n" ); + + for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) + { + memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); + + mvOsOutput( "win%d - ", winNum ); + + if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + + } + else + mvOsOutput( "disable\n" ); + } + } + +} + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbus.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbus.h new file mode 100644 index 0000000..1b352a1 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbus.h @@ -0,0 +1,130 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbush +#define __INCmvAhbToMbush + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* defines */ + +#if defined(MV_88F1181) +/* This enumerator defines the Marvell controller possible MBUS arbiter */ +/* target ports. It is used to define crossbar priority scheame (pizza) */ +typedef enum _mvMBusArbTargetId +{ + DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ + TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ + ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ + PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ + PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ + MAX_MBUS_ARB_TARGETS +}MV_MBUS_ARB_TARGET; + +typedef struct _mvMBusArbCtrl +{ + MV_BOOL starvEn; + MV_BOOL highPrio; + MV_BOOL fixedRoundRobin; + +}MV_MBUS_ARB_CTRL; + +#endif /* #if defined(MV_88F1181) */ + +typedef struct _mvAhbtoMbusDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_AHB_TO_MBUS_DEC_WIN; + +/* mvAhbToMbus.h API list */ + +MV_STATUS mvAhbToMbusInit(MV_VOID); +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); + +#if defined(MV_88F1181) + +MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); +MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); +MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); + +#endif /* #if defined(MV_88F1181) */ + + +MV_VOID mvAhbToMbusAddDecShow(MV_VOID); + + +#endif /* __INCmvAhbToMbush */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbusConfig.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbusConfig.h new file mode 100644 index 0000000..e01ee38 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbusConfig.h @@ -0,0 +1,74 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbusConfigh +#define __INCmvAhbToMbusConfigh + +#include "mvSysHwConfig.h" +#include "mvAhbToMbusRegs.h" + + + +#endif /* __INCmvAhbToMbusConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbusRegs.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbusRegs.h new file mode 100644 index 0000000..981986e --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvAhbToMbusRegs.h @@ -0,0 +1,188 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbusRegsh +#define __INCmvAhbToMbusRegsh + +/******************************/ +/* ARM Address Map Registers */ +/******************************/ + +#define MAX_AHB_TO_MBUS_WINS 9 +#define MV_AHB_TO_MBUS_INTREG_WIN 8 + + +#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 + +/* Window Control Register */ +/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ +#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ + +#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated + with this window*/ +#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) + +#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes + Associated with this window */ +#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) + + +/* +Used with the Base register to set the address window size and location +Must be programed from LSB to MSB as sequence of 1’s followed +by sequence of 0’s. The number of 1’s specifies the size of the window +in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). + +NOTE: A value of 0x0 specifies 64KB size. +*/ +#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ +#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) +#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 + +/* Window Base Register */ +/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ + +/* +Used with the size field to set the address window size and location. +Corresponds to transaction address[31:16] +*/ +#define ATMWBR_BASE_OFFS 16 /* Base Address */ +#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) +#define ATMWBR_BASE_ALIGNMENT 0x10000 + +/* Window Remap Low Register */ +/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ + +/* +Used with the size field to specifies address bits[31:0] to be driven to +the target interface.: +target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) +*/ +#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ +#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) +#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 + +/* Window Remap High Register */ +/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ + +/* +Specifies address bits[63:32] to be driven to the target interface. +target_addr[63:32] = (RemapHigh[31:0] +*/ +#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ +#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) + +#if defined(MV_88F1181) || defined(MV_88F1281) +/*******************************************/ +/* Mbus Arbiter Registers */ +/*******************************************/ + +#define MBUS_ARBITER_CTRL_REG 0x10200 +#define MBUS_ARBITER_LOW_REG 0x10204 +#define MBUS_ARBITER_HIGH_REG 0x10208 + + + +/*******************************************/ +/* Mbus Arbiter Registers */ +/*******************************************/ + +/* MBus Arbiter Control register */ +/* MBUS_ARBITER_CTRL_REG (MACR)*/ + +#define MACR_ARB_REQ_CTRL_EN_OFFS 0 +#define MACR_ARB_REQ_CTRL_EN (1 << MACR_ARB_REQ_CTRL_EN_OFFS) + +#define MACR_ARB_ARM_TOP_OFFS 1 +#define MACR_ARB_ARM_TOP (1 << MACR_ARB_ARM_TOP_OFFS) + +#define MACR_ARB_TARGET_OFFS 3 +#define MACR_ARB_TARGET_MASK BIT3 +#define MACR_ARB_TARGET_FIXED (1 << MACR_ARB_TARGET_OFFS) + + + +/* Mbus Arbiter Low Register */ +/* MBUS_ARBITER_LOW_REG (MRLR) */ + +#define MRLR_LOW_ARB_OFFS(num) (num*4) +#define MRLR_LOW_ARB_MASK(num) (0xf << MRLR_LOW_ARB_OFFS(num)) +#define MRLR_SLICE_NUM 8 + +/* Mbus Arbiter High Register */ +/* MBUS_ARBITER_HIGH_REG (MRHR) */ + +#define MRHR_HIGH_ARB_OFFS(num) ((8-num)*4) +#define MRHR_HIGH_ARB_MASK(num) (0xf << MRHR_HIGH_ARB_OFFS(num)) +#define MRHR_SLICE_NUM 8 + +#endif /* defined(MV_88F1181) || defined(MV_88F1281) */ + +#endif /* __INCmvAhbToMbusRegsh */ + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIf.c b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIf.c new file mode 100644 index 0000000..92b69e0 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIf.c @@ -0,0 +1,1040 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvCpuIfConfig.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" + +/*#define MV_DEBUG*/ +/* defines */ + +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + + + +/* locals */ +/* static functions */ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); + +MV_TARGET sampleAtResetTargetArray[] = BOOT_TARGETS_NAME_ARRAY; +/******************************************************************************* +* mvCpuIfInit - Initialize Controller CPU interface +* +* DESCRIPTION: +* This function initialize Controller CPU interface: +* 1. Set CPU interface configuration registers. +* 2. Set CPU master Pizza arbiter control according to static +* configuration described in configuration file. +* 3. Opens CPU address decode windows. DRAM windows are assumed to be +* already set (auto detection). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + MV_U32 regVal; + MV_TARGET target; + MV_ADDR_WIN addrWin; + + if (cpuAddrWinMap == NULL) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); + return MV_ERROR; + } + + /* Set ARM Configuration register */ + regVal = MV_REG_READ(CPU_CONFIG_REG); + regVal &= ~CPU_CONFIG_DEFAULT_MASK; + regVal |= CPU_CONFIG_DEFAULT; + MV_REG_WRITE(CPU_CONFIG_REG,regVal); + + +#if defined(MV_CPU_ADDRESS_DECODE_WA) + /* Work around for CPU address decode BUG */ + MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(6), ATMWCR_WIN_ENABLE); +#endif + + /* First disable all CPU target windows */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) + { + if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) + { + continue; + } + +#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PCI(target)) + { + continue; + } +#endif + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + { + continue; + } +#endif +#if defined(MV_RUN_FROM_FLASH) + /* Don't disable the boot device. */ + if (target == DEV_BOOCS) + { + continue; + } +#endif /* MV_RUN_FROM_FLASH */ + mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); + } + +#if defined(MV_RUN_FROM_FLASH) + /* Resize the bootcs windows before other windows, because this */ + /* window is enabled and will cause an overlap if not resized. */ + target = DEV_BOOCS; + + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) + { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } + +#endif /* MV_RUN_FROM_FLASH */ + + /* Go through all targets in user table until table terminator */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) + { + +#if defined(MV_RUN_FROM_FLASH) + if (target == DEV_BOOCS) + { + continue; + } +#endif /* MV_RUN_FROM_FLASH */ + + /* if DRAM auto sizing is used do not initialized DRAM target windows, */ + /* assuming this already has been done earlier. */ +#ifdef MV_DRAM_AUTO_SIZE + if (MV_TARGET_IS_DRAM(target)) + { + continue; + } +#endif + +#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PCI(target)) + { + continue; + } +#endif + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + { + continue; + } +#endif + /* If the target attribute is the same as the boot device attribute */ + /* then it's stays disable */ + if (MV_TARGET_IS_AS_BOOT(target)) + { + continue; + } + + if((0 == cpuAddrWinMap[target].addrWin.size) || + (DIS == cpuAddrWinMap[target].enable)) + + { + if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); + return MV_ERROR; + } + + } + else + { + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) + { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } + + + } + } + + return MV_OK; + + +} +/******************************************************************************* +* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window +* +* DESCRIPTION: +* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) +* address window, also known as address decode window. +* A new address decode window is set for specified target address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the target window, allowing CPU to access +* the target window. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - CPU target window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU target window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU target window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the target is unsupported. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 existingWinNum; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); + return MV_BAD_PARAM; + } + + if (MV_TARGET_IS_DRAM(target)) + { + /* copy relevant data to MV_DRAM_DEC_WIN structure */ + addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; + addrDecWin.enable = pAddrDecWin->enable; + + + if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); + { + mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); + return MV_ERROR; + } + + } + else + { + /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ + decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + decWin.addrWin.size = pAddrDecWin->addrWin.size; + decWin.enable = pAddrDecWin->enable; + decWin.target = target; + + existingWinNum = mvAhbToMbusWinTargetGet(target); + + /* check if there is already another Window configured + for this target */ + if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& + (existingWinNum != pAddrDecWin->winNum)) + { + /* if we want to enable the new winow number + passed by the user , then the old one should + be disabled */ + if (MV_TRUE == pAddrDecWin->enable) + { + /* be sure it is disabled */ + mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); + } + } + + if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); + return MV_ERROR; + } + + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window +* +* DESCRIPTION: +* Get the CPU peripheral target address window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* pAddrDecWin - CPU target window information data structure. +* +* RETURN: +* MV_OK if target exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + + MV_U32 winNum=0xffffffff; + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); + return MV_ERROR; + } + + if (MV_TARGET_IS_DRAM(target)) + { + if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", + target); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; + pAddrDecWin->enable = addrDecWin.enable; + pAddrDecWin->winNum = 0xffffffff; + + } + else + { + /* get the Window number associated with this target */ + + winNum = mvAhbToMbusWinTargetGet(target); + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + return MV_NO_SUCH; + + } + + if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) + { + mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", + __FUNCTION__, winNum); + return MV_ERROR; + + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = decWin.addrWin.size; + pAddrDecWin->enable = decWin.enable; + pAddrDecWin->winNum = winNum; + + } + + + + + return MV_OK; +} + + +/******************************************************************************* +* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* target - Peripheral target enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other target window. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) +{ + MV_U32 winNum, temp; + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* get the window and check if it exist */ + temp = mvCpuIfTargetWinGet(target, &addrDecWin); + if (MV_NO_SUCH == temp) + { + return (enable? MV_ERROR: MV_OK); + } + else if( MV_OK != temp) + { + mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); + return MV_ERROR; + } + + + /* check overlap */ + + if (MV_TRUE == enable) + { + if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) + { + DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); + return MV_ERROR; + } + + } + + + if (MV_TARGET_IS_DRAM(target)) + { + if (mvDramIfWinEnable(target , enable) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); + return MV_ERROR; + + } + + } + else + { + /* get the Window number associated with this target */ + + winNum = mvAhbToMbusWinTargetGet(target); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + return (enable? MV_ERROR: MV_OK); + } + + if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", + winNum); + return MV_ERROR; + + } + + } + + return MV_OK; +} + + +/******************************************************************************* +* mvCpuIfTargetWinSizeGet - Get CPU target address window size +* +* DESCRIPTION: +* Get the size of CPU-to-peripheral target window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit size. Function also returns '0' if window is closed. +* Function returns 0xFFFFFFFF in case of an error. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); + return 0; + } + + /* Get the winNum window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", + target); + return 0; + } + + /* Check if window is enabled */ + if (addrDecWin.enable == MV_TRUE) + { + return (addrDecWin.addrWin.size); + } + else + { + return 0; /* Window disabled. return 0 */ + } +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target low base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit low base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", + target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + { + return 0xffffffff; + } + return (addrDecWin.addrWin.baseLow); +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target high base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit high base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", + target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + { + return 0; + } + + return (addrDecWin.addrWin.baseHigh); +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCpuIfPexRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pexTarget - Peripheral target enumerator. Must be a PEX target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PEX one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* Check parameters */ + + if (mvCtrlPexMaxIfGet() > 1) + { + if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) + { + mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); + return 0xffffffff; + } + + } + else + { + if (!MV_TARGET_IS_PEX0(pexTarget)) + { + mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); + return 0xffffffff; + } + + } + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pexTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + + } + + return mvAhbToMbusWinRemap(winNum , pAddrDecWin); +} + +#endif + +#if defined(MV_INCLUDE_PCI) +/******************************************************************************* +* mvCpuIfPciRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pciTarget - Peripheral target enumerator. Must be a PCI target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* Check parameters */ + if (!MV_TARGET_IS_PCI(pciTarget)) + { + mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); + return 0xffffffff; + } + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pciTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + + } + + return mvAhbToMbusWinRemap(winNum , pAddrDecWin); +} +#endif /* MV_INCLUDE_PCI */ + + +/******************************************************************************* +* mvCpuIfPciIfRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pciTarget - Peripheral target enumerator. Must be a PCI target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) +{ +#if defined(MV_INCLUDE_PEX) + if (MV_TARGET_IS_PEX(pciIfTarget)) + { + return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); + } +#endif +#if defined(MV_INCLUDE_PCI) + + if (MV_TARGET_IS_PCI(pciIfTarget)) + { + return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); + } +#endif + return 0; +} + + + +/******************************************************************************* +* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address +* +* DESCRIPTION: +* +* INPUT: +* baseAddress - base address to be checked +* +* OUTPUT: +* None. +* +* RETURN: +* the target number that baseAddress belongs to or MAX_TARGETS is not +* found +* +*******************************************************************************/ + +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + for( target = 0; target < MAX_TARGETS; target++ ) + { + if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) + { + if( win.enable ) + { + if ((baseAddress >= win.addrWin.baseLow) && + (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; + } + } + else return MAX_TARGETS; + + } + + return target; +} +/******************************************************************************* +* cpuTargetWinOverlap - Detect CPU address decode windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case CPU address decode +* windows overlapps. +* This function detects CPU address decode windows overlapping of a +* specified target. The function does not check the target itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 targetNum; + MV_CPU_DEC_WIN addrDecWin; + MV_STATUS status; + + + for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) + { +#if defined(MV_RUN_FROM_FLASH) + if(MV_TARGET_IS_AS_BOOT(target)) + { + if (MV_CHANGE_BOOT_CS(targetNum) == target) + continue; + } +#endif /* MV_RUN_FROM_FLASH */ + + /* don't check our target or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); + if(MV_NO_SUCH == status) + { + continue; + } + if(MV_OK != status) + { + DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); + return MV_TRUE; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + DB(mvOsPrintf( + "cpuTargetWinOverlap: Required target %d overlap current %d\n", + target, targetNum)); + return MV_TRUE; + } + } + + return MV_FALSE; + +} + +/******************************************************************************* +* mvCpuIfAddDecShow - Print the CPU address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCpuIfAddDecShow(MV_VOID) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + mvOsOutput( "\n" ); + mvOsOutput( "CPU Interface\n" ); + mvOsOutput( "-------------\n" ); + + for( target = 0; target < MAX_TARGETS; target++ ) + { + + memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); + + mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); + mvOsOutput( "...." ); + + if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "base %08x, ", win.addrWin.baseLow ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + + } + else + mvOsOutput( "disable\n" ); + } + else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) + { + mvOsOutput( "no such\n" ); + } + } +} + +/******************************************************************************* +* mvCpuIfEnablePex - Enable PCI Express. +* +* DESCRIPTION: +* This function Enable PCI Express. +* +* INPUT: +* pexIf - PEX interface number. +* pexType - MV_PEX_ROOT_COMPLEX - root complex device +* MV_PEX_END_POINT - end point device +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#if defined(MV_INCLUDE_PEX) +MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) +{ + /* Set ARM Control and Status register */ +#if !defined(MV_88F6183) && !defined(MV_88F6183L) && !defined(MV_88F6082) + MV_U32 regVal; + regVal = MV_REG_READ(CPU_CTRL_STAT_REG); + regVal &= ~CPU_CTRL_STAT_DEFAULT_MASK; + regVal |= CPU_CTRL_STAT_DEFAULT; + MV_REG_WRITE(CPU_CTRL_STAT_REG,regVal); +#else + /* Set pex mode incase S@R not exist */ + if( pexType == MV_PEX_END_POINT) + { + MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); + /* Change pex mode in capability reg */ + MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); + MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); + + } + else + { + MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); + } + + /* CPU config register Pex enable */ + MV_REG_BIT_RESET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); +#endif +} +#endif diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIf.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIf.h new file mode 100644 index 0000000..839995e --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIf.h @@ -0,0 +1,116 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfh +#define __INCmvCpuIfh + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ddr1_2/mvDramIf.h" +#if defined(MV_INCLUDE_PEX) +#include "pci-if/mvPciIf.h" +#endif + +/* defines */ + +/* typedefs */ +/* This structure describes CPU interface address decode window */ +typedef struct _mvCpuIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_CPU_DEC_WIN; + + + +/* mvCpuIfLib.h API list */ + +/* mvCpuIfLib.h API list */ + +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); +MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); +#endif +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); +#endif +MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); + +MV_VOID mvCpuIfAddDecShow(MV_VOID); + + +#endif /* __INCmvCpuIfh */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIfConfig.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIfConfig.h new file mode 100644 index 0000000..0e44e7d --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIfConfig.h @@ -0,0 +1,138 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfconfigh +#define __INCmvCpuIfConfigh + +#include "mvSysHwConfig.h" +#include "mvCpuIfRegs.h" + +#if defined(MV_88F1181) + +/* CPU control register map */ +/* Set bits means value is about to change according to new value */ +#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | \ + CCR_AHB_ERROR_PROP_MASK) + + +#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00 ) + +/* CPU Control and status defaults */ +#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) + + +#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) + +#else + +/* CPU control register map */ +/* Set bits means value is about to change according to new value */ +#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | \ + CCR_AHB_ERROR_PROP_MASK) + + +#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00 ) + +/* CPU Control and status defaults */ +#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) + + +#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) + +/* Ratio options for CPU to DDR */ +#define CPU_2_DDR_CLK_1x1 1 +#define CPU_2_DDR_CLK_1x2 2 +#define CPU_2_DDR_CLK_1x3 3 +#define CPU_2_DDR_CLK_1x4 4 +#define CPU_2_DDR_CLK_1x5 5 +#define CPU_2_DDR_CLK_1x6 6 +#define CPU_2_DDR_CLK_1x7 7 + +/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ +/* CPU to Mbus-L Tick Sample fields in CPU config register */ +#define TICK_DRV_1x2 0 +#define TICK_SMPL_1x2 0 +#define TICK_DRV_1x3 1 +#define TICK_SMPL_1x3 2 +#define TICK_DRV_1x4 2 +#define TICK_SMPL_1x4 2 + +#define CPU_2_MBUSL_DDR_CLK_1x2 \ + ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) +#define CPU_2_MBUSL_DDR_CLK_1x3 \ + ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) +#define CPU_2_MBUSL_DDR_CLK_1x4 \ + ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) + + +#define CPU_FTDLL_IC_CONFIG_DEFAULT 0x1b +#define CPU_FTDLL_DC_CONFIG_DEFAULT 0x2 +#endif /* #if defined(MV_88F1181) */ + + +#endif /* __INCmvCpuIfConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIfInit.S b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIfInit.S new file mode 100644 index 0000000..3415261 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIfInit.S @@ -0,0 +1,191 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include "mvBoardEnvSpec.h" +#include "mvCtrlEnvSpec.h" +#include "mvCpuIfConfig.h" +#include "pex/mvPexRegs.h" +#include "pci/mvPciRegs.h" +#include "mvCtrlEnvAsm.h" +#include "cpu/mvCpuArm.h" + + +/******************************************************************************* +* mvCpuIfPreInit - Make early initialization of CPU interface. +* +* DESCRIPTION: +* The function will initialize the CPU interface parameters that must +* be initialize before any BUS activity towards the DDR interface, +* which means it must be executed from ROM. Because of that, the function +* is implemented in assembly code. +* The function configure the following CPU config register parameters: +* 1) CPU2MbusLTickDrv +* 2) CPU2MbusLTickSample. +* NOTE: This function must be called AFTER the internal register +* base is modified to INTER_REGS_BASE. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* r11 holds return function address. +*******************************************************************************/ + .extern _start + .extern _cpuARMDDRCLK + .globl _mvCpuIfPreInit +_mvCpuIfPreInit: + + mov r11, LR /* Save link register */ + + /* This function is for Orion2 B0 and up or TC90 only */ + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r4, r5); + + /* goto calcConfigReg if device is TC90 */ + ldr r5, =MV_1281_DEV_ID + cmp r4, r5 + beq calcConfigReg + + /* goto calcConfigReg if bigger than Orion2 A0*/ + ldr r5, =MV_5281_DEV_ID + cmp r4, r5 + bne done + + /* Return if Orion2 and device revision A0 */ + /* Read device revision */ + MV_CTRL_REV_GET_ASM(r4, r5); + cmp r4, #0 + beq done + +calcConfigReg: +#if defined(MV_RUN_FROM_FLASH) + /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ + ldr r7, = _cpuARMDDRCLK + ldr r4, =_start + ldr r4, [r4] + sub r7, r7, r4 + ldr r4, = Lrom_start_of_data + ldr r4, [r4] + add r7, r4, r7 + + +#else + ldr r7, = _cpuARMDDRCLK + ldr r4, =_start /* r0 <- current position of code */ + ldr r5, =_TEXT_BASE /* test if we run from flash or RAM */ + cmp r4, r5 /* dont reloc during debug */ + beq dram + + /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ + sub r7, r7, r4 + add r7, r7, #CFG_MONITOR_BASE +#endif + /* Get the "sample on reset" register */ +dram: MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_ARMDDRCLCK_MASK + and r5, r4, r5 + mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS + tst r4, #MSAR_ARMDDRCLCK_H_MASK + beq 1f + orr r5, r5, #BIT4 + +1: + ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE + mul r5, r4, r5 + add r7, r7, r5 + add r7, r7, #MV_CPU_ARM_CLK_RATIO_OFF + ldr r5, [r7] + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x2 + cmp r5, #CPU_2_DDR_CLK_1x2 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4 + beq setConfigReg + + /* Note; x4 and x5 ratios are not supported */ + ldr r4, =0 + +setConfigReg: + /* Read CPU Config register */ + MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) + ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) + and r7, r7, r5 /* Clear register fields */ + orr r7, r7, r4 /* Set the values according to the findings */ + MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) + +done: + mov PC, r11 /* r11 is saved link register */ diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIfRegs.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIfRegs.h new file mode 100644 index 0000000..45870f7 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvCpuIfRegs.h @@ -0,0 +1,246 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfRegsh +#define __INCmvCpuIfRegsh + +/****************************************/ +/* ARM Control and Status Registers Map */ +/****************************************/ + +#define CPU_CONFIG_REG 0x20100 +#define CPU_CTRL_STAT_REG 0x20104 +#define CPU_RSTOUTN_MASK_REG 0x20108 +#define CPU_SYS_SOFT_RST_REG 0x2010C +#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 +#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 +#define CPU_FTDLL_CONFIG_REG 0x20120 + + + +/* ARM Configuration register */ +/* CPU_CONFIG_REG (CCR) */ + + +/* Reset vector location */ +#define CCR_VEC_INIT_LOC_OFFS 1 +#define CCR_VEC_INIT_LOC_MASK BIT1 +/* reset at 0x00000000 */ +#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0xFFFF0000 */ +#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) + + +#define CCR_AHB_ERROR_PROP_OFFS 2 +#define CCR_AHB_ERROR_PROP_MASK BIT2 +/* Erros are not propogated to AHB */ +#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) +/* Erros are propogated to AHB */ +#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) + + +#define CCR_ENDIAN_INIT_OFFS 3 +#define CCR_ENDIAN_INIT_MASK BIT3 +#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) + + +#define CCR_INCR_EN_OFFS 4 +#define CCR_INCR_EN_MASK BIT4 +#define CCR_INCR_EN BIT4 + + +#define CCR_MMU_DISABLED_OFFS 5 +#define CCR_MMU_DISABLED_MASK (1 << CCR_MMU_DISABLED_OFFS) +#define CCR_MMU_ENABLED (0 << CCR_MMU_DISABLED_OFFS) +#define CCR_MMU_DISABLED (1 << CCR_MMU_DISABLED_OFFS) +/* Orion2 B0 and up */ +#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 +#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) +#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 +#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) +#define CCR_ICACH_PREF_BUF_ENABLE BIT16 +#define CCR_DCACH_PREF_BUF_ENABLE BIT17 + + + + + +/* ARM Control and Status register */ +/* CPU_CTRL_STAT_REG (CCSR) */ + + +/* +This is used to block PCI express\PCI from access Socrates/Feroceon GP +while ARM boot is still in progress +*/ + +#define CCSR_PCI_ACCESS_OFFS 0 +#define CCSR_PCI_ACCESS_MASK BIT0 +#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) +#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) + +#define CCSR_ARM_RESET BIT1 +#define CCSR_SELF_INT BIT2 +#define CCSR_BIG_ENDIAN BIT3 + + +/* RSTOUTn Mask Register */ +/* CPU_RSTOUTN_MASK_REG (CRMR) */ + +#define CRMR_PEX_RST_OUT_OFFS 0 +#define CRMR_PEX_RST_OUT_MASK BIT0 +#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) +#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) + +#define CRMR_WD_RST_OUT_OFFS 1 +#define CRMR_WD_RST_OUT_MASK BIT1 +#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) +#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) + +#define CRMR_SOFT_RST_OUT_OFFS 2 +#define CRMR_SOFT_RST_OUT_MASK BIT2 +#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) +#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) + +/* System Software Reset Register */ +/* CPU_SYS_SOFT_RST_REG (CSSRR) */ + +#define CSSRR_SYSTEM_SOFT_RST BIT0 + +/* AHB to Mbus Bridge Interrupt Cause Register*/ +/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ + +#define CAMCIR_ARM_SELF_INT BIT0 +#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 +#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 +#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 + + +/* AHB to Mbus Bridge Interrupt Mask Register*/ +/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ + +#define CAMCIR_ARM_SELF_INT_OFFS 0 +#define CAMCIR_ARM_SELF_INT_MASK BIT0 +#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) +#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) + + +#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 +#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 +#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) +#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) + +#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 +#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 +#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) +#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) + +#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 +#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 +#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) +#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) + +/* CPU FTDLL Config register (CFCR) fields */ +#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 +#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) +#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 +#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) +#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) +/* For Orion 2 D2 only */ +#define CFCR_MRVL_CPU_ID_OFFS 16 +#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) +#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) +#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) +#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 +#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) +#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) +#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) + + +/*******************************************/ +/* Main Interrupt Controller Registers Map */ +/*******************************************/ + +#define CPU_MAIN_INT_CAUSE_REG 0x20200 +#define CPU_MAIN_IRQ_MASK_REG 0x20204 +#define CPU_MAIN_FIQ_MASK_REG 0x20208 +#define CPU_ENPOINT_MASK_REG 0x2020C + + + +/*******************************************/ +/* ARM Doorbell Registers Map */ +/*******************************************/ + +#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 +#define CPU_HOST_TO_ARM_MASK_REG 0x20404 +#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 +#define CPU_ARM_TO_HOST_MASK_REG 0x2040C + + + +#endif /* __INCmvCpuIfRegsh */ + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysAudio.c b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysAudio.c new file mode 100644 index 0000000..d79aaaa --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysAudio.c @@ -0,0 +1,321 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvSysAudio.h" + +/******************************************************************************* +* mvAudioWinSet - Set AUDIO target address window +* +* DESCRIPTION: +* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) +* address window, also known as address decode window. +* After setting this target window, the AUDIO will be able to access the +* target within the address window. +* +* INPUT: +* winNum - AUDIO target address decode window number. +* pAddrDecWin - AUDIO target window data structure. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if address window overlapps with other address decode windows. +* MV_BAD_PARAM if base address is invalid parameter or target is +* unknown. +* +*******************************************************************************/ +MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttribs; + MV_DEC_REGS decRegs; + + /* Parameter checking */ + if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = 0; + decRegs.sizeReg = 0; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; + decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); + + /* set target ID */ + decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; + decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); + + if (pAddrDecWin->enable == MV_TRUE) + { + decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; + } + else + { + decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; + } + + MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); + MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvAudioWinGet - Get AUDIO peripheral target address window. +* +* DESCRIPTION: +* Get AUDIO peripheral target address window. +* +* INPUT: +* winNum - AUDIO target address decode window number. +* +* OUTPUT: +* pAddrDecWin - AUDIO target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s : ERR. Invalid winNum %d\n", + __FUNCTION__, winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); + decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) + { + mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> + MV_AUDIO_WIN_ATTR_OFFSET; + targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> + MV_AUDIO_WIN_TARGET_OFFSET; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + return MV_OK; +} +/******************************************************************************* +* mvAudioAddrDecShow - Print the AUDIO address decode map. +* +* DESCRIPTION: +* This function print the AUDIO address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvAudioAddrDecShow(MV_VOID) +{ + + MV_AUDIO_DEC_WIN win; + int i; + + + mvOsOutput( "\n" ); + mvOsOutput( "AUDIO:\n" ); + mvOsOutput( "----\n" ); + + for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvAudioWinGet( i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + + +/******************************************************************************* +* mvAudioWinInit - Initialize the integrated AUDIO target address window. +* +* DESCRIPTION: +* Initialize the AUDIO peripheral target address window. +* +* INPUT: +* +* +* OUTPUT: +* +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvAudioInit(MV_VOID) +{ + int winNum; + MV_AUDIO_DEC_WIN audioWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 status; + + mvAudioHalInit(); + + /* Initiate Audio address decode */ + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); + regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; + MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); + } + + for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) + { + + /* We will set the Window to DRAM_CS0 in default */ + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(SDRAM_CS0, + &cpuAddrDecWin); + + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; + audioWin.enable = MV_TRUE; + audioWin.target = SDRAM_CS0; + + if(MV_OK != mvAudioWinSet(winNum, &audioWin)) + { + return MV_ERROR; + } + } + } + + return MV_OK; +} + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysAudio.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysAudio.h new file mode 100644 index 0000000..f59eb9a --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysAudio.h @@ -0,0 +1,123 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCMVSysAudioH +#define __INCMVSysAudioH + +#include "mvCommon.h" +#include "audio/mvAudio.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +/***********************************/ +/* Audio Address Decoding registers*/ +/***********************************/ + +#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 +#define MV_AUDIO_RECORD_WIN_NUM 0 +#define MV_AUDIO_PLAYBACK_WIN_NUM 1 + +#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) +#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) + +#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) +#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) +#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) +#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) + + +/* BITs in Windows 0-3 Control and Base Registers */ +#define MV_AUDIO_WIN_ENABLE_BIT 0 +#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) +MV_TARGET tdmaAddrDecPrioTable[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif + + TBL_TERM +}; + +/******************************************************************************* +* mvCesaWinGet - Get TDMA target address window. +* +* DESCRIPTION: +* Get TDMA target address window. +* +* INPUT: +* winNum - TDMA target address decode window number. +* +* OUTPUT: +* pDecWin - TDMA target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) +{ + MV_DEC_WIN_PARAMS winParam; + MV_U32 sizeReg, baseReg; + + /* Parameter checking */ + if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) + { + mvOsPrintf("%s : ERR. Invalid winNum %d\n", + __FUNCTION__, winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); + sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); + + /* Check if window is enabled */ + if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) + { + pDecWin->enable = MV_TRUE; + + /* Extract window parameters from registers */ + winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; + winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; + winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; + winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); + + /* Translate the decode window parameters to address decode struct */ + if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) + { + mvOsPrintf("Failed to translate register parameters to CESA address" \ + " decode window structure\n"); + return MV_ERROR; + } + } + else + { + pDecWin->enable = MV_FALSE; + } + return MV_OK; +} + +/******************************************************************************* +* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case TDMA address decode +* windows overlapps. +* This function detects TDMA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - if the given address window overlap current address +* decode map, +* MV_FALSE - otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_DEC_WIN addrDecWin; + + for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) + { + mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) + { + mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pDecWin->target), + pDecWin->addrWin.baseLow, + pDecWin->addrWin.size); + return MV_ERROR; + } + + if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) + { + mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* set Size, Attributes and TargetID */ + sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | + ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | + ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); + + if (pDecWin->enable == MV_TRUE) + { + sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; + } + else + { + sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; + } + + /* Update Base value */ + baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); + + MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); + MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); + + return MV_OK; +} + + +static MV_STATUS mvCesaTdmaAddrDecInit (void) +{ + MV_U32 winNum; + MV_STATUS status; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_DEC_WIN cesaWin; + MV_U32 winPrioIndex = 0; + + /* First disable all address decode windows */ + for(winNum=0; winNum= 2 */ + + + + +MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) +{ + MV_U32 cesaCryptEngBase; + MV_CPU_DEC_WIN addrDecWin; + + if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) + { + mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", + sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); + return MV_FAIL; + } + + if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) + cesaCryptEngBase = addrDecWin.addrWin.baseLow; + else + { + mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); + return MV_ERROR; + } + +#if (MV_CESA_VERSION >= 2) + mvCesaTdmaAddrDecInit(); +#endif /* MV_CESA_VERSION >= 2 */ + + return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, + osHandle); + +} diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysCesa.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysCesa.h new file mode 100644 index 0000000..73bcdc5 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysCesa.h @@ -0,0 +1,100 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvSysCesa_h__ +#define __mvSysCesa_h__ + + +#include "mvCommon.h" +#include "cesa/mvCesa.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +/***************************** TDMA Registers *************************************/ + +#define MV_CESA_TDMA_ADDR_DEC_WIN 4 + +#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) + +#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) + +#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 +#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) + +#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 +#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) + +#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 +#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) + +#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 +#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) + +#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 +#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) + + +MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); + +#endif diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysDram.c b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysDram.c new file mode 100644 index 0000000..6f76c2c --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysDram.c @@ -0,0 +1,348 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ + +#include "ddr2/mvDramIf.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvSysDram.h" + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); + +/******************************************************************************* +* mvDramIfWinSet - Set DRAM interface address decode window +* +* DESCRIPTION: +* This function sets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* pAddrDecWin - SDRAM address window structure. +* +* OUTPUT: +* None +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg=0,sizeReg=0; + MV_U32 baseToReg=0 , sizeToReg=0; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlaps with current enabled windows */ + if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + target, + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read base register*/ + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); + + /* read size register */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; + + /* Write to address decode Base Address Register */ + baseReg &= ~SCBAR_BASE_MASK; + baseReg |= baseToReg; + + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); + return MV_BAD_PARAM; + } + + /* set size */ + sizeReg &= ~SCSR_SIZE_MASK; + /* Size is located at upper 16 bits */ + sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); + + /* enable/Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + sizeReg |= SCSR_WIN_EN; + } + else + { + sizeReg &= ~SCSR_WIN_EN; + } + + /* 3) Write to address decode Base Address Register */ + MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinGet - Get DRAM interface address decode window +* +* DESCRIPTION: +* This function gets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* pAddrDecWin - SDRAM address window structure. +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg,sizeReg; + MV_U32 sizeRegVal; + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Read base and size registers */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); + + sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; + + pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, + SCSR_SIZE_ALIGNMENT); + + /* Check if ctrlRegToSize returned OK */ + if (-1 == pAddrDecWin->addrWin.size) + { + mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; + + pAddrDecWin->addrWin.baseHigh = 0; + + + if (sizeReg & SCSR_WIN_EN) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinEnable - Enable/Disable SDRAM address decode window +* +* DESCRIPTION: +* This function enable/Disable SDRAM address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case function parameter are invalid, MV_OK otherewise. +* +*******************************************************************************/ +MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) +{ + MV_DRAM_DEC_WIN addrDecWin; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", + target); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode winNum window */ + MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); + } + else + { /* Overlap detected */ + mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", + target); + return MV_ERROR; + } + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window +* +* DESCRIPTION: +* This function scan each SDRAM address decode window to test if it +* overlapps the given address windoow +* +* INPUT: +* target - SDRAM target where the function skips checking. +* pAddrDecWin - The tested address window for overlapping with +* SDRAM windows. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps any enabled address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_TARGET targetNum; + MV_DRAM_DEC_WIN addrDecWin; + + for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) + { + /* don't check our winNum or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf( + "sdramIfWinOverlap: Required target %d overlap winNum %d\n", + target, targetNum); + return MV_TRUE; + } + } + + return MV_FALSE; +} + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysDram.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysDram.h new file mode 100644 index 0000000..7bd9c9d --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysDram.h @@ -0,0 +1,80 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __sysDram +#define __sysDram + +/* This structure describes CPU interface address decode window */ +typedef struct _mvDramIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +}MV_DRAM_DEC_WIN; + +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); + +#endif diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysGbe.c b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysGbe.c new file mode 100644 index 0000000..b00d221 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysGbe.c @@ -0,0 +1,660 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "ctrlEnv/sys/mvSysGbe.h" + + + +typedef struct _mvEthDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_ETH_DEC_WIN; + +MV_TARGET ethAddrDecPrioTap[] = +{ +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif +#if defined(MV_INCLUDE_PCI) + PCI0_MEM, +#endif +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_DEVICE_CS0) + DEVICE_CS0, +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEVICE_CS1, +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEVICE_CS2, +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEVICE_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_IO, +#endif +#if defined(MV_INCLUDE_PCI) + PCI0_IO, +#endif + TBL_TERM +}; + +static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); +static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); +static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); + + +/******************************************************************************* +* mvEthWinInit - Initialize ETH address decode windows +* +* DESCRIPTION: +* This function initialize ETH window decode unit. It set the +* default address decode windows of the unit. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if setting fail. +*******************************************************************************/ +/* Configure EthDrv memory map registes. */ +MV_STATUS mvEthWinInit (int port) +{ + MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; + MV_ETH_DEC_WIN ethWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + static MV_U32 accessProtReg = 0; + +#if (MV_ETH_VERSION <= 1) + static MV_BOOL isFirst = MV_TRUE; + + if(isFirst == MV_FALSE) + { + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); + return MV_OK; + } + isFirst = MV_FALSE; +#endif /* MV_GIGA_ETH_VERSION */ + + /* Initiate Ethernet address decode */ + + /* First disable all address decode windows */ + for(winNum=0; winNum= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + + decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); + decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; + decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; + decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; + + /* for the safe side we disable the window before writing the new + values */ + mvEthWinEnable(port, winNum, MV_FALSE); + MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); + + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + { + mvEthWinEnable(port, winNum, MV_TRUE); + } + + return MV_OK; +} + +/******************************************************************************* +* mvETHWinGet - Get dma peripheral target address window. +* +* DESCRIPTION: +* Get ETH peripheral target address window. +* +* INPUT: +* winNum - ETH to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - ETH target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); + decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; + targetAttrib.targetId = + (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvEthWinEnable - Enable/disable a ETH to target address window +* +* DESCRIPTION: +* This function enable/disable a ETH to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling ETH accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - ETH to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) +{ + MV_ETH_DEC_WIN addrDecWin; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) + { + mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + } + else + { /* Overlap detected */ + mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { /* Disable address decode target window */ + MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + } + return MV_OK; +} + +/******************************************************************************* +* mvEthWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* window number +* +*******************************************************************************/ +MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) +{ + MV_ETH_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + for (winNum=0; winNum= mvCtrlEthMaxPortGet()) + { + mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); + return MV_ERROR; + } + + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) + { + mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); + return MV_ERROR; + } + /* Read current protection register */ + protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); + + /* Clear protection window field */ + protReg &= ~(ETH_PROT_WIN_MASK(winNum)); + + /* Set new protection field value */ + protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); + + /* Write protection register back */ + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); + + return MV_OK; +} + +/******************************************************************************* +* ethWinOverlapDetect - Detect ETH address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case ETH address decode +* windows overlapps. +* This function detects ETH address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex; + MV_ETH_DEC_WIN addrDecWin; + + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); + + for (winNumIndex=0; winNumIndex= IDMA_MAX_ADDR_DEC_WIN) + { + mvOsPrintf("mvDmaWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == dmaWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvDmaWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvDmaWinSet: Error setting IDMA window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + + decRegs.baseReg = MV_REG_READ(IDMA_BASE_ADDR_REG(winNum)); + decRegs.sizeReg = MV_REG_READ(IDMA_SIZE_REG(winNum)); + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvDmaWinSet: mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + +#if defined(MV_INCLUDE_CESA) + /* See BTS Nastore #19.*/ + /* To access Tunit SRAM from IDMA use targetId = 0x5 */ + /* To access Tunit SRAM from the CPU use targetId = 0x9 */ + if(pAddrDecWin->target == CRYPT_ENG) + targetAttribs.targetId = 5; +#endif /* defined(MV_INCLUDE_CESA) */ + + /* set attributes */ + decRegs.baseReg &= ~IDMA_WIN_ATTR_MASK; + decRegs.baseReg |= targetAttribs.attrib << IDMA_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.baseReg &= ~IDMA_WIN_TARGET_MASK; + decRegs.baseReg |= targetAttribs.targetId << IDMA_WIN_TARGET_OFFS; + + /* for the safe side we disable the window before writing the new + values */ + mvDmaWinEnable(winNum,MV_FALSE); + + MV_REG_WRITE(IDMA_BASE_ADDR_REG(winNum), decRegs.baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(IDMA_SIZE_REG(winNum), decRegs.sizeReg); + + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + { + mvDmaWinEnable(winNum, MV_TRUE); + } + + return MV_OK; +} + +/******************************************************************************* +* mvDmaWinGet - Get dma peripheral target address window. +* +* DESCRIPTION: +* Get IDMA peripheral target address window. +* +* INPUT: +* winNum - IDMA to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - IDMA target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvDmaWinGet(MV_U32 winNum, MV_DMA_DEC_WIN *pAddrDecWin) +{ + + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= IDMA_MAX_ADDR_DEC_WIN) + { + mvOsPrintf("mvDmaWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(IDMA_BASE_ADDR_REG(winNum)); + decRegs.sizeReg = MV_REG_READ(IDMA_SIZE_REG(winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvDmaWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (decRegs.baseReg & IDMA_WIN_ATTR_MASK) >> IDMA_WIN_ATTR_OFFS; + targetAttrib.targetId = + (decRegs.baseReg & IDMA_WIN_TARGET_MASK) >> IDMA_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if (~(MV_REG_READ(IDMA_BASE_ADDR_ENABLE_REG)) & (IBAER_ENABLE(winNum))) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvDmaWinEnable - Enable/disable a DMA to target address window +* +* DESCRIPTION: +* This function enable/disable a DMA to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling DMA accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - IDMA to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvDmaWinEnable(MV_U32 winNum,MV_BOOL enable) +{ + MV_DMA_DEC_WIN addrDecWin; + + /* Parameter checking */ + if (winNum >= IDMA_MAX_ADDR_DEC_WIN) + { + mvOsPrintf("mvDmaWinEnable:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvDmaWinGet(winNum, &addrDecWin)) + { + mvOsPrintf("mvDmaWinEnable:ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == dmaWinOverlapDetect(winNum, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_RESET(IDMA_BASE_ADDR_ENABLE_REG, IBAER_ENABLE(winNum)); + } + else + { /* Overlap detected */ + mvOsPrintf("mvDmaWinEnable:ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { /* Disable address decode target window */ + MV_REG_BIT_SET(IDMA_BASE_ADDR_ENABLE_REG, IBAER_ENABLE(winNum)); + } + return MV_OK; +} + +/******************************************************************************* +* mvDmaWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* window number +* +*******************************************************************************/ +MV_U32 mvDmaWinTargetGet(MV_TARGET target) +{ + MV_DMA_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvDmaWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + for (winNum = 0; winNum < IDMA_MAX_ADDR_DEC_WIN ; winNum++) + { + if (mvDmaWinGet(winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvDmaWinTargetGet: mvDmaWinGet returned error\n"); + return 0xffffffff; + } + if (decWin.enable == MV_TRUE) + { + if (decWin.target == target) + { + return winNum; + } + } + } + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvDmaProtWinSet - Set access protection of IDMA to target window. +* +* DESCRIPTION: +* Each IDMA channel can be configured with access attributes for each +* of the IDMA to target windows (address decode windows). This +* function sets access attributes to a given window for the given channel. +* +* INPUTS: +* chan - IDMA channel number. See MV_DMA_CHANNEL enumerator. +* winNum - IDMA to target address decode window number. +* access - IDMA access rights. See MV_ACCESS_RIGHTS enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case window number is invalid or access right reserved. +* +*******************************************************************************/ +MV_STATUS mvDmaProtWinSet (MV_U32 chan, MV_U32 winNum, MV_ACCESS_RIGHTS access) +{ + MV_U32 protReg; + + /* Parameter checking */ + if ((chan >= MV_IDMA_MAX_CHAN) || (winNum >= IDMA_MAX_ADDR_DEC_WIN)) + { + mvOsPrintf("mvDmaProtWinSet:ERR. Invalid chan number %d\n", chan); + return MV_ERROR; + } + if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) + { + mvOsPrintf("mvDmaProtWinSet:ERR. Inv access param %d\n", access); + return MV_ERROR; + } + /* Read current protection register */ + protReg = MV_REG_READ(IDMA_ACCESS_PROTECT_REG(chan)); + + /* Clear protection window field */ + protReg &= ~(ICAPR_PROT_WIN_MASK(winNum)); + + /* Set new protection field value */ + protReg |= (access << (ICAPR_PROT_WIN_OFFS(winNum))); + + /* Write protection register back */ + MV_REG_WRITE(IDMA_ACCESS_PROTECT_REG(chan), protReg); + + return MV_OK; +} + +/******************************************************************************* +* mvDmaOverrideSet - Set DMA target window override +* +* DESCRIPTION: +* The address override feature enables additional address decoupling. +* For example, it allows the use of the same source and destination +* addresses while the source is targeted to one interface and +* destination to a second interface. +* DMA source/destination/next descriptor addresses can be override per +* address decode windows 1, 2 and 3 only. +* This function set override parameters per DMA channel. It access +* DMA control register low. +* +* INPUT: +* chan - IDMA channel number. See MV_DMA_CHANNEL enumerator. +* winNum - Override window numver. +* Note: 1) Not all windows can override. +* 2) Window '0' means disable override. +* override - Type of override. See MV_DMA_OVERRIDE enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM in case window can not perform override. +* +*******************************************************************************/ +MV_STATUS mvDmaOverrideSet(MV_U32 chan, MV_U32 winNum, MV_DMA_OVERRIDE override) +{ + MV_U32 ctrlLowReg; + + /* Parameter checking */ + if ((chan >= MV_IDMA_MAX_CHAN) || (winNum >= IDMA_MAX_OVERRIDE_WIN)) + { + mvOsPrintf("mvDmaOverrideSet:ERR. Invalid chan num %d\n", chan); + return MV_ERROR; + } + /* Read control register */ + ctrlLowReg = MV_REG_READ(IDMA_CTRL_LOW_REG(chan)); + + switch (override) + { + case (DMA_SRC_ADDR): + ctrlLowReg &= ~ICCLR_OVRRD_SRC_MASK; /* Clear SRC field */ + ctrlLowReg |= ICCLR_OVRRD_SRC_BAR(winNum); /* Set reg field */ + break; + case (DMA_DST_ADDR): + ctrlLowReg &= ~ICCLR_OVRRD_DST_MASK; /* Clear DST field */ + ctrlLowReg |= ICCLR_OVRRD_DST_BAR(winNum); /* Set reg field */ + break; + case (DMA_NEXT_DESC): + ctrlLowReg &= ~ICCLR_OVRRD_NDSC_MASK; /* Clear N_Desc field*/ + ctrlLowReg |= ICCLR_OVRRD_NDSC_BAR(winNum); /* Set reg field */ + break; + default: + { + mvOsPrintf("mvDmaOverrideSet:ERR. Inv override param%d\n",override); + return MV_BAD_PARAM; + } + } + /* Write control word back */ + MV_REG_WRITE(IDMA_CTRL_LOW_REG(chan), ctrlLowReg); + + return MV_OK; +} + +/******************************************************************************* +* mvDmaPciRemap - Set DMA remap register for PCI address windows. +* +* DESCRIPTION: +* The PCI interface supports 64-bit addressing. Four of the eight +* address windows have an upper 32-bit address register. To access the +* PCI bus with 64-bit addressing cycles (DAC cycles), this function +* assigns one (or more) of these four windows to target the PCI bus. +* The address generated on the PCI bus is composed of the window base +* address and the High Remap register. +* +* INPUT: +* winNum - IDMA to target address decode window number. Only 0 - 3. +* addrHigh - upper 32-bit address. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if window number is not between 0 and 3. +* +*******************************************************************************/ +MV_STATUS mvDmaPciRemap(MV_U32 winNum, MV_U32 addrHigh) +{ + /* Parameter checking */ + if (winNum >= IDMA_MAX_OVERRIDE_WIN) + { + mvOsPrintf("mvDmaPciRemap:ERR. Invalid window num %d\n", winNum); + return MV_BAD_PARAM; + } + + MV_REG_WRITE(IDMA_HIGH_ADDR_REMAP_REG(winNum), addrHigh); + + return MV_OK; +} + +/******************************************************************************* +* dmaWinOverlapDetect - Detect DMA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case DMA address decode +* windows overlapps. +* This function detects DMA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS dmaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex; + MV_DMA_DEC_WIN addrDecWin; + + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(IDMA_BASE_ADDR_ENABLE_REG); + + for (winNumIndex = 0; winNumIndex < IDMA_MAX_ADDR_DEC_WIN; winNumIndex++) + { + /* Do not check window itself */ + if (winNumIndex == winNum) + { + continue; + } + + /* Do not check disabled windows */ + if (baseAddrEnableReg & (IBAER_ENABLE(winNumIndex))) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvDmaWinGet(winNumIndex, &addrDecWin)) + { + DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + return MV_FALSE; +} + +/******************************************************************************* +* mvDmaAddrDecShow - Print the DMA address decode map. +* +* DESCRIPTION: +* This function print the DMA address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvDmaAddrDecShow(MV_VOID) +{ + + MV_DMA_DEC_WIN win; + int i; + + mvOsOutput( "\n" ); + mvOsOutput( "DMA:\n" ); + mvOsOutput( "----\n" ); + + for( i = 0; i < IDMA_MAX_ADDR_DEC_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_DMA_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvDmaWinGet( i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysIdma.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysIdma.h new file mode 100644 index 0000000..5a2a70c --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysIdma.h @@ -0,0 +1,142 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvSysIdmah +#define __INCmvSysIdmah + +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* General IDMA */ +#define IDMA_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ +#define IDMA_MAX_OVERRIDE_WIN 4 /* Maximum address override windows */ + +/* IDMA Address Decoding Base and size Registers */ +#define IDMA_BASE_ADDR_REG(winNum) (0x60a00 + ((winNum) * 8)) +#define IDMA_SIZE_REG(winNum) (0x60a04 + ((winNum) * 8)) + +/* IDMA Address Decoding High Address Remap,. Note that only window 0 - 3 */ +/* has remap capabilities */ +#define IDMA_HIGH_ADDR_REMAP_REG(winNum) (0x60a60 + ((winNum) * 4)) + +/* IDMA Base Addres enable register*/ +#define IDMA_BASE_ADDR_ENABLE_REG 0x60a80 + +/* IDMA Access Protection Registers */ +#define IDMA_ACCESS_PROTECT_REG(chan) (0x60a70 + ((chan) * 4)) + /* IDMA Headers Retarget Registers */ +#define IDMA_HEADERS_RETARGET_CTRL_REG 0x60a84 +#define IDMA_HEADERS_RETARGET_BASE_REG 0x60a88 + + +/* Base Addr reg */ +#define IDMA_WIN_TARGET_OFFS 0 /* The target interface associated with window*/ +#define IDMA_WIN_TARGET_MASK (0xf << IDMA_WIN_TARGET_OFFS) +#define IDMA_WIN_ATTR_OFFS 8 /* The target attributes Associated with window*/ +#define IDMA_WIN_ATTR_MASK (0xff << IDMA_WIN_ATTR_OFFS) + +/* IDMA Base Address Enable Register (IBAER) */ +#define IBAER_ENABLE_OFFS 0 +#define IBAER_ENABLE_MASK (0xFF << IBAER_ENABLE_OFFS) +#define IBAER_ENABLE(winNum) (1 << (winNum)) + +/* IDMA Channel Access Protect Register (ICAPR)*/ +#define ICAPR_PROT_NO_ACCESS NO_ACCESS_ALLOWED +#define ICAPR_PROT_READ_ONLY READ_ONLY +#define ICAPR_PROT_FULL_ACCESS FULL_ACCESS +#define ICAPR_PROT_WIN_OFFS(winNum) (2 * (winNum)) +#define ICAPR_PROT_WIN_MASK(winNum) (0x3 << ICAPR_PROT_WIN_OFFS(winNum)) + +/* This struct describes address decode override types */ +typedef enum _mvDmaOverride +{ + DMA_SRC_ADDR, /* Override source address */ + DMA_DST_ADDR, /* Override destination address */ + DMA_NEXT_DESC /* Override next descriptor address */ +}MV_DMA_OVERRIDE; + + +typedef struct _mvDmaDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_DMA_DEC_WIN; + +MV_STATUS mvDmaInit (MV_VOID); + +MV_STATUS mvDmaWinSet(MV_U32 winNum, MV_DMA_DEC_WIN *pAddrDecWin); +MV_STATUS mvDmaWinGet(MV_U32 winNum, MV_DMA_DEC_WIN *pAddrDecWin); +MV_STATUS mvDmaWinEnable(MV_U32 winNum,MV_BOOL enable); +MV_U32 mvDmaWinTargetGet(MV_TARGET target); + +MV_STATUS mvDmaProtWinSet (MV_U32 chan, MV_U32 winNum, MV_ACCESS_RIGHTS access); +MV_STATUS mvDmaOverrideSet(MV_U32 chan, MV_U32 winNum, MV_DMA_OVERRIDE override); +MV_STATUS mvDmaPciRemap(MV_U32 winNum, MV_U32 addrHigh); + +MV_VOID mvDmaAddrDecShow(MV_VOID); + +#endif /* __INCmvSysIdmaBarh */ + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPci.c b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPci.c new file mode 100644 index 0000000..e9f97b9 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPci.c @@ -0,0 +1,1490 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/sys/mvSysPci.h" + +/* PCI BARs registers offsets are inconsecutive. This struct describes BAR */ +/* register offsets and its function where its is located. */ +/* Also, PCI address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _pciBarRegInfo +{ + MV_U32 funcNum; + MV_U32 baseLowRegOffs; + MV_U32 baseHighRegOffs; + MV_U32 sizeRegOffs; + MV_U32 remapLowRegOffs; + MV_U32 remapHighRegOffs; +}PCI_BAR_REG_INFO; + +typedef struct _pciBarStatus +{ + MV_PCI_BAR bar; + int enable; +}PCI_BAR_STATUS; + +PCI_BAR_STATUS pciBarStatusMap[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + {CS0_BAR, EN}, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + {CS1_BAR, EN}, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + {CS2_BAR, EN}, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + {CS3_BAR, EN}, +#endif +#if defined(MV_INCLUDE_DEVICE_CS0) + {DEVCS0_BAR, EN}, +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + {DEVCS1_BAR, EN}, +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + {DEVCS2_BAR, EN}, +#endif + {BOOTCS_BAR, EN}, + {MEM_INTER_REGS_BAR, EN}, + {IO_INTER_REGS_BAR, EN}, + {P2P_MEM0, DIS}, + {P2P_IO, DIS}, + {TBL_TERM, TBL_TERM} +}; + +/* PCI BAR table. Note that table entry number must match its target */ +/* enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* target which is represent by DEVICE_CS0 enumerator (4). */ +#if 0 +MV_PCI_BAR_WIN pciBarMap[] = +{ +/* base low base high size enable/disable */ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE }, EN}, + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE }, EN}, + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE }, EN}, + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE }, EN}, + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE }, EN}, + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE }, EN}, + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE }, EN}, + {{BOOTDEV_CS_BASE, 0, BOOTDEV_CS_SIZE }, EN}, + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE }, EN}, + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE }, EN}, + {{ 0xFFFFFFFF , 0, 0xFFFFFFFF }, DIS}, /* Ignore P2P */ + {{ 0xFFFFFFFF , 0, 0xFFFFFFFF }, DIS}, /* Ignore P2P */ + /* Table terminator */ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM} +}; +#endif + +/* Locals */ +static MV_U32 pciBurstBytes2Reg(MV_U32 size); +static MV_U32 pciBurstReg2Bytes(MV_U32 size); + +static MV_STATUS pciWinOverlapDetect(MV_U32 pciIf, MV_PCI_BAR bar, + MV_ADDR_WIN *pAddrWin); + +static MV_STATUS pciBarRegInfoGet(MV_U32 pciIf, MV_PCI_BAR bar, + PCI_BAR_REG_INFO *pBarRegInfo); + +static MV_STATUS pciWinIsValid(MV_U32 baseLow, MV_U32 size); + +/* Forward declarations */ +const MV_8* pciBarNameGet(MV_PCI_BAR bar); + +static MV_TARGET pciBarToTarget(MV_PCI_BAR bar) +{ + switch(bar) + { + #if defined(MV_INCLUDE_SDRAM_CS0) + case CS0_BAR: + return SDRAM_CS0; + #endif + #if defined(MV_INCLUDE_SDRAM_CS1) + case CS1_BAR: + return SDRAM_CS1; + #endif + #if defined(MV_INCLUDE_SDRAM_CS2) + case CS2_BAR: + return SDRAM_CS2; + #endif + #if defined(MV_INCLUDE_SDRAM_CS3) + case CS3_BAR: + return SDRAM_CS3; + #endif + #if defined(MV_INCLUDE_DEVICE_CS0) + case DEVCS0_BAR: + return DEVICE_CS0; + #endif + #if defined(MV_INCLUDE_DEVICE_CS1) + case DEVCS1_BAR: + return DEVICE_CS1; + #endif + #if defined(MV_INCLUDE_DEVICE_CS2) + case DEVCS2_BAR: + return DEVICE_CS2; + #endif + case BOOTCS_BAR: + return DEV_BOOCS; + case MEM_INTER_REGS_BAR: + case IO_INTER_REGS_BAR: + return INTER_REGS; + + default: + mvOsPrintf("pciBarToTarget: ERR. no such target\n"); + } + + return -1; + +} +/******************************************************************************* +* mvPciInit - Initialize PCI interfaces +* +* DESCRIPTION: +* This function initiate the PCI interface: +* 1) Set local bus number. In case of convential PCI it gets the bus +* number using mvPciLocalBusNumGet(). In case of PCI-X this +* information is read only. +* 2) Interface device number. In case of conventional PCI it gets the +* device number using mvPciLocalDevNumGet(). In case of PCI-X this +* information is read only. +* 3) PCI Arbiter if needed. +* 4) Enable Master and Slave on PCI interfaces. +* 5) Open PCI BARs according to default setting. +* Note that PCI bridge (P2P) is NOT initialized. +* 6) Enable CPU to PCI ordering. +* +* INPUT: +* +* pciIf - PCI interface number. +* localBus - Local Bus of the PCI interface to be set +* localDev - Local Dev of the PCI interface to be set +* bFirstCall - Indicates wether this is the first call of this +* function . +* +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM +* +*******************************************************************************/ +MV_STATUS mvPciInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) +{ + MV_PCI_BAR bar, barix; + MV_PCI_BAR_WIN dramDecWin; + MV_PCI_MODE pciMode; + MV_CPU_DEC_WIN addrDecWin; + MV_PCI_PROT_WIN pciProtWin; + MV_PCI_BAR_WIN pciBarMap[PCI_MAX_BARS]; + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciInit: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + + /* device and bus numbers */ + if (MV_OK != mvPciModeGet(pciIf, &pciMode)) + { + mvOsPrintf("mvPciInit: ERR. mvPciModeGet failed\n"); + return MV_ERROR; + } + + /* First disable all PCI target windows */ + for (bar = 0; bar < PCI_MAX_BARS; bar++) + { + mvPciTargetWinEnable(pciIf, bar, MV_FALSE); + } + + /* WA CQ 4382*/ + MV_REG_BIT_SET(PCI_BASE_ADDR_ENABLE_REG(pciIf) ,BIT15); + + /* Building in run time the pci bar mapping table */ + for (bar = 0; bar < PCI_MAX_BARS; bar++) + { + for(barix = 0 ;barix < PCI_MAX_BARS; barix++) + { + if(pciBarStatusMap[barix].bar == bar) + { + pciBarMap[bar].enable = pciBarStatusMap[barix].enable; + break; + } + } + + if(bar == MEM_INTER_REGS_BAR || bar == IO_INTER_REGS_BAR) + { + pciBarMap[bar].addrWin.baseLow = mvCpuIfTargetWinBaseLowGet(pciBarToTarget(bar)); + pciBarMap[bar].addrWin.baseHigh = mvCpuIfTargetWinBaseHighGet(pciBarToTarget(bar)); + pciBarMap[bar].addrWin.size = mvCpuIfTargetWinSizeGet(pciBarToTarget(bar)); + continue; + } + + if(bar == P2P_MEM0 || bar == P2P_IO) + { + pciBarMap[bar].addrWin.baseLow = 0xFFFFFFFF; + pciBarMap[bar].addrWin.baseHigh = 0; + pciBarMap[bar].addrWin.size = 0xFFFFFFFF; + continue; + } + + if (mvCpuIfTargetWinGet(pciBarToTarget(bar), &addrDecWin) == MV_OK) + { + pciBarMap[bar].addrWin.baseLow = addrDecWin.addrWin.baseLow; + pciBarMap[bar].addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pciBarMap[bar].addrWin.size = addrDecWin.addrWin.size; + if(addrDecWin.enable == MV_FALSE) + { + pciBarMap[bar].enable = DIS; + } + } + else + { + pciBarMap[bar].addrWin.baseLow = 0xFFFFFFFF; + pciBarMap[bar].addrWin.baseHigh = 0; + pciBarMap[bar].addrWin.size = 0xFFFFFFFF; + pciBarMap[bar].enable = DIS; + } + } + + /* finally fill table with TBL_TERM entry */ + bar = PCI_MAX_BARS - 1; + pciBarMap[bar].addrWin.baseLow = TBL_TERM; + pciBarMap[bar].addrWin.baseHigh = TBL_TERM; + pciBarMap[bar].addrWin.size = TBL_TERM; + pciBarMap[bar].enable = TBL_TERM; + + + /* Memory Mapped Internal Registers BAR can not be disabled. */ + /* Relocate its BAR first to avoid colisions with other BARs (e.g DRAM) */ + if (MV_OK != mvPciTargetWinSet(pciIf, MEM_INTER_REGS_BAR, + &pciBarMap[MEM_INTER_REGS_BAR])) + { + mvOsPrintf("mvPciInit: ERR. mvPciTargetWinSet failed\n"); + return MV_ERROR; + } + + /* Now, go through all targets in default table until table terminator */ + for (bar = 0; pciBarMap[bar].enable != TBL_TERM; bar++) + { + /* Skip the P2P BARs. They should be configured seperately */ + if (0xFFFFFFFF == pciBarMap[bar].addrWin.baseLow) + { + continue; + } + + + /* check if the size passed is zero ! */ + if (0 == pciBarMap[bar].addrWin.size) + { + /* disable the bar */ + mvPciTargetWinEnable(pciIf,bar,MV_FALSE); + continue; + } + + /* Get DRAM parameters from CPU interface */ + if (MV_PCI_BAR_IS_DRAM_BAR(bar)) + { + if (MV_OK != mvCpuIfTargetWinGet(MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar), + &addrDecWin)) + { + mvOsPrintf("mvPciInit:ERR. targetWinGet %d fail\n", bar); + return MV_ERROR; + } + + dramDecWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; + dramDecWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + dramDecWin.addrWin.size = addrDecWin.addrWin.size; + dramDecWin.enable = addrDecWin.enable; + + if (MV_OK != mvPciTargetWinSet(pciIf, bar, &dramDecWin)) + { + mvOsPrintf("mvPciInit: ERR. mvPciTargetWinSet %d failed\n",bar); + return MV_ERROR; + } + + continue; + } + + if (MV_OK != mvPciTargetWinSet(pciIf, bar, &pciBarMap[bar])) + { + mvOsPrintf("mvPciInit: ERR. mvPciTargetWinSet %d failed\n", bar); + return MV_ERROR; + } + } + + MV_REG_BIT_SET(PCI_ADDR_DECODE_CONTROL_REG(pciIf), + PADCR_REMAP_REG_WR_DIS); + + + /* configure access control unit 0 to DDR to enhance performance */ + pciProtWin.addrWin.baseLow = 0; + pciProtWin.addrWin.baseHigh = 0; + pciProtWin.addrWin.size = mvDramIfSizeGet(); + pciProtWin.attributes.access = ALLOWED; + pciProtWin.attributes.write = ALLOWED; + pciProtWin.attributes.swapType = MV_BYTE_SWAP; + pciProtWin.attributes.readMaxBurst = 128; + pciProtWin.attributes.readBurst = 256; + pciProtWin.attributes.writeMaxBurst = 128; + pciProtWin.attributes.pciOrder = MV_FALSE; + pciProtWin.enable = MV_TRUE; + if( mvPciProtWinSet(pciIf, 0, &pciProtWin) != MV_OK ) + { + mvOsPrintf("mvPciInit: ERR. mvPciProtWinSet failed\n"); + return MV_ERROR; + } + + mvPciHalInit(pciIf, pciIfmod); + + return MV_OK; +} + + + +/******************************************************************************* +* mvPciTargetWinSet - Set PCI to peripheral target address window BAR +* +* DESCRIPTION: +* This function sets an address window from PCI to a peripheral +* target (e.g. SDRAM bank0, PCI_MEM0), also known as BARs. +* A new PCI BAR window is set for specified target address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the target window, allowing PCI to access +* the target window. +* +* INPUT: +* pciIf - PCI interface number. +* bar - BAR to be accessed by slave. +* pAddrBarWin - PCI target window information data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if PCI BAR target window was set correctly, MV_BAD_PARAM on bad params +* MV_ERROR otherwise +* (e.g. address window overlapps with other active PCI target window). +* +*******************************************************************************/ +MV_STATUS mvPciTargetWinSet(MV_U32 pciIf, + MV_PCI_BAR bar, + MV_PCI_BAR_WIN *pAddrBarWin) +{ + MV_U32 pciData; + MV_U32 sizeToReg; + MV_U32 size; + MV_U32 baseLow; + MV_U32 baseHigh; + MV_U32 localBus; + MV_U32 localDev; + PCI_BAR_REG_INFO barRegInfo; + + size = pAddrBarWin->addrWin.size; + baseLow = pAddrBarWin->addrWin.baseLow; + baseHigh = pAddrBarWin->addrWin.baseHigh; + + /* Parameter checking */ + if(pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + + if(bar >= PCI_MAX_BARS ) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Illigal PCI BAR %d\n", bar); + return MV_BAD_PARAM; + } + + + /* if the address windows is disabled , we only disable the appropriare + pci bar and ignore other settings */ + + if (MV_FALSE == pAddrBarWin->enable) + { + MV_REG_BIT_SET(PCI_BASE_ADDR_ENABLE_REG(pciIf), BARER_ENABLE(bar)); + return MV_OK; + } + + if (0 == pAddrBarWin->addrWin.size) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Target %d can't be zero!\n",bar); + return MV_BAD_PARAM; + } + + /* Check if the window complies with PCI spec */ + if (MV_TRUE != pciWinIsValid(baseLow, size)) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Target %d window invalid\n", bar); + return MV_BAD_PARAM; + } + + /* 2) Check if the requested window overlaps with current windows */ + if(MV_TRUE == pciWinOverlapDetect(pciIf, bar, &pAddrBarWin->addrWin)) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Overlap detected for target %d\n", + bar); + return MV_BAD_PARAM; + } + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(size, PBBLR_BASE_ALIGNMET); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvPciTargetWinSet: ERR. Target BAR %d size invalid.\n",bar); + return MV_BAD_PARAM; + } + + localBus = mvPciLocalBusNumGet(pciIf); + localDev = mvPciLocalDevNumGet(pciIf); + + /* Get BAR register information */ + pciBarRegInfoGet(pciIf, bar, &barRegInfo); + + /* Internal register space size have no size register. Do not perform */ + /* size register assigment for this slave target */ + if (0 != barRegInfo.sizeRegOffs) + { + /* Update size register */ + MV_REG_WRITE(barRegInfo.sizeRegOffs, (sizeToReg << BAR_SIZE_OFFS)); + } + + /* Read current address */ + pciData = mvPciConfigRead(pciIf, localBus, localDev, barRegInfo.funcNum, + barRegInfo.baseLowRegOffs); + + /* Clear current address */ + pciData &= ~PBBLR_BASE_MASK; + pciData |= (baseLow & PBBLR_BASE_MASK); + + /* Write new address */ + mvPciConfigWrite(pciIf, localBus, localDev, barRegInfo.funcNum, + barRegInfo.baseLowRegOffs, pciData); + + /* Skip base high settings if the BAR has only base low (32-bit) */ + if (0 != barRegInfo.baseHighRegOffs) + { + mvPciConfigWrite(pciIf, localBus, localDev, barRegInfo.funcNum, + barRegInfo.baseHighRegOffs, baseHigh); + } + + /* Enable/disable the BAR */ + if (MV_TRUE == pAddrBarWin->enable) + { + MV_REG_BIT_RESET(PCI_BASE_ADDR_ENABLE_REG(pciIf), BARER_ENABLE(bar)); + } + else + { + MV_REG_BIT_SET(PCI_BASE_ADDR_ENABLE_REG(pciIf), BARER_ENABLE(bar)); + } + + return MV_OK; +} + +/******************************************************************************* +* mvPciTargetWinGet - Get PCI to peripheral target address window +* +* DESCRIPTION: +* Get the PCI to peripheral target address window BAR. +* +* INPUT: +* pciIf - PCI interface number. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* pAddrBarWin - PCI target window information data structure. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciTargetWinGet(MV_U32 pciIf, MV_PCI_BAR bar, + MV_PCI_BAR_WIN *pAddrBarWin) +{ + MV_U32 size; + MV_U32 baseLow; + MV_U32 baseHigh; + MV_U32 localBus; + MV_U32 localDev; + MV_U32 barEnable; + PCI_BAR_REG_INFO barRegInfo; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciTargetWinGet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + + if (bar >= PCI_MAX_BARS ) + { + mvOsPrintf("mvPciTargetWinGet: ERR. Illigal PCI BAR %d.\n", bar); + return MV_BAD_PARAM; + } + + localBus = mvPciLocalBusNumGet(pciIf); + localDev = mvPciLocalDevNumGet(pciIf); + + /* Get BAR register information */ + pciBarRegInfoGet(pciIf, bar, &barRegInfo); + + /* Reading Base Low bar */ + baseLow = mvPciConfigRead(pciIf, localBus, localDev, barRegInfo.funcNum, + barRegInfo.baseLowRegOffs); + + baseLow &= PBBLR_BASE_MASK; + + /* Skip base high if the BAR has only base low (32-bit) */ + if (0 != barRegInfo.baseHighRegOffs) + { + /* Reading Base High */ + baseHigh = mvPciConfigRead(pciIf, localBus, localDev, barRegInfo.funcNum, + barRegInfo.baseHighRegOffs); + } + else + { + baseHigh = 0; + } + + /* Internal register space size have no size register. Do not perform */ + /* size register assigment for this slave target */ + if (0 != barRegInfo.sizeRegOffs) + { + /* Reading bar size*/ + size = ctrlRegToSize( + (MV_REG_READ(barRegInfo.sizeRegOffs) >> PBSR_SIZE_OFFS), + PBBLR_BASE_ALIGNMET); + } + else + { + size = INTER_REGS_SIZE; + } + + /* Assign value to user struct */ + pAddrBarWin->addrWin.baseLow = baseLow; + pAddrBarWin->addrWin.baseHigh = baseHigh; + pAddrBarWin->addrWin.size = size; + + /* Check if window is enabled */ + barEnable = MV_REG_READ(PCI_BASE_ADDR_ENABLE_REG(pciIf)); + + if (~barEnable & (BARER_ENABLE(bar))) + { + pAddrBarWin->enable = MV_TRUE; + } + else + { + pAddrBarWin->enable = MV_FALSE; + } + + return MV_OK; +} + + +/******************************************************************************* +* mvPciTargetWinEnable - Enable/disable a PCI BAR window +* +* DESCRIPTION: +* This function enable/disable a PCI BAR window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling PCI accesses for that BAR (before enabling the +* window it is tested for overlapping). Otherwise, the window will +* be disabled. +* +* INPUT: +* pciIf - PCI interface number. +* bar - BAR to be accessed by slave. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciTargetWinEnable(MV_U32 pciIf, MV_PCI_BAR bar, MV_BOOL enable) +{ + MV_PCI_BAR_WIN barWin; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciTargetWinEnable: ERR. Invalid PCI interface %d\n", + pciIf); + return MV_BAD_PARAM; + } + + if (bar >= PCI_MAX_BARS ) + { + mvOsPrintf("mvPciTargetWinEnable: ERR. Illigal PCI BAR %d\n", bar); + return MV_BAD_PARAM; + } + + if (MV_TRUE == enable) + { /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvPciTargetWinGet(pciIf, bar, &barWin)) + { + mvOsPrintf("mvPciTargetWinEnable: ERR. targetWinGet fail\n"); + return MV_ERROR; + } + + /* Check for overlapping */ + if (MV_TRUE == pciWinOverlapDetect(pciIf, bar, &barWin.addrWin)) + + { /* Overlap detected */ + mvOsPrintf("mvPciTargetWinEnable: ERR. Overlap detected\n"); + return MV_ERROR; + } + else + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_RESET(PCI_BASE_ADDR_ENABLE_REG(pciIf),BARER_ENABLE(bar)); + } + } + else + { + /* Disable address decode target window */ + MV_REG_BIT_SET(PCI_BASE_ADDR_ENABLE_REG(pciIf), BARER_ENABLE(bar)); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvPciProtWinSet - Set PCI protection access window +* +* DESCRIPTION: +* This function sets a specified address window with access protection +* attributes. If protection structure enables the window the routine will +* also enable the protection window. +* +* INPUT: +* pciIf - PCI interface number. +* winNum - Protecion window number. +* pProtWin - Protection window structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciProtWinSet(MV_U32 pciIf, + MV_U32 winNum, + MV_PCI_PROT_WIN *pProtWin) +{ + MV_U32 protBaseLow; + MV_U32 protBaseHigh; + MV_U32 protSize; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciProtWinSet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + if (winNum >= PCI_MAX_PROT_WIN) + { + mvOsPrintf("mvPciProtWinSet: ERR. Invalid window num %d\n", winNum); + return MV_BAD_PARAM; + } + + /* Check if the window complies with PCI spec */ + if (MV_TRUE != pciWinIsValid(pProtWin->addrWin.baseLow, + pProtWin->addrWin.size)) + { + mvOsPrintf("mvPciProtWinSet: ERR. Win base 0x%x unaligned to size 0x%x\n", + pProtWin->addrWin.baseLow, pProtWin->addrWin.size); + + return MV_BAD_PARAM; + } + + if (pProtWin->attributes.swapType >= SWAP_TYPE_MAX) + { + mvOsPrintf("mvPciProtWinSet: ERR. Swap parameter invalid %d\n", + pProtWin->attributes.swapType); + return MV_BAD_PARAM; + + } + + /* 1) Calculate protection window base low register value */ + protBaseLow = pProtWin->addrWin.baseLow; + + /* Setting the appropriate bits according to the passed values */ + if (MV_TRUE == pProtWin->enable) + { + protBaseLow |= PACBLR_EN; + } + else + { + protBaseLow &= ~PACBLR_EN; + } + + + /* Access protect */ + if (ALLOWED == pProtWin->attributes.access) + { + protBaseLow &= ~PACBLR_ACCPROT; + } + else + { + protBaseLow |= PACBLR_ACCPROT; + } + + /* Write Protect */ + if (ALLOWED == pProtWin->attributes.write) + { + protBaseLow &= ~PACBLR_WRPROT; + } + else + { + protBaseLow |= PACBLR_WRPROT; + } + + /* PCI slave Data Swap Control */ + protBaseLow |= (pProtWin->attributes.swapType << PACBLR_PCISWAP_OFFS); + + + /* Read Max Burst */ + if (( pciBurstBytes2Reg(pProtWin->attributes.readMaxBurst) << PACBLR_RDMBURST_OFFS) > PACBLR_RDMBURST_128BYTE) + { + mvOsPrintf("mvPciProtWinSet: ERR illigal read max burst\n"); + return MV_ERROR; + } + protBaseLow |= (pciBurstBytes2Reg(pProtWin->attributes.readMaxBurst) << PACBLR_RDMBURST_OFFS); + + + /* Typical PCI read transaction Size. Only valid for PCI conventional */ + if ((pciBurstBytes2Reg(pProtWin->attributes.readBurst) << PACBLR_RDSIZE_OFFS) > PACBLR_RDSIZE_256BYTE ) + { + mvOsPrintf("mvPciProtWinSet: ERR. illigal read size\n"); + return MV_ERROR; + } + protBaseLow |= (pciBurstBytes2Reg(pProtWin->attributes.readBurst) << PACBLR_RDSIZE_OFFS); + + + /* 2) Calculate protection window base high register value */ + protBaseHigh = pProtWin->addrWin.baseHigh; + + /* 3) Calculate protection window size register value */ + protSize = ctrlSizeToReg(pProtWin->addrWin.size, PACSR_SIZE_ALIGNMENT) << PACSR_SIZE_OFFS; + + + /* Write Max Burst */ + if ((pciBurstBytes2Reg(pProtWin->attributes.writeMaxBurst) << PACSR_WRMBURST_OFFS) > PACSR_WRMBURST_128BYTE ) + { + mvOsPrintf("mvPciProtWinSet: ERR illigal write max burst\n"); + return MV_ERROR; + } + protSize |= (pciBurstBytes2Reg(pProtWin->attributes.writeMaxBurst) << PACSR_WRMBURST_OFFS); + + /* Pci Order */ + if (MV_TRUE == pProtWin->attributes.pciOrder) + { + protSize |= PACSR_PCI_ORDERING; + } + else + { + protSize &= ~PACSR_PCI_ORDERING; + } + + /* Writing protection window walues into registers */ + MV_REG_WRITE(PCI_ACCESS_CTRL_BASEL_REG(pciIf,winNum), protBaseLow); + MV_REG_WRITE(PCI_ACCESS_CTRL_BASEH_REG(pciIf,winNum), protBaseHigh); + MV_REG_WRITE(PCI_ACCESS_CTRL_SIZE_REG(pciIf,winNum), protSize); + + return MV_OK; +} +/******************************************************************************* +* mvPciProtWinGet - Get PCI protection access window +* +* DESCRIPTION: +* This function gets a specified address window and access protection +* attributes for a specific protection window . +* +* INPUT: +* pciIf - PCI interface number. +* winNum - Protecion window number. +* pProtWin - pointer to a Protection window structure. +* +* OUTPUT: +* pProtWin - Protection window structure. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciProtWinGet(MV_U32 pciIf, + MV_U32 winNum, + MV_PCI_PROT_WIN *pProtWin) +{ + MV_U32 protBaseLow; + MV_U32 protBaseHigh; + MV_U32 protSize; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciProtWinGet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + if (winNum >= PCI_MAX_PROT_WIN) + { + mvOsPrintf("mvPciProtWinGet: ERR. Invalid window num %d\n", winNum); + return MV_BAD_PARAM; + } + + /* Writing protection window walues into registers */ + protBaseLow = MV_REG_READ(PCI_ACCESS_CTRL_BASEL_REG(pciIf,winNum)); + protBaseHigh = MV_REG_READ(PCI_ACCESS_CTRL_BASEH_REG(pciIf,winNum)); + protSize = MV_REG_READ(PCI_ACCESS_CTRL_SIZE_REG(pciIf,winNum)); + + + /* 1) Get Protection Windows base low */ + pProtWin->addrWin.baseLow = protBaseLow & PACBLR_BASE_L_MASK; + + /* Get the appropriate protection attributes according to register bits*/ + + /* Is Windows enabled ? */ + if (protBaseLow & PACBLR_EN) + { + pProtWin->enable = MV_TRUE; + } + else + { + pProtWin->enable = MV_FALSE; + } + + + /* What is access protect ? */ + if (protBaseLow & PACBLR_ACCPROT) + { + pProtWin->attributes.access = FORBIDDEN; + } + else + { + pProtWin->attributes.access = ALLOWED; + } + + /* Is write protect ? */ + if (protBaseLow & PACBLR_WRPROT) + { + pProtWin->attributes.write = FORBIDDEN; + } + else + { + pProtWin->attributes.write = ALLOWED; + } + + + /* PCI slave Data Swap Control */ + pProtWin->attributes.swapType = (protBaseLow & PACBLR_PCISWAP_MASK) >> PACBLR_PCISWAP_OFFS; + + + /* Read Max Burst */ + pProtWin->attributes.readMaxBurst = pciBurstReg2Bytes((protBaseLow & PACBLR_RDMBURST_MASK) >> PACBLR_RDMBURST_OFFS); + + /* Typical PCI read transaction Size. */ + pProtWin->attributes.readBurst = pciBurstReg2Bytes((protBaseLow & PACBLR_RDSIZE_MASK) >> PACBLR_RDSIZE_OFFS); + + + /* window base high register value */ + pProtWin->addrWin.baseHigh = protBaseHigh; + + /*Calculate protection window size register value */ + pProtWin->addrWin.size = ctrlRegToSize(((protSize & PACSR_SIZE_MASK) >> PACSR_SIZE_OFFS),PACSR_SIZE_ALIGNMENT); + + + /* Write Max Burst */ + pProtWin->attributes.writeMaxBurst = pciBurstReg2Bytes((protSize & PACSR_WRMBURST_MASK) >> PACSR_WRMBURST_OFFS); + + /* Pci Order */ + if (protSize & PACSR_PCI_ORDERING) + { + pProtWin->attributes.pciOrder = MV_TRUE; + } + else + { + pProtWin->attributes.pciOrder = MV_FALSE; + } + + + return MV_OK; +} + + +/******************************************************************************* +* mvPciProtWinEnable - Enable/disable a PCI protection access window +* +* DESCRIPTION: +* This function enable/disable a PCI protection access window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* protection window, otherwise, the protection window will be disabled. +* +* INPUT: +* pciIf - PCI interface number. +* winNum - Protecion window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciProtWinEnable(MV_U32 pciIf, MV_U32 winNum, MV_BOOL enable) +{ + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciProtWinEnable: ERR. Invalid PCI interface %d\n", + pciIf); + return MV_BAD_PARAM; + } + + if (winNum >= PCI_MAX_PROT_WIN) + { + mvOsPrintf("mvPciProtWinEnable: ERR. Invalid window num %d\n", winNum); + return MV_BAD_PARAM; + } + + if (MV_TRUE == enable) + { + MV_REG_BIT_SET(PCI_ACCESS_CTRL_BASEL_REG(pciIf,winNum), PACBLR_EN); + } + else + { + MV_REG_BIT_RESET(PCI_ACCESS_CTRL_BASEL_REG(pciIf,winNum), PACBLR_EN); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvPciTargetRemap - Set PCI to target address window remap. +* +* DESCRIPTION: +* The PCI interface supports remap of the BAR original address window. +* For each BAR it is possible to define a remap address. For example +* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified +* according to remap register but will also be targeted to the +* SDRAM CS[0]. +* +* INPUT: +* pciIf - PCI interface number. +* bar - Peripheral target enumerator accessed by slave. +* pAddrWin - Address window to be checked. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciTargetRemap(MV_U32 pciIf, + MV_PCI_BAR bar, + MV_ADDR_WIN *pAddrWin) +{ + PCI_BAR_REG_INFO barRegInfo; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciTargetRemap: ERR. Invalid PCI interface num %d\n", + pciIf); + return MV_BAD_PARAM; + } + + if (MV_IS_NOT_ALIGN(pAddrWin->baseLow, PBARR_REMAP_ALIGNMENT)) + { + mvOsPrintf("mvPciTargetRemap: Error remapping PCI interface %d bar %s."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + pciIf, + pciBarNameGet(bar), + pAddrWin->baseLow, + pAddrWin->size); + return MV_ERROR; + } + + pciBarRegInfoGet(pciIf, bar, &barRegInfo); + + /* Set remap low register value */ + MV_REG_WRITE(barRegInfo.remapLowRegOffs, pAddrWin->baseLow); + + /* Skip base high settings if the BAR has only base low (32-bit) */ + if (0 != barRegInfo.remapHighRegOffs) + { + MV_REG_WRITE(barRegInfo.remapHighRegOffs, pAddrWin->baseHigh); + } + + return MV_OK; +} + +/******************************************************************************* +* pciWinOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PCI BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pciWinOverlapDetect(MV_U32 pciIf, + MV_PCI_BAR bar, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 barEnableReg; + MV_U32 targetBar; + MV_PCI_BAR_WIN barAddrWin; + + /* Read base address enable register. Do not check disabled windows */ + barEnableReg = MV_REG_READ(PCI_BASE_ADDR_ENABLE_REG(pciIf)); + + for(targetBar = 0; targetBar < PCI_MAX_BARS; targetBar++) + { + /* don't check our target or illegal targets */ + if (targetBar == bar) + { + continue; + } + + /* Do not check disabled windows */ + if (barEnableReg & (BARER_ENABLE(targetBar))) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvPciTargetWinGet(pciIf, targetBar, &barAddrWin)) + { + mvOsPrintf("pciWinOverlapDetect: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* skip overlapp detect between MEM_INTER_REGS_BAR and IO_INTER_REGS_BAR*/ + if (((bar == MEM_INTER_REGS_BAR)&&(targetBar == IO_INTER_REGS_BAR)) || + ((bar == IO_INTER_REGS_BAR)&&(targetBar == MEM_INTER_REGS_BAR))) + { + return MV_FALSE; + } + else if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barAddrWin.addrWin)) + { + mvOsPrintf("pciWinOverlapDetect: BAR %d overlap current %d\n", + bar, targetBar); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* cpuWinIsValid - Check if the given address window is valid +* +* DESCRIPTION: +* PCI spec restrict BAR base to be aligned to BAR size. +* This function checks if the given address window is valid. +* +* INPUT: +* baseLow - 32bit low base address. +* size - Window size. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the address window is valid, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_STATUS pciWinIsValid(MV_U32 baseLow, MV_U32 size) +{ + + /* PCI spec restrict BAR base to be aligned to BAR size */ + if(MV_IS_NOT_ALIGN(baseLow, size)) + { + return MV_ERROR; + } + else + { + return MV_TRUE; + } +} + +/******************************************************************************* +* pciBarRegInfoGet - Get BAR register information +* +* DESCRIPTION: +* PCI BARs registers offsets are inconsecutive. +* This function gets a PCI BAR register information like register offsets +* and function location of the BAR. +* +* INPUT: +* pciIf - PCI interface number. +* bar - The PCI BAR in question. +* +* OUTPUT: +* pBarRegInfo - BAR register info struct. +* +* RETURN: +* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK +* +*******************************************************************************/ +static MV_STATUS pciBarRegInfoGet(MV_U32 pciIf, + MV_PCI_BAR bar, + PCI_BAR_REG_INFO *pBarRegInfo) +{ + switch (bar) + { + /* Function 0 Bars */ + #if defined(MV_INCLUDE_SDRAM_CS0) + case CS0_BAR: /* SDRAM chip select 0 bar*/ + pBarRegInfo->funcNum = 0; + pBarRegInfo->baseLowRegOffs = PCI_SCS0_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_SCS0_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_CS0_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_CS0_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + #if defined(MV_INCLUDE_SDRAM_CS1) + case CS1_BAR: /* SDRAM chip select 1 bar*/ + pBarRegInfo->funcNum = 0; + pBarRegInfo->baseLowRegOffs = PCI_SCS1_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_SCS1_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_CS1_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_CS1_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + case MEM_INTER_REGS_BAR: /* Memory Mapped Internal bar */ + pBarRegInfo->funcNum = 0; + pBarRegInfo->baseLowRegOffs = PCI_INTER_REG_MEM_MAPPED_BASE_ADDR_L; + pBarRegInfo->baseHighRegOffs = PCI_INTER_REG_MEM_MAPPED_BASE_ADDR_H; + pBarRegInfo->sizeRegOffs = 0; + pBarRegInfo->remapLowRegOffs = 0; + pBarRegInfo->remapHighRegOffs = 0; + break; + + /* Function 1 Bars */ + #if defined(MV_INCLUDE_SDRAM_CS2) + case CS2_BAR: /* SDRAM chip select 2 bar*/ + pBarRegInfo->funcNum = 1; + pBarRegInfo->baseLowRegOffs = PCI_SCS2_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_SCS2_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_CS2_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_CS2_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + #if defined(MV_INCLUDE_SDRAM_CS3) + case CS3_BAR: /* SDRAM chip select 3 bar*/ + pBarRegInfo->funcNum = 1; + pBarRegInfo->baseLowRegOffs = PCI_SCS3_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_SCS3_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_CS3_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_CS3_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + #if defined(MV_INCLUDE_DEVICE_CS0) + /* Function 2 Bars */ + case DEVCS0_BAR: /* Device chip select 0 bar*/ + pBarRegInfo->funcNum = 2; + pBarRegInfo->baseLowRegOffs = PCI_DEVCS0_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_DEVCS0_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_DEVCS0_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_DEVCS0_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + #if defined(MV_INCLUDE_DEVICE_CS1) + case DEVCS1_BAR: /* Device chip select 0 bar*/ + pBarRegInfo->funcNum = 2; + pBarRegInfo->baseLowRegOffs = PCI_DEVCS1_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_DEVCS1_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_DEVCS1_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_DEVCS1_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + #if defined(MV_INCLUDE_DEVICE_CS2) + case DEVCS2_BAR: /* Device chip select 0 bar*/ + pBarRegInfo->funcNum = 2; + pBarRegInfo->baseLowRegOffs = PCI_DEVCS2_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_DEVCS2_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_DEVCS2_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_DEVCS2_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + #endif + case BOOTCS_BAR: /* Boot device chip select bar*/ + pBarRegInfo->funcNum = 3; + pBarRegInfo->baseLowRegOffs = PCI_BOOTCS_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_BOOTCS_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_BOOTCS_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_BOOTCS_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + + /* Function 4 Bars */ + case P2P_MEM0: /* P2P memory 0 */ + pBarRegInfo->funcNum = 4; + pBarRegInfo->baseLowRegOffs = PCI_P2P_MEM0_BASE_ADDR_LOW; + pBarRegInfo->baseHighRegOffs = PCI_P2P_MEM0_BASE_ADDR_HIGH; + pBarRegInfo->sizeRegOffs = PCI_P2P_MEM0_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_P2P_MEM0_ADDR_REMAP_LOW_REG(pciIf); + pBarRegInfo->remapHighRegOffs = PCI_P2P_MEM0_ADDR_REMAP_HIGH_REG(pciIf); + break; + case P2P_IO: /* P2P IO */ + pBarRegInfo->funcNum = 4; + pBarRegInfo->baseLowRegOffs = PCI_P2P_IO_BASE_ADDR; + pBarRegInfo->baseHighRegOffs = 0; + pBarRegInfo->sizeRegOffs = PCI_P2P_IO_BAR_SIZE_REG(pciIf); + pBarRegInfo->remapLowRegOffs = PCI_P2P_IO_ADDR_REMAP_REG(pciIf); + pBarRegInfo->remapHighRegOffs = 0; + break; + case IO_INTER_REGS_BAR: /* IO Mapped Internal bar */ + pBarRegInfo->funcNum = 4; + pBarRegInfo->baseLowRegOffs = PCI_INTER_REGS_IO_MAPPED_BASE_ADDR; + pBarRegInfo->baseHighRegOffs = 0; + pBarRegInfo->sizeRegOffs = 0; + pBarRegInfo->remapLowRegOffs = 0; + pBarRegInfo->remapHighRegOffs = 0; + break; + + + default: + mvOsPrintf("mvPciTargetWinGet: ERR.non existing target\n"); + return MV_ERROR; + + } + + return MV_OK; +} + +/******************************************************************************* +* pciBarNameGet - Get the string name of PCI BAR. +* +* DESCRIPTION: +* This function get the string name of PCI BAR. +* +* INPUT: +* bar - PCI bar number. +* +* OUTPUT: +* None. +* +* RETURN: +* pointer to the string name of PCI BAR. +* +*******************************************************************************/ +const MV_8* pciBarNameGet( MV_PCI_BAR bar ) +{ + switch( bar ) + { + #if defined(MV_INCLUDE_SDRAM_CS0) + case CS0_BAR: + return "CS0_BAR.............."; + #endif + #if defined(MV_INCLUDE_SDRAM_CS1) + case CS1_BAR: + return "CS1_BAR.............."; + #endif + #if defined(MV_INCLUDE_SDRAM_CS2) + case CS2_BAR: + return "CS2_BAR.............."; + #endif + #if defined(MV_INCLUDE_SDRAM_CS3) + case CS3_BAR: + return "CS3_BAR.............."; + #endif + #if defined(MV_INCLUDE_DEVICE_CS0) + case DEVCS0_BAR: + return "DEVCS0_BAR..........."; + #endif + #if defined(MV_INCLUDE_DEVICE_CS1) + case DEVCS1_BAR: + return "DEVCS1_BAR..........."; + #endif + #if defined(MV_INCLUDE_DEVICE_CS2) + case DEVCS2_BAR: + return "DEVCS2_BAR..........."; + #endif + case BOOTCS_BAR: + return "BOOTCS_BAR..........."; + case MEM_INTER_REGS_BAR: + return "MEM_INTER_REGS_BAR..."; + case IO_INTER_REGS_BAR: + return "IO_INTER_REGS_BAR...."; + case P2P_MEM0: + return "P2P_MEM0............."; + case P2P_IO: + return "P2P_IO..............."; + default: + return "target unknown"; + } +} + +/******************************************************************************* +* mvPciAddrDecShow - Print the PCI address decode map (BARs). +* +* DESCRIPTION: +* This function print the PCI address decode map (BARs). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvPciAddrDecShow(MV_VOID) +{ + MV_PCI_BAR_WIN win; + MV_PCI_BAR bar; + MV_U32 pciIf; + + for( pciIf = 0; pciIf < mvCtrlPciMaxIfGet(); pciIf++ ) + { + if (MV_FALSE == mvCtrlPwrClckGet(PCI_UNIT_ID, pciIf)) continue; + mvOsOutput( "\n" ); + mvOsOutput( "PCI%d:\n", pciIf ); + mvOsOutput( "-----\n" ); + + for( bar = 0; bar < PCI_MAX_BARS; bar++ ) + { + memset( &win, 0, sizeof(MV_PCI_BAR_WIN) ); + + mvOsOutput( "%s ", pciBarNameGet(bar) ); + + if( mvPciTargetWinGet( pciIf, bar, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "base %08x, ", win.addrWin.baseLow ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } + } +} + +/* convert burst bytes to register value*/ +static MV_U32 pciBurstBytes2Reg(MV_U32 size) +{ + MV_U32 ret; + switch(size) + { + case 32: ret = 0; break; + case 64: ret = 1; break; + case 128: ret = 2; break; + case 256: ret = 3; break; + default: ret = 0xF; /* error */ + } + return ret; +} + +/* convert register value to burst bytes*/ +static MV_U32 pciBurstReg2Bytes(MV_U32 size) +{ + MV_U32 ret; + switch(size) + { + case 0: ret = 32; break; + case 1: ret = 64; break; + case 2: ret = 128; break; + case 3: ret = 256; break; + default: ret = 0x0; /* error */ + } + return ret; +} + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPci.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPci.h new file mode 100644 index 0000000..de1f526 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPci.h @@ -0,0 +1,277 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCSysPCIH +#define __INCSysPCIH + +#include "ctrlEnv/sys/mvCpuIf.h" +#include "pci/mvPci.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#define PCI_MAX_PROT_WIN 6 + +/* 4KB granularity */ +#define MINIMUM_WINDOW_SIZE 0x1000 +#define MINIMUM_BAR_SIZE 0x1000 +#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 +#define BAR_SIZE_OFFS 12 +#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) + +#define PCI_IO_WIN_NUM 1 /* Number of PCI_IO windows */ +#define PCI_MEM_WIN_NUM 4 /* Number of PCI_MEM windows */ + +#ifndef MV_ASMLANGUAGE +#include "ctrlEnv/mvCtrlEnvLib.h" +typedef enum _mvPCIBars +{ + PCI_BAR_TBL_TERM = -1, /* none valid bar, used as bars list terminator */ +#if defined(MV_INCLUDE_SDRAM_CS0) + CS0_BAR, /* SDRAM chip select 0 bar*/ +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + CS1_BAR, /* SDRAM chip select 1 bar*/ +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + CS2_BAR, /* SDRAM chip select 2 bar*/ +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + CS3_BAR, /* SDRAM chip select 3 bar*/ +#endif +#if defined(MV_INCLUDE_DEVICE_CS0) + DEVCS0_BAR, /* Device chip select 0 bar*/ +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEVCS1_BAR, /* Device chip select 1 bar*/ +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEVCS2_BAR, /* Device chip select 2 bar*/ +#endif + BOOTCS_BAR, /* Boot device chip select bar*/ + MEM_INTER_REGS_BAR, /* Memory Mapped Internal bar */ + IO_INTER_REGS_BAR, /* IO Mapped Internal bar */ + P2P_MEM0, /* P2P memory 0 */ + P2P_IO, /* P2P IO */ + PCI_MAX_BARS + +}MV_PCI_BAR; +#endif /* MV_ASMLANGUAGE */ + +#if defined(MV_INCLUDE_SDRAM_CS3) +#define MV_PCI_BAR_IS_DRAM_BAR(bar) \ + ((bar >= CS0_BAR) && (bar <= CS3_BAR)) +#elif defined(MV_INCLUDE_SDRAM_CS2) +#define MV_PCI_BAR_IS_DRAM_BAR(bar) \ + ((bar >= CS0_BAR) && (bar <= CS2_BAR)) +#elif defined(MV_INCLUDE_SDRAM_CS1) +#define MV_PCI_BAR_IS_DRAM_BAR(bar) \ + ((bar >= CS0_BAR) && (bar <= CS1_BAR)) +#elif defined(MV_INCLUDE_SDRAM_CS0) +#define MV_PCI_BAR_IS_DRAM_BAR(bar) \ + ((bar == CS0_BAR)) +#endif + + +/****************************************/ +/* PCI Slave Address Decoding registers */ +/****************************************/ +#define PCI_CS0_BAR_SIZE_REG(pciIf) (0x30c08 + ((pciIf) * 0x80)) +#define PCI_CS1_BAR_SIZE_REG(pciIf) (0x30d08 + ((pciIf) * 0x80)) +#define PCI_CS2_BAR_SIZE_REG(pciIf) (0x30c0c + ((pciIf) * 0x80)) +#define PCI_CS3_BAR_SIZE_REG(pciIf) (0x30d0c + ((pciIf) * 0x80)) +#define PCI_DEVCS0_BAR_SIZE_REG(pciIf) (0x30c10 + ((pciIf) * 0x80)) +#define PCI_DEVCS1_BAR_SIZE_REG(pciIf) (0x30d10 + ((pciIf) * 0x80)) +#define PCI_DEVCS2_BAR_SIZE_REG(pciIf) (0x30d18 + ((pciIf) * 0x80)) +#define PCI_BOOTCS_BAR_SIZE_REG(pciIf) (0x30d14 + ((pciIf) * 0x80)) +#define PCI_P2P_MEM0_BAR_SIZE_REG(pciIf) (0x30d1c + ((pciIf) * 0x80)) +#define PCI_P2P_IO_BAR_SIZE_REG(pciIf) (0x30d24 + ((pciIf) * 0x80)) +#define PCI_EXPAN_ROM_BAR_SIZE_REG(pciIf) (0x30d2c + ((pciIf) * 0x80)) +#define PCI_BASE_ADDR_ENABLE_REG(pciIf) (0x30c3c + ((pciIf) * 0x80)) +#define PCI_CS0_ADDR_REMAP_REG(pciIf) (0x30c48 + ((pciIf) * 0x80)) +#define PCI_CS1_ADDR_REMAP_REG(pciIf) (0x30d48 + ((pciIf) * 0x80)) +#define PCI_CS2_ADDR_REMAP_REG(pciIf) (0x30c4c + ((pciIf) * 0x80)) +#define PCI_CS3_ADDR_REMAP_REG(pciIf) (0x30d4c + ((pciIf) * 0x80)) +#define PCI_DEVCS0_ADDR_REMAP_REG(pciIf) (0x30c50 + ((pciIf) * 0x80)) +#define PCI_DEVCS1_ADDR_REMAP_REG(pciIf) (0x30d50 + ((pciIf) * 0x80)) +#define PCI_DEVCS2_ADDR_REMAP_REG(pciIf) (0x30d58 + ((pciIf) * 0x80)) +#define PCI_BOOTCS_ADDR_REMAP_REG(pciIf) (0x30d54 + ((pciIf) * 0x80)) +#define PCI_P2P_MEM0_ADDR_REMAP_LOW_REG(pciIf) (0x30d5c + ((pciIf) * 0x80)) +#define PCI_P2P_MEM0_ADDR_REMAP_HIGH_REG(pciIf) (0x30d60 + ((pciIf) * 0x80)) +#define PCI_P2P_IO_ADDR_REMAP_REG(pciIf) (0x30d6c + ((pciIf) * 0x80)) +#define PCI_EXPAN_ROM_ADDR_REMAP_REG(pciIf) (0x30f38 + ((pciIf) * 0x80)) +#define PCI_DRAM_BAR_BANK_SELECT_REG(pciIf) (0x30c1c + ((pciIf) * 0x80)) +#define PCI_ADDR_DECODE_CONTROL_REG(pciIf) (0x30d3c + ((pciIf) * 0x80)) + +/* PCI Bars Size Registers (PBSR) */ +#define PBSR_SIZE_OFFS 12 +#define PBSR_SIZE_MASK (0xfffff << PBSR_SIZE_OFFS) + +/* Base Address Registers Enable Register (BARER) */ +#define BARER_ENABLE(target) (1 << (target)) + +/* PCI Base Address Remap Registers (PBARR) */ +#define PBARR_REMAP_OFFS 12 +#define PBARR_REMAP_MASK (0xfffff << PBARR_REMAP_OFFS) +#define PBARR_REMAP_ALIGNMENT (1 << PBARR_REMAP_OFFS) + +/* PCI DRAM Bar Bank Select Register (PDBBSR) */ +#define PDBBSR_DRAM_BANK_OFFS(bank) ((bank) * 2) +#define PDBBSR_DRAM_BANK_MASK(bank) (0x3 << PDBBSR_DRAM_BANK_OFFS(bank)) + +/* PCI Address Decode Control Register (PADCR)*/ +#define PADCR_REMAP_REG_WR_DIS BIT0 +#define PADCR_MSG_REG_ACC BIT3 + +#define PADCR_VPD_HIGH_ADDR_OFFS 8 /* Bits [31:15] of the VPD address */ +#define PADCR_VPD_HIGH_ADDR_MASK (0x1ffff << PADCR_VPD_HIGH_ADDR_OFFS) + +/* PCI Headers Retarget Control Register (PHRCR) */ +#define PHRCR_ENABLE BIT0 +#define PHRCR_BUFF_SIZE_OFFS 1 +#define PHRCR_BUFF_SIZE_MASK (0x7 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_258BYTE (0x0 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_512BYTE (0x1 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_1KB (0x2 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_2KB (0x3 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_4KB (0x4 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_BUFF_SIZE_8KB (0x5 << PHRCR_BUFF_SIZE_OFFS) +#define PHRCR_MASK1_OFFS 16 +#define PHRCR_MASK1_MASK (0xffff << PHRCR_MASK1_OFFS) + +/* PCI Headers Retarget Base Register (PHRBR) */ +#define PHRBR_BASE_OFFS 16 +#define PHRBR_BASE_MASK (0xffff << PHRBR_BASE_OFFS) + +/* PCI Headers Retarget Base High Register (PHRBHR) */ +#define PHRBHR_BASE_OFFS 0 +#define PHRBHR_BASE_MASK (0xffffffff << PHRBHR_BASE_OFFS) + +/* This structure describes a PCI BAR. It is also refered as PCI target */ +/* window to keep consistency with other address decode units in the system */ +typedef struct _mvPciBarWin +{ + MV_ADDR_WIN addrWin; /* Address window */ + MV_BOOL enable; /* BAR enable/disable */ +}MV_PCI_BAR_WIN; + +/* This structure describes PCI region attributes */ +typedef struct _mvPciRegionAttr +{ + MV_PROT_RIGHT access; /* Access protection */ + MV_PROT_RIGHT write; /* Write protection */ + MV_SWAP_TYPE swapType; /* Data swap mode for that region */ + MV_U32 readMaxBurst; /* Read max burst */ + MV_U32 readBurst; /* Read burst. Conventional PCI only */ + MV_U32 writeMaxBurst; /* Write max burst */ + MV_BOOL pciOrder; /* Hardware support for PCI ordering */ +}MV_PCI_REGION_ATTR; + +/* The PCI slave interface supports configurable access control. */ +/* It is possible to define up to six address ranges to different */ +/* configurations. This structure describes the PCI access region */ +typedef struct _mvPciProtWin +{ + MV_ADDR_WIN addrWin; /* An address window */ + MV_PCI_REGION_ATTR attributes; /* Window attributes */ + MV_BOOL enable; /* Window enabled/disabled */ +}MV_PCI_PROT_WIN; + +/* Global Functions prototypes */ + +/* mvPciInit - Initialize PCI interfaces*/ +MV_STATUS mvPciInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); + +/* mvPciTargetWinSet - Set PCI to peripheral target address window BAR*/ +MV_STATUS mvPciTargetWinSet(MV_U32 pciIf, MV_PCI_BAR slaveTarget, + MV_PCI_BAR_WIN *pAddrBarWin); + +/* mvPciTargetWinGet - Get PCI to peripheral target address window*/ +MV_STATUS mvPciTargetWinGet(MV_U32 pciIf, MV_PCI_BAR slaveTarget, + MV_PCI_BAR_WIN *pAddrBarWin); + +/* mvPciTargetWinEnable - Enable/disable a PCI BAR window*/ +MV_STATUS mvPciTargetWinEnable(MV_U32 pciIf,MV_PCI_BAR slaveTarget, + MV_BOOL enable); + +/* mvPciProtWinSet - Set PCI protection access window*/ +MV_STATUS mvPciProtWinSet(MV_U32 pciIf, MV_U32 winNum, + MV_PCI_PROT_WIN *pProtWin); + +/* mvPciProtWinGet - Get PCI protection access window*/ +MV_STATUS mvPciProtWinGet(MV_U32 pciIf, + MV_U32 winNum, + MV_PCI_PROT_WIN *pProtWin); + +/* mvPciProtWinEnable - Get PCI protection access window*/ +MV_STATUS mvPciProtWinEnable(MV_U32 pciIf, MV_U32 winNum, MV_BOOL enable); + +/* mvPciTargetRemap - Set PCI to target address window remap.*/ +MV_STATUS mvPciTargetRemap(MV_U32 pciIf, MV_PCI_BAR slaveTarget, + MV_ADDR_WIN *pAddrWin); + +/* mvPciAddrDecShow - Display address decode windows attributes */ +MV_VOID mvPciAddrDecShow(MV_VOID); + +#endif diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPex.c b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPex.c new file mode 100644 index 0000000..fd5a9e0 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPex.c @@ -0,0 +1,1696 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/sys/mvSysPex.h" + +/* this structure describes the mapping between a Pex Window and a CPU target*/ +typedef struct _pexWinToTarget +{ + MV_TARGET target; + MV_BOOL enable; + +}PEX_WIN_TO_TARGET; + +/* this array is a priority array that define How Pex windows should be +configured , We have only 6 Pex Windows that can be configured , but we +have maximum of 9 CPU target windows ! the following array is a priority +array where the lowest index has the highest priotiy and the highest +index has the lowest priority of being cnfigured */ + +MV_U32 pexDevBarPrioTable[] = +{ +#if defined(MV_INCLUDE_DEVICE_CS0) + DEVICE_CS0, +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEVICE_CS1, +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEVICE_CS2, +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEVICE_CS3, +#endif +/* +#if defined(MV_INCLUDE_DEVICE_CS4) + DEVICE_CS4, +#endif +*/ + TBL_TERM +}; + + +/* PEX Wins registers offsets are inconsecutive. This struct describes WIN */ +/* register offsets and its function where its is located. */ +/* Also, PEX address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _pexWinRegInfo +{ + MV_U32 baseLowRegOffs; + MV_U32 baseHighRegOffs; + MV_U32 sizeRegOffs; + MV_U32 remapLowRegOffs; + MV_U32 remapHighRegOffs; + +}PEX_WIN_REG_INFO; + +static MV_STATUS pexWinOverlapDetect(MV_U32 pexIf, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin); +static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, MV_U32 winNum, + PEX_WIN_REG_INFO *pWinRegInfo); +const MV_8* pexBarNameGet( MV_U32 bar ); + +static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size); + +static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf,MV_ADDR_WIN *pAddrWin); +static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf,MV_U32 barNum, + MV_ADDR_WIN *pAddrWin); + +/******************************************************************************* +* mvPexInit - Initialize PEX interfaces +* +* DESCRIPTION: +* +* This function is responsible of intialization of the Pex Interface , It +* configure the Pex Bars and Windows in the following manner: +* +* Assumptions : +* Bar0 is always internal registers bar +* Bar1 is always the DRAM bar +* Bar2 is always the Device bar +* +* 1) Sets the Internal registers bar base by obtaining the base from +* the CPU Interface +* 2) Sets the DRAM bar base and size by getting the base and size from +* the CPU Interface when the size is the sum of all enabled DRAM +* chip selects and the base is the base of CS0 . +* 3) Sets the Device bar base and size by getting these values from the +* CPU Interface when the base is the base of the lowest base of the +* Device chip selects, and the +* +* +* INPUT: +* +* pexIf - PEX interface number. +* +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM +* +*******************************************************************************/ +MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType) +{ + MV_U32 bar; + MV_U32 winNum; + MV_PEX_BAR pexBar; + MV_PEX_DEC_WIN pexWin; + MV_CPU_DEC_WIN addrDecWin; + MV_TARGET target; + MV_U32 pexCurrWin=0; + MV_U32 status; + /* default and exapntion rom + are always configured */ + +#ifndef MV_DISABLE_PEX_DEVICE_BAR + MV_U32 winIndex; + MV_U32 maxBase=0, sizeOfMaxBase=0; + MV_U32 pexStartWindow; +#endif + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + /* Enabled CPU access to PCI-Express */ + mvCpuIfEnablePex(pexIf, pexType); + + /* Start with bars */ + /* First disable all PEX bars*/ + for (bar = 0; bar < PEX_MAX_BARS; bar++) + { + if (PEX_INTER_REGS_BAR != bar) + { + if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) + { + mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); + return MV_ERROR; + } + + } + + } + + /* and disable all PEX target windows */ + for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) + { + mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", + winNum); + return MV_ERROR; + + } + } + + /* Now, go through all bars*/ + + + +/******************************************************************************/ +/* Internal registers bar */ +/******************************************************************************/ + bar = PEX_INTER_REGS_BAR; + + /* we only open the bar , no need to open windows for this bar */ + + /* first get the CS attribute from the CPU Interface */ + if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) + { + mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); + return MV_ERROR; + } + + pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexBar.addrWin.size = addrDecWin.addrWin.size; + pexBar.enable = MV_TRUE; + + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + +/******************************************************************************/ +/* DRAM bar */ +/******************************************************************************/ + + bar = PEX_DRAM_BAR; + + pexBar.addrWin.size = 0; + + for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) + { + + status = mvCpuIfTargetWinGet(target,&addrDecWin); + + if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) + { + continue; + } + + /* first get attributes from CPU If */ + if (MV_OK != status) + { + mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); + return MV_ERROR; + } + if (addrDecWin.enable == MV_TRUE) + { + /* the base is the base of DRAM CS0 always */ + if (SDRAM_CS0 == target ) + { + pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + + } + + /* increment the bar size to be the sum of the size of all + DRAM chips selecs */ + pexBar.addrWin.size += addrDecWin.addrWin.size; + + /* set a Pex window for this target ! + DRAM CS always will have a Pex Window , and is not a + part of the priority table */ + pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexWin.addrWin.size = addrDecWin.addrWin.size; + + /* we disable the windows at first because we are not + sure that it is witihin bar boundries */ + pexWin.enable =MV_FALSE; + pexWin.target = target; + pexWin.targetBar = bar; + + if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) + { + mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); + return MV_ERROR; + } + } + } + + /* check if the size of the bar is illeggal */ + if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) + { + /* try to get a good size */ + pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, + PXBCR_BAR_SIZE_ALIGNMENT); + } + + /* check if the size and base are valid */ + if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) + { + mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); + mvOsPrintf("it will be disabled\n"); + mvOsPrintf("please check Pex and CPU windows configuration\n"); + } + else + { + pexBar.enable = MV_TRUE; + + /* configure the bar */ + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + + /* after the bar was configured then we enable the Pex windows*/ + for (winNum = 0;winNum < pexCurrWin ;winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) + { + mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); + return MV_ERROR; + } + + } + } + +/******************************************************************************/ +/* DEVICE bar */ +/******************************************************************************/ + +/* Open the Device BAR for non linux only */ +#ifndef MV_DISABLE_PEX_DEVICE_BAR + + /* then device bar*/ + bar = PEX_DEVICE_BAR; + + /* save the starting window */ + pexStartWindow = pexCurrWin; + pexBar.addrWin.size = 0; + pexBar.addrWin.baseLow = 0xffffffff; + pexBar.addrWin.baseHigh = 0; + maxBase = 0; + + for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) + { + status = mvCpuIfTargetWinGet(target,&addrDecWin); + + if (MV_NO_SUCH == status) + { + continue; + } + + if (MV_OK != status) + { + mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); + return MV_ERROR; + } + + if (addrDecWin.enable == MV_TRUE) + { + /* get the minimum base */ + if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) + { + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + } + + /* get the maximum base */ + if (addrDecWin.addrWin.baseLow > maxBase) + { + maxBase = addrDecWin.addrWin.baseLow; + sizeOfMaxBase = addrDecWin.addrWin.size; + } + + /* search in the priority table for this target */ + for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; + winIndex++) + { + if (pexDevBarPrioTable[winIndex] != target) + { + continue; + } + else if (pexDevBarPrioTable[winIndex] == target) + { + /*found it */ + + /* if the index of this target in the prio table is valid + then we set the Pex window for this target, a valid index is + an index that is lower than the number of the windows that + was not configured yet */ + + /* we subtract 2 always because the default and expantion + rom windows are always configured */ + if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) + { + /* set a Pex window for this target ! */ + pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexWin.addrWin.size = addrDecWin.addrWin.size; + + /* we disable the windows at first because we are not + sure that it is witihin bar boundries */ + pexWin.enable = MV_FALSE; + pexWin.target = target; + pexWin.targetBar = bar; + + if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, + &pexWin)) + { + mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); + return MV_ERROR; + } + } + } + } + } + } + + pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; + pexBar.enable = MV_TRUE; + + /* check if the size of the bar is illegal */ + if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) + { + /* try to get a good size */ + pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, + PXBCR_BAR_SIZE_ALIGNMENT); + } + + /* check if the size and base are valid */ + if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) + { + mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); + mvOsPrintf("it will be disabled\n"); + mvOsPrintf("please check Pex and CPU windows configuration\n"); + } + else + { + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + + /* now enable the windows */ + for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) + { + mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", + winNum); + return MV_ERROR; + } + } + } + +#endif + + return mvPexHalInit(pexIf, pexType); + +} + +/******************************************************************************* +* mvPexTargetWinSet - Set PEX to peripheral target address window BAR +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if PEX BAR target window was set correctly, +* MV_BAD_PARAM on bad params +* MV_ERROR otherwise +* (e.g. address window overlapps with other active PEX target window). +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin) +{ + + MV_DEC_REGS decRegs; + PEX_WIN_REG_INFO winRegInfo; + MV_TARGET_ATTRIB targetAttribs; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf,winNum,&winRegInfo); + + + if (MV_TRUE == pAddrDecWin->enable) + { + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); + return MV_BAD_PARAM; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) + { + mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", + winNum); + return MV_BAD_PARAM; + } + + } + + + + /* read base register*/ + + if (winRegInfo.baseLowRegOffs) + { + decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); + } + else + { + decRegs.baseReg = 0; + } + + if (winRegInfo.sizeRegOffs) + { + decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); + } + else + { + decRegs.sizeReg =0; + } + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + /* enable\Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + decRegs.sizeReg |= PXWCR_WIN_EN; + } + else + { + decRegs.sizeReg &= ~PXWCR_WIN_EN; + } + + + /* clear bit location */ + decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; + + /* set bar Mapping */ + if (pAddrDecWin->targetBar == 1) + { + decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; + } + else if (pAddrDecWin->targetBar == 2) + { + decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; + decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; + /* set target ID */ + decRegs.sizeReg &= ~PXWCR_TARGET_MASK; + decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; + + + /* 3) Write to address decode Base Address Register */ + + if (winRegInfo.baseLowRegOffs) + { + MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); + } + + /* write size reg */ + if (winRegInfo.sizeRegOffs) + { + if ((MV_PEX_WIN_DEFAULT == winNum)|| + (MV_PEX_WIN_EXP_ROM == winNum)) + { + /* clear size because there is no size field*/ + decRegs.sizeReg &= ~PXWCR_SIZE_MASK; + + /* clear enable because there is no enable field*/ + decRegs.sizeReg &= ~PXWCR_WIN_EN; + + } + + MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); + } + + + return MV_OK; + +} + +/******************************************************************************* +* mvPexTargetWinGet - Get PEX to peripheral target address window +* +* DESCRIPTION: +* Get the PEX to peripheral target address window BAR. +* +* INPUT: +* pexIf - PEX interface number. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* pAddrBarWin - PEX target window information data structure. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttrib; + MV_DEC_REGS decRegs; + + PEX_WIN_REG_INFO winRegInfo; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf,winNum,&winRegInfo); + + /* read base register*/ + if (winRegInfo.baseLowRegOffs) + { + decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); + } + else + { + decRegs.baseReg = 0; + } + + /* read size reg */ + if (winRegInfo.sizeRegOffs) + { + decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); + } + else + { + decRegs.sizeReg =0; + } + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + + } + + if (decRegs.sizeReg & PXWCR_WIN_EN) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + + } + + + #if 0 + if (-1 == pAddrDecWin->addrWin.size) + { + return MV_ERROR; + } + #endif + + + /* get target bar */ + if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) + { + pAddrDecWin->targetBar = 1; + } + else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == + PXWCR_WIN_BAR_MAP_BAR2 ) + { + pAddrDecWin->targetBar = 2; + } + + /* attrib and targetId */ + pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> + PXWCR_ATTRIB_OFFS; + pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> + PXWCR_TARGET_OFFS; + + targetAttrib.attrib = pAddrDecWin->attrib; + targetAttrib.targetId = pAddrDecWin->targetId; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; + +} + + +/******************************************************************************* +* mvPexTargetWinEnable - Enable/disable a PEX BAR window +* +* DESCRIPTION: +* This function enable/disable a PEX BAR window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling PEX accesses for that BAR (before enabling the +* window it is tested for overlapping). Otherwise, the window will +* be disabled. +* +* INPUT: +* pexIf - PEX interface number. +* bar - BAR to be accessed by slave. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) +{ + PEX_WIN_REG_INFO winRegInfo; + MV_PEX_DEC_WIN addrDecWin; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); + return MV_BAD_PARAM; + } + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf,winNum,&winRegInfo); + + + /* if the address windows is disabled , we only disable the appropriare + pex window and ignore other settings */ + + if (MV_FALSE == enable) + { + + /* this is not relevant to default and expantion rom + windows */ + if (winRegInfo.sizeRegOffs) + { + if ((MV_PEX_WIN_DEFAULT != winNum)&& + (MV_PEX_WIN_EXP_ROM != winNum)) + { + MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); + } + } + + } + else + { + if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) + { + mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); + return MV_ERROR; + } + + /* Check if the requested window overlaps with current windows */ + if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) + { + mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); + return MV_BAD_PARAM; + } + + if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) + { + mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", + winNum); + return MV_BAD_PARAM; + } + + + /* this is not relevant to default and expantion rom + windows */ + if (winRegInfo.sizeRegOffs) + { + if ((MV_PEX_WIN_DEFAULT != winNum)&& + (MV_PEX_WIN_EXP_ROM != winNum)) + { + MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); + } + } + + + } + + return MV_OK; + +} + + + +/******************************************************************************* +* mvPexTargetWinRemap - Set PEX to target address window remap. +* +* DESCRIPTION: +* The PEX interface supports remap of the BAR original address window. +* For each BAR it is possible to define a remap address. For example +* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified +* according to remap register but will also be targeted to the +* SDRAM CS[0]. +* +* INPUT: +* pexIf - PEX interface number. +* bar - Peripheral target enumerator accessed by slave. +* pAddrWin - Address window to be checked. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_REMAP_WIN *pAddrWin) +{ + + PEX_WIN_REG_INFO winRegInfo; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", + pexIf); + return MV_BAD_PARAM; + } + if (MV_PEX_WIN_DEFAULT == winNum) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", + winNum); + return MV_BAD_PARAM; + + } + + if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) + { + mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + pexIf, + winNum, + pAddrWin->addrWin.baseLow, + pAddrWin->addrWin.size); + + return MV_ERROR; + } + + pexWinRegInfoGet(pexIf, winNum, &winRegInfo); + + /* Set remap low register value */ + MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); + + /* Skip base high settings if the BAR has only base low (32-bit) */ + if (0 != winRegInfo.remapHighRegOffs) + { + MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); + } + + + if (pAddrWin->enable == MV_TRUE) + { + MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + else + { + MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* mvPexTargetWinRemapEnable - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + +MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, + MV_BOOL enable) +{ + PEX_WIN_REG_INFO winRegInfo; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", + pexIf); + return MV_BAD_PARAM; + } + if (MV_PEX_WIN_DEFAULT == winNum) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", + winNum); + return MV_BAD_PARAM; + + } + + + pexWinRegInfoGet(pexIf, winNum, &winRegInfo); + + if (enable == MV_TRUE) + { + MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + else + { + MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + + return MV_OK; + +} + +/******************************************************************************* +* mvPexBarSet - Set PEX bar address and size +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexBarSet(MV_U32 pexIf, + MV_U32 barNum, + MV_PEX_BAR *pAddrWin) +{ + MV_U32 regBaseLow; + MV_U32 regSize,sizeToReg; + + + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + + if (pAddrWin->addrWin.size == 0) + { + mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); + return MV_BAD_PARAM; + } + + + /* Check if the window complies with PEX spec */ + if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, + pAddrWin->addrWin.size)) + { + mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); + return MV_BAD_PARAM; + } + + /* 2) Check if the requested bar overlaps with current bars */ + if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) + { + mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); + return MV_BAD_PARAM; + } + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); + + /* Read bar size */ + if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ + { + regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); + return MV_BAD_PARAM; + } + + regSize &= ~PXBCR_BAR_SIZE_MASK; + regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; + + MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); + + } + + /* set size */ + + + + /* Read base address low */ + regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, + PEX_MV_BAR_BASE(barNum))); + + /* clear current base */ + if (PEX_INTER_REGS_BAR == barNum) + { + regBaseLow &= ~PXBIR_BASE_MASK; + regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); + } + else + { + regBaseLow &= ~PXBR_BASE_MASK; + regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); + } + + /* if we had a previous value that contain the bar type (MeM\IO), we want to + restore it */ + regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; + + + + /* write base low */ + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), + regBaseLow); + + if (pAddrWin->addrWin.baseHigh != 0) + { + /* Read base address high */ + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), + pAddrWin->addrWin.baseHigh); + + } + + /* lastly enable the Bar */ + if (pAddrWin->enable == MV_TRUE) + { + if (PEX_INTER_REGS_BAR != barNum) /* internal registers + are enabled always */ + { + MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + } + } + else if (MV_FALSE == pAddrWin->enable) + { + if (PEX_INTER_REGS_BAR != barNum) /* internal registers + are enabled always */ + { + MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + } + + } + + + + return MV_OK; +} + + +/******************************************************************************* +* mvPexBarGet - Get PEX bar address and size +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + +MV_STATUS mvPexBarGet(MV_U32 pexIf, + MV_U32 barNum, + MV_PEX_BAR *pAddrWin) +{ + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + /* read base low */ + pAddrWin->addrWin.baseLow = + MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); + + + if (PEX_INTER_REGS_BAR == barNum) + { + pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; + } + else + { + pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; + } + + + /* read base high */ + pAddrWin->addrWin.baseHigh = + MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); + + + /* Read bar size */ + if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ + { + pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); + + /* check if enable or not */ + if (pAddrWin->addrWin.size & PXBCR_BAR_EN) + { + pAddrWin->enable = MV_TRUE; + } + else + { + pAddrWin->enable = MV_FALSE; + } + + /* now get the size */ + pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; + pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; + + pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, + PXBCR_BAR_SIZE_ALIGNMENT); + + } + else /* PEX_INTER_REGS_BAR */ + { + pAddrWin->addrWin.size = INTER_REGS_SIZE; + pAddrWin->enable = MV_TRUE; + } + + + return MV_OK; +} + +/******************************************************************************* +* mvPexBarEnable - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + + +MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) +{ + + MV_PEX_BAR pexBar; + + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + if (PEX_INTER_REGS_BAR == barNum) + { + if (MV_TRUE == enable) + { + return MV_OK; + } + else + { + return MV_ERROR; + } + } + + + if (MV_FALSE == enable) + { + /* disable bar and quit */ + MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + return MV_OK; + } + + /* else */ + + if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) + { + mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); + return MV_ERROR; + + } + + if (MV_TRUE == pexBar.enable) + { + /* it is already enabled !!! */ + return MV_OK; + } + + /* else enable the bar*/ + + pexBar.enable = MV_TRUE; + + if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) + { + mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); + return MV_ERROR; + + } + + return MV_OK; +} + + +/******************************************************************************* +* pexWinOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PEX BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, + MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 win; + MV_PEX_DEC_WIN addrDecWin; + + + for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) + { + /* don't check our target or illegal targets */ + if (winNum == win) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) + { + mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", + win); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", + winNum, win); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* pexIsWinWithinBar - Detect if address is within PEX bar boundries +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 bar; + MV_PEX_BAR addrDecWin; + + for(bar = 0; bar < PEX_MAX_BARS; bar++) + { + + /* Get window parameters */ + if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) + { + mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled bars */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + + if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) + { + return MV_TRUE; + } + } + + return MV_FALSE; + +} + +/******************************************************************************* +* pexBarOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PEX BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, + MV_U32 barNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 bar; + MV_PEX_BAR barDecWin; + + + for(bar = 0; bar < PEX_MAX_BARS; bar++) + { + /* don't check our target or illegal targets */ + if (barNum == bar) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) + { + mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* don'nt check disabled bars */ + if (barDecWin.enable == MV_FALSE) + { + continue; + } + + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) + { + mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", + barNum, bar); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* pexBarIsValid - Check if the given address window is valid +* +* DESCRIPTION: +* PEX spec restrict BAR base to be aligned to BAR size. +* This function checks if the given address window is valid. +* +* INPUT: +* baseLow - 32bit low base address. +* size - Window size. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the address window is valid, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) +{ + + /* PCI spec restrict BAR base to be aligned to BAR size */ + if(MV_IS_NOT_ALIGN(baseLow, size)) + { + return MV_ERROR; + } + else + { + return MV_TRUE; + } + + return MV_TRUE; +} + +/******************************************************************************* +* pexBarRegInfoGet - Get BAR register information +* +* DESCRIPTION: +* PEX BARs registers offsets are inconsecutive. +* This function gets a PEX BAR register information like register offsets +* and function location of the BAR. +* +* INPUT: +* pexIf - PEX interface number. +* bar - The PEX BAR in question. +* +* OUTPUT: +* pBarRegInfo - BAR register info struct. +* +* RETURN: +* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK +* +*******************************************************************************/ +static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, + MV_U32 winNum, + PEX_WIN_REG_INFO *pWinRegInfo) +{ + + if ((winNum >= 0)&&(winNum <=3)) + { + pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); + pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); + pWinRegInfo->remapHighRegOffs = 0; + } + else if ((winNum >= 4)&&(winNum <=5)) + { + pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); + pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); + pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); + + } + else if (MV_PEX_WIN_DEFAULT == winNum) + { + pWinRegInfo->baseLowRegOffs = 0; + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); + pWinRegInfo->remapLowRegOffs = 0; + pWinRegInfo->remapHighRegOffs = 0; + } + else if (MV_PEX_WIN_EXP_ROM == winNum) + { + pWinRegInfo->baseLowRegOffs = 0; + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); + pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); + pWinRegInfo->remapHighRegOffs = 0; + + } + + return MV_OK; +} + +/******************************************************************************* +* pexBarNameGet - Get the string name of PEX BAR. +* +* DESCRIPTION: +* This function get the string name of PEX BAR. +* +* INPUT: +* bar - PEX bar number. +* +* OUTPUT: +* None. +* +* RETURN: +* pointer to the string name of PEX BAR. +* +*******************************************************************************/ +const MV_8* pexBarNameGet( MV_U32 bar ) +{ + switch( bar ) + { + case PEX_INTER_REGS_BAR: + return "Internal Regs Bar0...."; + case PEX_DRAM_BAR: + return "DRAM Bar1............."; + case PEX_DEVICE_BAR: + return "Devices Bar2.........."; + default: + return "Bar unknown"; + } +} +/******************************************************************************* +* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). +* +* DESCRIPTION: +* This function print the PEX address decode map (BARs and windows). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvPexAddrDecShow(MV_VOID) +{ + MV_PEX_BAR pexBar; + MV_PEX_DEC_WIN win; + MV_U32 pexIf; + MV_U32 bar,winNum; + + for( pexIf = MV_PEX_START_IF; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) + { + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; + mvOsOutput( "\n" ); + mvOsOutput( "PEX%d:\n", pexIf ); + mvOsOutput( "-----\n" ); + + mvOsOutput( "\nPex Bars \n\n"); + + for( bar = 0; bar < PEX_MAX_BARS; bar++ ) + { + memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); + + mvOsOutput( "%s ", pexBarNameGet(bar) ); + + if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) + { + if( pexBar.enable ) + { + mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); + mvSizePrint( pexBar.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } + mvOsOutput( "\nPex Decode Windows\n\n"); + + for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) + { + memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "win%d - ", winNum ); + + if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) + { + if (win.enable) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + + + } + } + + memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "default win - " ); + + if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) + { + mvOsOutput( "%s ", + mvCtrlTargetNameGet(win.target) ); + mvOsOutput( "\n" ); + } + memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "Expansion ROM - " ); + + if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) + { + mvOsOutput( "%s ", + mvCtrlTargetNameGet(win.target) ); + mvOsOutput( "\n" ); + } + + } +} + + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPex.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPex.h new file mode 100644 index 0000000..3505613 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysPex.h @@ -0,0 +1,348 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCSysPEXH +#define __INCSysPEXH + +#include "mvCommon.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* 4KB granularity */ +#define MINIMUM_WINDOW_SIZE 0x1000 +#define MINIMUM_BAR_SIZE 0x1000 +#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 +#define BAR_SIZE_OFFS 12 +#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) + + + +#define MV_PEX_WIN_DEFAULT 6 +#define MV_PEX_WIN_EXP_ROM 7 +#define PEX_MAX_TARGET_WIN 8 + + +#define PEX_MAX_BARS 3 +#define PEX_INTER_REGS_BAR 0 +#define PEX_DRAM_BAR 1 +#define PEX_DEVICE_BAR 2 + +/*************************************/ +/* PCI Express BAR Control Registers */ +/*************************************/ +#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) +#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) + + +/* PCI Express BAR Control Register */ +/* PEX_BAR_CTRL_REG (PXBCR) */ + +#define PXBCR_BAR_EN BIT0 +#define PXBCR_BAR_SIZE_OFFS 16 +#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) +#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 + + + +/* PCI Express Expansion ROM BAR Control Register */ +/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ + +#define PXERBCR_EXPROM_EN BIT0 +#define PXERBCR_EXPROMSZ_OFFS 19 +#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) + +/************************************************/ +/* PCI Express Address Window Control Registers */ +/************************************************/ +#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ + (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) +#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ + (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) +#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ + (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) +#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ + (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) +#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ + (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) +#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ + (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) +#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ + (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) + +#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) +#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) +#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) + +/* PCI Express Window Control Register */ +/* PEX_WIN_CTRL_REG (PXWCR) */ + +#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ + +#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ +#define PXWCR_WIN_BAR_MAP_MASK BIT1 +#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) +#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) + +#define PXWCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) + +#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) + +#define PXWCR_SIZE_OFFS 16 /* size */ +#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) +#define PXWCR_SIZE_ALIGNMENT 0x10000 + +/* PCI Express Window Base Register */ +/* PEX_WIN_BASE_REG (PXWBR)*/ + +#define PXWBR_BASE_OFFS 16 /* address[31:16] */ +#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) +#define PXWBR_BASE_ALIGNMENT 0x10000 + +/* PCI Express Window Remap Register */ +/* PEX_WIN_REMAP_REG (PXWRR)*/ + +#define PXWRR_REMAP_EN BIT0 +#define PXWRR_REMAP_OFFS 16 +#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) +#define PXWRR_REMAP_ALIGNMENT 0x10000 + +/* PCI Express Window Remap (High) Register */ +/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ + +#define PXWRHR_REMAP_HIGH_OFFS 0 +#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) + +/* PCI Express Default Window Control Register */ +/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ + +#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) +#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) + +/* PCI Express Expansion ROM Window Control Register */ +/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ + +#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) +#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) + +/* PCI Express Expansion ROM Window Remap Register */ +/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ + +#define PXWERRR_REMAP_EN BIT0 +#define PXWERRR_REMAP_OFFS 16 +#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) +#define PXWERRR_REMAP_ALIGNMENT 0x10000 + + + +/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ +/* PCI Express BAR0 Internal Register*/ +/*PEX BAR0_INTER_REG (PXBIR)*/ + +#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ + +#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) +#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) +#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) + +#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ + +#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ +#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) +#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) + + +/* PCI Express BAR0 Internal (High) Register*/ +/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ + +#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ +#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) + + +#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ +#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB +#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB +#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB + + +/* PCI Express BAR1 Register */ +/* PCI Express BAR2 Register*/ +/*PEX BAR1_REG (PXBR)*/ +/*PEX BAR2_REG (PXBR)*/ + +#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ + +#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) +#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) +#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) + +#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ + +#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ +#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) +#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) + + +/* PCI Express BAR1 (High) Register*/ +/* PCI Express BAR2 (High) Register*/ +/*PEX BAR1_REG_HIGH (PXBRH)*/ +/*PEX BAR2_REG_HIGH (PXBRH)*/ + +#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ +#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) + +/* PCI Express Expansion ROM BAR Register*/ +/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ + +#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ + +#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) + +#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) + +#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) + +#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) + +/* PEX Bar attributes */ +typedef struct _mvPexBar +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_PEX_BAR; + +/* PEX Remap Window attributes */ +typedef struct _mvPexRemapWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_PEX_REMAP_WIN; + +/* PEX Remap Window attributes */ +typedef struct _mvPexDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_U32 targetBar; + MV_U8 attrib; /* chip select attributes */ + MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_PEX_DEC_WIN; + +/* Global Functions prototypes */ +/* mvPexHalInit - Initialize PEX interfaces*/ +MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); + + +/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ +MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin); + +/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ +MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin); + +/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ +MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); + +/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ +MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_REMAP_WIN *pAddrWin); + +/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ +MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, + MV_BOOL enable); + +/* mvPexBarSet - Set PEX bar address and size */ +MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); + +/* mvPexBarGet - Get PEX bar address and size */ +MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); + +/* mvPexBarEnable - enable\disable a PEX bar*/ +MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); + +/* mvPexAddrDecShow - Display address decode windows attributes */ +MV_VOID mvPexAddrDecShow(MV_VOID); + +#endif diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysSata.c b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysSata.c new file mode 100644 index 0000000..082cb4b --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysSata.c @@ -0,0 +1,427 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "sata/CoreDriver/mvRegs.h" +#include "ctrlEnv/sys/mvSysSata.h" + +MV_TARGET sataAddrDecPrioTab[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif +#if defined(MV_INCLUDE_PCI) + PCI0_MEM, +#endif + TBL_TERM +}; + + +/******************************************************************************* +* sataWinOverlapDetect - Detect SATA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case SATA address decode +* windows overlapps. +* This function detects SATA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_SATA_DEC_WIN addrDecWin; + + for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = 0; + decRegs.sizeReg = 0; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; + decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); + + /* set target ID */ + decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; + decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); + + if (pAddrDecWin->enable == MV_TRUE) + { + decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; + } + else + { + decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; + } + + MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); + MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvSataWinGet - Get SATA peripheral target address window. +* +* DESCRIPTION: +* Get SATA peripheral target address window. +* +* INPUT: +* winNum - SATA target address decode window number. +* +* OUTPUT: +* pAddrDecWin - SATA target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", + __FUNCTION__, dev, winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); + decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) + { + mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> + MV_SATA_WIN_ATTR_OFFSET; + targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> + MV_SATA_WIN_TARGET_OFFSET; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + return MV_OK; +} +/******************************************************************************* +* mvSataAddrDecShow - Print the SATA address decode map. +* +* DESCRIPTION: +* This function print the SATA address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvSataAddrDecShow(MV_VOID) +{ + + MV_SATA_DEC_WIN win; + int i; + + if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, 0)) return; + + mvOsOutput( "\n" ); + mvOsOutput( "SATA:\n" ); + mvOsOutput( "----\n" ); + + for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvSataWinGet(0, i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + + +/******************************************************************************* +* mvSataWinInit - Initialize the integrated SATA target address window. +* +* DESCRIPTION: +* Initialize the SATA peripheral target address window. +* +* INPUT: +* +* +* OUTPUT: +* +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSataWinInit(MV_VOID) +{ + int winNum; + MV_SATA_DEC_WIN sataWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 status, winPrioIndex = 0; + + /* Initiate Sata address decode */ + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); + regVal &= ~MV_SATA_WIN_ENABLE_MASK; + MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); + } + + winNum = 0; + while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && + (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) + { + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], + &cpuAddrDecWin); + + if(MV_NO_SUCH == status) + { + winPrioIndex++; + continue; + } + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; + sataWin.enable = MV_TRUE; + sataWin.target = sataAddrDecPrioTab[winPrioIndex]; + + if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) + { + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} + + + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysSata.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysSata.h new file mode 100644 index 0000000..325fb8d --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysSata.h @@ -0,0 +1,128 @@ + +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCMVSysSataAddrDech +#define __INCMVSysSataAddrDech + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct _mvSataDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +} MV_SATA_DEC_WIN; + + +#define MV_SATA_MAX_ADDR_DECODE_WIN 4 + +#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) +#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) + +/* BITs in Bridge Interrupt Cause and Mask registers */ +#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 +#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); + decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* for the safe side we disable the window before writing the new + values */ + mvTdmWinEnable(winNum, MV_FALSE); + + ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); + ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); + ctrlReg |= (decRegs.sizeReg << TDM_WIN_SIZE_OFFS); + + /* Write to address base and control registers */ + MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); + MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + { + mvTdmWinEnable(winNum, MV_TRUE); + } + return MV_OK; +} + +/******************************************************************************* +* mvTdmWinGet - Get peripheral target address window. +* +* DESCRIPTION: +* Get TDM peripheral target address window. +* +* INPUT: +* winNum - TDM to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - TDM target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ + +MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) +{ + + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); + decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; + targetAttrib.targetId = + (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvTdmWinEnable - Enable/disable a TDM to target address window +* +* DESCRIPTION: +* This function enable/disable a TDM to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling TDM accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - TDM to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) +{ + MV_TDM_DEC_WIN addrDecWin; + + if (MV_TRUE == enable) + { + if (winNum >= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) + { + mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); + } + else + { /* Overlap detected */ + mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { + MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); + } + return MV_OK; +} + + +/******************************************************************************* +* tdmWinOverlapDetect - Detect TDM address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviour is expected in case TDM address decode +* windows overlapps. +* This function detects TDM address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_TDM_DEC_WIN addrDecWin; + + for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) + { + /* Do not check window itself */ + if (winNumIndex == winNum) + { + continue; + } + /* Do not check disabled windows */ + if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) + { + /* Get window parameters */ + if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) + { + DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + } + return MV_FALSE; +} + +/******************************************************************************* +* mvTdmAddrDecShow - Print the TDM address decode map. +* +* DESCRIPTION: +* This function print the TDM address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvTdmAddrDecShow(MV_VOID) +{ + MV_TDM_DEC_WIN win; + int i; + + mvOsOutput( "\n" ); + mvOsOutput( "TDM:\n" ); + mvOsOutput( "----\n" ); + + for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if (mvTdmWinGet(i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); + mvOsOutput( "...." ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysTdm.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysTdm.h new file mode 100644 index 0000000..596c6c3 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysTdm.h @@ -0,0 +1,92 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSysTdmh +#define __INCmvSysTdmh + +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#define TDM_MBUS_MAX_WIN 4 +#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE +0x4030) + (win<<4)) +#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) + +/* TDM_WIN_CTRL_REG bits */ +#define TDM_WIN_ENABLE_OFFS 0 +#define TDM_WIN_ENABLE_MASK (1<= MV_USB_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) + { + mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pDecWin->target), + pDecWin->addrWin.baseLow, + pDecWin->addrWin.size); + return MV_ERROR; + } + + if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) + { + mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* set Size, Attributes and TargetID */ + sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | + ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | + ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); + +#if defined(MV645xx) || defined(MV646xx) + /* If window is DRAM with HW cache coherency, make sure bit2 is set */ + sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; + + if((MV_TARGET_IS_DRAM(pDecWin->target)) && + (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) + { + sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; + } + else + { + sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; + } +#endif /* MV645xx || MV646xx */ + + if (pDecWin->enable == MV_TRUE) + { + sizeReg |= MV_USB_WIN_ENABLE_MASK; + } + else + { + sizeReg &= ~MV_USB_WIN_ENABLE_MASK; + } + + /* Update Base value */ + baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); + + MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); + MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvUsbWinGet - Get USB peripheral target address window. +* +* DESCRIPTION: +* Get USB peripheral target address window. +* +* INPUT: +* winNum - USB target address decode window number. +* +* OUTPUT: +* pDecWin - USB target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) +{ + MV_DEC_WIN_PARAMS winParam; + MV_U32 sizeReg, baseReg; + + /* Parameter checking */ + if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", + __FUNCTION__, dev, winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); + sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); + + /* Check if window is enabled */ + if(sizeReg & MV_USB_WIN_ENABLE_MASK) + { + pDecWin->enable = MV_TRUE; + + /* Extract window parameters from registers */ + winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; + winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; + winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; + winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); + + /* Translate the decode window parameters to address decode struct */ + if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) + { + mvOsPrintf("Failed to translate register parameters to USB address" \ + " decode window structure\n"); + return MV_ERROR; + } + } + else + { + pDecWin->enable = MV_FALSE; + } + return MV_OK; +} + +/******************************************************************************* +* mvUsbWinInit - +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvUsbWinInit(int dev) +{ + MV_STATUS status; + MV_DEC_WIN usbWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + int winNum; + MV_U32 winPrioIndex = 0; + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); + } + + /* Go through all windows in user table until table terminator */ + winNum = 0; + while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && + (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) + { + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], + &cpuAddrDecWin); + + if(MV_NO_SUCH == status) + { + winPrioIndex++; + continue; + } + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; + usbWin.enable = MV_TRUE; + usbWin.target = usbAddrDecPrioTab[winPrioIndex]; + +#if defined(MV645xx) || defined(MV646xx) + /* Get the default attributes for that target window */ + mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); +#endif /* MV645xx || MV646xx */ + + if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) + { + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} + +/******************************************************************************* +* mvUsbAddrDecShow - Print the USB address decode map. +* +* DESCRIPTION: +* This function print the USB address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvUsbAddrDecShow(MV_VOID) +{ + MV_DEC_WIN addrDecWin; + int i, winNum; + + mvOsOutput( "\n" ); + mvOsOutput( "USB:\n" ); + mvOsOutput( "----\n" ); + + for(i=0; i= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + if (pAddrDecWin == NULL) + { + DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + /* Check if the requested window overlaps with current windows */ + if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) + { + DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); + return MV_ERROR; + } + + xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); + xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); + + /* Get Base Address and size registers values */ + if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) + { + DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); + return MV_BAD_PARAM; + } + + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; + xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; + /* set target ID */ + xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; + xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; + + + /* Write to address decode Base Address Register */ + MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); + + /* Write to Size Register */ + MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); + + for (chan = 0; chan < MV_XOR_MAX_CHAN; chan++) + { + if (pAddrDecWin->enable) + { + MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + else + { + MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + } + return MV_OK; +} + +/******************************************************************************* +* mvXorTargetWinGet - Get xor peripheral target address window. +* +* DESCRIPTION: +* Get xor peripheral target address window. +* +* INPUT: +* winNum - One of the possible XOR memory decode windows. +* +* OUTPUT: +* base - Window base address. +* size - Window size. +* enable - window enable/disable. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS xorDecRegs; + MV_TARGET_ATTRIB targetAttrib; + MV_U32 chan=0,chanWinEn; + + /* Parameter checking */ + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); + return MV_ERROR; + } + + if (NULL == pAddrDecWin) + { + DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + + chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + /* Check if enable bit is equal for all channels */ + if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & + XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) + { + mvOsPrintf("%s: ERR. Window enable field must be equal in " + "all channels\n",__FUNCTION__); + return MV_ERROR; + } + } + + + + xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); + xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; + targetAttrib.targetId = + (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; + + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + if(chanWinEn) + { + pAddrDecWin->enable = MV_TRUE; + } + else pAddrDecWin->enable = MV_FALSE; + + return MV_OK; +} + +/******************************************************************************* +* mvXorTargetWinEnable - Enable/disable a Xor address decode window +* +* DESCRIPTION: +* This function enable/disable a XOR address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling XOR accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) +{ + MV_XOR_DEC_WIN addrDecWin; + MV_U32 chan; + + /* Parameter checking */ + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { + /* Get current window */ + if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) + { + DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); + return MV_ERROR; + } + + /* Check for overlapping */ + if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) + { + /* Overlap detected */ + DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); + return MV_ERROR; + } + + /* No Overlap. Enable address decode target window */ + for (chan = 0; chan < MV_XOR_MAX_CHAN; chan++) + { + MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + + } + else + { + /* Disable address decode target window */ + + for (chan = 0; chan < MV_XOR_MAX_CHAN; chan++) + { + MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + + } + + return MV_OK; +} + +/******************************************************************************* +* mvXorSetProtWinSet - Configure access attributes of a XOR engine +* to one of the XOR memory windows. +* +* DESCRIPTION: +* Each engine can be configured with access attributes for each of the +* memory spaces. This function sets access attributes +* to a given window for the given engine +* +* INPUTS: +* chan - One of the possible engines. +* winNum - One of the possible XOR memory spaces. +* access - Protection access rights. +* write - Write rights. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, + MV_BOOL write) +{ + MV_U32 temp; + + /* Parameter checking */ + if (chan >= MV_XOR_MAX_CHAN) + { + DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); + return MV_BAD_PARAM; + } + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + + temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & + (~XEXWCR_WIN_ACC_MASK(winNum)); + + /* if access is disable */ + if (!access) + { + /* disable access */ + temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); + } + /* if access is enable */ + else + { + /* if write is enable */ + if (write) + { + /* enable write */ + temp |= XEXWCR_WIN_ACC_RW(winNum); + } + /* if write is disable */ + else + { + /* disable write */ + temp |= XEXWCR_WIN_ACC_RO(winNum); + } + } + MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); + return MV_OK; +} + +/******************************************************************************* +* mvXorPciRemap - Set XOR remap register for PCI address windows. +* +* DESCRIPTION: +* only Windows 0-3 can be remapped. +* +* INPUT: +* winNum - window number +* pAddrDecWin - pointer to address space window structure +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) +{ + /* Parameter checking */ + if (winNum >= XOR_MAX_REMAP_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + + MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); + + return MV_OK; +} + +/******************************************************************************* +* xorWinOverlapDetect - Detect XOR address windows overlaping +* +* DESCRIPTION: +* An unpredicted behaviour is expected in case XOR address decode +* windows overlaps. +* This function detects XOR address decode windows overlaping of a +* specified window. The function does not check the window itself for +* overlaping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex,chan; + MV_XOR_DEC_WIN addrDecWin; + + if (pAddrWin == NULL) + { + DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + + for (chan = 0; chan < MV_XOR_MAX_CHAN; chan++) + { + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); + + for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) + { + /* Do not check window itself */ + if (winNumIndex == winNum) + { + continue; + } + + /* Do not check disabled windows */ + if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) + { + DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + } + + return MV_FALSE; +} + +static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) +{ + MV_XOR_DEC_WIN win; + int i; + + mvOsOutput( "\n" ); + mvOsOutput( "XOR %d:\n", unit ); + mvOsOutput( "----\n" ); + + for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + +/******************************************************************************* +* mvXorAddrDecShow - Print the XOR address decode map. +* +* DESCRIPTION: +* This function print the XOR address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvXorAddrDecShow(MV_VOID) +{ + int i; + + for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) + mvXorAddrDecShowUnit(i); + +} diff --git a/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysXor.h b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysXor.h new file mode 100644 index 0000000..4d46708 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/ctrlEnv/sys/mvSysXor.h @@ -0,0 +1,141 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCMVSysXorh +#define __INCMVSysXorh + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ctrlEnv/sys/mvCpuIf.h" + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ +#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ + +/* XOR Engine Address Decoding Register Map */ +#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) +#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) +#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) +#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) + +/* XOR Engine [0..1] Window Control Registers (XExWCR) */ +#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) +#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) +#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) +#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) + +#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) +#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) + +/* XOR Engine Base Address Registers (XEBARx) */ +#define XEBARX_TARGET_OFFS (0) +#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) +#define XEBARX_ATTR_OFFS (8) +#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) +#define XEBARX_BASE_OFFS (16) +#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) + +/* XOR Engine Size Mask Registers (XESMRx) */ +#define XESMRX_SIZE_MASK_OFFS (16) +#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) + +/* XOR Engine High Address Remap Register (XEHARRx1) */ +#define XEHARRX_REMAP_OFFS (0) +#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) + +typedef struct _mvXorDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_XOR_DEC_WIN; + +MV_STATUS mvXorInit (MV_VOID); +MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, + MV_XOR_DEC_WIN *pAddrDecWin); +MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, + MV_XOR_DEC_WIN *pAddrDecWin); +MV_STATUS mvXorTargetWinEnable(MV_U32 unit, + MV_U32 winNum, MV_BOOL enable); +MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, + MV_BOOL write); +MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); + +MV_VOID mvXorAddrDecShow(MV_VOID); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/board/mv_feroceon/mv_orion/orion_family/device/mvDevice.c b/board/mv_feroceon/mv_orion/orion_family/device/mvDevice.c new file mode 100644 index 0000000..8078352 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/device/mvDevice.c @@ -0,0 +1,318 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvDevice.h" + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + + + +/******************************************************************************* +* mvDevPramSet - Set device interface bank parameters +* +* DESCRIPTION: +* This function sets a device bank parameters to a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* *pDevParams - Device bank parameter struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + + } + if (pDevParams->turnOff > MAX_DBP_TURNOFF) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. turnOff parameter out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2First > MAX_DBP_ACC2FIRST) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. acc2First out of range\n")); + return MV_ERROR; + } + if (pDevParams->acc2Next > MAX_DBP_ACC2NEXT) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. acc2Next out of range\n")); + return MV_ERROR; + } + if (pDevParams->ale2Wr > MAX_DBP_ALE2WR) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. ale2Wr parameter out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrLow > MAX_DBP_WRLOW) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. wrLow parameter out of range\n")); + return MV_ERROR; + } + if (pDevParams->wrHigh > MAX_DBP_WRHIGH) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. wrHigh parameter out of range\n")); + return MV_ERROR; + } + if ((pDevParams->badrSkew << DBP_BADRSKEW_OFFS) > DBP_BADRSKEW_2CYCLE ) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. badrSkew parameter out of range\n")); + return MV_ERROR; + } + if ((pDevParams->deviceWidth != 8 )&& + (pDevParams->deviceWidth != 16 )&& + (pDevParams->deviceWidth != 32 )) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. deviceWidth out of range\n")); + return MV_ERROR; + } + + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + + /* setting values */ + devParam |= (pDevParams->turnOff << DBP_TURNOFF_OFFS); + devParam |= (pDevParams->acc2First << DBP_ACC2FIRST_OFFS); + devParam |= (pDevParams->acc2Next << DBP_ACC2NEXT_OFFS); + devParam |= (pDevParams->ale2Wr << DBP_ALE2WR_OFFS); + devParam |= (pDevParams->wrLow << DBP_WRLOW_OFFS); + devParam |= (pDevParams->wrHigh << DBP_WRHIGH_OFFS); + devParam |= (pDevParams->badrSkew << DBP_BADRSKEW_OFFS); + + + switch (pDevParams->deviceWidth) + { + case 8: + devParam |= DBP_DEVWIDTH_8BIT; + break; + case 16: + devParam |= DBP_DEVWIDTH_16BIT; + break; + case 32: + devParam |= DBP_DEVWIDTH_32BIT; + break; + default: + DB(mvOsPrintf("mvDevIfPramSet: ERR. deviceWidth invalid\n")); + return MV_ERROR; + break; + } + + MV_REG_WRITE(DEV_BANK_PARAM_REG(device),devParam); + + return MV_OK; +} + +/******************************************************************************* +* mvDevPramget - Get device interface bank parameters +* +* DESCRIPTION: +* This function retrieves a device bank parameter settings. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* *pDevParams - Device bank parameter struct. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams) +{ + MV_U32 devParam; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + pDevParams->turnOff = (devParam & DBP_TURNOFF_MASK) >> DBP_TURNOFF_OFFS; + pDevParams->acc2First = (devParam & DBP_ACC2FIRST_MASK)>>DBP_ACC2FIRST_OFFS; + pDevParams->acc2Next = (devParam & DBP_ACC2NEXT_MASK) >> DBP_ACC2NEXT_OFFS; + pDevParams->ale2Wr = (devParam & DBP_ALE2WR_MASK) >> DBP_ALE2WR_OFFS; + pDevParams->wrLow = (devParam & DBP_WRLOW_MASK) >> DBP_WRLOW_OFFS; + pDevParams->wrHigh = (devParam & DBP_WRHIGH_MASK) >> DBP_WRHIGH_OFFS; + pDevParams->badrSkew = (devParam & DBP_BADRSKEW_MASK) >> DBP_BADRSKEW_OFFS; + + + + switch (devParam & DBP_DEVWIDTH_MASK) + { + case DBP_DEVWIDTH_8BIT: + pDevParams->deviceWidth=8; + break; + case DBP_DEVWIDTH_16BIT: + pDevParams->deviceWidth=16; + break; + case DBP_DEVWIDTH_32BIT: + pDevParams->deviceWidth=32; + break; + default: + DB(mvOsPrintf("mvDevIfPramSet: ERR. invalid deviceWidth\n")); + return MV_ERROR; + break; + } + + + return MV_OK; +} + +/******************************************************************************* +* mvDevWidthGet - Get device width parameter +* +* DESCRIPTION: +* This function gets width parameter of a given device. +* +* INPUT: +* device - Device number. See MV_DEVICE enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* Device width in bytes. +* +*******************************************************************************/ +MV_U32 mvDevWidthGet(MV_DEVICE device) +{ + + MV_U32 devParam; + + /* check parameters */ + if (device >= MV_DEV_MAX_CS) + { + DB(mvOsPrintf("mvDevIfPramSet: ERR. Invalid Device num %d\n", device)); + return MV_BAD_PARAM; + + } + + devParam = MV_REG_READ(DEV_BANK_PARAM_REG(device)); + + devParam = (devParam & DBP_DEVWIDTH_MASK) >> DBP_DEVWIDTH_OFFS; + + return (MV_U32)(0x8 << devParam); + +} + +/******************************************************************************* +* mvDevNandSet - Set NAND chip-select and care mode +* +* DESCRIPTION: +* This function set the NAND flash controller registers with NAND +* device chip-select. +* +* INPUT: +* devNum - Device number. See MV_DEVICE enumerator. +* careMode - NAND device care mode (0 = Don't care, '1' = care). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvDevNandSet(MV_DEVICE devNum, MV_BOOL careMode) +{ + MV_U32 nfCtrlReg; /* NAND Flash Control Register */ + + /* Set chip select */ + nfCtrlReg = MV_REG_READ(DEV_NAND_CTRL_REG); + + nfCtrlReg |= (DINFCR_NF_CS_MASK(devNum)); + + if (careMode) + nfCtrlReg |= (DINFCR_NF_ACT_CE_MASK(devNum)); + else + nfCtrlReg &= ~(DINFCR_NF_ACT_CE_MASK(devNum)); + + + MV_REG_WRITE(DEV_NAND_CTRL_REG, nfCtrlReg); + +} + + diff --git a/board/mv_feroceon/mv_orion/orion_family/device/mvDevice.h b/board/mv_feroceon/mv_orion/orion_family/device/mvDevice.h new file mode 100644 index 0000000..bcc868f --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/device/mvDevice.h @@ -0,0 +1,101 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDeviceH +#define __INCmvDeviceH + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "device/mvDeviceRegs.h" + +/* This structure describes device interface parameters to be assigned to */ +/* device bank parameter */ +typedef struct _mvDeviceParam +{ /* boundary values */ + MV_U32 turnOff; /* 0x0 - 0xf */ + MV_U32 acc2First; /* 0x0 - 0x1f */ + MV_U32 acc2Next; /* 0x0 - 0x1f */ + MV_U32 ale2Wr; /* 0x0 - 0xf */ + MV_U32 wrLow; /* 0x0 - 0xf */ + MV_U32 wrHigh; /* 0x0 - 0xf */ + MV_U32 badrSkew; /* 0x0 - 0x2 */ + MV_U32 deviceWidth; /* in Bytes */ +} MV_DEVICE_PARAM; + + +/* mvDevPramSet - Set device interface bank parameters */ +MV_STATUS mvDevIfPramSet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevPramget - Get device interface bank parameters */ +MV_STATUS mvDevPramGet(MV_DEVICE device, MV_DEVICE_PARAM *pDevParams); + +/* mvDevWidthGet - Get device width parameter*/ +MV_U32 mvDevWidthGet(MV_DEVICE device); + +/* mvDevNandDevCsSet - Set the NAND flash controller registers with */ +/* NAND device chip-select and care mode */ +MV_VOID mvDevNandSet(MV_DEVICE devNum, MV_BOOL careMode); + +#endif /* #ifndef __INCmvDeviceH */ diff --git a/board/mv_feroceon/mv_orion/orion_family/device/mvDeviceRegs.h b/board/mv_feroceon/mv_orion/orion_family/device/mvDeviceRegs.h new file mode 100644 index 0000000..b368028 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/device/mvDeviceRegs.h @@ -0,0 +1,223 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDeviceRegsH +#define __INCmvDeviceRegsH + +#ifndef MV_ASMLANGUAGE +#include "ctrlEnv/mvCtrlEnvLib.h" +/* This enumerator describes the Marvell controller possible devices that */ +/* can be connected to its device interface. */ +typedef enum _mvDevice +{ +#if defined(MV_INCLUDE_DEVICE_CS0) + DEV_CS0 = 0, /* Device connected to dev CS[0] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEV_CS1 = 1, /* Device connected to dev CS[1] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEV_CS2 = 2, /* Device connected to dev CS[2] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEV_CS3 = 3, /* Device connected to dev CS[2] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS4) + DEV_CS4 = 4, /* Device connected to BOOT dev */ +#endif + MV_DEV_MAX_CS = MV_DEVICE_MAX_CS +}MV_DEVICE; + + +#endif /* MV_ASMLANGUAGE */ + + +/* registers offsets */ + +#if defined(MV_88F5182) || defined(MV_88W8660) || defined(MV_88F5082) +#define DEV_NAND_CTRL_REG 0x104E8 +#define DEV_RGMII_AC_TIMING_REG 0x104F0 +#else +#define DEV_NAND_CTRL_REG 0x10470 +#define DEV_RGMII_AC_TIMING_REG 0x104E8 +#endif + + +#define DEV_INTERF_CTRL_REG 0x104C0 +#define DEV_INTERF_XBAR_TIMEOUT_REG 0x104C4 + +#define DEV_INTR_CAUSE_REG 0x104D0 +#define DEV_INTR_MASK_REG 0x104D4 + + +/* Device Bank Parameters register fields (DBP_REG)*/ +/* Boot Device Bank Parameters (DBP) register fields (DEV_BOOT_BANK_PARAM_REG)*/ + +#define DBP_TURNOFF_OFFS 0 +#define DBP_TURNOFF_MASK (0x7 << DBP_TURNOFF_OFFS) +#define MAX_DBP_TURNOFF 0x7 + +#define DBP_ACC2FIRST_OFFS 3 +#define DBP_ACC2FIRST_MASK (0xf << DBP_ACC2FIRST_OFFS) +#define MAX_DBP_ACC2FIRST 0xf + +#define DBP_ACC2NEXT_OFFS 7 +#define DBP_ACC2NEXT_MASK (0xf << DBP_ACC2NEXT_OFFS) +#define MAX_DBP_ACC2NEXT 0xf + + +#define DBP_ALE2WR_OFFS 11 +#define DBP_ALE2WR_MASK (0x7 << DBP_ALE2WR_OFFS) +#define MAX_DBP_ALE2WR 0x7 + + +#define DBP_WRLOW_OFFS 14 +#define DBP_WRLOW_MASK (0x7 << DBP_WRLOW_OFFS) +#define MAX_DBP_WRLOW 0x7 + + +#define DBP_WRHIGH_OFFS 17 +#define DBP_WRHIGH_MASK (0x7 << DBP_WRHIGH_OFFS) +#define MAX_DBP_WRHIGH 0x7 + + +#define DBP_DEVWIDTH_OFFS 20 /* Device Width */ +#define DBP_DEVWIDTH_MASK (0x3 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_8BIT (0x0 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_16BIT (0x1 << DBP_DEVWIDTH_OFFS) +#define DBP_DEVWIDTH_32BIT (0x2 << DBP_DEVWIDTH_OFFS) + + +#define DBP_TURNOFFEXT BIT22 /* TurnOff Extension */ +#define DBP_ACC2FIRSTEXT BIT23 /* Acc2First Extension */ +#define DBP_ACC2NEXTEXT BIT24 /* Acc2Next Extension */ +#define DBP_ALE2WREXT BIT25 /* ALE2Wr Extension */ +#define DBP_WRLOWEXT BIT26 /* WrLow Extension */ +#define DBP_WRHIGHEXT BIT27 /* WrHigh Extension */ + +#define DBP_BADRSKEW_OFFS 28 +#define DBP_BADRSKEW_MASK (0x3 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_NOGAP (0x0 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_1CYCLE (0x1 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_2CYCLE (0x2 << DBP_BADRSKEW_OFFS) + +#define DBP_BADRSKEW_OFFS 28 +#define DBP_BADRSKEW_MASK (0x3 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_NOGAP (0x0 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_1CYCLE (0x1 << DBP_BADRSKEW_OFFS) +#define DBP_BADRSKEW_2CYCLE (0x2 << DBP_BADRSKEW_OFFS) + +#define DBP_RESRV_OFFS 30 +#define DBP_RESRV_MASK (0x3 << DBP_RESRV_OFFS) +#define DBP_RESRV_VAL (0x2 << DBP_RESRV_OFFS) + + + +/* Device Interface Control register fields (DIC) (DIC_REG)*/ + +#define DIC_TIMEOUT_OFFS 0 /* Timeout Timer Preset Value. */ +#define DIC_TIMEOUT_MASK (0xffff << DIC_TIMEOUT_OFFS) +#define MAX_DIC_TIMEOUT 0xffff + +#define DIC_RDTRIG BIT16 /* Read Trigger Control */ +#define DIC_RES18 BIT18 /* must be 1 */ +#define DIC_PERRPROP BIT19 /* Parity error propagation enable */ +#define DIC_PARSEL BIT20 /* Even or Odd parity select */ +#define DIC_FORCEPAREN BIT21 /* Force Parity Enable */ + +#define DIC_RDDPPAR_OFFS 22 /* Read data path parity select */ +#define DIC_RDDPPAR_MASK (1 << DIC_RDDPPAR_OFFS) +#define DIC_RDDPPAR_EVEN (0 << DIC_RDDPPAR_OFFS) +#define DIC_RDDPPAR_ODD (1 << DIC_RDDPPAR_OFFS) + +#define DIC_WRDPPAR_OFFS 23 /* Write data path parity select*/ +#define DIC_WRDPPAR_MASK (1 << DIC_WRDPPAR_OFFS) +#define DIC_WRDPPAR_EVEN (0 << DIC_WRDPPAR_OFFS) +#define DIC_WRDPPAR_ODD (1 << DIC_WRDPPAR_OFFS) + +#define DIC_FORCEPAR_OFFS 24 +#define DIC_FORCEPAR_MASK (0xf << DIC_FORCEPAR_OFFS) +#define MAX_DIC_FORCEPAR 0xf + +#define DIC_RES30_OFFS 30 /* must be 0 */ +#define DIC_RES30_MASK (0x3 << DIC_RES30_OFFS + +/* Device Interface Crossbar Control Low (DICCL) register (DIC_L_XBAR_REG) */ +/* Device Interface Crossbar Control High (DICCH) register (DIC_H_XBAR_REG) */ + +#define DICCL_OFFS(num) (4*num) +#define DICCL_MASK(num) (0xf << DICCL_OFFS(num)) + +#define DICCH_OFFS(num) (4*(num-8)) +#define DICCH__MASK(num) (0xf << DICCH_OFFS(num)) + +#define DICC_CPU 0x2 +#define DICC_PCI0 0x3 +#define DICC_PCI1 0x4 +#define DICC_MPSC 0x5 +#define DICC_IDMA 0x6 +#define DICC_GETH 0x7 + + +#endif /* #ifndef __INCmvDeviceRegsH */ diff --git a/board/mv_feroceon/mv_orion/orion_family/mvCompVer.txt b/board/mv_feroceon/mv_orion/orion_family/mvCompVer.txt new file mode 100644 index 0000000..c6e1229 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_family/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_2 +Unit HAL Version: 3.1.0 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/board/mv_feroceon/mv_orion/orion_sys/mv88F1281SysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mv88F1281SysHwConfig.h new file mode 100644 index 0000000..20927a4 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mv88F1281SysHwConfig.h @@ -0,0 +1,182 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv88F1281SysHwConfigh +#define __INCmv88F1281SysHwConfigh + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ +#define MV_INCLUDE_PEX +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_UART +#define MV_INCLUDE_NAND + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NOR Flash support */ +#define MV_INC_BOARD_NOR_FLASH +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC +/* On-Board PCI\PEX SATA driver*/ +#define MV_INC_BOARD_PCI_SATA + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 1 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* Bridge exist on pciIf1*/ + +/*********************************************/ +/* U-Boot Specific */ +/*********************************************/ + +#define MV_INCLUDE_MONT_EXT + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#define MV_INCLUDE_MONT_LOAD_NET +#endif + + +/*********************************************/ +/* RD boards specifics */ +/*********************************************/ + + + + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M + +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _1M + + + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + + +#define PEX1_MEM_BASE 0x98000000 +#define PEX1_MEM_SIZE _128M + +#define PEX1_IO_BASE 0xf0100000 +#define PEX1_IO_SIZE _1M + + +/* Device: CS0 - Flash, CS1 - Boot Flash */ +#define DEVICE_CS0_BASE 0xf8000000 +#define DEVICE_CS0_SIZE _16M + +#define DEVICE_CS1_BASE BOOTDEV_CS_BASE +#define DEVICE_CS1_SIZE BOOTDEV_CS_SIZE + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PEX1_MEM_BASE +#define PCI_IF1_MEM0_SIZE PEX1_MEM_SIZE +#define PCI_IF1_IO_BASE PEX1_IO_BASE +#define PCI_IF1_IO_SIZE PEX1_IO_SIZE + + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE} ,0xFFFFFFFF,DIS}, \ + {{PEX0_MEM_BASE , 0, PEX0_MEM_SIZE } ,0x0 ,EN}, \ + {{PEX0_IO_BASE , 0, PEX0_IO_SIZE } ,0x2 ,EN}, \ + {{PEX1_MEM_BASE , 0, PEX1_MEM_SIZE } ,0x1 ,EN}, \ + {{PEX1_IO_BASE , 0, PEX1_IO_SIZE } ,0x3 ,EN}, \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE},0x8 ,EN}, \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE},0x7 ,EN}, \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE},0x4 ,EN}, \ + /* Table terminator */\ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM,TBL_TERM} \ +}; + +#endif /* __INCmv88F1281SysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_sys/mv88F1X81SysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mv88F1X81SysHwConfig.h new file mode 100644 index 0000000..44102cf --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mv88F1X81SysHwConfig.h @@ -0,0 +1,162 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv88F1X81SysHwConfigh +#define __INCmv88F1X81SysHwConfigh + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ +#define MV_INCLUDE_PEX +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_UART + + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NOR Flash support */ +#define MV_INC_BOARD_NOR_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC +/* On-Board PCI\PEX SATA driver*/ +#define MV_INC_BOARD_PCI_SATA + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 1 /* Bridge exist on pciIf1*/ + +/*********************************************/ +/* U-Boot Specific */ +/*********************************************/ + +#define MV_INCLUDE_MONT_EXT + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#define MV_INCLUDE_MONT_LOAD_NET +#endif + + +/*********************************************/ +/* RD boards specifics */ +/*********************************************/ + + + + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M + +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _1M + + + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + + +#define PEX1_MEM_BASE 0x98000000 +#define PEX1_MEM_SIZE _128M + +#define PEX1_IO_BASE 0xf0100000 +#define PEX1_IO_SIZE _1M + + + + +#define FLASH_CS_BASE 0xf8000000 +#define FLASH_CS_SIZE _16M + + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PEX1_MEM_BASE +#define PCI_IF1_MEM0_SIZE PEX1_MEM_SIZE +#define PCI_IF1_IO_BASE PEX1_IO_BASE +#define PCI_IF1_IO_SIZE PEX1_IO_SIZE + + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ + + + + +#endif /* __INCmv88F1X81SysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_sys/mv88F5082SysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mv88F5082SysHwConfig.h new file mode 100644 index 0000000..d55305f --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mv88F5082SysHwConfig.h @@ -0,0 +1,258 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv88F5082SysHwConfigh +#define __INCmv88F5082SysHwConfigh + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ + +#define MV_INCLUDE_PEX +#define MV_INCLUDE_IDMA +#define MV_INCLUDE_CESA +#define MV_INCLUDE_GIG_ETH +#define MV_INCLUDE_INTEG_SATA +#define MV_INCLUDE_USB +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART + + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NOR Flash support */ +#define MV_INC_BOARD_NOR_FLASH +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC +/* On-Board PCI\PEX SATA */ +#define MV_INC_BOARD_PEX_SATA + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + + +/*********************************************/ +/* U-Boot Specific */ +/*********************************************/ +#define MV_INCLUDE_MONT_EXT + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#define MV_INCLUDE_MONT_LOAD_NET +#endif + + +/*********************************************/ +/* RD boards specifics */ +/*********************************************/ + +/* RD Boards specific */ +#if defined(RD_88F5082) || defined (RD_88F5082_3) + +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INC_BOARD_DDIM +#undef MV_INCLUDE_IDMA + +#endif + + + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M + +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _1M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + +/* Device: CS0 - SRAM, CS1 - RTC, CS2 - UART, CS3 - large flash */ +#define DEVICE_CS0_BASE 0xfa000000 +#define DEVICE_CS0_SIZE _2M + +#define DEVICE_CS1_BASE 0xf8000000 +#define DEVICE_CS1_SIZE _32M + +#define DEVICE_CS2_BASE 0xfa800000 +#define DEVICE_CS2_SIZE _1M + +#define DEVICE_CS3_BASE BOOTDEV_CS_BASE +#define DEVICE_CS3_SIZE BOOTDEV_CS_SIZE + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + + +#define CRYPT_ENG_BASE 0xFB000000 +#define CRYPT_ENG_SIZE _64K + + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF1_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF1_IO_BASE PCI0_IO_BASE +#define PCI_IF1_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF0_IO_BASE PCI0_IO_BASE +#define PCI_IF0_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#endif + + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +#undef PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ + + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +/* HW cache coherency configuration */ +#define DMA_RAM_COHER NO_COHERENCY +#define ETHER_DRAM_COHER MV_UNCACHED +#define INTEG_SRAM_COHER MV_UNCACHED /* Where integrated SRAM available */ + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" + +#endif /* ETHER_DRAM_COHER */ + + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE} ,0xFFFFFFFF,DIS}, \ + {{PEX0_MEM_BASE , 0, PEX0_MEM_SIZE } ,0x0 ,EN}, \ + {{PEX0_IO_BASE , 0, PEX0_IO_SIZE } ,0x2 ,EN}, \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE},0x8 ,EN}, \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE},0x5 ,EN}, \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE},0x6 ,EN}, \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE},0x7 ,EN}, \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE},0x4 ,EN}, \ + {{CRYPT_ENG_BASE, 0, CRYPT_ENG_SIZE} ,0x7 ,DIS}, \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM,TBL_TERM} \ +} + +#endif /* __INCmv88F5082SysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_sys/mv88F5180NSysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mv88F5180NSysHwConfig.h new file mode 100644 index 0000000..ea767a7 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mv88F5180NSysHwConfig.h @@ -0,0 +1,221 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv88F5X81SysHwConfigh +#define __INCmv88F5X81SysHwConfigh + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ +#define MV_INCLUDE_PCI +#define MV_INCLUDE_IDMA +#define MV_INCLUDE_GIG_ETH +#define MV_INCLUDE_USB +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NOR Flash support */ +#define MV_INC_BOARD_NOR_FLASH +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC +/* On-Board PCI\PEX SATA */ +#define MV_INC_BOARD_PCI_SATA + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + +/*********************************************/ +/* U-Boot Specific */ +/*********************************************/ +#define MV_INCLUDE_MONT_EXT + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#define MV_INCLUDE_MONT_LOAD_NET +#endif + + + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M + +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _1M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + + +/* PCI0: IO and memory space */ +#define PCI0_MEM_BASE 0x98000000 +#define PCI0_MEM_SIZE _128M + +#define PCI0_IO_BASE 0xf0100000 +#define PCI0_IO_SIZE _1M + + +/* Device: CS0 - SRAM, CS1 - RTC, CS2 - UART, CS3 - large flash */ +#define DEVICE_CS0_BASE 0xfa000000 +#define DEVICE_CS0_SIZE _2M + +#define DEVICE_CS1_BASE 0xf8000000 +#define DEVICE_CS1_SIZE _32M + +#define DEVICE_CS2_BASE 0xfa800000 +#define DEVICE_CS2_SIZE _1M + +#define DEVICE_CS3_BASE BOOTDEV_CS_BASE +#define DEVICE_CS3_SIZE BOOTDEV_CS_SIZE + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + + +#define PCI_IF0_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF0_IO_BASE PCI0_IO_BASE +#define PCI_IF0_IO_SIZE PCI0_IO_SIZE + + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ + + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +/* HW cache coherency configuration */ +#define DMA_RAM_COHER NO_COHERENCY +#define ETHER_DRAM_COHER MV_UNCACHED +#define INTEG_SRAM_COHER MV_UNCACHED /* Where integrated SRAM available */ + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" + +#endif /* ETHER_DRAM_COHER */ + + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE} ,0xFFFFFFFF,DIS}, \ + {{PCI0_MEM_BASE , 0, PCI0_MEM_SIZE } ,0x1 ,EN}, \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE } ,0x3 ,EN}, \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE},0x8 ,EN}, \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE},0x5 ,EN}, \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE},0x6 ,EN}, \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE},0x7 ,EN}, \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE},0x4 ,EN}, \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM,TBL_TERM} \ +} + +#endif /* __INCmv88F5X81SysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_sys/mv88F5181LSysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mv88F5181LSysHwConfig.h new file mode 100644 index 0000000..78d7b91 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mv88F5181LSysHwConfig.h @@ -0,0 +1,272 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv88F5181LSysHwConfigh +#define __INCmv88F5181LSysHwConfigh + + +/****************************************/ +/* Soc supported Units definitions */ +/****************************************/ + +#define MV_INCLUDE_PCI +#define MV_INCLUDE_PEX +#define MV_INCLUDE_IDMA +#define MV_INCLUDE_CESA +#define MV_INCLUDE_GIG_ETH +#define MV_INCLUDE_USB +#define MV_INCLUDE_TDM +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NOR Flash support */ +#define MV_INC_BOARD_NOR_FLASH +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board Telephony SLIC */ +#define MV_INC_BOARD_SLIC +/* On-Board RTC */ +#define MV_INC_BOARD_RTC +/* On-Board PCI\PEX SATA */ +#define MV_INC_BOARD_PCI_SATA + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + + +/*********************************************/ +/* U-Boot Specific */ +/*********************************************/ +#define MV_INCLUDE_MONT_EXT + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#define MV_INCLUDE_MONT_LOAD_NET +#endif + +/*********************************************/ +/* RD boards specifics */ +/*********************************************/ + + +#if defined(RD_88F5181L_GE) || defined (RD_88F5181L_FE) || defined (RD_88F5181L_FXO_GE) + +/* On-Board Marvell Switch */ +#define MV_INC_BOARD_QD_SWITCH +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INC_BOARD_DDIM +#endif + + + + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M + +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _1M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + + +/* PCI0: IO and memory space */ +#define PCI0_MEM_BASE 0x98000000 +#define PCI0_MEM_SIZE _128M + +#define PCI0_IO_BASE 0xf0100000 +#define PCI0_IO_SIZE _1M + + +/* Device: CS0 - SRAM, CS1 - RTC, CS2 - UART, CS3 - large flash */ +#define DEVICE_CS0_BASE 0xfa000000 +#define DEVICE_CS0_SIZE _2M + +#define DEVICE_CS1_BASE 0xf8000000 +#define DEVICE_CS1_SIZE _32M + +#define DEVICE_CS2_BASE 0xfa800000 +#define DEVICE_CS2_SIZE _1M + +#define DEVICE_CS3_BASE BOOTDEV_CS_BASE +#define DEVICE_CS3_SIZE BOOTDEV_CS_SIZE + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + +#define CRYPT_ENG_BASE 0xFB000000 +#define CRYPT_ENG_SIZE _64K + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF1_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF1_IO_BASE PCI0_IO_BASE +#define PCI_IF1_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF0_IO_BASE PCI0_IO_BASE +#define PCI_IF0_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#endif + + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ + + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +/* HW cache coherency configuration */ +#define DMA_RAM_COHER NO_COHERENCY +#define ETHER_DRAM_COHER MV_UNCACHED +#define INTEG_SRAM_COHER MV_UNCACHED /* Where integrated SRAM available */ + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" + +#endif /* ETHER_DRAM_COHER */ + + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE} ,0xFFFFFFFF,DIS}, \ + {{PEX0_MEM_BASE , 0, PEX0_MEM_SIZE } ,0x0 ,EN}, \ + {{PEX0_IO_BASE , 0, PEX0_IO_SIZE } ,0x2 ,EN}, \ + {{PCI0_MEM_BASE , 0, PCI0_MEM_SIZE } ,0x1 ,EN}, \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE } ,0x3 ,EN}, \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE},0x8 ,EN}, \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE},0x5 ,EN}, \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE},0x6 ,EN}, \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE},0x7 ,EN}, \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE},0x4 ,EN}, \ + {{CRYPT_ENG_BASE, 0, CRYPT_ENG_SIZE} ,0x7 ,DIS}, \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM,TBL_TERM} \ +} + +#endif /* __INCmv88F5181LSysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_sys/mv88F5182SysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mv88F5182SysHwConfig.h new file mode 100644 index 0000000..4740055 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mv88F5182SysHwConfig.h @@ -0,0 +1,284 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv88F5182SysHwConfigh +#define __INCmv88F5182SysHwConfigh + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ + +#define MV_INCLUDE_PCI +#define MV_INCLUDE_PEX +#define MV_INCLUDE_IDMA +#define MV_INCLUDE_CESA +#define MV_INCLUDE_XOR +#define MV_INCLUDE_GIG_ETH +#define MV_INCLUDE_INTEG_SATA +#define MV_INCLUDE_USB +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART + + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NOR Flash support */ +#define MV_INC_BOARD_NOR_FLASH +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC +/* On-Board PCI\PEX SATA */ +#define MV_INC_BOARD_PCI_SATA + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + + +/*********************************************/ +/* U-Boot Specific */ +/*********************************************/ +#define MV_INCLUDE_MONT_EXT + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#define MV_INCLUDE_MONT_LOAD_NET +#endif + + +/*********************************************/ +/* RD boards specifics */ +/*********************************************/ + +/* RD Boards specific */ +#if defined(RD_88F5182) + +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INC_BOARD_DDIM +#undef MV_INCLUDE_IDMA + +#endif + +#if defined (RD_88F5182_3) + +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INC_BOARD_DDIM +#undef MV_INCLUDE_MONT_EXT +#undef MV_INCLUDE_IDMA +#undef MV_INCLUDE_CESA +#undef MV_INCLUDE_XOR +#endif + + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M + +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _1M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + +/* PCI0: IO and memory space */ +#define PCI0_MEM_BASE 0x98000000 +#define PCI0_MEM_SIZE _128M + +#define PCI0_IO_BASE 0xf0100000 +#define PCI0_IO_SIZE _1M + +/* Device: CS0 - 7seg, CS1 - large flash, CS2 - NAND, CS3 - NA */ +#define DEVICE_CS0_BASE 0xfa000000 +#define DEVICE_CS0_SIZE _2M + +#define DEVICE_CS1_BASE 0xf8000000 +#define DEVICE_CS1_SIZE _32M + +#define DEVICE_CS2_BASE 0xfa800000 +#define DEVICE_CS2_SIZE _1M + +#define DEVICE_CS3_BASE BOOTDEV_CS_BASE +#define DEVICE_CS3_SIZE BOOTDEV_CS_SIZE + +#ifdef MV_NAND_BOOT +#define CFG_NAND_BASE BOOTDEV_CS_BASE +#else +#define CFG_NAND_BASE DEVICE_CS2_BASE +#endif + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + + +#define CRYPT_ENG_BASE 0xFB000000 +#define CRYPT_ENG_SIZE _64K + + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF1_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF1_IO_BASE PCI0_IO_BASE +#define PCI_IF1_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF0_IO_BASE PCI0_IO_BASE +#define PCI_IF0_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#endif + + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ + + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +/* HW cache coherency configuration */ +#define DMA_RAM_COHER NO_COHERENCY +#define ETHER_DRAM_COHER MV_UNCACHED +#define INTEG_SRAM_COHER MV_UNCACHED /* Where integrated SRAM available */ + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" + +#endif /* ETHER_DRAM_COHER */ + + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE} ,0xFFFFFFFF,DIS}, \ + {{PEX0_MEM_BASE , 0, PEX0_MEM_SIZE } ,0x0 ,EN}, \ + {{PEX0_IO_BASE , 0, PEX0_IO_SIZE } ,0x2 ,EN}, \ + {{PCI0_MEM_BASE , 0, PCI0_MEM_SIZE } ,0x1 ,EN}, \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE } ,0x3 ,EN}, \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE},0x8 ,EN}, \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE},0x5 ,EN}, \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE},0x6 ,EN}, \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE},0x7 ,EN}, \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE},0x4 ,EN}, \ + {{CRYPT_ENG_BASE, 0, CRYPT_ENG_SIZE} ,0x7 ,DIS}, \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM,TBL_TERM} \ +} + +#endif /* __INCmv88F5182SysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_sys/mv88F5X81SysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mv88F5X81SysHwConfig.h new file mode 100644 index 0000000..0d68301 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mv88F5X81SysHwConfig.h @@ -0,0 +1,330 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv88F5X81SysHwConfigh +#define __INCmv88F5X81SysHwConfigh + + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ +#define MV_INCLUDE_PCI +#define MV_INCLUDE_PEX +#define MV_INCLUDE_IDMA +#define MV_INCLUDE_GIG_ETH +#define MV_INCLUDE_USB +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NOR Flash support */ +#define MV_INC_BOARD_NOR_FLASH +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC +/* On-Board PCI\PEX SATA */ +#define MV_INC_BOARD_PCI_SATA + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + +/*********************************************/ +/* U-Boot Specific */ +/*********************************************/ +#define MV_INCLUDE_MONT_EXT + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#define MV_INCLUDE_MONT_LOAD_NET +#endif + +/*********************************************/ +/* RD boards specifics */ +/*********************************************/ + +/* RD Boards specific */ +#if defined(MV_POS_NAS) + +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INC_BOARD_DDIM + +#endif + +#if defined(RD_88F5181_GTWGE) || defined (RD_88F5181_GTWFE) +/* On-Board Marvell Switch */ +#define MV_INC_BOARD_QD_SWITCH + +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INC_BOARD_DDIM + +#endif + + +#if defined(DB_VOIP) +/* On-Board Telephony SLIC */ +#define MV_INC_BOARD_SLIC +/* On-Board TDM FPGA */ +#define MV_INC_BOARD_TDM_FPGA +/* On-Board Marvell Switch */ +#define MV_INC_BOARD_QD_SWITCH + +#undef MV_INC_BOARD_NAND_FLASH +#endif + +#if defined(DB_MNG) +#undef MV_INC_BOARD_DDIM +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INCLUDE_USB +#endif + +#if defined(DB_PRPMC) || defined (DB_PEX_PCI) + +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INCLUDE_USB +#undef MV_INC_BOARD_DDIM +#if defined(DB_PEX_PCI) + #undef PCI1_IF_MODE + #define PCI1_IF_MODE PCI_IF_MODE_DEVICE +#endif + +#endif /* defined(DB_PRPMC) || defined (DB_PEX_PCI) */ + + +#if defined(MV_POS_NAS) +#undef MV_INCLUDE_MONT_FFS +#endif + +#if defined(DB_FPGA) +#undef MV_INCLUDE_PEX +#undef MV_INCLUDE_IDMA +#undef MV_INCLUDE_GIG_ETH +#undef MV_INCLUDE_USB +#undef MV_INCLUDE_TWSI +#undef MV_INCLUDE_NAND +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INC_BOARD_DDIM +#undef MV_MEM_OVER_PCI_WA +#undef MV_MEM_OVER_PEX_WA +#define MV_UART_OVER_PCI_WA +#endif + + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M + +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _1M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + + +/* PCI0: IO and memory space */ +#define PCI0_MEM_BASE 0x98000000 +#define PCI0_MEM_SIZE _128M + +#define PCI0_IO_BASE 0xf0100000 +#define PCI0_IO_SIZE _1M + +#if defined(DB_FPGA) +#define DEVICE_CS0_BASE 0xf8000000 +#define DEVICE_CS0_SIZE _32M + +#define DEVICE_CS1_BASE 0xfa000000 +#define DEVICE_CS1_SIZE _2M +#else +#define DEVICE_CS0_BASE 0xfa000000 +#define DEVICE_CS0_SIZE _2M + +#define DEVICE_CS1_BASE 0xf8000000 +#define DEVICE_CS1_SIZE _32M +#endif + +#define DEVICE_CS2_BASE 0xfa800000 +#define DEVICE_CS2_SIZE _1M + +#define DEVICE_CS3_BASE BOOTDEV_CS_BASE +#define DEVICE_CS3_SIZE BOOTDEV_CS_SIZE + +#ifdef MV_NAND_BOOT +#define CFG_NAND_BASE BOOTDEV_CS_BASE +#else +#define CFG_NAND_BASE DEVICE_CS2_BASE +#endif +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF1_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF1_IO_BASE PCI0_IO_BASE +#define PCI_IF1_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF0_IO_BASE PCI0_IO_BASE +#define PCI_IF0_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#endif + + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + + +/* Board clock detection */ +#undef MV_TCLK_CALC +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ + + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +/* HW cache coherency configuration */ +#define DMA_RAM_COHER NO_COHERENCY +#define ETHER_DRAM_COHER MV_UNCACHED +#define INTEG_SRAM_COHER MV_UNCACHED /* Where integrated SRAM available */ + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" + +#endif /* ETHER_DRAM_COHER */ + + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS2_BASE , 0, SDRAM_CS2_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS3_BASE , 0, SDRAM_CS3_SIZE} ,0xFFFFFFFF,DIS}, \ + {{PEX0_MEM_BASE , 0, PEX0_MEM_SIZE } ,0x0 ,EN}, \ + {{PEX0_IO_BASE , 0, PEX0_IO_SIZE } ,0x2 ,EN}, \ + {{PCI0_MEM_BASE , 0, PCI0_MEM_SIZE } ,0x1 ,EN}, \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE } ,0x3 ,EN}, \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE},0x8 ,EN}, \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE},0x5 ,EN}, \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE},0x6 ,EN}, \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE},0x7 ,EN}, \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE},0x4 ,EN}, \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM,TBL_TERM} \ +} + +#endif /* __INCmv88F5X81SysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_sys/mv88F6082SysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mv88F6082SysHwConfig.h new file mode 100644 index 0000000..63a57b2 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mv88F6082SysHwConfig.h @@ -0,0 +1,291 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv88F6082SysHwConfigh +#define __INCmv88F6082SysHwConfigh + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ + +#define MV_INCLUDE_PEX +#define MV_INCLUDE_CESA +#define MV_INCLUDE_GIG_ETH +#define MV_INCLUDE_INTEG_SATA +#define MV_INCLUDE_USB +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART +#define MV_INCLUDE_SPI +#define MV_INCLUDE_INTEG_MFLASH +/*#define MV_INCLUDE_INTEG_MFLASH_SPI*/ + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board SPI Flash support */ +#define MV_INC_BOARD_SPI_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + +#if defined(MV_INCLUDE_INTEG_MFLASH_SPI) && defined (MV_INC_BOARD_SPI_FLASH) +#error "Cannot Use MFlash in SPI mode while configuring and external SPI flash" +#endif + +/*********************************************/ +/* U-Boot Specific */ +/*********************************************/ +#define MV_INCLUDE_MONT_EXT + +/* Tailgate WA for Nanya memory */ +/* #define MV_MEM_OVER_PCI_WA */ + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#define MV_INCLUDE_MONT_LOAD_NET +#endif + + +/*********************************************/ +/* DB boards specifics */ +/*********************************************/ + +#if defined(DB_88F6082BP) || defined(DB_88F6082LBP) + +#undef MV_INC_BOARD_DDIM + +#endif + +/*********************************************/ +/* RD boards specifics */ +/*********************************************/ + +#if defined(RD_88F6082NAS) +#undef MV_INC_BOARD_DDIM +#undef MV_INCLUDE_IDMA +#undef MV_INCLUDE_PCI +#undef MV_INC_BOARD_SPI_FLASH +#endif + +#if defined (RD_88F6082GE_SATA) || defined (RD_88F6082SA) || defined (RD_88F6082DAS_PLUS) \ + || defined (RD_88F6082MICRO_DAS_NAS) +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INC_BOARD_DDIM +#undef MV_INCLUDE_IDMA +#undef MV_INCLUDE_PCI +#endif + +#if defined (RD_88F6082MICRO_DAS_NAS) +#define MV_INC_DRAM_MFG_TEST +#endif + +#if defined (RD_88F6082_DX243) +#undef MV_INC_BOARD_DDIM +#undef MV_INCLUDE_IDMA +#undef MV_INCLUDE_PCI +#define MV_INCLUDE_PEX +#undef MV_INCLUDE_CESA +#undef MV_INCLUDE_INTEG_SATA +#undef MV_INCLUDE_USB +#undef MV_INC_BOARD_NAND_FLASH +#endif + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _1M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + +/* Device: CS0 - NAND, CS1 - MFlash, CS2 - SPI, CS3 - Boot ROM, CS4 - Boot device */ +#define DEVICE_CS0_BASE 0xf8000000 +#define DEVICE_CS0_SIZE _1M + +#define DEVICE_MFLASH_BASE 0xf8100000 +#define DEVICE_CS1_BASE DEVICE_MFLASH_BASE +#define DEVICE_CS1_SIZE _1M + +#define DEVICE_CS2_BASE 0xf9000000 +#define DEVICE_CS2_SIZE _16M + +#define DEVICE_CS3_BASE 0xfa000000 +#define DEVICE_CS3_SIZE _1M + +#define DEVICE_CS4_BASE BOOTDEV_CS_BASE +#define DEVICE_CS4_SIZE BOOTDEV_CS_SIZE + +#define CFG_NAND_BASE DEVICE_CS0_BASE + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + + +#define CRYPT_ENG_BASE 0xFB000000 +#define CRYPT_ENG_SIZE _64K + + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF1_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF1_IO_BASE PCI0_IO_BASE +#define PCI_IF1_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF0_IO_BASE PCI0_IO_BASE +#define PCI_IF0_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#endif + + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ + + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +/* HW cache coherency configuration */ +#define DMA_RAM_COHER NO_COHERENCY +#define ETHER_DRAM_COHER MV_UNCACHED +#define INTEG_SRAM_COHER MV_UNCACHED /* Where integrated SRAM available */ + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" + +#endif /* ETHER_DRAM_COHER */ + + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE} ,0xFFFFFFFF,DIS}, \ + {{PEX0_MEM_BASE , 0, PEX0_MEM_SIZE } ,0x0 ,EN}, \ + {{PEX0_IO_BASE , 0, PEX0_IO_SIZE } ,0x2 ,EN}, \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE},0x8 ,EN}, \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE},0x1 ,EN}, \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE},0x3 ,EN}, \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE},0x5 ,EN}, \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE},0x6 ,EN}, \ + {{DEVICE_CS4_BASE, 0, DEVICE_CS4_SIZE},0x4 ,EN}, \ + {{CRYPT_ENG_BASE, 0, CRYPT_ENG_SIZE} ,0x7 ,EN}, \ + /* Table terminator */\ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM,TBL_TERM} \ +}; + +#endif /* __INCmv88F6082SysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_sys/mv88F6183LSysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mv88F6183LSysHwConfig.h new file mode 100644 index 0000000..1a8afd0 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mv88F6183LSysHwConfig.h @@ -0,0 +1,202 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv88F6183LSysHwConfigh +#define __INCmv88F6183LSysHwConfigh + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ + +#define MV_INCLUDE_PEX +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART +#define MV_INCLUDE_SPI + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board SPI Flash support */ +#define MV_INC_BOARD_SPI_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + +/*********************************************/ +/* U-Boot Specific */ +/*********************************************/ +#define MV_INCLUDE_MONT_EXT + +/* Tailgate WA for Nanya memory */ +/* #define MV_MEM_OVER_PCI_WA */ + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#endif + + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _1M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + +/* Device: CS0 - NAND, CS1 - SPI, CS2 - SPI, CS3 - Boot ROM, CS4 - Boot device */ + + +#define DEVICE_CS0_BASE 0xf8800000 +#define DEVICE_CS0_SIZE _8M + +#define DEVICE_SPI_BASE 0xf8000000 +#define DEVICE_CS1_BASE DEVICE_SPI_BASE +#define DEVICE_CS1_SIZE _8M + +#define DEVICE_CS4_BASE BOOTDEV_CS_BASE +#define DEVICE_CS4_SIZE BOOTDEV_CS_SIZE + +#ifdef MV_NAND_BOOT +#define CFG_NAND_BASE BOOTDEV_CS_BASE +#else +#define CFG_NAND_BASE DEVICE_CS2_BASE +#endif + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF1_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF1_IO_BASE PCI0_IO_BASE +#define PCI_IF1_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF0_IO_BASE PCI0_IO_BASE +#define PCI_IF0_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#endif + + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE} ,0xFFFFFFFF,DIS}, \ + {{PEX0_MEM_BASE , 0, PEX0_MEM_SIZE } ,0x0 ,EN}, \ + {{PEX0_IO_BASE , 0, PEX0_IO_SIZE } ,0x2 ,EN}, \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE},0x8 ,EN}, \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE},0x1 ,EN}, \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE},0x3 ,EN}, \ + {{DEVICE_CS4_BASE, 0, DEVICE_CS4_SIZE},0x4 ,EN}, \ + /* Table terminator */\ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM,TBL_TERM} \ +}; + +#endif /* __INCmv88F6183LSysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_sys/mv88F6183SysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mv88F6183SysHwConfig.h new file mode 100644 index 0000000..3878a70 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mv88F6183SysHwConfig.h @@ -0,0 +1,254 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv88F6183SysHwConfigh +#define __INCmv88F6183SysHwConfigh + +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ + +#define MV_INCLUDE_PEX +#define MV_INCLUDE_CESA +#define MV_INCLUDE_GIG_ETH +#define MV_INCLUDE_USB +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART +#define MV_INCLUDE_SPI + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board SPI Flash support */ +#define MV_INC_BOARD_SPI_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + +/*********************************************/ +/* U-Boot Specific */ +/*********************************************/ +#define MV_INCLUDE_MONT_EXT + +/* Tailgate WA for Nanya memory */ +/* #define MV_MEM_OVER_PCI_WA */ + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#define MV_INCLUDE_MONT_LOAD_NET +#endif + + +/*********************************************/ +/* RD boards specifics */ +/*********************************************/ + +#if defined(RD_88F6183AP) +#define MV_INC_BOARD_QD_SWITCH +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INC_BOARD_DDIM +#endif + +#if defined(RD_88F6183GP) +#undef MV_INC_BOARD_DDIM +#undef MV_INC_BOARD_SPI_FLASH +#endif + + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _1M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + +/* Device: CS0 - NAND, CS1 - SPI, CS2 - SPI, CS3 - Boot ROM, CS4 - Boot device */ + + +#define DEVICE_CS0_BASE 0xf8800000 +#define DEVICE_CS0_SIZE _8M + +#define DEVICE_SPI_BASE 0xf8000000 +#define DEVICE_CS1_BASE DEVICE_SPI_BASE +#define DEVICE_CS1_SIZE _8M + +#define DEVICE_CS4_BASE BOOTDEV_CS_BASE +#define DEVICE_CS4_SIZE BOOTDEV_CS_SIZE + +#ifdef MV_NAND_BOOT +#define CFG_NAND_BASE BOOTDEV_CS_BASE +#else +#define CFG_NAND_BASE DEVICE_CS2_BASE +#endif + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + + +#define CRYPT_ENG_BASE 0xFB000000 +#define CRYPT_ENG_SIZE _64K + + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF1_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF1_IO_BASE PCI0_IO_BASE +#define PCI_IF1_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF0_IO_BASE PCI0_IO_BASE +#define PCI_IF0_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#endif + + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ + + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +/* HW cache coherency configuration */ +#define DMA_RAM_COHER NO_COHERENCY +#define ETHER_DRAM_COHER MV_UNCACHED +#define INTEG_SRAM_COHER MV_UNCACHED /* Where integrated SRAM available */ + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" + +#endif /* ETHER_DRAM_COHER */ + + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE} ,0xFFFFFFFF,DIS}, \ + {{PEX0_MEM_BASE , 0, PEX0_MEM_SIZE } ,0x0 ,EN}, \ + {{PEX0_IO_BASE , 0, PEX0_IO_SIZE } ,0x2 ,EN}, \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE},0x8 ,EN}, \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE},0x1 ,EN}, \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE},0x3 ,EN}, \ + {{DEVICE_CS4_BASE, 0, DEVICE_CS4_SIZE},0x4 ,EN}, \ + {{CRYPT_ENG_BASE, 0, CRYPT_ENG_SIZE} ,0x7 ,EN}, \ + /* Table terminator */\ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM,TBL_TERM} \ +}; + +#endif /* __INCmv88F6183SysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_sys/mv88w8660SysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mv88w8660SysHwConfig.h new file mode 100644 index 0000000..9f39aea --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mv88w8660SysHwConfig.h @@ -0,0 +1,254 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmv88F5X81SysHwConfigh +#define __INCmv88F5X81SysHwConfigh +/****************************************/ +/* Soc supporetd Units definitions */ +/****************************************/ + +#define MV_INCLUDE_PCI +#define MV_INCLUDE_PEX +#define MV_INCLUDE_IDMA +#define MV_INCLUDE_UNM_ETH +#define MV_INCLUDE_USB +#define MV_INCLUDE_TWSI +#define MV_INCLUDE_NAND +#define MV_INCLUDE_UART + +/*********************************************/ +/* Board Specific defines : On-Board devices */ +/*********************************************/ + +/* DRAM ddim detection support */ +#define MV_INC_BOARD_DDIM +/* On-Board NOR Flash support */ +#define MV_INC_BOARD_NOR_FLASH +/* On-Board NAND Flash support */ +#define MV_INC_BOARD_NAND_FLASH +/* On-Board RTC */ +#define MV_INC_BOARD_RTC +/* On-Board PCI\PEX SATA */ +#define MV_INC_BOARD_PCI_SATA + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* no Bridge on pciIf0*/ +#define PCI1_IF_PTP 0 /* no Bridge on pciIf1*/ + +/*********************************************/ +/* U-Boot Specific */ +/*********************************************/ +#define MV_INCLUDE_MONT_EXT + +#if defined(MV_INCLUDE_MONT_EXT) +#define MV_INCLUDE_MONT_MMU +#define MV_INCLUDE_MONT_MPU +#if defined(MV_INC_BOARD_NOR_FLASH) +#define MV_INCLUDE_MONT_FFS +#endif +#define MV_INCLUDE_MONT_LOAD_NET +#endif + + +/*********************************************/ +/* RD boards specifics */ +/*********************************************/ + +#if defined(RD_88W8660) +#define MV_INC_BOARD_QD_SWITCH +#undef MV_INC_BOARD_NAND_FLASH +#undef MV_INC_BOARD_DDIM +#endif + + +#if defined(RD_88W8660_AP82S) +#define MV_INC_BOARD_QD_SWITCH +#undef MV_INC_BOARD_DDIM +#endif + +/* + * System memory mapping + */ + +/* SDRAM: actual mapping is auto detected */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0x90000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf0000000 +#define PEX0_IO_SIZE _1M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0x50000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + + +/* PCI0: IO and memory space */ +#define PCI0_MEM_BASE 0x98000000 +#define PCI0_MEM_SIZE _128M + +#define PCI0_IO_BASE 0xf0100000 +#define PCI0_IO_SIZE _1M + + +/* Device: CS0 - SRAM, CS1 - RTC, CS2 - UART, CS3 - large flash */ +#define DEVICE_CS0_BASE 0xfa000000 +#define DEVICE_CS0_SIZE _2M + +#define DEVICE_CS1_BASE 0xf8000000 +#define DEVICE_CS1_SIZE _32M + +#define DEVICE_CS2_BASE 0xfa800000 +#define DEVICE_CS2_SIZE _1M + +#define DEVICE_CS3_BASE BOOTDEV_CS_BASE +#define DEVICE_CS3_SIZE BOOTDEV_CS_SIZE + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xF1000000 + + +#if defined (MV_INCLUDE_PCI) && defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#define PCI_IF1_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF1_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF1_IO_BASE PCI0_IO_BASE +#define PCI_IF1_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PCI) + +#define PCI_IF0_MEM0_BASE PCI0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PCI0_MEM_SIZE +#define PCI_IF0_IO_BASE PCI0_IO_BASE +#define PCI_IF0_IO_SIZE PCI0_IO_SIZE + +#elif defined (MV_INCLUDE_PEX) + +#define PCI_IF0_MEM0_BASE PEX0_MEM_BASE +#define PCI_IF0_MEM0_SIZE PEX0_MEM_SIZE +#define PCI_IF0_IO_BASE PEX0_IO_BASE +#define PCI_IF0_IO_SIZE PEX0_IO_SIZE + +#endif + + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +#define PCI_ARBITER_CTRL /* Use/unuse the Marvell integrated PCI arbiter */ +#undef PCI_ARBITER_BOARD /* Use/unuse the PCI arbiter on board */ + +/* Check macro validity */ +#if defined(PCI_ARBITER_CTRL) && defined (PCI_ARBITER_BOARD) + #error "Please select either integrated PCI arbiter or board arbiter" +#endif + + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ + + +/************* Ethernet driver configuration ********************/ + +/*#define ETH_JUMBO_SUPPORT*/ +/* HW cache coherency configuration */ +#define DMA_RAM_COHER NO_COHERENCY +#define ETHER_DRAM_COHER MV_UNCACHED +#define INTEG_SRAM_COHER MV_UNCACHED /* Where integrated SRAM available */ + +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WB" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_HW_WT" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) +# define ETH_SDRAM_CONFIG_STR "MV_CACHE_COHER_SW" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "MV_UNCACHED" +#else +# error "Unexpected ETHER_DRAM_COHER value" + +#endif /* ETHER_DRAM_COHER */ + + +/*********** Idma default configuration ***********/ +#define UBOOT_CNTRL_DMA_DV (ICCLR_DST_BURST_LIM_8BYTE | \ + ICCLR_SRC_INC | \ + ICCLR_DST_INC | \ + ICCLR_SRC_BURST_LIM_8BYTE | \ + ICCLR_NON_CHAIN_MODE | \ + ICCLR_BLOCK_MODE ) + + +/* CPU address decode table. Note that table entry number must match its */ +/* winNum enumerator. For example, table entry '4' must describe Deivce CS0 */ +/* winNum which is represent by DEVICE_CS0 enumerator (4). */ +#define MV_CPU_IF_ADDR_WIN_MAP_TBL { \ +/* base low base high size WinNum enable */ \ + {{SDRAM_CS0_BASE , 0, SDRAM_CS0_SIZE} ,0xFFFFFFFF,DIS}, \ + {{SDRAM_CS1_BASE , 0, SDRAM_CS1_SIZE} ,0xFFFFFFFF,DIS}, \ + {{PEX0_MEM_BASE , 0, PEX0_MEM_SIZE } ,0x0 ,EN}, \ + {{PEX0_IO_BASE , 0, PEX0_IO_SIZE } ,0x2 ,EN}, \ + {{PCI0_MEM_BASE , 0, PCI0_MEM_SIZE } ,0x1 ,EN}, \ + {{PCI0_IO_BASE , 0, PCI0_IO_SIZE } ,0x3 ,EN}, \ + {{INTER_REGS_BASE, 0, INTER_REGS_SIZE},0x8 ,EN}, \ + {{DEVICE_CS0_BASE, 0, DEVICE_CS0_SIZE},0x5 ,EN}, \ + {{DEVICE_CS1_BASE, 0, DEVICE_CS1_SIZE},0x6 ,EN}, \ + {{DEVICE_CS2_BASE, 0, DEVICE_CS2_SIZE},0x7 ,EN}, \ + {{DEVICE_CS3_BASE, 0, DEVICE_CS3_SIZE},0x4 ,EN}, \ + /* Table terminator */ \ + {{TBL_TERM, TBL_TERM, TBL_TERM}, TBL_TERM,TBL_TERM} \ +} + +#endif /* __INCmv88F5X81SysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/orion_sys/mvSysHwConfig.h b/board/mv_feroceon/mv_orion/orion_sys/mvSysHwConfig.h new file mode 100644 index 0000000..c2dfe84 --- /dev/null +++ b/board/mv_feroceon/mv_orion/orion_sys/mvSysHwConfig.h @@ -0,0 +1,190 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmvSysHwConfigh +#define __INCmvSysHwConfigh + + +#define MV_CACHEABLE(address) ((address) | 0x80000000) + +/* includes */ +#define _1K 0x00000400 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + +#if defined(DB_CUSTOMER) +#include "mvCustomerSysHwConfig.h" +#elif defined(MV_88F1181) +#include "mv88F1X81SysHwConfig.h" +#elif defined(MV_88F1281) +#include "mv88F1281SysHwConfig.h" +#elif defined(MV_88F5182) +#include "mv88F5182SysHwConfig.h" +#elif defined(MV_88F5082) +#include "mv88F5082SysHwConfig.h" +#elif defined(MV_88F5181L) +#include "mv88F5181LSysHwConfig.h" +#elif defined(MV_88W8660) +#include "mv88w8660SysHwConfig.h" +#elif defined(MV_88F5181) +#include "mv88F5X81SysHwConfig.h" +#elif defined(MV_88F5180N) +#include "mv88F5180NSysHwConfig.h" +#elif defined(MV_88F6082) +#include "mv88F6082SysHwConfig.h" +#elif defined(MV_88F6183) +#include "mv88F6183SysHwConfig.h" +#elif defined(MV_88F6183L) +#include "mv88F6183LSysHwConfig.h" +#endif + +#if defined(MV_BOOTSIZE_256K) + +#define BOOTDEV_CS_SIZE _256K + +#elif defined(MV_BOOTSIZE_512K) + +#define BOOTDEV_CS_SIZE _512K + +#elif defined(MV_BOOTSIZE_4M) + +#define BOOTDEV_CS_SIZE _4M + +#elif defined(MV_BOOTSIZE_8M) + +#define BOOTDEV_CS_SIZE _8M + +#elif defined(MV_BOOTSIZE_16M) + +#define BOOTDEV_CS_SIZE _16M + +#elif defined(MV_BOOTSIZE_32M) + +#define BOOTDEV_CS_SIZE _32M + +#elif defined(MV_BOOTSIZE_64M) + +#define BOOTDEV_CS_SIZE _64M + +#elif defined(MV_NAND_BOOT) + +#define BOOTDEV_CS_SIZE _512K + +#else + +#define Error MV_BOOTSIZE undefined + +#endif + +#define BOOTDEV_CS_BASE ((0xFFFFFFFF - BOOTDEV_CS_SIZE) + 1) + +/* We use the following registers to store DRAM interface pre configuration */ +/* auto-detection results */ +/* IMPORTANT: We are using mask register for that purpose. Before writing */ +/* to units mask register, make sure main maks register is set to disable */ +/* all interrupts. */ +#define DRAM_BUF_REG0 0x1011c /* sdram bank 0 size */ +#define DRAM_BUF_REG1 0x20318 /* sdram config */ +#define DRAM_BUF_REG2 0x20114 /* sdram mode */ +#define DRAM_BUF_REG3 0x20320 /* dunit control low */ +#define DRAM_BUF_REG4 0x20404 /* sdram address control */ +#define DRAM_BUF_REG5 0x2040c /* sdram timing control low */ + +#if defined(MV_INCLUDE_PEX) +#define DRAM_BUF_REG6 0x40108 /* sdram timing control high */ +#define DRAM_BUF_REG7 0x40114 /* sdram ODT control low */ +#define DRAM_BUF_REG8 0x41910 /* sdram ODT control high */ +#define DRAM_BUF_REG9 0x41a08 /* sdram Dunit ODT control */ +#define DRAM_BUF_REG10 0x41a30 /* sdram Extended Mode */ +#elif defined(MV_INCLUDE_IDMA) +#define DRAM_BUF_REG6 0x60810 /* sdram timing control high */ +#define DRAM_BUF_REG7 0x60814 /* sdram ODT control low */ +#define DRAM_BUF_REG8 0x60818 /* sdram ODT control high */ +#define DRAM_BUF_REG9 0x6081c /* sdram Dunit ODT control */ +#define DRAM_BUF_REG10 0x60820 /* sdram Extended Mode */ +#elif defined(DB_FPGA) +#define DRAM_BUF_REG6 0x10108 /* sdram timing control high */ +#define DRAM_BUF_REG7 0x10118 /* sdram ODT control low */ +#define DRAM_BUF_REG8 0x10118 /* sdram ODT control high */ +#define DRAM_BUF_REG9 0x10118 /* sdram Dunit ODT control */ +#define DRAM_BUF_REG10 0x1010c /* sdram Extended Mode */ +#endif + +/* Following the pre-configuration registers default values restored after */ +/* auto-detection is done */ +#define DRAM_BUF_REG0_DV 0 /* GPIO Interrupt Level Mask Reg */ +#define DRAM_BUF_REG1_DV 0 /* ARM Timer 1 reload register */ +#define DRAM_BUF_REG2_DV 0 /* AHB to MBUS Bridge int Mask Reg */ +#define DRAM_BUF_REG3_DV 0 /* ARM Watchdog Timer Register */ +#define DRAM_BUF_REG4_DV 0 /* Host to ARM Doorbel Mask Register */ +#define DRAM_BUF_REG5_DV 0 /* ARM To Host Doorbel Mask Register */ +#define DRAM_BUF_REG6_DV 0 /* PCI Exp Uncorrectable Err Mask Reg */ +#define DRAM_BUF_REG7_DV 0 /* PCI Exp Correctable Err Mask Reg */ +#define DRAM_BUF_REG8_DV 0 /* PCI Express interrupt Mask Reg */ +#define DRAM_BUF_REG9_DV 0 /* PCI Express Spare Register */ +#if defined(DB_FPGA) +#define DRAM_BUF_REG10_DV 0x0 +#else +#define DRAM_BUF_REG10_DV 0x012C0004 /* PCI Exp Acknowledge Timers (x4) Reg*/ +#endif + + +#define MV_ETH_TX_Q_NUM 1 +#define MV_ETH_RX_Q_NUM 1 +#define ETH_NUM_OF_RX_DESCR 64 +#define ETH_NUM_OF_TX_DESCR ETH_NUM_OF_RX_DESCR*2 + +/* port's default queueus */ +#define ETH_DEF_TXQ 0 +#define ETH_DEF_RXQ 0 + +#define MV_DISABLE_PEX_DEVICE_BAR + +#endif /* __INCmvSysHwConfigh */ diff --git a/board/mv_feroceon/mv_orion/platform.S b/board/mv_feroceon/mv_orion/platform.S new file mode 100644 index 0000000..a7ebdcc --- /dev/null +++ b/board/mv_feroceon/mv_orion/platform.S @@ -0,0 +1,1682 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include +#include +#include "mvBoardEnvSpec.h" +#include "mvCtrlEnvSpec.h" +#include "mvCpuIfConfig.h" +#include "pex/mvPexRegs.h" +#include "ddr1_2/mvDramIfRegs.h" +#include "pci/mvPciRegs.h" +#include "mvCtrlEnvAsm.h" +#if defined(MV_INC_BOARD_SPI_FLASH) +#include "spi/mvSpiSpec.h" +#endif + + +#define MAGIC_BYTE0 ((MV_BOARD_I2C_MAGIC >> 24 )& 0xff) +#define MAGIC_BYTE1 ((MV_BOARD_I2C_MAGIC >> 16 )& 0xff) +#define MAGIC_BYTE2 ((MV_BOARD_I2C_MAGIC >> 8)& 0xff) +#define MAGIC_BYTE3 ((MV_BOARD_I2C_MAGIC >> 0)& 0xff) + + +/* + get_board_id - get board id from twsi eeprom + input : r5 - board id data start offset in the eeprom + +*/ +.globl lowlevel_init + +/************************************************/ +/* lowlevel_init * +/************************************************/ + +lowlevel_init: + + /* if we are DDRI board then we + should open the CS2 for only 1 MB + to turn the 7segement and not to overlap with the + internal registers and we will do it always + */ +#if !defined(MV_88F6183) && !defined(MV_88F6183L) +#if defined(MV_88F6082) + ldr r4, =0x000f1d11 +#else + ldr r4, =0x000f1b11 +#endif + + MV_DV_REG_WRITE_ASM(r4, r1, 0x20060) +#endif + + /* change reg base to 0xf1000000 */ + ldr r4, =CFG_MV_REGS + MV_DV_REG_WRITE_ASM(r4, r1, 0x20080) + +#ifndef DB_FPGA + /* Clear device ID in PCI in MV_88F5082 */ + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r4, r1); + ldr r1, =MV_5082_DEV_ID + cmp r4, r1 + bne next + + /* Read bus number */ + MV_REG_READ_ASM(r1, r4, PCI_P2P_CONFIG_REG(0)); + mov r4, r1; + and r1, r1, #PPCR_BUS_NUM_MASK; + /* Read dev number */ + and r4, r4, #PPCR_DEV_NUM_MASK; + orr r1, r4, LSR #(PPCR_DEV_NUM_OFFS - PCAR_DEVICE_NUM_OFFS); + /* Set PCI config enable BIT31 */ + orr r1, r1, #PCAR_CONFIG_EN; + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE_ASM(r1, r4, PCI_CONFIG_ADDR_REG(0)); + /* Set PCI configuration data to 0xffffffff */ + ldr r1, =0xffffffff + MV_REG_WRITE_ASM(r1, r4, PCI_CONFIG_DATA_REG(0)); + +#endif /* DB_FPGA */ + /* save Link Registers */ +next: mov r2, lr + +#ifndef DB_FPGA + bl _i2cInit + + /* Initialize BUS-L to DDR configuration parameters */ + /* Must be done prior to DDR operation */ + bl _mvCpuIfPreInit +#endif /* DB_FPGA */ + + +#if !defined(MV_INC_BOARD_DDIM) + + + +#if defined(DB_CUSTOMER) + /* Insert here customer boards specific */ + /* init MPP */ + ldr r6, =RD_88F5181L_CUS1_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_88F5181L_CUS1_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =RD_88F5181L_CUS1_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =RD_88F5181L_CUS1_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* init GPP , Out enable */ + ldr r6, =RD_88F5181L_CUS1_GPP_OE + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + ldr r6, =RD_88F5181L_CUS1_GPP_VAL + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F6183GP) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, 0x1480) + +#if defined(MV_INCLUDE_PCI) + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) +#endif + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F6183AP) +#if defined(MV_INC_BOARD_SPI_FLASH) + /* configure the Prescale of SPI clk Tclk = 166MHz */ + MV_REG_READ_ASM (r6, r1, MV_SPI_IF_CONFIG_REG) + and r6, r6, #~MV_SPI_CLK_PRESCALE_MASK + orr r6, r6, #0x14 + MV_REG_WRITE_ASM (r6, r1, MV_SPI_IF_CONFIG_REG) +#endif + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, 0x1480) + +#if defined(MV_INCLUDE_PCI) + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) +#endif + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F5082) + /* Set SATA LED to blink */ + ldr r6, =0x1 + MV_REG_WRITE_ASM (r6, r1, 0x8002C) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + +#if defined(MV_INCLUDE_PCI) + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) +#endif + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F5082_3) + /* Set SATA LED to blink */ + ldr r6, =0x1 + MV_REG_WRITE_ASM (r6, r1, 0x8002C) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F5182) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + +#if defined(MV_INCLUDE_PCI) + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) +#endif + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F5182_3) + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88W8660) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88W8660_AP82S) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F5181L_FE) + + /* init MPP */ + ldr r6, =RD_88F5181L_VOIP_FE_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_88F5181L_VOIP_FE_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =RD_88F5181L_VOIP_FE_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =RD_88F5181L_VOIP_FE_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* init GPP , Out enable */ + ldr r6, =RD_88F5181L_VOIP_FE_GPP_OE + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /* turn Led to 1 -turn off leds0 0,15 wireless indication-*/ + ldr r6, =RD_88F5181L_VOIP_FE_GPP_IO + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F5181L_GE) + + /* init MPP */ + ldr r6, =RD_88F5181L_VOIP_GE_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_88F5181L_VOIP_GE_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =RD_88F5181L_VOIP_GE_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =RD_88F5181L_VOIP_GE_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* init GPP , Out enable */ + ldr r6, =0xFFFF0330 + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /* turn Led to 1 -turn off leds 10 wireless indication-*/ + ldr r6, =0xC + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F5181_GTWFE) + + /* init MPP */ + ldr r6, =RD_88F5181_GTW_FE_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_88F5181_GTW_FE_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =RD_88F5181_GTW_FE_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =RD_88F5181_GTW_FE_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* init GPP , Out enable */ + ldr r6, =0xFFFF0330 + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /* turn Led to 1 -turn off leds 10 wireless indication-*/ + ldr r6, =0xC + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F5181_GTWGE) + + /* init MPP */ + ldr r6, =RD_88F5181_GTW_GE_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_88F5181_GTW_GE_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =RD_88F5181_GTW_GE_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =RD_88F5181_GTW_GE_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* init GPP , Out enable */ + ldr r6, =0xFFFF0330 + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /* turn Led to 1 -turn off leds 10 wireless indication-*/ + ldr r6, =0xC + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F5181L_FXO_GE) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(MV_POS_NAS) + + /* init MPP */ + ldr r6, =RD_88F5181_POS_NAS_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_88F5181_POS_NAS_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =RD_88F5181_POS_NAS_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =RD_88F5181_POS_NAS_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* init GPP , Out enable */ + ldr r6, =0x00000BDF + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /* turn Led to 1 */ + ldr r6, =0x0000e000 + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(MV_VOIP) + + /* init MPP */ + ldr r6, =RD_88F5181_VOIP_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_88F5181_VOIP_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =RD_88F5181_VOIP_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =RD_88F5181_VOIP_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* init GPP , Out enable */ + ldr r6, =0x000005F5 + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /* turn Led to 1 */ + ldr r6, =0x0000D000 + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + bl _mvDramIfStaticInit + + b done + +#elif defined(DB_PRPMC) + + /* init MPP */ + ldr r6, =DB_88F5181_DDR1_PRPMC_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F5181_DDR1_PRPMC_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =DB_88F5181_DDR1_PRPMC_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =DB_88F5181_DDR1_PRPMC_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* init GPP , Out enable */ + ldr r6, =0xFFFF8FFC + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /* turn Led to 1 */ + ldr r6, =0x00006000 + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + bl _mvDramIfStaticInit + + b done + +#elif defined(DB_MNG) + + /* init MPP */ + ldr r6, =DB_88F5181_DDR1_MNG_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F5181_DDR1_MNG_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =DB_88F5181_DDR1_MNG_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =DB_88F5181_DDR1_MNG_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* init GPP , Out enable */ + ldr r6, =DB_88F5181_DDR1_MNG_GPP_OE + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /* turn Led to 1 */ + ldr r6, =0x00006000 + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* Init PCI arbiter according to Monarch bit 4 in I2c register 0x27 */ + /* If this bit is set disable internal arbiter. */ + mov r4, #0x27 + mov r7, #1 + + bl _i2cRead /* result in r7 */ + + tst r7, #0x10 + + bne no_pci_arbiter + + /* Activate PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + +no_pci_arbiter: + bl _mvDramIfStaticInit + + b done + +#elif defined(DB_FPGA) + +#if defined(MV_MEM_OVER_PCI_WA) + /* Disable PCI ARBITER */ + ldr r6, =0x00000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + MV_REG_READ_ASM (r6, r1, 0x30c00) + orr r6, r6, #0x20000000 + bic r6, r6, #0x10 + MV_REG_WRITE_ASM (r6, r1, 0x30c00) + + /* Set config bus to 1 and device to 0 */ + MV_REG_READ_ASM(r6, r1, PCI_P2P_CONFIG_REG(0)); + mov r1, r6; + and r6, r6, #PPCR_BUS_NUM_MASK; + /* Read dev number */ + and r1, r1, #PPCR_DEV_NUM_MASK; + orr r6, r1, LSR #(PPCR_DEV_NUM_OFFS - PCAR_DEVICE_NUM_OFFS); /* toReg = toReg | (tmpReg >> 13) */ + /* Set PCI config enable BIT31 and config reg 64 */ + orr r6, r6, #PCAR_CONFIG_EN; + orr r6, r6, #0x64; + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE_ASM(r6, r1, PCI_CONFIG_ADDR_REG(0)); + MV_REG_READ_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + /* Write the Data to the PCI Data register */ + ldr r1, =0xffff + bic r7, r7, r1 + orr r7, r7, #0x100 + MV_REG_WRITE_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + + /* Set config PCI ME/IOE/MEME */ + MV_REG_READ_ASM(r6, r1, PCI_P2P_CONFIG_REG(0)); + mov r1, r6; + and r6, r6, #PPCR_BUS_NUM_MASK; + /* Read dev number */ + and r1, r1, #PPCR_DEV_NUM_MASK; + orr r6, r1, LSR #(PPCR_DEV_NUM_OFFS - PCAR_DEVICE_NUM_OFFS); /* toReg = toReg | (tmpReg >> 13) */ + /* Set PCI config enable BIT31 and config reg 4 */ + orr r6, r6, #(PCAR_CONFIG_EN | 0x4); + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE_ASM(r6, r1, PCI_CONFIG_ADDR_REG(0)); + MV_REG_READ_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + /* Write the Data to the PCI Data register */ + orr r7, r7, #0x7 + MV_REG_WRITE_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + + MV_REG_READ_ASM (r6, r1, 0x20104) + and r6, r6, #~0x1; + MV_REG_WRITE_ASM (r6, r1, 0x20104) + + /* Read PCI agent device ID */ + MV_REG_READ_ASM(r6, r1, PCI_P2P_CONFIG_REG(0)); + and r6, r6, #PPCR_BUS_NUM_MASK; + /* Read dev number */ + ldr r1, =(0x8 << PCAR_DEVICE_NUM_OFFS); + orr r6, r6, r1 + /* Set PCI config enable BIT31 */ + orr r6, r6, #PCAR_CONFIG_EN; + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE_ASM(r6, r1, PCI_CONFIG_ADDR_REG(0)); + +wait_for_pci: + /* Read the Data returned in the PCI Data register */ + MV_REG_READ_ASM(r6, r1, PCI_CONFIG_DATA_REG(0)); + mov r6, r6, LSR #PDVIR_DEV_ID_OFFS /* toReg = toReg >> 16 */ + + /* if Orion NAS default board is DB, rd must have special compilation flag */ + ldr r1, =MV_5181_DEV_ID + cmp r1, r6 + beq dram_config + ldr r1, =0x6450 + cmp r1, r6 + beq dram_config + b wait_for_pci + +dram_config: + /* Set PCI agent ME/IOE/MEME */ + MV_REG_READ_ASM(r6, r1, PCI_P2P_CONFIG_REG(0)); + and r6, r6, #PPCR_BUS_NUM_MASK; + /* Read dev number */ + ldr r1, =(0x8 << PCAR_DEVICE_NUM_OFFS); + orr r6, r6, r1 + /* Set PCI config enable BIT31 */ + orr r6, r6, #(PCAR_CONFIG_EN | 0x4); + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE_ASM(r6, r1, PCI_CONFIG_ADDR_REG(0)); + MV_REG_READ_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + /* Write the Data to the PCI Data register */ + orr r7, r7, #0x7 + MV_REG_WRITE_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + + ldr r6, =0x0 + /* Set PCI window base address to address 0 */ + MV_REG_WRITE_ASM (r6, r1, 0x20014) + /* Set remap to 128MB */ + ldr r6, =BIT27 + MV_REG_WRITE_ASM (r6, r1, 0x20018) + + /* Set PCI window size 128MB */ + MV_REG_READ_ASM (r6, r1, 0x20010) + ldr r1, =0xffff + and r6, r6, r1 + ldr r1, =0x7ff + orr r6, r1, LSL #16 + MV_REG_WRITE_ASM (r6, r1, 0x20010) + + /* Set PCI I/O window base address to address f2000000 */ + ldr r6, =0xf5131 + MV_REG_WRITE_ASM (r6, r1, 0x20030) + /* Set base to 0xf2000000 */ + ldr r6, =0xf2000000 + MV_REG_WRITE_ASM (r6, r1, 0x20034) + /* Set remap to 0xf1000000 */ + ldr r6, =0xf1000000 + MV_REG_WRITE_ASM (r6, r1, 0x20038) + +#else + + /* Disable PCI ARBITER */ + ldr r6, =0x00000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + MV_REG_READ_ASM (r6, r1, 0x30c00) + orr r6, r6, #0x20000000 + bic r6, r6, #0x10 + MV_REG_WRITE_ASM (r6, r1, 0x30c00) + + /* Enable access to internal registers in PCI IO tran' */ + MV_REG_READ_ASM (r6, r1, 0x30c3c) + bic r6, r6, #0x400 + MV_REG_WRITE_ASM (r6, r1, 0x30c3c) + + + /* Set config bus to 1 and device to 0 */ + MV_REG_READ_ASM(r6, r1, PCI_P2P_CONFIG_REG(0)); + mov r1, r6; + and r6, r6, #PPCR_BUS_NUM_MASK; + /* Read dev number */ + and r1, r1, #PPCR_DEV_NUM_MASK; + orr r6, r1, LSR #(PPCR_DEV_NUM_OFFS - PCAR_DEVICE_NUM_OFFS); /* toReg = toReg | (tmpReg >> 13) */ + /* Set PCI config enable BIT31 and config reg 64 */ + orr r6, r6, #PCAR_CONFIG_EN; + orr r6, r6, #0x64; + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE_ASM(r6, r1, PCI_CONFIG_ADDR_REG(0)); + MV_REG_READ_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + /* Write the Data to the PCI Data register */ + ldr r1, =0xffff + bic r7, r7, r1 + orr r7, r7, #0x100 + MV_REG_WRITE_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + + /* Set config PCI ME/IOE/MEME */ + MV_REG_READ_ASM(r6, r1, PCI_P2P_CONFIG_REG(0)); + mov r1, r6; + and r6, r6, #PPCR_BUS_NUM_MASK; + /* Read dev number */ + and r1, r1, #PPCR_DEV_NUM_MASK; + orr r6, r1, LSR #(PPCR_DEV_NUM_OFFS - PCAR_DEVICE_NUM_OFFS); /* toReg = toReg | (tmpReg >> 13) */ + /* Set PCI config enable BIT31 and config reg 4 */ + orr r6, r6, #(PCAR_CONFIG_EN | 0x4); + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE_ASM(r6, r1, PCI_CONFIG_ADDR_REG(0)); + MV_REG_READ_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + /* Write the Data to the PCI Data register */ + orr r7, r7, #0x7 + MV_REG_WRITE_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + + MV_REG_READ_ASM (r6, r1, 0x20104) + and r6, r6, #~0x1; + MV_REG_WRITE_ASM (r6, r1, 0x20104) + + /* Read PCI agent device ID */ + MV_REG_READ_ASM(r6, r1, PCI_P2P_CONFIG_REG(0)); + and r6, r6, #PPCR_BUS_NUM_MASK; + /* Read dev number */ + ldr r1, =(0x8 << PCAR_DEVICE_NUM_OFFS); + orr r6, r6, r1 + /* Set PCI config enable BIT31 */ + orr r6, r6, #PCAR_CONFIG_EN; + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE_ASM(r6, r1, PCI_CONFIG_ADDR_REG(0)); + +wait_for_pci: + /* Read the Data returned in the PCI Data register */ + MV_REG_READ_ASM(r6, r1, PCI_CONFIG_DATA_REG(0)); + mov r6, r6, LSR #PDVIR_DEV_ID_OFFS /* toReg = toReg >> 16 */ + + ldr r1, =0x6450 + cmp r1, r6 + beq con_config + b wait_for_pci + +con_config: + /* Set PCI agent ME/IOE/MEME */ + MV_REG_READ_ASM(r6, r1, PCI_P2P_CONFIG_REG(0)); + and r6, r6, #PPCR_BUS_NUM_MASK; + /* Read dev number */ + ldr r1, =(0x8 << PCAR_DEVICE_NUM_OFFS); + orr r6, r6, r1 + /* Set PCI config enable BIT31 */ + orr r6, r6, #(PCAR_CONFIG_EN | 0x4); + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE_ASM(r6, r1, PCI_CONFIG_ADDR_REG(0)); + MV_REG_READ_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + /* Write the Data to the PCI Data register */ + orr r7, r7, #0x7 + MV_REG_WRITE_ASM(r7, r1, PCI_CONFIG_DATA_REG(0)); + + /* Set PCI I/O window base address to address f2000000 */ + ldr r6, =0xf5131 + MV_REG_WRITE_ASM (r6, r1, 0x20030) + /* Set base to 0xf2000000 */ + ldr r6, =0xf2000000 + MV_REG_WRITE_ASM (r6, r1, 0x20034) + /* Set remap to 0xf1000000 */ + ldr r6, =0xf1000000 + MV_REG_WRITE_ASM (r6, r1, 0x20038) + + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + bl _mvDramIfStaticInit +#endif + b done +#elif defined(DB_PEX_PCI) + /* init MPP */ + ldr r6, =DB_88F5181_DDR1_PEXPCI_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F5181_DDR1_PEXPCI_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =DB_88F5181_DDR1_PEXPCI_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =DB_88F5181_DDR1_PEXPCI_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* init GPP , Out enable */ + ldr r6, =0xFFFF0FFF + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /* turn Led to 1 */ + ldr r6, =0x00001000 + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + bl _mvDramIfStaticInit + + b done + +#elif defined(RD_88F6082NAS) + /* Set SATA LED to blink and do not invert indication */ + ldr r6, =0x9 + MV_REG_WRITE_ASM (r6, r1, 0x6002C) + + /* init MPP */ + ldr r6, =RD_88F6082_NAS_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_88F6082_NAS_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + + /* init GPP , disable HDD power */ + MV_REG_READ_ASM (r6, r1, 0x10100) + bic r6, r6, #(1 << 11) + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /* init GPP , Out enable */ + ldr r6, =RD_88F6082_NAS_OE + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + b done + +#elif defined(RD_88F6082DAS_PLUS) + /* Set SATA LED to blink */ + ldr r6, =0x1 + MV_REG_WRITE_ASM (r6, r1, 0x6002C) + + /* init MPP */ + ldr r6, =RD_88F6082_DAS_P_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_88F6082_DAS_P_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + + /* init GPP , disable HDD power */ + MV_REG_READ_ASM (r6, r1, 0x10100) + bic r6, r6, #(1 << 2) + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /* init GPP , Out enable */ + ldr r6, =RD_88F6082_DAS_P_OE + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + b done + +#elif defined(RD_88F6082MICRO_DAS_NAS) + + /* Invert SATA indecation polarety and set LED to blink */ + ldr r6, =0x9 + MV_REG_WRITE_ASM (r6, r1, 0x6002C) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /*DDR SDRAM set pad drive */ + MV_REG_READ_ASM (r6, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + orr r6, r6, #0x80000000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + orr r6, r6, #0x3000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + bic r6, r6, #0x80000000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + MV_REG_READ_ASM (r6, r1, SDRAM_DATA_PADS_CAL_REG) + orr r6, r6, #0x80000000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_DATA_PADS_CAL_REG) + orr r6, r6, #0x3000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_DATA_PADS_CAL_REG) + bic r6, r6, #0x80000000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_DATA_PADS_CAL_REG) + +#ifdef MV_INC_DRAM_MFG_TEST + /* DDR MFG test */ + bl _mvDramMfgTest +#endif + + b done + +#elif defined(RD_88F6082GE_SATA) + /* Set SATA LED to blink */ + ldr r6, =0x1 + MV_REG_WRITE_ASM (r6, r1, 0x6002C) + + /* init MPP */ + ldr r6, =RD_88F6082_GE_SATA_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =RD_88F6082_GE_SATA_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + + /* init GPP , disable HDD power */ + MV_REG_READ_ASM (r6, r1, 0x10100) + and r6, r6, #(1 << 10) + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /* init GPP , Out enable */ + ldr r6, =RD_88F6082_GE_SATA_OE + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + b done + +#elif defined(DB_88F6082BP) + /* Set SATA LED to blink */ + ldr r6, =0x1 + MV_REG_WRITE_ASM (r6, r1, 0x6002C) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /*DDR SDRAM set pad drive */ + MV_REG_READ_ASM (r6, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + orr r6, r6, #0x80000000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + orr r6, r6, #0x3000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + bic r6, r6, #0x80000000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + MV_REG_READ_ASM (r6, r1, SDRAM_DATA_PADS_CAL_REG) + orr r6, r6, #0x80000000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_DATA_PADS_CAL_REG) + orr r6, r6, #0x3000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_DATA_PADS_CAL_REG) + bic r6, r6, #0x80000000 + MV_REG_WRITE_ASM (r6, r1, SDRAM_DATA_PADS_CAL_REG) + + b done + +#elif defined(DB_88F6082LBP) + /* Set SATA LED to blink */ + ldr r6, =0x1 + MV_REG_WRITE_ASM (r6, r1, 0x6002C) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + b done + +#elif defined(RD_88F6082_DX243) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + b done + +#endif + +#else /* #if !defined(MV_INC_BOARD_DDIM) */ + +/* First jump to the new board release without the board ID on the TWSI */ +#if defined(MV_88F5082) + b db_88f5082_ddr2 +#elif defined(MV_88F1281) + b db_88f1281_ddr2 +#elif defined(MV_88F5182) + b db_88f5182_ddr2 +#elif defined(DB_88F5181) + b db_88f5x81_ddrx +#elif defined(RD_DB_88F5181L) + b db_88f5181L_ddr2 +#elif defined(MV_88W8660) + b db_88w8660_ddr2 +#elif defined(MV_88F5180N) + b db_88f5180n_ddrx +#elif defined(MV_88F6082) + b db_88f6082_sa +#elif defined(MV_88F6183) ||defined(MV_88F6183L) + b db_88f6183_bp +#else + cmp r7, #DB_88F5181_5281_DDR1 + beq db_88f5181_5281_ddr1 + cmp r7, #DB_88F5181_5281_DDR2 + beq db_88f5181_5281_ddr2 +#endif + + +#if defined(MV_88F5082) + +db_88f5082_ddr2: + /* Set SATA LED to blink */ + ldr r6, =0x1 + MV_REG_WRITE_ASM (r6, r1, 0x8002C) + + /* init MPP */ + ldr r6, =DB_88F5082_DDR2_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F5082_DDR2_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =DB_88F5082_DDR2_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + + /* turn 7segment to val 1 - Set DevCS0- window 6 is the default*/ + ldr r6, =0x8FCFFFFF + MV_REG_WRITE_ASM (r6, r1, 0x1045C) + ldr r6, =0x000F1E11 + MV_REG_WRITE_ASM (r6, r1, 0x20050) + ldr r6, =0xE0000000 + MV_REG_WRITE_ASM (r6, r1, 0x20054) + + + ldr r6, =0xE0000010 /* DevCS0 Default base address +0x10 */ + ldr r6, [r6] + + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + /* Set dram width to 16bit */ + MV_REG_READ_ASM (r6, r1, 0x1400) + bic r6, r6, #0xc000 + orr r6, r6, #0x4000 + MV_REG_WRITE_ASM (r6, r1, 0x1400) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* Load r3 with the size to open SDRAM bank 0 */ + mov r3, #0x04000000 /* Open DRAM bank 0 to 64MB */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + + ldr r6, =0xE0000020 /* DevCS0 Default base address +0x20 */ + ldr r6, [r6] + + b done + + +#elif defined(MV_88F5182) + +db_88f5182_ddr2: + + /* init MPP */ + ldr r6, =DB_88F5182_DDR2_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F5182_DDR2_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =DB_88F5182_DDR2_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + + /* turn 7segment to val 1 - Set DevCS0- window 6 is the default*/ + ldr r6, =0x8FCFFFFF + MV_REG_WRITE_ASM (r6, r1, 0x1045C) + ldr r6, =0x000F1E11 + MV_REG_WRITE_ASM (r6, r1, 0x20050) + ldr r6, =0xE0000000 + MV_REG_WRITE_ASM (r6, r1, 0x20054) + + + ldr r6, =0xE0000010 /* DevCS0 Default base address +0x10 */ + ldr r6, [r6] + + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + /* Set dram width to 16bit */ + MV_REG_READ_ASM (r6, r1, 0x1400) + bic r6, r6, #0xc000 + orr r6, r6, #0x4000 + MV_REG_WRITE_ASM (r6, r1, 0x1400) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* Load r3 with the size to open SDRAM bank 0 */ + mov r3, #0x04000000 /* Open DRAM bank 0 to 64MB */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + + ldr r6, =0xE0000020 /* DevCS0 Default base address +0x20 */ + ldr r6, [r6] + + b done + +#elif defined(MV_88F1281) + +db_88f1281_ddr2: + + /* init MPP */ + ldr r6, =DB_88F1281_DDR2_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F1281_DDR2_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + /* init GPP , Out enable */ + ldr r6, =DB_88F1281_DDR2_OE + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /* turn Led to 1 */ + ldr r6, =0x4 + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* Load r3 with the size to open SDRAM bank 0 */ + mov r3, #0x04000000 /* Open DRAM bank 0 to 64MB */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + + b done + +#elif defined(RD_DB_88F5181L) + +db_88f5181L_ddr2: + + /* init MPP */ + ldr r6, =DB_88F5181L_DDR2_2XTDM_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F5181L_DDR2_2XTDM_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =DB_88F5181L_DDR2_2XTDM_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =DB_88F5181L_DDR2_2XTDM_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* turn 7segment to val 1 - Set DevCS0- window 6 is the default*/ + ldr r6, =0x8FCFFFFF + MV_REG_WRITE_ASM (r6, r1, 0x1045C) + ldr r6, =0x000F1E11 + MV_REG_WRITE_ASM (r6, r1, 0x20050) + ldr r6, =0xE0000000 + MV_REG_WRITE_ASM (r6, r1, 0x20054) + + + ldr r6, =0xE0000010 /* DevCS0 Default base address +0x10 */ + ldr r6, [r6] + + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* Load r3 with the size to open SDRAM bank 0 */ + mov r3, #0x04000000 /* Open DRAM bank 0 to 64MB */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + + ldr r6, =0xE0000020 /* DevCS0 Default base address +0x20 */ + ldr r6, [r6] + + b done + + +#elif defined(MV_88F6183) || defined(MV_88F6183L) +db_88f6183_bp: + +#if defined(MV_INC_BOARD_SPI_FLASH) + /* configure the Prescale of SPI clk Tclk = 166MHz */ + MV_REG_READ_ASM (r6, r1, MV_SPI_IF_CONFIG_REG) + and r6, r6, #~MV_SPI_CLK_PRESCALE_MASK + orr r6, r6, #0x14 + MV_REG_WRITE_ASM (r6, r1, MV_SPI_IF_CONFIG_REG) +#endif + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, 0x1480) + +1: MV_REG_READ_ASM (r6, r1, 0x1480) + cmp r6, #0 + bne 1b + + /* Load r3 with the size to open SDRAM bank 0 */ + mov r3, #0x04000000 /* Open DRAM bank 0 to 64MB */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + + b done + +#elif defined(MV_88W8660) + +db_88w8660_ddr2: + /* init MPP */ + ldr r6, =DB_88W8660_DDR2_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88W8660_DDR2_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + + /* turn 7segment to val 1 - Set DevCS0- window 6 is the default*/ + ldr r6, =0x8FCFFFFF + MV_REG_WRITE_ASM (r6, r1, 0x1045C) + ldr r6, =0x000F1E11 + MV_REG_WRITE_ASM (r6, r1, 0x20050) + ldr r6, =0xE0000000 + MV_REG_WRITE_ASM (r6, r1, 0x20054) + + + ldr r6, =0xE0000010 /* DevCS0 Default base address +0x10 */ + ldr r6, [r6] + + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* Load r3 with the size to open SDRAM bank 0 */ + mov r3, #0x04000000 /* Open DRAM bank 0 to 64MB */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + + ldr r6, =0xE0000020 /* DevCS0 Default base address +0x20 */ + ldr r6, [r6] + + b done + +#elif defined(MV_88F5180N) +db_88f5180n_ddrx: + + /* init MPP */ + ldr r6, =DB_88F5180N_DDRX_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F5180N_DDRX_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =DB_88F5180N_DDRX_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =DB_88F5180N_DDRX_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* turn 7segment to val 1 - Set DevCS0- window 6 is the default*/ + ldr r6, =0x8FCFFFFF + MV_REG_WRITE_ASM (r6, r1, 0x1045C) + ldr r6, =0x000F1E11 + MV_REG_WRITE_ASM (r6, r1, 0x20050) + ldr r6, =0xE0000000 + MV_REG_WRITE_ASM (r6, r1, 0x20054) + + + ldr r6, =0xE0000010 /* DevCS0 Default base address +0x10 */ + ldr r6, [r6] + + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* Load r3 with the size to open SDRAM bank 0 */ + mov r3, #0x04000000 /* Open DRAM bank 0 to 64MB */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + + ldr r6, =0xE0000020 /* DevCS0 Default base address +0x20 */ + ldr r6, [r6] + + b done + +#elif defined(MV_88F6082) +db_88f6082_sa: + /* init MPP */ + ldr r6, =DB_88F6082_SA_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F6082_SA_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + + /* init GPP , Out enable */ + ldr r6, =DB_88F6082_SA_OE + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* Load r3 with the size to open SDRAM bank 0 */ + mov r3, #0x04000000 /* Open DRAM bank 0 to 64MB */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + + ldr r6, =0xE0000020 /* DevCS0 Default base address +0x20 */ + ldr r6, [r6] + + b done +#else + +db_88f5181_5281_ddr1: /*old board*/ + + /* init MPP */ + ldr r6, =DB_88F5181_5281_DDR1_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F5181_5281_DDR1_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =DB_88F5181_5281_DDR1_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =DB_88F5181_5281_DDR1_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + + /* turn 7segment to val 1 - Set DevCS2- window 6 is the default*/ + ldr r6, =0x8FCFFFFF + MV_REG_WRITE_ASM (r6, r1, 0x10464) + ldr r6, =0x000F1B11 + MV_REG_WRITE_ASM (r6, r1, 0x20060) + ldr r6, =0xF0000000 + MV_REG_WRITE_ASM (r6, r1, 0x20064) + + + ldr r6, =0xF0000010 /* DevCS2 Default base address +0x10 */ + ldr r6, [r6] + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* Load r3 with the size to open SDRAM bank 0 */ + mov r3, #0x04000000 /* Open DRAM bank 0 to 64MB */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + #if 0 + ldr r6, =0xF0000020 /* DevCS2 Default base address +0x20 */ + ldr r6, [r6] + #endif + + b done + +db_88f5181_5281_ddr2: /*old board*/ + + /* init MPP */ + ldr r6, =DB_88F5181_5281_DDR2_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F5181_5281_DDR2_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =DB_88F5181_5281_DDR2_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =DB_88F5181_5281_DDR2_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* init GPP , Out enable */ + ldr r6, =0xFFFF3F3F + MV_REG_WRITE_ASM (r6, r1, 0x10104) + + /* turn Led to 1 */ + ldr r6, =0x00004000 + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* Load r3 with the size to open SDRAM bank 0 */ + mov r3, #0x04000000 /* Open DRAM bank 0 to 64MB */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + + /* turn Led to 2 */ + ldr r6, =0x00008000 + MV_REG_WRITE_ASM (r6, r1, 0x10100) + + b done + +db_88f5x81_ddrx: + + /* init MPP */ + ldr r6, =DB_88F5X81_DDRX_MPP0_7 + MV_REG_WRITE_ASM (r6, r1, 0x10000) + ldr r6, =DB_88F5X81_DDRX_MPP8_15 + MV_REG_WRITE_ASM (r6, r1, 0x10004) + ldr r6, =DB_88F5X81_DDRX_MPP16_23 + MV_REG_WRITE_ASM (r6, r1, 0x10050) + ldr r6, =DB_88F5X81_DDRX_MPP_DEV + MV_REG_WRITE_ASM (r6, r1, 0x10008) + + /* turn 7segment to val 1 - Set DevCS0- window 6 is the default*/ + ldr r6, =0x8FCFFFFF + MV_REG_WRITE_ASM (r6, r1, 0x1045C) + ldr r6, =0x000F1E11 + MV_REG_WRITE_ASM (r6, r1, 0x20050) + ldr r6, =0xE0000000 + MV_REG_WRITE_ASM (r6, r1, 0x20054) + + ldr r6, =0xE0000010 /* DevCS0 Default base address +0x10 */ + ldr r6, [r6] + + /* PCI ARBITER */ + ldr r6, =0x80000030 + MV_REG_WRITE_ASM (r6, r1, 0x31d00) + + /*DDR SDRAM Initialization Control */ + ldr r6, =0x00000001 + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +1: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + cmp r6, #0 + bne 1b + + /* Load r3 with the size to open SDRAM bank 0 */ + mov r3, #0x04000000 /* Open DRAM bank 0 to 64MB */ + + /* Call DRAM basic initialization to allow C runtime stack */ + bl _mvDramIfBasicInit + + ldr r6, =0xE0000020 /* DevCS0 Default base address +0x20 */ + ldr r6, [r6] + + b done +#endif + + +#endif /*#if !defined(MV_INC_BOARD_DDIM)*/ +done: + mov lr, r2 + + + /* All done by Integrator's boot monitor! */ + mov pc, lr + + + .globl _mvDramMfgTest + +_mvDramMfgTest: + + mov r11, lr /* Save link register */ + + ldr r3,=0x55555555 + ldr r7,=0x0 + ldr r8,=0x0 + +mem_test: + /* memory test for the U-Boot space */ + + ldr r4,= 0 + ldr r5,= 0x400000 + +fill_mem: + str r3, [r4] + add r4, r4, #4 + cmp r4, r5 + bne fill_mem + + ldr r4,= 0 + +check_mem: + ldr r6, [r4] + cmp r6, r3 + bne fail_mem + add r4, r4, #4 + cmp r4, r5 + bne check_mem + + cmp r8, #0x0 + bne next_test + ldr r3,=0xAAAAAAAA + add r8, r8, #1 + b mem_test + +next_test: + /* Undo walking 1 or 0 */ + b pass_mem + cmp r8, #0x1 + bne next_test1 + /* walking 1 */ + mov r3, r8, LSL r7 + add r7, r7, #1 + cmp r7, #0x32 + bne mem_test + + add r8, r8, #1 + eor r7, r7, r7 + ldr r3,=0x7FFFFFFF + +next_test1: + cmp r8, #0x2 + bne pass_mem + /* walking 0 */ + mov r3, r3, ROR r7 + add r7, r7, #1 + cmp r7, #0x32 + bne mem_test + +pass_mem: + mov lr, r11 + mov pc, lr + +fail_mem: + /* Error Message */ + bl _mvDramMfgFailMes +fail_mem1: + b fail_mem1 + + .globl _mvDramMfgFailMes + +_mvDramMfgFailMes: + + mov r11, lr /* Save link register */ + + ldr r2, =(INTER_REGS_BASE + 0x12000); + + mov r1, #10 + strb r1, [r2] + mov r1, #13 + strb r1, [r2] + mov r1, #'M' + strb r1, [r2] + mov r1, #'F' + strb r1, [r2] + mov r1, #'G' + strb r1, [r2] + mov r1, #' ' + strb r1, [r2] + mov r1, #'D' + strb r1, [r2] + mov r1, #'R' + strb r1, [r2] + mov r1, #'A' + strb r1, [r2] + mov r1, #'M' + strb r1, [r2] + mov r1, #' ' + strb r1, [r2] + mov r1, #'F' + strb r1, [r2] + mov r1, #'A' + strb r1, [r2] + mov r1, #'I' + strb r1, [r2] + mov r1, #'L' + strb r1, [r2] + mov r1, #'!' + strb r1, [r2] + mov lr, r11 + mov pc, lr + diff --git a/board/mv_feroceon/uboot_oss/mvOs.c b/board/mv_feroceon/uboot_oss/mvOs.c new file mode 100644 index 0000000..77f15e1 --- /dev/null +++ b/board/mv_feroceon/uboot_oss/mvOs.c @@ -0,0 +1,248 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +*******************************************************************************/ +/******************************************************************************* +* mvOsCpuArchLib.c - Marvell CPU architecture library +* +* DESCRIPTION: +* This library introduce Marvell API for OS dependent CPU architecture +* APIs. This library introduce single CPU architecture services APKI +* cross OS. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#include +#include "mvOs.h" + +static MV_U32 read_p15_c0 (void); + +/* defines */ +#define ARM_ID_REVISION_OFFS 0 +#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) + +#define ARM_ID_PART_NUM_OFFS 4 +#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) + +#define ARM_ID_ARCH_OFFS 16 +#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) + +#define ARM_ID_VAR_OFFS 20 +#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) + +#define ARM_ID_ASCII_OFFS 24 +#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) + + +/******************************************************************************* +* mvOsCpuVerGet() - +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit CPU Revision +* +*******************************************************************************/ +MV_U32 mvOsCpuRevGet( MV_VOID ) +{ + return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); +} +/******************************************************************************* +* mvOsCpuPartGet() - +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit CPU Part number +* +*******************************************************************************/ +MV_U32 mvOsCpuPartGet( MV_VOID ) +{ + return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); +} +/******************************************************************************* +* mvOsCpuArchGet() - +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit CPU Architicture number +* +*******************************************************************************/ +MV_U32 mvOsCpuArchGet( MV_VOID ) +{ + return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); +} +/******************************************************************************* +* mvOsCpuVarGet() - +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit CPU Variant number +* +*******************************************************************************/ +MV_U32 mvOsCpuVarGet( MV_VOID ) +{ + return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); +} +/******************************************************************************* +* mvOsCpuAsciiGet() - +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit CPU Variant number +* +*******************************************************************************/ +MV_U32 mvOsCpuAsciiGet( MV_VOID ) +{ + return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); +} + + + +/* +static unsigned long read_p15_c0 (void) +*/ +/* read co-processor 15, register #0 (ID register) */ +static MV_U32 read_p15_c0 (void) +{ + MV_U32 value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + + return value; +} + + +MV_U32 mvOsIoVirtToPhy( void* pDev, void* pVirtAddr ) +{ + return (MV_U32)pVirtAddr; +} + +void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32* memHandle) +{ + *pPhyAddr = (MV_ULONG)malloc(size); + return (void *)(*pPhyAddr); +} + +void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle) +{ + free(pVirtAddr); +} + +void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32* memHandle) +{ + *pPhyAddr = (MV_ULONG)malloc(size); + return (void *)(*pPhyAddr); +} + +void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle) +{ + free(pVirtAddr); +} + +MV_U32 mvOsCacheFlush( void* osHandle, void* p, int size ) +{ + return (MV_U32)p;/* ronen - need to be filled */ +} + +MV_U32 mvOsCacheInvalidate( void* osHandle, void* p, int size ) +{ + return (MV_U32)p;/* ronen - need to be filled */ +} + +int mvOsRand(void) +{ + return 0; +} + +int mvOsStrCmp(const char *str1,const char *str2) +{ + + do + { + if ((*str1++) != (*str2++)) return 1; /* not equal */ + + } + while ((*str1 != '\0') && (*str2 != '\0')); + + if (*str1 != *str2) return 1; /* not equal */ + + /* equal */ + return 0; + +} + +#if defined(REG_DEBUG) +extern int reg_arry[REG_ARRAY_SIZE][2]; +extern int reg_arry_index; +void reglog(unsigned int offset, unsigned int data) +{ + reg_arry[reg_arry_index%REG_ARRAY_SIZE][0] = (offset); + reg_arry[reg_arry_index%REG_ARRAY_SIZE][1] = (data); + reg_arry_index++; +} +#endif diff --git a/board/mv_feroceon/uboot_oss/mvOs.h b/board/mv_feroceon/uboot_oss/mvOs.h new file mode 100644 index 0000000..bb036c9 --- /dev/null +++ b/board/mv_feroceon/uboot_oss/mvOs.h @@ -0,0 +1,363 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef MV_OS_H +#define MV_OS_H + +/*************/ +/* Includes */ +/*************/ + +#include "mvTypes.h" +#include "mvCommon.h" +#include +#include +#include "mvSysHwConfig.h" +#include "mvCtrlEnvSpec.h" + + + +#ifdef __cplusplus +extern "C" { +#endif + +/*************/ +/* Constants */ +/*************/ + +#define MV_OS_WAIT_FOREVER 0 + +/*************/ +/* Datatypes */ +/*************/ + +#define CPU_PHY_MEM(x) (MV_U32)x +#define CPU_MEMIO_CACHED_ADDR(x) (void*)x +#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x + + +/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ +#define MV_MEMIO32_WRITE(addr, data) \ + ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) + +#define MV_MEMIO32_READ(addr) \ + ((*((volatile unsigned int*)(addr)))) + +#define MV_MEMIO16_WRITE(addr, data) \ + ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) + +#define MV_MEMIO16_READ(addr) \ + ((*((volatile unsigned short*)(addr)))) + +#define MV_MEMIO8_WRITE(addr, data) \ + ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) + +#define MV_MEMIO8_READ(addr) \ + ((*((volatile unsigned char*)(addr)))) + + +/* No Fast Swap implementation (in assembler) for ARM */ +#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) +#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) +#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) +#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) + +/* 32 and 16 bit read/write in big/little endian mode */ + +/* 16bit write in little endian mode */ +#define MV_MEMIO_LE16_WRITE(addr, data) \ + MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) + +/* 16bit read in little endian mode */ +static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) +{ + MV_U16 data; + + data= (MV_U16)MV_MEMIO16_READ(addr); + + return (MV_U16)MV_16BIT_LE_FAST(data); +} + +/* 32bit write in little endian mode */ +#define MV_MEMIO_LE32_WRITE(addr, data) \ + MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) + +/* 32bit read in little endian mode */ +static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) +{ + MV_U32 data; + + data= (MV_U32)MV_MEMIO32_READ(addr); + + return (MV_U32)MV_32BIT_LE_FAST(data); +} + +/****************************************************************************** +* This debug function enable the write of each register that u-boot access to +* to an array in the DRAM, the function record only MV_REG_WRITE access. +* The function could not be operate when booting from flash. +* In order to print the array we use the printreg command. +******************************************************************************/ +/* #define REG_DEBUG */ +#if defined(REG_DEBUG) +#define REG_ARRAY_SIZE 4096 +extern int reg_arry[REG_ARRAY_SIZE][2]; +extern int reg_arry_index; + +void reglog(unsigned int offset, unsigned int data); +#endif + +/* Marvell controller register read/write macros */ +#define MV_REG_VALUE(offset) \ + (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) + +#define MV_REG_READ(offset) \ + (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) + +#if defined(REG_DEBUG) +#define MV_REG_WRITE(offset, val) \ + MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ + reglog((INTER_REGS_BASE | (offset)), (val)); +#else +#define MV_REG_WRITE(offset, val) \ + MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); +#endif + +#if defined(REG_DEBUG) +#define MV_REG_WORD_WRITE(offset, val) \ + MV_MEMIO_LE16_WRITE((INTER_REGS_BASE | (offset)), (val)); \ + reglog((INTER_REGS_BASE | (offset)), (val)); +#else +#define MV_REG_WORD_WRITE(offset, val) \ + MV_MEMIO_LE16_WRITE((INTER_REGS_BASE | (offset)), (val)) +#endif + +#define MV_REG_WORD_READ(offset) \ + (MV_MEMIO16_READ((INTER_REGS_BASE | (offset)))) + +#define MV_REG_BYTE_READ(offset) \ + (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) + +#if defined(REG_DEBUG) +#define MV_REG_BYTE_WRITE(offset, val) \ + MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ + reglog((INTER_REGS_BASE | (offset)), (val)); +#else +#define MV_REG_BYTE_WRITE(offset, val) \ + MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) +#endif + +#if defined(REG_DEBUG) +#define MV_REG_BIT_SET(offset, bitMask) \ + (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ + (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ + MV_32BIT_LE_FAST(bitMask)))); \ + reglog((INTER_REGS_BASE | (offset)), (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)))); +#else +#define MV_REG_BIT_SET(offset, bitMask) \ + (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ + (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ + MV_32BIT_LE_FAST(bitMask)))) +#endif + +#if defined(REG_DEBUG) +#define MV_REG_BIT_RESET(offset,bitMask) \ + (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ + (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ + MV_32BIT_LE_FAST(~bitMask)))); \ + reglog((INTER_REGS_BASE | (offset)), (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)))); +#else +#define MV_REG_BIT_RESET(offset,bitMask) \ + (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ + (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ + MV_32BIT_LE_FAST(~bitMask)))) +#endif + + +/* Flash APIs */ +#define MV_FL_8_READ MV_MEMIO8_READ +#define MV_FL_16_READ MV_MEMIO_LE16_READ +#define MV_FL_32_READ MV_MEMIO_LE32_READ +#define MV_FL_8_DATA_READ MV_MEMIO8_READ +#define MV_FL_16_DATA_READ MV_MEMIO16_READ +#define MV_FL_32_DATA_READ MV_MEMIO32_READ +#define MV_FL_8_WRITE MV_MEMIO8_WRITE +#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE +#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE +#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE +#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE +#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE + + +/* CPU cache information */ +#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ +#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ + + +/* Data cache flush one line */ +#define mvOsCacheLineFlushInv(handle, addr) +#define mvOsCacheLineInv(handle, addr) +/* Flush CPU pipe */ +#define CPU_PIPE_FLUSH + +#define INLINE inline +#define mvOsSPrintf sprintf + +/* In order to minimize image size printf, is defined as NULL */ + +#ifdef MV_RT_DEBUG +# define mvOsPrintf printf +#else +# define mvOsPrintf(fmt,args...) +#endif /* MV_RT_DEBUG */ + +#define mvOsOutput printf +#define mvOsMalloc malloc +#define mvOsFree free +#define mvOsMemcpy memcpy +#define mvOsDelay(ms) udelay(ms*1000) +#define mvOsSleep(us) mvOsDelay(us) +#define mvOsTaskLock() +#define mvOsTaskUnlock() +#define mvOsIntLock() 0 +#define mvOsIntUnlock(key) +#define mvOsUDelay(x) udelay(x) + +#define strtol simple_strtoul + +#define mvOsDivide(num, div) \ +({ \ + int i=0, rem=(num); \ + \ + while(rem >= (div)) \ + { \ + rem -= (div); \ + i++; \ + } \ + (i); \ +}) + +#define mvOsReminder(num, div) \ +({ \ + int rem = (num); \ + \ + while(rem >= (div)) \ + rem -= (div); \ + (rem); \ +}) + +#if defined(MV_BRIDGE_SYNC_REORDER) +extern MV_U32 *mvUncachedParam; + +static INLINE void mvOsBridgeReorderWA(void) +{ + /* sync write reordering in the bridge */ + volatile MV_U32 val = 0; + + val = mvUncachedParam[0]; +} +#endif + +static INLINE void mvOsBCopy(MV_U8* srcAddr, MV_U8* dstAddr, int byteCount) + +{ + + while(byteCount != 0) + + { + + *dstAddr = *srcAddr; + + dstAddr++; + + srcAddr++; + + byteCount--; + + } + +} + +/* ARM architecture APIs */ +MV_U32 mvOsCpuRevGet (MV_VOID); +MV_U32 mvOsCpuPartGet (MV_VOID); +MV_U32 mvOsCpuArchGet (MV_VOID); +MV_U32 mvOsCpuVarGet (MV_VOID); +MV_U32 mvOsCpuAsciiGet (MV_VOID); +MV_U32 mvOsIoVirtToPhy( void* osHandle, void* pVirtAddr ); +void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32* memHandle); +void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle); +void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32* memHandle); +void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle); +MV_U32 mvOsCacheFlush( void* osHandle, void* p, int size ); +MV_U32 mvOsCacheInvalidate( void* osHandle, void* p, int size ); +int mvOsRand(void); +int mvOsStrCmp(const char *str1,const char *str2); + +#ifdef __cplusplus +} +#endif + +#endif /* MV_OS_H */ diff --git a/board/mv_feroceon/uboot_oss/mvOsAsm.h b/board/mv_feroceon/uboot_oss/mvOsAsm.h new file mode 100644 index 0000000..ca33ee2 --- /dev/null +++ b/board/mv_feroceon/uboot_oss/mvOsAsm.h @@ -0,0 +1,134 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvOsAsmh +#define __INCmvOsAsmh + + +#include "mvCommon.h" + +#if defined(MV_MIPS) + #define CPU_FAMILY MIPS + #include "asm.h" + +#elif defined (MV_PPC) + #define CPU_FAMILY PPC + #include + #include <74xx_7xx.h> + #include + #include + #include + #include + +#elif defined (MV_ARM) + #define CPU_FAMILY ARM + #include + +/* BE/ LE swap for Asm */ +#if defined(MV_CPU_LE) + +#define htoll(x) x +#define HTOLL(sr,tr) + +#elif defined(MV_CPU_BE) + +#define htoll(x) ((((x) & 0x00ff) << 24) | \ + (((x) & 0xff00) << 8) | \ + (((x) >> 8) & 0xff00) | \ + (((x) >> 24) & 0x00ff)) + + +#define HTOLL(sr,temp) /*sr = A ,B ,C ,D */\ + eor temp, sr, sr, ROR #16 ; /*temp = A^C,B^D,C^A,D^B */\ + bic temp, temp, #0xFF0000 ; /*temp = A^C,0 ,C^A,D^B */\ + mov sr, sr, ROR #8 ; /*sr = D ,A ,B ,C */\ + eor sr, sr, temp, LSR #8 /*sr = D ,C ,B ,A */ + +#endif + +#define MV_REG_READ_ASM(toReg, tmpReg, regOffs) \ + ldr tmpReg, =(INTER_REGS_BASE + regOffs) ; \ + ldr toReg, [tmpReg] ; \ + HTOLL(toReg,tmpReg) + +#define MV_REG_WRITE_ASM(fromReg, tmpReg, regOffs) \ + HTOLL(fromReg,tmpReg) ; \ + ldr tmpReg, =(INTER_REGS_BASE + regOffs) ; \ + str fromReg, [tmpReg] + +#define MV_DV_REG_READ_ASM(toReg, tmpReg, regOffs) \ + ldr tmpReg, =(CFG_DFL_MV_REGS + regOffs) ; \ + ldr toReg, [tmpReg] ; \ + HTOLL(toReg,tmpReg) + +#define MV_DV_REG_WRITE_ASM(fromReg, tmpReg, regOffs) \ + HTOLL(fromReg,tmpReg) ; \ + ldr tmpReg, =(CFG_DFL_MV_REGS + regOffs) ; \ + str fromReg, [tmpReg] + +#else + #error "CPU type not selected" +#endif + +#endif /* __INCmvOsAsmh */ diff --git a/board/mv_feroceon/uboot_oss/mvOsSata.c b/board/mv_feroceon/uboot_oss/mvOsSata.c new file mode 100644 index 0000000..cc457a4 --- /dev/null +++ b/board/mv_feroceon/uboot_oss/mvOsSata.c @@ -0,0 +1,31 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include "mvOsSata.h" + +MV_U16 mvSwapShort(MV_U16 data) +{ + return MV_CPU_TO_LE16(data); +} +MV_U32 mvSwapWord(MV_U32 data) +{ + return MV_CPU_TO_LE32(data); +} + diff --git a/board/mv_feroceon/uboot_oss/mvOsSata.h b/board/mv_feroceon/uboot_oss/mvOsSata.h new file mode 100644 index 0000000..2b4ca01 --- /dev/null +++ b/board/mv_feroceon/uboot_oss/mvOsSata.h @@ -0,0 +1,194 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvOsBios.h - O.S. interface header file for BIOS IAL +* +* DESCRIPTION: +* This header file contains OS dependent definition for BIOS +* +* DEPENDENCIES: +* +* FILE REVISION NUMBER: +* $Revision: 1.7 $ +*******************************************************************************/ + +#ifndef __INCmvOsSUBooth +#define __INCmvOsSUBooth + +#include "mvTypes.h" +#include "mvOs.h" + +/* Definitions */ +#if defined (LOG_DEBUG) || defined (LOG_ERROR) + #define PRNTHEXTSINGLE + #define DEBUG_IAL + #define DEBUG_IAL_SERIAL +#endif + +#if defined(REG_DEBUG) +extern int reg_arry[REG_ARRAY_SIZE][2]; +extern int reg_arry_index; +#endif + +/* + * Override CORE Driver SW queue size to 1. The CORE Driver SW queue is not + * used for issuing UDMA commands; so minimizing this to 1 makes it possible + * to minimize footprint of BIOS Extension driver when statically allocating + * the channel's data structures. + */ +#define MV_SATA_OVERRIDE_SW_QUEUE_SIZE +#define MV_SATA_REQUESTED_SW_QUEUE_SIZE 1 + + +#define MV_REGS_ACCESSED_BY_IO_BAR +/* System dependent macro for flushing CPU write cache */ +#define MV_CPU_WRITE_BUFFER_FLUSH() + +/* System dependent register read / write in byte/word/dword variants */ +unsigned long readRegister (unsigned long base, unsigned long offset); +void writeRegister (unsigned long base, unsigned long offset, unsigned long value); +/*void pioWrite16bit (unsigned short offset, unsigned short data); +unsigned short pioRead16bit (unsigned short offset);*/ +void waitForKeystroke (void); +unsigned short readSegmentOffset16bit (unsigned short segment_, unsigned short offset_); +unsigned char readSegmentOffset8bit (unsigned short segment_, unsigned short offset_); +void writeSegmentOffset16bit (unsigned short segment_, unsigned short offset_, unsigned short value_); +void writeSegmentOffset8bit (unsigned short segment_, unsigned short offset_, unsigned char value_); +void memcpySegmentOffset32bitForward (unsigned short segment_, + unsigned short destinationOffset_, + unsigned short sourceOffset_, + unsigned short byteCount_); + + +MV_U16 mvSwapShort(MV_U16 data); +MV_U32 mvSwapWord(MV_U32 data); + +#ifdef PRNTHEXTSINGLE +void printHexSingle(char *fmt, unsigned short value_); +#else + #define printHexSingle(x,y) +#endif + +/* System dependent little endian from / to CPU conversions */ +#if (_BYTE_ORDER == _BIG_ENDIAN) +# define MV_CPU_TO_LE16(x) MV_16BIT_LE(x) +# define MV_CPU_TO_LE32(x) MV_32BIT_LE(x) + +# define MV_LE16_TO_CPU(x) MV_16BIT_LE(x) +# define MV_LE32_TO_CPU(x) MV_32BIT_LE(x) +#else +# define MV_CPU_TO_LE16(x) (x) +# define MV_CPU_TO_LE32(x) (x) + +# define MV_LE16_TO_CPU(x) (x) +# define MV_LE32_TO_CPU(x) (x) +#endif + + +/* System dependent register read / write in byte/word/dword variants */ +/* Write 32/16/8 bit NonCacheable */ +#if defined(REG_DEBUG) +#define MV_WRITE_CHAR(address, data) \ + ((*((volatile unsigned char *)(address)))= \ + ((unsigned char)(data))); \ + reglog((address), (data)); +#else +#define MV_WRITE_CHAR(address, data) \ + ((*((volatile unsigned char *)(address)))= \ + ((unsigned char)(data))) +#endif + +#if defined(REG_DEBUG) +#define MV_WRITE_SHORT(address, data) \ + ((*((volatile unsigned short *)(address))) = \ + ((unsigned short)(data))); \ + reglog((address), (data)); +#else +#define MV_WRITE_SHORT(address, data) \ + ((*((volatile unsigned short *)(address))) = \ + ((unsigned short)(data))) +#endif + +#if defined(REG_DEBUG) +#define MV_WRITE_WORD(address, data) \ + ((*((volatile unsigned int *)(address))) = \ + ((unsigned int)(data))); \ + reglog((address), (data)); +#else +#define MV_WRITE_WORD(address, data) \ + ((*((volatile unsigned int *)(address))) = \ + ((unsigned int)(data))) +#endif + +/* Read 32/16/8 bit NonCacheable - returns data direct. */ + +#define MV_READCHAR(address) \ + ((*((volatile unsigned char *)(address)))) + +#define MV_READSHORT(address) \ + ((*((volatile unsigned short *)(address)))) + +#define MV_READWORD(address) \ + ((*((volatile unsigned int *)(address)))) + +#define MV_REG_WRITE_BYTE(base, offset, val) MV_WRITE_CHAR(base + offset, val) +#define MV_REG_WRITE_WORD(base, offset, val) MV_WRITE_SHORT(base + offset, MV_CPU_TO_LE16(val)) +#define MV_REG_WRITE_DWORD(base, offset, val) MV_WRITE_WORD(base + offset, MV_CPU_TO_LE32(val)) +#define MV_REG_READ_BYTE(base, offset) MV_READCHAR(base + offset) +#define MV_REG_READ_WORD(base, offset) mvSwapShort(MV_READSHORT(base + offset)) +#define MV_REG_READ_DWORD(base, offset) mvSwapWord(MV_READWORD(base + offset)) + + +/* System dependant typedefs */ +typedef void *MV_VOID_PTR; +typedef unsigned long *MV_U32_PTR; +typedef unsigned short *MV_U16_PTR; +typedef unsigned char *MV_U8_PTR; +typedef char *MV_CHAR_PTR; +typedef unsigned long MV_BUS_ADDR_T; +typedef unsigned long MV_CPU_FLAGS; + +/* Structures */ +/* System dependent structure */ +typedef struct mvOsSemaphore +{ + unsigned long lock; + unsigned long flags; +} MV_OS_SEMAPHORE; + +/* Typedefs */ +typedef enum mvBoolean +{ + MV_SFALSE, MV_STRUE +} MV_BOOLEAN; + + +/* Functions (User implemented)*/ +#include "sata/CoreDriver/mvLog.h" + +/* Semaphore init, take and release */ +#define mvOsSemInit(x) MV_TRUE +#define mvOsSemTake(x) +#define mvOsSemRelease(x) + +/* Delay function in micro seconds resolution */ +#define mvMicroSecondsDelay(dummy, time) udelay(time) + +#endif /* __INCmvOsSUBooth */ diff --git a/board/mvblue/Makefile b/board/mvblue/Makefile deleted file mode 100644 index 24dc026..0000000 --- a/board/mvblue/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o -SOBJS = - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/mvblue/config.mk b/board/mvblue/config.mk deleted file mode 100644 index 6e0ce4e..0000000 --- a/board/mvblue/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2001-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/mvblue/flash.c b/board/mvblue/flash.c deleted file mode 100644 index 8df573a..0000000 --- a/board/mvblue/flash.c +++ /dev/null @@ -1,583 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2001-2003 - * - * Changes for MATRIX Vision mvBLUE devices - * MATRIX Vision GmbH / hg,as info@matrix-vision.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if 0 - #define mvdebug(p) printf ##p -#else - #define mvdebug(p) -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -#define FLASH_BUS_WIDTH 8 - -#if (FLASH_BUS_WIDTH==32) - #define FLASH_DATA_MASK 0xffffffff - #define FLASH_SHIFT 1 - #define FDT vu_long -#elif (FLASH_BUS_WIDTH==16) - #define FLASH_DATA_MASK 0xff - #define FLASH_SHIFT 0 - #define FDT vu_short -#elif (FLASH_BUS_WIDTH==8) - #define FLASH_DATA_MASK 0xff - #define FLASH_SHIFT 0 - #define FDT vu_char -#else - #error FLASH_BUS_WIDTH undefined -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *address, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - - for (i=0; iflash_id & FLASH_BTYPE) - { /* bottom boot sector types - these are the useful ones! */ - /* set sector offsets for bottom boot block type */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) - { /* AMDLV320B has 8 x 8k bottom boot sectors */ - for (i = 0; i < 8; i++) /* +8k */ - info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); - for (; i < info->sector_count; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT); - } - else - { /* other types have 4 bottom boot sectors (16,8,8,32) */ - i = 0; - info->start[i++] = base + 0x00000000; /* - */ - info->start[i++] = base + (0x00004000 << FLASH_SHIFT); /* +16k */ - info->start[i++] = base + (0x00006000 << FLASH_SHIFT); /* +8k */ - info->start[i++] = base + (0x00008000 << FLASH_SHIFT); /* +8k */ - info->start[i++] = base + (0x00010000 << FLASH_SHIFT); /* +32k */ - for (; i < info->sector_count; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT); - } - } - else - { /* top boot sector types - not so useful */ - /* set sector offsets for top boot block type */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) - { /* AMDLV320T has 8 x 8k top boot sectors */ - for (i = 0; i < info->sector_count - 8; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); - for (; i < info->sector_count; i++) /* +8k */ - info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); - } - else - { /* other types have 4 top boot sectors (32,8,8,16) */ - for (i = 0; i < info->sector_count - 4; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); - - info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT); /* -32k */ - info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT); /* -8k */ - info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT); /* -8k */ - info->start[i] = base + info->size - (0x00004000 << FLASH_SHIFT); /* -16k */ - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_STM: printf ("ST "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_STMW320DB: printf ("M29W320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_STMW320DT: printf ("M29W320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ - -#define AMD_ID_LV160T_MVS (AMD_ID_LV160T & FLASH_DATA_MASK) -#define AMD_ID_LV160B_MVS (AMD_ID_LV160B & FLASH_DATA_MASK) -#define AMD_ID_LV320T_MVS (AMD_ID_LV320T & FLASH_DATA_MASK) -#define AMD_ID_LV320B_MVS (AMD_ID_LV320B & FLASH_DATA_MASK) -#define STM_ID_W320DT_MVS (STM_ID_29W320DT & FLASH_DATA_MASK) -#define STM_ID_W320DB_MVS (STM_ID_29W320DB & FLASH_DATA_MASK) -#define AMD_MANUFACT_MVS (AMD_MANUFACT & FLASH_DATA_MASK) -#define FUJ_MANUFACT_MVS (FUJ_MANUFACT & FLASH_DATA_MASK) -#define STM_MANUFACT_MVS (STM_MANUFACT & FLASH_DATA_MASK) - -#if (FLASH_BUS_WIDTH >= 16) - #define AUTOSELECT_ADDR1 0x0555 - #define AUTOSELECT_ADDR2 0x02AA - #define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1 -#else - #define AUTOSELECT_ADDR1 0x0AAA - #define AUTOSELECT_ADDR2 0x0555 - #define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1 -#endif - -#define AUTOSELECT_DATA1 (0x00AA00AA & FLASH_DATA_MASK) -#define AUTOSELECT_DATA2 (0x00550055 & FLASH_DATA_MASK) -#define AUTOSELECT_DATA3 (0x00900090 & FLASH_DATA_MASK) - -#define RESET_BANK_DATA (0x00F000F0 & FLASH_DATA_MASK) - - -static ulong flash_get_size (vu_long *address, flash_info_t *info) -{ - short i; - FDT value; - FDT *addr = (FDT *)address; - - ulong base = (ulong)address; - addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1; - addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2; - addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3; - __asm__ __volatile__("sync"); - - udelay(180); - - value = addr[0]; /* manufacturer ID */ - switch (value) { - case AMD_MANUFACT_MVS: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT_MVS: - info->flash_id = FLASH_MAN_FUJ; - break; - case STM_MANUFACT_MVS: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } -#if (FLASH_BUS_WIDTH >= 16) - value = addr[1]; /* device ID */ -#else - value = addr[2]; /* device ID */ -#endif - - switch (value) { - case AMD_ID_LV160T_MVS: - info->flash_id += FLASH_AM160T; - info->sector_count = 37; - info->size = (0x00200000 << FLASH_SHIFT); - break; /* => 2 or 4 MB */ - - case AMD_ID_LV160B_MVS: - info->flash_id += FLASH_AM160B; - info->sector_count = 37; - info->size = (0x00200000 << FLASH_SHIFT); - break; /* => 2 or 4 MB */ - - case AMD_ID_LV320T_MVS: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8 MB */ - - case AMD_ID_LV320B_MVS: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8MB */ - - case STM_ID_W320DT_MVS: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8 MB */ - - case STM_ID_W320DB_MVS: - info->flash_id += FLASH_STMW320DB; - info->sector_count = 67; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - flash_get_offsets (base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (FDT *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (FDT *)info->start[0]; - *addr = RESET_BANK_DATA; /* reset bank */ - } - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -#if (FLASH_BUS_WIDTH >= 16) - #define ERASE_ADDR1 0x0555 - #define ERASE_ADDR2 0x02AA -#else - #define ERASE_ADDR1 0x0AAA - #define ERASE_ADDR2 0x0555 -#endif - -#define ERASE_ADDR3 ERASE_ADDR1 -#define ERASE_ADDR4 ERASE_ADDR1 -#define ERASE_ADDR5 ERASE_ADDR2 - -#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK) -#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK) -#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK) -#define ERASE_DATA4 ERASE_DATA1 -#define ERASE_DATA5 ERASE_DATA2 - -#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK) -#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK) -#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK) - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FDT *addr = (FDT *)(info->start[0]); - - int prot, sect, l_sect, flag; - ulong start, now, last; - - __asm__ __volatile__ ("sync"); - addr[0] = 0xf0; - udelay(1000); - - printf("\nflash_erase: first = %d @ 0x%08lx\n", s_first, info->start[s_first] ); - printf(" last = %d @ 0x%08lx\n", s_last , info->start[s_last ] ); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ERASE_ADDR1] = ERASE_DATA1; - addr[ERASE_ADDR2] = ERASE_DATA2; - addr[ERASE_ADDR3] = ERASE_DATA3; - addr[ERASE_ADDR4] = ERASE_DATA4; - addr[ERASE_ADDR5] = ERASE_DATA5; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { - addr = (FDT *)(info->start[sect]); - addr[0] = ERASE_SECTOR_DATA; - l_sect = sect; - } - } - - if (flag) - enable_interrupts(); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FDT *)(info->start[l_sect]); - - while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ -#define BUFF_INC 4 - ulong cp, wp, data; - int i, l, rc; - - mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt)); - - wp = (addr & ~3); /* get lower word aligned address */ - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - mvdebug ((" handle unaligned start bytes (cnt = 0x%08lx)\n", cnt)); - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= BUFF_INC) { - data = 0; - for (i=0; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i= 16) - #define WRITE_ADDR1 0x0555 - #define WRITE_ADDR2 0x02AA -#else - #define WRITE_ADDR1 0x0AAA - #define WRITE_ADDR2 0x0555 - #define WRITE_ADDR3 WRITE_ADDR1 -#endif - -#define WRITE_DATA1 (0x00AA00AA & FLASH_DATA_MASK) -#define WRITE_DATA2 (0x00550055 & FLASH_DATA_MASK) -#define WRITE_DATA3 (0x00A000A0 & FLASH_DATA_MASK) - -#define WRITE_CONFIRM_DATA ERASE_CONFIRM_DATA - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_char (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *)dest) & data) != data) { - printf(" *** ERROR: Flash not erased !\n"); - return (2); - } - flag = disable_interrupts(); - - addr[WRITE_ADDR1] = WRITE_DATA1; - addr[WRITE_ADDR2] = WRITE_DATA2; - addr[WRITE_ADDR3] = WRITE_DATA3; - *((vu_char *)dest) = data; - - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - addr = (vu_char *)dest; - while (( (*addr) & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - printf(" *** ERROR: Flash write timeout !"); - return (1); - } - } - mvdebug (("-write_byte\n")); - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - int i, - result = 0; - - mvdebug (("+write_word : 0x%08lx @ 0x%08lx\n", data, dest)); - for ( i=0; (i < 4) && (result == 0); i++, dest+=1 ) - result = write_char (info, dest, (data >> (8*(3-i))) & 0xff ); - mvdebug (("-write_word\n")); - return result; -} -/*---------------------------------------------------------------- */ diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c deleted file mode 100644 index 20a551d..0000000 --- a/board/mvblue/mvblue.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * GNU General Public License for more details. - * - * MATRIX Vision GmbH / June 2002-Nov 2003 - * Andre Schwarz - */ - -#include -#include -#include -#include - -#ifdef CONFIG_PCI -#include -#endif - -u32 get_BoardType (void); - -#define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \ - | ((d&0x1f)<<11) \ - | ((f&0x7)<<7) \ - | (r&0xfc) ) - -int mv_pci_read (int bus, int dev, int func, int reg) -{ - *(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg); - asm ("sync"); - return cpu_to_le32 (*(u32 *) (0xfee00cfc)); -} - -u32 get_BoardType () -{ - return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1); -} - -void init_2nd_DUART (void) -{ - NS16550_t console = (NS16550_t) CFG_NS16550_COM2; - int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE; - - *(u8 *) (0xfc004511) = 0x1; - NS16550_init (console, clock_divisor); -} -void hw_watchdog_reset (void) -{ - if (get_BoardType () == 0) { - *(u32 *) (0xff000005) = 0; - asm ("sync"); - } -} -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - ulong busfreq = get_bus_freq (0); - char buf[32]; - u32 BoardType = get_BoardType (); - char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" }; - char *p; - bd_t *bd = gd->bd; - - hw_watchdog_reset (); - - printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION); - printf (" Found %s running at %s MHz memory clock.\n", - BoardName[BoardType], strmhz (buf, busfreq)); - - init_2nd_DUART (); - - if ((p = getenv ("console_nr")) != NULL) { - unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3; - - bd->bi_baudrate &= ~3; - bd->bi_baudrate |= con_nr & 3; - } - return 0; -} - -long int initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* ------------------------------------------------------------------------- */ -u8 *dhcp_vendorex_prep (u8 * e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - if ((ptr = getenv ("dhcp_vendor-class-identifier"))) { - *e++ = 60; - *e++ = strlen (ptr); - while (*ptr) - *e++ = *ptr++; - } - /* my DHCP_CLIENT_IDENTIFIER = 61 */ - if ((ptr = getenv ("dhcp_client_id"))) { - *e++ = 61; - *e++ = strlen (ptr); - while (*ptr) - *e++ = *ptr++; - } - return e; -} - -u8 *dhcp_vendorex_proc (u8 * popt) -{ - return NULL; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Initialize PCI Devices - */ -#ifdef CONFIG_PCI -void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev) -{ - u32 cnt; - - printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev), - PCI_FUNC (dev)); - for (cnt = 0; cnt < 6; cnt++) - pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt), - 0x0); - printf ("done\n"); -} - -void duart_setup (u32 base, u16 divisor) -{ - printf ("duart setup ..."); - out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80); - out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff); - out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8); - out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03); - out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03); - out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07); - printf ("done\n"); -} - -void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose, - pci_dev_t bridge, unsigned char irq) -{ - pci_dev_t d; - unsigned char bus; - unsigned short vendor, class; - - pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus); - for (d = PCI_BDF (bus, 0, 0); - d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1, - PCI_MAX_PCI_FUNCTIONS - 1); - d += PCI_BDF (0, 0, 1)) { - pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor); - if (vendor != 0xffff && vendor != 0x0000) { - pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE, - &class); - if (class == PCI_CLASS_BRIDGE_PCI) - pci_mvblue_fixup_irq_behind_bridge (hose, d, - irq); - else - pci_hose_write_config_byte (hose, d, - PCI_INTERRUPT_LINE, - irq); - } - } -} - -#define MV_MAX_PCI_BUSSES 3 -#define SLOT0_IRQ 3 -#define SLOT1_IRQ 4 -void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char line = 0xff; - unsigned short class; - - if (PCI_BUS (dev) == 0) { - switch (PCI_DEV (dev)) { - case 0xd: - if (get_BoardType () == 0) { - line = 1; - } else - /* mvBL */ - line = 2; - break; - case 0xe: - /* mvBB: IDE */ - line = 2; - pci_hose_write_config_byte (hose, dev, 0x8a, 0x20); - break; - case 0xf: - /* mvBB: Slot0 (Grabber) */ - pci_hose_read_config_word (hose, dev, - PCI_CLASS_DEVICE, &class); - if (class == PCI_CLASS_BRIDGE_PCI) { - pci_mvblue_fixup_irq_behind_bridge (hose, dev, - SLOT0_IRQ); - line = 0xff; - } else - line = SLOT0_IRQ; - break; - case 0x10: - /* mvBB: Slot1 */ - pci_hose_read_config_word (hose, dev, - PCI_CLASS_DEVICE, &class); - if (class == PCI_CLASS_BRIDGE_PCI) { - pci_mvblue_fixup_irq_behind_bridge (hose, dev, - SLOT1_IRQ); - line = 0xff; - } else - line = SLOT1_IRQ; - break; - default: - printf ("***pci_scan: illegal dev = 0x%08x\n", - PCI_DEV (dev)); - line = 0xff; - break; - } - pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, - line); - } -} - -struct pci_controller hose = { - fixup_irq:pci_mvblue_fixup_irq -}; - -void pci_init_board (void) -{ - pci_mpc824x_init (&hose); -} -#endif diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds deleted file mode 100644 index 7c05109..0000000 --- a/board/mvblue/u-boot.lds +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mvs1/Makefile b/board/mvs1/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/mvs1/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/mvs1/README b/board/mvs1/README deleted file mode 100644 index 69520bd..0000000 --- a/board/mvs1/README +++ /dev/null @@ -1,14 +0,0 @@ -This port is for the MATRIX Vision mvSensor. -It is an mpc823-based universal image processing board -with CMOS or CCD sensor, 4MB FLASH and 16-64MB RAM. - -See http://www.matrix-vision.de for more details or mail... - -mvsensor@matrix-vision.de - -Howard Gray -MATRIX Vision GmbH -Talstr. 16 -D-71570 -Oppenweiler -Germany diff --git a/board/mvs1/config.mk b/board/mvs1/config.mk deleted file mode 100644 index 9d6080b..0000000 --- a/board/mvs1/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TQM8xxL boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/mvs1/flash.c b/board/mvs1/flash.c deleted file mode 100644 index 0845943..0000000 --- a/board/mvs1/flash.c +++ /dev/null @@ -1,719 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Changes for MATRIX Vision MVsensor (C) Copyright 2001 - * MATRIX Vision GmbH / hg, info@matrix-vision.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#undef MVDEBUG -#ifdef MVDEBUG -#define mvdebug debug -#else -#define mvdebug(p) do {} while (0) -#endif - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -#ifdef CONFIG_MVS_16BIT_FLASH - #define FLASH_DATA_MASK 0xffff - #define FLASH_SHIFT 0 -#else - #define FLASH_DATA_MASK 0xffffffff - #define FLASH_SHIFT 1 -#endif - - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *address, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } -#else - size_b1 = 0; -#endif - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); -#ifdef CONFIG_MVS_16BIT_FLASH - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; -#else - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_GPCM | BR_V; -#endif - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE+monitor_flash_len-1, - &flash_info[0]); - - if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); -#ifdef CONFIG_MVS_16BIT_FLASH - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_PS_16 | BR_MS_GPCM | BR_V; -#else - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_PS_32 | BR_MS_GPCM | BR_V; -#endif - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE+monitor_flash_len-1, - &flash_info[1]); - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) - { /* bottom boot sector types - these are the useful ones! */ - /* set sector offsets for bottom boot block type */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) - { /* AMDLV320B has 8 x 8k bottom boot sectors */ - for (i = 0; i < 8; i++) /* +8k */ - info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); - for (; i < info->sector_count; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT); - } - else - { /* other types have 4 bottom boot sectors (16,8,8,32) */ - i = 0; - info->start[i++] = base + 0x00000000; /* - */ - info->start[i++] = base + (0x00004000 << FLASH_SHIFT); /* +16k */ - info->start[i++] = base + (0x00006000 << FLASH_SHIFT); /* +8k */ - info->start[i++] = base + (0x00008000 << FLASH_SHIFT); /* +8k */ - info->start[i++] = base + (0x00010000 << FLASH_SHIFT); /* +32k */ - for (; i < info->sector_count; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT); - } - } - else - { /* top boot sector types - not so useful */ - /* set sector offsets for top boot block type */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) - { /* AMDLV320T has 8 x 8k top boot sectors */ - for (i = 0; i < info->sector_count - 8; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); - for (; i < info->sector_count; i++) /* +8k */ - info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT)); - } - else - { /* other types have 4 top boot sectors (32,8,8,16) */ - for (i = 0; i < info->sector_count - 4; i++) /* +64k */ - info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)); - - info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT); /* -32k */ - info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT); /* -8k */ - info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT); /* -8k */ - info->start[i] = base + info->size - (0x00004000 << FLASH_SHIFT); /* -16k */ - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_STM: printf ("ST "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_STMW320DB: printf ("M29W320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_STMW320DT: printf ("M29W320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -#define AMD_ID_LV160T_MVS (AMD_ID_LV160T & FLASH_DATA_MASK) -#define AMD_ID_LV160B_MVS (AMD_ID_LV160B & FLASH_DATA_MASK) -#define AMD_ID_LV320T_MVS (AMD_ID_LV320T & FLASH_DATA_MASK) -#define AMD_ID_LV320B_MVS (AMD_ID_LV320B & FLASH_DATA_MASK) -#define STM_ID_W320DT_MVS (STM_ID_29W320DT & FLASH_DATA_MASK) -#define STM_ID_W320DB_MVS (STM_ID_29W320DB & FLASH_DATA_MASK) -#define AMD_MANUFACT_MVS (AMD_MANUFACT & FLASH_DATA_MASK) -#define FUJ_MANUFACT_MVS (FUJ_MANUFACT & FLASH_DATA_MASK) -#define STM_MANUFACT_MVS (STM_MANUFACT & FLASH_DATA_MASK) - -#define AUTOSELECT_ADDR1 0x0555 -#define AUTOSELECT_ADDR2 0x02AA -#define AUTOSELECT_ADDR3 AUTOSELECT_ADDR1 - -#define AUTOSELECT_DATA1 (0x00AA00AA & FLASH_DATA_MASK) -#define AUTOSELECT_DATA2 (0x00550055 & FLASH_DATA_MASK) -#define AUTOSELECT_DATA3 (0x00900090 & FLASH_DATA_MASK) - -#define RESET_BANK_DATA (0x00F000F0 & FLASH_DATA_MASK) - -static ulong flash_get_size (vu_long *address, flash_info_t *info) -{ - short i; -#ifdef CONFIG_MVS_16BIT_FLASH - ushort value; - vu_short *addr = (vu_short *)address; -#else - ulong value; - vu_long *addr = (vu_long *)address; -#endif - ulong base = (ulong)address; - - /* Write auto select command: read Manufacturer ID */ - addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1; - addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2; - addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3; - - value = addr[0]; /* manufacturer ID */ - switch (value) { - case AMD_MANUFACT_MVS: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT_MVS: - info->flash_id = FLASH_MAN_FUJ; - break; - case STM_MANUFACT_MVS: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - switch (value) { - case AMD_ID_LV160T_MVS: - info->flash_id += FLASH_AM160T; - info->sector_count = 37; - info->size = (0x00200000 << FLASH_SHIFT); - break; /* => 2 or 4 MB */ - - case AMD_ID_LV160B_MVS: - info->flash_id += FLASH_AM160B; - info->sector_count = 37; - info->size = (0x00200000 << FLASH_SHIFT); - break; /* => 2 or 4 MB */ - - case AMD_ID_LV320T_MVS: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8 MB */ - - case AMD_ID_LV320B_MVS: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8MB */ - - case STM_ID_W320DT_MVS: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8 MB */ - - case STM_ID_W320DB_MVS: - info->flash_id += FLASH_STMW320DB; - info->sector_count = 67; - info->size = (0x00400000 << FLASH_SHIFT); - break; /* => 4 or 8MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - flash_get_offsets (base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ -#ifdef CONFIG_MVS_16BIT_FLASH - addr = (vu_short *)(info->start[i]); -#else - addr = (vu_long *)(info->start[i]); -#endif - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { -#ifdef CONFIG_MVS_16BIT_FLASH - addr = (vu_short *)info->start[0]; -#else - addr = (vu_long *)info->start[0]; -#endif - *addr = RESET_BANK_DATA; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -#define ERASE_ADDR1 0x0555 -#define ERASE_ADDR2 0x02AA -#define ERASE_ADDR3 ERASE_ADDR1 -#define ERASE_ADDR4 ERASE_ADDR1 -#define ERASE_ADDR5 ERASE_ADDR2 - -#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK) -#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK) -#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK) -#define ERASE_DATA4 ERASE_DATA1 -#define ERASE_DATA5 ERASE_DATA2 - -#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK) -#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK) -#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK) - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ -#ifdef CONFIG_MVS_16BIT_FLASH - vu_short *addr = (vu_short *)(info->start[0]); -#else - vu_long *addr = (vu_long *)(info->start[0]); -#endif - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ERASE_ADDR1] = ERASE_DATA1; - addr[ERASE_ADDR2] = ERASE_DATA2; - addr[ERASE_ADDR3] = ERASE_DATA3; - addr[ERASE_ADDR4] = ERASE_DATA4; - addr[ERASE_ADDR5] = ERASE_DATA5; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ -#ifdef CONFIG_MVS_16BIT_FLASH - addr = (vu_short *)(info->start[sect]); -#else - addr = (vu_long *)(info->start[sect]); -#endif - addr[0] = ERASE_SECTOR_DATA; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; -#ifdef CONFIG_MVS_16BIT_FLASH - addr = (vu_short *)(info->start[l_sect]); -#else - addr = (vu_long *)(info->start[l_sect]); -#endif - while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ -#ifdef CONFIG_MVS_16BIT_FLASH - addr = (vu_short *)info->start[0]; -#else - addr = (vu_long *)info->start[0]; -#endif - addr[0] = RESET_BANK_DATA; /* reset bank */ - - printf (" done\n"); - return 0; -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ -#define BUFF_INC 4 - ulong cp, wp, data; - int i, l, rc; - - mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt)); - - wp = (addr & ~3); /* get lower word aligned address */ - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - mvdebug ((" handle unaligned start bytes (cnt = 0x%08%lx)\n", cnt)); - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= BUFF_INC) { - data = 0; - for (i=0; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; istart[0]); - ulong start; - int flag; - - mvdebug (("+write_word (to 0x%08lx)\n", dest)); - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[WRITE_ADDR1] = WRITE_DATA1; - addr[WRITE_ADDR2] = WRITE_DATA2; - addr[WRITE_ADDR3] = WRITE_DATA3; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - addr = (vu_long *)dest; - while ((*addr & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - mvdebug (("-write_word\n")); - return (0); -} -#else /* CONFIG_MVS_16BIT_FLASH */ -/*----------------------------------------------------------------------- - * Write a halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_halfword (flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *)(info->start[0]); - ulong start; - int flag; - - mvdebug (("+write_halfword (to 0x%08lx)\n", dest)); - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[WRITE_ADDR1] = WRITE_DATA1; - addr[WRITE_ADDR2] = WRITE_DATA2; - addr[WRITE_ADDR3] = WRITE_DATA3; - - *((vu_short *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - addr = (vu_short *)dest; - while ((*addr & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - mvdebug (("-write_halfword\n")); - return (0); -} - - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - int result = 0; - - if (write_halfword (info, dest, (data & ~FLASH_DATA_MASK) >> 16) == 0) - { - dest += 2; - data = data & FLASH_DATA_MASK; - result = write_halfword (info, dest, data); - } - return result; -} -#endif -/*----------------------------------------------------------------------- - */ diff --git a/board/mvs1/mvs1.c b/board/mvs1/mvs1.c deleted file mode 100644 index f8a8cb7..0000000 --- a/board/mvs1/mvs1.c +++ /dev/null @@ -1,376 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Changes for MATRIX Vision MVsensor (C) Copyright 2001 - * MATRIX Vision GmbH / hg, info@matrix-vision.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, - 0x1FF5FC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F0DFC04 /*0x1F2DFC04??*/, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: MATRIX Vision MVsensor\n"); - return 0; -} - - -#ifdef DO_RAM_TEST -/* ------------------------------------------------------------------------- */ - -/* - * Test SDRAM by writing its address to itself and reading several times -*/ -#define READ_RUNS 4 -static void test_dram (unsigned long *start, unsigned long *end) -{ - unsigned long *addr; - unsigned long value; - int read_runs, errors, addr_errors; - - printf ("\nChecking SDRAM from %p to %p\n", start, end); - udelay (1000000); - for (addr = start; addr < end; addr++) - *addr = (unsigned long) addr; - - for (addr = start, addr_errors = 0; addr < end; addr++) { - for (read_runs = READ_RUNS, errors = 0; read_runs > 0; read_runs--) { - if ((value = *addr) != (unsigned long) addr) - errors++; - } - if (errors > 0) { - addr_errors++; - printf ("SDRAM errors (%d) at %p, last read = %ld\n", - errors, addr, value); - udelay (10000); - } - } - printf ("SDRAM check finished, total errors = %d\n", addr_errors); -} -#endif /* DO_RAM_TEST */ - - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size_b1, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; - -#if defined (CFG_OR3_PRELIM) && defined (CFG_BR3_PRELIM) - if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - } -#endif - - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ - memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */ - udelay (1); - } - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); - } - - if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ - /* - * Check Bank 1 Memory Size - * use current column settings - * [9 column SDRAM may also be used in 8 column mode, - * but then only half the real size will be used.] - */ -#if defined (SDRAM_BASE3_PRELIM) - size_b1 = - dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); -#else - size_b1 = 0; -#endif - } else { - size_b1 = 0; - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - - memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b0 > 0) { - /* - * Position Bank 0 immediately above Bank 1 - */ - memctl->memc_or2 = - ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b1; - } else { - unsigned long reg; - - /* - * No bank 0 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - } else { /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or3 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b0; - } else { - unsigned long reg; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - } - - udelay (10000); - -#ifdef DO_RAM_TEST - if (size_b0 > 0) - test_dram ((unsigned long *) CFG_SDRAM_BASE, - (unsigned long *) (CFG_SDRAM_BASE + size_b0)); -#endif - - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - - -/* ------------------------------------------------------------------------- */ - -u8 *dhcp_vendorex_prep (u8 * e) -{ - char *ptr; - -/* DHCP vendor-class-identifier = 60 */ - if ((ptr = getenv ("dhcp_vendor-class-identifier"))) { - *e++ = 60; - *e++ = strlen (ptr); - while (*ptr) - *e++ = *ptr++; - } -/* my DHCP_CLIENT_IDENTIFIER = 61 */ - if ((ptr = getenv ("dhcp_client_id"))) { - *e++ = 61; - *e++ = strlen (ptr); - while (*ptr) - *e++ = *ptr++; - } - - return e; -} - - -/* ------------------------------------------------------------------------- */ -u8 *dhcp_vendorex_proc (u8 * popt) -{ - return NULL; -} diff --git a/board/mvs1/u-boot.lds b/board/mvs1/u-boot.lds deleted file mode 100644 index a04de3d..0000000 --- a/board/mvs1/u-boot.lds +++ /dev/null @@ -1,145 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_generic/ctype.o (.text) - lib_generic/string.o (.text) - lib_ppc/extable.o (.text) - lib_ppc/kgdb.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mvs1/u-boot.lds.debug b/board/mvs1/u-boot.lds.debug deleted file mode 100644 index ddd4678..0000000 --- a/board/mvs1/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile deleted file mode 100644 index 3e805fe..0000000 --- a/board/mx1ads/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# board/mx1ads/Makefile -# -# (c) Copyright 2004 -# Techware Information Technology, Inc. -# http://www.techware.com.tw/ -# -# Ming-Len Wu -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := mx1ads.o syncflash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mx1ads/config.mk b/board/mx1ads/config.mk deleted file mode 100644 index f6ac40d..0000000 --- a/board/mx1ads/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# board/mx1ads/config.mk -# -# (c) Copyright 2004 -# Techware Information Technology, Inc. -# http://www.techware.com.tw/ -# -# Ming-Len Wu -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -TEXT_BASE = 0x08400000 diff --git a/board/mx1ads/lowlevel_init.S b/board/mx1ads/lowlevel_init.S deleted file mode 100644 index 09c260d..0000000 --- a/board/mx1ads/lowlevel_init.S +++ /dev/null @@ -1,81 +0,0 @@ -/* - * board/mx1ads/lowlevel_init.S - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define SDCTL0 0x221000 -#define SDCTL1 0x221004 - - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevel_init -lowlevel_init: -/* memory controller init */ - - ldr r1, =SDCTL0 - -/* Set Precharge Command */ - - ldr r3, =0x92120200 -/* ldr r3, =0x92120251 -*/ - str r3, [r1] - -/* Issue Precharge All Commad */ - ldr r3, =0x8200000 - ldr r2, [r3] - -/* Set AutoRefresh Command */ - ldr r3, =0xA2120200 - str r3, [r1] - -/* Issue AutoRefresh Command */ - ldr r3, =0x8000000 - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - -/* Set Mode Register */ - ldr r3, =0xB2120200 - str r3, [r1] - -/* Issue Mode Register Command */ - ldr r3, =0x08111800 /* Mode Register Value */ - ldr r2, [r3] - -/* Set Normal Mode */ - ldr r3, =0x82124200 - str r3, [r1] - -/* everything is fine now */ - mov pc, lr diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c deleted file mode 100644 index 5c33ba3..0000000 --- a/board/mx1ads/mx1ads.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * board/mx1ads/mx1ads.c - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -/*#include */ -#include - -/* ------------------------------------------------------------------------- */ - -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -#if 0 - -static inline void delay (unsigned long loops) { - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -#endif - -/* - * Miscellaneous platform dependent initialisations - */ - -void SetAsynchMode(void) { - __asm__ ( - "mrc p15,0,r0,c1,c0,0 \n" - "mov r2, #0xC0000000 \n" - "orr r0,r2,r0 \n" - "mcr p15,0,r0,c1,c0,0 \n" - ); -} - -static u32 mc9328sid; - -int board_init (void) { - - DECLARE_GLOBAL_DATA_PTR; - - volatile unsigned int tmp; - - mc9328sid = SIDR; - - GPCR = 0x000003AB; /* I/O pad driving strength */ - -/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ -/* MX1_CS1L = 0x11110601; */ - - MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ - -/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and - * BCLK divider to 2 (i.e. BCLK to 48 MHz) - */ - CSCR = 0xAF000403; - - CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ - CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ - -/* setup cs4 for cs8900 ethernet */ - - CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ - CS4L = 0x00001501; - - GIUS(0) &= 0xFF3FFFFF; - GPR(0) &= 0xFF3FFFFF; - - tmp = *(unsigned int *)(0x1500000C); - tmp = *(unsigned int *)(0x1500000C); - - SetAsynchMode(); - - gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; - - gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ - - icache_enable(); - dcache_enable(); - -/* set PERCLKs */ - PCDR = 0x00000055; /* set PERCLKS */ - -/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes - * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place - * all sources selected as normal interrupt - */ - -/* MX1_INTTYPEH = 0; - MX1_INTTYPEL = 0; -*/ - return 0; -} - -int board_late_init(void) { - - setenv("stdout", "serial"); - setenv("stderr", "serial"); - - switch (mc9328sid) { - case 0x0005901d : - printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid); - break; - case 0x04d4c01d : - printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid); - break; - case 0x00d4c01d : - printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid); - break; - - default : - printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid); - break; - } - return 0; -} - -int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c deleted file mode 100644 index eb7fde5..0000000 --- a/board/mx1ads/syncflash.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * board/mx1ads/syncflash.c - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -/*#include */ -#include - -typedef unsigned long * p_u32; - -/* 4Mx16x2 IAM=0 CSD1 */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Following Setting is for CSD1 */ -#define SFCTL 0x00221004 -#define reg_SFCTL __REG(SFCTL) - -#define SYNCFLASH_A10 (0x00100000) - -#define CMD_NORMAL (0x81020300) /* Normal Mode */ -#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ -#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ -#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ -#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ -#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) - -#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ - -/* LCR Command */ -#define LCR_READSTATUS (0x0001C000) /* 0x70 */ -#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ -#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ -#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ -#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ - -/* Get Status register */ -u32 SF_SR(void) { - u32 tmp,tmp1; - - reg_SFCTL = CMD_PROGRAM; - tmp = __REG(CFG_FLASH_BASE); - - reg_SFCTL = CMD_NORMAL; - - reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ - tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR); - - return tmp; -} - -/* check if SyncFlash is ready */ -u8 SF_Ready(void) { - u32 tmp; - - tmp = SF_SR(); - - if ((tmp & 0x00800000) && (tmp & 0x001C0000)) { - printf ("SyncFlash Error code %08x\n",tmp); - }; - - if ((tmp & 0x00000080) && (tmp & 0x0000001C)) { - printf ("SyncFlash Error code %08x\n",tmp); - }; - - if (tmp == 0x00800080) /* Test Bit 7 of SR */ - return 1; - else - return 0; -} - -/* Issue the precharge all command */ -void SF_PrechargeAll(void) { - - u32 tmp; - - reg_SFCTL = CMD_PREC; /* Set Precharge Command */ - tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */ -} - -/* set SyncFlash to normal mode */ -void SF_Normal(void) { - - SF_PrechargeAll(); - - reg_SFCTL = CMD_NORMAL; -} - -/* Erase SyncFlash */ -void SF_Erase(u32 RowAddress) { - u32 tmp; - - reg_SFCTL = CMD_NORMAL; - tmp = __REG(RowAddress); - - reg_SFCTL = CMD_PREC; - tmp = __REG(RowAddress); - - reg_SFCTL = CMD_LCR; /* Set LCR mode */ - __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ - - reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ - __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ - - while(!SF_Ready()); -} - -void SF_NvmodeErase(void) { - SF_PrechargeAll(); - - reg_SFCTL = CMD_LCR; /* Set to LCR mode */ - __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ - - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ - - while(!SF_Ready()); -} - -void SF_NvmodeWrite(void) { - SF_PrechargeAll(); - - reg_SFCTL = CMD_LCR; /* Set to LCR mode */ - __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ - - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ -} - -/****************************************************************************************/ - -ulong flash_init(void) { - int i, j; - u32 tmp; - -/* Turn on CSD1 for negating RESETSF of SyncFLash */ - - reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */ - udelay(200); - - reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ - tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ - - SF_Normal(); - - i = 0; - - flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000; - } - - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); - - return FLASH_BANK_SIZE; -} - -void flash_print_info (flash_info_t *info) { - - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (FLASH_MAN_MT & FLASH_VENDMASK): - printf("Micron: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (FLASH_MT28S4M16LC & FLASH_TYPEMASK): - printf("2x FLASH_MT28S4M16LC (16MB Total)\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses: "); - - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) - printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*-----------------------------------------------------------------------*/ - -int flash_erase (flash_info_t *info, int s_first, int s_last) { - int iflag, cflag, prot, sect; - int rc = ERR_OK; - -/* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) - return ERR_INVAL; - - if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - prot = 0; - - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("protected!\n"); - return ERR_PROTECTED; - } -/* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status(); - icache_disable(); - iflag = disable_interrupts(); - -/* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc(); sect++) { - - printf("Erasing sector %2d ... ", sect); - -/* arm simple, non interrupt dependent timer */ - - reset_timer_masked(); - - SF_NvmodeErase(); - SF_NvmodeWrite(); - - SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect)); - SF_Normal(); - - printf("ok.\n"); - } - - if (ctrlc()) - printf("User Interrupt!\n"); - - if (iflag) - enable_interrupts(); - - if (cflag) - icache_enable(); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { - int i; - - for(i = 0; i < cnt; i += 4) { - - SF_PrechargeAll(); - - reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */ - __REG(addr + i) = __REG((u32)src + i); - - while(!SF_Ready()); - } - - SF_Normal(); - - return ERR_OK; -} diff --git a/board/mx1ads/u-boot.lds b/board/mx1ads/u-boot.lds deleted file mode 100644 index 8438f99..0000000 --- a/board/mx1ads/u-boot.lds +++ /dev/null @@ -1,58 +0,0 @@ -/* - * board/mx1ads/u-boot.lds - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/mx1fs2/Makefile b/board/mx1fs2/Makefile deleted file mode 100644 index 9e3bca1..0000000 --- a/board/mx1fs2/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := mx1fs2.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mx1fs2/config.mk b/board/mx1fs2/config.mk deleted file mode 100644 index 59ab542..0000000 --- a/board/mx1fs2/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# This config file is used for compilation of IMX sources -# -# You might change location of U-Boot in memory by setting right TEXT_BASE. -# This allows for example having one copy located at the end of ram and stored -# in flash device and later on while developing use other location to test -# the code in RAM device only. -# - -TEXT_BASE = 0x08f00000 diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c deleted file mode 100644 index 3806310..0000000 --- a/board/mx1fs2/flash.c +++ /dev/null @@ -1,849 +0,0 @@ -/* - * (C) 2000-2004 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) 2003 August Hoeraendl, Logotronic GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#undef CONFIG_FLASH_16BIT - -#include - -#define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE -#define MAIN_SECT_SIZE MX1FS2_FLASH_SECT_SIZE - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -#if 0 -static ulong flash_get_size(FPWV * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); -#endif -static void flash_reset(flash_info_t * info); -static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data); -static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data); -#define write_word(in, de, da) write_word_amd(in, de, da) -#ifdef CFG_FLASH_PROTECTION -static void flash_sync_real_protect(flash_info_t * info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -ulong -flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - flash_info[i].flash_id = - (FLASH_MAN_AMD & FLASH_VENDMASK) | - (FLASH_AM640U & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - switch (i) { - case 0: - flashbase = MX1FS2_FLASH_BASE; - break; - default: - panic("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _bss_start - _armboot_start, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void -flash_reset(flash_info_t * info) -{ - FPWV *base = (FPWV *) (info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW) 0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -#if 0 -static void -flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof (FPW) / 2); - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set up sector start address table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sect_size); - } -} -#endif /* 0 */ - -/*----------------------------------------------------------------------- - */ - -void -flash_print_info(flash_info_t * info) -{ - int i; - uchar *boottype; - uchar *bootletter; - uchar *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_BM: - printf("BRIGHT MICRO "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_INTEL: - printf("INTEL "); - break; - default: - printf("Unknown Vendor "); - break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf(fmt, bootletter, boottype); - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) { - printf("\n "); - } - - printf(" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -#if 0 -ulong -flash_get_size(FPWV * addr, flash_info_t * info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) - switch (addr[1]) { - - case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong) addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} -#endif /* 0 */ - -#ifdef CFG_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void -flash_sync_real_protect(flash_info_t * info) -{ - FPWV *addr = (FPWV *) (info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW) 0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *) (info->start[i]); - info->protect[i] = - (sect[2] & (FPW) (0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - break; - - case FLASH_AM640U: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int -flash_erase(flash_info_t * info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - break; - case FLASH_UNKNOWN: - default: - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - start = get_timer(0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *) (info->start[sect]); - if (intel) { - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - } else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *) (info->start[0]); - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00800080; /* erase mode */ - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - *addr = (FPW) 0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay(1000); - - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer(0)) - start > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - - flash_reset(info); /* reset to read mode */ - } - - printf(" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int -bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof (data), left -= sizeof (data) - bytes) { - - bytes = addr & (sizeof (data) - 1); - addr &= ~(sizeof (data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof (data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *) addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *) addr, data); - break; - default: - /* unknown flash type, error! */ - printf("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/** - * write_buf: - Copy memory to flash. - * - * @param info: - * @param src: source of copy transaction - * @param addr: where to copy to - * @param cnt: number of bytes to copy - * - * @return error code - */ - -int -write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* handle unaligned start bytes */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word(info, (FPWV *)wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* handle word aligned part */ - while (cnt >= 2) { - /* data = *((vushort*)src); */ - data = *((FPW *) src); - if ((rc = write_word(info, (FPWV *)wp, data)) != 0) { - return (rc); - } - src += sizeof (FPW); - wp += sizeof (FPW); - cnt -= sizeof (FPW); - } - - if (cnt == 0) - return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word(info, (FPWV *)wp, data); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_word_amd(flash_info_t * info, FPWV * dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *) (info->start[0]); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(0) - start > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00F000F0; /* reset bank */ - printf("SHA timeout\n"); - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_word_intel(flash_info_t * info, FPWV * dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - *dest = (FPW) 0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW) 0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CFG_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int -flash_real_protect(flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset(info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset(info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect(info); - break; - - case FLASH_AM640U: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/mx1fs2/intel.h b/board/mx1fs2/intel.h deleted file mode 100644 index 8db5dd4..0000000 --- a/board/mx1fs2/intel.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2002 ETC s.r.o. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the ETC s.r.o. nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Written by Marcel Telka , 2002. - * - * Documentation: - * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, - * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 - * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, - * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 - * - * This file is taken from OpenWinCE project hosted by SourceForge.net - * - */ - -#ifndef FLASH_INTEL_H -#define FLASH_INTEL_H - -#include - -/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ - -#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ - -/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ - -#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ - -/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ - -#define CFI_CHIP_INTEL_28F320J3A 0x0016 -#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" -#define CFI_CHIP_INTEL_28F640J3A 0x0017 -#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" -#define CFI_CHIP_INTEL_28F128J3A 0x0018 -#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" - -/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ - -#define CFI_CHIP_INTEL_28F640K3 0x8801 -#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" -#define CFI_CHIP_INTEL_28F128K3 0x8802 -#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" -#define CFI_CHIP_INTEL_28F256K3 0x8803 -#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" -#define CFI_CHIP_INTEL_28F640K18 0x8805 -#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" -#define CFI_CHIP_INTEL_28F128K18 0x8806 -#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" -#define CFI_CHIP_INTEL_28F256K18 0x8807 -#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" - -#endif /* FLASH_INTEL_H */ diff --git a/board/mx1fs2/lowlevel_init.S b/board/mx1fs2/lowlevel_init.S deleted file mode 100644 index 8211beb..0000000 --- a/board/mx1fs2/lowlevel_init.S +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - * 02111-1307, USA. - * - */ - -#include -#include -#include - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - -/* Change PERCLK1DIV to 14 ie 14+1 */ - ldr r0, =PCDR - ldr r1, =CFG_PCDR_VAL - str r1, [r0] - -/* set MCU PLL Control Register 0 */ - - ldr r0, =MPCTL0 - ldr r1, =CFG_MPCTL0_VAL - str r1, [r0] - -/* set MCU PLL Control Register 1 */ - - ldr r0, =MPCTL1 - ldr r1, =CFG_MPCTL1_VAL - str r1, [r0] - -/* set mpll restart bit */ - ldr r0, =CSCR - ldr r1, [r0] - orr r1,r1,#(1<<21) - str r1, [r0] - - mov r2,#0x10 -1: - mov r3,#0x2000 -2: - subs r3,r3,#1 - bne 2b - - subs r2,r2,#1 - bne 1b - -/* set System PLL Control Register 0 */ - - ldr r0, =SPCTL0 - ldr r1, =CFG_SPCTL0_VAL - str r1, [r0] - -/* set System PLL Control Register 1 */ - - ldr r0, =SPCTL1 - ldr r1, =CFG_SPCTL1_VAL - str r1, [r0] - -/* set spll restart bit */ - ldr r0, =CSCR - ldr r1, [r0] - orr r1,r1,#(1<<22) - str r1, [r0] - - mov r2,#0x10 -1: - mov r3,#0x2000 -2: - subs r3,r3,#1 - bne 2b - - subs r2,r2,#1 - bne 1b - - ldr r0, =CSCR - ldr r1, =CFG_CSCR_VAL - str r1, [r0] - - ldr r0, =GPCR - ldr r1, =CFG_GPCR_VAL - str r1, [r0] - -/* - * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon - * this..... - * - * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15 - * register 1, this stops it using the output of the PLL and thus runs at the - * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never - * use the value set in the CM_OSC registers...regardless of what you set it - * too! Thus, although i thought i was running at 140MHz, i'm actually running - * at 40!.. - * - * Slapping this into my bootloader does the trick... - * - * MRC p15,0,r0,c1,c0,0 ; read core configuration register - * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode - * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration - * register - * - */ - MRC p15,0,r0,c1,c0,0 -/* ORR r0,r0,#0xC0000000 async mode */ -/* ORR r0,r0,#0x40000000 sync mode */ - ORR r0,r0,#0xC0000000 - MCR p15,0,r0,c1,c0,0 - - ldr r0, =GIUS(0) - ldr r1, =CFG_GIUS_A_VAL - str r1, [r0] - - ldr r0, =FMCR - ldr r1, =CFG_FMCR_VAL - str r1, [r0] - - ldr r0, =CS0U - ldr r1, =CFG_CS0U_VAL - str r1, [r0] - - ldr r0, =CS0L - ldr r1, =CFG_CS0L_VAL - str r1, [r0] - - ldr r0, =CS1U - ldr r1, =CFG_CS1U_VAL - str r1, [r0] - - ldr r0, =CS1L - ldr r1, =CFG_CS1L_VAL - str r1, [r0] - - ldr r0, =CS4U - ldr r1, =CFG_CS4U_VAL - str r1, [r0] - - ldr r0, =CS4L - ldr r1, =CFG_CS4L_VAL - str r1, [r0] - - ldr r0, =CS5U - ldr r1, =CFG_CS5U_VAL - str r1, [r0] - - ldr r0, =CS5L - ldr r1, =CFG_CS5L_VAL - str r1, [r0] - -/* SDRAM Setup */ - - ldr r1,=0x00221000 /* adr of SDCTRL0 */ - ldr r0,=0x92120200 - str r0,[r1,#0] /* put in precharge command mode */ - ldr r2,=0x08200000 /* adr for precharge cmd */ - ldr r0,[r2,#0] /* precharge */ - ldr r0,=0xA2120200 - ldr r2,=0x08000000 /* start of SDRAM */ - str r0,[r1,#0] /* put in auto-refresh mode */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,=0xB2120200 - ldr r2,=0x08111800 - str r0,[r1,#0] /* setup for mode register of SDRAM */ - ldr r0,[r2,#0] /* program mode register */ - ldr r0,=0x82124267 - str r0,[r1,#0] /* back to normal operation */ - - mov pc,r10 diff --git a/board/mx1fs2/mx1fs2.c b/board/mx1fs2/mx1fs2.c deleted file mode 100644 index 9e7a06c..0000000 --- a/board/mx1fs2/mx1fs2.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include - -#include - -#define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) - -extern void imx_gpio_mode(int gpio_mode); - -static void logo_init(void) -{ - imx_gpio_mode(PD15_PF_LD0); - imx_gpio_mode(PD16_PF_LD1); - imx_gpio_mode(PD17_PF_LD2); - imx_gpio_mode(PD18_PF_LD3); - imx_gpio_mode(PD19_PF_LD4); - imx_gpio_mode(PD20_PF_LD5); - imx_gpio_mode(PD21_PF_LD6); - imx_gpio_mode(PD22_PF_LD7); - imx_gpio_mode(PD23_PF_LD8); - imx_gpio_mode(PD24_PF_LD9); - imx_gpio_mode(PD25_PF_LD10); - imx_gpio_mode(PD26_PF_LD11); - imx_gpio_mode(PD27_PF_LD12); - imx_gpio_mode(PD28_PF_LD13); - imx_gpio_mode(PD29_PF_LD14); - imx_gpio_mode(PD30_PF_LD15); - imx_gpio_mode(PD14_PF_FLM_VSYNC); - imx_gpio_mode(PD13_PF_LP_HSYNC); - imx_gpio_mode(PD6_PF_LSCLK); - imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_GPIO); - imx_gpio_mode(PD11_PF_CONTRAST); - imx_gpio_mode(PD10_PF_SPL_SPR); - - LCDC_RMCR = 0x00000000; - LCDC_PCR = PCR_COLOR | PCR_PBSIZ_8 | PCR_BPIX_16 | PCR_PCD(5); - LCDC_HCR = HCR_H_WIDTH(2); - LCDC_VCR = VCR_V_WIDTH(2); - - LCDC_PWMR = 0x00000380; /* contrast to 0x80 middle (is best !!!) */ - LCDC_SSA = 0x10040000; /* image in flash */ - - LCDC_SIZE = SIZE_XMAX(320) | SIZE_YMAX(240); /* screen size */ - - LCDC_VPW = 0x000000A0; /* Virtual Page Width Register */ - LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */ - - /* disable Cursor */ - LCDC_CPOS = 0x00000000; - - /* fixed burst length */ - LCDC_DMACR = DMACR_BURST | DMACR_HM(8) | DMACR_TM(2); - - /* enable LCD */ - DR(3) |= 0x00001000; - LCDC_RMCR = RMCR_LCDC_EN; - -} - -int -board_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_arch_number = MACH_TYPE_MX1FS2; - gd->bd->bi_boot_params = 0x08000100; -serial_init(); - logo_init(); - return 0; -} - -int -dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - -#if ( CONFIG_NR_DRAM_BANKS > 0 ) - gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1; - gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE; -#endif - return 0; -} - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - */ - -void -show_boot_progress(int status) -{ - /* We use this as a hook to disable serial ports just before booting - * This way we suppress the "uncompressing linux..." message - */ -#ifdef CONFIG_SILENT_CONSOLE - if( status == 8) { - if( getenv("silent") != NULL ) { - *(volatile unsigned long *)0x206080 &= ~1; - *(volatile unsigned long *)0x207080 &= ~1; - } - } -#endif - return; -} diff --git a/board/mx1fs2/u-boot.lds b/board/mx1fs2/u-boot.lds deleted file mode 100644 index 1d1669c..0000000 --- a/board/mx1fs2/u-boot.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/nc650/Makefile b/board/nc650/Makefile deleted file mode 100644 index a4dd85f..0000000 --- a/board/nc650/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/nc650/config.mk b/board/nc650/config.mk deleted file mode 100644 index fa8ba31..0000000 --- a/board/nc650/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# NC650 board -# - -TEXT_BASE = 0x40700000 diff --git a/board/nc650/flash.c b/board/nc650/flash.c deleted file mode 100644 index ce2f83b..0000000 --- a/board/nc650/flash.c +++ /dev/null @@ -1,542 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#undef DEBUG - -#include -#include - -#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ -#define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH8 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#elif FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#else /* FLASH_PORT_WIDTH8 */ -#define FLASH_PORT_WIDTH uchar -#define FLASH_PORT_WIDTHV vu_char -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPWV * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; -#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ - int scy, trlx, flash_or_timing, clk_diff; - - DECLARE_GLOBAL_DATA_PTR; - - scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; - if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { - trlx = OR_TRLX; - scy *= 2; - } else - trlx = 0; - - /* We assume that each 10MHz of bus clock require 1-clk SCY - * adjustment. - */ - clk_diff = (gd->bus_clk / 1000000) - 50; - - /* We need proper rounding here. This is what the "+5" and "-5" - * are here for. - */ - if (clk_diff >= 0) - scy += (clk_diff + 5) / 10; - else - scy += (clk_diff - 5) / 10; - - /* For bus frequencies above 50MHz, we want to use relaxed - * timing (OR_TRLX). - */ - if (gd->bus_clk >= 50000000) - trlx = OR_TRLX; - else - trlx = 0; - - if (trlx) - scy /= 2; - - if (scy > 0xf) - scy = 0xf; - if (scy < 1) - scy = 1; - - flash_or_timing = (scy << 4) | trlx | - (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); -#endif - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Remap FLASH according to real size */ -#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); -#else - memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK); -#endif - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPWV * addr, flash_info_t * info) -{ - FPW value; - - addr[0] = (FPW) 0x00900090; - - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - -#ifdef FLASH_PORT_WIDTH8 - value = addr[2]; /* device ID */ -#else - value = addr[1]; /* device ID */ -#endif - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { - case (FPW) INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - - int i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#elif defined(FLASH_PORT_WIDTH32) - wp = (addr & ~3); - port_width = 4; -#else - wp = addr; - port_width = 1; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c deleted file mode 100644 index fe96b93..0000000 --- a/board/nc650/nc650.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * Memory Controller Using - * - * CS0 - Flash memory (0x40000000) - * CS3 - SDRAM (0x00000000} - */ - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -const uint sdram_table[] = { - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* MRS initialization (offset 5) */ - - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ -}; - -const uint nand_flash_table[] = { - /* single read. (offset 0 in upm RAM) */ - 0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04, - 0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05, - - /* burst read. (offset 8 in upm RAM) */ - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - - /* single write. (offset 18 in upm RAM) */ - 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04, - 0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05, - - /* burst write. (offset 20 in upm RAM) */ - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - - /* refresh. (offset 30 in upm RAM) */ - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - - /* exception. (offset 3c in upm RAM) */ - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05 -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: NC650\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size_b0 = 0; - unsigned long reg; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 1 to the SDRAM bank at - * preliminary address - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80006105; /* SDRAM bank 0 */ - udelay (200); - memctl->memc_mcr = 0x80006230; /* SDRAM bank 0 - execute twice */ - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - if (size8 < size9) { - size_b0 = size9; - } else { - size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); - } - - /* - * Adjust refresh rate depending on SDRAM type, both banks. - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - - memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - - /* Configure UPMB for NAND flash access */ - upmconfig (UPMB, (uint *) nand_flash_table, - sizeof (nand_flash_table) / sizeof (uint)); - - memctl->memc_mbmr = CFG_MBMR_NAND; - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -void nand_init(void) -{ - extern unsigned long nand_probe(unsigned long physadr); - - unsigned long totlen = nand_probe(CFG_NAND_BASE); - - printf ("%4lu MB\n", totlen >> 20); -} -#endif diff --git a/board/nc650/u-boot.lds b/board/nc650/u-boot.lds deleted file mode 100644 index ca44918..0000000 --- a/board/nc650/u-boot.lds +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/nc650/u-boot.lds.debug b/board/nc650/u-boot.lds.debug deleted file mode 100644 index 2228a20..0000000 --- a/board/nc650/u-boot.lds.debug +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/netphone/Makefile b/board/netphone/Makefile deleted file mode 100644 index b3c1797..0000000 --- a/board/netphone/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o phone_console.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/netphone/config.mk b/board/netphone/config.mk deleted file mode 100644 index 8497ebc..0000000 --- a/board/netphone/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# netVia Boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/netphone/flash.c b/board/netphone/flash.c deleted file mode 100644 index 0c81140..0000000 --- a/board/netphone/flash.c +++ /dev/null @@ -1,529 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_byte(flash_info_t * info, ulong dest, uchar data); -static void flash_get_offsets(ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; -#if CONFIG_NETPHONE_VERSION == 2 - unsigned long size1; -#endif - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); - -#ifdef CFG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - -#if CONFIG_NETPHONE_VERSION == 2 - size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]); - if (size1 > 0) { - if (flash_info[1].flash_id == FLASH_UNKNOWN) - printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20); - - /* Remap FLASH according to real size */ - memctl->memc_or4 = CFG_OR_TIMING_FLASH | (-size1 & 0xFFFF8000); - memctl->memc_br4 = (CFG_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size1 = flash_get_size((vu_long *) CFG_FLASH_BASE4, &flash_info[1]); - - flash_get_offsets(CFG_FLASH_BASE4, &flash_info[1]); - - size += size1; - } else - memctl->memc_br4 &= ~BR_V; -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_MX: - printf("MXIC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - short i; - uchar mid; - uchar pid; - vu_char *caddr = (vu_char *) addr; - ulong base = (ulong) addr; - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - mid = caddr[0]; - switch (mid) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (MX_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_MX; - break; - case (STM_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - pid = caddr[1]; /* device ID */ - switch (pid) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - - case (STM_ID_M29W040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf(" "); - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *) info->start[0]; - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0xF0; - - udelay(20000); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *) (info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_char *) (info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_char *) info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte(flash_info_t * info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c deleted file mode 100644 index dd03e4b..0000000 --- a/board/netphone/netphone.c +++ /dev/null @@ -1,722 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#include -#include -#include -#include - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include -#endif - -int fec8xx_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define GPL0_AAAA 0x00000000 -#define GPL0_AAA0 0x00200000 -#define GPL0_AAA1 0x00300000 -#define GPL0_000A 0x00800000 -#define GPL0_0000 0x00A00000 -#define GPL0_0001 0x00B00000 -#define GPL0_111A 0x00C00000 -#define GPL0_1110 0x00E00000 -#define GPL0_1111 0x00F00000 - -#define GPL1_0000 0x00000000 -#define GPL1_0001 0x00040000 -#define GPL1_1110 0x00080000 -#define GPL1_1111 0x000C0000 - -#define GPL2_0000 0x00000000 -#define GPL2_0001 0x00010000 -#define GPL2_1110 0x00020000 -#define GPL2_1111 0x00030000 - -#define GPL3_0000 0x00000000 -#define GPL3_0001 0x00004000 -#define GPL3_1110 0x00008000 -#define GPL3_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -#define A10_AAAA GPL0_AAAA -#define A10_AAA0 GPL0_AAA0 -#define A10_AAA1 GPL0_AAA1 -#define A10_000A GPL0_000A -#define A10_0000 GPL0_0000 -#define A10_0001 GPL0_0001 -#define A10_111A GPL0_111A -#define A10_1110 GPL0_1110 -#define A10_1111 GPL0_1111 - -#define RAS_0000 GPL1_0000 -#define RAS_0001 GPL1_0001 -#define RAS_1110 GPL1_1110 -#define RAS_1111 GPL1_1111 - -#define CAS_0000 GPL2_0000 -#define CAS_0001 GPL2_0001 -#define CAS_1110 GPL2_1110 -#define CAS_1111 GPL2_1111 - -#define WE_0000 GPL3_0000 -#define WE_0001 GPL3_0001 -#define WE_1110 GPL3_1110 -#define WE_1111 GPL3_1111 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -#if CONFIG_NETPHONE_VERSION == 2 -static const uint nandcs_table[0x40] = { - /* RSS */ - CS_1000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1110 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111, - CS_0000 | GPL4_0001 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ - - /* RBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_1000 | GPL4_1111 | GPL5_1110 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0001 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, - - /* WBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 , - CS_0001 | LAST, -}; -#endif - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 8 */ -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -long int initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - - memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - { - u32 d1, d2; - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - - if (size == 0) { - printf("SIZE is zero: LOOP on 0\n"); - for (;;) { - *(volatile u32 *)0 = 0; - (void)*(volatile u32 *)0; - } - } - - return size; -} - -/* ------------------------------------------------------------------------- */ - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - udelay(10000); - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); - if (v == 0xFFFF) - continue; - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); - udelay(10000); - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, - PHY_BMCR_RESET | PHY_BMCR_AUTON); - udelay(10000); - } -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK 0 -#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15)) -#define PA_SP_MASK 0 -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK _B(28) -#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_MASK (_BR(22, 25)) -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_DIRVAL 0 - -#if CONFIG_NETPHONE_VERSION == 1 -#define PC_GP_INMASK _BW(12) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15)) -#elif CONFIG_NETPHONE_VERSION == 2 -#define PC_GP_INMASK (_BW(13) | _BW(15)) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12)) -#endif -#define PC_SP_MASK 0 -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL (_BW(10) | _BW(11)) -#define PC_SP_DIRVAL 0 - -#if CONFIG_NETPHONE_VERSION == 1 -#define PE_GP_INMASK _B(31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28)) -#elif CONFIG_NETPHONE_VERSION == 2 -#define PE_GP_INMASK _BR(28, 31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27)) -#endif -#define PE_SP_MASK 0 -#define PE_ODR_VAL 0 -#define PE_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* NAND chip select */ -#if CONFIG_NETPHONE_VERSION == 1 - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); -#elif CONFIG_NETPHONE_VERSION == 2 - upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA); - memctl->memc_mamr = 0; /* all clear */ -#endif - - /* DSP chip select */ - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); - memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); - -#if CONFIG_NETPHONE_VERSION == 1 - memctl->memc_br4 &= ~BR_V; -#endif - memctl->memc_br5 &= ~BR_V; - memctl->memc_br6 &= ~BR_V; - memctl->memc_br7 &= ~BR_V; - - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - cpm->cp_pedat = PE_GP_OUTVAL; - cpm->cp_peodr = PE_ODR_VAL; - cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; - cpm->cp_pepar = PE_SP_MASK; - - return 0; -} - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - -#include - -extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - unsigned long totlen; - - totlen = nand_probe(CFG_NAND_BASE); - printf ("%4lu MB\n", totlen >> 20); -} -#endif - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif - -#ifdef CONFIG_SHOW_ACTIVITY - -static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */ - -/* called from timer interrupt every 1/CFG_HZ sec */ -void board_show_activity(ulong timestamp) -{ - if (left_to_poll > -PHONE_CONSOLE_POLL_HZ) - --left_to_poll; -} - -extern void phone_console_do_poll(void); - -static void do_poll(void) -{ - unsigned int base; - - while (left_to_poll <= 0) { - phone_console_do_poll(); - base = left_to_poll + PHONE_CONSOLE_POLL_HZ; - do { - left_to_poll = base; - } while (base != left_to_poll); - } -} - -/* called when looping */ -void show_activity(int arg) -{ - do_poll(); -} - -#endif - -#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - /* printf("overwrite_console called\n"); */ - return 0; -} -#endif - -extern int drv_phone_init(void); -extern int drv_phone_use_me(void); -extern int drv_phone_is_idle(void); - -int misc_init_r(void) -{ - return drv_phone_init(); -} - -int last_stage_init(void) -{ - int i; - -#if CONFIG_NETPHONE_VERSION == 2 - /* assert peripheral reset */ - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); - for (i = 0; i < 10; i++) - udelay(1000); - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |= _BW(12); -#endif - reset_phys(); - - /* check in order to enable the local console */ - left_to_poll = PHONE_CONSOLE_POLL_HZ; - i = CFG_HZ * 2; - while (i > 0) { - - if (tstc()) { - getc(); - break; - } - - do_poll(); - - if (drv_phone_use_me()) { - status_led_set(0, STATUS_LED_ON); - while (!drv_phone_is_idle()) { - do_poll(); - udelay(1000000 / CFG_HZ); - } - - console_assign(stdin, "phone"); - console_assign(stdout, "phone"); - console_assign(stderr, "phone"); - setenv("bootdelay", "-1"); - break; - } - - udelay(1000000 / CFG_HZ); - i--; - left_to_poll--; - } - left_to_poll = PHONE_CONSOLE_POLL_HZ; - - return 0; -} diff --git a/board/netphone/phone_console.c b/board/netphone/phone_console.c deleted file mode 100644 index 408ada0..0000000 --- a/board/netphone/phone_console.c +++ /dev/null @@ -1,1144 +0,0 @@ -/* - * (C) Copyright 2004 Intracom S.A. - * Pantelis Antoniou - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * phone_console.c - * - * A phone based console - * - * Virtual display of 80x24 characters. - * The actual display is much smaller and panned to show the virtual one. - * Input is made by a numeric keypad utilizing the input method of - * mobile phones. Sorry no T9 lexicons... - * - */ - -#include - -#include -#include -#include - -#include - -/*************************************************************************************************/ - -#define ROWS 24 -#define COLS 80 - -#define REFRESH_HZ (CFG_HZ/50) /* refresh every 20ms */ -#define BLINK_HZ (CFG_HZ/2) /* cursor blink every 500ms */ - -/*************************************************************************************************/ - -#define DISPLAY_BACKLIT_PORT ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat -#define DISPLAY_BACKLIT_MASK 0x0010 - -/*************************************************************************************************/ - -#define KP_STABLE_HZ (CFG_HZ/100) /* stable for 10ms */ -#define KP_REPEAT_DELAY_HZ (CFG_HZ/4) /* delay before repeat 250ms */ -#define KP_REPEAT_HZ (CFG_HZ/20) /* repeat every 50ms */ -#define KP_FORCE_DELAY_HZ (CFG_HZ/2) /* key was force pressed */ -#define KP_IDLE_DELAY_HZ (CFG_HZ/2) /* key was released and idle */ - -#if CONFIG_NETPHONE_VERSION == 1 -#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) -#define KP_SPI_RXD_MASK 0x0008 - -#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) -#define KP_SPI_TXD_MASK 0x0004 - -#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) -#define KP_SPI_CLK_MASK 0x0001 -#elif CONFIG_NETPHONE_VERSION == 2 -#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define KP_SPI_RXD_MASK 0x00000008 - -#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define KP_SPI_TXD_MASK 0x00000004 - -#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define KP_SPI_CLK_MASK 0x00000002 -#endif - -#define KP_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) -#define KP_CS_MASK 0x00000010 - -#define KP_SPI_RXD() (KP_SPI_RXD_PORT & KP_SPI_RXD_MASK) - -#define KP_SPI_TXD(x) \ - do { \ - if (x) \ - KP_SPI_TXD_PORT |= KP_SPI_TXD_MASK; \ - else \ - KP_SPI_TXD_PORT &= ~KP_SPI_TXD_MASK; \ - } while(0) - -#define KP_SPI_CLK(x) \ - do { \ - if (x) \ - KP_SPI_CLK_PORT |= KP_SPI_CLK_MASK; \ - else \ - KP_SPI_CLK_PORT &= ~KP_SPI_CLK_MASK; \ - } while(0) - -#define KP_SPI_CLK_TOGGLE() (KP_SPI_CLK_PORT ^= KP_SPI_CLK_MASK) - -#define KP_SPI_BIT_DELAY() /* no delay */ - -#define KP_CS(x) \ - do { \ - if (x) \ - KP_CS_PORT |= KP_CS_MASK; \ - else \ - KP_CS_PORT &= ~KP_CS_MASK; \ - } while(0) - -#define KP_ROWS 7 -#define KP_COLS 4 - -#define KP_ROWS_MASK ((1 << KP_ROWS) - 1) -#define KP_COLS_MASK ((1 << KP_COLS) - 1) - -#define SCAN 0 -#define SCAN_FILTER 1 -#define SCAN_COL 2 -#define SCAN_COL_FILTER 3 -#define PRESSED 4 - -#define KP_F1 0 /* leftmost dot (tab) */ -#define KP_F2 1 /* middle left dot */ -#define KP_F3 2 /* up */ -#define KP_F4 3 /* middle right dot */ -#define KP_F5 4 /* rightmost dot */ -#define KP_F6 5 /* C */ -#define KP_F7 6 /* left */ -#define KP_F8 7 /* down */ -#define KP_F9 8 /* right */ -#define KP_F10 9 /* enter */ -#define KP_F11 10 /* R */ -#define KP_F12 11 /* save */ -#define KP_F13 12 /* redial */ -#define KP_F14 13 /* speaker */ -#define KP_F15 14 /* unused */ -#define KP_F16 15 /* unused */ - -#define KP_RELEASE -1 /* key depressed */ -#define KP_FORCE -2 /* key was pressed for more than force hz */ -#define KP_IDLE -3 /* key was released and idle */ - -#define KP_1 '1' -#define KP_2 '2' -#define KP_3 '3' -#define KP_4 '4' -#define KP_5 '5' -#define KP_6 '6' -#define KP_7 '7' -#define KP_8 '8' -#define KP_9 '9' -#define KP_0 '0' -#define KP_STAR '*' -#define KP_HASH '#' - -/*************************************************************************************************/ - -static int curs_disabled; -static int curs_col, curs_row; -static int disp_col, disp_row; - -static int width, height; - -/* the simulated vty buffer */ -static char vty_buf[ROWS * COLS]; -static char last_visible_buf[ROWS * COLS]; /* worst case */ -static char *last_visible_curs_ptr; -static int last_visible_curs_rev; -static int blinked_state; -static int last_input_mode; -static int refresh_time; -static int blink_time; -static char last_fast_punct; - -/*************************************************************************************************/ - -#define IM_SMALL 0 -#define IM_CAPITAL 1 -#define IM_NUMBER 2 - -static int input_mode; -static char fast_punct; -static int tab_indicator; -static const char *fast_punct_list = ",.:;*"; - -static const char *input_mode_txt[] = { "abc", "ABC", "123" }; - -static const char *punct = ".,!;?'\"-()@/:_+&%*=<>$[]{}\\~^#|"; -static const char *whspace = " 0\n"; -/* per mode character select (for 2-9) */ -static const char *digits_sel[2][8] = { - { /* small */ - "abc2", /* 2 */ - "def3", /* 3 */ - "ghi4", /* 4 */ - "jkl5", /* 5 */ - "mno6", /* 6 */ - "pqrs7", /* 7 */ - "tuv8", /* 8 */ - "wxyz9", /* 9 */ - }, { /* capital */ - "ABC2", /* 2 */ - "DEF3", /* 3 */ - "GHI4", /* 4 */ - "JKL5", /* 5 */ - "MNO6", /* 6 */ - "PQRS7", /* 7 */ - "TUV8", /* 8 */ - "WXYZ9", /* 9 */ - } -}; - -/*****************************************************************************/ - -static void update(void); -static void ensure_visible(int col, int row, int dx, int dy); - -static void console_init(void) -{ - curs_disabled = 0; - curs_col = 0; - curs_row = 0; - - disp_col = 0; - disp_row = 0; - - input_mode = IM_SMALL; - fast_punct = ','; - last_fast_punct = '\0'; - refresh_time = REFRESH_HZ; - blink_time = BLINK_HZ; - - memset(vty_buf, ' ', sizeof(vty_buf)); - - memset(last_visible_buf, ' ', sizeof(last_visible_buf)); - last_visible_curs_ptr = NULL; - last_input_mode = -1; - last_visible_curs_rev = 0; - - blinked_state = 0; - - sed156x_init(); - width = sed156x_text_width; - height = sed156x_text_height - 1; - - tab_indicator = 0; -} - -/*****************************************************************************/ - -void phone_putc(const char c); - -/*****************************************************************************/ - -static int queued_char = -1; -static int enabled = 0; - -/*****************************************************************************/ - -/* flush buffers */ -int phone_start(void) -{ - console_init(); - - update(); - sed156x_sync(); - - enabled = 1; - queued_char = 'U' - '@'; - - /* backlit on */ - DISPLAY_BACKLIT_PORT &= ~DISPLAY_BACKLIT_MASK; - - return 0; -} - -int phone_stop(void) -{ - enabled = 0; - - sed156x_clear(); - sed156x_sync(); - - /* backlit off */ - DISPLAY_BACKLIT_PORT |= DISPLAY_BACKLIT_MASK; - - return 0; -} - -void phone_puts(const char *s) -{ - int count = strlen(s); - - while (count--) - phone_putc(*s++); -} - -int phone_tstc(void) -{ - return queued_char >= 0 ? 1 : 0; -} - -int phone_getc(void) -{ - int r; - - if (queued_char < 0) - return -1; - - r = queued_char; - queued_char = -1; - - return r; -} - -/*****************************************************************************/ - -int drv_phone_init(void) -{ - device_t console_dev; - - console_init(); - - memset(&console_dev, 0, sizeof(console_dev)); - strcpy(console_dev.name, "phone"); - console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ - console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - console_dev.start = phone_start; - console_dev.stop = phone_stop; - console_dev.putc = phone_putc; /* 'putc' function */ - console_dev.puts = phone_puts; /* 'puts' function */ - console_dev.tstc = phone_tstc; /* 'tstc' function */ - console_dev.getc = phone_getc; /* 'getc' function */ - - if (device_register(&console_dev) == 0) - return 1; - - return 0; -} - -static int use_me; - -int drv_phone_use_me(void) -{ - return use_me; -} - -static void kp_do_poll(void); - -void phone_console_do_poll(void) -{ - int i, x, y; - - kp_do_poll(); - - if (enabled) { - /* do the blink */ - blink_time -= PHONE_CONSOLE_POLL_HZ; - if (blink_time <= 0) { - blink_time += BLINK_HZ; - if (last_visible_curs_ptr) { - i = last_visible_curs_ptr - last_visible_buf; - x = i % width; y = i / width; - sed156x_reverse_at(x, y, 1); - last_visible_curs_rev ^= 1; - } - } - - /* do the refresh */ - refresh_time -= PHONE_CONSOLE_POLL_HZ; - if (refresh_time <= 0) { - refresh_time += REFRESH_HZ; - sed156x_sync(); - } - } - -} - -static int last_scancode = -1; -static int forced_scancode = 0; -static int input_state = -1; -static int input_scancode = -1; -static int input_selected_char = -1; -static char input_covered_char; - -static void putchar_at_cursor(char c) -{ - vty_buf[curs_row * COLS + curs_col] = c; - ensure_visible(curs_col, curs_row, 1, 1); -} - -static char getchar_at_cursor(void) -{ - return vty_buf[curs_row * COLS + curs_col]; -} - -static void queue_input_char(char c) -{ - if (c <= 0) - return; - - queued_char = c; -} - -static void terminate_input(void) -{ - if (input_state < 0) - return; - - if (input_selected_char >= 0) - queue_input_char(input_selected_char); - - input_state = -1; - input_selected_char = -1; - putchar_at_cursor(input_covered_char); - - curs_disabled = 0; - blink_time = BLINK_HZ; - update(); -} - -static void handle_enabled_scancode(int scancode) -{ - char c; - int new_disp_col, new_disp_row; - const char *sel; - - - switch (scancode) { - - /* key was released */ - case KP_RELEASE: - forced_scancode = 0; - break; - - /* key was forced */ - case KP_FORCE: - - switch (last_scancode) { - case '#': - if (input_mode == IM_NUMBER) { - input_mode = IM_CAPITAL; - /* queue backspace to erase # */ - queue_input_char('\b'); - } else { - input_mode = IM_NUMBER; - fast_punct = '*'; - } - update(); - break; - - case '0': case '1': - case '2': case '3': case '4': case '5': - case '6': case '7': case '8': case '9': - - if (input_state < 0) - break; - - input_selected_char = last_scancode; - putchar_at_cursor((char)input_selected_char); - terminate_input(); - - break; - - default: - break; - } - - break; - - /* release and idle */ - case KP_IDLE: - input_scancode = -1; - if (input_state < 0) - break; - terminate_input(); - break; - - /* change input mode */ - case '#': - if (last_scancode == '#') /* no repeat */ - break; - - if (input_mode == IM_NUMBER) { - input_scancode = scancode; - input_state = 0; - input_selected_char = scancode; - input_covered_char = getchar_at_cursor(); - putchar_at_cursor((char)input_selected_char); - terminate_input(); - break; - } - - if (input_mode == IM_SMALL) - input_mode = IM_CAPITAL; - else - input_mode = IM_SMALL; - - update(); - break; - - case '*': - /* no repeat */ - if (last_scancode == scancode) - break; - - if (input_state >= 0) - terminate_input(); - - input_scancode = fast_punct; - input_state = 0; - input_selected_char = input_scancode; - input_covered_char = getchar_at_cursor(); - putchar_at_cursor((char)input_selected_char); - terminate_input(); - - break; - - case '0': case '1': - case '2': case '3': case '4': case '5': - case '6': case '7': case '8': case '9': - - /* no repeat */ - if (last_scancode == scancode) - break; - - if (input_mode == IM_NUMBER) { - input_scancode = scancode; - input_state = 0; - input_selected_char = scancode; - input_covered_char = getchar_at_cursor(); - putchar_at_cursor((char)input_selected_char); - terminate_input(); - break; - } - - if (input_state >= 0 && input_scancode != scancode) - terminate_input(); - - if (input_state < 0) { - curs_disabled = 1; - input_scancode = scancode; - input_state = 0; - input_covered_char = getchar_at_cursor(); - } else - input_state++; - - if (scancode == '0') - sel = whspace; - else if (scancode == '1') - sel = punct; - else - sel = digits_sel[input_mode][scancode - '2']; - c = *(sel + input_state); - if (c == '\0') { - input_state = 0; - c = *sel; - } - - input_selected_char = (int)c; - putchar_at_cursor((char)input_selected_char); - update(); - - break; - - /* move visible display */ - case KP_F3: case KP_F8: case KP_F7: case KP_F9: - - new_disp_col = disp_col; - new_disp_row = disp_row; - - switch (scancode) { - /* up */ - case KP_F3: - if (new_disp_row <= 0) - break; - new_disp_row--; - break; - - /* down */ - case KP_F8: - if (new_disp_row >= ROWS - height) - break; - new_disp_row++; - break; - - /* left */ - case KP_F7: - if (new_disp_col <= 0) - break; - new_disp_col--; - break; - - /* right */ - case KP_F9: - if (new_disp_col >= COLS - width) - break; - new_disp_col++; - break; - } - - /* no change? */ - if (disp_col == new_disp_col && disp_row == new_disp_row) - break; - - disp_col = new_disp_col; - disp_row = new_disp_row; - update(); - - break; - - case KP_F6: /* backspace */ - /* inputing something; no backspace sent, just cancel input */ - if (input_state >= 0) { - input_selected_char = -1; /* cancel */ - terminate_input(); - break; - } - queue_input_char('\b'); - break; - - case KP_F10: /* enter */ - /* inputing something; first cancel input */ - if (input_state >= 0) - terminate_input(); - queue_input_char('\r'); - break; - - case KP_F11: /* R -> Ctrl-C (abort) */ - if (input_state >= 0) - terminate_input(); - queue_input_char('C' - 'Q'); /* ctrl-c */ - break; - - case KP_F5: /* F% -> Ctrl-U (clear line) */ - if (input_state >= 0) - terminate_input(); - queue_input_char('U' - 'Q'); /* ctrl-c */ - break; - - - case KP_F1: /* tab */ - /* inputing something; first cancel input */ - if (input_state >= 0) - terminate_input(); - queue_input_char('\t'); - break; - - case KP_F2: /* change fast punct */ - sel = strchr(fast_punct_list, fast_punct); - if (sel == NULL) - sel = &fast_punct_list[0]; - sel++; - if (*sel == '\0') - sel = &fast_punct_list[0]; - fast_punct = *sel; - update(); - break; - - - } - - if (scancode != KP_FORCE && scancode != KP_IDLE) /* don't record forced or idle scancode */ - last_scancode = scancode; -} - -static void scancode_action(int scancode) -{ -#if 0 - if (scancode == KP_RELEASE) - printf(" RELEASE\n"); - else if (scancode == KP_FORCE) - printf(" FORCE\n"); - else if (scancode == KP_IDLE) - printf(" IDLE\n"); - else if (scancode < 32) - printf(" F%d", scancode + 1); - else - printf(" %c", (char)scancode); - printf("\n"); -#endif - - if (enabled) { - handle_enabled_scancode(scancode); - return; - } - - if (scancode == KP_FORCE && last_scancode == '*') - use_me = 1; - - last_scancode = scancode; -} - -/**************************************************************************************/ - -/* update the display; make sure to update only the differences */ -static void update(void) -{ - int i; - char *s, *e, *t, *r, *b, *cp; - - if (input_mode != last_input_mode) - sed156x_output_at(sed156x_text_width - 3, sed156x_text_height - 1, input_mode_txt[input_mode], 3); - - if (tab_indicator == 0) { - sed156x_output_at(0, sed156x_text_height - 1, "\\t", 2); - tab_indicator = 1; - } - - if (fast_punct != last_fast_punct) - sed156x_output_at(4, sed156x_text_height - 1, &fast_punct, 1); - - if (curs_disabled || - curs_col < disp_col || curs_col >= (disp_col + width) || - curs_row < disp_row || curs_row >= (disp_row + height)) { - cp = NULL; - } else - cp = last_visible_buf + (curs_row - disp_row) * width + (curs_col - disp_col); - - - /* printf("(%d,%d) (%d,%d) %s\n", curs_col, curs_row, disp_col, disp_row, cp ? "YES" : "no"); */ - - /* clear previous cursor */ - if (last_visible_curs_ptr && last_visible_curs_rev == 0) { - i = last_visible_curs_ptr - last_visible_buf; - sed156x_reverse_at(i % width, i / width, 1); - } - - b = vty_buf + disp_row * COLS + disp_col; - t = last_visible_buf; - for (i = 0; i < height; i++) { - s = b; - e = b + width; - /* update only the differences */ - do { - while (s < e && *s == *t) { - s++; - t++; - } - if (s == e) /* no more */ - break; - - /* find run */ - r = s; - while (s < e && *s != *t) - *t++ = *s++; - - /* and update */ - sed156x_output_at(r - b, i, r, s - r); - - } while (s < e); - - b += COLS; - } - - /* set cursor */ - if (cp) { - last_visible_curs_ptr = cp; - i = last_visible_curs_ptr - last_visible_buf; - sed156x_reverse_at(i % width, i / width, 1); - last_visible_curs_rev = 0; - } else { - last_visible_curs_ptr = NULL; - } - - last_input_mode = input_mode; - last_fast_punct = fast_punct; -} - -/* ensure visibility; the trick is to minimize the screen movement */ -static void ensure_visible(int col, int row, int dx, int dy) -{ - int x1, y1, x2, y2, a1, b1, a2, b2; - - /* clamp visible region */ - if (col < 0) { - dx -= col; - col = 0; - if (dx <= 0) - dx = 1; - } - - if (row < 0) { - dy -= row; - row = 0; - if (dy <= 0) - dy = 1; - } - - if (col + dx > COLS) - dx = COLS - col; - - if (row + dy > ROWS) - dy = ROWS - row; - - - /* move to easier to use vars */ - x1 = disp_col; y1 = disp_row; - x2 = x1 + width; y2 = y1 + height; - a1 = col; b1 = row; - a2 = a1 + dx; b2 = b1 + dy; - - /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */ - - if (a2 > x2) { - /* move to the right */ - x2 = a2; - x1 = x2 - width; - if (x1 < 0) { - x1 = 0; - x2 = width; - } - } else if (a1 < x1) { - /* move to the left */ - x1 = a1; - x2 = x1 + width; - if (x2 > COLS) { - x2 = COLS; - x1 = x2 - width; - } - } - - if (b2 > y2) { - /* move down */ - y2 = b2; - y1 = y2 - height; - if (y1 < 0) { - y1 = 0; - y2 = height; - } - } else if (b1 < y1) { - /* move up */ - y1 = b1; - y2 = y1 + width; - if (y2 > ROWS) { - y2 = ROWS; - y1 = y2 - height; - } - } - - /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */ - - /* no movement? */ - if (disp_col == x1 && disp_row == y1) - return; - - disp_col = x1; - disp_row = y1; -} - -/**************************************************************************************/ - -static void newline(void) -{ - curs_col = 0; - if (curs_row + 1 < ROWS) - curs_row++; - else { - memmove(vty_buf, vty_buf + COLS, COLS * (ROWS - 1)); - memset(vty_buf + (ROWS - 1) * COLS, ' ', COLS); - } -} - -void phone_putc(const char c) -{ - int i; - - if (input_mode != -1) { - input_selected_char = -1; - terminate_input(); - } - - curs_disabled = 1; - update(); - - blink_time = BLINK_HZ; - - switch (c) { - case '\a': /* ignore bell */ - case '\r': /* ignore carriage return */ - break; - - case '\n': /* next line */ - newline(); - ensure_visible(curs_col, curs_row, 1, 1); - break; - - case 9: /* tab 8 */ - /* move to tab */ - i = curs_col; - i |= 0x0008; - i &= ~0x0007; - - if (i < COLS) - curs_col = i; - else - newline(); - - ensure_visible(curs_col, curs_row, 1, 1); - break; - - case 8: /* backspace */ - if (curs_col <= 0) - break; - curs_col--; - - /* make sure that we see a couple of characters before */ - if (curs_col > 4) - ensure_visible(curs_col - 4, curs_row, 4, 1); - else - ensure_visible(curs_col, curs_row, 1, 1); - - break; - - default: /* draw the char */ - putchar_at_cursor(c); - - /* - * check for newline - */ - if (curs_col + 1 < COLS) - curs_col++; - else - newline(); - - ensure_visible(curs_col, curs_row, 1, 1); - - break; - } - - curs_disabled = 0; - blink_time = BLINK_HZ; - update(); -} - -/**************************************************************************************/ - -static inline unsigned int kp_transfer(unsigned int val) -{ - unsigned int rx; - int b; - - rx = 0; b = 8; - while (--b >= 0) { - KP_SPI_TXD(val & 0x80); - val <<= 1; - KP_SPI_CLK_TOGGLE(); - KP_SPI_BIT_DELAY(); - rx <<= 1; - if (KP_SPI_RXD()) - rx |= 1; - KP_SPI_CLK_TOGGLE(); - KP_SPI_BIT_DELAY(); - } - - return rx; -} - -unsigned int kp_data_transfer(unsigned int val) -{ - KP_SPI_CLK(1); - KP_CS(0); - val = kp_transfer(val); - KP_CS(1); - - return val; -} - -unsigned int kp_get_col_mask(unsigned int row_mask) -{ - unsigned int val, col_mask; - - val = 0x80 | (row_mask & 0x7F); - (void)kp_data_transfer(val); -#if CONFIG_NETPHONE_VERSION == 1 - col_mask = kp_data_transfer(val) & 0x0F; -#elif CONFIG_NETPHONE_VERSION == 2 - col_mask = ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & 0x0f; - /* XXX FUCK FUCK FUCK FUCK FUCK!!!! */ - col_mask = ((col_mask & 0x08) >> 3) | /* BKBR1 */ - ((col_mask & 0x04) << 1) | /* BKBR2 */ - (col_mask & 0x02) | /* BKBR3 */ - ((col_mask & 0x01) << 2); /* BKBR4 */ - -#endif - /* printf("col_mask(row_mask = 0x%x) -> col_mask = 0x%x\n", row_mask, col_mask); */ - - return col_mask; -} - -/**************************************************************************************/ - -static const int kp_scancodes[KP_ROWS * KP_COLS] = { - KP_F1, KP_F3, KP_F4, KP_F2, - KP_F6, KP_F8, KP_F9, KP_F7, - KP_1, KP_3, KP_F11, KP_2, - KP_4, KP_6, KP_F12, KP_5, - KP_7, KP_9, KP_F13, KP_8, - KP_STAR, KP_HASH, KP_F14, KP_0, - KP_F5, KP_F15, KP_F16, KP_F10, -}; - -static const int kp_repeats[KP_ROWS * KP_COLS] = { - 0, 1, 0, 0, - 0, 1, 1, 1, - 1, 1, 0, 1, - 1, 1, 0, 1, - 1, 1, 0, 1, - 1, 1, 0, 1, - 0, 0, 0, 1, -}; - -static int kp_state = SCAN; -static int kp_last_col_mask; -static int kp_cur_row, kp_cur_col; -static int kp_scancode; -static int kp_stable; -static int kp_repeat; -static int kp_repeat_time; -static int kp_force_time; -static int kp_idle_time; - -static void kp_do_poll(void) -{ - unsigned int col_mask; - int col; - - switch (kp_state) { - case SCAN: - if (kp_idle_time > 0) { - kp_idle_time -= PHONE_CONSOLE_POLL_HZ; - if (kp_idle_time <= 0) - scancode_action(KP_IDLE); - } - - col_mask = kp_get_col_mask(KP_ROWS_MASK); - if (col_mask == KP_COLS_MASK) - break; /* nothing */ - kp_last_col_mask = col_mask; - kp_stable = 0; - kp_state = SCAN_FILTER; - break; - - case SCAN_FILTER: - col_mask = kp_get_col_mask(KP_ROWS_MASK); - if (col_mask != kp_last_col_mask) { - kp_state = SCAN; - break; - } - - kp_stable += PHONE_CONSOLE_POLL_HZ; - if (kp_stable < KP_STABLE_HZ) - break; - - kp_cur_row = 0; - kp_stable = 0; - kp_state = SCAN_COL; - - (void)kp_get_col_mask(1 << kp_cur_row); - break; - - case SCAN_COL: - col_mask = kp_get_col_mask(1 << kp_cur_row); - if (col_mask == KP_COLS_MASK) { - if (++kp_cur_row >= KP_ROWS) { - kp_state = SCAN; - break; - } - kp_get_col_mask(1 << kp_cur_row); - break; - } - kp_last_col_mask = col_mask; - kp_stable = 0; - kp_state = SCAN_COL_FILTER; - break; - - case SCAN_COL_FILTER: - col_mask = kp_get_col_mask(1 << kp_cur_row); - if (col_mask != kp_last_col_mask || col_mask == KP_COLS_MASK) { - kp_state = SCAN; - break; - } - - kp_stable += PHONE_CONSOLE_POLL_HZ; - if (kp_stable < KP_STABLE_HZ) - break; - - for (col = 0; col < KP_COLS; col++) - if ((col_mask & (1 << col)) == 0) - break; - kp_cur_col = col; - kp_state = PRESSED; - kp_scancode = kp_scancodes[kp_cur_row * KP_COLS + kp_cur_col]; - kp_repeat = kp_repeats[kp_cur_row * KP_COLS + kp_cur_col]; - - if (kp_repeat) - kp_repeat_time = KP_REPEAT_DELAY_HZ; - kp_force_time = KP_FORCE_DELAY_HZ; - - scancode_action(kp_scancode); - - break; - - case PRESSED: - col_mask = kp_get_col_mask(1 << kp_cur_row); - if (col_mask != kp_last_col_mask) { - kp_state = SCAN; - scancode_action(KP_RELEASE); - kp_idle_time = KP_IDLE_DELAY_HZ; - break; - } - - if (kp_repeat) { - kp_repeat_time -= PHONE_CONSOLE_POLL_HZ; - if (kp_repeat_time <= 0) { - kp_repeat_time += KP_REPEAT_HZ; - scancode_action(kp_scancode); - } - } - - if (kp_force_time > 0) { - kp_force_time -= PHONE_CONSOLE_POLL_HZ; - if (kp_force_time <= 0) - scancode_action(KP_FORCE); - } - - break; - } -} - -/**************************************************************************************/ - -int drv_phone_is_idle(void) -{ - return kp_state == SCAN; -} diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds deleted file mode 100644 index 9f2901c..0000000 --- a/board/netphone/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug deleted file mode 100644 index 004e7fd..0000000 --- a/board/netphone/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/netta/Makefile b/board/netta/Makefile deleted file mode 100644 index 68e2402..0000000 --- a/board/netta/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o dsp.o codec.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/netta/codec.c b/board/netta/codec.c deleted file mode 100644 index 01ab14b..0000000 --- a/board/netta/codec.c +++ /dev/null @@ -1,1484 +0,0 @@ -/* - * CODEC - */ - -#include -#include - -#include "mpc8xx.h" - -/***********************************************/ - -#define MAX_DUSLIC 4 - -#define NUM_CHANNELS 2 -#define MAX_SLICS (MAX_DUSLIC * NUM_CHANNELS) - -/***********************************************/ - -#define SOP_READ_CH_0 0xC4 /* Read SOP Register for Channel A */ -#define SOP_READ_CH_1 0xCC /* Read SOP Register for Channel B */ -#define SOP_WRITE_CH_0 0x44 /* Write SOP Register for Channel A */ -#define SOP_WRITE_CH_1 0x4C /* Write SOP Register for Channel B */ - -#define COP_READ_CH_0 0xC5 -#define COP_READ_CH_1 0xCD -#define COP_WRITE_CH_0 0x45 -#define COP_WRITE_CH_1 0x4D - -#define POP_READ_CH_0 0xC6 -#define POP_READ_CH_1 0xCE -#define POP_WRITE_CH_0 0x46 -#define POP_WRITE_CH_1 0x4E - -#define RST_CMD_DUSLIC_CHIP 0x40 /* OR 0x48 */ -#define RST_CMD_DUSLIC_CH_A 0x41 -#define RST_CMD_DUSLIC_CH_B 0x49 - -#define PCM_RESYNC_CMD_CH_A 0x42 -#define PCM_RESYNC_CMD_CH_B 0x4A - -#define ACTIVE_HOOK_LEV_4 0 -#define ACTIVE_HOOK_LEV_12 1 - -#define SLIC_P_NORMAL 0x01 - -/************************************************/ - -#define CODSP_WR 0x00 -#define CODSP_RD 0x80 -#define CODSP_OP 0x40 -#define CODSP_ADR(x) (((unsigned char)(x) & 7) << 3) -#define CODSP_M(x) ((unsigned char)(x) & 7) -#define CODSP_CMD(x) ((unsigned char)(x) & 7) - -/************************************************/ - -/* command indication ops */ -#define CODSP_M_SLEEP_PWRDN 7 -#define CODSP_M_PWRDN_HIZ 0 -#define CODSP_M_ANY_ACT 2 -#define CODSP_M_RING 5 -#define CODSP_M_ACT_MET 6 -#define CODSP_M_GND_START 4 -#define CODSP_M_RING_PAUSE 1 - -/* single byte commands */ -#define CODSP_CMD_SOFT_RESET CODSP_CMD(0) -#define CODSP_CMD_RESET_CH CODSP_CMD(1) -#define CODSP_CMD_RESYNC CODSP_CMD(2) - -/* two byte commands */ -#define CODSP_CMD_SOP CODSP_CMD(4) -#define CODSP_CMD_COP CODSP_CMD(5) -#define CODSP_CMD_POP CODSP_CMD(6) - -/************************************************/ - -/* read as 4-bytes */ -#define CODSP_INTREG_INT_CH 0x80000000 -#define CODSP_INTREG_HOOK 0x40000000 -#define CODSP_INTREG_GNDK 0x20000000 -#define CODSP_INTREG_GNDP 0x10000000 -#define CODSP_INTREG_ICON 0x08000000 -#define CODSP_INTREG_VRTLIM 0x04000000 -#define CODSP_INTREG_OTEMP 0x02000000 -#define CODSP_INTREG_SYNC_FAIL 0x01000000 -#define CODSP_INTREG_LM_THRES 0x00800000 -#define CODSP_INTREG_READY 0x00400000 -#define CODSP_INTREG_RSTAT 0x00200000 -#define CODSP_INTREG_LM_OK 0x00100000 -#define CODSP_INTREG_IO4_DU 0x00080000 -#define CODSP_INTREG_IO3_DU 0x00040000 -#define CODSP_INTREG_IO2_DU 0x00020000 -#define CODSP_INTREG_IO1_DU 0x00010000 -#define CODSP_INTREG_DTMF_OK 0x00008000 -#define CODSP_INTREG_DTMF_KEY4 0x00004000 -#define CODSP_INTREG_DTMF_KEY3 0x00002000 -#define CODSP_INTREG_DTMF_KEY2 0x00001000 -#define CODSP_INTREG_DTMF_KEY1 0x00000800 -#define CODSP_INTREG_DTMF_KEY0 0x00000400 -#define CODSP_INTREG_UTDR_OK 0x00000200 -#define CODSP_INTREG_UTDX_OK 0x00000100 -#define CODSP_INTREG_EDSP_FAIL 0x00000080 -#define CODSP_INTREG_CIS_BOF 0x00000008 -#define CODSP_INTREG_CIS_BUF 0x00000004 -#define CODSP_INTREG_CIS_REQ 0x00000002 -#define CODSP_INTREG_CIS_ACT 0x00000001 - -/************************************************/ - -/* ======== SOP REG ADDRESSES =======*/ - -#define REVISION_ADDR 0x00 -#define PCMC1_ADDR 0x05 -#define XCR_ADDR 0x06 -#define INTREG1_ADDR 0x07 -#define INTREG2_ADDR 0x08 -#define INTREG3_ADDR 0x09 -#define INTREG4_ADDR 0x0A -#define LMRES1_ADDR 0x0D -#define MASK_ADDR 0x11 -#define IOCTL3_ADDR 0x14 -#define BCR1_ADDR 0x15 -#define BCR2_ADDR 0x16 -#define BCR3_ADDR 0x17 -#define BCR4_ADDR 0x18 -#define BCR5_ADDR 0x19 -#define DSCR_ADDR 0x1A -#define LMCR1_ADDR 0x1C -#define LMCR2_ADDR 0x1D -#define LMCR3_ADDR 0x1E -#define OFR1_ADDR 0x1F -#define PCMR1_ADDR 0x21 -#define PCMX1_ADDR 0x25 -#define TSTR3_ADDR 0x2B -#define TSTR4_ADDR 0x2C -#define TSTR5_ADDR 0x2D - -/* ========= POP REG ADDRESSES ========*/ - -#define CIS_DAT_ADDR 0x00 - -#define LEC_LEN_ADDR 0x3A -#define LEC_POWR_ADDR 0x3B -#define LEC_DELP_ADDR 0x3C -#define LEC_DELQ_ADDR 0x3D -#define LEC_GAIN_XI_ADDR 0x3E -#define LEC_GAIN_RI_ADDR 0x3F -#define LEC_GAIN_XO_ADDR 0x40 -#define LEC_RES_1_ADDR 0x41 -#define LEC_RES_2_ADDR 0x42 - -#define NLP_POW_LPF_ADDR 0x30 -#define NLP_POW_LPS_ADDR 0x31 -#define NLP_BN_LEV_X_ADDR 0x32 -#define NLP_BN_LEV_R_ADDR 0x33 -#define NLP_BN_INC_ADDR 0x34 -#define NLP_BN_DEC_ADDR 0x35 -#define NLP_BN_MAX_ADDR 0x36 -#define NLP_BN_ADJ_ADDR 0x37 -#define NLP_RE_MIN_ERLL_ADDR 0x38 -#define NLP_RE_EST_ERLL_ADDR 0x39 -#define NLP_SD_LEV_X_ADDR 0x3A -#define NLP_SD_LEV_R_ADDR 0x3B -#define NLP_SD_LEV_BN_ADDR 0x3C -#define NLP_SD_LEV_RE_ADDR 0x3D -#define NLP_SD_OT_DT_ADDR 0x3E -#define NLP_ERL_LIN_LP_ADDR 0x3F -#define NLP_ERL_LEC_LP_ADDR 0x40 -#define NLP_CT_LEV_RE_ADDR 0x41 -#define NLP_CTRL_ADDR 0x42 - -#define UTD_CF_H_ADDR 0x4B -#define UTD_CF_L_ADDR 0x4C -#define UTD_BW_H_ADDR 0x4D -#define UTD_BW_L_ADDR 0x4E -#define UTD_NLEV_ADDR 0x4F -#define UTD_SLEV_H_ADDR 0x50 -#define UTD_SLEV_L_ADDR 0x51 -#define UTD_DELT_ADDR 0x52 -#define UTD_RBRK_ADDR 0x53 -#define UTD_RTIME_ADDR 0x54 -#define UTD_EBRK_ADDR 0x55 -#define UTD_ETIME_ADDR 0x56 - -#define DTMF_LEV_ADDR 0x30 -#define DTMF_TWI_ADDR 0x31 -#define DTMF_NCF_H_ADDR 0x32 -#define DTMF_NCF_L_ADDR 0x33 -#define DTMF_NBW_H_ADDR 0x34 -#define DTMF_NBW_L_ADDR 0x35 -#define DTMF_GAIN_ADDR 0x36 -#define DTMF_RES1_ADDR 0x37 -#define DTMF_RES2_ADDR 0x38 -#define DTMF_RES3_ADDR 0x39 - -#define CIS_LEV_H_ADDR 0x43 -#define CIS_LEV_L_ADDR 0x44 -#define CIS_BRS_ADDR 0x45 -#define CIS_SEIZ_H_ADDR 0x46 -#define CIS_SEIZ_L_ADDR 0x47 -#define CIS_MARK_H_ADDR 0x48 -#define CIS_MARK_L_ADDR 0x49 -#define CIS_LEC_MODE_ADDR 0x4A - -/*=====================================*/ - -#define HOOK_LEV_ACT_START_ADDR 0x89 -#define RO1_START_ADDR 0x70 -#define RO2_START_ADDR 0x95 -#define RO3_START_ADDR 0x96 - -#define TG1_FREQ_START_ADDR 0x38 -#define TG1_GAIN_START_ADDR 0x39 -#define TG1_BANDPASS_START_ADDR 0x3B -#define TG1_BANDPASS_END_ADDR 0x3D - -#define TG2_FREQ_START_ADDR 0x40 -#define TG2_GAIN_START_ADDR 0x41 -#define TG2_BANDPASS_START_ADDR 0x43 -#define TG2_BANDPASS_END_ADDR 0x45 - -/*====================================*/ - -#define PCM_HW_B 0x80 -#define PCM_HW_A 0x00 -#define PCM_TIME_SLOT_0 0x00 /* Byte 0 of PCM Frame (by default is assigned to channel A ) */ -#define PCM_TIME_SLOT_1 0x01 /* Byte 1 of PCM Frame (by default is assigned to channel B ) */ -#define PCM_TIME_SLOT_4 0x04 /* Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */ - -#define RX_LEV_ADDR 0x28 -#define TX_LEV_ADDR 0x30 -#define Ik1_ADDR 0x83 - -#define AR_ROW 3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */ -#define AX_ROW 6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */ -#define DCF_ROW 0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */ - -/* Mark the start byte of Duslic parameters that we use with configurator */ -#define Ik1_START_BYTE 3 -#define RX_LEV_START_BYTE 0 -#define TX_LEV_START_BYTE 0 - -/************************************************/ - -#define INTREG4_CIS_ACT (1 << 0) - -#define BCR1_SLEEP 0x20 -#define BCR1_REVPOL 0x10 -#define BCR1_ACTR 0x08 -#define BCR1_ACTL 0x04 -#define BCR1_SLIC_MASK 0x03 - -#define BCR2_HARD_POL_REV 0x40 -#define BCR2_TTX 0x20 -#define BCR2_TTX_12K 0x10 -#define BCR2_HIMAN 0x08 -#define BCR2_PDOT 0x01 - -#define BCR3_PCMX_EN (1 << 4) - -#define BCR5_DTMF_EN (1 << 0) -#define BCR5_DTMF_SRC (1 << 1) -#define BCR5_LEC_EN (1 << 2) -#define BCR5_LEC_OUT (1 << 3) -#define BCR5_CIS_EN (1 << 4) -#define BCR5_CIS_AUTO (1 << 5) -#define BCR5_UTDX_EN (1 << 6) -#define BCR5_UTDR_EN (1 << 7) - -#define DSCR_TG1_EN (1 << 0) -#define DSCR_TG2_EN (1 << 1) -#define DSCR_PTG (1 << 2) -#define DSCR_COR8 (1 << 3) -#define DSCR_DG_KEY(x) (((x) & 0x0F) << 4) - -#define CIS_LEC_MODE_CIS_V23 (1 << 0) -#define CIS_LEC_MODE_CIS_FRM (1 << 1) -#define CIS_LEC_MODE_NLP_EN (1 << 2) -#define CIS_LEC_MODE_UTDR_SUM (1 << 4) -#define CIS_LEC_MODE_UTDX_SUM (1 << 5) -#define CIS_LEC_MODE_LEC_FREEZE (1 << 6) -#define CIS_LEC_MODE_LEC_ADAPT (1 << 7) - -#define TSTR4_COR_64 (1 << 5) - -#define TSTR3_AC_DLB_8K (1 << 2) -#define TSTR3_AC_DLB_32K (1 << 3) -#define TSTR3_AC_DLB_4M (1 << 5) - - -#define LMCR1_TEST_EN (1 << 7) -#define LMCR1_LM_EN (1 << 6) -#define LMCR1_LM_THM (1 << 5) -#define LMCR1_LM_ONCE (1 << 2) -#define LMCR1_LM_MASK (1 << 1) - -#define LMCR2_LM_RECT (1 << 5) -#define LMCR2_LM_SEL_VDD 0x0D -#define LMCR2_LM_SEL_IO3 0x0A -#define LMCR2_LM_SEL_IO4 0x0B -#define LMCR2_LM_SEL_IO4_MINUS_IO3 0x0F - -#define LMCR3_RTR_SEL (1 << 6) - -#define LMCR3_RNG_OFFSET_NONE 0x00 -#define LMCR3_RNG_OFFSET_1 0x01 -#define LMCR3_RNG_OFFSET_2 0x02 -#define LMCR3_RNG_OFFSET_3 0x03 - -#define TSTR5_DC_HOLD (1 << 3) - -/************************************************/ - -#define TARGET_ONHOOK_BATH_x100 4600 /* 46.0 Volt */ -#define TARGET_ONHOOK_BATL_x100 2500 /* 25.0 Volt */ -#define TARGET_V_DIVIDER_RATIO_x100 21376L /* (R1+R2)/R2 = 213.76 */ -#define DIVIDER_RATIO_ACCURx100 (22 * 100) -#define V_AD_x10000 10834L /* VAD = 1.0834 */ -#define TARGET_VDDx100 330 /* VDD = 3.3 * 10 */ -#define VDD_MAX_DIFFx100 20 /* VDD Accur = 0.2*100 */ - -#define RMS_MULTIPLIERx100 111 /* pi/(2xsqrt(2)) = 1.11*/ -#define K_INTDC_RECT_ON 4 /* When Rectifier is ON this value is necessary(2^4) */ -#define K_INTDC_RECT_OFF 2 /* 2^2 */ -#define RNG_FREQ 25 -#define SAMPLING_FREQ (2000L) -#define N_SAMPLES (SAMPLING_FREQ/RNG_FREQ) /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */ -#define HOOK_THRESH_RING_START_ADDR 0x8B -#define RING_PARAMS_START_ADDR 0x70 - -#define V_OUT_BATH_MAX_DIFFx100 300 /* 3.0 x100 */ -#define V_OUT_BATL_MAX_DIFFx100 400 /* 4.0 x100 */ -#define MAX_V_RING_MEANx100 50 -#define TARGET_V_RING_RMSx100 2720 -#define V_RMS_RING_MAX_DIFFx100 250 - -#define LM_OK_SRC_IRG_2 (1 << 4) - -/************************************************/ - -#define PORTB (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define PORTC (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) -#define PORTD (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) - -#define _PORTD_SET(mask, state) \ - do { \ - if (state) \ - PORTD |= mask; \ - else \ - PORTD &= ~mask; \ - } while (0) - -#define _PORTB_SET(mask, state) \ - do { \ - if (state) \ - PORTB |= mask; \ - else \ - PORTB &= ~mask; \ - } while (0) - -#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0) -#define _PORTB_GET(mask) (!!(PORTB & mask)) - -#define _PORTC_GET(mask) (!!(PORTC & mask)) - -/* port B */ -#define SPI_RXD (1 << (31 - 28)) -#define SPI_TXD (1 << (31 - 29)) -#define SPI_CLK (1 << (31 - 30)) - -/* port C */ -#define COM_HOOK1 (1 << (15 - 9)) -#define COM_HOOK2 (1 << (15 - 10)) - -#ifndef CONFIG_NETTA_SWAPHOOK - -#define COM_HOOK3 (1 << (15 - 11)) -#define COM_HOOK4 (1 << (15 - 12)) - -#else - -#define COM_HOOK3 (1 << (15 - 12)) -#define COM_HOOK4 (1 << (15 - 11)) - -#endif - -/* port D */ -#define SPIENC1 (1 << (15 - 9)) -#define SPIENC2 (1 << (15 - 10)) -#define SPIENC3 (1 << (15 - 11)) -#define SPIENC4 (1 << (15 - 14)) - -#define SPI_DELAY() udelay(1) - -static inline unsigned int __SPI_Transfer(unsigned int tx) -{ - unsigned int rx; - int b; - - rx = 0; b = 8; - while (--b >= 0) { - _PORTB_SET(SPI_TXD, tx & 0x80); - tx <<= 1; - _PORTB_TGL(SPI_CLK); - SPI_DELAY(); - rx <<= 1; - rx |= _PORTB_GET(SPI_RXD); - _PORTB_TGL(SPI_CLK); - SPI_DELAY(); - } - - return rx; -} - -static const char *codsp_dtmf_map = "D1234567890*#ABC"; - -static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 }; -static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 }; - -static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen) -{ - unsigned int rx; - int i; - - /* just some sanity checks */ - if (cmd == 0 || cmdlen < 0) - return -1; - - _PORTD_SET(spienc_mask_tab[duslic_id], 0); - - /* first 2 bytes are without response */ - i = 2; - while (i-- > 0 && cmdlen-- > 0) - __SPI_Transfer(*cmd++); - - while (cmdlen-- > 0) { - rx = __SPI_Transfer(*cmd++); - if (res != 0 && reslen-- > 0) - *res++ = (unsigned char)rx; - } - if (res != 0) { - while (reslen-- > 0) - *res++ = __SPI_Transfer(0xFF); - } - - _PORTD_SET(spienc_mask_tab[duslic_id], 1); - - return 0; -} - -/****************************************************************************/ - -void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m) -{ - unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m); - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -void codsp_reset_chip(int duslic_id) -{ - static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET; - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -void codsp_reset_channel(int duslic_id, int channel) -{ - unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH; - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -void codsp_resync_channel(int duslic_id, int channel) -{ - unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC; - codsp_send(duslic_id, &cmd, 1, 0, 0); -} - -/****************************************************************************/ - -void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val) -{ - unsigned char cmd[3]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - cmd[2] = val; - - codsp_send(duslic_id, cmd, 3, 0, 0); -} - -void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val) -{ - unsigned char cmd[4]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - cmd[2] = (unsigned char)(val >> 8); - cmd[3] = (unsigned char)val; - - codsp_send(duslic_id, cmd, 4, 0, 0); -} - -void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val) -{ - unsigned char cmd[5]; - - cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - cmd[2] = (unsigned char)(val >> 24); - cmd[3] = (unsigned char)(val >> 16); - cmd[4] = (unsigned char)(val >> 8); - cmd[5] = (unsigned char)val; - - codsp_send(duslic_id, cmd, 6, 0, 0); -} - -unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno) -{ - unsigned char cmd[3]; - unsigned char res[2]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - - codsp_send(duslic_id, cmd, 2, res, 2); - - return res[1]; -} - -unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[3]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - - codsp_send(duslic_id, cmd, 2, res, 3); - - return ((unsigned short)res[1] << 8) | res[2]; -} - -unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[5]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP; - cmd[1] = regno; - - codsp_send(duslic_id, cmd, 2, res, 5); - - return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4]; -} - -/****************************************************************************/ - -void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block) -{ - unsigned char cmd[10]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - memcpy(cmd + 2, block, 8); - codsp_send(duslic_id, cmd, 10, 0, 0); -} - -void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val) -{ - unsigned char cmd[3]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - cmd[2] = val; - codsp_send(duslic_id, cmd, 3, 0, 0); -} - -void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val) -{ - unsigned char cmd[3]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - cmd[2] = (unsigned char)(val >> 8); - cmd[3] = (unsigned char)val; - - codsp_send(duslic_id, cmd, 4, 0, 0); -} - -void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block) -{ - unsigned char cmd[2]; - unsigned char res[9]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - codsp_send(duslic_id, cmd, 2, res, 9); - memcpy(block, res + 1, 8); -} - -unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr) -{ - unsigned char cmd[2]; - unsigned char res[2]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - codsp_send(duslic_id, cmd, 2, res, 2); - return res[1]; -} - -unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr) -{ - unsigned char cmd[2]; - unsigned char res[3]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP; - cmd[1] = addr; - - codsp_send(duslic_id, cmd, 2, res, 3); - - return ((unsigned short)res[1] << 8) | res[2]; -} - -/****************************************************************************/ - -#define MAX_POP_BLOCK 50 - -void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr, - const unsigned char *block, int len) -{ - unsigned char cmd[2 + MAX_POP_BLOCK]; - - if (len > MAX_POP_BLOCK) /* truncate */ - len = MAX_POP_BLOCK; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = addr; - memcpy (cmd + 2, block, len); - codsp_send (duslic_id, cmd, 2 + len, 0, 0); -} - -void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno, - unsigned char val) -{ - unsigned char cmd[3]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - cmd[2] = val; - - codsp_send (duslic_id, cmd, 3, 0, 0); -} - -void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno, - unsigned short val) -{ - unsigned char cmd[4]; - - cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - cmd[2] = (unsigned char) (val >> 8); - cmd[3] = (unsigned char) val; - - codsp_send (duslic_id, cmd, 4, 0, 0); -} - -void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno, - unsigned int val) -{ - unsigned char cmd[5]; - - cmd[0] = CODSP_WR | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - cmd[2] = (unsigned char) (val >> 24); - cmd[3] = (unsigned char) (val >> 16); - cmd[4] = (unsigned char) (val >> 8); - cmd[5] = (unsigned char) val; - - codsp_send (duslic_id, cmd, 6, 0, 0); -} - -unsigned char codsp_read_pop_char (int duslic_id, int channel, - unsigned char regno) -{ - unsigned char cmd[3]; - unsigned char res[2]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - - codsp_send (duslic_id, cmd, 2, res, 2); - - return res[1]; -} - -unsigned short codsp_read_pop_short (int duslic_id, int channel, - unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[3]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - - codsp_send (duslic_id, cmd, 2, res, 3); - - return ((unsigned short) res[1] << 8) | res[2]; -} - -unsigned int codsp_read_pop_int (int duslic_id, int channel, - unsigned char regno) -{ - unsigned char cmd[2]; - unsigned char res[5]; - - cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP; - cmd[1] = regno; - - codsp_send (duslic_id, cmd, 2, res, 5); - - return (((unsigned int) res[1] << 24) | - ((unsigned int) res[2] << 16) | - ((unsigned int) res[3] << 8) | - res[4] ); -} -/****************************************************************************/ - -struct _coeffs { - unsigned char addr; - unsigned char values[8]; -}; - -struct _coeffs ac_coeffs[11] = { - { 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */ - { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */ - { 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter */ - { 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter */ - { 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter */ - { 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter */ - { 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter */ - { 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter */ - { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */ - { 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */ - { 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} } /* 0x10 TH-Filter part 3 */ -}; - -struct _coeffs ac_coeffs_0dB[11] = { - { 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} }, - { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} }, - { 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} }, - { 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} }, - { 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} }, - { 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} }, - { 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} }, - { 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} }, - { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, - { 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} }, - { 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} } -}; - -struct _coeffs dc_coeffs[9] = { - { 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter */ - { 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing */ - { 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters */ - { 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels */ - { 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator */ - { 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX */ - { 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1 */ - { 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2 */ - { 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} } /* 0x98 Reserved */ -}; - -void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size) -{ - int i; - - for (i = 0; i < tab_size; i++) - codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values); -} - -#define SS_OPEN_CIRCUIT 0 -#define SS_RING_PAUSE 1 -#define SS_ACTIVE 2 -#define SS_ACTIVE_HIGH 3 -#define SS_ACTIVE_RING 4 -#define SS_RINGING 5 -#define SS_ACTIVE_WITH_METERING 6 -#define SS_ONHOOKTRNSM 7 -#define SS_STANDBY 8 -#define SS_MAX 8 - -static void codsp_set_slic(int duslic_id, int channel, int state) -{ - unsigned char v; - - v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR); - - switch (state) { - - case SS_ACTIVE: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) | BCR1_ACTL); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); - break; - - case SS_ACTIVE_HIGH: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR | BCR1_ACTL)); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); - break; - - case SS_ACTIVE_RING: - case SS_ONHOOKTRNSM: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT); - break; - - case SS_STANDBY: - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL | BCR1_ACTR)); - codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN); - break; - - case SS_OPEN_CIRCUIT: - codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ); - break; - - case SS_RINGING: - codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING); - break; - - case SS_RING_PAUSE: - codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE); - break; - } -} - -const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 }; -const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 }; - -void retrieve_slic_state(int slic_id) -{ - int duslic_id = slic_id >> 1; - int channel = slic_id & 1; - - /* Retrieve the state of the SLICs */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); - - /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ - udelay(10000); - - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); - codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); - - /* Program Default Hook Ring thresholds */ - codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values); - - /* Now program Hook Threshold while Ring and ac RingTrip to max values */ - codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values); - - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); - - udelay(40000); -} - -int wait_level_metering_finish(int duslic_id, int channel) -{ - int cnt; - - for (cnt = 0; cnt < 1000 && - (codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { } - - return cnt != 1000; -} - -int measure_on_hook_voltages(int slic_id, long *vdd, - long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v) -{ - short LM_Result, Offset_Compensation; /* Signed 16 bit */ - long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ; - unsigned char err_mask = 0; - int duslic_id = slic_id >> 1; - int channel = slic_id & 1; - int i; - - /* measure VDD */ - /* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */ - codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD); - - /* Activate Test Mode ==> To Enable DC Hold !!! */ - /* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */ - /* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK); - - udelay(40000); - - /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD); - - /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ - udelay(10000); - - /* Now Read the LM Result Registers */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - VDD = (-1)*((((long int)LM_Result) * 390L ) >> 15) ; /* VDDx100 */ - - *vdd = VDD; - - VDD_diff = VDD - TARGET_VDDx100; - - if (VDD_diff < 0) - VDD_diff = -VDD_diff; - - if (VDD_diff > VDD_MAX_DIFFx100) - err_mask |= 1; - - Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100; - - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - - codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */ - - udelay(40000); - - codsp_write_sop_char(duslic_id, channel, - LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK); - - udelay(40000); - - /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3); - - /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */ - udelay(10000); - - /* Now Read the LM Result Registers */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/ - - V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ - - *v_oh_H = V_out; - - Vout_diff = V_out - TARGET_ONHOOK_BATH_x100; - - if (Vout_diff < 0) - Vout_diff = -Vout_diff; - - if (Vout_diff > V_OUT_BATH_MAX_DIFFx100) - err_mask |= 2; - - codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */ - - udelay(40000); - - /* Now Read the LM Result Registers */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - - V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/ - - V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ - - *v_oh_L = V_out; - - Vout_diff = V_out - TARGET_ONHOOK_BATL_x100; - - if (Vout_diff < 0) - Vout_diff = -Vout_diff; - - if (Vout_diff > V_OUT_BATL_MAX_DIFFx100) - err_mask |= 4; - - /* perform ring tests */ - - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00); - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - - udelay(40000); - - codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL | LMCR3_RNG_OFFSET_NONE); - - /* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/ - codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz); - - /* By Default RO1 is selected when ringing RNG-OFFSET = 00 */ - - /* Now program Hook Threshold while Ring and ac RingTrip to max values */ - for(i = 0; i < sizeof(Max_HookRingTh); i++) - codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]); - - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); - - codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */ - - /* select source for the levelmeter to be IO4-IO3 */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3); - - udelay(40000); - - /* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */ - codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF); - - udelay(10000); - - /* Enable LevelMeter to Integrate only once (Rectifier Disabled) */ - codsp_write_sop_char(duslic_id, channel, - LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */ - - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */ - - /* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */ - Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES); - - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); - - /* Now programm Integrator Offset Registers !!! */ - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation); - - codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */ - - udelay(40000); - - /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ - codsp_write_sop_char(duslic_id, channel, - LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */ - - /* Poll the LM_OK bit to see when Integration Result is Ready */ - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */ - - /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ - /* ==>After that Result Regs will be updated every 500us !!!) */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ; /* Vin x 10000*/ - - V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */ - - if (V_out < 0) - V_out= -V_out; - - if (V_out > MAX_V_RING_MEANx100) - err_mask |= 8; - - *ring_mean_v = V_out; - } else { - err_mask |= 8; - *ring_mean_v = 0; - } - } else { - err_mask |= 8; - *ring_mean_v = 0; - } - - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, - LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000); - - codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */ - - /* Now Enable Rectifier */ - /* select source for the levelmeter to be IO4-IO3 */ - codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, - LMCR2_LM_SEL_IO4_MINUS_IO3 | LMCR2_LM_RECT); - - /* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */ - codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON); - - udelay(40000); - - /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, - LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); - - /* Poll the LM_OK bit to see when Integration Result is Ready */ - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); - - /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ - /* ==>After that Result Regs will be updated every 500us !!!) */ - Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES); - - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE); - - /* Now programm Integrator Offset Registers !!! */ - codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation); - - /* Be sure that a Ring is generated !!!! */ - codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */ - - udelay(40000); - - /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, - LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE); - - udelay(40000); - - /* Poll the LM_OK bit to see when Integration Result is Ready */ - if (wait_level_metering_finish(duslic_id, channel)) { - - udelay(10000); - - /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */ - /* ==>After that Result Regs will be updated every 500us !!!) */ - LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR); - V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ; /* Vin x 10000*/ - - V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ; /* Vout_RMS x100 */ - if (V_out < 0) - V_out = -V_out; - - Vout_diff = (V_out - TARGET_V_RING_RMSx100); - - if (Vout_diff < 0) - Vout_diff = -Vout_diff; - - if (Vout_diff > V_RMS_RING_MAX_DIFFx100) - err_mask |= 16; - - *ring_rms_v = V_out; - } else { - err_mask |= 16; - *ring_rms_v = 0; - } - } else { - err_mask |= 16; - *ring_rms_v = 0; - } - /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */ - codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK); - - retrieve_slic_state(slic_id); - - return(err_mask); -} - -int test_dtmf(int slic_id) -{ - unsigned char code; - unsigned char b; - unsigned int intreg; - int duslic_id = slic_id >> 1; - int channel = slic_id & 1; - - for (code = 0; code < 16; code++) { - b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, - (b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN); - udelay(80000); - - intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); - if ((intreg & CODSP_INTREG_INT_CH) == 0) - break; - - if ((intreg & CODSP_INTREG_DTMF_OK) == 0 || - codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code]) - break; - - b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, - b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN)); - - udelay(80000); - - intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */ - } - - if (code != 16) { - b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */ - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, - b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN)); - return(1); - } - - return(0); -} - -void data_up_persist_time(int duslic_id, int channel, int time_ms) -{ - unsigned char b; - - b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR); - b = (b & 0x0F) | ((time_ms & 0x0F) << 4); - codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b); -} - -static void program_dtmf_params(int duslic_id, int channel) -{ - unsigned char b; - - codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10); - codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C); - codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79); - codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10); - codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02); - codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB); - codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91); - codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00); - codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00); - codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00); - - b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR); - codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b | BCR5_DTMF_EN); -} - -static void codsp_channel_full_reset(int duslic_id, int channel) -{ - - program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs)); - program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs)); - - /* program basic configuration registers */ - codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01); - codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41); - codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43); - codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00); - codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00); - - codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04); /* PG */ - - program_dtmf_params(duslic_id, channel); - - codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); /* RingTRip_SEL */ - - data_up_persist_time(duslic_id, channel, 4); - - codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF); /* All interrupts masked */ - - codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); -} - -static int codsp_chip_full_reset(int duslic_id) -{ - int i, cnt; - int intreg[NUM_CHANNELS]; - unsigned char pcm_resync; - unsigned char revision; - - codsp_reset_chip(duslic_id); - - udelay(2000); - - for (i = 0; i < NUM_CHANNELS; i++) - intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR); - - udelay(1500); - - if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) { - printf("_HOOK(%d) stayed low\n", duslic_id); - return -1; - } - - for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) { - if (intreg[i] & CODSP_INTREG_SYNC_FAIL) - pcm_resync |= 1 << i; - } - - for (cnt = 0; cnt < 5 && pcm_resync; cnt++) { - for (i = 0; i < NUM_CHANNELS; i++) - codsp_resync_channel(duslic_id, i); - - udelay(2000); - - pcm_resync = 0; - - for (i = 0; i < NUM_CHANNELS; i++) { - if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL) - pcm_resync |= 1 << i; - } - } - - if (cnt == 5) { - printf("PCM_Resync(%u) not completed\n", duslic_id); - return -2; - } - - revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR); - printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F); - - codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80); /* EDSP_EN */ - - for (i = 0; i < NUM_CHANNELS; i++) { - codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01); - codsp_channel_full_reset(duslic_id, i); - } - - return 0; -} - -int slic_self_test(int duslic_mask) -{ - int slic; - int i; - int r; - long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v; - const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" }; - int error = 0; - - for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */ - if (duslic_mask & (1 << (slic >> 1))) { - r = measure_on_hook_voltages(slic, &vdd, - &v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v); - - printf("SLIC %u measured voltages (x100):\n\t" - "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n", - slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v); - - if (r != 0) - error |= 1 << slic; - - for (i = 0; i < 5; i++) - if (r & (1 << i)) - printf("\t%s out of range\n", err_txt[i]); - } - } - - for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */ - if (duslic_mask & (1 << (slic >> 1))) { - printf("SLIC %u VOICE PATH...CHECKING", slic); - printf("\rSLIC %u VOICE PATH...%s\n", slic, - (r = test_dtmf(slic)) != 0 ? "FAILED " : "PASSED "); - - if (r != 0) - error |= 1 << slic; - } - } - - return(error); -} - -#if defined(CONFIG_NETTA_ISDN) - -#define SPIENS1 (1 << (31 - 15)) -#define SPIENS2 (1 << (31 - 19)) - -static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 }; -int s_initialized = 0; - -static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value) -{ - unsigned int rx, v; - - _PORTB_SET(spiens_mask_tab[s_id], 0); - - rx = __SPI_Transfer(address); - - switch (address & 0xF0) { - case 0x60: /* write byte register */ - case 0x70: - rx = __SPI_Transfer(value); - break; - - case 0xE0: /* read R6 register */ - v = __SPI_Transfer(0); - - rx = (rx << 8) | v; - - break; - - case 0xF0: /* read byte register */ - rx = __SPI_Transfer(0); - - break; - } - - _PORTB_SET(spiens_mask_tab[s_id], 1); - - return rx; -} - -static void s_write_BR(int s_id, unsigned int regno, unsigned int val) -{ - unsigned int address; - unsigned int v; - - address = 0x70 | (regno & 15); - val &= 0xff; - - v = s_transfer_internal(s_id, address, val); -} - -static void s_write_OR(int s_id, unsigned int regno, unsigned int val) -{ - unsigned int address; - unsigned int v; - - address = 0x70 | (regno & 15); - val &= 0xff; - - v = s_transfer_internal(s_id, address, val); -} - -static void s_write_NR(int s_id, unsigned int regno, unsigned int val) -{ - unsigned int address; - unsigned int v; - - address = (regno & 7) << 4; - val &= 0xf; - - v = s_transfer_internal(s_id, address | val, 0x00); -} - -#define BR7_IFR 0x08 /* IDL2 free run */ -#define BR7_ICSLSB 0x04 /* IDL2 clock speed LSB */ - -#define BR15_OVRL_REG_EN 0x80 -#define OR7_D3VR 0x80 /* disable 3V regulator */ - -#define OR8_TEME 0x10 /* TE mode enable */ -#define OR8_MME 0x08 /* master mode enable */ - -void s_initialize(void) -{ - int s_id; - - for (s_id = 0; s_id < 2; s_id++) { - s_write_BR(s_id, 7, BR7_IFR | BR7_ICSLSB); - s_write_BR(s_id, 15, BR15_OVRL_REG_EN); - s_write_OR(s_id, 8, OR8_TEME | OR8_MME); - s_write_OR(s_id, 7, OR7_D3VR); - s_write_OR(s_id, 6, 0); - s_write_BR(s_id, 15, 0); - s_write_NR(s_id, 3, 0); - } -} - -#endif - -int board_post_codec(int flags) -{ - int j; - int r; - int duslic_mask; - - printf("board_post_dsp\n"); - -#if defined(CONFIG_NETTA_ISDN) - if (s_initialized == 0) { - s_initialize(); - s_initialized = 1; - - printf("s_initialized\n"); - - udelay(20000); - } -#endif - duslic_mask = 0; - - for (j = 0; j < MAX_DUSLIC; j++) { - if (codsp_chip_full_reset(j) < 0) - printf("Error initializing DuSLIC#%d\n", j); - else - duslic_mask |= 1 << j; - } - - if (duslic_mask != 0) { - printf("Testing SLICs...\n"); - - r = slic_self_test(duslic_mask); - for (j = 0; j < MAX_SLICS; j++) { - if (duslic_mask & (1 << (j >> 1))) - printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK"); - } - } - printf("DuSLIC self test finished\n"); - - return 0; /* return -1 on error */ -} diff --git a/board/netta/config.mk b/board/netta/config.mk deleted file mode 100644 index 8497ebc..0000000 --- a/board/netta/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# netVia Boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/netta/dsp.c b/board/netta/dsp.c deleted file mode 100644 index 66e0b85..0000000 --- a/board/netta/dsp.c +++ /dev/null @@ -1,1208 +0,0 @@ -/* - * Intracom TI6711/TI6412 DSP - */ - -#include -#include - -#include "mpc8xx.h" - -struct ram_range { - u32 start; - u32 size; -}; - -#if defined(CONFIG_NETTA_6412) - -static const struct ram_range int_ram[] = { - { 0x00000000U, 0x00040000U }, -}; - -static const struct ram_range ext_ram[] = { - { 0x80000000U, 0x00100000U }, -}; - -static const struct ram_range ranges[] = { - { 0x00000000U, 0x00040000U }, - { 0x80000000U, 0x00100000U }, -}; - -static inline u16 bit_invert(u16 d) -{ - register u8 i; - register u16 r; - register u16 bit; - - r = 0; - for (i = 0; i < 16; i++) { - bit = d & (1 << i); - if (bit != 0) - r |= 1 << (15 - i); - } - return r; -} - -#else - -static const struct ram_range int_ram[] = { - { 0x00000000U, 0x00010000U }, -}; - -static const struct ram_range ext_ram[] = { - { 0x80000000U, 0x00100000U }, -}; - -static const struct ram_range ranges[] = { - { 0x00000000U, 0x00010000U }, - { 0x80000000U, 0x00100000U }, -}; - -#endif - -/*******************************************************************************************************/ - -static inline int addr_in_int_ram(u32 addr) -{ - int i; - - for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++) - if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size) - return 1; - - return 0; -} - -static inline int addr_in_ext_ram(u32 addr) -{ - int i; - - for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++) - if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size) - return 1; - - return 0; -} - -/*******************************************************************************************************/ - -#define DSP_HPIC 0x0 -#define DSP_HPIA 0x4 -#define DSP_HPID1 0x8 -#define DSP_HPID2 0xC - -static u32 dummy_delay; -static volatile u32 *ti6711_delay = &dummy_delay; - -static inline void dsp_go_slow(void) -{ - volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl; -#if defined(CONFIG_NETTA_6412) - memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX; -#else - memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX; -#endif - memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX; - - ti6711_delay = (u32 *)DUMMY_BASE; -} - -static inline void dsp_go_fast(void) -{ - volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl; -#if defined(CONFIG_NETTA_6412) - memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK; -#else - memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK; -#endif - memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK; - - ti6711_delay = &dummy_delay; -} - -/*******************************************************************************************************/ - -static inline void dsp_delay(void) -{ - /* perform ti6711_delay chip select read to have a small delay */ - (void) *(volatile u32 *)ti6711_delay; -} - -static inline u16 dsp_read_hpic(void) -{ -#if defined(CONFIG_NETTA_6412) - return bit_invert(*((volatile u16 *)DSP_BASE)); -#else - return *((volatile u16 *)DSP_BASE); -#endif -} - -static inline void dsp_write_hpic(u16 val) -{ -#if defined(CONFIG_NETTA_6412) - *((volatile u16 *)DSP_BASE) = bit_invert(val); -#else - *((volatile u16 *)DSP_BASE) = val; -#endif -} - -static inline void dsp_reset(void) -{ -#if defined(CONFIG_NETTA_6412) - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15)); - udelay(500); - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 15)); - udelay(500); -#else - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7)); - udelay(250); - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 7)); - udelay(250); -#endif -} - -static inline u32 dsp_read_hpic_word(u32 addr) -{ - u32 val; - volatile u16 *p; -#if defined(CONFIG_NETTA_6412) - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - - val = ((u32) bit_invert(p[0]) << 16); - /* dsp_delay(); */ - - val |= bit_invert(p[1]); - /* dsp_delay(); */ -#else - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - - val = ((u32) p[0] << 16); - dsp_delay(); - - val |= p[1]; - dsp_delay(); -#endif - return val; -} - -static inline u16 dsp_read_hpic_hi_hword(u32 addr) -{ -#if defined(CONFIG_NETTA_6412) - return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr)); -#else - return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr); -#endif -} - -static inline u16 dsp_read_hpic_lo_hword(u32 addr) -{ -#if defined(CONFIG_NETTA_6412) - return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2)); -#else - return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2); -#endif -} - -static inline void dsp_wait_hrdy(void) -{ - int i; - - i = 0; -#if defined(CONFIG_NETTA_6412) - while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) { -#else - while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) { -#endif - dsp_delay(); - i++; - } -} - -static inline void dsp_write_hpic_word(u32 addr, u32 val) -{ - volatile u16 *p; -#if defined(CONFIG_NETTA_6412) - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - p[0] = bit_invert((u16)(val >> 16)); - /* dsp_delay(); */ - - p[1] = bit_invert((u16)val); - /* dsp_delay(); */ -#else - p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr); - p[0] = (u16)(val >> 16); - dsp_delay(); - - p[1] = (u16)val; - dsp_delay(); -#endif -} - -static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h) -{ -#if defined(CONFIG_NETTA_6412) - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h); -#else - - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h; -#endif -} - -static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l) -{ -#if defined(CONFIG_NETTA_6412) - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l); -#else - *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l; -#endif -} - -/********************************************************************/ - -static inline void c62_write_word(u32 addr, u32 val) -{ - dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16)); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - - dsp_wait_hrdy(); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16)); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); - - /* dsp_wait_hrdy(); - dsp_delay(); */ -#endif - dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif -} - -static u32 c62_read_word(u32 addr) -{ - u32 val; - - dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16)); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - - /* FETCH */ -#if defined(CONFIG_NETTA_6412) - dsp_write_hpic_word(DSP_HPIC, 0x00100010); -#else - dsp_write_hpic(0x10); - dsp_delay(); -#endif - dsp_wait_hrdy(); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16; -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); - - /* dsp_wait_hrdy(); - dsp_delay(); */ -#endif - val |= dsp_read_hpic_lo_hword(DSP_HPID2); -#if !defined(CONFIG_NETTA_6412) - dsp_delay(); -#endif - return val; -} - -static inline void c62_read(u32 addr, u32 *buffer, int numdata) -{ - int i; - - if (numdata <= 0) - return; - - for (i = 0; i < numdata; i++) { - *buffer++ = c62_read_word(addr); - addr += 4; - } -} - -static inline u32 c62_checksum(u32 addr, int numdata) -{ - int i; - u32 chksum; - - chksum = 0; - for (i = 0; i < numdata; i++) { - chksum += c62_read_word(addr); - addr += 4; - } - - return chksum; -} - -static inline void c62_write(u32 addr, const u32 *buffer, int numdata) -{ - int i; - - if (numdata <= 0) - return; - - for (i = 0; i < numdata; i++) { - c62_write_word(addr, *buffer++); - addr += 4; - } -} - -static inline int c62_write_word_validated(u32 addr, u32 val) -{ - c62_write_word(addr, val); - return c62_read_word(addr) == val ? 0 : -1; -} - -static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata) -{ - int i, r; - - if (numdata <= 0) - return 0; - - for (i = 0; i < numdata; i++) { - r = c62_write_word_validated(addr, *buffer++); - if (r < 0) - return r; - addr += 4; - } - return 0; -} - -#if defined(CONFIG_NETTA_6412) - -#define DRAM_REGS_BASE 0x1800000 - -#define GBLCTL DRAM_REGS_BASE -#define CECTL1 (DRAM_REGS_BASE + 0x4) -#define CECTL0 (DRAM_REGS_BASE + 0x8) -#define CECTL2 (DRAM_REGS_BASE + 0x10) -#define CECTL3 (DRAM_REGS_BASE + 0x14) -#define SDCTL (DRAM_REGS_BASE + 0x18) -#define SDTIM (DRAM_REGS_BASE + 0x1C) -#define SDEXT (DRAM_REGS_BASE + 0x20) -#define SESEC1 (DRAM_REGS_BASE + 0x44) -#define SESEC0 (DRAM_REGS_BASE + 0x48) -#define SESEC2 (DRAM_REGS_BASE + 0x50) -#define SESEC3 (DRAM_REGS_BASE + 0x54) - -#define MAR128 0x1848200 -#define MAR129 0x1848204 - -void dsp_dram_initialize(void) -{ - c62_write_word(GBLCTL, 0x120E4); - c62_write_word(CECTL1, 0x18); - c62_write_word(CECTL0, 0xD0); - c62_write_word(CECTL2, 0x18); - c62_write_word(CECTL3, 0x18); - c62_write_word(SDCTL, 0x47115000); - c62_write_word(SDTIM, 1536); - c62_write_word(SDEXT, 0x534A9); -#if 0 - c62_write_word(SESEC1, 0); - c62_write_word(SESEC0, 0); - c62_write_word(SESEC2, 0); - c62_write_word(SESEC3, 0); -#endif - c62_write_word(MAR128, 1); - c62_write_word(MAR129, 0); -} - -#endif - -static inline void dsp_init_hpic(void) -{ - int i; - volatile u16 *p; -#if defined(CONFIG_NETTA_6412) - dsp_go_fast(); -#else - dsp_go_slow(); -#endif - i = 0; -#if defined(CONFIG_NETTA_6412) - while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) { -#else - while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) { -#endif - dsp_delay(); - i++; - } - - if (i == 1000) - printf("HRDY stuck\n"); - - dsp_delay(); - - /* write control register */ - p = (volatile u16 *)DSP_BASE; - p[0] = 0x0000; - dsp_delay(); - p[1] = 0x0000; - dsp_delay(); - -#if !defined(CONFIG_NETTA_6412) - dsp_go_fast(); -#endif -} - -/***********************************************************************************************************/ - -#if !defined(CONFIG_NETTA_6412) - -static const u8 bootstrap_rbin[5084] = { - 0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, - 0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a, - 0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, - 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, - 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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(too short header)\n"); - return -1; - } - - chksum = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] << 8) | (u32)s[ 7]; - rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] << 8) | (u32)s[11]; - s += 12; l -= 12; - - hdr = s; - s += 8 * rangenr; l -= 8 * rangenr; - data = s; - - /* validate bootstrap image */ - h = hdr; s = data; chksum2 = 0; - for (i = 0; i < rangenr; i++) { - start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; - length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; - h += 8; - - /* too short */ - if (l < length) { - printf("bootstrap image corrupted. (too short data)\n"); - return -1; - } - l -= length; - - j = (int)length / 4; - while (j-- > 0) { - chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] << 8) | (u32)s[3]; - s += 4; - } - } - - /* checksum must match */ - if (chksum != chksum2) { - printf("bootstrap image corrupted. (checksum error)\n"); - return -1; - } - - /* nothing must be left */ - if (l != 0) { - printf("bootstrap image corrupted. (garbage at the end)\n"); - return -1; - } - - /* write the image */ - h = hdr; - s = data; - for (i = 0; i < rangenr; i++) { - start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; - length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; - h += 8; - c62_write(start, (u32 *)s, length / 4); - s += length; - } - - /* and now validate checksum */ - h = hdr; - s = data; - chksum2 = 0; - for (i = 0; i < rangenr; i++) { - start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3]; - length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7]; - h += 8; - chksum2 += c62_checksum(start, length / 4); - s += length; - } - - /* checksum must match */ - if (chksum != chksum2) { - printf("bootstrap in DSP memory is corrupted\n"); - return -1; - } - - return 0; -} - -struct host_init { - u32 master_mode; - struct { - u8 port_id; - u8 slot_id; - } ch_serial_map[32]; - u32 clk_divider[2]; - /* pll */ - u32 initmode; - u32 pllm; - u32 div[4]; - u32 oscdiv1; - u32 unused[10]; -}; - -const struct host_init hi_default = { - .master_mode = -#if !defined(CONFIG_NETTA_ISDN) - -1, -#else - 0, -#endif - - .ch_serial_map = { - [ 0] = { .port_id = 2, .slot_id = 16 }, - [ 1] = { .port_id = 2, .slot_id = 17 }, - [ 2] = { .port_id = 2, .slot_id = 18 }, - [ 3] = { .port_id = 2, .slot_id = 19 }, - [ 4] = { .port_id = 2, .slot_id = 20 }, - [ 5] = { .port_id = 2, .slot_id = 21 }, - [ 6] = { .port_id = 2, .slot_id = 22 }, - [ 7] = { .port_id = 2, .slot_id = 23 }, - [ 8] = { .port_id = 2, .slot_id = 24 }, - [ 9] = { .port_id = 2, .slot_id = 25 }, - [10] = { .port_id = 2, .slot_id = 26 }, - [11] = { .port_id = 2, .slot_id = 27 }, - [12] = { .port_id = 2, .slot_id = 28 }, - [13] = { .port_id = 2, .slot_id = 29 }, - [14] = { .port_id = 2, .slot_id = 30 }, - [15] = { .port_id = 2, .slot_id = 31 }, - }, - - /* - dsp_clk(xin, pllm) = xin * pllm - serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1) - */ - - .clk_divider = { - [0] = 47, /* must be 2048Hz */ - [1] = 47, - }, - - .initmode = 1, - .pllm = -#if !defined(CONFIG_NETTA_ISDN) - 8, /* for =~ 25MHz 8 */ -#else - 4, -#endif - .div = { - [0] = 0x8000, - [1] = 0x8000, /* for =~ 25MHz 0x8000 */ - [2] = 0x8001, /* for =~ 25MHz 0x8001 */ - [3] = 0x8001, /* for =~ 25MHz 0x8001 */ - }, - - .oscdiv1 = 0, -}; - -static void hi_write(const struct host_init *hi) -{ - u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)]; - u32 *s; - u32 chksum; - int i; - - memset(hi_buf, 0, sizeof(hi_buf)); - - s = hi_buf; - s++; - *s++ = hi->master_mode; - for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++) - *s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) | - ((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id; - - for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++) - *s++ = hi->clk_divider[i]; - - *s++ = hi->initmode; - *s++ = hi->pllm; - for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++) - *s++ = hi->div[i]; - *s++ = hi->oscdiv1; - - chksum = 0; - for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++) - chksum += hi_buf[i]; - hi_buf[0] = -chksum; - - c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0])); -} - -static void run_bootstrap(void) -{ - dsp_go_slow(); - - hi_write(&hi_default); - - /* signal interrupt */ - dsp_write_hpic(0x0002); - dsp_delay(); - - dsp_go_fast(); -} - -#endif - -/***********************************************************************************************************/ - -int board_post_dsp(int flags) -{ - u32 ramS, ramE; - u32 data, data2; - int i, j, k; -#if !defined(CONFIG_NETTA_6412) - int r; -#endif - dsp_reset(); - dsp_init_hpic(); -#if !defined(CONFIG_NETTA_6412) - dsp_go_slow(); -#endif - data = 0x11223344; - dsp_write_hpic_word(DSP_HPIA, data); - data2 = dsp_read_hpic_word(DSP_HPIA); - if (data2 != 0x11223344) { - printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2); - goto err; - } - - data = 0xFFEEDDCC; - dsp_write_hpic_word(DSP_HPIA, data); - data2 = dsp_read_hpic_word(DSP_HPIA); - if (data2 != 0xFFEEDDCC) { - printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2); - goto err; - } -#if defined(CONFIG_NETTA_6412) - dsp_dram_initialize(); -#else - r = load_bootstrap(); - if (r < 0) { - printf("BOOTSTRAP: ** ERROR ** failed to load\n"); - goto err; - } - - run_bootstrap(); - - dsp_go_fast(); -#endif - printf(" "); - - /* test RAMs */ - for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) { - - ramS = ranges[k].start; - ramE = ranges[k].start + ranges[k].size; - - for (j = 0; j < 3; j++) { - - printf("\b\b\b\bR%d.%d", k, j); - - for (i = ramS; i < ramE; i += 4) { - - data = 0; - switch (j) { - case 0: data = 0xAA55AA55; break; - case 1: data = 0x55AA55AA; break; - case 2: data = (u32)i; break; - } - - c62_write_word(i, data); - data2 = c62_read_word(i); - if (data != data2) { - printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2); - goto err; - } - } - } - } - - printf("\b\b\b\b \b\b\b\bOK\n"); -#if !defined(CONFIG_NETTA_6412) - /* XXX assume that this works */ - load_bootstrap(); - run_bootstrap(); - dsp_go_fast(); -#endif - return 0; - -err: - return -1; -} - -int board_dsp_reset(void) -{ -#if !defined(CONFIG_NETTA_6412) - int r; -#endif - dsp_reset(); - dsp_init_hpic(); -#if defined(CONFIG_NETTA_6412) - dsp_dram_initialize(); -#else - dsp_go_slow(); - r = load_bootstrap(); - if (r < 0) - return r; - - run_bootstrap(); - dsp_go_fast(); -#endif - return 0; -} diff --git a/board/netta/flash.c b/board/netta/flash.c deleted file mode 100644 index ca3e061..0000000 --- a/board/netta/flash.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_byte(flash_info_t * info, ulong dest, uchar data); -static void flash_get_offsets(ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); - -#ifdef CFG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[0]); -#endif - - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_MX: - printf("MXIC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - short i; - uchar mid; - uchar pid; - vu_char *caddr = (vu_char *) addr; - ulong base = (ulong) addr; - - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - mid = caddr[0]; - switch (mid) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (MX_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_MX; - break; - case (STM_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - pid = caddr[1]; /* device ID */ - switch (pid) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - - case (STM_ID_M29W040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf(" "); - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *) info->start[0]; - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0xF0; - - udelay(20000); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *) (info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_char *) (info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (vu_char *) info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte(flash_info_t * info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/netta/netta.c b/board/netta/netta.c deleted file mode 100644 index 9194bfb..0000000 --- a/board/netta/netta.c +++ /dev/null @@ -1,600 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#include -#include - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include -#endif - -int fec8xx_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Intracom NETTA" -#if defined(CONFIG_NETTA_ISDN) - " with ISDN support" -#endif -#if defined(CONFIG_NETTA_6412) - " (DSP:TI6412)" -#else - " (DSP:TI6711)" -#endif - "\n" - ); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define A10_AAAA 0x00000000 -#define A10_AAA0 0x00200000 -#define A10_AAA1 0x00300000 -#define A10_000A 0x00800000 -#define A10_0000 0x00A00000 -#define A10_0001 0x00B00000 -#define A10_111A 0x00C00000 -#define A10_1110 0x00E00000 -#define A10_1111 0x00F00000 - -#define RAS_0000 0x00000000 -#define RAS_0001 0x00040000 -#define RAS_1110 0x00080000 -#define RAS_1111 0x000C0000 - -#define CAS_0000 0x00000000 -#define CAS_0001 0x00010000 -#define CAS_1110 0x00020000 -#define CAS_1111 0x00030000 - -#define WE_0000 0x00000000 -#define WE_0001 0x00004000 -#define WE_1110 0x00008000 -#define WE_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 8 */ -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -long int initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - - memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - { - u32 d1, d2; - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - -#if 0 - printf("check 0\n"); - check_ram(( 0 << 20), (2 << 20)); - printf("check 16\n"); - check_ram((16 << 20), (2 << 20)); - printf("check 32\n"); - check_ram((32 << 20), (2 << 20)); - printf("check 48\n"); - check_ram((48 << 20), (2 << 20)); -#endif - - if (size == 0) { - printf("SIZE is zero: LOOP on 0\n"); - for (;;) { - *(volatile u32 *)0 = 0; - (void)*(volatile u32 *)0; - } - } - - return size; -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r(void) -{ - return(0); -} - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); - if (v == 0xFFFF) - continue; - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); - udelay(10000); - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, - PHY_BMCR_RESET | PHY_BMCR_AUTON); - udelay(10000); - } -} - -extern int board_dsp_reset(void); - -int last_stage_init(void) -{ - int r; - - reset_phys(); - r = board_dsp_reset(); - if (r < 0) - printf("*** WARNING *** DSP reset failed (run diagnostics)\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK (_BWR(3) | _BWR(7, 9) | _BW(11)) -#define PA_GP_OUTMASK (_BW(6) | _BW(10) | _BWR(12, 15)) -#define PA_SP_MASK (_BWR(0, 2) | _BWR(4, 5)) -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(13) | _BWR(14, 15)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK (_B(28) | _B(31)) -#define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30)) -#define PB_SP_MASK (_BR(22, 25)) -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31)) -#define PB_SP_DIRVAL 0 - -#define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15)) -#define PC_GP_OUTMASK (_BW(6) | _BW(12)) -#define PC_SP_MASK (_BW(4) | _BW(8)) -#define PC_SOVAL 0 -#define PC_INTVAL _BW(7) -#define PC_GP_OUTVAL (_BW(6) | _BW(12)) -#define PC_SP_DIRVAL 0 - -#define PD_GP_INMASK 0 -#define PD_GP_OUTMASK _BWR(3, 15) -#define PD_SP_MASK 0 - -#if defined(CONFIG_NETTA_6412) - -#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15)) - -#else - -#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11)) - -#endif - -#define PD_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* CS1: NAND chip select */ - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ; - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); -#if !defined(CONFIG_NETTA_6412) - /* CS2: DSP */ - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); - memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); -#else - /* CS6: DSP */ - memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2); - memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); -#endif - /* CS4: External register chip select */ - memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); - memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); - - /* CS5: dummy for accurate delay */ - memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2); - memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); - - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - ioport->iop_pddat = PD_GP_OUTVAL; - ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; - ioport->iop_pdpar = PD_SP_MASK; - - /* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */ - - return 0; -} - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - -#include - -extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - unsigned long totlen = nand_probe(CFG_NAND_BASE); - - printf ("%4lu MB\n", totlen >> 20); -} -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) - -int pcmcia_init(void) -{ - return 0; -} - -#endif - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - return 0; /* No hotkeys supported */ -} -#endif - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds deleted file mode 100644 index 9f2901c..0000000 --- a/board/netta/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug deleted file mode 100644 index 004e7fd..0000000 --- a/board/netta/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/netta2/Makefile b/board/netta2/Makefile deleted file mode 100644 index d457020..0000000 --- a/board/netta2/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/netta2/config.mk b/board/netta2/config.mk deleted file mode 100644 index 8497ebc..0000000 --- a/board/netta2/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# netVia Boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/netta2/flash.c b/board/netta2/flash.c deleted file mode 100644 index a1c87f5..0000000 --- a/board/netta2/flash.c +++ /dev/null @@ -1,506 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_byte(flash_info_t * info, ulong dest, uchar data); -static void flash_get_offsets(ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); - -#ifdef CFG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_MX: - printf("MXIC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - short i; - uchar mid; - uchar pid; - vu_char *caddr = (vu_char *) addr; - ulong base = (ulong) addr; - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - mid = caddr[0]; - switch (mid) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (MX_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_MX; - break; - case (STM_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - pid = caddr[1]; /* device ID */ - switch (pid) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - - case (STM_ID_M29W040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf(" "); - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *) info->start[0]; - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0xF0; - - udelay(20000); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *) (info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_char *) (info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_char *) info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte(flash_info_t * info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c deleted file mode 100644 index c9b4051..0000000 --- a/board/netta2/netta2.c +++ /dev/null @@ -1,670 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#include -#include - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include -#endif - -int fec8xx_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define GPL0_AAAA 0x00000000 -#define GPL0_AAA0 0x00200000 -#define GPL0_AAA1 0x00300000 -#define GPL0_000A 0x00800000 -#define GPL0_0000 0x00A00000 -#define GPL0_0001 0x00B00000 -#define GPL0_111A 0x00C00000 -#define GPL0_1110 0x00E00000 -#define GPL0_1111 0x00F00000 - -#define GPL1_0000 0x00000000 -#define GPL1_0001 0x00040000 -#define GPL1_1110 0x00080000 -#define GPL1_1111 0x000C0000 - -#define GPL2_0000 0x00000000 -#define GPL2_0001 0x00010000 -#define GPL2_1110 0x00020000 -#define GPL2_1111 0x00030000 - -#define GPL3_0000 0x00000000 -#define GPL3_0001 0x00004000 -#define GPL3_1110 0x00008000 -#define GPL3_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -#define A10_AAAA GPL0_AAAA -#define A10_AAA0 GPL0_AAA0 -#define A10_AAA1 GPL0_AAA1 -#define A10_000A GPL0_000A -#define A10_0000 GPL0_0000 -#define A10_0001 GPL0_0001 -#define A10_111A GPL0_111A -#define A10_1110 GPL0_1110 -#define A10_1111 GPL0_1111 - -#define RAS_0000 GPL1_0000 -#define RAS_0001 GPL1_0001 -#define RAS_1110 GPL1_1110 -#define RAS_1111 GPL1_1111 - -#define CAS_0000 GPL2_0000 -#define CAS_0001 GPL2_0001 -#define CAS_1110 GPL2_1110 -#define CAS_1111 GPL2_1111 - -#define WE_0000 GPL3_0000 -#define WE_0001 GPL3_0001 -#define WE_1110 GPL3_1110 -#define WE_1111 GPL3_1111 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -#if CONFIG_NETTA2_VERSION == 2 -static const uint nandcs_table[0x40] = { - /* RSS */ - CS_1000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1110 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111, - CS_0000 | GPL4_0001 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ - - /* RBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_1000 | GPL4_1111 | GPL5_1110 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0001 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, - - /* WBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 , - CS_0001 | LAST, -}; -#endif - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 8 */ -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -long int initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - - memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - { - u32 d1, d2; - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - hang(); - } - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - - if (size == 0) { - printf("SIZE is zero: LOOP on 0\n"); - for (;;) { - *(volatile u32 *)0 = 0; - (void)*(volatile u32 *)0; - } - } - - return size; -} - -/* ------------------------------------------------------------------------- */ - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - udelay(10000); - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); - if (v == 0xFFFF) - continue; - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); - udelay(10000); - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, - PHY_BMCR_RESET | PHY_BMCR_AUTON); - udelay(10000); - } -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK 0 -#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15)) -#define PA_SP_MASK 0 -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK _B(28) -#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_MASK (_BR(22, 25)) -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30)) -#define PB_SP_DIRVAL 0 - -#if CONFIG_NETTA2_VERSION == 1 -#define PC_GP_INMASK _BW(12) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15)) -#elif CONFIG_NETTA2_VERSION == 2 -#define PC_GP_INMASK (_BW(13) | _BW(15)) -#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12)) -#endif -#define PC_SP_MASK 0 -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL (_BW(10) | _BW(11)) -#define PC_SP_DIRVAL 0 - -#if CONFIG_NETTA2_VERSION == 1 -#define PE_GP_INMASK _B(31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28)) -#elif CONFIG_NETTA2_VERSION == 2 -#define PE_GP_INMASK _BR(28, 31) -#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27)) -#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27)) -#endif -#define PE_SP_MASK 0 -#define PE_ODR_VAL 0 -#define PE_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* NAND chip select */ -#if CONFIG_NETTA2_VERSION == 1 - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); -#elif CONFIG_NETTA2_VERSION == 2 - upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA); - memctl->memc_mamr = 0; /* all clear */ -#endif - - /* DSP chip select */ - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); - memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); - -#if CONFIG_NETTA2_VERSION == 1 - memctl->memc_br4 &= ~BR_V; -#endif - memctl->memc_br5 &= ~BR_V; - memctl->memc_br6 &= ~BR_V; - memctl->memc_br7 &= ~BR_V; - - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - cpm->cp_pedat = PE_GP_OUTVAL; - cpm->cp_peodr = PE_ODR_VAL; - cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; - cpm->cp_pepar = PE_SP_MASK; - - return 0; -} - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - -#include - -extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - unsigned long totlen; - - totlen = nand_probe(CFG_NAND_BASE); - printf ("%4lu MB\n", totlen >> 20); -} -#endif - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif - -#ifdef CONFIG_SHOW_ACTIVITY - -/* called from timer interrupt every 1/CFG_HZ sec */ -void board_show_activity(ulong timestamp) -{ -} - -/* called when looping */ -void show_activity(int arg) -{ -} - -#endif - -#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - /* printf("overwrite_console called\n"); */ - return 0; -} -#endif - -extern int drv_phone_init(void); -extern int drv_phone_use_me(void); -extern int drv_phone_is_idle(void); - -int misc_init_r(void) -{ - return 0; -} - -int last_stage_init(void) -{ -#if CONFIG_NETTA2_VERSION == 2 - int i; -#endif - -#if CONFIG_NETTA2_VERSION == 2 - /* assert peripheral reset */ - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); - for (i = 0; i < 10; i++) - udelay(1000); - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |= _BW(12); -#endif - reset_phys(); - - return 0; -} diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds deleted file mode 100644 index 9f2901c..0000000 --- a/board/netta2/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug deleted file mode 100644 index 004e7fd..0000000 --- a/board/netta2/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/netvia/Makefile b/board/netvia/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/netvia/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/netvia/config.mk b/board/netvia/config.mk deleted file mode 100644 index 9dddaad..0000000 --- a/board/netvia/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# netVia Boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/netvia/flash.c b/board/netvia/flash.c deleted file mode 100644 index d31f770..0000000 --- a/board/netvia/flash.c +++ /dev/null @@ -1,511 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_byte(flash_info_t * info, ulong dest, uchar data); -static void flash_get_offsets(ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); - -#ifdef CFG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[0]); -#endif - - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_MX: - printf("MXIC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - short i; - uchar mid; - uchar pid; - vu_char *caddr = (vu_char *) addr; - ulong base = (ulong) addr; - - - /* Write auto select command: read Manufacturer ID */ - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - mid = caddr[0]; - switch (mid) { - case (AMD_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_FUJ; - break; - case (MX_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_MX; - break; - case (STM_MANUFACT & 0xFF): - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - pid = caddr[1]; /* device ID */ - switch (pid) { - case (AMD_ID_LV400T & 0xFF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV400B & 0xFF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 512 kB */ - - case (AMD_ID_LV800T & 0xFF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800B & 0xFF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV160T & 0xFF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160B & 0xFF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - - case (STM_ID_M29W040B & 0xFF): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; - -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & 0xFF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV320B & 0xFF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf(" "); - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection: D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (vu_char *) info->start[0]; - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0xF0; - - udelay(20000); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *) (info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (vu_char *) (info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (vu_char *) info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr++, *src++)) != 0) { - return (rc); - } - --cnt; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte(flash_info_t * info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *((vu_char *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c deleted file mode 100644 index fb7f770..0000000 --- a/board/netvia/netvia.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetVia board - */ - -#include -#include "mpc8xx.h" - -/****************************************************************/ - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 -/* last value written to the external register; we cannot read back */ -unsigned int last_er_val; -#endif - -/****************************************************************/ - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define A10_AAAA 0x00000000 -#define A10_AAA0 0x00200000 -#define A10_AAA1 0x00300000 -#define A10_000A 0x00800000 -#define A10_0000 0x00A00000 -#define A10_0001 0x00B00000 -#define A10_111A 0x00C00000 -#define A10_1110 0x00E00000 -#define A10_1111 0x00F00000 - -#define RAS_0000 0x00000000 -#define RAS_0001 0x00040000 -#define RAS_1110 0x00080000 -#define RAS_1111 0x000C0000 - -#define CAS_0000 0x00000000 -#define CAS_0001 0x00010000 -#define CAS_1110 0x00020000 -#define CAS_1111 0x00030000 - -#define WE_0000 0x00000000 -#define WE_0001 0x00004000 -#define WE_1110 0x00008000 -#define WE_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -const uint sdram_table[0x40] = { - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | LOOP, - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LOOP, - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LAST, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, - - /* REG */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1110 | AMX_MAR, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | TODT | LAST, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ETX ID string (ETX_xxx...) - * - * Return 1 always. - */ - -int checkboard(void) -{ -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 - printf ("NETVIA v1\n"); -#else - printf ("NETVIA v2+\n"); -#endif - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -#define MAR_SDRAM_INIT 0x000000C8LU - -#define MCR_OP(x) ((unsigned long)((x) & 3) << (31-1)) -#define MCR_OP_MASK MCR_OP(3) - -#define MCR_UM(x) ((unsigned long)((x) & 1) << (31 - 8)) -#define MCR_UM_MASK MCR_UM(1) -#define MCR_UM_UPMA MCR_UM(0) -#define MCR_UM_UPMB MCR_UM(1) - -#define MCR_MB(x) ((unsigned long)((x) & 7) << (31 - 18)) -#define MCR_MB_MASK MCR_MB(7) -#define MCR_MB_CS(x) MCR_MB(x) - -#define MCR_MCLF(x) ((unsigned long)((x) & 15) << (31 - 23)) -#define MCR_MCLF_MASK MCR_MCLF(15) - -long int initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - - upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = CFG_MPTPR_1BK_8K; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - - memctl->memc_mamr = CFG_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0) */ - udelay(1); - memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E); /* exception program (write mar) */ - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay(1000); - - memctl->memc_mamr = CFG_MAMR_9COL; - - size = SDRAM_MAX_SIZE; - - udelay(10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r(void) -{ -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - last_er_val = 0xffffffff; -#endif - return(0); -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK 0 -#define PA_GP_OUTMASK (_BW(5) | _BWR(14, 15)) -#define PA_SP_MASK (_BW(4) | _BWR(6, 13)) -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL _BW(5) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK _B(28) -#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 31)) -#define PB_SP_MASK _BR(22, 25) -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31)) -#define PB_SP_DIRVAL 0 - -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 - -#define PC_GP_INMASK (_BWR(5, 7) | _BWR(9, 10) | _BW(13)) -#define PC_GP_OUTMASK _BW(12) -#define PC_SP_MASK (_BW(4) | _BW(8)) -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL 0 -#define PC_SP_DIRVAL 0 - -#define PD_GP_INMASK 0 -#define PD_GP_OUTMASK _BWR(3, 15) -#define PD_SP_MASK 0 -#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15)) -#define PD_SP_DIRVAL 0 - -#elif CONFIG_NETVIA_VERSION >= 2 - -#define PC_GP_INMASK (_BW(5) | _BW(7) | _BWR(9, 11) | _BWR(13, 15)) -#define PC_GP_OUTMASK (_BW(6) | _BW(12)) -#define PC_SP_MASK (_BW(4) | _BW(8)) -#define PC_SOVAL 0 -#define PC_INTVAL _BW(7) -#define PC_GP_OUTVAL (_BW(6) | _BW(12)) -#define PC_SP_DIRVAL 0 - -#define PD_GP_INMASK 0 -#define PD_GP_OUTMASK _BWR(3, 15) -#define PD_SP_MASK 0 -#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(9) | _BW(11)) -#define PD_SP_DIRVAL 0 - -#else -#error Unknown NETVIA board version. -#endif - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* DSP0 chip select */ - memctl->memc_or4 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); - memctl->memc_br4 = ((DSP0_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); - - /* DSP1 chip select */ - memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); - memctl->memc_br5 = ((DSP1_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); - - /* FPGA chip select */ - memctl->memc_or6 = ((0xFFFFFFFFLU & ~(FPGA_SIZE - 1)) | OR_BI | OR_SCY_1_CLK); - memctl->memc_br6 = ((FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - /* NAND chip select */ - memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); - memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); - - /* kill this chip select */ - memctl->memc_br2 &= ~BR_V; /* invalid */ - - /* external reg chip select */ - memctl->memc_or7 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); - memctl->memc_br7 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); -#endif - - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - ioport->iop_pddat = PD_GP_OUTVAL; - ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; - ioport->iop_pdpar = PD_SP_MASK; - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - /* external register init */ - *(volatile uint *)ER_BASE = 0xFFFFFFFF; -#endif - - return 0; -} - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - -#include - -extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - unsigned long totlen = nand_probe(CFG_NAND_BASE); - - printf ("%4lu MB\n", totlen >> 20); -} -#endif diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds deleted file mode 100644 index dc69db6..0000000 --- a/board/netvia/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug deleted file mode 100644 index 96569bf..0000000 --- a/board/netvia/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/ns9750dev/Makefile b/board/ns9750dev/Makefile deleted file mode 100644 index fb4333c..0000000 --- a/board/ns9750dev/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := ns9750dev.o flash.o led.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/ns9750dev/config.mk b/board/ns9750dev/config.mk deleted file mode 100644 index 6a22cee..0000000 --- a/board/ns9750dev/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -####################################################################### -# -# Copyright (C) 2004 by FS Forth-Systeme GmbH. -# Markus Pietrek -# -# @TODO -# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000 -# optionally with a ramdisk at 0080'0000 -# -# we load ourself to 0078'0000 -# -# download area is 0060'0000 -# - - -TEXT_BASE = 0x00780000 diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c deleted file mode 100644 index e7d6515..0000000 --- a/board/ns9750dev/flash.c +++ /dev/null @@ -1,477 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - OrgDef *pOrgDef; - - pOrgDef = OrgIntel_28F256L18T; - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - flash_unprotect_sectors (addr); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/ns9750dev/led.c b/board/ns9750dev/led.c deleted file mode 100644 index b85c869..0000000 --- a/board/ns9750dev/led.c +++ /dev/null @@ -1,46 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: led.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @Descr: Defines helper functions for toggeling LEDs - * @Usage: - * @References: [1] - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ***********************************************************************/ - -#ifdef CONFIG_STATUS_LED - -#include - -static inline void __led_init( led_id_t mask, int state ) -{ - XXXX; -} - -static inline void __led_toggle( led_id_t mask ) -{ -} - -static inline void __led_set( led_id_t mask, int state ) -{ -} - -#endif /* CONFIG_STATUS_LED */ diff --git a/board/ns9750dev/lowlevel_init.S b/board/ns9750dev/lowlevel_init.S deleted file mode 100644 index 3a09786..0000000 --- a/board/ns9750dev/lowlevel_init.S +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Modified for the NS9750 DevBoard by - * (C) Copyright 2004 by FS Forth-Systeme GmbH. - * Markus Pietrek - * @References: [1] NS9750 Hardware Reference/December 2003 - * [2] ns9750_a.cmd from MAJIC configuration - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_NS9750DEV) -# ifndef CONFIG_SKIP_LOWLEVEL_INIT -# include <./ns9750_sys.h> -# include <./ns9750_mem.h> -# endif -#endif - -/*********************************************************************** - * @Function: write_register_block - * @Return: nothing - * @Descr: Copies the register block of register_offset:register value to - * the registers at base r0. The block is assumed to start in RAM at r1 - * and end at r2. The linked RAM base address of U-Boot is assumed to be - * in r5 while the ROM base address we are running from is r6 - * Uses r3 and r4 as tempory registers - ***********************************************************************/ - -.macro write_register_block - @@ map the addresses to high memory - sub r1, r1, r5 - add r1, r1, r6 - sub r2, r2, r5 - add r2, r2, r6 - - @@ copy all -1: - @@ Write register/value pair starting at [r1] to register base r0 - ldr r3, [r1], #4 - ldr r4, [r1], #4 - str r4, [r0,r3] - cmp r1, r2 - blt 1b -.endm - -_TEXT_BASE: - .word TEXT_BASE @ sdram load addr from config.mk -_PHYS_FLASH: - .word PHYS_FLASH_1 @ real flash address (without mirroring) -_CAS_LATENCY: - .word 0x00022000 @ for CAS2 latency - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -.globl lowlevel_init -lowlevel_init: - - /* U-Boot may be linked to RAM at 0x780000. But this code will run in - flash from 0x0. But in order to enable RAM we have to disable the - mirror bit, therefore we have to jump to our real flash address - beginning at PHYS_FLASH_1 (CS4 Base). Therefore, - _run_at_real_flash_address may be 0x500003b0 while be linked to - 0x7803b0. So we must modify our linked addresses */ - - @@ branch to high memory address, away from 0x0 - ldr r5, _TEXT_BASE - ldr r6, _PHYS_FLASH - ldr r0, =_run_at_real_flash_address - sub r0, r0, r5 - add r0, r0, r6 - mov pc, r0 - nop @ for pipelining - -_run_at_real_flash_address: - @@ now we are running > PHYS_FLASH_1, safe to enable memory controller - - @@ Write Memory Configuration Registers - - ldr r0, _NS9750_MEM_MODULE_BASE - ldr r1, =_MEM_CONFIG_START - ldr r2, =_MEM_CONFIG_END - - write_register_block - - @@ Give SDRAM some time to settle - @@ @TODO. According to [2] it should be 2 AHB cycles. Check - - ldr r1, =0x50 -_sdram_settle: - subs r1, r1, #1 - bne _sdram_settle - -_enable_mappings: - @@ Enable SDRAM Mode - - ldr r1, =_MEM_MODE_START - ldr r2, =_MEM_MODE_END - - write_register_block - - ldr r3, _CAS_LATENCY @ perform one read from SDRAM - ldr r3, [r3] - - @@ Enable SDRAM and memory mappings - - ldr r1, =_MEM_ENABLE_START - ldr r2, =_MEM_ENABLE_END - - write_register_block - - @@ Activate AHB monitor - - ldr r0, =NS9750_SYS_MODULE_BASE - ldr r1, =_AHB_MONITOR_START - ldr r2, =_AHB_MONITOR_END - - write_register_block -_relocate_lr: - /* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to - PHYS_FLASH. */ - mov r1, ip - add r1, r1, r6 - mov ip, r1 - - mov r1, lr - add r1, r1, r6 - mov lr, r1 - - @@ back to arch calling code - mov pc, lr - - .ltorg - -_NS9750_MEM_MODULE_BASE: - .word NS9750_MEM_MODULE_BASE - -_MEM_CONFIG_START: - /* Table of 2 32bit entries. First word is register address offset - relative to NS9750_MEM_MODULE_BASE, second one is value. They are - written in order of appearance */ - - @@ Register values taken from [2] - .word NS9750_MEM_CTRL - .word NS9750_MEM_CTRL_E - - .word NS9750_MEM_DYN_REFRESH - .word (0x6 & NS9750_MEM_DYN_REFRESH_MA) - - .word NS9750_MEM_DYN_READ_CFG - .word (0x1 & NS9750_MEM_DYN_READ_CFG_MA) - - .word NS9750_MEM_DYN_TRP - .word (0x1 & NS9750_MEM_DYN_TRP_MA) - - .word NS9750_MEM_DYN_TRAS - .word (0x4 & NS9750_MEM_DYN_TRAS_MA) - - .word NS9750_MEM_DYN_TAPR - .word (0x1 & NS9750_MEM_DYN_TRAS_MA) - - .word NS9750_MEM_DYN_TDAL - .word (0x5 & NS9750_MEM_DYN_TDAL_MA) - - .word NS9750_MEM_DYN_TWR - .word (0x1 & NS9750_MEM_DYN_TWR_MA) - - .word NS9750_MEM_DYN_TRC - .word (0x6 & NS9750_MEM_DYN_TRC_MA) - - .word NS9750_MEM_DYN_TRFC - .word (0x6 & NS9750_MEM_DYN_TRFC_MA) - - .word NS9750_MEM_DYN_TRRD - .word (0x1 & NS9750_MEM_DYN_TRRD_MA) - - .word NS9750_MEM_DYN_TMRD - .word (0x1 & NS9750_MEM_DYN_TMRD_MA) - - @@ CS 4 - .word NS9750_MEM_DYN_CFG(0) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(0) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - @@ CS 5 - .word NS9750_MEM_DYN_CFG(1) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(1) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - @@ CS 6 - .word NS9750_MEM_DYN_CFG(2) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(2) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - @@ CS 7 - .word NS9750_MEM_DYN_CFG(3) - .word (NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - .word NS9750_MEM_DYN_RAS_CAS(3) - .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \ - (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA)) - - .word NS9750_MEM_DYN_CTRL - .word (NS9750_MEM_DYN_CTRL_I_PALL | \ - NS9750_MEM_DYN_CTRL_SR | \ - NS9750_MEM_DYN_CTRL_CE ) - - .word NS9750_MEM_DYN_REFRESH - .word (0x1 & NS9750_MEM_DYN_REFRESH_MA) - @@ No further register settings after refresh -_MEM_CONFIG_END: - -_MEM_MODE_START: - .word NS9750_MEM_DYN_REFRESH - .word (0x30 & NS9750_MEM_DYN_REFRESH_MA) - - .word NS9750_MEM_DYN_CTRL - .word (NS9750_MEM_DYN_CTRL_I_MODE | \ - NS9750_MEM_DYN_CTRL_SR | \ - NS9750_MEM_DYN_CTRL_CE ) -_MEM_MODE_END: - -_MEM_ENABLE_START: - .word NS9750_MEM_DYN_CTRL - .word (NS9750_MEM_DYN_CTRL_I_NORMAL | \ - NS9750_MEM_DYN_CTRL_SR | \ - NS9750_MEM_DYN_CTRL_CE ) - - @@ CS 4 - .word NS9750_MEM_DYN_CFG(0) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - @@ CS 5 - .word NS9750_MEM_DYN_CFG(1) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - @@ CS 6 - .word NS9750_MEM_DYN_CFG(2) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) - - @@ CS 7 - .word NS9750_MEM_DYN_CFG(3) - .word (NS9750_MEM_DYN_CFG_BDMC | \ - NS9750_MEM_DYN_CFG_AM | \ - (0x280 & NS9750_MEM_DYN_CFG_AM_MA)) -_MEM_ENABLE_END: - -_AHB_MONITOR_START: - .word NS9750_SYS_AHB_TIMEOUT - .word 0x01000100 @ @TODO not calculated yet - - .word NS9750_SYS_AHB_MON - .word (NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \ - NS9750_SYS_AHB_MON_BATC_GEN_IRQ) -_AHB_MONITOR_END: - -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c deleted file mode 100644 index ea00d5a..0000000 --- a/board/ns9750dev/ns9750dev.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * Markus Pietrek - * derived from omap1610innovator.c - * @References: [1] NS9750 Hardware Reference/December 2003 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined(CONFIG_NS9750DEV) -# include <./configs/ns9750dev.h> -# include <./ns9750_bbus.h> -#endif - -void flash__init( void ); -void ether__init( void ); - -static inline void delay( unsigned long loops ) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - - -/*********************************************************************** - * @Function: board_init - * @Return: 0 - * @Descr: Enables BBUS modules and other devices - ***********************************************************************/ - -int board_init( void ) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Active BBUS modules */ - *get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0; - -#warning Please register your machine at http://www.arm.linux.org.uk/developer/machines/?action=new - /* arch number of OMAP 1510-Board */ - /* to be changed for OMAP 1610 Board */ - gd->bd->bi_arch_number = 234; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - -/* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable(); - - flash__init(); - ether__init(); - return 0; -} - - -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - -#if CONFIG_NR_DRAM_BANKS > 1 - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif - return 0; -} diff --git a/board/ns9750dev/u-boot.lds b/board/ns9750dev/u-boot.lds deleted file mode 100644 index 8ebb651..0000000 --- a/board/ns9750dev/u-boot.lds +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm926ejs/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = . ; - -} diff --git a/board/nx823/Makefile b/board/nx823/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/nx823/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/nx823/config.mk b/board/nx823/config.mk deleted file mode 100644 index 3b3ea1e..0000000 --- a/board/nx823/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Nexus boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/nx823/flash.c b/board/nx823/flash.c deleted file mode 100644 index 581925e..0000000 --- a/board/nx823/flash.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ -extern u_long *my_sernum; /* from nx823.c */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE+monitor_flash_len-1, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A\n"); break; - case FLASH_28F640J3A: - printf ("28F640J3A\n"); break; - case FLASH_28F128J3A: - printf ("28F128J3A\n"); break; - default: printf ("Unknown Chip Type\n"); break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW)0x00AA00AA; - addr[0x2AAA] = (FPW)0x00550055; - addr[0x5555] = (FPW)0x00900090; - - value = addr[0]; - - switch (value) { - case (FPW)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (FPW)INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FPW)INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FPW)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *)(info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW)0x00B000B0; /* suspend erase */ - *addr = (FPW)0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW)0x00FF00FF; /* reset to read mode */ - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* save sernum if needed */ - if (addr >= CFG_FLASH_SN_SECTOR && addr < CFG_FLASH_SN_BASE) - { - u_long dest = CFG_FLASH_SN_BASE; - u_short *sn = (u_short *)my_sernum; - - printf("(saving sernum)"); - for (i=0; i<4; i++) - { - if ((rc = write_data(info, dest, sn[i])) != 0) { - return (rc); - } - dest += port_width; - } - } - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= port_width) { - data = 0; - for (i=0; i 0x800) - { - putc('.'); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i CFG_FLASH_WRITE_TOUT) { - *addr = (FPW)0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW)0x00FF00FF; /* restore read mode */ - - return (0); -} diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c deleted file mode 100644 index 65d45c1..0000000 --- a/board/nx823/nx823.c +++ /dev/null @@ -1,404 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { -#if (MPC8XX_SPEED <= 50000000L) - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07, - 0xFFFFFFFF, - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FE7F434, 0xEFABE834, 0x1FA7D435, - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF -#else - - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800, - 0x1FF7F447, - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF7F434, 0xEFEBE834, 0x1FB7D435, - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ - printf ("Board: Nexus NX823"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size_b1, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Up to 2 Banks of 64Mbit x 2 devices - * Initial builds only have 1 - */ - memctl->memc_mptpr = CFG_MPTPR_1BK_4K; - memctl->memc_mar = 0x00000088; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - udelay (200); - - /* - * Map controller SDRAM bank 1 - */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - /* - * Check Bank 1 Memory Size - * use current column settings - * [9 column SDRAM may also be used in 8 column mode, - * but then only half the real size will be used.] - */ - size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); -/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */ - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b0 > 0) { - /* - * Position Bank 0 immediately above Bank 1 - */ - memctl->memc_or1 = - ((-size_b0) & 0xFFFF0000) | - CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | - BR_V) - + size_b1; - } else { - unsigned long reg; - - /* - * No bank 0 - * - * invalidate bank - */ - memctl->memc_br1 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - } else { /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or1 = - ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | - CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | - BR_V) - + size_b0; - } else { - unsigned long reg; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - } - - udelay (10000); - - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -u_long *my_sernum; - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - char tmp[50]; - u_char *e = gd->bd->bi_enetaddr; - - /* save serial numbre from flash (uniquely programmed) */ - my_sernum = malloc (8); - memcpy (my_sernum, gd->bd->bi_sernum, 8); - - /* save env variables according to sernum */ - sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]); - setenv ("serial#", tmp); - - sprintf (tmp, "%02x:%02x:%02x:%02x:%02x:%02x", e[0], e[1], e[2], e[3], - e[4], e[5]); - setenv ("ethaddr", tmp); - return (0); -} - -void load_sernum_ethaddr (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int i; - bd_t *bd = gd->bd; - - for (i = 0; i < 8; i++) { - bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i); - } - bd->bi_enetaddr[0] = 0x10; - bd->bi_enetaddr[1] = 0x20; - bd->bi_enetaddr[2] = 0x30; - bd->bi_enetaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2]; - bd->bi_enetaddr[4] = bd->bi_sernum[5]; - bd->bi_enetaddr[5] = bd->bi_sernum[6]; -} diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds deleted file mode 100644 index 7099fc4..0000000 --- a/board/nx823/u-boot.lds +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug deleted file mode 100644 index 3165d56..0000000 --- a/board/nx823/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/o2dnt/Makefile b/board/o2dnt/Makefile deleted file mode 100644 index 2eb4366..0000000 --- a/board/o2dnt/Makefile +++ /dev/null @@ -1,47 +0,0 @@ - -# -# (C) Copyright 2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/o2dnt/config.mk b/board/o2dnt/config.mk deleted file mode 100644 index b873376..0000000 --- a/board/o2dnt/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# boot low for 16 MiB boards -TEXT_BASE = 0xFF000000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/o2dnt/flash.c b/board/o2dnt/flash.c deleted file mode 100644 index 037d287..0000000 --- a/board/o2dnt/flash.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * flash_real_protect() routine based on boards/alaska/flash.c - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* Intel-compatible flash commands */ -#define INTEL_ERASE 0x20 -#define INTEL_PROGRAM 0x40 -#define INTEL_CLEAR 0x50 -#define INTEL_LOCKBIT 0x60 -#define INTEL_PROTECT 0x01 -#define INTEL_STATUS 0x70 -#define INTEL_READID 0x90 -#define INTEL_READID 0x90 -#define INTEL_SUSPEND 0xB0 -#define INTEL_CONFIRM 0xD0 -#define INTEL_RESET 0xFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x80 -#define INTEL_OK 0x80 - -typedef unsigned char FLASH_PORT_WIDTH; -typedef volatile unsigned char FLASH_PORT_WIDTHV; -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV -#define FLASH_ID_MASK 0xFF - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); -static int write_data (flash_info_t *info, FPWV *dest, FPW data); /* O2D */ -static void flash_sync_real_protect (flash_info_t * info); -static unsigned char intel_sector_protected (flash_info_t *info, ushort sector); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - extern void flash_preinit(void); - extern void flash_afterinit(ulong); - - flash_preinit(); - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - memset(&flash_info[i], 0, sizeof(flash_info_t)); - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Query flash chip */ - flash_info[0].size = - flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); - size += flash_info[0].size; - - /* get the h/w and s/w protection status in sync */ - flash_sync_real_protect(&flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - - flash_afterinit(size); - return (size ? size : 1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW) INTEL_RESET; /* Intel Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && - info->start[0] <= base && - base <= info->start[0] + info->size - 1) - break; - } - - return (i == CFG_MAX_FLASH_BANKS ? 0 : info); -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - fmt = "28F128J3 (128 Mbit, uniform sectors)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - int i; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW) INTEL_READID; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[0] & 0xff) { - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Strataflash is configurable to 8/16bit Bus, - * but the Query-Structure is Word-orientated */ - if (info->flash_id != FLASH_UNKNOWN) { - switch ((FPW)addr[2]) { - case (FPW)INTEL_ID_28F128J3: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = (ulong)addr + (i * 0x20000); - break; /* => Intel Strataflash 16MB */ - default: - printf("Flash_id != %xd\n", (FPW)addr[2]); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - } - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) - if (info->protect[sect]) - prot++; - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!", - prot); - - printf ("\n"); - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - *addr = (FPW) INTEL_CLEAR; /* clear status register */ - *addr = (FPW) INTEL_ERASE; /* erase setup */ - *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 80us for Intel - let's wait 1 ms */ - udelay (1000); - - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) INTEL_SUSPEND;/* suspend erase */ - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - res = write_data(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, FPWV *dest, FPW data) -{ - FPWV *addr = dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) INTEL_PROGRAM; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) INTEL_RESET; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) INTEL_RESET; /* restore read mode */ - if (flag) - enable_interrupts(); - - return (0); -} - - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - ulong start; - int i; - int rc = 0; - FPWV *addr = (FPWV *) (info->start[sector]); - int flag = disable_interrupts (); - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - start = get_timer (0); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) { - printf ("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf ("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint) addr, (uint) * addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - */ - if (!prot) { - for (i = 0; i < info->sector_count; i++) { - if (info->protect[i]) { - start = get_timer (0); - addr = (FPWV *) (info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - while ((*addr & INTEL_FINISHED) != - INTEL_FINISHED) { - if (get_timer (start) > - CFG_FLASH_UNLOCK_TOUT) { - printf ("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - } - } - } - - if (flag) - enable_interrupts (); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} - - -/* - * This function gets the u-boot flash sector protection status - * (flash_info_t.protect[]) in sync with the sector protection - * status stored in hardware. - */ -static void flash_sync_real_protect (flash_info_t * info) -{ - int i; - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - for (i = 0; i < info->sector_count; ++i) { - info->protect[i] = intel_sector_protected(info, i); - } - break; - default: - /* no h/w protect support */ - break; - } -} - - -/* - * checks if "sector" in bank "info" is protected. Should work on intel - * strata flash chips 28FxxxJ3x in 8-bit mode. - * Returns 1 if sector is protected (or timed-out while trying to read - * protection status), 0 if it is not. - */ -static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) -{ - FPWV *addr; - FPWV *lock_conf_addr; - ulong start; - unsigned char ret; - - /* - * first, wait for the WSM to be finished. The rationale for - * waiting for the WSM to become idle for at most - * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy - * because of: (1) erase, (2) program or (3) lock bit - * configuration. So we just wait for the longest timeout of - * the (1)-(3), i.e. the erase timeout. - */ - - /* wait at least 35ns (W12) before issuing Read Status Register */ - udelay(1); - addr = (FPWV *) info->start[sector]; - *addr = (FPW) INTEL_STATUS; - - start = get_timer (0); - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { - *addr = (FPW) INTEL_RESET; /* restore read mode */ - printf("WSM busy too long, can't get prot status\n"); - return 1; - } - } - - /* issue the Read Identifier Codes command */ - *addr = (FPW) INTEL_READID; - - /* wait at least 35ns (W12) before reading */ - udelay(1); - - /* Intel example code uses offset of 4 for 8-bit flash */ - lock_conf_addr = (FPWV *) info->start[sector] + 4; - ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0; - - /* put flash back in read mode */ - *addr = (FPW) INTEL_RESET; - - return ret; -} diff --git a/board/o2dnt/o2dnt.c b/board/o2dnt/o2dnt.c deleted file mode 100644 index 81a2700..0000000 --- a/board/o2dnt/o2dnt.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. - */ -long int initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - else - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); - - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); - } - - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) - dramsize2 = 0; - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - - return dramsize + dramsize2; -} - -int checkboard (void) -{ - puts ("Board: O2DNT\n"); - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -void flash_afterinit(ulong size) -{ - if (size == 0x800000) { /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); - - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); - } -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif diff --git a/board/o2dnt/u-boot.lds b/board/o2dnt/u-boot.lds deleted file mode 100644 index 88dc118..0000000 --- a/board/o2dnt/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/omap1510inn/Makefile b/board/omap1510inn/Makefile deleted file mode 100644 index 902b24e..0000000 --- a/board/omap1510inn/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := omap1510innovator.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/omap1510inn/config.mk b/board/omap1510inn/config.mk deleted file mode 100644 index 7b24780..0000000 --- a/board/omap1510inn/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Kshitij Gupta -# -# TI Innovator board with OMAP1510 (ARM925T) cpu -# see http://www.ti.com/ for more information on Texas Insturments -# -# Innovator has 1 bank of 256 MB SDRAM -# Physical Address: -# 1000'0000 to 2000'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved) -# -# we load ourself to 1108'0000 -# -# - - -TEXT_BASE = 0x11080000 diff --git a/board/omap1510inn/lowlevel_init.S b/board/omap1510inn/lowlevel_init.S deleted file mode 100644 index 1c68e5b..0000000 --- a/board/omap1510inn/lowlevel_init.S +++ /dev/null @@ -1,396 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, - * - * -- Some bits of code used from rrload's head_OMAP1510.s -- - * Copyright (C) 2002 RidgeRun, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_OMAP1510) -#include <./configs/omap1510.h> -#endif - -#define OMAP1510_CLKS ((1< - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -static void flash__init (void); -static void ether__init (void); - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* arch number of OMAP 1510-Board */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - -/* kk - this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); - - flash__init (); - ether__init (); - return 0; -} - - -int misc_init_r (void) -{ - /* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */ - /* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */ - - /* setup gpio direction to match board (no floats!) */ - /**gdir = 0xCFF9; */ - /**mdir = 0x103F; */ - - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -static void flash__init (void) -{ -#define CS0_CHIP_SELECT_REG 0xfffecc10 -#define CS3_CHIP_SELECT_REG 0xfffecc1c -#define EMIFS_GlB_Config_REG 0xfffecc0c - - { - unsigned int regval; - - regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); - regval = regval | 0x0001; /* Turn off write protection for flash devices. */ - if (regval & 0x0002) { - regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */ - /* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */ - /* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */ - /* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */ - } - *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; - } -} - - -/****************************** - Routine: - Description: -******************************/ -static void ether__init (void) -{ -#define ETH_CONTROL_REG 0x0800000b - /* take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. - */ - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (3); -} - - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} diff --git a/board/omap1510inn/u-boot.lds b/board/omap1510inn/u-boot.lds deleted file mode 100644 index b6d1619..0000000 --- a/board/omap1510inn/u-boot.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm925t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/omap1610inn/Makefile b/board/omap1610inn/Makefile deleted file mode 100644 index 4560102..0000000 --- a/board/omap1610inn/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := omap1610innovator.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/omap1610inn/config.mk b/board/omap1610inn/config.mk deleted file mode 100644 index 80976ef..0000000 --- a/board/omap1610inn/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Kshitij Gupta -# -# TI Innovator board with OMAP1610 (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Innovator has 1 bank of 256 MB SDRAM -# Physical Address: -# 1000'0000 to 2000'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 -# (mem base + reserved) -# -# we load ourself to 1108'0000 -# -# - - -TEXT_BASE = 0x11080000 diff --git a/board/omap1610inn/flash.c b/board/omap1610inn/flash.c deleted file mode 100644 index c8e4c9e..0000000 --- a/board/omap1610inn/flash.c +++ /dev/null @@ -1,493 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); -void flash_unlock(flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[i]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[i]); - /* to reset the lock bit */ - flash_unlock(&flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_unlock(flash_info_t * info) -{ - int j; - for (j=2;jstart[j]); - flash_unprotect_sectors (addr); - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - } -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - OrgDef *pOrgDef; - - pOrgDef = OrgIntel_28F256L18T; - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/omap1610inn/lowlevel_init.S b/board/omap1610inn/lowlevel_init.S deleted file mode 100644 index eaf1742..0000000 --- a/board/omap1610inn/lowlevel_init.S +++ /dev/null @@ -1,452 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - - - /*------------------------------------------------------* - *mask all IRQs by setting all bits in the INTMR default* - *------------------------------------------------------*/ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT1) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT1 - ldr r1, VAL_ARM_IDLECT1 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT2 - ldr r1, VAL_ARM_IDLECT2 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT3) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT3 - ldr r1, VAL_ARM_IDLECT3 - str r1, [r0] - -#ifdef CONFIG_CS_AUTOBOOT /* do the setup depending on boot mode */ - ldr r0, CONF_STATUS - ldr r1, [r0] - tst r1, #0x02 - beq disable_wd /* booting from RAM, skip setup */ -#endif - - mov r1, #0x01 /* PER_EN bit */ - ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ - - /* Set CLKM to Sync-Scalable */ - /* I supposedly need to enable the dsp clock before switching */ - mov r1, #0x0000 - ldr r0, REG_ARM_SYSST - strh r1, [r0] - mov r0, #0x400 -1: - subs r0, r0, #0x1 /* wait for any bubbles to finish */ - bne 1b - ldr r1, VAL_ARM_CKCTL - ldr r0, REG_ARM_CKCTL - strh r1, [r0] - - /* a few nops to let settle */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* setup DPLL 1 */ - /* Ramp up the clock to 96Mhz */ - ldr r1, VAL_DPLL1_CTL - ldr r0, REG_DPLL1_CTL - strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ -2: - ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit.*/ - beq 2b /* loop until bit goes hi. */ -lock_end: - - - /*------------------------------------------------------* - * Turn off the watchdog during init... * - *------------------------------------------------------*/ -disable_wd: - ldr r0, REG_WATCHDOG - ldr r1, WATCHDOG_VAL1 - str r1, [r0] - ldr r1, WATCHDOG_VAL2 - str r1, [r0] - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL1 - str r1, [r0] - ldr r0, REG_WWPSDOG - -watch1Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch1Wait - - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL2 - str r1, [r0] - ldr r0, REG_WWPSDOG -watch2Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch2Wait - - - /* Set memory timings corresponding to the new clock speed */ - - /* Check execution location to determine current execution location - * and branch to appropriate initialization code. - */ - /* Load physical SDRAM base. */ - mov r0, #0x10000000 - /* Get current execution location. */ - mov r1, pc - /* Compare. */ - cmp r1, r0 - /* Skip over EMIF-fast initialization if running from SDRAM. */ - bge skip_sdram - - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 /* value should be checked */ -3: - subs r3, r3, #0x1 /* Decrement count */ - bne 3b - - - /* - * Set SDRAM control values. Disable refresh before MRS command. - */ - - /* mobile ddr operation */ - ldr r0, REG_SDRAM_OPERATION - mov r2, #07 - str r2, [r0] - - /* config register */ - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] - - /* manual command register */ - ldr r0, REG_SDRAM_MANUAL_CMD - /* issue set cke high */ - mov r1, #CMD_SDRAM_CKE_SET_HIGH - str r1, [r0] - /* issue nop */ - mov r1, #CMD_SDRAM_NOP - str r1, [r0] - - mov r2, #0x0100 -waitMDDR1: - subs r2, r2, #1 - bne waitMDDR1 /* delay loop */ - - /* issue precharge */ - mov r1, #CMD_SDRAM_PRECHARGE - str r1, [r0] - - /* issue autorefresh x 2 */ - mov r1, #CMD_SDRAM_AUTOREFRESH - str r1, [r0] - str r1, [r0] - - /* mrs register ddr mobile */ - ldr r0, REG_SDRAM_MRS - mov r1, #0x33 - str r1, [r0] - - /* emrs1 low-power register */ - ldr r0, REG_SDRAM_EMRS1 - /* self refresh on all banks */ - mov r1, #0 - str r1, [r0] - - ldr r0, REG_DLL_URD_CONTROL - ldr r1, DLL_URD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_LRD_CONTROL - ldr r1, DLL_LRD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_WRT_CONTROL - ldr r1, DLL_WRT_CONTROL_VAL - str r1, [r0] - - /* delay loop */ - mov r2, #0x0100 -waitMDDR2: - subs r2, r2, #1 - bne waitMDDR2 - - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 -4: - subs r3, r3, #1 /* Decrement count. */ - bne 4b - b common_tc - -skip_sdram: - - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] - -common_tc: - /* slow interface */ - ldr r1, VAL_TC_EMIFS_CS0_CONFIG - ldr r0, REG_TC_EMIFS_CS0_CONFIG - str r1, [r0] /* Chip Select 0 */ - - ldr r1, VAL_TC_EMIFS_CS1_CONFIG - ldr r0, REG_TC_EMIFS_CS1_CONFIG - str r1, [r0] /* Chip Select 1 */ - ldr r1, VAL_TC_EMIFS_CS3_CONFIG - ldr r0, REG_TC_EMIFS_CS3_CONFIG - str r1, [r0] /* Chip Select 3 */ - -#ifdef CONFIG_H2_OMAP1610 - /* inserting additional 2 clock cycle hold time for LAN */ - ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED - str r1, [r0] -#endif - /* Start MPU Timer 1 */ - ldr r0, REG_MPU_LOAD_TIMER - ldr r1, VAL_MPU_LOAD_TIMER - str r1, [r0] - - ldr r0, REG_MPU_CNTL_TIMER - ldr r1, VAL_MPU_CNTL_TIMER - str r1, [r0] - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -#ifdef CONFIG_CS_AUTOBOOT -CONF_STATUS: - .word 0xfffe1130 /* 32 bits */ -#endif - -REG_TC_EMIFS_CONFIG: /* 32 bits */ - .word 0xfffecc0c -REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ - .word 0xfffecc10 -REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ - .word 0xfffecc14 -REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ - .word 0xfffecc18 -REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ - .word 0xfffecc1c - -#ifdef CONFIG_H2_OMAP1610 -REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ - .word 0xfffecc54 -#endif - -/* MPU clock/reset/power mode control registers */ -REG_ARM_CKCTL: /* 16 bits */ - .word 0xfffece00 - -REG_ARM_IDLECT3: /* 16 bits */ - .word 0xfffece24 -REG_ARM_IDLECT2: /* 16 bits */ - .word 0xfffece08 -REG_ARM_IDLECT1: /* 16 bits */ - .word 0xfffece04 - -REG_ARM_RSTCT2: /* 16 bits */ - .word 0xfffece14 -REG_ARM_SYSST: /* 16 bits */ - .word 0xfffece18 -/* DPLL control registers */ -REG_DPLL1_CTL: /* 16 bits */ - .word 0xfffecf00 - -/* Watch Dog register */ -/* secure watchdog stop */ -REG_WSPRDOG: - .word 0xfffeb048 -/* watchdog write pending */ -REG_WWPSDOG: - .word 0xfffeb034 - -WSPRDOG_VAL1: - .word 0x0000aaaa -WSPRDOG_VAL2: - .word 0x00005555 - -/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, - counter @8192 rows, 10 ns, 8 burst */ -REG_SDRAM_CONFIG: - .word 0xfffecc20 - -/* Operation register */ -REG_SDRAM_OPERATION: - .word 0xfffecc80 - -/* Manual command register */ -REG_SDRAM_MANUAL_CMD: - .word 0xfffecc84 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_MRS: - .word 0xfffecc70 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_EMRS1: - .word 0xfffecc78 - -/* WRT DLL register */ -REG_DLL_WRT_CONTROL: - .word 0xfffecc68 -DLL_WRT_CONTROL_VAL: - .word 0x03f00002 - -/* URD DLL register */ -REG_DLL_URD_CONTROL: - .word 0xfffeccc0 -DLL_URD_CONTROL_VAL: - .word 0x00800002 - -/* LRD DLL register */ -REG_DLL_LRD_CONTROL: - .word 0xfffecccc - -REG_WATCHDOG: - .word 0xfffec808 - -REG_MPU_LOAD_TIMER: - .word 0xfffec600 -REG_MPU_CNTL_TIMER: - .word 0xfffec500 - -/* 96 MHz Samsung Mobile DDR */ -SDRAM_CONFIG_VAL: - .word 0x001200f4 - -DLL_LRD_CONTROL_VAL: - .word 0x00800002 - -VAL_ARM_CKCTL: - .word 0x3000 -VAL_DPLL1_CTL: - .word 0x2830 - -#ifdef CONFIG_INNOVATOROMAP1610 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x002130b0 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x00001131 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0x000055f0 -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88011131 -#endif - -#ifdef CONFIG_H2_OMAP1610 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x00203331 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x8180fff3 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0xf800f22a -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88011131 -VAL_TC_EMIFS_CS1_ADVANCED: - .word 0x00000022 -#endif - -VAL_TC_EMIFF_SDRAM_CONFIG: - .word 0x010290fc -VAL_TC_EMIFF_MRS: - .word 0x00000027 - -VAL_ARM_IDLECT1: - .word 0x00000400 - -VAL_ARM_IDLECT2: - .word 0x00000886 -VAL_ARM_IDLECT3: - .word 0x00000015 - -WATCHDOG_VAL1: - .word 0x000000f5 -WATCHDOG_VAL2: - .word 0x000000a0 - -VAL_MPU_LOAD_TIMER: - .word 0xffffffff -VAL_MPU_CNTL_TIMER: - .word 0xffffffa1 - -/* command values */ -.equ CMD_SDRAM_NOP, 0x00000000 -.equ CMD_SDRAM_PRECHARGE, 0x00000001 -.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 -.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/omap1610inn/omap1610innovator.c b/board/omap1610inn/omap1610innovator.c deleted file mode 100644 index 7842518..0000000 --- a/board/omap1610inn/omap1610innovator.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - -#ifdef CONFIG_CS_AUTOBOOT -unsigned long omap_flash_base; -#endif - -void flash__init (void); -void ether__init (void); -void set_muxconf_regs (void); -void peripheral_power_enable (void); - -#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - if (machine_is_omap_h2()) - gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2; - else if (machine_is_omap_innovator()) - gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR; - else - gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - /* Configure MUX settings */ - set_muxconf_regs (); - peripheral_power_enable (); - -/* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); - - flash__init (); - ether__init (); - return 0; -} - - -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -#define EMIFS_GlB_Config_REG 0xfffecc0c - unsigned int regval; - -#ifdef CONFIG_CS_AUTOBOOT - /* Check swapping of CS0 and CS3, set flash base accordingly */ - omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ? - PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1; -#endif - regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); - /* Turn off write protection for flash devices. */ - regval = regval | 0x0001; - *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -#define ETH_CONTROL_REG 0x0400030b - -#ifdef CONFIG_H2_OMAP1610 - #define LAN_RESET_REGISTER 0x0400001c - - /* The debug board on which the lan chip resides may not be powered - * ON at the same time as the OMAP chip. So wait in a loop until the - * lan reset register (on the debug board) is available (powered on) - * and reset the lan chip. - */ - - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; - udelay (3); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001); - - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - udelay (3); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000); -#endif - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (3); -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -/****************************************************** - Routine: set_muxconf_regs - Description: Setting up the configuration Mux registers - specific to the hardware -*******************************************************/ -void set_muxconf_regs (void) -{ - volatile unsigned int *MuxConfReg; - /* set each registers to its reset value; */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* setup for UART1 */ - *MuxConfReg &= ~(0x02000000); /* bit 25 */ - /* setup for UART2 */ - *MuxConfReg &= ~(0x01000000); /* bit 24 */ - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x08000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); - /*setup mux for UART3 */ - *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ - *MuxConfReg &= ~0x0000003e; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); - /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ - /* hardware will actually use TX and RTS based on bit 25 in */ - /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ - *MuxConfReg |= 0x00201000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); - /* setup for UART2 */ - /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ - /* hardware will actually use TX and RTS based on bit 24 in */ - /* FUNC_MUX_CTRL_0. */ - *MuxConfReg |= 0x09000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); - *MuxConfReg = 0x00000000; - /* mux setup for SD/MMC driver */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); - *MuxConfReg &= 0xFFFE0FFF; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 13 for MMC2 XOR_CLK */ - *MuxConfReg &= ~(0x00002000); - /* bit 29 for UART 1 */ - *MuxConfReg &= ~(0x00002000); - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ - *MuxConfReg |= 0x000C0000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); - *MuxConfReg &= ~(0x00000070); - *MuxConfReg &= ~(0x00000008); - *MuxConfReg |= 0x00000003; - *MuxConfReg |= 0x00000180; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 17, software controls VBUS */ - *MuxConfReg &= ~(0x00020000); - /* Enable USB 48 and 12M clocks */ - *MuxConfReg |= 0x00000200; - *MuxConfReg &= ~(0x00000180); - /*2.75V for MMCSDIO1 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); - *MuxConfReg = 0x00001FE7; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); - *MuxConfReg = 0x00000000; - /* Turn on UART2 48 MHZ clock */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - *MuxConfReg |= 0x40000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); - /* setup for USB VBus detection OMAP161x */ - *MuxConfReg |= 0x00040000; /* bit 18 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - /* PullUps for SD/MMC driver */ - *MuxConfReg |= ~(0xFFFE0FFF); - MuxConfReg = - (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); - *MuxConfReg = COMP_MODE_ENABLE; -} - -/****************************************************** - Routine: peripheral_power_enable - Description: Enable the power for UART1 -*******************************************************/ -void peripheral_power_enable (void) -{ -#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) -#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) - - *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; -} diff --git a/board/omap1610inn/u-boot.lds b/board/omap1610inn/u-boot.lds deleted file mode 100644 index 710b2a2..0000000 --- a/board/omap1610inn/u-boot.lds +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - . = ALIGN(4); - .text : - { - cpu/arm926ejs/start.o (.text) - *(.text) - } - . = ALIGN(4); - .rodata : { *(.rodata) } - . = ALIGN(4); - .data : { *(.data) } - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/omap2420h4/Makefile b/board/omap2420h4/Makefile deleted file mode 100644 index ed47868..0000000 --- a/board/omap2420h4/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := omap2420h4.o mem.o sys_info.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/omap2420h4/config.mk b/board/omap2420h4/config.mk deleted file mode 100644 index 3edcde0..0000000 --- a/board/omap2420h4/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2004 -# Texas Instruments, -# -# TI H4 board with OMAP2420 (ARM1136) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 -# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) ES2 will be configurable -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -TEXT_BASE = 0x80e80000 - -# Used with full SRAM boot. -# This is either with a GP system or a signed boot image. -# easiest, and safest way to go if you can. -#TEXT_BASE = 0x40270000 - - -# Handy to get symbols to debug ROM version. -#TEXT_BASE = 0x0 -#TEXT_BASE = 0x08000000 -#TEXT_BASE = 0x04000000 diff --git a/board/omap2420h4/flash.c b/board/omap2420h4/flash.c deleted file mode 100644 index d5e106a..0000000 --- a/board/omap2420h4/flash.c +++ /dev/null @@ -1,537 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define PHYS_FLASH_SECT_SIZE SZ_128K -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -# define FLASH_PORT_WIDTH ushort -# define FLASH_PORT_WIDTHV vu_short -# define SWAP(x) __swab16(x) -#else -# define FLASH_PORT_WIDTH ulong -# define FLASH_PORT_WIDTHV vu_long -# define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, SZ_32K}, /* 4 * 32kBytes sectors */ - {255, SZ_128K}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); -void flash_unlock(flash_info_t * info, int bank); -int flash_probe(void); - -/*----------------------------------------------------------------------- - */ - -/* see if flash is ok */ -int flash_probe(void) -{ - return(flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[0])); -} - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - /* to reset the lock bit */ - flash_unlock(&flash_info[i],i); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - /* to reset the lock bit */ - flash_unlock(&flash_info[i],i); - break; - - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - -#ifdef CFG_ENV_IS_IN_FLASH - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_unlock(flash_info_t * info, int bank) -{ - int j; - if (!bank) - j=2; /* leave 0,1 locked for boot bank */ - else - j=0; /* get the whole bank for #2 */ - - for (;jstart[j]); - if (addr == NULL) { - printf("Warning Flash probe failed\n"); - break; - } - flash_unprotect_sectors (addr); - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - } -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - volatile int r; /* gcc 3.4.0-1 strangeness, need to follow up.*/ - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 254) { /* 255,256,257,258 */ - r=i; - info->start[i] = base + (((r-(int)255) * SZ_32K) + (255*PHYS_FLASH_SECT_SIZE)); - info->protect[i] = 0; - } else { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - /* mb(); this one makes ARM11 err go away, but I want it :) as a guide to problems */ - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0] & 0xFF; /* just looking for 89 (8989 is hw pat)*/ - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return(0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): /* 880D */ - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; /*0-258*/ - info->size = SZ_32M; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return(info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect; - ulong type, start, last; - int rcode = 0; -#ifdef CONFIG_USE_IRQ - int iflag; -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - start = get_timer (0); - last = start; - -#ifdef CONFIG_USE_IRQ - /* Disable interrupts which might cause a timeout here */ - iflag = disable_interrupts (); -#endif - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } -#ifdef CONFIG_USE_IRQ - if (iflag) - enable_interrupts(); -#endif - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return(rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return(rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return(0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return(write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; -#ifdef CONFIG_USE_IRQ - int iflag; -#endif - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return(2); - } - /* Disable interrupts which might cause a timeout here */ -#ifdef CONFIG_USE_IRQ - iflag = disable_interrupts (); -#endif - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return(1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - -#ifdef CONFIG_USE_IRQ - if (iflag) - enable_interrupts(); -#endif - - return(0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/omap2420h4/lowlevel_init.S b/board/omap2420h4/lowlevel_init.S deleted file mode 100644 index 9752fc4..0000000 --- a/board/omap2420h4/lowlevel_init.S +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = PRCM_CLKCFG_CTRL - addr of valid reg - * R1 = CM_CLKEN_PLL - addr dpll ctlr reg - * R2 = dpll value - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - ******************************************************************************/ -.global go_to_speed - go_to_speed: - sub sp, sp, #0x4 /* get some stack space */ - str r4, [sp] /* save r4's value */ - - /* move into fast relock bypass */ - ldr r8, pll_ctl_add - mov r4, #0x2 - str r4, [r8] - ldr r4, pll_stat -block: - ldr r8, [r4] /* wait for bypass to take effect */ - and r8, r8, #0x3 - cmp r8, #0x1 - bne block - - /* set new dpll dividers _after_ in bypass */ - ldr r4, pll_div_add - ldr r8, pll_div_val - str r8, [r4] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r4, cfg3_0_addr - ldr r8, cfg3_0_val - str r8, [r4] - ldr r4, cfg4_0_addr - ldr r8, cfg4_0_val - str r8, [r4] - ldr r4, cfg1_0_addr - ldr r8, [r4] - orr r8, r8, #0x3 /* up gpmc divider */ - str r8, [r4] - - /* setup to 2x loop though code. The first loop pre-loads the - * icache, the 2nd commits the prcm config, and locks the dpll - */ - mov r4, #0x1000 /* spin spin spin */ - mov r8, #0x4 /* first pass condition & set registers */ - cmp r8, #0x4 -2: - ldrne r8, [r3] /* DPLL lock check */ - and r8, r8, #0x7 - cmp r8, #0x2 - beq 4f -3: - subeq r8, r8, #0x1 - streq r8, [r0] /* commit dividers (2nd time) */ - nop -lloop1: - sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop1 - mov r4, #0x40000 - cmp r8, #0x1 - nop - streq r2, [r1] /* lock dpll (2nd time) */ - nop -lloop2: - sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop2 - mov r4, #0x40000 - cmp r8, #0x1 - nop - ldreq r8, [r3] /* get lock condition for dpll */ - cmp r8, #0x4 /* first time though? */ - bne 2b - moveq r8, #0x2 /* set to dpll check condition. */ - beq 3b /* if condition not true branch */ -4: - ldr r4, [sp] - add sp, sp, #0x4 /* return stack space */ - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -cfg3_0_addr: - .word GPMC_CONFIG3_0 -cfg3_0_val: - .word H4_24XX_GPMC_CONFIG3_0 -cfg4_0_addr: - .word GPMC_CONFIG4_0 -cfg4_0_val: - .word H4_24XX_GPMC_CONFIG4_0 -cfg1_0_addr: - .word GPMC_CONFIG1_0 -pll_ctl_add: - .word CM_CLKEN_PLL -pll_stat: - .word CM_IDLEST_CKGEN -pll_div_add: - .word CM_CLKSEL1_PLL -pll_div_val: - .word DPLL_VAL /* DPLL setting (300MHz default) */ - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* map interrupt controller */ - ldr r0, VAL_INTH_SETUP - mcr p15, 0, r0, c15, c2, 4 - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -VAL_INTH_SETUP: - .word PERIFERAL_PORT_BASE -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c deleted file mode 100644 index 62eb6e3..0000000 --- a/board/omap2420h4/mem.c +++ /dev/null @@ -1,375 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/************************************************************ - * sdelay() - simple spin loop. Will be constant time as - * its generally used in 12MHz bypass conditions only. This - * is necessary until timers are accessible. - * - * not inline to increase chances its in cache when called - *************************************************************/ -void sdelay (unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/********************************************************************************* - * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default). - * -- called from SRAM, or Flash (using temp SRAM stack). - *********************************************************************************/ -void prcm_init(void) -{ - u32 div; - void (*f_lock_pll) (u32, u32, u32, u32); - extern void *_end_vect, *_start; - - f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE); - - __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */ - __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */ - __raw_writel(0, CM_ICLKEN1_CORE); - __raw_writel(0, CM_ICLKEN2_CORE); - - __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */ - __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */ - __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */ - __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */ - - div = BUS_DIV; - __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */ - sdelay(1000); - - if(running_in_sram()){ - /* If running fully from SRAM this is OK. The Flash bus drops out for just a little. - * but then comes back. If running from Flash this sequence kills you, thus you need - * to run it using CONFIG_PARTIAL_SRAM. - */ - __raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */ - wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */ - sdelay(1000); - /* set clock selection and dpll dividers. */ - __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); /* set pll for target rate */ - __raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */ - sdelay(10000); - __raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */ - sdelay(10000); - wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY); /*wait for dpll lock */ - }else if(running_in_flash()){ - /* if running from flash, need to jump to small relocated code area in SRAM. - * This is the only safe spot to do configurations from. - */ - (*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN); - } - - __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */ - wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY); /* wait for apll lock */ - sdelay(1000); -} - -/************************************************************************** - * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow - * command line mem=xyz use all memory with out discontigious support - * compiled in. Could do it at the ATAG, but there really is two banks... - * Called as part of 2nd phase DDR init. - **************************************************************************/ -void make_cs1_contiguous(void) -{ - u32 size, a_add_low, a_add_high; - - size = get_sdr_cs_size(SDRC_CS0_OSET); - size /= SZ_32M; /* find size to offset CS1 */ - a_add_high = (size & 3) << 8; /* set up low field */ - a_add_low = (size & 0x3C) >> 2; /* set up high field */ - __raw_writel((a_add_high|a_add_low),SDRC_CS_CFG); - -} - -/******************************************************** - * mem_ok() - test used to see if timings are correct - * for a part. Helps in gussing which part - * we are currently using. - *******************************************************/ -u32 mem_ok(void) -{ - u32 val1, val2; - u32 pattern = 0x12345678; - - __raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */ - __raw_writel(pattern, OMAP2420_SDRC_CS0); /* pattern to pos B */ - __raw_writel(0x0,OMAP2420_SDRC_CS0+4); /* remove pattern off the bus */ - val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */ - val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */ - - if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed*/ - return(0); - else - return(1); -} - - -/******************************************************** - * sdrc_init() - init the sdrc chip selects CS0 and CS1 - * - early init routines, called from flash or - * SRAM. - *******************************************************/ -void sdrc_init(void) -{ - #define EARLY_INIT 1 - do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */ -} - -/************************************************************************* - * do_sdrc_init(): initialize the SDRAM for use. - * -called from low level code with stack only. - * -code sets up SDRAM timing and muxing for 2422 or 2420. - * -optimal settings can be placed here, or redone after i2c - * inspection of board info - * - * This is a bit ugly, but should handle all memory moduels - * used with the H4. The first time though this code from s_init() - * we configure the first chip select. Later on we come back and - * will configure the 2nd chip select if it exists. - * - **************************************************************************/ -void do_sdrc_init(u32 offset, u32 early) -{ - u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype; - sdrc_data_t *sdata; /* do not change type */ - u32 a, b, r; - - static const sdrc_data_t sdrc_2422 = - { - H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0, - H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR, - 0, H4_2422_SDRC_DLLAB_CTRL - }; - static const sdrc_data_t sdrc_2420 = - { - H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR, - H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0, - H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR, - H4_2420_SDRC_DLLAB_CTRL - }; - - if (offset == SDRC_CS0_OSET) - cs0 = common = 1; /* int regs shared between both chip select */ - - cpu = get_cpu_type(); - rev = get_cpu_rev(); - - /* warning generated, though code generation is correct. this may bite later, - * but is ok for now. there is only so much C code you can do on stack only - * operation. - */ - if (cpu == CPU_2422){ - sdata = (sdrc_data_t *)&sdrc_2422; - pass_type = STACKED; - } else{ - sdata = (sdrc_data_t *)&sdrc_2420; - pass_type = IP_DDR; - } - - __asm__ __volatile__("": : :"memory"); /* limit compiler scope */ - - /* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx. - * If we are running in flash prior to relocation and we use data - * here which is not pc relative we need to get the address correct. - * We need to find the current flash mapping to dress up the initial - * pointer load. As long as this is const data we should be ok. - */ - if((early) && running_in_flash()){ - sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base()); - /* NOR internal boot offset is 0x4000 from xloader signature */ - if(running_from_internal_boot()) - sdata = (sdrc_data_t *)((u32)sdata + 0x4000); - } - - if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) { - if(mtype == DDR_COMBO){ - pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */ - pass_type = COMBO_DDR; /* CS1 config */ - __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER); - } - if(rev != CPU_2420_2422_ES1) /* for es2 and above smooth things out */ - make_cs1_contiguous(); - } - -next_mem_type: - if (common) { /* do a SDRC reset between types to clear regs*/ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */ - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */ - __raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */ - __raw_writel(sdata->sdrc_sharing, SDRC_SHARING); -#ifdef POWER_SAVE - __raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG); - __raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING); - __raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER); -#endif - } - - if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */ - __raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset); - else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset); - } else if (pass_type == IP_SDR){ /* ip sdr-CS0 */ - __raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset); - } - - a = sdata->sdrc_actim_ctrla_0; - b = sdata->sdrc_actim_ctrlb_0; - r = sdata->sdrc_dllab_ctrl; - - /* work around ES1 DDR issues */ - if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){ - a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1; - b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1; - r = H4_242x_SDRC_RFR_CTRL_ES1; - } - - if (cs0) { - __raw_writel(a, SDRC_ACTIM_CTRLA_0); - __raw_writel(b, SDRC_ACTIM_CTRLB_0); - } else { - __raw_writel(a, SDRC_ACTIM_CTRLA_1); - __raw_writel(b, SDRC_ACTIM_CTRLB_1); - } - __raw_writel(r, SDRC_RFR_CTRL+offset); - - /* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0+offset); - sdelay(5000); /* susposed to be 100us per design spec for mddr/msdr */ - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset); - - /* - * CSx SDRC Mode Register - * Burst length = (4 - DDR) (2-SDR) - * Serial mode - * CAS latency = x - */ - if(pass_type == IP_SDR) - __raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset); - else - __raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset); - - /* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/ - if (rev == CPU_2420_2422_ES1){ - dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */ - __raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7) - ,SMS_CLASS_ARB0);/* enable bust complete for lcd */ - } - else - dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */ - - /* enable & load up DLL with good value for 75MHz, and set phase to 90 - * ES1 recommends 90 phase, ES2 recommends 72 phase. - */ - if (common && (pass_type != IP_SDR)) { - __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL); - __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL); - __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL); - __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL); - } - sdelay(90000); - - if(mem_ok()) - return; /* STACKED, other configued type */ - ++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */ - goto next_mem_type; -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - u32 mux=0, mtype, mwidth, rev, tval; - - rev = get_cpu_rev(); - if (rev == CPU_2420_2422_ES1) - tval = 1; - else - tval = 0; /* disable bit switched meaning */ - - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */ -#ifdef CFG_NAND_BOOT - __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ -#else - __raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */ -#endif - - /* discover bus connection from sysboot */ - if (is_gpmc_muxed() == GPMC_MUXED) - mux = BIT9; - mtype = get_gpmc0_type(); - mwidth = get_gpmc0_width(); - - /* setup cs0 */ - __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */ - sdelay(1000); - -#ifdef CFG_NAND_BOOT - __raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0); -#else - __raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0); -#endif - -#ifdef PRCM_CONFIG_III - __raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); -#endif - __raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0); - __raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0); -#ifdef PRCM_CONFIG_III - __raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); - __raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0); -#endif - __raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */ - sdelay(2000); - - /* setup cs1 */ - __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */ - sdelay(1000); - __raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1); - __raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1); - __raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1); - __raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1); - __raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1); - __raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1); - __raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */ - sdelay(2000); -} diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c deleted file mode 100644 index 6ae1a49..0000000 --- a/board/omap2420h4/omap2420h4.c +++ /dev/null @@ -1,868 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; -#endif - - void wait_for_command_complete(unsigned int wd_base); - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gpmc_init(); /* in SRAM or SDRM, finish GPMC */ - - gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */ - gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */ - - return 0; -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_sram(void) -{ - /* if GP device unlock device SRAM for general use */ - if (get_device_type() == GP_DEVICE) { - __raw_writel(0xFF, A_REQINFOPERM0); - __raw_writel(0xCFDE, A_READPERM0); - __raw_writel(0xCFDE, A_WRITEPERM0); - } -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called path is with sram stack. - **********************************************************/ -void s_init(void) -{ - int in_sdram = running_in_sdram(); - - watchdog_init(); - set_muxconf_regs(); - delay(100); - try_unlock_sram(); - - if(!in_sdram) - prcm_init(); - - peripheral_enable(); - icache_enable(); - if (!in_sdram) - sdrc_init(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - ether_init(); /* better done here so timers are init'ed */ - return(0); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 4 watch dogs. 1 secure, and 3 general purpose. - * The ROM takes care of the secure one. Of the 3 GP ones, - * 1 can reset us directly, the other 2 only generate MPU interrupts. - */ - __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); - -#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/ - __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR); - wait_for_command_complete(WD3_BASE); - __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR); - - __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR); - wait_for_command_complete(WD4_BASE); - __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR); -#endif -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base+WWPS); - } while (pending); -} - -/******************************************************************* - * Routine:ether_init - * Description: take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. - ******************************************************************/ -void ether_init (void) -{ -#ifdef CONFIG_DRIVER_LAN91C96 - int cnt = 20; - - __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */ - - __raw_writew(0x0, LAN_RESET_REGISTER); - do { - __raw_writew(0x1, LAN_RESET_REGISTER); - udelay (100); - if (cnt == 0) - goto h4reset_err_out; - --cnt; - } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); - - cnt = 20; - - do { - __raw_writew(0x0, LAN_RESET_REGISTER); - udelay (100); - if (cnt == 0) - goto h4reset_err_out; - --cnt; - } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); - udelay (1000); - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (1000); - - h4reset_err_out: - return; -#endif -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int size0=0,size1=0; - u32 mtype, btype, rev, cpu; - u8 chg_on = 0x5; /* enable charge of back up battery */ - u8 vmode_on = 0x8C; - #define NOT_EARLY 0 - - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */ - - btype = get_board_type(); - mtype = get_mem_type(); - rev = get_cpu_rev(); - cpu = get_cpu_type(); - - display_board_info(btype); - if (btype == BOARD_H4_MENELAUS){ - update_mux(btype,mtype); /* combo part on menelaus */ - i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */ - i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */ - } - - if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { - do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */ - } - size0 = get_sdr_cs_size(SDRC_CS0_OSET); - size1 = get_sdr_cs_size(SDRC_CS1_OSET); - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */ - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - else /* ES2 and above can remap at 32MB granularity */ - gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; - gd->bd->bi_dram[1].size = size1; - - return 0; -} - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware - *********************************************************/ -void set_muxconf_regs (void) -{ - muxSetupSDRC(); - muxSetupGPMC(); - muxSetupUsb0(); - muxSetupUart3(); - muxSetupI2C1(); - muxSetupUART1(); - muxSetupLCD(); - muxSetupCamera(); - muxSetupMMCSD(); - muxSetupTouchScreen(); - muxSetupHDQ(); -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void peripheral_enable(void) -{ - unsigned int v, if_clks=0, func_clks=0; - - /* Enable GP2 timer.*/ - if_clks |= BIT4; - func_clks |= BIT4; - v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */ - __raw_writel(v, CM_CLKSEL2_CORE); - __raw_writel(0x1, CM_CLKSEL_WKUP); - -#ifdef CFG_NS16550 - /* Enable UART1 clock */ - func_clks |= BIT21; - if_clks |= BIT21; -#endif - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ - __raw_writel(v,CM_ICLKEN1_CORE ); - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN1_CORE); - delay(1000); - -#ifndef KERNEL_UPDATED - { -#define V1 0xffffffff -#define V2 0x00000007 - - __raw_writel(V1, CM_FCLKEN1_CORE); - __raw_writel(V2, CM_FCLKEN2_CORE); - __raw_writel(V1, CM_ICLKEN1_CORE); - __raw_writel(V1, CM_ICLKEN2_CORE); - } -#endif -} - -/**************************************** - * Routine: muxSetupUsb0 (ostboot) - * Description: Setup usb muxing - *****************************************/ -void muxSetupUsb0(void) -{ - volatile uint8 *MuxConfigReg; - volatile uint32 *otgCtrlReg; - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT; - *MuxConfigReg &= (uint8)(~0x1F); - - /* setup for USB VBus detection */ - otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL; - *otgCtrlReg |= 0x00040000; /* bit 18 */ -} - -/**************************************** - * Routine: muxSetupUart3 (ostboot) - * Description: Setup uart3 muxing - *****************************************/ -void muxSetupUart3(void) -{ - volatile uint8 *MuxConfigReg; - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX; - *MuxConfigReg &= (uint8)(~0x1F); - - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX; - *MuxConfigReg &= (uint8)(~0x1F); -} - -/**************************************** - * Routine: muxSetupI2C1 (ostboot) - * Description: Setup i2c muxing - *****************************************/ -void muxSetupI2C1(void) -{ - volatile unsigned char *MuxConfigReg; - - /* I2C1 Clock pin configuration, PIN = M19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* I2C1 Data pin configuration, PIN = L15 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* Pull-up required on data line */ - /* external pull-up already present. */ - /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */ -} - -/**************************************** - * Routine: muxSetupUART1 (ostboot) - * Description: Set up uart1 muxing - *****************************************/ -void muxSetupUART1(void) -{ - volatile unsigned char *MuxConfigReg; - - /* UART1_CTS pin configuration, PIN = D21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_RTS pin configuration, PIN = H21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_TX pin configuration, PIN = L20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_RX pin configuration, PIN = T21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ -} - -/**************************************** - * Routine: muxSetupLCD (ostboot) - * Description: Setup lcd muxing - *****************************************/ -void muxSetupLCD(void) -{ - volatile unsigned char *MuxConfigReg; - - /* LCD_D0 pin configuration, PIN = Y7 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D1 pin configuration, PIN = P10 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D2 pin configuration, PIN = V8 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D3 pin configuration, PIN = Y8 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D4 pin configuration, PIN = W8 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D5 pin configuration, PIN = R10 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D6 pin configuration, PIN = Y9 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D7 pin configuration, PIN = V9 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D8 pin configuration, PIN = W9 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D9 pin configuration, PIN = P11 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D10 pin configuration, PIN = V10 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D11 pin configuration, PIN = Y10 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D12 pin configuration, PIN = W10 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D13 pin configuration, PIN = R11 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D14 pin configuration, PIN = V11 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D15 pin configuration, PIN = W11 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D16 pin configuration, PIN = P12 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_D17 pin configuration, PIN = R12 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_PCLK pin configuration, PIN = W6 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_VSYNC pin configuration, PIN = V7 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_HSYNC pin configuration, PIN = Y6 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* LCD_ACBIAS pin configuration, PIN = W7 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ -} - -/**************************************** - * Routine: muxSetupCamera (ostboot) - * Description: Setup camera muxing - *****************************************/ -void muxSetupCamera(void) -{ - volatile unsigned char *MuxConfigReg; - - /* CAMERA_RSTZ pin configuration, PIN = Y16 */ - /* CAM_RST is connected through the I2C IO expander.*/ - /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/ - /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled */ - - /* CAMERA_XCLK pin configuration, PIN = U3 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_LCLK pin configuration, PIN = V5 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_VSYNC pin configuration, PIN = U2 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_HSYNC pin configuration, PIN = T3 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT0 pin configuration, PIN = T4 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT1 pin configuration, PIN = V2 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT2 pin configuration, PIN = V3 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT3 pin configuration, PIN = U4 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT4 pin configuration, PIN = W2 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT5 pin configuration, PIN = V4 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT6 pin configuration, PIN = W3 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT7 pin configuration, PIN = Y2 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT8 pin configuration, PIN = Y4 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* CAMERA_DAT9 pin configuration, PIN = V6 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ -} - -/**************************************** - * Routine: muxSetupMMCSD (ostboot) - * Description: set up MMC muxing - *****************************************/ -void muxSetupMMCSD(void) -{ - volatile unsigned char *MuxConfigReg; - - /* SDMMC_CLKI pin configuration, PIN = H15 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_CLKO pin configuration, PIN = G19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_CMD pin configuration, PIN = H18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - /* External pull-ups are present. */ - /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ - - /* SDMMC_DAT0 pin configuration, PIN = F20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - /* External pull-ups are present. */ - /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ - - /* SDMMC_DAT1 pin configuration, PIN = H14 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - /* External pull-ups are present. */ - /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ - - /* SDMMC_DAT2 pin configuration, PIN = E19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - /* External pull-ups are present. */ - /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ - - /* SDMMC_DAT3 pin configuration, PIN = D19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - /* External pull-ups are present. */ - /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ - - /* SDMMC_DDIR0 pin configuration, PIN = F19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_DDIR1 pin configuration, PIN = E20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_DDIR2 pin configuration, PIN = F18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_DDIR3 pin configuration, PIN = E18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SDMMC_CDIR pin configuration, PIN = G18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* MMC_CD pin configuration, PIN = B3 ---2420IP ONLY---*/ - /* MMC_CD for 2422IP=K1 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14, - *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ - - /* MMC_WP pin configuration, PIN = B4 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13, - *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ -} - -/****************************************** - * Routine: muxSetupTouchScreen (ostboot) - * Description: Set up touch screen muxing - *******************************************/ -void muxSetupTouchScreen(void) -{ - volatile unsigned char *MuxConfigReg; - - /* SPI1_CLK pin configuration, PIN = U18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SPI1_MOSI pin configuration, PIN = V20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SPI1_MISO pin configuration, PIN = T18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* SPI1_nCS0 pin configuration, PIN = U19 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* PEN_IRQ pin configuration, PIN = P20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR, - *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ -} - -/**************************************** - * Routine: muxSetupHDQ (ostboot) - * Description: setup 1wire mux - *****************************************/ -void muxSetupHDQ(void) -{ - volatile unsigned char *MuxConfigReg; - - /* HDQ_SIO pin configuration, PIN = N18 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO, - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ -} - -/*************************************************************** - * Routine: muxSetupGPMC (ostboot) - * Description: Configures balls which cam up in protected mode - ***************************************************************/ -void muxSetupGPMC(void) -{ - volatile uint8 *MuxConfigReg; - volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C; - - /* gpmc_io_dir */ - *MCR = 0x19000000; - - /* NOR FLASH CS0 */ - /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3, - *MuxConfigReg = 0x00 ; - - /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3, - *MuxConfigReg = 0x01 ; - - /* MPDB(Multi Port Debug Port) CS1 */ - /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1, - *MuxConfigReg = 0x00 ; - - /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2, - *MuxConfigReg = 0x00 ; -} - -/**************************************************************** - * Routine: muxSetupSDRC (ostboot) - * Description: Configures balls which come up in protected mode - ****************************************************************/ -void muxSetupSDRC(void) -{ - volatile uint8 *MuxConfigReg; - - /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1, - *MuxConfigReg = 0x00 ; - - /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2, - *MuxConfigReg = 0x00 ; - - /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3 Pull/up - N/A */ - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3, - *MuxConfigReg = 0x00; - - if (get_cpu_type() == CPU_2422) { - MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0, - *MuxConfigReg = 0x1b; - } -} - -/***************************************************************************** - * Routine: update_mux() - * Description: Update balls which are different beween boards. All should be - * updated to match functionaly. However, I'm only updating ones - * which I'll be using for now. When power comes into play they - * all need updating. - *****************************************************************************/ -void update_mux(u32 btype,u32 mtype) -{ - u32 cpu, base = OMAP2420_CTRL_BASE; - cpu = get_cpu_type(); - - if (btype == BOARD_H4_MENELAUS) { - if (cpu == CPU_2420) { - /* PIN = B3, GPIO.0->KBR5, mode 3, (pun?),-DO-*/ - __raw_writeb(0x3, base+0x30); - /* PIN = B13, GPIO.38->KBC6, mode 3, (pun?)-DO-*/ - __raw_writeb(0x3, base+0xa3); - /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/ - /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/ - /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/ - /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/ - /* PIN = M1 (HSUSBOTG) */ - /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/ - __raw_writeb(0x3, base+0x9d); - /* PIN = U32, (WLAN_CLKREQ) */ - /* PIN = Y11, WLAN */ - /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */ - __raw_writeb(0x3, base+0xe7); - /* PIN = AA8, mDOC */ - /* PIN = AA10, BT */ - /* PIN = AA13, WLAN */ - /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */ - __raw_writeb(0x3, base+0x10e); - /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */ - __raw_writeb(0x3, base+0x110); - /* PIN = J15 HHUSB */ - /* PIN = H19 HSUSB */ - /* PIN = W13, P13, R13, W16 ... */ - /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */ - __raw_writeb(0x3, base+0xde); - /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */ - __raw_writeb(0x0, base+0x12c); - /* PIN = AA17->sys_clkreq mode 0 -DO- */ - __raw_writeb(0x0, base+0x136); - } else if (cpu == CPU_2422) { - /* PIN = B3, GPIO.0->nc, mode 3, set above (pun?)*/ - /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/ - /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/ - /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/ - /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/ - __raw_writeb(0x0, base+0x92); - /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/ - /* PIN = M1 (HSUSBOTG) */ - /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/ - __raw_writeb(0x3, base+0x10c); - /* PIN = U32, (WLAN_CLKREQ) */ - /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */ - __raw_writeb(0x3, base+0x30); - /* PIN = AA8, mDOC */ - /* PIN = AA10, BT */ - /* PIN = AA12, WLAN */ - /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */ - __raw_writeb(0x3, base+0x10e); - /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */ - __raw_writeb(0x3, base+0x110); - /* PIN = J15 HHUSB */ - /* PIN = H19 HSUSB */ - /* PIN = W13, P13, R13, W16 ... */ - /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */ - __raw_writeb(0x3, base+0xde); - /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */ - __raw_writeb(0x0, base+0x12c); - /* PIN = AA17->sys_clkreq mode 0 -DO- */ - __raw_writeb(0x0, base+0x136); - } - - } else if (btype == BOARD_H4_SDP) { - if (cpu == CPU_2420) { - /* PIN = B3, GPIO.0->nc mode 3, set above (pun?)*/ - /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/ - /* Pin = Y11 VLNQ */ - /* Pin = AA4 VLNQ */ - /* Pin = AA6 VLNQ */ - /* Pin = AA8 VLNQ */ - /* Pin = AA10 VLNQ */ - /* Pin = AA12 VLNQ */ - /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */ - __raw_writeb(0x3, base+0x10e); - /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */ - __raw_writeb(0x3, base+0x110); - /* PIN = J15 MDOC_nDMAREQ */ - /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */ - __raw_writeb(0x3, base+0x114); - /* PIN = W13, V12, P13, R13, W19, W16 ... */ - /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */ - } else if (cpu == CPU_2422) { - /* PIN = B3, GPIO.0->MMC_CD, mode 3, set above */ - /* PIN = B13, GPIO.38->wlan_int, mode 3, (pun?)*/ - /* Pin = Y11 VLNQ */ - /* Pin = AA4 VLNQ */ - /* Pin = AA6 VLNQ */ - /* Pin = AA8 VLNQ */ - /* Pin = AA10 VLNQ */ - /* Pin = AA12 VLNQ */ - /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */ - __raw_writeb(0x3, base+0x10e); - /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */ - __raw_writeb(0x3, base+0x110); - /* PIN = J15 MDOC_nDMAREQ */ - /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */ - __raw_writeb(0x3, base+0x114); - /* PIN = W13, V12, P13, R13, W19, W16 ... */ - /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */ - } - } -} - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -void nand_init(void) -{ - extern flash_info_t flash_info[]; - - nand_probe(CFG_NAND_ADDR); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } - -#ifdef CFG_JFFS2_MEM_NAND - flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; - flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */ - flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ - flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */ -#endif -} -#endif diff --git a/board/omap2420h4/sys_info.c b/board/omap2420h4/sys_info.c deleted file mode 100644 index a9f7241..0000000 --- a/board/omap2420h4/sys_info.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include /* get mem tables */ -#include -#include -#include - -/************************************************************************** - * get_prod_id() - get id info from chips - ***************************************************************************/ -static u32 get_prod_id(void) -{ - u32 p; - p = __raw_readl(PRODUCTION_ID); /* get production ID */ - return((p & CPU_242X_PID_MASK) >> 16); -} - -/************************************************************************** - * get_cpu_type() - low level get cpu type - * - no C globals yet. - * - just looking to say if this is a 2422 or 2420 or ... - * - to start with we will look at switch settings.. - * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics - * (mux for 2420, non-mux for 2422). - ***************************************************************************/ -u32 get_cpu_type(void) -{ - u32 v; - - switch(get_prod_id()){ - case 1:;/* 2420 */ - case 2: return(CPU_2420); break; /* 2420 pop */ - case 4: return(CPU_2422); break; - case 8: return(CPU_2423); break; - default: break; /* early 2420/2422's unmarked */ - } - - v = __raw_readl(TAP_IDCODE_REG); - v &= CPU_24XX_ID_MASK; - if (v == CPU_2420_CHIPID) { /* currently 2420 and 2422 have same id */ - if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */ - return(CPU_2420); - else - return(CPU_2422); - } else - return(CPU_2420); /* don't know, say 2420 */ -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 v; - v = __raw_readl(TAP_IDCODE_REG); - v = v >> 28; - return(v+1); /* currently 2422 and 2420 match up */ -} -/**************************************************** - * is_mem_sdr() - return 1 if mem type in use is SDR - ****************************************************/ -u32 is_mem_sdr(void) -{ - volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET); - if(*burst == H4_2420_SDRC_MR_0_SDR) - return(1); - return(0); -} - -/*********************************************************** - * get_mem_type() - identify type of mDDR part used. - * 2422 uses stacked DDR, 2 parts CS0/CS1. - * 2420 may have 1 or 2, no good way to know...only init 1... - * when eeprom data is up we can select 1 more. - *************************************************************/ -u32 get_mem_type(void) -{ - u32 cpu, sdr = is_mem_sdr(); - - cpu = get_cpu_type(); - if (cpu == CPU_2422 || cpu == CPU_2423) - return(DDR_STACKED); - - if(get_prod_id() == 0x2) - return(XDR_POP); - - if (get_board_type() == BOARD_H4_MENELAUS) - if(sdr) - return(SDR_DISCRETE); - else - return(DDR_COMBO); - else - if(sdr) /* SDP + SDR kit */ - return(SDR_DISCRETE); - else - return(DDR_DISCRETE); /* origional SDP */ -} - -/*********************************************************************** - * get_cs0_size() - get size of chip select 0/1 - ************************************************************************/ -u32 get_sdr_cs_size(u32 offset) -{ - u32 size; - size = __raw_readl(SDRC_MCFG_0+offset) >> 8; /* get ram size field */ - size &= 0x2FF; /* remove unwanted bits */ - size *= SZ_2M; /* find size in MB */ - return(size); -} - -/*********************************************************************** - * get_board_type() - get board type based on current production stats. - * --- NOTE: 2 I2C EEPROMs will someday be populated with proper info. - * when they are available we can get info from there. This should - * be correct of all known boards up until today. - ************************************************************************/ -u32 get_board_type(void) -{ - if (i2c_probe(I2C_MENELAUS) == 0) - return(BOARD_H4_MENELAUS); - else - return(BOARD_H4_SDP); -} - -/****************************************************************** - * get_sysboot_value() - get init word settings (dip switch on h4) - ******************************************************************/ -inline u32 get_sysboot_value(void) -{ - return(0x00000FFF & __raw_readl(CONTROL_STATUS)); -} - -/*************************************************************************** - * get_gpmc0_base() - Return current address hardware will be - * fetching from. The below effectively gives what is correct, its a bit - * mis-leading compared to the TRM. For the most general case the mask - * needs to be also taken into account this does work in practice. - * - for u-boot we currently map: - * -- 0 to nothing, - * -- 4 to flash - * -- 8 to enent - * -- c to wifi - ****************************************************************************/ -u32 get_gpmc0_base(void) -{ - u32 b; - - b = __raw_readl(GPMC_CONFIG7_0); - b &= 0x1F; /* keep base [5:0] */ - b = b << 24; /* ret 0x0b000000 */ - return(b); -} - -/***************************************************************** - * is_gpmc_muxed() - tells if address/data lines are multiplexed - *****************************************************************/ -u32 is_gpmc_muxed(void) -{ - u32 mux; - mux = get_sysboot_value(); - if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3)) - return(GPMC_MUXED); /* NAND Boot mode */ - if (mux & BIT1) /* if mux'ed */ - return(GPMC_MUXED); - else - return(GPMC_NONMUXED); -} - -/************************************************************************ - * get_gpmc0_type() - read sysboot lines to see type of memory attached - ************************************************************************/ -u32 get_gpmc0_type(void) -{ - u32 type; - type = get_sysboot_value(); - if ((type & (BIT3|BIT2)) == (BIT3|BIT2)) - return(TYPE_NAND); - else - return(TYPE_NOR); -} - -/******************************************************************* - * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) - *******************************************************************/ -u32 get_gpmc0_width(void) -{ - u32 width; - width = get_sysboot_value(); - if ((width & 0xF) == (BIT3|BIT2)) - return(WIDTH_8BIT); - else - return(WIDTH_16BIT); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return(1); - if (i==bound) - return(0); - } while (1); -} - -/********************************************************************* - * display_board_info() - print banner with board info. - *********************************************************************/ -void display_board_info(u32 btype) -{ - char cpu_2420[] = "2420"; /* cpu type */ - char cpu_2422[] = "2422"; - char cpu_2423[] = "2423"; - char db_men[] = "Menelaus"; /* board type */ - char db_ip[] = "IP"; - char mem_sdr[] = "mSDR"; /* memory type */ - char mem_ddr[] = "mDDR"; - char t_tst[] = "TST"; /* security level */ - char t_emu[] = "EMU"; - char t_hs[] = "HS"; - char t_gp[] = "GP"; - char unk[] = "?"; - - char *cpu_s, *db_s, *mem_s, *sec_s; - u32 cpu, rev, sec; - - rev = get_cpu_rev(); - cpu = get_cpu_type(); - sec = get_device_type(); - - if(is_mem_sdr()) - mem_s = mem_sdr; - else - mem_s = mem_ddr; - - if(cpu == CPU_2423) - cpu_s = cpu_2423; - else if (cpu == CPU_2422) - cpu_s = cpu_2422; - else - cpu_s = cpu_2420; - - if(btype == BOARD_H4_MENELAUS) - db_s = db_men; - else - db_s = db_ip; - - switch(sec){ - case TST_DEVICE: sec_s = t_tst; break; - case EMU_DEVICE: sec_s = t_emu; break; - case HS_DEVICE: sec_s = t_hs; break; - case GP_DEVICE: sec_s = t_gp; break; - default: sec_s = unk; - } - - printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev-1); - printf("TI H4 SDP Base Board + %s Daughter Board + %s \n", db_s, mem_s); -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = 242x IP platform (first 2xx boards) - * 1 = 242x Menelaus platfrom. - *************************************************************************/ -u32 get_board_rev(void) -{ - u32 rev = 0; - u32 btype = get_board_type(); - - if (btype == BOARD_H4_MENELAUS){ - rev = 1; - } - return(rev); -} - -/******************************************************** - * get_base(); get upper addr of current execution - *******************************************************/ -u32 get_base(void) -{ - u32 val; - __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory"); - val &= 0xF0000000; - val >>= 28; - return(val); -} - -/******************************************************** - * get_base2(); get 2upper addr of current execution - *******************************************************/ -u32 get_base2(void) -{ - u32 val; - __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory"); - val &= 0xFF000000; - val >>= 24; - return(val); -} - -/******************************************************** - * running_in_flash() - tell if currently running in - * flash. - *******************************************************/ -u32 running_in_flash(void) -{ - if (get_base() < 4) - return(1); /* in flash */ - return(0); /* running in SRAM or SDRAM */ -} - -/******************************************************** - * running_in_sram() - tell if currently running in - * sram. - *******************************************************/ -u32 running_in_sram(void) -{ - if (get_base() == 4) - return(1); /* in SRAM */ - return(0); /* running in FLASH or SDRAM */ -} -/******************************************************** - * running_in_sdram() - tell if currently running in - * flash. - *******************************************************/ -u32 running_in_sdram(void) -{ - if (get_base() > 4) - return(1); /* in sdram */ - return(0); /* running in SRAM or FLASH */ -} - -/************************************************************* - * running_from_internal_boot() - am I a signed NOR image. - *************************************************************/ -u32 running_from_internal_boot(void) -{ - u32 v, base; - - v = get_sysboot_value() & BIT3; - base = get_base2(); - /* if running at mask rom flash address and - * sysboot3 says this was an internal boot - */ - if ((base == 0x08) && v) - return(1); - else - return(0); -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8); - return(mode >>= 8); -} diff --git a/board/omap2420h4/u-boot.lds b/board/omap2420h4/u-boot.lds deleted file mode 100644 index 1460adc..0000000 --- a/board/omap2420h4/u-boot.lds +++ /dev/null @@ -1,59 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm1136/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/omap5912osk/Makefile b/board/omap5912osk/Makefile deleted file mode 100644 index 4b56421..0000000 --- a/board/omap5912osk/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := omap5912osk.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/omap5912osk/config.mk b/board/omap5912osk/config.mk deleted file mode 100644 index 0375796..0000000 --- a/board/omap5912osk/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2002-2004 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Kshitij Gupta -# -# (C) Copyright 2004 -# Texas Instruments, -# Rishi Bhattacharya -# -# TI OSK board with OMAP5912 (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# OSK has 1 bank of 256 MB SDRAM -# Physical Address: -# 1000'0000 to 2000'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 -# (mem base + reserved) -# -# we load ourself to 1108'0000 -# -# - - -TEXT_BASE = 0x11080000 diff --git a/board/omap5912osk/lowlevel_init.S b/board/omap5912osk/lowlevel_init.S deleted file mode 100644 index 3b9633a..0000000 --- a/board/omap5912osk/lowlevel_init.S +++ /dev/null @@ -1,442 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - - - /*------------------------------------------------------* - *mask all IRQs by setting all bits in the INTMR default* - *------------------------------------------------------*/ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT1) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT1 - ldr r1, VAL_ARM_IDLECT1 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT2 - ldr r1, VAL_ARM_IDLECT2 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT3) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT3 - ldr r1, VAL_ARM_IDLECT3 - str r1, [r0] - - - mov r1, #0x01 /* PER_EN bit */ - ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ - - /* Set CLKM to Sync-Scalable */ - /* I supposedly need to enable the dsp clock before switching */ - mov r1, #0x0000 - ldr r0, REG_ARM_SYSST - strh r1, [r0] - mov r0, #0x400 -1: - subs r0, r0, #0x1 /* wait for any bubbles to finish */ - bne 1b - ldr r1, VAL_ARM_CKCTL - ldr r0, REG_ARM_CKCTL - strh r1, [r0] - - /* a few nops to let settle */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* setup DPLL 1 */ - /* Ramp up the clock to 96Mhz */ - ldr r1, VAL_DPLL1_CTL - ldr r0, REG_DPLL1_CTL - strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ -2: - ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit.*/ - beq 2b /* loop until bit goes hi. */ -lock_end: - - - /*------------------------------------------------------* - * Turn off the watchdog during init... * - *------------------------------------------------------*/ - ldr r0, REG_WATCHDOG - ldr r1, WATCHDOG_VAL1 - str r1, [r0] - ldr r1, WATCHDOG_VAL2 - str r1, [r0] - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL1 - str r1, [r0] - ldr r0, REG_WWPSDOG - -watch1Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch1Wait - - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL2 - str r1, [r0] - ldr r0, REG_WWPSDOG -watch2Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch2Wait - - - /* Set memory timings corresponding to the new clock speed */ - - /* Check execution location to determine current execution location - * and branch to appropriate initialization code. - */ - /* Load physical SDRAM base. */ - mov r0, #0x10000000 - /* Get current execution location. */ - mov r1, pc - /* Compare. */ - cmp r1, r0 - /* Skip over EMIF-fast initialization if running from SDRAM. */ - bge skip_sdram - - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 /* value should be checked */ -3: - subs r3, r3, #0x1 /* Decrement count */ - bne 3b - - - /* - * Set SDRAM control values. Disable refresh before MRS command. - */ - - /* mobile ddr operation */ - ldr r0, REG_SDRAM_OPERATION - mov r2, #07 - str r2, [r0] - - /* config register */ - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] - - /* manual command register */ - ldr r0, REG_SDRAM_MANUAL_CMD - /* issue set cke high */ - mov r1, #CMD_SDRAM_CKE_SET_HIGH - str r1, [r0] - /* issue nop */ - mov r1, #CMD_SDRAM_NOP - str r1, [r0] - - mov r2, #0x0100 -waitMDDR1: - subs r2, r2, #1 - bne waitMDDR1 /* delay loop */ - - /* issue precharge */ - mov r1, #CMD_SDRAM_PRECHARGE - str r1, [r0] - - /* issue autorefresh x 2 */ - mov r1, #CMD_SDRAM_AUTOREFRESH - str r1, [r0] - str r1, [r0] - - /* mrs register ddr mobile */ - ldr r0, REG_SDRAM_MRS - mov r1, #0x33 - str r1, [r0] - - /* emrs1 low-power register */ - ldr r0, REG_SDRAM_EMRS1 - /* self refresh on all banks */ - mov r1, #0 - str r1, [r0] - - ldr r0, REG_DLL_URD_CONTROL - ldr r1, DLL_URD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_LRD_CONTROL - ldr r1, DLL_LRD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_WRT_CONTROL - ldr r1, DLL_WRT_CONTROL_VAL - str r1, [r0] - - /* delay loop */ - mov r2, #0x0100 -waitMDDR2: - subs r2, r2, #1 - bne waitMDDR2 - - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 -4: - subs r3, r3, #1 /* Decrement count. */ - bne 4b - b common_tc - -skip_sdram: - - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] - -common_tc: - /* slow interface */ - ldr r1, VAL_TC_EMIFS_CS0_CONFIG - ldr r0, REG_TC_EMIFS_CS0_CONFIG - str r1, [r0] /* Chip Select 0 */ - - ldr r1, VAL_TC_EMIFS_CS1_CONFIG - ldr r0, REG_TC_EMIFS_CS1_CONFIG - str r1, [r0] /* Chip Select 1 */ - ldr r1, VAL_TC_EMIFS_CS3_CONFIG - ldr r0, REG_TC_EMIFS_CS3_CONFIG - str r1, [r0] /* Chip Select 3 */ - -#ifdef CONFIG_H2_OMAP1610 - /* inserting additional 2 clock cycle hold time for LAN */ - ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED - str r1, [r0] -#endif - /* Start MPU Timer 1 */ - ldr r0, REG_MPU_LOAD_TIMER - ldr r1, VAL_MPU_LOAD_TIMER - str r1, [r0] - - ldr r0, REG_MPU_CNTL_TIMER - ldr r1, VAL_MPU_CNTL_TIMER - str r1, [r0] - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - - -REG_TC_EMIFS_CONFIG: /* 32 bits */ - .word 0xfffecc0c -REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ - .word 0xfffecc10 -REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ - .word 0xfffecc14 -REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ - .word 0xfffecc18 -REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ - .word 0xfffecc1c - -#ifdef CONFIG_H2_OMAP1610 -REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ - .word 0xfffecc54 -#endif - -/* MPU clock/reset/power mode control registers */ -REG_ARM_CKCTL: /* 16 bits */ - .word 0xfffece00 - -REG_ARM_IDLECT3: /* 16 bits */ - .word 0xfffece24 -REG_ARM_IDLECT2: /* 16 bits */ - .word 0xfffece08 -REG_ARM_IDLECT1: /* 16 bits */ - .word 0xfffece04 - -REG_ARM_RSTCT2: /* 16 bits */ - .word 0xfffece14 -REG_ARM_SYSST: /* 16 bits */ - .word 0xfffece18 -/* DPLL control registers */ -REG_DPLL1_CTL: /* 16 bits */ - .word 0xfffecf00 - -/* Watch Dog register */ -/* secure watchdog stop */ -REG_WSPRDOG: - .word 0xfffeb048 -/* watchdog write pending */ -REG_WWPSDOG: - .word 0xfffeb034 - -WSPRDOG_VAL1: - .word 0x0000aaaa -WSPRDOG_VAL2: - .word 0x00005555 - -/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, - counter @8192 rows, 10 ns, 8 burst */ -REG_SDRAM_CONFIG: - .word 0xfffecc20 - -/* Operation register */ -REG_SDRAM_OPERATION: - .word 0xfffecc80 - -/* Manual command register */ -REG_SDRAM_MANUAL_CMD: - .word 0xfffecc84 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_MRS: - .word 0xfffecc70 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_EMRS1: - .word 0xfffecc78 - -/* WRT DLL register */ -REG_DLL_WRT_CONTROL: - .word 0xfffecc68 -DLL_WRT_CONTROL_VAL: - .word 0x03f00002 - -/* URD DLL register */ -REG_DLL_URD_CONTROL: - .word 0xfffeccc0 -DLL_URD_CONTROL_VAL: - .word 0x00800002 - -/* LRD DLL register */ -REG_DLL_LRD_CONTROL: - .word 0xfffecccc - -REG_WATCHDOG: - .word 0xfffec808 - -REG_MPU_LOAD_TIMER: - .word 0xfffec600 -REG_MPU_CNTL_TIMER: - .word 0xfffec500 - -/* 96 MHz Samsung Mobile DDR */ -SDRAM_CONFIG_VAL: - .word 0x001200f4 - -DLL_LRD_CONTROL_VAL: - .word 0x00800002 - -VAL_ARM_CKCTL: - .word 0x3000 -VAL_DPLL1_CTL: - .word 0x2830 - -#ifdef CONFIG_OSK_OMAP5912 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x002130b0 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x00001131 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0x000055f0 -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88011131 -#endif - -#ifdef CONFIG_H2_OMAP1610 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x00203331 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x8180fff3 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0xf800f22a -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88011131 -VAL_TC_EMIFS_CS1_ADVANCED: - .word 0x00000022 -#endif - -VAL_TC_EMIFF_SDRAM_CONFIG: - .word 0x010290fc -VAL_TC_EMIFF_MRS: - .word 0x00000027 - -VAL_ARM_IDLECT1: - .word 0x00000400 - -VAL_ARM_IDLECT2: - .word 0x00000886 -VAL_ARM_IDLECT3: - .word 0x00000015 - -WATCHDOG_VAL1: - .word 0x000000f5 -WATCHDOG_VAL2: - .word 0x000000a0 - -VAL_MPU_LOAD_TIMER: - .word 0xffffffff -VAL_MPU_CNTL_TIMER: - .word 0xffffffa1 - -/* command values */ -.equ CMD_SDRAM_NOP, 0x00000000 -.equ CMD_SDRAM_PRECHARGE, 0x00000001 -.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 -.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/omap5912osk/omap5912osk.c b/board/omap5912osk/omap5912osk.c deleted file mode 100644 index 1faa084..0000000 --- a/board/omap5912osk/omap5912osk.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * (C) Copyright 2004 - * Texas Instruments, - * Rishi Bhattacharya - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - -void flash__init (void); -void ether__init (void); -void set_muxconf_regs (void); -void peripheral_power_enable (void); - -#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - /* Configure MUX settings */ - set_muxconf_regs (); - peripheral_power_enable (); - -/* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); - - flash__init (); - ether__init (); - return 0; -} - - -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -#define EMIFS_GlB_Config_REG 0xfffecc0c - unsigned int regval; - regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); - /* Turn off write protection for flash devices. */ - regval = regval | 0x0001; - *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -#define ETH_CONTROL_REG 0x0480000b - int i; - - *((volatile unsigned short *) 0xfffece08) = 0x03FF; - *((volatile unsigned short *) 0xfffb3824) = 0x8000; - *((volatile unsigned short *) 0xfffb3830) = 0x0000; - *((volatile unsigned short *) 0xfffb3834) = 0x0009; - *((volatile unsigned short *) 0xfffb3838) = 0x0009; - *((volatile unsigned short *) 0xfffb3818) = 0x0002; - *((volatile unsigned short *) 0xfffb382C) = 0x0048; - *((volatile unsigned short *) 0xfffb3824) = 0x8603; - udelay (3); - for (i=0;i<2000;i++); - *((volatile unsigned short *) 0xfffb381C) = 0x6610; - udelay (30); - for (i=0;i<10000;i++); - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (3); - - -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -/****************************************************** - Routine: set_muxconf_regs - Description: Setting up the configuration Mux registers - specific to the hardware -*******************************************************/ -void set_muxconf_regs (void) -{ - volatile unsigned int *MuxConfReg; - /* set each registers to its reset value; */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* setup for UART1 */ - *MuxConfReg &= ~(0x02000000); /* bit 25 */ - /* setup for UART2 */ - *MuxConfReg &= ~(0x01000000); /* bit 24 */ - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x08000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); - /*setup mux for UART3 */ - *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ - *MuxConfReg &= ~0x0000003e; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); - /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ - /* hardware will actually use TX and RTS based on bit 25 in */ - /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ - *MuxConfReg |= 0x00201000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); - /* setup for UART2 */ - /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ - /* hardware will actually use TX and RTS based on bit 24 in */ - /* FUNC_MUX_CTRL_0. */ - *MuxConfReg |= 0x09000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D); - *MuxConfReg |= 0x00000020; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); - *MuxConfReg = 0x00000000; - /* mux setup for SD/MMC driver */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); - *MuxConfReg &= 0xFFFE0FFF; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 13 for MMC2 XOR_CLK */ - *MuxConfReg &= ~(0x00002000); - /* bit 29 for UART 1 */ - *MuxConfReg &= ~(0x00002000); - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ - *MuxConfReg |= 0x000C0000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); - *MuxConfReg &= ~(0x00000070); - *MuxConfReg &= ~(0x00000008); - *MuxConfReg |= 0x00000003; - *MuxConfReg |= 0x00000180; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 17, software controls VBUS */ - *MuxConfReg &= ~(0x00020000); - /* Enable USB 48 and 12M clocks */ - *MuxConfReg |= 0x00000200; - *MuxConfReg &= ~(0x00000180); - /*2.75V for MMCSDIO1 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); - *MuxConfReg = 0x00001FE7; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); - *MuxConfReg = 0x00000000; - /* Turn on UART2 48 MHZ clock */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - *MuxConfReg |= 0x40000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); - /* setup for USB VBus detection OMAP161x */ - *MuxConfReg |= 0x00040000; /* bit 18 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - /* PullUps for SD/MMC driver */ - *MuxConfReg |= ~(0xFFFE0FFF); - MuxConfReg = - (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); - *MuxConfReg = COMP_MODE_ENABLE; -} - -/****************************************************** - Routine: peripheral_power_enable - Description: Enable the power for UART1 -*******************************************************/ -void peripheral_power_enable (void) -{ -#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) -#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) - - *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; -} diff --git a/board/omap5912osk/u-boot.lds b/board/omap5912osk/u-boot.lds deleted file mode 100644 index 142450c..0000000 --- a/board/omap5912osk/u-boot.lds +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - . = ALIGN(4); - .text : - { - cpu/arm926ejs/start.o (.text) - *(.text) - } - . = ALIGN(4); - .rodata : { *(.rodata) } - . = ALIGN(4); - .data : { *(.data) } - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/omap730p2/Makefile b/board/omap730p2/Makefile deleted file mode 100644 index 29467ac..0000000 --- a/board/omap730p2/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := omap730p2.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/omap730p2/config.mk b/board/omap730p2/config.mk deleted file mode 100644 index 16bff6f..0000000 --- a/board/omap730p2/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Kshitij Gupta -# -# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Innovator has 1 bank of 256 MB SDRAM -# Physical Address: -# 1000'0000 to 2000'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 -# (mem base + reserved) -# -# we load ourself to 1108'0000 -# -# - -TEXT_BASE = 0x11080000 diff --git a/board/omap730p2/flash.c b/board/omap730p2/flash.c deleted file mode 100644 index e7d6515..0000000 --- a/board/omap730p2/flash.c +++ /dev/null @@ -1,477 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - OrgDef *pOrgDef; - - pOrgDef = OrgIntel_28F256L18T; - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - flash_unprotect_sectors (addr); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/omap730p2/lowlevel_init.S b/board/omap730p2/lowlevel_init.S deleted file mode 100644 index 6c6f482..0000000 --- a/board/omap730p2/lowlevel_init.S +++ /dev/null @@ -1,395 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003-2004 - * - * Texas Instruments, - * Kshitij Gupta - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited - * (http://www.mpc-data.co.uk) - * - * TODO : Tidy up and change to use system register defines - * from omap730.h where possible. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_OMAP730) -#include <./configs/omap730.h> -#endif - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - /* Save callers address in r11 - r11 must never be modified */ - mov r11, lr - - /*------------------------------------------------------* - *mask all IRQs by setting all bits in the INTMR default* - *------------------------------------------------------*/ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT1) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT1 - ldr r1, VAL_ARM_IDLECT1 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT2 - ldr r1, VAL_ARM_IDLECT2 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT3) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT3 - ldr r1, VAL_ARM_IDLECT3 - str r1, [r0] - - - mov r1, #0x01 /* PER_EN bit */ - ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ - - /* Set CLKM to Sync-Scalable */ - /* I supposedly need to enable the dsp clock before switching */ - mov r1, #0x1000 - ldr r0, REG_ARM_SYSST - strh r1, [r0] - mov r0, #0x400 -1: - subs r0, r0, #0x1 /* wait for any bubbles to finish */ - bne 1b - ldr r1, VAL_ARM_CKCTL - ldr r0, REG_ARM_CKCTL - strh r1, [r0] - - /* a few nops to let settle */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* setup DPLL 1 */ - /* Ramp up the clock to 96Mhz */ - ldr r1, VAL_DPLL1_CTL - ldr r0, REG_DPLL1_CTL - strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ -2: - ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit.*/ - beq 2b /* loop until bit goes hi. */ -lock_end: - - /*------------------------------------------------------* - * Turn off the watchdog during init... * - *------------------------------------------------------*/ - ldr r0, REG_WATCHDOG - ldr r1, WATCHDOG_VAL1 - str r1, [r0] - ldr r1, WATCHDOG_VAL2 - str r1, [r0] - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL1 - str r1, [r0] - ldr r0, REG_WWPSDOG - -watch1Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch1Wait - - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL2 - str r1, [r0] - ldr r0, REG_WWPSDOG -watch2Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch2Wait - - /* Set memory timings corresponding to the new clock speed */ - - /* Check execution location to determine current execution location - * and branch to appropriate initialization code. - */ - /* Compare physical SDRAM base & current execution location. */ - and r0, pc, #0xF0000000 - /* Compare. */ - cmp r0, #0 - /* Skip over EMIF-fast initialization if running from SDRAM. */ - bne skip_sdram - - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 /* value should be checked */ -3: - subs r3, r3, #0x1 /* Decrement count */ - bne 3b - - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] - - ldr r0, REG_SDRAM_MRS_LEGACY - ldr r1, SDRAM_MRS_VAL - str r1, [r0] - -skip_sdram: - -common_tc: - /* slow interface */ - ldr r1, VAL_TC_EMIFS_CS0_CONFIG - ldr r0, REG_TC_EMIFS_CS0_CONFIG - str r1, [r0] /* Chip Select 0 */ - - ldr r1, VAL_TC_EMIFS_CS1_CONFIG - ldr r0, REG_TC_EMIFS_CS1_CONFIG - str r1, [r0] /* Chip Select 1 */ - ldr r1, VAL_TC_EMIFS_CS2_CONFIG - ldr r0, REG_TC_EMIFS_CS2_CONFIG - str r1, [r0] /* Chip Select 2 */ - ldr r1, VAL_TC_EMIFS_CS3_CONFIG - ldr r0, REG_TC_EMIFS_CS3_CONFIG - str r1, [r0] /* Chip Select 3 */ - - /* 48MHz clock request for UART1 */ - ldr r1, PERSEUS2_CONFIG_BASE - ldrh r0, [r1, #CONFIG_PCC_CONF] - orr r0, r0, #CONF_MOD_UART1_CLK_MODE_R - strh r0, [r1, #CONFIG_PCC_CONF] - - /* Initialize public and private rheas - * - set access factor 2 on both rhea / strobe - * - disable write buffer on strb0, enable write buffer on strb1 - */ - - ldr R0, REG_RHEA_PUB_CTL - ldr R1, REG_RHEA_PRIV_CTL - ldr R2, VAL_RHEA_CTL - strh R2, [R0] - strh R2, [R1] - mov R3, #2 /* disable write buffer on strb0, enable write buffer on strb1 */ - strh R3, [R0, #0x08] /* arm rhea control reg */ - strh R3, [R1, #0x08] - - /* enable IRQ and FIQ */ - - mrs r4, CPSR - bic r4, r4, #IRQ_MASK - bic r4, r4, #FIQ_MASK - msr CPSR, r4 - - /* set TAP CONF to TRI EMULATION */ - - ldr r1, [r0, #CONFIG_MODE2] - bic r1, r1, #0x18 - orr r1, r1, #0x10 - str r1, [r0, #CONFIG_MODE2] - - /* set tdbgen to 1 */ - - ldr r0, PERSEUS2_CONFIG_BASE - ldr r1, [r0, #CONFIG_MODE1] - mov r2, #0x10000 - orr r1, r1, r2 - str r1, [r0, #CONFIG_MODE1] - -#ifdef CONFIG_P2_OMAP1610 - /* inserting additional 2 clock cycle hold time for LAN */ - ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED - str r1, [r0] -#endif - /* Start MPU Timer 1 */ - ldr r0, REG_MPU_LOAD_TIMER - ldr r1, VAL_MPU_LOAD_TIMER - str r1, [r0] - - ldr r0, REG_MPU_CNTL_TIMER - ldr r1, VAL_MPU_CNTL_TIMER - str r1, [r0] - - /* back to arch calling code */ - mov pc, r11 - - /* the literal pools origin */ - .ltorg - -REG_TC_EMIFS_CONFIG: /* 32 bits */ - .word 0xfffecc0c -REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ - .word 0xfffecc10 -REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ - .word 0xfffecc14 -REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ - .word 0xfffecc18 -REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ - .word 0xfffecc1c - -#ifdef CONFIG_P2_OMAP730 -REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ - .word 0xfffecc54 -#endif - -/* MPU clock/reset/power mode control registers */ -REG_ARM_CKCTL: /* 16 bits */ - .word 0xfffece00 - -REG_ARM_IDLECT3: /* 16 bits */ - .word 0xfffece24 -REG_ARM_IDLECT2: /* 16 bits */ - .word 0xfffece08 -REG_ARM_IDLECT1: /* 16 bits */ - .word 0xfffece04 - -REG_ARM_RSTCT2: /* 16 bits */ - .word 0xfffece14 -REG_ARM_SYSST: /* 16 bits */ - .word 0xfffece18 -/* DPLL control registers */ -REG_DPLL1_CTL: /* 16 bits */ - .word 0xfffecf00 - -/* Watch Dog register */ -/* secure watchdog stop */ -REG_WSPRDOG: - .word 0xfffeb048 -/* watchdog write pending */ -REG_WWPSDOG: - .word 0xfffeb034 - -WSPRDOG_VAL1: - .word 0x0000aaaa -WSPRDOG_VAL2: - .word 0x00005555 - -/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, - counter @8192 rows, 10 ns, 8 burst */ -REG_SDRAM_CONFIG: - .word 0xfffecc20 - -REG_SDRAM_MRS_LEGACY: - .word 0xfffecc24 - -REG_WATCHDOG: - .word 0xfffec808 - -REG_MPU_LOAD_TIMER: - .word 0xfffec600 -REG_MPU_CNTL_TIMER: - .word 0xfffec500 - -/* Public and private rhea bridge registers definition */ - -REG_RHEA_PUB_CTL: - .word 0xFFFECA00 - -REG_RHEA_PRIV_CTL: - .word 0xFFFED300 - -/* EMIFF SDRAM Configuration register - - self refresh disable - - auto refresh enabled - - SDRAM type 64 Mb, 16 bits bus 4 banks - - power down enabled - - SDRAM clock disabled - */ -SDRAM_CONFIG_VAL: - .word 0x0C017DF4 - -/* Burst full page length ; cas latency = 3 */ -SDRAM_MRS_VAL: - .word 0x00000037 - -VAL_ARM_CKCTL: - .word 0x6505 -VAL_DPLL1_CTL: - .word 0x3412 - -#ifdef CONFIG_P2_OMAP730 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x0000FFF3 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x00004278 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0x00004278 -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x00004278 -VAL_TC_EMIFS_CS1_ADVANCED: - .word 0x00000022 -#endif - -VAL_ARM_IDLECT1: - .word 0x00000400 -VAL_ARM_IDLECT2: - .word 0x00000886 -VAL_ARM_IDLECT3: - .word 0x00000015 - -WATCHDOG_VAL1: - .word 0x000000f5 -WATCHDOG_VAL2: - .word 0x000000a0 - -VAL_MPU_LOAD_TIMER: - .word 0xffffffff -VAL_MPU_CNTL_TIMER: - .word 0xffffffa1 - -VAL_RHEA_CTL: - .word 0xFF22 - -/* Config Register vals */ -PERSEUS2_CONFIG_BASE: - .word 0xFFFE1000 - -.equ CONFIG_PCC_CONF, 0xB4 -.equ CONFIG_MODE1, 0x10 -.equ CONFIG_MODE2, 0x14 -.equ CONF_MOD_UART1_CLK_MODE_R, 0x0A - -/* misc values */ -.equ IRQ_MASK, 0x80 /* IRQ mask value */ -.equ FIQ_MASK, 0x40 /* FIQ mask value */ diff --git a/board/omap730p2/omap730p2.c b/board/omap730p2/omap730p2.c deleted file mode 100644 index 256c6a6..0000000 --- a/board/omap730p2/omap730p2.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined(CONFIG_OMAP730) -#include <./configs/omap730.h> -#endif - -int test_boot_mode(void); -void spin_up_leds(void); -void flash__init (void); -void ether__init (void); -void set_muxconf_regs (void); -void peripheral_power_enable (void); - -#define FLASH_ON_CS0 1 -#define FLASH_ON_CS3 0 - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -int test_boot_mode(void) -{ - /* Check for CS0 and CS3 address decode swapping */ - if (*((volatile int *)EMIFS_CONFIG) & 0x00000002) - return(FLASH_ON_CS3); - else - return(FLASH_ON_CS0); -} - -/* Toggle backup LED indication */ -void toggle_backup_led(void) -{ - static int backupLEDState = 0; /* Init variable so that the LED will be ON the first time */ - volatile unsigned int *IOConfReg; - - - IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT); - - if (backupLEDState != 0) { - *IOConfReg &= (0xFFFFEFFF); - backupLEDState = 0; - } else { - *IOConfReg |= (0x00001000); - backupLEDState = 1; - } -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* arch number of OMAP 730 P2 Board - Same as the Innovator! */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - /* Configure MUX settings */ - set_muxconf_regs (); - - peripheral_power_enable (); - - /* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */ - toggle_backup_led(); - - /* Hold GSM in reset until needed */ - *((volatile unsigned short *)M_CTL) &= ~1; - - /* - * CSx timings, GPIO Mux ... setup - */ - - /* Flash: CS0 timings setup */ - *((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3; - *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088; - - /* Ethernet support trough the debug board */ - /* CS1 timings setup */ - *((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3; - *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000; - - /* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); - - flash__init (); - ether__init (); - - return 0; -} - -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ - unsigned int regval; - - regval = *((volatile unsigned int *) EMIFS_CONFIG); - /* Turn off write protection for flash devices. */ - regval = regval | 0x0001; - *((volatile unsigned int *) EMIFS_CONFIG) = regval; -} - -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -#define LAN_RESET_REGISTER 0x0400001c - - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; - udelay (100); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001); - - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - udelay (100); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000); - -#define ETH_CONTROL_REG 0x0400030b - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (100); -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -/****************************************************** - Routine: set_muxconf_regs - Description: Setting up the configuration Mux registers - specific to the hardware -*******************************************************/ -void set_muxconf_regs (void) -{ - volatile unsigned int *MuxConfReg; - /* set each registers to its reset value; */ - - /* - * Backup LED Indication - */ - - /* Configure MUXed pin. Mode 6: GPIO_140 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10); - *MuxConfReg &= (0xFFFFFF1F); /* Clear D_MPU_LPG1 */ - *MuxConfReg |= 0x000000C0; /* Set D_MPU_LPG1 to 0x6 */ - - /* Configure GPIO_140 as output */ - MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL); - *MuxConfReg &= (0xFFFFEFFF); /* Clear direction (output) for GPIO 140 */ - - /* - * Configure GPIOs for battery charge & feedback - */ - - /* Configure MUXed pin. Mode 6: GPIO_35 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3); - *MuxConfReg &= 0xFFFFFFF1; /* Clear M_CLK_OUT */ - *MuxConfReg |= 0x0000000C; /* Set M_CLK_OUT = 0x6 (GPIOs) */ - - /* Configure MUXed pin. Mode 6: GPIO_72,73,74 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5); - *MuxConfReg &= 0xFFFF1FFF; /* Clear D_DDR */ - *MuxConfReg |= 0x0000C000; /* Set D_DDR = 0x6 (GPIOs) */ - - MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL); - *MuxConfReg |= 0x00000100; /* Configure GPIO_72 as input */ - *MuxConfReg &= 0xFFFFFDFF; /* Configure GPIO_73 as output */ - - /* - * Allow battery charge - */ - - MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT); - *MuxConfReg &= (0xFFFFFDFF); /* Clear GPIO_73 pin */ - - /* - * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, - * It is used as the Ethernet controller interrupt - */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9); - *MuxConfReg &= 0x1FFFFFFF; -} - -/****************************************************** - Routine: peripheral_power_enable - Description: Enable the power for UART1 -*******************************************************/ -void peripheral_power_enable (void) -{ - volatile unsigned int *MuxConfReg; - - - /* Set up pins used by UART */ - - /* Start UART clock (48MHz) */ - MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG); - *MuxConfReg &= (0xFFFFFFF7); - *MuxConfReg |= (0x00000008); - - /* Get the UART pin in mode0 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3); - *MuxConfReg &= (0xFF1FFFFF); - *MuxConfReg &= (0xF1FFFFFF); -} diff --git a/board/omap730p2/u-boot.lds b/board/omap730p2/u-boot.lds deleted file mode 100644 index 710b2a2..0000000 --- a/board/omap730p2/u-boot.lds +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - . = ALIGN(4); - .text : - { - cpu/arm926ejs/start.o (.text) - *(.text) - } - . = ALIGN(4); - .rodata : { *(.rodata) } - . = ALIGN(4); - .data : { *(.data) } - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/oxc/Makefile b/board/oxc/Makefile deleted file mode 100644 index ae7a932..0000000 --- a/board/oxc/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/oxc/config.mk b/board/oxc/config.mk deleted file mode 100644 index 7a5bcfc..0000000 --- a/board/oxc/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# OXC boards -# - -#TEXT_BASE = 0x00090000 -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/oxc/flash.c b/board/oxc/flash.c deleted file mode 100644 index 795b7cc..0000000 --- a/board/oxc/flash.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for STM29W320DB/STM29W800D flash chips - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static ulong flash_get_size (vu_char *addr, flash_info_t *info); -static int write_byte (flash_info_t *info, ulong dest, uchar data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_PRELIMBASE) - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_STM: - printf ("ST "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_STM320DB: - printf ("M29W320DB (32 Mbit)\n"); - break; - case FLASH_STM800DB: - printf ("M29W800DB (8 Mbit, bottom boot block)\n"); - break; - case FLASH_STM800DT: - printf ("M29W800DT (8 Mbit, top boot block)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_char *addr, flash_info_t *info) -{ - short i; - uchar vendor, devid; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - addr[0x0AAA] = 0x90; - - udelay(1000); - - vendor = addr[0]; - devid = addr[2]; - - /* only support STM */ - if ((vendor << 16) != FLASH_MAN_STM) { - return 0; - } - - if (devid == FLASH_STM320DB) { - /* MPC8240 can address maximum 2Mb of flash, that is why the MSB - * lead is grounded and we can access only 2 first Mb */ - info->flash_id = vendor << 16 | devid; - info->sector_count = 32; - info->size = info->sector_count * 0x10000; - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + i * 0x10000; - } - } - else if (devid == FLASH_STM800DB) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 19; - info->size = 0x100000; - info->start[0] = 0x0000; - info->start[1] = 0x4000; - info->start[2] = 0x6000; - info->start[3] = 0x8000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i-3) * 0x10000; - } - } - else if (devid == FLASH_STM800DT) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 19; - info->size = 0x100000; - for (i = 0; i < info->sector_count-4; i++) { - info->start[i] = base + i * 0x10000; - } - info->start[i] = base + i * 0x10000; - info->start[i+1] = base + i * 0x10000 + 0x8000; - info->start[i+2] = base + i * 0x10000 + 0xa000; - info->start[i+3] = base + i * 0x10000 + 0xc000; - } - else { - return 0; - } - - /* mark all sectors as unprotected */ - for (i = 0; i < info->sector_count; i++) { - info->protect[i] = 0; - } - - /* Issue the reset command */ - if (info->flash_id != FLASH_UNKNOWN) { - addr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_char *addr = (vu_char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - addr[0x0AAA] = 0x80; - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_char *)(info->start[l_sect]); - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - int rc; - - while (cnt > 0) { - if ((rc = write_byte(info, addr, *src)) != 0) { - return (rc); - } - addr++; - src++; - cnt--; - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Write a byte to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_byte (flash_info_t *info, ulong dest, uchar data) -{ - vu_char *addr = (vu_char *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_char *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0AAA] = 0xAA; - addr[0x0555] = 0x55; - addr[0x0AAA] = 0xA0; - - *((vu_char *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/oxc/oxc.c b/board/oxc/oxc.c deleted file mode 100644 index fa7ff02..0000000 --- a/board/oxc/oxc.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -int checkboard (void) -{ - puts ( "Board: OXC8240\n" ); - return 0; -} - -long int initdram (int board_type) -{ -#ifndef CFG_RAMBOOT - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -#else - /* if U-Boot starts from RAM, then suppose we have 16Mb of RAM */ - return (16 << 20); -#endif -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_oxc_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x14, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x15, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_oxc_config_table, -#endif -}; - -void pci_init_board (void) -{ - pci_mpc824x_init(&hose); -} - -int board_early_init_f (void) -{ - *(volatile unsigned char *)(CFG_CPLD_RESET) = 0x89; - return 0; -} - -#ifdef CONFIG_WATCHDOG -void oxc_wdt_reset(void) -{ - *(volatile unsigned char *)(CFG_CPLD_WATCHDOG) = 0xff; -} - -void watchdog_reset(void) -{ - int re_enable = disable_interrupts(); - - oxc_wdt_reset(); - if (re_enable) - enable_interrupts(); -} -#endif - -static int oxc_get_expander(unsigned char addr, unsigned char * val) -{ - return i2c_read(addr, 0, 0, val, 1); -} - -static int oxc_set_expander(unsigned char addr, unsigned char val) -{ - return i2c_write(addr, 0, 0, &val, 1); -} - -static int expander0alive = 0; - -#ifdef CONFIG_SHOW_ACTIVITY -static int ledtoggle = 0; -static int ledstatus = 1; - -void oxc_toggle_activeled(void) -{ - ledtoggle++; -} - -void board_show_activity (ulong timestamp) -{ - if ((timestamp % (CFG_HZ / 10)) == 0) - oxc_toggle_activeled (); -} - -void show_activity(int arg) -{ - static unsigned char led = 0; - unsigned char val; - - if (!expander0alive) return; - - if ((ledtoggle > (2 * arg)) && ledstatus) { - led ^= 0x80; - oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val); - udelay(200); - oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, (val & 0x7F) | led); - ledtoggle = 0; - } -} -#endif - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress(int arg) -{ - unsigned char val; - - if (!expander0alive) return; - - if (arg > 0 && ledstatus) { - ledstatus = 0; - oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val); - udelay(200); - oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val | 0x80); - } else if (arg < 0) { - oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val); - udelay(200); - oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val & 0x7F); - ledstatus = 1; - } -} -#endif - -int misc_init_r (void) -{ - /* check whether the i2c expander #0 is accessible */ - if (!oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, 0x7F)) { - udelay(200); - expander0alive = 1; - } - -#ifdef CFG_OXC_GENERATE_IP - { - DECLARE_GLOBAL_DATA_PTR; - - char str[32]; - unsigned long ip = CFG_OXC_IPMASK; - bd_t *bd = gd->bd; - - if (expander0alive) { - unsigned char val; - - if (!oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val)) { - ip = (ip & 0xffffff00) | ((val & 0x7c) >> 2); - } - } - - if ((ip & 0xff) < 3) { - /* if fail, set x.x.x.254 */ - ip = (ip & 0xffffff00) | 0xfe; - } - - bd->bi_ip_addr = ip; - sprintf(str, "%ld.%ld.%ld.%ld", - (bd->bi_ip_addr & 0xff000000) >> 24, - (bd->bi_ip_addr & 0x00ff0000) >> 16, - (bd->bi_ip_addr & 0x0000ff00) >> 8, - (bd->bi_ip_addr & 0x000000ff)); - setenv("ipaddr", str); - printf("ip: %s\n", str); - } -#endif - return (0); -} diff --git a/board/oxc/u-boot.lds b/board/oxc/u-boot.lds deleted file mode 100644 index 2a5cd2e..0000000 --- a/board/oxc/u-boot.lds +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/pb1x00/Makefile b/board/pb1x00/Makefile deleted file mode 100644 index d1cdc6b..0000000 --- a/board/pb1x00/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o -SOBJS = memsetup.o - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/pb1x00/README b/board/pb1x00/README deleted file mode 100644 index b37ff36..0000000 --- a/board/pb1x00/README +++ /dev/null @@ -1,63 +0,0 @@ -By Thomas.Lange@corelatus.se 2004-Oct-05 ----------------------------------------- -DbAu1xx0 are development boards from AMD containing -an Alchemy AU1xx0 series cpu with mips32 core. -Existing cpu:s are Au1000, Au1100, Au1500 and Au1550 - -Limitations & comments ----------------------- -Support was originally big endian only. -I have not tested, but several u-boot users report working -configurations in little endian mode. - -I named the board dbau1x00, to allow -support for all three development boards -( dbau1000, dbau1100 and dbau1500 ). -Now there is a new board called dbau1550 also, which -should be supported RSN. - -I only have a dbau1000, so my testing is limited -to this board. - -The board has two different flash banks, that can -be selected via dip switch. This makes it possible -to test new bootloaders without thrashing the YAMON -boot loader delivered with board. - -NOTE! When you switch between the two boot flashes, the -base addresses will be swapped. -Have this in mind when you compile u-boot. TEXT_BASE has -to match the address where u-boot is located when you -actually launch. - -Ethernet only supported for mac0. - -PCMCIA only supported for slot 0, only 3.3V. - -PCMCIA IDE tested with Sandisk Compact Flash and -IBM microdrive. - -################################### -######## NOTE!!!!!! ######### -################################### -If you partition a disk on another system (e.g. laptop), -all bytes will be swapped on 16bit level when using -PCMCIA and running cpu in big endian mode!!!! - -This is probably due to an error in Au1000 chip. - -Solution: - -a) Boot via network and partition disk directly from -dbau1x00. The endian will then be correct. - -b) Partition disk on "laptop" and fill it with all files -you need. Then write a simple program that endian swaps -whole disk, - -Example: -Original "laptop" byte order: -B0 B1 B2 B3 B4 B5 B6 B7 B8 B9... - -Dbau1000 byte order will then be: -B1 B0 B3 B2 B5 B4 B7 B6 B9 B8... diff --git a/board/pb1x00/config.mk b/board/pb1x00/config.mk deleted file mode 100644 index 396a045..0000000 --- a/board/pb1x00/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# AMD development board AMD Alchemy Pb1x00, MIPS32 core -# - -# ROM version -#TEXT_BASE = 0xbfc00000 - -# SDRAM version -TEXT_BASE = 0x83800000 diff --git a/board/pb1x00/flash.c b/board/pb1x00/flash.c deleted file mode 100644 index 3cf29e8..0000000 --- a/board/pb1x00/flash.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - printf ("Skipping flash_init\n"); - return (0); -} - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - printf ("write_buff not implemented\n"); - return (-1); -} diff --git a/board/pb1x00/memsetup.S b/board/pb1x00/memsetup.S deleted file mode 100644 index 44f02b9..0000000 --- a/board/pb1x00/memsetup.S +++ /dev/null @@ -1,392 +0,0 @@ -/* Memory sub-system initialization code */ - -#include -#include -#include -#include -#include - -#define AU1500_SYS_ADDR 0xB1900000 -#define sys_endian 0x0038 -#define CP0_Config0 $16 -#define MEM_1MS ((396000000/1000000) * 1000) - - .text - .set noreorder - .set mips32 - - .globl memsetup -memsetup: - /* - * Step 1) Establish CPU endian mode. - * NOTE: A fair amount of code is necessary on the Pb1000 to - * obtain the value of Switch S8.1 which is used to determine - * endian at run-time. - */ - - /* RCE1 */ - li t0, MEM_STCFG1 - li t1, 0x00000083 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x33030A10 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x11803E40 - sw t1, 0(t0) - - /* Set DSTRB bits so switch will read correctly */ - li t1, 0xBE00000C - lw t2, 0(t1) - or t2, t2, 0x00000300 - sw t2, 0(t1) - - /* Check switch setting */ - li t1, 0xBE000014 - lw t2, 0(t1) - and t2, t2, 0x00000100 - bne t2, zero, big_endian - nop - -little_endian: - - /* Change Au1 core to little endian */ - li t0, AU1500_SYS_ADDR - li t1, 1 - sw t1, sys_endian(t0) - mfc0 t2, CP0_CONFIG - mtc0 t2, CP0_CONFIG - nop - nop - - /* Big Endian is default so nothing to do but fall through */ - -big_endian: - - /* - * Step 2) Establish Status Register - * (set BEV, clear ERL, clear EXL, clear IE) - */ - li t1, 0x00400000 - mtc0 t1, CP0_STATUS - - /* - * Step 3) Establish CP0 Config0 - * (set OD, set K0=3) - */ - li t1, 0x00080003 - mtc0 t1, CP0_CONFIG - - /* - * Step 4) Disable Watchpoint facilities - */ - li t1, 0x00000000 - mtc0 t1, CP0_WATCHLO - mtc0 t1, CP0_IWATCHLO - /* - * Step 5) Disable the performance counters - */ - mtc0 zero, CP0_PERFORMANCE - nop - - /* - * Step 6) Establish EJTAG Debug register - */ - mtc0 zero, CP0_DEBUG - nop - - /* - * Step 7) Establish Cause - * (set IV bit) - */ - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* Establish Wired (and Random) */ - mtc0 zero, CP0_WIRED - nop - - /* First setup pll:s to make serial work ok */ - /* We have a 12 MHz crystal */ - li t0, SYS_CPUPLL - li t1, 0x21 /* 396 MHz */ - sw t1, 0(t0) - sync - nop - nop - - /* wait 1mS for clocks to settle */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - /* Setup AUX PLL */ - li t0, SYS_AUXPLL - li t1, 8 /* 96 MHz */ - sw t1, 0(t0) /* aux pll */ - sync - - /* Static memory controller */ - - /* RCE0 8MB AMD29D323 Flash */ - li t0, MEM_STCFG0 - li t1, 0x00001403 - sw t1, 0(t0) - - li t0, MEM_STTIME0 - li t1, 0xFFFFFFDD - sw t1, 0(t0) - - li t0, MEM_STADDR0 - li t1, 0x11F83FE0 - sw t1, 0(t0) - - /* RCE1 CPLD Board Logic */ - li t0, MEM_STCFG1 - li t1, 0x00000083 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x33030A10 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x11803E40 - sw t1, 0(t0) - - /* RCE2 CPLD Board Logic */ - li t0, MEM_STCFG2 - li t1, 0x00000004 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x08061908 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x12A03FC0 - sw t1, 0(t0) - - /* RCE3 PCMCIA 250ns */ - li t0, MEM_STCFG3 - li t1, 0x00000002 - sw t1, 0(t0) - - li t0, MEM_STTIME3 - li t1, 0x280E3E07 - sw t1, 0(t0) - - li t0, MEM_STADDR3 - li t1, 0x10000000 - sw t1, 0(t0) - - sync - - /* Set peripherals to a known state */ - li t0, IC0_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC0_CFG0CLR - sw t1, 0(t0) - - li t0, IC0_CFG1CLR - sw t1, 0(t0) - - li t0, IC0_CFG2CLR - sw t1, 0(t0) - - li t0, IC0_SRCSET - sw t1, 0(t0) - - li t0, IC0_ASSIGNSET - sw t1, 0(t0) - - li t0, IC0_WAKECLR - sw t1, 0(t0) - - li t0, IC0_RISINGCLR - sw t1, 0(t0) - - li t0, IC0_FALLINGCLR - sw t1, 0(t0) - - li t0, IC0_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, IC1_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC1_CFG0CLR - sw t1, 0(t0) - - li t0, IC1_CFG1CLR - sw t1, 0(t0) - - li t0, IC1_CFG2CLR - sw t1, 0(t0) - - li t0, IC1_SRCSET - sw t1, 0(t0) - - li t0, IC1_ASSIGNSET - sw t1, 0(t0) - - li t0, IC1_WAKECLR - sw t1, 0(t0) - - li t0, IC1_RISINGCLR - sw t1, 0(t0) - - li t0, IC1_FALLINGCLR - sw t1, 0(t0) - - li t0, IC1_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, SYS_FREQCTRL0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_FREQCTRL1 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_CLKSRC - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_PININPUTEN - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, 0xB1100100 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, 0xB1400100 - li t1, 0x00000000 - sw t1, 0(t0) - - - li t0, SYS_WAKEMSK - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_WAKESRC - li t1, 0x00000000 - sw t1, 0(t0) - - /* wait 1mS before setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - - /* - * Skip memory setup if we are running from memory - */ - li t0, 0x90000000 - sub t0, ra, t0 - bltz t0, skip_memsetup - nop - - /* - * SDCS0 - Not used, for SMROM - * SDCS1 - 32MB Micron 48LCBM16A2 - * SDCS2 - 32MB Micron 48LCBM16A2 - */ - li t0, MEM_SDMODE0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_SDMODE1 - li t1, 0x00552229 - sw t1, 0(t0) - - li t0, MEM_SDMODE2 - li t1, 0x00552229 - sw t1, 0(t0) - - li t0, MEM_SDADDR0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_SDADDR1 - li t1, 0x001003F8 - sw t1, 0(t0) - - li t0, MEM_SDADDR2 - li t1, 0x001023F8 - sw t1, 0(t0) - - sync - - li t0, MEM_SDREFCFG - li t1, 0x74000c30 /* Disable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD - sw zero, 0(t0) - sync - - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - sw zero, 0(t0) - sync - - li t0, MEM_SDREFCFG - li t1, 0x76000c30 /* Enable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x00000023 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x00000023 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD2 - li t1, 0x00000023 - sw t1, 0(t0) - sync - - /* wait 1mS after setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - -skip_memsetup: - - li t0, SYS_PINFUNC - li t1, 0/*0x00008080*/ - sw t1, 0(t0) - - /* - li t0, SYS_TRIOUTCLR - li t1, 0x00001FFF - sw t1, 0(t0) - - li t0, SYS_OUTPUTCLR - li t1, 0x00008000 - sw t1, 0(t0) - */ - sync - - j ra - nop diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c deleted file mode 100644 index 40ac2a4..0000000 --- a/board/pb1x00/pb1x00.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2003 - * Thomas.Lange@corelatus.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -long int initdram(int board_type) -{ - /* Sdram is setup by assembler code */ - /* If memory could be changed, we should return the true value here */ - return 64*1024*1024; -} - -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 - -/* In cpu/mips/cpu.c */ -void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); - -int checkboard (void) -{ - u16 status; - /* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */ - volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; - u32 proc_id; - - *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - - proc_id = read_32bit_cp0_register(CP0_PRID); - - switch (proc_id >> 24) { - case 0: - puts ("Board: Pb1000\n"); - printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 1: - puts ("Board: Pb1500\n"); - printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 2: - puts ("Board: Pb1100\n"); - printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - default: - printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); - } -#if defined(CONFIG_IDE_PCMCIA) && 0 - /* Enable 3.3 V on slot 0 ( VCC ) - No 5V */ - status = 4; - *pcmcia_bcsr = status; - - status |= BCSR_PCMCIA_PC0DRVEN; - *pcmcia_bcsr = status; - au_sync(); - - udelay(300*1000); - - status |= BCSR_PCMCIA_PC0RST; - *pcmcia_bcsr = status; - au_sync(); - - udelay(100*1000); - - /* PCMCIA is on a 36 bit physical address. - We need to map it into a 32 bit addresses */ - -#if 0 - /* We dont need theese unless we run whole pcmcia package */ - write_one_tlb(20, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_IO_BASE, /* Hi */ - 0x3C000017, /* Lo0 */ - 0x3C200017); /* Lo1 */ - - write_one_tlb(21, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_ATTR_BASE, /* Hi */ - 0x3D000017, /* Lo0 */ - 0x3D200017); /* Lo1 */ -#endif /* 0 */ - write_one_tlb(22, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_MEM_ADDR, /* Hi */ - 0x3E000017, /* Lo0 */ - 0x3E200017); /* Lo1 */ -#endif /* CONFIG_IDE_PCMCIA */ - - return 0; -} diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds deleted file mode 100644 index a2d19a8..0000000 --- a/board/pb1x00/u-boot.lds +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - _gp = ALIGN(16); - - __got_start = .; - .got : { *(.got) } - __got_end = .; - - .sdata : { *(.sdata) } - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) } - uboot_end = .; -} diff --git a/board/pcippc2/Makefile b/board/pcippc2/Makefile deleted file mode 100644 index 2998f23..0000000 --- a/board/pcippc2/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o \ - fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o - -AOBJS = - -OBJS = $(COBJS) $(AOBJS) - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/pcippc2/config.mk b/board/pcippc2/config.mk deleted file mode 100644 index 92d37c9..0000000 --- a/board/pcippc2/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# PCIPPC-2 boards -# - -TEXT_BASE = 0xfff00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/pcippc2/cpc710.h b/board/pcippc2/cpc710.h deleted file mode 100644 index 8167270..0000000 --- a/board/pcippc2/cpc710.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _CPC710_H_ -#define _CPC710_H_ - -/* Revision */ -#define CPC710_TYPE_100 0x80 -#define CPC710_TYPE_100P 0x90 - -/* System control area */ -#define HW_PHYS_SCA 0xff000000 - -#define HW_SCA_CPC0 0x000000 -#define HW_SCA_SDRAM0 0x000000 -#define HW_SCA_DMA0 0x1C0000 - -#define HW_PHYS_CPC0 (HW_PHYS_SCA + HW_SCA_CPC0) -#define HW_PHYS_SDRAM0 (HW_PHYS_SCA + HW_SCA_SDRAM0) - -#define HW_CPC0_PCICNFR 0x000c -#define HW_CPC0_RSTR 0x0010 -#define HW_CPC0_SPOR 0x00e8 -#define HW_CPC0_UCTL 0x1000 -#define HW_CPC0_SIOC0 0x1020 -#define HW_CPC0_ABCNTL 0x1030 -#define HW_CPC0_SESR 0x1060 -#define HW_CPC0_SEAR 0x1070 -#define HW_CPC0_PGCHP 0x1100 -#define HW_CPC0_RGBAN0 0x1110 -#define HW_CPC0_RGBAN1 0x1120 - -#define HW_CPC0_GPDIR 0x1130 -#define HW_CPC0_GPIN 0x1140 -#define HW_CPC0_GPOUT 0x1150 - -#define HW_CPC0_ATAS 0x1160 - -#define HW_CPC0_PCIBAR 0x200018 -#define HW_CPC0_PCIENB 0x201000 - -#define HW_SDRAM0_MCCR 0x1200 -#define HW_SDRAM0_MESR 0x1220 -#define HW_SDRAM0_MEAR 0x1230 - -#define HW_SDRAM0_MCER0 0x1300 -#define HW_SDRAM0_MCER1 0x1310 -#define HW_SDRAM0_MCER2 0x1320 -#define HW_SDRAM0_MCER3 0x1330 -#define HW_SDRAM0_MCER4 0x1340 -#define HW_SDRAM0_MCER5 0x1350 -#define HW_SDRAM0_MCER6 0x1360 -#define HW_SDRAM0_MCER7 0x1370 - -#define HW_BRIDGE_PCIDG 0xf6120 -#define HW_BRIDGE_INTACK 0xf7700 -#define HW_BRIDGE_PIBAR 0xf7800 -#define HW_BRIDGE_PMBAR 0xf7810 -#define HW_BRIDGE_CRR 0xf7ef0 -#define HW_BRIDGE_PR 0xf7f20 -#define HW_BRIDGE_ACR 0xf7f30 -#define HW_BRIDGE_MSIZE 0xf7f40 -#define HW_BRIDGE_IOSIZE 0xf7f60 -#define HW_BRIDGE_SMBAR 0xf7f80 -#define HW_BRIDGE_SIBAR 0xf7fc0 -#define HW_BRIDGE_CFGADDR 0xf8000 -#define HW_BRIDGE_CFGDATA 0xf8010 -#define HW_BRIDGE_PSSIZE 0xf8100 -#define HW_BRIDGE_BARPS 0xf8120 -#define HW_BRIDGE_PSBAR 0xf8140 - -/* Configuration space registers */ -#define CPC710_BUS_NUMBER 0x40 -#define CPC710_SUB_BUS_NUMBER 0x41 - -#endif diff --git a/board/pcippc2/cpc710_init_ram.c b/board/pcippc2/cpc710_init_ram.c deleted file mode 100644 index 57ed8f0..0000000 --- a/board/pcippc2/cpc710_init_ram.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "pcippc2.h" -#include "i2c.h" - -typedef struct cpc710_mem_org_s -{ - u8 rows; - u8 cols; - u8 banks2; - u8 org; -} cpc710_mem_org_t; - -static int cpc710_compute_mcer (u32 * mcer, - unsigned long * - size, - unsigned int sdram); -static int cpc710_eeprom_checksum (unsigned int sdram); -static u8 cpc710_eeprom_read (unsigned int sdram, - unsigned int offset); - -static u32 cpc710_mcer_mem [] = -{ - 0x000003f3, /* 18 lines, 4 Mb */ - 0x000003e3, /* 19 lines, 8 Mb */ - 0x000003c3, /* 20 lines, 16 Mb */ - 0x00000383, /* 21 lines, 32 Mb */ - 0x00000303, /* 22 lines, 64 Mb */ - 0x00000203, /* 23 lines, 128 Mb */ - 0x00000003, /* 24 lines, 256 Mb */ - 0x00000002, /* 25 lines, 512 Mb */ - 0x00000001 /* 26 lines, 1024 Mb */ -}; -static cpc710_mem_org_t cpc710_mem_org [] = -{ - { 0x0c, 0x09, 0x02, 0x00 }, /* 0000: 12/ 9/2 */ - { 0x0d, 0x09, 0x02, 0x00 }, /* 0000: 13/ 9/2 */ - { 0x0d, 0x0a, 0x02, 0x00 }, /* 0000: 13/10/2 */ - { 0x0d, 0x0b, 0x02, 0x00 }, /* 0000: 13/11/2 */ - { 0x0d, 0x0c, 0x02, 0x00 }, /* 0000: 13/12/2 */ - { 0x0e, 0x0c, 0x02, 0x00 }, /* 0000: 14/12/2 */ - { 0x0b, 0x08, 0x02, 0x01 }, /* 0001: 11/ 8/2 */ - { 0x0b, 0x09, 0x01, 0x02 }, /* 0010: 11/ 9/1 */ - { 0x0b, 0x0a, 0x01, 0x03 }, /* 0011: 11/10/1 */ - { 0x0c, 0x08, 0x02, 0x04 }, /* 0100: 12/ 8/2 */ - { 0x0c, 0x0a, 0x02, 0x05 }, /* 0101: 12/10/2 */ - { 0x0d, 0x08, 0x01, 0x06 }, /* 0110: 13/ 8/1 */ - { 0x0d, 0x08, 0x02, 0x07 }, /* 0111: 13/ 8/2 */ - { 0x0d, 0x09, 0x01, 0x08 }, /* 1000: 13/ 9/1 */ - { 0x0d, 0x0a, 0x01, 0x09 }, /* 1001: 13/10/1 */ - { 0x0b, 0x08, 0x01, 0x0a }, /* 1010: 11/ 8/1 */ - { 0x0c, 0x08, 0x01, 0x0b }, /* 1011: 12/ 8/1 */ - { 0x0c, 0x09, 0x01, 0x0c }, /* 1100: 12/ 9/1 */ - { 0x0e, 0x09, 0x02, 0x0d }, /* 1101: 14/ 9/2 */ - { 0x0e, 0x0a, 0x02, 0x0e }, /* 1110: 14/10/2 */ - { 0x0e, 0x0b, 0x02, 0x0f } /* 1111: 14/11/2 */ -}; - -unsigned long cpc710_ram_init (void) -{ - unsigned long memsize = 0; - unsigned long bank_size; - u32 mcer; - -#ifndef CFG_RAMBOOT - /* Clear memory banks - */ - out32(REG(SDRAM0, MCER0), 0); - out32(REG(SDRAM0, MCER1), 0); - out32(REG(SDRAM0, MCER2), 0); - out32(REG(SDRAM0, MCER3), 0); - out32(REG(SDRAM0, MCER4), 0); - out32(REG(SDRAM0, MCER5), 0); - out32(REG(SDRAM0, MCER6), 0); - out32(REG(SDRAM0, MCER7), 0); - iobarrier_rw(); - - /* Disable memory - */ - out32(REG(SDRAM0,MCCR), 0x13b06000); - iobarrier_rw(); -#endif - - /* Only the first memory bank is initialised now - */ - if (! cpc710_compute_mcer(& mcer, & bank_size, 0)) - { - puts("Unsupported SDRAM type !\n"); - hang(); - } - memsize += bank_size; -#ifndef CFG_RAMBOOT - /* Enable bank, zero start - */ - out32(REG(SDRAM0, MCER0), mcer | 0x80000000); - iobarrier_rw(); -#endif - -#ifndef CFG_RAMBOOT - /* Enable memory - */ - out32(REG(SDRAM0, MCCR), in32(REG(SDRAM0, MCCR)) | 0x80000000); - - /* Wait until initialisation finished - */ - while (! (in32 (REG(SDRAM0, MCCR)) & 0x20000000)) - { - iobarrier_rw(); - } - - /* Clear Memory Error Status and Address registers - */ - out32(REG(SDRAM0, MESR), 0); - out32(REG(SDRAM0, MEAR), 0); - iobarrier_rw(); - - /* ECC is not configured now - */ -#endif - - /* Memory size counter - */ - out32(REG(CPC0, RGBAN1), memsize); - - return memsize; -} - -static int cpc710_compute_mcer ( - u32 * mcer, - unsigned long * size, - unsigned int sdram) -{ - u8 rows; - u8 cols; - u8 banks2; - unsigned int lines; - u32 mc = 0; - unsigned int i; - cpc710_mem_org_t * org = 0; - - - if (! i2c_reset()) - { - puts("Can't reset I2C!\n"); - hang(); - } - - if (! cpc710_eeprom_checksum(sdram)) - { - puts("Invalid EEPROM checksum !\n"); - hang(); - } - - rows = cpc710_eeprom_read(sdram, 3); - cols = cpc710_eeprom_read(sdram, 4); - /* Can be 2 or 4 banks; divide by 2 - */ - banks2 = cpc710_eeprom_read(sdram, 17) / 2; - - lines = rows + cols + banks2; - - if (lines < 18 || lines > 26) - { - /* Unsupported configuration - */ - return 0; - } - - - mc |= cpc710_mcer_mem [lines - 18] << 6; - - for (i = 0; i < sizeof(cpc710_mem_org) / sizeof(cpc710_mem_org_t); i++) - { - cpc710_mem_org_t * corg = cpc710_mem_org + i; - - if (corg->rows == rows && corg->cols == cols && corg->banks2 == banks2) - { - org = corg; - - break; - } - } - - if (! org) - { - /* Unsupported configuration - */ - return 0; - } - - mc |= (u32) org->org << 2; - - /* Supported configuration - */ - *mcer = mc; - *size = 1l << (lines + 4); - - return 1; -} - -static int cpc710_eeprom_checksum ( - unsigned int sdram) -{ - u8 sum = 0; - unsigned int i; - - for (i = 0; i < 63; i++) - { - sum += cpc710_eeprom_read(sdram, i); - } - - return sum == cpc710_eeprom_read(sdram, 63); -} - -static u8 cpc710_eeprom_read ( - unsigned int sdram, - unsigned int offset) -{ - u8 dev = (sdram << 1) | 0xa0; - u8 data; - - if (! i2c_read_byte(& data, dev,offset)) - { - puts("I2C error !\n"); - hang(); - } - - return data; -} diff --git a/board/pcippc2/cpc710_pci.c b/board/pcippc2/cpc710_pci.c deleted file mode 100644 index bed8aea..0000000 --- a/board/pcippc2/cpc710_pci.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#include "hardware.h" -#include "pcippc2.h" - -struct pci_controller local_hose, cpci_hose; - -static u32 cpc710_mapped_ram; - - /* Enable PCI retry timeouts - */ -void cpc710_pci_enable_timeout (void) -{ - out32(BRIDGE(LOCAL, CFGADDR), 0x50000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), 0x32000000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x50000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x32000000); - iobarrier_rw(); -} - -void cpc710_pci_init (void) -{ - u32 sdram_size = pcippc2_sdram_size(); - - cpc710_mapped_ram = sdram_size < PCI_MEMORY_MAXSIZE ? - sdram_size : PCI_MEMORY_MAXSIZE; - - /* Select the local PCI - */ - out32(REG(CPC0, PCICNFR), 0x80000002); - iobarrier_rw(); - - out32(REG(CPC0, PCIBAR), BRIDGE_LOCAL_PHYS); - iobarrier_rw(); - - /* Enable PCI bridge address decoding - */ - out32(REG(CPC0, PCIENB), 0x80000000); - iobarrier_rw(); - - /* Select the CPCI bridge - */ - out32(REG(CPC0, PCICNFR), 0x80000003); - iobarrier_rw(); - - out32(REG(CPC0, PCIBAR), BRIDGE_CPCI_PHYS); - iobarrier_rw(); - - /* Enable PCI bridge address decoding - */ - out32(REG(CPC0, PCIENB), 0x80000000); - iobarrier_rw(); - - /* Disable configuration accesses - */ - out32(REG(CPC0, PCICNFR), 0x80000000); - iobarrier_rw(); - - /* Initialise the local PCI - */ - out32(BRIDGE(LOCAL, CRR), 0x7c000000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PCIDG), 0x40000000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PIBAR), BRIDGE_LOCAL_IO_BUS); - out32(BRIDGE(LOCAL, SIBAR), BRIDGE_LOCAL_IO_PHYS); - out32(BRIDGE(LOCAL, IOSIZE), -BRIDGE_LOCAL_IO_SIZE); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PMBAR), BRIDGE_LOCAL_MEM_BUS); - out32(BRIDGE(LOCAL, SMBAR), BRIDGE_LOCAL_MEM_PHYS); - out32(BRIDGE(LOCAL, MSIZE), -BRIDGE_LOCAL_MEM_SIZE); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PR), 0x00ffe000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, ACR), 0xfe000000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PSBAR), PCI_MEMORY_BUS >> 24); - out32(BRIDGE(LOCAL, BARPS), PCI_MEMORY_PHYS >> 24); - out32(BRIDGE(LOCAL, PSSIZE), 256 - (cpc710_mapped_ram >> 24)); - iobarrier_rw(); - - /* Initialise the CPCI bridge - */ - out32(BRIDGE(CPCI, CRR), 0x7c000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, PCIDG), 0xC0000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, PIBAR), BRIDGE_CPCI_IO_BUS); - out32(BRIDGE(CPCI, SIBAR), BRIDGE_CPCI_IO_PHYS); - out32(BRIDGE(CPCI, IOSIZE), -BRIDGE_CPCI_IO_SIZE); - iobarrier_rw(); - out32(BRIDGE(CPCI, PMBAR), BRIDGE_CPCI_MEM_BUS); - out32(BRIDGE(CPCI, SMBAR), BRIDGE_CPCI_MEM_PHYS); - out32(BRIDGE(CPCI, MSIZE), -BRIDGE_CPCI_MEM_SIZE); - iobarrier_rw(); - out32(BRIDGE(CPCI, PR), 0x80ffe000); - iobarrier_rw(); - out32(BRIDGE(CPCI, ACR), 0xdf000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, PSBAR), PCI_MEMORY_BUS >> 24); - out32(BRIDGE(CPCI, BARPS), PCI_MEMORY_PHYS >> 24); - out32(BRIDGE(CPCI, PSSIZE), 256 - (cpc710_mapped_ram >> 24)); - iobarrier_rw(); - - /* Local PCI - */ - - out32(BRIDGE(LOCAL, CFGADDR), 0x04000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), 0x56010000); - iobarrier_rw(); - - out32(BRIDGE(LOCAL, CFGADDR), 0x0c000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER_VAL << 16); - iobarrier_rw(); - - /* Set bus and subbus numbers - */ - out32(BRIDGE(LOCAL, CFGADDR), 0x40000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), 0x00000000); - iobarrier_rw(); - - out32(BRIDGE(LOCAL, CFGADDR), 0x50000080); - iobarrier_rw(); - /* PCI retry timeouts will be enabled later - */ - out32(BRIDGE(LOCAL, CFGDATA), 0x00000000); - iobarrier_rw(); - - /* CPCI - */ - - /* Set bus and subbus numbers - */ - out32(BRIDGE(CPCI, CFGADDR), 0x40000080); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x01010000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x04000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x56010000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x0c000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER_VAL << 16); - iobarrier_rw(); - - /* Write to the PSBAR */ - out32(BRIDGE(CPCI, CFGADDR), 0x10000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), cpu_to_le32(PCI_MEMORY_BUS)); - iobarrier_rw(); - - /* Set bus and subbus numbers - */ - out32(BRIDGE(CPCI, CFGADDR), 0x40000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x01ff0000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x50000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x32000000); - /* PCI retry timeouts will be enabled later - */ - out32(BRIDGE(CPCI, CFGDATA), 0x00000000); - iobarrier_rw(); - - /* Remove reset on the PCI buses - */ - out32(BRIDGE(LOCAL, CRR), 0xfc000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, CRR), 0xfc000000); - iobarrier_rw(); - - local_hose.first_busno = 0; - local_hose.last_busno = 0xff; - - /* System memory space */ - pci_set_region(local_hose.regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHYS, - PCI_MEMORY_MAXSIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region(local_hose.regions + 1, - BRIDGE_LOCAL_MEM_BUS, - BRIDGE_LOCAL_MEM_PHYS, - BRIDGE_LOCAL_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(local_hose.regions + 2, - BRIDGE_LOCAL_IO_BUS, - BRIDGE_LOCAL_IO_PHYS, - BRIDGE_LOCAL_IO_SIZE, - PCI_REGION_IO); - - local_hose.region_count = 3; - - pci_setup_indirect(&local_hose, - BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGADDR, - BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGDATA); - - pci_register_hose(&local_hose); - - /* Initialize PCI32 bus registers */ - pci_hose_write_config_byte(&local_hose, - PCI_BDF(local_hose.first_busno,0,0), - CPC710_BUS_NUMBER, - local_hose.first_busno); - pci_hose_write_config_byte(&local_hose, - PCI_BDF(local_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - local_hose.last_busno); - - local_hose.last_busno = pci_hose_scan(&local_hose); - - /* Write out correct max subordinate bus number for local hose */ - pci_hose_write_config_byte(&local_hose, - PCI_BDF(local_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - local_hose.last_busno); - - cpci_hose.first_busno = local_hose.last_busno + 1; - cpci_hose.last_busno = 0xff; - - /* System memory space */ - pci_set_region(cpci_hose.regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHYS, - PCI_MEMORY_MAXSIZE, - PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region(cpci_hose.regions + 1, - BRIDGE_CPCI_MEM_BUS, - BRIDGE_CPCI_MEM_PHYS, - BRIDGE_CPCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(cpci_hose.regions + 2, - BRIDGE_CPCI_IO_BUS, - BRIDGE_CPCI_IO_PHYS, - BRIDGE_CPCI_IO_SIZE, - PCI_REGION_IO); - - cpci_hose.region_count = 3; - - pci_setup_indirect(&cpci_hose, - BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGADDR, - BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGDATA); - - pci_register_hose(&cpci_hose); - - /* Initialize PCI64 bus registers */ - pci_hose_write_config_byte(&cpci_hose, - PCI_BDF(cpci_hose.first_busno,0,0), - CPC710_BUS_NUMBER, - cpci_hose.first_busno); - pci_hose_write_config_byte(&cpci_hose, - PCI_BDF(cpci_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - cpci_hose.last_busno); - - cpci_hose.last_busno = pci_hose_scan(&cpci_hose); - - /* Write out correct max subordinate bus number for cpci hose */ - pci_hose_write_config_byte(&cpci_hose, - PCI_BDF(cpci_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - cpci_hose.last_busno); -} diff --git a/board/pcippc2/cpc710_pci.h b/board/pcippc2/cpc710_pci.h deleted file mode 100644 index 24d0db6..0000000 --- a/board/pcippc2/cpc710_pci.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _CPC710_PCI_H_ -#define _CPC710_PCI_H_ - -#define PCI_MEMORY_PHYS 0x00000000 -#define PCI_MEMORY_BUS 0x80000000 -#define PCI_MEMORY_MAXSIZE 0x20000000 - -#define BRIDGE_CPCI_PHYS 0xff500000 -#define BRIDGE_CPCI_MEM_SIZE 0x08000000 -#define BRIDGE_CPCI_MEM_PHYS 0xf0000000 -#define BRIDGE_CPCI_MEM_BUS 0x00000000 -#define BRIDGE_CPCI_IO_SIZE 0x02000000 -#define BRIDGE_CPCI_IO_PHYS 0xfc000000 -#define BRIDGE_CPCI_IO_BUS 0x00000000 - -#define BRIDGE_LOCAL_PHYS 0xff400000 -#define BRIDGE_LOCAL_MEM_SIZE 0x04000000 -#define BRIDGE_LOCAL_MEM_PHYS 0xf8000000 -#define BRIDGE_LOCAL_MEM_BUS 0x40000000 -#define BRIDGE_LOCAL_IO_SIZE 0x01000000 -#define BRIDGE_LOCAL_IO_PHYS 0xfe000000 -#define BRIDGE_LOCAL_IO_BUS 0x04000000 - -#define BRIDGE(r, x) (BRIDGE_##r##_PHYS + HW_BRIDGE_##x) - -#define PCI_LATENCY_TIMER_VAL 0xff - -#endif diff --git a/board/pcippc2/flash.c b/board/pcippc2/flash.c deleted file mode 100644 index 8c01415..0000000 --- a/board/pcippc2/flash.c +++ /dev/null @@ -1,573 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -static ulong flash_get_size (ulong addr, flash_info_t *info); -static int flash_get_offsets (ulong base, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_reset (ulong addr); - -unsigned long flash_init (void) -{ - unsigned int i; - unsigned long flash_size = 0; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE && \ - CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - } else { - puts ("Warning: the BOOT Flash is not initialised !"); - } - - return flash_size; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (ulong addr, flash_info_t *info) -{ - short i; - uchar value; - - /* Write auto select command: read Manufacturer ID */ - out8(addr + 0x0555, 0xAA); - iobarrier_rw(); - out8(addr + 0x02AA, 0x55); - iobarrier_rw(); - out8(addr + 0x0555, 0x90); - iobarrier_rw(); - - value = in8(addr); - iobarrier_rw(); - - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value); - - switch (value | (value << 16)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - flash_reset (addr); - return 0; - } - - value = in8(addr + 1); /* device ID */ - iobarrier_rw(); - - DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value); - - switch ((ulong)value) { - case AMD_ID_F040B: - DEBUGF("Am29F040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - case AMD_ID_LV040B: - DEBUGF("Am29LV040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - case AMD_ID_LV400T: - DEBUGF("Am29LV400T\n"); - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - DEBUGF("Am29LV400B\n"); - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - DEBUGF("Am29LV800T\n"); - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - DEBUGF("Am29LV400B\n"); - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - DEBUGF("Am29LV160T\n"); - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - DEBUGF("Am29LV160B\n"); - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV320T: - DEBUGF("Am29LV320T\n"); - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 - /* Has the same ID as AMD_ID_LV320T, to be fixed */ - case AMD_ID_LV320B: - DEBUGF("Am29LV320B\n"); - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case AMD_ID_LV033C: - DEBUGF("Am29LV033C\n"); - info->flash_id += FLASH_AM033C; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16Mb */ - - case STM_ID_F040B: - DEBUGF("M29F040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - default: - info->flash_id = FLASH_UNKNOWN; - flash_reset (addr); - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - if (! flash_get_offsets (addr, info)) { - flash_reset (addr); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - value = in8(info->start[i] + 2); - iobarrier_rw(); - info->protect[i] = (value & 1) != 0; - } - - /* - * Reset bank to read mode - */ - flash_reset (addr); - - return (info->size); -} - -static int flash_get_offsets (ulong base, flash_info_t *info) -{ - unsigned int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + i * info->size / - info->sector_count; - } - break; - default: - return 0; - } - - return 1; -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile ulong addr = info->start[0]; - int flag, prot, sect, l_sect; - ulong start, now, last; - - if (s_first < 0 || s_first > s_last) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0x80); - iobarrier_rw(); - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = info->start[sect]; - out8(addr, 0x30); - iobarrier_rw(); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = info->start[l_sect]; - - DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT); - - while ((in8(addr) & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - flash_reset (info->start[0]); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - iobarrier_rw(); - } - -DONE: - /* reset to read mode */ - flash_reset (info->start[0]); - - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile ulong addr = info->start[0]; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((in32(dest) & data) != data) { - return (2); - } - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *)&data; - int flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0xA0); - iobarrier_rw(); - out8(dest+i, data_ch[i]); - iobarrier_rw(); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flash_reset (addr); - return (1); - } - iobarrier_rw(); - } - } - - flash_reset (addr); - return (0); -} - -/* - * Reset bank to read mode - */ -static void flash_reset (ulong addr) -{ - out8(addr, 0xF0); /* reset bank */ - iobarrier_rw(); -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_STM: printf ("SGS THOMSON "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size % 0x100000 == 0) { - printf (" Size: %ld MB in %d Sectors\n", - info->size / 0x100000, info->sector_count); - } else if (info->size % 0x400 == 0) { - printf (" Size: %ld KB in %d Sectors\n", - info->size / 0x400, info->sector_count); - } else { - printf (" Size: %ld B in %d Sectors\n", - info->size, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} diff --git a/board/pcippc2/fpga_serial.c b/board/pcippc2/fpga_serial.c deleted file mode 100644 index 579bfc7..0000000 --- a/board/pcippc2/fpga_serial.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "fpga_serial.h" -#include "hardware.h" -#include "pcippc2.h" - - /* 8 data, 1 stop, no parity - */ -#define LCRVAL 0x03 - /* RTS/DTR - */ -#define MCRVAL 0x03 - /* Clear & enable FIFOs - */ -#define FCRVAL 0x07 - -static void fpga_serial_wait (void); -static void fpga_serial_print (char c); - -void fpga_serial_init (int baudrate) -{ - int clock_divisor = 115200 / baudrate; - - out8 (FPGA (INT, SERIAL_CONFIG), 0x24); - iobarrier_rw (); - - fpga_serial_wait (); - - out8 (UART (IER), 0); - out8 (UART (LCR), LCRVAL | 0x80); - iobarrier_rw (); - out8 (UART (DLL), clock_divisor & 0xff); - out8 (UART (DLM), clock_divisor >> 8); - iobarrier_rw (); - out8 (UART (LCR), LCRVAL); - iobarrier_rw (); - out8 (UART (MCR), MCRVAL); - out8 (UART (FCR), FCRVAL); - iobarrier_rw (); -} - -void fpga_serial_putc (char c) -{ - if (c) { - fpga_serial_print (c); - } -} - -void fpga_serial_puts (const char *s) -{ - while (*s) { - fpga_serial_print (*s++); - } -} - -int fpga_serial_getc (void) -{ - while ((in8 (UART (LSR)) & 0x01) == 0); - - return in8 (UART (RBR)); -} - -int fpga_serial_tstc (void) -{ - return (in8 (UART (LSR)) & 0x01) != 0; -} - -void fpga_serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int clock_divisor = 115200 / gd->baudrate; - - fpga_serial_wait (); - - out8 (UART (LCR), LCRVAL | 0x80); - iobarrier_rw (); - out8 (UART (DLL), clock_divisor & 0xff); - out8 (UART (DLM), clock_divisor >> 8); - iobarrier_rw (); - out8 (UART (LCR), LCRVAL); - iobarrier_rw (); -} - -static void fpga_serial_wait (void) -{ - while ((in8 (UART (LSR)) & 0x40) == 0); -} - -static void fpga_serial_print (char c) -{ - if (c == '\n') { - while ((in8 (UART (LSR)) & 0x20) == 0); - - out8 (UART (THR), '\r'); - iobarrier_rw (); - } - - while ((in8 (UART (LSR)) & 0x20) == 0); - - out8 (UART (THR), c); - iobarrier_rw (); - - if (c == '\n') { - fpga_serial_wait (); - } -} diff --git a/board/pcippc2/fpga_serial.h b/board/pcippc2/fpga_serial.h deleted file mode 100644 index 92c9cdd..0000000 --- a/board/pcippc2/fpga_serial.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _FPGA_SERIAL_H_ -#define _FPGA_SERIAL_H_ - -extern void fpga_serial_init (int); -extern void fpga_serial_putc (char); -extern void fpga_serial_puts (const char *); -extern int fpga_serial_getc (void); -extern int fpga_serial_tstc (void); -extern void fpga_serial_setbrg (void); - -#endif diff --git a/board/pcippc2/hardware.h b/board/pcippc2/hardware.h deleted file mode 100644 index 489929d..0000000 --- a/board/pcippc2/hardware.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _HARDWARE_H_ -#define _HARDWARE_H_ - -#include "cpc710.h" -#include "cpc710_pci.h" -#include "pcippc2_fpga.h" -#include "ns16550.h" - -#define REG(r, x) (HW_PHYS_##r + HW_##r##_##x) - - /* Address map: - * - * 0x00000000-0x20000000 SDRAM - * 0x40000000-0x00008000 Init RAM in the CPU DCache - * 0xf0000000-0xf8000000 CPCI MEM - * 0xf8000000-0xfc000000 Local PCI MEM - * 0xfc000000-0xfe000000 CPCI I/O - * 0xfe000000-0xff000000 Local PCI I/O - * 0xff000000-0xff201000 System configuration space - * 0xff400000-0xff500000 Local PCI bridge space - * 0xff500000-0xff600000 CPCI bridge space - * 0xfff00000-0xfff80000 Boot Flash - */ - -#endif diff --git a/board/pcippc2/i2c.c b/board/pcippc2/i2c.c deleted file mode 100644 index 36b1d0f..0000000 --- a/board/pcippc2/i2c.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "hardware.h" -#include "i2c.h" - -static void i2c_start (void); -static void i2c_stop (void); -static int i2c_write (u8 data); -static void i2c_read (u8 * data); - -static inline void i2c_port_start (void); -static inline void i2c_clock (unsigned int val); -static inline void i2c_data (unsigned int val); -static inline unsigned int - i2c_in (void); -static inline void i2c_write_bit (unsigned int val); -static inline unsigned int - i2c_read_bit (void); - -static inline void i2c_udelay (unsigned int time); - -int i2c_read_byte ( - u8 * data, - u8 dev, - u8 offset) -{ - int err = 0; - - i2c_start(); - - err = ! i2c_write(dev); - - if (! err) - { - err = ! i2c_write(offset); - } - - if (! err) - { - i2c_start(); - } - - if (! err) - { - err = ! i2c_write(dev | 0x01); - } - - if (! err) - { - i2c_read(data); - } - - i2c_stop(); - - return ! err; -} - -static inline void i2c_udelay ( - unsigned int time) -{ - int v; - - asm volatile("mtdec %0" : : "r" (time * ((CFG_BUS_CLK / 4) / 1000000))); - - do - { - asm volatile("isync; mfdec %0" : "=r" (v)); - } while (v >= 0); -} - - /* Low-level hardware access - */ - -#define BIT_GPDATA 0x80000000 -#define BIT_GPCLK 0x40000000 - -static inline void i2c_port_start (void) -{ - out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~(BIT_GPCLK | BIT_GPDATA)); - out32(REG(CPC0, GPOUT), in32(REG(CPC0, GPOUT)) & ~(BIT_GPCLK | BIT_GPDATA)); - iobarrier_rw(); - - i2c_udelay(1); -} - -static inline void i2c_clock ( - unsigned int val) -{ - if (val) - { - out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPCLK); - } - else - { - out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPCLK); - } - - iobarrier_rw(); - - i2c_udelay(1); -} - -static inline void i2c_data ( - unsigned int val) -{ - if (val) - { - out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPDATA); - } - else - { - out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPDATA); - } - - iobarrier_rw(); - - i2c_udelay(1); -} - -static inline unsigned int i2c_in (void) -{ - unsigned int val = ((in32(REG(CPC0, GPIN)) & BIT_GPDATA) != 0)?1:0; - - iobarrier_rw(); - - return val; -} - - - /* Protocol implementation - */ - -static inline void i2c_write_bit ( - unsigned int val) -{ - i2c_data(val); - i2c_udelay(10); - i2c_clock(1); - i2c_udelay(10); - i2c_clock(0); - i2c_udelay(10); -} - -static inline unsigned int i2c_read_bit (void) -{ - unsigned int val; - - i2c_data(1); - i2c_udelay(10); - - i2c_clock(1); - i2c_udelay(10); - - val = i2c_in(); - - i2c_clock(0); - i2c_udelay(10); - - return val; -} - -unsigned int i2c_reset (void) -{ - unsigned int val; - int i; - - i2c_port_start(); - - i=0; - do { - i2c_udelay(10); - i2c_clock(0); - i2c_udelay(10); - i2c_clock(1); - i2c_udelay(10); - val = i2c_in(); - i++; - } while ((i<9)&&(val==0)); - return (val); -} - - -static void i2c_start (void) -{ - i2c_data(1); - i2c_clock(1); - i2c_udelay(10); - i2c_data(0); - i2c_udelay(10); - i2c_clock(0); - i2c_udelay(10); -} - -static void i2c_stop (void) -{ - i2c_data(0); - i2c_udelay(10); - i2c_clock(1); - i2c_udelay(10); - i2c_data(1); - i2c_udelay(10); -} - -static int i2c_write ( - u8 data) -{ - unsigned int i; - - for (i = 0; i < 8; i++) - { - i2c_write_bit(data >> 7); - data <<= 1; - } - - return i2c_read_bit() == 0; -} - -static void i2c_read ( - u8 * data) -{ - unsigned int i; - u8 val = 0; - - for (i = 0; i < 8; i++) - { - val <<= 1; - val |= i2c_read_bit(); - } - - *data = val; - i2c_write_bit(1); /* NoAck */ -} diff --git a/board/pcippc2/i2c.h b/board/pcippc2/i2c.h deleted file mode 100644 index 1224b42..0000000 --- a/board/pcippc2/i2c.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _I2C_H_ -#define _I2C_H_ - -#include - -extern int i2c_read_byte (u8 * data, - u8 dev, - u8 offset); - -extern unsigned int i2c_reset (void); - - -#endif diff --git a/board/pcippc2/ns16550.h b/board/pcippc2/ns16550.h deleted file mode 100644 index 7023f13..0000000 --- a/board/pcippc2/ns16550.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _NS16550_H_ -#define _NS16550_H_ - -#define NS16550_RBR 0x00 -#define NS16550_IER 0x01 -#define NS16550_FCR 0x02 -#define NS16550_LCR 0x03 -#define NS16550_MCR 0x04 -#define NS16550_LSR 0x05 -#define NS16550_MSR 0x06 -#define NS16550_SCR 0x07 - -#define NS16550_THR NS16550_RBR -#define NS16550_IIR NS16550_FCR -#define NS16550_DLL NS16550_RBR -#define NS16550_DLM NS16550_IER - -#endif diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c deleted file mode 100644 index 231b505..0000000 --- a/board/pcippc2/pcippc2.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "pcippc2.h" -#include "sconsole.h" -#include "fpga_serial.h" - -#if defined(CONFIG_WATCHDOG) - -static int pcippc2_wdt_init_done = 0; - -void pcippc2_wdt_init (void); - -#endif - - /* Check board identity - */ -int checkboard (void) -{ -#ifdef CONFIG_PCIPPC2 - puts ("Board: Gespac PCIPPC-2\n"); -#else - puts ("Board: Gespac PCIPPC-6\n"); -#endif - return 0; -} - - /* RAM size is stored in CPC0_RGBAN1 - */ -u32 pcippc2_sdram_size (void) -{ - return in32 (REG (CPC0, RGBAN1)); -} - -long initdram (int board_type) -{ - return cpc710_ram_init (); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - out32 (REG (CPC0, SPOR), 0); - iobarrier_rw (); - while (1); - /* notreached */ - return (-1); -} - -int board_early_init_f (void) -{ - out32 (REG (CPC0, RSTR), 0xC0000000); - iobarrier_rw (); - - out32 (REG (CPC0, RSTR), 0xF0000000); - iobarrier_rw (); - - out32 (REG (CPC0, UCTL), 0x00F80000); - - out32 (REG (CPC0, SIOC0), 0x30000000); - - out32 (REG (CPC0, ABCNTL), 0x00000000); - - out32 (REG (CPC0, SESR), 0x00000000); - out32 (REG (CPC0, SEAR), 0x00000000); - - /* Detect IBM Avignon CPC710 Revision */ - if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P) - out32 (REG (CPC0, PGCHP), 0xA0000040); - else - out32 (REG (CPC0, PGCHP), 0x80800040); - - - out32 (REG (CPC0, ATAS), 0x709C2508); - - iobarrier_rw (); - - return 0; -} - -void after_reloc (ulong dest_addr) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Jump to the main U-Boot board init code - */ - board_init_r ((gd_t *)gd, dest_addr); -} - -int misc_init_r (void) -{ - pcippc2_fpga_init (); - - pcippc2_cpci3264_init (); - -#if defined(CONFIG_WATCHDOG) - pcippc2_wdt_init (); -#endif - - fpga_serial_init (sconsole_get_baudrate ()); - - sconsole_putc = fpga_serial_putc; - sconsole_puts = fpga_serial_puts; - sconsole_getc = fpga_serial_getc; - sconsole_tstc = fpga_serial_tstc; - sconsole_setbrg = fpga_serial_setbrg; - - sconsole_flush (); - return (0); -} - -void pci_init_board (void) -{ - cpc710_pci_init (); - - /* FPGA requires no retry timeouts to be enabled - */ - cpc710_pci_enable_timeout (); -} - -void doc_init (void) -{ - doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC); -} - -void pcippc2_cpci3264_init (void) -{ - pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0); - - if (bdf == -1) - { - puts("Unable to find FPGA !\n"); - hang(); - } - - if((in32(pcippc2_fpga0_phys + HW_FPGA0_BOARD) & 0x01000000) == 0x01000000) - /* 32-bits Compact PCI bus - LSB bit */ - { - iobarrier_rw(); - out32(BRIDGE(CPCI, PCIDG), 0x40000000); /* 32-bits bridge, Pipeline */ - iobarrier_rw(); - } -} - -#if defined(CONFIG_WATCHDOG) - -void pcippc2_wdt_init (void) -{ - out16r (FPGA (WDT, PROG), 0xffff); - out8 (FPGA (WDT, CTRL), 0x1); - - pcippc2_wdt_init_done = 1; -} - -void pcippc2_wdt_done (void) -{ - out8 (FPGA (WDT, CTRL), 0x0); - - pcippc2_wdt_init_done = 0; -} - -void pcippc2_wdt_reset (void) -{ - if (pcippc2_wdt_init_done == 1) - out8 (FPGA (WDT, REFRESH), 0x56); -} - -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - pcippc2_wdt_reset (); - if (re_enable) - enable_interrupts (); -} - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) -int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - switch (argc) { - case 1: - printf ("Watchdog timer status is %s\n", - pcippc2_wdt_init_done == 1 ? "on" : "off"); - - return 0; - case 2: - if (!strcmp(argv[1],"on")) { - pcippc2_wdt_init(); - printf("Watchdog timer now is on\n"); - - return 0; - - } else if (!strcmp(argv[1],"off")) { - pcippc2_wdt_done(); - printf("Watchdog timer now is off\n"); - - return 0; - - } else - break; - default: - break; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD( - wd, 2, 1, do_wd, - "wd - check and set watchdog\n", - "on - switch watchDog on\n" - "wd off - switch watchdog off\n" - "wd - print current status\n" -); - -#endif /* CFG_CMD_BSP */ -#endif /* CONFIG_WATCHDOG */ diff --git a/board/pcippc2/pcippc2.h b/board/pcippc2/pcippc2.h deleted file mode 100644 index 3820bbe..0000000 --- a/board/pcippc2/pcippc2.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PCIPPC2_H_ -#define _PCIPPC2_H_ - -#include -#include - -#include "hardware.h" - -#define FPGA(r, p) (pcippc2_fpga0_phys + HW_FPGA0_##r##_##p) -#define UART(r) (pcippc2_fpga0_phys + HW_FPGA0_UART1 + NS16550_##r * 4) -#define RTC(r) (pcippc2_fpga1_phys + HW_FPGA1_RTC + r) - -extern u32 pcippc2_fpga0_phys; -extern u32 pcippc2_fpga1_phys; - -extern u32 pcippc2_sdram_size (void); - -extern void pcippc2_fpga_init (void); - -extern void pcippc2_cpci3264_init (void); - -extern void cpc710_pci_init (void); -extern void cpc710_pci_enable_timeout (void); - -extern unsigned long - cpc710_ram_init (void); - -#endif diff --git a/board/pcippc2/pcippc2_fpga.c b/board/pcippc2/pcippc2_fpga.c deleted file mode 100644 index 7f6739d..0000000 --- a/board/pcippc2/pcippc2_fpga.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "pci.h" - -#include "hardware.h" -#include "pcippc2.h" - -u32 pcippc2_fpga0_phys; -u32 pcippc2_fpga1_phys; - -void pcippc2_fpga_init (void) -{ - pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0); - unsigned int addr; - u16 cmd; - - if (bdf == -1) - { - puts("Unable to find FPGA !\n"); - hang(); - } - - pci_read_config_word(bdf, PCI_COMMAND, &cmd); - if ((cmd & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)) != (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)) - { - puts("FPGA is not configured !\n"); - hang(); - } - - pci_read_config_dword(bdf, PCI_BASE_ADDRESS_0, &addr); - if (addr & 0x1) - { - /* IO space - */ - pcippc2_fpga0_phys = pci_io_to_phys(bdf, addr & 0xfffffffc); - } - else - { - /* Memory space - */ - pcippc2_fpga0_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0); - } - - pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr); - if (addr & 0x1) - { - /* IO space - */ - pcippc2_fpga1_phys = pci_io_to_phys(bdf, addr & 0xfffffffc); - } - else - { - /* Memory space - */ - pcippc2_fpga1_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0); - } - - /* Interrupts are not used - */ - out32(FPGA(INT, INTR_MASK), 0xffffffff); - iobarrier_rw(); -} diff --git a/board/pcippc2/pcippc2_fpga.h b/board/pcippc2/pcippc2_fpga.h deleted file mode 100644 index 850c331..0000000 --- a/board/pcippc2/pcippc2_fpga.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PCIPPC2_FPGA_H_ -#define _PCIPPC2_FPGA_H_ - -#define FPGA_VENDOR_ID 0x1310 -#define FPGA_DEVICE_ID 0x000d - -#define HW_FPGA0_INT 0x0000 -#define HW_FPGA0_BOARD 0x0060 -#define HW_FPGA0_UART1 0x0080 -#define HW_FPGA0_UART2 0x0100 -#define HW_FPGA0_RTC 0x2000 -#define HW_FPGA0_DOC 0x4000 -#define HW_FPGA1_RTC 0x0000 -#define HW_FPGA1_DOC 0x4000 - -#define HW_FPGA0_INT_INTR_MASK 0x30 -#define HW_FPGA0_INT_INTR_STATUS 0x34 -#define HW_FPGA0_INT_INTR_EOI 0x40 -#define HW_FPGA0_INT_SERIAL_CONFIG 0x5c - -#define HW_FPGA0_WDT_CTRL 0x44 -#define HW_FPGA0_WDT_PROG 0x48 -#define HW_FPGA0_WDT_VAL 0x4c -#define HW_FPGA0_WDT_REFRESH 0x50 - -#endif diff --git a/board/pcippc2/sconsole.c b/board/pcippc2/sconsole.c deleted file mode 100644 index a9f2b29..0000000 --- a/board/pcippc2/sconsole.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include "sconsole.h" - -void (*sconsole_putc) (char) = 0; -void (*sconsole_puts) (const char *) = 0; -int (*sconsole_getc) (void) = 0; -int (*sconsole_tstc) (void) = 0; -void (*sconsole_setbrg) (void) = 0; - -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - sb->pos = 0; - sb->size = 0; - sb->baud = gd->baudrate; - sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t); - - return (0); -} - -void serial_putc (char c) -{ - if (sconsole_putc) { - (*sconsole_putc) (c); - } else { - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - if (c) { - sb->data[sb->pos++] = c; - if (sb->pos == sb->max_size) { - sb->pos = 0; - } - if (sb->size < sb->max_size) { - sb->size++; - } - } - } -} - -void serial_puts (const char *s) -{ - if (sconsole_puts) { - (*sconsole_puts) (s); - } else { - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - while (*s) { - sb->data[sb->pos++] = *s++; - if (sb->pos == sb->max_size) { - sb->pos = 0; - } - if (sb->size < sb->max_size) { - sb->size++; - } - } - } -} - -int serial_getc (void) -{ - if (sconsole_getc) { - return (*sconsole_getc) (); - } else { - return 0; - } -} - -int serial_tstc (void) -{ - if (sconsole_tstc) { - return (*sconsole_tstc) (); - } else { - return 0; - } -} - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - if (sconsole_setbrg) { - (*sconsole_setbrg) (); - } else { - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - sb->baud = gd->baudrate; - } -} - -int sconsole_get_baudrate (void) -{ - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - return sb->baud; -} - -void sconsole_flush (void) -{ - if (sconsole_putc) { - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - unsigned int end = sb->pos < sb->size - ? sb->pos + sb->max_size - sb->size - : sb->pos - sb->size; - - while (sb->size) { - (*sconsole_putc) (sb->data[end++]); - if (end == sb->max_size) { - end = 0; - } - sb->size--; - } - } -} diff --git a/board/pcippc2/sconsole.h b/board/pcippc2/sconsole.h deleted file mode 100644 index 40fd75b..0000000 --- a/board/pcippc2/sconsole.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SCONSOLE_H_ -#define _SCONSOLE_H_ - -#include - -typedef struct sconsole_buffer_s -{ - unsigned long size; - unsigned long max_size; - unsigned long pos; - unsigned long baud; - char data [1]; -} sconsole_buffer_t; - -#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR) - -extern void (* sconsole_putc) (char); -extern void (* sconsole_puts) (const char *); -extern int (* sconsole_getc) (void); -extern int (* sconsole_tstc) (void); -extern void (* sconsole_setbrg) (void); - -extern void sconsole_flush (void); -extern int sconsole_get_baudrate (void); - -#endif diff --git a/board/pcippc2/u-boot.lds b/board/pcippc2/u-boot.lds deleted file mode 100644 index 5c8cd5a..0000000 --- a/board/pcippc2/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/74xx_7xx/start.o (.text) - -/* store the environment in a seperate sector in the boot flash */ -/* . = env_offset; */ -/* common/environment.o(.text) */ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/pleb2/Makefile b/board/pleb2/Makefile deleted file mode 100644 index 95d9170..0000000 --- a/board/pleb2/Makefile +++ /dev/null @@ -1,48 +0,0 @@ - -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := pleb2.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/pleb2/config.mk b/board/pleb2/config.mk deleted file mode 100644 index 6958a63..0000000 --- a/board/pleb2/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -TEXT_BASE = 0xa1F80000 -#TEXT_BASE = 0xa3080000 -#TEXT_BASE = 0 diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c deleted file mode 100644 index 97271d9..0000000 --- a/board/pleb2/flash.c +++ /dev/null @@ -1,814 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -/* environment.h defines the various CFG_ENV_... values in terms - * of whichever ones are given in the configuration file. - */ -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPWV * addr, flash_info_t * info); -static void flash_reset (flash_info_t * info); -static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data); -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -#ifdef CFG_FLASH_PROTECTION -static void flash_sync_real_protect (flash_info_t * info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size_b; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b; - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n", - size_b); - } - - /* Do this again (was done already in flast_get_size), just - * in case we move it when remap the FLASH. - */ - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#ifdef CFG_FLASH_PROTECTION - /* read the hardware protection status (if any) into the - * protection array in flash_info. - */ - flash_sync_real_protect (&flash_info[0]); -#endif - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_ADDR - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - -#ifdef CFG_ENV_ADDR_REDUND - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[0]); -#endif - - return (size_b); -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset (flash_info_t * info) -{ - FPWV *base = (FPWV *) (info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW) 0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof (FPW) / 2); - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set up sector start address table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sect_size); - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set up sector start address table (top boot sector type) */ - for (i = 0; i < info->sector_count - 3; i++) - info->start[i] = base + (i * sect_size); - i = info->sector_count - 1; - info->start[i--] = - base + (info->size - 0x00004000) * (sizeof (FPW) / 2); - info->start[i--] = - base + (info->size - 0x00006000) * (sizeof (FPW) / 2); - info->start[i--] = - base + (info->size - 0x00008000) * (sizeof (FPW) / 2); - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t * info) -{ - int i; - uchar *boottype; - uchar *bootletter; - uchar *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_BM: - printf ("BRIGHT MICRO "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - fmt = "29LV800B%s (8 Mbit, %s)\n"; - break; - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV * addr, flash_info_t * info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) - switch (addr[1]) { - - case (FPW) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MiB */ - - case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets ((ulong) addr, info); - - /* Put FLASH back in read mode */ - flash_reset (info); - - return (info->size); -} - -#ifdef CFG_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void flash_sync_real_protect (flash_info_t * info) -{ - FPWV *addr = (FPWV *) (info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW) 0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *) (info->start[i]); - info->protect[i] = - (sect[2] & (FPW) (0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - case FLASH_AM800T: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - reset_timer_masked (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - reset_timer_masked (); - last = 0; - - addr = (FPWV *) (info->start[sect]); - if (intel) { - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - } else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *) (info->start[0]); - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00800080; /* erase mode */ - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - *addr = (FPW) 0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = - get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - } - - flash_reset (info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1 * CFG_HZ) { /* every second */ - putc ('.'); - last = now; - } - } - - flash_reset (info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof (data), left -= sizeof (data) - bytes) { - - bytes = addr & (sizeof (data) - 1); - addr &= ~(sizeof (data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ -#ifdef CFG_LITTLE_ENDIAN - for (i = 0; i < sizeof (data); i++) { - data >>= 8; - if (i < bytes || i - bytes >= left) - data += (*((uchar *) addr + i)) << 24; - else - data += (*src++) << 24; - } -#else - for (i = 0; i < sizeof (data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } -#endif - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd (info, (FPWV *) addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel (info, (FPWV *) addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) -{ - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *) (info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - reset_timer_masked (); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) -{ - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - *dest = (FPW) 0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - reset_timer_masked (); - - while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW) 0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CFG_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset (info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset (info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/pleb2/lowlevel_init.S b/board/pleb2/lowlevel_init.S deleted file mode 100644 index add2c53..0000000 --- a/board/pleb2/lowlevel_init.S +++ /dev/null @@ -1,488 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - - /* Set up GPIO pins first */ - - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GRER0 - ldr r1, =CFG_GRER0_VAL - str r1, [r0] - - ldr r0, =GRER1 - ldr r1, =CFG_GRER1_VAL - str r1, [r0] - - ldr r0, =GRER2 - ldr r1, =CFG_GRER2_VAL - str r1, [r0] - - ldr r0, =GFER0 - ldr r1, =CFG_GFER0_VAL - str r1, [r0] - - ldr r0, =GFER1 - ldr r1, =CFG_GFER1_VAL - str r1, [r0] - - ldr r0, =GFER2 - ldr r1, =CFG_GFER2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - /* enable GPIO pins */ - ldr r0, =PSSR - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - - -/********************************************************************* - Initlialize Memory Controller - - See PXA250 Operating System Developer's Guide - - pause for 200 uSecs- allow internal clocks to settle - *Note: only need this if hard reset... doing it anyway for now -*/ - - @ Step 1 - @ ---- Wait 200 usec - ldr r3, =OSCR @ reset the OS Timer Count to zero - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - @ get memory controller base address - ldr r1, =MEMC_BASE - -@**************************************************************************** -@ Step 2 -@ - - @ Step 2a - @ write msc0, read back to ensure data latches - @ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] - - @ write msc1 - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - @ write msc2 - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - -@ Step 2b - @ write mecr - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - - @ write mcmem0 - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - - @ write mcmem1 - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - - @ write mcatt0 - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - - @ write mcatt1 - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - - @ write mcio0 - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - - @ write mcio1 - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - -@ Step 2c - @ fly-by-dma is defeatured on this part - @ write flycnfg - @ldr r2, =CFG_FLYCNFG_VAL - @str r2, [r1, #FLYCNFG_OFFSET] - -/* FIXME Does this sequence really make sense */ -#ifdef REDBOOT_WAY - @ Step 2d - @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL - - @ extract DRI field (we need a valid DRI field) - @ - ldr r2, =0xFFF - - @ valid DRI field in r3 - @ - and r3, r3, r2 - - @ get the reset state of MDREFR - @ - ldr r4, [r1, #MDREFR_OFFSET] - - @ clear the DRI field - @ - bic r4, r4, r2 - - @ insert the valid DRI field loaded above - @ - orr r4, r4, r3 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ *Note: preserve the mdrefr value in r4 * - -@**************************************************************************** -@ Step 3 -@ -@ NO SRAM - - mov pc, r10 - - -@**************************************************************************** -@ Step 4 -@ - - @ Assumes previous mdrefr value in r4, if not then read current mdrefr - - @ clear the free-running clock bits - @ (clear K0Free, K1Free, K2Free - @ - bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000) - - @ set K0RUN for CPLD clock - @ - orr r4, r4, #0x00002000 - - @ set K1RUN if bank 0 installed - @ - orr r4, r4, #0x00010000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - @ deassert SLFRSH - @ - bic r4, r4, #0x00400000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ assert E1PIN - @ - orr r4, r4, #0x00008000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - nop - nop -#else - @ Step 2d - @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ Step 4 - - @ set K0RUN for CPLD clock - @ - orr r4, r4, #0x00002000 - - @ set K1RUN for bank 0 - @ - orr r4, r4, #0x00010000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - @ deassert SLFRSH - @ - bic r4, r4, #0x00400000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ assert E1PIN - @ - orr r4, r4, #0x00008000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - nop - nop -#endif - - @ Step 4d - @ fetch platform value of mdcnfg - @ - ldr r2, =CFG_MDCNFG_VAL - - @ disable all sdram banks - @ - bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) - bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3) - - @ program banks 0/1 for bus width - @ - bic r2, r2, #MDCNFG_DWID0 @0=32-bit - - @ write initial value of mdcnfg, w/o enabling sdram banks - @ - str r2, [r1, #MDCNFG_OFFSET] - - @ Step 4e - @ pause for 200 uSecs - @ - ldr r3, =OSCR @ reset the OS Timer Count to zero - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty - 1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - /* Why is this here??? */ - mov r0, #0x78 @turn everything off - mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.) - - @ Step 4f - @ Access memory *not yet enabled* for CBR refresh cycles (8) - @ - CBR is generated for all banks - - ldr r2, =CFG_DRAM_BASE - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - - @ Step 4g - @get memory controller base address - @ - ldr r1, =MEMC_BASE - - @fetch current mdcnfg value - @ - ldr r3, [r1, #MDCNFG_OFFSET] - - @enable sdram bank 0 if installed (must do for any populated bank) - @ - orr r3, r3, #MDCNFG_DE0 - - @write back mdcnfg, enabling the sdram bank(s) - @ - str r3, [r1, #MDCNFG_OFFSET] - - @ Step 4h - @ write mdmrs - @ - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - @ Done Memory Init - - /*SET_LED 6 */ - - @******************************************************************** - @ Disable (mask) all interrupts at the interrupt controller - @ - - @ clear the interrupt level register (use IRQ, not FIQ) - @ - mov r1, #0 - ldr r2, =ICLR - str r1, [r2] - - @ Set interrupt mask register - @ - ldr r1, =CFG_ICMR_VAL - ldr r2, =ICMR - str r1, [r2] - - @ ******************************************************************** - @ Disable the peripheral clocks, and set the core clock - @ - - @ Turn Off ALL on-chip peripheral clocks for re-configuration - @ - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - @ set core clocks - @ - ldr r2, =CFG_CCCR_VAL - ldr r1, =CCCR - str r2, [r1] - - #ifdef ENABLE32KHZ - @ enable the 32Khz oscillator for RTC and PowerManager - @ - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - @ NOTE: spin here until OSCC.OOK get set, - @ meaning the PLL has settled. - @ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#endif - - @ Turn on needed clocks - @ - ldr r1, =CKEN - ldr r2, =CFG_CKEN_VAL - str r2, [r1] - - /*SET_LED 7 */ - -/* Is this needed???? */ -#define NODEBUG -#ifdef NODEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ - -#endif - - mov pc, r10 - -@ End lowlevel_init diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c deleted file mode 100644 index ce9245c..0000000 --- a/board/pleb2/pleb2.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of Lubbock-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PLEB2; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; - - return 0; -} diff --git a/board/pleb2/u-boot.lds b/board/pleb2/u-boot.lds deleted file mode 100644 index f010239..0000000 --- a/board/pleb2/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/pm520/Makefile b/board/pm520/Makefile deleted file mode 100644 index 8cf0d7d..0000000 --- a/board/pm520/Makefile +++ /dev/null @@ -1,47 +0,0 @@ - -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/pm520/config.mk b/board/pm520/config.mk deleted file mode 100644 index ad689f3..0000000 --- a/board/pm520/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# PM520 board -# - -TEXT_BASE = 0xfff00000 -# TEXT_BASE = 0x00100000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/pm520/flash.c b/board/pm520/flash.c deleted file mode 100644 index 3868221..0000000 --- a/board/pm520/flash.c +++ /dev/null @@ -1,655 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) (x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) (x) -#endif - -/* Intel-compatible flash ID */ -#define INTEL_COMPAT 0x00890089 -#define INTEL_ALT 0x00B000B0 - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x00100010 -#define INTEL_ERASE 0x00200020 -#define INTEL_CLEAR 0x00500050 -#define INTEL_LOCKBIT 0x00600060 -#define INTEL_PROTECT 0x00010001 -#define INTEL_STATUS 0x00700070 -#define INTEL_READID 0x00900090 -#define INTEL_CONFIRM 0x00D000D0 -#define INTEL_RESET 0xFFFFFFFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x00800080 -#define INTEL_OK 0x00800080 - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); -static void flash_sync_real_protect (flash_info_t * info); -static unsigned char intel_sector_protected (flash_info_t *info, ushort sector); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - extern void flash_preinit(void); - extern void flash_afterinit(ulong, ulong); - ulong flashbase = CFG_FLASH_BASE; - - flash_preinit(); - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - memset(&flash_info[i], 0, sizeof(flash_info_t)); - flash_get_size ((FPW *) flashbase, &flash_info[i]); - flash_get_offsets (flash_info[i].start[0], &flash_info[i]); - break; - default: - panic ("configured to many flash banks!\n"); - break; - } - size += flash_info[i].size; - - /* get the h/w and s/w protection status in sync */ - flash_sync_real_protect(&flash_info[i]); - } - - /* Protect monitor and environment sectors - */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#ifndef CONFIG_BOOT_ROM - flash_protect ( FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0] ); -#endif -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); -#endif - - flash_afterinit(flash_info[0].start[0], flash_info[0].size); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - - case FLASH_28F320J3A: - printf ("28F320J3A\n"); - break; - - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - udelay(100); - - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - info->start[0] = CFG_FLASH_BASE; - break; /* => 32 MB */ - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - info->start[0] = CFG_FLASH_BASE + 0x01000000; - break; /* => 16 MB */ - - case (FPW) INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x800000; - info->start[0] = CFG_FLASH_BASE + 0x01800000; - break; /* => 8 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* - * This function gets the u-boot flash sector protection status - * (flash_info_t.protect[]) in sync with the sector protection - * status stored in hardware. - */ -static void flash_sync_real_protect (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - - case FLASH_28F128J3A: - case FLASH_28F640J3A: - case FLASH_28F320J3A: - for (i = 0; i < info->sector_count; ++i) { - info->protect[i] = intel_sector_protected(info, i); - } - break; - default: - /* no h/w protect support */ - break; - } -} - - -/* - * checks if "sector" in bank "info" is protected. Should work on intel - * strata flash chips 28FxxxJ3x in 8-bit mode. - * Returns 1 if sector is protected (or timed-out while trying to read - * protection status), 0 if it is not. - */ -static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) -{ - FPWV *addr; - FPWV *lock_conf_addr; - ulong start; - unsigned char ret; - - /* - * first, wait for the WSM to be finished. The rationale for - * waiting for the WSM to become idle for at most - * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy - * because of: (1) erase, (2) program or (3) lock bit - * configuration. So we just wait for the longest timeout of - * the (1)-(3), i.e. the erase timeout. - */ - - /* wait at least 35ns (W12) before issuing Read Status Register */ - udelay(1); - addr = (FPWV *) info->start[sector]; - *addr = (FPW) INTEL_STATUS; - - start = get_timer (0); - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { - *addr = (FPW) INTEL_RESET; /* restore read mode */ - printf("WSM busy too long, can't get prot status\n"); - return 1; - } - } - - /* issue the Read Identifier Codes command */ - *addr = (FPW) INTEL_READID; - - /* wait at least 35ns (W12) before reading */ - udelay(1); - - /* Intel example code uses offset of 2 for 16 bit flash */ - lock_conf_addr = (FPWV *) info->start[sector] + 2; - ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0; - - /* put flash back in read mode */ - *addr = (FPW) INTEL_RESET; - - return ret; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect (flash_info_t *info, long sector, int prot) -{ - ulong start; - int i; - int rc = 0; - vu_long *addr = (vu_long *)(info->start[sector]); - int flag = disable_interrupts(); - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } - else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - start = get_timer(0); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - * WARNING: code below re-locks sectors only for one bank (info). - * This causes problems on boards where several banks share - * the same chip, as sectors in othere banks will be unlocked - * but not re-locked. It works fine on pm520 though, as there - * is only one chip and one bank. - */ - if (!prot) - { - for (i = 0; i < info->sector_count; i++) - { - if (info->protect[i]) - { - start = get_timer(0); - addr = (vu_long *)(info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) - { - if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) - { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - } - } - /* - * get the s/w sector protection status in sync with the h/w, - * in case something went wrong during the re-locking. - */ - flash_sync_real_protect(info); /* resets flash to read mode */ - } - - if (flag) - enable_interrupts(); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h deleted file mode 100644 index f650faa..0000000 --- a/board/pm520/mt46v16m16-75.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 1 /* is DDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h deleted file mode 100644 index ffdf039..0000000 --- a/board/pm520/mt48lc16m16a2-75.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 0 /* is SDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c deleted file mode 100644 index d4cc5cb..0000000 --- a/board/pm520/pm520.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -#include "mt48lc16m16a2-75.h" -#endif - -#ifndef CFG_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. - */ - -#if defined(CONFIG_MPC5200) -long int initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CFG_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CFG_RAMBOOT */ - - return dramsize + dramsize2; -} - -#elif defined(CONFIG_MGT5100) - -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CFG_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CFG_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - -int checkboard (void) -{ -#if defined(CONFIG_MPC5200) - puts ("Board: MicroSys PM520 \n"); -#elif defined(CONFIG_MGT5100) - puts ("Board: MicroSys PM510 \n"); -#endif - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -void flash_afterinit(ulong start, ulong size) -{ -#if defined(CONFIG_BOOT_ROM) - /* adjust mapping */ - *(vu_long *)MPC5XXX_CS1_START = - START_REG(start); - *(vu_long *)MPC5XXX_CS1_STOP = - STOP_REG(start, size); -#else - /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(start); - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(start, size); -#endif -} - - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - /* adjust flash start */ - gd->bd->bi_flashstart = flash_info[0].start[0]; - return (0); -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - -} -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -extern void doc_probe (ulong physadr); -void doc_init (void) -{ - doc_probe (CFG_DOC_BASE); -} -#endif diff --git a/board/pm520/u-boot.lds b/board/pm520/u-boot.lds deleted file mode 100644 index 3cc2968..0000000 --- a/board/pm520/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/pm826/Makefile b/board/pm826/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/pm826/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/pm826/config.mk b/board/pm826/config.mk deleted file mode 100644 index c93bad9..0000000 --- a/board/pm826/config.mk +++ /dev/null @@ -1,37 +0,0 @@ -# -# (C) Copyright 2001-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MicroSys PM826 board: -# - - -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -## Standard: boot 64-bit flash -TEXT_BASE = 0xFF000000 - -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/pm826/flash.c b/board/pm826/flash.c deleted file mode 100644 index fee07cf..0000000 --- a/board/pm826/flash.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for Intel devices - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (volatile unsigned long *baseaddr, - flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - info->sector_count = info->size = 0; - info->flash_id = FLASH_UNKNOWN; - - /* Write query command sequence and test FLASH answer - */ - baseaddr[0] = 0x00980098; - baseaddr[1] = 0x00980098; - - flashtest_h = baseaddr[0]; /* manufacturer ID */ - flashtest_l = baseaddr[1]; - - if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) - return (0); /* no or unknown flash */ - - flashtest_h = baseaddr[2]; /* device ID */ - flashtest_l = baseaddr[3]; - - if (flashtest_h != flashtest_l) - return (0); - - switch (flashtest_h) { - case INTEL_ID_28F160C3B: - info->flash_id = FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F160F3B: - info->flash_id = FLASH_28F160F3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F640C3B: - info->flash_id = FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ - break; - default: - return (0); /* no or unknown flash */ - } - - info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ - - if (info->flash_id & FLASH_BTYPE) { - volatile unsigned long *tmp = baseaddr; - - /* set up sector start adress table (bottom sector type) - * AND unlock the sectors (if our chip is 160C3 or 640C3) - */ - for (i = 0; i < info->sector_count; i++) { - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { - tmp[0] = 0x00600060; - tmp[1] = 0x00600060; - tmp[0] = 0x00D000D0; - tmp[1] = 0x00D000D0; - } - info->start[i] = (uint) tmp; - tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ - } - } - - memset (info->protect, 0, info->sector_count); - - baseaddr[0] = 0x00FF00FF; - baseaddr[1] = 0x00FF00FF; - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known - */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* protect monitor and environment sectors - */ - -#ifndef CONFIG_BOOT_ROM - /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE - * but we shouldn't protect it. - */ - -# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] - ); -# endif -#endif /* CONFIG_BOOT_ROM */ - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x89: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf ("28F160C3B (16 M, bottom sector)\n"); - break; - case FLASH_28F160F3B: - printf ("28F160F3B (16 M, bottom sector)\n"); - break; - case FLASH_28F640C3B: - printf ("28F640C3B (64 M, bottom sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors - */ - for (sect = s_first; sect <= s_last; sect++) { - volatile ulong *addr = - (volatile unsigned long *) info->start[sect]; - - start = get_timer (0); - last = start; - if (info->protect[sect] == 0) { - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - /* Erase the block - */ - addr[0] = 0x00200020; - addr[1] = 0x00200020; - addr[0] = 0x00D000D0; - addr[1] = 0x00D000D0; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - last = start; - while ((addr[0] & 0x00800080) != 0x00800080 || - (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout (erase suspended!)\n"); - /* Suspend erase - */ - addr[0] = 0x00B000B0; - addr[1] = 0x00B000B0; - goto DONE; - } - /* show that we're waiting - */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { - printf ("*** ERROR: erase failed!\n"); - goto DONE; - } - } - /* Clear status register and reset to read mode - */ - addr[0] = 0x00500050; - addr[1] = 0x00500050; - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - - printf (" done\n"); - -DONE: - return 0; -} - -static int write_word (flash_info_t *, volatile unsigned long *, ulong); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong v; - int i, l, cc = cnt, res = 0; - - - for (v=0; cc > 0; addr += 4, cc -= 4 - l) { - l = (addr & 3); - addr &= ~3; - - for (i = 0; i < 4; i++) { - v = (v << 8) + (i < l || i - l >= cc ? - *((unsigned char *) addr + i) : *src++); - } - - if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) - break; - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, volatile unsigned long *addr, - ulong data) -{ - int flag, res = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - *addr = 0x00400040; - *addr = data; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - /* Suspend program - */ - *addr = 0x00B000B0; - res = 1; - goto OUT; - } - } - - if (*addr & 0x00220022) { - printf ("*** ERROR: program failed!\n"); - res = 1; - } - -OUT: - /* Clear status register and reset to read mode - */ - *addr = 0x00500050; - *addr = 0x00FF00FF; - - return (res); -} diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c deleted file mode 100644 index 7514cd7..0000000 --- a/board/pm826/pm826.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */ -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) -#ifdef CONFIG_ETHER_ON_FCC2 -#error "SCC1 conflicts with FCC2" -#endif - /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ -#else - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */ -#endif - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */ - /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */ - /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */ - /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SOFT_I2C) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - puts ("Board: PM826\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - - *orx_ptr = orx | ~(size - 1); - - return (size); -} - - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CFG_RAMBOOT - ulong size8, size9; -#endif - ulong psize = 32 * 1024 * 1024; - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - -#ifndef CFG_RAMBOOT - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, - (uchar *) CFG_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - printf ("(60x:8COL) "); - } -#endif - return (psize); -} - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -extern void doc_probe (ulong physadr); -void doc_init (void) -{ - doc_probe (CFG_DOC_BASE); -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif diff --git a/board/pm826/u-boot.lds b/board/pm826/u-boot.lds deleted file mode 100644 index 05f29c6..0000000 --- a/board/pm826/u-boot.lds +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - common/environment.o(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/pm828/Makefile b/board/pm828/Makefile deleted file mode 100644 index b9ef0c0..0000000 --- a/board/pm828/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/pm828/config.mk b/board/pm828/config.mk deleted file mode 100644 index e894af7..0000000 --- a/board/pm828/config.mk +++ /dev/null @@ -1,37 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MicroSys PM828 board: -# - - -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -## Standard: boot 64-bit flash -TEXT_BASE = 0x40000000 - -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/pm828/flash.c b/board/pm828/flash.c deleted file mode 100644 index 1f21b3e..0000000 --- a/board/pm828/flash.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for Intel devices - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (volatile unsigned long *baseaddr, - flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - info->sector_count = info->size = 0; - info->flash_id = FLASH_UNKNOWN; - - /* Write query command sequence and test FLASH answer - */ - baseaddr[0] = 0x00980098; - baseaddr[1] = 0x00980098; - - flashtest_h = baseaddr[0]; /* manufacturer ID */ - flashtest_l = baseaddr[1]; - - if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT) - return (0); /* no or unknown flash */ - - flashtest_h = baseaddr[2]; /* device ID */ - flashtest_l = baseaddr[3]; - - if (flashtest_h != flashtest_l) - return (0); - - switch (flashtest_h) { - case INTEL_ID_28F160C3B: - info->flash_id = FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F160F3B: - info->flash_id = FLASH_28F160F3B; - info->sector_count = 39; - info->size = 0x00800000; /* 4 * 2 MB = 8 MB */ - break; - case INTEL_ID_28F640C3B: - info->flash_id = FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x02000000; /* 16 * 2 MB = 32 MB */ - break; - default: - return (0); /* no or unknown flash */ - } - - info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */ - - if (info->flash_id & FLASH_BTYPE) { - volatile unsigned long *tmp = baseaddr; - - /* set up sector start adress table (bottom sector type) - * AND unlock the sectors (if our chip is 160C3 or 640c3) - */ - for (i = 0; i < info->sector_count; i++) { - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) { - tmp[0] = 0x00600060; - tmp[1] = 0x00600060; - tmp[0] = 0x00D000D0; - tmp[1] = 0x00D000D0; - } - info->start[i] = (uint) tmp; - tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */ - } - } - - memset (info->protect, 0, info->sector_count); - - baseaddr[0] = 0x00FF00FF; - baseaddr[1] = 0x00FF00FF; - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known - */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* protect monitor and environment sectors - */ - -#ifndef CONFIG_BOOT_ROM - /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE - * but we shouldn't protect it. - */ - -# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] - ); -# endif -#endif /* CONFIG_BOOT_ROM */ - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x89: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf ("28F160C3B (16 M, bottom sector)\n"); - break; - case FLASH_28F160F3B: - printf ("28F160F3B (16 M, bottom sector)\n"); - break; - case FLASH_28F640C3B: - printf ("28F640C3B (64 M, bottom sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors - */ - for (sect = s_first; sect <= s_last; sect++) { - volatile ulong *addr = - (volatile unsigned long *) info->start[sect]; - - start = get_timer (0); - last = start; - if (info->protect[sect] == 0) { - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - /* Erase the block - */ - addr[0] = 0x00200020; - addr[1] = 0x00200020; - addr[0] = 0x00D000D0; - addr[1] = 0x00D000D0; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms - */ - udelay (1000); - - last = start; - while ((addr[0] & 0x00800080) != 0x00800080 || - (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout (erase suspended!)\n"); - /* Suspend erase - */ - addr[0] = 0x00B000B0; - addr[1] = 0x00B000B0; - goto DONE; - } - /* show that we're waiting - */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - if (addr[0] & 0x00220022 || addr[1] & 0x00220022) { - printf ("*** ERROR: erase failed!\n"); - goto DONE; - } - } - /* Clear status register and reset to read mode - */ - addr[0] = 0x00500050; - addr[1] = 0x00500050; - addr[0] = 0x00FF00FF; - addr[1] = 0x00FF00FF; - } - - printf (" done\n"); - -DONE: - return 0; -} - -static int write_word (flash_info_t *, volatile unsigned long *, ulong); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong v; - int i, l, cc = cnt, res = 0; - - - for (v=0; cc > 0; addr += 4, cc -= 4 - l) { - l = (addr & 3); - addr &= ~3; - - for (i = 0; i < 4; i++) { - v = (v << 8) + (i < l || i - l >= cc ? - *((unsigned char *) addr + i) : *src++); - } - - if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0) - break; - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, volatile unsigned long *addr, - ulong data) -{ - int flag, res = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here - */ - flag = disable_interrupts (); - - *addr = 0x00400040; - *addr = data; - - /* re-enable interrupts if necessary - */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - /* Suspend program - */ - *addr = 0x00B000B0; - res = 1; - goto OUT; - } - } - - if (*addr & 0x00220022) { - printf ("*** ERROR: program failed!\n"); - res = 1; - } - -OUT: - /* Clear status register and reset to read mode - */ - *addr = 0x00500050; - *addr = 0x00FF00FF; - - return (res); -} diff --git a/board/pm828/pm828.c b/board/pm828/pm828.c deleted file mode 100644 index 3193274..0000000 --- a/board/pm828/pm828.c +++ /dev/null @@ -1,363 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */ -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) -#ifdef CONFIG_ETHER_ON_FCC2 -#error "SCC1 conflicts with FCC2" -#endif - /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ -#else - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */ -#endif - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ - /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */ - /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */ - /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */ - /* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */ -#if defined(CONFIG_SOFT_I2C) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - puts ("Board: PM828\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile ulong cnt, val; - volatile ulong *addr; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - int i; - ulong save[32]; /* to make test non-destructive */ - ulong maxsize; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - /* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - i = 0; - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = (volatile ulong *) base + cnt; /* pointer arith! */ - save[i++] = *addr; - *addr = ~cnt; - } - - addr = (volatile ulong *) base; - save[i] = *addr; - *addr = 0; - - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *) base + cnt; /* pointer arith! */ - val = *addr; - *addr = save[--i]; - if (val != ~cnt) { - /* Write the actual size to ORx - */ - *orx_ptr = orx | ~(cnt * sizeof (long) - 1); - return (cnt * sizeof (long)); - } - } - return (maxsize); -} - - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CFG_RAMBOOT - ulong size8, size9; -#endif - ulong psize = 32 * 1024 * 1024; - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - -#ifndef CFG_RAMBOOT - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, - (uchar *) CFG_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL) "); - } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - printf ("(60x:8COL) "); - } -#endif - return (psize); -} - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -extern void doc_probe (ulong physadr); -void doc_init (void) -{ - doc_probe (CFG_DOC_BASE); -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif diff --git a/board/pm828/u-boot.lds b/board/pm828/u-boot.lds deleted file mode 100644 index 928c1cf..0000000 --- a/board/pm828/u-boot.lds +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - common/environment.o(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/pm854/Makefile b/board/pm854/Makefile deleted file mode 100644 index 7828166..0000000 --- a/board/pm854/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2001-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o -SOBJS := init.o -#SOBJS := - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/pm854/config.mk b/board/pm854/config.mk deleted file mode 100644 index 7d58d6e..0000000 --- a/board/pm854/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright 2004 Freescale Semiconductor. -# Modified by Xianghua Xiao, X.Xiao@motorola.com -# (C) Copyright 2002,Motorola Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# pm854 board -# default CCARBAR is at 0xff700000 -# assume U-Boot is less than 0.5MB -# -TEXT_BASE = 0xfff80000 - -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1 -PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/pm854/init.S b/board/pm854/init.S deleted file mode 100644 index ade5d6e..0000000 --- a/board/pm854/init.S +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, sharen, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M FLASH (8,16,32 or 64 MB) - * Out of reset this entry is only 4K. - */ - .long TLB1_MAS0(1, 0, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long TLB1_MAS0(1, 5, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long TLB1_MAS0(1, 6, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) -#endif - - entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c deleted file mode 100644 index 94c492f..0000000 --- a/board/pm854/pm854.c +++ /dev/null @@ -1,296 +0,0 @@ - /* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include - -#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -extern long int spd_sdram(void); - -void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void); - - -int board_early_init_f (void) -{ -#if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; - - pci->peer &= 0xffffffdf; /* disable master abort */ -#endif - - return 0; -} - -int checkboard (void) -{ - puts("Board: MicroSys PM854\n"); - -#ifdef CONFIG_PCI - printf(" PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf(" PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init(); - - return 0; -} - - -long int -initdram(int board_type) -{ - long dram_size = 0; - extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur= &immap->im_gur; - int i,x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) - { - gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; idevdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); - x++; - } - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_DDR_ECC) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - puts(" DDR: "); - return dram_size; -} - - -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr(); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) -{ - #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CFG_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CFG_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_pm854_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_pm854_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} diff --git a/board/pm854/u-boot.lds b/board/pm854/u-boot.lds deleted file mode 100644 index fbfc65a..0000000 --- a/board/pm854/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2002,2003, Motorola,Inc. - * Xianghua Xiao, X.Xiao@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - board/pm854/init.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc85xx/start.o (.text) - board/pm854/init.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/pm856/Makefile b/board/pm856/Makefile deleted file mode 100644 index 5d8ea34..0000000 --- a/board/pm856/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o -SOBJS := init.o -#SOBJS := - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/pm856/config.mk b/board/pm856/config.mk deleted file mode 100644 index 1f98b33..0000000 --- a/board/pm856/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright 2004 Freescale Semiconductor. -# Modified by Xianghua Xiao, X.Xiao@motorola.com -# (C) Copyright 2002,2003 Motorola Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# PM856 board -# default CCARBAR is at 0xff700000 -# assume U-Boot is less than 0.5MB -# -TEXT_BASE = 0xfff80000 - -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1 -PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/pm856/init.S b/board/pm856/init.S deleted file mode 100644 index ade5d6e..0000000 --- a/board/pm856/init.S +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, sharen, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M FLASH (8,16,32 or 64 MB) - * Out of reset this entry is only 4K. - */ - .long TLB1_MAS0(1, 0, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long TLB1_MAS0(1, 5, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long TLB1_MAS0(1, 6, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) -#endif - - entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c deleted file mode 100644 index 5044708..0000000 --- a/board/pm856/pm856.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -extern long int spd_sdram(void); - -void local_bus_init(void); -long int fixed_sdram(void); - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - - -int board_early_init_f (void) -{ - return 0; -} - -void reset_phy (void) -{ -} - - -int checkboard (void) -{ - puts("Board: MicroSys PM856\n"); - -#ifdef CONFIG_PCI - printf(" PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf(" PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init(); - - return 0; -} - - -long int -initdram(int board_type) -{ - long dram_size = 0; - extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur= &immap->im_gur; - int i,x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) - { - gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; idevdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); - x++; - } - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_DDR_ECC) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - puts(" DDR: "); - return dram_size; -} - - -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr(); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) -{ - #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CFG_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CFG_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} diff --git a/board/pm856/u-boot.lds b/board/pm856/u-boot.lds deleted file mode 100644 index e946a8e..0000000 --- a/board/pm856/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2005 Wolfgang Denk - * (C) Copyright 2002,2003, Motorola,Inc. - * Xianghua Xiao, X.Xiao@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - board/pm856/init.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc85xx/start.o (.text) - board/pm856/init.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/pn62/Makefile b/board/pn62/Makefile deleted file mode 100644 index e85d4fd..0000000 --- a/board/pn62/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o cmd_pn62.o misc.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c deleted file mode 100644 index 3ea068d..0000000 --- a/board/pn62/cmd_pn62.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include "pn62.h" - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -extern int do_bootm (cmd_tbl_t *, int, int, char *[]); - -/* - * Command led: controls the various LEDs 0..11 on the PN62 card. - */ -int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int number, function; - - if (argc != 3) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - number = simple_strtoul(argv[1], NULL, 10); - if (number > PN62_LED_MAX) - return 1; - function = simple_strtoul(argv[2], NULL, 16); - set_led (number, function); - return 0; -} -U_BOOT_CMD( - led , 3, 1, do_led, - "led - set LED 0..11 on the PN62 board\n", - "i fun\n" - " - set 'i'th LED to function 'fun'\n" -); - -/* - * Command loadpci: loads a image over PCI. - */ -#define CMD_MOVE_WINDOW 0x1 -#define CMD_BOOT_IMAGE 0x2 - -int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - char *s; - ulong addr = 0, count = 0; - u32 off; - int cmd, rcode = 0; - - /* pre-set load_addr */ - if ((s = getenv("loadaddr")) != NULL) { - addr = simple_strtoul(s, NULL, 16); - } - - switch (argc) { - case 1: - break; - case 2: - addr = simple_strtoul(argv[1], NULL, 16); - break; - default: - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - printf ("## Ready for image download ...\n"); - - show_startup_phase(12); - - while (1) { - /* Alive indicator */ - i2155x_write_scrapad(BOOT_PROTO, BOOT_PROTO_READY); - - /* Toggle status LEDs */ - cmd = (count / 200) % 4; /* downscale */ - set_led(4, cmd == 0 ? LED_1 : LED_0); - set_led(5, cmd == 1 ? LED_1 : LED_0); - set_led(6, cmd == 2 ? LED_1 : LED_0); - set_led(7, cmd == 3 ? LED_1 : LED_0); - udelay(1000); - count++; - - cmd = i2155x_read_scrapad(BOOT_CMD); - - if (cmd == BOOT_CMD_MOVE) { - off = i2155x_read_scrapad(BOOT_DATA); - off += addr; - i2155x_set_bar_base(3, off); - printf ("## BAR3 Addr moved = 0x%08x\n", off); - i2155x_write_scrapad(BOOT_CMD, ~cmd); - show_startup_phase(13); - } - else if (cmd == BOOT_CMD_BOOT) { - set_led(4, LED_1); - set_led(5, LED_1); - set_led(6, LED_1); - set_led(7, LED_1); - - i2155x_write_scrapad(BOOT_CMD, ~cmd); - show_startup_phase(14); - break; - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - printf("\nAbort\n"); - return 0; - } - - } - - /* Repoint to the default shared memory */ - i2155x_set_bar_base(3, PN62_SMEM_DEFAULT); - - load_addr = addr; - printf ("## Start Addr = 0x%08lx\n", addr); - - show_startup_phase(15); - - /* Loading ok, check if we should attempt an auto-start */ - if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) { - char *local_args[2]; - local_args[0] = argv[0]; - local_args[1] = NULL; - - printf ("Automatic boot of image at addr 0x%08lX ...\n", - load_addr); - rcode = do_bootm (cmdtp, 0, 1, local_args); - } - -#ifdef CONFIG_AUTOSCRIPT - if (load_addr) { - char *s; - - if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { - printf("Running autoscript at addr 0x%08lX ...\n", load_addr); - rcode = autoscript (bd, load_addr); - } - } -#endif - return rcode; -} - -U_BOOT_CMD( - loadpci, 2, 1, do_loadpci, - "loadpci - load binary file over PCI\n", - "[addr]\n" - " - load binary file over PCI to address 'addr'\n" -); - -#endif diff --git a/board/pn62/config.mk b/board/pn62/config.mk deleted file mode 100644 index a2b6f05..0000000 --- a/board/pn62/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# PN62 boards -# - -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/pn62/misc.c b/board/pn62/misc.c deleted file mode 100644 index dcb2db5..0000000 --- a/board/pn62/misc.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#include "pn62.h" - -typedef struct { - pci_dev_t devno; - volatile u32 *csr; - -} i2155x_t; - -static i2155x_t i2155x = { 0, NULL }; - -static struct pci_device_id i2155x_ids[] = { - { 0x1011, 0x0046 }, /* i21554 */ - { 0x8086, 0xb555 } /* i21555 */ -}; - -int i2155x_init(void) -{ - pci_dev_t devno; - u32 val; - int i; - - /* - * Find the Intel bridge. - */ - if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) { - printf("Error: Intel bridge 2155x not found!\n"); - return -1; - } - i2155x.devno = devno; - - /* - * Get auto-configured base address for CSR access. - */ - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val); - if (val & PCI_BASE_ADDRESS_SPACE_IO) { - val &= PCI_BASE_ADDRESS_IO_MASK; - i2155x.csr = (volatile u32 *)(_IO_BASE + val); - } else { - val &= PCI_BASE_ADDRESS_MEM_MASK; - i2155x.csr = (volatile u32 *)val; - } - - /* - * Translate downstream memory 2 (bar3) to base of shared memory. - */ - i2155x_set_bar_base(3, PN62_SMEM_DEFAULT); - - /* - * Enable memory space, I/O space and bus master bits - * in both Primary and Secondary command registers. - */ - val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO; - pci_write_config_word(devno, 0x44, val); - pci_write_config_word(devno, 0x04, val); - - /* - * Clear scratchpad registers. - */ - for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) { - i2155x_write_scrapad(i, 0x0); - } - - /* - * Set interrupt line for Linux. - */ - pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3); - - return 0; -} - -/* - * Access the Scratchpad registers 0..7 of the Intel bridge. - */ -void i2155x_write_scrapad(int idx, u32 val) -{ - if (idx >= 0 && idx < I2155X_SCRAPAD_MAX) - out_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx, val); - else - printf("i2155x_write_scrapad: invalid index\n"); -} - -u32 i2155x_read_scrapad(int idx) -{ - if (idx >= 0 && idx < I2155X_SCRAPAD_MAX) - return in_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx); - else - printf("i2155x_read_scrapad: invalid index\n"); - return -1; -} - -void i2155x_set_bar_base(int bar, u32 base) -{ - if (bar >= 2 && bar <= 4) { - pci_write_config_dword(i2155x.devno, - I2155X_BAR2_BASE + (bar - 2) * 4, - base); - } -} - -/* - * Read Vital Product Data (VPD) from the Serial EPROM attached - * to the Intel bridge. - */ -int i2155x_read_vpd(int offset, int size, unsigned char *data) -{ - int i, n; - u16 val16; - - for (i = 0; i < size; i++) { - pci_write_config_word(i2155x.devno, I2155X_VPD_ADDR, - offset + i - I2155X_VPD_START); - for (n = 10000; n > 0; n--) { - pci_read_config_word(i2155x.devno, I2155X_VPD_ADDR, &val16); - if ((val16 & 0x8000) != 0) /* wait for completion */ - break; - udelay(100); - } - if (n == 0) { - printf("i2155x_read_vpd: TIMEOUT\n"); - return -1; - } - - pci_read_config_byte(i2155x.devno, I2155X_VPD_DATA, &data[i]); - } - - return i; -} - -static struct pci_device_id am79c95x_ids [] = { - { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE }, - { } -}; - - -/* - * Initialize the AMD ethernet controllers. - */ -int am79c95x_init(void) -{ - pci_dev_t devno; - int i; - - /* - * Set interrupt line for Linux. - */ - for (i = 0; i < 2; i++) { - if ((devno = pci_find_devices(am79c95x_ids, i)) < 0) - break; - pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i); - } - if (i < 2) - printf("Error: Only %d AMD Ethernet Controller found!\n", i); - - return 0; -} - - -void set_led(unsigned int number, unsigned int function) -{ - volatile u8 *addr; - - if ((number >= 0) && (number < PN62_LED_MAX) && - (function >= 0) && (function <= LED_LAST_FUNCTION)) { - addr = (volatile u8 *)(PN62_LED_BASE + number * 8); - out_8(addr, function&0xff); - } -} - -/* - * Show fatal error indicated by Kinght Rider(tm) effect - * in LEDS 0-7. LEDS 8-11 contain 4 bit error code. - * Note: this function will not terminate. - */ -void fatal_error(unsigned int error_code) -{ - int i, d; - - for (i = 0; i < 12; i++) { - set_led(i, LED_0); - } - - /* - * Write error code. - */ - set_led(8, (error_code & 0x01) ? LED_1 : LED_0); - set_led(9, (error_code & 0x02) ? LED_1 : LED_0); - set_led(10, (error_code & 0x04) ? LED_1 : LED_0); - set_led(11, (error_code & 0x08) ? LED_1 : LED_0); - - /* - * Yay - Knight Rider effect! - */ - while(1) { - unsigned int delay = 2000; - - for (i = 0; i < 8; i++) { - set_led(i, LED_1); - for (d = 0; d < delay; d++); - set_led(i, LED_0); - } - - for (i = 7; i > 0; i--) { - set_led(i, LED_1); - for (d = 0; d < delay; d++); - set_led(i, LED_0); - } - } -} diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c deleted file mode 100644 index 377aaa8..0000000 --- a/board/pn62/pn62.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "pn62.h" - - -static int get_serial_number (char *string, int size); -static int get_mac_address (int id, u8 * mac, char *string, int size); - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress (int phase) -{ - /* - * Show phases of the bootm command on the front panel - * LEDs and the scratchpad register #3 as well. We use - * blinking LEDs for logical "1". - */ - if (phase > 0) { - set_led (8, (phase & 0x1) ? LED_SLOW_CLOCK : LED_0); - set_led (9, (phase & 0x2) ? LED_SLOW_CLOCK : LED_0); - set_led (10, (phase & 0x4) ? LED_SLOW_CLOCK : LED_0); - set_led (11, (phase & 0x8) ? LED_SLOW_CLOCK : LED_0); - } - i2155x_write_scrapad (BOOT_STATUS, phase); - if (phase < 0) - i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR); -} -#endif - -void show_startup_phase (int phase) -{ - /* - * Show the phase of U-Boot startup on the front panel - * LEDs and the scratchpad register #3 as well. - */ - if (phase > 0) { - set_led (8, (phase & 0x1) ? LED_1 : LED_0); - set_led (9, (phase & 0x2) ? LED_1 : LED_0); - set_led (10, (phase & 0x4) ? LED_1 : LED_0); - set_led (11, (phase & 0x8) ? LED_1 : LED_0); - } - i2155x_write_scrapad (BOOT_STATUS, phase); - if (phase < 0) - i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR); -} - -int checkboard (void) -{ - show_startup_phase (1); - puts ("Board: PN62\n"); - return 0; -} - -long int initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - show_startup_phase (2); - - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg (MEAR1); - emear1 = mpc824x_mpc107_getreg (EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg (MEAR1, mear1); - mpc824x_mpc107_setreg (EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices. We rely on auto-configuration. - */ -#ifndef CONFIG_PCI_PNP -#error "CONFIG_PCI_PNP is not defined, please correct!" -#endif - -struct pci_controller hose = { -}; - -void pci_init_board (void) -{ - show_startup_phase (4); - pci_mpc824x_init (&hose); - - show_startup_phase (5); - i2155x_init (); - show_startup_phase (6); - am79c95x_init (); - show_startup_phase (7); -} - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - char str[20]; - u8 mac[6]; - - show_startup_phase (8); - /* - * Get serial number and ethernet addresses if not already defined - * and update the board info structure and the environment. - */ - if (getenv ("serial#") == NULL && - get_serial_number (str, strlen (str)) > 0) { - setenv ("serial#", str); - } - show_startup_phase (9); - - if (getenv ("ethaddr") == NULL && - get_mac_address (0, mac, str, sizeof (str)) > 0) { - setenv ("ethaddr", str); - memcpy (gd->bd->bi_enetaddr, mac, 6); - } - show_startup_phase (10); - -#ifdef CONFIG_HAS_ETH1 - if (getenv ("eth1addr") == NULL && - get_mac_address (1, mac, str, sizeof (str)) > 0) { - setenv ("eth1addr", str); - memcpy (gd->bd->bi_enet1addr, mac, 6); - } -#endif /* CONFIG_HAS_ETH1 */ - show_startup_phase (11); - - /* Tell everybody that U-Boot is up and runnig */ - i2155x_write_scrapad (0, 0x12345678); - return (0); -} - -static int get_serial_number (char *string, int size) -{ - int i; - char c; - - if (size < I2155X_VPD_SN_SIZE) - size = I2155X_VPD_SN_SIZE; - for (i = 0; i < (size - 1); i++) { - i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c); - if (c == '\0') - break; - string[i] = c; - } - string[i] = '\0'; /* make sure it's terminated */ - - return i; -} - -static int get_mac_address (int id, u8 * mac, char *string, int size) -{ - if (size < 6 * 3) - return -1; - - i2155x_read_vpd (I2155X_VPD_MAC0_START + 6 * id, 6, mac); - return sprintf (string, "%02x:%02x:%02x:%02x:%02x:%02x", - mac[0], mac[1], mac[2], - mac[3], mac[4], mac[5]); -} diff --git a/board/pn62/pn62.h b/board/pn62/pn62.h deleted file mode 100644 index 7bda0ad..0000000 --- a/board/pn62/pn62.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PN62_H_ -#define _PN62_H_ - -/* - * Definitions for the Intel Bridge 21554 or 21555. - */ -#define I2155X_VPD_ADDR 0xe6 -#define I2155X_VPD_DATA 0xe8 - -#define I2155X_VPD_START 0x80 -#define I2155X_VPD_SN_START 0x80 -#define I2155X_VPD_SN_SIZE 0x10 -#define I2155X_VPD_MAC0_START 0x90 -#define I2155X_VPD_MAC1_START 0x96 - -#define I2155X_SCRAPAD_ADDR 0xa8 -#define I2155X_SCRAPAD_MAX 8 - -#define I2155X_BAR2_BASE 0x98 -#define I2155X_BAR3_BASE 0x9c -#define I2155X_BAR4_BASE 0xa0 - -#define I2155X_BAR2_SETUP 0xb0 -#define I2155X_BAR3_SETUP 0xb4 -#define I2155X_BAR4_SETUP 0xb8 - -/* - * Interrupt request numbers - */ -#define PN62_IRQ_HOST 0x0 -#define PN62_IRQ_PLX9054 0x1 -#define PN62_IRQ_ETH0 0x2 -#define PN62_IRQ_ETH1 0x3 -#define PN62_IRQ_COM1 0x4 -#define PN62_IRQ_COM2 0x4 - -/* - * Miscellaneous definitons. - */ -#define PN62_SMEM_DEFAULT 0x1f00000 - -/* - * Definitions for boot protocol using Scratchpad registers. - */ -#define BOOT_DONE 0 -#define BOOT_DONE_CLEAR 0x00dead00 -#define BOOT_DONE_ERROR 0xbad0dead -#define BOOT_DONE_U_BOOT 0x12345678 -#define BOOT_DONE_LINUX 0x87654321 -#define BOOT_CMD 1 -#define BOOT_CMD_MOVE 0x1 -#define BOOT_CMD_BOOT 0x2 -#define BOOT_DATA 2 -#define BOOT_PROTO 3 -#define BOOT_PROTO_READY 0x23456789 -#define BOOT_PROTO_CLEAR 0x00000000 -#define BOOT_STATUS 4 - -/* - * LED Definitions: - */ -#define PN62_LED_BASE 0xff800300 -#define PN62_LED_MAX 12 - -/* - * LED0 - 7 mounted on top of board, D1 - D8 - * LED8 - 11 upper four LEDs on the front panel of the board. - */ -#define LED_0 0x00 /* OFF */ -#define LED_1 0x01 /* ON */ -#define LED_SLOW_CLOCK 0x02 /* SLOW 1Hz ish */ -#define LED_nSLOW_CLOCK 0x03 /* inverse of above */ -#define LED_WATCHDOG_OUT 0x06 /* Reset Watchdog level */ -#define LED_WATCHDOG_CLOCK 0x07 /* clock to watchdog */ - -/* - * LED's currently setup in AMD79C973 device as the following: - * LED0 100Mbit - * LED1 LNKSE - * LED2 TX Activity - * LED3 RX Activity - */ -#define LED_E0_LED0 0x08 /* Ethernet Port 0 LED 0 */ -#define LED_E0_LED1 0x09 /* Ethernet Port 0 LED 1 */ -#define LED_E0_LED2 0x0A /* Ethernet Port 0 LED 2 */ -#define LED_E0_LED3 0x0B /* Ethernet Port 0 LED 3 */ -#define LED_E1_LED0 0x0C /* Ethernet Port 1 LED 0 */ -#define LED_E1_LED1 0x0D /* Ethernet Port 1 LED 1 */ -#define LED_E1_LED2 0x0E /* Ethernet Port 1 LED 2 */ -#define LED_E1_LED3 0x0F /* Ethernet Port 1 LED 3 */ -#define LED_STROBE0 0x10 /* Processor Strobe 0 */ -#define LED_STROBE1 0x11 /* Processor Strobe 1 */ -#define LED_STROBE2 0x12 /* Processor Strobe 2 */ -#define LED_STROBE3 0x13 /* Processor Strobe 3 */ -#define LED_STROBE4 0x14 /* Processor Strobe 4 */ -#define LED_STROBE5 0x15 /* Processor Strobe 5 */ -#define LED_STROBE6 0x16 /* Processor Strobe 6 */ -#define LED_STROBE7 0x17 /* Processor Strobe 7 */ -#define LED_HOST_STROBE0 0x18 /* Host strobe 0 */ -#define LED_HOST_STROBE1 0x19 /* Host strobe 1 */ -#define LED_HOST_STROBE2 0x1A /* Host strobe 2 */ -#define LED_HOST_STROBE3 0x1B /* Host strobe 3 */ -#define LED_HOST_STROBE4 0x1C /* Host strobe 4 */ -#define LED_HOST_STROBE5 0x1D /* Host strobe 5 */ -#define LED_HOST_STROBE6 0x1E /* Host strobe 6 */ -#define LED_HOST_STROBE7 0x1F /* Host strobe 7 */ -#define LED_MPC_INT0 0x20 /* MPC8240 INT 0 */ -#define LED_MPC_INT1 0x21 /* MPC8240 INT 1 */ -#define LED_MPC_INT2 0x22 /* MPC8240 INT 2 */ -#define LED_MPC_INT3 0x23 /* MPC8240 INT 3 */ -#define LED_MPC_INT4 0x24 /* MPC8240 INT 4 */ -#define LED_UART0_CS 0x25 /* UART 0 Chip Select */ -#define LED_UART1_CS 0x26 /* UART 1 Chip Select */ -#define LED_SRAM_CS 0x27 /* SRAM Chip Select */ -#define LED_SRAM_WR 0x28 /* SRAM WR Signal */ -#define LED_SRAM_RD 0x29 /* SRAM RD Signal */ -#define LED_MPC_RCS0 0x2A /* MPC8240 RCS0 Signal */ -#define LED_S_PCI_FRAME 0x2B /* Secondary PCI Frame Signal */ -#define LED_MPC_CS0 0x2C /* MPC8240 CS0 Signal */ -#define LED_HOST_INT 0x2D /* MPC8240 to Host Interrupt signal */ -#define LED_LAST_FUNCTION LED_HOST_INT /* last function */ - -/* - * Forward declarations - */ -int i2155x_init (void); -void i2155x_write_scrapad(int idx, u32 val); -u32 i2155x_read_scrapad (int idx); -void i2155x_set_bar_base (int bar, u32 addr); -int i2155x_read_vpd (int offset, int size, unsigned char *data); - -int am79c95x_init (void); - -void set_led (unsigned int number, unsigned int function); -void fatal_error (unsigned int error_code); -void show_startup_phase (int phase); - - -#endif /* _PN62_H_ */ diff --git a/board/pn62/u-boot.lds b/board/pn62/u-boot.lds deleted file mode 100644 index eaee3fd..0000000 --- a/board/pn62/u-boot.lds +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/ppmc8260/Makefile b/board/ppmc8260/Makefile deleted file mode 100644 index 351f4ee..0000000 --- a/board/ppmc8260/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := ppmc8260.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/ppmc8260/config.mk b/board/ppmc8260/config.mk deleted file mode 100644 index d06fcea..0000000 --- a/board/ppmc8260/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MBX8xx boards -# - -TEXT_BASE = 0xfe000000 -TEXT_END = 0xfe080000 -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c deleted file mode 100644 index 2b20c26..0000000 --- a/board/ppmc8260/ppmc8260.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_A1:L1TSYNC */ - /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* TDN_A1:L1RSYNC */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_A1:L1CLK0 */ - /* PB15 */ { 1, 0, 0, 1, 0, 1 }, /* /FETHRST */ - /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* FETHDIS */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_B1:L1CLK0 */ - /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TXD */ - /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RXD */ - /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1TSYNC */ - /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_D1:L1RSYNC */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* CLK4 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* CLK7 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 0, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[0] */ - /* PC14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[0] */ - /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[1] */ - /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[1] */ - /* PC11 */ { 1, 1, 0, 1, 0, 0 }, /* TDM_D1:L1CLK0 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:TxAddr[2]*/ - /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[2] */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DACK */ - /* PC2 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DONE */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA2:DREQ */ - /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DREQ */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */ - /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1:RxAddr[3] */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* TDM_C1:L1RSYNC */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TXD */ - /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RXD */ - /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1TSYNC */ - /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* TDM_B1:L1RSYNC*/ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1:TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:RXD */ - /* PD7 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1:SMSYN */ - /* PD6 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DACK */ - /* PD5 */ { 1, 0, 0, 1, 0, 0 }, /* IDMA1:DONE */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: Wind River PPMC8260\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0xff; - volatile uchar *ramaddr0 = (uchar *) (CFG_SDRAM0_BASE); - volatile uchar *ramaddr1 = (uchar *) (CFG_SDRAM1_BASE); - ulong psdmr = CFG_PSDMR; - volatile uchar *ramaddr2 = (uchar *) (CFG_SDRAM2_BASE); - ulong lsdmr = CFG_LSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - -#ifndef CFG_RAMBOOT - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr0++ = c; - *ramaddr1++ = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - *ramaddr0++ = c; - *ramaddr1++ = c; - } - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - ramaddr0 = (uchar *) (CFG_SDRAM0_BASE + 0x110); - ramaddr1 = (uchar *) (CFG_SDRAM1_BASE + 0x110); - *ramaddr0 = c; - *ramaddr1 = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr0 = c; - *ramaddr1 = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; - *ramaddr2++ = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - *ramaddr2++ = c; - } - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW; - *ramaddr2++ = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr2 = c; -#endif - - /* return total ram size */ - return ((CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE) * 1024 * 1024); -} - -#ifdef CONFIG_MISC_INIT_R -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ -#ifdef CFG_LED_BASE - uchar ds = *(unsigned char *) (CFG_LED_BASE + 1); - uchar ss; - uchar tmp[64]; - int res; - - if ((ds != 0) && (ds != 0xff)) { - res = getenv_r ("ethaddr", (char *)tmp, sizeof (tmp)); - if (res > 0) { - ss = ((ds >> 4) & 0x0f); - ss += ss < 0x0a ? '0' : ('a' - 10); - tmp[15] = ss; - - ss = (ds & 0x0f); - ss += ss < 0x0a ? '0' : ('a' - 10); - tmp[16] = ss; - - tmp[17] = '\0'; - setenv ("ethaddr", (char *)tmp); - /* set the led to show the address */ - *((unsigned char *) (CFG_LED_BASE + 1)) = ds; - } - } -#endif /* CFG_LED_BASE */ - return (0); -} -#endif /* CONFIG_MISC_INIT_R */ diff --git a/board/ppmc8260/strataflash.c b/board/ppmc8260/strataflash.c deleted file mode 100644 index f9abfac..0000000 --- a/board/ppmc8260/strataflash.c +++ /dev/null @@ -1,752 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;iportwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; iportwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; isector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/ppmc8260/u-boot.lds b/board/ppmc8260/u-boot.lds deleted file mode 100644 index 84d4b78..0000000 --- a/board/ppmc8260/u-boot.lds +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - common/environment.o(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/prodrive/p3p440/Makefile b/board/prodrive/p3p440/Makefile deleted file mode 100644 index 47116d3..0000000 --- a/board/prodrive/p3p440/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/prodrive/p3p440/config.mk b/board/prodrive/p3p440/config.mk deleted file mode 100644 index e5722dd..0000000 --- a/board/prodrive/p3p440/config.mk +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 - -ifeq ($(ramsym),1) -TEXT_BASE = 0x07FD0000 -else -TEXT_BASE = 0xFFFC0000 -endif - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 -endif diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S deleted file mode 100644 index ee6b706..0000000 --- a/board/prodrive/p3p440/init.S +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) - tlbtab_end diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c deleted file mode 100644 index d42a643..0000000 --- a/board/prodrive/p3p440/p3p440.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "p3p440.h" - -void set_led(int color) -{ - switch (color) { - case LED_OFF: - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED); - break; - - case LED_GREEN: - out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED); - break; - - case LED_RED: - out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN); - break; - - case LED_ORANGE: - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED); - break; - } -} - -static int is_monarch(void) -{ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_GPIO_RDY); - udelay(1000); - - if (in32(GPIO0_IR) & CFG_MONARCH_IO) - return 0; - else - return 1; -} - -static void wait_for_pci_ready(void) -{ - /* - * Configure EREADY_IO as input - */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO); - udelay(1000); - - for (;;) { - if (in32(GPIO0_IR) & CFG_EREADY_IO) - return; - } - -} - -int board_early_init_f(void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ - - /*-------------------------------------------------------------------- - * Setup pin multiplexing (GPIO/IRQ...) - *-------------------------------------------------------------------*/ - mtdcr(cpc0_gpio, 0x03F01F80); - - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN); - out32(GPIO0_OR, CFG_GPIO_RDY); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */ - mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - return 0; -} - -int checkboard(void) -{ - char *s = getenv("serial#"); - - printf("Board: P3P440"); - if (s != NULL) { - puts(", serial# "); - puts(s); - } - - if (is_monarch()) { - puts(", Monarch"); - } else { - puts(", None-Monarch"); - } - - putc('\n'); - - return (0); -} - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if only one FLASH bank is available - */ - if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { - mtebc(pb1cr, 0); /* disable cs */ - mtebc(pb1ap, 0); - mtebc(pb2cr, 0); /* disable cs */ - mtebc(pb2ap, 0); - mtebc(pb3cr, 0); /* disable cs */ - mtebc(pb3ap, 0); - } - - return 0; -} - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The P3P440 board is always configured as the host & requires the - * PCI arbiter to be disabled because it's an PMC module. - *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); - if (strap & 0x00100000) { - printf("PCI: CPC0_STRP1[PAE] set.\n"); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - DECLARE_GLOBAL_DATA_PTR; - - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0SA, 0); /* disable */ - out32r(PCIX0_PIM1SA, 0); /* disable */ - out32r(PCIX0_PIM2SA, 0); /* disable */ - out32r(PCIX0_EROMBA, 0); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE); - out32r(PCIX0_PIM0LAH, 0); - out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); - - out32r(PCIX0_BAR0, 0); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); - out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); - - out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - if (is_monarch()) { - wait_for_pci_ready(); - return 1; /* return 1 for host controller */ - } else { - return 0; /* return 0 for adapter controller */ - } -} -#endif /* defined(CONFIG_PCI) */ diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h deleted file mode 100644 index e4e87d1..0000000 --- a/board/prodrive/p3p440/p3p440.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __P3P440_H__ -#define __P3P440_H__ - -#define CFG_GPIO_RDY (0x80000000 >> 11) -#define CFG_MONARCH_IO (0x80000000 >> 18) -#define CFG_EREADY_IO (0x80000000 >> 20) -#define CFG_LED_GREEN (0x80000000 >> 21) -#define CFG_LED_RED (0x80000000 >> 22) - -#define LED_OFF 1 -#define LED_GREEN 2 -#define LED_RED 3 -#define LED_ORANGE 4 - -long int fixed_sdram(void); - -#endif /* __P3P440_H__ */ diff --git a/board/prodrive/p3p440/u-boot.lds b/board/prodrive/p3p440/u-boot.lds deleted file mode 100644 index 92bb740..0000000 --- a/board/prodrive/p3p440/u-boot.lds +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/prodrive/p3p440/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c deleted file mode 100644 index 4965743..0000000 --- a/board/psyent/common/AMDLV065D.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#if defined(CONFIG_NIOS) -#include -#else -#include -#endif - -#define SECTSZ (64 * 1024) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------*/ -unsigned long flash_init (void) -{ - int i; - unsigned long addr; - flash_info_t *fli = &flash_info[0]; - - fli->size = CFG_FLASH_SIZE; - fli->sector_count = CFG_MAX_FLASH_SECT; - fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; - - addr = CFG_FLASH_BASE; - for (i = 0; i < fli->sector_count; ++i) { - fli->start[i] = addr; - addr += SECTSZ; - fli->protect[i] = 1; - } - - return (CFG_FLASH_SIZE); -} -/*--------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i, k; - unsigned long size; - int erased; - volatile unsigned char *flash; - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - - /* Check if whole sector is erased */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned char *) CACHE_BYPASS(info->start[i]); - for (k = 0; k < size; k++) { - if (*flash++ != 0xff) { - erased = 0; - break; - } - } - - /* Print the info */ - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - CACHE_NO_BYPASS(info->start[i]), - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*-------------------------------------------------------------------*/ - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) - CACHE_BYPASS(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; - int prot, sect; - ulong start; - - /* Some sanity checking */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* It's ok to erase multiple sectors provided we don't delay more - * than 50 usec between cmds ... at which point the erase time-out - * occurs. So don't go and put printf() calls in the loop ... it - * won't be very helpful ;-) - */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) - CACHE_BYPASS((info->start[sect])); - *addr = 0xaa; - *addr = 0x55; - *addr = 0x80; - *addr = 0xaa; - *addr = 0x55; - *addr2 = 0x30; - /* Now just wait for 0xff & provide some user - * feedback while we wait. - */ - start = get_timer (0); - while (*addr2 != 0xff) { - udelay (1000 * 1000); - putc ('.'); - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { - printf ("timeout\n"); - return 1; - } - } - } - } - printf ("\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - - vu_char *cmd = (vu_char *) CACHE_BYPASS(info->start[0]); - vu_char *dst = (vu_char *) CACHE_BYPASS(addr); - unsigned char b; - ulong start; - - while (cnt) { - /* Check for sufficient erase */ - b = *src; - if ((*dst & b) != b) { - printf ("%02x : %02x\n", *dst, b); - return (2); - } - - *cmd = 0xaa; - *cmd = 0x55; - *cmd = 0xa0; - *dst = b; - - /* Verify write */ - start = get_timer (0); - while (*dst != b) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return 1; - } - } - dst++; - src++; - cnt--; - } - - return (0); -} diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile deleted file mode 100644 index 8e55c9b..0000000 --- a/board/psyent/pci5441/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2001-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -COMOBJS := ../common/AMDLV065D.o - -OBJS := $(BOARD).o $(COMOBJS) - -SOBJS = - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/psyent/pci5441/config.mk b/board/psyent/pci5441/config.mk deleted file mode 100644 index d72bcee..0000000 --- a/board/psyent/pci5441/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2004, Psyent Corporation -# Scott McNutt -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x018e0000 - -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/psyent/pci5441/pci5441.c b/board/psyent/pci5441/pci5441.c deleted file mode 100644 index ea80dd1..0000000 --- a/board/psyent/pci5441/pci5441.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("BOARD : Psyent PCI-5441\n"); - return 0; -} - -long int initdram (int board_type) -{ - return (0); -} diff --git a/board/psyent/pci5441/u-boot.lds b/board/psyent/pci5441/u-boot.lds deleted file mode 100644 index 8f9cd8f..0000000 --- a/board/psyent/pci5441/u-boot.lds +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -OUTPUT_FORMAT("elf32-littlenios2") -OUTPUT_ARCH(nios2) -ENTRY(_start) - -SECTIONS -{ - .text : - { - cpu/nios2/start.o (.text) - *(.text) - *(.text.*) - *(.gnu.linkonce.t*) - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r*) - } - . = ALIGN (4); - _etext = .; - PROVIDE (etext = .); - - /* CMD TABLE - sandwich this in between text and data so - * the initialization code relocates the command table as - * well -- admittedly, this is just pure laziness ;-) - */ - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : - { - *(.u_boot_cmd) - } - . = ALIGN(4); - __u_boot_cmd_end = .; - - /* INIT DATA sections - "Small" data (see the gcc -G option) - * is always gp-relative. Here we make all init data sections - * adjacent to simplify the startup code -- and provide - * the global pointer for gp-relative access. - */ - _data = .; - .data : - { - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - } - - . = ALIGN(16); - _gp = .; /* Global pointer addr */ - PROVIDE (gp = .); - - .sdata : - { - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - } - . = ALIGN(4); - - _edata = .; - PROVIDE (edata = .); - - /* UNINIT DATA - Small uninitialized data is first so it's - * adjacent to sdata and can be referenced via gp. The normal - * bss follows. We keep it adjacent to simplify init code. - */ - __bss_start = .; - .sbss : - { - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - } - . = ALIGN(4); - .bss : - { - *(.bss) - *(.bss.*) - *(.dynbss) - *(COMMON) - *(.scommon) - } - . = ALIGN(4); - _end = .; - PROVIDE (end = .); - - /* DEBUG -- symbol table, string table, etc. etc. - */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile deleted file mode 100644 index 5c1db03..0000000 --- a/board/psyent/pk1c20/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2001-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -COMOBJS := ../common/AMDLV065D.o - -OBJS := $(BOARD).o led.o $(COMOBJS) - -SOBJS = - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk deleted file mode 100644 index d72bcee..0000000 --- a/board/psyent/pk1c20/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2004, Psyent Corporation -# Scott McNutt -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x018e0000 - -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c deleted file mode 100644 index c175c9b..0000000 --- a/board/psyent/pk1c20/led.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* The LED port is configured as output only, so we - * must track the state manually. - */ -static led_id_t val = 0; - -void __led_init (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - pio->data = val; -} - -void __led_set (led_id_t mask, int state) -{ - nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); - - if (state == STATUS_LED_ON) - val &= ~mask; - else - val |= mask; - pio->data = val; -} - -void __led_toggle (led_id_t mask) -{ - nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR); - - val ^= mask; - pio->data = val; -} diff --git a/board/psyent/pk1c20/pk1c20.c b/board/psyent/pk1c20/pk1c20.c deleted file mode 100644 index 1924ae3..0000000 --- a/board/psyent/pk1c20/pk1c20.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("BOARD : Psyent PK-1C20\n"); - return 0; -} - -long int initdram (int board_type) -{ - return (0); -} diff --git a/board/psyent/pk1c20/u-boot.lds b/board/psyent/pk1c20/u-boot.lds deleted file mode 100644 index 8f9cd8f..0000000 --- a/board/psyent/pk1c20/u-boot.lds +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -OUTPUT_FORMAT("elf32-littlenios2") -OUTPUT_ARCH(nios2) -ENTRY(_start) - -SECTIONS -{ - .text : - { - cpu/nios2/start.o (.text) - *(.text) - *(.text.*) - *(.gnu.linkonce.t*) - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r*) - } - . = ALIGN (4); - _etext = .; - PROVIDE (etext = .); - - /* CMD TABLE - sandwich this in between text and data so - * the initialization code relocates the command table as - * well -- admittedly, this is just pure laziness ;-) - */ - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : - { - *(.u_boot_cmd) - } - . = ALIGN(4); - __u_boot_cmd_end = .; - - /* INIT DATA sections - "Small" data (see the gcc -G option) - * is always gp-relative. Here we make all init data sections - * adjacent to simplify the startup code -- and provide - * the global pointer for gp-relative access. - */ - _data = .; - .data : - { - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - } - - . = ALIGN(16); - _gp = .; /* Global pointer addr */ - PROVIDE (gp = .); - - .sdata : - { - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - } - . = ALIGN(4); - - _edata = .; - PROVIDE (edata = .); - - /* UNINIT DATA - Small uninitialized data is first so it's - * adjacent to sdata and can be referenced via gp. The normal - * bss follows. We keep it adjacent to simplify init code. - */ - __bss_start = .; - .sbss : - { - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - } - . = ALIGN(4); - .bss : - { - *(.bss) - *(.bss.*) - *(.dynbss) - *(COMMON) - *(.scommon) - } - . = ALIGN(4); - _end = .; - PROVIDE (end = .); - - /* DEBUG -- symbol table, string table, etc. etc. - */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/board/purple/Makefile b/board/purple/Makefile deleted file mode 100644 index b2f2fc0..0000000 --- a/board/purple/Makefile +++ /dev/null @@ -1,42 +0,0 @@ - -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o sconsole.o -SOBJS = lowlevel_init.o - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/purple/config.mk b/board/purple/config.mk deleted file mode 100644 index ea478ed..0000000 --- a/board/purple/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Purple board with MIPS 5Kc CPU core -# - -# ROM version -TEXT_BASE = 0xB0000000 - -# RAM version -#TEXT_BASE = 0x80100000 diff --git a/board/purple/flash.c b/board/purple/flash.c deleted file mode 100644 index 7522580..0000000 --- a/board/purple/flash.c +++ /dev/null @@ -1,596 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFFFFFF - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -#define FLASH29_REG_ADRS(reg) ((FPWV *)PHYS_FLASH_1 + (reg)) - -/* FLASH29 command register addresses */ - -#define FLASH29_REG_FIRST_CYCLE FLASH29_REG_ADRS (0x1555) -#define FLASH29_REG_SECOND_CYCLE FLASH29_REG_ADRS (0x2aaa) -#define FLASH29_REG_THIRD_CYCLE FLASH29_REG_ADRS (0x3555) -#define FLASH29_REG_FOURTH_CYCLE FLASH29_REG_ADRS (0x4555) -#define FLASH29_REG_FIFTH_CYCLE FLASH29_REG_ADRS (0x5aaa) -#define FLASH29_REG_SIXTH_CYCLE FLASH29_REG_ADRS (0x6555) - -/* FLASH29 command definitions */ - -#define FLASH29_CMD_FIRST 0xaaaaaaaa -#define FLASH29_CMD_SECOND 0x55555555 -#define FLASH29_CMD_FOURTH 0xaaaaaaaa -#define FLASH29_CMD_FIFTH 0x55555555 -#define FLASH29_CMD_SIXTH 0x10101010 - -#define FLASH29_CMD_SECTOR 0x30303030 -#define FLASH29_CMD_PROGRAM 0xa0a0a0a0 -#define FLASH29_CMD_CHIP_ERASE 0x80808080 -#define FLASH29_CMD_READ_RESET 0xf0f0f0f0 -#define FLASH29_CMD_AUTOSELECT 0x90909090 -#define FLASH29_CMD_READ 0x70707070 - -#define IN_RAM_CMD_READ 0x1 -#define IN_RAM_CMD_WRITE 0x2 - -#define FLASH_WRITE_CMD ((ulong)(flash_write_cmd) & 0x7)+0xbf008000 -#define FLASH_READ_CMD ((ulong)(flash_read_cmd) & 0x7)+0xbf008000 - -typedef void (*FUNCPTR_CP)(ulong *source, ulong *destination, ulong nlongs); -typedef void (*FUNCPTR_RD)(int cmd, FPWV * pFA, char * string, int strLen); -typedef void (*FUNCPTR_WR)(int cmd, FPWV * pFA, FPW value); - -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static int write_word(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); - -static void load_cmd(ulong cmd); -static ulong in_ram_cmd = 0; - - -/****************************************************************************** -* -* Don't change the program architecture -* This architecture assure the program -* can be relocated to scratch ram -*/ -static void flash_read_cmd(int cmd, FPWV * pFA, char * string, int strLen) -{ - int i,j; - FPW temp,temp1; - FPWV *str; - - str = (FPWV *)string; - - j= strLen/4; - - if(cmd == FLASH29_CMD_AUTOSELECT) - { - *(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST; - *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND; - *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_AUTOSELECT; - } - - if(cmd == FLASH29_CMD_READ) - { - i = 0; - while(i= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM160B) { - - int bootsect_size[4]; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size[0] = 0x00008000; - bootsect_size[1] = 0x00004000; - bootsect_size[2] = 0x00004000; - bootsect_size[3] = 0x00010000; - sect_size = 0x00020000; - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += i < 4 ? bootsect_size[i] : sect_size; - } - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base < info->start[0] + info->size) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - uchar *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160B: - fmt = "29LV160B%s (16 Mbit, %s)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - FUNCPTR_RD absEntry; - FPW retValue; - int flag; - - load_cmd(IN_RAM_CMD_READ); - absEntry = (FUNCPTR_RD)FLASH_READ_CMD; - - flag = disable_interrupts(); - absEntry(FLASH29_CMD_AUTOSELECT,0,0,0); - if (flag) enable_interrupts(); - - udelay(100); - - flag = disable_interrupts(); - absEntry(FLASH29_CMD_READ, addr + 1, (char *)&retValue, sizeof(retValue)); - absEntry(FLASH29_CMD_READ_RESET,0,0,0); - if (flag) enable_interrupts(); - - udelay(100); - - switch (retValue) { - - case (FPW)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - ulong start, now, last; - int rcode = 0; - FUNCPTR_WR absEntry; - - load_cmd(IN_RAM_CMD_WRITE); - absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160B: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - absEntry(FLASH29_CMD_SECTOR, addr, 0); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - while ((now = get_timer(start)) <= CFG_FLASH_ERASE_TOUT) { - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - flag = disable_interrupts(); - absEntry(FLASH29_CMD_READ_RESET,0,0); - if (flag) - enable_interrupts(); - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - res = write_word(info, (FPWV *)addr, data); - } - - return (res); -} - -static int write_word (flash_info_t *info, FPWV *dest, FPW data) -{ - int res = 0; /* result, assume success */ - FUNCPTR_WR absEntry; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - if (info->start[0] != PHYS_FLASH_1) - { - return (3); - } - - load_cmd(IN_RAM_CMD_WRITE); - absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD; - - flag = disable_interrupts(); - absEntry(FLASH29_CMD_PROGRAM,dest,data); - if (flag) enable_interrupts(); - - udelay(100); - - flag = disable_interrupts(); - absEntry(FLASH29_CMD_READ_RESET,0,0); - if (flag) enable_interrupts(); - - return (res); -} diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S deleted file mode 100644 index 668124a..0000000 --- a/board/purple/lowlevel_init.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Memory sub-system initialization code for PURPLE development board. - * - * Copyright (c) 2003 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define MC_IOGP 0xBF800800 - - .globl lowlevel_init -lowlevel_init: - li t0, MC_IOGP - li t1, 0xf24 - sw t1, 0(t0) - j ra - nop diff --git a/board/purple/purple.c b/board/purple/purple.c deleted file mode 100644 index 4c3e5b4..0000000 --- a/board/purple/purple.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "sconsole.h" - -#define cache_unroll(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, (%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -typedef void (*FUNCPTR)(ulong *source, ulong *destination, ulong nlongs); - -extern void asc_serial_init (void); -extern void asc_serial_putc (char); -extern void asc_serial_puts (const char *); -extern int asc_serial_getc (void); -extern int asc_serial_tstc (void); -extern void asc_serial_setbrg (void); - -static void sdram_timing_init (ulong size) -{ - register uint pass; - register uint done; - register uint count; - register uint p0, p1, p2, p3, p4; - register uint addr; - -#define WRITE_MC_IOGP_1 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+(p4<<8)+(p0<<4)+p3; -#define WRITE_MC_IOGP_2 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+((p4-16)<<8)+(p0<<4)+p3; - - done = 0; - p0 = 2; - while (p0 < 4 && done == 0) { - p1 = 0; - while (p1 < 2 && done == 0) { - p2 = 0; - while (p2 < 2 && done == 0) { - p3 = 0; - while (p3 < 16 && done == 0) { - count = 0; - p4 = 0; - while (p4 < 32 && done == 0) { - WRITE_MC_IOGP_1; - - for (addr = KSEG1 + 0x4000; - addr < KSEG1ADDR (size); - addr = addr + 4) { - *(uint *) addr = 0xaa55aa55; - } - - pass = 1; - - for (addr = KSEG1 + 0x4000; - addr < KSEG1ADDR (size) && pass == 1; - addr = addr + 4) { - if (*(uint *) addr != 0xaa55aa55) - pass = 0; - } - - if (pass == 1) { - count++; - } else { - count = 0; - } - - if (count == 32) { - WRITE_MC_IOGP_2; - done = 1; - } - p4++; - } - p3++; - } - p2++; - } - p1++; - } - p0++; - if (p0 == 1) - p0++; - } -} - -long int initdram(int board_type) -{ - /* The only supported number of SDRAM banks is 4. - */ -#define CFG_NB 4 - - ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; - ulong cfgdw = *INCA_IP_SDRAM_MC_CFGDW; - int cols = cfgpb0 & 0xF; - int rows = (cfgpb0 & 0xF0) >> 4; - int dw = cfgdw & 0xF; - ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB; - void (* sdram_init) (ulong); - - sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init); - - sdram_init(0x10000); - - return size; -} - -int checkboard (void) -{ - - unsigned long chipid = *(unsigned long *)0xB800C800; - - printf ("Board: Purple PLB 2800 chip version %ld, ", chipid & 0xF); - - printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000); - - return 0; -} - -int misc_init_r (void) -{ - asc_serial_init (); - - sconsole_putc = asc_serial_putc; - sconsole_puts = asc_serial_puts; - sconsole_getc = asc_serial_getc; - sconsole_tstc = asc_serial_tstc; - sconsole_setbrg = asc_serial_setbrg; - - sconsole_flush (); - return (0); -} - -/******************************************************************************* -* -* copydwords - copy one buffer to another a long at a time -* -* This routine copies the first longs from to . -*/ -static void copydwords (ulong *source, ulong *destination, ulong nlongs) -{ - ulong temp,temp1; - ulong *dstend = destination + nlongs; - - while (destination < dstend) - { - temp = *source++; - /* dummy read from sdram */ - temp1 = *(ulong *)0xa0000000; - /* avoid optimization from compliler */ - *(ulong *)0xbf0081f8 = temp1 + temp; - *destination++ = temp; - - } -} - -/******************************************************************************* -* -* copyLongs - copy one buffer to another a long at a time -* -* This routine copies the first longs from to . -*/ -static void copyLongs (ulong *source, ulong *destination, ulong nlongs) -{ - FUNCPTR absEntry; - - absEntry = (FUNCPTR)(0xbf008000+((ulong)copydwords & 0x7)); - absEntry(source, destination, nlongs); -} - -/******************************************************************************* -* -* programLoad - load program into ram -* -* This routine load copydwords into ram -* -*/ -static void programLoad(void) -{ - FUNCPTR absEntry; - ulong *src,*dst; - - src = (ulong *)(TEXT_BASE + 0x428); - dst = (ulong *)0xbf0081d0; - - absEntry = (FUNCPTR)(TEXT_BASE + 0x400); - absEntry(src,dst,0x6); - - src = (ulong *)((ulong)copydwords & 0xfffffff8); - dst = (ulong *)0xbf008000; - - absEntry(src,dst,0x38); -} - -/******************************************************************************* -* -* copy_code - copy u-boot image from flash to RAM -* -* This routine is needed to solve flash problems on this board -* -*/ -void copy_code (ulong dest_addr) -{ - extern long uboot_end_data; - unsigned long start; - unsigned long end; - - /* load copydwords into ram - */ - programLoad(); - - /* copy u-boot code - */ - copyLongs((ulong *)CFG_MONITOR_BASE, - (ulong *)dest_addr, - ((ulong)&uboot_end_data - CFG_MONITOR_BASE + 3) / 4); - - - /* flush caches - */ - - start = KSEG0; - end = start + CFG_DCACHE_SIZE; - while(start < end) { - cache_unroll(start,Index_Writeback_Inv_D); - start += CFG_CACHELINE_SIZE; - } - - start = KSEG0; - end = start + CFG_ICACHE_SIZE; - while(start < end) { - cache_unroll(start,Index_Invalidate_I); - start += CFG_CACHELINE_SIZE; - } -} diff --git a/board/purple/sconsole.c b/board/purple/sconsole.c deleted file mode 100644 index f52d50d..0000000 --- a/board/purple/sconsole.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include "sconsole.h" - -void (*sconsole_putc) (char) = 0; -void (*sconsole_puts) (const char *) = 0; -int (*sconsole_getc) (void) = 0; -int (*sconsole_tstc) (void) = 0; -void (*sconsole_setbrg) (void) = 0; - -int serial_init (void) -{ - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - sb->pos = 0; - sb->size = 0; - sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t); - - return (0); -} - -void serial_putc (char c) -{ - if (sconsole_putc) { - (*sconsole_putc) (c); - } else { - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - if (c) { - sb->data[sb->pos++] = c; - if (sb->pos == sb->max_size) { - sb->pos = 0; - } - if (sb->size < sb->max_size) { - sb->size++; - } - } - } -} - -void serial_puts (const char *s) -{ - if (sconsole_puts) { - (*sconsole_puts) (s); - } else { - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - while (*s) { - sb->data[sb->pos++] = *s++; - if (sb->pos == sb->max_size) { - sb->pos = 0; - } - if (sb->size < sb->max_size) { - sb->size++; - } - } - } -} - -int serial_getc (void) -{ - if (sconsole_getc) { - return (*sconsole_getc) (); - } else { - return 0; - } -} - -int serial_tstc (void) -{ - if (sconsole_tstc) { - return (*sconsole_tstc) (); - } else { - return 0; - } -} - -void serial_setbrg (void) -{ - if (sconsole_setbrg) { - (*sconsole_setbrg) (); - } -} - -void sconsole_flush (void) -{ - if (sconsole_putc) { - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - unsigned int end = sb->pos < sb->size - ? sb->pos + sb->max_size - sb->size - : sb->pos - sb->size; - - while (sb->size) { - (*sconsole_putc) (sb->data[end++]); - if (end == sb->max_size) { - end = 0; - } - sb->size--; - } - } -} diff --git a/board/purple/sconsole.h b/board/purple/sconsole.h deleted file mode 100644 index d441f37..0000000 --- a/board/purple/sconsole.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SCONSOLE_H_ -#define _SCONSOLE_H_ - -#include - -typedef struct sconsole_buffer_s -{ - unsigned long size; - unsigned long max_size; - unsigned long pos; - char data [1]; -} sconsole_buffer_t; - -#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR) - -extern void (* sconsole_putc) (char); -extern void (* sconsole_puts) (const char *); -extern int (* sconsole_getc) (void); -extern int (* sconsole_tstc) (void); -extern void (* sconsole_setbrg) (void); - -extern void sconsole_flush (void); - -#endif diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds deleted file mode 100644 index 1bdac1f..0000000 --- a/board/purple/u-boot.lds +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/mips/start.o (.text) - board/purple/lowlevel_init.o (.text) - cpu/mips/cache.o (.text) - common/main.o (.text) - common/dlmalloc.o (.text) - common/cmd_boot.o (.text) - lib_generic/zlib.o (.text) - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) - - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - _gp = ALIGN(16); - - __got_start = .; - .got : { *(.got) } - __got_end = .; - - .sdata : { *(.sdata) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) } - uboot_end = .; -} diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile deleted file mode 100644 index b5f352a..0000000 --- a/board/pxa255_idp/Makefile +++ /dev/null @@ -1,48 +0,0 @@ - -# -# (C) Copyright 2000-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := pxa_idp.o -SOBJS := memsetup.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/pxa255_idp/README b/board/pxa255_idp/README deleted file mode 100644 index 0cc2f2a..0000000 --- a/board/pxa255_idp/README +++ /dev/null @@ -1,11 +0,0 @@ -Tested: - -- MMC -- Ethernet -- BL console (on serial port connector J5) -- flash support - -Todo: - -- display support -- PCMCIA support diff --git a/board/pxa255_idp/config.mk b/board/pxa255_idp/config.mk deleted file mode 100644 index d2a2040..0000000 --- a/board/pxa255_idp/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -#TEXT_BASE = 0xa1700000 -TEXT_BASE = 0xa3000000 -#TEXT_BASE = 0 diff --git a/board/pxa255_idp/idp_notes.txt b/board/pxa255_idp/idp_notes.txt deleted file mode 100644 index 4746748..0000000 --- a/board/pxa255_idp/idp_notes.txt +++ /dev/null @@ -1,46 +0,0 @@ -Notes on the Vibren PXA255 IDP. - -Chip select usage: - -CS0 - flash -CS1 - alt flash (Mdoc or main flash) -CS2 - high speed expansion bus -CS3 - Media Q, low speed exp bus -CS4 - low speed exp bus -CS5 - low speed exp bus - - IDE: offset 0x03000000 (abs: 0x17000000) - - Eth: offset 0x03400000 (abs: 0x17400000) - - core voltage latch: offset 0x03800000 (abs: 0x17800000) - - CPLD: offset 0x03C00000 (abs: 0x17C00000) - -PCMCIA Power control - -MAX1602EE w/ code pulled high (Cirrus code) -vx = 5v -vy = 3v - - Bit pattern - PWR 3,2,1,0 -vcc vpp A1VCC A0VCC A1VPP A0VPP -===================================================== -0 0 0 0 0 0 0x0 -3 (vy) 0 1 0 1 1 0xB -3 (vy) 3 (vy) 1 0 0 1 0x9 -3 (vy) 12(12in) 1 0 1 0 0xA -5 (vx) 0 0 1 1 1 0x7 -5 (vx) 5 (vx) 0 1 0 1 0x5 -5 (vx 12(12in) 0 1 1 0 0x6 - -Display power sequencing: - -- VDD applied -- within 1sec, activate scanning signals -- wait at least 50mS - scanning signals must be active before activating DISP - -Signal mapping: -Schematic LV8V31 signal name -========================================= -LCD_ENAVLCD DISP -LCD_PWR Applies VDD to board - -Both of the above signals are controlled by the CPLD diff --git a/board/pxa255_idp/memsetup.S b/board/pxa255_idp/memsetup.S deleted file mode 100644 index 7e485a2..0000000 --- a/board/pxa255_idp/memsetup.S +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/memsetup.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -/* - * Memory setup - */ -.globl memsetup -memsetup: - - mov r10, lr - -#ifdef DEBUG_BLINK_ENABLE - /* 3rd blink */ - bl blink -#endif - - /* Set up GPIO pins first ----------------------------------------- */ - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - -#ifdef DEBUG_BLINK_ENABLE - /* 4th debug blink */ - bl blink -#endif - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1, =MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - -#ifdef DEBUG_BLINK_ENABLE - /* 5th blink */ - bl blink -#endif - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r3, =CFG_MDREFR_VAL - ldr r2, =0xFFF - and r3, r3, r2 - ldr r4, =0x03ca4000 - orr r4, r4, r3 - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - /* FIXME: we use async mode for now */ - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - /* set MDREFR according to user define with exception of a few bits */ - - ldr r4, =CFG_MDREFR_VAL - orr r4, r4, #(MDREFR_SLFRSH) - bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Step 4b: de-assert MDREFR:SLFRSH. */ - - bic r4, r4, #(MDREFR_SLFRSH) - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ - - ldr r4, =CFG_MDREFR_VAL - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ - /* configure but not enable each SDRAM partition pair. */ - - ldr r4, =CFG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - ldr r3, =CFG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* (MDCNFG:DEx set to 1). */ - - ldr r3, [r1, #MDCNFG_OFFSET] - orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) - str r3, [r1, #MDCNFG_OFFSET] - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - /* We are finished with Intel's memory controller initialisation */ -#if 0 - /* FIXME turn on serial ports */ - /* look into moving this to board_init() */ - ldr r2, =(PXA_CS5_PHYS + 0x03C0002c) - mov r3, #0x13 - str r3, [r2] -#endif - -#ifdef DEBUG_BLINK_ENABLE - /* 6th blink */ - bl blink -#endif - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - /* (hard-coding at 398.12MHz for now). */ - - /* Turn Off ALL on-chip peripheral clocks for re-configuration */ - /* Note: See label 'ENABLECLKS' for the re-enabling */ -#if 0 - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - /* default value in case no valid rotary switch setting is found */ - ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ - - /* ... and write the core clock config register */ - ldr r1, =CCCR - str r2, [r1] - -#endif - -#ifdef RTC - /* enable the 32Khz oscillator for RTC and PowerManager */ - - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#endif - - /* ---------------------------------------------------------------- */ - /* */ - /* ---------------------------------------------------------------- */ - - /* Save SDRAM size */ - ldr r1, =DRAM_SIZE - str r8, [r1] - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - - /* FIXME */ - -#define NODEBUG -#ifdef NODEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ -#endif - - /* ---------------------------------------------------------------- */ - /* End memsetup */ - /* ---------------------------------------------------------------- */ - -#ifdef DEBUG_BLINK_ENABLE - /* 7th blink */ - bl blink -#endif - -endmemsetup: - - mov pc, r10 - - -#ifdef DEBUG_BLINK_ENABLE - -/* debug LED code */ - -/* delay about 200ms */ -delay: - - /* reset OSCR to 0 */ - ldr r8, =OSCR - mov r9, #0 - str r9, [r8] - - /* make sure new value has stuck */ -1: - ldr r8, =OSCR - ldr r9, [r8] - mov r8, #0x10000 - cmp r9, r8 - bgt 1b - - /* now, wait for delay to expire */ -1: - ldr r8, =OSCR - ldr r9, [r8] - mov r8, #0xd4000 - cmp r8, r9 - bgt 1b - - mov pc, lr - -/* blink code -- trashes r7, r8, r9 */ - -.globl blink -blink: - - mov r7, lr - - /* set GPIO10 as outout */ - ldr r8, =GPDR0 - ldr r9, [r8] - orr r9, r9, #(1<<10) - str r9, [r8] - - /* turn LED off */ - mov r9, #(1<<10) - ldr r8, =GPCR0 - str r9, [r8] - bl delay - - /* turn LED on */ - mov r9, #(1<<10) - ldr r8, =GPSR0 - str r9, [r8] - bl delay - - /* turn LED off */ - mov r9, #(1<<10) - ldr r8, =GPCR0 - str r9, [r8] - - mov pc, r7 - -#endif diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c deleted file mode 100644 index d5b993a..0000000 --- a/board/pxa255_idp/pxa_idp.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2004 - * BEC Systems - * Cliff Brake - * Support for Accelent/Vibren PXA255 IDP - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of Lubbock-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* turn on serial ports */ - *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13; - - /* set PWM for LCD */ - /* a value that works is 60Hz, 77% duty cycle */ - CKEN |= CKEN0_PWM0; - PWM_CTRL0 = 0x3f; - PWM_PERVAL0 = 0x3ff; - PWM_PWDUTY0 = 792; - - /* clear reset to AC97 codec */ - CKEN |= CKEN2_AC97; - GCR = GCR_COLD_RST; - - /* enable LCD backlight */ - /* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */ - - /* test display */ - /* lcd_puts("This is a test\nTest #2\n"); */ - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; - - return 0; -} - - -#ifdef DEBUG_BLINKC_ENABLE - -void delay_c(void) -{ - /* reset OSCR to 0 */ - OSCR = 0; - while(OSCR > 0x10000) - ; - - while(OSCR < 0xd4000) - ; -} - -void blink_c(void) -{ - int led_bit = (1<<10); - - GPDR0 = led_bit; - GPCR0 = led_bit; - delay_c(); - GPSR0 = led_bit; - delay_c(); - GPCR0 = led_bit; -} - -int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf("IDPCMD started\n"); - return 0; -} - -U_BOOT_CMD(idpcmd, CFG_MAXARGS, 0, do_idpcmd, - "idpcmd - custom IDP command\n", - "no args at this time\n" -); - -#endif diff --git a/board/pxa255_idp/pxa_reg_calcs.out b/board/pxa255_idp/pxa_reg_calcs.out deleted file mode 100644 index bda9946..0000000 --- a/board/pxa255_idp/pxa_reg_calcs.out +++ /dev/null @@ -1,119 +0,0 @@ -gafr0_l: 0x80001005 -gafr0_u: 0xa5128012 -gafr1_l: 0x699a9558 -gafr1_u: 0xaaa5aa6a -gafr2_l: 0xaaaaaaaa -gafr2_u: 0x2 -gpcr0: 0x1800400 -gpcr1: 0x0 -gpcr2: 0x0 -gpdr0: 0xc1818440 -gpdr1: 0xfcffab82 -gpdr2: 0x1ffff -gpsr0: 0x8000 -gpsr1: 0x3f0002 -gpsr2: 0x1c000 - - -#define CFG_GAFR0_L_VAL 0x80001005 -#define CFG_GAFR0_U_VAL 0xa5128012 -#define CFG_GAFR1_L_VAL 0x699a9558 -#define CFG_GAFR1_U_VAL 0xaaa5aa6a -#define CFG_GAFR2_L_VAL 0xaaaaaaaa -#define CFG_GAFR2_U_VAL 0x2 -#define CFG_GPCR0_VAL 0x1800400 -#define CFG_GPCR1_VAL 0x0 -#define CFG_GPCR2_VAL 0x0 -#define CFG_GPDR0_VAL 0xc1818440 -#define CFG_GPDR1_VAL 0xfcffab82 -#define CFG_GPDR2_VAL 0x1ffff -#define CFG_GPSR0_VAL 0x8000 -#define CFG_GPSR1_VAL 0x3f0002 -#define CFG_GPSR2_VAL 0x1c000 - - -GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET# -GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET# -GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA -GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ# -GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH -GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH# -GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK -GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD# -GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD# -GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD# -GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED -GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK -GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK -GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT -GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ -GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1# -GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0 -GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB -GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY -GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O# -GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0 -GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI -GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O# -GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK -GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM -GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD -GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD -GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK -GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK -GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0 -GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT -GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC -GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1 -GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5# -GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD -GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS -GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD -GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR -GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI -GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD -GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR -GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS -GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD -GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD -GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS -GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS -GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD -GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD -GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE# -GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE# -GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR# -GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW# -GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1# -GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2# -GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL -GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG# -GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT# -GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16# -GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0 -GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1 -GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2 -GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3 -GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4 -GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5 -GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6 -GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7 -GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8 -GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9 -GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10 -GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11 -GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12 -GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13 -GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14 -GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15 -GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK -GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK -GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK -GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS -GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2# -GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3# -GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4# -GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc= -GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc= -GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc= -GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc= diff --git a/board/pxa255_idp/pxa_reg_calcs.py b/board/pxa255_idp/pxa_reg_calcs.py deleted file mode 100644 index c4bcb4b..0000000 --- a/board/pxa255_idp/pxa_reg_calcs.py +++ /dev/null @@ -1,311 +0,0 @@ -#!/usr/bin/python - -# (C) Copyright 2004 -# BEC Systems -# Cliff Brake - -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -# calculations for PXA255 registers - -class gpio: - dir = '0' - set = '0' - clr = '0' - alt = '0' - desc = '' - - def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''): - self.dir = dir - self.set = set - self.clr = clr - self.alt = alt - self.desc = desc - - -# the following is a dictionary of all GPIOs in the system -# the key is the GPIO number - - -pxa255_alt_func = { - 0: ['gpio', 'none', 'none', 'none'], - 1: ['gpio', 'gpio reset', 'none', 'none'], - 2: ['gpio', 'none', 'none', 'none'], - 3: ['gpio', 'none', 'none', 'none'], - 4: ['gpio', 'none', 'none', 'none'], - 5: ['gpio', 'none', 'none', 'none'], - 6: ['gpio', 'MMC clk', 'none', 'none'], - 7: ['gpio', '48MHz clock', 'none', 'none'], - 8: ['gpio', 'MMC CS0', 'none', 'none'], - 9: ['gpio', 'MMC CS1', 'none', 'none'], - 10: ['gpio', 'RTC Clock', 'none', 'none'], - 11: ['gpio', '3.6MHz', 'none', 'none'], - 12: ['gpio', '32KHz', 'none', 'none'], - 13: ['gpio', 'none', 'MBGNT', 'none'], - 14: ['gpio', 'MBREQ', 'none', 'none'], - 15: ['gpio', 'none', 'nCS_1', 'none'], - 16: ['gpio', 'none', 'PWM0', 'none'], - 17: ['gpio', 'none', 'PWM1', 'none'], - 18: ['gpio', 'RDY', 'none', 'none'], - 19: ['gpio', 'DREQ[1]', 'none', 'none'], - 20: ['gpio', 'DREQ[0]', 'none', 'none'], - 21: ['gpio', 'none', 'none', 'none'], - 22: ['gpio', 'none', 'none', 'none'], - 23: ['gpio', 'none', 'SSP SCLK', 'none'], - 24: ['gpio', 'none', 'SSP SFRM', 'none'], - 25: ['gpio', 'none', 'SSP TXD', 'none'], - 26: ['gpio', 'SSP RXD', 'none', 'none'], - 27: ['gpio', 'SSP EXTCLK', 'none', 'none'], - 28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'], - 29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'], - 30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'], - 31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'], - 32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'], - 33: ['gpio', 'none', 'nCS_5', 'none'], - 34: ['gpio', 'FF RXD', 'MMC CS0', 'none'], - 35: ['gpio', 'FF CTS', 'none', 'none'], - 36: ['gpio', 'FF DCD', 'none', 'none'], - 37: ['gpio', 'FF DSR', 'none', 'none'], - 38: ['gpio', 'FF RI', 'none', 'none'], - 39: ['gpio', 'MMC CS1', 'FF TXD', 'none'], - 40: ['gpio', 'none', 'FF DTR', 'none'], - 41: ['gpio', 'none', 'FF RTS', 'none'], - 42: ['gpio', 'BT RXD', 'none', 'HW RXD'], - 43: ['gpio', 'none', 'BT TXD', 'HW TXD'], - 44: ['gpio', 'BT CTS', 'none', 'HW CTS'], - 45: ['gpio', 'none', 'BT RTS', 'HW RTS'], - 46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'], - 47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'], - 48: ['gpio', 'HW TXD', 'nPOE', 'none'], - 49: ['gpio', 'HW RXD', 'nPWE', 'none'], - 50: ['gpio', 'HW CTS', 'nPIOR', 'none'], - 51: ['gpio', 'nPIOW', 'HW RTS', 'none'], - 52: ['gpio', 'none', 'nPCE[1]', 'none'], - 53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'], - 54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'], - 55: ['gpio', 'none', 'nPREG', 'none'], - 56: ['gpio', 'nPWAIT', 'none', 'none'], - 57: ['gpio', 'nIOIS16', 'none', 'none'], - 58: ['gpio', 'none', 'LDD[0]', 'none'], - 59: ['gpio', 'none', 'LDD[1]', 'none'], - 60: ['gpio', 'none', 'LDD[2]', 'none'], - 61: ['gpio', 'none', 'LDD[3]', 'none'], - 62: ['gpio', 'none', 'LDD[4]', 'none'], - 63: ['gpio', 'none', 'LDD[5]', 'none'], - 64: ['gpio', 'none', 'LDD[6]', 'none'], - 65: ['gpio', 'none', 'LDD[7]', 'none'], - 66: ['gpio', 'MBREQ', 'LDD[8]', 'none'], - 67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'], - 68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'], - 69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'], - 70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'], - 71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'], - 72: ['gpio', '32 KHz', 'LDD[14]', 'none'], - 73: ['gpio', 'MBGNT', 'LDD[15]', 'none'], - 74: ['gpio', 'none', 'LCD_FCLK', 'none'], - 75: ['gpio', 'none', 'LCD_LCLK', 'none'], - 76: ['gpio', 'none', 'LCD_PCLK', 'none'], - 77: ['gpio', 'none', 'LCD_ACBIAS', 'none'], - 78: ['gpio', 'none', 'nCS_2', 'none'], - 79: ['gpio', 'none', 'nCS_3', 'none'], - 80: ['gpio', 'none', 'nCS_4', 'none'], - 81: ['gpio', 'NSSPSCLK', 'none', 'none'], - 82: ['gpio', 'NSSPSFRM', 'none', 'none'], - 83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'], - 84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'], -} - - -#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''): - -gpio_list = [] - -for i in range(0,85): - gpio_list.append(gpio()) - -#chip select GPIOs -gpio_list[18] = gpio(0, 0, 0, 1, 'RDY') -gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#') -gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#') -gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#') -gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#') -gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#') -gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#') -gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI') -gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#') -gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0') -gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0') -gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB') -gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0') - -# PCMCIA stuff -gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#') -gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#') -gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#') -gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL') -gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#') -gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#') -gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#') -gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#') -gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#') -gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#') - -# SSP port -gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD') -gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD') -gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM') -gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK') -gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK') - -# audio codec -gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1') -gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC') -gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT') -gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0') -gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK') - -# serial ports -gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD') -gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD') -gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS') -gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS') -gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR') -gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR') -gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI') -gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD') - -gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD') -gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD') -gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS') -gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS') - -gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD') -gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD') - -# misc GPIO signals -gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ') -gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT') -gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK') -gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK') -gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED') -gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#') -gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#') -gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#') -gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK') -gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#') -gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH') -gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#') -gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA') -gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#') -gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#') - -# LCD GPIOs -gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0') -gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1') -gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2') -gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3') -gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4') -gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5') -gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6') -gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7') -gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8') -gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9') -gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10') -gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11') -gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12') -gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13') -gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14') -gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15') -gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK') -gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK') -gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK') -gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS') - -# calculate registers -pxa_regs = { - 'gpdr0':0, 'gpdr1':0, 'gpdr2':0, - 'gpsr0':0, 'gpsr1':0, 'gpsr2':0, - 'gpcr0':0, 'gpcr1':0, 'gpcr2':0, - 'gafr0_l':0, 'gafr0_u':0, - 'gafr1_l':0, 'gafr1_u':0, - 'gafr2_l':0, 'gafr2_u':0, -} - -# U-boot define names -uboot_reg_names = { - 'gpdr0':'CFG_GPDR0_VAL', 'gpdr1':'CFG_GPDR1_VAL', 'gpdr2':'CFG_GPDR2_VAL', - 'gpsr0':'CFG_GPSR0_VAL', 'gpsr1':'CFG_GPSR1_VAL', 'gpsr2':'CFG_GPSR2_VAL', - 'gpcr0':'CFG_GPCR0_VAL', 'gpcr1':'CFG_GPCR1_VAL', 'gpcr2':'CFG_GPCR2_VAL', - 'gafr0_l':'CFG_GAFR0_L_VAL', 'gafr0_u':'CFG_GAFR0_U_VAL', - 'gafr1_l':'CFG_GAFR1_L_VAL', 'gafr1_u':'CFG_GAFR1_U_VAL', - 'gafr2_l':'CFG_GAFR2_L_VAL', 'gafr2_u':'CFG_GAFR2_U_VAL', -} - -# bit mappings - -bit_mappings = [ - -{ 'gpio':(0,32), 'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} }, -{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} }, -{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} }, -{ 'gpio':(0,16), 'shift':2, 'regs':{'alt':'gafr0_l'} }, -{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} }, -{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} }, -{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} }, -{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} }, -{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} }, - -] - -def stuff_bits(bit_mapping, gpio_list): - gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1]) - - for gpio in gpios: - for reg in bit_mapping['regs'].keys(): - value = eval( 'gpio_list[gpio].%s' % (reg) ) - if ( value ): - # we have a high bit - bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift'] - bit = value << (bit_shift) - pxa_regs[bit_mapping['regs'][reg]] |= bit - -for i in bit_mappings: - stuff_bits(i, gpio_list) - -# now print out all regs -registers = pxa_regs.keys() -registers.sort() -for reg in registers: - print '%s: 0x%x' % (reg, pxa_regs[reg]) - -# print define to past right into U-Boot source code - -print -print - -for reg in registers: - print '#define %s 0x%x' % (uboot_reg_names[reg], pxa_regs[reg]) - -# print all GPIOS -print -print - -for i in range(len(gpio_list)): - gpio_i = gpio_list[i] - alt_func_desc = pxa255_alt_func[i][gpio_i.alt] - print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc) - - diff --git a/board/pxa255_idp/u-boot.lds b/board/pxa255_idp/u-boot.lds deleted file mode 100644 index 20ce108..0000000 --- a/board/pxa255_idp/u-boot.lds +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/quantum/Makefile b/board/quantum/Makefile deleted file mode 100644 index e50f5ff..0000000 --- a/board/quantum/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o fpga.o - - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/quantum/config.mk b/board/quantum/config.mk deleted file mode 100644 index 7cb374e..0000000 --- a/board/quantum/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# RMU boards -# - -TEXT_BASE = 0xfff00000 diff --git a/board/quantum/fpga.c b/board/quantum/fpga.c deleted file mode 100644 index 75c2658..0000000 --- a/board/quantum/fpga.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* The DEBUG define must be before common to enable debugging */ -#undef DEBUG -#include -#include -#include -#include "fpga.h" -/* ------------------------------------------------------------------------- */ - -#define MAX_ONES 226 - -/* MPC850 port D */ -#define PD(bit) (1 << (15 - (bit))) -# define FPGA_INIT PD(11) /* FPGA init pin (ppc input) */ -# define FPGA_PRG PD(12) /* FPGA program pin (ppc output) */ -# define FPGA_CLK PD(13) /* FPGA clk pin (ppc output) */ -# define FPGA_DATA PD(14) /* FPGA data pin (ppc output) */ -# define FPGA_DONE PD(15) /* FPGA done pin (ppc input) */ - - -/* DDR 0 - input, 1 - output */ -#define FPGA_INIT_PDDIR FPGA_PRG | FPGA_CLK | FPGA_DATA /* just set outputs */ - - -#define SET_FPGA(data) immr->im_ioport.iop_pddat = (data) -#define GET_FPGA immr->im_ioport.iop_pddat - -#define FPGA_WRITE_1 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG); /* set data to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - - -int fpga_boot (unsigned char *fpgadata, int size) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - int i, index, len; - int count; - -#ifdef CFG_FPGA_SPARTAN2 - int j; - unsigned char data; -#else - unsigned char b; - int bit; -#endif - - debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size); - - /* display infos on fpgaimage */ - printf ("FPGA:"); - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf (" %s", &(fpgadata[index + 1])); - index += len + 3; - } - printf ("\n"); - - - index = 0; - -#ifdef CFG_FPGA_SPARTAN2 - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) - && (fpgadata[index + 2] == 0xff) - && (fpgadata[index + 3] == 0xff)) - break; /* preamble found */ - else - index++; - } -#else - /* search for preamble 0xFF2X */ - for (index = 0; index < size - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x30)) - break; - } - index += 2; -#endif - - debug ("FPGA: configdata starts at position 0x%x\n", index); - debug ("FPGA: length of fpga-data %d\n", size - index); - - /* - * Setup port pins for fpga programming - */ - immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR; - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA (FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA init line low */ - count = 0; - while (GET_FPGA & FPGA_INIT) { - udelay (1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* deassert PROGRAM* */ - SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(GET_FPGA & FPGA_INIT)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - debug ("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - -#ifdef CFG_FPGA_SPARTAN2 - /* - * Load uncompressed image into fpga - */ - for (i = index; i < size; i++) { -#ifdef CFG_FPGA_PROG_FEEDBACK - if ((i % 1024) == 0) - printf ("%6d out of %6d\r", i, size); /* let them know we are alive */ -#endif - - data = fpgadata[i]; - for (j = 0; j < 8; j++) { - if ((data & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - data <<= 1; - } - } - /* add some 0xff to the end of the file */ - for (i = 0; i < 8; i++) { - data = 0xff; - for (j = 0; j < 8; j++) { - if ((data & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - data <<= 1; - } - } -#else - /* send 0xff 0x20 */ - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - - /* - ** Bit_DeCompression - ** Code 1 .. maxOnes : n '1's followed by '0' - ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' - ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' - ** 255 : '1' - */ - - for (i = index; i < size; i++) { - b = fpgadata[i]; - if ((b >= 1) && (b <= MAX_ONES)) { - for (bit = 0; bit < b; bit++) { - FPGA_WRITE_1; - } - FPGA_WRITE_0; - } else if (b == (MAX_ONES + 1)) { - for (bit = 1; bit < b; bit++) { - FPGA_WRITE_1; - } - } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { - for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { - FPGA_WRITE_0; - } - FPGA_WRITE_1; - } else if (b == 255) { - FPGA_WRITE_1; - } - } -#endif - debug ("\n\n"); - debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Check if fpga's DONE signal - correctly booted ? - */ - - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(GET_FPGA & FPGA_DONE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - debug ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - debug ("FPGA: Booting successful!\n"); - return 0; -} diff --git a/board/quantum/fpga.h b/board/quantum/fpga.h deleted file mode 100644 index 2ef45e5..0000000 --- a/board/quantum/fpga.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* - * Virtex2 FPGA configuration support for the QUANTUM computer - */ -int fpga_boot(unsigned char *fpgadata, int size); - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ -/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c deleted file mode 100644 index 2861bc3..0000000 --- a/board/quantum/quantum.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include "fpga.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -unsigned long flash_init (void); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = { - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, - 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, - 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - * (Initialization code at 0x36) - */ - 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, - 0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char *s = getenv ("serial#"); - - puts ("Board QUANTUM, Serial No: "); - - for (; s && *s; ++s) { - if (*s == ' ') - break; - putc (*s); - } - putc ('\n'); - return (0); /* success */ -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CFG_MPTPR; - - memctl->memc_mar = 0x00000088; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - - memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size, - * 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - /* - * Final mapping: - */ - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - udelay (1000); - - return (size9); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile ulong *addr; - ulong cnt, val, size; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - memctl->memc_mamr = mamr_value; - - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - /* Restore the original data before leaving the function. - */ - *addr = save[i]; - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = (volatile ulong *) base + cnt; - *addr = save[--i]; - } - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - size = cnt * sizeof (long); - /* Restore the original data before returning - */ - for (cnt <<= 1; cnt <= maxsize / sizeof (long); - cnt <<= 1) { - addr = (volatile ulong *) base + cnt; - *addr = save[--i]; - } - return (size); - } - } - return (maxsize); -} - -/* - * Miscellaneous intialization - */ -int misc_init_r (void) -{ - char *fpga_data_str = getenv ("fpgadata"); - char *fpga_size_str = getenv ("fpgasize"); - void *fpga_data; - int fpga_size; - int status; - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - int flash_size; - - /* Remap FLASH according to real size */ - flash_size = flash_init (); - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - if (fpga_data_str && fpga_size_str) { - fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16); - fpga_size = simple_strtoul (fpga_size_str, NULL, 10); - - status = fpga_boot (fpga_data, fpga_size); - if (status != 0) { - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - } - } - return 0; -} diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds deleted file mode 100644 index 049f990..0000000 --- a/board/quantum/u-boot.lds +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) -/* XXX ? - . = env_offset; -*/ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug deleted file mode 100644 index 894b9bd..0000000 --- a/board/quantum/u-boot.lds.debug +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/r360mpi/Makefile b/board/r360mpi/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/r360mpi/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/r360mpi/config.mk b/board/r360mpi/config.mk deleted file mode 100644 index 9d6080b..0000000 --- a/board/r360mpi/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TQM8xxL boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/r360mpi/flash.c b/board/r360mpi/flash.c deleted file mode 100644 index 9b42960..0000000 --- a/board/r360mpi/flash.c +++ /dev/null @@ -1,484 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - FPW value; - - /* Make sure Block Lock Bits get cleared */ - addr[0] = (FPW) 0x00FF00FF; - addr[0] = (FPW) 0x00600060; - addr[0] = (FPW) 0x00D000D0; - addr[0] = (FPW) 0x00FF00FF; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { - case (FPW) INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - - int i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} diff --git a/board/r360mpi/r360mpi.c b/board/r360mpi/r360mpi.c deleted file mode 100644 index ffb4c0e..0000000 --- a/board/r360mpi/r360mpi.c +++ /dev/null @@ -1,419 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include /* for strdup */ - - -/* - * Memory Controller Using - * - * CS0 - Flash memory (0x40000000) - * CS1 - FLASH memory (0x????????) - * CS2 - SDRAM (0x00000000) - * CS3 - - * CS4 - - * CS5 - - * CS6 - PCMCIA device - * CS7 - PCMCIA device - */ - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -const uint sdram_table[]= -{ - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* MRS initialization (offset 5) */ - - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ }; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: R360 MPI Board\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size_b0 = 0; - unsigned long reg; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 2 to the SDRAM bank at - * preliminary address - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; - - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay (200); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 2 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - -#ifdef CONFIG_CAN_DRIVER - /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CFG_OR3_CAN; /* switch GPLB_5 to GPLA_5 */ - memctl->memc_br3 = CFG_BR3_CAN; - - /* Initialize MBMR */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; - memctl->memc_mcr = 0x0100 | UPMB; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMB; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMB; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMB; - - memctl->memc_mdr = 0xFFFFDC05; - memctl->memc_mcr = 0x0104 | UPMB; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x0118 | UPMB; - - memctl->memc_mdr = 0xCFFCD004; - memctl->memc_mcr = 0x0119 | UPMB; - - memctl->memc_mdr = 0x0FFCC000; - memctl->memc_mcr = 0x011A | UPMB; - - memctl->memc_mdr = 0x7FFCC004; - memctl->memc_mcr = 0x011B | UPMB; - - memctl->memc_mdr = 0xFFFDCC05; - memctl->memc_mcr = 0x011C | UPMB; -#endif - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, - long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -void r360_i2c_lcd_write (uchar data0, uchar data1) -{ - if (i2c_write (CFG_I2C_LCD_ADDR, data0, 1, &data1, 1)) { - printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1); - } -} - -/* ------------------------------------------------------------------------- */ - -/*----------------------------------------------------------------------- - * Keyboard Controller - */ - -/* Number of bytes returned from Keyboard Controller */ -#define KEYBD_KEY_MAX 16 /* maximum key number */ -#define KEYBD_DATALEN ((KEYBD_KEY_MAX + 7) / 8) /* normal key scan data */ - -static uchar *key_match (uchar *); - -int misc_init_r (void) -{ - char kbd_data[KEYBD_DATALEN]; - char keybd_env[2 * KEYBD_DATALEN + 1]; - char *str; - int i; - - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - - i2c_read (CFG_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN); - - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf (keybd_env + i + i, "%02X", kbd_data[i]); - } - setenv ("keybd", keybd_env); - - str = strdup ((char *)key_match ((uchar *)keybd_env)); /* decode keys */ - -#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ - setenv ("preboot", str); /* set or delete definition */ -#endif /* CONFIG_PREBOOT */ - if (str != NULL) { - free (str); - } - - return (0); -} - -/*----------------------------------------------------------------------- - * Check if pressed key(s) match magic sequence, - * and return the command string associated with that key(s). - * - * If no key press was decoded, NULL is returned. - * - * Note: the first character of the argument will be overwritten with - * the "magic charcter code" of the decoded key(s), or '\0'. - * - * - * Note: the string points to static environment data and must be - * saved before you call any function that modifies the environment. - */ -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -static uchar *key_match (uchar * kbd_str) -{ - uchar magic[sizeof (kbd_magic_prefix) + 1]; - uchar cmd_name[sizeof (kbd_command_prefix) + 1]; - uchar *str, *suffix; - uchar *kbd_magic_keys; - char *cmd; - - /* - * The following string defines the characters that can pe appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) { - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix = kbd_magic_keys; - *suffix || suffix == kbd_magic_keys; - ++suffix) { - sprintf ((char *)magic, "%s%c", kbd_magic_prefix, *suffix); - -#if 0 - printf ("### Check magic \"%s\"\n", magic); -#endif - - if ((str = (uchar *)getenv ((char *)magic)) != 0) { - -#if 0 - printf ("### Compare \"%s\" \"%s\"\n", - kbd_str, str); -#endif - if (strcmp ((char *)kbd_str, (char *)str) == 0) { - sprintf ((char *)cmd_name, "%s%c", - kbd_command_prefix, - *suffix); - - if ((cmd = getenv ((char *)cmd_name)) != 0) { -#if 0 - printf ("### Set PREBOOT to $(%s): \"%s\"\n", - cmd_name, cmd); -#endif - return ((uchar *)cmd); - } - } - } - } - } -#if 0 - printf ("### Delete PREBOOT\n"); -#endif - *kbd_str = '\0'; - return (NULL); -} -#endif /* CONFIG_PREBOOT */ - -/* Read Keyboard status */ -int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - uchar kbd_data[KEYBD_DATALEN]; - uchar keybd_env[2 * KEYBD_DATALEN + 1]; - int i; - - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - - /* Read keys */ - i2c_read (CFG_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN); - - puts ("Keys:"); - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]); - printf (" %02x", kbd_data[i]); - } - putc ('\n'); - setenv ("keybd", (char *)keybd_env); - return 0; -} - -U_BOOT_CMD( - kbd, 1, 1, do_kbd, - "kbd - read keyboard status\n", - NULL -); diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds deleted file mode 100644 index 8b06af7..0000000 --- a/board/r360mpi/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/cpu_init.o (.text) - cpu/mpc8xx/interrupts.o (.text) - cpu/mpc8xx/traps.o (.text) -/*** - . = env_offset; - common/environment.o (.text) -***/ - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); - . = ALIGN(128 * 1024); - .ppcenv : - { - common/environment.o (.ppcenv) - } -} diff --git a/board/rattler/Makefile b/board/rattler/Makefile deleted file mode 100644 index 52f0fd6..0000000 --- a/board/rattler/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2001-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/rattler/config.mk b/board/rattler/config.mk deleted file mode 100644 index 5fca8c7..0000000 --- a/board/rattler/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2001-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Modified by, Yuli Barcohen, Arabella Software Ltd. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Rattler series boards by Analogue & Micro -# - -TEXT_BASE = 0xFE000000 diff --git a/board/rattler/rattler.c b/board/rattler/rattler.c deleted file mode 100644 index be7977d..0000000 --- a/board/rattler/rattler.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Analogue&Micro Rattler boards family. - * Tested on Rattler8248. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 1, 0, 0, 1, 0, 1 }, /* Eth PHYs reset */ - /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */ - /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ - /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ - /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */ - /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -long int initdram(int board_type) -{ - long int msize = CFG_SDRAM_SIZE; - -#ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; - uchar c = 0xFF; - uint psdmr = CFG_PSDMR; - int i; - - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x30126745; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CFG_MPTPR; - - /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_or1 = CFG_SDRAM_OR; - memctl->memc_br1 = CFG_SDRAM_BR; - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ - *ramaddr = c; -#endif /* !CFG_RAMBOOT */ - - /* Return total 60x bus SDRAM size */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - vu_char *bcsr = (vu_char *)CFG_BCSR; - - printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40); - return 0; -} diff --git a/board/rattler/u-boot.lds b/board/rattler/u-boot.lds deleted file mode 100644 index 522e6da..0000000 --- a/board/rattler/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Yuli Barcohen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/rbc823/Makefile b/board/rbc823/Makefile deleted file mode 100644 index 0121ddc..0000000 --- a/board/rbc823/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o kbd.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/rbc823/config.mk b/board/rbc823/config.mk deleted file mode 100644 index 199ea3c..0000000 --- a/board/rbc823/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# RBC823 boards -# - -TEXT_BASE = 0xFFF00000 diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c deleted file mode 100644 index 84ae5c1..0000000 --- a/board/rbc823/flash.c +++ /dev/null @@ -1,469 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Detect size */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - /* Setup offsets */ - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - size_b1 = 0 ; - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - * Fix this to support variable sector sizes -*/ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - /* set sector offsets for bottom boot block type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) - { - puts ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) - { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >> 20) { - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - } else { - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); - } - - puts (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) - { - if ((i % 5) == 0) - { - puts ("\n "); - } - - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - putc ('\n'); - return; -} -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - volatile unsigned char *caddr; - char value; - - caddr = (volatile unsigned char *)addr ; - - /* Write auto select command: read Manufacturer ID */ - -#if 0 - printf("Base address is: %08x\n", caddr); -#endif - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - value = caddr[0]; - -#if 0 - printf("Manufact ID: %02x\n", value); -#endif - switch (value) - { - case 0x01: /*AMD_MANUFACT*/ - info->flash_id = FLASH_MAN_AMD; - break; - - case 0x04: /*FUJ_MANUFACT*/ - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = caddr[1]; /* device ID */ -#if 0 - printf("Device ID: %02x\n", value); -#endif - switch (value) - { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets ((ulong)addr, &flash_info[0]); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) - { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) - { - caddr = (volatile unsigned char *)info->start[0]; - *caddr = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile unsigned char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - - while ((addr[0] & 0xFF) != 0xFF) - { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - - addr[0] = 0xF0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]), - *cdest,*cdata; - ulong start; - int flag, count = 4 ; - - cdest = (volatile unsigned char *)dest ; - cdata = (volatile unsigned char *)&data ; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - while(count--) - { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *cdest = *cdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*cdest ^ *cdata) & 0x80) - { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - cdata++ ; - cdest++ ; - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/rbc823/kbd.c b/board/rbc823/kbd.c deleted file mode 100644 index c27929d..0000000 --- a/board/rbc823/kbd.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Modified by Udi Finkelstein - * - * This file includes communication routines for SMC1 that can run even if - * SMC2 have already been initialized. - */ - -#include -#include -#include -#include -#include - -#define SMC_INDEX 0 -#define PROFF_SMC PROFF_SMC1 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 - -#define RBC823_KBD_BAUDRATE 38400 -#define CPM_KEYBOARD_BASE 0x1000 -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -void smc1_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG2 to SMC1, BRG1 to SMC2 - */ - - cp->cp_simode = 0x00001000; - - cp->cp_brgc2 = - (((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN; -} - -int smc1_init (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); - up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 1; - - /* clear error conditions */ -#ifdef CFG_SDSR - im->im_sdma.sdma_sdsr = CFG_SDSR; -#else - im->im_sdma.sdma_sdsr = 0x83; -#endif - - /* clear SDMA interrupt mask */ -#ifdef CFG_SDMR - im->im_sdma.sdma_sdmr = CFG_SDMR; -#else - im->im_sdma.sdma_sdmr = 0x00; -#endif - - /* Use Port B for SMC1 instead of other functions. - */ - cp->cp_pbpar |= 0x000000c0; - cp->cp_pbdir &= ~0x000000c0; - cp->cp_pbodr &= ~0x000000c0; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - -#ifdef CFG_ALLOC_DPRAM - dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; -#else - dpaddr = CPM_KEYBOARD_BASE ; -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data - */ - - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - */ - smc1_setbrg (); - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - return (0); -} - -void smc1_putc(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *)tbdf->cbd_bufaddr; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__("eieio"); - - while (tbdf->cbd_sc & BD_SC_READY) { - WATCHDOG_RESET (); - __asm__("eieio"); - } -} - -int smc1_getc(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - - while (rbdf->cbd_sc & BD_SC_EMPTY) - WATCHDOG_RESET (); - - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -int smc1_tstc(void) -{ - volatile cbd_t *rbdf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} - -/* search for keyboard and register it if found */ -int drv_keyboard_init(void) -{ - int error = 0; - device_t kbd_dev; - - if (0) { - /* register the keyboard */ - memset (&kbd_dev, 0, sizeof(device_t)); - strcpy(kbd_dev.name, "kbd"); - kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbd_dev.putc = NULL; - kbd_dev.puts = NULL; - kbd_dev.getc = smc1_getc; - kbd_dev.tstc = smc1_tstc; - error = device_register (&kbd_dev); - } else { - lcd_is_enabled = 0; - lcd_disable(); - } - return error; -} diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c deleted file mode 100644 index 9e60c2b..0000000 --- a/board/rbc823/rbc823.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "mpc8xx.h" -#include - -extern int kbd_init(void); -extern int drv_kbd_init(void); - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x1FF7FC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -const uint static_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04, - 0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04, - 0xFFFFFC04, 0xFFFFFC05, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04, - 0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * Test TQ ID string (TQM8xx...) - * If present, check for "L" type (no second DRAM bank), - * otherwise "L" type is assumed as default. - * - * Return 1 for "L" type, 0 else. - */ - -int checkboard (void) -{ - char *s = getenv ("serial#"); - - if (!s || strncmp (s, "TQM8", 4)) { - printf ("### No HW ID - assuming RBC823\n"); - return (0); - } - - puts (s); - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * 1 Bank of 64Mbit x 2 devices - */ - memctl->memc_mptpr = CFG_MPTPR_1BK_4K; - memctl->memc_mar = 0x00000088; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or4 = CFG_OR4_PRELIM; - memctl->memc_br4 = CFG_BR4_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - udelay (200); - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X; - udelay (200); - memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X; - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /* 16: but should be: CFG_MPTPR_1BK_4K */ - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM, - SDRAM_MAX_SIZE); - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - udelay (1000); - } - - /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - udelay (10000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -void doc_init (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig (UPMB, (uint *) static_table, - sizeof (static_table) / sizeof (uint)); - memctl->memc_mbmr = MAMR_DSA_1_CYCL; - - doc_probe (FLASH_BASE1_PRELIM); -} diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds deleted file mode 100644 index 68ca856..0000000 --- a/board/rbc823/u-boot.lds +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/rmu/Makefile b/board/rmu/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/rmu/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/rmu/config.mk b/board/rmu/config.mk deleted file mode 100644 index 7cb374e..0000000 --- a/board/rmu/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# RMU boards -# - -TEXT_BASE = 0xfff00000 diff --git a/board/rmu/flash.c b/board/rmu/flash.c deleted file mode 100644 index 0f2c327..0000000 --- a/board/rmu/flash.c +++ /dev/null @@ -1,540 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_br0, memctl->memc_or0); - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - debug ("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[0]); -#endif - -#if defined(CFG_ENV_ADDR_REDUND) || defined(CFG_ENV_OFFSET_REDUND) - debug ("Protect redundand environment: %08lx ... %08lx\n", - (ulong)CFG_ENV_ADDR_REDUND, - (ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE - 1); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - debug ("## Final Flash bank size: %08lx\n", size_b0); - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0xAAAAAAAA ; - addr[0x555] = 0x55555555 ; - addr[0xAAA] = 0x90909090 ; - - value = addr[0] ; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value & 0x00FF00FF) { - case (AMD_ID_LV400T & 0x00FF00FF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & 0x00FF00FF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & 0x00FF00FF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & 0x00FF00FF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /*%%% Size doubled by yooth */ - break; /* => 4 MB */ - - case (AMD_ID_LV160T & 0x00FF00FF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & 0x00FF00FF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00800000; - break; /* => 8 MB */ - case (AMD_ID_LV320T & 0x00FF00FF): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_LV320B & 0x00FF00FF): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x01000000; - break; /* => 16 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/rmu/rmu.c b/board/rmu/rmu.c deleted file mode 100644 index 8cb03c7..0000000 --- a/board/rmu/rmu.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, - 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, - 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - * (Initialization code at 0x36) - */ - 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, - 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RMU\n") ; - return (0) ; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CFG_MPTPR; - - memctl->memc_mar = 0x00000088; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - - memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size, - * 9 column mode - */ - - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - /* - * Final mapping: - */ - - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - udelay (1000); - - return (size9); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/rmu/u-boot.lds b/board/rmu/u-boot.lds deleted file mode 100644 index 049f990..0000000 --- a/board/rmu/u-boot.lds +++ /dev/null @@ -1,142 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) -/* XXX ? - . = env_offset; -*/ - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/rmu/u-boot.lds.debug b/board/rmu/u-boot.lds.debug deleted file mode 100644 index 894b9bd..0000000 --- a/board/rmu/u-boot.lds.debug +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/rpxsuper/Makefile b/board/rpxsuper/Makefile deleted file mode 100644 index 4535106..0000000 --- a/board/rpxsuper/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := rpxsuper.o flash.o mii_phy.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/rpxsuper/config.mk b/board/rpxsuper/config.mk deleted file mode 100644 index 4b8c5d3..0000000 --- a/board/rpxsuper/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MBX8xx boards -# - -TEXT_BASE = 0x80F00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c deleted file mode 100644 index d80e778..0000000 --- a/board/rpxsuper/flash.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AMD 29F080B devices - * Added support for 64bit and AMD 29DL323B - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -#define RD_SWP32(x) in_le32((volatile u32*)x) - -/*----------------------------------------------------------------------- - * Functions - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD "); - break; - case (FUJ_MANUFACT & FLASH_VENDMASK): - printf ("FUJITSU "); - break; - case (SST_MANUFACT & FLASH_VENDMASK): - printf ("SST "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_DL323B & FLASH_TYPEMASK): - printf("AM29DL323B (32 MBit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - vu_long vendor[2], devid[2]; - ulong base = (ulong)addr; - - /* Reset and Write auto select command: read Manufacturer ID */ - addr[0] = 0xf0f0f0f0; - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x90909090; - addr[1] = 0xf0f0f0f0; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x90909090; - udelay (1000); - - vendor[0] = RD_SWP32(&addr[0]); - vendor[1] = RD_SWP32(&addr[1]); - if (vendor[0] != vendor[1] || vendor[0] != AMD_MANUFACT) { - info->size = 0; - goto out; - } - - devid[0] = RD_SWP32(&addr[2]); - devid[1] = RD_SWP32(&addr[3]); - - if (devid[0] == AMD_ID_DL323B) { - /* - * we have 2 Banks - * Bank 1 (23 Sectors): 0-7=8kbyte, 8-22=64kbyte - * Bank 2 (48 Sectors): 23-70=64kbyte - */ - info->flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_DL323B & FLASH_TYPEMASK); - info->sector_count = 71; - info->size = 4 * (8 * 8 + 63 * 64) * 1024; - } - else { - info->size = 0; - goto out; - } - - /* set up sector start address table */ - for (i = 0; i < 8; i++) { - info->start[i] = base + (i * 0x8000); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x40000) + 8 * 0x8000 - 8 * 0x40000; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address */ - addr = (volatile unsigned long *)(info->start[i]); - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x90909090; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x90909090; - udelay (1000); - base = RD_SWP32(&addr[4]); - base |= RD_SWP32(&addr[5]); - info->protect[i] = base & 0x00010001 ? 1 : 0; - } - addr = (vu_long*)info->start[0]; - -out: - /* reset command */ - addr[0] = 0xf0f0f0f0; - addr[1] = 0xf0f0f0f0; - - return info->size; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x80808080; - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x80808080; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - udelay (100); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - addr[1] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ( (addr[0] & 0x80808080) != 0x80808080 || - (addr[1] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - addr[1] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if ((dest & 0x00000004) == 0) { - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0xA0A0A0A0; - } - else { - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0xA0A0A0A0; - } - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/rpxsuper/mii_phy.c b/board/rpxsuper/mii_phy.c deleted file mode 100644 index ef99aff..0000000 --- a/board/rpxsuper/mii_phy.c +++ /dev/null @@ -1,107 +0,0 @@ -#include -#include -#include "rpxsuper.h" - -#define MII_MDIO 0x01 -#define MII_MDCK 0x02 -#define MII_MDIR 0x04 - -void -mii_discover_phy(void) -{ - int known; - unsigned short phy_reg; - unsigned long phy_id; - - known = 0; - printf("Discovering phy @ 0: "); - phy_id = mii_phy_read(2) << 16; - phy_id |= mii_phy_read(3); - if ((phy_id & 0xFFFFFC00) == 0x00137800) { - printf("Level One "); - if ((phy_id & 0x000003F0) == 0xE0) { - printf("LXT971A Revision %d\n", (int)(phy_id & 0xF)); - known = 1; - } - else printf("unknown type\n"); - } - else printf("unknown OUI = 0x%08lX\n", phy_id); - - phy_reg = mii_phy_read(1); - if (!(phy_reg & 0x0004)) printf("Link is down\n"); - if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n"); - if (phy_reg & 0x0002) printf("Jabber condition detected\n"); - if (phy_reg & 0x0010) printf("Remote fault condition detected \n"); - - if (known) { - phy_reg = mii_phy_read(17); - if (phy_reg & 0x0400) - printf("Phy operating at %d MBit/s in %s-duplex mode\n", - phy_reg & 0x4000 ? 100 : 10, - phy_reg & 0x0200 ? "full" : "half"); - else - printf("bad link!!\n"); -/* -left off: no link, green 100MBit, yellow 10MBit -right off: no activity, green full-duplex, yellow half-duplex -*/ - mii_phy_write(20, 0x0452); - } -} - -unsigned short -mii_phy_read(unsigned short reg) -{ - int i; - unsigned short tmp, val = 0, adr = 0; - t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; - - tmp = 0x6002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - regs->bcsr4 |= MII_MDIR; - for (i = 0; i < 16; i++) { - val <<= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK); - if (regs->bcsr4 & MII_MDIO) val |= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK); - } - return val; -} - -void -mii_phy_write(unsigned short reg, unsigned short val) -{ - int i; - unsigned short tmp, adr = 0; - t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; - - tmp = 0x5002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (val & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - val <<= 1; - } -} diff --git a/board/rpxsuper/readme b/board/rpxsuper/readme deleted file mode 100644 index 21267bd..0000000 --- a/board/rpxsuper/readme +++ /dev/null @@ -1,30 +0,0 @@ -Hi, - -so this is the port to the Embedded Planet RPX Super Board. - -ATTENTION -This code is only tested on the AY-Version, which is an early release with some -hardware bugs. The main problem is that this board uses the default Hard Reset -Configuration Word and not the 4 bytes located at start of FLASH because at -0xFE000000 is no FLASH. The FLASH consists out of 4 chips each 16bits wide. Be -carefull, the bytes are swapped. So DQ0-7 is the high byte, DQ8-15 ist the low -byte. - -The icache can only manually be enabled after reset. -The FLASH and main SDRAM is working with icache enabled. -The local SDRAM can only be used as data memory when icache is enabled. -If U-Boot runs in local SDRAM, TFTP does not work. -The functions in mii_phy.c are all working. Call mii_phy_discover() out of -eth_init() and solve the linker error. -I2C, RTC/NVRAM and PCMCIA are not working yet. - -TODO -The 32MB local SDRAM is working but not shown in the startup messages of -U-Boot. If you locate U-Boot or any other program to this area it won't run. -Turning the ichache off does not solve this problem. - -As I won't buy another RPX Super there might be some little work to do for you -getting this U-Boot port running on the final board. - - -frank.morauf@salzbrenner.com diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c deleted file mode 100644 index b4331f1..0000000 --- a/board/rpxsuper/rpxsuper.c +++ /dev/null @@ -1,305 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "rpxsuper.h" - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 1, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 1, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ - /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Setup CS4 to enable the Board Control/Status registers. - * Otherwise the smcs won't work. -*/ -int board_early_init_f (void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - memctl->memc_br4 = CFG_BR4_PRELIM; - memctl->memc_or4 = CFG_OR4_PRELIM; - regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */ - regs->bcsr2 = 0x20; /* mut be written to enable writing FLASH */ - return 0; -} - -void -reset_phy(void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; - regs->bcsr4 = 0xC3; -} - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; - printf ("Board: Embedded Planet RPX Super, Revision %d\n", - regs->bcsr0 >> 4); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr; - ulong psdmr, lsdmr, bcr; - long size = 0; - int i; - - psdmr = CFG_PSDMR; - lsdmr = CFG_LSDMR; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - size = CFG_SDRAM0_SIZE; - bcr = immap->im_siu_conf.sc_bcr; - immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM); - - memctl->memc_mptpr = CFG_MPTPR; - - ramaddr = (uchar *)(CFG_SDRAM0_BASE); - memctl->memc_psrt = CFG_PSRT; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - immap->im_siu_conf.sc_bcr = bcr; - -#ifndef CFG_RAMBOOT -/* size += CFG_SDRAM1_SIZE; */ - ramaddr = (uchar *)(CFG_SDRAM1_BASE); - memctl->memc_lsrt = CFG_LSRT; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; -#endif - - /* return total ram size */ - return (size * 1024 * 1024); -} diff --git a/board/rpxsuper/rpxsuper.h b/board/rpxsuper/rpxsuper.h deleted file mode 100644 index af31060..0000000 --- a/board/rpxsuper/rpxsuper.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __RPX8260_H__ -#define __RPX8260_H__ - -typedef struct tt_rpx_regs -{ - volatile unsigned char bcsr0; - volatile unsigned char bcsr1; - volatile unsigned char bcsr2; - volatile unsigned char bcsr3; - volatile unsigned char bcsr4; - volatile unsigned char bcsr5; - volatile unsigned char bcsr6; - volatile unsigned char bcsr7; - volatile unsigned char bcsr8; - volatile unsigned char bcsr9; - volatile unsigned char bcsr10; - volatile unsigned char bcsr11; - volatile unsigned char bcsr12; - volatile unsigned char bcsr13; - volatile unsigned char bcsr14; - volatile unsigned char bcsr15; -} t_rpx_regs; -typedef t_rpx_regs* tp_rpx_regs; - -#endif diff --git a/board/rpxsuper/u-boot.lds b/board/rpxsuper/u-boot.lds deleted file mode 100644 index 9e623d0..0000000 --- a/board/rpxsuper/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/rsdproto/Makefile b/board/rsdproto/Makefile deleted file mode 100644 index 9934787..0000000 --- a/board/rsdproto/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := rsdproto.o flash.o -SOBJS := flash_asm.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/rsdproto/config.mk b/board/rsdproto/config.mk deleted file mode 100644 index 5844ec1..0000000 --- a/board/rsdproto/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MBX8xx boards -# - -TEXT_BASE = 0xff000000 -/*TEXT_BASE = 0x00200000 */ diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c deleted file mode 100644 index 5ad3218..0000000 --- a/board/rsdproto/flash.c +++ /dev/null @@ -1,402 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AM290[48]0B devices - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* flash hardware ids */ -#define VENDOR_AMD 0x0001 -#define AMD_29DL323C_B 0x2253 - -/* Define this to include autoselect sequence in flash_init(). Does NOT - * work when executing from flash itself, so this should be turned - * on only when debugging the RAM version. - */ -#undef WITH_AUTOSELECT - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if 1 -#define D(x) -#else -#define D(x) printf x -#endif - -/*----------------------------------------------------------------------- - * Functions - */ - -static unsigned char write_ull(flash_info_t *info, - unsigned long address, - volatile unsigned long long data); - -/* from flash_asm.S */ -extern void ull_write(unsigned long long volatile *address, - unsigned long long volatile *data); -extern void ull_read(unsigned long long volatile *address, - unsigned long long volatile *data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong addr; - -#ifdef WITH_AUTOSELECT - { - unsigned long long *f_addr = (unsigned long long *)PHYS_FLASH; - unsigned long long f_command, vendor, device; - /* Perform Autoselect */ - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x0090009000900090ULL; - ull_write(&f_addr[0x555], &f_command); - ull_read(&f_addr[0], &vendor); - vendor &= 0xffff; - ull_read(&f_addr[1], &device); - device &= 0xffff; - f_command = 0x00F000F000F000F0ULL; - ull_write(&f_addr[0x555], &f_command); - if (vendor != VENDOR_AMD || device != AMD_29DL323C_B) - return 0; - } -#endif - - /* Init: no FLASHes known */ - for (i=0; i= PHYS_FLASH - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[1]); -#endif - - return flash_info[0].size + flash_info[1].size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id >> 16) { - case VENDOR_AMD: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_29DL323C_B: - printf ("AM29DL323CB (32 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start; - unsigned long long volatile *f_addr; - unsigned long long volatile f_command; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x0080008000800080ULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (l_sect = -1, sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - - f_addr = - (unsigned long long *)(info->start[sect]); - f_command = 0x0030003000300030ULL; - ull_write(f_addr, &f_command); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - do - { - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) - { /* write reset command, command address is unimportant */ - /* this command turns the flash back to read mode */ - f_addr = - (unsigned long long *)(info->start[l_sect]); - f_command = 0x00F000F000F000F0ULL; - ull_write(f_addr, &f_command); - printf (" timeout\n"); - return 1; - } - } while(*f_addr != 0xFFFFFFFFFFFFFFFFULL); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - unsigned long cp, wp; - unsigned long long data; - int i, l, rc; - - wp = (addr & ~7); /* get lower long long aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<8; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_ull(info, wp, data)) != 0) { - return rc; - } - wp += 4; - } - - /* - * handle long long aligned part - */ - while (cnt >= 8) { - data = 0; - for (i=0; i<8; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_ull(info, wp, data)) != 0) { - return rc; - } - wp += 8; - cnt -= 8; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<8; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return write_ull(info, wp, data); -} - -/*--------------------------------------------------------------------------- -* -* FUNCTION NAME: write_ull -* -* DESCRIPTION: writes 8 bytes to flash -* -* EXTERNAL EFFECT: nothing -* -* PARAMETERS: 32 bit long pointer to address, 64 bit long pointer to data -* -* RETURNS: 0 if OK, 1 if timeout, 4 if parameter error -*--------------------------------------------------------------------------*/ - -static unsigned char write_ull(flash_info_t *info, - unsigned long address, - volatile unsigned long long data) -{ - static unsigned long long f_command; - static unsigned long long *f_addr; - ulong start; - - /* address muss be 8-aligned! */ - if (address & 0x7) - return ERR_ALIGN; - - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x00A000A000A000A0ULL; - ull_write(&f_addr[0x555], &f_command); - - f_addr = (unsigned long long *)address; - f_command = data; - ull_write(f_addr, &f_command); - - start = get_timer (0); - do - { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) - { - /* write reset command, command address is unimportant */ - /* this command turns the flash back to read mode */ - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00F000F000F000F0ULL; - ull_write(f_addr, &f_command); - return ERR_TIMOUT; - } - } while(*((unsigned long long *)address) != data); - - return 0; -} diff --git a/board/rsdproto/flash_asm.S b/board/rsdproto/flash_asm.S deleted file mode 100644 index 557cac0..0000000 --- a/board/rsdproto/flash_asm.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * -*- mode:c -*- - * - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * void ull_write(unsigned long long volatile *address, - * unsigned long long volatile *data) - * r3 = address - * r4 = data - * - * void ull_read(unsigned long long volatile *address, - * unsigned long long volatile *data) - * r3 = address - * r4 = data - * - * Uses the floating point unit to read and write 64 bit wide - * data (unsigned long long) on the 60x bus. This is necessary - * because all 4 flash chips use the /WE line from byte lane 0 - * - * IMPORTANT: data should always be 8-aligned, otherwise an exception will - * occur. - */ - -#include -#include - - .globl ull_write -ull_write: - lfd 0,0(r4) - stfd 0,0(r3) - blr - - .globl ull_read -ull_read: - lfd 0, 0(r3) - stfd 0, 0(r4) - blr diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c deleted file mode 100644 index bf4fd53..0000000 --- a/board/rsdproto/rsdproto.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* define to initialise the SDRAM on the local bus */ -#undef INIT_LOCAL_BUS_SDRAM - -/* I2C Bus adresses for PPC & Protocol board */ -#define PPC8260_I2C_ADR 0x30 /*(0)011.0000 */ -#define LM84_PPC_I2C_ADR 0x2A /*(0)010.1010 */ -#define LM84_SHARC_I2C_ADR 0x29 /*(0)010.1001 */ -#define VIRTEX_I2C_ADR 0x25 /*(0)010.0101 */ -#define X24645_PPC_I2C_ADR 0x00 /*(0)00X.XXXX -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */ -#define RS5C372_PPC_I2C_ADR 0x32 /*(0)011.0010 -> this adress is programmed by the manufacturer and cannot be changed !!! */ - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 0, 0, 0 }, - /* PA30 */ { 0, 0, 0, 0, 0, 0 }, - /* PA29 */ { 0, 0, 0, 0, 0, 0 }, - /* PA28 */ { 0, 0, 0, 0, 0, 0 }, - /* PA27 */ { 0, 0, 0, 0, 0, 0 }, - /* PA26 */ { 0, 0, 0, 0, 0, 0 }, - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, - /* PA21 */ { 0, 0, 0, 0, 0, 0 }, - /* PA20 */ { 0, 0, 0, 0, 0, 0 }, - /* PA19 */ { 0, 0, 0, 0, 0, 0 }, - /* PA18 */ { 0, 0, 0, 0, 0, 0 }, - /* PA17 */ { 0, 0, 0, 0, 0, 0 }, - /* PA16 */ { 0, 0, 0, 0, 0, 0 }, - /* PA15 */ { 0, 0, 0, 0, 0, 0 }, - /* PA14 */ { 0, 0, 0, 0, 0, 0 }, - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, - /* PA9 */ { 0, 0, 0, 0, 0, 0 }, - /* PA8 */ { 0, 0, 0, 0, 0, 0 }, - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, - /* PA0 */ { 0, 0, 0, 0, 0, 0 } - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* ETHRXCLK: CLK14 */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* ETHTXCLK: CLK15 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART CD/ */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDC: GP */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDIO: GP */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, - /* PC0 */ { 0, 0, 0, 0, 0, 0 } - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -struct tm { - unsigned int tm_sec; - unsigned int tm_min; - unsigned int tm_hour; - unsigned int tm_wday; - unsigned int tm_mday; - unsigned int tm_mon; - unsigned int tm_year; -}; - -void read_RS5C372_time (struct tm *timedate) -{ - unsigned char buffer[8]; - -#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) - - if (i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) { - timedate->tm_sec = BCD_TO_BIN (buffer[0]); - timedate->tm_min = BCD_TO_BIN (buffer[1]); - timedate->tm_hour = BCD_TO_BIN (buffer[2]); - timedate->tm_wday = BCD_TO_BIN (buffer[3]); - timedate->tm_mday = BCD_TO_BIN (buffer[4]); - timedate->tm_mon = BCD_TO_BIN (buffer[5]); - timedate->tm_year = BCD_TO_BIN (buffer[6]) + 2000; - } else { - /*printf("i2c error %02x\n", rc); */ - memset (timedate, 0, sizeof (struct tm)); - } -} - -/* ------------------------------------------------------------------------- */ - -int read_LM84_temp (int address) -{ - unsigned char buffer[8]; - /*int rc;*/ - - if (i2c_read (address, 0, 1, buffer, 1)) { - return (int) buffer[0]; - } else { - /*printf("i2c error %02x\n", rc); */ - return -42; - } -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - struct tm timedate; - unsigned int ppctemp, prottemp; - - puts ("Board: Rohde & Schwarz 8260 Protocol Board\n"); - - /* initialise i2c */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - - read_RS5C372_time (&timedate); - printf (" Time: %02d:%02d:%02d\n", - timedate.tm_hour, timedate.tm_min, timedate.tm_sec); - printf (" Date: %02d-%02d-%04d\n", - timedate.tm_mday, timedate.tm_mon, timedate.tm_year); - ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR); - prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR); - printf (" Temp: PPC %d C, Protocol Board %d C\n", - ppctemp, prottemp); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations while still - * running in flash - */ - -int misc_init_f (void) -{ - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifdef INIT_LOCAL_BUS_SDRAM - volatile uchar *ramaddr8; -#endif - volatile ulong *ramaddr32; - ulong sdmr; - int i; - - /* - * Only initialize SDRAM when running from FLASH. - * When running from RAM, don't touch it. - */ - if ((ulong) initdram & 0xff000000) { - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x01267893; - immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_lcl_acr = 0x02; - immap->im_siu_conf.sc_lcl_alrh = 0x01234567; - immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; - /* - * Program local/60x bus Transfer Error Status and Control Regs: - * Disable parity errors - */ - immap->im_siu_conf.sc_tescr1 = 0x00040000; - immap->im_siu_conf.sc_ltescr1 = 0x00040000; - - /* - * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2) - * - * The appropriate BRx/ORx registers have already - * been set when we get here (see cpu_init_f). The - * SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - memctl->memc_mptpr = 0x2000; - memctl->memc_mar = 0x0200; -#ifdef INIT_LOCAL_BUS_SDRAM - /* initialise local bus ram - * - * (using the PSRMR_ definitions is NOT an error here - * - the LSDMR has the same fields as the PSDMR!) - */ - memctl->memc_lsrt = 0x0b; - memctl->memc_lurt = 0x00; - ramaddr = (uchar *) PHYS_SDRAM_LOCAL; - sdmr = CFG_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); - memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA; - *ramaddr = 0xff; - for (i = 0; i < 8; i++) { - memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR; - *ramaddr = 0xff; - } - memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW; - *ramaddr = 0xff; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_NORM; -#endif - /* initialise 60x bus ram */ - memctl->memc_psrt = 0x0b; - memctl->memc_purt = 0x08; - ramaddr32 = (ulong *) PHYS_SDRAM_60X; - sdmr = CFG_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); - memctl->memc_psdmr = sdmr | PSDMR_OP_PREA; - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - } - memctl->memc_psdmr = sdmr | PSDMR_OP_MRW; - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - } - - /* return the size of the 60x bus ram */ - return PHYS_SDRAM_60X_SIZE; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations after monitor - * has been relocated into ram - */ - -int misc_init_r (void) -{ - printf ("misc_init_r\n"); - return (0); -} diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds deleted file mode 100644 index 70fc3a5..0000000 --- a/board/rsdproto/u-boot.lds +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - /*. = env_offset; */ - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sacsng/Makefile b/board/sacsng/Makefile deleted file mode 100644 index baefa4a..0000000 --- a/board/sacsng/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := sacsng.o flash.o clkinit.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c deleted file mode 100644 index ea4c65d..0000000 --- a/board/sacsng/clkinit.c +++ /dev/null @@ -1,1025 +0,0 @@ -/* - * (C) Copyright 2002 - * Custom IDEAS, Inc. - * Jon Diekema - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#include "clkinit.h" - -int Daq64xSampling = 0; - - -void Daq_BRG_Reset(uint brg) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - *brg_ptr |= CPM_BRG_RST; - *brg_ptr &= ~CPM_BRG_RST; -} - -void Daq_BRG_Disable(uint brg) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - *brg_ptr &= ~CPM_BRG_EN; -} - -void Daq_BRG_Enable(uint brg) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - *brg_ptr |= CPM_BRG_EN; -} - -uint Daq_BRG_Get_Div16(uint brg) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - if (*brg_ptr & CPM_BRG_DIV16) { - /* DIV16 active */ - return (TRUE); - } - else { - /* DIV16 inactive */ - return (FALSE); - } -} - -void Daq_BRG_Set_Div16(uint brg, uint div16) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - if (div16) { - /* DIV16 active */ - *brg_ptr |= CPM_BRG_DIV16; - } - else { - /* DIV16 inactive */ - *brg_ptr &= ~CPM_BRG_DIV16; - } -} - -uint Daq_BRG_Get_Count(uint brg) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - uint *brg_ptr; - uint brg_cnt; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - /* Get the clock divider - * - * Note: A clock divider of 0 means divide by 1, - * therefore we need to add 1 to the count. - */ - brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT; - brg_cnt++; - if (*brg_ptr & CPM_BRG_DIV16) { - brg_cnt *= 16; - } - - return (brg_cnt); -} - -void Daq_BRG_Set_Count(uint brg, uint brg_cnt) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - /* - * Note: A clock divider of 0 means divide by 1, - * therefore we need to subtract 1 from the count. - */ - if (brg_cnt > 4096) { - /* Prescale = Divide by 16 */ - *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) | - (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT); - *brg_ptr |= CPM_BRG_DIV16; - } - else { - /* Prescale = Divide by 1 */ - *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) | - ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT); - *brg_ptr &= ~CPM_BRG_DIV16; - } -} - -uint Daq_BRG_Get_ExtClk(uint brg) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT); -} - -char* Daq_BRG_Get_ExtClk_Description(uint brg) -{ - uint extc; - - extc = Daq_BRG_Get_ExtClk(brg); - - switch (brg + 1) { - case 1: - case 2: - case 5: - case 6: { - switch (extc) { - case 0: { - return ("BRG_INT"); - } - case 1: { - return ("CLK3"); - } - case 2: { - return ("CLK5"); - } - } - return ("??1245??"); - } - case 3: - case 4: - case 7: - case 8: { - switch (extc) { - case 0: { - return ("BRG_INT"); - } - case 1: { - return ("CLK9"); - } - case 2: { - return ("CLK15"); - } - } - return ("??3478??"); - } - } - return ("??9876??"); -} - -void Daq_BRG_Set_ExtClk(uint brg, uint extc) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - uint *brg_ptr; - - brg_ptr = (uint *)&immr->im_brgc1; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg -= 4; - } - brg_ptr += brg; - - *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) | - ((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK); -} - -uint Daq_BRG_Rate(uint brg) -{ - DECLARE_GLOBAL_DATA_PTR; - volatile immap_t *immr = (immap_t *)CFG_IMMR; - uint *brg_ptr; - uint brg_cnt; - uint brg_freq = 0; - - brg_ptr = (uint *)&immr->im_brgc1; - brg_ptr += brg; - if (brg >= 5) { - brg_ptr = (uint *)&immr->im_brgc5; - brg_ptr += (brg - 4); - } - - brg_cnt = Daq_BRG_Get_Count(brg); - - switch (Daq_BRG_Get_ExtClk(brg)) { - case CPM_BRG_EXTC_CLK3: - case CPM_BRG_EXTC_CLK5: { - brg_freq = brg_cnt; - break; - } - default: { - brg_freq = (uint)BRG_INT_CLK / brg_cnt; - } - } - return (brg_freq); -} - -uint Daq_Get_SampleRate(void) -{ - /* - * Read the BRG's to return the actual sample rate. - */ - return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR)); -} - -void Daq_Init_Clocks(int sample_rate, int sample_64x) -{ - DECLARE_GLOBAL_DATA_PTR; - volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */); - uint mclk_divisor; /* MCLK divisor */ - int flag; /* Interrupt state */ - - /* Save off the clocking data */ - Daq64xSampling = sample_64x; - - /* - * Limit the sample rate to some sensible values. - */ - if (sample_rate > MAX_64x_SAMPLE_RATE) { - sample_rate = MAX_64x_SAMPLE_RATE; - } - if (sample_rate < MIN_SAMPLE_RATE) { - sample_rate = MIN_SAMPLE_RATE; - } - - /* - * Initialize the MCLK/SCLK/LRCLK baud rate generators. - */ - - /* Setup MCLK */ - Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK); - - /* Setup SCLK */ -# ifdef RUN_SCLK_ON_BRG_INT - Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK); -# else - Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9); -# endif - - /* Setup LRCLK */ -# ifdef RUN_LRCLK_ON_BRG_INT - Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK); -# else - Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5); -# endif - - /* - * Dynamically adjust MCLK based on the new sample rate. - */ - - /* Compute the divisors */ - mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR); - - /* - * Disable interrupt and save the current state - */ - flag = disable_interrupts(); - - /* Setup MCLK */ - Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor); - - /* Setup SCLK */ -# ifdef RUN_SCLK_ON_BRG_INT - Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR); -# else - Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR); -# endif - -# ifdef RUN_LRCLK_ON_BRG_INT - Daq_BRG_Set_Count(LRCLK_BRG, - mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR); -# else - Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR); -# endif - - /* - * Restore the Interrupt state - */ - if (flag) { - enable_interrupts(); - } - - /* Enable the clock drivers */ - iopa->pdat &= ~SLRCLK_EN_MASK; -} - -void Daq_Stop_Clocks(void) - -{ -#ifdef TIGHTEN_UP_BRG_TIMING - volatile immap_t *immr = (immap_t *)CFG_IMMR; - register uint mclk_brg; /* MCLK BRG value */ - register uint sclk_brg; /* SCLK BRG value */ - register uint lrclk_brg; /* LRCLK BRG value */ - unsigned long flag; /* Interrupt flags */ -#endif - -# ifdef TIGHTEN_UP_BRG_TIMING - /* - * Obtain MCLK BRG reset/disabled value - */ -# if (MCLK_BRG == 0) - mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 1) - mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 2) - mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 3) - mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 4) - mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 5) - mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 6) - mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (MCLK_BRG == 7) - mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif - - /* - * Obtain SCLK BRG reset/disabled value - */ -# if (SCLK_BRG == 0) - sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 1) - sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 2) - sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 3) - sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 4) - sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 5) - sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 6) - sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (SCLK_BRG == 7) - sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif - - /* - * Obtain LRCLK BRG reset/disabled value - */ -# if (LRCLK_BRG == 0) - lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 1) - lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 2) - lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 3) - lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 4) - lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 5) - lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 6) - lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 7) - lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN; -# endif - - /* - * Disable interrupt and save the current state - */ - flag = disable_interrupts(); - - /* - * Set reset on MCLK BRG - */ -# if (MCLK_BRG == 0) - *IM_BRGC1 = mclk_brg; -# endif -# if (MCLK_BRG == 1) - *IM_BRGC2 = mclk_brg; -# endif -# if (MCLK_BRG == 2) - *IM_BRGC3 = mclk_brg; -# endif -# if (MCLK_BRG == 3) - *IM_BRGC4 = mclk_brg; -# endif -# if (MCLK_BRG == 4) - *IM_BRGC5 = mclk_brg; -# endif -# if (MCLK_BRG == 5) - *IM_BRGC6 = mclk_brg; -# endif -# if (MCLK_BRG == 6) - *IM_BRGC7 = mclk_brg; -# endif -# if (MCLK_BRG == 7) - *IM_BRGC8 = mclk_brg; -# endif - - /* - * Set reset on SCLK BRG - */ -# if (SCLK_BRG == 0) - *IM_BRGC1 = sclk_brg; -# endif -# if (SCLK_BRG == 1) - *IM_BRGC2 = sclk_brg; -# endif -# if (SCLK_BRG == 2) - *IM_BRGC3 = sclk_brg; -# endif -# if (SCLK_BRG == 3) - *IM_BRGC4 = sclk_brg; -# endif -# if (SCLK_BRG == 4) - *IM_BRGC5 = sclk_brg; -# endif -# if (SCLK_BRG == 5) - *IM_BRGC6 = sclk_brg; -# endif -# if (SCLK_BRG == 6) - *IM_BRGC7 = sclk_brg; -# endif -# if (SCLK_BRG == 7) - *IM_BRGC8 = sclk_brg; -# endif - - /* - * Set reset on LRCLK BRG - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = lrclk_brg; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = lrclk_brg; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = lrclk_brg; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = lrclk_brg; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = lrclk_brg; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = lrclk_brg; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = lrclk_brg; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = lrclk_brg; -# endif - - /* - * Clear reset on MCLK BRG - */ -# if (MCLK_BRG == 0) - *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 1) - *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 2) - *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 3) - *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 4) - *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 5) - *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 6) - *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST; -# endif -# if (MCLK_BRG == 7) - *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST; -# endif - - /* - * Clear reset on SCLK BRG - */ -# if (SCLK_BRG == 0) - *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 1) - *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 2) - *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 3) - *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 4) - *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 5) - *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 6) - *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST; -# endif -# if (SCLK_BRG == 7) - *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST; -# endif - - /* - * Clear reset on LRCLK BRG - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST; -# endif - - /* - * Restore the Interrupt state - */ - if (flag) { - enable_interrupts(); - } -# else - /* - * Reset the clocks - */ - Daq_BRG_Reset(MCLK_BRG); - Daq_BRG_Reset(SCLK_BRG); - Daq_BRG_Reset(LRCLK_BRG); -# endif -} - -void Daq_Start_Clocks(int sample_rate) - -{ -#ifdef TIGHTEN_UP_BRG_TIMING - volatile immap_t *immr = (immap_t *)CFG_IMMR; - - register uint mclk_brg; /* MCLK BRG value */ - register uint sclk_brg; /* SCLK BRG value */ - register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */ - register uint real_lrclk_brg; /* Permanent LRCLK BRG value */ - uint lrclk_brg; /* LRCLK BRG value */ - unsigned long flags; /* Interrupt flags */ - uint sclk_cnt; /* SCLK count */ - uint delay_cnt; /* Delay count */ -#endif - -# ifdef TIGHTEN_UP_BRG_TIMING - /* - * Obtain the enabled MCLK BRG value - */ -# if (MCLK_BRG == 0) - mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 1) - mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 2) - mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 3) - mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 4) - mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 5) - mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 6) - mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (MCLK_BRG == 7) - mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif - - /* - * Obtain the enabled SCLK BRG value - */ -# if (SCLK_BRG == 0) - sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 1) - sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 2) - sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 3) - sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 4) - sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 5) - sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 6) - sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (SCLK_BRG == 7) - sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif - - /* - * Obtain the enabled LRCLK BRG value - */ -# if (LRCLK_BRG == 0) - lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 1) - lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 2) - lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 3) - lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 4) - lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 5) - lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 6) - lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif -# if (LRCLK_BRG == 7) - lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN; -# endif - - /* Save off the real LRCLK value */ - real_lrclk_brg = lrclk_brg; - - /* Obtain the current SCLK count */ - sclk_cnt = ((sclk_brg & 0x00001FFE) >> 1) + 1; - - /* Compute the delay as a function of SCLK count */ - delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6; - if (DaqSampleRate == 43402) { - delay_cnt++; - } - - /* Clear out the count */ - temp_lrclk_brg = sclk_brg & ~0x00001FFE; - - /* Insert the count */ - temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) & 0x00001FFE; - - /* - * Disable interrupt and save the current state - */ - flag = disable_interrupts(); - - /* - * Enable MCLK BRG - */ -# if (MCLK_BRG == 0) - *IM_BRGC1 = mclk_brg; -# endif -# if (MCLK_BRG == 1) - *IM_BRGC2 = mclk_brg; -# endif -# if (MCLK_BRG == 2) - *IM_BRGC3 = mclk_brg; -# endif -# if (MCLK_BRG == 3) - *IM_BRGC4 = mclk_brg; -# endif -# if (MCLK_BRG == 4) - *IM_BRGC5 = mclk_brg; -# endif -# if (MCLK_BRG == 5) - *IM_BRGC6 = mclk_brg; -# endif -# if (MCLK_BRG == 6) - *IM_BRGC7 = mclk_brg; -# endif -# if (MCLK_BRG == 7) - *IM_BRGC8 = mclk_brg; -# endif - - /* - * Enable SCLK BRG - */ -# if (SCLK_BRG == 0) - *IM_BRGC1 = sclk_brg; -# endif -# if (SCLK_BRG == 1) - *IM_BRGC2 = sclk_brg; -# endif -# if (SCLK_BRG == 2) - *IM_BRGC3 = sclk_brg; -# endif -# if (SCLK_BRG == 3) - *IM_BRGC4 = sclk_brg; -# endif -# if (SCLK_BRG == 4) - *IM_BRGC5 = sclk_brg; -# endif -# if (SCLK_BRG == 5) - *IM_BRGC6 = sclk_brg; -# endif -# if (SCLK_BRG == 6) - *IM_BRGC7 = sclk_brg; -# endif -# if (SCLK_BRG == 7) - *IM_BRGC8 = sclk_brg; -# endif - - /* - * Enable LRCLK BRG (1st time - temporary) - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = temp_lrclk_brg; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = temp_lrclk_brg; -# endif - - /* - * Enable LRCLK BRG (2nd time - permanent) - */ -# if (LRCLK_BRG == 0) - *IM_BRGC1 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 1) - *IM_BRGC2 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 2) - *IM_BRGC3 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 3) - *IM_BRGC4 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 4) - *IM_BRGC5 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 5) - *IM_BRGC6 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 6) - *IM_BRGC7 = real_lrclk_brg; -# endif -# if (LRCLK_BRG == 7) - *IM_BRGC8 = real_lrclk_brg; -# endif - - /* - * Restore the Interrupt state - */ - if (flag) { - enable_interrupts(); - } -# else - /* - * Enable the clocks - */ - Daq_BRG_Enable(LRCLK_BRG); - Daq_BRG_Enable(SCLK_BRG); - Daq_BRG_Enable(MCLK_BRG); -# endif -} - -void Daq_Display_Clocks(void) - -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - uint mclk_divisor; /* Detected MCLK divisor */ - uint sclk_divisor; /* Detected SCLK divisor */ - - printf("\nBRG:\n"); - if (immr->im_brgc4 != 0) { - printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, MCLK\n", - immr->im_brgc4, - (uint)&(immr->im_brgc4), - Daq_BRG_Get_Count(3), - Daq_BRG_Get_ExtClk(3), - Daq_BRG_Get_ExtClk_Description(3)); - } - if (immr->im_brgc8 != 0) { - printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCLK\n", - immr->im_brgc8, - (uint)&(immr->im_brgc8), - Daq_BRG_Get_Count(7), - Daq_BRG_Get_ExtClk(7), - Daq_BRG_Get_ExtClk_Description(7)); - } - if (immr->im_brgc6 != 0) { - printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, LRCLK\n", - immr->im_brgc6, - (uint)&(immr->im_brgc6), - Daq_BRG_Get_Count(5), - Daq_BRG_Get_ExtClk(5), - Daq_BRG_Get_ExtClk_Description(5)); - } - if (immr->im_brgc1 != 0) { - printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC1\n", - immr->im_brgc1, - (uint)&(immr->im_brgc1), - Daq_BRG_Get_Count(0), - Daq_BRG_Get_ExtClk(0), - Daq_BRG_Get_ExtClk_Description(0)); - } - if (immr->im_brgc2 != 0) { - printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SMC2\n", - immr->im_brgc2, - (uint)&(immr->im_brgc2), - Daq_BRG_Get_Count(1), - Daq_BRG_Get_ExtClk(1), - Daq_BRG_Get_ExtClk_Description(1)); - } - if (immr->im_brgc3 != 0) { - printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s, SCC1\n", - immr->im_brgc3, - (uint)&(immr->im_brgc3), - Daq_BRG_Get_Count(2), - Daq_BRG_Get_ExtClk(2), - Daq_BRG_Get_ExtClk_Description(2)); - } - if (immr->im_brgc5 != 0) { - printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n", - immr->im_brgc5, - (uint)&(immr->im_brgc5), - Daq_BRG_Get_Count(4), - Daq_BRG_Get_ExtClk(4), - Daq_BRG_Get_ExtClk_Description(4)); - } - if (immr->im_brgc7 != 0) { - printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n", - immr->im_brgc7, - (uint)&(immr->im_brgc7), - Daq_BRG_Get_Count(6), - Daq_BRG_Get_ExtClk(6), - Daq_BRG_Get_ExtClk_Description(6)); - } - -# ifdef RUN_SCLK_ON_BRG_INT - mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG); -# else - mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG); -# endif -# ifdef RUN_LRCLK_ON_BRG_INT - sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG); -# else - sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG); -# endif - - printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor); - printf("\tMCLK %8d Hz, or %3dx SCLK, or %3dx LRCLK\n", - Daq_BRG_Rate(MCLK_BRG), - mclk_divisor, - mclk_divisor * sclk_divisor); -# ifdef RUN_SCLK_ON_BRG_INT - printf("\tSCLK %8d Hz, or %3dx LRCLK\n", - Daq_BRG_Rate(SCLK_BRG), - sclk_divisor); -# else - printf("\tSCLK %8d Hz, or %3dx LRCLK\n", - Daq_BRG_Rate(MCLK_BRG) / mclk_divisor, - sclk_divisor); -# endif -# ifdef RUN_LRCLK_ON_BRG_INT - printf("\tLRCLK %8d Hz\n", - Daq_BRG_Rate(LRCLK_BRG)); -# else -# ifdef RUN_SCLK_ON_BRG_INT - printf("\tLRCLK %8d Hz\n", - Daq_BRG_Rate(SCLK_BRG) / sclk_divisor); -# else - printf("\tLRCLK %8d Hz\n", - Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor)); -# endif -# endif - printf("\n"); -} diff --git a/board/sacsng/clkinit.h b/board/sacsng/clkinit.h deleted file mode 100644 index 011638f..0000000 --- a/board/sacsng/clkinit.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2002 - * Custom IDEAS, Inc. - * Jon Diekema - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef FALSE -#define FALSE 0 -#define TRUE (!FALSE) -#endif - -#define SLRCLK_EN_MASK 0x00040000 /* PA13 - SLRCLK_EN* */ - -#define MIN_SAMPLE_RATE 4000 /* Minimum sample rate */ -#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */ -#define MAX_64x_SAMPLE_RATE 86805 /* Maximum 64x sample rate */ - -#define KHZ ((uint)1000) -#define MHZ ((uint)(1000 * KHZ)) - -#define MCLK_BRG 3 /* MCLK, Master CLocK for the A/D & D/A */ -#define SCLK_BRG 7 /* SCLK, Sample CLocK for the A/D & D/A */ -#define LRCLK_BRG 5 /* LRCLK, L/R CLocK for the A/D & D/A */ - /* 0 == BRG1 (used for SMC1) */ - /* 1 == BRG2 (used for SMC2) */ - /* 2 == BRG3 (used for SCC1) */ - /* 3 == BRG4 (MCLK) */ - /* 4 == BRG5 */ - /* 5 == BRG6 (LRCLK) */ - /* 6 == BRG7 */ - /* 7 == BRG8 (SCLK) */ - -#define MCLK_DIVISOR 4 /* SCLK = MCLK / MCLK_DIVISOR */ -#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128) - /* LRCLK = SCLK / SCLK_DIVISOR */ - -#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing */ -#define RUN_SCLK_ON_BRG_INT /* Run SCLK on BRG_INT instead of MCLK */ - /* The 8260 (Mask B.3) seems to have */ - /* problems generating SCLK from MCLK */ - /* via CLK9. */ -#define RUN_LRCLK_ON_BRG_INT /* Run LRCLK on BRG_INT instead of SCLK */ - /* The 8260 (Mask B.3) seems to have */ - /* problems generating LRCLK from SCLK */ - -#define NUM_LRCLKS_TO_STABILIZE 1 /* Number of LRCLK period (sample) */ - /* to wait for the clock to stabilize */ - -#define CPM_CLK (gd->bd->bi_cpmfreq) -#define DFBRG 4 -#define BRG_INT_CLK (CPM_CLK * 2 / DFBRG) - /* BRG = CPM * 2 / DFBRG (Sect 9.8) */ - /* BRG = CPM * 2 / 4 */ - /* BRG = CPM / 2 */ - -#define CPM_BRG_EXTC_MASK ((uint)0x0000C000) -#define CPM_BRG_EXTC_SHIFT 14 - -#define CPM_BRG_DIV16_MASK ((uint)0x00000001) -#define CPM_BRG_DIV16_SHIFT 1 - -#define CPM_BRG_EXTC_BRGCLK 0 -#define CPM_BRG_EXTC_CLK3 1 -#define CPM_BRG_EXTC_CLK9 CPM_BRG_EXTC_CLK3 -#define CPM_BRG_EXTC_CLK5 2 -#define CPM_BRG_EXTC_CLK15 CPM_BRG_EXTC_CLK5 - -#define IM_BRGC1 ((uint *)0xf00119f0) -#define IM_BRGC2 ((uint *)0xf00119f4) -#define IM_BRGC3 ((uint *)0xf00119f8) -#define IM_BRGC4 ((uint *)0xf00119fc) -#define IM_BRGC5 ((uint *)0xf00115f0) -#define IM_BRGC6 ((uint *)0xf00115f4) -#define IM_BRGC7 ((uint *)0xf00115f8) -#define IM_BRGC8 ((uint *)0xf00115fc) - -/* - * External declarations - */ - -extern int Daq64xSampling; - -extern void Daq_BRG_Reset(uint brg); -extern void Daq_BRG_Run(uint brg); - -extern void Daq_BRG_Disable(uint brg); -extern void Daq_BRG_Enable(uint brg); - -extern uint Daq_BRG_Get_Div16(uint brg); -extern void Daq_BRG_Set_Div16(uint brg, uint div16); - -extern uint Daq_BRG_Get_Count(uint brg); -extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt); - -extern uint Daq_BRG_Get_ExtClk(uint brg); -extern char* Daq_BRG_Get_ExtClk_Description(uint brg); -extern void Daq_BRG_Set_ExtClk(uint brg, uint extc); - -extern uint Daq_BRG_Rate(uint brg); - -extern uint Daq_Get_SampleRate(void); - -extern void Daq_Init_Clocks(int sample_rate, int sample_64x); -extern void Daq_Stop_Clocks(void); -extern void Daq_Start_Clocks(int sample_rate); -extern void Daq_Display_Clocks(void); diff --git a/board/sacsng/config.mk b/board/sacsng/config.mk deleted file mode 100644 index 220b218..0000000 --- a/board/sacsng/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# 82xx boards -# - -TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/sacsng/flash.c b/board/sacsng/flash.c deleted file mode 100644 index 52e01de..0000000 --- a/board/sacsng/flash.c +++ /dev/null @@ -1,523 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -#undef DEBUG - -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -#endif -#ifndef CFG_ENV_SIZE -#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -#endif - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_short *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[1]); -#endif - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - /* - * We only report the primary flash for U-Boot's use. - */ - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_short *addr, flash_info_t *info) -{ - short i; - ushort value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - addr[0x0555] = 0x9090; - __asm__ __volatile__(" sync\n "); - - value = addr[0]; -#ifdef DEBUG - printf("Flash manufacturer 0x%04X\n", value); -#endif - - if(value == (ushort)AMD_MANUFACT) { - info->flash_id = FLASH_MAN_AMD; - } else if (value == (ushort)FUJ_MANUFACT) { - info->flash_id = FLASH_MAN_FUJ; - } else { -#ifdef DEBUG - printf("Unknown flash manufacturer 0x%04X\n", value); -#endif - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ -#ifdef DEBUG - printf("Flash type 0x%04X\n", value); -#endif - - if(value == (ushort)AMD_ID_LV400T) { - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; /* => 0.5 MB */ - } else if(value == (ushort)AMD_ID_LV400B) { - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; /* => 0.5 MB */ - } else if(value == (ushort)AMD_ID_LV800T) { - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MB */ - } else if(value == (ushort)AMD_ID_LV800B) { - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MB */ - } else if(value == (ushort)AMD_ID_LV160T) { - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MB */ - } else if(value == (ushort)AMD_ID_LV160B) { - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MB */ - } else if(value == (ushort)AMD_ID_LV320T) { - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; /* => 4 MB */ - } else if(value == (ushort)AMD_ID_LV320B) { - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; /* => 4 MB */ - } else { -#ifdef DEBUG - printf("Unknown flash type 0x%04X\n", value); - info->size = CFG_FLASH_SIZE; -#else - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ -#endif - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i - 3) * 0x00010000); - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + (i * 0x00010000); - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned short *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned short *)info->start[0]; - - } - - addr[0] = 0xF0F0; /* reset bank */ - __asm__ __volatile__(" sync\n "); - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - addr[0x0555] = 0x8080; - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - __asm__ __volatile__(" sync\n "); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short*)(info->start[sect]); - addr[0] = 0x3030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_short*)(info->start[l_sect]); - while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - addr[0] = 0xF0F0; /* reset bank */ - __asm__ __volatile__(" sync\n "); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_short*)info->start[0]; - addr[0] = 0xF0F0; /* reset bank */ - __asm__ __volatile__(" sync\n "); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - ulong start; - int flag; - int j; - - /* Check if Flash is (sufficiently) erased */ - if (((*(vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* The original routine was designed to write 32 bit words to - * 32 bit wide memory. We have 16 bit wide memory so we do - * two writes. We write the LSB first at dest+2 and then the - * MSB at dest (lousy big endian). - */ - dest += 2; - for(j = 0; j < 2; j++) { - addr[0x0555] = 0xAAAA; - addr[0x02AA] = 0x5555; - addr[0x0555] = 0xA0A0; - __asm__ __volatile__(" sync\n "); - - *((vu_short *)dest) = (ushort)data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while (*(vu_short *)dest != (ushort)data) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - dest -= 2; - data >>= 16; - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/sacsng/ioconfig.h b/board/sacsng/ioconfig.h deleted file mode 100644 index be1ce7c..0000000 --- a/board/sacsng/ioconfig.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * I/O Port configuration table - * - * If conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -#ifdef SKIP -#undef SKIP -#endif - -#ifdef CONF -#undef CONF -#endif - -#ifdef DIN -#undef DIN -#endif - -#ifdef DOUT -#undef DOUT -#endif - -#ifdef GPIO -#undef GPIO -#endif - -#ifdef SPEC -#undef SPEC -#endif - -#ifdef ACTV -#undef ACTV -#endif - -#ifdef OPEN -#undef OPEN -#endif - -#define SKIP 0 /* SKIP over this port */ -#define CONF 1 /* CONFiguration the port */ - -#define DIN 0 /* PDIRx 0: Direction IN */ -#define DOUT 1 /* PDIRx 1: Direction OUT */ - -#define GPIO 0 /* PPARx 0: General Purpose I/O */ -#define SPEC 1 /* PPARx 1: dedicated to a peripheral function, */ - /* i.e. the port has a SPECial use. */ - -#define ACTV 0 /* PODRx 0: ACTiVely driven as an output */ -#define OPEN 1 /* PODRx 1: OPEN-drain driver */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS8* */ - /* PA30 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS7* */ - /* PA29 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS6* */ - /* PA28 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS5* */ - /* PA27 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS4* */ - /* PA26 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS3* */ - /* PA25 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS2* */ - /* PA24 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* RODIS1* */ - /* PA23 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* ODIS_EN* */ - /* PA22 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED2_EN* */ - /* PA21 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* STLED1_EN* */ - /* PA20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED3_EN* */ - /* PA19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PLED2_EN* */ - /* PA18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* PLED1_EN* */ - /* PA17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PA16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* DAC_RST* */ - /* PA15 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH34SDATA_PU */ - /* PA14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* CH12SDATA_PU */ - /* PA13 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SLRCLK_EN* */ - /* PA12 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4ACDC* */ - /* PA11 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4TEDS* */ - /* PA10 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_4XTDS* */ - /* PA9 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3ACDC* */ - /* PA8 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3TEDS* */ - /* PA7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_3XTDS* */ - /* PA6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2ACDC* */ - /* PA5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2TEDS* */ - /* PA4 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_2XTDS* */ - /* PA3 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PA2 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1ACDC* */ - /* PA1 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* MTRX_1TEDS* */ - /* PA0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 } /* MTRX_1XTDS* */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TX_ER */ - /* PB30 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_DV */ - /* PB29 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* FCC2 MII_TX_EN */ - /* PB28 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RX_ER */ - /* PB27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_COL */ - /* PB26 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_CRS */ - /* PB25 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD3 */ - /* PB24 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD2 */ - /* PB23 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD1 */ - /* PB22 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* FCC2 MII_TXD0 */ - /* PB21 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD0 */ - /* PB20 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD1 */ - /* PB19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD2 */ - /* PB18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* FCC2 MII_RXD3 */ - /* PB17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB14 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDC1, BSDATA_ADC12 */ - /* PB13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB12 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCC1, LRCLK */ - /* PB11 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1TXDD1, RSDATA_DAC12 */ - /* PB10 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RXDD1, BSDATA_ADC34 */ - /* PB9 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB8 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* L1RSYNCD1, LRCLK */ - /* PB7 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PB6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* XCITE_SHDN */ - /* PB5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* TRIGGER */ - /* PB4 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* ARM */ - /* PB3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PB2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PB1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PB0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC30 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC29 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK3, MCLK */ - /* PC28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* TOUT2* */ -#ifdef QQQ - /* PC28 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TOUT2* */ -#endif - /* PC27 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK5, SCLK */ - /* PC26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC25 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK7, SCLK */ - /* PC24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC23 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK9, MCLK */ - /* PC22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC21 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO6 (LRCLK) */ - /* PC20 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC19 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK13, MII_RXCLK */ - /* PC18 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* CLK14, MII_TXCLK */ - /* PC17 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* BRGO8 (SCLK) */ - /* PC16 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC15 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC2_TX */ - /* PC14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC13 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB3 */ - /* PC11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* TDM_STRB4 */ - /* PC9 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN3 */ - /* PC8 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN2 */ - /* PC7 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BPDIS_IN1 */ - /* PC6 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PC5 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN2* */ - /* PC4 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* BTST_IN1* */ - /* PC3 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* MUSH_STAT */ - /* PC2 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* OUTDRV_STAT */ - /* PC1 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* PHY_MDIO */ - /* PC0 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* PHY_MDC */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SCC1_RX */ - /* PD30 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SCC1_TX */ - /* PD29 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD28 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD27 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD26 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD25 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD24 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD23 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD22 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD21 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD20 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_ADC_CS* */ - /* PD19 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* SPI_DAC_CS* */ -#if defined(CONFIG_SOFT_SPI) - /* PD18 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_CLK */ - /* PD17 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* SPI_MOSI */ - /* PD16 */ { CONF, GPIO, 0, DIN, ACTV, 0 }, /* SPI_MISO */ -#else - /* PD18 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_CLK */ - /* PD17 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* SPI_MOSI */ - /* PD16 */ { CONF, SPEC, 1, DIN, ACTV, 0 }, /* SPI_MISO */ -#endif -#if defined(CONFIG_SOFT_I2C) - /* PD15 */ { CONF, GPIO, 0, DOUT, OPEN, 1 }, /* I2C_SDA */ - /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* I2C_SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SDA */ - /* PD14 */ { CONF, SPEC, 1, DIN, OPEN, 0 }, /* I2C_SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SDA */ - /* PD14 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* I2C_SCL */ -#endif -#endif - /* PD13 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB1 */ - /* PD12 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* TDM_STRB2 */ - /* PD11 */ { CONF, GPIO, 0, DOUT, ACTV, 0 }, /* N/C */ - /* PD10 */ { CONF, SPEC, 1, DOUT, ACTV, 0 }, /* BRGO4 (MCLK) */ - /* PD9 */ { CONF, SPEC, 0, DOUT, ACTV, 0 }, /* SMC1_TX */ - /* PD8 */ { CONF, SPEC, 0, DIN, ACTV, 0 }, /* SMC1_RX */ - /* PD7 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ - /* PD6 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ - /* PD5 */ { CONF, GPIO, 0, DOUT, ACTV, 1 }, /* N/C */ - /* PD4 */ { CONF, SPEC, 1, DOUT, ACTV, 1 }, /* SMC2_RX */ - /* PD3 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PD2 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PD1 */ { SKIP, GPIO, 0, DIN, ACTV, 0 }, /* pin doesn't exist */ - /* PD0 */ { SKIP, GPIO, 0, DIN, ACTV, 0 } /* pin doesn't exist */ - } -}; diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c deleted file mode 100644 index e50b747..0000000 --- a/board/sacsng/sacsng.c +++ /dev/null @@ -1,890 +0,0 @@ -/* - * (C) Copyright 2002 - * Custom IDEAS, Inc. - * Gerald Van Baren - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -#include -#endif - -#ifdef CONFIG_ETHER_LOOPBACK_TEST -extern void eth_loopback_test(void); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - -extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#include "clkinit.h" -#include "ioconfig.h" /* I/O configuration table */ - -/* - * PBI Page Based Interleaving - * PSDMR_PBI page based interleaving - * 0 bank based interleaving - * External Address Multiplexing (EAMUX) adds a clock to address cycles - * (this can help with marginal board layouts) - * PSDMR_EAMUX adds a clock - * 0 no extra clock - * Buffer Command (BUFCMD) adds a clock to command cycles. - * PSDMR_BUFCMD adds a clock - * 0 no extra clock - */ -#define CONFIG_PBI PSDMR_PBI -#define PESSIMISTIC_SDRAM 0 -#define EAMUX 0 /* EST requires EAMUX */ -#define BUFCMD 0 - -/* - * ADC/DAC Defines: - */ -#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */ -#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */ -#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */ -#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */ -#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */ - -/* - * ADC Defines: - */ -#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */ -#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */ - -#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */ -#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */ - -#define ADC_VREF_CAP 100 /* VREF capacitor in uF */ -#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */ -#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */ -#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500) - /* Wait at least 4100 LRCLK's */ - -#define ADC_REG1_FRAME_START 0x80 /* Frame start */ -#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */ -#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */ -#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */ - -#define ADC_REG2_128x 0x80 /* Oversample at 128x */ -#define ADC_REG2_CAL 0x40 /* System calibration enable */ -#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */ -#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */ -#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */ -#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */ -#define ADC_REG2_DFS 0x02 /* Digital format select */ -#define ADC_REG2_MUTE 0x01 /* Mute */ - -#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */ -#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */ -#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */ -#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */ -#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */ -#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */ -#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */ - -/* - * DAC Defines: - */ - -#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */ - -#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */ -#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */ -#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */ - -#define DAC_REG1_AMUTE 0x80 /* Auto-mute */ - -#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */ -#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */ -#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */ -#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */ -#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */ -#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */ - -#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */ -#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */ -#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */ -#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */ - -#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */ -#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */ -#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */ -#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */ - -#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */ -#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */ -#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */ -#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */ -#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */ -#define DAC_REG5_FREEZE 0x04 /* Freeze */ -#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */ -#define DAC_REG5_RESERVED 0x01 /* Reserved */ - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ - printf ("SACSng\n"); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0; - volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8); - uint psdmr = CFG_PSDMR; - int i; - uint psrt = 14; /* for no SPD */ - uint chipselects = 1; /* for no SPD */ - uint sdram_size = CFG_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CFG_OR2_PRELIM; /* for no SPD */ -#ifdef SDRAM_SPD_ADDR - uint data_width; - uint rows; - uint banks; - uint cols; - uint caslatency; - uint width; - uint rowst; - uint sdam; - uint bsma; - uint sda10; - u_char spd_size; - u_char data; - u_char cksum; - int j; -#endif - -#ifdef SDRAM_SPD_ADDR - /* Keep the compiler from complaining about potentially uninitialized vars */ - data_width = chipselects = rows = banks = cols = caslatency = psrt = 0; - - /* - * Read the SDRAM SPD EEPROM via I2C. - */ - i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); - spd_size = data; - cksum = data; - for(j = 1; j < 64; j++) { /* read only the checksummed bytes */ - /* note: the I2C address autoincrements when alen == 0 */ - i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); - if(j == 5) chipselects = data & 0x0F; - else if(j == 6) data_width = data; - else if(j == 7) data_width |= data << 8; - else if(j == 3) rows = data & 0x0F; - else if(j == 4) cols = data & 0x0F; - else if(j == 12) { - /* - * Refresh rate: this assumes the prescaler is set to - * approximately 1uSec per tick. - */ - switch(data & 0x7F) { - default: - case 0: psrt = 14 ; /* 15.625uS */ break; - case 1: psrt = 2; /* 3.9uS */ break; - case 2: psrt = 6; /* 7.8uS */ break; - case 3: psrt = 29; /* 31.3uS */ break; - case 4: psrt = 60; /* 62.5uS */ break; - case 5: psrt = 120; /* 125uS */ break; - } - } - else if(j == 17) banks = data; - else if(j == 18) { - caslatency = 3; /* default CL */ -#if(PESSIMISTIC_SDRAM) - if((data & 0x04) != 0) caslatency = 3; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x01) != 0) caslatency = 1; -#else - if((data & 0x01) != 0) caslatency = 1; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x04) != 0) caslatency = 3; -#endif - else { - printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n", - data); - } - } - else if(j == 63) { - if(data != cksum) { - printf ("WARNING: Configuration data checksum failure:" - " is 0x%02x, calculated 0x%02x\n", - data, cksum); - } - } - cksum += data; - } - - /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ - if(caslatency < 2) { - printf("WARNING: CL was %d, forcing to 2\n", caslatency); - caslatency = 2; - } - if(rows > 14) { - printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows); - rows = 14; - } - if(cols > 11) { - printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols); - cols = 11; - } - - if((data_width != 64) && (data_width != 72)) - { - printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", - data_width); - } - width = 3; /* 2^3 = 8 bytes = 64 bits wide */ - /* - * Convert banks into log2(banks) - */ - if (banks == 2) banks = 1; - else if(banks == 4) banks = 2; - else if(banks == 8) banks = 3; - - sdram_size = 1 << (rows + cols + banks + width); - -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - rowst = ((32 - 6) - (rows + cols + width)) * 2; -#else - rowst = 32 - (rows + banks + cols + width); -#endif - - or = ~(sdram_size - 1) | /* SDAM address mask */ - ((banks-1) << 13) | /* banks per device */ - (rowst << 9) | /* rowst */ - ((rows - 9) << 6); /* numr */ - - memctl->memc_or2 = or; - - /* - * SDAM specifies the number of columns that are multiplexed - * (reference AN2165/D), defined to be (columns - 6) for page - * interleave, (columns - 8) for bank interleave. - * - * BSMA is 14 - max(rows, cols). The bank select lines come - * into play above the highest "address" line going into the - * the SDRAM. - */ -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - sdam = cols - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam + 2; -#else - sdam = cols - 6; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam; -#endif -#if(PESSIMISTIC_SDRAM) - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_16_CLK |\ - PSDMR_PRETOACT_8W |\ - PSDMR_ACTTORW_8W |\ - PSDMR_WRC_4C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); -#else - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_WRC_1C | /* 1 clock + 7nSec */ - EAMUX |\ - BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); -#endif -#endif - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * Quote from Micron MT48LC8M16A2 data sheet: - * - * "...the SDRAM requires a 100uS delay prior to issuing any - * command other than a COMMAND INHIBIT or NOP. Starting at some - * point during this 100uS period and continuing at least through - * the end of this period, COMMAND INHIBIT or NOP commands should - * be applied." - * - * "Once the 100uS delay has been satisfied with at least one COMMAND - * INHIBIT or NOP command having been applied, a /PRECHARGE command/ - * should be applied. All banks must then be precharged, thereby - * placing the device in the all banks idle state." - * - * "Once in the idle state, /two/ AUTO REFRESH cycles must be - * performed. After the AUTO REFRESH cycles are complete, the - * SDRAM is ready for mode register programming." - * - * (/emphasis/ mine, gvb) - * - * The way I interpret this, Micron start up sequence is: - * 1. Issue a PRECHARGE-BANK command (initial precharge) - * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") - * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands - * 4. Issue a MODE-SET command to initialize the mode register - * - * -------- - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - memctl->memc_mptpr = CFG_MPTPR; - memctl->memc_psrt = psrt; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* - * Do it a second time for the second set of chips if the DIMM has - * two chip selects (double sided). - */ - if(chipselects > 1) { - ramaddr += sdram_size; - - memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size; - memctl->memc_or3 = or; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - } - - /* return total ram size */ - return (sdram_size * chipselects); -} - -/*----------------------------------------------------------------------- - * Board Control Functions - */ -void board_poweroff (void) -{ - while (1); /* hang forever */ -} - - -#ifdef CONFIG_MISC_INIT_R -/* ------------------------------------------------------------------------- */ -int misc_init_r(void) -{ - /* - * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization. - */ - volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */); - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); - - int reg; /* I2C register value */ - char *ep; /* Environment pointer */ - char str_buf[12] ; /* sprintf output buffer */ - int sample_rate; /* ADC/DAC sample rate */ - int sample_64x; /* Use 64/4 clocking for the ADC/DAC */ - int sample_128x; /* Use 128/4 clocking for the ADC/DAC */ - int right_just; /* Is the data to the DAC right justified? */ - int mclk_divide; /* MCLK Divide */ - int quiet; /* Quiet or minimal output mode */ - - quiet = 0; - if ((ep = getenv("quiet")) != NULL) { - quiet = simple_strtol(ep, NULL, 10); - } - else { - setenv("quiet", "0"); - } - - /* - * SACSng custom initialization: - * Start the ADC and DAC clocks, since the Crystal parts do not - * work on the I2C bus until the clocks are running. - */ - - sample_rate = INITIAL_SAMPLE_RATE; - if ((ep = getenv("DaqSampleRate")) != NULL) { - sample_rate = simple_strtol(ep, NULL, 10); - } - - sample_64x = INITIAL_SAMPLE_64X; - sample_128x = INITIAL_SAMPLE_128X; - if ((ep = getenv("Daq64xSampling")) != NULL) { - sample_64x = simple_strtol(ep, NULL, 10); - if (sample_64x) { - sample_128x = 0; - } - else { - sample_128x = 1; - } - } - else { - if ((ep = getenv("Daq128xSampling")) != NULL) { - sample_128x = simple_strtol(ep, NULL, 10); - if (sample_128x) { - sample_64x = 0; - } - else { - sample_64x = 1; - } - } - } - - /* - * Stop the clocks and wait for at least 1 LRCLK period - * to make sure the clocking has really stopped. - */ - Daq_Stop_Clocks(); - udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); - - /* - * Initialize the clocks with the new rates - */ - Daq_Init_Clocks(sample_rate, sample_64x); - sample_rate = Daq_Get_SampleRate(); - - /* - * Start the clocks and wait for at least 1 LRCLK period - * to make sure the clocking has become stable. - */ - Daq_Start_Clocks(sample_rate); - udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); - - sprintf(str_buf, "%d", sample_rate); - setenv("DaqSampleRate", str_buf); - - if (sample_64x) { - setenv("Daq64xSampling", "1"); - setenv("Daq128xSampling", NULL); - } - else { - setenv("Daq64xSampling", NULL); - setenv("Daq128xSampling", "1"); - } - - /* - * Display the ADC/DAC clocking information - */ - if (!quiet) { - Daq_Display_Clocks(); - } - - /* - * Determine the DAC data justification - */ - - right_just = INITIAL_RIGHT_JUST; - if ((ep = getenv("DaqDACRightJustified")) != NULL) { - right_just = simple_strtol(ep, NULL, 10); - } - - sprintf(str_buf, "%d", right_just); - setenv("DaqDACRightJustified", str_buf); - - /* - * Determine the DAC MCLK Divide - */ - - mclk_divide = INITIAL_MCLK_DIVIDE; - if ((ep = getenv("DaqDACMClockDivide")) != NULL) { - mclk_divide = simple_strtol(ep, NULL, 10); - } - - sprintf(str_buf, "%d", mclk_divide); - setenv("DaqDACMClockDivide", str_buf); - - /* - * Initializing the I2C address in the Crystal A/Ds: - * - * 1) Wait for VREF cap to settle (10uSec per uF) - * 2) Release pullup on SDATA - * 3) Write the I2C address to register 6 - * 4) Enable address matching by setting the MSB in register 7 - */ - - if (!quiet) { - printf("Initializing the ADC...\n"); - } - udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */ - - iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */ - udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ - - i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */ - i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */ - ADC_REG7_ADDR_ENABLE); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_HIGH_PASS_DIS | - ADC_REG2_SLAVE_MODE); - - reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F; - if(reg != I2C_ADC_1_ADDR) - printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n", - reg, I2C_ADC_1_ADDR); - - iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */ - udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ - - i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); /* set address (do not set ADDREN yet) */ - - i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_HIGH_PASS_DIS | - ADC_REG2_SLAVE_MODE); - - reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F; - if(reg != I2C_ADC_2_ADDR) - printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n", - reg, I2C_ADC_2_ADDR); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */ - ADC_REG1_FRAME_START | - ADC_REG1_GROUND_CAL); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_CAL | - ADC_REG2_HIGH_PASS_DIS | - ADC_REG2_SLAVE_MODE); - - udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */ - i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */ - - /* - * Now that we have synchronized the ADC's, enable address - * selection on the second ADC as well as the first. - */ - i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE); - - /* - * Initialize the Crystal DAC - * - * Two of the config lines are used for I2C so we have to set them - * to the proper initialization state without inadvertantly - * sending an I2C "start" sequence. When we bring the I2C back to - * the normal state, we send an I2C "stop" sequence. - */ - if (!quiet) { - printf("Initializing the DAC...\n"); - } - - /* - * Bring the I2C clock and data lines low for initialization - */ - I2C_SCL(0); - I2C_DELAY; - I2C_SDA(0); - I2C_ACTIVE; - I2C_DELAY; - - /* Reset the DAC */ - iopa->pdat &= ~DAC_RST_MASK; - udelay(DAC_RESET_DELAY); - - /* Release the DAC reset */ - iopa->pdat |= DAC_RST_MASK; - udelay(DAC_INITIAL_DELAY); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Going into power down - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - DAC_REG5_POWER_DOWN); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Going into power down - * . MCLK divide by 1 - * . MCLK divide by 2 - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - DAC_REG5_POWER_DOWN | - (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); - - /* - * Cause the DAC to: - * Auto-mute disabled - * . Format 0, left justified 24 bits - * . Format 3, right justified 24 bits - * No de-emphasis - * . Single speed mode - * . Double speed mode - */ - i2c_reg_write(I2C_DAC_ADDR, 0x01, - (right_just ? DAC_REG1_RIGHT_JUST_24BIT : - DAC_REG1_LEFT_JUST_24_BIT) | - DAC_REG1_DEM_NO | - (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE)); - - sprintf(str_buf, "%d", - sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE); - setenv("DaqDACFunctionalMode", str_buf); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Remove power down - * . MCLK divide by 1 - * . MCLK divide by 2 - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); - - /* - * Create a I2C stop condition: - * low->high on data while clock is high. - */ - I2C_SCL(1); - I2C_DELAY; - I2C_SDA(1); - I2C_DELAY; - I2C_TRISTATE; - - if (!quiet) { - printf("\n"); - } - -#ifdef CONFIG_ETHER_LOOPBACK_TEST - /* - * Run the Ethernet loopback test - */ - eth_loopback_test (); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - -#ifdef CONFIG_SHOW_BOOT_PROGRESS - /* - * Turn off the RED fail LED now that we are up and running. - */ - status_led_set(STATUS_LED_RED, STATUS_LED_OFF); -#endif - - return 0; -} - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -/* - * Show boot status: flash the LED if something goes wrong, indicating - * that last thing that worked and thus, by implication, what is broken. - * - * This stores the last OK value in RAM so this will not work properly - * before RAM is initialized. Since it is being used for indicating - * boot status (i.e. after RAM is initialized), that is OK. - */ -static void flash_code(uchar number, uchar modulo, uchar digits) -{ - int j; - - /* - * Recursively do upper digits. - */ - if(digits > 1) { - flash_code(number / modulo, modulo, digits - 1); - } - - number = number % modulo; - - /* - * Zero is indicated by one long flash (dash). - */ - if(number == 0) { - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); - udelay(1000000); - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - udelay(200000); - } else { - /* - * Non-zero is indicated by short flashes, one per count. - */ - for(j = 0; j < number; j++) { - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); - udelay(100000); - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - udelay(200000); - } - } - /* - * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total - */ - udelay(700000); -} - -static int last_boot_progress; - -void show_boot_progress (int status) -{ - int i,j; - if(status > 0) { - last_boot_progress = status; - } else { - /* - * If a specific failure code is given, flash this code - * else just use the last success code we've seen - */ - if(status < -1) - last_boot_progress = -status; - - /* - * Flash this code 5 times - */ - for(j=0; j<5; j++) { - /* - * Houston, we have a problem. - * Blink the last OK status which indicates where things failed. - */ - status_led_set(STATUS_LED_RED, STATUS_LED_ON); - flash_code(last_boot_progress, 5, 3); - - /* - * Delay 5 seconds between repetitions, - * with the fault LED blinking - */ - for(i=0; i<5; i++) { - status_led_set(STATUS_LED_RED, STATUS_LED_OFF); - udelay(500000); - status_led_set(STATUS_LED_RED, STATUS_LED_ON); - udelay(500000); - } - } - - /* - * Reset the board to retry initialization. - */ - do_reset (NULL, 0, 0, NULL); - } -} -#endif /* CONFIG_SHOW_BOOT_PROGRESS */ - - -/* - * The following are used to control the SPI chip selects for the SPI command. - */ -#if (CONFIG_COMMANDS & CFG_CMD_SPI) - -#define SPI_ADC_CS_MASK 0x00000800 -#define SPI_DAC_CS_MASK 0x00001000 - -void spi_adc_chipsel(int cs) -{ - volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); - - if(cs) - iopd->pdat &= ~SPI_ADC_CS_MASK; /* activate the chip select */ - else - iopd->pdat |= SPI_ADC_CS_MASK; /* deactivate the chip select */ -} - -void spi_dac_chipsel(int cs) -{ - volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); - - if(cs) - iopd->pdat &= ~SPI_DAC_CS_MASK; /* activate the chip select */ - else - iopd->pdat |= SPI_DAC_CS_MASK; /* deactivate the chip select */ -} - -/* - * The SPI command uses this table of functions for controlling the SPI - * chip selects: it calls the appropriate function to control the SPI - * chip selects. - */ -spi_chipsel_type spi_chipsel[] = { - spi_adc_chipsel, - spi_dac_chipsel -}; -int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); - -#endif /* CFG_CMD_SPI */ - -#endif /* CONFIG_MISC_INIT_R */ - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - return 0; /* No hotkeys supported */ -} - -#endif diff --git a/board/sacsng/u-boot.lds b/board/sacsng/u-boot.lds deleted file mode 100644 index 9e623d0..0000000 --- a/board/sacsng/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c deleted file mode 100644 index 762fb73..0000000 --- a/board/sandburst/common/flash.c +++ /dev/null @@ -1,512 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu - * Add support for Am29F016D and dynamic switch setting. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * Ported from Ebony flash support - * Travis B. Sawyer - * Sandburst Corporation - */ -#include -#include -#include - - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { - {0xfff80000} /* Boot Flash */ -}; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i=0; iflash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; - } - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); - - /* Write auto select command: read Manufacturer ID */ - udelay(10000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - udelay(1000); - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - udelay(1000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - udelay(1000); - - value = addr2[0]; - - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; /* => 512 kb */ - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* reset to return to reading data */ - addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - DEBUGF("Erasing sector %p\n", addr2); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c deleted file mode 100644 index 859dd7a..0000000 --- a/board/sandburst/common/ppc440gx_i2c.c +++ /dev/null @@ -1,512 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by - * Travis B. Sawyer - * Sandburst Corporation. - */ -#include -#include -#if defined(CONFIG_440) -# include <440_i2c.h> -#else -# include <405gp_i2c.h> -#endif -#include -#include <440_i2c.h> -#include -#include "ppc440gx_i2c.h" - -#ifdef CONFIG_I2C_BUS1 - -#define IIC_OK 0 -#define IIC_NOK 1 -#define IIC_NOK_LA 2 /* Lost arbitration */ -#define IIC_NOK_ICT 3 /* Incomplete transfer */ -#define IIC_NOK_XFRA 4 /* Transfer aborted */ -#define IIC_NOK_DATA 5 /* No data in buffer */ -#define IIC_NOK_TOUT 6 /* Transfer timeout */ - -#define IIC_TIMEOUT 1 /* 1 second */ -#if defined(CFG_I2C_NOPROBES) -static uchar i2c_no_probes[] = CFG_I2C_NOPROBES; -#endif - -static void _i2c_bus1_reset (void) -{ - int i, status; - - /* Reset status register */ - /* write 1 in SCMP and IRQA to clear these fields */ - out8 (IIC_STS1, 0x0A); - - /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ - out8 (IIC_EXTSTS1, 0x8F); - __asm__ volatile ("eieio"); - - /* - * Get current state, reset bus - * only if no transfers are pending. - */ - i = 10; - do { - /* Get status */ - status = in8 (IIC_STS1); - udelay (500); /* 500us */ - i--; - } while ((status & IIC_STS_PT) && (i > 0)); - /* Soft reset controller */ - status = in8 (IIC_XTCNTLSS1); - out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST)); - __asm__ volatile ("eieio"); - - /* make sure where in initial state, data hi, clock hi */ - out8 (IIC_DIRECTCNTL1, 0xC); - for (i = 0; i < 10; i++) { - if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) { - /* clock until we get to known state */ - out8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */ - udelay (100); /* 100us */ - out8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */ - udelay (100); /* 100us */ - } else { - break; - } - } - /* send start condition */ - out8 (IIC_DIRECTCNTL1, 0x4); - udelay (1000); /* 1ms */ - /* send stop condition */ - out8 (IIC_DIRECTCNTL1, 0xC); - udelay (1000); /* 1ms */ - /* Unreset controller */ - out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST)); - udelay (1000); /* 1ms */ -} - -void i2c1_init (int speed, int slaveadd) -{ - sys_info_t sysInfo; - unsigned long freqOPB; - int val, divisor; - -#ifdef CFG_I2C_INIT_BOARD - /* call board specific i2c bus reset routine before accessing the */ - /* environment, which might be in a chip on that bus. For details */ - /* about this problem see doc/I2C_Edge_Conditions. */ - i2c_init_board(); -#endif - - /* Handle possible failed I2C state */ - /* FIXME: put this into i2c_init_board()? */ - _i2c_bus1_reset (); - - /* clear lo master address */ - out8 (IIC_LMADR1, 0); - - /* clear hi master address */ - out8 (IIC_HMADR1, 0); - - /* clear lo slave address */ - out8 (IIC_LSADR1, 0); - - /* clear hi slave address */ - out8 (IIC_HSADR1, 0); - - /* Clock divide Register */ - /* get OPB frequency */ - get_sys_info (&sysInfo); - freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv; - /* set divisor according to freqOPB */ - divisor = (freqOPB - 1) / 10000000; - if (divisor == 0) - divisor = 1; - out8 (IIC_CLKDIV1, divisor); - - /* no interrupts */ - out8 (IIC_INTRMSK1, 0); - - /* clear transfer count */ - out8 (IIC_XFRCNT1, 0); - - /* clear extended control & stat */ - /* write 1 in SRC SRS SWC SWS to clear these fields */ - out8 (IIC_XTCNTLSS1, 0xF0); - - /* Mode Control Register - Flush Slave/Master data buffer */ - out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); - __asm__ volatile ("eieio"); - - - val = in8(IIC_MDCNTL1); - __asm__ volatile ("eieio"); - - /* Ignore General Call, slave transfers are ignored, - disable interrupts, exit unknown bus state, enable hold - SCL - 100kHz normaly or FastMode for 400kHz and above - */ - - val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL; - if( speed >= 400000 ){ - val |= IIC_MDCNTL_FSM; - } - out8 (IIC_MDCNTL1, val); - - /* clear control reg */ - out8 (IIC_CNTL1, 0x00); - __asm__ volatile ("eieio"); - -} - -/* - This code tries to use the features of the 405GP i2c - controller. It will transfer up to 4 bytes in one pass - on the loop. It only does out8(lbz) to the buffer when it - is possible to do out16(lhz) transfers. - - cmd_type is 0 for write 1 for read. - - addr_len can take any value from 0-255, it is only limited - by the char, we could make it larger if needed. If it is - 0 we skip the address write cycle. - - Typical case is a Write of an addr followd by a Read. The - IBM FAQ does not cover this. On the last byte of the write - we don't set the creg CHT bit, and on the first bytes of the - read we set the RPST bit. - - It does not support address only transfers, there must be - a data part. If you want to write the address yourself, put - it in the data pointer. - - It does not support transfer to/from address 0. - - It does not check XFRCNT. -*/ -static -int i2c_transfer1(unsigned char cmd_type, - unsigned char chip, - unsigned char addr[], - unsigned char addr_len, - unsigned char data[], - unsigned short data_len ) -{ - unsigned char* ptr; - int reading; - int tran,cnt; - int result; - int status; - int i; - uchar creg; - - if( data == 0 || data_len == 0 ){ - /*Don't support data transfer of no length or to address 0*/ - printf( "i2c_transfer: bad call\n" ); - return IIC_NOK; - } - if( addr && addr_len ){ - ptr = addr; - cnt = addr_len; - reading = 0; - }else{ - ptr = data; - cnt = data_len; - reading = cmd_type; - } - - /*Clear Stop Complete Bit*/ - out8(IIC_STS1,IIC_STS_SCMP); - /* Check init */ - i=10; - do { - /* Get status */ - status = in8(IIC_STS1); - __asm__ volatile("eieio"); - i--; - } while ((status & IIC_STS_PT) && (i>0)); - - if (status & IIC_STS_PT) { - result = IIC_NOK_TOUT; - return(result); - } - /*flush the Master/Slave Databuffers*/ - out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB)); - /*need to wait 4 OPB clocks? code below should take that long*/ - - /* 7-bit adressing */ - out8(IIC_HMADR1,0); - out8(IIC_LMADR1, chip); - __asm__ volatile("eieio"); - - tran = 0; - result = IIC_OK; - creg = 0; - - while ( tran != cnt && (result == IIC_OK)) { - int bc,j; - - /* Control register = - Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start, - Transfer is a sequence of transfers - */ - creg |= IIC_CNTL_PT; - - bc = (cnt - tran) > 4 ? 4 : - cnt - tran; - creg |= (bc-1)<<4; - /* if the real cmd type is write continue trans*/ - if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) ) - creg |= IIC_CNTL_CHT; - - if (reading) - creg |= IIC_CNTL_READ; - else { - for(j=0; j0)); - - if (status & IIC_STS_ERR) { - result = IIC_NOK; - status = in8 (IIC_EXTSTS1); - /* Lost arbitration? */ - if (status & IIC_EXTSTS_LA) - result = IIC_NOK_LA; - /* Incomplete transfer? */ - if (status & IIC_EXTSTS_ICT) - result = IIC_NOK_ICT; - /* Transfer aborted? */ - if (status & IIC_EXTSTS_XFRA) - result = IIC_NOK_XFRA; - } else if ( status & IIC_STS_PT) { - result = IIC_NOK_TOUT; - } - /* Command is reading => get buffer */ - if ((reading) && (result == IIC_OK)) { - /* Are there data in buffer */ - if (status & IIC_STS_MDBS) { - /* - even if we have data we have to wait 4OPB clocks - for it to hit the front of the FIFO, after that - we can just read. We should check XFCNT here and - if the FIFO is full there is no need to wait. - */ - udelay (1); - for(j=0;jed (i.e. there was a chip at that address which - * drove the data line low). - */ - return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0); -} - - -int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - uchar xaddr[4]; - int ret; - - if ( alen > 4 ) { - printf ("I2C read: addr len %d not supported\n", alen); - return 1; - } - - if ( alen > 0 ) { - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - } - - -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if( alen > 0 ) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); -#endif - if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { - printf( "I2c read: failed %d\n", ret); - return 1; - } - return 0; -} - -int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - uchar xaddr[4]; - - if ( alen > 4 ) { - printf ("I2C write: addr len %d not supported\n", alen); - return 1; - - } - if ( alen > 0 ) { - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - } - -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if( alen > 0 ) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); -#endif - - return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); -} - -/*----------------------------------------------------------------------- - * Read a register - */ -uchar i2c_reg_read1(uchar i2c_addr, uchar reg) -{ - uchar buf; - - i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1); - - return(buf); -} - -/*----------------------------------------------------------------------- - * Write a register - */ -void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write1(i2c_addr, reg, 1, &val, 1); -} - - -int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int j; -#if defined(CFG_I2C_NOPROBES) - int k, skip; -#endif - - puts ("Valid chip addresses:"); - for(j = 0; j < 128; j++) { -#if defined(CFG_I2C_NOPROBES) - skip = 0; - for (k = 0; k < sizeof(i2c_no_probes); k++){ - if (j == i2c_no_probes[k]){ - skip = 1; - break; - } - } - if (skip) - continue; -#endif - if(i2c_probe1(j) == 0) { - printf(" %02X", j); - } - } - putc ('\n'); - -#if defined(CFG_I2C_NOPROBES) - puts ("Excluded chip addresses:"); - for( k = 0; k < sizeof(i2c_no_probes); k++ ) - printf(" %02X", i2c_no_probes[k] ); - putc ('\n'); -#endif - - return 0; -} - -U_BOOT_CMD( - iprobe1, 1, 1, do_i2c1_probe, - "iprobe1 - probe to discover valid I2C chip addresses\n", - "\n -discover valid I2C chip addresses\n" -); - -#endif /* CONFIG_I2C_BUS1 */ diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h deleted file mode 100644 index cd4fc86..0000000 --- a/board/sandburst/common/ppc440gx_i2c.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Ported from i2c driver for ppc4xx by AS HARNOIS by - * Travis B. Sawyer - * Sandburst Corporation - */ -#include -#include -#if defined(CONFIG_440) -# include <440_i2c.h> -#else -# include <405gp_i2c.h> -#endif -#include - -#ifdef CONFIG_HARD_I2C - -#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500) -#define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR -#define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF) -#define IIC_SDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF) -#define IIC_LMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLMADR) -#define IIC_HMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHMADR) -#define IIC_CNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCNTL) -#define IIC_MDCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDCNTL) -#define IIC_STS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSTS) -#define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS) -#define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR) -#define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR) -#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV) -#define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK) -#define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT) -#define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS) -#define IIC_DIRECTCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICDIRECTCNTL) - -void i2c1_init (int speed, int slaveadd); -int i2c_probe1 (uchar chip); -int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len); -int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len); -uchar i2c_reg_read1(uchar i2c_addr, uchar reg); -void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val); - -#endif /* CONFIG_HARD_I2C */ diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c deleted file mode 100644 index 3530416..0000000 --- a/board/sandburst/common/sb_common.c +++ /dev/null @@ -1,451 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include "ppc440gx_i2c.h" -#include "sb_common.h" - -long int fixed_sdram (void); - -/************************************************************************* - * metrobox_get_master - * - * PRI_N - active low signal. If the GPIO pin is low we are the master - * - ************************************************************************/ -int sbcommon_get_master(void) -{ - ppc440_gpio_regs_t *gpio_regs; - - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; - - if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) { - return 0; - } - else { - return 1; - } -} - -/************************************************************************* - * metrobox_secondary_present - * - * Figure out if secondary/slave board is present - * - ************************************************************************/ -int sbcommon_secondary_present(void) -{ - ppc440_gpio_regs_t *gpio_regs; - - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; - - if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES) - return 0; - else - return 1; -} - -/************************************************************************* - * sbcommon_get_serial_number - * - * Retrieve the board serial number via the mac address in eeprom - * - ************************************************************************/ -unsigned short sbcommon_get_serial_number(void) -{ - unsigned char buff[0x100]; - unsigned short sernum; - - /* Get the board serial number from eeprom */ - /* Initialize I2C */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x50, 0, 1, buff, 0x100); - - memcpy(&sernum, &buff[0xF4], 2); - sernum /= 32; - - return (sernum); -} - -/************************************************************************* - * sbcommon_fans - * - * Spin up fans 2 & 3 to get some air moving. OS will take care - * of the rest. This is mostly a precaution... - * - * Assumes i2c bus 1 is ready. - * - ************************************************************************/ -void sbcommon_fans(void) -{ - /* - * Attempt to turn on 2 of the fans... - * Need to go through the bridge - */ - puts ("FANS: "); - - /* select fan4 through the bridge */ - i2c_reg_write1(0x73, /* addr */ - 0x00, /* reg */ - 0x08); /* val = bus 4 */ - - /* Turn on FAN 4 */ - i2c_reg_write1(0x2e, - 1, - 0x80); - - i2c_reg_write1(0x2e, - 0, - 0x19); - - /* Deselect bus 4 on the bridge */ - i2c_reg_write1(0x73, - 0x00, - 0x00); - - /* select fan3 through the bridge */ - i2c_reg_write1(0x73, /* addr */ - 0x00, /* reg */ - 0x04); /* val = bus 3 */ - - /* Turn on FAN 3 */ - i2c_reg_write1(0x2e, - 1, - 0x80); - - i2c_reg_write1(0x2e, - 0, - 0x19); - - /* Deselect bus 3 on the bridge */ - i2c_reg_write1(0x73, - 0x00, - 0x00); - - /* select fan2 through the bridge */ - i2c_reg_write1(0x73, /* addr */ - 0x00, /* reg */ - 0x02); /* val = bus 4 */ - - /* Turn on FAN 2 */ - i2c_reg_write1(0x2e, - 1, - 0x80); - - i2c_reg_write1(0x2e, - 0, - 0x19); - - /* Deselect bus 2 on the bridge */ - i2c_reg_write1(0x73, - 0x00, - 0x00); - - /* select fan1 through the bridge */ - i2c_reg_write1(0x73, /* addr */ - 0x00, /* reg */ - 0x01); /* val = bus 0 */ - - /* Turn on FAN 1 */ - i2c_reg_write1(0x2e, - 1, - 0x80); - - i2c_reg_write1(0x2e, - 0, - 0x19); - - /* Deselect bus 1 on the bridge */ - i2c_reg_write1(0x73, - 0x00, - 0x00); - - puts ("on\n"); - - return; - -} - -/************************************************************************* - * initdram - * - * Initialize sdram - * - ************************************************************************/ -long int initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (0); -#else - dram_size = fixed_sdram (); -#endif - return dram_size; -} - - -/************************************************************************* - * testdram - * - * - ************************************************************************/ -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("Testing SDRAM: "); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("OK\n"); - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay (400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram (mem_mcsts, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) -int pci_pre_init(struct pci_controller * hose ) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The metrobox is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - DECLARE_GLOBAL_DATA_PTR; - - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIX0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); - - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - - -/************************************************************************* - * is_pci_host - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - /* The metrobox is always configured as host. */ - return(1); -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * board_get_enetaddr - * - * Get the ethernet MAC address for the management ethernet from the - * strap EEPROM. Note that is the BASE address for the range of - * external ethernet MACs on the board. The base + 31 is the actual - * mgmt mac address. - * - ************************************************************************/ -static int macaddr_idx = 0; - -void board_get_enetaddr (uchar * enet) -{ - int i; - unsigned short tmp; - unsigned char buff[0x100], *cp; - - if (0 == macaddr_idx) { - - /* Initialize I2C */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x50, 0, 1, buff, 0x100); - - cp = &buff[0xF0]; - - for (i = 0; i < 6; i++,cp++) - enet[i] = *cp; - - memcpy(&tmp, &enet[4], 2); - tmp += 31; - memcpy(&enet[4], &tmp, 2); - - macaddr_idx++; - } else { - enet[0] = 0x02; - enet[1] = 0x00; - enet[2] = 0x00; - enet[3] = 0x00; - enet[4] = 0x00; - if (1 == sbcommon_get_master() ) { - /* Master/Primary card */ - enet[5] = 0x01; - } else { - /* Slave/Secondary card */ - enet [5] = 0x02; - } - } - - return; -} - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - - return (ctrlc()); -} -#endif diff --git a/board/sandburst/common/sb_common.h b/board/sandburst/common/sb_common.h deleted file mode 100644 index 888e4f0..0000000 --- a/board/sandburst/common/sb_common.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef __SBCOMMON_H__ -#define __SBCOMMON_H__ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include "ppc440gx_i2c.h" - -/* - * GPIO Settings - */ -/* Chassis settings */ -#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */ -#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */ - -/* Debug LEDs */ -#define SBCOMMON_GPIO_DBGLED_0 0x00000400 -#define SBCOMMON_GPIO_DBGLED_1 0x00000200 -#define SBCOMMON_GPIO_DBGLED_2 0x00100000 -#define SBCOMMON_GPIO_DBGLED_3 0x00000100 - -#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \ - SBCOMMON_GPIO_DBGLED_1 | \ - SBCOMMON_GPIO_DBGLED_2 | \ - SBCOMMON_GPIO_DBGLED_3) - -#define SBCOMMON_GPIO_SYS_FAULT 0x00000080 -#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040 -#define SBCOMMON_GPIO_SYS_STATUS 0x00000020 - -#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS) - -#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \ - SBCOMMON_GPIO_DBGLED_1 | \ - SBCOMMON_GPIO_DBGLED_2 | \ - SBCOMMON_GPIO_DBGLED_3 | \ - SBCOMMON_GPIO_SYS_STATUS) - -typedef struct ppc440_gpio_regs { - volatile unsigned long out; - volatile unsigned long tri_state; - volatile unsigned long dummy[4]; - volatile unsigned long open_drain; - volatile unsigned long in; -} __attribute__((packed)) ppc440_gpio_regs_t; - -int sbcommon_get_master(void); -int sbcommon_secondary_present(void); -unsigned short sbcommon_get_serial_number(void); -void sbcommon_fans(void); - -#endif /* __SBCOMMON_H__ */ diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile deleted file mode 100644 index 8b3173c..0000000 --- a/board/sandburst/karef/Makefile +++ /dev/null @@ -1,59 +0,0 @@ -# -# (C) Copyright 2005 -# Sandburst Corporation -# Travis B. Sawyer -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -# TBS: add for debugging purposes -BUILDUSER := $(shell whoami) -FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o) - -CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' -# TBS: end debugging - - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ - ../common/sb_common.o - -SOBJS = init.o - - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend *~ - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk deleted file mode 100644 index 65c1e48..0000000 --- a/board/sandburst/karef/config.mk +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2005 -# Sandburst Corporation -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Sandburst Corporation Metrobox Reference Design -# Travis B. Sawyer -# - -ifeq ($(ramsym),1) -TEXT_BASE = 0x07FD0000 -else -TEXT_BASE = 0xFFF80000 -endif - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 -endif diff --git a/board/sandburst/karef/hal_ka_of_auto.h b/board/sandburst/karef/hal_ka_of_auto.h deleted file mode 100644 index cc501c9..0000000 --- a/board/sandburst/karef/hal_ka_of_auto.h +++ /dev/null @@ -1,324 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip ka_of - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_KA_OF_AUTO_H -#define HAL_KA_OF_AUTO_H - - -/* ---------------------------------------------------------------- - * For block: 'ofem' - */ - -/* ---- Block instance addressing (for block-select) */ -#define OFEM_BLOCK_ADDR_BIT_L 6 -#define OFEM_BLOCK_ADDR_BIT_H 9 -#define OFEM_BLOCK_ADDR_WIDTH 4 - -#define OFEM_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define OFEM_REG_ADDR_BIT_L 2 -#define OFEM_REG_ADDR_BIT_H 5 -#define OFEM_REG_ADDR_WIDTH 4 - - -/* ================================================================ - * ---- Register KA_OF_OFEM_REVISION */ -#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31 -#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_RESET */ -#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004 -#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31 -#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_CNTL */ -#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018 -#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31 -#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */ -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c -#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_INTERRUPT */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008 -#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_INTERRUPT_MASK */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c -#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_SCRATCH */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010 -#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_SCRATCH_MASK */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014 -#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register KA_OF_OFEM_REVISION */ -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_RESET */ -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_CNTL */ -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */ -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_INTERRUPT */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_INTERRUPT_MASK */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register KA_OF_OFEM_SCRATCH */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_SCRATCH_MASK */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_KA_OF_AUTO_H */ diff --git a/board/sandburst/karef/hal_ka_sc_auto.h b/board/sandburst/karef/hal_ka_sc_auto.h deleted file mode 100644 index db1cec2..0000000 --- a/board/sandburst/karef/hal_ka_sc_auto.h +++ /dev/null @@ -1,836 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip ka_sc - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_KA_SC_AUTO_H -#define HAL_KA_SC_AUTO_H - - -/* ---------------------------------------------------------------- - * For block: 'scan' - */ - -/* ---- Block instance addressing (for block-select) */ -#define SCAN_BLOCK_ADDR_BIT_L 7 -#define SCAN_BLOCK_ADDR_BIT_H 9 -#define SCAN_BLOCK_ADDR_WIDTH 3 - -#define SCAN_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define SCAN_REG_ADDR_BIT_L 2 -#define SCAN_REG_ADDR_BIT_H 6 -#define SCAN_REG_ADDR_WIDTH 5 - - -/* ================================================================ - * ---- Register KA_SC_SCAN_REVISION */ -#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31 -#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_RESET */ -#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004 -#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31 -#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_STATUS */ -#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008 -#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31 -#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_CNTL */ -#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c -#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_INFO */ -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_FROM_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_FROM_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_TO_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_TO_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_CTRL */ -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_PLL_CTRL */ -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038 -#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c -#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_DR_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040 -#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044 -#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_IN */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_MISC */ -#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054 -#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31 -#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_INTERRUPT */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c -#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_INTERRUPT_MASK */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010 -#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCRATCH */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014 -#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCRATCH_MASK */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018 -#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register KA_SC_SCAN_REVISION */ -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_RESET */ -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_STATUS */ -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_CNTL */ -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_INFO */ -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_FROM_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_FROM_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_TO_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_TO_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_CTRL */ -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_PLL_CTRL */ -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_DR_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_IN */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_MISC */ -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_INTERRUPT */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_INTERRUPT_MASK */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCRATCH */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCRATCH_MASK */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_KA_SC_AUTO_H */ diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S deleted file mode 100644 index b1d47a4..0000000 --- a/board/sandburst/karef/init.S +++ /dev/null @@ -1,101 +0,0 @@ -/* -* Copyright (C) 2005 Sandburst Corporation -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ -/* - * Ported from Ebony init.S by Travis B. Sawyer - */ - -#include -#include - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) - tlbtab_end diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c deleted file mode 100644 index 2d71d3b..0000000 --- a/board/sandburst/karef/karef.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * Travis B. Sawyer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "karef.h" -#include "karef_version.h" -#include -#include -#include -#include -#include "../common/sb_common.h" -#include "../common/ppc440gx_i2c.h" - -void fpga_init (void); - -KAREF_BOARD_ID_ST board_id_as[] = -{ - {"Undefined"}, /* Not specified */ - {"Kamino Reference Design"}, - {"Reserved"}, /* Reserved for future use */ - {"Reserved"}, /* Reserved for future use */ -}; - -KAREF_BOARD_ID_ST ofem_board_id_as[] = -{ - {"Undefined"}, - {"1x10 + 10x2"}, - {"Reserved"}, - {"Reserved"}, -}; - -/************************************************************************* - * board_early_init_f - * - * Setup chip selects, initialize the Opto-FPGA, initialize - * interrupt polarity and triggers. - ************************************************************************/ -int board_early_init_f (void) -{ - ppc440_gpio_regs_t *gpio_regs; - - /* Enable GPIO interrupts */ - mtsdr(sdr_pfc0, 0x00103E00); - - /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; - gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; - gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; - - /* Turn on all the leds for now */ - gpio_regs->out = SBCOMMON_GPIO_LEDS; - - /*--------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------*/ - mtebc(xbcfg, - EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | - EBC_CFG_PR_32); - - /*--------------------------------------------------------------------+ - | 1/2 MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb0ap, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - /*--------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb1ap, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(pb2ap, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | KaRef Scan FPGA. Initialize bank 3 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb5ap, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | MAC A & B for Kamino. OFEM FPGA decodes the addresses - | Initialize bank 4 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb4ap, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | - EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | OFEM FPGA Initialize bank 5 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb3ap, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - - mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(pb6ap, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | BME-32. Initialize bank 7 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb7ap, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - * Setup the interrupt controller polarities, triggers, etc. - +-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non- critical */ - mtdcr (uic0pr, 0xfffffe03); /* polarity */ - mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffc8ff); /* polarity */ - mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffff83ff); /* polarity */ - mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); - mtdcr (uicb0tr, 0x00000000); - mtdcr (uicb0vr, 0x00000001); - - fpga_init(); - - return 0; -} - - -/************************************************************************* - * checkboard - * - * Dump pertinent info to the console - ************************************************************************/ -int checkboard (void) -{ - sys_info_t sysinfo; - unsigned char brd_rev, brd_id; - unsigned short sernum; - unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0; - unsigned char ofem_brd_rev, ofem_brd_id; - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; - - scan_id = (unsigned char)((karef_ps->revision_ul & - SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT); - - scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK) - >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT); - - brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT); - - brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT); - - ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); - - ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT); - - if (0xF != ofem_brd_id) { - ofem_id = (unsigned char)((ofem_ps->revision_ul & - SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT); - - ofem_rev = (unsigned char)((ofem_ps->revision_ul & - SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK) - >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT); - } - - get_sys_info (&sysinfo); - - sernum = sbcommon_get_serial_number(); - - printf ("Board: Sandburst Corporation Kamino Reference Design " - "Serial Number: %d\n", sernum); - printf ("%s\n", KAREF_U_BOOT_REL_STR); - - printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER); - if (sbcommon_get_master()) { - printf("Slot 0 - Master\nSlave board"); - if (sbcommon_secondary_present()) - printf(" present\n"); - else - printf(" not detected\n"); - } else { - printf("Slot 1 - Slave\n\n"); - } - - printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev); - printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id); - if(0xF != ofem_brd_id) { - printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev); - printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev); - } - - /* Fix the ack in the bme 32 */ - udelay(5000); - out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); - asm("eieio"); - - - return (0); -} - -/************************************************************************* - * misc_init_f - * - * Initialize I2C bus one to gain access to the fans - ************************************************************************/ -int misc_init_f (void) -{ - /* Turn on i2c bus 1 */ - puts ("I2C1: "); - i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - puts ("ready\n"); - - /* Turn on fans 3 & 4 */ - sbcommon_fans(); - - return (0); -} - -/************************************************************************* - * misc_init_r - * - * Do nothing. - ************************************************************************/ -int misc_init_r (void) -{ - unsigned short sernum; - char envstr[255]; - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - - if(NULL != getenv("secondserial")) { - puts("secondserial is set, switching to second serial port\n"); - setenv("stderr", "serial1"); - setenv("stdout", "serial1"); - setenv("stdin", "serial1"); - } - - setenv("ubrelver", KAREF_U_BOOT_REL_STR); - - memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER); - setenv("bldstr", envstr); - saveenv(); - - if( getenv("autorecover")) { - setenv("autorecover", NULL); - saveenv(); - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for automatic filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type allow the system to continue to boot\n"); - } - - if( getenv("fakeled")) { - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; - ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK; - karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK; - setenv("bootdelay", "-1"); - saveenv(); - printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); - } - - return (0); -} - -/************************************************************************* - * ide_set_reset - ************************************************************************/ -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - KAREF_FPGA_REGS_ST *karef_ps; - /* TODO: ide reset */ - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; - - if (on) { - karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; - } else { - karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; - } -} -#endif /* CONFIG_IDE_RESET */ - -/************************************************************************* - * fpga_init - ************************************************************************/ -void fpga_init(void) -{ - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - unsigned char ofem_id; - unsigned long tmp; - - /* Ensure we have power all around */ - udelay(500); - - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; - tmp = - SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK; - - karef_ps->reset_ul = tmp; - - /* - * Wait a bit to allow the ofem fpga to get its brains - */ - udelay(5000); - - /* - * Check to see if the ofem is there - */ - ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); - if(0xF != ofem_id) { - tmp = - SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK | - SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK | - SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK; - - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; - ofem_ps->reset_ul = tmp; - - ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT; - } - - karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT; - - asm("eieio"); - - return; -} - -int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - memset(envstr, 0, 255); - /* - * Setup our ip address - */ - sprintf(envstr, "10.100.70.%d", sernum); - - setenv("ipaddr", envstr); - /* - * Setup the host ip address - */ - setenv("serverip", "10.100.17.10"); - - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " - "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d " - "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:" - "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33", - sernum, sernum, sernum); - - setenv("bootargs_nfs", envstr); - setenv("bootargs", envstr); - - /* - * Setup CF bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", - sernum, sernum); - - setenv("bootargs_cf", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000"); - setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000"); - - /* - * Setup compact flash boot command - */ - setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000"); - - saveenv(); - - return(1); -} - -int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - - setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type boot.\nWhen the kernel has booted" - " please type fsrecover.sh\n"); - - return(1); -} - -U_BOOT_CMD(kasetup, 1, 1, karefSetupVars, - "kasetup - Set environment to factory defaults\n", NULL); - -U_BOOT_CMD(karecover, 1, 1, karefRecover, - "karecover - Set environment to allow for fs recovery\n", NULL); diff --git a/board/sandburst/karef/karef.h b/board/sandburst/karef/karef.h deleted file mode 100644 index 5de7cb5..0000000 --- a/board/sandburst/karef/karef.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef __KAREF_H__ -#define __KAREF_H__ -/* - * (C) Copyright 2005 - * Sandburst Corporation - * Travis B. Sawyer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Ka Reference Design OFEM FPGA Registers & definitions */ -#include "hal_ka_sc_auto.h" -#include "hal_ka_of_auto.h" - -typedef struct karef_board_id_s { - const char name[40]; -} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST; - -/* SCAN FPGA */ -typedef struct karef_fpga_regs_s -{ - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long status_ul; /* Read Only */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long boardinfo_ul; /* Read Only */ - volatile unsigned long scan_from0_ul; /* Read Only */ - volatile unsigned long scan_from1_ul; /* Read Only */ - volatile unsigned long scan_to0_ul; /* Read/Write */ - volatile unsigned long scan_to1_ul; /* Read/Write */ - volatile unsigned long scan_control_ul; /* Read/Write */ - volatile unsigned long pll_control_ul; /* Read/Write */ - volatile unsigned long core_clock_cnt_ul; /* Read/Write */ - volatile unsigned long dr_clock_cnt_ul; /* Read/Write */ - volatile unsigned long spi_clock_cnt_ul; /* Read/Write */ - volatile unsigned long brdout_data_ul; /* Read/Write */ - volatile unsigned long brdout_enable_ul; /* Read/Write */ - volatile unsigned long brdin_data_ul; /* Read Only */ - volatile unsigned long misc_ul; /* Read/Write */ -} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST; - -/* OFEM FPGA */ -typedef struct ofem_fpga_regs_s -{ - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */ -} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST; - - -#endif /* __KAREF_H__ */ diff --git a/board/sandburst/karef/karef_version.h b/board/sandburst/karef/karef_version.h deleted file mode 100644 index 9960b9a..0000000 --- a/board/sandburst/karef/karef_version.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _KAREF_VERSION_H_ -#define _KAREF_VERSION_H_ -/* - * Copyright (C) 2005 Sandburst Corporation - * Travis B. Sawyer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#define KAREF_U_BOOT_REL_STR "Release 0.0.7" -#endif diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds deleted file mode 100644 index 9e9e990..0000000 --- a/board/sandburst/karef/u-boot.lds +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/sandburst/karef/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug deleted file mode 100644 index 47d80fa..0000000 --- a/board/sandburst/karef/u-boot.lds.debug +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/sandburst/karef/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* common/environment.o(.text) */ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile deleted file mode 100644 index 06a9a22..0000000 --- a/board/sandburst/metrobox/Makefile +++ /dev/null @@ -1,57 +0,0 @@ -# -# (C) Copyright 2005 -# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -# TBS: add for debugging purposes -BUILDUSER := $(shell whoami) -FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o) - -CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' -# TBS: end debugging - - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ - ../common/sb_common.o -SOBJS = init.o - - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend *~ - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk deleted file mode 100644 index 91aee2f..0000000 --- a/board/sandburst/metrobox/config.mk +++ /dev/null @@ -1,38 +0,0 @@ -# -# (C) Copyright 2005 -# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -ifeq ($(ramsym),1) -TEXT_BASE = 0x07FD0000 -else -TEXT_BASE = 0xFFF80000 -endif - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 -endif diff --git a/board/sandburst/metrobox/hal_xc_auto.h b/board/sandburst/metrobox/hal_xc_auto.h deleted file mode 100644 index c99b38c..0000000 --- a/board/sandburst/metrobox/hal_xc_auto.h +++ /dev/null @@ -1,553 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip xc - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_XC_AUTO_H -#define HAL_XC_AUTO_H - -/* ---------------------------------------------------------------- - * For block: 'xcvr_cntl' - */ - -/* ---- Block instance addressing (for block-select) */ -#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6 -#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9 -#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4 - -#define XCVR_CNTL_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define XCVR_CNTL_REG_ADDR_BIT_L 2 -#define XCVR_CNTL_REG_ADDR_BIT_H 5 -#define XCVR_CNTL_REG_ADDR_WIDTH 4 - - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_REVISION */ -#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_RESET */ -#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004 -#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_STATUS */ -#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008 -#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_CNTL */ -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c -#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_BRD_INFO */ -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020 -#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */ -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024 -#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_INTERRUPT */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c -#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010 -#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_SCRATCH */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014 -#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018 -#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_REVISION */ -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_RESET */ -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_STATUS */ -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_CNTL */ -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_BRD_INFO */ -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */ -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_INTERRUPT */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_SCRATCH */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_XC_AUTO_H */ diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S deleted file mode 100644 index e398f00..0000000 --- a/board/sandburst/metrobox/init.S +++ /dev/null @@ -1,99 +0,0 @@ -/* -* Copyright (C) 2005 -* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) - tlbtab_end diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c deleted file mode 100644 index 86d259f..0000000 --- a/board/sandburst/metrobox/metrobox.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - * Copyright (c) 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include "metrobox.h" -#include "metrobox_version.h" -#include -#include -#include -#include -#include "../common/ppc440gx_i2c.h" -#include "../common/sb_common.h" - -void fpga_init (void); - -METROBOX_BOARD_ID_ST board_id_as[] = -{ {"Undefined"}, /* Not specified */ - {"2x10Gb"}, /* 2 ports, 10 GbE */ - {"20x1Gb"}, /* 20 ports, 1 GbE */ - {"Reserved"}, /* Reserved for future use */ -}; - -/************************************************************************* - * board_early_init_f - * - * Setup chip selects, initialize the Opto-FPGA, initialize - * interrupt polarity and triggers. - ************************************************************************/ -int board_early_init_f (void) -{ - ppc440_gpio_regs_t *gpio_regs; - - /* Enable GPIO interrupts */ - mtsdr(sdr_pfc0, 0x00103E00); - - /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; - gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; - gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; - - /* Turn on all the leds for now */ - gpio_regs->out = SBCOMMON_GPIO_LEDS; - - /*--------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------*/ - mtebc(xbcfg, - EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | - EBC_CFG_PR_32); - - /*--------------------------------------------------------------------+ - | 1/2 MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb0ap, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - /*--------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb1ap, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(pb2ap, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | OPTO & OFEM FPGA. Initialize bank 3 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb3ap, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | MAC A for metrobox - | MAC A & B for Kamino. OFEM FPGA decodes the addresses - | Initialize bank 4 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb4ap, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | Metrobox MAC B Initialize bank 5 with default values. - | KA REF FPGA Initialize bank 5 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb5ap, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(pb6ap, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | BME-32. Initialize bank 7 with default values. - +-------------------------------------------------------------------*/ - mtebc(pb7ap, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - * Setup the interrupt controller polarities, triggers, etc. - +-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non- critical */ - mtdcr (uic0pr, 0xfffffe03); /* polarity */ - mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffc8ff); /* polarity */ - mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffff83ff); /* polarity */ - mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); - mtdcr (uicb0tr, 0x00000000); - mtdcr (uicb0vr, 0x00000001); - - fpga_init(); - - return 0; -} - -/************************************************************************* - * checkboard - * - * Dump pertinent info to the console - ************************************************************************/ -int checkboard (void) -{ - sys_info_t sysinfo; - unsigned char brd_rev, brd_id; - unsigned short sernum; - unsigned char opto_rev, opto_id; - OPTO_FPGA_REGS_ST *opto_ps; - - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; - - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - - opto_id = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT); - - brd_rev = (unsigned char)((opto_ps->boardinfo_ul & - SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK) - >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT); - - brd_id = (unsigned char)((opto_ps->boardinfo_ul & - SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK) - >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT); - - get_sys_info (&sysinfo); - - sernum = sbcommon_get_serial_number(); - printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum); - printf ("%s\n", METROBOX_U_BOOT_REL_STR); - - printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER); - if (sbcommon_get_master()) { - printf("Slot 0 - Master\nSlave board"); - if (sbcommon_secondary_present()) - printf(" present\n"); - else - printf(" not detected\n"); - } else { - printf("Slot 1 - Slave\n\n"); - } - - printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev); - printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]); - - /* Fix the ack in the bme 32 */ - udelay(5000); - out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); - asm("eieio"); - - - return (0); -} - -/************************************************************************* - * misc_init_f - * - * Initialize I2C bus one to gain access to the fans - ************************************************************************/ -int misc_init_f (void) -{ - /* Turn on i2c bus 1 */ - puts ("I2C1: "); - i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - puts ("ready\n"); - - /* Turn on fans */ - sbcommon_fans(); - - return (0); -} - -/************************************************************************* - * misc_init_r - * - * Do nothing. - ************************************************************************/ -int misc_init_r (void) -{ - unsigned short sernum; - char envstr[255]; - unsigned char opto_rev; - OPTO_FPGA_REGS_ST *opto_ps; - - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; - - if(NULL != getenv("secondserial")) { - puts("secondserial is set, switching to second serial port\n"); - setenv("stderr", "serial1"); - setenv("stdout", "serial1"); - setenv("stdin", "serial1"); - } - - setenv("ubrelver", METROBOX_U_BOOT_REL_STR); - - memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER); - setenv("bldstr", envstr); - saveenv(); - - if( getenv("autorecover")) { - setenv("autorecover", NULL); - saveenv(); - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for automatic filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type allow the system to continue to boot\n"); - } - - if( getenv("fakeled")) { - setenv("bootdelay", "-1"); - saveenv(); - printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - - if(0x12 <= opto_rev) { - opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK; - } - } - - return (0); -} - -/************************************************************************* - * ide_set_reset - ************************************************************************/ -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - OPTO_FPGA_REGS_ST *opto_ps; - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; - - if (on) { /* assert RESET */ - opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; - } else { /* release RESET */ - opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; - } -} -#endif /* CONFIG_IDE_RESET */ - -/************************************************************************* - * fpga_init - ************************************************************************/ -void fpga_init(void) -{ - OPTO_FPGA_REGS_ST *opto_ps; - unsigned char opto_rev; - unsigned long tmp; - - /* Ensure we have power all around */ - udelay(500); - - /* - * Take appropriate hw bits out of reset - */ - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; - - tmp = - SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK; - opto_ps->reset_ul = tmp; - /* - * Turn on the 'Slow Blink' for the System Error Led. - * Ensure FPGA rev is up to at least rev 0x12 - */ - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - if(0x12 <= opto_rev) { - opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT; - } - - asm("eieio"); - - return; -} - -int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - memset(envstr, 0, 255); - /* - * Setup our ip address - */ - sprintf(envstr, "10.100.60.%d", sernum); - - setenv("ipaddr", envstr); - /* - * Setup the host ip address - */ - setenv("serverip", "10.100.17.10"); - - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " - "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d " - "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1" - ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33", - sernum, sernum, sernum); - - setenv("bootargs_nfs", envstr); - setenv("bootargs", envstr); - - /* - * Setup CF bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", - sernum, sernum); - - setenv("bootargs_cf", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000"); - setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000"); - - /* - * Setup compact flash boot command - */ - setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000"); - - saveenv(); - - - return(1); -} - -int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none", - sernum, sernum); - - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type boot.\nWhen the kernel has booted" - " please type fsrecover.sh\n"); - - return(1); -} - -U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars, - "mbsetup - Set environment to factory defaults\n", NULL); - -U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover, - "mbrecover - Set environment to allow for fs recovery\n", NULL); diff --git a/board/sandburst/metrobox/metrobox.h b/board/sandburst/metrobox/metrobox.h deleted file mode 100644 index 3f28f00..0000000 --- a/board/sandburst/metrobox/metrobox.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef __METROBOX_H__ -#define __METROBOX_H__ -/* - * (C) Copyright 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -typedef struct metrobox_board_id_s { - const char name[40]; -} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST; - - -/* Metrobox Opto-FPGA registers and definitions */ -#include "hal_xc_auto.h" -typedef struct opto_fpga_regs_s { - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long status_ul; /* Read Only */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long boardinfo_ul; /* Read Only */ -} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST; - -#endif /* __METROBOX_H__ */ diff --git a/board/sandburst/metrobox/metrobox_version.h b/board/sandburst/metrobox/metrobox_version.h deleted file mode 100644 index 1b6fee5..0000000 --- a/board/sandburst/metrobox/metrobox_version.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _METROBOX_VERSION_H_ -#define _METROBOX_VERSION_H_ -/* - * (C) Copyright 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#define METROBOX_U_BOOT_REL_STR "Release 2.0.3" - -#endif diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds deleted file mode 100644 index a17401a..0000000 --- a/board/sandburst/metrobox/u-boot.lds +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/sandburst/metrobox/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug deleted file mode 100644 index fef4c42..0000000 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/sandburst/metrobox/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* common/environment.o(.text) */ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sandpoint/Makefile b/board/sandpoint/Makefile deleted file mode 100644 index d6bbf2f..0000000 --- a/board/sandpoint/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/sandpoint/README b/board/sandpoint/README deleted file mode 100644 index 9e48168..0000000 --- a/board/sandpoint/README +++ /dev/null @@ -1,15 +0,0 @@ -This port of U-Boot will run on a Motorola Sandpoint 3 development -system equipped with a Unity X4 PPMC card (MPC8240 CPU) only. It is a -snapshot of work in progress and far from being completed. In order -to run it on the target system, it has to be downloaded using the -DINK32 monitor program that came with your Sandpoint system. Please -note that DINK32 does not accept the S-Record file created by the -U-Boot build process unmodified, because it contains CR/LF line -terminators. You have to strip the CR characters first. There is a -tiny script named 'dinkdl' I created for this purpose. - -The Sandpoint port is based on the work of Rob Taylor, who does not -seem to maintain it any more. I can be reached by mail as -tkoeller@gmx.net. - -Thomas Koeller diff --git a/board/sandpoint/config.mk b/board/sandpoint/config.mk deleted file mode 100644 index b3f65eb..0000000 --- a/board/sandpoint/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Sandpoint boards -# - -#TEXT_BASE = 0x00090000 -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/sandpoint/dinkdl b/board/sandpoint/dinkdl deleted file mode 100644 index f281452..0000000 --- a/board/sandpoint/dinkdl +++ /dev/null @@ -1,2 +0,0 @@ -#! /bin/bash -tr -d "\r" <$1 >/dev/tts/1 diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S deleted file mode 100644 index 07dafb7..0000000 --- a/board/sandpoint/early_init.S +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2001 - * Thomas Koeller, tkoeller@gmx.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASSEMBLY__ -#define __ASSEMBLY__ 1 -#endif - -#include -#include -#include -#include - -#if defined(USE_DINK32) - /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ - #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) -#else - #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) -#endif - - .text - - /* Values to program into memory controller registers */ -tbl: .long MCCR1, MCCR1VAL - .long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT - .long MCCR3 - .long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ - (CFG_REFREC << MCCR3_REFREC_SHIFT) | \ - (CFG_RDLAT << MCCR3_RDLAT_SHIFT) - .long MCCR4 - .long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ - (CFG_REGISTERD_TYPE_BUFFER << 20) | \ - (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ - ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \ - (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ - (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ - ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) - .long MSAR1 - .long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR1 - .long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MSAR2 - .long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR2 - .long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR1 - .long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR1 - .long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR2 - .long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR2 - .long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long 0 - - - /* - * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This - * must be done in assembly, since we have no stack at this point. - */ - .global early_init_f -early_init_f: - mflr r10 - - /* basic memory controller configuration */ - lis r3, CONFIG_ADDR_HIGH - lis r4, CONFIG_DATA_HIGH - bl lab -lab: mflr r5 - lwzu r0, tbl - lab(r5) -loop: lwz r1, 4(r5) - stwbrx r0, 0, r3 - eieio - stwbrx r1, 0, r4 - eieio - lwzu r0, 8(r5) - cmpli cr0, 0, r0, 0 - bne cr0, loop - - /* set bank enable bits */ - lis r0, MBER@h - ori r0, 0, MBER@l - li r1, CFG_BANK_ENABLE - stwbrx r0, 0, r3 - eieio - stb r1, 0(r4) - eieio - - /* delay loop */ - lis r0, 0x0003 - mtctr r0 -delay: bdnz delay - - /* enable memory controller */ - lis r0, MCCR1@h - ori r0, 0, MCCR1@l - stwbrx r0, 0, r3 - eieio - lwbrx r0, 0, r4 - oris r0, 0, MCCR1_MEMGO@h - stwbrx r0, 0, r4 - eieio - - /* set up stack pointer */ - lis r1, CFG_INIT_SP_OFFSET@h - ori r1, r1, CFG_INIT_SP_OFFSET@l - - mtlr r10 - blr diff --git a/board/sandpoint/flash.c b/board/sandpoint/flash.c deleted file mode 100644 index a9f73ff..0000000 --- a/board/sandpoint/flash.c +++ /dev/null @@ -1,764 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); -#if 0 -static void flash_get_offsets (ulong base, flash_info_t *info); -#endif /* 0 */ - -/*flash command address offsets*/ - -#if 0 -#define ADDR0 (0x555) -#define ADDR1 (0x2AA) -#define ADDR3 (0x001) -#else -#define ADDR0 (0xAAA) -#define ADDR1 (0x555) -#define ADDR3 (0x001) -#endif - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -#if 0 -static int byte_parity_odd(unsigned char x) __attribute__ ((const)); -#endif /* 0 */ -static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const)); - -typedef struct -{ - FLASH_WORD_SIZE extval; - unsigned short intval; -} map_entry; - -#if 0 -static int -byte_parity_odd(unsigned char x) -{ - x ^= x >> 4; - x ^= x >> 2; - x ^= x >> 1; - return (x & 0x1) != 0; -} -#endif /* 0 */ - - -static unsigned long -flash_id(unsigned char mfct, unsigned char chip) -{ - static const map_entry mfct_map[] = - { - {(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, - {(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, - {(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, - {(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, - {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, - {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} - }; - - static const map_entry chip_map[] = - { - {AMD_ID_F040B, FLASH_AM040}, - {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} - }; - - const map_entry *p; - unsigned long result = FLASH_UNKNOWN; - - /* find chip id */ - for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) - if(p->extval == chip) - { - result = FLASH_VENDMASK | p->intval; - break; - } - - /* find vendor id */ - for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) - if(p->extval == mfct) - { - result &= ~FLASH_VENDMASK; - result |= (unsigned long) p->intval << 16; - break; - } - - return result; -} - - -unsigned long -flash_init(void) -{ - unsigned long i; - unsigned char j; - static const ulong flash_banks[] = CFG_FLASH_BANKS; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) - { - flash_info_t * const pflinfo = &flash_info[i]; - pflinfo->flash_id = FLASH_UNKNOWN; - pflinfo->size = 0; - pflinfo->sector_count = 0; - } - - /* Enable writes to Sandpoint flash */ - { - register unsigned char temp; - CONFIG_READ_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); - temp &= ~0x20; /* clear BIOSWP bit */ - CONFIG_WRITE_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); - } - - for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) - { - flash_info_t * const pflinfo = &flash_info[i]; - const unsigned long base_address = flash_banks[i]; - volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address; -#if 0 - volatile FLASH_WORD_SIZE * addr2; -#endif -#if 0 - /* write autoselect sequence */ - flash[0x5555] = 0xaa; - flash[0x2aaa] = 0x55; - flash[0x5555] = 0x90; -#else - flash[0xAAA << (3 * i)] = 0xaa; - flash[0x555 << (3 * i)] = 0x55; - flash[0xAAA << (3 * i)] = 0x90; -#endif - __asm__ __volatile__("sync"); - -#if 0 - pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]); -#else - pflinfo->flash_id = flash_id(flash[0x0], flash[0x2 + 14 * i]); -#endif - - switch(pflinfo->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: - pflinfo->size = 0x00080000; - pflinfo->sector_count = 8; - for(j = 0; j < 8; j++) - { - pflinfo->start[j] = base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_STM800AB: - pflinfo->size = 0x00100000; - pflinfo->sector_count = 19; - pflinfo->start[0] = base_address; - pflinfo->start[1] = base_address + 0x4000; - pflinfo->start[2] = base_address + 0x6000; - pflinfo->start[3] = base_address + 0x8000; - for(j = 1; j < 16; j++) - { - pflinfo->start[j+3] = base_address + 0x00010000 * j; - } -#if 0 - /* check for protected sectors */ - for (j = 0; j < pflinfo->sector_count; j++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(pflinfo->start[j]); - if (pflinfo->flash_id & FLASH_MAN_SST) - pflinfo->protect[j] = 0; - else - pflinfo->protect[j] = addr2[2] & 1; - } -#endif - break; - } - /* Protect monitor and environment sectors - */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - /* reset device to read mode */ - flash[0x0000] = 0xf0; - __asm__ __volatile__("sync"); - } - - return flash_info[0].size + flash_info[1].size; -} - -#if 0 -static void -flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) - { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} -#endif /* 0 */ - -/*----------------------------------------------------------------------- - */ -void -flash_print_info(flash_info_t *info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if(info->flash_id != FLASH_UNKNOWN) - { - switch(info->flash_id & FLASH_VENDMASK) - { - case FLASH_MAN_AMD: mfct = "AMD"; break; - case FLASH_MAN_FUJ: mfct = "FUJITSU"; break; - case FLASH_MAN_STM: mfct = "STM"; break; - case FLASH_MAN_SST: mfct = "SST"; break; - case FLASH_MAN_BM: mfct = "Bright Microelectonics"; break; - case FLASH_MAN_INTEL: mfct = "Intel"; break; - } - - switch(info->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: type = "AM29F040B (512K * 8, uniform sector size)"; break; - case FLASH_AM400B: type = "AM29LV400B (4 Mbit, bottom boot sect)"; break; - case FLASH_AM400T: type = "AM29LV400T (4 Mbit, top boot sector)"; break; - case FLASH_AM800B: type = "AM29LV800B (8 Mbit, bottom boot sect)"; break; - case FLASH_AM800T: type = "AM29LV800T (8 Mbit, top boot sector)"; break; - case FLASH_AM160T: type = "AM29LV160T (16 Mbit, top boot sector)"; break; - case FLASH_AM320B: type = "AM29LV320B (32 Mbit, bottom boot sect)"; break; - case FLASH_AM320T: type = "AM29LV320T (32 Mbit, top boot sector)"; break; - case FLASH_STM800AB: type = "M29W800AB (8 Mbit, bottom boot sect)"; break; - case FLASH_SST800A: type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; break; - case FLASH_SST160A: type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; break; - } - } - - printf( - "\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, - type, - info->size >> 10, - info->sector_count - ); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) - { - unsigned long size; - unsigned int erased; - unsigned long * flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = - (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for( - flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) && erased; - flash++ - ) - erased = *flash == ~0x0UL; - - printf( - "%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", - info->protect[i] ? "RO" : " " - ); - } - - puts("\n"); - return; -} - -#if 0 - -/* - * The following code cannot be run from FLASH! - */ -ulong -flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - printf("flash_get_size: \n"); - /* Write auto select command: read Manufacturer ID */ - eieio(); - addr2[ADDR0] = (FLASH_WORD_SIZE)0xAA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x55; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x90; - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - printf("recognised manufacturer"); - - value = addr2[ADDR3]; /* device ID */ - debug ("\ndev_code=%x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf("flash id %lx; sector count %x, size %lx\n", info->flash_id,info->sector_count,info->size); - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) - { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if (info->flash_id & FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -#endif - - -int -flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *)(info->start[0] + ( - (info->start[sect] - info->start[0]) << sh8b)); - if (info->flash_id & FLASH_MAN_SST) - { - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - udelay(30000); /* wait 30 ms */ - } - else - addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *)(info->start[0] + ( - (info->start[l_sect] - info->start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c deleted file mode 100644 index d3445bd..0000000 --- a/board/sandpoint/sandpoint.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -int checkboard (void) -{ - /*TODO: Check processor type */ - - puts ( "Board: Sandpoint " -#ifdef CONFIG_MPC8240 - "8240" -#endif -#ifdef CONFIG_MPC8245 - "8245" -#endif - " Unity ##Test not implemented yet##\n"); - return 0; -} - -#if 0 /* NOT USED */ -int checkflash (void) -{ - /* TODO: XXX XXX XXX */ - printf ("## Test not implemented yet ##\n"); - - return (0); -} -#endif - -long int initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, - PCI_ENET1_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} diff --git a/board/sandpoint/speed.h b/board/sandpoint/speed.h deleted file mode 100644 index b66393b..0000000 --- a/board/sandpoint/speed.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds deleted file mode 100644 index 2a5cd2e..0000000 --- a/board/sandpoint/u-boot.lds +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sbc405/Makefile b/board/sbc405/Makefile deleted file mode 100644 index c4198c4..0000000 --- a/board/sbc405/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o strataflash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/sbc405/config.mk b/board/sbc405/config.mk deleted file mode 100644 index bd57217..0000000 --- a/board/sbc405/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Wind River sbc405 boards -# - -TEXT_BASE = 0xFFFC0000 diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c deleted file mode 100644 index cad5873..0000000 --- a/board/sbc405/sbc405.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2001 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (epcr, 0xa8400000); - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming sbc405"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - return spd_sdram (0); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 64 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c deleted file mode 100644 index d21d885..0000000 --- a/board/sbc405/strataflash.c +++ /dev/null @@ -1,793 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for ppcboot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#else - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - - CFG_MONITOR_LEN, - - 1, &flash_info[1]); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO - int k; - int size; - int erased; - volatile unsigned long *flash; - - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;iportwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; iportwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; isector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/sbc405/u-boot.lds b/board/sbc405/u-boot.lds deleted file mode 100644 index 39fba61..0000000 --- a/board/sbc405/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sbc8240/Makefile b/board/sbc8240/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/sbc8240/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/sbc8240/README b/board/sbc8240/README deleted file mode 100644 index 71595b4..0000000 --- a/board/sbc8240/README +++ /dev/null @@ -1,140 +0,0 @@ -The supported features of the SBC8240/8245 board are: - 8240 or 8245 processor - 66MHz & 100MHz bus speed - Decrementer timer - 1 UART channel (Console channel) - 8240 Interrupt Controller - 8240 PCI bridge - 8240 Memory Controller - SDRAM (16, 64 MB Memory DIMM) - FLASH 512K On board - FLASH 4MB On board - - -Memory Map from CPU point of view: - - Start Size Access to - ----------------------------------------------------- - 0x00000000 64MB SDRAM DIMM - 0xFF000000 4MB On Board FLASH - 0xFFF00000 512K On Board FLASH or SRAM (Configured by jumper) - 0xFFE00000 8K EEPROM - 0xFFE80000 8Bit LED - 0xFFF80000 8Bit UART - - -Setting the board Jumpers & Switches: - - In order to get the board running with the default configuration the - jumpers need to be set as follows: - - General Jumpers: - ____________________________________________ - | Jumpers | Jumpers | Jumpers | - |-------------|--------------|---------------| - |JP1 1-2 | JP14 1-2 | JP27 1-2 | - |JP5 Open | JP15 1-2 | JP28 2-3 | - |JP8 1-2 | JP16 1-2 | JP33 Open | - |JP9 1-2 | JP17 1-2 | JP37 Close | - |JP10 1-2 | JP18 1-2 | | - |JP11 2-3 | JP19 1-2 | | - |JP12 1-2 | JP20 1-2 | | - |JP13 1-2 | JP25 Open | | - |_____________|______________|_______________| - - Bus speed Jumpers: - _________________________ - | 100MHz Bus | 66 MHz Bus | - |------------|------------| - | JP2 1-2 | JP2 1-2 | - | JP3 1-2 | JP3 2-3 | - | JP4 1-2 | JP4 2-3 | - | JP6 1-2 | JP6 2-3 | - | JP7 1-2 | JP7 1-2 | - |____________|____________| - - -U-Boot 1.1.2 (Jun 24 2004 - 17:01:04) - -CPU: MPC8240 Revision 1.1 at 247.500 MHz: 16 kB I-Cache 16 kB D-Cache -Board: sbc8240 Revision 255 Local Bus at 99 MHz -DRAM: 64 MB -FLASH: 512 kB - 00 11 8086 1229 0200 00 -In: serial -Out: serial -Err: serial -Net: i82559#0 - -Welcome to U-Boot for the sbc8240 - -Type ? or help to get on-line help - -Hit any key to stop autoboot: 0 -=> printenv -bootcmd=version;echo;tftpboot $loadaddr $loadfile;bootvx -bootdelay=5 -baudrate=9600 -ethaddr=DE:AD:BE:EF:01:01 -ipaddr=192.168.193.102 -preboot=echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type "? or help" to get on-line help;echo -netmask=255.255.255.248 -clocks_in_mhz=1 -bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei -ipaddr=192.168.193.102 -loadfile=vxWorks.st -loadaddr=0x01000000 -net_load=tftpboot $loadaddr $loadfile -serverip=192.168.193.99 -ethact=i82559#0 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 631/16380 bytes -=> boot - -U-Boot 1.1.2 (Jun 24 2004 - 17:01:04) - -Using i82559#0 device -TFTP from server 192.168.193.99; our IP address is 192.168.193.102 -Filename 'vxWorks.st'. -Load address: 0x1000000 -Loading: ################################################################# - ################################################################# - ############################################################## -done -Bytes transferred = 979927 (ef3d7 hex) -## Ethernet MAC address not copied to NV RAM -Loading .text @ 0x00100000 (758848 bytes) -Loading .data @ 0x001b9440 (79904 bytes) -Clearing .bss @ 0x001ccc60 (20288 bytes) -## Using bootline (@ 0x4200): $fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei -## Starting vxWorks at 0x00100000 ... - -Adding 2845 symbols for standalone. - - - ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] - ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] - ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] - ]]]]]]]]]]] ]]]] ]]]]]]]]]] ]] ]]]] (R) - ] ]]]]]]]]] ]]]]]] ]]]]]]]] ]] ]]]] - ]] ]]]]]]] ]]]]]]]] ]]]]]] ] ]] ]]]] - ]]] ]]]]] ] ]]] ] ]]]] ]]] ]]]]]]]]] ]]]] ]] ]]]] ]] ]]]]] - ]]]] ]]] ]] ] ]]] ]] ]]]]] ]]]]]] ]] ]]]]]]] ]]]] ]] ]]]] - ]]]]] ] ]]]] ]]]]] ]]]]]]]] ]]]] ]] ]]]] ]]]]]]] ]]]] - ]]]]]] ]]]]] ]]]]]] ] ]]]]] ]]]] ]] ]]]] ]]]]]]]] ]]]] - ]]]]]]] ]]]]] ] ]]]]]] ] ]]] ]]]] ]] ]]]] ]]]] ]]]] ]]]] - ]]]]]]]] ]]]]] ]]] ]]]]]]] ] ]]]]]]] ]]]] ]]]] ]]]] ]]]]] - ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] - ]]]]]]]]]]]]]]]]]]]]]]]]]]]]] Development System - ]]]]]]]]]]]]]]]]]]]]]]]]]]]] - ]]]]]]]]]]]]]]]]]]]]]]]]]]] VxWorks version 5.5.1 - ]]]]]]]]]]]]]]]]]]]]]]]]]] KERNEL: WIND version 2.6 - ]]]]]]]]]]]]]]]]]]]]]]]]] Copyright Wind River Systems, Inc., 1984-2003 - - CPU: MPC8240 -- Wind River BSP. SBC8240 Board. Processor #0. - Memory Size: 0x2000000. BSP version 1.2/28. - --> diff --git a/board/sbc8240/config.mk b/board/sbc8240/config.mk deleted file mode 100644 index 1e97960..0000000 --- a/board/sbc8240/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# sbc8240 board -# - -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/sbc8240/flash.c b/board/sbc8240/flash.c deleted file mode 100644 index dec6156..0000000 --- a/board/sbc8240/flash.c +++ /dev/null @@ -1,638 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include -#include -#include - -#if CFG_MAX_FLASH_BANKS != 1 -#error "CFG_MAX_FLASH_BANKS must be 1" -#endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - - /* Init: no FLASHes known */ - flash_info[0].flash_id = FLASH_UNKNOWN; - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - /* Setup offsets */ - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM, - FLASH_BASE0_PRELIM + monitor_flash_len - 1, - &flash_info[0]); - flash_info[0].size = size_b0; - - return size_b0; -} - - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: - printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *) info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; - - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ -#if 0 /* enable when device IDs are available */ - case (FLASH_WORD_SIZE) AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - case (FLASH_WORD_SIZE) SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7 (flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = - (FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); - printf ("Erasing sector %p\n", addr2); /* CLH */ - - if ((info->flash_id & FLASH_VENDMASK) == - FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay (1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7 (info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7 (info, l_sect); - - DONE: -#endif - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = - (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/sbc8240/sbc8240.c b/board/sbc8240/sbc8240.c deleted file mode 100644 index a6d3bab..0000000 --- a/board/sbc8240/sbc8240.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, - - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define BOARD_REV_REG 0xFE80002B - -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - char revision = *(volatile char *)(BOARD_REV_REG); - char buf[32]; - - puts ("Board: sbc8240 "); - printf("Revision %d ", revision); - printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk)); - - return 0; -} - -long int initdram(int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices, report devices found. - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - - { } -}; -#endif - -struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_sandpoint_config_table, -#endif -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} - -#ifdef CONFIG_MISC_INIT_R -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ -#ifdef CFG_LED_BASE - *((unsigned char *) (CFG_LED_BASE)) = 0xFF; -#endif /* CFG_LED_BASE */ - - return (0); -} -#endif /* CONFIG_MISC_INIT_R */ diff --git a/board/sbc8240/u-boot.lds b/board/sbc8240/u-boot.lds deleted file mode 100644 index 7be85e4..0000000 --- a/board/sbc8240/u-boot.lds +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sbc8260/Makefile b/board/sbc8260/Makefile deleted file mode 100644 index 14ed457..0000000 --- a/board/sbc8260/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := sbc8260.o flash.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/sbc8260/config.mk b/board/sbc8260/config.mk deleted file mode 100644 index 1f18260..0000000 --- a/board/sbc8260/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MBX8xx boards -# - -TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/sbc8260/flash.c b/board/sbc8260/flash.c deleted file mode 100644 index 9a8b952..0000000 --- a/board/sbc8260/flash.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger - * Sysgo Real-Time Solutions, GmbH - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AMD 29F080B devices - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; i= CFG_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F080B: - printf ("AM29F080B (8 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - vu_long vendor, devid; - ulong base = (ulong)addr; - -/* printf("addr = %08lx\n", (unsigned long)addr); */ - - /* Reset and Write auto select command: read Manufacturer ID */ - addr[0] = 0xf0f0f0f0; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - udelay (1000); - - vendor = addr[0]; -/* printf("vendor = %08lx\n", vendor); */ - if (vendor != 0x01010101) { - info->size = 0; - goto out; - } - - devid = addr[1]; -/* printf("devid = %08lx\n", devid); */ - - if ((devid & 0xff) == AMD_ID_F080B) { - info->flash_id = (vendor & 0xff) << 16 | AMD_ID_F080B; - /* we have 16 sectors with 64KB each x 4 */ - info->sector_count = 16; - info->size = 4 * info->sector_count * 64*1024; - } - else { - info->size = 0; - goto out; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* reset command */ - addr = (vu_long *)info->start[0]; - -out: - addr[0] = 0xf0f0f0f0; - - return info->size; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - udelay (100); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/sbc8260/sbc8260.c b/board/sbc8260/sbc8260.c deleted file mode 100644 index 48aefa0..0000000 --- a/board/sbc8260/sbc8260.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 0, 0, 1, 0, 0 }, /* PB17 */ - /* PB16 */ { 1, 0, 0, 1, 0, 0 }, /* PB16 */ - /* PB15 */ { 1, 0, 0, 1, 0, 0 }, /* PB15 */ - /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* PB14 */ - /* PB13 */ { 1, 0, 0, 1, 0, 0 }, /* PB13 */ - /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* PB12 */ - /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* PB11 */ - /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* PB10 */ - /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* PB9 */ - /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* PB8 */ - /* PB7 */ { 1, 0, 0, 1, 0, 0 }, /* PB7 */ - /* PB6 */ { 1, 0, 0, 1, 0, 0 }, /* PB6 */ - /* PB5 */ { 1, 0, 0, 1, 0, 0 }, /* PB5 */ - /* PB4 */ { 1, 0, 0, 1, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 1, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 1, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 1, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 1, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ -#if defined(CONFIG_SOFT_I2C) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 1, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 1, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 1, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: EST SBC8260\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8); - ulong psdmr = CFG_PSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* return total ram size */ - return (CFG_SDRAM0_SIZE * 1024 * 1024); -} - -#ifdef CONFIG_MISC_INIT_R -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ -#ifdef CFG_LED_BASE - uchar ds = *(unsigned char *) (CFG_LED_BASE + 1); - uchar ss; - uchar tmp[64]; - int res; - - if ((ds != 0) && (ds != 0xff)) { - res = getenv_r ("ethaddr", tmp, sizeof (tmp)); - if (res > 0) { - ss = ((ds >> 4) & 0x0f); - ss += ss < 0x0a ? '0' : ('a' - 10); - tmp[15] = ss; - - ss = (ds & 0x0f); - ss += ss < 0x0a ? '0' : ('a' - 10); - tmp[16] = ss; - - tmp[17] = '\0'; - setenv ("ethaddr", tmp); - /* set the led to show the address */ - *((unsigned char *) (CFG_LED_BASE + 1)) = ds; - } - } -#endif /* CFG_LED_BASE */ - return (0); -} -#endif /* CONFIG_MISC_INIT_R */ diff --git a/board/sbc8260/u-boot.lds b/board/sbc8260/u-boot.lds deleted file mode 100644 index 9e623d0..0000000 --- a/board/sbc8260/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile deleted file mode 100644 index da295fb..0000000 --- a/board/sbc8560/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004 Wind River Systems Inc . -# Added support for Wind River SBC8560 board -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o -SOBJS := init.o -#SOBJS := - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/sbc8560/config.mk b/board/sbc8560/config.mk deleted file mode 100644 index 6d9ae45..0000000 --- a/board/sbc8560/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# Modified by Xianghua Xiao, X.Xiao@motorola.com -# (C) Copyright 2002,2003 Motorola Inc. -# -# (C) Copyright 2004 Wind River Systems Inc . -# Added support for Wind River SBC8560 board -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# -# based on mpc8560ads board -# default CCARBAR is at 0xff700000 -# assume U-Boot is less than 256K -# -TEXT_BASE = 0xfffc0000 - -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S deleted file mode 100644 index 3d8d180..0000000 --- a/board/sbc8560/init.S +++ /dev/null @@ -1,165 +0,0 @@ -/* -* Copyright (C) 2002,2003, Motorola Inc. -* Xianghua Xiao -* -* (C) Copyright 2004 Wind River Systems Inc . -* Added support for Wind River SBC8560 board -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include -#include - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - -/* LAW(Local Access Window) configuration: - * 0000_0000-0800_0000: DDR(512M) -or- larger - * c000_0000-cfff_ffff: PCI(256M) - * d000_0000-dfff_ffff: RapidIO(256M) - * e000_0000-ffff_ffff: localbus(512M) - * e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6 - * e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1 - * e800_0000-efff_ffff: LBC 128M, nothing here - * f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3 - * f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4 - * f800_0000-fdff_ffff: LBC 64M, nothing here - * fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5 - * fd00_0000-fdff_ffff: LBC 16M, nothing here - * fe00_0000-feff_ffff: LBC 16M, nothing here - * ff00_0000-ff6f_ffff: LBC 7M, nothing here - * ff70_0000-ff7f_ffff: CCSRBAR 1M - * ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0 - * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access - * Window. - * Note: If flash is 8M at default position(last 8M),no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) - #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) - #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) -#else - #define LAWBAR0 0 - #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR2 ((0xe0000000>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x03 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 - entry_end - -/* TLB1 entries configuration: */ - - .section .bootpg, "ax" - .globl tlb1_entry - -tlb1_entry: - entry_start - - .long 0x08 /* the following data table uses a few of 16 TLB entries */ - -/* TLB for CCSRBAR (IMMR) */ - - .long TLB1_MAS0(1,1,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - -/* TLB for Local Bus stuff, just map the whole 512M */ -/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ - - .long TLB1_MAS0(1,2,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((0xe0000000>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((0xe0000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,3,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((0xf0000000>>12)&0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((0xf0000000>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1) - -#if !defined(CONFIG_SPD_EEPROM) - .long TLB1_MAS0(1,4,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) - .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,5,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0) - .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) -#else - .long TLB1_MAS0(1,4,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,5,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) -#endif - - .long TLB1_MAS0(1,6,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) -#ifdef CONFIG_L2_INIT_RAM - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0) -#else - .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0) -#endif - .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1,7,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) - .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - .long TLB1_MAS0(1,15,0) - .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) - .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) -#else - .long TLB1_MAS0(1,15,0) - .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) - .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) - .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) -#endif - entry_end diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c deleted file mode 100644 index e8b9929..0000000 --- a/board/sbc8560/sbc8560.c +++ /dev/null @@ -1,460 +0,0 @@ -/* - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * (C) Copyright 2004 Wind River Systems Inc . - * Added support for Wind River SBC8560 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -extern long int spd_sdram (void); - -#include -#include -#include -#include -#include -#include - -long int fixed_sdram (void); - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ - /* PD27 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */ - /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -int board_early_init_f (void) -{ -#if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; - - pci->peer &= 0xfffffffdf; /* disable master abort */ -#endif - return 0; -} - -void reset_phy (void) -{ -#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ - volatile unsigned char *bcsr = (unsigned char *) CFG_BCSR; -#endif - /* reset Giga bit Ethernet port if needed here */ - - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr[0] &= ~0x20; - udelay(2); - bcsr[0] |= 0x20; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr[0] &= ~0x10; - udelay(2); - bcsr[0] |= 0x10; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1 ETHERNET", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); -#endif /* CONFIG_MII */ -} - -int checkboard (void) -{ - sys_info_t sysinfo; - - get_sys_info (&sysinfo); - -#ifdef CONFIG_SBC8560 - printf ("Board: Wind River SBC8560 Board\n"); -#else - printf ("Board: Wind River SBC8540 Board\n"); -#endif - printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); - printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000); - printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); - if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \ - || (CFG_LBC_LCRR & 0x0f) == 8) { - printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f)); - } else { - printf("\tLBC: unknown\n"); - } - printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); - printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n"); - return (0); -} - - -long int initdram (int board_type) -{ - long dram_size = 0; - extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; -#if 0 -#if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc= &immap->im_lbc; - sys_info_t sysinfo; - uint temp_lbcdll = 0; -#endif -#endif /* 0 */ -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur= &immap->im_gur; -#endif -#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - -#if 0 -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */ - get_sys_info(&sysinfo); - /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; - } else { -#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */ - lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */ -#endif - lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; - udelay(200); - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; - asm("sync;isync;msync"); - } - lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ - lbc->br2 = CFG_BR2_PRELIM; - lbc->lbcr = CFG_LBC_LBCR; - lbc->lsdmr = CFG_LBC_LSDMR_1; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_2; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_3; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_5; - asm("sync"); - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - lbc->mrtpr = CFG_LBC_MRTPR; - asm("sync"); -#endif -#endif - -#if defined(CONFIG_DDR_ECC) - { - /* Initialize all of memory for ECC, then - * enable errors */ - uint *p = 0; - uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - dma_init(); - for (*p = 0; p < (uint *)(8 * 1024); p++) { - if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } - *p = (unsigned int)0xdeadbeef; - if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } - } - - /* 8K */ - dma_xfer((uint *)0x2000,0x2000,(uint *)0); - /* 16K */ - dma_xfer((uint *)0x4000,0x4000,(uint *)0); - /* 32K */ - dma_xfer((uint *)0x8000,0x8000,(uint *)0); - /* 64K */ - dma_xfer((uint *)0x10000,0x10000,(uint *)0); - /* 128k */ - dma_xfer((uint *)0x20000,0x20000,(uint *)0); - /* 256k */ - dma_xfer((uint *)0x40000,0x40000,(uint *)0); - /* 512k */ - dma_xfer((uint *)0x80000,0x80000,(uint *)0); - /* 1M */ - dma_xfer((uint *)0x100000,0x100000,(uint *)0); - /* 2M */ - dma_xfer((uint *)0x200000,0x200000,(uint *)0); - /* 4M */ - dma_xfer((uint *)0x400000,0x400000,(uint *)0); - - for (i = 1; i < dram_size / 0x800000; i++) { - dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); - } - - /* Enable errors for ECC */ - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - } -#endif - - return dram_size; -} - - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) -{ - -#define CFG_DDR_CONTROL 0xc2000000 - - #ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - - ddr->cs0_bnds = 0x00000007; - ddr->cs1_bnds = 0x0010001f; - ddr->cs2_bnds = 0x00000000; - ddr->cs3_bnds = 0x00000000; - ddr->cs0_config = 0x80000102; - ddr->cs1_config = 0x80000102; - ddr->cs2_config = 0x00000000; - ddr->cs3_config = 0x00000000; - ddr->timing_cfg_1 = 0x37334321; - ddr->timing_cfg_2 = 0x00000800; - ddr->sdram_cfg = 0x42000000; - ddr->sdram_mode = 0x00000022; - ddr->sdram_interval = 0x05200100; - ddr->err_sbe = 0x00ff0000; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CFG_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CFG_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds deleted file mode 100644 index 48e19fe..0000000 --- a/board/sbc8560/u-boot.lds +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2002,2003,Motorola,Inc. - * Xianghua Xiao, X.Xiao@motorola.com. - * - * (C) Copyright 2004 Wind River Systems Inc . - * Added support for Wind River SBC8560 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - board/sbc8560/init.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc85xx/start.o (.text) - board/sbc8560/init.o (.text) - cpu/mpc85xx/commproc.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/serial_scc.o (.text) - cpu/mpc85xx/ether_fcc.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/i2c.o (.text) - cpu/mpc85xx/spd_sdram.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sc520_cdp/Makefile b/board/sc520_cdp/Makefile deleted file mode 100644 index ab06ebc..0000000 --- a/board/sc520_cdp/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2002 -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := sc520_cdp.o flash.o -SOBJS := sc520_cdp_asm.o sc520_cdp_asm16.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/sc520_cdp/config.mk b/board/sc520_cdp/config.mk deleted file mode 100644 index 2253815..0000000 --- a/board/sc520_cdp/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2002 -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - - -TEXT_BASE = 0x387c0000 diff --git a/board/sc520_cdp/flash.c b/board/sc520_cdp/flash.c deleted file mode 100644 index d52a847..0000000 --- a/board/sc520_cdp/flash.c +++ /dev/null @@ -1,637 +0,0 @@ -/* - * (C) Copyright 2002, 2003 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define PROBE_BUFFER_SIZE 1024 -static unsigned char buffer[PROBE_BUFFER_SIZE]; - -#define SC520_MAX_FLASH_BANKS 3 -#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */ -#define SC520_FLASH_BANK1_BASE 0x30000000 /* ROMCS0 */ -#define SC520_FLASH_BANK2_BASE 0x28000000 /* ROMCS1 */ -#define SC520_FLASH_BANKSIZE 0x8000000 - -#define AMD29LV016B_SIZE 0x200000 -#define AMD29LV016B_SECTORS 32 - -flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - - -static u32 _probe_flash(u32 addr, u32 bw, int il) -{ - u32 result=0; - - /* First do an unlock cycle for the benefit of - * devices that need it */ - - switch (bw) { - - case 1: - *(volatile u8*)(addr+0x5555) = 0xaa; - *(volatile u8*)(addr+0x2aaa) = 0x55; - *(volatile u8*)(addr+0x5555) = 0x90; - - /* Read vendor */ - result = *(volatile u8*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u8*)(addr+2); - - /* Return device to data mode */ - *(volatile u8*)addr = 0xff; - *(volatile u8*)(addr+0x5555), 0xf0; - break; - - case 2: - *(volatile u16*)(addr+0xaaaa) = 0xaaaa; - *(volatile u16*)(addr+0x5554) = 0x5555; - - /* Issue identification command */ - if (il == 2) { - *(volatile u16*)(addr+0xaaaa) = 0x9090; - - /* Read vendor */ - result = *(volatile u8*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u8*)(addr+2); - - /* Return device to data mode */ - *(volatile u16*)addr = 0xffff; - *(volatile u16*)(addr+0xaaaa), 0xf0f0; - - } else { - *(volatile u8*)(addr+0xaaaa) = 0x90; - /* Read vendor */ - result = *(volatile u16*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u16*)(addr+2); - - /* Return device to data mode */ - *(volatile u8*)addr = 0xff; - *(volatile u8*)(addr+0xaaaa), 0xf0; - } - - break; - - case 4: - *(volatile u32*)(addr+0x5554) = 0xaaaaaaaa; - *(volatile u32*)(addr+0xaaa8) = 0x55555555; - - switch (il) { - case 1: - /* Issue identification command */ - *(volatile u8*)(addr+0x5554) = 0x90; - - /* Read vendor */ - result = *(volatile u16*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u16*)(addr+4); - - /* Return device to data mode */ - *(volatile u8*)addr = 0xff; - *(volatile u8*)(addr+0x5554), 0xf0; - break; - - case 2: - /* Issue identification command */ - *(volatile u32*)(addr + 0x5554) = 0x00900090; - - /* Read vendor */ - result = *(volatile u16*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u16*)(addr+4); - - /* Return device to data mode */ - *(volatile u32*)addr = 0x00ff00ff; - *(volatile u32*)(addr+0x5554), 0x00f000f0; - break; - - case 4: - /* Issue identification command */ - *(volatile u32*)(addr+0x5554) = 0x90909090; - - /* Read vendor */ - result = *(volatile u8*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u8*)(addr+4); - - /* Return device to data mode */ - *(volatile u32*)addr = 0xffffffff; - *(volatile u32*)(addr+0x5554), 0xf0f0f0f0; - break; - } - break; - } - - - return result; -} - -extern int _probe_flash_end; -asm ("_probe_flash_end:\n" - ".long 0\n"); - -static int identify_flash(unsigned address, int width) -{ - int is; - int device; - int vendor; - int size; - unsigned res; - - u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il); - - size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; - - if (size > PROBE_BUFFER_SIZE) { - printf("_probe_flash() routine too large (%d) %p - %p\n", - size, &_probe_flash_end, _probe_flash); - return 0; - } - - memcpy(buffer, _probe_flash, size); - _probe_flash_ptr = (void*)buffer; - - is = disable_interrupts(); - res = _probe_flash_ptr(address, width, 1); - if (is) { - enable_interrupts(); - } - - - vendor = res >> 16; - device = res & 0xffff; - - - return res; -} - -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { - unsigned id; - ulong flashbase = 0; - int sectsize = 0; - - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - switch (i) { - case 0: - flashbase = SC520_FLASH_BANK0_BASE; - break; - case 1: - flashbase = SC520_FLASH_BANK1_BASE; - break; - case 2: - flashbase = SC520_FLASH_BANK2_BASE; - break; - default: - panic("configured too many flash banks!\n"); - } - - id = identify_flash(flashbase, 4); - switch (id & 0x00ff00ff) { - case 0x000100c8: - /* 29LV016B/29LV017B */ - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV016B & FLASH_TYPEMASK); - - flash_info[i].size = AMD29LV016B_SIZE*4; - flash_info[i].sector_count = AMD29LV016B_SECTORS; - sectsize = (AMD29LV016B_SIZE*4)/AMD29LV016B_SECTORS; - printf("Bank %d: 4 x AMD 29LV017B\n", i); - break; - - - default: - printf("Bank %d have unknown flash %08x\n", i, id); - flash_info[i].flash_id = FLASH_UNKNOWN; - continue; - } - - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j * sectsize; - } - size += flash_info[i].size; - - flash_protect(FLAG_PROTECT_CLEAR, - flash_info[i].start[0], - flash_info[i].start[0] + flash_info[i].size - 1, - &flash_info[i]); - } - - /* - * Protect monitor and environment sectors - */ - flash_protect(FLAG_PROTECT_SET, - i386boot_start, - i386boot_end, - &flash_info[0]); -#ifdef CFG_ENV_ADDR - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - - case (AMD_MANUFACT & FLASH_VENDMASK): - printf("AMD: "); - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV016B & FLASH_TYPEMASK): - printf("4x AMD29LV017B (4x16Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - goto done; - break; - } - - break; - default: - printf("Unknown Vendor "); - break; - } - - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -done: ; -} - -/*----------------------------------------------------------------------- - */ - -/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */ -#define __udelay(delay) \ -{ \ - unsigned micro; \ - unsigned milli=0; \ - \ - micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ - \ - for (;;) { \ - \ - milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ - micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \ - \ - if ((delay) <= (micro + (milli * 1000))) { \ - break; \ - } \ - } \ -} while (0) - -static u32 _amd_erase_flash(u32 addr, u32 sector) -{ - unsigned elapsed; - - /* Issue erase */ - *(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA; - *(volatile u32*)(addr + 0xaaa8) = 0x55555555; - *(volatile u32*)(addr + 0x5554) = 0x80808080; - /* And one unlock */ - *(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA; - *(volatile u32*)(addr + 0xaaa8) = 0x55555555; - /* Sector erase command comes last */ - *(volatile u32*)(addr + sector) = 0x30303030; - - elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ - elapsed = 0; - __udelay(50); - while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) { - - elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { - *(volatile u32*)(addr) = 0xf0f0f0f0; - return 1; - } - } - - *(volatile u32*)(addr) = 0xf0f0f0f0; - - return 0; -} - -extern int _amd_erase_flash_end; -asm ("_amd_erase_flash_end:\n" - ".long 0\n"); - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - u32 (*_erase_flash_ptr)(u32 a, u32 so); - int prot; - int sect; - unsigned size; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { - size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; - - if (size > PROBE_BUFFER_SIZE) { - printf("_amd_erase_flash() routine too large (%d) %p - %p\n", - size, &_amd_erase_flash_end, _amd_erase_flash); - return 0; - } - - memcpy(buffer, _amd_erase_flash, size); - _erase_flash_ptr = (void*)buffer; - - } else { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - - if (info->protect[sect] == 0) { /* not protected */ - int res; - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]); - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - - if (res) { - printf("Erase timed out, sector %d\n", sect); - return res; - } - - putc('.'); - } - } - - - return 0; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int _amd_write_word(unsigned start, unsigned dest, unsigned data) -{ - volatile u32 *addr2 = (u32*)start; - volatile u32 *dest2 = (u32*)dest; - volatile u32 *data2 = (u32*)&data; - unsigned elapsed; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile u32*)dest) & (u32)data) != (u32)data) { - return 2; - } - - addr2[0x5554] = 0xAAAAAAAA; - addr2[0xaaa8] = 0x55555555; - addr2[0x5554] = 0xA0A0A0A0; - - dest2[0] = data; - - elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ - elapsed = 0; - - /* data polling for D7 */ - while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) { - elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { - addr2[0] = 0xf0f0f0f0; - return 1; - } - } - - - addr2[0] = 0xf0f0f0f0; - - return 0; -} - -extern int _amd_write_word_end; -asm ("_amd_write_word_end:\n" - ".long 0\n"); - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - Unsupported flash type - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - int flag; - u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data); - unsigned size; - - if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { - size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; - - if (size > PROBE_BUFFER_SIZE) { - printf("_amd_write_word() routine too large (%d) %p - %p\n", - size, &_amd_write_word_end, _amd_write_word); - return 0; - } - - memcpy(buffer, _amd_write_word, size); - _write_word_ptr = (void*)buffer; - - } else { - printf ("Can't program unknown flash type - aborted\n"); - return 3; - } - - - wp = (addr & ~3); /* get lower word aligned address */ - - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data |= *src++ << (8*i); - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data |= (*(uchar *)cp) << (8*i); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - rc = _write_word_ptr(info->start[0], wp, data); - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - if (rc != 0) { - return rc; - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - - for (i=0; i<4; ++i) { - data |= *src++ << (8*i); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - rc = _write_word_ptr(info->start[0], wp, data); - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - if (rc != 0) { - return rc; - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return 0; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data |= *src++ << (8*i); - --cnt; - } - - for (; i<4; ++i, ++cp) { - data |= (*(uchar *)cp) << (8*i); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - rc = _write_word_ptr(info->start[0], wp, data); - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - return rc; - -} diff --git a/board/sc520_cdp/flash_old.c b/board/sc520_cdp/flash_old.c deleted file mode 100644 index 3c0f6d6..0000000 --- a/board/sc520_cdp/flash_old.c +++ /dev/null @@ -1,458 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -ulong myflush(void); - - -#define SC520_MAX_FLASH_BANKS 3 -#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */ -#define SC520_FLASH_BANK1_BASE 0x30000000 /* ROMCS0 */ -#define SC520_FLASH_BANK2_BASE 0x28000000 /* ROMCS1 */ -#define SC520_FLASH_BANKSIZE 0x8000000 - -#define AMD29LV016_SIZE 0x200000 -#define AMD29LV016_SECTORS 32 - -flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; - -#define CMD_READ_ARRAY 0x00F000F0 -#define CMD_UNLOCK1 0x00AA00AA -#define CMD_UNLOCK2 0x00550055 -#define CMD_ERASE_SETUP 0x00800080 -#define CMD_ERASE_CONFIRM 0x00300030 -#define CMD_PROGRAM 0x00A000A0 -#define CMD_UNLOCK_BYPASS 0x00200020 - - -#define BIT_ERASE_DONE 0x00800080 -#define BIT_RDY_MASK 0x00800080 -#define BIT_PROGRAM_ERROR 0x00200020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - int sectsize = 0; - if (i==0 || i==2) { - /* FixMe: this assumes that bank 0 and 2 - * are mapped to the two 8Mb banks */ - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV016B & FLASH_TYPEMASK); - - flash_info[i].size = AMD29LV016_SIZE*4; - flash_info[i].sector_count = AMD29LV016_SECTORS; - sectsize = (AMD29LV016_SIZE*4)/AMD29LV016_SECTORS; - } else { - /* FixMe: this assumes that bank1 is unmapped - * (or mapped to the same flash bank as BOOTCS) */ - flash_info[i].flash_id = 0; - flash_info[i].size = 0; - flash_info[i].sector_count = 0; - sectsize=0; - } - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - switch (i) { - case 0: - flashbase = SC520_FLASH_BANK0_BASE; - break; - case 1: - flashbase = SC520_FLASH_BANK1_BASE; - break; - case 2: - flashbase = SC520_FLASH_BANK0_BASE; - break; - default: - panic("configured too many flash banks!\n"); - } - - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = sectsize; - flash_info[i].start[j] = flashbase + j * sectsize; - } - size += flash_info[i].size; - } - - /* - * Protect monitor and environment sectors - */ - flash_protect(FLAG_PROTECT_SET, - i386boot_start-SC520_FLASH_BANK0_BASE, - i386boot_end-SC520_FLASH_BANK0_BASE, - &flash_info[0]); - -#ifdef CFG_ENV_ADDR - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf("AMD: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV016B & FLASH_TYPEMASK): - printf("4x Amd29LV016B (16Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - goto done; - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - done: -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - ulong result; - int iflag, prot, sect; - int rc = ERR_OK; - int chip1, chip2; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) { - return ERR_UNKNOWN_FLASH_TYPE; - } - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - return ERR_PROTECTED; - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { - printf("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer(); - - if (info->protect[sect] == 0) { - /* not protected */ - ulong addr = info->start[sect]; - - writel(CMD_UNLOCK1, addr + 1); - writel(CMD_UNLOCK2, addr + 2); - writel(CMD_ERASE_SETUP, addr + 1); - - writel(CMD_UNLOCK1, addr + 1); - writel(CMD_UNLOCK2, addr + 2); - writel(CMD_ERASE_CONFIRM, addr); - - - /* wait until flash is ready */ - chip1 = chip2 = 0; - - do { - result = readl(addr); - - /* check timeout */ - if (get_timer(0) > CFG_FLASH_ERASE_TOUT) { - writel(CMD_READ_ARRAY, addr + 1); - chip1 = TMO; - break; - } - - if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) { - chip1 = READY; - } - - if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) { - chip1 = ERR; - } - - if (!chip2 && (result >> 16) & BIT_ERASE_DONE) { - chip2 = READY; - } - - if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) { - chip2 = ERR; - } - - } while (!chip1 || !chip2); - - writel(CMD_READ_ARRAY, addr + 1); - - if (chip1 == ERR || chip2 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf("ok.\n"); - } else { /* it was protected */ - - printf("protected!\n"); - } - } - - if (ctrlc()) { - printf("User Interrupt!\n"); - } - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay(10000); - - if (iflag) { - enable_interrupts(); - } - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -volatile static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - ulong addr = dest; - ulong result; - int rc = ERR_OK; - int iflag; - int chip1, chip2; - - /* - * Check if Flash is (sufficiently) erased - */ - result = readl(addr); - if ((result & data) != data) { - return ERR_NOT_ERASED; - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts(); - - writel(CMD_UNLOCK1, addr + 1); - writel(CMD_UNLOCK2, addr + 2); - writel(CMD_UNLOCK_BYPASS, addr + 1); - writel(addr, CMD_PROGRAM); - writel(addr, data); - - /* arm simple, non interrupt dependent timer */ - reset_timer(); - - /* wait until flash is ready */ - chip1 = chip2 = 0; - do { - result = readl(addr); - - /* check timeout */ - if (get_timer(0) > CFG_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - - if (!chip1 && ((result & 0x80) == (data & 0x80))) { - chip1 = READY; - } - - if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = readl(addr); - - if ((result & 0x80) == (data & 0x80)) { - chip1 = READY; - } else { - chip1 = ERR; - } - } - - if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) { - chip2 = READY; - } - - if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) { - result = readl(addr); - - if ((result & (0x80 << 16)) == (data & (0x80 << 16))) { - chip2 = READY; - } else { - chip2 = ERR; - } - } - - } while (!chip1 || !chip2); - - writel(CMD_READ_ARRAY, addr); - - if (chip1 == ERR || chip2 == ERR || readl(addr) != data) { - rc = ERR_PROG_ERROR; - } - - if (iflag) { - enable_interrupts(); - } - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 24); - } - for (; i<4 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return rc; - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((vu_long*)src); - if ((rc = write_word(info, wp, data)) != 0) { - return rc; - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - return write_word(info, wp, data); -} diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c deleted file mode 100644 index cd52324..0000000 --- a/board/sc520_cdp/sc520_cdp.c +++ /dev/null @@ -1,630 +0,0 @@ -/* - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#undef SC520_CDP_DEBUG - -#ifdef SC520_CDP_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -/* ------------------------------------------------------------------------- */ - - -/* - * Theory: - * We first set up all IRQs to be non-pci, edge triggered, - * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets - * called we reallocate irqs to the pci bus with sc520_pci_set_irq() - * as needed. Whe choose the irqs to gram from a configurable list - * inside pci_sc520_fixup_irq() (If this list contains stupid irq's - * such as 0 thngas will not work) - */ - -static void irq_init(void) -{ - /* disable global interrupt mode */ - write_mmcr_byte(SC520_PICICR, 0x40); - - /* set all irqs to edge */ - write_mmcr_byte(SC520_MPICMODE, 0x00); - write_mmcr_byte(SC520_SL1PICMODE, 0x00); - write_mmcr_byte(SC520_SL2PICMODE, 0x00); - - /* active low polarity on PIC interrupt pins, - * active high polarity on all other irq pins */ - write_mmcr_word(SC520_INTPINPOL, 0x0000); - - /* set irq number mapping */ - write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */ - write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */ - write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */ - write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ - write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */ - write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */ - write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */ - write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */ - write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */ - write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */ - write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ - write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED); /* disable Synchronius serial INT */ - write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */ - write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */ - write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */ - write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ - write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ - - if (CFG_USE_SIO_UART) { - write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */ - write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */ - write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ - write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */ - } else { - write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */ - write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */ - write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ3 (ISA IRQ3) */ - write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ4 (ISA IRQ4) */ - } - - write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */ - write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */ - write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */ - write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7); /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */ - write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8); /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */ - write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9); /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */ - write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11); /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */ - write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */ - write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14); /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */ - - write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */ - write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */ - -} - - -/* PCI stuff */ -static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - /* a configurable lists of irqs to steal - * when we need one (a board with more pci interrupt pins - * would use a larger table */ - static int irq_list[] = { - CFG_FIRST_PCI_IRQ, - CFG_SECOND_PCI_IRQ, - CFG_THIRD_PCI_IRQ, - CFG_FORTH_PCI_IRQ - }; - static int next_irq_index=0; - - char tmp_pin; - int pin; - - pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); - pin = tmp_pin; - - pin-=1; /* pci config space use 1-based numbering */ - if (-1 == pin) { - return; /* device use no irq */ - } - - - /* map device number + pin to a pin on the sc520 */ - switch (PCI_DEV(dev)) { - case 20: - pin+=SC520_PCI_INTA; - break; - - case 19: - pin+=SC520_PCI_INTB; - break; - - case 18: - pin+=SC520_PCI_INTC; - break; - - case 17: - pin+=SC520_PCI_INTD; - break; - - default: - return; - } - - pin&=3; /* wrap around */ - - if (sc520_pci_ints[pin] == -1) { - /* re-route one interrupt for us */ - if (next_irq_index > 3) { - return; - } - if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { - return; - } - next_irq_index++; - } - - - if (-1 != sc520_pci_ints[pin]) { - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, - sc520_pci_ints[pin]); - } - PRINTF("fixup_irq: device %d pin %c irq %d\n", - PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); -} - -static struct pci_controller sc520_cdp_hose = { - fixup_irq: pci_sc520_cdp_fixup_irq, -}; - -void pci_init_board(void) -{ - pci_sc520_init(&sc520_cdp_hose); -} - - -static void silence_uart(int port) -{ - outb(0, port+1); -} - -void setup_ali_sio(int uart_primary) -{ - ali512x_init(); - - ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0); - ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3); - ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4); - ali512x_set_uart(ALI_ENABLED, ALI_UART2, uart_primary?0x2f8:0x2e8, 3); - ali512x_set_rtc(ALI_DISABLED, 0, 0); - ali512x_set_kbc(ALI_ENABLED, 1, 12); - ali512x_set_cio(ALI_ENABLED); - - /* IrDa pins */ - ali512x_cio_function(12, 1, 0, 0); - ali512x_cio_function(13, 1, 0, 0); - - /* SSI chip select pins */ - ali512x_cio_function(14, 0, 0, 0); /* SSI_CS */ - ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */ - ali512x_cio_function(16, 0, 0, 0); /* SSI_SPI# */ - - /* Board REV pins */ - ali512x_cio_function(20, 0, 0, 1); - ali512x_cio_function(21, 0, 0, 1); - ali512x_cio_function(22, 0, 0, 1); - ali512x_cio_function(23, 0, 0, 1); -} - - -/* set up the ISA bus timing and system address mappings */ -static void bus_init(void) -{ - - /* set up the GP IO pins */ - write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */ - write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */ - write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */ - write_mmcr_byte(SC520_CLKSEL, 0x70); - - - write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */ - write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */ - write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */ - write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */ - write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */ - write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */ - write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */ - - write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */ - write_mmcr_word(SC520_ROMCS1CTL, 0x1823); /* set up timing of ROMCS1 */ - write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */ - - /* adjust the memory map: - * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM - * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio - * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ - - - /* SRAM = GPCS3 128k @ d0000-effff*/ - write_mmcr_long(SC520_PAR2, 0x4e00400d); - - /* IDE0 = GPCS6 1f0-1f7 */ - write_mmcr_long(SC520_PAR3, 0x380801f0); - - /* IDE1 = GPCS7 3f6 */ - write_mmcr_long(SC520_PAR4, 0x3c0003f6); - /* bootcs */ - write_mmcr_long(SC520_PAR12, 0x8bffe800); - /* romcs2 */ - write_mmcr_long(SC520_PAR13, 0xcbfff000); - /* romcs1 */ - write_mmcr_long(SC520_PAR14, 0xabfff800); - /* 680 LEDS */ - write_mmcr_long(SC520_PAR15, 0x30000640); - - write_mmcr_byte(SC520_ADDDECCTL, 0); - - asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ - - if (CFG_USE_SIO_UART) { - write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS); - setup_ali_sio(1); - } else { - write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS)); - setup_ali_sio(0); - silence_uart(0x3e8); - silence_uart(0x2e8); - } - -} - -/* GPCS usage - * GPCS0 PIO27 (NMI) - * GPCS1 ROMCS1 - * GPCS2 ROMCS2 - * GPCS3 SRAMCS PAR2 - * GPCS4 unused PAR3 - * GPCS5 unused PAR4 - * GPCS6 IDE - * GPCS7 IDE - */ - - -/* par usage: - * PAR0 legacy_video - * PAR1 PCI ROM mapping - * PAR2 SRAM - * PAR3 IDE - * PAR4 IDE - * PAR5 legacy_video - * PAR6 legacy_video - * PAR7 legacy_video - * PAR8 legacy_video - * PAR9 legacy_video - * PAR10 legacy_video - * PAR11 ISAROM - * PAR12 BOOTCS - * PAR13 ROMCS1 - * PAR14 ROMCS2 - * PAR15 Port 0x680 LED display - */ - -/* - * This function should map a chunk of size bytes - * of the system address space to the ISA bus - * - * The function will return the memory address - * as seen by the host (which may very will be the - * same as the bus address) - */ -u32 isa_map_rom(u32 bus_addr, int size) -{ - u32 par; - - PRINTF("isa_map_rom asked to map %d bytes at %x\n", - size, bus_addr); - - par = size; - if (par < 0x80000) { - par = 0x80000; - } - par >>= 12; - par--; - par&=0x7f; - par <<= 18; - par |= (bus_addr>>12); - par |= 0x50000000; - - PRINTF ("setting PAR11 to %x\n", par); - - /* Map rom 0x10000 with PAR1 */ - write_mmcr_long(SC520_PAR11, par); - - return bus_addr; -} - -/* - * this function removed any mapping created - * with pci_get_rom_window() - */ -void isa_unmap_rom(u32 addr) -{ - PRINTF("isa_unmap_rom asked to unmap %x", addr); - if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) { - write_mmcr_long(SC520_PAR11, 0); - PRINTF(" done\n"); - return; - } - PRINTF(" not ours\n"); -} - -#ifdef CONFIG_PCI -#define PCI_ROM_TEMP_SPACE 0x10000 -/* - * This function should map a chunk of size bytes - * of the system address space to the PCI bus, - * suitable to map PCI ROMS (bus address < 16M) - * the function will return the host memory address - * which should be converted into a bus address - * before used to configure the PCI rom address - * decoder - */ -u32 pci_get_rom_window(struct pci_controller *hose, int size) -{ - u32 par; - - par = size; - if (par < 0x80000) { - par = 0x80000; - } - par >>= 16; - par--; - par&=0x7ff; - par <<= 14; - par |= (PCI_ROM_TEMP_SPACE>>16); - par |= 0x72000000; - - PRINTF ("setting PAR1 to %x\n", par); - - /* Map rom 0x10000 with PAR1 */ - write_mmcr_long(SC520_PAR1, par); - - return PCI_ROM_TEMP_SPACE; -} - -/* - * this function removed any mapping created - * with pci_get_rom_window() - */ -void pci_remove_rom_window(struct pci_controller *hose, u32 addr) -{ - PRINTF("pci_remove_rom_window: %x", addr); - if (addr == PCI_ROM_TEMP_SPACE) { - write_mmcr_long(SC520_PAR1, 0); - PRINTF(" done\n"); - return; - } - PRINTF(" not ours\n"); - -} - -/* - * This function is called in order to provide acces to the - * legacy video I/O ports on the PCI bus. - * After this function accesses to I/O ports 0x3b0-0x3bb and - * 0x3c0-0x3df shuld result in transactions on the PCI bus. - * - */ -int pci_enable_legacy_video_ports(struct pci_controller *hose) -{ - /* Map video memory to 0xa0000*/ - write_mmcr_long(SC520_PAR0, 0x7200400a); - - /* forward all I/O accesses to PCI */ - write_mmcr_byte(SC520_ADDDECCTL, - read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); - - - /* so we map away all io ports to pci (only way to access pci io - * below 0x400. But then we have to map back the portions that we dont - * use so that the generate cycles on the GPIO bus where the sio and - * ISA slots are connected, this requre the use of several PAR registers - */ - - /* bring 0x100 - 0x1ef back to ISA using PAR5 */ - write_mmcr_long(SC520_PAR5, 0x30ef0100); - - /* IDE use 1f0-1f7 */ - - /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */ - write_mmcr_long(SC520_PAR6, 0x30ff01f8); - - /* com2 use 2f8-2ff */ - - /* bring 0x300 - 0x3af back to ISA using PAR7 */ - write_mmcr_long(SC520_PAR7, 0x30af0300); - - /* vga use 3b0-3bb */ - - /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ - write_mmcr_long(SC520_PAR8, 0x300303bc); - - /* vga use 3c0-3df */ - - /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */ - write_mmcr_long(SC520_PAR9, 0x301503e0); - - /* ide use 3f6 */ - - /* bring 0x3f7 back to ISA using PAR10 */ - write_mmcr_long(SC520_PAR10, 0x300003f7); - - /* com1 use 3f8-3ff */ - - return 0; -} -#endif - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - init_sc520(); - bus_init(); - irq_init(); - - /* max drive current on SDRAM */ - write_mmcr_word(SC520_DSCTL, 0x0100); - - /* enter debug mode after next reset (only if jumper is also set) */ - write_mmcr_byte(SC520_RESCFG, 0x08); - /* configure the software timer to 33.333MHz */ - write_mmcr_byte(SC520_SWTMRCFG, 0); - gd->bus_clk = 33333000; - - return 0; -} - -int dram_init(void) -{ - init_sc520_dram(); - return 0; -} - -void show_boot_progress(int val) -{ - outb(val&0xff, 0x80); - outb((val&0xff00)>>8, 0x680); -} - - -int last_stage_init(void) -{ - int minor; - int major; - - major = minor = 0; - major |= ali512x_cio_in(23)?2:0; - major |= ali512x_cio_in(22)?1:0; - minor |= ali512x_cio_in(21)?2:0; - minor |= ali512x_cio_in(20)?1:0; - - printf("AMD SC520 CDP revision %d.%d\n", major, minor); - - return 0; -} - - -void ssi_chip_select(int dev) -{ - - /* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */ - switch (dev) { - case 1: /* SPI EEPROM */ - ali512x_cio_out(16, 0); - break; - - case 2: /* MW EEPROM */ - ali512x_cio_out(15, 1); - break; - - case 3: /* AUX */ - ali512x_cio_out(14, 1); - break; - - case 0: - ali512x_cio_out(16, 1); - ali512x_cio_out(15, 0); - ali512x_cio_out(14, 0); - break; - - default: - printf("Illegal SSI device requested: %d\n", dev); - } -} - -void spi_eeprom_probe(int x) -{ -} - -int spi_eeprom_read(int x, int offset, char *buffer, int len) -{ - return 0; -} - -int spi_eeprom_write(int x, int offset, char *buffer, int len) -{ - return 0; -} - -void spi_init_f(void) -{ -#ifdef CONFIG_SC520_CDP_USE_SPI - spi_eeprom_probe(1); -#endif -#ifdef CONFIG_SC520_CDP_USE_MW - mw_eeprom_probe(2); -#endif -} - -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) -{ - int offset; - int i; - ssize_t res; - - offset = 0; - for (i=0;i. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* now setup the General purpose bus to give us access to the LEDs. - * We can then use the leds to display status information. - */ - -sc520_cdp_registers: -/* size offset value */ -.word 1 ; .word 0x040 ; .long 0x00 /* SDRAM buffer control */ -.word 2 ; .word 0xc08 ; .long 0x0001 /* GP CS offset */ -.word 2 ; .word 0xc09 ; .long 0x0003 /* GP CS width */ -.word 2 ; .word 0xc0a ; .long 0x0001 /* GP CS width */ -.word 2 ; .word 0xc0b ; .long 0x0003 /* GP RD pulse width */ -.word 2 ; .word 0xc0c ; .long 0x0001 /* GP RD offse */ -.word 2 ; .word 0xc0d ; .long 0x0003 /* GP WR pulse width */ -.word 2 ; .word 0xc0e ; .long 0x0001 /* GP WR offset */ -.word 2 ; .word 0xc2c ; .long 0x0000 /* GPIO directionreg */ -.word 2 ; .word 0xc2a ; .long 0x0000 /* GPIO directionreg */ -.word 2 ; .word 0xc22 ; .long 0xffff /* GPIO pin function 31-16 reg */ -.word 2 ; .word 0xc20 ; .long 0xffff /* GPIO pin function 15-0 reg */ -.word 2 ; .word 0x0c4 ; .long 0x28000680 /* PAR 15 for access to led 680 */ -.word 0 ; .word 0x000 ; .long 0x00 - -/* board early intialization */ -.globl early_board_init -early_board_init: - movl $sc520_cdp_registers,%esi -init_loop: - movl $0xfffef000,%edi /* MMCR base to edi */ - movw (%esi), %bx /* load sizer to bx */ - cmpw $0, %bx /* if sie is 0 we're done */ - je done - xorl %edx,%edx - movw 2(%esi), %dx /* load MMCR offset to dx */ - addl %edx, %edi /* add offset to base in edi */ - movl 4(%esi), %eax /* load value in eax */ - cmpw $1, %bx - je byte /* byte op? */ - cmpw $2, %bx - je word /* word op? */ - movl %eax, (%edi) /* must be long, then */ - jmp next -byte: movb %al,(%edi) - jmp next -word: movw %ax,(%edi) -next: addl $8, %esi /* advance esi */ - jmp init_loop - - /* the leds ad 0x80 and 0x680 should now work */ -done: movb $0x88, %al - out %al, $0x80 - movw $0x680, %dx - out %al, %dx - - jmp *%ebp /* return to caller */ - - -.globl __show_boot_progress -__show_boot_progress: - out %al, $0x80 - xchg %al, %ah - movw $0x680, %dx - out %al, %dx - jmp *%ebp diff --git a/board/sc520_cdp/sc520_cdp_asm16.S b/board/sc520_cdp/sc520_cdp_asm16.S deleted file mode 100644 index a3e700a..0000000 --- a/board/sc520_cdp/sc520_cdp_asm16.S +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * 16bit initialization code. - * This code have to map the area of the boot flash - * that is used by U-boot to its final destination. - */ - -.text -.section .start16, "ax" -.code16 -.globl board_init16 -board_init16: - /* Alias MMCR to 0xdf000 */ - movw $0xfffc, %dx - movl $0x800df0cb, %eax - outl %eax, %dx - - /* Set ds to point to MMCR alias */ - movw $0xdf00, %ax - movw %ax, %ds - - /* Map the entire flash at 0x38000000 - * (with BOOTCS and PAR14, use 0xabfff800 for ROMCS1) */ - movl $0xc0, %edi - movl $0x8bfff800, %eax - movl %eax, (%di) - - /* Disable SDRAM write buffer */ - movw $0x40,%di - xorw %ax,%ax - movb %al, (%di) - - /* Disabe MMCR alias */ - movw $0xfffc, %dx - movl $0x000000cb, %eax - outl %eax, %dx - - /* the return address is tored in bp */ - jmp *%bp - - -.section .bios, "ax" -.code16 -.globl realmode_reset -realmode_reset: - /* Alias MMCR to 0xdf000 */ - movw $0xfffc, %dx - movl $0x800df0cb, %eax - outl %eax, %dx - - /* Set ds to point to MMCR alias */ - movw $0xdf00, %ax - movw %ax, %ds - - /* issue software reset thorugh MMCR */ - movl $0xd72, %edi - movb $0x01, %al - movb %al, (%di) - -1: hlt - jmp 1 diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds deleted file mode 100644 index 72164a1..0000000 --- a/board/sc520_cdp/u-boot.lds +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") -OUTPUT_ARCH(i386) -ENTRY(_start) - -SECTIONS -{ - . = 0x387c0000; /* Where bootcode in the flash is mapped */ - .text : { *(.text); } - - . = ALIGN(4); - .rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) } - - . = 0x400000; /* Ram data segment to use */ - _i386boot_romdata_dest = ABSOLUTE(.); - .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } - _i386boot_romdata_start = LOADADDR(.data); - - . = ALIGN(4); - .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) } - _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got); - - - . = ALIGN(4); - _i386boot_bss_start = ABSOLUTE(.); - .bss : { *(.bss) } - _i386boot_bss_size = SIZEOF(.bss); - - - /* 16bit realmode trampoline code */ - .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) } - - _i386boot_realmode = LOADADDR(.realmode); - _i386boot_realmode_size = SIZEOF(.realmode); - - /* 16bit BIOS emulation code (just enough to boot Linux) */ - .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } - - _i386boot_bios = LOADADDR(.bios); - _i386boot_bios_size = SIZEOF(.bios); - - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - /* The load addresses below assumes that the flash - * will be mapped so that 0x387f0000 == 0xffff0000 - * at reset time - * - * The fe00 and ff00 offsets of the start32 and start16 - * segments are arbitrary, the just have to be mapped - * at reset and the code have to fit. - * The fff0 offset of reset is important, however. - */ - - - . = 0xfffffe00; - .start32 : AT (0x387ffe00) { *(.start32); } - - . = 0xff00; - .start16 : AT (0x387fff00) { *(.start16); } - - . = 0xfff0; - .reset : AT (0x387ffff0) { *(.reset); } - _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); -} diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile deleted file mode 100644 index 242d53c..0000000 --- a/board/sc520_spunk/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2002 -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := sc520_spunk.o flash.o -SOBJS := sc520_spunk_asm.o sc520_spunk_asm16.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/sc520_spunk/config.mk b/board/sc520_spunk/config.mk deleted file mode 100644 index 2253815..0000000 --- a/board/sc520_spunk/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2002 -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - - -TEXT_BASE = 0x387c0000 diff --git a/board/sc520_spunk/flash.c b/board/sc520_spunk/flash.c deleted file mode 100644 index 4942e59..0000000 --- a/board/sc520_spunk/flash.c +++ /dev/null @@ -1,809 +0,0 @@ -/* - * (C) Copyright 2002, 2003 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define PROBE_BUFFER_SIZE 1024 -static unsigned char buffer[PROBE_BUFFER_SIZE]; - - -#define SC520_MAX_FLASH_BANKS 1 -#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */ -#define SC520_FLASH_BANKSIZE 0x8000000 - -#define A29LV641DH_SIZE 0x800000 -#define A29LV641DH_SECTORS 128 - -#define A29LV641MH_SIZE 0x800000 -#define A29LV641MH_SECTORS 128 - -#define I28F320J3A_SIZE 0x400000 -#define I28F320J3A_SECTORS 32 - -#define I28F640J3A_SIZE 0x800000 -#define I28F640J3A_SECTORS 64 - -#define I28F128J3A_SIZE 0x1000000 -#define I28F128J3A_SECTORS 128 - -flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - - -static u32 _probe_flash(u32 addr, u32 bw, int il) -{ - u32 result=0; - - /* First do an unlock cycle for the benefit of - * devices that need it */ - - switch (bw) { - - case 1: - *(volatile u8*)(addr+0x5555) = 0xaa; - *(volatile u8*)(addr+0x2aaa) = 0x55; - *(volatile u8*)(addr+0x5555) = 0x90; - - /* Read vendor */ - result = *(volatile u8*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u8*)(addr+2); - - /* Return device to data mode */ - *(volatile u8*)addr = 0xff; - *(volatile u8*)(addr+0x5555), 0xf0; - break; - - case 2: - *(volatile u16*)(addr+0xaaaa) = 0xaaaa; - *(volatile u16*)(addr+0x5554) = 0x5555; - - /* Issue identification command */ - if (il == 2) { - *(volatile u16*)(addr+0xaaaa) = 0x9090; - - /* Read vendor */ - result = *(volatile u8*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u8*)(addr+2); - - /* Return device to data mode */ - *(volatile u16*)addr = 0xffff; - *(volatile u16*)(addr+0xaaaa), 0xf0f0; - - } else { - *(volatile u8*)(addr+0xaaaa) = 0x90; - /* Read vendor */ - result = *(volatile u16*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u16*)(addr+2); - - /* Return device to data mode */ - *(volatile u8*)addr = 0xff; - *(volatile u8*)(addr+0xaaaa), 0xf0; - } - - break; - - case 4: - *(volatile u32*)(addr+0x5554) = 0xaaaaaaaa; - *(volatile u32*)(addr+0xaaa8) = 0x55555555; - - switch (il) { - case 1: - /* Issue identification command */ - *(volatile u8*)(addr+0x5554) = 0x90; - - /* Read vendor */ - result = *(volatile u16*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u16*)(addr+4); - - /* Return device to data mode */ - *(volatile u8*)addr = 0xff; - *(volatile u8*)(addr+0x5554), 0xf0; - break; - - case 2: - /* Issue identification command */ - *(volatile u32*)(addr + 0x5554) = 0x00900090; - - /* Read vendor */ - result = *(volatile u16*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u16*)(addr+4); - - /* Return device to data mode */ - *(volatile u32*)addr = 0x00ff00ff; - *(volatile u32*)(addr+0x5554), 0x00f000f0; - break; - - case 4: - /* Issue identification command */ - *(volatile u32*)(addr+0x5554) = 0x90909090; - - /* Read vendor */ - result = *(volatile u8*)addr; - result <<= 16; - - /* Read device */ - result |= *(volatile u8*)(addr+4); - - /* Return device to data mode */ - *(volatile u32*)addr = 0xffffffff; - *(volatile u32*)(addr+0x5554), 0xf0f0f0f0; - break; - } - break; - } - - - return result; -} - -extern int _probe_flash_end; -asm ("_probe_flash_end:\n" - ".long 0\n"); - -static int identify_flash(unsigned address, int width) -{ - int is; - int device; - int vendor; - int size; - unsigned res; - - u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il); - - size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; - - if (size > PROBE_BUFFER_SIZE) { - printf("_probe_flash() routine too large (%d) %p - %p\n", - size, &_probe_flash_end, _probe_flash); - return 0; - } - - memcpy(buffer, _probe_flash, size); - _probe_flash_ptr = (void*)buffer; - - is = disable_interrupts(); - res = _probe_flash_ptr(address, width, 1); - if (is) { - enable_interrupts(); - } - - - vendor = res >> 16; - device = res & 0xffff; - - - return res; -} - -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { - unsigned id; - ulong flashbase = 0; - int sectsize = 0; - - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - switch (i) { - case 0: - flashbase = SC520_FLASH_BANK0_BASE; - break; - default: - panic("configured too many flash banks!\n"); - } - - id = identify_flash(flashbase, 2); - switch (id) { - case 0x000122d7: - /* 29LV641DH */ - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV640U & FLASH_TYPEMASK); - - flash_info[i].size = A29LV641DH_SIZE; - flash_info[i].sector_count = A29LV641DH_SECTORS; - sectsize = A29LV641DH_SIZE/A29LV641DH_SECTORS; - printf("Bank %d: AMD 29LV641DH\n", i); - break; - - case 0x0001227E: - /* 29LV641MH */ - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_DL640 & FLASH_TYPEMASK); - - flash_info[i].size = A29LV641MH_SIZE; - flash_info[i].sector_count = A29LV641MH_SECTORS; - sectsize = A29LV641MH_SIZE/A29LV641MH_SECTORS; - printf("Bank %d: AMD 29LV641MH\n", i); - break; - - case 0x00890016: - /* 28F320J3A */ - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F320J3A & FLASH_TYPEMASK); - - flash_info[i].size = I28F320J3A_SIZE; - flash_info[i].sector_count = I28F320J3A_SECTORS; - sectsize = I28F320J3A_SIZE/I28F320J3A_SECTORS; - printf("Bank %d: Intel 28F320J3A\n", i); - break; - - case 0x00890017: - /* 28F640J3A */ - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F640J3A & FLASH_TYPEMASK); - - flash_info[i].size = I28F640J3A_SIZE; - flash_info[i].sector_count = I28F640J3A_SECTORS; - sectsize = I28F640J3A_SIZE/I28F640J3A_SECTORS; - printf("Bank %d: Intel 28F640J3A\n", i); - break; - - case 0x00890018: - /* 28F128J3A */ - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3A & FLASH_TYPEMASK); - - flash_info[i].size = I28F128J3A_SIZE; - flash_info[i].sector_count = I28F128J3A_SECTORS; - sectsize = I28F128J3A_SIZE/I28F128J3A_SECTORS; - printf("Bank %d: Intel 28F128J3A\n", i); - break; - - default: - printf("Bank %d have unknown flash %08x\n", i, id); - flash_info[i].flash_id = FLASH_UNKNOWN; - continue; - } - - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j * sectsize; - } - size += flash_info[i].size; - - flash_protect(FLAG_PROTECT_CLEAR, - flash_info[i].start[0], - flash_info[i].start[0] + flash_info[i].size - 1, - &flash_info[i]); - } - - /* - * Protect monitor and environment sectors - */ - flash_protect(FLAG_PROTECT_SET, - i386boot_start, - i386boot_end, - &flash_info[0]); -#ifdef CFG_ENV_ADDR - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf("INTEL: "); - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F320J3A & FLASH_TYPEMASK): - printf("1x I28F320J3A (32Mbit)\n"); - break; - case (INTEL_ID_28F640J3A & FLASH_TYPEMASK): - printf("1x I28F640J3A (64Mbit)\n"); - break; - case (INTEL_ID_28F128J3A & FLASH_TYPEMASK): - printf("1x I28F128J3A (128Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - goto done; - break; - } - - break; - - case (AMD_MANUFACT & FLASH_VENDMASK): - printf("AMD: "); - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV640U & FLASH_TYPEMASK): - printf("1x AMD29LV641DH (64Mbit)\n"); - break; - case (AMD_ID_DL640 & FLASH_TYPEMASK): - printf("1x AMD29LV641MH (64Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - goto done; - break; - } - - break; - default: - printf("Unknown Vendor "); - break; - } - - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - done: -} - -/*----------------------------------------------------------------------- - */ - - -static u32 _amd_erase_flash(u32 addr, u32 sector) -{ - unsigned elapsed; - - /* Issue erase */ - *(volatile u16*)(addr + 0xaaaa) = 0x00AA; - *(volatile u16*)(addr + 0x5554) = 0x0055; - *(volatile u16*)(addr + 0xaaaa) = 0x0080; - /* And one unlock */ - *(volatile u16*)(addr + 0xaaaa) = 0x00AA; - *(volatile u16*)(addr + 0x5554) = 0x0055; - /* Sector erase command comes last */ - *(volatile u16*)(addr + sector) = 0x0030; - - elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ - elapsed = 0; - while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) { - - elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { - *(volatile u16*)(addr) = 0x00f0; - return 1; - } - } - - *(volatile u16*)(addr) = 0x00f0; - - return 0; -} - -extern int _amd_erase_flash_end; -asm ("_amd_erase_flash_end:\n" - ".long 0\n"); - -/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */ -#define __udelay(delay) \ -{ \ - unsigned micro; \ - unsigned milli=0; \ - \ - micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ - \ - for (;;) { \ - \ - milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ - micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \ - \ - if ((delay) <= (micro + (milli * 1000))) { \ - break; \ - } \ - } \ -} while (0) - -static u32 _intel_erase_flash(u32 addr, u32 sector) -{ - unsigned elapsed; - - *(volatile u16*)(addr + sector) = 0x0050; /* clear status register */ - *(volatile u16*)(addr + sector) = 0x0020; /* erase setup */ - *(volatile u16*)(addr + sector) = 0x00D0; /* erase confirm */ - - - /* Wait at least 80us - let's wait 1 ms */ - __udelay(1000); - - elapsed = 0; - while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) { - elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { - *(volatile u16*)(addr + sector) = 0x00B0; /* suspend erase */ - *(volatile u16*)(addr + sector) = 0x00FF; /* reset to read mode */ - return 1; - } - } - - *(volatile u16*)(addr + sector) = 0x00FF; /* reset to read mode */ - - return 0; -} - - -extern int _intel_erase_flash_end; -asm ("_intel_erase_flash_end:\n" - ".long 0\n"); - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - u32 (*_erase_flash_ptr)(u32 a, u32 so); - int prot; - int sect; - unsigned size; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { - size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; - - if (size > PROBE_BUFFER_SIZE) { - printf("_amd_erase_flash() routine too large (%d) %p - %p\n", - size, &_amd_erase_flash_end, _amd_erase_flash); - return 0; - } - - memcpy(buffer, _amd_erase_flash, size); - _erase_flash_ptr = (void*)buffer; - - } else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) { - size = (unsigned)&_intel_erase_flash_end - (unsigned)_intel_erase_flash; - - if (size > PROBE_BUFFER_SIZE) { - printf("_intel_erase_flash() routine too large (%d) %p - %p\n", - size, &_intel_erase_flash_end, _intel_erase_flash); - return 0; - } - - memcpy(buffer, _intel_erase_flash, size); - _erase_flash_ptr = (void*)buffer; - } else { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - - if (info->protect[sect] == 0) { /* not protected */ - int res; - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]); - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - - if (res) { - printf("Erase timed out, sector %d\n", sect); - return res; - } - - putc('.'); - } - } - - - return 0; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int _amd_write_word(unsigned start, unsigned dest, unsigned data) -{ - volatile u16 *addr2 = (u16*)start; - volatile u16 *dest2 = (u16*)dest; - volatile u16 *data2 = (u16*)&data; - int i; - unsigned elapsed; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile u16*)dest) & (u16)data) != (u16)data) { - return 2; - } - - for (i = 0; i < 2; i++) { - - - addr2[0x5555] = 0x00AA; - addr2[0x2aaa] = 0x0055; - addr2[0x5555] = 0x00A0; - - dest2[i] = (data >> (i*16)) & 0xffff; - - elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ - elapsed = 0; - - /* data polling for D7 */ - while ((dest2[i] & 0x0080) != (data2[i] & 0x0080)) { - elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { - addr2[i] = 0x00f0; - return 1; - } - } - } - - addr2[i] = 0x00f0; - - return 0; -} - -extern int _amd_write_word_end; -asm ("_amd_write_word_end:\n" - ".long 0\n"); - - -static int _intel_write_word(unsigned start, unsigned dest, unsigned data) -{ - int i; - unsigned elapsed; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile u16*)dest) & (u16)data) != (u16)data) { - return 2; - } - - for (i = 0; i < 2; i++) { - - *(volatile u16*)(dest+2*i) = 0x0040; /* write setup */ - *(volatile u16*)(dest+2*i) = (data >> (i*16)) & 0xffff; - - elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ - elapsed = 0; - - /* data polling for D7 */ - while ((*(volatile u16*)dest & 0x0080) != 0x0080) { - elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { - *(volatile u16*)dest = 0x00ff; - return 1; - } - } - } - - *(volatile u16*)dest = 0x00ff; - - - return 0; - -} - -extern int _intel_write_word_end; -asm ("_intel_write_word_end:\n" - ".long 0\n"); - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - Unsupported flash type - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - int flag; - u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data); - unsigned size; - - if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { - size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; - - if (size > PROBE_BUFFER_SIZE) { - printf("_amd_write_word() routine too large (%d) %p - %p\n", - size, &_amd_write_word_end, _amd_write_word); - return 0; - } - - memcpy(buffer, _amd_write_word, size); - _write_word_ptr = (void*)buffer; - - } else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) { - size = (unsigned)&_intel_write_word_end - (unsigned)_intel_write_word; - - if (size > PROBE_BUFFER_SIZE) { - printf("_intel_write_word() routine too large (%d) %p - %p\n", - size, &_intel_write_word_end, _intel_write_word); - return 0; - } - - memcpy(buffer, _intel_write_word, size); - _write_word_ptr = (void*)buffer; - } else { - printf ("Can't program unknown flash type - aborted\n"); - return 3; - } - - - wp = (addr & ~3); /* get lower word aligned address */ - - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data |= *src++ << (8*i); - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data |= (*(uchar *)cp) << (8*i); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - rc = _write_word_ptr(info->start[0], wp, data); - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - if (rc != 0) { - return rc; - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - - for (i=0; i<4; ++i) { - data |= *src++ << (8*i); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - rc = _write_word_ptr(info->start[0], wp, data); - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - if (rc != 0) { - return rc; - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return 0; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data |= *src++ << (8*i); - --cnt; - } - - for (; i<4; ++i, ++cp) { - data |= (*(uchar *)cp) << (8*i); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - rc = _write_word_ptr(info->start[0], wp, data); - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - return rc; - -} diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c deleted file mode 100644 index e7a7d51..0000000 --- a/board/sc520_spunk/sc520_spunk.c +++ /dev/null @@ -1,681 +0,0 @@ -/* - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* ------------------------------------------------------------------------- */ - - -/* - * Theory: - * We first set up all IRQs to be non-pci, edge triggered, - * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets - * called we reallocate irqs to the pci bus with sc520_pci_set_irq() - * as needed. Whe choose the irqs to gram from a configurable list - * inside pci_sc520_fixup_irq() (If this list contains stupid irq's - * such as 0 thngas will not work) - */ - -static void irq_init(void) -{ - /* disable global interrupt mode */ - write_mmcr_byte(SC520_PICICR, 0x40); - - /* set all irqs to edge */ - write_mmcr_byte(SC520_MPICMODE, 0x00); - write_mmcr_byte(SC520_SL1PICMODE, 0x00); - write_mmcr_byte(SC520_SL2PICMODE, 0x00); - - /* active low polarity on PIC interrupt pins, - * active high polarity on all other irq pins */ - write_mmcr_word(SC520_INTPINPOL, 0x0000); - - /* set irq number mapping */ - write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */ - write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */ - write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */ - write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ - write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */ - write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */ - write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */ - write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */ - write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */ - write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */ - write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ - write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6); /* Set Synchronius serial INT to IRQ6*/ - write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */ - write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */ - write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */ - write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ - write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ - - write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */ - write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */ - - write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7); /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */ - write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14); /* Set GPIRQ1 (CF IRQ) to IRQ14 */ - write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5); /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */ - write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disbale GIRQ4 ( IRR IRQ ) */ - write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ5 */ - write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ6 */ - write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ7 */ - write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ8 */ - write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ9 */ - write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ2 */ - write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED); /* disable GPIRQ10 */ - - write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */ - write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */ - -} - - -/* PCI stuff */ -static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - int version = read_mmcr_byte(SC520_SYSINFO); - - /* a configurable lists of irqs to steal - * when we need one (a board with more pci interrupt pins - * would use a larger table */ - static int irq_list[] = { - CFG_FIRST_PCI_IRQ, - CFG_SECOND_PCI_IRQ, - CFG_THIRD_PCI_IRQ, - CFG_FORTH_PCI_IRQ - }; - static int next_irq_index=0; - - char tmp_pin; - int pin; - - pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); - pin = tmp_pin; - - pin-=1; /* pci config space use 1-based numbering */ - if (-1 == pin) { - return; /* device use no irq */ - } - - - /* map device number + pin to a pin on the sc520 */ - switch (PCI_DEV(dev)) { - case 6: /* ETH0 */ - pin+=SC520_PCI_INTA; - break; - - case 7: /* ETH1 */ - pin+=SC520_PCI_INTB; - break; - - case 8: /* Crypto */ - pin+=SC520_PCI_INTC; - break; - - case 9: /* PMC slot */ - pin+=SC520_PCI_INTD; - break; - - case 10: /* PC-Card */ - - if (version < 10) { - pin+=SC520_PCI_INTD; - } else { - pin+=SC520_PCI_INTC; - } - break; - - default: - return; - } - - pin&=3; /* wrap around */ - - if (sc520_pci_ints[pin] == -1) { - /* re-route one interrupt for us */ - if (next_irq_index > 3) { - return; - } - if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { - return; - } - next_irq_index++; - } - - - if (-1 != sc520_pci_ints[pin]) { - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, - sc520_pci_ints[pin]); - } -#if 0 - printf("fixup_irq: device %d pin %c irq %d\n", - PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); -#endif -} - - -static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *te) -{ - u32 io_base; - u32 temp; - - pciauto_config_device(hose, dev); - - pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */ - pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */ - pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */ - pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */ - pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */ - pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */ - pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */ - - pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */ - pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */ - /* route MF0 to ~INT and MF3 to IRQ7 - * reserve all others */ - pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002); - pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */ - pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */ - - if (te->device != 0xac56) { - pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */ - pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */ - pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */ - pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */ - pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */ - } else { - pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */ - } - pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */ - - - pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base); - io_base &= ~0xfL; - - writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */ - writel(0, io_base+0x10); /* CLKRUN default */ - writel(0, io_base+0x20); /* CLKRUN default */ - -} - - -static struct pci_config_table pci_sc520_spunk_config_table[] = { - { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, - { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, - { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}} -}; - -static struct pci_controller sc520_spunk_hose = { - fixup_irq: pci_sc520_spunk_fixup_irq, - config_table: pci_sc520_spunk_config_table, - first_busno: 0x00, - last_busno: 0xff, -}; - -void pci_init_board(void) -{ - pci_sc520_init(&sc520_spunk_hose); -} - - -/* set up the ISA bus timing and system address mappings */ -static void bus_init(void) -{ - /* versions - * 0 Hyglo versions 0.95 and 0.96 (large baords) - * ?? Hyglo version 0.97 (small board) - * 10 Spunk board - */ - int version = read_mmcr_byte(SC520_SYSINFO); - - if (version) { - /* set up the GP IO pins (for the Spunk board) */ - write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); /* set the GPIO pin function 31-16 reg */ - write_mmcr_word(SC520_PIOPFS15_0, 0x000f); /* set the GPIO pin function 15-0 reg */ - write_mmcr_word(SC520_PIODIR31_16, 0x000f); /* set the GPIO direction 31-16 reg */ - write_mmcr_word(SC520_PIODIR15_0, 0x1ff0); /* set the GPIO direction 15-0 reg */ - write_mmcr_byte(SC520_CSPFS, 0xc0); /* set the CS pin function reg */ - write_mmcr_byte(SC520_CLKSEL, 0x70); - - write_mmcr_word(SC520_PIOCLR31_16, 0x0003); /* reset SSI chip-selects */ - write_mmcr_word(SC520_PIOSET31_16, 0x000c); - - } else { - /* set up the GP IO pins (for the Hyglo board) */ - write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); /* set the GPIO pin function 31-16 reg */ - write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f); /* set the GPIO pin function 15-0 reg */ - write_mmcr_word(SC520_PIODIR31_16, 0x003f); /* set the GPIO direction 31-16 reg */ - write_mmcr_word(SC520_PIODIR15_0, 0xe180); /* set the GPIO direction 15-0 reg */ - write_mmcr_byte(SC520_CSPFS, 0x00); /* set the CS pin function reg */ - write_mmcr_byte(SC520_CLKSEL, 0x70); - - write_mmcr_word(SC520_PIOCLR15_0, 0x0180); /* reset SSI chip-selects */ - } - - write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */ - write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */ - write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */ - write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */ - write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */ - write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */ - write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */ - - write_mmcr_word(SC520_BOOTCSCTL, 0x0407); /* set up timing of BOOTCS */ - - /* adjust the memory map: - * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM - * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio - * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ - - - /* bootcs */ - write_mmcr_long(SC520_PAR12, 0x8bffe800); - - /* IDE0 = GPCS6 1f0-1f7 */ - write_mmcr_long(SC520_PAR3, 0x380801f0); - - /* IDE1 = GPCS7 3f6 */ - write_mmcr_long(SC520_PAR4, 0x3c0003f6); - - asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ - - write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS)); - -} - - -/* par usage: - * PAR0 (legacy_video) - * PAR1 (PCI ROM mapping) - * PAR2 - * PAR3 IDE - * PAR4 IDE - * PAR5 (legacy_video) - * PAR6 - * PAR7 (legacy_video) - * PAR8 (legacy_video) - * PAR9 (legacy_video) - * PAR10 - * PAR11 (ISAROM) - * PAR12 BOOTCS - * PAR13 - * PAR14 - * PAR15 - */ - -/* - * This function should map a chunk of size bytes - * of the system address space to the ISA bus - * - * The function will return the memory address - * as seen by the host (which may very will be the - * same as the bus address) - */ -u32 isa_map_rom(u32 bus_addr, int size) -{ - u32 par; - - printf("isa_map_rom asked to map %d bytes at %x\n", - size, bus_addr); - - par = size; - if (par < 0x80000) { - par = 0x80000; - } - par >>= 12; - par--; - par&=0x7f; - par <<= 18; - par |= (bus_addr>>12); - par |= 0x50000000; - - printf ("setting PAR11 to %x\n", par); - - /* Map rom 0x10000 with PAR1 */ - write_mmcr_long(SC520_PAR11, par); - - return bus_addr; -} - -/* - * this function removed any mapping created - * with pci_get_rom_window() - */ -void isa_unmap_rom(u32 addr) -{ - printf("isa_unmap_rom asked to unmap %x", addr); - if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) { - write_mmcr_long(SC520_PAR11, 0); - printf(" done\n"); - return; - } - printf(" not ours\n"); -} - -#ifdef CONFIG_PCI -#define PCI_ROM_TEMP_SPACE 0x10000 -/* - * This function should map a chunk of size bytes - * of the system address space to the PCI bus, - * suitable to map PCI ROMS (bus address < 16M) - * the function will return the host memory address - * which should be converted into a bus address - * before used to configure the PCI rom address - * decoder - */ -u32 pci_get_rom_window(struct pci_controller *hose, int size) -{ - u32 par; - - par = size; - if (par < 0x80000) { - par = 0x80000; - } - par >>= 16; - par--; - par&=0x7ff; - par <<= 14; - par |= (PCI_ROM_TEMP_SPACE>>16); - par |= 0x72000000; - - printf ("setting PAR1 to %x\n", par); - - /* Map rom 0x10000 with PAR1 */ - write_mmcr_long(SC520_PAR1, par); - - return PCI_ROM_TEMP_SPACE; -} - -/* - * this function removed any mapping created - * with pci_get_rom_window() - */ -void pci_remove_rom_window(struct pci_controller *hose, u32 addr) -{ - printf("pci_remove_rom_window: %x", addr); - if (addr == PCI_ROM_TEMP_SPACE) { - write_mmcr_long(SC520_PAR1, 0); - printf(" done\n"); - return; - } - printf(" not ours\n"); - -} - -/* - * This function is called in order to provide acces to the - * legacy video I/O ports on the PCI bus. - * After this function accesses to I/O ports 0x3b0-0x3bb and - * 0x3c0-0x3df shuld result in transactions on the PCI bus. - * - */ -int pci_enable_legacy_video_ports(struct pci_controller *hose) -{ - /* Map video memory to 0xa0000*/ - write_mmcr_long(SC520_PAR0, 0x7200400a); - - /* forward all I/O accesses to PCI */ - write_mmcr_byte(SC520_ADDDECCTL, - read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); - - - /* so we map away all io ports to pci (only way to access pci io - * below 0x400. But then we have to map back the portions that we dont - * use so that the generate cycles on the GPIO bus where the sio and - * ISA slots are connected, this requre the use of several PAR registers - */ - - /* bring 0x100 - 0x2f7 back to ISA using PAR5 */ - write_mmcr_long(SC520_PAR5, 0x31f70100); - - /* com2 use 2f8-2ff */ - - /* bring 0x300 - 0x3af back to ISA using PAR7 */ - write_mmcr_long(SC520_PAR7, 0x30af0300); - - /* vga use 3b0-3bb */ - - /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ - write_mmcr_long(SC520_PAR8, 0x300303bc); - - /* vga use 3c0-3df */ - - /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */ - write_mmcr_long(SC520_PAR9, 0x301703e0); - - /* com1 use 3f8-3ff */ - - return 0; -} -#endif - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - init_sc520(); - bus_init(); - irq_init(); - - /* max drive current on SDRAM */ - write_mmcr_word(SC520_DSCTL, 0x0100); - - /* enter debug mode after next reset (only if jumper is also set) */ - write_mmcr_byte(SC520_RESCFG, 0x08); - /* configure the software timer to 33.000MHz */ - write_mmcr_byte(SC520_SWTMRCFG, 1); - gd->bus_clk = 33000000; - - return 0; -} - -int dram_init(void) -{ - init_sc520_dram(); - return 0; -} - -void show_boot_progress(int val) -{ - int version = read_mmcr_byte(SC520_SYSINFO); - - if (version == 0) { - /* PIO31-PIO16 Data */ - write_mmcr_word(SC520_PIODATA31_16, - (read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */ - - /* PIO0-PIO15 Data */ - write_mmcr_word(SC520_PIODATA15_0, - (read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13)); - } else { - /* newer boards use PIO4-PIO12 */ - /* PIO0-PIO15 Data */ -#if 0 - val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3); -#else - val = (val & 0x007) | ((val & 0x07e) << 2); -#endif - write_mmcr_word(SC520_PIODATA15_0, - (read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4)); - } -} - - -int last_stage_init(void) -{ - - int version = read_mmcr_byte(SC520_SYSINFO); - - printf("Omicron Ceti SC520 Spunk revision %x\n", version); - -#if 0 - if (version) { - int x, y; - - printf("eeprom probe %d\n", spi_eeprom_probe(1)); - - spi_eeprom_read(1, 0, (u8*)&x, 2); - spi_eeprom_read(1, 1, (u8*)&y, 2); - printf("eeprom bytes %04x%04x\n", x, y); - x ^= 0xffff; - y ^= 0xffff; - spi_eeprom_write(1, 0, (u8*)&x, 2); - spi_eeprom_write(1, 1, (u8*)&y, 2); - - spi_eeprom_read(1, 0, (u8*)&x, 2); - spi_eeprom_read(1, 1, (u8*)&y, 2); - printf("eeprom bytes %04x%04x\n", x, y); - - } else { - int x, y; - - printf("eeprom probe %d\n", mw_eeprom_probe(1)); - - mw_eeprom_read(1, 0, (u8*)&x, 2); - mw_eeprom_read(1, 1, (u8*)&y, 2); - printf("eeprom bytes %04x%04x\n", x, y); - - x ^= 0xffff; - y ^= 0xffff; - mw_eeprom_write(1, 0, (u8*)&x, 2); - mw_eeprom_write(1, 1, (u8*)&y, 2); - - mw_eeprom_read(1, 0, (u8*)&x, 2); - mw_eeprom_read(1, 1, (u8*)&y, 2); - printf("eeprom bytes %04x%04x\n", x, y); - - - } -#endif - - ds1722_probe(2); - - return 0; -} - -void ssi_chip_select(int dev) -{ - int version = read_mmcr_byte(SC520_SYSINFO); - - if (version) { - /* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */ - switch (dev) { - case 1: /* EEPROM */ - write_mmcr_word(SC520_PIOCLR31_16, 0x0004); - break; - - case 2: /* Temp Probe */ - write_mmcr_word(SC520_PIOSET31_16, 0x0002); - break; - - case 3: /* CAN */ - write_mmcr_word(SC520_PIOCLR31_16, 0x0008); - break; - - case 4: /* AUX */ - write_mmcr_word(SC520_PIOSET31_16, 0x0001); - break; - - case 0: - write_mmcr_word(SC520_PIOCLR31_16, 0x0003); - write_mmcr_word(SC520_PIOSET31_16, 0x000c); - break; - - default: - printf("Illegal SSI device requested: %d\n", dev); - } - } else { - - /* Globox board: Both EEPROM and TEMP are active-high */ - - switch (dev) { - case 1: /* EEPROM */ - write_mmcr_word(SC520_PIOSET15_0, 0x0100); - break; - - case 2: /* Temp Probe */ - write_mmcr_word(SC520_PIOSET15_0, 0x0080); - break; - - case 0: - write_mmcr_word(SC520_PIOCLR15_0, 0x0180); - break; - - default: - printf("Illegal SSI device requested: %d\n", dev); - } - } -} - - -void spi_init_f(void) -{ - read_mmcr_byte(SC520_SYSINFO) ? - spi_eeprom_probe(1) : - mw_eeprom_probe(1); - -} - -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) -{ - int offset; - int i; - - offset = 0; - for (i=0;i. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* now setup the General purpose bus to give us access to the LEDs. - * We can then use the leds to display status information. - */ - -sc520_cdp_registers: -/* size offset value */ -.word 1 ; .word 0x040 ; .long 0x00 /* SDRAM buffer control */ -.word 2 ; .word 0xc08 ; .long 0x0001 /* GP CS offset */ -.word 2 ; .word 0xc09 ; .long 0x0003 /* GP CS width */ -.word 2 ; .word 0xc0a ; .long 0x0001 /* GP CS width */ -.word 2 ; .word 0xc0b ; .long 0x0003 /* GP RD pulse width */ -.word 2 ; .word 0xc0c ; .long 0x0001 /* GP RD offse */ -.word 2 ; .word 0xc0d ; .long 0x0003 /* GP WR pulse width */ -.word 2 ; .word 0xc0e ; .long 0x0001 /* GP WR offset */ -.word 2 ; .word 0xc2c ; .long 0x003f /* GPIO directionreg 31-16 */ -.word 2 ; .word 0xc2a ; .long 0xe000 /* GPIO directionreg 15-0 */ -.word 2 ; .word 0xc22 ; .long 0xffc0 /* GPIO pin function 31-16 reg */ -.word 2 ; .word 0xc20 ; .long 0x1fff /* GPIO pin function 15-0 reg */ -.word 0 ; .word 0x000 ; .long 0x00 - -/* board early intialization */ -.globl early_board_init -early_board_init: - movl $sc520_cdp_registers,%esi -init_loop: - movl $0xfffef000,%edi /* MMCR base to edi */ - movw (%esi), %bx /* load size to bx */ - cmpw $0, %bx /* if size is 0 we're done */ - je done - xorl %edx,%edx - movw 2(%esi), %dx /* load MMCR offset to dx */ - addl %edx, %edi /* add offset to base in edi */ - movl 4(%esi), %eax /* load value in eax */ - cmpw $1, %bx - je byte /* byte op? */ - cmpw $2, %bx - je word /* word op? */ - movl %eax, (%edi) /* must be long, then */ - jmp next -byte: movb %al,(%edi) - jmp next -word: movw %ax,(%edi) -next: addl $8, %esi /* advance esi */ - jmp init_loop - - /* light all leds */ -done: movl $0xfffefc32,%edx - movw $0000,(%edx) - - jmp *%ebp /* return to caller */ - - -.globl __show_boot_progress -__show_boot_progress: - movl $0xfffefc32,%edx - xorw $0xffff, %ax - movw %ax,(%edx) - jmp *%ebp diff --git a/board/sc520_spunk/sc520_spunk_asm16.S b/board/sc520_spunk/sc520_spunk_asm16.S deleted file mode 100644 index 8bb1766..0000000 --- a/board/sc520_spunk/sc520_spunk_asm16.S +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * 16bit initialization code. - * This code have to map the area of the boot flash - * that is used by U-boot to its final destination. - */ - -.text -.section .start16, "ax" -.code16 -.globl board_init16 -board_init16: - /* Alias MMCR to 0xdf000 */ - movw $0xfffc, %dx - movl $0x800df0cb, %eax - outl %eax, %dx - - /* Set ds to point to MMCR alias */ - movw $0xdf00, %ax - movw %ax, %ds - - /* Map the entire flash at 0x38000000 - * (with BOOTCS and PAR14, use 0xabfff800 for ROMCS1) */ - movl $0xc0, %edi - movl $0x8bfff800, %eax - movl %eax, (%di) - - /* Disable SDRAM write buffer */ - movw $0x40,%di - xorw %ax,%ax - movb %al, (%di) - - /* Disabe MMCR alias */ - movw $0xfffc, %dx - movl $0x000000cb, %eax - outl %eax, %dx - - /* the return address is stored in bp */ - jmp *%bp - - -.section .bios, "ax" -.code16 -.globl realmode_reset -realmode_reset: - /* Alias MMCR to 0xdf000 */ - movw $0xfffc, %dx - movl $0x800df0cb, %eax - outl %eax, %dx - - /* Set ds to point to MMCR alias */ - movw $0xdf00, %ax - movw %ax, %ds - - /* issue software reset thorugh MMCR */ - movl $0xd72, %edi - movb $0x01, %al - movb %al, (%di) - -1: hlt - jmp 1 diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds deleted file mode 100644 index 127d707..0000000 --- a/board/sc520_spunk/u-boot.lds +++ /dev/null @@ -1,92 +0,0 @@ - -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") -OUTPUT_ARCH(i386) -ENTRY(_start) - -SECTIONS -{ - . = 0x387c0000; /* Where bootcode in the flash is mapped */ - .text : { *(.text); } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = 0x400000; /* Ram data segment to use */ - _i386boot_romdata_dest = ABSOLUTE(.); - .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } - _i386boot_romdata_start = LOADADDR(.data); - - . = ALIGN(4); - .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) } - _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got); - - - . = ALIGN(4); - _i386boot_bss_start = ABSOLUTE(.); - .bss : { *(.bss) } - _i386boot_bss_size = SIZEOF(.bss); - - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - /* 16bit realmode trampoline code */ - .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) } - - _i386boot_realmode = LOADADDR(.realmode); - _i386boot_realmode_size = SIZEOF(.realmode); - - /* 16bit BIOS emulation code (just enough to boot Linux) */ - .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } - - _i386boot_bios = LOADADDR(.bios); - _i386boot_bios_size = SIZEOF(.bios); - - - /* The load addresses below assumes that the flash - * will be mapped so that 0x387f0000 == 0xffff0000 - * at reset time - * - * The fe00 and ff00 offsets of the start32 and start16 - * segments are arbitrary, the just have to be mapped - * at reset and the code have to fit. - * The fff0 offset of reset is important, however. - */ - - - . = 0xfffffe00; - .start32 : AT (0x387ffe00) { *(.start32); } - - . = 0xff00; - .start16 : AT (0x387fff00) { *(.start16); } - - . = 0xfff0; - .reset : AT (0x387ffff0) { *(.reset); } - _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); -} diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile deleted file mode 100644 index 5dc3fd4..0000000 --- a/board/scb9328/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := scb9328.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/scb9328/config.mk b/board/scb9328/config.mk deleted file mode 100644 index 8d1d79a..0000000 --- a/board/scb9328/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# This config file is used for compilation of scb93328 sources -# -# You might change location of U-Boot in memory by setting right TEXT_BASE. -# This allows for example having one copy located at the end of ram and stored -# in flash device and later on while developing use other location to test -# the code in RAM device only. -# - -TEXT_BASE = 0x08f00000 diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c deleted file mode 100644 index 1b56f8c..0000000 --- a/board/scb9328/flash.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (C) 2003 ETC s.r.o. - * - * This code was inspired by Marius Groeger and Kyle Harris code - * available in other board ports for U-Boot - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Written by Peter Figuli , 2003. - * - */ - -#include -#include "intel.h" - - -/* - * This code should handle CFI FLASH memory device. This code is very - * minimalistic approach without many essential error handling code as well. - * Because U-Boot actually is missing smart handling of FLASH device, - * we just set flash_id to anything else to FLASH_UNKNOW, so common code - * can call us without any restrictions. - * TODO: Add CFI Query, to be able to determine FLASH device. - * TODO: Add error handling code - * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but - * hopefully may work with other configurations. - */ - -#if ( SCB9328_FLASH_BUS_WIDTH == 1 ) -# define FLASH_BUS vu_char -# if ( SCB9328_FLASH_INTERLEAVE == 1 ) -# define FLASH_CMD( x ) x -# else -# error "With 8bit bus only one chip is allowed" -# endif - - -#elif ( SCB9328_FLASH_BUS_WIDTH == 2 ) -# define FLASH_BUS vu_short -# if ( SCB9328_FLASH_INTERLEAVE == 1 ) -# define FLASH_CMD( x ) x -# elif ( SCB9328_FLASH_INTERLEAVE == 2 ) -# define FLASH_CMD( x ) (( x << 8 )| x ) -# else -# error "With 16bit bus only 1 or 2 chip(s) are allowed" -# endif - - -#elif ( SCB9328_FLASH_BUS_WIDTH == 4 ) -# define FLASH_BUS vu_long -# if ( SCB9328_FLASH_INTERLEAVE == 1 ) -# define FLASH_CMD( x ) x -# elif ( SCB9328_FLASH_INTERLEAVE == 2 ) -# define FLASH_CMD( x ) (( x << 16 )| x ) -# elif ( SCB9328_FLASH_INTERLEAVE == 4 ) -# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x ) -# else -# error "With 32bit bus only 1,2 or 4 chip(s) are allowed" -# endif - -#else -# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration" -#endif - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -static FLASH_BUS flash_status_reg (void) -{ - - FLASH_BUS *addr = (FLASH_BUS *) 0; - - *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); - - return *addr; -} - -static int flash_ready (ulong timeout) -{ - int ok = 1; - - reset_timer_masked (); - while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != - FLASH_CMD (CFI_INTEL_SR_READY)) { - if (get_timer_masked () > timeout && timeout != 0) { - ok = 0; - break; - } - } - return ok; -} - -#if ( CFG_MAX_FLASH_BANKS != 1 ) -# error "SCB9328 platform has only one flash bank!" -#endif - - -ulong flash_init (void) -{ - int i; - unsigned long address = SCB9328_FLASH_BASE; - - flash_info[0].size = SCB9328_FLASH_BANK_SIZE; - flash_info[0].sector_count = CFG_MAX_FLASH_SECT; - flash_info[0].flash_id = INTEL_MANUFACT; - memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); - - for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { - flash_info[0].start[i] = address; -#ifdef SCB9328_FLASH_UNLOCK - /* Some devices are hw locked after start. */ - *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP); - *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK); - flash_ready (0); - *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); -#endif - address += SCB9328_FLASH_SECT_SIZE; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return SCB9328_FLASH_BANK_SIZE; -} - -void flash_print_info (flash_info_t * info) -{ - int i; - - printf (" Intel vendor\n"); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if (!(i % 5)) { - printf ("\n"); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, non_protected = 0, sector; - int rc = ERR_OK; - - FLASH_BUS *address; - - for (sector = s_first; sector <= s_last; sector++) { - if (!info->protect[sector]) { - non_protected++; - } - } - - if (!non_protected) { - return ERR_PROTECTED; - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - - /* Start erase on unprotected sectors */ - for (sector = s_first; sector <= s_last && !ctrlc (); sector++) { - if (info->protect[sector]) { - printf ("Protected sector %2d skipping...\n", sector); - continue; - } else { - printf ("Erasing sector %2d ... ", sector); - } - - address = (FLASH_BUS *) (info->start[sector]); - - *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); - *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); - if (flash_ready (CFG_FLASH_ERASE_TOUT)) { - *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); - printf ("ok.\n"); - } else { - *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); - rc = ERR_TIMOUT; - printf ("timeout! Aborting...\n"); - break; - } - *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); - } - if (ctrlc ()) - printf ("User Interrupt!\n"); - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - if (flag) { - enable_interrupts (); - } - - return rc; -} - -static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) -{ - FLASH_BUS *address = (FLASH_BUS *) dest; - int rc = ERR_OK; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*address & data) != data) { - return ERR_NOT_ERASED; - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - flag = disable_interrupts (); - - *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); - *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); - *address = data; - - if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { - *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); - rc = ERR_TIMOUT; - printf ("timeout! Aborting...\n"); - } - - *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); - if (flag) { - enable_interrupts (); - } - - return rc; -} - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong read_addr, write_addr; - FLASH_BUS data; - int i, result = ERR_OK; - - - read_addr = addr & ~(sizeof (FLASH_BUS) - 1); - write_addr = read_addr; - if (read_addr != addr) { - data = 0; - for (i = 0; i < sizeof (FLASH_BUS); i++) { - if (read_addr < addr || cnt == 0) { - data |= *((uchar *) read_addr) << i * 8; - } else { - data |= (*src++) << i * 8; - cnt--; - } - read_addr++; - } - if ((result = write_data (info, write_addr, data)) != ERR_OK) { - return result; - } - write_addr += sizeof (FLASH_BUS); - } - for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) { - if ((result = write_data (info, write_addr, - *((FLASH_BUS *) src))) != ERR_OK) { - return result; - } - write_addr += sizeof (FLASH_BUS); - src += sizeof (FLASH_BUS); - } - if (cnt > 0) { - read_addr = write_addr; - data = 0; - for (i = 0; i < sizeof (FLASH_BUS); i++) { - if (cnt > 0) { - data |= (*src++) << i * 8; - cnt--; - } else { - data |= *((uchar *) read_addr) << i * 8; - } - read_addr++; - } - if ((result = write_data (info, write_addr, data)) != 0) { - return result; - } - } - return ERR_OK; -} diff --git a/board/scb9328/intel.h b/board/scb9328/intel.h deleted file mode 100644 index 77498b6..0000000 --- a/board/scb9328/intel.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2002 ETC s.r.o. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the ETC s.r.o. nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Written by Marcel Telka , 2002. - * - * Documentation: - * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, - * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 - * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, - * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 - * - * This file is taken from OpenWinCE project hosted by SourceForge.net - * - */ - -#ifndef FLASH_INTEL_H -#define FLASH_INTEL_H - -#include - -/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ - -#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ - -/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ - -#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ - -/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ - -#define CFI_CHIP_INTEL_28F320J3A 0x0016 -#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" -#define CFI_CHIP_INTEL_28F640J3A 0x0017 -#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" -#define CFI_CHIP_INTEL_28F128J3A 0x0018 -#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" - -/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ - -#define CFI_CHIP_INTEL_28F640K3 0x8801 -#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" -#define CFI_CHIP_INTEL_28F128K3 0x8802 -#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" -#define CFI_CHIP_INTEL_28F256K3 0x8803 -#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" -#define CFI_CHIP_INTEL_28F640K18 0x8805 -#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" -#define CFI_CHIP_INTEL_28F128K18 0x8806 -#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" -#define CFI_CHIP_INTEL_28F256K18 0x8807 -#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" - -#endif /* FLASH_INTEL_H */ diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S deleted file mode 100644 index ba3b6d2..0000000 --- a/board/scb9328/lowlevel_init.S +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - * 02111-1307, USA. - * - */ - -#include -#include -#include - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - -/* Change PERCLK1DIV to 14 ie 14+1 */ - ldr r0, =PCDR - ldr r1, =CFG_PCDR_VAL - str r1, [r0] - -/* set MCU PLL Control Register 0 */ - - ldr r0, =MPCTL0 - ldr r1, =CFG_MPCTL0_VAL - str r1, [r0] - -/* set mpll restart bit */ - ldr r0, =CSCR - ldr r1, [r0] - orr r1,r1,#(1<<21) - str r1, [r0] - - mov r2,#0x10 -1: - mov r3,#0x2000 -2: - subs r3,r3,#1 - bne 2b - - subs r2,r2,#1 - bne 1b - -/* set System PLL Control Register 0 */ - - ldr r0, =SPCTL0 - ldr r1, =CFG_SPCTL0_VAL - str r1, [r0] - -/* set spll restart bit */ - ldr r0, =CSCR - ldr r1, [r0] - orr r1,r1,#(1<<22) - str r1, [r0] - - mov r2,#0x10 -1: - mov r3,#0x2000 -2: - subs r3,r3,#1 - bne 2b - - subs r2,r2,#1 - bne 1b - - ldr r0, =CSCR - ldr r1, =CFG_CSCR_VAL - str r1, [r0] - -/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon - *this..... - * - * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15 - * register 1, this stops it using the output of the PLL and thus runs at the - * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never - * use the value set in the CM_OSC registers...regardless of what you set it - * too! Thus, although i thought i was running at 140MHz, i'm actually running - * at 40!.. - - * Slapping this into my bootloader does the trick... - - * MRC p15,0,r0,c1,c0,0 ; read core configuration register - * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode - * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration - * register - */ - MRC p15,0,r0,c1,c0,0 - ORR r0,r0,#0xC0000000 - MCR p15,0,r0,c1,c0,0 - - ldr r0, =GPR(0) - ldr r1, =CFG_GPR_A_VAL - str r1, [r0] - - ldr r0, =GIUS(0) - ldr r1, =CFG_GIUS_A_VAL - str r1, [r0] - -/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ - - ldr r0, =FMCR - ldr r1, =CFG_FMCR_VAL - str r1, [r0] - - ldr r0, =CS0U - ldr r1, =CFG_CS0U_VAL - str r1, [r0] - - ldr r0, =CS0L - ldr r1, =CFG_CS0L_VAL - str r1, [r0] - - ldr r0, =CS1U - ldr r1, =CFG_CS1U_VAL - str r1, [r0] - - ldr r0, =CS1L - ldr r1, =CFG_CS1L_VAL - str r1, [r0] - - ldr r0, =CS2U - ldr r1, =CFG_CS2U_VAL - str r1, [r0] - - ldr r0, =CS2L - ldr r1, =CFG_CS2L_VAL - str r1, [r0] - - ldr r0, =CS3U - ldr r1, =CFG_CS3U_VAL - str r1, [r0] - - ldr r0, =CS3L - ldr r1, =CFG_CS3L_VAL - str r1, [r0] - - ldr r0, =CS4U - ldr r1, =CFG_CS4U_VAL - str r1, [r0] - - ldr r0, =CS4L - ldr r1, =CFG_CS4L_VAL - str r1, [r0] - - ldr r0, =CS5U - ldr r1, =CFG_CS5U_VAL - str r1, [r0] - - ldr r0, =CS5L - ldr r1, =CFG_CS5L_VAL - str r1, [r0] - -/* SDRAM Setup */ - - ldr r0, =SDCTL0 - ldr r1, =PRECHARGE_CMD - str r1, [r0] - - ldr r0, =0x08200000 - ldr r1, =0x0 /* Issue Precharge all Command */ - str r1, [r0] - - ldr r0, =SDCTL0 - ldr r1, =AUTOREFRESH_CMD - str r1, [r0] - - ldr r0, =0x08000000 - ldr r1, =0x0 /* Issue AutoRefresh Command */ - str r1, [r0] - str r1, [r0] - str r1, [r0] - str r1, [r0] - str r1, [r0] - str r1, [r0] - str r1, [r0] - str r1, [r0] - - ldr r0, =SDCTL0 - ldr r1, =0xb10a8300 - str r1, [r0] - - ldr r0, =0x08223000 /* CAS Latency 2 */ - ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */ - str r1, [r0] - - ldr r0, =SDCTL0 - ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */ - str r1, [r0] - - mov pc,r10 diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c deleted file mode 100644 index 3ed8753..0000000 --- a/board/scb9328/scb9328.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -int board_init( void ){ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_arch_number = MACH_TYPE_SCB9328; - gd->bd->bi_boot_params = 0x08000100; - - return 0; -} - -int dram_init( void ){ - DECLARE_GLOBAL_DATA_PTR; - -#if ( CONFIG_NR_DRAM_BANKS > 0 ) - gd->bd->bi_dram[0].start = SCB9328_SDRAM_1; - gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 1 ) - gd->bd->bi_dram[1].start = SCB9328_SDRAM_2; - gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 2 ) - gd->bd->bi_dram[2].start = SCB9328_SDRAM_3; - gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 3 ) - gd->bd->bi_dram[3].start = SCB9328_SDRAM_4; - gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE; -#endif - - return 0; -} - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - * The CSB226 does only have 3 LEDs, so we switch them on at the most - * important states (1, 5, 15). - */ - -void show_boot_progress (int status) -{ - return; -} diff --git a/board/scb9328/u-boot.lds b/board/scb9328/u-boot.lds deleted file mode 100644 index 1d1669c..0000000 --- a/board/scb9328/u-boot.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/shannon/Makefile b/board/shannon/Makefile deleted file mode 100644 index f66b096..0000000 --- a/board/shannon/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := shannon.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/shannon/config.mk b/board/shannon/config.mk deleted file mode 100644 index ca45733..0000000 --- a/board/shannon/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -# -# LART board with SA1100 cpu -# -# see http://www.lart.tudelft.nl/ for more information on LART -# - -# -# Tuxscreen has 4 banks of 4 MB DRAM each -# -# c000'0000 -# c800'0000 -# d000'0000 -# d800'0000 -# -# Linux-Kernel is expected to be at c000'8000, entry c000'8000 -# -# we load ourself to d838'0000, the upper 1 MB of the last (4th) bank -# -# download areas is c800'0000 -# - - -TEXT_BASE = 0xd8380000 diff --git a/board/shannon/flash.c b/board/shannon/flash.c deleted file mode 100644 index 13c01d8..0000000 --- a/board/shannon/flash.c +++ /dev/null @@ -1,473 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -ulong myflush(void); - - -#define FLASH_BANK_SIZE 0x400000 /* 4 MB */ -#define MAIN_SECT_SIZE 0x20000 /* 128 KB */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x00F000F0 -#define CMD_UNLOCK1 0x00AA00AA -#define CMD_UNLOCK2 0x00550055 -#define CMD_ERASE_SETUP 0x00800080 -#define CMD_ERASE_CONFIRM 0x00300030 -#define CMD_PROGRAM 0x00A000A0 -#define CMD_UNLOCK_BYPASS 0x00200020 - -#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2))) -#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2))) - -#define BIT_ERASE_DONE 0x00800080 -#define BIT_RDY_MASK 0x00800080 -#define BIT_PROGRAM_ERROR 0x00200020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) - { - ulong flashbase = 0; - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV160B & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) - { - - if (j <= 3) - { - /* 1st one is 32 KB */ - if (j == 0) - { - flash_info[i].start[j] = flashbase + 0; - } - - /* 2nd and 3rd are both 16 KB */ - if ((j == 1) || (j == 2)) - { - flash_info[i].start[j] = flashbase + 0x8000 + (j-1)*0x4000; - } - - /* 4th 64 KB */ - if (j == 3) - { - flash_info[i].start[j] = flashbase + 0x10000; - } - } - else - { - flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - /* - * Protect monitor and environment sectors - * Inferno is complicated, it's hardware locked - */ -#ifdef CONFIG_INFERNO - /* first one, 0x00000 to 0x07fff */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE + 0x00000, - CFG_FLASH_BASE + 0x08000 - 1, - &flash_info[0]); - - /* third to 10th, 0x0c000 - 0xdffff */ - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE + 0x0c000, - CFG_FLASH_BASE + 0xe0000 - 1, - &flash_info[0]); -#else - flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); -#endif - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) - { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf("AMD: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) - { - case (AMD_ID_LV160B & FLASH_TYPEMASK): - printf("2x Amd29F160BB (16Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - goto Done; - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) - { - if ((i % 5) == 0) - { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: - ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1, chip2; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status(); - icache_disable(); - iflag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) - { - printf("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - if (info->protect[sect] == 0) - { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = chip2 = 0; - - do - { - result = *addr; - - /* check timeout */ - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) - { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip1 = ERR; - - if (!chip2 && (result >> 16) & BIT_ERASE_DONE) - chip2 = READY; - - if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) - chip2 = ERR; - - } while (!chip1 || !chip2); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR || chip2 == ERR) - { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) - { - rc = ERR_TIMOUT; - goto outahere; - } - - printf("ok.\n"); - } - else /* it was protected */ - { - printf("protected!\n"); - } - } - - if (ctrlc()) - printf("User Interrupt!\n"); - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked(10000); - - if (iflag) - enable_interrupts(); - - if (cflag) - icache_enable(); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -volatile static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1, chip2; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status(); - icache_disable(); - iflag = disable_interrupts(); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - /* wait until flash is ready */ - chip1 = chip2 = 0; - do - { - result = *addr; - - /* check timeout */ - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) - { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) - { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip1 = READY; - else - chip1 = ERR; - } - - if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) - chip2 = READY; - - if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) - { - result = *addr; - - if ((result & (0x80 << 16)) == (data & (0x80 << 16))) - chip2 = READY; - else - chip2 = ERR; - } - - } while (!chip1 || !chip2); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || chip2 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts(); - - if (cflag) - icache_enable(); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 24); - } - for (; i<4 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((vu_long*)src); - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - return write_word(info, wp, data); -} diff --git a/board/shannon/inferno.header b/board/shannon/inferno.header deleted file mode 100644 index 28ee85a..0000000 Binary files a/board/shannon/inferno.header and /dev/null differ diff --git a/board/shannon/lowlevel_init.S b/board/shannon/lowlevel_init.S deleted file mode 100644 index 0655c42..0000000 --- a/board/shannon/lowlevel_init.S +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* some parameters for the board */ - -MEM_BASE: .long 0xa0000000 -MEM_START: .long 0xc0000000 - -#define MDCNFG 0x00 -#define MDCAS0 0x04 -#define MDCAS1 0x08 -#define MDCAS2 0x0c -#define MSC0 0x10 -#define MSC1 0x14 -#define MECR 0x18 - -mdcas0: .long 0xc71c703f @ cccccccf -mdcas1: .long 0xffc71c71 @ fffffffc -mdcas2: .long 0xffffffff @ ffffffff -mdcnfg: .long 0x0334b21f @ 9326991f -msc0: .long 0xfff84458 @ 42304230 -msc1: .long 0xffffffff @ 20182018 -mecr: .long 0x7fff7fff @ 01000000 - -/* setting up the memory */ - -.globl lowlevel_init -lowlevel_init: - ldr r0, MEM_BASE - - /* Setup the flash memory */ - ldr r1, msc0 - str r1, [r0, #MSC0] - - /* Set up the DRAM */ - - /* MDCAS0 */ - ldr r1, mdcas0 - str r1, [r0, #MDCAS0] - - /* MDCAS1 */ - ldr r1, mdcas1 - str r1, [r0, #MDCAS1] - - /* MDCAS2 */ - ldr r1, mdcas2 - str r1, [r0, #MDCAS2] - - /* MDCNFG */ - ldr r1, mdcnfg - str r1, [r0, #MDCNFG] - - /* Set up PCMCIA space */ - ldr r1, mecr - str r1, [r0, #MECR] - - /* Load something to activate bank */ - ldr r1, MEM_START - -.rept 8 - ldr r0, [r1] -.endr - - /* everything is fine now */ - mov pc, lr diff --git a/board/shannon/shannon.c b/board/shannon/shannon.c deleted file mode 100644 index 0d9f146..0000000 --- a/board/shannon/shannon.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* but if we use InfernoLoader, we must do some inits here */ - -#ifdef CONFIG_INFERNO - { - unsigned long temp; - __asm__ __volatile__(/* disable MMU, enable icache */ - "mrc p15, 0, %0, c1, c0\n" - "bic %0, %0, #0x00002000\n" - "bic %0, %0, #0x0000000f\n" - "orr %0, %0, #0x00001000\n" - "orr %0, %0, #0x00000002\n" - "mcr p15, 0, %0, c1, c0\n" - /* flush caches */ - "mov %0, #0\n" - "mcr p15, 0, %0, c7, c7, 0\n" - "mcr p15, 0, %0, c8, c7, 0\n" - : "=r" (temp) - : - : "memory"); - /* setup PCMCIA timing */ - temp = 0xa0000018; - *(unsigned long *)temp = 0x00060006; - - } -#endif /* CONFIG_INFERNO */ - - /* arch number for shannon */ - gd->bd->bi_arch_number = MACH_TYPE_SHANNON; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xc0000100; - - return 0; -} - -int dram_init (void) -{ -#if defined(PHYS_SDRAM_1) || defined(PHYS_SDRAM_2) || \ - defined(PHYS_SDRAM_3) || defined(PHYS_SDRAM_4) - DECLARE_GLOBAL_DATA_PTR; - bd_t *bd = gd->bd; -#endif - -#ifdef PHYS_SDRAM_1 - bd->bi_dram[0].start = PHYS_SDRAM_1; - bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -#endif - -#ifdef PHYS_SDRAM_2 - bd->bi_dram[1].start = PHYS_SDRAM_2; - bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -#endif - -#ifdef PHYS_SDRAM_3 - bd->bi_dram[2].start = PHYS_SDRAM_3; - bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; -#endif - -#ifdef PHYS_SDRAM_4 - bd->bi_dram[3].start = PHYS_SDRAM_4; - bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -#endif - - return (0); -} diff --git a/board/shannon/u-boot.lds b/board/shannon/u-boot.lds deleted file mode 100644 index 258bece..0000000 --- a/board/shannon/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/sa1100/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/siemens/CCM/Makefile b/board/siemens/CCM/Makefile deleted file mode 100644 index ee2fc53..0000000 --- a/board/siemens/CCM/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \ - ../../tqm8xx/load_sernum_ethaddr.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c deleted file mode 100644 index 5a32e45..0000000 --- a/board/siemens/CCM/ccm.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -void can_driver_enable (void); -void can_driver_disable (void); - -int fpga_init(void); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, - 0x1FF5FC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Always return 1 (no second DRAM bank since based on TQM8xxL module) - */ - -int checkboard (void) -{ - unsigned char *s; - unsigned char buf[64]; - - s = (getenv_r ("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL; - - puts ("Board: Siemens CCM"); - - if (s) { - puts (" ("); - - for (; *s; ++s) { - if (*s == ' ') - break; - putc (*s); - } - putc (')'); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * If Power-On-Reset switch off the Red and Green LED: At reset, the - * data direction registers are cleared and must therefore be restored. - */ -#define RSR_CSRS 0x08000000 - -int power_on_reset(void) -{ - /* Test Reset Status Register */ - return ((volatile immap_t *)CFG_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1; -} - -#define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */ -#define PB_LED_RED 0x20000 /* red LED is on PB.14 */ -#define PB_LEDS (PB_LED_GREEN | PB_LED_RED); - -static void init_leds (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - - immap->im_cpm.cp_pbpar &= ~PB_LEDS; - immap->im_cpm.cp_pbodr &= ~PB_LEDS; - immap->im_cpm.cp_pbdir |= PB_LEDS; - /* Check stop reset status */ - if (power_on_reset()) { - immap->im_cpm.cp_pbdat &= ~PB_LEDS; - } -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size = 0; - unsigned long reg; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; - - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay(500); -/* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type - * For types > 128 MBit leave it at the current (fast) rate - */ - if (size < 0x02000000) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - udelay(1000); - } - - /* - * Final mapping - */ - - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - can_driver_enable (); - init_leds (); - - udelay(10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Warning - both the PUMA load mode and the CAN driver use UPM B, - * so make sure only one of both is active. - */ -void can_driver_enable (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Initialize MBMR */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; - memctl->memc_mcr = 0x0100 | UPMB; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMB; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMB; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMB; - - memctl->memc_mdr = 0xFFFFDC05; - memctl->memc_mcr = 0x0104 | UPMB; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x0118 | UPMB; - - memctl->memc_mdr = 0xCFFCD004; - memctl->memc_mcr = 0x0119 | UPMB; - - memctl->memc_mdr = 0x0FFCC000; - memctl->memc_mcr = 0x011A | UPMB; - - memctl->memc_mdr = 0x7FFCC004; - memctl->memc_mcr = 0x011B | UPMB; - - memctl->memc_mdr = 0xFFFDCC05; - memctl->memc_mcr = 0x011C | UPMB; - - /* Initialize OR3 / BR3 for CAN Bus Controller */ - memctl->memc_or3 = CFG_OR3_CAN; - memctl->memc_br3 = CFG_BR3_CAN; -} - -void can_driver_disable (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Reset OR3 / BR3 to disable CAN Bus Controller */ - memctl->memc_br3 = 0; - memctl->memc_or3 = 0; - - memctl->memc_mbmr = 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) - -#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN) - -void reset_phy(void) -{ - immap_t *immr = (immap_t *)CFG_IMMR; - ulong value; - - /* Configure all needed port pins for GPIO */ -#ifdef CFG_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS; -#else - immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* Set low */ -#endif - immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* active output */ - immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET; /* output */ - - immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ - - value = immr->im_cpm.cp_pbdat; - - /* Assert Powerdown and Reset signals */ - value |= CFG_PB_ETH_POWERDOWN; - - /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ -#ifdef CFG_ETH_CFG1_VALUE - value |= CFG_PB_ETH_CFG1; -#else - value &= ~(CFG_PB_ETH_CFG1); -#endif -#ifdef CFG_ETH_CFG2_VALUE - value |= CFG_PB_ETH_CFG2; -#else - value &= ~(CFG_PB_ETH_CFG2); -#endif -#ifdef CFG_ETH_CFG3_VALUE - value |= CFG_PB_ETH_CFG3; -#else - value &= ~(CFG_PB_ETH_CFG3); -#endif - - /* Drive output signals to initial state */ - immr->im_cpm.cp_pbdat = value; - immr->im_cpm.cp_pbdir |= ETH_ALL_BITS; - udelay (10000); - - /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ - udelay (10000); - - /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_padat |= CFG_PA_ETH_RESET; - udelay (1000); -} - - -int misc_init_r (void) -{ - fpga_init(); - return (0); -} -/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/CCM/config.mk b/board/siemens/CCM/config.mk deleted file mode 100644 index 9c72c79..0000000 --- a/board/siemens/CCM/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TQM8xxL boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/siemens/CCM/flash.c b/board/siemens/CCM/flash.c deleted file mode 100644 index 9c32785..0000000 --- a/board/siemens/CCM/flash.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c deleted file mode 100644 index 11b97bc..0000000 --- a/board/siemens/CCM/fpga_ccm.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include - -#include "../common/fpga.h" - -fpga_t fpga_list[] = { - { "PUMA" , PUMA_CONF_BASE , - CFG_PC_PUMA_INIT , CFG_PC_PUMA_PROG , CFG_PC_PUMA_DONE } -}; -int fpga_count = sizeof(fpga_list) / sizeof(fpga_t); - -void can_driver_enable (void); -void can_driver_disable (void); - -#define _NOT_USED_ 0xFFFFFFFF - -/* - * PUMA access using UPM B - */ -const uint puma_table[] = -{ - /* - * Single Read. (Offset 0 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - /* - * Precharge and MRS - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -ulong fpga_control (fpga_t* fpga, int cmd) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - switch (cmd) { - case FPGA_INIT_IS_HIGH: - immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */ - return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0; - - case FPGA_INIT_SET_LOW: - immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pcdat &= ~fpga->init_mask; - break; - - case FPGA_INIT_SET_HIGH: - immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pcdat |= fpga->init_mask; - break; - - case FPGA_PROG_SET_LOW: - immr->im_ioport.iop_pcdat &= ~fpga->prog_mask; - break; - - case FPGA_PROG_SET_HIGH: - immr->im_ioport.iop_pcdat |= fpga->prog_mask; - break; - - case FPGA_DONE_IS_HIGH: - return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0; - - case FPGA_READ_MODE: - /* disable FPGA in memory controller */ - memctl->memc_br4 = 0; - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; - - /* (re-) enable CAN drivers */ - can_driver_enable (); - - break; - - case FPGA_LOAD_MODE: - /* disable FPGA in memory controller */ - memctl->memc_br4 = 0; - /* - * We must disable the CAN drivers first because - * they use UPM B, too. - */ - can_driver_disable (); - /* - * Configure UPMB for FPGA - */ - upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint)); - memctl->memc_or4 = PUMA_CONF_OR_LOAD; - memctl->memc_br4 = PUMA_CONF_BR_LOAD; - break; - - case FPGA_GET_ID: - return *(volatile ulong *)fpga->conf_base; - - case FPGA_INIT_PORTS: - immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */ - immr->im_ioport.iop_pcso &= ~fpga->init_mask; - immr->im_ioport.iop_pcdir &= ~fpga->init_mask; - - immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */ - immr->im_ioport.iop_pcso &= ~fpga->prog_mask; - immr->im_ioport.iop_pcdir |= fpga->prog_mask; - - immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */ - immr->im_ioport.iop_pcso &= ~fpga->done_mask; - immr->im_ioport.iop_pcdir &= ~fpga->done_mask; - - break; - - } - return 0; -} diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds deleted file mode 100644 index cdf550f..0000000 --- a/board/siemens/CCM/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug deleted file mode 100644 index 3b50272..0000000 --- a/board/siemens/CCM/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) -/* - . = env_offset; - common/environment.o(.text) -*/ - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c deleted file mode 100644 index e498937..0000000 --- a/board/siemens/IAD210/IAD210.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * (C) Copyright 2001 - * Paul Geerinckx - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "atm.h" -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -/* used PLD registers */ -# define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0) -# define PLD_EXT_RES (unsigned char *) (0x10000000 + 10) -# define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11) -# define PLD_EXT_LED (unsigned char *) (0x10000000 + 12) -# define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13) - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */ - _NOT_USED_, - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0xFFFAF834, 0xFFE5B435, /* last */ - _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00, - 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF1AAF804, 0xFFA5F447, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84, - 0xFFAFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * MRS sequence (Offset 38 in UPMA RAM) - */ - 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */ - _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0xFFAFFC04, 0xFFAFFC05, /* last */ - _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile iop8xx_t *iop = &immap->im_ioport; - volatile fec_t *fecp = &immap->im_cpm.cp_fec; - long int size; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; - - memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mcr = 0x80004105; /* SDRAM precharge */ - udelay (1); - memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - */ - size = dram_size (CFG_MAMR, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - - memctl->memc_mamr = CFG_MAMR; - udelay (1000); - - /* - * Final mapping - */ - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM; - memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V); - - udelay (10000); - - /* prepare pin multiplexing for fast ethernet */ - - atmLoad (); - fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */ - iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */ - - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - return (0); -} - -void board_serial_init (void) -{ - ; /* nothing to do here */ -} - -void board_ether_init (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile iop8xx_t *iop = &immap->im_ioport; - volatile fec_t *fecp = &immap->im_cpm.cp_fec; - - atmLoad (); - fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */ - iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */ -} - -int board_early_init_f (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile iop8xx_t *iop = &immap->im_ioport; - - /* configure the LED timing output pins - port A pin 4 */ - iop->iop_papar = 0x0800; - iop->iop_padir = 0x0800; - - /* start timer 2 for the 4hz LED blink rate */ - timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */ - timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */ - timers->cpmt_tgcr = 0x00000810; /* run timer 2 */ - - /* chip select for PLD access */ - memctl->memc_br6 = 0x10000401; - memctl->memc_or6 = 0xFC000908; - - /* PLD initial values ( set LEDs, remove reset on LXT) */ - - *PLD_GCR1_REG = 0x06; - *PLD_EXT_RES = 0xC0; - *PLD_EXT_FETH = 0x40; - *PLD_EXT_LED = 0xFF; - *PLD_EXT_X21 = 0x04; - return 0; -} - -void board_get_enetaddr (uchar * addr) -{ - int i; - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cpm = &immap->im_cpm; - unsigned int rccrtmp; - - char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 }; - - for (i = 0; i < 6; i++) - addr[i] = default_mac_addr[i]; - - printf ("There is an error in the i2c driver .. /n"); - printf ("You need to fix it first....../n"); - - rccrtmp = cpm->cp_rccr; - cpm->cp_rccr |= 0x0020; - - i2c_reg_read (0xa0, 0); - printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n", - i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0), - i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0), - i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0)); - - cpm->cp_rccr = rccrtmp; -} diff --git a/board/siemens/IAD210/Makefile b/board/siemens/IAD210/Makefile deleted file mode 100644 index 87a6893..0000000 --- a/board/siemens/IAD210/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o atm.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c deleted file mode 100644 index c77e359..0000000 --- a/board/siemens/IAD210/atm.c +++ /dev/null @@ -1,653 +0,0 @@ - -#include -#include -#include - -#include "atm.h" -#include - -#define SYNC __asm__("sync") -#define ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1))) - -#define FALSE 1 -#define TRUE 0 -#define OK 0 -#define ERROR -1 - -struct atm_connection_t g_conn[NUM_CONNECTIONS] = -{ - { NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */ -}; - -struct atm_driver_t g_atm = -{ - FALSE, /* loaded */ - FALSE, /* started */ - NULL, /* csram */ - 0, /* csram_size */ - NULL, /* am_top */ - NULL, /* ap_top */ - NULL, /* int_reload_ptr */ - NULL, /* int_serv_ptr */ - NULL, /* rbd_base_ptr */ - NULL, /* tbd_base_ptr */ - 0 /* linerate */ -}; - -char csram[1024]; /* more than enough for doing nothing*/ - -int atmLoad(void); -void atmUnload(void); -int atmMemInit(void); -void atmIntInit(void); -void atmApcInit(void); -void atmAmtInit(void); -void atmCpmInit(void); -void atmUtpInit(void); - -/***************************************************************************** - * - * FUNCTION NAME: atmLoad - * - * DESCRIPTION: Basic ATM initialization. - * - * PARAMETERS: none - * - * RETURNS: OK or ERROR - * - ****************************************************************************/ -int atmLoad() -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; - volatile iop8xx_t *iop = &immap->im_ioport; - - timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */ - immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */ - iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */ - - if ( atmMemInit() != OK ) return ERROR; - - atmIntInit(); - atmApcInit(); - atmAmtInit(); - atmCpmInit(); - atmUtpInit(); - - g_atm.loaded = TRUE; - - return OK; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmUnload - * - * DESCRIPTION: Disables ATM and UTOPIA. - * - * PARAMETERS: none - * - * RETURNS: void - * - ****************************************************************************/ -void atmUnload() -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; - volatile iop8xx_t *iop = &immap->im_ioport; - - timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */ - immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */ - iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */ - g_atm.loaded = FALSE; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmMemInit - * - * DESCRIPTION: - * - * The ATM driver uses the following resources: - * - * A. Memory in DPRAM to hold - * - * 1/ CT = Connection Table ( RCT & TCT ) - * 2/ TCTE = Transmit Connection Table Extension - * 3/ MPHYPT = Multi-PHY Pointing Table - * 4/ APCP = APC Parameter Table - * 5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 ) - * 6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR ) - * 7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR ) - * 8/ TQ = Transmit Queue - * 9/ AM = Address Matching Table - * 10/ AP = Address Pointing Table - * - * B. Memory in cache safe RAM to hold - * - * 1/ INT = Interrupt Queue - * 2/ RBD = Receive Buffer Descriptors - * 3/ TBD = Transmit Buffer Descriptors - * - * This function - * 1. clears the ATM DPRAM area, - * 2. Allocates and clears cache safe memory, - * 3. Initializes 'g_conn'. - * - * PARAMETERS: none - * - * RETURNS: OK or ERROR - * - ****************************************************************************/ -int atmMemInit() -{ - int i; - unsigned immr = CFG_IMMR; - int total_num_rbd = 0; - int total_num_tbd = 0; - - memset((char *)CFG_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE); - - g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY; - - for ( i = 0; i < NUM_CONNECTIONS; ++i ) { - total_num_rbd += g_conn[i].num_rbd; - total_num_tbd += g_conn[i].num_tbd; - } - - g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4; - - g_atm.csram = &csram[0]; - memset(&(g_atm.csram), 0x00, g_atm.csram_size); - - g_atm.int_reload_ptr = (uint32 *)ALIGN(g_atm.csram, 4); - g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES); - g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd); - - g_conn[0].rbd_ptr = g_atm.rbd_base_ptr; - g_conn[0].tbd_ptr = g_atm.tbd_base_ptr; - g_conn[0].ct_ptr = CT_PTR(immr); - g_conn[0].tcte_ptr = TCTE_PTR(immr); - - return OK; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmIntInit - * - * DESCRIPTION: - * - * Initialization of the MPC860 ESAR Interrupt Queue. - * This function - * - clears all entries in the INT, - * - sets the WRAP bit of the last INT entry, - * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure - * to the first INT entry. - * - * PARAMETERS: none - * - * RETURNS: void - * - * REMARKS: - * - * - The INT resides in external cache safe memory. - * - The base address of the INT is stored in g_atm.int_reload_ptr. - * - The number of entries in the INT is given by NUM_INT_ENTRIES. - * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit(). - * - ****************************************************************************/ -void atmIntInit() -{ - int i; - for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0; - g_atm.int_reload_ptr[i] = INT_WRAP; - g_atm.int_serv_ptr = g_atm.int_reload_ptr; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmApcInit - * - * DESCRIPTION: - * - * This function initializes the following ATM Pace Controller related - * data structures: - * - * - 1 MPHY Pointing Table (contains only one entry) - * - 3 APC Parameter Tables (one PHY with 3 priorities) - * - 3 APC Tables (one table for each priority) - * - 1 Transmit Queue (one transmit queue per PHY) - * - * PARAMETERS: none - * - * RETURNS: void - * - ****************************************************************************/ -void atmApcInit() -{ - int i; - /* unsigned immr = CFG_IMMR; */ - uint16 * mphypt_ptr = MPHYPT_PTR(CFG_IMMR); - struct apc_params_t * apcp_ptr = APCP_PTR(CFG_IMMR); - uint16 * apct_prio1_ptr = APCT1_PTR(CFG_IMMR); - uint16 * tq_ptr = TQ_PTR(CFG_IMMR); - /***************************************************/ - /* Initialize MPHY Pointing Table (only one entry) */ - /***************************************************/ - *mphypt_ptr = APCP_BASE; - - /********************************************/ - /* Initialize APC parameters for priority 1 */ - /********************************************/ - apcp_ptr->apct_base1 = APCT_PRIO_1_BASE; - apcp_ptr->apct_end1 = APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2; - apcp_ptr->apct_ptr1 = APCT_PRIO_1_BASE; - apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE; - apcp_ptr->etqbase = TQ_BASE; - apcp_ptr->etqend = TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2; - apcp_ptr->etqaptr = TQ_BASE; - apcp_ptr->etqtptr = TQ_BASE; - apcp_ptr->apc_mi = 8; - apcp_ptr->ncits = 0x0100; /* NCITS = 1 */ - apcp_ptr->apcnt = 0; - apcp_ptr->reserved1 = 0; - apcp_ptr->eapcst = 0x2009; /* LAST, ESAR, MPHY */ - apcp_ptr->ptp_counter = 0; - apcp_ptr->ptp_txch = 0; - apcp_ptr->reserved2 = 0; - - - /***************************************************/ - /* Initialize APC Tables with empty slots (0xFFFF) */ - /***************************************************/ - for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF; - - /************************/ - /* Clear Transmit Queue */ - /************************/ - for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmAmtInit - * - * DESCRIPTION: - * - * This function clears the first entry in the Address Matching Table and - * lets the first entry in the Address Pointing table point to the first - * entry in the TCT table (i.e. the raw cell channel). - * - * PARAMETERS: none - * - * RETURNS: void - * - * REMARKS: - * - * The values for the AMBASE, AMEND and APBASE registers in SAR parameter - * RAM are initialized by atmCpmInit(). - * - ****************************************************************************/ -void atmAmtInit() -{ - unsigned immr = CFG_IMMR; - - g_atm.am_top = AM_PTR(immr); - g_atm.ap_top = AP_PTR(immr); - - *(g_atm.ap_top--) = CT_BASE; - *(g_atm.am_top--) = 0; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmCpmInit - * - * DESCRIPTION: - * - * This function initializes the Utopia Interface Parameter RAM Map - * (SCC4, ATM Protocol) of the Communication Processor Modudule. - * - * PARAMETERS: none - * - * RETURNS: void - * - ****************************************************************************/ -void atmCpmInit() -{ - unsigned immr = CFG_IMMR; - - memset((char *)immr + 0x3F00, 0x00, 0xC0); - - /*-----------------------------------------------------------------*/ - /* RBDBASE - Receive buffer descriptors base address */ - /* The RBDs reside in cache safe external memory. */ - /*-----------------------------------------------------------------*/ - *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr; - - /*-----------------------------------------------------------------*/ - /* SRFCR - SAR receive function code */ - /* 0-2 rsvd = 000 */ - /* 3-4 BO = 11 Byte ordering (big endian). */ - /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */ - /* when the SDMA channel accesses memory. */ - /*-----------------------------------------------------------------*/ - *SRFCR(immr) = 0x18; - - /*-----------------------------------------------------------------*/ - /* SRSTATE - SAR receive status */ - /* 0 EXT = 0 Extended mode off. */ - /* 1 ACP = 0 Valid only if EXT = 1. */ - /* 2 EC = 0 Standard 53-byte ATM cell. */ - /* 3 SNC = 0 In sync. Must be set to 0 during initialization. */ - /* 4 ESAR = 1 Enhanced SAR functionality enabled. */ - /* 5 MCF = 1 Management Cell Filter active. */ - /* 6 SER = 0 UTOPIA mode. */ - /* 7 MPY = 1 Multiple PHY mode. */ - /*-----------------------------------------------------------------*/ - *SRSTATE(immr) = 0x0D; - - /*-----------------------------------------------------------------*/ - /* MRBLR - Maximum receive buffer length register. */ - /* Must be cleared for ATM operation (see also SMRBLR). */ - /*-----------------------------------------------------------------*/ - *MRBLR(immr) = 0; - - /*-----------------------------------------------------------------*/ - /* RSTATE - SCC internal receive state parameters */ - /* The first byte must be initialized with the value of SRFCR. */ - /*-----------------------------------------------------------------*/ - *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24; - - /*-----------------------------------------------------------------*/ - /* STFCR - SAR transmit function code */ - /* 0-2 rsvd = 000 */ - /* 3-4 BO = 11 Byte ordering (big endian). */ - /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */ - /* when the SDMA channel accesses memory. */ - /*-----------------------------------------------------------------*/ - *STFCR(immr) = 0x18; - - /*-----------------------------------------------------------------*/ - /* SRSTATE - SAR transmit status */ - /* 0 EXT = 0 : Extended mode off */ - /* 1 rsvd = 0 : */ - /* 2 EC = 0 : Standard 53-byte ATM cell */ - /* 3 rsvd = 0 : */ - /* 4 ESAR = 1 : Enhanced SAR functionality enabled */ - /* 5 rsvd = 0 : */ - /* 6 SER = 0 : UTOPIA mode */ - /* 7 MPY = 1 : Multiple PHY mode */ - /*-----------------------------------------------------------------*/ - *STSTATE(immr) = 0x09; - - /*-----------------------------------------------------------------*/ - /* TBDBASE - Transmit buffer descriptors base address */ - /* The TBDs reside in cache safe external memory. */ - /*-----------------------------------------------------------------*/ - *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr; - - /*-----------------------------------------------------------------*/ - /* TSTATE - SCC internal transmit state parameters */ - /* The first byte must be initialized with the value of STFCR. */ - /*-----------------------------------------------------------------*/ - *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24; - - /*-----------------------------------------------------------------*/ - /* CTBASE - Connection table base address */ - /* Offset from the beginning of DPRAM (64-byte aligned). */ - /*-----------------------------------------------------------------*/ - *CTBASE(immr) = CT_BASE; - - /*-----------------------------------------------------------------*/ - /* INTBASE - Interrupt queue base pointer. */ - /* The interrupt queue resides in cache safe external memory. */ - /*-----------------------------------------------------------------*/ - *INTBASE(immr) = (uint32)g_atm.int_reload_ptr; - - /*-----------------------------------------------------------------*/ - /* INTPTR - Pointer into interrupt queue. */ - /* Initialize to INTBASE. */ - /*-----------------------------------------------------------------*/ - *INTPTR(immr) = *INTBASE(immr); - - /*-----------------------------------------------------------------*/ - /* C_MASK - Constant mask for CRC32 */ - /* Must be initialized to 0xDEBB20E3. */ - /*-----------------------------------------------------------------*/ - *C_MASK(immr) = 0xDEBB20E3; - - /*-----------------------------------------------------------------*/ - /* INT_ICNT - Interrupt threshold value */ - /*-----------------------------------------------------------------*/ - *INT_ICNT(immr) = 1; - - /*-----------------------------------------------------------------*/ - /* INT_CNT - Interrupt counter */ - /* Initalize to INT_ICNT. Decremented for each interrupt entry */ - /* reported in the interrupt queue. On zero an interrupt is */ - /* signaled to the host by setting the GINT bit in the event */ - /* register. The counter is reinitialized with INT_ICNT. */ - /*-----------------------------------------------------------------*/ - *INT_CNT(immr) = *INT_ICNT(immr); - - /*-----------------------------------------------------------------*/ - /* SMRBLR - SAR maximum receive buffer length register. */ - /* Must be a multiple of 48 bytes. Common for all ATM connections. */ - /*-----------------------------------------------------------------*/ - *SMRBLR(immr) = SAR_RXB_SIZE; - - /*-----------------------------------------------------------------*/ - /* APCST - APC status register. */ - /* 0 rsvd 0 */ - /* 1-2 CSER 11 Initialize with the same value as NSER. */ - /* 3-4 NSER 11 Next serial or UTOPIA channel. */ - /* 5-7 rsvd 000 */ - /* 8-10 rsvd 000 */ - /* 11 rsvd 0 */ - /* 12 ESAR 1 UTOPIA Level 2 MPHY enabled. */ - /* 13 DIS 0 APC disable. Must be initiazed to 0. */ - /* 14 PL2 0 Not used. */ - /* 15 MPY 1 Multiple PHY mode on. */ - /*-----------------------------------------------------------------*/ - *APCST(immr) = 0x7809; - - /*-----------------------------------------------------------------*/ - /* APCPTR - Pointer to the APC parameter table */ - /* In MPHY master mode this parameter points to the MPHY pointing */ - /* table. 2-byte aligned. */ - /*-----------------------------------------------------------------*/ - *APCPTR(immr) = MPHYPT_BASE; - - /*-----------------------------------------------------------------*/ - /* HMASK - Header mask */ - /* Each incoming cell is masked with HMASK before being compared */ - /* to the entries in the address matching table. */ - /*-----------------------------------------------------------------*/ - *HMASK(immr) = AM_HMASK; - - /*-----------------------------------------------------------------*/ - /* AMBASE - Address matching table base address */ - /*-----------------------------------------------------------------*/ - *AMBASE(immr) = AM_BASE; - - /*-----------------------------------------------------------------*/ - /* AMEND - Address matching table end address */ - /*-----------------------------------------------------------------*/ - *AMEND(immr) = AM_BASE; - - /*-----------------------------------------------------------------*/ - /* APBASE - Address pointing table base address */ - /*-----------------------------------------------------------------*/ - *APBASE(immr) = AP_BASE; - - /*-----------------------------------------------------------------*/ - /* MPHYST - MPHY status register */ - /* 0-1 rsvd 00 */ - /* 2-6 NMPHY 00000 1 PHY */ - /* 7-9 rsvd 000 */ - /* 10-14 CMPHY 00000 Initialize with same value as NMPHY */ - /*-----------------------------------------------------------------*/ - *MPHYST(immr) = 0x0000; - - /*-----------------------------------------------------------------*/ - /* TCTEBASE - Transmit connection table extension base address */ - /* Offset from the beginning of DPRAM (32-byte aligned). */ - /*-----------------------------------------------------------------*/ - *TCTEBASE(immr) = TCTE_BASE; - - /*-----------------------------------------------------------------*/ - /* Clear not used registers. */ - /*-----------------------------------------------------------------*/ -} - -/***************************************************************************** - * - * FUNCTION NAME: atmUtpInit - * - * DESCRIPTION: - * - * This function initializes the ATM interface for - * - * - UTOPIA mode - * - muxed bus - * - master operation - * - multi PHY (because of a bug in the MPC860P rev. E.0) - * - internal clock = SYSCLK / 2 - * - * EXTERNAL EFFECTS: - * - * After calling this function, the MPC860ESAR UTOPIA bus is - * active and uses the following ports/pins: - * - * Port Pin Signal Description - * ------ --- ------- ------------------------------------------- - * PB[15] R17 TxClav Transmit cell available input/output signal - * PC[15] D16 RxClav Receive cell available input/output signal - * PD[15] U17 UTPB[0] UTOPIA bus bit 0 input/output signal - * PD[14] V19 UTPB[1] UTOPIA bus bit 1 input/output signal - * PD[13] V18 UTPB[2] UTOPIA bus bit 2 input/output signal - * PD[12] R16 UTPB[3] UTOPIA bus bit 3 input/output signal - * PD[11] T16 RXENB Receive enable input/output signal - * PD[10] W18 TXENB Transmit enable input/output signal - * PD[9] V17 UTPCLK UTOPIA clock input/output signal - * PD[7] T15 UTPB[4] UTOPIA bus bit 4 input/output signal - * PD[6] V16 UTPB[5] UTOPIA bus bit 5 input/output signal - * PD[5] U15 UTPB[6] UTOPIA bus bit 6 input/output signal - * PD[4] U16 UTPB[7] UTOPIA bus bit 7 input/output signal - * PD[3] W16 SOC Start of cell input/output signal - * - * PARAMETERS: none - * - * RETURNS: void - * - * REMARK: - * - * The ATM parameters and data structures must be configured before - * initializing the UTOPIA port. The UTOPIA port activates immediately - * upon initialization, and if its associated data structures are not - * initialized, the CPM will lock up. - * - ****************************************************************************/ -void atmUtpInit() -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile iop8xx_t *iop = &immap->im_ioport; - volatile car8xx_t *car = &immap->im_clkrst; - volatile cpm8xx_t *cpm = &immap->im_cpm; - int flag; - - flag = disable_interrupts(); - - /*-----------------------------------------------------------------*/ - /* SCCR - System Clock Control Register */ - /* */ - /* The UTOPIA clock can be selected to be internal clock or */ - /* external clock (selected by the UTOPIA mode register). */ - /* In case of internal clock, the UTOPIA clock is derived from */ - /* the system frequency divided by two dividers. */ - /* Bits 27-31 of the SCCR register are defined to control the */ - /* UTOPIA clock. */ - /* */ - /* SCCR[27:29] DFUTP Division factor. Divide the system clock */ - /* by 2^DFUTP. */ - /* SCCR[30:31] DFAUTP Additional division factor. Divide the */ - /* system clock by the following value: */ - /* 00 = divide by 1 */ - /* 00 = divide by 3 */ - /* 10 = divide by 5 */ - /* 11 = divide by 7 */ - /* */ - /* Note that the UTOPIA clock must be programmed as to operate */ - /* within the range SYSCLK/10 .. 50Mhz. */ - /*-----------------------------------------------------------------*/ - car->car_sccr &= 0xFFFFFFE0; - car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */ - - /*-----------------------------------------------------------------*/ - /* RCCR - RISC Controller Configuration Register */ - /* */ - /* RCCR[8] DR1M IDMA Request 0 Mode */ - /* 0 = edge sensitive */ - /* 1 = level sensitive */ - /* RCCR[9] DR0M IDMA Request 0 Mode */ - /* 0 = edge sensitive */ - /* 1 = level sensitive */ - /* RCCR[10:11] DRQP IDMA Request Priority */ - /* 00 = IDMA req. have more prio. than SCCs */ - /* 01 = IDMA req. have less prio. then SCCs */ - /* 10 = IDMA requests have the lowest prio. */ - /* 11 = reserved */ - /* */ - /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */ - /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */ - /* higher priority. */ - /*-----------------------------------------------------------------*/ - cpm->cp_rccr &= 0xFF0F; - cpm->cp_rccr |= 0x00D0; - - /*-----------------------------------------------------------------*/ - /* Port B - TxClav Signal */ - /*-----------------------------------------------------------------*/ - cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */ - cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */ - - /*-----------------------------------------------------------------*/ - /* UTOPIA Mode Register */ - /* */ - /* - muxed bus (master operation only) */ - /* - multi PHY (because of a bug in the MPC860P rev.E.0) */ - /* - internal clock */ - /* - no loopback */ - /* - do no activate statistical counters */ - /*-----------------------------------------------------------------*/ - iop->utmode = 0x00000004; SYNC; - - /*-----------------------------------------------------------------*/ - /* Port D - UTOPIA Data and Control Signals */ - /* */ - /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals */ - /* 11 RXENB UTOPIA receive enable input/output signal */ - /* 10 TXENB UTOPIA transmit enable input/output signal */ - /* 9 TUPCLK UTOPIA clock input/output signal */ - /* 8 MII-MDC Used by MII in simult. MII and UTOPIA operation */ - /* 7-4 UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals */ - /* 3 SOC UTOPIA Start of cell input/output signal */ - /* 2 Reserved */ - /* 1 Enable UTOPIA mode */ - /* 0 Enable SAR */ - /*-----------------------------------------------------------------*/ - iop->iop_pdpar |= 0xDF7F; SYNC; - iop->iop_pddir &= 0x2080; SYNC; - - /*-----------------------------------------------------------------*/ - /* Port C - RxClav Signal */ - /*-----------------------------------------------------------------*/ - iop->iop_pcpar |= 0x0001; /* PCPAR[15] = 1 */ - iop->iop_pcdir &= 0xFFFE; /* PCDIR[15] = 0 */ - iop->iop_pcso &= 0xFFFE; /* PCSO[15] = 0 */ - - if (flag) - enable_interrupts(); -} diff --git a/board/siemens/IAD210/atm.h b/board/siemens/IAD210/atm.h deleted file mode 100644 index 71b0497..0000000 --- a/board/siemens/IAD210/atm.h +++ /dev/null @@ -1,287 +0,0 @@ -typedef unsigned char uint8; -typedef unsigned short uint16; -typedef unsigned int uint32; -typedef volatile unsigned char vuint8; -typedef volatile unsigned short vuint16; -typedef volatile unsigned int vuint32; - - -#define DPRAM_ATM CFG_IMMR + 0x3000 - -#define ATM_DPRAM_BEGIN (DPRAM_ATM - CFG_IMMR - 0x2000) -#define NUM_CONNECTIONS 1 -#define SAR_RXB_SIZE 1584 -#define AM_HMASK 0x0FFFFFF0 - -#define NUM_CT_ENTRIES (NUM_CONNECTIONS) -#define NUM_TCTE_ENTRIES (NUM_CONNECTIONS) -#define NUM_AM_ENTRIES (NUM_CONNECTIONS+1) -#define NUM_AP_ENTRIES (NUM_CONNECTIONS+1) -#define NUM_MPHYPT_ENTRIES 1 -#define NUM_APCP_ENTRIES 1 -#define NUM_APCT_PRIO_1_ENTRIES 146 /* Determines minimum rate */ -#define NUM_TQ_ENTRIES 12 - -#define SIZE_OF_CT_ENTRY 64 -#define SIZE_OF_TCTE_ENTRY 32 -#define SIZE_OF_AM_ENTRY 4 -#define SIZE_OF_AP_ENTRY 2 -#define SIZE_OF_MPHYPT_ENTRY 2 -#define SIZE_OF_APCP_ENTRY 32 -#define SIZE_OF_APCT_ENTRY 2 -#define SIZE_OF_TQ_ENTRY 2 - -#define CT_BASE ((ATM_DPRAM_BEGIN + 63) & 0xFFC0) /*64 */ -#define TCTE_BASE (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY) /*32 */ -#define APCP_BASE (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY) /*32 */ -#define AM_BEGIN (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY) /*4 */ -#define AM_BASE (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY) -#define AP_BEGIN (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY) /*2 */ -#define AP_BASE (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY) -#define MPHYPT_BASE (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY) /*2 */ -#define APCT_PRIO_1_BASE (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY) /*2 */ -#define TQ_BASE (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY) /*2 */ -#define ATM_DPRAM_SIZE ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN) - -#define CT_PTR(base) ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE)) -#define TCTE_PTR(base) ((struct tcte_entry_t *)((char *)(base) + 0x2000 + TCTE_BASE)) -#define AM_PTR(base) ((uint32 *)((char *)(base) + 0x2000 + AM_BASE)) -#define AP_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + AP_BASE)) -#define MPHYPT_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + MPHYPT_BASE)) -#define APCP_PTR(base) ((struct apc_params_t *)((char*)(base) + 0x2000 + APCP_BASE)) -#define APCT1_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_1_BASE)) -#define APCT2_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_2_BASE)) -#define APCT3_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_3_BASE)) -#define TQ_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE)) - -/* SAR registers */ -#define RBDBASE(base) ((vuint32 *)(base + 0x3F00)) /* Base address of RxBD-List */ -#define SRFCR(base) ((vuint8 *)(base + 0x3F04)) /* DMA Receive function code */ -#define SRSTATE(base) ((vuint8 *)(base + 0x3F05)) /* DMA Receive status */ -#define MRBLR(base) ((vuint16 *)(base + 0x3F06)) /* Init to 0 for ATM */ -#define RSTATE(base) ((vuint32 *)(base + 0x3F08)) /* Do not write to */ -#define R_CNT(base) ((vuint16 *)(base + 0x3F10)) /* Do not write to */ -#define STFCR(base) ((vuint8 *)(base + 0x3F12)) /* DMA Transmit function code */ -#define STSTATE(base) ((vuint8 *)(base + 0x3F13)) /* DMA Transmit status */ -#define TBDBASE(base) ((vuint32 *)(base + 0x3F14)) /* Base address of TxBD-List */ -#define TSTATE(base) ((vuint32 *)(base + 0x3F18)) /* Do not write to */ -#define COMM_CH(base) ((vuint16 *)(base + 0x3F1C)) /* Command channel */ -#define STCHNUM(base) ((vuint16 *)(base + 0x3F1E)) /* Do not write to */ -#define T_CNT(base) ((vuint16 *)(base + 0x3F20)) /* Do not write to */ -#define CTBASE(base) ((vuint16 *)(base + 0x3F22)) /* Base address of Connection-table */ -#define ECTBASE(base) ((vuint32 *)(base + 0x3F24)) /* Valid only for external Conn.-table */ -#define INTBASE(base) ((vuint32 *)(base + 0x3F28)) /* Base address of Interrupt-table */ -#define INTPTR(base) ((vuint32 *)(base + 0x3F2C)) /* Pointer to Interrupt-queue */ -#define C_MASK(base) ((vuint32 *)(base + 0x3F30)) /* CRC-mask */ -#define SRCHNUM(base) ((vuint16 *)(base + 0x3F34)) /* Do not write to */ -#define INT_CNT(base) ((vuint16 *)(base + 0x3F36)) /* Interrupt-Counter */ -#define INT_ICNT(base) ((vuint16 *)(base + 0x3F38)) /* Interrupt threshold */ -#define TSTA(base) ((vuint16 *)(base + 0x3F3A)) /* Time-stamp-address */ -#define OLDLEN(base) ((vuint16 *)(base + 0x3F3C)) /* Do not write to */ -#define SMRBLR(base) ((vuint16 *)(base + 0x3F3E)) /* SAR max RXBuffer length */ -#define EHEAD(base) ((vuint32 *)(base + 0x3F40)) /* Valid for serial mode */ -#define EPAYLOAD(base) ((vuint32 *)(base + 0x3F44)) /* Valid for serial mode */ -#define TQBASE(base) ((vuint16 *)(base + 0x3F48)) /* Base address of Tx queue */ -#define TQEND(base) ((vuint16 *)(base + 0x3F4A)) /* End address of Tx queue */ -#define TQAPTR(base) ((vuint16 *)(base + 0x3F4C)) /* TQ APC pointer */ -#define TQTPTR(base) ((vuint16 *)(base + 0x3F4E)) /* TQ Tx pointer */ -#define APCST(base) ((vuint16 *)(base + 0x3F50)) /* APC status */ -#define APCPTR(base) ((vuint16 *)(base + 0x3F52)) /* APC parameter pointer */ -#define HMASK(base) ((vuint32 *)(base + 0x3F54)) /* Header mask */ -#define AMBASE(base) ((vuint16 *)(base + 0x3F58)) /* Address match table base */ -#define AMEND(base) ((vuint16 *)(base + 0x3F5A)) /* Address match table end */ -#define APBASE(base) ((vuint16 *)(base + 0x3F5C)) /* Address match parameter */ -#define FLBASE(base) ((vuint32 *)(base + 0x3F54)) /* First-level table base */ -#define SLBASE(base) ((vuint32 *)(base + 0x3F58)) /* Second-level table base */ -#define FLMASK(base) ((vuint16 *)(base + 0x3F5C)) /* First-level mask */ -#define ECSIZE(base) ((vuint16 *)(base + 0x3F5E)) /* Valid for extended mode */ -#define APCT_REAL(base) ((vuint32 *)(base + 0x3F60)) /* APC 32 bit counter */ -#define R_PTR(base) ((vuint32 *)(base + 0x3F64)) /* Do not write to */ -#define RTEMP(base) ((vuint32 *)(base + 0x3F68)) /* Do not write to */ -#define T_PTR(base) ((vuint32 *)(base + 0x3F6C)) /* Do not write to */ -#define TTEMP(base) ((vuint32 *)(base + 0x3F70)) /* Do not write to */ - -/* ESAR registers */ -#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80)) /* Perf.Mon.Timestamp */ -#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84)) /* Perf.Mon.Template */ -#define PMPTR(base) ((vuint16 *)(base + 0x3F88)) /* Perf.Mon.Table */ -#define PMCHANNEL(base) ((vuint16 *)(base + 0x3F8A)) /* Perf.Mon.Channel */ -#define MPHYST(base) ((vuint16 *)(base + 0x3F90)) /* Multi-PHY Status */ -#define TCTEBASE(base) ((vuint16 *)(base + 0x3F92)) /* Internal TCT Extension Base */ -#define ETCTEBASE(base) ((vuint32 *)(base + 0x3F94)) /* External TCT Extension Base */ -#define COMM_CH2(base) ((vuint32 *)(base + 0x3F98)) /* 2nd command channel word */ -#define STATBASE(base) ((vuint16 *)(base + 0x3F9C)) /* Statistics table pointer */ - -/* UTOPIA Mode Register */ -#define UTMODE(base) (CAST(vuint32 *)(base + 0x0978)) - -/* SAR commands */ -#define TRANSMIT_CHANNEL_ACTIVATE_CMD 0x0FC1 -#define TRANSMIT_CHANNEL_DEACTIVATE_CMD 0x1FC1 -#define STOP_TRANSMIT_CMD 0x2FC1 -#define RESTART_TRANSMIT_CMD 0x3FC1 -#define STOP_RECEIVE_CMD 0x4FC1 -#define RESTART_RECEIVE_CMD 0x5FC1 -#define APC_BYPASS_CMD 0x6FC1 -#define MEM_WRITE_CMD 0x7FC1 -#define CPCR_FLG 0x0001 - -/* INT flags */ -#define INT_VALID 0x80000000 -#define INT_WRAP 0x40000000 -#define INT_APCO 0x00800000 -#define INT_TQF 0x00200000 -#define INT_RXF 0x00080000 -#define INT_BSY 0x00040000 -#define INT_TXB 0x00020000 -#define INT_RXB 0x00010000 - -#define NUM_INT_ENTRIES 80 -#define SIZE_OF_INT_ENTRY 4 - -struct apc_params_t { - vuint16 apct_base1; /* APC Table - First Priority Base pointer */ - vuint16 apct_end1; /* First APC Table - Length */ - vuint16 apct_ptr1; /* First APC Table Pointer */ - vuint16 apct_sptr1; /* APC Table First Priority Service pointer */ - vuint16 etqbase; /* Enhanced Transmit Queue Base pointer */ - vuint16 etqend; /* Enhanced Transmit Queue End pointer */ - vuint16 etqaptr; /* Enhanced Transmit Queue APC pointer */ - vuint16 etqtptr; /* Enhanced Transmit Queue Transmitter pointer */ - vuint16 apc_mi; /* APC - Max Iteration */ - vuint16 ncits; /* Number of Cells In TimeSlot */ - vuint16 apcnt; /* APC - N Timer */ - vuint16 reserved1; /* reserved */ - vuint16 eapcst; /* APC status */ - vuint16 ptp_counter; /* PTP queue length */ - vuint16 ptp_txch; /* PTP channel */ - vuint16 reserved2; /* reserved */ -}; - -struct ct_entry_t { - /* RCT */ - unsigned fhnt:1; - unsigned pm_rct:1; - unsigned reserved0:6; - unsigned hec:1; - unsigned clp:1; - unsigned cng_ncrc:1; - unsigned inf_rct:1; - unsigned cngi_ptp:1; - unsigned cdis_rct:1; - unsigned aal_rct:2; - uint16 rbalen; - uint32 rcrc; - uint32 rb_ptr; - uint16 rtmlen; - uint16 rbd_ptr; - uint16 rbase; - uint16 tstamp; - uint16 imask; - unsigned ft:2; - unsigned nim:1; - unsigned reserved1:2; - unsigned rpmt:6; - unsigned reserved2:5; - uint8 reserved3[8]; - /* TCT */ - unsigned reserved4:1; - unsigned pm_tct:1; - unsigned reserved5:6; - unsigned pc:1; - unsigned reserved6:2; - unsigned inf_tct:1; - unsigned cr10:1; - unsigned cdis_tct:1; - unsigned aal_tct:2; - uint16 tbalen; - uint32 tcrc; - uint32 tb_ptr; - uint16 ttmlen; - uint16 tbd_ptr; - uint16 tbase; - unsigned reserved7:5; - unsigned tpmt:6; - unsigned reserved8:3; - unsigned avcf:1; - unsigned act:1; - uint32 chead; - uint16 apcl; - uint16 apcpr; - unsigned out:1; - unsigned bnr:1; - unsigned tservice:2; - unsigned apcp:12; - uint16 apcpf; -}; - -struct tcte_entry_t { - unsigned res1:4; - unsigned scr:12; - uint16 scrf; - uint16 bt; - uint16 buptrh; - uint32 buptrl; - unsigned vbr2:1; - unsigned res2:15; - uint16 oobr; - uint16 res3[8]; -}; - -#define SIZE_OF_RBD 12 -#define SIZE_OF_TBD 12 - -struct atm_bd_t { - vuint16 flags; - vuint16 length; - unsigned char *buffer_ptr; - vuint16 cpcs_uu_cpi; - vuint16 reserved; -}; - -/* BD flags */ -#define EMPTY 0x8000 -#define READY 0x8000 -#define WRAP 0x2000 -#define INTERRUPT 0x1000 -#define LAST 0x0800 -#define FIRST 0x0400 -#define OAM 0x0400 -#define CONTINUOUS 0x0200 -#define HEC_ERROR 0x0080 -#define CELL_LOSS 0x0040 -#define CONGESTION 0x0020 -#define ABORT 0x0010 -#define LEN_ERROR 0x0002 -#define CRC_ERROR 0x0001 - -struct atm_connection_t { - struct atm_bd_t *rbd_ptr; - int num_rbd; - struct atm_bd_t *tbd_ptr; - int num_tbd; - struct ct_entry_t *ct_ptr; - struct tcte_entry_t *tcte_ptr; - void *drv; - void (*notify) (void *drv, int event); -}; - -struct atm_driver_t { - int loaded; - int started; - char *csram; - int csram_size; - uint32 *am_top; - uint16 *ap_top; - uint32 *int_reload_ptr; - uint32 *int_serv_ptr; - struct atm_bd_t *rbd_base_ptr; - struct atm_bd_t *tbd_base_ptr; - unsigned linerate_in_bps; -}; - -extern struct atm_connection_t g_conn[NUM_CONNECTIONS]; -extern struct atm_driver_t g_atm; - -extern int atmLoad (void); -extern void atmUnload (void); diff --git a/board/siemens/IAD210/config.mk b/board/siemens/IAD210/config.mk deleted file mode 100644 index c30abcb..0000000 --- a/board/siemens/IAD210/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# iad210 boards -# - -TEXT_BASE = 0x08000000 -/*TEXT_BASE = 0x00200000 */ diff --git a/board/siemens/IAD210/flash.c b/board/siemens/IAD210/flash.c deleted file mode 100644 index 110858d..0000000 --- a/board/siemens/IAD210/flash.c +++ /dev/null @@ -1,502 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds deleted file mode 100644 index 42e1b83..0000000 --- a/board/siemens/IAD210/u-boot.lds +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - cpu/mpc8xx/interrupts.o (.text) - lib_ppc/time.o (.text) - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/SCM/Makefile b/board/siemens/SCM/Makefile deleted file mode 100644 index af646e4..0000000 --- a/board/siemens/SCM/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \ - ../../tqm8xx/load_sernum_ethaddr.o - - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/siemens/SCM/config.mk b/board/siemens/SCM/config.mk deleted file mode 100644 index 855ae38..0000000 --- a/board/siemens/SCM/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Siemens SCM boards -# - -# This should be equal to the CFG_FLASH_BASE define in config_SCM.h -# for the "final" configuration, with U-Boot in flash, or the address -# in RAM where U-Boot is loaded at for debugging. -# -TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/siemens/SCM/flash.c b/board/siemens/SCM/flash.c deleted file mode 100644 index 056fe81..0000000 --- a/board/siemens/SCM/flash.c +++ /dev/null @@ -1,488 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AMD devices on the TQM8260 board - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define V_ULONG(a) (*(volatile unsigned long *)( a )) -#define V_BYTE(a) (*(volatile unsigned char *)( a )) - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ -void flash_reset (void) -{ - if (flash_info[0].flash_id != FLASH_UNKNOWN) { - V_ULONG (flash_info[0].start[0]) = 0x00F000F0; - V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0; - } -} - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (ulong baseaddr, flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - /* Write auto select command sequence and test FLASH answer */ - V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA; - V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055; - V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090; - V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA; - V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055; - V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090; - - flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */ - flashtest_l = V_ULONG (baseaddr + 4); - - switch ((int) flashtest_h) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - flashtest_h = V_ULONG (baseaddr + 8); /* device ID */ - flashtest_l = V_ULONG (baseaddr + 12); - if (flashtest_h != flashtest_l) { - info->flash_id = FLASH_UNKNOWN; - } else { - switch (flashtest_h) { - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00400000; - break; /* 4 * 1 MB = 4 MB */ - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; - break; /* 4 * 1 MB = 4 MB */ - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00800000; - break; /* 4 * 2 MB = 8 MB */ - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00800000; - break; /* 4 * 2 MB = 8 MB */ - case AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x02000000; - break; /* 4 * 8 MB = 32 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* no or unknown flash */ - } - } - - if (flashtest_h == AMD_ID_LV640U) { - - /* set up sector start adress table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = baseaddr + (i * 0x00040000); - - } else if (info->flash_id & FLASH_BTYPE) { - - /* set up sector start adress table (bottom sector type) */ - info->start[0] = baseaddr + 0x00000000; - info->start[1] = baseaddr + 0x00010000; - info->start[2] = baseaddr + 0x00018000; - info->start[3] = baseaddr + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000; - } - - } else { - - /* set up sector start adress table (top sector type) */ - i = info->sector_count - 1; - info->start[i--] = baseaddr + info->size - 0x00010000; - info->start[i--] = baseaddr + info->size - 0x00018000; - info->start[i--] = baseaddr + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = baseaddr + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - if ((V_ULONG (info->start[i] + 16) & 0x00010001) || - (V_ULONG (info->start[i] + 20) & 0x00010001)) { - info->protect[i] = 1; /* D0 = 1 if protected */ - } else { - info->protect[i] = 0; - } - } - - flash_reset (); - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* - * protect monitor and environment sectors - */ - -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - printf ("29LV800T (8 M, top sector)\n"); - break; - case FLASH_AM800B: - printf ("29LV800T (8 M, bottom sector)\n"); - break; - case FLASH_AM160T: - printf ("29LV160T (16 M, top sector)\n"); - break; - case FLASH_AM160B: - printf ("29LV160B (16 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: - printf ("29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: - printf ("29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: - printf ("29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: - printf ("29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AM640U: - printf ("29LV640D (64 M, uniform sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - V_ULONG (info->start[sect]) = 0x00300030; - V_ULONG (info->start[sect] + 4) = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 || - (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080) - { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - flash_reset (); - - printf (" done\n"); - return 0; -} - -static int write_dword (flash_info_t *, ulong, unsigned char *); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong dp; - static unsigned char bb[8]; - int i, l, rc, cc = cnt; - - dp = (addr & ~7); /* get lower dword aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - dp) != 0) { - for (i = 0; i < 8; i++) - bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++; - if ((rc = write_dword (info, dp, bb)) != 0) { - return (rc); - } - dp += 8; - cc -= 8 - l; - } - - /* - * handle word aligned part - */ - while (cc >= 8) { - if ((rc = write_dword (info, dp, src)) != 0) { - return (rc); - } - dp += 8; - src += 8; - cc -= 8; - } - - if (cc <= 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - for (i = 0; i < 8; i++) { - bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i); - } - return (write_dword (info, dp, bb)); -} - -/*----------------------------------------------------------------------- - * Write a dword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) -{ - ulong start, cl, ch; - int flag, i; - - for (ch = 0, i = 0; i < 4; i++) - ch = (ch << 8) + *pdata++; /* high word */ - for (cl = 0, i = 0; i < 4; i++) - cl = (cl << 8) + *pdata++; /* low word */ - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & ch) != ch - || (*((vu_long *) (dest + 4)) & cl) != cl) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0; - V_ULONG (dest) = ch; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0; - V_ULONG (dest + 4) = cl; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) || - ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/siemens/SCM/fpga_scm.c b/board/siemens/SCM/fpga_scm.c deleted file mode 100644 index 661bf66..0000000 --- a/board/siemens/SCM/fpga_scm.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include "../common/fpga.h" - -fpga_t fpga_list[] = { - {"FIOX", CFG_FIOX_BASE, - CFG_PD_FIOX_INIT, CFG_PD_FIOX_PROG, CFG_PD_FIOX_DONE} - , - {"FDOHM", CFG_FDOHM_BASE, - CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE} -}; -int fpga_count = sizeof (fpga_list) / sizeof (fpga_t); - - -ulong fpga_control (fpga_t * fpga, int cmd) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - switch (cmd) { - case FPGA_INIT_IS_HIGH: - immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */ - return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0; - - case FPGA_INIT_SET_LOW: - immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pdatd &= ~fpga->init_mask; - break; - - case FPGA_INIT_SET_HIGH: - immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pdatd |= fpga->init_mask; - break; - - case FPGA_PROG_SET_LOW: - immr->im_ioport.iop_pdatd &= ~fpga->prog_mask; - break; - - case FPGA_PROG_SET_HIGH: - immr->im_ioport.iop_pdatd |= fpga->prog_mask; - break; - - case FPGA_DONE_IS_HIGH: - return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0; - - case FPGA_READ_MODE: - break; - - case FPGA_LOAD_MODE: - break; - - case FPGA_GET_ID: - if (fpga->conf_base == CFG_FIOX_BASE) { - ulong ver = - *(volatile ulong *) (fpga->conf_base + 0x10); - return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0); - } else if (fpga->conf_base == CFG_FDOHM_BASE) { - return (*(volatile ushort *) fpga->conf_base) & 0xff; - } else { - return *(volatile ulong *) fpga->conf_base; - } - - case FPGA_INIT_PORTS: - immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */ - immr->im_ioport.iop_psord &= ~fpga->init_mask; - immr->im_ioport.iop_pdird &= ~fpga->init_mask; - - immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */ - immr->im_ioport.iop_psord &= ~fpga->prog_mask; - immr->im_ioport.iop_pdird |= fpga->prog_mask; - - immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */ - immr->im_ioport.iop_psord &= ~fpga->done_mask; - immr->im_ioport.iop_pdird &= ~fpga->done_mask; - - break; - - } - return 0; -} diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c deleted file mode 100644 index d20688d..0000000 --- a/board/siemens/SCM/scm.c +++ /dev/null @@ -1,540 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "scm.h" - -static void config_scoh_cs(void); -extern int fpga_init(void); - -#if 0 -#define DEBUGF(fmt,args...) printf (fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1]*/ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, - /* PA9 */ { 1, 1, 1, 1, 0, 0 }, /* TDM_A1 L1TXD0 */ - /* PA8 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RXD0 */ - /* PA7 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1TSYNC */ - /* PA6 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RSYNC */ - /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* FIOX_FPGA_PR */ - /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* DOHM_FPGA_PR */ - /* PA3 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK4 */ - /* PA2 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK4 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, - /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* BUSY */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MIN */ - /* PB30 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MAJ */ - /* PB29 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MIN */ - /* PB28 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MAJ */ - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, - /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* LED_GREEN_L */ - /* PB24 */ { 1, 0, 0, 1, 0, 0 }, /* LED_RED_L */ - /* PB23 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TXD */ - /* PB22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RXD */ - /* PB21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TSYNC */ - /* PB20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RSYNC */ - /* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* UID */ - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK1 */ - /* PC30 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK1 */ - /* PC29 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK3 */ - /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK3 */ - /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK2 */ - /* PC26 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK2 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ - /* PC19 */ { 0, 1, 0, 0, 0, 0 }, - /* PC18 */ { 0, 1, 0, 0, 0, 0 }, - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, - /* PC9 */ { 0, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* FEP_RDY */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* RES_MISC_L */ - /* PC2 */ { 0, 0, 0, 1, 0, 0 }, /* RES_OH_L */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */ - }, - - /* Port D configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_F */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_F */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_D */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_D */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, - /* PD22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TXD */ - /* PD21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RXD */ - /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */ - /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPISEL */ - /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPICLK */ - /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSI */ - /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSO */ -#if defined(CONFIG_SOFT_I2C) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TXD */ - /* PD12 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RXD */ - /* PD11 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TSYNC */ - /* PD10 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RSYNC */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, - /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_F */ - /* PD4 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_D */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (!i || strncmp (str, "TQM8260", 7)) { - puts ("### No HW ID - assuming TQM8260\n"); - return (0); - } - - puts (str); - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; - orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -/* - * Test Power-On-Reset. - */ -int power_on_reset (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Test Reset Status Register */ - return gd->reset_status & RSR_CSRS ? 0 : 1; -} - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CFG_RAMBOOT - long size8, size9; -#endif - long psize, lsize; - - psize = 16 * 1024 * 1024; - lsize = 0; - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - -#if 0 /* Just for debugging */ -#define prt_br_or(brX,orX) do { \ - ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ - ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ - printf ("\n" \ - #brX " 0x%08x " #orX " 0x%08x " \ - "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ - memctl->memc_ ## brX, memctl->memc_ ## orX, \ - start, start+sizem, (sizem+1)>>20); \ - } while (0) - prt_br_or (br0, or0); - prt_br_or (br1, or1); - prt_br_or (br2, or2); - prt_br_or (br3, or3); -#endif - -#ifndef CFG_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, - (uchar *) CFG_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL - %ld MB, ", psize >> 20); - } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); - printf ("(60x:8COL - %ld MB, ", psize >> 20); - } - - /* Local SDRAM setup: - */ -#ifdef CFG_INIT_LOCAL_SDRAM - memctl->memc_lsrt = CFG_LSRT; - size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL, - (uchar *) SDRAM_BASE2_PRELIM); - - if (size8 < size9) { - lsize = size9; - printf ("Local:9COL - %ld MB) using ", lsize >> 20); - } else { - lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - printf ("Local:8COL - %ld MB) using ", lsize >> 20); - } - -#if 0 - /* Set up BR2 so that the local SDRAM goes - * right after the 60x SDRAM - */ - memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) | - (CFG_SDRAM_BASE + psize); -#endif -#endif /* CFG_INIT_LOCAL_SDRAM */ -#endif /* CFG_RAMBOOT */ - - icache_enable (); - - config_scoh_cs (); - - return (psize); -} - -/* ------------------------------------------------------------------------- */ - -static void config_scoh_cs (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE; - volatile uint tmp, i; - - /* Initialize OR3 / BR3 for CAN Bus Controller 0 */ - memctl->memc_or3 = CFG_CAN0_OR3; - memctl->memc_br3 = CFG_CAN0_BR3; - /* Initialize OR4 / BR4 for CAN Bus Controller 1 */ - memctl->memc_or4 = CFG_CAN1_OR4; - memctl->memc_br4 = CFG_CAN1_BR4; - - /* Initialize MAMR to write in the array at address 0x0 */ - memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS; - - /* Initialize UPMA for CAN: single read */ - memctl->memc_mdr = 0xcffeec00; - udelay (1); /* Necessary to have the data correct in the UPM array!!!! */ - /* The read on the CAN controller write the data of mdr in UPMA array. */ - /* The index to the array will be incremented automatically - through this read */ - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcfc00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcfc00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0xfffdec07; - udelay (1); - tmp = can->cpu_interface; - - - /* Initialize MAMR to write in the array at address 0x18 */ - memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS; - - /* Initialize UPMA for CAN: single write */ - memctl->memc_mdr = 0xfcffec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00ffec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00ffec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00ffec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00ffec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00fffc00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00fffc00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x30ffec07; - udelay (1); - tmp = can->cpu_interface; - - /* Initialize MAMR */ - memctl->memc_mamr = MxMR_GPL_x4DIS; /* GPL_B4 ouput line Disable */ - - - /* Initialize OR5 / BR5 for the extended EEPROM Bank0 */ - memctl->memc_or5 = CFG_EXTPROM_OR5; - memctl->memc_br5 = CFG_EXTPROM_BR5; - /* Initialize OR6 / BR6 for the extended EEPROM Bank1 */ - memctl->memc_or6 = CFG_EXTPROM_OR6; - memctl->memc_br6 = CFG_EXTPROM_BR6; - - /* Initialize OR7 / BR7 for the Glue Logic */ - memctl->memc_or7 = CFG_FIOX_OR7; - memctl->memc_br7 = CFG_FIOX_BR7; - - /* Initialize OR8 / BR8 for the DOH Logic */ - memctl->memc_or8 = CFG_FDOHM_OR8; - memctl->memc_br8 = CFG_FDOHM_BR8; - - DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0); - DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1); - DEBUGF ("OR2 %08x BR2 %08x\n", memctl->memc_or2, memctl->memc_br2); - DEBUGF ("OR3 %08x BR3 %08x\n", memctl->memc_or3, memctl->memc_br3); - DEBUGF ("OR4 %08x BR4 %08x\n", memctl->memc_or4, memctl->memc_br4); - DEBUGF ("OR5 %08x BR5 %08x\n", memctl->memc_or5, memctl->memc_br5); - DEBUGF ("OR6 %08x BR6 %08x\n", memctl->memc_or6, memctl->memc_br6); - DEBUGF ("OR7 %08x BR7 %08x\n", memctl->memc_or7, memctl->memc_br7); - DEBUGF ("OR8 %08x BR8 %08x\n", memctl->memc_or8, memctl->memc_br8); - - DEBUGF ("UPMA addr 0x0\n"); - memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS; - for (i = 0; i < 0x8; i++) { - tmp = can->cpu_interface; - udelay (1); - DEBUGF (" %08x ", memctl->memc_mdr); - } - DEBUGF ("\nUPMA addr 0x18\n"); - memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS; - for (i = 0; i < 0x8; i++) { - tmp = can->cpu_interface; - udelay (1); - DEBUGF (" %08x ", memctl->memc_mdr); - } - DEBUGF ("\n"); - memctl->memc_mamr = MxMR_GPL_x4DIS; -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r (void) -{ - fpga_init (); - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/SCM/scm.h b/board/siemens/SCM/scm.h deleted file mode 100644 index 70c12e6..0000000 --- a/board/siemens/SCM/scm.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SCM_H -#define __SCM_H - -/*----------------*/ -/* CAN Structures */ -/*----------------*/ - -/* Message */ -typedef struct can_msg { - uchar ctrl_0; - uchar ctrl_1; - uchar arbit_0; - uchar arbit_1; - uchar arbit_2; - uchar arbit_3; - uchar config; - uchar data[8]; -} can_msg_t; - -/* CAN Register */ -typedef struct can_reg { - uchar ctrl; - uchar status; - uchar cpu_interface; - uchar resv0; - ushort high_speed_rd; - ushort gbl_mask_std; - uint gbl_mask_extd; - uint msg15_mask; - can_msg_t msg1 __attribute__ ((packed)); - uchar clkout; - can_msg_t msg2 __attribute__ ((packed)); - uchar bus_config; - can_msg_t msg3 __attribute__ ((packed)); - uchar bit_timing_0; - can_msg_t msg4 __attribute__ ((packed)); - uchar bit_timing_1; - can_msg_t msg5 __attribute__ ((packed)); - uchar interrupt; - can_msg_t msg6 __attribute__ ((packed)); - uchar resv1; - can_msg_t msg7 __attribute__ ((packed)); - uchar resv2; - can_msg_t msg8 __attribute__ ((packed)); - uchar resv3; - can_msg_t msg9 __attribute__ ((packed)); - uchar p1conf; - can_msg_t msg10 __attribute__ ((packed)); - uchar p2conf; - can_msg_t msg11 __attribute__ ((packed)); - uchar p1in; - can_msg_t msg12 __attribute__ ((packed)); - uchar p2in; - can_msg_t msg13 __attribute__ ((packed)); - uchar p1out; - can_msg_t msg14 __attribute__ ((packed)); - uchar p2out; - can_msg_t msg15 __attribute__ ((packed)); - uchar ser_res_addr; - uchar resv_cs[0x8000-0x100]; /* 0x8000 is the min size for CS */ -} can_reg_t; - - -#endif /* __SCM_H */ diff --git a/board/siemens/SCM/u-boot.lds b/board/siemens/SCM/u-boot.lds deleted file mode 100644 index 05f29c6..0000000 --- a/board/siemens/SCM/u-boot.lds +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - common/environment.o(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/common/README b/board/siemens/common/README deleted file mode 100644 index 7f1c8cd..0000000 --- a/board/siemens/common/README +++ /dev/null @@ -1,27 +0,0 @@ -CCM/SCM-Ergaenzungen fuer U-Boot und Linux: -------------------------------------------- - -Es gibt nun ein gemeinsames Kommando zum Laden der FPGAs: - - => help fpga - fpga fpga status [name] - print FPGA status - fpga reset [name] - reset FPGA - fpga load [name] addr - load FPGA configuration data - -Der Name kann beim CCM-Module auch weggelassen werden. -Die Laengenangabe und damit "puma_len" ist nicht mehr -noetig: - - => fpga load puma 40600000 - FPGA load PUMA: addr 40600000: (00000005)... done - -Die MTD-Partitionierung kann nun mittels "bootargs" ueber- -geben werden: - - => printenv addmtd - addmtd=setenv bootargs ${bootargs} - mtdparts=0:256k(U-Boot)ro,768k(Kernel),-(Rest)\;1:-(myJFFS2) - -Die Portierung auf SMC ist natuerlich noch nicht getestet. - -Wolfgang Grandegger (04.06.2002) diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c deleted file mode 100644 index e9941cd..0000000 --- a/board/siemens/common/fpga.c +++ /dev/null @@ -1,364 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include - -#include "fpga.h" - -int power_on_reset(void); - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - - -static int fpga_get_version(fpga_t* fpga, char* name) -{ - char vname[12]; - /* - * Net-list string format: - * "vvvvvvvvddddddddn...". - * Version Date Name - * "0000000322042002PUMA" = PUMA version 3 from 22.04.2002. - */ - if (strlen(name) < (16 + strlen(fpga->name))) - goto failure; - /* Check FPGA name */ - if (strcmp(&name[16], fpga->name) != 0) - goto failure; - /* Get version number */ - memcpy(vname, name, 8); - vname[8] = '\0'; - return simple_strtoul(vname, NULL, 16); - - failure: - printf("Image name %s is invalid\n", name); - return -1; -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static fpga_t* fpga_get(char* fpga_name) -{ - char name[FPGA_NAME_LEN]; - int i; - - if (strlen(fpga_name) >= FPGA_NAME_LEN) - goto failure; - for (i = 0; i < strlen(fpga_name); i++) - name[i] = toupper(fpga_name[i]); - name[i] = '\0'; - for (i = 0; i < fpga_count; i++) { - if (strcmp(name, fpga_list[i].name) == 0) - return &fpga_list[i]; - } - failure: - printf("FPGA: name %s is invalid\n", fpga_name); - return NULL; -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static void fpga_status (fpga_t* fpga) -{ - /* Check state */ - if (fpga_control(fpga, FPGA_DONE_IS_HIGH)) - printf ("%s is loaded (%08lx)\n", - fpga->name, fpga_control(fpga, FPGA_GET_ID)); - else - printf ("%s is NOT loaded\n", fpga->name); -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -#define FPGA_RESET_TIMEOUT 100 /* = 10 ms */ - -static int fpga_reset (fpga_t* fpga) -{ - int i; - - /* Set PROG to low and wait til INIT goes low */ - fpga_control(fpga, FPGA_PROG_SET_LOW); - for (i = 0; i < FPGA_RESET_TIMEOUT; i++) { - udelay (100); - if (!fpga_control(fpga, FPGA_INIT_IS_HIGH)) - break; - } - if (i == FPGA_RESET_TIMEOUT) - goto failure; - - /* Set PROG to high and wait til INIT goes high */ - fpga_control(fpga, FPGA_PROG_SET_HIGH); - for (i = 0; i < FPGA_RESET_TIMEOUT; i++) { - udelay (100); - if (fpga_control(fpga, FPGA_INIT_IS_HIGH)) - break; - } - if (i == FPGA_RESET_TIMEOUT) - goto failure; - - return 0; - failure: - return 1; -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */ - -static int fpga_load (fpga_t* fpga, ulong addr, int checkall) -{ - volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base; - image_header_t hdr; - ulong len, checksum; - uchar *data = (uchar *)&hdr; - char *s, msg[32]; - int verify, i; - - /* - * Check the image header and data of the net-list - */ - memcpy (&hdr, (char *)addr, sizeof(image_header_t)); - - if (hdr.ih_magic != IH_MAGIC) { - strcpy (msg, "Bad Image Magic Number"); - goto failure; - } - - len = sizeof(image_header_t); - - checksum = hdr.ih_hcrc; - hdr.ih_hcrc = 0; - - if (crc32 (0, data, len) != checksum) { - strcpy (msg, "Bad Image Header CRC"); - goto failure; - } - - data = (uchar*)(addr + sizeof(image_header_t)); - len = hdr.ih_size; - - s = getenv ("verify"); - verify = (s && (*s == 'n')) ? 0 : 1; - if (verify) { - if (crc32 (0, data, len) != hdr.ih_dcrc) { - strcpy (msg, "Bad Image Data CRC"); - goto failure; - } - } - - if (checkall && fpga_get_version(fpga, (char *)(hdr.ih_name)) < 0) - return 1; - - /* align length */ - if (len & 1) - ++len; - - /* - * Reset FPGA and wait for completion - */ - if (fpga_reset(fpga)) { - strcpy (msg, "Reset Timeout"); - goto failure; - } - - printf ("(%s)... ", hdr.ih_name); - /* - * Copy data to FPGA - */ - fpga_control (fpga, FPGA_LOAD_MODE); - while (len--) { - *fpga_addr = *data++; - } - fpga_control (fpga, FPGA_READ_MODE); - - /* - * Wait for completion and check error status if timeout - */ - for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) { - udelay (100); - if (fpga_control (fpga, FPGA_DONE_IS_HIGH)) - break; - } - if (i == FPGA_LOAD_TIMEOUT) { - if (fpga_control(fpga, FPGA_INIT_IS_HIGH)) - strcpy(msg, "Invalid Size"); - else - strcpy(msg, "CRC Error"); - goto failure; - } - - printf("done\n"); - return 0; - - failure: - - printf("ERROR: %s\n", msg); - return 1; -} - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr = 0; - int i; - fpga_t* fpga; - - if (argc < 2) - goto failure; - - if (strncmp(argv[1], "stat", 4) == 0) { /* status */ - if (argc == 2) { - for (i = 0; i < fpga_count; i++) { - fpga_status (&fpga_list[i]); - } - } - else if (argc == 3) { - if ((fpga = fpga_get(argv[2])) == 0) - goto failure; - fpga_status (fpga); - } - else - goto failure; - } - else if (strcmp(argv[1],"load") == 0) { /* load */ - if (argc == 3 && fpga_count == 1) { - fpga = &fpga_list[0]; - } - else if (argc == 4) { - if ((fpga = fpga_get(argv[2])) == 0) - goto failure; - } - else - goto failure; - - addr = simple_strtoul(argv[argc-1], NULL, 16); - - printf ("FPGA load %s: addr %08lx: ", - fpga->name, addr); - fpga_load (fpga, addr, 1); - - } - else if (strncmp(argv[1], "rese", 4) == 0) { /* reset */ - if (argc == 2 && fpga_count == 1) { - fpga = &fpga_list[0]; - } - else if (argc == 3) { - if ((fpga = fpga_get(argv[2])) == 0) - goto failure; - } - else - goto failure; - - printf ("FPGA reset %s: ", fpga->name); - if (fpga_reset(fpga)) - printf ("ERROR: Timeout\n"); - else - printf ("done\n"); - } - else - goto failure; - - return 0; - - failure: - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD( - fpga, 4, 1, do_fpga, - "fpga - access FPGA(s)\n", - "fpga status [name] - print FPGA status\n" - "fpga reset [name] - reset FPGA\n" - "fpga load [name] addr - load FPGA configuration data\n" -); - -#endif /* CONFIG_COMMANDS & CFG_CMD_BSP */ - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -int fpga_init (void) -{ - ulong addr; - ulong new_id, old_id = 0; - image_header_t *hdr; - fpga_t* fpga; - int do_load, i, j; - char name[16], *s; - - /* - * Port setup for FPGA control - */ - for (i = 0; i < fpga_count; i++) { - fpga_control(&fpga_list[i], FPGA_INIT_PORTS); - } - - /* - * Load FPGA(s): a new net-list is loaded if the FPGA is - * empty, Power-on-Reset or the old one is not up-to-date - */ - for (i = 0; i < fpga_count; i++) { - fpga = &fpga_list[i]; - printf ("%s: ", fpga->name); - - for (j = 0; j < strlen(fpga->name); j++) - name[j] = tolower(fpga->name[j]); - name[j] = '\0'; - sprintf(name, "%s_addr", name); - addr = 0; - if ((s = getenv(name)) != NULL) - addr = simple_strtoul(s, NULL, 16); - - if (!addr) { - printf ("env. variable %s undefined\n", name); - return 1; - } - - hdr = (image_header_t *)addr; - if ((new_id = fpga_get_version(fpga, (char *)(hdr->ih_name))) == -1) - return 1; - - do_load = 1; - - if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) { - old_id = fpga_control(fpga, FPGA_GET_ID); - if (new_id == old_id) - do_load = 0; - } - - if (do_load) { - printf ("loading "); - fpga_load (fpga, addr, 0); - } else { - printf ("loaded (%08lx)\n", old_id); - } - } - - return 0; -} diff --git a/board/siemens/common/fpga.h b/board/siemens/common/fpga.h deleted file mode 100644 index 2de25b0..0000000 --- a/board/siemens/common/fpga.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#ifndef _FPGA_H_ -#define _FPGA_H_ - -#define FPGA_INIT_IS_HIGH 0 -#define FPGA_INIT_SET_HIGH 1 -#define FPGA_INIT_SET_LOW 2 -#define FPGA_PROG_SET_HIGH 3 -#define FPGA_PROG_SET_LOW 4 -#define FPGA_DONE_IS_HIGH 5 -#define FPGA_READ_MODE 6 -#define FPGA_LOAD_MODE 7 -#define FPGA_GET_ID 8 -#define FPGA_INIT_PORTS 9 - -#define FPGA_NAME_LEN 8 -typedef struct { - char name[FPGA_NAME_LEN]; - ulong conf_base; - uint init_mask; - uint prog_mask; - uint done_mask; -} fpga_t; - -extern fpga_t fpga_list[]; -extern int fpga_count; - -ulong fpga_control (fpga_t* fpga, int cmd); - -#endif /* _FPGA_H_ */ diff --git a/board/siemens/pcu_e/Makefile b/board/siemens/pcu_e/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/siemens/pcu_e/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/siemens/pcu_e/config.mk b/board/siemens/pcu_e/config.mk deleted file mode 100644 index 10f3773..0000000 --- a/board/siemens/pcu_e/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Siemens PCU E Boards -# - -TEXT_BASE = 0xFFF00000 diff --git a/board/siemens/pcu_e/flash.c b/board/siemens/pcu_e/flash.c deleted file mode 100644 index 05c364b..0000000 --- a/board/siemens/pcu_e/flash.c +++ /dev/null @@ -1,700 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - * - * The PCU E uses an address map where flash banks are aligned top - * down, so that the "first" flash bank ends at top of memory, and - * the monitor entry point is at address (0xFFF00100). The second - * flash bank is mapped immediately below bank 0. - * - * This is NOT in conformance to the "official" memory map! - * - */ - -#define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \ - - (0xFFFFFFFF - CFG_MONITOR_BASE) ) - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long base, size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - DEBUGF ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR6: 0x%08x OR6: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br6, memctl->memc_or6); - - /* Remap FLASH according to real size */ - base = 0 - size_b0; - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)base, &flash_info[0]); - base = 0 - size_b0; - - flash_info[0].size = size_b0; - - flash_get_offsets (base, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - PCU_MONITOR_BASE, - PCU_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - flash_info_t tmp_info; - - memctl->memc_or6 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) | - BR_PS_16 | BR_MS_GPCM | BR_V; - - DEBUGF("## New BR6: 0x%08x OR6: 0x%08x\n", - memctl->memc_br6, memctl->memc_or6); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(base - size_b1), - &flash_info[1]); - base -= size_b1; - - flash_get_offsets (base, &flash_info[1]); - - flash_info[1].size = size_b1; - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - /* - * Swap bank numbers so that addresses are in ascending order - */ - tmp_info = flash_info[0]; - flash_info[0] = flash_info[1]; - flash_info[1] = tmp_info; - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - short n; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) { - return; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL322T: - case FLASH_AMDL323T: - case FLASH_AMDL324T: - /* set sector offsets for top boot block type */ - - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - return; - case FLASH_AMDL322B: - case FLASH_AMDL323B: - case FLASH_AMDL324B: - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (base < info->size) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - return; - case FLASH_AMDL640: - /* set sector offsets for dual boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - n = info->sector_count - 8; - while (i < n) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - while (i < info->sector_count) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - ++i; - } - return; - default: - return; - } - /* NOTREACHED */ -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL322B: printf ("AM29DL322B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL323T: printf ("AM29DL323T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL324B: printf ("AM29DL324B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL640: printf ("AM29DL640D (64 Mbit, dual boot sector)\n"); - break; - default: printf ("Unknown Chip Type 0x%lX\n", - info->flash_id); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ushort value; - vu_short *saddr = (vu_short *)addr; - - /* Write auto select command: read Manufacturer ID */ - saddr[0x0555] = 0x00AA; - saddr[0x02AA] = 0x0055; - saddr[0x0555] = 0x0090; - - value = saddr[0]; - - DEBUGF("Manuf. ID @ 0x%08lx: 0x%04x\n", (ulong)addr, value); - - switch (value) { - case (AMD_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_FUJ; - break; - default: - DEBUGF("Unknown Manufacturer ID\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = saddr[1]; /* device ID */ - - DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value); - - switch (value) { - - case (AMD_ID_DL322T & 0xFFFF): - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL322B & 0xFFFF): - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL323T & 0xFFFF): - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL323B & 0xFFFF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL324T & 0xFFFF): - info->flash_id += FLASH_AMDL324T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL324B & 0xFFFF): - info->flash_id += FLASH_AMDL324B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - case (AMD_ID_DL640 & 0xFFFF): - info->flash_id += FLASH_AMDL640; - info->sector_count = 142; - info->size = 0x00800000; - break; - default: - DEBUGF("Unknown Device ID\n"); - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets ((ulong)addr, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { -#if 0 - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - saddr = (vu_short *)(info->start[i]); - info->protect[i] = saddr[2] & 1; -#else - info->protect[i] =0; -#endif - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - saddr = (vu_short *)info->start[0]; - *saddr = 0x00F0; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short*)(info->start[sect]); - addr[0] = 0x0030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_short*)(info->start[l_sect]); - while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -#define FLASH_WIDTH 2 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= FLASH_WIDTH) { - data = 0; - for (i=0; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; istart[0]); - vu_short *sdest = (vu_short *)dest; - ushort sdata = (ushort)data; - ushort sval; - ulong start, passed; - int flag, rc; - - /* Check if Flash is (sufficiently) erased */ - if ((*sdest & sdata) != sdata) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - -#ifdef WORKAROUND_FOR_BROKEN_HARDWARE - /* work around the timeout bugs */ - udelay(20); -#endif - - *sdest = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - rc = 0; - /* data polling for D7 */ - start = get_timer (0); - - for (passed=0; passed < CFG_FLASH_WRITE_TOUT; passed=get_timer(start)) { - - sval = *sdest; - - if ((sval & 0x0080) == (sdata & 0x0080)) - break; - - if ((sval & 0x0020) == 0) /* DQ5: Timeout? */ - continue; - - sval = *sdest; - - if ((sval & 0x0080) != (sdata & 0x0080)) - rc = 1; - - break; - } - - if (rc) { - DEBUGF ("Program cycle failed @ addr 0x%08lX: val %04X data %04X\n", - dest, sval, sdata); - } - - if (passed >= CFG_FLASH_WRITE_TOUT) { - DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n", - dest, sval, sdata); - rc = 1; - } - - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - - return (rc); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c deleted file mode 100644 index 3f05e4a..0000000 --- a/board/siemens/pcu_e/pcu_e.c +++ /dev/null @@ -1,563 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static void puma_status (void); -static void puma_set_mode (int mode); -static int puma_init_done (void); -static void puma_load (ulong addr, ulong len); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -/* - * 50 MHz SDRAM access using UPM A - */ -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00, - 0x1ffddc47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00, - 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - -/* - * PUMA access using UPM B - */ -const uint puma_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - /* - * Precharge and MRS - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ - puts ("Board: Siemens PCU E\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - long int size_b0, reg; - int i; - - /* - * Configure UPMA for SDRAM - */ - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = CFG_MPTPR; - - /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 2 to the SDRAM bank at preliminary address. - */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or5 = CFG_OR5_PRELIM; - memctl->memc_br5 = CFG_BR5_PRELIM; -#else /* XXX */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; -#endif /* XXX */ - - /* initialize memory address register */ - memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */ - - /* mode initialization (offset 5) */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (200); /* 0x8000A105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05); -#else /* XXX */ - udelay (200); /* 0x80004105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05); -#endif /* XXX */ - - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (1); /* 0x8000A830 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30); -#else /* XXX */ - udelay (1); /* 0x80004830 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30); -#endif /* XXX */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (1); /* 0x8000A106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06); -#else /* XXX */ - udelay (1); /* 0x80004106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06); -#endif /* XXX */ - - reg = memctl->memc_mamr; - reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */ - reg |= MAMR_TLFA_4X; /* ... to 4x */ - reg |= MAMR_PTAE; /* enable refresh */ - memctl->memc_mamr = reg; - - udelay (200); - - /* Need at least 10 DRAM accesses to stabilize */ - for (i = 0; i < 10; ++i) { -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE5_PRELIM; -#else /* XXX */ - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE2_PRELIM; -#endif /* XXX */ - unsigned long val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* - * Check Bank 0 Memory Size for re-configuration - */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); -#else /* XXX */ - size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); -#endif /* XXX */ - - memctl->memc_mamr = CFG_MAMR | MAMR_PTAE; - - /* - * Final mapping: - */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; -#else /* XXX */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; -#endif /* XXX */ - udelay (1000); - - /* - * Configure UPMB for PUMA - */ - upmconfig (UPMB, (uint *) puma_table, - sizeof (puma_table) / sizeof (uint)); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) -#else /* XXX */ -#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \ - CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) -#endif /* XXX */ - -#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET) - -void reset_phy (void) -{ - immap_t *immr = (immap_t *) CFG_IMMR; - ulong value; - - /* Configure all needed port pins for GPIO */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -# ifdef CFG_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS; -# else - immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */ -# endif - immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */ - immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */ -#endif /* XXX */ - immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ - - value = immr->im_cpm.cp_pbdat; - - /* Assert Powerdown and Reset signals */ - value |= CFG_PB_ETH_POWERDOWN; - value &= ~(CFG_PB_ETH_RESET); - - /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ -#if !PCU_E_WITH_SWAPPED_CS -# ifdef CFG_ETH_MDDIS_VALUE - value |= CFG_PB_ETH_MDDIS; -# else - value &= ~(CFG_PB_ETH_MDDIS); -# endif -#endif -#ifdef CFG_ETH_CFG1_VALUE - value |= CFG_PB_ETH_CFG1; -#else - value &= ~(CFG_PB_ETH_CFG1); -#endif -#ifdef CFG_ETH_CFG2_VALUE - value |= CFG_PB_ETH_CFG2; -#else - value &= ~(CFG_PB_ETH_CFG2); -#endif -#ifdef CFG_ETH_CFG3_VALUE - value |= CFG_PB_ETH_CFG3; -#else - value &= ~(CFG_PB_ETH_CFG3); -#endif - - /* Drive output signals to initial state */ - immr->im_cpm.cp_pbdat = value; - immr->im_cpm.cp_pbdir |= ETH_ALL_BITS; - udelay (10000); - - /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ - udelay (10000); - - /* de-assert RESET signal of PHY */ - immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET; - udelay (1000); -} - -/*----------------------------------------------------------------------- - * Board Special Commands: access functions for "PUMA" FPGA - */ -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -#define PUMA_READ_MODE 0 -#define PUMA_LOAD_MODE 1 - -int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr, len; - - switch (argc) { - case 2: /* PUMA reset */ - if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */ - puma_status (); - return 0; - } - break; - case 4: /* PUMA load addr len */ - if (strcmp (argv[1], "load") != 0) - break; - - addr = simple_strtoul (argv[2], NULL, 16); - len = simple_strtoul (argv[3], NULL, 16); - - printf ("PUMA load: addr %08lX len %ld (0x%lX): ", - addr, len, len); - puma_load (addr, len); - - return 0; - default: - break; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD (puma, 4, 1, do_puma, - "puma - access PUMA FPGA\n", - "status - print PUMA status\n" - "puma load addr len - load PUMA configuration data\n"); - -#endif /* CFG_CMD_BSP */ - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static void puma_set_mode (int mode) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - /* disable PUMA in memory controller */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_br3 = 0; -#else /* XXX */ - memctl->memc_br4 = 0; -#endif /* XXX */ - - switch (mode) { - case PUMA_READ_MODE: -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or3 = PUMA_CONF_OR_READ; - memctl->memc_br3 = PUMA_CONF_BR_READ; -#else /* XXX */ - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; -#endif /* XXX */ - break; - case PUMA_LOAD_MODE: -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or3 = PUMA_CONF_OR_LOAD; - memctl->memc_br3 = PUMA_CONF_BR_LOAD; -#else /* XXX */ - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; -#endif /* XXX */ - break; - } -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */ - -static void puma_load (ulong addr, ulong len) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */ - uchar *data = (uchar *) addr; - int i; - - /* align length */ - if (len & 1) - ++len; - - /* Reset FPGA */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */ - immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT); - immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT); - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */ - immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */ -#else - immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */ - immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */ - immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */ - immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */ -#endif /* XXX */ - udelay (100); - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */ -#else - immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */ -#endif /* XXX */ - - /* wait until INIT indicates completion of reset */ - for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) { - udelay (1000); - if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT) - break; - } - if (i == PUMA_INIT_TIMEOUT) { - printf ("*** PUMA init timeout ***\n"); - return; - } - - puma_set_mode (PUMA_LOAD_MODE); - - while (len--) - *fpga_addr = *data++; - - puma_set_mode (PUMA_READ_MODE); - - puma_status (); -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static void puma_status (void) -{ - /* Check state */ - printf ("PUMA initialization is %scomplete\n", - puma_init_done ()? "" : "NOT "); -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static int puma_init_done (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - /* make sure pin is GPIO input */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE); - immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE); - immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE); - - return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0; -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r (void) -{ - ulong addr = 0; - ulong len = 0; - char *s; - - printf ("PUMA: "); - if (puma_init_done ()) { - printf ("initialized\n"); - return 0; - } - - if ((s = getenv ("puma_addr")) != NULL) - addr = simple_strtoul (s, NULL, 16); - - if ((s = getenv ("puma_len")) != NULL) - len = simple_strtoul (s, NULL, 16); - - if ((!addr) || (!len)) { - printf ("net list undefined\n"); - return 0; - } - - printf ("loading... "); - - puma_load (addr, len); - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds deleted file mode 100644 index 6505d45..0000000 --- a/board/siemens/pcu_e/u-boot.lds +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - common/environment.o(.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug deleted file mode 100644 index 828afbb..0000000 --- a/board/siemens/pcu_e/u-boot.lds.debug +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sixnet/Makefile b/board/sixnet/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/sixnet/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/sixnet/config.mk b/board/sixnet/config.mk deleted file mode 100644 index 0cd8f44..0000000 --- a/board/sixnet/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# SIXNET boards -# - -TEXT_BASE = 0xF8000000 diff --git a/board/sixnet/flash.c b/board/sixnet/flash.c deleted file mode 100644 index 61d7580..0000000 --- a/board/sixnet/flash.c +++ /dev/null @@ -1,790 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -/* environment.h defines the various CFG_ENV_... values in terms - * of whichever ones are given in the configuration file. - */ -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -#ifdef CFG_FLASH_PROTECTION -static void flash_sync_real_protect(flash_info_t *info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b; - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",size_b); - } - - /* Remap FLASH according to real size, so only at proper address */ - memctl->memc_or0 = (memctl->memc_or0 & ~OR_AM_MSK) | ORMASK(size_b); - - /* Do this again (was done already in flast_get_size), just - * in case we move it when remap the FLASH. - */ - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#ifdef CFG_FLASH_PROTECTION - /* read the hardware protection status (if any) into the - * protection array in flash_info. - */ - flash_sync_real_protect(&flash_info[0]); -#endif - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_ADDR - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - -#ifdef CFG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[0]); -#endif - - return (size_b); -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (top boot sector type) */ - for (i = 0; i < info->sector_count - 3; i++) - info->start[i] = base + (i * sect_size); - i = info->sector_count - 1; - info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2); - info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2); - info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2); - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - fmt = "29LV800B%s (8 Mbit, %s)\n"; - break; - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { - - case (FPW)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MiB */ - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -#ifdef CFG_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void flash_sync_real_protect(flash_info_t *info) -{ - FPWV *addr = (FPWV *)(info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW)0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *)(info->start[i]); - info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - case FLASH_AM800T: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer(0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00800080; /* erase mode */ - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CFG_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset (info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset (info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/sixnet/fpgadata.c b/board/sixnet/fpgadata.c deleted file mode 100644 index 2d3a7b3..0000000 --- a/board/sixnet/fpgadata.c +++ /dev/null @@ -1,1719 +0,0 @@ - 0xff, 0x87, 0xff, 0x88, 0x7f, 0xff, 0xf9, 0xff, - 0xff, 0xf5, 0xff, 0x8f, 0xff, 0xf0, 0x8f, 0xf9, - 0xff, 0xef, 0xff, 0xff, 0xff, - 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0xff, 0x8f, 0xef, 0xe0, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0x8f, 0x3f, - 0xff, 0xdf, 0xf7, 0xff, 0x0f, 0xfe, 0xf0, 0xff, - 0xff, 0xff, 0xff, 0xef, 0xff, 0xdf, 0x8e, 0x7f, - 0xf1, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xbf, 0xbf, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xef, 0xff, 0xbf, 0x7f, 0xe1, 0xff, - 0xdf, 0xff, 0x7f, 0xff, 0xbf, - 0xff, 0xa7, 0xff, 0x88, 0xff, 0xf1, 0xfe, 0xff, - 0xff, 0xff, 0xff, 0x1f, 0xff, 0xf0, 0xcf, 0xb1, - 0xff, 0xef, 0xff, 0x7f, 0xff, diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c deleted file mode 100644 index 867589f..0000000 --- a/board/sixnet/sixnet.c +++ /dev/null @@ -1,603 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Dave Ellis, SIXNET, dge@sixnetio.com. - * Based on code by: - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * and other contributors to U-Boot. See file CREDITS for list - * of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include /* for eth_init() */ -#include -#include "sixnet.h" -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; -#endif - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -static long ram_size(ulong *, long); - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress (int status) -{ -#if defined(CONFIG_STATUS_LED) -# if defined(STATUS_LED_BOOT) - if (status == 15) { - /* ready to transfer to kernel, make sure LED is proper state */ - status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE); - } -# endif /* STATUS_LED_BOOT */ -#endif /* CONFIG_STATUS_LED */ -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * returns 0 if recognized, -1 if unknown - */ - -int checkboard (void) -{ - puts ("Board: SIXNET SXNI855T\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -#error "SXNI855T has no PCMCIA port" -#endif /* CFG_CMD_PCMCIA */ - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -/* UPMB table for dual UART. */ - -/* this table is for 50MHz operation, it should work at all lower speeds */ -const uint duart_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04, - 0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05, - - /* burst read. (offset 8 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04, - 0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05, - - /* burst write. (offset 20 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - _not_used_, _not_used_, _not_used_, _not_used_, -}; - -/* Load FPGA very early in boot sequence, since it must be - * loaded before the 16C2550 serial channels can be used as - * console channels. - * - * Note: Much of the configuration is not complete. The - * stack is in DPRAM since SDRAM has not been initialized, - * so the stack must be kept small. Global variables - * are still in FLASH, so they cannot be written. - * Only the FLASH, DPRAM, immap and FPGA can be addressed, - * the other chip selects may not have been initialized. - * The clocks have been initialized, so udelay() can be - * used. - */ -#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */ -#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */ -#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */ -#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */ - -int board_postclk_init (void) -{ - - /* the data to load to the XCSxxXL FPGA */ - static const unsigned char fpgadata[] = { -# include "fpgadata.c" - }; - - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; -#define porta (immap->im_ioport.iop_padat) - const unsigned char* pdata; - - /* /INITFPGA and DONEFPGA signals are inputs */ - immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE); - - /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */ - porta &= ~FPGA_PROGRAM_L; - - /* Set FPGA as an output */ - immap->im_ioport.iop_padir |= FPGA_PROGRAM_L; - - /* delay a little to make sure FPGA sees it, really - * only need less than a microsecond. - */ - udelay(10); - - /* unassert /PROGRAM */ - porta |= FPGA_PROGRAM_L; - - /* delay while FPGA does last erase, indicated by - * /INITFPGA going high. This should happen within a - * few milliseconds. - */ - /* ### FIXME - a timeout check would be good, maybe flash - * the status LED to indicate the error? - */ - while ((porta & FPGA_INIT_L) == 0) - ; /* waiting */ - - /* write program data to FPGA at the programming address - * so extra /CS1 strobes at end of configuration don't actually - * write to any registers. - */ - fpga = 0xff; /* first write is ignored */ - fpga = 0xff; /* fill byte */ - fpga = 0xff; /* fill byte */ - fpga = 0x4f; /* preamble code */ - fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */ - fpga = 0x4b; /* field check code */ - - pdata = fpgadata; - /* while no error write out each of the 28 byte frames */ - while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L - && pdata < fpgadata + sizeof(fpgadata)) { - - fpga = 0x4f; /* preamble code */ - - /* 21 bytes of data in a frame */ - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); fpga = *(pdata++); - fpga = *(pdata++); - - fpga = 0x4b; /* field check code */ - fpga = 0xff; /* extended write cycle */ - fpga = 0x4b; /* extended write cycle - * (actually 0x4b from bitgen.exe) - */ - fpga = 0xff; /* extended write cycle */ - fpga = 0xff; /* extended write cycle */ - fpga = 0xff; /* extended write cycle */ - } - - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - fpga = 0xff; /* startup byte */ - -#if 0 /* ### FIXME */ - /* If didn't load all the data or FPGA_DONE is low the load failed. - * Maybe someday stop here and flash the status LED? The console - * is not configured, so can't print an error message. Can't write - * global variables to set a flag (except gd?). - * For now it must work. - */ -#endif - - /* Now that the FPGA is loaded, set up the Dual UART chip - * selects. Must be done here since it may be used as the console. - */ - upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint)); - - memctl->memc_mbmr = DUART_MBMR; - memctl->memc_or5 = DUART_OR_VALUE; - memctl->memc_br5 = DUART_BR5_VALUE; - memctl->memc_or6 = DUART_OR_VALUE; - memctl->memc_br6 = DUART_BR6_VALUE; - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* base address for SRAM, assume 32-bit port, valid */ -#define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V) - -/* up to 64MB - will be adjusted for actual size */ -#define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \ - | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR) -/* - * Miscellaneous platform dependent initializations after running in RAM. - */ - -int misc_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - char* s; - char* e; - int reg; - bd_t *bd = gd->bd; - - memctl->memc_or2 = NVRAM_OR_PRELIM; - memctl->memc_br2 = NVRAM_BR_VALUE; - - /* Is there any SRAM? Is it 16 or 32 bits wide? */ - - /* First look for 32-bit SRAM */ - bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE); - - if (bd->bi_sramsize == 0) { - /* no 32-bit SRAM, but there could be 16-bit SRAM since - * it would report size 0 when configured for 32-bit bus. - * Try again with a 16-bit bus. - */ - memctl->memc_br2 |= BR_PS_16; - bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE); - } - - if (bd->bi_sramsize == 0) { - memctl->memc_br2 = 0; /* disable select since nothing there */ - } - else { - /* adjust or2 for actual size of SRAM */ - memctl->memc_or2 |= ORMASK(bd->bi_sramsize); - bd->bi_sramstart = CFG_SRAM_BASE; - printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10); - } - - - /* set standard MPC8xx clock so kernel will see the time - * even if it doesn't have a DS1306 clock driver. - * This helps with experimenting with standard kernels. - */ - { - ulong tim; - struct rtc_time tmp; - - rtc_get(&tmp); /* get time from DS1306 RTC */ - - /* convert to seconds since 1970 */ - tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday, - tmp.tm_hour, tmp.tm_min, tmp.tm_sec); - - immap->im_sitk.sitk_rtck = KAPWR_KEY; - immap->im_sit.sit_rtc = tim; - } - - /* set up ethernet address for SCC ethernet. If eth1addr - * is present it gets a unique address, otherwise it - * shares the FEC address. - */ - s = getenv("eth1addr"); - if (s == NULL) - s = getenv("ethaddr"); - for (reg=0; reg<6; ++reg) { - bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e+1 : e; - } - - return (0); -} - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -void nand_init(void) -{ - unsigned long totlen = nand_probe(CFG_DFLASH_BASE); - - printf ("%4lu MB\n", totlen >> 20); -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. - * - * The memory size MUST be a power of 2 for this to work. - * - * The only memory modified is 8 bytes at offset 0. This is important - * since for the SRAM this location is reserved for autosizing, so if - * it is modified and the board is reset before ram_size() completes - * no damage is done. Normally even the memory at 0 is preserved. The - * higher SRAM addresses may contain battery backed RAM disk data which - * must never be corrupted. - */ - -static long ram_size(ulong *base, long maxsize) -{ - volatile long *test_addr; - volatile ulong *base_addr = base; - ulong ofs; /* byte offset from base_addr */ - ulong save; /* to make test non-destructive */ - ulong save2; /* to make test non-destructive */ - long ramsize = -1; /* size not determined yet */ - - save = *base_addr; /* save value at 0 so can restore */ - save2 = *(base_addr+1); /* save value at 4 so can restore */ - - /* is any SRAM present? */ - *base_addr = 0x5555aaaa; - - /* It is important to drive the data bus with different data so - * it doesn't remember the value and look like RAM that isn't there. - */ - *(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */ - - if (*base_addr != 0x5555aaaa) - ramsize = 0; /* no RAM present, or defective */ - else { - *base_addr = 0xaaaa5555; - *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */ - if (*base_addr != 0xaaaa5555) - ramsize = 0; /* no RAM present, or defective */ - } - - /* now size it if any is present */ - for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) { - test_addr = (long*)((long)base_addr + ofs); /* location to test */ - - *base_addr = ~*test_addr; - if (*base_addr == *test_addr) - ramsize = ofs; /* wrapped back to 0, so this is the size */ - } - - *base_addr = save; /* restore value at 0 */ - *(base_addr+1) = save2; /* restore value at 4 */ - return (ramsize); -} - -/* ------------------------------------------------------------------------- */ -/* sdram table based on the FADS manual */ -/* for chip MB811171622A-100 */ - -/* this table is for 50MHz operation, it should work at all lower speeds */ - -const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* precharge and Mode Register Set initialization (offset 5). - * This is also entered at offset 6 to do Mode Register Set - * without the precharge. - */ - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - /* FADS had 0x1f27fc04, ... - * but most other boards have 0x1f07fc04, which - * sets GPL0 from A11MPC to 0 1/4 clock earlier, - * like the single read. - * This seems better so I am going with the change. - */ - 0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ }; - -/* ------------------------------------------------------------------------- */ - -#define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */ - -/* precharge and set Mode Register */ -#define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */ - -/* set Mode Register, no precharge */ -#define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */ - -/* runs refresh loop twice so get 8 refresh cycles */ -#define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \ - MCR_MB_CS3 | /* chip select */ \ - MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */ - -/* MAMR values work in either mamr or mbmr */ -#define SDRAM_MAMR_BASE /* refresh at 50MHz */ \ - ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \ - | MAMR_DSA_1_CYCL /* 1 cycle disable */ \ - | MAMR_RLFA_1X /* Read loop 1 time */ \ - | MAMR_WLFA_1X /* Write loop 1 time */ \ - | MAMR_TLFA_4X) /* Timer loop 4 times */ -/* 8 column SDRAM */ -#define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \ - | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \ - | MAMR_G0CLA_A11) /* GPL0 A11[MPC] */ - -/* 9 column SDRAM */ -#define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \ - | MAMR_AMA_TYPE_1 /* Address MUX 1 */ \ - | MAMR_G0CLA_A10) /* GPL0 A10[MPC] */ - -/* base address 0, 32-bit port, SDRAM UPM, valid */ -#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V) - -/* up to 256MB, SAM, G5LS - will be adjusted for actual size */ -#define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS) - -/* This is the Mode Select Register value for the SDRAM. - * Burst length: 4 - * Burst Type: sequential - * CAS Latency: 2 - * Write Burst Length: burst - */ -#define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */ - -/* ------------------------------------------------------------------------- */ - -long int initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - uint size_sdram = 0; - uint size_sdram9 = 0; - uint base = 0; /* SDRAM must start at 0 */ - int i; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Configure the refresh (mostly). This needs to be - * based upon processor clock speed and optimized to provide - * the highest level of performance. - * - * Preliminary prescaler for refresh. - * This value is selected for four cycles in 31.2 us, - * which gives 8192 cycles in 64 milliseconds. - * This may be too fast, but works for any memory. - * It is adjusted to 4096 cycles in 64 milliseconds if - * possible once we know what memory we have. - * - * We have to be careful changing UPM registers after we - * ask it to run these commands. - * - * PTA - periodic timer period for our design is - * 50 MHz x 31.2us - * --------------- = 195 - * 1 x 8 x 1 - * - * 50MHz clock - * 31.2us refresh interval - * SCCR[DFBRG] 0 - * PTP divide by 8 - * 1 chip select - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */ - memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */ - - /* The SDRAM Mode Register value is shifted left 2 bits since - * A30 and A31 don't connect to the SDRAM for 32-bit wide memory. - */ - memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */ - udelay(200); /* SDRAM needs 200uS before set it up */ - - /* Now run the precharge/nop/mrs commands. */ - memctl->memc_mcr = SDRAM_MCR_PRE; - udelay(2); - - /* Run 8 refresh cycles (2 sets of 4) */ - memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */ - udelay(2); - - /* some brands want Mode Register set after the refresh - * cycles. This shouldn't hurt anything for the brands - * that were happy with the first time we set it. - */ - memctl->memc_mcr = SDRAM_MCR_MRS; - udelay(2); - - memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */ - memctl->memc_or3 = SDRAM_OR_PRELIM; - memctl->memc_br3 = SDRAM_BR_VALUE + base; - - /* Some brands need at least 10 DRAM accesses to stabilize. - * It wont hurt the brands that don't. - */ - for (i=0; i<10; ++i) { - volatile ulong *addr = (volatile ulong *)base; - ulong val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* Check SDRAM memory Size in 8 column mode. - * For a 9 column memory we will get half the actual size. - */ - size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE); - - /* Check SDRAM memory Size in 9 column mode. - * For an 8 column memory we will see at most 4 megabytes. - */ - memctl->memc_mamr = SDRAM_MAMR_9COL; - size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE); - - if (size_sdram < size_sdram9) /* leave configuration at 9 columns */ - size_sdram = size_sdram9; - else /* go back to 8 columns */ - memctl->memc_mamr = SDRAM_MAMR_8COL; - - /* adjust or3 for actual size of SDRAM - */ - memctl->memc_or3 |= ORMASK(size_sdram); - - /* Adjust refresh rate depending on SDRAM type. - * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave - * it at the current (fast) rate. - * For 16, 64 and 128 MBit half the rate will do. - */ - if (size_sdram <= 32 * 1024 * 1024) - memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */ - - return (size_sdram); -} diff --git a/board/sixnet/sixnet.h b/board/sixnet/sixnet.h deleted file mode 100644 index e631874..0000000 --- a/board/sixnet/sixnet.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Memory map: - * - * ff100000 -> ff13ffff : FPGA CS1 - * ff030000 -> ff03ffff : EXPANSION CS7 - * ff020000 -> ff02ffff : DATA FLASH CS4 - * ff018000 -> ff01ffff : UART B CS6/UPMB - * ff010000 -> ff017fff : UART A CS5/UPMB - * ff000000 -> ff00ffff : IMAP internal to the MPC855T - * f8000000 -> fbffffff : FLASH CS0 up to 64MB - * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB - * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB - */ diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds deleted file mode 100644 index 1513a85..0000000 --- a/board/sixnet/u-boot.lds +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - common/environment.o(.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sl8245/Makefile b/board/sl8245/Makefile deleted file mode 100644 index 6d11240..0000000 --- a/board/sl8245/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 - 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/sl8245/config.mk b/board/sl8245/config.mk deleted file mode 100644 index 022512b..0000000 --- a/board/sl8245/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2001 - 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# SL8245 board -# - -TEXT_BASE = 0xFFF00000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -PLATFORM_LIBS += $(shell $(CC) -print-libgcc-file-name) diff --git a/board/sl8245/flash.c b/board/sl8245/flash.c deleted file mode 100644 index 553dc98..0000000 --- a/board/sl8245/flash.c +++ /dev/null @@ -1,488 +0,0 @@ -/* - * (C) Copyright 2001 - 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -#define FLASH_BANK_SIZE 0x800000 -#define MAIN_SECT_SIZE 0x40000 -#define PARAM_SECT1_SIZE 0x20000 -#define PARAM_SECT23_SIZE 0x8000 -#define PARAM_SECT4_SIZE 0x10000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -static int write_data (flash_info_t *info, ulong dest, ulong *data); -static void write_via_fpu(vu_long *addr, ulong *data); -static __inline__ unsigned long get_msr(void); -static __inline__ void set_msr(unsigned long msr); - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -/*---------------------------------------------------------------------*/ -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -#define __align__ __attribute__ ((aligned (8))) -static __align__ ulong precmd0[2] = { 0x00aa00aa, 0x00aa00aa }; -static __align__ ulong precmd1[2] = { 0x00550055, 0x00550055 }; -static __align__ ulong cmdid[2] = { 0x00900090, 0x00900090 }; -static __align__ ulong cmderase[2] = { 0x00800080, 0x00800080 }; -static __align__ ulong cmdersusp[2] = { 0x00b000b0, 0x00b000b0 }; -static __align__ ulong cmdsecter[2] = { 0x00300030, 0x00300030 }; -static __align__ ulong cmdprog[2] = { 0x00a000a0, 0x00a000a0 }; -static __align__ ulong cmdres[2] = { 0x00f000f0, 0x00f000f0 }; - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE); - - write_via_fpu (&addr[0xaaa], precmd0); - write_via_fpu (&addr[0x554], precmd1); - write_via_fpu (&addr[0xaaa], cmdid); - - DEBUGF ("Flash bank # %d:\n" - "\tManuf. ID @ 0x%08lX: 0x%08lX\n" - "\tDevice ID @ 0x%08lX: 0x%08lX\n", - i, - (ulong) (&addr[0]), addr[0], - (ulong) (&addr[2]), addr[2]); - - if ((addr[0] == addr[1]) && (addr[0] == AMD_MANUFACT) && - (addr[2] == addr[3]) && (addr[2] == AMD_ID_LV160T)) { - flash_info[i].flash_id = (FLASH_MAN_AMD & FLASH_VENDMASK) | - (FLASH_AM160T & FLASH_TYPEMASK); - } else { - flash_info[i].flash_id = FLASH_UNKNOWN; - write_via_fpu (addr, cmdres); - goto Done; - } - - DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); - - write_via_fpu (addr, cmdres); - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - for (j = 0; j < 32; j++) { - flash_info[i].start[j] = CFG_FLASH_BASE + - i * FLASH_BANK_SIZE + j * MAIN_SECT_SIZE; - } - flash_info[i].start[32] = - flash_info[i].start[31] + PARAM_SECT1_SIZE; - flash_info[i].start[33] = - flash_info[i].start[32] + PARAM_SECT23_SIZE; - flash_info[i].start[34] = - flash_info[i].start[33] + PARAM_SECT23_SIZE; - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE - flash_protect ( FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[1]); -#else - flash_protect ( FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); -#else - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif -#endif - -Done: - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch ((i = info->flash_id & FLASH_VENDMASK)) { - case (FLASH_MAN_AMD & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor 0x%04x ", i); - break; - } - - switch ((i = info->flash_id & FLASH_TYPEMASK)) { - case (FLASH_AM160T & FLASH_TYPEMASK): - printf ("AM29LV160BT (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type 0x%04x\n", i); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - DEBUGF ("Erase flash bank %d sect %d ... %d\n", - info - &flash_info[0], s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (FLASH_MAN_AMD & FLASH_VENDMASK)) { - printf ("Can erase only AMD flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - - DEBUGF ("Erase sect %d @ 0x%08lX\n", sect, (ulong) addr); - - /* Disable interrupts which might cause a timeout - * here. - */ - flag = disable_interrupts (); - - write_via_fpu (&addr[0xaaa], precmd0); - write_via_fpu (&addr[0x554], precmd1); - write_via_fpu (&addr[0xaaa], cmderase); - write_via_fpu (&addr[0xaaa], precmd0); - write_via_fpu (&addr[0x554], precmd1); - write_via_fpu (&addr[0xaaa], cmdsecter); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((addr[0] & 0x00800080) != 0x00800080) || - ((addr[1] & 0x00800080) != 0x00800080)) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - write_via_fpu (addr, cmdersusp); - write_via_fpu (addr, cmdres); - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - write_via_fpu (addr, cmdres); - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -#define FLASH_WIDTH 8 /* flash bus width in bytes */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, cp, msr; - int l, rc, i; - ulong data[2]; - ulong *datah = &data[0]; - ulong *datal = &data[1]; - - DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", - addr, (ulong) src, cnt); - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - msr = get_msr (); - set_msr (msr | MSR_FP); - - wp = (addr & ~(FLASH_WIDTH - 1)); /* get lower aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - *datah = *datal = 0; - - for (i = 0, cp = wp; i < l; i++, cp++) { - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | (*(uchar *) cp); - } - for (; i < FLASH_WIDTH && cnt > 0; ++i) { - char tmp; - - tmp = *src; - - src++; - - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | tmp; - - --cnt; - ++cp; - } - - for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datah << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - set_msr (msr); - return (rc); - } - - wp += FLASH_WIDTH; - } - - /* - * handle FLASH_WIDTH aligned part - */ - while (cnt >= FLASH_WIDTH) { - *datah = *(ulong *) src; - *datal = *(ulong *) (src + 4); - if ((rc = write_data (info, wp, data)) != 0) { - set_msr (msr); - return (rc); - } - wp += FLASH_WIDTH; - cnt -= FLASH_WIDTH; - src += FLASH_WIDTH; - } - - if (cnt == 0) { - set_msr (msr); - return (0); - } - - /* - * handle unaligned tail bytes - */ - *datah = *datal = 0; - for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { - char tmp; - - tmp = *src; - - src++; - - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | tmp; - - --cnt; - } - - for (; i < FLASH_WIDTH; ++i, ++cp) { - if (i >= 4) { - *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); - } - - *datal = (*datal << 8) | (*(uchar *) cp); - } - - rc = write_data (info, wp, data); - set_msr (msr); - - return (rc); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, ulong * data) -{ - vu_long *chip = (vu_long *) (info->start[0]); - vu_long *addr = (vu_long *) dest; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if (((addr[0] & data[0]) != data[0]) || - ((addr[1] & data[1]) != data[1])) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - write_via_fpu (&chip[0xaaa], precmd0); - write_via_fpu (&chip[0x554], precmd1); - write_via_fpu (&chip[0xaaa], cmdprog); - write_via_fpu (addr, data); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - - while (((addr[0] & 0x00800080) != (data[0] & 0x00800080)) || - ((addr[1] & 0x00800080) != (data[1] & 0x00800080))) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - write_via_fpu (chip, cmdres); - return (1); - } - } - - write_via_fpu (chip, cmdres); - - return (0); -} - -/*----------------------------------------------------------------------- - */ -static void write_via_fpu (vu_long * addr, ulong * data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); -} - -/*----------------------------------------------------------------------- - */ -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - return msr; -} - -static __inline__ void set_msr (unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); -} diff --git a/board/sl8245/sl8245.c b/board/sl8245/sl8245.c deleted file mode 100644 index 593eb4e..0000000 --- a/board/sl8245/sl8245.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -int checkboard (void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - printf("Board: SL8245, local bus @ %s MHz\n", strmhz(buf, busfreq)); - return 0; -} - -long int initdram (int board_type) -{ -#ifndef CFG_RAMBOOT - long size; - long new_bank0_end; - long mear1; - long emear1; - - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -#else - return CFG_MAX_RAM_SIZE; -#endif -} - -static struct pci_controller hose; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} diff --git a/board/sl8245/u-boot.lds b/board/sl8245/u-boot.lds deleted file mode 100644 index acb9ffd..0000000 --- a/board/sl8245/u-boot.lds +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/smdk2400/Makefile b/board/smdk2400/Makefile deleted file mode 100644 index fc3d48f..0000000 --- a/board/smdk2400/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := smdk2400.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/smdk2400/config.mk b/board/smdk2400/config.mk deleted file mode 100644 index 82400bf..0000000 --- a/board/smdk2400/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# SAMSUNG board with S3C2400X (ARM920T) CPU -# -# see http://www.samsung.com/ for more information on SAMSUNG -# - -# -# SAMSUNG has 1 bank of 32 MB DRAM -# -# 0C00'0000 to 0E00'0000 -# -# Linux-Kernel is expected to be at 0cf0'0000, entry 0cf0'0000 -# optionally with a ramdisk at 0c80'0000 -# -# we load ourself to 0CF80000 (must be high enough not to be -# overwritten by the uncompessing Linux kernel) -# -# download area is 0C80'0000 -# - - -TEXT_BASE = 0x0CF80000 diff --git a/board/smdk2400/flash.c b/board/smdk2400/flash.c deleted file mode 100644 index a108af7..0000000 --- a/board/smdk2400/flash.c +++ /dev/null @@ -1,491 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include -#include - -#define FLASH_BANK_SIZE 0x1000000 /* 2 x 8 MB */ -#define MAIN_SECT_SIZE 0x40000 /* 2 x 128 kB */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x00FF00FF -#define CMD_IDENTIFY 0x00900090 -#define CMD_ERASE_SETUP 0x00200020 -#define CMD_ERASE_CONFIRM 0x00D000D0 -#define CMD_PROGRAM 0x00400040 -#define CMD_RESUME 0x00D000D0 -#define CMD_SUSPEND 0x00B000B0 -#define CMD_STATUS_READ 0x00700070 -#define CMD_STATUS_RESET 0x00500050 - -#define BIT_BUSY 0x00800080 -#define BIT_ERASE_SUSPEND 0x00400040 -#define BIT_ERASE_ERROR 0x00200020 -#define BIT_PROGRAM_ERROR 0x00100010 -#define BIT_VPP_RANGE_ERROR 0x00080008 -#define BIT_PROGRAM_SUSPEND 0x00040004 -#define BIT_PROTECT_ERROR 0x00020002 -#define BIT_UNDEFINED 0x00010001 - -#define BIT_SEQUENCE_ERROR 0x00300030 -#define BIT_TIMEOUT 0x80000000 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F640J3A & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = CFG_FLASH_BASE; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase; - - /* uniform sector size */ - flashbase += MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* - * Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - -#ifdef CFG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[0]); -#endif - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F640J3A & FLASH_TYPEMASK): - printf ("2x 28F640J3A (64Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_error (ulong code) -{ - /* Check bit patterns */ - /* SR.7=0 is busy, SR.7=1 is ready */ - /* all other flags indicate error on 1 */ - /* SR.0 is undefined */ - /* Timeout is our faked flag */ - - /* sequence is described in Intel 290644-005 document */ - - /* check Timeout */ - if (code & BIT_TIMEOUT) { - puts ("Timeout\n"); - return ERR_TIMOUT; - } - - /* check Busy, SR.7 */ - if (~code & BIT_BUSY) { - puts ("Busy\n"); - return ERR_PROG_ERROR; - } - - /* check Vpp low, SR.3 */ - if (code & BIT_VPP_RANGE_ERROR) { - puts ("Vpp range error\n"); - return ERR_PROG_ERROR; - } - - /* check Device Protect Error, SR.1 */ - if (code & BIT_PROTECT_ERROR) { - puts ("Device protect error\n"); - return ERR_PROG_ERROR; - } - - /* check Command Seq Error, SR.4 & SR.5 */ - if (code & BIT_SEQUENCE_ERROR) { - puts ("Command seqence error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Error, SR.5 */ - if (code & BIT_ERASE_ERROR) { - puts ("Block erase error\n"); - return ERR_PROG_ERROR; - } - - /* check Program Error, SR.4 */ - if (code & BIT_PROGRAM_ERROR) { - puts ("Program error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Suspended, SR.6 */ - if (code & BIT_ERASE_SUSPEND) { - puts ("Block erase suspended\n"); - return ERR_PROG_ERROR; - } - - /* check Program Suspended, SR.2 */ - if (code & BIT_PROGRAM_SUSPEND) { - puts ("Program suspended\n"); - return ERR_PROG_ERROR; - } - - /* OK, no error */ - return ERR_OK; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result, result1; - int iflag, prot, sect; - int rc = ERR_OK; - -#ifdef USE_920T_MMU - int cflag; -#endif - - debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last); - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - debug ("Erasing sector %2d @ %08lX... ", - sect, info->start[sect]); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - ulong bsR7, bsR7_2, bsR5, bsR5_2; - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_ERASE_SETUP; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - *addr = CMD_STATUS_RESET; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - bsR7 = result & (1 << 7); - bsR7_2 = result & (1 << 23); - } while (!bsR7 | !bsR7_2); - - *addr = CMD_STATUS_READ; - result1 = *addr; - bsR5 = result1 & (1 << 5); - bsR5_2 = result1 & (1 << 21); -#ifdef SAMSUNG_FLASH_DEBUG - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); - if (bsR5 != 0 && bsR5_2 != 0) - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); -#endif - - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - - if ((rc = flash_error (result)) != ERR_OK) - goto outahere; -#if 0 - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); -#endif - } - } - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) -{ - vu_long *addr = (vu_long *) dest; - ulong result; - int rc = ERR_OK; - int iflag; - -#ifdef USE_920T_MMU - int cflag; -#endif - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - *addr = CMD_SUSPEND; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - } while (~result & BIT_BUSY); - - /* *addr = CMD_READ_ARRAY; */ - *addr = CMD_STATUS_READ; - result = *addr; - - rc = flash_error (result); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((vu_long *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - return write_word (info, wp, data); -} diff --git a/board/smdk2400/lowlevel_init.S b/board/smdk2400/lowlevel_init.S deleted file mode 100644 index a5de806..0000000 --- a/board/smdk2400/lowlevel_init.S +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the Samsung development board by - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* some parameters for the board */ - -/* - * - * Taken from linux/arch/arm/boot/compressed/head-s3c2400.S - * - * Copyright (C) 2001 Samsung Electronics by chc, 010406 - * - * S3C2400 specific tweaks. - * - */ - -/* memory controller */ -#define BWSCON 0x14000000 -#define BANKCON3 0x14000010 /* for cs8900, ethernet */ - -/* Bank0 */ -#define B0_Tacs 0x0 /* 0 clk */ -#define B0_Tcos 0x0 /* 0 clk */ -#define B0_Tacc 0x7 /* 14 clk */ -#define B0_Tcoh 0x0 /* 0 clk */ -#define B0_Tah 0x0 /* 0 clk */ -#define B0_Tacp 0x0 -#define B0_PMC 0x0 /* normal */ - -/* Bank1 */ -#define B1_Tacs 0x0 /* 0 clk */ -#define B1_Tcos 0x0 /* 0 clk */ -#define B1_Tacc 0x7 /* 14 clk */ -#define B1_Tcoh 0x0 /* 0 clk */ -#define B1_Tah 0x0 /* 0 clk */ -#define B1_Tacp 0x0 -#define B1_PMC 0x0 /* normal */ - -/* Bank2 */ -#define B2_Tacs 0x0 /* 0 clk */ -#define B2_Tcos 0x0 /* 0 clk */ -#define B2_Tacc 0x7 /* 14 clk */ -#define B2_Tcoh 0x0 /* 0 clk */ -#define B2_Tah 0x0 /* 0 clk */ -#define B2_Tacp 0x0 -#define B2_PMC 0x0 /* normal */ - -/* Bank3 - setup for the cs8900 */ -#define B3_Tacs 0x0 /* 0 clk */ -#define B3_Tcos 0x3 /* 4 clk */ -#define B3_Tacc 0x7 /* 14 clk */ -#define B3_Tcoh 0x1 /* 1 clk */ -#define B3_Tah 0x0 /* 0 clk */ -#define B3_Tacp 0x3 /* 6 clk */ -#define B3_PMC 0x0 /* normal */ - -/* Bank4 */ -#define B4_Tacs 0x0 /* 0 clk */ -#define B4_Tcos 0x0 /* 0 clk */ -#define B4_Tacc 0x7 /* 14 clk */ -#define B4_Tcoh 0x0 /* 0 clk */ -#define B4_Tah 0x0 /* 0 clk */ -#define B4_Tacp 0x0 -#define B4_PMC 0x0 /* normal */ - -/* Bank5 */ -#define B5_Tacs 0x0 /* 0 clk */ -#define B5_Tcos 0x0 /* 0 clk */ -#define B5_Tacc 0x7 /* 14 clk */ -#define B5_Tcoh 0x0 /* 0 clk */ -#define B5_Tah 0x0 /* 0 clk */ -#define B5_Tacp 0x0 -#define B5_PMC 0x0 /* normal */ - -/* Bank6 */ -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ -#define B6_SCAN 0x1 /* 9 bit */ - -/* Bank7 */ -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ -#define B7_SCAN 0x1 /* 9 bit */ - -/* refresh parameter */ -#define REFEN 0x1 /* enable refresh */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ -#define Trp 0x0 /* 2 clk */ -#define Trc 0x3 /* 7 clk */ -#define Tchr 0x2 /* 3 clk */ - -#define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */ - - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevel_init -lowlevel_init: - /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #52 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ - -SMRDATA: - .word 0x2211d114 /* d->Ethernet, BUSWIDTH=32 */ - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */ - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */ - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */ - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */ - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */ - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */ - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */ - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */ - .word 0x30 /* MRSR6, CL=3clk */ - .word 0x30 /* MRSR7 */ diff --git a/board/smdk2400/smdk2400.c b/board/smdk2400/smdk2400.c deleted file mode 100644 index cb70218..0000000 --- a/board/smdk2400/smdk2400.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void); -int mdm_init (bd_t *); -extern void disable_putc(void); -extern void enable_putc(void); -extern int hwflow_onoff(int); -extern int do_mdm_init; /* defined in common/main.c */ -#endif /* CONFIG_MODEM_SUPPORT */ - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* memory and cpu-speed are setup before relocation */ - /* change the clock to be 50 MHz 1:1:1 */ - clk_power->MPLLCON = 0x5c042; - clk_power->CLKDIVN = 0; - /* set up the I/O ports */ - gpio->PACON = 0x3ffff; - gpio->PBCON = 0xaaaaaaaa; - gpio->PBUP = 0xffff; - gpio->PECON = 0x0; - gpio->PEUP = 0x0; -#ifdef CONFIG_HWFLOW - /*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */ - /* 10, 10, 00, 00, 10, 00, 10 */ - gpio->PFCON=0xa22; - /* Disable pull-up on Rx, Tx, CTS and RTS pins */ - gpio->PFUP=0x35; -#else - /*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */ - /* 00, 00, 00, 00, 10, 00, 10 */ - gpio->PFCON = 0x22; - /* Disable pull-up on Rx and Tx pins */ - gpio->PFUP = 0x5; -#endif /* CONFIG_HWFLOW */ - gpio->PGCON = 0x0; - gpio->PGUP = 0x0; - gpio->OPENCR = 0x0; - - /* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */ - gd->bd->bi_arch_number = MACH_TYPE_SMDK2400; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x0C000100; - -#ifdef CONFIG_MODEM_SUPPORT - if (key_pressed()) { - disable_putc(); /* modem doesn't understand banner etc */ - do_mdm_init = 1; - } -#endif /* CONFIG_MODEM_SUPPORT */ - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void) -{ - int rc; - if (1) { /* check for button push here, now just return 1 */ - rc = 1; - } - - return rc; -} -#endif /* CONFIG_MODEM_SUPPORT */ diff --git a/board/smdk2400/u-boot.lds b/board/smdk2400/u-boot.lds deleted file mode 100644 index f4fbf96..0000000 --- a/board/smdk2400/u-boot.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/smdk2410/Makefile b/board/smdk2410/Makefile deleted file mode 100644 index 4ee21f5..0000000 --- a/board/smdk2410/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := smdk2410.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/smdk2410/config.mk b/board/smdk2410/config.mk deleted file mode 100644 index 1af85da..0000000 --- a/board/smdk2410/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu -# -# see http://www.samsung.com/ for more information on SAMSUNG -# - -# -# SMDK2410 has 1 bank of 64 MB DRAM -# -# 3000'0000 to 3400'0000 -# -# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 -# optionally with a ramdisk at 3080'0000 -# -# we load ourself to 33F8'0000 -# -# download area is 3300'0000 -# - - -TEXT_BASE = 0x33F80000 diff --git a/board/smdk2410/flash.c b/board/smdk2410/flash.c deleted file mode 100644 index 993946b..0000000 --- a/board/smdk2410/flash.c +++ /dev/null @@ -1,433 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -ulong myflush (void); - - -#define FLASH_BANK_SIZE PHYS_FLASH_SIZE -#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x000000F0 -#define CMD_UNLOCK1 0x000000AA -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000A0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = -#if defined(CONFIG_AMD_LV400) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV400B & FLASH_TYPEMASK); -#elif defined(CONFIG_AMD_LV800) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); -#else -#error "Unknown flash configured" -#endif - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 3) { - /* 1st one is 16 KB */ - if (j == 0) { - flash_info[i].start[j] = - flashbase + 0; - } - - /* 2nd and 3rd are both 8 KB */ - if ((j == 1) || (j == 2)) { - flash_info[i].start[j] = - flashbase + 0x4000 + (j - - 1) * - 0x2000; - } - - /* 4th 32 KB */ - if (j == 3) { - flash_info[i].start[j] = - flashbase + 0x8000; - } - } else { - flash_info[i].start[j] = - flashbase + (j - 3) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV400B & FLASH_TYPEMASK): - printf ("1x Amd29LV400BB (4Mbit)\n"); - break; - case (AMD_ID_LV800B & FLASH_TYPEMASK): - printf ("1x Amd29LV800BB (8Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done:; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ushort result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip = TMO; - break; - } - - if (!chip - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip = READY; - - if (!chip - && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip = ERR; - - } while (!chip); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -volatile static int write_hword (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - int cflag, iflag; - int chip; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - chip = ERR | TMO; - break; - } - if (!chip && ((result & 0x80) == (data & 0x80))) - chip = READY; - - if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip = READY; - else - chip = ERR; - } - - } while (!chip); - - *addr = CMD_READ_ARRAY; - - if (chip == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_hword (info, wp, data); -} diff --git a/board/smdk2410/lowlevel_init.S b/board/smdk2410/lowlevel_init.S deleted file mode 100644 index 310f2a0..0000000 --- a/board/smdk2410/lowlevel_init.S +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* some parameters for the board */ - -/* - * - * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S - * - * Copyright (C) 2002 Samsung Electronics SW.LEE - * - */ - -#define BWSCON 0x48000000 - -/* BWSCON */ -#define DW8 (0x0) -#define DW16 (0x1) -#define DW32 (0x2) -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -#define B1_BWSCON (DW32) -#define B2_BWSCON (DW16) -#define B3_BWSCON (DW16 + WAIT + UBLB) -#define B4_BWSCON (DW16) -#define B5_BWSCON (DW16) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x0 /* 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 -#define B0_PMC 0x0 /* normal */ - -/* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x0 /* 0clk */ -#define B1_Tacc 0x7 /* 14clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 -#define B1_PMC 0x0 - -#define B2_Tacs 0x0 -#define B2_Tcos 0x0 -#define B2_Tacc 0x7 -#define B2_Tcoh 0x0 -#define B2_Tah 0x0 -#define B2_Tacp 0x0 -#define B2_PMC 0x0 - -#define B3_Tacs 0x0 /* 0clk */ -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 /* 14clk */ -#define B3_Tcoh 0x1 /* 1clk */ -#define B3_Tah 0x0 /* 0clk */ -#define B3_Tacp 0x3 /* 6clk */ -#define B3_PMC 0x0 /* normal */ - -#define B4_Tacs 0x0 /* 0clk */ -#define B4_Tcos 0x0 /* 0clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x0 /* 0clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 -#define B4_PMC 0x0 /* normal */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x0 /* 0clk */ -#define B5_Tacc 0x7 /* 14clk */ -#define B5_Tcoh 0x0 /* 0clk */ -#define B5_Tah 0x0 /* 0clk */ -#define B5_Tacp 0x0 -#define B5_PMC 0x0 /* normal */ - -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 -#define B6_SCAN 0x1 /* 9bit */ - -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ -#define B7_SCAN 0x1 /* 9bit */ - -/* REFRESH parameter */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ -/**************************************/ - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevel_init -lowlevel_init: - /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #13*4 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ - -SMRDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 - .word 0x30 - .word 0x30 diff --git a/board/smdk2410/smdk2410.c b/board/smdk2410/smdk2410.c deleted file mode 100644 index 9623aef..0000000 --- a/board/smdk2410/smdk2410.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; - - /* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - - /* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x00044555; - gpio->GPBUP = 0x000007FF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x0000FFFF; - gpio->GPFCON = 0x000055AA; - gpio->GPFUP = 0x000000FF; - gpio->GPGCON = 0xFF95FFBA; - gpio->GPGUP = 0x0000FFFF; - gpio->GPHCON = 0x002AFAAA; - gpio->GPHUP = 0x000007FF; - - /* arch number of SMDK2410-Board */ - gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x30000100; - - icache_enable(); - dcache_enable(); - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} diff --git a/board/smdk2410/u-boot.lds b/board/smdk2410/u-boot.lds deleted file mode 100644 index f4fbf96..0000000 --- a/board/smdk2410/u-boot.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/snmc/qs850/Makefile b/board/snmc/qs850/Makefile deleted file mode 100644 index e5d8446..0000000 --- a/board/snmc/qs850/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/snmc/qs850/config.mk b/board/snmc/qs850/config.mk deleted file mode 100644 index 905f692..0000000 --- a/board/snmc/qs850/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2002-2003 -# Simple Network Magic Corporation, dnevil@snmc.com -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# QS850 -# Start address of Bootloader in Flash -# - -TEXT_BASE = 0xFFF00000 diff --git a/board/snmc/qs850/flash.c b/board/snmc/qs850/flash.c deleted file mode 100644 index d2f169b..0000000 --- a/board/snmc/qs850/flash.c +++ /dev/null @@ -1,616 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -#define FLASH_WORD_SIZE unsigned long -#define FLASH_ID_MASK 0xFFFFFFFF - -/*----------------------------------------------------------------------- - * Functions - */ -/* stolen from esteem192e/flash.c */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); - -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - volatile FLASH_WORD_SIZE* flash_base; - - /* Init: no FLASHes known */ - for (i=0; isize / (info->sector_count - 8 + 1); - small_sect_size = large_sect_size / 8; - - if (info->flash_id & FLASH_BTYPE) { - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 7; i++) { - info->start[i] = base; - base += small_sect_size; - } - - for (; i < info->sector_count; i++) { - info->start[i] = base; - base += large_sect_size; - } - } - else - { - /* set sector offsets for top boot block type */ - for (i = 0; i < (info->sector_count - 8); i++) { - info->start[i] = base; - base += large_sect_size; - } - - for (; i < info->sector_count; i++) { - info->start[i] = base; - base += small_sect_size; - } - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar botboot[]=", bottom boot sect)\n"; - uchar topboot[]=", top boot sector)\n"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - if (info->flash_id & 0x0001 ) { - boottype = botboot; - } else { - boottype = topboot; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit%s",boottype); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit%s",boottype); - break; - case FLASH_AMDL163T: - printf ("AM29DL163T (16 Mbit%s",boottype); - break; - case FLASH_AMDL163B: - printf ("AM29DL163B (16 Mbit%s",boottype); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit%s",boottype); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit%s",boottype); - break; - case FLASH_AMDL323T: - printf ("AM29DL323T (32 Mbit%s",boottype); - break; - case FLASH_AMDL323B: - printf ("AM29DL323B (32 Mbit%s",boottype); - break; - case FLASH_AMDL322T: - printf ("AM29DL322T (32 Mbit%s",boottype); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) -{ - short i; - ulong base = (ulong)addr; - FLASH_WORD_SIZE value; - - /* Write auto select command: read Manufacturer ID */ - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x00890089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x00900090; - if(addr[0x0000] != 0x00890089){ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - } - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (AMD_ID_LV160T & FLASH_ID_MASK): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & FLASH_ID_MASK): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_DL163T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL163T; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_DL163B & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL163B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_DL323T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_DL323B & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_DL322T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - default: - /* FIXME*/ - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP) ) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); - while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != - (0x00800080&FLASH_ID_MASK) ) - { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - return (0); -} diff --git a/board/snmc/qs850/qs850.c b/board/snmc/qs850/qs850.c deleted file mode 100644 index 637f125..0000000 --- a/board/snmc/qs850/qs850.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation, dnevil@snmc.com - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "mpc8xx.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0f07cc04, 0x00adcc04, 0x00a74c00, 0x00bfcc04, - 0x1fffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x0ff7fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00, - 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0f07cc04, 0x0fafcc00, 0x01ad0c04, 0x1ff74c07, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x0ff7fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00, - 0x00fffc00, 0x00fffc00, 0x0ffffc04, 0x0ff77c04, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0xffffcc04, 0x1ff5cc84, 0xffffcc04, 0xffffcc04, - 0xffffcc84, 0xffffcc05, 0xffffcc04, 0xffffcc04, - 0xffffcc04, 0xffffcc04, 0xffffcc04, 0xffffcc04, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x1ff74c04, 0xffffcc07, 0xffffaa34, 0x1fb54a37 -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ID string (QS850, QS823, ...) - * - * Always return 1 - */ - -int checkboard (void) -{ - char *s, *e; - char buf[64]; - int i; - - i = getenv_r("serial#", buf, sizeof(buf)); - s = (i>0) ? buf : NULL; - -#ifdef CONFIG_QS850 - if (!s || strncmp(s, "QS850", 5)) { - puts ("### No HW ID - assuming QS850"); -#endif -#ifdef CONFIG_QS823 - if (!s || strncmp(s, "QS823", 5)) { - puts ("### No HW ID - assuming QS823"); -#endif - } else { - for (e=s; *e; ++e) { - if (*e == ' ') - break; - } - - for ( ; sim_memctl; - long int size; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* - * Prescaler for refresh - */ - memctl->memc_mptpr = CFG_MPTPR; - - /* - * Map controller bank 1 to the SDRAM address - */ - memctl->memc_or1 = CFG_OR1; - memctl->memc_br1 = CFG_BR1; - udelay(1000); - - /* perform SDRAM initialization sequence */ - memctl->memc_mamr = CFG_16M_MAMR; - udelay(100); - - /* Program the SDRAM's Mode Register */ - memctl->memc_mar = SDRAM_MODE_REG; - - /* Run the Prechard Pattern at 0x3C */ - memctl->memc_mcr = UPMA_RUN(1,0x3c); - udelay(1); - - /* Run the Refresh program residing at MAD index 0x30 */ - /* This contains the CBR Refresh command with a loop */ - /* The SDRAM must be refreshed at least 2 times */ - /* Please note a value of zero = 16 loops */ - memctl->memc_mcr = UPMA_RUN(REFRESH_INIT_LOOPS,0x30); - udelay(1); - - /* Run the Exception program residing at MAD index 0x3E */ - /* This contains the Write Mode Register command */ - /* The Write Mode Register command uses the value written to MAR */ - memctl->memc_mcr = UPMA_RUN(1,0x3e); - - udelay (1000); - - /* - * Check for 32M SDRAM Memory Size - */ - size = dram_size(CFG_32M_MAMR|MAMR_PTAE, - (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE); - udelay (1000); - - /* - * Check for 16M SDRAM Memory Size - */ - if (size != SDRAM_32M_MAX_SIZE) { - size = dram_size(CFG_16M_MAMR|MAMR_PTAE, - (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); - udelay (1000); - } - - udelay(10000); - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds deleted file mode 100644 index cb3f456..0000000 --- a/board/snmc/qs850/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/snmc/qs860t/Makefile b/board/snmc/qs860t/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/snmc/qs860t/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/snmc/qs860t/config.mk b/board/snmc/qs860t/config.mk deleted file mode 100644 index f6ab260..0000000 --- a/board/snmc/qs860t/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2002 -# Simple Network Magic Corporation, dnevil@snmc.com -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# QS860T -# Start address of 512K Socketed Flash -# - -TEXT_BASE = 0xFFF00000 diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c deleted file mode 100644 index c84d08d..0000000 --- a/board/snmc/qs860t/flash.c +++ /dev/null @@ -1,1120 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -#ifdef CFG_FLASH_16BIT -#define FLASH_WORD_SIZE unsigned short -#define FLASH_ID_MASK 0xFFFF -#else -#define FLASH_WORD_SIZE unsigned long -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -/* stolen from esteem192e/flash.c */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); - -#ifndef CFG_FLASH_16BIT -static int write_word (flash_info_t *info, ulong dest, ulong data); -#else -static int write_short (flash_info_t *info, ulong dest, ushort data); -#endif -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i=0; iflash_id & FLASH_TYPEMASK) == INTEL_ID_28F320J3A || - (info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F640J3A || - (info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F128J3A) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * info->size/info->sector_count); - } - } - else if (info->flash_id & FLASH_BTYPE) { - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CFG_FLASH_16BIT - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00008000; - info->start[3] = base + 0x0000C000; - info->start[4] = base + 0x00010000; - info->start[5] = base + 0x00014000; - info->start[6] = base + 0x00018000; - info->start[7] = base + 0x0001C000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x000E0000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } -#else - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000A000; - info->start[6] = base + 0x0000C000; - info->start[7] = base + 0x0000E000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00070000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } -#endif - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CFG_FLASH_16BIT - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00014000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x0001C000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } else { - - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } else { - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -#endif - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar botboot[]=", bottom boot sect)\n"; - uchar topboot[]=", top boot sector)\n"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - if (info->flash_id & 0x0001 ) { - boottype = botboot; - } else { - boottype = topboot; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype); - break; - case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype); - break; - case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype); - break; - case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype); - break; - case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype); - break; - case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype); - break; - case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit%s",boottype); - break; - -#if 0 /* enable when devices are available */ - - case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype); - break; - case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype); - break; -#endif - case INTEL_ID_28F320J3A: printf ("INTEL28F320JA3 (32 Mbit%s",boottype); - break; - case INTEL_ID_28F640J3A: printf ("INTEL28F640JA3 (64 Mbit%s",boottype); - break; - case INTEL_ID_28F128J3A: printf ("INTEL28F128JA3 (128 Mbit%s",boottype); - break; - - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) -{ - short i; - ulong base = (ulong)addr; - FLASH_WORD_SIZE value; - - /* Write auto select command: read Manufacturer ID */ - - -#ifndef CFG_FLASH_16BIT - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x00890089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x00900090; - if(addr[0x0000] != 0x00890089){ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x0089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x0090; - - if(addr[0x0000] != 0x0089){ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0090; -#endif - } - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - - } - - value = addr[1]; /* device ID */ - - switch (value) { - - case (AMD_ID_LV400T & FLASH_ID_MASK): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & FLASH_ID_MASK): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & FLASH_ID_MASK): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & FLASH_ID_MASK): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160T & FLASH_ID_MASK): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & FLASH_ID_MASK): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & FLASH_ID_MASK): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_LV320B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case (AMD_ID_DL322T & FLASH_ID_MASK): - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (INTEL_ID_28F800B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800T; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F800B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F160B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160T; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F160B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 /* enable when devices are available */ - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ -#endif - case (INTEL_ID_28F320J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 32 MBit */ - case (INTEL_ID_28F640J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 64 MBit */ - case (INTEL_ID_28F128J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 128 MBit */ - - default: - /* FIXME*/ - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){ - *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - } - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - - volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); - int flag, prot, sect, l_sect, barf; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - ((info->flash_id > FLASH_AMD_COMP) && - ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){ - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - if(info->flash_id < FLASH_AMD_COMP) { -#ifndef CFG_FLASH_16BIT - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; -#endif - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); - while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != - (0x00800080&FLASH_ID_MASK) ) - { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - barf = 0; -#ifndef CFG_FLASH_16BIT - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00200020; - addr[0] = 0x00D000D0; - while(!(addr[0] & 0x00800080)); /* wait for error or finish */ - if( addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if( barf ) { - barf >>=16; - } else { - barf = addr[0] & 0x0000003A; - } - } -#else - addr = (vu_short*)(info->start[sect]); - addr[0] = 0x0020; - addr[0] = 0x00D0; - while(!(addr[0] & 0x0080)); /* wait for error or finish */ - if( addr[0] & 0x003A) /* check for error */ - barf = addr[0] & 0x003A; -#endif - if(barf) { - printf("\nFlash error in sector at %lx\n",(unsigned long)addr); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if((barf & 0x0030) == 0x0030) - printf("Command Sequence error.\n"); - if((barf & 0x0030) == 0x0020) - printf("Block Erase error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - rcode = 1; - } else printf("."); - l_sect = sect; - } - addr = (volatile FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - - } - - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ - -/*flash_info_t *addr2info (ulong addr) -{ - flash_info_t *info; - int i; - - for (i=0, info=&flash_info[0]; i= info->start[0]) && - (addr < (info->start[0] + info->size)) ) { - return (info); - } - } - - return (NULL); -} -*/ -/*----------------------------------------------------------------------- - * Copy memory to flash. - * Make sure all target addresses are within Flash bounds, - * and no protected sectors are hit. - * Returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - target range includes protected sectors - * 8 - target address not in Flash memory - */ - -/*int flash_write (uchar *src, ulong addr, ulong cnt) -{ - int i; - ulong end = addr + cnt - 1; - flash_info_t *info_first = addr2info (addr); - flash_info_t *info_last = addr2info (end ); - flash_info_t *info; - - if (cnt == 0) { - return (0); - } - - if (!info_first || !info_last) { - return (8); - } - - for (info = info_first; info <= info_last; ++info) { - ulong b_end = info->start[0] + info->size;*/ /* bank end addr */ -/* short s_end = info->sector_count - 1; - for (i=0; isector_count; ++i) { - ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; - - if ((end >= info->start[i]) && (addr < e_addr) && - (info->protect[i] != 0) ) { - return (4); - } - } - } - -*/ /* finally write data to flash */ -/* for (info = info_first; info <= info_last && cnt>0; ++info) { - ulong len; - - len = info->start[0] + info->size - addr; - if (len > cnt) - len = cnt; - if ((i = write_buff(info, src, addr, len)) != 0) { - return (i); - } - cnt -= len; - addr += len; - src += len; - } - return (0); -} -*/ -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ -#ifndef CFG_FLASH_16BIT - ulong cp, wp, data; - int l; -#else - ulong cp, wp; - ushort data; -#endif - int i, rc; - -#ifndef CFG_FLASH_16BIT - - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); - -#else - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start byte - */ - if (addr - wp) { - data = 0; - data = (data << 8) | *src++; - --cnt; - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ -/* l = 0; used for debuging */ - while (cnt >= 2) { - data = 0; - for (i=0; i<2; ++i) { - data = (data << 8) | *src++; - } - -/* if(!l){ - printf("%x",data); - l = 1; - } used for debuging */ - - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_short(info, wp, data)); - - -#endif -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifndef CFG_FLASH_16BIT -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start,barf; - int flag; - - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if(info->flash_id > FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - } else { - /* intel stuff */ - *addr = 0x00400040; - } - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - - if(info->flash_id > FLASH_AMD_COMP) { - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } else { - while(!(addr[0] & 0x00800080)) { /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - - if( addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if( barf ) { - barf >>=16; - } else { - barf = addr[0] & 0x0000003A; - } - printf("\nFlash write error at address %lx\n",(unsigned long)dest); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if(barf & 0x0010) printf("Programming error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - return(2); - } - } - - return (0); -} - -#else - -static int write_short (flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - ulong start,barf; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if(info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - } else { - /* intel stuff */ - *addr = 0x00D0; - *addr = 0x0040; - } - *((vu_short *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - - if(info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - } else { - /* intel stuff */ - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); - } - - if( addr[0] & 0x003A) { /* check for error */ - barf = addr[0] & 0x003A; - printf("\nFlash write error at address %lx\n",(unsigned long)dest); - if(barf & 0x0002) printf("Block locked, not erased.\n"); - if(barf & 0x0010) printf("Programming error.\n"); - if(barf & 0x0008) printf("Vpp Low error.\n"); - return(2); - } - *addr = 0x00B0; - *addr = 0x0070; - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); - } - *addr = 0x00FF; - } - return (0); -} - - -#endif - -/*----------------------------------------------------------------------- - */ diff --git a/board/snmc/qs860t/qs860t.c b/board/snmc/qs860t/qs860t.c deleted file mode 100644 index a11d863..0000000 --- a/board/snmc/qs860t/qs860t.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation, dnevil@snmc.com - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "mpc8xx.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04, - 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04 -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ID string (QS860T...) - * - * Always return 1 - */ - -int checkboard (void) -{ - char *s, *e; - char buf[64]; - int i; - - i = getenv_r("serial#", buf, sizeof(buf)); - s = (i>0) ? buf : NULL; - - if (!s || strncmp(s, "QS860T", 6)) { - puts ("### No HW ID - assuming QS860T"); - } else { - for (e=s; *e; ++e) { - if (*e == ' ') - break; - } - - for ( ; sim_memctl; - long int size; - - upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* - * Prescaler for refresh - */ - memctl->memc_mptpr = 0x0400; - - /* - * Map controller bank 2 to the SDRAM address - */ - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; - udelay(200); - - /* perform SDRAM initialization sequence */ - memctl->memc_mbmr = CFG_16M_MBMR; - udelay(100); - - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = 0x80804105; /* run precharge pattern */ - udelay(1); - - /* Run two refresh cycles on SDRAM */ - memctl->memc_mbmr = 0x18802118; - memctl->memc_mcr = 0x80804130; - memctl->memc_mbmr = 0x18802114; - memctl->memc_mcr = 0x80804106; - - udelay (1000); - -#if 0 - /* - * Check for 64M SDRAM Memory Size - */ - size = dram_size (CFG_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE); - udelay (1000); - - /* - * Check for 16M SDRAM Memory Size - */ - if (size != SDRAM_64M_MAX_SIZE) { -#endif - size = dram_size (CFG_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); - udelay (1000); -#if 0 - } - - memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; -#endif - - - udelay(10000); - - -#if 0 - - /* - * Also, map other memory to correct position - */ - - /* - * Map the 8M Intel Flash device to chip select 1 - */ - memctl->memc_or1 = CFG_OR1; - memctl->memc_br1 = CFG_BR1; - - - /* - * Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg - * to chip select 3 - */ - memctl->memc_or3 = CFG_OR3; - memctl->memc_br3 = CFG_BR3; - - /* - * Map chip selects 4, 5, 6, & 7 for external expansion connector - */ - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; - - memctl->memc_or5 = CFG_OR5; - memctl->memc_br5 = CFG_BR5; - - memctl->memc_or6 = CFG_OR6; - memctl->memc_br6 = CFG_BR6; - - memctl->memc_or7 = CFG_OR7; - memctl->memc_br7 = CFG_BR7; - -#endif - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mbmr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mbmr = mbmr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds deleted file mode 100644 index cb3f456..0000000 --- a/board/snmc/qs860t/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sorcery/Makefile b/board/sorcery/Makefile deleted file mode 100644 index 3d6d673..0000000 --- a/board/sorcery/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# (C) Copyright 2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/sorcery/config.mk b/board/sorcery/config.mk deleted file mode 100644 index 25de0b5..0000000 --- a/board/sorcery/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# sorcery board -# - -TEXT_BASE = 0xfff00000 -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/sorcery/sorcery.c b/board/sorcery/sorcery.c deleted file mode 100644 index 35d6a06..0000000 --- a/board/sorcery/sorcery.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2004, Freescale Inc. - * TsiChung Liew, Tsi-Chung.Liew@freescale.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -long int initdram (int board_type) -{ - ulong size; - - size = dramSetup (); - - return get_ram_size((ulong *)CFG_SDRAM_BASE, size); -} - -int checkboard (void) -{ - puts ("Board: Sorcery-C MPC8220\n"); - - return 0; -} - -#if defined(CONFIG_PCI) -/* - * Initialize PCI devices, report devices found. - */ -static struct pci_controller hose; - -#endif /* CONFIG_PCI */ - -void pci_init_board (void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc8220_init (struct pci_controller *hose); - pci_mpc8220_init (&hose); -#endif /* CONFIG_PCI */ -} diff --git a/board/sorcery/u-boot.lds b/board/sorcery/u-boot.lds deleted file mode 100644 index 889bc77..0000000 --- a/board/sorcery/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8220/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/spd8xx/Makefile b/board/spd8xx/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/spd8xx/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/spd8xx/config.mk b/board/spd8xx/config.mk deleted file mode 100644 index e1e0192..0000000 --- a/board/spd8xx/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# SPD823TS boards -# - -TEXT_BASE = 0xFF000000 diff --git a/board/spd8xx/flash.c b/board/spd8xx/flash.c deleted file mode 100644 index 8c0bb4f..0000000 --- a/board/spd8xx/flash.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - /* All Speech Design board memory (DRAM and EPROM) initialisation is - done in dram_init(). - The caller of ths function here expects the total size and will hang, - if we give here back 0. So we return the EPROM size. */ - - return (1024 * 1024); /* 1 MB */ -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - printf("no FLASH memory in MPC823TS board\n"); - return; -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - return 1; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/spd8xx/spd8xx.c b/board/spd8xx/spd8xx.c deleted file mode 100644 index c79b9b0..0000000 --- a/board/spd8xx/spd8xx.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sharc_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04, - 0xFFFFEC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04, - 0xFFFFEC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ - puts ("Board: SPD823TS\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0; - -#if 0 - /* - * Map controller bank 2 to the SRAM bank at preliminary address. - */ - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; -#endif - - /* - * Map controller bank 4 to the PER8 bank. - */ - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; - -#if 0 - /* Configure SHARC at UMA */ - upmconfig (UPMA, (uint *) sharc_table, - sizeof (sharc_table) / sizeof (uint)); - /* Map controller bank 5 to the SHARC */ - memctl->memc_or5 = CFG_OR5; - memctl->memc_br5 = CFG_BR5; -#endif - - memctl->memc_mamr = 0x00001000; - - /* Configure SDRAM at UMB */ - upmconfig (UPMB, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = CFG_MPTPR_1BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - - memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ - - udelay (200); - memctl->memc_mcr = 0x80806105; - udelay (1); - memctl->memc_mcr = 0x80806130; - udelay (1); - memctl->memc_mcr = 0x80806130; - udelay (1); - memctl->memc_mcr = 0x80806106; - - memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ - - /* - * Check Bank 0 Memory Size for re-configuration - */ - size_b0 = - dram_size (CFG_MBMR_8COL, SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); - - memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE; - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mbmr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -void reset_phy (void) -{ - immap_t *immr = (immap_t *) CFG_IMMR; - ushort sreg; - - /* Configure extra port pins for NS DP83843 PHY */ - immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO); - - sreg = immr->im_ioport.iop_padir; - sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */ - sreg &= ~(PA_ENET_MDIO); /* Mgmt. Data I/O is bidirect. => Input */ - immr->im_ioport.iop_padir = sreg; - - immr->im_ioport.iop_padat &= ~(PA_ENET_MDC); /* set MDC = 0 */ - - /* - * RESET in implemented by a positive pulse of at least 1 us - * at the reset pin. - * - * Configure RESET pins for NS DP83843 PHY, and RESET chip. - * - * Note: The RESET pin is high active, but there is an - * inverter on the SPD823TS board... - */ - immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET); - immr->im_ioport.iop_pcdir |= PC_ENET_RESET; - /* assert RESET signal of PHY */ - immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET); - udelay (10); - /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_pcdat |= PC_ENET_RESET; - udelay (10); -} - -/* ------------------------------------------------------------------------- */ - -void ide_set_reset (int on) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - /* - * Configure PC for IDE Reset Pin - */ - if (on) { /* assert RESET */ - immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); - } else { /* release RESET */ - immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; - } - - /* program port pin as GPIO output */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds deleted file mode 100644 index f9150ab..0000000 --- a/board/spd8xx/u-boot.lds +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - common/environment.o(.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug deleted file mode 100644 index 650572d..0000000 --- a/board/spd8xx/u-boot.lds.debug +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/ssv/adnpesc1/Makefile b/board/ssv/adnpesc1/Makefile deleted file mode 100644 index 9182a4e..0000000 --- a/board/ssv/adnpesc1/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2001-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o misc.o - -SOBJS = vectors.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/ssv/adnpesc1/adnpesc1.c b/board/ssv/adnpesc1/adnpesc1.c deleted file mode 100644 index 2f704a0..0000000 --- a/board/ssv/adnpesc1/adnpesc1.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_HW_WATCHDOG) -extern void ssv_wd_pio_init(void); /* comes from ../common/wd_pio.c - included by ./misc.c */ -#endif - -void _default_hdlr (void) -{ - printf ("default_hdlr\n"); -} - -int board_early_init_f (void) -{ -#if defined(CONFIG_HW_WATCHDOG) - ssv_wd_pio_init(); -#endif - return 0; -} - -int checkboard (void) -{ - puts ( "Board: SSV DilNetPC ADNP/ESC1" -#if defined(CONFIG_DNPEVA2) - " on DNP/EVA2" -#endif - "\n"); -#if defined(CONFIG_NIOS_BASE_32) - puts ("Conf.: SSV Base 32 (nios_32)\n"); -#endif - - return 0; -} - -long int initdram (int board_type) -{ - return (0); -} - -/* - * The following are used to control the SPI chip selects for the SPI command. - */ -#if (CONFIG_COMMANDS & CFG_CMD_SPI) && CONFIG_NIOS_SPI - -#define SPI_RTC_CS_MASK 0x00000001 - -void spi_rtc_chipsel(int cs) -{ - nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; - - if (cs) - spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */ - else - spi->slaveselect = 0; /* deactivate (0) */ -} - -/* - * The SPI command uses this table of functions for controlling the SPI - * chip selects: it calls the appropriate function to control the SPI - * chip selects. - */ -spi_chipsel_type spi_chipsel[] = { - spi_rtc_chipsel -}; -int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); - -#endif /* CFG_CMD_SPI */ - -#if defined(CONFIG_POST) -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - return 0; /* No hotkeys supported */ -} -#endif /* CONFIG_POST */ diff --git a/board/ssv/adnpesc1/config.mk b/board/ssv/adnpesc1/config.mk deleted file mode 100644 index 7d8eb03..0000000 --- a/board/ssv/adnpesc1/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2004 -# Li-Pro.Net -# Stephan Linz -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x02fc0000 # ATTENTION: notice your CFG_MONITOR_LEN setting - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/ssv/adnpesc1/flash.c b/board/ssv/adnpesc1/flash.c deleted file mode 100644 index fd8379b..0000000 --- a/board/ssv/adnpesc1/flash.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -/* - * include common flash code (for ssv boards) - */ -#include "../common/flash.c" - -/*---------------------------------------------------------------------*/ -#define BANKSZ (8 * 1024 * 1024) -#define SECTSZ (64 * 1024) -#define UBOOTSECS ((CFG_MONITOR_LEN + CFG_ENV_SIZE) / SECTSZ) -#define UBOOTAREA (UBOOTSECS * 64 * 1024) /* monitor / env area */ - -/*---------------------------------------------------------------------*/ -unsigned long flash_init (void) -{ - int i; - unsigned long addr; - flash_info_t *fli = &flash_info[0]; - - fli->size = BANKSZ; - fli->sector_count = CFG_MAX_FLASH_SECT; - fli->flash_id = FLASH_MAN_AMD + FLASH_AMLV640U; - - addr = CFG_FLASH_BASE; - for (i = 0; i < fli->sector_count; ++i) { - fli->start[i] = addr; - addr += SECTSZ; - - /* Protect monitor / environment area */ - if (addr <= (CFG_FLASH_BASE + UBOOTAREA)) - fli->protect[i] = 1; - else - fli->protect[i] = 0; - } - - return (BANKSZ); -} diff --git a/board/ssv/adnpesc1/misc.c b/board/ssv/adnpesc1/misc.c deleted file mode 100644 index 1c5fcb9..0000000 --- a/board/ssv/adnpesc1/misc.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * board/ssv/adnpesc1/misc.c - * - * miscellaneous board interfaces / drivers - */ - -#include - -#if defined(CONFIG_STATUS_LED) -#include "../common/cmd_sled.c" -#endif - -#if defined(CONFIG_HW_WATCHDOG) -#include "../common/wd_pio.c" -#endif - -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) -#include "../common/post.c" -#endif diff --git a/board/ssv/adnpesc1/u-boot.lds b/board/ssv/adnpesc1/u-boot.lds deleted file mode 100644 index 8b01f45..0000000 --- a/board/ssv/adnpesc1/u-boot.lds +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -OUTPUT_FORMAT("elf32-nios") -OUTPUT_ARCH(nios) -ENTRY(_start) - -SECTIONS -{ - .text : - { - cpu/nios/start.o (.text) - *(.text) - } - __text_end = .; - - . = ALIGN(4); - .rodata : - { - *(.rodata) - } - __rodata_end = .; - - . = ALIGN(4); - .data : - { - *(.data) - } - . = ALIGN(4); - __data_end = .; - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : - { - *(.u_boot_cmd) - } - . = ALIGN(4); - __u_boot_cmd_end = .; - - __bss_start = .; - . = ALIGN(4); - .bss : - { - *(.bss) - } - . = ALIGN(4); - __bss_end = .; -} diff --git a/board/ssv/adnpesc1/vectors.S b/board/ssv/adnpesc1/vectors.S deleted file mode 100644 index fb7e17e..0000000 --- a/board/ssv/adnpesc1/vectors.S +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - - -/************************************************************************* - * Exception Vector Table - * - * This could have gone in the cpu soure tree, but the whole point of - * Nios is customization -- and polluting the cpu source tree with - * board-specific ifdef's really defeats the purpose, no? With this in - * the board-specific tree, each board has the freedom to organize - * vectors/traps, etc anyway it wants. The init code copies this table - * to the proper location. - * - * Each board can do what it likes here. But there are four "standard" - * handlers availble: - * - * _cwp_lolimit -Handles register window underflows. - * _cwp_hilimit -Handles register window overflows. - * _timebase_int -Increments the timebase. - * _def_xhandler -Default exception handler. - * - * _timebase_int handles a Nios Timer interrupt and increments the - * timestamp used for the get_timer(), reset_timer(), etc. routines. It - * expects the timer to be configured like the standard-32 low priority - * timer. - * - * _def_xhandler dispatches exceptions/traps via the external_interrupt() - * routine. This lets you use the irq_install_handler() and handle your - * interrupts/traps with code written in C. - ************************************************************************/ - - .data - .global _vectors - .align 4 -_vectors: - -#if defined(CFG_NIOS_CPU_OCI_BASE) - /* OCI does the reset job */ - .long _def_xhandler@h /* Vector 0 - NMI / Reset */ -#else - /* there is no OCI, so we have to do a direct reset jump here */ - .long CFG_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */ -#endif - .long _cwp_lolimit@h /* Vector 1 - underflow */ - .long _cwp_hilimit@h /* Vector 2 - overflow */ - - .long _def_xhandler@h /* Vector 3 - GNUPro debug */ - .long _def_xhandler@h /* Vector 4 - GNUPro debug */ - .long _def_xhandler@h /* Vector 5 - GNUPro debug */ - .long _def_xhandler@h /* Vector 6 - future reserved */ - .long _def_xhandler@h /* Vector 7 - future reserved */ - .long _def_xhandler@h /* Vector 8 - future reserved */ - .long _def_xhandler@h /* Vector 9 - future reserved */ - .long _def_xhandler@h /* Vector 10 - future reserved */ - .long _def_xhandler@h /* Vector 11 - future reserved */ - .long _def_xhandler@h /* Vector 12 - future reserved */ - .long _def_xhandler@h /* Vector 13 - future reserved */ - .long _def_xhandler@h /* Vector 14 - future reserved */ - .long _def_xhandler@h /* Vector 15 - future reserved */ -#if (CFG_NIOS_TMRIRQ == 16) - .long _timebase_int@h /* Vector 16 - lopri timer*/ -#else - .long _def_xhandler@h /* Vector 16 */ -#endif - .long _def_xhandler@h /* Vector 17 */ - .long _def_xhandler@h /* Vector 18 */ - .long _def_xhandler@h /* Vector 19 */ - .long _def_xhandler@h /* Vector 20 */ - .long _def_xhandler@h /* Vector 21 */ - .long _def_xhandler@h /* Vector 22 */ - .long _def_xhandler@h /* Vector 23 */ - .long _def_xhandler@h /* Vector 24 */ - .long _def_xhandler@h /* Vector 25 */ - .long _def_xhandler@h /* Vector 26 */ - .long _def_xhandler@h /* Vector 27 */ - .long _def_xhandler@h /* Vector 28 */ - .long _def_xhandler@h /* Vector 29 */ - .long _def_xhandler@h /* Vector 30 */ - .long _def_xhandler@h /* Vector 31 */ - .long _def_xhandler@h /* Vector 32 */ - .long _def_xhandler@h /* Vector 33 */ - .long _def_xhandler@h /* Vector 34 */ - .long _def_xhandler@h /* Vector 35 */ - .long _def_xhandler@h /* Vector 36 */ - .long _def_xhandler@h /* Vector 37 */ - .long _def_xhandler@h /* Vector 38 */ - .long _def_xhandler@h /* Vector 39 */ - .long _def_xhandler@h /* Vector 40 */ - .long _def_xhandler@h /* Vector 41 */ - .long _def_xhandler@h /* Vector 42 */ - .long _def_xhandler@h /* Vector 43 */ - .long _def_xhandler@h /* Vector 44 */ - .long _def_xhandler@h /* Vector 45 */ - .long _def_xhandler@h /* Vector 46 */ - .long _def_xhandler@h /* Vector 47 */ - .long _def_xhandler@h /* Vector 48 */ - .long _def_xhandler@h /* Vector 49 */ -#if (CFG_NIOS_TMRIRQ == 50) - .long _timebase_int@h /* Vector 50 - lopri timer*/ -#else - .long _def_xhandler@h /* Vector 50 */ -#endif - .long _def_xhandler@h /* Vector 51 */ - .long _def_xhandler@h /* Vector 52 */ - .long _def_xhandler@h /* Vector 53 */ - .long _def_xhandler@h /* Vector 54 */ - .long _def_xhandler@h /* Vector 55 */ - .long _def_xhandler@h /* Vector 56 */ - .long _def_xhandler@h /* Vector 57 */ - .long _def_xhandler@h /* Vector 58 */ - .long _def_xhandler@h /* Vector 59 */ - .long _def_xhandler@h /* Vector 60 */ - .long _def_xhandler@h /* Vector 61 */ - .long _def_xhandler@h /* Vector 62 */ - .long _def_xhandler@h /* Vector 63 */ diff --git a/board/ssv/common/cmd_sled.c b/board/ssv/common/cmd_sled.c deleted file mode 100644 index d61fa3e..0000000 --- a/board/ssv/common/cmd_sled.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_STATUS_LED) - -/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - * !!!!! Q u i c k & D i r t y H a c k !!!!! - * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - * !!!!! !!!!! - * !!!!! Next type definition was coming from original !!!!! - * !!!!! status LED driver drivers/status_led.c and !!!!! - * !!!!! should exported for using here. !!!!! - * !!!!! !!!!! - * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ - -typedef struct { - led_id_t mask; - int state; - int period; - int cnt; -} led_dev_t; - -extern led_dev_t led_dev[]; - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) -int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - int led_id = 0; - - if (argc > 1) { -#ifdef STATUS_LED_BOOT - if (!strcmp (argv[1], "boot")) { - led_id = STATUS_LED_BOOT + 1; - } -#endif -#ifdef STATUS_LED_RED - if (!strcmp (argv[1], "red")) { - led_id = STATUS_LED_RED + 1; - } -#endif -#ifdef STATUS_LED_YELLOW - if (!strcmp (argv[1], "yellow")) { - led_id = STATUS_LED_YELLOW + 1; - } -#endif -#ifdef STATUS_LED_GREEN - if (!strcmp (argv[1], "green")) { - led_id = STATUS_LED_GREEN + 1; - } -#endif - } - - switch (argc) { - case 1: -#if (STATUS_LED_BITS > 3) - for (; led_id < 4; led_id++) -#elif (STATUS_LED_BITS > 2) - for (; led_id < 3; led_id++) -#elif (STATUS_LED_BITS > 1) - for (; led_id < 2; led_id++) -#elif (STATUS_LED_BITS > 0) - for (; led_id < 1; led_id++) -#else -#error "*** STATUS_LED_BITS not correct defined ***" -#endif - { - printf ("Status LED '%s' is %s\n", - led_id == STATUS_LED_BOOT ? "boot" - : led_id == STATUS_LED_RED ? "red" - : led_id == STATUS_LED_YELLOW ? "yellow" - : led_id == - STATUS_LED_GREEN ? "green" : "unknown", - led_dev[led_id].state == - STATUS_LED_ON ? "on" : led_dev[led_id]. - state == - STATUS_LED_OFF ? "off" : led_dev[led_id]. - state == - STATUS_LED_BLINKING ? "blinking" : "unknown"); - } - return 0; - case 2: - if (led_id) { - printf ("Status LED '%s' is %s\n", argv[1], - led_dev[led_id - 1].state == - STATUS_LED_ON ? "on" : led_dev[led_id - - 1].state == - STATUS_LED_OFF ? "off" : led_dev[led_id - - 1].state == - STATUS_LED_BLINKING ? "blinking" : "unknown"); - return 0; - } else - break; - case 3: - if (led_id) { - if (!strcmp (argv[2], "on")) { - status_led_set (led_id - 1, STATUS_LED_ON); - return 0; - } else if (!strcmp (argv[2], "off")) { - status_led_set (led_id - 1, STATUS_LED_OFF); - return 0; - } else if (!strcmp (argv[2], "blink")) { - status_led_set (led_id - 1, - STATUS_LED_BLINKING); - return 0; - } else - break; - } else - break; - default: - break; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; -} - -#ifdef STATUS_LED_BOOT -#ifdef STATUS_LED_RED -#ifdef STATUS_LED_YELLOW -#ifdef STATUS_LED_GREEN -#define __NAME_STR " - name: boot|red|yellow|green\n" -#else -#define __NAME_STR " - name: boot|red|yellow\n" -#endif -#else -#define __NAME_STR " - name: boot|red\n" -#endif -#else -#define __NAME_STR " - name: boot\n" -#endif -#else -#define __NAME_STR " - name: (no such defined)\n" -#endif - -U_BOOT_CMD (sled, 3, 0, do_sled, - "sled - check and set status led\n", - "sled [name [state]]\n" __NAME_STR " - state: on|off|blink\n"); -#endif /* CFG_CMD_BSP */ -#endif /* CONFIG_STATUS_LED */ diff --git a/board/ssv/common/flash.c b/board/ssv/common/flash.c deleted file mode 100644 index 70cab7f..0000000 --- a/board/ssv/common/flash.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -/*--------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i, k; - unsigned long size; - int erased; - volatile unsigned char *flash; - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - - /* Check if whole sector is erased */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned char *) info->start[i]; - for (k = 0; k < size; k++) { - if (*flash++ != 0xff) { - erased = 0; - break; - } - } - - /* Print the info */ - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", info->start[i], erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*-------------------------------------------------------------------*/ - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; - int prot, sect, wait; - unsigned oldpri; - ulong start; - - /* Some sanity checking */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - for (sect = s_first; sect <= s_last; sect++) { - printf("- Erase: Sect: %i @ 0x%08x\n", sect, info->start[sect]); - } -#endif - - /* NOTE: disabling interrupts on Nios can be very bad since it - * also disables the LO_LIMIT exception. It's better here to - * set the interrupt priority to 3 & restore it when we're done. - */ - oldpri = ipri (3); - - /* It's ok to erase multiple sectors provided we don't delay more - * than 50 usec between cmds ... at which point the erase time-out - * occurs. So don't go and put printf() calls in the loop ... it - * won't be very helpful ;-) - */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - *addr = 0xf0; - *(addr+0xAAA/2) = 0xaa; - *(addr+0x554/2) = 0x55; - *(addr+0xAAA/2) = 0x80; - *(addr+0xAAA/2) = 0xaa; - *(addr+0x554/2) = 0x55; - *addr2 = 0x30; - /* Now just wait for 0xffff & provide some user - * feedback while we wait. Here we have to grant - * timer interrupts. Otherwise get_timer() can't - * work right. */ - ipri(oldpri); - start = get_timer (0); - while (*addr2 != 0xffff) { - for (wait = 8; wait; wait--) { - udelay (125 * 1000); - } - putc ('.'); - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { - printf ("timeout\n"); - return 1; - } - } - oldpri = ipri (3); /* disallow non important irqs again */ - } - } - - printf ("\n"); - *addr = 0xf0; - - /* Restore interrupt priority */ - ipri (oldpri); - - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * srcbuffer, ulong addr, ulong cnt) -{ - - volatile CFG_FLASH_WORD_SIZE *cmd = (vu_short *) info->start[0]; - volatile CFG_FLASH_WORD_SIZE *dst = (vu_short *) addr; - CFG_FLASH_WORD_SIZE *src = (void *) srcbuffer; - CFG_FLASH_WORD_SIZE b; - unsigned oldpri; - ulong start; - - cnt /= sizeof(CFG_FLASH_WORD_SIZE); - while (cnt) { - /* Check for sufficient erase */ - b = *src; - if ((*dst & b) != b) { - printf ("%02x : %02x\n", *dst, b); - return (2); - } - - /* Disable interrupts other than window underflow - * (interrupt priority 2) - */ - oldpri = ipri (3); - *(cmd+0xAAA/2) = 0xaa; - *(cmd+0x554/2) = 0x55; - *(cmd+0xAAA/2) = 0xa0; - ipri (oldpri); - *dst = b; - - /* Verify write */ - start = get_timer (0); - while (*dst != b) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - *cmd = 0xf0; - return 1; - } - } - dst++; - src++; - cnt--; - } - - *cmd = 0xf0; - return (0); -} diff --git a/board/ssv/common/post.c b/board/ssv/common/post.c deleted file mode 100644 index a5f29c1..0000000 --- a/board/ssv/common/post.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - -#if !defined(CFG_NIOS_POST_WORD_ADDR) -#error "*** CFG_NIOS_POST_WORD_ADDR not defined ***" -#endif - -void post_word_store (ulong a) -{ - volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR); - *(volatile ulong *) save_addr = a; -} - -ulong post_word_load (void) -{ - volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR); - return *(volatile ulong *) save_addr; -} - -#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ diff --git a/board/ssv/common/wd_pio.c b/board/ssv/common/wd_pio.c deleted file mode 100644 index 3215ac9..0000000 --- a/board/ssv/common/wd_pio.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#if defined(CONFIG_HW_WATCHDOG) - -#if !defined(CONFIG_HW_WDENA_BASE) -#error "*** CONFIG_HW_WDENA_BASE not defined ***" -#if !defined(CONFIG_HW_WDENA_BIT) -#error "*** CONFIG_HW_WDENA_BIT not defined ***" -#endif -#endif - -#if !defined(CONFIG_HW_WDTOG_BASE) -#error "*** CONFIG_HW_WDTOG_BASE not defined ***" -#if !defined(CONFIG_HW_WDTOG_BIT) -#error "*** CONFIG_HW_WDTOG_BIT not defined ***" -#endif -#endif - -#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */ -static unsigned __wd_ena_pio_portval = 0; -#endif - -#define WD_PIO_INIT_DONE(V) ((V) & (1 << CONFIG_HW_WDENA_BIT)) - -void ssv_wd_pio_init(void) -{ - nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE; - nios_pio_t *trg_piop = (nios_pio_t*)CONFIG_HW_WDTOG_BASE; - - trg_piop->data &= ~(1 << CONFIG_HW_WDTOG_BIT); - -#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */ - - __wd_ena_pio_portval |= (1 << CONFIG_HW_WDENA_BIT); - ena_piop->data = __wd_ena_pio_portval; - -#else /* !CONFIG_HW_WDPORT_WRONLY */ - - trg_piop->direction |= (1 << CONFIG_HW_WDTOG_BIT); - - ena_piop->data |= (1 << CONFIG_HW_WDENA_BIT); - ena_piop->direction |= (1 << CONFIG_HW_WDENA_BIT); - -#endif /* CONFIG_HW_WDPORT_WRONLY */ -} - -void ssv_wd_pio_done(void) -{ - nios_pio_t *piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE; - -#ifdef CONFIG_HW_WDPORT_WRONLY /* emulate read access */ - - __wd_ena_pio_portval &= ~(1 << CONFIG_HW_WDENA_BIT); - piop->data = __wd_ena_pio_portval; - -#else /* !CONFIG_HW_WDPORT_WRONLY */ - - piop->data &= ~(1 << CONFIG_HW_WDENA_BIT); - -#endif /* CONFIG_HW_WDPORT_WRONLY */ -} - -void ssv_wd_pio_reset(void) -{ - nios_pio_t *trg_piop = (nios_pio_t*)CONFIG_HW_WDTOG_BASE; - -#ifdef CONFIG_HW_WDPORT_WRONLY - if (WD_PIO_INIT_DONE(__wd_ena_pio_portval)) -#else - nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE; - - if (WD_PIO_INIT_DONE(ena_piop->data)) -#endif - { - trg_piop->data |= (1 << CONFIG_HW_WDTOG_BIT); - trg_piop->data &= ~(1 << CONFIG_HW_WDTOG_BIT); - } -} - -void hw_watchdog_reset(void) -{ - int re_enable = disable_interrupts (); - - ssv_wd_pio_reset(); - if (re_enable) - enable_interrupts (); -} - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) -int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE; - - switch (argc) - { - case 1: - printf ("Watchdog timer status is %s\n", -#ifdef CONFIG_HW_WDPORT_WRONLY - WD_PIO_INIT_DONE(__wd_ena_pio_portval) -#else - WD_PIO_INIT_DONE(ena_piop->data) -#endif - ? "on" : "off"); - return 0; - case 2: - if (!strcmp(argv[1],"on")) - { - ssv_wd_pio_init(); - printf("Watchdog timer now is on\n"); - return 0; - } - else if (!strcmp(argv[1],"off")) - { - ssv_wd_pio_done(); - printf("Watchdog timer now is off\n"); - return 0; - } - break; - default: - break; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD( - wd, 2, 1, do_wd, - "wd - check and set watchdog\n", - "on - switch watchDog on\n" - "wd off - switch watchdog off\n" - "wd - print current status\n" -); -#endif /* CFG_CMD_BSP */ -#endif /* CONFIG_HW_WATCHDOG */ diff --git a/board/stxgp3/Makefile b/board/stxgp3/Makefile deleted file mode 100644 index d150df8..0000000 --- a/board/stxgp3/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o flash.o -SOBJS := init.o -#SOBJS := - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/stxgp3/config.mk b/board/stxgp3/config.mk deleted file mode 100644 index 2427818..0000000 --- a/board/stxgp3/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# Modified by Xianghua Xiao, X.Xiao@motorola.com -# (C) Copyright 2002,2003 Motorola Inc. -# -# Copied from ADS85xx for STx GP3 - Dan Malek -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# default CCARBAR is at 0xff700000 -# assume U-Boot is less than 0.5MB -# -TEXT_BASE = 0xfff80000 - -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/stxgp3/flash.c b/board/stxgp3/flash.c deleted file mode 100644 index 032989b..0000000 --- a/board/stxgp3/flash.c +++ /dev/null @@ -1,515 +0,0 @@ -/* - * (C) Copyright 2003, Dan Malek, Embedded Edge, LLC. - * Copied from ADS85xx. - * Updated to support the Silicon Tx GP3 8560. We should only find - * two Intel 28F640 parts in 16-bit mode (i.e. 32-bit wide flash), - * but I left other code here in case people order custom boards. - * - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao,(X.Xiao@motorola.com) - * - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if !defined(CFG_NO_FLASH) - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -#undef DEBUG - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ - for (i=0; i= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F640C3T: printf ("28F640C3T (64 Mbit x 2, 128 x 128k)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - -#ifdef DEBUG - printf("Check flash at 0x%08x\n",(uint)addr); -#endif - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - udelay(20); - asm("sync"); - - value = addr[0] & 0x00FF00FF; - -#ifdef DEBUG - printf("manufacturer=0x%x\n",(uint)value); -#endif - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - -#ifdef DEBUG - printf("deviceID=0x%x\n",(uint)value); -#endif - switch (value) { - - case (INTEL_ID_28F640C3T): - info->flash_id += FLASH_28F640C3T; - info->sector_count = 135; - info->size = 0x01000000; - sector_offset = 0x20000; - break; /* => 2x8 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table - * The first 127 blocks are large, the last 8 are small. - */ - for (i = 0; i < 127; i++) { - info->start[i] = base; - base += sector_offset; - /* Sectors are locked upon reset */ - info->protect[i] = 0; - } - for (i = 127; i < 135; i++) { - info->start[i] = base; - base += 0x4000; - /* Sectors are locked upon reset */ - info->protect[i] = 0; - } - - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - *addr = 0xFFFFFF; /* reset bank to read array mode */ - asm("sync"); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - printf("\nFlash Erase:\n"); -#endif - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - /* Start erase on unprotected sectors */ -#if defined(DEBUG) - printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); -#endif - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - asm("sync"); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - /* Single Block Erase Command */ - *addr = 0x20202020; - asm("sync"); - /* Confirm */ - *addr = 0xD0D0D0D0; - asm("sync"); - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - asm("sync"); - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x00800080) != 0x00800080) { - if(*addr & 0x00200020){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - } - } - - printf ("flash erase done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - asm("sync"); - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - - while (((csr = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - - *addr = 0x60606060; - asm("sync"); - *addr = 0xd0d0d0d0; - asm("sync"); - - start = get_timer (0); - while((*addr & 0x00800080) != 0x00800080){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - } - return 0; -} - -#endif /* !CFG_NO_FLASH */ diff --git a/board/stxgp3/init.S b/board/stxgp3/init.S deleted file mode 100644 index d504289..0000000 --- a/board/stxgp3/init.S +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright (C) 2004 Embedded Edge, LLC - * Dan Malek - * Copied from ADS85xx. - * Updates for Silicon Tx GP3 8560. We only support 32-bit flash - * and DDR with SPD EEPROM configuration. - * - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, sharen, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* - * TLB0 4K Non-cacheable, guarded - * 0xff700000 4K Initial CCSRBAR mapping - * - * This ends up at a TLB0 Index==0 entry, and must not collide - * with other TLB0 Entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) -#else -#error("Update the number of table entries in tlb1_entry") -#endif - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \ - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \ - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \ - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \ - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \ - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \ - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \ - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \ - 0,0,0,0,0,1,0,1,0,1) - - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - .long TLB1_MAS0(1, 0, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \ - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \ - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), \ - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), \ - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long TLB1_MAS0(1, 5, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - .long TLB1_MAS0(1, 6, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xfc000000 16K Configuration Latch register - */ - .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,0,1,0,1,0,1) - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - .long TLB1_MAS0(1, 8, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(1, 9, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000), - 0,0,0,0,0,1,0,1,0,1) -#endif - - entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xfc00_0000 0xfc00_ffff Config Latch 64K - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) -#else -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) -#endif - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c deleted file mode 100644 index 2b3949c..0000000 --- a/board/stxgp3/stxgp3.c +++ /dev/null @@ -1,382 +0,0 @@ -/* - * (C) Copyright 2003, Embedded Edge, LLC - * Dan Malek, - * Copied from ADS85xx. - * Updates for Silicon Tx GP3 8560 - * - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -extern long int spd_sdram (void); - -#include -#include -#include -#include -#include -#include -#include -#include - -long int fixed_sdram (void); - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -static uint64_t next_led_update; -static uint led_bit; - -int -board_early_init_f(void) -{ -#if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; - - pci->peer &= 0xfffffffdf; /* disable master abort */ -#endif - return 0; -} - -void -reset_phy(void) -{ - volatile uint *blatch; - - blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE; - - /* reset Giga bit Ethernet port if needed here */ - - *blatch &= ~0x000000c0; - udelay(100); - *blatch = 0x000000c1; /* Light one led, too */ - udelay(1000); - -#if 0 /* This is the port we really want to use for debugging. */ - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr->bcsr2 &= ~FETH2_RST; - udelay(2); - bcsr->bcsr2 |= FETH2_RST; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr->bcsr3 &= ~FETH3_RST; - udelay(2); - bcsr->bcsr3 |= FETH3_RST; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1 ETHERNET", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); -#endif /* CONFIG_MII */ -#endif -} - -int -checkboard(void) -{ - printf ("Board: Silicon Tx GPPP 8560 Board\n"); - return (0); -} - -/* Blinkin' LEDS for Robert. -*/ -void -show_activity(int flag) -{ - volatile uint *blatch; - - if (next_led_update > get_ticks()) - return; - - blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE; - - led_bit >>= 1; - if (led_bit == 0) - led_bit = 0x08; - *blatch = (0xc0 | led_bit); - eieio(); - next_led_update += (get_tbclk() / 4); -} - -long int -initdram (int board_type) -{ - long dram_size = 0; - extern long spd_sdram (void); - volatile immap_t *immap = (immap_t *)CFG_IMMR; - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur= &immap->im_gur; - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - - dram_size = spd_sdram (); - -#if defined(CONFIG_DDR_ECC) - /* Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - return dram_size; -} - - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - -#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_stxgp3_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_stxgp3_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds deleted file mode 100644 index 3bc6150..0000000 --- a/board/stxgp3/u-boot.lds +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2003 Embedded Edge, LLC - * Dan Malek, - * Copied from ADS85xx. - * Updates for Silicon Tx GP3 8560. - * - * (C) Copyright 2002,2003,Motorola,Inc. - * Xianghua Xiao, X.Xiao@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - board/stxgp3/init.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc85xx/start.o (.text) - board/stxgp3/init.o (.text) - cpu/mpc85xx/commproc.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/serial_scc.o (.text) - cpu/mpc85xx/ether_fcc.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/i2c.o (.text) - cpu/mpc85xx/spd_sdram.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/stxxtc/Makefile b/board/stxxtc/Makefile deleted file mode 100644 index 11065cf..0000000 --- a/board/stxxtc/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o oftree.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -%.dtb: %.dts - dtc -f -V 0x10 -I dts -O dtb $< >$@ - -%.c: %.dtb - xxd -i $< \ - | sed -e "s/^unsigned char/const unsigned char/g" \ - | sed -e "s/^unsigned int/const unsigned int/g" > $@ - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/stxxtc/config.mk b/board/stxxtc/config.mk deleted file mode 100644 index f5dc034..0000000 --- a/board/stxxtc/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# STx XTc -# - -TEXT_BASE = 0x40F00000 diff --git a/board/stxxtc/oftree.dts b/board/stxxtc/oftree.dts deleted file mode 100644 index e3f3017..0000000 --- a/board/stxxtc/oftree.dts +++ /dev/null @@ -1,52 +0,0 @@ -/ { - model = "STXXTC V1"; - compatible = "STXXTC"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - linux,phandle = <1>; - #address-cells = <1>; - #size-cells = <0>; - PowerPC,MPC870@0 { - linux,phandle = <3>; - name = "PowerPC,MPC870"; - device_type = "cpu"; - reg = <0>; - clock-frequency = <0>; /* place-holder for runtime fillup */ - timebase-frequency = <0>; /* dido */ - linux,boot-cpu; - i-cache-size = <2000>; - d-cache-size = <2000>; - 32-bit; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <00000000 00000000 00000000 20000000>; - }; - - /* copy of the bd_t information (place-holders) */ - bd_t { - memstart = <0>; - memsize = <0>; - flashstart = <0>; - flashsize = <0>; - flashoffset = <0>; - sramstart = <0>; - sramsize = <0>; - - immr_base = <0>; - - bootflags = <0>; - ip_addr = <0>; - enetaddr = [ 00 00 00 00 00 00 ]; - ethspeed = <0>; - intfreq = <0>; - busfreq = <0>; - - baudrate = <0>; - }; - -}; diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c deleted file mode 100644 index aa3d129..0000000 --- a/board/stxxtc/stxxtc.c +++ /dev/null @@ -1,638 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2005 - * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * U-Boot port on STx XTc board - * Mostly copied from Netta - */ - -#include -#include - -#include "mpc8xx.h" - -#ifdef CONFIG_HW_WATCHDOG -#include -#endif - -/****************************************************************/ - -/* some sane bit macros */ -#define _BD(_b) (1U << (31-(_b))) -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) - -#define _BW(_b) (1U << (15-(_b))) -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) - -#define _BB(_b) (1U << (7-(_b))) -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) - -#define _B(_b) _BD(_b) -#define _BR(_l, _h) _BDR(_l, _h) - -/****************************************************************/ - -/* - * Check Board Identity: - * - * Return 1 always. - */ - -int checkboard(void) -{ - printf ("Silicon Turnkey eXpress XTc\n"); - return (0); -} - -/****************************************************************/ - -#define _NOT_USED_ 0xFFFFFFFF - -/****************************************************************/ - -#define CS_0000 0x00000000 -#define CS_0001 0x10000000 -#define CS_0010 0x20000000 -#define CS_0011 0x30000000 -#define CS_0100 0x40000000 -#define CS_0101 0x50000000 -#define CS_0110 0x60000000 -#define CS_0111 0x70000000 -#define CS_1000 0x80000000 -#define CS_1001 0x90000000 -#define CS_1010 0xA0000000 -#define CS_1011 0xB0000000 -#define CS_1100 0xC0000000 -#define CS_1101 0xD0000000 -#define CS_1110 0xE0000000 -#define CS_1111 0xF0000000 - -#define BS_0000 0x00000000 -#define BS_0001 0x01000000 -#define BS_0010 0x02000000 -#define BS_0011 0x03000000 -#define BS_0100 0x04000000 -#define BS_0101 0x05000000 -#define BS_0110 0x06000000 -#define BS_0111 0x07000000 -#define BS_1000 0x08000000 -#define BS_1001 0x09000000 -#define BS_1010 0x0A000000 -#define BS_1011 0x0B000000 -#define BS_1100 0x0C000000 -#define BS_1101 0x0D000000 -#define BS_1110 0x0E000000 -#define BS_1111 0x0F000000 - -#define GPL0_AAAA 0x00000000 -#define GPL0_AAA0 0x00200000 -#define GPL0_AAA1 0x00300000 -#define GPL0_000A 0x00800000 -#define GPL0_0000 0x00A00000 -#define GPL0_0001 0x00B00000 -#define GPL0_111A 0x00C00000 -#define GPL0_1110 0x00E00000 -#define GPL0_1111 0x00F00000 - -#define GPL1_0000 0x00000000 -#define GPL1_0001 0x00040000 -#define GPL1_1110 0x00080000 -#define GPL1_1111 0x000C0000 - -#define GPL2_0000 0x00000000 -#define GPL2_0001 0x00010000 -#define GPL2_1110 0x00020000 -#define GPL2_1111 0x00030000 - -#define GPL3_0000 0x00000000 -#define GPL3_0001 0x00004000 -#define GPL3_1110 0x00008000 -#define GPL3_1111 0x0000C000 - -#define GPL4_0000 0x00000000 -#define GPL4_0001 0x00001000 -#define GPL4_1110 0x00002000 -#define GPL4_1111 0x00003000 - -#define GPL5_0000 0x00000000 -#define GPL5_0001 0x00000400 -#define GPL5_1110 0x00000800 -#define GPL5_1111 0x00000C00 -#define LOOP 0x00000080 - -#define EXEN 0x00000040 - -#define AMX_COL 0x00000000 -#define AMX_ROW 0x00000020 -#define AMX_MAR 0x00000030 - -#define NA 0x00000008 - -#define UTA 0x00000004 - -#define TODT 0x00000002 - -#define LAST 0x00000001 - -#define A10_AAAA GPL0_AAAA -#define A10_AAA0 GPL0_AAA0 -#define A10_AAA1 GPL0_AAA1 -#define A10_000A GPL0_000A -#define A10_0000 GPL0_0000 -#define A10_0001 GPL0_0001 -#define A10_111A GPL0_111A -#define A10_1110 GPL0_1110 -#define A10_1111 GPL0_1111 - -#define RAS_0000 GPL1_0000 -#define RAS_0001 GPL1_0001 -#define RAS_1110 GPL1_1110 -#define RAS_1111 GPL1_1111 - -#define CAS_0000 GPL2_0000 -#define CAS_0001 GPL2_0001 -#define CAS_1110 GPL2_1110 -#define CAS_1111 GPL2_1111 - -#define WE_0000 GPL3_0000 -#define WE_0001 GPL3_0001 -#define WE_1110 GPL3_1110 -#define WE_1111 GPL3_1111 - -/* #define CAS_LATENCY 3 */ -#define CAS_LATENCY 2 - -const uint sdram_table[0x40] = { - -#if CAS_LATENCY == 3 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif - -#if CAS_LATENCY == 2 - /* RSS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* RBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, - _NOT_USED_, - - /* WBS */ - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - -#endif - - /* UPT */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, -}; - -static const uint nandcs_table[0x40] = { - /* RSS */ - CS_1000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1110 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111 | UTA, - CS_0000 | GPL4_0000 | GPL5_1111, - CS_0000 | GPL4_0001 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ - - /* RBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* WSS */ - CS_1000 | GPL4_1111 | GPL5_1110 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0000 | UTA, - CS_0000 | GPL4_1111 | GPL5_0001 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111 | UTA, - CS_0000 | GPL4_1111 | GPL5_1111, - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, - - /* WBS */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* UPT */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* EXC */ - CS_0001 | LAST, - _NOT_USED_, - - /* REG */ - CS_1110 , - CS_0001 | LAST, -}; - -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) - -/* 9 */ -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -void check_ram(unsigned int addr, unsigned int size) -{ - unsigned int i, j, v, vv; - volatile unsigned int *p; - unsigned int pv; - - p = (unsigned int *)addr; - pv = (unsigned int)p; - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) - *p++ = pv; - - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - v = (unsigned int)p; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - p++; - } - - for (j = 0; j < 5; j++) { - switch (j) { - case 0: v = 0x00000000; break; - case 1: v = 0xffffffff; break; - case 2: v = 0x55555555; break; - case 3: v = 0xaaaaaaaa; break; - default:v = 0xdeadbeef; break; - } - p = (unsigned int *)addr; - for (i = 0; i < size / sizeof(unsigned int); i++) { - *p = v; - vv = *p; - if (vv != v) { - printf("%p: read %08x instead of %08x\n", p, vv, v); - hang(); - } - *p = ~v; - p++; - } - } -} - -#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0) - -long int initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size; - u32 d1, d2; - - upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); - - /* - * Preliminary prescaler for refresh - */ - memctl->memc_mptpr = MPTPR_PTP_DIV8; - - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or4 = CFG_OR4_PRELIM; - memctl->memc_br4 = CFG_BR4_PRELIM; - - memctl->memc_mamr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initialisation sequence */ - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ - udelay(1); - - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay(10000); - - - d1 = 0xAA55AA55; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - d1 = 0x55AA55AA; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - d1 = 0x12345678; - *(volatile u32 *)0 = d1; - d2 = *(volatile u32 *)0; - if (d1 != d2) { - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); - DO_LOOP; - } - - size = get_ram_size((long *)0, SDRAM_MAX_SIZE); - - return size; -} - -/* ------------------------------------------------------------------------- */ - -void reset_phys(void) -{ - int phyno; - unsigned short v; - - udelay(10000); - /* reset the damn phys */ - mii_init(); - - for (phyno = 0; phyno < 32; ++phyno) { - miiphy_read("FEC ETHERNET", phyno, PHY_PHYIDR1, &v); - if (v == 0xFFFF) - continue; - miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_POWD); - udelay(10000); - miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON); - udelay(10000); - } -} - -/* ------------------------------------------------------------------------- */ - -/* GP = general purpose, SP = special purpose (on chip peripheral) */ - -/* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_GP_INMASK _BW(6) -#define PA_GP_OUTMASK (_BW(7)) -#define PA_SP_MASK 0 -#define PA_ODR_VAL 0 -#define PA_GP_OUTVAL (_BW(7)) -#define PA_SP_DIRVAL 0 - -#define PB_GP_INMASK 0 -#define PB_GP_OUTMASK (_B(23)) -#define PB_SP_MASK 0 -#define PB_ODR_VAL 0 -#define PB_GP_OUTVAL (_B(23)) -#define PB_SP_DIRVAL 0 - -#define PC_GP_INMASK 0 -#define PC_GP_OUTMASK (_BW(15)) - -#define PC_SP_MASK 0 -#define PC_SOVAL 0 -#define PC_INTVAL 0 -#define PC_GP_OUTVAL 0 -#define PC_SP_DIRVAL 0 - -#define PE_GP_INMASK 0 -#define PE_GP_OUTMASK 0 -#define PE_GP_OUTVAL 0 - -#define PE_SP_MASK 0 -#define PE_ODR_VAL 0 -#define PE_SP_DIRVAL 0 - -int board_early_init_f(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile iop8xx_t *ioport = &immap->im_ioport; - volatile cpm8xx_t *cpm = &immap->im_cpm; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - (void)ioport; - (void)cpm; -#if 1 - /* NAND chip select */ - upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); - memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB); - memctl->memc_mbmr = 0; /* all clear */ -#endif - - memctl->memc_br5 &= ~BR_V; - memctl->memc_br6 &= ~BR_V; - memctl->memc_br7 &= ~BR_V; - -#if 1 - ioport->iop_padat = PA_GP_OUTVAL; - ioport->iop_paodr = PA_ODR_VAL; - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; - ioport->iop_papar = PA_SP_MASK; - - cpm->cp_pbdat = PB_GP_OUTVAL; - cpm->cp_pbodr = PB_ODR_VAL; - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; - cpm->cp_pbpar = PB_SP_MASK; - - ioport->iop_pcdat = PC_GP_OUTVAL; - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; - ioport->iop_pcso = PC_SOVAL; - ioport->iop_pcint = PC_INTVAL; - ioport->iop_pcpar = PC_SP_MASK; - - cpm->cp_pedat = PE_GP_OUTVAL; - cpm->cp_peodr = PE_ODR_VAL; - cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; - cpm->cp_pepar = PE_SP_MASK; -#endif - - return 0; -} - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - -#include - -extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - unsigned long totlen; - - totlen = nand_probe(CFG_NAND_BASE); - printf ("%4lu MB\n", totlen >> 20); -} -#endif - -#ifdef CONFIG_HW_WATCHDOG - -void hw_watchdog_reset(void) -{ - /* XXX add here the really funky stuff */ -} - -#endif - -#ifdef CONFIG_SHOW_ACTIVITY - -/* called from timer interrupt every 1/CFG_HZ sec */ -void board_show_activity(ulong timestamp) -{ -} - -/* called when looping */ -void show_activity(int arg) -{ -} - -#endif - -#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) -int overwrite_console(void) -{ - /* printf("overwrite_console called\n"); */ - return 0; -} -#endif - -extern int drv_phone_init(void); -extern int drv_phone_use_me(void); -extern int drv_phone_is_idle(void); - -int misc_init_r(void) -{ - return 0; -} - -int last_stage_init(void) -{ - reset_phys(); - - return 0; -} diff --git a/board/stxxtc/u-boot.lds b/board/stxxtc/u-boot.lds deleted file mode 100644 index 9f2901c..0000000 --- a/board/stxxtc/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/stxxtc/u-boot.lds.debug b/board/stxxtc/u-boot.lds.debug deleted file mode 100644 index 004e7fd..0000000 --- a/board/stxxtc/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/svm_sc8xx/Makefile b/board/svm_sc8xx/Makefile deleted file mode 100644 index 13ce9fc..0000000 --- a/board/svm_sc8xx/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/svm_sc8xx/config.mk b/board/svm_sc8xx/config.mk deleted file mode 100644 index 4bec9cb..0000000 --- a/board/svm_sc8xx/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x40000000 diff --git a/board/svm_sc8xx/flash.c b/board/svm_sc8xx/flash.c deleted file mode 100644 index 25e61dd..0000000 --- a/board/svm_sc8xx/flash.c +++ /dev/null @@ -1,797 +0,0 @@ -/* - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); -#if 0 -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); -#endif -#ifdef CONFIG_BOOT_8B -static int my_in_8( unsigned char *addr); -static void my_out_8( unsigned char *addr, int val); -#endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16( unsigned short *addr); -static void my_out_be16( unsigned short *addr, int val); -#endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32( unsigned *addr); -static void my_out_be32( unsigned *addr, int val); -#endif -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - size_b0=0; - size_b1=0; - /* Init: no FLASHes known */ - for (i=0; imemc_or5 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */ - memctl->memc_br5 = CFG_DOC_BASE | 0x401; -#else - memctl->memc_or3 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */ - memctl->memc_br3 = CFG_DOC_BASE | 0x401; -#endif -#endif -#if defined( CONFIG_BOOT_8B) -/* memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */ -/* memctl->memc_br0 = 0x40000401; */ - size_b0 = 0x80000; /* 512 K */ - flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040; - flash_info[0].sector_count = 8; - flash_info[0].size = 0x00080000; - /* set up sector start address table */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].start[i] = 0x40000000 + (i * 0x10000); - /* protect all sectors */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; -#elif defined (CONFIG_BOOT_16B) -/* memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */ -/* memctl->memc_br0 = 0x40000401; */ - size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */ - flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B; - flash_info[0].sector_count = 67; - flash_info[0].size = 0x00400000; - /* set up sector start address table */ - flash_info[0].start[0] = 0x40000000 ; - flash_info[0].start[1] = 0x40000000 + 0x4000; - flash_info[0].start[2] = 0x40000000 + 0x6000; - flash_info[0].start[3] = 0x40000000 + 0x8000; - for (i = 4; i < flash_info[0].sector_count; i++) - flash_info[0].start[i] = 0x40000000 + 0x10000 + ((i-4) * 0x10000); - /* protect all sectors */ - for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; -#endif - - -#ifdef CONFIG_BOOT_32B - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - -#endif /* CONFIG_BOOT_32B */ - - return (size_b0 + size_b1); -} -#if 0 -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -} -#endif -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -#if 0 -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect,in_mid,in_did; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); -#if defined (CONFIG_BOOT_8B ) - my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0xaa ); - my_out_8( (unsigned char * ) ((ulong)addr+0x2aa) , 0x55 ); - my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0x90 ); - in_mid=my_in_8( (unsigned char * ) addr ); - in_did=my_in_8( (unsigned char * ) ((ulong)addr+1) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_8( (unsigned char *)addr, 0xf0); - udelay(1); - my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa ); - my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 ); - my_out_8( (unsigned char *) ((ulong)addr+0x555),0x80 ); - my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa ); - my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 ); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - /*addr[0] = 0x00300030; */ - my_out_8( (unsigned char *) ((ulong)addr),0x30 ); - l_sect = sect; - } - } -#elif defined(CONFIG_BOOT_16B ) - my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0xaa ); - my_out_be16( (unsigned short * ) ((ulong)addr+ (0x554)) , 0x55 ); - my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0x90 ); - in_mid=my_in_be16( (unsigned short * ) addr ); - in_did=my_in_be16 ( (unsigned short * ) ((ulong)addr+2) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_be16( (unsigned short *)addr, 0xf0); - udelay(1); - my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa ); - my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 ); - my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0x80 ); - my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0xaa ); - my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 ); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - my_out_be16( (unsigned short *) ((ulong)addr),0x30 ); - l_sect = sect; - } - } - -#elif defined(CONFIG_BOOT_32B) - my_out_be32( (unsigned * ) ((ulong)addr+0x1554) , 0xaa ); - my_out_be32( (unsigned * ) ((ulong)addr+0xaa8) , 0x55 ); - my_out_be32( (unsigned *) ((ulong)addr+0x1554) , 0x90 ); - in_mid=my_in_be32( (unsigned * ) addr ); - in_did=my_in_be32( (unsigned * ) ((ulong)addr+4) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_be32( (unsigned *)addr, 0xf0); - udelay(1); - my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa ); - my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 ); - my_out_be32( (unsigned *) ((ulong)addr+0x1554),0x80 ); - my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa ); - my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 ); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - my_out_be32( (unsigned *) ((ulong)addr),0x00300030 ); - l_sect = sect; - } - } - -#else -# error CONFIG_BOOT_(size)B missing. -#endif - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); -#if defined (CONFIG_BOOT_8B) - while ( (my_in_8((unsigned char *)addr) & 0x80) != 0x80 ) -#elif defined(CONFIG_BOOT_16B ) - while ( (my_in_be16((unsigned short *)addr) & 0x0080) != 0x0080 ) -#elif defined(CONFIG_BOOT_32B) - while ( (my_in_be32((unsigned *)addr) & 0x00800080) != 0x00800080 ) -#else -# error CONFIG_BOOT_(size)B missing. -#endif - { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#if defined (CONFIG_BOOT_8B) - my_out_8( (unsigned char *)addr, 0xf0); -#elif defined(CONFIG_BOOT_16B ) - my_out_be16( (unsigned short * ) addr , 0x00f0 ); -#elif defined(CONFIG_BOOT_32B) - my_out_be32 ( (unsigned *)addr, 0x00F000F0 ); /* reset bank */ -#else -# error CONFIG_BOOT_(size)B missing. -#endif - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - ulong addr = (ulong)(info->start[0]); - ulong start,last; - int flag; - ulong i; - int data_short[2]; - - /* Check if Flash is (sufficiently) erased */ - if ( ((ulong) *(ulong *)dest & data) != data ) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); -#if defined(CONFIG_BOOT_8B) -#ifdef DEBUG - { - int in_mid,in_did; - my_out_8( (unsigned char * ) (addr+0x555) , 0xaa ); - my_out_8( (unsigned char * ) (addr+0x2aa) , 0x55 ); - my_out_8( (unsigned char * ) (addr+0x555) , 0x90 ); - in_mid=my_in_8( (unsigned char * ) addr ); - in_did=my_in_8( (unsigned char * ) (addr+1) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_8( (unsigned char *)addr, 0xf0); - udelay(1); - } -#endif - { - int data_ch[4]; - data_ch[0]=(int ) ((data>>24) & 0xff); - data_ch[1]=(int ) ((data>>16) &0xff ); - data_ch[2]=(int ) ((data >>8) & 0xff); - data_ch[3]=(int ) (data & 0xff); - for (i=0;i<4;i++ ){ - my_out_8( (unsigned char *) (addr+0x555),0xaa); - my_out_8((unsigned char *) (addr+0x2aa),0x55); - my_out_8( (unsigned char *) (addr+0x555),0xa0); - my_out_8((unsigned char *) (dest+i) ,data_ch[i]); - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - last = start; - while( ( my_in_8((unsigned char *) (dest+i)) ) != ( data_ch[i] ) ) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) { - return 1; - } - } - }/* for */ - } -#elif defined( CONFIG_BOOT_16B) - data_short[0]=(int) (data>>16) & 0xffff; - data_short[1]=(int ) data & 0xffff ; - for (i=0;i<2;i++ ){ - my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa ); - my_out_be16( (unsigned short *) ((ulong)addr+ 0x554),0x55 ); - my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xa0 ); - my_out_be16( (unsigned short *) (dest+(i*2)) ,data_short[i]); - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - start = get_timer (0); - last = start; - while( ( my_in_be16((unsigned short *) (dest+(i*2))) ) != ( data_short[i] ) ) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) { - return 1; - } - } - } -#elif defined( CONFIG_BOOT_32B) - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } -#endif - - - return (0); -} -#ifdef CONFIG_BOOT_8B -static int my_in_8 ( unsigned char *addr) -{ - int ret; - __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; -} - -static void my_out_8 ( unsigned char *addr, int val) -{ - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} -#endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16( unsigned short *addr) -{ - int ret; - __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; -} -static void my_out_be16( unsigned short *addr, int val) -{ - __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} -#endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32( unsigned *addr) -{ - unsigned ret; - __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; -} -static void my_out_be32( unsigned *addr, int val) -{ - __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); -} -#endif diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c deleted file mode 100644 index 9bb9fd0..0000000 --- a/board/svm_sc8xx/svm_sc8xx.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ -const uint sdram_table[] = -{ -/*----------------- - UPM A contents: ------------------ */ -/*--------------------------------------------------- - Read Single Beat Cycle. Offset 0 in the RAM array. ----------------------------------------------------- */ -0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00 , -0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35 , -/*------------------------------------------------ - Read Burst Cycle. Offset 0x8 in the RAM array. ------------------------------------------------- */ -0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, -0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, -/*------------------------------------------------------- - Write Single Beat Cycle. Offset 0x18 in the RAM array -------------------------------------------------------- */ -0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47 , -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*------------------------------------------------- - Write Burst Cycle. Offset 0x20 in the RAM array -------------------------------------------------- */ -0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, -0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*------------------------------------------------------------------------ - Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array ------------------------------------------------------------------------- */ -0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, -0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff, -0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , -/*----------- -* Exception: -* ----------- */ -0x7ffefc07, 0xffffffff, 0xffffffff, 0xffffffff , -}; - -/* ------------------------------------------------------------------------- */ -/* - * Check Board Identity: - * - * Test ID string (SVM8...) - * - * Return 1 for "SC8xx" type, 0 else. - */ - -int checkboard (void) -{ - char *s = getenv("serial#"); - int board_type; - - if (!s || strncmp(s, "SVM8", 4)) { - printf ("### No HW ID - assuming SVM SC8xx\n"); - return (0); - } - - board_type = 1; - - for (; *s; ++s) { - if (*s == ' ') - break; - putc (*s); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = CFG_MPTPR; -#if defined (CONFIG_SDRAM_16M) - memctl->memc_mamr = 0x00802114 | CFG_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xff000a00; - size_b0 = 0x01000000; -#elif defined (CONFIG_SDRAM_32M) - memctl->memc_mamr = 0x00904114 | CFG_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xfe000a00; - size_b0 = 0x02000000; -#elif defined (CONFIG_SDRAM_64M) - memctl->memc_mamr = 0x00a04114 | CFG_MxMR_PTx; - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80002830; - udelay(1); - memctl->memc_mar = 0x00000088; - udelay(1); - memctl->memc_mcr = 0x80002106; - udelay(1); - memctl->memc_or1 = 0xfc000a00; - size_b0 = 0x04000000; -#else -#error SDRAM size configuration missing. -#endif - memctl->memc_br1 = 0x00000081; - udelay(200); - return (size_b0 ); -} - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -extern void doc_probe (ulong physadr); -void doc_init (void) -{ - doc_probe (CFG_DOC_BASE); -} -#endif diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds deleted file mode 100644 index d7f7dc1..0000000 --- a/board/svm_sc8xx/u-boot.lds +++ /dev/null @@ -1,145 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = env_offset; - common/environment.o (.ppcenv) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug deleted file mode 100644 index 894b9bd..0000000 --- a/board/svm_sc8xx/u-boot.lds.debug +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sx1/Makefile b/board/sx1/Makefile deleted file mode 100644 index 8fbdf2a..0000000 --- a/board/sx1/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := sx1.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/sx1/config.mk b/board/sx1/config.mk deleted file mode 100644 index 4902e82..0000000 --- a/board/sx1/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, -# -# SX1 board with OMAP1510 (ARM925T) cpu -# see http://www.ti.com/ for more information on Texas Insturments -# -# SX1 has 1 bank of 256 MB SDRAM -# Physical Address: -# 1000'0000 to 2000'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved) -# -# we load ourself to 1108'0000 -# -# - -TEXT_BASE = 0x11080000 diff --git a/board/sx1/lowlevel_init.S b/board/sx1/lowlevel_init.S deleted file mode 100644 index bdf812e..0000000 --- a/board/sx1/lowlevel_init.S +++ /dev/null @@ -1,397 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, - * - * -- Some bits of code used from rrload's head_OMAP1510.s -- - * Copyright (C) 2002 RidgeRun, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_OMAP1510) -#include <./configs/omap1510.h> -#endif - -#define OMAP1510_CLKS ((1< - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -static void flash__init (void); -static void ether__init (void); - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* arch number of SX1 Board */ - gd->bd->bi_arch_number = MACH_TYPE_SX1; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - -/* kk - this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); - - flash__init (); - ether__init (); - return 0; -} - - -int misc_init_r (void) -{ - /* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */ - /* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */ - - /* setup gpio direction to match board (no floats!) */ - /**gdir = 0xCFF9; */ - /**mdir = 0x103F; */ - - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -static void flash__init (void) -{ -#define CS0_CHIP_SELECT_REG 0xfffecc10 -#define CS3_CHIP_SELECT_REG 0xfffecc1c -#define EMIFS_GlB_Config_REG 0xfffecc0c - - unsigned int regval; - - regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); - regval = regval | 0x0001; /* Turn off write protection for flash devices. */ - if (regval & 0x0002) { - regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */ - /* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */ - /* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */ - /* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */ - } - *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; -} - - -/****************************** - Routine: - Description: -******************************/ -static void ether__init (void) -{ -#define ETH_CONTROL_REG 0x0800000b - /* take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. - */ - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (3); -} - - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} diff --git a/board/sx1/u-boot.lds b/board/sx1/u-boot.lds deleted file mode 100644 index d28155f..0000000 --- a/board/sx1/u-boot.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm925t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/tb0229/Makefile b/board/tb0229/Makefile deleted file mode 100644 index 4375073..0000000 --- a/board/tb0229/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Masami Komiya 2004 -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o vr4131-pci.o -SOBJS = lowlevel_init.o - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/tb0229/config.mk b/board/tb0229/config.mk deleted file mode 100644 index 9a50850..0000000 --- a/board/tb0229/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Masami Komiya 2004 -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# ROM version -TEXT_BASE = 0xBFC00000 - -# RAM version -#TEXT_BASE = 0x80400000 diff --git a/board/tb0229/flash.c b/board/tb0229/flash.c deleted file mode 100644 index e9f6418..0000000 --- a/board/tb0229/flash.c +++ /dev/null @@ -1,1198 +0,0 @@ -/* - * (C) Masami Komiya 2004 - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -#ifdef CFG_FLASH_16BIT -#define FLASH_WORD_SIZE unsigned short -#define FLASH_ID_MASK 0xFFFF -#else -#define FLASH_WORD_SIZE unsigned long -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -/* stolen from esteem192e/flash.c */ -ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info); - -#ifndef CFG_FLASH_16BIT -static int write_word (flash_info_t * info, ulong dest, ulong data); -#else -static int write_short (flash_info_t * info, ulong dest, ushort data); -#endif -static void flash_get_offsets (ulong base, flash_info_t * info); - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = - flash_get_size ((volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE, - &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20); - } - - /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) { - /* Setup offsets */ - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - - /* Monitor protection ON by default */ -#if 0 /* sand: */ - (void) flash_protect (FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM - monitor_flash_len + - size_b0, - FLASH_BASE0_PRELIM - 1 + size_b0, - &flash_info[0]); -#else - (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - - 1, &flash_info[0]); -#endif - size_b1 = 0; - flash_info[0].size = size_b0; - } -#ifdef CFG_FLASH_BASE_2 - /* 2 banks */ - else { - size_b1 = - flash_get_size ((volatile FLASH_WORD_SIZE *) - CFG_FLASH_BASE_2, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); - base_b1 = -size_b1; - pbcr = (pbcr & 0x0001ffff) | base_b1 | - (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); - base_b0 = base_b1 - size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | - (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ - } - - size_b0 = - flash_get_size ((volatile FLASH_WORD_SIZE *) base_b0, - &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ -#if 0 /* sand: */ - (void) flash_protect (FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM - monitor_flash_len + - size_b0, - FLASH_BASE0_PRELIM - 1 + size_b0, - &flash_info[0]); -#else - (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - - 1, &flash_info[0]); -#endif - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = - flash_get_size ((volatile FLASH_WORD_SIZE *) - base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - base_b1 + size_b1 - - monitor_flash_len, - base_b1 + size_b1 - 1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - (void) flash_protect (FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - - monitor_flash_len, - base_b0 + size_b0 - 1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - } /* else 2 banks */ -#endif - return (size_b0 + size_b1); -} - - -/*----------------------------------------------------------------------- - */ - -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start adress table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F320J3A || - (info->flash_id & FLASH_TYPEMASK) == FLASH_28F640J3A || - (info->flash_id & FLASH_TYPEMASK) == FLASH_28F128J3A) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = - base + (i * info->size / info->sector_count); - } - } else if (info->flash_id & FLASH_BTYPE) { - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CFG_FLASH_16BIT - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00008000; - info->start[3] = base + 0x0000C000; - info->start[4] = base + 0x00010000; - info->start[5] = base + 0x00014000; - info->start[6] = base + 0x00018000; - info->start[7] = base + 0x0001C000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x000E0000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x00060000; - } - } -#else - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000A000; - info->start[6] = base + 0x0000C000; - info->start[7] = base + 0x0000E000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00070000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } -#endif - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - -#ifndef CFG_FLASH_16BIT - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00014000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x0001C000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - - } else { - - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - - } else { - - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } -#endif - } - - -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t * info) -{ - int i; - uchar *boottype; - uchar botboot[] = ", bottom boot sect)\n"; - uchar topboot[] = ", top boot sector)\n"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - if (info->flash_id & 0x0001) { - boottype = botboot; - } else { - boottype = topboot; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit%s", boottype); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit%s", boottype); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit%s", boottype); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit%s", boottype); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit%s", boottype); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit%s", boottype); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit%s", boottype); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit%s", boottype); - break; - case FLASH_INTEL800B: - printf ("INTEL28F800B (8 Mbit%s", boottype); - break; - case FLASH_INTEL800T: - printf ("INTEL28F800T (8 Mbit%s", boottype); - break; - case FLASH_INTEL160B: - printf ("INTEL28F160B (16 Mbit%s", boottype); - break; - case FLASH_INTEL160T: - printf ("INTEL28F160T (16 Mbit%s", boottype); - break; - case FLASH_INTEL320B: - printf ("INTEL28F320B (32 Mbit%s", boottype); - break; - case FLASH_INTEL320T: - printf ("INTEL28F320T (32 Mbit%s", boottype); - break; - -#if 0 /* enable when devices are available */ - - case FLASH_INTEL640B: - printf ("INTEL28F640B (64 Mbit%s", boottype); - break; - case FLASH_INTEL640T: - printf ("INTEL28F640T (64 Mbit%s", boottype); - break; -#endif - case FLASH_28F320J3A: - printf ("INTEL28F320J3A (32 Mbit%s", boottype); - break; - case FLASH_28F640J3A: - printf ("INTEL28F640J3A (64 Mbit%s", boottype); - break; - case FLASH_28F128J3A: - printf ("INTEL28F128J3A (128 Mbit%s", boottype); - break; - - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) -{ - short i; - ulong base = (ulong) addr; - FLASH_WORD_SIZE value; - - /* Write auto select command: read Manufacturer ID */ - - -#ifndef CFG_FLASH_16BIT - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x00890089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x00900090; - if (addr[0x0000] != 0x00890089) { - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - - /* - * Note: if it is an AMD flash and the word at addr[0000] - * is 0x0089 this routine will think it is an Intel - * flash device and may(most likely) cause trouble. - */ - - addr[0x0000] = 0x0090; - - if (addr[0x0000] != 0x0089) { - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0090; -#endif - } - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - - } - - value = addr[1]; /* device ID */ - - switch (value) { - - case (AMD_ID_LV400T & FLASH_ID_MASK): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & FLASH_ID_MASK): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & FLASH_ID_MASK): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & FLASH_ID_MASK): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV160T & FLASH_ID_MASK): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & FLASH_ID_MASK): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case (AMD_ID_LV320T & FLASH_ID_MASK): - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (AMD_ID_LV320B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case (INTEL_ID_28F800B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800T; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F800B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (INTEL_ID_28F160B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160T; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F160B3B & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 /* enable when devices are available */ - case (INTEL_ID_28F320B3T & FLASH_ID_MASK): - info->flash_id += FLASH_INTEL320T; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ - - case (INTEL_ID_28F320B3B & FLASH_ID_MASK): - info->flash_id += FLASH_AM320B; - info->sector_count = 135; - info->size = 0x01000000; - break; /* => 16 MB */ -#endif - case (INTEL_ID_28F320J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 32 MBit */ - case (INTEL_ID_28F640J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 64 MBit */ - case (INTEL_ID_28F128J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 128 MBit */ - - default: - /* FIXME */ - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets (base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile FLASH_WORD_SIZE *) (info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) { - *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - } - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - - volatile FLASH_WORD_SIZE *addr = - (volatile FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect, barf; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - ((info->flash_id > FLASH_AMD_COMP) && - ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - if (info->flash_id < FLASH_AMD_COMP) { -#ifndef CFG_FLASH_16BIT - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; -#endif - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *) (info-> - start - [sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]); - while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) != - (0x00800080 & FLASH_ID_MASK)) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { - - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - barf = 0; -#ifndef CFG_FLASH_16BIT - addr = (vu_long *) (info->start[sect]); - addr[0] = 0x00500050; - addr[0] = 0x00200020; - addr[0] = 0x00D000D0; - while (!(addr[0] & 0x00800080)); /* wait for error or finish */ - if (addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if (barf) { - barf >>= 16; - } else { - barf = addr[0] & 0x0000003A; - } - } -#else - addr = (vu_short *) (info->start[sect]); - addr[0] = 0x0050; /* clear status register */ - addr[0] = 0x0020; - addr[0] = 0x00D0; - while (!(addr[0] & 0x0080)); /* wait for error or finish */ - if (addr[0] & 0x003A) /* check for error */ - barf = addr[0] & 0x003A; -#endif - if (barf) { - printf ("\nFlash error in sector at %lx\n", (unsigned long) addr); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if ((barf & 0x0030) == 0x0030) - printf ("Command Sequence error.\n"); - if ((barf & 0x0030) == 0x0020) - printf ("Block Erase error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - rcode = 1; - } else - printf ("."); - l_sect = sect; - } - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; -#ifndef CFG_FLASH_16BIT - addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ -#else - addr[0] = (0x00FF & FLASH_ID_MASK); /* reset bank */ -#endif - } - - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ - -/*flash_info_t *addr2info (ulong addr) -{ - flash_info_t *info; - int i; - - for (i=0, info=&flash_info[0]; i= info->start[0]) && - (addr < (info->start[0] + info->size)) ) { - return (info); - } - } - - return (NULL); -} -*/ -/*----------------------------------------------------------------------- - * Copy memory to flash. - * Make sure all target addresses are within Flash bounds, - * and no protected sectors are hit. - * Returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - target range includes protected sectors - * 8 - target address not in Flash memory - */ - -/*int flash_write (uchar *src, ulong addr, ulong cnt) -{ - int i; - ulong end = addr + cnt - 1; - flash_info_t *info_first = addr2info (addr); - flash_info_t *info_last = addr2info (end ); - flash_info_t *info; - - if (cnt == 0) { - return (0); - } - - if (!info_first || !info_last) { - return (8); - } - - for (info = info_first; info <= info_last; ++info) { - ulong b_end = info->start[0] + info->size;*/ /* bank end addr */ -/* short s_end = info->sector_count - 1; - for (i=0; isector_count; ++i) { - ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; - - if ((end >= info->start[i]) && (addr < e_addr) && - (info->protect[i] != 0) ) { - return (4); - } - } - } - -*/ /* finally write data to flash */ -/* for (info = info_first; info <= info_last && cnt>0; ++info) { - ulong len; - - len = info->start[0] + info->size - addr; - if (len > cnt) - len = cnt; - if ((i = write_buff(info, src, addr, len)) != 0) { - return (i); - } - cnt -= len; - addr += len; - src += len; - } - return (0); -} -*/ -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ -#ifndef CFG_FLASH_16BIT - ulong cp, wp, data; - int l; -#else - ulong cp, wp; - ushort data; -#endif - int i, rc; - -#ifndef CFG_FLASH_16BIT - - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); - -#else - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start byte - */ - if (addr - wp) { - data = 0; - data = (data << 8) | *src++; - --cnt; - if ((rc = write_short (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ -/* l = 0; used for debuging */ - while (cnt >= 2) { - data = 0; - for (i = 0; i < 2; ++i) { - data = (data << 8) | *src++; - } - -/* if(!l){ - printf("%x",data); - l = 1; - } used for debuging */ - - if ((rc = write_short (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_short (info, wp, data)); - - -#endif -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifndef CFG_FLASH_16BIT -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) (info->start[0]); - ulong start, barf; - int flag; - -#if defined (__MIPSEL__) - data = cpu_to_be32 (data); -#endif - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - if (info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - } else { - /* intel stuff */ - *addr = 0x00400040; - } - - *((vu_long *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - - if (info->flash_id < FLASH_AMD_COMP) { - - while ((*((vu_long *) dest) & 0x00800080) != - (data & 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - printf ("timeout\n"); - return (1); - } - } - - } else { - - while (!(addr[0] & 0x00800080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - printf ("timeout\n"); - return (1); - } - } - - if (addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if (barf) { - barf >>= 16; - } else { - barf = addr[0] & 0x0000003A; - } - printf ("\nFlash write error at address %lx\n", - (unsigned long) dest); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if (barf & 0x0010) - printf ("Programming error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - return (2); - } - - - } - - return (0); -} - -#else - -static int write_short (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) (info->start[0]); - ulong start, barf; - int flag; - -#if defined (__MIPSEL__) - data = cpu_to_be16 (data); -#endif - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *) dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - if (info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - } else { - /* intel stuff */ - *addr = 0x00D0; - *addr = 0x0040; - } - *((vu_short *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - - if (info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - } else { - /* intel stuff */ - while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) - return (1); - } - - if (addr[0] & 0x003A) { /* check for error */ - barf = addr[0] & 0x003A; - printf ("\nFlash write error at address %lx\n", - (unsigned long) dest); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if (barf & 0x0010) - printf ("Programming error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - return (2); - } - *addr = 0x00B0; - *addr = 0x0070; - while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) - return (1); - } - - *addr = 0x00FF; - - } - - return (0); - -} -#endif diff --git a/board/tb0229/lowlevel_init.S b/board/tb0229/lowlevel_init.S deleted file mode 100644 index df31806..0000000 --- a/board/tb0229/lowlevel_init.S +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Memory sub-system initialization code for TANBAC Evaluation board TB0229. - * - * Copyright (c) 2003 Masami Komiya - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2, or (at - * your option) any later version. - */ - -#include -#include -#include - - - .globl lowlevel_init -lowlevel_init: - - /* BCUCNTREG1 = 0x0040 */ - la t0, 0xaf000000 - li t1, 0x0040 - sh t1, 0(t0) - - /* ROMSIZEREG = 0x3333 */ - la t0, 0xaf000004 - li t1, 0x3333 - sh t1, 0(t0) - - /* ROMSPEEDREG = 0x3003 */ - la t0, 0xaf000006 - li t1, 0x3003 - sh t1, 0(t0) - - /* BCUCNTREG3 = 0 */ - la t0, 0xaf000016 - li t1, 0x0000 - sh t1, 0(t0) - - /* CMUCLKMSK */ - la t0, 0xaf000060 - li t1, 0x39a2 - sh t1, 0(t0) - - /* PMUCNTREG */ - la t0, 0xaf0000c2 - li t1, 0x0006 - sh t1, 0(t0) - - /* SDRAMMODEREG = 0x8029 */ - la t0, 0xaf000400 - li t1, 0x8029 - sh t1, 0(t0) - - /* SDRAMCNTREG = 0x2322 */ - la t0, 0xaf000402 - li t1, 0x2322 - sh t1, 0(t0) - - /* BCURFCNTREG = 0x0106 */ - la t0, 0xaf000404 - li t1, 0x0106 - sh t1, 0(t0) - - /* RAMSZEREG = 0x5555 (64MB Bank) */ - la t0, 0xaf000408 - li t1, 0x5555 - sh t1, 0(t0) - - j ra - nop diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c deleted file mode 100644 index e7914bd..0000000 --- a/board/tb0229/tb0229.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Board initialize code for TANBAC Evaluation board TB0229. - * - * (C) Masami Komiya 2004 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2, or (at - * your option) any later version. - */ - -#include -#include -#include -#include -#include - -unsigned long mips_io_port_base = 0; - -#if defined(CONFIG_PCI) -static struct pci_controller hose; - -void pci_init_board (void) -{ - init_vr4131_pci(&hose); -} -#endif - - -long int initdram(int board_type) -{ - return get_ram_size (CFG_SDRAM_BASE, 0x8000000); -} - - -int checkboard (void) -{ - printf("Board: TANBAC TB0229 "); - printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000); - - return 0; -} diff --git a/board/tb0229/u-boot.lds b/board/tb0229/u-boot.lds deleted file mode 100644 index 30a2bc5..0000000 --- a/board/tb0229/u-boot.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Masami Komiya 2004 - * - * (C) Copyright 2003 - * Wolfgang Denk Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips") - -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - _gp = ALIGN(16); - - __got_start = .; - .got : { *(.got) } - __got_end = .; - - .sdata : { *(.sdata) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) } - uboot_end = .; -} diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c deleted file mode 100644 index 0ee4bf3..0000000 --- a/board/tb0229/vr4131-pci.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * VR4131 PCIU support code for TANBAC Evaluation board TB0229. - * - * (C) Masami Komiya 2004 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2, or (at - * your option) any later version. - */ - -#include -#include -#include - -#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00) -#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04) -#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08) -#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c) -#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10) -#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14) -#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18) -#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c) -#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24) -#define VR4131_INTCNTSTAREG (volatile unsigned int*)(KSEG1 + 0x0f000c28) -#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c) -#define VR4131_PCIRECONTREG (volatile unsigned int*)(KSEG1 + 0x0f000c30) -#define VR4131_PCIENREG (volatile unsigned int*)(KSEG1 + 0x0f000c34) -#define VR4131_PCICLKSELREG (volatile unsigned int*)(KSEG1 + 0x0f000c38) -#define VR4131_PCITRDYREG (volatile unsigned int*)(KSEG1 + 0x0f000c3c) -#define VR4131_PCICLKRUNREG (volatile unsigned int*)(KSEG1 + 0x0f000c60) -#define VR4131_PCIHOSTCONFIG (volatile unsigned int*)(KSEG1 + 0x0f000d00) -#define VR4131_VENDORIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) -#define VR4131_DEVICEIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) -#define VR4131_COMMANDREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) -#define VR4131_STATUSREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) -#define VR4131_REVREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) -#define VR4131_CLASSREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) -#define VR4131_CACHELSREG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) -#define VR4131_LATTIMERRG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) -#define VR4131_MAILBAREG (volatile unsigned int*)(KSEG1 + 0x0f000d10) -#define VR4131_PCIMBA1REG (volatile unsigned int*)(KSEG1 + 0x0f000d14) -#define VR4131_PCIMBA2REG (volatile unsigned int*)(KSEG1 + 0x0f000d18) - -/*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */ -/*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */ -/*#define VR4122_PCI_HOST_BASE 0xa0000000 */ - -volatile unsigned int *pciconfigaddr; -volatile unsigned int *pciconfigdata; - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -/* - * Access PCI Configuration Register for VR4131 - */ - -static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg, - u32 * data) -{ - u32 bus; - u32 device; - - bus = ((dev & 0xff0000) >> 16); - device = ((dev & 0xf800) >> 11); - - if (bus == 0) { - /* Type 0 Configuration */ - *VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc)); - } else { - /* Type 1 Configuration */ - *VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1); - } - - if (access_type == PCI_ACCESS_WRITE) { - *VR4131_PCICONFDREG = *data; - } else { - *data = *VR4131_PCICONFDREG; - } - - return (0); -} - -static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val) -{ - u32 data; - - if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) - return -1; - - *val = (data >> ((reg & 3) << 3)) & 0xff; - - return 0; -} - - -static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val) -{ - u32 data; - - if (reg & 1) - return -1; - - if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) - return -1; - - *val = (data >> ((reg & 3) << 3)) & 0xffff; - - return 0; -} - - -static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg, - u32 * val) -{ - u32 data = 0; - - if (reg & 3) - return -1; - - if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) - return -1; - - *val = data; - - return (0); -} - -static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val) -{ - u32 data = 0; - - if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) - return -1; - - data = (data & ~(0xff << ((reg & 3) << 3))) | (val << - ((reg & 3) << 3)); - - if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) - return -1; - - return 0; -} - - -static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val) -{ - u32 data = 0; - - if (reg & 1) - return -1; - - if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) - return -1; - - data = (data & ~(0xffff << ((reg & 3) << 3))) | (val << - ((reg & 3) << 3)); - - if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) - return -1; - - return 0; -} - -static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val) -{ - u32 data; - - if (reg & 3) { - return -1; - } - - data = val; - - if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) - return -1; - - return (0); -} - - -/* - * Initialize VR4131 PCIU - */ - -vr4131_pciu_init () -{ - /* PCI clock */ - *VR4131_PCICLKSELREG = 0x00000002; - - /* PCI memory and I/O space */ - *VR4131_PCIMMAW1REG = 0x100F9010; - *VR4131_PCIMMAW2REG = 0x140FD014; - *VR4131_PCIMIOAWREG = 0x160FD000; - - /* Target memory window */ - *VR4131_PCITAW1REG = 0x00081000; /* 64MB */ - *VR4131_PCITAW2REG = 0x00000000; - - *VR4131_MAILBAREG = 0UL; - *VR4131_PCIMBA1REG = 0UL; - - *VR4131_PCITRDYREG = 0x00008004; - - *VR4131_PCIENREG = 0x00000004; /* PCI enable */ - *VR4131_COMMANDREG = 0x02000007; -} - -/* - * Initialize Module - */ - -void init_vr4131_pci (struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0xff; - - vr4131_pciu_init (); /* Initialize VR4131 PCIU */ - - /* PCI memory space #1 */ - pci_set_region (hose->regions + 0, - 0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM); - - /* PCI memory space #2 */ - pci_set_region (hose->regions + 1, - 0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM); - - - /* PCI I/O space */ - pci_set_region (hose->regions + 2, - 0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO); - - /* System memory space */ - pci_set_region (hose->regions + 3, - 0x00000000, - 0x80000000, - 0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose->region_count = 4; - - hose->read_byte = vr4131_pci_read_config_byte; - hose->read_word = vr4131_pci_read_config_word; - hose->read_dword = vr4131_pci_read_config_dword; - hose->write_byte = vr4131_pci_write_config_byte; - hose->write_word = vr4131_pci_write_config_word; - hose->write_dword = vr4131_pci_write_config_dword; - - pci_register_hose (hose); - - hose->last_busno = pci_hose_scan (hose); - - return; -} diff --git a/board/total5200/Makefile b/board/total5200/Makefile deleted file mode 100644 index 232956a..0000000 --- a/board/total5200/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o sdram.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/total5200/config.mk b/board/total5200/config.mk deleted file mode 100644 index 1a7a7cf..0000000 --- a/board/total5200/config.mk +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Total5200 board: -# -# Valid values for TEXT_BASE are: -# -# 0xFFF00000 boot high (standard configuration) -# 0xFE000000 boot low -# 0x00100000 boot from RAM (for testing only) -# - -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -## Standard: boot high -TEXT_BASE = 0xFFF00000 -## For testing: boot from RAM -# TEXT_BASE = 0x00100000 -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h deleted file mode 100644 index 5b0923e..0000000 --- a/board/total5200/mt48lc16m16a2-75.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 0 /* is SDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h deleted file mode 100644 index 4b5ac80..0000000 --- a/board/total5200/mt48lc32m16a2-75.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Micron MT48LC32M16A2-75 is compatible to: - * - Infineon HYB39S512160AT-75 - */ - -#define SDRAM_DDR 0 /* is SDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x514F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -#else -#error CONFIG_MPC5200 is not defined -#endif diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c deleted file mode 100644 index a1601f2..0000000 --- a/board/total5200/sdram.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include "sdram.h" - -#ifndef CFG_RAMBOOT -static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - if (sdram_conf->ddr) { - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000; - __asm__ volatile ("sync"); - } - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. - */ - -#if defined(CONFIG_MPC5200) -long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2; - __asm__ volatile ("sync"); - - if (sdram_conf->ddr) { - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay; - __asm__ volatile ("sync"); - } - - /* find RAM size using SDRAM CS0 only */ - mpc5xxx_sdram_start(sdram_conf, 0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - mpc5xxx_sdram_start(sdram_conf, 1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - mpc5xxx_sdram_start(sdram_conf, 0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - mpc5xxx_sdram_start(sdram_conf, 0); - test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); - mpc5xxx_sdram_start(sdram_conf, 1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); - if (test1 > test2) { - mpc5xxx_sdram_start(sdram_conf, 0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CFG_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CFG_RAMBOOT */ - - return dramsize + dramsize2; -} - -#elif defined(CONFIG_MGT5100) - -long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel; - __asm__ volatile ("sync"); - - /* find RAM size */ - mpc5xxx_sdram_start(sdram_conf, 0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - mpc5xxx_sdram_start(sdram_conf, 1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - mpc5xxx_sdram_start(sdram_conf, 0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CFG_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CFG_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h deleted file mode 100644 index bc21e1d..0000000 --- a/board/total5200/sdram.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -typedef struct { - ulong ddr; - ulong mode; - ulong emode; - ulong control; - ulong config1; - ulong config2; -#if defined(CONFIG_MPC5200) - ulong tapdelay; -#endif -#if defined(CONFIG_MGT5100) - ulong addrsel; -#endif -} sdram_conf_t; - -long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf); diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c deleted file mode 100644 index 1a35187..0000000 --- a/board/total5200/total5200.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "sdram.h" - -#if CONFIG_TOTAL5200_REV==2 -#include "mt48lc32m16a2-75.h" -#else -#include "mt48lc16m16a2-75.h" -#endif - -long int initdram (int board_type) -{ - sdram_conf_t sdram_conf; - - sdram_conf.ddr = SDRAM_DDR; - sdram_conf.mode = SDRAM_MODE; - sdram_conf.emode = 0; - sdram_conf.control = SDRAM_CONTROL; - sdram_conf.config1 = SDRAM_CONFIG1; - sdram_conf.config2 = SDRAM_CONFIG2; -#if defined(CONFIG_MPC5200) - sdram_conf.tapdelay = 0; -#endif -#if defined(CONFIG_MGT5100) - sdram_conf.addrsel = SDRAM_ADDRSEL; -#endif - return mpc5xxx_sdram_init (&sdram_conf); -} - -int checkboard (void) -{ -#if defined(CONFIG_MPC5200) -#if CONFIG_TOTAL5200_REV==2 - puts ("Board: Total5200 Rev.2 "); -#else - puts ("Board: Total5200 "); -#endif -#elif defined(CONFIG_MGT5100) - puts ("Board: Total5100 "); -#endif - -/* - * Retrieve FPGA Revision. - */ -printf ("(FPGA %08X)\n", *(vu_long *) (CFG_FPGA_BASE + 0x400)); - -/* - * Take all peripherals in power-up mode. - */ -#if CONFIG_TOTAL5200_REV==2 - *(vu_char *) (CFG_CPLD_BASE + 0x46) = 0x70; -#else - *(vu_long *) (CFG_CPLD_BASE + 0x400) = 0x70; -#endif - - return 0; -} - -#if defined(CONFIG_MGT5100) -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable CS0 - * because CS_BOOT cannot be written. - */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ - - return 0; -} -#endif - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) - -/* IRDA_1 aka PSC6_3 (pin C13) */ -#define GPIO_IRDA_1 0x20000000UL - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - - /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1; - *(vu_long *) MPC5XXX_GPIO_DIR |= GPIO_IRDA_1; -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1; - } else { - *(vu_long *) MPC5XXX_GPIO_DATA_O |= GPIO_IRDA_1; - } -} -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ - -#ifdef CONFIG_VIDEO_SED13806 -#include - -#define DISPLAY_WIDTH 640 -#define DISPLAY_HEIGHT 480 - -#ifdef CONFIG_VIDEO_SED13806_8BPP -#error CONFIG_VIDEO_SED13806_8BPP not supported. -#endif /* CONFIG_VIDEO_SED13806_8BPP */ - -#ifdef CONFIG_VIDEO_SED13806_16BPP -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x00}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x00}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x05}, /* LCD Display Mode Register */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x00}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; -#endif /* CONFIG_VIDEO_SED13806_16BPP */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -/* Return text to be printed besides the logo. */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { -#ifdef CONFIG_MGT5100 - strcpy (info, " Total5100"); -#elif CONFIG_TOTAL5200_REV==1 - strcpy (info, " Total5200"); -#elif CONFIG_TOTAL5200_REV==2 - strcpy (info, " Total5200 Rev.2"); -#else -#error CONFIG_TOTAL5200_REV must be 1 or 2. -#endif - } else { - info [0] = '\0'; - } -} -#endif - -/* Returns SED13806 base address. First thing called in the driver. */ -unsigned int board_video_init (void) -{ - return CFG_LCD_BASE; -} - -/* Called after initializing the SED13806 and before clearing the screen. */ -void board_validate_screen (unsigned int base) -{ -} - -/* Return a pointer to the initialization sequence. */ -const S1D_REGS *board_get_regs (void) -{ - return init_regs; -} - -int board_get_width (void) -{ - return DISPLAY_WIDTH; -} - -int board_get_height (void) -{ - return DISPLAY_HEIGHT; -} - -#endif /* CONFIG_VIDEO_SED13806 */ diff --git a/board/total5200/u-boot.lds b/board/total5200/u-boot.lds deleted file mode 100644 index 3cc2968..0000000 --- a/board/total5200/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/tqm5200/Makefile b/board/tqm5200/Makefile deleted file mode 100644 index c234332..0000000 --- a/board/tqm5200/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -#OBJS := $(BOARD).o flash.o -OBJS := $(BOARD).o cmd_stk52xx.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqm5200/cmd_stk52xx.c deleted file mode 100755 index 8b9057f..0000000 --- a/board/tqm5200/cmd_stk52xx.c +++ /dev/null @@ -1,1221 +0,0 @@ -/* - * (C) Copyright 2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * SKT52XX specific functions - */ -/*#define DEBUG*/ - -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -#define DEFAULT_VOL 45 -#define DEFAULT_FREQ 500 -#define DEFAULT_DURATION 200 -#define LEFT 1 -#define RIGHT 2 -#define LEFT_RIGHT 3 -#define BL_OFF 0 -#define BL_ON 1 - -#define SM501_GPIO_CTRL_LOW 0x00000008UL -#define SM501_GPIO_CTRL_HIGH 0x0000000CUL -#define SM501_POWER_MODE0_GATE 0x00000040UL -#define SM501_POWER_MODE1_GATE 0x00000048UL -#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL -#define SM501_GPIO_DATA_LOW 0x00010000UL -#define SM501_GPIO_DATA_HIGH 0x00010004UL -#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL -#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL -#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL - -static int i2s_squarewave(unsigned long duration, unsigned int freq, - unsigned int channel); -static int i2s_sawtooth(unsigned long duration, unsigned int freq, - unsigned int channel); -static void spi_init(void); -static int spi_transmit(unsigned char data); -static void pcm1772_write_reg(unsigned char addr, unsigned char data); -static void set_attenuation(unsigned char attenuation); - -#ifdef CONFIG_STK52XX -static void spi_init(void) -{ - struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - /* PSC3 as SPI and GPIOs */ - gpio->port_config &= 0xFFFFF0FF; - gpio->port_config |= 0x00000800; - /* - * Its important to use the correct order when initializing the - * registers - */ - spi->ddr = 0x0F; /* set all SPI pins as output */ - spi->pdr = 0x08; /* set SS high */ - spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */ - spi->cr2 = 0x00; /* normal operation */ - spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */ -} - -static int spi_transmit(unsigned char data) -{ - int dummy; - struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; - - spi->dr = data; - /* wait for SPI transmission completed */ - while(!(spi->sr & 0x80)) - { - if (spi->sr & 0x40) /* if write collision occured */ - { - /* do dummy read to clear status register */ - dummy = spi->dr; - printf ("SPI write collision\n"); - return -1; - } - } - return (spi->dr); -} - -static void pcm1772_write_reg(unsigned char addr, unsigned char data) -{ - struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; - - spi->pdr = 0x00; /* Set SS low */ - spi_transmit(addr); - spi_transmit(data); - /* wait some time to meet MS# hold time of PCM1772 */ - udelay (1); - spi->pdr = 0x08; /* set SS high */ -} - -static void set_attenuation(unsigned char attenuation) -{ - pcm1772_write_reg(0x01, attenuation); /* left channel */ - debug ("PCM1772 attenuation left set to %d.\n", attenuation); - pcm1772_write_reg(0x02, attenuation); /* right channel */ - debug ("PCM1772 attenuation right set to %d.\n", attenuation); -} - -void amplifier_init(void) -{ - static int init_done = 0; - int i; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - /* Do this only once, because of the long time delay */ - if (!init_done) { - /* configure PCM1772 audio format as I2S */ - pcm1772_write_reg(0x03, 0x01); - /* enable audio amplifier */ - gpio->sint_gpioe |= 0x02; /* PSC3_5 as GPIO */ - gpio->sint_ode &= ~0x02; /* PSC3_5 is not open Drain */ - gpio->sint_dvo &= ~0x02; /* PSC3_5 is LOW */ - gpio->sint_ddr |= 0x02; /* PSC3_5 as output */ - /* - * wait some time to allow amplifier to recover from shutdown - * mode. - */ - for(i = 0; i < 350; i++) - udelay(1000); - /* - * The used amplifier (LM4867) has a so called "pop and click" - * elmination filter. The input signal of the amplifier must - * exceed a certain level once after power up to activate the - * generation of the output signal. This is achieved by - * sending a low frequent (nearly inaudible) sawtooth with a - * sufficient signal level. - */ - set_attenuation(50); - i2s_sawtooth (200, 5, LEFT_RIGHT); - init_done = 1; - } -} - -static void i2s_init(void) -{ - unsigned long i; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */ - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - psc->sicr = 0x22E00000; /* 16 bit data; I2S */ - - *(vu_long *)(CFG_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK - * 5.617 MHz */ - *(vu_long *)(CFG_MBAR + 0x214) |= 0x00000040; /* CDM clock enable - * register */ - psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */ - psc->ctur = 0x0F; /* 16 bit frame width */ - - for(i=0;i<128;i++) - { - psc->psc_buffer_32 = 0; /* clear tx fifo */ - } -} - -static int i2s_play_wave(unsigned long addr, unsigned long len) -{ - unsigned long i; - unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip - * wav header*/ - unsigned char swapped[4]; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; - - /* - * play wave file in memory; bytes/words are be swapped - */ - psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); - - for(i = 0;i < (len / 4); i++) { - swapped[3]=*wave_file++; - swapped[2]=*wave_file++; - swapped[1]=*wave_file++; - swapped[0]=*wave_file++; - psc->psc_buffer_32 = *((unsigned long*)swapped); - while (psc->tfnum > 400) { - if(ctrlc()) - return 0; - } - } - while (psc->tfnum > 0); /* wait for fifo empty */ - udelay (100); - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - return 0; -} - -static int i2s_sawtooth(unsigned long duration, unsigned int freq, - unsigned int channel) -{ - long i,j; - unsigned long data; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; - - psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); - - /* - * Generate sawtooth. Start with middle level up to highest level. Then - * go to lowest level and back to middle level. - */ - for(j = 0; j < ((duration * freq) / 1000); j++) { - for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4)))) { - data = (i & 0xFFFF); - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) { - data = (i & 0xFFFF); - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) { - data = (i & 0xFFFF); - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - } - while (psc->tfnum > 0); /* wait for fifo empty */ - udelay (100); - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - - return 0; -} - -static int i2s_squarewave(unsigned long duration, unsigned int freq, - unsigned int channel) -{ - long i,j; - unsigned long data; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; - - psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); - - /* - * Generate sqarewave. Start with high level, duty cycle 1:1. - */ - for(j = 0; j < ((duration * freq) / 1000); j++) { - for(i = 0; i < (44100/(freq*2)); i ++) { - data = 0x7FFF; - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - for(i = 0; i < (44100/(freq*2)); i ++) { - data = 0x8000; - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - } - while (psc->tfnum > 0); /* wait for fifo empty */ - udelay (100); - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - - return 0; -} - -static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned long reg, val, duration; - char *tmp; - unsigned int freq, channel; - unsigned char volume; - int rcode = 1; - -#ifdef CONFIG_STK52XX_REV100 - printf ("Revision 100 of STK52XX not supported!\n"); - return 1; -#endif - spi_init(); - i2s_init(); - amplifier_init(); - - if ((tmp = getenv ("volume")) != NULL) { - volume = simple_strtoul (tmp, NULL, 10); - } else { - volume = DEFAULT_VOL; - } - set_attenuation(volume); - - switch (argc) { - case 0: - case 1: - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - case 2: - if (strncmp(argv[1],"saw",3) == 0) { - printf ("Play sawtooth\n"); - rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - printf ("Play squarewave\n"); - rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } - - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - case 3: - if (strncmp(argv[1],"saw",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - printf ("Play sawtooth\n"); - rcode = i2s_sawtooth (duration, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - printf ("Play squarewave\n"); - rcode = i2s_squarewave (duration, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - case 4: - if (strncmp(argv[1],"saw",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - printf ("Play sawtooth\n"); - rcode = i2s_sawtooth (duration, freq, - LEFT_RIGHT); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - printf ("Play squarewave\n"); - rcode = i2s_squarewave (duration, freq, - LEFT_RIGHT); - return rcode; - } else if (strcmp(argv[1],"pcm1772") == 0) { - reg = simple_strtoul(argv[2], NULL, 10); - val = simple_strtoul(argv[3], NULL, 10); - printf("Set PCM1772 %lu. %lu\n", reg, val); - pcm1772_write_reg((uchar)reg, (uchar)val); - return 0; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - case 5: - if (strncmp(argv[1],"saw",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - if (strncmp(argv[4],"l",1) == 0) - channel = LEFT; - else if (strncmp(argv[4],"r",1) == 0) - channel = RIGHT; - else - channel = LEFT_RIGHT; - printf ("Play squarewave\n"); - rcode = i2s_sawtooth (duration, freq, - channel); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - if (strncmp(argv[4],"l",1) == 0) - channel = LEFT; - else if (strncmp(argv[4],"r",1) == 0) - channel = RIGHT; - else - channel = LEFT_RIGHT; - printf ("Play squarewave\n"); - rcode = i2s_squarewave (duration, freq, - channel); - return rcode; - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - printf ("Usage:\nsound cmd [arg1] [arg2] ...\n"); - return 1; -} - -static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned long length, addr; - unsigned char volume; - int rcode = 1; - char *tmp; - -#ifdef CONFIG_STK52XX_REV100 - printf ("Revision 100 of STK52XX not supported!\n"); - return 1; -#endif - spi_init(); - i2s_init(); - amplifier_init(); - - switch (argc) { - - case 3: - length = simple_strtoul(argv[2], NULL, 16); - addr = simple_strtoul(argv[1], NULL, 16); - break; - - case 2: - if ((tmp = getenv ("filesize")) != NULL) { - length = simple_strtoul (tmp, NULL, 16); - } else { - puts ("No filesize provided\n"); - return 1; - } - addr = simple_strtoul(argv[1], NULL, 16); - - case 1: - if ((tmp = getenv ("filesize")) != NULL) { - length = simple_strtoul (tmp, NULL, 16); - } else { - puts ("No filesize provided\n"); - return 1; - } - if ((tmp = getenv ("loadaddr")) != NULL) { - addr = simple_strtoul (tmp, NULL, 16); - } else { - puts ("No loadaddr provided\n"); - return 1; - } - break; - - default: - printf("Usage:\nwav usage); - return 1; - } - - if ((tmp = getenv ("volume")) != NULL) { - volume = simple_strtoul (tmp, NULL, 10); - } else { - volume = DEFAULT_VOL; - } - set_attenuation(volume); - - printf("Beep on "); - if (channel == LEFT) - printf ("left "); - else if (channel == RIGHT) - printf ("right "); - else - printf ("left and right "); - printf ("channel\n"); - - rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel); - - return rcode; -} - -void led_init(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - /* configure PSC3 for SPI and GPIO */ - gpio->port_config &= ~(0x00000F00); - gpio->port_config |= 0x00000800; - - gpio->simple_gpioe &= ~(0x00000F00); - gpio->simple_gpioe |= 0x00000F00; - - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000F00; - - /* configure timer 4-7 for simple GPIO output */ - gpt->gpt4.emsr |= 0x00000024; - gpt->gpt5.emsr |= 0x00000024; - gpt->gpt6.emsr |= 0x00000024; - gpt->gpt7.emsr |= 0x00000024; - - - /* enable SM501 GPIO control (in both power modes) */ - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - - /* configure SM501 gpio pins 24-27 as output */ - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24); - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24); - - /* configure SM501 gpio pins 48-51 as output */ - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16); -} - -/* - * return 1 if led number unknown - * return 0 else - */ -int do_led(char *argv[]) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - switch (simple_strtoul(argv[2], NULL, 10)) { - - case 0: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 8); - } else { - gpio->simple_dvo &= ~(1 << 8); - } - break; - - case 1: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 9); - } else { - gpio->simple_dvo &= ~(1 << 9); - } - break; - - case 2: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 10); - } else { - gpio->simple_dvo &= ~(1 << 10); - } - break; - - case 3: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 11); - } else { - gpio->simple_dvo &= ~(1 << 11); - } - break; - - case 4: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt4.emsr |= (1 << 4); - } else { - gpt->gpt4.emsr &= ~(1 << 4); - } - break; - - case 5: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt5.emsr |= (1 << 4); - } else { - gpt->gpt5.emsr &= ~(1 << 4); - } - break; - - case 6: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt6.emsr |= (1 << 4); - } else { - gpt->gpt6.emsr &= ~(1 << 4); - } - break; - - case 7: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt7.emsr |= (1 << 4); - } else { - gpt->gpt7.emsr &= ~(1 << 4); - } - break; - - case 24: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 24); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 24); - } - break; - - case 25: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 25); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 25); - } - break; - - case 26: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 26); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 26); - } - break; - - case 27: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 27); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 27); - } - break; - - case 48: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 16); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 16); - } - break; - - case 49: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 17); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 17); - } - break; - - case 50: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 18); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 18); - } - break; - - case 51: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 19); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 19); - } - break; - - default: - printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]); - return 1; - } - - return 0; -} - -/* - * return 1 on CAN initialization failure - * return 0 if no failure - */ -int can_init(void) -{ - static int init_done = 0; - int i; - struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); - struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); - - /* GPIO configuration of the CAN pins is done in TQM5200.h */ - - if (!init_done) { - /* init CAN 1 */ - can1->canctl1 |= 0x80; /* CAN enable */ - udelay(100); - - i = 0; - can1->canctl0 |= 0x02; /* sleep mode */ - /* wait until sleep mode reached */ - while (!(can1->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not enter sleep mode!\n", - __FUNCTION__); - return 1; - } - } - i = 0; - can1->canctl0 = 0x01; /* enter init mode */ - /* wait until init mode reached */ - while (!(can1->canctl1 & 0x01)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not enter init mode!\n", - __FUNCTION__); - return 1; - } - } - can1->canctl1 = 0x80; - can1->canctl1 |= 0x40; - can1->canbtr0 = 0x0F; - can1->canbtr1 = 0x7F; - can1->canidac &= ~(0x30); - can1->canidar1 = 0x00; - can1->canidar3 = 0x00; - can1->canidar5 = 0x00; - can1->canidar7 = 0x00; - can1->canidmr0 = 0xFF; - can1->canidmr1 = 0xFF; - can1->canidmr2 = 0xFF; - can1->canidmr3 = 0xFF; - can1->canidmr4 = 0xFF; - can1->canidmr5 = 0xFF; - can1->canidmr6 = 0xFF; - can1->canidmr7 = 0xFF; - - i = 0; - can1->canctl0 &= ~(0x01); /* leave init mode */ - can1->canctl0 &= ~(0x02); - /* wait until init and sleep mode left */ - while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not leave init/sleep mode!\n", - __FUNCTION__); - return 1; - } - } - - /* init CAN 2 */ - can2->canctl1 |= 0x80; /* CAN enable */ - udelay(100); - - i = 0; - can2->canctl0 |= 0x02; /* sleep mode */ - /* wait until sleep mode reached */ - while (!(can2->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not enter sleep mode!\n", - __FUNCTION__); - return 1; - } - } - i = 0; - can2->canctl0 = 0x01; /* enter init mode */ - /* wait until init mode reached */ - while (!(can2->canctl1 & 0x01)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not enter init mode!\n", - __FUNCTION__); - return 1; - } - } - can2->canctl1 = 0x80; - can2->canctl1 |= 0x40; - can2->canbtr0 = 0x0F; - can2->canbtr1 = 0x7F; - can2->canidac &= ~(0x30); - can2->canidar1 = 0x00; - can2->canidar3 = 0x00; - can2->canidar5 = 0x00; - can2->canidar7 = 0x00; - can2->canidmr0 = 0xFF; - can2->canidmr1 = 0xFF; - can2->canidmr2 = 0xFF; - can2->canidmr3 = 0xFF; - can2->canidmr4 = 0xFF; - can2->canidmr5 = 0xFF; - can2->canidmr6 = 0xFF; - can2->canidmr7 = 0xFF; - can2->canctl0 &= ~(0x01); /* leave init mode */ - can2->canctl0 &= ~(0x02); - - i = 0; - /* wait until init mode left */ - while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not leave init/sleep mode!\n", - __FUNCTION__); - return 1; - } - } - init_done = 1; - } - return 0; -} - -/* - * return 1 on CAN failure - * return 0 if no failure - */ -int do_can(char *argv[]) -{ - int i; - struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); - struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); - - /* send a message on CAN1 */ - can1->cantbsel = 0x01; - can1->cantxfg.idr[0] = 0x55; - can1->cantxfg.idr[1] = 0x00; - can1->cantxfg.idr[1] &= ~0x8; - can1->cantxfg.idr[1] &= ~0x10; - can1->cantxfg.dsr[0] = 0xCC; - can1->cantxfg.dlr = 1; - can1->cantxfg.tbpr = 0; - can1->cantflg = 0x01; - - i = 0; - while ((can1->cantflg & 0x01) == 0) { - i++; - if (i == 10) { - printf ("%s: CAN1 send timeout, " - "can not send message!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - udelay(1000); - - i = 0; - while (!(can2->canrflg & 0x01)) { - i++; - if (i == 10) { - printf ("%s: CAN2 receive timeout, " - "no message received!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - - if (can2->canrxfg.dsr[0] != 0xCC) { - printf ("%s: CAN2 receive error, " - "data mismatch!\n", - __FUNCTION__); - return 1; - } - - /* send a message on CAN2 */ - can2->cantbsel = 0x01; - can2->cantxfg.idr[0] = 0x55; - can2->cantxfg.idr[1] = 0x00; - can2->cantxfg.idr[1] &= ~0x8; - can2->cantxfg.idr[1] &= ~0x10; - can2->cantxfg.dsr[0] = 0xCC; - can2->cantxfg.dlr = 1; - can2->cantxfg.tbpr = 0; - can2->cantflg = 0x01; - - i = 0; - while ((can2->cantflg & 0x01) == 0) { - i++; - if (i == 10) { - printf ("%s: CAN2 send error, " - "can not send message!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - udelay(1000); - - i = 0; - while (!(can1->canrflg & 0x01)) { - i++; - if (i == 10) { - printf ("%s: CAN1 receive timeout, " - "no message received!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - - if (can1->canrxfg.dsr[0] != 0xCC) { - printf ("%s: CAN1 receive error 0x%02x\n", - __FUNCTION__, (can1->canrxfg.dsr[0])); - return 1; - } - - return 0; -} - -/* - * return 1 if rs232 port unknown - * return 2 on txd/rxd failure (only rs232 2) - * return 3 on rts/cts failure - * return 0 if no failure - */ -int do_rs232(char *argv[]) -{ - int error_status = 0; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; - - switch (simple_strtoul(argv[2], NULL, 10)) { - - case 1: - /* check RTS <-> CTS loop */ - /* set rts to 0 */ - psc1->op1 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 0) { - error_status = 3; - printf ("%s: failure at rs232_1, cts status is %d " - "(should be 0)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - - /* set rts to 1 */ - psc1->op0 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 1) { - error_status = 3; - printf ("%s: failure at rs232_1, cts status is %d " - "(should be 1)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - - break; - - case 2: - /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000500; - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000200) { - error_status = 2; - printf ("%s: failure at rs232_2, rxd status is %d " - "(should be 1)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000000) { - error_status = 2; - printf ("%s: failure at rs232_2, rxd status is %d " - "(should be 0)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000800) { - error_status = 3; - printf ("%s: failure at rs232_2, cts status is %d " - "(should be 1)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000000) { - error_status = 3; - printf ("%s: failure at rs232_2, cts status is %d " - "(should be 0)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - - /* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */ - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000F00; - break; - - default: - printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); - error_status = 1; - break; - } - - return error_status; -} - -static void sm501_backlight (unsigned int state) -{ - if (state == BL_ON) { - *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |= - (1 << 26) | (1 << 27); - } else if (state == BL_OFF) - *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= - ~((1 << 26) | (1 << 27)); -} - -int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int rcode; - -#ifdef CONFIG_STK52XX_REV100 - printf ("Revision 100 of STK52XX not supported!\n"); - return 1; -#endif - led_init(); - can_init(); - - switch (argc) { - - case 0: - case 1: - break; - - case 2: - if (strncmp (argv[1], "can", 3) == 0) { - rcode = do_can (argv); - if (rcode == 0) - printf ("OK\n"); - else - printf ("Error\n"); - return rcode; - } - break; - - case 3: - if (strncmp (argv[1], "rs232", 3) == 0) { - rcode = do_rs232 (argv); - if (rcode == 0) - printf ("OK\n"); - else - printf ("Error\n"); - return rcode; - } else if (strncmp (argv[1], "backlight", 4) == 0) { - if (strncmp (argv[2], "on", 2) == 0) { - sm501_backlight (BL_ON); - return 0; - } - else if (strncmp (argv[2], "off", 3) == 0) { - sm501_backlight (BL_OFF); - return 0; - } - } - break; - - case 4: - if (strcmp (argv[1], "led") == 0) { - return (do_led (argv)); - } - break; - - default: - break; - } - - printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n"); - return 1; -} - - -U_BOOT_CMD( - sound , 5, 1, cmd_sound, - "sound - Sound sub-system\n", - "saw [duration] [freq] [channel]\n" - " - generate sawtooth for 'duration' ms with frequency 'freq'\n" - " on left \"l\" or right \"r\" channel\n" - "sound square [duration] [freq] [channel]\n" - " - generate squarewave for 'duration' ms with frequency 'freq'\n" - " on left \"l\" or right \"r\" channel\n" - "pcm1772 reg val\n" -); - -U_BOOT_CMD( - wav , 3, 1, cmd_wav, - "wav - play wav file\n", - "[addr] [bytes]\n" - " - play wav file at address 'addr' with length 'bytes'\n" -); - -U_BOOT_CMD( - beep , 2, 1, cmd_beep, - "beep - play short beep\n", - "[channel]\n" - " - play short beep on \"l\"eft or \"r\"ight channel\n" -); - -U_BOOT_CMD( - fkt , 4, 1, cmd_fkt, - "fkt - Function test routines\n", - "led number on/off\n" - " - 'number's like printed on SKT52XX board\n" - "fkt can\n" - " - loopback plug for X83 required\n" - "fkt rs232 number\n" - " - loopback plug(s) for X2 required\n" - "fkt backlight on/off\n" - " - switch backlight on or off\n" -); -#endif /* CONFIG_STK52XX */ -#endif /* CFG_CMD_BSP */ diff --git a/board/tqm5200/config.mk b/board/tqm5200/config.mk deleted file mode 100644 index 585a99a..0000000 --- a/board/tqm5200/config.mk +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TQM5200 board: -# -# Valid values for TEXT_BASE are: -# -# 0xFC000000 boot low (standard configuration with room for max 64 MByte -# Flash ROM) -# 0x00100000 boot from RAM (for testing only) -# - -ifndef TEXT_BASE -## Standard: boot low -TEXT_BASE = 0xFC000000 -## For testing: boot from RAM -# TEXT_BASE = 0x00100000 -endif - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/tqm5200/flash.c b/board/tqm5200/flash.c deleted file mode 100644 index af4d78a..0000000 --- a/board/tqm5200/flash.c +++ /dev/null @@ -1,497 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * CPU to flash interface is 32-bit, so make declaration accordingly - */ -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - extern void flash_preinit(void); - ulong flashbase = CFG_FLASH_BASE; - - flash_preinit(); - - /* Init: no FLASHes known */ - memset(&flash_info[0], 0, sizeof(flash_info_t)); - - flash_info[0].size = - flash_get_size((FPW *)flashbase, &flash_info[0]); - - size = flash_info[0].size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -#endif - - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && info->start[0] <= base && - base <= info->start[0] + info->size - 1) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMLV128U: - printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - int i; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - udelay(100); - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - debug ("Manufacturer: AMD (Spansion)\n"); - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - debug ("Manufacturer: Intel (not supported yet)\n"); - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { - - case (FPW)AMD_ID_LV160B: - debug ("Chip: AM29LV160MB\n"); - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - /* - * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all - * the other ones are 64 kB - */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for( i = 4; i < info->sector_count; i++ ) - info->start[i] = - base + (i * 2 * (64 << 10)) - 0x00060000; - break; /* => 4 MB */ - - case AMD_ID_MIRROR: - debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", - addr[14], addr[15]); - - switch(addr[14]) { - case AMD_ID_LV128U_2: - if (addr[15] != AMD_ID_LV128U_3) { - debug ("Chip: AM29LVxxxM -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } else { - debug ("Chip: AM29LV128M\n"); - info->flash_id += FLASH_AMLV128U; - info->sector_count = 256; - info->size = 0x02000000; - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x20000; - } - } - break; /* => 32 MB */ - default: - debug ("Chip: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - /* - * Get lower word aligned address. Assumes 32 bit flash bus width. - */ - wp = (addr & ~3); - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word_amd(info, (FPW *)wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - return (1); - } - } - return (0); -} diff --git a/board/tqm5200/mt48lc16m16a2-75.h b/board/tqm5200/mt48lc16m16a2-75.h deleted file mode 100644 index 3f1e169..0000000 --- a/board/tqm5200/mt48lc16m16a2-75.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 0 /* is SDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ -/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ -#define SDRAM_CONFIG2 0x8AD70000 -/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c deleted file mode 100644 index 6aad920..0000000 --- a/board/tqm5200/tqm5200.c +++ /dev/null @@ -1,673 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_VIDEO_SM501 -#include -#endif - -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -#include "mt48lc16m16a2-75.h" -#endif - -#ifdef CONFIG_PS2MULT -void ps2mult_early_init(void); -#endif - -#ifndef CFG_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. - */ - -#if defined(CONFIG_MPC5200) -long int initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ - - /* find RAM size using SDRAM CS1 only */ - sdram_start(0); - test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); - sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CFG_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CFG_RAMBOOT */ - -/* return dramsize + dramsize2; */ - return dramsize; -} - -#elif defined(CONFIG_MGT5100) - -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CFG_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CFG_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - -int checkboard (void) -{ -#if defined (CONFIG_AEVFIFO) - puts ("Board: AEVFIFO\n"); - return 0; -#endif -#if defined (CONFIG_TQM5200_AA) - puts ("Board: TQM5200-AA (TQ-Components GmbH)\n"); -#elif defined (CONFIG_TQM5200_AB) - puts ("Board: TQM5200-AB (TQ-Components GmbH)\n"); -#elif defined (CONFIG_TQM5200_AC) - puts ("Board: TQM5200-AC (TQ-Components GmbH)\n"); -#elif defined (CONFIG_TQM5200) - puts ("Board: TQM5200 (TQ-Components GmbH)\n"); -#endif -#if defined (CONFIG_STK52XX) - puts (" on a STK52XX baseboard\n"); -#endif - - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) - -#if defined (CONFIG_MINIFAP) -#define SM501_POWER_MODE0_GATE 0x00000040UL -#define SM501_POWER_MODE1_GATE 0x00000048UL -#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL -#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL -#define SM501_GPIO_DATA_HIGH 0x00010004UL -#define SM501_GPIO_51 0x00080000UL -#else -#define GPIO_PSC1_4 0x01000000UL -#endif - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - -#if defined (CONFIG_MINIFAP) - /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */ - - /* enable GPIO control (in both power modes) */ - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - /* configure GPIO51 as output */ - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= - SM501_GPIO_51; -#else - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; -#endif -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - -#if defined (CONFIG_MINIFAP) - if (idereset) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~SM501_GPIO_51; - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - SM501_GPIO_51; - } -#else - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; - } -#endif -} -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ - -#ifdef CONFIG_POST -/* - * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 - * is left open, no keypress is detected. - */ -int post_hotkeys_pressed(void) -{ - struct mpc5xxx_gpio *gpio; - - gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; - - /* - * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in - * CODEC or UART mode. Consumer IrDA should still be possible. - */ - gpio->port_config &= ~(0x07000000); - gpio->port_config |= 0x03000000; - - /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ - gpio->simple_gpioe |= 0x20000000; - - /* Configure GPIO_IRDA_1 as input */ - gpio->simple_ddr &= ~(0x20000000); - - return ((gpio->simple_ival & 0x20000000) ? 0 : 1); -} -#endif - -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - -void post_word_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); - - *save_addr = a; -} - -ulong post_word_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); - - return *save_addr; -} -#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ - -#ifdef CONFIG_PS2MULT -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ - ps2mult_early_init(); - return (0); -} -#endif -#endif /* CONFIG_PS2MULT */ - -#if defined(CONFIG_CS_AUTOCONF) -int last_stage_init (void) -{ - /* - * auto scan for really existing devices and re-set chip select - * configuration. - */ - u16 save, tmp; - int restore; - - /* - * Check for SRAM and SRAM size - */ - - /* save original SRAM content */ - save = *(volatile u16 *)CFG_CS2_START; - restore = 1; - - /* write test pattern to SRAM */ - *(volatile u16 *)CFG_CS2_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in SRAM detection\n"); - - if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) { - /* no SRAM at all, disable cs */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); - *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; - *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; - restore = 0; - __asm__ volatile ("sync"); - } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) { - /* make sure that we access a mirrored address */ - *(volatile u16 *)CFG_CS2_START = 0x1111; - __asm__ volatile ("sync"); - if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) { - /* SRAM size = 512 kByte */ - *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, - 0x80000); - __asm__ volatile ("sync"); - puts ("SRAM: 512 kB\n"); - } - else - puts ("!! possible error in SRAM detection\n"); - } else { - puts ("SRAM: 1 MB\n"); - } - /* restore origianl SRAM content */ - if (restore) { - *(volatile u16 *)CFG_CS2_START = save; - __asm__ volatile ("sync"); - } - - /* - * Check for Grafic Controller - */ - - /* save origianl FB content */ - save = *(volatile u16 *)CFG_CS1_START; - restore = 1; - - /* write test pattern to FB memory */ - *(volatile u16 *)CFG_CS1_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in grafic controller detection\n"); - - if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { - /* no grafic controller at all, disable cs */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); - *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; - *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; - restore = 0; - __asm__ volatile ("sync"); - } else { - puts ("VGA: SMI501 (Voyager) with 8 MB\n"); - } - /* restore origianl FB content */ - if (restore) { - *(volatile u16 *)CFG_CS1_START = save; - __asm__ volatile ("sync"); - } - - return 0; -} -#endif /* CONFIG_CS_AUTOCONF */ - -#ifdef CONFIG_VIDEO_SM501 - -#define DISPLAY_WIDTH 640 -#define DISPLAY_HEIGHT 480 - -#ifdef CONFIG_VIDEO_SM501_8BPP -#error CONFIG_VIDEO_SM501_8BPP not supported. -#endif /* CONFIG_VIDEO_SM501_8BPP */ - -#ifdef CONFIG_VIDEO_SM501_16BPP -#error CONFIG_VIDEO_SM501_16BPP not supported. -#endif /* CONFIG_VIDEO_SM501_16BPP */ -#ifdef CONFIG_VIDEO_SM501_32BPP -static const SMI_REGS init_regs [] = -{ -#if 0 /* CRT only */ - {0x00004, 0x0}, - {0x00048, 0x00021807}, - {0x0004C, 0x10090a01}, - {0x00054, 0x1}, - {0x00040, 0x00021807}, - {0x00044, 0x10090a01}, - {0x00054, 0x0}, - {0x80200, 0x00010000}, - {0x80204, 0x0}, - {0x80208, 0x0A000A00}, - {0x8020C, 0x02fa027f}, - {0x80210, 0x004a028b}, - {0x80214, 0x020c01df}, - {0x80218, 0x000201e9}, - {0x80200, 0x00013306}, -#else /* panel + CRT */ - {0x00004, 0x0}, - {0x00048, 0x00021807}, - {0x0004C, 0x091a0a01}, - {0x00054, 0x1}, - {0x00040, 0x00021807}, - {0x00044, 0x091a0a01}, - {0x00054, 0x0}, - {0x80000, 0x0f013106}, - {0x80004, 0xc428bb17}, - {0x8000C, 0x00000000}, - {0x80010, 0x0a000a00}, - {0x80014, 0x02800000}, - {0x80018, 0x01e00000}, - {0x8001C, 0x00000000}, - {0x80020, 0x01e00280}, - {0x80024, 0x02fa027f}, - {0x80028, 0x004a028b}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201e9}, - {0x80200, 0x00010000}, -#endif - {0, 0} -}; -#endif /* CONFIG_VIDEO_SM501_32BPP */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { -#if defined (CONFIG_TQM5200_AA) - strcpy (info, " Board: TQM5200-AA (TQ-Components GmbH)"); -#elif defined (CONFIG_TQM5200_AB) - strcpy (info, " Board: TQM5200-AB (TQ-Components GmbH)"); -#elif defined (CONFIG_TQM5200_AC) - strcpy (info, " Board: TQM5200-AC (TQ-Components GmbH)"); -#elif defined (CONFIG_TQM5200) - strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); -#else -#error No supported board selected -#endif -#if defined (CONFIG_STK52XX) - } else if (line_number == 2) { - strcpy (info, " on a STK52XX baseboard"); -#endif - } - else { - info [0] = '\0'; - } -} -#endif - -/* - * Returns SM501 register base address. First thing called in the - * driver. Checks if SM501 is physically present. - */ -unsigned int board_video_init (void) -{ - u16 save, tmp; - int restore, ret; - - /* - * Check for Grafic Controller - */ - - /* save origianl FB content */ - save = *(volatile u16 *)CFG_CS1_START; - restore = 1; - - /* write test pattern to FB memory */ - *(volatile u16 *)CFG_CS1_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in grafic controller detection\n"); - - if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { - /* no grafic controller found */ - restore = 0; - ret = 0; - } else { - ret = SM501_MMIO_BASE; - } - - if (restore) { - *(volatile u16 *)CFG_CS1_START = save; - __asm__ volatile ("sync"); - } - return ret; -} - -/* - * Returns SM501 framebuffer address - */ -unsigned int board_video_get_fb (void) -{ - return SM501_FB_BASE; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen (unsigned int base) -{ -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs (void) -{ - return init_regs; -} - -int board_get_width (void) -{ - return DISPLAY_WIDTH; -} - -int board_get_height (void) -{ - return DISPLAY_HEIGHT; -} - -#endif /* CONFIG_VIDEO_SM501 */ diff --git a/board/tqm5200/u-boot.lds b/board/tqm5200/u-boot.lds deleted file mode 100644 index 3cc2968..0000000 --- a/board/tqm5200/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/tqm8260/Makefile b/board/tqm8260/Makefile deleted file mode 100644 index c10b9fe..0000000 --- a/board/tqm8260/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o ../tqm8xx/load_sernum_ethaddr.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/tqm8260/config.mk b/board/tqm8260/config.mk deleted file mode 100644 index 1fe9952..0000000 --- a/board/tqm8260/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TQM8260 boards -# - -# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h -# for the "final" configuration, with U-Boot in flash, or the address -# in RAM where U-Boot is loaded at for debugging. -# -TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/tqm8260/flash.c b/board/tqm8260/flash.c deleted file mode 100644 index 056fe81..0000000 --- a/board/tqm8260/flash.c +++ /dev/null @@ -1,488 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AMD devices on the TQM8260 board - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define V_ULONG(a) (*(volatile unsigned long *)( a )) -#define V_BYTE(a) (*(volatile unsigned char *)( a )) - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ -void flash_reset (void) -{ - if (flash_info[0].flash_id != FLASH_UNKNOWN) { - V_ULONG (flash_info[0].start[0]) = 0x00F000F0; - V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0; - } -} - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (ulong baseaddr, flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - /* Write auto select command sequence and test FLASH answer */ - V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA; - V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055; - V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090; - V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA; - V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055; - V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090; - - flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */ - flashtest_l = V_ULONG (baseaddr + 4); - - switch ((int) flashtest_h) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - flashtest_h = V_ULONG (baseaddr + 8); /* device ID */ - flashtest_l = V_ULONG (baseaddr + 12); - if (flashtest_h != flashtest_l) { - info->flash_id = FLASH_UNKNOWN; - } else { - switch (flashtest_h) { - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00400000; - break; /* 4 * 1 MB = 4 MB */ - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; - break; /* 4 * 1 MB = 4 MB */ - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00800000; - break; /* 4 * 2 MB = 8 MB */ - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00800000; - break; /* 4 * 2 MB = 8 MB */ - case AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x02000000; - break; /* 4 * 8 MB = 32 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* no or unknown flash */ - } - } - - if (flashtest_h == AMD_ID_LV640U) { - - /* set up sector start adress table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = baseaddr + (i * 0x00040000); - - } else if (info->flash_id & FLASH_BTYPE) { - - /* set up sector start adress table (bottom sector type) */ - info->start[0] = baseaddr + 0x00000000; - info->start[1] = baseaddr + 0x00010000; - info->start[2] = baseaddr + 0x00018000; - info->start[3] = baseaddr + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000; - } - - } else { - - /* set up sector start adress table (top sector type) */ - i = info->sector_count - 1; - info->start[i--] = baseaddr + info->size - 0x00010000; - info->start[i--] = baseaddr + info->size - 0x00018000; - info->start[i--] = baseaddr + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = baseaddr + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - if ((V_ULONG (info->start[i] + 16) & 0x00010001) || - (V_ULONG (info->start[i] + 20) & 0x00010001)) { - info->protect[i] = 1; /* D0 = 1 if protected */ - } else { - info->protect[i] = 0; - } - } - - flash_reset (); - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* - * protect monitor and environment sectors - */ - -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - printf ("29LV800T (8 M, top sector)\n"); - break; - case FLASH_AM800B: - printf ("29LV800T (8 M, bottom sector)\n"); - break; - case FLASH_AM160T: - printf ("29LV160T (16 M, top sector)\n"); - break; - case FLASH_AM160B: - printf ("29LV160B (16 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: - printf ("29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: - printf ("29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: - printf ("29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: - printf ("29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AM640U: - printf ("29LV640D (64 M, uniform sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - V_ULONG (info->start[sect]) = 0x00300030; - V_ULONG (info->start[sect] + 4) = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 || - (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080) - { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - flash_reset (); - - printf (" done\n"); - return 0; -} - -static int write_dword (flash_info_t *, ulong, unsigned char *); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong dp; - static unsigned char bb[8]; - int i, l, rc, cc = cnt; - - dp = (addr & ~7); /* get lower dword aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - dp) != 0) { - for (i = 0; i < 8; i++) - bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++; - if ((rc = write_dword (info, dp, bb)) != 0) { - return (rc); - } - dp += 8; - cc -= 8 - l; - } - - /* - * handle word aligned part - */ - while (cc >= 8) { - if ((rc = write_dword (info, dp, src)) != 0) { - return (rc); - } - dp += 8; - src += 8; - cc -= 8; - } - - if (cc <= 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - for (i = 0; i < 8; i++) { - bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i); - } - return (write_dword (info, dp, bb)); -} - -/*----------------------------------------------------------------------- - * Write a dword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) -{ - ulong start, cl, ch; - int flag, i; - - for (ch = 0, i = 0; i < 4; i++) - ch = (ch << 8) + *pdata++; /* high word */ - for (cl = 0, i = 0; i < 4; i++) - cl = (cl << 8) + *pdata++; /* low word */ - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & ch) != ch - || (*((vu_long *) (dest + 4)) & cl) != cl) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0; - V_ULONG (dest) = ch; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0; - V_ULONG (dest + 4) = cl; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) || - ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/tqm8260/tqm8260.c b/board/tqm8260/tqm8260.c deleted file mode 100644 index 029863b..0000000 --- a/board/tqm8260/tqm8260.c +++ /dev/null @@ -1,368 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ -#if defined(CONFIG_SOFT_I2C) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (!i || strncmp (str, "TQM82", 5)) { - puts ("### No HW ID - assuming TQM8260\n"); - return (0); - } - - puts (str); - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; - orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CFG_RAMBOOT - long size8, size9; -#endif - long psize, lsize; - - psize = 16 * 1024 * 1024; - lsize = 0; - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - -#if 0 /* Just for debugging */ -#define prt_br_or(brX,orX) do { \ - ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ - ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ - printf ("\n" \ - #brX " 0x%08x " #orX " 0x%08x " \ - "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ - memctl->memc_ ## brX, memctl->memc_ ## orX, \ - start, start+sizem, (sizem+1)>>20); \ - } while (0) - prt_br_or (br0, or0); - prt_br_or (br1, or1); - prt_br_or (br2, or2); - prt_br_or (br3, or3); -#endif - -#ifndef CFG_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, - (uchar *) CFG_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL - %ld MB, ", psize >> 20); - } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); - printf ("(60x:8COL - %ld MB, ", psize >> 20); - } - - /* Local SDRAM setup: - */ -#ifdef CFG_INIT_LOCAL_SDRAM - memctl->memc_lsrt = CFG_LSRT; - size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL, - (uchar *) SDRAM_BASE2_PRELIM); - - if (size8 < size9) { - lsize = size9; - printf ("Local:9COL - %ld MB) using ", lsize >> 20); - } else { - lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - printf ("Local:8COL - %ld MB) using ", lsize >> 20); - } - -#if 0 - /* Set up BR2 so that the local SDRAM goes - * right after the 60x SDRAM - */ - memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) | - (CFG_SDRAM_BASE + psize); -#endif -#endif /* CFG_INIT_LOCAL_SDRAM */ -#endif /* CFG_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/tqm8260/u-boot.lds b/board/tqm8260/u-boot.lds deleted file mode 100644 index 05f29c6..0000000 --- a/board/tqm8260/u-boot.lds +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - common/environment.o(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/tqm834x/Makefile b/board/tqm834x/Makefile deleted file mode 100644 index 3ecc7d0..0000000 --- a/board/tqm834x/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o pci.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/tqm834x/config.mk b/board/tqm834x/config.mk deleted file mode 100644 index f172c4e..0000000 --- a/board/tqm834x/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x80000000 diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c deleted file mode 100644 index 5a23e6c..0000000 --- a/board/tqm834x/pci.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -#ifdef CONFIG_PCI - -/* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_tqm834x_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } - }, - {} -}; -#endif - -static struct pci_controller pci1_hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_tqm834x_config_table, -#endif -}; - - -/************************************************************************** - * pci_init_board() - * - * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since - * per TQM834x design physical connections to external devices (PCI sockets) - * are routed only to the PCI1 we do not account for the second one - this code - * supports PCI1 module only. Should support for the PCI2 be required in the - * future it needs a separate pci_controller structure (above) and handling - - * please refer to other boards' implementation for dual PCI host controllers, - * for example board/Marvell/db64360/pci.c, pci_init_board() - * - */ -void -pci_init_board(void) -{ - volatile immap_t * immr; - volatile clk8349_t * clk; - volatile law8349_t * pci_law; - volatile pot8349_t * pci_pot; - volatile pcictrl8349_t * pci_ctrl; - volatile pciconf8349_t * pci_conf; - u16 reg16; - u32 reg32; - struct pci_controller * hose; - - immr = (immap_t *)CFG_IMMRBAR; - clk = (clk8349_t *)&immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - - hose = &pci1_hose; - - /* - * Configure PCI controller and PCI_CLK_OUTPUT - */ - - /* - * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one - * line actually used for clocking all external PCI devices in TQM83xx. - * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for - * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 - * are known to hang the board; this issue is under investigation - * (13 oct 05) - */ - reg32 = OCCR_PCICOE1; -#if 0 - /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ - reg32 = 0xff000000; -#endif - if (clk->spmr & SPMR_CKID) { - /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR - * fields accordingly */ - reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); - - reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ - | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ - | OCCR_PCICD6 | OCCR_PCICD7); - } - - clk->occr = reg32; - udelay(2000); - - /* - * Release PCI RST Output signal - */ - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - udelay(2000); - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI1 mem space */ - pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); - - /* PCI1 IO space */ - pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 2, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - CONFIG_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose->region_count = 3; - - pci_setup_indirect(hose, - (CFG_IMMRBAR+0x8300), - (CFG_IMMRBAR+0x8304)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, - ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, - reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, - 0xffff); - pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, - 0x80); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -} -#endif /* CONFIG_PCI */ diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c deleted file mode 100644 index dada673..0000000 --- a/board/tqm834x/tqm834x.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IOSYNC asm("eieio") -#define ISYNC asm("isync") -#define SYNC asm("sync") -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define DDR_MAX_SIZE_PER_CS 0x20000000 - -#if defined(DDR_CASLAT_20) -#define TIMING_CASLAT TIMING_CFG1_CASLAT_20 -#define MODE_CASLAT DDR_MODE_CASLAT_20 -#else -#define TIMING_CASLAT TIMING_CFG1_CASLAT_25 -#define MODE_CASLAT DDR_MODE_CASLAT_25 -#endif - -#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \ - CSCONFIG_COL_BIT_9) - -/* Global variable used to store detected number of banks */ -int tqm834x_num_flash_banks; - -/* External definitions */ -ulong flash_get_size (ulong base, int banknum); -extern flash_info_t flash_info[]; -extern long spd_sdram (void); - -/* Local functions */ -static int detect_num_flash_banks(void); -static long int get_ddr_bank_size(short cs, volatile long *base); -static void set_cs_bounds(short cs, long base, long size); -static void set_cs_config(short cs, long config); -static void set_ddr_config(void); - -/* Local variable */ -static volatile immap_t *im = (immap_t *)CFG_IMMRBAR; - -/************************************************************************** - * Board initialzation after relocation to RAM. Used to detect the number - * of Flash banks on TQM834x. - */ -int board_early_init_r (void) { - /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */ - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return 0; - - /* detect the number of Flash banks */ - return detect_num_flash_banks(); -} - -/************************************************************************** - * DRAM initalization and size detection - */ -long int initdram (int board_type) -{ - long bank_size; - long size; - int cs; - - /* during size detection, set up the max DDRLAW size */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE; - im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); - - /* set CS bounds to maximum size */ - for(cs = 0; cs < 4; ++cs) { - set_cs_bounds(cs, - CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), - DDR_MAX_SIZE_PER_CS); - - set_cs_config(cs, INITIAL_CS_CONFIG); - } - - /* configure ddr controller */ - set_ddr_config(); - - udelay(200); - - /* enable DDR controller */ - im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | - SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR); - SYNC; - - /* size detection */ - debug("\n"); - size = 0; - for(cs = 0; cs < 4; ++cs) { - debug("\nDetecting Bank%d\n", cs); - - bank_size = get_ddr_bank_size(cs, - (volatile long*)(CFG_DDR_BASE + size)); - size += bank_size; - - debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20); - - /* exit if less than one bank */ - if(size < DDR_MAX_SIZE_PER_CS) break; - } - - return size; -} - -/************************************************************************** - * checkboard() - */ -int checkboard (void) -{ - puts("Board: TQM834x\n"); - -#ifdef CONFIG_PCI - DECLARE_GLOBAL_DATA_PTR; - volatile immap_t * immr; - u32 w, f; - - immr = (immap_t *)CFG_IMMRBAR; - if (!(immr->reset.rcwh & RCWH_PCIHOST)) { - printf("PCI: NOT in host mode..?!\n"); - return 0; - } - - /* get bus width */ - w = 32; - if (immr->reset.rcwh & RCWH_PCI64) - w = 64; - - /* get clock */ - f = gd->pci_clk; - - printf("PCI1: %d bit, %d MHz\n", w, f / 1000000); -#else - printf("PCI: disabled\n"); -#endif - return 0; -} - - -/************************************************************************** - * - * Local functions - * - *************************************************************************/ - -/************************************************************************** - * Detect the number of flash banks (1 or 2). Store it in - * a global variable tqm834x_num_flash_banks. - * Bank detection code based on the Monitor code. - */ -static int detect_num_flash_banks(void) -{ - typedef unsigned long FLASH_PORT_WIDTH; - typedef volatile unsigned long FLASH_PORT_WIDTHV; - FPWV *bank1_base; - FPWV *bank2_base; - FPW bank1_read; - FPW bank2_read; - ulong bank1_size; - ulong bank2_size; - ulong total_size; - - tqm834x_num_flash_banks = 2; /* assume two banks */ - - /* Get bank 1 and 2 information */ - bank1_size = flash_get_size(CFG_FLASH_BASE, 0); - debug("Bank1 size: %lu\n", bank1_size); - bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1); - debug("Bank2 size: %lu\n", bank2_size); - total_size = bank1_size + bank2_size; - - if (bank2_size > 0) { - /* Seems like we've got bank 2, but maybe it's mirrored 1 */ - - /* Set the base addresses */ - bank1_base = (FPWV *) (CFG_FLASH_BASE); - bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size); - - /* Put bank 2 into CFI command mode and read */ - bank2_base[0x55] = 0x00980098; - IOSYNC; - ISYNC; - bank2_read = bank2_base[0x10]; - - /* Read from bank 1 (it's in read mode) */ - bank1_read = bank1_base[0x10]; - - /* Reset Flash */ - bank1_base[0] = 0x00F000F0; - bank2_base[0] = 0x00F000F0; - - if (bank2_read == bank1_read) { - /* - * Looks like just one bank, but not sure yet. Let's - * read from bank 2 in autosoelect mode. - */ - bank2_base[0x0555] = 0x00AA00AA; - bank2_base[0x02AA] = 0x00550055; - bank2_base[0x0555] = 0x00900090; - IOSYNC; - ISYNC; - bank2_read = bank2_base[0x10]; - - /* Read from bank 1 (it's in read mode) */ - bank1_read = bank1_base[0x10]; - - /* Reset Flash */ - bank1_base[0] = 0x00F000F0; - bank2_base[0] = 0x00F000F0; - - if (bank2_read == bank1_read) { - /* - * In both CFI command and autoselect modes, - * we got the some data reading from Flash. - * There is only one mirrored bank. - */ - tqm834x_num_flash_banks = 1; - total_size = bank1_size; - } - } - } - - debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks); - - /* set OR0 and BR0 */ - im->lbus.bank[0].or = CFG_OR_TIMING_FLASH | - (-(total_size) & OR_GPCM_AM); - im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) | - (BR_MS_GPCM | BR_PS_32 | BR_V); - - return (0); -} - -/************************************************************************* - * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly. - */ -static long int get_ddr_bank_size(short cs, volatile long *base) -{ - /* This array lists all valid DDR SDRAM configurations, with - * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM). - * The last entry has to to have size equal 0 and is igonred during - * autodection. Bank sizes must be in increasing order of size - */ - struct { - long row; - long col; - long size; - } conf[] = { - {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20}, - {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20}, - {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20}, - {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20}, - {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20}, - {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20}, - {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20}, - {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20}, - {0, 0, 0} - }; - - int i; - int detected; - long size; - - detected = -1; - for(i = 0; conf[i].size != 0; ++i) { - - /* set sdram bank configuration */ - set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row); - - debug("Getting RAM size...\n"); - size = get_ram_size(base, DDR_MAX_SIZE_PER_CS); - - if((size == conf[i].size) && (i == detected + 1)) - detected = i; - - debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n", - conf[i].row, - conf[i].col, - conf[i].size >> 20, - base, - size >> 20); - } - - if(detected == -1){ - /* disable empty cs */ - debug("\nNo valid configurations for CS%d, disabling...\n", cs); - set_cs_config(cs, 0); - return 0; - } - - debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n", - conf[detected].row, conf[detected].col, conf[detected].size >> 20, base); - - /* configure cs ro detected params */ - set_cs_config(cs, CSCONFIG_EN | conf[detected].row | - conf[detected].col); - - set_cs_bounds(cs, (long)base, conf[detected].size); - - return(conf[detected].size); -} - -/************************************************************************** - * Sets DDR bank CS bounds. - */ -static void set_cs_bounds(short cs, long base, long size) -{ - debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs); - if(size == 0){ - im->ddr.csbnds[cs].csbnds = 0x00000000; - } else { - im->ddr.csbnds[cs].csbnds = - ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((base + size - 1) >> CSBNDS_EA_SHIFT) & - CSBNDS_EA); - } - SYNC; -} - -/************************************************************************** - * Sets DDR banks CS configuration. - * config == 0x00000000 disables the CS. - */ -static void set_cs_config(short cs, long config) -{ - debug("Setting config %08x for cs %d\n", config, cs); - im->ddr.cs_config[cs] = config; - SYNC; -} - -/************************************************************************** - * Sets DDR clocks, timings and configuration. - */ -static void set_ddr_config(void) { - /* clock control */ - im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN | - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; - SYNC; - - /* timing configuration */ - im->ddr.timing_cfg_1 = - (4 << TIMING_CFG1_PRETOACT_SHIFT) | - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | - (4 << TIMING_CFG1_ACTTORW_SHIFT) | - (5 << TIMING_CFG1_REFREC_SHIFT) | - (3 << TIMING_CFG1_WRREC_SHIFT) | - (3 << TIMING_CFG1_ACTTOACT_SHIFT) | - (1 << TIMING_CFG1_WRTORD_SHIFT) | - (TIMING_CFG1_CASLAT & TIMING_CASLAT); - - im->ddr.timing_cfg_2 = - TIMING_CFG2_CPO_DEF | - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT); - SYNC; - - /* don't enable DDR controller yet */ - im->ddr.sdram_cfg = - SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR; - SYNC; - - /* Set SDRAM mode */ - im->ddr.sdram_mode = - ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) << - SDRAM_MODE_ESD_SHIFT) | - ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) << - SDRAM_MODE_SD_SHIFT) | - ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) & - MODE_CASLAT); - SYNC; - - /* Set fast SDRAM refresh rate */ - im->ddr.sdram_interval = - (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | - (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); - SYNC; -} diff --git a/board/tqm834x/u-boot.lds b/board/tqm834x/u-boot.lds deleted file mode 100644 index 020cfa6..0000000 --- a/board/tqm834x/u-boot.lds +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc83xx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/tqm85xx/Makefile b/board/tqm85xx/Makefile deleted file mode 100644 index 3933d46..0000000 --- a/board/tqm85xx/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o sdram.o -SOBJS := init.o -#SOBJS := - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/tqm85xx/config.mk b/board/tqm85xx/config.mk deleted file mode 100644 index 52e84ad..0000000 --- a/board/tqm85xx/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright 2004 Freescale Semiconductor. -# Modified by Xianghua Xiao, X.Xiao@motorola.com -# (C) Copyright 2002,Motorola Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# tqm85xx board -# default CCARBAR is at 0xff700000 -# assume U-Boot is less than 256k -# -TEXT_BASE = 0xfffc0000 diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S deleted file mode 100644 index 1f61038..0000000 --- a/board/tqm85xx/init.S +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2002,2003, Motorola Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - - -/* - * TLB0 and TLB1 Entries - * - * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. - * However, CCSRBAR is then relocated to CFG_CCSRBAR right after - * these TLB entries are established. - * - * The TLB entries for DDR are dynamically setup in spd_sdram() - * and use TLB1 Entries 8 through 15 as needed according to the - * size of DDR memory. - * - * MAS0: tlbsel, esel, nv - * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, sharen, x0, x1, w, i, m, g, e - * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr - */ - -#define entry_start \ - mflr r1 ; \ - bl 0f ; - -#define entry_end \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - - - .section .bootpg, "ax" - .globl tlb1_entry -tlb1_entry: - entry_start - - /* - * Number of TLB0 and TLB1 entries in the following table - */ - .long 13 - - /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization - * - * Use four 4K TLB0 entries. These entries must be cacheable - * as they provide the bootstrap memory before the memory - * controler and real memory have been configured. - * - * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, - * and must not collide with other TLB0 entries. - */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - - /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH - * Out of reset this entry is only 4K. - */ - .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) - .long TLB1_MAS0(1, 0, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - .long TLB1_MAS0(1, 5, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 6: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - .long TLB1_MAS0(1, 6, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 7+8: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) - .long TLB1_MAS0(1, 8, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1) - - entry_end - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) - -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -/* - * Rapid IO at 0xc000_0000 for 512 M - */ -#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - .long 0x05 - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4 - entry_end diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c deleted file mode 100644 index 9c1f087..0000000 --- a/board/tqm85xx/sdram.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include - -struct sdram_conf_s { - unsigned long size; - unsigned long reg; -}; - -typedef struct sdram_conf_s sdram_conf_t; - -sdram_conf_t ddr_cs_conf[] = { - {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ - {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ - {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ - {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ -}; - -#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) - -int cas_latency(void); - -/* - * Autodetect onboard DDR SDRAM on 85xx platforms - * - * NOTE: Some of the hardcoded values are hardware dependant, - * so this should be extended for other future boards - * using this routine! - */ -long int sdram_setup(int casl) -{ - int i; - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr; - unsigned long cfg_ddr_timing1; - unsigned long cfg_ddr_mode; - - /* - * Disable memory controller. - */ - ddr->cs0_config = 0; - ddr->sdram_cfg = 0; - - switch (casl) { - case 20: - cfg_ddr_timing1 = 0x47405331 | (3 << 16); - cfg_ddr_mode = 0x40020002 | (2 << 4); - break; - - case 25: - cfg_ddr_timing1 = 0x47405331 | (4 << 16); - cfg_ddr_mode = 0x40020002 | (6 << 4); - break; - - case 30: - default: - cfg_ddr_timing1 = 0x47405331 | (5 << 16); - cfg_ddr_mode = 0x40020002 | (3 << 4); - break; - } - - ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; - ddr->cs0_config = ddr_cs_conf[0].reg; - ddr->timing_cfg_1 = cfg_ddr_timing1; - ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */ - ddr->sdram_mode = cfg_ddr_mode; - ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ - ddr->err_disable = 0x0000000D; - - asm ("sync;isync;msync"); - udelay(1000); - - ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ - asm ("sync; isync; msync"); - udelay(1000); - - for (i=0; ics0_config = ddr_cs_conf[i].reg; - - if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) { - /* - * OK, size detected -> all done - */ - return ddr_cs_conf[i].size; - } - } - - return 0; /* nothing found ! */ -} - -void board_add_ram_info(int use_default) -{ - int casl; - - if (use_default) - casl = CONFIG_DDR_DEFAULT_CL; - else - casl = cas_latency(); - - puts(" (CL="); - switch (casl) { - case 20: - puts("2)"); - break; - - case 25: - puts("2.5)"); - break; - - case 30: - puts("3)"); - break; - } -} - -long int initdram (int board_type) -{ - long dram_size = 0; - int casl; - -#if defined(CONFIG_DDR_DLL) - /* - * This DLL-Override only used on TQM8540 and TQM8560 - */ - { - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ccsr_gur_t *gur= &immap->im_gur; - int i,x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) { - gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; idevdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); - x++; - } - } -#endif - - casl = cas_latency(); - dram_size = sdram_setup(casl); - if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { - /* - * Try again with default CAS latency - */ - puts("Problem with CAS lantency"); - board_add_ram_info(1); - puts(", using default CL!\n"); - casl = CONFIG_DDR_DEFAULT_CL; - dram_size = sdram_setup(casl); - puts(" "); - } - - return dram_size; -} - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - printf ("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf ("SDRAM test passed.\n"); - return 0; -} -#endif diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c deleted file mode 100644 index 13ea6f4..0000000 --- a/board/tqm85xx/tqm85xx.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include -#include - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -void local_bus_init (void); -long int fixed_sdram (void); -ulong flash_get_size (ulong base, int banknum); - -#ifdef CONFIG_CPM2 -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; -#endif /* CONFIG_CPM2 */ - -#define CASL_STRING1 "casl=xx" -#define CASL_STRING2 "casl=" - -static const int casl_table[] = { 20, 25, 30 }; -#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) - -int cas_latency(void) -{ - char *s = getenv("serial#"); - int casl; - int val; - int i; - - casl = CONFIG_DDR_DEFAULT_CL; - - if (s != NULL) { - if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2, - strlen(CASL_STRING2)) == 0) { - val = simple_strtoul(s + strlen(s) - 2, NULL, 10); - - for (i=0; iim_lbc; - - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if boot FLASH isn't max size - */ - if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { - memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); - memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); - } - - /* - * Check if only one FLASH bank is available - */ - if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { - memctl->or1 = 0; - memctl->br1 = 0; - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - } - - return 0; -} - -/* - * Initialize Local Bus - */ -void local_bus_init (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info (&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ - lbc->ltedr = 0xa4c80000; /* DK: !!! */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr (); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - udelay (200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm ("sync;isync;msync"); - } -} - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - {} -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void pci_init_board (void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc85xx_init (struct pci_controller *hose); - - pci_mpc85xx_init (&hose); -#endif /* CONFIG_PCI */ -} diff --git a/board/tqm85xx/u-boot.lds b/board/tqm85xx/u-boot.lds deleted file mode 100644 index 4cc825b..0000000 --- a/board/tqm85xx/u-boot.lds +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2002,2003, Motorola,Inc. - * Xianghua Xiao, X.Xiao@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/mpc85xx/start.o (.bootpg) - board/tqm85xx/init.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc85xx/start.o (.text) - board/tqm85xx/init.o (.text) - cpu/mpc85xx/traps.o (.text) - cpu/mpc85xx/interrupts.o (.text) - cpu/mpc85xx/cpu_init.o (.text) - cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/tqm8xx/Makefile b/board/tqm8xx/Makefile deleted file mode 100644 index 2ff9b4d..0000000 --- a/board/tqm8xx/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o load_sernum_ethaddr.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/tqm8xx/config.mk b/board/tqm8xx/config.mk deleted file mode 100644 index 9d6080b..0000000 --- a/board/tqm8xx/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# TQM8xxL boards -# - -TEXT_BASE = 0x40000000 diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c deleted file mode 100644 index 97bb5c3..0000000 --- a/board/tqm8xx/flash.c +++ /dev/null @@ -1,829 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if 0 -#define DEBUG -#endif - -#include -#include -#include - -#include - -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) -# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ -# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -# endif -#endif /* CONFIG_TQM8xxL/M, !TQM866M */ - -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - -#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ - int scy, trlx, flash_or_timing, clk_diff; - - DECLARE_GLOBAL_DATA_PTR; - - scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; - if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { - trlx = OR_TRLX; - scy *= 2; - } else - trlx = 0; - - /* We assume that each 10MHz of bus clock require 1-clk SCY - * adjustment. - */ - clk_diff = (gd->bus_clk / 1000000) - 50; - - /* We need proper rounding here. This is what the "+5" and "-5" - * are here for. - */ - if (clk_diff >= 0) - scy += (clk_diff + 5) / 10; - else - scy += (clk_diff - 5) / 10; - - /* For bus frequencies above 50MHz, we want to use relaxed timing - * (OR_TRLX). - */ - if (gd->bus_clk >= 50000000) - trlx = OR_TRLX; - else - trlx = 0; - - if (trlx) - scy /= 2; - - if (scy > 0xf) - scy = 0xf; - if (scy < 1) - scy = 1; - - flash_or_timing = (scy << 4) | trlx | - (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); -#endif - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - debug ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* Remap FLASH according to real size */ -#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); -#else - memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK); -#endif - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - debug ("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - debug ("Protect monitor: %08lx ... %08lx\n", - (ulong)CFG_MONITOR_BASE, - (ulong)CFG_MONITOR_BASE + monitor_flash_len - 1); - - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ -# ifdef CFG_ENV_ADDR_REDUND - debug ("Protect primary environment: %08lx ... %08lx\n", - (ulong)CFG_ENV_ADDR, - (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1); -# else - debug ("Protect environment: %08lx ... %08lx\n", - (ulong)CFG_ENV_ADDR, - (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1); -# endif - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_ADDR_REDUND - debug ("Protect redundand environment: %08lx ... %08lx\n", - (ulong)CFG_ENV_ADDR_REDUND, - (ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - if (size_b1) { -#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); -#else - memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000); -#endif - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - debug ("## BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - - debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - } - - debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { -#ifdef CONFIG_TQM8xxM /* mirror bit flash */ - case FLASH_AMLV128U: printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); - break; - case FLASH_AMLV320U: printf ("AM29LV320ML (32Mbit, uniform sector size)\n"); - break; - case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n"); - break; - case FLASH_AMLV320B: printf ("AM29LV320MB (32Mbit, bottom boot sect)\n"); - break; -# else /* ! TQM8xxM */ - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; -#endif /* TQM8xxM */ - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL163B: printf ("AM29DL163B (16 Mbit, bottom boot sect)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case AMD_MANUFACT: - debug ("Manufacturer: AMD\n"); - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - debug ("Manufacturer: FUJITSU\n"); - info->flash_id = FLASH_MAN_FUJ; - break; - default: - debug ("Manufacturer: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { -#ifdef CONFIG_TQM8xxM /* mirror bit flash */ - case AMD_ID_MIRROR: - debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", - addr[14], addr[15]); - /* Special case for AMLV320MH/L */ - if ((addr[14] & 0x00ff00ff) == 0x001d001d && - (addr[15] & 0x00ff00ff) == 0x00000000) { - debug ("Chip: AMLV320MH/L\n"); - info->flash_id += FLASH_AMLV320U; - info->sector_count = 64; - info->size = 0x00800000; /* => 8 MB */ - break; - } - switch(addr[14]) { - case AMD_ID_LV128U_2: - if (addr[15] != AMD_ID_LV128U_3) { - debug ("Chip: AMLV128U -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - debug ("Chip: AMLV128U\n"); - info->flash_id += FLASH_AMLV128U; - info->sector_count = 256; - info->size = 0x02000000; - } - break; /* => 32 MB */ - case AMD_ID_LV640U_2: - if (addr[15] != AMD_ID_LV640U_3) { - debug ("Chip: AMLV640U -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - debug ("Chip: AMLV640U\n"); - info->flash_id += FLASH_AMLV640U; - info->sector_count = 128; - info->size = 0x01000000; - } - break; /* => 16 MB */ - case AMD_ID_LV320B_2: - if (addr[15] != AMD_ID_LV320B_3) { - debug ("Chip: AMLV320B -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - debug ("Chip: AMLV320B\n"); - info->flash_id += FLASH_AMLV320B; - info->sector_count = 71; - info->size = 0x00800000; - } - break; /* => 8 MB */ - default: - debug ("Chip: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - break; - } - break; -# else /* ! TQM8xxM */ - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif /* TQM8xxM */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_DL163B: - info->flash_id += FLASH_AMDL163B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - switch (value) { -#ifdef CONFIG_TQM8xxM /* mirror bit flash */ - case AMD_ID_MIRROR: - switch (info->flash_id & FLASH_TYPEMASK) { - /* only known types here - no default */ - case FLASH_AMLV128U: - case FLASH_AMLV640U: - case FLASH_AMLV320U: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x20000; - } - break; - case FLASH_AMLV320B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - } - break; -# else /* ! TQM8xxM */ - case AMD_ID_LV400B: - case AMD_ID_LV800B: - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - break; - case AMD_ID_LV400T: - case AMD_ID_LV800T: - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - break; - case AMD_ID_LV320B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - case AMD_ID_LV320T: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The last 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < (info->sector_count - 8)) - ? 2 * (64 << 10) - : 2 * ( 8 << 10); - } - break; -#endif /* TQM8xxM */ - case AMD_ID_LV160B: - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - break; - case AMD_ID_LV160T: - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - break; - case AMD_ID_DL163B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - default: - return (0); - break; - } - -#if 0 - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } -#endif - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/tqm8xx/load_sernum_ethaddr.c b/board/tqm8xx/load_sernum_ethaddr.c deleted file mode 100644 index 143f368..0000000 --- a/board/tqm8xx/load_sernum_ethaddr.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/*----------------------------------------------------------------------- - * Process Hardware Information Block: - * - * If we boot on a system fresh from factory, check if the Hardware - * Information Block exists and save the information it contains. - * - * The TQM8xxL / TQM82xx Hardware Information Block is defined as - * follows: - * - located in first flash bank - * - starts at offset 0x0003FFC0 - * - size 0x00000040 - * - * Internal structure: - * - sequence of ASCII character strings - * - fields separated by a single space character (0x20) - * - last field terminated by NUL character (0x00) - * - remaining space filled with NUL characters (0x00) - * - * Fields in Hardware Information Block: - * 1) Module Type - * 2) Serial Number - * 3) First MAC Address - * 4) Number of additional MAC addresses - */ - -void load_sernum_ethaddr (void) -{ - unsigned char *hwi; - unsigned char serial [CFG_HWINFO_SIZE]; - unsigned char ethaddr[CFG_HWINFO_SIZE]; - unsigned short ih, is, ie, part; - - hwi = (unsigned char *)(CFG_FLASH_BASE + CFG_HWINFO_OFFSET); - ih = is = ie = 0; - - if (*((unsigned long *)hwi) != (unsigned long)CFG_HWINFO_MAGIC) { - return; - } - - part = 1; - - /* copy serial # / MAC address */ - while ((hwi[ih] != '\0') && (ih < CFG_HWINFO_SIZE)) { - if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */ - return; - } - switch (part) { - default: /* Copy serial # */ - if (hwi[ih] == ' ') { - ++part; - } - serial[is++] = hwi[ih]; - break; - case 3: /* Copy MAC address */ - if (hwi[ih] == ' ') { - ++part; - break; - } - ethaddr[ie++] = hwi[ih]; - if ((ie % 3) == 2) - ethaddr[ie++] = ':'; - break; - } - ++ih; - } - serial[is] = '\0'; - if (ie && ethaddr[ie-1] == ':') - --ie; - ethaddr[ie] = '\0'; - - /* set serial# and ethaddr if not yet defined */ - if (getenv("serial#") == NULL) { - setenv ((char *)"serial#", (char *)serial); - } - - if (getenv("ethaddr") == NULL) { - setenv ((char *)"ethaddr", (char *)ethaddr); - } -} diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c deleted file mode 100644 index 017bdf9..0000000 --- a/board/tqm8xx/tqm8xx.c +++ /dev/null @@ -1,501 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if 0 -#define DEBUG -#endif - -#include -#include -#ifdef CONFIG_PS2MULT -#include -#endif - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, - 0x1FF5FC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test TQ ID string (TQM8xx...) - * If present, check for "L" type (no second DRAM bank), - * otherwise "L" type is assumed as default. - * - * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else. - */ - -int checkboard (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - char *s = getenv ("serial#"); - - puts ("Board: "); - - if (!s || strncmp (s, "TQM8", 4)) { - puts ("### No HW ID - assuming TQM8xxL\n"); - return (0); - } - - if ((*(s + 6) == 'L')) { /* a TQM8xxL type */ - gd->board_type = 'L'; - } - - if ((*(s + 6) == 'M')) { /* a TQM8xxM type */ - gd->board_type = 'M'; - } - - for (; *s; ++s) { - if (*s == ' ') - break; - putc (*s); - } - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9, size10; - long int size_b0 = 0; - long int size_b1 = 0; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; - - /* - * The following value is used as an address (i.e. opcode) for - * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If - * the port size is 32bit the SDRAM does NOT "see" the lower two - * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for - * MICRON SDRAMs: - * -> 0 00 010 0 010 - * | | | | +- Burst Length = 4 - * | | | +----- Burst Type = Sequential - * | | +------- CAS Latency = 2 - * | +----------- Operating Mode = Standard - * +-------------- Write Burst Mode = Programmed Burst Length - */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; - } -#endif /* CONFIG_CAN_DRIVER */ - - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay (1); - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */ - memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */ - udelay (1); - } -#endif /* CONFIG_CAN_DRIVER */ - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20); - - udelay(1000); - -#if defined(CFG_MAMR_10COL) - /* - * try 10 column mode - */ - size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20); -#else - size10 = 0; -#endif /* CFG_MAMR_10COL */ - - if ((size8 < size10) && (size9 < size10)) { - size_b0 = size10; - } else if ((size8 < size9) && (size10 < size9)) { - size_b0 = size9; - memctl->memc_mamr = CFG_MAMR_9COL; - udelay (500); - } else { - size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; - udelay (500); - } - debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20); - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */ - /* - * Check Bank 1 Memory Size - * use current column settings - * [9 column SDRAM may also be used in 8 column mode, - * but then only half the real size will be used.] - */ - size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); - debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20); - } else { - size_b1 = 0; - } -#endif /* CONFIG_CAN_DRIVER */ - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - - memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b0 > 0) { - /* - * Position Bank 0 immediately above Bank 1 - */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b1; - } else { - unsigned long reg; - - /* - * No bank 0 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - } else { /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or3 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b0; - } else { - unsigned long reg; - -#ifndef CONFIG_CAN_DRIVER - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; -#endif /* CONFIG_CAN_DRIVER */ - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - } - - udelay (10000); - -#ifdef CONFIG_CAN_DRIVER - /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CFG_OR3_CAN; - memctl->memc_br3 = CFG_BR3_CAN; - - /* Initialize MBMR */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; - memctl->memc_mcr = 0x0100 | UPMB; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMB; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMB; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMB; - - memctl->memc_mdr = 0xFFFFDC05; - memctl->memc_mcr = 0x0104 | UPMB; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x0118 | UPMB; - - memctl->memc_mdr = 0xCFFCD004; - memctl->memc_mcr = 0x0119 | UPMB; - - memctl->memc_mdr = 0x0FFCC000; - memctl->memc_mcr = 0x011A | UPMB; - - memctl->memc_mdr = 0x7FFCC004; - memctl->memc_mcr = 0x011B | UPMB; - - memctl->memc_mdr = 0xFFFDCC05; - memctl->memc_mcr = 0x011C | UPMB; -#endif /* CONFIG_CAN_DRIVER */ - -#ifdef CONFIG_ISP1362_USB - /* Initialize OR5 / BR5 */ - memctl->memc_or5 = CFG_OR5_ISP1362; - memctl->memc_br5 = CFG_BR5_ISP1362; -#endif /* CONFIG_ISP1362_USB */ - - - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_PS2MULT - -#ifdef CONFIG_HMI10 -#define BASE_BAUD ( 1843200 / 16 ) -struct serial_state rs_table[] = { - { BASE_BAUD, 4, (void*)0xec140000 }, - { BASE_BAUD, 2, (void*)0xec150000 }, - { BASE_BAUD, 6, (void*)0xec160000 }, - { BASE_BAUD, 10, (void*)0xec170000 }, -}; - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ - ps2mult_early_init(); - return (0); -} -#endif -#endif /* CONFIG_HMI10 */ - -#endif /* CONFIG_PS2MULT */ - -/* ---------------------------------------------------------------------------- */ -/* HMI10 specific stuff */ -/* ---------------------------------------------------------------------------- */ -#ifdef CONFIG_HMI10 - -int misc_init_r (void) -{ -# ifdef CONFIG_IDE_LED - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - /* Configure PA15 as output port */ - immap->im_ioport.iop_padir |= 0x0001; - immap->im_ioport.iop_paodr |= 0x0001; - immap->im_ioport.iop_papar &= ~0x0001; - immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ -# endif - return (0); -} - -# ifdef CONFIG_IDE_LED -void ide_led (uchar led, uchar status) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - /* We have one led for both pcmcia slots */ - if (status) { /* led on */ - immap->im_ioport.iop_padat |= 0x0001; - } else { - immap->im_ioport.iop_padat &= ~0x0001; - } -} -# endif -#endif /* CONFIG_HMI10 */ - -/* ---------------------------------------------------------------------------- */ -/* NSCU specific stuff */ -/* ---------------------------------------------------------------------------- */ -#ifdef CONFIG_NSCU - -int misc_init_r (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - /* wake up ethernet module */ - immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ - immr->im_ioport.iop_pcdir |= 0x0004; /* output */ - immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ - immr->im_ioport.iop_pcdat |= 0x0004; /* enable */ - - return (0); -} -#endif /* CONFIG_NSCU */ - -/* ------------------------------------------------------------------------- */ diff --git a/board/tqm8xx/u-boot.lds b/board/tqm8xx/u-boot.lds deleted file mode 100644 index d526d1d..0000000 --- a/board/tqm8xx/u-boot.lds +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/tqm8xx/u-boot.lds.debug b/board/tqm8xx/u-boot.lds.debug deleted file mode 100644 index ddd4678..0000000 --- a/board/tqm8xx/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/trab/Makefile b/board/trab/Makefile deleted file mode 100644 index ced9bc5..0000000 --- a/board/trab/Makefile +++ /dev/null @@ -1,65 +0,0 @@ -# -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o -SOBJS := lowlevel_init.o - -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) - -LOAD_ADDR = 0xc100000 - -######################################################################### - -all: $(LIB) trab_fkt.srec trab_fkt.bin - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -trab_fkt.srec: trab_fkt.o rs485.o tsc2000.o $(LIB) - $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ $(LIB) \ - -L../../examples -lstubs \ - -L../../lib_generic -lgeneric \ - -L$(gcclibdir) -lgcc - $(OBJCOPY) -O srec $(<:.o=) $@ - -trab_fkt.bin: trab_fkt.srec - $(OBJCOPY) -O binary $< $@ 2>/dev/null - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/trab/Pt1000_temp_data.h b/board/trab/Pt1000_temp_data.h deleted file mode 100644 index 17e9ed7..0000000 --- a/board/trab/Pt1000_temp_data.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Data file for tsc2000 driver. - * Copyright (C) 2002, 2003 DENX Software Engineering, Wolfgang Denk, wd@denx.de - */ - -#ifndef _PT1000_TEMP_DATA_H -#define _PT1000_TEMP_DATA_H - -long Pt1000_temp_table[][2] = { - /* For quick range checking the largest element - * is placed at index 0. - * U, nV T, C*100 - */ - { 44000000 , 12165 }, - { -10000000 , -2644 }, - { -9000000 , -2381 }, - { -8000000 , -2118 }, - { -7000000 , -1855 }, - { -6000000 , -1591 }, - { -5000000 , -1327 }, - { -4000000 , -1063 }, - { -3000000 , -798 }, - { -2000000 , -532 }, - { -1000000 , -266 }, - { 0 , 000 }, - { 1000000 , 267 }, - { 2000000 , 534 }, - { 3000000 , 802 }, - { 4000000 , 1070 }, - { 5000000 , 1338 }, - { 6000000 , 1607 }, - { 7000000 , 1876 }, - { 8000000 , 2146 }, - { 9000000 , 2416 }, - { 10000000 , 2687 }, - { 11000000 , 2958 }, - { 12000000 , 3230 }, - { 13000000 , 3502 }, - { 14000000 , 3774 }, - { 15000000 , 4047 }, - { 16000000 , 4321 }, - { 17000000 , 4595 }, - { 18000000 , 4869 }, - { 19000000 , 5144 }, - { 20000000 , 5419 }, - { 21000000 , 5694 }, - { 22000000 , 5971 }, - { 23000000 , 6247 }, - { 24000000 , 6524 }, - { 25000000 , 6802 }, - { 26000000 , 7080 }, - { 27000000 , 7358 }, - { 28000000 , 7637 }, - { 29000000 , 7916 }, - { 30000000 , 8196 }, - { 31000000 , 8476 }, - { 32000000 , 8757 }, - { 33000000 , 9039 }, - { 34000000 , 9320 }, - { 35000000 , 9602 }, - { 36000000 , 9885 }, - { 37000000 , 10168 }, - { 38000000 , 10452 }, - { 39000000 , 10736 }, - { 40000000 , 11021 }, - { 41000000 , 11306 }, - { 42000000 , 11592 }, - { 43000000 , 11879 }, - { 44000000 , 12165 }, -}; -#endif /* _PT1000_TEMP_DATA_H */ diff --git a/board/trab/README.kbd b/board/trab/README.kbd deleted file mode 100644 index 3db00bc..0000000 --- a/board/trab/README.kbd +++ /dev/null @@ -1,44 +0,0 @@ - -The TRAB keyboard implementation is similar to that for LWMON and -R360MPI boards. The only difference concerns key naming. There are 4 -keys on TRAB: 1, 2, 3, 4. - -1) The "kbd" command provides information about the current state of - the keys. For example, - - TRAB # kbd - Keys: 1 0 1 0 - - means that keys 1 and 3 are pressed. The keyboard status is also - stored in the "keybd" environment variable. In this example we get - - keybd=1010 - -2) The "preboot" variable is set according to current environment - settings and keys pressed. This is an example: - - TRAB # setenv magic_keys XY - TRAB # setenv key_magicX 12 - TRAB # setenv key_cmdX echo ## Keys 1 + 2 pressed ##\;echo - TRAB # setenv key_magicY 13 - TRAB # setenv key_cmdY echo ## Keys 1 + 3 pressed ##\;echo - - Here "magic_keys=XY" means that the "key_magicX" and "key_magicY" - variables will be checked for a match. Each variable "key_magic*" - defines a set of keys. In the our example, if keys 1 and 3 are - pressed during reset, then "key_magicY" matches, so the "preboot" - variable will be set to the contents of "key_cmdY": - - preboot=echo ## Keys 1 + 3 pressed ##;echo - -3) The TRAB board has optional modem support. When a certain key - combination is pressed on the keyboard at power-on, the firmware - performs the necessary initialization of the modem and allows for - dial-in. The key combination is specified in the - "include/configs/trab.h" file. For example: - - #define CONFIG_MODEM_KEY_MAGIC "23" - - means that modem will be initialized if and only if both keys 2, 3 - are pressed. Note that the format of this string is similar to the - format of "key_magic*" environment variables described above. diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c deleted file mode 100644 index 056e562..0000000 --- a/board/trab/auto_update.c +++ /dev/null @@ -1,656 +0,0 @@ -/* - * (C) Copyright 2003 - * Gary Jennejohn, DENX Software Engineering, gj@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#ifdef CFG_HUSH_PARSER -#include -#endif - -#ifdef CONFIG_AUTO_UPDATE - -#ifndef CONFIG_USB_OHCI -#error "must define CONFIG_USB_OHCI" -#endif - -#ifndef CONFIG_USB_STORAGE -#error "must define CONFIG_USB_STORAGE" -#endif - -#ifndef CFG_HUSH_PARSER -#error "must define CFG_HUSH_PARSER" -#endif - -#if !(CONFIG_COMMANDS & CFG_CMD_FAT) -#error "must define CFG_CMD_FAT" -#endif - -/* - * Check whether a USB memory stick is plugged in. - * If one is found: - * 1) if prepare.img ist found load it into memory. If it is - * valid then run it. - * 2) if preinst.img is found load it into memory. If it is - * valid then run it. Update the EEPROM. - * 3) if firmware.img is found load it into memory. If it is valid, - * burn it into FLASH and update the EEPROM. - * 4) if kernel.img is found load it into memory. If it is valid, - * burn it into FLASH and update the EEPROM. - * 5) if app.img is found load it into memory. If it is valid, - * burn it into FLASH and update the EEPROM. - * 6) if disk.img is found load it into memory. If it is valid, - * burn it into FLASH and update the EEPROM. - * 7) if postinst.img is found load it into memory. If it is - * valid then run it. Update the EEPROM. - */ - -#undef AU_DEBUG - -#undef debug -#ifdef AU_DEBUG -#define debug(fmt,args...) printf (fmt ,##args) -#else -#define debug(fmt,args...) -#endif /* AU_DEBUG */ - -/* possible names of files on the USB stick. */ -#define AU_PREPARE "prepare.img" -#define AU_PREINST "preinst.img" -#define AU_FIRMWARE "firmware.img" -#define AU_KERNEL "kernel.img" -#define AU_APP "app.img" -#define AU_DISK "disk.img" -#define AU_POSTINST "postinst.img" - -struct flash_layout -{ - long start; - long end; -}; - -/* layout of the FLASH. ST = start address, ND = end address. */ -#ifndef CONFIG_FLASH_8MB /* 16 MB Flash, 32 MB RAM */ -#define AU_FL_FIRMWARE_ST 0x00000000 -#define AU_FL_FIRMWARE_ND 0x0009FFFF -#define AU_FL_VFD_ST 0x000A0000 -#define AU_FL_VFD_ND 0x000BFFFF -#define AU_FL_KERNEL_ST 0x000C0000 -#define AU_FL_KERNEL_ND 0x001BFFFF -#define AU_FL_APP_ST 0x001C0000 -#define AU_FL_APP_ND 0x005BFFFF -#define AU_FL_DISK_ST 0x005C0000 -#define AU_FL_DISK_ND 0x00FFFFFF -#else /* 8 MB Flash, 32 MB RAM */ -#define AU_FL_FIRMWARE_ST 0x00000000 -#define AU_FL_FIRMWARE_ND 0x0005FFFF -#define AU_FL_KERNEL_ST 0x00060000 -#define AU_FL_KERNEL_ND 0x0013FFFF -#define AU_FL_APP_ST 0x00140000 -#define AU_FL_APP_ND 0x0067FFFF -#define AU_FL_DISK_ST 0x00680000 -#define AU_FL_DISK_ND 0x007DFFFF -#define AU_FL_VFD_ST 0x007E0000 -#define AU_FL_VFD_ND 0x007FFFFF -#endif /* CONFIG_FLASH_8MB */ - -/* a structure with the offsets to values in the EEPROM */ -struct eeprom_layout -{ - int time; - int size; - int dcrc; -}; - -/* layout of the EEPROM - offset from the start. All entries are 32 bit. */ -#define AU_EEPROM_TIME_PREINST 64 -#define AU_EEPROM_SIZE_PREINST 68 -#define AU_EEPROM_DCRC_PREINST 72 -#define AU_EEPROM_TIME_FIRMWARE 76 -#define AU_EEPROM_SIZE_FIRMWARE 80 -#define AU_EEPROM_DCRC_FIRMWARE 84 -#define AU_EEPROM_TIME_KERNEL 88 -#define AU_EEPROM_SIZE_KERNEL 92 -#define AU_EEPROM_DCRC_KERNEL 96 -#define AU_EEPROM_TIME_APP 100 -#define AU_EEPROM_SIZE_APP 104 -#define AU_EEPROM_DCRC_APP 108 -#define AU_EEPROM_TIME_DISK 112 -#define AU_EEPROM_SIZE_DISK 116 -#define AU_EEPROM_DCRC_DISK 120 -#define AU_EEPROM_TIME_POSTINST 124 -#define AU_EEPROM_SIZE_POSTINST 128 -#define AU_EEPROM_DCRC_POSTINST 132 - -static int au_usb_stor_curr_dev; /* current device */ - -/* index of each file in the following arrays */ -#define IDX_PREPARE 0 -#define IDX_PREINST 1 -#define IDX_FIRMWARE 2 -#define IDX_KERNEL 3 -#define IDX_APP 4 -#define IDX_DISK 5 -#define IDX_POSTINST 6 -/* max. number of files which could interest us */ -#define AU_MAXFILES 7 -/* pointers to file names */ -char *aufile[AU_MAXFILES]; -/* sizes of flash areas for each file */ -long ausize[AU_MAXFILES]; -/* offsets into the EEEPROM */ -struct eeprom_layout auee_off[AU_MAXFILES] = { \ - {0}, \ - {AU_EEPROM_TIME_PREINST, AU_EEPROM_SIZE_PREINST, AU_EEPROM_DCRC_PREINST,}, \ - {AU_EEPROM_TIME_FIRMWARE, AU_EEPROM_SIZE_FIRMWARE, AU_EEPROM_DCRC_FIRMWARE,}, \ - {AU_EEPROM_TIME_KERNEL, AU_EEPROM_SIZE_KERNEL, AU_EEPROM_DCRC_KERNEL,}, \ - {AU_EEPROM_TIME_APP, AU_EEPROM_SIZE_APP, AU_EEPROM_DCRC_APP,}, \ - {AU_EEPROM_TIME_DISK, AU_EEPROM_SIZE_DISK, AU_EEPROM_DCRC_DISK,}, \ - {AU_EEPROM_TIME_POSTINST, AU_EEPROM_SIZE_POSTINST, AU_EEPROM_DCRC_POSTINST,} \ - }; -/* array of flash areas start and end addresses */ -struct flash_layout aufl_layout[AU_MAXFILES - 3] = { \ - {AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND,}, \ - {AU_FL_KERNEL_ST, AU_FL_KERNEL_ND,}, \ - {AU_FL_APP_ST, AU_FL_APP_ND,}, \ - {AU_FL_DISK_ST, AU_FL_DISK_ND,}, \ -}; -/* convert the index into aufile[] to an index into aufl_layout[] */ -#define FIDX_TO_LIDX(idx) ((idx) - 2) - -/* where to load files into memory */ -#define LOAD_ADDR ((unsigned char *)0x0C100000) -/* the app is the largest image */ -#define MAX_LOADSZ ausize[IDX_APP] - -/* externals */ -extern int fat_register_device(block_dev_desc_t *, int); -extern int file_fat_detectfs(void); -extern long file_fat_read(const char *, void *, unsigned long); -extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int); -extern int i2c_write (uchar, uint, int , uchar* , int); -#ifdef CONFIG_VFD -extern int trab_vfd (ulong); -extern int transfer_pic(unsigned char, unsigned char *, int, int); -#endif -extern int flash_sect_erase(ulong, ulong); -extern int flash_sect_protect (int, ulong, ulong); -extern int flash_write (char *, ulong, ulong); -/* change char* to void* to shutup the compiler */ -extern int i2c_write_multiple (uchar, uint, int, void *, int); -extern int i2c_read_multiple (uchar, uint, int, void *, int); -extern block_dev_desc_t *get_dev (char*, int); -extern int u_boot_hush_start(void); - -int -au_check_cksum_valid(int idx, long nbytes) -{ - image_header_t *hdr; - unsigned long checksum; - - hdr = (image_header_t *)LOAD_ADDR; - - if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) - { - printf ("Image %s bad total SIZE\n", aufile[idx]); - return -1; - } - /* check the data CRC */ - checksum = ntohl(hdr->ih_dcrc); - - if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) - != checksum) - { - printf ("Image %s bad data checksum\n", aufile[idx]); - return -1; - } - return 0; -} - -int -au_check_header_valid(int idx, long nbytes) -{ - image_header_t *hdr; - unsigned long checksum; - unsigned char buf[4]; - - hdr = (image_header_t *)LOAD_ADDR; - /* check the easy ones first */ -#undef CHECK_VALID_DEBUG -#ifdef CHECK_VALID_DEBUG - printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC); - printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_ARM); - printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes); - printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL); -#endif - if (nbytes < sizeof(*hdr)) - { - printf ("Image %s bad header SIZE\n", aufile[idx]); - return -1; - } - if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_ARM) - { - printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]); - return -1; - } - /* check the hdr CRC */ - checksum = ntohl(hdr->ih_hcrc); - hdr->ih_hcrc = 0; - - if (crc32 (0, (char *)hdr, sizeof(*hdr)) != checksum) { - printf ("Image %s bad header checksum\n", aufile[idx]); - return -1; - } - hdr->ih_hcrc = htonl(checksum); - /* check the type - could do this all in one gigantic if() */ - if ((idx == IDX_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) { - printf ("Image %s wrong type\n", aufile[idx]); - return -1; - } - if ((idx == IDX_KERNEL) && (hdr->ih_type != IH_TYPE_KERNEL)) { - printf ("Image %s wrong type\n", aufile[idx]); - return -1; - } - if ((idx == IDX_DISK) && (hdr->ih_type != IH_TYPE_FILESYSTEM)) { - printf ("Image %s wrong type\n", aufile[idx]); - return -1; - } - if ((idx == IDX_APP) && (hdr->ih_type != IH_TYPE_RAMDISK) - && (hdr->ih_type != IH_TYPE_FILESYSTEM)) { - printf ("Image %s wrong type\n", aufile[idx]); - return -1; - } - if ((idx == IDX_PREPARE || idx == IDX_PREINST || idx == IDX_POSTINST) - && (hdr->ih_type != IH_TYPE_SCRIPT)) - { - printf ("Image %s wrong type\n", aufile[idx]); - return -1; - } - /* special case for prepare.img */ - if (idx == IDX_PREPARE) - return 0; - /* recycle checksum */ - checksum = ntohl(hdr->ih_size); - /* for kernel and app the image header must also fit into flash */ - if ((idx != IDX_DISK) && (idx != IDX_FIRMWARE)) - checksum += sizeof(*hdr); - /* check the size does not exceed space in flash. HUSH scripts */ - /* all have ausize[] set to 0 */ - if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { - printf ("Image %s is bigger than FLASH\n", aufile[idx]); - return -1; - } - /* check the time stamp from the EEPROM */ - /* read it in */ - i2c_read_multiple(0x54, auee_off[idx].time, 1, buf, sizeof(buf)); -#ifdef CHECK_VALID_DEBUG - printf ("buf[0] %#x buf[1] %#x buf[2] %#x buf[3] %#x " - "as int %#x time %#x\n", - buf[0], buf[1], buf[2], buf[3], - *((unsigned int *)buf), ntohl(hdr->ih_time)); -#endif - /* check it */ - if (*((unsigned int *)buf) >= ntohl(hdr->ih_time)) { - printf ("Image %s is too old\n", aufile[idx]); - return -1; - } - - return 0; -} - -/* power control defines */ -#define CPLD_VFD_BK ((volatile char *)0x04038002) -#define POWER_OFF (1 << 1) - -int -au_do_update(int idx, long sz) -{ - image_header_t *hdr; - char *addr; - long start, end; - int off, rc; - uint nbytes; - - hdr = (image_header_t *)LOAD_ADDR; - - /* disable the power switch */ - *CPLD_VFD_BK |= POWER_OFF; - - /* execute a script */ - if (hdr->ih_type == IH_TYPE_SCRIPT) { - addr = (char *)((char *)hdr + sizeof(*hdr)); - /* stick a NULL at the end of the script, otherwise */ - /* parse_string_outer() runs off the end. */ - addr[ntohl(hdr->ih_size)] = 0; - addr += 8; - parse_string_outer(addr, FLAG_PARSE_SEMICOLON); - return 0; - } - - start = aufl_layout[FIDX_TO_LIDX(idx)].start; - end = aufl_layout[FIDX_TO_LIDX(idx)].end; - - /* unprotect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) { -#undef AU_UPDATE_TEST -#ifdef AU_UPDATE_TEST - /* erase it where Linux goes */ - start = aufl_layout[1].start; - end = aufl_layout[1].end; -#endif - flash_sect_protect(0, start, end); - } - - /* - * erase the address range. - */ - debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase(start, end); - wait_ms(100); - /* strip the header - except for the kernel and ramdisk */ - if (hdr->ih_type == IH_TYPE_KERNEL || hdr->ih_type == IH_TYPE_RAMDISK) { - addr = (char *)hdr; - off = sizeof(*hdr); - nbytes = sizeof(*hdr) + ntohl(hdr->ih_size); - } else { - addr = (char *)((char *)hdr + sizeof(*hdr)); -#ifdef AU_UPDATE_TEST - /* copy it to where Linux goes */ - if (idx == IDX_FIRMWARE) - start = aufl_layout[1].start; -#endif - off = 0; - nbytes = ntohl(hdr->ih_size); - } - - /* copy the data from RAM to FLASH */ - debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write(addr, start, nbytes); - if (rc != 0) { - printf("Flashing failed due to error %d\n", rc); - return -1; - } - - /* check the dcrc of the copy */ - if (crc32 (0, (char *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) { - printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]); - return -1; - } - - /* protect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) - flash_sect_protect(1, start, end); - return 0; -} - -int -au_update_eeprom(int idx) -{ - image_header_t *hdr; - int off; - uint32_t val; - - /* special case for prepare.img */ - if (idx == IDX_PREPARE) { - /* enable the power switch */ - *CPLD_VFD_BK &= ~POWER_OFF; - return 0; - } - - hdr = (image_header_t *)LOAD_ADDR; - /* write the time field into EEPROM */ - off = auee_off[idx].time; - val = ntohl(hdr->ih_time); - i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); - /* write the size field into EEPROM */ - off = auee_off[idx].size; - val = ntohl(hdr->ih_size); - i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); - /* write the dcrc field into EEPROM */ - off = auee_off[idx].dcrc; - val = ntohl(hdr->ih_dcrc); - i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); - /* enable the power switch */ - *CPLD_VFD_BK &= ~POWER_OFF; - return 0; -} - -/* - * this is called from board_init() after the hardware has been set up - * and is usable. That seems like a good time to do this. - * Right now the return value is ignored. - */ -int -do_auto_update(void) -{ - block_dev_desc_t *stor_dev; - long sz; - int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc; - char *env; - long start, end; - -#undef ERASE_EEPROM -#ifdef ERASE_EEPROM - int arr[18]; - memset(arr, 0, sizeof(arr)); - i2c_write_multiple(0x54, 64, 1, arr, sizeof(arr)); -#endif - au_usb_stor_curr_dev = -1; - /* start USB */ - if (usb_stop() < 0) { - debug ("usb_stop failed\n"); - return -1; - } - if (usb_init() < 0) { - debug ("usb_init failed\n"); - return -1; - } - /* - * check whether a storage device is attached (assume that it's - * a USB memory stick, since nothing else should be attached). - */ - au_usb_stor_curr_dev = usb_stor_scan(0); - if (au_usb_stor_curr_dev == -1) { - debug ("No device found. Not initialized?\n"); - return -1; - } - /* check whether it has a partition table */ - stor_dev = get_dev("usb", 0); - if (stor_dev == NULL) { - debug ("uknown device type\n"); - return -1; - } - if (fat_register_device(stor_dev, 1) != 0) { - debug ("Unable to use USB %d:%d for fatls\n", - au_usb_stor_curr_dev, 1); - return -1; - } - if (file_fat_detectfs() != 0) { - debug ("file_fat_detectfs failed\n"); - } - - /* initialize the array of file names */ - memset(aufile, 0, sizeof(aufile)); - aufile[IDX_PREPARE] = AU_PREPARE; - aufile[IDX_PREINST] = AU_PREINST; - aufile[IDX_FIRMWARE] = AU_FIRMWARE; - aufile[IDX_KERNEL] = AU_KERNEL; - aufile[IDX_APP] = AU_APP; - aufile[IDX_DISK] = AU_DISK; - aufile[IDX_POSTINST] = AU_POSTINST; - /* initialize the array of flash sizes */ - memset(ausize, 0, sizeof(ausize)); - ausize[IDX_FIRMWARE] = (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST; - ausize[IDX_KERNEL] = (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST; - ausize[IDX_APP] = (AU_FL_APP_ND + 1) - AU_FL_APP_ST; - ausize[IDX_DISK] = (AU_FL_DISK_ND + 1) - AU_FL_DISK_ST; - /* - * now check whether start and end are defined using environment - * variables. - */ - start = -1; - end = 0; - env = getenv("firmware_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("firmware_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_FIRMWARE] = (end + 1) - start; - aufl_layout[0].start = start; - aufl_layout[0].end = end; - } - start = -1; - end = 0; - env = getenv("kernel_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("kernel_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_KERNEL] = (end + 1) - start; - aufl_layout[1].start = start; - aufl_layout[1].end = end; - } - start = -1; - end = 0; - env = getenv("app_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("app_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_APP] = (end + 1) - start; - aufl_layout[2].start = start; - aufl_layout[2].end = end; - } - start = -1; - end = 0; - env = getenv("disk_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("disk_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_DISK] = (end + 1) - start; - aufl_layout[3].start = start; - aufl_layout[3].end = end; - } - /* make certain that HUSH is runnable */ - u_boot_hush_start(); - /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc(0); - - bitmap_first = 0; - /* just loop thru all the possible files */ - for (i = 0; i < AU_MAXFILES; i++) { - /* just read the header */ - sz = file_fat_read(aufile[i], LOAD_ADDR, sizeof(image_header_t)); - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, sizeof(image_header_t)); - if (sz <= 0 || sz < sizeof(image_header_t)) { - debug ("%s not found\n", aufile[i]); - continue; - } - if (au_check_header_valid(i, sz) < 0) { - debug ("%s header not valid\n", aufile[i]); - continue; - } - sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ); - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, sizeof(image_header_t)); - if (sz <= 0 || sz <= sizeof(image_header_t)) { - debug ("%s not found\n", aufile[i]); - continue; - } - if (au_check_cksum_valid(i, sz) < 0) { - debug ("%s checksum not valid\n", aufile[i]); - continue; - } -#ifdef CONFIG_VFD - /* now that we have a valid file we can display the */ - /* bitmap. */ - if (bitmap_first == 0) { - env = getenv("bitmap2"); - if (env == NULL) { - trab_vfd(0); - } else { - /* not so simple - bitmap2 is supposed to */ - /* contain the address of the bitmap */ - env = (char *)simple_strtoul(env, NULL, 16); -/* NOTE: these are taken from vfd_logo.h. If that file changes then */ -/* these defines MUST also be updated! These may be wrong for bitmap2. */ -#define VFD_LOGO_WIDTH 112 -#define VFD_LOGO_HEIGHT 72 - /* must call transfer_pic directly */ - transfer_pic(3, env, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH); - } - bitmap_first = 1; - } -#endif - /* this is really not a good idea, but it's what the */ - /* customer wants. */ - cnt = 0; - got_ctrlc = 0; - do { - res = au_do_update(i, sz); - /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc()) { - clear_ctrlc(); - if (res < 0) - got_ctrlc = 1; - break; - } - cnt++; -#ifdef AU_TEST_ONLY - } while (res < 0 && cnt < 3); - if (cnt < 3) -#else - } while (res < 0); -#endif - /* - * it doesn't make sense to update the EEPROM if the - * update was interrupted by the user due to errors. - */ - if (got_ctrlc == 0) - au_update_eeprom(i); - else - /* enable the power switch */ - *CPLD_VFD_BK &= ~POWER_OFF; - } - usb_stop(); - /* restore the old state */ - disable_ctrlc(old_ctrlc); - return 0; -} -#endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c deleted file mode 100644 index 00eb385..0000000 --- a/board/trab/cmd_trab.c +++ /dev/null @@ -1,895 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#undef DEBUG - -#include -#include -#include -#include - -/* - * TRAB board specific commands. Especially commands for burn-in and function - * test. - */ -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -/* limits for valid range of VCC5V in mV */ -#define VCC5V_MIN 4500 -#define VCC5V_MAX 5500 - -/* - * Test strings for EEPROM test. Length of string 2 must not exceed length of - * string 1. Otherwise a buffer overrun could occur! - */ -#define EEPROM_TEST_STRING_1 "0987654321 :tset a si siht" -#define EEPROM_TEST_STRING_2 "this is a test: 1234567890" - -/* - * min/max limits for valid contact temperature during burn in test (in - * degree Centigrade * 100) - */ -#define MIN_CONTACT_TEMP -1000 -#define MAX_CONTACT_TEMP +9000 - -/* blinking frequency of status LED */ -#define LED_BLINK_FREQ 5 - -/* delay time between burn in cycles in seconds */ -#ifndef BURN_IN_CYCLE_DELAY /* if not defined in include/configs/trab.h */ -#define BURN_IN_CYCLE_DELAY 5 -#endif - -/* physical SRAM parameters */ -#define SRAM_ADDR 0x02000000 /* GCS1 */ -#define SRAM_SIZE 0x40000 /* 256 kByte */ - -/* CPLD-Register for controlling TRAB hardware functions */ -#define CPLD_BUTTONS ((volatile unsigned long *)0x04020000) -#define CPLD_FILL_LEVEL ((volatile unsigned long *)0x04008000) -#define CPLD_ROTARY_SWITCH ((volatile unsigned long *)0x04018000) -#define CPLD_RS485_RE ((volatile unsigned long *)0x04028000) - -/* I2C EEPROM device address */ -#define I2C_EEPROM_DEV_ADDR 0x54 - -/* EEPROM address map */ -#define EE_ADDR_TEST 192 -#define EE_ADDR_MAX_CYCLES 256 -#define EE_ADDR_STATUS 258 -#define EE_ADDR_PASS_CYCLES 259 -#define EE_ADDR_FIRST_ERROR_CYCLE 261 -#define EE_ADDR_FIRST_ERROR_NUM 263 -#define EE_ADDR_FIRST_ERROR_NAME 264 -#define EE_ADDR_ACT_CYCLE 280 - -/* Bit definitions for ADCCON */ -#define ADC_ENABLE_START 0x1 -#define ADC_READ_START 0x2 -#define ADC_STDBM 0x4 -#define ADC_INP_AIN0 (0x0 << 3) -#define ADC_INP_AIN1 (0x1 << 3) -#define ADC_INP_AIN2 (0x2 << 3) -#define ADC_INP_AIN3 (0x3 << 3) -#define ADC_INP_AIN4 (0x4 << 3) -#define ADC_INP_AIN5 (0x5 << 3) -#define ADC_INP_AIN6 (0x6 << 3) -#define ADC_INP_AIN7 (0x7 << 3) -#define ADC_PRSCEN 0x4000 -#define ADC_ECFLG 0x800 - -/* misc */ - -/* externals */ -extern int memory_post_tests (unsigned long start, unsigned long size); -extern int i2c_write (uchar, uint, int , uchar* , int); -extern int i2c_read (uchar, uint, int , uchar* , int); -extern void tsc2000_reg_init (void); -extern s32 tsc2000_contact_temp (void); -extern void spi_init(void); - -/* function declarations */ -int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int i2c_write_multiple (uchar chip, uint addr, int alen, - uchar *buffer, int len); -int i2c_read_multiple (uchar chip, uint addr, int alen, - uchar *buffer, int len); -int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -/* helper functions */ -static void adc_init (void); -static int adc_read (unsigned int channel); -static int read_dip (void); -static int read_vcc5v (void); -static int test_dip (void); -static int test_vcc5v (void); -static int test_rotary_switch (void); -static int test_sram (void); -static int test_eeprom (void); -static int test_contact_temp (void); -static void led_set (unsigned int); -static void led_blink (void); -static void led_init (void); -static void sdelay (unsigned long seconds); /* delay in seconds */ -static int dummy (void); -static int read_max_cycles(void); -static void test_function_table_init (void); -static void global_vars_init (void); -static int global_vars_write_to_eeprom (void); - -/* globals */ -u16 max_cycles; -u8 status; -u16 pass_cycles; -u16 first_error_cycle; -u8 first_error_num; -unsigned char first_error_name[16]; -u16 act_cycle; - -typedef struct test_function_s { - unsigned char *name; - int (*pf)(void); -} test_function_t; - -/* max number of Burn In Functions */ -#define BIF_MAX 6 - -/* table with burn in functions */ -test_function_t test_function[BIF_MAX]; - - -int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int i; - int cycle_status; - - if (argc > 1) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - led_init (); - global_vars_init (); - test_function_table_init (); - spi_init (); - - if (global_vars_write_to_eeprom () != 0) { - printf ("%s: error writing global_vars to eeprom\n", - __FUNCTION__); - return (1); - } - - if (read_max_cycles () != 0) { - printf ("%s: error reading max_cycles from eeprom\n", - __FUNCTION__); - return (1); - } - - if (max_cycles == 0) { - printf ("%s: error, burn in max_cycles = 0\n", __FUNCTION__); - return (1); - } - - status = 0; - for (act_cycle = 1; act_cycle <= max_cycles; act_cycle++) { - - cycle_status = 0; - - /* - * avoid timestamp overflow problem after about 68 minutes of - * udelay() time. - */ - reset_timer_masked (); - for (i = 0; i < BIF_MAX; i++) { - - /* call test function */ - if ((*test_function[i].pf)() != 0) { - printf ("error in %s test\n", - test_function[i].name); - - /* is it the first error? */ - if (status == 0) { - status = 1; - first_error_cycle = act_cycle; - - /* do not use error_num 0 */ - first_error_num = i+1; - strncpy (first_error_name, - test_function[i].name, - sizeof (first_error_name)); - led_set (0); - } - cycle_status = 1; - } - } - /* were all tests of actual cycle OK? */ - if (cycle_status == 0) - pass_cycles++; - - /* set status LED if no error is occoured since yet */ - if (status == 0) - led_set (1); - - printf ("%s: cycle %d finished\n", __FUNCTION__, act_cycle); - - /* pause between cycles */ - sdelay (BURN_IN_CYCLE_DELAY); - } - - if (global_vars_write_to_eeprom () != 0) { - led_set (0); - printf ("%s: error writing global_vars to eeprom\n", - __FUNCTION__); - status = 1; - } - - if (status == 0) { - led_blink (); /* endless loop!! */ - return (0); - } else { - led_set (0); - return (1); - } -} - -U_BOOT_CMD( - burn_in, 1, 1, do_burn_in, - "burn_in - start burn-in test application on TRAB\n", - "\n" - " - start burn-in test application\n" - " The burn-in test could took a while to finish!\n" - " The content of the onboard EEPROM is modified!\n" -); - - -int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int i, dip; - - if (argc > 1) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - if ((dip = read_dip ()) == -1) { - return 1; - } - - for (i = 0; i < 4; i++) { - if ((dip & (1 << i)) == 0) - printf("0"); - else - printf("1"); - } - printf("\n"); - - return 0; -} - -U_BOOT_CMD( - dip, 1, 1, do_dip, - "dip - read dip switch on TRAB\n", - "\n" - " - read state of dip switch (S1) on TRAB board\n" - " read sequence: 1-2-3-4; ON=1; OFF=0; e.g.: \"0100\"\n" -); - - -int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int vcc5v; - - if (argc > 1) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - if ((vcc5v = read_vcc5v ()) == -1) { - return (1); - } - - printf ("%d", (vcc5v / 1000)); - printf (".%d", (vcc5v % 1000) / 100); - printf ("%d V\n", (vcc5v % 100) / 10) ; - - return 0; -} - -U_BOOT_CMD( - vcc5v, 1, 1, do_vcc5v, - "vcc5v - read VCC5V on TRAB\n", - "\n" - " - read actual value of voltage VCC5V\n" -); - - -int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int contact_temp; - - if (argc > 1) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - spi_init (); - - contact_temp = tsc2000_contact_temp(); - printf ("%d degree C * 100\n", contact_temp) ; - - return 0; -} - -U_BOOT_CMD( - c_temp, 1, 1, do_contact_temp, - "c_temp - read contact temperature on TRAB\n", - "\n" - " - reads the onboard temperature (=contact temperature)\n" -); - - -int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - if (argc > 1) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1, - (unsigned char*) &status, 1)) { - return (1); - } - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1, - (unsigned char*) &pass_cycles, 2)) { - return (1); - } - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE, - 1, (unsigned char*) &first_error_cycle, 2)) { - return (1); - } - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM, - 1, (unsigned char*) &first_error_num, 1)) { - return (1); - } - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME, - 1, first_error_name, - sizeof (first_error_name))) { - return (1); - } - - if (read_max_cycles () != 0) { - return (1); - } - - printf ("max_cycles = %d\n", max_cycles); - printf ("status = %d\n", status); - printf ("pass_cycles = %d\n", pass_cycles); - printf ("first_error_cycle = %d\n", first_error_cycle); - printf ("first_error_num = %d\n", first_error_num); - printf ("first_error_name = %.*s\n",(int) sizeof(first_error_name), - first_error_name); - - return 0; -} - -U_BOOT_CMD( - bis, 1, 1, do_burn_in_status, - "bis - print burn in status on TRAB\n", - "\n" - " - prints the status variables of the last burn in test\n" - " stored in the onboard EEPROM on TRAB board\n" -); - -static int read_dip (void) -{ - unsigned int result = 0; - int adc_val; - int i; - - /*********************************************************** - DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3): - SW1 - AIN4 - SW2 - AIN5 - SW3 - AIN6 - SW4 - AIN7 - - "On" DIP switch position short-circuits the voltage from - the input channel (i.e. '0' conversion result means "on"). - *************************************************************/ - - for (i = 7; i > 3; i--) { - - if ((adc_val = adc_read (i)) == -1) { - printf ("%s: Channel %d could not be read\n", - __FUNCTION__, i); - return (-1); - } - - /* - * Input voltage (switch open) is 1.8 V. - * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736 - * Set trigger at halve that value. - */ - if (adc_val < 368) - result |= (1 << (i-4)); - } - return (result); -} - - -static int read_vcc5v (void) -{ - s32 result; - - /* VCC5V is connected to channel 2 */ - - if ((result = adc_read (2)) == -1) { - printf ("%s: VCC5V could not be read\n", __FUNCTION__); - return (-1); - } - /* - * Calculate voltage value. Split in two parts because there is no - * floating point support. VCC5V is connected over an resistor divider: - * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K. - */ - result = result * 10 * 1000 / 1023; /* result in mV */ - - return (result); -} - - -static int test_dip (void) -{ - static int first_run = 1; - static int first_dip; - - if (first_run) { - if ((first_dip = read_dip ()) == -1) { - return (1); - } - first_run = 0; - debug ("%s: first_dip=%d\n", __FUNCTION__, first_dip); - } - if (first_dip != read_dip ()) { - return (1); - } else { - return (0); - } -} - - -static int test_vcc5v (void) -{ - int vcc5v; - - if ((vcc5v = read_vcc5v ()) == -1) { - return (1); - } - - if ((vcc5v > VCC5V_MAX) || (vcc5v < VCC5V_MIN)) { - printf ("%s: vcc5v[V/100]=%d\n", __FUNCTION__, vcc5v); - return (1); - } else { - return (0); - } -} - - -static int test_rotary_switch (void) -{ - static int first_run = 1; - static int first_rs; - - if (first_run) { - /* - * clear bits in CPLD, because they have random values after - * power-up or reset. - */ - *CPLD_ROTARY_SWITCH |= (1 << 16) | (1 << 17); - - first_rs = ((*CPLD_ROTARY_SWITCH >> 16) & 0x7); - first_run = 0; - debug ("%s: first_rs=%d\n", __FUNCTION__, first_rs); - } - - if (first_rs != ((*CPLD_ROTARY_SWITCH >> 16) & 0x7)) { - return (1); - } else { - return (0); - } -} - - -static int test_sram (void) -{ - return (memory_post_tests (SRAM_ADDR, SRAM_SIZE)); -} - - -static int test_eeprom (void) -{ - unsigned char temp[sizeof (EEPROM_TEST_STRING_1)]; - int result = 0; - - /* write test string 1, read back and verify */ - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, - EEPROM_TEST_STRING_1, - sizeof (EEPROM_TEST_STRING_1))) { - return (1); - } - - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, - temp, sizeof (EEPROM_TEST_STRING_1))) { - return (1); - } - - if (strcmp (temp, EEPROM_TEST_STRING_1) != 0) { - result = 1; - printf ("%s: error; read_str = \"%s\"\n", __FUNCTION__, temp); - } - - /* write test string 2, read back and verify */ - if (result == 0) { - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, - EEPROM_TEST_STRING_2, - sizeof (EEPROM_TEST_STRING_2))) { - return (1); - } - - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, - temp, sizeof (EEPROM_TEST_STRING_2))) { - return (1); - } - - if (strcmp (temp, EEPROM_TEST_STRING_2) != 0) { - result = 1; - printf ("%s: error; read str = \"%s\"\n", - __FUNCTION__, temp); - } - } - return (result); -} - - -static int test_contact_temp (void) -{ - int contact_temp; - - contact_temp = tsc2000_contact_temp (); - - if ((contact_temp < MIN_CONTACT_TEMP) - || (contact_temp > MAX_CONTACT_TEMP)) - return (1); - else - return (0); -} - - -int i2c_write_multiple (uchar chip, uint addr, int alen, - uchar *buffer, int len) -{ - int i; - - if (alen != 1) { - printf ("%s: addr len other than 1 not supported\n", - __FUNCTION__); - return (1); - } - - for (i = 0; i < len; i++) { - if (i2c_write (chip, addr+i, alen, buffer+i, 1)) { - printf ("%s: could not write to i2c device %d" - ", addr %d\n", __FUNCTION__, chip, addr); - return (1); - } -#if 0 - printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i=" - "%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i, - alen, buffer, i, buffer+i, buffer+i); -#endif - - udelay (30000); - } - return (0); -} - - -int i2c_read_multiple ( uchar chip, uint addr, int alen, - uchar *buffer, int len) -{ - int i; - - if (alen != 1) { - printf ("%s: addr len other than 1 not supported\n", - __FUNCTION__); - return (1); - } - - for (i = 0; i < len; i++) { - if (i2c_read (chip, addr+i, alen, buffer+i, 1)) { - printf ("%s: could not read from i2c device %#x" - ", addr %d\n", __FUNCTION__, chip, addr); - return (1); - } - } - return (0); -} - - -static int adc_read (unsigned int channel) -{ - int j = 1000; /* timeout value for wait loop in us */ - int result; - S3C2400_ADC *padc; - - padc = S3C2400_GetBase_ADC(); - channel &= 0x7; - - adc_init (); - - padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ - padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ - padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); - - while (j--) { - if ((padc->ADCCON & ADC_ENABLE_START) == 0) - break; - udelay (1); - } - - if (j == 0) { - printf("%s: ADC timeout\n", __FUNCTION__); - padc->ADCCON |= ADC_STDBM; /* select standby mode */ - return -1; - } - - result = padc->ADCDAT & 0x3FF; - - padc->ADCCON |= ADC_STDBM; /* select standby mode */ - - debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->ADCCON >> 3) & 0x7, result); - - /* - * Wait for ADC to be ready for next conversion. This delay value was - * estimated, because the datasheet does not specify a value. - */ - udelay (1000); - - return (result); -} - - -static void adc_init (void) -{ - S3C2400_ADC *padc; - - padc = S3C2400_GetBase_ADC(); - - padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ - padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ - - /* - * Wait some time to avoid problem with very first call of - * adc_read(). Without this delay, sometimes the first read - * adc value is 0. Perhaps because the adjustment of prescaler - * takes some clock cycles? - */ - udelay (1000); - - return; -} - - -static void led_set (unsigned int state) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - led_init (); - - switch (state) { - case 0: /* turn LED off */ - gpio->PADAT |= (1 << 12); - break; - case 1: /* turn LED on */ - gpio->PADAT &= ~(1 << 12); - break; - default: - break; - } -} - -static void led_blink (void) -{ - led_init (); - - /* blink LED. This function does not return! */ - while (1) { - led_set (1); - udelay (1000000 / LED_BLINK_FREQ / 2); - led_set (0); - udelay (1000000 / LED_BLINK_FREQ / 2); - } -} - - -static void led_init (void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* configure GPA12 as output and set to High -> LED off */ - gpio->PACON &= ~(1 << 12); - gpio->PADAT |= (1 << 12); -} - - -static void sdelay (unsigned long seconds) -{ - unsigned long i; - - for (i = 0; i < seconds; i++) { - udelay (1000000); - } -} - - -static int global_vars_write_to_eeprom (void) -{ - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1, - (unsigned char*) &status, 1)) { - return (1); - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1, - (unsigned char*) &pass_cycles, 2)) { - return (1); - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE, - 1, (unsigned char*) &first_error_cycle, 2)) { - return (1); - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM, - 1, (unsigned char*) &first_error_num, 1)) { - return (1); - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME, - 1, first_error_name, - sizeof(first_error_name))) { - return (1); - } - return (0); -} - -static void global_vars_init (void) -{ - status = 1; /* error */ - pass_cycles = 0; - first_error_cycle = 0; - first_error_num = 0; - first_error_name[0] = '\0'; - act_cycle = 0; - max_cycles = 0; -} - - -static void test_function_table_init (void) -{ - int i; - - for (i = 0; i < BIF_MAX; i++) - test_function[i].pf = dummy; - - /* - * the length of "name" must not exceed 16, including the '\0' - * termination. See also the EEPROM address map. - */ - test_function[0].pf = test_dip; - test_function[0].name = "dip"; - - test_function[1].pf = test_vcc5v; - test_function[1].name = "vcc5v"; - - test_function[2].pf = test_rotary_switch; - test_function[2].name = "rotary_switch"; - - test_function[3].pf = test_sram; - test_function[3].name = "sram"; - - test_function[4].pf = test_eeprom; - test_function[4].name = "eeprom"; - - test_function[5].pf = test_contact_temp; - test_function[5].name = "contact_temp"; -} - - -static int read_max_cycles (void) -{ - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_MAX_CYCLES, 1, - (unsigned char *) &max_cycles, 2) != 0) { - return (1); - } - - return (0); -} - -static int dummy(void) -{ - return (0); -} - -int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int contact_temp; - int delay = 0; -#if (CONFIG_COMMANDS & CFG_CMD_DATE) - struct rtc_time tm; -#endif - - if (argc > 2) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - if (argc > 1) { - delay = simple_strtoul(argv[1], NULL, 10); - } - - spi_init (); - while (1) { - -#if (CONFIG_COMMANDS & CFG_CMD_DATE) - rtc_get (&tm); - printf ("%4d-%02d-%02d %2d:%02d:%02d - ", - tm.tm_year, tm.tm_mon, tm.tm_mday, - tm.tm_hour, tm.tm_min, tm.tm_sec); -#endif - - contact_temp = tsc2000_contact_temp(); - printf ("%d\n", contact_temp) ; - - if (delay != 0) - /* - * reset timer to avoid timestamp overflow problem - * after about 68 minutes of udelay() time. - */ - reset_timer_masked (); - sdelay (delay); - } - - return 0; -} - -U_BOOT_CMD( - tlog, 2, 1, do_temp_log, - "tlog - log contact temperature [1/100 C] to console (endlessly)\n", - "delay\n" - " - contact temperature [1/100 C] is printed endlessly to console\n" - " specifies the seconds to wait between two measurements\n" - " For each measurment a timestamp is printeted\n" -); - -#endif /* CFG_CMD_BSP */ diff --git a/board/trab/config.mk b/board/trab/config.mk deleted file mode 100644 index f2411d0..0000000 --- a/board/trab/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# TRAB board with S3C2400X (arm920t) cpu -# -# see http://www.samsung.com/ for more information on SAMSUNG -# - -# -# TRAB has 1 bank of 16 MB or 32 MB DRAM -# -# 0c00'0000 to 0e00'0000 -# -# Linux-Kernel is expected to be at 0c00'8000, entry 0c00'8000 -# -# we load ourself to 0CF0'0000 / 0DF0'0000 -# -# download areas is 0C80'0000 -# - -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -TEXT_BASE = 0x0DF40000 -endif diff --git a/board/trab/flash.c b/board/trab/flash.c deleted file mode 100644 index b4435e3..0000000 --- a/board/trab/flash.c +++ /dev/null @@ -1,568 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include -#include - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x00F000F0 -#define CMD_UNLOCK1 0x00AA00AA -#define CMD_UNLOCK2 0x00550055 -#define CMD_ERASE_SETUP 0x00800080 -#define CMD_ERASE_CONFIRM 0x00300030 -#define CMD_PROGRAM 0x00A000A0 -#define CMD_UNLOCK_BYPASS 0x00200020 -#define CMD_READ_MANF_ID 0x00900090 -#define CMD_UNLOCK_BYPASS_RES1 0x00900090 -#define CMD_UNLOCK_BYPASS_RES2 0x00000000 - -#define MEM_FLASH_ADDR (*(volatile u32 *)CFG_FLASH_BASE) -#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2))) -#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2))) - -#define BIT_ERASE_DONE 0x00800080 -#define BIT_RDY_MASK 0x00800080 -#define BIT_PROGRAM_ERROR 0x00200020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i=0; iflash_id = FLASH_UNKNOWN; - - size += flash_get_size (CFG_FLASH_BASE, info); - - if (i == 0) - flashbase = CFG_FLASH_BASE; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < info->sector_count; j++) { - - info->protect[j] = 0; - info->start[j] = flashbase; - - switch (info->flash_id & FLASH_TYPEMASK) { - case (FLASH_AM320B & FLASH_TYPEMASK): - case (FLASH_MXLV320B & FLASH_TYPEMASK): - /* Boot sector type: 8 x 8 + N x 128 kB */ - flashbase += (j < 8) ? 0x4000 : 0x20000; - break; - case (FLASH_AM640U & FLASH_TYPEMASK): - /* Uniform sector type: 128 kB */ - flashbase += 0x20000; - break; - default: - printf ("## Bad flash chip type 0x%04lX\n", - info->flash_id & FLASH_TYPEMASK); - } - } - } - - /* - * Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - -#ifdef CFG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[0]); -#endif - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (FLASH_MAN_AMD & FLASH_VENDMASK): - printf ("AMD "); break; - case (FLASH_MAN_FUJ & FLASH_VENDMASK): - printf ("FUJITSU "); break; - case (FLASH_MAN_MX & FLASH_VENDMASK): - printf ("MACRONIX "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (FLASH_AM320B & FLASH_TYPEMASK): - printf ("2x Am29LV320DB (32Mbit)\n"); - break; - case (FLASH_MXLV320B & FLASH_TYPEMASK): - printf ("2x MX29LV320DB (32Mbit)\n"); - break; - case (FLASH_AM640U & FLASH_TYPEMASK): - printf ("2x Am29LV640D (64Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - -#if 0 - int cflag; -#endif - int iflag, prot, sect; - int rc = ERR_OK; - int chip1, chip2; - - debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last); - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case (FLASH_MAN_AMD & FLASH_VENDMASK): break; /* OK */ - case (FLASH_MAN_FUJ & FLASH_VENDMASK): break; /* OK */ - case (FLASH_MAN_MX & FLASH_VENDMASK): break; /* OK */ - default: - debug ("## flash_erase: unknown manufacturer\n"); - return (ERR_UNKNOWN_FLASH_VENDOR); - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#if 0 - cflag = icache_status (); - icache_disable (); -#endif - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - debug ("Erasing sector %2d @ %08lX... ", - sect, info->start[sect]); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = chip2 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip1 = ERR; - - if (!chip2 && (result >> 16) & BIT_ERASE_DONE) - chip2 = READY; - - if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) - chip2 = ERR; - - } while (!chip1 || !chip2); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR || chip2 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - } - } - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - -#if 0 - if (cflag) - icache_enable (); -#endif - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -volatile static int write_word (flash_info_t * info, ulong dest, - ulong data) -{ - vu_long *addr = (vu_long *) dest; - ulong result; - int rc = ERR_OK; - -#if 0 - int cflag; -#endif - int iflag; - int chip1, chip2; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#if 0 - cflag = icache_status (); - icache_disable (); -#endif - iflag = disable_interrupts (); - - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip1 = chip2 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip1 = READY; - else - chip1 = ERR; - } - - if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) - chip2 = READY; - - if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & (0x80 << 16)) == (data & (0x80 << 16))) - chip2 = READY; - else - chip2 = ERR; - } - - } while (!chip1 || !chip2); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || chip2 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - -#if 0 - if (cflag) - icache_enable (); -#endif - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - if ((rc = write_word (info, wp, data)) != 0) { - goto Done; - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - if (((ulong)src) & 0x3) { - for (i = 0; i < 4; i++) { - ((char *)&data)[i] = ((vu_char *)src)[i]; - } - } - else { - data = *((vu_long *) src); - } - - if ((rc = write_word (info, wp, data)) != 0) { - goto Done; - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - rc = ERR_OK; - goto Done; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - rc = write_word (info, wp, data); - - Done: - - MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES1; - MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES2; - - return (rc); -} - -/*----------------------------------------------------------------------- - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - ulong value; - - /* Write auto select command sequence and read Manufacturer ID */ - addr[0x0555] = CMD_UNLOCK1; - addr[0x02AA] = CMD_UNLOCK2; - addr[0x0555] = CMD_READ_MANF_ID; - - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case MX_MANUFACT: - info->flash_id = FLASH_MAN_MX; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = 0x00FF00FF; /* restore read mode */ - debug ("## flash_init: unknown manufacturer\n"); - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - - addr[0] = 0x00FF00FF; /* restore read mode */ - break; /* => 8 MB */ - - case AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x01000000; - - addr[0] = 0x00F000F0; /* restore read mode */ - break; /* => 16 MB */ - - case MX_ID_LV320B: - info->flash_id += FLASH_MXLV320B; - info->sector_count = 71; - info->size = 0x00800000; - - addr[0] = 0x00FF00FF; /* restore read mode */ - break; /* => 8 MB */ - - default: - debug ("## flash_init: unknown flash chip\n"); - info->flash_id = FLASH_UNKNOWN; - addr[0] = 0x00FF00FF; /* restore read mode */ - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - return (info->size); -} diff --git a/board/trab/lowlevel_init.S b/board/trab/lowlevel_init.S deleted file mode 100644 index 128ae7e..0000000 --- a/board/trab/lowlevel_init.S +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the TRAB board by - * (C) Copyright 2002-2003 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* some parameters for the board */ - -/* - * - * Copied from linux/arch/arm/boot/compressed/head-s3c2400.S - * - * Copyright (C) 2001 Samsung Electronics by chc, 010406 - * - * TRAB specific tweaks. - * - */ - -/* memory controller */ -#define BWSCON 0x14000000 - -/* Bank0 */ -#define B0_Tacs 0x1 /* 1 clk */ -#define B0_Tcos 0x1 /* 1 clk */ -#define B0_Tacc 0x5 /* 8 clk */ -#define B0_Tcoh 0x1 /* 1 clk */ -#define B0_Tah 0x1 /* 1 clk */ -#define B0_Tacp 0x0 -#define B0_PMC 0x0 /* normal */ - -/* Bank1 - SRAM */ -#define B1_Tacs 0x1 /* 1 clk */ -#define B1_Tcos 0x1 /* 1 clk */ -#define B1_Tacc 0x5 /* 8 clk */ -#define B1_Tcoh 0x1 /* 1 clk */ -#define B1_Tah 0x1 /* 1 clk */ -#define B1_Tacp 0x0 -#define B1_PMC 0x0 /* normal */ - -/* Bank2 - CPLD */ -#define B2_Tacs 0x1 /* 1 clk */ -#define B2_Tcos 0x1 /* 1 clk */ -#define B2_Tacc 0x5 /* 8 clk */ -#define B2_Tcoh 0x1 /* 1 clk */ -#define B2_Tah 0x1 /* 1 clk */ -#define B2_Tacp 0x0 -#define B2_PMC 0x0 /* normal */ - -/* Bank3 - setup for the cs8900 */ -#define B3_Tacs 0x3 /* 4 clk */ -#define B3_Tcos 0x3 /* 4 clk */ -#define B3_Tacc 0x7 /* 14 clk */ -#define B3_Tcoh 0x1 /* 1 clk */ -#define B3_Tah 0x0 /* 0 clk */ -#define B3_Tacp 0x3 /* 6 clk */ -#define B3_PMC 0x0 /* normal */ - -/* Bank4 */ -#define B4_Tacs 0x0 /* 0 clk */ -#define B4_Tcos 0x0 /* 0 clk */ -#define B4_Tacc 0x7 /* 14 clk */ -#define B4_Tcoh 0x0 /* 0 clk */ -#define B4_Tah 0x0 /* 0 clk */ -#define B4_Tacp 0x0 -#define B4_PMC 0x0 /* normal */ - -/* Bank5 */ -#define B5_Tacs 0x0 /* 0 clk */ -#define B5_Tcos 0x0 /* 0 clk */ -#define B5_Tacc 0x7 /* 14 clk */ -#define B5_Tcoh 0x0 /* 0 clk */ -#define B5_Tah 0x0 /* 0 clk */ -#define B5_Tacp 0x0 -#define B5_PMC 0x0 /* normal */ - -#ifndef CONFIG_RAM_16MB /* 32 MB RAM */ -/* Bank6 */ -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x0 /* 2clk */ -#define B6_SCAN 0x1 /* 9 bit */ - -/* Bank7 */ -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x0 /* 2clk */ -#define B7_SCAN 0x1 /* 9 bit */ -#else /* CONFIG_RAM_16MB = 16 MB RAM */ -/* Bank6 */ -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 2clk */ -#define B6_SCAN 0x0 /* 8 bit */ - -/* Bank7 */ -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 2clk */ -#define B7_SCAN 0x0 /* 8 bit */ -#endif /* CONFIG_RAM_16MB */ - -/* refresh parameter */ -#define REFEN 0x1 /* enable refresh */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ -#define Trp 0x0 /* 2 clk */ -#define Trc 0x3 /* 7 clk */ -#define Tchr 0x2 /* 3 clk */ - -#ifdef CONFIG_TRAB_50MHZ -#define REFCNT 1269 /* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */ -#else -#define REFCNT 1011 /* period=15.6 us, HCLK=66.5Mhz, (2048+1-15.6*66.5) */ -#endif - - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevel_init -lowlevel_init: - /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #52 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ - -SMRDATA: - .word 0x2211d644 /* d->Ethernet, 6->CPLD, 4->SRAM, 4->FLASH */ - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */ - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */ - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */ - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */ - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */ - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */ - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */ - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) -#ifndef CONFIG_RAM_16MB /* 32 MB RAM */ - .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */ -#else /* CONFIG_RAM_16MB = 16 MB RAM */ - .word 0x17 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */ -#endif /* CONFIG_RAM_16MB */ - .word 0x20 /* MRSR6, CL=2clk */ - .word 0x20 /* MRSR7 */ diff --git a/board/trab/memory.c b/board/trab/memory.c deleted file mode 100644 index 9104413..0000000 --- a/board/trab/memory.c +++ /dev/null @@ -1,485 +0,0 @@ -/* - * (C) Copyright 2002-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* Memory test - * - * General observations: - * o The recommended test sequence is to test the data lines: if they are - * broken, nothing else will work properly. Then test the address - * lines. Finally, test the cells in the memory now that the test - * program knows that the address and data lines work properly. - * This sequence also helps isolate and identify what is faulty. - * - * o For the address line test, it is a good idea to use the base - * address of the lowest memory location, which causes a '1' bit to - * walk through a field of zeros on the address lines and the highest - * memory location, which causes a '0' bit to walk through a field of - * '1's on the address line. - * - * o Floating buses can fool memory tests if the test routine writes - * a value and then reads it back immediately. The problem is, the - * write will charge the residual capacitance on the data bus so the - * bus retains its state briefely. When the test program reads the - * value back immediately, the capacitance of the bus can allow it - * to read back what was written, even though the memory circuitry - * is broken. To avoid this, the test program should write a test - * pattern to the target location, write a different pattern elsewhere - * to charge the residual capacitance in a differnt manner, then read - * the target location back. - * - * o Always read the target location EXACTLY ONCE and save it in a local - * variable. The problem with reading the target location more than - * once is that the second and subsequent reads may work properly, - * resulting in a failed test that tells the poor technician that - * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which - * doesn't help him one bit and causes puzzled phone calls. Been there, - * done that. - * - * Data line test: - * --------------- - * This tests data lines for shorts and opens by forcing adjacent data - * to opposite states. Because the data lines could be routed in an - * arbitrary manner the must ensure test patterns ensure that every case - * is tested. By using the following series of binary patterns every - * combination of adjacent bits is test regardless of routing. - * - * ...101010101010101010101010 - * ...110011001100110011001100 - * ...111100001111000011110000 - * ...111111110000000011111111 - * - * Carrying this out, gives us six hex patterns as follows: - * - * 0xaaaaaaaaaaaaaaaa - * 0xcccccccccccccccc - * 0xf0f0f0f0f0f0f0f0 - * 0xff00ff00ff00ff00 - * 0xffff0000ffff0000 - * 0xffffffff00000000 - * - * To test for short and opens to other signals on our boards, we - * simply test with the 1's complemnt of the paterns as well, resulting - * in twelve patterns total. - * - * After writing a test pattern. a special pattern 0x0123456789ABCDEF is - * written to a different address in case the data lines are floating. - * Thus, if a byte lane fails, you will see part of the special - * pattern in that byte lane when the test runs. For example, if the - * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa - * (for the 'a' test pattern). - * - * Address line test: - * ------------------ - * This function performs a test to verify that all the address lines - * hooked up to the RAM work properly. If there is an address line - * fault, it usually shows up as two different locations in the address - * map (related by the faulty address line) mapping to one physical - * memory storage location. The artifact that shows up is writing to - * the first location "changes" the second location. - * - * To test all address lines, we start with the given base address and - * xor the address with a '1' bit to flip one address line. For each - * test, we shift the '1' bit left to test the next address line. - * - * In the actual code, we start with address sizeof(ulong) since our - * test pattern we use is a ulong and thus, if we tried to test lower - * order address bits, it wouldn't work because our pattern would - * overwrite itself. - * - * Example for a 4 bit address space with the base at 0000: - * 0000 <- base - * 0001 <- test 1 - * 0010 <- test 2 - * 0100 <- test 3 - * 1000 <- test 4 - * Example for a 4 bit address space with the base at 0010: - * 0010 <- base - * 0011 <- test 1 - * 0000 <- (below the base address, skipped) - * 0110 <- test 2 - * 1010 <- test 3 - * - * The test locations are successively tested to make sure that they are - * not "mirrored" onto the base address due to a faulty address line. - * Note that the base and each test location are related by one address - * line flipped. Note that the base address need not be all zeros. - * - * Memory tests 1-4: - * ----------------- - * These tests verify RAM using sequential writes and reads - * to/from RAM. There are several test cases that use different patterns to - * verify RAM. Each test case fills a region of RAM with one pattern and - * then reads the region back and compares its contents with the pattern. - * The following patterns are used: - * - * 1a) zero pattern (0x00000000) - * 1b) negative pattern (0xffffffff) - * 1c) checkerboard pattern (0x55555555) - * 1d) checkerboard pattern (0xaaaaaaaa) - * 2) bit-flip pattern ((1 << (offset % 32)) - * 3) address pattern (offset) - * 4) address pattern (~offset) - * - * Being run in normal mode, the test verifies only small 4Kb - * regions of RAM around each 1Mb boundary. For example, for 64Mb - * RAM the following areas are verified: 0x00000000-0x00000800, - * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- - * 0x04000000. If the test is run in slow-test mode, it verifies - * the whole RAM. - */ - -/* #ifdef CONFIG_POST */ - -#include -#include - -/* #if CONFIG_POST & CFG_POST_MEMORY */ - -/* - * Define INJECT_*_ERRORS for testing error detection in the presence of - * _good_ hardware. - */ -#undef INJECT_DATA_ERRORS -#undef INJECT_ADDRESS_ERRORS - -#ifdef INJECT_DATA_ERRORS -#warning "Injecting data line errors for testing purposes" -#endif - -#ifdef INJECT_ADDRESS_ERRORS -#warning "Injecting address line errors for testing purposes" -#endif - - -/* - * This function performs a double word move from the data at - * the source pointer to the location at the destination pointer. - * This is helpful for testing memory on processors which have a 64 bit - * wide data bus. - * - * On those PowerPC with FPU, use assembly and a floating point move: - * this does a 64 bit move. - * - * For other processors, let the compiler generate the best code it can. - */ -static void move64(unsigned long long *src, unsigned long long *dest) -{ -#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0" ); /* Clobbers fr0 */ - return; -#else - *dest = *src; -#endif -} - -/* - * This is 64 bit wide test patterns. Note that they reside in ROM - * (which presumably works) and the tests write them to RAM which may - * not work. - * - * The "otherpattern" is written to drive the data bus to values other - * than the test pattern. This is for detecting floating bus lines. - * - */ -const static unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL, -}; -const unsigned long long otherpattern = 0x0123456789abcdefULL; - - -static int memory_post_dataline(unsigned long long * pmem) -{ - unsigned long long temp64; - int num_patterns = sizeof(pattern)/ sizeof(pattern[0]); - int i; - unsigned int hi, lo, pathi, patlo; - int ret = 0; - - for ( i = 0; i < num_patterns; i++) { - move64((unsigned long long *)&(pattern[i]), pmem++); - /* - * Put a different pattern on the data lines: otherwise they - * may float long enough to read back what we wrote. - */ - move64((unsigned long long *)&otherpattern, pmem--); - move64(pmem, &temp64); - -#ifdef INJECT_DATA_ERRORS - temp64 ^= 0x00008000; -#endif - - if (temp64 != pattern[i]){ - pathi = (pattern[i]>>32) & 0xffffffff; - patlo = pattern[i] & 0xffffffff; - - hi = (temp64>>32) & 0xffffffff; - lo = temp64 & 0xffffffff; - - printf ("Memory (date line) error at %08lx, " - "wrote %08x%08x, read %08x%08x !\n", - (ulong)pmem, pathi, patlo, hi, lo); - ret = -1; - } - } - return ret; -} - -static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) -{ - ulong *target; - ulong *end; - ulong readback; - ulong xor; - int ret = 0; - - end = (ulong *)((ulong)base + size); /* pointer arith! */ - xor = 0; - for(xor = sizeof(ulong); xor > 0; xor <<= 1) { - target = (ulong *)((ulong)testaddr ^ xor); - if((target >= base) && (target < end)) { - *testaddr = ~*target; - readback = *target; - -#ifdef INJECT_ADDRESS_ERRORS - if(xor == 0x00008000) { - readback = *testaddr; - } -#endif - if(readback == *testaddr) { - printf ("Memory (address line) error at %08lx<->%08lx, " - "XOR value %08lx !\n", - (ulong)testaddr, (ulong)target, - xor); - ret = -1; - } - } - } - return ret; -} - -static int memory_post_test1 (unsigned long start, - unsigned long size, - unsigned long val) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = val; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != val) { - printf ("Memory error at %08lx, " - "wrote %08lx, read %08lx !\n", - (ulong)(mem + i), val, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test2 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = 1 << (i % 32); - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != (1 << (i % 32))) { - printf ("Memory error at %08lx, " - "wrote %08x, read %08lx !\n", - (ulong)(mem + i), 1 << (i % 32), readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test3 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = i; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != i) { - printf ("Memory error at %08lx, " - "wrote %08lx, read %08lx !\n", - (ulong)(mem + i), i, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test4 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = ~i; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != ~i) { - printf ("Memory error at %08lx, " - "wrote %08lx, read %08lx !\n", - (ulong)(mem + i), ~i, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -int memory_post_tests (unsigned long start, unsigned long size) -{ - int ret = 0; - - if (ret == 0) - ret = memory_post_dataline ((long long *)start); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_addrline ((long *)start, (long *)start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_addrline ((long *)(start + size - 8), - (long *)start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0x00000000); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0xffffffff); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0x55555555); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0xaaaaaaaa); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test2 (start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test3 (start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test4 (start, size); - WATCHDOG_RESET (); - - return ret; -} - -#if 0 -int memory_post_test (int flags) -{ - int ret = 0; - DECLARE_GLOBAL_DATA_PTR; - bd_t *bd = gd->bd; - unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? - 256 << 20 : bd->bi_memsize) - (1 << 20); - - - if (flags & POST_SLOWTEST) { - ret = memory_post_tests (CFG_SDRAM_BASE, memsize); - } else { /* POST_NORMAL */ - - unsigned long i; - - for (i = 0; i < (memsize >> 20) && ret == 0; i++) { - if (ret == 0) - ret = memory_post_tests (i << 20, 0x800); - if (ret == 0) - ret = memory_post_tests ((i << 20) + 0xff800, 0x800); - } - } - - return ret; -} -#endif /* 0 */ - -/* #endif */ /* CONFIG_POST & CFG_POST_MEMORY */ -/* #endif */ /* CONFIG_POST */ diff --git a/board/trab/rs485.c b/board/trab/rs485.c deleted file mode 100644 index 2aedd2d..0000000 --- a/board/trab/rs485.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Krause, TQ-Systems GmbH, - * - * Based on cpu/arm920t/serial.c, by Gary Jennejohn - * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include -#include "rs485.h" - -static void rs485_setbrg (void); -static void rs485_cfgio (void); -static void set_rs485re(unsigned char rs485re_state); -static void set_rs485de(unsigned char rs485de_state); -static void rs485_setbrg (void); -#ifdef NOT_USED -static void trab_rs485_disable_tx(void); -static void trab_rs485_disable_rx(void); -#endif - -#define UART_NR S3C24X0_UART1 - -/* CPLD-Register for controlling TRAB hardware functions */ -#define CPLD_RS485_RE ((volatile unsigned long *)0x04028000) - -static void rs485_setbrg (void) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); - int i; - unsigned int reg = 0; - - /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ - /* reg = (33000000 / (16 * gd->baudrate)) - 1; */ - reg = (33000000 / (16 * 38400)) - 1; - - /* FIFO enable, Tx/Rx FIFO clear */ - uart->UFCON = 0x07; - uart->UMCON = 0x0; - /* Normal,No parity,1 stop,8 bit */ - uart->ULCON = 0x3; - /* - * tx=level,rx=edge,disable timeout int.,enable rx error int., - * normal,interrupt or polling - */ - uart->UCON = 0x245; - uart->UBRDIV = reg; - - for (i = 0; i < 100; i++); -} - -static void rs485_cfgio (void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - gpio->PFCON &= ~(0x3 << 2); - gpio->PFCON |= (0x2 << 2); /* configure GPF1 as RXD1 */ - - gpio->PFCON &= ~(0x3 << 6); - gpio->PFCON |= (0x2 << 6); /* configure GPF3 as TXD1 */ - - gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */ - gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */ - - gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */ -} - -/* - * Initialise the rs485 port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int rs485_init (void) -{ - rs485_cfgio (); - rs485_setbrg (); - - return (0); -} - -/* - * Read a single byte from the rs485 port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int rs485_getc (void) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); - - /* wait for character to arrive */ - while (!(uart->UTRSTAT & 0x1)); - - return uart->URXH & 0xff; -} - -/* - * Output a single byte to the rs485 port. - */ -void rs485_putc (const char c) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); - - /* wait for room in the tx FIFO */ - while (!(uart->UTRSTAT & 0x2)); - - uart->UTXH = c; - - /* If \n, also do \r */ - if (c == '\n') - rs485_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int rs485_tstc (void) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); - - return uart->UTRSTAT & 0x1; -} - -void rs485_puts (const char *s) -{ - while (*s) { - rs485_putc (*s++); - } -} - - -/* - * State table: - * RE DE Result - * 1 1 XMIT - * 0 0 RCV - * 1 0 Shutdown - */ - -/* function that controls the receiver enable for the rs485 */ -/* rs485re_state reflects the level (0/1) of the RE pin */ - -static void set_rs485re(unsigned char rs485re_state) -{ - if(rs485re_state) - *CPLD_RS485_RE = 0x010000; - else - *CPLD_RS485_RE = 0x0; -} - -/* function that controls the sender enable for the rs485 */ -/* rs485de_state reflects the level (0/1) of the DE pin */ - -static void set_rs485de(unsigned char rs485de_state) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* This is on PORT A bit 11 */ - if(rs485de_state) - gpio->PADAT |= (1 << 11); - else - gpio->PADAT &= ~(1 << 11); -} - - -void trab_rs485_enable_tx(void) -{ - set_rs485de(1); - set_rs485re(1); -} - -void trab_rs485_enable_rx(void) -{ - set_rs485re(0); - set_rs485de(0); -} - -#ifdef NOT_USED -static void trab_rs485_disable_tx(void) -{ - set_rs485de(0); -} - -static void trab_rs485_disable_rx(void) -{ - set_rs485re(1); -} -#endif diff --git a/board/trab/rs485.h b/board/trab/rs485.h deleted file mode 100644 index d4a008a..0000000 --- a/board/trab/rs485.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Krause, TQ-Systems GmbH, - * - * Based on cpu/arm920t/serial.c, by Gary Jennejohn - * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef _RS485_H_ -#define _RS485_H_ - -#include - -int rs485_init (void); -int rs485_getc (void); -void rs485_putc (const char c); -int rs485_tstc (void); -void rs485_puts (const char *s); -void trab_rs485_enable_tx(void); -void trab_rs485_enable_rx(void); - -#endif /* _RS485_H_ */ diff --git a/board/trab/trab.c b/board/trab/trab.c deleted file mode 100644 index e8dfd2c..0000000 --- a/board/trab/trab.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#ifdef CFG_BRIGHTNESS -static void spi_init(void); -static void wait_transmit_done(void); -static void tsc2000_write(unsigned int page, unsigned int reg, - unsigned int data); -static void tsc2000_set_brightness(void); -#endif -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void); -extern void disable_putc(void); -extern int do_mdm_init; /* defined in common/main.c */ - -/* - * We need a delay of at least 500 us after turning on the VFD clock - * before we can read any useful information for the CPLD controlling - * the keyboard switches. Let's play safe and wait 5 ms. The problem - * is that timers are not available yet, so we use a manually timed - * loop. - */ -#define KBD_MDELAY 5000 -static void udelay_no_timer (int usec) -{ - DECLARE_GLOBAL_DATA_PTR; - - int i; - int delay = usec * 3; - - for (i = 0; i < delay; i ++) gd->bd->bi_arch_number = MACH_TYPE_TRAB; -} -#endif /* CONFIG_MODEM_SUPPORT */ - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init () -{ -#if defined(CONFIG_VFD) - extern int vfd_init_clocks(void); -#endif - DECLARE_GLOBAL_DATA_PTR; - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* memory and cpu-speed are setup before relocation */ -#ifdef CONFIG_TRAB_50MHZ - /* change the clock to be 50 MHz 1:1:1 */ - /* MDIV:0x5c PDIV:4 SDIV:2 */ - clk_power->MPLLCON = 0x5c042; - clk_power->CLKDIVN = 0; -#else - /* change the clock to be 133 MHz 1:2:4 */ - /* MDIV:0x7d PDIV:4 SDIV:1 */ - clk_power->MPLLCON = 0x7d041; - clk_power->CLKDIVN = 3; -#endif - - /* set up the I/O ports */ - gpio->PACON = 0x3ffff; - gpio->PBCON = 0xaaaaaaaa; - gpio->PBUP = 0xffff; - /* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */ - /* 00, 10, 10, 10, 10, 10, 10 */ - gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10); -#ifdef CONFIG_HWFLOW - /* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */ - gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5); -#else - /* do not pull up RXD0, RXD1, TXD0, TXD1 */ - gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3); -#endif - gpio->PGCON = 0x0; - gpio->PGUP = 0x0; - gpio->OPENCR= 0x0; - - /* suppress flicker of the VFDs */ - gpio->MISCCR = 0x40; - gpio->PFCON |= (2<<12); - - gd->bd->bi_arch_number = MACH_TYPE_TRAB; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x0c000100; - - /* Make sure both buzzers are turned off */ - gpio->PDCON |= 0x5400; - gpio->PDDAT &= ~0xE0; - -#ifdef CONFIG_VFD - vfd_init_clocks(); -#endif /* CONFIG_VFD */ - -#ifdef CONFIG_MODEM_SUPPORT - udelay_no_timer (KBD_MDELAY); - - if (key_pressed()) { - disable_putc(); /* modem doesn't understand banner etc */ - do_mdm_init = 1; - } -#endif /* CONFIG_MODEM_SUPPORT */ - -#ifdef CONFIG_DRIVER_S3C24X0_I2C - /* Configure I/O ports PG5 und PG6 for I2C */ - gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00; -#endif /* CONFIG_DRIVER_S3C24X0_I2C */ - - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - return 0; -} - -/*----------------------------------------------------------------------- - * Keyboard Controller - */ - -/* Maximum key number */ -#define KEYBD_KEY_NUM 4 - -#define KBD_DATA (((*(volatile ulong *)0x04020000) >> 16) & 0xF) - -static uchar *key_match (ulong); - -int misc_init_r (void) -{ - ulong kbd_data = KBD_DATA; - uchar keybd_env[KEYBD_KEY_NUM + 1]; - uchar *str; - int i; - -#ifdef CONFIG_AUTO_UPDATE - extern int do_auto_update(void); - /* this has priority over all else */ - do_auto_update(); -#endif - - for (i = 0; i < KEYBD_KEY_NUM; ++i) { - keybd_env[i] = '0' + ((kbd_data >> i) & 1); - } - keybd_env[i] = '\0'; - debug ("** Setting keybd=\"%s\"\n", keybd_env); - setenv ("keybd", keybd_env); - - str = strdup (key_match (kbd_data)); /* decode keys */ - -#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ - debug ("** Setting preboot=\"%s\"\n", str); - setenv ("preboot", str); /* set or delete definition */ -#endif /* CONFIG_PREBOOT */ - if (str != NULL) { - free (str); - } - -#ifdef CFG_BRIGHTNESS - tsc2000_set_brightness(); -#endif - return (0); -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -static int compare_magic (ulong kbd_data, uchar *str) -{ - uchar key_mask; - - debug ("compare_magic: kbd: %04lx str: \"%s\"\n",kbd_data,str); - for (; *str; str++) - { - uchar c = *str - '1'; - - if (c >= KEYBD_KEY_NUM) /* bad key number */ - return -1; - - key_mask = 1 << c; - - if (!(kbd_data & key_mask)) { /* key not pressed */ - debug ( "compare_magic: " - "kbd: %04lx mask: %04lx - key not pressed\n", - kbd_data, key_mask ); - return -1; - } - - kbd_data &= ~key_mask; - } - - if (kbd_data) { /* key(s) not released */ - debug ( "compare_magic: " - "kbd: %04lx - key(s) not released\n", kbd_data); - return -1; - } - - return 0; -} - -/*----------------------------------------------------------------------- - * Check if pressed key(s) match magic sequence, - * and return the command string associated with that key(s). - * - * If no key press was decoded, NULL is returned. - * - * Note: the first character of the argument will be overwritten with - * the "magic charcter code" of the decoded key(s), or '\0'. - * - * - * Note: the string points to static environment data and must be - * saved before you call any function that modifies the environment. - */ -static uchar *key_match (ulong kbd_data) -{ - uchar magic[sizeof (kbd_magic_prefix) + 1]; - uchar cmd_name[sizeof (kbd_command_prefix) + 1]; - uchar *suffix; - uchar *kbd_magic_keys; - - /* - * The following string defines the characters that can pe appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - debug ("key_match: magic_keys=\"%s\"\n", kbd_magic_keys); - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix=kbd_magic_keys; *suffix || suffix==kbd_magic_keys; ++suffix) - { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); - - debug ("key_match: magic=\"%s\"\n", - getenv(magic) ? getenv(magic) : ""); - - if (compare_magic(kbd_data, getenv(magic)) == 0) - { - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - debug ("key_match: cmdname %s=\"%s\"\n", - cmd_name, - getenv (cmd_name) ? - getenv (cmd_name) : - ""); - return (getenv (cmd_name)); - } - } - debug ("key_match: no match\n"); - return (NULL); -} -#endif /* CONFIG_PREBOOT */ - -/* Read Keyboard status */ -int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - ulong kbd_data = KBD_DATA; - uchar keybd_env[KEYBD_KEY_NUM + 1]; - int i; - - puts ("Keys:"); - for (i = 0; i < KEYBD_KEY_NUM; ++i) { - keybd_env[i] = '0' + ((kbd_data >> i) & 1); - printf (" %c", keybd_env[i]); - } - keybd_env[i] = '\0'; - putc ('\n'); - setenv ("keybd", keybd_env); - return 0; -} - -U_BOOT_CMD( - kbd, 1, 1, do_kbd, - "kbd - read keyboard status\n", - NULL -); - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void) -{ - return (compare_magic(KBD_DATA, CONFIG_MODEM_KEY_MAGIC) == 0); -} -#endif /* CONFIG_MODEM_SUPPORT */ - -#ifdef CFG_BRIGHTNESS - -static inline void SET_CS_TOUCH(void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - gpio->PDDAT &= 0x5FF; -} - -static inline void CLR_CS_TOUCH(void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - gpio->PDDAT |= 0x200; -} - -static void spi_init(void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); - int i; - - /* Configure I/O ports. */ - gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; - gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; - gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; - gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; - - CLR_CS_TOUCH(); - - spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */ - spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */ - spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */ - - /* Dummy byte ensures clock to be low. */ - for (i = 0; i < 10; i++) { - spi->ch[0].SPTDAT = 0xFF; - } - wait_transmit_done(); -} - -static void wait_transmit_done(void) -{ - S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); - - while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */ -} - -static void tsc2000_write(unsigned int page, unsigned int reg, - unsigned int data) -{ - S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); - unsigned int command; - - SET_CS_TOUCH(); - command = 0x0000; - command |= (page << 11); - command |= (reg << 5); - - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; - wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); - wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; - wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0x00FF); - wait_transmit_done(); - - CLR_CS_TOUCH(); -} - -static void tsc2000_set_brightness(void) -{ - uchar tmp[10]; - int i, br; - - spi_init(); - tsc2000_write(1, 2, 0x0); /* Power up DAC */ - - i = getenv_r("brightness", tmp, sizeof(tmp)); - br = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CFG_BRIGHTNESS; - - tsc2000_write(0, 0xb, br & 0xff); -} -#endif diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c deleted file mode 100644 index abb3b29..0000000 --- a/board/trab/trab_fkt.c +++ /dev/null @@ -1,1411 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define DEBUG - -#include -#include -#include -#include "tsc2000.h" -#include "rs485.h" - -/* - * define, to wait for the touch to be pressed, before reading coordinates in - * command do_touch. If not defined, an error message is printed, when the - * command do_touch is invoked and the touch is not pressed within an specific - * interval. - */ -#undef CONFIG_TOUCH_WAIT_PRESSED - -/* max time to wait for touch is pressed */ -#ifndef CONFIG_TOUCH_WAIT_PRESSED -#define TOUCH_TIMEOUT 5 -#endif /* !CONFIG_TOUCH_WAIT_PRESSED */ - -/* assignment of CPU internal ADC channels with TRAB hardware */ -#define VCC5V 2 -#define VCC12V 3 - -/* CPLD-Register for controlling TRAB hardware functions */ -#define CPLD_BUTTONS ((volatile unsigned long *)0x04020000) -#define CPLD_FILL_LEVEL ((volatile unsigned long *)0x04008000) -#define CPLD_ROTARY_SWITCH ((volatile unsigned long *)0x04018000) -#define CPLD_RS485_RE ((volatile unsigned long *)0x04028000) - -/* timer configuration bits for buzzer and PWM */ -#define START2 (1 << 12) -#define UPDATE2 (1 << 13) -#define INVERT2 (1 << 14) -#define RELOAD2 (1 << 15) -#define START3 (1 << 16) -#define UPDATE3 (1 << 17) -#define INVERT3 (1 << 18) -#define RELOAD3 (1 << 19) - -#define PCLK 66000000 -#define BUZZER_FREQ 1000 /* frequency in Hz */ -#define PWM_FREQ 500 - - -/* definitions of I2C EEPROM device address */ -#define I2C_EEPROM_DEV_ADDR 0x54 - -/* definition for touch panel calibration points */ -#define CALIB_TL 0 /* calibration point in (T)op (L)eft corner */ -#define CALIB_DR 1 /* calibration point in (D)own (R)ight corner */ - -/* EEPROM address map */ -#define SERIAL_NUMBER 8 -#define TOUCH_X0 52 -#define TOUCH_Y0 54 -#define TOUCH_X1 56 -#define TOUCH_Y1 58 -#define CRC16 60 - -/* EEPROM stuff */ -#define EEPROM_MAX_CRC_BUF 64 - -/* RS485 stuff */ -#define RS485_MAX_RECEIVE_BUF_LEN 100 - -/* Bit definitions for ADCCON */ -#define ADC_ENABLE_START 0x1 -#define ADC_READ_START 0x2 -#define ADC_STDBM 0x4 -#define ADC_INP_AIN0 (0x0 << 3) -#define ADC_INP_AIN1 (0x1 << 3) -#define ADC_INP_AIN2 (0x2 << 3) -#define ADC_INP_AIN3 (0x3 << 3) -#define ADC_INP_AIN4 (0x4 << 3) -#define ADC_INP_AIN5 (0x5 << 3) -#define ADC_INP_AIN6 (0x6 << 3) -#define ADC_INP_AIN7 (0x7 << 3) -#define ADC_PRSCEN 0x4000 -#define ADC_ECFLG 0x8000 - -/* function test functions */ -int do_dip (void); -int do_info (void); -int do_vcc5v (void); -int do_vcc12v (void); -int do_buttons (void); -int do_fill_level (void); -int do_rotary_switch (void); -int do_pressure (void); -int do_v_bat (void); -int do_vfd_id (void); -int do_buzzer (char **); -int do_led (char **); -int do_full_bridge (char **); -int do_dac (char **); -int do_motor_contact (void); -int do_motor (char **); -int do_pwm (char **); -int do_thermo (char **); -int do_touch (char **); -int do_rs485 (char **); -int do_serial_number (char **); -int do_crc16 (void); -int do_power_switch (void); -int do_gain (char **); -int do_eeprom (char **); - -/* helper functions */ -static void adc_init (void); -static int adc_read (unsigned int channel); -static void print_identifier (void); - -#ifdef CONFIG_TOUCH_WAIT_PRESSED -static void touch_wait_pressed (void); -#else -static int touch_check_pressed (void); -#endif /* CONFIG_TOUCH_WAIT_PRESSED */ - -static void touch_read_x_y (int *x, int *y); -static int touch_write_clibration_values (int calib_point, int x, int y); -static int rs485_send_line (const char *data); -static int rs485_receive_chars (char *data, int timeout); -static unsigned short updcrc(unsigned short icrc, unsigned char *icp, - unsigned int icnt); - -#if (CONFIG_COMMANDS & CFG_CMD_I2C) -static int trab_eeprom_read (char **argv); -static int trab_eeprom_write (char **argv); -int i2c_write_multiple (uchar chip, uint addr, int alen, uchar *buffer, - int len); -int i2c_read_multiple ( uchar chip, uint addr, int alen, uchar *buffer, - int len); -#endif /* CFG_CMD_I2C */ - -/* - * TRAB board specific commands. Especially commands for burn-in and function - * test. - */ - -int trab_fkt (int argc, char *argv[]) -{ - int i; - - app_startup(argv); - if (get_version () != XF_VERSION) { - printf ("Wrong XF_VERSION. Please re-compile with actual " - "u-boot sources\n"); - printf ("Example expects ABI version %d\n", XF_VERSION); - printf ("Actual U-Boot ABI version %d\n", (int)get_version()); - return 1; - } - - debug ("argc = %d\n", argc); - - for (i=0; i<=argc; ++i) { - debug ("argv[%d] = \"%s\"\n", i, argv[i] ? argv[i] : ""); - } - - adc_init (); - - switch (argc) { - - case 0: - case 1: - break; - - case 2: - if (strcmp (argv[1], "info") == 0) { - return (do_info ()); - } - if (strcmp (argv[1], "dip") == 0) { - return (do_dip ()); - } - if (strcmp (argv[1], "vcc5v") == 0) { - return (do_vcc5v ()); - } - if (strcmp (argv[1], "vcc12v") == 0) { - return (do_vcc12v ()); - } - if (strcmp (argv[1], "buttons") == 0) { - return (do_buttons ()); - } - if (strcmp (argv[1], "fill_level") == 0) { - return (do_fill_level ()); - } - if (strcmp (argv[1], "rotary_switch") == 0) { - return (do_rotary_switch ()); - } - if (strcmp (argv[1], "pressure") == 0) { - return (do_pressure ()); - } - if (strcmp (argv[1], "v_bat") == 0) { - return (do_v_bat ()); - } - if (strcmp (argv[1], "vfd_id") == 0) { - return (do_vfd_id ()); - } - if (strcmp (argv[1], "motor_contact") == 0) { - return (do_motor_contact ()); - } - if (strcmp (argv[1], "crc16") == 0) { - return (do_crc16 ()); - } - if (strcmp (argv[1], "power_switch") == 0) { - return (do_power_switch ()); - } - break; - - case 3: - if (strcmp (argv[1], "full_bridge") == 0) { - return (do_full_bridge (argv)); - } - if (strcmp (argv[1], "dac") == 0) { - return (do_dac (argv)); - } - if (strcmp (argv[1], "motor") == 0) { - return (do_motor (argv)); - } - if (strcmp (argv[1], "pwm") == 0) { - return (do_pwm (argv)); - } - if (strcmp (argv[1], "thermo") == 0) { - return (do_thermo (argv)); - } - if (strcmp (argv[1], "touch") == 0) { - return (do_touch (argv)); - } - if (strcmp (argv[1], "serial_number") == 0) { - return (do_serial_number (argv)); - } - if (strcmp (argv[1], "buzzer") == 0) { - return (do_buzzer (argv)); - } - if (strcmp (argv[1], "gain") == 0) { - return (do_gain (argv)); - } - break; - - case 4: - if (strcmp (argv[1], "led") == 0) { - return (do_led (argv)); - } - if (strcmp (argv[1], "rs485") == 0) { - return (do_rs485 (argv)); - } - if (strcmp (argv[1], "serial_number") == 0) { - return (do_serial_number (argv)); - } - break; - - case 5: - if (strcmp (argv[1], "eeprom") == 0) { - return (do_eeprom (argv)); - } - break; - - case 6: - if (strcmp (argv[1], "eeprom") == 0) { - return (do_eeprom (argv)); - } - break; - - default: - break; - } - - printf ("Usage:\n ...\n"); - return 1; -} - -int do_info (void) -{ - printf ("Stand-alone application for TRAB board function test\n"); - printf ("Built: %s at %s\n", __DATE__ , __TIME__ ); - - return 0; -} - -int do_dip (void) -{ - unsigned int result = 0; - int adc_val; - int i; - - /*********************************************************** - DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3): - SW1 - AIN4 - SW2 - AIN5 - SW3 - AIN6 - SW4 - AIN7 - - "On" DIP switch position short-circuits the voltage from - the input channel (i.e. '0' conversion result means "on"). - *************************************************************/ - - for (i = 7; i > 3; i--) { - - if ((adc_val = adc_read (i)) == -1) { - printf ("Channel %d could not be read\n", i); - return 1; - } - - /* - * Input voltage (switch open) is 1.8 V. - * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736 - * Set trigger at halve that value. - */ - if (adc_val < 368) - result |= (1 << (i-4)); - } - - /* print result to console */ - print_identifier (); - for (i = 0; i < 4; i++) { - if ((result & (1 << i)) == 0) - printf("0"); - else - printf("1"); - } - printf("\n"); - - return 0; -} - - -int do_vcc5v (void) -{ - int result; - - /* VCC5V is connected to channel 2 */ - - if ((result = adc_read (VCC5V)) == -1) { - printf ("VCC5V could not be read\n"); - return 1; - } - - /* - * Calculate voltage value. Split in two parts because there is no - * floating point support. VCC5V is connected over an resistor divider: - * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K. - */ - print_identifier (); - printf ("%d", (result & 0x3FF)* 10 / 1023); - printf (".%d", ((result & 0x3FF)* 10 % 1023)* 10 / 1023); - printf ("%d V\n", (((result & 0x3FF) * 10 % 1023 ) * 10 % 1023) - * 10 / 1024); - - return 0; -} - - -int do_vcc12v (void) -{ - int result; - - if ((result = adc_read (VCC12V)) == -1) { - printf ("VCC12V could not be read\n"); - return 1; - } - - /* - * Calculate voltage value. Split in two parts because there is no - * floating point support. VCC5V is connected over an resistor divider: - * VCC12V=ADCval*2,5V/1023*(30K+270K)/30K. - */ - print_identifier (); - printf ("%d", (result & 0x3FF)* 25 / 1023); - printf (".%d V\n", ((result & 0x3FF)* 25 % 1023) * 10 / 1023); - - return 0; -} - -static int adc_read (unsigned int channel) -{ - int j = 1000; /* timeout value for wait loop in us */ - int result; - S3C2400_ADC *padc; - - padc = S3C2400_GetBase_ADC(); - channel &= 0x7; - - padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ - padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ - padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); - - while (j--) { - if ((padc->ADCCON & ADC_ENABLE_START) == 0) - break; - udelay (1); - } - - if (j == 0) { - printf("%s: ADC timeout\n", __FUNCTION__); - padc->ADCCON |= ADC_STDBM; /* select standby mode */ - return -1; - } - - result = padc->ADCDAT & 0x3FF; - - padc->ADCCON |= ADC_STDBM; /* select standby mode */ - - debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->ADCCON >> 3) & 0x7, result); - - /* - * Wait for ADC to be ready for next conversion. This delay value was - * estimated, because the datasheet does not specify a value. - */ - udelay (1000); - - return (result); -} - - -static void adc_init (void) -{ - S3C2400_ADC *padc; - - padc = S3C2400_GetBase_ADC(); - - padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ - padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ - - /* - * Wait some time to avoid problem with very first call of - * adc_read(). Without * this delay, sometimes the first read adc - * value is 0. Perhaps because the * adjustment of prescaler takes - * some clock cycles? - */ - udelay (1000); - - return; -} - - -int do_buttons (void) -{ - int result; - int i; - - result = *CPLD_BUTTONS; /* read CPLD */ - debug ("%s: cpld_taster (32 bit) %#x\n", __FUNCTION__, result); - - /* print result to console */ - print_identifier (); - for (i = 16; i <= 19; i++) { - if ((result & (1 << i)) == 0) - printf("0"); - else - printf("1"); - } - printf("\n"); - return 0; -} - - -int do_power_switch (void) -{ - int result; - - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* configure GPE7 as input */ - gpio->PECON &= ~(0x3 << (2 * 7)); - - /* signal GPE7 from power switch is low active: 0=on , 1=off */ - result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1; - - print_identifier (); - printf("%d\n", result); - return 0; -} - - -int do_fill_level (void) -{ - int result; - - result = *CPLD_FILL_LEVEL; /* read CPLD */ - debug ("%s: cpld_fuellstand (32 bit) %#x\n", __FUNCTION__, result); - - /* print result to console */ - print_identifier (); - if ((result & (1 << 16)) == 0) - printf("0\n"); - else - printf("1\n"); - return 0; -} - - -int do_rotary_switch (void) -{ - int result; - /* - * Please note, that the default values of the direction bits are - * undefined after reset. So it is a good idea, to make first a dummy - * call to this function, to clear the direction bits and set so to - * proper values. - */ - - result = *CPLD_ROTARY_SWITCH; /* read CPLD */ - debug ("%s: cpld_inc (32 bit) %#x\n", __FUNCTION__, result); - - *CPLD_ROTARY_SWITCH |= (3 << 16); /* clear direction bits in CPLD */ - - /* print result to console */ - print_identifier (); - if ((result & (1 << 16)) == (1 << 16)) - printf("R"); - if ((result & (1 << 17)) == (1 << 17)) - printf("L"); - if (((result & (1 << 16)) == 0) && ((result & (1 << 17)) == 0)) - printf("0"); - if ((result & (1 << 18)) == 0) - printf("0\n"); - else - printf("1\n"); - return 0; -} - - -int do_vfd_id (void) -{ - int i; - long int pcup_old, pccon_old; - int vfd_board_id; - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* try to red vfd board id from the value defined by pull-ups */ - - pcup_old = gpio->PCUP; - pccon_old = gpio->PCCON; - - gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pull-ups */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as - * inputs */ - udelay (10); /* allow signals to settle */ - vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */ - - gpio->PCCON = pccon_old; - gpio->PCUP = pcup_old; - - /* print vfd_board_id to console */ - print_identifier (); - for (i = 0; i < 4; i++) { - if ((vfd_board_id & (1 << i)) == 0) - printf("0"); - else - printf("1"); - } - printf("\n"); - return 0; -} - -int do_buzzer (char **argv) -{ - int counter; - - S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* set prescaler for timer 2, 3 and 4 */ - timers->TCFG0 &= ~0xFF00; - timers->TCFG0 |= 0x0F00; - - /* set divider for timer 2 */ - timers->TCFG1 &= ~0xF00; - timers->TCFG1 |= 0x300; - - /* set frequency */ - counter = (PCLK / BUZZER_FREQ) >> 9; - timers->ch[2].TCNTB = counter; - timers->ch[2].TCMPB = counter / 2; - - if (strcmp (argv[2], "on") == 0) { - debug ("%s: frequency: %d\n", __FUNCTION__, - BUZZER_FREQ); - - /* configure pin GPD7 as TOUT2 */ - gpio->PDCON &= ~0xC000; - gpio->PDCON |= 0x8000; - - /* start */ - timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) & - ~INVERT2; - timers->TCON = (timers->TCON | START2) & ~UPDATE2; - return (0); - } - else if (strcmp (argv[2], "off") == 0) { - /* stop */ - timers->TCON &= ~(START2 | RELOAD2); - - /* configure GPD7 as output and set to low */ - gpio->PDCON &= ~0xC000; - gpio->PDCON |= 0x4000; - gpio->PDDAT &= ~0x80; - return (0); - } - - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; -} - - -int do_led (char **argv) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* configure PC14 and PC15 as output */ - gpio->PCCON &= ~(0xF << 28); - gpio->PCCON |= (0x5 << 28); - - /* configure PD0 and PD4 as output */ - gpio->PDCON &= ~((0x3 << 8) | 0x3); - gpio->PDCON |= ((0x1 << 8) | 0x1); - - switch (simple_strtoul(argv[2], NULL, 10)) { - - case 0: - case 1: - break; - - case 2: - if (strcmp (argv[3], "on") == 0) - gpio->PCDAT |= (1 << 14); - else - gpio->PCDAT &= ~(1 << 14); - return 0; - - case 3: - if (strcmp (argv[3], "on") == 0) - gpio->PCDAT |= (1 << 15); - else - gpio->PCDAT &= ~(1 << 15); - return 0; - - case 4: - if (strcmp (argv[3], "on") == 0) - gpio->PDDAT |= (1 << 0); - else - gpio->PDDAT &= ~(1 << 0); - return 0; - - case 5: - if (strcmp (argv[3], "on") == 0) - gpio->PDDAT |= (1 << 4); - else - gpio->PDDAT &= ~(1 << 4); - return 0; - - default: - break; - - } - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; -} - - -int do_full_bridge (char **argv) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* configure PD5 and PD6 as output */ - gpio->PDCON &= ~((0x3 << 5*2) | (0x3 << 6*2)); - gpio->PDCON |= ((0x1 << 5*2) | (0x1 << 6*2)); - - if (strcmp (argv[2], "+") == 0) { - gpio->PDDAT |= (1 << 5); - gpio->PDDAT |= (1 << 6); - return 0; - } - else if (strcmp (argv[2], "-") == 0) { - gpio->PDDAT &= ~(1 << 5); - gpio->PDDAT |= (1 << 6); - return 0; - } - else if (strcmp (argv[2], "off") == 0) { - gpio->PDDAT &= ~(1 << 5); - gpio->PDDAT &= ~(1 << 6); - return 0; - } - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; -} - -/* val must be in [0, 4095] */ -static inline unsigned long tsc2000_to_uv (u16 val) -{ - return ((250000 * val) / 4096) * 10; -} - - -int do_dac (char **argv) -{ - int brightness; - - /* initialize SPI */ - spi_init (); - - if (((brightness = simple_strtoul (argv[2], NULL, 10)) < 0) || - (brightness > 255)) { - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; - } - tsc2000_write(TSC2000_REG_DACCTL, 0x0); /* Power up DAC */ - tsc2000_write(TSC2000_REG_DAC, brightness & 0xff); - - return 0; -} - - -int do_v_bat (void) -{ - unsigned long ret, res; - - /* initialize SPI */ - spi_init (); - - tsc2000_write(TSC2000_REG_ADC, 0x1836); - - /* now wait for data available */ - adc_wait_conversion_done(); - - ret = tsc2000_read(TSC2000_REG_BAT1); - res = (tsc2000_to_uv(ret) + 1250) / 2500; - res += (ERROR_BATTERY * res) / 1000; - - print_identifier (); - printf ("%ld", (res / 100)); - printf (".%ld", ((res % 100) / 10)); - printf ("%ld V\n", (res % 10)); - return 0; -} - - -int do_pressure (void) -{ - /* initialize SPI */ - spi_init (); - - tsc2000_write(TSC2000_REG_ADC, 0x2436); - - /* now wait for data available */ - adc_wait_conversion_done(); - - print_identifier (); - printf ("%d\n", tsc2000_read(TSC2000_REG_AUX2)); - return 0; -} - - -int do_motor_contact (void) -{ - int result; - - result = *CPLD_FILL_LEVEL; /* read CPLD */ - debug ("%s: cpld_fuellstand (32 bit) %#x\n", __FUNCTION__, result); - - /* print result to console */ - print_identifier (); - if ((result & (1 << 17)) == 0) - printf("0\n"); - else - printf("1\n"); - return 0; -} - -int do_motor (char **argv) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* Configure I/O port */ - gpio->PGCON &= ~(0x3 << 0); - gpio->PGCON |= (0x1 << 0); - - if (strcmp (argv[2], "on") == 0) { - gpio->PGDAT &= ~(1 << 0); - return 0; - } - if (strcmp (argv[2], "off") == 0) { - gpio->PGDAT |= (1 << 0); - return 0; - } - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; -} - -static void print_identifier (void) -{ - printf ("## FKT: "); -} - -int do_pwm (char **argv) -{ - int counter; - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); - - if (strcmp (argv[2], "on") == 0) { - /* configure pin GPD8 as TOUT3 */ - gpio->PDCON &= ~(0x3 << 8*2); - gpio->PDCON |= (0x2 << 8*2); - - /* set prescaler for timer 2, 3 and 4 */ - timers->TCFG0 &= ~0xFF00; - timers->TCFG0 |= 0x0F00; - - /* set divider for timer 3 */ - timers->TCFG1 &= ~(0xf << 12); - timers->TCFG1 |= (0x3 << 12); - - /* set frequency */ - counter = (PCLK / PWM_FREQ) >> 9; - timers->ch[3].TCNTB = counter; - timers->ch[3].TCMPB = counter / 2; - - /* start timer */ - timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; - timers->TCON = (timers->TCON | START3) & ~UPDATE3; - return 0; - } - if (strcmp (argv[2], "off") == 0) { - - /* stop timer */ - timers->TCON &= ~(START2 | RELOAD2); - - /* configure pin GPD8 as output and set to 0 */ - gpio->PDCON &= ~(0x3 << 8*2); - gpio->PDCON |= (0x1 << 8*2); - gpio->PDDAT &= ~(1 << 8); - return 0; - } - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; -} - - -int do_thermo (char **argv) -{ - int channel, res; - - tsc2000_reg_init (); - - if (strcmp (argv[2], "all") == 0) { - int i; - for (i=0; i <= 15; i++) { - res = tsc2000_read_channel(i); - print_identifier (); - printf ("c%d: %d\n", i, res); - } - return 0; - } - channel = simple_strtoul (argv[2], NULL, 10); - res = tsc2000_read_channel(channel); - print_identifier (); - printf ("%d\n", res); - return 0; /* return OK */ -} - - -int do_touch (char **argv) -{ - int x, y; - - if (strcmp (argv[2], "tl") == 0) { -#ifdef CONFIG_TOUCH_WAIT_PRESSED - touch_wait_pressed(); -#else - { - int i; - for (i = 0; i < (TOUCH_TIMEOUT * 1000); i++) { - if (touch_check_pressed ()) { - break; - } - udelay (1000); /* pause 1 ms */ - } - } - if (!touch_check_pressed()) { - print_identifier (); - printf ("error: touch not pressed\n"); - return 1; - } -#endif /* CONFIG_TOUCH_WAIT_PRESSED */ - touch_read_x_y (&x, &y); - - print_identifier (); - printf ("x=%d y=%d\n", x, y); - return touch_write_clibration_values (CALIB_TL, x, y); - } - else if (strcmp (argv[2], "dr") == 0) { -#ifdef CONFIG_TOUCH_WAIT_PRESSED - touch_wait_pressed(); -#else - { - int i; - for (i = 0; i < (TOUCH_TIMEOUT * 1000); i++) { - if (touch_check_pressed ()) { - break; - } - udelay (1000); /* pause 1 ms */ - } - } - if (!touch_check_pressed()) { - print_identifier (); - printf ("error: touch not pressed\n"); - return 1; - } -#endif /* CONFIG_TOUCH_WAIT_PRESSED */ - touch_read_x_y (&x, &y); - - print_identifier (); - printf ("x=%d y=%d\n", x, y); - - return touch_write_clibration_values (CALIB_DR, x, y); - } - return 1; /* not "tl", nor "dr", so return error */ -} - - -#ifdef CONFIG_TOUCH_WAIT_PRESSED -static void touch_wait_pressed (void) -{ - while (!(tsc2000_read(TSC2000_REG_ADC) & TC_PSM)); -} - -#else -static int touch_check_pressed (void) -{ - return (tsc2000_read(TSC2000_REG_ADC) & TC_PSM); -} -#endif /* CONFIG_TOUCH_WAIT_PRESSED */ - -static int touch_write_clibration_values (int calib_point, int x, int y) -{ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) - int x_verify = 0; - int y_verify = 0; - - tsc2000_reg_init (); - - if (calib_point == CALIB_TL) { - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1, - (char *)&x, 2)) { - return 1; - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1, - (char *)&y, 2)) { - return 1; - } - - /* verify written values */ - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1, - (char *)&x_verify, 2)) { - return 1; - } - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1, - (char *)&y_verify, 2)) { - return 1; - } - if ((y != y_verify) || (x != x_verify)) { - print_identifier (); - printf ("error: verify error\n"); - return 1; - } - return 0; /* no error */ - } - else if (calib_point == CALIB_DR) { - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1, - (char *)&x, 2)) { - return 1; - } - if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1, - (char *)&y, 2)) { - return 1; - } - - /* verify written values */ - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1, - (char *)&x_verify, 2)) { - return 1; - } - if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1, - (char *)&y_verify, 2)) { - return 1; - } - if ((y != y_verify) || (x != x_verify)) { - print_identifier (); - printf ("error: verify error\n"); - return 1; - } - return 0; - } - return 1; -#else - printf ("No I2C support enabled (CFG_CMD_I2C), could not write " - "to EEPROM\n"); - return (1); -#endif /* CFG_CMD_I2C */ -} - - -static void touch_read_x_y (int *px, int *py) -{ - tsc2000_write(TSC2000_REG_ADC, DEFAULT_ADC | TC_AD0 | TC_AD1); - adc_wait_conversion_done(); - *px = tsc2000_read(TSC2000_REG_X); - - tsc2000_write(TSC2000_REG_ADC, DEFAULT_ADC | TC_AD2); - adc_wait_conversion_done(); - *py = tsc2000_read(TSC2000_REG_Y); -} - - -int do_rs485 (char **argv) -{ - int timeout; - char data[RS485_MAX_RECEIVE_BUF_LEN]; - - if (strcmp (argv[2], "send") == 0) { - return (rs485_send_line (argv[3])); - } - else if (strcmp (argv[2], "receive") == 0) { - timeout = simple_strtoul(argv[3], NULL, 10); - if (rs485_receive_chars (data, timeout) != 0) { - print_identifier (); - printf ("## nothing received\n"); - return (1); - } - else { - print_identifier (); - printf ("%s\n", data); - return (0); - } - } - printf ("%s: unknown command %s\n", __FUNCTION__, argv[2]); - return (1); /* unknown command, return error */ -} - - -static int rs485_send_line (const char *data) -{ - rs485_init (); - trab_rs485_enable_tx (); - rs485_puts (data); - rs485_putc ('\n'); - - return (0); -} - - -static int rs485_receive_chars (char *data, int timeout) -{ - int i; - int receive_count = 0; - - rs485_init (); - trab_rs485_enable_rx (); - - /* test every 1 ms for received characters to avoid a receive FIFO - * overrun (@ 38.400 Baud) */ - for (i = 0; i < (timeout * 1000); i++) { - while (rs485_tstc ()) { - if (receive_count >= RS485_MAX_RECEIVE_BUF_LEN-1) - break; - *data++ = rs485_getc (); - receive_count++; - } - udelay (1000); /* pause 1 ms */ - } - *data = '\0'; /* terminate string */ - - if (receive_count == 0) - return (1); - else - return (0); -} - - -int do_serial_number (char **argv) -{ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) - unsigned int serial_number; - - if (strcmp (argv[2], "read") == 0) { - if (i2c_read (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1, - (char *)&serial_number, 4)) { - printf ("could not read from eeprom\n"); - return (1); - } - print_identifier (); - printf ("%08d\n", serial_number); - return (0); - } - else if (strcmp (argv[2], "write") == 0) { - serial_number = simple_strtoul(argv[3], NULL, 10); - if (i2c_write (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1, - (char *)&serial_number, 4)) { - printf ("could not write to eeprom\n"); - return (1); - } - return (0); - } - printf ("%s: unknown command %s\n", __FUNCTION__, argv[2]); - return (1); /* unknown command, return error */ -#else - printf ("No I2C support enabled (CFG_CMD_I2C), could not write " - "to EEPROM\n"); - return (1); -#endif /* CFG_CMD_I2C */ -} - - -int do_crc16 (void) -{ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) - int crc; - char buf[EEPROM_MAX_CRC_BUF]; - - if (i2c_read (I2C_EEPROM_DEV_ADDR, 0, 1, buf, 60)) { - printf ("could not read from eeprom\n"); - return (1); - } - crc = 0; /* start value of crc calculation */ - crc = updcrc (crc, buf, 60); - - print_identifier (); - printf ("crc16=%#04x\n", crc); - - if (i2c_write (I2C_EEPROM_DEV_ADDR, CRC16, 1, (char *)&crc, - sizeof (crc))) { - printf ("could not read from eeprom\n"); - return (1); - } - return (0); -#else - printf ("No I2C support enabled (CFG_CMD_I2C), could not write " - "to EEPROM\n"); - return (1); -#endif /* CFG_CMD_I2C */ -} - - -/* - * Calculate, intelligently, the CRC of a dataset incrementally given a - * buffer full at a time. - * Initialize crc to 0 for XMODEM, -1 for CCITT. - * - * Usage: - * newcrc = updcrc( oldcrc, bufadr, buflen ) - * unsigned int oldcrc, buflen; - * char *bufadr; - * - * Compile with -DTEST to generate program that prints CRC of stdin to stdout. - * Compile with -DMAKETAB to print values for crctab to stdout - */ - - /* the CRC polynomial. This is used by XMODEM (almost CCITT). - * If you change P, you must change crctab[]'s initial value to what is - * printed by initcrctab() - */ -#define P 0x1021 - - /* number of bits in CRC: don't change it. */ -#define W 16 - - /* this the number of bits per char: don't change it. */ -#define B 8 - -static unsigned short crctab[1<>(W-B)) ^ *cp++]; - - return (crc); -} - - -int do_gain (char **argv) -{ - int range; - - range = simple_strtoul (argv[2], NULL, 10); - if ((range < 1) || (range > 3)) - { - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return 1; - } - - tsc2000_set_range (range); - return (0); -} - - -int do_eeprom (char **argv) -{ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) - if (strcmp (argv[2], "read") == 0) { - return (trab_eeprom_read (argv)); - } - - else if (strcmp (argv[2], "write") == 0) { - return (trab_eeprom_write (argv)); - } - - printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); - return (1); -#else - printf ("No I2C support enabled (CFG_CMD_I2C), could not write " - "to EEPROM\n"); - return (1); -#endif /* CFG_CMD_I2C */ -} - -#if (CONFIG_COMMANDS & CFG_CMD_I2C) -static int trab_eeprom_read (char **argv) -{ - int i; - int len; - unsigned int addr; - long int value = 0; - uchar *buffer; - - buffer = (uchar *) &value; - addr = simple_strtoul (argv[3], NULL, 10); - addr &= 0xfff; - len = simple_strtoul (argv[4], NULL, 10); - if ((len < 1) || (len > 4)) { - printf ("%s: invalid parameter %s\n", __FUNCTION__, - argv[4]); - return (1); - } - for (i = 0; i < len; i++) { - if (i2c_read (I2C_EEPROM_DEV_ADDR, addr+i, 1, buffer+i, 1)) { - printf ("%s: could not read from i2c device %#x" - ", addr %d\n", __FUNCTION__, - I2C_EEPROM_DEV_ADDR, addr); - return (1); - } - } - print_identifier (); - if (strcmp (argv[5], "-") == 0) { - if (len == 1) - printf ("%d\n", (signed char) value); - else if (len == 2) - printf ("%d\n", (signed short int) value); - else - printf ("%ld\n", value); - } - else { - if (len == 1) - printf ("%d\n", (unsigned char) value); - else if (len == 2) - printf ("%d\n", (unsigned short int) value); - else - printf ("%ld\n", (unsigned long int) value); - } - return (0); -} - -static int trab_eeprom_write (char **argv) -{ - int i; - int len; - unsigned int addr; - long int value = 0; - uchar *buffer; - - buffer = (uchar *) &value; - addr = simple_strtoul (argv[3], NULL, 10); - addr &= 0xfff; - len = simple_strtoul (argv[4], NULL, 10); - if ((len < 1) || (len > 4)) { - printf ("%s: invalid parameter %s\n", __FUNCTION__, - argv[4]); - return (1); - } - value = simple_strtol (argv[5], NULL, 10); - debug ("value=%ld\n", value); - for (i = 0; i < len; i++) { - if (i2c_write (I2C_EEPROM_DEV_ADDR, addr+i, 1, buffer+i, 1)) { - printf ("%s: could not write to i2c device %d" - ", addr %d\n", __FUNCTION__, - I2C_EEPROM_DEV_ADDR, addr); - return (1); - } -#if 0 - printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i=" - "%#x+%d=%p=%#x \n",I2C_EEPROM_DEV_ADDR_DEV_ADDR , addr, - i, addr+i, 1, buffer, i, buffer+i, *(buffer+i)); -#endif - udelay (30000); /* wait for EEPROM ready */ - } - return (0); -} - -int i2c_write_multiple (uchar chip, uint addr, int alen, - uchar *buffer, int len) -{ - int i; - - if (alen != 1) { - printf ("%s: addr len other than 1 not supported\n", - __FUNCTION__); - return (1); - } - - for (i = 0; i < len; i++) { - if (i2c_write (chip, addr+i, alen, buffer+i, 1)) { - printf ("%s: could not write to i2c device %d" - ", addr %d\n", __FUNCTION__, chip, addr); - return (1); - } -#if 0 - printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i=" - "%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i, - alen, buffer, i, buffer+i, buffer+i); -#endif - - udelay (30000); - } - return (0); -} - -int i2c_read_multiple ( uchar chip, uint addr, int alen, - uchar *buffer, int len) -{ - int i; - - if (alen != 1) { - printf ("%s: addr len other than 1 not supported\n", - __FUNCTION__); - return (1); - } - - for (i = 0; i < len; i++) { - if (i2c_read (chip, addr+i, alen, buffer+i, 1)) { - printf ("%s: could not read from i2c device %#x" - ", addr %d\n", __FUNCTION__, chip, addr); - return (1); - } - } - return (0); -} -#endif /* CFG_CMD_I2C */ diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c deleted file mode 100644 index ca68682..0000000 --- a/board/trab/tsc2000.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - * Functions to access the TSC2000 controller on TRAB board (used for scanning - * thermo sensors) - * - * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "tsc2000.h" - -#include "Pt1000_temp_data.h" - -/* helper function */ -#define abs(value) (((value) < 0) ? ((value)*-1) : (value)) - -/* - * Maximal allowed deviation between two immediate meassurments of an analog - * thermo channel. 1 DIGIT = 0.0276 °C. This is used to filter sporadic - * "jumps" in measurment. - */ -#define MAX_DEVIATION 18 /* unit: DIGITs of adc; 18 DIGIT = 0.5 °C */ - -void spi_init(void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); - int i; - - /* Configure I/O ports. */ - gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; - gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; - gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; - gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; - - CLR_CS_TOUCH(); - - spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */ - spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */ - spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0, - CPHA=1 */ - - /* Dummy byte ensures clock to be low. */ - for (i = 0; i < 10; i++) { - spi->ch[0].SPTDAT = 0xFF; - } - spi_wait_transmit_done(); -} - - -void spi_wait_transmit_done(void) -{ - S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); - - while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */ -} - - -void tsc2000_write(unsigned short reg, unsigned short data) -{ - S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); - unsigned int command; - - SET_CS_TOUCH(); - command = reg; - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; - spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); - spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; - spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0x00FF); - spi_wait_transmit_done(); - - CLR_CS_TOUCH(); -} - - -unsigned short tsc2000_read (unsigned short reg) -{ - unsigned short command, data; - S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); - - SET_CS_TOUCH(); - command = 0x8000 | reg; - - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; - spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); - spi_wait_transmit_done(); - - spi->ch[0].SPTDAT = 0xFF; - spi_wait_transmit_done(); - data = spi->ch[0].SPRDAT; - spi->ch[0].SPTDAT = 0xFF; - spi_wait_transmit_done(); - - CLR_CS_TOUCH(); - return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8); -} - - -void tsc2000_set_mux (unsigned int channel) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - CLR_MUX1_ENABLE; CLR_MUX2_ENABLE; - CLR_MUX3_ENABLE; CLR_MUX4_ENABLE; - switch (channel) { - case 0: - CLR_MUX0; CLR_MUX1; - SET_MUX1_ENABLE; - break; - case 1: - SET_MUX0; CLR_MUX1; - SET_MUX1_ENABLE; - break; - case 2: - CLR_MUX0; SET_MUX1; - SET_MUX1_ENABLE; - break; - case 3: - SET_MUX0; SET_MUX1; - SET_MUX1_ENABLE; - break; - case 4: - CLR_MUX0; CLR_MUX1; - SET_MUX2_ENABLE; - break; - case 5: - SET_MUX0; CLR_MUX1; - SET_MUX2_ENABLE; - break; - case 6: - CLR_MUX0; SET_MUX1; - SET_MUX2_ENABLE; - break; - case 7: - SET_MUX0; SET_MUX1; - SET_MUX2_ENABLE; - break; - case 8: - CLR_MUX0; CLR_MUX1; - SET_MUX3_ENABLE; - break; - case 9: - SET_MUX0; CLR_MUX1; - SET_MUX3_ENABLE; - break; - case 10: - CLR_MUX0; SET_MUX1; - SET_MUX3_ENABLE; - break; - case 11: - SET_MUX0; SET_MUX1; - SET_MUX3_ENABLE; - break; - case 12: - CLR_MUX0; CLR_MUX1; - SET_MUX4_ENABLE; - break; - case 13: - SET_MUX0; CLR_MUX1; - SET_MUX4_ENABLE; - break; - case 14: - CLR_MUX0; SET_MUX1; - SET_MUX4_ENABLE; - break; - case 15: - SET_MUX0; SET_MUX1; - SET_MUX4_ENABLE; - break; - default: - CLR_MUX0; CLR_MUX1; - } -} - - -void tsc2000_set_range (unsigned int range) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - switch (range) { - case 1: - CLR_SEL_TEMP_V_0; SET_SEL_TEMP_V_1; - CLR_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3; - break; - case 2: - CLR_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1; - CLR_SEL_TEMP_V_2; SET_SEL_TEMP_V_3; - break; - case 3: - SET_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1; - SET_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3; - break; - } -} - - -u16 tsc2000_read_channel (unsigned int channel) -{ - u16 res; - - tsc2000_set_mux(channel); - udelay(3 * TSC2000_DELAY_BASE); - - tsc2000_write(TSC2000_REG_ADC, 0x2036); - adc_wait_conversion_done (); - res = tsc2000_read(TSC2000_REG_AUX1); - return res; -} - - -s32 tsc2000_contact_temp (void) -{ - long adc_pt1000, offset; - long u_pt1000; - long contact_temp; - long temp1, temp2; - - tsc2000_reg_init (); - tsc2000_set_range (3); - - /* - * Because of sporadic "jumps" in the measured adc values every - * channel is read two times. If there is a significant difference - * between the two measurements, then print an error and do a third - * measurement, because it is very unlikely that a successive third - * measurement goes also wrong. - */ - temp1 = tsc2000_read_channel (14); - temp2 = tsc2000_read_channel (14); - if (abs(temp2 - temp1) < MAX_DEVIATION) - adc_pt1000 = temp2; - else { - printf ("%s: read adc value (channel 14) exceeded max allowed " - "deviation: %d * 0.0276 °C\n", - __FUNCTION__, MAX_DEVIATION); - printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n", - temp1, temp2); - adc_pt1000 = tsc2000_read_channel (14); - printf ("use (third read) adc value: adc_pt1000 = " - "%ld DIGITs\n", adc_pt1000); - } - debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000); - - temp1 = tsc2000_read_channel (15); - temp2 = tsc2000_read_channel (15); - if (abs(temp2 - temp1) < MAX_DEVIATION) - offset = temp2; - else { - printf ("%s: read adc value (channel 15) exceeded max allowed " - "deviation: %d * 0.0276 °C\n", - __FUNCTION__, MAX_DEVIATION); - printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n", - temp1, temp2); - offset = tsc2000_read_channel (15); - printf ("use (third read) adc value: offset = %ld DIGITs\n", - offset); - } - debug ("read channel 15 (offset): %ld\n", offset); - - /* - * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 = - * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3: - * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The - * error correction Values err_vref and err_amp3 are assumed as 0 in - * u-boot, because this could cause only a very small error (< 1%). - */ - u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10; - debug ("u_pt1000: %ld\n", u_pt1000); - - if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table, - &contact_temp) == -1) { - printf ("%s: error interpolating PT1000 vlaue\n", - __FUNCTION__); - return (-1000); - } - debug ("contact_temp: %ld\n", contact_temp); - - return contact_temp; -} - - -void tsc2000_reg_init (void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - tsc2000_write(TSC2000_REG_ADC, 0x2036); - tsc2000_write(TSC2000_REG_REF, 0x0011); - tsc2000_write(TSC2000_REG_DACCTL, 0x0000); - - CON_MUX0; - CON_MUX1; - - CON_MUX1_ENABLE; - CON_MUX2_ENABLE; - CON_MUX3_ENABLE; - CON_MUX4_ENABLE; - - CON_SEL_TEMP_V_0; - CON_SEL_TEMP_V_1; - CON_SEL_TEMP_V_2; - CON_SEL_TEMP_V_3; - - tsc2000_set_mux(0); - tsc2000_set_range(0); -} - - -int tsc2000_interpolate(long value, long data[][2], long *result) -{ - int i; - - /* the data is sorted and the first element is upper - * limit so we can easily check for out-of-band values - */ - if (data[0][0] < value || data[1][0] > value) - return -1; - - i = 1; - while (data[i][0] < value) - i++; - - /* To prevent overflow we have to store the intermediate - result in 'long long'. - */ - - *result = data[i-1][1] + - ((unsigned long long)(data[i][1] - data[i-1][1]) - * (unsigned long long)(value - data[i-1][0])) - / (data[i][0] - data[i-1][0]); - - return 0; -} - - -void adc_wait_conversion_done(void) -{ - while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14))); -} diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h deleted file mode 100644 index aac9c0c..0000000 --- a/board/trab/tsc2000.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Functions to access the TSC2000 controller on TRAB board (used for scanning - * thermo sensors) - * - * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TSC2000_H_ -#define _TSC2000_H_ - -/* temperature channel multiplexer definitions */ -#define CON_MUX0 (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100) -#define CLR_MUX0 (gpio->PCDAT &= 0x0FFEF) -#define SET_MUX0 (gpio->PCDAT |= 0x00010) - -#define CON_MUX1 (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400) -#define CLR_MUX1 (gpio->PCDAT &= 0x0FFDF) -#define SET_MUX1 (gpio->PCDAT |= 0x00020) - -#define CON_MUX1_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000) -#define CLR_MUX1_ENABLE (gpio->PCDAT |= 0x00040) -#define SET_MUX1_ENABLE (gpio->PCDAT &= 0x0FFBF) - -#define CON_MUX2_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000) -#define CLR_MUX2_ENABLE (gpio->PCDAT |= 0x00080) -#define SET_MUX2_ENABLE (gpio->PCDAT &= 0x0FF7F) - -#define CON_MUX3_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000) -#define CLR_MUX3_ENABLE (gpio->PCDAT |= 0x00100) -#define SET_MUX3_ENABLE (gpio->PCDAT &= 0x0FEFF) - -#define CON_MUX4_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000) -#define CLR_MUX4_ENABLE (gpio->PCDAT |= 0x00200) -#define SET_MUX4_ENABLE (gpio->PCDAT &= 0x0FDFF) - -#define CON_SEL_TEMP_V_0 (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000) -#define CLR_SEL_TEMP_V_0 (gpio->PCDAT &= 0x0FBFF) -#define SET_SEL_TEMP_V_0 (gpio->PCDAT |= 0x00400) - -#define CON_SEL_TEMP_V_1 (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000) -#define CLR_SEL_TEMP_V_1 (gpio->PCDAT &= 0x0F7FF) -#define SET_SEL_TEMP_V_1 (gpio->PCDAT |= 0x00800) - -#define CON_SEL_TEMP_V_2 (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000) -#define CLR_SEL_TEMP_V_2 (gpio->PCDAT &= 0x0EFFF) -#define SET_SEL_TEMP_V_2 (gpio->PCDAT |= 0x01000) - -#define CON_SEL_TEMP_V_3 (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000) -#define CLR_SEL_TEMP_V_3 (gpio->PCDAT &= 0x0DFFF) -#define SET_SEL_TEMP_V_3 (gpio->PCDAT |= 0x02000) - -/* TSC2000 register definition */ -#define TSC2000_REG_X ((0 << 11) | (0 << 5)) -#define TSC2000_REG_Y ((0 << 11) | (1 << 5)) -#define TSC2000_REG_Z1 ((0 << 11) | (2 << 5)) -#define TSC2000_REG_Z2 ((0 << 11) | (3 << 5)) -#define TSC2000_REG_BAT1 ((0 << 11) | (5 << 5)) -#define TSC2000_REG_BAT2 ((0 << 11) | (6 << 5)) -#define TSC2000_REG_AUX1 ((0 << 11) | (7 << 5)) -#define TSC2000_REG_AUX2 ((0 << 11) | (8 << 5)) -#define TSC2000_REG_TEMP1 ((0 << 11) | (9 << 5)) -#define TSC2000_REG_TEMP2 ((0 << 11) | (0xA << 5)) -#define TSC2000_REG_DAC ((0 << 11) | (0xB << 5)) -#define TSC2000_REG_ZERO ((0 << 11) | (0x10 << 5)) -#define TSC2000_REG_ADC ((1 << 11) | (0 << 5)) -#define TSC2000_REG_DACCTL ((1 << 11) | (2 << 5)) -#define TSC2000_REG_REF ((1 << 11) | (3 << 5)) -#define TSC2000_REG_RESET ((1 << 11) | (4 << 5)) -#define TSC2000_REG_CONFIG ((1 << 11) | (5 << 5)) - -/* bit definition of TSC2000 ADC register */ -#define TC_PSM (1 << 15) -#define TC_STS (1 << 14) -#define TC_AD3 (1 << 13) -#define TC_AD2 (1 << 12) -#define TC_AD1 (1 << 11) -#define TC_AD0 (1 << 10) -#define TC_RS1 (1 << 9) -#define TC_RS0 (1 << 8) -#define TC_AV1 (1 << 7) -#define TC_AV0 (1 << 6) -#define TC_CL1 (1 << 5) -#define TC_CL0 (1 << 4) -#define TC_PV2 (1 << 3) -#define TC_PV1 (1 << 2) -#define TC_PV0 (1 << 1) - -/* default value for TSC2000 ADC register for use with touch functions */ -#define DEFAULT_ADC (TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0) - -#define TSC2000_DELAY_BASE 500 -#define TSC2000_NO_SENSOR -0x10000 - -#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on - * TRAB */ - -void tsc2000_write(unsigned short, unsigned short); -unsigned short tsc2000_read (unsigned short); -u16 tsc2000_read_channel (unsigned int); -void tsc2000_set_mux (unsigned int); -void tsc2000_set_range (unsigned int); -void tsc2000_reg_init (void); -s32 tsc2000_contact_temp (void); -void spi_wait_transmit_done (void); -void spi_init(void); -int tsc2000_interpolate(long value, long data[][2], long *result); -void adc_wait_conversion_done(void); - - -static inline void SET_CS_TOUCH(void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - gpio->PDDAT &= 0x5FF; -} - - -static inline void CLR_CS_TOUCH(void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - gpio->PDDAT |= 0x200; -} - -#endif /* _TSC2000_H_ */ diff --git a/board/trab/u-boot.lds b/board/trab/u-boot.lds deleted file mode 100644 index e56cdd3..0000000 --- a/board/trab/u-boot.lds +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm920t/start.o (.text) - lib_arm/_umodsi3.o (.text) - lib_generic/zlib.o (.text) - lib_generic/crc32.o (.text) - lib_generic/string.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) - - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/trab/vfd.c b/board/trab/vfd.c deleted file mode 100644 index f510ee5..0000000 --- a/board/trab/vfd.c +++ /dev/null @@ -1,571 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering -- wd@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************/ -/* ** DEBUG SETTINGS */ -/************************************************************************/ - -/* #define DEBUG */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_VFD - -/************************************************************************/ -/* ** CONFIG STUFF -- should be moved to board config file */ -/************************************************************************/ - -/************************************************************************/ - -#ifndef PAGE_SIZE -#define PAGE_SIZE 4096 -#endif - -#define ROT 0x09 -#define BLAU 0x0C -#define VIOLETT 0X0D - -/* MAGIC */ -#define FRAME_BUF_SIZE ((256*4*56)/8) -#define frame_buf_offs 4 - -/* defines for starting Timer3 as CPLD-Clk */ -#define START3 (1 << 16) -#define UPDATE3 (1 << 17) -#define INVERT3 (1 << 18) -#define RELOAD3 (1 << 19) - -/* CPLD-Register for controlling vfd-blank-signal */ -#define VFD_DISABLE (*(volatile uchar *)0x04038000=0x0000) -#define VFD_ENABLE (*(volatile uchar *)0x04038000=0x0001) - -/* Supported VFD Types */ -#define VFD_TYPE_T119C 1 /* Noritake T119C VFD */ -#define VFD_TYPE_MN11236 2 - -/*#define NEW_CPLD_CLK*/ - -int vfd_board_id; - -/* taken from armboot/common/vfd.c */ -unsigned long adr_vfd_table[112][18][2][4][2]; -unsigned char bit_vfd_table[112][18][2][4][2]; - -/* - * initialize the values for the VFD-grid-control in the framebuffer - */ -void init_grid_ctrl(void) -{ - DECLARE_GLOBAL_DATA_PTR; - ulong adr, grid_cycle; - unsigned int bit, display; - unsigned char temp, bit_nr; - - /* - * clear frame buffer (logical clear => set to "black") - */ - memset ((void *)(gd->fb_base), 0, FRAME_BUF_SIZE); - - switch (gd->vfd_type) { - case VFD_TYPE_T119C: - for (display=0; display<4; display++) { - for(grid_cycle=0; grid_cycle<56; grid_cycle++) { - bit = grid_cycle * 256 * 4 + - (grid_cycle + 200) * 4 + - frame_buf_offs + display; - /* wrap arround if offset (see manual S3C2400) */ - if (bit>=FRAME_BUF_SIZE*8) - bit = bit - (FRAME_BUF_SIZE * 8); - adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8); - bit_nr = bit % 8; - bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4; - temp=(*(volatile unsigned char*)(adr)); - temp |= (1<=FRAME_BUF_SIZE*8) - bit = bit-(FRAME_BUF_SIZE*8); - adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8); - bit_nr = bit%8; - bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; - temp=(*(volatile unsigned char*)(adr)); - temp |= (1<=FRAME_BUF_SIZE*8) - bit = bit - (FRAME_BUF_SIZE * 8); - adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8); - bit_nr = bit % 8; - bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4; - temp=(*(volatile unsigned char*)(adr)); - temp |= (1<=FRAME_BUF_SIZE*8) - bit = bit-(FRAME_BUF_SIZE*8); - adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8); - bit_nr = bit%8; - bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; - temp=(*(volatile unsigned char*)(adr)); - temp |= (1<vfd_type) { - case VFD_TYPE_T119C: - for(y=0; y<=17; y++) { /* Line */ - for(x=0; x<=111; x++) { /* Column */ - for(display=0; display <=3; display++) { - - /* Display 0 blue pixels */ - vfd_table[x][y][0][display][0] = - (x==0) ? y*16+display - : (x%4)*4+y*16+((x-1)/2)*1024+display; - /* Display 0 red pixels */ - vfd_table[x][y][1][display][0] = - (x==0) ? y*16+512+display - : (x%4)*4+y*16+((x-1)/2)*1024+512+display; - } - } - } - break; - case VFD_TYPE_MN11236: - for(y=0; y<=17; y++) { /* Line */ - for(x=0; x<=111; x++) { /* Column */ - for(display=0; display <=3; display++) { - - vfd_table[x][y][0][display][0]=0; - vfd_table[x][y][0][display][1]=0; - vfd_table[x][y][1][display][0]=0; - vfd_table[x][y][1][display][1]=0; - - switch (x%6) { - case 0: x_abcdef=0; break; /* a -> a */ - case 1: x_abcdef=2; break; /* b -> c */ - case 2: x_abcdef=4; break; /* c -> e */ - case 3: x_abcdef=5; break; /* d -> f */ - case 4: x_abcdef=3; break; /* e -> d */ - case 5: x_abcdef=1; break; /* f -> b */ - } - - /* blue pixels */ - vfd_table[x][y][0][display][0] = - (x>1) ? x_abcdef*4+((x-1)/3)*1024+y*48+display - : x_abcdef*4+ 0+y*48+display; - /* blue pixels */ - if (x>1 && (x-1)%3) - vfd_table[x][y][0][display][1] = x_abcdef*4+((x-1)/3+1)*1024+y*48+display; - - /* red pixels */ - vfd_table[x][y][1][display][0] = - (x>1) ? x_abcdef*4+24+((x-1)/3)*1024+y*48+display - : x_abcdef*4+24+ 0+y*48+display; - /* red pixels */ - if (x>1 && (x-1)%3) - vfd_table[x][y][1][display][1] = x_abcdef*4+24+((x-1)/3+1)*1024+y*48+display; - } - } - } - break; - default: - /* do nothing */ - return; - } - - /* - * Create table with entries for physical byte adresses and - * bit-number within the byte - * from table with bit-numbers within the total framebuffer - */ - for(y=0;y<18;y++) { - for(x=0;x<112;x++) { - for(color=0;color<2;color++) { - for(display=0;display<4;display++) { - for(entry=0;entry<2;entry++) { - unsigned long adr = gd->fb_base; - unsigned int bit_nr = 0; - - if (vfd_table[x][y][color][display][entry]) { - - pixel = vfd_table[x][y][color][display][entry] + frame_buf_offs; - /* - * wrap arround if offset - * (see manual S3C2400) - */ - if (pixel>=FRAME_BUF_SIZE*8) - pixel = pixel-(FRAME_BUF_SIZE*8); - adr = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8); - bit_nr = pixel%8; - bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; - } - adr_vfd_table[x][y][color][display][entry] = adr; - bit_vfd_table[x][y][color][display][entry] = bit_nr; - } - } - } - } - } -} - -/* - * Set/clear pixel of the VFDs - */ -void set_vfd_pixel(unsigned char x, unsigned char y, - unsigned char color, unsigned char display, - unsigned char value) -{ - DECLARE_GLOBAL_DATA_PTR; - ulong adr; - unsigned char bit_nr, temp; - - if (! gd->vfd_type) { - /* Unknown type. */ - return; - } - - /* Pixel-Eintrag Nr. 1 */ - adr = adr_vfd_table[x][y][color][display][0]; - /* Pixel-Eintrag Nr. 1 */ - bit_nr = bit_vfd_table[x][y][color][display][0]; - temp=(*(volatile unsigned char*)(adr)); - - if (value) - temp |= (1< 0; height -= 18) - { - if (height > 18) - y = 18; - else - y = height; - for (; y > 0; y--) - { - for (x = 0; x < width; x += 2) - { - temp = *adr++; - set_vfd_pixel(x, y-1, 0, display, 0); - set_vfd_pixel(x, y-1, 1, display, 0); - if ((temp >> 4) == BLAU) - set_vfd_pixel(x, y-1, 0, display, 1); - else if ((temp >> 4) == ROT) - set_vfd_pixel(x, y-1, 1, display, 1); - else if ((temp >> 4) == VIOLETT) - { - set_vfd_pixel(x, y-1, 0, display, 1); - set_vfd_pixel(x, y-1, 1, display, 1); - } - set_vfd_pixel(x+1, y-1, 0, display, 0); - set_vfd_pixel(x+1, y-1, 1, display, 0); - if ((temp & 0x0F) == BLAU) - set_vfd_pixel(x+1, y-1, 0, display, 1); - else if ((temp & 0x0F) == ROT) - set_vfd_pixel(x+1, y-1, 1, display, 1); - else if ((temp & 0x0F) == VIOLETT) - { - set_vfd_pixel(x+1, y-1, 0, display, 1); - set_vfd_pixel(x+1, y-1, 1, display, 1); - } - } - } - if (display > 0) - display--; - else - display = 3; - } -} - -/* - * This function initializes VFD clock that is needed for the CPLD that - * manages the keyboard. - */ -int vfd_init_clocks (void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); - S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD(); - - /* try to determine display type from the value - * defined by pull-ups - */ - gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */ - udelay (10); /* allow signals to settle */ - vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */ - - VFD_DISABLE; /* activate blank for the vfd */ - -#define NEW_CPLD_CLK - -#ifdef NEW_CPLD_CLK - if (vfd_board_id) { - /* If new board revision, then use PWM 3 as cpld-clock */ - /* Enable 500 Hz timer for fill level sensor to operate properly */ - /* Configure TOUT3 as functional pin, disable pull-up */ - gpio->PDCON &= ~0x30000; - gpio->PDCON |= 0x20000; - gpio->PDUP |= (1 << 8); - - /* Configure the prescaler */ - timers->TCFG0 &= ~0xff00; - timers->TCFG0 |= 0x0f00; - - /* Select MUX input (divider) for timer3 (1/16) */ - timers->TCFG1 &= ~0xf000; - timers->TCFG1 |= 0x3000; - - /* Enable autoreload and set the counter and compare - * registers to values for the 500 Hz clock - * (for a given prescaler (15) and divider (16)): - * counter = (66000000 / 500) >> 9; - */ - timers->ch[3].TCNTB = 0x101; - timers->ch[3].TCMPB = 0x101 / 2; - - /* Start timer */ - timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; - timers->TCON = (timers->TCON | START3) & ~UPDATE3; - } -#endif - /* If old board revision, then use vm-signal as cpld-clock */ - lcd->LCDCON2 = 0x00FFC000; - lcd->LCDCON3 = 0x0007FF00; - lcd->LCDCON4 = 0x00000000; - lcd->LCDCON5 = 0x00000400; - lcd->LCDCON1 = 0x00000B75; - /* VM (GPD1) is used as clock for the CPLD */ - gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008; - - return 0; -} - -/* - * initialize LCD-Controller of the S3C2400 for using VFDs - * - * VFD detection depends on the board revision: - * starting from Rev. 200 a type code can be read from the data pins, - * driven by some pull-up resistors; all earlier systems must be - * manually configured. The type is set in the "vfd_type" environment - * variable. - */ -int drv_vfd_init(void) -{ - S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD(); - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - char *tmp; - ulong palette; - static int vfd_init_done = 0; - int vfd_inv_data = 0; - - DECLARE_GLOBAL_DATA_PTR; - - if (vfd_init_done != 0) - return (0); - vfd_init_done = 1; - - debug("Detecting Revison of WA4-VFD: ID=0x%X\n", vfd_board_id); - - switch (vfd_board_id) { - case 0: /* board revision < Rev.200 */ - if ((tmp = getenv ("vfd_type")) == NULL) { - break; - } - if (strcmp(tmp, "T119C") == 0) { - gd->vfd_type = VFD_TYPE_T119C; - } else if (strcmp(tmp, "MN11236") == 0) { - gd->vfd_type = VFD_TYPE_MN11236; - } else { - /* cannot use printf for a warning here */ - gd->vfd_type = 0; /* unknown */ - } - - break; - default: /* default to MN11236, data inverted */ - gd->vfd_type = VFD_TYPE_MN11236; - vfd_inv_data = 1; - setenv ("vfd_type", "MN11236"); - } - debug ("VFD type: %s%s\n", - (gd->vfd_type == VFD_TYPE_T119C) ? "T119C" : - (gd->vfd_type == VFD_TYPE_MN11236) ? "MN11236" : - "unknown", - vfd_inv_data ? ", inverted data" : ""); - - gd->fb_base = gd->fb_base; - create_vfd_table(); - init_grid_ctrl(); - - for (palette=0; palette < 16; palette++) - (*(volatile unsigned int*)(PALETTE+(palette*4)))=palette; - for (palette=16; palette < 256; palette++) - (*(volatile unsigned int*)(PALETTE+(palette*4)))=0x00; - - /* - * Hinweis: Der Framebuffer ist um genau ein Nibble verschoben - * Das erste angezeigte Pixel wird aus dem zweiten Nibble geholt - * das letzte angezeigte Pixel wird aus dem ersten Nibble geholt - * (wrap around) - * see manual S3C2400 - */ - /* Stopp LCD-Controller */ - lcd->LCDCON1 = 0x00000000; - /* frame buffer startadr */ - lcd->LCDSADDR1 = gd->fb_base >> 1; - /* frame buffer endadr */ - lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1; - lcd->LCDSADDR3 = ((256/4)); - lcd->LCDCON2 = 0x000DC000; - if(gd->vfd_type == VFD_TYPE_MN11236) - lcd->LCDCON2 = 37 << 14; /* MN11236: 38 lines */ - else - lcd->LCDCON2 = 55 << 14; /* T119C: 56 lines */ - lcd->LCDCON3 = 0x0051000A; - lcd->LCDCON4 = 0x00000001; - if (gd->vfd_type && vfd_inv_data) - lcd->LCDCON5 = 0x000004C0; - else - lcd->LCDCON5 = 0x00000440; - - /* Port pins as LCD output */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00)| 0x000000AA; - gpio->PDCON = (gpio->PDCON & 0xFFFFFF03)| 0x000000A8; - - /* Synchronize VFD enable with LCD controller to avoid flicker */ - lcd->LCDCON1 = 0x00000B75; /* Start LCD-Controller */ - while((lcd->LCDCON5 & 0x180000)!=0x100000); /* Wait for end of VSYNC */ - while((lcd->LCDCON5 & 0x060000)!=0x040000); /* Wait for next HSYNC */ - while((lcd->LCDCON5 & 0x060000)==0x040000); - while((lcd->LCDCON5 & 0x060000)!=0x000000); - if(gd->vfd_type) - VFD_ENABLE; - - debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1); - debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2); - debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3); - - return 0; -} - -/* - * Disable VFD: should be run before resetting the system: - * disable VM, enable pull-up - */ -void disable_vfd (void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - VFD_DISABLE; - gpio->PDCON &= ~0xC; - gpio->PDUP &= ~0x2; -} - -/************************************************************************/ -/* ** ROM capable initialization part - needed to reserve FB memory */ -/************************************************************************/ - -/* - * This is called early in the system initialization to grab memory - * for the VFD controller. - * - * Note that this is running from ROM, so no write access to global data. - */ -ulong vfd_setmem (ulong addr) -{ - ulong size; - - /* Round up to nearest full page */ - size = (FRAME_BUF_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); - - debug ("Reserving %ldk for VFD Framebuffer at: %08lx\n", size>>10, addr); - - return (size); -} - -/* - * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb, - * descriptors and palette areas. - */ -ulong calc_fbsize (void) -{ - return FRAME_BUF_SIZE; -} - -#endif /* CONFIG_VFD */ diff --git a/board/uc100/Makefile b/board/uc100/Makefile deleted file mode 100644 index eb81625..0000000 --- a/board/uc100/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -#OBJS = $(BOARD).o flash.o -OBJS = $(BOARD).o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/uc100/config.mk b/board/uc100/config.mk deleted file mode 100644 index a65a8ba..0000000 --- a/board/uc100/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# UC100 boards -# - -#TEXT_BASE = 0x40000000 -TEXT_BASE = 0x40700000 diff --git a/board/uc100/u-boot.lds b/board/uc100/u-boot.lds deleted file mode 100644 index d7c798e..0000000 --- a/board/uc100/u-boot.lds +++ /dev/null @@ -1,143 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - - common/environment.o (.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/uc100/u-boot.lds.debug b/board/uc100/u-boot.lds.debug deleted file mode 100644 index d9bb868..0000000 --- a/board/uc100/u-boot.lds.debug +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/uc100/uc100.c b/board/uc100/uc100.c deleted file mode 100644 index 4f2cff6..0000000 --- a/board/uc100/uc100.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if 0 -#define DEBUG -#endif - -#include -#include -#include -#include - -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/*********************************************************************/ -/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */ -/*********************************************************************/ -const uint sdram_init_upm_table[] = { - /* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */ - /* NOP - Precharge - AutoRefr - NOP - NOP */ - /* NOP - AutoRefr - NOP */ - /* NOP - NOP - LoadModeR - NOP - Active */ - /* Position of Single Read */ - 0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04, - 0x0ffffc04, 0x0ff5fc04, 0x0ffffc04, - - /* Burst Read. (offset 8 in UPMA RAM) */ - /* Cycle lent for Initialisation WV */ - 0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Single Write. (offset 18 in UPMA RAM) */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Burst Write. (offset 20 in UPMA RAM) */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Refresh (offset 30 in UPMA RAM) */ - 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04, - 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, - - /* Exception. (offset 3c in UPMA RAM) */ - 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, -}; - -/*********************************************************************/ -/* UPMA initilization table. */ -/*********************************************************************/ -const uint sdram_upm_table[] = { - /* single read. (offset 0 in UPMA RAM) */ - 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x05-0x07 new WV */ - - /* Burst Read. (offset 8 in UPMA RAM) */ - 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00, - 0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Single Write. (offset 18 in UPMA RAM) */ - 0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04, - 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Burst Write. (offset 20 in UPMA RAM) */ - 0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00, - 0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Refresh (offset 30 in UPMA RAM) */ - 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04, - 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, - - /* Exception. (offset 3c in UPMA RAM) */ - 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */ -}; - -/*********************************************************************/ -/* UPMB initilization table. */ -/*********************************************************************/ -const uint mpm_upm_table[] = { - /* single read. (offset 0 in upm RAM) */ - 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001, - 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* burst read. (Offset 8 in upm RAM) */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* single write. (Offset 0x18 in upm RAM) */ - 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004, - 0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, - - /* burst write. (Offset 0x20 in upm RAM) */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Refresh cycle, offset 0x30 */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Exception, 0ffset 0x3C */ - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, -}; - - -int board_switch(void) -{ - volatile pcmconf8xx_t *pcmp; - - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - - return ((pcmp->pcmc_pipr >> 24) & 0xf); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming UC100"); - } else { - puts(str); - } - - printf (" (SWITCH=%1X)\n", board_switch()); - - return 0; -} - - -/* - * Initialize SDRAM - */ -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /*---------------------------------------------------------------------*/ - /* Initialize the UPMA/UPMB registers with the appropriate table. */ - /*---------------------------------------------------------------------*/ - upmconfig (UPMA, (uint *) sdram_init_upm_table, - sizeof (sdram_init_upm_table) / sizeof (uint)); - upmconfig (UPMB, (uint *) mpm_upm_table, - sizeof (mpm_upm_table) / sizeof (uint)); - - /*---------------------------------------------------------------------*/ - /* Memory Periodic Timer Prescaler: divide by 16 */ - /*---------------------------------------------------------------------*/ - memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */ - - memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */ - memctl->memc_mbmr = CFG_MBMR_VAL; - - /*---------------------------------------------------------------------*/ - /* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */ - /* for SDRAM */ - /* */ - /* NOTE: The refresh rate in MAMR reg is set according to the lowest */ - /* clock rate (16.67MHz) to allow proper operation for all ADS */ - /* clock frequencies. */ - /*---------------------------------------------------------------------*/ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - - /*-------------------------------------------------------------------*/ - /* Wait at least 200 usec for DRAM to stabilize, this magic number */ - /* obtained from the init code. */ - /*-------------------------------------------------------------------*/ - udelay(200); - - memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08; - - memctl->memc_br1 = CFG_BR1_PRELIM; - memctl->memc_or1 = CFG_OR1_PRELIM; - - /*---------------------------------------------------------------------*/ - /* run MRS command in location 5-8 of UPMB. */ - /*---------------------------------------------------------------------*/ - memctl->memc_mar = 0x88; - /* RUN UPMA on CS1 1-time from UPMA addr 0x05 */ - - memctl->memc_mcr = 0x80002100; - /* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */ - - udelay(200); - - /*---------------------------------------------------------------------*/ - /* Initialisation for normal access WV */ - /*---------------------------------------------------------------------*/ - - /*---------------------------------------------------------------------*/ - /* Initialize the UPMA register with the appropriate table. */ - /*---------------------------------------------------------------------*/ - upmconfig (UPMA, (uint *) sdram_upm_table, - sizeof (sdram_upm_table) / sizeof (uint)); - - /*---------------------------------------------------------------------*/ - /* rerstore MBMR value (4-beat refresh burst.) */ - /*---------------------------------------------------------------------*/ - memctl->memc_mamr = CFG_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */ - - udelay(200); - - return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */ -} - - -int misc_init_r (void) -{ - uchar val; - - /* - * Make sure that RTC has clock output enabled (triggers watchdog!) - */ - val = i2c_reg_read (CFG_I2C_RTC_ADDR, 0x0D); - val |= 0x80; - i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val); - - /* - * Configure PHY to setup LED's correctly and use 100MBit, FD - */ - mii_init(); - - /* disable auto-negotiation, 100mbit, full-duplex */ - fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100); - - /* set LED's to Link, Transmit, Receive */ - fec8xx_miiphy_write(NULL, 0, PHY_FCSCR, 0x4122); - - return 0; -} - - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed (void) -{ - return 0; /* No hotkeys supported */ -} -#endif diff --git a/board/utx8245/Makefile b/board/utx8245/Makefile deleted file mode 100644 index e698afc..0000000 --- a/board/utx8245/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Gregory E. Allen, gallen@arlut.utexas.edu -# Matthew E. Karger, karger@arlut.utexas.edu -# Applied Research Laboratories, The University of Texas at Austin -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -SOBJS = - -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/utx8245/config.mk b/board/utx8245/config.mk deleted file mode 100644 index a33faa7..0000000 --- a/board/utx8245/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Gregory E. Allen, gallen@arlut.utexas.edu -# Matthew E. Karger, karger@arlut.utexas.edu -# Applied Research Laboratories, The University of Texas at Austin -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# UTX8245 boards -# -TEXT_BASE = 0xFFF00000 -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/utx8245/flash.c b/board/utx8245/flash.c deleted file mode 100644 index 3271827..0000000 --- a/board/utx8245/flash.c +++ /dev/null @@ -1,560 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Matthew E. Karger, karger@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -#define FLASH_BANK_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ -#define MAIN_SECT_SIZE 0x10000 -#define SECT_SIZE_32KB 0x8000 -#define SECT_SIZE_8KB 0x2000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -static int write_word (flash_info_t * info, ulong dest, ulong data); -#if 0 -static void write_via_fpu (vu_long * addr, ulong * data); -#endif -static __inline__ unsigned long get_msr (void); -static __inline__ void set_msr (unsigned long msr); - -/*flash command address offsets*/ -#define ADDR0 (0x555) -#define ADDR1 (0xAAA) -#define ADDR3 (0x001) - -#define FLASH_WORD_SIZE unsigned char - -/*---------------------------------------------------------------------*/ -/*#define DEBUG_FLASH 1 */ - -/*---------------------------------------------------------------------*/ - -unsigned long flash_init (void) -{ - int i; /* flash bank counter */ - int j; /* flash device sector counter */ - int k; /* flash size calculation loop counter */ - int N; /* pow(2,N) is flash size, but we don't have */ - ulong total_size = 0, device_size = 1; - unsigned char manuf_id, device_id; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - vu_char *addr = (vu_char *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE); - - addr[0x555] = 0xAA; /* get manuf/device info command */ - addr[0x2AA] = 0x55; /* 3-cycle command */ - addr[0x555] = 0x90; - - manuf_id = addr[0]; /* read back manuf/device info */ - device_id = addr[1]; - - addr[0x55] = 0x98; /* CFI command */ - N = addr[0x27]; /* read back device_size = pow(2,N) */ - - for (k = 0; k < N; k++) /* calculate device_size = pow(2,N) */ - device_size *= 2; - - flash_info[i].size = device_size; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - -#if defined DEBUG_FLASH - printf ("manuf_id = %x, device_id = %x\n", manuf_id, device_id); -#endif - /* find out what kind of flash we are using */ - if ((manuf_id == (uchar) (AMD_MANUFACT)) - && (device_id == AMD_ID_LV033C)) { - flash_info[i].flash_id = - ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | - (FLASH_AM033C & FLASH_TYPEMASK); - - /* set individual sector start addresses */ - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE); - } - } - - else if ((manuf_id == (uchar) (AMD_MANUFACT)) && - (device_id == AMD_ID_LV116DT)) { - flash_info[i].flash_id = - ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | - (FLASH_AM160T & FLASH_TYPEMASK); - - /* set individual sector start addresses */ - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE); - - if (j < (CFG_MAX_FLASH_SECT - 3)) { - flash_info[i].start[j] = - (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE); - } else if (j == (CFG_MAX_FLASH_SECT - 3)) { - flash_info[i].start[j] = - (flash_info[i].start[j - 1] + SECT_SIZE_32KB); - - } else { - flash_info[i].start[j] = - (flash_info[i].start[j - 1] + SECT_SIZE_8KB); - } - } - } - - else { - flash_info[i].flash_id = FLASH_UNKNOWN; - addr[0] = 0xFF; - goto Done; - } - -#if defined DEBUG_FLASH - printf ("flash_id = 0x%08lX\n", flash_info[i].flash_id); -#endif - - addr[0] = 0xFF; - - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - - total_size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) - flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - - Done: - return total_size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if (info->flash_id != FLASH_UNKNOWN) { - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - mfct = "AMD"; - break; - case FLASH_MAN_FUJ: - mfct = "FUJITSU"; - break; - case FLASH_MAN_STM: - mfct = "STM"; - break; - case FLASH_MAN_SST: - mfct = "SST"; - break; - case FLASH_MAN_BM: - mfct = "Bright Microelectonics"; - break; - case FLASH_MAN_INTEL: - mfct = "Intel"; - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM033C: - type = "AM29LV033C (32 Mbit, uniform sector size)"; - break; - case FLASH_AM160T: - type = "AM29LV160T (16 Mbit, top boot sector)"; - break; - case FLASH_AM040: - type = "AM29F040B (512K * 8, uniform sector size)"; - break; - case FLASH_AM400B: - type = "AM29LV400B (4 Mbit, bottom boot sect)"; - break; - case FLASH_AM400T: - type = "AM29LV400T (4 Mbit, top boot sector)"; - break; - case FLASH_AM800B: - type = "AM29LV800B (8 Mbit, bottom boot sect)"; - break; - case FLASH_AM800T: - type = "AM29LV800T (8 Mbit, top boot sector)"; - break; - case FLASH_AM320B: - type = "AM29LV320B (32 Mbit, bottom boot sect)"; - break; - case FLASH_AM320T: - type = "AM29LV320T (32 Mbit, top boot sector)"; - break; - case FLASH_STM800AB: - type = "M29W800AB (8 Mbit, bottom boot sect)"; - break; - case FLASH_SST800A: - type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; - break; - case FLASH_SST160A: - type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; - break; - } - } - - printf ("\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, type, info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) { - unsigned long size; - unsigned int erased; - unsigned long *flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for (flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) && erased; - flash++) - erased = *flash == ~0x0UL; - - printf ("%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", info->protect[i] ? "RO" : " "); - } - - puts ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info-> - start[sect] - - info-> - start[0]) << - sh8b)); - - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - udelay (30000); /* wait 30 ms */ - } else { - addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - - info-> - start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ -#if 0 -static void write_via_fpu (vu_long * addr, ulong * data) -{ - __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); - __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); -} -#endif - -/*----------------------------------------------------------------------- - */ -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - return msr; -} - -static __inline__ void set_msr (unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); -} diff --git a/board/utx8245/u-boot.lds b/board/utx8245/u-boot.lds deleted file mode 100644 index 45f3018..0000000 --- a/board/utx8245/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Matthew E. Karger, karger@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc824x/start.o (.text) - lib_ppc/board.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) - - *(.text) - - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - _end = . ; - PROVIDE (end = .); -} diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c deleted file mode 100644 index 834fd84..0000000 --- a/board/utx8245/utx8245.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2001 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Matthew E. Karger, karger@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#define SAVE_SZ 32 - - -int checkboard(void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; -} - - -long int initdram(int board_type) -{ - long size; - long new_bank0_end; - long new_bank1_end; - long mear1; - long emear1; - - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); - - new_bank0_end = size/2 - 1; - new_bank1_end = size - 1; - mear1 = mpc824x_mpc107_getreg(MEAR1); - emear1 = mpc824x_mpc107_getreg(EMEAR1); - - mear1 = (mear1 & 0xFFFF0000) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - ((new_bank1_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT << 8); - emear1 = (emear1 & 0xFFFF0000) | - ((new_bank0_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - ((new_bank1_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT << 8); - - mpc824x_mpc107_setreg(MEAR1, mear1); - mpc824x_mpc107_setreg(EMEAR1, emear1); - - return (size); -} - - -/* - * Initialize PCI Devices, report devices found. - */ - -static struct pci_config_table pci_utx8245_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR, - PCI_FIREWIRE_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, -#endif /*CONFIG_PCI_PNP*/ - { } -}; - - -static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - if (PCI_DEV(dev) == 11) - /* assign serial interrupt line 9 (int25) to FireWire */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25); - - else if (PCI_DEV(dev) == 12) - /* assign serial interrupt line 8 (int24) to Ethernet */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24); - - else if (PCI_DEV(dev) == 14) - /* assign serial interrupt line 0 (int16) to PMC slot 0 */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16); - - else if (PCI_DEV(dev) == 15) - /* assign serial interrupt line 1 (int17) to PMC slot 1 */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17); -} - -static struct pci_controller utx8245_hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_utx8245_config_table, - fixup_irq: pci_utx8245_fixup_irq, - write_byte: pci_hose_write_config_byte -#endif /*CONFIG_PCI_PNP*/ -}; - -void pci_init_board (void) -{ - pci_mpc824x_init(&utx8245_hose); - - icache_enable(); -} diff --git a/board/v37/Makefile b/board/v37/Makefile deleted file mode 100644 index 7a17067..0000000 --- a/board/v37/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/v37/config.mk b/board/v37/config.mk deleted file mode 100644 index 50cac97..0000000 --- a/board/v37/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Marel V37 boards -# -TEXT_BASE = 0x40000000 diff --git a/board/v37/flash.c b/board/v37/flash.c deleted file mode 100644 index 6a31972..0000000 --- a/board/v37/flash.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips); -static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id); -static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - short manu, dev_id; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CFG_OR_TIMING_FLASH | (0 - size_b0); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE0 - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_get_id_long((void*)CFG_FLASH_BASE1,&manu,&dev_id); - - size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]); - - flash_get_offsets(CFG_FLASH_BASE1, &flash_info[1],1); - - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (0 - size_b1); - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0+size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips) -{ - int i, addr_shift; - vu_short *addr = (vu_short*)base; - - addr[0x555] = 0x00AA ; - addr[0xAAA] = 0x0055 ; - addr[0x555] = 0x0090 ; - - addr_shift = (two_chips ? 2 : 1 ); - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + (0x00000000<start[1] = base + (0x00002000<start[2] = base + (0x00003000<start[3] = base + (0x00004000<sector_count; i++) { - info->start[i] = base + ((i-3) * (0x00008000<sector_count - 1; - info->start[i--] = base + info->size - (0x00002000<start[i--] = base + info->size - (0x00003000<start[i--] = base + info->size - (0x00004000<= 0; i--) { - info->start[i] = base + i * (0x00008000<sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (vu_short *)(info->start[i]); - info->protect[i] = addr[1<start[0]; - *addr = 0xF0F0; /* reset bank */ -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_TOSH: printf ("TOSHIBA "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id) -{ - vu_short *addr = (vu_short*)ptr; - - addr[0x555] = 0x00AA ; - addr[0xAAA] = 0x0055 ; - addr[0x555] = 0x0090 ; - - *ptr_manuf = addr[0]; - *ptr_dev_id = addr[1]; - - addr[0] = 0xf0f0; /* return to normal */ -} - -static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id) -{ - vu_short *addr = (vu_short*)ptr; - vu_short *addr1, *addr2, *addr3; - - addr1 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); - addr2 = (vu_short*) ( ((int)ptr) + (0x2AAA<<2) ); - addr3 = (vu_short*) ( ((int)ptr) + (0x5555<<2) ); - - *addr1 = 0xAAAA; - *addr2 = 0x5555; - *addr3 = 0x9090; - - *ptr_manuf = addr[0]; - *ptr_dev_id = addr[2]; - - addr[0] = 0xf0f0; /* return to normal */ -} - -static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info) -{ - switch (manu) { - case ((short)AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - case ((short)FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - case ((short)TOSH_MANUFACT): - info->flash_id = FLASH_MAN_TOSH; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - - switch (dev_id) { - case ((short)TOSH_ID_FVT160): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 1 MB */ - - case ((short)TOSH_ID_FVB160): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV400T): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV400B): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case ((short)AMD_ID_LV800T): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case ((short)AMD_ID_LV800B): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /*%%% Size doubled by yooth */ - break; /* => 4 MB */ - - case ((short)AMD_ID_LV160T): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 4 MB */ - - case ((short)AMD_ID_LV160B): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 4 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = (vu_short)0xAAAAAAAA; - addr[0xAAA] = (vu_short)0x55555555; - addr[0x555] = (vu_short)0x80808080; - addr[0x555] = (vu_short)0xAAAAAAAA; - addr[0xAAA] = (vu_short)0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short *)(info->start[sect]) ; - addr[0] = (vu_short)0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_short *)(info->start[l_sect]); - while ((addr[0] & 0x8080) != 0x8080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = (vu_short)0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_short *addr = (vu_short *)(info->start[0]); - vu_short sdata; - - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* First write upper 16 bits */ - sdata = (short)(data>>16); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = 0xAAAA; - addr[0xAAA] = 0x5555; - addr[0x555] = 0xA0A0; - - *((vu_short *)dest) = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - - /* Now write lower 16 bits */ - sdata = (short)(data&0xffff); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x555] = 0xAAAA; - addr[0xAAA] = 0x5555; - addr[0x555] = 0xA0A0; - - *((vu_short *)dest + 1) = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds deleted file mode 100644 index f9722db..0000000 --- a/board/v37/u-boot.lds +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - cpu/mpc8xx/traps.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - lib_ppc/cache.o (.text) - lib_ppc/time.o (.text) - -/* - . = env_offset; -*/ - common/environment.o (.ppcenv) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/v37/v37.c b/board/v37/v37.c deleted file mode 100644 index 1ef879d..0000000 --- a/board/v37/v37.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * DRAM related UPMA register values are modified. - * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS - */ - -#include -#include "mpc8xx.h" - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (void); - -/* ------------------------------------------------------------------------- */ - -#define MBYTE (1024*1024) -#define DRAM_DELAY 0x00000379 /* DRAM delay count */ -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000, - 0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, - - /* burst read. (Offset 8 in upm RAM) */ - 0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000, - 0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* single write. (Offset 0x18 in upm RAM) */ - 0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* burst write. (Offset 0x20 in upm RAM) */ - 0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000, - 0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Refresh cycle, offset 0x30 */ - 0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* Exception, 0ffset 0x3C */ - 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, -}; -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Return 1 for now. - * - */ - -int checkboard (void) -{ - printf("Marel V37\n") ; - return (0) ; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long temp; - volatile int delay_cnt; - long int ramsize; - - ramsize = dram_size(); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = 0x400 ; - - if( ramsize == 32*MBYTE ) - temp = 0xd0904110; - else /* 16MB */ - temp = 0xd0802110; - - memctl->memc_mbmr = temp; - - upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* Map controller banks 2 to the SDRAM bank */ - memctl->memc_or2 = 0xA00 | (0 - ramsize); - memctl->memc_br2 = 0xC1; - - memctl->memc_mbmr = temp | 0x08; - memctl->memc_mcr = 0x80804130; - - delay_cnt = 0; - while( delay_cnt++ < DRAM_DELAY ) - ; - - /* Run MRS command in location 5-8 of UPMB */ - - memctl->memc_mbmr = temp | 0x04; - memctl->memc_mar = 0x88; - - memctl->memc_mcr = 0x80804105; - - delay_cnt = 0; - while( delay_cnt++ < DRAM_DELAY ) - ; - -#ifdef CONFIG_CAN_DRIVER - /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CFG_OR3_CAN; - memctl->memc_br3 = CFG_BR3_CAN; - - /* Initialize MBMR */ - memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; - memctl->memc_mcr = 0x0100 | UPMA; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMA; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMA; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMA; - - memctl->memc_mdr = 0xFFFFDC05; - memctl->memc_mcr = 0x0104 | UPMA; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x0118 | UPMA; - - memctl->memc_mdr = 0xCFFCD004; - memctl->memc_mcr = 0x0119 | UPMA; - - memctl->memc_mdr = 0x0FFCC000; - memctl->memc_mcr = 0x011A | UPMA; - - memctl->memc_mdr = 0x7FFCC004; - memctl->memc_mcr = 0x011B | UPMA; - - memctl->memc_mdr = 0xFFFDCC05; - memctl->memc_mcr = 0x011C | UPMA; -#endif /* CONFIG_CAN_DRIVER */ - - return (dram_size()); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Find size of RAM from configuration pins. - * The input pins that contain the memory size are also the debug port - * pins. Normally they are configured as debug port pins. To be able - * to read the memory configuration, we must deactivate the debug port - * and enable the pcmcia input pins. Then return the register to - * previous state. - */ - -static long int dram_size () -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile sysconf8xx_t *siu = &immap->im_siu_conf; - volatile pcmconf8xx_t *pcm = &immap->im_pcmcia; - long int i, memory=1; - unsigned long siu_mcr; - - siu_mcr = siu->sc_siumcr; - siu->sc_siumcr = siu_mcr & 0xFF9FFFFF; - for(i=0; i<10; i++) i = i; - - memory = (pcm->pcmc_pipr>>12) & 0x3; - - siu->sc_siumcr = siu_mcr; - - switch( memory ) - { - case 1: - return( 32*MBYTE ); - case 2: - return( 64*MBYTE ); - default: - break; - } - return( 16*MBYTE ); -} diff --git a/board/versatile/Makefile b/board/versatile/Makefile deleted file mode 100644 index fbdc627..0000000 --- a/board/versatile/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := versatile.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/versatile/config.mk b/board/versatile/config.mk deleted file mode 100644 index 25b79b3..0000000 --- a/board/versatile/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -# -# image should be loaded at 0x01000000 -# - -TEXT_BASE = 0x01000000 diff --git a/board/versatile/flash.c b/board/versatile/flash.c deleted file mode 100644 index 7153371..0000000 --- a/board/versatile/flash.c +++ /dev/null @@ -1,514 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256K3[] = { - {256, 128 * 1024}, /* 256 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ - -static void flash_vpp(int on) -{ - unsigned int tmp; - - tmp = *(unsigned int *)(VERSATILE_FLASHCTRL); - - if (on) - tmp |= VERSATILE_FLASHPROG_FLVPPEN; - else - tmp &= ~VERSATILE_FLASHPROG_FLVPPEN; - - *(unsigned int *)(VERSATILE_FLASHCTRL) = tmp; -} - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_vpp(1); - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - flash_vpp(0); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - OrgDef *pOrgDef; - - pOrgDef = OrgIntel_28F256K3; - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - case FLASH_28F256K3: - printf ("FLASH 28F256K3\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - case (FPW)(INTEL_ID_28F256K3): - info->flash_id += FLASH_28F256K3; - info->sector_count = 256; - info->size = 0x02000000; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - flash_vpp(1); - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - - flash_vpp(0); - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - flash_vpp(1); - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - flash_vpp(0); - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - flash_vpp(0); - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - flash_vpp(0); - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - rc = write_data (info, wp, SWAP (data)); - - flash_vpp(0); - - return rc; -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - - flash_vpp(1); - - flash_unprotect_sectors (addr); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - flash_vpp(0); - return (1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - flash_vpp(0); - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/versatile/lowlevel_init.S b/board/versatile/lowlevel_init.S deleted file mode 100644 index bdfce2d..0000000 --- a/board/versatile/lowlevel_init.S +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003, ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* Set up the platform, once the cpu has been initialized */ -.globl lowlevel_init -lowlevel_init: - - /* All done by Versatile's boot monitor! */ - mov pc, lr diff --git a/board/versatile/split_by_variant.sh b/board/versatile/split_by_variant.sh deleted file mode 100755 index 35c663e..0000000 --- a/board/versatile/split_by_variant.sh +++ /dev/null @@ -1,40 +0,0 @@ -#!/bin/sh -# --------------------------------------------------------- -# Set the core module defines according to Core Module -# --------------------------------------------------------- -# --------------------------------------------------------- -# Set up the Versatile type define -# --------------------------------------------------------- -variant=PB926EJ-S -if [ "$1" == "" ] -then - echo "$0:: No parameters - using versatilepb_config" - echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h - variant=PB926EJ-S -else - case "$1" in - versatilepb_config | \ - versatile_config) - echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h - ;; - - versatileab_config) - echo "#define CONFIG_ARCH_VERSATILE_AB" > ./include/config.h - variant=AB926EJ-S - ;; - - - *) - echo "$0:: Unrecognised config - using versatilepb_config" - echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h - variant=PB926EJ-S - ;; - - esac - -fi -# --------------------------------------------------------- -# Complete the configuration -# --------------------------------------------------------- -./mkconfig -a versatile arm arm926ejs versatile -echo "Variant:: $variant" diff --git a/board/versatile/u-boot.lds b/board/versatile/u-boot.lds deleted file mode 100644 index cb6ee18..0000000 --- a/board/versatile/u-boot.lds +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - . = ALIGN(4); - .text : - { - cpu/arm926ejs/start.o (.text) - *(.text) - } - .rodata : { *(.rodata) } - . = ALIGN(4); - .data : { *(.data) } - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/versatile/versatile.c b/board/versatile/versatile.c deleted file mode 100644 index 0274027..0000000 --- a/board/versatile/versatile.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -void flash__init (void); -void ether__init (void); -void peripheral_power_enable (void); - -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -void show_boot_progress(int progress) -{ - printf("Boot reached stage %d\n", progress); -} -#endif - -#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - - /* - * set clock frequency: - * VERSATILE_REFCLK is 32KHz - * VERSATILE_TIMCLK is 1MHz - */ - *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |= - ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | - (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel)); - - /* arch number of Versatile Board */ - gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - gd->flags = 0; - - icache_enable (); - - flash__init (); - ether__init (); - return 0; -} - - -int misc_init_r (void) -{ - setenv("verify", "n"); - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - return 0; -} diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile deleted file mode 100644 index 6302fa8..0000000 --- a/board/voiceblue/Makefile +++ /dev/null @@ -1,66 +0,0 @@ -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de -# -# (C) Copyright 2005 -# Ladislav Michl, 2N Telekomunikace, michl@2n.cz -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License version 2 as -# published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := voiceblue.o -SOBJS := setup.o - -gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) - -LOAD_ADDR = 0x10400000 -LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds - -all: $(LIB) eeprom.srec eeprom.bin - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -eeprom.srec: eeprom.o eeprom_start.o - $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \ - -o $(<:.o=) -e $(<:.o=) $^ \ - -L../../examples -lstubs \ - -L../../lib_generic -lgeneric \ - -L$(gcclibdir) -lgcc - $(OBJCOPY) -O srec $(<:.o=) $@ - -eeprom.bin: eeprom.srec - $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null - -clean: - rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin - -distclean: clean - rm -f $(LIB) core config.tmp *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/voiceblue/config.mk b/board/voiceblue/config.mk deleted file mode 100644 index c73cd27..0000000 --- a/board/voiceblue/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# Linux-Kernel is expected to be at 1000'8000, -# entry 1000'8000 (mem base + reserved) -# - -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - -ifeq ($(VOICEBLUE_SMALL_FLASH),y) -# We load ourself to internal SRAM at 2001'2000 -# Check map file when changing TEXT_BASE. -# Everything has fit into 192kB internal SRAM! -TEXT_BASE = 0x20012000 -else -# Running in SDRAM... -TEXT_BASE = 0x13000000 -endif diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c deleted file mode 100644 index 0ad1b66..0000000 --- a/board/voiceblue/eeprom.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * (C) Copyright 2005 - * Ladislav Michl, 2N Telekomunikace, michl@2n.cz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Some code shamelessly stolen back from Robin Getz. - */ - -#define DEBUG - -#include -#include -#include "../drivers/smc91111.h" - -#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE - -static u16 read_eeprom_reg(u16 reg) -{ - int timeout; - - SMC_SELECT_BANK(2); - SMC_outw(reg, PTR_REG); - - SMC_SELECT_BANK(1); - SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, - CTL_REG); - timeout = 100; - while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout) - udelay(100); - if (timeout == 0) { - printf("Timeout Reading EEPROM register %02x\n", reg); - return 0; - } - - return SMC_inw (GP_REG); -} - -static int write_eeprom_reg(u16 value, u16 reg) -{ - int timeout; - - SMC_SELECT_BANK(2); - SMC_outw(reg, PTR_REG); - - SMC_SELECT_BANK(1); - SMC_outw(value, GP_REG); - SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); - timeout = 100; - while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout) - udelay (100); - if (timeout == 0) { - printf("Timeout Writing EEPROM register %02x\n", reg); - return 0; - } - - return 1; -} - -static int write_data(u16 *buf, int len) -{ - u16 reg = 0x23; - - while (len--) - write_eeprom_reg(*buf++, reg++); - - return 0; -} - -static int verify_macaddr(char *s) -{ - u16 reg; - int i, err = 0; - - printf("MAC Address: "); - err = i = 0; - for (i = 0; i < 3; i++) { - reg = read_eeprom_reg(0x20 + i); - printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); - if (s) - err |= reg != ((u16 *)s)[i]; - } - - return err ? 0 : 1; -} - -static int set_mac(char *s) -{ - int i; - char *e, eaddr[6]; - - /* turn string into mac value */ - for (i = 0; i < 6; i++) { - eaddr[i] = simple_strtoul(s, &e, 16); - s = (*e) ? e+1 : e; - } - - for (i = 0; i < 3; i++) - write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); - - return 0; -} - -static int parse_element(char *s, unsigned char *buf, int len) -{ - int cnt; - char *p, num[3]; - unsigned char id; - - id = simple_strtoul(s, &p, 16); - if (*p++ != ':') - return -1; - cnt = 2; - num[2] = 0; - for (; *p; p += 2) { - if (p[1] == 0) - return -2; - if (cnt + 3 > len) - return -3; - num[0] = p[0]; - num[1] = p[1]; - buf[cnt++] = simple_strtoul(num, NULL, 16); - } - buf[0] = id; - buf[1] = cnt - 2; - - return cnt; -} - -int eeprom(int argc, char *argv[]) -{ - int i, len, ret; - unsigned char buf[58], *p; - - app_startup(argv); - if (get_version() != XF_VERSION) { - printf("Wrong XF_VERSION.\n"); - printf("Application expects ABI version %d\n", XF_VERSION); - printf("Actual U-Boot ABI version %d\n", (int)get_version()); - return 1; - } - - if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { - printf("SMSC91111 not found.\n"); - return 2; - } - - /* Called without parameters - print MAC address */ - if (argc < 2) { - verify_macaddr(NULL); - return 0; - } - - /* Print help message */ - if (argv[1][1] == 'h') { - printf("VoiceBlue EEPROM writer\n"); - printf("Built: %s at %s\n", __DATE__ , __TIME__ ); - printf("Usage:\n\t [] [<...>]\n"); - return 0; - } - - /* Try to parse information elements */ - len = sizeof(buf); - p = buf; - for (i = 2; i < argc; i++) { - ret = parse_element(argv[i], p, len); - switch (ret) { - case -1: - printf("Element %d: malformed\n", i - 1); - return 3; - case -2: - printf("Element %d: odd character count\n", i - 1); - return 3; - case -3: - printf("Out of EEPROM memory\n"); - return 3; - default: - p += ret; - len -= ret; - } - } - - /* First argument (MAC) is mandatory */ - set_mac(argv[1]); - if (verify_macaddr(argv[1])) { - printf("*** MAC address does not match! ***\n"); - return 4; - } - - while (len--) - *p++ = 0; - - write_data((u16 *)buf, sizeof(buf) >> 1); - - return 0; -} diff --git a/board/voiceblue/eeprom.lds b/board/voiceblue/eeprom.lds deleted file mode 100644 index 317550d..0000000 --- a/board/voiceblue/eeprom.lds +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * (C) Copyright 2005 - * Ladislav Michl, 2N Telekomunikace, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = ALIGN(4); - .text : - { - eeprom_start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/voiceblue/eeprom_start.S b/board/voiceblue/eeprom_start.S deleted file mode 100644 index 8f88de5..0000000 --- a/board/voiceblue/eeprom_start.S +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2005 2N Telekomunikace - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - */ - -.globl _start -_start: b eeprom diff --git a/board/voiceblue/setup.S b/board/voiceblue/setup.S deleted file mode 100644 index dcf37b5..0000000 --- a/board/voiceblue/setup.S +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004 Ales Jindra - * (C) Copyright 2005 Ladislav Michl - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* SDRAM load addr from config.mk */ - -OMAP5910_LPG1_BASE: .word 0xfffbd000 -OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800 -OMAP5910_MPU_TC_BASE: .word 0xfffecc00 -OMAP5910_MPU_CLKM_BASE: .word 0xfffece00 -OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800 -OMAP5910_DPLL1_BASE: .word 0xfffecf00 -OMAP5910_GPIO_BASE: .word 0xfffce000 -OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800 -OMAP5910_MPUI_BASE: .word 0xfffec900 - -_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL -_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK - -OMAP5910_MPUI_CTRL: .word 0x0000ff1b - -VAL_EMIFS_CS0_CONFIG: .word 0x00009090 -VAL_EMIFS_CS1_CONFIG: .word 0x00003031 -VAL_EMIFS_CS2_CONFIG: .word 0x00003031 -VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0 -VAL_EMIFS_DYN_WAIT: .word 0x00000000 -/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */ - /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */ -VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) -VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 -VAL_EMIFF_MRS: .word 0x00000037 - -/* - * GPIO04 - D4 (Onboard LED) - * GPIO07 - LAN91C111 reset - */ -GPIO_DIRECTION: - .word 0x0000ff6f -/* - * Disable everything, but D4 LED (connected through invertor) - */ -GPIO_OUTPUT: - .word 0x00000010 - -MUX_CONFIG_BASE: - .word 0xfffe1000 - -MUX_CONFIG_VALUES: - .align 4 - .word 0x00000000 @ FUNC_MUX_CTRL_0 - .word 0x00000000 @ FUNC_MUX_CTRL_1 - .word 0x00000000 @ FUNC_MUX_CTRL_2 - .word 0x00000000 @ FUNC_MUX_CTRL_3 - .word 0x00000000 @ FUNC_MUX_CTRL_4 - .word 0x12082480 @ FUNC_MUX_CTRL_5 - .word 0x00000004 @ FUNC_MUX_CTRL_6 - .word 0x00000003 @ FUNC_MUX_CTRL_7 - .word 0x10001200 @ FUNC_MUX_CTRL_8 - .word 0x01201012 @ FUNC_MUX_CTRL_9 - .word 0x02081248 @ FUNC_MUX_CTRL_A - .word 0x00001248 @ FUNC_MUX_CTRL_B - .word 0x12240000 @ FUNC_MUX_CTRL_C - .word 0x00002000 @ FUNC_MUX_CTRL_D - .word 0x00000000 @ PULL_DWN_CTRL_0 - .word 0x0000085f @ PULL_DWN_CTRL_1 - .word 0x01001000 @ PULL_DWN_CTRL_2 - .word 0x00000000 @ PULL_DWN_CTRL_3 - .word 0x00000000 @ GATE_INH_CTRL_0 - .word 0x00000000 @ VOLTAGE_CTRL_0 - .word 0x00000000 @ TEST_DBG_CTRL_0 - .word 0x00000006 @ MOD_CONF_CTRL_0 - .word 0x0000eaef @ COMP_MODE_CTRL_0 - -MUX_CONFIG_OFFSETS: - .align 1 - .byte 0x00 @ FUNC_MUX_CTRL_0 - .byte 0x04 @ FUNC_MUX_CTRL_1 - .byte 0x08 @ FUNC_MUX_CTRL_2 - .byte 0x10 @ FUNC_MUX_CTRL_3 - .byte 0x14 @ FUNC_MUX_CTRL_4 - .byte 0x18 @ FUNC_MUX_CTRL_5 - .byte 0x1c @ FUNC_MUX_CTRL_6 - .byte 0x20 @ FUNC_MUX_CTRL_7 - .byte 0x24 @ FUNC_MUX_CTRL_8 - .byte 0x28 @ FUNC_MUX_CTRL_9 - .byte 0x2c @ FUNC_MUX_CTRL_A - .byte 0x30 @ FUNC_MUX_CTRL_B - .byte 0x34 @ FUNC_MUX_CTRL_C - .byte 0x38 @ FUNC_MUX_CTRL_D - .byte 0x40 @ PULL_DWN_CTRL_0 - .byte 0x44 @ PULL_DWN_CTRL_1 - .byte 0x48 @ PULL_DWN_CTRL_2 - .byte 0x4c @ PULL_DWN_CTRL_3 - .byte 0x50 @ GATE_INH_CTRL_0 - .byte 0x60 @ VOLTAGE_CTRL_0 - .byte 0x70 @ TEST_DBG_CTRL_0 - .byte 0x80 @ MOD_CONF_CTRL_0 - .byte 0x0c @ COMP_MODE_CTRL_0 - .byte 0xff - -.globl lowlevel_init -lowlevel_init: - /* Improve performance a bit... */ - mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register - mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register - mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register - orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 - mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register - mov r1, #0x00 - mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache - nop - nop - nop - nop - - /* Setup clocking mode */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit - ldrh r1, [r0, #0x18] @ get reset status - bic r1, r1, #(7 << 11) @ clear clock select - orr r1, r1, #(2 << 11) @ set synchronous scalable - mov r2, #0 @ set wait counter to 100 clock cycles - -icache_loop: - cmp r2, #0x01 - streqh r1, [r0, #0x18] - add r2, r2, #0x01 - cmp r2, #0x10 - bne icache_loop - nop - - /* Setup clock divisors */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit - ldr r1, _OMAP5910_ARM_CKCTL - orr r1, r1, #0x2000 @ enable DSP clock - strh r1, [r0, #0x00] @ setup clock divisors - - /* Setup DPLL to generate requested freq */ - ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF - orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF - strh r1, [r0] @ write - -locking: - ldrh r1, [r0] @ get DPLL value - tst r1, #0x01 - beq locking @ while LOCK not set - - /* Enable clock */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit - mov r1, #(1 << 10) @ disable idle mode do not check - @ nWAKEUP pin, other remain active - strh r1, [r0, #0x04] - ldr r1, _OMAP5910_ARM_EN_CLK - strh r1, [r0, #0x08] - mov r1, #0x003f @ FLASH.RP not enabled in idle and - @ max delayed ( 32 x CLKIN ) - strh r1, [r0, #0x0c] - - /* Configure 5910 pins functions to match our board. */ - ldr r0, MUX_CONFIG_BASE - adr r1, MUX_CONFIG_VALUES - adr r2, MUX_CONFIG_OFFSETS -next_mux_cfg: - ldrb r3, [r2], #1 - ldr r4, [r1], #4 - cmp r3, #0xff - strne r4, [r0, r3] - bne next_mux_cfg - - /* Configure GPIO pins (also enables onboard LED) */ - ldr r0, OMAP5910_GPIO_BASE - ldr r1, GPIO_OUTPUT - strh r1, [r0, #0x04] - ldr r1, GPIO_DIRECTION - strh r1, [r0, #0x08] - - /* EnablePeripherals */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit - mov r1, #0x0001 @ Peripheral enable - strh r1, [r0, #0x14] - - /* Program LED Pulse Generator */ - ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator - mov r1, #0x7F @ Set obscure frequency in - strb r1, [r0, #0x00] @ LCR - mov r1, #0x01 @ Enable clock (CLK_EN) in - strb r1, [r0, #0x04] @ PMR - - /* TIPB Lock UART1 */ - ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches - mov r1, #1 @ ARM allocated - strh r1, [r0,#0x04] @ clear IRQ line and status bits - strh r1, [r0,#0x00] - ldrh r1, [r0,#0x04] - - /* Disable watchdog */ - ldr r0, OMAP5910_MPU_WD_TIMER_BASE - mov r1, #0xf5 - strh r1, [r0, #0x8] - mov r1, #0xa0 - strh r1, [r0, #0x8] - - /* Enable MCLK */ - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE - mov r1, #0x6 - strh r1, [r0, #0x34] - strh r1, [r0, #0x34] - - /* Setup clock divisors */ - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register - - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - strh r1, [r0] @ write - -ulocking: - ldrh r1, [r0] @ get DPLL value - tst r1, #1 - beq ulocking @ while LOCK not set - - /* EMIF init */ - ldr r0, OMAP5910_MPU_TC_BASE - ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG - bic r1, r1, #0x0c @ pwr down disabled, flash WP - orr r1, r1, #0x01 - str r1, [r0, #0x0c] - - ldr r1, VAL_EMIFS_CS0_CONFIG - str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG - ldr r1, VAL_EMIFS_CS1_CONFIG - str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG - ldr r1, VAL_EMIFS_CS2_CONFIG - str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG - ldr r1, VAL_EMIFS_CS3_CONFIG - str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG - ldr r1, VAL_EMIFS_DYN_WAIT - str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT - - /* Setup SDRAM */ - ldr r1, VAL_EMIFF_SDRAM_CONFIG - str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG - ldr r1, VAL_EMIFF_SDRAM_CONFIG2 - str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2 - ldr r1, VAL_EMIFF_MRS - str r1, [r0, #0x24] @ EMIFF_MRS - /* SDRAM needs 100us to stabilize */ - mov r0, #0x4000 -sdelay: - subs r0, r0, #0x1 - bne sdelay - - /* back to arch calling code */ - mov pc, lr -.end diff --git a/board/voiceblue/u-boot.lds b/board/voiceblue/u-boot.lds deleted file mode 100644 index f35a3ab..0000000 --- a/board/voiceblue/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm925t/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c deleted file mode 100644 index 7a2d243..0000000 --- a/board/voiceblue/voiceblue.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -int board_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa; - - /* arch number of VoiceBlue board */ - /* TODO: use define from asm/mach-types.h */ - gd->bd->bi_arch_number = 218; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff; - - /* Take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. */ - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; - udelay(10); /* doesn't work before interrupt_init call */ - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; - udelay(500); - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -int misc_init_r(void) -{ - *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55; - - return 0; -} - -int board_late_init(void) -{ - *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0x00; - - return 0; -} diff --git a/board/w7o/Makefile b/board/w7o/Makefile deleted file mode 100644 index d008f89..0000000 --- a/board/w7o/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2001 -# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \ - watchdog.o -SOBJS = init.o post1.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c deleted file mode 100644 index 449089e..0000000 --- a/board/w7o/cmd_vpd.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -#include "vpd.h" - -/* ====================================================================== - * Interpreter command to retrieve board specific Vital Product Data, "VPD" - * ====================================================================== - */ -int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - VPD vpd; /* Board specific data struct */ - uchar dev_addr = CFG_DEF_EEPROM_ADDR; - - /* Validate usage */ - if (argc > 2) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - /* Passed in EEPROM address */ - if (argc == 2) - dev_addr = (uchar) simple_strtoul (argv[1], NULL, 16); - - /* Read VPD and output it */ - if (!vpd_get_data (dev_addr, &vpd)) { - vpd_print (&vpd); - return 0; - } - - return 1; -} - -U_BOOT_CMD( - vpd, 2, 1, do_vpd, - "vpd - Read Vital Product Data\n", - "[dev_addr]\n" - " - Read VPD Data from default address, or device address 'dev_addr'.\n" -); - -#endif /* (CONFIG_COMMANDS & CFG_CMD_BSP) */ diff --git a/board/w7o/config.mk b/board/w7o/config.mk deleted file mode 100644 index bc341ca..0000000 --- a/board/w7o/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2001 -# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Wave 7 Optics boards -# - -#TEXT_BASE = 0xFFF80000 -TEXT_BASE = 0xFFFC0000 - -#PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARD) diff --git a/board/w7o/errors.h b/board/w7o/errors.h deleted file mode 100644 index 05b4eae..0000000 --- a/board/w7o/errors.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _ERRORS_H_ -#define _ERRORS_H_ - -#define ERR_FF -1 /* led test value(2) */ -#define ERR_00 0x0000 /* led test value(2) */ -#define ERR_LED 0x01 /* led test failed (1)(3)(4) */ -#define ERR_RAMG 0x04 /* start SDRAM data bus test (2) */ -#define ERR_RAML 0x05 /* SDRAM data bus fault in LSW chip (5) */ -#define ERR_RAMH 0x06 /* SDRAM data bus fault in MSW chip (6) */ -#define ERR_RAMB 0x07 /* SDRAM data bus fault both chips (5)(6)(7) */ -#define ERR_ADDG 0x08 /* start Address ghosting test (13) */ -#define ERR_ADDF 0x09 /* fault during Address ghosting test (13) */ -#define ERR_POST1 0x0a /* post1 tests complete */ -#define ERR_TMP1 0x0b /* */ -#define ERR_R55G 0x0c /* start SDRAM fill 55 test (2) */ -#define ERR_R55L 0x0d /* SDRAM fill test 55 failed in LSW chip (8) */ -#define ERR_R55H 0x0e /* SDRAM fill test 55 failed in MSW chip (9) */ -#define ERR_R55B 0x0f /* SDRAM fill test 55 fail in both chips (10) */ -#define ERR_RAAG 0x10 /* start SDRAM fill aa test (2) */ -#define ERR_RAAL 0x11 /* SDRAM fill test aa failed in LSW chip (8) */ -#define ERR_RAAH 0x12 /* SDRAM fill test aa failed in MSW chip (9) */ -#define ERR_RAAB 0x13 /* SDRAM fill test aa fail in both chips (10) */ -#define ERR_R00G 0x14 /* start SDRAM fill 00 test (2) */ -#define ERR_R00L 0x15 /* SDRAM fill test 00 failed in LSW chip (8) */ -#define ERR_R00H 0x16 /* SDRAM fill test 00 failed in MSW chip (9) */ -#define ERR_R00B 0x17 /* SDRAM fill test 00 fail in both chips (10) */ -#define ERR_RTCG 0x18 /* start RTC test */ -#define ERR_RTCBAT 0x19 /* RTC battery failure */ -#define ERR_RTCTIM 0x1A /* RTC invalid time/date values */ -#define ERR_RTCVAL 0x1B /* RTC NVRAM not accessable */ -#define ERR_FPGAG 0x20 /* fault during FPGA programming */ -#define ERR_XRW1 0x21 /* Xilinx - can't read/write regs on FPGA 1 */ -#define ERR_XRW2 0x22 /* Xilinx - can't read/write regs on FPGA 2 */ -#define ERR_XRW3 0x23 /* Xilinx - can't read/write regs on FPGA 3 */ -#define ERR_XRW4 0x24 /* Xilinx - can't read/write regs on FPGA 4 */ -#define ERR_XRW5 0x25 /* Xilinx - can't read/write regs on FPGA 5 */ -#define ERR_XRW6 0x26 /* Xilinx - can't read/write regs on FPGA 6 */ -#define ERR_XINIT0 0x27 /* Xilinx - INIT line failed to go low */ -#define ERR_XINIT1 0x28 /* Xilinx - INIT line failed to go high */ -#define ERR_XDONE1 0x29 /* Xilinx - DONE line failed to go high */ -#define ERR_XIMAGE 0x2A /* Xilinx - Bad FPGA image in Flash */ -#define ERR_TempG 0x2b /* start temp sensor tests */ -#define ERR_Tinit0 0x2C /* temp sensor 0 failed to init */ -#define ERR_Tinit1 0x2D /* temp sensor 1 failed to init */ -#define ERR_Ttest0 0x2E /* temp sensor 0 failed test */ -#define ERR_Ttest1 0x2F /* temp sensor 1 failed test */ -#define ERR_lm75r 0x30 /* temp sensor read failure */ -#define ERR_lm75w 0x31 /* temp sensor write failure */ - - -#define ERR_POSTOK 0x55 /* PANIC: psych... OK */ - -#if !defined(__ASSEMBLY__) -extern void log_stat(int errcode); -extern void log_warn(int errcode); -extern void log_err(int errcode); -#endif - -/* -Debugging suggestions: -(1) periferal data bus shorted or crossed -(2) general processor halt, check reset, watch dog, power supply ripple, processor clock. -(3) check p_we, p_r/w, p_oe, p_rdy lines. -(4) check LED buffers -(5) check SDRAM data bus bits 16-31, check LSW SDRAM chip. -(6) check SDRAM data bus bits 0-15, check MSW SDRAM chip. -(7) check SDRAM control lines and clocks -(8) check decoupling caps, replace LSW SDRAM -(9) check decoupling caps, replace MSW SDRAM -(10) -(11) -(12) -(13) SDRAM address shorted or unconnected, check sdram caps -*/ -#endif /* _ERRORS_H_ */ diff --git a/board/w7o/flash.c b/board/w7o/flash.c deleted file mode 100644 index 32815fb..0000000 --- a/board/w7o/flash.c +++ /dev/null @@ -1,940 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * Based on code by: - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word8(flash_info_t *info, ulong dest, ulong data); -static int write_word32 (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - unsigned long size_b0, base_b0; - unsigned long size_b1, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Get Size of Boot and Main Flashes */ - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - return 0; - } - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - if (flash_info[1].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", - size_b1, size_b1<<20); - return 0; - } - - /* Calculate base addresses */ - base_b0 = -size_b0; - base_b1 = -size_b1; - - /* Setup offsets for Boot Flash */ - flash_get_offsets (base_b0, &flash_info[0]); - - /* Protect board level data */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b0, - flash_info[0].start[1] - 1, - &flash_info[0]); - - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, - &flash_info[0]); - - /* Protect the FPGA image */ - (void)flash_protect(FLAG_PROTECT_SET, - FLASH_BASE1_PRELIM, - FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN - 1, - &flash_info[1]); - - /* Protect the default boot image */ - (void)flash_protect(FLAG_PROTECT_SET, - FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN, - FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN + 0x600000 - 1, - &flash_info[1]); - - /* Setup offsets for Main Flash */ - flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[1]); - - return (size_b0 + size_b1); -} /* end flash_init() */ - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table - FOR BOOT ROM ONLY!!! */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } -} /* end flash_get_offsets() */ - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("1 x AMD "); break; - case FLASH_MAN_STM: printf ("1 x STM "); break; - case FLASH_MAN_INTEL: printf ("2 x Intel "); break; - default: printf ("Unknown Vendor "); - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - printf ("AM29LV040 (4096 Kbit, uniform sector size)\n"); - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) - printf ("M29W040B (4096 Kbit, uniform block size)\n"); - else - printf ("UNKNOWN 29x040x (4096 Kbit, uniform sector size)\n"); - break; - case FLASH_28F320J3A: - printf ("28F320J3A (32 Mbit = 128K x 32)\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A (64 Mbit = 128K x 64)\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A (128 Mbit = 128K x 128)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) { - printf (" Size: %ld KB in %d Blocks\n", - info->size >> 10, info->sector_count); - } else { - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); -} /* end flash_print_info() */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong base = (ulong)addr; - - /* Setup default type */ - info->flash_id = FLASH_UNKNOWN; - info->sector_count =0; - info->size = 0; - - /* Test for Boot Flash */ - if (base == FLASH_BASE0_PRELIM) { - unsigned char value; - volatile unsigned char * addr2 = (unsigned char *)addr; - - /* Write auto select command: read Manufacturer ID */ - *(addr2 + 0x555) = 0xaa; - *(addr2 + 0x2aa) = 0x55; - *(addr2 + 0x555) = 0x90; - - /* Manufacture ID */ - value = *addr2; - switch (value) { - case (unsigned char)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (unsigned char)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - *addr2 = 0xf0; /* no or unknown flash */ - return 0; - } - - /* Device ID */ - value = *(addr2 + 1); - switch (value) { - case (unsigned char)AMD_ID_LV040B: - case (unsigned char)STM_ID_29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - default: - *addr2 = 0xf0; /* => no or unknown flash */ - return 0; - } - } - else { /* MAIN Flash */ - unsigned long value; - volatile unsigned long * addr2 = (unsigned long *)addr; - - /* Write auto select command: read Manufacturer ID */ - *addr2 = 0x90909090; - - /* Manufacture ID */ - value = *addr2; - switch (value) { - case (unsigned long)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - *addr2 = 0xff; /* no or unknown flash */ - return 0; - } - - /* Device ID - This shit is interleaved... */ - value = *(addr2 + 1); - switch (value) { - case (unsigned long)INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000 * 2; - break; /* => 2 X 4 MB */ - case (unsigned long)INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000 * 2; - break; /* => 2 X 8 MB */ - case (unsigned long)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000 * 2; - break; /* => 2 X 16 MB */ - default: - *addr2 = 0xff; /* => no or unknown flash */ - } - } - - /* Make sure we don't exceed CFG_MAX_FLASH_SECT */ - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - /* set up sector start address table */ - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - break; - case FLASH_28F320J3A: - case FLASH_28F640J3A: - case FLASH_28F128J3A: - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00020000 * 2); /* 2 Banks */ - break; - } - - /* Test for Boot Flash */ - if (base == FLASH_BASE0_PRELIM) { - volatile unsigned char *addr2; - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (AX .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile unsigned char *)(info->start[i]); - info->protect[i] = *(addr2 + 2) & 1; - } - - /* Restore read mode */ - *(unsigned char *)base = 0xF0; /* Reset NORMAL Flash */ - } - else { /* Main Flash */ - volatile unsigned long *addr2; - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (AX .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile unsigned long *)(info->start[i]); - info->protect[i] = *(addr2 + 2) & 0x1; - } - - /* Restore read mode */ - *(unsigned long *)base = 0xFFFFFFFF; /* Reset Flash */ - } - - return (info->size); -} /* end flash_get_size() */ - -/*----------------------------------------------------------------------- - */ - -static int wait_for_DQ7(ulong addr, uchar cmp_val, ulong tout) -{ - int i; - - volatile uchar *vaddr = (uchar *)addr; - - /* Loop X times */ - for (i = 1; i <= (100 * tout); i++) { /* Wait up to tout ms */ - udelay(10); - /* Pause 10 us */ - - /* Check for completion */ - if ((vaddr[0] & 0x80) == (cmp_val & 0x80)) { - return 0; - } - - /* KEEP THE LUSER HAPPY - Print a dot every 1.1 seconds */ - if (!(i % 110000)) - putc('.'); - - /* Kick the dog if needed */ - WATCHDOG_RESET(); - } - - return 1; -} /* wait_for_DQ7() */ - -/*----------------------------------------------------------------------- - */ - -static int flash_erase8(flash_info_t *info, int s_first, int s_last) -{ - int tcode, rcode = 0; - volatile uchar *addr = (uchar *)(info->start[0]); - volatile uchar *sector_addr; - int flag, prot, sect; - - /* Validate arguments */ - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf ("- missing\n"); - else - printf ("- no sectors to erase\n"); - return 1; - } - - /* Check for KNOWN flash type */ - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - /* Check for protected sectors */ - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - else - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - sector_addr = (uchar *)(info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) - printf("Erasing block %p\n", sector_addr); - else - printf("Erasing sector %p\n", sector_addr); - - /* Disable interrupts which might cause Flash to timeout */ - flag = disable_interrupts(); - - *(addr + 0x555) = (uchar)0xAA; - *(addr + 0x2aa) = (uchar)0x55; - *(addr + 0x555) = (uchar)0x80; - *(addr + 0x555) = (uchar)0xAA; - *(addr + 0x2aa) = (uchar)0x55; - *sector_addr = (uchar)0x30; /* sector erase */ - - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - * Takes up to 6 seconds. - */ - tcode = wait_for_DQ7((ulong)sector_addr, 0x80, 6000); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* Make sure we didn't timeout */ - if (tcode) { - printf ("Timeout\n"); - rcode = 1; - } - } - } - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (uchar *)info->start[0]; - *addr = (uchar)0xF0; /* reset bank */ - - printf (" done\n"); - return rcode; -} /* end flash_erase8() */ - -static int flash_erase32(flash_info_t *info, int s_first, int s_last) -{ - int flag, sect; - ulong start, now, last; - int prot = 0; - - /* Validate arguments */ - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf ("- missing\n"); - else - printf ("- no sectors to erase\n"); - return 1; - } - - /* Check for KNOWN flash type */ - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - /* Check for protected sectors */ - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - else - printf ("\n"); - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - WATCHDOG_RESET(); - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = 0x00500050; /* clear status register */ - *addr = 0x00200020; /* erase setup */ - *addr = 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* Wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0x00B000B0; /* suspend erase */ - *addr = 0x00FF00FF; /* reset to read mode */ - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 990) { /* every second */ - putc ('.'); - last = now; - } - } - *addr = 0x00FF00FF; /* reset to read mode */ - } - } - printf (" done\n"); - return 0; -} /* end flash_erase32() */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) - return flash_erase8(info, s_first, s_last); - else - return flash_erase32(info, s_first, s_last); -} /* end flash_erase() */ - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_buff8(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - ulong start; - int i, l, rc; - - start = get_timer (0); - - wp = (addr & ~3); /* get lower word - aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word8(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word8(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - if (get_timer(start) > 1000) { /* every second */ - WATCHDOG_RESET(); - putc ('.'); - start = get_timer(0); - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word8(info, wp, data)); -} /* end write_buff8() */ - -#define FLASH_WIDTH 4 /* flash bus width in bytes */ -static int write_buff32 (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - ulong start; - - start = get_timer (0); - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i= FLASH_WIDTH) { - data = 0; - for (i=0; i 990) { /* every second */ - putc ('.'); - start = get_timer(0); - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; iflash_id & FLASH_TYPEMASK) == FLASH_AM040) - retval = write_buff8(info, src, addr, cnt); - else - retval = write_buff32(info, src, addr, cnt); - - return retval; -} /* end write_buff() */ - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -static int write_word8(flash_info_t *info, ulong dest, ulong data) -{ - volatile uchar *addr2 = (uchar *)(info->start[0]); - volatile uchar *dest2 = (uchar *)dest; - volatile uchar *data2 = (uchar *)&data; - int flag; - int i, tcode, rcode = 0; - - /* Check if Flash is (sufficently) erased */ - if ((*((volatile uchar *)dest) & - (uchar)data) != (uchar)data) { - return (2); - } - - for (i=0; i < (4 / sizeof(uchar)); i++) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *(addr2 + 0x555) = (uchar)0xAA; - *(addr2 + 0x2aa) = (uchar)0x55; - *(addr2 + 0x555) = (uchar)0xA0; - - dest2[i] = data2[i]; - - /* Wait for write to complete, up to 1ms */ - tcode = wait_for_DQ7((ulong)&dest2[i], data2[i], 1); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* Make sure we didn't timeout */ - if (tcode) { - rcode = 1; - } - } - - return rcode; -} /* end write_word8() */ - -static int write_word32(flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = 0x00400040; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((status = *addr) & 0x00800080) != 0x00800080) { - WATCHDOG_RESET(); - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *addr = 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = 0x00FF00FF; /* restore read mode */ - - return (0); -} /* end write_word32() */ - - -static int _flash_protect(flash_info_t *info, long sector) -{ - int i; - int flag; - ulong status; - int rcode = 0; - volatile long *addr = (long *)sector; - - switch(info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - case FLASH_28F640J3A: - case FLASH_28F128J3A: - /* Disable interrupts which might cause Flash to timeout */ - flag = disable_interrupts(); - - /* Issue command */ - *addr = 0x00500050L; /* Clear the status register */ - *addr = 0x00600060L; /* Set lock bit setup */ - *addr = 0x00010001L; /* Set lock bit confirm */ - - /* Wait for command completion */ - for (i = 0; i < 10; i++) { /* 75us timeout, wait 100us */ - udelay(10); - if ((*addr & 0x00800080L) == 0x00800080L) - break; - } - - /* Not successful? */ - status = *addr; - if (status != 0x00800080L) { - printf("Protect %x sector failed: %x\n", - (uint)sector, (uint)status); - rcode = 1; - } - - /* Restore read mode */ - *addr = 0x00ff00ffL; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - break; - case FLASH_AM040: /* No soft sector protection */ - break; - } - - /* Turn protection on for this sector */ - for (i = 0; i < info->sector_count; i++) { - if (info->start[i] == sector) { - info->protect[i] = 1; - break; - } - } - - return rcode; -} /* end _flash_protect() */ - -static int _flash_unprotect(flash_info_t *info, long sector) -{ - int i; - int flag; - ulong status; - int rcode = 0; - volatile long *addr = (long *)sector; - - switch(info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - case FLASH_28F640J3A: - case FLASH_28F128J3A: - /* Disable interrupts which might cause Flash to timeout */ - flag = disable_interrupts(); - - *addr = 0x00500050L; /* Clear the status register */ - *addr = 0x00600060L; /* Clear lock bit setup */ - *addr = 0x00D000D0L; /* Clear lock bit confirm */ - - /* Wait for command completion */ - for (i = 0; i < 80 ; i++) { /* 700ms timeout, wait 800 */ - udelay(10000); /* Delay 10ms */ - if ((*addr & 0x00800080L) == 0x00800080L) - break; - } - - /* Not successful? */ - status = *addr; - if (status != 0x00800080L) { - printf("Un-protect %x sector failed: %x\n", - (uint)sector, (uint)status); - *addr = 0x00ff00ffL; - rcode = 1; - } - - /* restore read mode */ - *addr = 0x00ff00ffL; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - break; - case FLASH_AM040: /* No soft sector protection */ - break; - } - - /* - * Fix Intel's little red wagon. Reprotect - * sectors that were protected before we undid - * protection on a specific sector. - */ - for (i = 0; i < info->sector_count; i++) { - if (info->start[i] != sector) { - if (info->protect[i]) { - if (_flash_protect(info, info->start[i])) - rcode = 1; - } - } - else /* Turn protection off for this sector */ - info->protect[i] = 0; - } - - return rcode; -} /* end _flash_unprotect() */ - - -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int rcode; - - if (prot) - rcode = _flash_protect(info, info->start[sector]); - else - rcode = _flash_unprotect(info, info->start[sector]); - - return rcode; -} /* end flash_real_protect() */ - -/*----------------------------------------------------------------------- - */ diff --git a/board/w7o/fpga.c b/board/w7o/fpga.c deleted file mode 100644 index 100bce4..0000000 --- a/board/w7o/fpga.c +++ /dev/null @@ -1,379 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * and - * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include "w7o.h" -#include -#include "errors.h" - -static void -fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr) -{ - unsigned long i; - volatile unsigned long val; - volatile unsigned short *dest = daddr; /* volatile-bypass optimizer */ - - for (i = 0; i < len; i++, src++) { - val = *src; - *dest = (unsigned short)((val & 0xff000000L) >> 16); - *dest = (unsigned short)((val & 0x00ff0000L) >> 8); - *dest = (unsigned short)(val & 0x0000ff00L); - *dest = (unsigned short)((val & 0x000000ffL) << 8); - } - - /* Terminate programming with 4 C clocks */ - dest = daddr; - val = *(unsigned short *)dest; - val = *(unsigned short *)dest; - val = *(unsigned short *)dest; - val = *(unsigned short *)dest; - -} - - -int -fpgaDownload(unsigned char *saddr, - unsigned long size, - unsigned short *daddr) -{ - int i; /* index, intr disable flag */ - int start; /* timer */ - unsigned long greg, grego; /* GPIO & output register */ - unsigned long length; /* image size in words */ - unsigned long *source; /* image source addr */ - unsigned short *dest; /* destination FPGA addr */ - volatile unsigned short *ndest; /* temp dest FPGA addr */ - volatile unsigned short val; /* temp val */ - unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */ - unsigned long eirq = GPIO_XCV_IRQ; - int retval = -1; /* Function return value */ - - /* Setup some basic values */ - length = (size / 4) + 1; /* size in words, rounding UP - is OK */ - source = (unsigned long *)saddr; - dest = (unsigned short *)daddr; - - /* Get DCR output register */ - grego = in32(PPC405GP_GPIO0_OR); - - /* Reset FPGA */ - grego &= ~GPIO_XCV_PROG; /* PROG line low */ - out32(PPC405GP_GPIO0_OR, grego); - - /* Setup timeout timer */ - start = get_timer(0); - - /* Wait for FPGA init line */ - while(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */ - /* Check for timeout - 100us max, so use 3ms */ - if (get_timer(start) > 3) { - printf(" failed to start init.\n"); - log_warn(ERR_XINIT0); /* Don't halt */ - - /* Reset line stays low */ - goto done; /* I like gotos... */ - } - } - - /* Unreset FPGA */ - grego |= GPIO_XCV_PROG; /* PROG line high */ - out32(PPC405GP_GPIO0_OR, grego); - - /* Wait for FPGA end of init period . */ - while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */ - - /* Check for timeout */ - if (get_timer(start) > 3) { - printf(" failed to exit init.\n"); - log_warn(ERR_XINIT1); - - /* Reset FPGA */ - grego &= ~GPIO_XCV_PROG; /* PROG line low */ - out32(PPC405GP_GPIO0_OR, grego); - - goto done; - } - } - - /* Now program FPGA ... */ - ndest = dest; - for (i = 0; i < CONFIG_NUM_FPGAS; i++) { - /* Toggle IRQ/GPIO */ - greg = mfdcr(CPC0_CR0); /* get chip ctrl register */ - greg |= eirq; /* toggle irq/gpio */ - mtdcr(CPC0_CR0, greg); /* ... just do it */ - - /* turn on open drain for CNFG */ - greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */ - greg |= cnfg; /* CNFG open drain */ - out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */ - - /* Turn output enable on for CNFG */ - greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */ - greg |= cnfg; /* CNFG tristate inactive */ - out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */ - - /* Setup FPGA for programming */ - grego &= ~cnfg; /* CONFIG line low */ - out32(PPC405GP_GPIO0_OR, grego); - - /* - * Program the FPGA - */ - printf("\n destination: 0x%lx ", (unsigned long)ndest); - - fpga_img_write(source, length, (unsigned short *)ndest); - - /* Done programming */ - grego |= cnfg; /* CONFIG line high */ - out32(PPC405GP_GPIO0_OR, grego); - - /* Turn output enable OFF for CNFG */ - greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */ - greg &= ~cnfg; /* CNFG tristate inactive */ - out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */ - - /* Toggle IRQ/GPIO */ - greg = mfdcr(CPC0_CR0); /* get chip ctrl register */ - greg &= ~eirq; /* toggle irq/gpio */ - mtdcr(CPC0_CR0, greg); /* ... just do it */ - - ndest = (unsigned short *)((char *)ndest + 0x00100000L); /* XXX - Next FPGA addr */ - cnfg >>= 1; /* XXX - Next */ - eirq >>= 1; - } - - /* Terminate programming with 4 C clocks */ - ndest = dest; - for (i = 0; i < CONFIG_NUM_FPGAS; i++) { - val = *ndest; - val = *ndest; - val = *ndest; - val = *ndest; - ndest = (unsigned short *)((char *)ndest + 0x00100000L); - } - - /* Setup timer */ - start = get_timer(0); - - /* Wait for FPGA end of programming period . */ - while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */ - - /* Check for timeout */ - if (get_timer(start) > 3) { - printf(" done failed to come high.\n"); - log_warn(ERR_XDONE1); - - /* Reset FPGA */ - grego &= ~GPIO_XCV_PROG; /* PROG line low */ - out32(PPC405GP_GPIO0_OR, grego); - - goto done; - } - } - - printf("\n FPGA load succeeded\n"); - retval = 0; /* Program OK */ - -done: - return retval; -} - -/* FPGA image is stored in flash */ -extern flash_info_t flash_info[]; - -int init_fpga(void) -{ - unsigned int i,j,ptr; /* General purpose */ - unsigned char bufchar; /* General purpose character */ - unsigned char *buf; /* Start of image pointer */ - unsigned long len; /* Length of image */ - unsigned char *fn_buf; /* Start of filename string */ - unsigned int fn_len; /* Length of filename string */ - unsigned char *xcv_buf; /* Pointer to start of image */ - unsigned long xcv_len; /* Length of image */ - unsigned long crc; /* 30bit crc in image */ - unsigned long calc_crc; /* Calc'd 30bit crc */ - int retval = -1; - - /* Tell the world what we are doing */ - printf("FPGA: "); - - /* - * Get address of first sector where the FPGA - * image is stored. - */ - buf = (unsigned char *)flash_info[1].start[0]; - - /* - * Get the stored image's CRC & length. - */ - crc = *(unsigned long *)(buf+4); /* CRC is first long word */ - len = *(unsigned long *)(buf+8); /* Image len is next long */ - - /* Pedantic */ - if ((len < 0x133A4) || (len > 0x80000)) - goto bad_image; - - /* - * Get the file name pointer and length. - */ - fn_len = (*(unsigned short *)(buf+12) & 0xff); /* filename length - is next short */ - fn_buf = buf + 14; - - /* - * Get the FPGA image pointer and length length. - */ - xcv_buf = fn_buf + fn_len; /* pointer to fpga image */ - xcv_len = len - 14 - fn_len; /* fpga image length */ - - /* Check for uninitialized FLASH */ - if ((strncmp((char *)buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0)) - goto bad_image; - - /* - * Calculate and Check the image's CRC. - */ - calc_crc = crc32(0, xcv_buf, xcv_len); - if (crc != calc_crc) { - printf("\nfailed - bad CRC\n"); - goto done; - } - - /* Output the file name */ - printf("file name : "); - for (i=0;i'~') bufchar = '.'; - putc(bufchar); - } - - /* - * find rest of display data - */ - ptr = 15; /* Offset to ncd filename - length in fpga image */ - j = xcv_buf[ptr]; /* Get len of ncd filename */ - if (j > 32) goto bad_image; - ptr = ptr + j + 3; /* skip ncd filename string + - 3 bytes more bytes */ - - /* - * output target device string - */ - j = xcv_buf[ptr++] - 1; /* len of targ str less term */ - if (j > 32) goto bad_image; - printf("\n target : "); - for (i = 0; i < j; i++) { - bufchar = (xcv_buf[ptr++]); - if (bufchar<' ' || bufchar>'~') bufchar = '.'; - putc(bufchar); - } - - /* - * output compilation date string and time string - */ - ptr += 3; /* skip 2 bytes */ - printf("\n synth time : "); - j = (xcv_buf[ptr++] - 1); /* len of date str less term */ - if (j > 32) goto bad_image; - for (i = 0; i < j; i++) { - bufchar = (xcv_buf[ptr++]); - if (bufchar<' ' || bufchar>'~') bufchar = '.'; - putc(bufchar); - } - - ptr += 3; /* Skip 2 bytes */ - printf(" - "); - j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */ - if (j > 32) goto bad_image; - for (i = 0; i < j; i++) { - bufchar = (xcv_buf[ptr++]); - if (bufchar<' ' || bufchar>'~') bufchar = '.'; - putc(bufchar); - } - - /* - * output crc and length strings - */ - printf("\n len & crc : 0x%lx 0x%lx", len, crc); - - /* - * Program the FPGA. - */ - retval = fpgaDownload((unsigned char*)xcv_buf, xcv_len, - (unsigned short *)0xfd000000L); - return retval; - -bad_image: - printf("\n BAD FPGA image format @ %lx\n", flash_info[1].start[0]); - log_warn(ERR_XIMAGE); -done: - return retval; -} - -void test_fpga(unsigned short *daddr) -{ - int i; - volatile unsigned short *ndest = daddr; - - for (i = 0; i < CONFIG_NUM_FPGAS; i++) { -#if defined(CONFIG_W7OLMG) - ndest[0x7e] = 0x55aa; - if (ndest[0x7e] != 0x55aa) - log_warn(ERR_XRW1 + i); - ndest[0x7e] = 0xaa55; - if (ndest[0x7e] != 0xaa55) - log_warn(ERR_XRW1 + i); - ndest[0x7e] = 0xc318; - if (ndest[0x7e] != 0xc318) - log_warn(ERR_XRW1 + i); - -#elif defined(CONFIG_W7OLMC) - ndest[0x800] = 0x55aa; - ndest[0x801] = 0xaa55; - ndest[0x802] = 0xc318; - ndest[0x4800] = 0x55aa; - ndest[0x4801] = 0xaa55; - ndest[0x4802] = 0xc318; - if ((ndest[0x800] != 0x55aa) || - (ndest[0x801] != 0xaa55) || - (ndest[0x802] != 0xc318)) - log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */ - if ((ndest[0x4800] != 0x55aa) || - (ndest[0x4801] != 0xaa55) || - (ndest[0x4802] != 0xc318)) - log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */ - -#else -# error "Unknown W7O board configuration" -#endif - } - - printf(" FPGA ready\n"); - return; -} diff --git a/board/w7o/fsboot.c b/board/w7o/fsboot.c deleted file mode 100644 index 0ef9a61..0000000 --- a/board/w7o/fsboot.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * (C) Copyright 2001 - * Wave 7 Optics, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * FIXME: Add code to test image and it's header. - */ -extern int valid_elf_image (unsigned long addr); - -static int -image_check(ulong addr) -{ - return valid_elf_image(addr); -} - -void -init_fsboot(void) -{ - char *envp; - ulong loadaddr; - ulong testaddr; - ulong alt_loadaddr; - char buf[9]; - - /* - * Get test image address - */ - if ((envp = getenv("testaddr")) != NULL) - testaddr = simple_strtoul(envp, NULL, 16); - else - testaddr = -1; - - /* - * Are we going to test boot and image? - */ - if ((testaddr != -1) && image_check(testaddr)) { - - /* Set alt_loadaddr */ - alt_loadaddr = testaddr; - sprintf(buf, "%lX", alt_loadaddr); - setenv("alt_loadaddr", buf); - - /* Clear test_addr */ - setenv("testaddr", NULL); - - /* - * Save current environment with alt_loadaddr, - * and cleared testaddr. - */ - saveenv(); - - /* - * Setup temporary loadaddr to alt_loadaddr - * XXX - DO NOT SAVE ENVIRONMENT! - */ - loadaddr = alt_loadaddr; - sprintf(buf, "%lX", loadaddr); - setenv("loadaddr", buf); - - } else { /* Normal boot */ - setenv("alt_loadaddr", NULL); /* Clear alt_loadaddr */ - setenv("testaddr", NULL); /* Clear testaddr */ - saveenv(); - } - - return; -} diff --git a/board/w7o/init.S b/board/w7o/init.S deleted file mode 100644 index 35d7dbc..0000000 --- a/board/w7o/init.S +++ /dev/null @@ -1,264 +0,0 @@ -/****************************************************************************** - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - *****************************************************************************/ -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -/****************************************************************************** - * Function: ext_bus_cntlr_init - * - * Description: Configures EBC Controller and a few basic chip selects. - * - * CS0 is setup to get the Boot Flash out of the addresss range - * so that we may setup a stack. CS7 is setup so that we can - * access and reset the hardware watchdog. - * - * IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl ext_bus_cntlr_init - .type ext_bus_cntlr_init, @function -ext_bus_cntlr_init: - mflr r0 - /******************************************************************** - * Prefetch entire ext_bus_cntrl_init function into the icache. - * This is necessary because we are going to change the same CS we - * are executing from. Otherwise a CPU lockup may occur. - *******************************************************************/ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - - /* Calculate number of cache lines for this function */ - addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2) - mtctr r4 -..ebcloop: - icbt r0, r3 /* prefetch cache line for addr in r3*/ - addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */ - bdnz ..ebcloop /* continue for $CTR cache lines */ - - /******************************************************************** - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. - *******************************************************************/ - addis r3, 0, 0x0 - ori r3, r3, 0xA000 /* wait 200us from reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /******************************************************************** - * Setup External Bus Controller (EBC). - *******************************************************************/ - addi r3, 0, epcr - mtdcr ebccfga, r3 - addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */ - ori r4, r4, 0x0 /* Drive CS with external master */ - mtdcr ebccfgd, r4 - - /******************************************************************** - * Change PCIINT signal to PerWE - *******************************************************************/ - mfdcr r4, cntrl1 - ori r4, r4, 0x4000 - mtdcr cntrl1, r4 - - /******************************************************************** - * Memory Bank 0 (Flash Bank 0) initialization - *******************************************************************/ - addi r3, 0, pb0ap - mtdcr ebccfga, r3 - addis r4, 0, CFG_W7O_EBC_PB0AP@h - ori r4, r4, CFG_W7O_EBC_PB0AP@l - mtdcr ebccfgd, r4 - - addi r3, 0, pb0cr - mtdcr ebccfga, r3 - addis r4, 0, CFG_W7O_EBC_PB0CR@h - ori r4, r4, CFG_W7O_EBC_PB0CR@l - mtdcr ebccfgd, r4 - - /******************************************************************** - * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs. - *******************************************************************/ - addi r3, 0, pb7ap - mtdcr ebccfga, r3 - addis r4, 0, CFG_W7O_EBC_PB7AP@h - ori r4, r4, CFG_W7O_EBC_PB7AP@l - mtdcr ebccfgd, r4 - - addi r3, 0, pb7cr - mtdcr ebccfga, r3 - addis r4, 0, CFG_W7O_EBC_PB7CR@h - ori r4, r4, CFG_W7O_EBC_PB7CR@l - mtdcr ebccfgd, r4 - - /* We are all done */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ -.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init -/* end ext_bus_cntlr_init() */ - -/****************************************************************************** - * Function: sdram_init - * - * Description: Configures SDRAM memory banks. - * - * Serial Presence Detect, "SPD," reads the SDRAM EEPROM - * via the IIC bus and then configures the SDRAM memory - * banks appropriately. If Auto Memory Configuration is - * is not used, it is assumed that a 4MB 11x8x2, non-ECC, - * SDRAM is soldered down. - * - * Notes: Expects that the stack is already setup. - *****************************************************************************/ - .section ".text" - .align 2 - .globl sdram_init - .type sdram_init, @function -sdram_init: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save link register */ - - /* - * First call spd_sdram to try to init SDRAM according to the - * contents of the SPD EEPROM. If the SPD EEPROM is blank or - * erronious, spd_sdram returns 0 in R3. - */ - li r3,0 - bl spd_sdram - addic. r3, r3, 0 /* Check for error, save dram size */ - bne ..sdri_done /* If it worked, we're done... */ - - /******************************************************************** - * If SPD detection fails, we'll default to 4MB, 11x8x2, as this - * is the SMALLEST SDRAM size the 405 supports. We can do this - * because W7O boards have soldered on RAM, and there will always - * be some amount present. If we were using DIMMs, we should hang - * the board instead, since it doesn't have any RAM to continue - * running with. - *******************************************************************/ - - /* - * Disable memory controller to allow - * values to be changed. - */ - addi r3, 0, mem_mcopt1 - mtdcr memcfga, r3 - addis r4, 0, 0x0 - ori r4, r4, 0x0 - mtdcr memcfgd, r4 - - /* - * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2 - * All other banks are disabled. - */ - addi r3, 0, mem_mb0cf - mtdcr memcfga, r3 - addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */ - ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */ - mtdcr memcfgd, r4 - - /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */ - addi r4, 0, 0 /* Zero the data reg */ - - addi r3, r3, 4 /* Point to MB1CF reg */ - mtdcr memcfga, r3 /* Set the address */ - mtdcr memcfgd, r4 /* Zero the reg */ - - addi r3, r3, 4 /* Point to MB2CF reg */ - mtdcr memcfga, r3 /* Set the address */ - mtdcr memcfgd, r4 /* Zero the reg */ - - addi r3, r3, 4 /* Point to MB3CF reg */ - mtdcr memcfga, r3 /* Set the address */ - mtdcr memcfgd, r4 /* Zero the reg */ - - /******************************************************************** - * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. - * To set the appropriate timings, we assume sdram is - * 100MHz (pc100 compliant). - *******************************************************************/ - - /* - * Set up SDTR1 - */ - addi r3, 0, mem_sdtr1 - mtdcr memcfga, r3 - addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */ - ori r4, r4, 0x400D - mtdcr memcfgd, r4 - - /* - * Set RTR - */ - addi r3, 0, mem_rtr - mtdcr memcfga, r3 - addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */ - mtdcr memcfgd, r4 - - /******************************************************************** - * Delay to ensure 200usec have elapsed since reset. Assume worst - * case that the core is running 200Mhz: - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *******************************************************************/ - addis r3, 0, 0x0000 - ori r3, r3, 0xA000 /* Wait 200us from reset */ - mtctr r3 -..spinlp2: - bdnz ..spinlp2 /* spin loop */ - - /******************************************************************** - * Set memory controller options reg, MCOPT1. - *******************************************************************/ - addi r3, 0, mem_mcopt1 - mtdcr memcfga, r3 - addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */ - ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */ - mtdcr memcfgd, r4 /* EMDULR=1 */ - -..sdri_done: - /* restore and return */ - lwz r0, +12(r1) /* Get saved link register */ - addi r1, r1, +8 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ -.Lfe1: .size sdram_init,.Lfe1-sdram_init -/* end sdram_init() */ diff --git a/board/w7o/post1.S b/board/w7o/post1.S deleted file mode 100644 index 21d206e..0000000 --- a/board/w7o/post1.S +++ /dev/null @@ -1,742 +0,0 @@ -/* - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net - * and - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * Description: - * Routine to exercise memory for the bringing up of our boards. - */ -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#include - -#include "errors.h" - -#define _ASMLANGUAGE - - .globl test_sdram - .globl test_led - .globl log_stat - .globl log_warn - .globl log_err - .globl temp_uart_init - .globl post_puts - .globl disp_hex - -/***************************************************** -******* Text Strings for low level printing ****** -******* In section got2 ******* -*****************************************************/ - -/* - * Define the text strings for errors and warnings. - * Switch to .data section. - */ - .section ".data" -err_str: .asciz "*** POST ERROR = " -warn_str: .asciz "*** POST WARNING = " -end_str: .asciz "\r\n" - -/* - * Enter the labels in Global Entry Table (GOT). - * Switch to .got2 section. - */ - START_GOT - GOT_ENTRY(err_str) - GOT_ENTRY(warn_str) - GOT_ENTRY(end_str) - END_GOT - -/* - * Switch back to .text section. - */ - .text - -/**************************************** - **************************************** - ******** LED register test ******** - **************************************** - ***************************************/ -test_led: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r4, +8(r1) /* save R4 */ - - WATCHDOG_RESET /* Reset the watchdog */ - - addi r3, 0, ERR_FF /* first test value is ffff */ - addi r4, r3, 0 /* save copy of pattern */ - bl set_led /* store first test value */ - bl get_led /* read it back */ - xor. r4, r4, r3 /* compare to original */ -#if defined(CONFIG_W7OLMC) - andi. r4, r4, 0x00ff /* lmc has 8 bits */ -#else - andi. r4, r4, 0xffff /* lmg has 16 bits */ -#endif - beq LED2 /* next test */ - addi r3, 0, ERR_LED /* error code = 1 */ - bl log_err /* display error and halt */ -LED2: addi r3, 0, ERR_00 /* 2nd test value is 0000 */ - addi r4, r3, 0 /* save copy of pattern */ - bl set_led /* store first test value */ - bl get_led /* read it back */ - xor. r4, r4, r3 /* compare to original */ -#if defined(CONFIG_W7OLMC) - andi. r4, r4, 0x00ff /* lmc has 8 bits */ -#else - andi. r4, r4, 0xffff /* lmg has 16 bits */ -#endif - beq LED3 /* next test */ - addi r3, 0, ERR_LED /* error code = 1 */ - bl log_err /* display error and halt */ - -LED3: /* restore stack and return */ - lwz r0, +16(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - lwz r4, +8(r1) /* restore r4 */ - addi r1, r1, +12 /* Remove frame from stack */ - blr /* Return to calling function */ - -/**************************************** - **************************************** - ******** SDRAM TESTS ******** - **************************************** - ***************************************/ -test_sdram: - /* called with mem size in r3 */ - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -16(r1) /* Save back chain and move SP */ - stw r0, +20(r1) /* Save link register */ - stmw r30, +8(r1) /* save R30,R31 */ - /* r30 is log2(mem size) */ - /* r31 is mem size */ - - /* take log2 of total mem size */ - addi r31, r3, 0 /* save total mem size */ - addi r30, 0, 0 /* clear r30 */ -l2_loop: - srwi. r31, r31, 1 /* shift right 1 */ - addi r30, r30, 1 /* count shifts */ - bne l2_loop /* loop till done */ - addi r30, r30, -1 /* correct for over count */ - addi r31, r3, 0 /* save original size */ - - /* now kick the dog and test the mem */ - WATCHDOG_RESET /* Reset the watchdog */ - bl Data_Buster /* test crossed/shorted data lines */ - addi r3, r30, 0 /* get log2(memsize) */ - addi r4, r31, 0 /* get memsize */ - bl Ghost_Buster /* test crossed/shorted addr lines */ - addi r3, r31, 0 /* get mem size */ - bl Bit_Buster /* check for bad internal bits */ - - /* restore stack and return */ - lmw r30, +8(r1) /* Restore r30, r31 */ - lwz r0, +20(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - addi r1, r1, +16 /* Remove frame from stack */ - blr /* Return to calling function */ - - -/**************************************** - ******** sdram data bus test ******** - ***************************************/ -Data_Buster: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -24(r1) /* Save back chain and move SP */ - stw r0, +28(r1) /* Save link register */ - stmw r28, 8(r1) /* save r28 - r31 on stack */ - /* r31 i/o register */ - /* r30 sdram base address */ - /* r29 5555 syndrom */ - /* r28 aaaa syndrom */ - - /* set up led register for this test */ - addi r3, 0, ERR_RAMG /* set led code to 1 */ - bl log_stat /* store test value */ - /* now test the dram data bus */ - xor r30, r30, r30 /* load r30 with base addr of sdram */ - addis r31, 0, 0x5555 /* load r31 with test value */ - ori r31, r31, 0x5555 - stw r31,0(r30) /* sto the value */ - lwz r29,0(r30) /* read it back */ - xor r29,r31,r29 /* compare it to original */ - addis r31, 0, 0xaaaa /* load r31 with test value */ - ori r31, r31, 0xaaaa - stw r31,0(r30) /* sto the value */ - lwz r28,0(r30) /* read it back */ - xor r28,r31,r28 /* compare it to original */ - or r3,r28,r29 /* or together both error terms */ - /* - * Now that we have the error bits, - * we have to decide which part they are in. - */ - bl get_idx /* r5 is now index to error */ - addi r3, r3, ERR_RAMG - cmpwi r3, ERR_RAMG /* check for errors */ - beq db_done /* skip if no errors */ - bl log_err /* log the error */ - -db_done: - lmw r28, 8(r1) /* restore r28 - r31 from stack */ - lwz r0, +28(r1) /* Get saved link register */ - addi r1, r1, +24 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - - -/**************************************************** - ******** test for address ghosting in dram ******** - ***************************************************/ - -Ghost_Buster: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -36(r1) /* Save back chain and move SP */ - stw r0, +40(r1) /* Save link register */ - stmw r25, 8(r1) /* save r25 - r31 on stack */ - /* r31 = scratch register */ - /* r30 is main referance loop counter, - 0 to 23 */ - /* r29 is ghost loop count, 0 to 22 */ - /* r28 is referance address */ - /* r27 is ghost address */ - /* r26 is log2 (mem size) = - number of byte addr bits */ - /* r25 is mem size */ - - /* save the log2(mem size) and mem size */ - addi r26, r3, 0 /* r26 is number of byte addr bits */ - addi r25, r4, 0 /* r25 is mem size in bytes */ - - /* set the leds for address ghost test */ - addi r3, 0, ERR_ADDG - bl set_led - - /* first fill memory with zeros */ - srwi r31, r25, 2 /* convert bytes to longs */ - mtctr r31 /* setup byte counter */ - addi r28, 0, 0 /* start at address at 0 */ - addi r31, 0, 0 /* data value = 0 */ -clr_loop: - stw r31, 0(r28) /* Store zero value */ - addi r28, r28, 4 /* Increment to next word */ - andi. r27, r28, 0xffff /* check for 2^16 loops */ - bne clr_skip /* if not there, then skip */ - WATCHDOG_RESET /* kick the dog every now and then */ -clr_skip: - bdnz clr_loop /* Round and round... */ - - /* now do main test */ - addi r30, 0, 0 /* start referance counter at 0 */ -outside: - /* - * Calculate the referance address - * the referance address is calculated by setting the (r30-1) - * bit of the base address - * when r30=0, the referance address is the base address. - * thus the sequence 0,1,2,4,8,..,2^(n-1) - * setting the bit is done with the following shift functions. - */ - WATCHDOG_RESET /* Reset the watchdog */ - - addi r31, 0, 1 /* r31 = 1 */ - slw r28, r31, r30 /* set bit coresponding to loop cnt */ - srwi r28, r28, 1 /* then shift it right one so */ - /* we start at location 0 */ - /* fill referance address with Fs */ - addi r31, 0, 0x00ff /* r31 = one byte of set bits */ - stb r31,0(r28) /* save ff in referance address */ - - /* ghost (inner) loop, now check all posible ghosted addresses */ - addi r29, 0, 0 /* start ghosted loop counter at 0 */ -inside: - /* - * Calculate the ghost address by flipping one - * bit of referance address. This gives the - * sequence 1,2,4,8,...,2^(n-1) - */ - addi r31, 0, 1 /* r31 = 1 */ - slw r27, r31, r29 /* set bit coresponding to loop cnt */ - xor r27, r28, r27 /* ghost address = ref addr with - bit flipped*/ - - /* now check for ghosting */ - lbz r31,0(r27) /* get content of ghost addr */ - cmpwi r31, 0 /* compare read value to 0 */ - bne Casper /* we found a ghost! */ - - /* now close ghost ( inner ) loop */ - addi r29, r29, 1 /* increment inner loop counter */ - cmpw r29, r26 /* check for last inner loop */ - blt inside /* do more inner loops */ - - /* now close referance ( outer ) loop */ - addi r31, 0, 0 /* r31 = zero */ - stb r31, 0(28) /* zero out the altered address loc. */ - /* - * Increment and check for end, count is zero based. - * With the ble, this gives us one more loops than - * address bits for sequence 0,1,2,4,8,...2^(n-1) - */ - addi r30, r30, 1 /* increment outer loop counter */ - cmpw r30, r26 /* check for last inner loop */ - ble outside /* do more outer loops */ - - /* were done, lets go home */ - b gb_done -Casper: /* we found a ghost !! */ - addi r3, 0, ERR_ADDF /* get indexed error message */ - bl log_err /* log error led error code */ -gb_done: /* pack your bags, and go home */ - lmw r25, 8(r1) /* restore r25 - r31 from stack */ - lwz r0, +40(r1) /* Get saved link register */ - addi r1, r1, +36 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - -/**************************************************** - ******** SDRAM data fill tests ********** - ***************************************************/ -Bit_Buster: - /* called with mem size in r3 */ - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -16(r1) /* Save back chain and move SP */ - stw r0, +20(r1) /* Save link register */ - stw r4, +8(r1) /* save R4 */ - stw r5, +12(r1) /* save r5 */ - - addis r5, r3, 0 /* save mem size */ - - /* Test 55555555 */ - addi r3, 0, ERR_R55G /* set up error code in case we fail */ - bl log_stat /* store test value */ - addis r4, 0, 0x5555 - ori r4, r4, 0x5555 - bl fill_test - - /* Test aaaaaaaa */ - addi r3, 0, ERR_RAAG /* set up error code in case we fail */ - bl log_stat /* store test value */ - addis r4, 0, 0xAAAA - ori r4, r4, 0xAAAA - bl fill_test - - /* Test 00000000 */ - addi r3, 0, ERR_R00G /* set up error code in case we fail */ - bl log_stat /* store test value */ - addis r4, 0, 0 - ori r4, r4, 0 - bl fill_test - - /* restore stack and return */ - lwz r5, +12(r1) /* restore r4 */ - lwz r4, +8(r1) /* restore r4 */ - lwz r0, +20(r1) /* Get saved link register */ - addi r1, r1, +16 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - - -/**************************************************** - ******** fill test ******** - ***************************************************/ -/* tests memory by filling with value, and reading back */ -/* r5 = Size of memory in bytes */ -/* r4 = Value to write */ -/* r3 = Error code */ -fill_test: - mflr r0 /* Get link register */ - stwu r1, -32(r1) /* Save back chain and move SP */ - stw r0, +36(r1) /* Save link register */ - stmw r27, 8(r1) /* save r27 - r31 on stack */ - /* r31 - scratch register */ - /* r30 - memory address */ - mr r27, r3 - mr r28, r4 - mr r29, r5 - - WATCHDOG_RESET /* Reset the watchdog */ - - /* first fill memory with Value */ - srawi r31, r29, 2 /* convert bytes to longs */ - mtctr r31 /* setup counter */ - addi r30, 0, 0 /* Make r30 = addr 0 */ -ft_0: stw r28, 0(r30) /* Store value */ - addi r30, r30, 4 /* Increment to next word */ - andi. r31, r30, 0xffff /* check for 2^16 loops */ - bne ft_0a /* if not there, then skip */ - WATCHDOG_RESET /* kick the dog every now and then */ -ft_0a: bdnz ft_0 /* Round and round... */ - - WATCHDOG_RESET /* Reset the watchdog */ - - /* Now confirm Value is in memory */ - srawi r31, r29, 2 /* convert bytes to longs */ - mtctr r31 /* setup counter */ - addi r30, 0, 0 /* Make r30 = addr 0 */ -ft_1: lwz r31, 0(r30) /* get value from memory */ - xor. r31, r31, r28 /* Writen = Read ? */ - bne ft_err /* If bad, than halt */ - addi r30, r30, 4 /* Increment to next word */ - andi. r31, r30, 0xffff /* check for 2^16 loops*/ - bne ft_1a /* if not there, then skip */ - WATCHDOG_RESET /* kick the dog every now and then */ -ft_1a: bdnz ft_1 /* Round and round... */ - - WATCHDOG_RESET /* Reset the watchdog */ - - b fill_done /* restore and return */ - -ft_err: addi r29, r27, 0 /* save current led code */ - addi r27, r31, 0 /* get pattern in r27 */ - bl get_idx /* get index from r27 */ - add r27, r27, r29 /* add index to old led code */ - bl log_err /* output led err code, halt CPU */ - -fill_done: - lmw r27, 8(r1) /* restore r27 - r31 from stack */ - lwz r0, +36(r1) /* Get saved link register */ - addi r1, r1, +32 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - - -/**************************************************** - ******* get error index from r3 pattern ******** - ***************************************************/ -get_idx: /* r3 = (MSW(r3) !=0)*2 + - (LSW(r3) !=0) */ - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r4, +8(r1) /* save R4 */ - - andi. r4, r3, 0xffff /* check for lower bits */ - beq gi2 /* skip if no bits set */ - andis. r4, r3, 0xffff /* check for upper bits */ - beq gi3 /* skip if no bits set */ - addi r3, 0, 3 /* both upper and lower bits set */ - b gi_done -gi2: andis. r4, r3, 0xffff /* check for upper bits*/ - beq gi4 /* skip if no bits set */ - addi r3, 0, 2 /* only upper bits set */ - b gi_done -gi3: addi r3, 0, 1 /* only lower bits set */ - b gi_done -gi4: addi r3, 0, 0 /* no bits set */ -gi_done: - /* restore stack and return */ - lwz r0, +16(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - lwz r4, +8(r1) /* restore r4 */ - addi r1, r1, +12 /* Remove frame from stack */ - blr /* Return to calling function */ - -/**************************************************** - ******** set LED to R5 and hang ******** - ***************************************************/ -log_stat: /* output a led code and continue */ -set_led: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r4, +8(r1) /* save R4 */ - - addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */ -#if defined(CONFIG_W7OLMG) /* only on gateway, invert outputs */ - xori r3,r3, 0xffff /* complement led code, active low */ - sth r3, 0(r4) /* store first test value */ - xori r3,r3, 0xffff /* complement led code, active low */ -#else /* if not gateway, then don't invert */ - sth r3, 0(r4) /* store first test value */ -#endif - - /* restore stack and return */ - lwz r0, +16(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - lwz r4, +8(r1) /* restore r4 */ - addi r1, r1, +12 /* Remove frame from stack */ - blr /* Return to calling function */ - -get_led: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r4, +8(r1) /* save R4 */ - - addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */ - lhz r3, 0(r4) /* store first test value */ -#if defined(CONFIG_W7OLMG) /* only on gateway, invert inputs */ - xori r3,r3, 0xffff /* complement led code, active low */ -#endif - - /* restore stack and return */ - lwz r0, +16(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - lwz r4, +8(r1) /* restore r4 */ - addi r1, r1, +12 /* Remove frame from stack */ - blr /* Return to calling function */ - -log_err: /* output the error and hang the board ( for now ) */ - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r3, +8(r1) /* save a copy of error code */ - bl set_led /* set the led pattern */ - GET_GOT /* get GOT address in r14 */ - lwz r3,GOT(err_str) /* get address of string */ - bl post_puts /* output the warning string */ - lwz r3, +8(r1) /* get error code */ - addi r4, 0, 2 /* set disp length to 2 nibbles */ - bl disp_hex /* output the error code */ - lwz r3,GOT(end_str) /* get address of string */ - bl post_puts /* output the warning string */ -halt: - b halt /* hang */ - - /* restore stack and return */ - lwz r0, +16(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - addi r1, r1, +12 /* Remove frame from stack */ - blr /* Return to calling function */ - -log_warn: /* output a warning, then continue with operations */ - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -16(r1) /* Save back chain and move SP */ - stw r0, +20(r1) /* Save link register */ - stw r3, +8(r1) /* save a copy of error code */ - stw r14, +12(r1) /* save a copy of r14 (used by GOT) */ - - bl set_led /* set the led pattern */ - GET_GOT /* get GOT address in r14 */ - lwz r3,GOT(warn_str) /* get address of string */ - bl post_puts /* output the warning string */ - lwz r3, +8(r1) /* get error code */ - addi r4, 0, 2 /* set disp length to 2 nibbles */ - bl disp_hex /* output the error code */ - lwz r3,GOT(end_str) /* get address of string */ - bl post_puts /* output the warning string */ - - addis r3, 0, 64 /* has a long delay */ - mtctr r3 -log_2: - WATCHDOG_RESET /* this keeps dog from barking, */ - /* and takes time */ - bdnz log_2 /* loop till time expires */ - - /* restore stack and return */ - lwz r0, +20(r1) /* Get saved link register */ - lwz r14, +12(r1) /* restore r14 */ - mtlr r0 /* Restore link register */ - addi r1, r1, +16 /* Remove frame from stack */ - blr /* Return to calling function */ - -/******************************************************************* - * temp_uart_init - * Temporary UART initialization routine - * Sets up UART0 to run at 9600N81 off of the internal clock. - * R3-R4 are used. - ******************************************************************/ -temp_uart_init: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save link register */ - - addis r3, 0, 0xef60 - ori r3, r3, 0x0303 /* r3 = UART0_LCR */ - addi r4, 0, 0x83 /* n81 format, divisor regs enabled */ - stb r4, 0(r3) - - /* set baud rate to use internal clock, - baud = (200e6/16)/31/42 = 9600 */ - - addis r3, 0, 0xef60 /* Address of baud divisor reg */ - ori r3, r3, 0x0300 /* UART0_DLM */ - addi r4, 0, +42 /* uart baud divisor LSB = 93 */ - stb r4, 0(r3) /* baud = (200 /16)/14/93 */ - - addi r3, r3, 0x0001 /* uart baud divisor addr */ - addi r4, 0, 0 - stb r4, 0(r3) /* Divisor Latch MSB = 0 */ - - addis r3, 0, 0xef60 - ori r3, r3, 0x0303 /* r3 = UART0_LCR */ - addi r4, 0, 0x03 /* n81 format, tx/rx regs enabled */ - stb r4, 0(r3) - - /* output a few line feeds */ - addi r3, 0, '\n' /* load line feed */ - bl post_putc /* output the char */ - addi r3, 0, '\n' /* load line feed */ - bl post_putc /* output the char */ - - /* restore stack and return */ - lwz r0, +12(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - addi r1, r1, +8 /* Remove frame from stack */ - blr /* Return to calling function */ - -/********************************************************************** - ** post_putc - ** outputs charactor in R3 - ** r3 returns the error code ( -1 if there is an error ) - *********************************************************************/ - -post_putc: - - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -20(r1) /* Save back chain and move SP */ - stw r0, +24(r1) /* Save link register */ - stmw r29, 8(r1) /* save r29 - r31 on stack - r31 - uart base address - r30 - delay counter - r29 - scratch reg */ - - addis r31, 0, 0xef60 /* Point to uart base */ - ori r31, r31, 0x0300 - addis r30, 0, 152 /* Load about 10,000,000 ticks. */ -pputc_lp: - lbz r29, 5(r31) /* Read Line Status Register */ - andi. r29, r29, 0x20 /* Check THRE status */ - bne thre_set /* Branch if FIFO empty */ - addic. r30, r30, -1 /* Decrement and check if empty. */ - bne pputc_lp /* Try, try again */ - addi r3, 0, -1 /* Load error code for timeout */ - b pputc_done /* Bail out with error code set */ -thre_set: - stb r3, 0(r31) /* Store character to UART */ - addi r3, 0, 0 /* clear error code */ -pputc_done: - lmw r29, 8(r1) /*restore r29 - r31 from stack */ - lwz r0, +24(r1) /* Get saved link register */ - addi r1, r1, +20 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - - -/**************************************************************** - post_puts - Accepts a null-terminated string pointed to by R3 - Outputs to the serial port until 0x00 is found. - r3 returns the error code ( -1 if there is an error ) -*****************************************************************/ -post_puts: - - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -12(r1) /* Save back chain and move SP */ - stw r0, +16(r1) /* Save link register */ - stw r31, 8(r1) /* save r31 - char pointer */ - - addi r31, r3, 0 /* move pointer to R31 */ -pputs_nxt: - lbz r3, 0(r31) /* Get next character */ - addic. r3, r3, 0 /* Check for zero */ - beq pputs_term /* bail out if zero */ - bl post_putc /* output the char */ - addic. r3, r3, 0 /* check for error */ - bne pputs_err - addi r31, r31, 1 /* point to next char */ - b pputs_nxt /* loop till term */ -pputs_err: - addi r3, 0, -1 /* set error code */ - b pputs_end /* were outa here */ -pputs_term: - addi r3, 0, 1 /* set success code */ - /* restore stack and return */ -pputs_end: - lwz r31, 8(r1) /* restore r27 - r31 from stack */ - lwz r0, +16(r1) /* Get saved link register */ - addi r1, r1, +12 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ - - -/******************************************************************** - ***** disp_hex - ***** Routine to display a hex value from a register. - ***** R3 is value to display - ***** R4 is number of nibbles to display ie 2 for byte 8 for (long)word - ***** Returns -1 in R3 if there is an error ( ie serial port hangs ) - ***** Returns 0 in R3 if no error - *******************************************************************/ -disp_hex: - /* save the return info on stack */ - mflr r0 /* Get link register */ - stwu r1, -16(r1) /* Save back chain and move SP */ - stw r0, +20(r1) /* Save link register */ - stmw r30, 8(r1) /* save r30 - r31 on stack */ - /* r31 output char */ - /* r30 uart base address */ - addi r30, 0, 8 /* Go through 8 nibbles. */ - addi r31, r3, 0 -pputh_nxt: - rlwinm r31, r31, 4, 0, 31 /* Rotate next nibble into position */ - andi. r3, r31, 0x0f /* Get nibble. */ - addi r3, r3, 0x30 /* Add zero's ASCII code. */ - cmpwi r3, 0x03a - blt pputh_out - addi r3, r3, 0x07 /* 0x27 for lower case. */ -pputh_out: - cmpw r30, r4 - bgt pputh_skip - bl post_putc - addic. r3, r3, 0 /* check for error */ - bne pputh_err -pputh_skip: - addic. r30, r30, -1 - bne pputh_nxt - xor r3, r3, r3 /* Clear error code */ - b pputh_done -pputh_err: - addi r3, 0, -1 /* set error code */ -pputh_done: - /* restore stack and return */ - lmw r30, 8(r1) /* restore r30 - r31 from stack */ - lwz r0, +20(r1) /* Get saved link register */ - addi r1, r1, +16 /* Remove frame from stack */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ diff --git a/board/w7o/post2.c b/board/w7o/post2.c deleted file mode 100644 index e590128..0000000 --- a/board/w7o/post2.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net - * and - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "errors.h" -#include "dtt.h" - -#if defined(CONFIG_RTC_M48T35A) -void rtctest(void) -{ - volatile uchar *tchar = (uchar*)(CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 9); - struct rtc_time tmp; - - /* set up led code for RTC tests */ - log_stat(ERR_RTCG); - - /* - * Do RTC battery test. The first write after power up - * fails if battery is low. - */ - *tchar = 0xaa; - if ((*tchar ^ 0xaa) != 0x0) log_warn(ERR_RTCBAT); - *tchar = 0x55; /* Reset test address */ - - /* - * Now lets check the validity of the values in the RTC. - */ - rtc_get(&tmp); - if ((tmp.tm_sec < 0) | (tmp.tm_sec > 59) | - (tmp.tm_min < 0) | (tmp.tm_min > 59) | - (tmp.tm_hour < 0) | (tmp.tm_hour > 23) | - (tmp.tm_mday < 1 ) | (tmp.tm_mday > 31) | - (tmp.tm_mon < 1 ) | (tmp.tm_mon > 12) | - (tmp.tm_year < 2000) | (tmp.tm_year > 2500) | - (tmp.tm_wday < 1 ) | (tmp.tm_wday > 7)) { - log_warn(ERR_RTCTIM); - rtc_reset(); - } - - /* - * Now lets do a check to see if the NV RAM is there. - */ - *tchar = 0xaa; - if ((*tchar ^ 0xaa) != 0x0) log_err(ERR_RTCVAL); - *tchar = 0x55; /* Reset test address */ - -} /* rtctest() */ -#endif /* CONFIG_RTC_M48T35A */ - - -#ifdef CONFIG_DTT_LM75 -int dtt_test(int sensor) -{ - short temp, trip, hyst; - - /* get values */ - temp = dtt_read(sensor, DTT_READ_TEMP) / 256; - trip = dtt_read(sensor, DTT_TEMP_SET) / 256; - hyst = dtt_read(sensor, DTT_TEMP_HYST) / 256; - - /* check values */ - if ((hyst != (CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS)) || - (trip != CFG_DTT_MAX_TEMP) || - (temp < CFG_DTT_LOW_TEMP) || (temp > CFG_DTT_MAX_TEMP)) - return 1; - - return 0; -} /* dtt_test() */ -#endif /* CONFIG_DTT_LM75 */ - -/*****************************************/ - -void post2(void) -{ -#if defined(CONFIG_RTC_M48T35A) - rtctest(); -#endif /* CONFIG_RTC_M48T35A */ - -#ifdef CONFIG_DTT_LM75 - log_stat(ERR_TempG); - if(dtt_test(2) != 0) log_warn(ERR_Ttest0); - if(dtt_test(4) != 0) log_warn(ERR_Ttest1); -#endif /* CONFIG_DTT_LM75 */ -} /* post2() */ diff --git a/board/w7o/u-boot.lds b/board/w7o/u-boot.lds deleted file mode 100644 index 7e3e15d..0000000 --- a/board/w7o/u-boot.lds +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/ppc4xx/start.o (.text) - board/w7o/init.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug deleted file mode 100644 index a0c72c9..0000000 --- a/board/w7o/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/w7o/vpd.c b/board/w7o/vpd.c deleted file mode 100644 index 2ce1568..0000000 --- a/board/w7o/vpd.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if defined(VXWORKS) -# include -# include -# define CFG_DEF_EEPROM_ADDR 0xa0 -extern char iicReadByte( char, char ); -extern ulong_t crc32( unsigned char *, unsigned long ); -#else -#include -#endif - -#include "vpd.h" - -/* - * vpd_reader() - reads VPD data from I2C EEPROMS. - * returns pointer to buffer or NULL. - */ -static unsigned char * -vpd_reader(unsigned char *buf, unsigned dev_addr, unsigned off, unsigned count) -{ - unsigned offset = off; /* Calculated offset */ - - /* - * The main board EEPROM contains - * SDRAM SPD in the first 128 bytes, - * so skew the offset. - */ - if (dev_addr == CFG_DEF_EEPROM_ADDR) - offset += SDRAM_SPD_DATA_SIZE; - - /* Try to read the I2C EEPROM */ -#if defined(VXWORKS) - { - int i; - for( i = 0; i < count; ++i ) { - buf[ i ] = iicReadByte( dev_addr, offset+i ); - } - } -#else - if (eeprom_read(dev_addr, offset, buf, count)) { - printf("Failed to read %d bytes from VPD EEPROM 0x%x @ 0x%x\n", - count, dev_addr, offset); - return NULL; - } -#endif - - return buf; -} /* vpd_reader() */ - - -/* - * vpd_get_packet() - returns next VPD packet or NULL. - */ -static vpd_packet_t *vpd_get_packet(vpd_packet_t *vpd_packet) -{ - vpd_packet_t *packet = vpd_packet; - - if (packet != NULL) { - if (packet->identifier == VPD_PID_TERM) - return NULL; - else - packet = (vpd_packet_t *)((char *)packet + packet->size + 2); - } - - return packet; -} /* vpd_get_packet() */ - - -/* - * vpd_find_packet() - Locates and returns the specified - * VPD packet or NULL on error. - */ -static vpd_packet_t *vpd_find_packet(vpd_t *vpd, unsigned char ident) -{ - vpd_packet_t *packet = (vpd_packet_t *)&vpd->packets; - - /* Guaranteed illegal */ - if (ident == VPD_PID_GI) - return NULL; - - /* Scan tuples looking for a match */ - while ((packet->identifier != ident) && - (packet->identifier != VPD_PID_TERM)) - packet = vpd_get_packet(packet); - - /* Did we find it? */ - if ((packet->identifier) && (packet->identifier != ident)) - return NULL; - return packet; -} - - -/* - * vpd_is_valid() - Validates contents of VPD data - * in I2C EEPROM. Returns 1 for - * success or 0 for failure. - */ -static int vpd_is_valid(unsigned dev_addr, unsigned char *buf) -{ - unsigned num_bytes; - vpd_packet_t *packet; - vpd_t *vpd = (vpd_t *)buf; - unsigned short stored_crc16, calc_crc16 = 0xffff; - - /* Check Eyecatcher */ - if (strncmp((char *)(vpd->header.eyecatcher), VPD_EYECATCHER, VPD_EYE_SIZE) != 0) { - unsigned offset = 0; - if (dev_addr == CFG_DEF_EEPROM_ADDR) - offset += SDRAM_SPD_DATA_SIZE; - printf("Error: VPD EEPROM 0x%x corrupt @ 0x%x\n", dev_addr, offset); - - return 0; - } - - /* Check Length */ - if (vpd->header.size> VPD_MAX_EEPROM_SIZE) { - printf("Error: VPD EEPROM 0x%x contains bad size 0x%x\n", - dev_addr, vpd->header.size); - return 0; - } - - /* Now find the termination packet */ - if ((packet = vpd_find_packet(vpd, VPD_PID_TERM)) == NULL) { - printf("Error: VPD EEPROM 0x%x missing termination packet\n", - dev_addr); - return 0; - } - - /* Calculate data size */ - num_bytes = (unsigned long)((unsigned char *)packet - - (unsigned char *)vpd + sizeof(vpd_packet_t)); - - /* Find stored CRC and clear it */ - if ((packet = vpd_find_packet(vpd, VPD_PID_CRC)) == NULL) { - printf("Error: VPD EEPROM 0x%x missing CRC\n", dev_addr); - return 0; - } - stored_crc16 = *((ushort *)packet->data); - *(ushort *)packet->data = 0; - - /* OK, lets calculate the CRC and check it */ -#if defined(VXWORKS) - calc_crc16 = (0xffff & crc32(buf, num_bytes)); -#else - calc_crc16 = (0xffff & crc32(0, buf, num_bytes)); -#endif - *(ushort *)packet->data = stored_crc16; /* Now restore the CRC */ - if (stored_crc16 != calc_crc16) { - printf("Error: VPD EEPROM 0x%x has bad CRC 0x%x\n", - dev_addr, stored_crc16); - return 0; - } - - return 1; -} /* vpd_is_valid() */ - - -/* - * size_ok() - Check to see if packet size matches - * size of data we want. Returns 1 for - * good match or 0 for failure. - */ -static int size_ok(vpd_packet_t *packet, unsigned long size) -{ - if (packet->size != size) { - printf("VPD Packet 0x%x corrupt.\n", packet->identifier); - return 0; - } - return 1; -} /* size_ok() */ - - -/* - * strlen_ok() - Check to see if packet size matches - * strlen of the string we want to populate. - * Returns 1 for valid length or 0 for failure. - */ -static int strlen_ok(vpd_packet_t *packet, unsigned long length) -{ - if (packet->size >= length) { - printf("VPD Packet 0x%x corrupt.\n", packet->identifier); - return 0; - } - return 1; -} /* strlen_ok() */ - - -/* - * get_vpd_data() - populates the passed VPD structure 'vpdInfo' - * with data obtained from the specified - * I2C EEPROM 'dev_addr'. Returns 0 for - * success or 1 for failure. - */ -int vpd_get_data(unsigned char dev_addr, VPD *vpdInfo) -{ - unsigned char buf[VPD_EEPROM_SIZE]; - vpd_t *vpd = (vpd_t *)buf; - vpd_packet_t *packet; - - if (vpdInfo == NULL) - return 1; - - /* - * Fill vpdInfo with 0s to blank out - * unused fields, fill vpdInfo->ethAddrs - * with all 0xffs so that other's code can - * determine how many real Ethernet addresses - * there are. OUIs starting with 0xff are - * broadcast addresses, and would never be - * permantely stored. - */ - memset((void *)vpdInfo, 0, sizeof(VPD)); - memset((void *)&vpdInfo->ethAddrs, 0xff, sizeof(vpdInfo->ethAddrs)); - vpdInfo->_devAddr = dev_addr; - - /* Read the minimum size first */ - if (vpd_reader(buf, dev_addr, 0, VPD_EEPROM_SIZE) == NULL) { - return 1; - } - - /* Check validity of VPD data */ - if (!vpd_is_valid(dev_addr, buf)) { - printf("VPD Data is INVALID!\n"); - return 1; - } - - /* - * Walk all the packets and populate - * the VPD info structure. - */ - packet = (vpd_packet_t *)&vpd->packets; - do { - switch (packet->identifier) { - case VPD_PID_GI: - printf("Error: Illegal VPD value\n"); - break; - case VPD_PID_PID: - if (strlen_ok(packet, MAX_PROD_ID)) { - strncpy(vpdInfo->productId, - (char *)(packet->data), packet->size); - } - break; - case VPD_PID_REV: - if (size_ok(packet, sizeof(char))) - vpdInfo->revisionId = *packet->data; - break; - case VPD_PID_SN: - if (size_ok(packet, sizeof(unsigned long))) { - vpdInfo->serialNum = - *(unsigned long *)packet->data; - } - break; - case VPD_PID_MANID: - if (size_ok(packet, sizeof(unsigned char))) - vpdInfo->manuID = *packet->data; - break; - case VPD_PID_PCO: - if (size_ok(packet, sizeof(unsigned long))) { - vpdInfo->configOpt = - *(unsigned long *)packet->data; - } - break; - case VPD_PID_SYSCLK: - if (size_ok(packet, sizeof(unsigned long))) - vpdInfo->sysClk = *(unsigned long *)packet->data; - break; - case VPD_PID_SERCLK: - if (size_ok(packet, sizeof(unsigned long))) - vpdInfo->serClk = *(unsigned long *)packet->data; - break; - case VPD_PID_FLASH: - if (size_ok(packet, 9)) { /* XXX - hardcoded, - padding in struct */ - memcpy(&vpdInfo->flashCfg, packet->data, 9); - } - break; - case VPD_PID_ETHADDR: - memcpy(vpdInfo->ethAddrs, packet->data, packet->size); - break; - case VPD_PID_POTS: - if (size_ok(packet, sizeof(char))) - vpdInfo->numPOTS = (unsigned)*packet->data; - break; - case VPD_PID_DS1: - if (size_ok(packet, sizeof(char))) - vpdInfo->numDS1 = (unsigned)*packet->data; - case VPD_PID_GAL: - case VPD_PID_CRC: - case VPD_PID_TERM: - break; - default: - printf("Warning: Found unknown VPD packet ID 0x%x\n", - packet->identifier); - break; - } - } while ((packet = vpd_get_packet(packet))); - - return 0; -} /* end get_vpd_data() */ - - -/* - * vpd_init() - Initialize default VPD environment - */ -int vpd_init(unsigned char dev_addr) -{ - return (0); -} /* vpd_init() */ - - -/* - * vpd_print() - Pretty print the VPD data. - */ -void vpd_print(VPD *vpdInfo) -{ - const char *const sp = ""; - const char *const sfmt = "%4s%-20s: \"%s\"\n"; - const char *const cfmt = "%4s%-20s: '%c'\n"; - const char *const dfmt = "%4s%-20s: %ld\n"; - const char *const hfmt = "%4s%-20s: %08lX\n"; - const char *const dsfmt = "%4s%-20s: %d\n"; - const char *const hsfmt = "%4s%-20s: %04X\n"; - const char *const dhfmt = "%4s%-20s: %ld (%lX)\n"; - - printf("VPD read from I2C device: %02X\n", vpdInfo->_devAddr); - - if (vpdInfo->productId[0]) - printf(sfmt, sp, "Product ID", vpdInfo->productId); - else - printf(sfmt, sp, "Product ID", "UNKNOWN"); - - if (vpdInfo->revisionId) - printf(cfmt, sp, "Revision ID", vpdInfo->revisionId); - - if (vpdInfo->serialNum) - printf(dfmt, sp, "Serial Number", vpdInfo->serialNum); - - if (vpdInfo->manuID) - printf(dfmt, sp, "Manufacture ID", (long)vpdInfo->manuID); - - if (vpdInfo->configOpt) - printf(hfmt, sp, "Configuration", vpdInfo->configOpt); - - if (vpdInfo->sysClk) - printf(dhfmt, sp, "System Clock", vpdInfo->sysClk, vpdInfo->sysClk); - - if (vpdInfo->serClk) - printf(dhfmt, sp, "Serial Clock", vpdInfo->serClk, vpdInfo->serClk); - - if (vpdInfo->numPOTS) - printf(dfmt, sp, "Number of POTS lines", vpdInfo->numPOTS); - - if (vpdInfo->numDS1) - printf(dfmt, sp, "Number of DS1s", vpdInfo->numDS1); - - /* Print Ethernet Addresses */ - if (vpdInfo->ethAddrs[0][0] != 0xff) { - int i, j; - printf("%4sEtherNet Address(es): ", sp); - for (i = 0; i < MAX_ETH_ADDRS; i++) { - if (vpdInfo->ethAddrs[i][0] != 0xff) { - for (j = 0; j < 6; j++) { - printf("%02X", vpdInfo->ethAddrs[i][j]); - if (((j + 1) % 6) != 0) - printf(":"); - else - printf(" "); - } - if (((i + 1) % 3) == 0) printf("\n%24s: ", sp); - } - } - printf("\n"); - } - - if (vpdInfo->flashCfg.mfg && vpdInfo->flashCfg.dev) { - printf("Main Flash Configuration:\n"); - printf(hsfmt, sp, "Manufacture ID", vpdInfo->flashCfg.mfg); - printf(hsfmt, sp, "Device ID", vpdInfo->flashCfg.dev); - printf(dsfmt, sp, "Device Width", vpdInfo->flashCfg.devWidth); - printf(dsfmt, sp, "Num. Devices", vpdInfo->flashCfg.numDevs); - printf(dsfmt, sp, "Num. Columns", vpdInfo->flashCfg.numCols); - printf(dsfmt, sp, "Column Width", vpdInfo->flashCfg.colWidth); - printf(dsfmt, sp, "WE Data Width", vpdInfo->flashCfg.weDataWidth); - } -} /* vpd_print() */ diff --git a/board/w7o/vpd.h b/board/w7o/vpd.h deleted file mode 100644 index 1b71c8d..0000000 --- a/board/w7o/vpd.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _VPD_H_ -#define _VPD_H_ - -/* - * Main Flash Configuration. - */ -typedef struct flashCfg_s { - unsigned short mfg; /* Manufacture ID */ - unsigned short dev; /* Device ID */ - unsigned char devWidth; /* Device Width */ - unsigned char numDevs; /* Number of devices */ - unsigned char numCols; /* Number of columns */ - unsigned char colWidth; /* Width of a column */ - unsigned char weDataWidth; /* Write/Erase Data Width */ -} flashCfg_t; - -/* - * Vital Product Data - VPD - */ -#define MAX_PROD_ID 15 -#define MAX_ETH_ADDRS 10 -typedef unsigned char EthAddr[6]; -typedef struct vpd { - unsigned char _devAddr; /* Device address during read */ - char productId[MAX_PROD_ID]; /* Product ID */ - char revisionId; /* Revision ID as a char */ - unsigned long serialNum; /* Serial number */ - unsigned char manuID; /* Manufact ID - byte int */ - unsigned long configOpt; /* Config Option - bit field */ - unsigned long sysClk; /* System clock in Hertz */ - unsigned long serClk; /* Ext. clock in Hertz */ - flashCfg_t flashCfg; /* Flash configuration */ - unsigned long numPOTS; /* Number of POTS lines */ - unsigned long numDS1; /* Number of DS1 circuits */ - EthAddr ethAddrs[MAX_ETH_ADDRS]; /* Ethernet MAC, 1st = craft */ -} VPD; - - -#define VPD_MAX_EEPROM_SIZE 512 /* Max size VPD EEPROM */ -#define SDRAM_SPD_DATA_SIZE 128 /* Size SPD in VPD EEPROM */ - -/* - * PIDs - Packet Identifiers - */ -#define VPD_PID_GI 0x0 /* Guaranted Illegal */ -#define VPD_PID_PID 0x1 /* Product Identifier */ -#define VPD_PID_REV 0x2 /* Product Revision */ -#define VPD_PID_SN 0x3 /* Serial Number */ -#define VPD_PID_MANID 0x4 /* Manufacture ID */ -#define VPD_PID_PCO 0x5 /* Product configuration */ -#define VPD_PID_SYSCLK 0x6 /* System Clock */ -#define VPD_PID_SERCLK 0x7 /* Ser. Clk. Speed in Hertz */ -#define VPD_PID_CRC 0x8 /* VPD CRC */ -#define VPD_PID_FLASH 0x9 /* Flash Configuration */ -#define VPD_PID_ETHADDR 0xA /* Ethernet Address(es) */ -#define VPD_PID_GAL 0xB /* Galileo Switch Config */ -#define VPD_PID_POTS 0xC /* Number of POTS Lines */ -#define VPD_PID_DS1 0xD /* Number of DS1s */ -#define VPD_PID_TERM 0xFF /* Termination packet */ - -/* - * VPD - Eyecatcher/Magic - */ -#define VPD_EYECATCHER "W7O" -#define VPD_EYE_SIZE 3 -typedef struct vpd_header { - unsigned char eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "W7O" */ - unsigned short size __attribute__((packed)); /* size of EEPROM */ -} vpd_header_t; - - -#define VPD_DATA_SIZE (VPD_MAX_EEPROM_SIZE - SDRAM_SPD_DATA_SIZE - \ - sizeof(vpd_header_t)) -typedef struct vpd_s { - vpd_header_t header; - unsigned char packets[VPD_DATA_SIZE]; -} vpd_t; - -typedef struct vpd_packet { - unsigned char identifier; - unsigned char size; - unsigned char data[1]; -} vpd_packet_t; - -/* - * VPD configOpt bit mask - */ -#define VPD_HAS_BBRAM 0x1 /* Battery backed SRAM */ -#define VPD_HAS_RTC 0x2 /* Battery backed RTC */ -#define VPD_HAS_EXT_SER_CLK 0x4 /* External serial clock */ -#define VPD_HAS_SER_TRANS_1 0x8 /* COM1 transceiver */ -#define VPD_HAS_SER_TRANS_2 0x10 /* COM2 transceiver */ -#define VPD_HAS_CRAFT_PHY 0x20 /* CRAFT Ethernet */ -#define VPD_HAS_DTT_1 0x40 /* I2C Digital therm. #1 */ -#define VPD_HAS_DTT_2 0x80 /* I2C Digital therm. #2 */ -#define VPD_HAS_1000_UP_LASER 0x100 /* GMM - 1000Mbit Uplink */ -#define VPD_HAS_70KM_UP_LASER 0x200 /* CMM - 70KM Uplink laser */ -#define VPD_HAS_2_UPLINKS 0x400 /* CMM - 2 uplink lasers */ -#define VPD_HAS_FPGA 0x800 /* Has 1 or more FPGAs */ -#define VPD_HAS_DFA 0x1000 /* CLM - Has 2 Fiber Inter. */ -#define VPD_HAS_GAL_SWITCH 0x2000 /* GMM - Has a Gal switch */ -#define VPD_HAS_POTS_LINES 0x4000 /* GMM - Has POTS lines */ -#define VPD_HAS_DS1_CHANNELS 0x8000 /* GMM - Has DS1 channels */ -#define VPD_HAS_CABLE_RETURN 0x10000 /* GBM/GBR - Cable ret. path */ - -#define VPD_EEPROM_SIZE (256 - SDRAM_SPD_DATA_SIZE) /* Size EEPROM */ - -extern int vpd_get_data(unsigned char dev_addr, VPD *vpd); -extern void vpd_print(VPD *vpdInfo); - -#endif /* _VPD_H_ */ diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c deleted file mode 100644 index c56c269..0000000 --- a/board/w7o/w7o.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include "w7o.h" -#include - -#include "vpd.h" -#include "errors.h" -#include - -unsigned long get_dram_size (void); - -/* - * Macros to transform values - * into environment strings. - */ -#define XMK_STR(x) #x -#define MK_STR(x) XMK_STR(x) - -/* ------------------------------------------------------------------------- */ - -int board_early_init_f (void) -{ -#if defined(CONFIG_W7OLMG) - /* - * Setup GPIO pins - reset devices. - */ - out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */ - out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */ - out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive - * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive - * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive - * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive - * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive - * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive - */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0, - INT0 highest priority */ - - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - -#elif defined(CONFIG_W7OLMC) - /* - * Setup GPIO pins - */ - out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */ - out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */ - out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive - * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive - * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive - * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive - */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0, - INT0 highest priority */ - - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - -#else /* Unknown */ -# error "Unknown W7O board configuration" -#endif - - WATCHDOG_RESET (); /* Reset the watchdog */ - temp_uart_init (); /* init the uart for debug */ - WATCHDOG_RESET (); /* Reset the watchdog */ - test_led (); /* test the LEDs */ - test_sdram (get_dram_size ()); /* test the dram */ - log_stat (ERR_POST1); /* log status,post1 complete */ - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - VPD vpd; - - puts ("Board: "); - - /* VPD data present in I2C EEPROM */ - if (vpd_get_data (CFG_DEF_EEPROM_ADDR, &vpd) == 0) { - /* - * Known board type. - */ - if (vpd.productId[0] && - ((strncmp (vpd.productId, "GMM", 3) == 0) || - (strncmp (vpd.productId, "CMM", 3) == 0))) { - - /* Output board information on startup */ - printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID); - return (0); - } - } - - puts ("### Unknown HW ID - assuming NOTHING\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - return get_dram_size (); -} - -unsigned long get_dram_size (void) -{ - int tmp, i, regs[4]; - int size = 0; - - /* Get bank Size registers */ - mtdcr (memcfga, mem_mb0cf); /* get bank 0 config reg */ - regs[0] = mfdcr (memcfgd); - - mtdcr (memcfga, mem_mb1cf); /* get bank 1 config reg */ - regs[1] = mfdcr (memcfgd); - - mtdcr (memcfga, mem_mb2cf); /* get bank 2 config reg */ - regs[2] = mfdcr (memcfgd); - - mtdcr (memcfga, mem_mb3cf); /* get bank 3 config reg */ - regs[3] = mfdcr (memcfgd); - - /* compute the size, add each bank if enabled */ - for (i = 0; i < 4; i++) { - if (regs[i] & 0x0001) { /* if enabled, */ - tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */ - tmp = 0x400000 << tmp; /* Size bits X 4MB = size */ - size += tmp; - } - } - - return size; -} - -int misc_init_f (void) -{ - return 0; -} - -static void w7o_env_init (VPD * vpd) -{ - /* - * Read VPD - */ - if (vpd_get_data (CFG_DEF_EEPROM_ADDR, vpd) != 0) - return; - - /* - * Known board type. - */ - if (vpd->productId[0] && - ((strncmp (vpd->productId, "GMM", 3) == 0) || - (strncmp (vpd->productId, "CMM", 3) == 0))) { - char buf[30]; - char *eth; - char *serial = getenv ("serial#"); - char *ethaddr = getenv ("ethaddr"); - - /* Set 'serial#' envvar if serial# isn't set */ - if (!serial) { - sprintf (buf, "%s-%ld", vpd->productId, - vpd->serialNum); - setenv ("serial#", buf); - } - - /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */ - eth = (char *)(vpd->ethAddrs[0]); - if (ethaddr - && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) { - /* Now setup ethaddr */ - sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", - eth[0], eth[1], eth[2], eth[3], eth[4], - eth[5]); - setenv ("ethaddr", buf); - } - } -} /* w7o_env_init() */ - - -int misc_init_r (void) -{ - VPD vpd; /* VPD information */ - -#if defined(CONFIG_W7OLMG) - unsigned long greg; /* GPIO Register */ - - greg = in32 (PPC405GP_GPIO0_OR); - - /* - * XXX - Unreset devices - this should be moved into VxWorks driver code - */ - greg |= 0x41800000L; /* SAM, PHY, Galileo */ - - out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */ -#endif /* CONFIG_W7OLMG */ - - /* - * Initialize W7O environment variables - */ - w7o_env_init (&vpd); - - /* - * Initialize the FPGA(s). - */ - if (init_fpga () == 0) - test_fpga ((unsigned short *) CONFIG_FPGAS_BASE); - - /* More POST testing. */ - post2 (); - - /* Done with hardware initialization and POST. */ - log_stat (ERR_POSTOK); - - /* Call silly, fail safe boot init routine */ - init_fsboot (); - - return (0); -} diff --git a/board/w7o/w7o.h b/board/w7o/w7o.h deleted file mode 100644 index d6f50e2..0000000 --- a/board/w7o/w7o.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _W7O_H_ -#define _W7O_H_ -#include - -/* AMCC 405GP PowerPC GPIO registers */ -#define PPC405GP_GPIO0_OR 0xef600700L /* GPIO Output */ -#define PPC405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */ -#define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */ -#define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */ - -/* AMCC 405GP DCRs */ -#define CPC0_CR0 0xb1 /* Chip control register 0 */ - -/* LMG FPGA <=> CPU GPIO signals */ -#define LMG_XCV_INIT 0x10000000L -#define LMG_XCV_PROG 0x04000000L -#define LMG_XCV_DONE 0x00400000L -#define LMG_XCV_CNFG_0 0x08000000L -#define LMG_XCV_IRQ_0 0x0L - -/* LMC FPGA <=> CPU GPIO signals */ -#define LMC_XCV_INIT 0x00800000L -#define LMC_XCV_PROG 0x40000000L -#define LMC_XCV_DONE 0x01000000L -#define LMC_XCV_CNFG_0 0x00004000L /* Shared with IRQ 0 */ -#define LMC_XCV_CNFG_1 0x00002000L /* Shared with IRQ 1 */ -#define LMC_XCV_CNFG_2 0x00001000L /* Shared with IRQ 2 */ -#define LMC_XCV_IRQ_0 0x00080000L /* Shared with GPIO 17 */ -#define LMC_XCV_IRQ_1 0x00040000L /* Shared with GPIO 18 */ -#define LMC_XCV_IRQ_3 0x00020000L /* Shared tiwht GPIO 19 */ - - -/* - * Setup FPGA <=> GPIO mappings - */ -#if defined(CONFIG_W7OLMG) -# define GPIO_XCV_INIT LMG_XCV_INIT -# define GPIO_XCV_PROG LMG_XCV_PROG -# define GPIO_XCV_DONE LMG_XCV_DONE -# define GPIO_XCV_CNFG LMG_XCV_CNFG_0 -# define GPIO_XCV_IRQ LMG_XCV_IRQ_0 -# define GPIO_GPIO_1 0x40000000L -# define GPIO_GPIO_6 0x02000000L -# define GPIO_GPIO_7 0x01000000L -# define GPIO_GPIO_8 0x00800000L -#elif defined(CONFIG_W7OLMC) -# define GPIO_XCV_INIT LMC_XCV_INIT -# define GPIO_XCV_PROG LMC_XCV_PROG -# define GPIO_XCV_DONE LMC_XCV_DONE -# define GPIO_XCV_CNFG LMC_XCV_CNFG_0 -# define GPIO_XCV_IRQ LMC_XCV_IRQ_0 -#else -# error "Unknown W7O board configuration" -#endif - -/* Power On Self Tests */ -extern void post2(void); -extern int test_led(void); -extern int test_sdram(unsigned long size); -extern void test_fpga(unsigned short *daddr); - -/* FGPA */ -extern int init_fpga(void); - -/* Misc */ -extern int temp_uart_init(void); -extern void init_fsboot(void); - -#endif /* _W7O_H_ */ diff --git a/board/w7o/watchdog.c b/board/w7o/watchdog.c deleted file mode 100644 index 4bbd94f..0000000 --- a/board/w7o/watchdog.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * W7O board level hardware watchdog. - */ -#include -#include - -#ifdef CONFIG_HW_WATCHDOG -#include - -void hw_watchdog_reset(void) -{ - volatile ushort *hwd = (ushort *)(CFG_W7O_EBC_PB7CR & 0xfff00000); - - /* - * Read the LMG's hwd register and toggle the - * watchdog bit to reset it. On the LMC, just - * reading it is enough, but toggling the bit - * doen't hurt either. - */ - *hwd = *hwd ^ 0x8000; - -} /* hw_watchdog_reset() */ - -#endif /* CONFIG_HW_WATCHDOG */ diff --git a/board/wepep250/Makefile b/board/wepep250/Makefile deleted file mode 100644 index 11ad8fb..0000000 --- a/board/wepep250/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := wepep250.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/wepep250/config.mk b/board/wepep250/config.mk deleted file mode 100644 index 8701581..0000000 --- a/board/wepep250/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# This is config used for compilation of WEP EP250 sources -# -# You might change location of U-Boot in memory by setting right TEXT_BASE. -# This allows for example having one copy located at the end of ram and stored -# in flash device and later on while developing use other location to test -# the code in RAM device only. -# - -TEXT_BASE = 0xa1fe0000 -#TEXT_BASE = 0xa1001000 diff --git a/board/wepep250/flash.c b/board/wepep250/flash.c deleted file mode 100644 index 2a32290..0000000 --- a/board/wepep250/flash.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (C) 2003 ETC s.r.o. - * - * This code was inspired by Marius Groeger and Kyle Harris code - * available in other board ports for U-Boot - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Written by Peter Figuli , 2003. - * - */ - -#include -#include "intel.h" - - -/* - * This code should handle CFI FLASH memory device. This code is very - * minimalistic approach without many essential error handling code as well. - * Because U-Boot actually is missing smart handling of FLASH device, - * we just set flash_id to anything else to FLASH_UNKNOW, so common code - * can call us without any restrictions. - * TODO: Add CFI Query, to be able to determine FLASH device. - * TODO: Add error handling code - * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but - * hopefully may work with other configurations. - */ - -#if ( WEP_FLASH_BUS_WIDTH == 1 ) -# define FLASH_BUS vu_char -# if ( WEP_FLASH_INTERLEAVE == 1 ) -# define FLASH_CMD( x ) x -# else -# error "With 8bit bus only one chip is allowed" -# endif - - -#elif ( WEP_FLASH_BUS_WIDTH == 2 ) -# define FLASH_BUS vu_short -# if ( WEP_FLASH_INTERLEAVE == 1 ) -# define FLASH_CMD( x ) x -# elif ( WEP_FLASH_INTERLEAVE == 2 ) -# define FLASH_CMD( x ) (( x << 8 )| x ) -# else -# error "With 16bit bus only 1 or 2 chip(s) are allowed" -# endif - - -#elif ( WEP_FLASH_BUS_WIDTH == 4 ) -# define FLASH_BUS vu_long -# if ( WEP_FLASH_INTERLEAVE == 1 ) -# define FLASH_CMD( x ) x -# elif ( WEP_FLASH_INTERLEAVE == 2 ) -# define FLASH_CMD( x ) (( x << 16 )| x ) -# elif ( WEP_FLASH_INTERLEAVE == 4 ) -# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x ) -# else -# error "With 32bit bus only 1,2 or 4 chip(s) are allowed" -# endif - -#else -# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration" -#endif - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -static FLASH_BUS flash_status_reg (void) -{ - - FLASH_BUS *addr = (FLASH_BUS *) 0; - - *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); - - return *addr; -} - -static int flash_ready (ulong timeout) -{ - int ok = 1; - - reset_timer_masked (); - while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != - FLASH_CMD (CFI_INTEL_SR_READY)) { - if (get_timer_masked () > timeout && timeout != 0) { - ok = 0; - break; - } - } - return ok; -} - -#if ( CFG_MAX_FLASH_BANKS != 1 ) -# error "WEP platform has only one flash bank!" -#endif - - -ulong flash_init (void) -{ - int i; - FLASH_BUS address = WEP_FLASH_BASE; - - flash_info[0].size = WEP_FLASH_BANK_SIZE; - flash_info[0].sector_count = CFG_MAX_FLASH_SECT; - flash_info[0].flash_id = INTEL_MANUFACT; - memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); - - for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { - flash_info[0].start[i] = address; -#ifdef WEP_FLASH_UNLOCK - /* Some devices are hw locked after start. */ - *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP); - *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK); - flash_ready (0); - *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); -#endif - address += WEP_FLASH_SECT_SIZE; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return WEP_FLASH_BANK_SIZE; -} - -void flash_print_info (flash_info_t * info) -{ - int i; - - printf (" Intel vendor\n"); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if (!(i % 5)) { - printf ("\n"); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, non_protected = 0, sector; - int rc = ERR_OK; - - FLASH_BUS *address; - - for (sector = s_first; sector <= s_last; sector++) { - if (!info->protect[sector]) { - non_protected++; - } - } - - if (!non_protected) { - return ERR_PROTECTED; - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - - /* Start erase on unprotected sectors */ - for (sector = s_first; sector <= s_last && !ctrlc (); sector++) { - if (info->protect[sector]) { - printf ("Protected sector %2d skipping...\n", sector); - continue; - } else { - printf ("Erasing sector %2d ... ", sector); - } - - address = (FLASH_BUS *) (info->start[sector]); - - *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); - *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); - if (flash_ready (CFG_FLASH_ERASE_TOUT)) { - *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); - printf ("ok.\n"); - } else { - *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); - rc = ERR_TIMOUT; - printf ("timeout! Aborting...\n"); - break; - } - *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); - } - if (ctrlc ()) - printf ("User Interrupt!\n"); - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - if (flag) { - enable_interrupts (); - } - - return rc; -} - -static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) -{ - FLASH_BUS *address = (FLASH_BUS *) dest; - int rc = ERR_OK; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*address & data) != data) { - return ERR_NOT_ERASED; - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - flag = disable_interrupts (); - - *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); - *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); - *address = data; - - if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { - *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); - rc = ERR_TIMOUT; - printf ("timeout! Aborting...\n"); - } - - *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); - if (flag) { - enable_interrupts (); - } - - return rc; -} - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong read_addr, write_addr; - FLASH_BUS data; - int i, result = ERR_OK; - - - read_addr = addr & ~(sizeof (FLASH_BUS) - 1); - write_addr = read_addr; - if (read_addr != addr) { - data = 0; - for (i = 0; i < sizeof (FLASH_BUS); i++) { - if (read_addr < addr || cnt == 0) { - data |= *((uchar *) read_addr) << i * 8; - } else { - data |= (*src++) << i * 8; - cnt--; - } - read_addr++; - } - if ((result = write_data (info, write_addr, data)) != ERR_OK) { - return result; - } - write_addr += sizeof (FLASH_BUS); - } - for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) { - if ((result = write_data (info, write_addr, - *((FLASH_BUS *) src))) != ERR_OK) { - return result; - } - write_addr += sizeof (FLASH_BUS); - src += sizeof (FLASH_BUS); - } - if (cnt > 0) { - read_addr = write_addr; - data = 0; - for (i = 0; i < sizeof (FLASH_BUS); i++) { - if (cnt > 0) { - data |= (*src++) << i * 8; - cnt--; - } else { - data |= *((uchar *) read_addr) << i * 8; - } - read_addr++; - } - if ((result = write_data (info, write_addr, data)) != 0) { - return result; - } - } - return ERR_OK; -} diff --git a/board/wepep250/intel.h b/board/wepep250/intel.h deleted file mode 100644 index 77498b6..0000000 --- a/board/wepep250/intel.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2002 ETC s.r.o. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the ETC s.r.o. nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Written by Marcel Telka , 2002. - * - * Documentation: - * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, - * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 - * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, - * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 - * - * This file is taken from OpenWinCE project hosted by SourceForge.net - * - */ - -#ifndef FLASH_INTEL_H -#define FLASH_INTEL_H - -#include - -/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ - -#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ - -/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ - -#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ - -/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ - -#define CFI_CHIP_INTEL_28F320J3A 0x0016 -#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" -#define CFI_CHIP_INTEL_28F640J3A 0x0017 -#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" -#define CFI_CHIP_INTEL_28F128J3A 0x0018 -#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" - -/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ - -#define CFI_CHIP_INTEL_28F640K3 0x8801 -#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" -#define CFI_CHIP_INTEL_28F128K3 0x8802 -#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" -#define CFI_CHIP_INTEL_28F256K3 0x8803 -#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" -#define CFI_CHIP_INTEL_28F640K18 0x8805 -#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" -#define CFI_CHIP_INTEL_28F128K18 0x8806 -#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" -#define CFI_CHIP_INTEL_28F256K18 0x8807 -#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" - -#endif /* FLASH_INTEL_H */ diff --git a/board/wepep250/lowlevel_init.S b/board/wepep250/lowlevel_init.S deleted file mode 100644 index b172cea..0000000 --- a/board/wepep250/lowlevel_init.S +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (C) 2001, 2002 ETC s.r.o. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - * 02111-1307, USA. - * - * Written by Marcel Telka , 2001, 2002. - * Changes for U-Boot Peter Figuli , 2003. - * - * This file is taken from OpenWinCE project hosted by SourceForge.net - * - * Documentation: - * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors - * Developer's Manual", February 2002, Order Number: 278522-001 - * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P", - * Revision 1.0, February 2002 - * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)", - * Revision 1.0, February 2002 - * -*/ - -#include -#include -#include - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - -/* setup memory - see 6.12 in [1] - * Step 1 - wait 200 us - */ - mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */ -1: subs r0, r0, #1 - bne 1b -/* TODO: complete step 1 for Synchronous Static memory*/ - - ldr r0, =0x48000000 /* MC_BASE */ - - -/* step 1.a - setup MSCx - */ - ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */ - str r1, [r0, #0x8] /* MSC0_OFFSET */ - -/* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI - * see AUTO REFRESH chapter in section D. in [2] and in [3] - * DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633 - * DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633 - * TODO: complete for Synchronous Static memory - */ - ldr r1, [r0, #4] /* MDREFR_OFFSET */ - ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */ - bic r1, r1, r2 -#if defined( WEP_SDRAM_K4S281633 ) - orr r1, r1, #48 /* MDREFR_DRI(48) */ -#elif defined( WEP_SDRAM_K4S561633 ) - orr r1, r1, #24 /* MDREFR_DRI(24) */ -#else -#error SDRAM chip is not defined -#endif - - str r1, [r0, #4] /* MDREFR_OFFSET */ - -/* Step 2 - only for Synchronous Static memory (TODO) - * - * Step 3 - same as step 4 - * - * Step 4 - * - * Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2 - */ - orr r1, r1, #0x00010000 /* MDREFR_K1RUN */ - bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */ - str r1, [r0, #4] /* MDREFR_OFFSET */ - -/* Step 4.b - clear MDREFR:SLFRSH */ - bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */ - str r1, [r0, #4] /* MDREFR_OFFSET */ - -/* Step 4.c - set MDREFR:E1PIN */ - orr r1, r1, #0x00008000 /* MDREFR_E1PIN */ - str r1, [r0, #4] /* MDREFR_OFFSET */ - -/* Step 4.d - automatically done - * - * Steps 4.e and 4.f - configure SDRAM - */ -#if defined( WEP_SDRAM_K4S281633 ) - ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */ -#elif defined( WEP_SDRAM_K4S561633 ) - ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */ -#else -#error SDRAM chip is not defined -#endif - str r1, [r0, #0] /* MDCNFG_OFFSET */ - -/* Step 5 - wait at least 200 us for SDRAM - * see section B. in [2] - */ - mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */ -1: subs r2, r2, #1 - bne 1b - -/* Step 6 - after reset dcache is disabled, so automatically done - * - * Step 7 - eight refresh cycles - */ - mov r2, #0xA0000000 - ldr r3, [r2] - ldr r3, [r2] - ldr r3, [r2] - ldr r3, [r2] - ldr r3, [r2] - ldr r3, [r2] - ldr r3, [r2] - ldr r3, [r2] - -/* Step 8 - we don't need dcache now - * - * Step 9 - enable SDRAM partition 0 - */ - orr r1, r1, #1 /* MDCNFG_DE0 */ - str r1, [r0, #0] /* MDCNFG_OFFSET */ - -/* Step 10 - write MDMRS */ - mov r1, #0 - str r1, [r0, #0x40] /* MDMRS_OFFSET */ - -/* Step 11 - optional (TODO) */ - - mov pc,r10 diff --git a/board/wepep250/u-boot.lds b/board/wepep250/u-boot.lds deleted file mode 100644 index f010239..0000000 --- a/board/wepep250/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c deleted file mode 100644 index 56cb855..0000000 --- a/board/wepep250/wepep250.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) 2003 ETC s.r.o. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Written by Peter Figuli , 2003. - * - */ - -#include -#include - -int board_init( void ){ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250; - gd->bd->bi_boot_params = 0xa0000000; -/* - * Setup GPIO stuff to get serial working - */ -#if defined( CONFIG_FFUART ) - GPDR1 = 0x80; - GAFR1_L = 0x8010; -#elif defined( CONFIG_BTUART ) - GPDR1 = 0x800; - GAFR1_L = 0x900000; -#endif - PSSR = 0x20; - - return 0; -} - -int dram_init( void ){ - DECLARE_GLOBAL_DATA_PTR; - -#if ( CONFIG_NR_DRAM_BANKS > 0 ) - gd->bd->bi_dram[0].start = WEP_SDRAM_1; - gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 1 ) - gd->bd->bi_dram[1].start = WEP_SDRAM_2; - gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 2 ) - gd->bd->bi_dram[2].start = WEP_SDRAM_3; - gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE; -#endif -#if ( CONFIG_NR_DRAM_BANKS > 3 ) - gd->bd->bi_dram[3].start = WEP_SDRAM_4; - gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE; -#endif - - return 0; -} diff --git a/board/westel/amx860/Makefile b/board/westel/amx860/Makefile deleted file mode 100644 index 7a2014d..0000000 --- a/board/westel/amx860/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o flash.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/westel/amx860/amx860.c b/board/westel/amx860/amx860.c deleted file mode 100644 index 8826667..0000000 --- a/board/westel/amx860/amx860.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint edo_60ns[] = -{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04, - 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_, - 0x8fffec24, 0x0ffbec04, 0x08f3ec04, 0x07f3ec08, - 0x08f3ec04, 0x07f3ec48, 0x08f3ec04, 0x07f3ec48, - 0x08f3ec04, 0x07f3ec48, 0x1ff7ec47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, - 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: AMX860\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -long int initdram (int board_type) -{ - - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */ - - upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint)); - -#ifndef CONFIG_AMX_RAM_EXT - memctl->memc_mptpr = 0x0400; /* divide by 16 */ -#else - memctl->memc_mptpr = 0x0200; -#endif - - memctl->memc_mamr = 0x30a21114; - memctl->memc_or2 = 0xffc00800; -#ifndef CONFIG_AMX_RAM_EXT - memctl->memc_br2 = 0x81; - - return (4 << 20); -#else - memctl->memc_or1 = 0xff000800; - memctl->memc_br1 = 0x00000081; - memctl->memc_br2 = 0x01000081; - - return (20 << 20); -#endif -} diff --git a/board/westel/amx860/config.mk b/board/westel/amx860/config.mk deleted file mode 100644 index d0ee4a2..0000000 --- a/board/westel/amx860/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -#TEXT_BASE = 0xFE000000 -TEXT_BASE = 0x40000000 -OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data diff --git a/board/westel/amx860/flash.c b/board/westel/amx860/flash.c deleted file mode 100644 index 12a1335..0000000 --- a/board/westel/amx860/flash.c +++ /dev/null @@ -1,637 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } -#else - size_b1 = 0; -#endif /* FLASH_BASE1_PRELIM */ - - DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - DEBUGF ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK); - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - DEBUGF("## BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_info[1].size = size_b1; - - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); - -# if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -# endif - -# ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - } else { -#ifndef CONFIG_AMX_RAM_EXT - memctl->memc_br1 = 0; /* invalidate bank */ - memctl->memc_or1 = 0; /* invalidate bank */ -#endif - - DEBUGF("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - } - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00040000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - DEBUGF("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { - case AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds deleted file mode 100644 index cdf550f..0000000 --- a/board/westel/amx860/u-boot.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_ppc/ppcstring.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug deleted file mode 100644 index 87f228b..0000000 --- a/board/westel/amx860/u-boot.lds.debug +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - . = env_offset; - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile deleted file mode 100644 index 7c5f0cd..0000000 --- a/board/xaeniax/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := xaeniax.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/xaeniax/config.mk b/board/xaeniax/config.mk deleted file mode 100644 index 45079a0..0000000 --- a/board/xaeniax/config.mk +++ /dev/null @@ -1,2 +0,0 @@ -TEXT_BASE = 0xa3FB0000 -#TEXT_BASE = 0 diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c deleted file mode 100644 index 9874a14..0000000 --- a/board/xaeniax/flash.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/xaeniax/lowlevel_init.S b/board/xaeniax/lowlevel_init.S deleted file mode 100644 index fe3e712..0000000 --- a/board/xaeniax/lowlevel_init.S +++ /dev/null @@ -1,424 +0,0 @@ - /* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - - /* Set up GPIO pins first ----------------------------------------- */ - - ldr r0,=GPSR0 - ldr r1,=CFG_GPSR0_VAL - str r1,[r0] - - ldr r0,=GPSR1 - ldr r1,=CFG_GPSR1_VAL - str r1,[r0] - - ldr r0,=GPSR2 - ldr r1,=CFG_GPSR2_VAL - str r1,[r0] - - ldr r0,=GPCR0 - ldr r1,=CFG_GPCR0_VAL - str r1,[r0] - - ldr r0,=GPCR1 - ldr r1,=CFG_GPCR1_VAL - str r1,[r0] - - ldr r0,=GPCR2 - ldr r1,=CFG_GPCR2_VAL - str r1,[r0] - - ldr r0,=GPDR0 - ldr r1,=CFG_GPDR0_VAL - str r1,[r0] - - ldr r0,=GPDR1 - ldr r1,=CFG_GPDR1_VAL - str r1,[r0] - - ldr r0,=GPDR2 - ldr r1,=CFG_GPDR2_VAL - str r1,[r0] - - ldr r0,=GAFR0_L - ldr r1,=CFG_GAFR0_L_VAL - str r1,[r0] - - ldr r0,=GAFR0_U - ldr r1,=CFG_GAFR0_U_VAL - str r1,[r0] - - ldr r0,=GAFR1_L - ldr r1,=CFG_GAFR1_L_VAL - str r1,[r0] - - ldr r0,=GAFR1_U - ldr r1,=CFG_GAFR1_U_VAL - str r1,[r0] - - ldr r0,=GAFR2_L - ldr r1,=CFG_GAFR2_L_VAL - str r1,[r0] - - ldr r0,=GAFR2_U - ldr r1,=CFG_GAFR2_U_VAL - str r1,[r0] - - ldr r0,=PSSR /* enable GPIO pins */ - ldr r1,=CFG_PSSR_VAL - str r1,[r0] - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1,=MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2,=CFG_MSC0_VAL - str r2,[r1, #MSC0_OFFSET] - ldr r2,[r1, #MSC0_OFFSET] /* read back to ensure data latches */ - - /* MSC1: nCS(2,3) */ - ldr r2,=CFG_MSC1_VAL - str r2,[r1, #MSC1_OFFSET] - ldr r2,[r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2,=CFG_MSC2_VAL - str r2,[r1, #MSC2_OFFSET] - ldr r2,[r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2,=CFG_MECR_VAL - str r2,[r1, #MECR_OFFSET] - ldr r2,[r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2,=CFG_MCMEM0_VAL - str r2,[r1, #MCMEM0_OFFSET] - ldr r2,[r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2,=CFG_MCMEM1_VAL - str r2,[r1, #MCMEM1_OFFSET] - ldr r2,[r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2,=CFG_MCATT0_VAL - str r2,[r1, #MCATT0_OFFSET] - ldr r2,[r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2,=CFG_MCATT1_VAL - str r2,[r1, #MCATT1_OFFSET] - ldr r2,[r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2,=CFG_MCIO0_VAL - str r2,[r1, #MCIO0_OFFSET] - ldr r2,[r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2,=CFG_MCIO1_VAL - str r2,[r1, #MCIO1_OFFSET] - ldr r2,[r1, #MCIO1_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - @ get the mdrefr settings - ldr r4,=CFG_MDREFR_VAL - - @ write back mdrefr - str r4,[r1, #MDREFR_OFFSET] - ldr r4,[r1, #MDREFR_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - /* FIXME: we use async mode for now */ - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - @ set K1RUN for bank 0 - @ - orr r4, r4, #MDREFR_K1RUN - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - @ deassert SLFRSH - @ - bic r4, r4, #MDREFR_SLFRSH - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - @ assert E1PIN - @ if E0PIN is also used: #(MDREFR_E1PIN|MDREFR_E0PIN) - orr r4, r4, #(MDREFR_E1PIN) - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - nop - nop - - /* Step 4d: */ - /* fetch platform value of mdcnfg */ - @ - ldr r2, =CFG_MDCNFG_VAL - - @ disable all sdram banks - @ - bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) - bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3) - - @ program banks 0/1 for bus width - @ - bic r2, r2, #MDCNFG_DWID0 @0=32-bit - - @ write initial value of mdcnfg, w/o enabling sdram banks - @ - str r2, [r1, #MDCNFG_OFFSET] - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - ldr r3, =CFG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* get memory controller base address */ - ldr r1, =MEMC_BASE - - @fetch current mdcnfg value - @ - ldr r3, [r1, #MDCNFG_OFFSET] - - @enable sdram bank 0 if installed (must do for any populated bank) - @ - orr r3, r3, #MDCNFG_DE0 - - @write back mdcnfg, enabling the sdram bank(s) - @ - str r3, [r1, #MDCNFG_OFFSET] - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - - /* We are finished with Intel's memory controller initialisation */ - - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r1, =CFG_ICMR_VAL /* mask all interrupts at the controller */ - ldr r2, =ICMR - str r1, [r2] - - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - /* (hard-coding at 398.12MHz for now). */ - /* Turn Off ALL on-chip peripheral clocks for re-configuration */ - /* Note: See label 'ENABLECLKS' for the re-enabling */ - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - - /* default value */ - ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ - - /* ... and write the core clock config register */ - ldr r1, =CCCR - str r2, [r1] - -#ifdef RTC - /* enable the 32Khz oscillator for RTC and PowerManager */ - - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#endif - - @ Turn on needed clocks - @ -test: - ldr r1, =CKEN - ldr r2, =CFG_CKEN_VAL - str r2, [r1] - - /* ---------------------------------------------------------------- */ - /* */ - /* ---------------------------------------------------------------- */ - - /* Save SDRAM size ?*/ - ldr r1, =DRAM_SIZE - str r8, [r1] - - /* FIXME */ - -#define NODEBUG -#ifdef NODEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ - -#endif - - /* ---------------------------------------------------------------- */ - /* End lowlevel_init */ - /* ---------------------------------------------------------------- */ - -endlowlevel_init: - - mov pc, lr diff --git a/board/xaeniax/u-boot.lds b/board/xaeniax/u-boot.lds deleted file mode 100644 index f010239..0000000 --- a/board/xaeniax/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c deleted file mode 100644 index 26fb312..0000000 --- a/board/xaeniax/xaeniax.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2004 - * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of xaeniax */ - gd->bd->bi_arch_number = 585; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - /* gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/ - /* gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;*/ - /* gd->bd->bi_dram[2].start = PHYS_SDRAM_3; */ - /* gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; */ - /* gd->bd->bi_dram[3].start = PHYS_SDRAM_4; */ - /* gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; */ - - return 0; -} diff --git a/board/xilinx/common/xbasic_types.c b/board/xilinx/common/xbasic_types.c deleted file mode 100644 index c3a171a..0000000 --- a/board/xilinx/common/xbasic_types.c +++ /dev/null @@ -1,165 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* - * -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xbasic_types.c -* -* This file contains basic functions for Xilinx software IP. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -/** - * This variable allows testing to be done easier with asserts. An assert - * sets this variable such that a driver can evaluate this variable - * to determine if an assert occurred. - */ -unsigned int XAssertStatus; - -/** - * This variable allows the assert functionality to be changed for testing - * such that it does not wait infinitely. Use the debugger to disable the - * waiting during testing of asserts. - */ -u32 XWaitInAssert = TRUE; - -/* The callback function to be invoked when an assert is taken */ -static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL; - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* -* Implements assert. Currently, it calls a user-defined callback function -* if one has been set. Then, it potentially enters an infinite loop depending -* on the value of the XWaitInAssert variable. -* -* @param File is the name of the filename of the source -* @param Line is the linenumber within File -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -void -XAssert(char *File, int Line) -{ - /* if the callback has been set then invoke it */ - if (XAssertCallbackRoutine != NULL) { - (*XAssertCallbackRoutine) (File, Line); - } - - /* if specified, wait indefinitely such that the assert will show up - * in testing - */ - while (XWaitInAssert) { - } -} - -/*****************************************************************************/ -/** -* -* Sets up a callback function to be invoked when an assert occurs. If there -* was already a callback installed, then it is replaced. -* -* @param Routine is the callback to be invoked when an assert is taken -* -* @return -* -* None. -* -* @note -* -* This function has no effect if NDEBUG is set -* -******************************************************************************/ -void -XAssertSetCallback(XAssertCallback Routine) -{ - XAssertCallbackRoutine = Routine; -} - -/*****************************************************************************/ -/** -* -* Null handler function. This follows the XInterruptHandler signature for -* interrupt handlers. It can be used to assign a null handler (a stub) to an -* interrupt controller vector table. -* -* @param NullParameter is an arbitrary void pointer and not used. -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -void -XNullHandler(void *NullParameter) -{ -} diff --git a/board/xilinx/common/xbasic_types.h b/board/xilinx/common/xbasic_types.h deleted file mode 100644 index ef0b7c2..0000000 --- a/board/xilinx/common/xbasic_types.h +++ /dev/null @@ -1,283 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xbasic_types.h -* -* This file contains basic types for Xilinx software IP. These types do not -* follow the standard naming convention with respect to using the component -* name in front of each name because they are considered to be primitives. -* -* @note -* -* This file contains items which are architecture dependent. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver	Who    Date   Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rmm  12/14/01 First release
-*	rmm  05/09/03 Added "xassert always" macros to rid ourselves of diab
-*		      compiler warnings
-* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
-*
-* -******************************************************************************/ - -#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ -#define XBASIC_TYPES_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -/************************** Constant Definitions *****************************/ - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef NULL -#define NULL 0 -#endif -/** Null */ - -#define XCOMPONENT_IS_READY 0x11111111 /* component has been initialized */ -#define XCOMPONENT_IS_STARTED 0x22222222 /* component has been started */ - -/* the following constants and declarations are for unit test purposes and are - * designed to be used in test applications. - */ -#define XTEST_PASSED 0 -#define XTEST_FAILED 1 - -#define XASSERT_NONE 0 -#define XASSERT_OCCURRED 1 - -extern unsigned int XAssertStatus; -extern void XAssert(char *, int); - -/**************************** Type Definitions *******************************/ - -/** @name Primitive types - * These primitive types are created for transportability. - * They are dependent upon the target architecture. - * @{ - */ -#include - -typedef struct { - u32 Upper; - u32 Lower; -} Xuint64; - -/*@}*/ - -/** - * This data type defines an interrupt handler for a device. - * The argument points to the instance of the component - */ -typedef void (*XInterruptHandler) (void *InstancePtr); - -/** - * This data type defines a callback to be invoked when an - * assert occurs. The callback is invoked only when asserts are enabled - */ -typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber); - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** -* Return the most significant half of the 64 bit data type. -* -* @param x is the 64 bit word. -* -* @return -* -* The upper 32 bits of the 64 bit word. -* -* @note -* -* None. -* -******************************************************************************/ -#define XUINT64_MSW(x) ((x).Upper) - -/*****************************************************************************/ -/** -* Return the least significant half of the 64 bit data type. -* -* @param x is the 64 bit word. -* -* @return -* -* The lower 32 bits of the 64 bit word. -* -* @note -* -* None. -* -******************************************************************************/ -#define XUINT64_LSW(x) ((x).Lower) - -#ifndef NDEBUG - -/*****************************************************************************/ -/** -* This assert macro is to be used for functions that do not return anything -* (void). This in conjunction with the XWaitInAssert boolean can be used to -* accomodate tests so that asserts which fail allow execution to continue. -* -* @param expression is the expression to evaluate. If it evaluates to false, -* the assert occurs. -* -* @return -* -* Returns void unless the XWaitInAssert variable is true, in which case -* no return is made and an infinite loop is entered. -* -* @note -* -* None. -* -******************************************************************************/ -#define XASSERT_VOID(expression) \ -{ \ - if (expression) { \ - XAssertStatus = XASSERT_NONE; \ - } else { \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return; \ - } \ -} - -/*****************************************************************************/ -/** -* This assert macro is to be used for functions that do return a value. This in -* conjunction with the XWaitInAssert boolean can be used to accomodate tests so -* that asserts which fail allow execution to continue. -* -* @param expression is the expression to evaluate. If it evaluates to false, -* the assert occurs. -* -* @return -* -* Returns 0 unless the XWaitInAssert variable is true, in which case -* no return is made and an infinite loop is entered. -* -* @note -* -* None. -* -******************************************************************************/ -#define XASSERT_NONVOID(expression) \ -{ \ - if (expression) { \ - XAssertStatus = XASSERT_NONE; \ - } else { \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return 0; \ - } \ -} - -/*****************************************************************************/ -/** -* Always assert. This assert macro is to be used for functions that do not -* return anything (void). Use for instances where an assert should always -* occur. -* -* @return -* -* Returns void unless the XWaitInAssert variable is true, in which case -* no return is made and an infinite loop is entered. -* -* @note -* -* None. -* -******************************************************************************/ -#define XASSERT_VOID_ALWAYS() \ -{ \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return; \ -} - -/*****************************************************************************/ -/** -* Always assert. This assert macro is to be used for functions that do return -* a value. Use for instances where an assert should always occur. -* -* @return -* -* Returns void unless the XWaitInAssert variable is true, in which case -* no return is made and an infinite loop is entered. -* -* @note -* -* None. -* -******************************************************************************/ -#define XASSERT_NONVOID_ALWAYS() \ -{ \ - XAssert(__FILE__, __LINE__); \ - XAssertStatus = XASSERT_OCCURRED; \ - return 0; \ -} - -#else - -#define XASSERT_VOID(expression) -#define XASSERT_VOID_ALWAYS() -#define XASSERT_NONVOID(expression) -#define XASSERT_NONVOID_ALWAYS() -#endif - -/************************** Function Prototypes ******************************/ - -void XAssertSetCallback(XAssertCallback Routine); -void XNullHandler(void *NullParameter); - -#endif /* end of protection macro */ diff --git a/board/xilinx/common/xbuf_descriptor.h b/board/xilinx/common/xbuf_descriptor.h deleted file mode 100644 index fdd51d5..0000000 --- a/board/xilinx/common/xbuf_descriptor.h +++ /dev/null @@ -1,252 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -* FILENAME: -* -* xbuf_descriptor.h -* -* DESCRIPTION: -* -* This file contains the interface for the XBufDescriptor component. -* The XBufDescriptor component is a passive component that only maps over -* a buffer descriptor data structure shared by the scatter gather DMA hardware -* and software. The component's primary purpose is to provide encapsulation of -* the buffer descriptor processing. See the source file xbuf_descriptor.c for -* details. -* -* NOTES: -* -* Most of the functions of this component are implemented as macros in order -* to optimize the processing. The names are not all uppercase such that they -* can be switched between macros and functions easily. -* -******************************************************************************/ - -#ifndef XBUF_DESCRIPTOR_H /* prevent circular inclusions */ -#define XBUF_DESCRIPTOR_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xdma_channel_i.h" - -/************************** Constant Definitions *****************************/ - -/* The following constants allow access to all fields of a buffer descriptor - * and are necessary at this level of visibility to allow macros to access - * and modify the fields of a buffer descriptor. It is not expected that the - * user of a buffer descriptor would need to use these constants. - */ - -#define XBD_DEVICE_STATUS_OFFSET 0 -#define XBD_CONTROL_OFFSET 1 -#define XBD_SOURCE_OFFSET 2 -#define XBD_DESTINATION_OFFSET 3 -#define XBD_LENGTH_OFFSET 4 -#define XBD_STATUS_OFFSET 5 -#define XBD_NEXT_PTR_OFFSET 6 -#define XBD_ID_OFFSET 7 -#define XBD_FLAGS_OFFSET 8 -#define XBD_RQSTED_LENGTH_OFFSET 9 - -#define XBD_SIZE_IN_WORDS 10 - -/* - * The following constants define the bits of the flags field of a buffer - * descriptor - */ - -#define XBD_FLAGS_LOCKED_MASK 1UL - -/**************************** Type Definitions *******************************/ - -typedef u32 XBufDescriptor[XBD_SIZE_IN_WORDS]; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/* each of the following macros are named the same as functions rather than all - * upper case in order to allow either the macros or the functions to be - * used, see the source file xbuf_descriptor.c for documentation - */ - -#define XBufDescriptor_Initialize(InstancePtr) \ -{ \ - (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = 0); \ - (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = 0); \ - (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = 0); \ - (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = 0); \ - (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = 0); \ - (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = 0); \ - (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = 0); \ - (*((u32 *)InstancePtr + XBD_ID_OFFSET) = 0); \ - (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = 0); \ - (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = 0); \ -} - -#define XBufDescriptor_GetControl(InstancePtr) \ - (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET)) - -#define XBufDescriptor_SetControl(InstancePtr, Control) \ - (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = (u32)Control) - -#define XBufDescriptor_IsLastControl(InstancePtr) \ - (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) & \ - XDC_CONTROL_LAST_BD_MASK) - -#define XBufDescriptor_SetLast(InstancePtr) \ - (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) |= XDC_CONTROL_LAST_BD_MASK) - -#define XBufDescriptor_GetSrcAddress(InstancePtr) \ - ((u32 *)(*((u32 *)InstancePtr + XBD_SOURCE_OFFSET))) - -#define XBufDescriptor_SetSrcAddress(InstancePtr, Source) \ - (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = (u32)Source) - -#define XBufDescriptor_GetDestAddress(InstancePtr) \ - ((u32 *)(*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET))) - -#define XBufDescriptor_SetDestAddress(InstancePtr, Destination) \ - (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = (u32)Destination) - -#define XBufDescriptor_GetLength(InstancePtr) \ - (u32)(*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) - \ - *((u32 *)InstancePtr + XBD_LENGTH_OFFSET)) - -#define XBufDescriptor_SetLength(InstancePtr, Length) \ -{ \ - (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = (u32)(Length)); \ - (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = (u32)(Length));\ -} - -#define XBufDescriptor_GetStatus(InstancePtr) \ - (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET)) - -#define XBufDescriptor_SetStatus(InstancePtr, Status) \ - (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = (u32)Status) - -#define XBufDescriptor_IsLastStatus(InstancePtr) \ - (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET) & \ - XDC_STATUS_LAST_BD_MASK) - -#define XBufDescriptor_GetDeviceStatus(InstancePtr) \ - ((u32)(*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET))) - -#define XBufDescriptor_SetDeviceStatus(InstancePtr, Status) \ - (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = (u32)Status) - -#define XBufDescriptor_GetNextPtr(InstancePtr) \ - (XBufDescriptor *)(*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET)) - -#define XBufDescriptor_SetNextPtr(InstancePtr, NextPtr) \ - (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = (u32)NextPtr) - -#define XBufDescriptor_GetId(InstancePtr) \ - (u32)(*((u32 *)InstancePtr + XBD_ID_OFFSET)) - -#define XBufDescriptor_SetId(InstancePtr, Id) \ - (*((u32 *)InstancePtr + XBD_ID_OFFSET) = (u32)Id) - -#define XBufDescriptor_GetFlags(InstancePtr) \ - (u32)(*((u32 *)InstancePtr + XBD_FLAGS_OFFSET)) - -#define XBufDescriptor_SetFlags(InstancePtr, Flags) \ - (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = (u32)Flags) - -#define XBufDescriptor_Lock(InstancePtr) \ - (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) |= XBD_FLAGS_LOCKED_MASK) - -#define XBufDescriptor_Unlock(InstancePtr) \ - (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) &= ~XBD_FLAGS_LOCKED_MASK) - -#define XBufDescriptor_IsLocked(InstancePtr) \ - (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) & XBD_FLAGS_LOCKED_MASK) - -/************************** Function Prototypes ******************************/ - -/* The following prototypes are provided to allow each of the functions to - * be implemented as a function rather than a macro, and to provide the - * syntax to allow users to understand how to call the macros, they are - * commented out to prevent linker errors - * - -u32 XBufDescriptor_Initialize(XBufDescriptor* InstancePtr); - -u32 XBufDescriptor_GetControl(XBufDescriptor* InstancePtr); -void XBufDescriptor_SetControl(XBufDescriptor* InstancePtr, u32 Control); - -u32 XBufDescriptor_IsLastControl(XBufDescriptor* InstancePtr); -void XBufDescriptor_SetLast(XBufDescriptor* InstancePtr); - -u32 XBufDescriptor_GetLength(XBufDescriptor* InstancePtr); -void XBufDescriptor_SetLength(XBufDescriptor* InstancePtr, u32 Length); - -u32 XBufDescriptor_GetStatus(XBufDescriptor* InstancePtr); -void XBufDescriptor_SetStatus(XBufDescriptor* InstancePtr, u32 Status); -u32 XBufDescriptor_IsLastStatus(XBufDescriptor* InstancePtr); - -u32 XBufDescriptor_GetDeviceStatus(XBufDescriptor* InstancePtr); -void XBufDescriptor_SetDeviceStatus(XBufDescriptor* InstancePtr, - u32 Status); - -u32 XBufDescriptor_GetSrcAddress(XBufDescriptor* InstancePtr); -void XBufDescriptor_SetSrcAddress(XBufDescriptor* InstancePtr, - u32 SourceAddress); - -u32 XBufDescriptor_GetDestAddress(XBufDescriptor* InstancePtr); -void XBufDescriptor_SetDestAddress(XBufDescriptor* InstancePtr, - u32 DestinationAddress); - -XBufDescriptor* XBufDescriptor_GetNextPtr(XBufDescriptor* InstancePtr); -void XBufDescriptor_SetNextPtr(XBufDescriptor* InstancePtr, - XBufDescriptor* NextPtr); - -u32 XBufDescriptor_GetId(XBufDescriptor* InstancePtr); -void XBufDescriptor_SetId(XBufDescriptor* InstancePtr, u32 Id); - -u32 XBufDescriptor_GetFlags(XBufDescriptor* InstancePtr); -void XBufDescriptor_SetFlags(XBufDescriptor* InstancePtr, u32 Flags); - -void XBufDescriptor_Lock(XBufDescriptor* InstancePtr); -void XBufDescriptor_Unlock(XBufDescriptor* InstancePtr); -u32 XBufDescriptor_IsLocked(XBufDescriptor* InstancePtr); - -void XBufDescriptor_Copy(XBufDescriptor* InstancePtr, - XBufDescriptor* DestinationPtr); - -*/ - -#endif /* end of protection macro */ diff --git a/board/xilinx/common/xdma_channel.c b/board/xilinx/common/xdma_channel.c deleted file mode 100644 index 3d5fc75..0000000 --- a/board/xilinx/common/xdma_channel.c +++ /dev/null @@ -1,738 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -* FILENAME: -* -* xdma_channel.c -* -* DESCRIPTION: -* -* This file contains the DMA channel component. This component supports -* a distributed DMA design in which each device can have it's own dedicated -* DMA channel, as opposed to a centralized DMA design. This component -* performs processing for DMA on all devices. -* -* See xdma_channel.h for more information about this component. -* -* NOTES: -* -* None. -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xdma_channel.h" -#include "xbasic_types.h" -#include "xio.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_Initialize -* -* DESCRIPTION: -* -* This function initializes a DMA channel. This function must be called -* prior to using a DMA channel. Initialization of a channel includes setting -* up the registers base address, and resetting the channel such that it's in a -* known state. Interrupts for the channel are disabled when the channel is -* reset. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* BaseAddress contains the base address of the registers for the DMA channel. -* -* RETURN VALUE: -* -* XST_SUCCESS indicating initialization was successful. -* -* NOTES: -* -* None. -* -******************************************************************************/ -XStatus -XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress) -{ - /* assert to verify input arguments, don't assert base address */ - - XASSERT_NONVOID(InstancePtr != NULL); - - /* setup the base address of the registers for the DMA channel such - * that register accesses can be done - */ - InstancePtr->RegBaseAddress = BaseAddress; - - /* initialize the scatter gather list such that it indicates it has not - * been created yet and the DMA channel is ready to use (initialized) - */ - InstancePtr->GetPtr = NULL; - InstancePtr->PutPtr = NULL; - InstancePtr->CommitPtr = NULL; - InstancePtr->LastPtr = NULL; - - InstancePtr->TotalDescriptorCount = 0; - InstancePtr->ActiveDescriptorCount = 0; - InstancePtr->IsReady = XCOMPONENT_IS_READY; - - /* initialize the version of the component - */ - XVersion_FromString(&InstancePtr->Version, (s8 *)"1.00a"); - - /* reset the DMA channel such that it's in a known state and ready - * and indicate the initialization occured with no errors, note that - * the is ready variable must be set before this call or reset will assert - */ - XDmaChannel_Reset(InstancePtr); - - return XST_SUCCESS; -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_IsReady -* -* DESCRIPTION: -* -* This function determines if a DMA channel component has been successfully -* initialized such that it's ready to use. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* RETURN VALUE: -* -* TRUE if the DMA channel component is ready, FALSE otherwise. -* -* NOTES: -* -* None. -* -******************************************************************************/ -u32 -XDmaChannel_IsReady(XDmaChannel * InstancePtr) -{ - /* assert to verify input arguments used by the base component */ - - XASSERT_NONVOID(InstancePtr != NULL); - - return InstancePtr->IsReady == XCOMPONENT_IS_READY; -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_GetVersion -* -* DESCRIPTION: -* -* This function gets the software version for the specified DMA channel -* component. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* RETURN VALUE: -* -* A pointer to the software version of the specified DMA channel. -* -* NOTES: -* -* None. -* -******************************************************************************/ -XVersion * -XDmaChannel_GetVersion(XDmaChannel * InstancePtr) -{ - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* return a pointer to the version of the DMA channel */ - - return &InstancePtr->Version; -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_SelfTest -* -* DESCRIPTION: -* -* This function performs a self test on the specified DMA channel. This self -* test is destructive as the DMA channel is reset and a register default is -* verified. -* -* ARGUMENTS: -* -* InstancePtr is a pointer to the DMA channel to be operated on. -* -* RETURN VALUE: -* -* XST_SUCCESS is returned if the self test is successful, or one of the -* following errors. -* -* XST_DMA_RESET_REGISTER_ERROR Indicates the control register value -* after a reset was not correct -* -* NOTES: -* -* This test does not performs a DMA transfer to test the channel because the -* DMA hardware will not currently allow a non-local memory transfer to non-local -* memory (memory copy), but only allows a non-local memory to or from the device -* memory (typically a FIFO). -* -******************************************************************************/ - -#define XDC_CONTROL_REG_RESET_MASK 0x98000000UL /* control reg reset value */ - -XStatus -XDmaChannel_SelfTest(XDmaChannel * InstancePtr) -{ - u32 ControlReg; - - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* reset the DMA channel such that it's in a known state before the test - * it resets to no interrupts enabled, the desired state for the test - */ - XDmaChannel_Reset(InstancePtr); - - /* this should be the first test to help prevent a lock up with the polling - * loop that occurs later in the test, check the reset value of the DMA - * control register to make sure it's correct, return with an error if not - */ - ControlReg = XDmaChannel_GetControl(InstancePtr); - if (ControlReg != XDC_CONTROL_REG_RESET_MASK) { - return XST_DMA_RESET_REGISTER_ERROR; - } - - return XST_SUCCESS; -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_Reset -* -* DESCRIPTION: -* -* This function resets the DMA channel. This is a destructive operation such -* that it should not be done while a channel is being used. If the DMA channel -* is transferring data into other blocks, such as a FIFO, it may be necessary -* to reset other blocks. This function does not modify the contents of a -* scatter gather list for a DMA channel such that the user is responsible for -* getting buffer descriptors from the list if necessary. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ -void -XDmaChannel_Reset(XDmaChannel * InstancePtr) -{ - /* assert to verify input arguments */ - - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* reset the DMA channel such that it's in a known state, the reset - * register is self clearing such that it only has to be set - */ - XIo_Out32(InstancePtr->RegBaseAddress + XDC_RST_REG_OFFSET, - XDC_RESET_MASK); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_GetControl -* -* DESCRIPTION: -* -* This function gets the control register contents of the DMA channel. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* RETURN VALUE: -* -* The control register contents of the DMA channel. One or more of the -* following values may be contained the register. Each of the values are -* unique bit masks. -* -* XDC_DMACR_SOURCE_INCR_MASK Increment the source address -* XDC_DMACR_DEST_INCR_MASK Increment the destination address -* XDC_DMACR_SOURCE_LOCAL_MASK Local source address -* XDC_DMACR_DEST_LOCAL_MASK Local destination address -* XDC_DMACR_SG_ENABLE_MASK Scatter gather enable -* XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt -* XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet -* -* NOTES: -* -* None. -* -******************************************************************************/ -u32 -XDmaChannel_GetControl(XDmaChannel * InstancePtr) -{ - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* return the contents of the DMA control register */ - - return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_SetControl -* -* DESCRIPTION: -* -* This function sets the control register of the specified DMA channel. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* Control contains the value to be written to the control register of the DMA -* channel. One or more of the following values may be contained the register. -* Each of the values are unique bit masks such that they may be ORed together -* to enable multiple bits or inverted and ANDed to disable multiple bits. -* -* XDC_DMACR_SOURCE_INCR_MASK Increment the source address -* XDC_DMACR_DEST_INCR_MASK Increment the destination address -* XDC_DMACR_SOURCE_LOCAL_MASK Local source address -* XDC_DMACR_DEST_LOCAL_MASK Local destination address -* XDC_DMACR_SG_ENABLE_MASK Scatter gather enable -* XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt -* XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ -void -XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control) -{ - /* assert to verify input arguments except the control which can't be - * asserted since all values are valid - */ - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* set the DMA control register to the specified value */ - - XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET, Control); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_GetStatus -* -* DESCRIPTION: -* -* This function gets the status register contents of the DMA channel. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* RETURN VALUE: -* -* The status register contents of the DMA channel. One or more of the -* following values may be contained the register. Each of the values are -* unique bit masks. -* -* XDC_DMASR_BUSY_MASK The DMA channel is busy -* XDC_DMASR_BUS_ERROR_MASK A bus error occurred -* XDC_DMASR_BUS_TIMEOUT_MASK A bus timeout occurred -* XDC_DMASR_LAST_BD_MASK The last buffer descriptor of a packet -* -* NOTES: -* -* None. -* -******************************************************************************/ -u32 -XDmaChannel_GetStatus(XDmaChannel * InstancePtr) -{ - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* return the contents of the DMA status register */ - - return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_SetIntrStatus -* -* DESCRIPTION: -* -* This function sets the interrupt status register of the specified DMA channel. -* Setting any bit of the interrupt status register will clear the bit to -* indicate the interrupt processing has been completed. The definitions of each -* bit in the register match the definition of the bits in the interrupt enable -* register. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* Status contains the value to be written to the status register of the DMA -* channel. One or more of the following values may be contained the register. -* Each of the values are unique bit masks such that they may be ORed together -* to enable multiple bits or inverted and ANDed to disable multiple bits. -* -* XDC_IXR_DMA_DONE_MASK The dma operation is done -* XDC_IXR_DMA_ERROR_MASK The dma operation had an error -* XDC_IXR_PKT_DONE_MASK A packet is complete -* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached -* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached -* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed -* XDC_IXR_BD_MASK A buffer descriptor is done -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ -void -XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status) -{ - /* assert to verify input arguments except the status which can't be - * asserted since all values are valid - */ - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* set the interrupt status register with the specified value such that - * all bits which are set in the register are cleared effectively clearing - * any active interrupts - */ - XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, Status); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_GetIntrStatus -* -* DESCRIPTION: -* -* This function gets the interrupt status register of the specified DMA channel. -* The interrupt status register indicates which interrupts are active -* for the DMA channel. If an interrupt is active, the status register must be -* set (written) with the bit set for each interrupt which has been processed -* in order to clear the interrupts. The definitions of each bit in the register -* match the definition of the bits in the interrupt enable register. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* RETURN VALUE: -* -* The interrupt status register contents of the specified DMA channel. -* One or more of the following values may be contained the register. -* Each of the values are unique bit masks. -* -* XDC_IXR_DMA_DONE_MASK The dma operation is done -* XDC_IXR_DMA_ERROR_MASK The dma operation had an error -* XDC_IXR_PKT_DONE_MASK A packet is complete -* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached -* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached -* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed -* XDC_IXR_SG_END_MASK Current descriptor was the end of the list -* XDC_IXR_BD_MASK A buffer descriptor is done -* -* NOTES: -* -* None. -* -******************************************************************************/ -u32 -XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr) -{ - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* return the contents of the interrupt status register */ - - return XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_SetIntrEnable -* -* DESCRIPTION: -* -* This function sets the interrupt enable register of the specified DMA -* channel. The interrupt enable register contains bits which enable -* individual interrupts for the DMA channel. The definitions of each bit -* in the register match the definition of the bits in the interrupt status -* register. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* Enable contains the interrupt enable register contents to be written -* in the DMA channel. One or more of the following values may be contained -* the register. Each of the values are unique bit masks such that they may be -* ORed together to enable multiple bits or inverted and ANDed to disable -* multiple bits. -* -* XDC_IXR_DMA_DONE_MASK The dma operation is done -* XDC_IXR_DMA_ERROR_MASK The dma operation had an error -* XDC_IXR_PKT_DONE_MASK A packet is complete -* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached -* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached -* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed -* XDC_IXR_SG_END_MASK Current descriptor was the end of the list -* XDC_IXR_BD_MASK A buffer descriptor is done -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ -void -XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable) -{ - /* assert to verify input arguments except the enable which can't be - * asserted since all values are valid - */ - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* set the interrupt enable register to the specified value */ - - XIo_Out32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET, Enable); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_GetIntrEnable -* -* DESCRIPTION: -* -* This function gets the interrupt enable of the DMA channel. The -* interrupt enable contains flags which enable individual interrupts for the -* DMA channel. The definitions of each bit in the register match the definition -* of the bits in the interrupt status register. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* RETURN VALUE: -* -* The interrupt enable of the DMA channel. One or more of the following values -* may be contained the register. Each of the values are unique bit masks. -* -* XDC_IXR_DMA_DONE_MASK The dma operation is done -* XDC_IXR_DMA_ERROR_MASK The dma operation had an error -* XDC_IXR_PKT_DONE_MASK A packet is complete -* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached -* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached -* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed -* XDC_IXR_BD_MASK A buffer descriptor is done -* -* NOTES: -* -* None. -* -******************************************************************************/ -u32 -XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr) -{ - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* return the contents of the interrupt enable register */ - - return XIo_In32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_Transfer -* -* DESCRIPTION: -* -* This function starts the DMA channel transferring data from a memory source -* to a memory destination. This function only starts the operation and returns -* before the operation may be complete. If the interrupt is enabled, an -* interrupt will be generated when the operation is complete, otherwise it is -* necessary to poll the channel status to determine when it's complete. It is -* the responsibility of the caller to determine when the operation is complete -* by handling the generated interrupt or polling the status. It is also the -* responsibility of the caller to ensure that the DMA channel is not busy with -* another transfer before calling this function. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. -* -* SourcePtr contains a pointer to the source memory where the data is to -* be tranferred from and must be 32 bit aligned. -* -* DestinationPtr contains a pointer to the destination memory where the data -* is to be transferred and must be 32 bit aligned. -* -* ByteCount contains the number of bytes to transfer during the DMA operation. -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* The DMA h/w will not currently allow a non-local memory transfer to non-local -* memory (memory copy), but only allows a non-local memory to or from the device -* memory (typically a FIFO). -* -* It is the responsibility of the caller to ensure that the cache is -* flushed and invalidated both before and after the DMA operation completes -* if the memory pointed to is cached. The caller must also ensure that the -* pointers contain a physical address rather than a virtual address -* if address translation is being used. -* -******************************************************************************/ -void -XDmaChannel_Transfer(XDmaChannel * InstancePtr, - u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount) -{ - /* assert to verify input arguments and the alignment of any arguments - * which have expected alignments - */ - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(SourcePtr != NULL); - XASSERT_VOID(((u32) SourcePtr & 3) == 0); - XASSERT_VOID(DestinationPtr != NULL); - XASSERT_VOID(((u32) DestinationPtr & 3) == 0); - XASSERT_VOID(ByteCount != 0); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* setup the source and destination address registers for the transfer */ - - XIo_Out32(InstancePtr->RegBaseAddress + XDC_SA_REG_OFFSET, - (u32) SourcePtr); - - XIo_Out32(InstancePtr->RegBaseAddress + XDC_DA_REG_OFFSET, - (u32) DestinationPtr); - - /* start the DMA transfer to copy from the source buffer to the - * destination buffer by writing the length to the length register - */ - XIo_Out32(InstancePtr->RegBaseAddress + XDC_LEN_REG_OFFSET, ByteCount); -} diff --git a/board/xilinx/common/xdma_channel.h b/board/xilinx/common/xdma_channel.h deleted file mode 100644 index 06976c3..0000000 --- a/board/xilinx/common/xdma_channel.h +++ /dev/null @@ -1,291 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -* FILENAME: -* -* xdma_channel.h -* -* DESCRIPTION: -* -* This file contains the DMA channel component implementation. This component -* supports a distributed DMA design in which each device can have it's own -* dedicated DMA channel, as opposed to a centralized DMA design. -* A device which uses DMA typically contains two DMA channels, one for -* sending data and the other for receiving data. -* -* This component is designed to be used as a basic building block for -* designing a device driver. It provides registers accesses such that all -* DMA processing can be maintained easier, but the device driver designer -* must still understand all the details of the DMA channel. -* -* The DMA channel allows a CPU to minimize the CPU interaction required to move -* data between a memory and a device. The CPU requests the DMA channel to -* perform a DMA operation and typically continues performing other processing -* until the DMA operation completes. DMA could be considered a primitive form -* of multiprocessing such that caching and address translation can be an issue. -* -* Scatter Gather Operations -* -* The DMA channel may support scatter gather operations. A scatter gather -* operation automates the DMA channel such that multiple buffers can be -* sent or received with minimal software interaction with the hardware. Buffer -* descriptors, contained in the XBufDescriptor component, are used by the -* scatter gather operations of the DMA channel to describe the buffers to be -* processed. -* -* Scatter Gather List Operations -* -* A scatter gather list may be supported by each DMA channel. The scatter -* gather list allows buffer descriptors to be put into the list by a device -* driver which requires scatter gather. The hardware processes the buffer -* descriptors which are contained in the list and modifies the buffer -* descriptors to reflect the status of the DMA operations. The device driver -* is notified by interrupt that specific DMA events occur including scatter -* gather events. The device driver removes the completed buffer descriptors -* from the scatter gather list to evaluate the status of each DMA operation. -* -* The scatter gather list is created and buffer descriptors are inserted into -* the list. Buffer descriptors are never removed from the list after it's -* creation such that a put operation copies from a temporary buffer descriptor -* to a buffer descriptor in the list. Get operations don't copy from the list -* to a temporary, but return a pointer to the buffer descriptor in the list. -* A buffer descriptor in the list may be locked to prevent it from being -* overwritten by a put operation. This allows the device driver to get a -* descriptor from a scatter gather list and prevent it from being overwritten -* until the buffer associated with the buffer descriptor has been processed. -* -* Typical Scatter Gather Processing -* -* The following steps illustrate the typical processing to use the -* scatter gather features of a DMA channel. -* -* 1. Create a scatter gather list for the DMA channel which puts empty buffer -* descriptors into the list. -* 2. Create buffer descriptors which describe the buffers to be filled with -* receive data or the buffers which contain data to be sent. -* 3. Put buffer descriptors into the DMA channel scatter list such that scatter -* gather operations are requested. -* 4. Commit the buffer descriptors in the list such that they are ready to be -* used by the DMA channel hardware. -* 5. Start the scatter gather operations of the DMA channel. -* 6. Process any interrupts which occur as a result of the scatter gather -* operations or poll the DMA channel to determine the status. -* -* Interrupts -* -* Each DMA channel has the ability to generate an interrupt. This component -* does not perform processing for the interrupt as this processing is typically -* tightly coupled with the device which is using the DMA channel. It is the -* responsibility of the caller of DMA functions to manage the interrupt -* including connecting to the interrupt and enabling/disabling the interrupt. -* -* Critical Sections -* -* It is the responsibility of the device driver designer to use critical -* sections as necessary when calling functions of the DMA channel. This -* component does not use critical sections and it does access registers using -* read-modify-write operations. Calls to DMA functions from a main thread -* and from an interrupt context could produce unpredictable behavior such that -* the caller must provide the appropriate critical sections. -* -* Address Translation -* -* All addresses of data structures which are passed to DMA functions must -* be physical (real) addresses as opposed to logical (virtual) addresses. -* -* Caching -* -* The memory which is passed to the function which creates the scatter gather -* list must not be cached such that buffer descriptors are non-cached. This -* is necessary because the buffer descriptors are kept in a ring buffer and -* not directly accessible to the caller of DMA functions. -* -* The caller of DMA functions is responsible for ensuring that any data -* buffers which are passed to the DMA channel are cache-line aligned if -* necessary. -* -* The caller of DMA functions is responsible for ensuring that any data -* buffers which are passed to the DMA channel have been flushed from the cache. -* -* The caller of DMA functions is responsible for ensuring that the cache is -* invalidated prior to using any data buffers which are the result of a DMA -* operation. -* -* Memory Alignment -* -* The addresses of data buffers which are passed to DMA functions must be -* 32 bit word aligned since the DMA hardware performs 32 bit word transfers. -* -* Mutual Exclusion -* -* The functions of the DMA channel are not thread safe such that the caller -* of all DMA functions is responsible for ensuring mutual exclusion for a -* DMA channel. Mutual exclusion across multiple DMA channels is not -* necessary. -* -* NOTES: -* -* Many of the provided functions which are register accessors don't provide -* a lot of error detection. The caller is expected to understand the impact -* of a function call based upon the current state of the DMA channel. This -* is done to minimize the overhead in this component. -* -******************************************************************************/ - -#ifndef XDMA_CHANNEL_H /* prevent circular inclusions */ -#define XDMA_CHANNEL_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xdma_channel_i.h" /* constants shared with buffer descriptor */ -#include "xbasic_types.h" -#include "xstatus.h" -#include "xversion.h" -#include "xbuf_descriptor.h" - -/************************** Constant Definitions *****************************/ - -/* the following constants provide access to the bit fields of the DMA control - * register (DMACR) - */ -#define XDC_DMACR_SOURCE_INCR_MASK 0x80000000UL /* increment source address */ -#define XDC_DMACR_DEST_INCR_MASK 0x40000000UL /* increment dest address */ -#define XDC_DMACR_SOURCE_LOCAL_MASK 0x20000000UL /* local source address */ -#define XDC_DMACR_DEST_LOCAL_MASK 0x10000000UL /* local dest address */ -#define XDC_DMACR_SG_DISABLE_MASK 0x08000000UL /* scatter gather disable */ -#define XDC_DMACR_GEN_BD_INTR_MASK 0x04000000UL /* descriptor interrupt */ -#define XDC_DMACR_LAST_BD_MASK XDC_CONTROL_LAST_BD_MASK /* last buffer */ - /* descriptor */ - -/* the following constants provide access to the bit fields of the DMA status - * register (DMASR) - */ -#define XDC_DMASR_BUSY_MASK 0x80000000UL /* channel is busy */ -#define XDC_DMASR_BUS_ERROR_MASK 0x40000000UL /* bus error occurred */ -#define XDC_DMASR_BUS_TIMEOUT_MASK 0x20000000UL /* bus timeout occurred */ -#define XDC_DMASR_LAST_BD_MASK XDC_STATUS_LAST_BD_MASK /* last buffer */ - /* descriptor */ -#define XDC_DMASR_SG_BUSY_MASK 0x08000000UL /* scatter gather is busy */ - -/* the following constants provide access to the bit fields of the interrupt - * status register (ISR) and the interrupt enable register (IER), bit masks - * match for both registers such that they are named IXR - */ -#define XDC_IXR_DMA_DONE_MASK 0x1UL /* dma operation done */ -#define XDC_IXR_DMA_ERROR_MASK 0x2UL /* dma operation error */ -#define XDC_IXR_PKT_DONE_MASK 0x4UL /* packet done */ -#define XDC_IXR_PKT_THRESHOLD_MASK 0x8UL /* packet count threshold */ -#define XDC_IXR_PKT_WAIT_BOUND_MASK 0x10UL /* packet wait bound reached */ -#define XDC_IXR_SG_DISABLE_ACK_MASK 0x20UL /* scatter gather disable - acknowledge occurred */ -#define XDC_IXR_SG_END_MASK 0x40UL /* last buffer descriptor - disabled scatter gather */ -#define XDC_IXR_BD_MASK 0x80UL /* buffer descriptor done */ - -/**************************** Type Definitions *******************************/ - -/* - * the following structure contains data which is on a per instance basis - * for the XDmaChannel component - */ -typedef struct XDmaChannelTag { - XVersion Version; /* version of the driver */ - u32 RegBaseAddress; /* base address of registers */ - u32 IsReady; /* device is initialized and ready */ - - XBufDescriptor *PutPtr; /* keep track of where to put into list */ - XBufDescriptor *GetPtr; /* keep track of where to get from list */ - XBufDescriptor *CommitPtr; /* keep track of where to commit in list */ - XBufDescriptor *LastPtr; /* keep track of the last put in the list */ - u32 TotalDescriptorCount; /* total # of descriptors in the list */ - u32 ActiveDescriptorCount; /* # of descriptors pointing to buffers - * in the buffer descriptor list */ -} XDmaChannel; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -XStatus XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress); -u32 XDmaChannel_IsReady(XDmaChannel * InstancePtr); -XVersion *XDmaChannel_GetVersion(XDmaChannel * InstancePtr); -XStatus XDmaChannel_SelfTest(XDmaChannel * InstancePtr); -void XDmaChannel_Reset(XDmaChannel * InstancePtr); - -/* Control functions */ - -u32 XDmaChannel_GetControl(XDmaChannel * InstancePtr); -void XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control); - -/* Status functions */ - -u32 XDmaChannel_GetStatus(XDmaChannel * InstancePtr); -void XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status); -u32 XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr); -void XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable); -u32 XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr); - -/* DMA without scatter gather functions */ - -void XDmaChannel_Transfer(XDmaChannel * InstancePtr, - u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount); - -/* Scatter gather functions */ - -XStatus XDmaChannel_SgStart(XDmaChannel * InstancePtr); -XStatus XDmaChannel_SgStop(XDmaChannel * InstancePtr, - XBufDescriptor ** BufDescriptorPtr); -XStatus XDmaChannel_CreateSgList(XDmaChannel * InstancePtr, - u32 * MemoryPtr, u32 ByteCount); -u32 XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr); - -XStatus XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr, - XBufDescriptor * BufDescriptorPtr); -XStatus XDmaChannel_CommitPuts(XDmaChannel * InstancePtr); -XStatus XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr, - XBufDescriptor ** BufDescriptorPtr); - -/* Packet functions for interrupt collescing */ - -u32 XDmaChannel_GetPktCount(XDmaChannel * InstancePtr); -void XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr); -XStatus XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold); -u8 XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr); -void XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound); -u32 XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr); - -#endif /* end of protection macro */ diff --git a/board/xilinx/common/xdma_channel_i.h b/board/xilinx/common/xdma_channel_i.h deleted file mode 100644 index e9f343b..0000000 --- a/board/xilinx/common/xdma_channel_i.h +++ /dev/null @@ -1,110 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -* FILENAME: -* -* xdma_channel_i.h -* -* DESCRIPTION: -* -* This file contains data which is shared internal data for the DMA channel -* component. It is also shared with the buffer descriptor component which is -* very tightly coupled with the DMA channel component. -* -* NOTES: -* -* The last buffer descriptor constants must be located here to prevent a -* circular dependency between the DMA channel component and the buffer -* descriptor component. -* -******************************************************************************/ - -#ifndef XDMA_CHANNEL_I_H /* prevent circular inclusions */ -#define XDMA_CHANNEL_I_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xstatus.h" -#include "xversion.h" - -/************************** Constant Definitions *****************************/ - -#define XDC_DMA_CHANNEL_V1_00_A "1.00a" - -/* the following constant provides access to the bit fields of the DMA control - * register (DMACR) which must be shared between the DMA channel component - * and the buffer descriptor component - */ -#define XDC_CONTROL_LAST_BD_MASK 0x02000000UL /* last buffer descriptor */ - -/* the following constant provides access to the bit fields of the DMA status - * register (DMASR) which must be shared between the DMA channel component - * and the buffer descriptor component - */ -#define XDC_STATUS_LAST_BD_MASK 0x10000000UL /* last buffer descriptor */ - -/* the following constants provide access to each of the registers of a DMA - * channel - */ -#define XDC_RST_REG_OFFSET 0 /* reset register */ -#define XDC_MI_REG_OFFSET 0 /* module information register */ -#define XDC_DMAC_REG_OFFSET 4 /* DMA control register */ -#define XDC_SA_REG_OFFSET 8 /* source address register */ -#define XDC_DA_REG_OFFSET 12 /* destination address register */ -#define XDC_LEN_REG_OFFSET 16 /* length register */ -#define XDC_DMAS_REG_OFFSET 20 /* DMA status register */ -#define XDC_BDA_REG_OFFSET 24 /* buffer descriptor address register */ -#define XDC_SWCR_REG_OFFSET 28 /* software control register */ -#define XDC_UPC_REG_OFFSET 32 /* unserviced packet count register */ -#define XDC_PCT_REG_OFFSET 36 /* packet count threshold register */ -#define XDC_PWB_REG_OFFSET 40 /* packet wait bound register */ -#define XDC_IS_REG_OFFSET 44 /* interrupt status register */ -#define XDC_IE_REG_OFFSET 48 /* interrupt enable register */ - -/* the following constant is written to the reset register to reset the - * DMA channel - */ -#define XDC_RESET_MASK 0x0000000AUL - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -#endif /* end of protection macro */ diff --git a/board/xilinx/common/xdma_channel_sg.c b/board/xilinx/common/xdma_channel_sg.c deleted file mode 100644 index a8e9462..0000000 --- a/board/xilinx/common/xdma_channel_sg.c +++ /dev/null @@ -1,1317 +0,0 @@ -/* $Id: xdma_channel_sg.c,v 1.6 2003/02/03 19:50:33 moleres Exp $ */ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -* FILENAME: -* -* xdma_channel_sg.c -* -* DESCRIPTION: -* -* This file contains the implementation of the XDmaChannel component which is -* related to scatter gather operations. -* -* Scatter Gather Operations -* -* The DMA channel may support scatter gather operations. A scatter gather -* operation automates the DMA channel such that multiple buffers can be -* sent or received with minimal software interaction with the hardware. Buffer -* descriptors, contained in the XBufDescriptor component, are used by the -* scatter gather operations of the DMA channel to describe the buffers to be -* processed. -* -* Scatter Gather List Operations -* -* A scatter gather list may be supported by each DMA channel. The scatter -* gather list allows buffer descriptors to be put into the list by a device -* driver which requires scatter gather. The hardware processes the buffer -* descriptors which are contained in the list and modifies the buffer -* descriptors to reflect the status of the DMA operations. The device driver -* is notified by interrupt that specific DMA events occur including scatter -* gather events. The device driver removes the completed buffer descriptors -* from the scatter gather list to evaluate the status of each DMA operation. -* -* The scatter gather list is created and buffer descriptors are inserted into -* the list. Buffer descriptors are never removed from the list after it's -* creation such that a put operation copies from a temporary buffer descriptor -* to a buffer descriptor in the list. Get operations don't copy from the list -* to a temporary, but return a pointer to the buffer descriptor in the list. -* A buffer descriptor in the list may be locked to prevent it from being -* overwritten by a put operation. This allows the device driver to get a -* descriptor from a scatter gather list and prevent it from being overwritten -* until the buffer associated with the buffer descriptor has been processed. -* -* The get and put functions only operate on the list and are asynchronous from -* the hardware which may be using the list of descriptors. This is important -* because there are no checks in the get and put functions to ensure that the -* hardware has processed the descriptors. This must be handled by the driver -* using the DMA scatter gather channel through the use of the other functions. -* When a scatter gather operation is started, the start function does ensure -* that the descriptor to start has not already been processed by the hardware -* and is not the first of a series of descriptors that have not been committed -* yet. -* -* Descriptors are put into the list but not marked as ready to use by the -* hardware until a commit operation is done. This allows multiple descriptors -* which may contain a single packet of information for a protocol to be -* guaranteed not to cause any underflow conditions during transmission. The -* hardware design only allows descriptors to cause it to stop after a descriptor -* has been processed rather than before it is processed. A series of -* descriptors are put into the list followed by a commit operation, or each -* descriptor may be commited. A commit operation is performed by changing a -* single descriptor, the first of the series of puts, to indicate that the -* hardware may now use all descriptors after it. The last descriptor in the -* list is always set to cause the hardware to stop after it is processed. -* -* Typical Scatter Gather Processing -* -* The following steps illustrate the typical processing to use the -* scatter gather features of a DMA channel. -* -* 1. Create a scatter gather list for the DMA channel which puts empty buffer -* descriptors into the list. -* 2. Create buffer descriptors which describe the buffers to be filled with -* receive data or the buffers which contain data to be sent. -* 3. Put buffer descriptors into the DMA channel scatter list such that scatter -* gather operations are requested. -* 4. Commit the buffer descriptors in the list such that they are ready to be -* used by the DMA channel hardware. -* 5. Start the scatter gather operations of the DMA channel. -* 6. Process any interrupts which occur as a result of the scatter gather -* operations or poll the DMA channel to determine the status. This may -* be accomplished by getting the packet count for the channel and then -* getting the appropriate number of descriptors from the list for that -* number of packets. -* -* Minimizing Interrupts -* -* The Scatter Gather operating mode is designed to reduce the amount of CPU -* throughput necessary to manage the hardware for devices. A key to the CPU -* throughput is the number and rate of interrupts that the CPU must service. -* Devices with higher data rates can cause larger numbers of interrupts and -* higher frequency interrupts. Ideally the number of interrupts can be reduced -* by only generating an interrupt when a specific amount of data has been -* received from the interface. This design suffers from a lack of interrupts -* when the amount of data received is less than the specified amount of data -* to generate an interrupt. In order to help minimize the number of interrupts -* which the CPU must service, an algorithm referred to as "interrupt coalescing" -* is utilized. -* -* Interrupt Coalescing -* -* The principle of interrupt coalescing is to wait before generating an -* interrupt until a certain number of packets have been received or sent. An -* interrupt is also generated if a smaller number of packets have been received -* followed by a certain period of time with no packet reception. This is a -* trade-off of latency for bandwidth and is accomplished using several -* mechanisms of the hardware including a counter for packets received or -* transmitted and a packet timer. These two hardware mechanisms work in -* combination to allow a reduction in the number of interrupts processed by the -* CPU for packet reception. -* -* Unserviced Packet Count -* -* The purpose of the packet counter is to count the number of packets received -* or transmitted and provide an interrupt when a specific number of packets -* have been processed by the hardware. An interrupt is generated whenever the -* counter is greater than or equal to the Packet Count Threshold. This counter -* contains an accurate count of the number of packets that the hardware has -* processed, either received or transmitted, and the software has not serviced. -* -* The packet counter allows the number of interrupts to be reduced by waiting -* to generate an interrupt until enough packets are received. For packet -* reception, packet counts of less than the number to generate an interrupt -* would not be serviced without the addition of a packet timer. This counter is -* continuously updated by the hardware, not latched to the value at the time -* the interrupt occurred. -* -* The packet counter can be used within the interrupt service routine for the -* device to reduce the number of interrupts. The interrupt service routine -* loops while performing processing for each packet which has been received or -* transmitted and decrements the counter by a specified value. At the same time, -* the hardware is possibly continuing to receive or transmit more packets such -* that the software may choose, based upon the value in the packet counter, to -* remain in the interrupt service routine rather than exiting and immediately -* returning. This feature should be used with caution as reducing the number of -* interrupts is beneficial, but unbounded interrupt processing is not desirable. -* -* Since the hardware may be incrementing the packet counter simultaneously -* with the software decrementing the counter, there is a need for atomic -* operations. The hardware ensures that the operation is atomic such that -* simultaneous accesses are properly handled. -* -* Packet Wait Bound -* -* The purpose of the packet wait bound is to augment the unserviced packet -* count. Whenever there is no pending interrupt for the channel and the -* unserviced packet count is non-zero, a timer starts counting timeout at the -* value contained the the packet wait bound register. If the timeout is -* reached, an interrupt is generated such that the software may service the -* data which was buffered. -* -* NOTES: -* -* Special Test Conditions: -* -* The scatter gather list processing must be thoroughly tested if changes are -* made. Testing should include putting and committing single descriptors and -* putting multiple descriptors followed by a single commit. There are some -* conditions in the code which handle the exception conditions. -* -* The Put Pointer points to the next location in the descriptor list to copy -* in a new descriptor. The Get Pointer points to the next location in the -* list to get a descriptor from. The Get Pointer only allows software to -* have a traverse the list after the hardware has finished processing some -* number of descriptors. The Commit Pointer points to the descriptor in the -* list which is to be committed. It is also used to determine that no -* descriptor is waiting to be commited (NULL). The Last Pointer points to -* the last descriptor that was put into the list. It typically points -* to the previous descriptor to the one pointed to by the Put Pointer. -* Comparisons are done between these pointers to determine when the following -* special conditions exist. - -* Single Put And Commit -* -* The buffer descriptor is ready to be used by the hardware so it is important -* for the descriptor to not appear to be waiting to be committed. The commit -* pointer is reset when a commit is done indicating there are no descriptors -* waiting to be committed. In all cases but this one, the descriptor is -* changed to cause the hardware to go to the next descriptor after processing -* this one. But in this case, this is the last descriptor in the list such -* that it must not be changed. -* -* 3 Or More Puts And Commit -* -* A series of 3 or more puts followed by a single commit is different in that -* only the 1st descriptor put into the list is changed when the commit is done. -* This requires each put starting on the 3rd to change the previous descriptor -* so that it allows the hardware to continue to the next descriptor in the list. -* -* The 1st Put Following A Commit -* -* The commit caused the commit pointer to be NULL indicating that there are no -* descriptors waiting to be committed. It is necessary for the next put to set -* the commit pointer so that a commit must follow the put for the hardware to -* use the descriptor. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver	Who  Date     Changes
-* ----- ---- -------- ------------------------------------------------------
-* 1.00a rpm  02/03/03 Removed the XST_DMA_SG_COUNT_EXCEEDED return code
-*		      from SetPktThreshold.
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xdma_channel.h" -#include "xbasic_types.h" -#include "xio.h" -#include "xbuf_descriptor.h" -#include "xstatus.h" - -/************************** Constant Definitions *****************************/ - -#define XDC_SWCR_SG_ENABLE_MASK 0x80000000UL /* scatter gather enable */ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/* the following macro copies selected fields of a buffer descriptor to another - * buffer descriptor, this was provided by the buffer descriptor component but - * was moved here since it is only used internally to this component and since - * it does not copy all fields - */ -#define CopyBufferDescriptor(InstancePtr, DestinationPtr) \ -{ \ - *((u32 *)DestinationPtr + XBD_CONTROL_OFFSET) = \ - *((u32 *)InstancePtr + XBD_CONTROL_OFFSET); \ - *((u32 *)DestinationPtr + XBD_SOURCE_OFFSET) = \ - *((u32 *)InstancePtr + XBD_SOURCE_OFFSET); \ - *((u32 *)DestinationPtr + XBD_DESTINATION_OFFSET) = \ - *((u32 *)InstancePtr + XBD_DESTINATION_OFFSET); \ - *((u32 *)DestinationPtr + XBD_LENGTH_OFFSET) = \ - *((u32 *)InstancePtr + XBD_LENGTH_OFFSET); \ - *((u32 *)DestinationPtr + XBD_STATUS_OFFSET) = \ - *((u32 *)InstancePtr + XBD_STATUS_OFFSET); \ - *((u32 *)DestinationPtr + XBD_DEVICE_STATUS_OFFSET) = \ - *((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET); \ - *((u32 *)DestinationPtr + XBD_ID_OFFSET) = \ - *((u32 *)InstancePtr + XBD_ID_OFFSET); \ - *((u32 *)DestinationPtr + XBD_FLAGS_OFFSET) = \ - *((u32 *)InstancePtr + XBD_FLAGS_OFFSET); \ - *((u32 *)DestinationPtr + XBD_RQSTED_LENGTH_OFFSET) = \ - *((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET); \ -} - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_SgStart -* -* DESCRIPTION: -* -* This function starts a scatter gather operation for a scatter gather -* DMA channel. The first buffer descriptor in the buffer descriptor list -* will be started with the scatter gather operation. A scatter gather list -* should have previously been created for the DMA channel and buffer -* descriptors put into the scatter gather list such that there are scatter -* operations ready to be performed. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* RETURN VALUE: -* -* A status containing XST_SUCCESS if scatter gather was started successfully -* for the DMA channel. -* -* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not -* been created. -* -* A value of XST_DMA_SG_LIST_EMPTY indicates scatter gather was not started -* because the scatter gather list of the DMA channel does not contain any -* buffer descriptors that are ready to be processed by the hardware. -* -* A value of XST_DMA_SG_IS_STARTED indicates scatter gather was not started -* because the scatter gather was not stopped, but was already started. -* -* A value of XST_DMA_SG_BD_NOT_COMMITTED indicates the buffer descriptor of -* scatter gather list which was to be started is not committed to the list. -* This status is more likely if this function is being called from an ISR -* and non-ISR processing is putting descriptors into the list. -* -* A value of XST_DMA_SG_NO_DATA indicates that the buffer descriptor of the -* scatter gather list which was to be started had already been used by the -* hardware for a DMA transfer that has been completed. -* -* NOTES: -* -* It is the responsibility of the caller to get all the buffer descriptors -* after performing a stop operation and before performing a start operation. -* If buffer descriptors are not retrieved between stop and start operations, -* buffer descriptors may be processed by the hardware more than once. -* -******************************************************************************/ -XStatus -XDmaChannel_SgStart(XDmaChannel * InstancePtr) -{ - u32 Register; - XBufDescriptor *LastDescriptorPtr; - - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* if a scatter gather list has not been created yet, return a status */ - - if (InstancePtr->TotalDescriptorCount == 0) { - return XST_DMA_SG_NO_LIST; - } - - /* if the scatter gather list exists but is empty then return a status */ - - if (XDmaChannel_IsSgListEmpty(InstancePtr)) { - return XST_DMA_SG_LIST_EMPTY; - } - - /* if scatter gather is busy for the DMA channel, return a status because - * restarting it could lose data - */ - - Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET); - if (Register & XDC_DMASR_SG_BUSY_MASK) { - return XST_DMA_SG_IS_STARTED; - } - - /* get the address of the last buffer descriptor which the DMA hardware - * finished processing - */ - LastDescriptorPtr = - (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress + - XDC_BDA_REG_OFFSET); - - /* setup the first buffer descriptor that will be sent when the scatter - * gather channel is enabled, this is only necessary one time since - * the BDA register of the channel maintains the last buffer descriptor - * processed - */ - if (LastDescriptorPtr == NULL) { - XIo_Out32(InstancePtr->RegBaseAddress + XDC_BDA_REG_OFFSET, - (u32) InstancePtr->GetPtr); - } else { - XBufDescriptor *NextDescriptorPtr; - - /* get the next descriptor to be started, if the status indicates it - * hasn't already been used by the h/w, then it's OK to start it, - * s/w sets the status of each descriptor to busy and then h/w clears - * the busy when it is complete - */ - NextDescriptorPtr = - XBufDescriptor_GetNextPtr(LastDescriptorPtr); - - if ((XBufDescriptor_GetStatus(NextDescriptorPtr) & - XDC_DMASR_BUSY_MASK) == 0) { - return XST_DMA_SG_NO_DATA; - } - /* don't start the DMA SG channel if the descriptor to be processed - * by h/w is to be committed by the s/w, this function can be called - * such that it interrupts a thread that was putting into the list - */ - if (NextDescriptorPtr == InstancePtr->CommitPtr) { - return XST_DMA_SG_BD_NOT_COMMITTED; - } - } - - /* start the scatter gather operation by clearing the stop bit in the - * control register and setting the enable bit in the s/w control register, - * both of these are necessary to cause it to start, right now the order of - * these statements is important, the software control register should be - * set 1st. The other order can cause the CPU to have a loss of sync - * because it cannot read/write the register while the DMA operation is - * running - */ - - Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET); - - XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET, - Register | XDC_SWCR_SG_ENABLE_MASK); - - Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET); - - XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET, - Register & ~XDC_DMACR_SG_DISABLE_MASK); - - /* indicate the DMA channel scatter gather operation was started - * successfully - */ - return XST_SUCCESS; -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_SgStop -* -* DESCRIPTION: -* -* This function stops a scatter gather operation for a scatter gather -* DMA channel. This function starts the process of stopping a scatter -* gather operation that is in progress and waits for the stop to be completed. -* Since it waits for the operation to stopped before returning, this function -* could take an amount of time relative to the size of the DMA scatter gather -* operation which is in progress. The scatter gather list of the DMA channel -* is not modified by this function such that starting the scatter gather -* channel after stopping it will cause it to resume. This operation is -* considered to be a graceful stop in that the scatter gather operation -* completes the current buffer descriptor before stopping. -* -* If the interrupt is enabled, an interrupt will be generated when the -* operation is stopped and the caller is responsible for handling the -* interrupt. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* BufDescriptorPtr is also a return value which contains a pointer to the -* buffer descriptor which the scatter gather operation completed when it -* was stopped. -* -* RETURN VALUE: -* -* A status containing XST_SUCCESS if scatter gather was stopped successfully -* for the DMA channel. -* -* A value of XST_DMA_SG_IS_STOPPED indicates scatter gather was not stoppped -* because the scatter gather is not started, but was already stopped. -* -* BufDescriptorPtr contains a pointer to the buffer descriptor which was -* completed when the operation was stopped. -* -* NOTES: -* -* This function implements a loop which polls the hardware for an infinite -* amount of time. If the hardware is not operating correctly, this function -* may never return. -* -******************************************************************************/ -XStatus -XDmaChannel_SgStop(XDmaChannel * InstancePtr, - XBufDescriptor ** BufDescriptorPtr) -{ - u32 Register; - - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(BufDescriptorPtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* get the contents of the software control register, if scatter gather is not - * enabled (started), then return a status because the disable acknowledge - * would not be generated - */ - Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET); - - if ((Register & XDC_SWCR_SG_ENABLE_MASK) == 0) { - return XST_DMA_SG_IS_STOPPED; - } - - /* Ensure the interrupt status for the scatter gather is cleared such - * that this function will wait til the disable has occurred, writing - * a 1 to only that bit in the register will clear only it - */ - XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, - XDC_IXR_SG_DISABLE_ACK_MASK); - - /* disable scatter gather by writing to the software control register - * without modifying any other bits of the register - */ - XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET, - Register & ~XDC_SWCR_SG_ENABLE_MASK); - - /* scatter gather does not disable immediately, but after the current - * buffer descriptor is complete, so wait for the DMA channel to indicate - * the disable is complete - */ - do { - Register = - XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET); - } while ((Register & XDC_IXR_SG_DISABLE_ACK_MASK) == 0); - - /* Ensure the interrupt status for the scatter gather disable is cleared, - * writing a 1 to only that bit in the register will clear only it - */ - XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, - XDC_IXR_SG_DISABLE_ACK_MASK); - - /* set the specified buffer descriptor pointer to point to the buffer - * descriptor that the scatter gather DMA channel was processing - */ - *BufDescriptorPtr = - (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress + - XDC_BDA_REG_OFFSET); - - return XST_SUCCESS; -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_CreateSgList -* -* DESCRIPTION: -* -* This function creates a scatter gather list in the DMA channel. A scatter -* gather list consists of a list of buffer descriptors that are available to -* be used for scatter gather operations. Buffer descriptors are put into the -* list to request a scatter gather operation to be performed. -* -* A number of buffer descriptors are created from the specified memory and put -* into a buffer descriptor list as empty buffer descriptors. This function must -* be called before non-empty buffer descriptors may be put into the DMA channel -* to request scatter gather operations. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* MemoryPtr contains a pointer to the memory which is to be used for buffer -* descriptors and must not be cached. -* -* ByteCount contains the number of bytes for the specified memory to be used -* for buffer descriptors. -* -* RETURN VALUE: -* -* A status contains XST_SUCCESS if the scatter gather list was successfully -* created. -* -* A value of XST_DMA_SG_LIST_EXISTS indicates that the scatter gather list -* was not created because the list has already been created. -* -* NOTES: -* -* None. -* -******************************************************************************/ -XStatus -XDmaChannel_CreateSgList(XDmaChannel * InstancePtr, - u32 * MemoryPtr, u32 ByteCount) -{ - XBufDescriptor *BufferDescriptorPtr = (XBufDescriptor *) MemoryPtr; - XBufDescriptor *PreviousDescriptorPtr = NULL; - XBufDescriptor *StartOfListPtr = BufferDescriptorPtr; - u32 UsedByteCount; - - /* assert to verify valid input arguments, alignment for those - * arguments that have alignment restrictions, and at least enough - * memory for one buffer descriptor - */ - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(MemoryPtr != NULL); - XASSERT_NONVOID(((u32) MemoryPtr & 3) == 0); - XASSERT_NONVOID(ByteCount != 0); - XASSERT_NONVOID(ByteCount >= sizeof (XBufDescriptor)); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* if the scatter gather list has already been created, then return - * with a status - */ - if (InstancePtr->TotalDescriptorCount != 0) { - return XST_DMA_SG_LIST_EXISTS; - } - - /* loop thru the specified memory block and create as many buffer - * descriptors as possible putting each into the list which is - * implemented as a ring buffer, make sure not to use any memory which - * is not large enough for a complete buffer descriptor - */ - UsedByteCount = 0; - while ((UsedByteCount + sizeof (XBufDescriptor)) <= ByteCount) { - /* setup a pointer to the next buffer descriptor in the memory and - * update # of used bytes to know when all of memory is used - */ - BufferDescriptorPtr = (XBufDescriptor *) ((u32) MemoryPtr + - UsedByteCount); - - /* initialize the new buffer descriptor such that it doesn't contain - * garbage which could be used by the DMA hardware - */ - XBufDescriptor_Initialize(BufferDescriptorPtr); - - /* if this is not the first buffer descriptor to be created, - * then link it to the last created buffer descriptor - */ - if (PreviousDescriptorPtr != NULL) { - XBufDescriptor_SetNextPtr(PreviousDescriptorPtr, - BufferDescriptorPtr); - } - - /* always keep a pointer to the last created buffer descriptor such - * that they can be linked together in the ring buffer - */ - PreviousDescriptorPtr = BufferDescriptorPtr; - - /* keep a count of the number of descriptors in the list to allow - * error processing to be performed - */ - InstancePtr->TotalDescriptorCount++; - - UsedByteCount += sizeof (XBufDescriptor); - } - - /* connect the last buffer descriptor created and inserted in the list - * to the first such that a ring buffer is created - */ - XBufDescriptor_SetNextPtr(BufferDescriptorPtr, StartOfListPtr); - - /* initialize the ring buffer to indicate that there are no - * buffer descriptors in the list which point to valid data buffers - */ - InstancePtr->PutPtr = BufferDescriptorPtr; - InstancePtr->GetPtr = BufferDescriptorPtr; - InstancePtr->CommitPtr = NULL; - InstancePtr->LastPtr = BufferDescriptorPtr; - InstancePtr->ActiveDescriptorCount = 0; - - /* indicate the scatter gather list was successfully created */ - - return XST_SUCCESS; -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_IsSgListEmpty -* -* DESCRIPTION: -* -* This function determines if the scatter gather list of a DMA channel is -* empty with regard to buffer descriptors which are pointing to buffers to be -* used for scatter gather operations. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* RETURN VALUE: -* -* A value of TRUE if the scatter gather list is empty, otherwise a value of -* FALSE. -* -* NOTES: -* -* None. -* -******************************************************************************/ -u32 -XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr) -{ - /* assert to verify valid input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* if the number of descriptors which are being used in the list is zero - * then the list is empty - */ - return (InstancePtr->ActiveDescriptorCount == 0); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_PutDescriptor -* -* DESCRIPTION: -* -* This function puts a buffer descriptor into the DMA channel scatter -* gather list. A DMA channel maintains a list of buffer descriptors which are -* to be processed. This function puts the specified buffer descriptor -* at the next location in the list. Note that since the list is already intact, -* the information in the parameter is copied into the list (rather than modify -* list pointers on the fly). -* -* After buffer descriptors are put into the list, they must also be committed -* by calling another function. This allows multiple buffer descriptors which -* span a single packet to be put into the list while preventing the hardware -* from starting the first buffer descriptor of the packet. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* BufferDescriptorPtr is a pointer to the buffer descriptor to be put into -* the next available location of the scatter gather list. -* -* RETURN VALUE: -* -* A status which indicates XST_SUCCESS if the buffer descriptor was -* successfully put into the scatter gather list. -* -* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not -* been created. -* -* A value of XST_DMA_SG_LIST_FULL indicates the buffer descriptor was not -* put into the list because the list was full. -* -* A value of XST_DMA_SG_BD_LOCKED indicates the buffer descriptor was not -* put into the list because the buffer descriptor in the list which is to -* be overwritten was locked. A locked buffer descriptor indicates the higher -* layered software is still using the buffer descriptor. -* -* NOTES: -* -* It is necessary to create a scatter gather list for a DMA channel before -* putting buffer descriptors into it. -* -******************************************************************************/ -XStatus -XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr, - XBufDescriptor * BufferDescriptorPtr) -{ - u32 Control; - - /* assert to verify valid input arguments and alignment for those - * arguments that have alignment restrictions - */ - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(BufferDescriptorPtr != NULL); - XASSERT_NONVOID(((u32) BufferDescriptorPtr & 3) == 0); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* if a scatter gather list has not been created yet, return a status */ - - if (InstancePtr->TotalDescriptorCount == 0) { - return XST_DMA_SG_NO_LIST; - } - - /* if the list is full because all descriptors are pointing to valid - * buffers, then indicate an error, this code assumes no list or an - * empty list is detected above - */ - if (InstancePtr->ActiveDescriptorCount == - InstancePtr->TotalDescriptorCount) { - return XST_DMA_SG_LIST_FULL; - } - - /* if the buffer descriptor in the list which is to be overwritten is - * locked, then don't overwrite it and return a status - */ - if (XBufDescriptor_IsLocked(InstancePtr->PutPtr)) { - return XST_DMA_SG_BD_LOCKED; - } - - /* set the scatter gather stop bit in the control word of the descriptor - * to cause the h/w to stop after it processes this descriptor since it - * will be the last in the list - */ - Control = XBufDescriptor_GetControl(BufferDescriptorPtr); - XBufDescriptor_SetControl(BufferDescriptorPtr, - Control | XDC_DMACR_SG_DISABLE_MASK); - - /* set both statuses in the descriptor so we tell if they are updated with - * the status of the transfer, the hardware should change the busy in the - * DMA status to be false when it completes - */ - XBufDescriptor_SetStatus(BufferDescriptorPtr, XDC_DMASR_BUSY_MASK); - XBufDescriptor_SetDeviceStatus(BufferDescriptorPtr, 0); - - /* copy the descriptor into the next position in the list so it's ready to - * be used by the h/w, this assumes the descriptor in the list prior to this - * one still has the stop bit in the control word set such that the h/w - * use this one yet - */ - CopyBufferDescriptor(BufferDescriptorPtr, InstancePtr->PutPtr); - - /* only the last in the list and the one to be committed have scatter gather - * disabled in the control word, a commit requires only one descriptor - * to be changed, when # of descriptors to commit > 2 all others except the - * 1st and last have scatter gather enabled - */ - if ((InstancePtr->CommitPtr != InstancePtr->LastPtr) && - (InstancePtr->CommitPtr != NULL)) { - Control = XBufDescriptor_GetControl(InstancePtr->LastPtr); - XBufDescriptor_SetControl(InstancePtr->LastPtr, - Control & ~XDC_DMACR_SG_DISABLE_MASK); - } - - /* update the list data based upon putting a descriptor into the list, - * these operations must be last - */ - InstancePtr->ActiveDescriptorCount++; - - /* only update the commit pointer if it is not already active, this allows - * it to be deactivated after every commit such that a single descriptor - * which is committed does not appear to be waiting to be committed - */ - if (InstancePtr->CommitPtr == NULL) { - InstancePtr->CommitPtr = InstancePtr->LastPtr; - } - - /* these updates MUST BE LAST after the commit pointer update in order for - * the commit pointer to track the correct descriptor to be committed - */ - InstancePtr->LastPtr = InstancePtr->PutPtr; - InstancePtr->PutPtr = XBufDescriptor_GetNextPtr(InstancePtr->PutPtr); - - return XST_SUCCESS; -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_CommitPuts -* -* DESCRIPTION: -* -* This function commits the buffer descriptors which have been put into the -* scatter list for the DMA channel since the last commit operation was -* performed. This enables the calling functions to put several buffer -* descriptors into the list (e.g.,a packet's worth) before allowing the scatter -* gather operations to start. This prevents the DMA channel hardware from -* starting to use the buffer descriptors in the list before they are ready -* to be used (multiple buffer descriptors for a single packet). -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* RETURN VALUE: -* -* A status indicating XST_SUCCESS if the buffer descriptors of the list were -* successfully committed. -* -* A value of XST_DMA_SG_NOTHING_TO_COMMIT indicates that the buffer descriptors -* were not committed because there was nothing to commit in the list. All the -* buffer descriptors which are in the list are commited. -* -* NOTES: -* -* None. -* -******************************************************************************/ -XStatus -XDmaChannel_CommitPuts(XDmaChannel * InstancePtr) -{ - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* if the buffer descriptor to be committed is already committed or - * the list is empty (none have been put in), then indicate an error - */ - if ((InstancePtr->CommitPtr == NULL) || - XDmaChannel_IsSgListEmpty(InstancePtr)) { - return XST_DMA_SG_NOTHING_TO_COMMIT; - } - - /* last descriptor in the list must have scatter gather disabled so the end - * of the list is hit by h/w, if descriptor to commit is not last in list, - * commit descriptors by enabling scatter gather in the descriptor - */ - if (InstancePtr->CommitPtr != InstancePtr->LastPtr) { - u32 Control; - - Control = XBufDescriptor_GetControl(InstancePtr->CommitPtr); - XBufDescriptor_SetControl(InstancePtr->CommitPtr, Control & - ~XDC_DMACR_SG_DISABLE_MASK); - } - /* Update the commit pointer to indicate that there is nothing to be - * committed, this state is used by start processing to know that the - * buffer descriptor to start is not waiting to be committed - */ - InstancePtr->CommitPtr = NULL; - - return XST_SUCCESS; -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_GetDescriptor -* -* DESCRIPTION: -* -* This function gets a buffer descriptor from the scatter gather list of the -* DMA channel. The buffer descriptor is retrieved from the scatter gather list -* and the scatter gather list is updated to not include the retrieved buffer -* descriptor. This is typically done after a scatter gather operation -* completes indicating that a data buffer has been successfully sent or data -* has been received into the data buffer. The purpose of this function is to -* allow the device using the scatter gather operation to get the results of the -* operation. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* BufDescriptorPtr is a pointer to a pointer to the buffer descriptor which -* was retrieved from the list. The buffer descriptor is not really removed -* from the list, but it is changed to a state such that the hardware will not -* use it again until it is put into the scatter gather list of the DMA channel. -* -* RETURN VALUE: -* -* A status indicating XST_SUCCESS if a buffer descriptor was retrieved from -* the scatter gather list of the DMA channel. -* -* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not -* been created. -* -* A value of XST_DMA_SG_LIST_EMPTY indicates no buffer descriptor was -* retrieved from the list because there are no buffer descriptors to be -* processed in the list. -* -* BufDescriptorPtr is updated to point to the buffer descriptor which was -* retrieved from the list if the status indicates success. -* -* NOTES: -* -* None. -* -******************************************************************************/ -XStatus -XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr, - XBufDescriptor ** BufDescriptorPtr) -{ - u32 Control; - - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(BufDescriptorPtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* if a scatter gather list has not been created yet, return a status */ - - if (InstancePtr->TotalDescriptorCount == 0) { - return XST_DMA_SG_NO_LIST; - } - - /* if the buffer descriptor list is empty, then indicate an error */ - - if (XDmaChannel_IsSgListEmpty(InstancePtr)) { - return XST_DMA_SG_LIST_EMPTY; - } - - /* retrieve the next buffer descriptor which is ready to be processed from - * the buffer descriptor list for the DMA channel, set the control word - * such that hardware will stop after the descriptor has been processed - */ - Control = XBufDescriptor_GetControl(InstancePtr->GetPtr); - XBufDescriptor_SetControl(InstancePtr->GetPtr, - Control | XDC_DMACR_SG_DISABLE_MASK); - - /* set the input argument, which is also an output, to point to the - * buffer descriptor which is to be retrieved from the list - */ - *BufDescriptorPtr = InstancePtr->GetPtr; - - /* update the pointer of the DMA channel to reflect the buffer descriptor - * was retrieved from the list by setting it to the next buffer descriptor - * in the list and indicate one less descriptor in the list now - */ - InstancePtr->GetPtr = XBufDescriptor_GetNextPtr(InstancePtr->GetPtr); - InstancePtr->ActiveDescriptorCount--; - - return XST_SUCCESS; -} - -/*********************** Interrupt Collescing Functions **********************/ - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_GetPktCount -* -* DESCRIPTION: -* -* This function returns the value of the unserviced packet count register of -* the DMA channel. This count represents the number of packets that have been -* sent or received by the hardware, but not processed by software. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* RETURN VALUE: -* -* The unserviced packet counter register contents for the DMA channel. -* -* NOTES: -* -* None. -* -******************************************************************************/ -u32 -XDmaChannel_GetPktCount(XDmaChannel * InstancePtr) -{ - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* get the unserviced packet count from the register and return it */ - - return XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_DecrementPktCount -* -* DESCRIPTION: -* -* This function decrements the value of the unserviced packet count register. -* This informs the hardware that the software has processed a packet. The -* unserviced packet count register may only be decremented by one in the -* hardware. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ -void -XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr) -{ - u32 Register; - - /* assert to verify input arguments */ - - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* if the unserviced packet count register can be decremented (rather - * than rolling over) decrement it by writing a 1 to the register, - * this is the only valid write to the register as it serves as an - * acknowledge that a packet was handled by the software - */ - Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET); - if (Register > 0) { - XIo_Out32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET, - 1UL); - } -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_SetPktThreshold -* -* DESCRIPTION: -* -* This function sets the value of the packet count threshold register of the -* DMA channel. It reflects the number of packets that must be sent or -* received before generating an interrupt. This value helps implement -* a concept called "interrupt coalescing", which is used to reduce the number -* of interrupts from devices with high data rates. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* Threshold is the value that is written to the threshold register of the -* DMA channel. -* -* RETURN VALUE: -* -* A status containing XST_SUCCESS if the packet count threshold was -* successfully set. -* -* NOTES: -* -* The packet threshold could be set to larger than the number of descriptors -* allocated to the DMA channel. In this case, the wait bound will take over -* and always indicate data arrival. There was a check in this function that -* returned an error if the treshold was larger than the number of descriptors, -* but that was removed because users would then have to set the threshold -* only after they set descriptor space, which is an order dependency that -* caused confustion. -* -******************************************************************************/ -XStatus -XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold) -{ - /* assert to verify input arguments, don't assert the threshold since - * it's range is unknown - */ - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* set the packet count threshold in the register such that an interrupt - * may be generated, if enabled, when the packet count threshold is - * reached or exceeded - */ - XIo_Out32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET, - (u32) Threshold); - - /* indicate the packet count threshold was successfully set */ - - return XST_SUCCESS; -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_GetPktThreshold -* -* DESCRIPTION: -* -* This function gets the value of the packet count threshold register of the -* DMA channel. This value reflects the number of packets that must be sent or -* received before generating an interrupt. This value helps implement a concept -* called "interrupt coalescing", which is used to reduce the number of -* interrupts from devices with high data rates. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* RETURN VALUE: -* -* The packet threshold register contents for the DMA channel and is a value in -* the range 0 - 1023. A value of 0 indicates the packet wait bound timer is -* disabled. -* -* NOTES: -* -* None. -* -******************************************************************************/ -u8 -XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr) -{ - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* get the packet count threshold from the register and return it, - * since only 8 bits are used, cast it to return only those bits */ - - return (u8) XIo_In32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_SetPktWaitBound -* -* DESCRIPTION: -* -* This function sets the value of the packet wait bound register of the -* DMA channel. This value reflects the timer value used to trigger an -* interrupt when not enough packets have been received to reach the packet -* count threshold. -* -* The timer is in millisecond units with +/- 33% accuracy. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* WaitBound is the value, in milliseconds, to be stored in the wait bound -* register of the DMA channel and is a value in the range 0 - 1023. A value -* of 0 disables the packet wait bound timer. -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ -void -XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound) -{ - /* assert to verify input arguments */ - - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(WaitBound < 1024); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* set the packet wait bound in the register such that interrupt may be - * generated, if enabled, when packets have not been handled for a specific - * amount of time - */ - XIo_Out32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET, WaitBound); -} - -/****************************************************************************** -* -* FUNCTION: -* -* XDmaChannel_GetPktWaitBound -* -* DESCRIPTION: -* -* This function gets the value of the packet wait bound register of the -* DMA channel. This value contains the timer value used to trigger an -* interrupt when not enough packets have been received to reach the packet -* count threshold. -* -* The timer is in millisecond units with +/- 33% accuracy. -* -* ARGUMENTS: -* -* InstancePtr contains a pointer to the DMA channel to operate on. The DMA -* channel should be configured to use scatter gather in order for this function -* to be called. -* -* RETURN VALUE: -* -* The packet wait bound register contents for the DMA channel. -* -* NOTES: -* -* None. -* -******************************************************************************/ -u32 -XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr) -{ - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* get the packet wait bound from the register and return it */ - - return XIo_In32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET); -} diff --git a/board/xilinx/common/xio.h b/board/xilinx/common/xio.h deleted file mode 100644 index 5bb09c8..0000000 --- a/board/xilinx/common/xio.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * xio.h - * - * Defines XIo functions for Xilinx OCP in terms of Linux primitives - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * Copyright 2002 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR - * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef XIO_H -#define XIO_H - -#include "xbasic_types.h" -#include - -typedef u32 XIo_Address; - -extern inline u8 -XIo_In8(XIo_Address InAddress) -{ - return (u8) in_8((volatile unsigned char *) InAddress); -} -extern inline u16 -XIo_In16(XIo_Address InAddress) -{ - return (u16) in_be16((volatile unsigned short *) InAddress); -} -extern inline u32 -XIo_In32(XIo_Address InAddress) -{ - return (u32) in_be32((volatile unsigned *) InAddress); -} -extern inline void -XIo_Out8(XIo_Address OutAddress, u8 Value) -{ - out_8((volatile unsigned char *) OutAddress, Value); -} -extern inline void -XIo_Out16(XIo_Address OutAddress, u16 Value) -{ - out_be16((volatile unsigned short *) OutAddress, Value); -} -extern inline void -XIo_Out32(XIo_Address OutAddress, u32 Value) -{ - out_be32((volatile unsigned *) OutAddress, Value); -} - -#define XIo_ToLittleEndian16(s,d) (*(u16*)(d) = cpu_to_le16((u16)(s))) -#define XIo_ToLittleEndian32(s,d) (*(u32*)(d) = cpu_to_le32((u32)(s))) -#define XIo_ToBigEndian16(s,d) (*(u16*)(d) = cpu_to_be16((u16)(s))) -#define XIo_ToBigEndian32(s,d) (*(u32*)(d) = cpu_to_be32((u32)(s))) - -#define XIo_FromLittleEndian16(s,d) (*(u16*)(d) = le16_to_cpu((u16)(s))) -#define XIo_FromLittleEndian32(s,d) (*(u32*)(d) = le32_to_cpu((u32)(s))) -#define XIo_FromBigEndian16(s,d) (*(u16*)(d) = be16_to_cpu((u16)(s))) -#define XIo_FromBigEndian32(s,d) (*(u32*)(d) = be32_to_cpu((u32)(s))) - -#endif /* XIO_H */ diff --git a/board/xilinx/common/xipif_v1_23_b.c b/board/xilinx/common/xipif_v1_23_b.c deleted file mode 100644 index c7311ab..0000000 --- a/board/xilinx/common/xipif_v1_23_b.c +++ /dev/null @@ -1,331 +0,0 @@ -/* $Id: xipif_v1_23_b.c,v 1.1 2002/03/18 23:24:52 linnj Exp $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/****************************************************************************** -* -* FILENAME: -* -* xipif.c -* -* DESCRIPTION: -* -* This file contains the implementation of the XIpIf component. The -* XIpIf component encapsulates the IPIF, which is the standard interface -* that IP must adhere to when connecting to a bus. The purpose of this -* component is to encapsulate the IPIF processing such that maintainability -* is increased. This component does not provide a lot of abstraction from -* from the details of the IPIF as it is considered a building block for -* device drivers. A device driver designer must be familiar with the -* details of the IPIF hardware to use this component. -* -* The IPIF hardware provides a building block for all hardware devices such -* that each device does not need to reimplement these building blocks. The -* IPIF contains other building blocks, such as FIFOs and DMA channels, which -* are also common to many devices. These blocks are implemented as separate -* hardware blocks and instantiated within the IPIF. The primary hardware of -* the IPIF which is implemented by this software component is the interrupt -* architecture. Since there are many blocks of a device which may generate -* interrupts, all the interrupt processing is contained in the common part -* of the device, the IPIF. This interrupt processing is for the device level -* only and does not include any processing for the interrupt controller. -* -* A device is a mechanism such as an Ethernet MAC. The device is made -* up of several parts which include an IPIF and the IP. The IPIF contains most -* of the device infrastructure which is common to all devices, such as -* interrupt processing, DMA channels, and FIFOs. The infrastructure may also -* be referred to as IPIF internal blocks since they are part of the IPIF and -* are separate blocks that can be selected based upon the needs of the device. -* The IP of the device is the logic that is unique to the device and interfaces -* to the IPIF of the device. -* -* In general, there are two levels of registers within the IPIF. The first -* level, referred to as the device level, contains registers which are for the -* entire device. The second level, referred to as the IP level, contains -* registers which are specific to the IP of the device. The two levels of -* registers are designed to be hierarchical such that the device level is -* is a more general register set above the more specific registers of the IP. -* The IP level of registers provides functionality which is typically common -* across all devices and allows IP designers to focus on the unique aspects -* of the IP. -* -* The interrupt registers of the IPIF are parameterizable such that the only -* the number of bits necessary for the device are implemented. The functions -* of this component do not attempt to validate that the passed in arguments are -* valid based upon the number of implemented bits. This is necessary to -* maintain the level of performance required for the common components. Bits -* of the registers are assigned starting at the least significant bit of the -* registers. -* -* Critical Sections -* -* It is the responsibility of the device driver designer to use critical -* sections as necessary when calling functions of the IPIF. This component -* does not use critical sections and it does access registers using -* read-modify-write operations. Calls to IPIF functions from a main thread -* and from an interrupt context could produce unpredictable behavior such that -* the caller must provide the appropriate critical sections. -* -* Mutual Exclusion -* -* The functions of the IPIF are not thread safe such that the caller of all -* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual -* exclusion across multiple IPIF components is not necessary. -* -* NOTES: -* -* None. -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.23b jhl 02/27/01 Repartioned to reduce size -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xipif_v1_23_b.h" -#include "xio.h" - -/************************** Constant Definitions *****************************/ - -/* the following constant is used to generate bit masks for register testing - * in the self test functions, it defines the starting bit mask that is to be - * shifted from the LSB to MSB in creating a register test mask - */ -#define XIIF_V123B_FIRST_BIT_MASK 1UL - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -static XStatus IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth); - -/****************************************************************************** -* -* FUNCTION: -* -* XIpIf_SelfTest -* -* DESCRIPTION: -* -* This function performs a self test on the specified IPIF component. Many -* of the registers in the IPIF are tested to ensure proper operation. This -* function is destructive because the IPIF is reset at the start of the test -* and at the end of the test to ensure predictable results. The IPIF reset -* also resets the entire device that uses the IPIF. This function exits with -* all interrupts for the device disabled. -* -* ARGUMENTS: -* -* InstancePtr points to the XIpIf to operate on. -* -* DeviceRegistersWidth contains the number of bits in the device interrupt -* registers. The hardware is parameterizable such that only the number of bits -* necessary to support a device are implemented. This value must be between 0 -* and 32 with 0 indicating there are no device interrupt registers used. -* -* IpRegistersWidth contains the number of bits in the IP interrupt registers -* of the device. The hardware is parameterizable such that only the number of -* bits necessary to support a device are implemented. This value must be -* between 0 and 32 with 0 indicating there are no IP interrupt registers used. -* -* RETURN VALUE: -* -* A value of XST_SUCCESS indicates the test was successful with no errors. -* Any one of the following error values may also be returned. -* -* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was -* not valid -* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status -* register did not read back correctly -* XST_IPIF_IP_ACK_ERROR One or more bits in the IP interrupt -* status register did not reset when acked -* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register -* did not read back correctly based upon -* what was written to it -* -* NOTES: -* -* None. -* -******************************************************************************/ - -/* the following constant defines the maximum number of bits which may be - * used in the registers at the device and IP levels, this is based upon the - * number of bits available in the registers - */ -#define XIIF_V123B_MAX_REG_BIT_COUNT 32 - -XStatus -XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth) -{ - XStatus Status; - - /* assert to verify arguments are valid */ - - XASSERT_NONVOID(IpRegistersWidth <= XIIF_V123B_MAX_REG_BIT_COUNT); - - /* reset the IPIF such that it's in a known state before the test - * and interrupts are globally disabled - */ - XIIF_V123B_RESET(RegBaseAddress); - - /* perform the self test on the IP interrupt registers, if - * it is not successful exit with the status - */ - Status = IpIntrSelfTest(RegBaseAddress, IpRegistersWidth); - if (Status != XST_SUCCESS) { - return Status; - } - - /* reset the IPIF such that it's in a known state before exiting test */ - - XIIF_V123B_RESET(RegBaseAddress); - - /* reaching this point means there were no errors, return success */ - - return XST_SUCCESS; -} - -/****************************************************************************** -* -* FUNCTION: -* -* IpIntrSelfTest -* -* DESCRIPTION: -* -* Perform a self test on the IP interrupt registers of the IPIF. This -* function modifies registers of the IPIF such that they are not guaranteed -* to be in the same state when it returns. Any bits in the IP interrupt -* status register which are set are assumed to be set by default after a reset -* and are not tested in the test. -* -* ARGUMENTS: -* -* InstancePtr points to the XIpIf to operate on. -* -* IpRegistersWidth contains the number of bits in the IP interrupt registers -* of the device. The hardware is parameterizable such that only the number of -* bits necessary to support a device are implemented. This value must be -* between 0 and 32 with 0 indicating there are no IP interrupt registers used. -* -* RETURN VALUE: -* -* A status indicating XST_SUCCESS if the test was successful. Otherwise, one -* of the following values is returned. -* -* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was -* not valid -* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status -* register did not read back correctly -* XST_IPIF_IP_ACK_ERROR One or more bits in the IP status -* register did not reset when acked -* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register -* did not read back correctly based upon -* what was written to it -* NOTES: -* -* None. -* -******************************************************************************/ -static XStatus -IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth) -{ - /* ensure that the IP interrupt interrupt enable register is zero - * as it should be at reset, the interrupt status is dependent upon the - * IP such that it's reset value is not known - */ - if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) { - return XST_IPIF_RESET_REGISTER_ERROR; - } - - /* if there are any used IP interrupts, then test all of the interrupt - * bits in all testable registers - */ - if (IpRegistersWidth > 0) { - u32 BitCount; - u32 IpInterruptMask = XIIF_V123B_FIRST_BIT_MASK; - u32 Mask = XIIF_V123B_FIRST_BIT_MASK; /* bits assigned MSB to LSB */ - u32 InterruptStatus; - - /* generate the register masks to be used for IP register tests, the - * number of bits supported by the hardware is parameterizable such - * that only that number of bits are implemented in the registers, the - * bits are allocated starting at the MSB of the registers - */ - for (BitCount = 1; BitCount < IpRegistersWidth; BitCount++) { - Mask = Mask << 1; - IpInterruptMask |= Mask; - } - - /* get the current IP interrupt status register contents, any bits - * already set must default to 1 at reset in the device and these - * bits can't be tested in the following test, remove these bits from - * the mask that was generated for the test - */ - InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress); - IpInterruptMask &= ~InterruptStatus; - - /* set the bits in the device status register and verify them by reading - * the register again, all bits of the register are latched - */ - XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask); - InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress); - if ((InterruptStatus & IpInterruptMask) != IpInterruptMask) - { - return XST_IPIF_IP_STATUS_ERROR; - } - - /* test to ensure that the bits set in the IP interrupt status register - * can be cleared by acknowledging them in the IP interrupt status - * register then read it again and verify it was cleared - */ - XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask); - InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress); - if ((InterruptStatus & IpInterruptMask) != 0) { - return XST_IPIF_IP_ACK_ERROR; - } - - /* set the IP interrupt enable set register and then read the IP - * interrupt enable register and verify the interrupts were enabled - */ - XIIF_V123B_WRITE_IIER(RegBaseAddress, IpInterruptMask); - if (XIIF_V123B_READ_IIER(RegBaseAddress) != IpInterruptMask) { - return XST_IPIF_IP_ENABLE_ERROR; - } - - /* clear the IP interrupt enable register and then read the - * IP interrupt enable register and verify the interrupts were disabled - */ - XIIF_V123B_WRITE_IIER(RegBaseAddress, 0); - if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) { - return XST_IPIF_IP_ENABLE_ERROR; - } - } - return XST_SUCCESS; -} diff --git a/board/xilinx/common/xipif_v1_23_b.h b/board/xilinx/common/xipif_v1_23_b.h deleted file mode 100644 index 3ce1fff..0000000 --- a/board/xilinx/common/xipif_v1_23_b.h +++ /dev/null @@ -1,746 +0,0 @@ -/* $Id: xipif_v1_23_b.h,v 1.1 2002/03/18 23:24:52 linnj Exp $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/****************************************************************************** -* -* FILENAME: -* -* xipif.h -* -* DESCRIPTION: -* -* The XIpIf component encapsulates the IPIF, which is the standard interface -* that IP must adhere to when connecting to a bus. The purpose of this -* component is to encapsulate the IPIF processing such that maintainability -* is increased. This component does not provide a lot of abstraction from -* from the details of the IPIF as it is considered a building block for -* device drivers. A device driver designer must be familiar with the -* details of the IPIF hardware to use this component. -* -* The IPIF hardware provides a building block for all hardware devices such -* that each device does not need to reimplement these building blocks. The -* IPIF contains other building blocks, such as FIFOs and DMA channels, which -* are also common to many devices. These blocks are implemented as separate -* hardware blocks and instantiated within the IPIF. The primary hardware of -* the IPIF which is implemented by this software component is the interrupt -* architecture. Since there are many blocks of a device which may generate -* interrupts, all the interrupt processing is contained in the common part -* of the device, the IPIF. This interrupt processing is for the device level -* only and does not include any processing for the interrupt controller. -* -* A device is a mechanism such as an Ethernet MAC. The device is made -* up of several parts which include an IPIF and the IP. The IPIF contains most -* of the device infrastructure which is common to all devices, such as -* interrupt processing, DMA channels, and FIFOs. The infrastructure may also -* be referred to as IPIF internal blocks since they are part of the IPIF and -* are separate blocks that can be selected based upon the needs of the device. -* The IP of the device is the logic that is unique to the device and interfaces -* to the IPIF of the device. -* -* In general, there are two levels of registers within the IPIF. The first -* level, referred to as the device level, contains registers which are for the -* entire device. The second level, referred to as the IP level, contains -* registers which are specific to the IP of the device. The two levels of -* registers are designed to be hierarchical such that the device level is -* is a more general register set above the more specific registers of the IP. -* The IP level of registers provides functionality which is typically common -* across all devices and allows IP designers to focus on the unique aspects -* of the IP. -* -* Critical Sections -* -* It is the responsibility of the device driver designer to use critical -* sections as necessary when calling functions of the IPIF. This component -* does not use critical sections and it does access registers using -* read-modify-write operations. Calls to IPIF functions from a main thread -* and from an interrupt context could produce unpredictable behavior such that -* the caller must provide the appropriate critical sections. -* -* Mutual Exclusion -* -* The functions of the IPIF are not thread safe such that the caller of all -* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual -* exclusion across multiple IPIF components is not necessary. -* -* NOTES: -* -* None. -* -* MODIFICATION HISTORY: -* -* Ver Who Date Changes -* ----- ---- -------- ----------------------------------------------- -* 1.23b jhl 02/27/01 Repartioned to minimize size -* -******************************************************************************/ - -#ifndef XIPIF_H /* prevent circular inclusions */ -#define XIPIF_H /* by using protection macros */ - -/***************************** Include Files *********************************/ -#include "xbasic_types.h" -#include "xstatus.h" -#include "xversion.h" - -/************************** Constant Definitions *****************************/ - -/* the following constants define the register offsets for the registers of the - * IPIF, there are some holes in the memory map for reserved addresses to allow - * other registers to be added and still match the memory map of the interrupt - * controller registers - */ -#define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */ -#define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */ -#define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */ -#define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */ -#define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */ -#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ -#define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */ -#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ - -#define XIIF_V123B_RESET_MASK 0xAUL - -/* the following constant is used for the device global interrupt enable - * register, to enable all interrupts for the device, this is the only bit - * in the register - */ -#define XIIF_V123B_GINTR_ENABLE_MASK 0x80000000UL - -/* the following constants contain the masks to identify each internal IPIF - * condition in the device registers of the IPIF, interrupts are assigned - * in the register from LSB to the MSB - */ -#define XIIF_V123B_ERROR_MASK 1UL /* LSB of the register */ - -/* The following constants contain interrupt IDs which identify each internal - * IPIF condition, this value must correlate with the mask constant for the - * error - */ -#define XIIF_V123B_ERROR_INTERRUPT_ID 0 /* interrupt bit #, (LSB = 0) */ -#define XIIF_V123B_NO_INTERRUPT_ID 128 /* no interrupts are pending */ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_RESET -* -* DESCRIPTION: -* -* Reset the IPIF component and hardware. This is a destructive operation that -* could cause the loss of data since resetting the IPIF of a device also -* resets the device using the IPIF and any blocks, such as FIFOs or DMA -* channels, within the IPIF. All registers of the IPIF will contain their -* reset value when this function returns. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ - -/* the following constant is used in the reset register to cause the IPIF to - * reset - */ -#define XIIF_V123B_RESET(RegBaseAddress) \ - XIo_Out32(RegBaseAddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_WRITE_DISR -* -* DESCRIPTION: -* -* This function sets the device interrupt status register to the value. -* This register indicates the status of interrupt sources for a device -* which contains the IPIF. The status is independent of whether interrupts -* are enabled and could be used for polling a device at a higher level rather -* than a more detailed level. -* -* Each bit of the register correlates to a specific interrupt source within the -* device which contains the IPIF. With the exception of some internal IPIF -* conditions, the contents of this register are not latched but indicate -* the live status of the interrupt sources within the device. Writing any of -* the non-latched bits of the register will have no effect on the register. -* -* For the latched bits of this register only, setting a bit which is zero -* within this register causes an interrupt to generated. The device global -* interrupt enable register and the device interrupt enable register must be set -* appropriately to allow an interrupt to be passed out of the device. The -* interrupt is cleared by writing to this register with the bits to be -* cleared set to a one and all others to zero. This register implements a -* toggle on write functionality meaning any bits which are set in the value -* written cause the bits in the register to change to the opposite state. -* -* This function writes the specified value to the register such that -* some bits may be set and others cleared. It is the caller's responsibility -* to get the value of the register prior to setting the value to prevent a -* destructive behavior. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* Status contains the value to be written to the interrupt status register of -* the device. The only bits which can be written are the latched bits which -* contain the internal IPIF conditions. The following values may be used to -* set the status register or clear an interrupt condition. -* -* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ -#define XIIF_V123B_WRITE_DISR(RegBaseAddress, Status) \ - XIo_Out32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET, (Status)) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_READ_DISR -* -* DESCRIPTION: -* -* This function gets the device interrupt status register contents. -* This register indicates the status of interrupt sources for a device -* which contains the IPIF. The status is independent of whether interrupts -* are enabled and could be used for polling a device at a higher level. -* -* Each bit of the register correlates to a specific interrupt source within the -* device which contains the IPIF. With the exception of some internal IPIF -* conditions, the contents of this register are not latched but indicate -* the live status of the interrupt sources within the device. -* -* For only the latched bits of this register, the interrupt may be cleared by -* writing to these bits in the status register. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* RETURN VALUE: -* -* A status which contains the value read from the interrupt status register of -* the device. The bit definitions are specific to the device with -* the exception of the latched internal IPIF condition bits. The following -* values may be used to detect internal IPIF conditions in the status. -* -* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF -* -* NOTES: -* -* None. -* -******************************************************************************/ -#define XIIF_V123B_READ_DISR(RegBaseAddress) \ - XIo_In32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_WRITE_DIER -* -* DESCRIPTION: -* -* This function sets the device interrupt enable register contents. -* This register controls which interrupt sources of the device are allowed to -* generate an interrupt. The device global interrupt enable register must also -* be set appropriately for an interrupt to be passed out of the device. -* -* Each bit of the register correlates to a specific interrupt source within the -* device which contains the IPIF. Setting a bit in this register enables that -* interrupt source to generate an interrupt. Clearing a bit in this register -* disables interrupt generation for that interrupt source. -* -* This function writes only the specified value to the register such that -* some interrupts source may be enabled and others disabled. It is the -* caller's responsibility to get the value of the interrupt enable register -* prior to setting the value to prevent an destructive behavior. -* -* An interrupt source may not be enabled to generate an interrupt, but can -* still be polled in the interrupt status register. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* Enable contains the value to be written to the interrupt enable register -* of the device. The bit definitions are specific to the device with -* the exception of the internal IPIF conditions. The following -* values may be used to enable the internal IPIF conditions interrupts. -* -* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* Signature: u32 XIIF_V123B_WRITE_DIER(u32 RegBaseAddress, -* u32 Enable) -* -******************************************************************************/ -#define XIIF_V123B_WRITE_DIER(RegBaseAddress, Enable) \ - XIo_Out32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET, (Enable)) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_READ_DIER -* -* DESCRIPTION: -* -* This function gets the device interrupt enable register contents. -* This register controls which interrupt sources of the device -* are allowed to generate an interrupt. The device global interrupt enable -* register and the device interrupt enable register must also be set -* appropriately for an interrupt to be passed out of the device. -* -* Each bit of the register correlates to a specific interrupt source within the -* device which contains the IPIF. Setting a bit in this register enables that -* interrupt source to generate an interrupt if the global enable is set -* appropriately. Clearing a bit in this register disables interrupt generation -* for that interrupt source regardless of the global interrupt enable. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* RETURN VALUE: -* -* The value read from the interrupt enable register of the device. The bit -* definitions are specific to the device with the exception of the internal -* IPIF conditions. The following values may be used to determine from the -* value if the internal IPIF conditions interrupts are enabled. -* -* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF -* -* NOTES: -* -* None. -* -******************************************************************************/ -#define XIIF_V123B_READ_DIER(RegBaseAddress) \ - XIo_In32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_READ_DIPR -* -* DESCRIPTION: -* -* This function gets the device interrupt pending register contents. -* This register indicates the pending interrupt sources, those that are waiting -* to be serviced by the software, for a device which contains the IPIF. -* An interrupt must be enabled in the interrupt enable register of the IPIF to -* be pending. -* -* Each bit of the register correlates to a specific interrupt source within the -* the device which contains the IPIF. With the exception of some internal IPIF -* conditions, the contents of this register are not latched since the condition -* is latched in the IP interrupt status register, by an internal block of the -* IPIF such as a FIFO or DMA channel, or by the IP of the device. This register -* is read only and is not latched, but it is necessary to acknowledge (clear) -* the interrupt condition by performing the appropriate processing for the IP -* or block within the IPIF. -* -* This register can be thought of as the contents of the interrupt status -* register ANDed with the contents of the interrupt enable register. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* RETURN VALUE: -* -* The value read from the interrupt pending register of the device. The bit -* definitions are specific to the device with the exception of the latched -* internal IPIF condition bits. The following values may be used to detect -* internal IPIF conditions in the value. -* -* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF -* -* NOTES: -* -* None. -* -******************************************************************************/ -#define XIIF_V123B_READ_DIPR(RegBaseAddress) \ - XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_READ_DIIR -* -* DESCRIPTION: -* -* This function gets the device interrupt ID for the highest priority interrupt -* which is pending from the interrupt ID register. This function provides -* priority resolution such that faster interrupt processing is possible. -* Without priority resolution, it is necessary for the software to read the -* interrupt pending register and then check each interrupt source to determine -* if an interrupt is pending. Priority resolution becomes more important as the -* number of interrupt sources becomes larger. -* -* Interrupt priorities are based upon the bit position of the interrupt in the -* interrupt pending register with bit 0 being the highest priority. The -* interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the -* highest priority. The interrupt ID register is live rather than latched such -* that multiple calls to this function may not yield the same results. A -* special value, outside of the interrupt priority range of 0 - 31, is -* contained in the register which indicates that no interrupt is pending. This -* may be useful for allowing software to continue processing interrupts in a -* loop until there are no longer any interrupts pending. -* -* The interrupt ID is designed to allow a function pointer table to be used -* in the software such that the interrupt ID is used as an index into that -* table. The function pointer table could contain an instance pointer, such -* as to DMA channel, and a function pointer to the function which handles -* that interrupt. This design requires the interrupt processing of the device -* driver to be partitioned into smaller more granular pieces based upon -* hardware used by the device, such as DMA channels and FIFOs. -* -* It is not mandatory that this function be used by the device driver software. -* It may choose to read the pending register and resolve the pending interrupt -* priorities on it's own. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* RETURN VALUE: -* -* An interrupt ID, 0 - 31, which identifies the highest priority interrupt -* which is pending. A value of XIIF_NO_INTERRUPT_ID indicates that there is -* no interrupt pending. The following values may be used to identify the -* interrupt ID for the internal IPIF interrupts. -* -* XIIF_V123B_ERROR_INTERRUPT_ID Indicates a device error in the IPIF -* -* NOTES: -* -* None. -* -******************************************************************************/ -#define XIIF_V123B_READ_DIIR(RegBaseAddress) \ - XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_GLOBAL_INTR_DISABLE -* -* DESCRIPTION: -* -* This function disables all interrupts for the device by writing to the global -* interrupt enable register. This register provides the ability to disable -* interrupts without any modifications to the interrupt enable register such -* that it is minimal effort to restore the interrupts to the previous enabled -* state. The corresponding function, XIpIf_GlobalIntrEnable, is provided to -* restore the interrupts to the previous enabled state. This function is -* designed to be used in critical sections of device drivers such that it is -* not necessary to disable other device interrupts. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ -#define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \ - XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_GINTR_ENABLE -* -* DESCRIPTION: -* -* This function writes to the global interrupt enable register to enable -* interrupts from the device. This register provides the ability to enable -* interrupts without any modifications to the interrupt enable register such -* that it is minimal effort to restore the interrupts to the previous enabled -* state. This function does not enable individual interrupts as the interrupt -* enable register must be set appropriately. This function is designed to be -* used in critical sections of device drivers such that it is not necessary to -* disable other device interrupts. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ -#define XIIF_V123B_GINTR_ENABLE(RegBaseAddress) \ - XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \ - XIIF_V123B_GINTR_ENABLE_MASK) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_IS_GINTR_ENABLED -* -* DESCRIPTION: -* -* This function determines if interrupts are enabled at the global level by -* reading the gloabl interrupt register. This register provides the ability to -* disable interrupts without any modifications to the interrupt enable register -* such that it is minimal effort to restore the interrupts to the previous -* enabled state. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* RETURN VALUE: -* -* XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise. -* -* NOTES: -* -* None. -* -******************************************************************************/ -#define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress) \ - (XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) == \ - XIIF_V123B_GINTR_ENABLE_MASK) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_WRITE_IISR -* -* DESCRIPTION: -* -* This function sets the IP interrupt status register to the specified value. -* This register indicates the status of interrupt sources for the IP of the -* device. The IP is defined as the part of the device that connects to the -* IPIF. The status is independent of whether interrupts are enabled such that -* the status register may also be polled when interrupts are not enabled. -* -* Each bit of the register correlates to a specific interrupt source within the -* IP. All bits of this register are latched. Setting a bit which is zero -* within this register causes an interrupt to be generated. The device global -* interrupt enable register and the device interrupt enable register must be set -* appropriately to allow an interrupt to be passed out of the device. The -* interrupt is cleared by writing to this register with the bits to be -* cleared set to a one and all others to zero. This register implements a -* toggle on write functionality meaning any bits which are set in the value -* written cause the bits in the register to change to the opposite state. -* -* This function writes only the specified value to the register such that -* some status bits may be set and others cleared. It is the caller's -* responsibility to get the value of the register prior to setting the value -* to prevent an destructive behavior. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* Status contains the value to be written to the IP interrupt status -* register. The bit definitions are specific to the device IP. -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ -#define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \ - XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status)) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_READ_IISR -* -* DESCRIPTION: -* -* This function gets the contents of the IP interrupt status register. -* This register indicates the status of interrupt sources for the IP of the -* device. The IP is defined as the part of the device that connects to the -* IPIF. The status is independent of whether interrupts are enabled such -* that the status register may also be polled when interrupts are not enabled. -* -* Each bit of the register correlates to a specific interrupt source within the -* device. All bits of this register are latched. Writing a 1 to a bit within -* this register causes an interrupt to be generated if enabled in the interrupt -* enable register and the global interrupt enable is set. Since the status is -* latched, each status bit must be acknowledged in order for the bit in the -* status register to be updated. Each bit can be acknowledged by writing a -* 0 to the bit in the status register. - -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* RETURN VALUE: -* -* A status which contains the value read from the IP interrupt status register. -* The bit definitions are specific to the device IP. -* -* NOTES: -* -* None. -* -******************************************************************************/ -#define XIIF_V123B_READ_IISR(RegBaseAddress) \ - XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_WRITE_IIER -* -* DESCRIPTION: -* -* This function sets the IP interrupt enable register contents. This register -* controls which interrupt sources of the IP are allowed to generate an -* interrupt. The global interrupt enable register and the device interrupt -* enable register must also be set appropriately for an interrupt to be -* passed out of the device containing the IPIF and the IP. -* -* Each bit of the register correlates to a specific interrupt source within the -* IP. Setting a bit in this register enables the interrupt source to generate -* an interrupt. Clearing a bit in this register disables interrupt generation -* for that interrupt source. -* -* This function writes only the specified value to the register such that -* some interrupt sources may be enabled and others disabled. It is the -* caller's responsibility to get the value of the interrupt enable register -* prior to setting the value to prevent an destructive behavior. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* Enable contains the value to be written to the IP interrupt enable register. -* The bit definitions are specific to the device IP. -* -* RETURN VALUE: -* -* None. -* -* NOTES: -* -* None. -* -******************************************************************************/ -#define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \ - XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable)) - -/****************************************************************************** -* -* MACRO: -* -* XIIF_V123B_READ_IIER -* -* DESCRIPTION: -* -* -* This function gets the IP interrupt enable register contents. This register -* controls which interrupt sources of the IP are allowed to generate an -* interrupt. The global interrupt enable register and the device interrupt -* enable register must also be set appropriately for an interrupt to be -* passed out of the device containing the IPIF and the IP. -* -* Each bit of the register correlates to a specific interrupt source within the -* IP. Setting a bit in this register enables the interrupt source to generate -* an interrupt. Clearing a bit in this register disables interrupt generation -* for that interrupt source. -* -* ARGUMENTS: -* -* RegBaseAddress contains the base address of the IPIF registers. -* -* RETURN VALUE: -* -* The contents read from the IP interrupt enable register. The bit definitions -* are specific to the device IP. -* -* NOTES: -* -* Signature: u32 XIIF_V123B_READ_IIER(u32 RegBaseAddress) -* -******************************************************************************/ -#define XIIF_V123B_READ_IIER(RegBaseAddress) \ - XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET) - -/************************** Function Prototypes ******************************/ - -/* - * Initialization Functions - */ -XStatus XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth); - -#endif /* end of protection macro */ diff --git a/board/xilinx/common/xpacket_fifo_v1_00_b.c b/board/xilinx/common/xpacket_fifo_v1_00_b.c deleted file mode 100644 index ae2d6d4..0000000 --- a/board/xilinx/common/xpacket_fifo_v1_00_b.c +++ /dev/null @@ -1,448 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/* -* -* @file xpacket_fifo_v1_00_b.c -* -* Contains functions for the XPacketFifoV100b component. See xpacket_fifo_v1_00_b.h -* for more information about the component. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm 03/26/02  First release
-*
-* -*****************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xio.h" -#include "xstatus.h" -#include "xpacket_fifo_v1_00_b.h" - -/************************** Constant Definitions *****************************/ - -/* width of a FIFO word */ - -#define XPF_FIFO_WIDTH_BYTE_COUNT 4UL - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************* Variable Definitions ******************************/ - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/* -* -* This function initializes a packet FIFO. Initialization resets the -* FIFO such that it's empty and ready to use. -* -* @param InstancePtr contains a pointer to the FIFO to operate on. -* @param RegBaseAddress contains the base address of the registers for -* the packet FIFO. -* @param DataBaseAddress contains the base address of the data for -* the packet FIFO. -* -* @return -* -* Always returns XST_SUCCESS. -* -* @note -* -* None. -* -******************************************************************************/ -XStatus -XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr, - u32 RegBaseAddress, u32 DataBaseAddress) -{ - /* assert to verify input argument are valid */ - - XASSERT_NONVOID(InstancePtr != NULL); - - /* initialize the component variables to the specified state */ - - InstancePtr->RegBaseAddress = RegBaseAddress; - InstancePtr->DataBaseAddress = DataBaseAddress; - InstancePtr->IsReady = XCOMPONENT_IS_READY; - - /* reset the FIFO such that it's empty and ready to use and indicate the - * initialization was successful, note that the is ready variable must be - * set prior to calling the reset function to prevent an assert - */ - XPF_V100B_RESET(InstancePtr); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/* -* -* This function performs a self-test on the specified packet FIFO. The self -* test resets the FIFO and reads a register to determine if it is the correct -* reset value. This test is destructive in that any data in the FIFO will -* be lost. -* -* @param InstancePtr is a pointer to the packet FIFO to be operated on. -* -* @param FifoType specifies the type of FIFO, read or write, for the self test. -* The FIFO type is specified by the values XPF_READ_FIFO_TYPE or -* XPF_WRITE_FIFO_TYPE. -* -* @return -* -* XST_SUCCESS is returned if the selftest is successful, or -* XST_PFIFO_BAD_REG_VALUE indicating that the value readback from the -* occupancy/vacancy count register after a reset does not match the -* specified reset value. -* -* @note -* -* None. -* -******************************************************************************/ -XStatus -XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType) -{ - u32 Register; - - /* assert to verify valid input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID((FifoType == XPF_READ_FIFO_TYPE) || - (FifoType == XPF_WRITE_FIFO_TYPE)); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* reset the fifo and then check to make sure the occupancy/vacancy - * register contents are correct for a reset condition - */ - XPF_V100B_RESET(InstancePtr); - - Register = XIo_In32(InstancePtr->RegBaseAddress + - XPF_COUNT_STATUS_REG_OFFSET); - - /* check the value of the register to ensure that it's correct for the - * specified FIFO type since both FIFO types reset to empty, but a bit - * in the register changes definition based upon FIFO type - */ - - if (FifoType == XPF_READ_FIFO_TYPE) { - /* check the regiser value for a read FIFO which should be empty */ - - if (Register != XPF_EMPTY_FULL_MASK) { - return XST_PFIFO_BAD_REG_VALUE; - } - } else { - /* check the register value for a write FIFO which should not be full - * on reset - */ - if ((Register & XPF_EMPTY_FULL_MASK) != 0) { - return XST_PFIFO_BAD_REG_VALUE; - } - } - - /* the test was successful */ - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/* -* -* Read data from a FIFO and puts it into a specified buffer. The packet FIFO is -* currently 32 bits wide such that an input buffer which is a series of bytes -* is filled from the FIFO a word at a time. If the requested byte count is not -* a multiple of 32 bit words, it is necessary for this function to format the -* remaining 32 bit word from the FIFO into a series of bytes in the buffer. -* There may be up to 3 extra bytes which must be extracted from the last word -* of the FIFO and put into the buffer. -* -* @param InstancePtr contains a pointer to the FIFO to operate on. -* @param BufferPtr points to the memory buffer to write the data into. This -* buffer must be 32 bit aligned or an alignment exception could be -* generated. Since this buffer is a byte buffer, the data is assumed to -* be endian independent. -* @param ByteCount contains the number of bytes to read from the FIFO. This -* number of bytes must be present in the FIFO or an error will be -* returned. -* -* @return -* -* XST_SUCCESS indicates the operation was successful. If the number of -* bytes specified by the byte count is not present in the FIFO -* XST_PFIFO_LACK_OF_DATA is returned. -* -* If the function was successful, the specified buffer is modified to contain -* the bytes which were removed from the FIFO. -* -* @note -* -* Note that the exact number of bytes which are present in the FIFO is -* not known by this function. It can only check for a number of 32 bit -* words such that if the byte count specified is incorrect, but is still -* possible based on the number of words in the FIFO, up to 3 garbage bytes -* may be present at the end of the buffer. -*

-* This function assumes that if the device consuming data from the FIFO is -* a byte device, the order of the bytes to be consumed is from the most -* significant byte to the least significant byte of a 32 bit word removed -* from the FIFO. -* -******************************************************************************/ -XStatus -XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr, - u8 * BufferPtr, u32 ByteCount) -{ - u32 FifoCount; - u32 WordCount; - u32 ExtraByteCount; - u32 *WordBuffer = (u32 *) BufferPtr; - - /* assert to verify valid input arguments including 32 bit alignment of - * the buffer pointer - */ - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(BufferPtr != NULL); - XASSERT_NONVOID(((u32) BufferPtr & - (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0); - XASSERT_NONVOID(ByteCount != 0); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* get the count of how many 32 bit words are in the FIFO, if there aren't - * enought words to satisfy the request, return an error - */ - - FifoCount = XIo_In32(InstancePtr->RegBaseAddress + - XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; - - if ((FifoCount * XPF_FIFO_WIDTH_BYTE_COUNT) < ByteCount) { - return XST_PFIFO_LACK_OF_DATA; - } - - /* calculate the number of words to read from the FIFO before the word - * containing the extra bytes, and calculate the number of extra bytes - * the extra bytes are defined as those at the end of the buffer when - * the buffer does not end on a 32 bit boundary - */ - WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT; - ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT; - - /* Read the 32 bit words from the FIFO for all the buffer except the - * last word which contains the extra bytes, the following code assumes - * that the buffer is 32 bit aligned, otherwise an alignment exception could - * be generated - */ - for (FifoCount = 0; FifoCount < WordCount; FifoCount++) { - WordBuffer[FifoCount] = XIo_In32(InstancePtr->DataBaseAddress); - } - - /* if there are extra bytes to handle, read the last word from the FIFO - * and insert the extra bytes into the buffer - */ - if (ExtraByteCount > 0) { - u32 LastWord; - u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount); - - /* get the last word from the FIFO for the extra bytes */ - - LastWord = XIo_In32(InstancePtr->DataBaseAddress); - - /* one extra byte in the last word, put the byte into the next location - * of the buffer, bytes in a word of the FIFO are ordered from most - * significant byte to least - */ - if (ExtraByteCount == 1) { - ExtraBytesBuffer[0] = (u8) (LastWord >> 24); - } - - /* two extra bytes in the last word, put each byte into the next two - * locations of the buffer - */ - else if (ExtraByteCount == 2) { - ExtraBytesBuffer[0] = (u8) (LastWord >> 24); - ExtraBytesBuffer[1] = (u8) (LastWord >> 16); - } - /* three extra bytes in the last word, put each byte into the next three - * locations of the buffer - */ - else if (ExtraByteCount == 3) { - ExtraBytesBuffer[0] = (u8) (LastWord >> 24); - ExtraBytesBuffer[1] = (u8) (LastWord >> 16); - ExtraBytesBuffer[2] = (u8) (LastWord >> 8); - } - } - return XST_SUCCESS; -} - -/*****************************************************************************/ -/* -* -* Write data into a packet FIFO. The packet FIFO is currently 32 bits wide -* such that an input buffer which is a series of bytes must be written into the -* FIFO a word at a time. If the buffer is not a multiple of 32 bit words, it is -* necessary for this function to format the remaining bytes into a single 32 -* bit word to be inserted into the FIFO. This is necessary to avoid any -* accesses past the end of the buffer. -* -* @param InstancePtr contains a pointer to the FIFO to operate on. -* @param BufferPtr points to the memory buffer that data is to be read from -* and written into the FIFO. Since this buffer is a byte buffer, the data -* is assumed to be endian independent. This buffer must be 32 bit aligned -* or an alignment exception could be generated. -* @param ByteCount contains the number of bytes to read from the buffer and to -* write to the FIFO. -* -* @return -* -* XST_SUCCESS is returned if the operation succeeded. If there is not enough -* room in the FIFO to hold the specified bytes, XST_PFIFO_NO_ROOM is -* returned. -* -* @note -* -* This function assumes that if the device inserting data into the FIFO is -* a byte device, the order of the bytes in each 32 bit word is from the most -* significant byte to the least significant byte. -* -******************************************************************************/ -XStatus -XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr, - u8 * BufferPtr, u32 ByteCount) -{ - u32 FifoCount; - u32 WordCount; - u32 ExtraByteCount; - u32 *WordBuffer = (u32 *) BufferPtr; - - /* assert to verify valid input arguments including 32 bit alignment of - * the buffer pointer - */ - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(BufferPtr != NULL); - XASSERT_NONVOID(((u32) BufferPtr & - (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0); - XASSERT_NONVOID(ByteCount != 0); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* get the count of how many words may be inserted into the FIFO */ - - FifoCount = XIo_In32(InstancePtr->RegBaseAddress + - XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; - - /* Calculate the number of 32 bit words required to insert the specified - * number of bytes in the FIFO and determine the number of extra bytes - * if the buffer length is not a multiple of 32 bit words - */ - - WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT; - ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT; - - /* take into account the extra bytes in the total word count */ - - if (ExtraByteCount > 0) { - WordCount++; - } - - /* if there's not enough room in the FIFO to hold the specified - * number of bytes, then indicate an error, - */ - if (FifoCount < WordCount) { - return XST_PFIFO_NO_ROOM; - } - - /* readjust the word count to not take into account the extra bytes */ - - if (ExtraByteCount > 0) { - WordCount--; - } - - /* Write all the bytes of the buffer which can be written as 32 bit - * words into the FIFO, waiting to handle the extra bytes seperately - */ - for (FifoCount = 0; FifoCount < WordCount; FifoCount++) { - XIo_Out32(InstancePtr->DataBaseAddress, WordBuffer[FifoCount]); - } - - /* if there are extra bytes to handle, extract them from the buffer - * and create a 32 bit word and write it to the FIFO - */ - if (ExtraByteCount > 0) { - u32 LastWord = 0; - u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount); - - /* one extra byte in the buffer, put the byte into the last word - * to be inserted into the FIFO, perform this processing inline rather - * than in a loop to help performance - */ - if (ExtraByteCount == 1) { - LastWord = ExtraBytesBuffer[0] << 24; - } - - /* two extra bytes in the buffer, put each byte into the last word - * to be inserted into the FIFO - */ - else if (ExtraByteCount == 2) { - LastWord = ExtraBytesBuffer[0] << 24 | - ExtraBytesBuffer[1] << 16; - } - - /* three extra bytes in the buffer, put each byte into the last word - * to be inserted into the FIFO - */ - else if (ExtraByteCount == 3) { - LastWord = ExtraBytesBuffer[0] << 24 | - ExtraBytesBuffer[1] << 16 | - ExtraBytesBuffer[2] << 8; - } - - /* write the last 32 bit word to the FIFO and return with no errors */ - - XIo_Out32(InstancePtr->DataBaseAddress, LastWord); - } - - return XST_SUCCESS; -} diff --git a/board/xilinx/common/xpacket_fifo_v1_00_b.h b/board/xilinx/common/xpacket_fifo_v1_00_b.h deleted file mode 100644 index 1cda0e8..0000000 --- a/board/xilinx/common/xpacket_fifo_v1_00_b.h +++ /dev/null @@ -1,306 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/* -* -* @file xpacket_fifo_v1_00_b.h -* -* This component is a common component because it's primary purpose is to -* prevent code duplication in drivers. A driver which must handle a packet -* FIFO uses this component rather than directly manipulating a packet FIFO. -* -* A FIFO is a device which has dual port memory such that one user may be -* inserting data into the FIFO while another is consuming data from the FIFO. -* A packet FIFO is designed for use with packet protocols such as Ethernet and -* ATM. It is typically only used with devices when DMA and/or Scatter Gather -* is used. It differs from a nonpacket FIFO in that it does not provide any -* interrupts for thresholds of the FIFO such that it is less useful without -* DMA. -* -* @note -* -* This component has the capability to generate an interrupt when an error -* condition occurs. It is the user's responsibility to provide the interrupt -* processing to handle the interrupt. This component provides the ability to -* determine if that interrupt is active, a deadlock condition, and the ability -* to reset the FIFO to clear the condition. In this condition, the device which -* is using the FIFO should also be reset to prevent other problems. This error -* condition could occur as a normal part of operation if the size of the FIFO -* is not setup correctly. See the hardware IP specification for more details. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm 03/26/02  First release
-*
-* -*****************************************************************************/ -#ifndef XPACKET_FIFO_H /* prevent circular inclusions */ -#define XPACKET_FIFO_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xstatus.h" - -/************************** Constant Definitions *****************************/ - -/* - * These constants specify the FIFO type and are mutually exclusive - */ -#define XPF_READ_FIFO_TYPE 0 /* a read FIFO */ -#define XPF_WRITE_FIFO_TYPE 1 /* a write FIFO */ - -/* - * These constants define the offsets to each of the registers from the - * register base address, each of the constants are a number of bytes - */ -#define XPF_RESET_REG_OFFSET 0UL -#define XPF_MODULE_INFO_REG_OFFSET 0UL -#define XPF_COUNT_STATUS_REG_OFFSET 4UL - -/* - * This constant is used with the Reset Register - */ -#define XPF_RESET_FIFO_MASK 0x0000000A - -/* - * These constants are used with the Occupancy/Vacancy Count Register. This - * register also contains FIFO status - */ -#define XPF_COUNT_MASK 0x0000FFFF -#define XPF_DEADLOCK_MASK 0x20000000 -#define XPF_ALMOST_EMPTY_FULL_MASK 0x40000000 -#define XPF_EMPTY_FULL_MASK 0x80000000 - -/**************************** Type Definitions *******************************/ - -/* - * The XPacketFifo driver instance data. The driver is required to allocate a - * variable of this type for every packet FIFO in the device. - */ -typedef struct { - u32 RegBaseAddress; /* Base address of registers */ - u32 IsReady; /* Device is initialized and ready */ - u32 DataBaseAddress; /* Base address of data for FIFOs */ -} XPacketFifoV100b; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/* -* -* Reset the specified packet FIFO. Resetting a FIFO will cause any data -* contained in the FIFO to be lost. -* -* @param InstancePtr contains a pointer to the FIFO to operate on. -* -* @return -* -* None. -* -* @note -* -* Signature: void XPF_V100B_RESET(XPacketFifoV100b *InstancePtr) -* -******************************************************************************/ -#define XPF_V100B_RESET(InstancePtr) \ - XIo_Out32((InstancePtr)->RegBaseAddress + XPF_RESET_REG_OFFSET, XPF_RESET_FIFO_MASK); - -/*****************************************************************************/ -/* -* -* Get the occupancy count for a read packet FIFO and the vacancy count for a -* write packet FIFO. These counts indicate the number of 32-bit words -* contained (occupancy) in the FIFO or the number of 32-bit words available -* to write (vacancy) in the FIFO. -* -* @param InstancePtr contains a pointer to the FIFO to operate on. -* -* @return -* -* The occupancy or vacancy count for the specified packet FIFO. -* -* @note -* -* Signature: u32 XPF_V100B_GET_COUNT(XPacketFifoV100b *InstancePtr) -* -******************************************************************************/ -#define XPF_V100B_GET_COUNT(InstancePtr) \ - (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ - XPF_COUNT_MASK) - -/*****************************************************************************/ -/* -* -* Determine if the specified packet FIFO is almost empty. Almost empty is -* defined for a read FIFO when there is only one data word in the FIFO. -* -* @param InstancePtr contains a pointer to the FIFO to operate on. -* -* @return -* -* TRUE if the packet FIFO is almost empty, FALSE otherwise. -* -* @note -* -* Signature: u32 XPF_V100B_IS_ALMOST_EMPTY(XPacketFifoV100b *InstancePtr) -* -******************************************************************************/ -#define XPF_V100B_IS_ALMOST_EMPTY(InstancePtr) \ - (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ - XPF_ALMOST_EMPTY_FULL_MASK) - -/*****************************************************************************/ -/* -* -* Determine if the specified packet FIFO is almost full. Almost full is -* defined for a write FIFO when there is only one available data word in the -* FIFO. -* -* @param InstancePtr contains a pointer to the FIFO to operate on. -* -* @return -* -* TRUE if the packet FIFO is almost full, FALSE otherwise. -* -* @note -* -* Signature: u32 XPF_V100B_IS_ALMOST_FULL(XPacketFifoV100b *InstancePtr) -* -******************************************************************************/ -#define XPF_V100B_IS_ALMOST_FULL(InstancePtr) \ - (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ - XPF_ALMOST_EMPTY_FULL_MASK) - -/*****************************************************************************/ -/* -* -* Determine if the specified packet FIFO is empty. This applies only to a -* read FIFO. -* -* @param InstancePtr contains a pointer to the FIFO to operate on. -* -* @return -* -* TRUE if the packet FIFO is empty, FALSE otherwise. -* -* @note -* -* Signature: u32 XPF_V100B_IS_EMPTY(XPacketFifoV100b *InstancePtr) -* -******************************************************************************/ -#define XPF_V100B_IS_EMPTY(InstancePtr) \ - (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ - XPF_EMPTY_FULL_MASK) - -/*****************************************************************************/ -/* -* -* Determine if the specified packet FIFO is full. This applies only to a -* write FIFO. -* -* @param InstancePtr contains a pointer to the FIFO to operate on. -* -* @return -* -* TRUE if the packet FIFO is full, FALSE otherwise. -* -* @note -* -* Signature: u32 XPF_V100B_IS_FULL(XPacketFifoV100b *InstancePtr) -* -******************************************************************************/ -#define XPF_V100B_IS_FULL(InstancePtr) \ - (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ - XPF_EMPTY_FULL_MASK) - -/*****************************************************************************/ -/* -* -* Determine if the specified packet FIFO is deadlocked. This condition occurs -* when the FIFO is full and empty at the same time and is caused by a packet -* being written to the FIFO which exceeds the total data capacity of the FIFO. -* It occurs because of the mark/restore features of the packet FIFO which allow -* retransmission of a packet. The software should reset the FIFO and any devices -* using the FIFO when this condition occurs. -* -* @param InstancePtr contains a pointer to the FIFO to operate on. -* -* @return -* -* TRUE if the packet FIFO is deadlocked, FALSE otherwise. -* -* @note -* -* This component has the capability to generate an interrupt when an error -* condition occurs. It is the user's responsibility to provide the interrupt -* processing to handle the interrupt. This function provides the ability to -* determine if a deadlock condition, and the ability to reset the FIFO to -* clear the condition. -* -* In this condition, the device which is using the FIFO should also be reset -* to prevent other problems. This error condition could occur as a normal part -* of operation if the size of the FIFO is not setup correctly. -* -* Signature: u32 XPF_V100B_IS_DEADLOCKED(XPacketFifoV100b *InstancePtr) -* -******************************************************************************/ -#define XPF_V100B_IS_DEADLOCKED(InstancePtr) \ - (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \ - XPF_DEADLOCK_MASK) - -/************************** Function Prototypes ******************************/ - -/* Standard functions */ - -XStatus XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr, - u32 RegBaseAddress, u32 DataBaseAddress); -XStatus XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType); - -/* Data functions */ - -XStatus XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr, - u8 * ReadBufferPtr, u32 ByteCount); -XStatus XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr, - u8 * WriteBufferPtr, u32 ByteCount); - -#endif /* end of protection macro */ diff --git a/board/xilinx/common/xstatus.h b/board/xilinx/common/xstatus.h deleted file mode 100644 index ffda4d7..0000000 --- a/board/xilinx/common/xstatus.h +++ /dev/null @@ -1,347 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xstatus.h -* -* This file contains Xilinx software status codes. Status codes have their -* own data type called XStatus. These codes are used throughout the Xilinx -* device drivers. -* -******************************************************************************/ - -#ifndef XSTATUS_H /* prevent circular inclusions */ -#define XSTATUS_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" - -/************************** Constant Definitions *****************************/ - -/*********************** Common statuses 0 - 500 *****************************/ - -#define XST_SUCCESS 0L -#define XST_FAILURE 1L -#define XST_DEVICE_NOT_FOUND 2L -#define XST_DEVICE_BLOCK_NOT_FOUND 3L -#define XST_INVALID_VERSION 4L -#define XST_DEVICE_IS_STARTED 5L -#define XST_DEVICE_IS_STOPPED 6L -#define XST_FIFO_ERROR 7L /* an error occurred during an - operation with a FIFO such as - an underrun or overrun, this - error requires the device to - be reset */ -#define XST_RESET_ERROR 8L /* an error occurred which requires - the device to be reset */ -#define XST_DMA_ERROR 9L /* a DMA error occurred, this error - typically requires the device - using the DMA to be reset */ -#define XST_NOT_POLLED 10L /* the device is not configured for - polled mode operation */ -#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put - the specified data into */ -#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough - to hold the expected data */ -#define XST_NO_DATA 13L /* there was no data available */ -#define XST_REGISTER_ERROR 14L /* a register did not contain the - expected value */ -#define XST_INVALID_PARAM 15L /* an invalid parameter was passed - into the function */ -#define XST_NOT_SGDMA 16L /* the device is not configured for - scatter-gather DMA operation */ -#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ -#define XST_NO_CALLBACK 18L /* a callback has not yet been - * registered */ -#define XST_NO_FEATURE 19L /* device is not configured with - * the requested feature */ -#define XST_NOT_INTERRUPT 20L /* device is not configured for - * interrupt mode operation */ -#define XST_DEVICE_BUSY 21L /* device is busy */ -#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device - * have maxed out */ -#define XST_IS_STARTED 23L /* used when part of device is - * already started i.e. - * sub channel */ -#define XST_IS_STOPPED 24L /* used when part of device is - * already stopped i.e. - * sub channel */ - -/***************** Utility Component statuses 401 - 500 *********************/ - -#define XST_MEMTEST_FAILED 401L /* memory test failed */ - -/***************** Common Components statuses 501 - 1000 *********************/ - -/********************* Packet Fifo statuses 501 - 510 ************************/ - -#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ -#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ -#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value - was invalid after reset */ - -/************************** DMA statuses 511 - 530 ***************************/ - -#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer - failed */ -#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value - was invalid after reset */ -#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains - no buffer descriptors ready - to be processed */ -#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ -#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ -#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of - the scatter gather list are - being used */ -#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer - descriptor which is to be - copied over in the scatter - list is locked */ -#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been - put into the scatter gather - list to be commited */ -#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold - specified was larger than the - total # of buffer descriptors - in the scatter gather list */ -#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has - already been created */ -#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has - been created */ -#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was - being started was not committed - to the list */ -#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start - has already been used by the - hardware so it can't be reused - */ - -/************************** IPIF statuses 531 - 550 ***************************/ - -#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width - was passed into the function */ -#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at - reset was not valid */ -#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt - status register did not read - back correctly */ -#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status - register did not reset when - acked */ -#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable - register was not updated when - other registers changed */ -#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt - status register did not read - back correctly */ -#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register - did not reset when acked */ -#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was - not updated correctly when other - registers changed */ -#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending - register did not indicate the - expected value */ -#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register - did not indicate the expected - value */ - -/****************** Device specific statuses 1001 - 4095 *********************/ - -/********************* Ethernet statuses 1001 - 1050 *************************/ - -#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough - * to hold the minimum number of - * buffers or descriptors */ -#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ -#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ -#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ -#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Adapter is out of buffers */ -#define XST_EMAC_PARSE_ERROR 1006L /* Invalid adapter init string */ -#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late - * collision on polled send */ - -/*********************** UART statuses 1051 - 1075 ***************************/ -#define XST_UART - -#define XST_UART_INIT_ERROR 1051L -#define XST_UART_START_ERROR 1052L -#define XST_UART_CONFIG_ERROR 1053L -#define XST_UART_TEST_FAIL 1054L -#define XST_UART_BAUD_ERROR 1055L -#define XST_UART_BAUD_RANGE 1056L - -/************************ IIC statuses 1076 - 1100 ***************************/ - -#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ -#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ -#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ - /* general call address */ -#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ - /* value after reset not valid */ -#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ - /* value after reset not valid */ -#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ - /* didn't return value written */ -#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ - /* didn't return value written */ -#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ - /* didn't return written value */ -#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ - -/*********************** ATMC statuses 1101 - 1125 ***************************/ - -#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM - controller hit the max value - which requires the statistics - to be cleared */ - -/*********************** Flash statuses 1126 - 1150 **************************/ - -#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming */ -#define XST_FLASH_READY 1127L /* Flash is ready for commands */ -#define XST_FLASH_ERROR 1128L /* Flash had detected an internal - error. Use XFlash_DeviceControl - to retrieve device specific codes */ -#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state */ -#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state */ -#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by - driver */ -#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ -#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ -#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation - aborted due to a timeout */ -#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its - addressible range */ -#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ -#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from - write/erase function with - XFL_NON_BLOCKING_WRITE/ERASE - option cleared */ -#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ - -/*********************** SPI statuses 1151 - 1175 ****************************/ - -#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ -#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ -#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ -#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ -#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ -#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being - * selected */ -#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ -#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only */ -#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ - -/********************** OPB Arbiter statuses 1176 - 1200 *********************/ - -#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either - * one master assigned to two or more - * priorities, or one master not - * assigned to any priority - */ -#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the - * priority levels without first - * suspending the use of priority - * levels - */ -#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but - * bus parking was not enabled - */ -#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed - * priority mode to allow the - * priorities to be changed - */ - -/************************ Intc statuses 1201 - 1225 **************************/ - -#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ -#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ - -/********************** TmrCtr statuses 1226 - 1250 **************************/ - -#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ - -/********************** WdtTb statuses 1251 - 1275 ***************************/ - -#define XST_WDTTB_TIMER_FAILED 1251L - -/********************** PlbArb statuses 1276 - 1300 **************************/ - -#define XST_PLBARB_FAIL_SELFTEST 1276L - -/********************** Plb2Opb statuses 1301 - 1325 *************************/ - -#define XST_PLB2OPB_FAIL_SELFTEST 1301L - -/********************** Opb2Plb statuses 1326 - 1350 *************************/ - -#define XST_OPB2PLB_FAIL_SELFTEST 1326L - -/********************** SysAce statuses 1351 - 1360 **************************/ - -#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ - -/********************** PCI Bridge statuses 1361 - 1375 **********************/ - -#define XST_PCI_INVALID_ADDRESS 1361L - -/**************************** Type Definitions *******************************/ - -/** - * The status typedef. - */ -typedef u32 XStatus; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -#endif /* end of protection macro */ diff --git a/board/xilinx/common/xversion.c b/board/xilinx/common/xversion.c deleted file mode 100644 index c8a6915..0000000 --- a/board/xilinx/common/xversion.c +++ /dev/null @@ -1,350 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/***************************************************************************** -* -* This file contains the implementation of the XVersion component. This -* component represents a version ID. It is encapsulated within a component -* so that it's type and implementation can change without affecting users of -* it. -* -* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z -* X is the major revision, YY is the minor revision, and Z is the -* compatability revision. -* -* Packed versions are also utilized for the configuration ROM such that -* memory is minimized. A packed version consumes only 16 bits and is -* formatted as follows. -* -* 
-* Revision                  Range       Bit Positions
-*
-* Major Revision            0 - 9       Bits 15 - 12
-* Minor Revision            0 - 99      Bits 11 - 5
-* Compatability Revision    a - z       Bits 4 - 0
-
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xversion.h" - -/************************** Constant Definitions *****************************/ - -/* the following constants define the masks and shift values to allow the - * revisions to be packed and unpacked, a packed version is packed into a 16 - * bit value in the following format, XXXXYYYYYYYZZZZZ, where XXXX is the - * major revision, YYYYYYY is the minor revision, and ZZZZZ is the compatability - * revision - */ -#define XVE_MAJOR_SHIFT_VALUE 12 -#define XVE_MINOR_ONLY_MASK 0x0FE0 -#define XVE_MINOR_SHIFT_VALUE 5 -#define XVE_COMP_ONLY_MASK 0x001F - -/* the following constants define the specific characters of a version string - * for each character of the revision, a version string is in the following - * format, "X.YYZ" where X is the major revision (0 - 9), YY is the minor - * revision (00 - 99), and Z is the compatability revision (a - z) - */ -#define XVE_MAJOR_CHAR 0 /* major revision 0 - 9 */ -#define XVE_MINOR_TENS_CHAR 2 /* minor revision tens 0 - 9 */ -#define XVE_MINOR_ONES_CHAR 3 /* minor revision ones 0 - 9 */ -#define XVE_COMP_CHAR 4 /* compatability revision a - z */ -#define XVE_END_STRING_CHAR 5 - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -static u32 IsVersionStringValid(s8 * StringPtr); - -/***************************************************************************** -* -* Unpacks a packed version into the specified version. Versions are packed -* into the configuration ROM to reduce the amount storage. A packed version -* is a binary format as oppossed to a non-packed version which is implemented -* as a string. -* -* @param InstancePtr points to the version to unpack the packed version into. -* @param PackedVersion contains the packed version to unpack. -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -void -XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion) -{ - /* not implemented yet since CROM related */ -} - -/***************************************************************************** -* -* Packs a version into the specified packed version. Versions are packed into -* the configuration ROM to reduce the amount storage. -* -* @param InstancePtr points to the version to pack. -* @param PackedVersionPtr points to the packed version which will receive -* the new packed version. -* -* @return -* -* A status, XST_SUCCESS, indicating the packing was accomplished -* successfully, or an error, XST_INVALID_VERSION, indicating the specified -* input version was not valid such that the pack did not occur -*

-* The packed version pointed to by PackedVersionPtr is modified with the new -* packed version if the status indicates success. -* -* @note -* -* None. -* -******************************************************************************/ -XStatus -XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersionPtr) -{ - /* not implemented yet since CROM related */ - - return XST_SUCCESS; -} - -/***************************************************************************** -* -* Determines if two versions are equal. -* -* @param InstancePtr points to the first version to be compared. -* @param VersionPtr points to a second version to be compared. -* -* @return -* -* TRUE if the versions are equal, FALSE otherwise. -* -* @note -* -* None. -* -******************************************************************************/ -u32 -XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr) -{ - u8 *Version1 = (u8 *) InstancePtr; - u8 *Version2 = (u8 *) VersionPtr; - int Index; - - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(VersionPtr != NULL); - - /* check each byte of the versions to see if they are the same, - * return at any point a byte differs between them - */ - for (Index = 0; Index < sizeof (XVersion); Index++) { - if (Version1[Index] != Version2[Index]) { - return FALSE; - } - } - - /* No byte was found to be different between the versions, so indicate - * the versions are equal - */ - return TRUE; -} - -/***************************************************************************** -* -* Converts a version to a null terminated string. -* -* @param InstancePtr points to the version to convert. -* @param StringPtr points to the string which will be the result of the -* conversion. This does not need to point to a null terminated -* string as an input, but must point to storage which is an adequate -* amount to hold the result string. -* -* @return -* -* The null terminated string is inserted at the location pointed to by -* StringPtr if the status indicates success. -* -* @note -* -* It is necessary for the caller to have already allocated the storage to -* contain the string. The amount of memory necessary for the string is -* specified in the version header file. -* -******************************************************************************/ -void -XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr) -{ - /* assert to verify input arguments */ - - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(StringPtr != NULL); - - /* since version is implemented as a string, just copy the specified - * input into the specified output - */ - XVersion_Copy(InstancePtr, (XVersion *) StringPtr); -} - -/***************************************************************************** -* -* Initializes a version from a null terminated string. Since the string may not -* be a format which is compatible with the version, an error could occur. -* -* @param InstancePtr points to the version which is to be initialized. -* @param StringPtr points to a null terminated string which will be -* converted to a version. The format of the string must match the -* version string format which is X.YYX where X = 0 - 9, YY = 00 - 99, -* Z = a - z. -* -* @return -* -* A status, XST_SUCCESS, indicating the conversion was accomplished -* successfully, or XST_INVALID_VERSION indicating the version string format -* was not valid. -* -* @note -* -* None. -* -******************************************************************************/ -XStatus -XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr) -{ - /* assert to verify input arguments */ - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(StringPtr != NULL); - - /* if the version string specified is not valid, return an error */ - - if (!IsVersionStringValid(StringPtr)) { - return XST_INVALID_VERSION; - } - - /* copy the specified string into the specified version and indicate the - * conversion was successful - */ - XVersion_Copy((XVersion *) StringPtr, InstancePtr); - - return XST_SUCCESS; -} - -/***************************************************************************** -* -* Copies the contents of a version to another version. -* -* @param InstancePtr points to the version which is the source of data for -* the copy operation. -* @param VersionPtr points to another version which is the destination of -* the copy operation. -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -void -XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr) -{ - u8 *Source = (u8 *) InstancePtr; - u8 *Destination = (u8 *) VersionPtr; - int Index; - - /* assert to verify input arguments */ - - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(VersionPtr != NULL); - - /* copy each byte of the source version to the destination version */ - - for (Index = 0; Index < sizeof (XVersion); Index++) { - Destination[Index] = Source[Index]; - } -} - -/***************************************************************************** -* -* Determines if the specified version is valid. -* -* @param StringPtr points to the string to be validated. -* -* @return -* -* TRUE if the version string is a valid format, FALSE otherwise. -* -* @note -* -* None. -* -******************************************************************************/ -static u32 -IsVersionStringValid(s8 * StringPtr) -{ - /* if the input string is not a valid format, "X.YYZ" where X = 0 - 9, - * YY = 00 - 99, and Z = a - z, then indicate it's not valid - */ - if ((StringPtr[XVE_MAJOR_CHAR] < '0') || - (StringPtr[XVE_MAJOR_CHAR] > '9') || - (StringPtr[XVE_MINOR_TENS_CHAR] < '0') || - (StringPtr[XVE_MINOR_TENS_CHAR] > '9') || - (StringPtr[XVE_MINOR_ONES_CHAR] < '0') || - (StringPtr[XVE_MINOR_ONES_CHAR] > '9') || - (StringPtr[XVE_COMP_CHAR] < 'a') || - (StringPtr[XVE_COMP_CHAR] > 'z')) { - return FALSE; - } - - return TRUE; -} diff --git a/board/xilinx/common/xversion.h b/board/xilinx/common/xversion.h deleted file mode 100644 index 17f9da7..0000000 --- a/board/xilinx/common/xversion.h +++ /dev/null @@ -1,97 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/***************************************************************************** -* -* This file contains the interface for the XVersion component. This -* component represents a version ID. It is encapsulated within a component -* so that it's type and implementation can change without affecting users of -* it. -* -* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z -* X is the major revision, YY is the minor revision, and Z is the -* compatability revision. -* -* Packed versions are also utilized for the configuration ROM such that -* memory is minimized. A packed version consumes only 16 bits and is -* formatted as follows. -* -* 
-* Revision                  Range       Bit Positions
-*
-* Major Revision            0 - 9       Bits 15 - 12
-* Minor Revision            0 - 99      Bits 11 - 5
-* Compatability Revision    a - z       Bits 4 - 0
-*
-* -******************************************************************************/ - -#ifndef XVERSION_H /* prevent circular inclusions */ -#define XVERSION_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xstatus.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/* the following data type is used to hold a null terminated version string - * consisting of the following format, "X.YYX" - */ -typedef s8 XVersion[6]; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -void XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion); - -XStatus XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersion); - -u32 XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr); - -void XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr); - -XStatus XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr); - -void XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr); - -#endif /* end of protection macro */ diff --git a/board/xilinx/ml300/Makefile b/board/xilinx/ml300/Makefile deleted file mode 100644 index 880c494..0000000 --- a/board/xilinx/ml300/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -include $(TOPDIR)/config.mk - -CFLAGS += -I../ml300 -I../common -I../xilinx_enet -I../xilinx_iic - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o \ - serial.o \ - ../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \ - ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \ - ../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \ - ../xilinx_enet/xemac_intr_dma.o ../xilinx_iic/iic_adapter.o \ - ../xilinx_iic/xiic_l.o ../common/xipif_v1_23_b.o \ - ../common/xbasic_types.o ../common/xdma_channel.o \ - ../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \ - ../common/xversion.o \ - -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/xilinx/ml300/config.mk b/board/xilinx/ml300/config.mk deleted file mode 100644 index 57ddb2f..0000000 --- a/board/xilinx/ml300/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0x04000000 diff --git a/board/xilinx/ml300/init.S b/board/xilinx/ml300/init.S deleted file mode 100644 index f753df8..0000000 --- a/board/xilinx/ml300/init.S +++ /dev/null @@ -1,48 +0,0 @@ -/* - * init.S: Stubs for U-Boot initialization - * - * Author: Xilinx, Inc. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING - * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx hardware products are not intended for use in life support - * appliances, devices, or systems. Use in such applications is - * expressly prohibited. - * - * - * (c) Copyright 2002-2004 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * - */ - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - blr - - .globl sdram_init -sdram_init: - blr diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c deleted file mode 100644 index dad562f..0000000 --- a/board/xilinx/ml300/ml300.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * ml300.c: U-Boot platform support for Xilinx ML300 board - * - * Author: Xilinx, Inc. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING - * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx hardware products are not intended for use in life support - * appliances, devices, or systems. Use in such applications is - * expressly prohibited. - * - * - * (c) Copyright 2002-2004 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include -#include -#include "xparameters.h" - -#ifdef CFG_ENV_IS_IN_EEPROM -extern void convert_env(void); -#endif - -int -board_pre_init(void) -{ - return 0; -} - -int -checkboard(void) -{ - char tmp[64]; /* long enough for environment variables */ - char *s, *e; - int i = getenv_r("L", tmp, sizeof (tmp)); - - if (i < 0) { - printf("### No HW ID - assuming ML300"); - } else { - for (e = tmp; *e; ++e) { - if (*e == ' ') - break; - } - - printf("### Board Serial# is "); - - for (s = tmp; s < e; ++s) { - putc(*s); - } - - } - putc('\n'); - - return (0); -} - -long int -initdram(int board_type) -{ - return 128 * 1024 * 1024; -} - -int -testdram(void) -{ - printf("test: xxx MB - ok\n"); - - return (0); -} - -/* implement functions originally in cpu/ppc4xx/speed.c */ -void -get_sys_info(sys_info_t * sysInfo) -{ - sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - - /* only correct if the PLB and OPB run at the same frequency */ - sysInfo->freqPLB = XPAR_UARTNS550_0_CLOCK_FREQ_HZ; - sysInfo->freqPCI = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 3; -} - -ulong -get_PCI_freq(void) -{ - ulong val; - PPC405_SYS_INFO sys_info; - - get_sys_info(&sys_info); - val = sys_info.freqPCI; - return val; -} - -#ifdef CONFIG_MISC_INIT_R - -int -misc_init_r() -{ - /* convert env name and value to u-boot standard */ - convert_env(); - return 0; -} - -#endif diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c deleted file mode 100644 index 19bcc6f..0000000 --- a/board/xilinx/ml300/serial.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Author: Xilinx, Inc. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING - * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx hardware products are not intended for use in life support - * appliances, devices, or systems. Use in such applications is - * expressly prohibited. - * - * - * (c) Copyright 2002-2004 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include -#include -#include -#include -#include -#include "xparameters.h" - -#define USE_CHAN1 \ - ((defined XPAR_UARTNS550_0_BASEADDR) && (defined CFG_INIT_CHAN1)) -#define USE_CHAN2 \ - ((defined XPAR_UARTNS550_1_BASEADDR) && (defined CFG_INIT_CHAN2)) - -#if USE_CHAN1 -#include -#endif - -#if USE_CHAN1 -const NS16550_t COM_PORTS[] = { (NS16550_t) (XPAR_UARTNS550_0_BASEADDR + 3) -#if USE_CHAN2 - , (NS16550_t) (XPAR_UARTNS550_1_BASEADDR + 3) -#endif -}; -#endif - -int -serial_init(void) -{ -#if USE_CHAN1 - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor; - - clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; - (void) NS16550_init(COM_PORTS[0], clock_divisor); -#if USE_CHAN2 - clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate; - (void) NS16550_init(COM_PORTS[1], clock_divisor); -#endif -#endif - return 0; - -} - -void -serial_putc(const char c) -{ - if (c == '\n') - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); - - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); -} - -int -serial_getc(void) -{ - return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); -} - -int -serial_tstc(void) -{ - return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); -} - -void -serial_setbrg(void) -{ -#if USE_CHAN1 - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor; - - clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; - NS16550_reinit(COM_PORTS[0], clock_divisor); -#if USE_CHAN2 - clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate; - NS16550_reinit(COM_PORTS[1], clock_divisor); -#endif -#endif -} - -void -serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -void -kgdb_serial_init(void) -{ -} - -void -putDebugChar(int c) -{ - serial_putc(c); -} - -void -putDebugStr(const char *str) -{ - serial_puts(str); -} - -int -getDebugChar(void) -{ - return serial_getc(); -} - -void -kgdb_interruptible(int yes) -{ - return; -} -#endif /* CFG_CMD_KGDB */ diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes deleted file mode 100644 index 9daf147..0000000 --- a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes +++ /dev/null @@ -1,55 +0,0 @@ -#!/bin/bash - -if [ $# -ne 1 ] -then - echo "usage: Ltypes filename" >&2 - exit 2 -fi - -FILE="$1" -#TMPFILE='mktemp "${FILE}.XXXXXX"' || exit 1 -TMPFILE=${FILE}.`date "+%s"` -touch $TMPFILE || exit 1 - -# Change all the Xilinx types to Linux types and put the result into a temp file -sed \ - -e 's/\bXTRUE\b/TRUE/g' \ - -e 's/\bXFALSE\b/FALSE/g' \ - -e 's/\bXNULL\b/NULL/g' \ - -e 's/"xenv.h"//g' \ - -e 's/\bXENV_USLEEP\b/udelay/g' \ - -e 's/\bXuint8\b/u8/g' \ - -e 's/\bXuint16\b/u16/g' \ - -e 's/\bXuint32\b/u32/g' \ - -e 's/\bXint8\b/s8/g' \ - -e 's/\bXint16\b/s16/g' \ - -e 's/\bXint32\b/s32/g' \ - -e 's/\bXboolean\b/u32/g' \ - "${FILE}" > "${TMPFILE}" - -# Overlay the original file with the temp file -mv "${TMPFILE}" "${FILE}" - -# Are we doing xbasic_types.h? -if [ "${FILE##*/}" = xbasic_types.h ] -then - # Remember as you're reading this that we've already gone through the prior - # sed script. We need to do some other things to xbasic_types.h: - # 1) Add ifndefs around TRUE and FALSE defines - # 2) Remove definition of NULL as NULL - # 3) Replace most of the primitive types section with a #include - sed \ - -e '/u32 true/,/#define false/Ic\ -#ifndef TRUE\ -#define TRUE 1\ -#endif\ -#ifndef FALSE\ -#define FALSE 0\ -#endif' \ - -e '/#define[[:space:]][[:space:]]*NULL[[:space:]][[:space:]]*NULL/d' \ - -e '/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*char[[:space:]][[:space:]]*u8/,/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*long[[:space:]][[:space:]]*u32.*boolean/c\ -#include ' \ - "${FILE}" > "${TMPFILE}" - - mv "${TMPFILE}" "${FILE}" -fi diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld deleted file mode 100644 index 5169241..0000000 --- a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld +++ /dev/null @@ -1,52 +0,0 @@ -# (c) Copyright 2004 Xilinx Inc. -# Author: Xilinx, Inc. -# -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License as published by the -# Free Software Foundation; either version 2 of the License, or (at your -# option) any later version. -# -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -# XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -# FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -# ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -# WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -# CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -# FITNESS FOR A PARTICULAR PURPOSE. -# -# -# Xilinx hardware products are not intended for use in life support -# appliances, devices, or systems. Use in such applications is -# expressly prohibited. -# -# -# (c) Copyright 2002-2004 Xilinx Inc. -# All rights reserved. -# -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 675 Mass Ave, Cambridge, MA 02139, USA. - -OPTION psf_version = 2.1; - -BEGIN LIBRARY uboot OPTION DRC = uboot_drc; - -BEGIN ARRAY connected_periphs PROPERTY desc = "Peripherals connected to U-Boot"; -PROPERTY size = 0; -PARAM name = periph_name, desc = "Name of Peripheral connected", type = string; -END ARRAY - PARAMETER name = TARGET_DIR, desc = "Target Directory for U-Boot BSP", type = string; - -# location of persistent storage in the IIC EEPROM (defaults are set for ML300) -PARAMETER name = IIC_PERSISTENT_BASEADDR, desc = "Start of persistent storage block in the EEPROM address space", type = int, default = 1024; -PARAMETER name = IIC_PERSISTENT_HIGHADDR, desc = "End of persistent storage block in the EEPROM address space", type = int, default = 2047; -PARAMETER name = IIC_PERSISTENT_EEPROMADDR, desc = "Address of the EEPROM on the IIC bus", type = int, default = 0xA0; - -END LIBRARY diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl deleted file mode 100644 index 9d44f44..0000000 --- a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl +++ /dev/null @@ -1,325 +0,0 @@ -# -# Author: Xilinx, Inc. -# -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License as published by the -# Free Software Foundation; either version 2 of the License, or (at your -# option) any later version. -# -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -# XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -# FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -# ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -# WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -# CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -# FITNESS FOR A PARTICULAR PURPOSE. -# -# -# Xilinx hardware products are not intended for use in life support -# appliances, devices, or systems. Use in such applications is -# expressly prohibited. -# -# -# (c) Copyright 2002-2004 Xilinx Inc. -# All rights reserved. -# -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 675 Mass Ave, Cambridge, MA 02139, USA. -# -# Globals -lappend drvlist -set ltypes "../../../sw_services/uboot_v1_00_a/data/Ltypes" - -proc uboot_drc {lib_handle} { - puts "U-Boot DRC..." -} - -proc generate {libname} { - - global drvlist - - # Get list of peripherals connected to uboot - set conn_periphs [xget_handle $libname "ARRAY" "connected_periphs"] - #lappend drvlist - if {[string compare -nocase $conn_periphs ""] != 0} { - set conn_periphs_elems [xget_handle $conn_periphs "ELEMENTS" "*"] - # For each periph - foreach periph_elem $conn_periphs_elems { - set periph [xget_value $periph_elem "PARAMETER" "periph_name"] - # 1. Get driver - set drv [xget_swhandle $periph] - set posn [lsearch -exact $drvlist $drv] - if {$posn == -1} { - lappend drvlist $drv - } - } - - set file_handle [xopen_include_file "xparameters.h"] - puts $file_handle "\n/******************************************************************/\n" - puts $file_handle "/* U-Boot Redefines */" - puts $file_handle "\n/******************************************************************/\n" - close $file_handle - - foreach drv $drvlist { - set drvname [xget_value $drv "NAME"] - - #Redefines xparameters.h - if {[string compare -nocase $drvname "uartns550"] == 0} { - xredefine_uartns550 $drv "xparameters.h" - } elseif {[string compare -nocase $drvname "emac"] == 0} { - xredefine_emac $drv "xparameters.h" - } elseif {[string compare -nocase $drvname "iic"] == 0} { - xredefine_iic $drv "xparameters.h" - } - } - } - - # define core_clock - xredefine_params $libname "xparameters.h" "CORE_CLOCK_FREQ_HZ" - - # define the values for the persistent storage in IIC - xredefine_params $libname "xparameters.h" "IIC_PERSISTENT_BASEADDR" "IIC_PERSISTENT_HIGHADDR" "IIC_PERSISTENT_EEPROMADDR" - -} - -proc xget_corefreq {} { - set processor [xget_processor] - set name [xget_value $processor "NAME"] - puts "procname : $name" - set processor_driver [xget_swhandle [xget_value $processor "NAME"]] - puts "procdrv : $processor_driver" - if {[string compare -nocase $processor_driver ""] != 0} { - set arg "CORE_CLOCK_FREQ_HZ" - #set retval [xget_value $processor_driver "PARAMETER" $arg] - set retval [xget_dname [xget_value $processor_driver "NAME"] $arg] - return $retval - } -} - -# procedure that adds # defines to xparameters.h as XPAR_argument -proc xredefine_params {handle file_name args} { - - puts "xredfine ..." - # Open include file - set file_handle [xopen_include_file $file_name] - puts "args : $args" - - foreach arg $args { - if {[string compare -nocase $arg "CORE_CLOCK_FREQ_HZ"] == 0} { - set value [xget_corefreq] - puts "corefreq : $value" - } else { - set value [xget_value $handle "PARAMETER" $arg] - puts "value : $value" - } - - if {$value != ""} { - set value [xformat_addr_string $value $arg] - - if {[string compare -nocase $arg "IIC_PERSISTENT_BASEADDR"] == 0} { - set name "PERSISTENT_0_IIC_0_BASEADDR" - } elseif {[string compare -nocase $arg "IIC_PERSISTENT_HIGHADDR"] == 0} { - set name "PERSISTENT_0_IIC_0_HIGHADDR" - } elseif {[string compare -nocase $arg "IIC_PERSISTENT_EEPROMADDR"] == 0} { - set name "PERSISTENT_0_IIC_0_EEPROMADDR" - } else { - set name [string toupper $arg] - } - set name [format "XPAR_%s" $name] - puts $file_handle "#define $name $value" - } - } - - puts $file_handle "\n/******************************************************************/\n" - close $file_handle -} - -# uart redefines... -proc xredefine_uartns550 {drvhandle file_name} { - - xredefine_include_file $drvhandle $file_name "uartns550" "C_BASEADDR" "C_HIGHADDR" "CLOCK_HZ" "DEVICE_ID" - -} - -proc xredefine_emac {drvhandle file_name} { - - xredefine_include_file $drvhandle $file_name "emac" "C_BASEADDR" "C_HIGHADDR" "C_DMA_PRESENT" "C_MII_EXIST" "C_ERR_COUNT_EXIST" "DEVICE_ID" - -} - -proc xredefine_iic {drvhandle file_name} { - xredefine_include_file $drvhandle $file_name "iic" "C_BASEADDR" "C_HIGHADDR" "C_TEN_BIT_ADR" "DEVICE_ID" - -} - -####################### - -proc xredefine_include_file {drv_handle file_name drv_string args} { - - # Open include file - set file_handle [xopen_include_file $file_name] - - # Get all peripherals connected to this driver - set periphs [xget_periphs $drv_handle] - - set pname [format "XPAR_%s_" [string toupper $drv_string]] - - # Print all parameters for all peripherals - set device_id 0 - set sub_periphs 1 - foreach periph $periphs { - puts "$periph : $drv_string : $sub_periphs" - - for {set i 0} {$i < $sub_periphs} {incr i} { - foreach arg $args { - set name "${pname}${device_id}_" - - if {[string compare -nocase "CLOCK_HZ" $arg] == 0} { - set xdrv_string [format "%s%s" "X" $drv_string] - set value [xget_dname $xdrv_string $arg] - set name "${name}CLOCK_FREQ_HZ" - } else { - if {[string match C_* $arg]} { - set name [format "%s%s" $name [string range $arg 2 end]] - } else { - set name "${name}${arg}" - } - set value [xget_name $periph $arg] - } - - if {[string compare -nocase "uartns550" $drv_string] == 0} { - if {[string compare -nocase "C_BASEADDR" $arg] == 0} { - set value [format "(%s%s%s)" $value "+" "0x1000"] - } - } - - puts $file_handle "#define $name $value" - if {[string compare -nocase "DEVICE_ID" $arg] == 0} { - incr device_id - } - } - } - } - puts $file_handle "\n/******************************************************************/\n" - close $file_handle -} - -################################################## -# procedure post_generate -# This generates the drivers directory for uboot -# and runs the ltypes script -################################################## - -proc post_generate {lib_handle} { - - global drvlist - - # Create U-Boot tree structure - set pwd [pwd] - set common_dir "uboot/board/xilinx/common" - set xilinx_enet_dir "uboot/board/xilinx/xilinx_enet" - set ml300_dir "uboot/board/xilinx/ml300" - - exec bash -c "mkdir -p $common_dir $xilinx_enet_dir $ml300_dir" - - # Copy files for xilinx_ocp - xcopy_commonfiles - - foreach drv $drvlist { - set drvname [xget_value $drv "NAME"] - set ver [xget_value $drv "PARAMETER" "DRIVER_VER"] - set ver [string map {. _} $ver] - set dirname [format "%s_v%s" $drvname $ver] - - if {[string compare -nocase $drvname "emac"] == 0} { - xcopy_emac $drv $dirname - } elseif {[string compare -nocase $drvname "iic"] == 0} { - xcopy_iic $drv $dirname - } - } - - # Call Ltypes Script here - set uboot "uboot" - xltype_file $uboot - - # Move xparameters.h around - exec bash -c "cp ../../include/xparameters.h $ml300_dir" - - # copy the whole U-Boot BSP to its final destination - set value [xget_value $lib_handle "PARAMETER" TARGET_DIR] - puts "TARGET_DIR : $value" - - if {$value != ""} { - if {[file isdirectory $value] == 0} { - exec bash -c "mkdir -p $value" - } - exec bash -c "cp -Rp uboot/* $value" - } -} - -proc xcopy_commonfiles {} { - - global drvlist - - set common_dir "uboot/board/xilinx/common" - - foreach drv $drvlist { - set depends [xget_value $drv "OPTION" "DEPENDS"] - foreach dep $depends { - puts "dep : $dep" - if {[file isdirectory "../$dep"] == 1} { - exec bash -c "cp -f ../$dep/src/*.c $common_dir" - exec bash -c "cp -f ../$dep/src/*.h $common_dir" - } - } - } - -} - -proc xcopy_emac {drv_handle dirname} { - set emac "board/xilinx/xilinx_enet" - xcopy_dir $dirname $emac -} - -proc xcopy_iic {drv_handle dirname} { - set iic "board/xilinx/xilinx_iic" - xcopy_dir $dirname $iic -} - -proc xcopy_dir {srcdir dstdir} { - - set dstdirname [format "%s%s" "uboot/" $dstdir] - if {[file isdirectory "../$srcdir"] == 1} { - # Copy files from src to dst - exec bash -c "mkdir -p $dstdirname" - exec bash -c "cp -f ../$srcdir/src/*.c $dstdirname" - exec bash -c "cp -f ../$srcdir/src/*.h $dstdirname" - } else { - puts "$srcdir does not exist ..." - } -} - - -proc xltype_file {filename} { - - global ltypes - - puts $filename - - if {[file isdirectory $filename]} { - foreach entry [glob -nocomplain [file join $filename *]] { - xltype_file $entry - } - } else { - exec bash -c "$ltypes $filename" - } - -} diff --git a/board/xilinx/ml300/u-boot.lds b/board/xilinx/ml300/u-boot.lds deleted file mode 100644 index b6d748e..0000000 --- a/board/xilinx/ml300/u-boot.lds +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -ENTRY(_start) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ -/* - cpu/ppc4xx/start.o (.text) - board/xilinx/ml300/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) -*/ -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/xilinx/ml300/u-boot.lds.debug b/board/xilinx/ml300/u-boot.lds.debug deleted file mode 100644 index 1608f8c..0000000 --- a/board/xilinx/ml300/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/xilinx/ml300/xparameters.h b/board/xilinx/ml300/xparameters.h deleted file mode 100644 index 2c56737..0000000 --- a/board/xilinx/ml300/xparameters.h +++ /dev/null @@ -1,196 +0,0 @@ -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 6.2 EDK_Gm.11 -* DO NOT EDIT. -* -* Copyright (c) 2003 Xilinx, Inc. All rights reserved. -* -* Description: Driver parameters -* -*******************************************************************/ - -/******************************************************************/ - -/* U-Boot Redefines */ - -/******************************************************************/ - -#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000) -#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR -#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ -#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID -#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000) -#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR -#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ -#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID - -/******************************************************************/ - -#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR -#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR -#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR -#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR -#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR -#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT -#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST -#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST -#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ - -/******************************************************************/ - -#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 -#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF -#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 - -/******************************************************************/ - -#define XPAR_XPCI_NUM_INSTANCES 1 -#define XPAR_XPCI_CLOCK_HZ 33333333 -#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0 -#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000 -#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF -#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000 -#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004 -#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000 -#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000 -#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF -#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000 -#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF - -/******************************************************************/ - -#define XPAR_XEMAC_NUM_INSTANCES 1 -#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 -#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF -#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 -#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 -#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 -#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 - -/******************************************************************/ - -#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0 -#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000 -#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7) -#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1 -#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8) -#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F) -#define XPAR_XGPIO_NUM_INSTANCES 2 - -/******************************************************************/ - -#define XPAR_XIIC_NUM_INSTANCES 1 -#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 -#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF -#define XPAR_OPB_IIC_0_DEVICE_ID 0 -#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 - -/******************************************************************/ - -#define XPAR_XUARTNS550_NUM_INSTANCES 2 -#define XPAR_XUARTNS550_CLOCK_HZ 100000000 -#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000 -#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF -#define XPAR_OPB_UART16550_0_DEVICE_ID 0 -#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000 -#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF -#define XPAR_OPB_UART16550_1_DEVICE_ID 1 - -/******************************************************************/ - -#define XPAR_XSPI_NUM_INSTANCES 1 -#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000 -#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F -#define XPAR_OPB_SPI_0_DEVICE_ID 0 -#define XPAR_OPB_SPI_0_FIFO_EXIST 1 -#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0 -#define XPAR_OPB_SPI_0_NUM_SS_BITS 1 - -/******************************************************************/ - -#define XPAR_XPS2_NUM_INSTANCES 2 -#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 -#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000 -#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F) -#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1 -#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000) -#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F) - -/******************************************************************/ - -#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1 -#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000 -#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007 -#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0 - -/******************************************************************/ - -#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000 -#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF -#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000 -#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF -#define XPAR_PLB_DDR_0_BASEADDR 0x00000000 -#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF - -/******************************************************************/ - -#define XPAR_XINTC_HAS_IPR 1 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18 -#define XPAR_XINTC_USE_DCR 0 -#define XPAR_XINTC_NUM_INSTANCES 1 -#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0 -#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF -#define XPAR_DCR_INTC_0_DEVICE_ID 0 -#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000 - -/******************************************************************/ - -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0 -#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1 -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2 -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3 -#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4 -#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5 -#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6 -#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7 -#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8 -#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9 -#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10 -#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11 -#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12 -#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13 -#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14 -#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15 -#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16 -#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17 - -/******************************************************************/ - -#define XPAR_XTFT_NUM_INSTANCES 1 -#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200 -#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207 -#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0 - -/******************************************************************/ - -#define XPAR_XSYSACE_MEM_WIDTH 8 -#define XPAR_XSYSACE_NUM_INSTANCES 1 -#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000 -#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF -#define XPAR_OPB_SYSACE_0_DEVICE_ID 0 -#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8 - -/******************************************************************/ - -#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 - -/******************************************************************/ diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c deleted file mode 100644 index 1076345..0000000 --- a/board/xilinx/xilinx_enet/emac_adapter.c +++ /dev/null @@ -1,158 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ - -#include -#include -#include -#include "xparameters.h" -#include "xemac.h" - -#if defined(XPAR_EMAC_0_DEVICE_ID) -/* - * ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from - * PKTSIZE and PKTSIZE_ALIGN (include/net.h) - */ - -#define ENET_MAX_MTU PKTSIZE -#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN -#define ENET_ADDR_LENGTH 6 - -static XEmac Emac; -static char etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ - -/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/ -#ifdef CFG_ENV_IS_NOWHERE -static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; -#endif - -static int initialized = 0; - -void -eth_halt(void) -{ - if (initialized) - (void) XEmac_Stop(&Emac); -} - -int -eth_init(bd_t * bis) -{ - u32 Options; - XStatus Result; - -#ifdef DEBUG - printf("EMAC Initialization Started\n\r"); -#endif - - Result = XEmac_Initialize(&Emac, XPAR_EMAC_0_DEVICE_ID); - if (Result != XST_SUCCESS) { - return 0; - } - - /* make sure the Emac is stopped before it is started */ - (void) XEmac_Stop(&Emac); - -#ifdef CFG_ENV_IS_NOWHERE - memcpy(bis->bi_enetaddr, EMACAddr, 6); -#endif - - Result = XEmac_SetMacAddress(&Emac, bis->bi_enetaddr); - if (Result != XST_SUCCESS) { - return 0; - } - - Options = - (XEM_POLLED_OPTION | XEM_UNICAST_OPTION | XEM_BROADCAST_OPTION | - XEM_FDUPLEX_OPTION | XEM_INSERT_FCS_OPTION | - XEM_INSERT_PAD_OPTION); - Result = XEmac_SetOptions(&Emac, Options); - if (Result != XST_SUCCESS) { - return 0; - } - - Result = XEmac_Start(&Emac); - if (Result != XST_SUCCESS) { - return 0; - } -#ifdef DEBUG - printf("EMAC Initialization complete\n\r"); -#endif - - initialized = 1; - - return (0); -} - -/*-----------------------------------------------------------------------------+ -+-----------------------------------------------------------------------------*/ -int -eth_send(volatile void *ptr, int len) -{ - XStatus Result; - - if (len > ENET_MAX_MTU) - len = ENET_MAX_MTU; - - Result = XEmac_PollSend(&Emac, (u8 *) ptr, len); - if (Result == XST_SUCCESS) { - return (1); - } else { - printf("Error while sending frame\n\r"); - return (0); - } - -} - -int -eth_rx(void) -{ - u32 RecvFrameLength; - XStatus Result; - - RecvFrameLength = PKTSIZE; - Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength); - if (Result == XST_SUCCESS) { - NetReceive((uchar)etherrxbuff, RecvFrameLength); - return (1); - } else { - return (0); - } -} - -#endif diff --git a/board/xilinx/xilinx_enet/xemac.c b/board/xilinx/xilinx_enet/xemac.c deleted file mode 100644 index 48b4ede..0000000 --- a/board/xilinx/xilinx_enet/xemac.c +++ /dev/null @@ -1,844 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemac.c -* -* The XEmac driver. Functions in this file are the minimum required functions -* for this driver. See xemac.h for a detailed description of the driver. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm  07/31/01 First release
-* 1.00b rpm  02/20/02 Repartitioned files and functions
-* 1.00b rpm  07/23/02 Removed the PHY reset from Initialize()
-* 1.00b rmm  09/23/02 Removed commented code in Initialize(). Recycled as
-*                     XEmac_mPhyReset macro in xemac_l.h.
-* 1.00c rpm  12/05/02 New version includes support for simple DMA
-* 1.00c rpm  12/12/02 Changed location of IsStarted assignment in XEmac_Start
-*                     to be sure the flag is set before the device and
-*                     interrupts are enabled.
-* 1.00c rpm  02/03/03 SelfTest was not clearing polled mode. Take driver out
-*                     of polled mode in XEmac_Reset() to fix this problem.
-* 1.00c rmm  05/13/03 Fixed diab compiler warnings relating to asserts.
-*
-******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xemac_i.h" -#include "xio.h" -#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */ - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -static XStatus ConfigureDma(XEmac * InstancePtr); -static XStatus ConfigureFifo(XEmac * InstancePtr); -static void StubFifoHandler(void *CallBackRef); -static void StubErrorHandler(void *CallBackRef, XStatus ErrorCode); -static void StubSgHandler(void *CallBackRef, XBufDescriptor * BdPtr, - u32 NumBds); - -/************************** Variable Definitions *****************************/ - -/*****************************************************************************/ -/** -* -* Initialize a specific XEmac instance/driver. The initialization entails: -* - Initialize fields of the XEmac structure -* - Clear the Ethernet statistics for this device -* - Initialize the IPIF component with its register base address -* - Configure the FIFO components with their register base addresses. -* - If the device is configured with DMA, configure the DMA channel components -* with their register base addresses. At some later time, memory pools for -* the scatter-gather descriptor lists may be passed to the driver. -* - Reset the Ethernet MAC -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param DeviceId is the unique id of the device controlled by this XEmac -* instance. Passing in a device id associates the generic XEmac -* instance to a specific device, as chosen by the caller or application -* developer. -* -* @return -* -* - XST_SUCCESS if initialization was successful -* - XST_DEVICE_IS_STARTED if the device has already been started -* - XST_DEVICE_NOT_FOUND if device configuration information was not found for -* a device with the supplied device ID. -* -* @note -* -* None. -* -******************************************************************************/ -XStatus -XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId) -{ - XStatus Result; - XEmac_Config *ConfigPtr; /* configuration information */ - - XASSERT_NONVOID(InstancePtr != NULL); - - /* - * If the device is started, disallow the initialize and return a status - * indicating it is started. This allows the user to stop the device - * and reinitialize, but prevents a user from inadvertently initializing - */ - if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; - } - - /* - * Lookup the device configuration in the temporary CROM table. Use this - * configuration info down below when initializing this component. - */ - ConfigPtr = XEmac_LookupConfig(DeviceId); - if (ConfigPtr == NULL) { - return XST_DEVICE_NOT_FOUND; - } - - /* - * Set some default values - */ - InstancePtr->IsReady = 0; - InstancePtr->IsStarted = 0; - InstancePtr->IpIfDmaConfig = ConfigPtr->IpIfDmaConfig; - InstancePtr->HasMii = ConfigPtr->HasMii; - InstancePtr->HasMulticastHash = FALSE; - - /* Always default polled to false, let user configure this mode */ - InstancePtr->IsPolled = FALSE; - InstancePtr->FifoRecvHandler = StubFifoHandler; - InstancePtr->FifoSendHandler = StubFifoHandler; - InstancePtr->ErrorHandler = StubErrorHandler; - InstancePtr->SgRecvHandler = StubSgHandler; - InstancePtr->SgSendHandler = StubSgHandler; - - /* - * Clear the statistics for this driver - */ - XEmac_mClearStruct((u8 *) & InstancePtr->Stats, sizeof (XEmac_Stats)); - - /* - * Initialize the device register base addresses - */ - InstancePtr->BaseAddress = ConfigPtr->BaseAddress; - - /* - * Configure the send and receive FIFOs in the MAC - */ - Result = ConfigureFifo(InstancePtr); - if (Result != XST_SUCCESS) { - return Result; - } - - /* - * If the device is configured for DMA, configure the send and receive DMA - * channels in the MAC. - */ - if (XEmac_mIsDma(InstancePtr)) { - Result = ConfigureDma(InstancePtr); - if (Result != XST_SUCCESS) { - return Result; - } - } - - /* - * Indicate the component is now ready to use. Note that this is done before - * we reset the device and the PHY below, which may seem a bit odd. The - * choice was made to move it here rather than remove the asserts in various - * functions (e.g., Reset() and all functions that it calls). Applications - * that use multiple threads, one to initialize the XEmac driver and one - * waiting on the IsReady condition could have a problem with this sequence. - */ - InstancePtr->IsReady = XCOMPONENT_IS_READY; - - /* - * Reset the MAC to get it into its initial state. It is expected that - * device configuration by the user will take place after this - * initialization is done, but before the device is started. - */ - XEmac_Reset(InstancePtr); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Start the Ethernet controller as follows: -* - If not in polled mode -* - Set the internal interrupt enable registers appropriately -* - Enable interrupts within the device itself. Note that connection of -* the driver's interrupt handler to the interrupt source (typically -* done using the interrupt controller component) is done by the higher -* layer software. -* - If the device is configured with scatter-gather DMA, start the DMA -* channels if the descriptor lists are not empty -* - Enable the transmitter -* - Enable the receiver -* -* The PHY is enabled after driver initialization. We assume the upper layer -* software has configured it and the EMAC appropriately before this function -* is called. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* - XST_SUCCESS if the device was started successfully -* - XST_NO_CALLBACK if a callback function has not yet been registered using -* the SetxxxHandler function. This is required if in interrupt mode. -* - XST_DEVICE_IS_STARTED if the device is already started -* - XST_DMA_SG_NO_LIST if configured for scatter-gather DMA and a descriptor -* list has not yet been created for the send or receive channel. -* -* @note -* -* The driver tries to match the hardware configuration. So if the hardware -* is configured with scatter-gather DMA, the driver expects to start the -* scatter-gather channels and expects that the user has set up the buffer -* descriptor lists already. If the user expects to use the driver in a mode -* different than how the hardware is configured, the user should modify the -* configuration table to reflect the mode to be used. Modifying the config -* table is a workaround for now until we get some experience with how users -* are intending to use the hardware in its different configurations. For -* example, if the hardware is built with scatter-gather DMA but the user is -* intending to use only simple DMA, the user either needs to modify the config -* table as a workaround or rebuild the hardware with only simple DMA. -* -* This function makes use of internal resources that are shared between the -* Start, Stop, and SetOptions functions. So if one task might be setting device -* options while another is trying to start the device, the user is required to -* provide protection of this shared data (typically using a semaphore). -* -******************************************************************************/ -XStatus -XEmac_Start(XEmac * InstancePtr) -{ - u32 ControlReg; - XStatus Result; - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * If it is already started, return a status indicating so - */ - if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; - } - - /* - * If not polled, enable interrupts - */ - if (!InstancePtr->IsPolled) { - /* - * Verify that the callbacks have been registered, then enable - * interrupts - */ - if (XEmac_mIsSgDma(InstancePtr)) { - if ((InstancePtr->SgRecvHandler == StubSgHandler) || - (InstancePtr->SgSendHandler == StubSgHandler)) { - return XST_NO_CALLBACK; - } - - /* Enable IPIF interrupts */ - XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress, - XEM_IPIF_DMA_DFT_MASK | - XIIF_V123B_ERROR_MASK); - XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, - XEM_EIR_DFT_SG_MASK); - - /* Enable scatter-gather DMA interrupts */ - XDmaChannel_SetIntrEnable(&InstancePtr->RecvChannel, - XEM_DMA_SG_INTR_MASK); - XDmaChannel_SetIntrEnable(&InstancePtr->SendChannel, - XEM_DMA_SG_INTR_MASK); - } else { - if ((InstancePtr->FifoRecvHandler == StubFifoHandler) || - (InstancePtr->FifoSendHandler == StubFifoHandler)) { - return XST_NO_CALLBACK; - } - - /* Enable IPIF interrupts (used by simple DMA also) */ - XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress, - XEM_IPIF_FIFO_DFT_MASK | - XIIF_V123B_ERROR_MASK); - XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, - XEM_EIR_DFT_FIFO_MASK); - } - - /* Enable the global IPIF interrupt output */ - XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); - } - - /* - * Indicate that the device is started before we enable the transmitter - * or receiver. This needs to be done before because as soon as the - * receiver is enabled we may get an interrupt, and there are functions - * in the interrupt handling path that rely on the IsStarted flag. - */ - InstancePtr->IsStarted = XCOMPONENT_IS_STARTED; - - /* - * Enable the transmitter, and receiver (do a read/modify/write to preserve - * current settings). There is no critical section here since this register - * is not modified during interrupt context. - */ - ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET); - ControlReg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); - ControlReg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); - - XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg); - - /* - * If configured with scatter-gather DMA and not polled, restart the - * DMA channels in case there are buffers ready to be sent or received into. - * The DMA SgStart function uses data that can be modified during interrupt - * context, so a critical section is required here. - */ - if ((XEmac_mIsSgDma(InstancePtr)) && (!InstancePtr->IsPolled)) { - XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress); - - /* - * The only error we care about is if the list has not yet been - * created, or on receive, if no buffer descriptors have been - * added yet (the list is empty). Other errors are benign at this point. - */ - Result = XDmaChannel_SgStart(&InstancePtr->RecvChannel); - if ((Result == XST_DMA_SG_NO_LIST) - || (Result == XST_DMA_SG_LIST_EMPTY)) { - XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); - return Result; - } - - Result = XDmaChannel_SgStart(&InstancePtr->SendChannel); - if (Result == XST_DMA_SG_NO_LIST) { - XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); - return Result; - } - - XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Stop the Ethernet MAC as follows: -* - If the device is configured with scatter-gather DMA, stop the DMA -* channels (wait for acknowledgment of stop) -* - Disable the transmitter and receiver -* - Disable interrupts if not in polled mode (the higher layer software is -* responsible for disabling interrupts at the interrupt controller) -* -* The PHY is left enabled after a Stop is called. -* -* If the device is configured for scatter-gather DMA, the DMA engine stops at -* the next buffer descriptor in its list. The remaining descriptors in the list -* are not removed, so anything in the list will be transmitted or received when -* the device is restarted. The side effect of doing this is that the last -* buffer descriptor processed by the DMA engine before stopping may not be the -* last descriptor in the Ethernet frame. So when the device is restarted, a -* partial frame (i.e., a bad frame) may be transmitted/received. This is only a -* concern if a frame can span multiple buffer descriptors, which is dependent -* on the size of the network buffers. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* - XST_SUCCESS if the device was stopped successfully -* - XST_DEVICE_IS_STOPPED if the device is already stopped -* -* @note -* -* This function makes use of internal resources that are shared between the -* Start, Stop, and SetOptions functions. So if one task might be setting device -* options while another is trying to start the device, the user is required to -* provide protection of this shared data (typically using a semaphore). -* -******************************************************************************/ -XStatus -XEmac_Stop(XEmac * InstancePtr) -{ - u32 ControlReg; - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * If the device is already stopped, do nothing but return a status - * indicating so - */ - if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STOPPED; - } - - /* - * If configured for scatter-gather DMA, stop the DMA channels. Ignore - * the XST_DMA_SG_IS_STOPPED return code. There is a critical section - * here between SgStart and SgStop, and SgStart can be called in interrupt - * context, so disable interrupts while calling SgStop. - */ - if (XEmac_mIsSgDma(InstancePtr)) { - XBufDescriptor *BdTemp; /* temporary descriptor pointer */ - - XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress); - - (void) XDmaChannel_SgStop(&InstancePtr->SendChannel, &BdTemp); - (void) XDmaChannel_SgStop(&InstancePtr->RecvChannel, &BdTemp); - - XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); - } - - /* - * Disable the transmitter and receiver. There is no critical section - * here since this register is not modified during interrupt context. - */ - ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET); - ControlReg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); - XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg); - - /* - * If not in polled mode, disable interrupts for IPIF (includes MAC and - * DMAs) - */ - if (!InstancePtr->IsPolled) { - XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress); - } - - InstancePtr->IsStarted = 0; - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Reset the Ethernet MAC. This is a graceful reset in that the device is stopped -* first. Resets the DMA channels, the FIFOs, the transmitter, and the receiver. -* The PHY is not reset. Any frames in the scatter-gather descriptor lists will -* remain in the lists. The side effect of doing this is that after a reset and -* following a restart of the device, frames that were in the list before the -* reset may be transmitted or received. Reset must only be called after the -* driver has been initialized. -* -* The driver is also taken out of polled mode if polled mode was set. The user -* is responsbile for re-configuring the driver into polled mode after the -* reset if desired. -* -* The configuration after this reset is as follows: -* - Half duplex -* - Disabled transmitter and receiver -* - Enabled PHY (the PHY is not reset) -* - MAC transmitter does pad insertion, FCS insertion, and source address -* overwrite. -* - MAC receiver does not strip padding or FCS -* - Interframe Gap as recommended by IEEE Std. 802.3 (96 bit times) -* - Unicast addressing enabled -* - Broadcast addressing enabled -* - Multicast addressing disabled (addresses are preserved) -* - Promiscuous addressing disabled -* - Default packet threshold and packet wait bound register values for -* scatter-gather DMA operation -* - MAC address of all zeros -* - Non-polled mode -* -* The upper layer software is responsible for re-configuring (if necessary) -* and restarting the MAC after the reset. Note that the PHY is not reset. PHY -* control is left to the upper layer software. Note also that driver statistics -* are not cleared on reset. It is up to the upper layer software to clear the -* statistics if needed. -* -* When a reset is required due to an internal error, the driver notifies the -* upper layer software of this need through the ErrorHandler callback and -* specific status codes. The upper layer software is responsible for calling -* this Reset function and then re-configuring the device. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* None. -* -* @note -* -* None. -* -* @internal -* -* The reset is accomplished by setting the IPIF reset register. This takes -* care of resetting all hardware blocks, including the MAC. -* -******************************************************************************/ -void -XEmac_Reset(XEmac * InstancePtr) -{ - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * Stop the device first - */ - (void) XEmac_Stop(InstancePtr); - - /* - * Take the driver out of polled mode - */ - InstancePtr->IsPolled = FALSE; - - /* - * Reset the entire IPIF at once. If we choose someday to reset each - * hardware block separately, the reset should occur in the direction of - * data flow. For example, for the send direction the reset order is DMA - * first, then FIFO, then the MAC transmitter. - */ - XIIF_V123B_RESET(InstancePtr->BaseAddress); - - if (XEmac_mIsSgDma(InstancePtr)) { - /* - * After reset, configure the scatter-gather DMA packet threshold and - * packet wait bound registers to default values. Ignore the return - * values of these functions since they only return error if the device - * is not stopped. - */ - (void) XEmac_SetPktThreshold(InstancePtr, XEM_SEND, - XEM_SGDMA_DFT_THRESHOLD); - (void) XEmac_SetPktThreshold(InstancePtr, XEM_RECV, - XEM_SGDMA_DFT_THRESHOLD); - (void) XEmac_SetPktWaitBound(InstancePtr, XEM_SEND, - XEM_SGDMA_DFT_WAITBOUND); - (void) XEmac_SetPktWaitBound(InstancePtr, XEM_RECV, - XEM_SGDMA_DFT_WAITBOUND); - } -} - -/*****************************************************************************/ -/** -* -* Set the MAC address for this driver/device. The address is a 48-bit value. -* The device must be stopped before calling this function. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param AddressPtr is a pointer to a 6-byte MAC address. -* -* @return -* -* - XST_SUCCESS if the MAC address was set successfully -* - XST_DEVICE_IS_STARTED if the device has not yet been stopped -* -* @note -* -* None. -* -******************************************************************************/ -XStatus -XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr) -{ - u32 MacAddr = 0; - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(AddressPtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * The device must be stopped before setting the MAC address - */ - if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; - } - - /* - * Set the device station address high and low registers - */ - MacAddr = (AddressPtr[0] << 8) | AddressPtr[1]; - XIo_Out32(InstancePtr->BaseAddress + XEM_SAH_OFFSET, MacAddr); - - MacAddr = (AddressPtr[2] << 24) | (AddressPtr[3] << 16) | - (AddressPtr[4] << 8) | AddressPtr[5]; - - XIo_Out32(InstancePtr->BaseAddress + XEM_SAL_OFFSET, MacAddr); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Get the MAC address for this driver/device. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param BufferPtr is an output parameter, and is a pointer to a buffer into -* which the current MAC address will be copied. The buffer must be at -* least 6 bytes. -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -void -XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr) -{ - u32 MacAddrHi; - u32 MacAddrLo; - - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(BufferPtr != NULL); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - MacAddrHi = XIo_In32(InstancePtr->BaseAddress + XEM_SAH_OFFSET); - MacAddrLo = XIo_In32(InstancePtr->BaseAddress + XEM_SAL_OFFSET); - - BufferPtr[0] = (u8) (MacAddrHi >> 8); - BufferPtr[1] = (u8) MacAddrHi; - BufferPtr[2] = (u8) (MacAddrLo >> 24); - BufferPtr[3] = (u8) (MacAddrLo >> 16); - BufferPtr[4] = (u8) (MacAddrLo >> 8); - BufferPtr[5] = (u8) MacAddrLo; -} - -/******************************************************************************/ -/** -* -* Configure DMA capabilities. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* - XST_SUCCESS if successful initialization of DMA -* -* @note -* -* None. -* -******************************************************************************/ -static XStatus -ConfigureDma(XEmac * InstancePtr) -{ - XStatus Result; - - /* - * Initialize the DMA channels with their base addresses. We assume - * scatter-gather DMA is the only possible configuration. Descriptor space - * will need to be set later by the upper layer. - */ - Result = XDmaChannel_Initialize(&InstancePtr->RecvChannel, - InstancePtr->BaseAddress + - XEM_DMA_RECV_OFFSET); - if (Result != XST_SUCCESS) { - return Result; - } - - Result = XDmaChannel_Initialize(&InstancePtr->SendChannel, - InstancePtr->BaseAddress + - XEM_DMA_SEND_OFFSET); - - return Result; -} - -/******************************************************************************/ -/** -* -* Configure the send and receive FIFO components with their base addresses -* and interrupt masks. Currently the base addresses are defined constants. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* XST_SUCCESS if successful initialization of the packet FIFOs -* -* @note -* -* None. -* -******************************************************************************/ -static XStatus -ConfigureFifo(XEmac * InstancePtr) -{ - XStatus Result; - - /* - * Return status from the packet FIFOs initialization is ignored since - * they always return success. - */ - Result = XPacketFifoV100b_Initialize(&InstancePtr->RecvFifo, - InstancePtr->BaseAddress + - XEM_PFIFO_RXREG_OFFSET, - InstancePtr->BaseAddress + - XEM_PFIFO_RXDATA_OFFSET); - if (Result != XST_SUCCESS) { - return Result; - } - - Result = XPacketFifoV100b_Initialize(&InstancePtr->SendFifo, - InstancePtr->BaseAddress + - XEM_PFIFO_TXREG_OFFSET, - InstancePtr->BaseAddress + - XEM_PFIFO_TXDATA_OFFSET); - return Result; -} - -/******************************************************************************/ -/** -* -* This is a stub for the scatter-gather send and recv callbacks. The stub -* is here in case the upper layers forget to set the handlers. -* -* @param CallBackRef is a pointer to the upper layer callback reference -* @param BdPtr is a pointer to the first buffer descriptor in a list -* @param NumBds is the number of descriptors in the list. -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -static void -StubSgHandler(void *CallBackRef, XBufDescriptor * BdPtr, u32 NumBds) -{ - XASSERT_VOID_ALWAYS(); -} - -/******************************************************************************/ -/** -* -* This is a stub for the non-DMA send and recv callbacks. The stub is here in -* case the upper layers forget to set the handlers. -* -* @param CallBackRef is a pointer to the upper layer callback reference -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -static void -StubFifoHandler(void *CallBackRef) -{ - XASSERT_VOID_ALWAYS(); -} - -/******************************************************************************/ -/** -* -* This is a stub for the asynchronous error callback. The stub is here in -* case the upper layers forget to set the handler. -* -* @param CallBackRef is a pointer to the upper layer callback reference -* @param ErrorCode is the Xilinx error code, indicating the cause of the error -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -static void -StubErrorHandler(void *CallBackRef, XStatus ErrorCode) -{ - XASSERT_VOID_ALWAYS(); -} - -/*****************************************************************************/ -/** -* -* Lookup the device configuration based on the unique device ID. The table -* EmacConfigTable contains the configuration info for each device in the system. -* -* @param DeviceId is the unique device ID of the device being looked up. -* -* @return -* -* A pointer to the configuration table entry corresponding to the given -* device ID, or NULL if no match is found. -* -* @note -* -* None. -* -******************************************************************************/ -XEmac_Config * -XEmac_LookupConfig(u16 DeviceId) -{ - XEmac_Config *CfgPtr = NULL; - int i; - - for (i = 0; i < XPAR_XEMAC_NUM_INSTANCES; i++) { - if (XEmac_ConfigTable[i].DeviceId == DeviceId) { - CfgPtr = &XEmac_ConfigTable[i]; - break; - } - } - - return CfgPtr; -} diff --git a/board/xilinx/xilinx_enet/xemac.h b/board/xilinx/xilinx_enet/xemac.h deleted file mode 100644 index ed704bf..0000000 --- a/board/xilinx/xilinx_enet/xemac.h +++ /dev/null @@ -1,673 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemac.h -* -* The Xilinx Ethernet driver component. This component supports the Xilinx -* Ethernet 10/100 MAC (EMAC). -* -* The Xilinx Ethernet 10/100 MAC supports the following features: -* - Simple and scatter-gather DMA operations, as well as simple memory -* mapped direct I/O interface (FIFOs). -* - Media Independent Interface (MII) for connection to external -* 10/100 Mbps PHY transceivers. -* - MII management control reads and writes with MII PHYs -* - Independent internal transmit and receive FIFOs -* - CSMA/CD compliant operations for half-duplex modes -* - Programmable PHY reset signal -* - Unicast, broadcast, and promiscuous address filtering (no multicast yet) -* - Internal loopback -* - Automatic source address insertion or overwrite (programmable) -* - Automatic FCS insertion and stripping (programmable) -* - Automatic pad insertion and stripping (programmable) -* - Pause frame (flow control) detection in full-duplex mode -* - Programmable interframe gap -* - VLAN frame support. -* - Pause frame support -* -* The device driver supports all the features listed above. -* -* Driver Description -* -* The device driver enables higher layer software (e.g., an application) to -* communicate to the EMAC. The driver handles transmission and reception of -* Ethernet frames, as well as configuration of the controller. It does not -* handle protocol stack functionality such as Link Layer Control (LLC) or the -* Address Resolution Protocol (ARP). The protocol stack that makes use of the -* driver handles this functionality. This implies that the driver is simply a -* pass-through mechanism between a protocol stack and the EMAC. A single device -* driver can support multiple EMACs. -* -* The driver is designed for a zero-copy buffer scheme. That is, the driver will -* not copy buffers. This avoids potential throughput bottlenecks within the -* driver. -* -* Since the driver is a simple pass-through mechanism between a protocol stack -* and the EMAC, no assembly or disassembly of Ethernet frames is done at the -* driver-level. This assumes that the protocol stack passes a correctly -* formatted Ethernet frame to the driver for transmission, and that the driver -* does not validate the contents of an incoming frame -* -* PHY Communication -* -* The driver provides rudimentary read and write functions to allow the higher -* layer software to access the PHY. The EMAC provides MII registers for the -* driver to access. This management interface can be parameterized away in the -* FPGA implementation process. If this is the case, the PHY read and write -* functions of the driver return XST_NO_FEATURE. -* -* External loopback is usually supported at the PHY. It is up to the user to -* turn external loopback on or off at the PHY. The driver simply provides pass- -* through functions for configuring the PHY. The driver does not read, write, -* or reset the PHY on its own. All control of the PHY must be done by the user. -* -* Asynchronous Callbacks -* -* The driver services interrupts and passes Ethernet frames to the higher layer -* software through asynchronous callback functions. When using the driver -* directly (i.e., not with the RTOS protocol stack), the higher layer -* software must register its callback functions during initialization. The -* driver requires callback functions for received frames, for confirmation of -* transmitted frames, and for asynchronous errors. -* -* Interrupts -* -* The driver has no dependencies on the interrupt controller. The driver -* provides two interrupt handlers. XEmac_IntrHandlerDma() handles interrupts -* when the EMAC is configured with scatter-gather DMA. XEmac_IntrHandlerFifo() -* handles interrupts when the EMAC is configured for direct FIFO I/O or simple -* DMA. Either of these routines can be connected to the system interrupt -* controller by the user. -* -* Interrupt Frequency -* -* When the EMAC is configured with scatter-gather DMA, the frequency of -* interrupts can be controlled with the interrupt coalescing features of the -* scatter-gather DMA engine. The frequency of interrupts can be adjusted using -* the driver API functions for setting the packet count threshold and the packet -* wait bound values. -* -* The scatter-gather DMA engine only interrupts when the packet count threshold -* is reached, instead of interrupting for each packet. A packet is a generic -* term used by the scatter-gather DMA engine, and is equivalent to an Ethernet -* frame in our case. -* -* The packet wait bound is a timer value used during interrupt coalescing to -* trigger an interrupt when not enough packets have been received to reach the -* packet count threshold. -* -* These values can be tuned by the user to meet their needs. If there appear to -* be interrupt latency problems or delays in packet arrival that are longer than -* might be expected, the user should verify that the packet count threshold is -* set low enough to receive interrupts before the wait bound timer goes off. -* -* Device Reset -* -* Some errors that can occur in the device require a device reset. These errors -* are listed in the XEmac_SetErrorHandler() function header. The user's error -* handler is responsible for resetting the device and re-configuring it based on -* its needs (the driver does not save the current configuration). When -* integrating into an RTOS, these reset and re-configure obligations are -* taken care of by the Xilinx adapter software if it exists for that RTOS. -* -* Device Configuration -* -* The device can be configured in various ways during the FPGA implementation -* process. Configuration parameters are stored in the xemac_g.c files. -* A table is defined where each entry contains configuration information -* for an EMAC device. This information includes such things as the base address -* of the memory-mapped device, the base addresses of IPIF, DMA, and FIFO modules -* within the device, and whether the device has DMA, counter registers, -* multicast support, MII support, and flow control. -* -* The driver tries to use the features built into the device. So if, for -* example, the hardware is configured with scatter-gather DMA, the driver -* expects to start the scatter-gather channels and expects that the user has set -* up the buffer descriptor lists already. If the user expects to use the driver -* in a mode different than how the hardware is configured, the user should -* modify the configuration table to reflect the mode to be used. Modifying the -* configuration table is a workaround for now until we get some experience with -* how users are intending to use the hardware in its different configurations. -* For example, if the hardware is built with scatter-gather DMA but the user is -* intending to use only simple DMA, the user either needs to modify the config -* table as a workaround or rebuild the hardware with only simple DMA. The -* recommendation at this point is to build the hardware with the features you -* intend to use. If you're inclined to modify the table, do so before the call -* to XEmac_Initialize(). Here is a snippet of code that changes a device to -* simple DMA (the hardware needs to have DMA for this to work of course): -* 
-*	 XEmac_Config *ConfigPtr;
-*
-*	 ConfigPtr = XEmac_LookupConfig(DeviceId);
-*	 ConfigPtr->IpIfDmaConfig = XEM_CFG_SIMPLE_DMA;
-*
-* -* Simple DMA -* -* Simple DMA is supported through the FIFO functions, FifoSend and FifoRecv, of -* the driver (i.e., there is no separate interface for it). The driver makes use -* of the DMA engine for a simple DMA transfer if the device is configured with -* DMA, otherwise it uses the FIFOs directly. While the simple DMA interface is -* therefore transparent to the user, the caching of network buffers is not. -* If the device is configured with DMA and the FIFO interface is used, the user -* must ensure that the network buffers are not cached or are cache coherent, -* since DMA will be used to transfer to and from the Emac device. If the device -* is configured with DMA and the user really wants to use the FIFOs directly, -* the user should rebuild the hardware without DMA. If unable to do this, there -* is a workaround (described above in Device Configuration) to modify the -* configuration table of the driver to fake the driver into thinking the device -* has no DMA. A code snippet follows: -* 
-*	 XEmac_Config *ConfigPtr;
-*
-*	 ConfigPtr = XEmac_LookupConfig(DeviceId);
-*	 ConfigPtr->IpIfDmaConfig = XEM_CFG_NO_DMA;
-*
-* -* Asserts -* -* Asserts are used within all Xilinx drivers to enforce constraints on argument -* values. Asserts can be turned off on a system-wide basis by defining, at -* compile time, the NDEBUG identifier. By default, asserts are turned on and it -* is recommended that users leave asserts on during development. -* -* Building the driver -* -* The XEmac driver is composed of several source files. Why so many? This -* allows the user to build and link only those parts of the driver that are -* necessary. Since the EMAC hardware can be configured in various ways (e.g., -* with or without DMA), the driver too can be built with varying features. -* For the most part, this means that besides always linking in xemac.c, you -* link in only the driver functionality you want. Some of the choices you have -* are polled vs. interrupt, interrupt with FIFOs only vs. interrupt with DMA, -* self-test diagnostics, and driver statistics. Note that currently the DMA code -* must be linked in, even if you don't have DMA in the device. -* -* @note -* -* Xilinx drivers are typically composed of two components, one is the driver -* and the other is the adapter. The driver is independent of OS and processor -* and is intended to be highly portable. The adapter is OS-specific and -* facilitates communication between the driver and an OS. -*

-* This driver is intended to be RTOS and processor independent. It works -* with physical addresses only. Any needs for dynamic memory management, -* threads or thread mutual exclusion, virtual memory, or cache control must -* be satisfied by the layer above this driver. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver	Who  Date     Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm  07/31/01 First release
-* 1.00b rpm  02/20/02 Repartitioned files and functions
-* 1.00b rpm  10/08/02 Replaced HasSgDma boolean with IpifDmaConfig enumerated
-*		      configuration parameter
-* 1.00c rpm  12/05/02 New version includes support for simple DMA and the delay
-*		      argument to SgSend
-* 1.00c rpm  02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
-*		      from SetPktThreshold in the internal DMA driver. Also
-*		      avoided compiler warnings by initializing Result in the
-*		      DMA interrupt service routines.
-*
-* -******************************************************************************/ - -#ifndef XEMAC_H /* prevent circular inclusions */ -#define XEMAC_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xstatus.h" -#include "xparameters.h" -#include "xpacket_fifo_v1_00_b.h" /* Uses v1.00b of Packet Fifo */ -#include "xdma_channel.h" - -/************************** Constant Definitions *****************************/ - -/* - * Device information - */ -#define XEM_DEVICE_NAME "xemac" -#define XEM_DEVICE_DESC "Xilinx Ethernet 10/100 MAC" - -/** @name Configuration options - * - * Device configuration options (see the XEmac_SetOptions() and - * XEmac_GetOptions() for information on how to use these options) - * @{ - */ -/** - * 
- *   XEM_BROADCAST_OPTION	 Broadcast addressing on or off (default is on)
- *   XEM_UNICAST_OPTION		 Unicast addressing on or off (default is on)
- *   XEM_PROMISC_OPTION		 Promiscuous addressing on or off (default is off)
- *   XEM_FDUPLEX_OPTION		 Full duplex on or off (default is off)
- *   XEM_POLLED_OPTION		 Polled mode on or off (default is off)
- *   XEM_LOOPBACK_OPTION	 Internal loopback on or off (default is off)
- *   XEM_FLOW_CONTROL_OPTION	 Interpret pause frames in full duplex mode
- *				 (default is off)
- *   XEM_INSERT_PAD_OPTION	 Pad short frames on transmit (default is on)
- *   XEM_INSERT_FCS_OPTION	 Insert FCS (CRC) on transmit (default is on)
- *   XEM_INSERT_ADDR_OPTION	 Insert source address on transmit (default is on)
- *   XEM_OVWRT_ADDR_OPTION	 Overwrite source address on transmit. This is
- *				 only used if source address insertion is on.
- *				 (default is on)
- *   XEM_STRIP_PAD_FCS_OPTION	 Strip FCS and padding from received frames
- *				 (default is off)
-  *
- */ -#define XEM_UNICAST_OPTION 0x00000001UL -#define XEM_BROADCAST_OPTION 0x00000002UL -#define XEM_PROMISC_OPTION 0x00000004UL -#define XEM_FDUPLEX_OPTION 0x00000008UL -#define XEM_POLLED_OPTION 0x00000010UL -#define XEM_LOOPBACK_OPTION 0x00000020UL -#define XEM_FLOW_CONTROL_OPTION 0x00000080UL -#define XEM_INSERT_PAD_OPTION 0x00000100UL -#define XEM_INSERT_FCS_OPTION 0x00000200UL -#define XEM_INSERT_ADDR_OPTION 0x00000400UL -#define XEM_OVWRT_ADDR_OPTION 0x00000800UL -#define XEM_STRIP_PAD_FCS_OPTION 0x00002000UL -/*@}*/ -/* - * Not supported yet: - * XEM_MULTICAST_OPTION Multicast addressing on or off (default is off) - */ -/* NOT SUPPORTED YET... */ -#define XEM_MULTICAST_OPTION 0x00000040UL - -/* - * Some default values for interrupt coalescing within the scatter-gather - * DMA engine. - */ -#define XEM_SGDMA_DFT_THRESHOLD 1 /* Default pkt threshold */ -#define XEM_SGDMA_MAX_THRESHOLD 255 /* Maximum pkt theshold */ -#define XEM_SGDMA_DFT_WAITBOUND 5 /* Default pkt wait bound (msec) */ -#define XEM_SGDMA_MAX_WAITBOUND 1023 /* Maximum pkt wait bound (msec) */ - -/* - * Direction identifiers. These are used for setting values like packet - * thresholds and wait bound for specific channels - */ -#define XEM_SEND 1 -#define XEM_RECV 2 - -/* - * Arguments to SgSend function to indicate whether to hold off starting - * the scatter-gather engine. - */ -#define XEM_SGDMA_NODELAY 0 /* start SG DMA immediately */ -#define XEM_SGDMA_DELAY 1 /* do not start SG DMA */ - -/* - * Constants to determine the configuration of the hardware device. They are - * used to allow the driver to verify it can operate with the hardware. - */ -#define XEM_CFG_NO_IPIF 0 /* Not supported by the driver */ -#define XEM_CFG_NO_DMA 1 /* No DMA */ -#define XEM_CFG_SIMPLE_DMA 2 /* Simple DMA */ -#define XEM_CFG_DMA_SG 3 /* DMA scatter gather */ - -/* - * The next few constants help upper layers determine the size of memory - * pools used for Ethernet buffers and descriptor lists. - */ -#define XEM_MAC_ADDR_SIZE 6 /* six-byte MAC address */ -#define XEM_MTU 1500 /* max size of Ethernet frame */ -#define XEM_HDR_SIZE 14 /* size of Ethernet header */ -#define XEM_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */ -#define XEM_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ -#define XEM_MAX_FRAME_SIZE (XEM_MTU + XEM_HDR_SIZE + XEM_TRL_SIZE) -#define XEM_MAX_VLAN_FRAME_SIZE (XEM_MTU + XEM_HDR_VLAN_SIZE + XEM_TRL_SIZE) - -/* - * Define a default number of send and receive buffers - */ -#define XEM_MIN_RECV_BUFS 32 /* minimum # of recv buffers */ -#define XEM_DFT_RECV_BUFS 64 /* default # of recv buffers */ - -#define XEM_MIN_SEND_BUFS 16 /* minimum # of send buffers */ -#define XEM_DFT_SEND_BUFS 32 /* default # of send buffers */ - -#define XEM_MIN_BUFFERS (XEM_MIN_RECV_BUFS + XEM_MIN_SEND_BUFS) -#define XEM_DFT_BUFFERS (XEM_DFT_RECV_BUFS + XEM_DFT_SEND_BUFS) - -/* - * Define the number of send and receive buffer descriptors, used for - * scatter-gather DMA - */ -#define XEM_MIN_RECV_DESC 16 /* minimum # of recv descriptors */ -#define XEM_DFT_RECV_DESC 32 /* default # of recv descriptors */ - -#define XEM_MIN_SEND_DESC 8 /* minimum # of send descriptors */ -#define XEM_DFT_SEND_DESC 16 /* default # of send descriptors */ - -/**************************** Type Definitions *******************************/ - -/** - * Ethernet statistics (see XEmac_GetStats() and XEmac_ClearStats()) - */ -typedef struct { - u32 XmitFrames; /**< Number of frames transmitted */ - u32 XmitBytes; /**< Number of bytes transmitted */ - u32 XmitLateCollisionErrors; - /**< Number of transmission failures - due to late collisions */ - u32 XmitExcessDeferral; /**< Number of transmission failures - due o excess collision deferrals */ - u32 XmitOverrunErrors; /**< Number of transmit overrun errors */ - u32 XmitUnderrunErrors; /**< Number of transmit underrun errors */ - u32 RecvFrames; /**< Number of frames received */ - u32 RecvBytes; /**< Number of bytes received */ - u32 RecvFcsErrors; /**< Number of frames discarded due - to FCS errors */ - u32 RecvAlignmentErrors; /**< Number of frames received with - alignment errors */ - u32 RecvOverrunErrors; /**< Number of frames discarded due - to overrun errors */ - u32 RecvUnderrunErrors; /**< Number of recv underrun errors */ - u32 RecvMissedFrameErrors; - /**< Number of frames missed by MAC */ - u32 RecvCollisionErrors; /**< Number of frames discarded due - to collisions */ - u32 RecvLengthFieldErrors; - /**< Number of frames discarded with - invalid length field */ - u32 RecvShortErrors; /**< Number of short frames discarded */ - u32 RecvLongErrors; /**< Number of long frames discarded */ - u32 DmaErrors; /**< Number of DMA errors since init */ - u32 FifoErrors; /**< Number of FIFO errors since init */ - u32 RecvInterrupts; /**< Number of receive interrupts */ - u32 XmitInterrupts; /**< Number of transmit interrupts */ - u32 EmacInterrupts; /**< Number of MAC (device) interrupts */ - u32 TotalIntrs; /**< Total interrupts */ -} XEmac_Stats; - -/** - * This typedef contains configuration information for a device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Register base address */ - u32 HasCounters; /**< Does device have counters? */ - u8 IpIfDmaConfig; /**< IPIF/DMA hardware configuration */ - u32 HasMii; /**< Does device support MII? */ - -} XEmac_Config; - -/** @name Typedefs for callbacks - * Callback functions. - * @{ - */ -/** - * Callback when data is sent or received with scatter-gather DMA. - * - * @param CallBackRef is a callback reference passed in by the upper layer - * when setting the callback functions, and passed back to the upper - * layer when the callback is invoked. - * @param BdPtr is a pointer to the first buffer descriptor in a list of - * buffer descriptors. - * @param NumBds is the number of buffer descriptors in the list pointed - * to by BdPtr. - */ -typedef void (*XEmac_SgHandler) (void *CallBackRef, XBufDescriptor * BdPtr, - u32 NumBds); - -/** - * Callback when data is sent or received with direct FIFO communication or - * simple DMA. The user typically defines two callacks, one for send and one - * for receive. - * - * @param CallBackRef is a callback reference passed in by the upper layer - * when setting the callback functions, and passed back to the upper - * layer when the callback is invoked. - */ -typedef void (*XEmac_FifoHandler) (void *CallBackRef); - -/** - * Callback when an asynchronous error occurs. - * - * @param CallBackRef is a callback reference passed in by the upper layer - * when setting the callback functions, and passed back to the upper - * layer when the callback is invoked. - * @param ErrorCode is a Xilinx error code defined in xstatus.h. Also see - * XEmac_SetErrorHandler() for a description of possible errors. - */ -typedef void (*XEmac_ErrorHandler) (void *CallBackRef, XStatus ErrorCode); -/*@}*/ - -/** - * The XEmac driver instance data. The user is required to allocate a - * variable of this type for every EMAC device in the system. A pointer - * to a variable of this type is then passed to the driver API functions. - */ -typedef struct { - u32 BaseAddress; /* Base address (of IPIF) */ - u32 IsStarted; /* Device is currently started */ - u32 IsReady; /* Device is initialized and ready */ - u32 IsPolled; /* Device is in polled mode */ - u8 IpIfDmaConfig; /* IPIF/DMA hardware configuration */ - u32 HasMii; /* Does device support MII? */ - u32 HasMulticastHash; /* Does device support multicast hash table? */ - - XEmac_Stats Stats; - XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */ - XPacketFifoV100b SendFifo; /* FIFO used to send frames */ - - /* - * Callbacks - */ - XEmac_FifoHandler FifoRecvHandler; /* for non-DMA/simple DMA interrupts */ - void *FifoRecvRef; - XEmac_FifoHandler FifoSendHandler; /* for non-DMA/simple DMA interrupts */ - void *FifoSendRef; - XEmac_ErrorHandler ErrorHandler; /* for asynchronous errors */ - void *ErrorRef; - - XDmaChannel RecvChannel; /* DMA receive channel driver */ - XDmaChannel SendChannel; /* DMA send channel driver */ - - XEmac_SgHandler SgRecvHandler; /* callback for scatter-gather DMA */ - void *SgRecvRef; - XEmac_SgHandler SgSendHandler; /* callback for scatter-gather DMA */ - void *SgSendRef; -} XEmac; - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/** -* -* This macro determines if the device is currently configured for -* scatter-gather DMA. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* Boolean TRUE if the device is configured for scatter-gather DMA, or FALSE -* if it is not. -* -* @note -* -* Signature: u32 XEmac_mIsSgDma(XEmac *InstancePtr) -* -******************************************************************************/ -#define XEmac_mIsSgDma(InstancePtr) \ - ((InstancePtr)->IpIfDmaConfig == XEM_CFG_DMA_SG) - -/*****************************************************************************/ -/** -* -* This macro determines if the device is currently configured for simple DMA. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* Boolean TRUE if the device is configured for simple DMA, or FALSE otherwise -* -* @note -* -* Signature: u32 XEmac_mIsSimpleDma(XEmac *InstancePtr) -* -******************************************************************************/ -#define XEmac_mIsSimpleDma(InstancePtr) \ - ((InstancePtr)->IpIfDmaConfig == XEM_CFG_SIMPLE_DMA) - -/*****************************************************************************/ -/** -* -* This macro determines if the device is currently configured with DMA (either -* simple DMA or scatter-gather DMA) -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* Boolean TRUE if the device is configured with DMA, or FALSE otherwise -* -* @note -* -* Signature: u32 XEmac_mIsDma(XEmac *InstancePtr) -* -******************************************************************************/ -#define XEmac_mIsDma(InstancePtr) \ - (XEmac_mIsSimpleDma(InstancePtr) || XEmac_mIsSgDma(InstancePtr)) - -/************************** Function Prototypes ******************************/ - -/* - * Initialization functions in xemac.c - */ -XStatus XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId); -XStatus XEmac_Start(XEmac * InstancePtr); -XStatus XEmac_Stop(XEmac * InstancePtr); -void XEmac_Reset(XEmac * InstancePtr); -XEmac_Config *XEmac_LookupConfig(u16 DeviceId); - -/* - * Diagnostic functions in xemac_selftest.c - */ -XStatus XEmac_SelfTest(XEmac * InstancePtr); - -/* - * Polled functions in xemac_polled.c - */ -XStatus XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount); -XStatus XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr); - -/* - * Interrupts with scatter-gather DMA functions in xemac_intr_dma.c - */ -XStatus XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay); -XStatus XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr); -XStatus XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold); -XStatus XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction, - u8 * ThreshPtr); -XStatus XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction, - u32 TimerValue); -XStatus XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction, - u32 * WaitPtr); -XStatus XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr, - u32 ByteCount); -XStatus XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr, - u32 ByteCount); -void XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef, - XEmac_SgHandler FuncPtr); -void XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef, - XEmac_SgHandler FuncPtr); - -void XEmac_IntrHandlerDma(void *InstancePtr); /* interrupt handler */ - -/* - * Interrupts with direct FIFO functions in xemac_intr_fifo.c. Also used - * for simple DMA. - */ -XStatus XEmac_FifoSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount); -XStatus XEmac_FifoRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr); -void XEmac_SetFifoRecvHandler(XEmac * InstancePtr, void *CallBackRef, - XEmac_FifoHandler FuncPtr); -void XEmac_SetFifoSendHandler(XEmac * InstancePtr, void *CallBackRef, - XEmac_FifoHandler FuncPtr); - -void XEmac_IntrHandlerFifo(void *InstancePtr); /* interrupt handler */ - -/* - * General interrupt-related functions in xemac_intr.c - */ -void XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef, - XEmac_ErrorHandler FuncPtr); - -/* - * MAC configuration in xemac_options.c - */ -XStatus XEmac_SetOptions(XEmac * InstancePtr, u32 OptionFlag); -u32 XEmac_GetOptions(XEmac * InstancePtr); -XStatus XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr); -void XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr); -XStatus XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2); -void XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr); - -/* - * Multicast functions in xemac_multicast.c (not supported by EMAC yet) - */ -XStatus XEmac_MulticastAdd(XEmac * InstancePtr, u8 * AddressPtr); -XStatus XEmac_MulticastClear(XEmac * InstancePtr); - -/* - * PHY configuration in xemac_phy.c - */ -XStatus XEmac_PhyRead(XEmac * InstancePtr, u32 PhyAddress, - u32 RegisterNum, u16 * PhyDataPtr); -XStatus XEmac_PhyWrite(XEmac * InstancePtr, u32 PhyAddress, - u32 RegisterNum, u16 PhyData); - -/* - * Statistics in xemac_stats.c - */ -void XEmac_GetStats(XEmac * InstancePtr, XEmac_Stats * StatsPtr); -void XEmac_ClearStats(XEmac * InstancePtr); - -#endif /* end of protection macro */ diff --git a/board/xilinx/xilinx_enet/xemac_g.c b/board/xilinx/xilinx_enet/xemac_g.c deleted file mode 100644 index 9340f91..0000000 --- a/board/xilinx/xilinx_enet/xemac_g.c +++ /dev/null @@ -1,60 +0,0 @@ -/******************************************************************* -* -* CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 6.1.2 EDK_G.14 -* DO NOT EDIT. -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -* Description: Driver configuration -* -*******************************************************************/ - -#include "xparameters.h" -#include "xemac.h" - -/* -* The configuration table for devices -*/ - -XEmac_Config XEmac_ConfigTable[] = { - { - XPAR_OPB_ETHERNET_0_DEVICE_ID, - XPAR_OPB_ETHERNET_0_BASEADDR, - XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST, - XPAR_OPB_ETHERNET_0_DMA_PRESENT, - XPAR_OPB_ETHERNET_0_MII_EXIST} -}; diff --git a/board/xilinx/xilinx_enet/xemac_i.h b/board/xilinx/xilinx_enet/xemac_i.h deleted file mode 100644 index 9c160f3..0000000 --- a/board/xilinx/xilinx_enet/xemac_i.h +++ /dev/null @@ -1,207 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemac_i.h -* -* This header file contains internal identifiers, which are those shared -* between XEmac components. The identifiers in this file are not intended for -* use external to the driver. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver	Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rpm  07/31/01 First release
-* 1.00b rpm  02/20/02 Repartitioned files and functions
-* 1.00b rpm  04/29/02 Moved register definitions to xemac_l.h
-* 1.00c rpm  12/05/02 New version includes support for simple DMA
-*
-* -******************************************************************************/ - -#ifndef XEMAC_I_H /* prevent circular inclusions */ -#define XEMAC_I_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xemac.h" -#include "xemac_l.h" - -/************************** Constant Definitions *****************************/ - -/* - * Default buffer descriptor control word masks. The default send BD control - * is set for incrementing the source address by one for each byte transferred, - * and specify that the destination address (FIFO) is local to the device. The - * default receive BD control is set for incrementing the destination address - * by one for each byte transferred, and specify that the source address is - * local to the device. - */ -#define XEM_DFT_SEND_BD_MASK (XDC_DMACR_SOURCE_INCR_MASK | \ - XDC_DMACR_DEST_LOCAL_MASK) -#define XEM_DFT_RECV_BD_MASK (XDC_DMACR_DEST_INCR_MASK | \ - XDC_DMACR_SOURCE_LOCAL_MASK) - -/* - * Masks for the IPIF Device Interrupt enable and status registers. - */ -#define XEM_IPIF_EMAC_MASK 0x00000004UL /* MAC interrupt */ -#define XEM_IPIF_SEND_DMA_MASK 0x00000008UL /* Send DMA interrupt */ -#define XEM_IPIF_RECV_DMA_MASK 0x00000010UL /* Receive DMA interrupt */ -#define XEM_IPIF_RECV_FIFO_MASK 0x00000020UL /* Receive FIFO interrupt */ -#define XEM_IPIF_SEND_FIFO_MASK 0x00000040UL /* Send FIFO interrupt */ - -/* - * Default IPIF Device Interrupt mask when configured for DMA - */ -#define XEM_IPIF_DMA_DFT_MASK (XEM_IPIF_SEND_DMA_MASK | \ - XEM_IPIF_RECV_DMA_MASK | \ - XEM_IPIF_EMAC_MASK | \ - XEM_IPIF_SEND_FIFO_MASK | \ - XEM_IPIF_RECV_FIFO_MASK) - -/* - * Default IPIF Device Interrupt mask when configured without DMA - */ -#define XEM_IPIF_FIFO_DFT_MASK (XEM_IPIF_EMAC_MASK | \ - XEM_IPIF_SEND_FIFO_MASK | \ - XEM_IPIF_RECV_FIFO_MASK) - -#define XEM_IPIF_DMA_DEV_INTR_COUNT 7 /* Number of interrupt sources */ -#define XEM_IPIF_FIFO_DEV_INTR_COUNT 5 /* Number of interrupt sources */ -#define XEM_IPIF_DEVICE_INTR_COUNT 7 /* Number of interrupt sources */ -#define XEM_IPIF_IP_INTR_COUNT 22 /* Number of MAC interrupts */ - -/* a mask for all transmit interrupts, used in polled mode */ -#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK | \ - XEM_EIR_XMIT_ERROR_MASK | \ - XEM_EIR_XMIT_SFIFO_EMPTY_MASK | \ - XEM_EIR_XMIT_LFIFO_FULL_MASK) - -/* a mask for all receive interrupts, used in polled mode */ -#define XEM_EIR_RECV_ALL_MASK (XEM_EIR_RECV_DONE_MASK | \ - XEM_EIR_RECV_ERROR_MASK | \ - XEM_EIR_RECV_LFIFO_EMPTY_MASK | \ - XEM_EIR_RECV_LFIFO_OVER_MASK | \ - XEM_EIR_RECV_LFIFO_UNDER_MASK | \ - XEM_EIR_RECV_DFIFO_OVER_MASK | \ - XEM_EIR_RECV_MISSED_FRAME_MASK | \ - XEM_EIR_RECV_COLLISION_MASK | \ - XEM_EIR_RECV_FCS_ERROR_MASK | \ - XEM_EIR_RECV_LEN_ERROR_MASK | \ - XEM_EIR_RECV_SHORT_ERROR_MASK | \ - XEM_EIR_RECV_LONG_ERROR_MASK | \ - XEM_EIR_RECV_ALIGN_ERROR_MASK) - -/* a default interrupt mask for scatter-gather DMA operation */ -#define XEM_EIR_DFT_SG_MASK (XEM_EIR_RECV_ERROR_MASK | \ - XEM_EIR_RECV_LFIFO_OVER_MASK | \ - XEM_EIR_RECV_LFIFO_UNDER_MASK | \ - XEM_EIR_XMIT_SFIFO_OVER_MASK | \ - XEM_EIR_XMIT_SFIFO_UNDER_MASK | \ - XEM_EIR_XMIT_LFIFO_OVER_MASK | \ - XEM_EIR_XMIT_LFIFO_UNDER_MASK | \ - XEM_EIR_RECV_DFIFO_OVER_MASK | \ - XEM_EIR_RECV_MISSED_FRAME_MASK | \ - XEM_EIR_RECV_COLLISION_MASK | \ - XEM_EIR_RECV_FCS_ERROR_MASK | \ - XEM_EIR_RECV_LEN_ERROR_MASK | \ - XEM_EIR_RECV_SHORT_ERROR_MASK | \ - XEM_EIR_RECV_LONG_ERROR_MASK | \ - XEM_EIR_RECV_ALIGN_ERROR_MASK) - -/* a default interrupt mask for non-DMA operation (direct FIFOs) */ -#define XEM_EIR_DFT_FIFO_MASK (XEM_EIR_XMIT_DONE_MASK | \ - XEM_EIR_RECV_DONE_MASK | \ - XEM_EIR_DFT_SG_MASK) - -/* - * Mask for the DMA interrupt enable and status registers when configured - * for scatter-gather DMA. - */ -#define XEM_DMA_SG_INTR_MASK (XDC_IXR_DMA_ERROR_MASK | \ - XDC_IXR_PKT_THRESHOLD_MASK | \ - XDC_IXR_PKT_WAIT_BOUND_MASK | \ - XDC_IXR_SG_END_MASK) - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ -/* -* -* Clears a structure of given size, in bytes, by setting each byte to 0. -* -* @param StructPtr is a pointer to the structure to be cleared. -* @param NumBytes is the number of bytes in the structure. -* -* @return -* -* None. -* -* @note -* -* Signature: void XEmac_mClearStruct(u8 *StructPtr, unsigned int NumBytes) -* -******************************************************************************/ -#define XEmac_mClearStruct(StructPtr, NumBytes) \ -{ \ - int i; \ - u8 *BytePtr = (u8 *)(StructPtr); \ - for (i=0; i < (unsigned int)(NumBytes); i++) \ - { \ - *BytePtr++ = 0; \ - } \ -} - -/************************** Variable Definitions *****************************/ - -extern XEmac_Config XEmac_ConfigTable[]; - -/************************** Function Prototypes ******************************/ - -void XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus); -void XEmac_CheckFifoRecvError(XEmac * InstancePtr); -void XEmac_CheckFifoSendError(XEmac * InstancePtr); - -#endif /* end of protection macro */ diff --git a/board/xilinx/xilinx_enet/xemac_intr.c b/board/xilinx/xilinx_enet/xemac_intr.c deleted file mode 100644 index b9a2621..0000000 --- a/board/xilinx/xilinx_enet/xemac_intr.c +++ /dev/null @@ -1,402 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemac_intr.c -* -* This file contains general interrupt-related functions of the XEmac driver. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rpm  07/31/01 First release
-* 1.00b rpm  02/20/02 Repartitioned files and functions
-* 1.00c rpm  12/05/02 New version includes support for simple DMA
-* 1.00c rpm  03/31/03 Added comment to indicate that no Receive Length FIFO
-*                     overrun interrupts occur in v1.00l and later of the EMAC
-*                     device. This avoids the need to reset the device on
-*                     receive overruns.
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xemac_i.h" -#include "xio.h" -#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */ - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* -* Set the callback function for handling asynchronous errors. The upper layer -* software should call this function during initialization. -* -* The error callback is invoked by the driver within interrupt context, so it -* needs to do its job quickly. If there are potentially slow operations within -* the callback, these should be done at task-level. -* -* The Xilinx errors that must be handled by the callback are: -* - XST_DMA_ERROR indicates an unrecoverable DMA error occurred. This is -* typically a bus error or bus timeout. The handler must reset and -* re-configure the device. -* - XST_FIFO_ERROR indicates an unrecoverable FIFO error occurred. This is a -* deadlock condition in the packet FIFO. The handler must reset and -* re-configure the device. -* - XST_RESET_ERROR indicates an unrecoverable MAC error occurred, usually an -* overrun or underrun. The handler must reset and re-configure the device. -* - XST_DMA_SG_NO_LIST indicates an attempt was made to access a scatter-gather -* DMA list that has not yet been created. -* - XST_DMA_SG_LIST_EMPTY indicates the driver tried to get a descriptor from -* the receive descriptor list, but the list was empty. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param CallBackRef is a reference pointer to be passed back to the adapter in -* the callback. This helps the adapter correlate the callback to a -* particular driver. -* @param FuncPtr is the pointer to the callback function. -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -void -XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef, - XEmac_ErrorHandler FuncPtr) -{ - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(FuncPtr != NULL); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - InstancePtr->ErrorHandler = FuncPtr; - InstancePtr->ErrorRef = CallBackRef; -} - -/****************************************************************************/ -/* -* -* Check the interrupt status bits of the Ethernet MAC for errors. Errors -* currently handled are: -* - Receive length FIFO overrun. Indicates data was lost due to the receive -* length FIFO becoming full during the reception of a packet. Only a device -* reset clears this condition. -* - Receive length FIFO underrun. An attempt to read an empty FIFO. Only a -* device reset clears this condition. -* - Transmit status FIFO overrun. Indicates data was lost due to the transmit -* status FIFO becoming full following the transmission of a packet. Only a -* device reset clears this condition. -* - Transmit status FIFO underrun. An attempt to read an empty FIFO. Only a -* device reset clears this condition. -* - Transmit length FIFO overrun. Indicates data was lost due to the transmit -* length FIFO becoming full following the transmission of a packet. Only a -* device reset clears this condition. -* - Transmit length FIFO underrun. An attempt to read an empty FIFO. Only a -* device reset clears this condition. -* - Receive data FIFO overrun. Indicates data was lost due to the receive data -* FIFO becoming full during the reception of a packet. -* - Receive data errors: -* - Receive missed frame error. Valid data was lost by the MAC. -* - Receive collision error. Data was lost by the MAC due to a collision. -* - Receive FCS error. Data was dicarded by the MAC due to FCS error. -* - Receive length field error. Data was dicarded by the MAC due to an invalid -* length field in the packet. -* - Receive short error. Data was dicarded by the MAC because a packet was -* shorter than allowed. -* - Receive long error. Data was dicarded by the MAC because a packet was -* longer than allowed. -* - Receive alignment error. Data was truncated by the MAC because its length -* was not byte-aligned. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param IntrStatus is the contents of the interrupt status register to be checked -* -* @return -* -* None. -* -* @note -* -* This function is intended for internal use only. -* -******************************************************************************/ -void -XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus) -{ - u32 ResetError = FALSE; - - /* - * First check for receive fifo overrun/underrun errors. Most require a - * reset by the user to clear, but the data FIFO overrun error does not. - */ - if (IntrStatus & XEM_EIR_RECV_DFIFO_OVER_MASK) { - InstancePtr->Stats.RecvOverrunErrors++; - InstancePtr->Stats.FifoErrors++; - } - - if (IntrStatus & XEM_EIR_RECV_LFIFO_OVER_MASK) { - /* - * Receive Length FIFO overrun interrupts no longer occur in v1.00l - * and later of the EMAC device. Frames are just dropped by the EMAC - * if the length FIFO is full. The user would notice the Receive Missed - * Frame count incrementing without any other errors being reported. - * This code is left here for backward compatibility with v1.00k and - * older EMAC devices. - */ - InstancePtr->Stats.RecvOverrunErrors++; - InstancePtr->Stats.FifoErrors++; - ResetError = TRUE; /* requires a reset */ - } - - if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) { - InstancePtr->Stats.RecvUnderrunErrors++; - InstancePtr->Stats.FifoErrors++; - ResetError = TRUE; /* requires a reset */ - } - - /* - * Now check for general receive errors. Get the latest count where - * available, otherwise just bump the statistic so we know the interrupt - * occurred. - */ - if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) { - if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) { - /* - * Caused by length FIFO or data FIFO overruns on receive side - */ - InstancePtr->Stats.RecvMissedFrameErrors = - XIo_In32(InstancePtr->BaseAddress + - XEM_RMFC_OFFSET); - } - - if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) { - InstancePtr->Stats.RecvCollisionErrors = - XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET); - } - - if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) { - InstancePtr->Stats.RecvFcsErrors = - XIo_In32(InstancePtr->BaseAddress + - XEM_RFCSEC_OFFSET); - } - - if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) { - InstancePtr->Stats.RecvLengthFieldErrors++; - } - - if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) { - InstancePtr->Stats.RecvShortErrors++; - } - - if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) { - InstancePtr->Stats.RecvLongErrors++; - } - - if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) { - InstancePtr->Stats.RecvAlignmentErrors = - XIo_In32(InstancePtr->BaseAddress + - XEM_RAEC_OFFSET); - } - - /* - * Bump recv interrupts stats only if not scatter-gather DMA (this - * stat gets bumped elsewhere in that case) - */ - if (!XEmac_mIsSgDma(InstancePtr)) { - InstancePtr->Stats.RecvInterrupts++; /* TODO: double bump? */ - } - - } - - /* - * Check for transmit errors. These apply to both DMA and non-DMA modes - * of operation. The entire device should be reset after overruns or - * underruns. - */ - if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | - XEM_EIR_XMIT_LFIFO_OVER_MASK)) { - InstancePtr->Stats.XmitOverrunErrors++; - InstancePtr->Stats.FifoErrors++; - ResetError = TRUE; - } - - if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | - XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { - InstancePtr->Stats.XmitUnderrunErrors++; - InstancePtr->Stats.FifoErrors++; - ResetError = TRUE; - } - - if (ResetError) { - /* - * If a reset error occurred, disable the EMAC interrupts since the - * reset-causing interrupt(s) is latched in the EMAC - meaning it will - * keep occurring until the device is reset. In order to give the higher - * layer software time to reset the device, we have to disable the - * overrun/underrun interrupts until that happens. We trust that the - * higher layer resets the device. We are able to get away with disabling - * all EMAC interrupts since the only interrupts it generates are for - * error conditions, and we don't care about any more errors right now. - */ - XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, 0); - - /* - * Invoke the error handler callback, which should result in a reset - * of the device by the upper layer software. - */ - InstancePtr->ErrorHandler(InstancePtr->ErrorRef, - XST_RESET_ERROR); - } -} - -/*****************************************************************************/ -/* -* -* Check the receive packet FIFO for errors. FIFO error interrupts are: -* - Deadlock. See the XPacketFifo component for a description of deadlock on a -* FIFO. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* Although the function returns void, it can return an asynchronous error to the -* application through the error handler. It can return XST_FIFO_ERROR if a FIFO -* error occurred. -* -* @note -* -* This function is intended for internal use only. -* -******************************************************************************/ -void -XEmac_CheckFifoRecvError(XEmac * InstancePtr) -{ - /* - * Although the deadlock is currently the only interrupt from a packet - * FIFO, make sure it is deadlocked before taking action. There is no - * need to clear this interrupt since it requires a reset of the device. - */ - if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) { - u32 IntrEnable; - - InstancePtr->Stats.FifoErrors++; - - /* - * Invoke the error callback function, which should result in a reset - * of the device by the upper layer software. We first need to disable - * the FIFO interrupt, since otherwise the upper layer thread that - * handles the reset may never run because this interrupt condition - * doesn't go away until a reset occurs (there is no way to ack it). - */ - IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress); - XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress, - IntrEnable & ~XEM_IPIF_RECV_FIFO_MASK); - - InstancePtr->ErrorHandler(InstancePtr->ErrorRef, - XST_FIFO_ERROR); - } -} - -/*****************************************************************************/ -/* -* -* Check the send packet FIFO for errors. FIFO error interrupts are: -* - Deadlock. See the XPacketFifo component for a description of deadlock on a -* FIFO. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* Although the function returns void, it can return an asynchronous error to the -* application through the error handler. It can return XST_FIFO_ERROR if a FIFO -* error occurred. -* -* @note -* -* This function is intended for internal use only. -* -******************************************************************************/ -void -XEmac_CheckFifoSendError(XEmac * InstancePtr) -{ - /* - * Although the deadlock is currently the only interrupt from a packet - * FIFO, make sure it is deadlocked before taking action. There is no - * need to clear this interrupt since it requires a reset of the device. - */ - if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) { - u32 IntrEnable; - - InstancePtr->Stats.FifoErrors++; - - /* - * Invoke the error callback function, which should result in a reset - * of the device by the upper layer software. We first need to disable - * the FIFO interrupt, since otherwise the upper layer thread that - * handles the reset may never run because this interrupt condition - * doesn't go away until a reset occurs (there is no way to ack it). - */ - IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress); - XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress, - IntrEnable & ~XEM_IPIF_SEND_FIFO_MASK); - - InstancePtr->ErrorHandler(InstancePtr->ErrorRef, - XST_FIFO_ERROR); - } -} diff --git a/board/xilinx/xilinx_enet/xemac_intr_dma.c b/board/xilinx/xilinx_enet/xemac_intr_dma.c deleted file mode 100644 index 567abb4..0000000 --- a/board/xilinx/xilinx_enet/xemac_intr_dma.c +++ /dev/null @@ -1,1344 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemac_intr_dma.c -* -* Contains functions used in interrupt mode when configured with scatter-gather -* DMA. -* -* The interrupt handler, XEmac_IntrHandlerDma(), must be connected by the user -* to the interrupt controller. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a rpm  07/31/01 First release
-* 1.00b rpm  02/20/02 Repartitioned files and functions
-* 1.00c rpm  12/05/02 New version includes support for simple DMA and the delay
-*                     argument to SgSend
-* 1.00c rpm  02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
-*                     from SetPktThreshold in the internal DMA driver. Also
-*                     avoided compiler warnings by initializing Result in the
-*                     interrupt service routines.
-* 1.00c rpm  03/26/03 Fixed a problem in the interrupt service routines where
-*                     the interrupt status was toggled clear after a call to
-*                     ErrorHandler, but if ErrorHandler reset the device the
-*                     toggle actually asserted the interrupt because the
-*                     reset had cleared it.
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xemac_i.h" -#include "xio.h" -#include "xbuf_descriptor.h" -#include "xdma_channel.h" -#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */ - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -static void HandleDmaRecvIntr(XEmac * InstancePtr); -static void HandleDmaSendIntr(XEmac * InstancePtr); -static void HandleEmacDmaIntr(XEmac * InstancePtr); - -/*****************************************************************************/ -/** -* -* Send an Ethernet frame using scatter-gather DMA. The caller attaches the -* frame to one or more buffer descriptors, then calls this function once for -* each descriptor. The caller is responsible for allocating and setting up the -* descriptor. An entire Ethernet frame may or may not be contained within one -* descriptor. This function simply inserts the descriptor into the scatter- -* gather engine's transmit list. The caller is responsible for providing mutual -* exclusion to guarantee that a frame is contiguous in the transmit list. The -* buffer attached to the descriptor must be word-aligned. -* -* The driver updates the descriptor with the device control register before -* being inserted into the transmit list. If this is the last descriptor in -* the frame, the inserts are committed, which means the descriptors for this -* frame are now available for transmission. -* -* It is assumed that the upper layer software supplies a correctly formatted -* Ethernet frame, including the destination and source addresses, the -* type/length field, and the data field. It is also assumed that upper layer -* software does not append FCS at the end of the frame. -* -* The buffer attached to the descriptor must be word-aligned on the front end. -* -* This call is non-blocking. Notification of error or successful transmission -* is done asynchronously through the send or error callback function. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param BdPtr is the address of a descriptor to be inserted into the transmit -* ring. -* @param Delay indicates whether to start the scatter-gather DMA channel -* immediately, or whether to wait. This allows the user to build up a -* list of more than one descriptor before starting the transmission of -* the packets, which allows the application to keep up with DMA and have -* a constant stream of frames being transmitted. Use XEM_SGDMA_NODELAY or -* XEM_SGDMA_DELAY, defined in xemac.h, as the value of this argument. If -* the user chooses to delay and build a list, the user must call this -* function with the XEM_SGDMA_NODELAY option or call XEmac_Start() to -* kick off the tranmissions. -* -* @return -* -* - XST_SUCCESS if the buffer was successfull sent -* - XST_DEVICE_IS_STOPPED if the Ethernet MAC has not been started yet -* - XST_NOT_SGDMA if the device is not in scatter-gather DMA mode -* - XST_DMA_SG_LIST_FULL if the descriptor list for the DMA channel is full -* - XST_DMA_SG_BD_LOCKED if the DMA channel cannot insert the descriptor into -* the list because a locked descriptor exists at the insert point -* - XST_DMA_SG_NOTHING_TO_COMMIT if even after inserting a descriptor into the -* list, the DMA channel believes there are no new descriptors to commit. If -* this is ever encountered, there is likely a thread mutual exclusion problem -* on transmit. -* -* @note -* -* This function is not thread-safe. The user must provide mutually exclusive -* access to this function if there are to be multiple threads that can call it. -* -* @internal -* -* A status that should never be returned from this function, although -* the code is set up to handle it, is XST_DMA_SG_NO_LIST. Starting the device -* requires a list to be created, and this function requires the device to be -* started. -* -******************************************************************************/ -XStatus -XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay) -{ - XStatus Result; - u32 BdControl; - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(BdPtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * Be sure the device is configured for scatter-gather DMA, then be sure - * it is started. - */ - if (!XEmac_mIsSgDma(InstancePtr)) { - return XST_NOT_SGDMA; - } - - /* - * Set some descriptor control word defaults (source address increment - * and local destination address) and the destination address - * (the FIFO). These are the same for every transmit descriptor. - */ - BdControl = XBufDescriptor_GetControl(BdPtr); - XBufDescriptor_SetControl(BdPtr, BdControl | XEM_DFT_SEND_BD_MASK); - - XBufDescriptor_SetDestAddress(BdPtr, - InstancePtr->BaseAddress + - XEM_PFIFO_TXDATA_OFFSET); - - /* - * Put the descriptor in the send list. The DMA component accesses data - * here that can also be modified in interrupt context, so a critical - * section is required. - */ - XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress); - - Result = XDmaChannel_PutDescriptor(&InstancePtr->SendChannel, BdPtr); - if (Result != XST_SUCCESS) { - XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); - return Result; - } - - /* - * If this is the last buffer in the frame, commit the inserts and start - * the DMA engine if necessary - */ - if (XBufDescriptor_IsLastControl(BdPtr)) { - Result = XDmaChannel_CommitPuts(&InstancePtr->SendChannel); - if (Result != XST_SUCCESS) { - XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); - return Result; - } - - if (Delay == XEM_SGDMA_NODELAY) { - /* - * Start the DMA channel. Ignore the return status since we know the - * list exists and has at least one entry and we don't care if the - * channel is already started. The DMA component accesses data here - * that can be modified at interrupt or task levels, so a critical - * section is required. - */ - (void) XDmaChannel_SgStart(&InstancePtr->SendChannel); - } - } - - XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Add a descriptor, with an attached empty buffer, into the receive descriptor -* list. The buffer attached to the descriptor must be word-aligned. This is -* used by the upper layer software during initialization when first setting up -* the receive descriptors, and also during reception of frames to replace -* filled buffers with empty buffers. This function can be called when the -* device is started or stopped. Note that it does start the scatter-gather DMA -* engine. Although this is not necessary during initialization, it is not a -* problem during initialization because the MAC receiver is not yet started. -* -* The buffer attached to the descriptor must be word-aligned on both the front -* end and the back end. -* -* Notification of received frames are done asynchronously through the receive -* callback function. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param BdPtr is a pointer to the buffer descriptor that will be added to the -* descriptor list. -* -* @return -* -* - XST_SUCCESS if a descriptor was successfully returned to the driver -* - XST_NOT_SGDMA if the device is not in scatter-gather DMA mode -* - XST_DMA_SG_LIST_FULL if the receive descriptor list is full -* - XST_DMA_SG_BD_LOCKED if the DMA channel cannot insert the descriptor into -* the list because a locked descriptor exists at the insert point. -* - XST_DMA_SG_NOTHING_TO_COMMIT if even after inserting a descriptor into the -* list, the DMA channel believes there are no new descriptors to commit. -* -* @internal -* -* A status that should never be returned from this function, although -* the code is set up to handle it, is XST_DMA_SG_NO_LIST. Starting the device -* requires a list to be created, and this function requires the device to be -* started. -* -******************************************************************************/ -XStatus -XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr) -{ - XStatus Result; - u32 BdControl; - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(BdPtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * Be sure the device is configured for scatter-gather DMA - */ - if (!XEmac_mIsSgDma(InstancePtr)) { - return XST_NOT_SGDMA; - } - - /* - * Set some descriptor control word defaults (destination address increment - * and local source address) and the source address (the FIFO). These are - * the same for every receive descriptor. - */ - BdControl = XBufDescriptor_GetControl(BdPtr); - XBufDescriptor_SetControl(BdPtr, BdControl | XEM_DFT_RECV_BD_MASK); - XBufDescriptor_SetSrcAddress(BdPtr, - InstancePtr->BaseAddress + - XEM_PFIFO_RXDATA_OFFSET); - - /* - * Put the descriptor into the channel's descriptor list and commit. - * Although this function is likely called within interrupt context, there - * is the possibility that the upper layer software queues it to a task. - * In this case, a critical section is needed here to protect shared data - * in the DMA component. - */ - XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress); - - Result = XDmaChannel_PutDescriptor(&InstancePtr->RecvChannel, BdPtr); - if (Result != XST_SUCCESS) { - XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); - return Result; - } - - Result = XDmaChannel_CommitPuts(&InstancePtr->RecvChannel); - if (Result != XST_SUCCESS) { - XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); - return Result; - } - - /* - * Start the DMA channel. Ignore the return status since we know the list - * exists and has at least one entry and we don't care if the channel is - * already started. The DMA component accesses data here that can be - * modified at interrupt or task levels, so a critical section is required. - */ - (void) XDmaChannel_SgStart(&InstancePtr->RecvChannel); - - XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* The interrupt handler for the Ethernet driver when configured with scatter- -* gather DMA. -* -* Get the interrupt status from the IpIf to determine the source of the -* interrupt. The source can be: MAC, Recv Packet FIFO, Send Packet FIFO, Recv -* DMA channel, or Send DMA channel. The packet FIFOs only interrupt during -* "deadlock" conditions. -* -* @param InstancePtr is a pointer to the XEmac instance that just interrupted. -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -void -XEmac_IntrHandlerDma(void *InstancePtr) -{ - u32 IntrStatus; - XEmac *EmacPtr = (XEmac *) InstancePtr; - - EmacPtr->Stats.TotalIntrs++; - - /* - * Get the interrupt status from the IPIF. There is no clearing of - * interrupts in the IPIF. Interrupts must be cleared at the source. - */ - IntrStatus = XIIF_V123B_READ_DIPR(EmacPtr->BaseAddress); - - /* - * See which type of interrupt is being requested, and service it - */ - if (IntrStatus & XEM_IPIF_RECV_DMA_MASK) { /* Receive DMA interrupt */ - EmacPtr->Stats.RecvInterrupts++; - HandleDmaRecvIntr(EmacPtr); - } - - if (IntrStatus & XEM_IPIF_SEND_DMA_MASK) { /* Send DMA interrupt */ - EmacPtr->Stats.XmitInterrupts++; - HandleDmaSendIntr(EmacPtr); - } - - if (IntrStatus & XEM_IPIF_EMAC_MASK) { /* MAC interrupt */ - EmacPtr->Stats.EmacInterrupts++; - HandleEmacDmaIntr(EmacPtr); - } - - if (IntrStatus & XEM_IPIF_RECV_FIFO_MASK) { /* Receive FIFO interrupt */ - EmacPtr->Stats.RecvInterrupts++; - XEmac_CheckFifoRecvError(EmacPtr); - } - - if (IntrStatus & XEM_IPIF_SEND_FIFO_MASK) { /* Send FIFO interrupt */ - EmacPtr->Stats.XmitInterrupts++; - XEmac_CheckFifoSendError(EmacPtr); - } - - if (IntrStatus & XIIF_V123B_ERROR_MASK) { - /* - * An error occurred internal to the IPIF. This is more of a debug and - * integration issue rather than a production error. Don't do anything - * other than clear it, which provides a spot for software to trap - * on the interrupt and begin debugging. - */ - XIIF_V123B_WRITE_DISR(EmacPtr->BaseAddress, - XIIF_V123B_ERROR_MASK); - } -} - -/*****************************************************************************/ -/** -* -* Set the packet count threshold for this device. The device must be stopped -* before setting the threshold. The packet count threshold is used for interrupt -* coalescing, which reduces the frequency of interrupts from the device to the -* processor. In this case, the scatter-gather DMA engine only interrupts when -* the packet count threshold is reached, instead of interrupting for each packet. -* A packet is a generic term used by the scatter-gather DMA engine, and is -* equivalent to an Ethernet frame in our case. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param Direction indicates the channel, send or receive, from which the -* threshold register is read. -* @param Threshold is the value of the packet threshold count used during -* interrupt coalescing. A value of 0 disables the use of packet threshold -* by the hardware. -* -* @return -* -* - XST_SUCCESS if the threshold was successfully set -* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA -* - XST_DEVICE_IS_STARTED if the device has not been stopped -* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on -* asserts would also catch this error. -* -* @note -* -* The packet threshold could be set to larger than the number of descriptors -* allocated to the DMA channel. In this case, the wait bound will take over -* and always indicate data arrival. There was a check in this function that -* returned an error if the treshold was larger than the number of descriptors, -* but that was removed because users would then have to set the threshold -* only after they set descriptor space, which is an order dependency that -* caused confustion. -* -******************************************************************************/ -XStatus -XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold) -{ - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * Be sure device is configured for scatter-gather DMA and has been stopped - */ - if (!XEmac_mIsSgDma(InstancePtr)) { - return XST_NOT_SGDMA; - } - - if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; - } - - /* - * Based on the direction, set the packet threshold in the - * corresponding DMA channel component. Default to the receive - * channel threshold register (if an invalid Direction is passed). - */ - switch (Direction) { - case XEM_SEND: - return XDmaChannel_SetPktThreshold(&InstancePtr->SendChannel, - Threshold); - - case XEM_RECV: - return XDmaChannel_SetPktThreshold(&InstancePtr->RecvChannel, - Threshold); - - default: - return XST_INVALID_PARAM; - } -} - -/*****************************************************************************/ -/** -* -* Get the value of the packet count threshold for this driver/device. The packet -* count threshold is used for interrupt coalescing, which reduces the frequency -* of interrupts from the device to the processor. In this case, the -* scatter-gather DMA engine only interrupts when the packet count threshold is -* reached, instead of interrupting for each packet. A packet is a generic term -* used by the scatter-gather DMA engine, and is equivalent to an Ethernet frame -* in our case. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param Direction indicates the channel, send or receive, from which the -* threshold register is read. -* @param ThreshPtr is a pointer to the byte into which the current value of the -* packet threshold register will be copied. An output parameter. A value -* of 0 indicates the use of packet threshold by the hardware is disabled. -* -* @return -* -* - XST_SUCCESS if the packet threshold was retrieved successfully -* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA -* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on -* asserts would also catch this error. -* -* @note -* -* None. -* -******************************************************************************/ -XStatus -XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 * ThreshPtr) -{ - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV); - XASSERT_NONVOID(ThreshPtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - if (!XEmac_mIsSgDma(InstancePtr)) { - return XST_NOT_SGDMA; - } - - /* - * Based on the direction, return the packet threshold set in the - * corresponding DMA channel component. Default to the value in - * the receive channel threshold register (if an invalid Direction - * is passed). - */ - switch (Direction) { - case XEM_SEND: - *ThreshPtr = - XDmaChannel_GetPktThreshold(&InstancePtr->SendChannel); - break; - - case XEM_RECV: - *ThreshPtr = - XDmaChannel_GetPktThreshold(&InstancePtr->RecvChannel); - break; - - default: - return XST_INVALID_PARAM; - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Set the packet wait bound timer for this driver/device. The device must be -* stopped before setting the timer value. The packet wait bound is used during -* interrupt coalescing to trigger an interrupt when not enough packets have been -* received to reach the packet count threshold. A packet is a generic term used -* by the scatter-gather DMA engine, and is equivalent to an Ethernet frame in -* our case. The timer is in milliseconds. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param Direction indicates the channel, send or receive, from which the -* threshold register is read. -* @param TimerValue is the value of the packet wait bound used during interrupt -* coalescing. It is in milliseconds in the range 0 - 1023. A value of 0 -* disables the packet wait bound timer. -* -* @return -* -* - XST_SUCCESS if the packet wait bound was set successfully -* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA -* - XST_DEVICE_IS_STARTED if the device has not been stopped -* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on -* asserts would also catch this error. -* -* @note -* -* None. -* -******************************************************************************/ -XStatus -XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction, u32 TimerValue) -{ - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV); - XASSERT_NONVOID(TimerValue <= XEM_SGDMA_MAX_WAITBOUND); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * Be sure device is configured for scatter-gather DMA and has been stopped - */ - if (!XEmac_mIsSgDma(InstancePtr)) { - return XST_NOT_SGDMA; - } - - if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; - } - - /* - * Based on the direction, set the packet wait bound in the - * corresponding DMA channel component. Default to the receive - * channel wait bound register (if an invalid Direction is passed). - */ - switch (Direction) { - case XEM_SEND: - XDmaChannel_SetPktWaitBound(&InstancePtr->SendChannel, - TimerValue); - break; - - case XEM_RECV: - XDmaChannel_SetPktWaitBound(&InstancePtr->RecvChannel, - TimerValue); - break; - - default: - return XST_INVALID_PARAM; - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Get the packet wait bound timer for this driver/device. The packet wait bound -* is used during interrupt coalescing to trigger an interrupt when not enough -* packets have been received to reach the packet count threshold. A packet is a -* generic term used by the scatter-gather DMA engine, and is equivalent to an -* Ethernet frame in our case. The timer is in milliseconds. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param Direction indicates the channel, send or receive, from which the -* threshold register is read. -* @param WaitPtr is a pointer to the byte into which the current value of the -* packet wait bound register will be copied. An output parameter. Units -* are in milliseconds in the range 0 - 1023. A value of 0 indicates the -* packet wait bound timer is disabled. -* -* @return -* -* - XST_SUCCESS if the packet wait bound was retrieved successfully -* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA -* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on -* asserts would also catch this error. -* -* @note -* -* None. -* -******************************************************************************/ -XStatus -XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction, u32 * WaitPtr) -{ - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV); - XASSERT_NONVOID(WaitPtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - if (!XEmac_mIsSgDma(InstancePtr)) { - return XST_NOT_SGDMA; - } - - /* - * Based on the direction, return the packet wait bound set in the - * corresponding DMA channel component. Default to the value in - * the receive channel wait bound register (if an invalid Direction - * is passed). - */ - switch (Direction) { - case XEM_SEND: - *WaitPtr = - XDmaChannel_GetPktWaitBound(&InstancePtr->SendChannel); - break; - - case XEM_RECV: - *WaitPtr = - XDmaChannel_GetPktWaitBound(&InstancePtr->RecvChannel); - break; - - default: - return XST_INVALID_PARAM; - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Give the driver the memory space to be used for the scatter-gather DMA -* receive descriptor list. This function should only be called once, during -* initialization of the Ethernet driver. The memory space must be big enough -* to hold some number of descriptors, depending on the needs of the system. -* The xemac.h file defines minimum and default numbers of descriptors -* which can be used to allocate this memory space. -* -* The memory space must be word-aligned. An assert will occur if asserts are -* turned on and the memory is not word-aligned. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param MemoryPtr is a pointer to the word-aligned memory. -* @param ByteCount is the length, in bytes, of the memory space. -* -* @return -* -* - XST_SUCCESS if the space was initialized successfully -* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA -* - XST_DMA_SG_LIST_EXISTS if this list space has already been created -* -* @note -* -* If the device is configured for scatter-gather DMA, this function must be -* called AFTER the XEmac_Initialize() function because the DMA channel -* components must be initialized before the memory space is set. -* -******************************************************************************/ -XStatus -XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr, u32 ByteCount) -{ - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(MemoryPtr != NULL); - XASSERT_NONVOID(ByteCount != 0); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - if (!XEmac_mIsSgDma(InstancePtr)) { - return XST_NOT_SGDMA; - } - - return XDmaChannel_CreateSgList(&InstancePtr->RecvChannel, MemoryPtr, - ByteCount); -} - -/*****************************************************************************/ -/** -* -* Give the driver the memory space to be used for the scatter-gather DMA -* transmit descriptor list. This function should only be called once, during -* initialization of the Ethernet driver. The memory space must be big enough -* to hold some number of descriptors, depending on the needs of the system. -* The xemac.h file defines minimum and default numbers of descriptors -* which can be used to allocate this memory space. -* -* The memory space must be word-aligned. An assert will occur if asserts are -* turned on and the memory is not word-aligned. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param MemoryPtr is a pointer to the word-aligned memory. -* @param ByteCount is the length, in bytes, of the memory space. -* -* @return -* -* - XST_SUCCESS if the space was initialized successfully -* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA -* - XST_DMA_SG_LIST_EXISTS if this list space has already been created -* -* @note -* -* If the device is configured for scatter-gather DMA, this function must be -* called AFTER the XEmac_Initialize() function because the DMA channel -* components must be initialized before the memory space is set. -* -******************************************************************************/ -XStatus -XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr, u32 ByteCount) -{ - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(MemoryPtr != NULL); - XASSERT_NONVOID(ByteCount != 0); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - if (!XEmac_mIsSgDma(InstancePtr)) { - return XST_NOT_SGDMA; - } - - return XDmaChannel_CreateSgList(&InstancePtr->SendChannel, MemoryPtr, - ByteCount); -} - -/*****************************************************************************/ -/** -* -* Set the callback function for handling received frames in scatter-gather DMA -* mode. The upper layer software should call this function during -* initialization. The callback is called once per frame received. The head of -* a descriptor list is passed in along with the number of descriptors in the -* list. Before leaving the callback, the upper layer software should attach a -* new buffer to each descriptor in the list. -* -* The callback is invoked by the driver within interrupt context, so it needs -* to do its job quickly. Sending the received frame up the protocol stack -* should be done at task-level. If there are other potentially slow operations -* within the callback, these too should be done at task-level. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param CallBackRef is a reference pointer to be passed back to the adapter in -* the callback. This helps the adapter correlate the callback to a -* particular driver. -* @param FuncPtr is the pointer to the callback function. -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -void -XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef, - XEmac_SgHandler FuncPtr) -{ - /* - * Asserted IsDmaSg here instead of run-time check because there is really - * no ill-effects of setting these when not configured for scatter-gather. - */ - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(FuncPtr != NULL); - XASSERT_VOID(XEmac_mIsSgDma(InstancePtr)); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - InstancePtr->SgRecvHandler = FuncPtr; - InstancePtr->SgRecvRef = CallBackRef; -} - -/*****************************************************************************/ -/** -* -* Set the callback function for handling confirmation of transmitted frames in -* scatter-gather DMA mode. The upper layer software should call this function -* during initialization. The callback is called once per frame sent. The head -* of a descriptor list is passed in along with the number of descriptors in -* the list. The callback is responsible for freeing buffers attached to these -* descriptors. -* -* The callback is invoked by the driver within interrupt context, so it needs -* to do its job quickly. If there are potentially slow operations within the -* callback, these should be done at task-level. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param CallBackRef is a reference pointer to be passed back to the adapter in -* the callback. This helps the adapter correlate the callback to a -* particular driver. -* @param FuncPtr is the pointer to the callback function. -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -void -XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef, - XEmac_SgHandler FuncPtr) -{ - /* - * Asserted IsDmaSg here instead of run-time check because there is really - * no ill-effects of setting these when not configured for scatter-gather. - */ - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(FuncPtr != NULL); - XASSERT_VOID(XEmac_mIsSgDma(InstancePtr)); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - InstancePtr->SgSendHandler = FuncPtr; - InstancePtr->SgSendRef = CallBackRef; -} - -/*****************************************************************************/ -/* -* -* Handle an interrupt from the DMA receive channel. DMA interrupts are: -* -* - DMA error. DMA encountered a bus error or timeout. This is a fatal error -* that requires reset of the channel. The driver calls the error handler -* of the upper layer software with an error code indicating the device should -* be reset. -* - Packet count threshold reached. For scatter-gather operations, indicates -* the threshold for the number of packets not serviced by software has been -* reached. The driver behaves as follows: -* - Get the value of the packet counter, which tells us how many packets -* are ready to be serviced -* - For each packet -* - For each descriptor, remove it from the scatter-gather list -* - Check for the last descriptor in the frame, and if set -* - Bump frame statistics -* - Call the scatter-gather receive callback function -* - Decrement the packet counter by one -* Note that there are no receive errors reported in the status word of -* the buffer descriptor. If receive errors occur, the MAC drops the -* packet, and we only find out about the errors through various error -* count registers. -* - Packet wait bound reached. For scatter-gather, indicates the time to wait -* for the next packet has expired. The driver follows the same logic as when -* the packet count threshold interrupt is received. -* - Scatter-gather end acknowledge. Hardware has reached the end of the -* descriptor list. The driver follows the same logic as when the packet count -* threshold interrupt is received. In addition, the driver restarts the DMA -* scatter-gather channel in case there are newly inserted descriptors. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* Although the function returns void, there are asynchronous errors that can -* be generated (by calling the ErrorHandler) from this function. These are: -* - XST_DMA_SG_LIST_EMPTY indicates we tried to get a buffer descriptor from the -* DMA channel, but there was not one ready for software. -* - XST_DMA_ERROR indicates a DMA bus error or timeout occurred. This is a fatal -* error that requires reset. -* -* @note -* -* None. -* -******************************************************************************/ -static void -HandleDmaRecvIntr(XEmac * InstancePtr) -{ - u32 IntrStatus; - - /* - * Read the interrupt status - */ - IntrStatus = XDmaChannel_GetIntrStatus(&InstancePtr->RecvChannel); - - /* - * For packet threshold or wait bound interrupts, process desciptors. Also - * process descriptors on a SG end acknowledgement, which means the end of - * the descriptor list has been reached by the hardware. For receive, this - * is potentially trouble since it means the descriptor list is full, - * unless software can process enough packets quickly enough so the - * hardware has room to put new packets. - */ - if (IntrStatus & (XDC_IXR_PKT_THRESHOLD_MASK | - XDC_IXR_PKT_WAIT_BOUND_MASK | XDC_IXR_SG_END_MASK)) { - XStatus Result = XST_SUCCESS; - u32 NumFrames; - u32 NumProcessed; - u32 NumBuffers; - u32 NumBytes; - u32 IsLast; - XBufDescriptor *FirstBdPtr; - XBufDescriptor *BdPtr; - - /* - * Get the number of unserviced packets - */ - NumFrames = XDmaChannel_GetPktCount(&InstancePtr->RecvChannel); - - for (NumProcessed = 0; NumProcessed < NumFrames; NumProcessed++) { - IsLast = FALSE; - FirstBdPtr = NULL; - NumBuffers = 0; - NumBytes = 0; - - /* - * For each packet, get the descriptor from the list. On the - * last one in the frame, make the callback to the upper layer. - */ - while (!IsLast) { - Result = - XDmaChannel_GetDescriptor(&InstancePtr-> - RecvChannel, - &BdPtr); - if (Result != XST_SUCCESS) { - /* - * An error getting a buffer descriptor from the list. - * This should not happen, but if it does, report it to - * the error callback and break out of the loops to service - * other interrupts. - */ - InstancePtr->ErrorHandler(InstancePtr-> - ErrorRef, - Result); - break; - } - - /* - * Keep a pointer to the first descriptor in the list, as it - * will be passed to the upper layers in a bit. By the fact - * that we received this packet means no errors occurred, so - * no need to check the device status word for errors. - */ - if (FirstBdPtr == NULL) { - FirstBdPtr = BdPtr; - } - - NumBytes += XBufDescriptor_GetLength(BdPtr); - - /* - * Check to see if this is the last descriptor in the frame, - * and if so, set the IsLast flag to get out of the loop. - */ - if (XBufDescriptor_IsLastStatus(BdPtr)) { - IsLast = TRUE; - } - - /* - * Bump the number of buffers in this packet - */ - NumBuffers++; - - } /* end while loop */ - - /* - * Check for error that occurred inside the while loop, and break - * out of the for loop if there was one so other interrupts can - * be serviced. - */ - if (Result != XST_SUCCESS) { - break; - } - - InstancePtr->Stats.RecvFrames++; - InstancePtr->Stats.RecvBytes += NumBytes; - - /* - * Make the callback to the upper layers, passing it the first - * descriptor in the packet and the number of descriptors in the - * packet. - */ - InstancePtr->SgRecvHandler(InstancePtr->SgRecvRef, - FirstBdPtr, NumBuffers); - - /* - * Decrement the packet count register to reflect the fact we - * just processed a packet - */ - XDmaChannel_DecrementPktCount(&InstancePtr-> - RecvChannel); - - } /* end for loop */ - - /* - * If the interrupt was an end-ack, check the descriptor list again to - * see if it is empty. If not, go ahead and restart the scatter-gather - * channel. This is to fix a possible race condition where, on receive, - * the driver attempted to start a scatter-gather channel that was - * already started, which resulted in no action from the XDmaChannel - * component. But, just after the XDmaChannel component saw that the - * hardware was already started, the hardware stopped because it - * reached the end of the list. In that case, this interrupt is - * generated and we can restart the hardware here. - */ - if (IntrStatus & XDC_IXR_SG_END_MASK) { - /* - * Ignore the return status since we know the list exists and we - * don't care if the list is empty or the channel is already started. - */ - (void) XDmaChannel_SgStart(&InstancePtr->RecvChannel); - } - } - - /* - * All interrupts are handled (except the error below) so acknowledge - * (clear) the interrupts by writing the value read above back to the status - * register. The packet count interrupt must be acknowledged after the - * decrement, otherwise it will come right back. We clear the interrupts - * before we handle the error interrupt because the ErrorHandler should - * result in a reset, which clears the interrupt status register. So we - * don't want to toggle the interrupt back on by writing the interrupt - * status register with an old value after a reset. - */ - XDmaChannel_SetIntrStatus(&InstancePtr->RecvChannel, IntrStatus); - - /* - * Check for DMA errors and call the error callback function if an error - * occurred (DMA bus or timeout error), which should result in a reset of - * the device by the upper layer software. - */ - if (IntrStatus & XDC_IXR_DMA_ERROR_MASK) { - InstancePtr->Stats.DmaErrors++; - InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XST_DMA_ERROR); - } -} - -/*****************************************************************************/ -/* -* -* Handle an interrupt from the DMA send channel. DMA interrupts are: -* -* - DMA error. DMA encountered a bus error or timeout. This is a fatal error -* that requires reset of the channel. The driver calls the error handler -* of the upper layer software with an error code indicating the device should -* be reset. -* - Packet count threshold reached. For scatter-gather operations, indicates -* the threshold for the number of packets not serviced by software has been -* reached. The driver behaves as follows: -* - Get the value of the packet counter, which tells us how many packets -* are ready to be serviced -* - For each packet -* - For each descriptor, remove it from the scatter-gather list -* - Check for the last descriptor in the frame, and if set -* - Bump frame statistics -* - Call the scatter-gather receive callback function -* - Decrement the packet counter by one -* Note that there are no receive errors reported in the status word of -* the buffer descriptor. If receive errors occur, the MAC drops the -* packet, and we only find out about the errors through various error -* count registers. -* - Packet wait bound reached. For scatter-gather, indicates the time to wait -* for the next packet has expired. The driver follows the same logic as when -* the packet count threshold interrupt is received. -* - Scatter-gather end acknowledge. Hardware has reached the end of the -* descriptor list. The driver follows the same logic as when the packet count -* threshold interrupt is received. In addition, the driver restarts the DMA -* scatter-gather channel in case there are newly inserted descriptors. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* Although the function returns void, there are asynchronous errors -* that can be generated from this function. These are: -* - XST_DMA_SG_LIST_EMPTY indicates we tried to get a buffer descriptor from -* the DMA channel, but there was not one ready for software. -* - XST_DMA_ERROR indicates a DMA bus error or timeout occurred. This is a -* fatal error that requires reset. -* -* @note -* -* None. -* -******************************************************************************/ -static void -HandleDmaSendIntr(XEmac * InstancePtr) -{ - u32 IntrStatus; - - /* - * Read the interrupt status - */ - IntrStatus = XDmaChannel_GetIntrStatus(&InstancePtr->SendChannel); - - /* - * For packet threshold or wait bound interrupt, process descriptors. Also - * process descriptors on a SG end acknowledgement, which means the end of - * the descriptor list has been reached by the hardware. For transmit, - * this is a normal condition during times of light traffic. In fact, the - * wait bound interrupt may be masked for transmit since the end-ack would - * always occur before the wait bound expires. - */ - if (IntrStatus & (XDC_IXR_PKT_THRESHOLD_MASK | - XDC_IXR_PKT_WAIT_BOUND_MASK | XDC_IXR_SG_END_MASK)) { - XStatus Result = XST_SUCCESS; - u32 NumFrames; - u32 NumProcessed; - u32 NumBuffers; - u32 NumBytes; - u32 IsLast; - XBufDescriptor *FirstBdPtr; - XBufDescriptor *BdPtr; - - /* - * Get the number of unserviced packets - */ - NumFrames = XDmaChannel_GetPktCount(&InstancePtr->SendChannel); - - for (NumProcessed = 0; NumProcessed < NumFrames; NumProcessed++) { - IsLast = FALSE; - FirstBdPtr = NULL; - NumBuffers = 0; - NumBytes = 0; - - /* - * For each frame, traverse the descriptor list and look for - * errors. On the last one in the frame, make the callback. - */ - while (!IsLast) { - Result = - XDmaChannel_GetDescriptor(&InstancePtr-> - SendChannel, - &BdPtr); - if (Result != XST_SUCCESS) { - /* - * An error getting a buffer descriptor from the list. - * This should not happen, but if it does, report it to - * the error callback and break out of the loops to service - * other interrupts - */ - InstancePtr->ErrorHandler(InstancePtr-> - ErrorRef, - Result); - break; - } - - /* - * Keep a pointer to the first descriptor in the list and - * check the device status for errors. The device status is - * only available in the first descriptor of a packet. - */ - if (FirstBdPtr == NULL) { - u32 XmitStatus; - - FirstBdPtr = BdPtr; - - XmitStatus = - XBufDescriptor_GetDeviceStatus - (BdPtr); - if (XmitStatus & - XEM_TSR_EXCESS_DEFERRAL_MASK) { - InstancePtr->Stats. - XmitExcessDeferral++; - } - - if (XmitStatus & - XEM_TSR_LATE_COLLISION_MASK) { - InstancePtr->Stats. - XmitLateCollisionErrors++; - } - } - - NumBytes += XBufDescriptor_GetLength(BdPtr); - - /* - * Check to see if this is the last descriptor in the frame, - * and if so, set the IsLast flag to get out of the loop. The - * transmit channel must check the last bit in the control - * word, not the status word (the DMA engine does not update - * the last bit in the status word for the transmit direction). - */ - if (XBufDescriptor_IsLastControl(BdPtr)) { - IsLast = TRUE; - } - - /* - * Bump the number of buffers in this packet - */ - NumBuffers++; - - } /* end while loop */ - - /* - * Check for error that occurred inside the while loop, and break - * out of the for loop if there was one so other interrupts can - * be serviced. - */ - if (Result != XST_SUCCESS) { - break; - } - - InstancePtr->Stats.XmitFrames++; - InstancePtr->Stats.XmitBytes += NumBytes; - - /* - * Make the callback to the upper layers, passing it the first - * descriptor in the packet and the number of descriptors in the - * packet. - */ - InstancePtr->SgSendHandler(InstancePtr->SgSendRef, - FirstBdPtr, NumBuffers); - - /* - * Decrement the packet count register to reflect the fact we - * just processed a packet - */ - XDmaChannel_DecrementPktCount(&InstancePtr-> - SendChannel); - - } /* end for loop */ - - /* - * If the interrupt was an end-ack, check the descriptor list again to - * see if it is empty. If not, go ahead and restart the scatter-gather - * channel. This is to fix a possible race condition where, on transmit, - * the driver attempted to start a scatter-gather channel that was - * already started, which resulted in no action from the XDmaChannel - * component. But, just after the XDmaChannel component saw that the - * hardware was already started, the hardware stopped because it - * reached the end of the list. In that case, this interrupt is - * generated and we can restart the hardware here. - */ - if (IntrStatus & XDC_IXR_SG_END_MASK) { - /* - * Ignore the return status since we know the list exists and we - * don't care if the list is empty or the channel is already started. - */ - (void) XDmaChannel_SgStart(&InstancePtr->SendChannel); - } - } - - /* - * All interrupts are handled (except the error below) so acknowledge - * (clear) the interrupts by writing the value read above back to the status - * register. The packet count interrupt must be acknowledged after the - * decrement, otherwise it will come right back. We clear the interrupts - * before we handle the error interrupt because the ErrorHandler should - * result in a reset, which clears the interrupt status register. So we - * don't want to toggle the interrupt back on by writing the interrupt - * status register with an old value after a reset. - */ - XDmaChannel_SetIntrStatus(&InstancePtr->SendChannel, IntrStatus); - - /* - * Check for DMA errors and call the error callback function if an error - * occurred (DMA bus or timeout error), which should result in a reset of - * the device by the upper layer software. - */ - if (IntrStatus & XDC_IXR_DMA_ERROR_MASK) { - InstancePtr->Stats.DmaErrors++; - InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XST_DMA_ERROR); - } -} - -/*****************************************************************************/ -/* -* -* Handle an interrupt from the Ethernet MAC when configured with scatter-gather -* DMA. The only interrupts handled in this case are errors. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* None. -* -* @note -* -* None. -* -******************************************************************************/ -static void -HandleEmacDmaIntr(XEmac * InstancePtr) -{ - u32 IntrStatus; - - /* - * When configured with DMA, the EMAC generates interrupts only when errors - * occur. We clear the interrupts immediately so that any latched status - * interrupt bits will reflect the true status of the device, and so any - * pulsed interrupts (non-status) generated during the Isr will not be lost. - */ - IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); - XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, IntrStatus); - - /* - * Check the MAC for errors - */ - XEmac_CheckEmacError(InstancePtr, IntrStatus); -} diff --git a/board/xilinx/xilinx_enet/xemac_l.h b/board/xilinx/xilinx_enet/xemac_l.h deleted file mode 100644 index a463937..0000000 --- a/board/xilinx/xilinx_enet/xemac_l.h +++ /dev/null @@ -1,462 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemac_l.h -* -* This header file contains identifiers and low-level driver functions (or -* macros) that can be used to access the device. High-level driver functions -* are defined in xemac.h. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver	Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm  04/26/02 First release
-* 1.00b rmm  09/23/02 Added XEmac_mPhyReset macro
-* 1.00c rpm  12/05/02 New version includes support for simple DMA
-*
-* -******************************************************************************/ - -#ifndef XEMAC_L_H /* prevent circular inclusions */ -#define XEMAC_L_H /* by using protection macros */ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xio.h" - -/************************** Constant Definitions *****************************/ - -/* Offset of the MAC registers from the IPIF base address */ -#define XEM_REG_OFFSET 0x1100UL - -/* - * Register offsets for the Ethernet MAC. Each register is 32 bits. - */ -#define XEM_EMIR_OFFSET (XEM_REG_OFFSET + 0x0) /* EMAC Module ID */ -#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ -#define XEM_IFGP_OFFSET (XEM_REG_OFFSET + 0x8) /* Interframe Gap */ -#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ -#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ -#define XEM_MGTCR_OFFSET (XEM_REG_OFFSET + 0x14) /* MII mgmt control */ -#define XEM_MGTDR_OFFSET (XEM_REG_OFFSET + 0x18) /* MII mgmt data */ -#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ -#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ -#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ -#define XEM_RMFC_OFFSET (XEM_REG_OFFSET + 0x28) /* Rx missed frames */ -#define XEM_RCC_OFFSET (XEM_REG_OFFSET + 0x2C) /* Rx collisions */ -#define XEM_RFCSEC_OFFSET (XEM_REG_OFFSET + 0x30) /* Rx FCS errors */ -#define XEM_RAEC_OFFSET (XEM_REG_OFFSET + 0x34) /* Rx alignment errors */ -#define XEM_TEDC_OFFSET (XEM_REG_OFFSET + 0x38) /* Transmit excess - * deferral cnt */ - -/* - * Register offsets for the IPIF components - */ -#define XEM_ISR_OFFSET 0x20UL /* Interrupt status */ - -#define XEM_DMA_OFFSET 0x2300UL -#define XEM_DMA_SEND_OFFSET (XEM_DMA_OFFSET + 0x0) /* DMA send channel */ -#define XEM_DMA_RECV_OFFSET (XEM_DMA_OFFSET + 0x40) /* DMA recv channel */ - -#define XEM_PFIFO_OFFSET 0x2000UL -#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) /* Tx registers */ -#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) /* Rx registers */ -#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) /* Tx keyhole */ -#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) /* Rx keyhole */ - -/* - * EMAC Module Identification Register (EMIR) - */ -#define XEM_EMIR_VERSION_MASK 0xFFFF0000UL /* Device version */ -#define XEM_EMIR_TYPE_MASK 0x0000FF00UL /* Device type */ - -/* - * EMAC Control Register (ECR) - */ -#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL /* Full duplex mode */ -#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL /* Reset transmitter */ -#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL /* Enable transmitter */ -#define XEM_ECR_RECV_RESET_MASK 0x10000000UL /* Reset receiver */ -#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL /* Enable receiver */ -#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL /* Enable PHY */ -#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL /* Enable xmit pad insert */ -#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL /* Enable xmit FCS insert */ -#define XEM_ECR_XMIT_ADDR_INSERT_MASK 0x00800000UL /* Enable xmit source addr - * insertion */ -#define XEM_ECR_XMIT_ERROR_INSERT_MASK 0x00400000UL /* Insert xmit error */ -#define XEM_ECR_XMIT_ADDR_OVWRT_MASK 0x00200000UL /* Enable xmit source addr - * overwrite */ -#define XEM_ECR_LOOPBACK_MASK 0x00100000UL /* Enable internal - * loopback */ -#define XEM_ECR_RECV_STRIP_ENABLE_MASK 0x00080000UL /* Enable recv pad/fcs strip */ -#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL /* Enable unicast addr */ -#define XEM_ECR_MULTI_ENABLE_MASK 0x00010000UL /* Enable multicast addr */ -#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL /* Enable broadcast addr */ -#define XEM_ECR_PROMISC_ENABLE_MASK 0x00004000UL /* Enable promiscuous mode */ -#define XEM_ECR_RECV_ALL_MASK 0x00002000UL /* Receive all frames */ -#define XEM_ECR_RESERVED2_MASK 0x00001000UL /* Reserved */ -#define XEM_ECR_MULTI_HASH_ENABLE_MASK 0x00000800UL /* Enable multicast hash */ -#define XEM_ECR_PAUSE_FRAME_MASK 0x00000400UL /* Interpret pause frames */ -#define XEM_ECR_CLEAR_HASH_MASK 0x00000200UL /* Clear hash table */ -#define XEM_ECR_ADD_HASH_ADDR_MASK 0x00000100UL /* Add hash table address */ - -/* - * Interframe Gap Register (IFGR) - */ -#define XEM_IFGP_PART1_MASK 0xF8000000UL /* Interframe Gap Part1 */ -#define XEM_IFGP_PART1_SHIFT 27 -#define XEM_IFGP_PART2_MASK 0x07C00000UL /* Interframe Gap Part2 */ -#define XEM_IFGP_PART2_SHIFT 22 - -/* - * Station Address High Register (SAH) - */ -#define XEM_SAH_ADDR_MASK 0x0000FFFFUL /* Station address high bytes */ - -/* - * Station Address Low Register (SAL) - */ -#define XEM_SAL_ADDR_MASK 0xFFFFFFFFUL /* Station address low bytes */ - -/* - * MII Management Control Register (MGTCR) - */ -#define XEM_MGTCR_START_MASK 0x80000000UL /* Start/Busy */ -#define XEM_MGTCR_RW_NOT_MASK 0x40000000UL /* Read/Write Not (direction) */ -#define XEM_MGTCR_PHY_ADDR_MASK 0x3E000000UL /* PHY address */ -#define XEM_MGTCR_PHY_ADDR_SHIFT 25 /* PHY address shift */ -#define XEM_MGTCR_REG_ADDR_MASK 0x01F00000UL /* Register address */ -#define XEM_MGTCR_REG_ADDR_SHIFT 20 /* Register addr shift */ -#define XEM_MGTCR_MII_ENABLE_MASK 0x00080000UL /* Enable MII from EMAC */ -#define XEM_MGTCR_RD_ERROR_MASK 0x00040000UL /* MII mgmt read error */ - -/* - * MII Management Data Register (MGTDR) - */ -#define XEM_MGTDR_DATA_MASK 0x0000FFFFUL /* MII data */ - -/* - * Receive Packet Length Register (RPLR) - */ -#define XEM_RPLR_LENGTH_MASK 0x0000FFFFUL /* Receive packet length */ - -/* - * Transmit Packet Length Register (TPLR) - */ -#define XEM_TPLR_LENGTH_MASK 0x0000FFFFUL /* Transmit packet length */ - -/* - * Transmit Status Register (TSR) - */ -#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */ -#define XEM_TSR_FIFO_UNDERRUN_MASK 0x40000000UL /* Packet FIFO underrun */ -#define XEM_TSR_ATTEMPTS_MASK 0x3E000000UL /* Transmission attempts */ -#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */ - -/* - * Receive Missed Frame Count (RMFC) - */ -#define XEM_RMFC_DATA_MASK 0x0000FFFFUL - -/* - * Receive Collision Count (RCC) - */ -#define XEM_RCC_DATA_MASK 0x0000FFFFUL - -/* - * Receive FCS Error Count (RFCSEC) - */ -#define XEM_RFCSEC_DATA_MASK 0x0000FFFFUL - -/* - * Receive Alignment Error Count (RALN) - */ -#define XEM_RAEC_DATA_MASK 0x0000FFFFUL - -/* - * Transmit Excess Deferral Count (TEDC) - */ -#define XEM_TEDC_DATA_MASK 0x0000FFFFUL - -/* - * EMAC Interrupt Registers (Status and Enable) masks. These registers are - * part of the IPIF IP Interrupt registers - */ -#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */ -#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */ -#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */ -#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */ -#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */ -#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */ -#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */ -#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo - * overrun */ -#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo - * underrun */ -#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo - * overrun */ -#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo - * underrun */ -#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo - * overrun */ -#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo - * underrun */ -#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt - * received */ -#define XEM_EIR_RECV_DFIFO_OVER_MASK 0x00004000UL /* Receive data fifo - * overrun */ -#define XEM_EIR_RECV_MISSED_FRAME_MASK 0x00008000UL /* Receive missed frame - * error */ -#define XEM_EIR_RECV_COLLISION_MASK 0x00010000UL /* Receive collision - * error */ -#define XEM_EIR_RECV_FCS_ERROR_MASK 0x00020000UL /* Receive FCS error */ -#define XEM_EIR_RECV_LEN_ERROR_MASK 0x00040000UL /* Receive length field - * error */ -#define XEM_EIR_RECV_SHORT_ERROR_MASK 0x00080000UL /* Receive short frame - * error */ -#define XEM_EIR_RECV_LONG_ERROR_MASK 0x00100000UL /* Receive long frame - * error */ -#define XEM_EIR_RECV_ALIGN_ERROR_MASK 0x00200000UL /* Receive alignment - * error */ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/***************************************************************************** -* -* Low-level driver macros and functions. The list below provides signatures -* to help the user use the macros. -* -* u32 XEmac_mReadReg(u32 BaseAddress, int RegOffset) -* void XEmac_mWriteReg(u32 BaseAddress, int RegOffset, u32 Mask) -* -* void XEmac_mSetControlReg(u32 BaseAddress, u32 Mask) -* void XEmac_mSetMacAddress(u32 BaseAddress, u8 *AddressPtr) -* -* void XEmac_mEnable(u32 BaseAddress) -* void XEmac_mDisable(u32 BaseAddress) -* -* u32 XEmac_mIsTxDone(u32 BaseAddress) -* u32 XEmac_mIsRxEmpty(u32 BaseAddress) -* -* void XEmac_SendFrame(u32 BaseAddress, u8 *FramePtr, int Size) -* int XEmac_RecvFrame(u32 BaseAddress, u8 *FramePtr) -* -*****************************************************************************/ - -/****************************************************************************/ -/** -* -* Read the given register. -* -* @param BaseAddress is the base address of the device -* @param RegOffset is the register offset to be read -* -* @return The 32-bit value of the register -* -* @note None. -* -*****************************************************************************/ -#define XEmac_mReadReg(BaseAddress, RegOffset) \ - XIo_In32((BaseAddress) + (RegOffset)) - -/****************************************************************************/ -/** -* -* Write the given register. -* -* @param BaseAddress is the base address of the device -* @param RegOffset is the register offset to be written -* @param Data is the 32-bit value to write to the register -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -#define XEmac_mWriteReg(BaseAddress, RegOffset, Data) \ - XIo_Out32((BaseAddress) + (RegOffset), (Data)) - -/****************************************************************************/ -/** -* -* Set the contents of the control register. Use the XEM_ECR_* constants -* defined above to create the bit-mask to be written to the register. -* -* @param BaseAddress is the base address of the device -* @param Mask is the 16-bit value to write to the control register -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -#define XEmac_mSetControlReg(BaseAddress, Mask) \ - XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, (Mask)) - -/****************************************************************************/ -/** -* -* Set the station address of the EMAC device. -* -* @param BaseAddress is the base address of the device -* @param AddressPtr is a pointer to a 6-byte MAC address -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -#define XEmac_mSetMacAddress(BaseAddress, AddressPtr) \ -{ \ - u32 MacAddr; \ - \ - MacAddr = ((AddressPtr)[0] << 8) | (AddressPtr)[1]; \ - XIo_Out32((BaseAddress) + XEM_SAH_OFFSET, MacAddr); \ - \ - MacAddr = ((AddressPtr)[2] << 24) | ((AddressPtr)[3] << 16) | \ - ((AddressPtr)[4] << 8) | (AddressPtr)[5]; \ - \ - XIo_Out32((BaseAddress) + XEM_SAL_OFFSET, MacAddr); \ -} - -/****************************************************************************/ -/** -* -* Enable the transmitter and receiver. Preserve the contents of the control -* register. -* -* @param BaseAddress is the base address of the device -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -#define XEmac_mEnable(BaseAddress) \ -{ \ - u32 Control; \ - Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \ - Control &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); \ - Control |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); \ - XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \ -} - -/****************************************************************************/ -/** -* -* Disable the transmitter and receiver. Preserve the contents of the control -* register. -* -* @param BaseAddress is the base address of the device -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -#define XEmac_mDisable(BaseAddress) \ - XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, \ - XIo_In32((BaseAddress) + XEM_ECR_OFFSET) & \ - ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK)) - -/****************************************************************************/ -/** -* -* Check to see if the transmission is complete. -* -* @param BaseAddress is the base address of the device -* -* @return TRUE if it is done, or FALSE if it is not. -* -* @note None. -* -*****************************************************************************/ -#define XEmac_mIsTxDone(BaseAddress) \ - (XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_XMIT_DONE_MASK) - -/****************************************************************************/ -/** -* -* Check to see if the receive FIFO is empty. -* -* @param BaseAddress is the base address of the device -* -* @return TRUE if it is empty, or FALSE if it is not. -* -* @note None. -* -*****************************************************************************/ -#define XEmac_mIsRxEmpty(BaseAddress) \ - (!(XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_RECV_DONE_MASK)) - -/****************************************************************************/ -/** -* -* Reset MII compliant PHY -* -* @param BaseAddress is the base address of the device -* -* @return None. -* -* @note None. -* -*****************************************************************************/ -#define XEmac_mPhyReset(BaseAddress) \ -{ \ - u32 Control; \ - Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \ - Control &= ~XEM_ECR_PHY_ENABLE_MASK; \ - XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \ - Control |= XEM_ECR_PHY_ENABLE_MASK; \ - XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \ -} - -/************************** Function Prototypes ******************************/ - -void XEmac_SendFrame(u32 BaseAddress, u8 * FramePtr, int Size); -int XEmac_RecvFrame(u32 BaseAddress, u8 * FramePtr); - -#endif /* end of protection macro */ diff --git a/board/xilinx/xilinx_enet/xemac_options.c b/board/xilinx/xilinx_enet/xemac_options.c deleted file mode 100644 index 1f225f8..0000000 --- a/board/xilinx/xilinx_enet/xemac_options.c +++ /dev/null @@ -1,318 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemac_options.c -* -* Functions in this file handle configuration of the XEmac driver. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rpm  07/31/01 First release
-* 1.00b rpm  02/20/02 Repartitioned files and functions
-* 1.00c rpm  12/05/02 New version includes support for simple DMA
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xemac_i.h" -#include "xio.h" - -/************************** Constant Definitions *****************************/ - -#define XEM_MAX_IFG 32 /* Maximum Interframe gap value */ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/* - * A table of options and masks. This table maps the user-visible options with - * the control register masks. It is used in Set/GetOptions as an alternative - * to a series of if/else pairs. Note that the polled options does not have a - * corresponding entry in the control register, so it does not exist in the - * table. - */ -typedef struct { - u32 Option; - u32 Mask; -} OptionMap; - -static OptionMap OptionsTable[] = { - {XEM_UNICAST_OPTION, XEM_ECR_UNICAST_ENABLE_MASK}, - {XEM_BROADCAST_OPTION, XEM_ECR_BROAD_ENABLE_MASK}, - {XEM_PROMISC_OPTION, XEM_ECR_PROMISC_ENABLE_MASK}, - {XEM_FDUPLEX_OPTION, XEM_ECR_FULL_DUPLEX_MASK}, - {XEM_LOOPBACK_OPTION, XEM_ECR_LOOPBACK_MASK}, - {XEM_MULTICAST_OPTION, XEM_ECR_MULTI_ENABLE_MASK}, - {XEM_FLOW_CONTROL_OPTION, XEM_ECR_PAUSE_FRAME_MASK}, - {XEM_INSERT_PAD_OPTION, XEM_ECR_XMIT_PAD_ENABLE_MASK}, - {XEM_INSERT_FCS_OPTION, XEM_ECR_XMIT_FCS_ENABLE_MASK}, - {XEM_INSERT_ADDR_OPTION, XEM_ECR_XMIT_ADDR_INSERT_MASK}, - {XEM_OVWRT_ADDR_OPTION, XEM_ECR_XMIT_ADDR_OVWRT_MASK}, - {XEM_STRIP_PAD_FCS_OPTION, XEM_ECR_RECV_STRIP_ENABLE_MASK} -}; - -#define XEM_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionMap)) - -/*****************************************************************************/ -/** -* -* Set Ethernet driver/device options. The device must be stopped before -* calling this function. The options are contained within a bit-mask with each -* bit representing an option (i.e., you can OR the options together). A one (1) -* in the bit-mask turns an option on, and a zero (0) turns the option off. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param OptionsFlag is a bit-mask representing the Ethernet options to turn on -* or off. See xemac.h for a description of the available options. -* -* @return -* -* - XST_SUCCESS if the options were set successfully -* - XST_DEVICE_IS_STARTED if the device has not yet been stopped -* -* @note -* -* This function is not thread-safe and makes use of internal resources that are -* shared between the Start, Stop, and SetOptions functions, so if one task -* might be setting device options while another is trying to start the device, -* protection of this shared data (typically using a semaphore) is required. -* -******************************************************************************/ -XStatus -XEmac_SetOptions(XEmac * InstancePtr, u32 OptionsFlag) -{ - u32 ControlReg; - int Index; - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; - } - - ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET); - - /* - * Loop through the options table, turning the option on or off - * depending on whether the bit is set in the incoming options flag. - */ - for (Index = 0; Index < XEM_NUM_OPTIONS; Index++) { - if (OptionsFlag & OptionsTable[Index].Option) { - ControlReg |= OptionsTable[Index].Mask; /* turn it on */ - } else { - ControlReg &= ~OptionsTable[Index].Mask; /* turn it off */ - } - } - - /* - * TODO: need to validate addr-overwrite only if addr-insert? - */ - - /* - * Now write the control register. Leave it to the upper layers - * to restart the device. - */ - XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg); - - /* - * Check the polled option - */ - if (OptionsFlag & XEM_POLLED_OPTION) { - InstancePtr->IsPolled = TRUE; - } else { - InstancePtr->IsPolled = FALSE; - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Get Ethernet driver/device options. The 32-bit value returned is a bit-mask -* representing the options. A one (1) in the bit-mask means the option is on, -* and a zero (0) means the option is off. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* -* @return -* -* The 32-bit value of the Ethernet options. The value is a bit-mask -* representing all options that are currently enabled. See xemac.h for a -* description of the available options. -* -* @note -* -* None. -* -******************************************************************************/ -u32 -XEmac_GetOptions(XEmac * InstancePtr) -{ - u32 OptionsFlag = 0; - u32 ControlReg; - int Index; - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * Get the control register to determine which options are currently set. - */ - ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET); - - /* - * Loop through the options table to determine which options are set - */ - for (Index = 0; Index < XEM_NUM_OPTIONS; Index++) { - if (ControlReg & OptionsTable[Index].Mask) { - OptionsFlag |= OptionsTable[Index].Option; - } - } - - if (InstancePtr->IsPolled) { - OptionsFlag |= XEM_POLLED_OPTION; - } - - return OptionsFlag; -} - -/*****************************************************************************/ -/** -* -* Set the Interframe Gap (IFG), which is the time the MAC delays between -* transmitting frames. There are two parts required. The total interframe gap -* is the total of the two parts. The values provided for the Part1 and Part2 -* parameters are multiplied by 4 to obtain the bit-time interval. The first -* part should be the first 2/3 of the total interframe gap. The MAC will reset -* the interframe gap timer if carrier sense becomes true during the period -* defined by interframe gap Part1. Part1 may be shorter than 2/3 the total and -* can be as small as zero. The second part should be the last 1/3 of the total -* interframe gap, but can be as large as the total interframe gap. The MAC -* will not reset the interframe gap timer if carrier sense becomes true during -* the period defined by interframe gap Part2. -* -* The device must be stopped before setting the interframe gap. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param Part1 is the interframe gap part 1 (which will be multiplied by 4 to -* get the bit-time interval). -* @param Part2 is the interframe gap part 2 (which will be multiplied by 4 to -* get the bit-time interval). -* -* @return -* -* - XST_SUCCESS if the interframe gap was set successfully -* - XST_DEVICE_IS_STARTED if the device has not been stopped -* -* @note -* -* None. -* -******************************************************************************/ -XStatus -XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2) -{ - u32 Ifg; - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(Part1 < XEM_MAX_IFG); - XASSERT_NONVOID(Part2 < XEM_MAX_IFG); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * Be sure device has been stopped - */ - if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STARTED; - } - - Ifg = Part1 << XEM_IFGP_PART1_SHIFT; - Ifg |= (Part2 << XEM_IFGP_PART2_SHIFT); - XIo_Out32(InstancePtr->BaseAddress + XEM_IFGP_OFFSET, Ifg); - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Get the interframe gap, parts 1 and 2. See the description of interframe gap -* above in XEmac_SetInterframeGap(). -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param Part1Ptr is a pointer to an 8-bit buffer into which the interframe gap -* part 1 value will be copied. -* @param Part2Ptr is a pointer to an 8-bit buffer into which the interframe gap -* part 2 value will be copied. -* -* @return -* -* None. The values of the interframe gap parts are copied into the -* output parameters. -* -******************************************************************************/ -void -XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr) -{ - u32 Ifg; - - XASSERT_VOID(InstancePtr != NULL); - XASSERT_VOID(Part1Ptr != NULL); - XASSERT_VOID(Part2Ptr != NULL); - XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - Ifg = XIo_In32(InstancePtr->BaseAddress + XEM_IFGP_OFFSET); - *Part1Ptr = (Ifg & XEM_IFGP_PART1_MASK) >> XEM_IFGP_PART1_SHIFT; - *Part2Ptr = (Ifg & XEM_IFGP_PART2_MASK) >> XEM_IFGP_PART2_SHIFT; -} diff --git a/board/xilinx/xilinx_enet/xemac_polled.c b/board/xilinx/xilinx_enet/xemac_polled.c deleted file mode 100644 index 23768bc..0000000 --- a/board/xilinx/xilinx_enet/xemac_polled.c +++ /dev/null @@ -1,482 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xemac_polled.c -* -* Contains functions used when the driver is in polled mode. Use the -* XEmac_SetOptions() function to put the driver into polled mode. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rpm  07/31/01 First release
-* 1.00b rpm  02/20/02 Repartitioned files and functions
-* 1.00c rpm  12/05/02 New version includes support for simple DMA
-*
-* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xbasic_types.h" -#include "xemac_i.h" -#include "xio.h" -#include "xipif_v1_23_b.h" /* Uses v1.23b of the IPIF */ - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Variable Definitions *****************************/ - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* -* Send an Ethernet frame in polled mode. The device/driver must be in polled -* mode before calling this function. The driver writes the frame directly to -* the MAC's packet FIFO, then enters a loop checking the device status for -* completion or error. Statistics are updated if an error occurs. The buffer -* to be sent must be word-aligned. -* -* It is assumed that the upper layer software supplies a correctly formatted -* Ethernet frame, including the destination and source addresses, the -* type/length field, and the data field. It is also assumed that upper layer -* software does not append FCS at the end of the frame. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param BufPtr is a pointer to a word-aligned buffer containing the Ethernet -* frame to be sent. -* @param ByteCount is the size of the Ethernet frame. -* -* @return -* -* - XST_SUCCESS if the frame was sent successfully -* - XST_DEVICE_IS_STOPPED if the device has not yet been started -* - XST_NOT_POLLED if the device is not in polled mode -* - XST_FIFO_NO_ROOM if there is no room in the EMAC's length FIFO for this frame -* - XST_FIFO_ERROR if the FIFO was overrun or underrun. This error is critical -* and requires the caller to reset the device. -* - XST_EMAC_COLLISION if the send failed due to excess deferral or late -* collision -* -* @note -* -* There is the possibility that this function will not return if the hardware -* is broken (i.e., it never sets the status bit indicating that transmission is -* done). If this is of concern to the user, the user should provide protection -* from this problem - perhaps by using a different timer thread to monitor the -* PollSend thread. On a 10Mbps MAC, it takes about 1.21 msecs to transmit a -* maximum size Ethernet frame (1518 bytes). On a 100Mbps MAC, it takes about -* 121 usecs to transmit a maximum size Ethernet frame. -* -* @internal -* -* The EMAC uses FIFOs behind its length and status registers. For this reason, -* it is important to keep the length, status, and data FIFOs in sync when -* reading or writing to them. -* -******************************************************************************/ -XStatus -XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount) -{ - u32 IntrStatus; - u32 XmitStatus; - XStatus Result; - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(BufPtr != NULL); - XASSERT_NONVOID(ByteCount > XEM_HDR_SIZE); /* send at least 1 byte */ - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * Be sure the device is configured for polled mode and it is started - */ - if (!InstancePtr->IsPolled) { - return XST_NOT_POLLED; - } - - if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STOPPED; - } - - /* - * Check for overruns and underruns for the transmit status and length - * FIFOs and make sure the send packet FIFO is not deadlocked. Any of these - * conditions is bad enough that we do not want to continue. The upper layer - * software should reset the device to resolve the error. - */ - IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); - - /* - * Overrun errors - */ - if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | - XEM_EIR_XMIT_LFIFO_OVER_MASK)) { - InstancePtr->Stats.XmitOverrunErrors++; - InstancePtr->Stats.FifoErrors++; - return XST_FIFO_ERROR; - } - - /* - * Underrun errors - */ - if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | - XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { - InstancePtr->Stats.XmitUnderrunErrors++; - InstancePtr->Stats.FifoErrors++; - return XST_FIFO_ERROR; - } - - if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) { - InstancePtr->Stats.FifoErrors++; - return XST_FIFO_ERROR; - } - - /* - * Before writing to the data FIFO, make sure the length FIFO is not - * full. The data FIFO might not be full yet even though the length FIFO - * is. This avoids an overrun condition on the length FIFO and keeps the - * FIFOs in sync. - */ - if (IntrStatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) { - /* - * Clear the latched LFIFO_FULL bit so next time around the most - * current status is represented - */ - XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, - XEM_EIR_XMIT_LFIFO_FULL_MASK); - return XST_FIFO_NO_ROOM; - } - - /* - * This is a non-blocking write. The packet FIFO returns an error if there - * is not enough room in the FIFO for this frame. - */ - Result = - XPacketFifoV100b_Write(&InstancePtr->SendFifo, BufPtr, ByteCount); - if (Result != XST_SUCCESS) { - return Result; - } - - /* - * Loop on the MAC's status to wait for any pause to complete. - */ - IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); - - while ((IntrStatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) { - IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); - /* - * Clear the pause status from the transmit status register - */ - XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, - IntrStatus & XEM_EIR_XMIT_PAUSE_MASK); - } - - /* - * Set the MAC's transmit packet length register to tell it to transmit - */ - XIo_Out32(InstancePtr->BaseAddress + XEM_TPLR_OFFSET, ByteCount); - - /* - * Loop on the MAC's status to wait for the transmit to complete. The - * transmit status is in the FIFO when the XMIT_DONE bit is set. - */ - do { - IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); - } - while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0); - - XmitStatus = XIo_In32(InstancePtr->BaseAddress + XEM_TSR_OFFSET); - - InstancePtr->Stats.XmitFrames++; - InstancePtr->Stats.XmitBytes += ByteCount; - - /* - * Check for various errors, bump statistics, and return an error status. - */ - - /* - * Overrun errors - */ - if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | - XEM_EIR_XMIT_LFIFO_OVER_MASK)) { - InstancePtr->Stats.XmitOverrunErrors++; - InstancePtr->Stats.FifoErrors++; - return XST_FIFO_ERROR; - } - - /* - * Underrun errors - */ - if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | - XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { - InstancePtr->Stats.XmitUnderrunErrors++; - InstancePtr->Stats.FifoErrors++; - return XST_FIFO_ERROR; - } - - /* - * Clear the interrupt status register of transmit statuses - */ - XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, - IntrStatus & XEM_EIR_XMIT_ALL_MASK); - - /* - * Collision errors are stored in the transmit status register - * instead of the interrupt status register - */ - if (XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) { - InstancePtr->Stats.XmitExcessDeferral++; - return XST_EMAC_COLLISION_ERROR; - } - - if (XmitStatus & XEM_TSR_LATE_COLLISION_MASK) { - InstancePtr->Stats.XmitLateCollisionErrors++; - return XST_EMAC_COLLISION_ERROR; - } - - return XST_SUCCESS; -} - -/*****************************************************************************/ -/** -* -* Receive an Ethernet frame in polled mode. The device/driver must be in polled -* mode before calling this function. The driver receives the frame directly -* from the MAC's packet FIFO. This is a non-blocking receive, in that if there -* is no frame ready to be received at the device, the function returns with an -* error. The MAC's error status is not checked, so statistics are not updated -* for polled receive. The buffer into which the frame will be received must be -* word-aligned. -* -* @param InstancePtr is a pointer to the XEmac instance to be worked on. -* @param BufPtr is a pointer to a word-aligned buffer into which the received -* Ethernet frame will be copied. -* @param ByteCountPtr is both an input and an output parameter. It is a pointer -* to a 32-bit word that contains the size of the buffer on entry into the -* function and the size the received frame on return from the function. -* -* @return -* -* - XST_SUCCESS if the frame was sent successfully -* - XST_DEVICE_IS_STOPPED if the device has not yet been started -* - XST_NOT_POLLED if the device is not in polled mode -* - XST_NO_DATA if there is no frame to be received from the FIFO -* - XST_BUFFER_TOO_SMALL if the buffer to receive the frame is too small for -* the frame waiting in the FIFO. -* -* @note -* -* Input buffer must be big enough to hold the largest Ethernet frame. Buffer -* must also be 32-bit aligned. -* -* @internal -* -* The EMAC uses FIFOs behind its length and status registers. For this reason, -* it is important to keep the length, status, and data FIFOs in sync when -* reading or writing to them. -* -******************************************************************************/ -XStatus -XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr) -{ - XStatus Result; - u32 PktLength; - u32 IntrStatus; - - XASSERT_NONVOID(InstancePtr != NULL); - XASSERT_NONVOID(BufPtr != NULL); - XASSERT_NONVOID(ByteCountPtr != NULL); - XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY); - - /* - * Be sure the device is configured for polled mode and it is started - */ - if (!InstancePtr->IsPolled) { - return XST_NOT_POLLED; - } - - if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) { - return XST_DEVICE_IS_STOPPED; - } - - /* - * Make sure the buffer is big enough to hold the maximum frame size. - * We need to do this because as soon as we read the MAC's packet length - * register, which is actually a FIFO, we remove that length from the - * FIFO. We do not want to read the length FIFO without also reading the - * data FIFO since this would get the FIFOs out of sync. So we have to - * make this restriction. - */ - if (*ByteCountPtr < XEM_MAX_FRAME_SIZE) { - return XST_BUFFER_TOO_SMALL; - } - - /* - * First check for packet FIFO deadlock and return an error if it has - * occurred. A reset by the caller is necessary to correct this problem. - */ - if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) { - InstancePtr->Stats.FifoErrors++; - return XST_FIFO_ERROR; - } - - /* - * Get the interrupt status to know what happened (whether an error occurred - * and/or whether frames have been received successfully). When clearing the - * intr status register, clear only statuses that pertain to receive. - */ - IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); - XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, - IntrStatus & XEM_EIR_RECV_ALL_MASK); - - /* - * Check receive errors and bump statistics so the caller will have a clue - * as to why data may not have been received. We continue on if an error - * occurred since there still may be frames that were received successfully. - */ - if (IntrStatus & (XEM_EIR_RECV_LFIFO_OVER_MASK | - XEM_EIR_RECV_DFIFO_OVER_MASK)) { - InstancePtr->Stats.RecvOverrunErrors++; - InstancePtr->Stats.FifoErrors++; - } - - if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) { - InstancePtr->Stats.RecvUnderrunErrors++; - InstancePtr->Stats.FifoErrors++; - } - - /* - * General receive errors - */ - if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) { - if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) { - InstancePtr->Stats.RecvMissedFrameErrors = - XIo_In32(InstancePtr->BaseAddress + - XEM_RMFC_OFFSET); - } - - if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) { - InstancePtr->Stats.RecvCollisionErrors = - XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET); - } - - if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) { - InstancePtr->Stats.RecvFcsErrors = - XIo_In32(InstancePtr->BaseAddress + - XEM_RFCSEC_OFFSET); - } - - if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) { - InstancePtr->Stats.RecvLengthFieldErrors++; - } - - if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) { - InstancePtr->Stats.RecvShortErrors++; - } - - if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) { - InstancePtr->Stats.RecvLongErrors++; - } - - if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) { - InstancePtr->Stats.RecvAlignmentErrors = - XIo_In32(InstancePtr->BaseAddress + - XEM_RAEC_OFFSET); - } - } - - /* - * Before reading from the length FIFO, make sure the length FIFO is not - * empty. We could cause an underrun error if we try to read from an - * empty FIFO. - */ - if ((IntrStatus & XEM_EIR_RECV_DONE_MASK) == 0) { - return XST_NO_DATA; - } - - /* - * Determine, from the MAC, the length of the next packet available - * in the data FIFO (there should be a non-zero length here) - */ - PktLength = XIo_In32(InstancePtr->BaseAddress + XEM_RPLR_OFFSET); - if (PktLength == 0) { - return XST_NO_DATA; - } - - /* - * Write the RECV_DONE bit in the status register to clear it. This bit - * indicates the RPLR is non-empty, and we know it's set at this point. - * We clear it so that subsequent entry into this routine will reflect the - * current status. This is done because the non-empty bit is latched in the - * IPIF, which means it may indicate a non-empty condition even though - * there is something in the FIFO. - */ - XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, XEM_EIR_RECV_DONE_MASK); - - /* - * We assume that the MAC never has a length bigger than the largest - * Ethernet frame, so no need to make another check here. - */ - - /* - * This is a non-blocking read. The FIFO returns an error if there is - * not at least the requested amount of data in the FIFO. - */ - Result = - XPacketFifoV100b_Read(&InstancePtr->RecvFifo, BufPtr, PktLength); - if (Result != XST_SUCCESS) { - return Result; - } - - InstancePtr->Stats.RecvFrames++; - InstancePtr->Stats.RecvBytes += PktLength; - - *ByteCountPtr = PktLength; - - return XST_SUCCESS; -} diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c deleted file mode 100644 index f3ecba7..0000000 --- a/board/xilinx/xilinx_iic/iic_adapter.c +++ /dev/null @@ -1,530 +0,0 @@ -/****************************************************************************** -* -* Author: Xilinx, Inc. -* -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE. -* -* -* Xilinx hardware products are not intended for use in life support -* appliances, devices, or systems. Use in such applications is -* expressly prohibited. -* -* -* (c) Copyright 2002-2004 Xilinx Inc. -* All rights reserved. -* -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, write to the Free Software Foundation, Inc., -* 675 Mass Ave, Cambridge, MA 02139, USA. -* -******************************************************************************/ - -#include -#include -#include -#include -#include "xparameters.h" - -#ifdef CFG_ENV_IS_IN_EEPROM -#include -#include "xiic_l.h" - -#define IIC_DELAY 5000 - -static u8 envStep = 0; /* 0 means crc has not been read */ -const u8 hex[] = "0123456789ABCDEF"; /* lookup table for ML300 CRC */ - -/************************************************************************ - * Use Xilinx provided driver to send data to EEPROM using iic bus. - */ -static void -send(u32 adr, u8 * data, u32 len) -{ - u8 sendBuf[34]; /* first 2-bit is address and others are data */ - u32 pos, wlen; - u32 ret; - - wlen = 32; - for (pos = 0; pos < len; pos += 32) { - if ((len - pos) < 32) - wlen = len - pos; - - /* Put address and data bits together */ - sendBuf[0] = (u8) ((adr + pos) >> 8); - sendBuf[1] = (u8) (adr + pos); - memcpy(&sendBuf[2], &data[pos], wlen); - - /* Send to EEPROM through iic bus */ - ret = XIic_Send(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, - sendBuf, wlen + 2); - - udelay(IIC_DELAY); - } -} - -/************************************************************************ - * Use Xilinx provided driver to read data from EEPROM using the iic bus. - */ -static void -receive(u32 adr, u8 * data, u32 len) -{ - u8 address[2]; - u32 ret; - - address[0] = (u8) (adr >> 8); - address[1] = (u8) adr; - - /* Provide EEPROM address */ - ret = - XIic_Send(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, address, - 2); - /* Receive data from EEPROM */ - ret = - XIic_Recv(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, data, len); -} - -/************************************************************************ - * Convert a hexadecimal string to its equivalent integer value. - */ -static u8 -axtoi(u8 * hexStg) -{ - u8 n; /* position in string */ - u8 m; /* position in digit[] to shift */ - u8 count; /* loop index */ - u8 intValue; /* integer value of hex string */ - u8 digit[2]; /* hold values to convert */ - - for (n = 0; n < 2; n++) { - if (hexStg[n] == '\0') - break; - if (hexStg[n] > 0x29 && hexStg[n] < 0x40) - digit[n] = hexStg[n] & 0x0f; - else if (hexStg[n] >= 'a' && hexStg[n] <= 'f') - digit[n] = (hexStg[n] & 0x0f) + 9; - else if (hexStg[n] >= 'A' && hexStg[n] <= 'F') - digit[n] = (hexStg[n] & 0x0f) + 9; - else - break; - } - - intValue = 0; - count = n; - m = n - 1; - n = 0; - while (n < count) { - intValue = intValue | (digit[n] << (m << 2)); - m--; /* adjust the position to set */ - n++; /* next digit to process */ - } - - return (intValue); -} - -/************************************************************************ - * Convert an integer string to its equivalent value. - */ -static u8 -atoi(uchar * string) -{ - u8 res = 0; - while (*string >= '0' && *string <= '9') { - res *= 10; - res += *string - '0'; - string++; - } - - return res; -} - -/************************************************************************ - * Key-value pairs are separated by "=" sign. - */ -static void -findKey(uchar * buffer, int *loc, u8 len) -{ - u32 i; - - for (i = 0; i < len; i++) - if (buffer[i] == '=') { - *loc = i; - return; - } - - /* return -1 is no "=" sign found */ - *loc = -1; -} - -/************************************************************************ - * Compute a new ML300 CRC when user calls the saveenv command. - * Also update EEPROM with new CRC value. - */ -static u8 -update_crc(u32 len, uchar * data) -{ - uchar temp[6] = { 'C', '=', 0x00, 0x00, 0x00, 0x00 }; - u32 crc; /* new crc value */ - u32 i; - - crc = 0; - - /* calculate new CRC */ - for (i = 0; i < len; i++) - crc += data[i]; - - /* CRC includes key for check sum */ - crc += 'C' + '='; - - /* compose new CRC to be updated */ - temp[2] = hex[(crc >> 4) & 0xf]; - temp[3] = hex[crc & 0xf]; - - /* check to see if env size exceeded */ - if (len + 6 > ENV_SIZE) { - printf("ERROR: not enough space to store CRC on EEPROM"); - return 1; - } - - memcpy(data + len, temp, 6); - return 0; -} - -/************************************************************************ - * Read out ML300 CRC and compare it with a runtime calculated ML300 CRC. - * If equal, then pass back a u-boot CRC value, otherwise pass back - * junk to indicate CRC error. -*/ -static void -read_crc(uchar * buffer, int len) -{ - u32 addr, n; - u32 crc; /* runtime crc */ - u8 old[2] = { 0xff, 0xff }; /* current CRC in EEPROM */ - u8 stop; /* indication of end of env data */ - u8 pre; /* previous EEPROM data bit */ - int i, loc; - - addr = CFG_ENV_OFFSET; /* start from first env address */ - n = 0; - pre = 1; - stop = 1; - crc = 0; - - /* calculate runtime CRC according to ML300 and read back - old CRC stored in the EEPROM */ - while (n < CFG_ENV_SIZE) { - receive(addr, buffer, len); - - /* found two null chars, end of env */ - if ((pre || buffer[0]) == 0) - break; - - findKey(buffer, &loc, len); - - /* found old check sum, read and store old CRC */ - if ((loc == 0 && pre == 'C') - || (loc > 0 && buffer[loc - 1] == 'C')) - receive(addr + loc + 1, old, 2); - - pre = buffer[len - 1]; - - /* calculate runtime ML300 CRC */ - crc += buffer[0]; - i = 1; - do { - crc += buffer[i]; - stop = buffer[i] || buffer[i - 1]; - i++; - } while (stop && (i < len)); - - if (stop == 0) - break; - - n += len; - addr += len; - } - - /* exclude old CRC from runtime calculation */ - crc -= (old[0] + old[1]); - - /* match CRC values, send back u-boot CRC */ - if ((old[0] == hex[(crc >> 4) & 0xf]) - && (old[1] == hex[crc & 0xf])) { - crc = 0; - n = 0; - addr = - CFG_ENV_OFFSET - offsetof(env_t, crc) + offsetof(env_t, - data); - /* calculate u-boot crc */ - while (n < ENV_SIZE) { - receive(addr, buffer, len); - crc = crc32(crc, buffer, len); - n += len; - addr += len; - } - - memcpy(buffer, &crc, 4); - } -} - -/************************************************************************ - * Convert IP address to hexadecimals. - */ -static void -ip_ml300(uchar * s, uchar * res) -{ - char temp[2]; - u8 i; - - res[0] = 0x00; - - for (i = 0; i < 4; i++) { - sprintf(temp, "%02x", atoi(s)); - s = (uchar *)strchr((char *)s, '.') + 1; - strcat((char *)res, temp); - } -} - -/************************************************************************ - * Change 0xff (255), a dummy null char to 0x00. - */ -static void -change_null(uchar * s) -{ - if (s != NULL) { - change_null((uchar *)strchr((char *)s + 1, 255)); - *(strchr((char *)s, 255)) = '\0'; - } -} - -/************************************************************************ - * Update environment variable name and values to u-boot standard. - */ -void -convert_env(void) -{ - char *s; /* pointer to env value */ - char temp[20]; /* temp storage for addresses */ - - /* E -> ethaddr */ - s = getenv("E"); - if (s != NULL) { - sprintf(temp, "%c%c.%c%c.%c%c.%c%c.%c%c.%c%c", - s[0], s[1], s[ 2], s[ 3], - s[4], s[5], s[ 6], s[ 7], - s[8], s[9], s[10], s[11] ); - setenv("ethaddr", temp); - setenv("E", NULL); - } - - /* L -> serial# */ - s = getenv("L"); - if (s != NULL) { - setenv("serial#", s); - setenv("L", NULL); - } - - /* I -> ipaddr */ - s = getenv("I"); - if (s != NULL) { - sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)), - axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6))); - setenv("ipaddr", temp); - setenv("I", NULL); - } - - /* S -> serverip */ - s = getenv("S"); - if (s != NULL) { - sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)), - axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6))); - setenv("serverip", temp); - setenv("S", NULL); - } - - /* A -> bootargs */ - s = getenv("A"); - if (s != NULL) { - setenv("bootargs", s); - setenv("A", NULL); - } - - /* F -> bootfile */ - s = getenv("F"); - if (s != NULL) { - setenv("bootfile", s); - setenv("F", NULL); - } - - /* M -> bootcmd */ - s = getenv("M"); - if (s != NULL) { - setenv("bootcmd", s); - setenv("M", NULL); - } - - /* Don't include C (CRC) */ - setenv("C", NULL); -} - -/************************************************************************ - * Save user modified environment values back to EEPROM. - */ -static void -save_env(void) -{ - char eprom[ENV_SIZE]; /* buffer to be written back to EEPROM */ - char *s, temp[20]; - char ff[] = { 0xff, 0x00 }; /* dummy null value */ - u32 len; /* length of env to be written to EEPROM */ - - eprom[0] = 0x00; - - /* ethaddr -> E */ - s = getenv("ethaddr"); - if (s != NULL) { - strcat(eprom, "E="); - sprintf(temp, "%c%c%c%c%c%c%c%c%c%c%c%c", - *s, *(s + 1), *(s + 3), *(s + 4), *(s + 6), *(s + 7), - *(s + 9), *(s + 10), *(s + 12), *(s + 13), *(s + 15), - *(s + 16)); - strcat(eprom, temp); - strcat(eprom, ff); - } - - /* serial# -> L */ - s = getenv("serial#"); - if (s != NULL) { - strcat(eprom, "L="); - strcat(eprom, s); - strcat(eprom, ff); - } - - /* ipaddr -> I */ - s = getenv("ipaddr"); - if (s != NULL) { - strcat(eprom, "I="); - ip_ml300((uchar *)s, (uchar *)temp); - strcat(eprom, temp); - strcat(eprom, ff); - } - - /* serverip -> S */ - s = getenv("serverip"); - if (s != NULL) { - strcat(eprom, "S="); - ip_ml300((uchar *)s, (uchar *)temp); - strcat(eprom, temp); - strcat(eprom, ff); - } - - /* bootargs -> A */ - s = getenv("bootargs"); - if (s != NULL) { - strcat(eprom, "A="); - strcat(eprom, s); - strcat(eprom, ff); - } - - /* bootfile -> F */ - s = getenv("bootfile"); - if (s != NULL) { - strcat(eprom, "F="); - strcat(eprom, s); - strcat(eprom, ff); - } - - /* bootcmd -> M */ - s = getenv("bootcmd"); - if (s != NULL) { - strcat(eprom, "M="); - strcat(eprom, s); - strcat(eprom, ff); - } - - len = strlen(eprom); /* find env length without crc */ - change_null((uchar *)eprom); /* change 0xff to 0x00 */ - - /* update EEPROM env values if there is enough space */ - if (update_crc(len, (uchar *)eprom) == 0) - send(CFG_ENV_OFFSET, (uchar *)eprom, len + 6); -} - -/************************************************************************ - * U-boot call for EEPROM read associated activities. - */ -int -i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - - if (envStep == 0) { - /* first read call is for crc */ - read_crc(buffer, len); - ++envStep; - return 0; - } else if (envStep == 1) { - /* then read out EEPROM content for runtime u-boot CRC calculation */ - receive(addr, buffer, len); - - if (addr + len - CFG_ENV_OFFSET == CFG_ENV_SIZE) - /* end of runtime crc read */ - ++envStep; - return 0; - } - - if (len < 2) { - /* when call getenv_r */ - receive(addr, buffer, len); - } else if (addr + len < CFG_ENV_OFFSET + CFG_ENV_SIZE) { - /* calling env_relocate(), but don't read out - crc value from EEPROM */ - receive(addr, buffer + 4, len); - } else { - receive(addr, buffer + 4, len - 4); - } - - return 0; - -} - -/************************************************************************ - * U-boot call for EEPROM write acativities. - */ -int -i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - /* save env on last page write called by u-boot */ - if (addr + len >= CFG_ENV_OFFSET + CFG_ENV_SIZE) - save_env(); - - return 0; -} - -/************************************************************************ - * Dummy function. - */ -int -i2c_probe(uchar chip) -{ - return 1; -} - -#endif diff --git a/board/xilinx/xilinx_iic/xiic_l.c b/board/xilinx/xilinx_iic/xiic_l.c deleted file mode 100644 index 6b78163..0000000 --- a/board/xilinx/xilinx_iic/xiic_l.c +++ /dev/null @@ -1,484 +0,0 @@ -/* $Id: xiic_l.c,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */ -/****************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xiic_l.c -* -* This file contains low-level driver functions that can be used to access the -* device. The user should refer to the hardware device specification for more -* details of the device operation. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver	Who  Date     Changes
-* ----- --- -------  -----------------------------------------------
-* 1.01b jhl 5/13/02  First release
-* 1.01b jhl 10/14/02 Corrected bug in the receive function, the setup of the
-*		     interrupt status mask was not being done in the loop such
-*		     that a read would sometimes fail on the last byte because
-*		     the transmit error which should have been ignored was
-*		     being used.  This would leave an extra byte in the FIFO
-*		     and the bus throttled such that the next operation would
-*		     also fail.	 Also updated the receive function to not
-*		     disable the device after the last byte until after the
-*		     bus transitions to not busy which is more consistent
-*		     with the expected behavior.
-* 1.01c ecm 12/05/02 new rev
-*
-* -****************************************************************************/ - -/***************************** Include Files *******************************/ - -#include "xbasic_types.h" -#include "xio.h" -#include "xipif_v1_23_b.h" -#include "xiic_l.h" - -/************************** Constant Definitions ***************************/ - -/**************************** Type Definitions *****************************/ - - -/***************** Macros (Inline Functions) Definitions *******************/ - - -/****************************************************************************** -* -* This macro clears the specified interrupt in the IPIF interrupt status -* register. It is non-destructive in that the register is read and only the -* interrupt specified is cleared. Clearing an interrupt acknowledges it. -* -* @param BaseAddress contains the IPIF registers base address. -* -* @param InterruptMask contains the interrupts to be disabled -* -* @return -* -* None. -* -* @note -* -* Signature: void XIic_mClearIisr(u32 BaseAddress, -* u32 InterruptMask); -* -******************************************************************************/ -#define XIic_mClearIisr(BaseAddress, InterruptMask) \ - XIIF_V123B_WRITE_IISR((BaseAddress), \ - XIIF_V123B_READ_IISR(BaseAddress) & (InterruptMask)) - -/****************************************************************************** -* -* This macro sends the address for a 7 bit address during both read and write -* operations. It takes care of the details to format the address correctly. -* This macro is designed to be called internally to the drivers. -* -* @param SlaveAddress contains the address of the slave to send to. -* -* @param Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION -* -* @return -* -* None. -* -* @note -* -* Signature: void XIic_mSend7BitAddr(u16 SlaveAddress, u8 Operation); -* -******************************************************************************/ -#define XIic_mSend7BitAddress(BaseAddress, SlaveAddress, Operation) \ -{ \ - u8 LocalAddr = (u8)(SlaveAddress << 1); \ - LocalAddr = (LocalAddr & 0xFE) | (Operation); \ - XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET, LocalAddr); \ -} - -/************************** Function Prototypes ****************************/ - -static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr, - unsigned ByteCount); -static unsigned SendData (u32 BaseAddress, u8 * BufferPtr, - unsigned ByteCount); - -/************************** Variable Definitions **************************/ - - -/****************************************************************************/ -/** -* Receive data as a master on the IIC bus. This function receives the data -* using polled I/O and blocks until the data has been received. It only -* supports 7 bit addressing and non-repeated start modes of operation. The -* user is responsible for ensuring the bus is not busy if multiple masters -* are present on the bus. -* -* @param BaseAddress contains the base address of the IIC device. -* @param Address contains the 7 bit IIC address of the device to send the -* specified data to. -* @param BufferPtr points to the data to be sent. -* @param ByteCount is the number of bytes to be sent. -* -* @return -* -* The number of bytes received. -* -* @note -* -* None -* -******************************************************************************/ -unsigned XIic_Recv (u32 BaseAddress, u8 Address, - u8 * BufferPtr, unsigned ByteCount) -{ - u8 CntlReg; - unsigned RemainingByteCount; - - /* Tx error is enabled incase the address (7 or 10) has no device to answer - * with Ack. When only one byte of data, must set NO ACK before address goes - * out therefore Tx error must not be enabled as it will go off immediately - * and the Rx full interrupt will be checked. If full, then the one byte - * was received and the Tx error will be disabled without sending an error - * callback msg. - */ - XIic_mClearIisr (BaseAddress, - XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK | - XIIC_INTR_ARB_LOST_MASK); - - /* Set receive FIFO occupancy depth for 1 byte (zero based) - */ - XIo_Out8 (BaseAddress + XIIC_RFD_REG_OFFSET, 0); - - /* 7 bit slave address, send the address for a read operation - * and set the state to indicate the address has been sent - */ - XIic_mSend7BitAddress (BaseAddress, Address, XIIC_READ_OPERATION); - - /* MSMS gets set after putting data in FIFO. Start the master receive - * operation by setting CR Bits MSMS to Master, if the buffer is only one - * byte, then it should not be acknowledged to indicate the end of data - */ - CntlReg = XIIC_CR_MSMS_MASK | XIIC_CR_ENABLE_DEVICE_MASK; - if (ByteCount == 1) { - CntlReg |= XIIC_CR_NO_ACK_MASK; - } - - /* Write out the control register to start receiving data and call the - * function to receive each byte into the buffer - */ - XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, CntlReg); - - /* Clear the latched interrupt status for the bus not busy bit which must - * be done while the bus is busy - */ - XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK); - - /* Try to receive the data from the IIC bus */ - - RemainingByteCount = RecvData (BaseAddress, BufferPtr, ByteCount); - /* - * The receive is complete, disable the IIC device and return the number of - * bytes that was received - */ - XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0); - - /* Return the number of bytes that was received */ - - return ByteCount - RemainingByteCount; -} - -/****************************************************************************** -* -* Receive the specified data from the device that has been previously addressed -* on the IIC bus. This function assumes that the 7 bit address has been sent -* and it should wait for the transmit of the address to complete. -* -* @param BaseAddress contains the base address of the IIC device. -* @param BufferPtr points to the buffer to hold the data that is received. -* @param ByteCount is the number of bytes to be received. -* -* @return -* -* The number of bytes remaining to be received. -* -* @note -* -* This function does not take advantage of the receive FIFO because it is -* designed for minimal code space and complexity. It contains loops that -* that could cause the function not to return if the hardware is not working. -* -* This function assumes that the calling function will disable the IIC device -* after this function returns. -* -******************************************************************************/ -static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount) -{ - u8 CntlReg; - u32 IntrStatusMask; - u32 IntrStatus; - - /* Attempt to receive the specified number of bytes on the IIC bus */ - - while (ByteCount > 0) { - /* Setup the mask to use for checking errors because when receiving one - * byte OR the last byte of a multibyte message an error naturally - * occurs when the no ack is done to tell the slave the last byte - */ - if (ByteCount == 1) { - IntrStatusMask = - XIIC_INTR_ARB_LOST_MASK | XIIC_INTR_BNB_MASK; - } else { - IntrStatusMask = - XIIC_INTR_ARB_LOST_MASK | - XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK; - } - - /* Wait for the previous transmit and the 1st receive to complete - * by checking the interrupt status register of the IPIF - */ - while (1) { - IntrStatus = XIIF_V123B_READ_IISR (BaseAddress); - if (IntrStatus & XIIC_INTR_RX_FULL_MASK) { - break; - } - /* Check the transmit error after the receive full because when - * sending only one byte transmit error will occur because of the - * no ack to indicate the end of the data - */ - if (IntrStatus & IntrStatusMask) { - return ByteCount; - } - } - - CntlReg = XIo_In8 (BaseAddress + XIIC_CR_REG_OFFSET); - - /* Special conditions exist for the last two bytes so check for them - * Note that the control register must be setup for these conditions - * before the data byte which was already received is read from the - * receive FIFO (while the bus is throttled - */ - if (ByteCount == 1) { - /* For the last data byte, it has already been read and no ack - * has been done, so clear MSMS while leaving the device enabled - * so it can get off the IIC bus appropriately with a stop. - */ - XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, - XIIC_CR_ENABLE_DEVICE_MASK); - } - - /* Before the last byte is received, set NOACK to tell the slave IIC - * device that it is the end, this must be done before reading the byte - * from the FIFO - */ - if (ByteCount == 2) { - /* Write control reg with NO ACK allowing last byte to - * have the No ack set to indicate to slave last byte read. - */ - XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, - CntlReg | XIIC_CR_NO_ACK_MASK); - } - - /* Read in data from the FIFO and unthrottle the bus such that the - * next byte is read from the IIC bus - */ - *BufferPtr++ = XIo_In8 (BaseAddress + XIIC_DRR_REG_OFFSET); - - /* Clear the latched interrupt status so that it will be updated with - * the new state when it changes, this must be done after the receive - * register is read - */ - XIic_mClearIisr (BaseAddress, XIIC_INTR_RX_FULL_MASK | - XIIC_INTR_TX_ERROR_MASK | - XIIC_INTR_ARB_LOST_MASK); - ByteCount--; - } - - /* Wait for the bus to transition to not busy before returning, the IIC - * device cannot be disabled until this occurs. It should transition as - * the MSMS bit of the control register was cleared before the last byte - * was read from the FIFO. - */ - while (1) { - if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) { - break; - } - } - - return ByteCount; -} - -/****************************************************************************/ -/** -* Send data as a master on the IIC bus. This function sends the data -* using polled I/O and blocks until the data has been sent. It only supports -* 7 bit addressing and non-repeated start modes of operation. The user is -* responsible for ensuring the bus is not busy if multiple masters are present -* on the bus. -* -* @param BaseAddress contains the base address of the IIC device. -* @param Address contains the 7 bit IIC address of the device to send the -* specified data to. -* @param BufferPtr points to the data to be sent. -* @param ByteCount is the number of bytes to be sent. -* -* @return -* -* The number of bytes sent. -* -* @note -* -* None -* -******************************************************************************/ -unsigned XIic_Send (u32 BaseAddress, u8 Address, - u8 * BufferPtr, unsigned ByteCount) -{ - unsigned RemainingByteCount; - - /* Put the address into the FIFO to be sent and indicate that the operation - * to be performed on the bus is a write operation - */ - XIic_mSend7BitAddress (BaseAddress, Address, XIIC_WRITE_OPERATION); - - /* Clear the latched interrupt status so that it will be updated with the - * new state when it changes, this must be done after the address is put - * in the FIFO - */ - XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK | - XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_ARB_LOST_MASK); - - /* MSMS must be set after putting data into transmit FIFO, indicate the - * direction is transmit, this device is master and enable the IIC device - */ - XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, - XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK | - XIIC_CR_ENABLE_DEVICE_MASK); - - /* Clear the latched interrupt - * status for the bus not busy bit which must be done while the bus is busy - */ - XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK); - - /* Send the specified data to the device on the IIC bus specified by the - * the address - */ - RemainingByteCount = SendData (BaseAddress, BufferPtr, ByteCount); - - /* - * The send is complete, disable the IIC device and return the number of - * bytes that was sent - */ - XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0); - - return ByteCount - RemainingByteCount; -} - -/****************************************************************************** -* -* Send the specified buffer to the device that has been previously addressed -* on the IIC bus. This function assumes that the 7 bit address has been sent -* and it should wait for the transmit of the address to complete. -* -* @param BaseAddress contains the base address of the IIC device. -* @param BufferPtr points to the data to be sent. -* @param ByteCount is the number of bytes to be sent. -* -* @return -* -* The number of bytes remaining to be sent. -* -* @note -* -* This function does not take advantage of the transmit FIFO because it is -* designed for minimal code space and complexity. It contains loops that -* that could cause the function not to return if the hardware is not working. -* -******************************************************************************/ -static unsigned SendData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount) -{ - u32 IntrStatus; - - /* Send the specified number of bytes in the specified buffer by polling - * the device registers and blocking until complete - */ - while (ByteCount > 0) { - /* Wait for the transmit to be empty before sending any more data - * by polling the interrupt status register - */ - while (1) { - IntrStatus = XIIF_V123B_READ_IISR (BaseAddress); - - if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK | - XIIC_INTR_ARB_LOST_MASK | - XIIC_INTR_BNB_MASK)) { - return ByteCount; - } - - if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) { - break; - } - } - /* If there is more than one byte to send then put the next byte to send - * into the transmit FIFO - */ - if (ByteCount > 1) { - XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET, - *BufferPtr++); - } else { - /* Set the stop condition before sending the last byte of data so that - * the stop condition will be generated immediately following the data - * This is done by clearing the MSMS bit in the control register. - */ - XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, - XIIC_CR_ENABLE_DEVICE_MASK | - XIIC_CR_DIR_IS_TX_MASK); - - /* Put the last byte to send in the transmit FIFO */ - - XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET, - *BufferPtr++); - } - - /* Clear the latched interrupt status register and this must be done after - * the transmit FIFO has been written to or it won't clear - */ - XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK); - - /* Update the byte count to reflect the byte sent and clear the latched - * interrupt status so it will be updated for the new state - */ - ByteCount--; - } - - /* Wait for the bus to transition to not busy before returning, the IIC - * device cannot be disabled until this occurs. - * Note that this is different from a receive operation because the stop - * condition causes the bus to go not busy. - */ - while (1) { - if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) { - break; - } - } - - return ByteCount; -} diff --git a/board/xilinx/xilinx_iic/xiic_l.h b/board/xilinx/xilinx_iic/xiic_l.h deleted file mode 100644 index a2c4c49..0000000 --- a/board/xilinx/xilinx_iic/xiic_l.h +++ /dev/null @@ -1,150 +0,0 @@ -/* $Id: xiic_l.h,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */ -/***************************************************************************** -* -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE. -* -* (c) Copyright 2002 Xilinx Inc. -* All rights reserved. -* -*****************************************************************************/ -/****************************************************************************/ -/** -* -* @file xiic_l.h -* -* This header file contains identifiers and low-level driver functions (or -* macros) that can be used to access the device. High-level driver functions -* are defined in xiic.h. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver	Who  Date     Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl  05/07/02 First release
-* 1.01c ecm  12/05/02 new rev
-*
-* -*****************************************************************************/ - -#ifndef XIIC_L_H /* prevent circular inclusions */ -#define XIIC_L_H /* by using protection macros */ - -/***************************** Include Files ********************************/ - -#include "xbasic_types.h" - -/************************** Constant Definitions ****************************/ - -#define XIIC_MSB_OFFSET 3 - -#define XIIC_REG_OFFSET 0x100 + XIIC_MSB_OFFSET - -/* - * Register offsets in bytes from RegisterBase. Three is added to the - * base offset to access LSB (IBM style) of the word - */ -#define XIIC_CR_REG_OFFSET 0x00+XIIC_REG_OFFSET /* Control Register */ -#define XIIC_SR_REG_OFFSET 0x04+XIIC_REG_OFFSET /* Status Register */ -#define XIIC_DTR_REG_OFFSET 0x08+XIIC_REG_OFFSET /* Data Tx Register */ -#define XIIC_DRR_REG_OFFSET 0x0C+XIIC_REG_OFFSET /* Data Rx Register */ -#define XIIC_ADR_REG_OFFSET 0x10+XIIC_REG_OFFSET /* Address Register */ -#define XIIC_TFO_REG_OFFSET 0x14+XIIC_REG_OFFSET /* Tx FIFO Occupancy */ -#define XIIC_RFO_REG_OFFSET 0x18+XIIC_REG_OFFSET /* Rx FIFO Occupancy */ -#define XIIC_TBA_REG_OFFSET 0x1C+XIIC_REG_OFFSET /* 10 Bit Address reg */ -#define XIIC_RFD_REG_OFFSET 0x20+XIIC_REG_OFFSET /* Rx FIFO Depth reg */ - -/* Control Register masks */ - -#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ -#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ -#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ -#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ -#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ -#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ -#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ - -/* Status Register masks */ - -#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ -#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ -#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ -#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ -#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ -#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ -#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ - -/* IPIF Interrupt Status Register masks Interrupt occurs when... */ - -#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ -#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete*/ -#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ -#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level*/ -#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ -#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ -#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ -#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ - -/* IPIF Device Interrupt Register masks */ - -#define XIIC_IPIF_IIC_MASK 0x00000004UL /* 1=inter enabled */ -#define XIIC_IPIF_ERROR_MASK 0x00000001UL /* 1=inter enabled */ -#define XIIC_IPIF_INTER_ENABLE_MASK (XIIC_IPIF_IIC_MASK | \ - XIIC_IPIF_ERROR_MASK) - -#define XIIC_TX_ADDR_SENT 0x00 -#define XIIC_TX_ADDR_MSTR_RECV_MASK 0x02 - -/* The following constants specify the depth of the FIFOs */ - -#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ -#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ - -/* The following constants specify groups of interrupts that are typically - * enabled or disables at the same time - */ -#define XIIC_TX_INTERRUPTS \ - (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | \ - XIIC_INTR_TX_HALF_MASK) - -#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) - -/* The following constants are used with the following macros to specify the - * operation, a read or write operation. - */ -#define XIIC_READ_OPERATION 1 -#define XIIC_WRITE_OPERATION 0 - -/* The following constants are used with the transmit FIFO fill function to - * specify the role which the IIC device is acting as, a master or a slave. - */ -#define XIIC_MASTER_ROLE 1 -#define XIIC_SLAVE_ROLE 0 - -/**************************** Type Definitions ******************************/ - - -/***************** Macros (Inline Functions) Definitions ********************/ - - -/************************** Function Prototypes *****************************/ - -unsigned XIic_Recv(u32 BaseAddress, u8 Address, - u8 *BufferPtr, unsigned ByteCount); - -unsigned XIic_Send(u32 BaseAddress, u8 Address, - u8 *BufferPtr, unsigned ByteCount); - -#endif /* end of protection macro */ diff --git a/board/xm250/Makefile b/board/xm250/Makefile deleted file mode 100644 index 1b0a3f0..0000000 --- a/board/xm250/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := xm250.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/xm250/config.mk b/board/xm250/config.mk deleted file mode 100644 index 8ce0c48..0000000 --- a/board/xm250/config.mk +++ /dev/null @@ -1,35 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MicroSys XM250 board: -# - - -# This is the address where U-Boot lives in flash: -#TEXT_BASE = 0 - -# FIXME: armboot does only work correctly when being compiled -# for the addresses _after_ relocation to RAM!! Otherwhise the -# .bss segment is assumed in flash... -TEXT_BASE = 0xA3F80000 diff --git a/board/xm250/flash.c b/board/xm250/flash.c deleted file mode 100644 index aab47a0..0000000 --- a/board/xm250/flash.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -/* Intel-compatible flash ID */ -#define INTEL_COMPAT 0x00890089 -#define INTEL_ALT 0x00B000B0 - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x00100010 -#define INTEL_ERASE 0x00200020 -#define INTEL_CLEAR 0x00500050 -#define INTEL_LOCKBIT 0x00600060 -#define INTEL_PROTECT 0x00010001 -#define INTEL_STATUS 0x00700070 -#define INTEL_READID 0x00900090 -#define INTEL_CONFIRM 0x00D000D0 -#define INTEL_RESET 0xFFFFFFFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x00800080 -#define INTEL_OK 0x00800080 - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured to many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 32 MB */ - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int i; - int rc = 0; - vu_long *addr = (vu_long *)(info->start[sector]); - int flag = disable_interrupts(); - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } - else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - reset_timer_masked (); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - */ - if (!prot) - { - for (i = 0; i < info->sector_count; i++) - { - if (info->protect[i]) - { - reset_timer_masked (); - addr = (vu_long *)(info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) - { - if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) - { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - } - } - } - - if (flag) - enable_interrupts(); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} diff --git a/board/xm250/lowlevel_init.S b/board/xm250/lowlevel_init.S deleted file mode 100644 index 2ebd395..0000000 --- a/board/xm250/lowlevel_init.S +++ /dev/null @@ -1,519 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm -/* - .macro SET_LED val - ldr r6, =CRADLE_LED_CLR_REG - ldr r7, =0 - str r7, [r6] - ldr r6, =CRADLE_LED_SET_REG - ldr r7, =\val - str r7, [r6] - .endm -*/ - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - - /* Set up GPIO pins first */ - - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GRER0 - ldr r1, =CFG_GRER0_VAL - str r1, [r0] - - ldr r0, =GRER1 - ldr r1, =CFG_GRER1_VAL - str r1, [r0] - - ldr r0, =GRER2 - ldr r1, =CFG_GRER2_VAL - str r1, [r0] - - ldr r0, =GFER0 - ldr r1, =CFG_GFER0_VAL - str r1, [r0] - - ldr r0, =GFER1 - ldr r1, =CFG_GFER1_VAL - str r1, [r0] - - ldr r0, =GFER2 - ldr r1, =CFG_GFER2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - /* enable GPIO pins */ - ldr r0, =PSSR - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - - /* SET_LED 1 */ - - ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */ - ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */ - str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */ - ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */ - - -/********************************************************************* - * Initlialize Memory Controller - * - * See PXA250 Operating System Developer's Guide - * - * pause for 200 uSecs- allow internal clocks to settle - * *Note: only need this if hard reset... doing it anyway for now - */ - - @ Step 1 - @ ---- Wait 200 usec - ldr r3, =OSCR @ reset the OS Timer Count to zero - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - /* SET_LED 2 */ - -mem_init: - @ get memory controller base address - ldr r1, =MEMC_BASE - - -@**************************************************************************** -@ Step 2 -@ - - @ Step 2a - @ write msc0, read back to ensure data latches - @ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] - - @ write msc1 - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - @ write msc2 - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - @ Step 2b - @ write mecr - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - - @ write mcmem0 - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - - @ write mcmem1 - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - - @ write mcatt0 - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - - @ write mcatt1 - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - - @ write mcio0 - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - - @ write mcio1 - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - - /*SET_LED 3 */ - - @ Step 2c - @ fly-by-dma is defeatured on this part - @ write flycnfg - @ldr r2, =CFG_FLYCNFG_VAL - @str r2, [r1, #FLYCNFG_OFFSET] - -/* FIXME Does this sequence really make sense */ -#ifdef REDBOOT_WAY - @ Step 2d - @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL - - @ extract DRI field (we need a valid DRI field) - @ - ldr r2, =0xFFF - - @ valid DRI field in r3 - @ - and r3, r3, r2 - - @ get the reset state of MDREFR - @ - ldr r4, [r1, #MDREFR_OFFSET] - - @ clear the DRI field - @ - bic r4, r4, r2 - - @ insert the valid DRI field loaded above - @ - orr r4, r4, r3 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ *Note: preserve the mdrefr value in r4 * - - /*SET_LED 4 */ - -@**************************************************************************** -@ Step 3 -@ -@ NO SRAM - - mov pc, r10 - - -@**************************************************************************** -@ Step 4 -@ - - @ Assumes previous mdrefr value in r4, if not then read current mdrefr - - @ clear the free-running clock bits - @ (clear K0Free, K1Free, K2Free - @ - bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000) - - @ set K0RUN for CPLD clock - @ - orr r4, r4, #0x00002000 - - @ set K1RUN if bank 0 installed - @ - orr r4, r4, #0x00010000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - @ deassert SLFRSH - @ - bic r4, r4, #0x00400000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ assert E1PIN - @ - orr r4, r4, #0x00008000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - nop - nop -#else - @ Step 2d - @ get the mdrefr settings - ldr r4, =CFG_MDREFR_VAL - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ Step 4 - - @ set K0RUN for FLASH clock - @ - orr r4, r4, #0x00002000 - - @ set K1RUN for bank DRAM 0 - @ - orr r4, r4, #0x00010000 - - @ set K2RUN for bank PLD - @ - orr r4, r4, #0x00040000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - @ deassert SLFRSH - @ - bic r4, r4, #0x00400000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - - @ assert E1PIN - @ - orr r4, r4, #0x00008000 - - @ write back mdrefr - @ - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - nop - nop -#endif - - @ Step 4d - @ fetch platform value of mdcnfg - @ - ldr r2, =CFG_MDCNFG_VAL - - @ disable all sdram banks - @ - bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) - bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3) - - @ program banks 0/1 for bus width - @ - bic r2, r2, #MDCNFG_DWID0 @0=32-bit - - @ write initial value of mdcnfg, w/o enabling sdram banks - @ - str r2, [r1, #MDCNFG_OFFSET] - - @ Step 4e - @ pause for 200 uSecs - @ - ldr r3, =OSCR @ reset the OS Timer Count to zero - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - /*SET_LED 5 */ - - /* Why is this here??? */ - mov r0, #0x78 @turn everything off - mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.) - - @ Step 4f - @ Access memory *not yet enabled* for CBR refresh cycles (8) - @ - CBR is generated for all banks - - ldr r2, =CFG_DRAM_BASE - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - - @ Step 4g - @get memory controller base address - @ - ldr r1, =MEMC_BASE - - @fetch current mdcnfg value - @ - ldr r3, [r1, #MDCNFG_OFFSET] - - @enable sdram bank 0 if installed (must do for any populated bank) - @ - orr r3, r3, #MDCNFG_DE0 - - @write back mdcnfg, enabling the sdram bank(s) - @ - str r3, [r1, #MDCNFG_OFFSET] - - @ Step 4h - @ write mdmrs - @ - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - @ Done Memory Init - - /*SET_LED 6 */ - - @******************************************************************** - @ Disable (mask) all interrupts at the interrupt controller - @ - - @ clear the interrupt level register (use IRQ, not FIQ) - @ - mov r1, #0 - ldr r2, =ICLR - str r1, [r2] - - @ Set interrupt mask register - @ - ldr r1, =CFG_ICMR_VAL - ldr r2, =ICMR - str r1, [r2] - - @ ******************************************************************** - @ Disable the peripheral clocks, and set the core clock - @ - - @ Turn Off ALL on-chip peripheral clocks for re-configuration - @ - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - @ set core clocks - @ - ldr r2, =CFG_CCCR_VAL - ldr r1, =CCCR - str r2, [r1] - -#ifdef ENABLE32KHZ - @ enable the 32Khz oscillator for RTC and PowerManager - @ - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - @ NOTE: spin here until OSCC.OOK get set, - @ meaning the PLL has settled. - @ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#endif - - @ Turn on needed clocks - @ - ldr r1, =CKEN - ldr r2, =CFG_CKEN_VAL - str r2, [r1] - - /*SET_LED 7 */ - -/* Is this needed???? */ -#define NODEBUG -#ifdef NODEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ - -#endif - - /*SET_LED 8 */ - - mov pc, r10 - -@ End lowlevel_init diff --git a/board/xm250/u-boot.lds b/board/xm250/u-boot.lds deleted file mode 100644 index db83875..0000000 --- a/board/xm250/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c deleted file mode 100644 index ef5e9da..0000000 --- a/board/xm250/xm250.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -/* local prototypes */ - -inline void sleep (int i); - -inline void -/**********************************************************/ -sleep (int i) -/**********************************************************/ -{ - while (i--) { - udelay (1000000); - } -} - -/* - * Miscelaneous platform dependent initialisations - */ - -int -/**********************************************************/ -board_post_init (void) -/**********************************************************/ -{ - return (0); -} - -int -/**********************************************************/ -board_init (void) -/**********************************************************/ -{ - DECLARE_GLOBAL_DATA_PTR; - /* arch number of MicroSys XM250 */ - gd->bd->bi_arch_number = MACH_TYPE_XM250; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int -/**********************************************************/ -dram_init (void) -/**********************************************************/ -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; - - return (0); -} diff --git a/board/xpedite1k/Makefile b/board/xpedite1k/Makefile deleted file mode 100644 index c5c0915..0000000 --- a/board/xpedite1k/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2002-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS = $(BOARD).o -OBJS +=flash.o -SOBJS = init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/board/xpedite1k/config.mk b/board/xpedite1k/config.mk deleted file mode 100644 index e42b273..0000000 --- a/board/xpedite1k/config.mk +++ /dev/null @@ -1,42 +0,0 @@ -# -# (C) Copyright 2002-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# XES XPedite1000 PPC440GX -# - -ifeq ($(ramsym),1) -TEXT_BASE = 0x07FD0000 -else -TEXT_BASE = 0xFFF80000 -endif - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 -endif diff --git a/board/xpedite1k/flash.c b/board/xpedite1k/flash.c deleted file mode 100644 index ce5d4e1..0000000 --- a/board/xpedite1k/flash.c +++ /dev/null @@ -1,607 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu - * Add support for Am29F016D and dynamic switch setting. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -/* - * Ported to XPedite1000, 1/2 mb boot flash only - * Travis B. Sawyer, - */ - -#include -#include -#include - - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -#define BOOT_SMALL_FLASH_VAL 4 -#define FLASH_ONBD_N_VAL 2 -#define FLASH_SRAM_SEL_VAL 1 - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { - {0xfff80000}, /* 0:000: configuraton 3 */ - {0xfff90000}, /* 1:001: configuraton 4 */ - {0xfffa0000}, /* 2:010: configuraton 7 */ - {0xfffb0000}, /* 3:011: configuraton 8 */ - {0xfffc0000}, /* 4:100: configuraton 1 */ - {0xfffd0000}, /* 5:101: configuraton 2 */ - {0xfffe0000}, /* 6:110: configuraton 5 */ - {0xffff0000} /* 7:111: configuraton 6 */ -}; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - - -#ifdef CONFIG_XPEDITE1K -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char -#endif - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i=0; iflash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMD016: printf ("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; - } - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); - - /* Write auto select command: read Manufacturer ID */ - udelay(10000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - udelay(1000); - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - udelay(1000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - udelay(1000); - -#ifdef CONFIG_ADCIOP - value = addr2[2]; -#else - value = addr2[0]; -#endif - - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - -#ifdef CONFIG_ADCIOP - value = addr2[0]; /* device ID */ - debug ("\ndev_code=%x\n", value); -#else - value = addr2[1]; /* device ID */ -#endif - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; /* => 512 kb */ - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040) || - (info->flash_id == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ -#ifdef CONFIG_ADCIOP - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr2[4] & 1; -#else - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; -#endif - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { -#if 0 /* test-only */ -#ifdef CONFIG_ADCIOP - addr2 = (volatile unsigned char *)info->start[0]; - addr2[ADDR0] = 0xAA; - addr2[ADDR1] = 0x55; - addr2[ADDR0] = 0xF0; /* reset bank */ -#else - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ -#endif -#else /* test-only */ - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ -#endif /* test-only */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - printf("Erasing sector %p\n", addr2); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7(info, l_sect); - -DONE: -#endif - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/xpedite1k/init.S b/board/xpedite1k/init.S deleted file mode 100644 index 6cb20e4..0000000 --- a/board/xpedite1k/init.S +++ /dev/null @@ -1,96 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include -#include - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) - tlbtab_end diff --git a/board/xpedite1k/u-boot.lds b/board/xpedite1k/u-boot.lds deleted file mode 100644 index 0f08637..0000000 --- a/board/xpedite1k/u-boot.lds +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFFFF000 : - { - cpu/ppc4xx/start.o (.bootpg) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/xpedite1k/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/xpedite1k/u-boot.lds.debug b/board/xpedite1k/u-boot.lds.debug deleted file mode 100644 index 5066326..0000000 --- a/board/xpedite1k/u-boot.lds.debug +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - cpu/ppc4xx/start.o (.text) - board/xpedite1k/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* common/environment.o(.text) */ - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c deleted file mode 100644 index bb36c96..0000000 --- a/board/xpedite1k/xpedite1k.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Copyright (C) 2003 Travis B. Sawyer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -long int fixed_sdram (void); - -int board_early_init_f(void) -{ - unsigned long sdrreg; - /* TBS: Setup the GPIO access for the user LEDs */ - mfsdr(sdr_pfc0, sdrreg); - mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00); - out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); - LED0_OFF(); - LED1_OFF(); - LED2_OFF(); - LED3_OFF(); - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - - /* set the bus controller */ - mtebc (pb0ap, 0x04055200); /* FLASH/SRAM */ - mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ - mtebc (pb1ap, 0x04055200); /* FLASH/SRAM */ - mtebc (pb1cr, 0xfe098000); /* BAS=0xff8 16MB R/W 8-bit */ - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000003); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe00); /* per ref-board manual */ - mtdcr (uic0tr, 0x01c00000); /* per ref-board manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffc0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ff8000); /* per ref-board manual */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); /* */ - mtdcr (uicb0tr, 0x00000000); /* */ - mtdcr (uicb0vr, 0x00000001); /* */ - - LED0_ON(); - - - return 0; -} - -int checkboard (void) -{ - printf ("Board: XES XPedite1000 440GX\n"); - - return (0); -} - - -long int initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (0); -#else - dram_size = fixed_sdram (); -#endif - return dram_size; -} - - -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay (400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram (mem_mcsts, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) -int pci_pre_init(struct pci_controller * hose ) -{ - unsigned long strap; - /* See if we're supposed to setup the pci */ - mfsdr(sdr_sdstp1, strap); - if ((strap & 0x00010000) == 0) { - return (0); - } - -#if defined(CFG_PCI_FORCE_PCI_CONV) - /* Setup System Device Register PCIX0_XCR */ - mfsdr(sdr_xcr, strap); - strap &= 0x0f000000; - mtsdr(sdr_xcr, strap); -#endif - return 1; -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - DECLARE_GLOBAL_DATA_PTR; - - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIX0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); - - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - - -/************************************************************************* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - return ((in32(CFG_GPIO_BASE + 0x1C) & 0x00000800) == 0); -} -#endif /* defined(CONFIG_PCI) */ - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - - return (ctrlc()); -} - -void post_word_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)(CFG_POST_WORD_ADDR); - - *save_addr = a; -} - -ulong post_word_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)(CFG_POST_WORD_ADDR); - - return *save_addr; -} -#endif - -/*----------------------------------------------------------------------------- - * board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM - *----------------------------------------------------------------------------- - */ -static int enetaddr_num = 0; -void board_get_enetaddr (uchar * enet) -{ - int i; - unsigned char buff[0x100], *cp; - - /* Initialize I2C */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x50, 0, 1, buff, 0x100); - - if (enetaddr_num == 0) { - cp = &buff[0xF4]; - enetaddr_num = 1; - } - else - cp = &buff[0xFA]; - - for (i = 0; i < 6; i++,cp++) - enet[i] = *cp; - - printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n", - enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]); - -} diff --git a/board/xsengine/Makefile b/board/xsengine/Makefile deleted file mode 100644 index ed1464a..0000000 --- a/board/xsengine/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := xsengine.o flash.o -SOBJS := lowlevel_init.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/xsengine/config.mk b/board/xsengine/config.mk deleted file mode 100644 index 148c519..0000000 --- a/board/xsengine/config.mk +++ /dev/null @@ -1 +0,0 @@ -TEXT_BASE = 0xA3F80000 diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c deleted file mode 100644 index 2b9afc7..0000000 --- a/board/xsengine/flash.c +++ /dev/null @@ -1,470 +0,0 @@ -/* - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define SWAP(x) __swab32(x) - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Functions */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((long *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((long *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors */ - flash_protect ( FLAG_PROTECT_SET,CFG_FLASH_BASE,CFG_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] ); - flash_protect ( FLAG_PROTECT_SET,CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) return; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n"); - break; - case FLASH_S29GL064M: printf ("S29GL064M (64Mbit, top boot sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case AMD_MANUFACT: - debug ("Manufacturer: AMD\n"); - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - debug ("Manufacturer: FUJITSU\n"); - info->flash_id = FLASH_MAN_FUJ; - break; - default: - debug ("Manufacturer: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { - - case AMD_ID_MIRROR: - debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", - addr[14], addr[15]); - switch(addr[14]) { - case AMD_ID_LV640U_2: - if (addr[15] != AMD_ID_LV640U_3) { - debug ("Chip: AMLV640U -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - debug ("Chip: AMLV640U\n"); - info->flash_id += FLASH_AMLV640U; - info->sector_count = 128; - info->size = 0x01000000; - } - break; /* => 16 MB */ - case AMD_ID_GL064MT_2: - if (addr[15] != AMD_ID_GL064MT_3) { - debug ("Chip: S29GL064M-R3 -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - debug ("Chip: S29GL064M-R3\n"); - info->flash_id += FLASH_S29GL064M; - info->sector_count = 128; - info->size = 0x01000000; - } - break; /* => 16 MB */ - default: - debug ("Chip: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - break; - } - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - switch (value) { - case AMD_ID_MIRROR: - switch (info->flash_id & FLASH_TYPEMASK) { - /* only known types here - no default */ - case FLASH_AMLV128U: - case FLASH_AMLV640U: - case FLASH_AMLV320U: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x20000; - } - break; - case FLASH_AMLV320B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - } - break; - - default: - return (0); - break; - } - -#if 0 - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } -#endif - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 100000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, SWAP(data))) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, SWAP(data))) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, SWAP(data))); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/xsengine/lowlevel_init.S b/board/xsengine/lowlevel_init.S deleted file mode 100644 index 309faab..0000000 --- a/board/xsengine/lowlevel_init.S +++ /dev/null @@ -1,221 +0,0 @@ -#include -#include -#include - -DRAM_SIZE: .long CFG_DRAM_SIZE - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - -/* ---- GPIO INITIALISATION ---- */ -/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */ - - /* General purpose set registers */ - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - /* General purpose clear registers */ - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - /* General rising edge registers */ - ldr r0, =GRER0 - ldr r1, =CFG_GRER0_VAL - str r1, [r0] - ldr r0, =GRER1 - ldr r1, =CFG_GRER1_VAL - str r1, [r0] - ldr r0, =GRER2 - ldr r1, =CFG_GRER2_VAL - str r1, [r0] - - /* General falling edge registers */ - ldr r0, =GFER0 - ldr r1, =CFG_GFER0_VAL - str r1, [r0] - ldr r0, =GFER1 - ldr r1, =CFG_GFER1_VAL - str r1, [r0] - ldr r0, =GFER2 - ldr r1, =CFG_GFER2_VAL - str r1, [r0] - - /* General edge detect registers */ - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - /* General alternate function registers */ - ldr r0, =GAFR0_L /* [0:15] */ - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - ldr r0, =GAFR0_U /* [31:16] */ - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - ldr r0, =GAFR1_L /* [47:32] */ - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - ldr r0, =GAFR1_U /* [63:48] */ - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - ldr r0, =GAFR2_L /* [79:64] */ - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - ldr r0, =GAFR2_U /* [80] */ - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - /* General purpose direction registers */ - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - /* Power manager sleep status */ - ldr r0, =PSSR - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - -/* ---- MEMORY INITIALISATION ---- */ -/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */ -/* pause for 200 uSecs- allow internal clocks to settle */ - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: -/* get memory controller base address */ - ldr r1, =MEMC_BASE - -/* ---- FLASH INITIALISATION ---- */ -/* Write MSC0 and read back to ensure data change is accepted by cpu */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] - -/* ---- SDRAM INITIALISATION ---- */ -/* get the MDREFR settings */ - ldr r2, =CFG_MDREFR_VAL - str r2, [r1, #MDREFR_OFFSET] - -/* fetch platform value of MDCNFG */ - ldr r2, =CFG_MDCNFG_VAL - -/* disable all sdram banks */ - bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) - bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3) - -/* write initial value of MDCNFG, w/o enabling sdram banks */ - str r2, [r1, #MDCNFG_OFFSET] - -/* pause for 200 uSecs */ - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* about 200 usec */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -/* Access memory *not yet enabled* for CBR refresh cycles (8) */ -/* CBR is generated for all banks */ - - ldr r2, =CFG_DRAM_BASE - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - str r2, [r2] - -/* get memory controller base address */ - ldr r2, =MEMC_BASE - -/* Enable SDRAM bank 0 in MDCNFG register */ - ldr r2, [r1, #MDCNFG_OFFSET] - orr r2, r2, #MDCNFG_DE0 - str r2, [r1, #MDCNFG_OFFSET] - -/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */ - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - -/* ---- INTERRUPT INITIALISATION ---- */ -/* Disable (mask) all interrupts at the interrupt controller */ -/* clear the interrupt level register (use IRQ, not FIQ) */ - mov r1, #0 - ldr r2, =ICLR - str r1, [r2] - -/* Set interrupt mask register */ - ldr r1, =CFG_ICMR_VAL - ldr r2, =ICMR - str r1, [r2] - -/* ---- CLOCK INITIALISATION ---- */ -/* Disable the peripheral clocks, and set the core clock */ - -/* Turn Off ALL on-chip peripheral clocks for re-configuration */ - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - -/* set core clocks */ - ldr r2, =CFG_CCCR_VAL - ldr r1, =CCCR - str r2, [r1] - -#ifdef ENABLE32KHZ -/* enable the 32Khz oscillator for RTC and PowerManager */ - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - -/* NOTE: spin here until OSCC.OOK get set, meaning the PLL has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#endif - -/* Turn on needed clocks */ - ldr r1, =CKEN - ldr r2, =CFG_CKEN_VAL - str r2, [r1] - - mov pc, r10 diff --git a/board/xsengine/u-boot.lds b/board/xsengine/u-boot.lds deleted file mode 100644 index db83875..0000000 --- a/board/xsengine/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c deleted file mode 100644 index a9919db..0000000 --- a/board/xsengine/xsengine.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number */ - gd->bd->bi_arch_number = MACH_TYPE_XSENGINE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_post_init (void) -{ - setenv ("stdout", "serial"); - setenv ("stderr", "serial"); - return 0; -} - -int dram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} diff --git a/board/zpc1900/Makefile b/board/zpc1900/Makefile deleted file mode 100644 index 8b10993..0000000 --- a/board/zpc1900/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/zpc1900/config.mk b/board/zpc1900/config.mk deleted file mode 100644 index 1072dc7..0000000 --- a/board/zpc1900/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Modified by, Yuli Barcohen, Arabella Software Ltd. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# ZPC.1900 board -# - -TEXT_BASE = 0xFFE00000 diff --git a/board/zpc1900/u-boot.lds b/board/zpc1900/u-boot.lds deleted file mode 100644 index 18c4b46..0000000 --- a/board/zpc1900/u-boot.lds +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Yuli Barcohen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc8260/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c deleted file mode 100644 index 6d16a0d..0000000 --- a/board/zpc1900/zpc1900.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 Arabella Software Ltd. - * Yuli Barcohen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN CLSN */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RENA */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT972 MDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT972 MDIO */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -#ifdef CFG_NVRAM_ACCESS_ROUTINE -void *nvram_read(void *dest, long src, size_t count) -{ - return memcpy(dest, (const void *)src, count); -} - -void nvram_write(long dest, const void *src, size_t count) -{ - vu_char *p1 = (vu_char *)(CFG_EEPROM + 0x1555); - vu_char *p2 = (vu_char *)(CFG_EEPROM + 0x0AAA); - vu_char *d = (vu_char *)dest; - const uchar *s = (const uchar *)src; - - /* Unprotect the EEPROM */ - *p1 = 0xAA; - *p2 = 0x55; - *p1 = 0x80; - *p1 = 0xAA; - *p2 = 0x55; - *p1 = 0x20; - udelay(10000); - - /* Write the data to the EEPROM */ - while (count--) { - *d++ = *s++; - while (*(d - 1) != *(s - 1)) - /* wait */; - } - - /* Protect the EEPROM */ - *p1 = 0xAA; - *p2 = 0x55; - *p1 = 0xA0; - udelay(10000); -} -#endif /* CFG_NVRAM_ACCESS_ROUTINE */ - -long int initdram(int board_type) -{ - vu_char *bcsr = (vu_char *)CFG_BCSR; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr; - uchar c = 0xFF; - long int msize = CFG_SDRAM_SIZE; - uint psdmr = CFG_PSDMR; - int i; - - if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */ - immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; - immap->im_siu_conf.sc_siumcr = - (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) - | SIUMCR_LBPC01; - } - -#ifndef CFG_RAMBOOT - immap->im_siu_conf.sc_ppc_acr = 0x03; - immap->im_siu_conf.sc_ppc_alrh = 0x30126745; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - - memctl->memc_mptpr = CFG_MPTPR; - -#ifdef CFG_LSDRAM_BASE - /* - Initialise local bus SDRAM only if the pins - are configured as local bus pins and not as PCI. - */ - if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { - memctl->memc_lsrt = CFG_LSRT; - memctl->memc_or4 = 0xFFC01480; - memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA; - ramaddr = (vu_char *)CFG_LSDRAM_BASE; - *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_MRW; - *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_RFEN; - } -#endif /* CFG_LSDRAM_BASE */ - - /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_or2 = 0xFC0028C0; - memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041; - /* - * The mode data for Mode Register Write command must appear on - * the address lines during a mode-set cycle. It is driven by - * the memory controller, in single PowerQUICC II mode, - * according to PSDMR[CL] and PSDMR[BL] fields. In - * 60x-compatible mode, software must drive the correct value on - * the address lines. BL=0 because for 64-bit port size burst - * length must be 4. - */ - ramaddr = (vu_char *)(CFG_SDRAM_BASE | - ((psdmr & PSDMR_CL_MSK) << 7) | 0x10); - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ - *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ - *ramaddr = c; -#endif /* CFG_RAMBOOT */ - - /* Return total 60x bus SDRAM size */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - vu_char *bcsr = (vu_char *)CFG_BCSR; - - printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40); - return 0; -} diff --git a/buffalomake.sh b/buffalomake.sh new file mode 100755 index 0000000..222d1ba --- /dev/null +++ b/buffalomake.sh @@ -0,0 +1,132 @@ +#!/bin/sh + +. /opt/cross.conf + +CROSS_ENV_PATH=${MARVELL_ARM_ENV2} +export PATH=${CROSS_ENV_PATH}/bin:${PATH} +IMAGE_DIR=../images + +build_lsvl() +{ + echo "*** LS-VL ***" + OUTPUT=buffalo_mvlsvl_6282 + RULE=${OUTPUT}_config + + make mrproper + make OTHERCFLAGS="" ${RULE} SPIBOOT=1 DDR3=1 + make -s + if [ -f u-boot-${OUTPUT}.bin ]; then + ./tools/doimage -T flash -D 0x600000 -E 0x660000 -R dramregs_533ddr3db_A_buf.txt \ + u-boot-${OUTPUT}.bin u-boot_lsvl.bin + cp u-boot_lsvl.bin $IMAGE_DIR + fi +} + +build_lswvl() +{ + echo "*** LS-WVL ***" + OUTPUT=buffalo_mvlswvl_6282 + RULE=${OUTPUT}_config + + make mrproper + make OTHERCFLAGS="" ${RULE} SPIBOOT=1 DDR3=1 NAND=1 + make -s + if [ -f u-boot-${OUTPUT}.bin ]; then + ./tools/doimage -T flash -D 0x600000 -E 0x660000 -R dramregs_533ddr3db_A_buf.txt \ + u-boot-${OUTPUT}.bin u-boot_lswvl.bin + cp u-boot_lswvl.bin $IMAGE_DIR + fi +} + +build_lsxhl() +{ + echo "*** LS-XHL/LS-XL ***" + OUTPUT=buffalo_mvlsxh_6281 + RULE=${OUTPUT}_config + + make mrproper + make OTHERCFLAGS="" ${RULE} SPIBOOT=1 LE=1 + make -s + if [ -f u-boot-${OUTPUT}.bin ]; then + ./tools/doimage -T flash -D 0x600000 -E 0x660000 -R dramregs_400mvlsxh_A.txt \ + u-boot-${OUTPUT}.bin u-boot_lsxh.bin + cp u-boot_lsxh.bin $IMAGE_DIR + + ./tools/doimage -T flash -D 0x600000 -E 0x660000 -R dramregs_300xl_A.txt \ + u-boot-${OUTPUT}.bin u-boot_lsxl.bin + cp u-boot_lsxl.bin $IMAGE_DIR + fi +} + +build_lswxl() +{ + echo "*** LS-WXL/LS-WSX ***" + OUTPUT=buffalo_mvwxl_6281 + RULE=${OUTPUT}_config + + make mrproper + make OTHERCFLAGS="" ${RULE} SPIBOOT=1 LE=1 NAND=1 + make -s + if [ -f u-boot-${OUTPUT}.bin ]; then + ./tools/doimage -T flash -D 0x600000 -E 0x660000 -R dramregs_300wxl_A.txt \ + u-boot-${OUTPUT}.bin u-boot_lswxl.bin + cp u-boot_lswxl.bin $IMAGE_DIR + fi +} + +build_lsxlv2() +{ + echo "*** LS-XL-V2 ***" + OUTPUT=buffalo_mvlsxlv2_6192 + RULE=${OUTPUT}_config + + make mrproper + make OTHERCFLAGS="" ${RULE} SPIBOOT=1 LE=1 NAND=1 + make -s + if [ -f u-boot-${OUTPUT}.bin ]; then + ./tools/doimage -T flash -D 0x600000 -E 0x660000 -R dramregs_lsxlv2_64mb.txt \ + u-boot-${OUTPUT}.bin u-boot_lsxlv2_64mb.bin + cp u-boot_lsxlv2_64mb.bin $IMAGE_DIR + + ./tools/doimage -T uart -D 0x600000 -E 0x660000 -R dramregs_lsxlv2_64mb.txt \ + u-boot-${OUTPUT}.bin u-boot_lsxlv2_64mb_uart.bin + cp u-boot_lsxlv2_64mb_uart.bin $IMAGE_DIR + + ./tools/doimage -T flash -D 0x600000 -E 0x660000 -R dramregs_lsxlv2_128mb.txt \ + u-boot-${OUTPUT}.bin u-boot_lsxlv2_128mb.bin + cp u-boot_lsxlv2_128mb.bin $IMAGE_DIR + + ./tools/doimage -T uart -D 0x600000 -E 0x660000 -R dramregs_lsxlv2_128mb.txt \ + u-boot-${OUTPUT}.bin u-boot_lsxlv2_128mb_uart.bin + cp u-boot_lsxlv2_128mb_uart.bin $IMAGE_DIR + fi +} + +[ -d $IMAGE_DIR ] || mkdir $IMAGE_DIR + +case $1 in + lsxhl|lsxl) + build_lsxhl + ;; + lswxl|lswsxl) + build_lswxl + ;; + lsvl) + build_lsvl + ;; + lswvl) + build_lswvl + ;; + lsxlv2) + build_lsxlv2 + ;; + all) + build_lsxhl + build_lswxl + build_lsvl + build_lswvl + build_lsxlv2 + ;; + *) + echo "Usage: `basename $0` " +esac diff --git a/common/.depend b/common/.depend new file mode 100644 index 0000000..0beba03 --- /dev/null +++ b/common/.depend @@ -0,0 +1,2752 @@ +main.o: main.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/watchdog.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/hush.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/post.h +ACEX1K.o: ACEX1K.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ACEX1K.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/altera.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/fpga.h +altera.o: altera.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + 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/opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/domain.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/usb.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/usb_defs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/scsi.h +virtex2.o: virtex2.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/virtex2.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/xilinx.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/fpga.h +xilinx.o: xilinx.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/virtex2.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/xilinx.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/fpga.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/spartan2.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/spartan3.h diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 8599a49..312696a 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -38,6 +38,8 @@ #include #endif +extern unsigned int whoAmI(void); + /*cmd_boot.c*/ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); @@ -140,7 +142,11 @@ static boot_os_Fcn do_bootm_lynxkdi; extern void lynxkdi_boot( image_header_t * ); #endif -image_header_t header; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) +image_header_t header[2]; +#else +image_header_t header[1]; +#endif ulong load_addr = CFG_LOAD_ADDR; /* Default Load Address */ @@ -154,7 +160,13 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int i, verify; char *name, *s; int (*appl)(int, char *[]); - image_header_t *hdr = &header; + unsigned int cpu = 0; + image_header_t *hdr; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + + hdr = &header[cpu]; s = getenv ("verify"); verify = (s && (*s == 'n')) ? 0 : 1; @@ -171,11 +183,11 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* Copy header so we can blank CRC field for re-calculation */ #ifdef CONFIG_HAS_DATAFLASH if (addr_dataflash(addr)){ - read_dataflash(addr, sizeof(image_header_t), (char *)&header); + read_dataflash(addr, sizeof(image_header_t), (char *)&header[cpu]); } else #endif - memmove (&header, (char *)addr, sizeof(image_header_t)); - + memmove (&header[cpu], (char *)addr, sizeof(image_header_t)); + if (ntohl(hdr->ih_magic) != IH_MAGIC) { #ifdef __I386__ /* correct image format not implemented yet - fake it */ if (fake_header(hdr, (void*)addr, -1) != NULL) { @@ -195,7 +207,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } SHOW_BOOT_PROGRESS (2); - data = (ulong)&header; + data = (ulong)&header[cpu]; len = sizeof(image_header_t); checksum = ntohl(hdr->ih_hcrc); @@ -222,7 +234,6 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) data = addr + sizeof(image_header_t); len = ntohl(hdr->ih_size); - if (verify) { puts (" Verifying Checksum ... "); if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) { @@ -519,11 +530,17 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, char *s; bd_t *kbd; void (*kernel)(bd_t *, ulong, ulong, ulong, ulong); - image_header_t *hdr = &header; + unsigned int cpu = 0; + image_header_t *hdr; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + #ifdef CONFIG_OF_FLAT_TREE char *of_flat_tree; #endif + hdr = &header[cpu]; if ((s = getenv ("initrd_high")) != NULL) { /* a value of "no" or a similar string will act like 0, * turning the "load high" feature off. This is intentional. @@ -567,8 +584,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, cmdline = (char *)((sp - CFG_BARGSIZE) & ~0xF); kbd = (bd_t *)(((ulong)cmdline - sizeof(bd_t)) & ~0xF); - if ((s = getenv("bootargs")) == NULL) - s = ""; + if ((s = getenv("bootargs")) == NULL) s = ""; strcpy (cmdline, s); @@ -578,6 +594,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, *kbd = *(gd->bd); #ifdef DEBUG + printf ("## cmdline is %s\n", cmdline); printf ("## cmdline at 0x%08lX ... 0x%08lX\n", cmd_start, cmd_end); do_bdinfo (NULL, 0, 0, NULL); @@ -619,7 +636,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, printf ("## Loading RAMDisk Image at %08lx ...\n", addr); /* Copy header so we can blank CRC field for re-calculation */ - memmove (&header, (char *)addr, sizeof(image_header_t)); + memmove (&header[cpu], (char *)addr, sizeof(image_header_t)); if (hdr->ih_magic != IH_MAGIC) { puts ("Bad Magic Number\n"); @@ -627,7 +644,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, do_reset (cmdtp, flag, argc, argv); } - data = (ulong)&header; + data = (ulong)&header[cpu]; len = sizeof(image_header_t); checksum = hdr->ih_hcrc; @@ -839,6 +856,16 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, } #endif /* CONFIG_PPC */ +#ifdef CONFIG_MARVELL +char extraBootArgs[200]; + +/* NetBSD Stage-2 Loader Parameters: +* r6: boot args string +*/ +#define DECLARE_NETBSD_CMDLINE +register volatile char *cmdline asm ("r6"); +#endif + static void do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], @@ -847,14 +874,24 @@ do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, int verify) { DECLARE_GLOBAL_DATA_PTR; - - image_header_t *hdr = &header; - +#ifdef CONFIG_MARVELL + DECLARE_NETBSD_CMDLINE; +#else + char *cmdline; +#endif + image_header_t *hdr; + unsigned int cpu = 0; + bd_t *bd = gd->bd; + void (*loader)(bd_t *, image_header_t *, char *, char *); image_header_t *img_addr; char *consdev; - char *cmdline; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + + hdr = &header[cpu]; /* * Booting a (NetBSD) kernel image @@ -887,9 +924,27 @@ do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, if (argc > 2) { ulong len; int i; +#ifdef CONFIG_MARVELL + unsigned int mvBoardIdGet(void); + char buf[30]; + sprintf(extraBootArgs ,"boardId=%x",mvBoardIdGet()); + + for (i = 0; i < 4; i++) + { + sprintf(buf ," dram%d_start=%x",i, bd->bi_dram[i].start); + strcat(extraBootArgs, buf); + sprintf(buf ," dram%d_size=%x",i, bd->bi_dram[i].size); + strcat(extraBootArgs, buf); + } + +#endif for (i=2, len=0 ; i 2) cmdline[len++] = ' '; + strcpy (&cmdline[len], extraBootArgs); + len += strlen (extraBootArgs); +#endif + + } else if ((cmdline = getenv("bootargs")) == NULL) { cmdline = ""; } - loader = (void (*)(bd_t *, image_header_t *, char *, char *)) hdr->ih_ep; + loader = (void (*)(bd_t *, image_header_t *, char *, char *))ntohl(hdr->ih_ep); printf ("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n", (ulong)loader); @@ -938,7 +1001,14 @@ do_bootm_artos (cmd_tbl_t *cmdtp, int flag, int i, j, nxt, len, envno, envsz; bd_t *kbd; void (*entry)(bd_t *bd, char *cmdline, char **fwenv, ulong top); - image_header_t *hdr = &header; + unsigned int cpu = 0; + image_header_t *hdr; + +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + + hdr = &header[cpu]; /* * Booting an ARTOS kernel image + application @@ -1017,7 +1087,16 @@ int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int rcode = 0; #ifndef CFG_HUSH_PARSER - if (run_command (getenv ("bootcmd"), flag) < 0) rcode = 1; +#if defined(CONFIG_MARVELL) && (defined(DUAL_OS_78200) || defined(DUAL_OS_SHARED_MEM_78200)) + if (whoAmI() == 1) + { + if (run_command (getenv ("bootcmd2"), flag) < 0) rcode = 1; + } + else +#endif + { + if (run_command (getenv ("bootcmd"), flag) < 0) rcode = 1; + } #else if (parse_string_outer(getenv("bootcmd"), FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) != 0 ) rcode = 1; @@ -1046,6 +1125,10 @@ int do_iminfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int arg; ulong addr; int rcode=0; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif if (argc < 2) { return image_info (load_addr); @@ -1061,19 +1144,23 @@ int do_iminfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) static int image_info (ulong addr) { ulong data, len, checksum; - image_header_t *hdr = &header; - + image_header_t *hdr; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + hdr = &header[cpu]; printf ("\n## Checking Image at %08lx ...\n", addr); /* Copy header so we can blank CRC field for re-calculation */ - memmove (&header, (char *)addr, sizeof(image_header_t)); + memmove (&header[cpu], (char *)addr, sizeof(image_header_t)); if (ntohl(hdr->ih_magic) != IH_MAGIC) { puts (" Bad Magic Number\n"); return 1; } - data = (ulong)&header; + data = (ulong)&header[cpu]; len = sizeof(image_header_t); checksum = ntohl(hdr->ih_hcrc); @@ -1120,7 +1207,11 @@ int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int i, j; image_header_t *hdr; ulong data, len, checksum; - + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + for (i=0, info=&flash_info[0]; iflash_id == FLASH_UNKNOWN) goto next_bank; @@ -1131,12 +1222,12 @@ int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) goto next_sector; /* Copy header so we can blank CRC field for re-calculation */ - memmove (&header, (char *)hdr, sizeof(image_header_t)); + memmove (&header[cpu], (char *)hdr, sizeof(image_header_t)); - checksum = ntohl(header.ih_hcrc); - header.ih_hcrc = 0; + checksum = ntohl(header[cpu].ih_hcrc); + header[cpu].ih_hcrc = 0; - if (crc32 (0, (uchar *)&header, sizeof(image_header_t)) + if (crc32 (0, (uchar *)&header[cpu], sizeof(image_header_t)) != checksum) goto next_sector; @@ -1189,7 +1280,6 @@ print_image_hdr (image_header_t *hdr) printf (" Load Address: %08x\n" " Entry Point: %08x\n", ntohl(hdr->ih_load), ntohl(hdr->ih_ep)); - if (hdr->ih_type == IH_TYPE_MULTI) { int i; ulong len; @@ -1361,7 +1451,13 @@ do_bootm_rtems (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong addr, ulong *len_ptr, int verify) { DECLARE_GLOBAL_DATA_PTR; - image_header_t *hdr = &header; + unsigned int cpu = 0; + image_header_t *hdr; +#ifdef MV78XX0 + cpu = whoAmI(); +#endif + + hdr = &header[cpu]; void (*entry_point)(bd_t *); entry_point = (void (*)(bd_t *)) hdr->ih_ep; @@ -1384,9 +1480,14 @@ static void do_bootm_vxworks (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong addr, ulong *len_ptr, int verify) { - image_header_t *hdr = &header; + unsigned int cpu = 0; + image_header_t *hdr; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif char str[80]; + hdr = &header[cpu]; sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */ setenv("loadaddr", str); do_bootvx(cmdtp, 0, 0, NULL); @@ -1396,9 +1497,14 @@ static void do_bootm_qnxelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong addr, ulong *len_ptr, int verify) { - image_header_t *hdr = &header; + image_header_t *hdr; char *local_args[2]; char str[16]; + unsigned int cpu = 0; +#ifdef MV78XX0 + cpu = whoAmI(); +#endif + hdr = &header[cpu]; sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */ local_args[0] = argv[0]; @@ -1415,7 +1521,11 @@ do_bootm_lynxkdi (cmd_tbl_t *cmdtp, int flag, ulong *len_ptr, int verify) { - lynxkdi_boot( &header ); + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + lynxkdi_boot( &header[cpu] ); } #endif /* CONFIG_LYNXKDI */ diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c index d15a412..c75ccba 100644 --- a/common/cmd_eeprom.c +++ b/common/cmd_eeprom.c @@ -184,7 +184,7 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt #ifdef CONFIG_SPI spi_read (addr, alen, buffer, len); #else - if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0) + if (i2c_read (0, addr[0], offset, alen-1, buffer, len) != 0) rcode = 1; #endif buffer += len; @@ -294,7 +294,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn addr_void[0] |= CFG_I2C_EEPROM_ADDR; #endif contr_reg[0] = 0xff; - if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) { + if (i2c_read (0, contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) { rcode = 1; } ctrl_reg_v = contr_reg[0]; @@ -309,21 +309,21 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn /* Set write enable latch. */ contr_reg[0] = 0x02; - if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) { + if (i2c_write (0, contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) { rcode = 1; } /* Set register write enable latch. */ contr_reg[0] = 0x06; - if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { + if (i2c_write (0, contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { rcode = 1; } /* Modify ctrl register. */ contr_reg[0] = ctrl_reg_v; - if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { + if (i2c_write (0, contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { rcode = 1; } @@ -337,7 +337,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn */ contr_reg[0] = 0; for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) { - if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0) + if (i2c_read (0, addr_void[0], addr_void[1], 1, contr_reg, 1) == 0) break; /* got ack */ #if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS) udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); @@ -355,14 +355,14 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn /* Set write enable latch. */ contr_reg[0] = 0x02; - if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { + if (i2c_write (0, contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) { rcode = 1; } } /* Write is enabled ... now write eeprom value. */ #endif - if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0) + if (i2c_write (0, addr[0], offset, alen-1, buffer, len) != 0) rcode = 1; #endif @@ -395,7 +395,11 @@ eeprom_probe (unsigned dev_addr, unsigned offset) chip |= dev_addr; /* insert device address */ - return (i2c_probe (chip)); +#if defined(CONFIG_MARVELL) && defined(MV78XX0) + return (i2c_probe (1, chip)); +#else + return (i2c_probe (0, chip)); +#endif } #endif diff --git a/common/cmd_elf.c b/common/cmd_elf.c index eccf2e9..d645bbf 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -139,7 +139,11 @@ int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ if ((tmp = getenv ("bootaddr")) == NULL) + #ifdef __ARM__ + bootaddr = 0x700; + #else bootaddr = 0x4200; + #endif else bootaddr = simple_strtoul (tmp, NULL, 16); diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c index 5db42f2..9b78408 100644 --- a/common/cmd_ext2.c +++ b/common/cmd_ext2.c @@ -200,7 +200,8 @@ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + if (cmdtp) + printf ("Usage:\n%s\n", cmdtp->usage); return(1); } @@ -264,6 +265,7 @@ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ext2fs_close(); return(1); } + if ((count < filelen) && (count != 0)) { filelen = count; } diff --git a/common/cmd_flash.c b/common/cmd_flash.c index 0aa4783..f6e3dd0 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -45,6 +45,10 @@ int find_dev_and_part(const char *id, struct mtd_device **dev, extern flash_info_t flash_info[]; /* info for FLASH chips */ +#if defined (CONFIG_MARVELL) +extern int mv_flash_real_protect_bank(flash_info_t *info, int prot); +#endif + /* * The user interface starts numbering for Flash banks with 1 * for historical reasons. @@ -586,6 +590,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("missing or unknown FLASH type\n"); return 1; } + for (i=0; isector_count; ++i) { #if defined(CFG_FLASH_PROTECTION) if (flash_real_protect(info, i, p)) @@ -594,7 +599,8 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #else info->protect[i] = p; #endif /* CFG_FLASH_PROTECTION */ - } + } + #if defined(CFG_FLASH_PROTECTION) if (!rcode) puts (" done\n"); diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index c543bb5..8f89018 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -92,6 +92,7 @@ /* Display values from last command. * Memory modify remembered values are different from display memory. */ +static uchar i2c_dp_last_channel; static uchar i2c_dp_last_chip; static uint i2c_dp_last_addr; static uint i2c_dp_last_alen; @@ -117,19 +118,20 @@ extern int cmd_get_data_size(char* arg, int default_size); int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - u_char chip; + u_char chip, channel; uint addr, alen, length; int j, nbytes, linebytes; /* We use the last specified parameters, unless new ones are * entered. */ + channel= i2c_dp_last_channel; chip = i2c_dp_last_chip; addr = i2c_dp_last_addr; alen = i2c_dp_last_alen; length = i2c_dp_last_length; - if (argc < 3) { + if (argc < 3) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } @@ -140,26 +142,27 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ alen = 1; + channel = simple_strtoul(argv[1], NULL, 16); /* * I2C chip address */ - chip = simple_strtoul(argv[1], NULL, 16); + chip = simple_strtoul(argv[2], NULL, 16); /* * I2C data address within the chip. This can be 1 or * 2 bytes long. Some day it might be 3 bytes long :-). */ - addr = simple_strtoul(argv[2], NULL, 16); + addr = simple_strtoul(argv[3], NULL, 16); alen = 1; for(j = 0; j < 8; j++) { - if (argv[2][j] == '.') { - alen = argv[2][j+1] - '0'; + if (argv[3][j] == '.') { + alen = argv[3][j+1] - '0'; if (alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; - } else if (argv[2][j] == '\0') { + } else if (argv[3][j] == '\0') { break; } } @@ -168,8 +171,8 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * If another parameter, it is the length to display. * Length is the number of objects, not number of bytes. */ - if (argc > 3) - length = simple_strtoul(argv[3], NULL, 16); + if (argc > 4) + length = simple_strtoul(argv[4], NULL, 16); } /* @@ -180,12 +183,10 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ nbytes = length; do { - unsigned char linebuf[DISP_LINE_LEN]; - unsigned char *cp; - + unsigned char linebuf[DISP_LINE_LEN]; + unsigned char *cp; linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; - - if(i2c_read(chip, addr, alen, linebuf, linebytes) != 0) { + if(i2c_read(channel, chip, addr, alen, linebuf, linebytes) != 0) { puts ("Error reading the chip.\n"); } else { printf("%04x:", addr); @@ -207,7 +208,7 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } nbytes -= linebytes; } while (nbytes > 0); - + i2c_dp_last_channel = channel; i2c_dp_last_chip = chip; i2c_dp_last_addr = addr; i2c_dp_last_alen = alen; @@ -230,41 +231,44 @@ int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* Write (fill) memory * * Syntax: - * imw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}] + * imw {channel} {i2c_chip} {addr}{.0, .1, .2} {data} [{count}] */ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - uchar chip; + uchar chip, channel; ulong addr; uint alen; uchar byte; int count; int j; - if ((argc < 4) || (argc > 5)) { + if ((argc < 5) || (argc > 6)) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } /* - * Chip is always specified. + * Channel is always specified. */ - chip = simple_strtoul(argv[1], NULL, 16); + channel = simple_strtoul(argv[1], NULL, 16); + /* Chip is always specified. + */ + chip = simple_strtoul(argv[2], NULL, 16); /* * Address is always specified. */ - addr = simple_strtoul(argv[2], NULL, 16); + addr = simple_strtoul(argv[3], NULL, 16); alen = 1; for(j = 0; j < 8; j++) { - if (argv[2][j] == '.') { - alen = argv[2][j+1] - '0'; + if (argv[3][j] == '.') { + alen = argv[3][j+1] - '0'; if(alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; - } else if (argv[2][j] == '\0') { + } else if (argv[3][j] == '\0') { break; } } @@ -272,19 +276,19 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Value to write is always specified. */ - byte = simple_strtoul(argv[3], NULL, 16); + byte = simple_strtoul(argv[4], NULL, 16); /* * Optional count */ - if(argc == 5) { - count = simple_strtoul(argv[4], NULL, 16); + if(argc == 6) { + count = simple_strtoul(argv[5], NULL, 16); } else { count = 1; } while (count-- > 0) { - if(i2c_write(chip, addr++, alen, &byte, 1) != 0) { + if(i2c_write(channel, chip, addr++, alen, &byte, 1) != 0) { puts ("Error writing the chip.\n"); } /* @@ -322,7 +326,7 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - uchar chip; + uchar chip, channel; ulong addr; uint alen; int count; @@ -339,22 +343,23 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Chip is always specified. */ - chip = simple_strtoul(argv[1], NULL, 16); + channel = simple_strtoul(argv[1], NULL, 16); + chip = simple_strtoul(argv[2], NULL, 16); /* * Address is always specified. */ - addr = simple_strtoul(argv[2], NULL, 16); + addr = simple_strtoul(argv[3], NULL, 16); alen = 1; for(j = 0; j < 8; j++) { - if (argv[2][j] == '.') { - alen = argv[2][j+1] - '0'; + if (argv[3][j] == '.') { + alen = argv[3][j+1] - '0'; if(alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; - } else if (argv[2][j] == '\0') { + } else if (argv[3][j] == '\0') { break; } } @@ -362,7 +367,7 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Count is always specified */ - count = simple_strtoul(argv[3], NULL, 16); + count = simple_strtoul(argv[4], NULL, 16); printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1); /* @@ -372,7 +377,7 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) crc = 0; err = 0; while(count-- > 0) { - if(i2c_read(chip, addr, alen, &byte, 1) != 0) { + if(i2c_read(channel, chip, addr, alen, &byte, 1) != 0) { err++; } crc = crc32 (crc, &byte, 1); @@ -399,7 +404,7 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) static int mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) { - uchar chip; + uchar chip, channel; ulong addr; uint alen; ulong data; @@ -408,7 +413,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) int j; extern char console_buffer[]; - if (argc != 3) { + if (argc != 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } @@ -420,6 +425,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) * We use the last specified parameters, unless new ones are * entered. */ + channel= i2c_dp_last_channel; chip = i2c_mm_last_chip; addr = i2c_mm_last_addr; alen = i2c_mm_last_alen; @@ -431,25 +437,26 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) */ size = cmd_get_data_size(argv[0], 1); + channel = simple_strtoul(argv[1], NULL, 16); /* * Chip is always specified. */ - chip = simple_strtoul(argv[1], NULL, 16); + chip = simple_strtoul(argv[2], NULL, 16); /* * Address is always specified. */ - addr = simple_strtoul(argv[2], NULL, 16); + addr = simple_strtoul(argv[3], NULL, 16); alen = 1; for(j = 0; j < 8; j++) { - if (argv[2][j] == '.') { - alen = argv[2][j+1] - '0'; + if (argv[3][j] == '.') { + alen = argv[3][j+1] - '0'; if(alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; - } else if (argv[2][j] == '\0') { + } else if (argv[3][j] == '\0') { break; } } @@ -461,7 +468,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) */ do { printf("%08lx:", addr); - if(i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) { + if(i2c_read(channel, chip, addr, alen, (uchar *)&data, size) != 0) { puts ("\nError reading the chip,\n"); } else { data = cpu_to_be32(data); @@ -510,7 +517,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) */ reset_cmd_timeout(); #endif - if(i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) { + if(i2c_write(channel, chip, addr, alen, (uchar *)&data, size) != 0) { puts ("Error writing the chip.\n"); } #ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS @@ -536,10 +543,17 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int j; +#if defined(CONFIG_MARVELL) && (defined(MV78XX0) || defined(MV88F6282)) + int i = 0; +#endif #if defined(CFG_I2C_NOPROBES) int k, skip; #endif +#if defined(CONFIG_MARVELL) && (defined(MV78XX0) || defined(MV88F6282)) + for(i = 0; i < 2; i++) { + printf ("\nValid chip channel %d\n",i); +#endif puts ("Valid chip addresses:"); for(j = 0; j < 128; j++) { #if defined(CFG_I2C_NOPROBES) @@ -553,10 +567,19 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (skip) continue; #endif - if(i2c_probe(j) == 0) { +#if defined(CONFIG_MARVELL) && (defined(MV78XX0) || defined(MV88F6282)) + + if(i2c_probe(i,j) == 0) { +#else + if(i2c_probe(0,j) == 0) { +#endif printf(" %02X", j); } } +#if defined(CONFIG_MARVELL) && (defined(MV78XX0) || defined(MV88F6282)) + + } +#endif putc ('\n'); #if defined(CFG_I2C_NOPROBES) @@ -578,7 +601,7 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - u_char chip; + u_char chip,channel; ulong alen; uint addr; uint length; @@ -594,22 +617,23 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Chip is always specified. */ - chip = simple_strtoul(argv[1], NULL, 16); + channel = simple_strtoul(argv[1], NULL, 16); + chip = simple_strtoul(argv[2], NULL, 16); /* * Address is always specified. */ - addr = simple_strtoul(argv[2], NULL, 16); + addr = simple_strtoul(argv[3], NULL, 16); alen = 1; for(j = 0; j < 8; j++) { - if (argv[2][j] == '.') { - alen = argv[2][j+1] - '0'; + if (argv[3][j] == '.') { + alen = argv[3][j+1] - '0'; if (alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; - } else if (argv[2][j] == '\0') { + } else if (argv[3][j] == '\0') { break; } } @@ -618,7 +642,7 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Length is the number of objects, not number of bytes. */ length = 1; - length = simple_strtoul(argv[3], NULL, 16); + length = simple_strtoul(argv[4], NULL, 16); if(length > sizeof(bytes)) { length = sizeof(bytes); } @@ -628,13 +652,13 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ delay = 1000; if (argc > 3) { - delay = simple_strtoul(argv[4], NULL, 10); + delay = simple_strtoul(argv[5], NULL, 10); } /* * Run the loop... */ while(1) { - if(i2c_read(chip, addr, alen, bytes, length) != 0) { + if(i2c_read(channel, chip, addr, alen, bytes, length) != 0) { puts ("Error reading the chip.\n"); } udelay(delay); @@ -671,7 +695,7 @@ int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ chip = simple_strtoul(argv[1], NULL, 16); - if(i2c_read(chip, 0, 1, data, sizeof(data)) != 0) { + if(i2c_read(0, chip, 0, 1, data, sizeof(data)) != 0) { puts ("No SDRAM Serial Presence Detect found.\n"); return 1; } @@ -877,33 +901,33 @@ int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /***************************************************/ U_BOOT_CMD( - imd, 4, 1, do_i2c_md, \ + imd, 5, 1, do_i2c_md, \ "imd - i2c memory display\n", \ - "chip address[.0, .1, .2] [# of objects]\n - i2c memory display\n" \ + "I2C_channel chip address[.0, .1, .2] [# of objects]\n - i2c memory display\n" \ ); U_BOOT_CMD( - imm, 3, 1, do_i2c_mm, - "imm - i2c memory modify (auto-incrementing)\n", - "chip address[.0, .1, .2]\n" + imm, 4, 1, do_i2c_mm, + "imm[.b, .s, .w, .l] - i2c memory modify (auto-incrementing)\n", + "I2C_channel chip address[.0, .1, .2]\n" " - memory modify, auto increment address\n" ); U_BOOT_CMD( - inm, 3, 1, do_i2c_nm, + inm, 4, 1, do_i2c_nm, "inm - memory modify (constant address)\n", - "chip address[.0, .1, .2]\n - memory modify, read and keep address\n" + "I2C_channel chip address[.0, .1, .2]\n - memory modify, read and keep address\n" ); U_BOOT_CMD( - imw, 5, 1, do_i2c_mw, + imw, 6, 1, do_i2c_mw, "imw - memory write (fill)\n", - "chip address[.0, .1, .2] value [count]\n - memory write (fill)\n" + "I2C_channel chip address[.0, .1, .2] value [count]\n - memory write (fill)\n" ); U_BOOT_CMD( icrc32, 5, 1, do_i2c_crc, "icrc32 - checksum calculation\n", - "chip address[.0, .1, .2] count\n - compute CRC32 checksum\n" + "I2C_channel chip address[.0, .1, .2] count\n - compute CRC32 checksum\n" ); U_BOOT_CMD( diff --git a/common/cmd_ide.c b/common/cmd_ide.c index b67d35a..e340d34 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -31,6 +31,8 @@ #include #include #include +#ifndef CONFIG_MARVELL /* Marvell has a board specific IDE support */ + #if defined(CONFIG_IDE_8xx_DIRECT) || defined(CONFIG_IDE_PCMCIA) # include #endif @@ -2066,3 +2068,5 @@ U_BOOT_CMD( ); #endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ + +#endif diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index 34920b1..7fd1fa3 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -91,7 +91,6 @@ #include #include #include -#include #include #include @@ -99,11 +98,19 @@ #include +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#ifdef CFG_NAND_LEGACY +#include +#else /* !CFG_NAND_LEGACY */ +#include +#include +#endif /* !CFG_NAND_LEGACY */ +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ /* enable/disable debugging messages */ -#define DEBUG -#undef DEBUG +#define DEBUG_JFFS +#undef DEBUG_JFFS -#ifdef DEBUG +#ifdef DEBUG_JFFS # define DEBUGF(fmt, args...) printf(fmt ,##args) #else # define DEBUGF(fmt, args...) @@ -123,7 +130,7 @@ /* this flag needs to be set in part_info struct mask_flags * field for read-only partitions */ -#define MTD_WRITEABLE 1 +#define MTD_WRITEABLE_CMD 1 #ifdef CONFIG_JFFS2_CMDLINE /* default values for mtdids and mtdparts variables */ @@ -365,10 +372,9 @@ static int part_validate_nand(struct mtdids *id, struct part_info *part) { #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) /* info for NAND chips */ - extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - struct nand_chip *nand; + nand_info_t *nand; - nand = &nand_dev_desc[id->num]; + nand = &nand_info[id->num]; if ((unsigned long)(part->offset) % nand->erasesize) { printf("%s%d: partition (%s) start offset alignment incorrect\n", @@ -464,7 +470,9 @@ static int part_del(struct mtd_device *dev, struct part_info *part) } } +#ifdef CFG_NAND_LEGACY jffs2_free_cache(part); +#endif list_del(&part->link); free(part); dev->num_parts--; @@ -491,7 +499,9 @@ static void part_delall(struct list_head *head) list_for_each_safe(entry, n, head) { part_tmp = list_entry(entry, struct part_info, link); +#ifdef CFG_NAND_LEGACY jffs2_free_cache(part_tmp); +#endif list_del(entry); free(part_tmp); } @@ -646,7 +656,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i /* test for options */ mask_flags = 0; if (strncmp(p, "ro", 2) == 0) { - mask_flags |= MTD_WRITEABLE; + mask_flags |= MTD_WRITEABLE_CMD; p += 2; } @@ -713,6 +723,7 @@ static int device_validate(u8 type, u8 num, u32 *size) if (num < CFG_MAX_FLASH_BANKS) { extern flash_info_t flash_info[]; *size = flash_info[num].size; + return 0; } @@ -724,8 +735,12 @@ static int device_validate(u8 type, u8 num, u32 *size) } else if (type == MTD_DEV_TYPE_NAND) { #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) if (num < CFG_MAX_NAND_DEVICE) { +#ifndef CFG_NAND_LEGACY + *size = nand_info[num].size; +#else extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; *size = nand_dev_desc[num].totlen; +#endif return 0; } @@ -1169,7 +1184,7 @@ static int generate_mtdparts(char *buf, u32 buflen) } /* ro mask flag */ - if (part->mask_flags && MTD_WRITEABLE) { + if (part->mask_flags && MTD_WRITEABLE_CMD) { len = 2; if (len > maxlen) goto cleanup; @@ -1253,7 +1268,7 @@ static void list_partitions(void) part_num = 0; list_for_each(pentry, &dev->parts) { part = list_entry(pentry, struct part_info, link); - printf(" %d: %-22s\t0x%08x\t0x%08x\t%d\n", + printf("%2d: %-20s0x%08x\t0x%08x\t%d\n", part_num, part->name, part->size, part->offset, part->mask_flags); @@ -1285,7 +1300,7 @@ static void list_partitions(void) * Given partition identifier in form of , find * corresponding device and verify partition number. * - * @param id string describing device and partition + * @param id string describing device and partition or partition name * @param dev pointer to the requested device (output) * @param part_num verified partition number (output) * @param part pointer to requested partition (output) @@ -1294,11 +1309,23 @@ static void list_partitions(void) int find_dev_and_part(const char *id, struct mtd_device **dev, u8 *part_num, struct part_info **part) { + struct list_head *dentry, *pentry; u8 type, dnum, pnum; const char *p; DEBUGF("--- find_dev_and_part ---\nid = %s\n", id); + list_for_each(dentry, &devices) { + *part_num = 0; + *dev = list_entry(dentry, struct mtd_device, link); + list_for_each(pentry, &(*dev)->parts) { + *part = list_entry(pentry, struct part_info, link); + if (strcmp((*part)->name, id) == 0) + return 0; + (*part_num)++; + } + } + p = id; *dev = NULL; *part = NULL; diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 0f4f9b7..627805e 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -28,6 +28,7 @@ */ #include +#include #include #if (CONFIG_COMMANDS & CFG_CMD_MMC) #include @@ -429,8 +430,26 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int rc; puts ("Copy to Flash... "); +#if defined(CONFIG_MARVELL) + /* If source addr is flash copy data to memory first */ + if (addr2info(addr) != NULL) + { char* tmp_buff; + int i; + if (NULL == (tmp_buff = malloc(count*size))) + { + puts (" Copy fail, NULL pointer buffer\n"); + return (1); + } + for( i = 0 ; i < (count*size); i++) + *(tmp_buff + i) = *((char *)addr + i); + + rc = flash_write (tmp_buff, dest, count*size); + free(tmp_buff); + } + else +#endif /* defined(CONFIG_MARVELL) */ + rc = flash_write ((char *)addr, dest, count*size); - rc = flash_write ((char *)addr, dest, count*size); if (rc != 0) { flash_perror (rc); return (1); diff --git a/common/cmd_nand.c b/common/cmd_nand.c index b0c01d1..833e0dc 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -9,6 +9,612 @@ */ #include + + +#ifndef CFG_NAND_LEGACY +/* + * + * New NAND support + * + */ +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include +#include +#include +#include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + +/* parition handling routines */ +int mtdparts_init(void); +int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num); +int find_dev_and_part(const char *id, struct mtd_device **dev, + u8 *part_num, struct part_info **part); +#endif + +extern nand_info_t nand_info[]; /* info for NAND chips */ + +static int nand_dump_oob(nand_info_t *nand, ulong off) +{ + return 0; +} + +static int nand_dump(nand_info_t *nand, ulong off) +{ + int i; + u_char *buf, *p; + + buf = malloc(nand->oobblock + nand->oobsize); + if (!buf) { + puts("No memory for page buffer\n"); + return 1; + } + off &= ~(nand->oobblock - 1); + i = nand_read_raw(nand, buf, off, nand->oobblock, nand->oobsize); + if (i < 0) { + printf("Error (%d) reading page %08x\n", i, off); + free(buf); + return 1; + } + printf("Page %08x dump:\n", off); + i = nand->oobblock >> 4; p = buf; + while (i--) { + printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x" + " %02x %02x %02x %02x %02x %02x %02x %02x\n", + p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], + p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]); + p += 16; + } + puts("OOB:\n"); + i = nand->oobsize >> 3; + while (i--) { + printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x\n", + p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); + p += 8; + } + free(buf); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +static inline int str2long(char *p, ulong *num) +{ + char *endptr; + + *num = simple_strtoul(p, &endptr, 16); + return (*p != '\0' && *endptr == '\0') ? 1 : 0; +} + +static int +arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size) +{ + int idx = nand_curr_device; +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + struct mtd_device *dev; + struct part_info *part; + u8 pnum; + + if (argc >= 1 && !(str2long(argv[0], off))) { + if ((mtdparts_init() == 0) && + (find_dev_and_part(argv[0], &dev, &pnum, &part) == 0)) { + if (dev->id->type != MTD_DEV_TYPE_NAND) { + puts("not a NAND device\n"); + return -1; + } + *off = part->offset; + if (argc >= 2) { + if (!(str2long(argv[1], size))) { + printf("'%s' is not a number\n", argv[1]); + return -1; + } + if (*size > part->size) + *size = part->size; + } else { + *size = part->size; + } + idx = dev->id->num; + *nand = nand_info[idx]; + goto out; + } + } +#endif + + if (argc >= 1) { + if (!(str2long(argv[0], off))) { + printf("'%s' is not a number\n", argv[0]); + return -1; + } + } else { + *off = 0; + } + + if (argc >= 2) { + if (!(str2long(argv[1], size))) { + printf("'%s' is not a number\n", argv[1]); + return -1; + } + } else { + *size = nand->size - *off; + } + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +out: +#endif + printf("device %d ", idx); + if (*size == nand->size) + puts("whole chip\n"); + else + printf("offset 0x%x, size 0x%x\n", *off, *size); + return 0; +} + +int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int i, dev, ret; + ulong addr, off, size; + char *cmd, *s; + nand_info_t *nand; + int quiet = 0; + const char *quiet_str = getenv("quiet"); + + /* at least two arguments please */ + if (argc < 2) + goto usage; + + if (quiet_str) + quiet = simple_strtoul(quiet_str, NULL, 0) != 0; + + cmd = argv[1]; + + if (strcmp(cmd, "info") == 0) { + + putc('\n'); + for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) { + if (nand_info[i].name) + printf("Device %d: %s, sector size %lu KB\n", + i, nand_info[i].name, + nand_info[i].erasesize >> 10); + } + return 0; + } + + if (strcmp(cmd, "device") == 0) { + + if (argc < 3) { + if ((nand_curr_device < 0) || + (nand_curr_device >= CFG_MAX_NAND_DEVICE)) + puts("\nno devices available\n"); + else + printf("\nDevice %d: %s\n", nand_curr_device, + nand_info[nand_curr_device].name); + return 0; + } + dev = (int)simple_strtoul(argv[2], NULL, 10); + if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) { + puts("No such device\n"); + return 1; + } + printf("Device %d: %s", dev, nand_info[dev].name); + puts("... is now current device\n"); + nand_curr_device = dev; + +#ifdef CFG_NAND_SELECT_DEVICE + /* + * Select the chip in the board/cpu specific driver + */ + board_nand_select_device(nand_info[dev].priv, dev); +#endif + + return 0; + } + + if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 && + strncmp(cmd, "dump", 4) != 0 && + strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 && + strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 && + strcmp(cmd, "biterr") != 0 && + strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 ) + goto usage; + + /* the following commands operate on the current device */ + if (nand_curr_device < 0 || nand_curr_device >= CFG_MAX_NAND_DEVICE || + !nand_info[nand_curr_device].name) { + puts("\nno devices available\n"); + return 1; + } + nand = &nand_info[nand_curr_device]; + + if (strcmp(cmd, "bad") == 0) { + printf("\nDevice %d bad blocks:\n", nand_curr_device); + for (off = 0; off < nand->size; off += nand->erasesize) + if (nand_block_isbad(nand, off)) + printf(" %08x\n", off); + return 0; + } + + /* + * Syntax is: + * 0 1 2 3 4 + * nand erase [clean] [off size] + */ + if (strcmp(cmd, "erase") == 0 || strcmp(cmd, "scrub") == 0) { + nand_erase_options_t opts; + /* "clean" at index 2 means request to write cleanmarker */ + int clean = argc > 2 && !strcmp("clean", argv[2]); + int o = clean ? 3 : 2; + int scrub = !strcmp(cmd, "scrub"); + + printf("\nNAND %s: ", scrub ? "scrub" : "erase"); + /* skip first two or three arguments, look for offset and size */ + if (arg_off_size(argc - o, argv + o, nand, &off, &size) != 0) + return 1; + + memset(&opts, 0, sizeof(opts)); + opts.offset = off; + opts.length = size; + opts.jffs2 = clean; + opts.quiet = quiet; + + if (scrub) { + puts("Warning: " + "scrub option will erase all factory set " + "bad blocks!\n" + " " + "There is no reliable way to recover them.\n" + " " + "Use this command only for testing purposes " + "if you\n" + " " + "are sure of what you are doing!\n" + "\nReally scrub this NAND flash? \n"); + + if (getc() == 'y' && getc() == '\r') { + opts.scrub = 1; + } else { + puts("scrub aborted\n"); + return -1; + } + } + ret = nand_erase_opts(nand, &opts); + printf("%s\n", ret ? "ERROR" : "OK"); + + return ret == 0 ? 0 : 1; + } + + if (strncmp(cmd, "dump", 4) == 0) { + if (argc < 3) + goto usage; + + s = strchr(cmd, '.'); + off = (int)simple_strtoul(argv[2], NULL, 16); + + if (s != NULL && strcmp(s, ".oob") == 0) + ret = nand_dump_oob(nand, off); + else + ret = nand_dump(nand, off); + + return ret == 0 ? 1 : 0; + + } + + /* read write */ + if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) { + int read; + + if (argc < 4) + goto usage; + + addr = (ulong)simple_strtoul(argv[2], NULL, 16); + + read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ + printf("\nNAND %s: ", read ? "read" : "write"); + if (arg_off_size(argc - 3, argv + 3, nand, &off, &size) != 0) + return 1; + + s = strchr(cmd, '.'); + if (s != NULL && + (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) { + if (read) { + /* read */ + nand_read_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char*) addr; + opts.length = size; + opts.offset = off; + opts.quiet = quiet; + ret = nand_read_opts(nand, &opts); + } else { + /* write */ + nand_write_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char*) addr; + opts.length = size; + opts.offset = off; + /* opts.forcejffs2 = 1; */ + opts.pad = 1; + opts.blockalign = 1; + opts.quiet = quiet; + ret = nand_write_opts(nand, &opts); + } + } else { + if (read) + ret = nand_read(nand, off, &size, (u_char *)addr); + else + ret = nand_write(nand, off, &size, (u_char *)addr); + } + + printf(" %d bytes %s: %s\n", size, + read ? "read" : "written", ret ? "ERROR" : "OK"); + + return ret == 0 ? 0 : 1; + } + + if (strcmp(cmd, "markbad") == 0) { + addr = (ulong)simple_strtoul(argv[2], NULL, 16); + + int ret = nand->block_markbad(nand, addr); + if (ret == 0) { + printf("block 0x%08lx successfully marked as bad\n", + (ulong) addr); + return 0; + } else { + printf("block 0x%08lx NOT marked as bad! ERROR %d\n", + (ulong) addr, ret); + } + return 1; + } + if (strcmp(cmd, "biterr") == 0) { + /* todo */ + return 1; + } + + if (strcmp(cmd, "lock") == 0) { + int tight = 0; + int status = 0; + if (argc == 3) { + if (!strcmp("tight", argv[2])) + tight = 1; + if (!strcmp("status", argv[2])) + status = 1; + } + + if (status) { + ulong block_start = 0; + ulong off; + int last_status = -1; + + struct nand_chip *nand_chip = nand->priv; + /* check the WP bit */ + nand_chip->cmdfunc (nand, NAND_CMD_STATUS, -1, -1); + printf("device is %swrite protected\n", + (nand_chip->read_byte(nand) & 0x80 ? + "NOT " : "" ) ); + + for (off = 0; off < nand->size; off += nand->oobblock) { + int s = nand_get_lock_status(nand, off); + + /* print message only if status has changed + * or at end of chip + */ + if (off == nand->size - nand->oobblock + || (s != last_status && off != 0)) { + + printf("%08x - %08x: %8d pages %s%s%s\n", + block_start, + off-1, + (off-block_start)/nand->oobblock, + ((last_status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""), + ((last_status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""), + ((last_status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : "")); + } + + last_status = s; + } + } else { + if (!nand_lock(nand, tight)) { + puts("NAND flash successfully locked\n"); + } else { + puts("Error locking NAND flash\n"); + return 1; + } + } + return 0; + } + + if (strcmp(cmd, "unlock") == 0) { + if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0) + return 1; + + if (!nand_unlock(nand, off, size)) { + puts("NAND flash successfully unlocked\n"); + } else { + puts("Error unlocking NAND flash, " + "write and erase will probably fail\n"); + return 1; + } + return 0; + } + +usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD(nand, 5, 1, do_nand, + "nand - NAND sub-system\n", + "info - show available NAND devices\n" + "nand device [dev] - show or set current device\n" + "nand read[.jffs2/.e] - addr off|partition size (Using the .e option skips bad blocks)\n" + "nand write[.jffs2/.e] - addr off|partiton size (Using the .e option skips bad blocks)\n" + " at offset `off' to/from memory address `addr'\n" + "nand erase [clean] [off size] - erase `size' bytes from\n" + " offset `off' (entire device if not specified)\n" + "nand bad - show bad blocks\n" + "nand dump[.oob] off - dump page\n" + "nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n" + "nand markbad off - mark bad block at offset (UNSAFE)\n" + "nand biterr off - make a bit error at offset (UNSAFE)\n" + "nand lock [tight] [status] - bring nand to lock state or display locked pages\n" + "nand unlock [offset] [size] - unlock section\n"); + +static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, + ulong offset, ulong addr, char *cmd) +{ + int r; + char *ep; + ulong cnt; + image_header_t *hdr; + + printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset); + + cnt = nand->oobblock; + r = nand_read(nand, offset, &cnt, (u_char *) addr); + if (r) { + puts("** Read error\n"); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + hdr = (image_header_t *) addr; + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + print_image_hdr(hdr); + + cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t)); + + r = nand_read(nand, offset, &cnt, (u_char *) addr); + if (r) { + puts("** Read error\n"); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + /* Loading ok, update default load address */ + + load_addr = addr; + + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) { + char *local_args[2]; + extern int do_bootm(cmd_tbl_t *, int, int, char *[]); + + local_args[0] = cmd; + local_args[1] = NULL; + + printf("Automatic boot of image at addr 0x%08lx ...\n", addr); + + do_bootm(cmdtp, 0, 1, local_args); + return 1; + } + return 0; +} + +int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char *boot_device = NULL; + int idx; + ulong addr, offset = 0; +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + struct mtd_device *dev; + struct part_info *part; + u8 pnum; + + if (argc >= 2) { + char *p = (argc == 2) ? argv[1] : argv[2]; + if (!(str2long(p, &addr)) && (mtdparts_init() == 0) && + (find_dev_and_part(p, &dev, &pnum, &part) == 0)) { + if (dev->id->type != MTD_DEV_TYPE_NAND) { + puts("Not a NAND device\n"); + return 1; + } + if (argc > 3) + goto usage; + if (argc == 3) + addr = simple_strtoul(argv[2], NULL, 16); + else + addr = CFG_LOAD_ADDR; + return nand_load_image(cmdtp, &nand_info[dev->id->num], + part->offset, addr, argv[0]); + } + } +#endif + + switch (argc) { + case 1: + addr = CFG_LOAD_ADDR; + boot_device = getenv("bootdevice"); + break; + case 2: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = getenv("bootdevice"); + break; + case 3: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + break; + case 4: + addr = simple_strtoul(argv[1], NULL, 16); + boot_device = argv[2]; + offset = simple_strtoul(argv[3], NULL, 16); + break; + default: +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +usage: +#endif + printf("Usage:\n%s\n", cmdtp->usage); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + if (!boot_device) { + puts("\n** No boot device **\n"); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + idx = simple_strtoul(boot_device, NULL, 16); + + if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) { + printf("\n** Device %d not available\n", idx); + SHOW_BOOT_PROGRESS(-1); + return 1; + } + + return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]); +} + +U_BOOT_CMD(nboot, 4, 1, do_nandboot, + "nboot - boot from NAND device\n", + "[partition] | [[[loadAddr] dev] offset]\n"); + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ + +#else /* CFG_NAND_LEGACY */ +/* + * + * Legacy NAND support - to be phased out + * + */ #include #include #include @@ -22,10 +628,11 @@ #endif #if (CONFIG_COMMANDS & CFG_CMD_NAND) - -#include +#include +#if 0 #include #include +#endif #ifdef CONFIG_OMAP1510 void archflashwp(void *archdata, int wp); @@ -33,15 +640,6 @@ void archflashwp(void *archdata, int wp); #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) -/* - * Definition of the out of band configuration structure - */ -struct nand_oob_config { - int ecc_pos[6]; /* position of ECC bytes inside oob */ - int badblock_pos; /* position of bad block flag inside oob -1 = inactive */ - int eccvalid_pos; /* position of ECC valid flag inside oob -1 = inactive */ -} oob_config = { {0}, 0, 0}; - #undef NAND_DEBUG #undef PSYCHO_DEBUG @@ -63,218 +661,210 @@ struct nand_oob_config { #define CONFIG_MTD_NAND_ECC /* enable ECC */ #define CONFIG_MTD_NAND_ECC_JFFS2 -/* bits for nand_rw() `cmd'; or together as needed */ +/* bits for nand_legacy_rw() `cmd'; or together as needed */ #define NANDRW_READ 0x01 #define NANDRW_WRITE 0x00 #define NANDRW_JFFS2 0x02 #define NANDRW_JFFS2_SKIP 0x04 /* - * Function Prototypes + * Imports from nand_legacy.c */ -static void nand_print(struct nand_chip *nand); -int nand_rw (struct nand_chip* nand, int cmd, - size_t start, size_t len, - size_t * retlen, u_char * buf); -int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); -static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, - size_t * retlen, u_char *buf, u_char *ecc_code); -static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, - size_t * retlen, const u_char * buf, u_char * ecc_code); -static void nand_print_bad(struct nand_chip *nand); -static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, - size_t * retlen, u_char * buf); -static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, - size_t * retlen, const u_char * buf); -static int NanD_WaitReady(struct nand_chip *nand, int ale_wait); -#ifdef CONFIG_MTD_NAND_ECC -static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc); -static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code); -#endif +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern int curr_device; +extern int nand_legacy_erase(struct nand_chip *nand, size_t ofs, + size_t len, int clean); +extern int nand_legacy_rw(struct nand_chip *nand, int cmd, size_t start, + size_t len, size_t *retlen, u_char *buf); +extern void nand_print(struct nand_chip *nand); +extern void nand_print_bad(struct nand_chip *nand); +extern int nand_read_oob(struct nand_chip *nand, size_t ofs, + size_t len, size_t *retlen, u_char *buf); +extern int nand_write_oob(struct nand_chip *nand, size_t ofs, + size_t len, size_t *retlen, const u_char *buf); -struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}}; -/* Current NAND Device */ -static int curr_device = -1; - -/* ------------------------------------------------------------------------- */ - -int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - int rcode = 0; + int rcode = 0; - switch (argc) { - case 0: - case 1: - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - case 2: - if (strcmp(argv[1],"info") == 0) { - int i; + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strcmp (argv[1], "info") == 0) { + int i; - putc ('\n'); + putc ('\n'); - for (i=0; i= CFG_MAX_NAND_DEVICE)) { - puts ("\nno devices available\n"); - return 1; - } - printf ("\nDevice %d: ", curr_device); - nand_print(&nand_dev_desc[curr_device]); - return 0; - - } else if (strcmp(argv[1],"bad") == 0) { - if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { - puts ("\nno devices available\n"); - return 1; - } - printf ("\nDevice %d bad blocks:\n", curr_device); - nand_print_bad(&nand_dev_desc[curr_device]); - return 0; - - } - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - case 3: - if (strcmp(argv[1],"device") == 0) { - int dev = (int)simple_strtoul(argv[2], NULL, 10); - - printf ("\nDevice %d: ", dev); - if (dev >= CFG_MAX_NAND_DEVICE) { - puts ("unknown device\n"); - return 1; - } - nand_print(&nand_dev_desc[dev]); - /*nand_print (dev);*/ - - if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) { - return 1; - } - - curr_device = dev; - - puts ("... is now current device\n"); - - return 0; - } - else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) { - struct nand_chip* nand = &nand_dev_desc[curr_device]; - ulong off = 0; - ulong size = nand->totlen; - int ret; - - printf ("\nNAND erase: device %d offset %ld, size %ld ... ", - curr_device, off, size); - - ret = nand_erase (nand, off, size, 1); - - printf("%s\n", ret ? "ERROR" : "OK"); - - return ret; - } - - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - default: - /* at least 4 args */ - - if (strncmp(argv[1], "read", 4) == 0 || - strncmp(argv[1], "write", 5) == 0) { - ulong addr = simple_strtoul(argv[2], NULL, 16); - ulong off = simple_strtoul(argv[3], NULL, 16); - ulong size = simple_strtoul(argv[4], NULL, 16); - int cmd = (strncmp(argv[1], "read", 4) == 0) ? - NANDRW_READ : NANDRW_WRITE; - int ret, total; - char* cmdtail = strchr(argv[1], '.'); - - if (cmdtail && !strncmp(cmdtail, ".oob", 2)) { - /* read out-of-band data */ - if (cmd & NANDRW_READ) { - ret = nand_read_oob(nand_dev_desc + curr_device, - off, size, (size_t *)&total, - (u_char*)addr); + for (i = 0; i < CFG_MAX_NAND_DEVICE; ++i) { + if (nand_dev_desc[i].ChipID == + NAND_ChipID_UNKNOWN) + continue; /* list only known devices */ + printf ("Device %d: ", i); + nand_print (&nand_dev_desc[i]); } - else { - ret = nand_write_oob(nand_dev_desc + curr_device, - off, size, (size_t *)&total, - (u_char*)addr); + return 0; + + } else if (strcmp (argv[1], "device") == 0) { + if ((curr_device < 0) + || (curr_device >= CFG_MAX_NAND_DEVICE)) { + puts ("\nno devices available\n"); + return 1; } + printf ("\nDevice %d: ", curr_device); + nand_print (&nand_dev_desc[curr_device]); + return 0; + + } else if (strcmp (argv[1], "bad") == 0) { + if ((curr_device < 0) + || (curr_device >= CFG_MAX_NAND_DEVICE)) { + puts ("\nno devices available\n"); + return 1; + } + printf ("\nDevice %d bad blocks:\n", curr_device); + nand_print_bad (&nand_dev_desc[curr_device]); + return 0; + + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strcmp (argv[1], "device") == 0) { + int dev = (int) simple_strtoul (argv[2], NULL, 10); + + printf ("\nDevice %d: ", dev); + if (dev >= CFG_MAX_NAND_DEVICE) { + puts ("unknown device\n"); + return 1; + } + nand_print (&nand_dev_desc[dev]); + /*nand_print (dev); */ + + if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) { + return 1; + } + + curr_device = dev; + + puts ("... is now current device\n"); + + return 0; + } else if (strcmp (argv[1], "erase") == 0 + && strcmp (argv[2], "clean") == 0) { + struct nand_chip *nand = &nand_dev_desc[curr_device]; + ulong off = 0; + ulong size = nand->totlen; + int ret; + + printf ("\nNAND erase: device %d offset %ld, size %ld ... ", curr_device, off, size); + + ret = nand_legacy_erase (nand, off, size, 1); + + printf ("%s\n", ret ? "ERROR" : "OK"); + return ret; } - else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2)) - cmd |= NANDRW_JFFS2; /* skip bad blocks */ - else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) { - cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ - if (cmd & NANDRW_READ) - cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ - } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + default: + /* at least 4 args */ + + if (strncmp (argv[1], "read", 4) == 0 || + strncmp (argv[1], "write", 5) == 0) { + ulong addr = simple_strtoul (argv[2], NULL, 16); + ulong off = simple_strtoul (argv[3], NULL, 16); + ulong size = simple_strtoul (argv[4], NULL, 16); + int cmd = (strncmp (argv[1], "read", 4) == 0) ? + NANDRW_READ : NANDRW_WRITE; + int ret, total; + char *cmdtail = strchr (argv[1], '.'); + + if (cmdtail && !strncmp (cmdtail, ".oob", 2)) { + /* read out-of-band data */ + if (cmd & NANDRW_READ) { + ret = nand_read_oob (nand_dev_desc + curr_device, + off, size, (size_t *) & total, + (u_char *) addr); + } else { + ret = nand_write_oob (nand_dev_desc + curr_device, + off, size, (size_t *) & total, + (u_char *) addr); + } + return ret; + } else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2)) + cmd |= NANDRW_JFFS2; /* skip bad blocks */ + else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 2)) { + cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ + if (cmd & NANDRW_READ) + cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ + } #ifdef SXNI855T - /* need ".e" same as ".j" for compatibility with older units */ - else if (cmdtail && !strcmp(cmdtail, ".e")) - cmd |= NANDRW_JFFS2; /* skip bad blocks */ + /* need ".e" same as ".j" for compatibility with older units */ + else if (cmdtail && !strcmp (cmdtail, ".e")) + cmd |= NANDRW_JFFS2; /* skip bad blocks */ #endif #ifdef CFG_NAND_SKIP_BAD_DOT_I - /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */ - /* ".i" for image -> read skips bad block (no 0xff) */ - else if (cmdtail && !strcmp(cmdtail, ".i")) { - cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ - if (cmd & NANDRW_READ) - cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ - } + /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */ + /* ".i" for image -> read skips bad block (no 0xff) */ + else if (cmdtail && !strcmp (cmdtail, ".i")) { + cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ + if (cmd & NANDRW_READ) + cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ + } #endif /* CFG_NAND_SKIP_BAD_DOT_I */ - else if (cmdtail) { + else if (cmdtail) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + printf ("\nNAND %s: device %d offset %ld, size %ld ...\n", + (cmd & NANDRW_READ) ? "read" : "write", + curr_device, off, size); + + ret = nand_legacy_rw (nand_dev_desc + curr_device, + cmd, off, size, + (size_t *) & total, + (u_char *) addr); + + printf (" %d bytes %s: %s\n", total, + (cmd & NANDRW_READ) ? "read" : "written", + ret ? "ERROR" : "OK"); + + return ret; + } else if (strcmp (argv[1], "erase") == 0 && + (argc == 4 || strcmp ("clean", argv[2]) == 0)) { + int clean = argc == 5; + ulong off = + simple_strtoul (argv[2 + clean], NULL, 16); + ulong size = + simple_strtoul (argv[3 + clean], NULL, 16); + int ret; + + printf ("\nNAND erase: device %d offset %ld, size %ld ...\n", + curr_device, off, size); + + ret = nand_legacy_erase (nand_dev_desc + curr_device, + off, size, clean); + + printf ("%s\n", ret ? "ERROR" : "OK"); + + return ret; + } else { printf ("Usage:\n%s\n", cmdtp->usage); - return 1; + rcode = 1; } - printf ("\nNAND %s: device %d offset %ld, size %ld ... ", - (cmd & NANDRW_READ) ? "read" : "write", - curr_device, off, size); - - ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size, - (size_t *)&total, (u_char*)addr); - - printf (" %d bytes %s: %s\n", total, - (cmd & NANDRW_READ) ? "read" : "written", - ret ? "ERROR" : "OK"); - - return ret; - } else if (strcmp(argv[1],"erase") == 0 && - (argc == 4 || strcmp("clean", argv[2]) == 0)) { - int clean = argc == 5; - ulong off = simple_strtoul(argv[2 + clean], NULL, 16); - ulong size = simple_strtoul(argv[3 + clean], NULL, 16); - int ret; - - printf ("\nNAND erase: device %d offset %ld, size %ld ... ", - curr_device, off, size); - - ret = nand_erase (nand_dev_desc + curr_device, off, size, clean); - - printf("%s\n", ret ? "ERROR" : "OK"); - - return ret; - } else { - printf ("Usage:\n%s\n", cmdtp->usage); - rcode = 1; + return rcode; } - - return rcode; - } } U_BOOT_CMD( nand, 5, 1, do_nand, - "nand - NAND sub-system\n", + "nand - legacy NAND sub-system\n", "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" "nand read[.jffs2[s]] addr off size\n" @@ -340,8 +930,8 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR, offset); - if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset, - SECTORSIZE, NULL, (u_char *)addr)) { + if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset, + SECTORSIZE, NULL, (u_char *)addr)) { printf ("** Read error on %d\n", dev); SHOW_BOOT_PROGRESS (-1); return 1; @@ -356,13 +946,14 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); cnt -= SECTORSIZE; } else { - printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic); + printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic)); SHOW_BOOT_PROGRESS (-1); return 1; } - if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt, - NULL, (u_char *)(addr+SECTORSIZE))) { + if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, + offset + SECTORSIZE, cnt, NULL, + (u_char *)(addr+SECTORSIZE))) { printf ("** Read error on %d\n", dev); SHOW_BOOT_PROGRESS (-1); return 1; @@ -394,1505 +985,6 @@ U_BOOT_CMD( "loadAddr dev\n" ); -/* returns 0 if block containing pos is OK: - * valid erase block and - * not marked bad, or no bad mark position is specified - * returns 1 if marked bad or otherwise invalid - */ -int check_block (struct nand_chip *nand, unsigned long pos) -{ - size_t retlen; - uint8_t oob_data; - uint16_t oob_data16[6]; - int page0 = pos & (-nand->erasesize); - int page1 = page0 + nand->oobblock; - int badpos = oob_config.badblock_pos; - - if (pos >= nand->totlen) - return 1; - - if (badpos < 0) - return 0; /* no way to check, assume OK */ - - if (nand->bus16) { - if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16) - || (oob_data16[2] & 0xff00) != 0xff00) - return 1; - if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16) - || (oob_data16[2] & 0xff00) != 0xff00) - return 1; - } else { - /* Note - bad block marker can be on first or second page */ - if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data) - || oob_data != 0xff - || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data) - || oob_data != 0xff) - return 1; - } - - return 0; -} - -/* print bad blocks in NAND flash */ -static void nand_print_bad(struct nand_chip* nand) -{ - unsigned long pos; - - for (pos = 0; pos < nand->totlen; pos += nand->erasesize) { - if (check_block(nand, pos)) - printf(" 0x%8.8lx\n", pos); - } - puts("\n"); -} - -/* cmd: 0: NANDRW_WRITE write, fail on bad block - * 1: NANDRW_READ read, fail on bad block - * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks - * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks - * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks - */ -int nand_rw (struct nand_chip* nand, int cmd, - size_t start, size_t len, - size_t * retlen, u_char * buf) -{ - int ret = 0, n, total = 0; - char eccbuf[6]; - /* eblk (once set) is the start of the erase block containing the - * data being processed. - */ - unsigned long eblk = ~0; /* force mismatch on first pass */ - unsigned long erasesize = nand->erasesize; - - while (len) { - if ((start & (-erasesize)) != eblk) { - /* have crossed into new erase block, deal with - * it if it is sure marked bad. - */ - eblk = start & (-erasesize); /* start of block */ - if (check_block(nand, eblk)) { - if (cmd == (NANDRW_READ | NANDRW_JFFS2)) { - while (len > 0 && - start - eblk < erasesize) { - *(buf++) = 0xff; - ++start; - ++total; - --len; - } - continue; - } else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) { - start += erasesize; - continue; - } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) { - /* skip bad block */ - start += erasesize; - continue; - } else { - ret = 1; - break; - } - } - } - /* The ECC will not be calculated correctly if - less than 512 is written or read */ - /* Is request at least 512 bytes AND it starts on a proper boundry */ - if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200)) - printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n"); - - if (cmd & NANDRW_READ) { - ret = nand_read_ecc(nand, start, - min(len, eblk + erasesize - start), - (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); - } else { - ret = nand_write_ecc(nand, start, - min(len, eblk + erasesize - start), - (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); - } - - if (ret) - break; - - start += n; - buf += n; - total += n; - len -= n; - } - if (retlen) - *retlen = total; - - return ret; -} - -static void nand_print(struct nand_chip *nand) -{ - if (nand->numchips > 1) { - printf("%s at 0x%lx,\n" - "\t %d chips %s, size %d MB, \n" - "\t total size %ld MB, sector size %ld kB\n", - nand->name, nand->IO_ADDR, nand->numchips, - nand->chips_name, 1 << (nand->chipshift - 20), - nand->totlen >> 20, nand->erasesize >> 10); - } - else { - printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR); - print_size(nand->totlen, ", "); - print_size(nand->erasesize, " sector)\n"); - } -} - -/* ------------------------------------------------------------------------- */ - -static int NanD_WaitReady(struct nand_chip *nand, int ale_wait) -{ - /* This is inline, to optimise the common case, where it's ready instantly */ - int ret = 0; - -#ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */ - if(ale_wait) - NAND_WAIT_READY(nand); /* do the worst case 25us wait */ - else - udelay(10); -#else /* has functional r/b signal */ - NAND_WAIT_READY(nand); -#endif - return ret; -} - -/* NanD_Command: Send a flash command to the flash chip */ - -static inline int NanD_Command(struct nand_chip *nand, unsigned char command) -{ - unsigned long nandptr = nand->IO_ADDR; - - /* Assert the CLE (Command Latch Enable) line to the flash chip */ - NAND_CTL_SETCLE(nandptr); - - /* Send the command */ - WRITE_NAND_COMMAND(command, nandptr); - - /* Lower the CLE line */ - NAND_CTL_CLRCLE(nandptr); - -#ifdef NAND_NO_RB - if(command == NAND_CMD_RESET){ - u_char ret_val; - NanD_Command(nand, NAND_CMD_STATUS); - do { - ret_val = READ_NAND(nandptr);/* wait till ready */ - } while((ret_val & 0x40) != 0x40); - } -#endif - return NanD_WaitReady(nand, 0); -} - -/* NanD_Address: Set the current address for the flash chip */ - -static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs) -{ - unsigned long nandptr; - int i; - - nandptr = nand->IO_ADDR; - - /* Assert the ALE (Address Latch Enable) line to the flash chip */ - NAND_CTL_SETALE(nandptr); - - /* Send the address */ - /* Devices with 256-byte page are addressed as: - * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31) - * there is no device on the market with page256 - * and more than 24 bits. - * Devices with 512-byte page are addressed as: - * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31) - * 25-31 is sent only if the chip support it. - * bit 8 changes the read command to be sent - * (NAND_CMD_READ0 or NAND_CMD_READ1). - */ - - if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) - WRITE_NAND_ADDRESS(ofs, nandptr); - - ofs = ofs >> nand->page_shift; - - if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) { - for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) { - WRITE_NAND_ADDRESS(ofs, nandptr); - } - } - - /* Lower the ALE line */ - NAND_CTL_CLRALE(nandptr); - - /* Wait for the chip to respond */ - return NanD_WaitReady(nand, 1); -} - -/* NanD_SelectChip: Select a given flash chip within the current floor */ - -static inline int NanD_SelectChip(struct nand_chip *nand, int chip) -{ - /* Wait for it to be ready */ - return NanD_WaitReady(nand, 0); -} - -/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */ - -static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip) -{ - int mfr, id, i; - - NAND_ENABLE_CE(nand); /* set pin low */ - /* Reset the chip */ - if (NanD_Command(nand, NAND_CMD_RESET)) { -#ifdef NAND_DEBUG - printf("NanD_Command (reset) for %d,%d returned true\n", - floor, chip); -#endif - NAND_DISABLE_CE(nand); /* set pin high */ - return 0; - } - - /* Read the NAND chip ID: 1. Send ReadID command */ - if (NanD_Command(nand, NAND_CMD_READID)) { -#ifdef NAND_DEBUG - printf("NanD_Command (ReadID) for %d,%d returned true\n", - floor, chip); -#endif - NAND_DISABLE_CE(nand); /* set pin high */ - return 0; - } - - /* Read the NAND chip ID: 2. Send address byte zero */ - NanD_Address(nand, ADDR_COLUMN, 0); - - /* Read the manufacturer and device id codes from the device */ - - mfr = READ_NAND(nand->IO_ADDR); - - id = READ_NAND(nand->IO_ADDR); - - NAND_DISABLE_CE(nand); /* set pin high */ - -#ifdef NAND_DEBUG - printf("NanD_Command (ReadID) got %x %x\n", mfr, id); -#endif - if (mfr == 0xff || mfr == 0) { - /* No response - return failure */ - return 0; - } - - /* Check it's the same as the first chip we identified. - * M-Systems say that any given nand_chip device should only - * contain _one_ type of flash part, although that's not a - * hardware restriction. */ - if (nand->mfr) { - if (nand->mfr == mfr && nand->id == id) { - return 1; /* This is another the same the first */ - } else { - printf("Flash chip at floor %d, chip %d is different:\n", - floor, chip); - } - } - - /* Print and store the manufacturer and ID codes. */ - for (i = 0; nand_flash_ids[i].name != NULL; i++) { - if (mfr == nand_flash_ids[i].manufacture_id && - id == nand_flash_ids[i].model_id) { -#ifdef NAND_DEBUG - printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, " - "Chip ID: 0x%2.2X (%s)\n", mfr, id, - nand_flash_ids[i].name); -#endif - if (!nand->mfr) { - nand->mfr = mfr; - nand->id = id; - nand->chipshift = - nand_flash_ids[i].chipshift; - nand->page256 = nand_flash_ids[i].page256; - nand->eccsize = 256; - if (nand->page256) { - nand->oobblock = 256; - nand->oobsize = 8; - nand->page_shift = 8; - } else { - nand->oobblock = 512; - nand->oobsize = 16; - nand->page_shift = 9; - } - nand->pageadrlen = nand_flash_ids[i].pageadrlen; - nand->erasesize = nand_flash_ids[i].erasesize; - nand->chips_name = nand_flash_ids[i].name; - nand->bus16 = nand_flash_ids[i].bus16; - return 1; - } - return 0; - } - } - - -#ifdef NAND_DEBUG - /* We haven't fully identified the chip. Print as much as we know. */ - printf("Unknown flash chip found: %2.2X %2.2X\n", - id, mfr); -#endif - - return 0; -} - -/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */ - -static void NanD_ScanChips(struct nand_chip *nand) -{ - int floor, chip; - int numchips[NAND_MAX_FLOORS]; - int maxchips = NAND_MAX_CHIPS; - int ret = 1; - - nand->numchips = 0; - nand->mfr = 0; - nand->id = 0; - - - /* For each floor, find the number of valid chips it contains */ - for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { - ret = 1; - numchips[floor] = 0; - for (chip = 0; chip < maxchips && ret != 0; chip++) { - - ret = NanD_IdentChip(nand, floor, chip); - if (ret) { - numchips[floor]++; - nand->numchips++; - } - } - } - - /* If there are none at all that we recognise, bail */ - if (!nand->numchips) { -#ifdef NAND_DEBUG - puts ("No NAND flash chips recognised.\n"); -#endif - return; - } - - /* Allocate an array to hold the information for each chip */ - nand->chips = malloc(sizeof(struct Nand) * nand->numchips); - if (!nand->chips) { - puts ("No memory for allocating chip info structures\n"); - return; - } - - ret = 0; - - /* Fill out the chip array with {floor, chipno} for each - * detected chip in the device. */ - for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { - for (chip = 0; chip < numchips[floor]; chip++) { - nand->chips[ret].floor = floor; - nand->chips[ret].chip = chip; - nand->chips[ret].curadr = 0; - nand->chips[ret].curmode = 0x50; - ret++; - } - } - - /* Calculate and print the total size of the device */ - nand->totlen = nand->numchips * (1 << nand->chipshift); - -#ifdef NAND_DEBUG - printf("%d flash chips found. Total nand_chip size: %ld MB\n", - nand->numchips, nand->totlen >> 20); -#endif -} - -/* we need to be fast here, 1 us per read translates to 1 second per meg */ -static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr) -{ - unsigned long nandptr = nand->IO_ADDR; - - NanD_Command (nand, NAND_CMD_READ0); - - if (nand->bus16) { - u16 val; - - while (cntr >= 16) { - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - cntr -= 16; - } - - while (cntr > 0) { - val = READ_NAND (nandptr); - *data_buf++ = val & 0xff; - *data_buf++ = val >> 8; - cntr -= 2; - } - } else { - while (cntr >= 16) { - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - *data_buf++ = READ_NAND (nandptr); - cntr -= 16; - } - - while (cntr > 0) { - *data_buf++ = READ_NAND (nandptr); - cntr--; - } - } -} - -/* - * NAND read with ECC - */ -static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, - size_t * retlen, u_char *buf, u_char *ecc_code) -{ - int col, page; - int ecc_status = 0; -#ifdef CONFIG_MTD_NAND_ECC - int j; - int ecc_failed = 0; - u_char *data_poi; - u_char ecc_calc[6]; -#endif - - /* Do not allow reads past end of device */ - if ((start + len) > nand->totlen) { - printf ("%s: Attempt read beyond end of device %x %x %x\n", - __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen); - *retlen = 0; - return -1; - } - - /* First we calculate the starting page */ - /*page = shr(start, nand->page_shift);*/ - page = start >> nand->page_shift; - - /* Get raw starting column */ - col = start & (nand->oobblock - 1); - - /* Initialize return value */ - *retlen = 0; - - /* Select the NAND device */ - NAND_ENABLE_CE(nand); /* set pin low */ - - /* Loop until all data read */ - while (*retlen < len) { - -#ifdef CONFIG_MTD_NAND_ECC - /* Do we have this page in cache ? */ - if (nand->cache_page == page) - goto readdata; - /* Send the read command */ - NanD_Command(nand, NAND_CMD_READ0); - if (nand->bus16) { - NanD_Address(nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address(nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - - /* Read in a page + oob data */ - NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize); - - /* copy data into cache, for read out of cache and if ecc fails */ - if (nand->data_cache) { - memcpy (nand->data_cache, nand->data_buf, - nand->oobblock + nand->oobsize); - } - - /* Pick the ECC bytes out of the oob data */ - for (j = 0; j < 6; j++) { - ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])]; - } - - /* Calculate the ECC and verify it */ - /* If block was not written with ECC, skip ECC */ - if (oob_config.eccvalid_pos != -1 && - (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) { - - nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]); - switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) { - case -1: - printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); - ecc_failed++; - break; - case 1: - case 2: /* transfer ECC corrected data to cache */ - if (nand->data_cache) - memcpy (nand->data_cache, nand->data_buf, 256); - break; - } - } - - if (oob_config.eccvalid_pos != -1 && - nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) { - - nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]); - switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) { - case -1: - printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); - ecc_failed++; - break; - case 1: - case 2: /* transfer ECC corrected data to cache */ - if (nand->data_cache) - memcpy (&nand->data_cache[256], &nand->data_buf[256], 256); - break; - } - } -readdata: - /* Read the data from ECC data buffer into return buffer */ - data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf; - data_poi += col; - if ((*retlen + (nand->oobblock - col)) >= len) { - memcpy (buf + *retlen, data_poi, len - *retlen); - *retlen = len; - } else { - memcpy (buf + *retlen, data_poi, nand->oobblock - col); - *retlen += nand->oobblock - col; - } - /* Set cache page address, invalidate, if ecc_failed */ - nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1; - - ecc_status += ecc_failed; - ecc_failed = 0; - -#else - /* Send the read command */ - NanD_Command(nand, NAND_CMD_READ0); - if (nand->bus16) { - NanD_Address(nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address(nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - - /* Read the data directly into the return buffer */ - if ((*retlen + (nand->oobblock - col)) >= len) { - NanD_ReadBuf(nand, buf + *retlen, len - *retlen); - *retlen = len; - /* We're done */ - continue; - } else { - NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col); - *retlen += nand->oobblock - col; - } -#endif - /* For subsequent reads align to page boundary. */ - col = 0; - /* Increment page address */ - page++; - } - - /* De-select the NAND device */ - NAND_DISABLE_CE(nand); /* set pin high */ - - /* - * Return success, if no ECC failures, else -EIO - * fs driver will take care of that, because - * retlen == desired len and result == -EIO - */ - return ecc_status ? -1 : 0; -} - -/* - * Nand_page_program function is used for write and writev ! - */ -static int nand_write_page (struct nand_chip *nand, - int page, int col, int last, u_char * ecc_code) -{ - - int i; - unsigned long nandptr = nand->IO_ADDR; - -#ifdef CONFIG_MTD_NAND_ECC -#ifdef CONFIG_MTD_NAND_VERIFY_WRITE - int ecc_bytes = (nand->oobblock == 512) ? 6 : 3; -#endif -#endif - /* pad oob area */ - for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++) - nand->data_buf[i] = 0xff; - -#ifdef CONFIG_MTD_NAND_ECC - /* Zero out the ECC array */ - for (i = 0; i < 6; i++) - ecc_code[i] = 0x00; - - /* Read back previous written data, if col > 0 */ - if (col) { - NanD_Command (nand, NAND_CMD_READ0); - if (nand->bus16) { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - - if (nand->bus16) { - u16 val; - - for (i = 0; i < col; i += 2) { - val = READ_NAND (nandptr); - nand->data_buf[i] = val & 0xff; - nand->data_buf[i + 1] = val >> 8; - } - } else { - for (i = 0; i < col; i++) - nand->data_buf[i] = READ_NAND (nandptr); - } - } - - /* Calculate and write the ECC if we have enough data */ - if ((col < nand->eccsize) && (last >= nand->eccsize)) { - nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0])); - for (i = 0; i < 3; i++) { - nand->data_buf[(nand->oobblock + - oob_config.ecc_pos[i])] = ecc_code[i]; - } - if (oob_config.eccvalid_pos != -1) { - nand->data_buf[nand->oobblock + - oob_config.eccvalid_pos] = 0xf0; - } - } - - /* Calculate and write the second ECC if we have enough data */ - if ((nand->oobblock == 512) && (last == nand->oobblock)) { - nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3])); - for (i = 3; i < 6; i++) { - nand->data_buf[(nand->oobblock + - oob_config.ecc_pos[i])] = ecc_code[i]; - } - if (oob_config.eccvalid_pos != -1) { - nand->data_buf[nand->oobblock + - oob_config.eccvalid_pos] &= 0x0f; - } - } -#endif - /* Prepad for partial page programming !!! */ - for (i = 0; i < col; i++) - nand->data_buf[i] = 0xff; - - /* Postpad for partial page programming !!! oob is already padded */ - for (i = last; i < nand->oobblock; i++) - nand->data_buf[i] = 0xff; - - /* Send command to begin auto page programming */ - NanD_Command (nand, NAND_CMD_READ0); - NanD_Command (nand, NAND_CMD_SEQIN); - if (nand->bus16) { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - - /* Write out complete page of data */ - if (nand->bus16) { - for (i = 0; i < (nand->oobblock + nand->oobsize); i += 2) { - WRITE_NAND (nand->data_buf[i] + - (nand->data_buf[i + 1] << 8), - nand->IO_ADDR); - } - } else { - for (i = 0; i < (nand->oobblock + nand->oobsize); i++) - WRITE_NAND (nand->data_buf[i], nand->IO_ADDR); - } - - /* Send command to actually program the data */ - NanD_Command (nand, NAND_CMD_PAGEPROG); - NanD_Command (nand, NAND_CMD_STATUS); -#ifdef NAND_NO_RB - { - u_char ret_val; - - do { - ret_val = READ_NAND (nandptr); /* wait till ready */ - } while ((ret_val & 0x40) != 0x40); - } -#endif - /* See if device thinks it succeeded */ - if (READ_NAND (nand->IO_ADDR) & 0x01) { - printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, - page); - return -1; - } -#ifdef CONFIG_MTD_NAND_VERIFY_WRITE - /* - * The NAND device assumes that it is always writing to - * a cleanly erased page. Hence, it performs its internal - * write verification only on bits that transitioned from - * 1 to 0. The device does NOT verify the whole page on a - * byte by byte basis. It is possible that the page was - * not completely erased or the page is becoming unusable - * due to wear. The read with ECC would catch the error - * later when the ECC page check fails, but we would rather - * catch it early in the page write stage. Better to write - * no data than invalid data. - */ - - /* Send command to read back the page */ - if (col < nand->eccsize) - NanD_Command (nand, NAND_CMD_READ0); - else - NanD_Command (nand, NAND_CMD_READ1); - if (nand->bus16) { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - - /* Loop through and verify the data */ - if (nand->bus16) { - for (i = col; i < last; i = +2) { - if ((nand->data_buf[i] + - (nand->data_buf[i + 1] << 8)) != READ_NAND (nand->IO_ADDR)) { - printf ("%s: Failed write verify, page 0x%08x ", - __FUNCTION__, page); - return -1; - } - } - } else { - for (i = col; i < last; i++) { - if (nand->data_buf[i] != READ_NAND (nand->IO_ADDR)) { - printf ("%s: Failed write verify, page 0x%08x ", - __FUNCTION__, page); - return -1; - } - } - } - -#ifdef CONFIG_MTD_NAND_ECC - /* - * We also want to check that the ECC bytes wrote - * correctly for the same reasons stated above. - */ - NanD_Command (nand, NAND_CMD_READOOB); - if (nand->bus16) { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + (col >> 1)); - } else { - NanD_Address (nand, ADDR_COLUMN_PAGE, - (page << nand->page_shift) + col); - } - if (nand->bus16) { - for (i = 0; i < nand->oobsize; i += 2) { - u16 val; - - val = READ_NAND (nand->IO_ADDR); - nand->data_buf[i] = val & 0xff; - nand->data_buf[i + 1] = val >> 8; - } - } else { - for (i = 0; i < nand->oobsize; i++) { - nand->data_buf[i] = READ_NAND (nand->IO_ADDR); - } - } - for (i = 0; i < ecc_bytes; i++) { - if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) { - printf ("%s: Failed ECC write " - "verify, page 0x%08x, " - "%6i bytes were succesful\n", - __FUNCTION__, page, i); - return -1; - } - } -#endif /* CONFIG_MTD_NAND_ECC */ -#endif /* CONFIG_MTD_NAND_VERIFY_WRITE */ - return 0; -} - -static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, - size_t * retlen, const u_char * buf, u_char * ecc_code) -{ - int i, page, col, cnt, ret = 0; - - /* Do not allow write past end of device */ - if ((to + len) > nand->totlen) { - printf ("%s: Attempt to write past end of page\n", __FUNCTION__); - return -1; - } - - /* Shift to get page */ - page = ((int) to) >> nand->page_shift; - - /* Get the starting column */ - col = to & (nand->oobblock - 1); - - /* Initialize return length value */ - *retlen = 0; - - /* Select the NAND device */ -#ifdef CONFIG_OMAP1510 - archflashwp(0,0); -#endif -#ifdef CFG_NAND_WP - NAND_WP_OFF(); -#endif - - NAND_ENABLE_CE(nand); /* set pin low */ - - /* Check the WP bit */ - NanD_Command(nand, NAND_CMD_STATUS); - if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { - printf ("%s: Device is write protected!!!\n", __FUNCTION__); - ret = -1; - goto out; - } - - /* Loop until all data is written */ - while (*retlen < len) { - /* Invalidate cache, if we write to this page */ - if (nand->cache_page == page) - nand->cache_page = -1; - - /* Write data into buffer */ - if ((col + len) >= nand->oobblock) { - for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) { - nand->data_buf[i] = buf[(*retlen + cnt)]; - } - } else { - for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) { - nand->data_buf[i] = buf[(*retlen + cnt)]; - } - } - /* We use the same function for write and writev !) */ - ret = nand_write_page (nand, page, col, i, ecc_code); - if (ret) - goto out; - - /* Next data start at page boundary */ - col = 0; - - /* Update written bytes count */ - *retlen += cnt; - - /* Increment page address */ - page++; - } - - /* Return happy */ - *retlen = len; - -out: - /* De-select the NAND device */ - NAND_DISABLE_CE(nand); /* set pin high */ -#ifdef CONFIG_OMAP1510 - archflashwp(0,1); -#endif -#ifdef CFG_NAND_WP - NAND_WP_ON(); -#endif - - return ret; -} - -/* read from the 16 bytes of oob data that correspond to a 512 byte - * page or 2 256-byte pages. - */ -static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, - size_t * retlen, u_char * buf) -{ - int len256 = 0; - struct Nand *mychip; - int ret = 0; - - mychip = &nand->chips[ofs >> nand->chipshift]; - - /* update address for 2M x 8bit devices. OOB starts on the second */ - /* page to maintain compatibility with nand_read_ecc. */ - if (nand->page256) { - if (!(ofs & 0x8)) - ofs += 0x100; - else - ofs -= 0x8; - } - - NAND_ENABLE_CE(nand); /* set pin low */ - NanD_Command(nand, NAND_CMD_READOOB); - if (nand->bus16) { - NanD_Address(nand, ADDR_COLUMN_PAGE, - ((ofs >> nand->page_shift) << nand->page_shift) + - ((ofs & (nand->oobblock - 1)) >> 1)); - } else { - NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); - } - - /* treat crossing 8-byte OOB data for 2M x 8bit devices */ - /* Note: datasheet says it should automaticaly wrap to the */ - /* next OOB block, but it didn't work here. mf. */ - if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { - len256 = (ofs | 0x7) + 1 - ofs; - NanD_ReadBuf(nand, buf, len256); - - NanD_Command(nand, NAND_CMD_READOOB); - NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); - } - - NanD_ReadBuf(nand, &buf[len256], len - len256); - - *retlen = len; - /* Reading the full OOB data drops us off of the end of the page, - * causing the flash device to go into busy mode, so we need - * to wait until ready 11.4.1 and Toshiba TC58256FT nands */ - - ret = NanD_WaitReady(nand, 1); - NAND_DISABLE_CE(nand); /* set pin high */ - - return ret; - -} - -/* write to the 16 bytes of oob data that correspond to a 512 byte - * page or 2 256-byte pages. - */ -static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, - size_t * retlen, const u_char * buf) -{ - int len256 = 0; - int i; - unsigned long nandptr = nand->IO_ADDR; - -#ifdef PSYCHO_DEBUG - printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n", - (long)ofs, len, buf[0], buf[1], buf[2], buf[3], - buf[8], buf[9], buf[14],buf[15]); -#endif - - NAND_ENABLE_CE(nand); /* set pin low to enable chip */ - - /* Reset the chip */ - NanD_Command(nand, NAND_CMD_RESET); - - /* issue the Read2 command to set the pointer to the Spare Data Area. */ - NanD_Command(nand, NAND_CMD_READOOB); - if (nand->bus16) { - NanD_Address(nand, ADDR_COLUMN_PAGE, - ((ofs >> nand->page_shift) << nand->page_shift) + - ((ofs & (nand->oobblock - 1)) >> 1)); - } else { - NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); - } - - /* update address for 2M x 8bit devices. OOB starts on the second */ - /* page to maintain compatibility with nand_read_ecc. */ - if (nand->page256) { - if (!(ofs & 0x8)) - ofs += 0x100; - else - ofs -= 0x8; - } - - /* issue the Serial Data In command to initial the Page Program process */ - NanD_Command(nand, NAND_CMD_SEQIN); - if (nand->bus16) { - NanD_Address(nand, ADDR_COLUMN_PAGE, - ((ofs >> nand->page_shift) << nand->page_shift) + - ((ofs & (nand->oobblock - 1)) >> 1)); - } else { - NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); - } - - /* treat crossing 8-byte OOB data for 2M x 8bit devices */ - /* Note: datasheet says it should automaticaly wrap to the */ - /* next OOB block, but it didn't work here. mf. */ - if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { - len256 = (ofs | 0x7) + 1 - ofs; - for (i = 0; i < len256; i++) - WRITE_NAND(buf[i], nandptr); - - NanD_Command(nand, NAND_CMD_PAGEPROG); - NanD_Command(nand, NAND_CMD_STATUS); -#ifdef NAND_NO_RB - { u_char ret_val; - do { - ret_val = READ_NAND(nandptr); /* wait till ready */ - } while ((ret_val & 0x40) != 0x40); - } -#endif - if (READ_NAND(nandptr) & 1) { - puts ("Error programming oob data\n"); - /* There was an error */ - NAND_DISABLE_CE(nand); /* set pin high */ - *retlen = 0; - return -1; - } - NanD_Command(nand, NAND_CMD_SEQIN); - NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); - } - - if (nand->bus16) { - for (i = len256; i < len; i += 2) { - WRITE_NAND(buf[i] + (buf[i+1] << 8), nandptr); - } - } else { - for (i = len256; i < len; i++) - WRITE_NAND(buf[i], nandptr); - } - - NanD_Command(nand, NAND_CMD_PAGEPROG); - NanD_Command(nand, NAND_CMD_STATUS); -#ifdef NAND_NO_RB - { u_char ret_val; - do { - ret_val = READ_NAND(nandptr); /* wait till ready */ - } while ((ret_val & 0x40) != 0x40); - } -#endif - if (READ_NAND(nandptr) & 1) { - puts ("Error programming oob data\n"); - /* There was an error */ - NAND_DISABLE_CE(nand); /* set pin high */ - *retlen = 0; - return -1; - } - - NAND_DISABLE_CE(nand); /* set pin high */ - *retlen = len; - return 0; - -} - -int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean) -{ - /* This is defined as a structure so it will work on any system - * using native endian jffs2 (the default). - */ - static struct jffs2_unknown_node clean_marker = { - JFFS2_MAGIC_BITMASK, - JFFS2_NODETYPE_CLEANMARKER, - 8 /* 8 bytes in this node */ - }; - unsigned long nandptr; - struct Nand *mychip; - int ret = 0; - - if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) { - printf ("Offset and size must be sector aligned, erasesize = %d\n", - (int) nand->erasesize); - return -1; - } - - nandptr = nand->IO_ADDR; - - /* Select the NAND device */ -#ifdef CONFIG_OMAP1510 - archflashwp(0,0); -#endif -#ifdef CFG_NAND_WP - NAND_WP_OFF(); -#endif - NAND_ENABLE_CE(nand); /* set pin low */ - - /* Check the WP bit */ - NanD_Command(nand, NAND_CMD_STATUS); - if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { - printf ("nand_write_ecc: Device is write protected!!!\n"); - ret = -1; - goto out; - } - - /* Check the WP bit */ - NanD_Command(nand, NAND_CMD_STATUS); - if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { - printf ("%s: Device is write protected!!!\n", __FUNCTION__); - ret = -1; - goto out; - } - - /* FIXME: Do nand in the background. Use timers or schedule_task() */ - while(len) { - /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/ - mychip = &nand->chips[ofs >> nand->chipshift]; - - /* always check for bad block first, genuine bad blocks - * should _never_ be erased. - */ - if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) { - /* Select the NAND device */ - NAND_ENABLE_CE(nand); /* set pin low */ - - NanD_Command(nand, NAND_CMD_ERASE1); - NanD_Address(nand, ADDR_PAGE, ofs); - NanD_Command(nand, NAND_CMD_ERASE2); - - NanD_Command(nand, NAND_CMD_STATUS); - -#ifdef NAND_NO_RB - { u_char ret_val; - do { - ret_val = READ_NAND(nandptr); /* wait till ready */ - } while ((ret_val & 0x40) != 0x40); - } -#endif - if (READ_NAND(nandptr) & 1) { - printf ("%s: Error erasing at 0x%lx\n", - __FUNCTION__, (long)ofs); - /* There was an error */ - ret = -1; - goto out; - } - if (clean) { - int n; /* return value not used */ - int p, l; - - /* clean marker position and size depend - * on the page size, since 256 byte pages - * only have 8 bytes of oob data - */ - if (nand->page256) { - p = NAND_JFFS2_OOB8_FSDAPOS; - l = NAND_JFFS2_OOB8_FSDALEN; - } else { - p = NAND_JFFS2_OOB16_FSDAPOS; - l = NAND_JFFS2_OOB16_FSDALEN; - } - - ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n, - (u_char *)&clean_marker); - /* quit here if write failed */ - if (ret) - goto out; - } - } - ofs += nand->erasesize; - len -= nand->erasesize; - } - -out: - /* De-select the NAND device */ - NAND_DISABLE_CE(nand); /* set pin high */ -#ifdef CONFIG_OMAP1510 - archflashwp(0,1); -#endif -#ifdef CFG_NAND_WP - NAND_WP_ON(); -#endif - - return ret; -} - -static inline int nandcheck(unsigned long potential, unsigned long physadr) -{ - return 0; -} - -unsigned long nand_probe(unsigned long physadr) -{ - struct nand_chip *nand = NULL; - int i = 0, ChipID = 1; - -#ifdef CONFIG_MTD_NAND_ECC_JFFS2 - oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0; - oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1; - oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2; - oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3; - oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4; - oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5; - oob_config.eccvalid_pos = 4; -#else - oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0; - oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1; - oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2; - oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3; - oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4; - oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5; - oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS; -#endif - oob_config.badblock_pos = 5; - - for (i=0; iIO_ADDR = physadr; - nand->cache_page = -1; /* init the cache page */ - NanD_ScanChips(nand); - - if (nand->totlen == 0) { - /* no chips found, clean up and quit */ - memset((char *)nand, 0, sizeof(struct nand_chip)); - nand->ChipID = NAND_ChipID_UNKNOWN; - return (0); - } - - nand->ChipID = ChipID; - if (curr_device == -1) - curr_device = i; - - nand->data_buf = malloc (nand->oobblock + nand->oobsize); - if (!nand->data_buf) { - puts ("Cannot allocate memory for data structures.\n"); - return (0); - } - - return (nand->totlen); -} - -#ifdef CONFIG_MTD_NAND_ECC -/* - * Pre-calculated 256-way 1 byte column parity - */ -static const u_char nand_ecc_precalc_table[] = { - 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, - 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, - 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, - 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, - 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, - 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, - 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, - 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, - 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, - 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, - 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, - 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, - 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, - 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, - 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, - 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, - 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, - 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, - 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, - 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, - 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, - 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, - 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, - 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, - 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, - 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, - 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, - 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, - 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, - 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, - 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, - 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 -}; - - -/* - * Creates non-inverted ECC code from line parity - */ -static void nand_trans_result(u_char reg2, u_char reg3, - u_char *ecc_code) -{ - u_char a, b, i, tmp1, tmp2; - - /* Initialize variables */ - a = b = 0x80; - tmp1 = tmp2 = 0; - - /* Calculate first ECC byte */ - for (i = 0; i < 4; i++) { - if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ - tmp1 |= b; - b >>= 1; - if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ - tmp1 |= b; - b >>= 1; - a >>= 1; - } - - /* Calculate second ECC byte */ - b = 0x80; - for (i = 0; i < 4; i++) { - if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ - tmp2 |= b; - b >>= 1; - if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ - tmp2 |= b; - b >>= 1; - a >>= 1; - } - - /* Store two of the ECC bytes */ - ecc_code[0] = tmp1; - ecc_code[1] = tmp2; -} - -/* - * Calculate 3 byte ECC code for 256 byte block - */ -static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) -{ - u_char idx, reg1, reg3; - int j; - - /* Initialize variables */ - reg1 = reg3 = 0; - ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; - - /* Build up column parity */ - for(j = 0; j < 256; j++) { - - /* Get CP0 - CP5 from table */ - idx = nand_ecc_precalc_table[dat[j]]; - reg1 ^= idx; - - /* All bit XOR = 1 ? */ - if (idx & 0x40) { - reg3 ^= (u_char) j; - } - } - - /* Create non-inverted ECC code from line parity */ - nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code); - - /* Calculate final ECC code */ - ecc_code[0] = ~ecc_code[0]; - ecc_code[1] = ~ecc_code[1]; - ecc_code[2] = ((~reg1) << 2) | 0x03; -} - -/* - * Detect and correct a 1 bit error for 256 byte block - */ -static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc) -{ - u_char a, b, c, d1, d2, d3, add, bit, i; - - /* Do error detection */ - d1 = calc_ecc[0] ^ read_ecc[0]; - d2 = calc_ecc[1] ^ read_ecc[1]; - d3 = calc_ecc[2] ^ read_ecc[2]; - - if ((d1 | d2 | d3) == 0) { - /* No errors */ - return 0; - } else { - a = (d1 ^ (d1 >> 1)) & 0x55; - b = (d2 ^ (d2 >> 1)) & 0x55; - c = (d3 ^ (d3 >> 1)) & 0x54; - - /* Found and will correct single bit error in the data */ - if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { - c = 0x80; - add = 0; - a = 0x80; - for (i=0; i<4; i++) { - if (d1 & c) - add |= a; - c >>= 2; - a >>= 1; - } - c = 0x80; - for (i=0; i<4; i++) { - if (d2 & c) - add |= a; - c >>= 2; - a >>= 1; - } - bit = 0; - b = 0x04; - c = 0x80; - for (i=0; i<3; i++) { - if (d3 & c) - bit |= b; - c >>= 2; - b >>= 1; - } - b = 0x01; - a = dat[add]; - a ^= (b << bit); - dat[add] = a; - return 1; - } - else { - i = 0; - while (d1) { - if (d1 & 0x01) - ++i; - d1 >>= 1; - } - while (d2) { - if (d2 & 0x01) - ++i; - d2 >>= 1; - } - while (d3) { - if (d3 & 0x01) - ++i; - d3 >>= 1; - } - if (i == 1) { - /* ECC Code Error Correction */ - read_ecc[0] = calc_ecc[0]; - read_ecc[1] = calc_ecc[1]; - read_ecc[2] = calc_ecc[2]; - return 2; - } - else { - /* Uncorrectable Error */ - return -1; - } - } - } - - /* Should never happen */ - return -1; -} - -#endif - -#ifdef CONFIG_JFFS2_NAND - -int read_jffs2_nand(size_t start, size_t len, - size_t * retlen, u_char * buf, int nanddev) -{ - return nand_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2, - start, len, retlen, buf); -} - -#endif /* CONFIG_JFFS2_NAND */ - - #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ + +#endif /* CFG_NAND_LEGACY */ diff --git a/common/cmd_net.c b/common/cmd_net.c index 2cb2c5d..0819293 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -163,7 +163,7 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) load_addr = simple_strtoul(s, NULL, 16); } - switch (argc) { + switch (argc) { case 1: break; @@ -187,7 +187,8 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) return 1; } - if ((size = NetLoop(proto)) < 0) + size = NetLoop(proto); + if (size < 0) return 1; /* NetLoop ok, update environment */ diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 1babffe..c8c1ced 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -289,7 +289,6 @@ int _do_setenv (int flag, int argc, char *argv[]) env_crc_update (); return 0; } - /* * Append new definition at the end */ @@ -530,7 +529,7 @@ int getenv_r (char *name, char *buf, unsigned len) return (-1); } -#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ +#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || defined(CFG_ENV_IS_IN_NAND) || \ ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \ (CFG_CMD_ENV|CFG_CMD_FLASH)) int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -586,7 +585,7 @@ U_BOOT_CMD( " - delete environment variable 'name'\n" ); -#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ +#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || defined(CFG_ENV_IS_IN_NAND) || \ ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \ (CFG_CMD_ENV|CFG_CMD_FLASH)) U_BOOT_CMD( diff --git a/common/cmd_pci.c b/common/cmd_pci.c index 4508546..a50ae29 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -89,10 +89,11 @@ void pciinfo(int BusNum, int ShortPCIListing) break; dev = PCI_BDF(BusNum, Device, Function); - pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID); if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) - continue; + { + continue; + } if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType); diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index e804861..3df5ce3 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -27,12 +27,16 @@ /* * SCSI support. */ + +/* #define DEBUG */ + #include #include #include #include #include #include +#include #if (CONFIG_COMMANDS & CFG_CMD_SCSI) @@ -43,8 +47,18 @@ #else #define SCSI_DEV_ID CONFIG_SCSI_DEV_ID #endif +#elif defined CONFIG_SATA_ULI5288 + +#define SCSI_VEND_ID 0x10b9 +#define SCSI_DEV_ID 0x5288 + +#elif defined CONFIG_SATA_6121 + +#define SCSI_VEND_ID 0x11ab +#define SCSI_DEV_ID 0x6121 + #else -#error CONFIG_SCSI_SYM53C8XX must be defined +#error no scsi device defined #endif diff --git a/common/cmd_usb.c b/common/cmd_usb.c index fdfd042..2001632 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -29,7 +29,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_USB) +#if (CONFIG_COMMANDS & CFG_CMD_USB) && CONFIG_CMD_USB #include @@ -278,7 +278,8 @@ void usb_show_tree_graph(struct usb_device *dev,char *pre) pre[index++]= has_child ? '|' : ' '; pre[index]=0; printf(" %s (%s, %dmA)\n",usb_get_class_desc(dev->config.if_desc[0].bInterfaceClass), - dev->slow ? "1.5MBit/s" : "12MBit/s",dev->config.MaxPower * 2); + (dev->speed == USB_SPEED_LOW) ? "1.5MBit/s" : (dev->speed == USB_SPEED_FULL) + ? "12MBit/s" : "480MBit/s", dev->config.MaxPower * 2); if (strlen(dev->mf) || strlen(dev->prod) || strlen(dev->serial)) @@ -456,7 +457,12 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #ifdef CONFIG_USB_STORAGE /* try to recognize storage devices immediately */ if (i >= 0) - usb_stor_curr_dev = usb_stor_scan(1); + { + /* Some of Mass Storage devices require up to 5 sec delay after setConfiguration */ + printf("Waiting for storage device(s) to settle before scanning...\n"); + wait_ms(5000); + usb_stor_curr_dev = usb_stor_scan(); + } #endif return 0; } @@ -603,24 +609,19 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } -#endif /* (CONFIG_COMMANDS & CFG_CMD_USB) */ - - -#if (CONFIG_COMMANDS & CFG_CMD_USB) - #ifdef CONFIG_USB_STORAGE U_BOOT_CMD( usb, 5, 1, do_usb, "usb - USB sub-system\n", - "reset - reset (rescan) USB controller\n" - "usb stop [f] - stop USB [f]=force stop\n" + "usb start - start the usb interface, including scan of the bus. Must be\n" + " executed prior to using the USB, and should be executed only once.\n" "usb tree - show USB device tree\n" "usb info [dev] - show available USB devices\n" "usb storage - show details of USB storage devices\n" "usb dev [dev] - show or set current USB storage device\n" "usb part [dev] - print partition table of one or all USB storage devices\n" "usb read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n" - " to memory address `addr'\n" + " to memory address `addr'\n" ); diff --git a/common/env_common.c b/common/env_common.c index 3201135..4eac781 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -136,6 +136,7 @@ uchar default_environment[] = { #ifdef CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_SETTINGS #endif + "run_diag=" "yes" "\0" "\0" }; @@ -258,7 +259,13 @@ void env_relocate (void) gd->env_valid = 1; } else { +#ifdef CONFIG_MARVELL + mvMPPConfigToSPI(); env_relocate_spec (); + mvMPPConfigToDefault(); +#else + env_relocate_spec (); +#endif } gd->env_addr = (ulong)&(env_ptr->data); @@ -307,3 +314,43 @@ int env_complete(char *var, int maxv, char *cmdv[], int bufsz, char *buf) return found; } #endif + +#if defined(CONFIG_BUFFALO_PLATFORM) +void +bfKeepEthAddr(void) +{ + extern env_t *env_ptr; + env_t tmp_env; + char *env; + char ethaddr[18]; + char eth1addr[18]; + + memset(ethaddr, 0, sizeof(ethaddr)); + memset(eth1addr, 0, sizeof(eth1addr)); + + env = getenv("ethaddr"); + if (env) + strcpy(ethaddr, env); + + env = getenv("eth1addr"); + if (env) + strcpy(eth1addr, env); + + tmp_env = *env_ptr; + memcpy(env_ptr->data, default_environment, sizeof(default_environment)); + + if (ethaddr[0] && strncmp(ethaddr, "00:50:43", 8) != 0) { + setenv("ethaddr", ethaddr); + } + + if (eth1addr[0] && strncmp(eth1addr, "00:50:43", 8) != 0) { + setenv("eth1addr", eth1addr); + } + + env_crc_update(); + if (saveenv() != 0) + printf("%s > saveenv failed.\n", __FUNCTION__); + + *env_ptr = tmp_env; +} +#endif diff --git a/common/env_flash.c b/common/env_flash.c index a2ea9c4..67c6b49 100644 --- a/common/env_flash.c +++ b/common/env_flash.c @@ -160,6 +160,14 @@ int saveenv(void) ulong up_data = 0; #endif +#ifdef CONFIG_MARVELL + if (whoAmI()) + { + puts ("Only Master CPU can saveenv!\n"); + return 0; + } +#endif + debug ("Protect off %08lX ... %08lX\n", (ulong)flash_addr, end_addr); @@ -261,15 +269,25 @@ Done: int env_init(void) { DECLARE_GLOBAL_DATA_PTR; + unsigned int tmpBuf[CFG_ENV_SIZE]; #ifdef CONFIG_OMAP2420H4 int flash_probe(void); if(flash_probe() == 0) goto bad_flash; #endif - if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { - gd->env_addr = (ulong)&(env_ptr->data); - gd->env_valid = 1; +#if defined(CONFIG_MARVELL) && defined(MV_SPI_BOOT) + mvMPPConfigToSPI(); + memcpyFlash(env_ptr, tmpBuf, CFG_ENV_SIZE); + if (crc32(0, &tmpBuf[1], ENV_SIZE) == tmpBuf[0]) { + gd->env_addr = (ulong)&(env_ptr->data); + gd->env_valid = 1; + mvMPPConfigToDefault(); +#else + if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { + gd->env_addr = (ulong)&(env_ptr->data); + gd->env_valid = 1; +#endif return(0); } #ifdef CONFIG_OMAP2420H4 @@ -295,6 +313,14 @@ int saveenv(void) #endif /* CFG_ENV_SECT_SIZE */ int rcode = 0; +#ifdef CONFIG_MARVELL + if (whoAmI()) + { + puts ("Only Master CPU can saveenv!\n"); + return 0; + } +#endif + #if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE) flash_offset = ((ulong)flash_addr) & (CFG_ENV_SECT_SIZE-1); @@ -305,7 +331,11 @@ int saveenv(void) flash_sect_addr, (ulong)flash_addr, flash_offset); /* copy old contents to temporary buffer */ +#if defined(CONFIG_MARVELL) && defined(MV_SPI_BOOT) + memcpyFlash(flash_sect_addr, (void*)env_buffer, CFG_ENV_SECT_SIZE); +#else memcpy (env_buffer, (void *)flash_sect_addr, CFG_ENV_SECT_SIZE); +#endif /* copy current environment to temporary buffer */ memcpy ((uchar *)((unsigned long)env_buffer + flash_offset), @@ -400,7 +430,11 @@ void env_relocate_spec (void) puts ("*** Warning - some problems detected " "reading environment; recovered successfully\n\n"); #endif /* CFG_ENV_ADDR_REDUND */ +#if defined(CONFIG_MARVELL) && defined(MV_SPI_BOOT) + memcpyFlash(flash_addr, (void*)env_ptr, CFG_ENV_SIZE); +#else memcpy (env_ptr, (void*)flash_addr, CFG_ENV_SIZE); +#endif #endif /* ! ENV_IS_EMBEDDED || CFG_ENV_ADDR_REDUND */ } diff --git a/common/env_nand.c b/common/env_nand.c index 60aba1e..0d85271 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -2,7 +2,7 @@ * (C) Copyright 2004 * Jian Zhang, Texas Instruments, jzhang@ti.com. - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH @@ -36,42 +36,36 @@ #include #include #include -#include +#include +#include #if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_NAND)) == (CFG_CMD_ENV|CFG_CMD_NAND)) #define CMD_SAVEENV +#elif defined(CFG_ENV_OFFSET_REDUND) +#error Cannot use CFG_ENV_OFFSET_REDUND without CFG_CMD_ENV & CFG_CMD_NAND #endif -#if defined(CFG_ENV_SIZE_REDUND) -#error CFG_ENV_SIZE_REDUND not supported yet +#if defined(CFG_ENV_SIZE_REDUND) && (CFG_ENV_SIZE_REDUND != CFG_ENV_SIZE) +#error CFG_ENV_SIZE_REDUND should be the same as CFG_ENV_SIZE #endif -#if defined(CFG_ENV_ADDR_REDUND) -#error CFG_ENV_ADDR_REDUND and CFG_ENV_IS_IN_NAND not supported yet -#endif - - #ifdef CONFIG_INFERNO #error CONFIG_INFERNO not supported yet #endif -/* references to names in cmd_nand.c */ -#define NANDRW_READ 0x01 -#define NANDRW_WRITE 0x00 -#define NANDRW_JFFS2 0x02 -extern struct nand_chip nand_dev_desc[]; -int nand_rw (struct nand_chip* nand, int cmd, +int nand_legacy_rw (struct nand_chip* nand, int cmd, size_t start, size_t len, size_t * retlen, u_char * buf); -int nand_erase(struct nand_chip* nand, size_t ofs, - size_t len, int clean); + +/* info for NAND chips, defined in drivers/nand/nand.c */ +extern nand_info_t nand_info[]; /* references to names in env_common.c */ extern uchar default_environment[]; extern int default_environment_size; char * env_name_spec = "NAND"; - +extern int nandenvECC; #ifdef ENV_IS_EMBEDDED extern uchar environment[]; @@ -82,13 +76,14 @@ env_t *env_ptr = 0; /* local functions */ +#if !defined(ENV_IS_EMBEDDED) static void use_default(void); +#endif +DECLARE_GLOBAL_DATA_PTR; uchar env_get_char_spec (int index) { - DECLARE_GLOBAL_DATA_PTR; - return ( *((uchar *)(gd->env_addr + index)) ); } @@ -98,62 +93,260 @@ uchar env_get_char_spec (int index) * Mark it OK for now. env_relocate() in env_common.c * will call our relocate function which will does * the real validation. + * + * When using a NAND boot image (like sequoia_nand), the environment + * can be embedded or attached to the U-Boot image in NAND flash. This way + * the SPL loads not only the U-Boot image from NAND but also the + * environment. */ int env_init(void) { - DECLARE_GLOBAL_DATA_PTR; +#if defined(ENV_IS_EMBEDDED) + ulong total; + int crc1_ok = 0, crc2_ok = 0; + env_t *tmp_env1, *tmp_env2; - gd->env_addr = (ulong)&default_environment[0]; + total = CFG_ENV_SIZE; + + tmp_env1 = env_ptr; + tmp_env2 = (env_t *)((ulong)env_ptr + CFG_ENV_SIZE); + + crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc); + crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc); + + if (!crc1_ok && !crc2_ok) + gd->env_valid = 0; + else if(crc1_ok && !crc2_ok) + gd->env_valid = 1; + else if(!crc1_ok && crc2_ok) + gd->env_valid = 2; + else { + /* both ok - check serial */ + if(tmp_env1->flags == 255 && tmp_env2->flags == 0) + gd->env_valid = 2; + else if(tmp_env2->flags == 255 && tmp_env1->flags == 0) + gd->env_valid = 1; + else if(tmp_env1->flags > tmp_env2->flags) + gd->env_valid = 1; + else if(tmp_env2->flags > tmp_env1->flags) + gd->env_valid = 2; + else /* flags are equal - almost impossible */ + gd->env_valid = 1; + } + + if (gd->env_valid == 1) + env_ptr = tmp_env1; + else if (gd->env_valid == 2) + env_ptr = tmp_env2; +#else /* ENV_IS_EMBEDDED */ + gd->env_addr = (ulong)&default_environment[0]; gd->env_valid = 1; +#if defined(CONFIG_MARVELL) +// gd->env_addr = CFG_ENV_ADDR; +#endif /* defined(CONFIG_MARVELL) */ +#endif /* ENV_IS_EMBEDDED */ return (0); } #ifdef CMD_SAVEENV +/* + * The legacy NAND code saved the environment in the first NAND device i.e., + * nand_dev_desc + 0. This is also the behaviour using the new NAND code. + */ +#ifdef CFG_ENV_OFFSET_REDUND int saveenv(void) { - int total, ret = 0; - puts ("Erasing Nand..."); - if (nand_erase(nand_dev_desc + 0, CFG_ENV_OFFSET, CFG_ENV_SIZE, 0)) - return 1; + ulong total; + int ret = 0; - puts ("Writing to Nand... "); - ret = nand_rw(nand_dev_desc + 0, - NANDRW_WRITE | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE, - &total, (u_char*)env_ptr); - if (ret || total != CFG_ENV_SIZE) + env_ptr->flags++; + total = CFG_ENV_SIZE; + + if(gd->env_valid == 1) { + puts ("Erasing redundant Nand..."); + if (nand_erase(&nand_info[0], + CFG_ENV_OFFSET_REDUND, CFG_ENV_SIZE)) + return 1; + puts ("Writing to redundant Nand... "); + ret = nand_write(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total, + (u_char*) env_ptr); + } else { + puts ("Erasing Nand..."); + if (nand_erase(&nand_info[0], + CFG_ENV_OFFSET, CFG_ENV_SIZE)) + return 1; + + puts ("Writing to Nand... "); + ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, + (u_char*) env_ptr); + } + if (ret || total != CFG_ENV_SIZE) return 1; - puts ("done\n"); - return ret; + puts ("done\n"); + gd->env_valid = (gd->env_valid == 2 ? 1 : 2); + return ret; } +#else /* ! CFG_ENV_OFFSET_REDUND */ +int saveenv(void) +{ + ulong total; + int ret = 0, eccEnv = 0, i = 0, goodBlockCounter = 0; + +#ifdef CONFIG_MARVELL + if (whoAmI()) + { + puts ("Only Master CPU can saveenv!\n"); + return 0; + } +#endif + + /* The environment has Reed-Solomon ECC protection in the NAND */ + nandenvECC = 1; + + puts ("Erasing Nand..."); +#ifndef MV78XX0 + while(i * nand_info[0].erasesize < nand_info[0].size) + { + if(nand_info[0].block_isbad(&nand_info[0], i * nand_info[0].erasesize) == 0) + goodBlockCounter++; + if((goodBlockCounter * nand_info[0].erasesize) >= CFG_ENV_OFFSET + CFG_ENV_SECT_SIZE) + break; + i++; + } + if (nand_erase(&nand_info[0], i * nand_info[0].erasesize, CFG_ENV_SIZE)) +#else + if (nand_erase(&nand_info[0], CFG_ENV_OFFSET, CFG_ENV_SIZE)) +#endif + { + nandenvECC = 0; + return 1; + } + + puts ("Writing to Nand... "); + total = CFG_ENV_SIZE; +#ifndef MV78XX0 + ret = nand_write(&nand_info[0], i * nand_info[0].erasesize, &total, (u_char*)env_ptr); +#else + ret = nand_write(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); +#endif + if (ret || total != CFG_ENV_SIZE) + { + nandenvECC = 0; + return 1; + } + + nandenvECC = 0; + + puts ("done\n"); + return ret; +} +#endif /* CFG_ENV_OFFSET_REDUND */ #endif /* CMD_SAVEENV */ +#ifdef CFG_ENV_OFFSET_REDUND +void env_relocate_spec (void) +{ +#if !defined(ENV_IS_EMBEDDED) + ulong total; + int crc1_ok = 0, crc2_ok = 0; + env_t *tmp_env1, *tmp_env2; + + total = CFG_ENV_SIZE; + + tmp_env1 = (env_t *) malloc(CFG_ENV_SIZE); + tmp_env2 = (env_t *) malloc(CFG_ENV_SIZE); + + nand_read(&nand_info[0], CFG_ENV_OFFSET, &total, + (u_char*) tmp_env1); + nand_read(&nand_info[0], CFG_ENV_OFFSET_REDUND, &total, + (u_char*) tmp_env2); + + crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc); + crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc); + + if(!crc1_ok && !crc2_ok) + return use_default(); + else if(crc1_ok && !crc2_ok) + gd->env_valid = 1; + else if(!crc1_ok && crc2_ok) + gd->env_valid = 2; + else { + /* both ok - check serial */ + if(tmp_env1->flags == 255 && tmp_env2->flags == 0) + gd->env_valid = 2; + else if(tmp_env2->flags == 255 && tmp_env1->flags == 0) + gd->env_valid = 1; + else if(tmp_env1->flags > tmp_env2->flags) + gd->env_valid = 1; + else if(tmp_env2->flags > tmp_env1->flags) + gd->env_valid = 2; + else /* flags are equal - almost impossible */ + gd->env_valid = 1; + + } + + free(env_ptr); + if(gd->env_valid == 1) { + env_ptr = tmp_env1; + free(tmp_env2); + } else { + env_ptr = tmp_env2; + free(tmp_env1); + } + +#endif /* ! ENV_IS_EMBEDDED */ +} +#else /* ! CFG_ENV_OFFSET_REDUND */ +/* + * The legacy NAND code saved the environment in the first NAND device i.e., + * nand_dev_desc + 0. This is also the behaviour using the new NAND code. + */ +uint nandEnvBase = 0; void env_relocate_spec (void) { #if !defined(ENV_IS_EMBEDDED) - int ret, total; + ulong total; + int ret, i = 0, goodBlockCounter = 0; - ret = nand_rw(nand_dev_desc + 0, - NANDRW_READ | NANDRW_JFFS2, CFG_ENV_OFFSET, CFG_ENV_SIZE, - &total, (u_char*)env_ptr); - if (ret || total != CFG_ENV_SIZE) + /* The environment has Reed-Solomon ECC protection in the NAND */ + nandenvECC = 1; + total = CFG_ENV_SIZE; +#ifndef MV78XX0 + while(i * nand_info[0].erasesize < nand_info[0].size) + { + if(nand_info[0].block_isbad(&nand_info[0], i * nand_info[0].erasesize) == 0) + goodBlockCounter++; + if((goodBlockCounter * nand_info[0].erasesize) >= CFG_ENV_OFFSET + CFG_ENV_SECT_SIZE) + break; + i++; + } + ret = nand_read(&nand_info[0], i * nand_info[0].erasesize, &total, (u_char*)env_ptr); + nandEnvBase = i * nand_info[0].erasesize; +#else + ret = nand_read(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); +#endif + /* Set environment base offset variable to be used by Linux to locate the environment */ + + nandenvECC = 0; + + if (ret || total != CFG_ENV_SIZE) return use_default(); if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc) return use_default(); #endif /* ! ENV_IS_EMBEDDED */ - } +#endif /* CFG_ENV_OFFSET_REDUND */ +#if !defined(ENV_IS_EMBEDDED) static void use_default() { - DECLARE_GLOBAL_DATA_PTR; - puts ("*** Warning - bad CRC or NAND, using default environment\n\n"); - if (default_environment_size > CFG_ENV_SIZE){ + if (default_environment_size > CFG_ENV_SIZE){ puts ("*** Error - default environment is too large\n\n"); return; } @@ -163,8 +356,9 @@ static void use_default() default_environment, default_environment_size); env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); - gd->env_valid = 1; + gd->env_valid = 1; } +#endif #endif /* CFG_ENV_IS_IN_NAND */ diff --git a/common/exports.c b/common/exports.c index 9858217..42406e0 100644 --- a/common/exports.c +++ b/common/exports.c @@ -28,6 +28,14 @@ void jumptable_init (void) gd->jt[XF_install_hdlr] = (void *) irq_install_handler; gd->jt[XF_free_hdlr] = (void *) irq_free_handler; #endif /* I386 || PPC */ +#ifdef CONFIG_MARVELL + gd->jt[XF_calloc] = (void *) calloc; + gd->jt[XF_realloc] = (void *) realloc; + gd->jt[XF_memalign] = (void *) memalign; +#ifndef MV_TINY_IMAGE + gd->jt[XF_mvGetRtcSec] = (void *) mvGetRtcSec; +#endif +#endif #if (CONFIG_COMMANDS & CFG_CMD_I2C) gd->jt[XF_i2c_write] = (void *) i2c_write; gd->jt[XF_i2c_read] = (void *) i2c_read; diff --git a/common/flash.c b/common/flash.c index a64bc98..c173a67 100644 --- a/common/flash.c +++ b/common/flash.c @@ -21,7 +21,7 @@ * MA 02111-1307 USA */ -/* #define DEBUG */ +/* #define DEBUG */ #include #include diff --git a/common/main.c b/common/main.c index f042f3a..9c2b4cb 100644 --- a/common/main.c +++ b/common/main.c @@ -36,12 +36,15 @@ #include + #if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY) extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* for do_reset() prototype */ #endif extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - +#if defined(CONFIG_MARVELL) +extern unsigned int whoAmI(void); +#endif #define MAX_DELAY_STOP_STR 32 @@ -73,6 +76,7 @@ static int retry_time = -1; /* -1 so can call readline before main_loop */ int do_mdm_init = 0; extern void mdm_init(void); /* defined in board.c */ #endif +extern int g_stack_cachable; /*************************************************************************** * Watch for 'delay' seconds for autoboot stop or autoboot delay string. @@ -323,10 +327,18 @@ void main_loop (void) char bcs_set[16]; #endif /* CONFIG_BOOTCOUNT_LIMIT */ +#if defined(CONFIG_MARVELL) + if (g_stack_cachable == 1) + {/* set the stack to be cachable */ + __asm__ __volatile__ ( " orr sp, sp, #0x80000000 " : ); + } +#endif /* CONFIG_MARVELL */ #if defined(CONFIG_VFD) && defined(VFD_TEST_LOGO) ulong bmp = 0; /* default bitmap */ extern int trab_vfd (ulong bitmap); + + #ifdef CONFIG_MODEM_SUPPORT if (do_mdm_init) bmp = 1; /* alternate bitmap */ @@ -408,21 +420,87 @@ void main_loop (void) } else #endif /* CONFIG_BOOTCOUNT_LIMIT */ +#if defined(CONFIG_MARVELL) +#ifdef MV78XX0 + if (whoAmI() == 0) +#endif + { s = getenv ("bootcmd"); + } +#ifdef MV78200 + else + { + s = getenv ("bootcmd2"); + } +#endif +#else + s = getenv ("bootcmd"); +#endif +#if defined(CONFIG_BUFFALO_PLATFORM) + char *env = getenv("force_tftp"); + + if (env && !strcmp(env, "1") && getenv("tftpbootcmd")) { + printf("*** TFTP boot mode\n"); + s = getenv("tftpbootcmd"); + } + else { + printf("hit any key to switch tftp boot.\n"); + if (getenv("tftpbootcmd") && abortboot(2)){ + printf("switched to TFTP boot.\n"); + s = getenv("tftpbootcmd"); + } + } + + setenv("force_tftp", NULL); +#endif // !defined(CONFIG_BUFFALO_PLATFORM) debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : ""); +#if defined (CONFIG_MARVELL) && (defined(MV_88F6183) || defined(MV_88F6183L)) + /* 6183 UART work around - need incase uart pin's left unconnected */ + if (tstc()) + (void) getc(); /* consume input */ +#endif +#if defined (RD_88F6281A_SHEEVA_PLUG) + (*((volatile unsigned int*)(0xf1010140))) &= (~0x20000); +#endif if (bootdelay >= 0 && s && !abortboot (bootdelay)) { # ifdef CONFIG_AUTOBOOT_KEYED int prev = disable_ctrlc(1); /* disable Control C checking */ # endif -# ifndef CFG_HUSH_PARSER +# if defined(CONFIG_BUFFALO_PLATFORM) +# if !defined(CFG_HUSH_PARSER) + rc = run_command (s, 0); + if (rc == -1) { + extern void bfDispAllInitrdError(void); + bfDispAllInitrdError(); + if (!abortboot(3)) { + s = getenv("tftpbootcmd"); + rc = run_command(s, 0); + } + } +# else // !defined(CFG_HUSH_PARSER) + int rc = parse_string_outer(s, FLAG_PARSE_SEMICOLON | + FLAG_EXIT_FROM_LOOP); + if (rc != 0) { + extern void bfDispAllInitrdError(void); + bfDispAllInitrdError(); + if (!abortboot(3)) { + s = getenv("tftpbootcmd"); + parse_string_outer(s, FLAG_PARSE_SEMICOLON | + FLAG_EXIT_FROM_LOOP); + } + } +# endif // defined(CFG_HUSH_PARSER) +# else // !defined(CONFIG_BUFFALO_PLATFORM) +# ifndef CFG_HUSH_PARSER run_command (s, 0); -# else +# else parse_string_outer(s, FLAG_PARSE_SEMICOLON | - FLAG_EXIT_FROM_LOOP); -# endif + FLAG_EXIT_FROM_LOOP); +# endif +# endif // defined(CONFIG_BUFFALO_PLATFORM) # ifdef CONFIG_AUTOBOOT_KEYED disable_ctrlc(prev); /* restore Control C checking */ @@ -921,6 +999,19 @@ int run_command (const char *cmd, int flag) /* Extract arguments */ argc = parse_line (finaltoken, argv); + #if defined(CONFIG_MARVELL) + if(enaMonExt()){ + if ((cmdtp = find_cmd(argv[0])) == NULL) { + int i; + argv[argc+1]= NULL; + for(i = argc; i > 0; i--){ + argv[i] = argv[i-1];} + argv[0] = "FSrun"; + argc++; + } + } + #endif + /* Look up command in command table */ if ((cmdtp = find_cmd(argv[0])) == NULL) { printf ("Unknown command '%s' - try 'help'\n", argv[0]); diff --git a/common/usb.c b/common/usb.c index d9515e6..01b22ea 100644 --- a/common/usb.c +++ b/common/usb.c @@ -44,16 +44,18 @@ * * For each transfer (except "Interrupt") we wait for completion. */ + #include #include #include #include +#include -#if (CONFIG_COMMANDS & CFG_CMD_USB) +#if defined(CONFIG_CMD_USB) #include #ifdef CONFIG_4xx -#include <405gp_pci.h> +#include #endif #undef USB_DEBUG @@ -66,12 +68,19 @@ #define USB_BUFSIZ 512 +extern void mvUsbSwapWindows(); static struct usb_device usb_dev[USB_MAX_DEVICE]; static int dev_index; static int running; static int asynch_allowed; +static int hubIndex=0; static struct devrequest setup_packet; +static int hub_port_reset(struct usb_device *dev, int port, + unsigned short *portstat); + +char usb_started; /* flag for the started/stopped USB status */ + /********************************************************************** * some forward declerations... */ @@ -101,6 +110,22 @@ int usb_init(void) running=0; dev_index=0; asynch_allowed=1; +#if defined(MV78200) +#if defined(DUAL_OS_78200) || defined(DUAL_OS_SHARED_MEM_78200) + /* Check in dual CPU system which CPU use spi */ + if (!mvSocUnitIsMappedToThisCpu(11)) /* USB0 = 11 */ + { + printf("USB 0 interface not assigned to this CPU !\n"); + return -1; + } +#endif +#if defined(DUAL_OS_78200) + else + { + mvUsbSwapWindows(); + } +#endif +#endif usb_hub_reset(); /* init low_level USB */ printf("USB: "); @@ -110,10 +135,12 @@ int usb_init(void) printf("scanning bus for devices... "); running=1; usb_scan_devices(); + usb_started = 1; return 0; } else { printf("Error, couldn't init Lowlevel part\n"); + usb_started = 0; return -1; } } @@ -123,7 +150,9 @@ int usb_init(void) */ int usb_stop(void) { + unsigned int i; asynch_allowed=1; + usb_started = 0; usb_hub_reset(); return usb_lowlevel_stop(); } @@ -172,10 +201,10 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, /* set setup command */ setup_packet.requesttype = requesttype; setup_packet.request = request; - setup_packet.value = swap_16(value); - setup_packet.index = swap_16(index); - setup_packet.length = swap_16(size); - USB_PRINTF("usb_control_msg: request: 0x%X, requesttype: 0x%X\nvalue 0x%X index 0x%X length 0x%X\n", + setup_packet.value = cpu_to_le16(value); + setup_packet.index = cpu_to_le16(index); + setup_packet.length = cpu_to_le16(size); + USB_PRINTF("usb_control_msg: request: 0x%X, requesttype: 0x%X, value 0x%X index 0x%X length 0x%X\n", request,requesttype,value,index,size); dev->status=USB_ST_NOT_PROC; /*not yet processed */ @@ -212,6 +241,7 @@ int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, break; wait_ms(1); } + wait_ms(1); *actual_length=dev->act_len; if(dev->status==0) return 0; @@ -246,7 +276,7 @@ int usb_set_maxpacket(struct usb_device *dev) for(i=0; iconfig.bNumInterfaces;i++) { for(ii=0; iiconfig.if_desc[i].bNumEndpoints; ii++) { - ep=&dev->config.if_desc[i].ep_desc[ii]; + ep = &dev->config.if_desc[i].ep_desc[ii]; b=ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; if((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)==USB_ENDPOINT_XFER_CONTROL) { /* Control => bidirectional */ @@ -280,56 +310,67 @@ int usb_set_maxpacket(struct usb_device *dev) int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno) { struct usb_descriptor_header *head; - int index,ifno,epno; - ifno=-1; - epno=-1; + int index, ifno, epno, curr_if_num; + int i; + unsigned char *ch; - dev->configno=cfgno; - head =(struct usb_descriptor_header *)&buffer[0]; - if(head->bDescriptorType!=USB_DT_CONFIG) { - printf(" ERROR: NOT USB_CONFIG_DESC %x\n",head->bDescriptorType); + ifno = -1; + epno = -1; + curr_if_num = -1; + + dev->configno = cfgno; + head = (struct usb_descriptor_header *) &buffer[0]; + if(head->bDescriptorType != USB_DT_CONFIG) { + printf(" ERROR: NOT USB_CONFIG_DESC %x\n", head->bDescriptorType); return -1; } - memcpy(&dev->config,buffer,buffer[0]); - dev->config.wTotalLength=swap_16(dev->config.wTotalLength); - dev->config.no_of_if=0; + memcpy(&dev->config, buffer, buffer[0]); + le16_to_cpus(&(dev->config.wTotalLength)); + dev->config.no_of_if = 0; - index=dev->config.bLength; + index = dev->config.bLength; /* Ok the first entry must be a configuration entry, now process the others */ - head=(struct usb_descriptor_header *)&buffer[index]; - while(index+1 < dev->config.wTotalLength) { + head = (struct usb_descriptor_header *) &buffer[index]; + while(index + 1 < dev->config.wTotalLength) { switch(head->bDescriptorType) { case USB_DT_INTERFACE: - ifno=dev->config.no_of_if; - dev->config.no_of_if++; /* found an interface desc, increase numbers */ - memcpy(&dev->config.if_desc[ifno],&buffer[index],buffer[index]); /* copy new desc */ - dev->config.if_desc[ifno].no_of_ep=0; - + if(((struct usb_interface_descriptor *) &buffer[index])-> + bInterfaceNumber != curr_if_num) { + /* this is a new interface, copy new desc */ + ifno = dev->config.no_of_if; + dev->config.no_of_if++; + memcpy(&dev->config.if_desc[ifno], + &buffer[index], buffer[index]); + dev->config.if_desc[ifno].no_of_ep = 0; + dev->config.if_desc[ifno].num_altsetting = 1; + curr_if_num = dev->config.if_desc[ifno].bInterfaceNumber; + } else { + /* found alternate setting for the interface */ + dev->config.if_desc[ifno].num_altsetting++; + } break; case USB_DT_ENDPOINT: - epno=dev->config.if_desc[ifno].no_of_ep; + epno = dev->config.if_desc[ifno].no_of_ep; dev->config.if_desc[ifno].no_of_ep++; /* found an endpoint */ - memcpy(&dev->config.if_desc[ifno].ep_desc[epno],&buffer[index],buffer[index]); - dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize - =swap_16(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize); - USB_PRINTF("if %d, ep %d\n",ifno,epno); + memcpy(&dev->config.if_desc[ifno].ep_desc[epno], + &buffer[index], buffer[index]); + le16_to_cpus(&(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize)); + USB_PRINTF("if %d, ep %d\n", ifno, epno); break; default: - if(head->bLength==0) + if(head->bLength == 0) return 1; - USB_PRINTF("unknown Description Type : %x\n",head->bDescriptorType); + USB_PRINTF("unknown Description Type : %x\n", head->bDescriptorType); { - int i; - unsigned char *ch; - ch=(unsigned char *)head; - for(i=0;ibLength; i++) - USB_PRINTF("%02X ",*ch++); + ch = (unsigned char *)head; + for(i = 0; i < head->bLength; i++) + USB_PRINTF("%02X ", *ch++); USB_PRINTF("\n\n\n"); } break; } - index+=head->bLength; - head=(struct usb_descriptor_header *)&buffer[index]; + index += head->bLength; + head = (struct usb_descriptor_header *)&buffer[index]; } return 1; } @@ -370,11 +411,11 @@ int usb_clear_halt(struct usb_device *dev, int pipe) int usb_get_descriptor(struct usb_device *dev, unsigned char type, unsigned char index, void *buf, int size) { int res; - res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, (type << 8) + index, 0, buf, size, USB_CNTL_TIMEOUT); - return res; + return res; } /********************************************************************** @@ -382,11 +423,10 @@ int usb_get_descriptor(struct usb_device *dev, unsigned char type, unsigned char */ int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cfgno) { - int result; + int result; unsigned int tmp; struct usb_config_descriptor *config; - config=(struct usb_config_descriptor *)&buffer[0]; result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, 8); if (result < 8) { @@ -396,7 +436,7 @@ int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cf printf("config descriptor too short (expected %i, got %i)\n",8,result); return -1; } - tmp=swap_16(config->wTotalLength); + tmp = le16_to_cpu(config->wTotalLength); if (tmp > USB_BUFSIZ) { USB_PRINTF("usb_get_configuration_no: failed to get descriptor - too long: %d\n", @@ -443,6 +483,14 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate) printf("selecting invalid interface %d", interface); return -1; } + /* + * We should return now for devices with only one alternate setting. + * According to 9.4.10 of the Universal Serial Bus Specification Revision 2.0 + * such devices can return with a STALL. This results in some USB sticks + * timeouting during initialization and then being unusable in U-Boot. + */ + if (if_face->num_altsetting == 1) + return 0; if ((ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), USB_REQ_SET_INTERFACE, USB_RECIP_INTERFACE, alternate, @@ -602,7 +650,7 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size) if (size <= 0 || !buf || !index) return -1; buf[0] = 0; - tbuf=&mybuf[0]; + tbuf = &mybuf[0]; /* get langid for strings if it's not yet known */ if (!dev->have_langid) { @@ -670,7 +718,7 @@ struct usb_device * usb_alloc_new_device(void) printf("ERROR, too many USB Devices, max=%d\n",USB_MAX_DEVICE); return NULL; } - usb_dev[dev_index].devnum=dev_index+1; /* default Address is 0, real addresses start with 1 */ + usb_dev[dev_index].devnum=dev_index + 1; /* default Address is 0, real addresses start with 1 */ usb_dev[dev_index].maxchild=0; for(i=0;iepmaxpacketin [0] = 8; dev->epmaxpacketout[0] = 8; + dev->speed = (0x0c000000 & (*(volatile unsigned int *)(0xf1050184))) >> 26; /* We still haven't set the Address yet */ addr = dev->devnum; dev->devnum = 0; @@ -730,7 +779,6 @@ int usb_new_device(struct usb_device *dev) } } dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0; - /* find the port number we're at */ if (parent) { @@ -744,7 +792,6 @@ int usb_new_device(struct usb_device *dev) printf("usb_new_device: cannot locate device's port..\n"); return 1; } - /* reset the port for the second time */ err = hub_port_reset(dev->parent, port, &portstatus); if (err < 0) { @@ -753,24 +800,53 @@ int usb_new_device(struct usb_device *dev) } } #else + struct usb_device *parent = dev->parent; + unsigned short portstatus; + + /* reset the port for the first time */ + if(parent) + { + err = hub_port_reset(dev->parent, dev->portnr - 1, &portstatus); + if (err < 0) { + printf("\n Couldn't reset port %i\n", dev->portnr - 1); + return 1; + } + wait_ms(200); + } /* and this is the old and known way of initializing devices */ err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, 8); if (err < 8) { printf("\n USB device not responding, giving up (status=%lX)\n",dev->status); return 1; } + /* reset the port for the second time */ + if(parent) + { + err = hub_port_reset(dev->parent, dev->portnr - 1, &portstatus); + if (err < 0) { + printf("\n Couldn't reset port %i\n", dev->portnr - 1); + return 1; + } + wait_ms(200); + } + #endif - dev->epmaxpacketin [0] = dev->descriptor.bMaxPacketSize0; + dev->epmaxpacketin [0] = dev->descriptor.bMaxPacketSize0; dev->epmaxpacketout[0] = dev->descriptor.bMaxPacketSize0; switch (dev->descriptor.bMaxPacketSize0) { case 8: dev->maxpacketsize = 0; break; case 16: dev->maxpacketsize = 1; break; case 32: dev->maxpacketsize = 2; break; case 64: dev->maxpacketsize = 3; break; + case 512: dev->maxpacketsize = 6; break; + default: + printf("XXX bMaxPacketSize0 unsupported (%u)\n", + dev->descriptor.bMaxPacketSize0); + break; } - dev->devnum = addr; + dev->devnum = addr; err = usb_set_address(dev); /* set address */ if (err < 0) { @@ -781,7 +857,6 @@ int usb_new_device(struct usb_device *dev) wait_ms(10); /* Let the SET_ADDRESS settle */ tmp = sizeof(dev->descriptor); - err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, sizeof(dev->descriptor)); if (err < tmp) { if (err < 0) @@ -791,24 +866,21 @@ int usb_new_device(struct usb_device *dev) return 1; } /* correct le values */ - dev->descriptor.bcdUSB=swap_16(dev->descriptor.bcdUSB); - dev->descriptor.idVendor=swap_16(dev->descriptor.idVendor); - dev->descriptor.idProduct=swap_16(dev->descriptor.idProduct); - dev->descriptor.bcdDevice=swap_16(dev->descriptor.bcdDevice); + le16_to_cpus(&dev->descriptor.bcdUSB); + le16_to_cpus(&dev->descriptor.idVendor); + le16_to_cpus(&dev->descriptor.idProduct); + le16_to_cpus(&dev->descriptor.bcdDevice); /* only support for one config for now */ usb_get_configuration_no(dev,&tmpbuf[0],0); usb_parse_config(dev,&tmpbuf[0],0); usb_set_maxpacket(dev); - /* we set the default configuration here */ - if (usb_set_configuration(dev, dev->config.bConfigurationValue)) { - printf("failed to set default configuration len %d, status %lX\n",dev->act_len,dev->status); - return -1; - } + USB_PRINTF("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n", dev->descriptor.iManufacturer, dev->descriptor.iProduct, dev->descriptor.iSerialNumber); memset(dev->mf, 0, sizeof(dev->mf)); memset(dev->prod, 0, sizeof(dev->prod)); memset(dev->serial, 0, sizeof(dev->serial)); + if (dev->descriptor.iManufacturer) usb_string(dev, dev->descriptor.iManufacturer, dev->mf, sizeof(dev->mf)); if (dev->descriptor.iProduct) @@ -818,6 +890,13 @@ int usb_new_device(struct usb_device *dev) USB_PRINTF("Manufacturer %s\n", dev->mf); USB_PRINTF("Product %s\n", dev->prod); USB_PRINTF("SerialNumber %s\n", dev->serial); + + /* we set the default configuration here */ + if (usb_set_configuration(dev, dev->config.bConfigurationValue)) { + printf("failed to set default configuration len %d, status %lX\n",dev->act_len,dev->status); + return -1; + } + /* now prode if the device is a hub */ usb_hub_probe(dev,0); return 0; @@ -832,7 +911,7 @@ void usb_scan_devices(void) /* first make all devices unknown */ for(i=0;istatus); return -1; } - portstatus = swap_16(portsts.wPortStatus); - portchange = swap_16(portsts.wPortChange); - USB_HUB_PRINTF("portstatus %x, change %x, %s\n", portstatus ,portchange, - portstatus&(1<slow = (portstatus & USB_PORT_STAT_LOW_SPEED) ? 1 : 0; - + switch (portstatus & USB_PORT_STAT_SPEED) { + case 0: + usb->speed = USB_SPEED_FULL; + // HP hub don't support FULL speed, skipping... + if (hubIndex > 1) + { + USB_HUB_PRINTF("device FULL speed skipped\n"); + return; + } + break; + case USB_PORT_STAT_LOW_SPEED: + usb->speed = USB_SPEED_LOW; + // HP hub don't support LOW speed, skipping... + if (hubIndex > 1) + { + USB_HUB_PRINTF("device LOW speed skipped\n"); + return; + } + break; + case USB_PORT_STAT_HIGH_SPEED: + usb->speed = USB_SPEED_HIGH; + break; + } dev->children[port] = usb; usb->parent=dev; + usb->portnr = port + 1; /* Run it through the hoops (find a driver, etc) */ if (usb_new_device(usb)) { /* Woops, disable the port */ @@ -1063,7 +1166,7 @@ int usb_hub_configure(struct usb_device *dev) /* silence compiler warning if USB_BUFSIZ is > 256 [= sizeof(char)] */ i = descriptor->bLength; if (i > USB_BUFSIZ) { - USB_HUB_PRINTF("usb_hub_configure: failed to get hub descriptor - too long: %d\N", + USB_HUB_PRINTF("usb_hub_configure: failed to get hub descriptor - too long: %d\n", descriptor->bLength); return -1; } @@ -1074,7 +1177,7 @@ int usb_hub_configure(struct usb_device *dev) } memcpy((unsigned char *)&hub->desc,buffer,descriptor->bLength); /* adjust 16bit values */ - hub->desc.wHubCharacteristics=swap_16(descriptor->wHubCharacteristics); + hub->desc.wHubCharacteristics = le16_to_cpu(descriptor->wHubCharacteristics); /* set the bitmap */ bitmap=(unsigned char *)&hub->desc.DeviceRemovable[0]; memset(bitmap,0xff,(USB_MAXCHILDREN+1+7)/8); /* devices not removable by default */ @@ -1136,12 +1239,13 @@ int usb_hub_configure(struct usb_device *dev) } hubsts = (struct usb_hub_status *)buffer; USB_HUB_PRINTF("get_hub_status returned status %X, change %X\n", - swap_16(hubsts->wHubStatus),swap_16(hubsts->wHubChange)); + le16_to_cpu(hubsts->wHubStatus),le16_to_cpu(hubsts->wHubChange)); USB_HUB_PRINTF("local power source is %s\n", - (swap_16(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? "lost (inactive)" : "good"); + (le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? "lost (inactive)" : "good"); USB_HUB_PRINTF("%sover-current condition exists\n", - (swap_16(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? "" : "no "); + (le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? "" : "no "); usb_hub_power_on(hub); + for (i = 0; i < dev->maxchild; i++) { struct usb_port_status portsts; unsigned short portstatus, portchange; @@ -1150,8 +1254,8 @@ int usb_hub_configure(struct usb_device *dev) USB_HUB_PRINTF("get_port_status failed\n"); continue; } - portstatus = swap_16(portsts.wPortStatus); - portchange = swap_16(portsts.wPortChange); + portstatus = le16_to_cpu(portsts.wPortStatus); + portchange = le16_to_cpu(portsts.wPortChange); USB_HUB_PRINTF("Port %d Status %X Change %X\n",i+1,portstatus,portchange); if (portchange & USB_PORT_STAT_C_CONNECTION) { USB_HUB_PRINTF("port %d connection change\n", i + 1); @@ -1218,10 +1322,11 @@ int usb_hub_probe(struct usb_device *dev, int ifnum) return 0; /* We found a hub */ USB_HUB_PRINTF("USB hub found\n"); + hubIndex++; ret=usb_hub_configure(dev); return ret; } -#endif /* (CONFIG_COMMANDS & CFG_CMD_USB) */ +#endif /* EOF */ diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 56c2166..c876495 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -26,6 +26,7 @@ */ #include #include +#include #ifdef CONFIG_USB_KEYBOARD @@ -84,6 +85,7 @@ int repeat_delay; static unsigned char num_lock = 0; static unsigned char caps_lock = 0; static unsigned char scroll_lock = 0; +static unsigned char ctrl = 0; static unsigned char leds __attribute__ ((aligned (0x4))); @@ -120,6 +122,9 @@ static void usb_kbd_put_queue(char data) /* test if a character is in the queue */ static int usb_kbd_testc(void) { +#ifdef CFG_USB_EVENT_POLL + usb_event_poll(); +#endif if(usb_in_pointer==usb_out_pointer) return(0); /* no data */ else @@ -129,7 +134,11 @@ static int usb_kbd_testc(void) static int usb_kbd_getc(void) { char c; - while(usb_in_pointer==usb_out_pointer); + while(usb_in_pointer==usb_out_pointer) { +#ifdef CFG_USB_EVENT_POLL + usb_event_poll(); +#endif + } if((usb_out_pointer+1)==USB_KBD_BUFFER_LEN) usb_out_pointer=0; else @@ -230,7 +239,7 @@ static void usb_kbd_setled(struct usb_device *dev) leds|=1; usb_control_msg(dev, usb_sndctrlpipe(dev, 0), USB_REQ_SET_REPORT, USB_TYPE_CLASS | USB_RECIP_INTERFACE, - 0x200, iface->bInterfaceNumber,(void *)&leds, 1, 0); + 0x200, iface->bInterfaceNumber,(void *)&leds, 1, 0); } @@ -243,7 +252,7 @@ static int usb_kbd_translate(unsigned char scancode,unsigned char modifier,int p if(pressed==0) { /* key released */ - repeat_delay=0; + repeat_delay=0; return 0; } if(pressed==2) { @@ -253,7 +262,7 @@ static int usb_kbd_translate(unsigned char scancode,unsigned char modifier,int p repeat_delay=REPEAT_DELAY; } keycode=0; - if((scancode>3) && (scancode<0x1d)) { /* alpha numeric values */ + if((scancode>3) && (scancode<=0x1d)) { /* alpha numeric values */ keycode=scancode-4 + 0x61; if(caps_lock) keycode&=~CAPITAL_MASK; /* switch to capital Letters */ @@ -270,6 +279,10 @@ static int usb_kbd_translate(unsigned char scancode,unsigned char modifier,int p else /* non shifted */ keycode=usb_kbd_numkey[scancode-0x1e]; } + + if (ctrl) + keycode = scancode - 0x3; + if(pressed==1) { if(scancode==NUM_LOCK) { num_lock=~num_lock; @@ -302,6 +315,17 @@ static int usb_kbd_irq(struct usb_device *dev) return 1; } res=0; + + switch (new[0]) { + case 0x0: /* No combo key pressed */ + ctrl = 0; + break; + case 0x01: /* Left Ctrl pressed */ + case 0x10: /* Right Ctrl pressed */ + ctrl = 1; + break; + } + for (i = 2; i < 8; i++) { if (old[i] > 3 && memscan(&new[2], old[i], 6) == &new[8]) { res|=usb_kbd_translate(old[i],new[0],0); @@ -452,14 +476,14 @@ static int fetch_item(unsigned char *start,unsigned char *end, struct hid_item * break; case 2: if ((end - start) >= 2) { - item->data.u16 = swap_16((unsigned short *)start); + item->data.u16 = le16_to_cpu((unsigned short *)start); start+=2; return item->size; } case 3: item->size++; if ((end - start) >= 4) { - item->data.u32 = swap_32((unsigned long *)start); + item->data.u32 = le32_to_cpu((unsigned long *)start); start+=4; return item->size; } @@ -682,15 +706,15 @@ static int usb_kbd_get_hid_desc(struct usb_device *dev) } index=head->bLength; config=(struct usb_config_descriptor *)&buffer[0]; - len=swap_16(config->wTotalLength); + len=le16_to_cpu(config->wTotalLength); /* Ok the first entry must be a configuration entry, now process the others */ head=(struct usb_descriptor_header *)&buffer[index]; while(index+1 < len) { if(head->bDescriptorType==USB_DT_HID) { printf("HID desc found\n"); memcpy(&usb_kbd_hid_desc,&buffer[index],buffer[index]); - usb_kbd_hid_desc.bcdHID=swap_16(usb_kbd_hid_desc.bcdHID); - usb_kbd_hid_desc.wDescriptorLength=swap_16(usb_kbd_hid_desc.wDescriptorLength); + le16_to_cpus(&usb_kbd_hid_desc.bcdHID); + le16_to_cpus(&usb_kbd_hid_desc.wDescriptorLength); usb_kbd_display_hid(&usb_kbd_hid_desc); len=0; break; @@ -706,8 +730,8 @@ static int usb_kbd_get_hid_desc(struct usb_device *dev) return -1; } printf(" report descriptor (size %u, read %d)\n", len, index); - start=&buffer[0]; - end=&buffer[len]; + start = &buffer[0]; + end = &buffer[len]; i=0; do { index=fetch_item(start,end,&item); diff --git a/common/usb_storage.c b/common/usb_storage.c index 99e4ab0..436803a 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -52,10 +52,12 @@ #include #include +#include #include -#if (CONFIG_COMMANDS & CFG_CMD_USB) +#if defined(CONFIG_CMD_USB) +#include #include #ifdef CONFIG_USB_STORAGE @@ -112,7 +114,7 @@ typedef struct { __u8 CBWCDB[CBWCDBLENGTH]; } umass_bbb_cbw_t; #define UMASS_BBB_CBW_SIZE 31 -static __u32 CBWTag = 0; +static __u32 CBWTag = 1; /* Command Status Wrapper */ typedef struct { @@ -168,13 +170,13 @@ static struct us_data usb_stor[USB_MAX_STOR_DEV]; int usb_stor_get_info(struct usb_device *dev, struct us_data *us, block_dev_desc_t *dev_desc); int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data *ss); -unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, unsigned long *buffer); +unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer); struct usb_device * usb_get_dev_index(int index); void uhci_show_temp_int_td(void); block_dev_desc_t *usb_stor_get_dev(int index) { - return &usb_dev_desc[index]; + return (index < USB_MAX_STOR_DEV) ? &usb_dev_desc[index] : NULL; } @@ -187,25 +189,27 @@ void usb_show_progress(void) * show info on storage devices; 'usb start/init' must be invoked earlier * as we only retrieve structures populated during devices initialization */ -void usb_stor_info(void) +int usb_stor_info(void) { int i; - if (usb_max_devs > 0) + if (usb_max_devs > 0) { for (i = 0; i < usb_max_devs; i++) { printf (" Device %d: ", i); dev_print(&usb_dev_desc[i]); } - else - printf("No storage devices, perhaps not 'usb start'ed..?\n"); + return 0; + } + + printf("No storage devices, perhaps not 'usb start'ed..?\n"); + return 1; } /********************************************************************************* * scan the usb and reports device info - * to the user if mode = 1 * returns current device or -1 if no */ -int usb_stor_scan(int mode) +int usb_stor_scan(void) { unsigned char i; struct usb_device *dev; @@ -213,9 +217,6 @@ int usb_stor_scan(int mode) /* GJ */ memset(usb_stor_buf, 0, sizeof(usb_stor_buf)); - if(mode==1) { - printf(" scanning bus for storage devices... "); - } usb_disable_asynch(1); /* asynch transfer not allowed */ for(i=0;ipusb_dev, pipe, buf, - this_xfer, &partial, USB_CNTL_TIMEOUT*5); + this_xfer, &partial, USB_BULK_TIMEOUT*5); USB_STOR_PRINTF("bulk_msg returned %d xferred %d/%d\n", result, partial, this_xfer); if(us->pusb_dev->status!=0) { @@ -451,6 +452,8 @@ int usb_stor_BBB_comdat(ccb *srb, struct us_data *us) unsigned int pipe; umass_bbb_cbw_t cbw; + memset(&cbw, 0, sizeof(cbw)); + dir_in = US_DIRECTION(srb->cmd[0]); #ifdef BBB_COMDAT_TRACE @@ -470,16 +473,16 @@ int usb_stor_BBB_comdat(ccb *srb, struct us_data *us) /* always OUT to the ep */ pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); - cbw.dCBWSignature = swap_32(CBWSIGNATURE); - cbw.dCBWTag = swap_32(CBWTag++); - cbw.dCBWDataTransferLength = swap_32(srb->datalen); + cbw.dCBWSignature = cpu_to_le32(CBWSIGNATURE); + cbw.dCBWTag = cpu_to_le32(CBWTag++); + cbw.dCBWDataTransferLength = cpu_to_le32(srb->datalen); cbw.bCBWFlags = (dir_in? CBWFLAGS_IN : CBWFLAGS_OUT); cbw.bCBWLUN = srb->lun; cbw.bCDBLength = srb->cmdlen; /* copy the command data into the CBW command data buffer */ /* DST SRC LEN!!! */ memcpy(cbw.CBWCDB, srb->cmd, srb->cmdlen); - result = usb_bulk_msg(us->pusb_dev, pipe, &cbw, UMASS_BBB_CBW_SIZE, &actlen, USB_CNTL_TIMEOUT*5); + result = usb_bulk_msg(us->pusb_dev, pipe, &cbw, UMASS_BBB_CBW_SIZE, &actlen, USB_BULK_TIMEOUT*5); if (result < 0) USB_STOR_PRINTF("usb_stor_BBB_comdat:usb_bulk_msg error\n"); return result; @@ -624,7 +627,7 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us) usb_stor_BBB_reset(us); return USB_STOR_TRANSPORT_FAILED; } - wait_ms(5); + /*wait_ms(5); */ pipein = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); pipeout = usb_sndbulkpipe(us->pusb_dev, us->ep_out); /* DATA phase + error handling */ @@ -637,7 +640,7 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us) pipe = pipein; else pipe = pipeout; - result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, &data_actlen, USB_CNTL_TIMEOUT*5); + result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, &data_actlen, USB_BULK_TIMEOUT*5); /* special handling of STALL in DATA phase */ if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) { USB_STOR_PRINTF("DATA:stall\n"); @@ -664,7 +667,7 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us) again: USB_STOR_PRINTF("STATUS phase\n"); result = usb_bulk_msg(us->pusb_dev, pipein, &csw, UMASS_BBB_CSW_SIZE, - &actlen, USB_CNTL_TIMEOUT*5); + &actlen, USB_BULK_TIMEOUT*5); /* special handling of STALL in STATUS phase */ if((result < 0) && (retry < 1) && (us->pusb_dev->status & USB_ST_STALLED)) { @@ -688,14 +691,14 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us) printf("\n"); #endif /* misuse pipe to get the residue */ - pipe = swap_32(csw.dCSWDataResidue); + pipe = le32_to_cpu(csw.dCSWDataResidue); if (pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0) pipe = srb->datalen - data_actlen; - if (CSWSIGNATURE != swap_32(csw.dCSWSignature)) { + if (CSWSIGNATURE != le32_to_cpu(csw.dCSWSignature)) { USB_STOR_PRINTF("!CSWSIGNATURE\n"); usb_stor_BBB_reset(us); return USB_STOR_TRANSPORT_FAILED; - } else if ((CBWTag - 1) != swap_32(csw.dCSWTag)) { + } else if ((CBWTag - 1) != le32_to_cpu(csw.dCSWTag)) { USB_STOR_PRINTF("!Tag\n"); usb_stor_BBB_reset(us); return USB_STOR_TRANSPORT_FAILED; @@ -726,7 +729,7 @@ int usb_stor_CB_transport(ccb *srb, struct us_data *us) ccb reqsrb; int retry,notready; - psrb=&reqsrb; + psrb = &reqsrb; status=USB_STOR_TRANSPORT_GOOD; retry=0; notready=0; @@ -771,8 +774,8 @@ do_retry: psrb->cmd[1]=srb->lun<<5; psrb->cmd[4]=18; psrb->datalen=18; - psrb->pdata=&srb->sense_buf[0]; - psrb->cmdlen=12; + psrb->pdata = &srb->sense_buf[0]; + psrb->cmdlen=6; /*12*/ /* issue the command */ result=usb_stor_CB_comdat(psrb,us); USB_STOR_PRINTF("auto request returned %d\n",result); @@ -829,7 +832,7 @@ static int usb_inquiry(ccb *srb,struct us_data *ss) srb->cmd[1]=srb->lun<<5; srb->cmd[4]=36; srb->datalen=36; - srb->cmdlen=12; + srb->cmdlen=6; /*12*/ i=ss->transport(srb,ss); USB_STOR_PRINTF("inquiry returns %d\n",i); if(i==0) @@ -853,8 +856,8 @@ static int usb_request_sense(ccb *srb,struct us_data *ss) srb->cmd[1]=srb->lun<<5; srb->cmd[4]=18; srb->datalen=18; - srb->pdata=&srb->sense_buf[0]; - srb->cmdlen=12; + srb->pdata = &srb->sense_buf[0]; + srb->cmdlen=6; /*12*/ ss->transport(srb,ss); USB_STOR_PRINTF("Request Sense returned %02X %02X %02X\n",srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); srb->pdata=(uchar *)ptr; @@ -870,12 +873,12 @@ static int usb_test_unit_ready(ccb *srb,struct us_data *ss) srb->cmd[0]=SCSI_TST_U_RDY; srb->cmd[1]=srb->lun<<5; srb->datalen=0; - srb->cmdlen=12; + srb->cmdlen=6; /*12*/ if(ss->transport(srb,ss)==USB_STOR_TRANSPORT_GOOD) { return 0; } usb_request_sense (srb, ss); - wait_ms (100); + wait_ms (1000); } while(retries--); return -1; @@ -890,7 +893,7 @@ static int usb_read_capacity(ccb *srb,struct us_data *ss) srb->cmd[0]=SCSI_RD_CAPAC; srb->cmd[1]=srb->lun<<5; srb->datalen=8; - srb->cmdlen=12; + srb->cmdlen=10; /*12*/ if(ss->transport(srb,ss)==USB_STOR_TRANSPORT_GOOD) { return 0; } @@ -901,7 +904,7 @@ static int usb_read_capacity(ccb *srb,struct us_data *ss) static int usb_read_10(ccb *srb,struct us_data *ss, unsigned long start, unsigned short blocks) { - memset(&srb->cmd[0],0,12); + memset(&srb->cmd[0],0,16); srb->cmd[0]=SCSI_READ10; srb->cmd[1]=srb->lun<<5; srb->cmd[2]=((unsigned char) (start>>24))&0xff; @@ -910,15 +913,37 @@ static int usb_read_10(ccb *srb,struct us_data *ss, unsigned long start, unsigne srb->cmd[5]=((unsigned char) (start))&0xff; srb->cmd[7]=((unsigned char) (blocks>>8))&0xff; srb->cmd[8]=(unsigned char) blocks & 0xff; - srb->cmdlen=12; + srb->cmdlen=10; /*12 */ USB_STOR_PRINTF("read10: start %lx blocks %x\n",start,blocks); return ss->transport(srb,ss); } -#define USB_MAX_READ_BLK 20 +#ifdef CONFIG_USB_BIN_FIXUP +/* + * Some USB storage devices queried for SCSI identification data respond with + * binary strings, which if output to the console freeze the terminal. The + * workaround is to modify the vendor and product strings read from such + * device with proper values (as reported by 'usb info'). + * + * Vendor and product length limits are taken from the definition of + * block_dev_desc_t in include/part.h. + */ +static void usb_bin_fixup(struct usb_device_descriptor descriptor, + unsigned char vendor[], + unsigned char product[]) { + const unsigned char max_vendor_len = 40; + const unsigned char max_product_len = 20; + if (descriptor.idVendor == 0x0424 && descriptor.idProduct == 0x223a) { + strncpy ((char *)vendor, "SMSC", max_vendor_len); + strncpy ((char *)product, "Flash Media Cntrller", max_product_len); + } +} +#endif /* CONFIG_USB_BIN_FIXUP */ -unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, unsigned long *buffer) +#define USB_MAX_READ_BLK 20 /*20*/ + +unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer) { unsigned long start,blks, buf_addr; unsigned short smallblks; @@ -1000,16 +1025,17 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data /* let's examine the device now */ iface = &dev->config.if_desc[ifnum]; + USB_STOR_PRINTF("iVendor %X iProduct %X\n",dev->descriptor.idVendor,dev->descriptor.idProduct); #if 0 /* this is the place to patch some storage devices */ - USB_STOR_PRINTF("iVendor %X iProduct %X\n",dev->descriptor.idVendor,dev->descriptor.idProduct); if ((dev->descriptor.idVendor) == 0x066b && (dev->descriptor.idProduct) == 0x0103) { USB_STOR_PRINTF("patched for E-USB\n"); protocol = US_PR_CB; subclass = US_SC_UFI; /* an assumption */ } #endif - + USB_STOR_PRINTF("devClass=%x IFClass=%x IFSubClass=%x \n",dev->descriptor.bDeviceClass, iface->bInterfaceClass, + iface->bInterfaceSubClass); if (dev->descriptor.bDeviceClass != 0 || iface->bInterfaceClass != USB_CLASS_MASS_STORAGE || iface->bInterfaceSubClass < US_SC_MIN || @@ -1129,6 +1155,7 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t unsigned long *capacity,*blksz; ccb *pccb = &usb_ccb; +#if 0 /* for some reasons a couple of devices would not survive this reset */ if ( /* Sony USM256E */ @@ -1139,10 +1166,15 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t /* USB007 Mini-USB2 Flash Drive */ (dev->descriptor.idVendor == 0x066f && dev->descriptor.idProduct == 0x2010) + || + /* SanDisk Corporation Cruzer Micro 20044318410546613953 */ + (dev->descriptor.idVendor == 0x0781 && + dev->descriptor.idProduct == 0x5151) ) USB_STOR_PRINTF("usb_stor_get_info: skipping RESET..\n"); else ss->transport_reset(ss); +#endif pccb->pdata = usb_stor_buf; @@ -1153,7 +1185,7 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t if(usb_inquiry(pccb,ss)) return -1; - perq = usb_stor_buf[0]; + perq = usb_stor_buf[0]; modi = usb_stor_buf[1]; if((perq & 0x1f) == 0x1f) { return 0; /* skip unknown devices */ @@ -1167,6 +1199,9 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t dev_desc->vendor[8] = 0; dev_desc->product[16] = 0; dev_desc->revision[4] = 0; +#ifdef CONFIG_USB_BIN_FIXUP + usb_bin_fixup(dev->descriptor, (uchar *)dev_desc->vendor, (uchar *)dev_desc->product); +#endif /* CONFIG_USB_BIN_FIXUP */ USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n",usb_stor_buf[2],usb_stor_buf[3]); if(usb_test_unit_ready(pccb,ss)) { printf("Device NOT ready\n Request Sense returned %02X %02X %02X\n",pccb->sense_buf[2],pccb->sense_buf[12],pccb->sense_buf[13]); @@ -1189,18 +1224,8 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t if(cap[0]>(0x200000 * 10)) /* greater than 10 GByte */ cap[0]>>=16; #endif -#ifdef LITTLEENDIAN - cap[0] = ((unsigned long)( - (((unsigned long)(cap[0]) & (unsigned long)0x000000ffUL) << 24) | - (((unsigned long)(cap[0]) & (unsigned long)0x0000ff00UL) << 8) | - (((unsigned long)(cap[0]) & (unsigned long)0x00ff0000UL) >> 8) | - (((unsigned long)(cap[0]) & (unsigned long)0xff000000UL) >> 24) )); - cap[1] = ((unsigned long)( - (((unsigned long)(cap[1]) & (unsigned long)0x000000ffUL) << 24) | - (((unsigned long)(cap[1]) & (unsigned long)0x0000ff00UL) << 8) | - (((unsigned long)(cap[1]) & (unsigned long)0x00ff0000UL) >> 8) | - (((unsigned long)(cap[1]) & (unsigned long)0xff000000UL) >> 24) )); -#endif + cap[0] = cpu_to_be32(cap[0]); + cap[1] = cpu_to_be32(cap[1]); /* this assumes bigendian! */ cap[0] += 1; capacity = &cap[0]; @@ -1219,4 +1244,4 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t } #endif /* CONFIG_USB_STORAGE */ -#endif /* CFG_CMD_USB */ +#endif diff --git a/config.mk b/config.mk index d85ac36..5437b0a 100644 --- a/config.mk +++ b/config.mk @@ -24,7 +24,8 @@ ######################################################################### # clean the slate ... -PLATFORM_RELFLAGS = +# support 3TB HDD +PLATFORM_RELFLAGS = -DCFG_64BIT_LBA PLATFORM_CPPFLAGS = PLATFORM_LDFLAGS = @@ -118,7 +119,7 @@ OBJCFLAGS += --gap-fill=0xff gccincdir := $(shell $(CC) -print-file-name=include) -CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ +CPPFLAGS += $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \ -I$(TOPDIR)/include \ -fno-builtin -ffreestanding -nostdinc -isystem \ @@ -183,7 +184,7 @@ export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS %.s: %.S $(CPP) $(AFLAGS) -o $@ $(CURDIR)/$< %.o: %.S - $(CC) $(AFLAGS) -c -o $@ $(CURDIR)/$< + $(CC) $(AFLAGS) -c -o $@ $< %.o: %.c $(CC) $(CFLAGS) -c -o $@ $< diff --git a/cpu/74xx_7xx/Makefile b/cpu/74xx_7xx/Makefile deleted file mode 100644 index 0e10d3a..0000000 --- a/cpu/74xx_7xx/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -ASOBJS = cache.o kgdb.o io.o -OBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o - -all: .depend $(START) $(ASOBJS) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(ASOBJS) $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S deleted file mode 100644 index a793d79..0000000 --- a/cpu/74xx_7xx/cache.S +++ /dev/null @@ -1,381 +0,0 @@ -#include -#include <74xx_7xx.h> -#include - -#include -#include - -#include -#include - -#ifndef CACHE_LINE_SIZE -# define CACHE_LINE_SIZE L1_CACHE_BYTES -#endif - -#if CACHE_LINE_SIZE == 128 -#define LG_CACHE_LINE_SIZE 7 -#elif CACHE_LINE_SIZE == 32 -#define LG_CACHE_LINE_SIZE 5 -#elif CACHE_LINE_SIZE == 16 -#define LG_CACHE_LINE_SIZE 4 -#elif CACHE_LINE_SIZE == 8 -#define LG_CACHE_LINE_SIZE 3 -#else -# error "Invalid cache line size!" -#endif - -/* - * Invalidate L1 instruction cache. - */ -_GLOBAL(invalidate_l1_instruction_cache) - mfspr r3,PVR - rlwinm r3,r3,16,16,31 - cmpi 0,r3,1 - beqlr /* for 601, do nothing */ - /* 603/604 processor - use invalidate-all bit in HID0 */ - mfspr r3,HID0 - ori r3,r3,HID0_ICFI - mtspr HID0,r3 - isync - blr - -/* - * Invalidate L1 data cache. - */ -_GLOBAL(invalidate_l1_data_cache) - mfspr r3,HID0 - ori r3,r3,HID0_DCFI - mtspr HID0,r3 - isync - blr - -/* - * Flush data cache. - */ -_GLOBAL(flush_data_cache) - lis r3,0 - lis r5,CACHE_LINE_SIZE -flush: - cmp 0,1,r3,r5 - bge done - lwz r5,0(r3) - lis r5,CACHE_LINE_SIZE - addi r3,r3,0x4 - b flush -done: - blr -/* - * Write any modified data cache blocks out to memory - * and invalidate the corresponding instruction cache blocks. - * This is a no-op on the 601. - * - * flush_icache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(flush_icache_range) - mfspr r5,PVR - rlwinm r5,r5,16,16,31 - cmpi 0,r5,1 - beqlr /* for 601, do nothing */ - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CACHE_LINE_SIZE - bdnz 2b - sync /* additional sync needed on g4 */ - isync - blr -/* - * Write any modified data cache blocks out to memory. - * Does not invalidate the corresponding cache lines (especially for - * any corresponding instruction cache). - * - * clean_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(clean_dcache_range) - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 /* align r3 down to cache line */ - subf r4,r3,r4 /* r4 = offset of stop from start of cache line */ - add r4,r4,r5 /* r4 += cache_line_size-1 */ - srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */ - beqlr /* if r4 == 0 return */ - mtctr r4 /* ctr = r4 */ - - sync -1: dcbst 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - blr - -/* - * Write any modified data cache blocks out to memory - * and invalidate the corresponding instruction cache blocks. - * - * flush_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(flush_dcache_range) - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE - beqlr - mtctr r4 - - sync -1: dcbf 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbf's to get to ram */ - blr - -/* - * Like above, but invalidate the D-cache. This is used by the 8xx - * to invalidate the cache so the PPC core doesn't get stale data - * from the CPM (no cache snooping here :-). - * - * invalidate_dcache_range(unsigned long start, unsigned long stop) - */ -_GLOBAL(invalidate_dcache_range) - li r5,CACHE_LINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE - beqlr - mtctr r4 - - sync -1: dcbi 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync /* wait for dcbi's to get to ram */ - blr - -/* - * Flush a particular page from the data cache to RAM. - * Note: this is necessary because the instruction cache does *not* - * snoop from the data cache. - * This is a no-op on the 601 which has a unified cache. - * - * void __flush_page_to_ram(void *page) - */ -_GLOBAL(__flush_page_to_ram) - mfspr r5,PVR - rlwinm r5,r5,16,16,31 - cmpi 0,r5,1 - beqlr /* for 601, do nothing */ - rlwinm r3,r3,0,0,19 /* Get page base address */ - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ - mtctr r4 - mr r6,r3 -0: dcbst 0,r3 /* Write line to ram */ - addi r3,r3,CACHE_LINE_SIZE - bdnz 0b - sync - mtctr r4 -1: icbi 0,r6 - addi r6,r6,CACHE_LINE_SIZE - bdnz 1b - sync - isync - blr - -/* - * Flush a particular page from the instruction cache. - * Note: this is necessary because the instruction cache does *not* - * snoop from the data cache. - * This is a no-op on the 601 which has a unified cache. - * - * void __flush_icache_page(void *page) - */ -_GLOBAL(__flush_icache_page) - mfspr r5,PVR - rlwinm r5,r5,16,16,31 - cmpi 0,r5,1 - beqlr /* for 601, do nothing */ - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ - mtctr r4 -1: icbi 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - sync - isync - blr - -/* - * Clear a page using the dcbz instruction, which doesn't cause any - * memory traffic (except to write out any cache lines which get - * displaced). This only works on cacheable memory. - */ -_GLOBAL(clear_page) - li r0,4096/CACHE_LINE_SIZE - mtctr r0 -1: dcbz 0,r3 - addi r3,r3,CACHE_LINE_SIZE - bdnz 1b - blr - -/* - * Enable L1 Instruction cache - */ -_GLOBAL(icache_enable) - mfspr r3, HID0 - li r5, HID0_ICFI|HID0_ILOCK - andc r3, r3, r5 - ori r3, r3, HID0_ICE - ori r5, r3, HID0_ICFI - mtspr HID0, r5 - mtspr HID0, r3 - isync - blr - -/* - * Disable L1 Instruction cache - */ -_GLOBAL(icache_disable) - mfspr r3, HID0 - li r5, 0 - ori r5, r5, HID0_ICE - andc r3, r3, r5 - mtspr HID0, r3 - isync - blr - -/* - * Is instruction cache enabled? - */ -_GLOBAL(icache_status) - mfspr r3, HID0 - andi. r3, r3, HID0_ICE - blr - - -_GLOBAL(l1dcache_enable) - mfspr r3, HID0 - li r5, HID0_DCFI|HID0_DLOCK - andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ - ori r3, r3, HID0_DCE - ori r5, r3, HID0_DCFI - mtspr HID0, r5 /* enable + invalidate */ - mtspr HID0, r3 /* enable */ - sync - blr - -/* - * Enable data cache(s) - L1 and optionally L2 - * Calls l2cache_enable. LR saved in r5 - */ -_GLOBAL(dcache_enable) - mfspr r3, HID0 - li r5, HID0_DCFI|HID0_DLOCK - andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ - ori r3, r3, HID0_DCE - ori r5, r3, HID0_DCFI - mtspr HID0, r5 /* enable + invalidate */ - mtspr HID0, r3 /* enable */ - sync -#ifdef CFG_L2 - mflr r5 - bl l2cache_enable /* uses r3 and r4 */ - sync - mtlr r5 -#endif - blr - - -/* - * Disable data cache(s) - L1 and optionally L2 - * Calls flush_data_cache and l2cache_disable_no_flush. - * LR saved in r4 - */ -_GLOBAL(dcache_disable) - mflr r4 /* save link register */ - bl flush_data_cache /* uses r3 and r5 */ - sync - mfspr r3, HID0 - li r5, HID0_DCFI|HID0_DLOCK - andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ - li r5, HID0_DCE|HID0_DCFI - andc r3, r3, r5 /* no enable, no invalidate */ - mtspr HID0, r3 - sync -#ifdef CFG_L2 - bl l2cache_disable_no_flush /* uses r3 */ -#endif - mtlr r4 /* restore link register */ - blr - -/* - * Is data cache enabled? - */ -_GLOBAL(dcache_status) - mfspr r3, HID0 - andi. r3, r3, HID0_DCE - blr - -/* - * Invalidate L2 cache using L2I and polling L2IP - */ -_GLOBAL(l2cache_invalidate) - sync - oris r3, r3, L2CR_L2I@h - sync - mtspr l2cr, r3 - sync -invl2: - mfspr r3, l2cr - andi. r3, r3, L2CR_L2IP - bne invl2 - /* turn off the global invalidate bit */ - mfspr r3, l2cr - rlwinm r3, r3, 0, 11, 9 - sync - mtspr l2cr, r3 - sync - blr - -/* - * Enable L2 cache - * Calls l2cache_invalidate. LR is saved in r4 - */ -_GLOBAL(l2cache_enable) - mflr r4 /* save link register */ - bl l2cache_invalidate /* uses r3 */ - sync - lis r3, L2_ENABLE@h - ori r3, r3, L2_ENABLE@l - mtspr l2cr, r3 - isync - mtlr r4 /* restore link register */ - blr - -/* - * Disable L2 cache - * Calls flush_data_cache. LR is saved in r4 - */ -_GLOBAL(l2cache_disable) - mflr r4 /* save link register */ - bl flush_data_cache /* uses r3 and r5 */ - sync - mtlr r4 /* restore link register */ -l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ - lis r3, L2_INIT@h - ori r3, r3, L2_INIT@l - mtspr l2cr, r3 - isync - blr diff --git a/cpu/74xx_7xx/config.mk b/cpu/74xx_7xx/config.mk deleted file mode 100644 index 417d99f..0000000 --- a/cpu/74xx_7xx/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2001 -# Josh Huber , Mission Critical Linux, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing - -PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -ffixed-r29 -mstring diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c deleted file mode 100644 index 629ed66..0000000 --- a/cpu/74xx_7xx/cpu.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * cpu.c - * - * CPU specific code - * - * written or collected and sometimes rewritten by - * Magnus Damm - * - * minor modifications by - * Wolfgang Denk - * - * more modifications by - * Josh Huber - * added support for the 74xx series of cpus - * added support for the 7xx series of cpus - * made the code a little less hard-coded, and more auto-detectish - */ - -#include -#include -#include <74xx_7xx.h> -#include - -#ifdef CONFIG_AMIGAONEG3SE -#include "../board/MAI/AmigaOneG3SE/via686.h" -#include "../board/MAI/AmigaOneG3SE/memio.h" -#endif - -cpu_t -get_cpu_type(void) -{ - uint pvr = get_pvr(); - cpu_t type; - - type = CPU_UNKNOWN; - - switch (PVR_VER(pvr)) { - case 0x000c: - type = CPU_7400; - break; - case 0x0008: - type = CPU_750; - - if (((pvr >> 8) & 0xff) == 0x01) { - type = CPU_750CX; /* old CX (80100 and 8010x?)*/ - } else if (((pvr >> 8) & 0xff) == 0x22) { - type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */ - } else if (((pvr >> 8) & 0xff) == 0x33) { - type = CPU_750CX; /* CXe (83311) */ - } else if (((pvr >> 12) & 0xF) == 0x3) { - type = CPU_755; - } - break; - - case 0x7000: - type = CPU_750FX; - break; - - case 0x7002: - type = CPU_750GX; - break; - - case 0x800C: - type = CPU_7410; - break; - - case 0x8000: - type = CPU_7450; - break; - - case 0x8001: - type = CPU_7455; - break; - - case 0x8002: - type = CPU_7457; - break; - - default: - break; - } - - return type; -} - -/* ------------------------------------------------------------------------- */ - -#if !defined(CONFIG_BAB7xx) -int checkcpu (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - uint type = get_cpu_type(); - uint pvr = get_pvr(); - ulong clock = gd->cpu_clk; - char buf[32]; - char *str; - - puts ("CPU: "); - - switch (type) { - case CPU_750CX: - printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"", - (pvr>>8) & 0xf, - pvr & 0xf); - goto PR_CLK; - - case CPU_750: - str = "750"; - break; - - case CPU_750FX: - str = "750FX"; - break; - - case CPU_750GX: - str = "750GX"; - break; - - case CPU_755: - str = "755"; - break; - - case CPU_7400: - str = "MPC7400"; - break; - - case CPU_7410: - str = "MPC7410"; - break; - - case CPU_7450: - str = "MPC7450"; - break; - - case CPU_7455: - str = "MPC7455"; - break; - - case CPU_7457: - str = "MPC7457"; - break; - - default: - printf("Unknown CPU -- PVR: 0x%08x\n", pvr); - return -1; - } - - printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF); -PR_CLK: - printf (" @ %s MHz\n", strmhz(buf, clock)); - - return (0); -} -#endif -/* these two functions are unimplemented currently [josh] */ - -/* -------------------------------------------------------------------- */ -/* L1 i-cache */ - -int -checkicache(void) -{ - return 0; /* XXX */ -} - -/* -------------------------------------------------------------------- */ -/* L1 d-cache */ - -int -checkdcache(void) -{ - return 0; /* XXX */ -} - -/* -------------------------------------------------------------------- */ - -static inline void -soft_restart(unsigned long addr) -{ - /* SRR0 has system reset vector, SRR1 has default MSR value */ - /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ - - __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); - __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); - __asm__ __volatile__ ("mtspr 27, 4"); - __asm__ __volatile__ ("rfi"); - - while(1); /* not reached */ -} - - -#if !defined(CONFIG_PCIPPC2) && \ - !defined(CONFIG_BAB7xx) && \ - !defined(CONFIG_ELPPC) -/* no generic way to do board reset. simply call soft_reset. */ -void -do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr; - /* flush and disable I/D cache */ - __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); - __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); - __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); - __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 4"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 5"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; -#else - /* - * note: when CFG_MONITOR_BASE points to a RAM address, - * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid - * address. Better pick an address known to be invalid on your - * system and assign it to CFG_RESET_ADDRESS. - */ - addr = CFG_MONITOR_BASE - sizeof (ulong); -#endif - soft_restart(addr); - while(1); /* not reached */ -} -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * For the 7400 the TB clock runs at 1/4 the cpu bus speed. - */ -#ifdef CONFIG_AMIGAONEG3SE -unsigned long get_tbclk(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - return (gd->bus_clk / 4); -} -#else /* ! CONFIG_AMIGAONEG3SE */ - -unsigned long get_tbclk (void) -{ - return CFG_BUS_HZ / 4; -} -#endif /* CONFIG_AMIGAONEG3SE */ -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) -#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx) -void -watchdog_reset(void) -{ - -} -#endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */ -#endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/74xx_7xx/cpu_init.c b/cpu/74xx_7xx/cpu_init.c deleted file mode 100644 index 93f180f..0000000 --- a/cpu/74xx_7xx/cpu_init.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * cpu_init.c - low level cpu init - * - * there's really nothing going on here yet. future work area? - */ - -#include -#include <74xx_7xx.h> - -/* - * Breath some life into the CPU... - * - * there's basically nothing to do here since the memory controller - * isn't on the CPU in this case. - */ -void -cpu_init_f (void) -{ - switch (get_cpu_type()) { - case CPU_7450: - case CPU_7455: - case CPU_7457: - /* enable the timebase bit in HID0 */ - set_hid0(get_hid0() | 0x4000000); - break; - default: - /* do nothing */ - break; - } -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r (void) -{ - return (0); -} diff --git a/cpu/74xx_7xx/interrupts.c b/cpu/74xx_7xx/interrupts.c deleted file mode 100644 index f0ea485..0000000 --- a/cpu/74xx_7xx/interrupts.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * interrupts.c - just enough support for the decrementer/timer - */ - -#include -#include -#include -#include -#include -#include - -int interrupt_init_cpu (unsigned *decrementer_count) -{ -#if defined(DEBUG) && !defined(CONFIG_AMIGAONEG3SE) - printf("interrupt_init: GT main cause reg: %08x:%08x\n", - GTREGREAD(LOW_INTERRUPT_CAUSE_REGISTER), - GTREGREAD(HIGH_INTERRUPT_CAUSE_REGISTER)); - printf("interrupt_init: ethernet cause regs: %08x %08x %08x\n", - GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER), - GTREGREAD(ETHERNET1_INTERRUPT_CAUSE_REGISTER), - GTREGREAD(ETHERNET2_INTERRUPT_CAUSE_REGISTER)); - printf("interrupt_init: ethernet mask regs: %08x %08x %08x\n", - GTREGREAD(ETHERNET0_INTERRUPT_MASK_REGISTER), - GTREGREAD(ETHERNET1_INTERRUPT_MASK_REGISTER), - GTREGREAD(ETHERNET2_INTERRUPT_MASK_REGISTER)); - puts("interrupt_init: setting decrementer_count\n"); -#endif - *decrementer_count = get_tbclk() / CFG_HZ; - - return (0); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void -external_interrupt(struct pt_regs *regs) -{ - puts("external_interrupt (oops!)\n"); -} - -volatile ulong timestamp = 0; - -/* - * timer_interrupt - gets called when the decrementer overflows, - * with interrupts disabled. - * Trivial implementation - no need to be really accurate. - */ -void -timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} - -/****************************************************************************/ - -/* - * Install and free a interrupt handler. - */ - -void -irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) -{ - -} - -void -irq_free_handler(int vec) -{ - -} - -/****************************************************************************/ - -void -do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - puts("IRQ related functions are unimplemented currently.\n"); -} diff --git a/cpu/74xx_7xx/io.S b/cpu/74xx_7xx/io.S deleted file mode 100644 index af2e6d1..0000000 --- a/cpu/74xx_7xx/io.S +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH - * Andreas Heppel - * Copyright (C) 2002 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in16 -in16: - lhz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in16r -in16r: - lhbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0(3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in32r -in32r: - lwbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16 -out16: - sth r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16r -out16r: - sthbrx r4,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32r -out32r: - stwbrx r4,0,r3 - sync - blr diff --git a/cpu/74xx_7xx/kgdb.S b/cpu/74xx_7xx/kgdb.S deleted file mode 100644 index e838513..0000000 --- a/cpu/74xx_7xx/kgdb.S +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2000 Murray Jensen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307USA - */ - -#include -#include -#include <74xx_7xx.h> -#include - -#include -#include - -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - - /* - * cache flushing routines for kgdb - */ - - .globl kgdb_flush_cache_all -kgdb_flush_cache_all: - lis r3,0 - addis r4,r0,0x0040 -kgdb_flush_loop: - lwz r5,0(r3) - addi r3,r3,CFG_CACHELINE_SIZE - cmp 0,0,r3,r4 - bne kgdb_flush_loop - SYNC - mfspr r3,1008 - ori r3,r3,0x8800 - mtspr 1008,r3 - sync - blr - - .globl kgdb_flush_cache_range -kgdb_flush_cache_range: - li r5,CFG_CACHELINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,CFG_CACHELINE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CFG_CACHELINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CFG_CACHELINE_SIZE - bdnz 2b - SYNC - blr - -#endif /* CFG_CMD_KGDB */ diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c deleted file mode 100644 index f94ff78..0000000 --- a/cpu/74xx_7xx/speed.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include <74xx_7xx.h> -#include - -#ifdef CONFIG_AMIGAONEG3SE -#include "../board/MAI/AmigaOneG3SE/via686.h" -#endif - -static const int hid1_multipliers_x_10[] = { - 25, /* 0000 - 2.5x */ - 75, /* 0001 - 7.5x */ - 70, /* 0010 - 7x */ - 10, /* 0011 - bypass */ - 20, /* 0100 - 2x */ - 65, /* 0101 - 6.5x */ - 100, /* 0110 - 10x */ - 45, /* 0111 - 4.5x */ - 30, /* 1000 - 3x */ - 55, /* 1001 - 5.5x */ - 40, /* 1010 - 4x */ - 50, /* 1011 - 5x */ - 80, /* 1100 - 8x */ - 60, /* 1101 - 6x */ - 35, /* 1110 - 3.5x */ - 0 /* 1111 - off */ -}; - -static const int hid1_fx_multipliers_x_10[] = { - 00, /* 0000 - off */ - 00, /* 0001 - off */ - 10, /* 0010 - bypass */ - 10, /* 0011 - bypass */ - 20, /* 0100 - 2x */ - 25, /* 0101 - 2.5x */ - 30, /* 0110 - 3x */ - 35, /* 0111 - 3.5x */ - 40, /* 1000 - 4x */ - 45, /* 1001 - 4.5x */ - 50, /* 1010 - 5x */ - 55, /* 1011 - 5.5x */ - 60, /* 1100 - 6x */ - 65, /* 1101 - 6.5x */ - 70, /* 1110 - 7x */ - 75, /* 1111 - 7.5 */ - 80, /* 10000 - 8x */ - 85, /* 10001 - 8.5x */ - 90, /* 10010 - 9x */ - 95, /* 10011 - 9.5x */ - 100, /* 10100 - 10x */ - 110, /* 10101 - 11x */ - 120, /* 10110 - 12x */ -}; - - -/* ------------------------------------------------------------------------- */ - -/* - * Measure CPU clock speed (core clock GCLK1, GCLK2) - * - * (Approx. GCLK frequency in Hz) - */ - -int get_clocks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - ulong clock = 0; - - /* calculate the clock frequency based upon the CPU type */ - switch (get_cpu_type()) { - case CPU_7455: - case CPU_7457: - /* - * It is assumed that the PLL_EXT line is zero. - * Make sure division is done before multiplication to prevent 32-bit - * arithmetic overflows which will cause a negative number - */ - clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF]; - break; - - case CPU_750GX: - case CPU_750FX: - clock = CFG_BUS_CLK * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; - break; - - case CPU_7450: - case CPU_740: - case CPU_740P: - case CPU_745: - case CPU_750CX: - case CPU_750: - case CPU_750P: - case CPU_755: - case CPU_7400: - case CPU_7410: - /* - * Make sure division is done before multiplication to prevent 32-bit - * arithmetic overflows which will cause a negative number - */ - clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[get_hid1 () >> 28]; - break; - - case CPU_UNKNOWN: - printf ("get_gclk_freq(): unknown CPU type\n"); - clock = 0; - return (1); - } - - gd->cpu_clk = clock; - gd->bus_clk = CFG_BUS_CLK; - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S deleted file mode 100644 index ff1cce5..0000000 --- a/cpu/74xx_7xx/start.S +++ /dev/null @@ -1,897 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000,2001,2002 Wolfgang Denk - * Copyright (C) 2001 Josh Huber - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* U-Boot - Startup Code for PowerPC based Embedded Boards - * - * - * The processor starts at 0xfff00100 and the code is executed - * from flash. The code is organized to be at an other address - * in memory, but as long we don't jump around before relocating. - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - */ -#include -#include <74xx_7xx.h> -#include - -#include -#include - -#include -#include - -#if !defined(CONFIG_DB64360) && \ - !defined(CONFIG_DB64460) && \ - !defined(CONFIG_CPCI750) -#include -#endif - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Machine Check and Recoverable Interr. */ -#define MSR_KERNEL ( MSR_ME | MSR_RI ) - -/* - * Set up GOT: Global Offset Table - * - * Use r14 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ - b boot_cold - sync - - . = EXC_OFF_SYS_RESET + 0x10 - - .globl _start_warm -_start_warm: - li r21, BOOTFLAG_WARM /* Software reboot */ - b boot_warm - sync - - /* the boot code is located below the exception table */ - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - - /* No FPU on MPC8xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - /* - * On the MPC8xx, this is a software emulation interrupt. It - * occurs for all unimplemented and illegal instructions. - */ - STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) - - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x2000 - -boot_cold: -boot_warm: - /* disable everything */ - li r0, 0 - mtspr HID0, r0 - sync - mtmsr 0 - bl invalidate_bats - sync - -#ifdef CFG_L2 - /* init the L2 cache */ - addis r3, r0, L2_INIT@h - ori r3, r3, L2_INIT@l - sync - mtspr l2cr, r3 -#endif -#if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx) - .long 0x7e00066c - /* - * dssall instruction, gas doesn't have it yet - * ...for altivec, data stream stop all this probably - * isn't needed unless we warm (software) reboot U-Boot - */ -#endif - -#ifdef CFG_L2 - /* invalidate the L2 cache */ - bl l2cache_invalidate - sync -#endif -#ifdef CFG_BOARD_ASM_INIT - /* do early init */ - bl board_asm_init -#endif - - /* - * Calculate absolute address in FLASH and jump there - *------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*------------------------------------------------------*/ - - /* perform low-level init */ - /* sdram init, galileo init, etc */ - /* r3: NHR bit from HID0 */ - - /* setup the bats */ - bl setup_bats - sync - - /* - * Cache must be enabled here for stack-in-cache trick. - * This means we need to enable the BATS. - * This means: - * 1) for the EVB, original gt regs need to be mapped - * 2) need to have an IBAT for the 0xf region, - * we are running there! - * Cache should be turned on after BATs, since by default - * everything is write-through. - * The init-mem BAT can be reused after reloc. The old - * gt-regs BAT can be reused after board_init_f calls - * board_early_init_f (EVB only). - */ -#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) - /* enable address translation */ - bl enable_addr_trans - sync - - /* enable and invalidate the data cache */ - bl l1dcache_enable - sync -#endif -#ifdef CFG_INIT_RAM_LOCK - bl lock_ram_in_cache - sync -#endif - - /* set up the stack pointer in our newly created - * cache-ram (r1) */ - lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - GET_GOT /* initialize GOT access */ - - /* run low-level CPU init code (from Flash) */ - bl cpu_init_f - sync - - mr r3, r21 - - /* r3: BOOTFLAG */ - /* run 1st part of board init code (from Flash) */ - bl board_init_f - sync - - /* NOTREACHED */ - - .globl invalidate_bats -invalidate_bats: - /* invalidate BATs */ - mtspr IBAT0U, r0 - mtspr IBAT1U, r0 - mtspr IBAT2U, r0 - mtspr IBAT3U, r0 -#ifdef CONFIG_750FX - mtspr IBAT4U, r0 - mtspr IBAT5U, r0 - mtspr IBAT6U, r0 - mtspr IBAT7U, r0 -#endif - isync - mtspr DBAT0U, r0 - mtspr DBAT1U, r0 - mtspr DBAT2U, r0 - mtspr DBAT3U, r0 -#ifdef CONFIG_750FX - mtspr DBAT4U, r0 - mtspr DBAT5U, r0 - mtspr DBAT6U, r0 - mtspr DBAT7U, r0 -#endif - isync - sync - blr - - /* setup_bats - set them up to some initial state */ - .globl setup_bats -setup_bats: - addis r0, r0, 0x0000 - - /* IBAT 0 */ - addis r4, r0, CFG_IBAT0L@h - ori r4, r4, CFG_IBAT0L@l - addis r3, r0, CFG_IBAT0U@h - ori r3, r3, CFG_IBAT0U@l - mtspr IBAT0L, r4 - mtspr IBAT0U, r3 - isync - - /* DBAT 0 */ - addis r4, r0, CFG_DBAT0L@h - ori r4, r4, CFG_DBAT0L@l - addis r3, r0, CFG_DBAT0U@h - ori r3, r3, CFG_DBAT0U@l - mtspr DBAT0L, r4 - mtspr DBAT0U, r3 - isync - - /* IBAT 1 */ - addis r4, r0, CFG_IBAT1L@h - ori r4, r4, CFG_IBAT1L@l - addis r3, r0, CFG_IBAT1U@h - ori r3, r3, CFG_IBAT1U@l - mtspr IBAT1L, r4 - mtspr IBAT1U, r3 - isync - - /* DBAT 1 */ - addis r4, r0, CFG_DBAT1L@h - ori r4, r4, CFG_DBAT1L@l - addis r3, r0, CFG_DBAT1U@h - ori r3, r3, CFG_DBAT1U@l - mtspr DBAT1L, r4 - mtspr DBAT1U, r3 - isync - - /* IBAT 2 */ - addis r4, r0, CFG_IBAT2L@h - ori r4, r4, CFG_IBAT2L@l - addis r3, r0, CFG_IBAT2U@h - ori r3, r3, CFG_IBAT2U@l - mtspr IBAT2L, r4 - mtspr IBAT2U, r3 - isync - - /* DBAT 2 */ - addis r4, r0, CFG_DBAT2L@h - ori r4, r4, CFG_DBAT2L@l - addis r3, r0, CFG_DBAT2U@h - ori r3, r3, CFG_DBAT2U@l - mtspr DBAT2L, r4 - mtspr DBAT2U, r3 - isync - - /* IBAT 3 */ - addis r4, r0, CFG_IBAT3L@h - ori r4, r4, CFG_IBAT3L@l - addis r3, r0, CFG_IBAT3U@h - ori r3, r3, CFG_IBAT3U@l - mtspr IBAT3L, r4 - mtspr IBAT3U, r3 - isync - - /* DBAT 3 */ - addis r4, r0, CFG_DBAT3L@h - ori r4, r4, CFG_DBAT3L@l - addis r3, r0, CFG_DBAT3U@h - ori r3, r3, CFG_DBAT3U@l - mtspr DBAT3L, r4 - mtspr DBAT3U, r3 - isync - -#ifdef CONFIG_750FX - /* IBAT 4 */ - addis r4, r0, CFG_IBAT4L@h - ori r4, r4, CFG_IBAT4L@l - addis r3, r0, CFG_IBAT4U@h - ori r3, r3, CFG_IBAT4U@l - mtspr IBAT4L, r4 - mtspr IBAT4U, r3 - isync - - /* DBAT 4 */ - addis r4, r0, CFG_DBAT4L@h - ori r4, r4, CFG_DBAT4L@l - addis r3, r0, CFG_DBAT4U@h - ori r3, r3, CFG_DBAT4U@l - mtspr DBAT4L, r4 - mtspr DBAT4U, r3 - isync - - /* IBAT 5 */ - addis r4, r0, CFG_IBAT5L@h - ori r4, r4, CFG_IBAT5L@l - addis r3, r0, CFG_IBAT5U@h - ori r3, r3, CFG_IBAT5U@l - mtspr IBAT5L, r4 - mtspr IBAT5U, r3 - isync - - /* DBAT 5 */ - addis r4, r0, CFG_DBAT5L@h - ori r4, r4, CFG_DBAT5L@l - addis r3, r0, CFG_DBAT5U@h - ori r3, r3, CFG_DBAT5U@l - mtspr DBAT5L, r4 - mtspr DBAT5U, r3 - isync - - /* IBAT 6 */ - addis r4, r0, CFG_IBAT6L@h - ori r4, r4, CFG_IBAT6L@l - addis r3, r0, CFG_IBAT6U@h - ori r3, r3, CFG_IBAT6U@l - mtspr IBAT6L, r4 - mtspr IBAT6U, r3 - isync - - /* DBAT 6 */ - addis r4, r0, CFG_DBAT6L@h - ori r4, r4, CFG_DBAT6L@l - addis r3, r0, CFG_DBAT6U@h - ori r3, r3, CFG_DBAT6U@l - mtspr DBAT6L, r4 - mtspr DBAT6U, r3 - isync - - /* IBAT 7 */ - addis r4, r0, CFG_IBAT7L@h - ori r4, r4, CFG_IBAT7L@l - addis r3, r0, CFG_IBAT7U@h - ori r3, r3, CFG_IBAT7U@l - mtspr IBAT7L, r4 - mtspr IBAT7U, r3 - isync - - /* DBAT 7 */ - addis r4, r0, CFG_DBAT7L@h - ori r4, r4, CFG_DBAT7L@l - addis r3, r0, CFG_DBAT7U@h - ori r3, r3, CFG_DBAT7U@l - mtspr DBAT7L, r4 - mtspr DBAT7U, r3 - isync -#endif - - /* bats are done, now invalidate the TLBs */ - - addis r3, 0, 0x0000 - addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */ - - isync - -tlblp: - tlbie r3 - sync - addi r3, r3, 0x1000 - cmp 0, 0, r3, r5 - blt tlblp - - blr - - .globl enable_addr_trans -enable_addr_trans: - /* enable address translation */ - mfmsr r5 - ori r5, r5, (MSR_IR | MSR_DR) - mtmsr r5 - isync - blr - - .globl disable_addr_trans -disable_addr_trans: - /* disable address translation */ - mflr r4 - mfmsr r3 - andi. r0, r3, (MSR_IR | MSR_DR) - beqlr - andc r3, r3, r0 - mtspr SRR0, r4 - mtspr SRR1, r3 - rfi - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - - .globl dc_read -dc_read: - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -/*-----------------------------------------------------------------------*/ -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r14, r14, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ -#ifdef CONFIG_ECC - bl board_relocate_rom - sync - mr r3, r10 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ -#else - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b -#endif -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: -#ifdef CONFIG_ECC - bl board_init_ecc -#endif - /* - * Relocation Function, r14 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - add r0,r0,r11 - stw r0,0(r3) - bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ -2: li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -/* clear_bss: */ - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - mr r3, r10 /* Destination Address */ -#if defined(CONFIG_AMIGAONEG3SE) || \ - defined(CONFIG_DB64360) || \ - defined(CONFIG_DB64460) || \ - defined(CONFIG_CPCI750) - mr r4, r9 /* Use RAM copy of the global data */ -#endif - bl after_reloc - - /* not reached - end relocate_code */ -/*-----------------------------------------------------------------------*/ - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - /* enable execptions from RAM vectors */ - mfmsr r7 - li r8,MSR_IP - andc r7,r7,r8 - mtmsr r7 - - mtlr r4 /* restore link register */ - blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - sync - isync - - blr - -#ifdef CFG_INIT_RAM_LOCK -lock_ram_in_cache: - /* Allocate Initial RAM in data cache. - */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2, ((CFG_INIT_RAM_END & ~31) + \ - (CFG_INIT_RAM_ADDR & 31) + 31) / 32 - mtctr r2 -1: - dcbz r0, r3 - addi r3, r3, 32 - bdnz 1b - - /* Lock the data cache */ - mfspr r0, HID0 - ori r0, r0, 0x1000 - sync - mtspr HID0, r0 - sync - blr - -.globl unlock_ram_in_cache -unlock_ram_in_cache: - /* invalidate the INIT_RAM section */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2, ((CFG_INIT_RAM_END & ~31) + \ - (CFG_INIT_RAM_ADDR & 31) + 31) / 32 - mtctr r2 -1: icbi r0, r3 - addi r3, r3, 32 - bdnz 1b - sync /* Wait for all icbi to complete on bus */ - isync - - /* Unlock the data cache and invalidate it */ - mfspr r0, HID0 - li r3,0x1000 - andc r0,r0,r3 - li r3,0x0400 - or r0,r0,r3 - sync - mtspr HID0, r0 - sync - blr -#endif diff --git a/cpu/74xx_7xx/traps.c b/cpu/74xx_7xx/traps.c deleted file mode 100644 index ac5f8bf..0000000 --- a/cpu/74xx_7xx/traps.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * linux/arch/ppc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -int (*debugger_exception_handler)(struct pt_regs *) = 0; -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#ifdef CONFIG_AMIGAONEG3SE -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) -#else -#define END_OF_MEM 0x02000000 -#endif - -/* - * Trap & Exception support - */ - -void -print_backtrace(unsigned long *sp) -{ -#ifdef CONFIG_AMIGAONEG3SE - DECLARE_GLOBAL_DATA_PTR; -#endif - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void -show_regs(struct pt_regs * regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS:" - " %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP:" - " %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -void -_exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void -MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void -AlignmentException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void -ProgramCheckException(struct pt_regs *regs) -{ - unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; - int i, j; - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - - p = (unsigned char *) ((unsigned long)p & 0xFFFFFFE0); - p -= 32; - for (i = 0; i < 256; i+=16) { - printf("%08x: ", (unsigned int)p+i); - for (j = 0; j < 16; j++) { - printf("%02x ", p[i+j]); - } - printf("\n"); - } - - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void -SoftEmuException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void -UnknownException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int -addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/cpu/arm1136/Makefile b/cpu/arm1136/Makefile deleted file mode 100644 index 203278e..0000000 --- a/cpu/arm1136/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = interrupts.o cpu.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk deleted file mode 100644 index e39e774..0000000 --- a/cpu/arm1136/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float - -# Make ARMv5 to allow more compilers to work, even though its v6. -PLATFORM_CPPFLAGS += -march=armv5 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c deleted file mode 100644 index 85a4849..0000000 --- a/cpu/arm1136/cpu.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * (C) Copyright 2004 Texas Insturments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include -#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) -#include -#endif - -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_WB (1<<3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - DECLARE_GLOBAL_DATA_PTR; - - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - unsigned long i; - - disable_interrupts (); - -#ifdef CONFIG_LCD - { - extern void lcd_disable(void); - extern void lcd_panel_disable(void); - - lcd_disable(); /* proper disable of lcd & panel */ - lcd_panel_disable(); - } -#endif - - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ - asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ - return(0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return(0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return(read_p15_c1 () & C1_IC) != 0; -} diff --git a/cpu/arm1136/interrupts.c b/cpu/arm1136/interrupts.c deleted file mode 100644 index 1dc36d0..0000000 --- a/cpu/arm1136/interrupts.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments - * Richard Woodruff - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) -# include -#endif - -#include - -#define TIMER_LOAD_VAL 0 - -/* macro to read the 32 bit timer */ -#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR)) - -#ifdef CONFIG_USE_IRQ -/* enable IRQ interrupts */ -void enable_interrupts (void) -{ - unsigned long temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); -} - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ - unsigned long old,temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); - return(old & 0x80) == 0; -} -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32", - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) -/* Use the IntegratorCP function from board/integratorcp.c */ -#else - -static ulong timestamp; -static ulong lastinc; - -/* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init (void) -{ - int32_t val; - - /* Start the counter ticking up */ - *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ - val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ - *((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */ - - reset_timer_masked(); /* init the timestamp and lastinc value */ - - return(0); -} -/* - * timer without interrupts - */ -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -/* delay x useconds AND perserve advance timstamp value */ -void udelay (unsigned long usec) -{ - ulong tmo, tmp; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; - tmo /= (1000*1000); - } - - tmp = get_timer (0); /* get current timestamp */ - if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ - reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ - else - tmo += tmp; /* else, set advancing stamp wake up time */ - while (get_timer_masked () < tmo)/* loop till event */ - /*NOP*/; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastinc = READ_TIMER; /* capture current incrementer value time */ - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; /* current tick value */ - - if (now >= lastinc) /* normal mode (non roll) */ - timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */ - else /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - lastinc = now; - return timestamp; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; - tmo /= (1000*1000); - } - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - tbclk = CFG_HZ; - return tbclk; -} -#endif /* !Integrator/CP */ diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S deleted file mode 100644 index 17c7a83..0000000 --- a/cpu/arm1136/start.S +++ /dev/null @@ -1,417 +0,0 @@ -/* - * armboot - Startup Code for OMP2420/ARM1136 CPU-core - * - * Copyright (c) 2004 Texas Instruments - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) -#include -#endif -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq -_pad: .word 0x12345678 /* now 16*4=64 */ -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - -#ifdef CONFIG_OMAP2420H4 - /* Copy vectors to mask ROM indirect addr */ - adr r0, _start /* r0 <- current position of code */ - add r0, r0, #4 /* skip reset vector */ - mov r2, #64 /* r2 <- size to copy */ - add r2, r0, r2 /* r2 <- source end address */ - mov r1, #SRAM_OFFSET0 /* build vect addr */ - mov r3, #SRAM_OFFSET1 - add r1, r1, r3 - mov r3, #SRAM_OFFSET2 - add r1, r1, r3 -next: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next /* loop until equal */ - bl cpy_clk_code /* put dpll adjust code behind vectors */ -#endif - /* the mask ROM code should have PLL and others stable */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - -#ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - bne clbss_l - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - mcr p15, 0, r0, c1, c0, 0 - - /* - * Jump to board specific initialization... The Mask ROM will have already initialized - * basic memory. Go here to bump up clock rate and handle wake up conditions. - */ - mov ip, lr /* persevere link reg across call */ - bl lowlevel_init /* go setup pll,mux,memory */ - mov lr, ip /* restore link */ - mov pc, lr /* back to my caller */ -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, _armboot_start - sub r2, r2, #(CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack (enter in banked mode) - sub r13, r13, #(CFG_MALLOC_LEN) @ move past malloc pool - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_bad_stack_swi - sub r13, r13, #4 @ space on current stack for scratch reg. - str r0, [r13] @ save R0's value. - ldr r0, _armboot_start @ get data regions start - sub r0, r0, #(CFG_MALLOC_LEN) @ move past malloc pool - sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack - str lr, [r0] @ save caller lr in position 0 of saved stack - mrs r0, spsr @ get the spsr - str lr, [r0, #4] @ save spsr in position 1 of saved stack - ldr r0, [r13] @ restore r0 - add r13, r13, #4 @ pop stack entry - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - .align 5 -.global arm1136_cache_flush -arm1136_cache_flush: - mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache - mov pc, lr @ back to caller - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) -/* Use the IntegratorCP function from board/integratorcp/platform.S */ -#else - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r1, rstctl /* get addr for global reset reg */ - mov r3, #0x2 /* full reset pll+mpu */ - str r3, [r1] /* force reset */ - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PM_RSTCTRL_WKUP - -#endif diff --git a/cpu/arm720t/Makefile b/cpu/arm720t/Makefile deleted file mode 100644 index f273d92..0000000 --- a/cpu/arm720t/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = serial.o serial_netarm.o interrupts.o cpu.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/arm720t/config.mk b/cpu/arm720t/config.mk deleted file mode 100644 index 641b91c..0000000 --- a/cpu/arm720t/config.mk +++ /dev/null @@ -1,35 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c deleted file mode 100644 index a5b6de7..0000000 --- a/cpu/arm720t/cpu.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include -#include -#include - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - * and we set the CPU-speed to 73 MHz - see start.S for details - */ - -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - unsigned long i; - - disable_interrupts (); - - /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -#ifdef CONFIG_ARM7_REVD - /* go to high speed */ - IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; -#endif -#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) - disable_interrupts (); - /* Nothing more needed */ -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No cleanup before linux for IntegratorAP/CM720T as yet */ -#else -#error No cleanup_before_linux() defined for this CPU type -#endif - return 0; -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -/* - * Instruction and Data cache enable and disable functions - * - */ - -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1(void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - /* printf("p15/c1 is = %08lx\n", value); */ - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1(unsigned long value) -{ - /* printf("write %08lx to p15/c1\n", value); */ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1(); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_IDC (1<<2) /* icache and/or dcache off/on */ -#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_IDC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IDC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IDC) != 0; -} - -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_IDC); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IDC); -} - -int dcache_status (void) -{ - return (read_p15_c1 () & C1_IDC) != 0; -} - -#elif defined(CONFIG_S3C4510B) - -void icache_enable (void) -{ - s32 i; - - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); - - /* 8KB cache, write enable */ - SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); - - /* clear TAG RAM bits */ - for ( i = 0; i < 256; i++) - PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); - - /* clear SET0 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); - - /* clear SET1 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); - - /* enable cache */ - SET_REG( REG_SYSCFG, CACHE_ENABLE); - -} - -void icache_disable (void) -{ - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); -} - -int icache_status (void) -{ - return GET_REG( REG_SYSCFG) & CACHE_ENABLE; -} - -void dcache_enable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_enable(); -} - -void dcache_disable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_disable(); -} - -int dcache_status (void) -{ - /* we don't have seperate instruction/data caches */ - return icache_status(); -} - -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No specific cache setup for IntegratorAP/CM720T as yet */ - void icache_enable (void) - { - } -#else -#error No icache/dcache enable/disable functions defined for this CPU type -#endif diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c deleted file mode 100644 index da62502..0000000 --- a/cpu/arm720t/interrupts.c +++ /dev/null @@ -1,413 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#ifndef CONFIG_NETARM -/* we always count down the max. */ -#define TIMER_LOAD_VAL 0xffff -/* macro to read the 16 bit timer */ -#define READ_TIMER (IO_TC1D & 0xffff) -#else -#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE)) -#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL)) -#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS)) -#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK -#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK) -#endif - -#ifdef CONFIG_S3C4510B -/* require interrupts for the S3C4510B */ -# ifndef CONFIG_USE_IRQ -# error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B -# else -static struct _irq_handler IRQ_HANDLER[N_IRQS]; -# endif -#endif /* CONFIG_S3C4510B */ - -#ifdef CONFIG_USE_IRQ -/* enable IRQ/FIQ interrupts */ -void enable_interrupts (void) -{ - unsigned long temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); -} - - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ - unsigned long old,temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0x80\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); - return (old & 0x80) == 0; -} -#else /* CONFIG_USE_IRQ */ -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = - { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26", -"UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26", - "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", - "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32", - "UK14_32", "SYS_32" - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -#elif defined(CONFIG_S3C4510B) - unsigned int pending; - - while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */ - IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data); - - /* clear pending interrupt */ - PUT_REG( REG_INTPEND, (1<<(pending>>2))); - } -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No do_irq() for IntegratorAP/CM720T as yet */ -#else -#error do_irq() not defined for this CPU type -#endif -} - - -#ifdef CONFIG_S3C4510B -static void default_isr( void *data) { - printf ("default_isr(): called for IRQ %d\n", (int)data); -} - -static void timer_isr( void *data) { - unsigned int *pTime = (unsigned int *)data; - - (*pTime)++; - if ( !(*pTime % (CFG_HZ/4))) { - /* toggle LED 0 */ - PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1); - } - -} -#endif - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* Use IntegratorAP routines in board/integratorap.c */ -#else - -static ulong timestamp; -static ulong lastdec; - -int interrupt_init (void) -{ - -#if defined(CONFIG_NETARM) - /* disable all interrupts */ - IRQEN = 0; - - /* operate timer 2 in non-prescale mode */ - TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) | - NETARM_GEN_TCTL_ENABLE | - NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL)); - - /* set timer 2 counter */ - lastdec = TIMER_LOAD_VAL; -#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - /* disable all interrupts */ - IO_INTMR1 = 0; - - /* operate timer 1 in prescale mode */ - IO_SYSCON1 |= SYSCON1_TC1M; - - /* select 2kHz clock source for timer 1 */ - IO_SYSCON1 &= ~SYSCON1_TC1S; - - /* set timer 1 counter */ - lastdec = IO_TC1D = TIMER_LOAD_VAL; -#elif defined(CONFIG_S3C4510B) - int i; - - /* install default interrupt handlers */ - for ( i = 0; i < N_IRQS; i++) { - IRQ_HANDLER[i].m_data = (void *)i; - IRQ_HANDLER[i].m_func = default_isr; - } - - /* configure interrupts for IRQ mode */ - PUT_REG( REG_INTMODE, 0x0); - /* clear any pending interrupts */ - PUT_REG( REG_INTPEND, 0x1FFFFF); - - lastdec = 0; - - /* install interrupt handler for timer */ - IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp; - IRQ_HANDLER[INT_TIMER0].m_func = timer_isr; - - /* configure free running timer 0 */ - PUT_REG( REG_TMOD, 0x0); - /* Stop timer 0 */ - CLR_REG( REG_TMOD, TM0_RUN); - - /* Configure for interval mode */ - CLR_REG( REG_TMOD, TM1_TOGGLE); - - /* - * Load Timer data register with count down value. - * count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ - */ - PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ)); - - /* - * Enable global interrupt - * Enable timer0 interrupt - */ - CLR_REG( REG_INTMASK, ((1<= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CFG_HZ; - tmo /= 1000; - } else { - tmo = usec * CFG_HZ; - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -#elif defined(CONFIG_S3C4510B) - -ulong get_timer (ulong base) -{ - return timestamp - base; -} - -void udelay (unsigned long usec) -{ - u32 ticks; - - ticks = (usec * CFG_HZ) / 1000000; - - ticks += get_timer (0); - - while (get_timer (0) < ticks) - /*NOP*/; - -} - -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No timer routines for IntegratorAP/CM720T as yet */ -#else -#error Timer routines not defined for this CPU type -#endif diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c deleted file mode 100644 index 0f99979..0000000 --- a/cpu/arm720t/serial.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include - -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - -#include - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned int reg = 0; - - switch (gd->baudrate) { - case 1200: reg = 191; break; - case 9600: reg = 23; break; - case 19200: reg = 11; break; - case 38400: reg = 5; break; - case 57600: reg = 3; break; - case 115200: reg = 1; break; - default: hang (); break; - } - - /* init serial serial 1,2 */ - IO_SYSCON1 = SYSCON1_UART1EN; - IO_SYSCON2 = SYSCON2_UART2EN; - - reg |= UBRLCR_WRDLEN8; - - IO_UBRLCR1 = reg; - IO_UBRLCR2 = reg; -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - int tmo; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); - - tmo = get_timer (0) + 1 * CFG_HZ; - while (IO_SYSFLG1 & SYSFLG1_UTXFF) - if (get_timer (0) > tmo) - break; - - IO_UARTDR1 = c; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_tstc (void) -{ - return !(IO_SYSFLG1 & SYSFLG1_URXFE); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - while (IO_SYSFLG1 & SYSFLG1_URXFE); - - return IO_UARTDR1 & 0xff; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#endif /* defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) */ diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c deleted file mode 100644 index 5ad98f0..0000000 --- a/cpu/arm720t/serial_netarm.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Serial Port stuff - taken from Linux - * - * (C) Copyright 2002 - * MAZeT GmbH - * Stephan Linz , - * - * (c) 2004 - * IMMS gGmbH - * Thomas Elste - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include - -#ifdef CONFIG_NETARM - -#include - -#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA)) -#if !defined(CONFIG_NETARM_NS7520) -#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB)) -#else -#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC)) -#endif - -/* wait until transmitter is ready for another character */ -#define TXWAITRDY(registers) \ -{ \ - ulong tmo = get_timer(0) + 1 * CFG_HZ; \ - while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \ - if (get_timer(0) > tmo) \ - break; \ - } \ -} - - -#ifndef CONFIG_UART1_CONSOLE -volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0); -volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1); -#else -volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(1); -volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(0); -#endif - -extern void _netarm_led_FAIL1(void); - -/* - * Setup both serial i/f with given baudrate - */ -void serial_setbrg (void) -{ - /* get the gd pointer */ - DECLARE_GLOBAL_DATA_PTR; - - /* set 0 ... make sure pins are configured for serial */ -#if !defined(CONFIG_NETARM_NS7520) - PORTA = PORTB = - NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); -#else - PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); - PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); -#endif - - /* first turn em off */ - serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0; - - /* clear match register, we don't need it */ - serial_reg_ch1->rx_match = serial_reg_ch2->rx_match = 0; - - /* setup bit rate generator and rx buffer gap timer (1 byte only) */ - if ((gd->baudrate >= MIN_BAUD_RATE) - && (gd->baudrate <= MAX_BAUD_RATE)) { - serial_reg_ch1->bitrate = serial_reg_ch2->bitrate = - NETARM_SER_BR_X16 (gd->baudrate); - serial_reg_ch1->rx_buf_timer = serial_reg_ch2->rx_buf_timer = - 0; - serial_reg_ch1->rx_char_timer = serial_reg_ch2->rx_char_timer = - NETARM_SER_RXGAP (gd->baudrate); - } else { - hang (); - } - - /* setup port mode */ - serial_reg_ch1->ctrl_b = serial_reg_ch2->ctrl_b = - ( NETARM_SER_CTLB_RCGT_EN | - NETARM_SER_CTLB_UART_MODE); - serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = - ( NETARM_SER_CTLA_ENABLE | - NETARM_SER_CTLA_P_NONE | - /* see errata */ - NETARM_SER_CTLA_2STOP | - NETARM_SER_CTLA_8BITS | - NETARM_SER_CTLA_DTR_EN | - NETARM_SER_CTLA_RTS_EN); -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - */ -int serial_init (void) -{ - serial_setbrg (); - return 0; -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - volatile unsigned char *fifo; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); - - fifo = (volatile unsigned char *) &(serial_reg_ch1->fifo); - TXWAITRDY (serial_reg_ch1); - *fifo = c; -} - -/* - * Test of a single byte from the serial port. Returns 1 on success, 0 - * otherwise. - */ -int serial_tstc(void) -{ - return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. - */ -int serial_getc (void) -{ - unsigned int ch_uint; - volatile unsigned int *fifo; - volatile unsigned char *fifo_char = NULL; - int buf_count = 0; - - while (!(serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY)) - /* NOP */ ; - - fifo = (volatile unsigned int *) &(serial_reg_ch1->fifo); - fifo_char = (unsigned char *) &ch_uint; - ch_uint = *fifo; - - buf_count = NETARM_SER_STATA_RXFDB (serial_reg_ch1->status_a); - switch (buf_count) { - case NETARM_SER_STATA_RXFDB_4BYTES: - buf_count = 4; - break; - case NETARM_SER_STATA_RXFDB_3BYTES: - buf_count = 3; - break; - case NETARM_SER_STATA_RXFDB_2BYTES: - buf_count = 2; - break; - case NETARM_SER_STATA_RXFDB_1BYTES: - buf_count = 1; - break; - default: - /* panic, be never here */ - break; - } - - serial_reg_ch1->status_a |= NETARM_SER_STATA_RX_CLOSED; - - return ch_uint & 0xff; -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#endif /* CONFIG_NETARM */ diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S deleted file mode 100644 index e66d109..0000000 --- a/cpu/arm720t/start.S +++ /dev/null @@ -1,542 +0,0 @@ -/* - * armboot - Startup Code for ARM720 CPU-core - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from RAM! - * relocate armboot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0x13 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - -#ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - -#if TEXT_BASE - ldr r2, =0x0 /* Relocate the exception vectors */ - cmp r1, r2 /* and associated data to address */ - ldmneia r0!, {r3-r10} /* 0x0. Do nothing if TEXT_BASE is */ - stmneia r2!, {r3-r10} /* 0x0. Copy the first 15 words. */ - ldmneia r0, {r3-r9} - stmneia r2, {r3-r9} - adrne r0, _start /* restore r0 */ -#endif - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop - -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - -/* Interupt-Controller base addresses */ -INTMR1: .word 0x80000280 @ 32 bit size -INTMR2: .word 0x80001280 @ 16 bit size -INTMR3: .word 0x80002280 @ 8 bit size - -/* SYSCONs */ -SYSCON1: .word 0x80000100 -SYSCON2: .word 0x80001100 -SYSCON3: .word 0x80002200 - -#define CLKCTL 0x6 /* mask */ -#define CLKCTL_18 0x0 /* 18.432 MHz */ -#define CLKCTL_36 0x2 /* 36.864 MHz */ -#define CLKCTL_49 0x4 /* 49.152 MHz */ -#define CLKCTL_73 0x6 /* 73.728 MHz */ - -#endif - -cpu_init_crit: -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - - /* - * mask all IRQs by clearing all bits in the INTMRs - */ - mov r1, #0x00 - ldr r0, INTMR1 - str r1, [r0] - ldr r0, INTMR2 - str r1, [r0] - ldr r0, INTMR3 - str r1, [r0] - - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15,0,r0,c1,c0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - mcr p15,0,r0,c1,c0 -#elif defined(CONFIG_NETARM) - /* - * prior to software reset : need to set pin PORTC4 to be *HRESET - */ - ldr r0, =NETARM_GEN_MODULE_BASE - ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \ - NETARM_GEN_PORT_DIR(0x10)) - str r1, [r0, #+NETARM_GEN_PORTC] - /* - * software reset : see HW Ref. Guide 8.2.4 : Software Service register - * for an explanation of this process - */ - ldr r0, =NETARM_GEN_MODULE_BASE - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - /* - * setup PLL and System Config - */ - ldr r0, =NETARM_GEN_MODULE_BASE - - ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \ - NETARM_GEN_SYS_CFG_BUSFULL | \ - NETARM_GEN_SYS_CFG_USER_EN | \ - NETARM_GEN_SYS_CFG_ALIGN_ABORT | \ - NETARM_GEN_SYS_CFG_BUSARB_INT | \ - NETARM_GEN_SYS_CFG_BUSMON_EN ) - - str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL] - -#ifndef CONFIG_NETARM_PLL_BYPASS - ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \ - NETARM_GEN_PLL_CTL_POLTST_DEF | \ - NETARM_GEN_PLL_CTL_INDIV(1) | \ - NETARM_GEN_PLL_CTL_ICP_DEF | \ - NETARM_GEN_PLL_CTL_OUTDIV(2) ) - str r1, [r0, #+NETARM_GEN_PLL_CONTROL] -#endif - - /* - * mask all IRQs by clearing all bits in the INTMRs - */ - mov r1, #0 - ldr r0, =NETARM_GEN_MODULE_BASE - str r1, [r0, #+NETARM_GEN_INTR_ENABLE] - -#elif defined(CONFIG_S3C4510B) - - /* - * Mask off all IRQ sources - */ - ldr r1, =REG_INTMASK - ldr r0, =0x3FFFFF - str r0, [r1] - - /* - * Disable Cache - */ - ldr r0, =REG_SYSCFG - ldr r1, =0x83ffffa0 /* cache-disabled */ - str r1, [r0] - -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No specific initialisation for IntegratorAP/CM720T as yet */ -#else -#error No cpu_init_crit() defined for current CPU type -#endif - -#ifdef CONFIG_ARM7_REVD - /* set clock speed */ - /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */ - /* !!! not doing DRAM refresh properly! */ - ldr r0, SYSCON3 - ldr r1, [r0] - bic r1, r1, #CLKCTL - orr r1, r1, #CLKCTL_36 - str r1, [r0] -#endif - - mov ip, lr - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependent, you will - * find a lowlevel_init.S in your board directory. - */ - bl lowlevel_init - mov lr, ip - - mov pc, lr - - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - - ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - .align 5 -.globl reset_cpu -reset_cpu: - mov ip, #0 - mcr p15, 0, ip, c7, c7, 0 @ invalidate cache - mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) - mrc p15, 0, ip, c1, c0, 0 @ get ctrl register - bic ip, ip, #0x000f @ ............wcam - bic ip, ip, #0x2100 @ ..v....s........ - mcr p15, 0, ip, c1, c0, 0 @ ctrl register - mov pc, r0 -#elif defined(CONFIG_NETARM) - .align 5 -.globl reset_cpu -reset_cpu: - ldr r1, =NETARM_MEM_MODULE_BASE - ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] - ldr r1, =0xFFFFF000 - and r0, r1, r0 - ldr r1, =(relocate-TEXT_BASE) - add r0, r1, r0 - ldr r4, =NETARM_GEN_MODULE_BASE - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - mov pc, r0 -#elif defined(CONFIG_S3C4510B) -/* Nothing done here as reseting the CPU is board specific, depending - * on external peripherals such as watchdog timers, etc. */ -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No specific reset actions for IntegratorAP/CM720T as yet */ -#else -#error No reset_cpu() defined for current CPU type -#endif diff --git a/cpu/arm920t/Makefile b/cpu/arm920t/Makefile deleted file mode 100644 index 8f256e9..0000000 --- a/cpu/arm920t/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = cpu.o interrupts.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile deleted file mode 100644 index aec9cb6..0000000 --- a/cpu/arm920t/at91rm9200/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2000-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(SOC).a - -OBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ - lxt972.o serial.o usb_ohci.o -SOBJS = lowlevel_init.o - -all: .depend $(LIB) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/arm920t/at91rm9200/bcm5221.c b/cpu/arm920t/at91rm9200/bcm5221.c deleted file mode 100644 index 6db1435..0000000 --- a/cpu/arm920t/at91rm9200/bcm5221.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Broadcom BCM5221 Ethernet PHY - * - * (C) Copyright 2005 REA Elektronik GmbH - * Anders Larsen - * - * (C) Copyright 2003 - * Author : Hamid Ikdoumi (Atmel) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_DRIVER_ETHER - -#if (CONFIG_COMMANDS & CFG_CMD_NET) - -/* - * Name: - * bcm5221_IsPhyConnected - * Description: - * Reads the 2 PHY ID registers - * Arguments: - * p_mac - pointer to AT91S_EMAC struct - * Return value: - * TRUE - if id read successfully - * FALSE- if error - */ -unsigned int bcm5221_IsPhyConnected (AT91PS_EMAC p_mac) -{ - unsigned short Id1, Id2; - - at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID1, &Id1); - at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID2, &Id2); - at91rm9200_EmacDisableMDIO (p_mac); - - if ((Id1 == (BCM5221_PHYID1_OUI >> 6)) && - ((Id2 >> 10) == (BCM5221_PHYID1_OUI & BCM5221_LSB_MASK))) - return TRUE; - - return FALSE; -} - -/* - * Name: - * bcm5221_GetLinkSpeed - * Description: - * Link parallel detection status of MAC is checked and set in the - * MAC configuration registers - * Arguments: - * p_mac - pointer to MAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -unsigned char bcm5221_GetLinkSpeed (AT91PS_EMAC p_mac) -{ - unsigned short stat1, stat2; - - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &stat1)) - return FALSE; - - if (!(stat1 & BCM5221_LINK_STATUS)) /* link status up? */ - return FALSE; - - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ACSR, &stat2)) - return FALSE; - - if ((stat1 & BCM5221_100BASE_TX_FD) && (stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) { - /*set Emac for 100BaseTX and Full Duplex */ - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - return TRUE; - } - - if ((stat1 & BCM5221_10BASE_T_FD) && !(stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) { - /*set MII for 10BaseT and Full Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - return TRUE; - } - - if ((stat1 & BCM5221_100BASE_TX_HD) && (stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) { - /*set MII for 100BaseTX and Half Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_SPD; - return TRUE; - } - - if ((stat1 & BCM5221_10BASE_T_HD) && !(stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) { - /*set MII for 10BaseT and Half Duplex */ - p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); - return TRUE; - } - return FALSE; -} - - -/* - * Name: - * bcm5221_InitPhy - * Description: - * MAC starts checking its link by using parallel detection and - * Autonegotiation and the same is set in the MAC configuration registers - * Arguments: - * p_mac - pointer to struct AT91S_EMAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -unsigned char bcm5221_InitPhy (AT91PS_EMAC p_mac) -{ - unsigned char ret = TRUE; - unsigned short IntValue; - - at91rm9200_EmacEnableMDIO (p_mac); - - if (!bcm5221_GetLinkSpeed (p_mac)) { - /* Try another time */ - ret = bcm5221_GetLinkSpeed (p_mac); - } - - /* Disable PHY Interrupts */ - at91rm9200_EmacReadPhy (p_mac, BCM5221_INTR, &IntValue); - /* clear FDX LED and INTR Enable */ - IntValue &= ~(BCM5221_FDX_LED | BCM5221_INTR_ENABLE); - /* set FDX, SPD, Link, INTR masks */ - IntValue |= (BCM5221_FDX_MASK | BCM5221_SPD_MASK | - BCM5221_LINK_MASK | BCM5221_INTR_MASK); - at91rm9200_EmacWritePhy (p_mac, BCM5221_INTR, &IntValue); - at91rm9200_EmacDisableMDIO (p_mac); - - return (ret); -} - - -/* - * Name: - * bcm5221_AutoNegotiate - * Description: - * MAC Autonegotiates with the partner status of same is set in the - * MAC configuration registers - * Arguments: - * dev - pointer to struct net_device - * Return value: - * TRUE - if link status set successfully - * FALSE - if link status not set - */ -unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status) -{ - unsigned short value; - unsigned short PhyAnar; - unsigned short PhyAnalpar; - - /* Set bcm5221 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value)) - return FALSE; - value &= ~BCM5221_AUTONEG; /* remove autonegotiation enable */ - value |= BCM5221_ISOLATE; /* Electrically isolate PHY */ - if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value)) - return FALSE; - - /* Set the Auto_negotiation Advertisement Register */ - /* MII advertising for 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ - PhyAnar = BCM5221_TX_FDX | BCM5221_TX_HDX | - BCM5221_10_FDX | BCM5221_10_HDX | BCM5221_AN_IEEE_802_3; - if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_ANAR, &PhyAnar)) - return FALSE; - - /* Read the Control Register */ - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value)) - return FALSE; - - value |= BCM5221_SPEED_SELECT | BCM5221_AUTONEG | BCM5221_DUPLEX_MODE; - if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value)) - return FALSE; - /* Restart Auto_negotiation */ - value |= BCM5221_RESTART_AUTONEG; - value &= ~BCM5221_ISOLATE; - if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value)) - return FALSE; - - /*check AutoNegotiate complete */ - udelay (10000); - at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &value); - if (!(value & BCM5221_AUTONEG_COMP)) - return FALSE; - - /* Get the AutoNeg Link partner base page */ - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ANLPAR, &PhyAnalpar)) - return FALSE; - - if ((PhyAnar & BCM5221_TX_FDX) && (PhyAnalpar & BCM5221_TX_FDX)) { - /*set MII for 100BaseTX and Full Duplex */ - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - return TRUE; - } - - if ((PhyAnar & BCM5221_10_FDX) && (PhyAnalpar & BCM5221_10_FDX)) { - /*set MII for 10BaseT and Full Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - return TRUE; - } - return FALSE; -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/dm9161.c b/cpu/arm920t/at91rm9200/dm9161.c deleted file mode 100644 index 4b13c23..0000000 --- a/cpu/arm920t/at91rm9200/dm9161.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * (C) Copyright 2003 - * Author : Hamid Ikdoumi (Atmel) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_DRIVER_ETHER - -#if (CONFIG_COMMANDS & CFG_CMD_NET) - -/* - * Name: - * dm9161_IsPhyConnected - * Description: - * Reads the 2 PHY ID registers - * Arguments: - * p_mac - pointer to AT91S_EMAC struct - * Return value: - * TRUE - if id read successfully - * FALSE- if error - */ -unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac) -{ - unsigned short Id1, Id2; - - at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1); - at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2); - at91rm9200_EmacDisableMDIO (p_mac); - - if ((Id1 == (DM9161_PHYID1_OUI >> 6)) && - ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK))) - return TRUE; - - return FALSE; -} - -/* - * Name: - * dm9161_GetLinkSpeed - * Description: - * Link parallel detection status of MAC is checked and set in the - * MAC configuration registers - * Arguments: - * p_mac - pointer to MAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac) -{ - unsigned short stat1, stat2; - - if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1)) - return FALSE; - - if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */ - return FALSE; - - if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2)) - return FALSE; - - if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) { - /*set Emac for 100BaseTX and Full Duplex */ - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - return TRUE; - } - - if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) { - /*set MII for 10BaseT and Full Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - return TRUE; - } - - if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) { - /*set MII for 100BaseTX and Half Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_SPD; - return TRUE; - } - - if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) { - /*set MII for 10BaseT and Half Duplex */ - p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); - return TRUE; - } - return FALSE; -} - - -/* - * Name: - * dm9161_InitPhy - * Description: - * MAC starts checking its link by using parallel detection and - * Autonegotiation and the same is set in the MAC configuration registers - * Arguments: - * p_mac - pointer to struct AT91S_EMAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac) -{ - UCHAR ret = TRUE; - unsigned short IntValue; - - at91rm9200_EmacEnableMDIO (p_mac); - - if (!dm9161_GetLinkSpeed (p_mac)) { - /* Try another time */ - ret = dm9161_GetLinkSpeed (p_mac); - } - - /* Disable PHY Interrupts */ - at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue); - /* set FDX, SPD, Link, INTR masks */ - IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK | - DM9161_LINK_MASK | DM9161_INTR_MASK); - at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue); - at91rm9200_EmacDisableMDIO (p_mac); - - return (ret); -} - - -/* - * Name: - * dm9161_AutoNegotiate - * Description: - * MAC Autonegotiates with the partner status of same is set in the - * MAC configuration registers - * Arguments: - * dev - pointer to struct net_device - * Return value: - * TRUE - if link status set successfully - * FALSE - if link status not set - */ -UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status) -{ - unsigned short value; - unsigned short PhyAnar; - unsigned short PhyAnalpar; - - /* Set dm9161 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value)) - return FALSE; - value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */ - value |= DM9161_ISOLATE; /* Electrically isolate PHY */ - if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) - return FALSE; - - /* Set the Auto_negotiation Advertisement Register */ - /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ - PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX | - DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; - if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar)) - return FALSE; - - /* Read the Control Register */ - if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value)) - return FALSE; - - value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE; - if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) - return FALSE; - /* Restart Auto_negotiation */ - value |= DM9161_RESTART_AUTONEG; - value &= ~DM9161_ISOLATE; - if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) - return FALSE; - - /*check AutoNegotiate complete */ - udelay (10000); - at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value); - if (!(value & DM9161_AUTONEG_COMP)) - return FALSE; - - /* Get the AutoNeg Link partner base page */ - if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar)) - return FALSE; - - if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) { - /*set MII for 100BaseTX and Full Duplex */ - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - return TRUE; - } - - if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) { - /*set MII for 10BaseT and Full Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - return TRUE; - } - return FALSE; -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/ether.c b/cpu/arm920t/at91rm9200/ether.c deleted file mode 100644 index 67008d0..0000000 --- a/cpu/arm920t/at91rm9200/ether.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * (C) Copyright 2003 - * Author : Hamid Ikdoumi (Atmel) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* ----- Ethernet Buffer definitions ----- */ - -typedef struct { - unsigned long addr, size; -} rbf_t; - -#define RBF_ADDR 0xfffffffc -#define RBF_OWNER (1<<0) -#define RBF_WRAP (1<<1) -#define RBF_BROADCAST (1<<31) -#define RBF_MULTICAST (1<<30) -#define RBF_UNICAST (1<<29) -#define RBF_EXTERNAL (1<<28) -#define RBF_UNKOWN (1<<27) -#define RBF_SIZE 0x07ff -#define RBF_LOCAL4 (1<<26) -#define RBF_LOCAL3 (1<<25) -#define RBF_LOCAL2 (1<<24) -#define RBF_LOCAL1 (1<<23) - -#define RBF_FRAMEMAX 64 -#define RBF_FRAMELEN 0x600 - -#ifdef CONFIG_DRIVER_ETHER - -#if (CONFIG_COMMANDS & CFG_CMD_NET) - -/* alignment as per Errata #11 (64 bytes) is insufficient! */ -rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512))); -rbf_t *rbfp; - -unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN] __attribute((aligned(4))); - -/* structure to interface the PHY */ -AT91S_PhyOps PhyOps; - -AT91PS_EMAC p_mac; - -/*********** EMAC Phy layer Management functions *************************/ -/* - * Name: - * at91rm9200_EmacEnableMDIO - * Description: - * Enables the MDIO bit in MAC control register - * Arguments: - * p_mac - pointer to struct AT91S_EMAC - * Return value: - * none - */ -void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac) -{ - /* Mac CTRL reg set for MDIO enable */ - p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */ -} - -/* - * Name: - * at91rm9200_EmacDisableMDIO - * Description: - * Disables the MDIO bit in MAC control register - * Arguments: - * p_mac - pointer to struct AT91S_EMAC - * Return value: - * none - */ -void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac) -{ - /* Mac CTRL reg set for MDIO disable */ - p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */ -} - - -/* - * Name: - * at91rm9200_EmacReadPhy - * Description: - * Reads data from the PHY register - * Arguments: - * dev - pointer to struct net_device - * RegisterAddress - unsigned char - * pInput - pointer to value read from register - * Return value: - * TRUE - if data read successfully - */ -UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac, - unsigned char RegisterAddress, - unsigned short *pInput) -{ - p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) | - (AT91C_EMAC_RW_R) | - (RegisterAddress << 18) | - (AT91C_EMAC_CODE_802_3); - - udelay (10000); - - *pInput = (unsigned short) p_mac->EMAC_MAN; - - return TRUE; -} - - -/* - * Name: - * at91rm9200_EmacWritePhy - * Description: - * Writes data to the PHY register - * Arguments: - * dev - pointer to struct net_device - * RegisterAddress - unsigned char - * pOutput - pointer to value to be written in the register - * Return value: - * TRUE - if data read successfully - */ -UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac, - unsigned char RegisterAddress, - unsigned short *pOutput) -{ - p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) | - AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W | - (RegisterAddress << 18) | *pOutput; - - udelay (10000); - - return TRUE; -} - -int eth_init (bd_t * bd) -{ - int ret; - int i; - - p_mac = AT91C_BASE_EMAC; - - /* PIO Disable Register */ - *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | - AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | - AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | - AT91C_PA7_ETXCK_EREFCK; - -#ifdef CONFIG_AT91C_USE_RMII - *AT91C_PIOB_PDR = AT91C_PB19_ERXCK; - *AT91C_PIOB_BSR = AT91C_PB19_ERXCK; -#else - *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | - AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | - AT91C_PB13_ETX3 | AT91C_PB12_ETX2; - - /* Select B Register */ - *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | - AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | - AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; -#endif - - *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */ - - p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */ - - /* Init Ehternet buffers */ - for (i = 0; i < RBF_FRAMEMAX; i++) { - rbfdt[i].addr = (unsigned long)rbf_framebuf[i]; - rbfdt[i].size = 0; - } - rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; - rbfp = &rbfdt[0]; - - p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16) - | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]); - p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]); - - p_mac->EMAC_RBQP = (long) (&rbfdt[0]); - p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA); - - p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC) - & ~AT91C_EMAC_CLK; - -#ifdef CONFIG_AT91C_USE_RMII - p_mac->EMAC_CFG |= AT91C_EMAC_RMII; -#endif - -#if (AT91C_MASTER_CLOCK > 40000000) - /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ - p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64; -#endif - - p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE; - - at91rm9200_GetPhyInterface (& PhyOps); - - if (!PhyOps.IsPhyConnected (p_mac)) - printf ("PHY not connected!!\n\r"); - - /* MII management start from here */ - if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) { - if (!(ret = PhyOps.Init (p_mac))) { - printf ("MAC: error during MII initialization\n"); - return 0; - } - } else { - printf ("No link\n\r"); - return 0; - } - - return 0; -} - -int eth_send (volatile void *packet, int length) -{ - while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ)); - p_mac->EMAC_TAR = (long) packet; - p_mac->EMAC_TCR = length; - while (p_mac->EMAC_TCR & 0x7ff); - p_mac->EMAC_TSR |= AT91C_EMAC_COMP; - return 0; -} - -int eth_rx (void) -{ - int size; - - if (!(rbfp->addr & RBF_OWNER)) - return 0; - - size = rbfp->size & RBF_SIZE; - NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size); - - rbfp->addr &= ~RBF_OWNER; - if (rbfp->addr & RBF_WRAP) - rbfp = &rbfdt[0]; - else - rbfp++; - - p_mac->EMAC_RSR |= AT91C_EMAC_REC; - - return size; -} - -void eth_halt (void) -{ -}; - -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) -int at91rm9200_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short * value) -{ - at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy (p_mac, reg, value); - at91rm9200_EmacDisableMDIO (p_mac); - return 0; -} - -int at91rm9200_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacWritePhy (p_mac, reg, &value); - at91rm9200_EmacDisableMDIO (p_mac); - return 0; -} - -#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */ - -int at91rm9200_miiphy_initialize(bd_t *bis) -{ -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) - miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write); -#endif - return 0; -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/i2c.c b/cpu/arm920t/at91rm9200/i2c.c deleted file mode 100644 index 2565998..0000000 --- a/cpu/arm920t/at91rm9200/i2c.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * i2c Support for Atmel's AT91RM9200 Two-Wire Interface - * - * (c) Rick Bronson - * - * Borrowed heavily from original work by: - * Copyright (c) 2000 Philip Edelbrock - * - * Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * -*/ -#include - -#ifdef CONFIG_HARD_I2C - -#include -#include -#include - -#include - -/* define DEBUG */ - -/* - * Poll the i2c status register until the specified bit is set. - * Returns 0 if timed out (100 msec) - */ -static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) { - int loop_cntr = 10000; - do { - udelay(10); - } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0)); - - return (loop_cntr > 0); -} - -/* - * Generic i2c master transfer entrypoint - * - * rw == 1 means that this is a read - */ -static int -at91_xfer(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len, int rw) -{ - AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; - int length; - unsigned char *buf; - /* Set the TWI Master Mode Register */ - twi->TWI_MMR = (chip << 16) | (alen << 8) - | ((rw == 1) ? AT91C_TWI_MREAD : 0); - - /* Set TWI Internal Address Register with first messages data field */ - if (alen > 0) - twi->TWI_IADR = addr; - - length = len; - buf = buffer; - if (length && buf) { /* sanity check */ - if (rw) { - twi->TWI_CR = AT91C_TWI_START; - while (length--) { - if (!length) - twi->TWI_CR = AT91C_TWI_STOP; - /* Wait until transfer is finished */ - if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) { - debug ("at91_i2c: timeout 1\n"); - return 1; - } - *buf++ = twi->TWI_RHR; - } - if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { - debug ("at91_i2c: timeout 2\n"); - return 1; - } - } else { - twi->TWI_CR = AT91C_TWI_START; - while (length--) { - twi->TWI_THR = *buf++; - if (!length) - twi->TWI_CR = AT91C_TWI_STOP; - if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) { - debug ("at91_i2c: timeout 3\n"); - return 1; - } - } - /* Wait until transfer is finished */ - if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { - debug ("at91_i2c: timeout 4\n"); - return 1; - } - } - } - return 0; -} - -int -i2c_probe(unsigned char chip) -{ - char buffer[1]; - - return at91_xfer(chip, 0, 0, buffer, 1, 1); -} - -int -i2c_read (unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len) -{ -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - /* we only allow one address byte */ - if (alen > 1) - return 1; - /* XXX assume an ATMEL AT24C16 */ - if (alen == 1) { -#if 0 /* EEPROM code already sets this correctly */ - chip |= (addr >> 8) & 0xff; -#endif - addr = addr & 0xff; - } -#endif - return at91_xfer(chip, addr, alen, buffer, len, 1); -} - -int -i2c_write(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len) -{ -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - int i; - unsigned char *buf; - - /* we only allow one address byte */ - if (alen > 1) - return 1; - /* XXX assume an ATMEL AT24C16 */ - if (alen == 1) { - buf = buffer; - /* do single byte writes */ - for (i = 0; i < len; i++) { -#if 0 /* EEPROM code already sets this correctly */ - chip |= (addr >> 8) & 0xff; -#endif - addr = addr & 0xff; - if (at91_xfer(chip, addr, alen, buf++, 1, 0)) - return 1; - addr++; - } - return 0; - } -#endif - return at91_xfer(chip, addr, alen, buffer, len, 0); -} - -/* - * Main initialization routine - */ -void -i2c_init(int speed, int slaveaddr) -{ - AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; - - *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */ - - twi->TWI_IDR = 0x3ff; /* Disable all interrupts */ - twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */ - twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */ - - /* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */ - twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8); - - debug ("Found AT91 i2c\n"); - return; -} - -uchar i2c_reg_read(uchar i2c_addr, uchar reg) -{ - char buf; - - i2c_read(i2c_addr, reg, 1, &buf, 1); - - return(buf); -} - -void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write(i2c_addr, reg, 1, &val, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/arm920t/at91rm9200/interrupts.c b/cpu/arm920t/at91rm9200/interrupts.c deleted file mode 100644 index 1054602..0000000 --- a/cpu/arm920t/at91rm9200/interrupts.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * (C) Copyright 2002 - * Lineo, Inc. - * Bernhard Kuhn - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -/*#include */ -#include -/*#include */ - -/* the number of clocks per CFG_HZ */ -#define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ) - -/* macro to read the 16 bit timer */ -#define READ_TIMER (tmr->TC_CV & 0x0000ffff) -AT91PS_TC tmr; - -static ulong timestamp; -static ulong lastinc; - -int interrupt_init (void) -{ - tmr = AT91C_BASE_TC0; - - /* enables TC1.0 clock */ - *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */ - - *AT91C_TCB0_BCR = 0; - *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE; - tmr->TC_CCR = AT91C_TC_CLKDIS; -#define AT91C_TC_CMR_CPCTRG (1 << 14) - /* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */ - tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG; - - tmr->TC_IDR = ~0ul; - tmr->TC_RC = TIMER_LOAD_VAL; - lastinc = 0; - tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN; - timestamp = 0; - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - udelay_masked(usec); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastinc = READ_TIMER; - timestamp = 0; -} - -ulong get_timer_raw (void) -{ - ulong now = READ_TIMER; - - if (now >= lastinc) { - /* normal mode */ - timestamp += now - lastinc; - } else { - /* we have an overflow ... */ - timestamp += now + TIMER_LOAD_VAL - lastinc; - } - lastinc = now; - - return timestamp; -} - -ulong get_timer_masked (void) -{ - return get_timer_raw()/TIMER_LOAD_VAL; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - tmo = CFG_HZ_CLOCK / 1000; - tmo *= usec; - tmo /= 1000; - - endtime = get_timer_raw () + tmo; - - do { - ulong now = get_timer_raw (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = CFG_HZ; - return tbclk; -} - -/* - * Reset the cpu by setting up the watchdog timer and let him time out - * or toggle a GPIO pin on the AT91RM9200DK board - */ -void reset_cpu (ulong ignored) -{ - -#ifdef CONFIG_DBGU - AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU; -#endif -#ifdef CONFIG_USART0 - AT91PS_USART us = AT91C_BASE_US0; -#endif -#ifdef CONFIG_USART1 - AT91PS_USART us = AT91C_BASE_US1; -#endif -#ifdef CONFIG_AT91RM9200DK - AT91PS_PIO pio = AT91C_BASE_PIOA; -#endif - - /*shutdown the console to avoid strange chars during reset */ - us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX); - -#ifdef CONFIG_AT91RM9200DK - /* Clear PA19 to trigger the hard reset */ - pio->PIO_CODR = 0x00080000; - pio->PIO_OER = 0x00080000; - pio->PIO_PER = 0x00080000; -#endif - - /* this is the way Linux does it */ - - /* FIXME: - * These defines should be moved into - * include/asm-arm/arch-at91rm9200/AT91RM9200.h - * as soon as the whitespace fix gets applied. - */ - #define AT91C_ST_RSTEN (0x1 << 16) - #define AT91C_ST_EXTEN (0x1 << 17) - #define AT91C_ST_WDRST (0x1 << 0) - #define ST_WDMR *((unsigned long *)0xfffffd08) /* watchdog mode register */ - #define ST_CR *((unsigned long *)0xfffffd00) /* system clock control register */ - - ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ; - ST_CR = AT91C_ST_WDRST; - - while (1); - /* Never reached */ -} diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S deleted file mode 100644 index 1902bd0..0000000 --- a/cpu/arm920t/at91rm9200/lowlevel_init.S +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the at91rm9200dk board by - * (C) Copyright 2004 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -/* - * some parameters for the board - * - * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in - * turn is based on the boot.bin code from ATMEL - * - */ - -/* flash */ -#define MC_PUIA 0xFFFFFF10 -#define MC_PUP 0xFFFFFF50 -#define MC_PUER 0xFFFFFF54 -#define MC_ASR 0xFFFFFF04 -#define MC_AASR 0xFFFFFF08 -#define EBI_CFGR 0xFFFFFF64 -#define SMC2_CSR 0xFFFFFF70 - -/* clocks */ -#define PLLAR 0xFFFFFC28 -#define PLLBR 0xFFFFFC2C -#define MCKR 0xFFFFFC30 - -#define AT91C_BASE_CKGR 0xFFFFFC20 -#define CKGR_MOR 0 - -/* sdram */ -#define PIOC_ASR 0xFFFFF870 -#define PIOC_BSR 0xFFFFF874 -#define PIOC_PDR 0xFFFFF804 -#define EBI_CSA 0xFFFFFF60 -#define SDRC_CR 0xFFFFFF98 -#define SDRC_MR 0xFFFFFF90 -#define SDRC_TR 0xFFFFFF94 - - -_MTEXT_BASE: -#undef START_FROM_MEM -#ifdef START_FROM_MEM - .word TEXT_BASE-PHYS_FLASH_1 -#else - .word TEXT_BASE -#endif - -.globl lowlevel_init -lowlevel_init: - /* Get the CKGR Base Address */ - ldr r1, =AT91C_BASE_CKGR - /* Main oscillator Enable register */ -#ifdef CFG_USE_MAIN_OSCILLATOR - ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */ -#else - ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */ -#endif - str r0, [r1, #CKGR_MOR] - /* Add loop to compensate Main Oscillator startup time */ - ldr r0, =0x00000010 -LoopOsc: - subs r0, r0, #1 - bhi LoopOsc - - /* memory control configuration */ - /* this isn't very elegant, but what the heck */ - ldr r0, =SMRDATA - ldr r1, _MTEXT_BASE - sub r0, r0, r1 - add r2, r0, #80 -0: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 0b - /* delay - this is all done by guess */ - ldr r0, =0x00010000 -1: - subs r0, r0, #1 - bhi 1b - ldr r0, =SMRDATA1 - ldr r1, _MTEXT_BASE - sub r0, r0, r1 - add r2, r0, #176 -2: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 2b - - /* switch from FastBus to Asynchronous clock mode */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0xC0000000 @ set bit 31 (iA) and 30 (nF) - mcr p15, 0, r0, c1, c0, 0 - - /* everything is fine now */ - mov pc, lr - - .ltorg - -SMRDATA: - .word MC_PUIA - .word MC_PUIA_VAL - .word MC_PUP - .word MC_PUP_VAL - .word MC_PUER - .word MC_PUER_VAL - .word MC_ASR - .word MC_ASR_VAL - .word MC_AASR - .word MC_AASR_VAL - .word EBI_CFGR - .word EBI_CFGR_VAL - .word SMC2_CSR - .word SMC2_CSR_VAL - .word PLLAR - .word PLLAR_VAL - .word PLLBR - .word PLLBR_VAL - .word MCKR - .word MCKR_VAL - /* SMRDATA is 80 bytes long */ - /* here there's a delay of 100 */ -SMRDATA1: - .word PIOC_ASR - .word PIOC_ASR_VAL - .word PIOC_BSR - .word PIOC_BSR_VAL - .word PIOC_PDR - .word PIOC_PDR_VAL - .word EBI_CSA - .word EBI_CSA_VAL - .word SDRC_CR - .word SDRC_CR_VAL - .word SDRC_MR - .word SDRC_MR_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRC_MR - .word SDRC_MR_VAL1 - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRC_MR - .word SDRC_MR_VAL2 - .word SDRAM1 - .word SDRAM_VAL - .word SDRC_TR - .word SDRC_TR_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRC_MR - .word SDRC_MR_VAL3 - .word SDRAM - .word SDRAM_VAL - /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/cpu/arm920t/at91rm9200/lxt972.c b/cpu/arm920t/at91rm9200/lxt972.c deleted file mode 100644 index f12c59c..0000000 --- a/cpu/arm920t/at91rm9200/lxt972.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * - * (C) Copyright 2003 - * Author : Hamid Ikdoumi (Atmel) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Adapted for KwikByte KB920x board: 22APR2005 - */ - -#include -#include -#include -#include - -#ifdef CONFIG_DRIVER_ETHER - -#if (CONFIG_COMMANDS & CFG_CMD_NET) - -/* - * Name: - * lxt972_IsPhyConnected - * Description: - * Reads the 2 PHY ID registers - * Arguments: - * p_mac - pointer to AT91S_EMAC struct - * Return value: - * TRUE - if id read successfully - * FALSE- if error - */ -unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac) -{ - unsigned short Id1, Id2; - - at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID1, &Id1); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID2, &Id2); - at91rm9200_EmacDisableMDIO (p_mac); - - if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0)) - return TRUE; - - return FALSE; -} - -/* - * Name: - * lxt972_GetLinkSpeed - * Description: - * Link parallel detection status of MAC is checked and set in the - * MAC configuration registers - * Arguments: - * p_mac - pointer to MAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac) -{ - unsigned short stat1; - - if (!at91rm9200_EmacReadPhy (p_mac, PHY_LXT971_STAT2, &stat1)) - return FALSE; - - if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link status up? */ - return FALSE; - - if (stat1 & PHY_LXT971_STAT2_100BTX) { - - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - - /*set Emac for 100BaseTX and Full Duplex */ - p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; - } else { - - /*set Emac for 100BaseTX and Half Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_SPD; - } - - return TRUE; - - } else { - - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - - /*set MII for 10BaseT and Full Duplex */ - p_mac->EMAC_CFG = (p_mac->EMAC_CFG & - ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) - | AT91C_EMAC_FD; - } else { - - /*set MII for 10BaseT and Half Duplex */ - p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); - } - - return TRUE; - } - - return FALSE; -} - - -/* - * Name: - * lxt972_InitPhy - * Description: - * MAC starts checking its link by using parallel detection and - * Autonegotiation and the same is set in the MAC configuration registers - * Arguments: - * p_mac - pointer to struct AT91S_EMAC - * Return value: - * TRUE - if link status set succesfully - * FALSE - if link status not set - */ -UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac) -{ - UCHAR ret = TRUE; - - at91rm9200_EmacEnableMDIO (p_mac); - - if (!lxt972_GetLinkSpeed (p_mac)) { - /* Try another time */ - ret = lxt972_GetLinkSpeed (p_mac); - } - - /* Disable PHY Interrupts */ - at91rm9200_EmacWritePhy (p_mac, PHY_LXT971_INT_ENABLE, 0); - - at91rm9200_EmacDisableMDIO (p_mac); - - return (ret); -} - - -/* - * Name: - * lxt972_AutoNegotiate - * Description: - * MAC Autonegotiates with the partner status of same is set in the - * MAC configuration registers - * Arguments: - * dev - pointer to struct net_device - * Return value: - * TRUE - if link status set successfully - * FALSE - if link status not set - */ -UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status) -{ - unsigned short value; - - /* Set lxt972 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_CTRL, &value)) - return FALSE; - - /* Restart Auto_negotiation */ - value |= PHY_COMMON_CTRL_RES_AUTO; - if (!at91rm9200_EmacWritePhy (p_mac, PHY_COMMON_CTRL, &value)) - return FALSE; - - /*check AutoNegotiate complete */ - udelay (10000); - at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_STAT, &value); - if (!(value & PHY_COMMON_STAT_AN_COMP)) - return FALSE; - - return (lxt972_GetLinkSpeed (p_mac)); -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/serial.c b/cpu/arm920t/at91rm9200/serial.c deleted file mode 100644 index a281932..0000000 --- a/cpu/arm920t/at91rm9200/serial.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2002 - * Lineo, Inc - * Bernhard Kuhn - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include -#include - -#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1) -#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1 -#endif - -/* ggi thunder */ -#ifdef CONFIG_DBGU -AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU; -#endif -#ifdef CONFIG_USART0 -AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US0; -#endif -#ifdef CONFIG_USART1 -AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US1; -#endif - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - int baudrate; - - if ((baudrate = gd->baudrate) <= 0) - baudrate = CONFIG_BAUDRATE; - /* MASTER_CLOCK/(16 * baudrate) */ - us->US_BRGR = (AT91C_MASTER_CLOCK >> 4) / (unsigned)baudrate; -} - -int serial_init (void) -{ - /* make any port initializations specific to this port */ -#ifdef CONFIG_DBGU - *AT91C_PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; /* PA 31 & 30 */ - *AT91C_PMC_PCER = 1 << AT91C_ID_SYS; /* enable clock */ -#endif -#ifdef CONFIG_USART0 - *AT91C_PIOA_PDR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0; - *AT91C_PMC_PCER |= 1 << AT91C_ID_USART0; /* enable clock */ -#endif -#ifdef CONFIG_USART1 - *AT91C_PIOB_PDR = AT91C_PB21_TXD1 | AT91C_PB20_RXD1; - *AT91C_PMC_PCER |= 1 << AT91C_ID_USART1; /* enable clock */ -#endif - serial_setbrg (); - - us->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX; - us->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; - us->US_MR = - (AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS | - AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT); - us->US_IMR = ~0ul; - return (0); -} - -void serial_putc (const char c) -{ - if (c == '\n') - serial_putc ('\r'); - while ((us->US_CSR & AT91C_US_TXRDY) == 0); - us->US_THR = c; -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - while ((us->US_CSR & AT91C_US_RXRDY) == 0); - return us->US_RHR; -} - -int serial_tstc (void) -{ - return ((us->US_CSR & AT91C_US_RXRDY) == AT91C_US_RXRDY); -} diff --git a/cpu/arm920t/at91rm9200/usb_ohci.c b/cpu/arm920t/at91rm9200/usb_ohci.c deleted file mode 100644 index 5b2c56c..0000000 --- a/cpu/arm920t/at91rm9200/usb_ohci.c +++ /dev/null @@ -1,1635 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200. - * - * (C) Copyright 2003 - * Gary Jennejohn, DENX Software Engineering - * - * Note: Much of this code has been derived from Linux 2.4 - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2002 David Brownell - * - * Modified for the MP2USB by (C) Copyright 2005 Eric Benard - * ebenard@eukrea.com - based on s3c24x0's driver - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* - * IMPORTANT NOTES - * 1 - you MUST define LITTLEENDIAN in the configuration file for the - * board or this driver will NOT work! - * 2 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! - * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG - * to activate workaround for bug #41 or this driver will NOT work! - */ - -#include -/* #include no PCI on the S3C24X0 */ - -#ifdef CONFIG_USB_OHCI - -#include - -#include -#include -#include "usb_ohci.h" - -#define OHCI_USE_NPS /* force NoPowerSwitching mode */ -#undef OHCI_VERBOSE_DEBUG /* not always helpful */ - -/* For initializing controller (mask in an HCFS mode too) */ -#define OHCI_CONTROL_INIT \ - (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE - -#define readl(a) (*((vu_long *)(a))) -#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) - -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - -#undef DEBUG -#ifdef DEBUG -#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) -#else -#define dbg(format, arg...) do {} while(0) -#endif /* DEBUG */ -#define err(format, arg...) printf("ERROR: " format "\n", ## arg) -#undef SHOW_INFO -#ifdef SHOW_INFO -#define info(format, arg...) printf("INFO: " format "\n", ## arg) -#else -#define info(format, arg...) do {} while(0) -#endif - -#define m16_swap(x) swap_16(x) -#define m32_swap(x) swap_32(x) - -/* global ohci_t */ -static ohci_t gohci; -/* this must be aligned to a 256 byte boundary */ -struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* urb_priv */ -urb_priv_t urb_priv; -/* RHSC flag */ -int got_rhsc; -/* device which was disconnected */ -struct usb_device *devgone; - -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a (struct ohci *hc) - { return read_roothub (hc, a, 0xfc0fe000); } -static inline u32 roothub_b (struct ohci *hc) - { return readl (&hc->regs->roothub.b); } -static inline u32 roothub_status (struct ohci *hc) - { return readl (&hc->regs->roothub.status); } -static u32 roothub_portstatus (struct ohci *hc, int i) - { return read_roothub (hc, portstatus [i], 0xffe0fce0); } - - -/* forward declaration */ -static int hc_interrupt (void); -static void -td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); - -/*-------------------------------------------------------------------------* - * URB support functions - *-------------------------------------------------------------------------*/ - -/* free HCD-private data associated with this URB */ - -static void urb_free_priv (urb_priv_t * urb) -{ - int i; - int last; - struct td * td; - - last = urb->length - 1; - if (last >= 0) { - for (i = 0; i <= last; i++) { - td = urb->td[i]; - if (td) { - td->usb_dev = NULL; - urb->td[i] = NULL; - } - } - } -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -static int sohci_get_current_frame_number (struct usb_device * dev); - -/* debug| print the main components of an URB - * small: 0) header + data packets 1) just header */ - -static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, char * str, int small) -{ - urb_priv_t * purb = &urb_priv; - - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", - str, - sohci_get_current_frame_number (dev), - usb_pipedevice (pipe), - usb_pipeendpoint (pipe), - usb_pipeout (pipe)? 'O': 'I', - usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): - (usb_pipecontrol (pipe)? "CTRL": "BULK"), - purb->actual_length, - transfer_len, dev->status); -#ifdef OHCI_VERBOSE_DEBUG - if (!small) { - int i, len; - - if (usb_pipecontrol (pipe)) { - printf (__FILE__ ": cmd(8):"); - for (i = 0; i < 8 ; i++) - printf (" %02x", ((__u8 *) setup) [i]); - printf ("\n"); - } - if (transfer_len > 0 && buffer) { - printf (__FILE__ ": data(%d/%d):", - purb->actual_length, - transfer_len); - len = usb_pipeout (pipe)? - transfer_len: purb->actual_length; - for (i = 0; i < 16 && i < len; i++) - printf (" %02x", ((__u8 *) buffer) [i]); - printf ("%s\n", i < len? "...": ""); - } - } -#endif -} - -/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ -void ep_print_int_eds (ohci_t *ohci, char * str) { - int i, j; - __u32 * ed_p; - for (i= 0; i < 32; i++) { - j = 5; - ed_p = &(ohci->hcca->int_table [i]); - if (*ed_p == 0) - continue; - printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); - while (*ed_p != 0 && j--) { - ed_t *ed = (ed_t *)m32_swap(ed_p); - printf (" ed: %4x;", ed->hwINFO); - ed_p = &ed->hwNextED; - } - printf ("\n"); - } -} - -static void ohci_dump_intr_mask (char *label, __u32 mask) -{ - dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", - label, - mask, - (mask & OHCI_INTR_MIE) ? " MIE" : "", - (mask & OHCI_INTR_OC) ? " OC" : "", - (mask & OHCI_INTR_RHSC) ? " RHSC" : "", - (mask & OHCI_INTR_FNO) ? " FNO" : "", - (mask & OHCI_INTR_UE) ? " UE" : "", - (mask & OHCI_INTR_RD) ? " RD" : "", - (mask & OHCI_INTR_SF) ? " SF" : "", - (mask & OHCI_INTR_WDH) ? " WDH" : "", - (mask & OHCI_INTR_SO) ? " SO" : "" - ); -} - -static void maybe_print_eds (char *label, __u32 value) -{ - ed_t *edp = (ed_t *)value; - - if (value) { - dbg ("%s %08x", label, value); - dbg ("%08x", edp->hwINFO); - dbg ("%08x", edp->hwTailP); - dbg ("%08x", edp->hwHeadP); - dbg ("%08x", edp->hwNextED); - } -} - -static char * hcfs2string (int state) -{ - switch (state) { - case OHCI_USB_RESET: return "reset"; - case OHCI_USB_RESUME: return "resume"; - case OHCI_USB_OPER: return "operational"; - case OHCI_USB_SUSPEND: return "suspend"; - } - return "?"; -} - -/* dump control and status registers */ -static void ohci_dump_status (ohci_t *controller) -{ - struct ohci_regs *regs = controller->regs; - __u32 temp; - - temp = readl (®s->revision) & 0xff; - if (temp != 0x10) - dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); - - temp = readl (®s->control); - dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, - (temp & OHCI_CTRL_RWE) ? " RWE" : "", - (temp & OHCI_CTRL_RWC) ? " RWC" : "", - (temp & OHCI_CTRL_IR) ? " IR" : "", - hcfs2string (temp & OHCI_CTRL_HCFS), - (temp & OHCI_CTRL_BLE) ? " BLE" : "", - (temp & OHCI_CTRL_CLE) ? " CLE" : "", - (temp & OHCI_CTRL_IE) ? " IE" : "", - (temp & OHCI_CTRL_PLE) ? " PLE" : "", - temp & OHCI_CTRL_CBSR - ); - - temp = readl (®s->cmdstatus); - dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, - (temp & OHCI_SOC) >> 16, - (temp & OHCI_OCR) ? " OCR" : "", - (temp & OHCI_BLF) ? " BLF" : "", - (temp & OHCI_CLF) ? " CLF" : "", - (temp & OHCI_HCR) ? " HCR" : "" - ); - - ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); - ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); - - maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); - - maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); - maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); - - maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); - maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); - - maybe_print_eds ("donehead", readl (®s->donehead)); -} - -static void ohci_dump_roothub (ohci_t *controller, int verbose) -{ - __u32 temp, ndp, i; - - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); -#ifdef CONFIG_AT91C_PQFP_UHPBUG - ndp = (ndp == 2) ? 1:0; -#endif - if (verbose) { - dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, - ((temp & RH_A_POTPGT) >> 24) & 0xff, - (temp & RH_A_NOCP) ? " NOCP" : "", - (temp & RH_A_OCPM) ? " OCPM" : "", - (temp & RH_A_DT) ? " DT" : "", - (temp & RH_A_NPS) ? " NPS" : "", - (temp & RH_A_PSM) ? " PSM" : "", - ndp - ); - temp = roothub_b (controller); - dbg ("roothub.b: %08x PPCM=%04x DR=%04x", - temp, - (temp & RH_B_PPCM) >> 16, - (temp & RH_B_DR) - ); - temp = roothub_status (controller); - dbg ("roothub.status: %08x%s%s%s%s%s%s", - temp, - (temp & RH_HS_CRWE) ? " CRWE" : "", - (temp & RH_HS_OCIC) ? " OCIC" : "", - (temp & RH_HS_LPSC) ? " LPSC" : "", - (temp & RH_HS_DRWE) ? " DRWE" : "", - (temp & RH_HS_OCI) ? " OCI" : "", - (temp & RH_HS_LPS) ? " LPS" : "" - ); - } - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", - i, - temp, - (temp & RH_PS_PRSC) ? " PRSC" : "", - (temp & RH_PS_OCIC) ? " OCIC" : "", - (temp & RH_PS_PSSC) ? " PSSC" : "", - (temp & RH_PS_PESC) ? " PESC" : "", - (temp & RH_PS_CSC) ? " CSC" : "", - - (temp & RH_PS_LSDA) ? " LSDA" : "", - (temp & RH_PS_PPS) ? " PPS" : "", - (temp & RH_PS_PRS) ? " PRS" : "", - (temp & RH_PS_POCI) ? " POCI" : "", - (temp & RH_PS_PSS) ? " PSS" : "", - - (temp & RH_PS_PES) ? " PES" : "", - (temp & RH_PS_CCS) ? " CCS" : "" - ); - } -} - -static void ohci_dump (ohci_t *controller, int verbose) -{ - dbg ("OHCI controller usb-%s state", controller->slot_name); - - /* dumps some of the state we know about */ - ohci_dump_status (controller); - if (verbose) - ep_print_int_eds (controller, "hcca"); - dbg ("hcca frame #%04x", controller->hcca->frame_no); - ohci_dump_roothub (controller, 1); -} - - -#endif /* DEBUG */ - -/*-------------------------------------------------------------------------* - * Interface functions (URB) - *-------------------------------------------------------------------------*/ - -/* get a transfer request */ - -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - ohci_t *ohci; - ed_t * ed; - urb_priv_t *purb_priv; - int i, size = 0; - - ohci = &gohci; - - /* when controller's hung, permit only roothub cleanup attempts - * such as powering down ports */ - if (ohci->disabled) { - err("sohci_submit_job: EPIPE"); - return -1; - } - - /* every endpoint has a ed, locate and fill it */ - if (!(ed = ep_add_ed (dev, pipe))) { - err("sohci_submit_job: ENOMEM"); - return -1; - } - - /* for the private part of the URB we need the number of TDs (size) */ - switch (usb_pipetype (pipe)) { - case PIPE_BULK: /* one TD for every 4096 Byte */ - size = (transfer_len - 1) / 4096 + 1; - break; - case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ - size = (transfer_len == 0)? 2: - (transfer_len - 1) / 4096 + 3; - break; - } - - if (size >= (N_URB_TD - 1)) { - err("need %d TDs, only have %d", size, N_URB_TD); - return -1; - } - purb_priv = &urb_priv; - purb_priv->pipe = pipe; - - /* fill the private part of the URB */ - purb_priv->length = size; - purb_priv->ed = ed; - purb_priv->actual_length = 0; - - /* allocate the TDs */ - /* note that td[0] was allocated in ep_add_ed */ - for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc (dev); - if (!purb_priv->td[i]) { - purb_priv->length = i; - urb_free_priv (purb_priv); - err("sohci_submit_job: ENOMEM"); - return -1; - } - } - - if (ed->state == ED_NEW || (ed->state & ED_DEL)) { - urb_free_priv (purb_priv); - err("sohci_submit_job: EINVAL"); - return -1; - } - - /* link the ed into a chain if is not already */ - if (ed->state != ED_OPER) - ep_link (ohci, ed); - - /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -/* tell us the current USB frame number */ - -static int sohci_get_current_frame_number (struct usb_device *usb_dev) -{ - ohci_t *ohci = &gohci; - - return m16_swap (ohci->hcca->frame_no); -} -#endif - -/*-------------------------------------------------------------------------* - * ED handling functions - *-------------------------------------------------------------------------*/ - -/* link an ed into one of the HC chains */ - -static int ep_link (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->state = ED_OPER; - - switch (ed->type) { - case PIPE_CONTROL: - ed->hwNextED = 0; - if (ohci->ed_controltail == NULL) { - writel (ed, &ohci->regs->ed_controlhead); - } else { - ohci->ed_controltail->hwNextED = m32_swap (ed); - } - ed->ed_prev = ohci->ed_controltail; - if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_controltail = edi; - break; - - case PIPE_BULK: - ed->hwNextED = 0; - if (ohci->ed_bulktail == NULL) { - writel (ed, &ohci->regs->ed_bulkhead); - } else { - ohci->ed_bulktail->hwNextED = m32_swap (ed); - } - ed->ed_prev = ohci->ed_bulktail; - if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_bulktail = edi; - break; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* unlink an ed from one of the HC chains. - * just the link to the ed is unlinked. - * the link from the ed still points to another operational ed or 0 - * so the HC can eventually finish the processing of the unlinked ed */ - -static int ep_unlink (ohci_t *ohci, ed_t *ed) -{ - ed->hwINFO |= m32_swap (OHCI_ED_SKIP); - - switch (ed->type) { - case PIPE_CONTROL: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_controltail == ed) { - ohci->ed_controltail = ed->ed_prev; - } else { - ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - - case PIPE_BULK: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_bulktail == ed) { - ohci->ed_bulktail = ed->ed_prev; - } else { - ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - } - ed->state = ED_UNLINK; - return 0; -} - - -/*-------------------------------------------------------------------------*/ - -/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, - * but the USB stack is a little bit stateless so we do it at every transaction - * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK - * in all other cases the state is left unchanged - * the ed info fields are setted anyway even though most of them should not change */ - -static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) -{ - td_t *td; - ed_t *ed_ret; - volatile ed_t *ed; - - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | - (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; - - if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { - err("ep_add_ed: pending delete"); - /* pending delete request */ - return NULL; - } - - if (ed->state == ED_NEW) { - ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ - /* dummy td; end of td list for ed */ - td = td_alloc (usb_dev); - ed->hwTailP = m32_swap (td); - ed->hwHeadP = ed->hwTailP; - ed->state = ED_UNLINK; - ed->type = usb_pipetype (pipe); - ohci_dev.ed_cnt++; - } - - ed->hwINFO = m32_swap (usb_pipedevice (pipe) - | usb_pipeendpoint (pipe) << 7 - | (usb_pipeisoc (pipe)? 0x8000: 0) - | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | usb_pipeslow (pipe) << 13 - | usb_maxpacket (usb_dev, pipe) << 16); - - return ed_ret; -} - -/*-------------------------------------------------------------------------* - * TD handling functions - *-------------------------------------------------------------------------*/ - -/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ - -static void td_fill (ohci_t *ohci, unsigned int info, - void *data, int len, - struct usb_device *dev, int index, urb_priv_t *urb_priv) -{ - volatile td_t *td, *td_pt; -#ifdef OHCI_FILL_TRACE - int i; -#endif - - if (index > urb_priv->length) { - err("index > length"); - return; - } - /* use this td as the next dummy */ - td_pt = urb_priv->td [index]; - td_pt->hwNextTD = 0; - - /* fill the old dummy TD */ - td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); - - td->ed = urb_priv->ed; - td->next_dl_td = NULL; - td->index = index; - td->data = (__u32)data; -#ifdef OHCI_FILL_TRACE - if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { - for (i = 0; i < len; i++) - printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); - printf("\n"); - } -#endif - if (!len) - data = 0; - - td->hwINFO = m32_swap (info); - td->hwCBP = m32_swap (data); - if (data) - td->hwBE = m32_swap (data + len - 1); - else - td->hwBE = 0; - td->hwNextTD = m32_swap (td_pt); - td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000); - - /* append to queue */ - td->ed->hwTailP = td->hwNextTD; -} - -/*-------------------------------------------------------------------------*/ - -/* prepare all TDs of a transfer */ - -static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) -{ - ohci_t *ohci = &gohci; - int data_len = transfer_len; - void *data; - int cnt = 0; - __u32 info = 0; - unsigned int toggle = 0; - - /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ - if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { - toggle = TD_T_TOGGLE; - } else { - toggle = TD_T_DATA0; - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); - } - urb->td_cnt = 0; - if (data_len) - data = buffer; - else - data = 0; - - switch (usb_pipetype (pipe)) { - case PIPE_BULK: - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; - while(data_len > 4096) { - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); - data += 4096; data_len -= 4096; cnt++; - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); - cnt++; - - if (!ohci->sleeping) - writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ - break; - - case PIPE_CONTROL: - info = TD_CC | TD_DP_SETUP | TD_T_DATA0; - td_fill (ohci, info, setup, 8, dev, cnt++, urb); - if (data_len > 0) { - info = usb_pipeout (pipe)? - TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; - /* NOTE: mishandles transfers >8K, some >4K */ - td_fill (ohci, info, data, data_len, dev, cnt++, urb); - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; - td_fill (ohci, info, data, 0, dev, cnt++, urb); - if (!ohci->sleeping) - writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ - break; - } - if (urb->length != cnt) - dbg("TD LENGTH %d != CNT %d", urb->length, cnt); -} - -/*-------------------------------------------------------------------------* - * Done List handling functions - *-------------------------------------------------------------------------*/ - - -/* calculate the transfer length and update the urb */ - -static void dl_transfer_length(td_t * td) -{ - __u32 tdINFO, tdBE, tdCBP; - urb_priv_t *lurb_priv = &urb_priv; - - tdINFO = m32_swap (td->hwINFO); - tdBE = m32_swap (td->hwBE); - tdCBP = m32_swap (td->hwCBP); - - - if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && - ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { - if (tdBE != 0) { - if (td->hwCBP == 0) - lurb_priv->actual_length += tdBE - td->data + 1; - else - lurb_priv->actual_length += tdCBP - td->data; - } - } -} - -/*-------------------------------------------------------------------------*/ - -/* replies to the request have to be on a FIFO basis so - * we reverse the reversed done-list */ - -static td_t * dl_reverse_done_list (ohci_t *ohci) -{ - __u32 td_list_hc; - td_t *td_rev = NULL; - td_t *td_list = NULL; - urb_priv_t *lurb_priv = NULL; - - td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; - ohci->hcca->done_head = 0; - - while (td_list_hc) { - td_list = (td_t *)td_list_hc; - - if (TD_CC_GET (m32_swap (td_list->hwINFO))) { - lurb_priv = &urb_priv; - dbg(" USB-error/status: %x : %p", - TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); - if (td_list->ed->hwHeadP & m32_swap (0x1)) { - if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { - td_list->ed->hwHeadP = - (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | - (td_list->ed->hwHeadP & m32_swap (0x2)); - lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; - } else - td_list->ed->hwHeadP &= m32_swap (0xfffffff2); - } - } - - td_list->next_dl_td = td_rev; - td_rev = td_list; - td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; - } - return td_list; -} - -/*-------------------------------------------------------------------------*/ - -/* td done list */ -static int dl_done_list (ohci_t *ohci, td_t *td_list) -{ - td_t *td_list_next = NULL; - ed_t *ed; - int cc = 0; - int stat = 0; - /* urb_t *urb; */ - urb_priv_t *lurb_priv; - __u32 tdINFO, edHeadP, edTailP; - - while (td_list) { - td_list_next = td_list->next_dl_td; - - lurb_priv = &urb_priv; - tdINFO = m32_swap (td_list->hwINFO); - - ed = td_list->ed; - - dl_transfer_length(td_list); - - /* error code of transfer */ - cc = TD_CC_GET (tdINFO); - if (cc != 0) { - dbg("ConditionCode %#x", cc); - stat = cc_to_error[cc]; - } - - if (ed->state != ED_NEW) { - edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; - edTailP = m32_swap (ed->hwTailP); - - /* unlink eds if they are not busy */ - if ((edHeadP == edTailP) && (ed->state == ED_OPER)) - ep_unlink (ohci, ed); - } - - td_list = td_list_next; - } - return stat; -} - -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ - -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - -/* Hub class-specific descriptor is constructed dynamically */ - - -/*-------------------------------------------------------------------------*/ - -#define OK(x) len = (x); break -#ifdef DEBUG -#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} -#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} -#else -#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) -#endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) - -/* request to virtual root hub */ - -int rh_check_port_status(ohci_t *controller) -{ - __u32 temp, ndp, i; - int res; - - res = -1; - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); -#ifdef CONFIG_AT91C_PQFP_UHPBUG - ndp = (ndp == 2) ? 1:0; -#endif - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - /* check for a device disconnect */ - if (((temp & (RH_PS_PESC | RH_PS_CSC)) == - (RH_PS_PESC | RH_PS_CSC)) && - ((temp & RH_PS_CCS) == 0)) { - res = i; - break; - } - } - return res; -} - -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *cmd) -{ - void * data = buffer; - int leni = transfer_len; - int len = 0; - int stat = 0; - __u32 datab[4]; - __u8 *data_buf = (__u8 *)datab; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; - -#ifdef DEBUG -urb_priv.actual_length = 0; -pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { - info("Root-Hub submit IRQ: NOT implemented"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = m16_swap (cmd->value); - wIndex = m16_swap (cmd->index); - wLength = m16_swap (cmd->length); - - info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", - dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(__u16 *) data_buf = m16_swap (1); OK (2); - case RH_GET_STATUS | RH_INTERFACE: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_ENDPOINT: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_CLASS: - *(__u32 *) data_buf = m32_swap ( - RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); - OK (4); - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); - - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case RH_C_HUB_LOCAL_POWER: - OK(0); - case (RH_C_HUB_OVER_CURRENT): - WR_RH_STAT(RH_HS_OCIC); OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_POCI); OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); - case (RH_C_PORT_CONNECTION): - WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); - case (RH_C_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_PESC); OK (0); - case (RH_C_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); - case (RH_C_PORT_OVER_CURRENT): - WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); - case (RH_C_PORT_RESET): - WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); - } - break; - - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); - case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PRS); - OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); - case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PES ); - OK (0); - } - break; - - case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_dev_des), - wLength)); - data_buf = root_hub_dev_des; OK(len); - case (0x02): /* configuration descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_config_des), - wLength)); - data_buf = root_hub_config_des; OK(len); - case (0x03): /* string descriptors */ - if(wValue==0x0300) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index0), - wLength)); - data_buf = root_hub_str_index0; - OK(len); - } - if(wValue==0x0301) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index1), - wLength)); - data_buf = root_hub_str_index1; - OK(len); - } - default: - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - { - __u32 temp = roothub_a (&gohci); - - data_buf [0] = 9; /* min length; */ - data_buf [1] = 0x29; - data_buf [2] = temp & RH_A_NDP; -#ifdef CONFIG_AT91C_PQFP_UHPBUG - data_buf [2] = (data_buf [2] == 2) ? 1:0; -#endif - data_buf [3] = 0; - if (temp & RH_A_PSM) /* per-port power switching? */ - data_buf [3] |= 0x1; - if (temp & RH_A_NOCP) /* no overcurrent reporting? */ - data_buf [3] |= 0x10; - else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ - data_buf [3] |= 0x8; - - /* corresponds to data_buf[4-7] */ - datab [1] = 0; - data_buf [5] = (temp & RH_A_POTPGT) >> 24; - temp = roothub_b (&gohci); - data_buf [7] = temp & RH_B_DR; - if (data_buf [2] < 7) { - data_buf [8] = 0xff; - } else { - data_buf [0] += 2; - data_buf [8] = (temp & RH_B_DR) >> 8; - data_buf [10] = data_buf [9] = 0xff; - } - - len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf [0], wLength)); - OK (len); - } - - case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); - - case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); - - default: - dbg ("unsupported root hub command"); - stat = USB_ST_STALLED; - } - -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#else - wait_ms(1); -#endif - - len = min_t(int, len, leni); - if (data != data_buf) - memcpy (data, data_buf, len); - dev->act_len = len; - dev->status = stat; - -#ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); -#else - wait_ms(1); -#endif - - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/* common code for handling submit messages - used for all but root hub */ -/* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; - - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } - -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if (!maxsize) { - err("submit_common_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { - err("sohci_submit_job failed"); - return -1; - } - - wait_ms(10); - /* ohci_dump_status(&gohci); */ - - /* allow more time for a BULK device to react - some are slow */ -#define BULK_TO 5000 /* timeout in milliseconds */ - if (usb_pipetype (pipe) == PIPE_BULK) - timeout = BULK_TO; - else - timeout = 100; - - /* wait for it to complete */ - for (;;) { - /* check whether the controller is done */ - stat = hc_interrupt(); - if (stat < 0) { - stat = USB_ST_CRC_ERR; - break; - } - if (stat >= 0 && stat != 0xff) { - /* 0xff is returned for an SF-interrupt */ - break; - } - if (--timeout) { - wait_ms(1); - } else { - err("CTL:TIMEOUT "); - stat = USB_ST_CRC_ERR; - break; - } - } - /* we got an Root Hub Status Change interrupt */ - if (got_rhsc) { -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - got_rhsc = 0; - /* abuse timeout */ - timeout = rh_check_port_status(&gohci); - if (timeout >= 0) { -#if 0 /* this does nothing useful, but leave it here in case that changes */ - /* the called routine adds 1 to the passed value */ - usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); -#endif - /* - * XXX - * This is potentially dangerous because it assumes - * that only one device is ever plugged in! - */ - devgone = dev; - } - } - - dev->status = stat; - dev->act_len = transfer_len; - -#ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - - /* free TDs in urb_priv */ - urb_free_priv (&urb_priv); - return 0; -} - -/* submit routines called from usb.c */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) -{ - info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) -{ - int maxsize = usb_maxpacket(dev, pipe); - - info("submit_control_msg"); -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if (!maxsize) { - err("submit_control_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; - /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); - } - - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return -1; -} - -/*-------------------------------------------------------------------------* - * HC functions - *-------------------------------------------------------------------------*/ - -/* reset the HC and BUS */ - -static int hc_reset (ohci_t *ohci) -{ - int timeout = 30; - int smm_timeout = 50; /* 0,5 sec */ - - dbg("%s\n", __FUNCTION__); - - if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ - writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ - info("USB HC TakeOver from SMM"); - while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms (10); - if (--smm_timeout == 0) { - err("USB HC TakeOver failed!"); - return -1; - } - } - } - - /* Disable HC interrupts */ - writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); - - dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", - ohci->slot_name, - readl(&ohci->regs->control)); - - /* Reset USB (needed by some controllers) */ - writel (0, &ohci->regs->control); - - /* HC Reset requires max 10 us delay */ - writel (OHCI_HCR, &ohci->regs->cmdstatus); - while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { - if (--timeout == 0) { - err("USB HC reset timed out!"); - return -1; - } - udelay (1); - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* Start an OHCI controller, set the BUS operational - * enable interrupts - * connect the virtual root hub */ - -static int hc_start (ohci_t * ohci) -{ - __u32 mask; - unsigned int fminterval; - - ohci->disabled = 1; - - /* Tell the controller where the control and bulk lists are - * The lists are empty now. */ - - writel (0, &ohci->regs->ed_controlhead); - writel (0, &ohci->regs->ed_bulkhead); - - writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ - - fminterval = 0x2edf; - writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); - fminterval |= ((((fminterval - 210) * 6) / 7) << 16); - writel (fminterval, &ohci->regs->fminterval); - writel (0x628, &ohci->regs->lsthresh); - - /* start controller operations */ - ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; - ohci->disabled = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* disable all interrupts */ - mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | - OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | - OHCI_INTR_OC | OHCI_INTR_MIE); - writel (mask, &ohci->regs->intrdisable); - /* clear all interrupts */ - mask &= ~OHCI_INTR_MIE; - writel (mask, &ohci->regs->intrstatus); - /* Choose the interrupts we care about now - but w/o MIE */ - mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; - writel (mask, &ohci->regs->intrenable); - -#ifdef OHCI_USE_NPS - /* required for AMD-756 and some Mac platforms */ - writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, - &ohci->regs->roothub.a); - writel (RH_HS_LPSC, &ohci->regs->roothub.status); -#endif /* OHCI_USE_NPS */ - -#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay ((roothub_a (ohci) >> 23) & 0x1fe); - - /* connect the virtual root hub */ - ohci->rh.devnum = 0; - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* an interrupt happens */ - -static int -hc_interrupt (void) -{ - ohci_t *ohci = &gohci; - struct ohci_regs *regs = ohci->regs; - int ints; - int stat = -1; - - if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) { - ints = OHCI_INTR_WDH; - } else { - ints = readl (®s->intrstatus); - } - - /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ - - if (ints & OHCI_INTR_RHSC) { - got_rhsc = 1; - } - - if (ints & OHCI_INTR_UE) { - ohci->disabled++; - err ("OHCI Unrecoverable Error, controller usb-%s disabled", - ohci->slot_name); - /* e.g. due to PCI Master/Target Abort */ - -#ifdef DEBUG - ohci_dump (ohci, 1); -#else - wait_ms(1); -#endif - /* FIXME: be optimistic, hope that bug won't repeat often. */ - /* Make some non-interrupt context restart the controller. */ - /* Count and limit the retries though; either hardware or */ - /* software errors can go forever... */ - hc_reset (ohci); - return -1; - } - - if (ints & OHCI_INTR_WDH) { - wait_ms(1); - writel (OHCI_INTR_WDH, ®s->intrdisable); - stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); - writel (OHCI_INTR_WDH, ®s->intrenable); - } - - if (ints & OHCI_INTR_SO) { - dbg("USB Schedule overrun\n"); - writel (OHCI_INTR_SO, ®s->intrenable); - stat = -1; - } - - /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ - if (ints & OHCI_INTR_SF) { - unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; - wait_ms(1); - writel (OHCI_INTR_SF, ®s->intrdisable); - if (ohci->ed_rm_list[frame] != NULL) - writel (OHCI_INTR_SF, ®s->intrenable); - stat = 0xff; - } - - writel (ints, ®s->intrstatus); - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -/* De-allocate all resources.. */ - -static void hc_release_ohci (ohci_t *ohci) -{ - dbg ("USB HC release ohci usb-%s", ohci->slot_name); - - if (!ohci->disabled) - hc_reset (ohci); -} - -/*-------------------------------------------------------------------------*/ - -/* - * low level initalisation routine, called from usb.c - */ -static char ohci_inited = 0; - -int usb_lowlevel_init(void) -{ - /* - * Enable USB host clock. - */ - *AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */ - *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable Register */ - - memset (&gohci, 0, sizeof (ohci_t)); - memset (&urb_priv, 0, sizeof (urb_priv_t)); - - /* align the storage */ - if ((__u32)&ghcca[0] & 0xff) { - err("HCCA not aligned!!"); - return -1; - } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32)&ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); - if ((__u32)gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset (phcca, 0, sizeof (struct ohci_hcca)); - - gohci.disabled = 1; - gohci.sleeping = 0; - gohci.irq = -1; - gohci.regs = (struct ohci_regs *)AT91_USB_HOST_BASE; - - gohci.flags = 0; - gohci.slot_name = "at91rm9200"; - - if (hc_reset (&gohci) < 0) { - hc_release_ohci (&gohci); - /* Initialization failed */ - *AT91C_PMC_PCER = AT91C_ID_UHP; - *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ - return -1; - } - - /* FIXME this is a second HC reset; why?? */ -/* writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); - wait_ms (10);*/ - - if (hc_start (&gohci) < 0) { - err ("can't start usb-%s", gohci.slot_name); - hc_release_ohci (&gohci); - /* Initialization failed */ - *AT91C_PMC_PCER = AT91C_ID_UHP; - *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ - return -1; - } - -#ifdef DEBUG - ohci_dump (&gohci, 1); -#else - wait_ms(1); -#endif - ohci_inited = 1; - return 0; -} - -int usb_lowlevel_stop(void) -{ - /* this gets called really early - before the controller has */ - /* even been initialized! */ - if (!ohci_inited) - return 0; - /* TODO release any interrupts, etc. */ - /* call hc_release_ohci() here ? */ - hc_reset (&gohci); - /* may not want to do this */ - *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; - *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ - return 0; -} - -#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/arm920t/at91rm9200/usb_ohci.h b/cpu/arm920t/at91rm9200/usb_ohci.h deleted file mode 100644 index ecb4e93..0000000 --- a/cpu/arm920t/at91rm9200/usb_ohci.h +++ /dev/null @@ -1,419 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB. - * - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2001 David Brownell - * - * usb-ohci.h - */ - - -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -/* ED States */ - -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 -#define ED_OPER 0x02 -#define ED_DEL 0x04 -#define ED_URB_DEL 0x08 - -/* usb_ohci_ed */ -struct ed { - __u32 hwINFO; - __u32 hwTailP; - __u32 hwHeadP; - __u32 hwNextED; - - struct ed *ed_prev; - __u8 int_period; - __u8 int_branch; - __u8 int_load; - __u8 int_interval; - __u8 state; - __u8 type; - __u16 last_iso; - struct ed *ed_rm_list; - - struct usb_device *usb_dev; - __u32 unused[3]; -} __attribute((aligned(16))); -typedef struct ed ed_t; - - -/* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 - -/* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F - - -#define MAXPSW 1 - -struct td { - __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u16 hwPSW[MAXPSW]; - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; - struct usb_device *usb_dev; - int transfer_len; - __u32 data; - - __u32 unused2[2]; -} __attribute((aligned(32))); -typedef struct td td_t; - -#define OHCI_ED_SKIP (1 << 14) - -/* - * The HCCA (Host Controller Communications Area) is a 256 byte - * structure defined in the OHCI spec. that the host controller is - * told the base address of. It must be 256-byte aligned. - */ - -#define NUM_INTS 32 /* part of the OHCI standard */ -struct ohci_hcca { - __u32 int_table[NUM_INTS]; /* Interrupt ED table */ - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ - __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; -} __attribute((aligned(256))); - - -/* - * Maximum number of root hub ports. - */ -#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ - -/* - * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and - * writel() macros defined in asm/io.h to access these!! - */ -struct ohci_regs { - /* control and status registers */ - __u32 revision; - __u32 control; - __u32 cmdstatus; - __u32 intrstatus; - __u32 intrenable; - __u32 intrdisable; - /* memory pointers */ - __u32 hcca; - __u32 ed_periodcurrent; - __u32 ed_controlhead; - __u32 ed_controlcurrent; - __u32 ed_bulkhead; - __u32 ed_bulkcurrent; - __u32 donehead; - /* frame counters */ - __u32 fminterval; - __u32 fmremaining; - __u32 fmnumber; - __u32 periodicstart; - __u32 lsthresh; - /* Root hub ports */ - struct ohci_roothub_regs { - __u32 a; - __u32 b; - __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; - } roothub; -} __attribute((aligned(32))); - - -/* OHCI CONTROL AND STATUS REGISTER MASKS */ - -/* - * HcControl (control) register masks - */ -#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ -#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ - -/* pre-shifted values for HCFS */ -# define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) -# define OHCI_USB_OPER (2 << 6) -# define OHCI_USB_SUSPEND (3 << 6) - -/* - * HcCommandStatus (cmdstatus) register masks - */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ - -/* - * masks used with interrupt registers: - * HcInterruptStatus (intrstatus) - * HcInterruptEnable (intrenable) - * HcInterruptDisable (intrdisable) - */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ - - -/* Virtual Root HUB */ -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - void *dev; /* was urb */ - void *int_addr; - int send; - int interval; -}; - -/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ - -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* OHCI ROOT HUB REGISTER MASKS */ - -/* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ - -/* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ - -/* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ - -/* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ - -/* urb */ -#define N_URB_TD 48 -typedef struct -{ - ed_t *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ - int state; - unsigned long pipe; - int actual_length; - td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ -} urb_priv_t; -#define URB_DEL 1 - -/* - * This is the full ohci controller description - * - * Note how the "proper" USB information is just - * a subset of what the full implementation needs. (Linus) - */ - - -typedef struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma;*/ - - int irq; - int disabled; /* e.g. got a UE, we're hung */ - int sleeping; - unsigned long flags; /* for HC bugs */ - - struct ohci_regs *regs; /* OHCI controller's memory */ - - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ - int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ - struct usb_device *dev[32]; - struct virt_root_hub rh; - - const char *slot_name; -} ohci_t; - -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - ed_t ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(ohci_t * ohci, ed_t * ed); -static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -td_t gtd[NUM_TD+1]; -/* pointers to aligned storage */ -td_t *ptd; - -/* TDs ... */ -static inline struct td * -td_alloc (struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) - { - if (ptd[i].usb_dev == NULL) - { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - - return td; -} - -static inline void -ed_free (struct ed *ed) -{ - ed->usb_dev = NULL; -} diff --git a/cpu/arm920t/config.mk b/cpu/arm920t/config.mk deleted file mode 100644 index 8db4adb..0000000 --- a/cpu/arm920t/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c deleted file mode 100644 index 2f7963d..0000000 --- a/cpu/arm920t/cpu.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include -#include - -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM920T Technical reference Manual */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ - -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - DECLARE_GLOBAL_DATA_PTR; - - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - unsigned long i; - - disable_interrupts (); - - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} - -#ifdef USE_920T_MMU -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_DC); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - reg &= ~C1_DC; - write_p15_c1 (reg); -} - -int dcache_status (void) -{ - return (read_p15_c1 () & C1_DC) != 0; -} -#endif diff --git a/cpu/arm920t/imx/Makefile b/cpu/arm920t/imx/Makefile deleted file mode 100644 index 8865f82..0000000 --- a/cpu/arm920t/imx/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(SOC).a - -OBJS = generic.o interrupts.o serial.o speed.o - -all: .depend $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/arm920t/imx/generic.c b/cpu/arm920t/imx/generic.c deleted file mode 100644 index aa7c8c1..0000000 --- a/cpu/arm920t/imx/generic.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * arch/arm/mach-imx/generic.c - * - * author: Sascha Hauer - * Created: april 20th, 2004 - * Copyright: Synertronixx GmbH - * - * Common code for i.MX machines - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include - -#ifdef CONFIG_IMX - -#include - -void imx_gpio_mode(int gpio_mode) -{ - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10; - unsigned int tmp; - - /* Pullup enable */ - if(gpio_mode & GPIO_PUEN) - PUEN(port) |= (1< - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined (CONFIG_IMX) - -#include -#include - -int interrupt_init (void) -{ - int i; - /* setup GP Timer 1 */ - TCTL1 = TCTL_SWR; - for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */ - TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */ - TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */ - - reset_timer_masked(); - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked (); -} - -void set_timer (ulong t) -{ - /* nop */ -} - -void reset_timer_masked (void) -{ - TCTL1 &= ~TCTL_TEN; - TCTL1 |= TCTL_TEN; /* Enable timer */ -} - -ulong get_timer_masked (void) -{ - return TCN1; -} - -void udelay_masked (unsigned long usec) -{ - ulong endtime = get_timer_masked() + usec; - signed long diff; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -void udelay (unsigned long usec) -{ - udelay_masked(usec); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = CFG_HZ; - - return tbclk; -} - -/* - * Reset the cpu by setting up the watchdog timer and let him time out - */ -void reset_cpu (ulong ignored) -{ - /* Disable watchdog and set Time-Out field to 0 */ - WCR = 0x00000000; - - /* Write Service Sequence */ - WSR = 0x00005555; - WSR = 0x0000AAAA; - - /* Enable watchdog */ - WCR = 0x00000001; - - while (1); - /*NOTREACHED*/ -} - -#endif /* defined (CONFIG_IMX) */ diff --git a/cpu/arm920t/imx/serial.c b/cpu/arm920t/imx/serial.c deleted file mode 100644 index 9dbaa56..0000000 --- a/cpu/arm920t/imx/serial.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * (c) 2004 Sascha Hauer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#if defined (CONFIG_IMX) - -#include - -#ifndef CONFIG_IMX_SERIAL_NONE - -#if defined CONFIG_IMX_SERIAL1 -#define UART_BASE IMX_UART1_BASE -#elif defined CONFIG_IMX_SERIAL2 -#define UART_BASE IMX_UART2_BASE -#else -#error "define CONFIG_IMX_SERIAL1, CONFIG_IMX_SERIAL2 or CONFIG_IMX_SERIAL_NONE" -#endif - -struct imx_serial { - volatile uint32_t urxd[16]; - volatile uint32_t utxd[16]; - volatile uint32_t ucr1; - volatile uint32_t ucr2; - volatile uint32_t ucr3; - volatile uint32_t ucr4; - volatile uint32_t ufcr; - volatile uint32_t usr1; - volatile uint32_t usr2; - volatile uint32_t uesc; - volatile uint32_t utim; - volatile uint32_t ubir; - volatile uint32_t ubmr; - volatile uint32_t ubrc; - volatile uint32_t bipr[4]; - volatile uint32_t bmpr[4]; - volatile uint32_t uts; -}; - -void serial_setbrg (void) -{ - serial_init(); -} - -extern void imx_gpio_mode(int gpio_mode); - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; -#ifdef CONFIG_IMX_SERIAL1 - imx_gpio_mode(PC11_PF_UART1_TXD); - imx_gpio_mode(PC12_PF_UART1_RXD); -#else - imx_gpio_mode(PB30_PF_UART2_TXD); - imx_gpio_mode(PB31_PF_UART2_RXD); -#endif - - /* Disable UART */ - base->ucr1 &= ~UCR1_UARTEN; - - /* Set to default POR state */ - - base->ucr1 = 0x00000004; - base->ucr2 = 0x00000000; - base->ucr3 = 0x00000000; - base->ucr4 = 0x00008040; - base->uesc = 0x0000002B; - base->utim = 0x00000000; - base->ubir = 0x00000000; - base->ubmr = 0x00000000; - base->uts = 0x00000000; - /* Set clocks */ - base->ucr4 |= UCR4_REF16; - - /* Configure FIFOs */ - base->ufcr = 0xa81; - - /* Set the numerator value minus one of the BRM ratio */ - base->ubir = (CONFIG_BAUDRATE / 100) - 1; - - /* Set the denominator value minus one of the BRM ratio */ - base->ubmr = 10000 - 1; - - /* Set to 8N1 */ - base->ucr2 &= ~UCR2_PREN; - base->ucr2 |= UCR2_WS; - base->ucr2 &= ~UCR2_STPB; - - /* Ignore RTS */ - base->ucr2 |= UCR2_IRTS; - - /* Enable UART */ - base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN; - - /* Enable FIFOs */ - base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN; - - /* Clear status flags */ - base->usr2 |= USR2_ADET | - USR2_DTRF | - USR2_IDLE | - USR2_IRINT | - USR2_WAKE | - USR2_RTSF | - USR2_BRCD | - USR2_ORE | - USR2_RDR; - - /* Clear status flags */ - base->usr1 |= USR1_PARITYERR | - USR1_RTSD | - USR1_ESCF | - USR1_FRAMERR | - USR1_AIRINT | - USR1_AWAKE; - return (0); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is successful, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; - unsigned char ch; - - while(base->uts & UTS_RXEMPTY); - - ch = (char)base->urxd[0]; - - return ch; -} - -#ifdef CONFIG_HWFLOW -static int hwflow = 0; /* turned off by default */ -int hwflow_onoff(int on) -{ -} -#endif - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; - - /* Wait for Tx FIFO not full */ - while (base->uts & UTS_TXFULL); - - base->utxd[0] = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc (void) -{ - volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; - - /* If receive fifo is empty, return false */ - if (base->uts & UTS_RXEMPTY) - return 0; - return 1; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} -#endif /* CONFIG_IMX_SERIAL_NONE */ -#endif /* defined CONFIG_IMX */ diff --git a/cpu/arm920t/imx/speed.c b/cpu/arm920t/imx/speed.c deleted file mode 100644 index 1e29698..0000000 --- a/cpu/arm920t/imx/speed.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * - * (c) 2004 Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#if defined (CONFIG_IMX) - -#include - -/* ------------------------------------------------------------------------- */ -/* NOTE: This describes the proper use of this file. - * - * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. - * SH FIXME: 16780000 in our case - * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of - * the specified bus in HZ. - */ -/* ------------------------------------------------------------------------- */ - -ulong get_systemPLLCLK(void) -{ - /* FIXME: We assume System_SEL = 0 here */ - u32 spctl0 = SPCTL0; - u32 mfi = (spctl0 >> 10) & 0xf; - u32 mfn = spctl0 & 0x3f; - u32 mfd = (spctl0 >> 16) & 0x3f; - u32 pd = (spctl0 >> 26) & 0xf; - - mfi = mfi<=5 ? 5 : mfi; - - return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); -} - -ulong get_mcuPLLCLK(void) -{ - /* FIXME: We assume System_SEL = 0 here */ - u32 mpctl0 = MPCTL0; - u32 mfi = (mpctl0 >> 10) & 0xf; - u32 mfn = mpctl0 & 0x3f; - u32 mfd = (mpctl0 >> 16) & 0x3f; - u32 pd = (mpctl0 >> 26) & 0xf; - - mfi = mfi<=5 ? 5 : mfi; - - return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); -} - -ulong get_FCLK(void) -{ - return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK(); -} - -/* return HCLK frequency */ -ulong get_HCLK(void) -{ - u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; - printf("bclkdiv: %d\n", bclkdiv); - return get_systemPLLCLK() / bclkdiv; -} - -/* return BCLK frequency */ -ulong get_BCLK(void) -{ - return get_HCLK(); -} - -ulong get_PERCLK1(void) -{ - return get_systemPLLCLK() / (((PCDR) & 0xf)+1); -} - -ulong get_PERCLK2(void) -{ - return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1); -} - -ulong get_PERCLK3(void) -{ - return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1); -} - -#endif /* defined (CONFIG_IMX) */ diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c deleted file mode 100644 index a43a3ed..0000000 --- a/cpu/arm920t/interrupts.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_USE_IRQ -/* enable IRQ interrupts */ -void enable_interrupts (void) -{ - unsigned long temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); -} - - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ - unsigned long old,temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); - return (old & 0x80) == 0; -} -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32", - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ -#if defined (CONFIG_USE_IRQ) && defined (CONFIG_ARCH_INTEGRATOR) - /* ASSUMED to be a timer interrupt */ - /* Just clear it - count handled in */ - /* integratorap.c */ - *(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0; -#else - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -#endif -} diff --git a/cpu/arm920t/ks8695/Makefile b/cpu/arm920t/ks8695/Makefile deleted file mode 100644 index ac49060..0000000 --- a/cpu/arm920t/ks8695/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2005 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(SOC).a - -OBJS = interrupts.o serial.o -SOBJS = lowlevel_init.o - -all: .depend $(LIB) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/arm920t/ks8695/interrupts.c b/cpu/arm920t/ks8695/interrupts.c deleted file mode 100644 index 883d689..0000000 --- a/cpu/arm920t/ks8695/interrupts.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2004-2005, Greg Ungerer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* - * Handy KS8695 register access functions. - */ -#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a))) -#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v) - -int timer_inited; -ulong timer_ticks; - -int interrupt_init (void) -{ - /* nothing happens here - we don't setup any IRQs */ - return (0); -} - -/* - * Initial timer set constants. Nothing complicated, just set for a 1ms - * tick. - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1) -#define TIMER_COUNT (TIMER_INTERVAL / 2) -#define TIMER_PULSE TIMER_COUNT - -void reset_timer_masked(void) -{ - /* Set the hadware timer for 1ms */ - ks8695_write(KS8695_TIMER1, TIMER_COUNT); - ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE); - ks8695_write(KS8695_TIMER_CTRL, 0x2); - timer_ticks = 0; - timer_inited++; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - -ulong get_timer_masked(void) -{ - /* Check for timer wrap */ - if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) { - /* Clear interrupt condition */ - ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1); - timer_ticks++; - } - return timer_ticks; -} - -ulong get_timer(ulong base) -{ - return (get_timer_masked() - base); -} - -void set_timer(ulong t) -{ - timer_ticks = t; -} - -void udelay(ulong usec) -{ - ulong start = get_timer_masked(); - ulong end; - - if (!timer_inited) - reset_timer(); - - /* Only 1ms resolution :-( */ - end = usec / 1000; - while (get_timer(start) < end) - ; -} - -void reset_cpu (ulong ignored) -{ - ulong tc; - - /* Set timer0 to watchdog, and let it timeout */ - tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2; - ks8695_write(KS8695_TIMER_CTRL, tc); - ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff)); - ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1)); - - /* Should only wait here till watchdog resets */ - for (;;) - ; -} diff --git a/cpu/arm920t/ks8695/lowlevel_init.S b/cpu/arm920t/ks8695/lowlevel_init.S deleted file mode 100644 index e9f1227..0000000 --- a/cpu/arm920t/ks8695/lowlevel_init.S +++ /dev/null @@ -1,205 +0,0 @@ -/* - * lowlevel_init.S - basic hardware initialization for the KS8695 CPU - * - * Copyright (c) 2004-2005, Greg Ungerer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - -/* - ************************************************************************* - * - * Handy dandy macros - * - ************************************************************************* - */ - -/* Delay a bit */ -.macro DELAY_FOR cycles, reg0 - ldr \reg0, =\cycles - subs \reg0, \reg0, #1 - subne pc, pc, #0xc -.endm - -/* - ************************************************************************* - * - * Some local storage. - * - ************************************************************************* - */ - -/* Should we boot with an interactive console or not */ -.globl serial_console - -/* - ************************************************************************* - * - * Raw hardware initialization code. The important thing is to get - * SDRAM setup and running. We do some other basic things here too, - * like getting the PLL set for high speed, and init the LEDs. - * - ************************************************************************* - */ - -.globl lowlevel_init -lowlevel_init: - -#if DEBUG - /* - * enable UART for early debug trace - */ - ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR) - mov r2, #0xd9 - str r2, [r1] /* 115200 baud */ - ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL) - mov r2, #0x03 - str r2, [r1] /* 8 data bits, no parity, 1 stop */ - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) - mov r2, #0x41 - str r2, [r1] /* write 'A' */ -#endif -#if DEBUG - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) - mov r2, #0x42 - str r2, [r1] -#endif - - /* - * remap the memory and flash regions. we want to end up with - * ram from address 0, and flash at 32MB. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0) - ldr r2, =0xbfc00040 - str r2, [r1] /* large flash map */ - ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */ -highflash: - ldr r2, =0x8fe00040 - str r2, [r1] /* remap flash range */ - - /* - * remap the second select region to the 4MB immediately after - * the first region. This way if you have a larger flash (say 8Mb) - * then you can have it all mapped nicely. Has no effect if you - * only have a 4Mb or smaller flash. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1) - ldr r2, =0x9fe40040 - str r2, [r1] /* remap flash2 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) - ldr r2, =0x30000005 - str r2, [r1] /* enable both flash selects */ - -#ifdef CONFIG_CM41xx - /* - * map the second flash chip, using the external IO lines. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0) - ldr r2, =0xafe80b6d - str r2, [r1] /* remap io0 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1) - ldr r2, =0xbfec0b6d - str r2, [r1] /* remap io1 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) - ldr r2, =0x30050005 - str r2, [r1] /* enable second flash */ -#endif - - /* - * before relocating, we have to setup RAM timing - */ - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0) -#if (PHYS_SDRAM_1_SIZE == 0x02000000) - ldr r2, =0x7fc0000e /* 32MB */ -#else - ldr r2, =0x3fc0000e /* 16MB */ -#endif - str r2, [r1] /* configure sdram bank0 setup */ - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1) - mov r2, #0 - str r2, [r1] /* configure sdram bank1 setup */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL) - ldr r2, =0x0000000a - str r2, [r1] /* set RAS/CAS timing */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) - ldr r2, =0x00030000 - str r2, [r1] /* send NOP command */ - DELAY_FOR 0x100, r0 - ldr r2, =0x00010000 - str r2, [r1] /* send PRECHARGE-ALL */ - DELAY_FOR 0x100, r0 - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH) - ldr r2, =0x00000020 - str r2, [r1] /* set for fast refresh */ - DELAY_FOR 0x100, r0 - ldr r2, =0x00000190 - str r2, [r1] /* set normal refresh timing */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) - ldr r2, =0x00020033 - str r2, [r1] /* send mode command */ - DELAY_FOR 0x100, r0 - ldr r2, =0x01f00000 - str r2, [r1] /* enable sdram fifos */ - - /* - * set pll to top speed - */ - ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK) - mov r2, #0 - str r2, [r1] /* set pll clock to 166MHz */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0) - ldr r2, [r1] /* Get switch ctrl0 register */ - and r2, r2, #0x0fc00000 /* Mask out LED control bits */ - orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */ - str r2, [r1] - -#ifdef CONFIG_CM4008 - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE) - ldr r2, =0x0000fe30 - str r2, [r1] /* enable LED's as outputs */ - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA) - ldr r2, =0x0000fe20 - str r2, [r1] /* turn on power LED */ -#endif -#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx) - ldr r2, [r1] /* get current GPIO input data */ - tst r2, #0x8 /* check if "erase" depressed */ - beq nobutton - mov r2, #0 /* be quiet on boot, no console */ - ldr r1, =serial_console - str r2, [r1] -nobutton: -#endif - - add lr, lr, #0x02000000 /* flash is now mapped high */ - add ip, ip, #0x02000000 /* this is a hack */ - mov pc, lr /* all done, return */ - -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/cpu/arm920t/ks8695/serial.c b/cpu/arm920t/ks8695/serial.c deleted file mode 100644 index 0dd91e7..0000000 --- a/cpu/arm920t/ks8695/serial.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * serial.c -- KS8695 serial driver - * - * (C) Copyright 2004, Greg Ungerer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include - -#ifndef CONFIG_SERIAL1 -#error "Bad: you didn't configure serial ..." -#endif - -/* - * Define the UART hardware register access structure. - */ -struct ks8695uart { - unsigned int RX; /* 0x00 - Receive data (r) */ - unsigned int TX; /* 0x04 - Transmit data (w) */ - unsigned int FCR; /* 0x08 - Fifo Control (r/w) */ - unsigned int LCR; /* 0x0c - Line Control (r/w) */ - unsigned int MCR; /* 0x10 - Modem Control (r/w) */ - unsigned int LSR; /* 0x14 - Line Status (r/w) */ - unsigned int MSR; /* 0x18 - Modem Status (r/w) */ - unsigned int BD; /* 0x1c - Baud Rate (r/w) */ - unsigned int SR; /* 0x20 - Status (r/w) */ -}; - -#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER)) -#define KS8695_UART_CLK 25000000 - - -/* - * Under some circumstances we want to be "quiet" and not issue any - * serial output - though we want u-boot to otherwise work and behave - * the same. By default be noisy. - */ -int serial_console = 1; - - -void serial_setbrg(void) -{ - DECLARE_GLOBAL_DATA_PTR; - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - - /* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/ - uartp->BD = KS8695_UART_CLK / gd->baudrate; - uartp->LCR = KS8695_UART_LINEC_WLEN8; -} - -int serial_init(void) -{ - serial_console = 1; - serial_setbrg(); - return 0; -} - -void serial_raw_putc(const char c) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - int i; - - for (i = 0; (i < 0x100000); i++) { - if (uartp->LSR & KS8695_UART_LINES_TXFE) - break; - } - - uartp->TX = c; -} - -void serial_putc(const char c) -{ - if (serial_console) { - serial_raw_putc(c); - if (c == '\n') - serial_raw_putc('\r'); - } -} - -int serial_tstc(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - if (serial_console) - return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0); - return 0; -} - -void serial_puts(const char *s) -{ - char c; - while ((c = *s++) != 0) - serial_putc(c); -} - -int serial_getc(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - - while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0) - ; - return (uartp->RX); -} diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile deleted file mode 100644 index af9e4ef..0000000 --- a/cpu/arm920t/s3c24x0/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(SOC).a - -OBJS = i2c.o interrupts.o serial.o speed.o \ - usb_ohci.o - -all: .depend $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/arm920t/s3c24x0/i2c.c b/cpu/arm920t/s3c24x0/i2c.c deleted file mode 100644 index ef56cd1..0000000 --- a/cpu/arm920t/s3c24x0/i2c.c +++ /dev/null @@ -1,447 +0,0 @@ -/* - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This code should work for both the S3C2400 and the S3C2410 - * as they seem to have the same I2C controller inside. - * The different address mapping is handled by the s3c24xx.h files below. - */ - -#include - -#ifdef CONFIG_DRIVER_S3C24X0_I2C - -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif -#include - -#ifdef CONFIG_HARD_I2C - -#define I2C_WRITE 0 -#define I2C_READ 1 - -#define I2C_OK 0 -#define I2C_NOK 1 -#define I2C_NACK 2 -#define I2C_NOK_LA 3 /* Lost arbitration */ -#define I2C_NOK_TOUT 4 /* time out */ - -#define I2CSTAT_BSY 0x20 /* Busy bit */ -#define I2CSTAT_NACK 0x01 /* Nack bit */ -#define I2CCON_IRPND 0x10 /* Interrupt pending bit */ -#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ -#define I2C_MODE_MR 0x80 /* Master Receive Mode */ -#define I2C_START_STOP 0x20 /* START / STOP */ -#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ - -#define I2C_TIMEOUT 1 /* 1 second */ - - -static int GetI2CSDA(void) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - -#ifdef CONFIG_S3C2410 - return (gpio->GPEDAT & 0x8000) >> 15; -#endif -#ifdef CONFIG_S3C2400 - return (gpio->PGDAT & 0x0020) >> 5; -#endif -} - -#if 0 -static void SetI2CSDA(int x) -{ - rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15; -} -#endif - -static void SetI2CSCL(int x) -{ - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - -#ifdef CONFIG_S3C2410 - gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14; -#endif -#ifdef CONFIG_S3C2400 - gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6; -#endif -} - - -static int WaitForXfer (void) -{ - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - int i, status; - - i = I2C_TIMEOUT * 10000; - status = i2c->IICCON; - while ((i > 0) && !(status & I2CCON_IRPND)) { - udelay (100); - status = i2c->IICCON; - i--; - } - - return (status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; -} - -static int IsACK (void) -{ - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - - return (!(i2c->IICSTAT & I2CSTAT_NACK)); -} - -static void ReadWriteByte (void) -{ - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - - i2c->IICCON &= ~I2CCON_IRPND; -} - -void i2c_init (int speed, int slaveadd) -{ - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - S3C24X0_GPIO *const gpio = S3C24X0_GetBase_GPIO (); - ulong freq, pres = 16, div; - int i, status; - - /* wait for some time to give previous transfer a chance to finish */ - - i = I2C_TIMEOUT * 1000; - status = i2c->IICSTAT; - while ((i > 0) && (status & I2CSTAT_BSY)) { - udelay (1000); - status = i2c->IICSTAT; - i--; - } - - if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) { -#ifdef CONFIG_S3C2410 - ulong old_gpecon = gpio->GPECON; -#endif -#ifdef CONFIG_S3C2400 - ulong old_gpecon = gpio->PGCON; -#endif - /* bus still busy probably by (most) previously interrupted transfer */ - -#ifdef CONFIG_S3C2410 - /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ - gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000; -#endif -#ifdef CONFIG_S3C2400 - /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ - gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00000c00; -#endif - - /* toggle I2CSCL until bus idle */ - SetI2CSCL (0); - udelay (1000); - i = 10; - while ((i > 0) && (GetI2CSDA () != 1)) { - SetI2CSCL (1); - udelay (1000); - SetI2CSCL (0); - udelay (1000); - i--; - } - SetI2CSCL (1); - udelay (1000); - - /* restore pin functions */ -#ifdef CONFIG_S3C2410 - gpio->GPECON = old_gpecon; -#endif -#ifdef CONFIG_S3C2400 - gpio->PGCON = old_gpecon; -#endif - } - - /* calculate prescaler and divisor values */ - freq = get_PCLK (); - if ((freq / pres / (16 + 1)) > speed) - /* set prescaler to 512 */ - pres = 512; - - div = 0; - while ((freq / pres / (div + 1)) > speed) - div++; - - /* set prescaler, divisor according to freq, also set - * ACKGEN, IRQ */ - i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0); - - /* init to SLAVE REVEIVE and set slaveaddr */ - i2c->IICSTAT = 0; - i2c->IICADD = slaveadd; - /* program Master Transmit (and implicit STOP) */ - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; - -} - -/* - * cmd_type is 0 for write, 1 for read. - * - * addr_len can take any value from 0-255, it is only limited - * by the char, we could make it larger if needed. If it is - * 0 we skip the address write cycle. - */ -static -int i2c_transfer (unsigned char cmd_type, - unsigned char chip, - unsigned char addr[], - unsigned char addr_len, - unsigned char data[], unsigned short data_len) -{ - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - int i, status, result; - - if (data == 0 || data_len == 0) { - /*Don't support data transfer of no length or to address 0 */ - printf ("i2c_transfer: bad call\n"); - return I2C_NOK; - } - - /* Check I2C bus idle */ - i = I2C_TIMEOUT * 1000; - status = i2c->IICSTAT; - while ((i > 0) && (status & I2CSTAT_BSY)) { - udelay (1000); - status = i2c->IICSTAT; - i--; - } - - if (status & I2CSTAT_BSY) - return I2C_NOK_TOUT; - - i2c->IICCON |= 0x80; - result = I2C_OK; - - switch (cmd_type) { - case I2C_WRITE: - if (addr && addr_len) { - i2c->IICDS = chip; - /* send START */ - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; - i = 0; - while ((i < addr_len) && (result == I2C_OK)) { - result = WaitForXfer (); - i2c->IICDS = addr[i]; - ReadWriteByte (); - i++; - } - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - result = WaitForXfer (); - i2c->IICDS = data[i]; - ReadWriteByte (); - i++; - } - } else { - i2c->IICDS = chip; - /* send START */ - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; - i = 0; - while ((i < data_len) && (result = I2C_OK)) { - result = WaitForXfer (); - i2c->IICDS = data[i]; - ReadWriteByte (); - i++; - } - } - - if (result == I2C_OK) - result = WaitForXfer (); - - /* send STOP */ - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; - ReadWriteByte (); - break; - - case I2C_READ: - if (addr && addr_len) { - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; - i2c->IICDS = chip; - /* send START */ - i2c->IICSTAT |= I2C_START_STOP; - result = WaitForXfer (); - if (IsACK ()) { - i = 0; - while ((i < addr_len) && (result == I2C_OK)) { - i2c->IICDS = addr[i]; - ReadWriteByte (); - result = WaitForXfer (); - i++; - } - - i2c->IICDS = chip; - /* resend START */ - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA | - I2C_START_STOP; - ReadWriteByte (); - result = WaitForXfer (); - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - /* disable ACK for final READ */ - if (i == data_len - 1) - i2c->IICCON &= ~0x80; - ReadWriteByte (); - result = WaitForXfer (); - data[i] = i2c->IICDS; - i++; - } - } else { - result = I2C_NACK; - } - - } else { - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; - i2c->IICDS = chip; - /* send START */ - i2c->IICSTAT |= I2C_START_STOP; - result = WaitForXfer (); - - if (IsACK ()) { - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - /* disable ACK for final READ */ - if (i == data_len - 1) - i2c->IICCON &= ~0x80; - ReadWriteByte (); - result = WaitForXfer (); - data[i] = i2c->IICDS; - i++; - } - } else { - result = I2C_NACK; - } - } - - /* send STOP */ - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; - ReadWriteByte (); - break; - - default: - printf ("i2c_transfer: bad call\n"); - result = I2C_NOK; - break; - } - - return (result); -} - -int i2c_probe (uchar chip) -{ - uchar buf[1]; - - buf[0] = 0; - - /* - * What is needed is to send the chip address and verify that the - * address was ed (i.e. there was a chip at that address which - * drove the data line low). - */ - return (i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK); -} - -int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - uchar xaddr[4]; - int ret; - - if (alen > 4) { - printf ("I2C read: addr len %d not supported\n", alen); - return 1; - } - - if (alen > 0) { - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - } - -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if (alen > 0) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); -#endif - if ((ret = - i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen, - buffer, len)) != 0) { - printf ("I2c read: failed %d\n", ret); - return 1; - } - return 0; -} - -int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - uchar xaddr[4]; - - if (alen > 4) { - printf ("I2C write: addr len %d not supported\n", alen); - return 1; - } - - if (alen > 0) { - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - } -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if (alen > 0) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); -#endif - return (i2c_transfer - (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, - len) != 0); -} -#endif /* CONFIG_HARD_I2C */ - -#endif /* CONFIG_DRIVER_S3C24X0_I2C */ diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c deleted file mode 100644 index 3ec9b54..0000000 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) - -#include -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif - -int timer_load_val = 0; - -/* macro to read the 16 bit timer */ -static inline ulong READ_TIMER(void) -{ - S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); - - return (timers->TCNTO4 & 0xffff); -} - -static ulong timestamp; -static ulong lastdec; - -int interrupt_init (void) -{ - S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); - - /* use PWM Timer 4 because it has no output */ - /* prescaler for Timer 4 is 16 */ - timers->TCFG0 = 0x0f00; - if (timer_load_val == 0) - { - /* - * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 - * (default) and prescaler = 16. Should be 10390 - * @33.25MHz and 15625 @ 50 MHz - */ - timer_load_val = get_PCLK()/(2 * 16 * 100); - } - /* load value for 10 ms timeout */ - lastdec = timers->TCNTB4 = timer_load_val; - /* auto load, manual update of Timer 4 */ - timers->TCON = (timers->TCON & ~0x0700000) | 0x600000; - /* auto load, start Timer 4 */ - timers->TCON = (timers->TCON & ~0x0700000) | 0x500000; - timestamp = 0; - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - ulong tmo; - ulong start = get_timer(0); - - tmo = usec / 1000; - tmo *= (timer_load_val * 100); - tmo /= 1000; - - while ((ulong)(get_timer_masked () - start) < tmo) - /*NOP*/; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER(); - timestamp = 0; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + timer_load_val - now; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= (timer_load_val * 100); - tmo /= 1000; - } else { - tmo = usec * (timer_load_val * 100); - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - -#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) - tbclk = timer_load_val * 100; -#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9) - tbclk = CFG_HZ; -#else -# error "tbclk not configured" -#endif - - return tbclk; -} - -/* - * reset the cpu by setting up the watchdog timer and let him time out - */ -void reset_cpu (ulong ignored) -{ - volatile S3C24X0_WATCHDOG * watchdog; - -#ifdef CONFIG_TRAB - extern void disable_vfd (void); - - disable_vfd(); -#endif - - watchdog = S3C24X0_GetBase_WATCHDOG(); - - /* Disable watchdog */ - watchdog->WTCON = 0x0000; - - /* Initialize watchdog timer count register */ - watchdog->WTCNT = 0x0001; - - /* Enable watchdog timer; assert reset at timer timeout */ - watchdog->WTCON = 0x0021; - - while(1); /* loop forever and wait for reset to happen */ - - /*NOTREACHED*/ -} - -#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/s3c24x0/serial.c b/cpu/arm920t/s3c24x0/serial.c deleted file mode 100644 index 8327443..0000000 --- a/cpu/arm920t/s3c24x0/serial.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) - -#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif - -#ifdef CONFIG_SERIAL1 -#define UART_NR S3C24X0_UART0 - -#elif defined(CONFIG_SERIAL2) -# if defined(CONFIG_TRAB) -# error "TRAB supports only CONFIG_SERIAL1" -# endif -#define UART_NR S3C24X0_UART1 - -#elif defined(CONFIG_SERIAL3) -# if defined(CONFIG_TRAB) -# #error "TRAB supports only CONFIG_SERIAL1" -# endif -#define UART_NR S3C24X0_UART2 - -#else -#error "Bad: you didn't configure serial ..." -#endif - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); - int i; - unsigned int reg = 0; - - /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ - reg = get_PCLK() / (16 * gd->baudrate) - 1; - - /* FIFO enable, Tx/Rx FIFO clear */ - uart->UFCON = 0x07; - uart->UMCON = 0x0; - /* Normal,No parity,1 stop,8 bit */ - uart->ULCON = 0x3; - /* - * tx=level,rx=edge,disable timeout int.,enable rx error int., - * normal,interrupt or polling - */ - uart->UCON = 0x245; - uart->UBRDIV = reg; - -#ifdef CONFIG_HWFLOW - uart->UMCON = 0x1; /* RTS up */ -#endif - for (i = 0; i < 100; i++); -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - serial_setbrg (); - - return (0); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); - - /* wait for character to arrive */ - while (!(uart->UTRSTAT & 0x1)); - - return uart->URXH & 0xff; -} - -#ifdef CONFIG_HWFLOW -static int hwflow = 0; /* turned off by default */ -int hwflow_onoff(int on) -{ - switch(on) { - case 0: - default: - break; /* return current */ - case 1: - hwflow = 1; /* turn on */ - break; - case -1: - hwflow = 0; /* turn off */ - break; - } - return hwflow; -} -#endif - -#ifdef CONFIG_MODEM_SUPPORT -static int be_quiet = 0; -void disable_putc(void) -{ - be_quiet = 1; -} - -void enable_putc(void) -{ - be_quiet = 0; -} -#endif - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); -#ifdef CONFIG_MODEM_SUPPORT - if (be_quiet) - return; -#endif - - /* wait for room in the tx FIFO */ - while (!(uart->UTRSTAT & 0x2)); - -#ifdef CONFIG_HWFLOW - /* Wait for CTS up */ - while(hwflow && !(uart->UMSTAT & 0x1)) - ; -#endif - - uart->UTXH = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc (void) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); - - return uart->UTRSTAT & 0x1; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c deleted file mode 100644 index e0dca62..0000000 --- a/cpu/arm920t/s3c24x0/speed.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This code should work for both the S3C2400 and the S3C2410 - * as they seem to have the same PLL and clock machinery inside. - * The different address mapping is handled by the s3c24xx.h files below. - */ - -#include -#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) - -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif - -#define MPLL 0 -#define UPLL 1 - -/* ------------------------------------------------------------------------- */ -/* NOTE: This describes the proper use of this file. - * - * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. - * - * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of - * the specified bus in HZ. - */ -/* ------------------------------------------------------------------------- */ - -static ulong get_PLLCLK(int pllreg) -{ - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - ulong r, m, p, s; - - if (pllreg == MPLL) - r = clk_power->MPLLCON; - else if (pllreg == UPLL) - r = clk_power->UPLLCON; - else - hang(); - - m = ((r & 0xFF000) >> 12) + 8; - p = ((r & 0x003F0) >> 4) + 2; - s = r & 0x3; - - return((CONFIG_SYS_CLK_FREQ * m) / (p << s)); -} - -/* return FCLK frequency */ -ulong get_FCLK(void) -{ - return(get_PLLCLK(MPLL)); -} - -/* return HCLK frequency */ -ulong get_HCLK(void) -{ - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - - return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK()); -} - -/* return PCLK frequency */ -ulong get_PCLK(void) -{ - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - - return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK()); -} - -/* return UCLK frequency */ -ulong get_UCLK(void) -{ - return(get_PLLCLK(UPLL)); -} - -#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c deleted file mode 100644 index b4cc744..0000000 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ /dev/null @@ -1,1688 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400. - * - * (C) Copyright 2003 - * Gary Jennejohn, DENX Software Engineering - * - * Note: Much of this code has been derived from Linux 2.4 - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2002 David Brownell - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* - * IMPORTANT NOTES - * 1 - you MUST define LITTLEENDIAN in the configuration file for the - * board or this driver will NOT work! - * 2 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! - */ - -#include -/* #include no PCI on the S3C24X0 */ - -#ifdef CONFIG_USB_OHCI - -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif - -#include -#include -#include "usb_ohci.h" - -#define OHCI_USE_NPS /* force NoPowerSwitching mode */ -#undef OHCI_VERBOSE_DEBUG /* not always helpful */ - - -/* For initializing controller (mask in an HCFS mode too) */ -#define OHCI_CONTROL_INIT \ - (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE - -#define readl(a) (*((vu_long *)(a))) -#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) - -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - -#undef DEBUG -#ifdef DEBUG -#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) -#else -#define dbg(format, arg...) do {} while(0) -#endif /* DEBUG */ -#define err(format, arg...) printf("ERROR: " format "\n", ## arg) -#undef SHOW_INFO -#ifdef SHOW_INFO -#define info(format, arg...) printf("INFO: " format "\n", ## arg) -#else -#define info(format, arg...) do {} while(0) -#endif - -#define m16_swap(x) swap_16(x) -#define m32_swap(x) swap_32(x) - -/* global ohci_t */ -static ohci_t gohci; -/* this must be aligned to a 256 byte boundary */ -struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* urb_priv */ -urb_priv_t urb_priv; -/* RHSC flag */ -int got_rhsc; -/* device which was disconnected */ -struct usb_device *devgone; -/* flag guarding URB transation */ -int urb_finished = 0; - -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a (struct ohci *hc) - { return read_roothub (hc, a, 0xfc0fe000); } -static inline u32 roothub_b (struct ohci *hc) - { return readl (&hc->regs->roothub.b); } -static inline u32 roothub_status (struct ohci *hc) - { return readl (&hc->regs->roothub.status); } -static u32 roothub_portstatus (struct ohci *hc, int i) - { return read_roothub (hc, portstatus [i], 0xffe0fce0); } - - -/* forward declaration */ -static int hc_interrupt (void); -static void -td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); - -/*-------------------------------------------------------------------------* - * URB support functions - *-------------------------------------------------------------------------*/ - -/* free HCD-private data associated with this URB */ - -static void urb_free_priv (urb_priv_t * urb) -{ - int i; - int last; - struct td * td; - - last = urb->length - 1; - if (last >= 0) { - for (i = 0; i <= last; i++) { - td = urb->td[i]; - if (td) { - td->usb_dev = NULL; - urb->td[i] = NULL; - } - } - } -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -static int sohci_get_current_frame_number (struct usb_device * dev); - -/* debug| print the main components of an URB - * small: 0) header + data packets 1) just header */ - -static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, char * str, int small) -{ - urb_priv_t * purb = &urb_priv; - - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", - str, - sohci_get_current_frame_number (dev), - usb_pipedevice (pipe), - usb_pipeendpoint (pipe), - usb_pipeout (pipe)? 'O': 'I', - usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): - (usb_pipecontrol (pipe)? "CTRL": "BULK"), - purb->actual_length, - transfer_len, dev->status); -#ifdef OHCI_VERBOSE_DEBUG - if (!small) { - int i, len; - - if (usb_pipecontrol (pipe)) { - printf (__FILE__ ": cmd(8):"); - for (i = 0; i < 8 ; i++) - printf (" %02x", ((__u8 *) setup) [i]); - printf ("\n"); - } - if (transfer_len > 0 && buffer) { - printf (__FILE__ ": data(%d/%d):", - purb->actual_length, - transfer_len); - len = usb_pipeout (pipe)? - transfer_len: purb->actual_length; - for (i = 0; i < 16 && i < len; i++) - printf (" %02x", ((__u8 *) buffer) [i]); - printf ("%s\n", i < len? "...": ""); - } - } -#endif -} - -/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ -void ep_print_int_eds (ohci_t *ohci, char * str) { - int i, j; - __u32 * ed_p; - for (i= 0; i < 32; i++) { - j = 5; - ed_p = &(ohci->hcca->int_table [i]); - if (*ed_p == 0) - continue; - printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); - while (*ed_p != 0 && j--) { - ed_t *ed = (ed_t *)m32_swap(ed_p); - printf (" ed: %4x;", ed->hwINFO); - ed_p = &ed->hwNextED; - } - printf ("\n"); - } -} - -static void ohci_dump_intr_mask (char *label, __u32 mask) -{ - dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", - label, - mask, - (mask & OHCI_INTR_MIE) ? " MIE" : "", - (mask & OHCI_INTR_OC) ? " OC" : "", - (mask & OHCI_INTR_RHSC) ? " RHSC" : "", - (mask & OHCI_INTR_FNO) ? " FNO" : "", - (mask & OHCI_INTR_UE) ? " UE" : "", - (mask & OHCI_INTR_RD) ? " RD" : "", - (mask & OHCI_INTR_SF) ? " SF" : "", - (mask & OHCI_INTR_WDH) ? " WDH" : "", - (mask & OHCI_INTR_SO) ? " SO" : "" - ); -} - -static void maybe_print_eds (char *label, __u32 value) -{ - ed_t *edp = (ed_t *)value; - - if (value) { - dbg ("%s %08x", label, value); - dbg ("%08x", edp->hwINFO); - dbg ("%08x", edp->hwTailP); - dbg ("%08x", edp->hwHeadP); - dbg ("%08x", edp->hwNextED); - } -} - -static char * hcfs2string (int state) -{ - switch (state) { - case OHCI_USB_RESET: return "reset"; - case OHCI_USB_RESUME: return "resume"; - case OHCI_USB_OPER: return "operational"; - case OHCI_USB_SUSPEND: return "suspend"; - } - return "?"; -} - -/* dump control and status registers */ -static void ohci_dump_status (ohci_t *controller) -{ - struct ohci_regs *regs = controller->regs; - __u32 temp; - - temp = readl (®s->revision) & 0xff; - if (temp != 0x10) - dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); - - temp = readl (®s->control); - dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, - (temp & OHCI_CTRL_RWE) ? " RWE" : "", - (temp & OHCI_CTRL_RWC) ? " RWC" : "", - (temp & OHCI_CTRL_IR) ? " IR" : "", - hcfs2string (temp & OHCI_CTRL_HCFS), - (temp & OHCI_CTRL_BLE) ? " BLE" : "", - (temp & OHCI_CTRL_CLE) ? " CLE" : "", - (temp & OHCI_CTRL_IE) ? " IE" : "", - (temp & OHCI_CTRL_PLE) ? " PLE" : "", - temp & OHCI_CTRL_CBSR - ); - - temp = readl (®s->cmdstatus); - dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, - (temp & OHCI_SOC) >> 16, - (temp & OHCI_OCR) ? " OCR" : "", - (temp & OHCI_BLF) ? " BLF" : "", - (temp & OHCI_CLF) ? " CLF" : "", - (temp & OHCI_HCR) ? " HCR" : "" - ); - - ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); - ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); - - maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); - - maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); - maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); - - maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); - maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); - - maybe_print_eds ("donehead", readl (®s->donehead)); -} - -static void ohci_dump_roothub (ohci_t *controller, int verbose) -{ - __u32 temp, ndp, i; - - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - - if (verbose) { - dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, - ((temp & RH_A_POTPGT) >> 24) & 0xff, - (temp & RH_A_NOCP) ? " NOCP" : "", - (temp & RH_A_OCPM) ? " OCPM" : "", - (temp & RH_A_DT) ? " DT" : "", - (temp & RH_A_NPS) ? " NPS" : "", - (temp & RH_A_PSM) ? " PSM" : "", - ndp - ); - temp = roothub_b (controller); - dbg ("roothub.b: %08x PPCM=%04x DR=%04x", - temp, - (temp & RH_B_PPCM) >> 16, - (temp & RH_B_DR) - ); - temp = roothub_status (controller); - dbg ("roothub.status: %08x%s%s%s%s%s%s", - temp, - (temp & RH_HS_CRWE) ? " CRWE" : "", - (temp & RH_HS_OCIC) ? " OCIC" : "", - (temp & RH_HS_LPSC) ? " LPSC" : "", - (temp & RH_HS_DRWE) ? " DRWE" : "", - (temp & RH_HS_OCI) ? " OCI" : "", - (temp & RH_HS_LPS) ? " LPS" : "" - ); - } - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", - i, - temp, - (temp & RH_PS_PRSC) ? " PRSC" : "", - (temp & RH_PS_OCIC) ? " OCIC" : "", - (temp & RH_PS_PSSC) ? " PSSC" : "", - (temp & RH_PS_PESC) ? " PESC" : "", - (temp & RH_PS_CSC) ? " CSC" : "", - - (temp & RH_PS_LSDA) ? " LSDA" : "", - (temp & RH_PS_PPS) ? " PPS" : "", - (temp & RH_PS_PRS) ? " PRS" : "", - (temp & RH_PS_POCI) ? " POCI" : "", - (temp & RH_PS_PSS) ? " PSS" : "", - - (temp & RH_PS_PES) ? " PES" : "", - (temp & RH_PS_CCS) ? " CCS" : "" - ); - } -} - -static void ohci_dump (ohci_t *controller, int verbose) -{ - dbg ("OHCI controller usb-%s state", controller->slot_name); - - /* dumps some of the state we know about */ - ohci_dump_status (controller); - if (verbose) - ep_print_int_eds (controller, "hcca"); - dbg ("hcca frame #%04x", controller->hcca->frame_no); - ohci_dump_roothub (controller, 1); -} - - -#endif /* DEBUG */ - -/*-------------------------------------------------------------------------* - * Interface functions (URB) - *-------------------------------------------------------------------------*/ - -/* get a transfer request */ - -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - ohci_t *ohci; - ed_t * ed; - urb_priv_t *purb_priv; - int i, size = 0; - - ohci = &gohci; - - /* when controller's hung, permit only roothub cleanup attempts - * such as powering down ports */ - if (ohci->disabled) { - err("sohci_submit_job: EPIPE"); - return -1; - } - - /* if we have an unfinished URB from previous transaction let's - * fail and scream as quickly as possible so as not to corrupt - * further communication */ - if (!urb_finished) { - err("sohci_submit_job: URB NOT FINISHED"); - return -1; - } - /* we're about to begin a new transaction here so mark the URB unfinished */ - urb_finished = 0; - - /* every endpoint has a ed, locate and fill it */ - if (!(ed = ep_add_ed (dev, pipe))) { - err("sohci_submit_job: ENOMEM"); - return -1; - } - - /* for the private part of the URB we need the number of TDs (size) */ - switch (usb_pipetype (pipe)) { - case PIPE_BULK: /* one TD for every 4096 Byte */ - size = (transfer_len - 1) / 4096 + 1; - break; - case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ - size = (transfer_len == 0)? 2: - (transfer_len - 1) / 4096 + 3; - break; - } - - if (size >= (N_URB_TD - 1)) { - err("need %d TDs, only have %d", size, N_URB_TD); - return -1; - } - purb_priv = &urb_priv; - purb_priv->pipe = pipe; - - /* fill the private part of the URB */ - purb_priv->length = size; - purb_priv->ed = ed; - purb_priv->actual_length = 0; - - /* allocate the TDs */ - /* note that td[0] was allocated in ep_add_ed */ - for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc (dev); - if (!purb_priv->td[i]) { - purb_priv->length = i; - urb_free_priv (purb_priv); - err("sohci_submit_job: ENOMEM"); - return -1; - } - } - - if (ed->state == ED_NEW || (ed->state & ED_DEL)) { - urb_free_priv (purb_priv); - err("sohci_submit_job: EINVAL"); - return -1; - } - - /* link the ed into a chain if is not already */ - if (ed->state != ED_OPER) - ep_link (ohci, ed); - - /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -/* tell us the current USB frame number */ - -static int sohci_get_current_frame_number (struct usb_device *usb_dev) -{ - ohci_t *ohci = &gohci; - - return m16_swap (ohci->hcca->frame_no); -} -#endif - -/*-------------------------------------------------------------------------* - * ED handling functions - *-------------------------------------------------------------------------*/ - -/* link an ed into one of the HC chains */ - -static int ep_link (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->state = ED_OPER; - - switch (ed->type) { - case PIPE_CONTROL: - ed->hwNextED = 0; - if (ohci->ed_controltail == NULL) { - writel (ed, &ohci->regs->ed_controlhead); - } else { - ohci->ed_controltail->hwNextED = m32_swap (ed); - } - ed->ed_prev = ohci->ed_controltail; - if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_controltail = edi; - break; - - case PIPE_BULK: - ed->hwNextED = 0; - if (ohci->ed_bulktail == NULL) { - writel (ed, &ohci->regs->ed_bulkhead); - } else { - ohci->ed_bulktail->hwNextED = m32_swap (ed); - } - ed->ed_prev = ohci->ed_bulktail; - if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_bulktail = edi; - break; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* unlink an ed from one of the HC chains. - * just the link to the ed is unlinked. - * the link from the ed still points to another operational ed or 0 - * so the HC can eventually finish the processing of the unlinked ed */ - -static int ep_unlink (ohci_t *ohci, ed_t *ed) -{ - ed->hwINFO |= m32_swap (OHCI_ED_SKIP); - - switch (ed->type) { - case PIPE_CONTROL: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_controltail == ed) { - ohci->ed_controltail = ed->ed_prev; - } else { - ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - - case PIPE_BULK: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_bulktail == ed) { - ohci->ed_bulktail = ed->ed_prev; - } else { - ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - } - ed->state = ED_UNLINK; - return 0; -} - - -/*-------------------------------------------------------------------------*/ - -/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, - * but the USB stack is a little bit stateless so we do it at every transaction - * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK - * in all other cases the state is left unchanged - * the ed info fields are setted anyway even though most of them should not change */ - -static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) -{ - td_t *td; - ed_t *ed_ret; - volatile ed_t *ed; - - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | - (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; - - if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { - err("ep_add_ed: pending delete"); - /* pending delete request */ - return NULL; - } - - if (ed->state == ED_NEW) { - ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ - /* dummy td; end of td list for ed */ - td = td_alloc (usb_dev); - ed->hwTailP = m32_swap (td); - ed->hwHeadP = ed->hwTailP; - ed->state = ED_UNLINK; - ed->type = usb_pipetype (pipe); - ohci_dev.ed_cnt++; - } - - ed->hwINFO = m32_swap (usb_pipedevice (pipe) - | usb_pipeendpoint (pipe) << 7 - | (usb_pipeisoc (pipe)? 0x8000: 0) - | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | usb_pipeslow (pipe) << 13 - | usb_maxpacket (usb_dev, pipe) << 16); - - return ed_ret; -} - -/*-------------------------------------------------------------------------* - * TD handling functions - *-------------------------------------------------------------------------*/ - -/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ - -static void td_fill (ohci_t *ohci, unsigned int info, - void *data, int len, - struct usb_device *dev, int index, urb_priv_t *urb_priv) -{ - volatile td_t *td, *td_pt; -#ifdef OHCI_FILL_TRACE - int i; -#endif - - if (index > urb_priv->length) { - err("index > length"); - return; - } - /* use this td as the next dummy */ - td_pt = urb_priv->td [index]; - td_pt->hwNextTD = 0; - - /* fill the old dummy TD */ - td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); - - td->ed = urb_priv->ed; - td->next_dl_td = NULL; - td->index = index; - td->data = (__u32)data; -#ifdef OHCI_FILL_TRACE - if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { - for (i = 0; i < len; i++) - printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); - printf("\n"); - } -#endif - if (!len) - data = 0; - - td->hwINFO = m32_swap (info); - td->hwCBP = m32_swap (data); - if (data) - td->hwBE = m32_swap (data + len - 1); - else - td->hwBE = 0; - td->hwNextTD = m32_swap (td_pt); - - /* append to queue */ - td->ed->hwTailP = td->hwNextTD; -} - -/*-------------------------------------------------------------------------*/ - -/* prepare all TDs of a transfer */ - -static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) -{ - ohci_t *ohci = &gohci; - int data_len = transfer_len; - void *data; - int cnt = 0; - __u32 info = 0; - unsigned int toggle = 0; - - /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ - if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { - toggle = TD_T_TOGGLE; - } else { - toggle = TD_T_DATA0; - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); - } - urb->td_cnt = 0; - if (data_len) - data = buffer; - else - data = 0; - - switch (usb_pipetype (pipe)) { - case PIPE_BULK: - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; - while(data_len > 4096) { - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); - data += 4096; data_len -= 4096; cnt++; - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); - cnt++; - - if (!ohci->sleeping) - writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ - break; - - case PIPE_CONTROL: - info = TD_CC | TD_DP_SETUP | TD_T_DATA0; - td_fill (ohci, info, setup, 8, dev, cnt++, urb); - if (data_len > 0) { - info = usb_pipeout (pipe)? - TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; - /* NOTE: mishandles transfers >8K, some >4K */ - td_fill (ohci, info, data, data_len, dev, cnt++, urb); - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; - td_fill (ohci, info, data, 0, dev, cnt++, urb); - if (!ohci->sleeping) - writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ - break; - } - if (urb->length != cnt) - dbg("TD LENGTH %d != CNT %d", urb->length, cnt); -} - -/*-------------------------------------------------------------------------* - * Done List handling functions - *-------------------------------------------------------------------------*/ - - -/* calculate the transfer length and update the urb */ - -static void dl_transfer_length(td_t * td) -{ - __u32 tdINFO, tdBE, tdCBP; - urb_priv_t *lurb_priv = &urb_priv; - - tdINFO = m32_swap (td->hwINFO); - tdBE = m32_swap (td->hwBE); - tdCBP = m32_swap (td->hwCBP); - - - if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && - ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { - if (tdBE != 0) { - if (td->hwCBP == 0) - lurb_priv->actual_length += tdBE - td->data + 1; - else - lurb_priv->actual_length += tdCBP - td->data; - } - } -} - -/*-------------------------------------------------------------------------*/ - -/* replies to the request have to be on a FIFO basis so - * we reverse the reversed done-list */ - -static td_t * dl_reverse_done_list (ohci_t *ohci) -{ - __u32 td_list_hc; - td_t *td_rev = NULL; - td_t *td_list = NULL; - urb_priv_t *lurb_priv = NULL; - - td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; - ohci->hcca->done_head = 0; - - while (td_list_hc) { - td_list = (td_t *)td_list_hc; - - if (TD_CC_GET (m32_swap (td_list->hwINFO))) { - lurb_priv = &urb_priv; - dbg(" USB-error/status: %x : %p", - TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); - if (td_list->ed->hwHeadP & m32_swap (0x1)) { - if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { - td_list->ed->hwHeadP = - (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | - (td_list->ed->hwHeadP & m32_swap (0x2)); - lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; - } else - td_list->ed->hwHeadP &= m32_swap (0xfffffff2); - } - } - - td_list->next_dl_td = td_rev; - td_rev = td_list; - td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; - } - - return td_list; -} - -/*-------------------------------------------------------------------------*/ - -/* td done list */ -static int dl_done_list (ohci_t *ohci, td_t *td_list) -{ - td_t *td_list_next = NULL; - ed_t *ed; - int cc = 0; - int stat = 0; - /* urb_t *urb; */ - urb_priv_t *lurb_priv; - __u32 tdINFO, edHeadP, edTailP; - - while (td_list) { - td_list_next = td_list->next_dl_td; - - lurb_priv = &urb_priv; - tdINFO = m32_swap (td_list->hwINFO); - - ed = td_list->ed; - - dl_transfer_length(td_list); - - /* error code of transfer */ - cc = TD_CC_GET (tdINFO); - if (cc != 0) { - dbg("ConditionCode %#x", cc); - stat = cc_to_error[cc]; - } - - /* see if this done list makes for all TD's of current URB, - * and mark the URB finished if so */ - if (++(lurb_priv->td_cnt) == lurb_priv->length) { - if ((ed->state & (ED_OPER | ED_UNLINK))) - urb_finished = 1; - else - dbg("dl_done_list: strange.., ED state %x, ed->state\n"); - } else - dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt, - lurb_priv->length); - - if (ed->state != ED_NEW) { - edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; - edTailP = m32_swap (ed->hwTailP); - - /* unlink eds if they are not busy */ - if ((edHeadP == edTailP) && (ed->state == ED_OPER)) - ep_unlink (ohci, ed); - } - - td_list = td_list_next; - } - return stat; -} - -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ - -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - -/* Hub class-specific descriptor is constructed dynamically */ - - -/*-------------------------------------------------------------------------*/ - -#define OK(x) len = (x); break -#ifdef DEBUG -#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} -#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} -#else -#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) -#endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) - -/* request to virtual root hub */ - -int rh_check_port_status(ohci_t *controller) -{ - __u32 temp, ndp, i; - int res; - - res = -1; - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - /* check for a device disconnect */ - if (((temp & (RH_PS_PESC | RH_PS_CSC)) == - (RH_PS_PESC | RH_PS_CSC)) && - ((temp & RH_PS_CCS) == 0)) { - res = i; - break; - } - } - return res; -} - -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *cmd) -{ - void * data = buffer; - int leni = transfer_len; - int len = 0; - int stat = 0; - __u32 datab[4]; - __u8 *data_buf = (__u8 *)datab; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; - -#ifdef DEBUG -urb_priv.actual_length = 0; -pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { - info("Root-Hub submit IRQ: NOT implemented"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = m16_swap (cmd->value); - wIndex = m16_swap (cmd->index); - wLength = m16_swap (cmd->length); - - info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", - dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(__u16 *) data_buf = m16_swap (1); OK (2); - case RH_GET_STATUS | RH_INTERFACE: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_ENDPOINT: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_CLASS: - *(__u32 *) data_buf = m32_swap ( - RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); - OK (4); - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); - - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case RH_C_HUB_LOCAL_POWER: - OK(0); - case (RH_C_HUB_OVER_CURRENT): - WR_RH_STAT(RH_HS_OCIC); OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_POCI); OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); - case (RH_C_PORT_CONNECTION): - WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); - case (RH_C_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_PESC); OK (0); - case (RH_C_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); - case (RH_C_PORT_OVER_CURRENT): - WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); - case (RH_C_PORT_RESET): - WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); - } - break; - - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); - case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PRS); - OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); - case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PES ); - OK (0); - } - break; - - case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_dev_des), - wLength)); - data_buf = root_hub_dev_des; OK(len); - case (0x02): /* configuration descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_config_des), - wLength)); - data_buf = root_hub_config_des; OK(len); - case (0x03): /* string descriptors */ - if(wValue==0x0300) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index0), - wLength)); - data_buf = root_hub_str_index0; - OK(len); - } - if(wValue==0x0301) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index1), - wLength)); - data_buf = root_hub_str_index1; - OK(len); - } - default: - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - { - __u32 temp = roothub_a (&gohci); - - data_buf [0] = 9; /* min length; */ - data_buf [1] = 0x29; - data_buf [2] = temp & RH_A_NDP; - data_buf [3] = 0; - if (temp & RH_A_PSM) /* per-port power switching? */ - data_buf [3] |= 0x1; - if (temp & RH_A_NOCP) /* no overcurrent reporting? */ - data_buf [3] |= 0x10; - else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ - data_buf [3] |= 0x8; - - /* corresponds to data_buf[4-7] */ - datab [1] = 0; - data_buf [5] = (temp & RH_A_POTPGT) >> 24; - temp = roothub_b (&gohci); - data_buf [7] = temp & RH_B_DR; - if (data_buf [2] < 7) { - data_buf [8] = 0xff; - } else { - data_buf [0] += 2; - data_buf [8] = (temp & RH_B_DR) >> 8; - data_buf [10] = data_buf [9] = 0xff; - } - - len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf [0], wLength)); - OK (len); - } - - case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); - - case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); - - default: - dbg ("unsupported root hub command"); - stat = USB_ST_STALLED; - } - -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#else - wait_ms(1); -#endif - - len = min_t(int, len, leni); - if (data != data_buf) - memcpy (data, data_buf, len); - dev->act_len = len; - dev->status = stat; - -#ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); -#else - wait_ms(1); -#endif - - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/* common code for handling submit messages - used for all but root hub */ -/* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; - - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } - -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if (!maxsize) { - err("submit_common_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { - err("sohci_submit_job failed"); - return -1; - } - - wait_ms(10); - /* ohci_dump_status(&gohci); */ - - /* allow more time for a BULK device to react - some are slow */ -#define BULK_TO 5000 /* timeout in milliseconds */ - if (usb_pipetype (pipe) == PIPE_BULK) - timeout = BULK_TO; - else - timeout = 100; - - /* wait for it to complete */ - for (;;) { - /* check whether the controller is done */ - stat = hc_interrupt(); - - if (stat < 0) { - stat = USB_ST_CRC_ERR; - break; - } - - /* NOTE: since we are not interrupt driven in U-Boot and always - * handle only one URB at a time, we cannot assume the - * transaction finished on the first successful return from - * hc_interrupt().. unless the flag for current URB is set, - * meaning that all TD's to/from device got actually - * transferred and processed. If the current URB is not - * finished we need to re-iterate this loop so as - * hc_interrupt() gets called again as there needs to be some - * more TD's to process still */ - if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { - /* 0xff is returned for an SF-interrupt */ - break; - } - - if (--timeout) { - wait_ms(1); - if (!urb_finished) - dbg("\%"); - - } else { - err("CTL:TIMEOUT "); - dbg("submit_common_msg: TO status %x\n", stat); - stat = USB_ST_CRC_ERR; - urb_finished = 1; - break; - } - } - -#if 0 - /* we got an Root Hub Status Change interrupt */ - if (got_rhsc) { -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - got_rhsc = 0; - /* abuse timeout */ - timeout = rh_check_port_status(&gohci); - if (timeout >= 0) { -#if 0 /* this does nothing useful, but leave it here in case that changes */ - /* the called routine adds 1 to the passed value */ - usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); -#endif - /* - * XXX - * This is potentially dangerous because it assumes - * that only one device is ever plugged in! - */ - devgone = dev; - } - } -#endif - - dev->status = stat; - dev->act_len = transfer_len; - -#ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - - /* free TDs in urb_priv */ - urb_free_priv (&urb_priv); - return 0; -} - -/* submit routines called from usb.c */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) -{ - info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) -{ - int maxsize = usb_maxpacket(dev, pipe); - - info("submit_control_msg"); -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if (!maxsize) { - err("submit_control_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; - /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); - } - - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return -1; -} - -/*-------------------------------------------------------------------------* - * HC functions - *-------------------------------------------------------------------------*/ - -/* reset the HC and BUS */ - -static int hc_reset (ohci_t *ohci) -{ - int timeout = 30; - int smm_timeout = 50; /* 0,5 sec */ - - if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ - writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ - info("USB HC TakeOver from SMM"); - while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms (10); - if (--smm_timeout == 0) { - err("USB HC TakeOver failed!"); - return -1; - } - } - } - - /* Disable HC interrupts */ - writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); - - dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", - ohci->slot_name, - readl (&ohci->regs->control)); - - /* Reset USB (needed by some controllers) */ - writel (0, &ohci->regs->control); - - /* HC Reset requires max 10 us delay */ - writel (OHCI_HCR, &ohci->regs->cmdstatus); - while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { - if (--timeout == 0) { - err("USB HC reset timed out!"); - return -1; - } - udelay (1); - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* Start an OHCI controller, set the BUS operational - * enable interrupts - * connect the virtual root hub */ - -static int hc_start (ohci_t * ohci) -{ - __u32 mask; - unsigned int fminterval; - - ohci->disabled = 1; - - /* Tell the controller where the control and bulk lists are - * The lists are empty now. */ - - writel (0, &ohci->regs->ed_controlhead); - writel (0, &ohci->regs->ed_bulkhead); - - writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ - - fminterval = 0x2edf; - writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); - fminterval |= ((((fminterval - 210) * 6) / 7) << 16); - writel (fminterval, &ohci->regs->fminterval); - writel (0x628, &ohci->regs->lsthresh); - - /* start controller operations */ - ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; - ohci->disabled = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* disable all interrupts */ - mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | - OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | - OHCI_INTR_OC | OHCI_INTR_MIE); - writel (mask, &ohci->regs->intrdisable); - /* clear all interrupts */ - mask &= ~OHCI_INTR_MIE; - writel (mask, &ohci->regs->intrstatus); - /* Choose the interrupts we care about now - but w/o MIE */ - mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; - writel (mask, &ohci->regs->intrenable); - -#ifdef OHCI_USE_NPS - /* required for AMD-756 and some Mac platforms */ - writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, - &ohci->regs->roothub.a); - writel (RH_HS_LPSC, &ohci->regs->roothub.status); -#endif /* OHCI_USE_NPS */ - -#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay ((roothub_a (ohci) >> 23) & 0x1fe); - - /* connect the virtual root hub */ - ohci->rh.devnum = 0; - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* an interrupt happens */ - -static int -hc_interrupt (void) -{ - ohci_t *ohci = &gohci; - struct ohci_regs *regs = ohci->regs; - int ints; - int stat = -1; - - if ((ohci->hcca->done_head != 0) && - !(m32_swap (ohci->hcca->done_head) & 0x01)) { - - ints = OHCI_INTR_WDH; - - } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { - ohci->disabled++; - err ("%s device removed!", ohci->slot_name); - return -1; - - } else if ((ints &= readl (®s->intrenable)) == 0) { - dbg("hc_interrupt: returning..\n"); - return 0xff; - } - - /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ - - if (ints & OHCI_INTR_RHSC) { - got_rhsc = 1; - stat = 0xff; - } - - if (ints & OHCI_INTR_UE) { - ohci->disabled++; - err ("OHCI Unrecoverable Error, controller usb-%s disabled", - ohci->slot_name); - /* e.g. due to PCI Master/Target Abort */ - -#ifdef DEBUG - ohci_dump (ohci, 1); -#else - wait_ms(1); -#endif - /* FIXME: be optimistic, hope that bug won't repeat often. */ - /* Make some non-interrupt context restart the controller. */ - /* Count and limit the retries though; either hardware or */ - /* software errors can go forever... */ - hc_reset (ohci); - return -1; - } - - if (ints & OHCI_INTR_WDH) { - wait_ms(1); - - writel (OHCI_INTR_WDH, ®s->intrdisable); - stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); - writel (OHCI_INTR_WDH, ®s->intrenable); - } - - if (ints & OHCI_INTR_SO) { - dbg("USB Schedule overrun\n"); - writel (OHCI_INTR_SO, ®s->intrenable); - stat = -1; - } - - /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ - if (ints & OHCI_INTR_SF) { - unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; - wait_ms(1); - writel (OHCI_INTR_SF, ®s->intrdisable); - if (ohci->ed_rm_list[frame] != NULL) - writel (OHCI_INTR_SF, ®s->intrenable); - stat = 0xff; - } - - writel (ints, ®s->intrstatus); - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -/* De-allocate all resources.. */ - -static void hc_release_ohci (ohci_t *ohci) -{ - dbg ("USB HC release ohci usb-%s", ohci->slot_name); - - if (!ohci->disabled) - hc_reset (ohci); -} - -/*-------------------------------------------------------------------------*/ - -/* - * low level initalisation routine, called from usb.c - */ -static char ohci_inited = 0; - -int usb_lowlevel_init(void) -{ - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); - - /* - * Set the 48 MHz UPLL clocking. Values are taken from - * "PLL value selection guide", 6-23, s3c2400_UM.pdf. - */ - clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2); - gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */ - - /* - * Enable USB host clock. - */ - clk_power->CLKCON |= (1 << 4); - - memset (&gohci, 0, sizeof (ohci_t)); - memset (&urb_priv, 0, sizeof (urb_priv_t)); - - /* align the storage */ - if ((__u32)&ghcca[0] & 0xff) { - err("HCCA not aligned!!"); - return -1; - } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32)&ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); - if ((__u32)gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset (phcca, 0, sizeof (struct ohci_hcca)); - - gohci.disabled = 1; - gohci.sleeping = 0; - gohci.irq = -1; - gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE; - - gohci.flags = 0; - gohci.slot_name = "s3c2400"; - - if (hc_reset (&gohci) < 0) { - hc_release_ohci (&gohci); - /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); - return -1; - } - - /* FIXME this is a second HC reset; why?? */ - writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); - wait_ms (10); - - if (hc_start (&gohci) < 0) { - err ("can't start usb-%s", gohci.slot_name); - hc_release_ohci (&gohci); - /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); - return -1; - } - -#ifdef DEBUG - ohci_dump (&gohci, 1); -#else - wait_ms(1); -#endif - ohci_inited = 1; - urb_finished = 1; - - return 0; -} - -int usb_lowlevel_stop(void) -{ - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); - - /* this gets called really early - before the controller has */ - /* even been initialized! */ - if (!ohci_inited) - return 0; - /* TODO release any interrupts, etc. */ - /* call hc_release_ohci() here ? */ - hc_reset (&gohci); - /* may not want to do this */ - clk_power->CLKCON &= ~(1 << 4); - return 0; -} - -#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/arm920t/s3c24x0/usb_ohci.h b/cpu/arm920t/s3c24x0/usb_ohci.h deleted file mode 100644 index 5e9a0fd..0000000 --- a/cpu/arm920t/s3c24x0/usb_ohci.h +++ /dev/null @@ -1,417 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB. - * - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2001 David Brownell - * - * usb-ohci.h - */ - - -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -/* ED States */ -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 -#define ED_OPER 0x02 -#define ED_DEL 0x04 -#define ED_URB_DEL 0x08 - -/* usb_ohci_ed */ -struct ed { - __u32 hwINFO; - __u32 hwTailP; - __u32 hwHeadP; - __u32 hwNextED; - - struct ed *ed_prev; - __u8 int_period; - __u8 int_branch; - __u8 int_load; - __u8 int_interval; - __u8 state; - __u8 type; - __u16 last_iso; - struct ed *ed_rm_list; - - struct usb_device *usb_dev; - __u32 unused[3]; -} __attribute((aligned(16))); -typedef struct ed ed_t; - - -/* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 - -/* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F - - -#define MAXPSW 1 - -struct td { - __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; - struct usb_device *usb_dev; - int transfer_len; - __u32 data; - - __u32 unused2[2]; -} __attribute((aligned(32))); -typedef struct td td_t; - -#define OHCI_ED_SKIP (1 << 14) - -/* - * The HCCA (Host Controller Communications Area) is a 256 byte - * structure defined in the OHCI spec. that the host controller is - * told the base address of. It must be 256-byte aligned. - */ - -#define NUM_INTS 32 /* part of the OHCI standard */ -struct ohci_hcca { - __u32 int_table[NUM_INTS]; /* Interrupt ED table */ - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ - __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; -} __attribute((aligned(256))); - - -/* - * Maximum number of root hub ports. - */ -#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ - -/* - * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and - * writel() macros defined in asm/io.h to access these!! - */ -struct ohci_regs { - /* control and status registers */ - __u32 revision; - __u32 control; - __u32 cmdstatus; - __u32 intrstatus; - __u32 intrenable; - __u32 intrdisable; - /* memory pointers */ - __u32 hcca; - __u32 ed_periodcurrent; - __u32 ed_controlhead; - __u32 ed_controlcurrent; - __u32 ed_bulkhead; - __u32 ed_bulkcurrent; - __u32 donehead; - /* frame counters */ - __u32 fminterval; - __u32 fmremaining; - __u32 fmnumber; - __u32 periodicstart; - __u32 lsthresh; - /* Root hub ports */ - struct ohci_roothub_regs { - __u32 a; - __u32 b; - __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; - } roothub; -} __attribute((aligned(32))); - - -/* OHCI CONTROL AND STATUS REGISTER MASKS */ - -/* - * HcControl (control) register masks - */ -#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ -#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ - -/* pre-shifted values for HCFS */ -# define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) -# define OHCI_USB_OPER (2 << 6) -# define OHCI_USB_SUSPEND (3 << 6) - -/* - * HcCommandStatus (cmdstatus) register masks - */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ - -/* - * masks used with interrupt registers: - * HcInterruptStatus (intrstatus) - * HcInterruptEnable (intrenable) - * HcInterruptDisable (intrdisable) - */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ - - -/* Virtual Root HUB */ -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - void *dev; /* was urb */ - void *int_addr; - int send; - int interval; -}; - -/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ - -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* OHCI ROOT HUB REGISTER MASKS */ - -/* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ - -/* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ - -/* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ - -/* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ - -/* urb */ -#define N_URB_TD 48 -typedef struct -{ - ed_t *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ - int state; - unsigned long pipe; - int actual_length; - td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ -} urb_priv_t; -#define URB_DEL 1 - -/* - * This is the full ohci controller description - * - * Note how the "proper" USB information is just - * a subset of what the full implementation needs. (Linus) - */ - - -typedef struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma;*/ - - int irq; - int disabled; /* e.g. got a UE, we're hung */ - int sleeping; - unsigned long flags; /* for HC bugs */ - - struct ohci_regs *regs; /* OHCI controller's memory */ - - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ - int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ - struct usb_device *dev[32]; - struct virt_root_hub rh; - - const char *slot_name; -} ohci_t; - -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - ed_t ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(ohci_t * ohci, ed_t * ed); -static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -td_t gtd[NUM_TD+1]; -/* pointers to aligned storage */ -td_t *ptd; - -/* TDs ... */ -static inline struct td * -td_alloc (struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) - { - if (ptd[i].usb_dev == NULL) - { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - - return td; -} - -static inline void -ed_free (struct ed *ed) -{ - ed->usb_dev = NULL; -} diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S deleted file mode 100644 index 4603cf5..0000000 --- a/cpu/arm920t/start.S +++ /dev/null @@ -1,433 +0,0 @@ -/* - * armboot - Startup Code for ARM920 CPU-core - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * relocate armboot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - -/* turn off the watchdog */ -#if defined(CONFIG_S3C2400) -# define pWTCON 0x15300000 -# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ -# define CLKDIVN 0x14800014 /* clock divisor register */ -#elif defined(CONFIG_S3C2410) -# define pWTCON 0x53000000 -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ -# define INTSUBMSK 0x4A00001C -# define CLKDIVN 0x4C000014 /* clock divisor register */ -#endif - -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) - ldr r0, =pWTCON - mov r1, #0x0 - str r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTMR - default - */ - mov r1, #0xffffffff - ldr r0, =INTMSK - str r1, [r0] -# if defined(CONFIG_S3C2410) - ldr r1, =0x3ff - ldr r0, =INTSUBMSK - str r1, [r0] -# endif - - /* FCLK:HCLK:PCLK = 1:2:4 */ - /* default FCLK is 120 MHz ! */ - ldr r0, =CLKDIVN - mov r1, #3 - str r1, [r0] -#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */ - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - -#ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - -#if 0 - /* try doing this stuff after the relocation */ - ldr r0, =pWTCON - mov r1, #0x0 - str r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTMR - default - */ - mov r1, #0xffffffff - ldr r0, =INTMR - str r1, [r0] - - /* FCLK:HCLK:PCLK = 1:2:4 */ - /* default FCLK is 120 MHz ! */ - ldr r0, =CLKDIVN - mov r1, #3 - str r1, [r0] - /* END stuff after relocation */ -#endif - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - - -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - mcr p15, 0, r0, c1, c0, 0 - - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - mov ip, lr - bl lowlevel_init - mov lr, ip - mov pc, lr - - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get pc, cpsr - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif diff --git a/cpu/arm925t/Makefile b/cpu/arm925t/Makefile deleted file mode 100644 index a1db818..0000000 --- a/cpu/arm925t/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = interrupts.o cpu.o omap925.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/arm925t/config.mk b/cpu/arm925t/config.mk deleted file mode 100644 index 8db4adb..0000000 --- a/cpu/arm925t/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c deleted file mode 100644 index c1c6b03..0000000 --- a/cpu/arm925t/cpu.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include -#include - -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_WB (1<<3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - DECLARE_GLOBAL_DATA_PTR; - - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - unsigned long i; - - disable_interrupts (); - - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/interrupts.c deleted file mode 100644 index 57bb4ea..0000000 --- a/cpu/arm925t/interrupts.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include - -#define TIMER_LOAD_VAL 0xffffffff - -/* macro to read the 32 bit timer */ -#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8)) - -#ifdef CONFIG_USE_IRQ -/* enable IRQ interrupts */ -void enable_interrupts (void) -{ - unsigned long temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); -} - - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ - unsigned long old,temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); - return (old & 0x80) == 0; -} -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32", - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -static ulong timestamp; -static ulong lastdec; - -/* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init (void) -{ - int32_t val; - - /* Start the decrementer ticking down from 0xffffffff */ - *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; - val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT); - *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val; - - /* init the timestamp and lastdec value */ - reset_timer_masked(); - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -/* delay x useconds AND preserve advance timestamp value */ -void udelay (unsigned long usec) -{ - ulong tmo, tmp; - - if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - }else{ /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; - tmo /= (1000*1000); - } - - tmp = get_timer (0); /* get current timestamp */ - if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ - reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ - else - tmo += tmp; /* else, set advancing stamp wake up time */ - - while (get_timer_masked () < tmo) /* loop till event */ - /*NOP*/; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; /* capure current decrementer value time */ - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; /* current tick value */ - - if (lastdec >= now) { /* normal mode (non roll) */ - /* normal mode */ - timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ - } else { /* we have overflow of the count down timer */ - /* nts = ts + ld + (TLV - now) - * ts=old stamp, ld=time that passed before passing through -1 - * (TLV-now) amount of time after passing though -1 - * nts = new "advancing time stamp"...it could also roll and cause problems. - */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) -{ -#ifdef CONFIG_INNOVATOROMAP1510 - #define LOOPS_PER_MSEC 60 /* tuned on omap1510 */ - volatile int i, time_remaining = LOOPS_PER_MSEC*usec; - for (i=time_remaining; i>0; i--) { } -#else - - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -#endif -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = CFG_HZ; - return tbclk; -} diff --git a/cpu/arm925t/omap925.c b/cpu/arm925t/omap925.c deleted file mode 100644 index ae62656..0000000 --- a/cpu/arm925t/omap925.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -ushort gpioreserved; - -void gpioreserve(ushort mask) -{ - gpioreserved |= mask; -} - -void gpiosetdir(ushort mask, ushort in) -{ - *(ushort *)GPIO_DIR_CONTROL_REG = (*(ushort *)GPIO_DIR_CONTROL_REG & ~mask) | (in & mask); -} - - -void gpiosetout(ushort mask, ushort out) -{ - ushort *r_ptr, r_val; - - r_ptr = (ushort *)GPIO_DATA_OUTPUT_REG; /* set pointer */ - r_val = *r_ptr & ~mask; /* get previous val, clear bits we want to change */ - r_val |= (out & mask); /* set specified bits in value + plus origional ones */ - *r_ptr = r_val; /* write it out */ -/* - * gcc screwed this one up :(. - * - * *(ushort *)GPIO_DATA_OUTPUT_REG = (*(ushort *)GPIO_DATA_OUTPUT_REG & ~mask) | (out & mask); - */ - -} - -void gpioinit(void) -{ -} - - -#define MIF_CONFIG_REG 0xFFFECC0C -#define FLASH_GLOBAL_CTRL_NWP 1 - -void archflashwp (void *archdata, int wp) -{ - ulong *fgc = (ulong *) MIF_CONFIG_REG; - - if (wp == 1) - *fgc &= ~FLASH_GLOBAL_CTRL_NWP; - else - *fgc |= FLASH_GLOBAL_CTRL_NWP; -} diff --git a/cpu/arm925t/start.S b/cpu/arm925t/start.S deleted file mode 100644 index acd7742..0000000 --- a/cpu/arm925t/start.S +++ /dev/null @@ -1,429 +0,0 @@ -/* - * armboot - Startup Code for ARM925 CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1510 from ARM920 code ------ - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -#if defined(CONFIG_OMAP1510) -#include <./configs/omap1510.h> -#endif - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * Set up 925T mode - */ - mov r1, #0x81 /* Set ARM925T configuration. */ - mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */ - - /* - * turn off the watchdog, unlock/diable sequence - */ - mov r1, #0xF5 - ldr r0, =WDTIM_MODE - strh r1, [r0] - mov r1, #0xA0 - strh r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTMR - default - */ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /* - * wait for dpll to lock - */ - ldr r0, =CK_DPLL1 - mov r1, #0x10 - strh r1, [r0] -poll1: - ldrh r1, [r0] - ands r1, r1, #0x01 - beq poll1 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - -#ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - - -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - mcr p15, 0, r0, c1, c0, 0 - - /* - * Go setup Memory and board specific bits prior to relocation. - */ - mov ip, lr /* perserve link reg across call */ - bl lowlevel_init /* go setup pll,mux,memory */ - mov lr, ip /* restore link */ - mov pc, lr /* back to my caller */ -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x3 /* dsp_en + arm_rst = global reset */ - strh r3, [r1] /* force reset */ - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl1: - .word 0xfffece10 diff --git a/cpu/arm926ejs/.depend b/cpu/arm926ejs/.depend new file mode 100644 index 0000000..e356412 --- /dev/null +++ b/cpu/arm926ejs/.depend @@ -0,0 +1,79 @@ +start.o: start.S \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/arm926ejs.h diff --git a/cpu/arm926ejs/Makefile b/cpu/arm926ejs/Makefile index 203278e..eff665c 100644 --- a/cpu/arm926ejs/Makefile +++ b/cpu/arm926ejs/Makefile @@ -22,6 +22,7 @@ # include $(TOPDIR)/config.mk +include $(TOPDIR)/board/mv_feroceon/$(BOARD)/mvRules.mk LIB = lib$(CPU).a diff --git a/cpu/arm926ejs/config.mk b/cpu/arm926ejs/config.mk index 8db4adb..1e6e113 100644 --- a/cpu/arm926ejs/config.mk +++ b/cpu/arm926ejs/config.mk @@ -21,14 +21,19 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float -PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +ifeq ($(CROSS_COMPILE),arm-linux-) + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -mshort-load-bytes -msoft-float + +PLATFORM_CPPFLAGS += -mapcs-32 -march=armv5 + +else + +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv5t + +endif diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c index f57c5a5..b7956d9 100644 --- a/cpu/arm926ejs/cpu.c +++ b/cpu/arm926ejs/cpu.c @@ -28,7 +28,6 @@ /* * CPU specific code */ - #include #include #include @@ -43,6 +42,7 @@ static unsigned long read_p15_c1 (void) : "=r" (value) : : "memory"); + __asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop"); #ifdef MMU_DEBUG printf ("p15/c1 is = %08lx\n", value); @@ -112,20 +112,54 @@ int cleanup_before_linux (void) disable_interrupts (); +#ifdef CONFIG_MARVELL + /* turn off L2 Cache */ + asm ("mrc p15, 1, %0, c15, c1, 0":"=r" (i)); + i &= ~0x00400000; + asm ("mcr p15, 1, %0, c15, c1, 0": :"r" (i)); + __asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop"); + /* Clean L2 Cache */ + asm ("mcr p15, 1, %0, c15, c9, 0": :"r" (i)); + __asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop"); + /* Drain write buffer */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); + __asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop"); +#endif + /* turn off I/D-cache */ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + __asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop"); i &= ~(C1_DC | C1_IC); asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + - /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + + /* Check if we are 926 or 946 */ + asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (i)); + __asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop"); + + + if (((i >> 4)&0xfff) == 0x926) + { + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + } + else + { + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); + } return (0); } int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + extern void reset_cpu (ulong addr); + disable_interrupts (); reset_cpu (0); /*NOTREACHED*/ @@ -149,6 +183,21 @@ void icache_disable (void) cp_delay (); write_p15_c1 (reg & ~C1_IC); } +void dcache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + reg &= ~C1_DC; + write_p15_c1 (reg); + +} +int dcache_status (void) +{ + return (read_p15_c1 () & C1_DC) != 0; +} + int icache_status (void) { diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c index 0457bff..d282056 100644 --- a/cpu/arm926ejs/interrupts.c +++ b/cpu/arm926ejs/interrupts.c @@ -39,15 +39,29 @@ #include #include +extern void reset_cpu(ulong addr); #define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ #ifdef CONFIG_OMAP #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8)) #endif +#ifdef CONFIG_INTEGRATOR +#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4)) +#endif #ifdef CONFIG_VERSATILE #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4)) #endif +#ifdef CONFIG_MARVELL +#include "cntmr/mvCntmr.h" +#define READ_TIMER (mvCntmrRead(UBOOT_CNTR)/(mvTclkGet()/1000)) +#endif + +#if defined(MV78XX0) + extern unsigned int whoAmI(void); +#else + #define whoAmI() 0 +#endif #ifdef CONFIG_USE_IRQ /* enable IRQ interrupts */ @@ -182,14 +196,9 @@ void do_irq (struct pt_regs *pt_regs) bad_mode (); } -#ifdef CONFIG_INTEGRATOR - /* Timer functionality supplied by Integrator board (AP or CP) */ - -#else - -static ulong timestamp; -static ulong lastdec; +static ulong timestamp[2]; +static ulong lastdec[2]; /* nothing really to do with interrupts, just starts up a counter. */ int interrupt_init (void) @@ -202,7 +211,20 @@ int interrupt_init (void) val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT); *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val; #endif /* CONFIG_OMAP */ +#ifdef CONFIG_INTEGRATOR + /* Load timer with initial value */ + *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL; + /* Set timer to be enabled, free-running, no interrupts, 256 divider */ + *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C; +#endif /* CONFIG_INTEGRATOR */ +#ifdef CONFIG_MARVELL + /* init the counter */ + MV_CNTMR_CTRL cntmr; + cntmr.enable = 1; + cntmr.autoEnable = 1; + mvCntmrStart(UBOOT_CNTR, TIMER_LOAD_VAL, &cntmr); +#endif /* #ifdef CONFIG_MARVELL */ #ifdef CONFIG_VERSATILE *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD; /* TimerLoad */ *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; /* TimerValue */ @@ -231,15 +253,19 @@ ulong get_timer (ulong base) void set_timer (ulong t) { - timestamp = t; + timestamp[whoAmI()] = t; } /* delay x useconds AND perserve advance timstamp value */ +#ifndef CONFIG_MARVELL void udelay (unsigned long usec) { ulong tmo, tmp; - - if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ + if(usec >= 1000000){ /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + + }else if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ @@ -257,32 +283,52 @@ void udelay (unsigned long usec) while (get_timer_masked () < tmo)/* loop till event */ /*NOP*/; } +#else +void udelay (unsigned long usec) +{ + uint current; + ulong delayticks; + + current = mvCntmrRead(UBOOT_CNTR); + delayticks = (usec * (mvTclkGet()/ 1000000)); + if(current < delayticks) + { + delayticks -= current; + while(mvCntmrRead(UBOOT_CNTR) < current); + while((TIMER_LOAD_VAL - delayticks) < mvCntmrRead(UBOOT_CNTR)); + } + else + { + while(mvCntmrRead(UBOOT_CNTR) > (current-delayticks)); + } +} +#endif void reset_timer_masked (void) { /* reset time */ - lastdec = READ_TIMER; /* capure current decrementer value time */ - timestamp = 0; /* start "advancing" time stamp from 0 */ + lastdec[whoAmI()] = READ_TIMER; /* capure current decrementer value time */ + timestamp[whoAmI()] = 0; /* start "advancing" time stamp from 0 */ } ulong get_timer_masked (void) { ulong now = READ_TIMER; /* current tick value */ - if (lastdec >= now) { /* normal mode (non roll) */ + if (lastdec[whoAmI()] >= now) { /* normal mode (non roll) */ /* normal mode */ - timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + timestamp[whoAmI()] += lastdec[whoAmI()] - now; /* move stamp fordward with absoulte diff ticks */ } else { /* we have overflow of the count down timer */ /* nts = ts + ld + (TLV - now) * ts=old stamp, ld=time that passed before passing through -1 * (TLV-now) amount of time after passing though -1 * nts = new "advancing time stamp"...it could also roll and cause problems. */ - timestamp += lastdec + TIMER_LOAD_VAL - now; + timestamp[whoAmI()]+= lastdec[whoAmI()] + (TIMER_LOAD_VAL/(mvTclkGet()/1000))- now; } - lastdec = now; + lastdec[whoAmI()] = now; - return timestamp; + return timestamp[whoAmI()]; } /* waits specified delay value and resets timestamp */ @@ -330,4 +376,3 @@ ulong get_tbclk (void) return tbclk; } -#endif /* CONFIG_INTEGRATOR */ diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index fc6b20b..83e1e13 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -3,10 +3,10 @@ * * Copyright (c) 2003 Texas Instruments * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * ----- Adapted for OMAP1610 from ARM925t code ------ * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke * Copyright (c) 2002 Gary Jennejohn * Copyright (c) 2003 Richard Woodruff * Copyright (c) 2003 Kshitij @@ -90,7 +90,7 @@ _fiq: * ************************************************************************* */ - +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE @@ -134,6 +134,65 @@ reset: bic r0,r0,#0x1f orr r0,r0,#0xd3 msr cpsr,r0 +#if defined(MV_88F6183) + /* Start of SPI errata change */ + + /* + * set the cpu to SVC32 mode, I and F disabled. + */ + mov r1, #0xd3 + msr cpsr,r1 + +/* Add for load code into I cache */ + mvn r5, #0xff + and r4, r4, r5 + + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000007 /* 2:0 (CAM) */ + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00001000 /* Enabled I-cache */ + mcr p15, 0, r0, c1, c0, 0 + + /* Add nop commands for cache flush operations */ + nop + nop + nop + /* here. MUST BE IN THE SAME CACHE LINE */ + + /* lock I-Cache */ + mrc p15, 0, r8, c9, c0, 1 + orr r8, r8, #0xf + mcr p15, 0, r8, c9, c0, 1 + + /* Load source code from 0xfff90000-0xfff94000 */ + mov r8, #0 + mov r0, #0xff /* U-boot base address on flash */ + orr r8, r8, r0, LSL #24 + mov r0, #0xf9 /* U-boot base address on flash */ + orr r8, r8, r0, LSL #16 + mov r2, #0x5000 /* U-boot size of code in reset vector */ + + /* Load code into I Cache */ +load_loop1: + mcr p15, 0, r8, c7, c13, 1 + add r8, r8, #32 /* 8 dwords * 4 bytes */ + sub r2, r2, #32 /* 8 dwords * 4 bytes */ + cmp r2, #0 /* check if we have read a full Page */ + bne load_loop1 +/* End of code load */ + /*End of SPI errata change */ +#endif /*MV_88F6183*/ /* * we do sys-critical inits only at reboot, @@ -144,6 +203,15 @@ reset: #endif #ifndef CONFIG_SKIP_RELOCATE_UBOOT +#if defined(CONFIG_MARVELL) && defined(MV78200) && !defined(DUAL_OS_78200) + mov r0, #0 + mrc p15, 1, r0, c15, c1, 0 + /* Check if we are CPU0 or CPU1 */ + and r0, r0, #0x4000 + cmp r0, #0x4000 + beq slave_cpu_relocate +#endif + relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ @@ -165,12 +233,14 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ +#ifndef CONFIG_MARVELL sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ +#endif sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ + sub sp, r0, #16 /* leave 4 words for abort-stack */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ @@ -184,6 +254,19 @@ clbss_l:str r2, [r0] /* clear loop... */ ldr pc, _start_armboot +#if defined(CONFIG_MARVELL) && defined(MV78200) && !defined(DUAL_OS_78200) +/* Dummy relocate code for slave cpu + Create new stack +*/ +slave_cpu_relocate: + /* Set up the stack */ + ldr r0, _TEXT_BASE /* stack from uboot base (6MB) - first CPU (2MB)*/ + sub r0, r0, #CONFIG_STACKSIZE + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub sp, r0, #12 /* leave 3 words for abort-stack */ + ldr pc, _start_armboot +#endif + _start_armboot: .word start_armboot @@ -201,23 +284,75 @@ _start_armboot: cpu_init_crit: + + /* Check if we are 926 or 946 */ + mrc p15, 0, r0, c0, c0, 0 + mov r0, r0, LSR #4 + ldr r1, =0xfff + and r0, r0, r1 + ldr r1, =0x946 + cmp r0, r1 + beq cpu_946 + +cpu_926: +#if !defined(MV78XX0) && !defined(MV_88F6183) /* * flush v4 I/D caches */ mov r0, #0 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ +#endif + b cpu_continue + + +cpu_946: + + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 /* invalidate v4 I-cache */ + mcr p15, 0, r0, c7, c6, 0 /* flush D-Cache */ + + + + + +cpu_continue: /* * disable MMU stuff and caches */ mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ - bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ + bic r0, r0, #0x00000007 /* 2:0 (CAM) */ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ - orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ +#if !defined(MV78XX0) + orr r0, r0, #0x00001000 /* set bit 12 (I-cache) */ +#endif mcr p15, 0, r0, c1, c0, 0 +#if !defined(MV78XX0) + /* + * Initialize Dcache lockdown register for KW A0 only + */ + ldr r1, =(0xd0000000 + 0x40008) + ldr r6, [r1] +#if defined(MV_CPU_BE) + eor temp, r6, r6, ROR #16 ; /*temp = A^C,B^D,C^A,D^B */\ + bic r1, r1, #0xFF0000 ; /*temp = A^C,0 ,C^A,D^B */\ + mov r6, r6, ROR #8 ; /*sr = D ,A ,B ,C */\ + eor r6, r6, r1, LSR #8 /*sr = D ,C ,B ,A */ +#endif + ldr r1, =0x3 /* MV_88F6XXX_A1_REV */ + and r6, r6, #0xff + cmp r1, r6 + bne kw_a1 + mov r0, #0 + mcr p15, 0, r0, c9, c0, 0 +kw_a1: +#endif + /* * Go setup Memory and board specific bits prior to relocation. */ @@ -225,6 +360,69 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ +/* + ************************************************************************* + * + * Flush DCache + * + ************************************************************************* + */ + +.globl _dcache_index_max +_dcache_index_max: + .word 0x0 + +.globl _dcache_index_inc +_dcache_index_inc: + .word 0x0 + +.globl _dcache_set_max +_dcache_set_max: + .word 0x0 + +.globl _dcache_set_index +_dcache_set_index: + .word 0x0 + + +#define s_max r0 +#define s_inc r1 +#define i_max r2 +#define i_inc r3 + +.globl cpu_dcache_flush_all +cpu_dcache_flush_all: + stmdb sp!, {r0-r3,ip} + + ldr i_max, _dcache_index_max + ldr i_inc, _dcache_index_inc + ldr s_max, _dcache_set_max + ldr s_inc, _dcache_set_index + +Lnext_set_inv: + orr ip, s_max, i_max +Lnext_index_inv: + mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */ + sub ip, ip, i_inc + tst ip, i_max /* Index 0 is last one */ + bne Lnext_index_inv /* Next index */ + mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */ + subs s_max, s_max, s_inc + bpl Lnext_set_inv /* Next set */ + ldmia sp!, {r0-r3,ip} + + mov pc, lr /* back to my caller */ + +.globl cpu_icache_flush_invalidate_all +cpu_icache_flush_invalidate_all: + stmdb sp!, {r0} + + ldr r0,=0 + mcr p15, 0, r0, c7, c5, 0 /* Flush Invalidate I caches */ + ldmia sp!, {r0} + + mov pc, lr /* back to my caller */ + /* ************************************************************************* * @@ -272,7 +470,11 @@ cpu_init_crit: stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) +#ifndef CONFIG_MARVELL + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) +#else + sub r2, r2, #CONFIG_STACKSIZE +#endif sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack @ get values for "aborted" pc and cpsr (into parm regs) ldmia r2, {r2 - r3} @@ -306,7 +508,11 @@ cpu_init_crit: .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) +#ifndef CONFIG_MARVELL + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) +#else + sub r13, r13, #CONFIG_STACKSIZE +#endif sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr in position 0 of saved stack @@ -315,6 +521,9 @@ cpu_init_crit: mov r13, #MODE_SVC @ prepare SVC-Mode @ msr spsr_c, r13 msr spsr, r13 @ switch modes, make sure moves will execute +#ifdef CONFIG_MARVELL + ldr r13, _TEXT_BASE +#endif mov lr, pc @ capture return pc movs pc, lr @ jump to next instruction & switch modes. .endm @@ -393,13 +602,15 @@ fiq: #endif -# ifdef CONFIG_INTEGRATOR +#ifdef CONFIG_INTEGRATOR /* Satisfied by Integrator routine (AP or CP) */ #else .align 5 + +#ifndef CONFIG_MARVELL .globl reset_cpu reset_cpu: ldr r1, rstctl1 /* get clkm1 reset ctl */ @@ -412,5 +623,5 @@ _loop_forever: rstctl1: .word 0xfffece10 - +#endif /* CONFIG_MARVELL */ #endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/cpu/arm946es/Makefile b/cpu/arm946es/Makefile deleted file mode 100644 index 203278e..0000000 --- a/cpu/arm946es/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = interrupts.o cpu.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/arm946es/config.mk b/cpu/arm946es/config.mk deleted file mode 100644 index 81ca288..0000000 --- a/cpu/arm946es/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c deleted file mode 100644 index ba0a4e4..0000000 --- a/cpu/arm946es/cpu.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include -#include - -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM946E-S Technical Reference Manual */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ - -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - DECLARE_GLOBAL_DATA_PTR; - - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - unsigned long i; - - disable_interrupts (); - - /* ARM926E-S needs the protection unit enabled for the icache to have - * been enabled - left for possible later use - * should turn off the protection unit as well.... - */ - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - extern void reset_cpu (ulong addr); - - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} -/* ARM926E-S needs the protection unit enabled for this to have any effect - - left for possible later use */ -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} diff --git a/cpu/arm946es/interrupts.c b/cpu/arm946es/interrupts.c index 5728c3a..98f219f 100644 --- a/cpu/arm946es/interrupts.c +++ b/cpu/arm946es/interrupts.c @@ -209,7 +209,6 @@ void set_timer (ulong t) { timestamp = t; } - /* delay x useconds AND perserve advance timstamp value */ void udelay(unsigned long usec) { diff --git a/cpu/arm946es/start.S b/cpu/arm946es/start.S deleted file mode 100644 index e8c908b..0000000 --- a/cpu/arm946es/start.S +++ /dev/null @@ -1,409 +0,0 @@ -/* - * armboot - Startup Code for ARM926EJS CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifdef CONFIG_INIT_CRITICAL - bl cpu_init_crit -#endif - -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - bne clbss_l - - ldr pc, _start_armboot - -_start_armboot: - .word start_armboot - - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - - -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */ - mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ - bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ - orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ - orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ - mcr p15, 0, r0, c1, c0, 0 - - /* - * Go setup Memory and board specific bits prior to relocation. - */ - mov ip, lr /* perserve link reg across call */ - bl lowlevel_init /* go setup memory */ - mov lr, ip /* restore link */ - mov pc, lr /* back to my caller */ -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -# ifdef CONFIG_INTEGRATOR - - /* Satisfied by general board level routine */ - -#else - - .align 5 -.globl reset_cpu -reset_cpu: - - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x0 - strh r3, [r1] /* clear it */ - mov r3, #0x8 - strh r3, [r1] /* force dsp+arm reset */ -_loop_forever: - b _loop_forever - -rstctl1: - .word 0xfffece10 - -#endif /* #ifdef CONFIG_INTEGRATOR */ diff --git a/cpu/arm_intcm/Makefile b/cpu/arm_intcm/Makefile deleted file mode 100644 index 203278e..0000000 --- a/cpu/arm_intcm/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = interrupts.o cpu.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/arm_intcm/config.mk b/cpu/arm_intcm/config.mk deleted file mode 100644 index 81ca288..0000000 --- a/cpu/arm_intcm/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c deleted file mode 100644 index d03b09d..0000000 --- a/cpu/arm_intcm/cpu.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code for an unknown cpu - * - hence fairly empty...... - */ - -#include -#include - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - DECLARE_GLOBAL_DATA_PTR; - - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - disable_interrupts (); - - /* Since the CM has unknown processor we do not support - * cache operations - */ - - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - extern void reset_cpu (ulong addr); - - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -/* May not be cahed processor on the CM - do nothing */ -void icache_enable (void) -{ -} - -void icache_disable (void) -{ -} - -/* return "disabled" */ -int icache_status (void) -{ - return 0; -} diff --git a/cpu/arm_intcm/interrupts.c b/cpu/arm_intcm/interrupts.c deleted file mode 100644 index 1763176..0000000 --- a/cpu/arm_intcm/interrupts.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifndef CONFIG_INTEGRATOR -/* Only to be used for integrator/AP or /CP */ -/* Allows U-Boot to be used with any ARM supplied core module (CM), - * provided the ARM boot monitor, or similar software, - * runs first to set up the platform e.g. map writeable memory to 0x00000000 - * - see Integrator User Guides - * Versatile has a supported cpu - arm926ejs - * Some integrator CMs cpus are supported - * CM926EJ-S, CM946E-S - * For platforms with supported cpus U-Boot can be used as the sole boot - * monitor/loader - it will configure the platform itself - * Also U-Boot may be faster/smaller in those cases since specific - * qualities of the cpu and/or CM can be used e.g i and/or d caches etc. - */ -#endif -extern void reset_cpu(ulong addr); - -#ifdef CONFIG_USE_IRQ -/* enable IRQ interrupts */ -void enable_interrupts (void) -{ - unsigned long temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); -} - - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ - unsigned long old,temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); - return (old & 0x80) == 0; -} -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32", - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -/* The timer functionality is supplied by the Integrator board */ -/* - see board/integrator<>.c */ diff --git a/cpu/arm_intcm/start.S b/cpu/arm_intcm/start.S deleted file mode 100644 index 75fe917..0000000 --- a/cpu/arm_intcm/start.S +++ /dev/null @@ -1,370 +0,0 @@ -/* - * armboot - Startup Code for ARM926EJS CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -/* - ************************************************************************* - * - * Jump vector table - * - ************************************************************************* - */ - -.globl _start -_start: - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: - .word undefined_instruction -_software_interrupt: - .word software_interrupt -_prefetch_abort: - .word prefetch_abort -_data_abort: - .word data_abort -_not_used: - .word not_used -_irq: - .word irq -_fiq: - .word fiq - - .balignl 16,0xdeadbeef - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE /* address of _start in the linked image */ - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - - -/* - * the actual reset code - */ -.globl reset -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifdef CONFIG_INIT_CRITICAL - bl cpu_init_crit -#endif - -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* pc relative address of label */ - ldr r1, _TEXT_BASE /* linked image address of label */ - cmp r0, r1 /* test if we run from flash or RAM */ - beq stack_setup /* ifeq we are in the RAM copy */ - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - - ldr pc, _start_armboot - -_start_armboot: - .word start_armboot - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -cpu_init_crit: - /* arm_int_generic assumes the ARM boot monitor, or user software, - * has initialized the platform - */ - mov pc, lr /* back to my caller */ -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - @ carve out a frame on current user stack - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - - ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - @ get values for "aborted" pc and cpsr (into parm regs) - ldmia r2, {r2 - r3} - add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp @ save current stack into r0 (param register) - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack - - str lr, [r13] @ save caller lr in position 0 of saved stack - mrs lr, spsr @ get the spsr - str lr, [r13, #4] @ save spsr in position 1 of saved stack - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 @ switch modes, make sure moves will execute - mov lr, pc @ capture return pc - movs pc, lr @ jump to next instruction & switch modes. - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -.globl undefined_instruction -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -.globl software_interrupt -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -.globl prefetch_abort -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -.globl data_abort -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -.globl not_used -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - .align 5 -.globl irq -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -.globl fiq -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -.globl irq -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -.globl fiq -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile deleted file mode 100644 index c44412a..0000000 --- a/cpu/i386/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2002 -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o start16.o reset.o -COBJS = serial.o interrupts.o cpu.o timer.o sc520.o -AOBJS = sc520_asm.o - -all: .depend $(START) $(LIB) - -$(LIB): $(COBJS) $(AOBJS) - $(AR) crv $@ $(COBJS) $(AOBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(COBJS:.o=.c) $(AOBJS:.o=.S) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) $(AOBJS:.o=.S) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/i386/config.mk b/cpu/i386/config.mk deleted file mode 100644 index 16a160d..0000000 --- a/cpu/i386/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2002 -# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += - -PLATFORM_CPPFLAGS += -march=i386 -Werror diff --git a/cpu/i386/cpu.c b/cpu/i386/cpu.c deleted file mode 100644 index 5fd37c7..0000000 --- a/cpu/i386/cpu.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include - -int cpu_init(void) -{ - /* initialize FPU, reset EM, set MP and NE */ - asm ("fninit\n" \ - "movl %cr0, %eax\n" \ - "andl $~0x4, %eax\n" \ - "orl $0x22, %eax\n" \ - "movl %eax, %cr0\n" ); - - return 0; -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf ("resetting ...\n"); - udelay(50000); /* wait 50 ms */ - disable_interrupts(); - reset_cpu(0); - - /*NOTREACHED*/ - return 0; -} - -void flush_cache (unsigned long dummy1, unsigned long dummy2) -{ - asm("wbinvd\n"); - return; -} diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c deleted file mode 100644 index f340119..0000000 --- a/cpu/i386/interrupts.c +++ /dev/null @@ -1,525 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - - -struct idt_entry { - u16 base_low; - u16 selector; - u8 res; - u8 access; - u16 base_high; -} __attribute__ ((packed)); - - -struct idt_entry idt[256]; - - -#define MAX_IRQ 16 - -typedef struct irq_handler { - struct irq_handler *next; - interrupt_handler_t* isr_func; - void *isr_data; -} irq_handler_t; - -#define IRQ_DISABLED 1 - -typedef struct { - irq_handler_t *handler; - unsigned long status; -} irq_desc_t; - -static irq_desc_t irq_table[MAX_IRQ]; - -asm ("irq_return:\n" - " addl $4, %esp\n" - " popa\n" - " iret\n"); - -asm ("exp_return:\n" - " addl $12, %esp\n" - " pop %esp\n" - " popa\n" - " iret\n"); - -char exception_stack[4096]; - -#define DECLARE_INTERRUPT(x) \ - asm(".globl irq_"#x"\n" \ - "irq_"#x":\n" \ - "pusha \n" \ - "pushl $"#x"\n" \ - "pushl $irq_return\n" \ - "jmp do_irq\n"); \ - void __attribute__ ((regparm(0))) irq_##x(void) - -#define DECLARE_EXCEPTION(x, f) \ - asm(".globl exp_"#x"\n" \ - "exp_"#x":\n" \ - "pusha \n" \ - "movl %esp, %ebx\n" \ - "movl $exception_stack, %eax\n" \ - "movl %eax, %esp \n" \ - "pushl %ebx\n" \ - "movl 32(%esp), %ebx\n" \ - "xorl %edx, %edx\n" \ - "movw 36(%esp), %dx\n" \ - "pushl %edx\n" \ - "pushl %ebx\n" \ - "pushl $"#x"\n" \ - "pushl $exp_return\n" \ - "jmp "#f"\n"); \ - void __attribute__ ((regparm(0))) exp_##x(void) - -DECLARE_EXCEPTION(0, divide_exception_entry); /* Divide exception */ -DECLARE_EXCEPTION(1, debug_exception_entry); /* Debug exception */ -DECLARE_EXCEPTION(2, nmi_entry); /* NMI */ -DECLARE_EXCEPTION(3, unknown_exception_entry); /* Breakpoint/Coprocessor Error */ -DECLARE_EXCEPTION(4, unknown_exception_entry); /* Overflow */ -DECLARE_EXCEPTION(5, unknown_exception_entry); /* Bounds */ -DECLARE_EXCEPTION(6, invalid_instruction_entry); /* Invalid instruction */ -DECLARE_EXCEPTION(7, unknown_exception_entry); /* Device not present */ -DECLARE_EXCEPTION(8, double_fault_entry); /* Double fault */ -DECLARE_EXCEPTION(9, unknown_exception_entry); /* Co-processor segment overrun */ -DECLARE_EXCEPTION(10, invalid_tss_exception_entry);/* Invalid TSS */ -DECLARE_EXCEPTION(11, seg_fault_entry); /* Segment not present */ -DECLARE_EXCEPTION(12, stack_fault_entry); /* Stack overflow */ -DECLARE_EXCEPTION(13, gpf_entry); /* GPF */ -DECLARE_EXCEPTION(14, page_fault_entry); /* PF */ -DECLARE_EXCEPTION(15, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(16, fp_exception_entry); /* Floating point */ -DECLARE_EXCEPTION(17, alignment_check_entry); /* alignment check */ -DECLARE_EXCEPTION(18, machine_check_entry); /* machine check */ -DECLARE_EXCEPTION(19, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(20, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(21, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(22, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(23, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(24, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(25, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(26, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(27, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(28, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(29, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(30, unknown_exception_entry); /* Reserved */ -DECLARE_EXCEPTION(31, unknown_exception_entry); /* Reserved */ - -DECLARE_INTERRUPT(0); -DECLARE_INTERRUPT(1); -DECLARE_INTERRUPT(3); -DECLARE_INTERRUPT(4); -DECLARE_INTERRUPT(5); -DECLARE_INTERRUPT(6); -DECLARE_INTERRUPT(7); -DECLARE_INTERRUPT(8); -DECLARE_INTERRUPT(9); -DECLARE_INTERRUPT(10); -DECLARE_INTERRUPT(11); -DECLARE_INTERRUPT(12); -DECLARE_INTERRUPT(13); -DECLARE_INTERRUPT(14); -DECLARE_INTERRUPT(15); - -void __attribute__ ((regparm(0))) default_isr(void); -asm ("default_isr: iret\n"); - -void disable_irq(int irq) -{ - if (irq >= MAX_IRQ) { - return; - } - irq_table[irq].status |= IRQ_DISABLED; - -} - -void enable_irq(int irq) -{ - if (irq >= MAX_IRQ) { - return; - } - irq_table[irq].status &= ~IRQ_DISABLED; -} - -/* masks one specific IRQ in the PIC */ -static void unmask_irq(int irq) -{ - int imr_port; - - if (irq >= MAX_IRQ) { - return; - } - if (irq > 7) { - imr_port = SLAVE_PIC + IMR; - } else { - imr_port = MASTER_PIC + IMR; - } - - outb(inb(imr_port)&~(1<<(irq&7)), imr_port); -} - - -/* unmasks one specific IRQ in the PIC */ -static void mask_irq(int irq) -{ - int imr_port; - - if (irq >= MAX_IRQ) { - return; - } - if (irq > 7) { - imr_port = SLAVE_PIC + IMR; - } else { - imr_port = MASTER_PIC + IMR; - } - - outb(inb(imr_port)|(1<<(irq&7)), imr_port); -} - - -/* issue a Specific End Of Interrupt instruciton */ -static void specific_eoi(int irq) -{ - /* If it is on the slave PIC this have to be performed on - * both the master and the slave PICs */ - if (irq > 7) { - outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2); - irq = SEOI_IR2; /* also do IR2 on master */ - } - outb(OCW2_SEOI|irq, MASTER_PIC + OCW2); -} - -void __attribute__ ((regparm(0))) do_irq(int irq) -{ - - mask_irq(irq); - - if (irq_table[irq].status & IRQ_DISABLED) { - unmask_irq(irq); - specific_eoi(irq); - return; - } - - - if (NULL != irq_table[irq].handler) { - irq_handler_t *handler; - for (handler = irq_table[irq].handler; - NULL!= handler; handler = handler->next) { - handler->isr_func(handler->isr_data); - } - } else { - if ((irq & 7) != 7) { - printf("Spurious irq %d\n", irq); - } - } - unmask_irq(irq); - specific_eoi(irq); -} - - -void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg) -{ - printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip); -} - -void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg) -{ - printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg) -{ - printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg) -{ - printf("NMI Interrupt at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg) -{ - printf("Invalid Instruction at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg) -{ - printf("Double fault at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg) -{ - printf("Invalid TSS at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg) -{ - printf("Segmentation fault at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg) -{ - printf("Stack fault at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg) -{ - printf("General protection fault at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg) -{ - printf("Page fault at %04x:%08x\n", seg, ip); - while(1); -} - -void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg) -{ - printf("Floating point exception at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg) -{ - printf("Alignment check at %04x:%08x\n", seg, ip); -} - -void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg) -{ - printf("Machine check exception at %04x:%08x\n", seg, ip); -} - - -void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata) -{ - int status; - - if (ino>MAX_IRQ) { - return; - } - - if (NULL != irq_table[ino].handler) { - return; - } - - status = disable_interrupts(); - irq_table[ino].handler = malloc(sizeof(irq_handler_t)); - if (NULL == irq_table[ino].handler) { - return; - } - - memset(irq_table[ino].handler, 0, sizeof(irq_handler_t)); - - irq_table[ino].handler->isr_func = func; - irq_table[ino].handler->isr_data = pdata; - if (status) { - enable_interrupts(); - } - - unmask_irq(ino); - - return; -} - -void irq_free_handler(int ino) -{ - int status; - if (ino>MAX_IRQ) { - return; - } - - status = disable_interrupts(); - mask_irq(ino); - if (NULL == irq_table[ino].handler) { - return; - } - free(irq_table[ino].handler); - irq_table[ino].handler=NULL; - if (status) { - enable_interrupts(); - } - return; -} - - -asm ("idt_ptr:\n" - ".word 0x800\n" /* size of the table 8*256 bytes */ - ".long idt\n" /* offset */ - ".word 0x18\n");/* data segment */ - -static void set_vector(int intnum, void *routine) -{ - idt[intnum].base_high = (u16)((u32)(routine)>>16); - idt[intnum].base_low = (u16)((u32)(routine)&0xffff); -} - - -int interrupt_init(void) -{ - int i; - - /* Just in case... */ - disable_interrupts(); - - /* Initialize the IDT and stuff */ - - - memset(irq_table, 0, sizeof(irq_table)); - - /* Setup the IDT */ - for (i=0;i<256;i++) { - idt[i].access = 0x8e; - idt[i].res = 0; - idt[i].selector = 0x10; - set_vector(i, default_isr); - } - - asm ("cs lidt idt_ptr\n"); - - /* Setup exceptions */ - set_vector(0x00, exp_0); - set_vector(0x01, exp_1); - set_vector(0x02, exp_2); - set_vector(0x03, exp_3); - set_vector(0x04, exp_4); - set_vector(0x05, exp_5); - set_vector(0x06, exp_6); - set_vector(0x07, exp_7); - set_vector(0x08, exp_8); - set_vector(0x09, exp_9); - set_vector(0x0a, exp_10); - set_vector(0x0b, exp_11); - set_vector(0x0c, exp_12); - set_vector(0x0d, exp_13); - set_vector(0x0e, exp_14); - set_vector(0x0f, exp_15); - set_vector(0x10, exp_16); - set_vector(0x11, exp_17); - set_vector(0x12, exp_18); - set_vector(0x13, exp_19); - set_vector(0x14, exp_20); - set_vector(0x15, exp_21); - set_vector(0x16, exp_22); - set_vector(0x17, exp_23); - set_vector(0x18, exp_24); - set_vector(0x19, exp_25); - set_vector(0x1a, exp_26); - set_vector(0x1b, exp_27); - set_vector(0x1c, exp_28); - set_vector(0x1d, exp_29); - set_vector(0x1e, exp_30); - set_vector(0x1f, exp_31); - - - /* Setup interrupts */ - set_vector(0x20, irq_0); - set_vector(0x21, irq_1); - set_vector(0x23, irq_3); - set_vector(0x24, irq_4); - set_vector(0x25, irq_5); - set_vector(0x26, irq_6); - set_vector(0x27, irq_7); - set_vector(0x28, irq_8); - set_vector(0x29, irq_9); - set_vector(0x2a, irq_10); - set_vector(0x2b, irq_11); - set_vector(0x2c, irq_12); - set_vector(0x2d, irq_13); - set_vector(0x2e, irq_14); - set_vector(0x2f, irq_15); - /* vectors 0x30-0x3f are reserved for irq 16-31 */ - - - /* Mask all interrupts */ - outb(0xff, MASTER_PIC + IMR); - outb(0xff, SLAVE_PIC + IMR); - - /* Master PIC */ - outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1); - outb(0x20, MASTER_PIC + ICW2); /* Place master PIC interrupts at INT20 */ - outb(IR2, MASTER_PIC + ICW3); /* ICW3, One slevc PIC is present */ - outb(ICW4_PM, MASTER_PIC + ICW4); - - for (i=0;i<8;i++) { - outb(OCW2_SEOI|i, MASTER_PIC + OCW2); - } - - /* Slave PIC */ - outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1); - outb(0x28, SLAVE_PIC + ICW2); /* Place slave PIC interrupts at INT28 */ - outb(0x02, SLAVE_PIC + ICW3); /* Slave ID */ - outb(ICW4_PM, SLAVE_PIC + ICW4); - - for (i=0;i<8;i++) { - outb(OCW2_SEOI|i, SLAVE_PIC + OCW2); - } - - - /* enable cascade interrerupt */ - outb(0xfb, MASTER_PIC + IMR); - outb(0xff, SLAVE_PIC + IMR); - - /* It is now safe to enable interrupts */ - enable_interrupts(); - - return 0; -} - -void enable_interrupts(void) -{ - asm("sti\n"); -} - -int disable_interrupts(void) -{ - long flags; - - asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : ); - - return (flags&0x200); /* IE flags is bit 9 */ -} - - -#ifdef CFG_RESET_GENERIC - -void __attribute__ ((regparm(0))) generate_gpf(void); -asm(".globl generate_gpf\n" - "generate_gpf:\n" - "ljmp $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not - * exist */ -void reset_cpu(ulong addr) -{ - set_vector(13, generate_gpf); /* general protection fault handler */ - set_vector(8, generate_gpf); /* double fault handler */ - generate_gpf(); /* start the show */ -} -#endif diff --git a/cpu/i386/reset.S b/cpu/i386/reset.S deleted file mode 100644 index 07a7384..0000000 --- a/cpu/i386/reset.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * U-boot - i386 Startup Code - * - * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Reset vector, jumps to start16.S */ - -.extern start16 - -.section .reset, "ax" -.code16 -reset_vector: - cli - cld - jmp start16 - - .org 0xf - nop diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c deleted file mode 100644 index 689e775..0000000 --- a/cpu/i386/sc520.c +++ /dev/null @@ -1,501 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* stuff specific for the sc520, - * but idependent of implementation */ - -#include - -#ifdef CONFIG_SC520 - -#include -#include -#include -#include -#include -#include -#include - -/* - * utility functions for boards based on the AMD sc520 - * - * void write_mmcr_byte(u16 mmcr, u8 data) - * void write_mmcr_word(u16 mmcr, u16 data) - * void write_mmcr_long(u16 mmcr, u32 data) - * - * u8 read_mmcr_byte(u16 mmcr) - * u16 read_mmcr_word(u16 mmcr) - * u32 read_mmcr_long(u16 mmcr) - * - * void init_sc520(void) - * unsigned long init_sc520_dram(void) - * void pci_sc520_init(struct pci_controller *hose) - * - * void reset_timer(void) - * ulong get_timer(ulong base) - * void set_timer(ulong t) - * void udelay(unsigned long usec) - * - */ - -static u32 mmcr_base= 0xfffef000; - -void write_mmcr_byte(u16 mmcr, u8 data) -{ - writeb(data, mmcr+mmcr_base); -} - -void write_mmcr_word(u16 mmcr, u16 data) -{ - writew(data, mmcr+mmcr_base); -} - -void write_mmcr_long(u16 mmcr, u32 data) -{ - writel(data, mmcr+mmcr_base); -} - -u8 read_mmcr_byte(u16 mmcr) -{ - return readb(mmcr+mmcr_base); -} - -u16 read_mmcr_word(u16 mmcr) -{ - return readw(mmcr+mmcr_base); -} - -u32 read_mmcr_long(u16 mmcr) -{ - return readl(mmcr+mmcr_base); -} - - -void init_sc520(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Set the UARTxCTL register at it's slower, - * baud clock giving us a 1.8432 MHz reference - */ - write_mmcr_byte(SC520_UART1CTL, 7); - write_mmcr_byte(SC520_UART2CTL, 7); - - /* first set the timer pin mapping */ - write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */ - - /* enable PCI bus arbitrer */ - write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */ - - write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */ - write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */ - - - if (CFG_SC520_HIGH_SPEED) { - write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */ - gd->cpu_clk = 133000000; - printf("## CPU Speed set to 133MHz\n"); - } else { - write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */ - printf("## CPU Speed set to 100MHz\n"); - gd->cpu_clk = 100000000; - } - - - /* wait at least one millisecond */ - asm("movl $0x2000,%%ecx\n" - "wait_loop: pushl %%ecx\n" - "popl %%ecx\n" - "loop wait_loop\n": : : "ecx"); - - /* turn on the SDRAM write buffer */ - write_mmcr_byte(SC520_DBCTL, 0x11); - - /* turn on the cache and disable write through */ - asm("movl %%cr0, %%eax\n" - "andl $0x9fffffff, %%eax\n" - "movl %%eax, %%cr0\n" : : : "eax"); -} - -unsigned long init_sc520_dram(void) -{ - DECLARE_GLOBAL_DATA_PTR; - bd_t *bd = gd->bd; - - u32 dram_present=0; - u32 dram_ctrl; - - int val; - - int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY; - int refresh_rate = CFG_SDRAM_REFRESH_RATE; - int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY; - - /* set SDRAM speed here */ - - refresh_rate/=78; - if (refresh_rate<=1) { - val = 0; /* 7.8us */ - } else if (refresh_rate==2) { - val = 1; /* 15.6us */ - } else if (refresh_rate==3 || refresh_rate==4) { - val = 2; /* 31.2us */ - } else { - val = 3; /* 62.4us */ - } - write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4)); - - val = read_mmcr_byte(SC520_DRCTMCTL); - val &= 0xf0; - - if (cas_precharge_delay==3) { - val |= 0x04; /* 3T */ - } else if (cas_precharge_delay==4) { - val |= 0x08; /* 4T */ - } else if (cas_precharge_delay>4) { - val |= 0x0c; - } - - if (ras_cas_delay > 3) { - val |= 2; - } else { - val |= 1; - } - write_mmcr_byte(SC520_DRCTMCTL, val); - - - /* We read-back the configuration of the dram - * controller that the assembly code wrote */ - dram_ctrl = read_mmcr_long(SC520_DRCBENDADR); - - - bd->bi_dram[0].start = 0; - if (dram_ctrl & 0x80) { - /* bank 0 enabled */ - dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22; - bd->bi_dram[0].size = bd->bi_dram[1].start; - - } else { - bd->bi_dram[0].size = 0; - bd->bi_dram[1].start = bd->bi_dram[0].start; - } - - if (dram_ctrl & 0x8000) { - /* bank 1 enabled */ - dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14; - bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start; - } else { - bd->bi_dram[1].size = 0; - bd->bi_dram[2].start = bd->bi_dram[1].start; - } - - if (dram_ctrl & 0x800000) { - /* bank 2 enabled */ - dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6; - bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start; - } else { - bd->bi_dram[2].size = 0; - bd->bi_dram[3].start = bd->bi_dram[2].start; - } - - if (dram_ctrl & 0x80000000) { - /* bank 3 enabled */ - dram_present = (dram_ctrl & 0x7f000000) >> 2; - bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start; - } else { - bd->bi_dram[3].size = 0; - } - - -#if 0 - printf("Configured %d bytes of dram\n", dram_present); -#endif - gd->ram_size = dram_present; - - return dram_present; -} - - -#ifdef CONFIG_PCI - - -static struct { - u8 priority; - u16 level_reg; - u8 level_bit; -} sc520_irq[] = { - { SC520_IRQ0, SC520_MPICMODE, 0x01 }, - { SC520_IRQ1, SC520_MPICMODE, 0x02 }, - { SC520_IRQ2, SC520_SL1PICMODE, 0x02 }, - { SC520_IRQ3, SC520_MPICMODE, 0x08 }, - { SC520_IRQ4, SC520_MPICMODE, 0x10 }, - { SC520_IRQ5, SC520_MPICMODE, 0x20 }, - { SC520_IRQ6, SC520_MPICMODE, 0x40 }, - { SC520_IRQ7, SC520_MPICMODE, 0x80 }, - - { SC520_IRQ8, SC520_SL1PICMODE, 0x01 }, - { SC520_IRQ9, SC520_SL1PICMODE, 0x02 }, - { SC520_IRQ10, SC520_SL1PICMODE, 0x04 }, - { SC520_IRQ11, SC520_SL1PICMODE, 0x08 }, - { SC520_IRQ12, SC520_SL1PICMODE, 0x10 }, - { SC520_IRQ13, SC520_SL1PICMODE, 0x20 }, - { SC520_IRQ14, SC520_SL1PICMODE, 0x40 }, - { SC520_IRQ15, SC520_SL1PICMODE, 0x80 } -}; - - -/* The interrupt used for PCI INTA-INTD */ -int sc520_pci_ints[15] = { - -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1 -}; - -/* utility function to configure a pci interrupt */ -int pci_sc520_set_irq(int pci_pin, int irq) -{ - int i; - -# if 0 - printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); -#endif - if (irq < 0 || irq > 15) { - return -1; /* illegal irq */ - } - - if (pci_pin < 0 || pci_pin > 15) { - return -1; /* illegal pci int pin */ - } - - /* first disable any non-pci interrupt source that use - * this level */ - for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) { - if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) { - continue; - } - if (read_mmcr_byte(i) == sc520_irq[irq].priority) { - write_mmcr_byte(i, SC520_IRQ_DISABLED); - } - } - - /* Set the trigger to level */ - write_mmcr_byte(sc520_irq[irq].level_reg, - read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit); - - - if (pci_pin < 4) { - /* PCI INTA-INTD */ - /* route the interrupt */ - write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority); - - - } else { - /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ - write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority); - - /* also set the polarity in this case */ - write_mmcr_word(SC520_INTPINPOL, - read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4))); - - } - - /* register the pin */ - sc520_pci_ints[pci_pin] = irq; - - - return 0; /* OK */ -} - -void pci_sc520_init(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - SC520_PCI_MEMORY_BUS, - SC520_PCI_MEMORY_PHYS, - SC520_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - SC520_PCI_MEM_BUS, - SC520_PCI_MEM_PHYS, - SC520_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - SC520_ISA_MEM_BUS, - SC520_ISA_MEM_PHYS, - SC520_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - SC520_PCI_IO_BUS, - SC520_PCI_IO_PHYS, - SC520_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - SC520_ISA_IO_BUS, - SC520_ISA_IO_PHYS, - SC520_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; - - pci_setup_type1(hose, - SC520_REG_ADDR, - SC520_REG_DATA); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - - /* enable target memory acceses on host brige */ - pci_write_config_word(0, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - -} - - -#endif - -#ifdef CFG_TIMER_SC520 - - -void reset_timer(void) -{ - write_mmcr_word(SC520_GPTMR0CNT, 0); - write_mmcr_word(SC520_GPTMR0CTL, 0x6001); - -} - -ulong get_timer(ulong base) -{ - /* fixme: 30 or 33 */ - return read_mmcr_word(SC520_GPTMR0CNT) / 33; -} - -void set_timer(ulong t) -{ - /* FixMe: use two cascade coupled timers */ - write_mmcr_word(SC520_GPTMR0CTL, 0x4001); - write_mmcr_word(SC520_GPTMR0CNT, t*33); - write_mmcr_word(SC520_GPTMR0CTL, 0x6001); -} - - -void udelay(unsigned long usec) -{ - int m=0; - long u; - - read_mmcr_word(SC520_SWTMRMILLI); - read_mmcr_word(SC520_SWTMRMICRO); - -#if 0 - /* do not enable this line, udelay is used in the serial driver -> recursion */ - printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu); -#endif - while (1) { - - m += read_mmcr_word(SC520_SWTMRMILLI); - u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000); - - if (usec <= u) { - break; - } - } -} - -#endif - -int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase) -{ - u8 temp=0; - - if (freq >= 8192) { - temp |= CTL_CLK_SEL_4; - } else if (freq >= 4096) { - temp |= CTL_CLK_SEL_8; - } else if (freq >= 2048) { - temp |= CTL_CLK_SEL_16; - } else if (freq >= 1024) { - temp |= CTL_CLK_SEL_32; - } else if (freq >= 512) { - temp |= CTL_CLK_SEL_64; - } else if (freq >= 256) { - temp |= CTL_CLK_SEL_128; - } else if (freq >= 128) { - temp |= CTL_CLK_SEL_256; - } else { - temp |= CTL_CLK_SEL_512; - } - - if (!lsb_first) { - temp |= MSBF_ENB; - } - - if (inv_clock) { - temp |= CLK_INV_ENB; - } - - if (inv_phase) { - temp |= PHS_INV_ENB; - } - - write_mmcr_byte(SC520_SSICTL, temp); - - return 0; -} - -u8 ssi_txrx_byte(u8 data) -{ - write_mmcr_byte(SC520_SSIXMIT, data); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - return read_mmcr_byte(SC520_SSIRCV); -} - - -void ssi_tx_byte(u8 data) -{ - write_mmcr_byte(SC520_SSIXMIT, data); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT); -} - -u8 ssi_rx_byte(void) -{ - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV); - while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); - return read_mmcr_byte(SC520_SSIRCV); -} - -#endif /* CONFIG_SC520 */ diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S deleted file mode 100644 index 80464fa..0000000 --- a/cpu/i386/sc520_asm.S +++ /dev/null @@ -1,536 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This file is largely based on code obtned from AMD. AMD's original - * copyright is included below - */ - -/* - * ============================================================================= - * - * Copyright 1999 Advanced Micro Devices, Inc. - * - * This software is the property of Advanced Micro Devices, Inc (AMD) which - * specifically grants the user the right to modify, use and distribute this - * software provided this COPYRIGHT NOTICE is not removed or altered. All - * other rights are reserved by AMD. - * - * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY - * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF - * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE. - * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS - * INTERRUPTION, LOSS OF INFORMAITON) ARISING OUT OF THE USE OF OR INABILITY - * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR - * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE - * LIMITATION MAY NOT APPLY TO YOU. - * - * AMD does not assume any responsibility for any errors that may appear in - * the Materials nor any responsibility to support or update the Materials. - * AMD retains the right to make changes to its test specifications at any - * time, without notice. - * - * So that all may benefit from your experience, please report any problems - * or suggestions about this software back to AMD. Please include your name, - * company, telephone number, AMD product requiring support and question or - * problem encountered. - * - * Advanced Micro Devices, Inc. Worldwide support and contact - * Embedded Processor Division information available at: - * Systems Engineering epd.support@amd.com - * 5204 E. Ben White Blvd. -or- - * Austin, TX 78741 http://www.amd.com/html/support/techsup.html - * ============================================================================ - */ - - -/******************************************************************************* - * AUTHOR : Buddy Fey - Original. - ******************************************************************************* - */ - - -/******************************************************************************* - * FUNCTIONAL DESCRIPTION: - * This routine is called to autodetect the geometry of the DRAM. - * - * This routine is called to determine the number of column bits for the DRAM - * devices in this external bank. This routine assumes that the external bank - * has been configured for an 11-bit column and for 4 internal banks. This gives - * us the maximum address reach in memory. By writing a test value to the max - * address and locating where it aliases to, we can determine the number of valid - * column bits. - * - * This routine is called to determine the number of internal banks each DRAM - * device has. The external bank (under test) is configured for maximum reach - * with 11-bit columns and 4 internal banks. This routine will write to a max - * address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if - * that column is a "don't care". If BA1 does not affect write/read of data, - * then this device has only 2 internal banks. - * - * This routine is called to determine the ending address for this external - * bank of SDRAM. We write to a max address with a data value and then disable - * row address bits looking for "don't care" locations. Each "don't care" bit - * represents a dividing of the maximum density (128M) by 2. By dividing the - * maximum of 32 4M chunks in an external bank down by all the "don't care" bits - * determined during sizing, we set the proper density. - * - * WARNINGS. - * bp must be preserved because it is used for return linkage. - * - * EXIT - * nothing returned - but the memory subsystem is enabled - ******************************************************************************* - */ - -#include -#ifdef CONFIG_SC520 - -.section .text -.equ DRCCTL, 0x0fffef010 /* DRAM control register */ -.equ DRCTMCTL, 0x0fffef012 /* DRAM timing control register */ -.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */ -.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */ -.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */ -.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */ - -.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */ -.equ COL11_ADR, 0x0e001e00 /* 11 col addrs */ -.equ COL10_ADR, 0x0e000e00 /* 10 col addrs */ -.equ COL09_ADR, 0x0e000600 /* 9 col addrs */ -.equ COL08_ADR, 0x0e000200 /* 8 col addrs */ -.equ ROW14_ADR, 0x0f000000 /* 14 row addrs */ -.equ ROW13_ADR, 0x07000000 /* 13 row addrs */ -.equ ROW12_ADR, 0x03000000 /* 12 row addrs */ -.equ ROW11_ADR, 0x01000000 /* 11 row addrs/also bank switch */ -.equ ROW10_ADR, 0x00000000 /* 10 row addrs/also bank switch */ -.equ COL11_DATA, 0x0b0b0b0b /* 11 col addrs */ -.equ COL10_DATA, 0x0a0a0a0a /* 10 col data */ -.equ COL09_DATA, 0x09090909 /* 9 col data */ -.equ COL08_DATA, 0x08080808 /* 8 col data */ -.equ ROW14_DATA, 0x3f3f3f3f /* 14 row data (MASK) */ -.equ ROW13_DATA, 0x1f1f1f1f /* 13 row data (MASK) */ -.equ ROW12_DATA, 0x0f0f0f0f /* 12 row data (MASK) */ -.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */ -.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */ - - - /* - * initialize dram controller registers - */ -.globl mem_init -mem_init: - xorw %ax,%ax - movl $DBCTL, %edi - movb %al, (%edi) /* disable write buffer */ - - movl $ECCCTL, %edi - movb %al, (%edi) /* disable ECC */ - - movl $DRCTMCTL, %edi - movb $0x1E,%al /* Set SDRAM timing for slowest */ - movb %al, (%edi) - - /* - * setup loop to do 4 external banks starting with bank 3 - */ - movl $0xff000000,%eax /* enable last bank and setup */ - movl $DRCBENDADR, %edi /* ending address register */ - movl %eax, (%edi) - - movl $DRCCFG, %edi /* setup */ - movw $0xbbbb,%ax /* dram config register for */ - movw %ax, (%edi) - - /* - * issue a NOP to all DRAMs - */ - movl $DRCCTL, %edi /* setup DRAM control register with */ - movb $0x1,%al /* Disable refresh,disable write buffer */ - movb %al, (%edi) - movl $CACHELINESZ, %esi /* just a dummy address to write for */ - movw %ax, (%esi) - /* - * delay for 100 usec? 200? - * ******this is a cludge for now ************* - */ - movw $100,%cx -sizdelay: - loop sizdelay /* we need 100 usec here */ - /***********************************************/ - - /* - * issue all banks precharge - */ - movb $0x2,%al /* All banks precharge */ - movb %al, (%edi) - movw %ax, (%esi) - - /* - * issue 2 auto refreshes to all banks - */ - movb $0x4,%al /* Auto refresh cmd */ - movb %al, (%edi) - movw $2,%cx -refresh1: - movw %ax, (%esi) - loop refresh1 - - /* - * issue LOAD MODE REGISTER command - */ - movb $0x3,%al /* Load mode register cmd */ - movb %al, (%edi) - movw %ax, (%esi) - - /* - * issue 8 more auto refreshes to all banks - */ - movb $0x4,%al /* Auto refresh cmd */ - movb %al, (%edi) - movw $8,%cx -refresh2: - movw %ax, (%esi) - loop refresh2 - - /* - * set control register to NORMAL mode - */ - movb $0x0,%al /* Normal mode value */ - movb %al, (%edi) - - /* - * size dram starting with external bank 3 moving to external bank 0 - */ - movl $0x3,%ecx /* start with external bank 3 */ - -nextbank: - - /* - * write col 11 wrap adr - */ - movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ - movl $COL11_DATA, %eax /* pattern for max supported columns(11) */ - movl %eax, (%esi) /* write max col pattern at max col adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write col 10 wrap adr - */ - - movl $COL10_ADR, %esi /* set address to 10 col wrap address */ - movl $COL10_DATA, %eax /* pattern for 10 col wrap */ - movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write col 9 wrap adr - */ - movl $COL09_ADR, %esi /* set address to 9 col wrap address */ - movl $COL09_DATA, %eax /* pattern for 9 col wrap */ - movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write col 8 wrap adr - */ - movl $COL08_ADR, %esi /* set address to min(8) col wrap address */ - movl $COL08_DATA, %eax /* pattern for min (8) col wrap */ - movl %eax, (%esi) /* write min col pattern @ min col adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 14 wrap adr - */ - movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */ - movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */ - movl %eax, (%esi) /* write max row pattern at max row adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 13 wrap adr - */ - movl $ROW13_ADR, %esi /* set address to 13 row wrap address */ - movl $ROW13_DATA, %eax /* pattern for 13 row wrap */ - movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 12 wrap adr - */ - movl $ROW12_ADR, %esi /* set address to 12 row wrap address */ - movl $ROW12_DATA, %eax /* pattern for 12 row wrap */ - movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 11 wrap adr - */ - movl $ROW11_ADR, %edi /* set address to 11 row wrap address */ - movl $ROW11_DATA, %eax /* pattern for 11 row wrap */ - movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */ - movl (%edi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 10 wrap adr --- this write is really to determine number of banks - */ - movl $ROW10_ADR, %edi /* set address to 10 row wrap address */ - movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */ - movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */ - movl (%edi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * read data @ row 12 wrap adr to determine * banks, - * and read data @ row 14 wrap adr to determine * rows. - * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM. - * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 - * if data @ row 12 wrap == 11 or 12, we have 4 banks, - */ - xorw %di,%di /* value for 2 banks in DI */ - movl (%esi), %ebx /* read from 12 row wrap to check banks - * (esi is setup from the write to row 12 wrap) */ - cmpl %ebx,%eax /* check for AA pattern (eax holds the aa pattern) */ - jz only2 /* if pattern == AA, we only have 2 banks */ - - /* 4 banks */ - - movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */ - cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */ - jz only2 - cmpl $ROW12_DATA, %ebx /* and 12 */ - jnz bad_ram /* its bad if not 11 or 12! */ - - /* fall through */ -only2: - /* - * validate row mask - */ - movl $ROW14_ADR, %esi /* set address back to max row wrap addr */ - movl (%esi), %eax /* read actual number of rows @ row14 adr */ - - cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */ - jb bad_ram - - cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */ - ja bad_ram - - cmpb %ah,%al /* verify all 4 bytes of dword same */ - jnz bad_ram - movl %eax,%ebx - shrl $16,%ebx - cmpw %bx,%ax - jnz bad_ram - /* - * read col 11 wrap adr for real column data value - */ - movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ - movl (%esi), %eax /* read real col number at max col adr */ - /* - * validate column data - */ - cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */ - jb bad_ram - - cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */ - ja bad_ram - - subl $COL08_DATA, %eax /* normalize column data to zero */ - jc bad_ram - cmpb %ah,%al /* verify all 4 bytes of dword equal */ - jnz bad_ram - movl %eax,%edx - shrl $16,%edx - cmpw %dx,%ax - jnz bad_ram - /* - * merge bank and col data together - */ - addw %di,%dx /* merge of bank and col info in dl */ - /* - * fix ending addr mask based upon col info - */ - movb $3,%al - subb %dh,%al /* dh contains the overflow from the bank/col merge */ - movb %bl,%dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */ - xchgw %cx,%ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */ - shrb %cl,%dh /* */ - incb %dh /* ending addr is 1 greater than real end */ - xchgw %cx,%ax /* cx is bank number again */ - /* - * issue all banks precharge - */ -bad_reint: - movl $DRCCTL, %esi /* setup DRAM control register with */ - movb $0x2,%al /* All banks precharge */ - movb %al, (%esi) - movl $CACHELINESZ, %esi /* address to init read buffer */ - movw %ax, (%esi) - - /* - * update ENDING ADDRESS REGISTER - */ - movl $DRCBENDADR, %edi /* DRAM ending address register */ - movl %ecx,%ebx - addl %ebx, %edi - movb %dh, (%edi) - /* - * update CONFIG REGISTER - */ - xorb %dh,%dh - movw $0x00f,%bx - movw %cx,%ax - shlw $2,%ax - xchgw %cx,%ax - shlw %cl,%dx - shlw %cl,%bx - notw %bx - xchgw %cx,%ax - movl $DRCCFG, %edi - mov (%edi), %ax - andw %bx,%ax - orw %dx,%ax - movw %ax, (%edi) - jcxz cleanup - - decw %cx - movl %ecx,%ebx - movl $DRCBENDADR, %edi /* DRAM ending address register */ - movb $0xff,%al - addl %ebx, %edi - movb %al, (%edi) - /* - * set control register to NORMAL mode - */ - movl $DRCCTL, %esi /* setup DRAM control register with */ - movb $0x0,%al /* Normal mode value */ - movb %al, (%esi) - movl $CACHELINESZ, %esi /* address to init read buffer */ - movw %ax, (%esi) - jmp nextbank - -cleanup: - movl $DRCBENDADR, %edi /* DRAM ending address register */ - movw $4,%cx - xorw %ax,%ax -cleanuplp: - movb (%edi), %al - orb %al,%al - jz emptybank - - addb %ah,%al - jns nottoomuch - - movb $0x7f,%al -nottoomuch: - movb %al,%ah - orb $0x80,%al - movb %al, (%edi) -emptybank: - incl %edi - loop cleanuplp - -#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T) - /* set the CAS latency now since it is hard to do - * when we run from the RAM */ - movl $DRCTMCTL, %edi /* DRAM timing register */ - movb (%edi), %al -#ifdef CFG_SDRAM_CAS_LATENCY_2T - andb $0xef, %al -#endif -#ifdef CFG_SDRAM_CAS_LATENCY_3T - orb $0x10, %al -#endif - movb %al, (%edi) -#endif - movl $DRCCTL, %edi /* DRAM Control register */ - movb $0x3,%al /* Load mode register cmd */ - movb %al, (%edi) - movw %ax, (%esi) - - - movl $DRCCTL, %edi /* DRAM Control register */ - movb $0x18,%al /* Enable refresh and NORMAL mode */ - movb %al, (%edi) - - jmp dram_done - -bad_ram: - xorl %edx,%edx - xorl %edi,%edi - jmp bad_reint - -dram_done: - - /* readback DRCBENDADR and return the number - * of available ram bytes in %eax */ - - movl $DRCBENDADR, %edi /* DRAM ending address register */ - - movl (%edi), %eax - movl %eax, %ecx - andl $0x80000000, %ecx - jz bank2 - andl $0x7f000000, %eax - shrl $2, %eax - movl %eax, %ebx - -bank2: movl (%edi), %eax - movl %eax, %ecx - andl $0x00800000, %ecx - jz bank1 - andl $0x007f0000, %eax - shll $6, %eax - movl %eax, %ebx - -bank1: movl (%edi), %eax - movl %eax, %ecx - andl $0x00008000, %ecx - jz bank0 - andl $0x00007f00, %eax - shll $14, %eax - movl %eax, %ebx - -bank0: movl (%edi), %eax - movl %eax, %ecx - andl $0x00000080, %ecx - jz done - andl $0x0000007f, %eax - shll $22, %eax - movl %eax, %ebx - -done: movl %ebx, %eax - - jmp *%ebp - - -#endif /* CONFIG_SC520 */ diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c deleted file mode 100644 index db13008..0000000 --- a/cpu/i386/serial.c +++ /dev/null @@ -1,509 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/*------------------------------------------------------------------------------+ */ - -/* - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - */ -/*------------------------------------------------------------------------------- */ - -#include -#include -#include -#include - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -#include -#endif - -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncLSRDataReady1 0x01 -#define asyncLSROverrunError1 0x02 -#define asyncLSRParityError1 0x04 -#define asyncLSRFramingError1 0x08 -#define asyncLSRBreakInterrupt1 0x10 -#define asyncLSRTxHoldEmpty1 0x20 -#define asyncLSRTxShiftEmpty1 0x40 -#define asyncLSRRxFifoError1 0x80 - - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -/*-----------------------------------------------------------------------------+ - | Fifo - +-----------------------------------------------------------------------------*/ -typedef struct { - char *rx_buffer; - ulong rx_put; - ulong rx_get; - int cts; -} serial_buffer_t; - -volatile serial_buffer_t buf_info; -static int serial_buffer_active=0; -#endif - - -static int serial_div(int baudrate) -{ - - switch (baudrate) { - case 1200: - return 96; - case 9600: - return 12; - case 19200: - return 6; - case 38400: - return 3; - case 57600: - return 2; - case 115200: - return 1; - } - - return 12; -} - - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -int serial_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile char val; - - int bdiv = serial_div(gd->baudrate); - - - outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */ - outb(bdiv, UART0_BASE + UART_DLL); /* set baudrate divisor */ - outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */ - outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */ - outb(0x01, UART0_BASE + UART_FCR); /* enable FIFO */ - outb(0x0b, UART0_BASE + UART_MCR); /* Set DTR and RTS active */ - val = inb(UART0_BASE + UART_LSR); /* clear line status */ - val = inb(UART0_BASE + UART_RBR); /* read receive buffer */ - outb(0x00, UART0_BASE + UART_SCR); /* set scratchpad */ - outb(0x00, UART0_BASE + UART_IER); /* set interrupt enable reg */ - - return 0; -} - - -void serial_setbrg(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned short bdiv; - - bdiv = serial_div(gd->baudrate); - - outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */ - outb(bdiv&0xff, UART0_BASE + UART_DLL); /* set baudrate divisor */ - outb(bdiv >> 8, UART0_BASE + UART_DLM);/* set baudrate divisor */ - outb(0x03, UART0_BASE + UART_LCR); /* clear DLAB; set 8 bits, no parity */ -} - - -void serial_putc(const char c) -{ - int i; - - if (c == '\n') - serial_putc ('\r'); - - /* check THRE bit, wait for transmiter available */ - for (i = 1; i < 3500; i++) { - if ((inb (UART0_BASE + UART_LSR) & 0x20) == 0x20) { - break; - } - udelay(100); - } - outb(c, UART0_BASE + UART_THR); /* put character out */ -} - - -void serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - - -int serial_getc(void) -{ - unsigned char status = 0; - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - if (serial_buffer_active) { - return serial_buffered_getc(); - } -#endif - - while (1) { -#if defined(CONFIG_HW_WATCHDOG) - WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ -#endif /* CONFIG_HW_WATCHDOG */ - status = inb(UART0_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - outb(asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR); - } - } - return (0x000000ff & (int) inb (UART0_BASE)); -} - - -int serial_tstc(void) -{ - unsigned char status; - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - if (serial_buffer_active) { - return serial_buffered_tstc(); - } -#endif - - status = inb(UART0_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - return (1); - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - outb(asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1, UART0_BASE + UART_LSR); - } - return 0; -} - - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - -void serial_isr(void *arg) -{ - int space; - int c; - int rx_put = buf_info.rx_put; - - if (buf_info.rx_get <= rx_put) { - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - buf_info.rx_get); - } else { - space = buf_info.rx_get - rx_put; - } - - while (inb(UART0_BASE + UART_LSR) & 1) { - c = inb(UART0_BASE); - if (space) { - buf_info.rx_buffer[rx_put++] = c; - space--; - - if (rx_put == buf_info.rx_get) { - buf_info.rx_get++; - if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) { - buf_info.rx_get = 0; - } - } - - if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) { - rx_put = 0; - if (0 == buf_info.rx_get) { - buf_info.rx_get = 1; - } - - } - - } - if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { - /* Stop flow by setting RTS inactive */ - outb(inb(UART0_BASE + UART_MCR) & (0xFF ^ 0x02), - UART0_BASE + UART_MCR); - } - } - buf_info.rx_put = rx_put; -} - -void serial_buffered_init(void) -{ - serial_puts ("Switching to interrupt driven serial input mode.\n"); - buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); - buf_info.rx_put = 0; - buf_info.rx_get = 0; - - if (inb (UART0_BASE + UART_MSR) & 0x10) { - serial_puts ("Check CTS signal present on serial port: OK.\n"); - buf_info.cts = 1; - } else { - serial_puts ("WARNING: CTS signal not present on serial port.\n"); - buf_info.cts = 0; - } - - irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , - serial_isr /*interrupt_handler_t *handler */ , - (void *) &buf_info /*void *arg */ ); - - /* Enable "RX Data Available" Interrupt on UART */ - /* outb(inb(UART0_BASE + UART_IER) |0x01, UART0_BASE + UART_IER); */ - outb(0x01, UART0_BASE + UART_IER); - - /* Set DTR and RTS active, enable interrupts */ - outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR); - - /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ - outb( /*(1 << 6) |*/ 1, UART0_BASE + UART_FCR); - - serial_buffer_active = 1; -} - -void serial_buffered_putc (const char c) -{ - int i; - /* Wait for CTS */ -#if defined(CONFIG_HW_WATCHDOG) - while (!(inb (UART0_BASE + UART_MSR) & 0x10)) - WATCHDOG_RESET (); -#else - if (buf_info.cts) { - for (i=0;i<1000;i++) { - if ((inb (UART0_BASE + UART_MSR) & 0x10)) { - break; - } - } - if (i!=1000) { - buf_info.cts = 0; - } - } else { - if ((inb (UART0_BASE + UART_MSR) & 0x10)) { - buf_info.cts = 1; - } - } - -#endif - serial_putc (c); -} - -void serial_buffered_puts(const char *s) -{ - serial_puts (s); -} - -int serial_buffered_getc(void) -{ - int space; - int c; - int rx_get = buf_info.rx_get; - int rx_put; - -#if defined(CONFIG_HW_WATCHDOG) - while (rx_get == buf_info.rx_put) - WATCHDOG_RESET (); -#else - while (rx_get == buf_info.rx_put); -#endif - c = buf_info.rx_buffer[rx_get++]; - if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) { - rx_get = 0; - } - buf_info.rx_get = rx_get; - - rx_put = buf_info.rx_put; - if (rx_get <= rx_put) { - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - } else { - space = rx_get - rx_put; - } - if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { - /* Start flow by setting RTS active */ - outb(inb (UART0_BASE + UART_MCR) | 0x02, UART0_BASE + UART_MCR); - } - - return c; -} - -int serial_buffered_tstc(void) -{ - return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; -} - -#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ - - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -/* - AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port - number 0 or number 1 - - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : - configuration has been already done - - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : - configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE -*/ -#if (CONFIG_KGDB_SER_INDEX & 2) -void kgdb_serial_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile char val; - bdiv = serial_div (CONFIG_KGDB_BAUDRATE); - - /* - * Init onboard 16550 UART - */ - outb(0x80, UART1_BASE + UART_LCR); /* set DLAB bit */ - outb(bdiv & 0xff), UART1_BASE + UART_DLL); /* set divisor for 9600 baud */ - outb(bdiv >> 8), UART1_BASE + UART_DLM); /* set divisor for 9600 baud */ - outb(0x03, UART1_BASE + UART_LCR); /* line control 8 bits no parity */ - outb(0x00, UART1_BASE + UART_FCR); /* disable FIFO */ - outb(0x00, UART1_BASE + UART_MCR); /* no modem control DTR RTS */ - val = inb(UART1_BASE + UART_LSR); /* clear line status */ - val = inb(UART1_BASE + UART_RBR); /* read receive buffer */ - outb(0x00, UART1_BASE + UART_SCR); /* set scratchpad */ - outb(0x00, UART1_BASE + UART_IER); /* set interrupt enable reg */ -} - - -void putDebugChar(const char c) -{ - if (c == '\n') - serial_putc ('\r'); - - outb(c, UART1_BASE + UART_THR); /* put character out */ - - /* check THRE bit, wait for transfer done */ - while ((inb(UART1_BASE + UART_LSR) & 0x20) != 0x20); -} - - -void putDebugStr(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - - -int getDebugChar(void) -{ - unsigned char status = 0; - - while (1) { - status = inb(UART1_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - outb(asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1, UART1_BASE + UART_LSR); - } - } - return (0x000000ff & (int) inb(UART1_BASE)); -} - - -void kgdb_interruptible(int yes) -{ - return; -} - -#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ - -void kgdb_serial_init(void) -{ - serial_printf ("[on serial] "); -} - -void putDebugChar(int c) -{ - serial_putc (c); -} - -void putDebugStr(const char *str) -{ - serial_puts (str); -} - -int getDebugChar(void) -{ - return serial_getc (); -} - -void kgdb_interruptible(int yes) -{ - return; -} -#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ -#endif /* CFG_CMD_KGDB */ diff --git a/cpu/i386/start.S b/cpu/i386/start.S deleted file mode 100644 index afcbb24..0000000 --- a/cpu/i386/start.S +++ /dev/null @@ -1,196 +0,0 @@ -/* - * U-boot - i386 Startup Code - * - * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -.section .text -.code32 -.globl _start -.type _start, @function -.globl _i386boot_start -_i386boot_start: -_start: - movl $0x18,%eax /* Load our segement registes, the - * gdt have already been loaded by start16.S */ - movw %ax,%fs - movw %ax,%ds - movw %ax,%gs - movw %ax,%es - movw %ax,%ss - - /* We call a few functions in the board support package - * since we have no stack yet we'll have to use %ebp - * to store the return address */ - - /* Early platform init (setup gpio, etc ) */ - mov $early_board_init_ret, %ebp - jmp early_board_init -early_board_init_ret: - - /* The __port80 entry-point should be usabe by now */ - /* so we try to indicate progress */ - movw $0x01, %ax - movl $.progress0, %ebp - jmp __show_boot_progress -.progress0: - - /* size memory */ - mov $mem_init_ret, %ebp - jmp mem_init -mem_init_ret: - - /* check ammount of configured memory - * (we need atleast bss start+bss size+stack size) */ - movl $_i386boot_bss_start, %ecx /* BSS start */ - addl $_i386boot_bss_size, %ecx /* BSS size */ - addl $CFG_STACK_SIZE, %ecx - cmpl %ecx, %eax - jae mem_ok - - /* indicate (lack of) progress */ - movw $0x81, %ax - movl $.progress0a, %ebp - jmp __show_boot_progress -.progress0a: - jmp die -mem_ok: - - /* indicate progress */ - movw $0x02, %ax - movl $.progress1, %ebp - jmp __show_boot_progress -.progress1: - - /* create a stack after the bss */ - movl $_i386boot_bss_start, %eax - addl $_i386boot_bss_size, %eax - addl $CFG_STACK_SIZE, %eax - movl %eax, %esp - - pushl $0 - popl %eax - cmpl $0, %eax - jne no_stack - push $0x55aa55aa - popl %ebx - cmpl $0x55aa55aa, %ebx - je stack_ok - -no_stack: - /* indicate (lack of) progress */ - movw $0x82, %ax - movl $.progress1a, %ebp - jmp __show_boot_progress -.progress1a: - jmp die - - -stack_ok: - /* indicate progress */ - movw $0x03, %ax - movl $.progress2, %ebp - jmp __show_boot_progress -.progress2: - - /* copy data section to ram, size must be 4-byte aligned */ - movl $_i386boot_romdata_dest, %edi /* destination address */ - movl $_i386boot_romdata_start, %esi /* source address */ - movl $_i386boot_romdata_size, %ecx /* number of bytes to copy */ - movl %ecx, %eax - andl $3, %eax - jnz data_fail - - shrl $2, %ecx /* copy 4 byte each time */ - cld - cmpl $0, %ecx - je data_ok -data_segment: - movsl - loop data_segment - jmp data_ok -data_fail: - /* indicate (lack of) progress */ - movw $0x83, %ax - movl $.progress2a, %ebp - jmp __show_boot_progress -.progress2a: - jmp die - -data_ok: - - /* indicate progress */ - movw $0x04, %ax - movl $.progress3, %ebp - jmp __show_boot_progress -.progress3: - - /* clear bss section in ram, size must be 4-byte aligned */ - movl $_i386boot_bss_start, %eax /* BSS start */ - movl $_i386boot_bss_size, %ecx /* BSS size */ - movl %ecx, %eax - andl $3, %eax - jnz bss_fail - shrl $2, %ecx /* clear 4 byte each time */ - cld - cmpl $0, %ecx - je bss_ok -bss: - movl $0, (%edi) - add $4, %edi - loop bss - jmp bss_ok - -bss_fail: - /* indicate (lack of) progress */ - movw $0x84, %ax - movl $.progress3a, %ebp - jmp __show_boot_progress -.progress3a: - jmp die - -bss_ok: - - wbinvd - - - /* indicate progress */ - movw $0x05, %ax - movl $.progress4, %ebp - jmp __show_boot_progress -.progress4: - - call start_i386boot /* Enter, U-boot! */ - - /* indicate (lack of) progress */ - movw $0x85, %ax - movl $.progress4a, %ebp - jmp __show_boot_progress -.progress4a: - -die: hlt - jmp die - hlt diff --git a/cpu/i386/start16.S b/cpu/i386/start16.S deleted file mode 100644 index 239f2ff..0000000 --- a/cpu/i386/start16.S +++ /dev/null @@ -1,112 +0,0 @@ -/* - * U-boot - i386 Startup Code - * - * Copyright (c) 2002, 2003 Omicron Ceti AB, Daniel Engström - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#define BOOT_SEG 0xffff0000 /* linear segment of boot code */ -#define a32 .byte 0x67; -#define o32 .byte 0x66; - -.section .start16, "ax" -.code16 -.globl start16 -start16: - /* First we let the BSP do some early initialization - * this code have to map the flash to its final position - */ - mov $board_init16_ret, %bp - jmp board_init16 -board_init16_ret: - - /* Turn of cache (this might require a 486-class CPU) */ - movl %cr0, %eax - orl $0x60000000,%eax - movl %eax, %cr0 - wbinvd - - /* load the descriptor tables */ -o32 cs lidt idt_ptr -o32 cs lgdt gdt_ptr - - - /* Now, we enter protected mode */ - movl %cr0, %eax - orl $1,%eax - movl %eax, %cr0 - - /* Flush the prefetch queue */ - jmp ff -ff: - - /* Finally jump to the 32bit initialization code */ - movw $code32start, %ax - movw %ax,%bp -o32 cs ljmp *(%bp) - - /* 48-bit far pointer */ -code32start: - .long _start /* offset */ - .word 0x10 /* segment */ - -idt_ptr: - .word 0 /* limit */ - .long 0 /* base */ - -gdt_ptr: - .word 0x30 /* limit (48 bytes = 6 GDT entries) */ - .long BOOT_SEG + gdt /* base */ - - /* The GDT table ... - * - * Selector Type - * 0x00 NULL - * 0x08 Unused - * 0x10 32bit code - * 0x18 32bit data/stack - * 0x20 16bit code - * 0x28 16bit data/stack - */ - -gdt: - .word 0, 0, 0, 0 /* NULL */ - .word 0, 0, 0, 0 /* unused */ - - .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ - .word 0 /* base address = 0 */ - .word 0x9B00 /* code read/exec */ - .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ - - .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ - .word 0x0 /* base address = 0 */ - .word 0x9300 /* data read/write */ - .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ - - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9b00 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ - - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9300 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ diff --git a/cpu/i386/timer.c b/cpu/i386/timer.c deleted file mode 100644 index 486d927..0000000 --- a/cpu/i386/timer.c +++ /dev/null @@ -1,211 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - - -static volatile unsigned long system_ticks; -static int timer_init_done =0; - -static void timer_isr(void *unused) -{ - system_ticks++; -} - -unsigned long get_system_ticks(void) -{ - return system_ticks; -} - -#define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */ -#define TIMER2_VALUE 0x0a8e /* 440Hz */ - -int timer_init(void) -{ - system_ticks = 0; - - irq_install_handler(0, timer_isr, NULL); - - /* initialize timer 0 and 2 - * - * Timer 0 is used to increment system_tick 1000 times/sec - * Timer 1 was used for DRAM refresh in early PC's - * Timer 2 is used to drive the speaker - * (to stasrt a beep: write 3 to port 0x61, - * to stop it again: write 0) - */ - - outb(PIT_CMD_CTR0|PIT_CMD_BOTH|PIT_CMD_MODE2, PIT_BASE + PIT_COMMAND); - outb(TIMER0_VALUE&0xff, PIT_BASE + PIT_T0); - outb(TIMER0_VALUE>>8, PIT_BASE + PIT_T0); - - outb(PIT_CMD_CTR2|PIT_CMD_BOTH|PIT_CMD_MODE3, PIT_BASE + PIT_COMMAND); - outb(TIMER2_VALUE&0xff, PIT_BASE + PIT_T2); - outb(TIMER2_VALUE>>8, PIT_BASE + PIT_T2); - - timer_init_done = 1; - - return 0; -} - - -#ifdef CFG_TIMER_GENERIC - -/* the unit for these is CFG_HZ */ - -/* FixMe: implement these */ -void reset_timer (void) -{ - system_ticks = 0; -} - -ulong get_timer (ulong base) -{ - return (system_ticks - base); -} - -void set_timer (ulong t) -{ - system_ticks = t; -} - -static u16 read_pit(void) -{ - u8 low; - outb(PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND); - low = inb(PIT_BASE + PIT_T0); - return ((inb(PIT_BASE + PIT_T0) << 8) | low); -} - -/* this is not very exact */ -void udelay (unsigned long usec) -{ - int counter; - int wraps; - - if (!timer_init_done) { - return; - } - counter = read_pit(); - wraps = usec/1000; - usec = usec%1000; - - usec*=1194; - usec/=1000; - usec+=counter; - if (usec > 1194) { - usec-=1194; - wraps++; - } - - while (1) { - int new_count = read_pit(); - - if (((new_count < usec) && !wraps) || wraps < 0) { - break; - } - - if (new_count > counter) { - wraps--; - } - counter = new_count; - } - -} - -#if 0 -/* this is a version with debug output */ -void _udelay (unsigned long usec) -{ - int counter; - int wraps; - - int usec1, usec2, usec3; - int wraps1, wraps2, wraps3, wraps4; - int ctr1, ctr2, ctr3, nct1, nct2; - int i; - usec1=usec; - if (!timer_init_done) { - return; - } - counter = read_pit(); - ctr1 = counter; - wraps = usec/1000; - usec = usec%1000; - - usec2 = usec; - wraps1 = wraps; - - usec*=1194; - usec/=1000; - usec+=counter; - if (usec > 1194) { - usec-=1194; - wraps++; - } - - usec3 = usec; - wraps2 = wraps; - - ctr2 = wraps3 = nct1 = 4711; - ctr3 = wraps4 = nct2 = 4711; - i=0; - while (1) { - int new_count = read_pit(); - i++; - if ((new_count < usec && !wraps) || wraps < 0) { - break; - } - - if (new_count > counter) { - wraps--; - } - if (ctr2==4711) { - ctr2 = counter; - wraps3 = wraps; - nct1 = new_count; - } else { - ctr3 = counter; - wraps4 = wraps; - nct2 = new_count; - } - - counter = new_count; - } - - printf("udelay(%d)\n", usec1); - printf("counter %d\n", ctr1); - printf("1: wraps %d, usec %d\n", wraps1, usec2); - printf("2: wraps %d, usec %d\n", wraps2, usec3); - printf("new_count[0] %d counter %d wraps %d\n", nct1, ctr2, wraps3); - printf("new_count[%d] %d counter %d wraps %d\n", i, nct2, ctr3, wraps4); - - printf("%d %d %d %d %d\n", - read_pit(), read_pit(), read_pit(), - read_pit(), read_pit()); -} -#endif -#endif diff --git a/cpu/ixp/Makefile b/cpu/ixp/Makefile deleted file mode 100644 index ba2e589..0000000 --- a/cpu/ixp/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = serial.o interrupts.o cpu.o timer.o pci.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/ixp/config.mk b/cpu/ixp/config.mk deleted file mode 100644 index eddda39..0000000 --- a/cpu/ixp/config.mk +++ /dev/null @@ -1,37 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -BIG_ENDIAN = y - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float -mbig-endian - -PLATFORM_CPPFLAGS += -mbig-endian -march=armv4 -mtune=strongarm1100 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c deleted file mode 100644 index 9383473..0000000 --- a/cpu/ixp/cpu.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include -#include - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - DECLARE_GLOBAL_DATA_PTR; - - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - - pci_init(); - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * just disable everything that can disturb booting linux - */ - - unsigned long i; - - disable_interrupts (); - - /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf ("resetting ...\n"); - - udelay (50000); /* wait 50 ms */ - disable_interrupts (); - reset_cpu (0); - - /*NOTREACHED*/ - return (0); -} - -/* taken from blob */ -void icache_enable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* set i-cache */ - i |= 0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void icache_disable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* clear i-cache */ - i &= ~0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush i-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -} - -int icache_status (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* return bit */ - return (i & 0x1000); -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} - -/* FIXME */ -/* -void pci_init(void) -{ - return; -} -*/ diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c deleted file mode 100644 index e260dea..0000000 --- a/cpu/ixp/interrupts.c +++ /dev/null @@ -1,158 +0,0 @@ -/* vi: set ts=8 sw=8 noet: */ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifdef CONFIG_USE_IRQ -/* enable IRQ/FIQ interrupts */ -void enable_interrupts (void) -{ -#error: interrupts not implemented yet -} - - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ -#error: interrupts not implemented yet -} -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32" - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - - -int interrupt_init (void) -{ - /* nothing happens here - we don't setup any IRQs */ - return (0); -} diff --git a/cpu/ixp/pci.c b/cpu/ixp/pci.c deleted file mode 100644 index 84c4339..0000000 --- a/cpu/ixp/pci.c +++ /dev/null @@ -1,575 +0,0 @@ -/* - * IXP PCI Init - * (C) Copyright 2004 eslab.whut.edu.cn - * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include - -#ifdef CONFIG_PCI - -#include -#include -#include -#include -#include - -static void non_prefetch_read (unsigned int addr, unsigned int cmd, - unsigned int *data); -static void non_prefetch_write (unsigned int addr, unsigned int cmd, - unsigned int data); -static void configure_pins (void); -static void sys_pci_gpio_clock_config (void); -static void pci_bus_scan (void); -static int pci_device_exists (unsigned int deviceNo); -static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus, - unsigned int dev, unsigned int func); -static void sys_pci_device_bars_write (void); -static void calc_bars (PciBar * Bars[], unsigned int nBars, - unsigned int startAddr); - -#define PCI_MEMORY_BUS 0x00000000 -#define PCI_MEMORY_PHY 0x48000000 -#define PCI_MEMORY_SIZE 0x04000000 - -#define PCI_MEM_BUS 0x40000000 -#define PCI_MEM_PHY 0x00000000 -#define PCI_MEM_SIZE 0x04000000 - -#define PCI_IO_BUS 0x40000000 -#define PCI_IO_PHY 0x50000000 -#define PCI_IO_SIZE 0x10000000 - -struct pci_controller hose; - -unsigned int nDevices; -unsigned int nMBars; -unsigned int nIOBars; -PciBar *memBars[IXP425_PCI_MAX_BAR]; -PciBar *ioBars[IXP425_PCI_MAX_BAR]; -PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS]; - -int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val) -{ - unsigned int retval; - unsigned int addr; - - /*address bits 31:28 specify the device 10:8 specify the function */ - /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval); - - *val = retval; - - return (OK); -} - -int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val) -{ - unsigned int n; - unsigned int retval; - unsigned int addr; - unsigned int byteEnables; - - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = - (~(BIT (n) | BIT ((n + 1)))) & - IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - /*address bits 31:28 specify the device 10:8 specify the function */ - /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); - - /*Pick out the word we are interested in */ - *val = (retval >> (8 * n)); - - return (OK); -} - -int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val) -{ - unsigned int retval; - unsigned int n; - unsigned int byteEnables; - unsigned int addr; - - n = where % 4; - /*byte enables are 4 bits, active low, the position of each - bit maps to the byte that it enables */ - byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - - /*address bits 31:28 specify the device, 10:8 specify the function */ - /*Set the address to be read */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval); - /*Pick out the byte we are interested in */ - *val = (retval >> (8 * n)); - - return (OK); -} - -int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val) -{ - unsigned int addr; - unsigned int byteEnables; - unsigned int n; - unsigned int ldata; - - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - ldata = val << (8 * n); - /*address bits 31:28 specify the device 10:8 specify the function */ - /*Set the address to be written */ - addr = BIT ((31 - dev)) | (where & ~3); - non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - - return (OK); -} - -int pci_write_config_word (pci_dev_t dev, int where, unsigned short val) -{ - unsigned int addr; - unsigned int byteEnables; - unsigned int n; - unsigned int ldata; - - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = - (~(BIT (n) | BIT ((n + 1)))) & - IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - ldata = val << (8 * n); - /*address bits 31:28 specify the device 10:8 specify the function */ - /*Set the address to be written */ - addr = BIT (31 - dev) | (where & ~3); - non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - - return (OK); -} - -int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val) -{ - unsigned int addr; - - /*address bits 31:28 specify the device 10:8 specify the function */ - /*Set the address to be written */ - addr = BIT (31 - dev) | (where & ~3); - non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val); - - return (OK); -} - -void non_prefetch_read (unsigned int addr, - unsigned int cmd, unsigned int *data) -{ - REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); - - /*set up and execute the read */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); - - /*The result of the read is now in np_rdata */ - REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data); - - return; -} - -void non_prefetch_write (unsigned int addr, - unsigned int cmd, unsigned int data) -{ - - REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr); - /*set up the write */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd); - /*Execute the write by writing to NP_WDATA */ - REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data); - - return; -} - -/* - * PCI controller config registers are accessed through these functions - * i.e. these allow us to set up our own BARs etc. - */ -void crp_read (unsigned int offset, unsigned int *data) -{ - REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset); - REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data); -} - -void crp_write (unsigned int offset, unsigned int data) -{ - /*The CRP address register bit 16 indicates that we want to do a write */ - REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, - PCI_CRP_WRITE | offset); - REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data); -} - -/*struct pci_controller *hose*/ -void pci_ixp_init (struct pci_controller *hose) -{ - unsigned int regval; - - hose->first_busno = 0; - hose->last_busno = 0x00; - - /* System memory space */ - pci_set_region (hose->regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region (hose->regions + 1, - PCI_MEM_BUS, - PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM); - /* PCI I/O space */ - pci_set_region (hose->regions + 2, - PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose (hose); - -/* - ========================================================== - Init IXP PCI - ========================================================== -*/ - REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - regval |= 1 << 2; - REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - - configure_pins (); - - READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13))); - udelay (533); - sys_pci_gpio_clock_config (); - REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0); - udelay (100); - READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13)); - udelay (533); - crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT); - crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT); - /*Setup PCI-AHB and AHB-PCI address mappings */ - REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET, - IXP425_PCI_AHBMEMBASE_DEFAULT); - - REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET, - IXP425_PCI_AHBIOBASE_DEFAULT); - - REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET, - IXP425_PCI_PCIMEMBASE_DEFAULT); - - crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM); - - REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS; - REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); - crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME); - udelay (1000); - - pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD); - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); -#ifdef CONFIG_PCI_SCAN_SHOW - printf ("Device bus dev func deviceID vendorID \n"); -#endif - pci_bus_scan (); -} - -void configure_pins (void) -{ - unsigned int regval; - - /* Disable clock on GPIO PIN 14 */ - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8))); - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - - READ_GPIO_REG (IXP425_GPIO_GPOER, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPOER, - (((~(3 << 13)) & regval) | (0xf << 8))); - READ_GPIO_REG (IXP425_GPIO_GPOER, regval); - - READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPIT2R, - (regval & - ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1))); - READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval); - - READ_GPIO_REG (IXP425_GPIO_GPISR, regval); - WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8))); - READ_GPIO_REG (IXP425_GPIO_GPISR, regval); -} - -void sys_pci_gpio_clock_config (void) -{ - unsigned int regval; - - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - regval |= 0x1 << 4; - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval); - regval |= 0x1 << 8; - WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval); -} - -void pci_bus_scan (void) -{ - unsigned int bus = 0, dev, func = 0; - unsigned short data16; - unsigned int data32; - unsigned char intPin; - - /* Assign first device to ourselves */ - devices[0].bus = 0; - devices[0].device = 0; - devices[0].func = 0; - - crp_read (PCI_CFG_VENDOR_ID, &data32); - - devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK; - devices[0].device_id = data32 >> 16; - devices[0].error = FALSE; - devices[0].bar[NO_BAR].size = 0; /*dummy - required */ - - nDevices = 1; - - nMBars = 0; - nIOBars = 0; - - for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) { - - /*Check whether a device is present */ - if (pci_device_exists (dev) != TRUE) { - - /*Clear error bits in ISR, write 1 to clear */ - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | - PCI_ISR_AHBE); - continue; - } - - /*A device is present, add an entry to the array */ - devices[nDevices].bus = bus; - devices[nDevices].device = dev; - devices[nDevices].func = func; - - pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16); - - devices[nDevices].vendor_id = data16; - - pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16); - devices[nDevices].device_id = data16; - - /*The device is functioning correctly, set error to FALSE */ - devices[nDevices].error = FALSE; - - /*Figure out what BARs are on this device */ - sys_pci_bar_info_get (nDevices, bus, dev, func); - /*Figure out what INTX# line the card uses */ - pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin); - - /*assign the appropriate irq line */ - if (intPin > PCI_IRQ_LINES) { - devices[nDevices].error = TRUE; - } else if (intPin != 0) { - /*This device uses an interrupt line */ - /*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */ - devices[nDevices].irq = intPin; - } -#ifdef CONFIG_PCI_SCAN_SHOW - printf ("%06d %03d %03d %04d %08d %08x\n", nDevices, - devices[nDevices].vendor_id); -#endif - nDevices++; - - } - - calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE); - sys_pci_device_bars_write (); - - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE - | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE); -} - -void sys_pci_bar_info_get (unsigned int devnum, - unsigned int bus, - unsigned int dev, unsigned int func) -{ - unsigned int data32; - unsigned int tmp; - unsigned int size; - - pci_write_config_dword (devnum, - PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY); - pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32); - - devices[devnum].bar[0].address = (data32 & 1); - - if (data32 & 1) { - /* IO space */ - tmp = data32 & ~0x3; - size = ~(tmp - 1); - devices[devnum].bar[0].size = size; - - if (nIOBars < IXP425_PCI_MAX_BAR) { - ioBars[nIOBars++] = &devices[devnum].bar[0]; - } - } else { - /* Mem space */ - tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - size = ~(tmp - 1); - devices[devnum].bar[0].size = size; - - if (nMBars < IXP425_PCI_MAX_BAR) { - memBars[nMBars++] = &devices[devnum].bar[0]; - } else { - devices[devnum].error = TRUE; - } - - } - - devices[devnum].bar[1].size = 0; -} - -void sortBars (PciBar * Bars[], unsigned int nBars) -{ - unsigned int i, j; - PciBar *tmp; - - if (nBars == 0) { - return; - } - - /* Sort biggest to smallest */ - for (i = 0; i < nBars - 1; i++) { - for (j = i + 1; j < nBars; j++) { - if (Bars[j]->size > Bars[i]->size) { - /* swap them */ - tmp = Bars[i]; - Bars[i] = Bars[j]; - Bars[j] = tmp; - } - } - } -} - -void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr) -{ - unsigned int i; - - if (nBars == 0) { - return; - } - - for (i = 0; i < nBars; i++) { - Bars[i]->address |= startAddr; - startAddr += Bars[i]->size; - } -} - -void sys_pci_device_bars_write (void) -{ - unsigned int i; - int addr; - - for (i = 1; i < nDevices; i++) { - if (devices[i].error) { - continue; - } - - pci_write_config_dword (devices[i].device, - PCI_CFG_BASE_ADDRESS_0, - devices[i].bar[0].address); - addr = BIT (31 - devices[i].device) | - (0 << PCI_NP_AD_FUNCSL) | - (PCI_CFG_BASE_ADDRESS_0 & ~3); - pci_write_config_dword (devices[i].device, - PCI_CFG_DEV_INT_LINE, devices[i].irq); - - pci_write_config_word (devices[i].device, - PCI_CFG_COMMAND, INITIAL_PCI_CMD); - - } -} - - -int pci_device_exists (unsigned int deviceNo) -{ - unsigned int vendorId; - unsigned int regval; - - pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId); - - /* There are two ways to find out an empty device. - * 1. check Master Abort bit after the access. - * 2. check whether the vendor id read back is 0x0. - */ - REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval); - if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) { - return TRUE; - } - /*no device present, make sure that the master abort bit is reset */ - - REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE); - return FALSE; -} - -pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo) -{ - unsigned int i; - unsigned int devdidvid; - unsigned int didvid; - unsigned int vendorId, deviceId; - - vendorId = ids->vendor; - deviceId = ids->device; - didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) | - (vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK); - - for (i = devNo + 1; i < nDevices; i++) { - - pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID, - &devdidvid); - - if (devdidvid == didvid) { - return devices[i].device; - } - } - return -1; -} -#endif /* CONFIG_PCI */ diff --git a/cpu/ixp/serial.c b/cpu/ixp/serial.c deleted file mode 100644 index aea0cf8..0000000 --- a/cpu/ixp/serial.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned int quot = 0; - int uart = CFG_IXP425_CONSOLE; - - if (gd->baudrate == 1200) - quot = 192; - else if (gd->baudrate == 9600) - quot = 96; - else if (gd->baudrate == 19200) - quot = 48; - else if (gd->baudrate == 38400) - quot = 24; - else if (gd->baudrate == 57600) - quot = 16; - else if (gd->baudrate == 115200) - quot = 8; - else - hang (); - - IER(uart) = 0; /* Disable for now */ - FCR(uart) = 0; /* No fifos enabled */ - - /* set baud rate */ - LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - DLL(uart) = quot & 0xff; - DLH(uart) = quot >> 8; - LCR(uart) = LCR_WLS0 | LCR_WLS1; - - IER(uart) = IER_UUE; -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - /* wait for room in the tx FIFO on UART */ - while ((LSR(CFG_IXP425_CONSOLE) & LSR_TEMT) == 0); - - THR(CFG_IXP425_CONSOLE) = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_tstc (void) -{ - return LSR(CFG_IXP425_CONSOLE) & LSR_DR; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - while (!(LSR(CFG_IXP425_CONSOLE) & LSR_DR)); - - return (char) RBR(CFG_IXP425_CONSOLE) & 0xff; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} diff --git a/cpu/ixp/start.S b/cpu/ixp/start.S deleted file mode 100644 index 2726f65..0000000 --- a/cpu/ixp/start.S +++ /dev/null @@ -1,499 +0,0 @@ -/* vi: set ts=8 sw=8 noet: */ -/* - * u-boot - Startup Code for XScale IXP - * - * Copyright (C) 2003 Kyle Harris - * - * Based on startup code example contained in the - * Intel IXP4xx Programmer's Guide and past u-boot Start.S - * samples. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define MMU_Control_M 0x001 /* Enable MMU */ -#define MMU_Control_A 0x002 /* Enable address alignment faults */ -#define MMU_Control_C 0x004 /* Enable cache */ -#define MMU_Control_W 0x008 /* Enable write-buffer */ -#define MMU_Control_P 0x010 /* Compatability: 32 bit code */ -#define MMU_Control_D 0x020 /* Compatability: 32 bit data */ -#define MMU_Control_L 0x040 /* Compatability: */ -#define MMU_Control_B 0x080 /* Enable Big-Endian */ -#define MMU_Control_S 0x100 /* Enable system protection */ -#define MMU_Control_R 0x200 /* Enable ROM protection */ -#define MMU_Control_I 0x1000 /* Enable Instruction cache */ -#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */ -#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L) - - -/* - * Macro definitions - */ - /* Delay a bit */ - .macro DELAY_FOR cycles, reg0 - ldr \reg0, =\cycles - subs \reg0, \reg0, #1 - subne pc, pc, #0xc - .endm - - /* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * - relocate armboot to ram - * - setup stack - * - jump to second stage - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/****************************************************************************/ -/* */ -/* the actual reset code */ -/* */ -/****************************************************************************/ - -reset: - /* disable mmu, set big-endian */ - mov r0, #0xf8 - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - /* invalidate I & D caches & BTB */ - mcr p15, 0, r0, c7, c7, 0 - CPWAIT r0 - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* drain write and fill buffers */ - mcr p15, 0, r0, c7, c10, 4 - CPWAIT r0 - - /* disable write buffer coalescing */ - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #1 - mcr p15, 0, r0, c1, c0, 1 - CPWAIT r0 - - /* set EXP CS0 to the optimum timing */ - ldr r1, =CFG_EXP_CS0 - ldr r2, =IXP425_EXP_CS0 - str r1, [r2] - - /* make sure flash is visible at 0 */ -#if 0 - ldr r2, =IXP425_EXP_CFG0 - ldr r1, [r2] - orr r1, r1, #0x80000000 - str r1, [r2] -#endif - mov r1, #CFG_SDR_CONFIG - ldr r2, =IXP425_SDR_CONFIG - str r1, [r2] - - /* disable refresh cycles */ - mov r1, #0 - ldr r3, =IXP425_SDR_REFRESH - str r1, [r3] - - /* send nop command */ - mov r1, #3 - ldr r4, =IXP425_SDR_IR - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* set SDRAM internal refresh val */ - ldr r1, =CFG_SDRAM_REFRESH_CNT - str r1, [r3] - DELAY_FOR 0x4000, r0 - - /* send precharge-all command to close all open banks */ - mov r1, #2 - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* provide 8 auto-refresh cycles */ - mov r1, #4 - mov r5, #8 -111: str r1, [r4] - DELAY_FOR 0x100, r0 - subs r5, r5, #1 - bne 111b - - /* set mode register in sdram */ - mov r1, #CFG_SDR_MODE_CONFIG - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* send normal operation command */ - mov r1, #6 - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* copy */ - mov r0, #0 - mov r4, r0 - add r2, r0, #0x40000 - mov r1, #0x10000000 - mov r5, r1 - - 30: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r0, r2 - bne 30b - - /* invalidate I & D caches & BTB */ - mcr p15, 0, r0, c7, c7, 0 - CPWAIT r0 - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* drain write and fill buffers */ - mcr p15, 0, r0, c7, c10, 4 - CPWAIT r0 - - /* move flash to 0x50000000 */ - ldr r2, =IXP425_EXP_CFG0 - ldr r1, [r2] - bic r1, r1, #0x80000000 - str r1, [r2] - - nop - nop - nop - nop - nop - nop - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* enable I cache */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #MMU_Control_I - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - mrs r0,cpsr /* set the cpu to SVC32 mode */ - bic r0,r0,#0x1f /* (superviser mode, M=10011) */ - orr r0,r0,#0x13 - msr cpsr,r0 - -#ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - - -/****************************************************************************/ -/* */ -/* Interrupt handling */ -/* */ -/****************************************************************************/ - -/* IRQ stack frame */ - -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 - - /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - - ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ - add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ - mov r0, sp - .endm - - - /* use irq_save_user_regs / irq_restore_user_regs for */ - /* IRQ/FIQ handling */ - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ /* Calling SP, LR */ - str lr, [r8, #0] /* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] /* Save CPSR */ - str r0, [r8, #8] /* Save OLD_R0 */ - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - - -/****************************************************************************/ -/* */ -/* exception handlers */ -/* */ -/****************************************************************************/ - - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - irq_save_user_regs /* someone ought to write a more */ - bl do_fiq /* effiction fiq_save_user_regs */ - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -/****************************************************************************/ -/* */ -/* Reset function: Use Watchdog to reset */ -/* */ -/****************************************************************************/ - - .align 5 -.globl reset_cpu - -reset_cpu: - ldr r1, =0x482e - ldr r2, =IXP425_OSWK - str r1, [r2] - ldr r1, =0x0fff - ldr r2, =IXP425_OSWT - str r1, [r2] - ldr r1, =0x5 - ldr r2, =IXP425_OSWE - str r1, [r2] - b reset_endless - - -reset_endless: - - b reset_endless diff --git a/cpu/ixp/timer.c b/cpu/ixp/timer.c deleted file mode 100644 index 8df2a31..0000000 --- a/cpu/ixp/timer.c +++ /dev/null @@ -1,79 +0,0 @@ -/* vi: set ts=8 sw=8 noet: */ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void ixp425_udelay(unsigned long usec) -{ - /* - * This function has a max usec, but since it is called from udelay - * we should not have to worry... be happy - */ - unsigned long usecs = CFG_HZ/1000000L & ~IXP425_OST_RELOAD_MASK; - - *IXP425_OSST = IXP425_OSST_TIMER_1_PEND; - usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; - *IXP425_OSRT1 = usecs; - while (!(*IXP425_OSST & IXP425_OSST_TIMER_1_PEND)); -} - -void udelay (unsigned long usec) -{ - while (usec--) ixp425_udelay(1); -} - -static ulong reload_constant = 0xfffffff0; - -void reset_timer_masked (void) -{ - ulong reload = reload_constant | IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; - - *IXP425_OSST = IXP425_OSST_TIMER_1_PEND; - *IXP425_OSRT1 = reload; -} - -ulong get_timer_masked (void) -{ - /* - * Note that it is possible for this to wrap! - * In this case we return max. - */ - ulong current = *IXP425_OST1; - if (*IXP425_OSST & IXP425_OSST_TIMER_1_PEND) - { - return reload_constant; - } - return (reload_constant - current); -} diff --git a/cpu/lh7a40x/Makefile b/cpu/lh7a40x/Makefile deleted file mode 100644 index b45bd6a..0000000 --- a/cpu/lh7a40x/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = cpu.o speed.o interrupts.o serial.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/lh7a40x/config.mk b/cpu/lh7a40x/config.mk deleted file mode 100644 index 10e755b..0000000 --- a/cpu/lh7a40x/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c deleted file mode 100644 index 718f253..0000000 --- a/cpu/lh7a40x/cpu.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include -#include - -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - DECLARE_GLOBAL_DATA_PTR; - - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - unsigned long i; - - disable_interrupts (); - - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} - -#ifdef USE_920T_MMU -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_DC); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - reg &= ~C1_DC; - write_p15_c1 (reg); -} - -int dcache_status (void) -{ - return (read_p15_c1 () & C1_DC) != 0; -} -#endif diff --git a/cpu/lh7a40x/interrupts.c b/cpu/lh7a40x/interrupts.c deleted file mode 100644 index 23d8039..0000000 --- a/cpu/lh7a40x/interrupts.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include - -static ulong timer_load_val = 0; - -/* macro to read the 16 bit timer */ -static inline ulong READ_TIMER(void) -{ - lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; - lh7a40x_timer_t* timer = &timers->timer1; - - return (timer->value & 0x0000ffff); -} - -#ifdef CONFIG_USE_IRQ -/* enable IRQ interrupts */ -void enable_interrupts (void) -{ - unsigned long temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); -} - - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ - unsigned long old,temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); - return (old & 0x80) == 0; -} -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32", - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -static ulong timestamp; -static ulong lastdec; - -int interrupt_init (void) -{ - lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; - lh7a40x_timer_t* timer = &timers->timer1; - - /* a periodic timer using the 508kHz source */ - timer->control = (TIMER_PER | TIMER_CLK508K); - - if (timer_load_val == 0) { - /* - * 10ms period with 508.469kHz clock = 5084 - */ - timer_load_val = CFG_HZ/100; - } - - /* load value for 10 ms timeout */ - lastdec = timer->load = timer_load_val; - - /* auto load, start timer */ - timer->control = timer->control | TIMER_EN; - timestamp = 0; - - return (0); -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return (get_timer_masked() - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - ulong tmo,tmp; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CFG_HZ; - tmo /= 1000; - } - else { - if (usec > 1) { - tmo = usec * CFG_HZ; - tmo /= (1000*1000); - } - else - tmo = 1; - } - - /* check for rollover during this delay */ - tmp = get_timer (0); - if ((tmp + tmo) < tmp ) - reset_timer_masked(); /* timer would roll over */ - else - tmo += tmp; - - while (get_timer_masked () < tmo); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER(); - timestamp = 0; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += (lastdec - now); - } else { - /* we have an overflow ... */ - timestamp += ((lastdec + timer_load_val) - now); - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CFG_HZ; - tmo /= 1000; - } else { - if (usec > 1) { - tmo = usec * CFG_HZ; - tmo /= (1000*1000); - } else { - tmo = 1; - } - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = timer_load_val * 100; - - return tbclk; -} diff --git a/cpu/lh7a40x/serial.c b/cpu/lh7a40x/serial.c deleted file mode 100644 index ff5b2d8..0000000 --- a/cpu/lh7a40x/serial.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -#if defined(CONFIG_CONSOLE_UART1) -# define UART_CONSOLE 1 -#elif defined(CONFIG_CONSOLE_UART2) -# define UART_CONSOLE 2 -#elif defined(CONFIG_CONSOLE_UART3) -# define UART_CONSOLE 3 -#else -# error "No console configured ... " -#endif - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - int i; - unsigned int reg = 0; - - /* - * userguide 15.1.2.4 - * - * BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1 - * - * UART_REF_FREQ = external system clock input / 2 (Hz) - * BAUD is desired baudrate (bits/s) - * - * NOTE: we add (divisor/2) to numerator to round for - * more precision - */ - reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1; - uart->brcon = reg; - - for (i = 0; i < 100; i++); -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - /* UART must be enabled before writing to any config registers */ - uart->con |= (UART_EN); - -#ifdef CONFIG_CONSOLE_UART1 - /* infrared disabled */ - uart->con |= UART_SIRD; -#endif - /* loopback disabled */ - uart->con &= ~(UART_LBE); - - /* modem lines and tx/rx polarities */ - uart->con &= ~(UART_MXP | UART_TXP | UART_RXP); - - /* FIFO enable, N81 */ - uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1); - - /* set baudrate */ - serial_setbrg (); - - /* enable rx interrupt */ - uart->inten |= UART_RI; - - return (0); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - /* wait for character to arrive */ - while (uart->status & UART_RXFE); - - return(uart->data & 0xff); -} - -#ifdef CONFIG_HWFLOW -static int hwflow = 0; /* turned off by default */ -int hwflow_onoff(int on) -{ - switch(on) { - case 0: - default: - break; /* return current */ - case 1: - hwflow = 1; /* turn on */ - break; - case -1: - hwflow = 0; /* turn off */ - break; - } - return hwflow; -} -#endif - -#ifdef CONFIG_MODEM_SUPPORT -static int be_quiet = 0; -void disable_putc(void) -{ - be_quiet = 1; -} - -void enable_putc(void) -{ - be_quiet = 0; -} -#endif - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - -#ifdef CONFIG_MODEM_SUPPORT - if (be_quiet) - return; -#endif - - /* wait for room in the tx FIFO */ - while (!(uart->status & UART_TXFE)); - -#ifdef CONFIG_HWFLOW - /* Wait for CTS up */ - while(hwflow && !(uart->status & UART_CTS)); -#endif - - uart->data = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc (void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - return(!(uart->status & UART_RXFE)); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} diff --git a/cpu/lh7a40x/speed.c b/cpu/lh7a40x/speed.c deleted file mode 100644 index 333ebb5..0000000 --- a/cpu/lh7a40x/speed.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -/* ------------------------------------------------------------------------- */ -/* NOTE: This describes the proper use of this file. - * - * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. - * - * get_FCLK(), get_HCLK(), get_PCLK() return the clock of - * the specified bus in HZ. - */ -/* ------------------------------------------------------------------------- */ - -ulong get_PLLCLK (void) -{ - return CONFIG_SYS_CLK_FREQ; -} - -/* return FCLK frequency */ -ulong get_FCLK (void) -{ - lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; - ulong maindiv1, maindiv2, prediv, ps; - - /* - * from userguide 6.1.1.2 - * - * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) / - * ((PREDIV+2) * (2^PS)) - */ - maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11; - maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7; - prediv = (csc->clkset & CLKSET_PREDIV) >> 2; - ps = (csc->clkset & CLKSET_PS) >> 16; - - return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) / - ((prediv + 2) * (1 << ps))); -} - - -/* return HCLK frequency */ -ulong get_HCLK (void) -{ - lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; - - return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1)); -} - -/* return PCLK frequency */ -ulong get_PCLK (void) -{ - lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; - - return (get_HCLK () / - (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1))); -} diff --git a/cpu/lh7a40x/start.S b/cpu/lh7a40x/start.S deleted file mode 100644 index fb748cf..0000000 --- a/cpu/lh7a40x/start.S +++ /dev/null @@ -1,428 +0,0 @@ -/* - * armboot - Startup Code for ARM920 CPU-core - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * relocate armboot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - -#define pWDTCTL 0x80001400 /* Watchdog Timer control register */ -#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */ -#define pCLKSET 0x80000420 /* clock divisor register */ - - /* disable watchdog, set watchdog control register to - * all zeros (default reset) - */ - ldr r0, =pWDTCTL - mov r1, #0x0 - str r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTENC register (default) - */ - mov r1, #0xffffffff - ldr r0, =pINTENC - str r1, [r0] - - /* FCLK:HCLK:PCLK = 1:2:2 */ - /* default FCLK is 200 MHz, using 14.7456 MHz fin */ - ldr r0, =pCLKSET - ldr r1, =0x0004ee39 -@ ldr r1, =0x0005ee39 @ 1: 2: 4 - str r1, [r0] - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - -#ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - blt copy_loop /* a 'ble' here actually copies */ - /* four bytes of bss */ -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - @add r0, r0, #4 /* start at first byte of bss */ - /* why inc. 4 bytes past then? */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - - -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus - mcr p15, 0, r0, c1, c0, 0 - - - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - mov ip, lr - bl lowlevel_init - mov lr, ip - - mov pc, lr - - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get pc, cpsr - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - - .align 5 -.globl reset_cpu -reset_cpu: - bl disable_interrupts - - /* Disable watchdog */ - ldr r1, =pWDTCTL - mov r3, #0 - str r3, [r1] - - /* reset counter */ - ldr r3, =0x00001984 - str r3, [r1, #4] - - /* Enable the watchdog */ - mov r3, #1 - str r3, [r1] - -_loop_forever: - b _loop_forever diff --git a/cpu/mcf52x2/Makefile b/cpu/mcf52x2/Makefile deleted file mode 100644 index 879deb7..0000000 --- a/cpu/mcf52x2/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -# CFLAGS += -DET_DEBUG - -LIB = lib$(CPU).a - -START = -OBJS = serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk deleted file mode 100644 index 650db85..0000000 --- a/cpu/mcf52x2/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -ffixed-d7 -msep-data -PLATFORM_CPPFLAGS += -m5307 diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c deleted file mode 100644 index 32a524f..0000000 --- a/cpu/mcf52x2/cpu.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2003 - * Josef Baumgartner - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_M5272 -#include -#include -#endif - -#ifdef CONFIG_M5282 - -#endif - -#ifdef CONFIG_M5249 -#include -#endif - - -#ifdef CONFIG_M5272 -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR); - - wdp->wdog_wrrr = 0; - udelay (1000); - - /* enable watchdog, set timeout to 0 and wait */ - wdp->wdog_wrrr = 1; - while (1); - - /* we don't return! */ - return 0; -}; - -int checkcpu(void) { - ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR); - uchar msk; - char *suf; - - puts ("CPU: "); - msk = (*dirp > 28) & 0xf; - switch (msk) { - case 0x2: suf = "1K75N"; break; - case 0x4: suf = "3K75N"; break; - default: - suf = NULL; - printf ("MOTOROLA MCF5272 (Mask:%01x)\n", msk); - break; - } - - if (suf) - printf ("MOTOROLA MCF5272 %s\n", suf); - return 0; -}; - - -#if defined(CONFIG_WATCHDOG) -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset (void) -{ - volatile immap_t * regp = (volatile immap_t *)CFG_MBAR; - regp->wdog_reg.wdog_wcr = 0; -} - -int watchdog_disable (void) -{ - volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; - - regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ - regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ - regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */ - - puts ("WATCHDOG:disabled\n"); - return (0); -} - -int watchdog_init (void) -{ - volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; - - regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ - - /* set timeout and enable watchdog */ - regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; - regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ - - puts ("WATCHDOG:enabled\n"); - return (0); -} -#endif /* #ifdef CONFIG_WATCHDOG */ - -#endif /* #ifdef CONFIG_M5272 */ - - -#ifdef CONFIG_M5282 -int checkcpu (void) -{ - puts ("CPU: MOTOROLA Coldfire MCF5282\n"); - return 0; -} - -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - return 0; -}; -#endif - -#ifdef CONFIG_M5249 /* test-only: todo... */ -int checkcpu (void) -{ - char buf[32]; - - printf ("CPU: MOTOROLA Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK)); - return 0; -} - -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - /* enable watchdog, set timeout to 0 and wait */ - mbar_writeByte(MCFSIM_SYPCR, 0xc0); - while (1); - - /* we don't return! */ - return 0; -}; -#endif diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c deleted file mode 100644 index 350c431..0000000 --- a/cpu/mcf52x2/cpu_init.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * (C) Copyright 2003 - * Josef Baumgartner - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifdef CONFIG_M5272 -#include -#include -#endif - -#ifdef CONFIG_M5282 -#include -#include -#endif - -#ifdef CONFIG_M5249 -#include -#endif - -#if defined(CONFIG_M5272) -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f (void) -{ - /* if we come from RAM we assume the CPU is - * already initialized. - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM - volatile immap_t *regp = (immap_t *)CFG_MBAR; - - volatile unsigned char *mbar; - mbar = (volatile unsigned char *) CFG_MBAR; - - regp->sysctrl_reg.sc_scr = CFG_SCR; - regp->sysctrl_reg.sc_spr = CFG_SPR; - - /* Setup Ports: */ - regp->gpio_reg.gpio_pacnt = CFG_PACNT; - regp->gpio_reg.gpio_paddr = CFG_PADDR; - regp->gpio_reg.gpio_padat = CFG_PADAT; - regp->gpio_reg.gpio_pbcnt = CFG_PBCNT; - regp->gpio_reg.gpio_pbddr = CFG_PBDDR; - regp->gpio_reg.gpio_pbdat = CFG_PBDAT; - regp->gpio_reg.gpio_pdcnt = CFG_PDCNT; - - /* Memory Controller: */ - regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM; - regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM; - -#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) - regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM; - regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM; -#endif - -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM; - regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM; -#endif - -#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) - regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM; - regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM; -#endif - -#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) - regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM; - regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM; -#endif - -#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) - regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM; - regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM; -#endif - -#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) - regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM; - regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM; -#endif - -#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) - regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM; - regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM; -#endif - -#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ - - /* enable instruction cache now */ - icache_enable(); - -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r (void) -{ - return (0); -} -#endif /* #if defined(CONFIG_M5272) */ - - -#ifdef CONFIG_M5282 -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f (void) -{ - -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r (void) -{ - return (0); -} -#endif - -#if defined(CONFIG_M5249) -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f (void) -{ -#ifndef CFG_PLL_BYPASS - /* - * Setup the PLL to run at the specified speed - * - */ - volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); - unsigned long pllcr; -#ifdef CFG_FAST_CLK - pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ -#else - pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ -#endif - cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ - pllcr ^= 0x00000001; /* Set pll bypass to 1 */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ - udelay(0x20); /* Wait for a lock ... */ -#endif /* #ifndef CFG_PLL_BYPASS */ - - /* - * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins - * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins - * which is their primary function. - * ~Jeremy - */ - mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC); - mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC); - mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN); - mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN); - mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT); - mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT); - - /* - * dBug Compliance: - * You can verify these values by using dBug's 'ird' - * (Internal Register Display) command - * ~Jeremy - * - */ - mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ - mbar_writeByte(MCFSIM_SYPCR, 0x00); - mbar_writeByte(MCFSIM_SWIVR, 0x0f); - mbar_writeByte(MCFSIM_SWSR, 0x00); - mbar_writeLong(MCFSIM_IMR, 0xfffffbff); - mbar_writeByte(MCFSIM_SWDICR, 0x00); - mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); - mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); - mbar_writeByte(MCFSIM_I2CICR, 0x00); - mbar_writeByte(MCFSIM_UART1ICR, 0x00); - mbar_writeByte(MCFSIM_UART2ICR, 0x00); - mbar_writeByte(MCFSIM_ICR6, 0x00); - mbar_writeByte(MCFSIM_ICR7, 0x00); - mbar_writeByte(MCFSIM_ICR8, 0x00); - mbar_writeByte(MCFSIM_ICR9, 0x00); - mbar_writeByte(MCFSIM_QSPIICR, 0x00); - - mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); - mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ - mbar2_writeByte(MCFSIM_SPURVEC, 0x00); - mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ - - /* Setup interrupt priorities for gpio7 */ - /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ - - /* IDE Config registers */ - mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); - mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); - - /* - * Setup chip selects... - */ - - mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1); - mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1); - mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1); - - mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0); - mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0); - mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0); - - /* enable instruction cache now */ - icache_enable(); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r (void) -{ - return (0); -} -#endif /* #if defined(CONFIG_M5249) */ diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c deleted file mode 100644 index a5c50af..0000000 --- a/cpu/mcf52x2/fec.c +++ /dev/null @@ -1,569 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_M5272 -#include -#include -#endif - -#ifdef CONFIG_M5282 -#include -#include -#endif - -#include -#include - -#ifdef CONFIG_M5272 -#define FEC_ADDR (CFG_MBAR + 0x840) -#endif -#ifdef CONFIG_M5282 -#define FEC_ADDR (CFG_MBAR + 0x1000) -#endif - -#undef ET_DEBUG -#undef MII_DEBUG - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) - -#ifdef CFG_DISCOVER_PHY -#include -static void mii_discover_phy (void); -#endif - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 100 - -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 -#define PKT_MAXBLR_SIZE 1520 - - -static char txbuf[DBUF_LENGTH]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FEC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx = NULL; - -int eth_send (volatile void *packet, int length) -{ - int j, rc; - volatile fec_t *fecp = (fec_t *) (FEC_ADDR); - - /* section 16.9.23.3 - * Wait for ready - */ - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) - && (j < TOUT_LOOP)) { - udelay (1); - j++; - } - if (j >= TOUT_LOOP) { - printf ("TX not ready\n"); - } - - rtx->txbd[txIdx].cbd_bufaddr = (uint) packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST; - - /* Activate transmit Buffer Descriptor polling */ - fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */ - - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) - && (j < TOUT_LOOP)) { - udelay (1); - j++; - } - if (j >= TOUT_LOOP) { - printf ("TX timeout\n"); - } -#ifdef ET_DEBUG - printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", - __FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc, - (rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2); -#endif - - /* return only status bits */ ; - rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS); - - txIdx = (txIdx + 1) % TX_BUF_CNT; - - return rc; -} - -int eth_rx (void) -{ - int length; - volatile fec_t *fecp = (fec_t *) FEC_ADDR; - - for (;;) { - /* section 16.9.23.2 */ - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { -#ifdef ET_DEBUG - printf ("%s[%d] err: %x\n", - __FUNCTION__, __LINE__, - rtx->rxbd[rxIdx].cbd_sc); -#endif - } else { - /* Pass the packet up to the protocol layers. */ - NetReceive (NetRxPackets[rxIdx], length - 4); - } - - /* Give the buffer back to the FEC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - - /* Try to fill Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - } - - return length; -} - -/************************************************************** - * - * FEC Ethernet Initialization Routine - * - *************************************************************/ -#define FEC_ECNTRL_ETHER_EN 0x00000002 -#define FEC_ECNTRL_RESET 0x00000001 - -#define FEC_RCNTRL_BC_REJ 0x00000010 -#define FEC_RCNTRL_PROM 0x00000008 -#define FEC_RCNTRL_MII_MODE 0x00000004 -#define FEC_RCNTRL_DRT 0x00000002 -#define FEC_RCNTRL_LOOP 0x00000001 - -#define FEC_TCNTRL_FDEN 0x00000004 -#define FEC_TCNTRL_HBC 0x00000002 -#define FEC_TCNTRL_GTS 0x00000001 - -#define FEC_RESET_DELAY 50000 - -int eth_init (bd_t * bd) -{ - - int i; - volatile fec_t *fecp = (fec_t *) (FEC_ADDR); - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - fecp->fec_ecntrl = FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) { - printf ("FEC_RESET_DELAY timeout\n"); - return 0; - } - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt */ - fecp->fec_ievent = 0xffffffff; - - /* Set station address */ -#define ea bd->bi_enetaddr - fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | - (ea[2] << 8) | (ea[3]); - fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16); -#ifdef ET_DEBUG - printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n", - ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); -#endif -#undef ea - - /* Clear multicast address hash table - */ - fecp->fec_hash_table_high = 0; - fecp->fec_hash_table_low = 0; - - /* Set maximum receive buffer size. - */ - fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; - - /* - * Setup Buffers and Buffer Desriptors - */ - rxIdx = 0; - txIdx = 0; - - if (!rtx) { - rtx = (RTXBD *) CFG_ENET_BD_BASE; - } - - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; - } - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Last, Tx CRC - */ - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* Set receive and transmit descriptor base - */ - fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]); - fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]); - - /* Enable MII mode - */ -#if 0 /* Full duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; - fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; -#else /* Half duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; - fecp->fec_x_cntrl = 0; -#endif - /* Set MII speed */ - fecp->fec_mii_speed = 0x0e; - - /* Configure port B for MII. - */ - /* port initialization was already made in cpu_init_f() */ - - /* Now enable the transmit and receive processing - */ - fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN; - -#ifdef CFG_DISCOVER_PHY - /* wait for the PHY to wake up after reset */ - mii_discover_phy (); -#endif - - /* And last, try to fill Rx Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - - return 1; -} - -void eth_halt (void) -{ - volatile fec_t *fecp = (fec_t *) FEC_ADDR; - - fecp->fec_ecntrl = 0; -} - - -#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) - -static int phyaddr = -1; /* didn't find a PHY yet */ -static uint phytype; - -/* Make MII read/write commands for the FEC. -*/ - -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18) | \ - (VAL & 0xffff)) - -/* Interrupt events/masks. -*/ -#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ -#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ -#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ -#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ -#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ -#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ -#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ -#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ -#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ -#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ - -/* PHY identification - */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ - -/* send command to phy using mii, wait for result */ -static uint mii_send (uint mii_cmd) -{ - uint mii_reply; - volatile fec_t *ep = (fec_t *) (FEC_ADDR); - - ep->fec_mii_data = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */ - mii_reply = ep->fec_mii_data; /* result from phy */ - ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ - -#if defined(CFG_DISCOVER_PHY) -static void mii_discover_phy (void) -{ -#define MAX_PHY_PASSES 11 - uint phyno; - int pass; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay (10000); /* wait 10ms */ - } - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf ("PHY type 0x%x pass %d type ", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= mii_send (mk_mii_read (phyno, - PHY_PHYIDR2)); - -#ifdef ET_DEBUG - printf ("PHY @ 0x%x pass %d type ", phyno, - pass); - switch (phytype & 0xfffffff0) { - case PHY_ID_LXT970: - printf ("LXT970\n"); - break; - case PHY_ID_LXT971: - printf ("LXT971\n"); - break; - case PHY_ID_82555: - printf ("82555\n"); - break; - case PHY_ID_QS6612: - printf ("QS6612\n"); - break; - case PHY_ID_AMD79C784: - printf ("AMD79C784\n"); - break; - case PHY_ID_LSI80225B: - printf ("LSI L80225/B\n"); - break; - default: - printf ("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) { - printf ("No PHY device found.\n"); - } -} -#endif /* CFG_DISCOVER_PHY */ - -#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) - -static int mii_init_done = 0; - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_init (void) -{ - volatile fec_t *fecp = (fec_t *) (FEC_ADDR); - - int i; - - if (mii_init_done != 0) { - return; - } - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - - fecp->fec_ecntrl = FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) { - printf ("FEC_RESET_DELAY timeout\n"); - return; - } - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt - */ - fecp->fec_ievent = 0xffffffff; - - /* Set MII speed */ - fecp->fec_mii_speed = 0x0e; - - /* Configure port B for MII. - */ - /* port initialization was already made in cpu_init_f() */ - - /* Now enable the transmit and receive processing */ - fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN; - - mii_init_done = 1; -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcf52x2_miiphy_read (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send (mk_mii_read (addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf ("0x%04x\n", *value); -#endif - - return 0; -} - -int mcf52x2_miiphy_write (char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send (mk_mii_write (addr, reg, value)); - -#ifdef MII_DEBUG - printf ("0x%04x\n", value); -#endif - - return 0; -} -#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */ -#endif /* CFG_CMD_NET, FEC_ENET */ - -int mcf52x2_miiphy_initialize(bd_t *bis) -{ -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) -#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) - miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write); -#endif -#endif - return 0; -} diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c deleted file mode 100644 index 868df39..0000000 --- a/cpu/mcf52x2/interrupts.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * (C) Copyright 2003 Josef Baumgartner - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_M5272 -#include -#include -#endif - -#ifdef CONFIG_M5282 -#include -#include -#endif - -#ifdef CONFIG_M5249 -#include -#endif - - -#define NR_IRQS 31 - -/* - * Interrupt vector functions. - */ -struct interrupt_action { - interrupt_handler_t *handler; - void *arg; -}; - -static struct interrupt_action irq_vecs[NR_IRQS]; - -static __inline__ unsigned short get_sr (void) -{ - unsigned short sr; - - asm volatile ("move.w %%sr,%0":"=r" (sr):); - - return sr; -} - -static __inline__ void set_sr (unsigned short sr) -{ - asm volatile ("move.w %0,%%sr"::"r" (sr)); -} - -/************************************************************************/ -/* - * Install and free an interrupt handler - */ -void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) -{ -#ifdef CONFIG_M5272 - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); -#endif - int vec_base = 0; - -#ifdef CONFIG_M5272 - vec_base = intp->int_pivr & 0xe0; -#endif - - if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) { - printf ("irq_install_handler: wrong interrupt vector %d\n", - vec); - return; - } - - irq_vecs[vec - vec_base].handler = handler; - irq_vecs[vec - vec_base].arg = arg; -} - -void irq_free_handler (int vec) -{ -#ifdef CONFIG_M5272 - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); -#endif - int vec_base = 0; - -#ifdef CONFIG_M5272 - vec_base = intp->int_pivr & 0xe0; -#endif - - if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) { - return; - } - - irq_vecs[vec - vec_base].handler = NULL; - irq_vecs[vec - vec_base].arg = NULL; -} - -void enable_interrupts (void) -{ - unsigned short sr; - - sr = get_sr (); - set_sr (sr & ~0x0700); -} - -int disable_interrupts (void) -{ - unsigned short sr; - - sr = get_sr (); - set_sr (sr | 0x0700); - - return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */ -} - -void int_handler (struct pt_regs *fp) -{ -#ifdef CONFIG_M5272 - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); -#endif - int vec, vec_base = 0; - - vec = (fp->vector >> 2) & 0xff; -#ifdef CONFIG_M5272 - vec_base = intp->int_pivr & 0xe0; -#endif - - if (irq_vecs[vec - vec_base].handler != NULL) { - irq_vecs[vec - - vec_base].handler (irq_vecs[vec - vec_base].arg); - } else { - printf ("\nBogus External Interrupt Vector %d\n", vec); - } -} - - -#ifdef CONFIG_M5272 -int interrupt_init (void) -{ - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); - - /* disable all external interrupts */ - intp->int_icr1 = 0x88888888; - intp->int_icr2 = 0x88888888; - intp->int_icr3 = 0x88888888; - intp->int_icr4 = 0x88888888; - intp->int_pitr = 0x00000000; - /* initialize vector register */ - intp->int_pivr = 0x40; - - enable_interrupts (); - - return 0; -} -#endif - -#ifdef CONFIG_M5282 -int interrupt_init (void) -{ - return 0; -} -#endif - -#ifdef CONFIG_M5249 -int interrupt_init (void) -{ - enable_interrupts (); - - return 0; -} -#endif diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c deleted file mode 100644 index c730922..0000000 --- a/cpu/mcf52x2/serial.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include - -#ifdef CONFIG_M5272 -#include -#endif - -#ifdef CONFIG_M5282 -#include -#endif - -#ifdef CONFIG_M5249 -#include -#endif - -#ifdef CONFIG_M5249 -#define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a)) -#else -#define DoubleClock(a) ((double)(CFG_CLK) / 32.0 / (double)(a)) -#endif - -void rs_serial_setbaudrate(int port,int baudrate) -{ -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) - volatile unsigned char *uartp; - double clock, fraction; - - if (port == 0) - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - else - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - - clock = DoubleClock(baudrate); /* Set baud above */ - - fraction = ((clock - (int)clock) * 16.0) + 0.5; - - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ - uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ - uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ -#endif -}; - -void rs_serial_init(int port,int baudrate) -{ - volatile unsigned char *uartp; - - /* - * Reset UART, get it into known state... - */ - if (port == 0) - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - else - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ - - /* - * Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity. - */ - uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8; - uartp[MCFUART_UMR] = MCFUART_MR2_STOP1; - - rs_serial_setbaudrate(port,baudrate); - - uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER; - uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE; - - return; -} - -/****************************************************************************/ -/* - * Output a single character, using UART polled mode. - * This is used for console output. - */ - -void rs_put_char(char ch) -{ - volatile unsigned char *uartp; - int i; - - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - - for (i = 0; (i < 0x10000); i++) { - if (uartp[MCFUART_USR] & MCFUART_USR_TXREADY) - break; - } - uartp[MCFUART_UTB] = ch; - return; -} - -int rs_is_char(void) -{ - volatile unsigned char *uartp; - - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - return((uartp[MCFUART_USR] & MCFUART_USR_RXREADY) ? 1 : 0); -} - -int rs_get_char(void) -{ - volatile unsigned char *uartp; - - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - return(uartp[MCFUART_URB]); -} - -void serial_setbrg(void) { - DECLARE_GLOBAL_DATA_PTR; - rs_serial_setbaudrate(0,gd->bd->bi_baudrate); -} - -int serial_init(void) { - DECLARE_GLOBAL_DATA_PTR; - rs_serial_init(0,gd->baudrate); - return 0; -} - - -void serial_putc(const char c) { - if (c == '\n') - serial_putc ('\r'); - rs_put_char(c); -} - -void serial_puts (const char *s) { - while (*s) { - serial_putc(*s++); - } -} - -int serial_getc(void) { - while(!rs_is_char()); - return rs_get_char(); -} - -int serial_tstc() { - return rs_is_char(); -} diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c deleted file mode 100644 index 519c992..0000000 --- a/cpu/mcf52x2/speed.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2003 - * Josef Baumgartner - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* - * get_clocks() fills in gd->cpu_clock and gd->bus_clk - */ -int get_clocks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->cpu_clk = CFG_CLK; -#ifdef CONFIG_M5249 - gd->bus_clk = gd->cpu_clk / 2; -#else - gd->bus_clk = gd->cpu_clk; -#endif - return (0); -} diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S deleted file mode 100644 index b4926e2..0000000 --- a/cpu/mcf52x2/start.S +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright (C) 2003 Josef Baumgartner - * Based on code from Bernhard Kuhn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include "version.h" - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - - -#define _START _start -#define _FAULT _fault - - -#define SAVE_ALL \ - move.w #0x2700,%sr; /* disable intrs */ \ - subl #60,%sp; /* space for 15 regs */ \ - moveml %d0-%d7/%a0-%a6,%sp@; \ - -#define RESTORE_ALL \ - moveml %sp@,%d0-%d7/%a0-%a6; \ - addl #60,%sp; /* space for 15 regs */ \ - rte - -/* If we come from a pre-loader we don't need an initial exception - * table. - */ -#if !defined(CONFIG_MONITOR_IS_IN_RAM) - -.text -/* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. - */ -_vectors: - -.long 0x00000000, _START -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -#endif - - .text - - .globl _start -_start: - nop - nop - move.w #0x2700,%sr - - /* if we come from a pre-loader we have no exception table and - * therefore no VBR to set - */ -#if !defined(CONFIG_MONITOR_IS_IN_RAM) - move.l #CFG_FLASH_BASE, %d0 - movec %d0, %VBR -#endif - -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) - move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */ - move.c %d0, %MBAR - - /*** The 5249 has MBAR2 as well ***/ -#ifdef CFG_MBAR2 - move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */ - movec %d0, #0xc0e /* Set MBAR2 */ -#endif - - move.l #(CFG_INIT_RAM_ADDR + 1), %d0 - movec %d0, %RAMBAR0 -#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */ - -#ifdef CONFIG_M5282 - /* Initialize IPSBAR */ - move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ - move.l %d0, 0x40000000 - - /* Initialize FLASHBAR: locate internal Flash and validate it */ - move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 - movec %d0, %RAMBAR0 - - /* Initialize RAMBAR1: locate SRAM and validate it */ - move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 - movec %d0, %RAMBAR1 -#endif - - /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp - clr.l %sp@- - - move.l #__got_start, %a5 /* put relocation table address to a5 */ - - bsr cpu_init_f /* run low-level CPU init code (from flash) */ - bsr board_init_f /* run low-level board init code (from flash) */ - - /* board_init_f() does not return - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ - - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ - - move.l #CFG_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 - - /* copy the code to RAM */ -1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - move.l %a0, %a1 - add.l #(in_ram - CFG_MONITOR_BASE), %a1 - jmp (%a1) - -in_ram: - -clear_bss: - /* - * Now clear BSS segment - */ - move.l %a0, %a1 - add.l #(_sbss - CFG_MONITOR_BASE),%a1 - move.l %a0, %d1 - add.l #(_ebss - CFG_MONITOR_BASE),%d1 -6: - clr.l (%a1)+ - cmp.l %a1,%d1 - bgt.s 6b - - /* - * fix got table in RAM - */ - move.l %a0, %a1 - add.l #(__got_start - CFG_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ - - move.l %a0, %a2 - add.l #(__got_end - CFG_MONITOR_BASE),%a2 - -7: - move.l (%a1),%d1 - sub.l #_start,%d1 - add.l %a0,%d1 - move.l %d1,(%a1)+ - cmp.l %a2, %a1 - bne 7b - - /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CFG_MONITOR_BASE), %a1 - - /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ - jsr (%a1) - -/*------------------------------------------------------------------------------*/ -/* exception code */ - .globl _fault -_fault: - jmp _fault - - .globl _exc_handler -_exc_handler: - SAVE_ALL - movel %sp,%sp@- - bsr exc_handler - addql #4,%sp - RESTORE_ALL - - .globl _int_handler -_int_handler: - SAVE_ALL - movel %sp,%sp@- - bsr int_handler - addql #4,%sp - RESTORE_ALL - -/*------------------------------------------------------------------------------*/ -/* cache functions */ -#ifdef CONFIG_M5272 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0xff00c000, %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - -#ifdef CONFIG_M5282 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0xff00c000, %d0 /* Setup cache mask */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - -#ifdef CONFIG_M5249 - .globl icache_enable -icache_enable: - /* - * Note: The 5249 Documentation doesn't give a bit position for CINV! - * From the 5272 and the 5307 documentation, I have deduced that it is - * probably CACR[24]. Should someone say something to Motorola? - * ~Jeremy - */ - move.l #0x01000000, %d0 /* Invalidate whole cache */ - move.c %d0,%CACR - move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */ - move.c %d0, %ACR0 - move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */ - move.c %d0, %ACR1 - move.l #0x90000200, %d0 /* Set cache enable cmd */ - move.c %d0,%CACR - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - - .globl icache_disable -icache_disable: - move.l #0x00000100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - clr.l %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - movec %d0, %ACR1 /* Enable cache */ - moveq #0, %d0 - move.l %d0, icache_state - rts - - .globl icache_status -icache_status: - move.l icache_state, %d0 - rts - - .data -icache_state: - .long 1 - - -/*------------------------------------------------------------------------------*/ - - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile deleted file mode 100644 index 610043e..0000000 --- a/cpu/microblaze/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = cpu.o interrupts.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/microblaze/cpu.c b/cpu/microblaze/cpu.c deleted file mode 100644 index 4d2b270..0000000 --- a/cpu/microblaze/cpu.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* EMPTY FILE */ diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c deleted file mode 100644 index ccf67e1..0000000 --- a/cpu/microblaze/interrupts.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -void enable_interrupts(void) -{ -} - -int disable_interrupts(void) -{ - return 0; -} diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S deleted file mode 100644 index 7efdbb0..0000000 --- a/cpu/microblaze/start.S +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - - .text - .global _start -_start: - - addi r1, r0, CFG_SDRAM_BASE /* init stack pointer */ - addi r1, r1, CFG_SDRAM_SIZE /* set sp to high up */ - - brai board_init - -1: bri 1b diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile deleted file mode 100644 index c8b30c7..0000000 --- a/cpu/mips/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \ - cpu.o interrupts.o incaip_clock.o -SOBJS = incaip_wdt.o cache.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/mips/asc_serial.c b/cpu/mips/asc_serial.c deleted file mode 100644 index d95ec3f..0000000 --- a/cpu/mips/asc_serial.c +++ /dev/null @@ -1,371 +0,0 @@ -/* - * (INCA) ASC UART support - */ - -#include - -#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP) - -#ifdef CONFIG_PURPLE -#define serial_init asc_serial_init -#define serial_putc asc_serial_putc -#define serial_puts asc_serial_puts -#define serial_getc asc_serial_getc -#define serial_tstc asc_serial_tstc -#define serial_setbrg asc_serial_setbrg -#endif - -#include -#include -#include "asc_serial.h" - -#ifdef CONFIG_PURPLE - -#undef ASC_FIFO_PRESENT -#define TOUT_LOOP 100000 - -/* Set base address for second FPI interrupt control register bank */ -#define SFPI_INTCON_BASEADDR 0xBF0F0000 - -/* Register offset from base address */ -#define FBS_ISR 0x00000000 /* Interrupt status register */ -#define FBS_IMR 0x00000008 /* Interrupt mask register */ -#define FBS_IDIS 0x00000010 /* Interrupt disable register */ - -/* Interrupt status register bits */ -#define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */ -#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */ -#define FBS_ISR_AE 0x00000010 /* ASC error interrupt */ -#define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */ -#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */ -#define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */ - -#else - -#define ASC_FIFO_PRESENT - -#endif - - -#define SET_BIT(reg, mask) reg |= (mask) -#define CLEAR_BIT(reg, mask) reg &= (~mask) -#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) -#define SET_BITS(reg, mask) SET_BIT(reg, mask) -#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} - -extern uint incaip_get_fpiclk(void); - -static int serial_setopt (void); - -/* pointer to ASC register base address */ -static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC; - -/****************************************************************************** -* -* serial_init - initialize a INCAASC channel -* -* This routine initializes the number of data bits, parity -* and set the selected baud rate. Interrupts are disabled. -* Set the modem control signals if the option is selected. -* -* RETURNS: N/A -*/ - -int serial_init (void) -{ -#ifdef CONFIG_INCA_IP - /* we have to set PMU.EN13 bit to enable an ASC device*/ - INCAASC_PMU_ENABLE(13); -#endif - - /* and we have to set CLC register*/ - CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS); - SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001); - - /* initialy we are in async mode */ - pAsc->asc_con = ASCCON_M_8ASYNC; - - /* select input port */ - pAsc->asc_pisel = (CONSOLE_TTY & 0x1); - -#ifdef ASC_FIFO_PRESENT - /* TXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK, - ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL); - /* enable TXFIFO */ - SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN); - - /* RXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK, - ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL); - /* enable RXFIFO */ - SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN); -#endif - - /* enable error signals */ - SET_BIT(pAsc->asc_con, ASCCON_FEN); - SET_BIT(pAsc->asc_con, ASCCON_OEN); - -#ifdef CONFIG_INCA_IP - /* acknowledge ASC interrupts */ - ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL); - - /* disable ASC interrupts */ - ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL); -#endif - -#ifdef ASC_FIFO_PRESENT - /* set FIFOs into the transparent mode */ - SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN); - SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN); -#endif - - /* set baud rate */ - serial_setbrg(); - - /* set the options */ - serial_setopt(); - - return 0; -} - -void serial_setbrg (void) -{ - ulong uiReloadValue, fdv; - ulong f_ASC; - -#ifdef CONFIG_INCA_IP - f_ASC = incaip_get_fpiclk(); -#else - f_ASC = ASC_CLOCK_RATE; -#endif - -#ifndef INCAASC_USE_FDV - fdv = 2; - uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; -#else - fdv = INCAASC_FDV_HIGH_BAUDRATE; - uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; -#endif /* INCAASC_USE_FDV */ - - if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) - { -#ifndef INCAASC_USE_FDV - fdv = 3; - uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; -#else - fdv = INCAASC_FDV_LOW_BAUDRATE; - uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; -#endif /* INCAASC_USE_FDV */ - - if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) - { - return; /* can't impossibly generate that baud rate */ - } - } - - /* Disable Baud Rate Generator; BG should only be written when R=0 */ - CLEAR_BIT(pAsc->asc_con, ASCCON_R); - -#ifndef INCAASC_USE_FDV - /* - * Disable Fractional Divider (FDE) - * Divide clock by reload-value + constant (BRS) - */ - /* FDE = 0 */ - CLEAR_BIT(pAsc->asc_con, ASCCON_FDE); - - if ( fdv == 2 ) - CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */ - else - SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */ - -#else /* INCAASC_USE_FDV */ - - /* Enable Fractional Divider */ - SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */ - - /* Set fractional divider value */ - pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK; - -#endif /* INCAASC_USE_FDV */ - - /* Set reload value in BG */ - pAsc->asc_bg = uiReloadValue; - - /* Enable Baud Rate Generator */ - SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */ -} - -/******************************************************************************* -* -* serial_setopt - set the serial options -* -* Set the channel operating mode to that specified. Following options -* are supported: CREAD, CSIZE, PARENB, and PARODD. -* -* Note, this routine disables the transmitter. The calling routine -* may have to re-enable it. -* -* RETURNS: -* Returns 0 to indicate success, otherwise -1 is returned -*/ - -static int serial_setopt (void) -{ - ulong con; - - switch ( ASC_OPTIONS & ASCOPT_CSIZE ) - { - /* 7-bit-data */ - case ASCOPT_CS7: - con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */ - break; - - /* 8-bit-data */ - case ASCOPT_CS8: - if ( ASC_OPTIONS & ASCOPT_PARENB ) - con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */ - else - con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */ - break; - - /* - * only 7 and 8-bit frames are supported - * if we don't use IOCTL extensions - */ - default: - return -1; - } - - if ( ASC_OPTIONS & ASCOPT_STOPB ) - SET_BIT(con, ASCCON_STP); /* 2 stop bits */ - else - CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */ - - if ( ASC_OPTIONS & ASCOPT_PARENB ) - SET_BIT(con, ASCCON_PEN); /* enable parity checking */ - else - CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */ - - if ( ASC_OPTIONS & ASCOPT_PARODD ) - SET_BIT(con, ASCCON_ODD); /* odd parity */ - else - CLEAR_BIT(con, ASCCON_ODD); /* even parity */ - - if ( ASC_OPTIONS & ASCOPT_CREAD ) - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */ - - pAsc->asc_con |= con; - - return 0; -} - -void serial_putc (const char c) -{ -#ifdef ASC_FIFO_PRESENT - uint txFl = 0; -#else - uint timeout = 0; -#endif - - if (c == '\n') serial_putc ('\r'); - -#ifdef ASC_FIFO_PRESENT - /* check do we have a free space in the TX FIFO */ - /* get current filling level */ - do - { - txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; - } - while ( txFl == INCAASC_TXFIFO_FULL ); -#else - - while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & - FBS_ISR_AB)) - { - if (timeout++ > TOUT_LOOP) - { - break; - } - } -#endif - - pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */ - -#ifndef ASC_FIFO_PRESENT - *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB | - FBS_ISR_AT; -#endif - - /* check for errors */ - if ( pAsc->asc_con & ASCCON_OE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); - return; - } -} - -void serial_puts (const char *s) -{ - while (*s) - { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - ulong symbol_mask; - char c; - - while (!serial_tstc()); - - symbol_mask = - ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff); - - c = (char)(pAsc->asc_rbuf & symbol_mask); - -#ifndef ASC_FIFO_PRESENT - *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR; -#endif - - return c; -} - -int serial_tstc (void) -{ - int res = 1; - -#ifdef ASC_FIFO_PRESENT - if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) - { - res = 0; - } -#else - if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & - FBS_ISR_AR)) - - { - res = 0; - } -#endif - else if ( pAsc->asc_con & ASCCON_FE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_PE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_OE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); - res = 0; - } - - return res; -} -#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */ diff --git a/cpu/mips/asc_serial.h b/cpu/mips/asc_serial.h deleted file mode 100644 index 7ffdcfa..0000000 --- a/cpu/mips/asc_serial.h +++ /dev/null @@ -1,177 +0,0 @@ -/* incaAscSio.h - (INCA) ASC UART tty driver header */ - -#ifndef __INCincaAscSioh -#define __INCincaAscSioh - -#include - -/* channel operating modes */ -#define ASCOPT_CSIZE 0x00000003 -#define ASCOPT_CS7 0x00000001 -#define ASCOPT_CS8 0x00000002 -#define ASCOPT_PARENB 0x00000004 -#define ASCOPT_STOPB 0x00000008 -#define ASCOPT_PARODD 0x00000010 -#define ASCOPT_CREAD 0x00000020 - -#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) - -/* ASC input select (0 or 1) */ -#define CONSOLE_TTY 0 - -/* use fractional divider for baudrate settings */ -#define INCAASC_USE_FDV - -#ifdef INCAASC_USE_FDV - #define INCAASC_FDV_LOW_BAUDRATE 71 - #define INCAASC_FDV_HIGH_BAUDRATE 453 -#endif /*INCAASC_USE_FDV*/ - - -#define INCAASC_TXFIFO_FL 1 -#define INCAASC_RXFIFO_FL 1 -#define INCAASC_TXFIFO_FULL 16 - -/* interrupt lines masks for the ASC device interrupts*/ -/* change these macroses if it's necessary */ -#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */ - -#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */ -#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */ -#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */ -#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/ - -/* interrupt controller access macros */ -#define ASC_INTERRUPTS_ENABLE(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X; -#define ASC_INTERRUPTS_DISABLE(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X; -#define ASC_INTERRUPTS_CLEAR(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X; - -/* CLC register's bits and bitfields */ -#define ASCCLC_DISR 0x00000001 -#define ASCCLC_DISS 0x00000002 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 - -/* CON register's bits and bitfields */ -#define ASCCON_MODEMASK 0x0007 - #define ASCCON_M_8SYNC 0x0 - #define ASCCON_M_8ASYNC 0x1 - #define ASCCON_M_8IRDAASYNC 0x2 - #define ASCCON_M_7ASYNCPAR 0x3 - #define ASCCON_M_9ASYNC 0x4 - #define ASCCON_M_8WAKEUPASYNC 0x5 - #define ASCCON_M_8ASYNCPAR 0x7 -#define ASCCON_STP 0x0008 -#define ASCCON_REN 0x0010 -#define ASCCON_PEN 0x0020 -#define ASCCON_FEN 0x0040 -#define ASCCON_OEN 0x0080 -#define ASCCON_PE 0x0100 -#define ASCCON_FE 0x0200 -#define ASCCON_OE 0x0400 -#define ASCCON_FDE 0x0800 -#define ASCCON_ODD 0x1000 -#define ASCCON_BRS 0x2000 -#define ASCCON_LB 0x4000 -#define ASCCON_R 0x8000 - -/* WHBCON register's bits and bitfields */ -#define ASCWHBCON_CLRREN 0x0010 -#define ASCWHBCON_SETREN 0x0020 -#define ASCWHBCON_CLRPE 0x0100 -#define ASCWHBCON_CLRFE 0x0200 -#define ASCWHBCON_CLROE 0x0400 -#define ASCWHBCON_SETPE 0x0800 -#define ASCWHBCON_SETFE 0x1000 -#define ASCWHBCON_SETOE 0x2000 - -/* ABCON register's bits and bitfields */ -#define ASCABCON_ABEN 0x0001 -#define ASCABCON_AUREN 0x0002 -#define ASCABCON_ABSTEN 0x0004 -#define ASCABCON_ABDETEN 0x0008 -#define ASCABCON_FCDETEN 0x0010 -#define ASCABCON_EMMASK 0x0300 - #define ASCABCON_EMOFF 8 - #define ASCABCON_EM_DISAB 0x0 - #define ASCABCON_EM_DURAB 0x1 - #define ASCABCON_EM_ALWAYS 0x2 -#define ASCABCON_TXINV 0x0400 -#define ASCABCON_RXINV 0x0800 - -/* FDV register mask, offset and bitfields*/ -#define ASCFDV_VALUE_MASK 0x000001FF - -/* WHBABCON register's bits and bitfields */ -#define ASCWHBABCON_SETABEN 0x0001 -#define ASCWHBABCON_CLRABEN 0x0002 - -/* ABSTAT register's bits and bitfields */ -#define ASCABSTAT_FCSDET 0x0001 -#define ASCABSTAT_FCCDET 0x0002 -#define ASCABSTAT_SCSDET 0x0004 -#define ASCABSTAT_SCCDET 0x0008 -#define ASCABSTAT_DETWAIT 0x0010 - -/* WHBABSTAT register's bits and bitfields */ -#define ASCWHBABSTAT_CLRFCSDET 0x0001 -#define ASCWHBABSTAT_SETFCSDET 0x0002 -#define ASCWHBABSTAT_CLRFCCDET 0x0004 -#define ASCWHBABSTAT_SETFCCDET 0x0008 -#define ASCWHBABSTAT_CLRSCSDET 0x0010 -#define ASCWHBABSTAT_SETSCSDET 0x0020 -#define ASCWHBABSTAT_SETSCCDET 0x0040 -#define ASCWHBABSTAT_CLRSCCDET 0x0080 -#define ASCWHBABSTAT_CLRDETWAIT 0x0100 -#define ASCWHBABSTAT_SETDETWAIT 0x0200 - -/* TXFCON register's bits and bitfields */ -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXTMEN 0x0004 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 - -/* RXFCON register's bits and bitfields */ -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXTMEN 0x0004 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 - -/* FSTAT register's bits and bitfields */ -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - -#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT); - -typedef struct /* incaAsc_t */ -{ - volatile unsigned long asc_clc; /*0x0000*/ - volatile unsigned long asc_pisel; /*0x0004*/ - volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/ - volatile unsigned long asc_con; /*0x0010*/ - volatile unsigned long asc_bg; /*0x0014*/ - volatile unsigned long asc_fdv; /*0x0018*/ - volatile unsigned long asc_pmw; /* not used */ /*0x001C*/ - volatile unsigned long asc_tbuf; /*0x0020*/ - volatile unsigned long asc_rbuf; /*0x0024*/ - volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/ - volatile unsigned long asc_abcon; /*0x0030*/ - volatile unsigned long asc_abstat; /* not used */ /*0x0034*/ - volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/ - volatile unsigned long asc_rxfcon; /*0x0040*/ - volatile unsigned long asc_txfcon; /*0x0044*/ - volatile unsigned long asc_fstat; /*0x0048*/ - volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/ - volatile unsigned long asc_whbcon; /*0x0050*/ - volatile unsigned long asc_whbabcon; /*0x0054*/ - volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/ - -} incaAsc_t; - -#endif /* __INCincaAscSioh */ diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c deleted file mode 100644 index 9ce9b35..0000000 --- a/cpu/mips/au1x00_eth.c +++ /dev/null @@ -1,307 +0,0 @@ -/* Only eth0 supported for now - * - * (C) Copyright 2003 - * Thomas.Lange@corelatus.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include - -#ifdef CONFIG_AU1X00 - -#if defined(CFG_DISCOVER_PHY) -#error "PHY not supported yet" -/* We just assume that we are running 100FD for now */ -/* We all use switches, right? ;-) */ -#endif - -/* I assume ethernet behaves like au1000 */ - -#ifdef CONFIG_AU1000 -/* Base address differ between cpu:s */ -#define ETH0_BASE AU1000_ETH0_BASE -#define MAC0_ENABLE AU1000_MAC0_ENABLE -#else -#ifdef CONFIG_AU1100 -#define ETH0_BASE AU1100_ETH0_BASE -#define MAC0_ENABLE AU1100_MAC0_ENABLE -#else -#ifdef CONFIG_AU1500 -#define ETH0_BASE AU1500_ETH0_BASE -#define MAC0_ENABLE AU1500_MAC0_ENABLE -#else -#ifdef CONFIG_AU1550 -#define ETH0_BASE AU1550_ETH0_BASE -#define MAC0_ENABLE AU1550_MAC0_ENABLE -#else -#error "No valid cpu set" -#endif -#endif -#endif -#endif - -#include -#include -#include -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_MII) -#include -#endif - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 -#define PKT_MAXBUF_SIZE 1518 - -static char txbuf[DBUF_LENGTH]; - -static int next_tx; -static int next_rx; - -/* 4 rx and 4 tx fifos */ -#define NO_OF_FIFOS 4 - -typedef struct{ - u32 status; - u32 addr; - u32 len; /* Only used for tx */ - u32 not_used; -} mac_fifo_t; - -mac_fifo_t mac_fifo[NO_OF_FIFOS]; - -#define MAX_WAIT 1000 - -static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){ - volatile mac_fifo_t *fifo_tx = - (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); - int i; - int res; - - /* tx fifo should always be idle */ - fifo_tx[next_tx].len = length; - fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE; - au_sync(); - - udelay(1); - i=0; - while(!(fifo_tx[next_tx].addr&TX_T_DONE)){ - if(i>MAX_WAIT){ - printf("TX timeout\n"); - break; - } - udelay(1); - i++; - } - - /* Clear done bit */ - fifo_tx[next_tx].addr = 0; - fifo_tx[next_tx].len = 0; - au_sync(); - - res = fifo_tx[next_tx].status; - - next_tx++; - if(next_tx>=NO_OF_FIFOS){ - next_tx=0; - } - return(res); -} - -static int au1x00_recv(struct eth_device* dev){ - volatile mac_fifo_t *fifo_rx = - (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS); - - int length; - u32 status; - - for(;;){ - if(!(fifo_rx[next_rx].addr&RX_T_DONE)){ - /* Nothing has been received */ - return(-1); - } - - status = fifo_rx[next_rx].status; - - length = status&0x3FFF; - - if(status&RX_ERROR){ - printf("Rx error 0x%x\n", status); - } - else{ - /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[next_rx], length - 4); - } - - fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE; - - next_rx++; - if(next_rx>=NO_OF_FIFOS){ - next_rx=0; - } - } /* for */ - - return(0); /* Does anyone use this? */ -} - -static int au1x00_init(struct eth_device* dev, bd_t * bd){ - - volatile u32 *macen = (volatile u32*)MAC0_ENABLE; - volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL); - volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH); - volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW); - volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH); - volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW); - volatile mac_fifo_t *fifo_tx = - (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); - volatile mac_fifo_t *fifo_rx = - (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS); - int i; - - next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr); - next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr); - - /* We have to enable clocks before releasing reset */ - *macen = MAC_EN_CLOCK_ENABLE; - udelay(10); - - /* Enable MAC0 */ - /* We have to release reset before accessing registers */ - *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0| - MAC_EN_RESET1|MAC_EN_RESET2; - udelay(10); - - for(i=0;ienetaddr - *mac_addr_high = (ea[5] << 8) | (ea[4] ) ; - *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) | - (ea[1] << 8) | (ea[0] ) ; -#undef ea - *mac_mcast_low = 0; - *mac_mcast_high = 0; - - /* Make sure the MAC buffer is in the correct endian mode */ -#ifdef __LITTLE_ENDIAN - *mac_ctrl = MAC_FULL_DUPLEX; - udelay(1); - *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE; -#else - *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX; - udelay(1); - *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE; -#endif - - return(1); -} - -static void au1x00_halt(struct eth_device* dev){ -} - -int au1x00_enet_initialize(bd_t *bis){ - struct eth_device* dev; - - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - sprintf(dev->name, "Au1X00 ETHERNET"); - dev->iobase = 0; - dev->priv = 0; - dev->init = au1x00_init; - dev->halt = au1x00_halt; - dev->send = au1x00_send; - dev->recv = au1x00_recv; - - eth_register(dev); - -#if (CONFIG_COMMANDS & CFG_CMD_MII) - miiphy_register(dev->name, - au1x00_miiphy_read, au1x00_miiphy_write); -#endif - - return 1; -} - -#if (CONFIG_COMMANDS & CFG_CMD_MII) -int au1x00_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short * value) -{ - volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); - volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); - u32 mii_control; - unsigned int timedout = 20; - - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_read busy timeout!!\n"); - return -1; - } - } - - mii_control = MAC_SET_MII_SELECT_REG(reg) | - MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ; - - *mii_control_reg = mii_control; - - timedout = 20; - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_read busy timeout!!\n"); - return -1; - } - } - *value = *mii_data_reg; - return 0; -} - -int au1x00_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); - volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); - u32 mii_control; - unsigned int timedout = 20; - - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_write busy timeout!!\n"); - return; - } - } - - mii_control = MAC_SET_MII_SELECT_REG(reg) | - MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE; - - *mii_data_reg = value; - *mii_control_reg = mii_control; - return 0; -} -#endif /* CONFIG_COMMANDS & CFG_CMD_MII */ - -#endif /* CONFIG_AU1X00 */ diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c deleted file mode 100644 index 42c668e..0000000 --- a/cpu/mips/au1x00_serial.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * AU1X00 UART support - * - * Hardcoded to UART 0 for now - * Speed and options also hardcoded to 115200 8N1 - * - * Copyright (c) 2003 Thomas.Lange@corelatus.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifdef CONFIG_AU1X00 - -#include -#include - -/****************************************************************************** -* -* serial_init - initialize a channel -* -* This routine initializes the number of data bits, parity -* and set the selected baud rate. Interrupts are disabled. -* Set the modem control signals if the option is selected. -* -* RETURNS: N/A -*/ - -int serial_init (void) -{ - volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR); - volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE); - - /* Enable clocks first */ - *uart_enable = UART_EN_CE; - - /* Then release reset */ - /* Must release reset before setting other regs */ - *uart_enable = UART_EN_CE|UART_EN_E; - - /* Activate fifos, reset tx and rx */ - /* Set tx trigger level to 12 */ - *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR| - UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12; - - serial_setbrg(); - - return 0; -} - - -void serial_setbrg (void) -{ - volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK); - volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR); - volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL; - int sd; - int divisorx2; - - /* sd is system clock divisor */ - /* see section 10.4.5 in au1550 datasheet */ - sd = (*sys_powerctrl & 0x03) + 2; - - /* calulate 2x baudrate and round */ - divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE))); - - if (divisorx2 & 0x01) - divisorx2 = divisorx2 + 1; - - *uart_clk = divisorx2 / 2; - - /* Set parity, stop bits and word length to 8N1 */ - *uart_lcr = UART_LCR_WLEN8; -} - -void serial_putc (const char c) -{ - volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR); - volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX); - - if (c == '\n') serial_putc ('\r'); - - /* Wait for fifo to shift out some bytes */ - while((*uart_lsr&UART_LSR_THRE)==0); - - *uart_tx = (u32)c; -} - -void serial_puts (const char *s) -{ - while (*s) - { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX); - char c; - - while (!serial_tstc()); - - c = (*uart_rx&0xFF); - return c; -} - -int serial_tstc (void) -{ - volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR); - - if(*uart_lsr&UART_LSR_DR){ - /* Data in rfifo */ - return(1); - } - return 0; -} -#endif /* CONFIG_SERIAL_AU1X00 */ diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c deleted file mode 100644 index dbf72dc..0000000 --- a/cpu/mips/au1x00_usb_ohci.c +++ /dev/null @@ -1,1727 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00. - * - * (C) Copyright 2003 - * Gary Jennejohn, DENX Software Engineering - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Note: Part of this code has been derived from linux - * - */ -/* - * IMPORTANT NOTES - * 1 - you MUST define LITTLEENDIAN in the configuration file for the - * board or this driver will NOT work! - * 2 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! - */ - -#include - -#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI) - -/* #include no PCI on the AU1x00 */ - -#include -#include -#include -#include -#include -#include "au1x00_usb_ohci.h" - -#define OHCI_USE_NPS /* force NoPowerSwitching mode */ -#define OHCI_VERBOSE_DEBUG /* not always helpful */ -#define OHCI_FILL_TRACE - -#define USBH_ENABLE_BE (1<<0) -#define USBH_ENABLE_C (1<<1) -#define USBH_ENABLE_E (1<<2) -#define USBH_ENABLE_CE (1<<3) -#define USBH_ENABLE_RD (1<<4) - -#ifdef LITTLEENDIAN -#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) -#else -#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE) -#endif - - -/* For initializing controller (mask in an HCFS mode too) */ -#define OHCI_CONTROL_INIT \ - (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE - -#undef readl -#undef writel - -#define readl(a) au_readl((long)(a)) -#define writel(v,a) au_writel((v),(int)(a)) - -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - -#define DEBUG -#ifdef DEBUG -#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) -#else -#define dbg(format, arg...) do {} while(0) -#endif /* DEBUG */ -#define err(format, arg...) printf("ERROR: " format "\n", ## arg) -#define SHOW_INFO -#ifdef SHOW_INFO -#define info(format, arg...) printf("INFO: " format "\n", ## arg) -#else -#define info(format, arg...) do {} while(0) -#endif - -#define m16_swap(x) swap_16(x) -#define m32_swap(x) swap_32(x) - -/* global ohci_t */ -static ohci_t gohci; -/* this must be aligned to a 256 byte boundary */ -struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* urb_priv */ -urb_priv_t urb_priv; -/* RHSC flag */ -int got_rhsc; -/* device which was disconnected */ -struct usb_device *devgone; - -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a (struct ohci *hc) - { return read_roothub (hc, a, 0xfc0fe000); } -static inline u32 roothub_b (struct ohci *hc) - { return readl (&hc->regs->roothub.b); } -static inline u32 roothub_status (struct ohci *hc) - { return readl (&hc->regs->roothub.status); } -static u32 roothub_portstatus (struct ohci *hc, int i) - { return read_roothub (hc, portstatus [i], 0xffe0fce0); } - - -/* forward declaration */ -static int hc_interrupt (void); -static void -td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); - -/*-------------------------------------------------------------------------* - * URB support functions - *-------------------------------------------------------------------------*/ - -/* free HCD-private data associated with this URB */ - -static void urb_free_priv (urb_priv_t * urb) -{ - int i; - int last; - struct td * td; - - last = urb->length - 1; - if (last >= 0) { - for (i = 0; i <= last; i++) { - td = urb->td[i]; - if (td) { - td->usb_dev = NULL; - urb->td[i] = NULL; - } - } - } -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -static int sohci_get_current_frame_number (struct usb_device * dev); - -/* debug| print the main components of an URB - * small: 0) header + data packets 1) just header */ - -static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, char * str, int small) -{ - urb_priv_t * purb = &urb_priv; - - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", - str, - sohci_get_current_frame_number (dev), - usb_pipedevice (pipe), - usb_pipeendpoint (pipe), - usb_pipeout (pipe)? 'O': 'I', - usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): - (usb_pipecontrol (pipe)? "CTRL": "BULK"), - purb->actual_length, - transfer_len, dev->status); -#ifdef OHCI_VERBOSE_DEBUG - if (!small) { - int i, len; - - if (usb_pipecontrol (pipe)) { - printf (__FILE__ ": cmd(8):"); - for (i = 0; i < 8 ; i++) - printf (" %02x", ((__u8 *) setup) [i]); - printf ("\n"); - } - if (transfer_len > 0 && buffer) { - printf (__FILE__ ": data(%d/%d):", - purb->actual_length, - transfer_len); - len = usb_pipeout (pipe)? - transfer_len: purb->actual_length; - for (i = 0; i < 16 && i < len; i++) - printf (" %02x", ((__u8 *) buffer) [i]); - printf ("%s\n", i < len? "...": ""); - } - } -#endif -} - -/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ -void ep_print_int_eds (ohci_t *ohci, char * str) { - int i, j; - __u32 * ed_p; - for (i= 0; i < 32; i++) { - j = 5; - ed_p = &(ohci->hcca->int_table [i]); - if (*ed_p == 0) - continue; - printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); - while (*ed_p != 0 && j--) { - ed_t *ed = (ed_t *)m32_swap(ed_p); - printf (" ed: %4x;", ed->hwINFO); - ed_p = &ed->hwNextED; - } - printf ("\n"); - } -} - -static void ohci_dump_intr_mask (char *label, __u32 mask) -{ - dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", - label, - mask, - (mask & OHCI_INTR_MIE) ? " MIE" : "", - (mask & OHCI_INTR_OC) ? " OC" : "", - (mask & OHCI_INTR_RHSC) ? " RHSC" : "", - (mask & OHCI_INTR_FNO) ? " FNO" : "", - (mask & OHCI_INTR_UE) ? " UE" : "", - (mask & OHCI_INTR_RD) ? " RD" : "", - (mask & OHCI_INTR_SF) ? " SF" : "", - (mask & OHCI_INTR_WDH) ? " WDH" : "", - (mask & OHCI_INTR_SO) ? " SO" : "" - ); -} - -static void maybe_print_eds (char *label, __u32 value) -{ - ed_t *edp = (ed_t *)value; - - if (value) { - dbg ("%s %08x", label, value); - dbg ("%08x", edp->hwINFO); - dbg ("%08x", edp->hwTailP); - dbg ("%08x", edp->hwHeadP); - dbg ("%08x", edp->hwNextED); - } -} - -static char * hcfs2string (int state) -{ - switch (state) { - case OHCI_USB_RESET: return "reset"; - case OHCI_USB_RESUME: return "resume"; - case OHCI_USB_OPER: return "operational"; - case OHCI_USB_SUSPEND: return "suspend"; - } - return "?"; -} - -/* dump control and status registers */ -static void ohci_dump_status (ohci_t *controller) -{ - struct ohci_regs *regs = controller->regs; - __u32 temp; - - temp = readl (®s->revision) & 0xff; - if (temp != 0x10) - dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); - - temp = readl (®s->control); - dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, - (temp & OHCI_CTRL_RWE) ? " RWE" : "", - (temp & OHCI_CTRL_RWC) ? " RWC" : "", - (temp & OHCI_CTRL_IR) ? " IR" : "", - hcfs2string (temp & OHCI_CTRL_HCFS), - (temp & OHCI_CTRL_BLE) ? " BLE" : "", - (temp & OHCI_CTRL_CLE) ? " CLE" : "", - (temp & OHCI_CTRL_IE) ? " IE" : "", - (temp & OHCI_CTRL_PLE) ? " PLE" : "", - temp & OHCI_CTRL_CBSR - ); - - temp = readl (®s->cmdstatus); - dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, - (temp & OHCI_SOC) >> 16, - (temp & OHCI_OCR) ? " OCR" : "", - (temp & OHCI_BLF) ? " BLF" : "", - (temp & OHCI_CLF) ? " CLF" : "", - (temp & OHCI_HCR) ? " HCR" : "" - ); - - ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); - ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); - - maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); - - maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); - maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); - - maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); - maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); - - maybe_print_eds ("donehead", readl (®s->donehead)); -} - -static void ohci_dump_roothub (ohci_t *controller, int verbose) -{ - __u32 temp, ndp, i; - - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - - if (verbose) { - dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, - ((temp & RH_A_POTPGT) >> 24) & 0xff, - (temp & RH_A_NOCP) ? " NOCP" : "", - (temp & RH_A_OCPM) ? " OCPM" : "", - (temp & RH_A_DT) ? " DT" : "", - (temp & RH_A_NPS) ? " NPS" : "", - (temp & RH_A_PSM) ? " PSM" : "", - ndp - ); - temp = roothub_b (controller); - dbg ("roothub.b: %08x PPCM=%04x DR=%04x", - temp, - (temp & RH_B_PPCM) >> 16, - (temp & RH_B_DR) - ); - temp = roothub_status (controller); - dbg ("roothub.status: %08x%s%s%s%s%s%s", - temp, - (temp & RH_HS_CRWE) ? " CRWE" : "", - (temp & RH_HS_OCIC) ? " OCIC" : "", - (temp & RH_HS_LPSC) ? " LPSC" : "", - (temp & RH_HS_DRWE) ? " DRWE" : "", - (temp & RH_HS_OCI) ? " OCI" : "", - (temp & RH_HS_LPS) ? " LPS" : "" - ); - } - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", - i, - temp, - (temp & RH_PS_PRSC) ? " PRSC" : "", - (temp & RH_PS_OCIC) ? " OCIC" : "", - (temp & RH_PS_PSSC) ? " PSSC" : "", - (temp & RH_PS_PESC) ? " PESC" : "", - (temp & RH_PS_CSC) ? " CSC" : "", - - (temp & RH_PS_LSDA) ? " LSDA" : "", - (temp & RH_PS_PPS) ? " PPS" : "", - (temp & RH_PS_PRS) ? " PRS" : "", - (temp & RH_PS_POCI) ? " POCI" : "", - (temp & RH_PS_PSS) ? " PSS" : "", - - (temp & RH_PS_PES) ? " PES" : "", - (temp & RH_PS_CCS) ? " CCS" : "" - ); - } -} - -static void ohci_dump (ohci_t *controller, int verbose) -{ - dbg ("OHCI controller usb-%s state", controller->slot_name); - - /* dumps some of the state we know about */ - ohci_dump_status (controller); - if (verbose) - ep_print_int_eds (controller, "hcca"); - dbg ("hcca frame #%04x", controller->hcca->frame_no); - ohci_dump_roothub (controller, 1); -} - - -#endif /* DEBUG */ - -/*-------------------------------------------------------------------------* - * Interface functions (URB) - *-------------------------------------------------------------------------*/ - -/* get a transfer request */ - -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - ohci_t *ohci; - ed_t * ed; - urb_priv_t *purb_priv; - int i, size = 0; - - ohci = &gohci; - - /* when controller's hung, permit only roothub cleanup attempts - * such as powering down ports */ - if (ohci->disabled) { - err("sohci_submit_job: EPIPE"); - return -1; - } - - /* every endpoint has a ed, locate and fill it */ - if (!(ed = ep_add_ed (dev, pipe))) { - err("sohci_submit_job: ENOMEM"); - return -1; - } - - /* for the private part of the URB we need the number of TDs (size) */ - switch (usb_pipetype (pipe)) { - case PIPE_BULK: /* one TD for every 4096 Byte */ - size = (transfer_len - 1) / 4096 + 1; - break; - case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ - size = (transfer_len == 0)? 2: - (transfer_len - 1) / 4096 + 3; - break; - } - - if (size >= (N_URB_TD - 1)) { - err("need %d TDs, only have %d", size, N_URB_TD); - return -1; - } - purb_priv = &urb_priv; - purb_priv->pipe = pipe; - - /* fill the private part of the URB */ - purb_priv->length = size; - purb_priv->ed = ed; - purb_priv->actual_length = 0; - - /* allocate the TDs */ - /* note that td[0] was allocated in ep_add_ed */ - for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc (dev); - if (!purb_priv->td[i]) { - purb_priv->length = i; - urb_free_priv (purb_priv); - err("sohci_submit_job: ENOMEM"); - return -1; - } - } - - if (ed->state == ED_NEW || (ed->state & ED_DEL)) { - urb_free_priv (purb_priv); - err("sohci_submit_job: EINVAL"); - return -1; - } - - /* link the ed into a chain if is not already */ - if (ed->state != ED_OPER) - ep_link (ohci, ed); - - /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -/* tell us the current USB frame number */ - -static int sohci_get_current_frame_number (struct usb_device *usb_dev) -{ - ohci_t *ohci = &gohci; - - return m16_swap (ohci->hcca->frame_no); -} -#endif - -/*-------------------------------------------------------------------------* - * ED handling functions - *-------------------------------------------------------------------------*/ - -/* link an ed into one of the HC chains */ - -static int ep_link (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->state = ED_OPER; - - switch (ed->type) { - case PIPE_CONTROL: - ed->hwNextED = 0; - if (ohci->ed_controltail == NULL) { - writel ((long)ed, &ohci->regs->ed_controlhead); - } else { - ohci->ed_controltail->hwNextED = m32_swap (ed); - } - ed->ed_prev = ohci->ed_controltail; - if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_controltail = edi; - break; - - case PIPE_BULK: - ed->hwNextED = 0; - if (ohci->ed_bulktail == NULL) { - writel ((long)ed, &ohci->regs->ed_bulkhead); - } else { - ohci->ed_bulktail->hwNextED = m32_swap (ed); - } - ed->ed_prev = ohci->ed_bulktail; - if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_bulktail = edi; - break; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* unlink an ed from one of the HC chains. - * just the link to the ed is unlinked. - * the link from the ed still points to another operational ed or 0 - * so the HC can eventually finish the processing of the unlinked ed */ - -static int ep_unlink (ohci_t *ohci, ed_t *ed) -{ - ed->hwINFO |= m32_swap (OHCI_ED_SKIP); - - switch (ed->type) { - case PIPE_CONTROL: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_controltail == ed) { - ohci->ed_controltail = ed->ed_prev; - } else { - ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - - case PIPE_BULK: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_bulktail == ed) { - ohci->ed_bulktail = ed->ed_prev; - } else { - ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - } - ed->state = ED_UNLINK; - return 0; -} - - -/*-------------------------------------------------------------------------*/ - -/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, - * but the USB stack is a little bit stateless so we do it at every transaction - * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK - * in all other cases the state is left unchanged - * the ed info fields are setted anyway even though most of them should not change */ - -static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) -{ - td_t *td; - ed_t *ed_ret; - volatile ed_t *ed; - - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | - (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; - - if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { - err("ep_add_ed: pending delete"); - /* pending delete request */ - return NULL; - } - - if (ed->state == ED_NEW) { - ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ - /* dummy td; end of td list for ed */ - td = td_alloc (usb_dev); - ed->hwTailP = m32_swap (td); - ed->hwHeadP = ed->hwTailP; - ed->state = ED_UNLINK; - ed->type = usb_pipetype (pipe); - ohci_dev.ed_cnt++; - } - - ed->hwINFO = m32_swap (usb_pipedevice (pipe) - | usb_pipeendpoint (pipe) << 7 - | (usb_pipeisoc (pipe)? 0x8000: 0) - | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | usb_pipeslow (pipe) << 13 - | usb_maxpacket (usb_dev, pipe) << 16); - - return ed_ret; -} - -/*-------------------------------------------------------------------------* - * TD handling functions - *-------------------------------------------------------------------------*/ - -/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ - -static void td_fill (ohci_t *ohci, unsigned int info, - void *data, int len, - struct usb_device *dev, int index, urb_priv_t *urb_priv) -{ - volatile td_t *td, *td_pt; -#ifdef OHCI_FILL_TRACE - int i; -#endif - - if (index > urb_priv->length) { - err("index > length"); - return; - } - /* use this td as the next dummy */ - td_pt = urb_priv->td [index]; - td_pt->hwNextTD = 0; - - /* fill the old dummy TD */ - td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); - - td->ed = urb_priv->ed; - td->next_dl_td = NULL; - td->index = index; - td->data = (__u32)data; -#ifdef OHCI_FILL_TRACE - if (1 || ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe))) { - for (i = 0; i < len; i++) - printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]); - } -#endif - if (!len) - data = 0; - - td->hwINFO = m32_swap (info); - td->hwCBP = m32_swap (data); - if (data) - td->hwBE = m32_swap (data + len - 1); - else - td->hwBE = 0; - td->hwNextTD = m32_swap (td_pt); - td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000); - - /* append to queue */ - td->ed->hwTailP = td->hwNextTD; -} - -/*-------------------------------------------------------------------------*/ - -/* prepare all TDs of a transfer */ - -#define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000)) - -static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) -{ - ohci_t *ohci = &gohci; - int data_len = transfer_len; - void *data; - int cnt = 0; - __u32 info = 0; - unsigned int toggle = 0; - - /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ - if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { - toggle = TD_T_TOGGLE; - } else { - toggle = TD_T_DATA0; - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); - } - urb->td_cnt = 0; - if (data_len) - data = kseg_to_phys(buffer); - else - data = 0; - - switch (usb_pipetype (pipe)) { - case PIPE_BULK: - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; - while(data_len > 4096) { - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); - data += 4096; data_len -= 4096; cnt++; - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); - cnt++; - - if (!ohci->sleeping) - writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ - break; - - case PIPE_CONTROL: - info = TD_CC | TD_DP_SETUP | TD_T_DATA0; - td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb); - if (data_len > 0) { - info = usb_pipeout (pipe)? - TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; - /* NOTE: mishandles transfers >8K, some >4K */ - td_fill (ohci, info, data, data_len, dev, cnt++, urb); - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; - td_fill (ohci, info, data, 0, dev, cnt++, urb); - if (!ohci->sleeping) - writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ - break; - } - if (urb->length != cnt) - dbg("TD LENGTH %d != CNT %d", urb->length, cnt); -} - -/*-------------------------------------------------------------------------* - * Done List handling functions - *-------------------------------------------------------------------------*/ - - -/* calculate the transfer length and update the urb */ - -static void dl_transfer_length(td_t * td) -{ - __u32 tdINFO, tdBE, tdCBP; - urb_priv_t *lurb_priv = &urb_priv; - - tdINFO = m32_swap (td->hwINFO); - tdBE = m32_swap (td->hwBE); - tdCBP = m32_swap (td->hwCBP); - - - if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && - ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { - if (tdBE != 0) { - if (td->hwCBP == 0) - lurb_priv->actual_length += tdBE - td->data + 1; - else - lurb_priv->actual_length += tdCBP - td->data; - } - } -} - -/*-------------------------------------------------------------------------*/ - -/* replies to the request have to be on a FIFO basis so - * we reverse the reversed done-list */ - -static td_t * dl_reverse_done_list (ohci_t *ohci) -{ - __u32 td_list_hc; - td_t *td_rev = NULL; - td_t *td_list = NULL; - urb_priv_t *lurb_priv = NULL; - - td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; - ohci->hcca->done_head = 0; - - while (td_list_hc) { - td_list = (td_t *)td_list_hc; - - if (TD_CC_GET (m32_swap (td_list->hwINFO))) { - lurb_priv = &urb_priv; - dbg(" USB-error/status: %x : %p", - TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); - if (td_list->ed->hwHeadP & m32_swap (0x1)) { - if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { - td_list->ed->hwHeadP = - (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | - (td_list->ed->hwHeadP & m32_swap (0x2)); - lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; - } else - td_list->ed->hwHeadP &= m32_swap (0xfffffff2); - } - } - - td_list->next_dl_td = td_rev; - td_rev = td_list; - td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; - } - return td_list; -} - -/*-------------------------------------------------------------------------*/ - -/* td done list */ -static int dl_done_list (ohci_t *ohci, td_t *td_list) -{ - td_t *td_list_next = NULL; - ed_t *ed; - int cc = 0; - int stat = 0; - /* urb_t *urb; */ - urb_priv_t *lurb_priv; - __u32 tdINFO, edHeadP, edTailP; - - while (td_list) { - td_list_next = td_list->next_dl_td; - - lurb_priv = &urb_priv; - tdINFO = m32_swap (td_list->hwINFO); - - ed = td_list->ed; - - dl_transfer_length(td_list); - - /* error code of transfer */ - cc = TD_CC_GET (tdINFO); - if (cc != 0) { - dbg("ConditionCode %#x", cc); - stat = cc_to_error[cc]; - } - - if (ed->state != ED_NEW) { - edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; - edTailP = m32_swap (ed->hwTailP); - - /* unlink eds if they are not busy */ - if ((edHeadP == edTailP) && (ed->state == ED_OPER)) - ep_unlink (ohci, ed); - } - - td_list = td_list_next; - } - return stat; -} - -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ - -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - -/* Hub class-specific descriptor is constructed dynamically */ - - -/*-------------------------------------------------------------------------*/ - -#define OK(x) len = (x); break -#ifdef DEBUG -#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} -#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} -#else -#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) -#endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) - -/* request to virtual root hub */ - -int rh_check_port_status(ohci_t *controller) -{ - __u32 temp, ndp, i; - int res; - - res = -1; - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - /* check for a device disconnect */ - if (((temp & (RH_PS_PESC | RH_PS_CSC)) == - (RH_PS_PESC | RH_PS_CSC)) && - ((temp & RH_PS_CCS) == 0)) { - res = i; - break; - } - } - return res; -} - -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *cmd) -{ - void * data = buffer; - int leni = transfer_len; - int len = 0; - int stat = 0; - __u32 datab[4]; - __u8 *data_buf = (__u8 *)datab; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; - -#ifdef DEBUG -urb_priv.actual_length = 0; -pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { - info("Root-Hub submit IRQ: NOT implemented"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = m16_swap (cmd->value); - wIndex = m16_swap (cmd->index); - wLength = m16_swap (cmd->length); - - info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", - dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(__u16 *) data_buf = m16_swap (1); OK (2); - case RH_GET_STATUS | RH_INTERFACE: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_ENDPOINT: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_CLASS: - *(__u32 *) data_buf = m32_swap ( - RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); - OK (4); - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); - - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case RH_C_HUB_LOCAL_POWER: - OK(0); - case (RH_C_HUB_OVER_CURRENT): - WR_RH_STAT(RH_HS_OCIC); OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_POCI); OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); - case (RH_C_PORT_CONNECTION): - WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); - case (RH_C_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_PESC); OK (0); - case (RH_C_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); - case (RH_C_PORT_OVER_CURRENT): - WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); - case (RH_C_PORT_RESET): - WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); - } - break; - - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); - case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PRS); - OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); - case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PES ); - OK (0); - } - break; - - case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_dev_des), - wLength)); - data_buf = root_hub_dev_des; OK(len); - case (0x02): /* configuration descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_config_des), - wLength)); - data_buf = root_hub_config_des; OK(len); - case (0x03): /* string descriptors */ - if(wValue==0x0300) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index0), - wLength)); - data_buf = root_hub_str_index0; - OK(len); - } - if(wValue==0x0301) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index1), - wLength)); - data_buf = root_hub_str_index1; - OK(len); - } - default: - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - { - __u32 temp = roothub_a (&gohci); - - data_buf [0] = 9; /* min length; */ - data_buf [1] = 0x29; - data_buf [2] = temp & RH_A_NDP; - data_buf [3] = 0; - if (temp & RH_A_PSM) /* per-port power switching? */ - data_buf [3] |= 0x1; - if (temp & RH_A_NOCP) /* no overcurrent reporting? */ - data_buf [3] |= 0x10; - else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ - data_buf [3] |= 0x8; - - /* corresponds to data_buf[4-7] */ - datab [1] = 0; - data_buf [5] = (temp & RH_A_POTPGT) >> 24; - temp = roothub_b (&gohci); - data_buf [7] = temp & RH_B_DR; - if (data_buf [2] < 7) { - data_buf [8] = 0xff; - } else { - data_buf [0] += 2; - data_buf [8] = (temp & RH_B_DR) >> 8; - data_buf [10] = data_buf [9] = 0xff; - } - - len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf [0], wLength)); - OK (len); - } - - case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); - - case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); - - default: - dbg ("unsupported root hub command"); - stat = USB_ST_STALLED; - } - -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#else - wait_ms(1); -#endif - - len = min_t(int, len, leni); - if (data != data_buf) - memcpy (data, data_buf, len); - dev->act_len = len; - dev->status = stat; - -#ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); -#else - wait_ms(1); -#endif - - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/* common code for handling submit messages - used for all but root hub */ -/* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; - - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } - -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if (!maxsize) { - err("submit_common_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { - err("sohci_submit_job failed"); - return -1; - } - - wait_ms(10); - /* ohci_dump_status(&gohci); */ - - /* allow more time for a BULK device to react - some are slow */ -#define BULK_TO 5000 /* timeout in milliseconds */ - if (usb_pipetype (pipe) == PIPE_BULK) - timeout = BULK_TO; - else - timeout = 100; - - timeout *= 4; - /* wait for it to complete */ - for (;;) { - /* check whether the controller is done */ - stat = hc_interrupt(); - if (stat < 0) { - stat = USB_ST_CRC_ERR; - break; - } - if (stat >= 0 && stat != 0xff) { - /* 0xff is returned for an SF-interrupt */ - break; - } - if (--timeout) { - udelay(250); /* wait_ms(1); */ - } else { - err("CTL:TIMEOUT "); - stat = USB_ST_CRC_ERR; - break; - } - } - /* we got an Root Hub Status Change interrupt */ - if (got_rhsc) { -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - got_rhsc = 0; - /* abuse timeout */ - timeout = rh_check_port_status(&gohci); - if (timeout >= 0) { -#if 0 /* this does nothing useful, but leave it here in case that changes */ - /* the called routine adds 1 to the passed value */ - usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); -#endif - /* - * XXX - * This is potentially dangerous because it assumes - * that only one device is ever plugged in! - */ - devgone = dev; - } - } - - dev->status = stat; - dev->act_len = transfer_len; - -#ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - - /* free TDs in urb_priv */ - urb_free_priv (&urb_priv); - return 0; -} - -/* submit routines called from usb.c */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) -{ - info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) -{ - int maxsize = usb_maxpacket(dev, pipe); - - info("submit_control_msg"); -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#else - wait_ms(1); -#endif - if (!maxsize) { - err("submit_control_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; - /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); - } - - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return -1; -} - -/*-------------------------------------------------------------------------* - * HC functions - *-------------------------------------------------------------------------*/ - -/* reset the HC and BUS */ - -static int hc_reset (ohci_t *ohci) -{ - int timeout = 30; - int smm_timeout = 50; /* 0,5 sec */ - - if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ - writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ - info("USB HC TakeOver from SMM"); - while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms (10); - if (--smm_timeout == 0) { - err("USB HC TakeOver failed!"); - return -1; - } - } - } - - /* Disable HC interrupts */ - writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); - - dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", - ohci->slot_name, - readl (&ohci->regs->control)); - - /* Reset USB (needed by some controllers) */ - writel (0, &ohci->regs->control); - - /* HC Reset requires max 10 us delay */ - writel (OHCI_HCR, &ohci->regs->cmdstatus); - while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { - if (--timeout == 0) { - err("USB HC reset timed out!"); - return -1; - } - udelay (1); - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* Start an OHCI controller, set the BUS operational - * enable interrupts - * connect the virtual root hub */ - -static int hc_start (ohci_t * ohci) -{ - __u32 mask; - unsigned int fminterval; - - ohci->disabled = 1; - - /* Tell the controller where the control and bulk lists are - * The lists are empty now. */ - - writel (0, &ohci->regs->ed_controlhead); - writel (0, &ohci->regs->ed_bulkhead); - - writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ - - fminterval = 0x2edf; - writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); - fminterval |= ((((fminterval - 210) * 6) / 7) << 16); - writel (fminterval, &ohci->regs->fminterval); - writel (0x628, &ohci->regs->lsthresh); - - /* start controller operations */ - ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; - ohci->disabled = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* disable all interrupts */ - mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | - OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | - OHCI_INTR_OC | OHCI_INTR_MIE); - writel (mask, &ohci->regs->intrdisable); - /* clear all interrupts */ - mask &= ~OHCI_INTR_MIE; - writel (mask, &ohci->regs->intrstatus); - /* Choose the interrupts we care about now - but w/o MIE */ - mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; - writel (mask, &ohci->regs->intrenable); - -#ifdef OHCI_USE_NPS - /* required for AMD-756 and some Mac platforms */ - writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, - &ohci->regs->roothub.a); - writel (RH_HS_LPSC, &ohci->regs->roothub.status); -#endif /* OHCI_USE_NPS */ - -#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay ((roothub_a (ohci) >> 23) & 0x1fe); - - /* connect the virtual root hub */ - ohci->rh.devnum = 0; - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* an interrupt happens */ - -static int -hc_interrupt (void) -{ - ohci_t *ohci = &gohci; - struct ohci_regs *regs = ohci->regs; - int ints; - int stat = -1; - - if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) { - ints = OHCI_INTR_WDH; - } else { - ints = readl (®s->intrstatus); - } - - /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ - - if (ints & OHCI_INTR_RHSC) { - got_rhsc = 1; - } - - if (ints & OHCI_INTR_UE) { - ohci->disabled++; - err ("OHCI Unrecoverable Error, controller usb-%s disabled", - ohci->slot_name); - /* e.g. due to PCI Master/Target Abort */ - -#ifdef DEBUG - ohci_dump (ohci, 1); -#else - wait_ms(1); -#endif - /* FIXME: be optimistic, hope that bug won't repeat often. */ - /* Make some non-interrupt context restart the controller. */ - /* Count and limit the retries though; either hardware or */ - /* software errors can go forever... */ - hc_reset (ohci); - return -1; - } - - if (ints & OHCI_INTR_WDH) { - wait_ms(1); - writel (OHCI_INTR_WDH, ®s->intrdisable); - stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); - writel (OHCI_INTR_WDH, ®s->intrenable); - } - - if (ints & OHCI_INTR_SO) { - dbg("USB Schedule overrun\n"); - writel (OHCI_INTR_SO, ®s->intrenable); - stat = -1; - } - - /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ - if (ints & OHCI_INTR_SF) { - unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; - wait_ms(1); - writel (OHCI_INTR_SF, ®s->intrdisable); - if (ohci->ed_rm_list[frame] != NULL) - writel (OHCI_INTR_SF, ®s->intrenable); - stat = 0xff; - } - - writel (ints, ®s->intrstatus); - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -/* De-allocate all resources.. */ - -static void hc_release_ohci (ohci_t *ohci) -{ - dbg ("USB HC release ohci usb-%s", ohci->slot_name); - - if (!ohci->disabled) - hc_reset (ohci); -} - -/*-------------------------------------------------------------------------*/ - -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define read_c0_prid() __read_32bit_c0_register($15, 0) - -/* - * low level initalisation routine, called from usb.c - */ -static char ohci_inited = 0; - -int usb_lowlevel_init(void) -{ - u32 pin_func; - u32 sys_freqctrl, sys_clksrc; - u32 prid = read_c0_prid(); - - dbg("in usb_lowlevel_init\n"); - - /* zero and disable FREQ2 */ - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* zero and disable USBH/USBD clocks */ - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~0x00007FE0; - au_writel(sys_clksrc, SYS_CLKSRC); - - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~0x00007FE0; - - switch (prid & 0x000000FF) { - case 0x00: /* DA */ - case 0x01: /* HA */ - case 0x02: /* HB */ - /* CPU core freq to 48MHz to slow it way down... */ - au_writel(4, SYS_CPUPLL); - - /* - * Setup 48MHz FREQ2 from CPUPLL for USB Host - */ - /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */ - sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20)); - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* CPU core freq to 384MHz */ - au_writel(0x20, SYS_CPUPLL); - - printf("Au1000: 48MHz OHCI workaround enabled\n"); - break; - - default: /* HC and newer */ - /* FREQ2 = aux/2 = 48 MHz */ - sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); - au_writel(sys_freqctrl, SYS_FREQCTRL0); - break; - } - - /* - * Route 48MHz FREQ2 into USB Host and/or Device - */ - sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); - au_writel(sys_clksrc, SYS_CLKSRC); - - /* configure pins GPIO[14:9] as GPIO */ - pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080); - - au_writel(pin_func, SYS_PINFUNC); - au_writel(0x2800, SYS_TRIOUTCLR); - au_writel(0x0030, SYS_OUTPUTCLR); - - dbg("OHCI board setup complete\n"); - - /* enable host controller */ - au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG); - udelay(1000); - au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG); - udelay(1000); - - /* wait for reset complete (read register twice; see au1500 errata) */ - while (au_readl(USB_HOST_CONFIG), - !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) - udelay(1000); - - dbg("OHCI clock running\n"); - - memset (&gohci, 0, sizeof (ohci_t)); - memset (&urb_priv, 0, sizeof (urb_priv_t)); - - /* align the storage */ - if ((__u32)&ghcca[0] & 0xff) { - err("HCCA not aligned!!"); - return -1; - } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32)&ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); - if ((__u32)gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset (phcca, 0, sizeof (struct ohci_hcca)); - - gohci.disabled = 1; - gohci.sleeping = 0; - gohci.irq = -1; - gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000); - - gohci.flags = 0; - gohci.slot_name = "au1x00"; - - dbg("OHCI revision: 0x%08x\n" - " RH: a: 0x%08x b: 0x%08x\n", - readl(&gohci.regs->revision), - readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b)); - - if (hc_reset (&gohci) < 0) - goto errout; - - /* FIXME this is a second HC reset; why?? */ - writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); - wait_ms (10); - - if (hc_start (&gohci) < 0) - goto errout; - -#ifdef DEBUG - ohci_dump (&gohci, 1); -#else - wait_ms(1); -#endif - ohci_inited = 1; - return 0; - - errout: - err("OHCI initialization error\n"); - hc_release_ohci (&gohci); - /* Initialization failed */ - au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); - return -1; -} - -int usb_lowlevel_stop(void) -{ - /* this gets called really early - before the controller has */ - /* even been initialized! */ - if (!ohci_inited) - return 0; - /* TODO release any interrupts, etc. */ - /* call hc_release_ohci() here ? */ - hc_reset (&gohci); - /* may not want to do this */ - /* Disable clock */ - au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); - return 0; -} - -#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/mips/au1x00_usb_ohci.h b/cpu/mips/au1x00_usb_ohci.h deleted file mode 100644 index 4ef06ff..0000000 --- a/cpu/mips/au1x00_usb_ohci.h +++ /dev/null @@ -1,416 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB. - * - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2001 David Brownell - * - * usb-ohci.h - */ - - -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -/* ED States */ - -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 -#define ED_OPER 0x02 -#define ED_DEL 0x04 -#define ED_URB_DEL 0x08 - -/* usb_ohci_ed */ -struct ed { - __u32 hwINFO; - __u32 hwTailP; - __u32 hwHeadP; - __u32 hwNextED; - - struct ed *ed_prev; - __u8 int_period; - __u8 int_branch; - __u8 int_load; - __u8 int_interval; - __u8 state; - __u8 type; - __u16 last_iso; - struct ed *ed_rm_list; - - struct usb_device *usb_dev; - __u32 unused[3]; -} __attribute((aligned(16))); -typedef struct ed ed_t; - - -/* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 - -/* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F - - -#define MAXPSW 1 - -struct td { - __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u16 hwPSW[MAXPSW]; - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; - struct usb_device *usb_dev; - int transfer_len; - __u32 data; - - __u32 unused2[2]; -} __attribute((aligned(32))); -typedef struct td td_t; - -#define OHCI_ED_SKIP (1 << 14) - -/* - * The HCCA (Host Controller Communications Area) is a 256 byte - * structure defined in the OHCI spec. that the host controller is - * told the base address of. It must be 256-byte aligned. - */ - -#define NUM_INTS 32 /* part of the OHCI standard */ -struct ohci_hcca { - __u32 int_table[NUM_INTS]; /* Interrupt ED table */ - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ - __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; -} __attribute((aligned(256))); - - -/* - * Maximum number of root hub ports. - */ -#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ - -/* - * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and - * writel() macros defined in asm/io.h to access these!! - */ -struct ohci_regs { - /* control and status registers */ - __u32 revision; - __u32 control; - __u32 cmdstatus; - __u32 intrstatus; - __u32 intrenable; - __u32 intrdisable; - /* memory pointers */ - __u32 hcca; - __u32 ed_periodcurrent; - __u32 ed_controlhead; - __u32 ed_controlcurrent; - __u32 ed_bulkhead; - __u32 ed_bulkcurrent; - __u32 donehead; - /* frame counters */ - __u32 fminterval; - __u32 fmremaining; - __u32 fmnumber; - __u32 periodicstart; - __u32 lsthresh; - /* Root hub ports */ - struct ohci_roothub_regs { - __u32 a; - __u32 b; - __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; - } roothub; -} __attribute((aligned(32))); - - -/* OHCI CONTROL AND STATUS REGISTER MASKS */ - -/* - * HcControl (control) register masks - */ -#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ -#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ - -/* pre-shifted values for HCFS */ -# define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) -# define OHCI_USB_OPER (2 << 6) -# define OHCI_USB_SUSPEND (3 << 6) - -/* - * HcCommandStatus (cmdstatus) register masks - */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ - -/* - * masks used with interrupt registers: - * HcInterruptStatus (intrstatus) - * HcInterruptEnable (intrenable) - * HcInterruptDisable (intrdisable) - */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ - - -/* Virtual Root HUB */ -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - void *dev; /* was urb */ - void *int_addr; - int send; - int interval; -}; - -/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ - -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* OHCI ROOT HUB REGISTER MASKS */ - -/* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ - -/* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ - -/* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ - -/* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ - -/* urb */ -#define N_URB_TD 48 -typedef struct -{ - ed_t *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ - int state; - unsigned long pipe; - int actual_length; - td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ -} urb_priv_t; -#define URB_DEL 1 - -/* - * This is the full ohci controller description - * - * Note how the "proper" USB information is just - * a subset of what the full implementation needs. (Linus) - */ - - -typedef struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma;*/ - - int irq; - int disabled; /* e.g. got a UE, we're hung */ - int sleeping; - unsigned long flags; /* for HC bugs */ - - struct ohci_regs *regs; /* OHCI controller's memory */ - - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ - int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ - struct usb_device *dev[32]; - struct virt_root_hub rh; - - const char *slot_name; -} ohci_t; - -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - ed_t ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(ohci_t * ohci, ed_t * ed); -static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -td_t gtd[NUM_TD+1]; -/* pointers to aligned storage */ -td_t *ptd; - -/* TDs ... */ -static inline struct td * -td_alloc (struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) { - if (ptd[i].usb_dev == NULL) { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - return td; -} - -static inline void -ed_free (struct ed *ed) -{ - ed->usb_dev = NULL; -} diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S deleted file mode 100644 index aad76e0..0000000 --- a/cpu/mips/cache.S +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Cache-handling routined for MIPS 4K CPUs - * - * Copyright (c) 2003 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include - - - /* 16KB is the maximum size of instruction and data caches on - * MIPS 4K. - */ -#define MIPS_MAX_CACHE_SIZE 0x4000 - - -/* - * cacheop macro to automate cache operations - * first some helpers... - */ -#define _mincache(size, maxsize) \ - bltu size,maxsize,9f ; \ - move size,maxsize ; \ -9: - -#define _align(minaddr, maxaddr, linesize) \ - .set noat ; \ - subu AT,linesize,1 ; \ - not AT ; \ - and minaddr,AT ; \ - addu maxaddr,-1 ; \ - and maxaddr,AT ; \ - .set at - -/* general operations */ -#define doop1(op1) \ - cache op1,0(a0) -#define doop2(op1, op2) \ - cache op1,0(a0) ; \ - nop ; \ - cache op2,0(a0) - -/* specials for cache initialisation */ -#define doop1lw(op1) \ - lw zero,0(a0) -#define doop1lw1(op1) \ - cache op1,0(a0) ; \ - lw zero,0(a0) ; \ - cache op1,0(a0) -#define doop121(op1,op2) \ - cache op1,0(a0) ; \ - nop; \ - cache op2,0(a0) ; \ - nop; \ - cache op1,0(a0) - -#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \ - .set noreorder ; \ -10: doop##tag##ops ; \ - bne minaddr,maxaddr,10b ; \ - add minaddr,linesize ; \ - .set reorder - -/* finally the cache operation macros */ -#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ - blez n,11f ; \ - addu n,kva ; \ - _align(kva, n, cacheLineSize) ; \ - _oploopn(kva, n, cacheLineSize, tag, ops) ; \ -11: - -#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ - _mincache(n, cacheSize); \ - blez n,11f ; \ - addu n,kva ; \ - _align(kva, n, cacheLineSize) ; \ - _oploopn(kva, n, cacheLineSize, tag, ops) ; \ -11: - -#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ - vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) - -#define icacheop(kva, n, cacheSize, cacheLineSize, op) \ - icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) - -/******************************************************************************* -* -* mips_cache_reset - low level initialisation of the primary caches -* -* This routine initialises the primary caches to ensure that they -* have good parity. It must be called by the ROM before any cached locations -* are used to prevent the possibility of data with bad parity being written to -* memory. -* To initialise the instruction cache it is essential that a source of data -* with good parity is available. This routine -* will initialise an area of memory starting at location zero to be used as -* a source of parity. -* -* RETURNS: N/A -* -*/ - .globl mips_cache_reset - .ent mips_cache_reset -mips_cache_reset: - - li t2, CFG_ICACHE_SIZE - li t3, CFG_DCACHE_SIZE - li t4, CFG_CACHELINE_SIZE - move t5, t4 - - - li v0, MIPS_MAX_CACHE_SIZE - - /* Now clear that much memory starting from zero. - */ - - li a0, KSEG1 - addu a1, a0, v0 - -2: sw zero, 0(a0) - sw zero, 4(a0) - sw zero, 8(a0) - sw zero, 12(a0) - sw zero, 16(a0) - sw zero, 20(a0) - sw zero, 24(a0) - sw zero, 28(a0) - addu a0, 32 - bltu a0, a1, 2b - - /* Set invalid tag. - */ - - mtc0 zero, CP0_TAGLO - - /* - * The caches are probably in an indeterminate state, - * so we force good parity into them by doing an - * invalidate, load/fill, invalidate for each line. - */ - - /* Assume bottom of RAM will generate good parity for the cache. - */ - - li a0, K0BASE - move a2, t2 # icacheSize - move a3, t4 # icacheLineSize - move a1, a2 - icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) - - /* To support Orion/R4600, we initialise the data cache in 3 passes. - */ - - /* 1: initialise dcache tags. - */ - - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheop(a0,a1,a2,a3,Index_Store_Tag_D) - - /* 2: fill dcache. - */ - - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheopn(a0,a1,a2,a3,1lw,(dummy)) - - /* 3: clear dcache tags. - */ - - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheop(a0,a1,a2,a3,Index_Store_Tag_D) - - j ra - .end mips_cache_reset - - -/******************************************************************************* -* -* dcache_status - get cache status -* -* RETURNS: 0 - cache disabled; 1 - cache enabled -* -*/ - .globl dcache_status - .ent dcache_status -dcache_status: - - mfc0 v0, CP0_CONFIG - andi v0, v0, 1 - j ra - - .end dcache_status - -/******************************************************************************* -* -* dcache_disable - disable cache -* -* RETURNS: N/A -* -*/ - .globl dcache_disable - .ent dcache_disable -dcache_disable: - - mfc0 t0, CP0_CONFIG - li t1, -8 - and t0, t0, t1 - ori t0, t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG - j ra - - .end dcache_disable - - -/******************************************************************************* -* -* mips_cache_lock - lock RAM area pointed to by a0 in cache. -* -* RETURNS: N/A -* -*/ -#if defined(CONFIG_PURPLE) -# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2) -#else -# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE) -#endif - .globl mips_cache_lock - .ent mips_cache_lock -mips_cache_lock: - li a1, K0BASE - CACHE_LOCK_SIZE - addu a0, a1 - li a2, CACHE_LOCK_SIZE - li a3, CFG_CACHELINE_SIZE - move a1, a2 - icacheop(a0,a1,a2,a3,0x1d) - - j ra - .end mips_cache_lock diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk deleted file mode 100644 index c357615..0000000 --- a/cpu/mips/config.mk +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -v=$(shell \ -mips-linux-as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}') -MIPSFLAGS=$(shell \ -if [ "$v" -lt "14" ]; then \ - echo "-mcpu=4kc"; \ -else \ - echo "-march=4kc -mtune=4kc"; \ -fi) - -ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) -ENDIANNESS = -EL -else -ENDIANNESS = -EB -endif - -MIPSFLAGS += $(ENDIANNESS) -mabicalls - -PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c deleted file mode 100644 index f48675e..0000000 --- a/cpu/mips/cpu.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ -#if defined(CONFIG_INCA_IP) - *INCA_IP_WDT_RST_REQ = 0x3f; -#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229) - void (*f)(void) = (void *) 0xbfc00000; - - f(); -#endif - fprintf(stderr, "*** reset failed ***\n"); - return 0; -} - -void flush_cache (ulong start_addr, ulong size) -{ - -} - -void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){ - write_32bit_cp0_register(CP0_ENTRYLO0, low0); - write_32bit_cp0_register(CP0_PAGEMASK, pagemask); - write_32bit_cp0_register(CP0_ENTRYLO1, low1); - write_32bit_cp0_register(CP0_ENTRYHI, hi); - write_32bit_cp0_register(CP0_INDEX, index); - tlb_write_indexed(); -} diff --git a/cpu/mips/incaip_clock.c b/cpu/mips/incaip_clock.c deleted file mode 100644 index d0515ca..0000000 --- a/cpu/mips/incaip_clock.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -/******************************************************************************* -* -* get_cpuclk - returns the frequency of the CPU. -* -* Gets the value directly from the INCA-IP hardware. -* -* RETURNS: -* 150.000.000 for 150 MHz -* 133.333.333 for 133 Mhz (= 400MHz/3) -* 100.000.000 for 100 Mhz (= 400MHz/4) -* NOTE: -* This functions should be used by the hardware driver to get the correct -* frequency of the CPU. Don't use the macros, which are set to init the CPU -* frequency in the ROM code. -*/ -uint incaip_get_cpuclk (void) -{ - /*-------------------------------------------------------------------------*/ - /* CPU Clock Input Multiplexer (MUX I) */ - /* Multiplexer MUX I selects the maximum input clock to the CPU. */ - /*-------------------------------------------------------------------------*/ - if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) & - INCA_IP_CGU_CGU_MUXCR_MUXI) { - /* MUX I set to 150 MHz clock */ - return 150000000; - } else { - /* MUX I set to 100/133 MHz clock */ - if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) { - /* Division value is 1/3, maximum CPU operating */ - /* frequency is 133.3 MHz */ - return 133333333; - } else { - /* Division value is 1/4, maximum CPU operating */ - /* frequency is 100 MHz */ - return 100000000; - } - } -} - -/******************************************************************************* -* -* get_fpiclk - returns the frequency of the FPI bus. -* -* Gets the value directly from the INCA-IP hardware. -* -* RETURNS: Frquency in Hz -* -* NOTE: -* This functions should be used by the hardware driver to get the correct -* frequency of the CPU. Don't use the macros, which are set to init the CPU -* frequency in the ROM code. -* The calculation for the -*/ -uint incaip_get_fpiclk (void) -{ - uint clkCPU; - - clkCPU = incaip_get_cpuclk (); - - switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) { - case 0x4: - return clkCPU >> 1; /* devided by 2 */ - break; - case 0x8: - return clkCPU >> 2; /* devided by 4 */ - break; - default: - return clkCPU; - break; - } -} - -int incaip_set_cpuclk (void) -{ - extern void ebu_init(long); - extern void cgu_init(long); - extern void sdram_init(long); - char tmp[64]; - ulong cpuclk; - - if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) { - cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; - cgu_init (cpuclk); - ebu_init (cpuclk); - sdram_init (cpuclk); - } - - return 0; -} diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S deleted file mode 100644 index 71adaa1..0000000 --- a/cpu/mips/incaip_wdt.S +++ /dev/null @@ -1,72 +0,0 @@ -/* - * INCA-IP Watchdog timer management code. - * - * Copyright (c) 2003 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include - - -#define WD_BASE 0xb8000000 -#define WD_CON0(value) 0x0020(value) -#define WD_CON1(value) 0x0024(value) -#define WD_DISABLE 0x00000008 -#define WD_ENABLE 0x00000000 -#define WD_WRITE_PW 0xFFFC00F8 -#define WD_WRITE_ENDINIT 0xFFFC00F3 -#define WD_WRITE_INIT 0xFFFC00F2 - - - .globl disable_incaip_wdt -disable_incaip_wdt: - li t0, WD_BASE - - /* Calculate password. - */ - lw t2, WD_CON1(t0) - and t2, 0xC - - lw t3, WD_CON0(t0) - and t3, 0xFFFFFF01 - - or t3, t2 - or t3, 0xF0 - - sw t3, WD_CON0(t0) /* write password */ - - /* Clear ENDINIT. - */ - li t1, WD_WRITE_INIT - sw t1, WD_CON0(t0) - - - li t1, WD_DISABLE - sw t1, WD_CON1(t0) /* disable watchdog */ - li t1, WD_WRITE_PW - sw t1, WD_CON0(t0) /* write password */ - li t1, WD_WRITE_ENDINIT - sw t1, WD_CON0(t0) /* end command */ - - j ra - nop diff --git a/cpu/mips/interrupts.c b/cpu/mips/interrupts.c deleted file mode 100644 index 87f7a9f..0000000 --- a/cpu/mips/interrupts.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -void enable_interrupts(void) -{ -} - -int disable_interrupts(void) -{ - return 0; -} diff --git a/cpu/mips/start.S b/cpu/mips/start.S deleted file mode 100644 index e91e213..0000000 --- a/cpu/mips/start.S +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Startup Code for MIPS32 CPU-core - * - * Copyright (c) 2003 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include - - -#define RVECENT(f,n) \ - b f; nop -#define XVECENT(f,bev) \ - b f ; \ - li k0,bev - - .set noreorder - - .globl _start - .text -_start: - RVECENT(reset,0) /* U-boot entry point */ - RVECENT(reset,1) /* software reboot */ -#if defined(CONFIG_INCA_IP) - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ - .word 0x00000000 /* phase of the flash */ -#elif defined(CONFIG_PURPLE) - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ -#else - RVECENT(romReserved,2) -#endif - RVECENT(romReserved,3) - RVECENT(romReserved,4) - RVECENT(romReserved,5) - RVECENT(romReserved,6) - RVECENT(romReserved,7) - RVECENT(romReserved,8) - RVECENT(romReserved,9) - RVECENT(romReserved,10) - RVECENT(romReserved,11) - RVECENT(romReserved,12) - RVECENT(romReserved,13) - RVECENT(romReserved,14) - RVECENT(romReserved,15) - RVECENT(romReserved,16) - RVECENT(romReserved,17) - RVECENT(romReserved,18) - RVECENT(romReserved,19) - RVECENT(romReserved,20) - RVECENT(romReserved,21) - RVECENT(romReserved,22) - RVECENT(romReserved,23) - RVECENT(romReserved,24) - RVECENT(romReserved,25) - RVECENT(romReserved,26) - RVECENT(romReserved,27) - RVECENT(romReserved,28) - RVECENT(romReserved,29) - RVECENT(romReserved,30) - RVECENT(romReserved,31) - RVECENT(romReserved,32) - RVECENT(romReserved,33) - RVECENT(romReserved,34) - RVECENT(romReserved,35) - RVECENT(romReserved,36) - RVECENT(romReserved,37) - RVECENT(romReserved,38) - RVECENT(romReserved,39) - RVECENT(romReserved,40) - RVECENT(romReserved,41) - RVECENT(romReserved,42) - RVECENT(romReserved,43) - RVECENT(romReserved,44) - RVECENT(romReserved,45) - RVECENT(romReserved,46) - RVECENT(romReserved,47) - RVECENT(romReserved,48) - RVECENT(romReserved,49) - RVECENT(romReserved,50) - RVECENT(romReserved,51) - RVECENT(romReserved,52) - RVECENT(romReserved,53) - RVECENT(romReserved,54) - RVECENT(romReserved,55) - RVECENT(romReserved,56) - RVECENT(romReserved,57) - RVECENT(romReserved,58) - RVECENT(romReserved,59) - RVECENT(romReserved,60) - RVECENT(romReserved,61) - RVECENT(romReserved,62) - RVECENT(romReserved,63) - XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */ - RVECENT(romReserved,65) - RVECENT(romReserved,66) - RVECENT(romReserved,67) - RVECENT(romReserved,68) - RVECENT(romReserved,69) - RVECENT(romReserved,70) - RVECENT(romReserved,71) - RVECENT(romReserved,72) - RVECENT(romReserved,73) - RVECENT(romReserved,74) - RVECENT(romReserved,75) - RVECENT(romReserved,76) - RVECENT(romReserved,77) - RVECENT(romReserved,78) - RVECENT(romReserved,79) - XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */ - RVECENT(romReserved,81) - RVECENT(romReserved,82) - RVECENT(romReserved,83) - RVECENT(romReserved,84) - RVECENT(romReserved,85) - RVECENT(romReserved,86) - RVECENT(romReserved,87) - RVECENT(romReserved,88) - RVECENT(romReserved,89) - RVECENT(romReserved,90) - RVECENT(romReserved,91) - RVECENT(romReserved,92) - RVECENT(romReserved,93) - RVECENT(romReserved,94) - RVECENT(romReserved,95) - XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */ - RVECENT(romReserved,97) - RVECENT(romReserved,98) - RVECENT(romReserved,99) - RVECENT(romReserved,100) - RVECENT(romReserved,101) - RVECENT(romReserved,102) - RVECENT(romReserved,103) - RVECENT(romReserved,104) - RVECENT(romReserved,105) - RVECENT(romReserved,106) - RVECENT(romReserved,107) - RVECENT(romReserved,108) - RVECENT(romReserved,109) - RVECENT(romReserved,110) - RVECENT(romReserved,111) - XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */ - RVECENT(romReserved,113) - RVECENT(romReserved,114) - RVECENT(romReserved,115) - RVECENT(romReserved,116) - RVECENT(romReserved,116) - RVECENT(romReserved,118) - RVECENT(romReserved,119) - RVECENT(romReserved,120) - RVECENT(romReserved,121) - RVECENT(romReserved,122) - RVECENT(romReserved,123) - RVECENT(romReserved,124) - RVECENT(romReserved,125) - RVECENT(romReserved,126) - RVECENT(romReserved,127) - - /* We hope there are no more reserved vectors! - * 128 * 8 == 1024 == 0x400 - * so this is address R_VEC+0x400 == 0xbfc00400 - */ -#ifdef CONFIG_PURPLE -/* 0xbfc00400 */ - .word 0xdc870000 - .word 0xfca70000 - .word 0x20840008 - .word 0x20a50008 - .word 0x20c6ffff - .word 0x14c0fffa - .word 0x00000000 - .word 0x03e00008 - .word 0x00000000 - .word 0x00000000 -/* 0xbfc00428 */ - .word 0xdc870000 - .word 0xfca70000 - .word 0x20840008 - .word 0x20a50008 - .word 0x20c6ffff - .word 0x14c0fffa - .word 0x00000000 - .word 0x03e00008 - .word 0x00000000 - .word 0x00000000 -#endif /* CONFIG_PURPLE */ - .align 4 -reset: - - /* Clear watch registers. - */ - mtc0 zero, CP0_WATCHLO - mtc0 zero, CP0_WATCHHI - - /* STATUS register */ -#ifdef CONFIG_TB0229 - li k0, ST0_CU0 -#else - mfc0 k0, CP0_STATUS -#endif - li k1, ~ST0_IE - and k0, k1 - mtc0 k0, CP0_STATUS - - /* CAUSE register */ - mtc0 zero, CP0_CAUSE - - /* Init Timer */ - mtc0 zero, CP0_COUNT - mtc0 zero, CP0_COMPARE - - /* CONFIG0 register */ - li t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG - - /* Initialize GOT pointer. - */ - bal 1f - nop - .word _GLOBAL_OFFSET_TABLE_ - 1: - move gp, ra - lw t1, 0(ra) - move gp, t1 - -#ifdef CONFIG_INCA_IP - /* Disable INCA-IP Watchdog. - */ - la t9, disable_incaip_wdt - jalr t9 - nop -#endif - - /* Initialize any external memory. - */ - la t9, lowlevel_init - jalr t9 - nop - - /* Initialize caches... - */ - la t9, mips_cache_reset - jalr t9 - nop - - /* ... and enable them. - */ - li t0, CONF_CM_CACHABLE_NONCOHERENT - mtc0 t0, CP0_CONFIG - - - /* Set up temporary stack. - */ - li a0, CFG_INIT_SP_OFFSET - la t9, mips_cache_lock - jalr t9 - nop - - li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET - la sp, 0(t0) - - la t9, board_init_f - j t9 - nop - - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * a0 = addr_sp - * a1 = gd - * a2 = destination address - */ - .globl relocate_code - .ent relocate_code -relocate_code: - move sp, a0 /* Set new stack pointer */ - - li t0, CFG_MONITOR_BASE - la t3, in_ram - lw t2, -12(t3) /* t2 <-- uboot_end_data */ - move t1, a2 - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address - */ - move t6, gp - sub gp, CFG_MONITOR_BASE - add gp, a2 /* gp now adjusted */ - sub t6, gp, t6 /* t6 <-- relocation offset */ - - /* - * t0 = source address - * t1 = target address - * t2 = source end address - */ - /* On the purple board we copy the code earlier in a special way - * in order to solve flash problems - */ -#ifndef CONFIG_PURPLE -1: - lw t3, 0(t0) - sw t3, 0(t1) - addu t0, 4 - ble t0, t2, 1b - addu t1, 4 /* delay slot */ -#endif - - /* If caches were enabled, we would have to flush them here. - */ - - /* Jump to where we've relocated ourselves. - */ - addi t0, a2, in_ram - _start - j t0 - nop - - .word uboot_end_data - .word uboot_end - .word num_got_entries - -in_ram: - /* Now we want to update GOT. - */ - lw t3, -4(t0) /* t3 <-- num_got_entries */ - addi t4, gp, 8 /* Skipping first two entries. */ - li t2, 2 -1: - lw t1, 0(t4) - beqz t1, 2f - add t1, t6 - sw t1, 0(t4) -2: - addi t2, 1 - blt t2, t3, 1b - addi t4, 4 /* delay slot */ - - /* Clear BSS. - */ - lw t1, -12(t0) /* t1 <-- uboot_end_data */ - lw t2, -8(t0) /* t2 <-- uboot_end */ - add t1, t6 /* adjust pointers */ - add t2, t6 - - sub t1, 4 -1: addi t1, 4 - bltl t1, t2, 1b - sw zero, 0(t1) /* delay slot */ - - move a0, a1 - la t9, board_init_r - j t9 - move a1, a2 /* delay slot */ - - .end relocate_code - - - /* Exception handlers. - */ -romReserved: - b romReserved - -romExcHandle: - b romExcHandle diff --git a/cpu/mpc5xx/Makefile b/cpu/mpc5xx/Makefile deleted file mode 100644 index b787b61..0000000 --- a/cpu/mpc5xx/Makefile +++ /dev/null @@ -1,52 +0,0 @@ -# -# (C) Copyright 2003 -# Martin Winistoerfer, martinwinistoerfer@gmx.ch. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# File: cpu/mpc5xx/Makefile -# -# Discription: Makefile to build mpc5xx cpu configuration. -# Will include top config.mk which itselfs -# uses the definitions made in cpu/mpc5xx/config.mk -# - - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.S -OBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk deleted file mode 100644 index 5b26a76..0000000 --- a/cpu/mpc5xx/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2003 -# Martin Winistoerfer, martinwinistoerfer@gmx.ch. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# File: config.mk -# -# Discription: compiler flags and make definitions -# - - -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float diff --git a/cpu/mpc5xx/cpu.c b/cpu/mpc5xx/cpu.c deleted file mode 100644 index 0c22a31..0000000 --- a/cpu/mpc5xx/cpu.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, - */ - -/* - * File: cpu.c - * - * Discription: Some cpu specific function for watchdog, - * cpu version test, clock setting ... - * - */ - - -#include -#include -#include -#include - - -#if (defined(CONFIG_MPC555)) -# define ID_STR "MPC555/556" - -/* - * Check version of cpu with Processor Version Register (PVR) - */ -static int check_cpu_version (long clock, uint pvr, uint immr) -{ - char buf[32]; - /* The highest 16 bits should be 0x0002 for a MPC555/556 */ - if ((pvr >> 16) == 0x0002) { - printf (" " ID_STR " Version %x", (pvr >> 16)); - printf (" at %s MHz:", strmhz (buf, clock)); - } else { - printf ("Not supported cpu version"); - return -1; - } - return 0; -} -#endif /* CONFIG_MPC555 */ - - -/* - * Check version of mpc5xx - */ -int checkcpu (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong clock = gd->cpu_clk; - uint immr = get_immr (0); /* Return full IMMR contents */ - uint pvr = get_pvr (); /* Retrieve PVR register */ - - puts ("CPU: "); - - return check_cpu_version (clock, pvr, immr); -} - -/* - * Called by macro WATCHDOG_RESET - */ -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - reset_5xx_watchdog ((immap_t *) CFG_IMMR); - if (re_enable) - enable_interrupts (); -} - -/* - * Will clear software reset - */ -void reset_5xx_watchdog (volatile immap_t * immr) -{ - /* Use the MPC5xx Internal Watchdog */ - immr->im_siu_conf.sc_swsr = 0x556c; /* Prevent SW time-out */ - immr->im_siu_conf.sc_swsr = 0xaa39; -} - -#endif /* CONFIG_WATCHDOG */ - - -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk (void) -{ - DECLARE_GLOBAL_DATA_PTR; - volatile immap_t *immr = (volatile immap_t *) CFG_IMMR; - ulong oscclk, factor; - - if (immr->im_clkrst.car_sccr & SCCR_TBS) { - return (gd->cpu_clk / 16); - } - - factor = (((CFG_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1; - - oscclk = gd->cpu_clk / factor; - - if ((immr->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { - return (oscclk / 4); - } - return (oscclk / 16); -} - -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} - -/* - * Reset board - */ -int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ -#if defined(CONFIG_PATI) - volatile ulong *addr = (ulong *) CFG_RESET_ADDRESS; - *addr = 1; -#else - ulong addr; - - /* Interrupts off, enable reset */ - __asm__ volatile (" mtspr 81, %r0 \n\t" - " mfmsr %r3 \n\t" - " rlwinm %r31,%r3,0,25,23\n\t" - " mtmsr %r31 \n\t"); - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; -#else - /* - * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. - * "(ulong)-1" used to be a good choice for many systems... - */ - addr = CFG_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*) (void)) addr) (); -#endif /* #if defined(CONFIG_PATI) */ - return 1; -} diff --git a/cpu/mpc5xx/cpu_init.c b/cpu/mpc5xx/cpu_init.c deleted file mode 100644 index f4cd24b..0000000 --- a/cpu/mpc5xx/cpu_init.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, - */ - -/* - * File: cpu_init.c - * - * Discription: Contains initialisation functions to setup - * the cpu properly - * - */ - -#include -#include -#include - -/* - * Setup essential cpu registers to run - */ -void cpu_init_f (volatile immap_t * immr) -{ - volatile memctl5xx_t *memctl = &immr->im_memctl; - ulong reg; - - /* SYPCR - contains watchdog control. This will enable watchdog */ - /* if CONFIG_WATCHDOG is set */ - immr->im_siu_conf.sc_sypcr = CFG_SYPCR; - -#if defined(CONFIG_WATCHDOG) - reset_5xx_watchdog (immr); -#endif - - /* SIUMCR - contains debug pin configuration */ - immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR; - - /* Initialize timebase. Unlock TBSCRK */ - immr->im_sitk.sitk_tbscrk = KAPWR_KEY; - immr->im_sit.sit_tbscr = CFG_TBSCR; - - /* Full IMB bus speed */ - immr->im_uimb.uimb_umcr = CFG_UMCR; - - /* Time base and decrementer will be enables (TBE) */ - /* in init_timebase() in time.c called from board_init_f(). */ - - /* Initialize the PIT. Unlock PISCRK */ - immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CFG_PISCR; - -#if !defined(CONFIG_PATI) - /* PATI sest PLL in start.S */ - /* PLL (CPU clock) settings */ - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - - /* If CFG_PLPRCR (set in the various *_config.h files) tries to - * set the MF field, then just copy CFG_PLPRCR over car_plprcr, - * otherwise OR in CFG_PLPRCR so we do not change the currentMF - * field value. - */ -#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0) - reg = CFG_PLPRCR; /* reset control bits */ -#else - reg = immr->im_clkrst.car_plprcr; - reg &= PLPRCR_MF_MSK; /* isolate MF field */ - reg |= CFG_PLPRCR; /* reset control bits */ -#endif - immr->im_clkrst.car_plprcr = reg; - -#endif /* !defined(CONFIG_PATI) */ - - /* System integration timers. CFG_MASK has EBDF configuration */ - immr->im_clkrstk.cark_sccrk = KAPWR_KEY; - reg = immr->im_clkrst.car_sccr; - reg &= SCCR_MASK; - reg |= CFG_SCCR; - immr->im_clkrst.car_sccr = reg; - - /* Memory Controller */ - memctl->memc_br0 = CFG_BR0_PRELIM; - memctl->memc_or0 = CFG_OR0_PRELIM; - -#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; -#endif - -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; -#endif - -#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; -#endif - -} - -/* - * Initialize higher level parts of cpu - */ -int cpu_init_r (void) -{ - /* Nothing to do at the moment */ - return (0); -} diff --git a/cpu/mpc5xx/interrupts.c b/cpu/mpc5xx/interrupts.c deleted file mode 100644 index 7f6e136..0000000 --- a/cpu/mpc5xx/interrupts.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * (C) Copyright 2000-2002 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, - */ - -/* - * File: interrupt.c - * - * Discription: Contains interrupt routines needed by U-Boot - * - */ - -#include -#include -#include -#include - -#if defined(CONFIG_PATI) -/* PATI uses IRQs for PCI doorbell */ -#undef NR_IRQS -#define NR_IRQS 16 -#endif - -struct interrupt_action { - interrupt_handler_t *handler; - void *arg; - int count; -}; - -static struct interrupt_action irq_vecs[NR_IRQS]; - -/* - * Initialise interrupts - */ - -int interrupt_init_cpu (ulong *decrementer_count) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - int vec; - - /* Decrementer used here for status led */ - *decrementer_count = get_tbclk () / CFG_HZ; - - /* Disable all interrupts */ - immr->im_siu_conf.sc_simask = 0; - for (vec=0; vecim_siu_conf.sc_sivec; - irq = vec >> 26; - v_bit = 0x80000000UL >> irq; - - /* - * Read Interrupt Mask Register and Mask Interrupts - */ - simask = immr->im_siu_conf.sc_simask; - newmask = simask & (~(0xFFFF0000 >> irq)); - immr->im_siu_conf.sc_simask = newmask; - - if (!(irq & 0x1)) { /* External Interrupt ? */ - ulong siel; - - /* - * Read Interrupt Edge/Level Register - */ - siel = immr->im_siu_conf.sc_siel; - - if (siel & v_bit) { /* edge triggered interrupt ? */ - /* - * Rewrite SIPEND Register to clear interrupt - */ - immr->im_siu_conf.sc_sipend = v_bit; - } - } - - if (irq_vecs[irq].handler != NULL) { - irq_vecs[irq].handler (irq_vecs[irq].arg); - } else { - printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", - irq, vec); - /* turn off the bogus interrupt to avoid it from now */ - simask &= ~v_bit; - } - /* - * Re-Enable old Interrupt Mask - */ - immr->im_siu_conf.sc_simask = simask; -} - -/* - * Install and free an interrupt handler - */ -void irq_install_handler (int vec, interrupt_handler_t * handler, - void *arg) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - /* SIU interrupt */ - if (irq_vecs[vec].handler != NULL) { - printf ("SIU interrupt %d 0x%x\n", - vec, - (uint) handler); - } - irq_vecs[vec].handler = handler; - irq_vecs[vec].arg = arg; - immr->im_siu_conf.sc_simask |= 1 << (31 - vec); -#if 0 - printf ("Install SIU interrupt for vector %d ==> %p\n", - vec, handler); -#endif -} - -void irq_free_handler (int vec) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - /* SIU interrupt */ -#if 0 - printf ("Free CPM interrupt for vector %d\n", - vec); -#endif - immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec)); - irq_vecs[vec].handler = NULL; - irq_vecs[vec].arg = NULL; -} - -/* - * Timer interrupt - gets called when bit 0 of DEC changes from - * 0. Decrementer is enabled with bit TBE in TBSCR. - */ -void timer_interrupt_cpu (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - -#if 0 - printf ("*** Timer Interrupt *** "); -#endif - /* Reset Timer Status Bit and Timers Interrupt Status */ - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - __asm__ ("nop"); - immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST; - - return; -} - -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) -/******************************************************************************* - * - * irqinfo - print information about IRQs - * - */ -int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int vec; - - printf ("\nInterrupt-Information:\n"); - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec -#include -#include -#include - - -/* - * Local function prototypes - */ - -static int ready_to_send(void); - -/* - * Minimal global serial functions needed to use one of the SCI modules. - */ - -int serial_init (void) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - - serial_setbrg(); - -#if defined(CONFIG_5xx_CONS_SCI1) - /* 10-Bit, 1 start bit, 8 data bit, no parity, 1 stop bit */ - immr->im_qsmcm.qsmcm_scc1r1 = SCI_M_10; - immr->im_qsmcm.qsmcm_scc1r1 = SCI_TE | SCI_RE; -#else - immr->im_qsmcm.qsmcm_scc2r1 = SCI_M_10; - immr->im_qsmcm.qsmcm_scc2r1 = SCI_TE | SCI_RE; -#endif - return 0; -} - -void serial_putc(const char c) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - - /* Test for completition */ - if(ready_to_send()) { -#if defined(CONFIG_5xx_CONS_SCI1) - immr->im_qsmcm.qsmcm_sc1dr = (short)c; -#else - immr->im_qsmcm.qsmcm_sc2dr = (short)c; -#endif - if(c == '\n') { - if(ready_to_send()); -#if defined(CONFIG_5xx_CONS_SCI1) - immr->im_qsmcm.qsmcm_sc1dr = (short)'\r'; -#else - immr->im_qsmcm.qsmcm_sc2dr = (short)'\r'; -#endif - } - } -} - -int serial_getc(void) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile short status; - unsigned char tmp; - - /* New data ? */ - do { -#if defined(CONFIG_5xx_CONS_SCI1) - status = immr->im_qsmcm.qsmcm_sc1sr; -#else - status = immr->im_qsmcm.qsmcm_sc2sr; -#endif - -#if defined(CONFIG_WATCHDOG) - reset_5xx_watchdog (immr); -#endif - } while ((status & SCI_RDRF) == 0); - - /* Read data */ -#if defined(CONFIG_5xx_CONS_SCI1) - tmp = (unsigned char)(immr->im_qsmcm.qsmcm_sc1dr & SCI_SCXDR_MK); -#else - tmp = (unsigned char)( immr->im_qsmcm.qsmcm_sc2dr & SCI_SCXDR_MK); -#endif - return tmp; -} - -int serial_tstc() -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - short status; - - /* New data character ? */ -#if defined(CONFIG_5xx_CONS_SCI1) - status = immr->im_qsmcm.qsmcm_sc1sr; -#else - status = immr->im_qsmcm.qsmcm_sc2sr; -#endif - return (status & SCI_RDRF); -} - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - volatile immap_t *immr = (immap_t *)CFG_IMMR; - short scxbr; - - /* Set baudrate */ - scxbr = (gd->cpu_clk / (32 * gd->baudrate)); -#if defined(CONFIG_5xx_CONS_SCI1) - immr->im_qsmcm.qsmcm_scc1r0 = (scxbr & SCI_SCXBR_MK); -#else - immr->im_qsmcm.qsmcm_scc2r0 = (scxbr & SCI_SCXBR_MK); -#endif -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc(*s); - ++s; - } -} - -int ready_to_send(void) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile short status; - - do { -#if defined(CONFIG_5xx_CONS_SCI1) - status = immr->im_qsmcm.qsmcm_sc1sr; -#else - status = immr->im_qsmcm.qsmcm_sc2sr; -#endif - -#if defined(CONFIG_WATCHDOG) - reset_5xx_watchdog (immr); -#endif - } while ((status & SCI_TDRE) == 0); - return 1; - -} diff --git a/cpu/mpc5xx/speed.c b/cpu/mpc5xx/speed.c deleted file mode 100644 index f6097f5..0000000 --- a/cpu/mpc5xx/speed.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, - */ - -/* - * File: speed.c - * - * Discription: Provides cpu speed calculation - * - */ - -#include -#include -#include - -/* - * Get cpu and bus clock - */ -int get_clocks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - volatile immap_t *immr = (immap_t *) CFG_IMMR; - -#ifndef CONFIG_5xx_GCLK_FREQ - uint divf = (immr->im_clkrst.car_plprcr & PLPRCR_DIVF_MSK); - uint mf = ((immr->im_clkrst.car_plprcr & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT); - ulong vcoout; - - vcoout = (CFG_OSC_CLK / (divf + 1)) * (mf + 1) * 2; - if(immr->im_clkrst.car_plprcr & PLPRCR_CSRC_MSK) { - gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1)); - } else { - gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK)); - } - -#else /* CONFIG_5xx_GCLK_FREQ */ - gd->bus_clk = CONFIG_5xx_GCLK_FREQ; -#endif /* CONFIG_5xx_GCLK_FREQ */ - - if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) { - /* No Bus Divider active */ - gd->bus_clk = gd->cpu_clk; - } else { - /* CLKOUT is GCLK / 2 */ - gd->bus_clk = gd->cpu_clk / 2; - } - return (0); -} diff --git a/cpu/mpc5xx/spi.c b/cpu/mpc5xx/spi.c deleted file mode 100644 index 81c9ddb..0000000 --- a/cpu/mpc5xx/spi.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * , - * - * Copyright (c) 2001 Gerd Mennchen - * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MPC5xx CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd@denx.de - * - * Ported to MPC5xx - * Copyright (c) 2003 Denis Peter, MPL AG Switzerland, d.petr@mpl.ch. - */ - -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_SPI) - -#undef DEBUG - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - - -#ifdef DEBUG - -#define DPRINT(a) printf a; -/* ----------------------------------------------- - * Helper functions to peek into tx and rx buffers - * ----------------------------------------------- */ -static const char * const hex_digit = "0123456789ABCDEF"; - -static char quickhex (int i) -{ - return hex_digit[i]; -} - -static void memdump (void *pv, int num) -{ - int i; - unsigned char *pc = (unsigned char *) pv; - - for (i = 0; i < num; i++) - printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); - printf ("\t"); - for (i = 0; i < num; i++) - printf ("%c", isprint (pc[i]) ? pc[i] : '.'); - printf ("\n"); -} -#else /* !DEBUG */ - -#define DPRINT(a) - -#endif /* DEBUG */ - -/* ------------------- - * Function prototypes - * ------------------- */ -void spi_init (void); - -ssize_t spi_read (uchar *, int, uchar *, int); -ssize_t spi_write (uchar *, int, uchar *, int); -ssize_t spi_xfer (size_t); - - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ - -void spi_init_f (void) -{ - int i; - - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - - immr = (immap_t *) CFG_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - - qsmcm->qsmcm_qsmcr = 0; /* all accesses enabled */ - qsmcm->qsmcm_qspi_il = 0; /* lowest IRQ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PQSPAR[00] = 0 reserved - * PQSPAR[01] = 1 [0x4000] -> PERI: (SPICS3) - * PQSPAR[02] = 0 [0x0000] -> GPIO - * PQSPAR[03] = 0 [0x0000] -> GPIO - * PQSPAR[04] = 1 [0x0800] -> PERI: (SPICS0) - * PQSPAR[05] = 0 reseved - * PQSPAR[06] = 1 [0x0200] -> PERI: (SPIMOSI) - * PQSPAR[07] = 1 [0x0100] -> PERI: (SPIMISO) - * -------------------------------------------- */ - qsmcm->qsmcm_pqspar = 0x3 | (CFG_SPI_CS_USED << 3); - - /* -------------------------------------------- - * DDRQS[00] = 0 reserved - * DDRQS[01] = 1 [0x0040] -> SPICS3 Output - * DDRQS[02] = 0 [0x0000] -> GPIO Output - * DDRQS[03] = 0 [0x0000] -> GPIO Output - * DDRQS[04] = 1 [0x0008] -> SPICS0 Output - * DDRQS[05] = 1 [0x0004] -> SPICLK Output - * DDRQS[06] = 1 [0x0002] -> SPIMOSI Output - * DDRQS[07] = 0 [0x0001] -> SPIMISO Input - * -------------------------------------------- */ - qsmcm->qsmcm_ddrqs = 0x7E; - /* -------------------------------------------- - * Base state for used SPI CS pins, if base = 0 active must be 1 - * PORTQS[00] = 0 reserved - * PORTQS[01] = 0 reserved - * PORTQS[02] = 0 reserved - * PORTQS[03] = 0 reserved - * PORTQS[04] = 0 [0x0000] RxD2 - * PORTQS[05] = 1 [0x0400] TxD2 - * PORTQS[06] = 0 [0x0000] RxD1 - * PORTQS[07] = 1 [0x0100] TxD1 - * PORTQS[08] = 0 reserved - * PORTQS[09] = 0 [0x0000] -> SPICS3 Base Output - * PORTQS[10] = 0 [0x0000] -> SPICS2 Base Output - * PORTQS[11] = 0 [0x0000] -> SPICS1 Base Output - * PORTQS[12] = 0 [0x0000] -> SPICS0 Base Output - * PORTQS[13] = 0 [0x0004] -> SPICLK Output - * PORTQS[14] = 0 [0x0002] -> SPIMOSI Output - * PORTQS[15] = 0 [0x0001] -> SPIMISO Input - * -------------------------------------------- */ - qsmcm->qsmcm_portqs |= (CFG_SPI_CS_BASE << 3); - /* -------------------------------------------- - * Controll Register 0 - * SPCR0[00] = 1 (0x8000) Master - * SPCR0[01] = 0 (0x0000) Wired-Or - * SPCR0[2..5] = (0x2000) Bits per transfer (default 8) - * SPCR0[06] = 0 (0x0000) Normal polarity - * SPCR0[07] = 0 (0x0000) Normal Clock Phase - * SPCR0[08..15] = 14 1.4MHz - */ - qsmcm->qsmcm_spcr0=0xA00E; - /* -------------------------------------------- - * Controll Register 1 - * SPCR1[00] = 0 (0x0000) QSPI enabled - * SPCR1[1..7] = (0x7F00) Delay before Transfer - * SPCR1[8..15] = (0x0000) Delay After transfer (204.8usec@40MHz) - */ - qsmcm->qsmcm_spcr1=0x7F00; - /* -------------------------------------------- - * Controll Register 2 - * SPCR2[00] = 0 (0x0000) SPI IRQs Disabeld - * SPCR2[01] = 0 (0x0000) No Wrap around - * SPCR2[02] = 0 (0x0000) Wrap to 0 - * SPCR2[3..7] = (0x0000) End Queue pointer = 0 - * SPCR2[8..10] = 0 (0x0000) reserved - * SPCR2[11..15] = 0 (0x0000) NewQueue Address = 0 - */ - qsmcm->qsmcm_spcr2=0x0000; - /* -------------------------------------------- - * Controll Register 3 - * SPCR3[00..04] = 0 (0x0000) reserved - * SPCR3[05] = 0 (0x0000) Feedback disabled - * SPCR3[06] = 0 (0x0000) IRQ on HALTA & MODF disabled - * SPCR3[07] = 0 (0x0000) Not halted - */ - qsmcm->qsmcm_spcr3=0x00; - /* -------------------------------------------- - * SPSR (Controll Register 3) Read only/ reset Flags 08,09,10 - * SPCR3[08] = 1 (0x80) QSPI finished - * SPCR3[09] = 1 (0x40) Mode Fault Flag - * SPCR3[10] = 1 (0x20) HALTA - * SPCR3[11..15] = 0 (0x0000) Last executed command - */ - qsmcm->qsmcm_spsr=0xE0; - /*------------------------------------------- - * Setup RAM - */ - for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; - } - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * Dummy, all initializations have been done in spi_init_r - * *********************************************************************** */ -void spi_init_r (void) -{ - return; - -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int i,dlen; - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - - immr = (immap_t *) CFG_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; - } - qsmcm->qsmcm_tranram[0] = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - i=0; - qsmcm->qsmcm_tranram[i++] = SPI_EEPROM_WRITE; /* WRITE memory array */ - qsmcm->qsmcm_tranram[i++] = addr[0]; - qsmcm->qsmcm_tranram[i++] = addr[1]; - - for(dlen=0;dlenqsmcm_tranram[i+dlen] = buffer[dlen]; /* WRITE memory array */ - } - /* transmit it */ - spi_xfer(i+dlen); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - qsmcm->qsmcm_tranram[0] = SPI_EEPROM_RDSR; /* read status */ - qsmcm->qsmcm_tranram[1] = 0; - spi_xfer(2); - if (!(qsmcm->qsmcm_recram[1] & 1)) { - break; - } - udelay(1000); - } - if (i >= 1000) { - printf ("*** spi_write: Time out while writing!\n"); - } - return len; -} - -#define TRANSFER_LEN 16 - -ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int index,i,newlen; - uchar newaddr[2]; - int curraddr; - - curraddr=(addr[alen-2]<<8)+addr[alen-1]; - i=len; - index=0; - do { - newaddr[1]=(curraddr & 0xff); - newaddr[0]=((curraddr>>8) & 0xff); - if(i>TRANSFER_LEN) { - newlen=TRANSFER_LEN; - i-=TRANSFER_LEN; - } - else { - newlen=i; - i=0; - } - short_spi_write (newaddr, 2, &buffer[index], newlen); - index+=newlen; - curraddr+=newlen; - }while(i); - return (len); -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - - immr = (immap_t *) CFG_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - - for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; - } - i=0; - qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */ - qsmcm->qsmcm_tranram[i++] = addr[0] & 0xff; - qsmcm->qsmcm_tranram[i++] = addr[1] & 0xff; - spi_xfer(3 + len); - for(i=0;iqsmcm_recram[i+3]; - } - return len; -} - -ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - int index,i,newlen; - uchar newaddr[2]; - int curraddr; - - curraddr=(addr[alen-2]<<8)+addr[alen-1]; - i=len; - index=0; - do { - newaddr[1]=(curraddr & 0xff); - newaddr[0]=((curraddr>>8) & 0xff); - if(i>TRANSFER_LEN) { - newlen=TRANSFER_LEN; - i-=TRANSFER_LEN; - } - else { - newlen=i; - i=0; - } - short_spi_read (newaddr, 2, &buffer[index], newlen); - index+=newlen; - curraddr+=newlen; - }while(i); - return (len); -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer (size_t count) -{ - volatile immap_t *immr; - volatile qsmcm5xx_t *qsmcm; - int i; - int tm; - ushort status; - immr = (immap_t *) CFG_IMMR; - qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; - DPRINT (("*** spi_xfer entered count %d***\n",count)); - - /* Set CS for device */ - for(i=0;i<(count-1);i++) - qsmcm->qsmcm_comdram[i] = 0x80 | CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ - - qsmcm->qsmcm_comdram[i] = CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ - qsmcm->qsmcm_spcr2=((count-1)&0x1F)<<8; - - DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", count)); - - qsmcm->qsmcm_spsr=0xE0; /* clear all flags */ - - /* start spi transfer */ - DPRINT (("*** spi_xfer: Performing transfer ...\n")); - qsmcm->qsmcm_spcr1 |= 0x8000; /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm=0; tm<1000; ++tm) { - status=qsmcm->qsmcm_spcr1; - if((status & 0x8000)==0) - break; - udelay (1000); - } - if (tm >= 1000) { - printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); - } -#ifdef DEBUG - printf ("\nspi_xfer: txbuf after xfer\n"); - memdump ((void *) qsmcm->qsmcm_tranram, 32); /* dump of txbuf before transmit */ - printf ("spi_xfer: rxbuf after xfer\n"); - memdump ((void *) qsmcm->qsmcm_recram, 32); /* dump of rxbuf after transmit */ - printf ("\nspi_xfer: commbuf after xfer\n"); - memdump ((void *) qsmcm->qsmcm_comdram, 32); /* dump of txbuf before transmit */ - printf ("\n"); -#endif - - return count; -} - -#endif /* CONFIG_SPI */ diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S deleted file mode 100644 index 087435e..0000000 --- a/cpu/mpc5xx/start.S +++ /dev/null @@ -1,603 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000, 2001, 2002 Wolfgang Denk - * Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * File: start.S - * - * Discription: startup code - * - */ - -#include -#include -#include - -#define CONFIG_5xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -/* We don't have a MMU. -*/ -#undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */ - -/* - * Set up GOT: Global Offset Table - * - * Use r14 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - mfspr r3, 638 - li r4, CFG_ISB /* Set ISB bit */ - or r3, r3, r4 - mtspr 638, r3 - li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ - b boot_cold - - . = EXC_OFF_SYS_RESET + 0x20 - - .globl _start_warm -_start_warm: - li r21, BOOTFLAG_WARM /* Software reboot */ - b boot_warm - -boot_cold: -boot_warm: - - /* Initialize machine status; enable machine check interrupt */ - /*----------------------------------------------------------------------*/ - li r3, MSR_KERNEL /* Set ME, RI flags */ - mtmsr r3 - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - /* Initialize debug port registers */ - /*----------------------------------------------------------------------*/ - xor r0, r0, r0 /* Clear R0 */ - mtspr LCTRL1, r0 /* Initialize debug port regs */ - mtspr LCTRL2, r0 - mtspr COUNTA, r0 - mtspr COUNTB, r0 - -#if defined(CONFIG_PATI) - /* the external flash access on PATI fails if programming the PLL to 40MHz. - * Copy the PLL programming code to the internal RAM and execute it - *----------------------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l - addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET - - lis r4, CFG_INIT_RAM_ADDR@h - ori r4, r4, CFG_INIT_RAM_ADDR@l - mtlr r4 - addis r5,0,0x0 - ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2) - mtctr r5 - addi r3, r3, -4 - addi r4, r4, -4 -0: - lwzu r0,4(r3) - stwu r0,4(r4) - bdnz 0b /* copy loop */ - blrl -#endif - - /* - * Calculate absolute address in FLASH and jump there - *----------------------------------------------------------------------*/ - - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: - - /* Initialize some SPRs that are hard to access from C */ - /*----------------------------------------------------------------------*/ - - lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */ - lis r2, CFG_INIT_SP_ADDR@h - ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */ - /* Note: R0 is still 0 here */ - stwu r0, -4(r1) /* Clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* - * Disable serialized ifetch and show cycles - * (i.e. set processor to normal mode) for maximum - * performance. - */ - - li r2, 0x0007 - mtspr ICTRL, r2 - - /* Set up debug mode entry */ - - lis r2, CFG_DER@h - ori r2, r2, CFG_DER@l - mtspr DER, r2 - - /* Let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*----------------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - - mr r3, r21 - /* r3: BOOTFLAG */ - bl board_init_f /* run 1st part of board init code (from Flash) */ - - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - - /* FPU on MPC5xx available. We will use it later. - */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - /* On the MPC8xx, this is a software emulation interrupt. It occurs - * for all unimplemented and illegal instructions. - */ - STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x2000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - - -/* - * unsigned int get_immr (unsigned int mask) - * - * return (mask ? (IMMR & mask) : IMMR); - */ - .globl get_immr -get_immr: - mr r4,r3 /* save mask */ - mfspr r3, IMMR /* IMMR */ - cmpwi 0,r4,0 /* mask != 0 ? */ - beq 4f - and r3,r3,r4 /* IMMR & mask */ -4: - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer in SRAM */ - mr r9, r4 /* Save copy of global data pointer in SRAM */ - mr r10, r5 /* Save copy of monitor destination Address in SRAM */ - - mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r14, r14, r15 - /* the the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 4f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -4: sync - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r14 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - add r0,r0,r11 - stw r0,0(r3) - bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ -2: li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(_end) - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mtlr r4 /* restore link register */ - blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - sync - isync - - blr - - -#if defined(CONFIG_PATI) -/* Program the PLL */ -pll_prog_code_start: - lis r4, (CFG_IMMR + 0x002fc384)@h - ori r4, r4, (CFG_IMMR + 0x002fc384)@l - lis r3, (0x55ccaa33)@h - ori r3, r3, (0x55ccaa33)@l - stw r3, 0(r4) - lis r4, (CFG_IMMR + 0x002fc284)@h - ori r4, r4, (CFG_IMMR + 0x002fc284)@l - lis r3, CFG_PLPRCR@h - ori r3, r3, CFG_PLPRCR@l - stw r3, 0(r4) - addis r3,0,0x0 - ori r3,r3,0xA000 - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - blr -pll_prog_code_end: - nop - blr -#endif diff --git a/cpu/mpc5xx/traps.c b/cpu/mpc5xx/traps.c deleted file mode 100644 index 14fd59e..0000000 --- a/cpu/mpc5xx/traps.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * linux/arch/ppc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -int (*debugger_exception_handler)(struct pt_regs *) = 0; -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x0001000 - - -/* - * Print stack backtrace - */ -void print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -/* - * Print current registers - */ -void show_regs(struct pt_regs * regs) -{ - int i; - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -/* - * General exception handler routine - */ -void _exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -/* - * Machine check exception handler routine - */ -void MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -/* - * Alignment exception handler routine - */ -void AlignmentException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -/* - * Program check exception handler routine - */ -void ProgramCheckException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -/* - * Software emulation exception handler routine - */ -void SoftEmuException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -/* - * Unknown exception handler routine - */ -void UnknownException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -/* - * Debug exception handler routine - */ -void DebugException(struct pt_regs *regs) -{ - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} diff --git a/cpu/mpc5xxx/Makefile b/cpu/mpc5xxx/Makefile deleted file mode 100644 index a97b625..0000000 --- a/cpu/mpc5xxx/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o -OBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \ - loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o - -all: .depend $(START) $(ASOBJS) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(ASOBJS) $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/mpc5xxx/config.mk b/cpu/mpc5xxx/config.mk deleted file mode 100644 index ecd94e9..0000000 --- a/cpu/mpc5xxx/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 -ffixed-r29 \ - -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c deleted file mode 100644 index 2d695d1..0000000 --- a/cpu/mpc5xxx/cpu.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code for the MPC5xxx CPUs - */ - -#include -#include -#include -#include -#include - -int checkcpu (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong clock = gd->cpu_clk; - char buf[32]; -#ifndef CONFIG_MGT5100 - uint svr; -#endif - - puts ("CPU: "); - -#ifdef CONFIG_MGT5100 - puts (CPU_ID_STR); - printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID); -#else - svr = get_svr (); - switch (SVR_VER (svr)) { - case SVR_MPC5200: - printf ("MPC5200"); - break; - default: - printf ("MPC52?? (SVR %08x)", svr); - break; - } - - printf (" v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr)); -#endif - - printf (" at %s MHz\n", strmhz (buf, clock)); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -int -do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - ulong msr; - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* Charge the watchdog timer */ - *(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f; - *(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */ - while(1); - - return 1; - -} - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * - */ -unsigned long get_tbclk (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong tbclk; - - tbclk = (gd->bus_clk + 3L) / 4L; - - return (tbclk); -} - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c deleted file mode 100644 index 3df0050..0000000 --- a/cpu/mpc5xxx/cpu_init.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers. - */ -void cpu_init_f (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned long addecr = (1 << 25); /* Boot_CS */ -#if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100) - addecr |= (1 << 22); /* SDRAM enable */ -#endif - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* - * Memory Controller: configure chip selects and enable them - */ -#if defined(CFG_BOOTCS_START) && defined(CFG_BOOTCS_SIZE) - *(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CFG_BOOTCS_START); - *(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CFG_BOOTCS_START, - CFG_BOOTCS_SIZE); -#endif -#if defined(CFG_BOOTCS_CFG) - *(vu_long *)MPC5XXX_BOOTCS_CFG = CFG_BOOTCS_CFG; -#endif - -#if defined(CFG_CS0_START) && defined(CFG_CS0_SIZE) - *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_CS0_START); - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_CS0_START, CFG_CS0_SIZE); - /* CS0 and BOOT_CS cannot be enabled at once. */ - /* addecr |= (1 << 16); */ -#endif -#if defined(CFG_CS0_CFG) - *(vu_long *)MPC5XXX_CS0_CFG = CFG_CS0_CFG; -#endif - -#if defined(CFG_CS1_START) && defined(CFG_CS1_SIZE) - *(vu_long *)MPC5XXX_CS1_START = START_REG(CFG_CS1_START); - *(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CFG_CS1_START, CFG_CS1_SIZE); - addecr |= (1 << 17); -#endif -#if defined(CFG_CS1_CFG) - *(vu_long *)MPC5XXX_CS1_CFG = CFG_CS1_CFG; -#endif - -#if defined(CFG_CS2_START) && defined(CFG_CS2_SIZE) - *(vu_long *)MPC5XXX_CS2_START = START_REG(CFG_CS2_START); - *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, CFG_CS2_SIZE); - addecr |= (1 << 18); -#endif -#if defined(CFG_CS2_CFG) - *(vu_long *)MPC5XXX_CS2_CFG = CFG_CS2_CFG; -#endif - -#if defined(CFG_CS3_START) && defined(CFG_CS3_SIZE) - *(vu_long *)MPC5XXX_CS3_START = START_REG(CFG_CS3_START); - *(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CFG_CS3_START, CFG_CS3_SIZE); - addecr |= (1 << 19); -#endif -#if defined(CFG_CS3_CFG) - *(vu_long *)MPC5XXX_CS3_CFG = CFG_CS3_CFG; -#endif - -#if defined(CFG_CS4_START) && defined(CFG_CS4_SIZE) - *(vu_long *)MPC5XXX_CS4_START = START_REG(CFG_CS4_START); - *(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CFG_CS4_START, CFG_CS4_SIZE); - addecr |= (1 << 20); -#endif -#if defined(CFG_CS4_CFG) - *(vu_long *)MPC5XXX_CS4_CFG = CFG_CS4_CFG; -#endif - -#if defined(CFG_CS5_START) && defined(CFG_CS5_SIZE) - *(vu_long *)MPC5XXX_CS5_START = START_REG(CFG_CS5_START); - *(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CFG_CS5_START, CFG_CS5_SIZE); - addecr |= (1 << 21); -#endif -#if defined(CFG_CS5_CFG) - *(vu_long *)MPC5XXX_CS5_CFG = CFG_CS5_CFG; -#endif - -#if defined(CONFIG_MPC5200) - addecr |= 1; -#if defined(CFG_CS6_START) && defined(CFG_CS6_SIZE) - *(vu_long *)MPC5XXX_CS6_START = START_REG(CFG_CS6_START); - *(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CFG_CS6_START, CFG_CS6_SIZE); - addecr |= (1 << 26); -#endif -#if defined(CFG_CS6_CFG) - *(vu_long *)MPC5XXX_CS6_CFG = CFG_CS6_CFG; -#endif - -#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE) - *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START); - *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE); - addecr |= (1 << 27); -#endif -#if defined(CFG_CS7_CFG) - *(vu_long *)MPC5XXX_CS7_CFG = CFG_CS7_CFG; -#endif - -#if defined(CFG_CS_BURST) - *(vu_long *)MPC5XXX_CS_BURST = CFG_CS_BURST; -#endif -#if defined(CFG_CS_DEADCYCLE) - *(vu_long *)MPC5XXX_CS_DEADCYCLE = CFG_CS_DEADCYCLE; -#endif -#endif /* CONFIG_MPC5200 */ - - /* Enable chip selects */ - *(vu_long *)MPC5XXX_ADDECR = addecr; - *(vu_long *)MPC5XXX_CS_CTRL = (1 << 24); - - /* Setup pin multiplexing */ -#if defined(CFG_GPS_PORT_CONFIG) - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CFG_GPS_PORT_CONFIG; -#endif - -#if defined(CONFIG_MPC5200) - /* enable timebase */ - *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13); - -# if defined(CFG_IPBSPEED_133) - /* Motorola reports IPB should better run at 133 MHz. */ - *(vu_long *)MPC5XXX_ADDECR |= 1; - /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ - addecr = *(vu_long *)MPC5XXX_CDM_CFG; - addecr &= ~0x103; -# if defined(CFG_PCISPEED_66) - /* pci_clk_sel = 0x01 -> IPB_CLK/2 */ - addecr |= 0x01; -# else - /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ - addecr |= 0x02; -# endif /* CFG_PCISPEED_66 */ - *(vu_long *)MPC5XXX_CDM_CFG = addecr; -# endif /* CFG_IPBSPEED_133 */ - /* Configure the XLB Arbiter */ - *(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff; - *(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111; - -# if defined(CFG_XLB_PIPELINING) - /* Enable piplining */ - *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31); -# endif -#endif /* CONFIG_MPC5200 */ -} - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ - /* mask all interrupts */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xfffffc00; -#elif defined(CONFIG_MPC5200) - *(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xffffff00; -#endif - *(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff; - *(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00; - /* route critical ints to normal ints */ - *(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001; - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC) - /* load FEC microcode */ - loadtask(0, 2); -#endif - - return (0); -} diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c deleted file mode 100644 index 86c8ce6..0000000 --- a/cpu/mpc5xxx/fec.c +++ /dev/null @@ -1,1043 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on mpc4200fec.c, - * (C) Copyright Motorola, Inc., 2000 - */ - -#include -#include -#include -#include -#include -#include "sdma.h" -#include "fec.h" - -/* #define DEBUG 0x28 */ - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ - defined(CONFIG_MPC5xxx_FEC) - -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) -#error "CONFIG_MII has to be defined!" -#endif - -#if (DEBUG & 0x60) -static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec); -static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec); -#endif /* DEBUG */ - -#if (DEBUG & 0x40) -static uint32 local_crc32(char *string, unsigned int crc_value, int len); -#endif - -typedef struct { - uint8 data[1500]; /* actual data */ - int length; /* actual length */ - int used; /* buffer in use or not */ - uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */ -} NBUF; - -int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal); -int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); - -/********************************************************************/ -#if (DEBUG & 0x2) -static void mpc5xxx_fec_phydump (char *devname) -{ - uint16 phyStatus, i; - uint8 phyAddr = CONFIG_PHY_ADDR; - uint8 reg_mask[] = { -#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */ - /* regs to print: 0...7, 16...19, 21, 23, 24 */ - 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, -#else - /* regs to print: 0...8, 16...20 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -#endif - }; - - for (i = 0; i < 32; i++) { - if (reg_mask[i]) { - miiphy_read(devname, phyAddr, i, &phyStatus); - printf("Mii reg %d: 0x%04x\n", i, phyStatus); - } - } -} -#endif - -/********************************************************************/ -static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec) -{ - int ix; - char *data; - static int once = 0; - - for (ix = 0; ix < FEC_RBD_NUM; ix++) { - if (!once) { - data = (char *)malloc(FEC_MAX_PKT_SIZE); - if (data == NULL) { - printf ("RBD INIT FAILED\n"); - return -1; - } - fec->rbdBase[ix].dataPointer = (uint32)data; - } - fec->rbdBase[ix].status = FEC_RBD_EMPTY; - fec->rbdBase[ix].dataLength = 0; - } - once ++; - - /* - * have the last RBD to close the ring - */ - fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP; - fec->rbdIndex = 0; - - return 0; -} - -/********************************************************************/ -static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec) -{ - int ix; - - for (ix = 0; ix < FEC_TBD_NUM; ix++) { - fec->tbdBase[ix].status = 0; - } - - /* - * Have the last TBD to close the ring - */ - fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP; - - /* - * Initialize some indices - */ - fec->tbdIndex = 0; - fec->usedTbdIndex = 0; - fec->cleanTbdNum = FEC_TBD_NUM; -} - -/********************************************************************/ -static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd) -{ - /* - * Reset buffer descriptor as empty - */ - if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) - pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); - else - pRbd->status = FEC_RBD_EMPTY; - - pRbd->dataLength = 0; - - /* - * Now, we have an empty RxBD, restart the SmartDMA receive task - */ - SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); - - /* - * Increment BD count - */ - fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; -} - -/********************************************************************/ -static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec) -{ - volatile FEC_TBD *pUsedTbd; - -#if (DEBUG & 0x1) - printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", - fec->cleanTbdNum, fec->usedTbdIndex); -#endif - - /* - * process all the consumed TBDs - */ - while (fec->cleanTbdNum < FEC_TBD_NUM) { - pUsedTbd = &fec->tbdBase[fec->usedTbdIndex]; - if (pUsedTbd->status & FEC_TBD_READY) { -#if (DEBUG & 0x20) - printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum); -#endif - return; - } - - /* - * clean this buffer descriptor - */ - if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) - pUsedTbd->status = FEC_TBD_WRAP; - else - pUsedTbd->status = 0; - - /* - * update some indeces for a correct handling of the TBD ring - */ - fec->cleanTbdNum++; - fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; - } -} - -/********************************************************************/ -static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac) -{ - uint8 currByte; /* byte for which to compute the CRC */ - int byte; /* loop - counter */ - int bit; /* loop - counter */ - uint32 crc = 0xffffffff; /* initial value */ - - /* - * The algorithm used is the following: - * we loop on each of the six bytes of the provided address, - * and we compute the CRC by left-shifting the previous - * value by one position, so that each bit in the current - * byte of the address may contribute the calculation. If - * the latter and the MSB in the CRC are different, then - * the CRC value so computed is also ex-ored with the - * "polynomium generator". The current byte of the address - * is also shifted right by one bit at each iteration. - * This is because the CRC generatore in hardware is implemented - * as a shift-register with as many ex-ores as the radixes - * in the polynomium. This suggests that we represent the - * polynomiumm itself as a 32-bit constant. - */ - for (byte = 0; byte < 6; byte++) { - currByte = mac[byte]; - for (bit = 0; bit < 8; bit++) { - if ((currByte & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - currByte >>= 1; - } - } - - crc = crc >> 26; - - /* - * Set individual hash table register - */ - if (crc >= 32) { - fec->eth->iaddr1 = (1 << (crc - 32)); - fec->eth->iaddr2 = 0; - } else { - fec->eth->iaddr1 = 0; - fec->eth->iaddr2 = (1 << crc); - } - - /* - * Set physical address - */ - fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; - fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808; -} - -/********************************************************************/ -static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) -{ - DECLARE_GLOBAL_DATA_PTR; - mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; - -#if (DEBUG & 0x1) - printf ("mpc5xxx_fec_init... Begin\n"); -#endif - - /* - * Initialize RxBD/TxBD rings - */ - mpc5xxx_fec_rbd_init(fec); - mpc5xxx_fec_tbd_init(fec); - - /* - * Clear FEC-Lite interrupt event register(IEVENT) - */ - fec->eth->ievent = 0xffffffff; - - /* - * Set interrupt mask register - */ - fec->eth->imask = 0x00000000; - - /* - * Set FEC-Lite receive control register(R_CNTRL): - */ - if (fec->xcv_type == SEVENWIRE) { - /* - * Frame length=1518; 7-wire mode - */ - fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */ - } else { - /* - * Frame length=1518; MII mode; - */ - fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */ - } - - fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */ - if (fec->xcv_type != SEVENWIRE) { - /* - * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock - * and do not drop the Preamble. - */ - fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */ - } - - /* - * Set Opcode/Pause Duration Register - */ - fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */ - - /* - * Set Rx FIFO alarm and granularity value - */ - fec->eth->rfifo_cntrl = 0x0c000000 - | (fec->eth->rfifo_cntrl & ~0x0f000000); - fec->eth->rfifo_alarm = 0x0000030c; -#if (DEBUG & 0x22) - if (fec->eth->rfifo_status & 0x00700000 ) { - printf("mpc5xxx_fec_init() RFIFO error\n"); - } -#endif - - /* - * Set Tx FIFO granularity value - */ - fec->eth->tfifo_cntrl = 0x0c000000 - | (fec->eth->tfifo_cntrl & ~0x0f000000); -#if (DEBUG & 0x2) - printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status); - printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm); -#endif - - /* - * Set transmit fifo watermark register(X_WMRK), default = 64 - */ - fec->eth->tfifo_alarm = 0x00000080; - fec->eth->x_wmrk = 0x2; - - /* - * Set individual address filter for unicast address - * and set physical address registers. - */ - mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr); - - /* - * Set multicast address filter - */ - fec->eth->gaddr1 = 0x00000000; - fec->eth->gaddr2 = 0x00000000; - - /* - * Turn ON cheater FSM: ???? - */ - fec->eth->xmit_fsm = 0x03000000; - -#if defined(CONFIG_MPC5200) - /* - * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't - * work w/ the current receive task. - */ - sdma->PtdCntrl |= 0x00000001; -#endif - - /* - * Set priority of different initiators - */ - sdma->IPR0 = 7; /* always */ - sdma->IPR3 = 6; /* Eth RX */ - sdma->IPR4 = 5; /* Eth Tx */ - - /* - * Clear SmartDMA task interrupt pending bits - */ - SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO); - - /* - * Initialize SmartDMA parameters stored in SRAM - */ - *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase; - *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase; - *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase; - *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase; - - /* - * Enable FEC-Lite controller - */ - fec->eth->ecntrl |= 0x00000006; - -#if (DEBUG & 0x2) - if (fec->xcv_type != SEVENWIRE) - mpc5xxx_fec_phydump (); -#endif - - /* - * Enable SmartDMA receive task - */ - SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); - -#if (DEBUG & 0x1) - printf("mpc5xxx_fec_init... Done \n"); -#endif - - return 1; -} - -/********************************************************************/ -static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) -{ - DECLARE_GLOBAL_DATA_PTR; - mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; - const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ - -#if (DEBUG & 0x1) - printf ("mpc5xxx_fec_init_phy... Begin\n"); -#endif - - /* - * Initialize GPIO pins - */ - if (fec->xcv_type == SEVENWIRE) { - /* 10MBit with 7-wire operation */ -#if defined(CONFIG_TOTAL5200) - /* 7-wire and USB2 on Ethernet */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000; -#else /* !CONFIG_TOTAL5200 */ - /* 7-wire only */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000; -#endif /* CONFIG_TOTAL5200 */ - } else { - /* 100MBit with MD operation */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000; - } - - /* - * Clear FEC-Lite interrupt event register(IEVENT) - */ - fec->eth->ievent = 0xffffffff; - - /* - * Set interrupt mask register - */ - fec->eth->imask = 0x00000000; - - if (fec->xcv_type != SEVENWIRE) { - /* - * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock - * and do not drop the Preamble. - */ - fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */ - } - - if (fec->xcv_type != SEVENWIRE) { - /* - * Initialize PHY(LXT971A): - * - * Generally, on power up, the LXT971A reads its configuration - * pins to check for forced operation, If not cofigured for - * forced operation, it uses auto-negotiation/parallel detection - * to automatically determine line operating conditions. - * If the PHY device on the other side of the link supports - * auto-negotiation, the LXT971A auto-negotiates with it - * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not - * support auto-negotiation, the LXT971A automatically detects - * the presence of either link pulses(10Mbps PHY) or Idle - * symbols(100Mbps) and sets its operating conditions accordingly. - * - * When auto-negotiation is controlled by software, the following - * steps are recommended. - * - * Note: - * The physical address is dependent on hardware configuration. - * - */ - int timeout = 1; - uint16 phyStatus; - - /* - * Reset PHY, then delay 300ns - */ - miiphy_write(dev->name, phyAddr, 0x0, 0x8000); - udelay(1000); - - if (fec->xcv_type == MII10) { - /* - * Force 10Base-T, FDX operation - */ -#if (DEBUG & 0x2) - printf("Forcing 10 Mbps ethernet link... "); -#endif - miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); - /* - miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100); - */ - miiphy_write(dev->name, phyAddr, 0x0, 0x0180); - - timeout = 20; - do { /* wait for link status to go down */ - udelay(10000); - if ((timeout--) == 0) { -#if (DEBUG & 0x2) - printf("hmmm, should not have waited..."); -#endif - break; - } - miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); -#if (DEBUG & 0x2) - printf("="); -#endif - } while ((phyStatus & 0x0004)); /* !link up */ - - timeout = 1000; - do { /* wait for link status to come back up */ - udelay(10000); - if ((timeout--) == 0) { - printf("failed. Link is down.\n"); - break; - } - miiphy_read(dev->name, phyAddr, 0x1, &phyStatus); -#if (DEBUG & 0x2) - printf("+"); -#endif - } while (!(phyStatus & 0x0004)); /* !link up */ - -#if (DEBUG & 0x2) - printf ("done.\n"); -#endif - } else { /* MII100 */ - /* - * Set the auto-negotiation advertisement register bits - */ - miiphy_write(dev->name, phyAddr, 0x4, 0x01e1); - - /* - * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation - */ - miiphy_write(dev->name, phyAddr, 0x0, 0x1200); - - /* - * Wait for AN completion - */ - timeout = 5000; - do { - udelay(1000); - - if ((timeout--) == 0) { -#if (DEBUG & 0x2) - printf("PHY auto neg 0 failed...\n"); -#endif - return -1; - } - - if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) { -#if (DEBUG & 0x2) - printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus); -#endif - return -1; - } - } while (!(phyStatus & 0x0004)); - -#if (DEBUG & 0x2) - printf("PHY auto neg complete! \n"); -#endif - } - - } - -#if (DEBUG & 0x2) - if (fec->xcv_type != SEVENWIRE) - mpc5xxx_fec_phydump (dev->name); -#endif - - -#if (DEBUG & 0x1) - printf("mpc5xxx_fec_init_phy... Done \n"); -#endif - - return 1; -} - -/********************************************************************/ -static void mpc5xxx_fec_halt(struct eth_device *dev) -{ -#if defined(CONFIG_MPC5200) - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; -#endif - mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; - int counter = 0xffff; - -#if (DEBUG & 0x2) - if (fec->xcv_type != SEVENWIRE) - mpc5xxx_fec_phydump (); -#endif - - /* - * mask FEC chip interrupts - */ - fec->eth->imask = 0; - - /* - * issue graceful stop command to the FEC transmitter if necessary - */ - fec->eth->x_cntrl |= 0x00000001; - - /* - * wait for graceful stop to register - */ - while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ; - - /* - * Disable SmartDMA tasks - */ - SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO); - SDMA_TASK_DISABLE (FEC_RECV_TASK_NO); - -#if defined(CONFIG_MPC5200) - /* - * Turn on COMM bus prefetch in the MGT5200 BestComm after we're - * done. It doesn't work w/ the current receive task. - */ - sdma->PtdCntrl &= ~0x00000001; -#endif - - /* - * Disable the Ethernet Controller - */ - fec->eth->ecntrl &= 0xfffffffd; - - /* - * Clear FIFO status registers - */ - fec->eth->rfifo_status &= 0x00700000; - fec->eth->tfifo_status &= 0x00700000; - - fec->eth->reset_cntrl = 0x01000000; - - /* - * Issue a reset command to the FEC chip - */ - fec->eth->ecntrl |= 0x1; - - /* - * wait at least 16 clock cycles - */ - udelay(10); - -#if (DEBUG & 0x3) - printf("Ethernet task stopped\n"); -#endif -} - -#if (DEBUG & 0x60) -/********************************************************************/ - -static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec) -{ - uint16 phyAddr = CONFIG_PHY_ADDR; - uint16 phyStatus; - - if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr) - || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) { - - miiphy_read(devname, phyAddr, 0x1, &phyStatus); - printf("\nphyStatus: 0x%04x\n", phyStatus); - printf("ecntrl: 0x%08x\n", fec->eth->ecntrl); - printf("ievent: 0x%08x\n", fec->eth->ievent); - printf("x_status: 0x%08x\n", fec->eth->x_status); - printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status); - - printf(" control 0x%08x\n", fec->eth->tfifo_cntrl); - printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr); - printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr); - printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm); - printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr); - printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr); - } -} - -static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec) -{ - uint16 phyAddr = CONFIG_PHY_ADDR; - uint16 phyStatus; - - if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr) - || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) { - - miiphy_read(devname, phyAddr, 0x1, &phyStatus); - printf("\nphyStatus: 0x%04x\n", phyStatus); - printf("ecntrl: 0x%08x\n", fec->eth->ecntrl); - printf("ievent: 0x%08x\n", fec->eth->ievent); - printf("x_status: 0x%08x\n", fec->eth->x_status); - printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status); - - printf(" control 0x%08x\n", fec->eth->rfifo_cntrl); - printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr); - printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr); - printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm); - printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr); - printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr); - } -} -#endif /* DEBUG */ - -/********************************************************************/ - -static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data, - int data_length) -{ - /* - * This routine transmits one frame. This routine only accepts - * 6-byte Ethernet addresses. - */ - mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; - volatile FEC_TBD *pTbd; - -#if (DEBUG & 0x20) - printf("tbd status: 0x%04x\n", fec->tbdBase[0].status); - tfifo_print(dev->name, fec); -#endif - - /* - * Clear Tx BD ring at first - */ - mpc5xxx_fec_tbd_scrub(fec); - - /* - * Check for valid length of data. - */ - if ((data_length > 1500) || (data_length <= 0)) { - return -1; - } - - /* - * Check the number of vacant TxBDs. - */ - if (fec->cleanTbdNum < 1) { -#if (DEBUG & 0x20) - printf("No available TxBDs ...\n"); -#endif - return -1; - } - - /* - * Get the first TxBD to send the mac header - */ - pTbd = &fec->tbdBase[fec->tbdIndex]; - pTbd->dataLength = data_length; - pTbd->dataPointer = (uint32)eth_data; - pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; - fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; - -#if (DEBUG & 0x100) - printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex); -#endif - - /* - * Kick the MII i/f - */ - if (fec->xcv_type != SEVENWIRE) { - uint16 phyStatus; - miiphy_read(dev->name, 0, 0x1, &phyStatus); - } - - /* - * Enable SmartDMA transmit task - */ - -#if (DEBUG & 0x20) - tfifo_print(dev->name, fec); -#endif - SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO); -#if (DEBUG & 0x20) - tfifo_print(dev->name, fec); -#endif -#if (DEBUG & 0x8) - printf( "+" ); -#endif - - fec->cleanTbdNum -= 1; - -#if (DEBUG & 0x129) && (DEBUG & 0x80000000) - printf ("smartDMA ethernet Tx task enabled\n"); -#endif - /* - * wait until frame is sent . - */ - while (pTbd->status & FEC_TBD_READY) { - udelay(10); -#if (DEBUG & 0x8) - printf ("TDB status = %04x\n", pTbd->status); -#endif - } - - return 0; -} - - -/********************************************************************/ -static int mpc5xxx_fec_recv(struct eth_device *dev) -{ - /* - * This command pulls one frame from the card - */ - mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; - volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex]; - unsigned long ievent; - int frame_length, len = 0; - NBUF *frame; - uchar buff[FEC_MAX_PKT_SIZE]; - -#if (DEBUG & 0x1) - printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex); -#endif -#if (DEBUG & 0x8) - printf( "-" ); -#endif - - /* - * Check if any critical events have happened - */ - ievent = fec->eth->ievent; - fec->eth->ievent = ievent; - if (ievent & 0x20060000) { - /* BABT, Rx/Tx FIFO errors */ - mpc5xxx_fec_halt(dev); - mpc5xxx_fec_init(dev, NULL); - return 0; - } - if (ievent & 0x80000000) { - /* Heartbeat error */ - fec->eth->x_cntrl |= 0x00000001; - } - if (ievent & 0x10000000) { - /* Graceful stop complete */ - if (fec->eth->x_cntrl & 0x00000001) { - mpc5xxx_fec_halt(dev); - fec->eth->x_cntrl &= ~0x00000001; - mpc5xxx_fec_init(dev, NULL); - } - } - - if (!(pRbd->status & FEC_RBD_EMPTY)) { - if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) && - ((pRbd->dataLength - 4) > 14)) { - - /* - * Get buffer address and size - */ - frame = (NBUF *)pRbd->dataPointer; - frame_length = pRbd->dataLength - 4; - -#if (DEBUG & 0x20) - { - int i; - printf("recv data hdr:"); - for (i = 0; i < 14; i++) - printf("%x ", *(frame->head + i)); - printf("\n"); - } -#endif - /* - * Fill the buffer and pass it to upper layers - */ - memcpy(buff, frame->head, 14); - memcpy(buff + 14, frame->data, frame_length); - NetReceive(buff, frame_length); - len = frame_length; - } - /* - * Reset buffer descriptor as empty - */ - mpc5xxx_fec_rbd_clean(fec, pRbd); - } - SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO); - return len; -} - - -/********************************************************************/ -int mpc5xxx_fec_initialize(bd_t * bis) -{ - mpc5xxx_fec_priv *fec; - struct eth_device *dev; - char *tmp, *end; - char env_enetaddr[6]; - int i; - - fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec)); - dev = (struct eth_device *)malloc(sizeof(*dev)); - memset(dev, 0, sizeof *dev); - - fec->eth = (ethernet_regs *)MPC5XXX_FEC; - fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; - fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); -#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \ - defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \ - defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \ - defined(CONFIG_TQM5200) || defined(CONFIG_O2DNT) -# ifndef CONFIG_FEC_10MBIT - fec->xcv_type = MII100; -# else - fec->xcv_type = MII10; -# endif -#elif defined(CONFIG_TOTAL5200) - fec->xcv_type = SEVENWIRE; -#else -#error fec->xcv_type not initialized. -#endif - - dev->priv = (void *)fec; - dev->iobase = MPC5XXX_FEC; - dev->init = mpc5xxx_fec_init; - dev->halt = mpc5xxx_fec_halt; - dev->send = mpc5xxx_fec_send; - dev->recv = mpc5xxx_fec_recv; - - sprintf(dev->name, "FEC ETHERNET"); - eth_register(dev); - -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) - miiphy_register (dev->name, - fec5xxx_miiphy_read, fec5xxx_miiphy_write); -#endif - - /* - * Try to set the mac address now. The fec mac address is - * a garbage after reset. When not using fec for booting - * the Linux fec driver will try to work with this garbage. - */ - tmp = getenv("ethaddr"); - if (tmp) { - for (i=0; i<6; i++) { - env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; - } - mpc5xxx_fec_set_hwaddr(fec, env_enetaddr); - } - - mpc5xxx_fec_init_phy(dev, bis); - - return 1; -} - -/* MII-interface related functions */ -/********************************************************************/ -int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal) -{ - ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; - uint32 reg; /* convenient holder for the PHY register */ - uint32 phy; /* convenient holder for the PHY */ - int timeout = 0xffff; - - /* - * reading from any PHY's register is done by properly - * programming the FEC's MII data register. - */ - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; - - eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg); - - /* - * wait for the related interrupt - */ - while ((timeout--) && (!(eth->ievent & 0x00800000))) ; - - if (timeout == 0) { -#if (DEBUG & 0x2) - printf ("Read MDIO failed...\n"); -#endif - return -1; - } - - /* - * clear mii interrupt bit - */ - eth->ievent = 0x00800000; - - /* - * it's now safe to read the PHY's register - */ - *retVal = (uint16) eth->mii_data; - - return 0; -} - -/********************************************************************/ -int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data) -{ - ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; - uint32 reg; /* convenient holder for the PHY register */ - uint32 phy; /* convenient holder for the PHY */ - int timeout = 0xffff; - - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; - - eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | - FEC_MII_DATA_TA | phy | reg | data); - - /* - * wait for the MII interrupt - */ - while ((timeout--) && (!(eth->ievent & 0x00800000))) ; - - if (timeout == 0) { -#if (DEBUG & 0x2) - printf ("Write MDIO failed...\n"); -#endif - return -1; - } - - /* - * clear MII interrupt bit - */ - eth->ievent = 0x00800000; - - return 0; -} - -#if (DEBUG & 0x40) -static uint32 local_crc32(char *string, unsigned int crc_value, int len) -{ - int i; - char c; - unsigned int crc, count; - - /* - * crc32 algorithm - */ - /* - * crc = 0xffffffff; * The initialized value should be 0xffffffff - */ - crc = crc_value; - - for (i = len; --i >= 0;) { - c = *string++; - for (count = 0; count < 8; count++) { - if ((c & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - c >>= 1; - } - } - - /* - * In big endian system, do byte swaping for crc value - */ - /**/ return crc; -} -#endif /* DEBUG */ - -#endif /* CONFIG_MPC5xxx_FEC */ diff --git a/cpu/mpc5xxx/fec.h b/cpu/mpc5xxx/fec.h deleted file mode 100644 index 81756a5..0000000 --- a/cpu/mpc5xxx/fec.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on mpc4200fec.h - * (C) Copyright Motorola, Inc., 2000 - * - * odin ethernet header file - */ - -#ifndef __MPC5XXX_FEC_H -#define __MPC5XXX_FEC_H - -#include -#include -#include "sdma.h" - -typedef unsigned long uint32; -typedef unsigned short uint16; -typedef unsigned char uint8; - -typedef struct ethernet_register_set { - -/* [10:2]addr = 00 */ - -/* Control and status Registers (offset 000-1FF) */ - - volatile uint32 fec_id; /* MBAR_ETH + 0x000 */ - volatile uint32 ievent; /* MBAR_ETH + 0x004 */ - volatile uint32 imask; /* MBAR_ETH + 0x008 */ - - volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ - volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ - volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ - volatile uint32 r_des_active_cl; /* MBAR_ETH + 0x018 */ - volatile uint32 x_des_active_cl; /* MBAR_ETH + 0x01C */ - volatile uint32 ivent_set; /* MBAR_ETH + 0x020 */ - volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ - - volatile uint32 RES1[6]; /* MBAR_ETH + 0x028-03C */ - volatile uint32 mii_data; /* MBAR_ETH + 0x040 */ - volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */ - volatile uint32 mii_status; /* MBAR_ETH + 0x048 */ - - volatile uint32 RES2[5]; /* MBAR_ETH + 0x04C-05C */ - volatile uint32 mib_data; /* MBAR_ETH + 0x060 */ - volatile uint32 mib_control; /* MBAR_ETH + 0x064 */ - - volatile uint32 RES3[6]; /* MBAR_ETH + 0x068-7C */ - volatile uint32 r_activate; /* MBAR_ETH + 0x080 */ - volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ - volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ - volatile uint32 r_data; /* MBAR_ETH + 0x08C */ - volatile uint32 ar_done; /* MBAR_ETH + 0x090 */ - volatile uint32 r_test; /* MBAR_ETH + 0x094 */ - volatile uint32 r_mib; /* MBAR_ETH + 0x098 */ - volatile uint32 r_da_low; /* MBAR_ETH + 0x09C */ - volatile uint32 r_da_high; /* MBAR_ETH + 0x0A0 */ - - volatile uint32 RES4[7]; /* MBAR_ETH + 0x0A4-0BC */ - volatile uint32 x_activate; /* MBAR_ETH + 0x0C0 */ - volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ - volatile uint32 backoff; /* MBAR_ETH + 0x0C8 */ - volatile uint32 x_data; /* MBAR_ETH + 0x0CC */ - volatile uint32 x_status; /* MBAR_ETH + 0x0D0 */ - volatile uint32 x_mib; /* MBAR_ETH + 0x0D4 */ - volatile uint32 x_test; /* MBAR_ETH + 0x0D8 */ - volatile uint32 fdxfc_da1; /* MBAR_ETH + 0x0DC */ - volatile uint32 fdxfc_da2; /* MBAR_ETH + 0x0E0 */ - volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ - volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ - volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */ - - volatile uint32 RES5[4]; /* MBAR_ETH + 0x0F0-0FC */ - volatile uint32 instr_reg; /* MBAR_ETH + 0x100 */ - volatile uint32 context_reg; /* MBAR_ETH + 0x104 */ - volatile uint32 test_cntrl; /* MBAR_ETH + 0x108 */ - volatile uint32 acc_reg; /* MBAR_ETH + 0x10C */ - volatile uint32 ones; /* MBAR_ETH + 0x110 */ - volatile uint32 zeros; /* MBAR_ETH + 0x114 */ - volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */ - volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */ - volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */ - volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */ - volatile uint32 random; /* MBAR_ETH + 0x128 */ - volatile uint32 rand1; /* MBAR_ETH + 0x12C */ - volatile uint32 tmp; /* MBAR_ETH + 0x130 */ - - volatile uint32 RES6[3]; /* MBAR_ETH + 0x134-13C */ - volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */ - volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */ - volatile uint32 fcntrl; /* MBAR_ETH + 0x148 */ - volatile uint32 r_bound; /* MBAR_ETH + 0x14C */ - volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */ - volatile uint32 r_count; /* MBAR_ETH + 0x154 */ - volatile uint32 r_lag; /* MBAR_ETH + 0x158 */ - volatile uint32 r_read; /* MBAR_ETH + 0x15C */ - volatile uint32 r_write; /* MBAR_ETH + 0x160 */ - volatile uint32 x_count; /* MBAR_ETH + 0x164 */ - volatile uint32 x_lag; /* MBAR_ETH + 0x168 */ - volatile uint32 x_retry; /* MBAR_ETH + 0x16C */ - volatile uint32 x_write; /* MBAR_ETH + 0x170 */ - volatile uint32 x_read; /* MBAR_ETH + 0x174 */ - - volatile uint32 RES7[2]; /* MBAR_ETH + 0x178-17C */ - volatile uint32 fm_cntrl; /* MBAR_ETH + 0x180 */ - volatile uint32 rfifo_data; /* MBAR_ETH + 0x184 */ - volatile uint32 rfifo_status; /* MBAR_ETH + 0x188 */ - volatile uint32 rfifo_cntrl; /* MBAR_ETH + 0x18C */ - volatile uint32 rfifo_lrf_ptr; /* MBAR_ETH + 0x190 */ - volatile uint32 rfifo_lwf_ptr; /* MBAR_ETH + 0x194 */ - volatile uint32 rfifo_alarm; /* MBAR_ETH + 0x198 */ - volatile uint32 rfifo_rdptr; /* MBAR_ETH + 0x19C */ - volatile uint32 rfifo_wrptr; /* MBAR_ETH + 0x1A0 */ - volatile uint32 tfifo_data; /* MBAR_ETH + 0x1A4 */ - volatile uint32 tfifo_status; /* MBAR_ETH + 0x1A8 */ - volatile uint32 tfifo_cntrl; /* MBAR_ETH + 0x1AC */ - volatile uint32 tfifo_lrf_ptr; /* MBAR_ETH + 0x1B0 */ - volatile uint32 tfifo_lwf_ptr; /* MBAR_ETH + 0x1B4 */ - volatile uint32 tfifo_alarm; /* MBAR_ETH + 0x1B8 */ - volatile uint32 tfifo_rdptr; /* MBAR_ETH + 0x1BC */ - volatile uint32 tfifo_wrptr; /* MBAR_ETH + 0x1C0 */ - - volatile uint32 reset_cntrl; /* MBAR_ETH + 0x1C4 */ - volatile uint32 xmit_fsm; /* MBAR_ETH + 0x1C8 */ - - volatile uint32 RES8[3]; /* MBAR_ETH + 0x1CC-1D4 */ - volatile uint32 rdes_data0; /* MBAR_ETH + 0x1D8 */ - volatile uint32 rdes_data1; /* MBAR_ETH + 0x1DC */ - volatile uint32 r_length; /* MBAR_ETH + 0x1E0 */ - volatile uint32 x_length; /* MBAR_ETH + 0x1E4 */ - volatile uint32 x_addr; /* MBAR_ETH + 0x1E8 */ - volatile uint32 cdes_data; /* MBAR_ETH + 0x1EC */ - volatile uint32 status; /* MBAR_ETH + 0x1F0 */ - volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */ - volatile uint32 des_cmnd; /* MBAR_ETH + 0x1F8 */ - volatile uint32 data; /* MBAR_ETH + 0x1FC */ - -/* MIB COUNTERS (Offset 200-2FF) */ - - volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */ - volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */ - volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ - volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ - volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */ - volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */ - volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */ - volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */ - volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */ - volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */ - volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */ - volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */ - volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */ - volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */ - volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ - volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ - volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ - volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */ - volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */ - volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ - volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */ - volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */ - volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */ - volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */ - volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */ - volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */ - volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */ - volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */ - volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */ - volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ - - volatile uint32 RES9[2]; /* MBAR_ETH + 0x278-27C */ - volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */ - volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */ - volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ - volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ - volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */ - volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */ - volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */ - volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */ - volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */ - - volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ - - volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */ - volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ - volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ - volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ - volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ - volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ - volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ - volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */ - volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */ - volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ - volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */ - volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */ - volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */ - volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */ - volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ - - volatile uint32 RES10[6]; /* MBAR_ETH + 0x2E4-2FC */ - - volatile uint32 RES11[64]; /* MBAR_ETH + 0x300-3FF */ -} ethernet_regs; - -/* Receive & Transmit Buffer Descriptor definitions */ -typedef struct BufferDescriptor { - uint16 status; - uint16 dataLength; - uint32 dataPointer; -} FEC_RBD; -typedef struct { - uint16 status; - uint16 dataLength; - uint32 dataPointer; -} FEC_TBD; - -/* private structure */ -typedef enum { - SEVENWIRE, /* 7-wire */ - MII10, /* MII 10Mbps */ - MII100 /* MII 100Mbps */ -} xceiver_type; - -typedef struct { - ethernet_regs *eth; - xceiver_type xcv_type; /* transceiver type */ - FEC_RBD *rbdBase; /* RBD ring */ - FEC_TBD *tbdBase; /* TBD ring */ - uint16 rbdIndex; /* next receive BD to read */ - uint16 tbdIndex; /* next transmit BD to send */ - uint16 usedTbdIndex; /* next transmit BD to clean */ - uint16 cleanTbdNum; /* the number of available transmit BDs */ -} mpc5xxx_fec_priv; - -/* Ethernet parameter area */ -#define FEC_TBD_BASE (FEC_PARAM_BASE + 0x00) -#define FEC_TBD_NEXT (FEC_PARAM_BASE + 0x04) -#define FEC_RBD_BASE (FEC_PARAM_BASE + 0x08) -#define FEC_RBD_NEXT (FEC_PARAM_BASE + 0x0c) - -/* BD Numer definitions */ -#define FEC_TBD_NUM 48 /* The user can adjust this value */ -#define FEC_RBD_NUM 32 /* The user can adjust this value */ - -/* packet size limit */ -#define FEC_MAX_PKT_SIZE 1536 - -/* RBD bits definitions */ -#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ -#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ -#define FEC_RBD_INT 0x1000 /* Interrupt */ -#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ -#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ -#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ -#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ -#define FEC_RBD_LG 0x0020 /* Frame length violation */ -#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ -#define FEC_RBD_SH 0x0008 /* Short frame */ -#define FEC_RBD_CR 0x0004 /* CRC error */ -#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ -#define FEC_RBD_TR 0x0001 /* Frame is truncated */ -#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ - FEC_RBD_OV | FEC_RBD_TR) - -/* TBD bits definitions */ -#define FEC_TBD_READY 0x8000 /* Buffer is ready */ -#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ -#define FEC_TBD_INT 0x1000 /* Interrupt */ -#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ -#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ -#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ - -/* MII-related definitios */ -#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ -#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ -#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ -#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ -#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ -#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ -#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ - -#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ -#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ - -#endif /* __MPC5XXX_FEC_H */ diff --git a/cpu/mpc5xxx/firmware_sc_task.impl.S b/cpu/mpc5xxx/firmware_sc_task.impl.S deleted file mode 100644 index b668ee5..0000000 --- a/cpu/mpc5xxx/firmware_sc_task.impl.S +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright (C) 2001, Software Center, Motorola China. - * - * This file contains microcode for the FEC controller of the MGT5100 CPU. - */ - -#include - -#if defined(CONFIG_MGT5100) - -/* sas/sccg, gas target */ -.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ -.section smartdmaTaskTable,"aw",@progbits /* Task tables */ -.globl taskTable -taskTable: -.globl scEthernetRecv_Entry -scEthernetRecv_Entry: /* Task 0 */ -.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ -.long scEthernetRecv_TDT - taskTable + 0x000000a4 -.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ -.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long 0xf0000000 -.globl scEthernetXmit_Entry -scEthernetXmit_Entry: /* Task 1 */ -.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ -.long scEthernetXmit_TDT - taskTable + 0x000000d0 -.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ -.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long 0xf0000000 - - -.globl scEthernetRecv_TDT -scEthernetRecv_TDT: /* Task 0 Descriptor Table */ -.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ -.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */ -.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x010c504c /* 0020: DRD2B1: var4 = EU1(); EU1(var1,var12) */ -.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ -.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018c504e /* 0030: DRD2B1: var6 = EU1(); EU1(var1,var14) */ -.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x020c504f /* 0038: DRD2B1: var8 = EU1(); EU1(var1,var15) */ -.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */ -.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */ -.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */ -.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */ -.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */ -.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */ -.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */ -.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ -.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */ -.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ -.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080c504c /* 00A0: DRD2B1: idx0 = EU1(); EU1(var1,var12) */ -.long 0x000001f8 /* 00A4(:0): NOP */ - - -.globl scEthernetXmit_TDT -scEthernetXmit_TDT: /* Task 1 Descriptor Table */ -.long 0x80014800 /* 0000: LCDEXT: idx0 = 0xf0004800; ; */ -.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x024c504d /* 0020: DRD2B1: var9 = EU1(); EU1(var1,var13) */ -.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ -.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */ -.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ -.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x010c504e /* 0034: DRD2B1: var4 = EU1(); EU1(var1,var14) */ -.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x014c504f /* 003C: DRD2B1: var5 = EU1(); EU1(var1,var15) */ -.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x028c5050 /* 0044: DRD2B1: var10 = EU1(); EU1(var1,var16) */ -.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018c5051 /* 004C: DRD2B1: var6 = EU1(); EU1(var1,var17) */ -.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x01cc50a1 /* 0058: DRD2B1: var7 = EU1(); EU1(var2,idx1) */ -.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ -.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ -.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */ -.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */ -.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ -.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ -.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */ -.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x60000100 /* 0088: DRD2A: EU0=0 EU1=1 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x0c4c5c4d /* 008C: DRD2B1: *idx1 = EU1(); EU1(*idx1,var13) */ -.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ -.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ -.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */ -.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ -.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ -.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080c504d /* 00CC: DRD2B1: idx0 = EU1(); EU1(var1,var13) */ -.long 0x000001f8 /* 00D0(:0): NOP */ - -.align 8 - -.globl scEthernetRecv_VarTab -scEthernetRecv_VarTab: /* Task 0 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0xf0004800 /* var[9] */ -.long 0x00000008 /* var[10] */ -.long 0x0000000c /* var[11] */ -.long 0x80000000 /* var[12] */ -.long 0x00000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x20000000 /* var[15] */ -.long 0x000005e4 /* var[16] */ -.long 0x0000000e /* var[17] */ -.long 0x000005e0 /* var[18] */ -.long 0x00000004 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x20000001 /* inc[2] */ -.long 0x80000000 /* inc[3] */ -.long 0x40000000 /* inc[4] */ -.long 0x00000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetXmit_VarTab -scEthernetXmit_VarTab: /* Task 1 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0x00000000 /* var[9] */ -.long 0x00000000 /* var[10] */ -.long 0xf0004800 /* var[11] */ -.long 0x00000000 /* var[12] */ -.long 0x80000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x08000000 /* var[15] */ -.long 0x20000000 /* var[16] */ -.long 0x0000ffff /* var[17] */ -.long 0xffffffff /* var[18] */ -.long 0x00000008 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x40000000 /* inc[2] */ -.long 0x4000ffff /* inc[3] */ -.long 0xe0000001 /* inc[4] */ -.long 0x80000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetRecv_FDT -scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x05800000 /* and(), EU# 1 */ -.long 0x05400000 /* andn(), EU# 1 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - -.align 8 - -.globl scEthernetXmit_FDT -scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x05800000 /* and(), EU# 1 */ -.long 0x05400000 /* andn(), EU# 1 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - - -.align 8 -.globl scEthernetRecv_CSave -scEthernetRecv_CSave: /* Task 0 context save space */ -.space 256, 0x0 - - -.align 8 -.globl scEthernetXmit_CSave -scEthernetXmit_CSave: /* Task 1 context save space */ -.space 256, 0x0 - -#endif /* CONFIG_MGT5100 */ diff --git a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S deleted file mode 100644 index 1d83fe2..0000000 --- a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright (C) 2001, Software Center, Motorola China. - * - * This file contains microcode for the FEC controller of the MPC5200 CPU. - */ - -#include - -#if defined(CONFIG_MPC5200) - -/* sas/sccg, gas target */ -.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ -.section smartdmaTaskTable,"aw",@progbits /* Task tables */ -.align 9 -.globl taskTable -taskTable: -.globl scEthernetRecv_Entry -scEthernetRecv_Entry: /* Task 0 */ -.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ -.long scEthernetRecv_TDT - taskTable + 0x000000a4 -.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ -.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long 0xf0000000 -.globl scEthernetXmit_Entry -scEthernetXmit_Entry: /* Task 1 */ -.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ -.long scEthernetXmit_TDT - taskTable + 0x000000d0 -.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ -.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long 0xf0000000 - - -.globl scEthernetRecv_TDT -scEthernetRecv_TDT: /* Task 0 Descriptor Table */ -.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ -.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */ -.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x010cf04c /* 0020: DRD2B1: var4 = EU3(); EU3(var1,var12) */ -.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ -.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018cf04e /* 0030: DRD2B1: var6 = EU3(); EU3(var1,var14) */ -.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x020cf04f /* 0038: DRD2B1: var8 = EU3(); EU3(var1,var15) */ -.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */ -.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */ -.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */ -.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */ -.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */ -.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */ -.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */ -.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */ -.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */ -.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ -.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */ -.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ -.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080cf04c /* 00A0: DRD2B1: idx0 = EU3(); EU3(var1,var12) */ -.long 0x000001f8 /* 00A4(:0): NOP */ - - -.globl scEthernetXmit_TDT -scEthernetXmit_TDT: /* Task 1 Descriptor Table */ -.long 0x80024800 /* 0000: LCDEXT: idx0 = 0xf0008800; ; */ -.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x024cf04d /* 0020: DRD2B1: var9 = EU3(); EU3(var1,var13) */ -.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ -.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */ -.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ -.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x010cf04e /* 0034: DRD2B1: var4 = EU3(); EU3(var1,var14) */ -.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x014cf04f /* 003C: DRD2B1: var5 = EU3(); EU3(var1,var15) */ -.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x028cf050 /* 0044: DRD2B1: var10 = EU3(); EU3(var1,var16) */ -.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018cf051 /* 004C: DRD2B1: var6 = EU3(); EU3(var1,var17) */ -.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x01ccf0a1 /* 0058: DRD2B1: var7 = EU3(); EU3(var2,idx1) */ -.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ -.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ -.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ -.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */ -.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */ -.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */ -.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ -.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ -.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */ -.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x60000001 /* 0088: DRD2A: EU0=0 EU1=0 EU2=0 EU3=1 EXT init=0 WS=0 RS=0 */ -.long 0x0c4cfc4d /* 008C: DRD2B1: *idx1 = EU3(); EU3(*idx1,var13) */ -.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ -.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ -.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */ -.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ -.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ -.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080cf04d /* 00CC: DRD2B1: idx0 = EU3(); EU3(var1,var13) */ -.long 0x000001f8 /* 00D0(:0): NOP */ - -.align 8 - -.globl scEthernetRecv_VarTab -scEthernetRecv_VarTab: /* Task 0 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0xf0008800 /* var[9] */ -.long 0x00000008 /* var[10] */ -.long 0x0000000c /* var[11] */ -.long 0x80000000 /* var[12] */ -.long 0x00000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x20000000 /* var[15] */ -.long 0x000005e4 /* var[16] */ -.long 0x0000000e /* var[17] */ -.long 0x000005e0 /* var[18] */ -.long 0x00000004 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x20000001 /* inc[2] */ -.long 0x80000000 /* inc[3] */ -.long 0x40000000 /* inc[4] */ -.long 0x00000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetXmit_VarTab -scEthernetXmit_VarTab: /* Task 1 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0x00000000 /* var[9] */ -.long 0x00000000 /* var[10] */ -.long 0xf0008800 /* var[11] */ -.long 0x00000000 /* var[12] */ -.long 0x80000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x08000000 /* var[15] */ -.long 0x20000000 /* var[16] */ -.long 0x0000ffff /* var[17] */ -.long 0xffffffff /* var[18] */ -.long 0x00000008 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x40000000 /* inc[2] */ -.long 0x4000ffff /* inc[3] */ -.long 0xe0000001 /* inc[4] */ -.long 0x80000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetRecv_FDT -scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x21800000 /* and(), EU# 3 */ -.long 0x21400000 /* andn(), EU# 3 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - -.align 8 - -.globl scEthernetXmit_FDT -scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x21800000 /* and(), EU# 3 */ -.long 0x21400000 /* andn(), EU# 3 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - - -.globl scEthernetRecv_CSave -scEthernetRecv_CSave: /* Task 0 context save space */ -.space 128, 0x0 - - -.globl scEthernetXmit_CSave -scEthernetXmit_CSave: /* Task 1 context save space */ -.space 128, 0x0 - -#endif /* CONFIG_MPC5200 */ diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c deleted file mode 100644 index 044db46..0000000 --- a/cpu/mpc5xxx/i2c.c +++ /dev/null @@ -1,398 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifdef CONFIG_HARD_I2C - -#include -#include - -#if (CFG_I2C_MODULE == 2) -#define I2C_BASE MPC5XXX_I2C2 -#elif (CFG_I2C_MODULE == 1) -#define I2C_BASE MPC5XXX_I2C1 -#else -#error CFG_I2C_MODULE is not properly configured -#endif - -#define I2C_TIMEOUT 100 -#define I2C_RETRIES 3 - -struct mpc5xxx_i2c_tap { - int scl2tap; - int tap2tap; -}; - -static int mpc_reg_in (volatile u32 *reg); -static void mpc_reg_out (volatile u32 *reg, int val, int mask); -static int wait_for_bb (void); -static int wait_for_pin (int *status); -static int do_address (uchar chip, char rdwr_flag); -static int send_bytes (uchar chip, char *buf, int len); -static int receive_bytes (uchar chip, char *buf, int len); -static int mpc_get_fdr (int); - -static int mpc_reg_in(volatile u32 *reg) -{ - int ret = *reg >> 24; - __asm__ __volatile__ ("eieio"); - return ret; -} - -static void mpc_reg_out(volatile u32 *reg, int val, int mask) -{ - int tmp; - - if (!mask) { - *reg = val << 24; - } else { - tmp = mpc_reg_in(reg); - *reg = ((tmp & ~mask) | (val & mask)) << 24; - } - __asm__ __volatile__ ("eieio"); - - return; -} - -static int wait_for_bb(void) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int timeout = I2C_TIMEOUT; - int status; - - status = mpc_reg_in(®s->msr); - - while (timeout-- && (status & I2C_BB)) { -#if 1 - volatile int temp; - mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); - temp = mpc_reg_in(®s->mdr); - mpc_reg_out(®s->mcr, 0, I2C_STA); - mpc_reg_out(®s->mcr, 0, 0); - mpc_reg_out(®s->mcr, I2C_EN, 0); -#endif - udelay(1000); - status = mpc_reg_in(®s->msr); - } - - return (status & I2C_BB); -} - -static int wait_for_pin(int *status) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int timeout = I2C_TIMEOUT; - - *status = mpc_reg_in(®s->msr); - - while (timeout-- && !(*status & I2C_IF)) { - udelay(1000); - *status = mpc_reg_in(®s->msr); - } - - if (!(*status & I2C_IF)) { - return -1; - } - - mpc_reg_out(®s->msr, 0, I2C_IF); - - return 0; -} - -static int do_address(uchar chip, char rdwr_flag) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int status; - - chip <<= 1; - - if (rdwr_flag) { - chip |= 1; - } - - mpc_reg_out(®s->mcr, I2C_TX, I2C_TX); - mpc_reg_out(®s->mdr, chip, 0); - - if (wait_for_pin(&status)) { - return -2; - } - - if (status & I2C_RXAK) { - return -3; - } - - return 0; -} - -static int send_bytes(uchar chip, char *buf, int len) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int wrcount; - int status; - - for (wrcount = 0; wrcount < len; ++wrcount) { - - mpc_reg_out(®s->mdr, buf[wrcount], 0); - - if (wait_for_pin(&status)) { - break; - } - - if (status & I2C_RXAK) { - break; - } - - } - - return !(wrcount == len); -} - -static int receive_bytes(uchar chip, char *buf, int len) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int dummy = 1; - int rdcount = 0; - int status; - int i; - - mpc_reg_out(®s->mcr, 0, I2C_TX); - - for (i = 0; i < len; ++i) { - buf[rdcount] = mpc_reg_in(®s->mdr); - - if (dummy) { - dummy = 0; - } else { - rdcount++; - } - - - if (wait_for_pin(&status)) { - return -4; - } - } - - mpc_reg_out(®s->mcr, I2C_TXAK, I2C_TXAK); - buf[rdcount++] = mpc_reg_in(®s->mdr); - - if (wait_for_pin(&status)) { - return -5; - } - - mpc_reg_out(®s->mcr, 0, I2C_TXAK); - - return 0; -} - -/**************** I2C API ****************/ - -void i2c_init(int speed, int saddr) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - - mpc_reg_out(®s->mcr, 0, 0); - mpc_reg_out(®s->madr, saddr << 1, 0); - - /* Set clock - */ - mpc_reg_out(®s->mfdr, mpc_get_fdr(speed), 0); - - /* Enable module - */ - mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK); - mpc_reg_out(®s->msr, 0, I2C_IF); - - return; -} - -static int mpc_get_fdr(int speed) -{ - DECLARE_GLOBAL_DATA_PTR; - static int fdr = -1; - - if (fdr == -1) { - ulong best_speed = 0; - ulong divider; - ulong ipb, scl; - ulong bestmatch = 0xffffffffUL; - int best_i = 0, best_j = 0, i, j; - int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8}; - struct mpc5xxx_i2c_tap scltap[] = { - {4, 1}, - {4, 2}, - {6, 4}, - {6, 8}, - {14, 16}, - {30, 32}, - {62, 64}, - {126, 128} - }; - - ipb = gd->ipb_clk; - for (i = 7; i >= 0; i--) { - for (j = 7; j >= 0; j--) { - scl = 2 * (scltap[j].scl2tap + - (SCL_Tap[i] - 1) * scltap[j].tap2tap + 2); - if (ipb <= speed*scl) { - if ((speed*scl - ipb) < bestmatch) { - bestmatch = speed*scl - ipb; - best_i = i; - best_j = j; - best_speed = ipb/scl; - } - } - } - } - divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2); - if (gd->flags & GD_FLG_RELOC) { - fdr = divider; - } else { - printf("%ld kHz, ", best_speed / 1000); - return divider; - } - } - - return fdr; -} - -int i2c_probe(uchar chip) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int i; - - for (i = 0; i < I2C_RETRIES; i++) { - mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); - - if (! do_address(chip, 0)) { - mpc_reg_out(®s->mcr, 0, I2C_STA); - udelay(500); - break; - } - - mpc_reg_out(®s->mcr, 0, I2C_STA); - udelay(500); - } - - return (i == I2C_RETRIES); -} - -int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - char xaddr[4]; - struct mpc5xxx_i2c * regs = (struct mpc5xxx_i2c *)I2C_BASE; - int ret = -1; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - - if (wait_for_bb()) { - printf("i2c_read: bus is busy\n"); - goto Done; - } - - mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); - if (do_address(chip, 0)) { - printf("i2c_read: failed to address chip\n"); - goto Done; - } - - if (send_bytes(chip, &xaddr[4-alen], alen)) { - printf("i2c_read: send_bytes failed\n"); - goto Done; - } - - mpc_reg_out(®s->mcr, I2C_RSTA, I2C_RSTA); - if (do_address(chip, 1)) { - printf("i2c_read: failed to address chip\n"); - goto Done; - } - - if (receive_bytes(chip, (char *)buf, len)) { - printf("i2c_read: receive_bytes failed\n"); - goto Done; - } - - ret = 0; -Done: - mpc_reg_out(®s->mcr, 0, I2C_STA); - return ret; -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - char xaddr[4]; - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int ret = -1; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - - if (wait_for_bb()) { - printf("i2c_write: bus is busy\n"); - goto Done; - } - - mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); - if (do_address(chip, 0)) { - printf("i2c_write: failed to address chip\n"); - goto Done; - } - - if (send_bytes(chip, &xaddr[4-alen], alen)) { - printf("i2c_write: send_bytes failed\n"); - goto Done; - } - - if (send_bytes(chip, (char *)buf, len)) { - printf("i2c_write: send_bytes failed\n"); - goto Done; - } - - ret = 0; -Done: - mpc_reg_out(®s->mcr, 0, I2C_STA); - return ret; -} - -uchar i2c_reg_read(uchar chip, uchar reg) -{ - uchar buf; - - i2c_read(chip, reg, 1, &buf, 1); - - return buf; -} - -void i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - i2c_write(chip, reg, 1, &val, 1); - - return; -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c deleted file mode 100644 index 1af794c..0000000 --- a/cpu/mpc5xxx/ide.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2004 - * Pierre AUBERT, Staubli Faverges, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Init is derived from Linux code. - */ -#include - -#ifdef CFG_CMD_IDE -#include - -#define CALC_TIMING(t) (t + period - 1) / period - -#ifdef CONFIG_IDE_RESET -extern void init_ide_reset (void); -#endif - -int ide_preinit (void) -{ - DECLARE_GLOBAL_DATA_PTR; - long period, t0, t1, t2_8, t2_16, t4, ta; - vu_long reg; - struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA; - - reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG; -#if defined(CONFIG_TOTAL5200) - /* ATA cs0/1 on i2c2 clk/io */ - reg = (reg & ~0x03000000ul) | 0x02000000ul; -#else - /* ATA cs0/1 on Local Plus cs4/5 */ - reg = (reg & ~0x03000000ul) | 0x01000000ul; -#endif /* CONFIG_TOTAL5200 */ - *(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg; - - /* All sample codes do that... */ - *(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0; - - /* Configure and reset host */ - *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY | - MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; - udelay (10); - *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY; - - /* Disable prefetch on Commbus */ - psdma->PtdCntrl |= 1; - - /* Init timings : we use PIO mode 0 timings */ - period = 1000000000 / gd->ipb_clk; /* period in ns */ - - t0 = CALC_TIMING (600); - t2_8 = CALC_TIMING (290); - t2_16 = CALC_TIMING (165); - reg = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8); - *(vu_long *) MPC5XXX_ATA_PIO1 = reg; - - t4 = CALC_TIMING (30); - t1 = CALC_TIMING (70); - ta = CALC_TIMING (35); - reg = (t4 << 24) | (t1 << 16) | (ta << 8); - - *(vu_long *) MPC5XXX_ATA_PIO2 = reg; - -#ifdef CONFIG_IDE_RESET - init_ide_reset (); -#endif /* CONFIG_IDE_RESET */ - - return (0); -} -#endif /* CFG_CMD_IDE */ diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c deleted file mode 100644 index 7bacecd..0000000 --- a/cpu/mpc5xxx/interrupts.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright -2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * interrupts.c - just enough support for the decrementer/timer - */ - -#include -#include -#include - -int interrupt_init_cpu (ulong *decrementer_count) -{ - *decrementer_count = get_tbclk() / CFG_HZ; - - return (0); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void -external_interrupt(struct pt_regs *regs) -{ - puts("external_interrupt (oops!)\n"); -} - -void -timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} - -/****************************************************************************/ - -/* - * Install and free a interrupt handler. - */ - -void -irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) -{ - -} - -void -irq_free_handler(int vec) -{ - -} - -/****************************************************************************/ - -void -do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - puts("IRQ related functions are unimplemented currently.\n"); -} diff --git a/cpu/mpc5xxx/io.S b/cpu/mpc5xxx/io.S deleted file mode 100644 index 2178a26..0000000 --- a/cpu/mpc5xxx/io.S +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH - * Andreas Heppel - * Copyright (C) 2003 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in16 -in16: - lhz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in16r -in16r: - lhbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0(3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in32r -in32r: - lwbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16 -out16: - sth r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16r -out16r: - sthbrx r4,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32r -out32r: - stwbrx r4,0,r3 - sync - blr diff --git a/cpu/mpc5xxx/loadtask.c b/cpu/mpc5xxx/loadtask.c deleted file mode 100644 index 47e7b59..0000000 --- a/cpu/mpc5xxx/loadtask.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on code - * (C) Copyright Motorola, Inc., 2000 - */ - -#include -#include - -/* BestComm/SmartComm microcode */ -extern int taskTable; - -void loadtask(int basetask, int tasks) -{ - int *sram = (int *)MPC5XXX_SRAM; - int *task_org = &taskTable; - unsigned int start, offset, end; - int i; - -#ifdef DEBUG - printf("basetask = %d, tasks = %d\n", basetask, tasks); - printf("task_org = 0x%08x\n", (unsigned int)task_org); -#endif - - /* setup TaskBAR register */ - *(vu_long *)MPC5XXX_SDMA = MPC5XXX_SRAM; - - /* relocate task table entries */ - offset = (unsigned int)sram; - for (i = basetask; i < basetask + tasks; i++) { - sram[i * 8 + 0] = task_org[i * 8 + 0] + offset; - sram[i * 8 + 1] = task_org[i * 8 + 1] + offset; - sram[i * 8 + 2] = task_org[i * 8 + 2] + offset; - sram[i * 8 + 3] = task_org[i * 8 + 3] + offset; - sram[i * 8 + 4] = task_org[i * 8 + 4]; - sram[i * 8 + 5] = task_org[i * 8 + 5]; - sram[i * 8 + 6] = task_org[i * 8 + 6] + offset; - sram[i * 8 + 7] = task_org[i * 8 + 7]; - } - - /* relocate task descriptors */ - start = (sram[basetask * 8] - (unsigned int)sram); - end = (sram[(basetask + tasks - 1) * 8 + 1] - (unsigned int)sram); - -#ifdef DEBUG - printf ("TDT start = 0x%08x, end = 0x%08x\n", start, end); -#endif - - start /= 4; - end /= 4; - for (i = start; i <= end; i++) { - sram[i] = task_org[i]; - } - - /* relocate variables */ - start = (sram[basetask * 8 + 2] - (unsigned int)sram); - end = (sram[(basetask + tasks - 1) * 8 + 2] + 256 - (unsigned int)sram); - start /= 4; - end /= 4; - for (i = start; i < end; i++) { - sram[i] = task_org[i]; - } - - /* relocate function decriptors */ - start = ((sram[basetask * 8 + 3] & 0xfffffffc) - (unsigned int)sram); - end = ((sram[(basetask + tasks - 1) * 8 + 3] & 0xfffffffc) + 256 - (unsigned int)sram); - start /= 4; - end /= 4; - for (i = start; i < end; i++) { - sram[i] = task_org[i]; - } - - asm volatile ("sync"); -} diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c deleted file mode 100644 index 1d90345..0000000 --- a/cpu/mpc5xxx/pci_mpc5200.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200) - -#include -#include -#include -#include - -/* System RAM mapped over PCI */ -#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE -#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024) - -/* PCIIWCR bit fields */ -#define IWCR_MEM (0 << 3) -#define IWCR_IO (1 << 3) -#define IWCR_READ (0 << 1) -#define IWCR_READLINE (1 << 1) -#define IWCR_READMULT (2 << 1) -#define IWCR_EN (1 << 0) - -static int mpc5200_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32* value) -{ - *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; - eieio(); - udelay(10); -#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200) - if (dev & 0x00ff0000) { - u32 val; - val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2)); - udelay(10); - val = val << 16; - val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0)); - *value = val; - } else { - *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); - } - udelay(10); -#else - *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS); -#endif - eieio(); - *(volatile u32 *)MPC5XXX_PCI_CAR = 0; - udelay(10); - return 0; -} - -static int mpc5200_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset; - eieio(); - udelay(10); - out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value); - eieio(); - *(volatile u32 *)MPC5XXX_PCI_CAR = 0; - udelay(10); - return 0; -} - -void pci_mpc5xxx_init (struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEMORY_BUS, - CONFIG_PCI_MEMORY_PHYS, - CONFIG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose(hose); - - /* GPIO Multiplexing - enable PCI */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15); - - /* Set host bridge as pci master and enable memory decoding */ - *(vu_long *)MPC5XXX_PCI_CMD |= - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - - /* Set maximum latency timer */ - *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800); - - /* Set cache line size */ - *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) | - (CFG_CACHELINE_SIZE / 4); - - /* Map MBAR to PCI space */ - *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR; - *(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1; - - /* Map RAM to PCI space */ - *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3); - *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1; - - /* Enable snooping for RAM */ - *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15); - *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d; - - /* Park XLB on PCI */ - *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5)); - *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5); - - /* Disable interrupts from PCI controller */ - *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12); - *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24); - - /* Set PCI retry counter to 0 = infinite retry. */ - /* The default of 255 is too short for slow devices. */ - *(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00; - - /* Disable initiator windows */ - *(vu_long *)MPC5XXX_PCI_IWCR = 0; - - /* Map PCI memory to physical space */ - *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS | - (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) | - (CONFIG_PCI_MEM_BUS >> 16); - *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24; - - /* Map PCI I/O to physical space */ - *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS | - (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) | - (CONFIG_PCI_IO_BUS >> 16); - *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16; - - /* Reset the PCI bus */ - *(vu_long *)MPC5XXX_PCI_GSCR |= 1; - udelay(1000); - *(vu_long *)MPC5XXX_PCI_GSCR &= ~1; - udelay(1000); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - mpc5200_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - mpc5200_write_config_dword); - - udelay(1000); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - - hose->last_busno = pci_hose_scan(hose); -} -#endif /* CONFIG_PCI && CONFIG_MPC5200 */ diff --git a/cpu/mpc5xxx/sdma.h b/cpu/mpc5xxx/sdma.h deleted file mode 100644 index 8b740e4..0000000 --- a/cpu/mpc5xxx/sdma.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on code - * (C) Copyright Motorola, Inc., 2000 - * - * odin smartdma header file - */ - -#ifndef __MPC5XXX_SDMA_H -#define __MPC5XXX_SDMA_H - -#include -#include - -/* Task number assignment */ -#define FEC_RECV_TASK_NO 0 -#define FEC_XMIT_TASK_NO 1 - -/*---------------------------------------------------------------------*/ - -/* Stuff for Ethernet Tx/Rx tasks */ - -/*---------------------------------------------------------------------*/ - -/* Layout of Ethernet controller Parameter SRAM area: ----------------------------------------------------------------- -0x00: TBD_BASE, base address of TX BD ring -0x04: TBD_NEXT, address of next TX BD to be processed -0x08: RBD_BASE, base address of RX BD ring -0x0C: RBD_NEXT, address of next RX BD to be processed ---------------------------------------------------------------- -ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH). -*/ - -/* base address of SRAM area to store parameters used by Ethernet tasks */ -#define FEC_PARAM_BASE (MPC5XXX_SRAM + 0x0800) - -/* base address of SRAM area for buffer descriptors */ -#define FEC_BD_BASE (MPC5XXX_SRAM + 0x0820) - -/*---------------------------------------------------------------------*/ - -/* common shortcuts used by driver C code */ - -/*---------------------------------------------------------------------*/ - -/* Disable SmartDMA task */ -#define SDMA_TASK_DISABLE(tasknum) \ -{ \ - volatile ushort *tcr = (ushort *)(MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ - *tcr = (*tcr) & (~0x8000); \ -} - -/* Enable SmartDMA task */ -#define SDMA_TASK_ENABLE(tasknum) \ -{ \ - volatile ushort *tcr = (ushort *) (MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ - *tcr = (*tcr) | 0x8000; \ -} - -/* Enable interrupt */ -#define SDMA_INT_ENABLE(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntMask &= ~(1 << tasknum); \ -} - -/* Disable interrupt */ -#define SDMA_INT_DISABLE(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntMask |= (1 << tasknum); \ -} - - -/* Clear interrupt pending bits */ -#define SDMA_CLEAR_IEVENT(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntPend = (1 << tasknum); \ -} - -/* get interupt pending bit of a task */ -#define SDMA_GET_PENDINGBIT(tasknum) \ - ((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum))) - -/* get interupt mask bit of a task */ -#define SDMA_GET_MASKBIT(tasknum) \ - ((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum))) - -#endif /* __MPC5XXX_SDMA_H */ diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c deleted file mode 100644 index 91e1def..0000000 --- a/cpu/mpc5xxx/serial.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * (C) Copyright 2000 - 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with - * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the - * Linux/PPC sources (m8260_tty.c had no copyright info in it). - */ - -/* - * Minimal serial functions needed to use one of the PSC ports - * as serial console interface. - */ - -#include -#include - -#if defined(CONFIG_PSC_CONSOLE) - -#if CONFIG_PSC_CONSOLE == 1 -#define PSC_BASE MPC5XXX_PSC1 -#elif CONFIG_PSC_CONSOLE == 2 -#define PSC_BASE MPC5XXX_PSC2 -#elif CONFIG_PSC_CONSOLE == 3 -#define PSC_BASE MPC5XXX_PSC3 -#elif defined(CONFIG_MGT5100) -#error CONFIG_PSC_CONSOLE must be in 1, 2 or 3 -#elif CONFIG_PSC_CONSOLE == 4 -#define PSC_BASE MPC5XXX_PSC4 -#elif CONFIG_PSC_CONSOLE == 5 -#define PSC_BASE MPC5XXX_PSC5 -#elif CONFIG_PSC_CONSOLE == 6 -#define PSC_BASE MPC5XXX_PSC6 -#else -#error CONFIG_PSC_CONSOLE must be in 1 ... 6 -#endif - -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; - unsigned long baseclk; - int div; - - /* reset PSC */ - psc->command = PSC_SEL_MODE_REG_1; - - /* select clock sources */ -#if defined(CONFIG_MGT5100) - psc->psc_clock_select = 0xdd00; - baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32; -#elif defined(CONFIG_MPC5200) - psc->psc_clock_select = 0; - baseclk = (gd->ipb_clk + 16) / 32; -#endif - - /* switch to UART mode */ - psc->sicr = 0; - - /* configure parity, bit length and so on */ -#if defined(CONFIG_MGT5100) - psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#elif defined(CONFIG_MPC5200) - psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; -#endif - psc->mode = PSC_MODE_ONE_STOP; - - /* set up UART divisor */ - div = (baseclk + (gd->baudrate/2)) / gd->baudrate; - psc->ctur = (div >> 8) & 0xff; - psc->ctlr = div & 0xff; - - /* disable all interrupts */ - psc->psc_imr = 0; - - /* reset and enable Rx/Tx */ - psc->command = PSC_RST_RX; - psc->command = PSC_RST_TX; - psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; - - return (0); -} - -void -serial_putc(const char c) -{ - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; - - if (c == '\n') - serial_putc('\r'); - - /* Wait for last character to go. */ - while (!(psc->psc_status & PSC_SR_TXEMP)) - ; - - psc->psc_buffer_8 = c; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int -serial_getc(void) -{ - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; - - /* Wait for a character to arrive. */ - while (!(psc->psc_status & PSC_SR_RXRDY)) - ; - - return psc->psc_buffer_8; -} - -int -serial_tstc(void) -{ - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; - - return (psc->psc_status & PSC_SR_RXRDY); -} - -void -serial_setbrg(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; - unsigned long baseclk, div; - -#if defined(CONFIG_MGT5100) - baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32; -#elif defined(CONFIG_MPC5200) - baseclk = (gd->ipb_clk + 16) / 32; -#endif - - /* set up UART divisor */ - div = (baseclk + (gd->baudrate/2)) / gd->baudrate; - psc->ctur = (div >> 8) & 0xFF; - psc->ctlr = div & 0xff; -} -#endif /* CONFIG_PSC_CONSOLE */ diff --git a/cpu/mpc5xxx/speed.c b/cpu/mpc5xxx/speed.c deleted file mode 100644 index 4f4e814..0000000 --- a/cpu/mpc5xxx/speed.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -/* Bus-to-Core Multipliers */ - -static int bus2core[] = { - 3, 2, 2, 2, 4, 4, 5, 9, - 6, 11, 8, 10, 3, 12, 7, 0, - 6, 5, 13, 2, 14, 4, 15, 9, - 0, 11, 8, 10, 16, 12, 7, 0 -}; -/* ------------------------------------------------------------------------- */ - -/* - * - */ - -int get_clocks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong val, vco; - -#if !defined(CFG_MPC5XXX_CLKIN) -#error clock measuring not implemented yet - define CFG_MPC5XXX_CLKIN -#endif - - val = *(vu_long *)MPC5XXX_CDM_PORCFG; - if (val & (1 << 6)) { - vco = CFG_MPC5XXX_CLKIN * 12; - } else { - vco = CFG_MPC5XXX_CLKIN * 16; - } - if (val & (1 << 5)) { - gd->bus_clk = vco / 8; - } else { - gd->bus_clk = vco / 4; - } - gd->cpu_clk = gd->bus_clk * bus2core[val & 0x1f] / 2; - - val = *(vu_long *)MPC5XXX_CDM_CFG; - if (val & (1 << 8)) { - gd->ipb_clk = gd->bus_clk / 2; - } else { - gd->ipb_clk = gd->bus_clk; - } - switch (val & 3) { - case 0: gd->pci_clk = gd->ipb_clk; break; - case 1: gd->pci_clk = gd->ipb_clk / 2; break; - default: gd->pci_clk = gd->bus_clk / 4; break; - } - - return (0); -} - -int prt_mpc5xxx_clks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - printf(" Bus %ld MHz, IPB %ld MHz, PCI %ld MHz\n", - gd->bus_clk / 1000000, gd->ipb_clk / 1000000, - gd->pci_clk / 1000000); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S deleted file mode 100644 index 3936b55..0000000 --- a/cpu/mpc5xxx/start.S +++ /dev/null @@ -1,810 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000 - 2003 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * U-Boot - Startup Code for MPC5xxx CPUs - */ -#include -#include -#include - -#define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Floating Point enable, Machine Check and Recoverable Interr. */ -#ifdef DEBUG -#define MSR_KERNEL (MSR_FP|MSR_RI) -#else -#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) -#endif - -/* - * Set up GOT: Global Offset Table - * - * Use r14 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * Version string - */ - .data - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - -/* - * Exception vectors - */ - .text - . = EXC_OFF_SYS_RESET - .globl _start -_start: - li r21, BOOTFLAG_COLD /* Normal Power-On */ - nop - b boot_cold - - . = EXC_OFF_SYS_RESET + 0x10 - - .globl _start_warm -_start_warm: - li r21, BOOTFLAG_WARM /* Software reboot */ - b boot_warm - -boot_cold: -boot_warm: - mfmsr r5 /* save msr contents */ - - /* Move CSBoot and adjust instruction pointer */ - /*--------------------------------------------------------------*/ - -#if defined(CFG_LOWBOOT) -# if defined(CFG_RAMBOOT) -# error CFG_LOWBOOT is incompatible with CFG_RAMBOOT -# endif /* CFG_RAMBOOT */ -# if defined(CONFIG_MGT5100) -# error CFG_LOWBOOT is incompatible with MGT5100 -# endif /* CONFIG_MGT5100 */ - lis r4, CFG_DEFAULT_MBAR@h - lis r3, START_REG(CFG_BOOTCS_START)@h - ori r3, r3, START_REG(CFG_BOOTCS_START)@l - stw r3, 0x4(r4) /* CS0 start */ - lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h - ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l - stw r3, 0x8(r4) /* CS0 stop */ - lis r3, 0x02010000@h - ori r3, r3, 0x02010000@l - stw r3, 0x54(r4) /* CS0 and Boot enable */ - - lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */ - ori r3, r3, lowboot_reentry@l /* to the address space the linker used */ - mtlr r3 - blr - -lowboot_reentry: - lis r3, START_REG(CFG_BOOTCS_START)@h - ori r3, r3, START_REG(CFG_BOOTCS_START)@l - stw r3, 0x4c(r4) /* Boot start */ - lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h - ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l - stw r3, 0x50(r4) /* Boot stop */ - lis r3, 0x02000001@h - ori r3, r3, 0x02000001@l - stw r3, 0x54(r4) /* Boot enable, CS0 disable */ -#endif /* CFG_LOWBOOT */ - -#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT) - lis r3, CFG_MBAR@h - ori r3, r3, CFG_MBAR@l -#if defined(CONFIG_MPC5200) - /* MBAR is mirrored into the MBAR SPR */ - mtspr MBAR,r3 - rlwinm r3, r3, 16, 16, 31 -#endif -#if defined(CONFIG_MGT5100) - rlwinm r3, r3, 17, 15, 31 -#endif - lis r4, CFG_DEFAULT_MBAR@h - stw r3, 0(r4) -#endif /* CFG_DEFAULT_MBAR */ - - /* Initialise the MPC5xxx processor core */ - /*--------------------------------------------------------------*/ - - bl init_5xxx_core - - /* initialize some things that are hard to access from C */ - /*--------------------------------------------------------------*/ - - /* set up stack in on-chip SRAM */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l - ori r1, r3, CFG_INIT_SP_OFFSET - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*--------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (in Flash)*/ - - mr r3, r21 - /* r3: BOOTFLAG */ - bl board_init_f /* run 1st part of board init code (in Flash)*/ - -/* - * Vector Table - */ - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) -#ifdef DEBUG - . = 0x1300 - /* - * This exception occurs when the program counter matches the - * Instruction Address Breakpoint Register (IABR). - * - * I want the cpu to halt if this occurs so I can hunt around - * with the debugger and look at things. - * - * When DEBUG is defined, both machine check enable (in the MSR) - * and checkstop reset enable (in the reset mode register) are - * turned off and so a checkstop condition will result in the cpu - * halting. - * - * I force the cpu into a checkstop condition by putting an illegal - * instruction here (at least this is the theory). - * - * well - that didnt work, so just do an infinite loop! - */ -1: b 1b -#else - STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) -#endif - STD_EXCEPTION(0x1400, SMI, UnknownException) - - STD_EXCEPTION(0x1500, Trap_15, UnknownException) - STD_EXCEPTION(0x1600, Trap_16, UnknownException) - STD_EXCEPTION(0x1700, Trap_17, UnknownException) - STD_EXCEPTION(0x1800, Trap_18, UnknownException) - STD_EXCEPTION(0x1900, Trap_19, UnknownException) - STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) - STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) - STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) - STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) - STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) - STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) - STD_EXCEPTION(0x2000, Trap_20, UnknownException) - STD_EXCEPTION(0x2100, Trap_21, UnknownException) - STD_EXCEPTION(0x2200, Trap_22, UnknownException) - STD_EXCEPTION(0x2300, Trap_23, UnknownException) - STD_EXCEPTION(0x2400, Trap_24, UnknownException) - STD_EXCEPTION(0x2500, Trap_25, UnknownException) - STD_EXCEPTION(0x2600, Trap_26, UnknownException) - STD_EXCEPTION(0x2700, Trap_27, UnknownException) - STD_EXCEPTION(0x2800, Trap_28, UnknownException) - STD_EXCEPTION(0x2900, Trap_29, UnknownException) - STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) - STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) - STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) - STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) - STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) - STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x3000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* - * This code initialises the MPC5xxx processor core - * (conforms to PowerPC 603e spec) - * Note: expects original MSR contents to be in r5. - */ - - .globl init_5xx_core -init_5xxx_core: - - /* Initialize machine status; enable machine check interrupt */ - /*--------------------------------------------------------------*/ - - li r3, MSR_KERNEL /* Set ME and RI flags */ - rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ -#ifdef DEBUG - rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ -#endif - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - /* Initialize the Hardware Implementation-dependent Registers */ - /* HID0 also contains cache control */ - /*--------------------------------------------------------------*/ - - lis r3, CFG_HID0_INIT@h - ori r3, r3, CFG_HID0_INIT@l - SYNC - mtspr HID0, r3 - - lis r3, CFG_HID0_FINAL@h - ori r3, r3, CFG_HID0_FINAL@l - SYNC - mtspr HID0, r3 - - /* clear all BAT's */ - /*--------------------------------------------------------------*/ - - li r0, 0 - mtspr DBAT0U, r0 - mtspr DBAT0L, r0 - mtspr DBAT1U, r0 - mtspr DBAT1L, r0 - mtspr DBAT2U, r0 - mtspr DBAT2L, r0 - mtspr DBAT3U, r0 - mtspr DBAT3L, r0 - mtspr DBAT4U, r0 - mtspr DBAT4L, r0 - mtspr DBAT5U, r0 - mtspr DBAT5L, r0 - mtspr DBAT6U, r0 - mtspr DBAT6L, r0 - mtspr DBAT7U, r0 - mtspr DBAT7L, r0 - mtspr IBAT0U, r0 - mtspr IBAT0L, r0 - mtspr IBAT1U, r0 - mtspr IBAT1L, r0 - mtspr IBAT2U, r0 - mtspr IBAT2L, r0 - mtspr IBAT3U, r0 - mtspr IBAT3L, r0 - mtspr IBAT4U, r0 - mtspr IBAT4L, r0 - mtspr IBAT5U, r0 - mtspr IBAT5L, r0 - mtspr IBAT6U, r0 - mtspr IBAT6L, r0 - mtspr IBAT7U, r0 - mtspr IBAT7L, r0 - SYNC - - /* invalidate all tlb's */ - /* */ - /* From the 603e User Manual: "The 603e provides the ability to */ - /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ - /* instruction invalidates the TLB entry indexed by the EA, and */ - /* operates on both the instruction and data TLBs simultaneously*/ - /* invalidating four TLB entries (both sets in each TLB). The */ - /* index corresponds to bits 15-19 of the EA. To invalidate all */ - /* entries within both TLBs, 32 tlbie instructions should be */ - /* issued, incrementing this field by one each time." */ - /* */ - /* "Note that the tlbia instruction is not implemented on the */ - /* 603e." */ - /* */ - /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ - /* incrementing by 0x1000 each time. The code below is sort of */ - /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */ - /* */ - /*--------------------------------------------------------------*/ - - li r3, 32 - mtctr r3 - li r3, 0 -1: tlbie r3 - addi r3, r3, 0x1000 - bdnz 1b - SYNC - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr - -/* Cache functions. - * - * Note: requires that all cache bits in - * HID0 are in the low half word. - */ - .globl icache_enable -icache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_ICE - lis r4, 0 - ori r4, r4, HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_disable -icache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_ICE|HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 - blr - - .globl dcache_enable -dcache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_DCE - lis r4, 0 - ori r4, r4, HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_disable -dcache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_DCE|HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 - blr - - .globl get_svr -get_svr: - mfspr r3, SVR - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r14, r14, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ - rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 - cmpwi r7,0 - beq 9f - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ -9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ - rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 - cmpwi r7,0 - beq 7f - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r14 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - add r0,r0,r11 - stw r0,0(r3) - bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ -2: li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mfmsr r3 /* now that the vectors have */ - lis r7, MSR_IP@h /* relocated into low memory */ - ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ - andc r3, r3, r7 /* (if it was on) */ - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - - mtlr r4 /* restore link register */ - blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr diff --git a/cpu/mpc5xxx/traps.c b/cpu/mpc5xxx/traps.c deleted file mode 100644 index 2ee782b..0000000 --- a/cpu/mpc5xxx/traps.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * linux/arch/ppc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * fixed Machine Check Reasons by Reinhard Meyer (r.meyer@emk-elektronik.de) - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -int (*debugger_exception_handler)(struct pt_regs *) = 0; -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x02000000 - -/* - * Trap & Exception support - */ - -void -print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs * regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -void -_exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void -MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - /* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */ - switch( regs->msr & 0x000F0000) - { - case (0x80000000>>12) : - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13) : - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14) : - printf("Data parity signal\n"); - break; - case (0x80000000>>15) : - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void -AlignmentException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void -ProgramCheckException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void -SoftEmuException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void -UnknownException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -void -DebugException(struct pt_regs *regs) -{ - - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int -addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/cpu/mpc5xxx/usb_ohci.c b/cpu/mpc5xxx/usb_ohci.c deleted file mode 100644 index c774da3..0000000 --- a/cpu/mpc5xxx/usb_ohci.c +++ /dev/null @@ -1,1649 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200. - * - * (C) Copyright 2003-2004 - * Gary Jennejohn, DENX Software Engineering - * - * (C) Copyright 2004 - * Pierre Aubert, Staubli Faverges - * - * Note: Much of this code has been derived from Linux 2.4 - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2002 David Brownell - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* - * IMPORTANT NOTES - * 1 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! - */ - -#include - -#ifdef CONFIG_USB_OHCI - -#include -#include -#include "usb_ohci.h" - -#include - -#define OHCI_USE_NPS /* force NoPowerSwitching mode */ -#undef OHCI_VERBOSE_DEBUG /* not always helpful */ -#undef DEBUG -#undef SHOW_INFO -#undef OHCI_FILL_TRACE - -/* For initializing controller (mask in an HCFS mode too) */ -#define OHCI_CONTROL_INIT \ - (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE - -#define readl(a) (*((vu_long *)(a))) -#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) - -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - -#ifdef DEBUG -#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) -#else -#define dbg(format, arg...) do {} while(0) -#endif /* DEBUG */ -#define err(format, arg...) printf("ERROR: " format "\n", ## arg) -#ifdef SHOW_INFO -#define info(format, arg...) printf("INFO: " format "\n", ## arg) -#else -#define info(format, arg...) do {} while(0) -#endif - -#define m16_swap(x) swap_16(x) -#define m32_swap(x) swap_32(x) - -#ifdef CONFIG_MPC5200 -#define ohci_cpu_to_le16(x) (x) -#define ohci_cpu_to_le32(x) (x) -#else -#define ohci_cpu_to_le16(x) swap_16(x) -#define ohci_cpu_to_le32(x) swap_32(x) -#endif - -/* global ohci_t */ -static ohci_t gohci; -/* this must be aligned to a 256 byte boundary */ -struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* urb_priv */ -urb_priv_t urb_priv; -/* RHSC flag */ -int got_rhsc; -/* device which was disconnected */ -struct usb_device *devgone; -/* flag guarding URB transation */ -int urb_finished = 0; - -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a (struct ohci *hc) - { return read_roothub (hc, a, 0xfc0fe000); } -static inline u32 roothub_b (struct ohci *hc) - { return readl (&hc->regs->roothub.b); } -static inline u32 roothub_status (struct ohci *hc) - { return readl (&hc->regs->roothub.status); } -static u32 roothub_portstatus (struct ohci *hc, int i) - { return read_roothub (hc, portstatus [i], 0xffe0fce0); } - - -/* forward declaration */ -static int hc_interrupt (void); -static void -td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); - -/*-------------------------------------------------------------------------* - * URB support functions - *-------------------------------------------------------------------------*/ - -/* free HCD-private data associated with this URB */ - -static void urb_free_priv (urb_priv_t * urb) -{ - int i; - int last; - struct td * td; - - last = urb->length - 1; - if (last >= 0) { - for (i = 0; i <= last; i++) { - td = urb->td[i]; - if (td) { - td->usb_dev = NULL; - urb->td[i] = NULL; - } - } - } -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -static int sohci_get_current_frame_number (struct usb_device * dev); - -/* debug| print the main components of an URB - * small: 0) header + data packets 1) just header */ - -static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, char * str, int small) -{ - urb_priv_t * purb = &urb_priv; - - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", - str, - sohci_get_current_frame_number (dev), - usb_pipedevice (pipe), - usb_pipeendpoint (pipe), - usb_pipeout (pipe)? 'O': 'I', - usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): - (usb_pipecontrol (pipe)? "CTRL": "BULK"), - purb->actual_length, - transfer_len, dev->status); -#ifdef OHCI_VERBOSE_DEBUG - if (!small) { - int i, len; - - if (usb_pipecontrol (pipe)) { - printf (__FILE__ ": cmd(8):"); - for (i = 0; i < 8 ; i++) - printf (" %02x", ((__u8 *) setup) [i]); - printf ("\n"); - } - if (transfer_len > 0 && buffer) { - printf (__FILE__ ": data(%d/%d):", - purb->actual_length, - transfer_len); - len = usb_pipeout (pipe)? - transfer_len: purb->actual_length; - for (i = 0; i < 16 && i < len; i++) - printf (" %02x", ((__u8 *) buffer) [i]); - printf ("%s\n", i < len? "...": ""); - } - } -#endif -} - -/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ -void ep_print_int_eds (ohci_t *ohci, char * str) { - int i, j; - __u32 * ed_p; - for (i= 0; i < 32; i++) { - j = 5; - ed_p = &(ohci->hcca->int_table [i]); - if (*ed_p == 0) - continue; - printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); - while (*ed_p != 0 && j--) { - ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p); - printf (" ed: %4x;", ed->hwINFO); - ed_p = &ed->hwNextED; - } - printf ("\n"); - } -} - -static void ohci_dump_intr_mask (char *label, __u32 mask) -{ - dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", - label, - mask, - (mask & OHCI_INTR_MIE) ? " MIE" : "", - (mask & OHCI_INTR_OC) ? " OC" : "", - (mask & OHCI_INTR_RHSC) ? " RHSC" : "", - (mask & OHCI_INTR_FNO) ? " FNO" : "", - (mask & OHCI_INTR_UE) ? " UE" : "", - (mask & OHCI_INTR_RD) ? " RD" : "", - (mask & OHCI_INTR_SF) ? " SF" : "", - (mask & OHCI_INTR_WDH) ? " WDH" : "", - (mask & OHCI_INTR_SO) ? " SO" : "" - ); -} - -static void maybe_print_eds (char *label, __u32 value) -{ - ed_t *edp = (ed_t *)value; - - if (value) { - dbg ("%s %08x", label, value); - dbg ("%08x", edp->hwINFO); - dbg ("%08x", edp->hwTailP); - dbg ("%08x", edp->hwHeadP); - dbg ("%08x", edp->hwNextED); - } -} - -static char * hcfs2string (int state) -{ - switch (state) { - case OHCI_USB_RESET: return "reset"; - case OHCI_USB_RESUME: return "resume"; - case OHCI_USB_OPER: return "operational"; - case OHCI_USB_SUSPEND: return "suspend"; - } - return "?"; -} - -/* dump control and status registers */ -static void ohci_dump_status (ohci_t *controller) -{ - struct ohci_regs *regs = controller->regs; - __u32 temp; - - temp = readl (®s->revision) & 0xff; - if (temp != 0x10) - dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); - - temp = readl (®s->control); - dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, - (temp & OHCI_CTRL_RWE) ? " RWE" : "", - (temp & OHCI_CTRL_RWC) ? " RWC" : "", - (temp & OHCI_CTRL_IR) ? " IR" : "", - hcfs2string (temp & OHCI_CTRL_HCFS), - (temp & OHCI_CTRL_BLE) ? " BLE" : "", - (temp & OHCI_CTRL_CLE) ? " CLE" : "", - (temp & OHCI_CTRL_IE) ? " IE" : "", - (temp & OHCI_CTRL_PLE) ? " PLE" : "", - temp & OHCI_CTRL_CBSR - ); - - temp = readl (®s->cmdstatus); - dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, - (temp & OHCI_SOC) >> 16, - (temp & OHCI_OCR) ? " OCR" : "", - (temp & OHCI_BLF) ? " BLF" : "", - (temp & OHCI_CLF) ? " CLF" : "", - (temp & OHCI_HCR) ? " HCR" : "" - ); - - ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); - ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); - - maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); - - maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); - maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); - - maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); - maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); - - maybe_print_eds ("donehead", readl (®s->donehead)); -} - -static void ohci_dump_roothub (ohci_t *controller, int verbose) -{ - __u32 temp, ndp, i; - - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - - if (verbose) { - dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, - ((temp & RH_A_POTPGT) >> 24) & 0xff, - (temp & RH_A_NOCP) ? " NOCP" : "", - (temp & RH_A_OCPM) ? " OCPM" : "", - (temp & RH_A_DT) ? " DT" : "", - (temp & RH_A_NPS) ? " NPS" : "", - (temp & RH_A_PSM) ? " PSM" : "", - ndp - ); - temp = roothub_b (controller); - dbg ("roothub.b: %08x PPCM=%04x DR=%04x", - temp, - (temp & RH_B_PPCM) >> 16, - (temp & RH_B_DR) - ); - temp = roothub_status (controller); - dbg ("roothub.status: %08x%s%s%s%s%s%s", - temp, - (temp & RH_HS_CRWE) ? " CRWE" : "", - (temp & RH_HS_OCIC) ? " OCIC" : "", - (temp & RH_HS_LPSC) ? " LPSC" : "", - (temp & RH_HS_DRWE) ? " DRWE" : "", - (temp & RH_HS_OCI) ? " OCI" : "", - (temp & RH_HS_LPS) ? " LPS" : "" - ); - } - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", - i, - temp, - (temp & RH_PS_PRSC) ? " PRSC" : "", - (temp & RH_PS_OCIC) ? " OCIC" : "", - (temp & RH_PS_PSSC) ? " PSSC" : "", - (temp & RH_PS_PESC) ? " PESC" : "", - (temp & RH_PS_CSC) ? " CSC" : "", - - (temp & RH_PS_LSDA) ? " LSDA" : "", - (temp & RH_PS_PPS) ? " PPS" : "", - (temp & RH_PS_PRS) ? " PRS" : "", - (temp & RH_PS_POCI) ? " POCI" : "", - (temp & RH_PS_PSS) ? " PSS" : "", - - (temp & RH_PS_PES) ? " PES" : "", - (temp & RH_PS_CCS) ? " CCS" : "" - ); - } -} - -static void ohci_dump (ohci_t *controller, int verbose) -{ - dbg ("OHCI controller usb-%s state", controller->slot_name); - - /* dumps some of the state we know about */ - ohci_dump_status (controller); - if (verbose) - ep_print_int_eds (controller, "hcca"); - dbg ("hcca frame #%04x", controller->hcca->frame_no); - ohci_dump_roothub (controller, 1); -} - - -#endif /* DEBUG */ - -/*-------------------------------------------------------------------------* - * Interface functions (URB) - *-------------------------------------------------------------------------*/ - -/* get a transfer request */ - -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - ohci_t *ohci; - ed_t * ed; - urb_priv_t *purb_priv; - int i, size = 0; - - ohci = &gohci; - - /* when controller's hung, permit only roothub cleanup attempts - * such as powering down ports */ - if (ohci->disabled) { - err("sohci_submit_job: EPIPE"); - return -1; - } - - /* if we have an unfinished URB from previous transaction let's - * fail and scream as quickly as possible so as not to corrupt - * further communication */ - if (!urb_finished) { - err("sohci_submit_job: URB NOT FINISHED"); - return -1; - } - /* we're about to begin a new transaction here so mark the URB unfinished */ - urb_finished = 0; - - /* every endpoint has a ed, locate and fill it */ - if (!(ed = ep_add_ed (dev, pipe))) { - err("sohci_submit_job: ENOMEM"); - return -1; - } - - /* for the private part of the URB we need the number of TDs (size) */ - switch (usb_pipetype (pipe)) { - case PIPE_BULK: /* one TD for every 4096 Byte */ - size = (transfer_len - 1) / 4096 + 1; - break; - case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ - size = (transfer_len == 0)? 2: - (transfer_len - 1) / 4096 + 3; - break; - } - - if (size >= (N_URB_TD - 1)) { - err("need %d TDs, only have %d", size, N_URB_TD); - return -1; - } - purb_priv = &urb_priv; - purb_priv->pipe = pipe; - - /* fill the private part of the URB */ - purb_priv->length = size; - purb_priv->ed = ed; - purb_priv->actual_length = 0; - - /* allocate the TDs */ - /* note that td[0] was allocated in ep_add_ed */ - for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc (dev); - if (!purb_priv->td[i]) { - purb_priv->length = i; - urb_free_priv (purb_priv); - err("sohci_submit_job: ENOMEM"); - return -1; - } - } - - if (ed->state == ED_NEW || (ed->state & ED_DEL)) { - urb_free_priv (purb_priv); - err("sohci_submit_job: EINVAL"); - return -1; - } - - /* link the ed into a chain if is not already */ - if (ed->state != ED_OPER) - ep_link (ohci, ed); - - /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -/* tell us the current USB frame number */ - -static int sohci_get_current_frame_number (struct usb_device *usb_dev) -{ - ohci_t *ohci = &gohci; - - return ohci_cpu_to_le16 (ohci->hcca->frame_no); -} -#endif - -/*-------------------------------------------------------------------------* - * ED handling functions - *-------------------------------------------------------------------------*/ - -/* link an ed into one of the HC chains */ - -static int ep_link (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->state = ED_OPER; - - switch (ed->type) { - case PIPE_CONTROL: - ed->hwNextED = 0; - if (ohci->ed_controltail == NULL) { - writel (ed, &ohci->regs->ed_controlhead); - } else { - ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); - } - ed->ed_prev = ohci->ed_controltail; - if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_controltail = edi; - break; - - case PIPE_BULK: - ed->hwNextED = 0; - if (ohci->ed_bulktail == NULL) { - writel (ed, &ohci->regs->ed_bulkhead); - } else { - ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); - } - ed->ed_prev = ohci->ed_bulktail; - if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_bulktail = edi; - break; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* unlink an ed from one of the HC chains. - * just the link to the ed is unlinked. - * the link from the ed still points to another operational ed or 0 - * so the HC can eventually finish the processing of the unlinked ed */ - -static int ep_unlink (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP); - - switch (ed->type) { - case PIPE_CONTROL: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_controltail == ed) { - ohci->ed_controltail = ed->ed_prev; - } else { - ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - - case PIPE_BULK: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_bulktail == ed) { - ohci->ed_bulktail = ed->ed_prev; - } else { - ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - } - ed->state = ED_UNLINK; - return 0; -} - - -/*-------------------------------------------------------------------------*/ - -/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, - * but the USB stack is a little bit stateless so we do it at every transaction - * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK - * in all other cases the state is left unchanged - * the ed info fields are setted anyway even though most of them should not change */ - -static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) -{ - td_t *td; - ed_t *ed_ret; - volatile ed_t *ed; - - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | - (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; - - if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { - err("ep_add_ed: pending delete"); - /* pending delete request */ - return NULL; - } - - if (ed->state == ED_NEW) { - ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */ - /* dummy td; end of td list for ed */ - td = td_alloc (usb_dev); - ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td); - ed->hwHeadP = ed->hwTailP; - ed->state = ED_UNLINK; - ed->type = usb_pipetype (pipe); - ohci_dev.ed_cnt++; - } - - ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe) - | usb_pipeendpoint (pipe) << 7 - | (usb_pipeisoc (pipe)? 0x8000: 0) - | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | usb_pipeslow (pipe) << 13 - | usb_maxpacket (usb_dev, pipe) << 16); - - return ed_ret; -} - -/*-------------------------------------------------------------------------* - * TD handling functions - *-------------------------------------------------------------------------*/ - -/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ - -static void td_fill (ohci_t *ohci, unsigned int info, - void *data, int len, - struct usb_device *dev, int index, urb_priv_t *urb_priv) -{ - volatile td_t *td, *td_pt; -#ifdef OHCI_FILL_TRACE - int i; -#endif - - if (index > urb_priv->length) { - err("index > length"); - return; - } - /* use this td as the next dummy */ - td_pt = urb_priv->td [index]; - td_pt->hwNextTD = 0; - - /* fill the old dummy TD */ - td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf); - - td->ed = urb_priv->ed; - td->next_dl_td = NULL; - td->index = index; - td->data = (__u32)data; -#ifdef OHCI_FILL_TRACE - if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { - for (i = 0; i < len; i++) - printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); - printf("\n"); - } -#endif - if (!len) - data = 0; - - td->hwINFO = ohci_cpu_to_le32 (info); - td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data); - if (data) - td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1)); - else - td->hwBE = 0; - td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt); - - /* append to queue */ - td->ed->hwTailP = td->hwNextTD; -} - -/*-------------------------------------------------------------------------*/ - -/* prepare all TDs of a transfer */ -static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) -{ - ohci_t *ohci = &gohci; - int data_len = transfer_len; - void *data; - int cnt = 0; - __u32 info = 0; - unsigned int toggle = 0; - - /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ - if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { - toggle = TD_T_TOGGLE; - } else { - toggle = TD_T_DATA0; - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); - } - urb->td_cnt = 0; - if (data_len) - data = buffer; - else - data = 0; - - switch (usb_pipetype (pipe)) { - case PIPE_BULK: - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; - while(data_len > 4096) { - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); - data += 4096; data_len -= 4096; cnt++; - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); - cnt++; - - if (!ohci->sleeping) - writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ - break; - - case PIPE_CONTROL: - info = TD_CC | TD_DP_SETUP | TD_T_DATA0; - td_fill (ohci, info, setup, 8, dev, cnt++, urb); - if (data_len > 0) { - info = usb_pipeout (pipe)? - TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; - /* NOTE: mishandles transfers >8K, some >4K */ - td_fill (ohci, info, data, data_len, dev, cnt++, urb); - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; - td_fill (ohci, info, data, 0, dev, cnt++, urb); - if (!ohci->sleeping) - writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ - break; - } - if (urb->length != cnt) - dbg("TD LENGTH %d != CNT %d", urb->length, cnt); -} - -/*-------------------------------------------------------------------------* - * Done List handling functions - *-------------------------------------------------------------------------*/ - - -/* calculate the transfer length and update the urb */ - -static void dl_transfer_length(td_t * td) -{ - __u32 tdINFO, tdBE, tdCBP; - urb_priv_t *lurb_priv = &urb_priv; - - tdINFO = ohci_cpu_to_le32 (td->hwINFO); - tdBE = ohci_cpu_to_le32 (td->hwBE); - tdCBP = ohci_cpu_to_le32 (td->hwCBP); - - - if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && - ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { - if (tdBE != 0) { - if (td->hwCBP == 0) - lurb_priv->actual_length += tdBE - td->data + 1; - else - lurb_priv->actual_length += tdCBP - td->data; - } - } -} - -/*-------------------------------------------------------------------------*/ - -/* replies to the request have to be on a FIFO basis so - * we reverse the reversed done-list */ - -static td_t * dl_reverse_done_list (ohci_t *ohci) -{ - __u32 td_list_hc; - td_t *td_rev = NULL; - td_t *td_list = NULL; - urb_priv_t *lurb_priv = NULL; - - td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0; - ohci->hcca->done_head = 0; - - while (td_list_hc) { - td_list = (td_t *)td_list_hc; - - if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) { - lurb_priv = &urb_priv; - dbg(" USB-error/status: %x : %p", - TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list); - if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) { - if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { - td_list->ed->hwHeadP = - (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) | - (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2)); - lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; - } else - td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); - } -#ifdef CONFIG_MPC5200 - td_list->hwNextTD = 0; -#endif - } - - td_list->next_dl_td = td_rev; - td_rev = td_list; - td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0; - } - return td_list; -} - -/*-------------------------------------------------------------------------*/ - -/* td done list */ -static int dl_done_list (ohci_t *ohci, td_t *td_list) -{ - td_t *td_list_next = NULL; - ed_t *ed; - int cc = 0; - int stat = 0; - /* urb_t *urb; */ - urb_priv_t *lurb_priv; - __u32 tdINFO, edHeadP, edTailP; - - while (td_list) { - td_list_next = td_list->next_dl_td; - - lurb_priv = &urb_priv; - tdINFO = ohci_cpu_to_le32 (td_list->hwINFO); - - ed = td_list->ed; - - dl_transfer_length(td_list); - - /* error code of transfer */ - cc = TD_CC_GET (tdINFO); - if (++(lurb_priv->td_cnt) == lurb_priv->length) { - if ((ed->state & (ED_OPER | ED_UNLINK)) - && (lurb_priv->state != URB_DEL)) { - dbg("ConditionCode %#x", cc); - stat = cc_to_error[cc]; - urb_finished = 1; - } - } - - if (ed->state != ED_NEW) { - edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0; - edTailP = ohci_cpu_to_le32 (ed->hwTailP); - - /* unlink eds if they are not busy */ - if ((edHeadP == edTailP) && (ed->state == ED_OPER)) - ep_unlink (ohci, ed); - } - - td_list = td_list_next; - } - return stat; -} - -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ - -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - -/* Hub class-specific descriptor is constructed dynamically */ - - -/*-------------------------------------------------------------------------*/ - -#define OK(x) len = (x); break -#ifdef DEBUG -#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} -#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} -#else -#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) -#endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) - -/* request to virtual root hub */ - -int rh_check_port_status(ohci_t *controller) -{ - __u32 temp, ndp, i; - int res; - - res = -1; - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - /* check for a device disconnect */ - if (((temp & (RH_PS_PESC | RH_PS_CSC)) == - (RH_PS_PESC | RH_PS_CSC)) && - ((temp & RH_PS_CCS) == 0)) { - res = i; - break; - } - } - return res; -} - -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *cmd) -{ - void * data = buffer; - int leni = transfer_len; - int len = 0; - int stat = 0; - __u32 datab[4]; - __u8 *data_buf = (__u8 *)datab; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; - -#ifdef DEBUG -urb_priv.actual_length = 0; -pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); -#endif - if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { - info("Root-Hub submit IRQ: NOT implemented"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = m16_swap (cmd->value); - wIndex = m16_swap (cmd->index); - wLength = m16_swap (cmd->length); - - info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", - dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(__u16 *) data_buf = m16_swap (1); OK (2); - case RH_GET_STATUS | RH_INTERFACE: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_ENDPOINT: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_CLASS: - *(__u32 *) data_buf = m32_swap ( - RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); - OK (4); - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); - - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case RH_C_HUB_LOCAL_POWER: - OK(0); - case (RH_C_HUB_OVER_CURRENT): - WR_RH_STAT(RH_HS_OCIC); OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_POCI); OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); - case (RH_C_PORT_CONNECTION): - WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); - case (RH_C_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_PESC); OK (0); - case (RH_C_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); - case (RH_C_PORT_OVER_CURRENT): - WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); - case (RH_C_PORT_RESET): - WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); - } - break; - - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); - case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PRS); - OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); - case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PES ); - OK (0); - } - break; - - case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_dev_des), - wLength)); - data_buf = root_hub_dev_des; OK(len); - case (0x02): /* configuration descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_config_des), - wLength)); - data_buf = root_hub_config_des; OK(len); - case (0x03): /* string descriptors */ - if(wValue==0x0300) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index0), - wLength)); - data_buf = root_hub_str_index0; - OK(len); - } - if(wValue==0x0301) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index1), - wLength)); - data_buf = root_hub_str_index1; - OK(len); - } - default: - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - { - __u32 temp = roothub_a (&gohci); - - data_buf [0] = 9; /* min length; */ - data_buf [1] = 0x29; - data_buf [2] = temp & RH_A_NDP; - data_buf [3] = 0; - if (temp & RH_A_PSM) /* per-port power switching? */ - data_buf [3] |= 0x1; - if (temp & RH_A_NOCP) /* no overcurrent reporting? */ - data_buf [3] |= 0x10; - else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ - data_buf [3] |= 0x8; - - /* corresponds to data_buf[4-7] */ - datab [1] = 0; - data_buf [5] = (temp & RH_A_POTPGT) >> 24; - temp = roothub_b (&gohci); - data_buf [7] = temp & RH_B_DR; - if (data_buf [2] < 7) { - data_buf [8] = 0xff; - } else { - data_buf [0] += 2; - data_buf [8] = (temp & RH_B_DR) >> 8; - data_buf [10] = data_buf [9] = 0xff; - } - - len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf [0], wLength)); - OK (len); - } - - case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); - - case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); - - default: - dbg ("unsupported root hub command"); - stat = USB_ST_STALLED; - } - -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - - len = min_t(int, len, leni); - if (data != data_buf) - memcpy (data, data_buf, len); - dev->act_len = len; - dev->status = stat; - -#ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); -#endif - - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/* common code for handling submit messages - used for all but root hub */ -/* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; - - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } - -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#endif - if (!maxsize) { - err("submit_common_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { - err("sohci_submit_job failed"); - return -1; - } - - /* allow more time for a BULK device to react - some are slow */ -#define BULK_TO 5000 /* timeout in milliseconds */ - if (usb_pipetype (pipe) == PIPE_BULK) - timeout = BULK_TO; - else - timeout = 100; - - /* wait for it to complete */ - for (;;) { - /* check whether the controller is done */ - stat = hc_interrupt(); - if (stat < 0) { - stat = USB_ST_CRC_ERR; - break; - } - - /* NOTE: since we are not interrupt driven in U-Boot and always - * handle only one URB at a time, we cannot assume the - * transaction finished on the first successful return from - * hc_interrupt().. unless the flag for current URB is set, - * meaning that all TD's to/from device got actually - * transferred and processed. If the current URB is not - * finished we need to re-iterate this loop so as - * hc_interrupt() gets called again as there needs to be some - * more TD's to process still */ - if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { - /* 0xff is returned for an SF-interrupt */ - break; - } - - if (--timeout) { - wait_ms(1); - if (!urb_finished) - dbg("\%"); - - } else { - err("CTL:TIMEOUT "); - dbg("submit_common_msg: TO status %x\n", stat); - stat = USB_ST_CRC_ERR; - urb_finished = 1; - break; - } - } -#if 0 - /* we got an Root Hub Status Change interrupt */ - if (got_rhsc) { -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - got_rhsc = 0; - /* abuse timeout */ - timeout = rh_check_port_status(&gohci); - if (timeout >= 0) { -#if 0 /* this does nothing useful, but leave it here in case that changes */ - /* the called routine adds 1 to the passed value */ - usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); -#endif - /* - * XXX - * This is potentially dangerous because it assumes - * that only one device is ever plugged in! - */ - devgone = dev; - } - } -#endif - - dev->status = stat; - dev->act_len = transfer_len; - -#ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); -#endif - - /* free TDs in urb_priv */ - urb_free_priv (&urb_priv); - return 0; -} - -/* submit routines called from usb.c */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) -{ - info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) -{ - int maxsize = usb_maxpacket(dev, pipe); - - info("submit_control_msg"); -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#endif - if (!maxsize) { - err("submit_control_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; - /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); - } - - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return -1; -} - -/*-------------------------------------------------------------------------* - * HC functions - *-------------------------------------------------------------------------*/ - -/* reset the HC and BUS */ - -static int hc_reset (ohci_t *ohci) -{ - int timeout = 30; - int smm_timeout = 50; /* 0,5 sec */ - - if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ - writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ - info("USB HC TakeOver from SMM"); - while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms (10); - if (--smm_timeout == 0) { - err("USB HC TakeOver failed!"); - return -1; - } - } - } - - /* Disable HC interrupts */ - writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); - - dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", - ohci->slot_name, - readl (&ohci->regs->control)); - - /* Reset USB (needed by some controllers) */ - ohci->hc_control = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* HC Reset requires max 10 us delay */ - writel (OHCI_HCR, &ohci->regs->cmdstatus); - while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { - if (--timeout == 0) { - err("USB HC reset timed out!"); - return -1; - } - udelay (1); - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* Start an OHCI controller, set the BUS operational - * enable interrupts - * connect the virtual root hub */ - -static int hc_start (ohci_t * ohci) -{ - __u32 mask; - unsigned int fminterval; - - ohci->disabled = 1; - - /* Tell the controller where the control and bulk lists are - * The lists are empty now. */ - - writel (0, &ohci->regs->ed_controlhead); - writel (0, &ohci->regs->ed_bulkhead); - - writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ - - fminterval = 0x2edf; - writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); - fminterval |= ((((fminterval - 210) * 6) / 7) << 16); - writel (fminterval, &ohci->regs->fminterval); - writel (0x628, &ohci->regs->lsthresh); - - /* start controller operations */ - ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; - ohci->disabled = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* disable all interrupts */ - mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | - OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | - OHCI_INTR_OC | OHCI_INTR_MIE); - writel (mask, &ohci->regs->intrdisable); - /* clear all interrupts */ - mask &= ~OHCI_INTR_MIE; - writel (mask, &ohci->regs->intrstatus); - /* Choose the interrupts we care about now - but w/o MIE */ - mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; - writel (mask, &ohci->regs->intrenable); - -#ifdef OHCI_USE_NPS - /* required for AMD-756 and some Mac platforms */ - writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, - &ohci->regs->roothub.a); - writel (RH_HS_LPSC, &ohci->regs->roothub.status); -#endif /* OHCI_USE_NPS */ - -#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay ((roothub_a (ohci) >> 23) & 0x1fe); - - /* connect the virtual root hub */ - ohci->rh.devnum = 0; - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* an interrupt happens */ - -static int -hc_interrupt (void) -{ - ohci_t *ohci = &gohci; - struct ohci_regs *regs = ohci->regs; - int ints; - int stat = -1; - - if ((ohci->hcca->done_head != 0) && - !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) { - - ints = OHCI_INTR_WDH; - - } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { - ohci->disabled++; - err ("%s device removed!", ohci->slot_name); - return -1; - - } else if ((ints &= readl (®s->intrenable)) == 0) { - dbg("hc_interrupt: returning..\n"); - return 0xff; - } - - /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ - - if (ints & OHCI_INTR_RHSC) { - got_rhsc = 1; - stat = 0xff; - } - - if (ints & OHCI_INTR_UE) { - ohci->disabled++; - err ("OHCI Unrecoverable Error, controller usb-%s disabled", - ohci->slot_name); - /* e.g. due to PCI Master/Target Abort */ - -#ifdef DEBUG - ohci_dump (ohci, 1); -#endif - /* FIXME: be optimistic, hope that bug won't repeat often. */ - /* Make some non-interrupt context restart the controller. */ - /* Count and limit the retries though; either hardware or */ - /* software errors can go forever... */ - hc_reset (ohci); - return -1; - } - - if (ints & OHCI_INTR_WDH) { - writel (OHCI_INTR_WDH, ®s->intrdisable); - stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); - writel (OHCI_INTR_WDH, ®s->intrenable); - } - - if (ints & OHCI_INTR_SO) { - dbg("USB Schedule overrun\n"); - writel (OHCI_INTR_SO, ®s->intrenable); - stat = -1; - } - - /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ - if (ints & OHCI_INTR_SF) { - unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1; - wait_ms(1); - writel (OHCI_INTR_SF, ®s->intrdisable); - if (ohci->ed_rm_list[frame] != NULL) - writel (OHCI_INTR_SF, ®s->intrenable); - stat = 0xff; - } - - writel (ints, ®s->intrstatus); - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -/* De-allocate all resources.. */ - -static void hc_release_ohci (ohci_t *ohci) -{ - dbg ("USB HC release ohci usb-%s", ohci->slot_name); - - if (!ohci->disabled) - hc_reset (ohci); -} - -/*-------------------------------------------------------------------------*/ - -/* - * low level initalisation routine, called from usb.c - */ -static char ohci_inited = 0; - -int usb_lowlevel_init(void) -{ - - /* Set the USB Clock */ - *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK; - - /* remove all USB bits first before ORing in ours */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000; - - /* Activate USB port */ - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG; - - memset (&gohci, 0, sizeof (ohci_t)); - memset (&urb_priv, 0, sizeof (urb_priv_t)); - - /* align the storage */ - if ((__u32)&ghcca[0] & 0xff) { - err("HCCA not aligned!!"); - return -1; - } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32)&ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); - if ((__u32)gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset (phcca, 0, sizeof (struct ohci_hcca)); - - gohci.disabled = 1; - gohci.sleeping = 0; - gohci.irq = -1; - gohci.regs = (struct ohci_regs *)MPC5XXX_USB; - - gohci.flags = 0; - gohci.slot_name = "mpc5200"; - - if (hc_reset (&gohci) < 0) { - hc_release_ohci (&gohci); - return -1; - } - - if (hc_start (&gohci) < 0) { - err ("can't start usb-%s", gohci.slot_name); - hc_release_ohci (&gohci); - return -1; - } - -#ifdef DEBUG - ohci_dump (&gohci, 1); -#endif - ohci_inited = 1; - urb_finished = 1; - - return 0; -} - -int usb_lowlevel_stop(void) -{ - /* this gets called really early - before the controller has */ - /* even been initialized! */ - if (!ohci_inited) - return 0; - /* TODO release any interrupts, etc. */ - /* call hc_release_ohci() here ? */ - hc_reset (&gohci); - return 0; -} - -#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/mpc5xxx/usb_ohci.h b/cpu/mpc5xxx/usb_ohci.h deleted file mode 100644 index 884f1d5..0000000 --- a/cpu/mpc5xxx/usb_ohci.h +++ /dev/null @@ -1,423 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB. - * - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2001 David Brownell - * - * usb-ohci.h - */ - - -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -/* ED States */ - -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 -#define ED_OPER 0x02 -#define ED_DEL 0x04 -#define ED_URB_DEL 0x08 - -/* usb_ohci_ed */ -struct ed { - __u32 hwINFO; - __u32 hwTailP; - __u32 hwHeadP; - __u32 hwNextED; - - struct ed *ed_prev; - __u8 int_period; - __u8 int_branch; - __u8 int_load; - __u8 int_interval; - __u8 state; - __u8 type; - __u16 last_iso; - struct ed *ed_rm_list; - - struct usb_device *usb_dev; - __u32 unused[3]; -} __attribute((aligned(16))); -typedef struct ed ed_t; - - -/* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 - -/* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F - - -#define MAXPSW 1 - -struct td { - __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; - struct usb_device *usb_dev; - int transfer_len; - __u32 data; - - __u32 unused2[2]; -} __attribute((aligned(32))); -typedef struct td td_t; - -#define OHCI_ED_SKIP (1 << 14) - -/* - * The HCCA (Host Controller Communications Area) is a 256 byte - * structure defined in the OHCI spec. that the host controller is - * told the base address of. It must be 256-byte aligned. - */ - -#define NUM_INTS 32 /* part of the OHCI standard */ -struct ohci_hcca { - __u32 int_table[NUM_INTS]; /* Interrupt ED table */ -#if defined(CONFIG_MPC5200) - __u16 pad1; /* set to 0 on each frame_no change */ - __u16 frame_no; /* current frame number */ -#else - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ -#endif - __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; -} __attribute((aligned(256))); - - -/* - * Maximum number of root hub ports. - */ -#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ - -/* - * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and - * writel() macros defined in asm/io.h to access these!! - */ -struct ohci_regs { - /* control and status registers */ - __u32 revision; - __u32 control; - __u32 cmdstatus; - __u32 intrstatus; - __u32 intrenable; - __u32 intrdisable; - /* memory pointers */ - __u32 hcca; - __u32 ed_periodcurrent; - __u32 ed_controlhead; - __u32 ed_controlcurrent; - __u32 ed_bulkhead; - __u32 ed_bulkcurrent; - __u32 donehead; - /* frame counters */ - __u32 fminterval; - __u32 fmremaining; - __u32 fmnumber; - __u32 periodicstart; - __u32 lsthresh; - /* Root hub ports */ - struct ohci_roothub_regs { - __u32 a; - __u32 b; - __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; - } roothub; -} __attribute((aligned(32))); - - -/* OHCI CONTROL AND STATUS REGISTER MASKS */ - -/* - * HcControl (control) register masks - */ -#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ -#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ - -/* pre-shifted values for HCFS */ -# define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) -# define OHCI_USB_OPER (2 << 6) -# define OHCI_USB_SUSPEND (3 << 6) - -/* - * HcCommandStatus (cmdstatus) register masks - */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ - -/* - * masks used with interrupt registers: - * HcInterruptStatus (intrstatus) - * HcInterruptEnable (intrenable) - * HcInterruptDisable (intrdisable) - */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ - - -/* Virtual Root HUB */ -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - void *dev; /* was urb */ - void *int_addr; - int send; - int interval; -}; - -/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ - -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* OHCI ROOT HUB REGISTER MASKS */ - -/* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ - -/* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ - -/* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ - -/* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ - -/* urb */ -#define N_URB_TD 48 -typedef struct -{ - ed_t *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ - int state; - unsigned long pipe; - int actual_length; - td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ -} urb_priv_t; -#define URB_DEL 1 - -/* - * This is the full ohci controller description - * - * Note how the "proper" USB information is just - * a subset of what the full implementation needs. (Linus) - */ - - -typedef struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma;*/ - - int irq; - int disabled; /* e.g. got a UE, we're hung */ - int sleeping; - unsigned long flags; /* for HC bugs */ - - struct ohci_regs *regs; /* OHCI controller's memory */ - - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ - int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ - struct usb_device *dev[32]; - struct virt_root_hub rh; - - const char *slot_name; -} ohci_t; - -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - ed_t ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(ohci_t * ohci, ed_t * ed); -static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -td_t gtd[NUM_TD+1]; -/* pointers to aligned storage */ -td_t *ptd; - -/* TDs ... */ -static inline struct td * -td_alloc (struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) - { - if (ptd[i].usb_dev == NULL) - { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - - return td; -} - -static inline void -ed_free (struct ed *ed) -{ - ed->usb_dev = NULL; -} diff --git a/cpu/mpc8220/Makefile b/cpu/mpc8220/Makefile deleted file mode 100644 index 7c9b6c9..0000000 --- a/cpu/mpc8220/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -ASOBJS = io.o fec_dma_tasks.o -OBJS = cpu.o cpu_init.o dramSetup.o fec.o i2c.o \ - interrupts.o loadtask.o speed.o \ - traps.o uart.o pci.o - -all: .depend $(START) $(ASOBJS) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(ASOBJS) $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/mpc8220/config.mk b/cpu/mpc8220/config.mk deleted file mode 100644 index 6fec5df..0000000 --- a/cpu/mpc8220/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 -ffixed-r29 \ - -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc8220/cpu.c b/cpu/mpc8220/cpu.c deleted file mode 100644 index 0cfe808..0000000 --- a/cpu/mpc8220/cpu.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code for the MPC8220 CPUs - */ - -#include -#include -#include -#include -#include - -int checkcpu (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong clock = gd->cpu_clk; - char buf[32]; - - puts ("CPU: "); - - printf (CPU_ID_STR); - - printf (" (JTAG ID %08lx)", *(vu_long *) (CFG_MBAR + 0x50)); - - printf (" at %s MHz\n", strmhz (buf, clock)); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - volatile gptmr8220_t *gptmr = (volatile gptmr8220_t *) MMAP_GPTMR; - ulong msr; - - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* Charge the watchdog timer */ - gptmr->Prescl = 10; - gptmr->Count = 1; - - gptmr->Mode = GPT_TMS_SGPIO; - - gptmr->Control = GPT_CTRL_WDEN | GPT_CTRL_CE; - - return 1; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * - */ -unsigned long get_tbclk (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong tbclk; - - tbclk = (gd->bus_clk + 3L) / 4L; - - return (tbclk); -} - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8220/cpu_init.c b/cpu/mpc8220/cpu_init.c deleted file mode 100644 index 8c358a8..0000000 --- a/cpu/mpc8220/cpu_init.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers. - */ -void cpu_init_f (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile flexbus8220_t *flexbus = (volatile flexbus8220_t *) MMAP_FB; - volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG; - volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB; - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* Clear all port configuration */ - portcfg->pcfg0 = 0; - portcfg->pcfg1 = 0; - portcfg->pcfg2 = 0; - portcfg->pcfg3 = 0; - portcfg->pcfg2 = CFG_GP1_PORT2_CONFIG; - portcfg->pcfg3 = CFG_PCI_PORT3_CONFIG | CFG_GP2_PORT3_CONFIG; - - /* - * Flexbus Controller: configure chip selects and enable them - */ -#if defined (CFG_CS0_BASE) - flexbus->csar0 = CFG_CS0_BASE; - -/* Sorcery-C can hang-up after CTRL reg initialization */ -#if defined (CFG_CS0_CTRL) - flexbus->cscr0 = CFG_CS0_CTRL; -#endif - flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1; - __asm__ volatile ("sync"); -#endif -#if defined (CFG_CS1_BASE) - flexbus->csar1 = CFG_CS1_BASE; - flexbus->cscr1 = CFG_CS1_CTRL; - flexbus->csmr1 = ((CFG_CS1_MASK - 1) & 0xffff0000) | 1; - __asm__ volatile ("sync"); -#endif -#if defined (CFG_CS2_BASE) - flexbus->csar2 = CFG_CS2_BASE; - flexbus->cscr2 = CFG_CS2_CTRL; - flexbus->csmr2 = ((CFG_CS2_MASK - 1) & 0xffff0000) | 1; - portcfg->pcfg3 |= CFG_CS2_PORT3_CONFIG; - __asm__ volatile ("sync"); -#endif -#if defined (CFG_CS3_BASE) - flexbus->csar3 = CFG_CS3_BASE; - flexbus->cscr3 = CFG_CS3_CTRL; - flexbus->csmr3 = ((CFG_CS3_MASK - 1) & 0xffff0000) | 1; - portcfg->pcfg3 |= CFG_CS3_PORT3_CONFIG; - __asm__ volatile ("sync"); -#endif -#if defined (CFG_CS4_BASE) - flexbus->csar4 = CFG_CS4_BASE; - flexbus->cscr4 = CFG_CS4_CTRL; - flexbus->csmr4 = ((CFG_CS4_MASK - 1) & 0xffff0000) | 1; - portcfg->pcfg3 |= CFG_CS4_PORT3_CONFIG; - __asm__ volatile ("sync"); -#endif -#if defined (CFG_CS5_BASE) - flexbus->csar5 = CFG_CS5_BASE; - flexbus->cscr5 = CFG_CS5_CTRL; - flexbus->csmr5 = ((CFG_CS5_MASK - 1) & 0xffff0000) | 1; - portcfg->pcfg3 |= CFG_CS5_PORT3_CONFIG; - __asm__ volatile ("sync"); -#endif - - /* This section of the code cannot place in cpu_init_r(), - it will cause the system to hang */ - /* enable timebase */ - xlbarb->addrTenTimeOut = 0x1000; - xlbarb->dataTenTimeOut = 0x1000; - xlbarb->busActTimeOut = 0x2000; - - xlbarb->config = 0x00002000; - - /* Master Priority Enable */ - xlbarb->mastPriority = 0; - xlbarb->mastPriEn = 0xff; -} - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ - /* this may belongs to disable interrupt section */ - /* mask all interrupts */ - *(vu_long *) 0xf0000700 = 0xfffffc00; - *(vu_long *) 0xf0000714 |= 0x0001ffff; - *(vu_long *) 0xf0000710 &= ~0x00000f00; - - /* route critical ints to normal ints */ - *(vu_long *) 0xf0000710 |= 0x00000001; - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC8220_FEC) - /* load FEC microcode */ - loadtask (0, 2); -#endif - return (0); -} diff --git a/cpu/mpc8220/dma.h b/cpu/mpc8220/dma.h deleted file mode 100644 index d06ee63..0000000 --- a/cpu/mpc8220/dma.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on code - * (C) Copyright Motorola, Inc., 2000 - * - * MPC8220 dma header file - */ - -#ifndef __MPC8220_DMA_H -#define __MPC8220_DMA_H - -#include -#include - -/* Task number assignment */ -#define FEC_RECV_TASK_NO 0 -#define FEC_XMIT_TASK_NO 1 - -/*--------------------------------------------------------------------- - * Stuff for Ethernet Tx/Rx tasks - *--------------------------------------------------------------------- - */ - -/* Layout of Ethernet controller Parameter SRAM area: - * ---------------------------------------------------------------- - * 0x00: TBD_BASE, base address of TX BD ring - * 0x04: TBD_NEXT, address of next TX BD to be processed - * 0x08: RBD_BASE, base address of RX BD ring - * 0x0C: RBD_NEXT, address of next RX BD to be processed - * --------------------------------------------------------------- - * ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH). - */ - -/* base address of SRAM area to store parameters used by Ethernet tasks */ -#define FEC_PARAM_BASE (MMAP_SRAM + 0x5b00) - -/* base address of SRAM area for buffer descriptors */ -#define FEC_BD_BASE (MMAP_SRAM + 0x5b20) - -/*--------------------------------------------------------------------- - * common shortcuts used by driver C code - *--------------------------------------------------------------------- - */ - -/* Disable SmartDMA task */ -#define DMA_TASK_DISABLE(tasknum) \ -{ \ - volatile ushort *tcr = (ushort *)(MMAP_DMA + 0x0000001c + 2 * tasknum); \ - *tcr = (*tcr) & (~0x8000); \ -} - -/* Enable SmartDMA task */ -#define DMA_TASK_ENABLE(tasknum) \ -{ \ - volatile ushort *tcr = (ushort *) (MMAP_DMA + 0x0000001c + 2 * tasknum);\ - *tcr = (*tcr) | 0x8000; \ -} - -/* Clear interrupt pending bits */ -#define DMA_CLEAR_IEVENT(tasknum) \ -{ \ - struct mpc8220_dma *dma = (struct mpc8220_dma *)MMAP_DMA; \ - dma->IntPend = (1 << tasknum); \ -} - -#endif /* __MPC8220_DMA_H */ diff --git a/cpu/mpc8220/dramSetup.c b/cpu/mpc8220/dramSetup.c deleted file mode 100644 index 1d0d384..0000000 --- a/cpu/mpc8220/dramSetup.c +++ /dev/null @@ -1,754 +0,0 @@ -/* - * (C) Copyright 2004, Freescale, Inc - * TsiChung Liew, Tsi-Chung.Liew@freescale.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -DESCRIPTION -Read Dram spd and base on its information to calculate the memory size, -characteristics to initialize the dram on MPC8220 -*/ - -#include -#include -#include "i2cCore.h" -#include "dramSetup.h" - -#define SPD_SIZE CFG_SDRAM_SPD_SIZE -#define DRAM_SPD (CFG_SDRAM_SPD_I2C_ADDR)<<1 /* on Board SPD eeprom */ -#define TOTAL_BANK CFG_SDRAM_TOTAL_BANKS - -int spd_status (volatile i2c8220_t * pi2c, u8 sta_bit, u8 truefalse) -{ - int i; - - for (i = 0; i < I2C_POLL_COUNT; i++) { - if ((pi2c->sr & sta_bit) == (truefalse ? sta_bit : 0)) - return (OK); - } - - return (ERROR); -} - -int spd_clear (volatile i2c8220_t * pi2c) -{ - pi2c->adr = 0; - pi2c->fdr = 0; - pi2c->cr = 0; - pi2c->sr = 0; - - return (OK); -} - -int spd_stop (volatile i2c8220_t * pi2c) -{ - pi2c->cr &= ~I2C_CTL_STA; /* Generate stop signal */ - if (spd_status (pi2c, I2C_STA_BB, 0) != OK) - return ERROR; - - return (OK); -} - -int spd_readbyte (volatile i2c8220_t * pi2c, u8 * readb, int *index) -{ - pi2c->sr &= ~I2C_STA_IF; /* Clear Interrupt Bit */ - *readb = pi2c->dr; /* Read a byte */ - - /* - Set I2C_CTRL_TXAK will cause Transfer pending and - set I2C_CTRL_STA will cause Interrupt pending - */ - if (*index != 2) { - if (spd_status (pi2c, I2C_STA_CF, 1) != OK) /* Transfer not complete? */ - return ERROR; - } - - if (*index != 1) { - if (spd_status (pi2c, I2C_STA_IF, 1) != OK) - return ERROR; - } - - return (OK); -} - -int readSpdData (u8 * spdData) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile i2c8220_t *pi2cReg; - volatile pcfg8220_t *pcfg; - u8 slvAdr = DRAM_SPD; - u8 Tmp; - int Length = SPD_SIZE; - int i = 0; - - /* Enable Port Configuration for SDA and SDL signals */ - pcfg = (volatile pcfg8220_t *) (MMAP_PCFG); - __asm__ ("sync"); - pcfg->pcfg3 &= ~CFG_I2C_PORT3_CONFIG; - __asm__ ("sync"); - - /* Points the structure to I2c mbar memory offset */ - pi2cReg = (volatile i2c8220_t *) (MMAP_I2C); - - - /* Clear FDR, ADR, SR and CR reg */ - pi2cReg->adr = 0; - pi2cReg->fdr = 0; - pi2cReg->cr = 0; - pi2cReg->sr = 0; - - /* Set for fix XLB Bus Frequency */ - switch (gd->bus_clk) { - case 60000000: - pi2cReg->fdr = 0x15; - break; - case 70000000: - pi2cReg->fdr = 0x16; - break; - case 80000000: - pi2cReg->fdr = 0x3a; - break; - case 90000000: - pi2cReg->fdr = 0x17; - break; - case 100000000: - pi2cReg->fdr = 0x3b; - break; - case 110000000: - pi2cReg->fdr = 0x18; - break; - case 120000000: - pi2cReg->fdr = 0x19; - break; - case 130000000: - pi2cReg->fdr = 0x1a; - break; - } - - pi2cReg->adr = CFG_I2C_SLAVE<<1; - - pi2cReg->cr = I2C_CTL_EN; /* Set Enable */ - - /* - The I2C bus should be in Idle state. If the bus is busy, - clear the STA bit in control register - */ - if (spd_status (pi2cReg, I2C_STA_BB, 0) != OK) { - if ((pi2cReg->cr & I2C_CTL_STA) == I2C_CTL_STA) - pi2cReg->cr &= ~I2C_CTL_STA; - - /* Check again if it is still busy, return error if found */ - if (spd_status (pi2cReg, I2C_STA_BB, 1) == OK) - return ERROR; - } - - pi2cReg->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack */ - pi2cReg->cr |= I2C_CTL_STA; /* Generate start signal */ - - if (spd_status (pi2cReg, I2C_STA_BB, 1) != OK) - return ERROR; - - - /* Write slave address */ - pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */ - pi2cReg->dr = slvAdr; /* Write a byte */ - - if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */ - spd_stop (pi2cReg); - return ERROR; - } - - if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) { - spd_stop (pi2cReg); - return ERROR; - } - - - /* Issue the offset to start */ - pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */ - pi2cReg->dr = 0; /* Write a byte */ - - if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */ - spd_stop (pi2cReg); - return ERROR; - } - - if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) { - spd_stop (pi2cReg); - return ERROR; - } - - - /* Set repeat start */ - pi2cReg->cr |= I2C_CTL_RSTA; /* Repeat Start */ - - pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */ - pi2cReg->dr = slvAdr | 1; /* Write a byte */ - - if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */ - spd_stop (pi2cReg); - return ERROR; - } - - if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) { - spd_stop (pi2cReg); - return ERROR; - } - - if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01)) - return ERROR; - - pi2cReg->cr &= ~I2C_CTL_TX; /* Set receive mode */ - - if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01)) - return ERROR; - - /* Dummy Read */ - if (spd_readbyte (pi2cReg, &Tmp, &i) != OK) { - spd_stop (pi2cReg); - return ERROR; - } - - i = 0; - while (Length) { - if (Length == 2) - pi2cReg->cr |= I2C_CTL_TXAK; - - if (Length == 1) - pi2cReg->cr &= ~I2C_CTL_STA; - - if (spd_readbyte (pi2cReg, spdData, &Length) != OK) { - return spd_stop (pi2cReg); - } - i++; - Length--; - spdData++; - } - - /* Stop the service */ - spd_stop (pi2cReg); - - return OK; -} - -int getBankInfo (int bank, draminfo_t * pBank) -{ - int status; - int checksum; - int count; - u8 spdData[SPD_SIZE]; - - - if (bank > 2 || pBank == 0) { - /* illegal values */ - return (-42); - } - - status = readSpdData (&spdData[0]); - if (status < 0) - return (-1); - - /* check the checksum */ - for (count = 0, checksum = 0; count < LOC_CHECKSUM; count++) - checksum += spdData[count]; - - checksum = checksum - ((checksum / 256) * 256); - - if (checksum != spdData[LOC_CHECKSUM]) - return (-2); - - /* Get the memory type */ - if (! - ((spdData[LOC_TYPE] == TYPE_DDR) - || (spdData[LOC_TYPE] == TYPE_SDR))) - /* not one of the types we support */ - return (-3); - - pBank->type = spdData[LOC_TYPE]; - - /* Set logical banks */ - pBank->banks = spdData[LOC_LOGICAL_BANKS]; - - /* Check that we have enough physical banks to cover the bank we are - * figuring out. Odd-numbered banks correspond to the second bank - * on the device. - */ - if (bank & 1) { - /* Second bank of a "device" */ - if (spdData[LOC_PHYS_BANKS] < 2) - /* this bank doesn't exist on the "device" */ - return (-4); - - if (spdData[LOC_ROWS] & 0xf0) - /* Two asymmetric banks */ - pBank->rows = spdData[LOC_ROWS] >> 4; - else - pBank->rows = spdData[LOC_ROWS]; - - if (spdData[LOC_COLS] & 0xf0) - /* Two asymmetric banks */ - pBank->cols = spdData[LOC_COLS] >> 4; - else - pBank->cols = spdData[LOC_COLS]; - } else { - /* First bank of a "device" */ - pBank->rows = spdData[LOC_ROWS]; - pBank->cols = spdData[LOC_COLS]; - } - - pBank->width = spdData[LOC_WIDTH_HIGH] << 8 | spdData[LOC_WIDTH_LOW]; - pBank->bursts = spdData[LOC_BURSTS]; - pBank->CAS = spdData[LOC_CAS]; - pBank->CS = spdData[LOC_CS]; - pBank->WE = spdData[LOC_WE]; - pBank->Trp = spdData[LOC_Trp]; - pBank->Trcd = spdData[LOC_Trcd]; - pBank->buffered = spdData[LOC_Buffered] & 1; - pBank->refresh = spdData[LOC_REFRESH]; - - return (0); -} - - -/* checkMuxSetting -- given a row/column device geometry, return a mask - * of the valid DRAM controller addr_mux settings for - * that geometry. - * - * Arguments: u8 rows: number of row addresses in this device - * u8 columns: number of column addresses in this device - * - * Returns: a mask of the allowed addr_mux settings for this - * geometry. Each bit in the mask represents a - * possible addr_mux settings (for example, the - * (1<<2) bit in the mask represents the 0b10 setting)/ - * - */ -u8 checkMuxSetting (u8 rows, u8 columns) -{ - muxdesc_t *pIdx, *pMux; - u8 mask; - int lrows, lcolumns; - u32 mux[4] = { 0x00080c04, 0x01080d03, 0x02080e02, 0xffffffff }; - - /* Setup MuxDescriptor in SRAM space */ - /* MUXDESC AddressRuns [] = { - { 0, 8, 12, 4 }, / setting, columns, rows, extra columns / - { 1, 8, 13, 3 }, / setting, columns, rows, extra columns / - { 2, 8, 14, 2 }, / setting, columns, rows, extra columns / - { 0xff } / list terminator / - }; */ - - pIdx = (muxdesc_t *) & mux[0]; - - /* Check rows x columns against each possible address mux setting */ - for (pMux = pIdx, mask = 0;; pMux++) { - lrows = rows; - lcolumns = columns; - - if (pMux->MuxValue == 0xff) - break; /* end of list */ - - /* For a given mux setting, since we want all the memory in a - * device to be contiguous, we want the device "use up" the - * address lines such that there are no extra column or row - * address lines on the device. - */ - - lcolumns -= pMux->Columns; - if (lcolumns < 0) - /* Not enough columns to get to the rows */ - continue; - - lrows -= pMux->Rows; - if (lrows > 0) - /* we have extra rows left -- can't do that! */ - continue; - - /* At this point, we either have to have used up all the - * rows or we have to have no columns left. - */ - - if (lcolumns != 0 && lrows != 0) - /* rows AND columns are left. Bad! */ - continue; - - lcolumns -= pMux->MoreColumns; - - if (lcolumns <= 0) - mask |= (1 << pMux->MuxValue); - } - - return (mask); -} - - -u32 dramSetup (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - draminfo_t DramInfo[TOTAL_BANK]; - draminfo_t *pDramInfo; - u32 size, temp, cfg_value, mode_value, refresh; - u8 *ptr; - u8 bursts, Trp, Trcd, type, buffered; - u8 muxmask, rows, columns; - int count, banknum; - u32 *prefresh, *pIdx; - u32 refrate[8] = { 15625, 3900, 7800, 31300, - 62500, 125000, 0xffffffff, 0xffffffff - }; - volatile sysconf8220_t *sysconf; - volatile memctl8220_t *memctl; - - sysconf = (volatile sysconf8220_t *) MMAP_MBAR; - memctl = (volatile memctl8220_t *) MMAP_MEMCTL; - - /* Set everything in the descriptions to zero */ - ptr = (u8 *) & DramInfo[0]; - for (count = 0; count < sizeof (DramInfo); count++) - *ptr++ = 0; - - for (banknum = 0; banknum < TOTAL_BANK; banknum++) - sysconf->cscfg[banknum]; - - /* Descriptions of row/column address muxing for various - * addr_mux settings. - */ - - pIdx = prefresh = (u32 *) & refrate[0]; - - /* Get all the info for all three logical banks */ - bursts = 0xff; - Trp = 0; - Trcd = 0; - type = 0; - buffered = 0xff; - refresh = 0xffffffff; - muxmask = 0xff; - - /* Two bank, CS0 and CS1 */ - for (banknum = 0, pDramInfo = &DramInfo[0]; - banknum < TOTAL_BANK; banknum++, pDramInfo++) { - pDramInfo->ordinal = banknum; /* initial sorting */ - if (getBankInfo (banknum, pDramInfo) < 0) - continue; - - /* get cumulative parameters of all three banks */ - if (type && pDramInfo->type != type) - return 0; - - type = pDramInfo->type; - rows = pDramInfo->rows; - columns = pDramInfo->cols; - - /* This chip only supports 13 DRAM memory lines, but some devices - * have 14 rows. To deal with this, ignore the 14th address line - * by limiting the number of rows (and columns) to 13. This will - * mean that for 14-row devices we will only be able to use - * half of the memory, but it's better than nothing. - */ - if (rows > 13) - rows = 13; - if (columns > 13) - columns = 13; - - pDramInfo->size = - ((1 << (rows + columns)) * pDramInfo->width); - pDramInfo->size *= pDramInfo->banks; - pDramInfo->size >>= 3; - - /* figure out which addr_mux configurations will support this device */ - muxmask &= checkMuxSetting (rows, columns); - if (muxmask == 0) - return 0; - - buffered = pDramInfo->buffered; - bursts &= pDramInfo->bursts; /* union of all bursts */ - if (pDramInfo->Trp > Trp) /* worst case (longest) Trp */ - Trp = pDramInfo->Trp; - - if (pDramInfo->Trcd > Trcd) /* worst case (longest) Trcd */ - Trcd = pDramInfo->Trcd; - - prefresh = pIdx; - /* worst case (shortest) Refresh period */ - if (refresh > prefresh[pDramInfo->refresh & 7]) - refresh = prefresh[pDramInfo->refresh & 7]; - - } /* for loop */ - - - /* We only allow a burst length of 8! */ - if (!(bursts & 8)) - bursts = 8; - - /* Sort the devices. In order to get each chip select region - * aligned properly, put the biggest device at the lowest address. - * A simple bubble sort will do the trick. - */ - for (banknum = 0, pDramInfo = &DramInfo[0]; - banknum < TOTAL_BANK; banknum++, pDramInfo++) { - int i; - - for (i = 0; i < TOTAL_BANK; i++) { - if (pDramInfo->size < DramInfo[i].size && - pDramInfo->ordinal < DramInfo[i].ordinal) { - /* If the current bank is smaller, but if the ordinal is also - * smaller, swap the ordinals - */ - u8 temp8; - - temp8 = DramInfo[i].ordinal; - DramInfo[i].ordinal = pDramInfo->ordinal; - pDramInfo->ordinal = temp8; - } - } - } - - - /* Now figure out the base address for each bank. While - * we're at it, figure out how much memory there is. - * - */ - size = 0; - for (banknum = 0; banknum < TOTAL_BANK; banknum++) { - int i; - - for (i = 0; i < TOTAL_BANK; i++) { - if (DramInfo[i].ordinal == banknum - && DramInfo[i].size != 0) { - DramInfo[i].base = size; - size += DramInfo[i].size; - } - } - } - - /* Set up the Drive Strength register */ - sysconf->sdramds = CFG_SDRAM_DRIVE_STRENGTH; - - /* ********************** Cfg 1 ************************* */ - - /* Set the single read to read/write/precharge delay */ - cfg_value = CFG1_SRD2RWP ((type == TYPE_DDR) ? 7 : 0xb); - - /* Set the single write to read/write/precharge delay. - * This may or may not be correct. The controller spec - * says "tWR", but "tWR" does not appear in the SPD. It - * always seems to be 15nsec for the class of device we're - * using, which turns out to be 2 clock cycles at 133MHz, - * so that's what we're going to use. - * - * HOWEVER, because of a bug in the controller, for DDR - * we need to set this to be the same as the value - * calculated for bwt2rwp. - */ - cfg_value |= CFG1_SWT2RWP ((type == TYPE_DDR) ? 7 : 2); - - /* Set the Read CAS latency. We're going to use a CL of - * 2.5 for DDR and 2 SDR. - */ - cfg_value |= CFG1_RLATENCY ((type == TYPE_DDR) ? 7 : 2); - - - /* Set the Active to Read/Write delay. This depends - * on Trcd which is reported as nanoseconds times 4. - * We want to calculate Trcd (in nanoseconds) times XLB clock (in Hz) - * which gives us a dimensionless quantity. Play games with - * the divisions so we don't run out of dynamic ranges. - */ - /* account for megaherz and the times 4 */ - temp = (Trcd * (gd->bus_clk / 1000000)) / 4; - - /* account for nanoseconds and round up, with a minimum value of 2 */ - temp = ((temp + 999) / 1000) - 1; - if (temp < 2) - temp = 2; - - cfg_value |= CFG1_ACT2WR (temp); - - /* Set the precharge to active delay. This depends - * on Trp which is reported as nanoseconds times 4. - * We want to calculate Trp (in nanoseconds) times XLB clock (in Hz) - * which gives us a dimensionless quantity. Play games with - * the divisions so we don't run out of dynamic ranges. - */ - /* account for megaherz and the times 4 */ - temp = (Trp * (gd->bus_clk / 1000000)) / 4; - - /* account for nanoseconds and round up, then subtract 1, with a - * minumum value of 1 and a maximum value of 7. - */ - temp = (((temp + 999) / 1000) - 1) & 7; - if (temp < 1) - temp = 1; - - cfg_value |= CFG1_PRE2ACT (temp); - - /* Set refresh to active delay. This depends - * on Trfc which is not reported in the SPD. - * We'll use a nominal value of 75nsec which is - * what the controller spec uses. - */ - temp = (75 * (gd->bus_clk / 1000000)); - /* account for nanoseconds and round up, then subtract 1 */ - cfg_value |= CFG1_REF2ACT (((temp + 999) / 1000) - 1); - - /* Set the write latency, using the values given in the controller spec */ - cfg_value |= CFG1_WLATENCY ((type == TYPE_DDR) ? 3 : 0); - memctl->cfg1 = cfg_value; /* cfg 1 */ - asm volatile ("sync"); - - - /* ********************** Cfg 2 ************************* */ - - /* Set the burst read to read/precharge delay */ - cfg_value = CFG2_BRD2RP ((type == TYPE_DDR) ? 5 : 8); - - /* Set the burst write to read/precharge delay. Semi-magic numbers - * based on the controller spec recommendations, assuming tWR is - * two clock cycles. - */ - cfg_value |= CFG2_BWT2RWP ((type == TYPE_DDR) ? 7 : 10); - - /* Set the Burst read to write delay. Semi-magic numbers - * based on the DRAM controller documentation. - */ - cfg_value |= CFG2_BRD2WT ((type == TYPE_DDR) ? 7 : 0xb); - - /* Set the burst length -- must be 8!! Well, 7, actually, becuase - * it's burst lenght minus 1. - */ - cfg_value |= CFG2_BURSTLEN (7); - memctl->cfg2 = cfg_value; /* cfg 2 */ - asm volatile ("sync"); - - - /* ********************** mode ************************* */ - - /* Set enable bit, CKE high/low bits, and the DDR/SDR mode bit, - * disable automatic refresh. - */ - cfg_value = CTL_MODE_ENABLE | CTL_CKE_HIGH | - ((type == TYPE_DDR) ? CTL_DDR_MODE : 0); - - /* Set the address mux based on whichever setting(s) is/are common - * to all the devices we have. If there is more than one, choose - * one arbitrarily. - */ - if (muxmask & 0x4) - cfg_value |= CTL_ADDRMUX (2); - else if (muxmask & 0x2) - cfg_value |= CTL_ADDRMUX (1); - else - cfg_value |= CTL_ADDRMUX (0); - - /* Set the refresh interval. */ - temp = ((refresh * (gd->bus_clk / 1000000)) / (1000 * 64)) - 1; - cfg_value |= CTL_REFRESH_INTERVAL (temp); - - /* Set buffered/non-buffered memory */ - if (buffered) - cfg_value |= CTL_BUFFERED; - - memctl->ctrl = cfg_value; /* ctrl */ - asm volatile ("sync"); - - if (type == TYPE_DDR) { - /* issue precharge all */ - temp = cfg_value | CTL_PRECHARGE_CMD; - memctl->ctrl = temp; /* ctrl */ - asm volatile ("sync"); - } - - - /* Set up mode value for CAS latency */ -#if (CFG_SDRAM_CAS_LATENCY==5) /* CL=2.5 */ - mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) | - MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2p5) | MODE_CMD); -#else - mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) | - MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2) | MODE_CMD); -#endif - asm volatile ("sync"); - - /* Write Extended Mode - enable DLL */ - if (type == TYPE_DDR) { - temp = MODE_EXTENDED | MODE_X_DLL_ENABLE | - MODE_X_DS_NORMAL | MODE_CMD; - memctl->mode = (temp >> 16); /* mode */ - asm volatile ("sync"); - - /* Write Mode - reset DLL, set CAS latency */ - temp = mode_value | MODE_OPMODE (MODE_OPMODE_RESETDLL); - memctl->mode = (temp >> 16); /* mode */ - asm volatile ("sync"); - } - - /* Program the chip selects. */ - for (banknum = 0; banknum < TOTAL_BANK; banknum++) { - if (DramInfo[banknum].size != 0) { - u32 mask; - int i; - - for (i = 0, mask = 1; i < 32; mask <<= 1, i++) { - if (DramInfo[banknum].size & mask) - break; - } - temp = (DramInfo[banknum].base & 0xfff00000) | (i - - 1); - - sysconf->cscfg[banknum] = temp; - asm volatile ("sync"); - } - } - - /* Wait for DLL lock */ - udelay (200); - - temp = cfg_value | CTL_PRECHARGE_CMD; /* issue precharge all */ - memctl->ctrl = temp; /* ctrl */ - asm volatile ("sync"); - - temp = cfg_value | CTL_REFRESH_CMD; /* issue precharge all */ - memctl->ctrl = temp; /* ctrl */ - asm volatile ("sync"); - - memctl->ctrl = temp; /* ctrl */ - asm volatile ("sync"); - - /* Write Mode - DLL normal */ - temp = mode_value | MODE_OPMODE (MODE_OPMODE_NORMAL); - memctl->mode = (temp >> 16); /* mode */ - asm volatile ("sync"); - - /* Enable refresh, enable DQS's (if DDR), and lock the control register */ - cfg_value &= ~CTL_MODE_ENABLE; /* lock register */ - cfg_value |= CTL_REFRESH_ENABLE; /* enable refresh */ - - if (type == TYPE_DDR) - cfg_value |= CTL_DQSOEN (0xf); /* enable DQS's for DDR */ - - memctl->ctrl = cfg_value; /* ctrl */ - asm volatile ("sync"); - - return size; -} diff --git a/cpu/mpc8220/dramSetup.h b/cpu/mpc8220/dramSetup.h deleted file mode 100644 index 3b64e08..0000000 --- a/cpu/mpc8220/dramSetup.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * dramSetup.h - * - * Prototypes, etc. for the Motorola MPC8220 - * embedded cpu chips - * - * 2004 (c) Freescale, Inc. - * Author: TsiChung Liew - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __INCdramsetuph -#define __INCdramsetuph -#ifndef __ASSEMBLY__ -/* Where various things are in the SPD */ -#define LOC_TYPE 2 -#define LOC_CHECKSUM 63 -#define LOC_PHYS_BANKS 5 -#define LOC_LOGICAL_BANKS 17 -#define LOC_ROWS 3 -#define LOC_COLS 4 -#define LOC_WIDTH_HIGH 7 -#define LOC_WIDTH_LOW 6 -#define LOC_REFRESH 12 -#define LOC_BURSTS 16 -#define LOC_CAS 18 -#define LOC_CS 19 -#define LOC_WE 20 -#define LOC_Tcyc 9 -#define LOC_Tac 10 -#define LOC_Trp 27 -#define LOC_Trrd 28 -#define LOC_Trcd 29 -#define LOC_Tras 30 -#define LOC_Buffered 21 -/* Types of memory the SPD can tell us about. - * We can actually only use SDRAM and DDR. - */ -#define TYPE_DRAM 1 /* plain old dram */ -#define TYPE_EDO 2 /* EDO dram */ -#define TYPE_Nibble 3 /* serial nibble memory */ -#define TYPE_SDR 4 /* SDRAM */ -#define TYPE_ROM 5 /* */ -#define TYPE_SGRRAM 6 /* graphics memory */ -#define TYPE_DDR 7 /* DDR sdram */ -#define SDRAMDS_MASK 0x3 /* each field is 2 bits wide */ -#define SDRAMDS_SBE_SHIFT 8 /* Clock enable drive strength */ -#define SDRAMDS_SBC_SHIFT 6 /* Clocks drive strength */ -#define SDRAMDS_SBA_SHIFT 4 /* Address drive strength */ -#define SDRAMDS_SBS_SHIFT 2 /* SDR DQS drive strength */ -#define SDRAMDS_SBD_SHIFT 0 /* Data and DQS drive strength */ -#define DRIVE_STRENGTH_HIGH 0 -#define DRIVE_STRENGTH_MED 1 -#define DRIVE_STRENGTH_LOW 2 -#define DRIVE_STRENGTH_OFF 3 - -#define OK 0 -#define ERROR -1 -/* Structure to hold information about address muxing. */ - typedef struct tagMuxDescriptor { - u8 MuxValue; - u8 Columns; - u8 Rows; - u8 MoreColumns; -} muxdesc_t; - -/* Structure to define one physical bank of - * memory. Note that dram size in bytes is - * (2^^(rows+columns)) * width * banks / 8 -*/ -typedef struct tagDramInfo { - u32 size; /* size in bytes */ - u32 base; /* base address */ - u8 ordinal; /* where in the memory map will we put this */ - u8 type; - u8 rows; - u8 cols; - u16 width; /* width of each chip in bits */ - u8 banks; /* number of chips, aka logical banks */ - u8 bursts; /* bit-encoded allowable burst length */ - u8 CAS; /* bit-encoded CAS latency values */ - u8 CS; /* bit-encoded CS latency values */ - u8 WE; /* bit-encoded WE latency values */ - u8 Trp; /* bit-encoded row precharge time */ - u8 Trcd; /* bit-encoded RAS to CAS delay */ - u8 buffered; /* buffered or not */ - u8 refresh; /* encoded refresh rate */ -} draminfo_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __INCdramsetuph */ diff --git a/cpu/mpc8220/fec.c b/cpu/mpc8220/fec.c deleted file mode 100644 index 1201e79..0000000 --- a/cpu/mpc8220/fec.c +++ /dev/null @@ -1,1000 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on mpc4200fec.c, - * (C) Copyright Motorola, Inc., 2000 - */ - -#include -#include -#include -#include -#include -#include "dma.h" -#include "fec.h" - -#undef DEBUG -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ - defined(CONFIG_MPC8220_FEC) - -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) -#error "CONFIG_MII has to be defined!" -#endif - -#ifdef DEBUG -static void tfifo_print (char *devname, mpc8220_fec_priv * fec); -static void rfifo_print (char *devname, mpc8220_fec_priv * fec); -#endif /* DEBUG */ - -#ifdef DEBUG -static u32 local_crc32 (char *string, unsigned int crc_value, int len); -#endif - -typedef struct { - u8 data[1500]; /* actual data */ - int length; /* actual length */ - int used; /* buffer in use or not */ - u8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */ -} NBUF; - -int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal); -int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data); - -/********************************************************************/ -#ifdef DEBUG -static void mpc8220_fec_phydump (char *devname) -{ - u16 phyStatus, i; - u8 phyAddr = CONFIG_PHY_ADDR; - u8 reg_mask[] = { -#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */ - /* regs to print: 0...7, 16...19, 21, 23, 24 */ - 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, -#else - /* regs to print: 0...8, 16...20 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -#endif - }; - - for (i = 0; i < 32; i++) { - if (reg_mask[i]) { - miiphy_read (devname, phyAddr, i, &phyStatus); - printf ("Mii reg %d: 0x%04x\n", i, phyStatus); - } - } -} -#endif - -/********************************************************************/ -static int mpc8220_fec_rbd_init (mpc8220_fec_priv * fec) -{ - int ix; - char *data; - static int once = 0; - - for (ix = 0; ix < FEC_RBD_NUM; ix++) { - if (!once) { - data = (char *) malloc (FEC_MAX_PKT_SIZE); - if (data == NULL) { - printf ("RBD INIT FAILED\n"); - return -1; - } - fec->rbdBase[ix].dataPointer = (u32) data; - } - fec->rbdBase[ix].status = FEC_RBD_EMPTY; - fec->rbdBase[ix].dataLength = 0; - } - once++; - - /* - * have the last RBD to close the ring - */ - fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP; - fec->rbdIndex = 0; - - return 0; -} - -/********************************************************************/ -static void mpc8220_fec_tbd_init (mpc8220_fec_priv * fec) -{ - int ix; - - for (ix = 0; ix < FEC_TBD_NUM; ix++) { - fec->tbdBase[ix].status = 0; - } - - /* - * Have the last TBD to close the ring - */ - fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP; - - /* - * Initialize some indices - */ - fec->tbdIndex = 0; - fec->usedTbdIndex = 0; - fec->cleanTbdNum = FEC_TBD_NUM; -} - -/********************************************************************/ -static void mpc8220_fec_rbd_clean (mpc8220_fec_priv * fec, FEC_RBD * pRbd) -{ - /* - * Reset buffer descriptor as empty - */ - if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) - pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); - else - pRbd->status = FEC_RBD_EMPTY; - - pRbd->dataLength = 0; - - /* - * Now, we have an empty RxBD, restart the SmartDMA receive task - */ - DMA_TASK_ENABLE (FEC_RECV_TASK_NO); - - /* - * Increment BD count - */ - fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; -} - -/********************************************************************/ -static void mpc8220_fec_tbd_scrub (mpc8220_fec_priv * fec) -{ - FEC_TBD *pUsedTbd; - -#ifdef DEBUG - printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", - fec->cleanTbdNum, fec->usedTbdIndex); -#endif - - /* - * process all the consumed TBDs - */ - while (fec->cleanTbdNum < FEC_TBD_NUM) { - pUsedTbd = &fec->tbdBase[fec->usedTbdIndex]; - if (pUsedTbd->status & FEC_TBD_READY) { -#ifdef DEBUG - printf ("Cannot clean TBD %d, in use\n", - fec->cleanTbdNum); -#endif - return; - } - - /* - * clean this buffer descriptor - */ - if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) - pUsedTbd->status = FEC_TBD_WRAP; - else - pUsedTbd->status = 0; - - /* - * update some indeces for a correct handling of the TBD ring - */ - fec->cleanTbdNum++; - fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; - } -} - -/********************************************************************/ -static void mpc8220_fec_set_hwaddr (mpc8220_fec_priv * fec, char *mac) -{ - u8 currByte; /* byte for which to compute the CRC */ - int byte; /* loop - counter */ - int bit; /* loop - counter */ - u32 crc = 0xffffffff; /* initial value */ - - /* - * The algorithm used is the following: - * we loop on each of the six bytes of the provided address, - * and we compute the CRC by left-shifting the previous - * value by one position, so that each bit in the current - * byte of the address may contribute the calculation. If - * the latter and the MSB in the CRC are different, then - * the CRC value so computed is also ex-ored with the - * "polynomium generator". The current byte of the address - * is also shifted right by one bit at each iteration. - * This is because the CRC generatore in hardware is implemented - * as a shift-register with as many ex-ores as the radixes - * in the polynomium. This suggests that we represent the - * polynomiumm itself as a 32-bit constant. - */ - for (byte = 0; byte < 6; byte++) { - currByte = mac[byte]; - for (bit = 0; bit < 8; bit++) { - if ((currByte & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - currByte >>= 1; - } - } - - crc = crc >> 26; - - /* - * Set individual hash table register - */ - if (crc >= 32) { - fec->eth->iaddr1 = (1 << (crc - 32)); - fec->eth->iaddr2 = 0; - } else { - fec->eth->iaddr1 = 0; - fec->eth->iaddr2 = (1 << crc); - } - - /* - * Set physical address - */ - fec->eth->paddr1 = - (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; - fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808; -} - -/********************************************************************/ -static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis) -{ - mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv; - struct mpc8220_dma *dma = (struct mpc8220_dma *) MMAP_DMA; - const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ - -#ifdef DEBUG - printf ("mpc8220_fec_init... Begin\n"); -#endif - - /* - * Initialize RxBD/TxBD rings - */ - mpc8220_fec_rbd_init (fec); - mpc8220_fec_tbd_init (fec); - - /* - * Set up Pin Muxing for FEC 1 - */ - *(vu_long *) MMAP_PCFG = 0; - *(vu_long *) (MMAP_PCFG + 4) = 0; - /* - * Clear FEC-Lite interrupt event register(IEVENT) - */ - fec->eth->ievent = 0xffffffff; - - /* - * Set interrupt mask register - */ - fec->eth->imask = 0x00000000; - - /* - * Set FEC-Lite receive control register(R_CNTRL): - */ - if (fec->xcv_type == SEVENWIRE) { - /* - * Frame length=1518; 7-wire mode - */ - fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */ - } else { - /* - * Frame length=1518; MII mode; - */ - fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */ - } - - fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */ - if (fec->xcv_type != SEVENWIRE) { - /* - * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock - * and do not drop the Preamble. - */ - /* tbd - rtm */ - /*fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); */ - /* No MII for 7-wire mode */ - fec->eth->mii_speed = 0x00000030; - } - - /* - * Set Opcode/Pause Duration Register - */ - fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */ - - /* - * Set Rx FIFO alarm and granularity value - */ - fec->eth->rfifo_cntrl = 0x0c000000; - fec->eth->rfifo_alarm = 0x0000030c; -#ifdef DEBUG - if (fec->eth->rfifo_status & 0x00700000) { - printf ("mpc8220_fec_init() RFIFO error\n"); - } -#endif - - /* - * Set Tx FIFO granularity value - */ - /*fec->eth->tfifo_cntrl = 0x0c000000; */ /*tbd - rtm */ - fec->eth->tfifo_cntrl = 0x0e000000; -#ifdef DEBUG - printf ("tfifo_status: 0x%08x\n", fec->eth->tfifo_status); - printf ("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm); -#endif - - /* - * Set transmit fifo watermark register(X_WMRK), default = 64 - */ - fec->eth->tfifo_alarm = 0x00000080; - fec->eth->x_wmrk = 0x2; - - /* - * Set individual address filter for unicast address - * and set physical address registers. - */ - mpc8220_fec_set_hwaddr (fec, (char *)(dev->enetaddr)); - - /* - * Set multicast address filter - */ - fec->eth->gaddr1 = 0x00000000; - fec->eth->gaddr2 = 0x00000000; - - /* - * Turn ON cheater FSM: ???? - */ - fec->eth->xmit_fsm = 0x03000000; - -#if 1 -/*#if defined(CONFIG_MPC5200)*/ - /* - * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't - * work w/ the current receive task. - */ - dma->PtdCntrl |= 0x00000001; -#endif - - /* - * Set priority of different initiators - */ - dma->IPR0 = 7; /* always */ - dma->IPR3 = 6; /* Eth RX */ - dma->IPR4 = 5; /* Eth Tx */ - - /* - * Clear SmartDMA task interrupt pending bits - */ - DMA_CLEAR_IEVENT (FEC_RECV_TASK_NO); - - /* - * Initialize SmartDMA parameters stored in SRAM - */ - *(int *) FEC_TBD_BASE = (int) fec->tbdBase; - *(int *) FEC_RBD_BASE = (int) fec->rbdBase; - *(int *) FEC_TBD_NEXT = (int) fec->tbdBase; - *(int *) FEC_RBD_NEXT = (int) fec->rbdBase; - - if (fec->xcv_type != SEVENWIRE) { - /* - * Initialize PHY(LXT971A): - * - * Generally, on power up, the LXT971A reads its configuration - * pins to check for forced operation, If not cofigured for - * forced operation, it uses auto-negotiation/parallel detection - * to automatically determine line operating conditions. - * If the PHY device on the other side of the link supports - * auto-negotiation, the LXT971A auto-negotiates with it - * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not - * support auto-negotiation, the LXT971A automatically detects - * the presence of either link pulses(10Mbps PHY) or Idle - * symbols(100Mbps) and sets its operating conditions accordingly. - * - * When auto-negotiation is controlled by software, the following - * steps are recommended. - * - * Note: - * The physical address is dependent on hardware configuration. - * - */ - int timeout = 1; - u16 phyStatus; - - /* - * Reset PHY, then delay 300ns - */ - miiphy_write (dev->name, phyAddr, 0x0, 0x8000); - udelay (1000); - - if (fec->xcv_type == MII10) { - /* - * Force 10Base-T, FDX operation - */ -#ifdef DEBUG - printf ("Forcing 10 Mbps ethernet link... "); -#endif - miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); - /* - miiphy_write(fec, phyAddr, 0x0, 0x0100); - */ - miiphy_write (dev->name, phyAddr, 0x0, 0x0180); - - timeout = 20; - do { /* wait for link status to go down */ - udelay (10000); - if ((timeout--) == 0) { -#ifdef DEBUG - printf ("hmmm, should not have waited..."); -#endif - break; - } - miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); -#ifdef DEBUG - printf ("="); -#endif - } while ((phyStatus & 0x0004)); /* !link up */ - - timeout = 1000; - do { /* wait for link status to come back up */ - udelay (10000); - if ((timeout--) == 0) { - printf ("failed. Link is down.\n"); - break; - } - miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); -#ifdef DEBUG - printf ("+"); -#endif - } while (!(phyStatus & 0x0004)); /* !link up */ - -#ifdef DEBUG - printf ("done.\n"); -#endif - } else { /* MII100 */ - /* - * Set the auto-negotiation advertisement register bits - */ - miiphy_write (dev->name, phyAddr, 0x4, 0x01e1); - - /* - * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation - */ - miiphy_write (dev->name, phyAddr, 0x0, 0x1200); - - /* - * Wait for AN completion - */ - timeout = 5000; - do { - udelay (1000); - - if ((timeout--) == 0) { -#ifdef DEBUG - printf ("PHY auto neg 0 failed...\n"); -#endif - return -1; - } - - if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != - 0) { -#ifdef DEBUG - printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus); -#endif - return -1; - } - } while (!(phyStatus & 0x0004)); - -#ifdef DEBUG - printf ("PHY auto neg complete! \n"); -#endif - } - - } - - /* - * Enable FEC-Lite controller - */ - fec->eth->ecntrl |= 0x00000006; - -#ifdef DEBUG - if (fec->xcv_type != SEVENWIRE) - mpc8220_fec_phydump (dev->name); -#endif - - /* - * Enable SmartDMA receive task - */ - DMA_TASK_ENABLE (FEC_RECV_TASK_NO); - -#ifdef DEBUG - printf ("mpc8220_fec_init... Done \n"); -#endif - - return 1; -} - -/********************************************************************/ -static void mpc8220_fec_halt (struct eth_device *dev) -{ - mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv; - int counter = 0xffff; - -#ifdef DEBUG - if (fec->xcv_type != SEVENWIRE) - mpc8220_fec_phydump (dev->name); -#endif - - /* - * mask FEC chip interrupts - */ - fec->eth->imask = 0; - - /* - * issue graceful stop command to the FEC transmitter if necessary - */ - fec->eth->x_cntrl |= 0x00000001; - - /* - * wait for graceful stop to register - */ - while ((counter--) && (!(fec->eth->ievent & 0x10000000))); - - /* - * Disable SmartDMA tasks - */ - DMA_TASK_DISABLE (FEC_XMIT_TASK_NO); - DMA_TASK_DISABLE (FEC_RECV_TASK_NO); - - /* - * Disable the Ethernet Controller - */ - fec->eth->ecntrl &= 0xfffffffd; - - /* - * Clear FIFO status registers - */ - fec->eth->rfifo_status &= 0x00700000; - fec->eth->tfifo_status &= 0x00700000; - - fec->eth->reset_cntrl = 0x01000000; - - /* - * Issue a reset command to the FEC chip - */ - fec->eth->ecntrl |= 0x1; - - /* - * wait at least 16 clock cycles - */ - udelay (10); - -#ifdef DEBUG - printf ("Ethernet task stopped\n"); -#endif -} - -#ifdef DEBUG -/********************************************************************/ - -static void tfifo_print (char *devname, mpc8220_fec_priv * fec) -{ - u16 phyAddr = CONFIG_PHY_ADDR; - u16 phyStatus; - - if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr) - || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) { - - miiphy_read (devname, phyAddr, 0x1, &phyStatus); - printf ("\nphyStatus: 0x%04x\n", phyStatus); - printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl); - printf ("ievent: 0x%08x\n", fec->eth->ievent); - printf ("x_status: 0x%08x\n", fec->eth->x_status); - printf ("tfifo: status 0x%08x\n", fec->eth->tfifo_status); - - printf (" control 0x%08x\n", fec->eth->tfifo_cntrl); - printf (" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr); - printf (" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr); - printf (" alarm 0x%08x\n", fec->eth->tfifo_alarm); - printf (" readptr 0x%08x\n", fec->eth->tfifo_rdptr); - printf (" writptr 0x%08x\n", fec->eth->tfifo_wrptr); - } -} - -static void rfifo_print (char *devname, mpc8220_fec_priv * fec) -{ - u16 phyAddr = CONFIG_PHY_ADDR; - u16 phyStatus; - - if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr) - || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) { - - miiphy_read (devname, phyAddr, 0x1, &phyStatus); - printf ("\nphyStatus: 0x%04x\n", phyStatus); - printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl); - printf ("ievent: 0x%08x\n", fec->eth->ievent); - printf ("x_status: 0x%08x\n", fec->eth->x_status); - printf ("rfifo: status 0x%08x\n", fec->eth->rfifo_status); - - printf (" control 0x%08x\n", fec->eth->rfifo_cntrl); - printf (" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr); - printf (" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr); - printf (" alarm 0x%08x\n", fec->eth->rfifo_alarm); - printf (" readptr 0x%08x\n", fec->eth->rfifo_rdptr); - printf (" writptr 0x%08x\n", fec->eth->rfifo_wrptr); - } -} -#endif /* DEBUG */ - -/********************************************************************/ - -static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data, - int data_length) -{ - /* - * This routine transmits one frame. This routine only accepts - * 6-byte Ethernet addresses. - */ - mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv; - FEC_TBD *pTbd; - -#ifdef DEBUG - printf ("tbd status: 0x%04x\n", fec->tbdBase[0].status); - tfifo_print (dev->name, fec); -#endif - - /* - * Clear Tx BD ring at first - */ - mpc8220_fec_tbd_scrub (fec); - - /* - * Check for valid length of data. - */ - if ((data_length > 1500) || (data_length <= 0)) { - return -1; - } - - /* - * Check the number of vacant TxBDs. - */ - if (fec->cleanTbdNum < 1) { -#ifdef DEBUG - printf ("No available TxBDs ...\n"); -#endif - return -1; - } - - /* - * Get the first TxBD to send the mac header - */ - pTbd = &fec->tbdBase[fec->tbdIndex]; - pTbd->dataLength = data_length; - pTbd->dataPointer = (u32) eth_data; - pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; - fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; - -#ifdef DEBUG - printf ("DMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex); -#endif - - /* - * Kick the MII i/f - */ - if (fec->xcv_type != SEVENWIRE) { - u16 phyStatus; - - miiphy_read (dev->name, 0, 0x1, &phyStatus); - } - - /* - * Enable SmartDMA transmit task - */ - -#ifdef DEBUG - tfifo_print (dev->name, fec); -#endif - - DMA_TASK_ENABLE (FEC_XMIT_TASK_NO); - -#ifdef DEBUG - tfifo_print (dev->name, fec); -#endif - -#ifdef DEBUG - printf ("+"); -#endif - - fec->cleanTbdNum -= 1; - -#ifdef DEBUG - printf ("smartDMA ethernet Tx task enabled\n"); -#endif - /* - * wait until frame is sent . - */ - while (pTbd->status & FEC_TBD_READY) { - udelay (10); -#ifdef DEBUG - printf ("TDB status = %04x\n", pTbd->status); -#endif - } - - return 0; -} - - -/********************************************************************/ -static int mpc8220_fec_recv (struct eth_device *dev) -{ - /* - * This command pulls one frame from the card - */ - mpc8220_fec_priv *fec = (mpc8220_fec_priv *) dev->priv; - FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex]; - unsigned long ievent; - int frame_length, len = 0; - NBUF *frame; - -#ifdef DEBUG - printf ("mpc8220_fec_recv %d Start...\n", fec->rbdIndex); - printf ("-"); -#endif - - /* - * Check if any critical events have happened - */ - ievent = fec->eth->ievent; - fec->eth->ievent = ievent; - if (ievent & 0x20060000) { - /* BABT, Rx/Tx FIFO errors */ - mpc8220_fec_halt (dev); - mpc8220_fec_init (dev, NULL); - return 0; - } - if (ievent & 0x80000000) { - /* Heartbeat error */ - fec->eth->x_cntrl |= 0x00000001; - } - if (ievent & 0x10000000) { - /* Graceful stop complete */ - if (fec->eth->x_cntrl & 0x00000001) { - mpc8220_fec_halt (dev); - fec->eth->x_cntrl &= ~0x00000001; - mpc8220_fec_init (dev, NULL); - } - } - - if (!(pRbd->status & FEC_RBD_EMPTY)) { - if ((pRbd->status & FEC_RBD_LAST) - && !(pRbd->status & FEC_RBD_ERR) - && ((pRbd->dataLength - 4) > 14)) { - - /* - * Get buffer address and size - */ - frame = (NBUF *) pRbd->dataPointer; - frame_length = pRbd->dataLength - 4; - -#if (0) - { - int i; - - printf ("recv data hdr:"); - for (i = 0; i < 14; i++) - printf ("%x ", *(frame->head + i)); - printf ("\n"); - } -#endif - /* - * Fill the buffer and pass it to upper layers - */ -/* memcpy(buff, frame->head, 14); - memcpy(buff + 14, frame->data, frame_length);*/ - NetReceive ((volatile uchar *) pRbd->dataPointer, - frame_length); - len = frame_length; - } - /* - * Reset buffer descriptor as empty - */ - mpc8220_fec_rbd_clean (fec, pRbd); - } - DMA_CLEAR_IEVENT (FEC_RECV_TASK_NO); - return len; -} - - -/********************************************************************/ -int mpc8220_fec_initialize (bd_t * bis) -{ - mpc8220_fec_priv *fec; - -#ifdef CONFIG_HAS_ETH1 - mpc8220_fec_priv *fec2; -#endif - struct eth_device *dev; - char *tmp, *end; - char env_enetaddr[6]; - -#ifdef CONFIG_HAS_ETH1 - char env_enet1addr[6]; -#endif - int i; - - fec = (mpc8220_fec_priv *) malloc (sizeof (*fec)); - dev = (struct eth_device *) malloc (sizeof (*dev)); - memset (dev, 0, sizeof *dev); - - fec->eth = (ethernet_regs *) MMAP_FEC1; -#ifdef CONFIG_HAS_ETH1 - fec2 = (mpc8220_fec_priv *) malloc (sizeof (*fec)); - fec2->eth = (ethernet_regs *) MMAP_FEC2; -#endif - fec->tbdBase = (FEC_TBD *) FEC_BD_BASE; - fec->rbdBase = - (FEC_RBD *) (FEC_BD_BASE + FEC_TBD_NUM * sizeof (FEC_TBD)); - fec->xcv_type = MII100; - - dev->priv = (void *) fec; - dev->iobase = MMAP_FEC1; - dev->init = mpc8220_fec_init; - dev->halt = mpc8220_fec_halt; - dev->send = mpc8220_fec_send; - dev->recv = mpc8220_fec_recv; - - sprintf (dev->name, "FEC ETHERNET"); - eth_register (dev); - -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) - miiphy_register (dev->name, - fec8220_miiphy_read, fec8220_miiphy_write); -#endif - - /* - * Try to set the mac address now. The fec mac address is - * a garbage after reset. When not using fec for booting - * the Linux fec driver will try to work with this garbage. - */ - tmp = getenv ("ethaddr"); - if (tmp) { - for (i = 0; i < 6; i++) { - env_enetaddr[i] = - tmp ? simple_strtoul (tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end + 1 : end; - } - mpc8220_fec_set_hwaddr (fec, env_enetaddr); - } -#ifdef CONFIG_HAS_ETH1 - tmp = getenv ("eth1addr"); - if (tmp) { - for (i = 0; i < 6; i++) { - env_enet1addr[i] = - tmp ? simple_strtoul (tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end + 1 : end; - } - mpc8220_fec_set_hwaddr (fec2, env_enet1addr); - } -#endif - - return 1; -} - -/* MII-interface related functions */ -/********************************************************************/ -int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal) -{ - ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1; - u32 reg; /* convenient holder for the PHY register */ - u32 phy; /* convenient holder for the PHY */ - int timeout = 0xffff; - - /* - * reading from any PHY's register is done by properly - * programming the FEC's MII data register. - */ - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; - - eth->mii_data = - (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy - | reg); - - /* - * wait for the related interrupt - */ - while ((timeout--) && (!(eth->ievent & 0x00800000))); - - if (timeout == 0) { -#ifdef DEBUG - printf ("Read MDIO failed...\n"); -#endif - return -1; - } - - /* - * clear mii interrupt bit - */ - eth->ievent = 0x00800000; - - /* - * it's now safe to read the PHY's register - */ - *retVal = (u16) eth->mii_data; - - return 0; -} - -/********************************************************************/ -int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data) -{ - ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1; - u32 reg; /* convenient holder for the PHY register */ - u32 phy; /* convenient holder for the PHY */ - int timeout = 0xffff; - - reg = regAddr << FEC_MII_DATA_RA_SHIFT; - phy = phyAddr << FEC_MII_DATA_PA_SHIFT; - - eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | - FEC_MII_DATA_TA | phy | reg | data); - - /* - * wait for the MII interrupt - */ - while ((timeout--) && (!(eth->ievent & 0x00800000))); - - if (timeout == 0) { -#ifdef DEBUG - printf ("Write MDIO failed...\n"); -#endif - return -1; - } - - /* - * clear MII interrupt bit - */ - eth->ievent = 0x00800000; - - return 0; -} - -#ifdef DEBUG -static u32 local_crc32 (char *string, unsigned int crc_value, int len) -{ - int i; - char c; - unsigned int crc, count; - - /* - * crc32 algorithm - */ - /* - * crc = 0xffffffff; * The initialized value should be 0xffffffff - */ - crc = crc_value; - - for (i = len; --i >= 0;) { - c = *string++; - for (count = 0; count < 8; count++) { - if ((c & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - c >>= 1; - } - } - - /* - * In big endian system, do byte swaping for crc value - */ - return crc; -} -#endif /* DEBUG */ - -#endif /* CONFIG_MPC8220_FEC */ diff --git a/cpu/mpc8220/fec.h b/cpu/mpc8220/fec.h deleted file mode 100644 index a8927fc..0000000 --- a/cpu/mpc8220/fec.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on mpc4200fec.h - * (C) Copyright Motorola, Inc., 2000 - * - * odin ethernet header file - */ - -#ifndef __MPC8220_FEC_H -#define __MPC8220_FEC_H - -#include -#include -#include "dma.h" - -typedef struct ethernet_register_set { - -/* [10:2]addr = 00 */ - -/* Control and status Registers (offset 000-1FF) */ - - volatile u32 fec_id; /* MBAR_ETH + 0x000 */ - volatile u32 ievent; /* MBAR_ETH + 0x004 */ - volatile u32 imask; /* MBAR_ETH + 0x008 */ - - volatile u32 RES0[1]; /* MBAR_ETH + 0x00C */ - volatile u32 r_des_active; /* MBAR_ETH + 0x010 */ - volatile u32 x_des_active; /* MBAR_ETH + 0x014 */ - volatile u32 r_des_active_cl; /* MBAR_ETH + 0x018 */ - volatile u32 x_des_active_cl; /* MBAR_ETH + 0x01C */ - volatile u32 ivent_set; /* MBAR_ETH + 0x020 */ - volatile u32 ecntrl; /* MBAR_ETH + 0x024 */ - - volatile u32 RES1[6]; /* MBAR_ETH + 0x028-03C */ - volatile u32 mii_data; /* MBAR_ETH + 0x040 */ - volatile u32 mii_speed; /* MBAR_ETH + 0x044 */ - volatile u32 mii_status; /* MBAR_ETH + 0x048 */ - - volatile u32 RES2[5]; /* MBAR_ETH + 0x04C-05C */ - volatile u32 mib_data; /* MBAR_ETH + 0x060 */ - volatile u32 mib_control; /* MBAR_ETH + 0x064 */ - - volatile u32 RES3[6]; /* MBAR_ETH + 0x068-7C */ - volatile u32 r_activate; /* MBAR_ETH + 0x080 */ - volatile u32 r_cntrl; /* MBAR_ETH + 0x084 */ - volatile u32 r_hash; /* MBAR_ETH + 0x088 */ - volatile u32 r_data; /* MBAR_ETH + 0x08C */ - volatile u32 ar_done; /* MBAR_ETH + 0x090 */ - volatile u32 r_test; /* MBAR_ETH + 0x094 */ - volatile u32 r_mib; /* MBAR_ETH + 0x098 */ - volatile u32 r_da_low; /* MBAR_ETH + 0x09C */ - volatile u32 r_da_high; /* MBAR_ETH + 0x0A0 */ - - volatile u32 RES4[7]; /* MBAR_ETH + 0x0A4-0BC */ - volatile u32 x_activate; /* MBAR_ETH + 0x0C0 */ - volatile u32 x_cntrl; /* MBAR_ETH + 0x0C4 */ - volatile u32 backoff; /* MBAR_ETH + 0x0C8 */ - volatile u32 x_data; /* MBAR_ETH + 0x0CC */ - volatile u32 x_status; /* MBAR_ETH + 0x0D0 */ - volatile u32 x_mib; /* MBAR_ETH + 0x0D4 */ - volatile u32 x_test; /* MBAR_ETH + 0x0D8 */ - volatile u32 fdxfc_da1; /* MBAR_ETH + 0x0DC */ - volatile u32 fdxfc_da2; /* MBAR_ETH + 0x0E0 */ - volatile u32 paddr1; /* MBAR_ETH + 0x0E4 */ - volatile u32 paddr2; /* MBAR_ETH + 0x0E8 */ - volatile u32 op_pause; /* MBAR_ETH + 0x0EC */ - - volatile u32 RES5[4]; /* MBAR_ETH + 0x0F0-0FC */ - volatile u32 instr_reg; /* MBAR_ETH + 0x100 */ - volatile u32 context_reg; /* MBAR_ETH + 0x104 */ - volatile u32 test_cntrl; /* MBAR_ETH + 0x108 */ - volatile u32 acc_reg; /* MBAR_ETH + 0x10C */ - volatile u32 ones; /* MBAR_ETH + 0x110 */ - volatile u32 zeros; /* MBAR_ETH + 0x114 */ - volatile u32 iaddr1; /* MBAR_ETH + 0x118 */ - volatile u32 iaddr2; /* MBAR_ETH + 0x11C */ - volatile u32 gaddr1; /* MBAR_ETH + 0x120 */ - volatile u32 gaddr2; /* MBAR_ETH + 0x124 */ - volatile u32 random; /* MBAR_ETH + 0x128 */ - volatile u32 rand1; /* MBAR_ETH + 0x12C */ - volatile u32 tmp; /* MBAR_ETH + 0x130 */ - - volatile u32 RES6[3]; /* MBAR_ETH + 0x134-13C */ - volatile u32 fifo_id; /* MBAR_ETH + 0x140 */ - volatile u32 x_wmrk; /* MBAR_ETH + 0x144 */ - volatile u32 fcntrl; /* MBAR_ETH + 0x148 */ - volatile u32 r_bound; /* MBAR_ETH + 0x14C */ - volatile u32 r_fstart; /* MBAR_ETH + 0x150 */ - volatile u32 r_count; /* MBAR_ETH + 0x154 */ - volatile u32 r_lag; /* MBAR_ETH + 0x158 */ - volatile u32 r_read; /* MBAR_ETH + 0x15C */ - volatile u32 r_write; /* MBAR_ETH + 0x160 */ - volatile u32 x_count; /* MBAR_ETH + 0x164 */ - volatile u32 x_lag; /* MBAR_ETH + 0x168 */ - volatile u32 x_retry; /* MBAR_ETH + 0x16C */ - volatile u32 x_write; /* MBAR_ETH + 0x170 */ - volatile u32 x_read; /* MBAR_ETH + 0x174 */ - - volatile u32 RES7[2]; /* MBAR_ETH + 0x178-17C */ - volatile u32 fm_cntrl; /* MBAR_ETH + 0x180 */ - volatile u32 rfifo_data; /* MBAR_ETH + 0x184 */ - volatile u32 rfifo_status; /* MBAR_ETH + 0x188 */ - volatile u32 rfifo_cntrl; /* MBAR_ETH + 0x18C */ - volatile u32 rfifo_lrf_ptr; /* MBAR_ETH + 0x190 */ - volatile u32 rfifo_lwf_ptr; /* MBAR_ETH + 0x194 */ - volatile u32 rfifo_alarm; /* MBAR_ETH + 0x198 */ - volatile u32 rfifo_rdptr; /* MBAR_ETH + 0x19C */ - volatile u32 rfifo_wrptr; /* MBAR_ETH + 0x1A0 */ - volatile u32 tfifo_data; /* MBAR_ETH + 0x1A4 */ - volatile u32 tfifo_status; /* MBAR_ETH + 0x1A8 */ - volatile u32 tfifo_cntrl; /* MBAR_ETH + 0x1AC */ - volatile u32 tfifo_lrf_ptr; /* MBAR_ETH + 0x1B0 */ - volatile u32 tfifo_lwf_ptr; /* MBAR_ETH + 0x1B4 */ - volatile u32 tfifo_alarm; /* MBAR_ETH + 0x1B8 */ - volatile u32 tfifo_rdptr; /* MBAR_ETH + 0x1BC */ - volatile u32 tfifo_wrptr; /* MBAR_ETH + 0x1C0 */ - - volatile u32 reset_cntrl; /* MBAR_ETH + 0x1C4 */ - volatile u32 xmit_fsm; /* MBAR_ETH + 0x1C8 */ - - volatile u32 RES8[3]; /* MBAR_ETH + 0x1CC-1D4 */ - volatile u32 rdes_data0; /* MBAR_ETH + 0x1D8 */ - volatile u32 rdes_data1; /* MBAR_ETH + 0x1DC */ - volatile u32 r_length; /* MBAR_ETH + 0x1E0 */ - volatile u32 x_length; /* MBAR_ETH + 0x1E4 */ - volatile u32 x_addr; /* MBAR_ETH + 0x1E8 */ - volatile u32 cdes_data; /* MBAR_ETH + 0x1EC */ - volatile u32 status; /* MBAR_ETH + 0x1F0 */ - volatile u32 dma_control; /* MBAR_ETH + 0x1F4 */ - volatile u32 des_cmnd; /* MBAR_ETH + 0x1F8 */ - volatile u32 data; /* MBAR_ETH + 0x1FC */ - - /* MIB COUNTERS (Offset 200-2FF) */ - - volatile u32 rmon_t_drop; /* MBAR_ETH + 0x200 */ - volatile u32 rmon_t_packets; /* MBAR_ETH + 0x204 */ - volatile u32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ - volatile u32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ - volatile u32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */ - volatile u32 rmon_t_undersize; /* MBAR_ETH + 0x214 */ - volatile u32 rmon_t_oversize; /* MBAR_ETH + 0x218 */ - volatile u32 rmon_t_frag; /* MBAR_ETH + 0x21C */ - volatile u32 rmon_t_jab; /* MBAR_ETH + 0x220 */ - volatile u32 rmon_t_col; /* MBAR_ETH + 0x224 */ - volatile u32 rmon_t_p64; /* MBAR_ETH + 0x228 */ - volatile u32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */ - volatile u32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */ - volatile u32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */ - volatile u32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ - volatile u32 rmon_t_p1024to2047;/* MBAR_ETH + 0x23C */ - volatile u32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ - volatile u32 rmon_t_octets; /* MBAR_ETH + 0x244 */ - volatile u32 ieee_t_drop; /* MBAR_ETH + 0x248 */ - volatile u32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ - volatile u32 ieee_t_1col; /* MBAR_ETH + 0x250 */ - volatile u32 ieee_t_mcol; /* MBAR_ETH + 0x254 */ - volatile u32 ieee_t_def; /* MBAR_ETH + 0x258 */ - volatile u32 ieee_t_lcol; /* MBAR_ETH + 0x25C */ - volatile u32 ieee_t_excol; /* MBAR_ETH + 0x260 */ - volatile u32 ieee_t_macerr; /* MBAR_ETH + 0x264 */ - volatile u32 ieee_t_cserr; /* MBAR_ETH + 0x268 */ - volatile u32 ieee_t_sqe; /* MBAR_ETH + 0x26C */ - volatile u32 t_fdxfc; /* MBAR_ETH + 0x270 */ - volatile u32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ - - volatile u32 RES9[2]; /* MBAR_ETH + 0x278-27C */ - volatile u32 rmon_r_drop; /* MBAR_ETH + 0x280 */ - volatile u32 rmon_r_packets; /* MBAR_ETH + 0x284 */ - volatile u32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ - volatile u32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ - volatile u32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */ - volatile u32 rmon_r_undersize; /* MBAR_ETH + 0x294 */ - volatile u32 rmon_r_oversize; /* MBAR_ETH + 0x298 */ - volatile u32 rmon_r_frag; /* MBAR_ETH + 0x29C */ - volatile u32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */ - - volatile u32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ - - volatile u32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */ - volatile u32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ - volatile u32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ - volatile u32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ - volatile u32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ - volatile u32 rmon_r_p1024to2047;/* MBAR_ETH + 0x2BC */ - volatile u32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ - volatile u32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */ - volatile u32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */ - volatile u32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ - volatile u32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */ - volatile u32 ieee_r_align; /* MBAR_ETH + 0x2D4 */ - volatile u32 r_macerr; /* MBAR_ETH + 0x2D8 */ - volatile u32 r_fdxfc; /* MBAR_ETH + 0x2DC */ - volatile u32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ - - volatile u32 RES10[6]; /* MBAR_ETH + 0x2E4-2FC */ - - volatile u32 RES11[64]; /* MBAR_ETH + 0x300-3FF */ -} ethernet_regs; - -/* Receive & Transmit Buffer Descriptor definitions */ -typedef struct BufferDescriptor { - u16 status; - u16 dataLength; - u32 dataPointer; -} FEC_RBD; - -typedef struct { - u16 status; - u16 dataLength; - u32 dataPointer; -} FEC_TBD; - -/* private structure */ -typedef enum { - SEVENWIRE, /* 7-wire */ - MII10, /* MII 10Mbps */ - MII100 /* MII 100Mbps */ -} xceiver_type; - -typedef struct { - ethernet_regs *eth; - xceiver_type xcv_type; /* transceiver type */ - FEC_RBD *rbdBase; /* RBD ring */ - FEC_TBD *tbdBase; /* TBD ring */ - u16 rbdIndex; /* next receive BD to read */ - u16 tbdIndex; /* next transmit BD to send */ - u16 usedTbdIndex; /* next transmit BD to clean */ - u16 cleanTbdNum; /* the number of available transmit BDs */ -} mpc8220_fec_priv; - -/* Ethernet parameter area */ -#define FEC_TBD_BASE (FEC_PARAM_BASE + 0x00) -#define FEC_TBD_NEXT (FEC_PARAM_BASE + 0x04) -#define FEC_RBD_BASE (FEC_PARAM_BASE + 0x08) -#define FEC_RBD_NEXT (FEC_PARAM_BASE + 0x0c) - -/* BD Numer definitions */ -#define FEC_TBD_NUM 48 /* The user can adjust this value */ -#define FEC_RBD_NUM 32 /* The user can adjust this value */ - -/* packet size limit */ -#define FEC_MAX_PKT_SIZE 1536 - -/* RBD bits definitions */ -#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ -#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ -#define FEC_RBD_INT 0x1000 /* Interrupt */ -#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ -#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ -#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ -#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ -#define FEC_RBD_LG 0x0020 /* Frame length violation */ -#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ -#define FEC_RBD_SH 0x0008 /* Short frame */ -#define FEC_RBD_CR 0x0004 /* CRC error */ -#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ -#define FEC_RBD_TR 0x0001 /* Frame is truncated */ -#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ - FEC_RBD_OV | FEC_RBD_TR) - -/* TBD bits definitions */ -#define FEC_TBD_READY 0x8000 /* Buffer is ready */ -#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ -#define FEC_TBD_INT 0x1000 /* Interrupt */ -#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ -#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ -#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ - -/* MII-related definitios */ -#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ -#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ -#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ -#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ -#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ -#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ -#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ - -#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ -#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ - -#endif /* __MPC8220_FEC_H */ diff --git a/cpu/mpc8220/fec_dma_tasks.S b/cpu/mpc8220/fec_dma_tasks.S deleted file mode 100644 index 3f8a03b..0000000 --- a/cpu/mpc8220/fec_dma_tasks.S +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright (C) 2004, Freescale Semiconductor, Inc. - * - * This file contains microcode for the FEC controller of the MPC8220. - */ - -#include - -#if defined(CONFIG_MPC8220) - -/* sas/sccg, gas target */ -.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */ -.section smartdmaTaskTable,"aw",@progbits /* Task tables */ -.align 9 -.globl taskTable -taskTable: -.globl scEthernetRecv_Entry -scEthernetRecv_Entry: /* Task 0 */ -.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */ -.long scEthernetRecv_TDT - taskTable + 0x00000094 -.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */ -.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long 0xf0000000 -.globl scEthernetXmit_Entry -scEthernetXmit_Entry: /* Task 1 */ -.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ -.long scEthernetXmit_TDT - taskTable + 0x000000e0 -.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */ -.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */ -.long 0x00000000 -.long 0x00000000 -.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long 0xf0000000 - - -.globl scEthernetRecv_TDT -scEthernetRecv_TDT: /* Task 0 Descriptor Table */ -.long 0xc4c50000 /* 0000(153): LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */ -.long 0x84c5e000 /* 0004(153): LCD: idx1 = var9 + var11; ; idx1 += inc0 */ -.long 0x10001f08 /* 0008(156): DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000380 /* 000C(157): DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f88 /* 0010(158): DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014(162): LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018(164): DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C(165): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x010cf04c /* 0020(165): DRD2B1: var4 = EU3(); EU3(var1,var12) */ -.long 0x82180349 /* 0024(169): LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */ -.long 0x81c68004 /* 0028(172): LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x70000000 /* 002C(174): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018cf04e /* 0030(174): DRD2B1: var6 = EU3(); EU3(var1,var14) */ -.long 0x70000000 /* 0034(175): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x020cf04f /* 0038(175): DRD2B1: var8 = EU3(); EU3(var1,var15) */ -.long 0x00000b88 /* 003C(176): DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0x80025184 /* 0040(205): LCDEXT: idx1 = 0xf0009184; ; */ -.long 0x86810412 /* 0044(205): LCD: idx2 = var13, idx3 = var2; idx2 < var16; idx2 += inc2, idx3 += inc2 */ -.long 0x0200cf88 /* 0048(209): DRD1A: *idx3 = *idx1; FN=0 init=16 WS=0 RS=0 */ -.long 0x80025184 /* 004C(217): LCDEXT: idx1 = 0xf0009184; ; */ -.long 0x8681845b /* 0050(217): LCD: idx2 = var13, idx3 = var3; idx2 < var17; idx2 += inc3, idx3 += inc3 */ -.long 0x0000cf88 /* 0054(221): DRD1A: *idx3 = *idx1; FN=0 init=0 WS=0 RS=0 */ -.long 0xc31883a4 /* 0058(225): LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc4 */ -.long 0x80190000 /* 005C(225): LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008468 /* 0060(227): DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4038360 /* 0064(232): LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc4, idx2 += inc0 */ -.long 0x81c50000 /* 0068(233): LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */ -.long 0x1000cb18 /* 006C(235): DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 0070(236): DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc418836d /* 0074(238): LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc5 */ -.long 0x83990000 /* 0078(238): LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */ -.long 0x10000c00 /* 007C(240): DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x0000c800 /* 0080(241): DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 0084(245): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 0088(247): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 008C(248): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080cf04c /* 0090(248): DRD2B1: idx0 = EU3(); EU3(var1,var12) */ -.long 0x000001f8 /* 0094(:0): NOP */ - - -.globl scEthernetXmit_TDT -scEthernetXmit_TDT: /* Task 1 Descriptor Table */ -.long 0x80095b00 /* 0000(280): LCDEXT: idx0 = 0xf0025b00; ; */ -.long 0x85c60004 /* 0004(280): LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */ -.long 0x10002308 /* 0008(283): DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x10000f88 /* 000C(284): DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000380 /* 0010(285): DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */ -.long 0x81980000 /* 0014(288): LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */ -.long 0x10000780 /* 0018(290): DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 001C(291): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x024cf04d /* 0020(291): DRD2B1: var9 = EU3(); EU3(var1,var13) */ -.long 0x84980309 /* 0024(294): LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */ -.long 0xc0004003 /* 0028(297): LCDEXT: idx1 = 0x00000003; ; */ -.long 0x81c60004 /* 002C(297): LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ -.long 0x70000000 /* 0030(299): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x010cf04e /* 0034(299): DRD2B1: var4 = EU3(); EU3(var1,var14) */ -.long 0x70000000 /* 0038(300): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x014cf04f /* 003C(300): DRD2B1: var5 = EU3(); EU3(var1,var15) */ -.long 0x70000000 /* 0040(301): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x028cf050 /* 0044(301): DRD2B1: var10 = EU3(); EU3(var1,var16) */ -.long 0x70000000 /* 0048(302): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */ -.long 0x018cf051 /* 004C(302): DRD2B1: var6 = EU3(); EU3(var1,var17) */ -.long 0x10000b90 /* 0050(303): DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 0054(304): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x01ccf0a1 /* 0058(304): DRD2B1: var7 = EU3(); EU3(var2,idx1) */ -.long 0xc2988312 /* 005C(308): LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */ -.long 0x83490000 /* 0060(308): LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */ -.long 0x00001b10 /* 0064(310): DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */ -.long 0x800251a4 /* 0068(315): LCDEXT: idx1 = 0xf00091a4; ; */ -.long 0xc30104dc /* 006C(315): LCDEXT: idx2 = var6, idx3 = var2; idx2 >= var19; idx2 += inc3, idx3 += inc4 */ -.long 0x839a032d /* 0070(316): LCD: idx4 = var7; idx4 == var12; idx4 += inc5 */ -.long 0x0220c798 /* 0074(321): DRD1A: *idx1 = *idx3; FN=0 init=17 WS=0 RS=0 */ -.long 0x800251a4 /* 0078(329): LCDEXT: idx1 = 0xf00091a4; ; */ -.long 0x99198337 /* 007C(329): LCD: idx2 = idx2, idx3 = idx3; idx2 > var12; idx2 += inc6, idx3 += inc7 */ -.long 0x022ac798 /* 0080(333): DRD1A: *idx1 = *idx3; FN=0 init=17 WS=1 RS=1 */ -.long 0x800251a4 /* 0084(350): LCDEXT: idx1 = 0xf00091a4; ; */ -.long 0xc1430000 /* 0088(350): LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */ -.long 0x82998312 /* 008C(351): LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */ -.long 0x0a2ac790 /* 0090(354): DRD1A: *idx1 = *idx2; FN=0 TFD init=17 WS=1 RS=1 */ -.long 0x81988000 /* 0094(359): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x60000002 /* 0098(361): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=0 RS=0 */ -.long 0x0c4cfc4d /* 009C(361): DRD2B1: *idx1 = EU3(); EU3(*idx1,var13) */ -.long 0xc21883ad /* 00A0(365): LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */ -.long 0x80190000 /* 00A4(365): LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ -.long 0x04008460 /* 00A8(367): DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */ -.long 0xc4052305 /* 00AC(371): LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */ -.long 0x81ca0000 /* 00B0(372): LCD: idx3 = var3 + var20; idx3 once var0; idx3 += inc0 */ -.long 0x1000c718 /* 00B4(374): DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00000f18 /* 00B8(375): DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ -.long 0xc4188000 /* 00BC(378): LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */ -.long 0x85190312 /* 00C0(378): LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */ -.long 0x10000c00 /* 00C4(380): DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x1000c400 /* 00C8(381): DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x00008860 /* 00CC(382): DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */ -.long 0x81988000 /* 00D0(386): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ -.long 0x10000788 /* 00D4(388): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ -.long 0x60000000 /* 00D8(389): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */ -.long 0x080cf04d /* 00DC(389): DRD2B1: idx0 = EU3(); EU3(var1,var13) */ -.long 0x000001f8 /* 00E0(:0): NOP */ - -.align 8 - -.globl scEthernetRecv_VarTab -scEthernetRecv_VarTab: /* Task 0 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0xf0025b00 /* var[9] */ -.long 0x00000008 /* var[10] */ -.long 0x0000000c /* var[11] */ -.long 0x80000000 /* var[12] */ -.long 0x00000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x20000000 /* var[15] */ -.long 0x00000800 /* var[16] */ -.long 0x00000001 /* var[17] */ -.long 0x00000000 /* var[18] */ -.long 0x00000000 /* var[19] */ -.long 0x00000000 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x20000004 /* inc[2] */ -.long 0x20000001 /* inc[3] */ -.long 0x80000000 /* inc[4] */ -.long 0x40000000 /* inc[5] */ -.long 0x00000000 /* inc[6] */ -.long 0x00000000 /* inc[7] */ - -.align 8 - -.globl scEthernetXmit_VarTab -scEthernetXmit_VarTab: /* Task 1 Variable Table */ -.long 0x00000000 /* var[0] */ -.long 0x00000000 /* var[1] */ -.long 0x00000000 /* var[2] */ -.long 0x00000000 /* var[3] */ -.long 0x00000000 /* var[4] */ -.long 0x00000000 /* var[5] */ -.long 0x00000000 /* var[6] */ -.long 0x00000000 /* var[7] */ -.long 0x00000000 /* var[8] */ -.long 0x00000000 /* var[9] */ -.long 0x00000000 /* var[10] */ -.long 0xf0025b00 /* var[11] */ -.long 0x00000000 /* var[12] */ -.long 0x80000000 /* var[13] */ -.long 0x10000000 /* var[14] */ -.long 0x08000000 /* var[15] */ -.long 0x20000000 /* var[16] */ -.long 0x0000ffff /* var[17] */ -.long 0xffffffff /* var[18] */ -.long 0x00000004 /* var[19] */ -.long 0x00000008 /* var[20] */ -.long 0x00000000 /* var[21] */ -.long 0x00000000 /* var[22] */ -.long 0x00000000 /* var[23] */ -.long 0x00000000 /* inc[0] */ -.long 0x60000000 /* inc[1] */ -.long 0x40000000 /* inc[2] */ -.long 0xc000fffc /* inc[3] */ -.long 0xe0000004 /* inc[4] */ -.long 0x80000000 /* inc[5] */ -.long 0x4000ffff /* inc[6] */ -.long 0xe0000001 /* inc[7] */ - -.align 8 - -.globl scEthernetRecv_FDT -scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x21800000 /* and(), EU# 3 */ -.long 0x21e00000 /* or(), EU# 3 */ -.long 0x21400000 /* andn(), EU# 3 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - -.align 8 - -.globl scEthernetXmit_FDT -scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x21800000 /* and(), EU# 3 */ -.long 0x21e00000 /* or(), EU# 3 */ -.long 0x21400000 /* andn(), EU# 3 */ -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 -.long 0x00000000 - - -.globl scEthernetRecv_CSave -scEthernetRecv_CSave: /* Task 0 context save space */ -.space 128, 0x0 - - -.globl scEthernetXmit_CSave -scEthernetXmit_CSave: /* Task 1 context save space */ -.space 128, 0x0 - -#endif diff --git a/cpu/mpc8220/i2c.c b/cpu/mpc8220/i2c.c deleted file mode 100644 index 62f7c0f..0000000 --- a/cpu/mpc8220/i2c.c +++ /dev/null @@ -1,405 +0,0 @@ -/* - * (C) Copyright 2004, Freescale, Inc - * TsiChung Liew, Tsi-Chung.Liew@freescale.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifdef CONFIG_HARD_I2C - -#include -#include - -typedef struct mpc8220_i2c { - volatile u32 adr; /* I2Cn + 0x00 */ - volatile u32 fdr; /* I2Cn + 0x04 */ - volatile u32 cr; /* I2Cn + 0x08 */ - volatile u32 sr; /* I2Cn + 0x0C */ - volatile u32 dr; /* I2Cn + 0x10 */ -} i2c_t; - -/* I2Cn control register bits */ -#define I2C_EN 0x80 -#define I2C_IEN 0x40 -#define I2C_STA 0x20 -#define I2C_TX 0x10 -#define I2C_TXAK 0x08 -#define I2C_RSTA 0x04 -#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) - -/* I2Cn status register bits */ -#define I2C_CF 0x80 -#define I2C_AAS 0x40 -#define I2C_BB 0x20 -#define I2C_AL 0x10 -#define I2C_SRW 0x04 -#define I2C_IF 0x02 -#define I2C_RXAK 0x01 - -#define I2C_TIMEOUT 100 -#define I2C_RETRIES 1 - -struct mpc8220_i2c_tap { - int scl2tap; - int tap2tap; -}; - -static int mpc_reg_in (volatile u32 * reg); -static void mpc_reg_out (volatile u32 * reg, int val, int mask); -static int wait_for_bb (void); -static int wait_for_pin (int *status); -static int do_address (uchar chip, char rdwr_flag); -static int send_bytes (uchar chip, char *buf, int len); -static int receive_bytes (uchar chip, char *buf, int len); -static int mpc_get_fdr (int); - -static int mpc_reg_in (volatile u32 * reg) -{ - int ret; - ret = *reg >> 24; - __asm__ __volatile__ ("eieio"); - return ret; -} - -static void mpc_reg_out (volatile u32 * reg, int val, int mask) -{ - int tmp; - - if (!mask) { - *reg = val << 24; - } else { - tmp = mpc_reg_in (reg); - *reg = ((tmp & ~mask) | (val & mask)) << 24; - } - __asm__ __volatile__ ("eieio"); - - return; -} - -static int wait_for_bb (void) -{ - i2c_t *regs = (i2c_t *) MMAP_I2C; - int timeout = I2C_TIMEOUT; - int status; - - status = mpc_reg_in (®s->sr); - - while (timeout-- && (status & I2C_BB)) { -#if 1 - volatile int temp; - - mpc_reg_out (®s->cr, I2C_STA, I2C_STA); - temp = mpc_reg_in (®s->dr); - mpc_reg_out (®s->cr, 0, I2C_STA); - mpc_reg_out (®s->cr, 0, 0); - mpc_reg_out (®s->cr, I2C_EN, 0); -#endif - udelay (1000); - status = mpc_reg_in (®s->sr); - } - - return (status & I2C_BB); -} - -static int wait_for_pin (int *status) -{ - i2c_t *regs = (i2c_t *) MMAP_I2C; - int timeout = I2C_TIMEOUT; - - *status = mpc_reg_in (®s->sr); - - while (timeout-- && !(*status & I2C_IF)) { - udelay (1000); - *status = mpc_reg_in (®s->sr); - } - - if (!(*status & I2C_IF)) { - return -1; - } - - mpc_reg_out (®s->sr, 0, I2C_IF); - return 0; -} - -static int do_address (uchar chip, char rdwr_flag) -{ - i2c_t *regs = (i2c_t *) MMAP_I2C; - int status; - - chip <<= 1; - - if (rdwr_flag) - chip |= 1; - - mpc_reg_out (®s->cr, I2C_TX, I2C_TX); - mpc_reg_out (®s->dr, chip, 0); - - if (wait_for_pin (&status)) - return -2; - if (status & I2C_RXAK) - return -3; - return 0; -} - -static int send_bytes (uchar chip, char *buf, int len) -{ - i2c_t *regs = (i2c_t *) MMAP_I2C; - int wrcount; - int status; - - for (wrcount = 0; wrcount < len; ++wrcount) { - - mpc_reg_out (®s->dr, buf[wrcount], 0); - - if (wait_for_pin (&status)) - break; - - if (status & I2C_RXAK) - break; - - } - - return !(wrcount == len); - return 0; -} - -static int receive_bytes (uchar chip, char *buf, int len) -{ - i2c_t *regs = (i2c_t *) MMAP_I2C; - int dummy = 1; - int rdcount = 0; - int status; - int i; - - mpc_reg_out (®s->cr, 0, I2C_TX); - - for (i = 0; i < len; ++i) { - buf[rdcount] = mpc_reg_in (®s->dr); - - if (dummy) - dummy = 0; - else - rdcount++; - - if (wait_for_pin (&status)) - return -4; - } - - mpc_reg_out (®s->cr, I2C_TXAK, I2C_TXAK); - buf[rdcount++] = mpc_reg_in (®s->dr); - - if (wait_for_pin (&status)) - return -5; - - mpc_reg_out (®s->cr, 0, I2C_TXAK); - return 0; -} - -/**************** I2C API ****************/ - -void i2c_init (int speed, int saddr) -{ - i2c_t *regs = (i2c_t *) MMAP_I2C; - - mpc_reg_out (®s->cr, 0, 0); - mpc_reg_out (®s->adr, saddr << 1, 0); - - /* Set clock - */ - mpc_reg_out (®s->fdr, mpc_get_fdr (speed), 0); - - /* Enable module - */ - mpc_reg_out (®s->cr, I2C_EN, I2C_INIT_MASK); - mpc_reg_out (®s->sr, 0, I2C_IF); - return; -} - -static int mpc_get_fdr (int speed) -{ - DECLARE_GLOBAL_DATA_PTR; - static int fdr = -1; - - if (fdr == -1) { - ulong best_speed = 0; - ulong divider; - ulong ipb, scl; - ulong bestmatch = 0xffffffffUL; - int best_i = 0, best_j = 0, i, j; - int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8 }; - struct mpc8220_i2c_tap scltap[] = { - {4, 1}, - {4, 2}, - {6, 4}, - {6, 8}, - {14, 16}, - {30, 32}, - {62, 64}, - {126, 128} - }; - - ipb = gd->bus_clk; - for (i = 7; i >= 0; i--) { - for (j = 7; j >= 0; j--) { - scl = 2 * (scltap[j].scl2tap + - (SCL_Tap[i] - - 1) * scltap[j].tap2tap + 2); - if (ipb <= speed * scl) { - if ((speed * scl - ipb) < bestmatch) { - bestmatch = speed * scl - ipb; - best_i = i; - best_j = j; - best_speed = ipb / scl; - } - } - } - } - divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2); - if (gd->flags & GD_FLG_RELOC) { - fdr = divider; - } else { - printf ("%ld kHz, ", best_speed / 1000); - return divider; - } - } - - return fdr; -} - -int i2c_probe (uchar chip) -{ - i2c_t *regs = (i2c_t *) MMAP_I2C; - int i; - - for (i = 0; i < I2C_RETRIES; i++) { - mpc_reg_out (®s->cr, I2C_STA, I2C_STA); - - if (!do_address (chip, 0)) { - mpc_reg_out (®s->cr, 0, I2C_STA); - break; - } - - mpc_reg_out (®s->cr, 0, I2C_STA); - udelay (50); - } - - return (i == I2C_RETRIES); -} - -int i2c_read (uchar chip, uint addr, int alen, uchar * buf, int len) -{ - uchar xaddr[4]; - i2c_t *regs = (i2c_t *) MMAP_I2C; - int ret = -1; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - - if (wait_for_bb ()) { - printf ("i2c_read: bus is busy\n"); - goto Done; - } - - mpc_reg_out (®s->cr, I2C_STA, I2C_STA); - if (do_address (chip, 0)) { - printf ("i2c_read: failed to address chip\n"); - goto Done; - } - - if (send_bytes (chip, (char *)&xaddr[4 - alen], alen)) { - printf ("i2c_read: send_bytes failed\n"); - goto Done; - } - - mpc_reg_out (®s->cr, I2C_RSTA, I2C_RSTA); - if (do_address (chip, 1)) { - printf ("i2c_read: failed to address chip\n"); - goto Done; - } - - if (receive_bytes (chip, (char *)buf, len)) { - printf ("i2c_read: receive_bytes failed\n"); - goto Done; - } - - ret = 0; - Done: - mpc_reg_out (®s->cr, 0, I2C_STA); - return ret; -} - -int i2c_write (uchar chip, uint addr, int alen, uchar * buf, int len) -{ - uchar xaddr[4]; - i2c_t *regs = (i2c_t *) MMAP_I2C; - int ret = -1; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - - if (wait_for_bb ()) { - printf ("i2c_write: bus is busy\n"); - goto Done; - } - - mpc_reg_out (®s->cr, I2C_STA, I2C_STA); - if (do_address (chip, 0)) { - printf ("i2c_write: failed to address chip\n"); - goto Done; - } - - if (send_bytes (chip, (char *)&xaddr[4 - alen], alen)) { - printf ("i2c_write: send_bytes failed\n"); - goto Done; - } - - if (send_bytes (chip, (char *)buf, len)) { - printf ("i2c_write: send_bytes failed\n"); - goto Done; - } - - ret = 0; - Done: - mpc_reg_out (®s->cr, 0, I2C_STA); - return ret; -} - -uchar i2c_reg_read (uchar chip, uchar reg) -{ - uchar buf; - - i2c_read (chip, reg, 1, &buf, 1); - - return buf; -} - -void i2c_reg_write (uchar chip, uchar reg, uchar val) -{ - i2c_write (chip, reg, 1, &val, 1); - - return; -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8220/i2cCore.c b/cpu/mpc8220/i2cCore.c deleted file mode 100644 index accf43c..0000000 --- a/cpu/mpc8220/i2cCore.c +++ /dev/null @@ -1,627 +0,0 @@ -/* I2cCore.c - MPC8220 PPC I2C Library */ - -/* Copyright 2004 Freescale Semiconductor, Inc. */ - -/* -modification history --------------------- -01c,29jun04,tcl 1.3 removed CR. Added two bytes offset support. -01b,19jan04,tcl 1.2 removed i2cMsDelay and sysDecGet. renamed i2cMsDelay - back to sysMsDelay -01a,19jan04,tcl 1.1 created and seperated from i2c.c -*/ - -/* -DESCRIPTION -This file contain I2C low level handling library functions -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* BSP Includes */ -#include "config.h" -#include "mpc8220.h" -#include "i2cCore.h" - -#ifdef DEBUG_I2CCORE -int I2CCDbg = 0; -#endif - -#define ABS(x) ((x < 0)? -x : x) - -char *I2CERR[16] = { - "Transfer in Progress\n", /* 0 */ - "Transfer complete\n", - "Not Addressed\n", /* 2 */ - "Addressed as a slave\n", - "Bus is Idle\n", /* 4 */ - "Bus is busy\n", - "Arbitration Lost\n", /* 6 */ - "Arbitration on Track\n", - "Slave receive, master writing to slave\n", /* 8 */ - "Slave transmit, master reading from slave\n", - "Interrupt is pending\n", /* 10 */ - "Interrupt complete\n", - "Acknowledge received\n", /* 12 */ - "No acknowledge received\n", - "Unknown status\n", /* 14 */ - "\n" -}; - -/****************************************************************************** - * - * chk_status - Check I2C status bit - * - * RETURNS: OK, or ERROR if the bit encounter - * - */ - -STATUS chk_status (PSI2C pi2c, UINT8 sta_bit, UINT8 truefalse) -{ - int i, status = 0; - - for (i = 0; i < I2C_POLL_COUNT; i++) { - if ((pi2c->sr & sta_bit) == (truefalse ? sta_bit : 0)) - return (OK); - } - - I2CCDBG (L2, ("--- sr %x stabit %x truefalse %d\n", - pi2c->sr, sta_bit, truefalse, 0, 0, 0)); - - if (i == I2C_POLL_COUNT) { - switch (sta_bit) { - case I2C_STA_CF: - status = 0; - break; - case I2C_STA_AAS: - status = 2; - break; - case I2C_STA_BB: - status = 4; - break; - case I2C_STA_AL: - status = 6; - break; - case I2C_STA_SRW: - status = 8; - break; - case I2C_STA_IF: - status = 10; - break; - case I2C_STA_RXAK: - status = 12; - break; - default: - status = 14; - break; - } - - if (!truefalse) - status++; - - I2CCDBG (NO, ("--- status %d\n", status, 0, 0, 0, 0, 0)); - I2CCDBG (NO, (I2CERR[status], 0, 0, 0, 0, 0, 0)); - } - - return (ERROR); -} - -/****************************************************************************** - * - * I2C Enable - Enable the I2C Controller - * - */ -STATUS i2c_enable (SI2C * pi2c, PI2CSET pi2cSet) -{ - int fdr = pi2cSet->bit_rate; - UINT8 adr = pi2cSet->i2c_adr; - - I2CCDBG (L2, ("i2c_enable fdr %d adr %x\n", fdr, adr, 0, 0, 0, 0)); - - i2c_clear (pi2c); /* Clear FDR, ADR, SR and CR reg */ - - SetI2cFDR (pi2c, fdr); /* Frequency */ - pi2c->adr = adr; - - pi2c->cr = I2C_CTL_EN; /* Set Enable */ - - /* - The I2C bus should be in Idle state. If the bus is busy, - clear the STA bit in control register - */ - if (chk_status (pi2c, I2C_STA_BB, 0) != OK) { - if ((pi2c->cr & I2C_CTL_STA) == I2C_CTL_STA) - pi2c->cr &= ~I2C_CTL_STA; - - /* Check again if it is still busy, return error if found */ - if (chk_status (pi2c, I2C_STA_BB, 1) == OK) - return ERROR; - } - - return (OK); -} - -/****************************************************************************** - * - * I2C Disable - Disable the I2C Controller - * - */ -STATUS i2c_disable (PSI2C pi2c) -{ - i2c_clear (pi2c); - - pi2c->cr &= I2C_CTL_EN; /* Disable I2c */ - - if ((pi2c->cr & I2C_CTL_STA) == I2C_CTL_STA) - pi2c->cr &= ~I2C_CTL_STA; - - if (chk_status (pi2c, I2C_STA_BB, 0) != OK) - return ERROR; - - return (OK); -} - -/****************************************************************************** - * - * I2C Clear - Clear the I2C Controller - * - */ -STATUS i2c_clear (PSI2C pi2c) -{ - pi2c->adr = 0; - pi2c->fdr = 0; - pi2c->cr = 0; - pi2c->sr = 0; - - return (OK); -} - - -STATUS i2c_start (PSI2C pi2c, PI2CSET pi2cSet) -{ -#ifdef TWOBYTES - UINT16 ByteOffset = pi2cSet->str_adr; -#else - UINT8 ByteOffset = pi2cSet->str_adr; -#endif -#if 1 - UINT8 tmp = 0; -#endif - UINT8 Addr = pi2cSet->slv_adr; - - pi2c->cr |= I2C_CTL_STA; /* Generate start signal */ - - if (chk_status (pi2c, I2C_STA_BB, 1) != OK) - return ERROR; - - /* Write slave address */ - if (i2c_writebyte (pi2c, &Addr) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } -#ifdef TWOBYTES -# if 0 - /* Issue the offset to start */ - if (i2c_write2byte (pi2c, &ByteOffset) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } -#endif - tmp = (ByteOffset >> 8) & 0xff; - if (i2c_writebyte (pi2c, &tmp) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } - tmp = ByteOffset & 0xff; - if (i2c_writebyte (pi2c, &tmp) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } -#else - if (i2c_writebyte (pi2c, &ByteOffset) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } -#endif - - return (OK); -} - -STATUS i2c_stop (PSI2C pi2c) -{ - pi2c->cr &= ~I2C_CTL_STA; /* Generate stop signal */ - if (chk_status (pi2c, I2C_STA_BB, 0) != OK) - return ERROR; - - return (OK); -} - -/****************************************************************************** - * - * Read Len bytes to the location pointed to by *Data from the device - * with address Addr. - */ -int i2c_readblock (SI2C * pi2c, PI2CSET pi2cSet, UINT8 * Data) -{ - int i = 0; - UINT8 Tmp; - -/* UINT8 ByteOffset = pi2cSet->str_adr; not used? */ - UINT8 Addr = pi2cSet->slv_adr; - int Length = pi2cSet->xfer_size; - - I2CCDBG (L1, ("i2c_readblock addr %x data 0x%08x len %d offset %d\n", - Addr, (int) Data, Length, ByteOffset, 0, 0)); - - if (pi2c->sr & I2C_STA_AL) { /* Check if Arbitration lost */ - I2CCDBG (FN, ("Arbitration lost\n", 0, 0, 0, 0, 0, 0)); - pi2c->sr &= ~I2C_STA_AL; /* Clear Arbitration status bit */ - return ERROR; - } - - pi2c->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack */ - - if (i2c_start (pi2c, pi2cSet) == ERROR) - return ERROR; - - pi2c->cr |= I2C_CTL_RSTA; /* Repeat Start */ - - Tmp = Addr | 1; - - if (i2c_writebyte (pi2c, &Tmp) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } - - if (((pi2c->sr & 0x07) == 0x07) || (pi2c->sr & 0x01)) - return ERROR; - - pi2c->cr &= ~I2C_CTL_TX; /* Set receive mode */ - - if (((pi2c->sr & 0x07) == 0x07) || (pi2c->sr & 0x01)) - return ERROR; - - /* Dummy Read */ - if (i2c_readbyte (pi2c, &Tmp, &i) != OK) { - i2c_stop (pi2c); /* Disable I2c */ - return ERROR; - } - - i = 0; - while (Length) { - if (Length == 2) - pi2c->cr |= I2C_CTL_TXAK; - - if (Length == 1) - pi2c->cr &= ~I2C_CTL_STA; - - if (i2c_readbyte (pi2c, Data, &Length) != OK) { - return i2c_stop (pi2c); - } - i++; - Length--; - Data++; - } - - if (i2c_stop (pi2c) == ERROR) - return ERROR; - - return i; -} - -STATUS i2c_writeblock (SI2C * pi2c, PI2CSET pi2cSet, UINT8 * Data) -{ - int Length = pi2cSet->xfer_size; - -#ifdef TWOBYTES - UINT16 ByteOffset = pi2cSet->str_adr; -#else - UINT8 ByteOffset = pi2cSet->str_adr; -#endif - int j, k; - - I2CCDBG (L2, ("i2c_writeblock\n", 0, 0, 0, 0, 0, 0)); - - if (pi2c->sr & I2C_STA_AL) { - /* Check if arbitration lost */ - I2CCDBG (L2, ("Arbitration lost\n", 0, 0, 0, 0, 0, 0)); - pi2c->sr &= ~I2C_STA_AL; /* Clear the condition */ - return ERROR; - } - - pi2c->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack */ - - /* Do the not even offset first */ - if ((ByteOffset % 8) != 0) { - int remain; - - if (Length > 8) { - remain = 8 - (ByteOffset % 8); - Length -= remain; - - pi2cSet->str_adr = ByteOffset; - - if (i2c_start (pi2c, pi2cSet) == ERROR) - return ERROR; - - for (j = ByteOffset; j < remain; j++) { - if (i2c_writebyte (pi2c, Data++) != OK) - return ERROR; - } - - if (i2c_stop (pi2c) == ERROR) - return ERROR; - - sysMsDelay (32); - - /* Update the new ByteOffset */ - ByteOffset += remain; - } - } - - for (j = ByteOffset, k = 0; j < (Length + ByteOffset); j++) { - if ((j % 8) == 0) { - pi2cSet->str_adr = j; - if (i2c_start (pi2c, pi2cSet) == ERROR) - return ERROR; - } - - k++; - - if (i2c_writebyte (pi2c, Data++) != OK) - return ERROR; - - if ((j == (Length - 1)) || ((k % 8) == 0)) { - if (i2c_stop (pi2c) == ERROR) - return ERROR; - - sysMsDelay (50); - } - - } - - return k; -} - -STATUS i2c_readbyte (SI2C * pi2c, UINT8 * readb, int *index) -{ - pi2c->sr &= ~I2C_STA_IF; /* Clear Interrupt Bit */ - *readb = pi2c->dr; /* Read a byte */ - - /* - Set I2C_CTRL_TXAK will cause Transfer pending and - set I2C_CTRL_STA will cause Interrupt pending - */ - if (*index != 2) { - if (chk_status (pi2c, I2C_STA_CF, 1) != OK) /* Transfer not complete? */ - return ERROR; - } - - if (*index != 1) { - if (chk_status (pi2c, I2C_STA_IF, 1) != OK) - return ERROR; - } - - return (OK); -} - - -STATUS i2c_writebyte (SI2C * pi2c, UINT8 * writeb) -{ - pi2c->sr &= ~I2C_STA_IF; /* Clear Interrupt */ - pi2c->dr = *writeb; /* Write a byte */ - - if (chk_status (pi2c, I2C_STA_CF, 1) != OK) /* Transfer not complete? */ - return ERROR; - - if (chk_status (pi2c, I2C_STA_IF, 1) != OK) - return ERROR; - - return OK; -} - -STATUS i2c_write2byte (SI2C * pi2c, UINT16 * writeb) -{ - UINT8 data; - - data = (UINT8) ((*writeb >> 8) & 0xff); - if (i2c_writebyte (pi2c, &data) != OK) - return ERROR; - data = (UINT8) (*writeb & 0xff); - if (i2c_writebyte (pi2c, &data) != OK) - return ERROR; - return OK; -} - -/* FDR table base on 33Mhz - more detail please refer to Odini2c_dividers.xls -FDR FDR scl sda scl2tap2 -510 432 tap tap tap tap scl_per sda_hold I2C Freq 0 1 2 3 4 5 -000 000 9 3 4 1 28 Clocks 9 Clocks 1190 KHz 0 0 0 0 0 0 -000 001 9 3 4 2 44 Clocks 11 Clocks 758 KHz 0 0 1 0 0 0 -000 010 9 3 6 4 80 Clocks 17 Clocks 417 KHz 0 0 0 1 0 0 -000 011 9 3 6 8 144 Clocks 25 Clocks 231 KHz 0 0 1 1 0 0 -000 100 9 3 14 16 288 Clocks 49 Clocks 116 KHz 0 0 0 0 1 0 -000 101 9 3 30 32 576 Clocks 97 Clocks 58 KHz 0 0 1 0 1 0 -000 110 9 3 62 64 1152 Clocks 193 Clocks 29 KHz 0 0 0 1 1 0 -000 111 9 3 126 128 2304 Clocks 385 Clocks 14 KHz 0 0 1 1 1 0 -001 000 10 3 4 1 30 Clocks 9 Clocks 1111 KHz1 0 0 0 0 0 -001 001 10 3 4 2 48 Clocks 11 Clocks 694 KHz 1 0 1 0 0 0 -001 010 10 3 6 4 88 Clocks 17 Clocks 379 KHz 1 0 0 1 0 0 -001 011 10 3 6 8 160 Clocks 25 Clocks 208 KHz 1 0 1 1 0 0 -001 100 10 3 14 16 320 Clocks 49 Clocks 104 KHz 1 0 0 0 1 0 -001 101 10 3 30 32 640 Clocks 97 Clocks 52 KHz 1 0 1 0 1 0 -001 110 10 3 62 64 1280 Clocks 193 Clocks 26 KHz 1 0 0 1 1 0 -001 111 10 3 126 128 2560 Clocks 385 Clocks 13 KHz 1 0 1 1 1 0 -010 000 12 4 4 1 34 Clocks 10 Clocks 980 KHz 0 1 0 0 0 0 -010 001 12 4 4 2 56 Clocks 13 Clocks 595 KHz 0 1 1 0 0 0 -010 010 12 4 6 4 104 Clocks 21 Clocks 321 KHz 0 1 0 1 0 0 -010 011 12 4 6 8 192 Clocks 33 Clocks 174 KHz 0 1 1 1 0 0 -010 100 12 4 14 16 384 Clocks 65 Clocks 87 KHz 0 1 0 0 1 0 -010 101 12 4 30 32 768 Clocks 129 Clocks 43 KHz 0 1 1 0 1 0 -010 110 12 4 62 64 1536 Clocks 257 Clocks 22 KHz 0 1 0 1 1 0 -010 111 12 4 126 128 3072 Clocks 513 Clocks 11 KHz 0 1 1 1 1 0 -011 000 15 4 4 1 40 Clocks 10 Clocks 833 KHz 1 1 0 0 0 0 -011 001 15 4 4 2 68 Clocks 13 Clocks 490 KHz 1 1 1 0 0 0 -011 010 15 4 6 4 128 Clocks 21 Clocks 260 KHz 1 1 0 1 0 0 -011 011 15 4 6 8 240 Clocks 33 Clocks 139 KHz 1 1 1 1 0 0 -011 100 15 4 14 16 480 Clocks 65 Clocks 69 KHz 1 1 0 0 1 0 -011 101 15 4 30 32 960 Clocks 129 Clocks 35 KHz 1 1 1 0 1 0 -011 110 15 4 62 64 1920 Clocks 257 Clocks 17 KHz 1 1 0 1 1 0 -011 111 15 4 126 128 3840 Clocks 513 Clocks 9 KHz 1 1 1 1 1 0 -100 000 5 1 4 1 20 Clocks 7 Clocks 1667 KHz 0 0 0 0 0 1 -100 001 5 1 4 2 28 Clocks 7 Clocks 1190 KHz 0 0 1 0 0 1 -100 010 5 1 6 4 48 Clocks 9 Clocks 694 KHz 0 0 0 1 0 1 -100 011 5 1 6 8 80 Clocks 9 Clocks 417 KHz 0 0 1 1 0 1 -100 100 5 1 14 16 160 Clocks 17 Clocks 208 KHz 0 0 0 0 1 1 -100 101 5 1 30 32 320 Clocks 33 Clocks 104 KHz 0 0 1 0 1 1 -100 110 5 1 62 64 640 Clocks 65 Clocks 52 KHz 0 0 0 1 1 1 -100 111 5 1 126 128 1280 Clocks 129 Clocks 26 KHz 0 0 1 1 1 1 -101 000 6 1 4 1 22 Clocks 7 Clocks 1515 KHz 1 0 0 0 0 1 -101 001 6 1 4 2 32 Clocks 7 Clocks 1042 KHz 1 0 1 0 0 1 -101 010 6 1 6 4 56 Clocks 9 Clocks 595 KHz 1 0 0 1 0 1 -101 011 6 1 6 8 96 Clocks 9 Clocks 347 KHz 1 0 1 1 0 1 -101 100 6 1 14 16 192 Clocks 17 Clocks 174 KHz 1 0 0 0 1 1 -101 101 6 1 30 32 384 Clocks 33 Clocks 87 KHz 1 0 1 0 1 1 -101 110 6 1 62 64 768 Clocks 65 Clocks 43 KHz 1 0 0 1 1 1 -101 111 6 1 126 128 1536 Clocks 129 Clocks 22 KHz 1 0 1 1 1 1 -110 000 7 2 4 1 24 Clocks 8 Clocks 1389 KHz 0 1 0 0 0 1 -110 001 7 2 4 2 36 Clocks 9 Clocks 926 KHz 0 1 1 0 0 1 -110 010 7 2 6 4 64 Clocks 13 Clocks 521 KHz 0 1 0 1 0 1 -110 011 7 2 6 8 112 Clocks 17 Clocks 298 KHz 0 1 1 1 0 1 -110 100 7 2 14 16 224 Clocks 33 Clocks 149 KHz 0 1 0 0 1 1 -110 101 7 2 30 32 448 Clocks 65 Clocks 74 KHz 0 1 1 0 1 1 -110 110 7 2 62 64 896 Clocks 129 Clocks 37 KHz 0 1 0 1 1 1 -110 111 7 2 126 128 1792 Clocks 257 Clocks 19 KHz 0 1 1 1 1 1 -111 000 8 2 4 1 26 Clocks 8 Clocks 1282 KHz 1 1 0 0 0 1 -111 001 8 2 4 2 40 Clocks 9 Clocks 833 KHz 1 1 1 0 0 1 -111 010 8 2 6 4 72 Clocks 13 Clocks 463 KHz 1 1 0 1 0 1 -111 011 8 2 6 8 128 Clocks 17 Clocks 260 KHz 1 1 1 1 0 1 -111 100 8 2 14 16 256 Clocks 33 Clocks 130 KHz 1 1 0 0 1 1 -111 101 8 2 30 32 512 Clocks 65 Clocks 65 KHz 1 1 1 0 1 1 -111 110 8 2 62 64 1024 Clocks 129 Clocks 33 KHz 1 1 0 1 1 1 -111 111 8 2 126 128 2048 Clocks 257 Clocks 16 KHz 1 1 1 1 1 1 -*/ -STATUS SetI2cFDR (PSI2C pi2cRegs, int bitrate) -{ -/* Constants */ - const UINT8 div_hold[8][3] = { {9, 3}, {10, 3}, - {12, 4}, {15, 4}, - {5, 1}, {6, 1}, - {7, 2}, {8, 2} - }; - - const UINT8 scl_tap[8][2] = { {4, 1}, {4, 2}, - {6, 4}, {6, 8}, - {14, 16}, {30, 32}, - {62, 64}, {126, 128} - }; - - UINT8 mfdr_bits; - - int i = 0; - int j = 0; - - int Diff, min; - int WhichFreq, iRec, jRec; - int SCL_Period; - int SCL_Hold; - int I2C_Freq; - - I2CCDBG (L2, ("Entering getBitRate: bitrate %d pi2cRegs 0x%08x\n", - bitrate, (int) pi2cRegs, 0, 0, 0, 0)); - - if (bitrate < 0) { - I2CCDBG (NO, ("Invalid bitrate\n", 0, 0, 0, 0, 0, 0)); - return ERROR; - } - - /* Initialize */ - mfdr_bits = 0; - min = 0x7fffffff; - WhichFreq = iRec = jRec = 0; - - for (i = 0; i < 8; i++) { - for (j = 0; j < 8; j++) { - /* SCL Period = 2 * (scl2tap + [(SCL_Tap - 1) * tap2tap] + 2) - * SCL Hold = scl2tap + ((SDA_Tap - 1) * tap2tap) + 3 - * Bit Rate (I2C Freq) = System Freq / SCL Period - */ - SCL_Period = - 2 * (scl_tap[i][0] + - ((div_hold[j][0] - 1) * scl_tap[i][1]) + - 2); - - /* Now get the I2C Freq */ - I2C_Freq = DEV_CLOCK_FREQ / SCL_Period; - - /* Take equal or slower */ - if (I2C_Freq > bitrate) - continue; - - /* Take the differences */ - Diff = I2C_Freq - bitrate; - - Diff = ABS (Diff); - - /* Find the closer value */ - if (Diff < min) { - min = Diff; - WhichFreq = I2C_Freq; - iRec = i; - jRec = j; - } - - I2CCDBG (L2, - ("--- (%d,%d) I2C_Freq %d minDiff %d min %d\n", - i, j, I2C_Freq, Diff, min, 0)); - } - } - - SCL_Period = - 2 * (scl_tap[iRec][0] + - ((div_hold[jRec][0] - 1) * scl_tap[iRec][1]) + 2); - - I2CCDBG (L2, ("\nmin %d WhichFreq %d iRec %d jRec %d\n", - min, WhichFreq, iRec, jRec, 0, 0)); - I2CCDBG (L2, ("--- scl2tap %d SCL_Tap %d tap2tap %d\n", - scl_tap[iRec][0], div_hold[jRec][0], scl_tap[iRec][1], - 0, 0, 0)); - - /* This may no require */ - SCL_Hold = - scl_tap[iRec][0] + - ((div_hold[jRec][1] - 1) * scl_tap[iRec][1]) + 3; - I2CCDBG (L2, - ("--- SCL_Period %d SCL_Hold %d\n", SCL_Period, SCL_Hold, 0, - 0, 0, 0)); - - I2CCDBG (L2, ("--- mfdr_bits %x\n", mfdr_bits, 0, 0, 0, 0, 0)); - - /* FDR 4,3,2 */ - if ((iRec & 1) == 1) - mfdr_bits |= 0x04; /* FDR 2 */ - if ((iRec & 2) == 2) - mfdr_bits |= 0x08; /* FDR 3 */ - if ((iRec & 4) == 4) - mfdr_bits |= 0x10; /* FDR 4 */ - /* FDR 5,1,0 */ - if ((jRec & 1) == 1) - mfdr_bits |= 0x01; /* FDR 0 */ - if ((jRec & 2) == 2) - mfdr_bits |= 0x02; /* FDR 1 */ - if ((jRec & 4) == 4) - mfdr_bits |= 0x20; /* FDR 5 */ - - I2CCDBG (L2, ("--- mfdr_bits %x\n", mfdr_bits, 0, 0, 0, 0, 0)); - - pi2cRegs->fdr = mfdr_bits; - - return OK; -} diff --git a/cpu/mpc8220/i2cCore.h b/cpu/mpc8220/i2cCore.h deleted file mode 100644 index 72783fd..0000000 --- a/cpu/mpc8220/i2cCore.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * i2cCore.h - * - * Prototypes, etc. for the Motorola MPC8220 - * embedded cpu chips - * - * 2004 (c) Freescale, Inc. - * Author: TsiChung Liew - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __INCi2ccoreh -#define __INCi2ccoreh -#ifndef __ASSEMBLY__ -/* device types */ -#define I2C_DEVICE_TYPE_EEPROM 0 -#define I2C_EEPROM_ADRS 0xa0 -#define I2C_CTRL_ADRS I2C_EEPROM_ADRS -#define EEPROM_ADDR0 0xA2 /* on Dimm SPD eeprom */ -#define EEPROM_ADDR1 0xA4 /* on Board SPD eeprom */ -#define EEPROM_ADDR2 0xD2 /* non-standard eeprom - clock generator */ -/* Control Register */ -#define I2C_CTL_EN 0x80 /* I2C Enable */ -#define I2C_CTL_IEN 0x40 /* I2C Interrupt Enable */ -#define I2C_CTL_STA 0x20 /* Master/Slave Mode select */ -#define I2C_CTL_TX 0x10 /* Transmit/Receive Mode Select */ -#define I2C_CTL_TXAK 0x08 /* Transmit Acknowledge Enable */ -#define I2C_CTL_RSTA 0x04 /* Repeat Start */ -/* Status Register */ -#define I2C_STA_CF 0x80 /* Data Transfer */ -#define I2C_STA_AAS 0x40 /* Adressed As Slave */ -#define I2C_STA_BB 0x20 /* Bus Busy */ -#define I2C_STA_AL 0x10 /* Arbitration Lost */ -#define I2C_STA_SRW 0x04 /* Slave Read/Write */ -#define I2C_STA_IF 0x02 /* I2C Interrupt */ -#define I2C_STA_RXAK 0x01 /* Receive Acknowledge */ -/* Interrupt Contol Register */ -#define I2C_INT_BNBE2 0x80 /* Bus Not Busy Enable 2 */ -#define I2C_INT_TE2 0x40 /* Transmit Enable 2 */ -#define I2C_INT_RE2 0x20 /* Receive Enable 2 */ -#define I2C_INT_IE2 0x10 /* Interrupt Enable 2 */ -#define I2C_INT_BNBE1 0x08 /* Bus Not Busy Enable 1 */ -#define I2C_INT_TE1 0x04 /* Transmit Enable 1 */ -#define I2C_INT_RE1 0x02 /* Receive Enable 1 */ -#define I2C_INT_IE1 0x01 /* Interrupt Enable 1 */ -#define I2C_POLL_COUNT 0x100000 -#define I2C_ENABLE 0x00000001 -#define I2C_DISABLE 0x00000002 -#define I2C_START 0x00000004 -#define I2C_REPSTART 0x00000008 -#define I2C_STOP 0x00000010 -#define I2C_BITRATE 0x00000020 -#define I2C_SLAVEADR 0x00000040 -#define I2C_STARTADR 0x00000080 -#undef TWOBYTES -typedef struct i2c_settings { - /* Device settings */ - int bit_rate; /* Device bit rate */ - u8 i2c_adr; /* I2C address */ - u8 slv_adr; /* Slave address */ -#ifdef TWOBYTES - u16 str_adr; /* Start address */ -#else - u8 str_adr; /* Start address */ -#endif - int xfer_size; /* Transfer Size */ - - int bI2c_en; /* Enable or Disable */ - int cmdFlag; /* I2c Command Flags */ -} i2cset_t; - -/* -int check_status(PSI2C pi2c, u8 sta_bit, u8 truefalse); -int i2c_enable(PSI2C pi2c, PI2CSET pi2cSet); -int i2c_disable(PSI2C pi2c); -int i2c_start(PSI2C pi2c, PI2CSET pi2cSet); -int i2c_stop(PSI2C pi2c); -int i2c_clear(PSI2C pi2c); -int i2c_readblock (PSI2C pi2c, PI2CSET pi2cSet, u8 *Data); -int i2c_writeblock (PSI2C pi2c, PI2CSET pi2cSet, u8 *Data); -int i2c_readbyte(PSI2C pi2c, u8 *readb, int *index); -int i2c_writebyte(PSI2C pi2c, u8 *writeb); -int SetI2cFDR( PSI2C pi2cRegs, int bitrate ); -*/ -#endif /* __ASSEMBLY__ */ - -#endif /* __INCi2ccoreh */ diff --git a/cpu/mpc8220/interrupts.c b/cpu/mpc8220/interrupts.c deleted file mode 100644 index 036378c..0000000 --- a/cpu/mpc8220/interrupts.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright -2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * interrupts.c - just enough support for the decrementer/timer - */ - -#include -#include -#include - -int interrupt_init_cpu (ulong * decrementer_count) -{ - *decrementer_count = get_tbclk () / CFG_HZ; - - return (0); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt (struct pt_regs *regs) -{ - puts ("external_interrupt (oops!)\n"); -} - -void timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} - -/****************************************************************************/ - -/* - * Install and free a interrupt handler. - */ - -void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) -{ - -} - -void irq_free_handler (int vec) -{ - -} - -/****************************************************************************/ - -void -do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) -{ - puts ("IRQ related functions are unimplemented currently.\n"); -} diff --git a/cpu/mpc8220/io.S b/cpu/mpc8220/io.S deleted file mode 100644 index 5ecdf55..0000000 --- a/cpu/mpc8220/io.S +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH - * Andreas Heppel - * Copyright (C) 2003 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in16 -in16: - lhz r3,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in16r -in16r: - lhbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0(3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/* ------------------------------------------------------------------------------- */ - .globl in32r -in32r: - lwbrx r3,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16 -out16: - sth r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out16r -out16r: - sthbrx r4,0,r3 - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0(r3) - sync - blr - -/* ------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/* ------------------------------------------------------------------------------- */ - .globl out32r -out32r: - stwbrx r4,0,r3 - sync - blr diff --git a/cpu/mpc8220/loadtask.c b/cpu/mpc8220/loadtask.c deleted file mode 100644 index 6d8b627..0000000 --- a/cpu/mpc8220/loadtask.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on code - * (C) Copyright Motorola, Inc., 2000 - */ - -#include -#include - -/* Multichannel DMA microcode */ -extern int taskTable; - -void loadtask (int basetask, int tasks) -{ - int *sram = (int *) (MMAP_SRAM + 512); - int *task_org = &taskTable; - unsigned int start, offset, end; - int i; - -#ifdef DEBUG - printf ("basetask = %d, tasks = %d\n", basetask, tasks); - printf ("task_org = 0x%08x\n", (unsigned int) task_org); -#endif - - /* setup TaskBAR register */ - *(vu_long *) MMAP_DMA = (MMAP_SRAM + 512); - - /* relocate task table entries */ - offset = (unsigned int) sram; - for (i = basetask; i < basetask + tasks; i++) { - sram[i * 8 + 0] = task_org[i * 8 + 0] + offset; - sram[i * 8 + 1] = task_org[i * 8 + 1] + offset; - sram[i * 8 + 2] = task_org[i * 8 + 2] + offset; - sram[i * 8 + 3] = task_org[i * 8 + 3] + offset; - sram[i * 8 + 4] = task_org[i * 8 + 4]; - sram[i * 8 + 5] = task_org[i * 8 + 5]; - sram[i * 8 + 6] = task_org[i * 8 + 6] + offset; - sram[i * 8 + 7] = task_org[i * 8 + 7]; - } - - /* relocate task descriptors */ - start = (sram[basetask * 8] - (unsigned int) sram); - end = (sram[(basetask + tasks - 1) * 8 + 1] - (unsigned int) sram); - -#ifdef DEBUG - printf ("TDT start = 0x%08x, end = 0x%08x\n", start, end); -#endif - - start /= 4; - end /= 4; - for (i = start; i <= end; i++) { - sram[i] = task_org[i]; - } - - /* relocate variables */ - start = (sram[basetask * 8 + 2] - (unsigned int) sram); - end = (sram[(basetask + tasks - 1) * 8 + 2] + 256 - - (unsigned int) sram); - start /= 4; - end /= 4; - for (i = start; i < end; i++) { - sram[i] = task_org[i]; - } - - /* relocate function decriptors */ - start = ((sram[basetask * 8 + 3] & 0xfffffffc) - (unsigned int) sram); - end = ((sram[(basetask + tasks - 1) * 8 + 3] & 0xfffffffc) + 256 - - (unsigned int) sram); - start /= 4; - end /= 4; - for (i = start; i < end; i++) { - sram[i] = task_org[i]; - } - - asm volatile ("sync"); -} diff --git a/cpu/mpc8220/pci.c b/cpu/mpc8220/pci.c deleted file mode 100644 index ca4a04d..0000000 --- a/cpu/mpc8220/pci.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2003 Motorola Inc. - * Xianghua Xiao (x.xiao@motorola.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCI Configuration space access support for MPC8220 PCI Bridge - */ -#include -#include -#include -#include - -#if defined(CONFIG_PCI) - -/* System RAM mapped over PCI */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) - -#define cfg_read(val, addr, type, op) *val = op((type)(addr)); -#define cfg_write(val, addr, type, op) op((type *)(addr), (val)); - -#define PCI_OP(rw, size, type, op, mask) \ -int mpc8220_pci_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - u32 addr = 0; \ - u16 cfg_type = 0; \ - addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ - out_be32(hose->cfg_addr, addr); \ - __asm__ __volatile__("sync"); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ - out_be32(hose->cfg_addr, addr & 0x7fffffff); \ - __asm__ __volatile__("sync"); \ - return 0; \ -} - -PCI_OP(read, byte, u8 *, in_8, 3) -PCI_OP(read, word, u16 *, in_le16, 2) -PCI_OP(write, byte, u8, out_8, 3) -PCI_OP(write, word, u16, out_le16, 2) -PCI_OP(write, dword, u32, out_le32, 0) - -int mpc8220_pci_read_config_dword(struct pci_controller *hose, pci_dev_t dev, - int offset, u32 *val) -{ - u32 addr; - u32 tmpv; - u32 mask = 2; /* word access */ - /* Read lower 16 bits */ - addr = ((offset & 0xfc) | (dev) | 0x80000000); - out_be32(hose->cfg_addr, addr); - __asm__ __volatile__("sync"); - *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); - out_be32(hose->cfg_addr, addr & 0x7fffffff); - __asm__ __volatile__("sync"); - - /* Read upper 16 bits */ - offset += 2; - addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); - out_be32(hose->cfg_addr, addr); - __asm__ __volatile__("sync"); - tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); - out_be32(hose->cfg_addr, addr & 0x7fffffff); - __asm__ __volatile__("sync"); - - /* combine results into dword value */ - *val = (tmpv << 16) | *val; - - return 0; -} - -void -pci_mpc8220_init(struct pci_controller *hose) -{ - u32 win0, win1, win2; - volatile mpc8220_xcpci_t *xcpci = - (volatile mpc8220_xcpci_t *) MMAP_XCPCI; - - volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG; - - win0 = (u32) CONFIG_PCI_MEM_PHYS; - win1 = (u32) CONFIG_PCI_IO_PHYS; - win2 = (u32) CONFIG_PCI_CFG_PHYS; - - /* Assert PCI reset */ - out_be32 (&xcpci->glb_stat_ctl, PCI_GLB_STAT_CTRL_PR); - - /* Disable prefetching but read-multiples will still prefetch */ - out_be32 (&xcpci->target_ctrl, 0x00000000); - - /* Initiator windows */ - out_be32 (&xcpci->init_win0, (win0 >> 16) | win0 | 0x003f0000); - out_be32 (&xcpci->init_win1, ((win1 >> 16) | win1 )); - out_be32 (&xcpci->init_win2, ((win2 >> 16) | win2 )); - - out_be32 (&xcpci->init_win_cfg, - PCI_INIT_WIN_CFG_WIN0_CTRL_EN | - PCI_INIT_WIN_CFG_WIN1_CTRL_EN | PCI_INIT_WIN_CFG_WIN1_CTRL_IO | - PCI_INIT_WIN_CFG_WIN2_CTRL_EN | PCI_INIT_WIN_CFG_WIN2_CTRL_IO); - - out_be32 (&xcpci->init_ctrl, 0x00000000); - - /* Enable bus master and mem access */ - out_be32 (&xcpci->stat_cmd_reg, PCI_STAT_CMD_B | PCI_STAT_CMD_M); - - /* Cache line size and master latency */ - out_be32 (&xcpci->bist_htyp_lat_cshl, (0xf8 << PCI_CFG1_LT_SHIFT)); - - out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */ - out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */ - - out_be32 (&xcpci->target_bar0, - PCI_TARGET_BASE_ADDR_REG0 | PCI_TARGET_BASE_ADDR_EN); - out_be32 (&xcpci->target_bar1, - PCI_TARGET_BASE_ADDR_REG1 | PCI_TARGET_BASE_ADDR_EN); - - /* Deassert reset bit */ - out_be32 (&xcpci->glb_stat_ctl, 0x00000000); - - /* Enable PCI bus master support */ - /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, - PCIREQ2, PCIGNT2 */ - out_be32((volatile u32 *)&portcfg->pcfg3, - (in_be32((volatile u32 *)&portcfg->pcfg3) & 0xFC3FCE7F)); - out_be32((volatile u32 *)&portcfg->pcfg3, - (in_be32((volatile u32 *)&portcfg->pcfg3) | 0x01400180)); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - pci_set_region(hose->regions + 2, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - CONFIG_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose->region_count = 3; - - hose->cfg_addr = &(xcpci->cfg_adr); - hose->cfg_data = CONFIG_PCI_CFG_BUS; - - pci_set_ops(hose, - mpc8220_pci_read_config_byte, - mpc8220_pci_read_config_word, - mpc8220_pci_read_config_dword, - mpc8220_pci_write_config_byte, - mpc8220_pci_write_config_word, - mpc8220_pci_write_config_dword); - - /* Hose scan */ - pci_register_hose(hose); - hose->last_busno = pci_hose_scan(hose); - - out_be32 (&xcpci->base0, PCI_BASE_ADDR_REG0); /* 256MB - MBAR space */ - out_be32 (&xcpci->base1, PCI_BASE_ADDR_REG1); /* 1GB - SDRAM space */ -} - -#endif /* CONFIG_PCI */ diff --git a/cpu/mpc8220/speed.c b/cpu/mpc8220/speed.c deleted file mode 100644 index 8346efe..0000000 --- a/cpu/mpc8220/speed.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2004, Freescale, Inc - * TsiChung Liew, Tsi-Chung.Liew@freescale.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -typedef struct pllmultiplier { - u8 hid1; - int multi; - int vco_div; -} pllcfg_t; - -/* ------------------------------------------------------------------------- */ - -/* - * - */ - -int get_clocks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - pllcfg_t bus2core[] = { - {0x02, 2, 8}, /* 1 */ - {0x01, 2, 4}, - {0x0C, 3, 8}, /* 1.5 */ - {0x00, 3, 4}, - {0x18, 3, 2}, - {0x05, 4, 4}, /* 2 */ - {0x04, 4, 2}, - {0x11, 5, 4}, /* 2.5 */ - {0x06, 5, 2}, - {0x10, 6, 4}, /* 3 */ - {0x08, 6, 2}, - {0x0E, 7, 2}, /* 3.5 */ - {0x0A, 8, 2}, /* 4 */ - {0x07, 9, 2}, /* 4.5 */ - {0x0B, 10, 2}, /* 5 */ - {0x09, 11, 2}, /* 5.5 */ - {0x0D, 12, 2}, /* 6 */ - {0x12, 13, 2}, /* 6.5 */ - {0x14, 14, 2}, /* 7 */ - {0x16, 15, 2}, /* 7.5 */ - {0x1C, 16, 2} /* 8 */ - }; - u32 hid1; - int i, size, pci2bus; - -#if !defined(CFG_MPC8220_CLKIN) -#error clock measuring not implemented yet - define CFG_MPC8220_CLKIN -#endif - - gd->inp_clk = CFG_MPC8220_CLKIN; - - /* Read XLB to PCI(INP) clock multiplier */ - pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) & - PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK)>>PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT; - - /* XLB bus clock */ - gd->bus_clk = CFG_MPC8220_CLKIN * pci2bus; - - /* PCI clock is same as input clock */ - gd->pci_clk = CFG_MPC8220_CLKIN; - - /* FlexBus is temporary set as the same as input clock */ - /* will do dynamic in the future */ - gd->flb_clk = CFG_MPC8220_CLKIN; - - /* CPU Clock - Read HID1 */ - asm volatile ("mfspr %0, 1009":"=r" (hid1):); - - size = sizeof (bus2core) / sizeof (pllcfg_t); - - hid1 >>= 27; - - for (i = 0; i < size; i++) - if (hid1 == bus2core[i].hid1) { - gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1; - gd->vco_clk = CFG_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2; - break; - } - - /* hardcoded 81MHz for now */ - gd->pev_clk = 81000000; - - return (0); -} - -int prt_mpc8220_clks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - printf (" Bus %ld MHz, CPU %ld MHz, PCI %ld MHz, VCO %ld MHz\n", - gd->bus_clk / 1000000, gd->cpu_clk / 1000000, - gd->pci_clk / 1000000, gd->vco_clk / 1000000); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S deleted file mode 100644 index 5233202..0000000 --- a/cpu/mpc8220/start.S +++ /dev/null @@ -1,775 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000 - 2003 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * U-Boot - Startup Code for MPC8220 CPUs - */ -#include -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Floating Point enable, Machine Check and Recoverable Interr. */ -#ifdef DEBUG -#define MSR_KERNEL (MSR_FP|MSR_RI) -#else -#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) -#endif - -/* - * Set up GOT: Global Offset Table - * - * Use r14 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * Version string - */ - .data - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - -/* - * Exception vectors - */ - .text - . = EXC_OFF_SYS_RESET - .globl _start -_start: - li r21, BOOTFLAG_COLD /* Normal Power-On */ - nop - b boot_cold - - . = EXC_OFF_SYS_RESET + 0x10 - - .globl _start_warm -_start_warm: - li r21, BOOTFLAG_WARM /* Software reboot */ - b boot_warm - -boot_cold: -boot_warm: - mfmsr r5 /* save msr contents */ - - /* replace default MBAR base address from 0x80000000 - to 0xf0000000 */ - -#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT) - lis r3, CFG_MBAR@h - ori r3, r3, CFG_MBAR@l - - /* MBAR is mirrored into the MBAR SPR */ - mtspr MBAR,r3 - mtspr SPRN_SPRG7W,r3 - lis r4, CFG_DEFAULT_MBAR@h - stw r3, 0(r4) -#endif /* CFG_DEFAULT_MBAR */ - - /* Initialise the MPC8220 processor core */ - /*--------------------------------------------------------------*/ - - bl init_8220_core - - /* initialize some things that are hard to access from C */ - /*--------------------------------------------------------------*/ - - /* set up stack in on-chip SRAM */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l - ori r1, r3, CFG_INIT_SP_OFFSET - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*--------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (in Flash)*/ - - mr r3, r21 - /* r3: BOOTFLAG */ - bl board_init_f /* run 1st part of board init code (in Flash)*/ - -/* - * Vector Table - */ - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) -#ifdef DEBUG - . = 0x1300 - /* - * This exception occurs when the program counter matches the - * Instruction Address Breakpoint Register (IABR). - * - * I want the cpu to halt if this occurs so I can hunt around - * with the debugger and look at things. - * - * When DEBUG is defined, both machine check enable (in the MSR) - * and checkstop reset enable (in the reset mode register) are - * turned off and so a checkstop condition will result in the cpu - * halting. - * - * I force the cpu into a checkstop condition by putting an illegal - * instruction here (at least this is the theory). - * - * well - that didnt work, so just do an infinite loop! - */ -1: b 1b -#else - STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) -#endif - STD_EXCEPTION(0x1400, SMI, UnknownException) - - STD_EXCEPTION(0x1500, Trap_15, UnknownException) - STD_EXCEPTION(0x1600, Trap_16, UnknownException) - STD_EXCEPTION(0x1700, Trap_17, UnknownException) - STD_EXCEPTION(0x1800, Trap_18, UnknownException) - STD_EXCEPTION(0x1900, Trap_19, UnknownException) - STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) - STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) - STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) - STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) - STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) - STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) - STD_EXCEPTION(0x2000, Trap_20, UnknownException) - STD_EXCEPTION(0x2100, Trap_21, UnknownException) - STD_EXCEPTION(0x2200, Trap_22, UnknownException) - STD_EXCEPTION(0x2300, Trap_23, UnknownException) - STD_EXCEPTION(0x2400, Trap_24, UnknownException) - STD_EXCEPTION(0x2500, Trap_25, UnknownException) - STD_EXCEPTION(0x2600, Trap_26, UnknownException) - STD_EXCEPTION(0x2700, Trap_27, UnknownException) - STD_EXCEPTION(0x2800, Trap_28, UnknownException) - STD_EXCEPTION(0x2900, Trap_29, UnknownException) - STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) - STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) - STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) - STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) - STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) - STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x3000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* - * This code initialises the MPC8220 processor core - * (conforms to PowerPC 603e spec) - * Note: expects original MSR contents to be in r5. - */ - - .globl init_8220_core -init_8220_core: - - /* Initialize machine status; enable machine check interrupt */ - /*--------------------------------------------------------------*/ - - li r3, MSR_KERNEL /* Set ME and RI flags */ - rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ -#ifdef DEBUG - rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ -#endif - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - /* Initialize the Hardware Implementation-dependent Registers */ - /* HID0 also contains cache control */ - /*--------------------------------------------------------------*/ - - lis r3, CFG_HID0_INIT@h - ori r3, r3, CFG_HID0_INIT@l - SYNC - mtspr HID0, r3 - - lis r3, CFG_HID0_FINAL@h - ori r3, r3, CFG_HID0_FINAL@l - SYNC - mtspr HID0, r3 - - /* Enable Extra BATs */ - mfspr r3, 1011 /* HID2 */ - lis r4, 0x0004 - ori r4, r4, 0x0000 - or r4, r4, r3 - mtspr 1011, r4 - sync - - /* clear all BAT's */ - /*--------------------------------------------------------------*/ - - li r0, 0 - mtspr DBAT0U, r0 - mtspr DBAT0L, r0 - mtspr DBAT1U, r0 - mtspr DBAT1L, r0 - mtspr DBAT2U, r0 - mtspr DBAT2L, r0 - mtspr DBAT3U, r0 - mtspr DBAT3L, r0 - mtspr DBAT4U, r0 - mtspr DBAT4L, r0 - mtspr DBAT5U, r0 - mtspr DBAT5L, r0 - mtspr DBAT6U, r0 - mtspr DBAT6L, r0 - mtspr DBAT7U, r0 - mtspr DBAT7L, r0 - mtspr IBAT0U, r0 - mtspr IBAT0L, r0 - mtspr IBAT1U, r0 - mtspr IBAT1L, r0 - mtspr IBAT2U, r0 - mtspr IBAT2L, r0 - mtspr IBAT3U, r0 - mtspr IBAT3L, r0 - mtspr IBAT4U, r0 - mtspr IBAT4L, r0 - mtspr IBAT5U, r0 - mtspr IBAT5L, r0 - mtspr IBAT6U, r0 - mtspr IBAT6L, r0 - mtspr IBAT7U, r0 - mtspr IBAT7L, r0 - SYNC - - /* invalidate all tlb's */ - /* */ - /* From the 603e User Manual: "The 603e provides the ability to */ - /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ - /* instruction invalidates the TLB entry indexed by the EA, and */ - /* operates on both the instruction and data TLBs simultaneously*/ - /* invalidating four TLB entries (both sets in each TLB). The */ - /* index corresponds to bits 15-19 of the EA. To invalidate all */ - /* entries within both TLBs, 32 tlbie instructions should be */ - /* issued, incrementing this field by one each time." */ - /* */ - /* "Note that the tlbia instruction is not implemented on the */ - /* 603e." */ - /* */ - /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ - /* incrementing by 0x1000 each time. The code below is sort of */ - /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */ - /* */ - /*--------------------------------------------------------------*/ - - li r3, 32 - mtctr r3 - li r3, 0 -1: tlbie r3 - addi r3, r3, 0x1000 - bdnz 1b - SYNC - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr - -/* Cache functions. - * - * Note: requires that all cache bits in - * HID0 are in the low half word. - */ - .globl icache_enable -icache_enable: - lis r4, 0 - ori r4, r4, CFG_HID0_INIT /* set ICE & ICFI bit */ - rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */ - - /* - * The setting of the instruction cache enable (ICE) bit must be - * preceded by an isync instruction to prevent the cache from being - * enabled or disabled while an instruction access is in progress. - */ - isync - mtspr HID0, r4 /* Enable Instr Cache & Inval cache */ - mtspr HID0, r3 /* using 2 consec instructions */ - isync - blr - - .globl icache_disable -icache_disable: - mfspr r3, HID0 - rlwinm r3, r3, 0, 17, 15 /* clear the ICE bit */ - mtspr HID0, r3 - isync - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 - blr - - .globl dcache_enable -dcache_enable: - lis r4, 0 - ori r4, r4, HID0_DCE|HID0_DCFI /* set DCE & DCFI bit */ - rlwinm r3, r4, 0, 22, 20 /* clear the DCFI bit */ - - /* Enable address translation in MSR bit */ - mfmsr r5 - ori r5, r5, 0x - - - /* - * The setting of the instruction cache enable (ICE) bit must be - * preceded by an isync instruction to prevent the cache from being - * enabled or disabled while an instruction access is in progress. - */ - isync - mtspr HID0, r4 /* Enable Data Cache & Inval cache*/ - mtspr HID0, r3 /* using 2 consec instructions */ - isync - blr - - .globl dcache_disable -dcache_disable: - mfspr r3, HID0 - rlwinm r3, r3, 0, 18, 16 /* clear the DCE bit */ - mtspr HID0, r3 - isync - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r14, r14, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ - rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 - cmpwi r7,0 - beq 9f - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ -9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ - rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 - cmpwi r7,0 - beq 7f - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r14 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - add r0,r0,r11 - stw r0,0(r3) - bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ -2: li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mfmsr r3 /* now that the vectors have */ - lis r7, MSR_IP@h /* relocated into low memory */ - ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ - andc r3, r3, r7 /* (if it was on) */ - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - - mtlr r4 /* restore link register */ - blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr diff --git a/cpu/mpc8220/traps.c b/cpu/mpc8220/traps.c deleted file mode 100644 index cdee2be..0000000 --- a/cpu/mpc8220/traps.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * linux/arch/ppc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * fixed Machine Check Reasons by Reinhard Meyer (r.meyer@emk-elektronik.de) - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -int (*debugger_exception_handler) (struct pt_regs *) = 0; -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table (unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x02000000 - -/* - * Trap & Exception support - */ - -void print_backtrace (unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf ("Call backtrace: "); - while (sp) { - if ((uint) sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf ("\n"); - printf ("%08lX ", i); - if (cnt > 32) - break; - sp = (unsigned long *) *sp; - } - printf ("\n"); -} - -void show_regs (struct pt_regs *regs) -{ - int i; - - printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, - regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0, regs->msr & MSR_ME ? 1 : 0, - regs->msr & MSR_IR ? 1 : 0, regs->msr & MSR_DR ? 1 : 0); - - printf ("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) { - printf ("GPR%02d: ", i); - } - - printf ("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) { - printf ("\n"); - } - } -} - - -void _exception (int signr, struct pt_regs *regs) -{ - show_regs (regs); - print_backtrace ((unsigned long *) regs->gpr[1]); - panic ("Exception in kernel pc %lx signal %d", regs->nip, signr); -} - -void MachineCheckException (struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table (regs->nip)) != 0) { - regs->nip = fixup; - return; - } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler - && (*debugger_exception_handler) (regs)) - return; -#endif - - printf ("Machine check in kernel mode.\n"); - printf ("Caused by (from msr): "); - printf ("regs %p ", regs); - /* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */ - switch (regs->msr & 0x000F0000) { - case (0x80000000 >> 12): - printf ("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000 >> 13): - printf ("Transfer error ack signal\n"); - break; - case (0x80000000 >> 14): - printf ("Data parity signal\n"); - break; - case (0x80000000 >> 15): - printf ("Address parity signal\n"); - break; - default: - printf ("Unknown values in msr\n"); - } - show_regs (regs); - print_backtrace ((unsigned long *) regs->gpr[1]); - panic ("machine check"); -} - -void AlignmentException (struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler - && (*debugger_exception_handler) (regs)) - return; -#endif - show_regs (regs); - print_backtrace ((unsigned long *) regs->gpr[1]); - panic ("Alignment Exception"); -} - -void ProgramCheckException (struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler - && (*debugger_exception_handler) (regs)) - return; -#endif - show_regs (regs); - print_backtrace ((unsigned long *) regs->gpr[1]); - panic ("Program Check Exception"); -} - -void SoftEmuException (struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler - && (*debugger_exception_handler) (regs)) - return; -#endif - show_regs (regs); - print_backtrace ((unsigned long *) regs->gpr[1]); - panic ("Software Emulation Exception"); -} - - -void UnknownException (struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler - && (*debugger_exception_handler) (regs)) - return; -#endif - printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception (0, regs); -} - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) -extern void do_bedbug_breakpoint (struct pt_regs *); -#endif - -void DebugException (struct pt_regs *regs) -{ - - printf ("Debugger trap at @ %lx\n", regs->nip); - show_regs (regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - do_bedbug_breakpoint (regs); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int addr_probe (uint * addr) -{ -#if 0 - int retval; - - __asm__ __volatile__ ("1: lwz %0,0(%1)\n" - " eieio\n" - " li %0,0\n" - "2:\n" - ".section .fixup,\"ax\"\n" - "3: li %0,-1\n" - " b 2b\n" - ".section __ex_table,\"a\"\n" - " .align 2\n" - " .long 1b,3b\n" - ".text":"=r" (retval):"r" (addr)); - - return (retval); -#endif - return 0; -} diff --git a/cpu/mpc8220/uart.c b/cpu/mpc8220/uart.c deleted file mode 100644 index 5f54aac..0000000 --- a/cpu/mpc8220/uart.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2004, Freescale, Inc - * TsiChung Liew, Tsi-Chung.Liew@freescale.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* - * Minimal serial functions needed to use one of the PSC ports - * as serial console interface. - */ - -#include -#include - -#define PSC_BASE MMAP_PSC1 - -#if defined(CONFIG_PSC_CONSOLE) -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; - u32 counter; - - /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ - psc->cr = 0; - psc->ipcr_acr = 0; - psc->isr_imr = 0; - - /* write to CSR: RX/TX baud rate from timers */ - psc->sr_csr = 0xdd000000; - - psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1; - - /* Setting up BaudRate */ - counter = ((gd->bus_clk / gd->baudrate)) >> 5; - counter++; - - /* write to CTUR: divide counter upper byte */ - psc->ctur = ((counter & 0xff00) << 16); - /* write to CTLR: divide counter lower byte */ - psc->ctlr = ((counter & 0x00ff) << 24); - - psc->cr = PSC_CR_RST_RX_CMD; - psc->cr = PSC_CR_RST_TX_CMD; - psc->cr = PSC_CR_RST_ERR_STS_CMD; - psc->cr = PSC_CR_RST_BRK_INT_CMD; - psc->cr = PSC_CR_RST_MR_PTR_CMD; - - psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE; - return (0); -} - -void serial_putc (const char c) -{ - volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; - - if (c == '\n') - serial_putc ('\r'); - - /* Wait for last character to go. */ - while (!(psc->sr_csr & PSC_SR_TXRDY)); - - psc->xmitbuf[0] = c; -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc (void) -{ - volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; - - /* Wait for a character to arrive. */ - while (!(psc->sr_csr & PSC_SR_RXRDY)); - return psc->xmitbuf[2]; -} - -int serial_tstc (void) -{ - volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; - - return (psc->sr_csr & PSC_SR_RXRDY); -} - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; - u32 counter; - - counter = ((gd->bus_clk / gd->baudrate)) >> 5; - counter++; - - /* write to CTUR: divide counter upper byte */ - psc->ctur = ((counter & 0xff00) << 16); - /* write to CTLR: divide counter lower byte */ - psc->ctlr = ((counter & 0x00ff) << 24); - - psc->cr = PSC_CR_RST_RX_CMD; - psc->cr = PSC_CR_RST_TX_CMD; - - psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE; -} -#endif /* CONFIG_PSC_CONSOLE */ diff --git a/cpu/mpc824x/Makefile b/cpu/mpc824x/Makefile deleted file mode 100644 index df0d64e..0000000 --- a/cpu/mpc824x/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.S -OBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \ - drivers/epic/epic1.o drivers/i2c/i2c.o pci.o bedbug_603e.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -bedbug_603e.c: - ln -s ../mpc8260/bedbug_603e.c bedbug_603e.c - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk deleted file mode 100644 index dac61d8..0000000 --- a/cpu/mpc824x/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing - -PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float diff --git a/cpu/mpc824x/cpu.c b/cpu/mpc824x/cpu.c deleted file mode 100644 index 312dfe2..0000000 --- a/cpu/mpc824x/cpu.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - * (C) Copyright 2000 - 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -int checkcpu (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned int pvr = get_pvr (); - unsigned int version = pvr >> 16; - unsigned char revision; - ulong clock = gd->cpu_clk; - char buf[32]; - - puts ("CPU: "); - - switch (version) { - case CPU_TYPE_8240: - puts ("MPC8240"); - break; - - case CPU_TYPE_8245: - puts ("MPC8245"); - break; - - default: - return -1; /*not valid for this source */ - } - - CONFIG_READ_BYTE (REVID, revision); - - if (revision) { - printf (" Revision %d.%d", - (revision & 0xf0) >> 4, - (revision & 0x0f)); - } else { - return -1; /* no valid CPU revision info */ - } - - printf (" at %s MHz:", strmhz (buf, clock)); - - printf (" %u kB I-Cache", checkicache () >> 10); - printf (" %u kB D-Cache", checkdcache () >> 10); - - puts ("\n"); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -/* L1 i-cache */ - -int checkicache (void) -{ - /*TODO*/ - return 128 * 4 * 32; -}; - -/* ------------------------------------------------------------------------- */ -/* L1 d-cache */ - -int checkdcache (void) -{ - /*TODO*/ - return 128 * 4 * 32; - -}; - -/*------------------------------------------------------------------- */ - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong msr, addr; - - /* Interrupts and MMU off */ - __asm__ ("mtspr 81, 0"); - - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~0x1030; - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; -#else - /* - * note: when CFG_MONITOR_BASE points to a RAM address, - * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid - * address. Better pick an address known to be invalid on - * your system and assign it to CFG_RESET_ADDRESS. - * "(ulong)-1" used to be a good choice for many systems... - */ - addr = CFG_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*)(void)) addr) (); - return 1; - -} - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * This is the sys_logic_clk (memory bus) divided by 4 - */ -unsigned long get_tbclk (void) -{ - return ((get_bus_freq (0) + 2L) / 4L); -} - -/* ------------------------------------------------------------------------- */ - -/* - * The MPC824x has an integrated PCI controller known as the MPC107. - * The following are MPC107 Bridge Controller and PCI Support functions - * - */ - -/* - * This procedure reads a 32-bit address MPC107 register, and returns - * a 32 bit value. It swaps the address to little endian before - * writing it to config address, and swaps the value to big endian - * before returning to the caller. - */ -unsigned int mpc824x_mpc107_getreg (unsigned int regNum) -{ - unsigned int temp; - - /* swap the addr. to little endian */ - *(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum); - temp = *(volatile unsigned int *) CHRP_REG_DATA; - return PCISWAP (temp); /* swap the data upon return */ -} - -/* - * This procedure writes a 32-bit address MPC107 register. It swaps - * the address to little endian before writing it to config address. - */ - -void mpc824x_mpc107_setreg (unsigned int regNum, unsigned int regVal) -{ - /* swap the addr. to little endian */ - *(volatile unsigned int *) CHRP_REG_ADDR = PCISWAP (regNum); - *(volatile unsigned int *) CHRP_REG_DATA = PCISWAP (regVal); - return; -} - - -/* - * Write a byte (8 bits) to a memory location. - */ -void mpc824x_mpc107_write8 (unsigned int addr, unsigned char data) -{ - *(unsigned char *) addr = data; - __asm__ ("sync"); -} - -/* - * Write a word (16 bits) to a memory location after the value - * has been byte swapped (big to little endian or vice versa) - */ - -void mpc824x_mpc107_write16 (unsigned int address, unsigned short data) -{ - *(volatile unsigned short *) address = BYTE_SWAP_16_BIT (data); - __asm__ ("sync"); -} - -/* - * Write a long word (32 bits) to a memory location after the value - * has been byte swapped (big to little endian or vice versa) - */ - -void mpc824x_mpc107_write32 (unsigned int address, unsigned int data) -{ - *(volatile unsigned int *) address = LONGSWAP (data); - __asm__ ("sync"); -} - -/* - * Read a byte (8 bits) from a memory location. - */ -unsigned char mpc824x_mpc107_read8 (unsigned int addr) -{ - return *(volatile unsigned char *) addr; -} - - -/* - * Read a word (16 bits) from a memory location, and byte swap the - * value before returning to the caller. - */ -unsigned short mpc824x_mpc107_read16 (unsigned int address) -{ - unsigned short retVal; - - retVal = BYTE_SWAP_16_BIT (*(unsigned short *) address); - return retVal; -} - - -/* - * Read a long word (32 bits) from a memory location, and byte - * swap the value before returning to the caller. - */ -unsigned int mpc824x_mpc107_read32 (unsigned int address) -{ - unsigned int retVal; - - retVal = LONGSWAP (*(unsigned int *) address); - return (retVal); -} - - -/* - * Read a register in the Embedded Utilities Memory Block address - * space. - * Input: regNum - register number + utility base address. Example, - * the base address of EPIC is 0x40000, the register number - * being passed is 0x40000+the address of the target register. - * (See epic.h for register addresses). - * Output: The 32 bit little endian value of the register. - */ - -unsigned int mpc824x_eummbar_read (unsigned int regNum) -{ - unsigned int temp; - - temp = *(volatile unsigned int *) (EUMBBAR_VAL + regNum); - temp = PCISWAP (temp); - return temp; -} - - -/* - * Write a value to a register in the Embedded Utilities Memory - * Block address space. - * Input: regNum - register number + utility base address. Example, - * the base address of EPIC is 0x40000, the register - * number is 0x40000+the address of the target register. - * (See epic.h for register addresses). - * regVal - value to be written to the register. - */ - -void mpc824x_eummbar_write (unsigned int regNum, unsigned int regVal) -{ - *(volatile unsigned int *) (EUMBBAR_VAL + regNum) = PCISWAP (regVal); - return; -} - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c deleted file mode 100644 index 7871031..0000000 --- a/cpu/mpc824x/cpu_init.c +++ /dev/null @@ -1,417 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor. Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifndef CFG_BANK0_ROW -#define CFG_BANK0_ROW 0 -#endif -#ifndef CFG_BANK1_ROW -#define CFG_BANK1_ROW 0 -#endif -#ifndef CFG_BANK2_ROW -#define CFG_BANK2_ROW 0 -#endif -#ifndef CFG_BANK3_ROW -#define CFG_BANK3_ROW 0 -#endif -#ifndef CFG_BANK4_ROW -#define CFG_BANK4_ROW 0 -#endif -#ifndef CFG_BANK5_ROW -#define CFG_BANK5_ROW 0 -#endif -#ifndef CFG_BANK6_ROW -#define CFG_BANK6_ROW 0 -#endif -#ifndef CFG_BANK7_ROW -#define CFG_BANK7_ROW 0 -#endif -#ifndef CFG_DBUS_SIZE2 -#define CFG_DBUS_SIZE2 0 -#endif - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - */ -void -cpu_init_f (void) -{ -/* MOUSSE board is initialized in asm */ -#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW) - register unsigned long val; - CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ -/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/ - -#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62) -/* Why is this here, you ask? Try, just try setting 0x8000 - * in PCIACR with CONFIG_WRITE_HALFWORD() - * this one was a stumper, and we are annoyed - */ - -#define M_CONFIG_WRITE_HALFWORD( addr, data ) \ - __asm__ __volatile__(" \ - stw %2,0(%0)\n \ - sync\n \ - sth %3,2(%1)\n \ - sync\n \ - " \ - : /* no output */ \ - : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \ - "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \ - ); - - M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000); -#endif - - CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */ - CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */ - /* - * Note that although this bit is cleared after a hard reset, it - * must be explicitly set and then cleared by software during - * initialization in order to guarantee correct operation of the - * DLL and the SDRAM_CLK[0:3] signals (if they are used). - */ - CONFIG_READ_BYTE (AMBOR, val); - CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); - CONFIG_WRITE_BYTE(AMBOR, val | 0x20); - CONFIG_WRITE_BYTE(AMBOR, val & 0xDF); -#ifdef CONFIG_MPC8245 - /* silicon bug 28 MPC8245 */ - CONFIG_READ_BYTE(AMBOR,val); - CONFIG_WRITE_BYTE(AMBOR,val|0x1); - -#if 0 - /* - * The following bug only affects older (XPC8245) processors. - * DMA transfers initiated by external devices get corrupted due - * to a hardware scheduling problem. - * - * The effect is: - * when transferring X words, the first 32 words are transferred - * OK, the next 3 x 32 words are 'old' data (from previous DMA) - * while the rest of the X words is xferred fine. - * - * Disabling 3 of the 4 32 word hardware buffers solves the problem - * with no significant performance loss. - */ - - CONFIG_READ_BYTE(PCMBCR,val); - /* in order not to corrupt data which is being read over the PCI bus - * with the PPC as slave, we need to reduce the number of PCMRBs to 1, - * 4.11 in the processor user manual - * */ - -#if 1 - CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */ -#else - CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */ - CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */ - /* default, 4 PCMRBs are used */ -#endif -#endif -#endif - - CONFIG_READ_WORD(PICR1, val); -#if defined(CONFIG_MPC8240) - CONFIG_WRITE_WORD( PICR1, - (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) | - PIRC1_MSK | PICR1_PROC_TYPE_603E | - PICR1_FLASH_WR_EN | PICR1_MCP_EN | - PICR1_CF_DPARK | PICR1_EN_PCS | - PICR1_CF_APARK ); -#elif defined(CONFIG_MPC8245) - CONFIG_WRITE_WORD( PICR1, - (val & (PICR1_RCS0)) | - PICR1_PROC_TYPE_603E | - PICR1_FLASH_WR_EN | PICR1_MCP_EN | - PICR1_CF_DPARK | PICR1_NO_BUSW_CK | - PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */ -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - - CONFIG_READ_WORD(PICR2, val); - val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/ -#ifndef CONFIG_PN62 - val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/ -#endif - CONFIG_WRITE_WORD(PICR2, val); - - CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR); -#ifndef CFG_RAMBOOT - CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | - (CFG_BANK0_ROW) | - (CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) | - (CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) | - (CFG_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) | - (CFG_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) | - (CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) | - (CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) | - (CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) | - (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)); -#endif - -#if defined(CFG_ASRISE) && defined(CFG_ASFALL) - CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT | - CFG_ASRISE << MCCR2_ASRISE_SHIFT | - CFG_ASFALL << MCCR2_ASFALL_SHIFT); -#else - CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT); -#endif - -#if defined(CONFIG_MPC8240) - CONFIG_WRITE_WORD(MCCR3, - (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CFG_REFREC << MCCR3_REFREC_SHIFT) | - (CFG_RDLAT << MCCR3_RDLAT_SHIFT)); -#elif defined(CONFIG_MPC8245) - CONFIG_WRITE_WORD(MCCR3, - (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CFG_REFREC << MCCR3_REFREC_SHIFT)); -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -/* this is gross. We think these should all be the same, and various boards - * should define CFG_ACTORW to 0 if they don't want to set it, or even, if - * its not set, we define it to zero in this file - */ -#if defined(CONFIG_CU824) || defined(CONFIG_PN62) - CONFIG_WRITE_WORD(MCCR4, - (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | - MCCR4_BIT21 | - (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CFG_BSTOPRE & 0x0003) <> 6) << MCCR4_BSTOPRE6TO9_SHIFT)); -#elif defined(CONFIG_MPC8240) - CONFIG_WRITE_WORD(MCCR4, - (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | - MCCR4_BIT21 | - (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CFG_BSTOPRE & 0x0003) <> 6) <> 6) <> MICR_ADDR_SHIFT) | - (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMSAR1, - ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MSAR2, - ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMSAR2, - ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MEAR1, - ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMEAR1, - ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(MEAR2, - ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); - CONFIG_WRITE_WORD(EMEAR2, - ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - - CONFIG_WRITE_BYTE(ODCR, CFG_ODCR); -#ifdef CFG_DLL_MAX_DELAY - CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY); /* needed to make DLL lock */ -#endif -#if defined(CFG_DLL_EXTEND) && defined(CFG_PCI_HOLD_DEL) - CONFIG_WRITE_BYTE(PMCR2, CFG_DLL_EXTEND | CFG_PCI_HOLD_DEL); -#endif -#if defined(MIOCR2) && defined(CFG_SDRAM_DSCD) - CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD); /* change memory input */ -#endif /* setup & hold time */ - - CONFIG_WRITE_BYTE(MBER, - CFG_BANK0_ENABLE | - (CFG_BANK1_ENABLE << 1) | - (CFG_BANK2_ENABLE << 2) | - (CFG_BANK3_ENABLE << 3) | - (CFG_BANK4_ENABLE << 4) | - (CFG_BANK5_ENABLE << 5) | - (CFG_BANK6_ENABLE << 6) | - (CFG_BANK7_ENABLE << 7)); - -#ifdef CFG_PGMAX - CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX); -#endif - - /* ! Wait 200us before initialize other registers */ - /*FIXME: write a decent udelay wait */ - __asm__ __volatile__( - " mtctr %0 \n \ - 0: bdnz 0b\n" - : - : "r" (0x10000)); - - CONFIG_READ_WORD(MCCR1, val); - CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */ - __asm__ __volatile__("eieio"); - -#endif /* !CONFIG_MOUSSE && !CONFIG_BMW */ -} - - -#ifdef CONFIG_MOUSSE -#ifdef INCLUDE_MPC107_REPORT -struct MPC107_s { - unsigned int iobase; - char desc[120]; -} MPC107Regs[] = { - { BMC_BASE + 0x00, "MPC107 Vendor/Device ID" }, - { BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" }, - { BMC_BASE + 0x08, "MPC107 Revision" }, - { BMC_BASE + 0x0C, "MPC107 Cache Line Size" }, - { BMC_BASE + 0x10, "MPC107 LMBAR" }, - { BMC_BASE + 0x14, "MPC824x PCSR" }, - { BMC_BASE + 0xA8, "MPC824x PICR1" }, - { BMC_BASE + 0xAC, "MPC824x PICR2" }, - { BMC_BASE + 0x46, "MPC824x PACR" }, - { BMC_BASE + 0x310, "MPC824x ITWR" }, - { BMC_BASE + 0x300, "MPC824x OMBAR" }, - { BMC_BASE + 0x308, "MPC824x OTWR" }, - { BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" }, - { BMC_BASE + 0x78, "MPC107 EUMBAR" }, - { BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" }, - { BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" }, - { BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" }, - { BMC_BASE + 0xE0, "MPC107 AMBOR Register" }, - { BMC_BASE + 0xF0, "MPC107 MCCR1 Register" }, - { BMC_BASE + 0xF4, "MPC107 MCCR2 Register" }, - { BMC_BASE + 0xF8, "MPC107 MCCR3 Register" }, - { BMC_BASE + 0xFC, "MPC107 MCCR4 Register" }, -}; -#define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0])) -#endif /* INCLUDE_MPC107_REPORT */ -#endif /* CONFIG_MOUSSE */ - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ -#ifdef CONFIG_MOUSSE -#ifdef INCLUDE_MPC107_REPORT - unsigned int tmp = 0, i; -#endif - /* - * Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg). - * This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can - * be accessed. - */ - -#ifdef CONFIG_MPC8240 /* only on MPC8240 */ - mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL); - /* MOT/SPS: Issue #10002, PCI (FD Alias enable) */ - mpc824x_mpc107_setreg (AMBOR, 0x000000C0); -#endif - - -#ifdef INCLUDE_MPC107_REPORT - /* Check MPC824x PCI Device and Vendor ID */ - while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) { - printf (" MPC107: offset=0x%x, val = 0x%x\n", - BMC_BASE, - tmp); - } - - for (i = 0; i < N_MPC107_Regs; i++) { - printf (" 0x%x/%s = 0x%x\n", - MPC107Regs[i].iobase, - MPC107Regs[i].desc, - mpc824x_mpc107_getreg (MPC107Regs[i].iobase)); - } - - printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L)); - printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U)); - printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L)); - printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U)); - printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L)); - printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U)); - printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L)); - printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U)); - printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L)); - printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U)); - printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L)); - printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U)); - printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L)); - printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U)); - printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L)); - printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U)); -#endif /* INCLUDE_MPC107_REPORT */ -#endif /* CONFIG_MOUSSE */ - return (0); -} diff --git a/cpu/mpc824x/drivers/dma/Makefile b/cpu/mpc824x/drivers/dma/Makefile deleted file mode 100644 index 59e2fac..0000000 --- a/cpu/mpc824x/drivers/dma/Makefile +++ /dev/null @@ -1,83 +0,0 @@ -########################################################################## -# -# Copyright Motorola, Inc. 1997 -# ALL RIGHTS RESERVED -# -# You are hereby granted a copyright license to use, modify, and -# distribute the SOFTWARE so long as this entire notice is retained -# without alteration in any modified and/or redistributed versions, -# and that such modified versions are clearly identified as such. -# No licenses are granted by implication, estoppel or otherwise under -# any patents or trademarks of Motorola, Inc. -# -# The SOFTWARE is provided on an "AS IS" basis and without warranty. -# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS -# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED -# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR -# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH -# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS -# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. -# -# To the maximum extent permitted by applicable law, IN NO EVENT SHALL -# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER -# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF -# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR -# INABILITY TO USE THE SOFTWARE. -# -############################################################################ -TARGET = libdma.a - -DEBUG = -DDMADBG -LST = -Hanno -S -OPTIM = -CC = /risc/tools/pkgs/metaware/bin/hcppc -CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc -CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) -PREP = $(CC) $(CFLAGS) -P - -# Assembler used to build the .s files (for the board version) - -ASOPT = -big_si -c -ASDEBUG = -l -fm -AS = /risc/tools/pkgs/metaware/bin/asppc - -# Linker to bring .o files together into an executable. - -LKOPT = -Bbase=0 -q -r -Qn -LKCMD = -LINK = /risc/tools/pkgs/metaware/bin/ldppc $(LKCMD) $(LKOPT) - -# DOS Utilities - -DEL = rm -COPY = cp -LIST = ls - -OBJECTS = dma1.o dma2.o - -all: $(TARGET) - -$(TARGET): $(OBJECTS) - $(LINK) $(OBJECTS) -o $@ - -objects: dma1.o - -clean: - $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) - -.s.o: - $(DEL) -f $*.i - $(PREP) -Hasmcpp $< - $(AS) $(ASOPT) $*.i -# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst - -.c.o: - $(CCobj) $< - -.c.s: - $(CCobj) $(LST) $< - -dma1.o: dma_export.h dma.h dma1.c - -dma2.o: dma.h dma2.s diff --git a/cpu/mpc824x/drivers/dma/Makefile_pc b/cpu/mpc824x/drivers/dma/Makefile_pc deleted file mode 100644 index 8df2a3c..0000000 --- a/cpu/mpc824x/drivers/dma/Makefile_pc +++ /dev/null @@ -1,89 +0,0 @@ -########################################################################## -# -# makefile_pc for use with mksnt tools drivers/dma -# -# Copyright Motorola, Inc. 1997 -# ALL RIGHTS RESERVED -# -# You are hereby granted a copyright license to use, modify, and -# distribute the SOFTWARE so long as this entire notice is retained -# without alteration in any modified and/or redistributed versions, -# and that such modified versions are clearly identified as such. -# No licenses are granted by implication, estoppel or otherwise under -# any patents or trademarks of Motorola, Inc. -# -# The SOFTWARE is provided on an "AS IS" basis and without warranty. -# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS -# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED -# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR -# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH -# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS -# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. -# -# To the maximum extent permitted by applicable law, IN NO EVENT SHALL -# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER -# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF -# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR -# INABILITY TO USE THE SOFTWARE. -# -############################################################################ -TARGET = libdma.a - -DEBUG = -DDMADBG -LST = -Hanno -S -OPTIM = -CC = m:/old_tools/tools/hcppc/bin/hcppc -CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc -CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) -PREP = $(CC) $(CFLAGS) -P - -# Assembler used to build the .s files (for the board version) - -ASOPT = -big_si -c -ASDEBUG = -l -fm -AS = m:/old_tools/tools/hcppc/bin/asppc - -# Linker to bring .o files together into an executable. - -LKOPT = -Bbase=0 -q -r -Qn -LKCMD = -LINK = m:/old_tools/tools/hcppc/bin/ldppc $(LKCMD) $(LKOPT) - -# DOS Utilities - -DEL = rm -COPY = cp -LIST = ls - -OBJECTS = dma1.o dma2.o - -all: $(TARGET) - -$(TARGET): $(OBJECTS) - $(LINK) $(OBJECTS) -o $@ - -objects: dma1.o - -clean: - $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) - -.s.o: - $(DEL) -f $*.i - $(PREP) -Hasmcpp $< - $(AS) $(ASOPT) $*.i -# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst - -.c.o: - $(CCobj) $< - -.c.s: - $(CCobj) $(LST) $< - -dma1.o: dma_export.h dma.h dma1.c - $(CCobj) $< - -dma2.o: dma.h dma2.s - $(DEL) -f $*.i - $(PREP) -Hasmcpp $< - $(AS) $(ASOPT) $*.i diff --git a/cpu/mpc824x/drivers/dma/README b/cpu/mpc824x/drivers/dma/README deleted file mode 100644 index 06f4bc0..0000000 --- a/cpu/mpc824x/drivers/dma/README +++ /dev/null @@ -1,100 +0,0 @@ -CONTENT: - - dma.h - dma1.c - dma2.s - -WHAT ARE THESE FILES: - -These files contain MPC8240 (Kahlua) DMA controller -driver routines. The driver routines are not -written for any specific operating system. -They serves the purpose of code sample, and -jump-start for using the MPC8240 DMA controller. - -For the reason of correctness of C language -syntax, these files are compiled by Metaware -C compiler and assembler. - -ENDIAN NOTATION: - -The algorithm is designed for big-endian mode, -software is responsible for byte swapping. - -USAGE: - -1. The host system that is running on MPC8240 - or using MPC8240 as I/O device shall link - the files listed here. The memory location - of driver routines shall take into account of - that driver routines need to run in supervisor - mode and they process DMA controller interrupt. - -2. The host system is responsible for configuring - the MPC8240 including Embedded Utilities Memory - Block. Since the DMA controller on MPC8240 can - be accessed by either local 603e core or the host - that MPC8240 serves as I/O processor through host - PCI configuration, it is important that the local - processor uses EUMBBAR to access its local DMA - controller while the PCI master uses I/O - processor's PCSRBAR to access the DMA controller - on I/O device. - - To qualify whether is EUMBBAR or PCSRBAR, one - additional parameter is requied from the host - system, LOCAL or REMOTE so that the base value - can be correctly interpreted. - -3. If the host system is also using the EPIC unit - on MPC8240, the system can register the - DMA_ISR with the EPIC including other - desired resources. - - If the host system does not using the EPIC unit - on MPC8240, DMA_ISR function can be called for - each desired time interval. - - In both cases, the host system is free to - provide its own interrupt service routine. - -4. To start a direct mode DMA transaction, - use DMA_Bld_Curr with the start parameter - set to 1. - - To start a chaining mode DMA transaction, - the application shall build descriptors - in memory first, next, use DMA_Bld_Desp - with the start parameter set to 1. - -5. DMA_Start function clears, then sets the CS - bit of DMA mode register. - - DMA_Halt function clears the CS bit of DMA - mode register. - - These functions can be used to start and - halt the DMA transaction. - - If the chaining descriptors has been - modified since the last time a DMA - transaction started, use DMA_Chn_Cnt - function to let DMA controller process - the modified descriptor chain without - stopping or disturbing the current DMA - transaction. - - It is the host system's responsibility of - setting up the correct DMA transfer mode - and pass the correct memory address parameters. - -6. It is the host system's responsibility of - queueing the DMA I/O request. The host - system can call the DMA_ISR with its own - desired interrupt service subroutines to - handle each individual interrupt and queued - DMA I/O requests. - -7. The DMA driver routines contains a set - of utilities, Set and Get, for host system - to query and modify the desired DMA registers. diff --git a/cpu/mpc824x/drivers/dma/dma.h b/cpu/mpc824x/drivers/dma/dma.h deleted file mode 100644 index a21be74..0000000 --- a/cpu/mpc824x/drivers/dma/dma.h +++ /dev/null @@ -1,326 +0,0 @@ -#ifndef DMA_H -#define DMA_H -/******************************************************* - * - * copyright @ Motorola 1999 - * - *******************************************************/ -#define NUM_DMA_REG 7 -#define DMA_MR_REG 0 -#define DMA_SR_REG 1 -#define DMA_CDAR_REG 2 -#define DMA_SAR_REG 3 -#define DMA_DAR_REG 4 -#define DMA_BCR_REG 5 -#define DMA_NDAR_REG 6 - -typedef enum _dmastatus -{ - DMASUCCESS = 0x1000, - DMALMERROR, - DMAPERROR, - DMACHNBUSY, - DMAEOSINT, - DMAEOCAINT, - DMAINVALID, - DMANOEVENT, -} DMAStatus; - -typedef enum _location -{ - LOCAL = 0, /* local processor accesses on board DMA, - local processor's eumbbar is required */ - REMOTE = 1, /* PCI master accesses DMA on I/O board, - I/O processor's pcsrbar is required */ -} LOCATION; - -typedef enum dma_mr_bit -{ - IRQS = 0x00080000, - PDE = 0x00040000, - DAHTS = 0x00030000, - SAHTS = 0x0000c000, - DAHE = 0x00002000, - SAHE = 0x00001000, - PRC = 0x00000c00, - EIE = 0x00000080, - EOTIE = 0x00000040, - DL = 0x00000008, - CTM = 0x00000004, - CC = 0x00000002, - CS = 0x00000001, -} DMA_MR_BIT; - -typedef enum dma_sr_bit -{ - LME = 0x00000080, - PE = 0x00000010, - CB = 0x00000004, - EOSI = 0x00000002, - EOCAI = 0x00000001, -} DMA_SR_BIT; - -/* structure for DMA Mode Register */ -typedef struct _dma_mr -{ - unsigned int reserved0 : 12; - unsigned int irqs : 1; - unsigned int pde : 1; - unsigned int dahts : 2; - unsigned int sahts : 2; - unsigned int dahe : 1; - unsigned int sahe : 1; - unsigned int prc : 2; - unsigned int reserved1 : 1; - unsigned int eie : 1; - unsigned int eotie : 1; - unsigned int reserved2 : 3; - unsigned int dl : 1; - unsigned int ctm : 1; - /* if chaining mode is enabled, any time, user can modify the - * descriptor and does not need to halt the current DMA transaction. - * Set CC bit, enable DMA to process the modified descriptors - * Hardware will clear this bit each time, DMA starts. - */ - unsigned int cc : 1; - /* cs bit has dua role, halt the current DMA transaction and - * (re)start DMA transaction. In chaining mode, if the descriptor - * needs modification, cs bit shall be used not the cc bit. - * Hardware will not set/clear this bit each time DMA transaction - * stops or starts. Software shall do it. - * - * cs bit shall not be used to halt chaining DMA transaction for - * modifying the descriptor. That is the role of CC bit. - */ - unsigned int cs : 1; -} DMA_MR; - -/* structure for DMA Status register */ -typedef struct _dma_sr -{ - unsigned int reserved0 : 24; - unsigned int lme : 1; - unsigned int reserved1 : 2; - unsigned int pe : 1; - unsigned int reserved2 : 1; - unsigned int cb : 1; - unsigned int eosi : 1; - unsigned int eocai : 1; -} DMA_SR; - -/* structure for DMA current descriptor address register */ -typedef struct _dma_cdar -{ - unsigned int cda : 27; - unsigned int snen : 1; - unsigned int eosie : 1; - unsigned int ctt : 2; - unsigned int eotd : 1; -} DMA_CDAR; - -/* structure for DMA byte count register */ -typedef struct _dma_bcr -{ - unsigned int reserved : 6; - unsigned int bcr : 26; -} DMA_BCR; - -/* structure for DMA Next Descriptor Address register */ -typedef struct _dma_ndar -{ - unsigned int nda : 27; - unsigned int ndsnen : 1; - unsigned int ndeosie: 1; - unsigned int ndctt : 2; - unsigned int eotd : 1; -} DMA_NDAR; - -/* structure for DMA current transaction info */ -typedef struct _dma_curr -{ - unsigned int src_addr; - unsigned int dest_addr; - unsigned int byte_cnt; -} DMA_CURR; - -/************************* Kernel API******************** - * Kernel APIs are used to interface with O.S. kernel. - * They are the functions required by O.S. kernel to - * provide I/O service. - ********************************************************/ - -/**************DMA Device Control Functions ********/ - -/** - * Note: - * - * In all following functions, the host (KAHLUA) processor has a - * choice of accessing on board local DMA (LOCAL), - * or DMA on a distributed KAHLUA (REMOTE). In either case, - * the caller shall pass the configured embedded utility memory - * block base address relative to the DMA. If LOCAL DMA is used, - * this parameter shall be EUMBBAR, if REMOTE is used, the - * parameter shall be the corresponding PCSRBAR. - **/ - -/************************************************************** - * function: DMA_Get_Stat - * - * description: return the content of status register of - * the given DMA channel - * if error, return DMAINVALID. Otherwise return - * DMASUCCESS. - * - **************************************************************/ -static DMAStatus DMA_Get_Stat( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_SR * ); - -/************************************************************** - * function: DMA_Get_Mode - * - * description: return the content of mode register of the - * given DMA channel - * if error, return DMAINVALID. Otherwise return DMASUCCESS. - * - **************************************************************/ -static DMAStatus DMA_Get_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR * ); - -/************************************************************** - * function: DMA_Set_Mode - * - * description: Set a new mode to a given DMA channel - * return DMASUCCESS if success, otherwise return DMACHNINVALID - * - * note: It is not a good idea of changing the DMA mode during - * the middle of a transaction. - **************************************************************/ -static DMAStatus DMA_Set_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR mode ); - -/************************************************************* - * function: DMA_ISR - * - * description: DMA interrupt service routine - * return DMAStatus based on the status - * - *************************************************************/ -static DMAStatus DMA_ISR( unsigned int eumbbar, - unsigned int channel, - DMAStatus (*lme_func)( unsigned int, unsigned int, DMAStatus ), - DMAStatus (*pe_func) ( unsigned int, unsigned int, DMAStatus ), - DMAStatus (*eosi_func)( unsigned int, unsigned int, DMAStatus ), - DMAStatus (*eocai_func)(unsigned int, unsigned int, DMAStatus )); - -static DMAStatus dma_error_func( unsigned int, unsigned int, DMAStatus ); - -/********************* DMA I/O function ********************/ - -/************************************************************ - * function: DMA_Start - * - * description: start a given DMA channel transaction - * return DMASUCCESS if success, otherwise return DMACHNINVALID - * - * note: this function will clear DMA_MR(CC) first, then - * set DMA_MR(CC). - ***********************************************************/ -static DMAStatus DMA_Start( LOCATION, unsigned int eumbbar,unsigned int channel ); - -/*********************************************************** - * function: DMA_Halt - * - * description: halt the current dma transaction on the specified - * channel. - * return DMASUCCESS if success, otherwise return DMACHNINVALID - * - * note: if the specified DMA channel is idle, nothing happens - *************************************************************/ -static DMAStatus DMA_Halt( LOCATION, unsigned int eumbbar,unsigned int channel ); - -/************************************************************* - * function: DMA_Chn_Cnt - * - * description: set the DMA_MR(CC) bit for a given channel - * that is in chaining mode. - * return DMASUCCESS if successfule, otherwise return DMACHNINVALID - * - * note: if the given channel is not in chaining mode, nothing - * happen. - * - *************************************************************/ -static DMAStatus DMA_Chn_Cnt( LOCATION, unsigned int eumbbar,unsigned int channel ); - -/*********************** App. API *************************** - * App. API are the APIs Kernel provides for the application - * level program - ************************************************************/ -/************************************************************** - * function: DMA_Bld_Curr - * - * description: set current src, dest, byte count registers - * according to the desp for a given channel - * - * if the given channel is busy, no change made, - * return DMACHNBUSY. - * - * otherwise return DMASUCCESS. - * - * note: - **************************************************************/ -static DMAStatus DMA_Bld_Curr( LOCATION, - unsigned int eumbbar, - unsigned int channel, - DMA_CURR desp ); - -/************************************************************** - * function: DMA_Poke_Curr - * - * description: poke the current src, dest, byte count registers - * for a given channel. - * - * return DMASUCCESS if no error otherwise return DMACHNERROR - * - * note: Due to the undeterministic parallelism, in chaining - * mode, the value returned by this function shall - * be taken as reference when the query is made rather - * than the absolute snapshot when the value is returned. - **************************************************************/ -static DMAStatus DMA_Poke_Curr( LOCATION, - unsigned int eumbbar, - unsigned int channel, - DMA_CURR* desp ); - -/************************************************************** - * function: DMA_Bld_Desp - * - * description: set current descriptor address register - * according to the desp for a given channel - * - * if the given channel is busy return DMACHNBUSY - * and no change made, otherwise return DMASUCCESS. - * - * note: - **************************************************************/ -static DMAStatus DMA_Bld_Desp( LOCATION host, - unsigned int eumbbar, - unsigned int channel, - DMA_CDAR desp ); - -/************************************************************** - * function: DMA_Poke_Desp - * - * description: poke the current descriptor address register - * for a given channel - * - * return DMASUCCESS if no error otherwise return - * DMAINVALID - * - * note: Due to the undeterministic parallellism of DMA operation, - * the value returned by this function shall be taken as - * the most recently used descriptor when the last time - * DMA starts a chaining mode operation. - **************************************************************/ -static DMAStatus DMA_Poke_Desp( LOCATION, - unsigned int eumbbar, - unsigned int channel, - DMA_CDAR *desp ); - -#endif diff --git a/cpu/mpc824x/drivers/dma/dma1.c b/cpu/mpc824x/drivers/dma/dma1.c deleted file mode 100644 index 9c85267..0000000 --- a/cpu/mpc824x/drivers/dma/dma1.c +++ /dev/null @@ -1,801 +0,0 @@ -/************************************************************ - * - * copyright @ Motorola, 1999 - * - * App. API - * - * App. API are the APIs Kernel provides for the application - * level program - * - ************************************************************/ -#include "dma_export.h" -#include "dma.h" - -/* Define a macro to use an optional application-layer print function, if - * one was passed to the library during initialization. If there was no - * function pointer passed, this protects against referencing a NULL pointer. - * Also define The global variable that holds the passed pointer. - */ -#define PRINT if ( app_print ) app_print -static int (*app_print)(char *,...); - -/* Set by call to get_eumbbar during DMA_Initialize. - * This could be globally available to the library, but there is - * an advantage to passing it as a parameter: it is already in a register - * and doesn't have to be loaded from memory. Also, that is the way the - * library was already implemented and I don't want to change it without - * a more detailed analysis. - * It is being set as a global variable during initialization to hide it from - * the DINK application layer, because it is Kahlua-specific. I think that - * get_eumbbar, load_runtime_reg, and store_runtime_reg should be defined in - * a Kahlua-specific library dealing with the embedded utilities memory block. - * Right now, get_eumbbar is defined in dink32/kahlua.s. The other two are - * defined in dink32/drivers/i2c/i2c2.s, drivers/dma/dma2.s, etc. - */ -static unsigned int Global_eumbbar = 0; -extern unsigned int get_eumbbar(); - - -extern unsigned int load_runtime_reg( unsigned int eumbbar, unsigned int reg ); -#pragma Alias( load_runtime_reg, "load_runtime_reg" ); - -extern void store_runtime_reg( unsigned int eumbbar, unsigned int reg, unsigned int val ); -#pragma Alias( store_runtime_reg, "store_runtime_reg" ); - -unsigned int dma_reg_tb[][14] = { - /* local DMA registers */ - { - /* DMA_0_MR */ 0x00001100, - /* DMA_0_SR */ 0x00001104, - /* DMA_0_CDAR */ 0x00001108, - /* DMA_0_SAR */ 0x00001110, - /* DMA_0_DAR */ 0x00001118, - /* DMA_0_BCR */ 0x00001120, - /* DMA_0_NDAR */ 0x00001124, - /* DMA_1_MR */ 0x00001200, - /* DMA_1_SR */ 0x00001204, - /* DMA_1_CDAR */ 0x00001208, - /* DMA_1_SAR */ 0x00001210, - /* DMA_1_DAR */ 0x00001218, - /* DMA_1_BCR */ 0x00001220, - /* DMA_1_NDAR */ 0x00001224, - }, - /* remote DMA registers */ - { - /* DMA_0_MR */ 0x00000100, - /* DMA_0_SR */ 0x00000104, - /* DMA_0_CDAR */ 0x00000108, - /* DMA_0_SAR */ 0x00000110, - /* DMA_0_DAR */ 0x00000118, - /* DMA_0_BCR */ 0x00000120, - /* DMA_0_NDAR */ 0x00000124, - /* DMA_1_MR */ 0x00000200, - /* DMA_1_SR */ 0x00000204, - /* DMA_1_CDAR */ 0x00000208, - /* DMA_1_SAR */ 0x00000210, - /* DMA_1_DAR */ 0x00000218, - /* DMA_1_BCR */ 0x00000220, - /* DMA_1_NDAR */ 0x00000224, - }, -}; - -/* API functions */ - -/* Initialize DMA unit with the following: - * optional pointer to application layer print function - * - * These parameters may be added: - * ??? - * Interrupt enables, modes, etc. are set for each transfer. - * - * This function must be called before DMA unit can be used. - */ -extern -DMA_Status DMA_Initialize( int (*p)(char *,...)) -{ - DMAStatus status; - /* establish the pointer, if there is one, to the application's "printf" */ - app_print = p; - - /* If this is the first call, get the embedded utilities memory block - * base address. I'm not sure what to do about error handling here: - * if a non-zero value is returned, accept it. - */ - if ( Global_eumbbar == 0) - Global_eumbbar = get_eumbbar(); - if ( Global_eumbbar == 0) - { - PRINT( "DMA_Initialize: can't find EUMBBAR\n" ); - return DMA_ERROR; - } - - return DMA_SUCCESS; -} - - -/* Perform the DMA transfer, only direct mode is currently implemented. - * At this point, I think it would be better to define a different - * function for chaining mode. - * Also, I'm not sure if it is appropriate to have the "generic" API - * accept snoop and int_steer parameters. The DINK user interface allows - * them, so for now I'll leave them. - * - * int_steer controls DMA interrupt steering to PCI or local processor - * type is the type of transfer: M2M, M2P, P2M, P2P - * source is the source address of the data - * dest is the destination address of the data - * len is the length of data to transfer - * channel is the DMA channel to use for the transfer - * snoop is the snoop enable control - */ -extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer, - DMA_TRANSFER_TYPE type, - unsigned int source, - unsigned int dest, - unsigned int len, - DMA_CHANNEL channel, - DMA_SNOOP_MODE snoop) -{ - DMA_MR md; - DMA_CDAR cdar; - /* it's inappropriate for curr to be a struct, but I'll leave it */ - DMA_CURR curr; - - DMAStatus stat; - - /* The rest of this code was moved from device.c test_dma to here. - * It needs to be cleaned up and validated, but at least it is removed - * from the application and API. Most of the mode is left hard coded. - * This should be changed after the final API is defined and the user - * application has a way to control the transfer. - * - */ - - if ( DMA_Get_Mode( LOCAL, Global_eumbbar, channel, &md ) != DMASUCCESS ) - { - return DMA_ERROR; - } - - md.irqs = int_steer; - md.pde = 0; - md.dahts = 3; /* 8 - byte */ - md.sahts = 3; /* 8 - byte */ - md.dahe = 0; - md.sahe = 0; - md.prc = 0; - /* if steering interrupts to local processor, use polling mode */ - if ( int_steer == DMA_INT_STEER_PCI ) - { - md.eie = 1; - md.eotie = 1; - } else { - md.eie = 0; - md.eotie = 0; - } - md.dl = 0; - md.ctm = 1; /* direct mode */ - md.cc = 0; - - /* validate the length range */ - if (len > 0x3ffffff ) - { - PRINT( "dev DMA: length of transfer too large: %d\n", len ); - return DMA_ERROR; - } - - /* inappropriate to use a struct, but leave as is for now */ - curr.src_addr = source; - curr.dest_addr = dest; - curr.byte_cnt = len; - - (void)DMA_Poke_Desp( LOCAL, Global_eumbbar, channel, &cdar ); - cdar.snen = snoop; - cdar.ctt = type; - - if ( ( stat = DMA_Bld_Desp( LOCAL, Global_eumbbar, channel, cdar )) - != DMASUCCESS || - ( stat = DMA_Bld_Curr( LOCAL, Global_eumbbar, channel, curr )) - != DMASUCCESS || - ( stat = DMA_Set_Mode( LOCAL, Global_eumbbar, channel, md )) - != DMASUCCESS || - ( stat = DMA_Start( LOCAL, Global_eumbbar, channel )) - != DMASUCCESS ) - { - if ( stat == DMACHNBUSY ) - { - PRINT( "dev DMA: channel %d busy.\n", channel ); - } - else - { - PRINT( "dev DMA: invalid channel request.\n", channel ); - } - - return DMA_ERROR; - } - -/* Since we are interested at the DMA performace right now, - we are going to do as less as possible to burden the - 603e core. - - if you have epic enabled or don't care the return from - DMA operation, you can just return SUCCESS. - - if you don't have epic enabled and care the DMA result, - you can use the polling method below. - - Note: I'll attempt to activate the code for handling polling. - */ - -#if 0 - /* if steering interrupt to local processor, let it handle results */ - if ( int_steer == DMA_INT_STEER_LOCAL ) - { - return DMA_SUCCESS; - } - - /* polling since interrupt goes to PCI */ - do - { - stat = DMA_ISR( Global_eumbbar, channel, dma_error_func, - dma_error_func, dma_error_func, dma_error_func ); - } - while ( stat == DMANOEVENT ); -#endif - - return DMA_SUCCESS; -} - -/* DMA library internal functions */ - -/** - * Note: - * - * In all following functions, the host (KAHLUA) processor has a - * choice of accessing on board local DMA (LOCAL), - * or DMA on a distributed KAHLUA (REMOTE). In either case, - * the caller shall pass the configured embedded utility memory - * block base address relative to the DMA. If LOCAL DMA is used, - * this parameter shall be EUMBBAR, if REMOTE is used, the - * parameter shall be the corresponding PCSRBAR. - **/ - -/************************************************************** - * function: DMA_Get_Stat - * - * description: return the content of status register of - * the given DMA channel - * - * if error, reserved0 field all 1s. - **************************************************************/ -static -DMAStatus DMA_Get_Stat( LOCATION host, unsigned int eumbbar, unsigned int channel, DMA_SR *stat ) -{ - unsigned int tmp; - - if ( channel != 0 && channel != 1 || stat == 0 ) - { - return DMAINVALID; - } - - tmp = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SR_REG] ); -#ifdef DMADBG0 - PRINT( "%s(%d): %s DMA %d (0x%08x) stat = 0x%08x\n", __FILE__, __LINE__, - ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SR_REG], tmp ); -#endif - - stat->reserved0 = ( tmp & 0xffffff00 ) >> 8; - stat->lme = ( tmp & 0x00000080 ) >> 7; - stat->reserved1 = ( tmp & 0x00000060 ) >> 5; - stat->pe = ( tmp & 0x00000010 ) >> 4; - stat->reserved2 = ( tmp & 0x00000008 ) >> 3; - stat->cb = ( tmp & 0x00000004 ) >> 2; - stat->eosi = ( tmp & 0x00000002 ) >> 1; - stat->eocai = ( tmp & 0x00000001 ); - - return DMASUCCESS; -} - -/************************************************************** - * function: DMA_Get_Mode - * - * description: return the content of mode register of the - * given DMA channel - * - * if error, return DMAINVALID, otherwise return - * DMASUCCESS - **************************************************************/ -static -DMAStatus DMA_Get_Mode( LOCATION host, unsigned eumbbar, unsigned int channel, DMA_MR *mode ) -{ - unsigned int tmp; - if ( channel != 0 && channel != 1 || mode == 0 ) - { - return DMAINVALID; - } - - tmp = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_MR_REG] ); - -#ifdef DMADBG0 - PRINT( "%s(%d): %s DMA %d (0x%08x) mode = 0x%08x\n", __FILE__, __LINE__, - ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_MR_REG], tmp ); -#endif - - mode->reserved0 = (tmp & 0xfff00000) >> 20; - mode->irqs = (tmp & 0x00080000) >> 19; - mode->pde = (tmp & 0x00040000) >> 18; - mode->dahts = (tmp & 0x00030000) >> 16; - mode->sahts = (tmp & 0x0000c000) >> 14; - mode->dahe = (tmp & 0x00002000) >> 13; - mode->sahe = (tmp & 0x00001000) >> 12; - mode->prc = (tmp & 0x00000c00) >> 10; - mode->reserved1 = (tmp & 0x00000200) >> 9; - mode->eie = (tmp & 0x00000100) >> 8; - mode->eotie = (tmp & 0x00000080) >> 7; - mode->reserved2 = (tmp & 0x00000070) >> 4; - mode->dl = (tmp & 0x00000008) >> 3; - mode->ctm = (tmp & 0x00000004) >> 2; - mode->cc = (tmp & 0x00000002) >> 1; - mode->cs = (tmp & 0x00000001); - - return DMASUCCESS; -} - -/************************************************************** - * function: DMA_Set_Mode - * - * description: Set a new mode to a given DMA channel - * - * note: It is not a good idea of changing the DMA mode during - * the middle of a transaction. - **************************************************************/ -static -DMAStatus DMA_Set_Mode( LOCATION host, unsigned eumbbar, unsigned int channel, DMA_MR mode ) -{ - unsigned int tmp; - if ( channel != 0 && channel != 1 ) - { - return DMAINVALID; - } - - tmp = ( mode.reserved0 & 0xfff ) << 20; - tmp |= ( ( mode.irqs & 0x1 ) << 19); - tmp |= ( ( mode.pde & 0x1 ) << 18 ); - tmp |= ( ( mode.dahts & 0x3 ) << 16 ); - tmp |= ( ( mode.sahts & 0x3 ) << 14 ); - tmp |= ( ( mode.dahe & 0x1 ) << 13 ); - tmp |= ( ( mode.sahe & 0x1 ) << 12 ); - tmp |= ( ( mode.prc & 0x3 ) << 10 ); - tmp |= ( ( mode.reserved1 & 0x1 ) << 9 ); - tmp |= ( ( mode.eie & 0x1 ) << 8 ); - tmp |= ( ( mode.eotie & 0x1 ) << 7 ); - tmp |= ( ( mode.reserved2 & 0x7 ) << 4 ); - tmp |= ( ( mode.dl & 0x1 ) << 3 ); - tmp |= ( ( mode.ctm & 0x1 ) << 2 ); - tmp |= ( ( mode.cc & 0x1 ) << 1 ) ; - tmp |= ( mode.cs & 0x1 ); - - store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], tmp ); - return DMASUCCESS; -} - -/************************************************************ - * function: DMA_Start - * - * description: start a given DMA channel transaction - * return DMASUCCESS if success otherwise return - * DMAStatus value - * - * note: this function will clear DMA_MR(CC) first, then - * set DMA_MR(CC). - ***********************************************************/ -static -DMAStatus DMA_Start( LOCATION host, unsigned int eumbbar, unsigned int channel ) -{ - DMA_SR stat; - unsigned int mode; - - if ( channel != 0 && channel != 1 ) - { - return DMAINVALID; - } - - if ( DMA_Get_Stat( host, eumbbar, channel, &stat ) != DMASUCCESS ) - { - return DMAINVALID; - } - - if ( stat.cb == 1 ) - { - /* DMA is not free */ - return DMACHNBUSY; - } - - mode = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG] ); - /* clear DMA_MR(CS) */ - mode &= 0xfffffffe; - store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode ); - - /* set DMA_MR(CS) */ - mode |= CS; - store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode ); - return DMASUCCESS; -} - -/*********************************************************** - * function: DMA_Halt - * - * description: halt the current dma transaction on the specified - * channel. - * return DMASUCCESS if success otherwise return DMAINVALID - * - * note: if the specified DMA channel is idle, nothing happens - *************************************************************/ -static -DMAStatus DMA_Halt( LOCATION host, unsigned int eumbbar, unsigned int channel ) -{ - unsigned int mode; - if ( channel != 0 && channel != 1 ) - { - return DMAINVALID; - } - - mode = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG]); - - /* clear DMA_MR(CS) */ - mode &= 0xfffffffe; - store_runtime_reg(eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode ); - return DMASUCCESS; -} - -/************************************************************* - * function: DMA_Chn_Cnt - * - * description: set the DMA_MR(CC) bit for a given channel - * that is in chaining mode. - * return DMASUCCESS if successfule, otherwise return - * DMAINVALID. - * - * note: if the given channel is not in chaining mode, nothing - * happen. - * - *************************************************************/ -static -DMAStatus DMA_Chn_Cnt( LOCATION host, unsigned int eumbbar, unsigned int channel ) -{ - DMA_MR mode; - if ( channel != 0 && channel != 1 ) - { - return DMAINVALID; - } - - if ( DMA_Get_Mode( host, eumbbar, channel, &mode ) != DMASUCCESS ) - { - return DMAINVALID; - } - - if ( mode.ctm == 0 ) - { - /* either illegal mode or not chaining mode */ - return DMAINVALID; - } - - mode.cc = 1; - return DMA_Set_Mode( host, eumbbar, channel, mode ); -} - -/************************************************************** - * function: DMA_Bld_Desp - * - * description: set current descriptor address register - * according to the desp for a given channel - * - * if the given channel is busy return DMACHNBUSY - * and no change made, otherwise return DMASUCCESS. - * - * note: - **************************************************************/ -static -DMAStatus DMA_Bld_Desp( LOCATION host, - unsigned int eumbbar, - unsigned int channel, - DMA_CDAR desp ) -{ - DMA_SR status; - unsigned int temp; - - if ( channel != 0 && channel != 1 ) - { - /* channel number out of range */ - return DMAINVALID; - } - - if ( DMA_Get_Stat( host, eumbbar, channel, &status ) != DMASUCCESS ) - { - return DMAINVALID; - } - - if ( status.cb == 1 ) - { - /* channel busy */ - return DMACHNBUSY; - } - - temp = ( desp.cda & 0x7ffffff ) << 5; - temp |= (( desp.snen & 0x1 ) << 4 ); - temp |= (( desp.eosie & 0x1 ) << 3 ); - temp |= (( desp.ctt & 0x3 ) << 1 ); - temp |= ( desp.eotd & 0x1 ); - - store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], temp ); - -#ifdef DMADBG0 - PRINT( "%s(%d): %s DMA %d (0x%08x) cdar := 0x%08x\n", __FILE__, __LINE__, - ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], temp ); -#endif - - return DMASUCCESS; -} - -/************************************************************** - * function: DMA_Poke_Desp - * - * description: poke the current descriptor address register - * for a given channel - * - * return DMASUCCESS if no error - * - * note: Due to the undeterministic parallellism of DMA operation, - * the value returned by this function shall be taken as - * the most recently used descriptor when the last time - * DMA starts a chaining mode operation. - **************************************************************/ -static -DMAStatus DMA_Poke_Desp( LOCATION host, - unsigned int eumbbar, - unsigned int channel, - DMA_CDAR *desp ) -{ - unsigned int cdar; - if ( channel != 0 && channel != 1 || desp == 0 ) - { - return DMAINVALID; - } - - cdar = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG] ); - -#ifdef DMADBG0 - PRINT( "%s(%d): %s DMA %d (0x%08x) cdar : 0x%08x\n", __FILE__, __LINE__, - ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], cdar ); -#endif - - - desp->cda = ( cdar & 0xffffffe0 ) >> 5; - desp->snen = ( cdar & 0x00000010 ) >> 4; - desp->eosie = ( cdar & 0x00000008 ) >> 3; - desp->ctt = ( cdar & 0x00000006 ) >> 1; - desp->eotd = ( cdar & 0x00000001 ); - - return DMASUCCESS; -} - -/************************************************************** - * function: DMA_Bld_Curr - * - * description: set current src, dest, byte count registers - * according to the desp for a given channel - * return DMASUCCESS if no error. - * - * note: - **************************************************************/ -static -DMAStatus DMA_Bld_Curr( LOCATION host, - unsigned int eumbbar, - unsigned int channel, - DMA_CURR desp ) -{ - DMA_SR status; - if ( channel != 0 && channel != 1 ) - { - /* channel number out of range */ - return DMAINVALID; - } - - if ( DMA_Get_Stat( host, eumbbar, channel, &status ) != DMASUCCESS ) - { - return DMAINVALID; - } - - if ( status.cb == 1 ) - { - /* channel busy */ - return DMACHNBUSY; - } - - desp.byte_cnt &= 0x03ffffff; /* upper 6-bits are 0s */ - - store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SAR_REG], desp.src_addr ); -#ifdef DMADBG0 - PRINT( "%s(%d): %s DMA %d (0x%08x) src := 0x%08x\n", __FILE__, __LINE__, - ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.src_addr ); -#endif - - store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_DAR_REG], desp.dest_addr ); -#ifdef DMADBG0 - PRINT( "%s(%d): %s DMA %d (0x%08x) dest := 0x%08x\n", __FILE__, __LINE__, - ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.dest_addr ); -#endif - - store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_BCR_REG], desp.byte_cnt ); -#ifdef DMADBG0 - PRINT( "%s(%d): %s DMA %d (0x%08x) count := 0x%08x\n", __FILE__, __LINE__, - ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.byte_cnt ); -#endif - - - return DMASUCCESS; - -} - -/************************************************************** - * function: DMA_Poke_Curr - * - * description: poke the current src, dest, byte count registers - * for a given channel. - * - * return DMASUCCESS if no error - * - * note: Due to the undeterministic parallelism, in chaining - * mode, the value returned by this function shall - * be taken as reference when the query is made rather - * than the absolute snapshot when the value is returned. - **************************************************************/ -static -DMAStatus DMA_Poke_Curr( LOCATION host, - unsigned int eumbbar, - unsigned int channel, - DMA_CURR* desp ) -{ - if ( channel != 0 && channel != 1 || desp == 0 ) - { - return DMAINVALID; - } - - desp->src_addr = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SAR_REG] ); -#ifdef DMADBG0 - PRINT( "%s(%d): %s DMA %d (0x%08x) src : 0x%08x\n", __FILE__, __LINE__, - ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->src_addr ); -#endif - - desp->dest_addr = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_DAR_REG] ); -#ifdef DMADBG0 - PRINT( "%s(%d): %s DMA %d (0x%08x) dest : 0x%08x\n", __FILE__, __LINE__, - ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->dest_addr ); -#endif - - desp->byte_cnt = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_BCR_REG] ); -#ifdef DMADBG0 - PRINT( "%s(%d): %s DMA %d (0x%08x) count : 0x%08x\n", __FILE__, __LINE__, - ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->byte_cnt ); -#endif - - - return DMASUCCESS; -} - -/***************************************************************** - * function: dma_error_func - * - * description: display the error information - * - * note: This seems like a highly convoluted way to handle messages, - * but I'll leave it as it was in device.c when I moved it into the - * DMA library source. - ****************************************************************/ -static -DMAStatus dma_error_func( unsigned int eumbbar, unsigned int chn, DMAStatus err) -{ - unsigned char *msg[] = - { - "Local Memory Error", - "PCI Error", - "Channel Busy", - "End-of-Segment Interrupt", - "End-of-Chain/Direct Interrupt", - }; - - if ( err >= DMALMERROR && err <= DMAEOCAINT ) - { - PRINT( "DMA Status: channel %d %s\n", chn, msg[err-DMASUCCESS-1] ); - } - - return err; - -} - -/************************************************************* - * function: DMA_ISR - * - * description: DMA interrupt service routine - * return DMAStatus value based on - * the status - * - *************************************************************/ -static -DMAStatus DMA_ISR( unsigned int eumbbar, - unsigned int channel, - DMAStatus (*lme_func)( unsigned int, unsigned int, DMAStatus ), - DMAStatus (*pe_func) ( unsigned int, unsigned int, DMAStatus ), - DMAStatus (*eosi_func)( unsigned int, unsigned int, DMAStatus ), - DMAStatus (*eocai_func)(unsigned int, unsigned int, DMAStatus )) -{ - - DMA_SR stat; - DMAStatus rval = DMANOEVENT; - unsigned int temp; - - if ( channel != 0 && channel != 1 ) - { - return DMAINVALID; - } - - if ( DMA_Get_Stat( LOCAL, eumbbar, channel, &stat ) != DMASUCCESS ) - { - return DMAINVALID; - } - - if ( stat.lme == 1 ) - { - /* local memory error */ - rval = DMALMERROR; - if ( lme_func != 0 ) - { - rval = (*lme_func)(eumbbar, channel, DMALMERROR ); - } - - } - else if ( stat.pe == 1 ) - { - /* PCI error */ - rval = DMAPERROR; - if ( pe_func != 0 ) - { - rval = (*pe_func)(eumbbar, channel, DMAPERROR ); - } - - } - else if ( stat.eosi == 1 ) - { - /* end-of-segment interrupt */ - rval = DMAEOSINT; - if ( eosi_func != 0 ) - { - rval = (*eosi_func)(eumbbar, channel, DMAEOSINT ); - } - } - else - { - /* End-of-chain/direct interrupt */ - rval = DMAEOCAINT; - if ( eocai_func != 0 ) - { - rval = (*eocai_func)(eumbbar, channel, DMAEOCAINT ); - } - } - - temp = ( stat.reserved0 & 0xffffff ) << 8; - temp |= ( ( stat.lme & 0x1 ) << 7 ); /* write one to clear */ - temp |= ( ( stat.reserved1 & 0x3 ) << 5 ); - temp |= ( ( stat.pe & 0x1 ) << 4 ); /* write one to clear */ - temp |= ( ( stat.reserved2 & 0x1 ) << 3 ); - temp |= ( ( stat.cb & 0x1 ) << 2 ); /* write one to clear */ - temp |= ( ( stat.eosi & 0x1 ) << 1 ); /* write one to clear */ - temp |= ( stat.eocai & 0x1 ); /* write one to clear */ - - store_runtime_reg( eumbbar, dma_reg_tb[LOCAL][channel*NUM_DMA_REG + DMA_SR_REG], temp ); - -#ifdef DMADBG0 - PRINT( "%s(%d): DMA channel %d SR := 0x%08x\n", __FILE__, __LINE__, channel, temp ); -#endif - - return rval; -} diff --git a/cpu/mpc824x/drivers/dma/dma2.S b/cpu/mpc824x/drivers/dma/dma2.S deleted file mode 100644 index ccbc226..0000000 --- a/cpu/mpc824x/drivers/dma/dma2.S +++ /dev/null @@ -1,42 +0,0 @@ -/************************************** - * - * copyright @ Motorola, 1999 - * - **************************************/ - -/********************************************************** - * function: load_runtime_reg - * - * input: r3 - value of eumbbar - * r4 - register offset in embedded utility space - * - * output: r3 - register content - **********************************************************/ - .text - .align 2 - .global load_runtime_reg - -load_runtime_reg: - - lwbrx r3,r4,r3 - sync - - bclr 20, 0 - -/**************************************************************** - * function: store_runtime_reg - * - * input: r3 - value of eumbbar - * r4 - register offset in embedded utility space - * r5 - new value to be stored - * - ****************************************************************/ - .text - .align 2 - .global store_runtime_reg -store_runtime_reg: - - stwbrx r5, r4, r3 - sync - - bclr 20,0 diff --git a/cpu/mpc824x/drivers/dma/dma_export.h b/cpu/mpc824x/drivers/dma/dma_export.h deleted file mode 100644 index 471e488..0000000 --- a/cpu/mpc824x/drivers/dma/dma_export.h +++ /dev/null @@ -1,100 +0,0 @@ -#ifndef DMA_EXPORT_H -#define DMA_EXPORT_H - -/**************************************************** - * $Id: - * - * Copyright Motorola 1999 - * - * $Log: - * - ****************************************************/ - -/* These are the defined return values for the DMA_* functions. - * Any non-zero value indicates failure. Failure modes can be added for - * more detailed error reporting. - */ -typedef enum _dma_status -{ - DMA_SUCCESS = 0, - DMA_ERROR, -} DMA_Status; - -/* These are the defined channel transfer types. */ -typedef enum _dma_transfer_types -{ - DMA_M2M = 0, /* local memory to local memory */ - DMA_M2P = 1, /* local memory to PCI */ - DMA_P2M = 2, /* PCI to local memory */ - DMA_P2P = 3, /* PCI to PCI */ -} DMA_TRANSFER_TYPE; - -typedef enum _dma_interrupt_steer -{ - DMA_INT_STEER_LOCAL = 0, /* steer DMA int to local processor */ - DMA_INT_STEER_PCI = 1, /* steer DMA int to PCI bus through INTA_ */ -} DMA_INTERRUPT_STEER; - -typedef enum _dma_channel -{ - DMA_CHN_0 = 0, /* kahlua has two dma channels: 0 and 1 */ - DMA_CHN_1 = 1, -} DMA_CHANNEL; - -typedef enum _dma_snoop_mode -{ - DMA_SNOOP_DISABLE = 0, - DMA_SNOOP_ENABLE = 1, -} DMA_SNOOP_MODE; - -/******************** App. API ******************** - * The application API is for user level application - * to use the functionality provided by DMA driver. - * This is a "generic" DMA interface, it should contain - * nothing specific to the Kahlua implementation. - * Only the generic functions are exported by the library. - * - * Note: Its App.s responsibility to swap the data - * byte. In our API, we currently transfer whatever - * we are given - Big/Little Endian. This could - * become part of the DMA config, though. - **************************************************/ - - -/* Initialize DMA unit with the following: - * optional pointer to application layer print function - * - * These parameters may be added: - * ??? - * Interrupt enables, modes, etc. are set for each transfer. - * - * This function must be called before DMA unit can be used. - */ -extern DMA_Status DMA_Initialize( - int (*app_print_function)(char *,...)); /* pointer to optional "printf" - * provided by application - */ - -/* Perform the DMA transfer, only direct mode is currently implemented. - * At this point, I think it would be better to define a different - * function for chaining mode. - * Also, I'm not sure if it is appropriate to have the "generic" API - * accept snoop and int_steer parameters. The DINK user interface allows - * them, so for now I'll leave them. - * - * int_steer controls DMA interrupt steering to PCI or local processor - * type is the type of transfer: M2M, M2P, P2M, P2P - * source is the source address of the data - * dest is the destination address of the data - * len is the length of data to transfer - * channel is the DMA channel to use for the transfer - * snoop is the snoop enable control - */ -extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer, - DMA_TRANSFER_TYPE type, - unsigned int source, - unsigned int dest, - unsigned int len, - DMA_CHANNEL channel, - DMA_SNOOP_MODE snoop); -#endif diff --git a/cpu/mpc824x/drivers/dma_export.h b/cpu/mpc824x/drivers/dma_export.h deleted file mode 100644 index 471e488..0000000 --- a/cpu/mpc824x/drivers/dma_export.h +++ /dev/null @@ -1,100 +0,0 @@ -#ifndef DMA_EXPORT_H -#define DMA_EXPORT_H - -/**************************************************** - * $Id: - * - * Copyright Motorola 1999 - * - * $Log: - * - ****************************************************/ - -/* These are the defined return values for the DMA_* functions. - * Any non-zero value indicates failure. Failure modes can be added for - * more detailed error reporting. - */ -typedef enum _dma_status -{ - DMA_SUCCESS = 0, - DMA_ERROR, -} DMA_Status; - -/* These are the defined channel transfer types. */ -typedef enum _dma_transfer_types -{ - DMA_M2M = 0, /* local memory to local memory */ - DMA_M2P = 1, /* local memory to PCI */ - DMA_P2M = 2, /* PCI to local memory */ - DMA_P2P = 3, /* PCI to PCI */ -} DMA_TRANSFER_TYPE; - -typedef enum _dma_interrupt_steer -{ - DMA_INT_STEER_LOCAL = 0, /* steer DMA int to local processor */ - DMA_INT_STEER_PCI = 1, /* steer DMA int to PCI bus through INTA_ */ -} DMA_INTERRUPT_STEER; - -typedef enum _dma_channel -{ - DMA_CHN_0 = 0, /* kahlua has two dma channels: 0 and 1 */ - DMA_CHN_1 = 1, -} DMA_CHANNEL; - -typedef enum _dma_snoop_mode -{ - DMA_SNOOP_DISABLE = 0, - DMA_SNOOP_ENABLE = 1, -} DMA_SNOOP_MODE; - -/******************** App. API ******************** - * The application API is for user level application - * to use the functionality provided by DMA driver. - * This is a "generic" DMA interface, it should contain - * nothing specific to the Kahlua implementation. - * Only the generic functions are exported by the library. - * - * Note: Its App.s responsibility to swap the data - * byte. In our API, we currently transfer whatever - * we are given - Big/Little Endian. This could - * become part of the DMA config, though. - **************************************************/ - - -/* Initialize DMA unit with the following: - * optional pointer to application layer print function - * - * These parameters may be added: - * ??? - * Interrupt enables, modes, etc. are set for each transfer. - * - * This function must be called before DMA unit can be used. - */ -extern DMA_Status DMA_Initialize( - int (*app_print_function)(char *,...)); /* pointer to optional "printf" - * provided by application - */ - -/* Perform the DMA transfer, only direct mode is currently implemented. - * At this point, I think it would be better to define a different - * function for chaining mode. - * Also, I'm not sure if it is appropriate to have the "generic" API - * accept snoop and int_steer parameters. The DINK user interface allows - * them, so for now I'll leave them. - * - * int_steer controls DMA interrupt steering to PCI or local processor - * type is the type of transfer: M2M, M2P, P2M, P2P - * source is the source address of the data - * dest is the destination address of the data - * len is the length of data to transfer - * channel is the DMA channel to use for the transfer - * snoop is the snoop enable control - */ -extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer, - DMA_TRANSFER_TYPE type, - unsigned int source, - unsigned int dest, - unsigned int len, - DMA_CHANNEL channel, - DMA_SNOOP_MODE snoop); -#endif diff --git a/cpu/mpc824x/drivers/epic.h b/cpu/mpc824x/drivers/epic.h deleted file mode 100644 index 2803f63..0000000 --- a/cpu/mpc824x/drivers/epic.h +++ /dev/null @@ -1 +0,0 @@ -#include "epic/epic.h" diff --git a/cpu/mpc824x/drivers/epic/README b/cpu/mpc824x/drivers/epic/README deleted file mode 100644 index 5798996..0000000 --- a/cpu/mpc824x/drivers/epic/README +++ /dev/null @@ -1,102 +0,0 @@ -CONTENT: - - epic.h - epic1.c - epic2.s - -WHAT ARE THESE FILES: - -These files contain MPC8240 (Kahlua) EPIC -driver routines. The driver routines are not -written for any specific operating system. -They serves the purpose of code sample, and -jump-start for using the MPC8240 EPIC unit. - -For the reason of correctness of C language -syntax, these files are compiled by Metaware -C compiler and assembler. - -ENDIAN NOTATION: - -The algorithm is designed for big-endian mode, -software is responsible for byte swapping. - -USAGE: - -1. The host system that is running on MPC8240 - shall link the files listed here. The memory - location of driver routines shall take into - account of that driver routines need to run - in supervisor mode and they process external - interrupts. - - The routine epic_exception shall be called by - exception vector at location 0x500, i.e., - 603e core external exception vector. - -2. The host system is responsible for configuring - the MPC8240 including Embedded Utilities Memory - Block. All EPIC driver functions require the - content of Embedded Utilities Memory Block - Base Address Register, EUMBBAR, as the first - parameter. - -3. Before EPIC unit of MPC8240 can be used, - initialize EPIC unit by calling epicInit - with the corresponding parameters. - - The initialization shall disable the 603e - core External Exception by calling CoreExtIntDisable( ). - Next, call epicInit( ). Last, enable the 603e core - External Exception by calling CoreExtIntEnable( ). - -4. After EPIC unit has been successfully initialized, - epicIntSourceSet( ) shall be used to register each - external interrupt source. Anytime, an external - interrupt source can be disabled or enabled by - calling corresponding function, epicIntDisable( ), - or epicIntEnable( ). - - Global Timers' resource, base count and frequency, - can be changed by calling epicTmFrequencySet( ) - and epicTmBaseSet( ). - - To stop counting a specific global timer, use - the function, epicTmInhibit while epicTmEnable - can be used to start counting a timer. - -5. To mask a set of external interrupts that are - are certain level below, epicIntPrioritySet( ) - can be used. For example, if the processor's - current task priority register is set to 0x7, - only interrupts of priority 0x8 or higher will - be passed to the processor. - - Be careful when using this function. It may - corrupt the current interrupt pending, selector, - and request registers, resulting an invalid vetor. - - After enabling an interrupt, disable it may also - cause an invalid vector. User may consider using - the spurious vector interrupt service routine to - handle this case. - -6. The EPIC driver routines contains a set - of utilities, Set and Get, for host system - to query and modify the desired EPIC source - registers. - -7. Each external interrupt source shall register - its interrupt service routine. The routine - shall contain all interrupt source specific - processes and keep as short as possible. - - Special customized end of interrupt routine - is optional. If it is needed, it shall contain - the external interrupt source specific end of - interrupt process. - - External interrupt exception vector at 0x500 - shall always call the epicEOI just before - rfi instruction. Refer to the routine, - epic_exception, for a code sample. diff --git a/cpu/mpc824x/drivers/epic/epic.h b/cpu/mpc824x/drivers/epic/epic.h deleted file mode 100644 index 58f81c5..0000000 --- a/cpu/mpc824x/drivers/epic/epic.h +++ /dev/null @@ -1,163 +0,0 @@ -/********************************************************************* - * mpc8240epic.h - EPIC module of the MPC8240 micro-controller - * - * Copyrigh 1999 Motorola Inc. - * - * Modification History: - * ===================== - * 01a,04Feb99,My Created. - * 15Nov200, robt -modified to use in U-Boot - * -*/ - -#ifndef __INCEPICh -#define __INCEPICh - -#define ULONG unsigned long -#define MAXVEC 20 -#define MAXIRQ 5 /* IRQs */ -#define EPIC_DIRECT_IRQ 0 /* Direct interrupt type */ - -/* EPIC register addresses */ - -#define EPIC_EUMBBAR 0x40000 /* EUMBBAR of EPIC */ -#define EPIC_FEATURES_REG (EPIC_EUMBBAR + 0x01000)/* Feature reporting */ -#define EPIC_GLOBAL_REG (EPIC_EUMBBAR + 0x01020)/* Global config. */ -#define EPIC_INT_CONF_REG (EPIC_EUMBBAR + 0x01030)/* Interrupt config. */ -#define EPIC_VENDOR_ID_REG (EPIC_EUMBBAR + 0x01080)/* Vendor id */ -#define EPIC_PROC_INIT_REG (EPIC_EUMBBAR + 0x01090)/* Processor init. */ -#define EPIC_SPUR_VEC_REG (EPIC_EUMBBAR + 0x010e0)/* Spurious vector */ -#define EPIC_TM_FREQ_REG (EPIC_EUMBBAR + 0x010f0)/* Timer Frequency */ - -#define EPIC_TM0_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01100)/* Gbl TM0 Cur. Count*/ -#define EPIC_TM0_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01110)/* Gbl TM0 Base Count*/ -#define EPIC_TM0_VEC_REG (EPIC_EUMBBAR + 0x01120)/* Gbl TM0 Vector Pri*/ -#define EPIC_TM0_DES_REG (EPIC_EUMBBAR + 0x01130)/* Gbl TM0 Dest. */ - -#define EPIC_TM1_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01140)/* Gbl TM1 Cur. Count*/ -#define EPIC_TM1_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01150)/* Gbl TM1 Base Count*/ -#define EPIC_TM1_VEC_REG (EPIC_EUMBBAR + 0x01160)/* Gbl TM1 Vector Pri*/ -#define EPIC_TM1_DES_REG (EPIC_EUMBBAR + 0x01170)/* Gbl TM1 Dest. */ - -#define EPIC_TM2_CUR_COUNT_REG (EPIC_EUMBBAR + 0x01180)/* Gbl TM2 Cur. Count*/ -#define EPIC_TM2_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01190)/* Gbl TM2 Base Count*/ -#define EPIC_TM2_VEC_REG (EPIC_EUMBBAR + 0x011a0)/* Gbl TM2 Vector Pri*/ -#define EPIC_TM2_DES_REG (EPIC_EUMBBAR + 0x011b0)/* Gbl TM2 Dest */ - -#define EPIC_TM3_CUR_COUNT_REG (EPIC_EUMBBAR + 0x011c0)/* Gbl TM3 Cur. Count*/ -#define EPIC_TM3_BASE_COUNT_REG (EPIC_EUMBBAR + 0x011d0)/* Gbl TM3 Base Count*/ -#define EPIC_TM3_VEC_REG (EPIC_EUMBBAR + 0x011e0)/* Gbl TM3 Vector Pri*/ -#define EPIC_TM3_DES_REG (EPIC_EUMBBAR + 0x011f0)/* Gbl TM3 Dest. */ - -#define EPIC_EX_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Ext. Int. Sr0 Des */ -#define EPIC_EX_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Ext. Int. Sr0 Vect*/ -#define EPIC_EX_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Ext. Int. Sr1 Des */ -#define EPIC_EX_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Ext. Int. Sr1 Vect*/ -#define EPIC_EX_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Ext. Int. Sr2 Des */ -#define EPIC_EX_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Ext. Int. Sr2 Vect*/ -#define EPIC_EX_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Ext. Int. Sr3 Des */ -#define EPIC_EX_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Ext. Int. Sr3 Vect*/ -#define EPIC_EX_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Ext. Int. Sr4 Des */ -#define EPIC_EX_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Ext. Int. Sr4 Vect*/ - -#define EPIC_SR_INT0_VEC_REG (EPIC_EUMBBAR + 0x10200)/* Sr. Int. Sr0 Des */ -#define EPIC_SR_INT0_DES_REG (EPIC_EUMBBAR + 0x10210)/* Sr. Int. Sr0 Vect */ -#define EPIC_SR_INT1_VEC_REG (EPIC_EUMBBAR + 0x10220)/* Sr. Int. Sr1 Des */ -#define EPIC_SR_INT1_DES_REG (EPIC_EUMBBAR + 0x10230)/* Sr. Int. Sr1 Vect.*/ -#define EPIC_SR_INT2_VEC_REG (EPIC_EUMBBAR + 0x10240)/* Sr. Int. Sr2 Des */ -#define EPIC_SR_INT2_DES_REG (EPIC_EUMBBAR + 0x10250)/* Sr. Int. Sr2 Vect.*/ -#define EPIC_SR_INT3_VEC_REG (EPIC_EUMBBAR + 0x10260)/* Sr. Int. Sr3 Des */ -#define EPIC_SR_INT3_DES_REG (EPIC_EUMBBAR + 0x10270)/* Sr. Int. Sr3 Vect.*/ -#define EPIC_SR_INT4_VEC_REG (EPIC_EUMBBAR + 0x10280)/* Sr. Int. Sr4 Des */ -#define EPIC_SR_INT4_DES_REG (EPIC_EUMBBAR + 0x10290)/* Sr. Int. Sr4 Vect.*/ - -#define EPIC_SR_INT5_VEC_REG (EPIC_EUMBBAR + 0x102a0)/* Sr. Int. Sr5 Des */ -#define EPIC_SR_INT5_DES_REG (EPIC_EUMBBAR + 0x102b0)/* Sr. Int. Sr5 Vect.*/ -#define EPIC_SR_INT6_VEC_REG (EPIC_EUMBBAR + 0x102c0)/* Sr. Int. Sr6 Des */ -#define EPIC_SR_INT6_DES_REG (EPIC_EUMBBAR + 0x102d0)/* Sr. Int. Sr6 Vect.*/ -#define EPIC_SR_INT7_VEC_REG (EPIC_EUMBBAR + 0x102e0)/* Sr. Int. Sr7 Des */ -#define EPIC_SR_INT7_DES_REG (EPIC_EUMBBAR + 0x102f0)/* Sr. Int. Sr7 Vect.*/ -#define EPIC_SR_INT8_VEC_REG (EPIC_EUMBBAR + 0x10300)/* Sr. Int. Sr8 Des */ -#define EPIC_SR_INT8_DES_REG (EPIC_EUMBBAR + 0x10310)/* Sr. Int. Sr8 Vect.*/ -#define EPIC_SR_INT9_VEC_REG (EPIC_EUMBBAR + 0x10320)/* Sr. Int. Sr9 Des */ -#define EPIC_SR_INT9_DES_REG (EPIC_EUMBBAR + 0x10330)/* Sr. Int. Sr9 Vect.*/ - -#define EPIC_SR_INT10_VEC_REG (EPIC_EUMBBAR + 0x10340)/* Sr. Int. Sr10 Des */ -#define EPIC_SR_INT10_DES_REG (EPIC_EUMBBAR + 0x10350)/* Sr. Int. Sr10 Vect*/ -#define EPIC_SR_INT11_VEC_REG (EPIC_EUMBBAR + 0x10360)/* Sr. Int. Sr11 Des */ -#define EPIC_SR_INT11_DES_REG (EPIC_EUMBBAR + 0x10370)/* Sr. Int. Sr11 Vect*/ -#define EPIC_SR_INT12_VEC_REG (EPIC_EUMBBAR + 0x10380)/* Sr. Int. Sr12 Des */ -#define EPIC_SR_INT12_DES_REG (EPIC_EUMBBAR + 0x10390)/* Sr. Int. Sr12 Vect*/ -#define EPIC_SR_INT13_VEC_REG (EPIC_EUMBBAR + 0x103a0)/* Sr. Int. Sr13 Des */ -#define EPIC_SR_INT13_DES_REG (EPIC_EUMBBAR + 0x103b0)/* Sr. Int. Sr13 Vect*/ -#define EPIC_SR_INT14_VEC_REG (EPIC_EUMBBAR + 0x103c0)/* Sr. Int. Sr14 Des */ -#define EPIC_SR_INT14_DES_REG (EPIC_EUMBBAR + 0x103d0)/* Sr. Int. Sr14 Vect*/ -#define EPIC_SR_INT15_VEC_REG (EPIC_EUMBBAR + 0x103e0)/* Sr. Int. Sr15 Des */ -#define EPIC_SR_INT15_DES_REG (EPIC_EUMBBAR + 0x103f0)/* Sr. Int. Sr15 Vect*/ - -#define EPIC_I2C_INT_VEC_REG (EPIC_EUMBBAR + 0x11020)/* I2C Int. Vect Pri.*/ -#define EPIC_I2C_INT_DES_REG (EPIC_EUMBBAR + 0x11030)/* I2C Int. Dest */ -#define EPIC_DMA0_INT_VEC_REG (EPIC_EUMBBAR + 0x11040)/* DMA0 Int. Vect Pri*/ -#define EPIC_DMA0_INT_DES_REG (EPIC_EUMBBAR + 0x11050)/* DMA0 Int. Dest */ -#define EPIC_DMA1_INT_VEC_REG (EPIC_EUMBBAR + 0x11060)/* DMA1 Int. Vect Pri*/ -#define EPIC_DMA1_INT_DES_REG (EPIC_EUMBBAR + 0x11070)/* DMA1 Int. Dest */ -#define EPIC_MSG_INT_VEC_REG (EPIC_EUMBBAR + 0x110c0)/* Msg Int. Vect Pri*/ -#define EPIC_MSG_INT_DES_REG (EPIC_EUMBBAR + 0x110d0)/* Msg Int. Dest */ - -#define EPIC_PROC_CTASK_PRI_REG (EPIC_EUMBBAR + 0x20080)/* Proc. current task*/ -#define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */ -#define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */ - -#define EPIC_VEC_PRI_MASK 0x80000000 /* Mask Interrupt bit in IVPR */ -#define EPIC_VEC_PRI_DFLT_PRI 8 /* Interrupt Priority in IVPR */ - -/* Error code */ - -#define OK 0 -#define ERROR -1 - -/* function prototypes */ - -void epicVendorId( unsigned int *step, - unsigned int *devId, - unsigned int *venId - ); -void epicFeatures( unsigned int *noIRQs, - unsigned int *noCPUs, - unsigned int *VerId ); -extern void epicInit( unsigned int IRQType, unsigned int clkRatio); -ULONG sysEUMBBARRead ( ULONG regNum ); -void sysEUMBBARWrite ( ULONG regNum, ULONG regVal); -extern void epicTmFrequencySet( unsigned int frq ); -extern unsigned int epicTmFrequencyGet(void); -extern unsigned int epicTmBaseSet( ULONG srcAddr, - unsigned int cnt, - unsigned int inhibit ); -extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val ); -extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ); -extern unsigned int epicTmInhibit( unsigned int timer ); -extern unsigned int epicTmEnable( ULONG srcAdr ); -extern void CoreExtIntEnable(void); /* Enable 603e external interrupts */ -extern void CoreExtIntDisable(void); /* Disable 603e external interrupts */ -extern unsigned char epicIntTaskGet(void); -extern void epicIntTaskSet( unsigned char val ); -extern unsigned int epicIntAck(void); -extern void epicSprSet( unsigned int eumbbar, unsigned char ); -extern void epicConfigGet( unsigned int *clkRatio, - unsigned int *serEnable ); -extern void SrcVecTableInit(void); -extern unsigned int epicModeGet(void); -extern void epicIntEnable(int Vect); -extern void epicIntDisable(int Vect); -extern int epicIntSourceConfig(int Vect, int Polarity, int Sense, int Prio); -extern unsigned int epicIntAck(void); -extern void epicEOI(void); -extern int epicCurTaskPrioSet(int Vect); - -struct SrcVecTable - { - ULONG srcAddr; - char srcName[40]; - }; - -#endif /* EPIC_H */ diff --git a/cpu/mpc824x/drivers/epic/epic1.c b/cpu/mpc824x/drivers/epic/epic1.c deleted file mode 100644 index f89deed..0000000 --- a/cpu/mpc824x/drivers/epic/epic1.c +++ /dev/null @@ -1,517 +0,0 @@ -/************************************************** - * - * copyright @ motorola, 1999 - * - *************************************************/ -#include -#include -#include "epic.h" - - -#define PRINT(format, args...) printf(format , ## args) - -typedef void (*VOIDFUNCPTR) (void); /* ptr to function returning void */ -struct SrcVecTable SrcVecTable[MAXVEC] = /* Addr/Vector cross-reference tbl */ - { - { EPIC_EX_INT0_VEC_REG, "External Direct/Serial Source 0"}, - { EPIC_EX_INT1_VEC_REG, "External Direct/Serial Source 1"}, - { EPIC_EX_INT2_VEC_REG, "External Direct/Serial Source 2"}, - { EPIC_EX_INT3_VEC_REG, "External Direct/Serial Source 3"}, - { EPIC_EX_INT4_VEC_REG, "External Direct/Serial Source 4"}, - - { EPIC_SR_INT5_VEC_REG, "External Serial Source 5"}, - { EPIC_SR_INT6_VEC_REG, "External Serial Source 6"}, - { EPIC_SR_INT7_VEC_REG, "External Serial Source 7"}, - { EPIC_SR_INT8_VEC_REG, "External Serial Source 8"}, - { EPIC_SR_INT9_VEC_REG, "External Serial Source 9"}, - { EPIC_SR_INT10_VEC_REG, "External Serial Source 10"}, - { EPIC_SR_INT11_VEC_REG, "External Serial Source 11"}, - { EPIC_SR_INT12_VEC_REG, "External Serial Source 12"}, - { EPIC_SR_INT13_VEC_REG, "External Serial Source 13"}, - { EPIC_SR_INT14_VEC_REG, "External Serial Source 14"}, - { EPIC_SR_INT15_VEC_REG, "External Serial Source 15"}, - - { EPIC_I2C_INT_VEC_REG, "Internal I2C Source"}, - { EPIC_DMA0_INT_VEC_REG, "Internal DMA0 Source"}, - { EPIC_DMA1_INT_VEC_REG, "Internal DMA1 Source"}, - { EPIC_MSG_INT_VEC_REG, "Internal Message Source"}, - }; - -VOIDFUNCPTR intVecTbl[MAXVEC]; /* Interrupt vector table */ - - -/**************************************************************************** -* epicInit - Initialize the EPIC registers -* -* This routine resets the Global Configuration Register, thus it: -* - Disables all interrupts -* - Sets epic registers to reset values -* - Sets the value of the Processor Current Task Priority to the -* highest priority (0xF). -* epicInit then sets the EPIC operation mode to Mixed Mode (vs. Pass -* Through or 8259 compatible mode). -* -* If IRQType (input) is Direct IRQs: -* - IRQType is written to the SIE bit of the EPIC Interrupt -* Configuration register (ICR). -* - clkRatio is ignored. -* If IRQType is Serial IRQs: -* - both IRQType and clkRatio will be written to the ICR register -*/ - -void epicInit - ( - unsigned int IRQType, /* Direct or Serial */ - unsigned int clkRatio /* Clk Ratio for Serial IRQs */ - ) - { - ULONG tmp; - - tmp = sysEUMBBARRead(EPIC_GLOBAL_REG); - tmp |= 0xa0000000; /* Set the Global Conf. register */ - sysEUMBBARWrite(EPIC_GLOBAL_REG, tmp); - /* - * Wait for EPIC to reset - CLH - */ - while( (sysEUMBBARRead(EPIC_GLOBAL_REG) & 0x80000000) == 1); - sysEUMBBARWrite(EPIC_GLOBAL_REG, 0x20000000); - tmp = sysEUMBBARRead(EPIC_INT_CONF_REG); /* Read interrupt conf. reg */ - - if (IRQType == EPIC_DIRECT_IRQ) /* direct mode */ - sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff); - else /* Serial mode */ - { - tmp = (clkRatio << 28) | 0x08000000; /* Set clock ratio */ - sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp); - } - - while (epicIntAck() != 0xff) /* Clear all pending interrupts */ - epicEOI(); -} - -/**************************************************************************** - * epicIntEnable - Enable an interrupt source - * - * This routine clears the mask bit of an external, an internal or - * a Timer register to enable the interrupt. - * - * RETURNS: None - */ -void epicIntEnable(int intVec) -{ - ULONG tmp; - ULONG srAddr; - - srAddr = SrcVecTable[intVec].srcAddr; /* Retrieve src Vec/Prio register */ - tmp = sysEUMBBARRead(srAddr); - tmp &= ~EPIC_VEC_PRI_MASK; /* Clear the mask bit */ - tmp |= (EPIC_VEC_PRI_DFLT_PRI << 16); /* Set priority to Default - CLH */ - tmp |= intVec; /* Set Vector number */ - sysEUMBBARWrite(srAddr, tmp); - - return; - } - -/**************************************************************************** - * epicIntDisable - Disable an interrupt source - * - * This routine sets the mask bit of an external, an internal or - * a Timer register to disable the interrupt. - * - * RETURNS: OK or ERROR - * - */ - -void epicIntDisable - ( - int intVec /* Interrupt vector number */ - ) - { - - ULONG tmp, srAddr; - - srAddr = SrcVecTable[intVec].srcAddr; - tmp = sysEUMBBARRead(srAddr); - tmp |= 0x80000000; /* Set the mask bit */ - sysEUMBBARWrite(srAddr, tmp); - return; - } - -/**************************************************************************** - * epicIntSourceConfig - Set properties of an interrupt source - * - * This function sets interrupt properites (Polarity, Sense, Interrupt - * Prority, and Interrupt Vector) of an Interrupt Source. The properties - * can be set when the current source is not in-request or in-service, - * which is determined by the Activity bit. This routine return ERROR - * if the the Activity bit is 1 (in-request or in-service). - * - * This function assumes that the Source Vector/Priority register (input) - * is a valid address. - * - * RETURNS: OK or ERROR - */ - -int epicIntSourceConfig - ( - int Vect, /* interrupt source vector number */ - int Polarity, /* interrupt source polarity */ - int Sense, /* interrupt source Sense */ - int Prio /* interrupt source priority */ - ) - - { - ULONG tmp, newVal; - ULONG actBit, srAddr; - - srAddr = SrcVecTable[Vect].srcAddr; - tmp = sysEUMBBARRead(srAddr); - actBit = (tmp & 40000000) >> 30; /* retrieve activity bit - bit 30 */ - if (actBit == 1) - return ERROR; - - tmp &= 0xff30ff00; /* Erase previously set P,S,Prio,Vector bits */ - newVal = (Polarity << 23) | (Sense << 22) | (Prio << 16) | Vect; - sysEUMBBARWrite(srAddr, tmp | newVal ); - return (OK); - } - -/**************************************************************************** - * epicIntAck - acknowledge an interrupt - * - * This function reads the Interrupt acknowldge register and return - * the vector number of the highest pending interrupt. - * - * RETURNS: Interrupt Vector number. - */ - -unsigned int epicIntAck(void) -{ - return(sysEUMBBARRead( EPIC_PROC_INT_ACK_REG )); -} - -/**************************************************************************** - * epicEOI - signal an end of interrupt - * - * This function writes 0x0 to the EOI register to signal end of interrupt. - * It is usually called after an interrupt routine is served. - * - * RETURNS: None - */ - -void epicEOI(void) - { - sysEUMBBARWrite(EPIC_PROC_EOI_REG, 0x0); - } - -/**************************************************************************** - * epicCurTaskPrioSet - sets the priority of the Processor Current Task - * - * This function should be called after epicInit() to lower the priority - * of the processor current task. - * - * RETURNS: OK or ERROR - */ - -int epicCurTaskPrioSet - ( - int prioNum /* New priority value */ - ) - { - - if ( (prioNum < 0) || (prioNum > 0xF)) - return ERROR; - sysEUMBBARWrite(EPIC_PROC_CTASK_PRI_REG, prioNum); - return OK; - } - - -/************************************************************************ - * function: epicIntTaskGet - * - * description: Get value of processor current interrupt task priority register - * - * note: - ***********************************************************************/ -unsigned char epicIntTaskGet() -{ - /* get the interrupt task priority register */ - ULONG reg; - unsigned char rec; - - reg = sysEUMBBARRead( EPIC_PROC_CTASK_PRI_REG ); - rec = ( reg & 0x0F ); - return rec; -} - - -/************************************************************** - * function: epicISR - * - * description: EPIC service routine called by the core exception - * at 0x500 - * - * note: - **************************************************************/ -unsigned int epicISR(void) -{ - return 0; -} - - -/************************************************************ - * function: epicModeGet - * - * description: query EPIC mode, return 0 if pass through mode - * return 1 if mixed mode - * - * note: - *************************************************************/ -unsigned int epicModeGet(void) -{ - ULONG val; - - val = sysEUMBBARRead( EPIC_GLOBAL_REG ); - return (( val & 0x20000000 ) >> 29); -} - - -/********************************************* - * function: epicConfigGet - * - * description: Get the EPIC interrupt Configuration - * return 0 if not error, otherwise return 1 - * - * note: - ********************************************/ -void epicConfigGet( unsigned int *clkRatio, unsigned int *serEnable) -{ - ULONG val; - - val = sysEUMBBARRead( EPIC_INT_CONF_REG ); - *clkRatio = ( val & 0x70000000 ) >> 28; - *serEnable = ( val & 0x8000000 ) >> 27; -} - - -/******************************************************************* - * sysEUMBBARRead - Read a 32-bit EUMBBAR register - * - * This routine reads the content of a register in the Embedded - * Utilities Memory Block, and swaps to big endian before returning - * the value. - * - * RETURNS: The content of the specified EUMBBAR register. - */ - -ULONG sysEUMBBARRead - ( - ULONG regNum - ) - { - ULONG temp; - - temp = *(ULONG *) (CFG_EUMB_ADDR + regNum); - return ( LONGSWAP(temp)); - } - -/******************************************************************* - * sysEUMBBARWrite - Write a 32-bit EUMBBAR register - * - * This routine swaps the value to little endian then writes it to - * a register in the Embedded Utilities Memory Block address space. - * - * RETURNS: N/A - */ - -void sysEUMBBARWrite - ( - ULONG regNum, /* EUMBBAR register address */ - ULONG regVal /* Value to be written */ - ) - { - - *(ULONG *) (CFG_EUMB_ADDR + regNum) = LONGSWAP(regVal); - return ; - } - - -/******************************************************** - * function: epicVendorId - * - * description: return the EPIC Vendor Identification - * register: - * - * siliccon version, device id, and vendor id - * - * note: - ********************************************************/ -void epicVendorId - ( - unsigned int *step, - unsigned int *devId, - unsigned int *venId - ) - { - ULONG val; - val = sysEUMBBARRead( EPIC_VENDOR_ID_REG ); - *step = ( val & 0x00FF0000 ) >> 16; - *devId = ( val & 0x0000FF00 ) >> 8; - *venId = ( val & 0x000000FF ); - } - -/************************************************** - * function: epicFeatures - * - * description: return the number of IRQ supported, - * number of CPU, and the version of the - * OpenEPIC - * - * note: - *************************************************/ -void epicFeatures - ( - unsigned int *noIRQs, - unsigned int *noCPUs, - unsigned int *verId - ) - { - ULONG val; - - val = sysEUMBBARRead( EPIC_FEATURES_REG ); - *noIRQs = ( val & 0x07FF0000 ) >> 16; - *noCPUs = ( val & 0x00001F00 ) >> 8; - *verId = ( val & 0x000000FF ); -} - - -/********************************************************* - * function: epciTmFrequncySet - * - * description: Set the timer frequency reporting register - ********************************************************/ -void epicTmFrequencySet( unsigned int frq ) -{ - sysEUMBBARWrite(EPIC_TM_FREQ_REG, frq); -} - -/******************************************************* - * function: epicTmFrequncyGet - * - * description: Get the current value of the Timer Frequency - * Reporting register - * - ******************************************************/ -unsigned int epicTmFrequencyGet(void) -{ - return( sysEUMBBARRead(EPIC_TM_FREQ_REG)) ; -} - - -/**************************************************** - * function: epicTmBaseSet - * - * description: Set the #n global timer base count register - * return 0 if no error, otherwise return 1. - * - * note: - ****************************************************/ -unsigned int epicTmBaseSet - ( - ULONG srcAddr, /* Address of the Timer Base register */ - unsigned int cnt, /* Base count */ - unsigned int inhibit /* 1 - count inhibit */ - ) -{ - - unsigned int val = 0x80000000; - /* First inhibit counting the timer */ - sysEUMBBARWrite(srcAddr, val) ; - - /* set the new value */ - val = (cnt & 0x7fffffff) | ((inhibit & 0x1) << 31); - sysEUMBBARWrite(srcAddr, val) ; - return 0; -} - -/*********************************************************************** - * function: epicTmBaseGet - * - * description: Get the current value of the global timer base count register - * return 0 if no error, otherwise return 1. - * - * note: - ***********************************************************************/ -unsigned int epicTmBaseGet( ULONG srcAddr, unsigned int *val ) -{ - *val = sysEUMBBARRead( srcAddr ); - *val = *val & 0x7fffffff; - return 0; -} - -/*********************************************************** - * function: epicTmCountGet - * - * description: Get the value of a given global timer - * current count register - * return 0 if no error, otherwise return 1 - * note: - **********************************************************/ -unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val ) -{ - *val = sysEUMBBARRead( srcAddr ); - *val = *val & 0x7fffffff; - return 0; -} - - -/*********************************************************** - * function: epicTmInhibit - * - * description: Stop counting of a given global timer - * return 0 if no error, otherwise return 1 - * - * note: - ***********************************************************/ -unsigned int epicTmInhibit( unsigned int srcAddr ) -{ - ULONG val; - - val = sysEUMBBARRead( srcAddr ); - val |= 0x80000000; - sysEUMBBARWrite( srcAddr, val ); - return 0; -} - -/****************************************************************** - * function: epicTmEnable - * - * description: Enable counting of a given global timer - * return 0 if no error, otherwise return 1 - * - * note: - *****************************************************************/ -unsigned int epicTmEnable( ULONG srcAddr ) -{ - ULONG val; - - val = sysEUMBBARRead( srcAddr ); - val &= 0x7fffffff; - sysEUMBBARWrite( srcAddr, val ); - return 0; -} - -void epicSourcePrint(int Vect) - { - ULONG srcVal; - - srcVal = sysEUMBBARRead(SrcVecTable[Vect].srcAddr); - PRINT("%s\n", SrcVecTable[Vect].srcName); - PRINT("Address = 0x%lx\n", SrcVecTable[Vect].srcAddr); - PRINT("Vector = %ld\n", (srcVal & 0x000000FF) ); - PRINT("Mask = %ld\n", srcVal >> 31); - PRINT("Activitiy = %ld\n", (srcVal & 40000000) >> 30); - PRINT("Polarity = %ld\n", (srcVal & 0x00800000) >> 23); - PRINT("Sense = %ld\n", (srcVal & 0x00400000) >> 22); - PRINT("Priority = %ld\n", (srcVal & 0x000F0000) >> 16); - } diff --git a/cpu/mpc824x/drivers/epic/epic2.S b/cpu/mpc824x/drivers/epic/epic2.S deleted file mode 100644 index 8cc2fc6..0000000 --- a/cpu/mpc824x/drivers/epic/epic2.S +++ /dev/null @@ -1,196 +0,0 @@ -/************************************** - * - * copyright @ Motorola, 1999 - * - **************************************/ - -#include -#include -#include - -/********************************************* - * function: CoreExtIntEnable - * - * description: Enable 603e core external interrupt - * - * note: mtmsr is context-synchronization - **********************************************/ - .text - .align 2 - .global CoreExtIntEnable -CoreExtIntEnable: - mfmsr r3 - - ori r3,r3,0x8000 /* enable external interrupt */ - mtmsr r3 - - bclr 20, 0 - -/******************************************* - * function: CoreExtIntDisable - * - * description: Disable 603e core external interrupt - * - * note: - *******************************************/ - .text - .align 2 - .global CoreExtIntDisable -CoreExtIntDisable: - mfmsr r4 - - xor r3,r3,r3 - or r3,r3,r4 - - andis. r4,r4,0xffff - andi. r3,r3,0x7fff /* disable external interrupt */ - - or r3,r3,r4 - mtmsr r3 - - bclr 20, 0 - -/********************************************************* - * function: epicEOI - * - * description: signal the EOI and restore machine status - * Input: r3 - value of eumbbar - * Output: r3 - value of eumbbar - * r4 - ISR vector value - * note: - ********************************************************/ - .text - .align 2 - .global epicEOI -epicEOI: - lis r5,0x0006 /* Build End Of Interrupt Register offset */ - ori r5,r5,0x00b0 - xor r7,r7,r7 /* Clear r7 */ - stwbrx r7,r5,r3 /* Save r7, writing to this register will - * intidate the end of processing the - * highest interrupt. - */ - sync - - /* ---RESTORE MACHINE STATE */ - mfmsr r13 /* Clear Recoverable Interrupt bit in MSR */ - or r7,r7,r13 - - andis. r7,r7,0xffff - andi. r13,r13,0x7ffd /* (and disable interrupts) */ - or r13,r13,r7 - mtmsr r13 - - lwz r13,0x1c(r1) /* pull ctr */ - mtctr r13 - - lwz r13,0x18(r1) /* pull xer */ - mtctr r13 - - lwz r13,0x14(r1) /* pull lr */ - mtctr r13 - - lwz r13,0x10(r1) /* Pull SRR1 from stack */ - mtspr SRR1,r13 /* Restore SRR1 */ - - lwz r13,0xc(r1) /* Pull SRR0 from stack */ - mtspr SRR0,r13 /* Restore SRR0 */ - - lwz r13,0x8(r1) /* Pull User stack pointer from stack */ - mtspr SPRG1,r13 /* Restore SPRG1 */ - - lwz r4,0x4(r1) /* vector value */ - lwz r3,0x0(r1) /* eumbbar */ - sync - - addi r1,r1,0x20 /* Deallocate stack */ - mtspr SPRG0,r1 /* Save updated Supervisor stack pointer */ - mfspr r1,SPRG1 /* Restore User stack pointer */ - - bclr 20,0 - -/*********************************************************** - * function: exception routine called by exception vector - * at 0x500, external interrupt - * - * description: Kahlua EPIC controller - * - * input: r3 - content of eumbbar - * output: r3 - ISR return value - * r4 - Interrupt vector number - * note: - ***********************************************************/ - - .text - .align 2 - .global epic_exception - -epic_exception: - - /*---SAVE MACHINE STATE TO A STACK */ - mtspr SPRG1,r1 /* Save User stack pointer to SPRG1 */ - mfspr r1,SPRG0 /* Load Supervisor stack pointer into r1 */ - - stwu r3,-0x20(r1) /* Push the value of eumbbar onto stack */ - - mfspr r3,SPRG1 /* Push User stack pointer onto stack */ - stw r3,0x8(r1) - mfspr r3,SRR0 /* Push SRR0 onto stack */ - stw r1,0xc(r1) - mfspr r3,SRR1 /* Push SRR1 onto stack */ - stw r3,0x10(r1) - mflr r3 - stw r3,0x14(r1) /* Push LR */ - mfxer r3 - stw r3,0x18(r1) /* Push Xer */ - mfctr r3 - stw r3,0x1c(r1) /* Push CTR */ - - mtspr SPRG0,r1 /* Save updated Supervisor stack pointer - * value to SPRG0 - */ - mfmsr r3 - ori r3,r3,0x0002 /* Set Recoverable Interrupt bit in MSR */ - mtmsr r3 - - /* ---READ IN THE EUMBAR REGISTER */ - lwz r6,0(r1) /* this is eumbbar */ - sync - - /* ---READ EPIC REGISTER: PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */ - lis r5,0x0006 /* Build Interrupt Acknowledge Register - * offset - */ - ori r5,r5,0x00a0 - lwbrx r7,r5,r6 /* Load interrupt vector into r7 */ - sync - - /* --MASK OFF ALL BITS EXCEPT THE VECTOR */ - xor r3,r3,r3 - xor r4,r4,r4 - or r3, r3, r6 /* eumbbar in r3 */ - andi. r4,r7,0x00ff /* Mask off bits, vector in r4 */ - - stw r4,0x04(r1) /* save the vector value */ - - lis r5,epicISR@ha - ori r5,r5,epicISR@l - mtlr r5 - blrl - - xor r30,r30,r30 - or r30,r30,r3 /* save the r3 which containts the return value from epicISR */ - - /* ---READ IN THE EUMBAR REGISTER */ - lwz r3,0(r1) - sync - - lis r5,epicEOI@ha - ori r5,r5,epicEOI@l - mtlr r5 - blrl - - xor r3,r3,r3 - or r3,r3,r30 /* restore the ISR return value */ - - bclr 20,0 diff --git a/cpu/mpc824x/drivers/epic/epicutil.S b/cpu/mpc824x/drivers/epic/epicutil.S deleted file mode 100644 index 4877050..0000000 --- a/cpu/mpc824x/drivers/epic/epicutil.S +++ /dev/null @@ -1,57 +0,0 @@ -/************************************** - * - * copyright @ Motorola, 1999 - * - * - * This file contains two commonly used - * lower level utility routines. - * - * The utility routines are also in other - * Kahlua device driver libraries. The - * need to be linked in only once. - **************************************/ - -#include -#include - -/********************************************************** - * function: load_runtime_reg - * - * input: r3 - value of eumbbar - * r4 - register offset in embedded utility space - * - * output: r3 - register content - **********************************************************/ - .text - .align 2 - .global load_runtime_reg - -load_runtime_reg: - - xor r5,r5,r5 - or r5,r5,r3 /* save eumbbar */ - - lwbrx r3,r4,r5 - sync - - bclr 20, 0 - -/**************************************************************** - * function: store_runtime_reg - * - * input: r3 - value of eumbbar - * r4 - register offset in embedded utility space - * r5 - new value to be stored - * - ****************************************************************/ - .text - .align 2 - .global store_runtime_reg -store_runtime_reg: - - xor r0,r0,r0 - - stwbrx r5, r4, r3 - sync - - bclr 20,0 diff --git a/cpu/mpc824x/drivers/errors.h b/cpu/mpc824x/drivers/errors.h deleted file mode 100644 index 887f284..0000000 --- a/cpu/mpc824x/drivers/errors.h +++ /dev/null @@ -1,212 +0,0 @@ -/* Copyright Motorola, Inc. 1993, 1994 - ALL RIGHTS RESERVED - - You are hereby granted a copyright license to use, modify, and - distribute the SOFTWARE so long as this entire notice is retained - without alteration in any modified and/or redistributed versions, - and that such modified versions are clearly identified as such. - No licenses are granted by implication, estoppel or otherwise under - any patents or trademarks of Motorola, Inc. - - The SOFTWARE is provided on an "AS IS" basis and without warranty. - To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS - ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED - WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR - PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS - THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. - - To the maximum extent permitted by applicable law, IN NO EVENT SHALL - MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER - (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF - BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS - INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR - INABILITY TO USE THE SOFTWARE. Motorola assumes no responsibility - for the maintenance and support of the SOFTWARE. - -*/ - - -#include "config.h" - -/* - 1 2 3 4 5 6 7 8 -01234567890123456789012345678901234567890123456789012345678901234567890123456789 -*/ -/* List define statements here */ - -/* These are for all the toolboxes and functions to use. These will help -to standardize the error handling in the current project */ - - /* this is the "data type" for the error - messages in the system */ -#define STATUS unsigned int - - /* this is a success status code */ -#define SUCCESS 1 - - /* likewise this is failure */ -#define FAILURE 0 - -#define NUM_ERRORS 47 - -/* This first section of "defines" are for error codes ONLY. The called - routine will return one of these error codes to the caller. If the final - returned code is "VALID", then everything is a-okay. However, if one - of the functions returns a non-valid status, that error code should be - propogated back to all the callers. At the end, the last caller will - call an error_processing function, and send in the status which was - returned. It's up to the error_processing function to determine which - error occured (as indicated by the status), and print an appropriate - message back to the user. -*/ -/*----------------------------------------------------------------------*/ -/* these are specifically for the parser routines */ - -#define UNKNOWN_COMMAND 0xfb00 /* "unrecognized command " */ -#define UNKNOWN_REGISTER 0xfb01 /* "unknown register "*/ -#define ILLEGAL_RD_STAGE 0xfb02 /* cannot specify reg. family in range*/ -#define ILLEGAL_REG_FAMILY 0xfb03 /* "cannot specify a range of special - or miscellaneous registers"*/ -#define RANGE_CROSS_FAMILY 0xfb04 /* "cannot specify a range across - register families" */ -#define UNIMPLEMENTED_STAGE 0xfb05 /* invalid rd or rmm parameter format */ -#define REG_NOT_WRITEABLE 0xfb06 /* "unknown operator in arguements"*/ -#define INVALID_FILENAME 0xfb07 /* "invalid download filename" */ -#define INVALID_BAUD_RATE 0xfb08 /* invalid baud rate from sb command */ -#define UNSUPPORTED_REGISTER 0xfb09 /* Special register is not supported */ -#define FOR_BOARD_ONLY 0xfb0a /* "Not available for Unix." */ - - -/*----------------------------------------------------------------------*/ -/* these are for the error checking toolbox */ - -#define INVALID 0xfd00 /* NOT valid */ -#define VALID 0xfd01 /* valid */ - - /* This error is found in the fcn: - is_right_size_input() to indicate - that the input was not 8 characters - long. */ -#define INVALID_SIZE 0xfd02 - - /* This error is found in the fcn: - is_valid_address_range() to indicate - that the address given falls outside - of valid memory defined by MEM_START - to MEM_END. - */ -#define OUT_OF_BOUNDS_ADDRESS 0xfd03 - - /* This error is found in the fcn: - is_valid_hex_input() to indicate that - one of more of the characters entered - are not valid hex characters. Valid - hex characters are 0-9, A-F, a-f. - */ -#define INVALID_HEX_INPUT 0xfd04 - - /* This error is found in the fcn: - is_valid_register_number() to indicate - that a given register does not exist. - */ -#define REG_NOT_READABLE 0xfd05 - - /* This error is found in the fcn: - is_word_aligned_address() to indicate - that the given address is not word- - aligned. A word-aligned address ends - in 0x0,0x4,0x8,0xc. - */ -#define NOT_WORD_ALIGNED 0xfd07 - - /* This error is found in the fcn: - is_valid_address_range() to indicate - that the starting address is greater - than the ending address. - */ -#define REVERSED_ADDRESS 0xfd08 - - /* this error tells us that the address - specified as the destination is within - the source addresses */ -#define RANGE_OVERLAP 0xfd09 - - -#define ERROR 0xfd0a /* An error occured */ -#define INVALID_PARAM 0xfd0b /* "invalid input parameter " */ - - -#define INVALID_FLAG 0xfd0c /* invalid flag */ - -/*----------------------------------------------------------------------*/ -/* these are for the getarg toolbox */ - -#define INVALID_NUMBER_ARGS 0xFE00 /* invalid number of commd arguements */ -#define UNKNOWN_PARAMETER 0xFE01 /* "unknown type of parameter "*/ - - -/*----------------------------------------------------------------------*/ -/* these are for the tokenizer toolbox */ - -#define ILLEGAL_CHARACTER 0xFF00 /* unrecognized char. in input stream*/ -#define TTL_NOT_SORTED 0xFF01 /* token translation list not sorted */ -#define TTL_NOT_DEFINED 0xFF02 /* token translation list not assigned*/ -#define INVALID_STRING 0xFF03 /* unable to extract string from input */ -#define BUFFER_EMPTY 0xFF04 /* "input buffer is empty" */ -#define INVALID_MODE 0xFF05 /* input buf is in an unrecognized mode*/ -#define TOK_INTERNAL_ERROR 0xFF06 /* "internal tokenizer error" */ -#define TOO_MANY_IBS 0xFF07 /* "too many open input buffers" */ -#define NO_OPEN_IBS 0xFF08 /* "no open input buffers" */ - - -/* these are for the read from screen toolbox */ - -#define RESERVED_WORD 0xFC00 /* used a reserved word as an arguement*/ - - -/* these are for the breakpoint routines */ - -#define FULL_BPDS 0xFA00 /* breakpoint data structure is full */ - - -/* THESE are for the downloader */ - -#define NOT_IN_S_RECORD_FORMAT 0xf900 /* "not in S-Record Format" */ -#define UNREC_RECORD_TYPE 0xf901 /* "unrecognized record type" */ -#define CONVERSION_ERROR 0xf902 /* "ascii to int conversion error" */ -#define INVALID_MEMORY 0xf903 /* "bad s-record memory address " */ - - -/* these are for the compression and decompression stuff */ - -#define COMP_UNK_CHARACTER 0xf800 /* "unknown compressed character " */ - -#define COMP_UNKNOWN_STATE 0xf801 /* "unknown binary state" */ - -#define NOT_IN_COMPRESSED_FORMAT 0xf802 /* not in compressed S-Record format */ - - -/* these are for the DUART handling things */ - - /* "unrecognized serial port configuration" */ -#define UNKNOWN_PORT_STATE 0xf700 - - -/* these are for the register toolbox */ - - /* "cannot find register in special - purpose register file " */ -#define SPR_NOT_FOUND 0xf600 - - -/* these are for the duart specific stuff */ - - /* "transparent mode needs access to - two serial ports" */ -#define TM_NEEDS_BOTH_PORTS 0xf500 - - -/*----------------------------------------------------------------------*/ -/* these are specifically for the flash routines */ -#define FLASH_ERROR 0xf100 /* general flash error */ diff --git a/cpu/mpc824x/drivers/i2c/i2c.c b/cpu/mpc824x/drivers/i2c/i2c.c deleted file mode 100644 index 3add687..0000000 --- a/cpu/mpc824x/drivers/i2c/i2c.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * (C) Copyright 2003 - * Gleb Natapov - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk - * - * Hardware I2C driver for MPC107 PCI bridge. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#undef I2CDBG - -#ifdef CONFIG_HARD_I2C -#include - -#define TIMEOUT (CFG_HZ/4) - -#define I2C_Addr ((unsigned *)(CFG_EUMB_ADDR + 0x3000)) - -#define I2CADR &I2C_Addr[0] -#define I2CFDR &I2C_Addr[1] -#define I2CCCR &I2C_Addr[2] -#define I2CCSR &I2C_Addr[3] -#define I2CCDR &I2C_Addr[4] - -#define MPC107_CCR_MEN 0x80 -#define MPC107_CCR_MIEN 0x40 -#define MPC107_CCR_MSTA 0x20 -#define MPC107_CCR_MTX 0x10 -#define MPC107_CCR_TXAK 0x08 -#define MPC107_CCR_RSTA 0x04 - -#define MPC107_CSR_MCF 0x80 -#define MPC107_CSR_MAAS 0x40 -#define MPC107_CSR_MBB 0x20 -#define MPC107_CSR_MAL 0x10 -#define MPC107_CSR_SRW 0x04 -#define MPC107_CSR_MIF 0x02 -#define MPC107_CSR_RXAK 0x01 - -#define I2C_READ 1 -#define I2C_WRITE 0 - -/* taken from linux include/asm-ppc/io.h */ -inline unsigned in_le32 (volatile unsigned *addr) -{ - unsigned ret; - - __asm__ __volatile__ ("lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync":"=r" (ret): "r" (addr), "m" (*addr)); - return ret; -} - -inline void out_le32 (volatile unsigned *addr, int val) -{ - __asm__ __volatile__ ("stwbrx %1,0,%2; eieio":"=m" (*addr):"r" (val), - "r" (addr)); -} - -#define writel(val, addr) out_le32(addr, val) -#define readl(addr) in_le32(addr) - -void i2c_init (int speed, int slaveadd) -{ - /* stop I2C controller */ - writel (0x0, I2CCCR); - /* set clock */ - writel (0x1020, I2CFDR); - /* write slave address */ - writel (slaveadd, I2CADR); - /* clear status register */ - writel (0x0, I2CCSR); - /* start I2C controller */ - writel (MPC107_CCR_MEN, I2CCCR); - - return; -} - -static __inline__ int i2c_wait4bus (void) -{ - ulong timeval = get_timer (0); - - while (readl (I2CCSR) & MPC107_CSR_MBB) - if (get_timer (timeval) > TIMEOUT) - return -1; - - return 0; -} - -static __inline__ int i2c_wait (int write) -{ - u32 csr; - ulong timeval = get_timer (0); - - do { - csr = readl (I2CCSR); - - if (!(csr & MPC107_CSR_MIF)) - continue; - - writel (0x0, I2CCSR); - - if (csr & MPC107_CSR_MAL) { -#ifdef I2CDBG - printf ("i2c_wait: MAL\n"); -#endif - return -1; - } - - if (!(csr & MPC107_CSR_MCF)) { -#ifdef I2CDBG - printf ("i2c_wait: unfinished\n"); -#endif - return -1; - } - - if (write == I2C_WRITE && (csr & MPC107_CSR_RXAK)) { -#ifdef I2CDBG - printf ("i2c_wait: No RXACK\n"); -#endif - return -1; - } - - return 0; - } while (get_timer (timeval) < TIMEOUT); - -#ifdef I2CDBG - printf ("i2c_wait: timed out\n"); -#endif - return -1; -} - -static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta) -{ - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX | - (rsta ? MPC107_CCR_RSTA : 0), I2CCCR); - - writel ((dev << 1) | dir, I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - return 0; - - return 1; -} - -static __inline__ int __i2c_write (u8 * data, int length) -{ - int i; - - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | MPC107_CCR_MTX, I2CCCR); - - for (i = 0; i < length; i++) { - writel (data[i], I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - break; - } - - return i; -} - -static __inline__ int __i2c_read (u8 * data, int length) -{ - int i; - - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | - ((length == 1) ? MPC107_CCR_TXAK : 0), I2CCCR); - - /* dummy read */ - readl (I2CCDR); - - for (i = 0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) - break; - - /* Generate ack on last next to last byte */ - if (i == length - 2) - writel (MPC107_CCR_MEN | MPC107_CCR_MSTA | - MPC107_CCR_TXAK, I2CCCR); - - /* Generate stop on last byte */ - if (i == length - 1) - writel (MPC107_CCR_MEN | MPC107_CCR_TXAK, I2CCCR); - - data[i] = readl (I2CCDR); - } - - return i; -} - -int i2c_read (u8 dev, uint addr, int alen, u8 * data, int length) -{ - int i = 0; - u8 *a = (u8 *) & addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr (dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read (data, length); - -exit: - writel (MPC107_CCR_MEN, I2CCCR); - - return !(i == length); -} - -int i2c_write (u8 dev, uint addr, int alen, u8 * data, int length) -{ - int i = 0; - u8 *a = (u8 *) & addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write (data, length); - -exit: - writel (MPC107_CCR_MEN, I2CCCR); - - return !(i == length); -} - -int i2c_probe (uchar chip) -{ - int tmp; - - /* - * Try to read the first location of the chip. The underlying - * driver doesn't appear to support sending just the chip address - * and looking for an back. - */ - udelay (10000); - return i2c_read (chip, 0, 1, (uchar *) &tmp, 1); -} - -uchar i2c_reg_read (uchar i2c_addr, uchar reg) -{ - uchar buf[1]; - - i2c_read (i2c_addr, reg, 1, buf, 1); - - return (buf[0]); -} - -void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write (i2c_addr, reg, 1, &val, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc824x/drivers/i2c_export.h b/cpu/mpc824x/drivers/i2c_export.h deleted file mode 100644 index 6264d18..0000000 --- a/cpu/mpc824x/drivers/i2c_export.h +++ /dev/null @@ -1,103 +0,0 @@ -#ifndef I2C_EXPORT_H -#define I2C_EXPORT_H - -/**************************************************** - * - * Copyright Motrola 1999 - * - ****************************************************/ - -/* These are the defined return values for the I2C_do_transaction function. - * Any non-zero value indicates failure. Failure modes can be added for - * more detailed error reporting. - */ -typedef enum _i2c_status -{ - I2C_SUCCESS = 0, - I2C_ERROR, -} I2C_Status; - -/* These are the defined tasks for I2C_do_transaction. - * Modes for SLAVE_RCV and SLAVE_XMIT will be added. - */ -typedef enum _i2c_transaction_mode -{ - I2C_MASTER_RCV = 0, - I2C_MASTER_XMIT = 1, -} I2C_TRANSACTION_MODE; - -typedef enum _i2c_interrupt_mode -{ - I2C_INT_DISABLE = 0, - I2C_INT_ENABLE = 1, -} I2C_INTERRUPT_MODE; - -typedef enum _i2c_stop -{ - I2C_NO_STOP = 0, - I2C_STOP = 1, -} I2C_STOP_MODE; - -typedef enum _i2c_restart -{ - I2C_NO_RESTART = 0, - I2C_RESTART = 1, -} I2C_RESTART_MODE; - -/******************** App. API ******************** - * The application API is for user level application - * to use the functionality provided by I2C driver. - * This is a "generic" I2C interface, it should contain - * nothing specific to the Kahlua implementation. - * Only the generic functions are exported by the library. - * - * Note: Its App.s responsibility to swap the data - * byte. In our API, we just transfer whatever - * we are given - **************************************************/ - - -/* Initialize I2C unit with the following: - * driver's slave address - * interrupt enabled - * optional pointer to application layer print function - * - * These parameters may be added: - * desired clock rate - * digital filter frequency sampling rate - * - * This function must be called before I2C unit can be used. - */ -extern I2C_Status I2C_Initialize( - unsigned char addr, /* driver's I2C slave address */ - I2C_INTERRUPT_MODE en_int, /* 1 - enable I2C interrupt - * 0 - disable I2C interrupt - */ - int (*app_print_function)(char *,...)); /* pointer to optional "printf" - * provided by application - */ - -/* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV - * are implemented. Both are only in polling mode. - * - * en_int controls interrupt/polling mode - * act is the type of transaction - * addr is the I2C address of the slave device - * len is the length of data to send or receive - * buffer is the address of the data buffer - * stop = I2C_NO_STOP, don't signal STOP at end of transaction - * I2C_STOP, signal STOP at end of transaction - * retry is the timeout retry value, currently ignored - * rsta = I2C_NO_RESTART, this is not continuation of existing transaction - * I2C_RESTART, this is a continuation of existing transaction - */ -extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int, - I2C_TRANSACTION_MODE act, - unsigned char i2c_addr, - unsigned char data_addr, - int len, - char *buffer, - I2C_STOP_MODE stop, - int retry, - I2C_RESTART_MODE rsta); -#endif diff --git a/cpu/mpc824x/drivers/i2o.h b/cpu/mpc824x/drivers/i2o.h deleted file mode 100644 index c47253d..0000000 --- a/cpu/mpc824x/drivers/i2o.h +++ /dev/null @@ -1,344 +0,0 @@ -#ifndef I2O_H -#define I2O_H -/********************************************************* - * - * copyright @ Motorola, 1999 - *********************************************************/ - -#define I2O_REG_OFFSET 0x0004 - -#define PCI_CFG_CLA 0x0B -#define PCI_CFG_SCL 0x0A -#define PCI_CFG_PIC 0x09 - -#define I2O_IMR0 0x0050 -#define I2O_IMR1 0x0054 -#define I2O_OMR0 0x0058 -#define I2O_OMR1 0x005C - -#define I2O_ODBR 0x0060 -#define I2O_IDBR 0x0068 - -#define I2O_OMISR 0x0030 -#define I2O_OMIMR 0x0034 -#define I2O_IMISR 0x0100 -#define I2O_IMIMR 0x0104 - -/* accessable to PCI master but local processor */ -#define I2O_IFQPR 0x0040 -#define I2O_OFQPR 0x0044 - -/* accessable to local processor */ -#define I2O_IFHPR 0x0120 -#define I2O_IFTPR 0x0128 -#define I2O_IPHPR 0x0130 -#define I2O_IPTPR 0x0138 -#define I2O_OFHPR 0x0140 -#define I2O_OFTPR 0x0148 -#define I2O_OPHPR 0x0150 -#define I2O_OPTPR 0x0158 -#define I2O_MUCR 0x0164 -#define I2O_QBAR 0x0170 - -#define I2O_NUM_MSG 2 - -typedef enum _i2o_status -{ - I2OSUCCESS = 0, - I2OINVALID, - I2OMSGINVALID, - I2ODBINVALID, - I2OQUEINVALID, - I2OQUEEMPTY, - I2OQUEFULL, - I2ONOEVENT, -} I2OSTATUS; - -typedef enum _queue_size -{ - QSIZE_4K = 0x02, - QSIZE_8K = 0x04, - QSIZE_16K = 0x08, - QSIZE_32K = 0x10, - QSIZe_64K = 0x20, -} QUEUE_SIZE; - -typedef enum _location -{ - LOCAL = 0, /* used by local processor to access its own on board device, - local processor's eumbbar is required */ - REMOTE, /* used by PCI master to access the devices on its PCI device, - device's pcsrbar is required */ -} LOCATION; - -/* door bell */ -typedef enum _i2o_in_db -{ - IN_DB = 1, - MC, /* machine check */ -} I2O_IN_DB; - -/* I2O PCI configuration identification */ -typedef struct _i2o_iop -{ - unsigned int base_class : 8; - unsigned int sub_class : 8; - unsigned int prg_code : 8; -} I2OIOP; - -/* I2O Outbound Message Interrupt Status Register */ -typedef struct _i2o_om_stat -{ - unsigned int rsvd0 : 26; - unsigned int opqi : 1; - unsigned int rsvd1 : 1; - unsigned int odi : 1; - unsigned int rsvd2 : 1; - unsigned int om1i : 1; - unsigned int om0i : 1; -} I2OOMSTAT; - -/* I2O inbound Message Interrupt Status Register */ -typedef struct _i2o_im_stat -{ - unsigned int rsvd0 : 23; - unsigned int ofoi : 1; - unsigned int ipoi : 1; - unsigned int rsvd1 : 1; - unsigned int ipqi : 1; - unsigned int mci : 1; - unsigned int idi : 1; - unsigned int rsvd2 : 1; - unsigned int im1i : 1; - unsigned int im0i : 1; -} I2OIMSTAT; - -/** - Enable the interrupt associated with in/out bound msg - - Inbound message interrupt generated by PCI master and serviced by local processor - local processor needs to enable its inbound interrupts it wants to handle (LOCAL) - - Outbound message interrupt generated by local processor and serviced by PCI master - PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE) - **/ -extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned char n ); /* b'1' - msg 0 - * b'10'- msg 1 - * b'11'- both - */ - -/** - Disable the interrupt associated with in/out bound msg - - local processor needs to disable its inbound interrupts it is not interested (LOCAL) - - PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE) - **/ -extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned char n ); /* b'1' - msg 0 - * b'10'- msg 1 - * b'11'- both - */ - -/** - Read the msg register either from local inbound msg 0/1, - or an outbound msg 0/1 of devices. - - If it is not local, pcsrbar must be passed to the function. - Otherwise eumbbar is passed. - - If it is remote, outbound msg of the device is read. - Otherwise local inbound msg is read. - **/ -extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /*pcsrbar/eumbbar */ - unsigned int n, /* 0 or 1 */ - unsigned int *msg ); - -/** - Write to nth Msg register either on local outbound msg 0/1, - or aninbound msg 0/1 of devices - - If it is not local, pcsrbar must be passed to the function. - Otherwise eumbbar is passed. - - If it is remote, inbound msg on the device is written. - Otherwise local outbound msg is written. - **/ -extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /*pcsrbar/eumbbar */ - unsigned int n, /* 0 or 1 */ - unsigned int msg ); - -/** - Enable the In/Out DoorBell Interrupt - - InDoorBell interrupt is generated by PCI master and serviced by local processor - local processor needs to enable its inbound doorbell interrupts it wants to handle - - OutDoorbell interrupt is generated by local processor and serviced by PCI master - PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle - **/ -extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ - -/** - Disable the In/Out DoorBell Interrupt - - local processor needs to disable its inbound doorbell interrupts it is not interested - - PCI master needs to disable outbound doorbell interrupts of devices it is not interested - - **/ -extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ - -/** - Read a local indoorbell register, or an outdoorbell of devices. - Reading a doorbell register, the register will be cleared. - - If it is not local, pcsrbar must be passed to the function. - Otherwise eumbbar is passed. - - If it is remote, outdoorbell register on the device is read. - Otherwise local in doorbell is read - **/ -extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */ - unsigned int base); /* pcsrbar/eumbbar */ - -/** - Write to a local outdoorbell register, or an indoorbell register of devices. - - If it is not local, pcsrbar must be passed to the function. - Otherwise eumbbar is passed. - - If it is remote, in doorbell register on the device is written. - Otherwise local out doorbell is written - **/ -extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned int msg ); /* in / out */ - -/** - Read the outbound msg unit interrupt status of devices. Reading an interrupt status register, - the register will be cleared. - - The outbound interrupt status is AND with the outbound - interrupt mask. The result is returned. - - PCI master must pass the pcsrbar to the function. - **/ -extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * ); - -/** - Read the inbound msg unit interrupt status. Reading an interrupt status register, - the register will be cleared. - - The inbound interrupt status is AND with the inbound - interrupt mask. The result is returned. - - Local process must pass its eumbbar to the function. -**/ -extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * ); - -/** - Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR, - MUCR. - **/ -extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar, - QUEUE_SIZE, - unsigned int qba);/* queue base address that must be aligned at 1M */ -/** - Enable the circular queue - **/ -extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar ); - -/** - Disable the circular queue - **/ -extern void I2OFIFODisable( unsigned int eumbbar ); - -/** - Enable the circular queue interrupt - PCI master enables outbound FIFO interrupt of device - Device enables its inbound FIFO interrupt - **/ -extern void I2OFIFOIntEnable( LOCATION, unsigned int base ); - -/** - Disable the circular queue interrupt - PCI master disables outbound FIFO interrupt of device - Device disables its inbound FIFO interrupt - **/ -extern void I2OFIFOIntDisable( LOCATION, unsigned int base ); - -/** - Enable the circular queue overflow interrupt - **/ -extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar ); - -/** - Disable the circular queue overflow interrupt - **/ -extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar ); - -/** - Allocate a free msg frame from free FIFO. - - PCI Master allocates a free msg frame through inbound queue port of device(IFQPR) - while local processor allocates a free msg frame from outbound free queue(OFTPR) - - Unless both free queues are initialized, allocating a free MF will return 0xffffffff - **/ -extern I2OSTATUS I2OFIFOAlloc( LOCATION, - unsigned int base, - void **pMsg); -/** - Free a used msg frame back to free queue - PCI Master frees a MFA through outbound queue port of device(OFQPR) - while local processor frees a MFA into its inbound free queue(IFHPR) - - Used msg frame does not need to be recycled in the order they - read - - This function has to be called by PCI master to initialize Inbound free queue - and by device to initialize Outbound free queue before I2OFIFOAlloc can be used. - **/ -extern I2OSTATUS I2OFIFOFree( LOCATION, - unsigned int base, - void *pMsg ); - -/** - Post a msg into FIFO - PCI Master posts a msg through inbound queue port of device(IFQPR) - while local processor post a msg into its outbound post queue(OPHPR) - - The total number of msg must be less than the max size of the queue - Otherwise queue overflow interrupt will assert. - **/ -extern I2OSTATUS I2OFIFOPost( LOCATION, - unsigned int base, - void *pMsg ); - -/** - Read a msg from FIFO - PCI Master reads a msg through outbound queue port of device(OFQPR) - while local processor reads a msg from its inbound post queue(IPTPR) - **/ -extern I2OSTATUS I2OFIFOGet( LOCATION, - unsigned int base, - void **pMsg ); - -/** - Get the I2O PCI configuration identification register - **/ -extern I2OSTATUS I2OPCIConfigGet( LOCATION, - unsigned int base, - I2OIOP *); - -#endif diff --git a/cpu/mpc824x/drivers/i2o/Makefile b/cpu/mpc824x/drivers/i2o/Makefile deleted file mode 100644 index 3f5ca26..0000000 --- a/cpu/mpc824x/drivers/i2o/Makefile +++ /dev/null @@ -1,84 +0,0 @@ -########################################################################## -# -# Copyright Motorola, Inc. 1997 -# ALL RIGHTS RESERVED -# -# You are hereby granted a copyright license to use, modify, and -# distribute the SOFTWARE so long as this entire notice is retained -# without alteration in any modified and/or redistributed versions, -# and that such modified versions are clearly identified as such. -# No licenses are granted by implication, estoppel or otherwise under -# any patents or trademarks of Motorola, Inc. -# -# The SOFTWARE is provided on an "AS IS" basis and without warranty. -# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS -# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED -# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR -# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH -# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS -# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. -# -# To the maximum extent permitted by applicable law, IN NO EVENT SHALL -# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER -# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF -# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR -# INABILITY TO USE THE SOFTWARE. -# -############################################################################ -TARGET = libi2o.a - -#DEBUG = -g -DEBUG = -LST = -Hanno -S -OPTIM = -CC = /risc/tools/pkgs/metaware/bin/hcppc -CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc -CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) -PREP = $(CC) $(CFLAGS) -P - -# Assembler used to build the .s files (for the board version) - -ASOPT = -big_si -c -ASDEBUG = -l -fm -AS = /risc/tools/pkgs/metaware/bin/asppc - -# Linker to bring .o files together into an executable. - -LKOPT = -Bbase=0 -Qn -q -r -LKCMD = -LINK = /risc/tools/pkgs/metaware/bin/ldppc $(LKCMD) $(LKOPT) - -# DOS Utilities - -DEL = rm -COPY = cp -LIST = ls - -OBJECTS = i2o1.o i2o2.o - -all: $(TARGET) - -$(TARGET): $(OBJECTS) - $(LINK) $(OBJECTS) -o $@ - -objects: i2o1.o - -clean: - $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) - -.s.o: - $(DEL) -f $*.i - $(PREP) -Hasmcpp $< - $(AS) $(ASOPT) $*.i -# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst - -.c.o: - $(CCobj) $< - -.c.s: - $(CCobj) $(LST) $< - -i2o1.o: i2o.h i2o1.c - -i2o2.o: i2o.h i2o2.s diff --git a/cpu/mpc824x/drivers/i2o/Makefile_pc b/cpu/mpc824x/drivers/i2o/Makefile_pc deleted file mode 100644 index 6867f58..0000000 --- a/cpu/mpc824x/drivers/i2o/Makefile_pc +++ /dev/null @@ -1,90 +0,0 @@ -########################################################################## -# -# makefile_pc for use with PC mksnt tools dink32/drivers/i2o -# -# Copyright Motorola, Inc. 1997 -# ALL RIGHTS RESERVED -# -# You are hereby granted a copyright license to use, modify, and -# distribute the SOFTWARE so long as this entire notice is retained -# without alteration in any modified and/or redistributed versions, -# and that such modified versions are clearly identified as such. -# No licenses are granted by implication, estoppel or otherwise under -# any patents or trademarks of Motorola, Inc. -# -# The SOFTWARE is provided on an "AS IS" basis and without warranty. -# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS -# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED -# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR -# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH -# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS -# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. -# -# To the maximum extent permitted by applicable law, IN NO EVENT SHALL -# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER -# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF -# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR -# INABILITY TO USE THE SOFTWARE. -# -############################################################################ -TARGET = libi2o.a - -#DEBUG = -g -DEBUG = -LST = -Hanno -S -OPTIM = -CC = m:/old_tools/tools/hcppc/bin/hcppc -CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc -CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) -PREP = $(CC) $(CFLAGS) -P - -# Assembler used to build the .s files (for the board version) - -ASOPT = -big_si -c -ASDEBUG = -l -fm -AS = m:/old_tools/tools/hcppc/bin/asppc - -# Linker to bring .o files together into an executable. - -LKOPT = -Bbase=0 -Qn -q -r -LKCMD = -LINK = m:/old_tools/tools/hcppc/bin/ldppc $(LKCMD) $(LKOPT) - -# DOS Utilities - -DEL = rm -COPY = cp -LIST = ls - -OBJECTS = i2o1.o i2o2.o - -all: $(TARGET) - -$(TARGET): $(OBJECTS) - $(LINK) $(OBJECTS) -o $@ - -objects: i2o1.o - -clean: - $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) - -.s.o: - $(DEL) -f $*.i - $(PREP) -Hasmcpp $< - $(AS) $(ASOPT) $*.i -# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst - -.c.o: - $(CCobj) $< - -.c.s: - $(CCobj) $(LST) $< - -i2o1.o: i2o.h i2o1.c - $(CCobj) $< - -i2o2.o: i2o.h i2o2.s - $(DEL) -f $*.i - $(PREP) -Hasmcpp $< - $(AS) $(ASOPT) $*.i diff --git a/cpu/mpc824x/drivers/i2o/i2o.h b/cpu/mpc824x/drivers/i2o/i2o.h deleted file mode 100644 index 71572b2..0000000 --- a/cpu/mpc824x/drivers/i2o/i2o.h +++ /dev/null @@ -1,345 +0,0 @@ -#ifndef I2O_H -#define I2O_H -/********************************************************* - * - * copyright @ Motorola, 1999 - * - *********************************************************/ - -#define I2O_REG_OFFSET 0x0004 - -#define PCI_CFG_CLA 0x0B -#define PCI_CFG_SCL 0x0A -#define PCI_CFG_PIC 0x09 - -#define I2O_IMR0 0x0050 -#define I2O_IMR1 0x0054 -#define I2O_OMR0 0x0058 -#define I2O_OMR1 0x005C - -#define I2O_ODBR 0x0060 -#define I2O_IDBR 0x0068 - -#define I2O_OMISR 0x0030 -#define I2O_OMIMR 0x0034 -#define I2O_IMISR 0x0100 -#define I2O_IMIMR 0x0104 - -/* accessable to PCI master but local processor */ -#define I2O_IFQPR 0x0040 -#define I2O_OFQPR 0x0044 - -/* accessable to local processor */ -#define I2O_IFHPR 0x0120 -#define I2O_IFTPR 0x0128 -#define I2O_IPHPR 0x0130 -#define I2O_IPTPR 0x0138 -#define I2O_OFHPR 0x0140 -#define I2O_OFTPR 0x0148 -#define I2O_OPHPR 0x0150 -#define I2O_OPTPR 0x0158 -#define I2O_MUCR 0x0164 -#define I2O_QBAR 0x0170 - -#define I2O_NUM_MSG 2 - -typedef enum _i2o_status -{ - I2OSUCCESS = 0, - I2OINVALID, - I2OMSGINVALID, - I2ODBINVALID, - I2OQUEINVALID, - I2OQUEEMPTY, - I2OQUEFULL, - I2ONOEVENT, -} I2OSTATUS; - -typedef enum _queue_size -{ - QSIZE_4K = 0x02, - QSIZE_8K = 0x04, - QSIZE_16K = 0x08, - QSIZE_32K = 0x10, - QSIZe_64K = 0x20, -} QUEUE_SIZE; - -typedef enum _location -{ - LOCAL = 0, /* used by local processor to access its own on board device, - local processor's eumbbar is required */ - REMOTE, /* used by PCI master to access the devices on its PCI device, - device's pcsrbar is required */ -} LOCATION; - -/* door bell */ -typedef enum _i2o_in_db -{ - IN_DB = 1, - MC, /* machine check */ -} I2O_IN_DB; - -/* I2O PCI configuration identification */ -typedef struct _i2o_iop -{ - unsigned int base_class : 8; - unsigned int sub_class : 8; - unsigned int prg_code : 8; -} I2OIOP; - -/* I2O Outbound Message Interrupt Status Register */ -typedef struct _i2o_om_stat -{ - unsigned int rsvd0 : 26; - unsigned int opqi : 1; - unsigned int rsvd1 : 1; - unsigned int odi : 1; - unsigned int rsvd2 : 1; - unsigned int om1i : 1; - unsigned int om0i : 1; -} I2OOMSTAT; - -/* I2O inbound Message Interrupt Status Register */ -typedef struct _i2o_im_stat -{ - unsigned int rsvd0 : 23; - unsigned int ofoi : 1; - unsigned int ipoi : 1; - unsigned int rsvd1 : 1; - unsigned int ipqi : 1; - unsigned int mci : 1; - unsigned int idi : 1; - unsigned int rsvd2 : 1; - unsigned int im1i : 1; - unsigned int im0i : 1; -} I2OIMSTAT; - -/** - Enable the interrupt associated with in/out bound msg - - Inbound message interrupt generated by PCI master and serviced by local processor - local processor needs to enable its inbound interrupts it wants to handle (LOCAL) - - Outbound message interrupt generated by local processor and serviced by PCI master - PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE) - **/ -extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned char n ); /* b'1' - msg 0 - * b'10'- msg 1 - * b'11'- both - */ - -/** - Disable the interrupt associated with in/out bound msg - - local processor needs to disable its inbound interrupts it is not interested (LOCAL) - - PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE) - **/ -extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned char n ); /* b'1' - msg 0 - * b'10'- msg 1 - * b'11'- both - */ - -/** - Read the msg register either from local inbound msg 0/1, - or an outbound msg 0/1 of devices. - - If it is not local, pcsrbar must be passed to the function. - Otherwise eumbbar is passed. - - If it is remote, outbound msg of the device is read. - Otherwise local inbound msg is read. - **/ -extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /*pcsrbar/eumbbar */ - unsigned int n, /* 0 or 1 */ - unsigned int *msg ); - -/** - Write to nth Msg register either on local outbound msg 0/1, - or aninbound msg 0/1 of devices - - If it is not local, pcsrbar must be passed to the function. - Otherwise eumbbar is passed. - - If it is remote, inbound msg on the device is written. - Otherwise local outbound msg is written. - **/ -extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /*pcsrbar/eumbbar */ - unsigned int n, /* 0 or 1 */ - unsigned int msg ); - -/** - Enable the In/Out DoorBell Interrupt - - InDoorBell interrupt is generated by PCI master and serviced by local processor - local processor needs to enable its inbound doorbell interrupts it wants to handle - - OutDoorbell interrupt is generated by local processor and serviced by PCI master - PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle - **/ -extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ - -/** - Disable the In/Out DoorBell Interrupt - - local processor needs to disable its inbound doorbell interrupts it is not interested - - PCI master needs to disable outbound doorbell interrupts of devices it is not interested - - **/ -extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ - -/** - Read a local indoorbell register, or an outdoorbell of devices. - Reading a doorbell register, the register will be cleared. - - If it is not local, pcsrbar must be passed to the function. - Otherwise eumbbar is passed. - - If it is remote, outdoorbell register on the device is read. - Otherwise local in doorbell is read - **/ -extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */ - unsigned int base); /* pcsrbar/eumbbar */ - -/** - Write to a local outdoorbell register, or an indoorbell register of devices. - - If it is not local, pcsrbar must be passed to the function. - Otherwise eumbbar is passed. - - If it is remote, in doorbell register on the device is written. - Otherwise local out doorbell is written - **/ -extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned int msg ); /* in / out */ - -/** - Read the outbound msg unit interrupt status of devices. Reading an interrupt status register, - the register will be cleared. - - The outbound interrupt status is AND with the outbound - interrupt mask. The result is returned. - - PCI master must pass the pcsrbar to the function. - **/ -extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * ); - -/** - Read the inbound msg unit interrupt status. Reading an interrupt status register, - the register will be cleared. - - The inbound interrupt status is AND with the inbound - interrupt mask. The result is returned. - - Local process must pass its eumbbar to the function. -**/ -extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * ); - -/** - Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR, - MUCR. - **/ -extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar, - QUEUE_SIZE, - unsigned int qba);/* queue base address that must be aligned at 1M */ -/** - Enable the circular queue - **/ -extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar ); - -/** - Disable the circular queue - **/ -extern void I2OFIFODisable( unsigned int eumbbar ); - -/** - Enable the circular queue interrupt - PCI master enables outbound FIFO interrupt of device - Device enables its inbound FIFO interrupt - **/ -extern void I2OFIFOIntEnable( LOCATION, unsigned int base ); - -/** - Disable the circular queue interrupt - PCI master disables outbound FIFO interrupt of device - Device disables its inbound FIFO interrupt - **/ -extern void I2OFIFOIntDisable( LOCATION, unsigned int base ); - -/** - Enable the circular queue overflow interrupt - **/ -extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar ); - -/** - Disable the circular queue overflow interrupt - **/ -extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar ); - -/** - Allocate a free msg frame from free FIFO. - - PCI Master allocates a free msg frame through inbound queue port of device(IFQPR) - while local processor allocates a free msg frame from outbound free queue(OFTPR) - - Unless both free queues are initialized, allocating a free MF will return 0xffffffff - **/ -extern I2OSTATUS I2OFIFOAlloc( LOCATION, - unsigned int base, - void **pMsg); -/** - Free a used msg frame back to free queue - PCI Master frees a MFA through outbound queue port of device(OFQPR) - while local processor frees a MFA into its inbound free queue(IFHPR) - - Used msg frame does not need to be recycled in the order they - read - - This function has to be called by PCI master to initialize Inbound free queue - and by device to initialize Outbound free queue before I2OFIFOAlloc can be used. - **/ -extern I2OSTATUS I2OFIFOFree( LOCATION, - unsigned int base, - void *pMsg ); - -/** - Post a msg into FIFO - PCI Master posts a msg through inbound queue port of device(IFQPR) - while local processor post a msg into its outbound post queue(OPHPR) - - The total number of msg must be less than the max size of the queue - Otherwise queue overflow interrupt will assert. - **/ -extern I2OSTATUS I2OFIFOPost( LOCATION, - unsigned int base, - void *pMsg ); - -/** - Read a msg from FIFO - PCI Master reads a msg through outbound queue port of device(OFQPR) - while local processor reads a msg from its inbound post queue(IPTPR) - **/ -extern I2OSTATUS I2OFIFOGet( LOCATION, - unsigned int base, - void **pMsg ); - -/** - Get the I2O PCI configuration identification register - **/ -extern I2OSTATUS I2OPCIConfigGet( LOCATION, - unsigned int base, - I2OIOP *); - -#endif diff --git a/cpu/mpc824x/drivers/i2o/i2o1.c b/cpu/mpc824x/drivers/i2o/i2o1.c deleted file mode 100644 index f058151..0000000 --- a/cpu/mpc824x/drivers/i2o/i2o1.c +++ /dev/null @@ -1,890 +0,0 @@ -/********************************************************* - * $Id - * - * copyright @ Motorola, 1999 - *********************************************************/ -#include "i2o.h" - -extern unsigned int load_runtime_reg( unsigned int eumbbar, unsigned int reg ); -#pragma Alias( load_runtime_reg, "load_runtime_reg" ); - -extern void store_runtime_reg( unsigned int eumbbar, unsigned int reg, unsigned int val ); -#pragma Alias( store_runtime_reg, "store_runtime_reg" ); - -typedef struct _fifo_stat -{ - QUEUE_SIZE qsz; - unsigned int qba; -} FIFOSTAT; - -FIFOSTAT fifo_stat = { QSIZE_4K, 0xffffffff }; - -/********************************************************************************** - * function: I2OMsgEnable - * - * description: Enable the interrupt associated with in/out bound msg - * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID. - * - * All previously enabled interrupts are preserved. - * note: - * Inbound message interrupt generated by PCI master and serviced by local processor - * Outbound message interrupt generated by local processor and serviced by PCI master - * - * local processor needs to enable its inbound interrupts it wants to handle(LOCAL) - * PCI master needs to enable the outbound interrupts of devices it wants to handle(REMOTE) - ************************************************************************************/ -I2OSTATUS I2OMsgEnable ( LOCATION loc, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned char n ) /* b'1' - msg 0 - * b'10'- msg 1 - * b'11'- both - */ -{ - unsigned int reg, val; - if ( ( n & 0x3 ) == 0 ) - { - /* neither msg 0, nor msg 1 */ - return I2OMSGINVALID; - } - - n = (~n) & 0x3; - /* LOCATION - REMOTE : enable outbound message of device, pcsrbar as base - * LOCAL : enable local inbound message, eumbbar as base - */ - reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); - val = load_runtime_reg( base, reg ); - - val &= 0xfffffffc; /* masked out the msg interrupt bits */ - val |= n; /* LSB are the one we want */ - store_runtime_reg( base, reg, val ); - - return I2OSUCCESS; -} - -/********************************************************************************* - * function: I2OMsgDisable - * - * description: Disable the interrupt associated with in/out bound msg - * Other previously enabled interrupts are preserved. - * return I2OSUCCESS if no error otherwise return I2OMSGINVALID - * - * note: - * local processor needs to disable its inbound interrupts it is not interested(LOCAL) - * PCI master needs to disable outbound interrupts of devices it is not interested(REMOTE) - *********************************************************************************/ -I2OSTATUS I2OMsgDisable( LOCATION loc, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned char n ) /* b'1' - msg 0 - * b'10'- msg 1 - * b'11'- both - */ -{ - unsigned int reg, val; - - if ( ( n & 0x3 ) == 0 ) - { - /* neither msg 0, nor msg 1 */ - return I2OMSGINVALID; - } - - /* LOCATION - REMOTE : disable outbound message interrupt of device, pcsrbar as base - * LOCAL : disable local inbound message interrupt, eumbbar as base - */ - reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); - val = load_runtime_reg( base, reg ); - - val &= 0xfffffffc; /* masked out the msg interrupt bits */ - val |= ( n & 0x3 ); - store_runtime_reg( base, reg, val ); - - return I2OSUCCESS; - -} - -/************************************************************************** - * function: I2OMsgGet - * - * description: Local processor reads the nth Msg register from its inbound msg, - * or a PCI Master reads nth outbound msg from device - * - * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID. - * - * note: - * If it is not local, pcsrbar must be passed to the function. Otherwise eumbbar is passed. - * If it is remote, outbound msg on the device is read; otherwise local inbound msg is read - *************************************************************************/ -I2OSTATUS I2OMsgGet ( LOCATION loc, /* REMOTE/LOCAL */ - unsigned int base, /*pcsrbar/eumbbar */ - unsigned int n, /* 0 or 1 */ - unsigned int *msg ) -{ - if ( n >= I2O_NUM_MSG || msg == 0 ) - { - return I2OMSGINVALID; - } - - if ( loc == REMOTE ) - { - /* read the outbound msg of the device, pcsrbar as base */ - *msg = load_runtime_reg( base, I2O_OMR0+n*I2O_REG_OFFSET ); - } - else - { - /* read the inbound msg sent by PCI master, eumbbar as base */ - *msg = load_runtime_reg( base, I2O_IMR0+n*I2O_REG_OFFSET ); - } - - return I2OSUCCESS; -} - -/*************************************************************** - * function: I2OMsgPost - * - * description: Kahlua writes to its nth outbound msg register - * PCI master writes to nth inbound msg register of device - * - * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID. - * - * note: - * If it is not local, pcsrbar must be passed to the function. Otherwise eumbbar is passed. - * - * If it is remote, inbound msg on the device is written; otherwise local outbound msg is written - ***************************************************************/ -I2OSTATUS I2OMsgPost( LOCATION loc, /* REMOTE/LOCAL */ - unsigned int base, /*pcsrbar/eumbbar */ - unsigned int n, /* 0 or 1 */ - unsigned int msg ) -{ - if ( n >= I2O_NUM_MSG ) - { - return I2OMSGINVALID; - } - - if ( loc == REMOTE ) - { - /* write to the inbound msg register of the device, pcsrbar as base */ - store_runtime_reg( base, I2O_IMR0+n*I2O_REG_OFFSET, msg ); - } - else - { - /* write to the outbound msg register for PCI master to read, eumbbar as base */ - store_runtime_reg( base, I2O_OMR0+n*I2O_REG_OFFSET, msg ); - } - - return I2OSUCCESS; -} - -/*********************************************************************** - * function: I2ODBEnable - * - * description: Local processor enables it's inbound doorbell interrupt - * PCI master enables outbound doorbell interrupt of devices - * Other previously enabled interrupts are preserved. - * Return I2OSUCCESS if no error otherwise return I2ODBINVALID - * - * note: - * In DoorBell interrupt is generated by PCI master and serviced by local processor - * Out Doorbell interrupt is generated by local processor and serviced by PCI master - * - * Out Doorbell interrupt is generated by local processor and serviced by PCI master - * PCI master needs to enable the outbound doorbell interrupts of device it wants to handle - **********************************************************************/ -I2OSTATUS I2ODBEnable( LOCATION loc, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ -{ - - /* LOCATION - REMOTE : PCI master initializes outbound doorbell message of device - * LOCAL : Kahlua initializes its inbound doorbell message - */ - unsigned int val; - - if ( loc == LOCAL && ( in_db & 0x3 ) == 0 ) - { - return I2ODBINVALID; - } - - if ( loc == REMOTE ) - { - /* pcsrbar is base */ - val = load_runtime_reg( base, I2O_OMIMR ); - val &= 0xfffffff7; - store_runtime_reg( base, I2O_OMIMR , val ); - } - else - { - /* eumbbar is base */ - val = load_runtime_reg( base, I2O_IMIMR); - in_db = ( (~in_db) & 0x3 ) << 3; - val = ( val & 0xffffffe7) | in_db; - store_runtime_reg( base, I2O_IMIMR, val ); - } - - return I2OSUCCESS; -} - -/********************************************************************************** - * function: I2ODBDisable - * - * description: local processor disables its inbound DoorBell Interrupt - * PCI master disables outbound DoorBell interrupt of device - * Other previously enabled interrupts are preserved. - * return I2OSUCCESS if no error.Otherwise return I2ODBINVALID - * - * note: - * local processor needs to disable its inbound doorbell interrupts it is not interested - * - * PCI master needs to disable outbound doorbell interrupts of device it is not interested - ************************************************************************************/ -I2OSTATUS I2ODBDisable( LOCATION loc, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ -{ - /* LOCATION - REMOTE : handle device's out bound message initialization - * LOCAL : handle local in bound message initialization - */ - unsigned int val; - - if ( loc == LOCAL && ( in_db & 0x3 ) == 0 ) - { - return I2ODBINVALID; - } - - if ( loc == REMOTE ) - { - /* pcsrbar is the base */ - val = load_runtime_reg( base, I2O_OMIMR ); - val |= 0x8; - store_runtime_reg( base, I2O_OMIMR, val ); - } - else - { - val = load_runtime_reg( base, I2O_IMIMR); - in_db = ( in_db & 0x3 ) << 3; - val |= in_db; - store_runtime_reg( base, I2O_IMIMR, val ); - } - - return I2OSUCCESS; -} - -/********************************************************************************** - * function: I2ODBGet - * - * description: Local processor reads its in doorbell register, - * PCI master reads the outdoorbell register of device. - * After a doorbell register is read, the whole register will be cleared. - * Otherwise, HW keeps generating interrupt. - * - * note: - * If it is not local, pcsrbar must be passed to the function. - * Otherwise eumbbar is passed. - * - * If it is remote, out doorbell register on the device is read. - * Otherwise local in doorbell is read - * - * If the register is not cleared by write to it, any remaining bit of b'1's - * will cause interrupt pending. - *********************************************************************************/ -unsigned int I2ODBGet( LOCATION loc, /* REMOTE/LOCAL */ - unsigned int base) /* pcsrbar/eumbbar */ -{ - unsigned int msg, val; - - if ( loc == REMOTE ) - { - /* read outbound doorbell register of device, pcsrbar is the base */ - val = load_runtime_reg( base, I2O_ODBR ); - msg = val & 0xe0000000; - store_runtime_reg( base, I2O_ODBR, val ); /* clear the register */ - } - else - { - /* read the inbound doorbell register, eumbbar is the base */ - val = load_runtime_reg( base, I2O_IDBR ); - store_runtime_reg( base, I2O_IDBR, val ); /* clear the register */ - msg = val; - } - - return msg; -} - -/********************************************************************** - * function: I2ODBPost - * - * description: local processor writes to a outbound doorbell register, - * PCI master writes to the inbound doorbell register of device - * - * note: - * If it is not local, pcsrbar must be passed to the function. - * Otherwise eumbbar is passed. - * - * If it is remote, in doorbell register on the device is written. - * Otherwise local out doorbell is written - *********************************************************************/ -void I2ODBPost( LOCATION loc, /* REMOTE/LOCAL */ - unsigned int base, /* pcsrbar/eumbbar */ - unsigned int msg ) /* in / out */ -{ - if ( loc == REMOTE ) - { - /* write to inbound doorbell register of device, pcsrbar is the base */ - store_runtime_reg( base, I2O_IDBR, msg ); - } - else - { - /* write to local outbound doorbell register, eumbbar is the base */ - store_runtime_reg( base, I2O_ODBR, msg & 0x1fffffff ); - } - -} - -/******************************************************************** - * function: I2OOutMsgStatGet - * - * description: PCI master reads device's outbound msg unit interrupt status. - * Reading an interrupt status register, - * the register will be cleared. - * - * The value of the status register is AND with the outbound - * interrupt mask and result is returned. - * - * note: - * pcsrbar must be passed to the function. - ********************************************************************/ -I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT *val ) -{ - unsigned int stat; - unsigned int mask; - - if ( val == 0 ) - { - return I2OINVALID; - } - - /* read device's outbound status */ - stat = load_runtime_reg( pcsrbar, I2O_OMISR ); - mask = load_runtime_reg( pcsrbar, I2O_OMIMR ); - store_runtime_reg( pcsrbar, I2O_OMISR, stat & 0xffffffd7); - - stat &= mask; - val->rsvd0 = ( stat & 0xffffffc0 ) >> 6; - val->opqi = ( stat & 0x00000020 ) >> 5; - val->rsvd1 = ( stat & 0x00000010 ) >> 4; - val->odi = ( stat & 0x00000008 ) >> 3; - val->rsvd2 = ( stat & 0x00000004 ) >> 2; - val->om1i = ( stat & 0x00000002 ) >> 1; - val->om0i = ( stat & 0x00000001 ); - - return I2OSUCCESS; -} - -/******************************************************************** - * function: I2OInMsgStatGet - * - * description: Local processor reads its inbound msg unit interrupt status. - * Reading an interrupt status register, - * the register will be cleared. - * - * The inbound msg interrupt status is AND with the inbound - * msg interrupt mask and result is returned. - * - * note: - * eumbbar must be passed to the function. - ********************************************************************/ -I2OSTATUS I2OInMsgStatGet(unsigned int eumbbar, I2OIMSTAT *val) -{ - unsigned int stat; - unsigned int mask; - - if ( val == 0 ) - { - return I2OINVALID; - } - - /* read device's outbound status */ - stat = load_runtime_reg( eumbbar, I2O_OMISR ); - mask = load_runtime_reg( eumbbar, I2O_OMIMR ); - store_runtime_reg( eumbbar, I2O_OMISR, stat & 0xffffffe7 ); - - stat &= mask; - val->rsvd0 = ( stat & 0xfffffe00 ) >> 9; - val->ofoi = ( stat & 0x00000100 ) >> 8; - val->ipoi = ( stat & 0x00000080 ) >> 7; - val->rsvd1 = ( stat & 0x00000040 ) >> 6; - val->ipqi = ( stat & 0x00000020 ) >> 5; - val->mci = ( stat & 0x00000010 ) >> 4; - val->idi = ( stat & 0x00000008 ) >> 3; - val->rsvd2 = ( stat & 0x00000004 ) >> 2; - val->im1i = ( stat & 0x00000002 ) >> 1; - val->im0i = ( stat & 0x00000001 ); - - return I2OSUCCESS; - -} - -/*********************************************************** - * function: I2OFIFOInit - * - * description: Configure the I2O FIFO, including QBAR, - * IFHPR/IFTPR, IPHPR/IPTPR, OFHPR/OFTPR, - * OPHPR/OPTPR, MUCR. - * - * return I2OSUCCESS if no error, - * otherwise return I2OQUEINVALID - * - * note: It is NOT this driver's responsibility of initializing - * MFA blocks, i.e., FIFO queue itself. The MFA blocks - * must be initialized before I2O unit can be used. - ***********************************************************/ -I2OSTATUS I2OFIFOInit( unsigned int eumbbar, - QUEUE_SIZE sz, /* value of CQS of MUCR */ - unsigned int qba) /* queue base address that must be aligned at 1M */ -{ - - if ( ( qba & 0xfffff ) != 0 ) - { - /* QBA must be aligned at 1Mbyte boundary */ - return I2OQUEINVALID; - } - - store_runtime_reg( eumbbar, I2O_QBAR, qba ); - store_runtime_reg( eumbbar, I2O_MUCR, (unsigned int)sz ); - store_runtime_reg( eumbbar, I2O_IFHPR, qba ); - store_runtime_reg( eumbbar, I2O_IFTPR, qba ); - store_runtime_reg( eumbbar, I2O_IPHPR, qba + 1 * ( sz << 11 )); - store_runtime_reg( eumbbar, I2O_IPTPR, qba + 1 * ( sz << 11 )); - store_runtime_reg( eumbbar, I2O_OFHPR, qba + 2 * ( sz << 11 )); - store_runtime_reg( eumbbar, I2O_OFTPR, qba + 2 * ( sz << 11 )); - store_runtime_reg( eumbbar, I2O_OPHPR, qba + 3 * ( sz << 11 )); - store_runtime_reg( eumbbar, I2O_OPTPR, qba + 3 * ( sz << 11 )); - - fifo_stat.qsz = sz; - fifo_stat.qba = qba; - - return I2OSUCCESS; -} - -/************************************************** - * function: I2OFIFOEnable - * - * description: Enable the circular queue - * return I2OSUCCESS if no error. - * Otherwise I2OQUEINVALID is returned. - * - * note: - *************************************************/ -I2OSTATUS I2OFIFOEnable( unsigned int eumbbar ) -{ - unsigned int val; - - if ( fifo_stat.qba == 0xfffffff ) - { - return I2OQUEINVALID; - } - - val = load_runtime_reg( eumbbar, I2O_MUCR ); - store_runtime_reg( eumbbar, I2O_MUCR, val | 0x1 ); - - return I2OSUCCESS; -} - -/************************************************** - * function: I2OFIFODisable - * - * description: Disable the circular queue - * - * note: - *************************************************/ -void I2OFIFODisable( unsigned int eumbbar ) -{ - if ( fifo_stat.qba == 0xffffffff ) - { - /* not enabled */ - return; - } - - unsigned int val = load_runtime_reg( eumbbar, I2O_MUCR ); - store_runtime_reg( eumbbar, I2O_MUCR, val & 0xfffffffe ); -} - -/**************************************************** - * function: I2OFIFOAlloc - * - * description: Allocate a free MFA from free FIFO. - * return I2OSUCCESS if no error. - * return I2OQUEEMPTY if no more free MFA. - * return I2OINVALID on other errors. - * - * A free MFA must be allocated before a - * message can be posted. - * - * note: - * PCI Master allocates a free MFA from inbound queue of device - * (pcsrbar is the base,) through the inbound queue port of device - * while local processor allocates a free MFA from its outbound - * queue (eumbbar is the base.) - * - ****************************************************/ -I2OSTATUS I2OFIFOAlloc( LOCATION loc, - unsigned int base, - void **pMsg ) -{ - I2OSTATUS stat = I2OSUCCESS; - void *pHdr, *pTil; - - if ( pMsg == 0 || *pMsg == 0 || fifo_stat.qba == 0xffffffff ) - { - /* not configured */ - return I2OQUEINVALID; - } - - if ( loc == REMOTE ) - { - /* pcsrbar is the base and read the inbound free tail ptr */ - pTil = (void *)load_runtime_reg( base, I2O_IFQPR ); - if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF ) - { - stat = I2OQUEEMPTY; - } - else - { - *pMsg = pTil; - } - } - else - { - /* eumbbar is the base and read the outbound free tail ptr */ - pHdr = (void *)load_runtime_reg( base, I2O_OFHPR ); /* queue head */ - pTil = (void *)load_runtime_reg( base, I2O_OFTPR ); /* queue tail */ - - /* check underflow */ - if ( pHdr == pTil ) - { - /* hdr and til point to the same fifo item, no free MFA */ - stat = I2OQUEEMPTY; - } - else - { - /* update OFTPR */ - *pMsg = (void *)(*(unsigned char *)pTil); - pTil = (void *)((unsigned int)pTil + 4); - if ( (unsigned int)pTil == fifo_stat.qba + ( 4 * ( fifo_stat.qsz << 11 ) ) ) - { - /* reach the upper limit */ - pTil = (void *)(fifo_stat.qba + ( 3 * (fifo_stat.qsz << 11) )); - } - store_runtime_reg( base, I2O_OFTPR, (unsigned int)pTil ); - } - } - - return stat; -} - -/****************************************************** - * function: I2OFIFOFree - * - * description: Free a used MFA back to free queue after - * use. - * return I2OSUCCESS if no error. - * return I2OQUEFULL if inbound free queue - * overflow - * - * note: PCI Master frees a MFA into device's outbound queue - * (OFQPR) while local processor frees a MFA into its - * inbound queue (IFHPR). - *****************************************************/ -I2OSTATUS I2OFIFOFree( LOCATION loc, - unsigned int base, - void *pMsg ) -{ - void **pHdr, **pTil; - I2OSTATUS stat = I2OSUCCESS; - - if ( fifo_stat.qba == 0xffffffff || pMsg == 0 ) - { - return I2OQUEINVALID; - } - - if ( loc == REMOTE ) - { - /* pcsrbar is the base */ - store_runtime_reg( base, I2O_OFQPR, (unsigned int)pMsg ); - } - else - { - /* eumbbar is the base */ - pHdr = (void **)load_runtime_reg( base, I2O_IFHPR ); - pTil = (void **)load_runtime_reg( base, I2O_IFTPR ); - - /* store MFA */ - *pHdr = pMsg; - - /* update IFHPR */ - pHdr += 4; - - if ( (unsigned int)pHdr == fifo_stat.qba + ( fifo_stat.qsz << 11 ) ) - { - /* reach the upper limit */ - pHdr = (void **)fifo_stat.qba; - } - - /* check inbound free queue overflow */ - if ( pHdr != pTil ) - { - store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr); - } - else - { - stat = I2OQUEFULL; - } - - } - - return stat; - -} - -/********************************************* - * function: I2OFIFOPost - * - * description: Post a msg into FIFO post queue - * the value of msg must be the one - * returned by I2OFIFOAlloc - * - * note: PCI Master posts a msg into device's inbound queue - * (IFQPR) while local processor post a msg into device's - * outbound queue (OPHPR) - *********************************************/ -I2OSTATUS I2OFIFOPost( LOCATION loc, - unsigned int base, - void *pMsg ) -{ - void **pHdr, **pTil; - I2OSTATUS stat = I2OSUCCESS; - - if ( fifo_stat.qba == 0xffffffff || pMsg == 0 ) - { - return I2OQUEINVALID; - } - - if ( loc == REMOTE ) - { - /* pcsrbar is the base */ - store_runtime_reg( base, I2O_IFQPR, (unsigned int)pMsg ); - } - else - { - /* eumbbar is the base */ - pHdr = (void **)load_runtime_reg( base, I2O_OPHPR ); - pTil = (void **)load_runtime_reg( base, I2O_OPTPR ); - - /* store MFA */ - *pHdr = pMsg; - - /* update IFHPR */ - pHdr += 4; - - if ( (unsigned int)pHdr == fifo_stat.qba + 3 * ( fifo_stat.qsz << 11 ) ) - { - /* reach the upper limit */ - pHdr = (void **)(fifo_stat.qba + 2 * ( fifo_stat.qsz << 11 ) ); - } - - /* check post queue overflow */ - if ( pHdr != pTil ) - { - store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr); - } - else - { - stat = I2OQUEFULL; - } - } - - return stat; -} - -/************************************************ - * function: I2OFIFOGet - * - * description: Read a msg from FIFO - * This function should be called - * only when there is a corresponding - * msg interrupt. - * - * note: PCI Master reads a msg from device's outbound queue - * (OFQPR) while local processor reads a msg from device's - * inbound queue (IPTPR) - ************************************************/ -I2OSTATUS I2OFIFOGet( LOCATION loc, - unsigned int base, - void **pMsg ) -{ - I2OSTATUS stat = I2OSUCCESS; - void *pHdr, *pTil; - - if ( pMsg == 0 || *pMsg == 0 || fifo_stat.qba == 0xffffffff ) - { - /* not configured */ - return I2OQUEINVALID; - } - - if ( loc == REMOTE ) - { - /* pcsrbar is the base */ - pTil = (void *)load_runtime_reg( base, I2O_OFQPR ); - if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF ) - { - stat = I2OQUEEMPTY; - } - else - { - *pMsg = pTil; - } - } - else - { - /* eumbbar is the base and read the outbound free tail ptr */ - pHdr = (void *)load_runtime_reg( base, I2O_IPHPR ); /* queue head */ - pTil = (void *)load_runtime_reg( base, I2O_IPTPR ); /* queue tail */ - - /* check underflow */ - if ( pHdr == pTil ) - { - /* no free MFA */ - stat = I2OQUEEMPTY; - } - else - { - /* update OFTPR */ - *pMsg = (void *)(*(unsigned char *)pTil); - pTil = (void *)((unsigned int)pTil + 4); - if ( (unsigned int)pTil == fifo_stat.qba + 2 * ( fifo_stat.qsz << 11 ) ) - { - /* reach the upper limit */ - pTil = (void *)(fifo_stat.qba + 1 * (fifo_stat.qsz << 11) ); - } - - store_runtime_reg( base, I2O_IPTPR, (unsigned int)pTil ); - } - } - - return stat; -} - -/******************************************************** - * function: I2OIOP - * - * description: Get the I2O PCI configuration identification - * register. - * - * note: PCI master should pass pcsrbar while local processor - * should pass eumbbar. - *********************************************************/ -I2OSTATUS I2OPCIConfigGet( LOCATION loc, - unsigned int base, - I2OIOP * val) -{ - unsigned int tmp; - if ( val == 0 ) - { - return I2OINVALID; - } - tmp = load_runtime_reg( base, PCI_CFG_CLA ); - val->base_class = ( tmp & 0xFF) << 16; - tmp = load_runtime_reg( base, PCI_CFG_SCL ); - val->sub_class= ( (tmp & 0xFF) << 8 ); - tmp = load_runtime_reg( base, PCI_CFG_PIC ); - val->prg_code = (tmp & 0xFF); - return I2OSUCCESS; -} - -/********************************************************* - * function: I2OFIFOIntEnable - * - * description: Enable the circular post queue interrupt - * - * note: - * PCI master enables outbound FIFO interrupt of device - * pscrbar is the base - * Device enables its inbound FIFO interrupt - * eumbbar is the base - *******************************************************/ -void I2OFIFOIntEnable( LOCATION loc, unsigned int base ) -{ - unsigned int reg, val; - - /* LOCATION - REMOTE : enable outbound message of device, pcsrbar as base - * LOCAL : enable local inbound message, eumbbar as base - */ - reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); - val = load_runtime_reg( base, reg ); - - val &= 0xffffffdf; /* clear the msg interrupt bits */ - store_runtime_reg( base, reg, val ); - -} - -/**************************************************** - * function: I2OFIFOIntDisable - * - * description: Disable the circular post queue interrupt - * - * note: - * PCI master disables outbound FIFO interrupt of device - * (pscrbar is the base) - * Device disables its inbound FIFO interrupt - * (eumbbar is the base) - *****************************************************/ -void I2OFIFOIntDisable( LOCATION loc, unsigned int base ) -{ - - /* LOCATION - REMOTE : disable outbound message interrupt of device, pcsrbar as base - * LOCAL : disable local inbound message interrupt, eumbbar as base - */ - unsigned int reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); - unsigned int val = load_runtime_reg( base, reg ); - - val |= 0x00000020; /* masked out the msg interrupt bits */ - store_runtime_reg( base, reg, val ); - -} - -/********************************************************* - * function: I2OFIFOOverflowIntEnable - * - * description: Enable the circular queue overflow interrupt - * - * note: - * Device enables its inbound FIFO post overflow interrupt - * and outbound free overflow interrupt. - * eumbbar is the base - *******************************************************/ -void I2OFIFOOverflowIntEnable( unsigned int eumbbar ) -{ - unsigned int val = load_runtime_reg( eumbbar, I2O_IMIMR ); - - val &= 0xfffffe7f; /* clear the two overflow interrupt bits */ - store_runtime_reg( eumbbar, I2O_IMIMR, val ); - -} - -/**************************************************** - * function: I2OFIFOOverflowIntDisable - * - * description: Disable the circular queue overflow interrupt - * - * note: - * Device disables its inbound post FIFO overflow interrupt - * and outbound free FIFO overflow interrupt - * (eumbbar is the base) - *****************************************************/ -void I2OFIFOOverflowIntDisable( unsigned int eumbbar ) -{ - - unsigned int val = load_runtime_reg( eumbbar, I2O_IMIMR ); - - val |= 0x00000180; /* masked out the msg overflow interrupt bits */ - store_runtime_reg( eumbbar, I2O_IMIMR, val ); -} diff --git a/cpu/mpc824x/drivers/i2o/i2o2.S b/cpu/mpc824x/drivers/i2o/i2o2.S deleted file mode 100644 index 990f9ef..0000000 --- a/cpu/mpc824x/drivers/i2o/i2o2.S +++ /dev/null @@ -1,47 +0,0 @@ -/************************************** - * - * copyright @ Motorola, 1999 - * - **************************************/ - -/********************************************************** - * function: load_runtime_reg - * - * input: r3 - value of eumbbar - * r4 - register offset in embedded utility space - * - * output: r3 - register content - **********************************************************/ - .text - .align 2 - .global load_runtime_reg - -load_runtime_reg: - - xor r5,r5,r5 - or r5,r5,r3 /* save eumbbar */ - - lwbrx r3,r4,r5 - sync - - bclr 20, 0 - -/**************************************************************** - * function: store_runtime_reg - * - * input: r3 - value of eumbbar - * r4 - register offset in embedded utility space - * r5 - new value to be stored - * - ****************************************************************/ - .text - .align 2 - .global store_runtime_reg -store_runtime_reg: - - xor r0,r0,r0 - - stwbrx r5, r4, r3 - sync - - bclr 20,0 diff --git a/cpu/mpc824x/interrupts.c b/cpu/mpc824x/interrupts.c deleted file mode 100644 index acb8947..0000000 --- a/cpu/mpc824x/interrupts.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include "drivers/epic.h" - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - *decrementer_count = (get_bus_freq (0) / 4) / CFG_HZ; - - /* - * It's all broken at the moment and I currently don't need - * interrupts. If you want to fix it, have a look at the epic - * drivers in dink32 v12. They do everthing and Motorola said - * I could use the dink source in this project as long as - * copyright notices remain intact. - */ - - epicInit (EPIC_DIRECT_IRQ, 0); - /* EPIC won't generate INT unless Current Task Pri < 15 */ - epicCurTaskPrioSet(0); - - return (0); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt (struct pt_regs *regs) -{ - register unsigned long temp; - - pci_readl (CFG_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp); - sync (); /* i'm not convinced this is needed, but dink source has it */ - temp &= 0xff; /*get vector */ - - /*TODO: handle them -... */ - epicEOI (); -} - -/****************************************************************************/ - -/* - * blank int handlers. - */ - -void -irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) -{ -} - -void irq_free_handler (int vec) -{ - -} - -/*TODO: some handlers for winbond and 87308 interrupts - and what about generic pci inteerupts? - vga? - */ - -void timer_interrupt_cpu (struct pt_regs *regs, ulong timestamp) -{ - /* nothing to do here */ - return; -} diff --git a/cpu/mpc824x/pci.c b/cpu/mpc824x/pci.c deleted file mode 100644 index 7e3c4c3..0000000 --- a/cpu/mpc824x/pci.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * arch/ppc/kernel/mpc10x_common.c - * - * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge, - * Mem ctlr, EPIC, etc. - * - * Author: Mark A. Greer - * mgreer@mvista.com - * - * Copyright 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include - -#ifdef CONFIG_PCI - -#include -#include -#include -#include - -void pci_mpc824x_init (struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - CHRP_PCI_MEMORY_BUS, - CHRP_PCI_MEMORY_PHYS, - CHRP_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CHRP_PCI_MEM_BUS, - CHRP_PCI_MEM_PHYS, - CHRP_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* ISA/PCI memory space */ - pci_set_region(hose->regions + 2, - CHRP_ISA_MEM_BUS, - CHRP_ISA_MEM_PHYS, - CHRP_ISA_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(hose->regions + 3, - CHRP_PCI_IO_BUS, - CHRP_PCI_IO_PHYS, - CHRP_PCI_IO_SIZE, - PCI_REGION_IO); - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + 4, - CHRP_ISA_IO_BUS, - CHRP_ISA_IO_PHYS, - CHRP_ISA_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 5; - - pci_setup_indirect(hose, - CHRP_REG_ADDR, - CHRP_REG_DATA); - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); -} - -#endif diff --git a/cpu/mpc824x/speed.c b/cpu/mpc824x/speed.c deleted file mode 100644 index a37a087..0000000 --- a/cpu/mpc824x/speed.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ -/* NOTE: This describes the proper use of this file. - * - * CONFIG_SYS_CLK_FREQ should be defined as the input frequency on - * PCI_SYNC_IN . - * - * CONFIG_PLL_PCI_TO_MEM_MULTIPLIER is only required on MPC8240 - * boards. It should be defined as the PCI to Memory Multiplier as - * documented in the MPC8240 Hardware Specs. - * - * Other mpc824x boards don't need CONFIG_PLL_PCI_TO_MEM_MULTIPLIER - * because they can determine it from the PCR. - * - * Gary Milliorn (who should know since - * he designed the Sandpoint) told us that the PCR is not in all revs - * of the MPC8240 CPU, so it's not guaranteeable and we cannot do - * away with CONFIG_PLL_PCI_TO_MEM_MULTIPLIER altogether. - */ -/* ------------------------------------------------------------------------- */ - -/* This gives the PCI to Memory multiplier times 10 */ -/* The index is the value of PLL_CFG[0:4] */ -/* This is documented in the MPC8240/5 Hardware Specs */ - -short pll_pci_to_mem_multiplier[] = { -#if defined(CONFIG_MPC8240) - 30, 30, 10, 10, 20, 10, 0, 10, - 10, 0, 20, 0, 20, 0, 20, 0, - 30, 0, 15, 0, 20, 0, 20, 0, - 25, 0, 10, 0, 15, 15, 0, 0, -#elif defined(CONFIG_MPC8245) - 30, 30, 10, 10, 20, 10, 10, 10, - 10, 20, 20, 15, 20, 15, 20, 30, - 30, 40, 15, 40, 20, 25, 20, 40, - 25, 20, 10, 20, 15, 15, 15, 0, -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -}; - -#define CU824_PLL_STATE_REG 0xFE80002F -#define PCR 0x800000E2 - -/* ------------------------------------------------------------------------- */ - -/* compute the memory bus clock frequency */ -ulong get_bus_freq (ulong dummy) -{ - unsigned char pll_cfg; -#if defined(CONFIG_MPC8240) && !defined(CONFIG_CU824) - return (CONFIG_SYS_CLK_FREQ) * (CONFIG_PLL_PCI_TO_MEM_MULTIPLIER); -#elif defined(CONFIG_CU824) - pll_cfg = *(volatile unsigned char *) (CU824_PLL_STATE_REG); - pll_cfg &= 0x1f; -#else - CONFIG_READ_BYTE(PCR, pll_cfg); - pll_cfg = (pll_cfg >> 3) & 0x1f; -#endif - return ((CONFIG_SYS_CLK_FREQ) * pll_pci_to_mem_multiplier[pll_cfg] + 5) / 10; -} - - -/* ------------------------------------------------------------------------- */ - -/* This gives the Memory to CPU Core multiplier times 10 */ -/* The index is the value of PLLRATIO in HID1 */ -/* This is documented in the MPC8240 Hardware Specs */ -/* This is not documented for MPC8245 ? FIXME */ -short pllratio_to_factor[] = { - 0, 0, 0, 10, 20, 20, 25, 45, - 30, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 10, 0, 0, 0, 45, - 30, 0, 40, 0, 0, 0, 35, 0, -}; - -/* compute the CPU and memory bus clock frequencies */ -int get_clocks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - uint hid1 = mfspr(HID1); - hid1 = (hid1 >> (32-5)) & 0x1f; - gd->cpu_clk = (pllratio_to_factor[hid1] * get_bus_freq(0) + 5) - / 10; - gd->bus_clk = get_bus_freq(0); - return (0); -} diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S deleted file mode 100644 index 9ff052c..0000000 --- a/cpu/mpc824x/start.S +++ /dev/null @@ -1,789 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000,2001,2002 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* U-Boot - Startup Code for PowerPC based Embedded Boards - * - * - * The processor starts at 0x00000100 and the code is executed - * from flash. The code is organized to be at an other address - * in memory, but as long we don't jump around before relocating. - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - * This works because the cpu gives the FLASH (CS0) the whole - * address space at startup, and board_init lies as a echo of - * the flash somewhere up there in the memorymap. - * - * board_init will change CS0 to be positioned at the correct - * address and (s)dram will be positioned at address 0 - */ -#include -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* FP, Machine Check and Recoverable Interr. */ -#define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI ) - -/* - * Set up GOT: Global Offset Table - * - * Use r14 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) -#if defined(CONFIG_FADS) - GOT_ENTRY(environment) -#endif - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ - b boot_cold - - . = EXC_OFF_SYS_RESET + 0x10 - - .globl _start_warm -_start_warm: - li r21, BOOTFLAG_WARM /* Software reboot */ - b boot_warm - -boot_cold: -boot_warm: - - /* Initialize machine status; enable machine check interrupt */ - /*----------------------------------------------------------------------*/ - li r3, MSR_KERNEL /* Set FP, ME, RI flags */ - mtmsr r3 - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - addis r0,0,0x0000 /* lets make sure that r0 is really 0 */ - mtspr HID0, r0 /* disable I and D caches */ - - mfspr r3, ICR /* clear Interrupt Cause Register */ - - mfmsr r3 /* turn off address translation */ - addis r4,0,0xffff - ori r4,r4,0xffcf - and r3,r3,r4 - mtmsr r3 - isync - sync /* the MMU should be off... */ - - -in_flash: -#if defined(CONFIG_BMW) - bl early_init_f /* Must be ASM: no stack yet! */ -#endif - /* - * Setup BATs - cannot be done in C since we don't have a stack yet - */ - bl setup_bats - - /* Enable MMU. - */ - mfmsr r3 - ori r3, r3, (MSR_IR | MSR_DR) - mtmsr r3 -#if !defined(CONFIG_BMW) - /* Enable and invalidate data cache. - */ - mfspr r3, HID0 - mr r2, r3 - ori r3, r3, HID0_DCE | HID0_DCI - ori r2, r2, HID0_DCE - sync - mtspr HID0, r3 - mtspr HID0, r2 - sync - - /* Allocate Initial RAM in data cache. - */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l - li r2, 128 - mtctr r2 -1: - dcbz r0, r3 - addi r3, r3, 32 - bdnz 1b - - /* Lock way0 in data cache. - */ - mfspr r3, 1011 - lis r2, 0xffff - ori r2, r2, 0xff1f - and r3, r3, r2 - ori r3, r3, 0x0080 - sync - mtspr 1011, r3 -#endif /* !CONFIG_BMW */ - /* - * Thisk the stack pointer *somewhere* sensible. Doesnt - * matter much where as we'll move it when we relocate - */ - lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*----------------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - - mr r3, r21 - /* r3: BOOTFLAG */ - bl board_init_f /* run 1st part of board init code (from Flash) */ - - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = EXC_OFF_ALIGN -Alignment: - EXCEPTION_PROLOG - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - -/* Program check exception */ - . = EXC_OFF_PROGRAM -ProgramCheck: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - - /* No FPU on MPC8xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - - STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException) - - STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException) - STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException) - - STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException) - STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException) - STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException) - STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException) - STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException) - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - STD_EXCEPTION(0x1c00, ReservedC, UnknownException) - STD_EXCEPTION(0x1d00, ReservedD, UnknownException) - STD_EXCEPTION(0x1e00, ReservedE, UnknownException) - STD_EXCEPTION(0x1f00, ReservedF, UnknownException) - - STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException) - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x3000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) -#if 0 - andi. r23,r23,MSR_PR - mfspr r23,SPRG3 /* if from user, fix up tss.regs */ - beq 2f - addi r24,r1,STACK_FRAME_OVERHEAD - stw r24,PT_REGS(r23) -2: addi r2,r23,-TSS /* set r2 to current */ - tovirt(r2,r2,r23) -#endif - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ -#if 0 - addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */ - cmplw 0,r1,r2 - cmplw 1,r1,r24 - crand 1,1,4 - bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */ -#endif - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - ori r20,r20,0x30 /* enable IR, DR */ - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* Cache functions. -*/ - .globl icache_enable -icache_enable: - mfspr r5,HID0 /* turn on the I cache. */ - ori r5,r5,0x8800 /* Instruction cache only! */ - addis r6,0,0xFFFF - ori r6,r6,0xF7FF - and r6,r5,r6 /* clear the invalidate bit */ - sync - mtspr HID0,r5 - mtspr HID0,r6 - isync - sync - blr - - .globl icache_disable -icache_disable: - mfspr r5,HID0 - addis r6,0,0xFFFF - ori r6,r6,0x7FFF - and r5,r5,r6 - sync - mtspr HID0,r5 - isync - sync - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - srwi r3, r3, 15 /* >>15 & 1=> select bit 16 */ - andi. r3, r3, 1 - blr - - .globl dcache_enable -dcache_enable: - mfspr r5,HID0 /* turn on the D cache. */ - ori r5,r5,0x4400 /* Data cache only! */ - mfspr r4, PVR /* read PVR */ - srawi r3, r4, 16 /* shift off the least 16 bits */ - cmpi 0, 0, r3, 0xC /* Check for Max pvr */ - bne NotMax - ori r5,r5,0x0040 /* setting the DCFA bit, for Max rev 1 errata */ -NotMax: - addis r6,0,0xFFFF - ori r6,r6,0xFBFF - and r6,r5,r6 /* clear the invalidate bit */ - sync - mtspr HID0,r5 - mtspr HID0,r6 - isync - sync - blr - - .globl dcache_disable -dcache_disable: - mfspr r5,HID0 - addis r6,0,0xFFFF - ori r6,r6,0xBFFF - and r5,r5,r6 - sync - mtspr HID0,r5 - isync - sync - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - srwi r3, r3, 14 /* >>14 & 1=> select bit 17 */ - andi. r3, r3, 1 - blr - - .globl dc_read -dc_read: -/*TODO : who uses this, what should it do? -*/ - blr - - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - mr r3, r5 /* Destination Address */ -#ifdef CFG_RAMBOOT - lis r4, CFG_SDRAM_BASE@h /* Source Address */ - ori r4, r4, CFG_SDRAM_BASE@l -#else - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l -#endif - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r14, r14, r15 - /* the the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -4: -#if !defined(CONFIG_BMW) -/* Unlock the data cache and invalidate locked area */ - xor r0, r0, r0 - mtspr 1011, r0 - lis r4, CFG_INIT_RAM_ADDR@h - ori r4, r4, CFG_INIT_RAM_ADDR@l - li r0, 128 - mtctr r0 -41: - dcbi r0, r4 - addi r4, r4, 32 - bdnz 41b -#endif - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ - cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r14 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - add r0,r0,r11 - stw r0,0(r3) - bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ -2: li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - blt 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mtlr r4 /* restore link register */ - blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr - - /* Setup the BAT registers. - */ -setup_bats: - lis r4, CFG_IBAT0L@h - ori r4, r4, CFG_IBAT0L@l - lis r3, CFG_IBAT0U@h - ori r3, r3, CFG_IBAT0U@l - mtspr IBAT0L, r4 - mtspr IBAT0U, r3 - isync - - lis r4, CFG_DBAT0L@h - ori r4, r4, CFG_DBAT0L@l - lis r3, CFG_DBAT0U@h - ori r3, r3, CFG_DBAT0U@l - mtspr DBAT0L, r4 - mtspr DBAT0U, r3 - isync - - lis r4, CFG_IBAT1L@h - ori r4, r4, CFG_IBAT1L@l - lis r3, CFG_IBAT1U@h - ori r3, r3, CFG_IBAT1U@l - mtspr IBAT1L, r4 - mtspr IBAT1U, r3 - isync - - lis r4, CFG_DBAT1L@h - ori r4, r4, CFG_DBAT1L@l - lis r3, CFG_DBAT1U@h - ori r3, r3, CFG_DBAT1U@l - mtspr DBAT1L, r4 - mtspr DBAT1U, r3 - isync - - lis r4, CFG_IBAT2L@h - ori r4, r4, CFG_IBAT2L@l - lis r3, CFG_IBAT2U@h - ori r3, r3, CFG_IBAT2U@l - mtspr IBAT2L, r4 - mtspr IBAT2U, r3 - isync - - lis r4, CFG_DBAT2L@h - ori r4, r4, CFG_DBAT2L@l - lis r3, CFG_DBAT2U@h - ori r3, r3, CFG_DBAT2U@l - mtspr DBAT2L, r4 - mtspr DBAT2U, r3 - isync - - lis r4, CFG_IBAT3L@h - ori r4, r4, CFG_IBAT3L@l - lis r3, CFG_IBAT3U@h - ori r3, r3, CFG_IBAT3U@l - mtspr IBAT3L, r4 - mtspr IBAT3U, r3 - isync - - lis r4, CFG_DBAT3L@h - ori r4, r4, CFG_DBAT3L@l - lis r3, CFG_DBAT3U@h - ori r3, r3, CFG_DBAT3U@l - mtspr DBAT3L, r4 - mtspr DBAT3U, r3 - isync - - /* Invalidate TLBs. - * -> for (val = 0; val < 0x20000; val+=0x1000) - * -> tlbie(val); - */ - lis r3, 0 - lis r5, 2 - -1: - tlbie r3 - addi r3, r3, 0x1000 - cmp 0, 0, r3, r5 - blt 1b - - blr diff --git a/cpu/mpc824x/traps.c b/cpu/mpc824x/traps.c deleted file mode 100644 index 071d003..0000000 --- a/cpu/mpc824x/traps.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * linux/arch/ppc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x00400000 - -/* - * Trap & Exception support - */ - -void -print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs * regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -void -_exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void -MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void -AlignmentException(struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void -ProgramCheckException(struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void -SoftEmuException(struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void -UnknownException(struct pt_regs *regs) -{ - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -void -DebugException(struct pt_regs *regs) -{ - - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int -addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/cpu/mpc8260/Makefile b/cpu/mpc8260/Makefile deleted file mode 100644 index b4c269f..0000000 --- a/cpu/mpc8260/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o kgdb.o -OBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ - interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \ - bedbug_603e.o pci.o spi.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) kgdb.o - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/mpc8260/bedbug_603e.c b/cpu/mpc8260/bedbug_603e.c deleted file mode 100644 index be09cfb..0000000 --- a/cpu/mpc8260/bedbug_603e.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Bedbug Functions specific to the MPC603e core - */ - -#include -#include -#include -#include -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)) - -#define MAX_BREAK_POINTS 1 - -extern CPU_DEBUG_CTX bug_ctx; - -void bedbug603e_init __P((void)); -void bedbug603e_do_break __P((cmd_tbl_t*,int,int,char*[])); -void bedbug603e_break_isr __P((struct pt_regs*)); -int bedbug603e_find_empty __P((void)); -int bedbug603e_set __P((int,unsigned long)); -int bedbug603e_clear __P((int)); - - -/* ====================================================================== - * Initialize the global bug_ctx structure for the processor. Clear all - * of the breakpoints. - * ====================================================================== */ - -void bedbug603e_init( void ) -{ - int i; - /* -------------------------------------------------- */ - - bug_ctx.hw_debug_enabled = 0; - bug_ctx.stopped = 0; - bug_ctx.current_bp = 0; - bug_ctx.regs = NULL; - - bug_ctx.do_break = bedbug603e_do_break; - bug_ctx.break_isr = bedbug603e_break_isr; - bug_ctx.find_empty = bedbug603e_find_empty; - bug_ctx.set = bedbug603e_set; - bug_ctx.clear = bedbug603e_clear; - - for( i = 1; i <= MAX_BREAK_POINTS; ++i ) - (*bug_ctx.clear)( i ); - - puts ("BEDBUG:ready\n"); - return; -} /* bedbug_init_breakpoints */ - - - -/* ====================================================================== - * Set/clear/show the hardware breakpoint for the 603e. The "off" - * string will disable a specific breakpoint. The "show" string will - * display the current breakpoints. Otherwise an address will set a - * breakpoint at that address. Setting a breakpoint uses the CPU-specific - * set routine which will assign a breakpoint number. - * ====================================================================== */ - -void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc, - char *argv[]) -{ - long addr; /* Address to break at */ - int which_bp; /* Breakpoint number */ - /* -------------------------------------------------- */ - - if (argc < 2) - { - printf ("Usage:\n%s\n", cmdtp->usage); - return; - } - - /* Turn off a breakpoint */ - - if( strcmp( argv[ 1 ], "off" ) == 0 ) - { - if( bug_ctx.hw_debug_enabled == 0 ) - { - puts ( "No breakpoints enabled\n" ); - return; - } - - which_bp = simple_strtoul( argv[ 2 ], NULL, 10 ); - - if( bug_ctx.clear ) - (*bug_ctx.clear)( which_bp ); - - printf( "Breakpoint %d removed\n", which_bp ); - return; - } - - /* Show a list of breakpoints */ - - if( strcmp( argv[ 1 ], "show" ) == 0 ) - { - for( which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp ) - { - - addr = GET_IABR(); - - printf( "Breakpoint [%d]: ", which_bp ); - if( (addr & 0x00000002) == 0 ) - puts ( "NOT SET\n" ); - else - disppc( (unsigned char *)(addr & 0xFFFFFFFC), 0, 1, bedbug_puts, F_RADHEX ); - } - return; - } - - /* Set a breakpoint at the address */ - - if(!(( isdigit( argv[ 1 ][ 0 ] )) || - (( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) || - (( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' )))) - { - printf ("Usage:\n%s\n", cmdtp->usage); - return; - } - - addr = simple_strtoul( argv[ 1 ], NULL, 16 ); - - if(( bug_ctx.set ) && ( which_bp = (*bug_ctx.set)( 0, addr )) > 0 ) - { - printf( "Breakpoint [%d]: ", which_bp ); - disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); - } - - return; -} /* bedbug603e_do_break */ - - - -/* ====================================================================== - * Handle a breakpoint. Enter a mini main loop. Stay in the loop until - * the stopped flag in the debug context is cleared. - * ====================================================================== */ - -void bedbug603e_break_isr( struct pt_regs *regs ) -{ - unsigned long addr; /* Address stopped at */ - /* -------------------------------------------------- */ - - bug_ctx.current_bp = 1; - addr = GET_IABR() & 0xFFFFFFFC; - - bedbug_main_loop( addr, regs ); - return; -} /* bedbug603e_break_isr */ - - - -/* ====================================================================== - * See if the hardware breakpoint is available. - * ====================================================================== */ - -int bedbug603e_find_empty( void ) -{ - /* -------------------------------------------------- */ - - if( (GET_IABR() && 0x00000002) == 0 ) - return 1; - - return 0; -} /* bedbug603e_find_empty */ - - - -/* ====================================================================== - * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint - * number, otherwise reassign the given breakpoint. If hardware debugging - * is not enabled, then turn it on via the MSR and DBCR0. Set the break - * address in the IABR register. - * ====================================================================== */ - -int bedbug603e_set( int which_bp, unsigned long addr ) -{ - /* -------------------------------------------------- */ - - if(( addr & 0x00000003 ) != 0 ) - { - puts ( "Breakpoints must be on a 32 bit boundary\n" ); - return 0; - } - - /* Only look if which_bp == 0, else use which_bp */ - if(( bug_ctx.find_empty ) && ( !which_bp ) && - ( which_bp = (*bug_ctx.find_empty)()) == 0 ) - { - puts ( "All breakpoints in use\n" ); - return 0; - } - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # %d\n", which_bp ); - return 0; - } - - if( ! bug_ctx.hw_debug_enabled ) - { - bug_ctx.hw_debug_enabled = 1; - } - - SET_IABR( addr | 0x00000002 ); - - return which_bp; -} /* bedbug603e_set */ - - - -/* ====================================================================== - * Disable a specific breakoint by setting the IABR register to zero. - * ====================================================================== */ - -int bedbug603e_clear( int which_bp ) -{ - /* -------------------------------------------------- */ - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # (%d)\n", which_bp ); - return -1; - } - - SET_IABR( 0 ); - - return 0; -} /* bedbug603e_clear */ - - -/* ====================================================================== */ -#endif diff --git a/cpu/mpc8260/commproc.c b/cpu/mpc8260/commproc.c deleted file mode 100644 index e5c5fcf..0000000 --- a/cpu/mpc8260/commproc.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's - * copyright notice: - * - * General Purpose functions for the global management of the - * 8260 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) - * 2.3.99 Updates - * - * In addition to the individual control of the communication - * channels, there are a few functions that globally affect the - * communication processor. - * - * Buffer descriptors must be allocated from the dual ported memory - * space. The allocator for that is here. When the communication - * process is reset, we reclaim the memory available. There is - * currently no deallocator for this memory. - */ -#include -#include - -void -m8260_cpm_reset(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ulong count; - - /* Reclaim the DP memory for our use. - */ - gd->dp_alloc_base = CPM_DATAONLY_BASE; - gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE; - - /* - * Reset CPM - */ - immr->im_cpm.cp_cpcr = CPM_CR_RST; - count = 0; - do { /* Spin until command processed */ - __asm__ __volatile__ ("eieio"); - } while ((immr->im_cpm.cp_cpcr & CPM_CR_FLG) && ++count < 1000000); - -#ifdef CONFIG_HARD_I2C - *((unsigned short*)(&immr->im_dprambase[PROFF_I2C_BASE])) = 0; -#endif -} - -/* Allocate some memory from the dual ported ram. - * To help protocols with object alignment restrictions, we do that - * if they ask. - */ -uint -m8260_cpm_dpalloc(uint size, uint align) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *)CFG_IMMR; - uint retloc; - uint align_mask, off; - uint savebase; - - align_mask = align - 1; - savebase = gd->dp_alloc_base; - - if ((off = (gd->dp_alloc_base & align_mask)) != 0) - gd->dp_alloc_base += (align - off); - - if ((off = size & align_mask) != 0) - size += align - off; - - if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) { - gd->dp_alloc_base = savebase; - panic("m8260_cpm_dpalloc: ran out of dual port ram!"); - } - - retloc = gd->dp_alloc_base; - gd->dp_alloc_base += size; - - memset((void *)&immr->im_dprambase[retloc], 0, size); - - return(retloc); -} - -/* We also own one page of host buffer space for the allocation of - * UART "fifos" and the like. - */ -uint -m8260_cpm_hostalloc(uint size, uint align) -{ - /* the host might not even have RAM yet - just use dual port RAM */ - return (m8260_cpm_dpalloc(size, align)); -} - -/* Set a baud rate generator. This needs lots of work. There are - * eight BRGs, which can be connected to the CPM channels or output - * as clocks. The BRGs are in two different block of internal - * memory mapped space. - * The baud rate clock is the system clock divided by something. - * It was set up long ago during the initial boot phase and is - * is given to us. - * Baud rate clocks are zero-based in the driver code (as that maps - * to port numbers). Documentation uses 1-based numbering. - */ -#define BRG_INT_CLK gd->brg_clk -#define BRG_UART_CLK (BRG_INT_CLK / 16) - -/* This function is used by UARTs, or anything else that uses a 16x - * oversampled clock. - */ -void -m8260_cpm_setbrg(uint brg, uint rate) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile uint *bp; - uint cd = BRG_UART_CLK / rate; - - if ((BRG_UART_CLK % rate) < (rate / 2)) - cd--; - if (brg < 4) { - bp = (uint *)&immr->im_brgc1; - } - else { - bp = (uint *)&immr->im_brgc5; - brg -= 4; - } - bp += brg; - *bp = (cd << 1) | CPM_BRG_EN; -} - -/* This function is used to set high speed synchronous baud rate - * clocks. - */ -void -m8260_cpm_fastbrg(uint brg, uint rate, int div16) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile uint *bp; - - /* This is good enough to get SMCs running..... - */ - if (brg < 4) { - bp = (uint *)&immr->im_brgc1; - } - else { - bp = (uint *)&immr->im_brgc5; - brg -= 4; - } - bp += brg; - *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; - if (div16) - *bp |= CPM_BRG_DIV16; -} - -/* This function is used to set baud rate generators using an external - * clock source and 16x oversampling. - */ - -void -m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile uint *bp; - - if (brg < 4) { - bp = (uint *)&immr->im_brgc1; - } - else { - bp = (uint *)&immr->im_brgc5; - brg -= 4; - } - bp += brg; - *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; - if (pinsel == 0) - *bp |= CPM_BRG_EXTC_CLK3_9; - else - *bp |= CPM_BRG_EXTC_CLK5_15; -} - -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - -void post_word_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); - - *save_addr = a; -} - -ulong post_word_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); - - return *save_addr; -} - -#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_BOOTCOUNT_ADDR); - - save_addr[0] = a; - save_addr[1] = BOOTCOUNT_MAGIC; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_BOOTCOUNT_ADDR); - - if (save_addr[1] != BOOTCOUNT_MAGIC) - return 0; - else - return save_addr[0]; -} - -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk deleted file mode 100644 index dd7a71f..0000000 --- a/cpu/mpc8260/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \ - -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c deleted file mode 100644 index 5d97933..0000000 --- a/cpu/mpc8260/cpu.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x - * - * written or collected and sometimes rewritten by - * Magnus Damm - * - * modified by - * Wolfgang Denk - * - * modified for 8260 by - * Murray Jensen - * - * added 8260 masks by - * Marius Groeger - * - * added HiP7 (824x/827x/8280) processors support by - * Yuli Barcohen - */ - -#include -#include -#include -#include -#include -#include - -int checkcpu (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immap = (immap_t *) CFG_IMMR; - ulong clock = gd->cpu_clk; - uint pvr = get_pvr (); - uint immr, rev, m, k; - char buf[32]; - - puts ("CPU: "); - - switch (pvr) { - case PVR_8260: - case PVR_8260_HIP3: - k = 3; - break; - case PVR_8260_HIP4: - k = 4; - break; - case PVR_8260_HIP7R1: - case PVR_8260_HIP7RA: - case PVR_8260_HIP7: - k = 7; - break; - default: - return -1; /* whoops! not an MPC8260 */ - } - rev = pvr & 0xff; - - immr = immap->im_memctl.memc_immr; - if ((immr & IMMR_ISB_MSK) != CFG_IMMR) - return -1; /* whoops! someone moved the IMMR */ - - printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev); - - /* - * the bottom 16 bits of the immr are the Part Number and Mask Number - * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the - * RISC Microcode Revision Number (13-10). - * For the 8260, Motorola doesn't include the Microcode Revision - * in the mask. - */ - m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK); - k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]); - - switch (m) { - case 0x0000: - puts ("0.2 2J24M"); - break; - case 0x0010: - puts ("A.0 K22A"); - break; - case 0x0011: - puts ("A.1 1K22A-XC"); - break; - case 0x0001: - puts ("B.1 1K23A"); - break; - case 0x0021: - puts ("B.2 2K23A-XC"); - break; - case 0x0023: - puts ("B.3 3K23A"); - break; - case 0x0024: - puts ("C.2 6K23A"); - break; - case 0x0060: - puts ("A.0(A) 2K25A"); - break; - case 0x0062: - puts ("B.1 4K25A"); - break; - case 0x0064: - puts ("C.0 5K25A"); - break; - case 0x0A00: - puts ("0.0 0K49M"); - break; - case 0x0A01: - puts ("0.1 1K49M"); - break; - case 0x0A10: - puts ("1.0 1K49M"); - break; - case 0x0C00: - puts ("0.0 0K50M"); - break; - case 0x0C10: - puts ("1.0 1K50M"); - break; - case 0x0D00: - puts ("0.0 0K50M"); - break; - case 0x0D10: - puts ("1.0 1K50M"); - break; - default: - printf ("unknown [immr=0x%04x,k=0x%04x]", m, k); - break; - } - - printf (") at %s MHz\n", strmhz (buf, clock)); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -/* configures a UPM by writing into the UPM RAM array */ -/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */ -/* NOTE: the physical address chosen must not overlap into any other area */ -/* mapped by the memory controller because bank 11 has the lowest priority */ - -void upmconfig (uint upm, uint * table, uint size) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */ - uint i; - - /* first set up bank 11 to reference the correct UPM at a dummy address */ - - memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */ - - switch (upm) { - - case UPMA: - memctl->memc_br11 = - ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA | - BRx_V; - memctl->memc_mamr = MxMR_OP_WARR; - break; - - case UPMB: - memctl->memc_br11 = - ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB | - BRx_V; - memctl->memc_mbmr = MxMR_OP_WARR; - break; - - case UPMC: - memctl->memc_br11 = - ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC | - BRx_V; - memctl->memc_mcmr = MxMR_OP_WARR; - break; - - default: - panic ("upmconfig passed invalid UPM number (%u)\n", upm); - break; - - } - - /* - * at this point, the dummy address is set up to access the selected UPM, - * the MAD pointer is zero, and the MxMR OP is set for writing to RAM - * - * now we simply load the mdr with each word and poke the dummy address. - * the MAD is incremented on each access. - */ - - for (i = 0; i < size; i++) { - memctl->memc_mdr = table[i]; - *dummy = 0; - } - - /* now kill bank 11 */ - memctl->memc_br11 = 0; -} - -/* ------------------------------------------------------------------------- */ - -#if !defined(CONFIG_HAVE_OWN_RESET) -int -do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - ulong msr, addr; - - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */ - - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; -#else - /* - * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE - * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. - */ - addr = CFG_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*)(void)) addr) (); - return 1; - -} -#endif /* CONFIG_HAVE_OWN_RESET */ - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * - */ -unsigned long get_tbclk (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong tbclk; - - tbclk = (gd->bus_clk + 3L) / 4L; - - return (tbclk); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - reset_8260_watchdog ((immap_t *) CFG_IMMR); - if (re_enable) - enable_interrupts (); -} -#endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c deleted file mode 100644 index babcce4..0000000 --- a/cpu/mpc8260/cpu_init.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -static void config_8260_ioports (volatile immap_t * immr) -{ - int portnum; - - for (portnum = 0; portnum < 4; portnum++) { - uint pmsk = 0, - ppar = 0, - psor = 0, - pdir = 0, - podr = 0, - pdat = 0; - iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; - iop_conf_t *eiopc = iopc + 32; - uint msk = 1; - - /* - * NOTE: - * index 0 refers to pin 31, - * index 31 refers to pin 0 - */ - while (iopc < eiopc) { - if (iopc->conf) { - pmsk |= msk; - if (iopc->ppar) - ppar |= msk; - if (iopc->psor) - psor |= msk; - if (iopc->pdir) - pdir |= msk; - if (iopc->podr) - podr |= msk; - if (iopc->pdat) - pdat |= msk; - } - - msk <<= 1; - iopc++; - } - - if (pmsk != 0) { - volatile ioport_t *iop = ioport_addr (immr, portnum); - uint tpmsk = ~pmsk; - - /* - * the (somewhat confused) paragraph at the - * bottom of page 35-5 warns that there might - * be "unknown behaviour" when programming - * PSORx and PDIRx, if PPARx = 1, so I - * decided this meant I had to disable the - * dedicated function first, and enable it - * last. - */ - iop->ppar &= tpmsk; - iop->psor = (iop->psor & tpmsk) | psor; - iop->podr = (iop->podr & tpmsk) | podr; - iop->pdat = (iop->pdat & tpmsk) | pdat; - iop->pdir = (iop->pdir & tpmsk) | pdir; - iop->ppar |= ppar; - } - } -} - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f (volatile immap_t * immr) -{ - DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */ - uint sccr; -#endif - volatile memctl8260_t *memctl = &immr->im_memctl; - extern void m8260_cpm_reset (void); - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* RSR - Reset Status Register - clear all status (5-4) */ - gd->reset_status = immr->im_clkrst.car_rsr; - immr->im_clkrst.car_rsr = RSR_ALLBITS; - - /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */ - immr->im_clkrst.car_rmr = CFG_RMR; - - /* BCR - Bus Configuration Register (4-25) */ - immr->im_siu_conf.sc_bcr = CFG_BCR; - - /* SIUMCR - contains debug pin configuration (4-31) */ - immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; - - config_8260_ioports (immr); - - /* initialize time counter status and control register (4-40) */ - immr->im_sit.sit_tmcntsc = CFG_TMCNTSC; - - /* initialize the PIT (4-42) */ - immr->im_sit.sit_piscr = CFG_PISCR; - -#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */ - /* System clock control register (9-8) */ - sccr = immr->im_clkrst.car_sccr & - (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK); - immr->im_clkrst.car_sccr = sccr | - (CFG_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) ); -#endif /* !CONFIG_COGENT */ - - /* - * Memory Controller: - */ - - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ - -#if defined(CFG_OR0_REMAP) - memctl->memc_or0 = CFG_OR0_REMAP; -#endif -#if defined(CFG_OR1_REMAP) - memctl->memc_or1 = CFG_OR1_REMAP; -#endif - - /* now restrict to preliminary range */ - memctl->memc_br0 = CFG_BR0_PRELIM; - memctl->memc_or0 = CFG_OR0_PRELIM; - -#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; -#endif - -#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; -#endif - -#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; -#endif - -#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) - memctl->memc_or4 = CFG_OR4_PRELIM; - memctl->memc_br4 = CFG_BR4_PRELIM; -#endif - -#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) - memctl->memc_or5 = CFG_OR5_PRELIM; - memctl->memc_br5 = CFG_BR5_PRELIM; -#endif - -#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) - memctl->memc_or6 = CFG_OR6_PRELIM; - memctl->memc_br6 = CFG_BR6_PRELIM; -#endif - -#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) - memctl->memc_or7 = CFG_OR7_PRELIM; - memctl->memc_br7 = CFG_BR7_PRELIM; -#endif - -#if defined(CFG_BR8_PRELIM) && defined(CFG_OR8_PRELIM) - memctl->memc_or8 = CFG_OR8_PRELIM; - memctl->memc_br8 = CFG_BR8_PRELIM; -#endif - -#if defined(CFG_BR9_PRELIM) && defined(CFG_OR9_PRELIM) - memctl->memc_or9 = CFG_OR9_PRELIM; - memctl->memc_br9 = CFG_BR9_PRELIM; -#endif - -#if defined(CFG_BR10_PRELIM) && defined(CFG_OR10_PRELIM) - memctl->memc_or10 = CFG_OR10_PRELIM; - memctl->memc_br10 = CFG_BR10_PRELIM; -#endif - -#if defined(CFG_BR11_PRELIM) && defined(CFG_OR11_PRELIM) - memctl->memc_or11 = CFG_OR11_PRELIM; - memctl->memc_br11 = CFG_BR11_PRELIM; -#endif - - m8260_cpm_reset (); -} - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base; - - immr->im_cpm.cp_rccr = CFG_RCCR; - - return (0); -} - -/* - * print out the reason for the reset - */ -int prt_8260_rsr (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - static struct { - ulong mask; - char *desc; - } bits[] = { - { - RSR_JTRS, "JTAG"}, { - RSR_CSRS, "Check Stop"}, { - RSR_SWRS, "Software Watchdog"}, { - RSR_BMRS, "Bus Monitor"}, { - RSR_ESRS, "External Soft"}, { - RSR_EHRS, "External Hard"} - }; - static int n = sizeof bits / sizeof bits[0]; - ulong rsr = gd->reset_status; - int i; - char *sep; - - puts (CPU_ID_STR " Reset Status:"); - - sep = " "; - for (i = 0; i < n; i++) - if (rsr & bits[i].mask) { - printf ("%s%s", sep, bits[i].desc); - sep = ", "; - } - - puts ("\n\n"); - return (0); -} diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c deleted file mode 100644 index ed3515f..0000000 --- a/cpu/mpc8260/ether_fcc.c +++ /dev/null @@ -1,1190 +0,0 @@ -/* - * MPC8260 FCC Fast Ethernet - * - * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MPC8260 FCC Fast Ethernet - * Basic ET HW initialization and packet RX/TX routines - * - * This code will not perform the IO port configuration. This should be - * done in the iop_conf_t structure specific for the board. - * - * TODO: - * add a PHY driver to do the negotiation - * reflect negotiation results in FPSMR - * look for ways to configure the board specific stuff elsewhere, eg. - * config_xxx.h or the board directory - */ - -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) -#include -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \ - defined(CONFIG_NET_MULTI) - -static struct ether_fcc_info_s -{ - int ether_index; - int proff_enet; - ulong cpm_cr_enet_sblock; - ulong cpm_cr_enet_page; - ulong cmxfcr_mask; - ulong cmxfcr_value; -} - ether_fcc_info[] = -{ -#ifdef CONFIG_ETHER_ON_FCC1 -{ - 0, - PROFF_FCC1, - CPM_CR_FCC1_SBLOCK, - CPM_CR_FCC1_PAGE, - CFG_CMXFCR_MASK1, - CFG_CMXFCR_VALUE1 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC2 -{ - 1, - PROFF_FCC2, - CPM_CR_FCC2_SBLOCK, - CPM_CR_FCC2_PAGE, - CFG_CMXFCR_MASK2, - CFG_CMXFCR_VALUE2 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC3 -{ - 2, - PROFF_FCC3, - CPM_CR_FCC3_SBLOCK, - CPM_CR_FCC3_PAGE, - CFG_CMXFCR_MASK3, - CFG_CMXFCR_VALUE3 -}, -#endif -}; - -/*---------------------------------------------------------------------*/ - -/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ -#define PKT_MAXDMA_SIZE 1520 - -/* The FCC stores dest/src/type, data, and checksum for receive packets. */ -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 - -/* Maximum input buffer size. Must be a multiple of 32. */ -#define PKT_MAXBLR_SIZE 1536 - -#define TOUT_LOOP 1000000 - -#define TX_BUF_CNT 2 -#ifdef __GNUC__ -static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8))); -#else -#error "txbuf must be 64-bit aligned" -#endif - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FCC Ethernet Tx and Rx buffer descriptors. - * Provide for Double Buffering - * Note: PKTBUFSRX is defined in net.h - */ - -typedef volatile struct rtxbd { - cbd_t rxbd[PKTBUFSRX]; - cbd_t txbd[TX_BUF_CNT]; -} RTXBD; - -/* Good news: the FCC supports external BDs! */ -#ifdef __GNUC__ -static RTXBD rtx __attribute__ ((aligned(8))); -#else -#error "rtx must be 64-bit aligned" -#endif - -static int fec_send(struct eth_device* dev, volatile void *packet, int length) -{ - int i; - int result = 0; - - if (length <= 0) { - printf("fec: bad packet size: %d\n", length); - goto out; - } - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - puts ("fec: tx buffer not ready\n"); - goto out; - } - } - - rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx.txbd[txIdx].cbd_datlen = length; - rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | - BD_ENET_TX_WRAP); - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - puts ("fec: tx error\n"); - goto out; - } - } - -#ifdef ET_DEBUG - printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc); -#endif - - /* return only status bits */ - result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; - -out: - return result; -} - -static int fec_recv(struct eth_device* dev) -{ - int length; - - for (;;) - { - if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - length = rtx.rxbd[rxIdx].cbd_datlen; - - if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { - printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); - } - else { - /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[rxIdx], length - 4); - } - - - /* Give the buffer back to the FCC. */ - rtx.rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } - else { - rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - - -static int fec_init(struct eth_device* dev, bd_t *bis) -{ - struct ether_fcc_info_s * info = dev->priv; - int i; - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile cpm8260_t *cp = &(immr->im_cpm); - fcc_enet_t *pram_ptr; - unsigned long mem_addr; - -#if 0 - mii_discover_phy(); -#endif - - /* 28.9 - (1-2): ioports have been set up already */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) | - info->cmxfcr_value; - - /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */ - immr->im_fcc[info->ether_index].fcc_gfmr = - FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - - /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */ - immr->im_fcc[info->ether_index].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; - - /* 28.9 - (6): FDSR: Ethernet Syn */ - immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555; - - /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ - rxIdx = 0; - txIdx = 0; - - /* Setup Receiver Buffer Descriptors */ - for (i = 0; i < PKTBUFSRX; i++) - { - rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx.rxbd[i].cbd_datlen = 0; - rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; - } - rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* Setup Ethernet Transmitter Buffer Descriptors */ - for (i = 0; i < TX_BUF_CNT; i++) - { - rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); - rtx.txbd[i].cbd_datlen = 0; - rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; - } - rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* 28.9 - (7): initialise parameter ram */ - pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]); - - /* clear whole structure to make sure all reserved fields are zero */ - memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); - - /* - * common Parameter RAM area - * - * Allocate space in the reserved FCC area of DPRAM for the - * internal buffers. No one uses this space (yet), so we - * can do this. Later, we will add resource management for - * this area. - */ - mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); - pram_ptr->fen_genfcc.fcc_riptr = mem_addr; - pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; - /* - * Set maximum bytes per receive buffer. - * It must be a multiple of 32. - */ - pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; - pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); - pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); - - /* protocol-specific area */ - pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ - pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ - pram_ptr->fen_retlim = 15; /* Retry limit threshold */ - pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ - /* - * Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - * So, far we have only been given one Ethernet address. We make - * it unique by setting a few bits in the upper byte of the - * non-static part of the address. - */ -#define ea eth_get_dev()->enetaddr - pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */ - /* pad pointer. use tiptr since we don't need a specific padding char */ - pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; - pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */ - pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */ - pram_ptr->fen_rfthr = 1; - pram_ptr->fen_rfcnt = 1; -#if 0 - printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n", - pram_ptr->fen_genfcc.fcc_rbase); - printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n", - pram_ptr->fen_genfcc.fcc_tbase); -#endif - - /* 28.9 - (8): clear out events in FCCE */ - immr->im_fcc[info->ether_index].fcc_fcce = ~0x0; - - /* 28.9 - (9): FCCM: mask all events */ - immr->im_fcc[info->ether_index].fcc_fccm = 0; - - /* 28.9 - (10-12): we don't use ethernet interrupts */ - - /* 28.9 - (13) - * - * Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page, - info->cpm_cr_enet_sblock, - 0x0c, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); - - /* 28.9 - (14): enable tx/rx in gfmr */ - immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - - return 1; -} - -static void fec_halt(struct eth_device* dev) -{ - struct ether_fcc_info_s * info = dev->priv; - volatile immap_t *immr = (immap_t *)CFG_IMMR; - - /* write GFMR: disable tx/rx */ - immr->im_fcc[info->ether_index].fcc_gfmr &= - ~(FCC_GFMR_ENT | FCC_GFMR_ENR); -} - -int fec_initialize(bd_t *bis) -{ - struct eth_device* dev; - int i; - - for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) - { - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - sprintf(dev->name, "FCC%d ETHERNET", - ether_fcc_info[i].ether_index + 1); - dev->priv = ðer_fcc_info[i]; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - eth_register(dev); - -#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \ - && defined(CONFIG_BITBANGMII) - miiphy_register(dev->name, - bb_miiphy_read, bb_miiphy_write); -#endif - } - - return 1; -} - -#ifdef CONFIG_ETHER_LOOPBACK_TEST - -#define ELBT_BUFSZ 1024 /* must be multiple of 32 */ - -#define ELBT_CRCSZ 4 - -#define ELBT_NRXBD 4 /* must be at least 2 */ -#define ELBT_NTXBD 4 - -#define ELBT_MAXRXERR 32 -#define ELBT_MAXTXERR 32 - -#define ELBT_CLSWAIT 1000 /* msec to wait for further input frames */ - -typedef - struct { - uint off; - char *lab; - } -elbt_prdesc; - -typedef - struct { - uint _l, _f, m, bc, mc, lg, no, sh, cr, ov, cl; - uint badsrc, badtyp, badlen, badbit; - } -elbt_rxeacc; - -static elbt_prdesc rxeacc_descs[] = { - { offsetof(elbt_rxeacc, _l), "Not Last in Frame" }, - { offsetof(elbt_rxeacc, _f), "Not First in Frame" }, - { offsetof(elbt_rxeacc, m), "Address Miss" }, - { offsetof(elbt_rxeacc, bc), "Broadcast Address" }, - { offsetof(elbt_rxeacc, mc), "Multicast Address" }, - { offsetof(elbt_rxeacc, lg), "Frame Length Violation"}, - { offsetof(elbt_rxeacc, no), "Non-Octet Alignment" }, - { offsetof(elbt_rxeacc, sh), "Short Frame" }, - { offsetof(elbt_rxeacc, cr), "CRC Error" }, - { offsetof(elbt_rxeacc, ov), "Overrun" }, - { offsetof(elbt_rxeacc, cl), "Collision" }, - { offsetof(elbt_rxeacc, badsrc), "Bad Src Address" }, - { offsetof(elbt_rxeacc, badtyp), "Bad Frame Type" }, - { offsetof(elbt_rxeacc, badlen), "Bad Frame Length" }, - { offsetof(elbt_rxeacc, badbit), "Data Compare Errors" }, -}; -static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]); - -typedef - struct { - uint def, hb, lc, rl, rc, un, csl; - } -elbt_txeacc; - -static elbt_prdesc txeacc_descs[] = { - { offsetof(elbt_txeacc, def), "Defer Indication" }, - { offsetof(elbt_txeacc, hb), "Heartbeat" }, - { offsetof(elbt_txeacc, lc), "Late Collision" }, - { offsetof(elbt_txeacc, rl), "Retransmission Limit" }, - { offsetof(elbt_txeacc, rc), "Retry Count" }, - { offsetof(elbt_txeacc, un), "Underrun" }, - { offsetof(elbt_txeacc, csl), "Carrier Sense Lost" }, -}; -static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]); - -typedef - struct { - uchar rxbufs[ELBT_NRXBD][ELBT_BUFSZ]; - uchar txbufs[ELBT_NTXBD][ELBT_BUFSZ]; - cbd_t rxbd[ELBT_NRXBD]; - cbd_t txbd[ELBT_NTXBD]; - enum { Idle, Running, Closing, Closed } state; - int proff, page, sblock; - uint clstime, nsent, ntxerr, nrcvd, nrxerr; - ushort rxerrs[ELBT_MAXRXERR], txerrs[ELBT_MAXTXERR]; - elbt_rxeacc rxeacc; - elbt_txeacc txeacc; - } __attribute__ ((aligned(8))) -elbt_chan; - -static uchar patbytes[ELBT_NTXBD] = { - 0xff, 0xaa, 0x55, 0x00 -}; -static uint patwords[ELBT_NTXBD] = { - 0xffffffff, 0xaaaaaaaa, 0x55555555, 0x00000000 -}; - -#ifdef __GNUC__ -static elbt_chan elbt_chans[3] __attribute__ ((aligned(8))); -#else -#error "elbt_chans must be 64-bit aligned" -#endif - -#define CPM_CR_GRACEFUL_STOP_TX ((ushort)0x0005) - -static elbt_prdesc epram_descs[] = { - { offsetof(fcc_enet_t, fen_crcec), "CRC Errors" }, - { offsetof(fcc_enet_t, fen_alec), "Alignment Errors" }, - { offsetof(fcc_enet_t, fen_disfc), "Discarded Frames" }, - { offsetof(fcc_enet_t, fen_octc), "Octets" }, - { offsetof(fcc_enet_t, fen_colc), "Collisions" }, - { offsetof(fcc_enet_t, fen_broc), "Broadcast Frames" }, - { offsetof(fcc_enet_t, fen_mulc), "Multicast Frames" }, - { offsetof(fcc_enet_t, fen_uspc), "Undersize Frames" }, - { offsetof(fcc_enet_t, fen_frgc), "Fragments" }, - { offsetof(fcc_enet_t, fen_ospc), "Oversize Frames" }, - { offsetof(fcc_enet_t, fen_jbrc), "Jabbers" }, - { offsetof(fcc_enet_t, fen_p64c), "64 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p65c), "65-127 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p128c), "128-255 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p256c), "256-511 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" }, - { offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"}, -}; -static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]); - -/* - * given an elbt_prdesc array and an array of base addresses, print - * each prdesc down the screen with the values fetched from each - * base address across the screen - */ -static void -print_desc (elbt_prdesc descs[], int ndesc, uchar *bases[], int nbase) -{ - elbt_prdesc *dp = descs, *edp = dp + ndesc; - int i; - - printf ("%32s", ""); - - for (i = 0; i < nbase; i++) - printf (" Channel %d", i); - - putc ('\n'); - - while (dp < edp) { - - printf ("%-32s", dp->lab); - - for (i = 0; i < nbase; i++) { - uint val = *(uint *)(bases[i] + dp->off); - - printf (" %10u", val); - } - - putc ('\n'); - - dp++; - } -} - -/* - * return number of bits that are set in a value; value contains - * nbits (right-justified) bits. - */ -static uint __inline__ -nbs (uint value, uint nbits) -{ - uint cnt = 0; -#if 1 - uint pos = sizeof (uint) * 8; - - __asm__ __volatile__ ("\ - mtctr %2\n\ -1: rlwnm. %2,%1,%4,31,31\n\ - beq 2f\n\ - addi %0,%0,1\n\ -2: subi %4,%4,1\n\ - bdnz 1b" - : "=r"(cnt) - : "r"(value), "r"(nbits), "r"(cnt), "r"(pos) - : "ctr", "cc" ); -#else - uint mask = 1; - - do { - if (value & mask) - cnt++; - mask <<= 1; - } while (--nbits); -#endif - - return (cnt); -} - -static ulong -badbits (uchar *bp, int n, ulong pat) -{ - ulong *lp, cnt = 0; - int nl; - - while (n > 0 && ((ulong)bp & (sizeof (ulong) - 1)) != 0) { - uchar diff; - - diff = *bp++ ^ (uchar)pat; - - if (diff) - cnt += nbs ((ulong)diff, 8); - - n--; - } - - lp = (ulong *)bp; - nl = n / sizeof (ulong); - n -= nl * sizeof (ulong); - - while (nl > 0) { - ulong diff; - - diff = *lp++ ^ pat; - - if (diff) - cnt += nbs (diff, 32); - - nl--; - } - - bp = (uchar *)lp; - - while (n > 0) { - uchar diff; - - diff = *bp++ ^ (uchar)pat; - - if (diff) - cnt += nbs ((ulong)diff, 8); - - n--; - } - - return (cnt); -} - -static inline unsigned short -swap16 (unsigned short x) -{ - return (((x & 0xff) << 8) | ((x & 0xff00) >> 8)); -} - -/* broadcast is not an error - we send them like that */ -#define BD_ENET_RX_ERRS (BD_ENET_RX_STATS & ~BD_ENET_RX_BC) - -void -eth_loopback_test (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile cpm8260_t *cp = &(immr->im_cpm); - int c, nclosed; - ulong runtime, nmsec; - uchar *bases[3]; - - puts ("FCC Ethernet External loopback test\n"); - - memcpy (NetOurEther, gd->bd->bi_enetaddr, 6); - - /* - * global initialisations for all FCC channels - */ - - /* 28.9 - (1-2): ioports have been set up already */ - -#if defined(CONFIG_HYMOD) - /* - * Attention: this is board-specific - * 0, FCC1 - * 1, FCC2 - * 2, FCC3 - */ -# define FCC_START_LOOP 0 -# define FCC_END_LOOP 2 - - /* - * Attention: this is board-specific - * - FCC1 Rx-CLK is CLK10 - * - FCC1 Tx-CLK is CLK11 - * - FCC2 Rx-CLK is CLK13 - * - FCC2 Tx-CLK is CLK14 - * - FCC3 Rx-CLK is CLK15 - * - FCC3 Tx-CLK is CLK16 - */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\ - CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\ - CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16; -#elif defined(CONFIG_SBC8260) || defined(CONFIG_SACSng) - /* - * Attention: this is board-specific - * 1, FCC2 - */ -# define FCC_START_LOOP 1 -# define FCC_END_LOOP 1 - - /* - * Attention: this is board-specific - * - FCC2 Rx-CLK is CLK13 - * - FCC2 Tx-CLK is CLK14 - */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14; -#else -#error "eth_loopback_test not supported on your board" -#endif - - puts ("Initialise FCC channels:"); - - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { - elbt_chan *ecp = &elbt_chans[c]; - volatile fcc_t *fcp = &immr->im_fcc[c]; - volatile fcc_enet_t *fpp; - int i; - ulong addr; - - /* - * initialise channel data - */ - - printf (" %d", c); - - memset ((void *)ecp, 0, sizeof (*ecp)); - - ecp->state = Idle; - - switch (c) { - - case 0: /* FCC1 */ - ecp->proff = PROFF_FCC1; - ecp->page = CPM_CR_FCC1_PAGE; - ecp->sblock = CPM_CR_FCC1_SBLOCK; - break; - - case 1: /* FCC2 */ - ecp->proff = PROFF_FCC2; - ecp->page = CPM_CR_FCC2_PAGE; - ecp->sblock = CPM_CR_FCC2_SBLOCK; - break; - - case 2: /* FCC3 */ - ecp->proff = PROFF_FCC3; - ecp->page = CPM_CR_FCC3_PAGE; - ecp->sblock = CPM_CR_FCC3_SBLOCK; - break; - } - - /* - * set up tx buffers and bds - */ - - for (i = 0; i < ELBT_NTXBD; i++) { - cbd_t *bdp = &ecp->txbd[i]; - uchar *bp = &ecp->txbufs[i][0]; - - bdp->cbd_bufaddr = (uint)bp; - /* room for crc */ - bdp->cbd_datlen = ELBT_BUFSZ - ELBT_CRCSZ; - bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \ - BD_ENET_TX_LAST | BD_ENET_TX_TC; - - memset ((void *)bp, patbytes[i], ELBT_BUFSZ); - NetSetEther (bp, NetBcastAddr, 0x8000); - } - ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* - * set up rx buffers and bds - */ - - for (i = 0; i < ELBT_NRXBD; i++) { - cbd_t *bdp = &ecp->rxbd[i]; - uchar *bp = &ecp->rxbufs[i][0]; - - bdp->cbd_bufaddr = (uint)bp; - bdp->cbd_datlen = 0; - bdp->cbd_sc = BD_ENET_RX_EMPTY; - - memset ((void *)bp, 0, ELBT_BUFSZ); - } - ecp->rxbd[ELBT_NRXBD - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * set up the FCC channel hardware - */ - - /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */ - fcp->fcc_gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - - /* 28.9 - (5): FPSMR: fd, enet CRC, Promis, RMON, Rx SHort */ - fcp->fcc_fpsmr = FCC_PSMR_FDE | FCC_PSMR_LPB | \ - FCC_PSMR_ENCRC | FCC_PSMR_PRO | \ - FCC_PSMR_MON | FCC_PSMR_RSH; - - /* 28.9 - (6): FDSR: Ethernet Syn */ - fcp->fcc_fdsr = 0xD555; - - /* 29.9 - (7): initialise parameter ram */ - fpp = (fcc_enet_t *)&(immr->im_dprambase[ecp->proff]); - - /* clear whole struct to make sure all resv fields are zero */ - memset ((void *)fpp, 0, sizeof (fcc_enet_t)); - - /* - * common Parameter RAM area - * - * Allocate space in the reserved FCC area of DPRAM for the - * internal buffers. No one uses this space (yet), so we - * can do this. Later, we will add resource management for - * this area. - */ - addr = CPM_FCC_SPECIAL_BASE + (c * 64); - fpp->fen_genfcc.fcc_riptr = addr; - fpp->fen_genfcc.fcc_tiptr = addr + 32; - - /* - * Set maximum bytes per receive buffer. - * It must be a multiple of 32. - * buffers are in 60x bus memory. - */ - fpp->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; - fpp->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24; - fpp->fen_genfcc.fcc_rbase = (unsigned int)(&ecp->rxbd[0]); - fpp->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24; - fpp->fen_genfcc.fcc_tbase = (unsigned int)(&ecp->txbd[0]); - - /* protocol-specific area */ - fpp->fen_cmask = 0xdebb20e3; /* CRC mask */ - fpp->fen_cpres = 0xffffffff; /* CRC preset */ - fpp->fen_retlim = 15; /* Retry limit threshold */ - fpp->fen_mflr = PKT_MAXBUF_SIZE;/* max frame length register */ - - /* - * Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - * So, far we have only been given one Ethernet address. We use - * the same address for all channels - */ -#define ea gd->bd->bi_enetaddr - fpp->fen_paddrh = (ea[5] << 8) + ea[4]; - fpp->fen_paddrm = (ea[3] << 8) + ea[2]; - fpp->fen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - - fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */ - /* - * pad pointer. use tiptr since we don't need - * a specific padding char - */ - fpp->fen_padptr = fpp->fen_genfcc.fcc_tiptr; - fpp->fen_maxd1 = PKT_MAXDMA_SIZE; /* max DMA1 length */ - fpp->fen_maxd2 = PKT_MAXDMA_SIZE; /* max DMA2 length */ - fpp->fen_rfthr = 1; - fpp->fen_rfcnt = 1; - - /* 28.9 - (8): clear out events in FCCE */ - fcp->fcc_fcce = ~0x0; - - /* 28.9 - (9): FCCM: mask all events */ - fcp->fcc_fccm = 0; - - /* 28.9 - (10-12): we don't use ethernet interrupts */ - - /* 28.9 - (13) - * - * Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cp_cpcr = mk_cr_cmd (ecp->page, ecp->sblock, \ - 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); - } - - puts (" done\nStarting test... (Ctrl-C to Finish)\n"); - - /* - * Note: don't want serial output from here until the end of the - * test - the delays would probably stuff things up. - */ - - clear_ctrlc (); - runtime = get_timer (0); - - do { - nclosed = 0; - - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { - volatile fcc_t *fcp = &immr->im_fcc[c]; - elbt_chan *ecp = &elbt_chans[c]; - int i; - - switch (ecp->state) { - - case Idle: - /* - * set the channel Running ... - */ - - /* 28.9 - (14): enable tx/rx in gfmr */ - fcp->fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - - ecp->state = Running; - break; - - case Running: - /* - * (while Running only) check for - * termination of the test - */ - - (void)ctrlc (); - - if (had_ctrlc ()) { - /* - * initiate a "graceful stop transmit" - * on the channel - */ - cp->cp_cpcr = mk_cr_cmd (ecp->page, \ - ecp->sblock, 0x0c, \ - CPM_CR_GRACEFUL_STOP_TX) | \ - CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); - - ecp->clstime = get_timer (0); - ecp->state = Closing; - } - /* fall through ... */ - - case Closing: - /* - * (while Running or Closing) poll the channel: - * - check for any non-READY tx buffers and - * make them ready - * - check for any non-EMPTY rx buffers and - * check that they were received correctly, - * adjust counters etc, then make empty - */ - - for (i = 0; i < ELBT_NTXBD; i++) { - cbd_t *bdp = &ecp->txbd[i]; - ushort sc = bdp->cbd_sc; - - if ((sc & BD_ENET_TX_READY) != 0) - continue; - - /* - * this frame has finished - * transmitting - */ - ecp->nsent++; - - if (sc & BD_ENET_TX_STATS) { - ulong n; - - /* - * we had an error on - * the transmission - */ - n = ecp->ntxerr++; - if (n < ELBT_MAXTXERR) - ecp->txerrs[n] = sc; - - if (sc & BD_ENET_TX_DEF) - ecp->txeacc.def++; - if (sc & BD_ENET_TX_HB) - ecp->txeacc.hb++; - if (sc & BD_ENET_TX_LC) - ecp->txeacc.lc++; - if (sc & BD_ENET_TX_RL) - ecp->txeacc.rl++; - if (sc & BD_ENET_TX_RCMASK) - ecp->txeacc.rc++; - if (sc & BD_ENET_TX_UN) - ecp->txeacc.un++; - if (sc & BD_ENET_TX_CSL) - ecp->txeacc.csl++; - - bdp->cbd_sc &= \ - ~BD_ENET_TX_STATS; - } - - if (ecp->state == Closing) - ecp->clstime = get_timer (0); - - /* make it ready again */ - bdp->cbd_sc |= BD_ENET_TX_READY; - } - - for (i = 0; i < ELBT_NRXBD; i++) { - cbd_t *bdp = &ecp->rxbd[i]; - ushort sc = bdp->cbd_sc, mask; - - if ((sc & BD_ENET_RX_EMPTY) != 0) - continue; - - /* we have a new frame in this buffer */ - ecp->nrcvd++; - - mask = BD_ENET_RX_LAST|BD_ENET_RX_FIRST; - if ((sc & mask) != mask) { - /* somethings wrong here ... */ - if (!(sc & BD_ENET_RX_LAST)) - ecp->rxeacc._l++; - if (!(sc & BD_ENET_RX_FIRST)) - ecp->rxeacc._f++; - } - - if (sc & BD_ENET_RX_ERRS) { - ulong n; - - /* - * we had some sort of error - * on the frame - */ - n = ecp->nrxerr++; - if (n < ELBT_MAXRXERR) - ecp->rxerrs[n] = sc; - - if (sc & BD_ENET_RX_MISS) - ecp->rxeacc.m++; - if (sc & BD_ENET_RX_BC) - ecp->rxeacc.bc++; - if (sc & BD_ENET_RX_MC) - ecp->rxeacc.mc++; - if (sc & BD_ENET_RX_LG) - ecp->rxeacc.lg++; - if (sc & BD_ENET_RX_NO) - ecp->rxeacc.no++; - if (sc & BD_ENET_RX_SH) - ecp->rxeacc.sh++; - if (sc & BD_ENET_RX_CR) - ecp->rxeacc.cr++; - if (sc & BD_ENET_RX_OV) - ecp->rxeacc.ov++; - if (sc & BD_ENET_RX_CL) - ecp->rxeacc.cl++; - - bdp->cbd_sc &= \ - ~BD_ENET_RX_ERRS; - } - else { - ushort datlen = bdp->cbd_datlen; - Ethernet_t *ehp; - ushort prot; - int ours, tb, n, nbytes; - - ehp = (Ethernet_t *) \ - &ecp->rxbufs[i][0]; - - ours = memcmp (ehp->et_src, \ - NetOurEther, 6); - - prot = swap16 (ehp->et_protlen); - tb = prot & 0x8000; - n = prot & 0x7fff; - - nbytes = ELBT_BUFSZ - \ - offsetof (Ethernet_t, \ - et_dsap) - \ - ELBT_CRCSZ; - - /* check the frame is correct */ - if (datlen != ELBT_BUFSZ) - ecp->rxeacc.badlen++; - else if (!ours) - ecp->rxeacc.badsrc++; - else if (!tb || n >= ELBT_NTXBD) - ecp->rxeacc.badtyp++; - else { - ulong patword = \ - patwords[n]; - uint nbb; - - nbb = badbits ( \ - &ehp->et_dsap, \ - nbytes, \ - patword); - - ecp->rxeacc.badbit += \ - nbb; - } - } - - if (ecp->state == Closing) - ecp->clstime = get_timer (0); - - /* make it empty again */ - bdp->cbd_sc |= BD_ENET_RX_EMPTY; - } - - if (ecp->state != Closing) - break; - - /* - * (while Closing) check to see if - * waited long enough - */ - - if (get_timer (ecp->clstime) >= ELBT_CLSWAIT) { - /* write GFMR: disable tx/rx */ - fcp->fcc_gfmr &= \ - ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - ecp->state = Closed; - } - - break; - - case Closed: - nclosed++; - break; - } - } - - } while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1)); - - runtime = get_timer (runtime); - if (runtime <= ELBT_CLSWAIT) { - printf ("Whoops! somehow elapsed time (%ld) is wrong (<= %d)\n", - runtime, ELBT_CLSWAIT); - return; - } - nmsec = runtime - ELBT_CLSWAIT; - - printf ("Test Finished in %ldms (plus %dms close wait period)!\n\n", - nmsec, ELBT_CLSWAIT); - - /* - * now print stats - */ - - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) { - elbt_chan *ecp = &elbt_chans[c]; - uint rxpps, txpps, nerr; - - rxpps = (ecp->nrcvd * 1000) / nmsec; - txpps = (ecp->nsent * 1000) / nmsec; - - printf ("Channel %d: %d rcvd (%d pps, %d rxerrs), " - "%d sent (%d pps, %d txerrs)\n\n", c, - ecp->nrcvd, rxpps, ecp->nrxerr, - ecp->nsent, txpps, ecp->ntxerr); - - if ((nerr = ecp->nrxerr) > 0) { - ulong i; - - printf ("\tFirst %d rx errs:", nerr); - for (i = 0; i < nerr; i++) - printf (" %04x", ecp->rxerrs[i]); - putc ('\n'); - } - - if ((nerr = ecp->ntxerr) > 0) { - ulong i; - - printf ("\tFirst %d tx errs:", nerr); - for (i = 0; i < nerr; i++) - printf (" %04x", ecp->txerrs[i]); - putc ('\n'); - } - } - - puts ("Receive Error Counts:\n"); - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) - bases[c] = (uchar *)&elbt_chans[c].rxeacc; - print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3); - - puts ("\nTransmit Error Counts:\n"); - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) - bases[c] = (uchar *)&elbt_chans[c].txeacc; - print_desc (txeacc_descs, txeacc_ndesc, bases, 3); - - puts ("\nRMON(-like) Counters:\n"); - for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) - bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff]; - print_desc (epram_descs, epram_ndesc, bases, 3); -} - -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - -#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */ diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c deleted file mode 100644 index a733b45..0000000 --- a/cpu/mpc8260/ether_scc.c +++ /dev/null @@ -1,356 +0,0 @@ -/* - * MPC8260 SCC Ethernet - * - * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright (c) 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_COMMANDS & CFG_CMD_NET) - -#if (CONFIG_ETHER_INDEX == 1) -# define PROFF_ENET PROFF_SCC1 -# define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC1 |\ - CMXSCR_RS1CS_MSK |\ - CMXSCR_TS1CS_MSK) - -#elif (CONFIG_ETHER_INDEX == 2) -# define PROFF_ENET PROFF_SCC2 -# define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC2 |\ - CMXSCR_RS2CS_MSK |\ - CMXSCR_TS2CS_MSK) - -#elif (CONFIG_ETHER_INDEX == 3) -# define PROFF_ENET PROFF_SCC3 -# define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC3 |\ - CMXSCR_RS3CS_MSK |\ - CMXSCR_TS3CS_MSK) -#elif (CONFIG_ETHER_INDEX == 4) -# define PROFF_ENET PROFF_SCC4 -# define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE -# define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK -# define CMXSCR_MASK (CMXSCR_SC4 |\ - CMXSCR_RS4CS_MSK |\ - CMXSCR_TS4CS_MSK) - -#endif - - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 1000000 - -static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * SCC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx; - - -int eth_send(volatile void *packet, int length) -{ - int i; - int result = 0; - - if (length <= 0) { - printf("scc: bad packet size: %d\n", length); - goto out; - } - - for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - puts ("scc: tx buffer not ready\n"); - goto out; - } - } - - rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | - BD_ENET_TX_WRAP); - - for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - puts ("scc: tx error\n"); - goto out; - } - } - - /* return only status bits */ - result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; - - out: - return result; -} - - -int eth_rx(void) -{ - int length; - - for (;;) - { - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) - { - printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); - } - else - { - /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[rxIdx], length - 4); - } - - - /* Give the buffer back to the SCC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | - BD_ENET_RX_EMPTY); - rxIdx = 0; - } - else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - -/************************************************************** - * - * SCC Ethernet Initialization Routine - * - *************************************************************/ - -int eth_init(bd_t *bis) -{ - int i; - volatile immap_t *immr = (immap_t *)CFG_IMMR; - scc_enet_t *pram_ptr; - uint dpaddr; - - rxIdx = 0; - txIdx = 0; - - /* assign static pointer to BD area */ - dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16); - rtx = (RTXBD *)&immr->im_dprambase[dpaddr]; - - /* 24.21 - (1-3): ioports have been set up already */ - - /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) | - CFG_CMXSCR_VALUE); - - - /* 24.21 (6) write RBASE and TBASE to parameter RAM */ - pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]); - pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); - pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); - - pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */ - pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */ - - pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */ - - pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ - pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ - - - /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */ - while(immr->im_cpm.cp_cpcr & CPM_CR_FLG); - immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE, - CPM_CR_ENET_SBLOCK, - 0x0c, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - - /* 24.21 - (8-18): Set up parameter RAM */ - pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ - pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */ - pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ - - pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ - - pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ - - pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ - pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ - - pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ - pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ - - pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ - pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ - pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ - pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ - -# define ea bis->bi_enetaddr - pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; -# undef ea - - pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ - - pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ - pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ - pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ - pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ - - pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ - pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ - pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ - - - /* 24.21 - (19): Initialize RxBD */ - for (i = 0; i < PKTBUFSRX; i++) - { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; - } - - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* 24.21 - (20): Initialize TxBD */ - for (i = 0; i < TX_BUF_CNT; i++) - { - rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | - BD_ENET_TX_LAST | - BD_ENET_TX_TC); - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; - } - - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* 24.21 - (21): Write 0xffff to SCCE */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0); - - /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE | - SCCE_ENET_RXF | - SCCE_ENET_TXB); - - /* 24.21 - (23): we don't use ethernet interrupts */ - - /* 24.21 - (24): Clear GSMR_H to enable normal operations */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0; - - /* 24.21 - (25): Clear GSMR_L to enable normal operations */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI | - SCC_GSMRL_TPL_48 | - SCC_GSMRL_TPP_10 | - SCC_GSMRL_MODE_ENET); - - /* 24.21 - (26): Initialize DSR */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555; - - /* 24.21 - (27): Initialize PSMR2 - * - * Settings: - * CRC = 32-Bit CCITT - * NIB = Begin searching for SFD 22 bits after RENA - * FDE = Full Duplex Enable - * BRO = Reject broadcast packets - * PROMISCOUS = Catch all packets regardless of dest. MAC adress - */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC | - SCC_PSMR_NIB22 | -#if defined(CONFIG_SCC_ENET_FULL_DUPLEX) - SCC_PSMR_FDE | -#endif -#if defined(CONFIG_SCC_ENET_NO_BROADCAST) - SCC_PSMR_BRO | -#endif -#if defined(CONFIG_SCC_ENET_PROMISCOUS) - SCC_PSMR_PRO | -#endif - 0; - - /* 24.21 - (28): Write to GSMR_L to enable SCC */ - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | - SCC_GSMRL_ENT); - - return 0; -} - - -void eth_halt(void) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR | - SCC_GSMRL_ENT); -} - -#if 0 -void restart(void) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | - SCC_GSMRL_ENT); -} -#endif - -#endif /* CONFIG_ETHER_ON_SCC && CFG_CMD_NET */ diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c deleted file mode 100644 index ea97ab8..0000000 --- a/cpu/mpc8260/i2c.c +++ /dev/null @@ -1,768 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if defined(CONFIG_HARD_I2C) - -#include -#include - -/* define to enable debug messages */ -#undef DEBUG_I2C - -/* uSec to wait between polls of the i2c */ -#define DELAY_US 100 -/* uSec to wait for the CPM to start processing the buffer */ -#define START_DELAY_US 1000 - -/* - * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the - * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP - */ -#define TOUT_LOOP 5 - -/*----------------------------------------------------------------------- - * Set default values - */ -#ifndef CFG_I2C_SPEED -#define CFG_I2C_SPEED 50000 -#endif - -#ifndef CFG_I2C_SLAVE -#define CFG_I2C_SLAVE 0xFE -#endif -/*----------------------------------------------------------------------- - */ - -typedef void (*i2c_ecb_t)(int, int, void *); /* error callback function */ - -/* This structure keeps track of the bd and buffer space usage. */ -typedef struct i2c_state { - int rx_idx; /* index to next free Rx BD */ - int tx_idx; /* index to next free Tx BD */ - void *rxbd; /* pointer to next free Rx BD */ - void *txbd; /* pointer to next free Tx BD */ - int tx_space; /* number of Tx bytes left */ - unsigned char *tx_buf; /* pointer to free Tx area */ - i2c_ecb_t err_cb; /* error callback function */ - void *cb_data; /* private data to be passed */ -} i2c_state_t; - -/* flags for i2c_send() and i2c_receive() */ -#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */ -#define I2CF_START_COND 0x02 /* tx: generate start condition */ -#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */ - -/* return codes */ -#define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */ -#define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */ -#define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */ -#define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/receive */ -#define I2CERR_IO_ERROR 5 /* had an error during comms */ - -/* error callback flags */ -#define I2CECB_RX_ERR 0x10 /* this is a receive error */ -#define I2CECB_RX_OV 0x02 /* receive overrun error */ -#define I2CECB_RX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TX_ERR 0x20 /* this is a transmit error */ -#define I2CECB_TX_CL 0x01 /* transmit collision error */ -#define I2CECB_TX_UN 0x02 /* transmit underflow error */ -#define I2CECB_TX_NAK 0x04 /* transmit no ack error */ -#define I2CECB_TX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */ - -#define ERROR_I2C_NONE 0 -#define ERROR_I2C_LENGTH 1 - -#define I2C_WRITE_BIT 0x00 -#define I2C_READ_BIT 0x01 - -#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ - - -#define NUM_RX_BDS 4 -#define NUM_TX_BDS 4 -#define MAX_TX_SPACE 256 - -typedef struct I2C_BD -{ - unsigned short status; - unsigned short length; - unsigned char *addr; -} I2C_BD; -#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */ - -#define BD_I2C_TX_CL 0x0001 /* collision error */ -#define BD_I2C_TX_UN 0x0002 /* underflow error */ -#define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */ -#define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL) - -#define BD_I2C_RX_ERR BD_SC_OV - -#ifdef DEBUG_I2C -#define PRINTD(x) printf x -#else -#define PRINTD(x) -#endif - -/* - * Returns the best value of I2BRG to meet desired clock speed of I2C with - * input parameters (clock speed, filter, and predivider value). - * It returns computer speed value and the difference between it and desired - * speed. - */ -static inline int -i2c_roundrate(int hz, int speed, int filter, int modval, - int *brgval, int *totspeed) -{ - int moddiv = 1 << (5-(modval & 3)), brgdiv, div; - - PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n", - hz, speed, filter, modval)); - - div = moddiv * speed; - brgdiv = (hz + div - 1) / div; - - PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv)); - - *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter); - - if ((*brgval < 0) || (*brgval > 255)) { - PRINTD(("\t\trejected brgval=%d\n", *brgval)); - return -1; - } - - brgdiv = 2 * (*brgval + 3 + (2 * filter)); - div = moddiv * brgdiv ; - *totspeed = hz / div; - - PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed)); - - return 0; -} - -/* - * Sets the I2C clock predivider and divider to meet required clock speed. - */ -static int i2c_setrate(int hz, int speed) -{ - immap_t *immap = (immap_t *)CFG_IMMR ; - volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; - int brgval, - modval, /* 0-3 */ - bestspeed_diff = speed, - bestspeed_brgval=0, - bestspeed_modval=0, - bestspeed_filter=0, - totspeed, - filter = 0; /* Use this fixed value */ - - for (modval = 0; modval < 4; modval++) - { - if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0) - { - int diff = speed - totspeed ; - - if ((diff >= 0) && (diff < bestspeed_diff)) - { - bestspeed_diff = diff ; - bestspeed_modval = modval; - bestspeed_brgval = brgval; - bestspeed_filter = filter; - } - } - } - - PRINTD(("[I2C] Best is:\n")); - PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", - hz, speed, - bestspeed_filter, bestspeed_modval, bestspeed_brgval, - bestspeed_diff)); - - i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3); - i2c->i2c_i2brg = bestspeed_brgval & 0xff; - - PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg)); - - return 1 ; -} - -void i2c_init(int speed, int slaveadd) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immap = (immap_t *)CFG_IMMR ; - volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm; - volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; - volatile iic_t *iip; - ulong rbase, tbase; - volatile I2C_BD *rxbd, *txbd; - uint dpaddr; - -#ifdef CFG_I2C_INIT_BOARD - /* call board specific i2c bus reset routine before accessing the */ - /* environment, which might be in a chip on that bus. For details */ - /* about this problem see doc/I2C_Edge_Conditions. */ - i2c_init_board(); -#endif - - dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])); - if (dpaddr == 0) { - /* need to allocate dual port ram */ - dpaddr = m8260_cpm_dpalloc(64 + - (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) + - MAX_TX_SPACE, 64); - *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = dpaddr; - } - - /* - * initialise data in dual port ram: - * - * dpaddr -> parameter ram (64 bytes) - * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes) - * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes) - * tx buffer (MAX_TX_SPACE bytes) - */ - - iip = (iic_t *)&immap->im_dprambase[dpaddr]; - memset((void*)iip, 0, sizeof(iic_t)); - - rbase = dpaddr + 64; - tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD); - - /* Disable interrupts */ - i2c->i2c_i2mod = 0x00; - i2c->i2c_i2cmr = 0x00; - i2c->i2c_i2cer = 0xff; - i2c->i2c_i2add = slaveadd; - - /* - * Set the I2C BRG Clock division factor from desired i2c rate - * and current CPU rate (we assume sccr dfbgr field is 0; - * divide BRGCLK by 1) - */ - PRINTD(("[I2C] Setting rate...\n")); - i2c_setrate (gd->brg_clk, CFG_I2C_SPEED) ; - - /* Set I2C controller in master mode */ - i2c->i2c_i2com = 0x01; - - /* Initialize Tx/Rx parameters */ - iip->iic_rbase = rbase; - iip->iic_tbase = tbase; - rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]); - txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]); - - PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase)); - PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase)); - PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); - - /* Set big endian byte order */ - iip->iic_tfcr = 0x10; - iip->iic_rfcr = 0x10; - - /* Set maximum receive size. */ - iip->iic_mrblr = I2C_RXTX_LEN; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE, - CPM_CR_I2C_SBLOCK, - 0x00, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); - - /* Clear events and interrupts */ - i2c->i2c_i2cer = 0xff; - i2c->i2c_i2cmr = 0x00; -} - -static -void i2c_newio(i2c_state_t *state) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR ; - volatile iic_t *iip; - uint dpaddr; - - PRINTD(("[I2C] i2c_newio\n")); - - dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])); - iip = (iic_t *)&immap->im_dprambase[dpaddr]; - state->rx_idx = 0; - state->tx_idx = 0; - state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase]; - state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase]; - state->tx_space = MAX_TX_SPACE; - state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD); - state->err_cb = NULL; - state->cb_data = NULL; - - PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd)); - PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf)); - - /* clear the buffer memory */ - memset((char *)state->tx_buf, 0, MAX_TX_SPACE); -} - -static -int i2c_send(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, - unsigned short size, - unsigned char *dataout) -{ - volatile I2C_BD *txbd; - int i,j; - - PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n", - address, secondary_address, flags, size)); - - /* trying to send message larger than BD */ - if (size > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; - - /* no more free bds */ - if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size)) - return I2CERR_NO_BUFFERS; - - txbd = (I2C_BD *)state->txbd; - txbd->addr = state->tx_buf; - - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); - - if (flags & I2CF_START_COND) - { - PRINTD(("[I2C] Formatting addresses...\n")); - if (flags & I2CF_ENABLE_SECONDARY) - { - txbd->length = size + 2; /* Length of message plus dest addresses */ - txbd->addr[0] = address << 1; - txbd->addr[1] = secondary_address; - i = 2; - } - else - { - txbd->length = size + 1; /* Length of message plus dest address */ - txbd->addr[0] = address << 1; /* Write destination address to BD */ - i = 1; - } - } - else - { - txbd->length = size; /* Length of message */ - i = 0; - } - - /* set up txbd */ - txbd->status = BD_SC_READY; - if (flags & I2CF_START_COND) - txbd->status |= BD_I2C_TX_START; - if (flags & I2CF_STOP_COND) - txbd->status |= BD_SC_LAST | BD_SC_WRAP; - - /* Copy data to send into buffer */ - PRINTD(("[I2C] copy data...\n")); - for(j = 0; j < size; i++, j++) - txbd->addr[i] = dataout[j]; - - PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, - txbd->status, - txbd->addr[0], - txbd->addr[1])); - - /* advance state */ - state->tx_buf += txbd->length; - state->tx_space -= txbd->length; - state->tx_idx++; - state->txbd = (void*)(txbd + 1); - - return 0; -} - -static -int i2c_receive(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, - unsigned short size_to_expect, - unsigned char *datain) -{ - volatile I2C_BD *rxbd, *txbd; - - PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags)); - - /* Expected to receive too much */ - if (size_to_expect > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; - - /* no more free bds */ - if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS - || state->tx_space < 2) - return I2CERR_NO_BUFFERS; - - rxbd = (I2C_BD *)state->rxbd; - txbd = (I2C_BD *)state->txbd; - - PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); - - txbd->addr = state->tx_buf; - - /* set up TXBD for destination address */ - if (flags & I2CF_ENABLE_SECONDARY) - { - txbd->length = 2; - txbd->addr[0] = address << 1; /* Write data */ - txbd->addr[1] = secondary_address; /* Internal address */ - txbd->status = BD_SC_READY; - } - else - { - txbd->length = 1 + size_to_expect; - txbd->addr[0] = (address << 1) | 0x01; - txbd->status = BD_SC_READY; - memset(&txbd->addr[1], 0, txbd->length); - } - - /* set up rxbd for reception */ - rxbd->status = BD_SC_EMPTY; - rxbd->length = size_to_expect; - rxbd->addr = datain; - - txbd->status |= BD_I2C_TX_START; - if (flags & I2CF_STOP_COND) - { - txbd->status |= BD_SC_LAST | BD_SC_WRAP; - rxbd->status |= BD_SC_WRAP; - } - - PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, - txbd->status, - txbd->addr[0], - txbd->addr[1])); - PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - rxbd->length, - rxbd->status, - rxbd->addr[0], - rxbd->addr[1])); - - /* advance state */ - state->tx_buf += txbd->length; - state->tx_space -= txbd->length; - state->tx_idx++; - state->txbd = (void*)(txbd + 1); - state->rx_idx++; - state->rxbd = (void*)(rxbd + 1); - - return 0; -} - - -static -int i2c_doio(i2c_state_t *state) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR ; - volatile iic_t *iip; - volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; - volatile I2C_BD *txbd, *rxbd; - int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0; - uint dpaddr; - - PRINTD(("[I2C] i2c_doio\n")); - - if (state->tx_idx <= 0 && state->rx_idx <= 0) { - PRINTD(("[I2C] No I/O is queued\n")); - return I2CERR_QUEUE_EMPTY; - } - - dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])); - iip = (iic_t *)&immap->im_dprambase[dpaddr]; - iip->iic_rbptr = iip->iic_rbase; - iip->iic_tbptr = iip->iic_tbase; - - /* Enable I2C */ - PRINTD(("[I2C] Enabling I2C...\n")); - i2c->i2c_i2mod |= 0x01; - - /* Begin transmission */ - i2c->i2c_i2com |= 0x80; - - /* Loop until transmit & receive completed */ - - if ((n = state->tx_idx) > 0) { - - txbd = ((I2C_BD*)state->txbd) - n; - for (i = 0; i < n; i++) { - txtimeo += TOUT_LOOP * txbd->length; - txbd++; - } - - txbd--; /* wait until last in list is done */ - - PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd)); - - udelay(START_DELAY_US); /* give it time to start */ - while((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) { - udelay(DELAY_US); - if (ctrlc()) - return (-1); - __asm__ __volatile__ ("eieio"); - } - } - - if (txcnt < txtimeo && (n = state->rx_idx) > 0) { - - rxbd = ((I2C_BD*)state->rxbd) - n; - for (i = 0; i < n; i++) { - rxtimeo += TOUT_LOOP * rxbd->length; - rxbd++; - } - - rxbd--; /* wait until last in list is done */ - - PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd)); - - udelay(START_DELAY_US); /* give it time to start */ - while((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) { - udelay(DELAY_US); - if (ctrlc()) - return (-1); - __asm__ __volatile__ ("eieio"); - } - } - - /* Turn off I2C */ - i2c->i2c_i2mod &= ~0x01; - - if ((n = state->tx_idx) > 0) { - for (i = 0; i < n; i++) { - txbd = ((I2C_BD*)state->txbd) - (n - i); - if ((b = txbd->status & BD_I2C_TX_ERR) != 0) { - if (state->err_cb != NULL) - (*state->err_cb)(I2CECB_TX_ERR|b, i, - state->cb_data); - if (rc == 0) - rc = I2CERR_IO_ERROR; - } - } - } - - if ((n = state->rx_idx) > 0) { - for (i = 0; i < n; i++) { - rxbd = ((I2C_BD*)state->rxbd) - (n - i); - if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) { - if (state->err_cb != NULL) - (*state->err_cb)(I2CECB_RX_ERR|b, i, - state->cb_data); - if (rc == 0) - rc = I2CERR_IO_ERROR; - } - } - } - - if ((txtimeo > 0 && txcnt >= txtimeo) || \ - (rxtimeo > 0 && rxcnt >= rxtimeo)) { - if (state->err_cb != NULL) - (*state->err_cb)(I2CECB_TIMEOUT, -1, state->cb_data); - if (rc == 0) - rc = I2CERR_TIMEOUT; - } - - return (rc); -} - -static void -i2c_probe_callback(int flags, int xnum, void *data) -{ - /* - * the only acceptable errors are a transmit NAK or a receive - * overrun - tx NAK means the device does not exist, rx OV - * means the device must have responded to the slave address - * even though the transfer failed - */ - if (flags == (I2CECB_TX_ERR|I2CECB_TX_NAK)) - *(int *)data |= 1; - if (flags == (I2CECB_RX_ERR|I2CECB_RX_OV)) - *(int *)data |= 2; -} - -int -i2c_probe(uchar chip) -{ - i2c_state_t state; - int rc, err_flag; - uchar buf[1]; - - i2c_newio(&state); - - state.err_cb = i2c_probe_callback; - state.cb_data = (void *) &err_flag; - err_flag = 0; - - rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf); - - if (rc != 0) - return (rc); /* probe failed */ - - rc = i2c_doio(&state); - - if (rc == 0) - return (0); /* device exists - read succeeded */ - - if (rc == I2CERR_TIMEOUT) - return (-1); /* device does not exist - timeout */ - - if (rc != I2CERR_IO_ERROR || err_flag == 0) - return (rc); /* probe failed */ - - if (err_flag & 1) - return (-1); /* device does not exist - had transmit NAK */ - - return (0); /* device exists - had receive overrun */ -} - - -int -i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - i2c_state_t state; - uchar xaddr[4]; - int rc; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address - * and the extra bits end up in the "chip address" bit slots. - * This makes a 24WC08 (1Kbyte) chip look like four 256 byte - * chips. - * - * Note that we consider the length of the address field to still - * be one byte because the extra address bits are hidden in the - * chip address. - */ - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); -#endif - - i2c_newio(&state); - - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); - if (rc != 0) { - printf("i2c_read: i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer); - if (rc != 0) { - printf("i2c_read: i2c_receive failed (%d)\n", rc); - return 1; - } - - rc = i2c_doio(&state); - if (rc != 0) { - printf("i2c_read: i2c_doio failed (%d)\n", rc); - return 1; - } - return 0; -} - -int -i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - i2c_state_t state; - uchar xaddr[4]; - int rc; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address - * and the extra bits end up in the "chip address" bit slots. - * This makes a 24WC08 (1Kbyte) chip look like four 256 byte - * chips. - * - * Note that we consider the length of the address field to still - * be one byte because the extra address bits are hidden in the - * chip address. - */ - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); -#endif - - i2c_newio(&state); - - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); - if (rc != 0) { - printf("i2c_write: first i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer); - if (rc != 0) { - printf("i2c_write: second i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_doio(&state); - if (rc != 0) { - printf("i2c_write: i2c_doio failed (%d)\n", rc); - return 1; - } - return 0; -} - -uchar -i2c_reg_read(uchar chip, uchar reg) -{ - uchar buf; - - i2c_read(chip, reg, 1, &buf, 1); - - return (buf); -} - -void -i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - i2c_write(chip, reg, 1, &val, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8260/interrupts.c b/cpu/mpc8260/interrupts.c deleted file mode 100644 index b2e4d83..0000000 --- a/cpu/mpc8260/interrupts.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00 - */ - -#include -#include -#include -#include -#include - -/****************************************************************************/ - -struct irq_action { - interrupt_handler_t *handler; - void *arg; - ulong count; -}; - -static struct irq_action irq_handlers[NR_IRQS]; - -static ulong ppc_cached_irq_mask[NR_MASK_WORDS]; - -/****************************************************************************/ -/* this section was ripped out of arch/ppc/kernel/ppc8260_pic.c in the */ -/* Linux/PPC 2.4.x source. There was no copyright notice in that file. */ - -/* The 8260 internal interrupt controller. It is usually - * the only interrupt controller. - * There are two 32-bit registers (high/low) for up to 64 - * possible interrupts. - * - * Now, the fun starts.....Interrupt Numbers DO NOT MAP - * in a simple arithmetic fashion to mask or pending registers. - * That is, interrupt 4 does not map to bit position 4. - * We create two tables, indexed by vector number, to indicate - * which register to use and which bit in the register to use. - */ -static u_char irq_to_siureg[] = { - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u_char irq_to_siubit[] = { - 31, 16, 17, 18, 19, 20, 21, 22, - 23, 24, 25, 26, 27, 28, 29, 30, - 29, 30, 16, 17, 18, 19, 20, 21, - 22, 23, 24, 25, 26, 27, 28, 31, - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 15, 14, 13, 12, 11, 10, 9, 8, - 7, 6, 5, 4, 3, 2, 1, 0 -}; - -static void m8260_mask_irq (unsigned int irq_nr) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - int bit, word; - volatile uint *simr; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(immr->im_intctl.ic_simrh); - ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); - simr[word] = ppc_cached_irq_mask[word]; -} - -static void m8260_unmask_irq (unsigned int irq_nr) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - int bit, word; - volatile uint *simr; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(immr->im_intctl.ic_simrh); - ppc_cached_irq_mask[word] |= (1 << (31 - bit)); - simr[word] = ppc_cached_irq_mask[word]; -} - -static void m8260_mask_and_ack (unsigned int irq_nr) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - int bit, word; - volatile uint *simr, *sipnr; - - bit = irq_to_siubit[irq_nr]; - word = irq_to_siureg[irq_nr]; - - simr = &(immr->im_intctl.ic_simrh); - sipnr = &(immr->im_intctl.ic_sipnrh); - ppc_cached_irq_mask[word] &= ~(1 << (31 - bit)); - simr[word] = ppc_cached_irq_mask[word]; - sipnr[word] = 1 << (31 - bit); -} - -static int m8260_get_irq (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - int irq; - unsigned long bits; - - /* For MPC8260, read the SIVEC register and shift the bits down - * to get the irq number. */ - bits = immr->im_intctl.ic_sivec; - irq = bits >> 26; - return irq; -} - -/* end of code ripped out of arch/ppc/kernel/ppc8260_pic.c */ -/****************************************************************************/ - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - *decrementer_count = (gd->bus_clk / 4) / CFG_HZ; - - /* Initialize the default interrupt mapping priorities */ - immr->im_intctl.ic_sicr = 0; - immr->im_intctl.ic_siprr = 0x05309770; - immr->im_intctl.ic_scprrh = 0x05309770; - immr->im_intctl.ic_scprrl = 0x05309770; - - /* disable all interrupts and clear all pending bits */ - immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0; - immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0; - immr->im_intctl.ic_sipnrh = 0xffffffff; - immr->im_intctl.ic_sipnrl = 0xffffffff; - -#ifdef CONFIG_HYMOD - /* - * ensure all external interrupt sources default to trigger on - * high-to-low transition (i.e. edge triggered active low) - */ - immr->im_intctl.ic_siexr = -1; -#endif - - return (0); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt (struct pt_regs *regs) -{ - int irq, unmask = 1; - - irq = m8260_get_irq (regs); - - m8260_mask_and_ack (irq); - - enable_interrupts (); - - if (irq_handlers[irq].handler != NULL) - (*irq_handlers[irq].handler) (irq_handlers[irq].arg); - else { - printf ("\nBogus External Interrupt IRQ %d\n", irq); - /* - * turn off the bogus interrupt, otherwise it - * might repeat forever - */ - unmask = 0; - } - - if (unmask) - m8260_unmask_irq (irq); -} - -/****************************************************************************/ - -/* - * Install and free an interrupt handler. - */ - -void -irq_install_handler (int irq, interrupt_handler_t * handler, void *arg) -{ - if (irq < 0 || irq >= NR_IRQS) { - printf ("irq_install_handler: bad irq number %d\n", irq); - return; - } - - if (irq_handlers[irq].handler != NULL) - printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n", - (ulong) handler, (ulong) irq_handlers[irq].handler); - - irq_handlers[irq].handler = handler; - irq_handlers[irq].arg = arg; - - m8260_unmask_irq (irq); -} - -void irq_free_handler (int irq) -{ - if (irq < 0 || irq >= NR_IRQS) { - printf ("irq_free_handler: bad irq number %d\n", irq); - return; - } - - m8260_mask_irq (irq); - - irq_handlers[irq].handler = NULL; - irq_handlers[irq].arg = NULL; -} - -/****************************************************************************/ - -void timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} - -/****************************************************************************/ - -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) - -/* ripped this out of ppc4xx/interrupts.c */ - -/******************************************************************************* -* -* irqinfo - print information about PCI devices -* -*/ -void -do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) -{ - int irq, re_enable; - - re_enable = disable_interrupts (); - - puts ("\nInterrupt-Information:\n" - "Nr Routine Arg Count\n"); - - for (irq = 0; irq < 32; irq++) - if (irq_handlers[irq].handler != NULL) - printf ("%02d %08lx %08lx %ld\n", irq, - (ulong) irq_handlers[irq].handler, - (ulong) irq_handlers[irq].arg, - irq_handlers[irq].count); - - if (re_enable) - enable_interrupts (); -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/mpc8260/kgdb.S b/cpu/mpc8260/kgdb.S deleted file mode 100644 index 2a25024..0000000 --- a/cpu/mpc8260/kgdb.S +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2000 Murray Jensen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - - /* - * cache flushing routines for kgdb - */ - - .globl kgdb_flush_cache_all -kgdb_flush_cache_all: - mfspr r3, HID0 - ori r3, r3, HID0_ICFI|HID0_DCI /* Invalidate All */ - SYNC - mtspr HID0, r3 - blr - - .globl kgdb_flush_cache_range -kgdb_flush_cache_range: - li r5,CFG_CACHELINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,CFG_CACHELINE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CFG_CACHELINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CFG_CACHELINE_SIZE - bdnz 2b - SYNC - blr - -#endif /* CFG_CMD_KGDB */ diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c deleted file mode 100644 index 44576de..0000000 --- a/cpu/mpc8260/pci.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (c) 2005 MontaVista Software, Inc. - * Vitaly Bordug - * Added support for PCI bridge on MPC8272ADS - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifdef CONFIG_PCI - -#include -#include -#include -#include -/* - * Local->PCI map (from CPU) controlled by - * MPC826x master window - * - * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0 - * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1 - * - * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1) - * PCI Mem with prefetch - * - * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2) - * PCI Mem w/o prefetch - * - * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3) - * 32-bit PCI IO - * - * PCI->Local map (from PCI) - * MPC826x slave window controlled by - * - * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1) - * MPC826x local memory - */ - -/* - * Slave window that allows PCI masters to access MPC826x local memory. - * This window is set up using the first set of Inbound ATU registers - */ - -#ifndef CFG_PCI_SLV_MEM_LOCAL -#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ -#else -#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL -#endif - -#ifndef CFG_PCI_SLV_MEM_BUS -#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ -#else -#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS -#endif - -#ifndef CFG_PICMR0_MASK_ATTRIB -#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ - PICMR_PREFETCH_EN) -#else -#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB -#endif - -/* - * These are the windows that allow the CPU to access PCI address space. - * All three PCI master windows, which allow the CPU to access PCI - * prefetch, non prefetch, and IO space (see below), must all fit within - * these windows. - */ - -/* PCIBR0 */ -#ifndef CFG_PCI_MSTR0_LOCAL -#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ -#else -#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL -#endif - -#ifndef CFG_PCIMSK0_MASK -#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ -#else -#define PCIMSK0_MASK CFG_PCIMSK0_MASK -#endif - -/* PCIBR1 */ -#ifndef CFG_PCI_MSTR1_LOCAL -#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ -#else -#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL -#endif - -#ifndef CFG_PCIMSK1_MASK -#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ -#else -#define PCIMSK1_MASK CFG_PCIMSK1_MASK -#endif - -/* - * Master window that allows the CPU to access PCI Memory (prefetch). - * This window will be setup with the first set of Outbound ATU registers - * in the bridge. - */ - -#ifndef CFG_PCI_MSTR_MEM_LOCAL -#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#else -#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL -#endif - -#ifndef CFG_PCI_MSTR_MEM_BUS -#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#else -#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS -#endif - -#ifndef CFG_CPU_PCI_MEM_START -#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#else -#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START -#endif - -#ifndef CFG_PCI_MSTR_MEM_SIZE -#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ -#else -#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE -#endif - -#ifndef CFG_POCMR0_MASK_ATTRIB -#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN) -#else -#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB -#endif - -/* - * Master window that allows the CPU to access PCI Memory (non-prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#ifndef CFG_PCI_MSTR_MEMIO_LOCAL -#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ -#else -#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL -#endif - -#ifndef CFG_PCI_MSTR_MEMIO_BUS -#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ -#else -#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS -#endif - -#ifndef CFG_CPU_PCI_MEMIO_START -#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#else -#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START -#endif - -#ifndef CFG_PCI_MSTR_MEMIO_SIZE -#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ -#else -#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE -#endif - -#ifndef CFG_POCMR1_MASK_ATTRIB -#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) -#else -#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB -#endif - -/* - * Master window that allows the CPU to access PCI IO space. - * This window will be setup with the third set of Outbound ATU registers - * in the bridge. - */ - -#ifndef CFG_PCI_MSTR_IO_LOCAL -#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ -#else -#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL -#endif - -#ifndef CFG_PCI_MSTR_IO_BUS -#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ -#else -#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS -#endif - -#ifndef CFG_CPU_PCI_IO_START -#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#else -#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START -#endif - -#ifndef CFG_PCI_MSTR_IO_SIZE -#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ -#else -#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE -#endif - -#ifndef CFG_POCMR2_MASK_ATTRIB -#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) -#else -#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB -#endif - -/* PCI bus configuration registers. - */ - -#define PCI_CLASS_BRIDGE_CTLR 0x06 - - -static inline void pci_outl (u32 addr, u32 data) -{ - *(volatile u32 *) addr = cpu_to_le32 (data); -} - -void pci_mpc8250_init (struct pci_controller *hose) -{ -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 - DECLARE_GLOBAL_DATA_PTR; -#endif - u16 tempShort; - - volatile immap_t *immap = (immap_t *) CFG_IMMR; - pci_dev_t host_devno = PCI_BDF (0, 0, 0); - - pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG, - CFG_IMMR + PCI_CFG_DATA_REG); - - /* - * Setting required to enable local bus for PCI (SIUMCR [LBPC]). - */ -#ifdef CONFIG_MPC8266ADS - immap->im_siu_conf.sc_siumcr = - (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) - | SIUMCR_LBPC01; -#elif defined CONFIG_MPC8272 - immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & - ~SIUMCR_BBD & - ~SIUMCR_ESE & - ~SIUMCR_PBSE & - ~SIUMCR_CDIS & - ~SIUMCR_DPPC11 & - ~SIUMCR_L2CPC11 & - ~SIUMCR_LBPC11 & - ~SIUMCR_APPC11 & - ~SIUMCR_CS10PC11 & - ~SIUMCR_BCTLC11 & - ~SIUMCR_MMR11) - | SIUMCR_DPPC11 - | SIUMCR_L2CPC01 - | SIUMCR_LBPC00 - | SIUMCR_APPC10 - | SIUMCR_CS10PC00 - | SIUMCR_BCTLC00 - | SIUMCR_MMR11; - -#else - /* - * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), - * and local bus for PCI (SIUMCR [LBPC]). - */ - immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & - ~SIUMCR_LBPC11 & - ~SIUMCR_CS10PC11 & - ~SIUMCR_LBPC11) | - SIUMCR_LBPC01 | - SIUMCR_CS10PC01 | - SIUMCR_APPC10; -#endif - - /* Make PCI lowest priority */ - /* Each 4 bits is a device bus request and the MS 4bits - is highest priority */ - /* Bus 4bit value - --- ---------- - CPM high 0b0000 - CPM middle 0b0001 - CPM low 0b0010 - PCI reguest 0b0011 - Reserved 0b0100 - Reserved 0b0101 - Internal Core 0b0110 - External Master 1 0b0111 - External Master 2 0b1000 - External Master 3 0b1001 - The rest are reserved */ - immap->im_siu_conf.sc_ppc_alrh = 0x61207893; - - /* Park bus on core while modifying PCI Bus accesses */ - immap->im_siu_conf.sc_ppc_acr = 0x6; - - /* - * Set up master windows that allow the CPU to access PCI space. These - * windows are set up using the two SIU PCIBR registers. - */ - immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK; - immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE; - -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 - immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK; - immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE; -#endif - - /* Release PCI RST (by default the PCI RST signal is held low) */ - immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN); - - /* give it some time */ - { -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 - /* Give the PCI cards more time to initialize before query - This might be good for other boards also - */ - int i; - - for (i = 0; i < 1000; ++i) -#endif - udelay (1000); - } - - /* - * Set up master window that allows the CPU to access PCI Memory (prefetch) - * space. This window is set up using the first set of Outbound ATU registers. - */ - immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */ - immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */ - immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up master window that allows the CPU to access PCI Memory (non-prefetch) - * space. This window is set up using the second set of Outbound ATU registers. - */ - immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */ - immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */ - immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up master window that allows the CPU to access PCI IO space. This window - * is set up using the third set of Outbound ATU registers. - */ - immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */ - immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */ - immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */ - - /* - * Set up slave window that allows PCI masters to access MPC826x local memory. - * This window is set up using the first set of Inbound ATU registers - */ - immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */ - immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */ - immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */ - - /* See above for description - puts PCI request as highest priority */ -#ifdef CONFIG_MPC8272 - immap->im_siu_conf.sc_ppc_alrh = 0x01236745; -#else - immap->im_siu_conf.sc_ppc_alrh = 0x03124567; -#endif - - /* Park the bus on the PCI */ - immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; - - /* Host mode - specify the bridge as a host-PCI bridge */ - - pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE, - PCI_CLASS_BRIDGE_CTLR); - - /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */ - pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort); - pci_hose_write_config_word (hose, host_devno, PCI_COMMAND, - tempShort | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); - - /* do some bridge init, should be done on all 8260 based bridges */ - pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE, - 0x08); - pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER, - 0xF8); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 - pci_set_region (hose->regions + 0, - PCI_SLV_MEM_BUS, - PCI_SLV_MEM_LOCAL, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); -#else - pci_set_region (hose->regions + 0, - CFG_SDRAM_BASE, - CFG_SDRAM_BASE, - 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY); -#endif - - /* PCI memory space */ -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 - pci_set_region (hose->regions + 1, - PCI_MSTR_MEMIO_BUS, - PCI_MSTR_MEMIO_LOCAL, - PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM); -#else - pci_set_region (hose->regions + 1, - PCI_MSTR_MEM_BUS, - PCI_MSTR_MEM_LOCAL, - PCI_MSTR_MEM_SIZE, PCI_REGION_MEM); -#endif - - /* PCI I/O space */ - pci_set_region (hose->regions + 2, - PCI_MSTR_IO_BUS, - PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose (hose); - /* Mask off master abort machine checks */ - immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP); - eieio (); - - hose->last_busno = pci_hose_scan (hose); - - - /* clear the error in the error status register */ - immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); - - /* unmask master abort machine checks */ - immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); -} - -#endif /* CONFIG_PCI */ diff --git a/cpu/mpc8260/serial_scc.c b/cpu/mpc8260/serial_scc.c deleted file mode 100644 index 32016f2..0000000 --- a/cpu/mpc8260/serial_scc.c +++ /dev/null @@ -1,498 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00. - */ - -/* - * Minimal serial functions needed to use one of the SCC ports - * as serial console interface. - */ - -#include -#include -#include - -#if defined(CONFIG_CONS_ON_SCC) - -#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ - -#define SCC_INDEX 0 -#define PROFF_SCC PROFF_SCC1 -#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ - CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) -#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK - -#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */ - -#define SCC_INDEX 1 -#define PROFF_SCC PROFF_SCC2 -#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ - CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) -#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK - -#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */ - -#define SCC_INDEX 2 -#define PROFF_SCC PROFF_SCC3 -#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ - CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) -#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK - -#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */ - -#define SCC_INDEX 3 -#define PROFF_SCC PROFF_SCC4 -#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ - CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) -#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK - -#else - -#error "console not correctly defined" - -#endif - -int serial_init (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SCC */ - - sp = (scc_t *) &(im->im_scc[SCC_INDEX]); - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - - /* Disable transmitter/receiver. - */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* put the SCC channel into NMSI (non multiplexd serial interface) - * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). - */ - im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr&~CMXSCR_MASK)|CMXSCR_VALUE; - - /* Set up the baud rate generator. - */ - serial_setbrg (); - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = BD_SC_WRAP; - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - up->scc_genscc.scc_rfcr = CPMFCR_EB; - up->scc_genscc.scc_tfcr = CPMFCR_EB; - up->scc_genscc.scc_mrblr = 1; - up->scc_maxidl = 0; - up->scc_brkcr = 1; - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; - up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Mask all interrupts and remove anything pending. - */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - - /* Set 8 bit FIFO, 16 bit oversampling and UART mode. - */ - sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ - sp->scc_gsmrl = \ - SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; - - /* Set CTS flow control, 1 stop bit, 8 bit character length, - * normal async UART mode, no parity - */ - sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL; - - /* execute the "Init Rx and Tx params" CP command. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; - - return (0); -} - -void -serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CONS_USE_EXTC) - m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate, - CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); -#else - m8260_cpm_setbrg(SCC_INDEX, gd->baudrate); -#endif -} - -void -serial_putc(const char c) -{ - volatile scc_uart_t *up; - volatile cbd_t *tbdf; - volatile immap_t *im; - - if (c == '\n') - serial_putc ('\r'); - - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. - */ - while (tbdf->cbd_sc & BD_SC_READY) - ; - - /* Load the character into the transmit buffer. - */ - *(volatile char *)tbdf->cbd_bufaddr = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int -serial_getc(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im; - unsigned char c; - - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. - */ - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - - /* Grab the char and clear the buffer again. - */ - c = *(volatile unsigned char *)rbdf->cbd_bufaddr; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - -int -serial_tstc() -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im; - - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; - rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; - - return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); -} - -#endif /* CONFIG_CONS_ON_SCC */ - -#if defined(CONFIG_KGDB_ON_SCC) - -#if defined(CONFIG_CONS_ON_SCC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX -#error Whoops! serial console and kgdb are on the same scc serial port -#endif - -#if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SCC1 */ - -#define KGDB_SCC_INDEX 0 -#define KGDB_PROFF_SCC PROFF_SCC1 -#define KGDB_CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ - CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK - -#elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SCC2 */ - -#define KGDB_SCC_INDEX 1 -#define KGDB_PROFF_SCC PROFF_SCC2 -#define KGDB_CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ - CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK - -#elif CONFIG_KGDB_INDEX == 3 /* KGDB Port on SCC3 */ - -#define KGDB_SCC_INDEX 2 -#define KGDB_PROFF_SCC PROFF_SCC3 -#define KGDB_CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ - CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK - -#elif CONFIG_KGDB_INDEX == 4 /* KGDB Port on SCC4 */ - -#define KGDB_SCC_INDEX 3 -#define KGDB_PROFF_SCC PROFF_SCC4 -#define KGDB_CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ - CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) -#define KGDB_CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) -#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE -#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK - -#else - -#error "kgdb serial port not correctly defined" - -#endif - -void -kgdb_serial_init (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr, speed = CONFIG_KGDB_BAUDRATE; - char *s, *e; - - if ((s = getenv("kgdbrate")) != NULL && *s != '\0') { - ulong rate = simple_strtoul(s, &e, 10); - if (e > s && *e == '\0') - speed = rate; - } - - /* initialize pointers to SCC */ - - sp = (scc_t *) &(im->im_scc[KGDB_SCC_INDEX]); - up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; - - /* Disable transmitter/receiver. - */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* put the SCC channel into NMSI (non multiplexd serial interface) - * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). - */ - im->im_cpmux.cmx_scr = \ - (im->im_cpmux.cmx_scr & ~KGDB_CMXSCR_MASK) | KGDB_CMXSCR_VALUE; - - /* Set up the baud rate generator. - */ -#if defined(CONFIG_KGDB_USE_EXTC) - m8260_cpm_extcbrg(KGDB_SCC_INDEX, speed, - CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL); -#else - m8260_cpm_setbrg(KGDB_SCC_INDEX, speed); -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = BD_SC_WRAP; - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - up->scc_genscc.scc_rfcr = CPMFCR_EB; - up->scc_genscc.scc_tfcr = CPMFCR_EB; - up->scc_genscc.scc_mrblr = 1; - up->scc_maxidl = 0; - up->scc_brkcr = 1; - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; - up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Mask all interrupts and remove anything pending. - */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - - /* Set 8 bit FIFO, 16 bit oversampling and UART mode. - */ - sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ - sp->scc_gsmrl = \ - SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; - - /* Set CTS flow control, 1 stop bit, 8 bit character length, - * normal async UART mode, no parity - */ - sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL; - - /* execute the "Init Rx and Tx params" CP command. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SCC_PAGE, KGDB_CPM_CR_SCC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; - - printf("SCC%d at %dbps ", CONFIG_KGDB_INDEX, speed); -} - -void -putDebugChar(const char c) -{ - volatile scc_uart_t *up; - volatile cbd_t *tbdf; - volatile immap_t *im; - - if (c == '\n') - putDebugChar ('\r'); - - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; - tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. - */ - while (tbdf->cbd_sc & BD_SC_READY) - ; - - /* Load the character into the transmit buffer. - */ - *(volatile char *)tbdf->cbd_bufaddr = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -void -putDebugStr (const char *s) -{ - while (*s) { - putDebugChar (*s++); - } -} - -int -getDebugChar(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im; - unsigned char c; - - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; - rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. - */ - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - - /* Grab the char and clear the buffer again. - */ - c = *(volatile unsigned char *)rbdf->cbd_bufaddr; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - -void -kgdb_interruptible(int yes) -{ - return; -} - -#endif /* CONFIG_KGDB_ON_SCC */ diff --git a/cpu/mpc8260/serial_smc.c b/cpu/mpc8260/serial_smc.c deleted file mode 100644 index b486f83..0000000 --- a/cpu/mpc8260/serial_smc.c +++ /dev/null @@ -1,462 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with - * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the - * Linux/PPC sources (m8260_tty.c had no copyright info in it). - */ - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -#include -#include -#include - -#if defined(CONFIG_CONS_ON_SMC) - -#if CONFIG_CONS_INDEX == 1 /* Console on SMC1 */ - -#define SMC_INDEX 0 -#define PROFF_SMC_BASE PROFF_SMC1_BASE -#define PROFF_SMC PROFF_SMC1 -#define CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE -#define CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK -#define CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK) -#define CMXSMR_VALUE CMXSMR_SMC1CS_BRG7 - -#elif CONFIG_CONS_INDEX == 2 /* Console on SMC2 */ - -#define SMC_INDEX 1 -#define PROFF_SMC_BASE PROFF_SMC2_BASE -#define PROFF_SMC PROFF_SMC2 -#define CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE -#define CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK -#define CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK) -#define CMXSMR_VALUE CMXSMR_SMC2CS_BRG8 - -#else - -#error "console not correctly defined" - -#endif - -/* map rs_table index to baud rate generator index */ -static unsigned char brg_map[] = { - 6, /* BRG7 for SMC1 */ - 7, /* BRG8 for SMC2 */ - 0, /* BRG1 for SCC1 */ - 1, /* BRG1 for SCC2 */ - 2, /* BRG1 for SCC3 */ - 3, /* BRG1 for SCC4 */ -}; - -int serial_init (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(im->im_smc[SMC_INDEX]); - *(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC; - up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = CPMFCR_EB; - up->smc_tfcr = CPMFCR_EB; - up->smc_brklen = 0; - up->smc_brkec = 0; - up->smc_brkcr = 0; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* put the SMC channel into NMSI (non multiplexd serial interface) - * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17). - */ - im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE; - - /* Set up the baud rate generator. - */ - serial_setbrg (); - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - return (0); -} - -void -serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CONS_USE_EXTC) - m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate, - CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); -#else - m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate); -#endif -} - -void -serial_putc(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - - if (c == '\n') - serial_putc ('\r'); - - up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); - - tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase]; - - /* Wait for last character to go. - */ - buf = (char *)tbdf->cbd_bufaddr; - while (tbdf->cbd_sc & BD_SC_READY) - ; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int -serial_getc(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - unsigned char c; - - up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); - - rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -int -serial_tstc() -{ - volatile cbd_t *rbdf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - - up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); - - rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} - -#endif /* CONFIG_CONS_ON_SMC */ - -#if defined(CONFIG_KGDB_ON_SMC) - -#if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX -#error Whoops! serial console and kgdb are on the same smc serial port -#endif - -#if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SMC1 */ - -#define KGDB_SMC_INDEX 0 -#define KGDB_PROFF_SMC_BASE PROFF_SMC1_BASE -#define KGDB_PROFF_SMC PROFF_SMC1 -#define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE -#define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK -#define KGDB_CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK) -#define KGDB_CMXSMR_VALUE CMXSMR_SMC1CS_BRG7 - -#elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SMC2 */ - -#define KGDB_SMC_INDEX 1 -#define KGDB_PROFF_SMC_BASE PROFF_SMC2_BASE -#define KGDB_PROFF_SMC PROFF_SMC2 -#define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE -#define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK -#define KGDB_CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK) -#define KGDB_CMXSMR_VALUE CMXSMR_SMC2CS_BRG8 - -#else - -#error "console not correctly defined" - -#endif - -void -kgdb_serial_init (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8260_t *cp = &(im->im_cpm); - uint dpaddr, speed = CONFIG_KGDB_BAUDRATE; - char *s, *e; - - if ((s = getenv("kgdbrate")) != NULL && *s != '\0') { - ulong rate = simple_strtoul(s, &e, 10); - if (e > s && *e == '\0') - speed = rate; - } - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]); - *(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC; - up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = CPMFCR_EB; - up->smc_tfcr = CPMFCR_EB; - up->smc_brklen = 0; - up->smc_brkec = 0; - up->smc_brkcr = 0; - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* put the SMC channel into NMSI (non multiplexd serial interface) - * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17). - */ - im->im_cpmux.cmx_smr = - (im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE; - - /* Set up the baud rate generator. - */ -#if defined(CONFIG_KGDB_USE_EXTC) - m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed, - CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL); -#else - m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed); -#endif - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed); -} - -void -putDebugChar(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - - if (c == '\n') - putDebugChar ('\r'); - - up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]); - - tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase]; - - /* Wait for last character to go. - */ - buf = (char *)tbdf->cbd_bufaddr; - while (tbdf->cbd_sc & BD_SC_READY) - ; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -void -putDebugStr (const char *s) -{ - while (*s) { - putDebugChar (*s++); - } -} - -int -getDebugChar(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - unsigned char c; - - up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]); - - rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -void -kgdb_interruptible(int yes) -{ - return; -} - -#endif /* CONFIG_KGDB_ON_SMC */ diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c deleted file mode 100644 index a761a17..0000000 --- a/cpu/mpc8260/speed.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -/* Bus-to-Core Multiplier */ -#define _1x 2 -#define _1_5x 3 -#define _2x 4 -#define _2_5x 5 -#define _3x 6 -#define _3_5x 7 -#define _4x 8 -#define _4_5x 9 -#define _5x 10 -#define _5_5x 11 -#define _6x 12 -#define _6_5x 13 -#define _7x 14 -#define _7_5x 15 -#define _8x 16 -#define _byp -1 -#define _off -2 -#define _unk -3 - -typedef struct { - int b2c_mult; - int vco_div; - char *freq_60x; - char *freq_core; -} corecnf_t; - -/* - * this table based on "Errata to MPC8260 PowerQUICC II User's Manual", - * Rev. 1, 8/2000, page 10. - */ -corecnf_t corecnf_tab[] = { - { _1_5x, 4, " 33-100", " 33-100" }, /* 0x00 */ - { _1x, 4, " 50-150", " 50-150" }, /* 0x01 */ - { _1x, 8, " 25-75 ", " 25-75 " }, /* 0x02 */ - { _byp, -1, " ?-? ", " ?-? " }, /* 0x03 */ - { _2x, 2, " 50-150", "100-300" }, /* 0x04 */ - { _2x, 4, " 25-75 ", " 50-150" }, /* 0x05 */ - { _2_5x, 2, " 40-120", "100-240" }, /* 0x06 */ - { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x07 */ - { _3x, 2, " 33-100", "100-300" }, /* 0x08 */ - { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x09 */ - { _4x, 2, " 25-75 ", "100-300" }, /* 0x0A */ - { _5x, 2, " 20-60 ", "100-300" }, /* 0x0B */ - { _1_5x, 8, " 16-50 ", " 16-50 " }, /* 0x0C */ - { _6x, 2, " 16-50 ", "100-300" }, /* 0x0D */ - { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x0E */ - { _off, -1, " ?-? ", " ?-? " }, /* 0x0F */ - { _3x, 4, " 16-50 ", " 50-150" }, /* 0x10 */ - { _2_5x, 4, " 20-60 ", " 50-120" }, /* 0x11 */ - { _6_5x, 2, " 15-46 ", "100-300" }, /* 0x12 */ - { _byp, -1, " ?-? ", " ?-? " }, /* 0x13 */ - { _7x, 2, " 14-43 ", "100-300" }, /* 0x14 */ - { _2x, 4, " 25-75 ", " 50-150" }, /* 0x15 */ - { _7_5x, 2, " 13-40 ", "100-300" }, /* 0x16 */ - { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x17 */ - { _unk, -1, " ?-? ", " ?-? " }, /* 0x18 */ - { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x19 */ - { _4x, 2, " 25-75 ", "100-300" }, /* 0x1A */ - { _5x, 2, " 20-60 ", "100-300" }, /* 0x1B */ - { _8x, 2, " 12-38 ", "100-300" }, /* 0x1C */ - { _6x, 2, " 16-50 ", "100-300" }, /* 0x1D */ - { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x1E */ - { _off, -1, " ?-? ", " ?-? " }, /* 0x1F */ -}; - -/* ------------------------------------------------------------------------- */ - -/* - * - */ - -int get_clocks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immap = (immap_t *) CFG_IMMR; - ulong clkin; - ulong sccr, dfbrg; - ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf; - corecnf_t *cp; - -#if !defined(CONFIG_8260_CLKIN) -#error clock measuring not implemented yet - define CONFIG_8260_CLKIN -#else - clkin = CONFIG_8260_CLKIN; -#endif - - sccr = immap->im_clkrst.car_sccr; - dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; - - scmr = immap->im_clkrst.car_scmr; - corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; - cp = &corecnf_tab[corecnf]; - - busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; - cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; - - /* HiP7, HiP7 Rev01, HiP7 RevA */ - if ((get_pvr () == PVR_8260_HIP7) || - (get_pvr () == PVR_8260_HIP7R1) || - (get_pvr () == PVR_8260_HIP7RA)) { - pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT; - gd->vco_out = clkin * (pllmf + 1); - } else { /* HiP3, HiP4 */ - pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; - plldf = (scmr & SCMR_PLLDF) ? 1 : 0; - gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); - } -#if 0 - if (gd->vco_out / (busdf + 1) != clkin) { - /* aaarrrggghhh!!! */ - return (1); - } -#endif - - gd->cpm_clk = gd->vco_out / 2; - gd->bus_clk = clkin; - gd->scc_clk = gd->vco_out / 4; - gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); - - if (cp->b2c_mult > 0) { - gd->cpu_clk = (clkin * cp->b2c_mult) / 2; - } else { - gd->cpu_clk = clkin; - } - - return (0); -} - -int prt_8260_clks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immap = (immap_t *) CFG_IMMR; - ulong sccr, dfbrg; - ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf; - corecnf_t *cp; - - sccr = immap->im_clkrst.car_sccr; - dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; - - scmr = immap->im_clkrst.car_scmr; - corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; - busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; - cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; - plldf = (scmr & SCMR_PLLDF) ? 1 : 0; - pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; - - cp = &corecnf_tab[corecnf]; - - puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult "); - - switch (cp->b2c_mult) { - case _byp: - puts ("BYPASS"); - break; - - case _off: - puts ("OFF"); - break; - - case _unk: - puts ("UNKNOWN"); - break; - - default: - printf ("%d%sx", - cp->b2c_mult / 2, - (cp->b2c_mult % 2) ? ".5" : ""); - break; - } - - printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n", - cp->vco_div, cp->freq_60x, cp->freq_core); - - printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, " - "plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf, - pllmf); - - printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n", - gd->vco_out, gd->scc_clk, gd->brg_clk); - - printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n", - gd->cpu_clk, gd->cpm_clk, gd->bus_clk); - - if (sccr & SCCR_PCI_MODE) { - uint pci_div; - - pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) * - ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1); - - printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div); - } - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8260/speed.h b/cpu/mpc8260/speed.h deleted file mode 100644 index b66393b..0000000 --- a/cpu/mpc8260/speed.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*----------------------------------------------------------------------- - * Timer value for timer 2, ICLK = 10 - * - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 - * - * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock - * SPEED_TMR2_PS prescaler - */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ - -/*----------------------------------------------------------------------- - * Timer value for PIT - * - * PIT_TIME = SPEED_PITC / PITRTCLK - * PITRTCLK = 8192 - */ -#define SPEED_PITC (82 << 16) /* start counting from 82 */ - -/* - * The new value for PTA is calculated from - * - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) - * - * gclk CPU clock (not bus clock !) - * Trefresh Refresh cycle * 4 (four word bursts used) - * DFBRG For normal mode (no clock reduction) always 0 - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) - * NCS Number of SDRAM banks (chip selects) on this UPM. - */ diff --git a/cpu/mpc8260/spi.c b/cpu/mpc8260/spi.c deleted file mode 100644 index c1a607c..0000000 --- a/cpu/mpc8260/spi.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * , - * - * Copyright (c) 2001 Gerd Mennchen - * Copyright (c) 2001-2003 Wolfgang Denk, DENX Software Engineering, . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MPC8260 CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd@denx.de - * - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_SPI) - -/* Warning: - * You cannot enable DEBUG for early system initalization, i. e. when - * this driver is used to read environment parameters like "baudrate" - * from EEPROM which are used to initialize the serial port which is - * needed to print the debug messages... - */ -#undef DEBUG - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0x2000 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CFG_SPI_INIT_OFFSET -#define CFG_SPI_INIT_OFFSET 0x2000 -#endif - -#define CPM_SPI_BASE 0x100 - -#ifdef DEBUG - -#define DPRINT(a) printf a; -/* ----------------------------------------------- - * Helper functions to peek into tx and rx buffers - * ----------------------------------------------- */ -static const char * const hex_digit = "0123456789ABCDEF"; - -static char quickhex (int i) -{ - return hex_digit[i]; -} - -static void memdump (void *pv, int num) -{ - int i; - unsigned char *pc = (unsigned char *) pv; - - for (i = 0; i < num; i++) - printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); - printf ("\t"); - for (i = 0; i < num; i++) - printf ("%c", isprint (pc[i]) ? pc[i] : '.'); - printf ("\n"); -} -#else /* !DEBUG */ - -#define DPRINT(a) - -#endif /* DEBUG */ - -/* ------------------- - * Function prototypes - * ------------------- */ -void spi_init (void); - -ssize_t spi_read (uchar *, int, uchar *, int); -ssize_t spi_write (uchar *, int, uchar *, int); -ssize_t spi_xfer (size_t); - -/* ------------------- - * Variables - * ------------------- */ - -#define MAX_BUFFER 0x104 - -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase - [CFG_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase - [CFG_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f (void) -{ - unsigned int dpaddr; - - volatile spi_t *spi; - volatile immap_t *immr; - volatile cpm8260_t *cp; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CFG_IMMR; - cp = (cpm8260_t *) &immr->im_cpm; - - *(ushort *)(&immr->im_dprambase[PROFF_SPI_BASE]) = PROFF_SPI; - spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; - -/* 1 */ - /* ------------------------------------------------ - * Initialize Port D SPI pins - * (we are only in Master Mode !) - * ------------------------------------------------ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PPARD[16] = 1 [0x00008000] (SPIMISO) - * PPARD[17] = 1 [0x00004000] (SPIMOSI) - * PPARD[18] = 1 [0x00002000] (SPICLK) - * PPARD[12] = 0 [0x00080000] -> GPIO: (CS for ATC EEPROM) - * -------------------------------------------- */ - immr->im_ioport.iop_ppard |= 0x0000E000; /* set bits */ - immr->im_ioport.iop_ppard &= ~0x00080000; /* reset bit */ - - /* ---------------------------------------------- - * In/Out or per. Function 0/1 - * PDIRD[16] = 0 [0x00008000] -> PERI1: SPIMISO - * PDIRD[17] = 0 [0x00004000] -> PERI1: SPIMOSI - * PDIRD[18] = 0 [0x00002000] -> PERI1: SPICLK - * PDIRD[12] = 1 [0x00080000] -> GPIO OUT: CS for ATC EEPROM - * ---------------------------------------------- */ - immr->im_ioport.iop_pdird &= ~0x0000E000; - immr->im_ioport.iop_pdird |= 0x00080000; - - /* ---------------------------------------------- - * special option reg. - * PSORD[16] = 1 [0x00008000] -> SPIMISO - * PSORD[17] = 1 [0x00004000] -> SPIMOSI - * PSORD[18] = 1 [0x00002000] -> SPICLK - * ---------------------------------------------- */ - immr->im_ioport.iop_psord |= 0x0000E000; - - /* Initialize the parameter ram. - * We need to make sure many things are initialized to zero - */ - spi->spi_rstate = 0; - spi->spi_rdp = 0; - spi->spi_rbptr = 0; - spi->spi_rbc = 0; - spi->spi_rxtmp = 0; - spi->spi_tstate = 0; - spi->spi_tdp = 0; - spi->spi_tbptr = 0; - spi->spi_tbc = 0; - spi->spi_txtmp = 0; - - /* Allocate space for one transmit and one receive buffer - * descriptor in the DP ram - */ -#ifdef CFG_ALLOC_DPRAM - dpaddr = m8260_cpm_dpalloc (sizeof(cbd_t)*2, 8); -#else - dpaddr = CPM_SPI_BASE; -#endif - -/* 3 */ - /* Set up the SPI parameters in the parameter ram */ - spi->spi_rbase = dpaddr; - spi->spi_tbase = dpaddr + sizeof (cbd_t); - - /***********IMPORTANT******************/ - - /* - * Setting transmit and receive buffer descriptor pointers - * initially to rbase and tbase. Only the microcode patches - * documentation talks about initializing this pointer. This - * is missing from the sample I2C driver. If you dont - * initialize these pointers, the kernel hangs. - */ - spi->spi_rbptr = spi->spi_rbase; - spi->spi_tbptr = spi->spi_tbase; - -/* 4 */ - /* Init SPI Tx + Rx Parameters */ - while (cp->cp_cpcr & CPM_CR_FLG) - ; - cp->cp_cpcr = mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG) - ; - -/* 6 */ - /* Set to big endian. */ - spi->spi_tfcr = CPMFCR_EB; - spi->spi_rfcr = CPMFCR_EB; - -/* 7 */ - /* Set maximum receive size. */ - spi->spi_mrblr = MAX_BUFFER; - -/* 8 + 9 */ - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; - rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; - - tbdf->cbd_sc &= ~BD_SC_READY; - rbdf->cbd_sc &= ~BD_SC_EMPTY; - - /* Set the bd's rx and tx buffer address pointers */ - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - -/* 10 + 11 */ - immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ - immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ - - - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r (void) -{ - volatile spi_t *spi; - volatile immap_t *immr; - volatile cpm8260_t *cp; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CFG_IMMR; - cp = (cpm8260_t *) &immr->im_cpm; - - spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; - rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *) malloc (MAX_BUFFER); - txbuf = (uchar *) malloc (MAX_BUFFER); - - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) { - break; - } - udelay(1000); - } - if (i >= 1000) { - printf ("*** spi_write: Time out while writing!\n"); - } - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer (size_t count) -{ - volatile immap_t *immr; - volatile cpm8260_t *cp; - volatile spi_t *spi; - cbd_t *tbdf, *rbdf; - int tm; - - DPRINT (("*** spi_xfer entered ***\n")); - - immr = (immap_t *) CFG_IMMR; - cp = (cpm8260_t *) &immr->im_cpm; - - spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; - - tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase]; - rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase]; - - /* Board-specific: Set CS for device (ATC EEPROM) */ - immr->im_ioport.iop_pdatd &= ~0x00080000; - - /* Setting tx bd status and data length */ - tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP; - tbdf->cbd_datlen = count; - - DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", - tbdf->cbd_datlen)); - - /* Setting rx bd status and data length */ - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - rbdf->cbd_datlen = 0; /* rx length has no significance */ - - immr->im_spi.spi_spmode = SPMODE_REV | - SPMODE_MSTR | - SPMODE_EN | - SPMODE_LEN(8) | /* 8 Bits per char */ - SPMODE_PM(0x8) ; /* medium speed */ - immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */ - immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */ - - /* start spi transfer */ - DPRINT (("*** spi_xfer: Performing transfer ...\n")); - immr->im_spi.spi_spcom |= SPI_STR; /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm=0; tm<1000; ++tm) { - if (immr->im_spi.spi_spie & SPI_TXB) { /* Tx Buffer Empty */ - DPRINT (("*** spi_xfer: Tx buffer empty\n")); - break; - } - if ((tbdf->cbd_sc & BD_SC_READY) == 0) { - DPRINT (("*** spi_xfer: Tx BD done\n")); - break; - } - udelay (1000); - } - if (tm >= 1000) { - printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); - } - DPRINT (("*** spi_xfer: ... transfer ended\n")); - -#ifdef DEBUG - printf ("\nspi_xfer: txbuf after xfer\n"); - memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */ - printf ("spi_xfer: rxbuf after xfer\n"); - memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */ - printf ("\n"); -#endif - - /* Clear CS for device */ - immr->im_ioport.iop_pdatd |= 0x00080000; - - return count; -} -#endif /* CONFIG_SPI */ diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S deleted file mode 100644 index 2e93bbb..0000000 --- a/cpu/mpc8260/start.S +++ /dev/null @@ -1,1046 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000, 2001,2002 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards - */ -#include -#include -#include - -#define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Floating Point enable, Machine Check and Recoverable Interr. */ -#ifdef DEBUG -#define MSR_KERNEL (MSR_FP|MSR_RI) -#else -#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) -#endif - -/* - * Set up GOT: Global Offset Table - * - * Use r14 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) -#if defined(CONFIG_HYMOD) - GOT_ENTRY(environment) -#endif - END_GOT - -/* - * Version string - must be in data segment because MPC8260 uses the first - * 256 bytes for the Hard Reset Configuration Word table (see below). - * Similarly, can't have the U-Boot Magic Number as the first thing in - * the image - don't know how this will affect the image tools, but I guess - * I'll find out soon - */ - .data - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - -/* - * Hard Reset Configuration Word (HRCW) table - * - * The Hard Reset Configuration Word (HRCW) sets a number of useful things - * such as whether there is an external memory controller, whether the - * PowerPC core is disabled (i.e. only the communications processor is - * active, accessed by another CPU on the bus), whether using external - * arbitration, external bus mode, boot port size, core initial prefix, - * internal space base, boot memory space, etc. - * - * These things dictate where the processor begins execution, where the - * boot ROM appears in memory, the memory controller setup when access - * boot ROM, etc. The HRCW is *extremely* important. - * - * The HRCW is read from the bus during reset. One CPU on the bus will - * be a hard reset configuration master, any others will be hard reset - * configuration slaves. The master reads eight HRCWs from flash during - * reset - the first it uses for itself, the other 7 it communicates to - * up to 7 configuration slaves by some complicated mechanism, which is - * not really important here. - * - * The configuration master performs 32 successive reads starting at address - * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8 - * bits is read, and always from byte lane D[0-7] (so that port size of the - * boot device does not matter). The first four reads form the 32 bit HRCW - * for the master itself. The second four reads form the HRCW for the first - * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by - * concatenating the four bytes, with the first read placed in byte 0 (the - * most significant byte), and so on with the fourth read placed in byte 3 - * (the least significant byte). - */ -#define _HRCW_TABLE_ENTRY(w) \ - .fill 8,1,(((w)>>24)&0xff); \ - .fill 8,1,(((w)>>16)&0xff); \ - .fill 8,1,(((w)>> 8)&0xff); \ - .fill 8,1,(((w) )&0xff) - .text - .globl _hrcw_table -_hrcw_table: - _HRCW_TABLE_ENTRY(CFG_HRCW_MASTER) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE1) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE2) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE3) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE4) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE5) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE6) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE7) -/* - * After configuration, a system reset exception is executed using the - * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP] - * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address - * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value - * of MSR[IP] is determined by the CIP field in the HRCW. - * - * Other bits in the HRCW set up the Base Address and Port Size in BR0. - * This determines the location of the boot ROM (flash or EPROM) in the - * processor's address space at boot time. As long as the HRCW is set up - * so that we eventually end up executing the code below when the processor - * executes the reset exception, the actual values used should not matter. - * - * Once we have got here, the address mask in OR0 is cleared so that the - * bottom 32K of the boot ROM is effectively repeated all throughout the - * processor's address space, after which we can jump to the absolute - * address at which the boot ROM was linked at compile time, and proceed - * to initialise the memory controller without worrying if the rug will be - * pulled out from under us, so to speak (it will be fine as long as we - * configure BR0 with the same boot ROM link address). - */ - . = EXC_OFF_SYS_RESET - - .globl _start -_start: - li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/ - nop - b boot_cold - - . = EXC_OFF_SYS_RESET + 0x10 - - .globl _start_warm -_start_warm: - li r21, BOOTFLAG_WARM /* Software reboot */ - b boot_warm - -boot_cold: -#if defined(CONFIG_MPC8260ADS) && defined(CFG_DEFAULT_IMMR) - lis r3, CFG_DEFAULT_IMMR@h - nop - lwz r4, 0(r3) - nop - rlwinm r4, r4, 0, 8, 5 - nop - oris r4, r4, 0x0200 - nop - stw r4, 0(r3) - nop -#endif /* CONFIG_MPC8260ADS && CFG_DEFAULT_IMMR */ -boot_warm: - mfmsr r5 /* save msr contents */ - -#if defined(CONFIG_COGENT) - /* this is what the cogent EPROM does */ - li r0, 0 - mtmsr r0 - isync - bl cogent_init_8260 -#endif /* CONFIG_COGENT */ - -#if defined(CFG_DEFAULT_IMMR) - lis r3, CFG_IMMR@h - ori r3, r3, CFG_IMMR@l - lis r4, CFG_DEFAULT_IMMR@h - stw r3, 0x1A8(r4) -#endif /* CFG_DEFAULT_IMMR */ - - /* Initialise the MPC8260 processor core */ - /*--------------------------------------------------------------*/ - - bl init_8260_core - -#ifndef CFG_RAMBOOT - /* When booting from ROM (Flash or EPROM), clear the */ - /* Address Mask in OR0 so ROM appears everywhere */ - /*--------------------------------------------------------------*/ - - lis r3, (CFG_IMMR+IM_REGBASE)@h - lwz r4, IM_OR0@l(r3) - li r5, 0x7fff - and r4, r4, r5 - stw r4, IM_OR0@l(r3) - - /* Calculate absolute address in FLASH and jump there */ - /*--------------------------------------------------------------*/ - - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: -#endif /* CFG_RAMBOOT */ - - /* initialize some things that are hard to access from C */ - /*--------------------------------------------------------------*/ - - lis r3, CFG_IMMR@h /* set up stack in internal DPRAM */ - ori r1, r3, CFG_INIT_SP_OFFSET - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*--------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (in Flash)*/ - -#ifdef DEBUG - bl init_debug /* set up debugging stuff */ -#endif - - mr r3, r21 - /* r3: BOOTFLAG */ - bl board_init_f /* run 1st part of board init code (in Flash)*/ - -/* - * Vector Table - */ - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) -#ifdef DEBUG - . = 0x1300 - /* - * This exception occurs when the program counter matches the - * Instruction Address Breakpoint Register (IABR). - * - * I want the cpu to halt if this occurs so I can hunt around - * with the debugger and look at things. - * - * When DEBUG is defined, both machine check enable (in the MSR) - * and checkstop reset enable (in the reset mode register) are - * turned off and so a checkstop condition will result in the cpu - * halting. - * - * I force the cpu into a checkstop condition by putting an illegal - * instruction here (at least this is the theory). - * - * well - that didnt work, so just do an infinite loop! - */ -1: b 1b -#else - STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) -#endif - STD_EXCEPTION(0x1400, SMI, UnknownException) - - STD_EXCEPTION(0x1500, Trap_15, UnknownException) - STD_EXCEPTION(0x1600, Trap_16, UnknownException) - STD_EXCEPTION(0x1700, Trap_17, UnknownException) - STD_EXCEPTION(0x1800, Trap_18, UnknownException) - STD_EXCEPTION(0x1900, Trap_19, UnknownException) - STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) - STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) - STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) - STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) - STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) - STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) - STD_EXCEPTION(0x2000, Trap_20, UnknownException) - STD_EXCEPTION(0x2100, Trap_21, UnknownException) - STD_EXCEPTION(0x2200, Trap_22, UnknownException) - STD_EXCEPTION(0x2300, Trap_23, UnknownException) - STD_EXCEPTION(0x2400, Trap_24, UnknownException) - STD_EXCEPTION(0x2500, Trap_25, UnknownException) - STD_EXCEPTION(0x2600, Trap_26, UnknownException) - STD_EXCEPTION(0x2700, Trap_27, UnknownException) - STD_EXCEPTION(0x2800, Trap_28, UnknownException) - STD_EXCEPTION(0x2900, Trap_29, UnknownException) - STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) - STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) - STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) - STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) - STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) - STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x3000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -#if defined(CONFIG_COGENT) - -/* - * This code initialises the MPC8260 processor core - * (conforms to PowerPC 603e spec) - */ - - .globl cogent_init_8260 -cogent_init_8260: - - /* Taken from page 14 of CMA282 manual */ - /*--------------------------------------------------------------*/ - - lis r4, (CFG_IMMR+IM_REGBASE)@h - lis r3, CFG_IMMR@h - stw r3, IM_IMMR@l(r4) - lwz r3, IM_IMMR@l(r4) - stw r3, 0(r0) - lis r3, CFG_SYPCR@h - ori r3, r3, CFG_SYPCR@l - stw r3, IM_SYPCR@l(r4) - lwz r3, IM_SYPCR@l(r4) - stw r3, 4(r0) - lis r3, CFG_SCCR@h - ori r3, r3, CFG_SCCR@l - stw r3, IM_SCCR@l(r4) - lwz r3, IM_SCCR@l(r4) - stw r3, 8(r0) - - /* the rest of this was disassembled from the */ - /* EPROM code that came with my CMA282 CPU module */ - /*--------------------------------------------------------------*/ - - lis r1, 0x1234 - ori r1, r1, 0x5678 - stw r1, 0x20(r0) - lwz r1, 0x20(r0) - stw r1, 0x24(r0) - lwz r1, 0x24(r0) - lis r3, 0x0e80 - ori r3, r3, 0 - stw r1, 4(r3) - lwz r1, 4(r3) - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr - -#endif /* CONFIG_COGENT */ - -/* - * This code initialises the MPC8260 processor core - * (conforms to PowerPC 603e spec) - * Note: expects original MSR contents to be in r5. - */ - - .globl init_8260_core -init_8260_core: - - /* Initialize machine status; enable machine check interrupt */ - /*--------------------------------------------------------------*/ - - li r3, MSR_KERNEL /* Set ME and RI flags */ - rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ -#ifdef DEBUG - rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ -#endif - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - /* Initialise the SYPCR early, and reset the watchdog (if req) */ - /*--------------------------------------------------------------*/ - - lis r3, (CFG_IMMR+IM_REGBASE)@h -#if !defined(CONFIG_COGENT) - lis r4, CFG_SYPCR@h - ori r4, r4, CFG_SYPCR@l - stw r4, IM_SYPCR@l(r3) -#endif /* !CONFIG_COGENT */ -#if defined(CONFIG_WATCHDOG) - li r4, 21868 /* = 0x556c */ - sth r4, IM_SWSR@l(r3) - li r4, -21959 /* = 0xaa39 */ - sth r4, IM_SWSR@l(r3) -#endif /* CONFIG_WATCHDOG */ - - /* Initialize the Hardware Implementation-dependent Registers */ - /* HID0 also contains cache control */ - /*--------------------------------------------------------------*/ - - lis r3, CFG_HID0_INIT@h - ori r3, r3, CFG_HID0_INIT@l - SYNC - mtspr HID0, r3 - - lis r3, CFG_HID0_FINAL@h - ori r3, r3, CFG_HID0_FINAL@l - SYNC - mtspr HID0, r3 - - lis r3, CFG_HID2@h - ori r3, r3, CFG_HID2@l - mtspr HID2, r3 - - /* clear all BAT's */ - /*--------------------------------------------------------------*/ - - li r0, 0 - mtspr DBAT0U, r0 - mtspr DBAT0L, r0 - mtspr DBAT1U, r0 - mtspr DBAT1L, r0 - mtspr DBAT2U, r0 - mtspr DBAT2L, r0 - mtspr DBAT3U, r0 - mtspr DBAT3L, r0 - mtspr IBAT0U, r0 - mtspr IBAT0L, r0 - mtspr IBAT1U, r0 - mtspr IBAT1L, r0 - mtspr IBAT2U, r0 - mtspr IBAT2L, r0 - mtspr IBAT3U, r0 - mtspr IBAT3L, r0 - SYNC - - /* invalidate all tlb's */ - /* */ - /* From the 603e User Manual: "The 603e provides the ability to */ - /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */ - /* instruction invalidates the TLB entry indexed by the EA, and */ - /* operates on both the instruction and data TLBs simultaneously*/ - /* invalidating four TLB entries (both sets in each TLB). The */ - /* index corresponds to bits 15-19 of the EA. To invalidate all */ - /* entries within both TLBs, 32 tlbie instructions should be */ - /* issued, incrementing this field by one each time." */ - /* */ - /* "Note that the tlbia instruction is not implemented on the */ - /* 603e." */ - /* */ - /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */ - /* incrementing by 0x1000 each time. The code below is sort of */ - /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */ - /* */ - /*--------------------------------------------------------------*/ - - li r3, 32 - mtctr r3 - li r3, 0 -1: tlbie r3 - addi r3, r3, 0x1000 - bdnz 1b - SYNC - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr - -#ifdef DEBUG - -/* - * initialise things related to debugging. - * - * must be called after the global offset table (GOT) is initialised - * (GET_GOT) and after cpu_init_f() has executed. - */ - - .globl init_debug -init_debug: - - lis r3, (CFG_IMMR+IM_REGBASE)@h - - /* Quick and dirty hack to enable the RAM and copy the */ - /* vectors so that we can take exceptions. */ - /*--------------------------------------------------------------*/ - /* write Memory Refresh Prescaler */ - li r4, CFG_MPTPR - sth r4, IM_MPTPR@l(r3) - /* write 60x Refresh Timer */ - li r4, CFG_PSRT - stb r4, IM_PSRT@l(r3) - /* init the 60x SDRAM Mode Register */ - lis r4, (CFG_PSDMR|PSDMR_OP_NORM)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM)@l - stw r4, IM_PSDMR@l(r3) - /* write Precharge All Banks command */ - lis r4, (CFG_PSDMR|PSDMR_OP_PREA)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_PREA)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - /* write eight CBR Refresh commands */ - lis r4, (CFG_PSDMR|PSDMR_OP_CBRR)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_CBRR)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - stb r0, 0(0) - /* write Mode Register Write command */ - lis r4, (CFG_PSDMR|PSDMR_OP_MRW)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_MRW)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - /* write Normal Operation command and enable Refresh */ - lis r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l - stw r4, IM_PSDMR@l(r3) - stb r0, 0(0) - /* RAM should now be operational */ - -#define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4) - - lwz r3, GOT(_end_of_vectors) - rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */ - lis r5, VEC_WRD_CNT@h - ori r5, r5, VEC_WRD_CNT@l - mtctr r5 -1: - lwzu r5, -4(r3) - stwu r5, -4(r4) - bdnz 1b - - /* Load the Instruction Address Breakpoint Register (IABR). */ - /* */ - /* The address to load is stored in the first word of dual port */ - /* ram and should be preserved while the power is on, so you */ - /* can plug addresses into that location then reset the cpu and */ - /* this code will load that address into the IABR after the */ - /* reset. */ - /* */ - /* When the program counter matches the contents of the IABR, */ - /* an exception is generated (before the instruction at that */ - /* location completes). The vector for this exception is 0x1300 */ - /*--------------------------------------------------------------*/ - lis r3, CFG_IMMR@h - lwz r3, 0(r3) - mtspr IABR, r3 - - /* Set the entire dual port RAM (where the initial stack */ - /* resides) to a known value - makes it easier to see where */ - /* the stack has been written */ - /*--------------------------------------------------------------*/ - lis r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@h - ori r3, r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@l - li r4, ((CFG_INIT_SP_OFFSET - 4) / 4) - mtctr r4 - lis r4, 0xdeadbeaf@h - ori r4, r4, 0xdeadbeaf@l -1: - stwu r4, -4(r3) - bdnz 1b - - /* Done! */ - /*--------------------------------------------------------------*/ - - blr -#endif - -/* Cache functions. - * - * Note: requires that all cache bits in - * HID0 are in the low half word. - */ - .globl icache_enable -icache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_ICE - lis r4, 0 - ori r4, r4, HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_disable -icache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_ICE|HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31 - blr - - .globl dcache_enable -dcache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_DCE - lis r4, 0 - ori r4, r4, HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_disable -dcache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_DCE|HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI - sync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31 - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r14, r14, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mfspr r7,HID0 /* don't do dcbst if dcache is disabled */ - rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31 - cmpwi r7,0 - beq 9f - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ -9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ - rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31 - cmpwi r7,0 - beq 7f - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r14 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - add r0,r0,r11 - stw r0,0(r3) - bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ -2: li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) -#if defined(CONFIG_HYMOD) - /* - * For HYMOD - the environment is the very last item in flash. - * The real .bss stops just before environment starts, so only - * clear up to that point. - * - * taken from mods for FADS board - */ - lwz r4,GOT(environment) -#else - lwz r4,GOT(_end) -#endif - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mfmsr r3 /* now that the vectors have */ - lis r7, MSR_IP@h /* relocated into low memory */ - ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ - andc r3, r3, r7 /* (if it was on) */ - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - - mtlr r4 /* restore link register */ - blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c deleted file mode 100644 index 0c39e43..0000000 --- a/cpu/mpc8260/traps.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * linux/arch/ppc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -int (*debugger_exception_handler)(struct pt_regs *) = 0; -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x02000000 - -/* - * Trap & Exception support - */ - -void -print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - puts ("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - putc ('\n'); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - putc ('\n'); -} - -void show_regs(struct pt_regs * regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - putc ('\n'); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) { - putc ('\n'); - } - } -} - - -void -_exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -#ifdef CONFIG_PCI -void dump_pci (void) -{ - - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - printf ("PCI: err status %x err mask %x err ctrl %x\n", - le32_to_cpu (immap->im_pci.pci_esr), - le32_to_cpu (immap->im_pci.pci_emr), - le32_to_cpu (immap->im_pci.pci_ecr)); - printf (" error address %x error data %x ctrl %x\n", - le32_to_cpu (immap->im_pci.pci_eacr), - le32_to_cpu (immap->im_pci.pci_edcr), - le32_to_cpu (immap->im_pci.pci_eccr)); - -} -#endif - -void -MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ -#ifdef CONFIG_PCI - volatile immap_t *immap = (immap_t *)CFG_IMMR; -#ifdef DEBUG - dump_pci(); -#endif - /* clear the error in the error status register */ - if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) { - immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP); - return; - } -#endif - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - puts ("Machine check in kernel mode.\n" - "Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - puts ("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - puts ("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - puts ("Data parity signal\n"); - break; - case (0x80000000>>15): - puts ("Address parity signal\n"); - break; - default: - puts ("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); -#ifdef CONFIG_PCI - dump_pci(); -#endif - panic("machine check"); -} - -void -AlignmentException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void -ProgramCheckException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void -SoftEmuException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void -UnknownException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -void -DebugException(struct pt_regs *regs) -{ - - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int -addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile deleted file mode 100644 index 60df4cd..0000000 --- a/cpu/mpc83xx/Makefile +++ /dev/null @@ -1,52 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o \ - resetvec.o - -COBJS = traps.o \ - cpu.o \ - cpu_init.o \ - speed.o \ - interrupts.o \ - i2c.o \ - spd_sdram.o - -OBJS = $(COBJS) - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk deleted file mode 100644 index 8b4ff92..0000000 --- a/cpu/mpc83xx/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \ - -ffixed-r2 -ffixed-r29 -msoft-float diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c deleted file mode 100644 index 8c9b515..0000000 --- a/cpu/mpc83xx/cpu.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - */ - -/* - * CPU specific code for the MPC83xx family. - * - * Derived from the MPC8260 and MPC85xx. - */ - -#include -#include -#include -#include -#include - - -int checkcpu(void) -{ - DECLARE_GLOBAL_DATA_PTR; - ulong clock = gd->cpu_clk; - u32 pvr = get_pvr(); - char buf[32]; - - if ((pvr & 0xFFFF0000) != PVR_83xx) { - puts("Not MPC83xx Family!!!\n"); - return -1; - } - - puts("CPU: MPC83xx, "); - switch(pvr) { - case PVR_8349_REV10: - break; - case PVR_8349_REV11: - break; - default: - puts("Rev: Unknown\n"); - return -1; /* Not sure what this is */ - } - printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4, - (pvr & 0x0f), strmhz(buf, clock)); - - return 0; -} - - -void upmconfig (uint upm, uint *table, uint size) -{ - hang(); /* FIXME: upconfig() needed? */ -} - - -int -do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - ulong msr; -#ifndef MPC83xx_RESET - ulong addr; -#endif - - volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; - -#ifdef MPC83xx_RESET - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~( MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* enable Reset Control Reg */ - immap->reset.rpr = 0x52535445; - - /* confirm Reset Control Reg is enabled */ - while(!((immap->reset.rcer) & RCER_CRE)); - - printf("Resetting the board."); - printf("\n"); - - udelay(200); - - /* perform reset, only one bit */ - immap->reset.rcr = RCR_SWHR; - -#else /* ! MPC83xx_RESET */ - - immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */ - - /* Interrupts and MMU off */ - __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); - - msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); - __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); - - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ - addr = CFG_RESET_ADDRESS; - - printf("resetting the board."); - printf("\n"); - ((void (*)(void)) addr) (); -#endif /* MPC83xx_RESET */ - - return 1; -} - - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - */ - -unsigned long get_tbclk(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong tbclk; - - tbclk = (gd->bus_clk + 3L) / 4L; - - return tbclk; -} - - -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ - hang(); /* FIXME: implement watchdog_reset()? */ -} -#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c deleted file mode 100644 index dcb3445..0000000 --- a/cpu/mpc83xx/cpu_init.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - */ - -#include -#include -#include - -/* - * Breathe some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f (volatile immap_t * im) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - /* RSR - Reset Status Register - clear all status (4.6.1.3) */ - gd->reset_status = im->reset.rsr; - im->reset.rsr = ~(RSR_RES); - - /* - * RMR - Reset Mode Register - * contains checkstop reset enable (4.6.1.4) - */ - im->reset.rmr = (RMR_CSRE & (1<lbus.lcrr = CFG_LCRR; - - /* Enable Time Base & Decrimenter ( so we will have udelay() )*/ - im->sysconf.spcr |= SPCR_TBEN; - - /* System General Purpose Register */ - im->sysconf.sicrh = SICRH_TSOBI1; - im->sysconf.sicrl = SICRL_LDP_A; - - /* - * Memory Controller: - */ - - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ - -#if defined(CFG_BR0_PRELIM) \ - && defined(CFG_OR0_PRELIM) \ - && defined(CFG_LBLAWBAR0_PRELIM) \ - && defined(CFG_LBLAWAR0_PRELIM) - im->lbus.bank[0].br = CFG_BR0_PRELIM; - im->lbus.bank[0].or = CFG_OR0_PRELIM; - im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM; - im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM; -#else -#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined -#endif - -#if defined(CFG_BR1_PRELIM) \ - && defined(CFG_OR1_PRELIM) \ - && defined(CFG_LBLAWBAR1_PRELIM) \ - && defined(CFG_LBLAWAR1_PRELIM) - im->lbus.bank[1].br = CFG_BR1_PRELIM; - im->lbus.bank[1].or = CFG_OR1_PRELIM; - im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM; - im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM; -#endif -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) - im->lbus.bank[2].br = CFG_BR2_PRELIM; - im->lbus.bank[2].or = CFG_OR2_PRELIM; - im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM; - im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM; -#endif -#if defined(CFG_BR3_PRELIM) \ - && defined(CFG_OR3_PRELIM) \ - && defined(CFG_LBLAWBAR3_PRELIM) \ - && defined(CFG_LBLAWAR3_PRELIM) - im->lbus.bank[3].br = CFG_BR3_PRELIM; - im->lbus.bank[3].or = CFG_OR3_PRELIM; - im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM; - im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM; -#endif -#if defined(CFG_BR4_PRELIM) \ - && defined(CFG_OR4_PRELIM) \ - && defined(CFG_LBLAWBAR4_PRELIM) \ - && defined(CFG_LBLAWAR4_PRELIM) - im->lbus.bank[4].br = CFG_BR4_PRELIM; - im->lbus.bank[4].or = CFG_OR4_PRELIM; - im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM; - im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM; -#endif -#if defined(CFG_BR5_PRELIM) \ - && defined(CFG_OR5_PRELIM) \ - && defined(CFG_LBLAWBAR5_PRELIM) \ - && defined(CFG_LBLAWAR5_PRELIM) - im->lbus.bank[5].br = CFG_BR5_PRELIM; - im->lbus.bank[5].or = CFG_OR5_PRELIM; - im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM; - im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM; -#endif -#if defined(CFG_BR6_PRELIM) \ - && defined(CFG_OR6_PRELIM) \ - && defined(CFG_LBLAWBAR6_PRELIM) \ - && defined(CFG_LBLAWAR6_PRELIM) - im->lbus.bank[6].br = CFG_BR6_PRELIM; - im->lbus.bank[6].or = CFG_OR6_PRELIM; - im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM; - im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM; -#endif -#if defined(CFG_BR7_PRELIM) \ - && defined(CFG_OR7_PRELIM) \ - && defined(CFG_LBLAWBAR7_PRELIM) \ - && defined(CFG_LBLAWAR7_PRELIM) - im->lbus.bank[7].br = CFG_BR7_PRELIM; - im->lbus.bank[7].or = CFG_OR7_PRELIM; - im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM; - im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM; -#endif -} - - -/* - * Initialize higher level parts of CPU like time base and timers. - */ - -int cpu_init_r (void) -{ - return 0; -} diff --git a/cpu/mpc83xx/i2c.c b/cpu/mpc83xx/i2c.c deleted file mode 100644 index 4e70f80..0000000 --- a/cpu/mpc83xx/i2c.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao - * Adapted for Motorola 85xx chip. - * - * (C) Copyright 2003 - * Gleb Natapov - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk - * - * Hardware I2C driver for MPC107 PCI bridge. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - */ - -#include -#include -#include - -#ifdef CONFIG_HARD_I2C -#include -#include - -#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X) -i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET); -#endif - -void -i2c_init(int speed, int slaveadd) -{ - /* stop I2C controller */ - writeb(0x00 , &I2C->cr); - - /* set clock */ - writeb(0x3f, &I2C->fdr); - - /* set default filter */ - writeb(0x10,&I2C->dfsrr); - - /* write slave address */ - writeb(slaveadd, &I2C->adr); - - /* clear status register */ - writeb(0x00, &I2C->sr); - - /* start I2C controller */ - writeb(I2C_CR_MEN, &I2C->cr); -} - -static __inline__ int -i2c_wait4bus (void) -{ - ulong timeval = get_timer (0); - while (readb(&I2C->sr) & I2C_SR_MBB) { - if (get_timer (timeval) > I2C_TIMEOUT) { - return -1; - } - } - return 0; -} - -static __inline__ int -i2c_wait (int write) -{ - u32 csr; - ulong timeval = get_timer(0); - do { - csr = readb(&I2C->sr); - - if (!(csr & I2C_SR_MIF)) - continue; - - writeb(0x0, &I2C->sr); - - if (csr & I2C_SR_MAL) { - debug("i2c_wait: MAL\n"); - return -1; - } - - if (!(csr & I2C_SR_MCF)) { - debug("i2c_wait: unfinished\n"); - return -1; - } - - if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { - debug("i2c_wait: No RXACK\n"); - return -1; - } - - return 0; - } while (get_timer (timeval) < I2C_TIMEOUT); - - debug("i2c_wait: timed out\n"); - return -1; -} - -static __inline__ int -i2c_write_addr (u8 dev, u8 dir, int rsta) -{ - writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | - (rsta?I2C_CR_RSTA:0), - &I2C->cr); - - writeb((dev << 1) | dir, &I2C->dr); - - if (i2c_wait (I2C_WRITE) < 0) - return 0; - return 1; -} - -static __inline__ int -__i2c_write (u8 *data, int length) -{ - int i; - - writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, - &I2C->cr); - - for (i=0; i < length; i++) { - writeb(data[i], &I2C->dr); - - if (i2c_wait (I2C_WRITE) < 0) - break; - } - return i; -} - -static __inline__ int -__i2c_read (u8 *data, int length) -{ - int i; - - writeb(I2C_CR_MEN | I2C_CR_MSTA | - ((length == 1) ? I2C_CR_TXAK : 0), - &I2C->cr); - - /* dummy read */ - readb(&I2C->dr); - - for (i=0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) - break; - - /* Generate ack on last next to last byte */ - if (i == length - 2) - writeb(I2C_CR_MEN | I2C_CR_MSTA | - I2C_CR_TXAK, - &I2C->cr); - - /* Generate stop on last byte */ - if (i == length - 1) - writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); - - data[i] = readb(&I2C->dr); - } - return i; -} - -int -i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr (dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read (data, length); - - exit: - writeb(I2C_CR_MEN, &I2C->cr); - return !(i == length); -} - -int -i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write (data, length); - - exit: - writeb(I2C_CR_MEN, &I2C->cr); - return !(i == length); -} - -int i2c_probe (uchar chip) -{ - int tmp; - - /* - * Try to read the first location of the chip. The underlying - * driver doesn't appear to support sending just the chip address - * and looking for an back. - */ - udelay(10000); - return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); -} - -uchar i2c_reg_read (uchar i2c_addr, uchar reg) -{ - uchar buf[1]; - - i2c_read (i2c_addr, reg, 1, buf, 1); - - return (buf[0]); -} - -void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write (i2c_addr, reg, 1, &val, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c deleted file mode 100644 index 53474f6..0000000 --- a/cpu/mpc83xx/interrupts.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright 2004 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00 - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - */ - -#include -#include -#include -#include - -struct irq_action { - interrupt_handler_t *handler; - void *arg; - ulong count; -}; - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - return 0; -} - - -/* - * Handle external interrupts - */ - -void external_interrupt (struct pt_regs *regs) -{ -} - - -/* - * Install and free an interrupt handler. - */ - -void -irq_install_handler (int irq, interrupt_handler_t * handler, void *arg) -{ -} - - -void irq_free_handler (int irq) -{ -} - - -void timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} - - -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) - -/* ripped this out of ppc4xx/interrupts.c */ - -/* - * irqinfo - print information about PCI devices - */ - -void -do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/mpc83xx/resetvec.S b/cpu/mpc83xx/resetvec.S deleted file mode 100644 index 3dfcd0d..0000000 --- a/cpu/mpc83xx/resetvec.S +++ /dev/null @@ -1,6 +0,0 @@ - .section .resetvec,"ax" -#ifndef FIXME -#if 0 - b _start_e500 -#endif -#endif diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c deleted file mode 100644 index 63dcd66..0000000 --- a/cpu/mpc83xx/spd_sdram.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao (X.Xiao@motorola.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - */ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SPD_EEPROM - -#if defined(CONFIG_DDR_ECC) -extern void dma_init(void); -extern uint dma_check(void); -extern int dma_xfer(void *dest, uint count, void *src); -#endif - -#ifndef CFG_READ_SPD -#define CFG_READ_SPD i2c_read -#endif - -/* - * Convert picoseconds into clock cycles (rounding up if needed). - */ - -int -picos_to_clk(int picos) -{ - int clks; - - clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); - if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { - clks++; - } - - return clks; -} - -unsigned int -banksize(unsigned char row_dens) -{ - return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; -} - -long int spd_sdram(int(read_spd)(uint addr)) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; - volatile ddr8349_t *ddr = &immap->ddr; - volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0]; - spd_eeprom_t spd; - unsigned tmp, tmp1; - unsigned int memsize; - unsigned int law_size; - unsigned char caslat; - unsigned int trfc, trfc_clk, trfc_low; - -#warning Current spd_sdram does not fit its usage... adjust implementation or API... - - CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); - - if (spd.nrows > 2) { - puts("DDR:Only two chip selects are supported on ADS.\n"); - return 0; - } - - if (spd.nrow_addr < 12 - || spd.nrow_addr > 14 - || spd.ncol_addr < 8 - || spd.ncol_addr > 11) { - puts("DDR:Row or Col number unsupported.\n"); - return 0; - } - - ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; - ddr->cs_config[2] = ( 1 << 31 - | (spd.nrow_addr - 12) << 8 - | (spd.ncol_addr - 8) ); - debug("\n"); - debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); - debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); - - if (spd.nrows == 2) { - ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8) - | ((banksize(spd.row_dens) >> 23) - 1) ); - ddr->cs_config[3] = ( 1<<31 - | (spd.nrow_addr-12) << 8 - | (spd.ncol_addr-8) ); - debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); - debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); - } - - if (spd.mem_type != 0x07) { - puts("No DDR module found!\n"); - return 0; - } - - /* - * Figure out memory size in Megabytes. - */ - memsize = spd.nrows * banksize(spd.row_dens) / 0x100000; - - /* - * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. - */ - law_size = 19 + __ilog2(memsize); - - /* - * Set up LAWBAR for all of DDR. - */ - ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); - ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); - debug("DDR:bar=0x%08x\n", ecm->bar); - debug("DDR:ar=0x%08x\n", ecm->ar); - - /* - * find the largest CAS - */ - if(spd.cas_lat & 0x40) { - caslat = 7; - } else if (spd.cas_lat & 0x20) { - caslat = 6; - } else if (spd.cas_lat & 0x10) { - caslat = 5; - } else if (spd.cas_lat & 0x08) { - caslat = 4; - } else if (spd.cas_lat & 0x04) { - caslat = 3; - } else if (spd.cas_lat & 0x02) { - caslat = 2; - } else if (spd.cas_lat & 0x01) { - caslat = 1; - } else { - puts("DDR:no valid CAS Latency information.\n"); - return 0; - } - - tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10 - + (spd.clk_cycle & 0x0f)); - debug("DDR:Module maximum data rate is: %dMhz\n", tmp); - - tmp1 = get_bus_freq(0) / 1000000; - if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) { - /* 90~230 range, treated as DDR 200 */ - if (spd.clk_cycle3 == 0xa0) - caslat -= 2; - else if(spd.clk_cycle2 == 0xa0) - caslat--; - } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) { - /* 230-280 range, treated as DDR 266 */ - if (spd.clk_cycle3 == 0x75) - caslat -= 2; - else if (spd.clk_cycle2 == 0x75) - caslat--; - } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) { - /* 280~350 range, treated as DDR 333 */ - if (spd.clk_cycle3 == 0x60) - caslat -= 2; - else if (spd.clk_cycle2 == 0x60) - caslat--; - } else if (tmp1 < 90 || tmp1 >= 350) { - /* DDR rate out-of-range */ - puts("DDR:platform frequency is not fit for DDR rate\n"); - return 0; - } - - /* - * note: caslat must also be programmed into ddr->sdram_mode - * register. - * - * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD, - * use conservative value here. - */ - trfc = spd.trfc * 1000; /* up to ps */ - trfc_clk = picos_to_clk(trfc); - trfc_low = (trfc_clk - 8) & 0xf; - - ddr->timing_cfg_1 = - (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | - ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | - ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) | - ((caslat & 0x07) << 16 ) | - (trfc_low << 12 ) | - ( 0x300 ) | - ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1); - - ddr->timing_cfg_2 = 0x00000800; - - debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); - debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); - - /* - * Only DDR I is supported - * DDR I and II have different mode-register-set definition - */ - - /* burst length is always 4 */ - switch(caslat) { - case 2: - ddr->sdram_mode = 0x52; /* 1.5 */ - break; - case 3: - ddr->sdram_mode = 0x22; /* 2.0 */ - break; - case 4: - ddr->sdram_mode = 0x62; /* 2.5 */ - break; - case 5: - ddr->sdram_mode = 0x32; /* 3.0 */ - break; - default: - puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n"); - return 0; - } - debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); - - switch(spd.refresh) { - case 0x00: - case 0x80: - tmp = picos_to_clk(15625000); - break; - case 0x01: - case 0x81: - tmp = picos_to_clk(3900000); - break; - case 0x02: - case 0x82: - tmp = picos_to_clk(7800000); - break; - case 0x03: - case 0x83: - tmp = picos_to_clk(31300000); - break; - case 0x04: - case 0x84: - tmp = picos_to_clk(62500000); - break; - case 0x05: - case 0x85: - tmp = picos_to_clk(125000000); - break; - default: - tmp = 0x512; - break; - } - - /* - * Set BSTOPRE to 0x100 for page mode - * If auto-charge is used, set BSTOPRE = 0 - */ - ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100; - debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); - - /* - * Is this an ECC DDR chip? - */ -#if defined(CONFIG_DDR_ECC) - if (spd.config == 0x02) { - ddr->err_disable = 0x0000000d; - ddr->err_sbe = 0x00ff0000; - } - debug("DDR:err_disable=0x%08x\n", ddr->err_disable); - debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); -#endif - asm("sync;isync"); - - udelay(500); - - /* - * SS_EN=1, - * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM - * clock cycle after address/command - */ - ddr->sdram_clk_cntl = 0x82000000; - - /* - * Figure out the settings for the sdram_cfg register. Build up - * the entire register in 'tmp' before writing since the write into - * the register will actually enable the memory controller, and all - * settings must be done before enabling. - * - * sdram_cfg[0] = 1 (ddr sdram logic enable) - * sdram_cfg[1] = 1 (self-refresh-enable) - * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM) - */ - tmp = 0xc2000000; - - /* - * sdram_cfg[3] = RD_EN - registered DIMM enable - * A value of 0x26 indicates micron registered DIMMS (micron.com) - */ - if (spd.mod_attr == 0x26) { - tmp |= 0x10000000; - } - -#if defined(CONFIG_DDR_ECC) - /* - * If the user wanted ECC (enabled via sdram_cfg[2]) - */ - if (spd.config == 0x02) { - tmp |= 0x20000000; - } -#endif - -#if defined(CONFIG_DDR_2T_TIMING) - /* - * Enable 2T timing by setting sdram_cfg[16]. - */ - tmp |= SDRAM_CFG_2T_EN; -#endif - - ddr->sdram_cfg = tmp; - asm("sync;isync"); - udelay(500); - - debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg); - - return memsize;/*in MBytes*/ -} -#endif /* CONFIG_SPD_EEPROM */ - - -#if defined(CONFIG_DDR_ECC) -/* - * Initialize all of memory for ECC, then enable errors. - */ - -void -ddr_enable_ecc(unsigned int dram_size) -{ -#ifndef FIXME - uint *p = 0; - uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - - dma_init(); - - for (*p = 0; p < (uint *)(8 * 1024); p++) { - if (((unsigned int)p & 0x1f) == 0) { - ppcDcbz((unsigned long) p); - } - *p = (unsigned int)0xdeadbeef; - if (((unsigned int)p & 0x1c) == 0x1c) { - ppcDcbf((unsigned long) p); - } - } - - /* 8K */ - dma_xfer((uint *)0x2000, 0x2000, (uint *)0); - /* 16K */ - dma_xfer((uint *)0x4000, 0x4000, (uint *)0); - /* 32K */ - dma_xfer((uint *)0x8000, 0x8000, (uint *)0); - /* 64K */ - dma_xfer((uint *)0x10000, 0x10000, (uint *)0); - /* 128k */ - dma_xfer((uint *)0x20000, 0x20000, (uint *)0); - /* 256k */ - dma_xfer((uint *)0x40000, 0x40000, (uint *)0); - /* 512k */ - dma_xfer((uint *)0x80000, 0x80000, (uint *)0); - /* 1M */ - dma_xfer((uint *)0x100000, 0x100000, (uint *)0); - /* 2M */ - dma_xfer((uint *)0x200000, 0x200000, (uint *)0); - /* 4M */ - dma_xfer((uint *)0x400000, 0x400000, (uint *)0); - - for (i = 1; i < dram_size / 0x800000; i++) { - dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); - } - - /* - * Enable errors for ECC. - */ - ddr->err_disable = 0x00000000; - asm("sync;isync"); -#endif -} - -#endif /* CONFIG_DDR_ECC */ diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c deleted file mode 100644 index 1368fc3..0000000 --- a/cpu/mpc83xx/speed.c +++ /dev/null @@ -1,366 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright 2004 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - */ - -#include -#include -#include - -/* ----------------------------------------------------------------- */ - -typedef enum { - _unk, - _off, - _byp, - _x8, - _x4, - _x2, - _x1, - _1x, - _1_5x, - _2x, - _2_5x, - _3x -} mult_t; - -typedef struct { - mult_t core_csb_ratio; - mult_t vco_divider; -} corecnf_t; - -corecnf_t corecnf_tab[] = { - { _byp, _byp}, /* 0x00 */ - { _byp, _byp}, /* 0x01 */ - { _byp, _byp}, /* 0x02 */ - { _byp, _byp}, /* 0x03 */ - { _byp, _byp}, /* 0x04 */ - { _byp, _byp}, /* 0x05 */ - { _byp, _byp}, /* 0x06 */ - { _byp, _byp}, /* 0x07 */ - { _1x, _x2}, /* 0x08 */ - { _1x, _x4}, /* 0x09 */ - { _1x, _x8}, /* 0x0A */ - { _1x, _x8}, /* 0x0B */ - {_1_5x, _x2}, /* 0x0C */ - {_1_5x, _x4}, /* 0x0D */ - {_1_5x, _x8}, /* 0x0E */ - {_1_5x, _x8}, /* 0x0F */ - { _2x, _x2}, /* 0x10 */ - { _2x, _x4}, /* 0x11 */ - { _2x, _x8}, /* 0x12 */ - { _2x, _x8}, /* 0x13 */ - {_2_5x, _x2}, /* 0x14 */ - {_2_5x, _x4}, /* 0x15 */ - {_2_5x, _x8}, /* 0x16 */ - {_2_5x, _x8}, /* 0x17 */ - { _3x, _x2}, /* 0x18 */ - { _3x, _x4}, /* 0x19 */ - { _3x, _x8}, /* 0x1A */ - { _3x, _x8}, /* 0x1B */ -}; - -/* ----------------------------------------------------------------- */ - -/* - * - */ -int get_clocks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - volatile immap_t *im = (immap_t *)CFG_IMMRBAR; - u32 pci_sync_in; - u8 spmf; - u8 clkin_div; - u32 sccr; - u32 corecnf_tab_index; - u8 corepll; - u32 lcrr; - - u32 csb_clk; - u32 tsec1_clk; - u32 tsec2_clk; - u32 core_clk; - u32 usbmph_clk; - u32 usbdr_clk; - u32 i2c_clk; - u32 enc_clk; - u32 lbiu_clk; - u32 lclk_clk; - u32 ddr_clk; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -1; - -#ifndef CFG_HRCW_HIGH -# error "CFG_HRCW_HIGH must be defined in board config file" -#endif /* CFG_HCWD_HIGH */ - -#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST) - -# ifndef CONFIG_83XX_CLKIN -# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file" -# endif /* CONFIG_83XX_CLKIN */ -# ifdef CONFIG_83XX_PCICLK -# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred" -# endif /* CONFIG_83XX_PCICLK */ - - /* PCI Host Mode */ - if (!(im->reset.rcwh & RCWH_PCIHOST)) { - /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH - * the im->reset.rcwhr PCI Host Mode is disabled - * FIXME: findout if there is a way to issue some warning */ - return -2; - } - if (im->clk.spmr & SPMR_CKID) { - /* PCI Clock is half CONFIG_83XX_CLKIN */ - pci_sync_in = CONFIG_83XX_CLKIN / 2; - } - else { - pci_sync_in = CONFIG_83XX_CLKIN; - } - -#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */ - -# ifdef CONFIG_83XX_CLKIN -# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred" -# endif /* CONFIG_83XX_CLKIN */ -# ifndef CONFIG_83XX_PCICLK -# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file" -# endif /* CONFIG_83XX_PCICLK */ - - /* PCI Agent Mode */ - if (im->reset.rcwh & RCWH_PCIHOST) { - /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH - * the im->reset.rcwhr PCI Host Mode is enabled */ - return -3; - } - pci_sync_in = CONFIG_83XX_PCICLK; - -#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */ - - /* we have up to date pci_sync_in */ - spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); - clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); - - if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) { - csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2; - } - else { - csb_clk = pci_sync_in * spmf * (1 + clkin_div); - } - - sccr = im->clk.sccr; - switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { - case 0: - tsec1_clk = 0; - break; - case 1: - tsec1_clk = csb_clk; - break; - case 2: - tsec1_clk = csb_clk / 2; - break; - case 3: - tsec1_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_TSEC1CM value */ - return -4; - } - - switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { - case 0: - tsec2_clk = 0; - break; - case 1: - tsec2_clk = csb_clk; - break; - case 2: - tsec2_clk = csb_clk / 2; - break; - case 3: - tsec2_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_TSEC2CM value */ - return -5; - } - i2c_clk = tsec2_clk; - - switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { - case 0: - enc_clk = 0; - break; - case 1: - enc_clk = csb_clk; - break; - case 2: - enc_clk = csb_clk / 2; - break; - case 3: - enc_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_ENCCM value */ - return -6; - } - - switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { - case 0: - usbmph_clk = 0; - break; - case 1: - usbmph_clk = csb_clk; - break; - case 2: - usbmph_clk = csb_clk / 2; - break; - case 3: - usbmph_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_USBMPHCM value */ - return -7; - } - - switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { - case 0: - usbdr_clk = 0; - break; - case 1: - usbdr_clk = csb_clk; - break; - case 2: - usbdr_clk = csb_clk / 2; - break; - case 3: - usbdr_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_USBDRCM value */ - return -8; - } - - if (usbmph_clk != 0 - && usbdr_clk != 0 - && usbmph_clk != usbdr_clk ) { - /* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */ - return -9; - } - - lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); - lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; - switch (lcrr) { - case 2: - case 4: - case 8: - lclk_clk = lbiu_clk / lcrr; - break; - default: - /* unknown lcrr */ - return -10; - } - - ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); - - corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; - corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); - if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) { - /* corecnf_tab_index is too high, possibly worng value */ - return -11; - } - switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) { - case _byp: - case _x1: - case _1x: - core_clk = csb_clk; - break; - case _1_5x: - core_clk = (3 * csb_clk) / 2; - break; - case _2x: - core_clk = 2 * csb_clk; - break; - case _2_5x: - core_clk = ( 5 * csb_clk) / 2; - break; - case _3x: - core_clk = 3 * csb_clk; - break; - default: - /* unkown core to csb ratio */ - return -12; - } - - gd->csb_clk = csb_clk ; - gd->tsec1_clk = tsec1_clk ; - gd->tsec2_clk = tsec2_clk ; - gd->core_clk = core_clk ; - gd->usbmph_clk = usbmph_clk; - gd->usbdr_clk = usbdr_clk ; - gd->i2c_clk = i2c_clk ; - gd->enc_clk = enc_clk ; - gd->lbiu_clk = lbiu_clk ; - gd->lclk_clk = lclk_clk ; - gd->ddr_clk = ddr_clk ; - gd->pci_clk = pci_sync_in; - - gd->cpu_clk = gd->core_clk; - gd->bus_clk = gd->lbiu_clk; - return 0; -} - -/******************************************** - * get_bus_freq - * return system bus freq in Hz - *********************************************/ -ulong get_bus_freq (ulong dummy) -{ - DECLARE_GLOBAL_DATA_PTR; - return gd->csb_clk; -} - -int print_clock_conf (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - printf("Clock configuration:\n"); - printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000); - printf(" Core: %4d MHz\n",gd->core_clk/1000000); - debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000); - printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000); - debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000); - debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000); - debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000); - debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000); - debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000); - debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000); - - return 0; -} diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S deleted file mode 100644 index fb001a6..0000000 --- a/cpu/mpc83xx/start.S +++ /dev/null @@ -1,1093 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000, 2001,2002 Wolfgang Denk - * Copyright 2004 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards - */ - -#include -#include -#include - -#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "MPC83XX" -#endif - -/* We don't want the MMU yet. - */ -#undef MSR_KERNEL - -/* - * Floating Point enable, Machine Check and Recoverable Interr. - */ -#ifdef DEBUG -#define MSR_KERNEL (MSR_FP|MSR_RI) -#else -#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) -#endif - -/* - * Set up GOT: Global Offset Table - * - * Use r14 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * Version string - must be in data segment because MPC83xx uses the - * first 256 bytes for the Hard Reset Configuration Word table (see - * below). Similarly, can't have the U-Boot Magic Number as the first - * thing in the image - don't know how this will affect the image tools, - * but I guess I'll find out soon. - */ - .data - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii " ", CONFIG_IDENT_STRING, "\0" - - .text -#define _HRCW_TABLE_ENTRY(w) \ - .fill 8,1,(((w)>>24)&0xff); \ - .fill 8,1,(((w)>>16)&0xff); \ - .fill 8,1,(((w)>> 8)&0xff); \ - .fill 8,1,(((w) )&0xff) - - _HRCW_TABLE_ENTRY(CFG_HRCW_LOW) - _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH) - - -#ifndef CONFIG_DEFAULT_IMMR -#error CONFIG_DEFAULT_IMMR must be defined -#endif /* CFG_DEFAULT_IMMR */ -#ifndef CFG_IMMRBAR -#define CFG_IMMRBAR CONFIG_DEFAULT_IMMR -#endif /* CFG_IMMRBAR */ - -/* - * After configuration, a system reset exception is executed using the - * vector at offset 0x100 relative to the base set by MSR[IP]. If - * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the - * base address is 0xfff00000. In the case of a Power On Reset or Hard - * Reset, the value of MSR[IP] is determined by the CIP field in the - * HRCW. - * - * Other bits in the HRCW set up the Base Address and Port Size in BR0. - * This determines the location of the boot ROM (flash or EPROM) in the - * processor's address space at boot time. As long as the HRCW is set up - * so that we eventually end up executing the code below when the - * processor executes the reset exception, the actual values used should - * not matter. - * - * Once we have got here, the address mask in OR0 is cleared so that the - * bottom 32K of the boot ROM is effectively repeated all throughout the - * processor's address space, after which we can jump to the absolute - * address at which the boot ROM was linked at compile time, and proceed - * to initialise the memory controller without worrying if the rug will - * be pulled out from under us, so to speak (it will be fine as long as - * we configure BR0 with the same boot ROM link address). - */ - . = EXC_OFF_SYS_RESET - - .globl _start -_start: /* time t 0 */ - li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/ - nop - b boot_cold - - . = EXC_OFF_SYS_RESET + 0x10 - - .globl _start_warm -_start_warm: - li r21, BOOTFLAG_WARM /* Software reboot */ - b boot_warm - - -boot_cold: /* time t 3 */ - lis r4, CONFIG_DEFAULT_IMMR@h - nop -boot_warm: /* time t 5 */ - mfmsr r5 /* save msr contents */ - lis r3, CFG_IMMRBAR@h - ori r3, r3, CFG_IMMRBAR@l - stw r3, IMMRBAR(r4) - - /* Initialise the E300 processor core */ - /*------------------------------------------*/ - - bl init_e300_core - -#ifndef CFG_RAMBOOT - - /* Inflate flash location so it appears everywhere, calculate */ - /* the absolute address in final location of the FLASH, jump */ - /* there and deflate the flash size back to minimal size */ - /*------------------------------------------------------------*/ - bl map_flash_by_law1 - lis r4, (CFG_MONITOR_BASE)@h - ori r4, r4, (CFG_MONITOR_BASE)@l - addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r5 - blr -in_flash: -#if 1 /* Remapping flash with LAW0. */ - bl remap_flash_by_law0 -#endif -#endif /* CFG_RAMBOOT */ - - bl setup_stack_in_data_cache_on_r1 - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable & stack humble */ - /*------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - lis r3, CFG_IMMRBAR@h - /* run low-level CPU init code (in Flash)*/ - bl cpu_init_f - - /* r3: BOOTFLAG */ - mr r3, r21 - /* run 1st part of board init code (in Flash)*/ - bl board_init_f - -/* - * Vector Table - */ - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ -#ifndef FIXME - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) -#endif - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) -#ifdef DEBUG - . = 0x1300 - /* - * This exception occurs when the program counter matches the - * Instruction Address Breakpoint Register (IABR). - * - * I want the cpu to halt if this occurs so I can hunt around - * with the debugger and look at things. - * - * When DEBUG is defined, both machine check enable (in the MSR) - * and checkstop reset enable (in the reset mode register) are - * turned off and so a checkstop condition will result in the cpu - * halting. - * - * I force the cpu into a checkstop condition by putting an illegal - * instruction here (at least this is the theory). - * - * well - that didnt work, so just do an infinite loop! - */ -1: b 1b -#else - STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) -#endif - STD_EXCEPTION(0x1400, SMI, UnknownException) - - STD_EXCEPTION(0x1500, Trap_15, UnknownException) - STD_EXCEPTION(0x1600, Trap_16, UnknownException) - STD_EXCEPTION(0x1700, Trap_17, UnknownException) - STD_EXCEPTION(0x1800, Trap_18, UnknownException) - STD_EXCEPTION(0x1900, Trap_19, UnknownException) - STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) - STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) - STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) - STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) - STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) - STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) - STD_EXCEPTION(0x2000, Trap_20, UnknownException) - STD_EXCEPTION(0x2100, Trap_21, UnknownException) - STD_EXCEPTION(0x2200, Trap_22, UnknownException) - STD_EXCEPTION(0x2300, Trap_23, UnknownException) - STD_EXCEPTION(0x2400, Trap_24, UnknownException) - STD_EXCEPTION(0x2500, Trap_25, UnknownException) - STD_EXCEPTION(0x2600, Trap_26, UnknownException) - STD_EXCEPTION(0x2700, Trap_27, UnknownException) - STD_EXCEPTION(0x2800, Trap_28, UnknownException) - STD_EXCEPTION(0x2900, Trap_29, UnknownException) - STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) - STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) - STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) - STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) - STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) - STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - . = 0x3000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* - * This code initialises the E300 processor core - * (conforms to PowerPC 603e spec) - * Note: expects original MSR contents to be in r5. - */ - .globl init_e300_core -init_e300_core: /* time t 10 */ - /* Initialize machine status; enable machine check interrupt */ - /*-----------------------------------------------------------*/ - - li r3, MSR_KERNEL /* Set ME and RI flags */ - rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ -#ifdef DEBUG - rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ -#endif - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - - lis r3, CFG_IMMRBAR@h -#if defined(CONFIG_WATCHDOG) - /* Initialise the Wathcdog values and reset it (if req) */ - /*------------------------------------------------------*/ - lis r4, CFG_WATCHDOG_VALUE - ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) - stw r4, SWCRR(r3) - - /* and reset it */ - - li r4, 0x556C - sth r4, SWSRR@l(r3) - li r4, 0xAA39 - sth r4, SWSRR@l(r3) -#else - /* Disable Wathcdog */ - /*-------------------*/ - xor r4, r4, r4 - stw r4, SWCRR(r3) -#endif /* CONFIG_WATCHDOG */ - - /* Initialize the Hardware Implementation-dependent Registers */ - /* HID0 also contains cache control */ - /*------------------------------------------------------*/ - - lis r3, CFG_HID0_INIT@h - ori r3, r3, CFG_HID0_INIT@l - SYNC - mtspr HID0, r3 - - lis r3, CFG_HID0_FINAL@h - ori r3, r3, CFG_HID0_FINAL@l - SYNC - mtspr HID0, r3 - - lis r3, CFG_HID2@h - ori r3, r3, CFG_HID2@l - SYNC - mtspr HID2, r3 - - /* clear all BAT's */ - /*----------------------------------*/ - - xor r0, r0, r0 - mtspr DBAT0U, r0 - mtspr DBAT0L, r0 - mtspr DBAT1U, r0 - mtspr DBAT1L, r0 - mtspr DBAT2U, r0 - mtspr DBAT2L, r0 - mtspr DBAT3U, r0 - mtspr DBAT3L, r0 - mtspr IBAT0U, r0 - mtspr IBAT0L, r0 - mtspr IBAT1U, r0 - mtspr IBAT1L, r0 - mtspr IBAT2U, r0 - mtspr IBAT2L, r0 - mtspr IBAT3U, r0 - mtspr IBAT3L, r0 - SYNC - - /* invalidate all tlb's - * - * From the 603e User Manual: "The 603e provides the ability to - * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) - * instruction invalidates the TLB entry indexed by the EA, and - * operates on both the instruction and data TLBs simultaneously - * invalidating four TLB entries (both sets in each TLB). The - * index corresponds to bits 15-19 of the EA. To invalidate all - * entries within both TLBs, 32 tlbie instructions should be - * issued, incrementing this field by one each time." - * - * "Note that the tlbia instruction is not implemented on the - * 603e." - * - * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 - * incrementing by 0x1000 each time. The code below is sort of - * based on code in "flush_tlbs" from arch/ppc/kernel/head.S - * - */ - - li r3, 32 - mtctr r3 - li r3, 0 -1: tlbie r3 - addi r3, r3, 0x1000 - bdnz 1b - SYNC - - /* Done! */ - /*------------------------------*/ - blr - -/* Cache functions. - * - * Note: requires that all cache bits in - * HID0 are in the low half word. - */ - .globl icache_enable -icache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_ICE - lis r4, 0 - ori r4, r4, HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_disable -icache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_ICE|HID0_ILOCK - andc r3, r3, r4 - ori r4, r3, HID0_ICFI - isync - mtspr HID0, r4 /* sets invalidate, clears enable and lock*/ - isync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl icache_status -icache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_ICE_SHIFT, 31, 31 - blr - - .globl dcache_enable -dcache_enable: - mfspr r3, HID0 - ori r3, r3, HID0_ENABLE_DATA_CACHE - lis r4, 0 - ori r4, r4, HID0_LOCK_DATA_CACHE - andc r3, r3, r4 - ori r4, r3, HID0_LOCK_INSTRUCTION_CACHE - sync - mtspr HID0, r4 /* sets enable and invalidate, clears lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_disable -dcache_disable: - mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_ENABLE_DATA_CACHE|HID0_LOCK_DATA_CACHE - andc r3, r3, r4 - ori r4, r3, HID0_INVALIDATE_DATA_CACHE - sync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ - sync - mtspr HID0, r3 /* clears invalidate */ - blr - - .globl dcache_status -dcache_status: - mfspr r3, HID0 - rlwinm r3, r3, HID0_DCE_SHIFT, 31, 31 - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -/*-------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) - * + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r14, r14, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - la r8,-4(r4) - la r7,-4(r3) - - /* copy */ -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - - addi r0,r5,3 - srwi. r0,r0,2 - mtctr r0 - la r8,-4(r4) - la r7,-4(r3) - - /* and compare */ -20: lwzu r20,4(r8) - lwzu r21,4(r7) - xor. r22, r20, r21 - bne 30f - bdnz 20b - b 4f - - /* compare failed */ -30: li r3, 0 - blr - -2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: - bl un_setup_stack_in_data_cache - mr r7, r3 - mr r8, r4 - bl dcache_disable - mr r3, r7 - mr r4, r8 - - cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mfspr r7,HID0 /* don't do dcbst if dcache is disabled*/ - rlwinm r7,r7,HID0_DCE_SHIFT,31,31 - cmpwi r7,0 - beq 9f - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ -9: mfspr r7,HID0 /* don't do icbi if icache is disabled */ - rlwinm r7,r7,HID0_DCE_SHIFT,31,31 - cmpwi r7,0 - beq 7f - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r14 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - add r0,r0,r11 - stw r0,0(r3) - bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ -2: li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) -#if defined(CONFIG_HYMOD) - /* - * For HYMOD - the environment is the very last item in flash. - * The real .bss stops just before environment starts, so only - * clear up to that point. - * - * taken from mods for FADS board - */ - lwz r4,GOT(environment) -#else - lwz r4,GOT(_end) -#endif - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mfmsr r3 /* now that the vectors have */ - lis r7, MSR_IP@h /* relocated into low memory */ - ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ - andc r3, r3, r7 /* (if it was on) */ - SYNC /* Some chip revs need this... */ - mtmsr r3 - SYNC - - mtlr r4 /* restore link register */ - blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr - -#ifdef CFG_INIT_RAM_LOCK -.globl unlock_ram_in_cache -unlock_ram_in_cache: - /* invalidate the INIT_RAM section */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2,512 - mtctr r2 -1: icbi r0, r3 - dcbi r0, r3 - addi r3, r3, 32 - bdnz 1b - sync /* Wait for all icbi to complete on bus */ - isync - blr -#endif - -map_flash_by_law1: - /* When booting from ROM (Flash or EPROM), clear the */ - /* Address Mask in OR0 so ROM appears everywhere */ - /*----------------------------------------------------*/ - lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */ - lwz r4, OR0@l(r3) - li r5, 0x7fff /* r5 <= 0x00007FFFF */ - and r4, r4, r5 - stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ - - /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, - * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] - * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot - * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is - * 0xFF800. From the hard resetting to here, the processor fetched and - * executed the instructions one by one. There is not absolutely - * jumping happened. Laterly, the u-boot code has to do an absolutely - * jumping to tell the CPU instruction fetching component what the - * u-boot TEXT base address is. Because the TEXT base resides in the - * boot ROM memory space, to garantee the code can run smoothly after - * that jumping, we must map in the entire boot ROM by Local Access - * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting - * address for boot ROM, such as 0xFE000000. In this case, the default - * LBIU Local Access Widow 0 will not cover this memory space. So, we - * need another window to map in it. - */ - lis r4, (CFG_FLASH_BASE)@h - ori r4, r4, (CFG_FLASH_BASE)@l - stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */ - lis r4, (0x80000016)@h - ori r4, r4, (0x80000016)@l - stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ - blr - - /* Though all the LBIU Local Access Windows and LBC Banks will be - * initialized in the C code, we'd better configure boot ROM's - * window 0 and bank 0 correctly at here. - */ -remap_flash_by_law0: - /* Initialize the BR0 with the boot ROM starting address. */ - lwz r4, BR0(r3) - li r5, 0x7FFF - and r4, r4, r5 - lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h - ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l - or r5, r5, r4 - stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ - - lwz r4, OR0(r3) - lis r5, 0xFF80 /* 8M */ - or r4, r4, r5 - stw r4, OR0(r3) /* OR0 <= OR0 | 0xFF800000 */ - - lis r4, (CFG_FLASH_BASE)@h - ori r4, r4, (CFG_FLASH_BASE)@l - stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */ - - lis r4, (0x80000016)@h - ori r4, r4, (0x80000016)@l - stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 8MB Flash Size */ - - xor r4, r4, r4 - stw r4, LBLAWBAR1(r3) - stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ - blr - -setup_stack_in_data_cache_on_r1: - lis r3, (CFG_IMMRBAR)@h - - /* setup D-BAT for the D-Cache (with out real memory backup) */ - - lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h - mtspr DBAT0U, r4 - ori r4, r4, 0x0002 - mtspr DBAT0L, r4 - isync - -#if 0 - /* Enable MMU */ - mfmsr r4 - ori r4, r4, (MSR_DR | MSR_IR)@l - mtmsr r4 -#endif - - /* Enable and invalidate data cache. */ - mfspr r4, HID0 - mr r5, r4 - ori r4, r4, HID0_DCE | HID0_DCI - ori r5, r5, HID0_DCE - sync - mtspr HID0, r4 - mtspr HID0, r5 - sync - - /* Allocate Initial RAM in data cache.*/ - li r0, 0 - lis r4, (CFG_INIT_RAM_ADDR)@h - ori r4, r4, (CFG_INIT_RAM_ADDR)@l - li r5, 128*8 /* 128*8*32=32Kb */ - mtctr r5 -1: - dcbz r0, r4 - addi r4, r4, 32 - bdnz 1b - isync - - /* Lock all the D-cache, basically leaving the reset of the program without dcache */ - mfspr r4, HID0 - ori r4, r4, (HID0_DLOCK)@l - sync - mtspr HID0 , r4 - - /* setup the stack pointer in r1 */ - lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l - li r0, 0 /* Make room for stack frame header and */ - - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - blr - -un_setup_stack_in_data_cache: - blr - mr r14, r4 - mr r15, r5 - - - lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h - mtspr DBAT0U, r4 - ori r4, r4, 0x0002 - mtspr DBAT0L, r4 - isync - - /* un lock all the D-cache */ - mfspr r4, HID0 - lis r5, (~(HID0_DLOCK))@h - ori r5, r5, (~(HID0_DLOCK))@l - and r4, r4, r5 - sync - mtspr HID0 , r4 - - /* Re - Allocate Initial RAM in data cache.*/ - li r0, 0 - lis r4, (CFG_INIT_RAM_ADDR)@h - ori r4, r4, (CFG_INIT_RAM_ADDR)@l - li r5, 128*8 /* 128*8*32=32Kb */ - mtctr r5 -1: - dcbz r0, r4 - addi r4, r4, 32 - bdnz 1b - isync - - mflr r16 - bl dcache_disable - mtlr r16 - - blr - -#if 0 -#define GREEN_LIGHT 0x2B0D4046 -#define RED_LIGHT 0x250D4046 -#define LIB_CNT 0x4FFF - -/* - * Lib Light - */ - - .globl liblight -liblight: - lis r3, CFG_IMMRBAR@h - ori r3, r3, CFG_IMMRBAR@l - li r4, 0x3002 - mtmsr r4 - xor r4, r4, r4 - mtspr HID0, r4 - mtspr HID2, r4 - lis r4, 0xF8000000@h - ori r4, r4, 0xF8000000@l - stw r4, LBLAWBAR1(r3) - lis r4, 0x8000000E@h - ori r4, r4, 0x8000000E@l - stw r4, LBLAWAR1(r3) - lis r4, 0xF8000801@h - ori r4, r4, 0xF8000801@l - stw r4, BR1(r3) - lis r4, 0xFFFFE8f0@h - ori r4, r4, 0xFFFFE8f0@l - stw r4, OR1(r3) - - lis r4, 0xF8000000@h - ori r4, r4, 0xF8000000@l - lis r5, GREEN_LIGHT@h - ori r5, r5, GREEN_LIGHT@l - lis r6, RED_LIGHT@h - ori r6, r6, RED_LIGHT@l - lis r7, LIB_CNT@h - ori r7, r7, LIB_CNT@l - -1: - stw r5, 0(r4) - mtctr r7 -2: bdnz 2b - stw r6, 0(r4) - mtctr r7 -3: bdnz 3b - b 1b - -#endif diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c deleted file mode 100644 index c7a5638..0000000 --- a/cpu/mpc83xx/traps.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * linux/arch/ppc/kernel/traps.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - */ - -/* - * This file handles the architecture-dependent parts of hardware - * exceptions - */ - -#include -#include -#include -#include - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) - -/* - * Trap & Exception support - */ - -void -print_backtrace(unsigned long *sp) -{ - DECLARE_GLOBAL_DATA_PTR; - int cnt = 0; - unsigned long i; - - puts ("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - putc ('\n'); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - putc ('\n'); -} - -void show_regs(struct pt_regs * regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - putc ('\n'); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) { - putc ('\n'); - } - } -} - - -void -_exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -#ifdef CONFIG_PCI -void dump_pci (void) -{ -/* - volatile immap_t *immap = (immap_t *) CFG_IMMR; - printf ("PCI: err status %x err mask %x err ctrl %x\n", - le32_to_cpu (immap->im_pci.pci_esr), - le32_to_cpu (immap->im_pci.pci_emr), - le32_to_cpu (immap->im_pci.pci_ecr)); - printf (" error address %x error data %x ctrl %x\n", - le32_to_cpu (immap->im_pci.pci_eacr), - le32_to_cpu (immap->im_pci.pci_edcr), - le32_to_cpu (immap->im_pci.pci_eccr)); -*/ -} -#endif - -void -MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ -#ifdef CONFIG_PCI -#if 0 - volatile immap_t *immap = (immap_t *)CFG_IMMR; -#ifdef DEBUG - dump_pci(); -#endif - /* clear the error in the error status register */ - if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) { - immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP); - return; - } -#endif -#endif /* CONFIG_PCI */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - puts ("Machine check in kernel mode.\n" - "Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - puts ("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - puts ("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - puts ("Data parity signal\n"); - break; - case (0x80000000>>15): - puts ("Address parity signal\n"); - break; - default: - puts ("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); -#ifdef CONFIG_PCI - dump_pci(); -#endif - panic("machine check"); -} - -void -AlignmentException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void -ProgramCheckException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void -SoftEmuException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void -UnknownException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -void -DebugException(struct pt_regs *regs) -{ - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int -addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile deleted file mode 100644 index 5298dc1..0000000 --- a/cpu/mpc85xx/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2002,2003 Motorola Inc. -# Xianghua Xiao,X.Xiao@motorola.com -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o resetvec.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o -OBJS = $(COBJS) - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c deleted file mode 100644 index aa8a5a5..0000000 --- a/cpu/mpc85xx/commproc.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Adapted for Motorola MPC8560 chips - * Xianghua Xiao - * - * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's - * copyright notice: - * - * General Purpose functions for the global management of the - * 8220 Communication Processor Module. - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) - * 2.3.99 Updates - * Copyright (c) 2003 Motorola,Inc. - * - * In addition to the individual control of the communication - * channels, there are a few functions that globally affect the - * communication processor. - * - * Buffer descriptors must be allocated from the dual ported memory - * space. The allocator for that is here. When the communication - * process is reset, we reclaim the memory available. There is - * currently no deallocator for this memory. - */ -#include -#include - -#if defined(CONFIG_CPM2) -/* - * because we have stack and init data in dual port ram - * we must reduce the size - */ -#undef CPM_DATAONLY_SIZE -#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) - -void -m8560_cpm_reset(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ulong count; - - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - - /* Reclaim the DP memory for our use. - */ - gd->dp_alloc_base = CPM_DATAONLY_BASE; - gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE; - - /* - * Reset CPM - */ - immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST; - count = 0; - do { /* Spin until command processed */ - __asm__ __volatile__ ("eieio"); - } while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000); -} - -/* Allocate some memory from the dual ported ram. - * To help protocols with object alignment restrictions, we do that - * if they ask. - */ -uint -m8560_cpm_dpalloc(uint size, uint align) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *)CFG_IMMR; - uint retloc; - uint align_mask, off; - uint savebase; - - align_mask = align - 1; - savebase = gd->dp_alloc_base; - - if ((off = (gd->dp_alloc_base & align_mask)) != 0) - gd->dp_alloc_base += (align - off); - - if ((off = size & align_mask) != 0) - size += align - off; - - if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) { - gd->dp_alloc_base = savebase; - panic("m8560_cpm_dpalloc: ran out of dual port ram!"); - } - - retloc = gd->dp_alloc_base; - gd->dp_alloc_base += size; - - memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size); - - return(retloc); -} - -/* We also own one page of host buffer space for the allocation of - * UART "fifos" and the like. - */ -uint -m8560_cpm_hostalloc(uint size, uint align) -{ - /* the host might not even have RAM yet - just use dual port RAM */ - return (m8560_cpm_dpalloc(size, align)); -} - -/* Set a baud rate generator. This needs lots of work. There are - * eight BRGs, which can be connected to the CPM channels or output - * as clocks. The BRGs are in two different block of internal - * memory mapped space. - * The baud rate clock is the system clock divided by something. - * It was set up long ago during the initial boot phase and is - * is given to us. - * Baud rate clocks are zero-based in the driver code (as that maps - * to port numbers). Documentation uses 1-based numbering. - */ -#define BRG_INT_CLK gd->brg_clk -#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16) - -/* This function is used by UARTS, or anything else that uses a 16x - * oversampled clock. - */ -void -m8560_cpm_setbrg(uint brg, uint rate) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile uint *bp; - - /* This is good enough to get SMCs running..... - */ - if (brg < 4) { - bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); - } - else { - bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); - brg -= 4; - } - bp += brg; - *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; -} - -/* This function is used to set high speed synchronous baud rate - * clocks. - */ -void -m8560_cpm_fastbrg(uint brg, uint rate, int div16) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile uint *bp; - - /* This is good enough to get SMCs running..... - */ - if (brg < 4) { - bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); - } - else { - bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); - brg -= 4; - } - bp += brg; - *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; - if (div16) - *bp |= CPM_BRG_DIV16; -} - -/* This function is used to set baud rate generators using an external - * clock source and 16x oversampling. - */ - -void -m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile uint *bp; - - if (brg < 4) { - bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); - } - else { - bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); - brg -= 4; - } - bp += brg; - *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; - if (pinsel == 0) - *bp |= CPM_BRG_EXTC_CLK3_9; - else - *bp |= CPM_BRG_EXTC_CLK5_15; -} - -#ifdef CONFIG_POST - -void post_word_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); - - *save_addr = a; -} - -ulong post_word_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); - - return *save_addr; -} - -#endif /* CONFIG_POST */ - -#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk deleted file mode 100644 index 6121074..0000000 --- a/cpu/mpc85xx/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2002,2003 Motorola Inc. -# Xianghua Xiao, X.Xiao@motorola.com -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi - -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 -ffixed-r29 -Wa,-me500 -msoft-float -mno-string diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c deleted file mode 100644 index f7fe22e..0000000 --- a/cpu/mpc85xx/cpu.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002, 2003 Motorola Inc. - * Xianghua Xiao (X.Xiao@motorola.com) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -int checkcpu (void) -{ - sys_info_t sysinfo; - uint lcrr; /* local bus clock ratio register */ - uint clkdiv; /* clock divider portion of lcrr */ - uint pvr, svr; - uint fam; - uint ver; - uint major, minor; - - svr = get_svr(); - ver = SVR_VER(svr); - major = SVR_MAJ(svr); - minor = SVR_MIN(svr); - - puts("CPU: "); - switch (ver) { - case SVR_8540: - puts("8540"); - break; - case SVR_8541: - puts("8541"); - break; - case SVR_8555: - puts("8555"); - break; - case SVR_8560: - puts("8560"); - break; - case SVR_8548: - puts("8548"); - break; - case SVR_8548_E: - puts("8548_E"); - break; - default: - puts("Unknown"); - break; - } - printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); - - pvr = get_pvr(); - fam = PVR_FAM(pvr); - ver = PVR_VER(pvr); - major = PVR_MAJ(pvr); - minor = PVR_MIN(pvr); - - printf("Core: "); - switch (fam) { - case PVR_FAM(PVR_85xx): - puts("E500"); - break; - default: - puts("Unknown"); - break; - } - printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); - - get_sys_info(&sysinfo); - - puts("Clock Configuration:\n"); - printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); - printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000); - printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); - -#if defined(CFG_LBC_LCRR) - lcrr = CFG_LBC_LCRR; -#else - { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc= &immap->im_lbc; - - lcrr = lbc->lcrr; - } -#endif - clkdiv = lcrr & 0x0f; - if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#ifdef CONFIG_MPC8548 - /* - * Yes, the entire PQ38 family use the same - * bit-representation for twice the clock divider values. - */ - clkdiv *= 2; -#endif - printf("LBC:%4lu MHz\n", - sysinfo.freqSystemBus / 1000000 / clkdiv); - } else { - printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); - } - - if (ver == SVR_8560) { - printf("CPM: %lu Mhz\n", - sysinfo.freqSystemBus / 1000000); - } - - puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - /* - * Initiate hard reset in debug control register DBCR0 - * Make sure MSR[DE] = 1 - */ - unsigned long val; - - val = mfspr(DBCR0); - val |= 0x70000000; - mtspr(DBCR0,val); - - return 1; -} - - -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk (void) -{ - - sys_info_t sys_info; - - get_sys_info(&sys_info); - return ((sys_info.freqSystemBus + 7L) / 8L); -} - - -#if defined(CONFIG_WATCHDOG) -void -watchdog_reset(void) -{ - int re_enable = disable_interrupts(); - reset_85xx_watchdog(); - if (re_enable) enable_interrupts(); -} - -void -reset_85xx_watchdog(void) -{ - /* - * Clear TSR(WIS) bit by writing 1 - */ - unsigned long val; - val = mfspr(tsr); - val |= 0x40000000; - mtspr(tsr, val); -} -#endif /* CONFIG_WATCHDOG */ - -#if defined(CONFIG_DDR_ECC) -void dma_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; - - dma->satr0 = 0x02c40000; - dma->datr0 = 0x02c40000; - asm("sync; isync; msync"); - return; -} - -uint dma_check(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; - volatile uint status = dma->sr0; - - /* While the channel is busy, spin */ - while((status & 4) == 4) { - status = dma->sr0; - } - - if (status != 0) { - printf ("DMA Error: status = %x\n", status); - } - return status; -} - -int dma_xfer(void *dest, uint count, void *src) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_dma_t *dma = &immap->im_dma; - - dma->dar0 = (uint) dest; - dma->sar0 = (uint) src; - dma->bcr0 = count; - dma->mr0 = 0xf000004; - asm("sync;isync;msync"); - dma->mr0 = 0xf000005; - asm("sync;isync;msync"); - return dma_check(); -} -#endif diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c deleted file mode 100644 index efde9cc..0000000 --- a/cpu/mpc85xx/cpu_init.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2003 Motorola Inc. - * Modified by Xianghua Xiao, X.Xiao@motorola.com - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_CPM2 -static void config_8560_ioports (volatile immap_t * immr) -{ - int portnum; - - for (portnum = 0; portnum < 4; portnum++) { - uint pmsk = 0, - ppar = 0, - psor = 0, - pdir = 0, - podr = 0, - pdat = 0; - iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; - iop_conf_t *eiopc = iopc + 32; - uint msk = 1; - - /* - * NOTE: - * index 0 refers to pin 31, - * index 31 refers to pin 0 - */ - while (iopc < eiopc) { - if (iopc->conf) { - pmsk |= msk; - if (iopc->ppar) - ppar |= msk; - if (iopc->psor) - psor |= msk; - if (iopc->pdir) - pdir |= msk; - if (iopc->podr) - podr |= msk; - if (iopc->pdat) - pdat |= msk; - } - - msk <<= 1; - iopc++; - } - - if (pmsk != 0) { - volatile ioport_t *iop = ioport_addr (immr, portnum); - uint tpmsk = ~pmsk; - - /* - * the (somewhat confused) paragraph at the - * bottom of page 35-5 warns that there might - * be "unknown behaviour" when programming - * PSORx and PDIRx, if PPARx = 1, so I - * decided this meant I had to disable the - * dedicated function first, and enable it - * last. - */ - iop->ppar &= tpmsk; - iop->psor = (iop->psor & tpmsk) | psor; - iop->podr = (iop->podr & tpmsk) | podr; - iop->pdat = (iop->pdat & tpmsk) | pdat; - iop->pdir = (iop->pdir & tpmsk) | pdir; - iop->ppar |= ppar; - } - } -} -#endif - -/* - * Breathe some life into the CPU... - * - * Set up the memory map - * initialize a bunch of registers - */ - -void cpu_init_f (void) -{ - DECLARE_GLOBAL_DATA_PTR; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *memctl = &immap->im_lbc; - extern void m8560_cpm_reset (void); - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - -#ifdef CONFIG_CPM2 - config_8560_ioports(immap); -#endif - - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ -#if defined(CFG_OR0_REMAP) - memctl->or0 = CFG_OR0_REMAP; -#endif -#if defined(CFG_OR1_REMAP) - memctl->or1 = CFG_OR1_REMAP; -#endif - - /* now restrict to preliminary range */ -#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) - memctl->br0 = CFG_BR0_PRELIM; - memctl->or0 = CFG_OR0_PRELIM; -#endif - -#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->or1 = CFG_OR1_PRELIM; - memctl->br1 = CFG_BR1_PRELIM; -#endif - -#if !defined(CONFIG_MPC85xx) -#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) - memctl->or2 = CFG_OR2_PRELIM; - memctl->br2 = CFG_BR2_PRELIM; -#endif -#endif - -#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) - memctl->or3 = CFG_OR3_PRELIM; - memctl->br3 = CFG_BR3_PRELIM; -#endif - -#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) - memctl->or4 = CFG_OR4_PRELIM; - memctl->br4 = CFG_BR4_PRELIM; -#endif - -#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) - memctl->or5 = CFG_OR5_PRELIM; - memctl->br5 = CFG_BR5_PRELIM; -#endif - -#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) - memctl->or6 = CFG_OR6_PRELIM; - memctl->br6 = CFG_BR6_PRELIM; -#endif - -#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) - memctl->or7 = CFG_OR7_PRELIM; - memctl->br7 = CFG_BR7_PRELIM; -#endif - -#if defined(CONFIG_CPM2) - m8560_cpm_reset(); -#endif -} - - -/* - * Initialize L2 as cache. - * - * The newer 8548, etc, parts have twice as much cache, but - * use the same bit-encoding as the older 8555, etc, parts. - * - * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()? - */ - -int cpu_init_r(void) -{ -#if defined(CONFIG_L2_CACHE) - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache; - volatile uint cache_ctl; - uint svr, ver; - - svr = get_svr(); - ver = SVR_VER(svr); - - asm("msync;isync"); - cache_ctl = l2cache->l2ctl; - - switch (cache_ctl & 0x30000000) { - case 0x20000000: - if (ver == SVR_8548 || ver == SVR_8548_E) { - printf ("L2 cache 512KB:"); - } else { - printf ("L2 cache 256KB:"); - } - break; - case 0x00000000: - case 0x10000000: - case 0x30000000: - default: - printf ("L2 cache unknown size (0x%08x)\n", cache_ctl); - return -1; - } - - asm("msync;isync"); - l2cache->l2ctl = 0x68000000; /* invalidate */ - cache_ctl = l2cache->l2ctl; - asm("msync;isync"); - - l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */ - cache_ctl = l2cache->l2ctl; - asm("msync;isync"); - - printf(" enabled\n"); -#else - printf("L2 cache: disabled\n"); -#endif - - return 0; -} diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c deleted file mode 100644 index d15d242..0000000 --- a/cpu/mpc85xx/ether_fcc.c +++ /dev/null @@ -1,473 +0,0 @@ -/* - * MPC8560 FCC Fast Ethernet - * Copyright (c) 2003 Motorola,Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MPC8560 FCC Fast Ethernet - * Basic ET HW initialization and packet RX/TX routines - * - * This code will not perform the IO port configuration. This should be - * done in the iop_conf_t structure specific for the board. - * - * TODO: - * add a PHY driver to do the negotiation - * reflect negotiation results in FPSMR - * look for ways to configure the board specific stuff elsewhere, eg. - * config_xxx.h or the board directory - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) -#include -#endif - -#if defined(CONFIG_CPM2) - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \ - defined(CONFIG_NET_MULTI) - -static struct ether_fcc_info_s -{ - int ether_index; - int proff_enet; - ulong cpm_cr_enet_sblock; - ulong cpm_cr_enet_page; - ulong cmxfcr_mask; - ulong cmxfcr_value; -} - ether_fcc_info[] = -{ -#ifdef CONFIG_ETHER_ON_FCC1 -{ - 0, - PROFF_FCC1, - CPM_CR_FCC1_SBLOCK, - CPM_CR_FCC1_PAGE, - CFG_CMXFCR_MASK1, - CFG_CMXFCR_VALUE1 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC2 -{ - 1, - PROFF_FCC2, - CPM_CR_FCC2_SBLOCK, - CPM_CR_FCC2_PAGE, - CFG_CMXFCR_MASK2, - CFG_CMXFCR_VALUE2 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC3 -{ - 2, - PROFF_FCC3, - CPM_CR_FCC3_SBLOCK, - CPM_CR_FCC3_PAGE, - CFG_CMXFCR_MASK3, - CFG_CMXFCR_VALUE3 -}, -#endif -}; - -/*---------------------------------------------------------------------*/ - -/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ -#define PKT_MAXDMA_SIZE 1520 - -/* The FCC stores dest/src/type, data, and checksum for receive packets. */ -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 - -/* Maximum input buffer size. Must be a multiple of 32. */ -#define PKT_MAXBLR_SIZE 1536 - -#define TOUT_LOOP 1000000 - -#define TX_BUF_CNT 2 - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FCC Ethernet Tx and Rx buffer descriptors. - * Provide for Double Buffering - * Note: PKTBUFSRX is defined in net.h - */ - -typedef volatile struct rtxbd { - cbd_t rxbd[PKTBUFSRX]; - cbd_t txbd[TX_BUF_CNT]; -} RTXBD; - -/* Good news: the FCC supports external BDs! */ -#ifdef __GNUC__ -static RTXBD rtx __attribute__ ((aligned(8))); -#else -#error "rtx must be 64-bit aligned" -#endif - -#undef ET_DEBUG - -static int fec_send(struct eth_device* dev, volatile void *packet, int length) -{ - int i = 0; - int result = 0; - - if (length <= 0) { - printf("fec: bad packet size: %d\n", length); - goto out; - } - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - printf("fec: tx buffer not ready\n"); - goto out; - } - } - - rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx.txbd[txIdx].cbd_datlen = length; - rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \ - BD_ENET_TX_TC | BD_ENET_TX_PAD); - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - printf("fec: tx error\n"); - goto out; - } - } - -#ifdef ET_DEBUG - printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc); - printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length); - for(i=0;i<(length/16 + 1);i++) { - printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\ - *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \ - *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3)); - } -#endif - - /* return only status bits */ - result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; - txIdx = (txIdx + 1) % TX_BUF_CNT; - -out: - return result; -} - -static int fec_recv(struct eth_device* dev) -{ - int length; - - for (;;) - { - if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - length = rtx.rxbd[rxIdx].cbd_datlen; - - if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { - printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); - } - else { - /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[rxIdx], length - 4); - } - - - /* Give the buffer back to the FCC. */ - rtx.rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } - else { - rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - - -static int fec_init(struct eth_device* dev, bd_t *bis) -{ - struct ether_fcc_info_s * info = dev->priv; - int i; - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp); - fcc_enet_t *pram_ptr; - unsigned long mem_addr; - -#if 0 - mii_discover_phy(); -#endif - - /* 28.9 - (1-2): ioports have been set up already */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */ - immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | - info->cmxfcr_value; - - /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ - if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } - - /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ - if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; - } else if (info->ether_index == 1){ - immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; - } else if (info->ether_index == 2){ - immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; - } - - /* 28.9 - (6): FDSR: Ethernet Syn */ - if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555; - } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555; - } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555; - } - - /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ - rxIdx = 0; - txIdx = 0; - - /* Setup Receiver Buffer Descriptors */ - for (i = 0; i < PKTBUFSRX; i++) - { - rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx.rxbd[i].cbd_datlen = 0; - rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; - } - rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* Setup Ethernet Transmitter Buffer Descriptors */ - for (i = 0; i < TX_BUF_CNT; i++) - { - rtx.txbd[i].cbd_sc = 0; - rtx.txbd[i].cbd_datlen = 0; - rtx.txbd[i].cbd_bufaddr = 0; - } - rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* 28.9 - (7): initialize parameter ram */ - pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]); - - /* clear whole structure to make sure all reserved fields are zero */ - memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); - - /* - * common Parameter RAM area - * - * Allocate space in the reserved FCC area of DPRAM for the - * internal buffers. No one uses this space (yet), so we - * can do this. Later, we will add resource management for - * this area. - * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560 - * 0x9000 for MPC8541, MPC8555 - */ - mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); - pram_ptr->fen_genfcc.fcc_riptr = mem_addr; - pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; - /* - * Set maximum bytes per receive buffer. - * It must be a multiple of 32. - */ - pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */ - /* localbus SDRAM should be preferred */ - pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); - pram_ptr->fen_genfcc.fcc_rbdstat = 0; - pram_ptr->fen_genfcc.fcc_rbdlen = 0; - pram_ptr->fen_genfcc.fcc_rdptr = 0; - /* localbus SDRAM should be preferred */ - pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); - pram_ptr->fen_genfcc.fcc_tbdstat = 0; - pram_ptr->fen_genfcc.fcc_tbdlen = 0; - pram_ptr->fen_genfcc.fcc_tdptr = 0; - - /* protocol-specific area */ - pram_ptr->fen_statbuf = 0x0; - pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ - pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ - pram_ptr->fen_crcec = 0; - pram_ptr->fen_alec = 0; - pram_ptr->fen_disfc = 0; - pram_ptr->fen_retlim = 15; /* Retry limit threshold */ - pram_ptr->fen_retcnt = 0; - pram_ptr->fen_pper = 0; - pram_ptr->fen_boffcnt = 0; - pram_ptr->fen_gaddrh = 0; - pram_ptr->fen_gaddrl = 0; - pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ - /* - * Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - * So far we have only been given one Ethernet address. We make - * it unique by setting a few bits in the upper byte of the - * non-static part of the address. - */ -#define ea eth_get_dev()->enetaddr - pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - pram_ptr->fen_ibdcount = 0; - pram_ptr->fen_ibdstart = 0; - pram_ptr->fen_ibdend = 0; - pram_ptr->fen_txlen = 0; - pram_ptr->fen_iaddrh = 0; /* disable hash */ - pram_ptr->fen_iaddrl = 0; - pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */ - /* pad pointer. use tiptr since we don't need a specific padding char */ - pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; - pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */ - pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */ - -#if defined(ET_DEBUG) - printf("parm_ptr(0xff788500) = %p\n",pram_ptr); - printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n", - pram_ptr->fen_genfcc.fcc_rbase); - printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n", - pram_ptr->fen_genfcc.fcc_tbase); -#endif - - /* 28.9 - (8)(9): clear out events in FCCE */ - /* 28.9 - (9): FCCM: mask all events */ - if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.fcce = ~0x0; - immr->im_cpm.im_cpm_fcc1.fccm = 0; - } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.fcce = ~0x0; - immr->im_cpm.im_cpm_fcc2.fccm = 0; - } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.fcce = ~0x0; - immr->im_cpm.im_cpm_fcc3.fccm = 0; - } - - /* 28.9 - (10-12): we don't use ethernet interrupts */ - - /* 28.9 - (13) - * - * Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page, - info->cpm_cr_enet_sblock, - 0x0c, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cpcr & CPM_CR_FLG); - - /* 28.9 - (14): enable tx/rx in gfmr */ - if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } else if (info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } else if (info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } - - return 1; -} - -static void fec_halt(struct eth_device* dev) -{ - struct ether_fcc_info_s * info = dev->priv; - volatile immap_t *immr = (immap_t *)CFG_IMMR; - - /* write GFMR: disable tx/rx */ - if(info->ether_index == 0) { - immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } else if(info->ether_index == 1) { - immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } else if(info->ether_index == 2) { - immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } -} - -int fec_initialize(bd_t *bis) -{ - struct eth_device* dev; - int i; - - for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) - { - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - sprintf(dev->name, "FCC%d ETHERNET", - ether_fcc_info[i].ether_index + 1); - dev->priv = ðer_fcc_info[i]; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - eth_register(dev); - -#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \ - && defined(CONFIG_BITBANGMII) - miiphy_register(dev->name, - bb_miiphy_read, bb_miiphy_write); -#endif - } - - return 1; -} - -#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */ - -#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/i2c.c b/cpu/mpc85xx/i2c.c deleted file mode 100644 index 32dcf5d..0000000 --- a/cpu/mpc85xx/i2c.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao - * Adapted for Motorola 85xx chip. - * - * (C) Copyright 2003 - * Gleb Natapov - * Some bits are taken from linux driver writen by adrian@humboldt.co.uk - * - * Hardware I2C driver for MPC107 PCI bridge. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#ifdef CONFIG_HARD_I2C -#include - -#define TIMEOUT (CFG_HZ/4) - -#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3000)) - -#define I2CADR &I2C_Addr[0] -#define I2CFDR &I2C_Addr[4] -#define I2CCCR &I2C_Addr[8] -#define I2CCSR &I2C_Addr[12] -#define I2CCDR &I2C_Addr[16] -#define I2CDFSRR &I2C_Addr[20] - -#define I2C_READ 1 -#define I2C_WRITE 0 - -void -i2c_init(int speed, int slaveadd) -{ - /* stop I2C controller */ - writeb(0x0, I2CCCR); - - /* set clock */ - writeb(0x3f, I2CFDR); - - /* set default filter */ - writeb(0x10,I2CDFSRR); - - /* write slave address */ - writeb(slaveadd, I2CADR); - - /* clear status register */ - writeb(0x0, I2CCSR); - - /* start I2C controller */ - writeb(MPC85xx_I2CCR_MEN, I2CCCR); -} - -static __inline__ int -i2c_wait4bus (void) -{ - ulong timeval = get_timer (0); - - while (readb(I2CCSR) & MPC85xx_I2CSR_MBB) { - if (get_timer (timeval) > TIMEOUT) { - return -1; - } - } - - return 0; -} - -static __inline__ int -i2c_wait (int write) -{ - u32 csr; - ulong timeval = get_timer (0); - - do { - csr = readb(I2CCSR); - - if (!(csr & MPC85xx_I2CSR_MIF)) - continue; - - writeb(0x0, I2CCSR); - - if (csr & MPC85xx_I2CSR_MAL) { - debug("i2c_wait: MAL\n"); - return -1; - } - - if (!(csr & MPC85xx_I2CSR_MCF)) { - debug("i2c_wait: unfinished\n"); - return -1; - } - - if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) { - debug("i2c_wait: No RXACK\n"); - return -1; - } - - return 0; - } while (get_timer (timeval) < TIMEOUT); - - debug("i2c_wait: timed out\n"); - return -1; -} - -static __inline__ int -i2c_write_addr (u8 dev, u8 dir, int rsta) -{ - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX | - (rsta?MPC85xx_I2CCR_RSTA:0), - I2CCCR); - - writeb((dev << 1) | dir, I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - return 0; - - return 1; -} - -static __inline__ int -__i2c_write (u8 *data, int length) -{ - int i; - - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, - I2CCCR); - - for (i=0; i < length; i++) { - writeb(data[i], I2CCDR); - - if (i2c_wait (I2C_WRITE) < 0) - break; - } - - return i; -} - -static __inline__ int -__i2c_read (u8 *data, int length) -{ - int i; - - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | - ((length == 1) ? MPC85xx_I2CCR_TXAK : 0), - I2CCCR); - - /* dummy read */ - readb(I2CCDR); - - for (i=0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) - break; - - /* Generate ack on last next to last byte */ - if (i == length - 2) - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | - MPC85xx_I2CCR_TXAK, - I2CCCR); - - /* Generate stop on last byte */ - if (i == length - 1) - writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR); - - data[i] = readb(I2CCDR); - } - - return i; -} - -int -i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - if (i2c_write_addr (dev, I2C_READ, 1) == 0) - goto exit; - - i = __i2c_read (data, length); - - exit: - writeb(MPC85xx_I2CCR_MEN, I2CCCR); - - return !(i == length); -} - -int -i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) -{ - int i = 0; - u8 *a = (u8*)&addr; - - if (i2c_wait4bus () < 0) - goto exit; - - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; - - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; - - i = __i2c_write (data, length); - - exit: - writeb(MPC85xx_I2CCR_MEN, I2CCCR); - - return !(i == length); -} - -int i2c_probe (uchar chip) -{ - int tmp; - - /* - * Try to read the first location of the chip. The underlying - * driver doesn't appear to support sending just the chip address - * and looking for an back. - */ - udelay(10000); - return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); -} - -uchar i2c_reg_read (uchar i2c_addr, uchar reg) -{ - uchar buf[1]; - - i2c_read (i2c_addr, reg, 1, buf, 1); - - return (buf[0]); -} - -void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write (i2c_addr, reg, 1, &val, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c deleted file mode 100644 index 832781b..0000000 --- a/cpu/mpc85xx/interrupts.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 (440 port) - * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com - * - * (C) Copyright 2003 Motorola Inc. (MPC85xx port) - * Xianghua Xiao (X.Xiao@motorola.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -unsigned decrementer_count; /* count value for 1e6/HZ microseconds */ - -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); - asm volatile("isync"); -} - -static __inline__ unsigned long get_dec (void) -{ - unsigned long val; - - asm volatile ("mfdec %0":"=r" (val):); - - return val; -} - - -static __inline__ void set_dec (unsigned long val) -{ - if (val) - asm volatile ("mtdec %0"::"r" (val)); -} - -void enable_interrupts (void) -{ - set_msr (get_msr() | MSR_EE); -} - -/* returns flag if MSR_EE was set before */ -int disable_interrupts (void) -{ - ulong msr = get_msr(); - set_msr (msr & ~MSR_EE); - return ((msr & MSR_EE) != 0); -} - -int interrupt_init (void) -{ - volatile immap_t *immr = (immap_t *)CFG_IMMR; - - immr->im_pic.gcr = MPC85xx_PICGCR_RST; - while (immr->im_pic.gcr & MPC85xx_PICGCR_RST); - immr->im_pic.gcr = MPC85xx_PICGCR_M; - decrementer_count = get_tbclk() / CFG_HZ; - mtspr(SPRN_TCR, TCR_PIE); - set_dec (decrementer_count); - set_msr (get_msr () | MSR_EE); - return (0); -} - -/* - * Install and free a interrupt handler. Not implemented yet. - */ - -void -irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) -{ - return; -} - -void -irq_free_handler(int vec) -{ - return; -} - -/****************************************************************************/ - - -volatile ulong timestamp = 0; - -/* - * timer_interrupt - gets called when the decrementer overflows, - * with interrupts disabled. - * Trivial implementation - no need to be really accurate. - */ -void timer_interrupt(struct pt_regs *regs) -{ - timestamp++; - set_dec (decrementer_count); - mtspr(SPRN_TSR, TSR_PIS); -#if defined(CONFIG_WATCHDOG) - if ((timestamp % 1000) == 0) - reset_85xx_watchdog(); -#endif /* CONFIG_WATCHDOG */ -} - -void reset_timer (void) -{ - timestamp = 0; -} - -ulong get_timer (ulong base) -{ - return (timestamp - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) - -/******************************************************************************* - * - * irqinfo - print information about PCI devices,not implemented. - * - */ -int -do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf ("\nInterrupt-unsupported:\n"); - - return 0; -} - -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c deleted file mode 100644 index a94493e..0000000 --- a/cpu/mpc85xx/pci.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2003 Motorola Inc. - * Xianghua Xiao (x.xiao@motorola.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCI Configuration space access support for MPC85xx PCI Bridge - */ -#include -#include -#include - - -#if defined(CONFIG_PCI) - -void -pci_mpc85xx_init(struct pci_controller *hose) -{ - volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; - volatile ccsr_pcix_t *pcix = &immap->im_pcix; - - u16 reg16; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - pci_set_region(hose->regions + 1, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 2; - - pci_setup_indirect(hose, - (CFG_IMMR+0x8000), - (CFG_IMMR+0x8004)); - - pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcix->potear1 = 0x00000000; - pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcix->powbear1 = 0x00000000; - pcix->powar1 = 0x8004401c; /* 512M MEM space */ - - pcix->potar2 = 0x00000000; - pcix->potear2 = 0x00000000; - pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pcix->powbear2 = 0x00000000; - pcix->powar2 = 0x80088017; /* 16M IO space */ - - pcix->pitar1 = 0x00000000; - pcix->piwbar1 = 0x00000000; - pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, - * Snoop R/W, 2G */ - - /* - * Hose scan. - */ - pci_register_hose(hose); - - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); - -#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS) - /* - * This is a SW workaround for an apparent HW problem - * in the PCI controller on the MPC85555/41 CDS boards. - * The first config cycle must be to a valid, known - * device on the PCI bus in order to trick the PCI - * controller state machine into a known valid state. - * Without this, the first config cycle has the chance - * of hanging the controller permanently, just leaving - * it in a semi-working state, or leaving it working. - * - * Pick on the Tundra, Device 17, to get it right. - */ - { - u8 header_type; - - pci_hose_read_config_byte(hose, - PCI_BDF(0,17,0), - PCI_HEADER_TYPE, - &header_type); - } -#endif - - hose->last_busno = pci_hose_scan(hose); -} - -#endif /* CONFIG_PCI */ diff --git a/cpu/mpc85xx/resetvec.S b/cpu/mpc85xx/resetvec.S deleted file mode 100644 index 29555d4..0000000 --- a/cpu/mpc85xx/resetvec.S +++ /dev/null @@ -1,2 +0,0 @@ - .section .resetvec,"ax" - b _start_e500 diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c deleted file mode 100644 index cf060d6..0000000 --- a/cpu/mpc85xx/serial_scc.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao (X.Xiao@motorola.com) - * Modified based on 8260 for 8560. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00. - */ - -/* - * Minimal serial functions needed to use one of the SCC ports - * as serial console interface. - */ - -#include -#include - -#if defined(CONFIG_CPM2) -#if defined(CONFIG_CONS_ON_SCC) - -#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ - -#define SCC_INDEX 0 -#define PROFF_SCC PROFF_SCC1 -#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ - CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) -#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK - -#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */ - -#define SCC_INDEX 1 -#define PROFF_SCC PROFF_SCC2 -#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ - CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) -#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK - -#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */ - -#define SCC_INDEX 2 -#define PROFF_SCC PROFF_SCC3 -#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ - CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) -#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK - -#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */ - -#define SCC_INDEX 3 -#define PROFF_SCC PROFF_SCC4 -#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ - CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) -#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) -#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE -#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK - -#else - -#error "console not correctly defined" - -#endif - -int serial_init (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile ccsr_cpm_scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp); - uint dpaddr; - - /* initialize pointers to SCC */ - - sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]); - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); - - /* Disable transmitter/receiver. - */ - sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* put the SCC channel into NMSI (non multiplexd serial interface) - * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). - */ - im->im_cpm.im_cpm_mux.cmxscr = \ - (im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; - - /* Set up the baud rate generator. - */ - serial_setbrg (); - - /* Allocate space for two buffer descriptors in the DP ram. - * damm: allocating space after the two buffers for rx/tx data - */ - - dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]); - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = BD_SC_WRAP; - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - up->scc_genscc.scc_rfcr = CPMFCR_EB; - up->scc_genscc.scc_tfcr = CPMFCR_EB; - up->scc_genscc.scc_mrblr = 1; - up->scc_maxidl = 0; - up->scc_brkcr = 1; - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; - up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Mask all interrupts and remove anything pending. - */ - sp->sccm = 0; - sp->scce = 0xffff; - - /* Set 8 bit FIFO, 16 bit oversampling and UART mode. - */ - sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ - sp->gsmrl = \ - SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; - - /* Set CTS no flow control, 1 stop bit, 8 bit character length, - * normal async UART mode, no parity - */ - sp->psmr = SCU_PSMR_CL; - - /* execute the "Init Rx and Tx params" CP command. - */ - - while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, - 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; - - return (0); -} - -void -serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CONS_USE_EXTC) - m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate, - CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); -#else - m8560_cpm_setbrg(SCC_INDEX, gd->baudrate); -#endif -} - -void -serial_putc(const char c) -{ - volatile scc_uart_t *up; - volatile cbd_t *tbdf; - volatile immap_t *im; - - if (c == '\n') - serial_putc ('\r'); - - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); - tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]); - - /* Wait for last character to go. - */ - while (tbdf->cbd_sc & BD_SC_READY) - ; - - /* Load the character into the transmit buffer. - */ - *(volatile char *)tbdf->cbd_bufaddr = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int -serial_getc(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im; - unsigned char c; - - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); - rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); - - /* Wait for character to show up. - */ - while (rbdf->cbd_sc & BD_SC_EMPTY) - ; - - /* Grab the char and clear the buffer again. - */ - c = *(volatile unsigned char *)rbdf->cbd_bufaddr; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - -int -serial_tstc() -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im; - - im = (immap_t *)CFG_IMMR; - up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); - rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); - - return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); -} - -#endif /* CONFIG_CONS_ON_SCC */ - -#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c deleted file mode 100644 index af99282..0000000 --- a/cpu/mpc85xx/spd_sdram.c +++ /dev/null @@ -1,1118 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao (X.Xiao@motorola.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void dma_init(void); -extern uint dma_check(void); -extern int dma_xfer(void *dest, uint count, void *src); -#endif - -#ifdef CONFIG_SPD_EEPROM - -#ifndef CFG_READ_SPD -#define CFG_READ_SPD i2c_read -#endif - -static unsigned int setup_laws_and_tlbs(unsigned int memsize); - - -/* - * Convert picoseconds into clock cycles (rounding up if needed). - */ - -int -picos_to_clk(int picos) -{ - int clks; - - clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); - if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { - clks++; - } - - return clks; -} - - -/* - * Calculate the Density of each Physical Rank. - * Returned size is in bytes. - * - * Study these table from Byte 31 of JEDEC SPD Spec. - * - * DDR I DDR II - * Bit Size Size - * --- ----- ------ - * 7 high 512MB 512MB - * 6 256MB 256MB - * 5 128MB 128MB - * 4 64MB 16GB - * 3 32MB 8GB - * 2 16MB 4GB - * 1 2GB 2GB - * 0 low 1GB 1GB - * - * Reorder Table to be linear by stripping the bottom - * 2 or 5 bits off and shifting them up to the top. - */ - -unsigned int -compute_banksize(unsigned int mem_type, unsigned char row_dens) -{ - unsigned int bsize; - - if (mem_type == SPD_MEMTYPE_DDR) { - /* Bottom 2 bits up to the top. */ - bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; - debug("DDR: DDR I rank density = 0x%08x\n", bsize); - } else { - /* Bottom 5 bits up to the top. */ - bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27; - debug("DDR: DDR II rank density = 0x%08x\n", bsize); - } - return bsize; -} - - -/* - * Convert a two-nibble BCD value into a cycle time. - * While the spec calls for nano-seconds, picos are returned. - * - * This implements the tables for bytes 9, 23 and 25 for both - * DDR I and II. No allowance for distinguishing the invalid - * fields absent for DDR I yet present in DDR II is made. - * (That is, cycle times of .25, .33, .66 and .75 ns are - * allowed for both DDR II and I.) - */ - -unsigned int -convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) -{ - /* - * Table look up the lower nibble, allow DDR I & II. - */ - unsigned int tenths_ps[16] = { - 0, - 100, - 200, - 300, - 400, - 500, - 600, - 700, - 800, - 900, - 250, - 330, /* FIXME: Is 333 better/valid? */ - 660, /* FIXME: Is 667 better/valid? */ - 750, - 0, /* undefined */ - 0 /* undefined */ - }; - - unsigned int whole_ns = (spd_val & 0xF0) >> 4; - unsigned int tenth_ns = spd_val & 0x0F; - unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; - - return ps; -} - - -long int -spd_sdram(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr; - volatile ccsr_gur_t *gur = &immap->im_gur; - spd_eeprom_t spd; - unsigned int n_ranks; - unsigned int rank_density; - unsigned int odt_rd_cfg, odt_wr_cfg; - unsigned int odt_cfg, mode_odt_enable; - unsigned int dqs_cfg; - unsigned char twr_clk, twtr_clk, twr_auto_clk; - unsigned int tCKmin_ps, tCKmax_ps; - unsigned int max_data_rate, effective_data_rate; - unsigned int busfreq; - unsigned sdram_cfg; - unsigned int memsize; - unsigned char caslat, caslat_ctrl; - unsigned int trfc, trfc_clk, trfc_low, trfc_high; - unsigned int trcd_clk; - unsigned int trtp_clk; - unsigned char cke_min_clk; - unsigned char add_lat; - unsigned char wr_lat; - unsigned char wr_data_delay; - unsigned char four_act; - unsigned char cpo; - unsigned char burst_len; - unsigned int mode_caslat; - unsigned char sdram_type; - unsigned char d_init; - - /* - * Read SPD information. - */ - CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd)); - - /* - * Check for supported memory module types. - */ - if (spd.mem_type != SPD_MEMTYPE_DDR && - spd.mem_type != SPD_MEMTYPE_DDR2) { - printf("Unable to locate DDR I or DDR II module.\n" - " Fundamental memory type is 0x%0x\n", - spd.mem_type); - return 0; - } - - /* - * These test gloss over DDR I and II differences in interpretation - * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks - * are not supported on DDR I; and not encoded on DDR II. - * - * Also note that the 8548 controller can support: - * 12 <= nrow <= 16 - * and - * 8 <= ncol <= 11 (still, for DDR) - * 6 <= ncol <= 9 (for FCRAM) - */ - if (spd.nrow_addr < 12 || spd.nrow_addr > 14) { - printf("DDR: Unsupported number of Row Addr lines: %d.\n", - spd.nrow_addr); - return 0; - } - if (spd.ncol_addr < 8 || spd.ncol_addr > 11) { - printf("DDR: Unsupported number of Column Addr lines: %d.\n", - spd.ncol_addr); - return 0; - } - - /* - * Determine the number of physical banks controlled by - * different Chip Select signals. This is not quite the - * same as the number of DIMM modules on the board. Feh. - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - n_ranks = spd.nrows; - } else { - n_ranks = (spd.nrows & 0x7) + 1; - } - - debug("DDR: number of ranks = %d\n", n_ranks); - - if (n_ranks > 2) { - printf("DDR: Only 2 chip selects are supported: %d\n", - n_ranks); - return 0; - } - - /* - * Adjust DDR II IO voltage biasing. It just makes it work. - */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - gur->ddrioovcr = (0 - | 0x80000000 /* Enable */ - | 0x10000000 /* VSEL to 1.8V */ - ); - } - - /* - * Determine the size of each Rank in bytes. - */ - rank_density = compute_banksize(spd.mem_type, spd.row_dens); - - - /* - * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg - */ - ddr->cs0_bnds = (rank_density >> 24) - 1; - - /* - * ODT configuration recommendation from DDR Controller Chapter. - */ - odt_rd_cfg = 0; /* Never assert ODT */ - odt_wr_cfg = 0; /* Never assert ODT */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ -#if 0 - /* FIXME: How to determine the number of dimm modules? */ - if (n_dimm_modules == 2) { - odt_rd_cfg = 1; /* Assert ODT on reads to CS0 */ - } -#endif - } - - ddr->cs0_config = ( 1 << 31 - | (odt_rd_cfg << 20) - | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 - | (spd.ncol_addr - 8) ); - debug("\n"); - debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); - debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); - - if (n_ranks == 2) { - /* - * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg - */ - ddr->cs1_bnds = ( (rank_density >> 8) - | ((rank_density >> (24 - 1)) - 1) ); - ddr->cs1_config = ( 1<<31 - | (odt_rd_cfg << 20) - | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 - | (spd.ncol_addr - 8) ); - debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds); - debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config); - } - - - /* - * Find the largest CAS by locating the highest 1 bit - * in the spd.cas_lat field. Translate it to a DDR - * controller field value: - * - * CAS Lat DDR I DDR II Ctrl - * Clocks SPD Bit SPD Bit Value - * ------- ------- ------- ----- - * 1.0 0 0001 - * 1.5 1 0010 - * 2.0 2 2 0011 - * 2.5 3 0100 - * 3.0 4 3 0101 - * 3.5 5 0110 - * 4.0 4 0111 - * 4.5 1000 - * 5.0 5 1001 - */ - caslat = __ilog2(spd.cas_lat); - if ((spd.mem_type == SPD_MEMTYPE_DDR) - && (caslat > 5)) { - printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat); - return 0; - - } else if (spd.mem_type == SPD_MEMTYPE_DDR2 - && (caslat < 2 || caslat > 5)) { - printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n", - spd.cas_lat); - return 0; - } - debug("DDR: caslat SPD bit is %d\n", caslat); - - /* - * Calculate the Maximum Data Rate based on the Minimum Cycle time. - * The SPD clk_cycle field (tCKmin) is measured in tenths of - * nanoseconds and represented as BCD. - */ - tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle); - debug("DDR: tCKmin = %d ps\n", tCKmin_ps); - - /* - * Double-data rate, scaled 1000 to picoseconds, and back down to MHz. - */ - max_data_rate = 2 * 1000 * 1000 / tCKmin_ps; - debug("DDR: Module max data rate = %d Mhz\n", max_data_rate); - - - /* - * Adjust the CAS Latency to allow for bus speeds that - * are slower than the DDR module. - */ - busfreq = get_bus_freq(0) / 1000000; /* MHz */ - - effective_data_rate = max_data_rate; - if (busfreq < 90) { - /* DDR rate out-of-range */ - puts("DDR: platform frequency is not fit for DDR rate\n"); - return 0; - - } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) { - /* - * busfreq 90~230 range, treated as DDR 200. - */ - effective_data_rate = 200; - if (spd.clk_cycle3 == 0xa0) /* 10 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0xa0) - caslat--; - - } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) { - /* - * busfreq 230~280 range, treated as DDR 266. - */ - effective_data_rate = 266; - if (spd.clk_cycle3 == 0x75) /* 7.5 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0x75) - caslat--; - - } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) { - /* - * busfreq 280~350 range, treated as DDR 333. - */ - effective_data_rate = 333; - if (spd.clk_cycle3 == 0x60) /* 6.0 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0x60) - caslat--; - - } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) { - /* - * busfreq 350~460 range, treated as DDR 400. - */ - effective_data_rate = 400; - if (spd.clk_cycle3 == 0x50) /* 5.0 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0x50) - caslat--; - - } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) { - /* - * busfreq 460~560 range, treated as DDR 533. - */ - effective_data_rate = 533; - if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0x3D) - caslat--; - - } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) { - /* - * busfreq 560~700 range, treated as DDR 667. - */ - effective_data_rate = 667; - if (spd.clk_cycle3 == 0x30) /* 3.0 ns */ - caslat -= 2; - else if (spd.clk_cycle2 == 0x30) - caslat--; - - } else if (700 <= busfreq) { - /* - * DDR rate out-of-range - */ - printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n", - busfreq, max_data_rate); - return 0; - } - - - /* - * Convert caslat clocks to DDR controller value. - * Force caslat_ctrl to be DDR Controller field-sized. - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - caslat_ctrl = (caslat + 1) & 0x07; - } else { - caslat_ctrl = (2 * caslat - 1) & 0x0f; - } - - debug("DDR: effective data rate is %d MHz\n", effective_data_rate); - debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", - caslat, caslat_ctrl); - - /* - * Timing Config 0. - * Avoid writing for DDR I. The new PQ38 DDR controller - * dreams up non-zero default values to be backwards compatible. - */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - unsigned char taxpd_clk = 8; /* By the book. */ - unsigned char tmrd_clk = 2; /* By the book. */ - unsigned char act_pd_exit = 2; /* Empirical? */ - unsigned char pre_pd_exit = 6; /* Empirical? */ - - ddr->timing_cfg_0 = (0 - | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ - | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ - | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ - | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ - ); -#if 0 - ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */ -#endif - debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); - - } else { -#if 0 - /* - * Force extra cycles with 0xaa bits. - * Incidentally supply the dreamt-up backwards compat value! - */ - ddr->timing_cfg_0 = 0x00110105; /* backwards compat value */ - ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */ - debug("DDR: HACK timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); -#endif - } - - - /* - * Some Timing Config 1 values now. - * Sneak Extended Refresh Recovery in here too. - */ - - /* - * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD, - * use conservative value. - * For DDR II, they are bytes 36 and 37, in quarter nanos. - */ - - if (spd.mem_type == SPD_MEMTYPE_DDR) { - twr_clk = 3; /* Clocks */ - twtr_clk = 1; /* Clocks */ - } else { - twr_clk = picos_to_clk(spd.twr * 250); - twtr_clk = picos_to_clk(spd.twtr * 250); - } - - /* - * Calculate Trfc, in picos. - * DDR I: Byte 42 straight up in ns. - * DDR II: Byte 40 and 42 swizzled some, in ns. - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - trfc = spd.trfc * 1000; /* up to ps */ - } else { - unsigned int byte40_table_ps[8] = { - 0, - 250, - 330, - 500, - 660, - 750, - 0, - 0 - }; - - trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000 - + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7]; - } - trfc_clk = picos_to_clk(trfc); - - /* - * Trcd, Byte 29, from quarter nanos to ps and clocks. - */ - trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7; - - /* - * Convert trfc_clk to DDR controller fields. DDR I should - * fit in the REFREC field (16-19) of TIMING_CFG_1, but the - * 8548 controller has an extended REFREC field of three bits. - * The controller automatically adds 8 clocks to this value, - * so preadjust it down 8 first before splitting it up. - */ - trfc_low = (trfc_clk - 8) & 0xf; - trfc_high = ((trfc_clk - 8) >> 4) & 0x3; - - /* - * Sneak in some Extended Refresh Recovery. - */ - ddr->ext_refrec = (trfc_high << 16); - debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); - - ddr->timing_cfg_1 = - (0 - | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */ - | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */ - | (trcd_clk << 20) /* ACTTORW */ - | (caslat_ctrl << 16) /* CASLAT */ - | (trfc_low << 12) /* REFEC */ - | ((twr_clk & 0x07) << 8) /* WRRREC */ - | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */ - | ((twtr_clk & 0x07) << 0) /* WRTORD */ - ); - - debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); - - - /* - * Timing_Config_2 - * Was: 0x00000800; - */ - - /* - * Additive Latency - * For DDR I, 0. - * For DDR II, with ODT enabled, use "a value" less than ACTTORW, - * which comes from Trcd, and also note that: - * add_lat + caslat must be >= 4 - */ - add_lat = 0; - if (spd.mem_type == SPD_MEMTYPE_DDR2 - && (odt_wr_cfg || odt_rd_cfg) - && (caslat < 4)) { - add_lat = 4 - caslat; - if (add_lat > trcd_clk) { - add_lat = trcd_clk - 1; - } - } - - /* - * Write Data Delay - * Historically 0x2 == 4/8 clock delay. - * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. - */ - wr_data_delay = 3; - - /* - * Write Latency - * Read to Precharge - * Minimum CKE Pulse Width. - * Four Activate Window - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - /* - * This is a lie. It should really be 1, but if it is - * set to 1, bits overlap into the old controller's - * otherwise unused ACSM field. If we leave it 0, then - * the HW will magically treat it as 1 for DDR 1. Oh Yea. - */ - wr_lat = 0; - - trtp_clk = 2; /* By the book. */ - cke_min_clk = 1; /* By the book. */ - four_act = 1; /* By the book. */ - - } else { - wr_lat = caslat - 1; - - /* Convert SPD value from quarter nanos to picos. */ - trtp_clk = picos_to_clk(spd.trtp * 250); - - cke_min_clk = 3; /* By the book. */ - four_act = picos_to_clk(37500); /* By the book. 1k pages? */ - } - - /* - * Empirically set ~MCAS-to-preamble override for DDR 2. - * Your milage will vary. - */ - cpo = 0; - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - if (effective_data_rate == 266 || effective_data_rate == 333) { - cpo = 0x7; /* READ_LAT + 5/4 */ - } else if (effective_data_rate == 400) { - cpo = 0x9; /* READ_LAT + 7/4 */ - } else { - /* Pure speculation */ - cpo = 0xb; - } - } - - ddr->timing_cfg_2 = (0 - | ((add_lat & 0x7) << 28) /* ADD_LAT */ - | ((cpo & 0x1f) << 23) /* CPO */ - | ((wr_lat & 0x7) << 19) /* WR_LAT */ - | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ - | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ - | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */ - | ((four_act & 0x1f) << 0) /* FOUR_ACT */ - ); - - debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); - - - /* - * Determine the Mode Register Set. - * - * This is nominally part specific, but it appears to be - * consistent for all DDR I devices, and for all DDR II devices. - * - * caslat must be programmed - * burst length is always 4 - * burst type is sequential - * - * For DDR I: - * operating mode is "normal" - * - * For DDR II: - * other stuff - */ - - mode_caslat = 0; - - /* - * Table lookup from DDR I or II Device Operation Specs. - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - if (1 <= caslat && caslat <= 4) { - unsigned char mode_caslat_table[4] = { - 0x5, /* 1.5 clocks */ - 0x2, /* 2.0 clocks */ - 0x6, /* 2.5 clocks */ - 0x3 /* 3.0 clocks */ - }; - mode_caslat = mode_caslat_table[caslat - 1]; - } else { - puts("DDR I: Only CAS Latencies of 1.5, 2.0, " - "2.5 and 3.0 clocks are supported.\n"); - return 0; - } - - } else { - if (2 <= caslat && caslat <= 5) { - mode_caslat = caslat; - } else { - puts("DDR II: Only CAS Latencies of 2.0, 3.0, " - "4.0 and 5.0 clocks are supported.\n"); - return 0; - } - } - - /* - * Encoded Burst Lenght of 4. - */ - burst_len = 2; /* Fiat. */ - - if (spd.mem_type == SPD_MEMTYPE_DDR) { - twr_auto_clk = 0; /* Historical */ - } else { - /* - * Determine tCK max in picos. Grab tWR and convert to picos. - * Auto-precharge write recovery is: - * WR = roundup(tWR_ns/tCKmax_ns). - * - * Ponder: Is twr_auto_clk different than twr_clk? - */ - tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax); - twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps; - } - - - /* - * Mode Reg in bits 16 ~ 31, - * Extended Mode Reg 1 in bits 0 ~ 15. - */ - mode_odt_enable = 0x0; /* Default disabled */ - if (odt_wr_cfg || odt_rd_cfg) { - /* - * Bits 6 and 2 in Extended MRS(1) - * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules. - * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module. - */ - mode_odt_enable = 0x40; /* 150 Ohm */ - } - - ddr->sdram_mode = - (0 - | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ - | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ - | (twr_auto_clk << 9) /* Write Recovery Autopre */ - | (mode_caslat << 4) /* caslat */ - | (burst_len << 0) /* Burst length */ - ); - - debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode); - - - /* - * Clear EMRS2 and EMRS3. - */ - ddr->sdram_mode_2 = 0; - debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2); - - - /* - * Determine Refresh Rate. Ignore self refresh bit on DDR I. - * Table from SPD Spec, Byte 12, converted to picoseconds and - * filled in with "default" normal values. - */ - { - unsigned int refresh_clk; - unsigned int refresh_time_ns[8] = { - 15625000, /* 0 Normal 1.00x */ - 3900000, /* 1 Reduced .25x */ - 7800000, /* 2 Extended .50x */ - 31300000, /* 3 Extended 2.00x */ - 62500000, /* 4 Extended 4.00x */ - 125000000, /* 5 Extended 8.00x */ - 15625000, /* 6 Normal 1.00x filler */ - 15625000, /* 7 Normal 1.00x filler */ - }; - - refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]); - - /* - * Set BSTOPRE to 0x100 for page mode - * If auto-charge is used, set BSTOPRE = 0 - */ - ddr->sdram_interval = - (0 - | (refresh_clk & 0x3fff) << 16 - | 0x100 - ); - debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); - } - - /* - * Is this an ECC DDR chip? - * But don't mess with it if the DDR controller will init mem. - */ -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - if (spd.config == 0x02) { - ddr->err_disable = 0x0000000d; - ddr->err_sbe = 0x00ff0000; - } - debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); - debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); -#endif - - asm("sync;isync;msync"); - udelay(500); - - /* - * SDRAM Cfg 2 - */ - - /* - * When ODT is enabled, Chap 9 suggests asserting ODT to - * internal IOs only during reads. - */ - odt_cfg = 0; - if (odt_rd_cfg | odt_wr_cfg) { - odt_cfg = 0x2; /* ODT to IOs during reads */ - } - - /* - * Try to use differential DQS with DDR II. - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - dqs_cfg = 0; /* No Differential DQS for DDR I */ - } else { - dqs_cfg = 0x1; /* Differential DQS for DDR II */ - } - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Use the DDR controller to auto initialize memory. - */ - d_init = 1; - ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE; - debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init); -#else - /* - * Memory will be initialized via DMA, or not at all. - */ - d_init = 0; -#endif - - ddr->sdram_cfg_2 = (0 - | (dqs_cfg << 26) /* Differential DQS */ - | (odt_cfg << 21) /* ODT */ - | (d_init << 4) /* D_INIT auto init DDR */ - ); - - debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2); - - -#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL - { - unsigned char clk_adjust; - - /* - * Setup the clock control. - * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 - * SDRAM_CLK_CNTL[5-7] = Clock Adjust - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - clk_adjust = 0x6; - } else { - clk_adjust = 0x7; - } - - ddr->sdram_clk_cntl = (0 - | 0x80000000 - | (clk_adjust << 23) - ); - debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); - } -#endif - - /* - * Figure out the settings for the sdram_cfg register. - * Build up the entire register in 'sdram_cfg' before writing - * since the write into the register will actually enable the - * memory controller; all settings must be done before enabling. - * - * sdram_cfg[0] = 1 (ddr sdram logic enable) - * sdram_cfg[1] = 1 (self-refresh-enable) - * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) - * 010 DDR 1 SDRAM - * 011 DDR 2 SDRAM - */ - sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; - sdram_cfg = (0 - | (1 << 31) /* Enable */ - | (1 << 30) /* Self refresh */ - | (sdram_type << 24) /* SDRAM type */ - ); - - /* - * sdram_cfg[3] = RD_EN - registered DIMM enable - * A value of 0x26 indicates micron registered DIMMS (micron.com) - */ - if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) { - sdram_cfg |= 0x10000000; /* RD_EN */ - } - -#if defined(CONFIG_DDR_ECC) - /* - * If the user wanted ECC (enabled via sdram_cfg[2]) - */ - if (spd.config == 0x02) { - sdram_cfg |= 0x20000000; /* ECC_EN */ - } -#endif - - /* - * REV1 uses 1T timing. - * REV2 may use 1T or 2T as configured by the user. - */ - { - uint pvr = get_pvr(); - - if (pvr != PVR_85xx_REV1) { -#if defined(CONFIG_DDR_2T_TIMING) - /* - * Enable 2T timing by setting sdram_cfg[16]. - */ - sdram_cfg |= 0x8000; /* 2T_EN */ -#endif - } - } - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - - /* - * Go! - */ - ddr->sdram_cfg = sdram_cfg; - - asm("sync;isync;msync"); - udelay(500); - - debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg); - - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { - udelay(1000); - } -#endif - - - /* - * Figure out memory size in Megabytes. - */ - memsize = n_ranks * rank_density / 0x100000; - - /* - * Establish Local Access Window and TLB mappings for DDR memory. - */ - memsize = setup_laws_and_tlbs(memsize); - if (memsize == 0) { - return 0; - } - - return memsize * 1024 * 1024; -} - - -/* - * Setup Local Access Window and TLB1 mappings for the requested - * amount of memory. Returns the amount of memory actually mapped - * (usually the original request size), or 0 on error. - */ - -static unsigned int -setup_laws_and_tlbs(unsigned int memsize) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; - unsigned int tlb_size; - unsigned int law_size; - unsigned int ram_tlb_index; - unsigned int ram_tlb_address; - - /* - * Determine size of each TLB1 entry. - */ - switch (memsize) { - case 16: - case 32: - tlb_size = BOOKE_PAGESZ_16M; - break; - case 64: - case 128: - tlb_size = BOOKE_PAGESZ_64M; - break; - case 256: - case 512: - case 1024: - case 2048: - tlb_size = BOOKE_PAGESZ_256M; - break; - default: - puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n"); - - /* - * The memory was not able to be mapped. - */ - return 0; - break; - } - - /* - * Configure DDR TLB1 entries. - * Starting at TLB1 8, use no more than 8 TLB1 entries. - */ - ram_tlb_index = 8; - ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; - while (ram_tlb_address < (memsize * 1024 * 1024) - && ram_tlb_index < 16) { - mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0)); - mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size)); - mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), - 0, 0, 0, 0, 0, 0, 0, 0)); - mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), - 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); - asm volatile("isync;msync;tlbwe;isync"); - - debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0)); - debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size)); - debug("DDR: MAS2=0x%08x\n", - TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), - 0, 0, 0, 0, 0, 0, 0, 0)); - debug("DDR: MAS3=0x%08x\n", - TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), - 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); - - ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); - ram_tlb_index++; - } - - - /* - * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. - */ - law_size = 19 + __ilog2(memsize); - - /* - * Set up LAWBAR for all of DDR. - */ - ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); - ecm->lawar1 = (LAWAR_EN - | LAWAR_TRGT_IF_DDR - | (LAWAR_SIZE & law_size)); - debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1); - debug("DDR: LARAR1=0x%08x\n", ecm->lawar1); - - /* - * Confirm that the requested amount of memory was mapped. - */ - return memsize; -} - -#endif /* CONFIG_SPD_EEPROM */ - - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - -/* - * Initialize all of memory for ECC, then enable errors. - */ - -void -ddr_enable_ecc(unsigned int dram_size) -{ - uint *p = 0; - uint i = 0; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; - - dma_init(); - - for (*p = 0; p < (uint *)(8 * 1024); p++) { - if (((unsigned int)p & 0x1f) == 0) { - ppcDcbz((unsigned long) p); - } - *p = (unsigned int)CONFIG_MEM_INIT_VALUE; - if (((unsigned int)p & 0x1c) == 0x1c) { - ppcDcbf((unsigned long) p); - } - } - - /* 8K */ - dma_xfer((uint *)0x2000, 0x2000, (uint *)0); - /* 16K */ - dma_xfer((uint *)0x4000, 0x4000, (uint *)0); - /* 32K */ - dma_xfer((uint *)0x8000, 0x8000, (uint *)0); - /* 64K */ - dma_xfer((uint *)0x10000, 0x10000, (uint *)0); - /* 128k */ - dma_xfer((uint *)0x20000, 0x20000, (uint *)0); - /* 256k */ - dma_xfer((uint *)0x40000, 0x40000, (uint *)0); - /* 512k */ - dma_xfer((uint *)0x80000, 0x80000, (uint *)0); - /* 1M */ - dma_xfer((uint *)0x100000, 0x100000, (uint *)0); - /* 2M */ - dma_xfer((uint *)0x200000, 0x200000, (uint *)0); - /* 4M */ - dma_xfer((uint *)0x400000, 0x400000, (uint *)0); - - for (i = 1; i < dram_size / 0x800000; i++) { - dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); - } - - /* - * Enable errors for ECC. - */ - debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); -} - -#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c deleted file mode 100644 index d736742..0000000 --- a/cpu/mpc85xx/speed.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* --------------------------------------------------------------- */ - -void get_sys_info (sys_info_t * sysInfo) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - uint plat_ratio,e500_ratio; - - plat_ratio = (gur->porpllsr) & 0x0000003e; - plat_ratio >>= 1; - switch(plat_ratio) { - case 0x02: - case 0x03: - case 0x04: - case 0x05: - case 0x06: - case 0x08: - case 0x09: - case 0x0a: - case 0x0c: - case 0x10: - sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; - break; - default: - sysInfo->freqSystemBus = 0; - break; - } - - e500_ratio = (gur->porpllsr) & 0x003f0000; - e500_ratio >>= 16; - switch(e500_ratio) { - case 0x04: - sysInfo->freqProcessor = 2*sysInfo->freqSystemBus; - break; - case 0x05: - sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2; - break; - case 0x06: - sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; - break; - case 0x07: - sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2; - break; - default: - sysInfo->freqProcessor = 0; - break; - } -} - -int get_clocks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - sys_info_t sys_info; -#if defined(CONFIG_CPM2) - volatile immap_t *immap = (immap_t *) CFG_IMMR; - uint sccr, dfbrg; - - /* set VCO = 4 * BRG */ - immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc; - sccr = immap->im_cpm.im_cpm_intctl.sccr; - dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; -#endif - get_sys_info (&sys_info); - gd->cpu_clk = sys_info.freqProcessor; - gd->bus_clk = sys_info.freqSystemBus; -#if defined(CONFIG_CPM2) - gd->vco_out = 2*sys_info.freqSystemBus; - gd->cpm_clk = gd->vco_out / 2; - gd->scc_clk = gd->vco_out / 4; - gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); -#endif - - if(gd->cpu_clk != 0) return (0); - else return (1); -} - - -/******************************************** - * get_bus_freq - * return system bus freq in Hz - *********************************************/ -ulong get_bus_freq (ulong dummy) -{ - ulong val; - - sys_info_t sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqSystemBus; - - return val; -} diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S deleted file mode 100644 index 7ac6573..0000000 --- a/cpu/mpc85xx/start.S +++ /dev/null @@ -1,1157 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Copyright (C) 2003 Motorola,Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards - * - * The processor starts at 0xfffffffc and the code is first executed in the - * last 4K page(0xfffff000-0xffffffff) in flash/rom. - * - */ - -#include -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -#undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ - -/* - * Set up GOT: Global Offset Table - * - * Use r14 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * e500 Startup -- after reset only the last 4KB of the effective - * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg - * section is located at THIS LAST page and basically does three - * things: clear some registers, set up exception tables and - * add more TLB entries for 'larger spaces'(e.g. the boot rom) to - * continue the boot procedure. - - * Once the boot rom is mapped by TLB entries we can proceed - * with normal startup. - * - */ - - .section .bootpg,"ax" - .globl _start_e500 - -_start_e500: - mfspr r0, PVR - lis r1, PVR_85xx_REV1@h - ori r1, r1, PVR_85xx_REV1@l - cmpw r0, r1 - bne 1f - - /* Semi-bogus errata fixup for Rev 1 */ - li r0,0x2000 - mtspr 977,r0 - - /* - * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then - * write it back immediately to fixup a Rev 1 bug (Errata CPU4) - * for this initial TLB1 entry 0, otherwise the TLB1 entry 0 - * will be invalidated (incorrectly). - */ - lis r2,0x1000 - mtspr MAS0,r2 - tlbre - tlbwe - isync - -1: - /* - * Clear and set up some registers. - * Note: Some registers need strict synchronization by - * sync/mbar/msync/isync when being "mtspr". - * BookE: isync before PID,tlbivax,tlbwe - * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe - * E500: msync,isync before L1CSR0 - * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1, - * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2], - * SPEFCSR - */ - - /* invalidate d-cache */ - mfspr r0,L1CSR0 - ori r0,r0,0x0002 - msync - isync - mtspr L1CSR0,r0 - isync - - /* disable d-cache */ - li r0,0x0 - mtspr L1CSR0,r0 - - /* invalidate i-cache */ - mfspr r0,L1CSR1 - ori r0,r0,0x0002 - mtspr L1CSR1,r0 - isync - - /* disable i-cache */ - li r0,0x0 - mtspr L1CSR1,r0 - isync - - /* clear registers */ - li r0,0 - mtspr SRR0,r0 - mtspr SRR1,r0 - mtspr CSRR0,r0 - mtspr CSRR1,r0 - mtspr MCSRR0,r0 - mtspr MCSRR1,r0 - - mtspr ESR,r0 - mtspr MCSR,r0 - mtspr DEAR,r0 - - /* not needed and conflicts with some debuggers */ - /* mtspr DBCR0,r0 */ - mtspr DBCR1,r0 - mtspr DBCR2,r0 - /* not needed and conflicts with some debuggers */ - /* mtspr IAC1,r0 */ - /* mtspr IAC2,r0 */ - mtspr DAC1,r0 - mtspr DAC2,r0 - - mfspr r1,DBSR - mtspr DBSR,r1 /* Clear all valid bits */ - - mtspr PID0,r0 - mtspr PID1,r0 - mtspr PID2,r0 - mtspr TCR,r0 - - mtspr BUCSR,r0 /* disable branch prediction */ - mtspr MAS4,r0 - mtspr MAS6,r0 -#if defined(CONFIG_ENABLE_36BIT_PHYS) - mtspr MAS7,r0 -#endif - isync - - /* Setup interrupt vectors */ - lis r1,TEXT_BASE@h - mtspr IVPR, r1 - - li r1,0x0100 - mtspr IVOR0,r1 /* 0: Critical input */ - li r1,0x0200 - mtspr IVOR1,r1 /* 1: Machine check */ - li r1,0x0300 - mtspr IVOR2,r1 /* 2: Data storage */ - li r1,0x0400 - mtspr IVOR3,r1 /* 3: Instruction storage */ - li r1,0x0500 - mtspr IVOR4,r1 /* 4: External interrupt */ - li r1,0x0600 - mtspr IVOR5,r1 /* 5: Alignment */ - li r1,0x0700 - mtspr IVOR6,r1 /* 6: Program check */ - li r1,0x0800 - mtspr IVOR7,r1 /* 7: floating point unavailable */ - li r1,0x0900 - mtspr IVOR8,r1 /* 8: System call */ - /* 9: Auxiliary processor unavailable(unsupported) */ - li r1,0x0a00 - mtspr IVOR10,r1 /* 10: Decrementer */ - li r1,0x0b00 - mtspr IVOR11,r1 /* 11: Interval timer */ - li r1,0x0c00 - mtspr IVOR12,r1 /* 12: Watchdog timer */ - li r1,0x0d00 - mtspr IVOR13,r1 /* 13: Data TLB error */ - li r1,0x0e00 - mtspr IVOR14,r1 /* 14: Instruction TLB error */ - li r1,0x0f00 - mtspr IVOR15,r1 /* 15: Debug */ - - /* - * Invalidate MMU L1/L2 - * - * Note: There is a fixup earlier for Errata CPU4 on - * Rev 1 parts that must precede this MMU invalidation. - */ - li r2, 0x001e - mtspr MMUCSR0, r2 - isync - - /* - * Invalidate all TLB0 entries. - */ - li r3,4 - li r4,0 - tlbivax r4,r3 - /* - * To avoid REV1 Errata CPU6 issues, make sure - * the instruction following tlbivax is not a store. - */ - - /* - * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. - * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB - * region before we can access any CCSR registers such as L2 - * registers, Local Access Registers,etc. We will also re-allocate - * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup. - * - * Please refer to board-specif directory for TLB1 entry configuration. - * (e.g. board//init.S) - * - */ - bl tlb1_entry - mr r5,r0 - li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */ - mtctr r1 - lwzu r4,0(r5) /* how many TLB1 entries we actually use */ - -0: cmpwi r4,0 - beq 1f - lwzu r0,4(r5) - lwzu r1,4(r5) - lwzu r2,4(r5) - lwzu r3,4(r5) - mtspr MAS0,r0 - mtspr MAS1,r1 - mtspr MAS2,r2 - mtspr MAS3,r3 - isync - msync - tlbwe - isync - addi r4,r4,-1 - bdnz 0b - -1: -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* Special sequence needed to update CCSRBAR itself */ - lis r4, CFG_CCSRBAR_DEFAULT@h - ori r4, r4, CFG_CCSRBAR_DEFAULT@l - - lis r5, CFG_CCSRBAR@h - ori r5, r5, CFG_CCSRBAR@l - srwi r6,r5,12 - stw r6, 0(r4) - isync - - lis r5, 0xffff - ori r5,r5,0xf000 - lwz r5, 0(r5) - isync - - lis r3, CFG_CCSRBAR@h - lwz r5, CFG_CCSRBAR@l(r3) - isync -#endif - - - /* set up local access windows, defined at board//init.S */ - lis r7,CFG_CCSRBAR@h - ori r7,r7,CFG_CCSRBAR@l - - bl law_entry - mr r6,r0 - li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */ - mtctr r1 - lwzu r5,0(r6) /* how many windows we actually use */ - - li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */ - li r1,0x0c30 - -0: cmpwi r5,0 - beq 1f - lwzu r4,4(r6) - lwzu r3,4(r6) - stwx r4,r7,r2 - stwx r3,r7,r1 - addi r5,r5,-1 - addi r2,r2,0x0020 - addi r1,r1,0x0020 - bdnz 0b - - /* Jump out the last 4K page and continue to 'normal' start */ -1: bl 3f - b _start - -3: li r0,0 - mtspr SRR1,r0 /* Keep things disabled for now */ - mflr r1 - mtspr SRR0,r1 - rfi - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-BOOT Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - /* Clear and set up some registers. */ - li r0,0x0000 - lis r1,0xffff - mtspr DEC,r0 /* prevent dec exceptions */ - mttbl r0 /* prevent fit & wdt exceptions */ - mttbu r0 - mtspr TSR,r1 /* clear all timer exception status */ - mtspr TCR,r0 /* disable all */ - mtspr ESR,r0 /* clear exception syndrome register */ - mtspr MCSR,r0 /* machine check syndrome register */ - mtxer r0 /* clear integer exception register */ - lis r1,0x0002 /* set CE bit (Critical Exceptions) */ - ori r1,r1,0x1200 /* set ME/DE bit */ - mtmsr r1 /* change MSR */ - isync - - /* Enable Time Base and Select Time Base Clock */ - lis r0,HID0_EMCP@h /* Enable machine check */ - ori r0,r0,0x4000 /* time base is processor clock */ -#if defined(CONFIG_ENABLE_36BIT_PHYS) - ori r0,r0,0x0080 /* enable MAS7 updates */ -#endif - mtspr HID0,r0 - -#if defined(CONFIG_ADDR_STREAMING) - li r0,0x3000 -#else - li r0,0x1000 -#endif - mtspr HID1,r0 - - /* Enable Branch Prediction */ -#if defined(CONFIG_BTB) - li r0,0x201 /* BBFI = 1, BPEN = 1 */ - mtspr BUCSR,r0 -#endif - -#if defined(CFG_INIT_DBCR) - lis r1,0xffff - ori r1,r1,0xffff - mtspr DBSR,r1 /* Clear all status bits */ - lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */ - ori r0,r0,CFG_INIT_DBCR@l - mtspr DBCR0,r0 -#endif - -/* L1 DCache is used for initial RAM */ - mfspr r2, L1CSR0 - ori r2, r2, 0x0003 - oris r2, r2, 0x0001 - mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */ - isync - - /* Allocate Initial RAM in data cache. - */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l - li r2, 512 /* 512*32=16K */ - mtctr r2 - li r0, 0 -1: - dcbz r0, r3 - dcbtls 0,r0, r3 - addi r3, r3, 32 - bdnz 1b - -#ifndef CFG_RAMBOOT - /* Calculate absolute address in FLASH and jump there */ - /*--------------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: -#endif /* CFG_RAMBOOT */ - - /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l - - li r0,0 - stwu r0,-4(r1) - stwu r0,-4(r1) /* Terminate call chain */ - - stwu r1,-8(r1) /* Save back chain and move SP */ - lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0, RESET_VECTOR@l - stwu r1,-8(r1) /* Save back chain and move SP */ - stw r0,+12(r1) /* Save return addr (underflow vect) */ - - GET_GOT - bl cpu_init_f - bl icache_enable - bl board_init_f - isync - -/* --FIXME-- machine check with MCSRRn and rfmci */ - - .globl _start_of_vectors -_start_of_vectors: -#if 0 -/* Critical input. */ - CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException) -#endif -/* Machine check --FIXME-- Should be MACH_EXCEPTION */ - CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x0300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x0400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException) - -/* Alignment exception. */ - . = 0x0600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - -/* Program check exception */ - . = 0x0700 -ProgramCheck: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - - /* No FPU on MPC85xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) - - . = 0x0900 -/* - * r0 - SYSCALL number - * r3-... arguments - */ -SystemCall: - addis r11,r0,0 /* get functions table addr */ - ori r11,r11,0 /* Note: this code is patched in trap_init */ - addis r12,r0,0 /* get number of functions */ - ori r12,r12,0 - - cmplw 0, r0, r12 - bge 1f - - rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ - add r11,r11,r0 - lwz r11,0(r11) - - li r20,0xd00-4 /* Get stack pointer */ - lwz r12,0(r20) - subi r12,r12,12 /* Adjust stack pointer */ - li r0,0xc00+_end_back-SystemCall - cmplw 0, r0, r12 /* Check stack overflow */ - bgt 1f - stw r12,0(r20) - - mflr r0 - stw r0,0(r12) - mfspr r0,SRR0 - stw r0,4(r12) - mfspr r0,SRR1 - stw r0,8(r12) - - li r12,0xc00+_back-SystemCall - mtlr r12 - mtspr SRR0,r11 - -1: SYNC - rfi -_back: - - mfmsr r11 /* Disable interrupts */ - li r12,0 - ori r12,r12,MSR_EE - andc r11,r11,r12 - SYNC /* Some chip revs need this... */ - mtmsr r11 - SYNC - - li r12,0xd00-4 /* restore regs */ - lwz r12,0(r12) - - lwz r11,0(r12) - mtlr r11 - lwz r11,4(r12) - mtspr SRR0,r11 - lwz r11,8(r12) - mtspr SRR1,r11 - - addi r12,r12,12 /* Adjust stack pointer */ - li r20,0xd00-4 - stw r12,0(r20) - - SYNC - rfi -_end_back: - - STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) - STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) - STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) - - STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) - STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) - - CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x2100 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -crit_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr 990,r2 /* SRR2 */ - mtspr 991,r0 /* SRR3 */ - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfci - -/* Cache functions. -*/ -invalidate_icache: - mfspr r0,L1CSR1 - ori r0,r0,0x0002 - mtspr L1CSR1,r0 - isync - blr /* entire I cache */ - -invalidate_dcache: - mfspr r0,L1CSR0 - ori r0,r0,0x0002 - msync - isync - mtspr L1CSR0,r0 - isync - blr - - .globl icache_enable -icache_enable: - mflr r8 - bl invalidate_icache - mtlr r8 - isync - mfspr r4,L1CSR1 - ori r4,r4,0x0001 - oris r4,r4,0x0001 - mtspr L1CSR1,r4 - isync - blr - - .globl icache_disable -icache_disable: - mfspr r0,L1CSR1 - lis r1,0xfffffffe@h - ori r1,r1,0xfffffffe@l - and r0,r0,r1 - mtspr L1CSR1,r0 - isync - blr - - .globl icache_status -icache_status: - mfspr r3,L1CSR1 - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl dcache_enable -dcache_enable: - mflr r8 - bl invalidate_dcache - mtlr r8 - isync - mfspr r0,L1CSR0 - ori r0,r0,0x0001 - oris r0,r0,0x0001 - msync - isync - mtspr L1CSR0,r0 - isync - blr - - .globl dcache_disable -dcache_disable: - mfspr r0,L1CSR0 - lis r1,0xfffffffe@h - ori r1,r1,0xfffffffe@l - and r0,r0,r1 - msync - isync - mtspr L1CSR0,r0 - isync - blr - - .globl dcache_status -dcache_status: - mfspr r3,L1CSR0 - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl get_pir -get_pir: - mfspr r3, PIR - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - .globl get_svr -get_svr: - mfspr r3, SVR - blr - - .globl wr_tcr -wr_tcr: - mtspr TCR, r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl out16 -out16: - sth r4,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl out16r -out16r: - sthbrx r4,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl out32r -out32r: - stwbrx r4,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl in16 -in16: - lhz r3,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ - .globl in16r -in16r: - lhbrx r3,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0x0000(3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ - .globl in32r -in32r: - lwbrx r3,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*-------------------------------------------------------------------------- - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - *-------------------------------------------------------------------------- */ - - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcSync */ -/* Description: Processor Synchronize */ -/* Input: none. */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcSync -ppcSync: - sync - blr - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Init Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l - lwz r5,GOT(__init_end) - sub r5,r5,r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r14, r14, r15 - /* the the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - - /* - * Re-point the IVPR at RAM - */ - mtspr IVPR,r10 - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr /* NEVER RETURNS! */ - -in_ram: - - /* - * Relocation Function, r14 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - add r0,r0,r11 - stw r0,0(r3) - bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ -2: li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Init Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - li r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET - bl trap_reloc - li r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET - bl trap_reloc - li r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET - bl trap_reloc - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - bl trap_reloc - li r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET - bl trap_reloc - li r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - lis r7,0x0 - mtspr IVPR, r7 - - mtlr r4 /* restore link register */ - blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr - -#ifdef CFG_INIT_RAM_LOCK -.globl unlock_ram_in_cache -unlock_ram_in_cache: - /* invalidate the INIT_RAM section */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2,512 - mtctr r2 -1: icbi r0, r3 - dcbi r0, r3 - addi r3, r3, 32 - bdnz 1b - sync /* Wait for all icbi to complete on bus */ - isync - blr -#endif diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c deleted file mode 100644 index a87eed2..0000000 --- a/cpu/mpc85xx/traps.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * linux/arch/ppc/kernel/traps.c - * - * Copyright (C) 2003 Motorola - * Modified by Xianghua Xiao(x.xiao@motorola.com) - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -int (*debugger_exception_handler)(struct pt_regs *) = 0; -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* - * End of memory as shown by board info and determined by DDR setup. - */ -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) - - -static __inline__ void set_tsr(unsigned long val) -{ - asm volatile("mtspr 0x150, %0" : : "r" (val)); -} - -static __inline__ unsigned long get_esr(void) -{ - unsigned long val; - asm volatile("mfspr %0, 0x03e" : "=r" (val) :); - return val; -} - -#define ESR_MCI 0x80000000 -#define ESR_PIL 0x08000000 -#define ESR_PPR 0x04000000 -#define ESR_PTR 0x02000000 -#define ESR_DST 0x00800000 -#define ESR_DIZ 0x00400000 -#define ESR_U0F 0x00008000 - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -/* - * Trap & Exception support - */ - -void -print_backtrace(unsigned long *sp) -{ - DECLARE_GLOBAL_DATA_PTR; - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs * regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -void -_exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void -CritcalInputException(struct pt_regs *regs) -{ - panic("Critical Input Exception"); -} - -void -MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void -AlignmentException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void -ProgramCheckException(struct pt_regs *regs) -{ - long esr_val; - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - show_regs(regs); - - esr_val = get_esr(); - if( esr_val & ESR_PIL ) - printf( "** Illegal Instruction **\n" ); - else if( esr_val & ESR_PPR ) - printf( "** Privileged Instruction **\n" ); - else if( esr_val & ESR_PTR ) - printf( "** Trap Instruction **\n" ); - - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void -PITException(struct pt_regs *regs) -{ - /* - * Reset PIT interrupt - */ - set_tsr(0x0c000000); - - /* - * Call timer_interrupt routine in interrupts.c - */ - timer_interrupt(NULL); -} - - -void -UnknownException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -void -DebugException(struct pt_regs *regs) -{ - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int -addr_probe(uint *addr) -{ - return 0; -} diff --git a/cpu/mpc8xx/Makefile b/cpu/mpc8xx/Makefile deleted file mode 100644 index de75fad..0000000 --- a/cpu/mpc8xx/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -# CFLAGS += -DET_DEBUG - -LIB = lib$(CPU).a - -START = start.o kgdb.o -OBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \ - fec.o i2c.o interrupts.o lcd.o scc.o \ - serial.o speed.o spi.o \ - traps.o upatch.o video.o -SOBJS = plprcr_write.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) kgdb.o - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/mpc8xx/bedbug_860.c b/cpu/mpc8xx/bedbug_860.c deleted file mode 100644 index e91a100..0000000 --- a/cpu/mpc8xx/bedbug_860.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Bedbug Functions specific to the MPC860 chip - */ - -#include -#include -#include -#include -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_8xx) - -#define MAX_BREAK_POINTS 2 - -extern CPU_DEBUG_CTX bug_ctx; - -void bedbug860_init __P((void)); -void bedbug860_do_break __P((cmd_tbl_t*,int,int,char*[])); -void bedbug860_break_isr __P((struct pt_regs*)); -int bedbug860_find_empty __P((void)); -int bedbug860_set __P((int,unsigned long)); -int bedbug860_clear __P((int)); - - -/* ====================================================================== - * Initialize the global bug_ctx structure for the MPC860. Clear all - * of the breakpoints. - * ====================================================================== */ - -void bedbug860_init( void ) -{ - int i; - /* -------------------------------------------------- */ - - bug_ctx.hw_debug_enabled = 0; - bug_ctx.stopped = 0; - bug_ctx.current_bp = 0; - bug_ctx.regs = NULL; - - bug_ctx.do_break = bedbug860_do_break; - bug_ctx.break_isr = bedbug860_break_isr; - bug_ctx.find_empty = bedbug860_find_empty; - bug_ctx.set = bedbug860_set; - bug_ctx.clear = bedbug860_clear; - - for( i = 1; i <= MAX_BREAK_POINTS; ++i ) - (*bug_ctx.clear)( i ); - - puts ("BEDBUG:ready\n"); - return; -} /* bedbug_init_breakpoints */ - - - -/* ====================================================================== - * Set/clear/show one of the hardware breakpoints for the 860. The "off" - * string will disable a specific breakpoint. The "show" string will - * display the current breakpoints. Otherwise an address will set a - * breakpoint at that address. Setting a breakpoint uses the CPU-specific - * set routine which will assign a breakpoint number. - * ====================================================================== */ - -void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc, - char *argv[]) -{ - long addr = 0; /* Address to break at */ - int which_bp; /* Breakpoint number */ - /* -------------------------------------------------- */ - - if (argc < 2) - { - printf ("Usage:\n%s\n", cmdtp->usage); - return; - } - - /* Turn off a breakpoint */ - - if( strcmp( argv[ 1 ], "off" ) == 0 ) - { - if( bug_ctx.hw_debug_enabled == 0 ) - { - printf( "No breakpoints enabled\n" ); - return; - } - - which_bp = simple_strtoul( argv[ 2 ], NULL, 10 ); - - if( bug_ctx.clear ) - (*bug_ctx.clear)( which_bp ); - - printf( "Breakpoint %d removed\n", which_bp ); - return; - } - - /* Show a list of breakpoints */ - - if( strcmp( argv[ 1 ], "show" ) == 0 ) - { - for( which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp ) - { - - switch( which_bp ) - { - case 1: addr = GET_CMPA(); break; - case 2: addr = GET_CMPB(); break; - case 3: addr = GET_CMPC(); break; - case 4: addr = GET_CMPD(); break; - } - - printf( "Breakpoint [%d]: ", which_bp ); - if( addr == 0 ) - printf( "NOT SET\n" ); - else - disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); - } - return; - } - - /* Set a breakpoint at the address */ - - if( !isdigit( argv[ 1 ][ 0 ])) - { - printf ("Usage:\n%s\n", cmdtp->usage); - return; - } - - addr = simple_strtoul( argv[ 1 ], NULL, 16 ) & 0xfffffffc; - - if(( bug_ctx.set ) && ( which_bp = (*bug_ctx.set)( 0, addr )) > 0 ) - { - printf( "Breakpoint [%d]: ", which_bp ); - disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX ); - } - - return; -} /* bedbug860_do_break */ - - - -/* ====================================================================== - * Handle a breakpoint. First determine which breakpoint was hit by - * looking at the DeBug Status Register (DBSR), clear the breakpoint - * and enter a mini main loop. Stay in the loop until the stopped flag - * in the debug context is cleared. - * ====================================================================== */ - -void bedbug860_break_isr( struct pt_regs *regs ) -{ - unsigned long addr; /* Address stopped at */ - unsigned long cause; /* Address stopped at */ - /* -------------------------------------------------- */ - - cause = GET_ICR(); - - if( !(cause & 0x00000004)) { - printf( "Not an instruction breakpoint (ICR 0x%08lx)\n", cause ); - return; - } - - addr = regs->nip; - - if( addr == GET_CMPA() ) - { - bug_ctx.current_bp = 1; - } - else if( addr == GET_CMPB() ) - { - bug_ctx.current_bp = 2; - } - else if( addr == GET_CMPC() ) - { - bug_ctx.current_bp = 3; - } - else if( addr == GET_CMPD() ) - { - bug_ctx.current_bp = 4; - } - - bedbug_main_loop( addr, regs ); - return; -} /* bedbug860_break_isr */ - - - -/* ====================================================================== - * Look through all of the hardware breakpoints available to see if one - * is unused. - * ====================================================================== */ - -int bedbug860_find_empty( void ) -{ - /* -------------------------------------------------- */ - - if( GET_CMPA() == 0 ) - return 1; - - if( GET_CMPB() == 0 ) - return 2; - - if( GET_CMPC() == 0 ) - return 3; - - if( GET_CMPD() == 0 ) - return 4; - - return 0; -} /* bedbug860_find_empty */ - - - -/* ====================================================================== - * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint - * number, otherwise reassign the given breakpoint. If hardware debugging - * is not enabled, then turn it on via the MSR and DBCR0. Set the break - * address in the appropriate IACx register and enable proper address - * beakpoint in DBCR0. - * ====================================================================== */ - -int bedbug860_set( int which_bp, unsigned long addr ) -{ - /* -------------------------------------------------- */ - - /* Only look if which_bp == 0, else use which_bp */ - if(( bug_ctx.find_empty ) && ( !which_bp ) && - ( which_bp = (*bug_ctx.find_empty)()) == 0 ) - { - printf( "All breakpoints in use\n" ); - return 0; - } - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # %d\n", which_bp ); - return 0; - } - - if( ! bug_ctx.hw_debug_enabled ) - { - bug_ctx.hw_debug_enabled = 1; - SET_DER( GET_DER() | 0x00000004 ); - } - - switch( which_bp ) - { - case 1: - SET_CMPA( addr ); - SET_ICTRL( GET_ICTRL() | 0x80080800 ); /* CTA=Equal,IW0=Match A,SIW0EN */ - break; - - case 2: - SET_CMPB( addr ); - SET_ICTRL( GET_ICTRL() | 0x10020400 ); /* CTB=Equal,IW1=Match B,SIW1EN */ - break; - - case 3: - SET_CMPC( addr ); - SET_ICTRL( GET_ICTRL() | 0x02008200 ); /* CTC=Equal,IW2=Match C,SIW2EN */ - break; - - case 4: - SET_CMPD( addr ); - SET_ICTRL( GET_ICTRL() | 0x00404100 ); /* CTD=Equal,IW3=Match D,SIW3EN */ - break; - } - - return which_bp; -} /* bedbug860_set */ - - - -/* ====================================================================== - * Disable a specific breakoint by setting the appropriate IACx register - * to zero and claring the instruction address breakpoint in DBCR0. - * ====================================================================== */ - -int bedbug860_clear( int which_bp ) -{ - /* -------------------------------------------------- */ - - if( which_bp < 1 || which_bp > MAX_BREAK_POINTS ) - { - printf( "Invalid break point # (%d)\n", which_bp ); - return -1; - } - - switch( which_bp ) - { - case 1: - SET_CMPA( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x80080800 ); /* CTA=Equal,IW0=Match A,SIW0EN */ - break; - - case 2: - SET_CMPB( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x10020400 ); /* CTB=Equal,IW1=Match B,SIW1EN */ - break; - - case 3: - SET_CMPC( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x02008200 ); /* CTC=Equal,IW2=Match C,SIW2EN */ - break; - - case 4: - SET_CMPD( 0 ); - SET_ICTRL( GET_ICTRL() & ~0x00404100 ); /* CTD=Equal,IW3=Match D,SIW3EN */ - break; - } - - return 0; -} /* bedbug860_clear */ - - -/* ====================================================================== */ -#endif diff --git a/cpu/mpc8xx/commproc.c b/cpu/mpc8xx/commproc.c deleted file mode 100644 index 75740e0..0000000 --- a/cpu/mpc8xx/commproc.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifdef CFG_ALLOC_DPRAM - -int dpram_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Reclaim the DP memory for our use. */ - gd->dp_alloc_base = CPM_DATAONLY_BASE; - gd->dp_alloc_top = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE; - - return (0); -} - -/* Allocate some memory from the dual ported ram. We may want to - * enforce alignment restrictions, but right now everyone is a good - * citizen. - */ -uint dpram_alloc (uint size) -{ - DECLARE_GLOBAL_DATA_PTR; - uint addr = gd->dp_alloc_base; - - if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) - return (CPM_DP_NOSPACE); - - gd->dp_alloc_base += size; - - return addr; -} - -uint dpram_base (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - return gd->dp_alloc_base; -} - -/* Allocate some memory from the dual ported ram. We may want to - * enforce alignment restrictions, but right now everyone is a good - * citizen. - */ -uint dpram_alloc_align (uint size, uint align) -{ - DECLARE_GLOBAL_DATA_PTR; - - uint addr, mask = align - 1; - - addr = (gd->dp_alloc_base + mask) & ~mask; - - if ((addr + size) >= gd->dp_alloc_top) - return (CPM_DP_NOSPACE); - - gd->dp_alloc_base = addr + size; - - return addr; -} - -uint dpram_base_align (uint align) -{ - DECLARE_GLOBAL_DATA_PTR; - - uint mask = align - 1; - - return (gd->dp_alloc_base + mask) & ~mask; -} -#endif /* CFG_ALLOC_DPRAM */ - -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - -void post_word_store (ulong a) -{ - volatile void *save_addr = - ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR; - - *(volatile ulong *) save_addr = a; -} - -ulong post_word_load (void) -{ - volatile void *save_addr = - ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR; - - return *(volatile ulong *) save_addr; -} - -#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)( ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + - CPM_BOOTCOUNT_ADDR ); - - save_addr[0] = a; - save_addr[1] = BOOTCOUNT_MAGIC; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)( ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + - CPM_BOOTCOUNT_ADDR ); - - if (save_addr[1] != BOOTCOUNT_MAGIC) - return 0; - else - return save_addr[0]; -} - -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/cpu/mpc8xx/config.mk b/cpu/mpc8xx/config.mk deleted file mode 100644 index bfa6625..0000000 --- a/cpu/mpc8xx/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing - -PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -ffixed-r29 -mstring -mcpu=860 -msoft-float diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c deleted file mode 100644 index 4a32986..0000000 --- a/cpu/mpc8xx/cpu.c +++ /dev/null @@ -1,631 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * m8xx.c - * - * CPU specific code - * - * written or collected and sometimes rewritten by - * Magnus Damm - * - * minor modifications by - * Wolfgang Denk - */ - -#include -#include -#include -#include -#include - -static char *cpu_warning = "\n " \ - "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***"; - -#if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \ - !defined(CONFIG_MPC862)) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - char *id_str = -# if defined(CONFIG_MPC855) - "PC855"; -# elif defined(CONFIG_MPC860P) - "PC860P"; -# else - NULL; -# endif - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - char pre = 'X'; - char *mid = "xx"; - char *suf; - - /* the highest 16 bits should be 0x0050 for a 860 */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); - m = 0; - - /* - * Some boards use sockets so different CPUs can be used. - * We have to check chip version in run time. - */ - switch (k) { - case 0x00020001: pre = 'P'; suf = ""; break; - case 0x00030001: suf = ""; break; - case 0x00120003: suf = "A"; break; - case 0x00130003: suf = "A3"; break; - - case 0x00200004: suf = "B"; break; - - case 0x00300004: suf = "C"; break; - case 0x00310004: suf = "C1"; m = 1; break; - - case 0x00200064: mid = "SR"; suf = "B"; break; - case 0x00300065: mid = "SR"; suf = "C"; break; - case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break; - case 0x05010000: suf = "D3"; m = 1; break; - case 0x05020000: suf = "D4"; m = 1; break; - /* this value is not documented anywhere */ - case 0x40000000: pre = 'P'; suf = "D"; m = 1; break; - /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */ - case 0x08000003: pre = 'M'; suf = ""; m = 1; - if (id_str == NULL) - id_str = -# if defined(CONFIG_MPC852T) - "PC852T"; -# elif defined(CONFIG_MPC859T) - "PC859T"; -# elif defined(CONFIG_MPC859DSL) - "PC859DSL"; -# elif defined(CONFIG_MPC866T) - "PC866T"; -# else - "PC866x"; /* Unknown chip from MPC866 family */ -# endif - break; - case 0x09000000: pre = 'M'; mid = suf = ""; m = 1; - if (id_str == NULL) - id_str = "PC885"; /* 870/875/880/885 */ - break; - - default: suf = NULL; break; - } - - if (id_str == NULL) - id_str = "PC86x"; /* Unknown 86x chip */ - if (suf) - printf ("%c%s%sZPnn%s", pre, id_str, mid, suf); - else - printf ("unknown M%s (0x%08x)", id_str, k); - - -#if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX) - printf (" at %s MHz [%d.%d...%d.%d MHz]\n ", - strmhz (buf, clock), - CFG_8xx_CPUCLK_MIN / 1000000, - ((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000, - CFG_8xx_CPUCLK_MAX / 1000000, - ((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000 - ); -#else - printf (" at %s MHz: ", strmhz (buf, clock)); -#endif - printf ("%u kB I-Cache %u kB D-Cache", - checkicache () >> 10, - checkdcache () >> 10 - ); - - /* do we have a FEC (860T/P or 852/859/866/885)? */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - printf (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - -#ifdef DEBUG - if(clock != measure_gclk()) { - printf ("clock %ldHz != %dHz\n", clock, measure_gclk()); - } -#endif - - return 0; -} - -#elif defined(CONFIG_MPC862) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - char pre = 'X'; - char *mid = "xx"; - char *suf; - - /* the highest 16 bits should be 0x0050 for a 8xx */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); - m = 0; - - switch (k) { - - /* this value is not documented anywhere */ - case 0x06000000: mid = "P"; suf = "0"; break; - case 0x06010001: mid = "P"; suf = "A"; m = 1; break; - case 0x07000003: mid = "P"; suf = "B"; m = 1; break; - default: suf = NULL; break; - } - -#ifndef CONFIG_MPC857 - if (suf) - printf ("%cPC862%sZPnn%s", pre, mid, suf); - else - printf ("unknown MPC862 (0x%08x)", k); -#else - if (suf) - printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */ - else - printf ("unknown MPC857 (0x%08x)", k); -#endif - - printf (" at %s MHz:", strmhz (buf, clock)); - - printf (" %u kB I-Cache", checkicache () >> 10); - printf (" %u kB D-Cache", checkdcache () >> 10); - - /* lets check and see if we're running on a 862T (or P?) */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - printf (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - - return 0; -} - -#elif defined(CONFIG_MPC823) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - char *suf; - - /* the highest 16 bits should be 0x0050 for a 8xx */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); - m = 0; - - switch (k) { - /* MPC823 */ - case 0x20000000: suf = "0"; break; - case 0x20010000: suf = "0.1"; break; - case 0x20020000: suf = "Z2/3"; break; - case 0x20020001: suf = "Z3"; break; - case 0x21000000: suf = "A"; break; - case 0x21010000: suf = "B"; m = 1; break; - case 0x21010001: suf = "B2"; m = 1; break; - /* MPC823E */ - case 0x24010000: suf = NULL; - puts ("PPC823EZTnnB2"); - m = 1; - break; - default: - suf = NULL; - printf ("unknown MPC823 (0x%08x)", k); - break; - } - if (suf) - printf ("PPC823ZTnn%s", suf); - - printf (" at %s MHz:", strmhz (buf, clock)); - - printf (" %u kB I-Cache", checkicache () >> 10); - printf (" %u kB D-Cache", checkdcache () >> 10); - - /* lets check and see if we're running on a 860T (or P?) */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - puts (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - - return 0; -} - -#elif defined(CONFIG_MPC850) - -static int check_CPU (long clock, uint pvr, uint immr) -{ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint k, m; - char buf[32]; - - /* the highest 16 bits should be 0x0050 for a 8xx */ - - if ((pvr >> 16) != 0x0050) - return -1; - - k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); - m = 0; - - switch (k) { - case 0x20020001: - printf ("XPC850xxZT"); - break; - case 0x21000065: - printf ("XPC850xxZTA"); - break; - case 0x21010067: - printf ("XPC850xxZTB"); - m = 1; - break; - case 0x21020068: - printf ("XPC850xxZTC"); - m = 1; - break; - default: - printf ("unknown MPC850 (0x%08x)", k); - } - printf (" at %s MHz:", strmhz (buf, clock)); - - printf (" %u kB I-Cache", checkicache () >> 10); - printf (" %u kB D-Cache", checkdcache () >> 10); - - /* lets check and see if we're running on a 850T (or P?) */ - - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { - printf (" FEC present"); - } - - if (!m) { - puts (cpu_warning); - } - - putc ('\n'); - - return 0; -} -#else -#error CPU undefined -#endif -/* ------------------------------------------------------------------------- */ - -int checkcpu (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong clock = gd->cpu_clk; - uint immr = get_immr (0); /* Return full IMMR contents */ - uint pvr = get_pvr (); - - puts ("CPU: "); - - /* 850 has PARTNUM 20 */ - /* 801 has PARTNUM 10 */ - return check_CPU (clock, pvr, immr); -} - -/* ------------------------------------------------------------------------- */ -/* L1 i-cache */ -/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ -/* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */ - -int checkicache (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - u32 cacheon = rd_ic_cst () & IDC_ENABLED; - -#ifdef CONFIG_IP86x - u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ -#else - u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ -#endif - u32 m; - u32 lines = -1; - - wr_ic_cst (IDC_UNALL); - wr_ic_cst (IDC_INVALL); - wr_ic_cst (IDC_DISABLE); - __asm__ volatile ("isync"); - - while (!((m = rd_ic_cst ()) & IDC_CERR2)) { - wr_ic_adr (k); - wr_ic_cst (IDC_LDLCK); - __asm__ volatile ("isync"); - - lines++; - k += 0x10; /* the number of bytes in a cacheline */ - } - - wr_ic_cst (IDC_UNALL); - wr_ic_cst (IDC_INVALL); - - if (cacheon) - wr_ic_cst (IDC_ENABLE); - else - wr_ic_cst (IDC_DISABLE); - - __asm__ volatile ("isync"); - - return lines << 4; -}; - -/* ------------------------------------------------------------------------- */ -/* L1 d-cache */ -/* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ -/* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */ -/* call with cache disabled */ - -int checkdcache (void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - u32 cacheon = rd_dc_cst () & IDC_ENABLED; - -#ifdef CONFIG_IP86x - u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ -#else - u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ -#endif - u32 m; - u32 lines = -1; - - wr_dc_cst (IDC_UNALL); - wr_dc_cst (IDC_INVALL); - wr_dc_cst (IDC_DISABLE); - - while (!((m = rd_dc_cst ()) & IDC_CERR2)) { - wr_dc_adr (k); - wr_dc_cst (IDC_LDLCK); - lines++; - k += 0x10; /* the number of bytes in a cacheline */ - } - - wr_dc_cst (IDC_UNALL); - wr_dc_cst (IDC_INVALL); - - if (cacheon) - wr_dc_cst (IDC_ENABLE); - else - wr_dc_cst (IDC_DISABLE); - - return lines << 4; -}; - -/* ------------------------------------------------------------------------- */ - -void upmconfig (uint upm, uint * table, uint size) -{ - uint i; - uint addr = 0; - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - for (i = 0; i < size; i++) { - memctl->memc_mdr = table[i]; /* (16-15) */ - memctl->memc_mcr = addr | upm; /* (16-16) */ - addr++; - } -} - -/* ------------------------------------------------------------------------- */ - -#ifndef CONFIG_LWMON - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong msr, addr; - - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */ - - /* Interrupts and MMU off */ - __asm__ volatile ("mtspr 81, 0"); - __asm__ volatile ("mfmsr %0":"=r" (msr)); - - msr &= ~0x1030; - __asm__ volatile ("mtmsr %0"::"r" (msr)); - - /* - * Trying to execute the next instruction at a non-existing address - * should cause a machine check, resulting in reset - */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; -#else - /* - * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE - * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. - * "(ulong)-1" used to be a good choice for many systems... - */ - addr = CFG_MONITOR_BASE - sizeof (ulong); -#endif - ((void (*)(void)) addr) (); - return 1; -} - -#else /* CONFIG_LWMON */ - -/* - * On the LWMON board, the MCLR reset input of the PIC's on the board - * uses a 47K/1n RC combination which has a 47us time constant. The - * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us - * and thus too short to reset the external hardware. So we use the - * watchdog to reset the board. - */ -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - /* prevent triggering the watchdog */ - disable_interrupts (); - - /* make sure the watchdog is running */ - reset_8xx_watchdog ((immap_t *) CFG_IMMR); - - /* wait for watchdog reset */ - while (1) {}; - - /* NOTREACHED */ - return 1; -} - -#endif /* CONFIG_LWMON */ - -/* ------------------------------------------------------------------------- */ - -/* - * Get timebase clock frequency (like cpu_clk in Hz) - * - * See sections 14.2 and 14.6 of the User's Manual - */ -unsigned long get_tbclk (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - uint immr = get_immr (0); /* Return full IMMR contents */ - volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000); - ulong oscclk, factor, pll; - - if (immap->im_clkrst.car_sccr & SCCR_TBS) { - return (gd->cpu_clk / 16); - } - - pll = immap->im_clkrst.car_plprcr; - -#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) - - /* - * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication - * factor is calculated as follows: - * - * MFN - * MFI + ------- - * MFD + 1 - * factor = ----------------- - * (PDF + 1) * 2^S - * - * For older chips, it's just MF field of PLPRCR plus one. - */ - if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ - factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/ - (PLPRCR_val(PDF)+1) / (1<cpu_clk / factor; - - if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { - return (oscclk / 4); - } - return (oscclk / 16); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - reset_8xx_watchdog ((immap_t *) CFG_IMMR); - if (re_enable) - enable_interrupts (); -} -#endif /* CONFIG_WATCHDOG */ - -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON) - -void reset_8xx_watchdog (volatile immap_t * immr) -{ -# if defined(CONFIG_LWMON) - /* - * The LWMON board uses a MAX6301 Watchdog - * with the trigger pin connected to port PA.7 - * - * (The old board version used a MAX706TESA Watchdog, which - * had to be handled exactly the same.) - */ -# define WATCHDOG_BIT 0x0100 - immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ - immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ - immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ - - immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ -# elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) - /* - * The KUP4 boards uses a TPS3705 Watchdog - * with the trigger pin connected to port PA.5 - */ -# define WATCHDOG_BIT 0x0400 - immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ - immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ - immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ - - immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ -# else - /* - * All other boards use the MPC8xx Internal Watchdog - */ - immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */ - immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ -# endif /* CONFIG_LWMON */ -} - -#endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c deleted file mode 100644 index b2c59c6..0000000 --- a/cpu/mpc8xx/cpu_init.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include -#include - -#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) -void cpm_load_patch (volatile immap_t * immr); -#endif - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f (volatile immap_t * immr) -{ -#ifndef CONFIG_MBX - volatile memctl8xx_t *memctl = &immr->im_memctl; -# ifdef CFG_PLPRCR - ulong mfmask; -# endif -#endif - ulong reg; - - /* SYPCR - contains watchdog control (11-9) */ - - immr->im_siu_conf.sc_sypcr = CFG_SYPCR; - -#if defined(CONFIG_WATCHDOG) - reset_8xx_watchdog (immr); -#endif /* CONFIG_WATCHDOG */ - - /* SIUMCR - contains debug pin configuration (11-6) */ -#ifndef CONFIG_SVM_SC8xx - immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR; -#else - immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; -#endif - /* initialize timebase status and control register (11-26) */ - /* unlock TBSCRK */ - - immr->im_sitk.sitk_tbscrk = KAPWR_KEY; - immr->im_sit.sit_tbscr = CFG_TBSCR; - - /* initialize the PIT (11-31) */ - - immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CFG_PISCR; - - /* System integration timers. Don't change EBDF! (15-27) */ - - immr->im_clkrstk.cark_sccrk = KAPWR_KEY; - reg = immr->im_clkrst.car_sccr; - reg &= SCCR_MASK; - reg |= CFG_SCCR; - immr->im_clkrst.car_sccr = reg; - - /* PLL (CPU clock) settings (15-30) */ - - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - -#ifndef CONFIG_MBX /* MBX board does things different */ - - /* If CFG_PLPRCR (set in the various *_config.h files) tries to - * set the MF field, then just copy CFG_PLPRCR over car_plprcr, - * otherwise OR in CFG_PLPRCR so we do not change the current MF - * field value. - * - * For newer (starting MPC866) chips PLPRCR layout is different. - */ -#ifdef CFG_PLPRCR - if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK) - mfmask = PLPRCR_MFACT_MSK; - else - mfmask = PLPRCR_MF_MSK; - - if ((CFG_PLPRCR & mfmask) != 0) - reg = CFG_PLPRCR; /* reset control bits */ - else { - reg = immr->im_clkrst.car_plprcr; - reg &= mfmask; /* isolate MF-related fields */ - reg |= CFG_PLPRCR; /* reset control bits */ - } - immr->im_clkrst.car_plprcr = reg; -#endif - - /* - * Memory Controller: - */ - - /* perform BR0 reset that MPC850 Rev. A can't guarantee */ - reg = memctl->memc_br0; - reg &= BR_PS_MSK; /* Clear everything except Port Size bits */ - reg |= BR_V; /* then add just the "Bank Valid" bit */ - memctl->memc_br0 = reg; - - /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at - * preliminary addresses - these have to be modified later - * when FLASH size has been determined - * - * Depending on the size of the memory region defined by - * CFG_OR0_REMAP some boards (wide address mask) allow to map the - * CFG_MONITOR_BASE, while others (narrower address mask) can't - * map CFG_MONITOR_BASE. - * - * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is - * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000. - * - * If BR0 wasn't loaded with address base 0xff000000, then BR0's - * base address remains as 0x00000000. However, the address mask - * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped - * into the Bank0. - * - * This is why CONFIG_IVMS8 and similar boards must load BR0 with - * CFG_BR0_PRELIM in advance. - * - * [Thanks to Michael Liao for this explanation. - * I owe him a free beer. - wd] - */ - -#if defined(CONFIG_GTH) || \ - defined(CONFIG_HERMES) || \ - defined(CONFIG_ICU862) || \ - defined(CONFIG_IP860) || \ - defined(CONFIG_IVML24) || \ - defined(CONFIG_IVMS8) || \ - defined(CONFIG_LWMON) || \ - defined(CONFIG_MHPC) || \ - defined(CONFIG_PCU_E) || \ - defined(CONFIG_R360MPI) || \ - defined(CONFIG_RMU) || \ - defined(CONFIG_RPXCLASSIC) || \ - defined(CONFIG_RPXLITE) || \ - defined(CONFIG_SPD823TS) - - memctl->memc_br0 = CFG_BR0_PRELIM; -#endif - -#if defined(CFG_OR0_REMAP) - memctl->memc_or0 = CFG_OR0_REMAP; -#endif -#if defined(CFG_OR1_REMAP) - memctl->memc_or1 = CFG_OR1_REMAP; -#endif -#if defined(CFG_OR5_REMAP) - memctl->memc_or5 = CFG_OR5_REMAP; -#endif - - /* now restrict to preliminary range */ - memctl->memc_br0 = CFG_BR0_PRELIM; - memctl->memc_or0 = CFG_OR0_PRELIM; - -#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; -#endif - -#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */ - memctl->memc_br0 = 0; -#endif - -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; -#endif - -#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; -#endif - -#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) - memctl->memc_or4 = CFG_OR4_PRELIM; - memctl->memc_br4 = CFG_BR4_PRELIM; -#endif - -#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) - memctl->memc_or5 = CFG_OR5_PRELIM; - memctl->memc_br5 = CFG_BR5_PRELIM; -#endif - -#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) - memctl->memc_or6 = CFG_OR6_PRELIM; - memctl->memc_br6 = CFG_BR6_PRELIM; -#endif - -#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) - memctl->memc_or7 = CFG_OR7_PRELIM; - memctl->memc_br7 = CFG_BR7_PRELIM; -#endif - -#endif /* ! CONFIG_MBX */ - - /* - * Reset CPM - */ - immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG; - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - -#ifdef CONFIG_MBX - /* - * on the MBX, things are a little bit different: - * - we need to read the VPD to get board information - * - the plprcr is set up dynamically - * - the memory controller is set up dynamically - */ - mbx_init (); -#endif /* CONFIG_MBX */ - -#ifdef CONFIG_RPXCLASSIC - rpxclassic_init (); -#endif - -#if defined(CONFIG_RPXLITE) && defined(CFG_ENV_IS_IN_NVRAM) - rpxlite_init (); -#endif - -#ifdef CFG_RCCR /* must be done before cpm_load_patch() */ - /* write config value */ - immr->im_cpm.cp_rccr = CFG_RCCR; -#endif - -#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) - cpm_load_patch (immr); /* load mpc8xx microcode patch */ -#endif -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r (void) -{ -#if defined(CFG_RTCSC) || defined(CFG_RMDS) - DECLARE_GLOBAL_DATA_PTR; - - bd_t *bd = gd->bd; - volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base); -#endif - -#ifdef CFG_RTCSC - /* Unlock RTSC register */ - immr->im_sitk.sitk_rtcsck = KAPWR_KEY; - /* write config value */ - immr->im_sit.sit_rtcsc = CFG_RTCSC; -#endif - -#ifdef CFG_RMDS - /* write config value */ - immr->im_cpm.cp_rmds = CFG_RMDS; -#endif - return (0); -} diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c deleted file mode 100644 index d2f5d88..0000000 --- a/cpu/mpc8xx/fec.c +++ /dev/null @@ -1,1020 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#undef ET_DEBUG - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && \ - (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)) - -/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */ -#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2) -#define CONFIG_ETHER_ON_FEC1 1 -#endif - -/* define WANT_MII when MII support is required */ -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY) -#define WANT_MII -#else -#undef WANT_MII -#endif - -#if defined(WANT_MII) -#include - -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) -#error "CONFIG_MII has to be defined!" -#endif - -#endif - -#if defined(CONFIG_RMII) && !defined(WANT_MII) -#error RMII support is unusable without a working PHY. -#endif - -#ifdef CFG_DISCOVER_PHY -static int mii_discover_phy(struct eth_device *dev); -#endif - -int fec8xx_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -static struct ether_fcc_info_s -{ - int ether_index; - int fecp_offset; - int phy_addr; - int actual_phy_addr; - int initialized; -} - ether_fcc_info[] = { -#if defined(CONFIG_ETHER_ON_FEC1) - { - 0, - offsetof(immap_t, im_cpm.cp_fec1), -#if defined(CONFIG_FEC1_PHY) - CONFIG_FEC1_PHY, -#else - -1, /* discover */ -#endif - -1, - 0, - - }, -#endif -#if defined(CONFIG_ETHER_ON_FEC2) - { - 1, - offsetof(immap_t, im_cpm.cp_fec2), -#if defined(CONFIG_FEC2_PHY) - CONFIG_FEC2_PHY, -#else - -1, -#endif - -1, - 0, - }, -#endif -}; - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 100 - -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 -#define PKT_MAXBLR_SIZE 1520 - -#ifdef __GNUC__ -static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8))); -#else -#error txbuf must be aligned. -#endif - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FEC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx = NULL; - -static int fec_send(struct eth_device* dev, volatile void *packet, int length); -static int fec_recv(struct eth_device* dev); -static int fec_init(struct eth_device* dev, bd_t * bd); -static void fec_halt(struct eth_device* dev); - -int fec_initialize(bd_t *bis) -{ - struct eth_device* dev; - struct ether_fcc_info_s *efis; - int i; - - for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) { - - dev = malloc(sizeof(*dev)); - if (dev == NULL) - hang(); - - memset(dev, 0, sizeof(*dev)); - - /* for FEC1 make sure that the name of the interface is the same - as the old one for compatibility reasons */ - if (i == 0) { - sprintf (dev->name, "FEC ETHERNET"); - } else { - sprintf (dev->name, "FEC%d ETHERNET", - ether_fcc_info[i].ether_index + 1); - } - - efis = ðer_fcc_info[i]; - - /* - * reset actual phy addr - */ - efis->actual_phy_addr = -1; - - dev->priv = efis; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - eth_register(dev); - -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) - miiphy_register(dev->name, - fec8xx_miiphy_read, fec8xx_miiphy_write); -#endif - } - return 1; -} - -static int fec_send(struct eth_device* dev, volatile void *packet, int length) -{ - int j, rc; - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); - - /* section 16.9.23.3 - * Wait for ready - */ - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) { - printf("TX not ready\n"); - } - - rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST; - __asm__ ("eieio"); - - /* Activate transmit Buffer Descriptor polling */ - fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */ - - j = 0; - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) { - printf("TX timeout\n"); - } -#ifdef ET_DEBUG - printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", - __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc, - (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2); -#endif - /* return only status bits */; - rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS); - - txIdx = (txIdx + 1) % TX_BUF_CNT; - - return rc; -} - -static int fec_recv (struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = - (volatile fec_t *) (CFG_IMMR + efis->fecp_offset); - int length; - - for (;;) { - /* section 16.9.23.2 */ - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { -#ifdef ET_DEBUG - printf ("%s[%d] err: %x\n", - __FUNCTION__, __LINE__, - rtx->rxbd[rxIdx].cbd_sc); -#endif - } else { - volatile uchar *rx = NetRxPackets[rxIdx]; - - length -= 4; - -#if (CONFIG_COMMANDS & CFG_CMD_CDP) - if ((rx[0] & 1) != 0 - && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0 - && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0) - rx = NULL; -#endif - /* - * Pass the packet up to the protocol layers. - */ - if (rx != NULL) - NetReceive (rx, length); - } - - /* Give the buffer back to the FEC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - - __asm__ ("eieio"); - - /* Try to fill Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - } - - return length; -} - -/************************************************************** - * - * FEC Ethernet Initialization Routine - * - *************************************************************/ - -#define FEC_ECNTRL_PINMUX 0x00000004 -#define FEC_ECNTRL_ETHER_EN 0x00000002 -#define FEC_ECNTRL_RESET 0x00000001 - -#define FEC_RCNTRL_BC_REJ 0x00000010 -#define FEC_RCNTRL_PROM 0x00000008 -#define FEC_RCNTRL_MII_MODE 0x00000004 -#define FEC_RCNTRL_DRT 0x00000002 -#define FEC_RCNTRL_LOOP 0x00000001 - -#define FEC_TCNTRL_FDEN 0x00000004 -#define FEC_TCNTRL_HBC 0x00000002 -#define FEC_TCNTRL_GTS 0x00000001 - -#define FEC_RESET_DELAY 50 - -#if defined(CONFIG_RMII) - -static inline void fec_10Mbps(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - int fecidx = efis->ether_index; - uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; - - if ((unsigned int)fecidx >= 2) - hang(); - - ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= mask; -} - -static inline void fec_100Mbps(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - int fecidx = efis->ether_index; - uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; - - if ((unsigned int)fecidx >= 2) - hang(); - - ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~mask; -} - -#endif - -static inline void fec_full_duplex(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); - - fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT; - fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */ -} - -static inline void fec_half_duplex(struct eth_device *dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); - - fecp->fec_r_cntrl |= FEC_RCNTRL_DRT; - fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */ -} - -static void fec_pin_init(int fecidx) -{ - DECLARE_GLOBAL_DATA_PTR; - bd_t *bd = gd->bd; - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile fec_t *fecp; - - /* - * only two FECs please - */ - if ((unsigned int)fecidx >= 2) - hang(); - - if (fecidx == 0) - fecp = &immr->im_cpm.cp_fec1; - else - fecp = &immr->im_cpm.cp_fec2; - - /* - * Set MII speed to 2.5 MHz or slightly below. - * * According to the MPC860T (Rev. D) Fast ethernet controller user - * * manual (6.2.14), - * * the MII management interface clock must be less than or equal - * * to 2.5 MHz. - * * This MDC frequency is equal to system clock / (2 * MII_SPEED). - * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz. - */ - fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; - -#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) - /* our PHYs are the limit at 2.5 MHz */ - fecp->fec_mii_speed <<= 1; -#endif - -#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) - /* use MDC for MII */ - immr->im_ioport.iop_pdpar |= 0x0080; - immr->im_ioport.iop_pddir &= ~0x0080; -#endif - - if (fecidx == 0) { -#if defined(CONFIG_ETHER_ON_FEC1) - -#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ - -#if !defined(CONFIG_RMII) - - immr->im_ioport.iop_papar |= 0xf830; - immr->im_ioport.iop_padir |= 0x0830; - immr->im_ioport.iop_padir &= ~0xf000; - - immr->im_cpm.cp_pbpar |= 0x00001001; - immr->im_cpm.cp_pbdir &= ~0x00001001; - - immr->im_ioport.iop_pcpar |= 0x000c; - immr->im_ioport.iop_pcdir &= ~0x000c; - - immr->im_cpm.cp_pepar |= 0x00000003; - immr->im_cpm.cp_pedir |= 0x00000003; - immr->im_cpm.cp_peso &= ~0x00000003; - - immr->im_cpm.cp_cptr &= ~0x00000100; - -#else - -#if !defined(CONFIG_FEC1_PHY_NORXERR) - immr->im_ioport.iop_papar |= 0x1000; - immr->im_ioport.iop_padir &= ~0x1000; -#endif - immr->im_ioport.iop_papar |= 0xe810; - immr->im_ioport.iop_padir |= 0x0810; - immr->im_ioport.iop_padir &= ~0xe000; - - immr->im_cpm.cp_pbpar |= 0x00000001; - immr->im_cpm.cp_pbdir &= ~0x00000001; - - immr->im_cpm.cp_cptr |= 0x00000100; - immr->im_cpm.cp_cptr &= ~0x00000050; - -#endif /* !CONFIG_RMII */ - -#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) - /* - * Configure all of port D for MII. - */ - immr->im_ioport.iop_pdpar = 0x1fff; - - /* - * Bits moved from Rev. D onward - */ - if ((get_immr(0) & 0xffff) < 0x0501) - immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ - else - immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ -#else - /* - * Configure port A for MII. - */ - -#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY) - - /* - * On the ICU862 board the MII-MDC pin is routed to PD8 pin - * * of CPU, so for this board we need to configure Utopia and - * * enable PD8 to MII-MDC function - */ - immr->im_ioport.iop_pdpar |= 0x4080; -#endif - - /* - * Has Utopia been configured? - */ - if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) { - /* - * YES - Use MUXED mode for UTOPIA bus. - * This frees Port A for use by MII (see 862UM table 41-6). - */ - immr->im_ioport.utmode &= ~0x80; - } else { - /* - * NO - set SPLIT mode for UTOPIA bus. - * - * This doesn't really effect UTOPIA (which isn't - * enabled anyway) but just tells the 862 - * to use port A for MII (see 862UM table 41-6). - */ - immr->im_ioport.utmode |= 0x80; - } -#endif /* !defined(CONFIG_ICU862) */ - -#endif /* CONFIG_ETHER_ON_FEC1 */ - } else if (fecidx == 1) { - -#if defined(CONFIG_ETHER_ON_FEC2) - -#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ - -#if !defined(CONFIG_RMII) - -#warning this configuration is not tested; please report if it works - immr->im_cpm.cp_pepar |= 0x0003fffc; - immr->im_cpm.cp_pedir |= 0x0003fffc; - immr->im_cpm.cp_peso &= ~0x000087fc; - immr->im_cpm.cp_peso |= 0x00037800; - - immr->im_cpm.cp_cptr &= ~0x00000080; -#else - -#if !defined(CONFIG_FEC2_PHY_NORXERR) - immr->im_cpm.cp_pepar |= 0x00000010; - immr->im_cpm.cp_pedir |= 0x00000010; - immr->im_cpm.cp_peso &= ~0x00000010; -#endif - immr->im_cpm.cp_pepar |= 0x00039620; - immr->im_cpm.cp_pedir |= 0x00039620; - immr->im_cpm.cp_peso |= 0x00031000; - immr->im_cpm.cp_peso &= ~0x00008620; - - immr->im_cpm.cp_cptr |= 0x00000080; - immr->im_cpm.cp_cptr &= ~0x00000028; -#endif /* CONFIG_RMII */ - -#endif /* CONFIG_MPC885_FAMILY */ - -#endif /* CONFIG_ETHER_ON_FEC2 */ - - } -} - -static int fec_init (struct eth_device *dev, bd_t * bd) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile fec_t *fecp = - (volatile fec_t *) (CFG_IMMR + efis->fecp_offset); - int i; - - if (efis->ether_index == 0) { -#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */ -#if defined(CONFIG_MPC885ADS) - *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST); -#else - /* configure FADS for fast (FEC) ethernet, half-duplex */ - /* The LXT970 needs about 50ms to recover from reset, so - * wait for it by discovering the PHY before leaving eth_init(). - */ - { - volatile uint *bcsr4 = (volatile uint *) BCSR4; - - *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1)) - | (BCSR4_FETHCFG0 | BCSR4_FETHFDE | - BCSR4_FETHRST); - - /* reset the LXT970 PHY */ - *bcsr4 &= ~BCSR4_FETHRST; - udelay (10); - *bcsr4 |= BCSR4_FETHRST; - udelay (10); - } -#endif /* CONFIG_MPC885ADS */ -#endif /* CONFIG_FADS */ - } - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) { - printf ("FEC_RESET_DELAY timeout\n"); - return 0; - } - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt - */ - fecp->fec_ievent = 0xffc0; - - /* No need to set the IVEC register */ - - /* Set station address - */ -#define ea eth_get_dev()->enetaddr - fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); - fecp->fec_addr_high = (ea[4] << 8) | (ea[5]); -#undef ea - -#if (CONFIG_COMMANDS & CFG_CMD_CDP) - /* - * Turn on multicast address hash table - */ - fecp->fec_hash_table_high = 0xffffffff; - fecp->fec_hash_table_low = 0xffffffff; -#else - /* Clear multicast address hash table - */ - fecp->fec_hash_table_high = 0; - fecp->fec_hash_table_low = 0; -#endif - - /* Set maximum receive buffer size. - */ - fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; - - /* Set maximum frame length - */ - fecp->fec_r_hash = PKT_MAXBUF_SIZE; - - /* - * Setup Buffers and Buffer Desriptors - */ - rxIdx = 0; - txIdx = 0; - - if (!rtx) { -#ifdef CFG_ALLOC_DPRAM - rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + - dpram_alloc_align (sizeof (RTXBD), 8)); -#else - rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE); -#endif - } - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; - } - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Last, Tx CRC - */ - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* Set receive and transmit descriptor base - */ - fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]); - fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]); - - /* Enable MII mode - */ -#if 0 /* Full duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; - fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; -#else /* Half duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; - fecp->fec_x_cntrl = 0; -#endif - - /* Enable big endian and don't care about SDMA FC. - */ - fecp->fec_fun_code = 0x78000000; - - /* - * Setup the pin configuration of the FEC - */ - fec_pin_init (efis->ether_index); - - rxIdx = 0; - txIdx = 0; - - /* - * Now enable the transmit and receive processing - */ - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; - - if (efis->phy_addr == -1) { -#ifdef CFG_DISCOVER_PHY - /* - * wait for the PHY to wake up after reset - */ - efis->actual_phy_addr = mii_discover_phy (dev); - - if (efis->actual_phy_addr == -1) { - printf ("Unable to discover phy!\n"); - return 0; - } -#else - efis->actual_phy_addr = -1; -#endif - } else { - efis->actual_phy_addr = efis->phy_addr; - } -#if defined(CONFIG_MII) && defined(CONFIG_RMII) - - /* the MII interface is connected to FEC1 - * so for the miiphy_xxx function to work we must - * call mii_init since fec_halt messes the thing up - */ - if (efis->ether_index != 0) - mii_init(); - - /* - * adapt the RMII speed to the speed of the phy - */ - if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) { - fec_100Mbps (dev); - } else { - fec_10Mbps (dev); - } -#endif - -#if defined(CONFIG_MII) - /* - * adapt to the half/full speed settings - */ - if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) { - fec_full_duplex (dev); - } else { - fec_half_duplex (dev); - } -#endif - - /* And last, try to fill Rx Buffer Descriptors */ - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ - - efis->initialized = 1; - - return 1; -} - - -static void fec_halt(struct eth_device* dev) -{ - struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); - int i; - - /* avoid halt if initialized; mii gets stuck otherwise */ - if (!efis->initialized) - return; - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) { - printf ("FEC_RESET_DELAY timeout\n"); - return; - } - - efis->initialized = 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) - -/* Make MII read/write commands for the FEC. -*/ - -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18) | \ - (VAL & 0xffff)) - -/* Interrupt events/masks. -*/ -#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ -#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ -#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ -#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ -#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ -#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ -#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ -#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ -#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ -#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ - -/* PHY identification - */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */ - -/* send command to phy using mii, wait for result */ -static uint -mii_send(uint mii_cmd) -{ - uint mii_reply; - volatile fec_t *ep; - int cnt; - - ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec); - - ep->fec_mii_data = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - cnt = 0; - while (!(ep->fec_ievent & FEC_ENET_MII)) { - if (++cnt > 1000) { - printf("mii_send STUCK!\n"); - break; - } - } - mii_reply = ep->fec_mii_data; /* result from phy */ - ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ -#if 0 - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply); -#endif - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ - -#if defined(CFG_DISCOVER_PHY) -static int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - uint phyno; - int pass; - uint phytype; - int phyaddr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type ", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= mii_send(mk_mii_read(phyno, - PHY_PHYIDR2)); - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ",phyno,pass); - switch (phytype & 0xfffffff0) { - case PHY_ID_LXT970: - printf("LXT970\n"); - break; - case PHY_ID_LXT971: - printf("LXT971\n"); - break; - case PHY_ID_82555: - printf("82555\n"); - break; - case PHY_ID_QS6612: - printf("QS6612\n"); - break; - case PHY_ID_AMD79C784: - printf("AMD79C784\n"); - break; - case PHY_ID_LSI80225B: - printf("LSI L80225/B\n"); - break; - case PHY_ID_DM9161: - printf("Davicom DM9161\n"); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) { - printf("No PHY device found.\n"); - } - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII) - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_init (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile fec_t *fecp = &(immr->im_cpm.cp_fec); - int i, j; - - for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) { - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) { - printf ("FEC_RESET_DELAY timeout\n"); - return; - } - - /* We use strictly polling mode only - */ - fecp->fec_imask = 0; - - /* Clear any pending interrupt - */ - fecp->fec_ievent = 0xffc0; - - /* Setup the pin configuration of the FEC(s) - */ - fec_pin_init(ether_fcc_info[i].ether_index); - - /* Now enable the transmit and receive processing - */ - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; - } -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int fec8xx_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; -#ifdef MII_DEBUG - printf ("0x%04x\n", *value); -#endif - return 0; -} - -int fec8xx_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - short rdreg; /* register working value */ -#ifdef MII_DEBUG - printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf ("0x%04x\n", value); -#endif - return 0; -} -#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/ - -#endif /* CFG_CMD_NET, FEC_ENET */ diff --git a/cpu/mpc8xx/fec.h b/cpu/mpc8xx/fec.h deleted file mode 100644 index a49417c..0000000 --- a/cpu/mpc8xx/fec.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _FEC_H_ -#define _FEC_H_ - - -#endif /* _FEC_H_ */ diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c deleted file mode 100644 index 682db53..0000000 --- a/cpu/mpc8xx/i2c.c +++ /dev/null @@ -1,744 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Back ported to the 8xx platform (from the 8260 platform) by - * Murray.Jensen@cmst.csiro.au, 27-Jan-01. - */ - -#include - -#ifdef CONFIG_HARD_I2C - -#include -#include -#ifdef CONFIG_LWMON -#include -#endif - -/* define to enable debug messages */ -#undef DEBUG_I2C - -/*----------------------------------------------------------------------- - * Set default values - */ -#ifndef CFG_I2C_SPEED -#define CFG_I2C_SPEED 50000 -#endif - -#ifndef CFG_I2C_SLAVE -#define CFG_I2C_SLAVE 0xFE -#endif -/*----------------------------------------------------------------------- - */ - -/* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */ -#define TOUT_LOOP 1000000 - -#define NUM_RX_BDS 4 -#define NUM_TX_BDS 4 -#define MAX_TX_SPACE 256 -#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ - -typedef struct I2C_BD -{ - unsigned short status; - unsigned short length; - unsigned char *addr; -} I2C_BD; -#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */ - -#define BD_I2C_TX_CL 0x0001 /* collision error */ -#define BD_I2C_TX_UN 0x0002 /* underflow error */ -#define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */ -#define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL) - -#define BD_I2C_RX_ERR BD_SC_OV - -typedef void (*i2c_ecb_t)(int, int); /* error callback function */ - -/* This structure keeps track of the bd and buffer space usage. */ -typedef struct i2c_state { - int rx_idx; /* index to next free Rx BD */ - int tx_idx; /* index to next free Tx BD */ - void *rxbd; /* pointer to next free Rx BD */ - void *txbd; /* pointer to next free Tx BD */ - int tx_space; /* number of Tx bytes left */ - unsigned char *tx_buf; /* pointer to free Tx area */ - i2c_ecb_t err_cb; /* error callback function */ -} i2c_state_t; - - -/* flags for i2c_send() and i2c_receive() */ -#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */ -#define I2CF_START_COND 0x02 /* tx: generate start condition */ -#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */ - -/* return codes */ -#define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */ -#define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */ -#define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */ -#define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */ - -/* error callback flags */ -#define I2CECB_RX_ERR 0x10 /* this is a receive error */ -#define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */ -#define I2CECB_RX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TX_ERR 0x20 /* this is a transmit error */ -#define I2CECB_TX_CL 0x01 /* transmit collision error */ -#define I2CECB_TX_UN 0x02 /* transmit underflow error */ -#define I2CECB_TX_NAK 0x04 /* transmit no ack error */ -#define I2CECB_TX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */ - -#ifdef DEBUG_I2C -#define PRINTD(x) printf x -#else -#define PRINTD(x) -#endif - -/* - * Returns the best value of I2BRG to meet desired clock speed of I2C with - * input parameters (clock speed, filter, and predivider value). - * It returns computer speed value and the difference between it and desired - * speed. - */ -static inline int -i2c_roundrate(int hz, int speed, int filter, int modval, - int *brgval, int *totspeed) -{ - int moddiv = 1 << (5-(modval & 3)), brgdiv, div; - - PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n", - hz, speed, filter, modval)); - - div = moddiv * speed; - brgdiv = (hz + div - 1) / div; - - PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv)); - - *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter); - - if ((*brgval < 0) || (*brgval > 255)) { - PRINTD(("\t\trejected brgval=%d\n", *brgval)); - return -1; - } - - brgdiv = 2 * (*brgval + 3 + (2 * filter)); - div = moddiv * brgdiv ; - *totspeed = hz / div; - - PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed)); - - return 0; -} - -/* - * Sets the I2C clock predivider and divider to meet required clock speed. - */ -static int -i2c_setrate (int hz, int speed) -{ - immap_t *immap = (immap_t *) CFG_IMMR; - volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c; - int brgval, - modval, /* 0-3 */ - bestspeed_diff = speed, - bestspeed_brgval = 0, - bestspeed_modval = 0, - bestspeed_filter = 0, - totspeed, - filter = 0; /* Use this fixed value */ - - for (modval = 0; modval < 4; modval++) { - if (i2c_roundrate(hz,speed,filter,modval,&brgval,&totspeed) == 0) { - int diff = speed - totspeed; - - if ((diff >= 0) && (diff < bestspeed_diff)) { - bestspeed_diff = diff; - bestspeed_modval = modval; - bestspeed_brgval = brgval; - bestspeed_filter = filter; - } - } - } - - PRINTD (("[I2C] Best is:\n")); - PRINTD (("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", - hz, - speed, - bestspeed_filter, - bestspeed_modval, - bestspeed_brgval, - bestspeed_diff)); - - i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3); - i2c->i2c_i2brg = bestspeed_brgval & 0xff; - - PRINTD (("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, - i2c->i2c_i2brg)); - - return 1; -} - -void -i2c_init(int speed, int slaveaddr) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immap = (immap_t *)CFG_IMMR ; - volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; - volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; - volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - ulong rbase, tbase; - volatile I2C_BD *rxbd, *txbd; - uint dpaddr; - -#ifdef CFG_I2C_INIT_BOARD - /* call board specific i2c bus reset routine before accessing the */ - /* environment, which might be in a chip on that bus. For details */ - /* about this problem see doc/I2C_Edge_Conditions. */ - i2c_init_board(); -#endif - -#ifdef CFG_I2C_UCODE_PATCH - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#else - /* Disable relocation */ - iip->iic_rpbase = 0; -#endif - -#ifdef CFG_ALLOC_DPRAM - dpaddr = iip->iic_rbase; - if (dpaddr == 0) { - /* need to allocate dual port ram */ - dpaddr = dpram_alloc_align( - (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) + - MAX_TX_SPACE, 8); - } -#else - dpaddr = CPM_I2C_BASE; -#endif - - /* - * initialise data in dual port ram: - * - * dpaddr->rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes) - * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes) - * tx buffer (MAX_TX_SPACE bytes) - */ - - rbase = dpaddr; - tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD); - - /* Initialize Port B I2C pins. */ - cp->cp_pbpar |= 0x00000030; - cp->cp_pbdir |= 0x00000030; - cp->cp_pbodr |= 0x00000030; - - /* Disable interrupts */ - i2c->i2c_i2mod = 0x00; - i2c->i2c_i2cmr = 0x00; - i2c->i2c_i2cer = 0xff; - i2c->i2c_i2add = slaveaddr; - - /* - * Set the I2C BRG Clock division factor from desired i2c rate - * and current CPU rate (we assume sccr dfbgr field is 0; - * divide BRGCLK by 1) - */ - PRINTD(("[I2C] Setting rate...\n")); - i2c_setrate (gd->cpu_clk, CFG_I2C_SPEED) ; - - /* Set I2C controller in master mode */ - i2c->i2c_i2com = 0x01; - - /* Set SDMA bus arbitration level to 5 (SDCR) */ - immap->im_siu_conf.sc_sdcr = 0x0001 ; - - /* Initialize Tx/Rx parameters */ - iip->iic_rbase = rbase; - iip->iic_tbase = tbase; - rxbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_rbase]); - txbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_tbase]); - - PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase)); - PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase)); - PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); - - /* Set big endian byte order */ - iip->iic_tfcr = 0x10; - iip->iic_rfcr = 0x10; - - /* Set maximum receive size. */ - iip->iic_mrblr = I2C_RXTX_LEN; - -#ifdef CFG_I2C_UCODE_PATCH - /* - * Initialize required parameters if using microcode patch. - */ - iip->iic_rbptr = iip->iic_rbase; - iip->iic_tbptr = iip->iic_tbase; - iip->iic_rstate = 0; - iip->iic_tstate = 0; -#else - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); -#endif - - /* Clear events and interrupts */ - i2c->i2c_i2cer = 0xff; - i2c->i2c_i2cmr = 0x00; -} - -static void -i2c_newio(i2c_state_t *state) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR ; - volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; - volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - - PRINTD(("[I2C] i2c_newio\n")); - -#ifdef CFG_I2C_UCODE_PATCH - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - state->rx_idx = 0; - state->tx_idx = 0; - state->rxbd = (void*)&cp->cp_dpmem[iip->iic_rbase]; - state->txbd = (void*)&cp->cp_dpmem[iip->iic_tbase]; - state->tx_space = MAX_TX_SPACE; - state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD); - state->err_cb = NULL; - - PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd)); - PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf)); - - /* clear the buffer memory */ - memset((char *)state->tx_buf, 0, MAX_TX_SPACE); -} - -static int -i2c_send(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, - unsigned short size, - unsigned char *dataout) -{ - volatile I2C_BD *txbd; - int i,j; - - PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n", - address, secondary_address, flags, size)); - - /* trying to send message larger than BD */ - if (size > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; - - /* no more free bds */ - if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size)) - return I2CERR_NO_BUFFERS; - - txbd = (I2C_BD *)state->txbd; - txbd->addr = state->tx_buf; - - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); - - if (flags & I2CF_START_COND) { - PRINTD(("[I2C] Formatting addresses...\n")); - if (flags & I2CF_ENABLE_SECONDARY) { - txbd->length = size + 2; /* Length of msg + dest addr */ - txbd->addr[0] = address << 1; - txbd->addr[1] = secondary_address; - i = 2; - } else { - txbd->length = size + 1; /* Length of msg + dest addr */ - txbd->addr[0] = address << 1; /* Write dest addr to BD */ - i = 1; - } - } else { - txbd->length = size; /* Length of message */ - i = 0; - } - - /* set up txbd */ - txbd->status = BD_SC_READY; - if (flags & I2CF_START_COND) - txbd->status |= BD_I2C_TX_START; - if (flags & I2CF_STOP_COND) - txbd->status |= BD_SC_LAST | BD_SC_WRAP; - - /* Copy data to send into buffer */ - PRINTD(("[I2C] copy data...\n")); - for(j = 0; j < size; i++, j++) - txbd->addr[i] = dataout[j]; - - PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, - txbd->status, - txbd->addr[0], - txbd->addr[1])); - - /* advance state */ - state->tx_buf += txbd->length; - state->tx_space -= txbd->length; - state->tx_idx++; - state->txbd = (void*)(txbd + 1); - - return 0; -} - -static int -i2c_receive(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, - unsigned short size_to_expect, - unsigned char *datain) -{ - volatile I2C_BD *rxbd, *txbd; - - PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags)); - - /* Expected to receive too much */ - if (size_to_expect > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; - - /* no more free bds */ - if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS - || state->tx_space < 2) - return I2CERR_NO_BUFFERS; - - rxbd = (I2C_BD *)state->rxbd; - txbd = (I2C_BD *)state->txbd; - - PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); - - txbd->addr = state->tx_buf; - - /* set up TXBD for destination address */ - if (flags & I2CF_ENABLE_SECONDARY) { - txbd->length = 2; - txbd->addr[0] = address << 1; /* Write data */ - txbd->addr[1] = secondary_address; /* Internal address */ - txbd->status = BD_SC_READY; - } else { - txbd->length = 1 + size_to_expect; - txbd->addr[0] = (address << 1) | 0x01; - txbd->status = BD_SC_READY; - memset(&txbd->addr[1], 0, txbd->length); - } - - /* set up rxbd for reception */ - rxbd->status = BD_SC_EMPTY; - rxbd->length = size_to_expect; - rxbd->addr = datain; - - txbd->status |= BD_I2C_TX_START; - if (flags & I2CF_STOP_COND) { - txbd->status |= BD_SC_LAST | BD_SC_WRAP; - rxbd->status |= BD_SC_WRAP; - } - - PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, - txbd->status, - txbd->addr[0], - txbd->addr[1])); - PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - rxbd->length, - rxbd->status, - rxbd->addr[0], - rxbd->addr[1])); - - /* advance state */ - state->tx_buf += txbd->length; - state->tx_space -= txbd->length; - state->tx_idx++; - state->txbd = (void*)(txbd + 1); - state->rx_idx++; - state->rxbd = (void*)(rxbd + 1); - - return 0; -} - - -static int i2c_doio(i2c_state_t *state) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR ; - volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; - volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; - volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - volatile I2C_BD *txbd, *rxbd; - volatile int j = 0; - - PRINTD(("[I2C] i2c_doio\n")); - -#ifdef CFG_I2C_UCODE_PATCH - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - - if (state->tx_idx <= 0 && state->rx_idx <= 0) { - PRINTD(("[I2C] No I/O is queued\n")); - return I2CERR_QUEUE_EMPTY; - } - - iip->iic_rbptr = iip->iic_rbase; - iip->iic_tbptr = iip->iic_tbase; - - /* Enable I2C */ - PRINTD(("[I2C] Enabling I2C...\n")); - i2c->i2c_i2mod |= 0x01; - - /* Begin transmission */ - i2c->i2c_i2com |= 0x80; - - /* Loop until transmit & receive completed */ - - if (state->tx_idx > 0) { - txbd = ((I2C_BD*)state->txbd) - 1; - PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd)); - while((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) { - if (ctrlc()) { - return (-1); - } - __asm__ __volatile__ ("eieio"); - } - } - - if ((state->rx_idx > 0) && (j < TOUT_LOOP)) { - rxbd = ((I2C_BD*)state->rxbd) - 1; - PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd)); - while((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) { - if (ctrlc()) { - return (-1); - } - __asm__ __volatile__ ("eieio"); - } - } - - /* Turn off I2C */ - i2c->i2c_i2mod &= ~0x01; - - if (state->err_cb != NULL) { - int n, i, b; - - /* - * if we have an error callback function, look at the - * error bits in the bd status and pass them back - */ - - if ((n = state->tx_idx) > 0) { - for (i = 0; i < n; i++) { - txbd = ((I2C_BD*)state->txbd) - (n - i); - if ((b = txbd->status & BD_I2C_TX_ERR) != 0) - (*state->err_cb)(I2CECB_TX_ERR|b, i); - } - } - - if ((n = state->rx_idx) > 0) { - for (i = 0; i < n; i++) { - rxbd = ((I2C_BD*)state->rxbd) - (n - i); - if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) - (*state->err_cb)(I2CECB_RX_ERR|b, i); - } - } - - if (j >= TOUT_LOOP) - (*state->err_cb)(I2CECB_TIMEOUT, 0); - } - - return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0; -} - -static int had_tx_nak; - -static void -i2c_test_callback(int flags, int xnum) -{ - if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK)) - had_tx_nak = 1; -} - -int i2c_probe(uchar chip) -{ - i2c_state_t state; - int rc; - uchar buf[1]; - - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); - - i2c_newio(&state); - - state.err_cb = i2c_test_callback; - had_tx_nak = 0; - - rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf); - - if (rc != 0) - return (rc); - - rc = i2c_doio(&state); - - if ((rc != 0) && (rc != I2CERR_TIMEOUT)) - return (rc); - - return (had_tx_nak); -} - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - DECLARE_GLOBAL_DATA_PTR; - - i2c_state_t state; - uchar xaddr[4]; - int rc; - -#ifdef CONFIG_LWMON - WATCHDOG_RESET(); -#endif - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones like - * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the - * extra bits end up in the "chip address" bit slots. This makes - * a 24WC08 (1Kbyte) chip look like four 256 byte chips. - * - * Note that we consider the length of the address field to still - * be one byte because the extra address bits are hidden in the - * chip address. - */ - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); -#endif - - i2c_newio(&state); - - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); - if (rc != 0) { - if (gd->have_console) - printf("i2c_read: i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer); - if (rc != 0) { - if (gd->have_console) - printf("i2c_read: i2c_receive failed (%d)\n", rc); - return 1; - } - - rc = i2c_doio(&state); - if (rc != 0) { - if (gd->have_console) - printf("i2c_read: i2c_doio failed (%d)\n", rc); - return 1; - } - return 0; -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - DECLARE_GLOBAL_DATA_PTR; - - i2c_state_t state; - uchar xaddr[4]; - int rc; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones like - * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the - * extra bits end up in the "chip address" bit slots. This makes - * a 24WC08 (1Kbyte) chip look like four 256 byte chips. - * - * Note that we consider the length of the address field to still - * be one byte because the extra address bits are hidden in the - * chip address. - */ - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); -#endif - - i2c_newio(&state); - - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); - if (rc != 0) { - if (gd->have_console) - printf("i2c_write: first i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer); - if (rc != 0) { - if (gd->have_console) - printf("i2c_write: second i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_doio(&state); - if (rc != 0) { - if (gd->have_console) - printf("i2c_write: i2c_doio failed (%d)\n", rc); - return 1; - } - return 0; -} - -uchar -i2c_reg_read(uchar i2c_addr, uchar reg) -{ - uchar buf; - - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); - - i2c_read(i2c_addr, reg, 1, &buf, 1); - - return (buf); -} - -void -i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); - - i2c_write(i2c_addr, reg, 1, &val, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8xx/interrupts.c b/cpu/mpc8xx/interrupts.c deleted file mode 100644 index 20e7012..0000000 --- a/cpu/mpc8xx/interrupts.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -/************************************************************************/ - -/* - * CPM interrupt vector functions. - */ -struct interrupt_action { - interrupt_handler_t *handler; - void *arg; -}; - -static struct interrupt_action cpm_vecs[CPMVEC_NR]; -static struct interrupt_action irq_vecs[NR_IRQS]; - -static void cpm_interrupt_init (void); -static void cpm_interrupt (void *regs); - -/************************************************************************/ - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - *decrementer_count = get_tbclk () / CFG_HZ; - - /* disable all interrupts */ - immr->im_siu_conf.sc_simask = 0; - - /* Configure CPM interrupts */ - cpm_interrupt_init (); - - return (0); -} - -/************************************************************************/ - -/* - * Handle external interrupts - */ -void external_interrupt (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - int irq; - ulong simask, newmask; - ulong vec, v_bit; - - /* - * read the SIVEC register and shift the bits down - * to get the irq number - */ - vec = immr->im_siu_conf.sc_sivec; - irq = vec >> 26; - v_bit = 0x80000000UL >> irq; - - /* - * Read Interrupt Mask Register and Mask Interrupts - */ - simask = immr->im_siu_conf.sc_simask; - newmask = simask & (~(0xFFFF0000 >> irq)); - immr->im_siu_conf.sc_simask = newmask; - - if (!(irq & 0x1)) { /* External Interrupt ? */ - ulong siel; - - /* - * Read Interrupt Edge/Level Register - */ - siel = immr->im_siu_conf.sc_siel; - - if (siel & v_bit) { /* edge triggered interrupt ? */ - /* - * Rewrite SIPEND Register to clear interrupt - */ - immr->im_siu_conf.sc_sipend = v_bit; - } - } - - if (irq_vecs[irq].handler != NULL) { - irq_vecs[irq].handler (irq_vecs[irq].arg); - } else { - printf ("\nBogus External Interrupt IRQ %d Vector %ld\n", - irq, vec); - /* turn off the bogus interrupt to avoid it from now */ - simask &= ~v_bit; - } - /* - * Re-Enable old Interrupt Mask - */ - immr->im_siu_conf.sc_simask = simask; -} - -/************************************************************************/ - -/* - * CPM interrupt handler - */ -static void cpm_interrupt (void *regs) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - uint vec; - - /* - * Get the vector by setting the ACK bit - * and then reading the register. - */ - immr->im_cpic.cpic_civr = 1; - vec = immr->im_cpic.cpic_civr; - vec >>= 11; - - if (cpm_vecs[vec].handler != NULL) { - (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg); - } else { - immr->im_cpic.cpic_cimr &= ~(1 << vec); - printf ("Masking bogus CPM interrupt vector 0x%x\n", vec); - } - /* - * After servicing the interrupt, - * we have to remove the status indicator. - */ - immr->im_cpic.cpic_cisr |= (1 << vec); -} - -/* - * The CPM can generate the error interrupt when there is a race - * condition between generating and masking interrupts. All we have - * to do is ACK it and return. This is a no-op function so we don't - * need any special tests in the interrupt handler. - */ -static void cpm_error_interrupt (void *dummy) -{ -} - -/************************************************************************/ -/* - * Install and free an interrupt handler - */ -void irq_install_handler (int vec, interrupt_handler_t * handler, - void *arg) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - if ((vec & CPMVEC_OFFSET) != 0) { - /* CPM interrupt */ - vec &= 0xffff; - if (cpm_vecs[vec].handler != NULL) { - printf ("CPM interrupt 0x%x replacing 0x%x\n", - (uint) handler, - (uint) cpm_vecs[vec].handler); - } - cpm_vecs[vec].handler = handler; - cpm_vecs[vec].arg = arg; - immr->im_cpic.cpic_cimr |= (1 << vec); -#if 0 - printf ("Install CPM interrupt for vector %d ==> %p\n", - vec, handler); -#endif - } else { - /* SIU interrupt */ - if (irq_vecs[vec].handler != NULL) { - printf ("SIU interrupt %d 0x%x replacing 0x%x\n", - vec, - (uint) handler, - (uint) cpm_vecs[vec].handler); - } - irq_vecs[vec].handler = handler; - irq_vecs[vec].arg = arg; - immr->im_siu_conf.sc_simask |= 1 << (31 - vec); -#if 0 - printf ("Install SIU interrupt for vector %d ==> %p\n", - vec, handler); -#endif - } -} - -void irq_free_handler (int vec) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - if ((vec & CPMVEC_OFFSET) != 0) { - /* CPM interrupt */ - vec &= 0xffff; -#if 0 - printf ("Free CPM interrupt for vector %d ==> %p\n", - vec, cpm_vecs[vec].handler); -#endif - immr->im_cpic.cpic_cimr &= ~(1 << vec); - cpm_vecs[vec].handler = NULL; - cpm_vecs[vec].arg = NULL; - } else { - /* SIU interrupt */ -#if 0 - printf ("Free CPM interrupt for vector %d ==> %p\n", - vec, cpm_vecs[vec].handler); -#endif - immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec)); - irq_vecs[vec].handler = NULL; - irq_vecs[vec].arg = NULL; - } -} - -/************************************************************************/ - -static void cpm_interrupt_init (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - /* - * Initialize the CPM interrupt controller. - */ - - immr->im_cpic.cpic_cicr = - (CICR_SCD_SCC4 | - CICR_SCC_SCC3 | - CICR_SCB_SCC2 | - CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK; - - immr->im_cpic.cpic_cimr = 0; - - /* - * Install the error handler. - */ - irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL); - - immr->im_cpic.cpic_cicr |= CICR_IEN; - - /* - * Install the cpm interrupt handler - */ - irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL); -} - -/************************************************************************/ - -/* - * timer_interrupt - gets called when the decrementer overflows, - * with interrupts disabled. - * Trivial implementation - no need to be really accurate. - */ -void timer_interrupt_cpu (struct pt_regs *regs) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - -#if 0 - printf ("*** Timer Interrupt *** "); -#endif - /* Reset Timer Expired and Timers Interrupt Status */ - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - __asm__ ("nop"); - /* - Clear TEXPS (and TMIST on older chips). SPLSS (on older - chips) is cleared too. - - Bitwise OR is a read-modify-write operation so ALL bits - which are cleared by writing `1' would be cleared by - operations like - - immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS; - - The same can be achieved by simple writing of the PLPRCR - to itself. If a bit value should be preserved, read the - register, ZERO the bit and write, not OR, the result back. - */ - immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr; -} - -/************************************************************************/ diff --git a/cpu/mpc8xx/kgdb.S b/cpu/mpc8xx/kgdb.S deleted file mode 100644 index 11c3c69..0000000 --- a/cpu/mpc8xx/kgdb.S +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2000 Murray Jensen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - - /* - * cache flushing routines for kgdb - */ - - .globl kgdb_flush_cache_all -kgdb_flush_cache_all: - lis r3, IDC_INVALL@h - mtspr DC_CST, r3 - sync - lis r3, IDC_INVALL@h - mtspr IC_CST, r3 - SYNC - blr - - .globl kgdb_flush_cache_range -kgdb_flush_cache_range: - li r5,CFG_CACHELINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,CFG_CACHELINE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CFG_CACHELINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CFG_CACHELINE_SIZE - bdnz 2b - SYNC - blr - -#endif /* CFG_CMD_KGDB */ diff --git a/cpu/mpc8xx/lcd.c b/cpu/mpc8xx/lcd.c deleted file mode 100644 index 3c64a9b..0000000 --- a/cpu/mpc8xx/lcd.c +++ /dev/null @@ -1,621 +0,0 @@ -/* - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering -- wd@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -/* #define DEBUG */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_POST) -#include -#endif -#include - -#ifdef CONFIG_LCD - -/************************************************************************/ -/* ** CONFIG STUFF -- should be moved to board config file */ -/************************************************************************/ -#ifndef CONFIG_LCD_INFO -#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */ -#endif - -#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10) -#undef CONFIG_LCD_LOGO -#undef CONFIG_LCD_INFO -#endif - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_KYOCERA_KCS057QV1AJ -/* - * Kyocera KCS057QV1AJ-G23. Passive, color, single scan. - */ -#define LCD_BPP LCD_COLOR4 - -vidinfo_t panel_info = { - 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, - LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_KYOCERA_KCS057QV1AJ */ -/*----------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_HITACHI_SP19X001_Z1A -/* - * Hitachi SP19X001-. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 154, 116, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, - LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_HITACHI_SP19X001_Z1A */ -/*----------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_NEC_NL6448AC33 -/* - * NEC NL6448AC33-18. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448AC33 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_NEC_NL6448BC20 -/* - * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448BC20 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_NEC_NL6448BC33_54 -/* - * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 212, 158, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448BC33_54 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ104V7DS01 -/* - * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW, - 3, 0, 0, 1, 1, 25, 1, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ104V7DS01 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_16x9 -/* - * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am - * not sure what it is....... - */ -vidinfo_t panel_info = { - 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, - 3, 0, 0, 1, 1, 15, 4, 0, 3 -}; -#endif /* CONFIG_SHARP_16x9 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ057Q3DC02 -/* - * Sharp LQ057Q3DC02 display. Active, color, single scan. - */ -#undef LCD_DF -#define LCD_DF 12 - -vidinfo_t panel_info = { - 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, - 3, 0, 0, 1, 1, 15, 4, 0, 3 - /* wbl, vpw, lcdac, wbf */ -}; -#define CONFIG_LCD_INFO_BELOW_LOGO -#endif /* CONFIG_SHARP_LQ057Q3DC02 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ64D341 -/* - * Sharp LQ64D341 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, - 3, 0, 0, 1, 1, 128, 16, 0, 32 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ64D341 */ - -#ifdef CONFIG_SHARP_LQ065T9DR51U -/* - * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan. - */ -vidinfo_t panel_info = { - 400, 240, 143, 79, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, - 3, 0, 0, 1, 1, 248, 4, 0, 35 - /* wbl, vpw, lcdac, wbf */ -}; -#define CONFIG_LCD_INFO_BELOW_LOGO -#endif /* CONFIG_SHARP_LQ065T9DR51U */ - -#ifdef CONFIG_SHARP_LQ084V1DG21 -/* - * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 171, 129, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW, - 3, 0, 0, 1, 1, 160, 3, 0, 48 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ084V1DG21 */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_HLD1045 -/* - * HLD1045 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, - 3, 0, 0, 1, 1, 160, 3, 0, 48 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_HLD1045 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_PRIMEVIEW_V16C6448AC -/* - * Prime View V16C6448AC - */ -vidinfo_t panel_info = { - 640, 480, 130, 98, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 35 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_PRIMEVIEW_V16C6448AC */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_OPTREX_BW -/* - * Optrex CBL50840-2 NF-FW 99 22 M5 - * or - * Hitachi LMG6912RPFC-00T - * or - * Hitachi SP14Q002 - * - * 320x240. Black & white. - */ -#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */ - /* 1 - 4 grey levels, 2 bpp */ - /* 2 - 16 grey levels, 4 bpp */ -vidinfo_t panel_info = { - 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW, - OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4 -}; -#endif /* CONFIG_OPTREX_BW */ - -/*-----------------------------------------------------------------*/ -#ifdef CONFIG_EDT32F10 -/* - * Emerging Display Technologies 320x240. Passive, monochrome, single scan. - */ -#define LCD_BPP LCD_MONOCHROME -#define LCD_DF 10 - -vidinfo_t panel_info = { - 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW, - LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0 -}; -#endif -/*----------------------------------------------------------------------*/ - - -int lcd_line_length; - -int lcd_color_fg; -int lcd_color_bg; - -/* - * Frame buffer memory information - */ -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - -/************************************************************************/ - -void lcd_ctrl_init (void *lcdbase); -void lcd_enable (void); -#if LCD_BPP == LCD_COLOR8 -void lcd_setcolreg (ushort regno, - ushort red, ushort green, ushort blue); -#endif -#if LCD_BPP == LCD_MONOCHROME -void lcd_initcolregs (void); -#endif - -#if defined(CONFIG_RBC823) -void lcd_disable (void); -#endif - -/************************************************************************/ - -/************************************************************************/ -/* ----------------- chipset specific functions ----------------------- */ -/************************************************************************/ - -/* - * Calculate fb size for VIDEOLFB_ATAG. - */ -ulong calc_fbsize (void) -{ - ulong size; - int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; - - size = line_length * panel_info.vl_row; - - return size; -} - -void lcd_ctrl_init (void *lcdbase) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - - uint lccrtmp; - uint lchcr_hpc_tmp; - - /* Initialize the LCD control register according to the LCD - * parameters defined. We do everything here but enable - * the controller. - */ - -#ifdef CONFIG_RPXLITE - /* This is special for RPXlite_DW Software Development Platform **[Sam]** */ - panel_info.vl_dp = CFG_LOW; -#endif - - lccrtmp = LCDBIT (LCCR_BNUM_BIT, - (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128)); - - lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) | - LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) | - LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) | - LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) | - LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) | - LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) | - LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) | - LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) | - LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) | - LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft); - -#if 0 - lccrtmp |= ((SIU_LEVEL5 / 2) << 12); - lccrtmp |= LCCR_EIEN; -#endif - - lcdp->lcd_lccr = lccrtmp; - lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */ - - /* Initialize LCD controller bus priorities. - */ -#ifdef CONFIG_RBC823 - immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */ -#else - immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */ - - /* set SHFT/CLOCK division factor 4 - * This needs to be set based upon display type and processor - * speed. The TFT displays run about 20 to 30 MHz. - * I was running 64 MHz processor speed. - * The value for this divider must be chosen so the result is - * an integer of the processor speed (i.e., divide by 3 with - * 64 MHz would be bad). - */ - immr->im_clkrst.car_sccr &= ~0x1F; - immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */ - -#endif /* CONFIG_RBC823 */ - -#if defined(CONFIG_RBC823) - /* Enable LCD on port D. - */ - immr->im_ioport.iop_pddat &= 0x0300; - immr->im_ioport.iop_pdpar |= 0x1CFF; - immr->im_ioport.iop_pddir |= 0x1CFF; - - /* Configure LCD_ON, VEE_ON, CCFL_ON on port B. - */ - immr->im_cpm.cp_pbdat &= ~0x00005001; - immr->im_cpm.cp_pbpar &= ~0x00005001; - immr->im_cpm.cp_pbdir |= 0x00005001; -#elif !defined(CONFIG_EDT32F10) - /* Enable LCD on port D. - */ - immr->im_ioport.iop_pdpar |= 0x1FFF; - immr->im_ioport.iop_pddir |= 0x1FFF; - - /* Enable LCD_A/B/C on port B. - */ - immr->im_cpm.cp_pbpar |= 0x00005001; - immr->im_cpm.cp_pbdir |= 0x00005001; -#else - /* Enable LCD on port D. - */ - immr->im_ioport.iop_pdpar |= 0x1DFF; - immr->im_ioport.iop_pdpar &= ~0x0200; - immr->im_ioport.iop_pddir |= 0x1FFF; - immr->im_ioport.iop_pddat |= 0x0200; -#endif - - /* Load the physical address of the linear frame buffer - * into the LCD controller. - * BIG NOTE: This has to be modified to load A and B depending - * upon the split mode of the LCD. - */ - lcdp->lcd_lcfaa = (ulong)lcd_base; - lcdp->lcd_lcfba = (ulong)lcd_base; - - /* MORE HACKS...This must be updated according to 823 manual - * for different panels. - * Udi Finkelstein - done - see below: - * Note: You better not try unsupported combinations such as - * 4-bit wide passive dual scan LCD at 4/8 Bit color. - */ - lchcr_hpc_tmp = - (panel_info.vl_col * - (panel_info.vl_tft ? 8 : - (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */ - /* use << to mult by: single scan = 1, dual scan = 2 */ - panel_info.vl_splt) * - (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */ - - lcdp->lcd_lchcr = LCHCR_BO | - LCDBIT (LCHCR_AT_BIT, 4) | - LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) | - panel_info.vl_wbl; - - lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) | - LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) | - LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) | - panel_info.vl_wbf; - -} - -/*----------------------------------------------------------------------*/ - -#ifdef NOT_USED_SO_FAR -static void -lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cp = &(immr->im_cpm); - unsigned short colreg, *cmap_ptr; - - cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; - - colreg = *cmap_ptr; -#ifdef CFG_INVERT_COLORS - colreg ^= 0x0FFF; -#endif - - *red = (colreg >> 8) & 0x0F; - *green = (colreg >> 4) & 0x0F; - *blue = colreg & 0x0F; -} -#endif /* NOT_USED_SO_FAR */ - -/*----------------------------------------------------------------------*/ - -#if LCD_BPP == LCD_COLOR8 -void -lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cp = &(immr->im_cpm); - unsigned short colreg, *cmap_ptr; - - cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; - - colreg = ((red & 0x0F) << 8) | - ((green & 0x0F) << 4) | - (blue & 0x0F) ; -#ifdef CFG_INVERT_COLORS - colreg ^= 0x0FFF; -#endif - *cmap_ptr = colreg; - - debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n", - regno, &(cp->lcd_cmap[regno * 2]), - red, green, blue, - cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]); -} -#endif /* LCD_COLOR8 */ - -/*----------------------------------------------------------------------*/ - -#if LCD_BPP == LCD_MONOCHROME -static -void lcd_initcolregs (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cp = &(immr->im_cpm); - ushort regno; - - for (regno = 0; regno < 16; regno++) { - cp->lcd_cmap[regno * 2] = 0; - cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f; - } -} -#endif - -/*----------------------------------------------------------------------*/ - -void lcd_enable (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - - /* Enable the LCD panel */ -#ifndef CONFIG_RBC823 - immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ -#endif - lcdp->lcd_lccr |= LCCR_PON; - -#ifdef CONFIG_V37 - /* Turn on display backlight */ - immr->im_cpm.cp_pbpar |= 0x00008000; - immr->im_cpm.cp_pbdir |= 0x00008000; -#elif defined(CONFIG_RBC823) - /* Turn on display backlight */ - immr->im_cpm.cp_pbdat |= 0x00004000; -#endif - -#if defined(CONFIG_LWMON) - { uchar c = pic_read (0x60); -#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CFG_POST_SYSMON) - /* Enable LCD later in sysmon test, only if temperature is OK */ -#else - c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */ -#endif - pic_write (0x60, c); - } -#endif /* CONFIG_LWMON */ - -#if defined(CONFIG_R360MPI) - { - extern void r360_i2c_lcd_write (uchar data0, uchar data1); - unsigned long bgi, ctr; - char *p; - - if ((p = getenv("lcdbgi")) != NULL) { - bgi = simple_strtoul (p, 0, 10) & 0xFFF; - } else { - bgi = 0xFFF; - } - - if ((p = getenv("lcdctr")) != NULL) { - ctr = simple_strtoul (p, 0, 10) & 0xFFF; - } else { - ctr=0x7FF; - } - - r360_i2c_lcd_write(0x10, 0x01); - r360_i2c_lcd_write(0x20, 0x01); - r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF); - r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF); - } -#endif /* CONFIG_R360MPI */ -#ifdef CONFIG_RBC823 - udelay(200000); /* wait 200ms */ - /* Turn VEE_ON first */ - immr->im_cpm.cp_pbdat |= 0x00000001; - udelay(200000); /* wait 200ms */ - /* Now turn on LCD_ON */ - immr->im_cpm.cp_pbdat |= 0x00001000; -#endif -#ifdef CONFIG_RRVISION - debug ("PC4->Output(1): enable LVDS\n"); - debug ("PC5->Output(0): disable PAL clock\n"); - immr->im_ioport.iop_pddir |= 0x1000; - immr->im_ioport.iop_pcpar &= ~(0x0C00); - immr->im_ioport.iop_pcdir |= 0x0C00 ; - immr->im_ioport.iop_pcdat |= 0x0800 ; - immr->im_ioport.iop_pcdat &= ~(0x0400); - debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", - immr->im_ioport.iop_pdpar, - immr->im_ioport.iop_pddir, - immr->im_ioport.iop_pddat); - debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", - immr->im_ioport.iop_pcpar, - immr->im_ioport.iop_pcdir, - immr->im_ioport.iop_pcdat); -#endif -} - -/*----------------------------------------------------------------------*/ - -#if defined (CONFIG_RBC823) -void lcd_disable (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - -#if defined(CONFIG_LWMON) - { uchar c = pic_read (0x60); - c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */ - pic_write (0x60, c); - } -#elif defined(CONFIG_R360MPI) - { - extern void r360_i2c_lcd_write (uchar data0, uchar data1); - - r360_i2c_lcd_write(0x10, 0x00); - r360_i2c_lcd_write(0x20, 0x00); - r360_i2c_lcd_write(0x30, 0x00); - r360_i2c_lcd_write(0x40, 0x00); - } -#endif /* CONFIG_LWMON */ - /* Disable the LCD panel */ - lcdp->lcd_lccr &= ~LCCR_PON; -#ifdef CONFIG_RBC823 - /* Turn off display backlight, VEE and LCD_ON */ - immr->im_cpm.cp_pbdat &= ~0x00005001; -#else - immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */ -#endif /* CONFIG_RBC823 */ -} -#endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */ - - -/************************************************************************/ - -#endif /* CONFIG_LCD */ diff --git a/cpu/mpc8xx/plprcr_write.S b/cpu/mpc8xx/plprcr_write.S deleted file mode 100644 index e325671..0000000 --- a/cpu/mpc8xx/plprcr_write.S +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define CACHE_CMD_ENABLE 0x02000000 -#define CACHE_CMD_DISABLE 0x04000000 -#define CACHE_CMD_LOAD_LOCK 0x06000000 -#define CACHE_CMD_UNLOCK_LINE 0x08000000 -#define CACHE_CMD_UNLOCK_ALL 0x0A000000 -#define CACHE_CMD_INVALIDATE 0x0C000000 -#define SPEED_PLPRCR_WAIT_5CYC 150 -#define _CACHE_ALIGN_SIZE 16 - - - .text - .align 2 - .globl plprcr_write_866 - -/* - * void plprcr_write_866 (long plprcr) - * Write PLPRCR, including workaround for device errata SIU4 and SIU9. - */ - -plprcr_write_866: - mfspr r10, LR /* save the Link Register value */ - - /* turn instruction cache on (no MMU required for instructions) - */ - lis r4, CACHE_CMD_ENABLE@h - ori r4, r4, CACHE_CMD_ENABLE@l - mtspr IC_CST, r4 - isync - - /* clear IC_CST error bits - */ - mfspr r4, IC_CST - - bl plprcr_here - -plprcr_here: - mflr r5 - - /* calculate relocation offset - */ - lis r4, plprcr_here@h - ori r4, r4, plprcr_here@l - sub r5, r5, r4 - - /* calculate first address of this function - */ - lis r6, plprcr_write_866@h - ori r6, r6, plprcr_write_866@l - add r6, r6, r5 - - /* calculate end address of this function - */ - lis r7, plprcr_end@h - ori r7, r7, plprcr_end@l - add r7, r7, r5 - - /* load and lock code addresses - */ - mr r5, r6 - -plprcr_loop: - mtspr IC_ADR, r5 - addi r5, r5, _CACHE_ALIGN_SIZE /* increment by one line */ - - lis r4, CACHE_CMD_LOAD_LOCK@h - ori r4, r4, CACHE_CMD_LOAD_LOCK@l - mtspr IC_CST, r4 - isync - - cmpw r5, r7 - blt plprcr_loop - - /* IC_CST error bits not evaluated - */ - - /* switch PLPRCR - */ - mfspr r4, IMMR /* read IMMR */ - rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */ - - /* write sequence according to MPC866 Errata - */ - stw r3, PLPRCR(r4) - isync - - lis r3, SPEED_PLPRCR_WAIT_5CYC@h - ori r3, r3, SPEED_PLPRCR_WAIT_5CYC@l - -plprcr_wait: - cmpwi r3, 0 - beq plprcr_wait_end - nop - subi r3, r3, 1 - b plprcr_wait - -plprcr_wait_end: - - /* unlock instruction cache but leave it enabled - */ - lis r4, CACHE_CMD_UNLOCK_ALL@h - ori r4, r4, CACHE_CMD_UNLOCK_ALL@l - mtspr IC_CST, r4 - isync - - mtspr LR, r10 /* restore original Link Register value */ - blr - -plprcr_end: diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c deleted file mode 100644 index 6b9110f..0000000 --- a/cpu/mpc8xx/scc.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * File: scc.c - * Description: - * Basic ET HW initialization and packet RX/TX routines - * - * NOTE <<>>: - * Do not cache Rx/Tx buffers! - */ - -/* - * MPC823 <-> MC68160 Connections: - * - * Setup MPC823 to work with MC68160 Enhanced Ethernet - * Serial Tranceiver as follows: - * - * MPC823 Signal MC68160 Comments - * ------ ------ ------- -------- - * PA-12 ETHTX --------> TX Eth. Port Transmit Data - * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable - * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock - * PA-13 ETHRX <-------- RX Eth. Port Receive Data - * PC-8 E_RENA <-------- RENA Eth. Receive Enable - * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock - * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication - * - * FADS Board Signal MC68160 Comments - * ----------------- ------- -------- - * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable - * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable - * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex - * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back - * - */ - -#include -#include -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET) - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 10000 /* 10 ms to have a packet sent */ - -static char txbuf[DBUF_LENGTH]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * SCC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx; - -static int scc_send(struct eth_device* dev, volatile void *packet, int length); -static int scc_recv(struct eth_device* dev); -static int scc_init (struct eth_device* dev, bd_t * bd); -static void scc_halt(struct eth_device* dev); - -int scc_initialize(bd_t *bis) -{ - struct eth_device* dev; - - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - sprintf(dev->name, "SCC ETHERNET"); - dev->iobase = 0; - dev->priv = 0; - dev->init = scc_init; - dev->halt = scc_halt; - dev->send = scc_send; - dev->recv = scc_recv; - - eth_register(dev); - - return 1; -} - -static int scc_send(struct eth_device* dev, volatile void *packet, int length) -{ - int i, j=0; -#if 0 - volatile char *in, *out; -#endif - - /* section 16.9.23.3 - * Wait for ready - */ -#if 0 - while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY); - out = (char *)(rtx->txbd[txIdx].cbd_bufaddr); - in = packet; - for(i = 0; i < length; i++) { - *out++ = *in++; - } - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST); - while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++; - -#ifdef ET_DEBUG - printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); -#endif - i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; - - /* wrap around buffer index when necessary */ - if (txIdx >= TX_BUF_CNT) txIdx = 0; -#endif - - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) printf("TX not ready\n"); - rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP); - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j=TOUT_LOOP) printf("TX timeout\n"); -#ifdef ET_DEBUG - printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc); -#endif - i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */; - return i; -} - -static int scc_recv (struct eth_device *dev) -{ - int length; - - for (;;) { - /* section 16.9.23.2 */ - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = rtx->rxbd[rxIdx].cbd_datlen; - - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { -#ifdef ET_DEBUG - printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); -#endif - } else { - /* Pass the packet up to the protocol layers. */ - NetReceive (NetRxPackets[rxIdx], length - 4); - } - - - /* Give the buffer back to the SCC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - -/************************************************************** - * - * SCC Ethernet Initialization Routine - * - *************************************************************/ - -static int scc_init (struct eth_device *dev, bd_t * bis) -{ - - int i; - scc_enet_t *pram_ptr; - - volatile immap_t *immr = (immap_t *) CFG_IMMR; - -#if defined(CONFIG_LWMON) - reset_phy(); -#endif - -#ifdef CONFIG_FADS -#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T) - /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */ - *((uint *) BCSR4) &= ~BCSR4_ETHLOOP; - *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL; - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#else - *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN); - *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE; - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#endif -#endif - - pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]); - - rxIdx = 0; - txIdx = 0; - -#ifdef CFG_ALLOC_DPRAM - rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + - dpram_alloc_align (sizeof (RTXBD), 8)); -#else - rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE); -#endif /* 0 */ - -#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) - /* Configure port A pins for Txd and Rxd. - */ - immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; -#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) - /* Configure port B pins for Txd and Rxd. - */ - immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD; -#else -#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined -#endif - -#if defined(PC_ENET_LBK) - /* Configure port C pins to disable External Loopback - */ - immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdir |= PC_ENET_LBK; - immr->im_ioport.iop_pcso &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ -#endif /* PC_ENET_LBK */ - - /* Configure port C pins to enable CLSN and RENA. - */ - immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); - - /* Configure port A for TCLK and RCLK. - */ - immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); - immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); - - /* - * Configure Serial Interface clock routing -- see section 16.7.5.3 - * First, clear all SCC bits to zero, then set the ones we want. - */ - - immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; - immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; - - - /* - * Initialize SDCR -- see section 16.9.23.7 - * SDMA configuration register - */ - immr->im_siu_conf.sc_sdcr = 0x01; - - - /* - * Setup SCC Ethernet Parameter RAM - */ - - pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ - pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ - - pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ - - pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */ - pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */ - - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; - } - - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Add PADs to Short FRAMES, Wrap, Last, Tx CRC - */ - - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = - (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* - * Enter Command: Initialize Rx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Ethernet Specific Parameter RAM - * see table 13-16, pg. 660, - * pg. 681 (example with suggested settings) - */ - - pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ - pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ - pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ - pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ - pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ - pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ - - pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ - pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ - pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ - - pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ - pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ - - pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ - pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ - pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ - pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ - -#define ea eth_get_dev()->enetaddr - pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - - pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ - pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ - pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ - pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ - pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ - pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ - pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ - pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ - - /* - * Enter Command: Initialize Tx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Mask all Events in SCCM - we use polling mode - */ - immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0; - - /* - * Clear Events in SCCE -- Clear bits by writing 1's - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0); - - - /* - * Initialize GSMR High 32-Bits - * Settings: Normal Mode - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0; - - /* - * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive - * Settings: - * TCI = Invert - * TPL = 48 bits - * TPP = Repeating 10's - * MODE = Ethernet - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI | - SCC_GSMRL_TPL_48 | - SCC_GSMRL_TPP_10 | - SCC_GSMRL_MODE_ENET); - - /* - * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555; - - /* - * Initialize the PSMR - * Settings: - * CRC = 32-Bit CCITT - * NIB = Begin searching for SFD 22 bits after RENA - * FDE = Full Duplex Enable - * LPB = Loopback Enable (Needed when FDE is set) - * BRO = Reject broadcast packets - * PROMISCOUS = Catch all packets regardless of dest. MAC adress - */ - immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC | - SCC_PSMR_NIB22 | -#if defined(CONFIG_SCC_ENET_FULL_DUPLEX) - SCC_PSMR_FDE | SCC_PSMR_LPB | -#endif -#if defined(CONFIG_SCC_ENET_NO_BROADCAST) - SCC_PSMR_BRO | -#endif -#if defined(CONFIG_SCC_ENET_PROMISCOUS) - SCC_PSMR_PRO | -#endif - 0; - - /* - * Configure Ethernet TENA Signal - */ - -#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA)) - immr->im_ioport.iop_pcpar |= PC_ENET_TENA; - immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA; -#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA)) - immr->im_cpm.cp_pbpar |= PB_ENET_TENA; - immr->im_cpm.cp_pbdir |= PB_ENET_TENA; -#else -#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined -#endif - -#if defined(CONFIG_ADS) && defined(CONFIG_MPC860) - /* - * Port C is used to control the PHY,MC68160. - */ - immr->im_ioport.iop_pcdir |= - (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL); - - immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL; - immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL); - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#endif /* MPC860ADS */ - -#if defined(CONFIG_AMX860) - /* - * Port B is used to control the PHY,MC68160. - */ - immr->im_cpm.cp_pbdir |= - (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL); - - immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL; - immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL); - - immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN; - immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN; -#endif /* AMX860 */ - -#ifdef CONFIG_RPXCLASSIC - *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; - *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); -#endif - -#ifdef CONFIG_RPXLITE - *((uchar *) BCSR0) |= BCSR0_ETHEN; -#endif - -#if defined(CONFIG_QS860T) - /* - * PB27=FDE-, set output low for full duplex - * PB26=Link Test Enable, normally high output - */ - immr->im_cpm.cp_pbdir |= 0x00000030; - immr->im_cpm.cp_pbdat |= 0x00000020; - immr->im_cpm.cp_pbdat &= ~0x00000010; -#endif /* QS860T */ - -#ifdef CONFIG_MBX - board_ether_init (); -#endif - -#if defined(CONFIG_NETVIA) -#if defined(PA_ENET_PDN) - immr->im_ioport.iop_papar &= ~PA_ENET_PDN; - immr->im_ioport.iop_padir |= PA_ENET_PDN; - immr->im_ioport.iop_padat |= PA_ENET_PDN; -#elif defined(PB_ENET_PDN) - immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN; - immr->im_cpm.cp_pbdir |= PB_ENET_PDN; - immr->im_cpm.cp_pbdat |= PB_ENET_PDN; -#elif defined(PC_ENET_PDN) - immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN; - immr->im_ioport.iop_pcdir |= PC_ENET_PDN; - immr->im_ioport.iop_pcdat |= PC_ENET_PDN; -#elif defined(PD_ENET_PDN) - immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN; - immr->im_ioport.iop_pddir |= PD_ENET_PDN; - immr->im_ioport.iop_pddat |= PD_ENET_PDN; -#endif -#endif - - /* - * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive - */ - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= - (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* - * Work around transmit problem with first eth packet - */ -#if defined (CONFIG_FADS) - udelay (10000); /* wait 10 ms */ -#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC) - udelay (100000); /* wait 100 ms */ -#endif - - return 1; -} - - -static void scc_halt (struct eth_device *dev) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= - ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA); -} - -#if 0 -void restart (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= - (SCC_GSMRL_ENR | SCC_GSMRL_ENT); -} -#endif -#endif /* CFG_CMD_NET, SCC_ENET */ diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c deleted file mode 100644 index fa0405f..0000000 --- a/cpu/mpc8xx/serial.c +++ /dev/null @@ -1,722 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */ - -#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ -#define SMC_INDEX 0 -#define PROFF_SMC PROFF_SMC1 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 - -#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */ -#define SMC_INDEX 1 -#define PROFF_SMC PROFF_SMC2 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC2 - -#endif /* CONFIG_8xx_CONS_SMCx */ - -#if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */ -#define SCC_INDEX 0 -#define PROFF_SCC PROFF_SCC1 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC1 - -#elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */ -#define SCC_INDEX 1 -#define PROFF_SCC PROFF_SCC2 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC2 - -#elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */ -#define SCC_INDEX 2 -#define PROFF_SCC PROFF_SCC3 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC3 - -#elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */ -#define SCC_INDEX 3 -#define PROFF_SCC PROFF_SCC4 -#define CPM_CR_CH_SCC CPM_CR_CH_SCC4 - -#endif /* CONFIG_8xx_CONS_SCCx */ - -static void serial_setdivisor(volatile cpm8xx_t *cp) -{ - DECLARE_GLOBAL_DATA_PTR; - int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate; - - if(divisor/16>0x1000) { - /* bad divisor, assume 50Mhz clock and 9600 baud */ - divisor=(50*1000*1000 + 8*9600)/16/9600; - } - -#ifdef CFG_BRGCLK_PRESCALE - divisor /= CFG_BRGCLK_PRESCALE; -#endif - - if(divisor<=0x1000) { - cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN; - } else { - cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16; - } -} - -#if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2)) - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -static void smc_setbrg (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SMCx - */ - - cp->cp_simode = 0x00000000; - - serial_setdivisor(cp); -} - -static int smc_init (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); -#if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850)) - volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); -#endif - uint dpaddr; - - /* initialize pointers to SMC */ - - sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); - up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 1; - - /* clear error conditions */ -#ifdef CFG_SDSR - im->im_sdma.sdma_sdsr = CFG_SDSR; -#else - im->im_sdma.sdma_sdsr = 0x83; -#endif - - /* clear SDMA interrupt mask */ -#ifdef CFG_SDMR - im->im_sdma.sdma_sdmr = CFG_SDMR; -#else - im->im_sdma.sdma_sdmr = 0x00; -#endif - -#if defined(CONFIG_8xx_CONS_SMC1) - /* Use Port B for SMC1 instead of other functions. - */ - cp->cp_pbpar |= 0x000000c0; - cp->cp_pbdir &= ~0x000000c0; - cp->cp_pbodr &= ~0x000000c0; -#else /* CONFIG_8xx_CONS_SMC2 */ -# if defined(CONFIG_MPC823) || defined(CONFIG_MPC850) - /* Use Port A for SMC2 instead of other functions. - */ - ip->iop_papar |= 0x00c0; - ip->iop_padir &= ~0x00c0; - ip->iop_paodr &= ~0x00c0; -# else /* must be a 860 then */ - /* Use Port B for SMC2 instead of other functions. - */ - cp->cp_pbpar |= 0x00000c00; - cp->cp_pbdir &= ~0x00000c00; - cp->cp_pbodr &= ~0x00000c00; -# endif -#endif - -#if defined(CONFIG_FADS) || defined(CONFIG_ADS) - /* Enable RS232 */ -#if defined(CONFIG_8xx_CONS_SMC1) - *((uint *) BCSR1) &= ~BCSR1_RS232EN_1; -#else - *((uint *) BCSR1) &= ~BCSR1_RS232EN_2; -#endif -#endif /* CONFIG_FADS */ - -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) - /* Enable Monitor Port Transceiver */ - *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ; -#endif /* CONFIG_RPXLITE */ - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - -#ifdef CFG_ALLOC_DPRAM - dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; -#else - dpaddr = CPM_SERIAL_BASE ; -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data - */ - - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr+sizeof(cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; - -#if defined(CONFIG_MBX) - board_serial_init(); -#endif /* CONFIG_MBX */ - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - */ - smc_setbrg (); - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; - - return (0); -} - -static void -smc_putc(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - -#ifdef CONFIG_MODEM_SUPPORT - DECLARE_GLOBAL_DATA_PTR; - - if (gd->be_quiet) - return; -#endif - - if (c == '\n') - smc_putc ('\r'); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *)tbdf->cbd_bufaddr; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__("eieio"); - - while (tbdf->cbd_sc & BD_SC_READY) { - WATCHDOG_RESET (); - __asm__("eieio"); - } -} - -static void -smc_puts (const char *s) -{ - while (*s) { - smc_putc (*s++); - } -} - -static int -smc_getc(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - - while (rbdf->cbd_sc & BD_SC_EMPTY) - WATCHDOG_RESET (); - - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -static int -smc_tstc(void) -{ - volatile cbd_t *rbdf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} - -struct serial_device serial_smc_device = -{ - "serial_smc", - "SMC", - smc_init, - smc_setbrg, - smc_getc, - smc_tstc, - smc_putc, - smc_puts, -}; - -#endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */ - -#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \ - defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) - -static void -scc_setbrg (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SCCx - */ - - cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX)); - - serial_setdivisor(cp); -} - -static int scc_init (void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; -#if (SCC_INDEX != 2) || !defined(CONFIG_MPC850) - volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); -#endif - - /* initialize pointers to SCC */ - - sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]); - up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC]; - -#if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2) - { /* Disable Ethernet, enable Serial */ - uchar c; - - c = pic_read (0x61); - c &= ~0x40; /* enable COM3 */ - c |= 0x80; /* disable Ethernet */ - pic_write (0x61, c); - - /* enable RTS2 */ - cp->cp_pbpar |= 0x2000; - cp->cp_pbdat |= 0x2000; - cp->cp_pbdir |= 0x2000; - } -#endif /* CONFIG_LWMON */ - - /* Disable transmitter/receiver. - */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - -#if (SCC_INDEX == 2) && defined(CONFIG_MPC850) - /* - * The MPC850 has SCC3 on Port B - */ - cp->cp_pbpar |= 0x06; - cp->cp_pbdir &= ~0x06; - cp->cp_pbodr &= ~0x06; - -#elif (SCC_INDEX < 2) || !defined(CONFIG_IP860) - /* - * Standard configuration for SCC's is on Part A - */ - ip->iop_papar |= ((3 << (2 * SCC_INDEX))); - ip->iop_padir &= ~((3 << (2 * SCC_INDEX))); - ip->iop_paodr &= ~((3 << (2 * SCC_INDEX))); -#else - /* - * The IP860 has SCC3 and SCC4 on Port D - */ - ip->iop_pdpar |= ((3 << (2 * SCC_INDEX))); -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - */ - -#ifdef CFG_ALLOC_DPRAM - dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; -#else - dpaddr = CPM_SERIAL2_BASE ; -#endif - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 0x0001; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the baud rate generator. - */ - scc_setbrg (); - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - - /* Initialize Tx/Rx parameters. - */ - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - up->scc_genscc.scc_rfcr = SCC_EB | 0x05; - up->scc_genscc.scc_tfcr = SCC_EB | 0x05; - - up->scc_genscc.scc_mrblr = 1; /* Single character receive */ - up->scc_maxidl = 0; /* disable max idle */ - up->scc_brkcr = 1; /* send one break character on stop TX */ - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = 0x8000; - up->scc_char2 = 0x8000; - up->scc_char3 = 0x8000; - up->scc_char4 = 0x8000; - up->scc_char5 = 0x8000; - up->scc_char6 = 0x8000; - up->scc_char7 = 0x8000; - up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Set low latency / small fifo. - */ - sp->scc_gsmrh = SCC_GSMRH_RFW; - - /* Set SCC(x) clock mode to 16x - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SCCn - */ - - /* Set UART mode, clock divider 16 on Tx and Rx - */ - sp->scc_gsmrl &= ~0xF; - sp->scc_gsmrl |= - (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); - - sp->scc_psmr = 0; - sp->scc_psmr |= SCU_PSMR_CL; - - /* Mask all interrupts and remove anything pending. - */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - sp->scc_dsr = 0x7e7e; - sp->scc_psmr = 0x3000; - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Enable transmitter/receiver. - */ - sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - return (0); -} - -static void -scc_putc(const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - -#ifdef CONFIG_MODEM_SUPPORT - DECLARE_GLOBAL_DATA_PTR; - - if (gd->be_quiet) - return; -#endif - - if (c == '\n') - scc_putc ('\r'); - - up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; - - tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *)tbdf->cbd_bufaddr; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__("eieio"); - - while (tbdf->cbd_sc & BD_SC_READY) { - __asm__("eieio"); - WATCHDOG_RESET (); - } -} - -static void -scc_puts (const char *s) -{ - while (*s) { - scc_putc (*s++); - } -} - -static int -scc_getc(void) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - - up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - - while (rbdf->cbd_sc & BD_SC_EMPTY) - WATCHDOG_RESET (); - - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return(c); -} - -static int -scc_tstc(void) -{ - volatile cbd_t *rbdf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; - - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); -} - -struct serial_device serial_scc_device = -{ - "serial_scc", - "SCC", - scc_init, - scc_setbrg, - scc_getc, - scc_tstc, - scc_putc, - scc_puts, -}; - -#endif /* CONFIG_8xx_CONS_SCCx */ - -#ifdef CONFIG_MODEM_SUPPORT -void disable_putc(void) -{ - DECLARE_GLOBAL_DATA_PTR; - gd->be_quiet = 1; -} - -void enable_putc(void) -{ - DECLARE_GLOBAL_DATA_PTR; - gd->be_quiet = 0; -} -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - -void -kgdb_serial_init(void) -{ - int i = -1; - - if (strcmp(default_serial_console()->ctlr, "SMC") == 0) - { -#if defined(CONFIG_8xx_CONS_SMC1) - i = 1; -#elif defined(CONFIG_8xx_CONS_SMC2) - i = 2; -#endif - } - else if (strcmp(default_serial_console()->ctlr, "SMC") == 0) - { -#if defined(CONFIG_8xx_CONS_SCC1) - i = 1; -#elif defined(CONFIG_8xx_CONS_SCC2) - i = 2; -#elif defined(CONFIG_8xx_CONS_SCC3) - i = 3; -#elif defined(CONFIG_8xx_CONS_SCC4) - i = 4; -#endif - } - - if (i >= 0) - { - serial_printf("[on %s%d] ", default_serial_console()->ctlr, i); - } -} - -void -putDebugChar (int c) -{ - serial_putc (c); -} - -void -putDebugStr (const char *str) -{ - serial_puts (str); -} - -int -getDebugChar (void) -{ - return serial_getc(); -} - -void -kgdb_interruptible (int yes) -{ - return; -} -#endif /* CFG_CMD_KGDB */ - -#endif /* CONFIG_8xx_CONS_NONE */ diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c deleted file mode 100644 index f038316..0000000 --- a/cpu/mpc8xx/speed.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG) - -#define PITC_SHIFT 16 -#define PITR_SHIFT 16 -/* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */ -#define SPEED_PIT_COUNTS 58 -#define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT) -#define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT) - -/* Access functions for the Machine State Register */ -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Measure CPU clock speed (core clock GCLK1, GCLK2), - * also determine bus clock speed (checking bus divider factor) - * - * (Approx. GCLK frequency in Hz) - * - * Initializes timer 2 and PIT, but disables them before return. - * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4] - * - * When measuring the CPU clock against the PIT, we count cpu clocks - * for 58/8192 seconds with a prescale divide by 177 for the cpu clock. - * These strange values for the timing interval and prescaling are used - * because the formula for the CPU clock is: - * - * CPU clock = count * (177 * (8192 / 58)) - * - * = count * 24999.7241 - * - * which is very close to - * - * = count * 25000 - * - * Since the count gives the CPU clock divided by 25000, we can get - * the CPU clock rounded to the nearest 0.1 MHz by - * - * CPU clock = ((count + 2) / 4) * 100000; - * - * The rounding is important since the measurement is sometimes going - * to be high or low by 0.025 MHz, depending on exactly how the clocks - * and counters interact. By rounding we get the exact answer for any - * CPU clock that is an even multiple of 0.1 MHz. - */ - -unsigned long measure_gclk(void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer; - ulong timer2_val; - ulong msr_val; - -#ifdef CFG_8XX_XIN - /* dont use OSCM, only use EXTCLK/512 */ - immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV; -#else - immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV); -#endif - - /* Reset + Stop Timer 2, no cascading - */ - timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2); - - /* Keep stopped, halt in debug mode - */ - timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2); - - /* Timer 2 setup: - * Output ref. interrupt disable, int. clock - * Prescale by 177. Note that prescaler divides by value + 1 - * so we must subtract 1 here. - */ - timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN; - - timerp->cpmt_tcn2 = 0; /* reset state */ - timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */ - - /* - * PIT setup: - * - * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz), - * so the count value would be SPEED_PITC_COUNTS - 1. - * But there would be an uncertainty in the start time of 1/4 - * count since when we enable the PIT the count is not - * synchronized to the 32768 Hz oscillator. The trick here is - * to start the count higher and wait until the PIT count - * changes to the required value before starting timer 2. - * - * One count high should be enough, but occasionally the start - * is off by 1 or 2 counts of 32768 Hz. With the start value - * set two counts high it seems very reliable. - */ - - immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */ - immr->im_sit.sit_pitc = SPEED_PITC_INIT; - - immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CFG_PISCR; - - /* - * Start measurement - disable interrupts, just in case - */ - msr_val = get_msr (); - set_msr (msr_val & ~MSR_EE); - - immr->im_sit.sit_piscr |= PISCR_PTE; - - /* spin until get exact count when we want to start */ - while (immr->im_sit.sit_pitr > SPEED_PITC); - - timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */ - while ((immr->im_sit.sit_piscr & PISCR_PS) == 0); - timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */ - - /* re-enable external interrupts if they were on */ - set_msr (msr_val); - - /* Disable timer and PIT - */ - timer2_val = timerp->cpmt_tcn2; /* save before reset timer */ - - timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2); - immr->im_sit.sit_piscr &= ~PISCR_PTE; - -#if defined(CFG_8XX_XIN) - /* not using OSCM, using XIN, so scale appropriately */ - return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L; -#else - return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */ -#endif -} - -#endif - -#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) - -/* - * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ - * or (if it is not defined) measure_gclk() (which uses the ref clock) - * from above. - */ -int get_clocks (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - uint immr = get_immr (0); /* Return full IMMR contents */ - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); - uint sccr = immap->im_clkrst.car_sccr; - /* - * If for some reason measuring the gclk frequency won't - * work, we return the hardwired value. - * (For example, the cogent CMA286-60 CPU module has no - * separate oscillator for PITRTCLK) - */ -#if defined(CONFIG_8xx_GCLK_FREQ) - gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; -#elif defined(CONFIG_8xx_OSCLK) -#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) - uint pll = immap->im_clkrst.car_plprcr; - uint clk; - - if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ - clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) * - (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) / - (1<cpu_clk = clk / (2 << ((sccr >> 8) & 7)); - } else { /* High frequency division factor is used */ - gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7)); - } -#else - gd->cpu_clk = measure_gclk(); -#endif /* CONFIG_8xx_GCLK_FREQ */ - - if ((sccr & SCCR_EBDF11) == 0) { - /* No Bus Divider active */ - gd->bus_clk = gd->cpu_clk; - } else { - /* The MPC8xx has only one BDF: half clock speed */ - gd->bus_clk = gd->cpu_clk / 2; - } - - return (0); -} - -#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */ - -static long init_pll_866 (long clk); - -/* This function sets up PLL (init_pll_866() is called) and - * fills gd->cpu_clk and gd->bus_clk according to the environment - * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk' - * contains invalid value). - * This functions requires an MPC866 or newer series CPU. - */ -int get_clocks_866 (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *) CFG_IMMR; - char tmp[64]; - long cpuclk = 0; - long sccr_reg; - - if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) - cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; - - if ((CFG_8xx_CPUCLK_MIN > cpuclk) || (CFG_8xx_CPUCLK_MAX < cpuclk)) - cpuclk = CONFIG_8xx_CPUCLK_DEFAULT; - - gd->cpu_clk = init_pll_866 (cpuclk); -#if defined(CFG_MEASURE_CPUCLK) - gd->cpu_clk = measure_gclk (); -#endif - - /* if cpu clock <= 66 MHz then set bus division factor to 1, - * otherwise set it to 2 - */ - sccr_reg = immr->im_clkrst.car_sccr; - sccr_reg &= ~SCCR_EBDF11; - if (gd->cpu_clk <= 66000000) { - sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ - gd->bus_clk = gd->cpu_clk; - } else { - sccr_reg |= SCCR_EBDF01; /* bus division factor = 2 */ - gd->bus_clk = gd->cpu_clk / 2; - } - immr->im_clkrst.car_sccr = sccr_reg; - - return (0); -} - -/* Adjust sdram refresh rate to actual CPU clock. - */ -int sdram_adjust_866 (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *) CFG_IMMR; - long mamr; - - mamr = immr->im_memctl.memc_mamr; - mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT); - immr->im_memctl.memc_mamr = mamr; - - return (0); -} - -/* Configure PLL for MPC866/859/885 CPU series - * PLL multiplication factor is set to the value nearest to the desired clk, - * assuming a oscclk of 10 MHz. - */ -static long init_pll_866 (long clk) -{ - extern void plprcr_write_866 (long); - - volatile immap_t *immr = (immap_t *) CFG_IMMR; - long n, plprcr; - char mfi, mfn, mfd, s, pdf; - long step_mfi, step_mfn; - - if (clk < 20000000) { - clk *= 2; - pdf = 1; - } else { - pdf = 0; - } - - if (clk < 40000000) { - s = 2; - step_mfi = CONFIG_8xx_OSCLK / 4; - mfd = 7; - step_mfn = CONFIG_8xx_OSCLK / 30; - } else if (clk < 80000000) { - s = 1; - step_mfi = CONFIG_8xx_OSCLK / 2; - mfd = 14; - step_mfn = CONFIG_8xx_OSCLK / 30; - } else { - s = 0; - step_mfi = CONFIG_8xx_OSCLK; - mfd = 29; - step_mfn = CONFIG_8xx_OSCLK / 30; - } - - /* Calculate integer part of multiplication factor - */ - n = clk / step_mfi; - mfi = (char)n; - - /* Calculate numerator of fractional part of multiplication factor - */ - n = clk - (n * step_mfi); - mfn = (char)(n / step_mfn); - - /* Calculate effective clk - */ - n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1); - - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - - plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK - | PLPRCR_MFD_MSK | PLPRCR_S_MSK - | PLPRCR_MFI_MSK | PLPRCR_DBRMO - | PLPRCR_PDF_MSK)) - | (mfn << PLPRCR_MFN_SHIFT) - | (mfd << PLPRCR_MFD_SHIFT) - | (s << PLPRCR_S_SHIFT) - | (mfi << PLPRCR_MFI_SHIFT) - | (pdf << PLPRCR_PDF_SHIFT); - - if( (mfn > 0) && ((mfd / mfn) > 10) ) - plprcr |= PLPRCR_DBRMO; - - plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */ - immr->im_clkrstk.cark_plprcrk = 0x00000000; - - return (n); -} - -#endif /* CONFIG_8xx_CPUCLK_DEFAULT */ - -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) -/* - * Adjust sdram refresh rate to actual CPU clock - * and set timebase source according to actual CPU clock - */ -int adjust_sdram_tbs_8xx (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile immap_t *immr = (immap_t *) CFG_IMMR; - long mamr; - long sccr; - - mamr = immr->im_memctl.memc_mamr; - mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT); - immr->im_memctl.memc_mamr = mamr; - - if (gd->cpu_clk < 67000000) { - sccr = immr->im_clkrst.car_sccr; - sccr |= SCCR_TBS; - immr->im_clkrst.car_sccr = sccr; - } - - return (0); -} -#endif /* CONFIG_TQM8xxL/M, !TQM866M */ - -/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8xx/spi.c b/cpu/mpc8xx/spi.c deleted file mode 100644 index e318ed0..0000000 --- a/cpu/mpc8xx/spi.c +++ /dev/null @@ -1,560 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * , - * - * Copyright (c) 2001 Gerd Mennchen - * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, . - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MPC8xx CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd@denx.de - * - */ - -#include -#include -#include -#include -#include -#include -#include - -#if (defined(CONFIG_SPI)) || (CONFIG_POST & CFG_POST_SPI) - -/* Warning: - * You cannot enable DEBUG for early system initalization, i. e. when - * this driver is used to read environment parameters like "baudrate" - * from EEPROM which are used to initialize the serial port which is - * needed to print the debug messages... - */ -#undef DEBUG - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0xb00 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CFG_SPI_INIT_OFFSET -#define CFG_SPI_INIT_OFFSET 0xB00 -#endif - -#ifdef DEBUG - -#define DPRINT(a) printf a; -/* ----------------------------------------------- - * Helper functions to peek into tx and rx buffers - * ----------------------------------------------- */ -static const char * const hex_digit = "0123456789ABCDEF"; - -static char quickhex (int i) -{ - return hex_digit[i]; -} - -static void memdump (void *pv, int num) -{ - int i; - unsigned char *pc = (unsigned char *) pv; - - for (i = 0; i < num; i++) - printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); - printf ("\t"); - for (i = 0; i < num; i++) - printf ("%c", isprint (pc[i]) ? pc[i] : '.'); - printf ("\n"); -} -#else /* !DEBUG */ - -#define DPRINT(a) - -#endif /* DEBUG */ - -/* ------------------- - * Function prototypes - * ------------------- */ -void spi_init (void); - -ssize_t spi_read (uchar *, int, uchar *, int); -ssize_t spi_write (uchar *, int, uchar *, int); -ssize_t spi_xfer (size_t); - -/* ------------------- - * Variables - * ------------------- */ - -#define MAX_BUFFER 0x104 - -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem - [CFG_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem - [CFG_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f (void) -{ - unsigned int dpaddr; - - volatile spi_t *spi; - volatile immap_t *immr; - volatile cpic8xx_t *cpi; - volatile cpm8xx_t *cp; - volatile iop8xx_t *iop; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CFG_IMMR; - cpi = (cpic8xx_t *)&immr->im_cpic; - iop = (iop8xx_t *) &immr->im_ioport; - cp = (cpm8xx_t *) &immr->im_cpm; - -#ifdef CFG_SPI_UCODE_PATCH - spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; -#else - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; - /* Disable relocation */ - spi->spi_rpbase = 0; -#endif - -/* 1 */ - /* ------------------------------------------------ - * Initialize Port B SPI pins -> page 34-8 MPC860UM - * (we are only in Master Mode !) - * ------------------------------------------------ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO) - * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI) - * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK) - * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM) - * -------------------------------------------- */ - cp->cp_pbpar |= 0x0000000E; /* set bits */ - cp->cp_pbpar &= ~0x00000001; /* reset bit */ - - /* ---------------------------------------------- - * In/Out or per. Function 0/1 - * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO - * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI - * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK - * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM - * ---------------------------------------------- */ - cp->cp_pbdir |= 0x0000000F; - - /* ---------------------------------------------- - * open drain or active output - * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO - * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI - * PBODR[30] = 0 [0x00000002] -> active output: SPICLK - * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM - * ---------------------------------------------- */ - - cp->cp_pbodr |= 0x00000008; - cp->cp_pbodr &= ~0x00000007; - - /* Initialize the parameter ram. - * We need to make sure many things are initialized to zero - */ - spi->spi_rstate = 0; - spi->spi_rdp = 0; - spi->spi_rbptr = 0; - spi->spi_rbc = 0; - spi->spi_rxtmp = 0; - spi->spi_tstate = 0; - spi->spi_tdp = 0; - spi->spi_tbptr = 0; - spi->spi_tbc = 0; - spi->spi_txtmp = 0; - - /* Allocate space for one transmit and one receive buffer - * descriptor in the DP ram - */ -#ifdef CFG_ALLOC_DPRAM - dpaddr = dpram_alloc_align (sizeof(cbd_t)*2, 8); -#else - dpaddr = CPM_SPI_BASE; -#endif - -/* 3 */ - /* Set up the SPI parameters in the parameter ram */ - spi->spi_rbase = dpaddr; - spi->spi_tbase = dpaddr + sizeof (cbd_t); - - /***********IMPORTANT******************/ - - /* - * Setting transmit and receive buffer descriptor pointers - * initially to rbase and tbase. Only the microcode patches - * documentation talks about initializing this pointer. This - * is missing from the sample I2C driver. If you dont - * initialize these pointers, the kernel hangs. - */ - spi->spi_rbptr = spi->spi_rbase; - spi->spi_tbptr = spi->spi_tbase; - -/* 4 */ -#ifdef CFG_SPI_UCODE_PATCH - /* - * Initialize required parameters if using microcode patch. - */ - spi->spi_rstate = 0; - spi->spi_tstate = 0; -#else - /* Init SPI Tx + Rx Parameters */ - while (cp->cp_cpcr & CPM_CR_FLG) - ; - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG; - while (cp->cp_cpcr & CPM_CR_FLG) - ; -#endif /* CFG_SPI_UCODE_PATCH */ - -/* 5 */ - /* Set SDMA configuration register */ - immr->im_siu_conf.sc_sdcr = 0x0001; - -/* 6 */ - /* Set to big endian. */ - spi->spi_tfcr = SMC_EB; - spi->spi_rfcr = SMC_EB; - -/* 7 */ - /* Set maximum receive size. */ - spi->spi_mrblr = MAX_BUFFER; - -/* 8 + 9 */ - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; - - tbdf->cbd_sc &= ~BD_SC_READY; - rbdf->cbd_sc &= ~BD_SC_EMPTY; - - /* Set the bd's rx and tx buffer address pointers */ - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - -/* 10 + 11 */ - cp->cp_spim = 0; /* Mask all SPI events */ - cp->cp_spie = SPI_EMASK; /* Clear all SPI events */ - - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r (void) -{ - volatile cpm8xx_t *cp; - volatile spi_t *spi; - volatile immap_t *immr; - volatile cbd_t *tbdf, *rbdf; - - immr = (immap_t *) CFG_IMMR; - cp = (cpm8xx_t *) &immr->im_cpm; - -#ifdef CFG_SPI_UCODE_PATCH - spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; -#else - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; - /* Disable relocation */ - spi->spi_rpbase = 0; -#endif - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *) malloc (MAX_BUFFER); - txbuf = (uchar *) malloc (MAX_BUFFER); - - rbdf->cbd_bufaddr = (ulong) rxbuf; - tbdf->cbd_bufaddr = (ulong) txbuf; - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) { - break; - } - udelay(1000); - } - if (i >= 1000) { - printf ("*** spi_write: Time out while writing!\n"); - } - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer (size_t count) -{ - volatile immap_t *immr; - volatile cpm8xx_t *cp; - volatile spi_t *spi; - cbd_t *tbdf, *rbdf; - ushort loop; - int tm; - - DPRINT (("*** spi_xfer entered ***\n")); - - immr = (immap_t *) CFG_IMMR; - cp = (cpm8xx_t *) &immr->im_cpm; - -#ifdef CFG_SPI_UCODE_PATCH - spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; -#else - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; - /* Disable relocation */ - spi->spi_rpbase = 0; -#endif - - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase]; - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase]; - - /* Set CS for device */ - cp->cp_pbdat &= ~0x0001; - - /* Setting tx bd status and data length */ - tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP; - tbdf->cbd_datlen = count; - - DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", - tbdf->cbd_datlen)); - - /* Setting rx bd status and data length */ - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; - rbdf->cbd_datlen = 0; /* rx length has no significance */ - - loop = cp->cp_spmode & SPMODE_LOOP; - cp->cp_spmode = /*SPMODE_DIV16 |*/ /* BRG/16 mode not used here */ - loop | - SPMODE_REV | - SPMODE_MSTR | - SPMODE_EN | - SPMODE_LEN(8) | /* 8 Bits per char */ - SPMODE_PM(0x8) ; /* medium speed */ - cp->cp_spim = 0; /* Mask all SPI events */ - cp->cp_spie = SPI_EMASK; /* Clear all SPI events */ - - /* start spi transfer */ - DPRINT (("*** spi_xfer: Performing transfer ...\n")); - cp->cp_spcom |= SPI_STR; /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm=0; tm<1000; ++tm) { - if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */ - DPRINT (("*** spi_xfer: Tx buffer empty\n")); - break; - } - if ((tbdf->cbd_sc & BD_SC_READY) == 0) { - DPRINT (("*** spi_xfer: Tx BD done\n")); - break; - } - udelay (1000); - } - if (tm >= 1000) { - printf ("*** spi_xfer: Time out while xferring to/from SPI!\n"); - } - DPRINT (("*** spi_xfer: ... transfer ended\n")); - -#ifdef DEBUG - printf ("\nspi_xfer: txbuf after xfer\n"); - memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */ - printf ("spi_xfer: rxbuf after xfer\n"); - memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */ - printf ("\n"); -#endif - - /* Clear CS for device */ - cp->cp_pbdat |= 0x0001; - - return count; -} -#endif /* CONFIG_SPI || (CONFIG_POST & CFG_POST_SPI) */ - -/* - * SPI test - * - * The Serial Peripheral Interface (SPI) is tested in the local loopback mode. - * The interface is configured accordingly and several packets - * are transfered. The configurable test parameters are: - * TEST_MIN_LENGTH - minimum size of packet to transfer - * TEST_MAX_LENGTH - maximum size of packet to transfer - * TEST_NUM - number of tests - */ - -#if CONFIG_POST & CFG_POST_SPI - -#define TEST_MIN_LENGTH 1 -#define TEST_MAX_LENGTH MAX_BUFFER -#define TEST_NUM 1 - -static void packet_fill (char * packet, int length) -{ - char c = (char) length; - int i; - - for (i = 0; i < length; i++) - { - packet[i] = c++; - } -} - -static int packet_check (char * packet, int length) -{ - char c = (char) length; - int i; - - for (i = 0; i < length; i++) { - if (packet[i] != c++) return -1; - } - - return 0; -} - -int spi_post_test (int flags) -{ - int res = -1; - volatile immap_t *immr = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cp = (cpm8xx_t *) & immr->im_cpm; - int i; - int l; - - spi_init_f (); - spi_init_r (); - - cp->cp_spmode |= SPMODE_LOOP; - - for (i = 0; i < TEST_NUM; i++) { - for (l = TEST_MIN_LENGTH; l <= TEST_MAX_LENGTH; l += 8) { - packet_fill ((char *)txbuf, l); - - spi_xfer (l); - - if (packet_check ((char *)rxbuf, l) < 0) { - goto Done; - } - } - } - - res = 0; - - Done: - - cp->cp_spmode &= ~SPMODE_LOOP; - - /* - * SCC2 parameter RAM space overlaps - * the SPI parameter RAM space. So we need to restore - * the SCC2 configuration if it is used by UART. - */ - -#if !defined(CONFIG_8xx_CONS_NONE) - serial_reinit_all (); -#endif - - if (res != 0) { - post_log ("SPI test failed\n"); - } - - return res; -} -#endif /* CONFIG_POST & CFG_POST_SPI */ diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S deleted file mode 100644 index 33a3f6c..0000000 --- a/cpu/mpc8xx/start.S +++ /dev/null @@ -1,710 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000,2001,2002 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* U-Boot - Startup Code for PowerPC based Embedded Boards - * - * - * The processor starts at 0x00000100 and the code is executed - * from flash. The code is organized to be at an other address - * in memory, but as long we don't jump around before relocating, - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - * This works because the cpu gives the FLASH (CS0) the whole - * address space at startup, and board_init lies as a echo of - * the flash somewhere up there in the memory map. - * - * board_init will change CS0 to be positioned at the correct - * address and (s)dram will be positioned at address 0 - */ -#include -#include -#include - -#define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */ - -/* - * Set up GOT: Global Offset Table - * - * Use r14 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - - . = EXC_OFF_SYS_RESET - .globl _start -_start: - lis r3, CFG_IMMR@h /* position IMMR */ - mtspr 638, r3 - li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ - b boot_cold - - . = EXC_OFF_SYS_RESET + 0x10 - - .globl _start_warm -_start_warm: - li r21, BOOTFLAG_WARM /* Software reboot */ - b boot_warm - -boot_cold: -boot_warm: - - /* Initialize machine status; enable machine check interrupt */ - /*----------------------------------------------------------------------*/ - li r3, MSR_KERNEL /* Set ME, RI flags */ - mtmsr r3 - mtspr SRR1, r3 /* Make SRR1 match MSR */ - - mfspr r3, ICR /* clear Interrupt Cause Register */ - - /* Initialize debug port registers */ - /*----------------------------------------------------------------------*/ - xor r0, r0, r0 /* Clear R0 */ - mtspr LCTRL1, r0 /* Initialize debug port regs */ - mtspr LCTRL2, r0 - mtspr COUNTA, r0 - mtspr COUNTB, r0 - - /* Reset the caches */ - /*----------------------------------------------------------------------*/ - - mfspr r3, IC_CST /* Clear error bits */ - mfspr r3, DC_CST - - lis r3, IDC_UNALL@h /* Unlock all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - lis r3, IDC_INVALL@h /* Invalidate all */ - mtspr IC_CST, r3 - mtspr DC_CST, r3 - - lis r3, IDC_DISABLE@h /* Disable data cache */ - mtspr DC_CST, r3 - -#if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM)) - /* On IP860 and PCU E, - * we cannot enable IC yet - */ - lis r3, IDC_ENABLE@h /* Enable instruction cache */ -#endif - mtspr IC_CST, r3 - - /* invalidate all tlb's */ - /*----------------------------------------------------------------------*/ - - tlbia - isync - - /* - * Calculate absolute address in FLASH and jump there - *----------------------------------------------------------------------*/ - - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET - mtlr r3 - blr - -in_flash: - - /* initialize some SPRs that are hard to access from C */ - /*----------------------------------------------------------------------*/ - - lis r3, CFG_IMMR@h /* pass IMMR as arg1 to C routine */ - ori r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */ - /* Note: R0 is still 0 here */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - /* - * Disable serialized ifetch and show cycles - * (i.e. set processor to normal mode). - * This is also a silicon bug workaround, see errata - */ - - li r2, 0x0007 - mtspr ICTRL, r2 - - /* Set up debug mode entry */ - - lis r2, CFG_DER@h - ori r2, r2, CFG_DER@l - mtspr DER, r2 - - /* let the C-code set up the rest */ - /* */ - /* Be careful to keep code relocatable ! */ - /*----------------------------------------------------------------------*/ - - GET_GOT /* initialize GOT access */ - - /* r3: IMMR */ - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - - mr r3, r21 - /* r3: BOOTFLAG */ - bl board_init_f /* run 1st part of board init code (from Flash) */ - - - .globl _start_of_vectors -_start_of_vectors: - -/* Machine check */ - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. "Never" generated on the 860. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - - /* No FPU on MPC8xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - /* On the MPC8xx, this is a software emulation interrupt. It occurs - * for all unimplemented and illegal instructions. - */ - STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) - - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x2000 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -/* Cache functions. -*/ - .globl icache_enable -icache_enable: - SYNC - lis r3, IDC_INVALL@h - mtspr IC_CST, r3 - lis r3, IDC_ENABLE@h - mtspr IC_CST, r3 - blr - - .globl icache_disable -icache_disable: - SYNC - lis r3, IDC_DISABLE@h - mtspr IC_CST, r3 - blr - - .globl icache_status -icache_status: - mfspr r3, IC_CST - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl dcache_enable -dcache_enable: -#if 0 - SYNC -#endif -#if 1 - lis r3, 0x0400 /* Set cache mode with MMU off */ - mtspr MD_CTR, r3 -#endif - - lis r3, IDC_INVALL@h - mtspr DC_CST, r3 -#if 0 - lis r3, DC_SFWT@h - mtspr DC_CST, r3 -#endif - lis r3, IDC_ENABLE@h - mtspr DC_CST, r3 - blr - - .globl dcache_disable -dcache_disable: - SYNC - lis r3, IDC_DISABLE@h - mtspr DC_CST, r3 - lis r3, IDC_INVALL@h - mtspr DC_CST, r3 - blr - - .globl dcache_status -dcache_status: - mfspr r3, DC_CST - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl dc_read -dc_read: - mtspr DC_ADR, r3 - mfspr r3, DC_DAT - blr - -/* - * unsigned int get_immr (unsigned int mask) - * - * return (mask ? (IMMR & mask) : IMMR); - */ - .globl get_immr -get_immr: - mr r4,r3 /* save mask */ - mfspr r3, IMMR /* IMMR */ - cmpwi 0,r4,0 /* mask != 0 ? */ - beq 4f - and r3,r3,r4 /* IMMR & mask */ -4: - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - - .globl wr_ic_cst -wr_ic_cst: - mtspr IC_CST, r3 - blr - - .globl rd_ic_cst -rd_ic_cst: - mfspr r3, IC_CST - blr - - .globl wr_ic_adr -wr_ic_adr: - mtspr IC_ADR, r3 - blr - - - .globl wr_dc_cst -wr_dc_cst: - mtspr DC_CST, r3 - blr - - .globl rd_dc_cst -rd_dc_cst: - mfspr r3, DC_CST - blr - - .globl wr_dc_adr -wr_dc_adr: - mtspr DC_ADR, r3 - blr - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Global Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r14, r14, r15 - /* then the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr - -in_ram: - - /* - * Relocation Function, r14 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - add r0,r0,r11 - stw r0,0(r3) - bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ -2: li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Global Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mtlr r4 /* restore link register */ - blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - sync - isync - - blr diff --git a/cpu/mpc8xx/traps.c b/cpu/mpc8xx/traps.c deleted file mode 100644 index 67b75cc..0000000 --- a/cpu/mpc8xx/traps.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * linux/arch/ppc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -int (*debugger_exception_handler)(struct pt_regs *) = 0; -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. -*/ -#define END_OF_MEM 0x02000000 - -/* - * Trap & Exception support - */ - -void -print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs * regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -void -_exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void -MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void -AlignmentException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void -ProgramCheckException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void -SoftEmuException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Software Emulation Exception"); -} - - -void -UnknownException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -void -DebugException(struct pt_regs *regs) -{ - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int -addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/cpu/mpc8xx/upatch.c b/cpu/mpc8xx/upatch.c deleted file mode 100644 index eccff64..0000000 --- a/cpu/mpc8xx/upatch.c +++ /dev/null @@ -1,102 +0,0 @@ -#include -#include - -#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) - -static void UcodeCopy (volatile cpm8xx_t *cpm); - -void cpm_load_patch (volatile immap_t *immr) -{ - immr->im_cpm.cp_rccr &= ~0x0003; /* Disable microcode program area */ - - UcodeCopy ((cpm8xx_t *)&immr->im_cpm); /* Copy ucode patch to DPRAM */ -#ifdef CFG_SPI_UCODE_PATCH - { - volatile spi_t *spi = (spi_t *) & immr->im_cpm.cp_dparam[PROFF_SPI]; - /* Activate the microcode per the instructions in the microcode manual */ - /* NOTE: We're only relocating the SPI parameters (not I2C). */ - immr->im_cpm.cp_cpmcr1 = 0x802a; /* Write Trap register 1 value */ - immr->im_cpm.cp_cpmcr2 = 0x8028; /* Write Trap register 2 value */ - spi->spi_rpbase = CFG_SPI_DPMEM_OFFSET; /* Where to relocte SPI params */ - } -#endif - -#ifdef CFG_I2C_UCODE_PATCH - { - volatile iic_t *iip = (iic_t *) & immr->im_cpm.cp_dparam[PROFF_IIC]; - /* Activate the microcode per the instructions in the microcode manual */ - /* NOTE: We're only relocating the I2C parameters (not SPI). */ - immr->im_cpm.cp_cpmcr3 = 0x802e; /* Write Trap register 3 value */ - immr->im_cpm.cp_cpmcr4 = 0x802c; /* Write Trap register 4 value */ - iip->iic_rpbase = CFG_I2C_DPMEM_OFFSET; /* Where to relocte I2C params */ - } -#endif - - /* - * Enable DPRAM microcode to execute from the first 512 bytes - * and a 256 byte extension of DPRAM. - */ - immr->im_cpm.cp_rccr |= 0x0001; -} - -static ulong patch_2000[] = { - 0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000, - 0x5FEFADF7, 0x5F88ADF7, 0x5FEFAFF7, 0x5F88AFF7, - 0x3A9CFBC8, 0x77CAE1BB, 0xF4DE7FAD, 0xABAE9330, - 0x4E08FDCF, 0x6E0FAFF8, 0x7CCF76CF, 0xFDAFF9CF, - 0xABF88DC8, 0xAB5879F7, 0xB0927383, 0xDFD079F7, - 0xB090E6BB, 0xE5BBE74F, 0xB3FA6F0F, 0x6FFB76CE, - 0xEE0CF9CF, 0x2BFBEFEF, 0xCFEEF9CF, 0x76CEAD23, - 0x90B3DF99, 0x7FDDD0C1, 0x4BF847FD, 0x7CCF76CE, - 0xCFEF77CA, 0x7EAF7FAD, 0x7DFDF0B7, 0xEF7A7FCA, - 0x77CAFBC8, 0x6079E722, 0xFBC85FFF, 0xDFFF5FB3, - 0xFFFBFBC8, 0xF3C894A5, 0xE7C9EDF9, 0x7F9A7FAD, - 0x5F36AFE8, 0x5F5BFFDF, 0xDF95CB9E, 0xAF7D5FC3, - 0xAFED8C1B, 0x5FC3AFDD, 0x5FC5DF99, 0x7EFDB0B3, - 0x5FB3FFFE, 0xABAE5FB3, 0xFFFE5FD0, 0x600BE6BB, - 0x600B5FD0, 0xDFC827FB, 0xEFDF5FCA, 0xCFDE3A9C, - 0xE7C9EDF9, 0xF3C87F9E, 0x54CA7FED, 0x2D3A3637, - 0x756F7E9A, 0xF1CE37EF, 0x2E677FEE, 0x10EBADF8, - 0xEFDECFEA, 0xE52F7D9F, 0xE12BF1CE, 0x5F647E9A, - 0x4DF8CFEA, 0x5F717D9B, 0xEFEECFEA, 0x5F73E522, - 0xEFDE5F73, 0xCFDA0B61, 0x7385DF61, 0xE7C9EDF9, - 0x7E9A30D5, 0x1458BFFF, 0xF3C85FFF, 0xDFFFA7F8, - 0x5F5BBFFE, 0x7F7D10D0, 0x144D5F33, 0xBFFFAF78, - 0x5F5BBFFD, 0xA7F85F33, 0xBFFE77FD, 0x30BD4E08, - 0xFDCFE5FF, 0x6E0FAFF8, 0x7EEF7E9F, 0xFDEFF1CF, - 0x5F17ABF8, 0x0D5B5F5B, 0xFFEF79F7, 0x309EAFDD, - 0x5F3147F8, 0x5F31AFED, 0x7FDD50AF, 0x497847FD, - 0x7F9E7FED, 0x7DFD70A9, 0xEF7E7ECE, 0x6BA07F9E, - 0x2D227EFD, 0x30DB5F5B, 0xFFFD5F5B, 0xFFEF5F5B, - 0xFFDF0C9C, 0xAFED0A9A, 0xAFDD0C37, 0x5F37AFBD, - 0x7FBDB081, 0x5F8147F8, -}; - -static ulong patch_2F00[] = { - 0x3E303430, 0x34343737, 0xABBF9B99, 0x4B4FBDBD, - 0x59949334, 0x9FFF37FB, 0x9B177DD9, 0x936956BB, - 0xFBDD697B, 0xDD2FD113, 0x1DB9F7BB, 0x36313963, - 0x79373369, 0x3193137F, 0x7331737A, 0xF7BB9B99, - 0x9BB19795, 0x77FDFD3D, 0x573B773F, 0x737933F7, - 0xB991D115, 0x31699315, 0x31531694, 0xBF4FBDBD, - 0x35931497, 0x35376956, 0xBD697B9D, 0x96931313, - 0x19797937, 0x69350000, -}; - -static void UcodeCopy (volatile cpm8xx_t *cpm) -{ - vu_long *p; - int i; - - p = (vu_long *)&(cpm->cp_dpmem[0x0000]); - for (i=0; i < sizeof(patch_2000)/4; ++i) { - p[i] = patch_2000[i]; - } - - p = (vu_long *)&(cpm->cp_dpmem[0x0F00]); - for (i=0; i < sizeof(patch_2F00)/4; ++i) { - p[i] = patch_2F00[i]; - } -} - -#endif /* CFG_I2C_UCODE_PATCH, CFG_SPI_UCODE_PATCH */ diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c deleted file mode 100644 index ee60477..0000000 --- a/cpu/mpc8xx/video.c +++ /dev/null @@ -1,1330 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * (C) Copyright 2002 - * Wolfgang Denk, wd@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_VIDEO - -/************************************************************************/ -/* ** DEBUG SETTINGS */ -/************************************************************************/ - -#if 0 -#define VIDEO_DEBUG_COLORBARS /* Force colorbars output */ -#endif - -/************************************************************************/ -/* ** VIDEO MODE SETTINGS */ -/************************************************************************/ - -#if 0 -#define VIDEO_MODE_EXTENDED /* Allow screen size bigger than visible area */ -#define VIDEO_MODE_NTSC -#endif - -#define VIDEO_MODE_PAL - -#if 0 -#define VIDEO_BLINK /* This enables cursor blinking (under construction) */ -#endif - -#define VIDEO_INFO /* Show U-Boot information */ -#define VIDEO_INFO_X VIDEO_LOGO_WIDTH+8 -#define VIDEO_INFO_Y 16 - -/************************************************************************/ -/* ** VIDEO ENCODER CONSTANTS */ -/************************************************************************/ - -#ifdef CONFIG_VIDEO_ENCODER_AD7176 - -#include /* Sets encoder data, mode, and visible and active area */ - -#define VIDEO_I2C 1 -#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7176_ADDR -#endif - -#ifdef CONFIG_VIDEO_ENCODER_AD7177 - -#include /* Sets encoder data, mode, and visible and active area */ - -#define VIDEO_I2C 1 -#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7177_ADDR -#endif - -#ifdef CONFIG_VIDEO_ENCODER_AD7179 - -#include /* Sets encoder data, mode, and visible and active area */ - -#define VIDEO_I2C 1 -#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7179_ADDR -#endif - -/************************************************************************/ -/* ** VIDEO MODE CONSTANTS */ -/************************************************************************/ - -#ifdef VIDEO_MODE_EXTENDED -#define VIDEO_COLS VIDEO_ACTIVE_COLS -#define VIDEO_ROWS VIDEO_ACTIVE_ROWS -#else -#define VIDEO_COLS VIDEO_VISIBLE_COLS -#define VIDEO_ROWS VIDEO_VISIBLE_ROWS -#endif - -#define VIDEO_PIXEL_SIZE (VIDEO_MODE_BPP/8) -#define VIDEO_SIZE (VIDEO_ROWS*VIDEO_COLS*VIDEO_PIXEL_SIZE) /* Total size of buffer */ -#define VIDEO_PIX_BLOCKS (VIDEO_SIZE >> 2) /* Number of ints */ -#define VIDEO_LINE_LEN (VIDEO_COLS*VIDEO_PIXEL_SIZE) /* Number of bytes per line */ -#define VIDEO_BURST_LEN (VIDEO_COLS/8) - -#ifdef VIDEO_MODE_YUYV -#define VIDEO_BG_COL 0x80D880D8 /* Background color in YUYV format */ -#else -#define VIDEO_BG_COL 0xF8F8F8F8 /* Background color in RGB format */ -#endif - -/************************************************************************/ -/* ** FONT AND LOGO DATA */ -/************************************************************************/ - -#include /* Get font data, width and height */ - -#ifdef CONFIG_VIDEO_LOGO -#include /* Get logo data, width and height */ - -#define VIDEO_LOGO_WIDTH DEF_U_BOOT_LOGO_WIDTH -#define VIDEO_LOGO_HEIGHT DEF_U_BOOT_LOGO_HEIGHT -#define VIDEO_LOGO_ADDR &u_boot_logo -#endif - -/************************************************************************/ -/* ** VIDEO CONTROLLER CONSTANTS */ -/************************************************************************/ - -/* VCCR - VIDEO CONTROLLER CONFIGURATION REGISTER */ - -#define VIDEO_VCCR_VON 0 /* Video controller ON */ -#define VIDEO_VCCR_CSRC 1 /* Clock source */ -#define VIDEO_VCCR_PDF 13 /* Pixel display format */ -#define VIDEO_VCCR_IEN 11 /* Interrupt enable */ - -/* VSR - VIDEO STATUS REGISTER */ - -#define VIDEO_VSR_CAS 6 /* Active set */ -#define VIDEO_VSR_EOF 0 /* End of frame */ - -/* VCMR - VIDEO COMMAND REGISTER */ - -#define VIDEO_VCMR_BD 0 /* Blank display */ -#define VIDEO_VCMR_ASEL 1 /* Active set selection */ - -/* VBCB - VIDEO BACKGROUND COLOR BUFFER REGISTER */ - -#define VIDEO_BCSR4_RESET_BIT 21 /* BCSR4 - Extern video encoder reset */ -#define VIDEO_BCSR4_EXTCLK_BIT 22 /* BCSR4 - Extern clock enable */ -#define VIDEO_BCSR4_VIDLED_BIT 23 /* BCSR4 - Video led disable */ - -/************************************************************************/ -/* ** CONSOLE CONSTANTS */ -/************************************************************************/ - -#ifdef CONFIG_VIDEO_LOGO -#define CONSOLE_ROWS ((VIDEO_ROWS - VIDEO_LOGO_HEIGHT) / VIDEO_FONT_HEIGHT) -#define VIDEO_LOGO_SKIP (VIDEO_COLS - VIDEO_LOGO_WIDTH) -#else -#define CONSOLE_ROWS (VIDEO_ROWS / VIDEO_FONT_HEIGHT) -#endif - -#define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH) -#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN) -#define CONSOLE_ROW_FIRST (video_console_address) -#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE) -#define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE) -#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) -#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) - -/* - * Simple color definitions - */ -#define CONSOLE_COLOR_BLACK 0 -#define CONSOLE_COLOR_RED 1 -#define CONSOLE_COLOR_GREEN 2 -#define CONSOLE_COLOR_YELLOW 3 -#define CONSOLE_COLOR_BLUE 4 -#define CONSOLE_COLOR_MAGENTA 5 -#define CONSOLE_COLOR_CYAN 6 -#define CONSOLE_COLOR_GREY 13 -#define CONSOLE_COLOR_GREY2 14 -#define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ - -/************************************************************************/ -/* ** BITOPS MACROS */ -/************************************************************************/ - -#define HISHORT(i) ((i >> 16)&0xffff) -#define LOSHORT(i) (i & 0xffff) -#define HICHAR(s) ((i >> 8)&0xff) -#define LOCHAR(s) (i & 0xff) -#define HI(c) ((c >> 4)&0xf) -#define LO(c) (c & 0xf) -#define SWAPINT(i) (HISHORT(i) | (LOSHORT(i) << 16)) -#define SWAPSHORT(s) (HICHAR(s) | (LOCHAR(s) << 8)) -#define SWAPCHAR(c) (HI(c) | (LO(c) << 4)) -#define BITMASK(b) (1 << (b)) -#define GETBIT(v,b) (((v) & BITMASK(b)) > 0) -#define SETBIT(v,b,d) (v = (((d)>0) ? (v) | BITMASK(b): (v) & ~BITMASK(b))) - -/************************************************************************/ -/* ** STRUCTURES */ -/************************************************************************/ - -typedef struct { - unsigned char V, Y1, U, Y2; -} tYUYV; - -/* This structure is based on the Video Ram in the MPC823. */ -typedef struct VRAM { - unsigned hx:2, /* Horizontal sync */ - vx:2, /* Vertical sync */ - fx:2, /* Frame */ - bx:2, /* Blank */ - res1:6, /* Reserved */ - vds:2, /* Video Data Select */ - inter:1, /* Interrupt */ - res2:2, /* Reserved */ - lcyc:11, /* Loop/video cycles */ - lp:1, /* Loop start/end */ - lst:1; /* Last entry */ -} VRAM; - -/************************************************************************/ -/* ** VARIABLES */ -/************************************************************************/ - -static int - video_panning_range_x = 0, /* Video mode invisible pixels x range */ - video_panning_range_y = 0, /* Video mode invisible pixels y range */ - video_panning_value_x = 0, /* Video mode x panning value (absolute) */ - video_panning_value_y = 0, /* Video mode y panning value (absolute) */ - video_panning_factor_x = 0, /* Video mode x panning value (-127 +127) */ - video_panning_factor_y = 0, /* Video mode y panning value (-127 +127) */ - console_col = 0, /* Cursor col */ - console_row = 0, /* Cursor row */ - video_palette[16]; /* Our palette */ - -static const int video_font_draw_table[] = - { 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff }; - -static char - video_color_fg = 0, /* Current fg color index (0-15) */ - video_color_bg = 0, /* Current bg color index (0-15) */ - video_enable = 0; /* Video has been initialized? */ - -static void - *video_fb_address, /* Frame buffer address */ - *video_console_address; /* Console frame buffer start address */ - -/************************************************************************/ -/* ** MEMORY FUNCTIONS (32bit) */ -/************************************************************************/ - -static void memsetl (int *p, int c, int v) -{ - while (c--) - *(p++) = v; -} - -static void memcpyl (int *d, int *s, int c) -{ - while (c--) - *(d++) = *(s++); -} - -/************************************************************************/ -/* ** VIDEO DRAWING AND COLOR FUNCTIONS */ -/************************************************************************/ - -static int video_maprgb (int r, int g, int b) -{ -#ifdef VIDEO_MODE_YUYV - unsigned int pR, pG, pB; - tYUYV YUYV; - unsigned int *ret = (unsigned int *) &YUYV; - - /* Transform (0-255) components to (0-100) */ - - pR = r * 100 / 255; - pG = g * 100 / 255; - pB = b * 100 / 255; - - /* Calculate YUV values (0-255) from RGB beetween 0-100 */ - - YUYV.Y1 = YUYV.Y2 = 209 * (pR + pG + pB) / 300 + 16; - YUYV.U = pR - (pG * 3 / 4) - (pB / 4) + 128; - YUYV.V = pB - (pR / 4) - (pG * 3 / 4) + 128; - return *ret; -#endif -#ifdef VIDEO_MODE_RGB - return ((r >> 3) << 11) | ((g > 2) << 6) | (b >> 3); -#endif -} - -static void video_setpalette (int color, int r, int g, int b) -{ - color &= 0xf; - - video_palette[color] = video_maprgb (r, g, b); - - /* Swap values if our panning offset is odd */ - if (video_panning_value_x & 1) - video_palette[color] = SWAPINT (video_palette[color]); -} - -static void video_fill (int color) -{ - memsetl (video_fb_address, VIDEO_PIX_BLOCKS, color); -} - -static void video_setfgcolor (int i) -{ - video_color_fg = i & 0xf; -} - -static void video_setbgcolor (int i) -{ - video_color_bg = i & 0xf; -} - -static int video_pickcolor (int i) -{ - return video_palette[i & 0xf]; -} - -/* Absolute console plotting functions */ - -#ifdef VIDEO_BLINK -static void video_revchar (int xx, int yy) -{ - int rows; - u8 *dest; - - dest = video_fb_address + yy * VIDEO_LINE_LEN + xx * 2; - - for (rows = VIDEO_FONT_HEIGHT; rows--; dest += VIDEO_LINE_LEN) { - switch (VIDEO_FONT_WIDTH) { - case 16: - ((u32 *) dest)[6] ^= 0xffffffff; - ((u32 *) dest)[7] ^= 0xffffffff; - /* FALL THROUGH */ - case 12: - ((u32 *) dest)[4] ^= 0xffffffff; - ((u32 *) dest)[5] ^= 0xffffffff; - /* FALL THROUGH */ - case 8: - ((u32 *) dest)[2] ^= 0xffffffff; - ((u32 *) dest)[3] ^= 0xffffffff; - /* FALL THROUGH */ - case 4: - ((u32 *) dest)[0] ^= 0xffffffff; - ((u32 *) dest)[1] ^= 0xffffffff; - } - } -} -#endif - -static void video_drawchars (int xx, int yy, unsigned char *s, int count) -{ - u8 *cdat, *dest, *dest0; - int rows, offset, c; - u32 eorx, fgx, bgx; - - offset = yy * VIDEO_LINE_LEN + xx * 2; - dest0 = video_fb_address + offset; - - fgx = video_pickcolor (video_color_fg); - bgx = video_pickcolor (video_color_bg); - - if (xx & 1) { - fgx = SWAPINT (fgx); - bgx = SWAPINT (bgx); - } - - eorx = fgx ^ bgx; - - switch (VIDEO_FONT_WIDTH) { - case 4: - case 8: - while (count--) { - c = *s; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; - rows--; - dest += VIDEO_LINE_LEN) { - u8 bits = *cdat++; - - ((u32 *) dest)[0] = - (video_font_draw_table[bits >> 6] & eorx) ^ bgx; - ((u32 *) dest)[1] = - (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; - if (VIDEO_FONT_WIDTH == 8) { - ((u32 *) dest)[2] = - (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; - ((u32 *) dest)[3] = - (video_font_draw_table[bits & 3] & eorx) ^ bgx; - } - } - dest0 += VIDEO_FONT_WIDTH * 2; - s++; - } - break; - case 12: - case 16: - while (count--) { - cdat = video_fontdata + (*s) * (VIDEO_FONT_HEIGHT << 1); - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; - dest += VIDEO_LINE_LEN) { - u8 bits = *cdat++; - - ((u32 *) dest)[0] = - (video_font_draw_table[bits >> 6] & eorx) ^ bgx; - ((u32 *) dest)[1] = - (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; - ((u32 *) dest)[2] = - (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; - ((u32 *) dest)[3] = - (video_font_draw_table[bits & 3] & eorx) ^ bgx; - bits = *cdat++; - ((u32 *) dest)[4] = - (video_font_draw_table[bits >> 6] & eorx) ^ bgx; - ((u32 *) dest)[5] = - (video_font_draw_table[bits >> 4 & 3] & eorx) ^ bgx; - if (VIDEO_FONT_WIDTH == 16) { - ((u32 *) dest)[6] = - (video_font_draw_table[bits >> 2 & 3] & eorx) ^ bgx; - ((u32 *) dest)[7] = - (video_font_draw_table[bits & 3] & eorx) ^ bgx; - } - } - s++; - dest0 += VIDEO_FONT_WIDTH * 2; - } - break; - } -} - -static inline void video_drawstring (int xx, int yy, char *s) -{ - video_drawchars (xx, yy, (unsigned char *)s, strlen (s)); -} - -/* Relative to console plotting functions */ - -static void video_putchars (int xx, int yy, unsigned char *s, int count) -{ -#ifdef CONFIG_VIDEO_LOGO - video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, s, count); -#else - video_drawchars (xx, yy, s, count); -#endif -} - -static void video_putchar (int xx, int yy, unsigned char c) -{ -#ifdef CONFIG_VIDEO_LOGO - video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, &c, 1); -#else - video_drawchars (xx, yy, &c, 1); -#endif -} - -static inline void video_putstring (int xx, int yy, unsigned char *s) -{ - video_putchars (xx, yy, (unsigned char *)s, strlen ((char *)s)); -} - -/************************************************************************/ -/* ** VIDEO CONTROLLER LOW-LEVEL FUNCTIONS */ -/************************************************************************/ - -#if !defined(CONFIG_RRVISION) -static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries) -{ - int i; - - for (i = 0; i < entries; i++) { - dest[i] = source[i]; /* Copy the entire record */ - dest[i].fx = (!dest[i].fx) * 3; /* Negate field bit */ - } - - dest[0].lcyc++; /* Add a cycle to the first entry */ - dest[entries - 1].lst = 1; /* Set end of ram entries */ -} -#endif - -static void inline video_mode_addentry (VRAM * vr, - int Hx, int Vx, int Fx, int Bx, - int VDS, int INT, int LCYC, int LP, int LST) -{ - vr->hx = Hx; - vr->vx = Vx; - vr->fx = Fx; - vr->bx = Bx; - vr->vds = VDS; - vr->inter = INT; - vr->lcyc = LCYC; - vr->lp = LP; - vr->lst = LST; -} - -#define ADDENTRY(a,b,c,d,e,f,g,h,i) video_mode_addentry(&vr[entry++],a,b,c,d,e,f,g,h,i) - -static int video_mode_generate (void) -{ - immap_t *immap = (immap_t *) CFG_IMMR; - VRAM *vr = (VRAM *) (((void *) immap) + 0xb00); /* Pointer to the VRAM table */ - int DX, X1, X2, DY, Y1, Y2, entry = 0, fifo; - - /* CHECKING PARAMETERS */ - - if (video_panning_factor_y < -128) - video_panning_factor_y = -128; - - if (video_panning_factor_y > 128) - video_panning_factor_y = 128; - - if (video_panning_factor_x < -128) - video_panning_factor_x = -128; - - if (video_panning_factor_x > 128) - video_panning_factor_x = 128; - - /* Setting panning */ - - DX = video_panning_range_x = (VIDEO_ACTIVE_COLS - VIDEO_COLS) * 2; - DY = video_panning_range_y = (VIDEO_ACTIVE_ROWS - VIDEO_ROWS) / 2; - - video_panning_value_x = (video_panning_factor_x + 128) * DX / 256; - video_panning_value_y = (video_panning_factor_y + 128) * DY / 256; - - /* We assume these are burst units (multiplied by 2, we need it pari) */ - X1 = video_panning_value_x & 0xfffe; - X2 = DX - X1; - - /* We assume these are field line units (divided by 2, we need it pari) */ - Y1 = video_panning_value_y & 0xfffe; - Y2 = DY - Y1; - - debug("X1=%d, X2=%d, Y1=%d, Y2=%d, DX=%d, DY=%d VIDEO_COLS=%d \n", - X1, X2, Y1, Y2, DX, DY, VIDEO_COLS); - -#ifdef VIDEO_MODE_NTSC -/* - * Hx Vx Fx Bx VDS INT LCYC LP LST - * - * Retrace blanking - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 3, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 18, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); -/* - * Odd field active area (TOP) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y1, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); - } -/* - * Odd field active area - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 240 - DY, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 8 + X1, 0, 0); - ADDENTRY (3, 0, 0, 3, 0, 0, VIDEO_COLS * 2, 0, 0); - - if (X2 > 0) - ADDENTRY (3, 0, 0, 3, 1, 0, X2, 0, 0); - - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); - -/* - * Odd field active area (BOTTOM) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y2, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); - } -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 4, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 32, 1, 0); -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 19, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); -/* - * Even field active area (TOP) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 3, 0, 1, 0, Y1, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 3, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); - } -/* - * Even field active area (CENTER) - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 240 - DY, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 3, 3, 1, 0, 8 + X1, 0, 0); - ADDENTRY (3, 0, 3, 3, 0, 0, VIDEO_COLS * 2, 0, 0); - - if (X2 > 0) - ADDENTRY (3, 0, 3, 3, 1, 0, X2, 0, 0); - - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); -/* - * Even field active area (BOTTOM) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 3, 0, 1, 0, Y2, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 235, 0, 0); - ADDENTRY (3, 0, 3, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 32, 1, 0); - } -/* - * Vertical blanking - */ - ADDENTRY (0, 0, 3, 0, 1, 0, 1, 1, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 243, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 3, 0, 1, 1, 32, 1, 1); -#endif - -#ifdef VIDEO_MODE_PAL - -#if defined(CONFIG_RRVISION) - -#define HPW 160 /* horizontal pulse width (was 139) */ -#define VPW 2 /* vertical pulse width */ -#define HBP 104 /* horizontal back porch (was 112) */ -#define VBP 19 /* vertical back porch (was 19) */ -#define VID_R 240 /* number of rows */ - - debug ("[VIDEO CTRL] Starting to add controller entries..."); -/* - * Even field - */ - ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0); - - ADDENTRY (0, 0, 0, 3, 1, 0, VPW, 1, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); - - ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); -/* - * Active area - */ - ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0); - ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1); - - ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0); -/* - * Odd field - */ - ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0); - - ADDENTRY (0, 0, 0, 3, 1, 0, VPW+1, 1, 0); - ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); - - ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0); -/* - * Active area - */ - ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0); - ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1); - - ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0); - ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0); - ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0); - - debug ("done\n"); - -#else /* !CONFIG_RRVISION */ - -/* - * Hx Vx Fx Bx VDS INT LCYC LP LST - * - * vertical; blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 22, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 263, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); -/* - * active area (TOP) - */ - if (Y1 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y1, 1, 0); /* 11? */ - ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); - } -/* - * field active area (CENTER) - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 288 - DY, 1, 0); /* 265? */ - ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 8 + X1, 0, 0); - ADDENTRY (3, 0, 0, 3, 0, 0, VIDEO_COLS * 2, 0, 0); - - if (X2 > 0) - ADDENTRY (3, 0, 0, 1, 1, 0, X2, 0, 0); - - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); -/* - * field active area (BOTTOM) - */ - if (Y2 > 0) { - ADDENTRY (0, 0, 0, 0, 1, 0, Y2, 1, 0); /* 12? */ - ADDENTRY (3, 0, 0, 0, 1, 0, 255, 0, 0); - ADDENTRY (3, 0, 0, 3, 1, 0, 1448, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); - } -/* - * field vertical; blanking - */ - ADDENTRY (0, 0, 0, 0, 1, 0, 2, 1, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 263, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 1440, 0, 0); - ADDENTRY (3, 0, 0, 0, 1, 0, 24, 1, 0); -/* - * Create the other field (like this, but whit other field selected, - * one more cycle loop and a last identifier) - */ - video_mode_dupefield (vr, &vr[entry], entry); -#endif /* CONFIG_RRVISION */ - -#endif /* VIDEO_MODE_PAL */ - - /* See what FIFO are we using */ - fifo = GETBIT (immap->im_vid.vid_vsr, VIDEO_VSR_CAS); - - /* Set number of lines and burst (only one frame for now) */ - if (fifo) { - immap->im_vid.vid_vfcr0 = VIDEO_BURST_LEN | - (VIDEO_BURST_LEN << 8) | ((VIDEO_ROWS / 2) << 19); - } else { - immap->im_vid.vid_vfcr1 = VIDEO_BURST_LEN | - (VIDEO_BURST_LEN << 8) | ((VIDEO_ROWS / 2) << 19); - } - - SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_ASEL, !fifo); - -/* - * Wait until changes are applied (not done) - * while (GETBIT(immap->im_vid.vid_vsr, VIDEO_VSR_CAS) == fifo) ; - */ - - /* Return number of VRAM entries */ - return entry * 2; -} - -static void video_encoder_init (void) -{ -#ifdef VIDEO_I2C - int rc; - - /* Initialize the I2C */ - debug ("[VIDEO ENCODER] Initializing I2C bus...\n"); - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - -#ifdef CONFIG_FADS - /* Reset ADV7176 chip */ - debug ("[VIDEO ENCODER] Resetting encoder...\n"); - (*(int *) BCSR4) &= ~(1 << 21); - - /* Wait for 5 ms inside the reset */ - debug ("[VIDEO ENCODER] Waiting for encoder reset...\n"); - udelay (5000); - - /* Take ADV7176 out of reset */ - (*(int *) BCSR4) |= 1 << 21; - - /* Wait for 5 ms after the reset */ - udelay (5000); -#endif /* CONFIG_FADS */ - - /* Send configuration */ -#ifdef DEBUG - { - int i; - - puts ("[VIDEO ENCODER] Configuring the encoder...\n"); - - printf ("Sending %d bytes (@ %08lX) to I2C 0x%X:\n ", - sizeof(video_encoder_data), - (ulong)video_encoder_data, - VIDEO_I2C_ADDR); - for (i=0; iim_vid.vid_vbcb = VIDEO_BG_COL; - - /* Show the background */ - debug ("[VIDEO CTRL] Forcing background...\n"); - SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_BD, 1); - - /* Turn off video controller */ - debug ("[VIDEO CTRL] Turning off video controller...\n"); - SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 0); - -#ifdef CONFIG_FADS - /* Turn on Video Port LED */ - debug ("[VIDEO CTRL] Turning off video port led...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 1); - - /* Disable internal clock */ - debug ("[VIDEO CTRL] Disabling internal clock...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 0); -#endif - - /* Generate and make active a new video mode */ - debug ("[VIDEO CTRL] Generating video mode...\n"); - video_mode_generate (); - - /* Start of frame buffer (even and odd frame, to make it working with */ - /* any selected active set) */ - debug ("[VIDEO CTRL] Setting frame buffer address...\n"); - immap->im_vid.vid_vfaa1 = - immap->im_vid.vid_vfaa0 = (u32) video_fb_address; - immap->im_vid.vid_vfba1 = - immap->im_vid.vid_vfba0 = - (u32) video_fb_address + VIDEO_LINE_LEN; - - /* YUV, Big endian, SHIFT/CLK/CLK input (BEFORE ENABLING 27MHZ EXT CLOCK) */ - debug ("[VIDEO CTRL] Setting pixel mode and clocks...\n"); - immap->im_vid.vid_vccr = 0x2042; - - /* Configure port pins */ - debug ("[VIDEO CTRL] Configuring input/output pins...\n"); - immap->im_ioport.iop_pdpar = 0x1fff; - immap->im_ioport.iop_pddir = 0x0000; - -#ifdef CONFIG_FADS - /* Turn on Video Port Clock - ONLY AFTER SET VCCR TO ENABLE EXTERNAL CLOCK */ - debug ("[VIDEO CTRL] Turning on video clock...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 1); - - /* Turn on Video Port LED */ - debug ("[VIDEO CTRL] Turning on video port led...\n"); - SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 0); -#endif -#ifdef CONFIG_RRVISION - debug ("PC5->Output(1): enable PAL clock"); - immap->im_ioport.iop_pcpar &= ~(0x0400); - immap->im_ioport.iop_pcdir |= 0x0400 ; - immap->im_ioport.iop_pcdat |= 0x0400 ; - debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", - immap->im_ioport.iop_pdpar, - immap->im_ioport.iop_pddir, - immap->im_ioport.iop_pddat); - debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", - immap->im_ioport.iop_pcpar, - immap->im_ioport.iop_pcdir, - immap->im_ioport.iop_pcdat); -#endif /* CONFIG_RRVISION */ - - /* Blanking the screen. */ - debug ("[VIDEO CTRL] Blanking the screen...\n"); - video_fill (VIDEO_BG_COL); - - /* - * Turns on Aggressive Mode. Normally, turning on the caches - * will cause the screen to flicker when the caches try to - * fill. This gives the FIFO's for the Video Controller - * higher priority and prevents flickering because of - * underrun. This may still be an issue when using FLASH, - * since accessing data from Flash is so slow. - */ - debug ("[VIDEO CTRL] Turning on aggressive mode...\n"); - immap->im_siu_conf.sc_sdcr = 0x40; - - /* Turn on video controller */ - debug ("[VIDEO CTRL] Turning on video controller...\n"); - SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 1); - - /* Show the display */ - debug ("[VIDEO CTRL] Enabling the video...\n"); - SETBIT (immap->im_vid.vid_vcmr, VIDEO_VCMR_BD, 0); -} - -/************************************************************************/ -/* ** CONSOLE FUNCTIONS */ -/************************************************************************/ - -static void console_scrollup (void) -{ - /* Copy up rows ignoring the first one */ - memcpyl (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE >> 2); - - /* Clear the last one */ - memsetl (CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, VIDEO_BG_COL); -} - -static inline void console_back (void) -{ - console_col--; - - if (console_col < 0) { - console_col = CONSOLE_COLS - 1; - console_row--; - if (console_row < 0) - console_row = 0; - } - - video_putchar ( console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, ' '); -} - -static inline void console_newline (void) -{ - console_row++; - console_col = 0; - - /* Check if we need to scroll the terminal */ - if (console_row >= CONSOLE_ROWS) { - /* Scroll everything up */ - console_scrollup (); - - /* Decrement row number */ - console_row--; - } -} - -void video_putc (const char c) -{ - if (!video_enable) { - serial_putc (c); - return; - } - - switch (c) { - case 13: /* Simply ignore this */ - break; - - case '\n': /* Next line, please */ - console_newline (); - break; - - case 9: /* Tab (8 chars alignment) */ - console_col |= 0x0008; /* Next 8 chars boundary */ - console_col &= ~0x0007; /* Set this bit to zero */ - - if (console_col >= CONSOLE_COLS) - console_newline (); - break; - - case 8: /* Eat last character */ - console_back (); - break; - - default: /* Add to the console */ - video_putchar ( console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, c); - console_col++; - /* Check if we need to go to next row */ - if (console_col >= CONSOLE_COLS) - console_newline (); - } -} - -void video_puts (const char *s) -{ - int count = strlen (s); - - if (!video_enable) - while (count--) - serial_putc (*s++); - else - while (count--) - video_putc (*s++); -} - -/************************************************************************/ -/* ** CURSOR BLINKING FUNCTIONS */ -/************************************************************************/ - -#ifdef VIDEO_BLINK - -#define BLINK_TIMER_ID 0 -#define BLINK_TIMER_HZ 2 - -static unsigned char blink_enabled = 0; -static timer_t blink_timer; - -static void blink_update (void) -{ - static int blink_row = -1, blink_col = -1, blink_old = 0; - - /* Check if we have a new position to invert */ - if ((console_row != blink_row) || (console_col != blink_col)) { - /* Check if we need to reverse last character */ - if (blink_old) - video_revchar ( blink_col * VIDEO_FONT_WIDTH, - (blink_row -#ifdef CONFIG_VIDEO_LOGO - + VIDEO_LOGO_HEIGHT -#endif - ) * VIDEO_FONT_HEIGHT); - - /* Update values */ - blink_row = console_row; - blink_col = console_col; - blink_old = 0; - } - -/* Reverse this character */ - blink_old = !blink_old; - video_revchar ( console_col * VIDEO_FONT_WIDTH, - (console_row -#ifdef CONFIG_VIDEO_LOGO - + VIDEO_LOGO_HEIGHT -#endif - ) * VIDEO_FONT_HEIGHT); - -} - -/* - * Handler for blinking cursor - */ -static void blink_handler (void *arg) -{ -/* Blink */ - blink_update (); -/* Ack the timer */ - timer_ack (&blink_timer); -} - -int blink_set (int blink) -{ - int ret = blink_enabled; - - if (blink) - timer_enable (&blink_timer); - else - timer_disable (&blink_timer); - - blink_enabled = blink; - - return ret; -} - -static inline void blink_close (void) -{ - timer_close (&blink_timer); -} - -static inline void blink_init (void) -{ - timer_init (&blink_timer, - BLINK_TIMER_ID, BLINK_TIMER_HZ, - blink_handler); -} -#endif - -/************************************************************************/ -/* ** LOGO PLOTTING FUNCTIONS */ -/************************************************************************/ - -#ifdef CONFIG_VIDEO_LOGO -void easylogo_plot (fastimage_t * image, void *screen, int width, int x, - int y) -{ - int skip = width - image->width, xcount, ycount = image->height; - -#ifdef VIDEO_MODE_YUYV - ushort *source = (ushort *) image->data; - ushort *dest = (ushort *) screen + y * width + x; - - while (ycount--) { - xcount = image->width; - while (xcount--) - *dest++ = *source++; - dest += skip; - } -#endif -#ifdef VIDEO_MODE_RGB - unsigned char - *source = (unsigned short *) image->data, - *dest = (unsigned short *) screen + ((y * width) + x) * 3; - - while (ycount--) { - xcount = image->width * 3; - memcpy (dest, source, xcount); - source += xcount; - dest += ycount; - } -#endif -} - -static void *video_logo (void) -{ - u16 *screen = video_fb_address, width = VIDEO_COLS; -#ifdef VIDEO_INFO -# ifndef CONFIG_FADS - DECLARE_GLOBAL_DATA_PTR; - char temp[32]; -# endif - char info[80]; -#endif /* VIDEO_INFO */ - - easylogo_plot (VIDEO_LOGO_ADDR, screen, width, 0, 0); - -#ifdef VIDEO_INFO - sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info); - - sprintf (info, "(C) 2002 DENX Software Engineering"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, - info); - - sprintf (info, " Wolfgang DENK, wd@denx.de"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, - info); -#ifndef CONFIG_FADS /* all normal boards */ - /* leave one blank line */ - - sprintf (info, "MPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash", - strmhz(temp, gd->cpu_clk), - gd->ram_size >> 20, - gd->bd->bi_flashsize >> 20 ); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 4, - info); -#else /* FADS :-( */ - sprintf (info, "MPC823 CPU at 50 MHz on FADS823 board"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, - info); - - sprintf (info, "2MB FLASH - 8MB DRAM - 4MB SRAM"); - video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2, - info); -#endif -#endif - - return video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN; -} -#endif - -/************************************************************************/ -/* ** VIDEO HIGH-LEVEL FUNCTIONS */ -/************************************************************************/ - -static int video_init (void *videobase) -{ - /* Initialize the encoder */ - debug ("[VIDEO] Initializing video encoder...\n"); - video_encoder_init (); - - /* Initialize the video controller */ - debug ("[VIDEO] Initializing video controller at %08x...\n", - (int) videobase); - video_ctrl_init (videobase); - - /* Setting the palette */ - video_setpalette (CONSOLE_COLOR_BLACK, 0, 0, 0); - video_setpalette (CONSOLE_COLOR_RED, 0xFF, 0, 0); - video_setpalette (CONSOLE_COLOR_GREEN, 0, 0xFF, 0); - video_setpalette (CONSOLE_COLOR_YELLOW, 0xFF, 0xFF, 0); - video_setpalette (CONSOLE_COLOR_BLUE, 0, 0, 0xFF); - video_setpalette (CONSOLE_COLOR_MAGENTA, 0xFF, 0, 0xFF); - video_setpalette (CONSOLE_COLOR_CYAN, 0, 0xFF, 0xFF); - video_setpalette (CONSOLE_COLOR_GREY, 0xAA, 0xAA, 0xAA); - video_setpalette (CONSOLE_COLOR_GREY2, 0xF8, 0xF8, 0xF8); - video_setpalette (CONSOLE_COLOR_WHITE, 0xFF, 0xFF, 0xFF); - -#ifndef CFG_WHITE_ON_BLACK - video_setfgcolor (CONSOLE_COLOR_BLACK); - video_setbgcolor (CONSOLE_COLOR_GREY2); -#else - video_setfgcolor (CONSOLE_COLOR_GREY2); - video_setbgcolor (CONSOLE_COLOR_BLACK); -#endif /* CFG_WHITE_ON_BLACK */ - -#ifdef CONFIG_VIDEO_LOGO - /* Paint the logo and retrieve tv base address */ - debug ("[VIDEO] Drawing the logo...\n"); - video_console_address = video_logo (); -#else - video_console_address = video_fb_address; -#endif - -#ifdef VIDEO_BLINK - /* Enable the blinking (under construction) */ - blink_init (); - blink_set (0); /* To Fix! */ -#endif - - /* Initialize the console */ - console_col = 0; - console_row = 0; - video_enable = 1; - -#ifdef VIDEO_MODE_PAL -# define VIDEO_MODE_TMP1 "PAL" -#endif -#ifdef VIDEO_MODE_NTSC -# define VIDEO_MODE_TMP1 "NTSC" -#endif -#ifdef VIDEO_MODE_YUYV -# define VIDEO_MODE_TMP2 "YCbYCr" -#endif -#ifdef VIDEO_MODE_RGB -# define VIDEO_MODE_TMP2 "RGB" -#endif - debug ( VIDEO_MODE_TMP1 - " %dx%dx%d (" VIDEO_MODE_TMP2 ") on %s - console %dx%d\n", - VIDEO_COLS, VIDEO_ROWS, VIDEO_MODE_BPP, - VIDEO_ENCODER_NAME, CONSOLE_COLS, CONSOLE_ROWS); - return 0; -} - -int drv_video_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int error, devices = 1; - - device_t videodev; - - video_init ((void *)(gd->fb_base)); /* Video initialization */ - -/* Device initialization */ - - memset (&videodev, 0, sizeof (videodev)); - - strcpy (videodev.name, "video"); - videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ - videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */ - videodev.putc = video_putc; /* 'putc' function */ - videodev.puts = video_puts; /* 'puts' function */ - - error = device_register (&videodev); - - return (error == 0) ? devices : error; -} - -/************************************************************************/ -/* ** ROM capable initialization part - needed to reserve FB memory */ -/************************************************************************/ - -/* - * This is called early in the system initialization to grab memory - * for the video controller. - * Returns new address for monitor, after reserving video buffer memory - * - * Note that this is running from ROM, so no write access to global data. - */ -ulong video_setmem (ulong addr) -{ - /* Allocate pages for the frame buffer. */ - addr -= VIDEO_SIZE; - - debug ("Reserving %dk for Video Framebuffer at: %08lx\n", - VIDEO_SIZE>>10, addr); - - return (addr); -} - -#endif diff --git a/cpu/mpc8xx/wlkbd.c b/cpu/mpc8xx/wlkbd.c deleted file mode 100644 index 13009e2..0000000 --- a/cpu/mpc8xx/wlkbd.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifdef CONFIG_WL_4PPM_KEYBOARD - -/* WIP: Wireless keyboard on SMC - */ -int drv_wlkbd_init (void) -{ - return 0 ; -} - -#endif /* CONFIG_WL_4PPM_KEYBOARD */ diff --git a/cpu/nios/Makefile b/cpu/nios/Makefile deleted file mode 100644 index 7855325..0000000 --- a/cpu/nios/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -AOBJS = traps.o -OBJS = cpu.o interrupts.o serial.o asmi.o spi.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) $(AOBJS) - $(AR) crv $@ $(OBJS) $(AOBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/nios/asmi.c b/cpu/nios/asmi.c deleted file mode 100644 index ce2863e..0000000 --- a/cpu/nios/asmi.c +++ /dev/null @@ -1,695 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if defined(CONFIG_NIOS_ASMI) -#include -#include - -#if !defined(CFG_NIOS_ASMIBASE) -#error "*** CFG_NIOS_ASMIBASE not defined ***" -#endif - -/*-----------------------------------------------------------------------*/ -#define SHORT_HELP\ - "asmi - read/write Cyclone ASMI configuration device.\n" - -#define LONG_HELP\ - "\n"\ - "asmi erase start [end]\n"\ - " - erase sector start or sectors start through end.\n"\ - "asmi info\n"\ - " - display ASMI device information.\n"\ - "asmi protect on | off\n"\ - " - turn device protection on or off.\n"\ - "asmi read addr offset count\n"\ - " - read count bytes from offset to addr.\n"\ - "asmi write addr offset count\n"\ - " - write count bytes to offset from addr.\n"\ - "asmi verify addr offset count\n"\ - " - verify count bytes at offset from addr.\n" - - -/*-----------------------------------------------------------------------*/ -/* Operation codes for serial configuration devices - */ -#define ASMI_WRITE_ENA 0x06 /* Write enable */ -#define ASMI_WRITE_DIS 0x04 /* Write disable */ -#define ASMI_READ_STAT 0x05 /* Read status */ -#define ASMI_READ_BYTES 0x03 /* Read bytes */ -#define ASMI_READ_ID 0xab /* Read silicon id */ -#define ASMI_WRITE_STAT 0x01 /* Write status */ -#define ASMI_WRITE_BYTES 0x02 /* Write bytes */ -#define ASMI_ERASE_BULK 0xc7 /* Erase entire device */ -#define ASMI_ERASE_SECT 0xd8 /* Erase sector */ - -/* Device status register bits - */ -#define ASMI_STATUS_WIP (1<<0) /* Write in progress */ -#define ASMI_STATUS_WEL (1<<1) /* Write enable latch */ - -static nios_asmi_t *asmi = (nios_asmi_t *)CFG_NIOS_ASMIBASE; - -/*********************************************************************** - * Device access - ***********************************************************************/ -static void asmi_cs (int assert) -{ - if (assert) { - asmi->control |= NIOS_ASMI_SSO; - } else { - /* Let all bits shift out */ - while ((asmi->status & NIOS_ASMI_TMT) == 0) - ; - asmi->control &= ~NIOS_ASMI_SSO; - } -} - -static void asmi_tx (unsigned char c) -{ - while ((asmi->status & NIOS_ASMI_TRDY) == 0) - ; - asmi->txdata = c; -} - -static int asmi_rx (void) -{ - while ((asmi->status & NIOS_ASMI_RRDY) == 0) - ; - return (asmi->rxdata); -} - -static unsigned char bitrev[] = { - 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, - 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f -}; - -static unsigned char asmi_bitrev( unsigned char c ) -{ - unsigned char val; - - val = bitrev[c>>4]; - val |= bitrev[c & 0x0f]<<4; - return (val); -} - -static void asmi_rcv (unsigned char *dst, int len) -{ - while (len--) { - asmi_tx (0); - *dst++ = asmi_rx (); - } -} - -static void asmi_rrcv (unsigned char *dst, int len) -{ - while (len--) { - asmi_tx (0); - *dst++ = asmi_bitrev (asmi_rx ()); - } -} - -static void asmi_snd (unsigned char *src, int len) -{ - while (len--) { - asmi_tx (*src++); - asmi_rx (); - } -} - -static void asmi_rsnd (unsigned char *src, int len) -{ - while (len--) { - asmi_tx (asmi_bitrev (*src++)); - asmi_rx (); - } -} - -static void asmi_wr_enable (void) -{ - asmi_cs (1); - asmi_tx (ASMI_WRITE_ENA); - asmi_rx (); - asmi_cs (0); -} - -static unsigned char asmi_status_rd (void) -{ - unsigned char status; - - asmi_cs (1); - asmi_tx (ASMI_READ_STAT); - asmi_rx (); - asmi_tx (0); - status = asmi_rx (); - asmi_cs (0); - return (status); -} - -static void asmi_status_wr (unsigned char status) -{ - asmi_wr_enable (); - asmi_cs (1); - asmi_tx (ASMI_WRITE_STAT); - asmi_rx (); - asmi_tx (status); - asmi_rx (); - asmi_cs (0); - return; -} - -/*********************************************************************** - * Device information - ***********************************************************************/ -typedef struct asmi_devinfo_t { - const char *name; /* Device name */ - unsigned char id; /* Device silicon id */ - unsigned char size; /* Total size log2(bytes)*/ - unsigned char num_sects; /* Number of sectors */ - unsigned char sz_sect; /* Sector size log2(bytes) */ - unsigned char sz_page; /* Page size log2(bytes) */ - unsigned char prot_mask; /* Protection mask */ -}asmi_devinfo_t; - -static struct asmi_devinfo_t devinfo[] = { - { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, - { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, - { 0, 0, 0, 0, 0, 0 } -}; - -static asmi_devinfo_t *asmi_dev_find (void) -{ - unsigned char buf[4]; - unsigned char id; - int i; - struct asmi_devinfo_t *dev = NULL; - - /* Read silicon id requires 3 "dummy bytes" before it's put - * on the wire. - */ - buf[0] = ASMI_READ_ID; - buf[1] = 0; - buf[2] = 0; - buf[3] = 0; - - asmi_cs (1); - asmi_snd (buf,4); - asmi_rcv (buf,1); - asmi_cs (0); - id = buf[0]; - - /* Find the info struct */ - i = 0; - while (devinfo[i].name) { - if (id == devinfo[i].id) { - dev = &devinfo[i]; - break; - } - i++; - } - - return (dev); -} - -/*********************************************************************** - * Misc Utilities - ***********************************************************************/ -static unsigned asmi_cfgsz (void) -{ - unsigned sz = 0; - unsigned char buf[128]; - unsigned char *p; - - /* Read in the first 128 bytes of the device */ - buf[0] = ASMI_READ_BYTES; - buf[1] = 0; - buf[2] = 0; - buf[3] = 0; - - asmi_cs (1); - asmi_snd (buf,4); - asmi_rrcv (buf, sizeof(buf)); - asmi_cs (0); - - /* Search for the starting 0x6a which is followed by the - * 4-byte 'register' and 4-byte bit-count. - */ - p = buf; - while (p < buf + sizeof(buf)-8) { - if ( *p == 0x6a ) { - /* Point to bit count and extract */ - p += 5; - sz = *p++; - sz |= *p++ << 8; - sz |= *p++ << 16; - sz |= *p++ << 24; - /* Convert to byte count */ - sz += 7; - sz >>= 3; - } else if (*p == 0xff) { - /* 0xff is ok ... just skip */ - p++; - continue; - } else { - /* Not 0xff or 0x6a ... something's not - * right ... report 'unknown' (sz=0). - */ - break; - } - } - return (sz); -} - -static int asmi_erase (unsigned start, unsigned end) -{ - unsigned off, sectsz; - unsigned char buf[4]; - struct asmi_devinfo_t *dev = asmi_dev_find (); - - if (!dev || (start>end)) - return (-1); - - /* Erase the requested sectors. An address is required - * that lies within the requested sector -- we'll just - * use the first address in the sector. - */ - printf ("asmi erasing sector %d ", start); - if (start != end) - printf ("to %d ", end); - sectsz = (1 << dev->sz_sect); - while (start <= end) { - off = start * sectsz; - start++; - - buf[0] = ASMI_ERASE_SECT; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - asmi_wr_enable (); - asmi_cs (1); - asmi_snd (buf,4); - asmi_cs (0); - - printf ("."); /* Some user feedback */ - - /* Wait for erase to complete */ - while (asmi_status_rd() & ASMI_STATUS_WIP) - ; - } - printf (" done.\n"); - return (0); -} - -static int asmi_read (ulong addr, ulong off, ulong cnt) -{ - unsigned char buf[4]; - - buf[0] = ASMI_READ_BYTES; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - asmi_cs (1); - asmi_snd (buf,4); - asmi_rrcv ((unsigned char *)addr, cnt); - asmi_cs (0); - - return (0); -} - -static -int asmi_write (ulong addr, ulong off, ulong cnt) -{ - ulong wrcnt; - unsigned pgsz; - unsigned char buf[4]; - struct asmi_devinfo_t *dev = asmi_dev_find (); - - if (!dev) - return (-1); - - pgsz = (1<sz_page); - while (cnt) { - if (off % pgsz) - wrcnt = pgsz - (off % pgsz); - else - wrcnt = pgsz; - wrcnt = (wrcnt > cnt) ? cnt : wrcnt; - - buf[0] = ASMI_WRITE_BYTES; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - asmi_wr_enable (); - asmi_cs (1); - asmi_snd (buf,4); - asmi_rsnd ((unsigned char *)addr, wrcnt); - asmi_cs (0); - - /* Wait for write to complete */ - while (asmi_status_rd() & ASMI_STATUS_WIP) - ; - - cnt -= wrcnt; - off += wrcnt; - addr += wrcnt; - } - - return (0); -} - -static -int asmi_verify (ulong addr, ulong off, ulong cnt, ulong *err) -{ - ulong rdcnt; - unsigned char buf[256]; - unsigned char *start,*end; - int i; - - start = end = (unsigned char *)addr; - while (cnt) { - rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt; - asmi_read ((ulong)buf, off, rdcnt); - for (i=0; isz_sect); - off = sectsz * sect; - end = off + sectsz; - - while (off < end) { - asmi_read ((ulong)buf, off, sizeof(buf)); - for (i=0; i < sizeof(buf); i++) { - if (buf[i] != 0xff) { - *offset = off + i; - return (0); - } - } - off += sizeof(buf); - } - return (1); -} - - -/*********************************************************************** - * Commands - ***********************************************************************/ -static -void do_asmi_info (struct asmi_devinfo_t *dev, int argc, char *argv[]) -{ - int i; - unsigned char stat; - unsigned tmp; - int erased; - - /* Basic device info */ - printf ("%s: %d kbytes (%d sectors x %d kbytes," - " %d bytes/page)\n", - dev->name, 1 << (dev->size-10), - dev->num_sects, 1 << (dev->sz_sect-10), - 1 << dev->sz_page ); - - /* Status -- for now protection is all-or-nothing */ - stat = asmi_status_rd(); - printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n", - stat, - (stat & ASMI_STATUS_WIP) ? 1 : 0, - (stat & ASMI_STATUS_WEL) ? 1 : 0, - (stat & dev->prot_mask) ? "on" : "off" ); - - /* Configuration */ - tmp = asmi_cfgsz (); - if (tmp) { - printf ("config: 0x%06x (%d) bytes\n", tmp, tmp ); - } else { - printf ("config: unknown\n" ); - } - - /* Sector info */ - for (i=0; inum_sects; i++) { - erased = asmi_sect_erased (i, &tmp, dev); - printf (" %d: %06x ", - i, i*(1<sz_sect) ); - if (erased) - printf ("erased\n"); - else - printf ("data @ 0x%06x\n", tmp); - } - - return; -} - -static -void do_asmi_erase (struct asmi_devinfo_t *dev, int argc, char *argv[]) -{ - unsigned start,end; - - if ((argc < 3) || (argc > 4)) { - printf ("USAGE: asmi erase sect [end]\n"); - return; - } - if ((asmi_status_rd() & dev->prot_mask) != 0) { - printf ( "asmi: device protected.\n"); - return; - } - - start = simple_strtoul (argv[2], NULL, 10); - if (argc > 3) - end = simple_strtoul (argv[3], NULL, 10); - else - end = start; - if ((start >= dev->num_sects) || (start > end)) { - printf ("asmi: invalid sector range: [%d:%d]\n", - start, end ); - return; - } - - asmi_erase (start, end); - - return; -} - -static -void do_asmi_protect (struct asmi_devinfo_t *dev, int argc, char *argv[]) -{ - unsigned char stat; - - /* For now protection is all-or-nothing to keep things - * simple. The protection bits don't map in a linear - * fashion ... and we would rather protect the bottom - * of the device since it contains the config data and - * leave the top unprotected for app use. But unfortunately - * protection works from top-to-bottom so it does - * really help very much from a software app point-of-view. - */ - if (argc < 3) { - printf ("USAGE: asmi protect on | off\n"); - return; - } - if (!dev) - return; - - /* Protection on/off is just a matter of setting/clearing - * all protection bits in the status register. - */ - stat = asmi_status_rd (); - if (strcmp ("on", argv[2]) == 0) { - stat |= dev->prot_mask; - } else if (strcmp ("off", argv[2]) == 0 ) { - stat &= ~dev->prot_mask; - } else { - printf ("asmi: unknown protection: %s\n", argv[2]); - return; - } - asmi_status_wr (stat); - return; -} - -static -void do_asmi_read (struct asmi_devinfo_t *dev, int argc, char *argv[]) -{ - ulong addr,off,cnt; - ulong sz; - - if (argc < 5) { - printf ("USAGE: asmi read addr offset count\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("asmi: read %08lx <- %06lx (0x%lx bytes)\n", - addr, off, cnt); - asmi_read (addr, off, cnt); - - return; -} - -static -void do_asmi_write (struct asmi_devinfo_t *dev, int argc, char *argv[]) -{ - ulong addr,off,cnt; - ulong sz; - ulong err; - - if (argc < 5) { - printf ("USAGE: asmi write addr offset count\n"); - return; - } - if ((asmi_status_rd() & dev->prot_mask) != 0) { - printf ( "asmi: device protected.\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("asmi: write %08lx -> %06lx (0x%lx bytes)\n", - addr, off, cnt); - asmi_write (addr, off, cnt); - if (asmi_verify (addr, off, cnt, &err) != 0) - printf ("asmi: write error at offset %06lx\n", err); - - return; -} - -static -void do_asmi_verify (struct asmi_devinfo_t *dev, int argc, char *argv[]) -{ - ulong addr,off,cnt; - ulong sz; - ulong err; - - if (argc < 5) { - printf ("USAGE: asmi verify addr offset count\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("asmi: verify %08lx -> %06lx (0x%lx bytes)\n", - addr, off, cnt); - if (asmi_verify (addr, off, cnt, &err) != 0) - printf ("asmi: verify error at offset %06lx\n", err); - - return; -} - -/*-----------------------------------------------------------------------*/ -int do_asmi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int len; - struct asmi_devinfo_t *dev = asmi_dev_find (); - - if (argc < 2) { - printf ("Usage:%s", LONG_HELP); - return (0); - } - - if (!dev) { - printf ("asmi: device not found.\n"); - return (0); - } - - len = strlen (argv[1]); - if (strncmp ("info", argv[1], len) == 0) { - do_asmi_info ( dev, argc, argv); - } else if (strncmp ("erase", argv[1], len) == 0) { - do_asmi_erase (dev, argc, argv); - } else if (strncmp ("protect", argv[1], len) == 0) { - do_asmi_protect (dev, argc, argv); - } else if (strncmp ("read", argv[1], len) == 0) { - do_asmi_read (dev, argc, argv); - } else if (strncmp ("write", argv[1], len) == 0) { - do_asmi_write (dev, argc, argv); - } else if (strncmp ("verify", argv[1], len) == 0) { - do_asmi_verify (dev, argc, argv); - } else { - printf ("asmi: unknown operation: %s\n", argv[1]); - } - - return (0); -} - -/*-----------------------------------------------------------------------*/ - - -U_BOOT_CMD( asmi, 5, 0, do_asmi, SHORT_HELP, LONG_HELP ); - -#endif /* CONFIG_NIOS_ASMI */ diff --git a/cpu/nios/config.mk b/cpu/nios/config.mk deleted file mode 100644 index f228d72..0000000 --- a/cpu/nios/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += diff --git a/cpu/nios/cpu.c b/cpu/nios/cpu.c deleted file mode 100644 index d2bb2c0..0000000 --- a/cpu/nios/cpu.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -int checkcpu (void) -{ - unsigned val; - unsigned rev_major; - unsigned rev_minor; - short nregs, hi_limit, lo_limit; - - /* Get cpu version info */ - val = rdctl (CTL_CPU_ID); - printf ("CPU: "); - printf ("%s", (val & 0x00008000) ? "Nios-16 " : "Nios-32 "); - rev_major = (val>>12) & 0x07; - rev_minor = (val>>4) & 0x0ff; - printf ("Rev. %d.%d (0x%04x)", rev_major, rev_minor, - val & 0xffff); - if (rev_major == 0x08) - printf (" [OpenCore (R) Plus]"); - printf ("\n"); - - /* Check register file */ - val = rdctl (CTL_WVALID); - lo_limit = val & 0x01f; - hi_limit = (val>>5) & 0x1f; - nregs = (hi_limit + 2) * 16; - printf ("Reg file size: %d LO_LIMIT/HI_LIMIT: %d/%d\n", - nregs, lo_limit, hi_limit); - - return (0); -} - - -int do_reset (void) -{ - /* trap 0 does the trick ... at least with the OCI debug - * present -- haven't tested without it yet (stm). - */ - disable_interrupts (); - ipri (1); - asm volatile ("trap 0\n"); - - /* No return ;-) */ - - return(0); -} - - -#if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) -{ -} -#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/nios/interrupts.c b/cpu/nios/interrupts.c deleted file mode 100644 index 48fc81e..0000000 --- a/cpu/nios/interrupts.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif - -/****************************************************************************/ - -struct irq_action { - interrupt_handler_t *handler; - void *arg; - int count; -}; - -static struct irq_action irq_vecs[64]; - -/*************************************************************************/ -volatile ulong timestamp = 0; - -void reset_timer (void) -{ - timestamp = 0; -} - -ulong get_timer (ulong base) -{ - WATCHDOG_RESET (); - return (timestamp - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} - - -/* The board must handle this interrupt if a timer is not - * provided. - */ -#if defined(CFG_NIOS_TMRBASE) -void timer_interrupt (struct pt_regs *regs) -{ - /* Interrupt is cleared by writing anything to the - * status register. - */ - nios_timer_t *tmr = (nios_timer_t *)CFG_NIOS_TMRBASE; - tmr->status = 0; - timestamp += CFG_NIOS_TMRMS; -#ifdef CONFIG_STATUS_LED - status_led_tick(timestamp); -#endif -} -#endif - -/*************************************************************************/ -int disable_interrupts (void) -{ - int val = 0; - - /* Writing anything to CLR_IE disables interrupts */ - val = rdctl (CTL_STATUS); - wrctl (CTL_CLR_IE, 0); - return (val & STATUS_IE); -} - -void enable_interrupts( void ) -{ - /* Writing anything SET_IE enables interrupts */ - wrctl (CTL_SET_IE, 0); -} - -void external_interrupt (struct pt_regs *regs) -{ - unsigned vec; - - vec = (regs->status & STATUS_IPRI) >> 9; /* ipri */ - - irq_vecs[vec].count++; - if (irq_vecs[vec].handler != NULL) { - (*irq_vecs[vec].handler)(irq_vecs[vec].arg); - } else { - /* A sad side-effect of masking a bogus interrupt is - * that lower priority interrupts will also be disabled. - * This is probably not what we want ... so hang insted. - */ - printf ("Unhandled interrupt: 0x%x\n", vec); - disable_interrupts (); - hang (); - } -} - -/*************************************************************************/ -int interrupt_init (void) -{ - int vec; - -#if defined(CFG_NIOS_TMRBASE) - nios_timer_t *tmr = (nios_timer_t *)CFG_NIOS_TMRBASE; - - tmr->control &= ~NIOS_TIMER_ITO; - tmr->control |= NIOS_TIMER_STOP; -#if defined(CFG_NIOS_TMRCNT) - tmr->periodl = CFG_NIOS_TMRCNT & 0xffff; - tmr->periodh = (CFG_NIOS_TMRCNT >> 16) & 0xffff; -#endif -#endif - - for (vec=0; vec<64; vec++ ) { - irq_vecs[vec].handler = NULL; - irq_vecs[vec].arg = NULL; - irq_vecs[vec].count = 0; - } - - /* Need timus interruptus -- start the lopri timer */ -#if defined(CFG_NIOS_TMRBASE) - tmr->control |= ( NIOS_TIMER_ITO | - NIOS_TIMER_CONT | - NIOS_TIMER_START ); - ipri (CFG_NIOS_TMRIRQ + 1); -#endif - enable_interrupts (); - return (0); -} - -void irq_install_handler (int vec, interrupt_handler_t *handler, void *arg) -{ - struct irq_action *irqa = irq_vecs; - int i = vec; - int flag; - - if (irqa[i].handler != NULL) { - printf ("Interrupt vector %d: handler 0x%x " - "replacing 0x%x\n", - vec, (uint)handler, (uint)irqa[i].handler); - } - - flag = disable_interrupts (); - irqa[i].handler = handler; - irqa[i].arg = arg; - if (flag ) - enable_interrupts (); -} - -/*************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) -int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int vec; - - printf ("\nInterrupt-Information:\n"); - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec<64; vec++) { - if (irq_vecs[vec].handler != NULL) { - printf ("%02d %08lx %08lx %d\n", - vec, - (ulong)irq_vecs[vec].handler<<1, - (ulong)irq_vecs[vec].arg, - irq_vecs[vec].count); - } - } - - return (0); -} -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/nios/serial.c b/cpu/nios/serial.c deleted file mode 100644 index 4bdda25..0000000 --- a/cpu/nios/serial.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include - -/*------------------------------------------------------------------ - * JTAG acts as the serial port - *-----------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) - -static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE; - -void serial_setbrg( void ){ return; } -int serial_init( void ) { return(0);} - -void serial_putc (char c) -{ - while ((jtag->txcntl & NIOS_JTAG_TRDY) != 0) - WATCHDOG_RESET (); - jtag->txcntl = NIOS_JTAG_TRDY | (unsigned char)c; -} - -void serial_puts (const char *s) -{ - while (*s != 0) - serial_putc (*s++); -} - -int serial_tstc (void) -{ - return (jtag->rxcntl & NIOS_JTAG_RRDY); -} - -int serial_getc (void) -{ - int c; - while (serial_tstc() == 0) - WATCHDOG_RESET (); - c = jtag->rxcntl & 0x0ff; - jtag->rxcntl = 0; - return (c); -} - -/*------------------------------------------------------------------ - * UART the serial port - *-----------------------------------------------------------------*/ -#else - -static nios_uart_t *uart = (nios_uart_t *)CFG_NIOS_CONSOLE; - -#if defined(CFG_NIOS_FIXEDBAUD) - -/* Everything's already setup for fixed-baud PTF - * assignment - */ -void serial_setbrg (void){ return; } -int serial_init (void) { return (0);} - -#else - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned div; - - div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; - uart->divisor = div; - return; -} - -int serial_init (void) -{ - serial_setbrg (); - return (0); -} - -#endif /* CFG_NIOS_FIXEDBAUD */ - - -/*----------------------------------------------------------------------- - * UART CONSOLE - *---------------------------------------------------------------------*/ -void serial_putc (char c) -{ - if (c == '\n') - serial_putc ('\r'); - while ((uart->status & NIOS_UART_TRDY) == 0) - WATCHDOG_RESET (); - uart->txdata = (unsigned char)c; -} - -void serial_puts (const char *s) -{ - while (*s != 0) { - serial_putc (*s++); - } -} - -int serial_tstc (void) -{ - return (uart->status & NIOS_UART_RRDY); -} - -int serial_getc (void) -{ - while (serial_tstc () == 0) - WATCHDOG_RESET (); - return( uart->rxdata & 0x00ff ); -} - -#endif /* CONFIG_JTAG_CONSOLE */ diff --git a/cpu/nios/spi.c b/cpu/nios/spi.c deleted file mode 100644 index f37146b..0000000 --- a/cpu/nios/spi.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_NIOS_SPI) -#include -#include - -#if !defined(CFG_NIOS_SPIBASE) -#error "*** CFG_NIOS_SPIBASE not defined ***" -#endif - -#if !defined(CFG_NIOS_SPIBITS) -#error "*** CFG_NIOS_SPIBITS not defined ***" -#endif - -#if (CFG_NIOS_SPIBITS != 8) && (CFG_NIOS_SPIBITS != 16) -#error "*** CFG_NIOS_SPIBITS should be either 8 or 16 ***" -#endif - -static nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; - -/* Warning: - * You cannot enable DEBUG for early system initalization, i. e. when - * this driver is used to read environment parameters like "baudrate" - * from EEPROM which are used to initialize the serial port which is - * needed to print the debug messages... - */ -#undef DEBUG - -#ifdef DEBUG - -#define DPRINT(a) printf a; -/* ----------------------------------------------- - * Helper functions to peek into tx and rx buffers - * ----------------------------------------------- */ -static const char * const hex_digit = "0123456789ABCDEF"; - -static char quickhex (int i) -{ - return hex_digit[i]; -} - -static void memdump (void *pv, int num) -{ - int i; - unsigned char *pc = (unsigned char *) pv; - - for (i = 0; i < num; i++) - printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); - printf ("\t"); - for (i = 0; i < num; i++) - printf ("%c", isprint (pc[i]) ? pc[i] : '.'); - printf ("\n"); -} -#else /* !DEBUG */ - -#define DPRINT(a) -#define memdump(p,n) - -#endif /* DEBUG */ - - -/* - * SPI transfer: - * - * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf - * for more informations. - */ -int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) -{ - int j; - - DPRINT(("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", - (int)chipsel, *(uint *)dout, *(uint *)din, bitlen)); - - memdump((void*)dout, (bitlen + 7) / 8); - - if(chipsel != NULL) { - chipsel(1); /* select the target chip */ - } - - if (bitlen > CFG_NIOS_SPIBITS) { /* leave chip select active */ - spi->control |= NIOS_SPI_SSO; - } - - for ( j = 0; /* count each byte in */ - j < ((bitlen + 7) / 8); /* dout[] and din[] */ - -#if (CFG_NIOS_SPIBITS == 8) - j++) { - - while ((spi->status & NIOS_SPI_TRDY) == 0) - ; - spi->txdata = (unsigned)(dout[j]); - - while ((spi->status & NIOS_SPI_RRDY) == 0) - ; - din[j] = (unsigned char)(spi->rxdata & 0xff); - -#elif (CFG_NIOS_SPIBITS == 16) - j++, j++) { - - while ((spi->status & NIOS_SPI_TRDY) == 0) - ; - if ((j+1) < ((bitlen + 7) / 8)) - spi->txdata = (unsigned)((dout[j] << 8) | dout[j+1]); - else - spi->txdata = (unsigned)(dout[j] << 8); - - while ((spi->status & NIOS_SPI_RRDY) == 0) - ; - din[j] = (unsigned char)((spi->rxdata >> 8) & 0xff); - if ((j+1) < ((bitlen + 7) / 8)) - din[j+1] = (unsigned char)(spi->rxdata & 0xff); - -#else -#error "*** unsupported value of CFG_NIOS_SPIBITS ***" -#endif - - } - - if (bitlen > CFG_NIOS_SPIBITS) { - spi->control &= ~NIOS_SPI_SSO; - } - - if(chipsel != NULL) { - chipsel(0); /* deselect the target chip */ - } - - memdump((void*)din, (bitlen + 7) / 8); - - return 0; -} - -#endif /* CONFIG_NIOS_SPI */ diff --git a/cpu/nios/start.S b/cpu/nios/start.S deleted file mode 100644 index cb1af3c..0000000 --- a/cpu/nios/start.S +++ /dev/null @@ -1,237 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -#if !defined(CONFIG_IDENT_STRING) -#define CONFIG_IDENT_STRING "" -#endif - -#define STATUS_INIT 0x8600 /* IE=1, IPRI=2 */ - -/************************************************************************* - * RESTART - ************************************************************************/ - - .text - .global _start - -_start: - bsr 0f - nop - .long _start - - /* GERMS -- The "standard-32" configuration GERMS monitor looks - * for the string "Nios" at flash_base + 0xc (actually it only - * tests for 'N', 'i'). You can leave support for this in place - * as it's only a few words. - */ - . = _start + 0x000c - .string "Nios" - - .align 4 -0: - /* - * Early setup -- set cwp = HI_LIMIT, IPRI = 2, IE = 1 to - * enable underflow exceptions. Disable cache. - * NOTE: %o7 has return addr -- save in %g7 use later. - */ - mov %g7, %o7 - - pfx 2 /* WVALID */ - rdctl %g0 - lsri %g0, 1 - pfx %hi(STATUS_INIT) - or %g0, %lo(STATUS_INIT) - wrctl %g0 /* update status */ - nop - - /* - * STACK - */ - pfx %hi(CFG_INIT_SP) - movi %sp, %lo(CFG_INIT_SP) - pfx %xhi(CFG_INIT_SP) - movhi %sp, %xlo(CFG_INIT_SP) - mov %fp, %sp - - pfx %hi(4*16) - subi %sp, %lo(4*16) /* Space for reg window mgmt */ - - /* - * RELOCATE -- %g7 has return addr from bsr at _start. - */ - pfx %hi(__u_boot_cmd_end) - movi %g5, %lo(__u_boot_cmd_end) - pfx %xhi(__u_boot_cmd_end) - movhi %g5, %xlo(__u_boot_cmd_end) /* %g5 <- end address */ - - lsli %g7, 1 /* mem = retaddr << 1 */ - mov %g6, %g7 - subi %g6, 4 /* %g6 <- src addr */ - ld %g7, [%g7] /* %g7 <- dst addr */ - - /* No need to move text sections if we're already located - * at the proper address. - */ - cmp %g7, %g6 - ifs cc_z - br reloc - nop /* delay slot */ - -1: cmp %g7, %g5 - skps cc_nz - br 2f - nop /* delay slot */ - - ld %g0, [%g6] - addi %g6, 4 /* src++ */ - st [%g7], %g0 - addi %g7, 4 /* dst++ */ - br 1b - nop /* delay slot */ -2: - - /* - * Jump to relocation address - */ - pfx %hi(reloc@h) - movi %g0, %lo(reloc@h) - pfx %xhi(reloc@h) - movhi %g0, %xlo(reloc@h) - jmp %g0 - nop /* delay slot */ -reloc: - - /* - * CLEAR BSS - */ - pfx %hi(__bss_end) - movi %g5, %lo(__bss_end) - pfx %xhi(__bss_end) - movhi %g5, %xlo(__bss_end) /* %g5 <- end address */ - pfx %hi(__bss_start) - movi %g7, %lo(__bss_start) - pfx %xhi(__bss_start) - movhi %g7, %xlo(__bss_start) /* %g7 <- end address */ - - movi %g0, 0 -3: cmp %g7, %g5 - skps cc_nz - br 4f - nop /* delay slot */ - - st [%g7], %g0 - addi %g7, 4 /* (delay slot) dst++ */ - br 3b - nop /* delay slot */ -4: - - /* - * INIT VECTOR TABLE - */ - pfx %hi(CFG_VECT_BASE) - movi %g0, %lo(CFG_VECT_BASE) - pfx %xhi(CFG_VECT_BASE) - movhi %g0, %xlo(CFG_VECT_BASE) /* dst */ - mov %l0, %g0 - - pfx %hi(_vectors) - movi %g1, %lo(_vectors) - pfx %xhi(_vectors) - movhi %g1, %xlo(_vectors) /* src */ - bgen %g2, 6 /* cnt = 64 */ - - ldp %g3, [%l0, 3] /* bkpt vector */ - ldp %g4, [%l0, 4] /* single step vector */ - -5: ld %g7, [%g1] - addi %g1, 4 /* src++ */ - st [%g0], %g7 - addi %g0, 4 /* dst++ */ - - subi %g2, 1 /* cnt-- */ - ifrnz %g2 - br 5b - nop /* delay slot */ - -#if defined(CONFIG_ROM_STUBS) - /* Restore the breakpoint and single step exception - * vectors to their original values. - */ - stp [%l0,3], %g3 /* breakpoint */ - stp [%l0,4], %g4 /* single step */ -#endif - - /* For debug startup convenience ... software breakpoints - * set prior to this point may not succeed ;-) - */ - .global __start -__start: - - /* - * Call board_init -- never returns - */ - pfx %hi(board_init@h) - movi %g1, %lo(board_init@h) - pfx %xhi(board_init@h) - movhi %g1, %xlo(board_init@h) - call %g1 - nop /* Delaly slot */ - /* NEVER RETURNS */ - -/* - * dly_clks -- Nios doesn't have a time/clk reference for simple - * delay loops, so we do our best by counting instruction cycles. - * A control register that counts system clock cycles would be - * a handy feature -- hint for Altera ;-) - */ - .globl dly_clks - /* Each loop is 4 instructions as delay slot is always - * executed. Each instruction is approximately 4 clocks - * (according to some lame info from Altera). So ... - * ... each loop is about 16 clocks. - */ - -dly_clks: - lsri %o0, 4 /* cnt/16 */ - -8: skprnz %o0 - br 9f - subi %o0, 1 /* cnt--, Delay slot */ - br 8b - nop - -9: lret - nop /* Delay slot */ - - - .data - .globl version_string - -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" diff --git a/cpu/nios/traps.S b/cpu/nios/traps.S deleted file mode 100644 index bc4d3f6..0000000 --- a/cpu/nios/traps.S +++ /dev/null @@ -1,582 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/************************************************************************* - * Register window underflow - * - * The register window underflow exception occurs whenever the lowest - * valid register window is in use (CWP=LO_LIMIT) and a save instruction - * is issued. The save moves CWP below LO_LIMIT, %sp is set as normal, - * then the exception is generated prior to executing the instruction - * after the save. - ************************************************************************/ - .text - .global _cwp_lolimit - .align 4 - -_cwp_lolimit: - - /* Sixteen words are always allocated by the compiler in every - * procedure's stack frame, always starting at %sp, for saving - * 'in' and 'local' registers on a window overflow. - * - * Save the 'global' and 'in' regs on stack. They are restored - * at cwp = HI_LIMIT. The 'local' regs aren't in-use at this point. - */ - sts [%sp,0], %g0 /* Save 'global' regs*/ - sts [%sp,1], %g1 - sts [%sp,2], %g2 - sts [%sp,3], %g3 - sts [%sp,4], %g4 - sts [%sp,5], %g5 - sts [%sp,6], %g6 - sts [%sp,7], %g7 - - sts [%sp,8], %i0 /* Save 'in' regs */ - sts [%sp,9], %i1 - sts [%sp,10], %i2 - sts [%sp,11], %i3 - sts [%sp,12], %i4 - sts [%sp,13], %i5 - sts [%sp,14], %i6 - sts [%sp,15], %i7 - - /* Save current %sp and return address in a global so they are - * available at cwp = HI_LIMIT ... where the 'global'/'in' regs - * are restored. NOTE: %sp changes with cwp. - */ - mov %g7, %o7 - mov %g6, %sp - - /* Get LO_LIMIT/HI_LIMIT to know where to start & stop. Note: in - * the underflow exception, cwp is __NOT__ guaranteed to be zero. - * If the OCI debug module is enabled the reset value for LO_LIMIT - * is 2, not 1 -- so cwp can be 1 or 0. - */ - pfx 2 /* WVALID */ - rdctl %g1 - mov %g2, %g1 - pfx 0 - and %g1, 0x1f /* g1 <- LO_LIMIT */ - lsri %g2, 5 - pfx 0 - and %g2,0x1f /* g2 <- HI_LIMIT */ - - /* Set istatus so cwp = HI_LIMIT after tret - */ - movi %g5, 0x1f - lsli %g5, 4 - not %g5 /* mask to clr cwp */ - pfx 1 /* istatus */ - rdctl %g0 - and %g0, %g5 /* clear cwp field */ - - mov %g4, %g2 - lsli %g4, 4 - or %g0, %g4 /* cwp = HI_LIMIT */ - pfx 1 - wrctl %g0 /* update istatus */ - - /* Now move up the register file, saving as we go. When loop - * is first entered, %g1 is at LO_LIMIT. - */ -0: - restore /* cwp++ */ - sts [%sp,0], %l0 /* Save "local" regs*/ - sts [%sp,1], %l1 - sts [%sp,2], %l2 - sts [%sp,3], %l3 - sts [%sp,4], %l4 - sts [%sp,5], %l5 - sts [%sp,6], %l6 - sts [%sp,7], %l7 - - sts [%sp,8], %i0 /* Save 'in' regs */ - sts [%sp,9], %i1 - sts [%sp,10], %i2 - sts [%sp,11], %i3 - sts [%sp,12], %i4 - sts [%sp,13], %i5 - sts [%sp,14], %i6 - sts [%sp,15], %i7 - - cmp %g1, %g2 /* cwp == HI_LIMIT ? */ - skps cc_ne /* if so, we're done */ - br 1f - nop /* delay slot */ - - inc %g1 /* g1 <- cwp++ */ - br 0b - nop /* delay slot */ - - /* At this point cwp = HI_LIMIT, so the global/in regs that were - * in place when the underflow occurred must be restored using - * the original stack pointer (saved in g6). - */ -1: - mov %o7, %g7 /* restore return addr */ - mov %sp, %g6 /* Restore original sp */ - - lds %g0, [%sp,0] /* Restore 'global' regs*/ - lds %g1, [%sp,1] - lds %g2, [%sp,2] - lds %g3, [%sp,3] - lds %g4, [%sp,4] - lds %g5, [%sp,5] - lds %g6, [%sp,6] - lds %g7, [%sp,7] - - lds %i0, [%sp,8] /* Restore 'in' regs*/ - lds %i1, [%sp,9] - lds %i2, [%sp,10] - lds %i3, [%sp,11] - lds %i4, [%sp,12] - lds %i5, [%sp,13] - lds %i6, [%sp,14] - lds %i7, [%sp,15] - - tret %o7 /* All done */ - -/************************************************************************* - * Register window overflow - * - * The register window overflow exception occurs whenever the highest - * valid register window is in use (cwp = HI_LIMIT) and a restore - * instruction is issued. Control is transferred to the overflow handler - * before the instruction following restore is executed. - * - * When a register window overflow exception is taken, the exception - * handler sees cwp at HI_LIMIT. - ************************************************************************/ - .text - .global _cwp_hilimit - .align 4 - -_cwp_hilimit: - - /* Save 'global'/'in' regs on the stack -- will restore when cwp - * is at LO_LIMIT. Locals don't need saving as they are going away. - */ - sts [%sp,0], %g0 /* Save "global" regs*/ - sts [%sp,1], %g1 - sts [%sp,2], %g2 - sts [%sp,3], %g3 - sts [%sp,4], %g4 - sts [%sp,5], %g5 - sts [%sp,6], %g6 - sts [%sp,7], %g7 - - sts [%sp,8], %i0 /* Save 'in' regs */ - sts [%sp,9], %i1 - sts [%sp,10], %i2 - sts [%sp,11], %i3 - sts [%sp,12], %i4 - sts [%sp,13], %i5 - sts [%sp,14], %i6 - sts [%sp,15], %i7 - - /* The current %sp must be available in global to restore regs - * saved on stack. Need return addr as well ;-) - */ - mov %g7, %o7 - mov %g6, %sp - - /* Get HI_LIMIT & LO_LIMIT - */ - pfx 2 /* WVALID */ - rdctl %g1 - mov %g2, %g1 - pfx 0 - and %g1, 0x1f /* g1 <- LO_LIMIT */ - lsri %g2, 5 - pfx 0 - and %g2,0x1f /* g2 <- HI_LIMIT */ - - /* Set istatus so cwp = LO_LIMIT after tret - */ - movi %g5, 0x1f - lsli %g5, 4 - not %g5 /* mask to clr cwp */ - pfx 1 /* istatus */ - rdctl %g0 - and %g0, %g5 /* clear cwp field */ - - mov %g4, %g1 /* g4 <- LO_LIMIT */ - lsli %g4, 4 - or %g0, %g4 /* cwp = LO_LIMIT */ - pfx 1 - wrctl %g0 /* update istatus */ - - /* Move to cwp = LO_LIMIT-1 and restore 'in' regs. - */ - subi %g4,(1 << 4) /* g4 <- LO_LIMIT - 1 */ - rdctl %g0 - and %g0, %g5 /* clear cwp field */ - or %g0, %g4 /* cwp = LO_LIMIT - 1 */ - wrctl %g0 /* update status */ - nop - - mov %sp, %g6 /* Restore sp */ - lds %i0, [%sp,8] /* Restore 'in' regs */ - lds %i1, [%sp,9] - lds %i2, [%sp,10] - lds %i3, [%sp,11] - lds %i4, [%sp,12] - lds %i5, [%sp,13] - lds %i6, [%sp,14] /* sp in next window */ - lds %i7, [%sp,15] - - /* Starting at LO_LIMIT-1, move up the register file, restoring - * along the way. - */ -0: - restore /* cwp++ */ - lds %l0, [%sp,0] /* Restore 'local' regs*/ - lds %l1, [%sp,1] - lds %l2, [%sp,2] - lds %l3, [%sp,3] - lds %l4, [%sp,4] - lds %l5, [%sp,5] - lds %l6, [%sp,6] - lds %l7, [%sp,7] - - lds %i0, [%sp,8] /* Restore 'in' regs */ - lds %i1, [%sp,9] - lds %i2, [%sp,10] - lds %i3, [%sp,11] - lds %i4, [%sp,12] - lds %i5, [%sp,13] - lds %i6, [%sp,14] /* sp in next window */ - lds %i7, [%sp,15] - - cmp %g1, %g2 /* cwp == HI_LIMIT ? */ - skps cc_ne /* if so, we're done */ - br 1f - nop /* delay slot */ - - inc %g1 /* cwp++ */ - br 0b - nop /* delay slot */ - - /* All windows have been updated at this point, but the globals - * still need to be restored. Go to cwp = LO_LIMIT-1 to get - * some registers to use. - */ -1: - rdctl %g0 - and %g0, %g5 /* clear cwp field */ - or %g0, %g4 /* cwp = LO_LIMIT - 1 */ - wrctl %g0 /* update status */ - nop - - /* Now there are some registers available to use in restoring - * the globals. - */ - mov %sp, %g6 - mov %o7, %g7 - - lds %g0, [%sp,0] /* Restore "global" regs*/ - lds %g1, [%sp,1] - lds %g2, [%sp,2] - lds %g3, [%sp,3] - lds %g4, [%sp,4] - lds %g5, [%sp,5] - lds %g6, [%sp,6] - lds %g7, [%sp,7] - - /* The tret moves istatus -> status. istatus was already set for - * cwp = LO_LIMIT. - */ - - tret %o7 /* done */ - -/************************************************************************* - * Default exception handler - * - * The default handler passes control to external_interrupt(). So trap - * or hardware interrupt hanlders can be installed using the familiar - * irq_install_handler(). - * - * Here, the stack is fixed-up and cwp is incremented prior to calling - * external_interrupt(). This lets the underflow and overflow handlers - * operate normally during the exception. - ************************************************************************/ - .text - .global _def_xhandler - .align 4 - -_def_xhandler: - - /* Allocate some stack space: 16 words at %sp to accomodate - * a reg window underflow, 8 words to save interrupted task's - * 'out' regs (which are now the 'in' regs), 8 words to preserve - * the 'global' regs and 3 words to save the return address, - * status and istatus. istatus must be saved in the event an - * underflow occurs in a dispatched handler. status is saved so - * a handler can access it on stack. - */ - pfx %hi((16+16+3) * 4) - subi %fp, %lo((16+16+3) * 4) - mov %sp, %fp - - /* Save the 'global' regs and the interrupted task's 'out' regs - * (our 'in' regs) along with the return addr, status & istatus. - * First 16 words are for underflow exception. - */ - rdctl %l0 /* status */ - pfx 1 /* istatus */ - rdctl %l1 - - sts [%sp,16+0], %g0 /* Save 'global' regs*/ - sts [%sp,16+1], %g1 - sts [%sp,16+2], %g2 - sts [%sp,16+3], %g3 - sts [%sp,16+4], %g4 - sts [%sp,16+5], %g5 - sts [%sp,16+6], %g6 - sts [%sp,16+7], %g7 - - sts [%sp,16+8], %i0 /* Save 'in' regs */ - sts [%sp,16+9], %i1 - sts [%sp,16+10], %i2 - sts [%sp,16+11], %i3 - sts [%sp,16+12], %i4 - sts [%sp,16+13], %i5 - sts [%sp,16+14], %i6 - sts [%sp,16+15], %i7 - - sts [%sp,16+16], %l0 /* status */ - sts [%sp,16+17], %l1 /* istatus */ - sts [%sp,16+18], %o7 /* return addr */ - - /* Move to cwp+1 ... this guarantees cwp is at or above LO_LIMIT. - * Need to set IPRI=3 and IE=1 to enable underflow exceptions. - * NOTE: only the 'out' regs have been saved ... can't touch - * the 'in' or 'local' here. - */ - restore /* cwp++ */ - rdctl %o0 /* o0 <- status */ - - pfx %hi(0x7e00) - movi %o1, %lo(0x7e00) - not %o1 - and %o0, %o1 /* clear IPRI */ - - pfx %hi(0x8600) - movi %o1, %lo(0x8600) - or %o0, %o1 /* IPRI=3, IE=1 */ - - wrctl %o0 /* o0 -> status */ - nop - - /* It's ok to call a C routine now since cwp >= LO_LIMIT, - * interrupt task's registers are/will be preserved, and - * underflow exceptions can be handled. - */ - pfx %hi(external_interrupt@h) - movi %o1, %lo(external_interrupt@h) - pfx %xhi(external_interrupt@h) - movhi %o1, %xlo(external_interrupt@h) - bgen %o0, 4+2 /* 16 * 4 */ - add %o0, %sp /* Ptr to regs */ - call %o1 - nop - - /* Move back to the exception register window, restore the 'out' - * registers, then return from exception. - */ - rdctl %o0 /* o0 <- status */ - subi %o0, 16 - wrctl %o0 /* cwp-- */ - nop - - mov %sp, %fp - lds %g0, [%sp,16+0] /* Restore 'global' regs*/ - lds %g1, [%sp,16+1] - lds %g2, [%sp,16+2] - lds %g3, [%sp,16+3] - lds %g4, [%sp,16+4] - lds %g5, [%sp,16+5] - lds %g6, [%sp,16+6] - lds %g7, [%sp,16+7] - - lds %i0, [%sp,16+8] /* Restore 'in' regs*/ - lds %i1, [%sp,16+9] - lds %i2, [%sp,16+10] - lds %i3, [%sp,16+11] - lds %i4, [%sp,16+12] - lds %i5, [%sp,16+13] - lds %i6, [%sp,16+14] - lds %i7, [%sp,16+15] - - lds %l0, [%sp,16+16] /* status */ - lds %l1, [%sp,16+17] /* istatus */ - lds %o7, [%sp,16+18] /* return addr */ - - pfx 1 - wrctl %l1 /* restore istatus */ - - pfx %hi((16+16+3) * 4) - addi %sp, %lo((16+16+3) * 4) - mov %fp, %sp - - tret %o7 /* Done */ - - -/************************************************************************* - * Timebase Timer Interrupt -- This has identical structure to above, - * but calls timer_interrupt(). Doing it this way keeps things similar - * to other architectures (e.g. ppc). - ************************************************************************/ - .text - .global _timebase_int - .align 4 - -_timebase_int: - - /* Allocate stack space. - */ - pfx %hi((16+16+3) * 4) - subi %fp, %lo((16+16+3) * 4) - mov %sp, %fp - - /* Save the 'global' regs & 'out' regs (our 'in' regs) - */ - rdctl %l0 /* status */ - pfx 1 /* istatus */ - rdctl %l1 - - sts [%sp,16+0], %g0 /* Save 'global' regs*/ - sts [%sp,16+1], %g1 - sts [%sp,16+2], %g2 - sts [%sp,16+3], %g3 - sts [%sp,16+4], %g4 - sts [%sp,16+5], %g5 - sts [%sp,16+6], %g6 - sts [%sp,16+7], %g7 - - sts [%sp,16+8], %i0 /* Save 'in' regs */ - sts [%sp,16+9], %i1 - sts [%sp,16+10], %i2 - sts [%sp,16+11], %i3 - sts [%sp,16+12], %i4 - sts [%sp,16+13], %i5 - sts [%sp,16+14], %i6 - sts [%sp,16+15], %i7 - - sts [%sp,16+16], %l0 /* status */ - sts [%sp,16+17], %l1 /* istatus */ - sts [%sp,16+18], %o7 /* return addr */ - - /* Move to cwp+1. - */ - restore /* cwp++ */ - rdctl %o0 /* o0 <- status */ - - pfx %hi(0x7e00) - movi %o1, %lo(0x7e00) - not %o1 - and %o0, %o1 /* clear IPRI */ - - pfx %hi(0x8600) - movi %o1, %lo(0x8600) - or %o0, %o1 /* IPRI=3, IE=1 */ - - wrctl %o0 /* o0 -> status */ - nop - - /* Call timer_interrupt() - */ - pfx %hi(timer_interrupt@h) - movi %o1, %lo(timer_interrupt@h) - pfx %xhi(timer_interrupt@h) - movhi %o1, %xlo(timer_interrupt@h) - bgen %o0, 4+2 /* 16 * 4 */ - add %o0, %sp /* Ptr to regs */ - call %o1 - nop - - /* Move back to the exception register window, restore the 'out' - * registers, then return from exception. - */ - rdctl %o0 /* o0 <- status */ - subi %o0, 16 - wrctl %o0 /* cwp-- */ - nop - - mov %sp, %fp - lds %g0, [%sp,16+0] /* Restore 'global' regs*/ - lds %g1, [%sp,16+1] - lds %g2, [%sp,16+2] - lds %g3, [%sp,16+3] - lds %g4, [%sp,16+4] - lds %g5, [%sp,16+5] - lds %g6, [%sp,16+6] - lds %g7, [%sp,16+7] - - lds %i0, [%sp,16+8] /* Restore 'in' regs*/ - lds %i1, [%sp,16+9] - lds %i2, [%sp,16+10] - lds %i3, [%sp,16+11] - lds %i4, [%sp,16+12] - lds %i5, [%sp,16+13] - lds %i6, [%sp,16+14] - lds %i7, [%sp,16+15] - - lds %l0, [%sp,16+16] /* status */ - lds %l1, [%sp,16+17] /* istatus */ - lds %o7, [%sp,16+18] /* return addr */ - - pfx 1 - wrctl %l1 /* restore istatus */ - - pfx %hi((16+16+3) * 4) - addi %sp, %lo((16+16+3) * 4) - mov %fp, %sp - - tret %o7 /* Done */ - -/************************************************************************* - * GDB stubs - ************************************************************************/ - .text - .global _brkpt_hw_int, _brkpt_sw_int - .align 4 - -_brkpt_hw_int: - movi %l1, 9 - pfx 3 - wrctl %l1 - pfx 4 - wrctl %l1 - -_brkpt_sw_int: - movi %l1, 9 - pfx 3 - wrctl %l1 - pfx 4 - wrctl %l1 - - tret %o7 diff --git a/cpu/nios2/Makefile b/cpu/nios2/Makefile deleted file mode 100644 index 11fda50..0000000 --- a/cpu/nios2/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -AOBJS = exceptions.o -OBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) $(AOBJS) - $(AR) crv $@ $(OBJS) $(AOBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/nios2/config.mk b/cpu/nios2/config.mk deleted file mode 100644 index f228d72..0000000 --- a/cpu/nios2/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += diff --git a/cpu/nios2/cpu.c b/cpu/nios2/cpu.c deleted file mode 100644 index f4217a8..0000000 --- a/cpu/nios2/cpu.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined (CFG_NIOS_SYSID_BASE) -extern void display_sysid (void); -#endif /* CFG_NIOS_SYSID_BASE */ - -int checkcpu (void) -{ - printf ("CPU : Nios-II\n"); -#if !defined(CFG_NIOS_SYSID_BASE) - printf ("SYSID : \n"); -#else - display_sysid (); -#endif - return (0); -} - - -int do_reset (void) -{ - void (*rst)(void) = (void(*)(void))CFG_RESET_ADDR; - disable_interrupts (); - rst(); - return(0); -} diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c deleted file mode 100644 index a8851e9..0000000 --- a/cpu/nios2/epcs.c +++ /dev/null @@ -1,711 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if defined(CFG_NIOS_EPCSBASE) -#include -#include -#include -#include - - -/*-----------------------------------------------------------------------*/ -#define SHORT_HELP\ - "epcs - read/write Cyclone EPCS configuration device.\n" - -#define LONG_HELP\ - "\n"\ - "epcs erase start [end]\n"\ - " - erase sector start or sectors start through end.\n"\ - "epcs info\n"\ - " - display EPCS device information.\n"\ - "epcs protect on | off\n"\ - " - turn device protection on or off.\n"\ - "epcs read addr offset count\n"\ - " - read count bytes from offset to addr.\n"\ - "epcs write addr offset count\n"\ - " - write count bytes to offset from addr.\n"\ - "epcs verify addr offset count\n"\ - " - verify count bytes at offset from addr.\n" - - -/*-----------------------------------------------------------------------*/ -/* Operation codes for serial configuration devices - */ -#define EPCS_WRITE_ENA 0x06 /* Write enable */ -#define EPCS_WRITE_DIS 0x04 /* Write disable */ -#define EPCS_READ_STAT 0x05 /* Read status */ -#define EPCS_READ_BYTES 0x03 /* Read bytes */ -#define EPCS_READ_ID 0xab /* Read silicon id */ -#define EPCS_WRITE_STAT 0x01 /* Write status */ -#define EPCS_WRITE_BYTES 0x02 /* Write bytes */ -#define EPCS_ERASE_BULK 0xc7 /* Erase entire device */ -#define EPCS_ERASE_SECT 0xd8 /* Erase sector */ - -/* Device status register bits - */ -#define EPCS_STATUS_WIP (1<<0) /* Write in progress */ -#define EPCS_STATUS_WEL (1<<1) /* Write enable latch */ - -/* Misc - */ -#define EPCS_TIMEOUT 100 /* 100 msec timeout */ - -static nios_spi_t *epcs = - (nios_spi_t *)CACHE_BYPASS(CFG_NIOS_EPCSBASE); - -/*********************************************************************** - * Device access - ***********************************************************************/ -static int epcs_cs (int assert) -{ - ulong start; - - if (assert) { - epcs->control |= NIOS_SPI_SSO; - } else { - /* Let all bits shift out */ - start = get_timer (0); - while ((epcs->status & NIOS_SPI_TMT) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - epcs->control &= ~NIOS_SPI_SSO; - } - return (0); -} - -static int epcs_tx (unsigned char c) -{ - ulong start; - - start = get_timer (0); - while ((epcs->status & NIOS_SPI_TRDY) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - epcs->txdata = c; - return (0); -} - -static int epcs_rx (void) -{ - ulong start; - - start = get_timer (0); - while ((epcs->status & NIOS_SPI_RRDY) == 0) - if (get_timer (start) > EPCS_TIMEOUT) - return (-1); - return (epcs->rxdata); -} - -static unsigned char bitrev[] = { - 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e, - 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f -}; - -static unsigned char epcs_bitrev (unsigned char c) -{ - unsigned char val; - - val = bitrev[c>>4]; - val |= bitrev[c & 0x0f]<<4; - return (val); -} - -static void epcs_rcv (unsigned char *dst, int len) -{ - while (len--) { - epcs_tx (0); - *dst++ = epcs_rx (); - } -} - -static void epcs_rrcv (unsigned char *dst, int len) -{ - while (len--) { - epcs_tx (0); - *dst++ = epcs_bitrev (epcs_rx ()); - } -} - -static void epcs_snd (unsigned char *src, int len) -{ - while (len--) { - epcs_tx (*src++); - epcs_rx (); - } -} - -static void epcs_rsnd (unsigned char *src, int len) -{ - while (len--) { - epcs_tx (epcs_bitrev (*src++)); - epcs_rx (); - } -} - -static void epcs_wr_enable (void) -{ - epcs_cs (1); - epcs_tx (EPCS_WRITE_ENA); - epcs_rx (); - epcs_cs (0); -} - -static unsigned char epcs_status_rd (void) -{ - unsigned char status; - - epcs_cs (1); - epcs_tx (EPCS_READ_STAT); - epcs_rx (); - epcs_tx (0); - status = epcs_rx (); - epcs_cs (0); - return (status); -} - -static void epcs_status_wr (unsigned char status) -{ - epcs_wr_enable (); - epcs_cs (1); - epcs_tx (EPCS_WRITE_STAT); - epcs_rx (); - epcs_tx (status); - epcs_rx (); - epcs_cs (0); - return; -} - -/*********************************************************************** - * Device information - ***********************************************************************/ - -static struct epcs_devinfo_t devinfo[] = { - { "EPCS1 ", 0x10, 17, 4, 15, 8, 0x0c }, - { "EPCS4 ", 0x12, 19, 8, 16, 8, 0x1c }, - { 0, 0, 0, 0, 0, 0 } -}; - -epcs_devinfo_t *epcs_dev_find (void) -{ - unsigned char buf[4]; - unsigned char id; - int i; - struct epcs_devinfo_t *dev = NULL; - - /* Read silicon id requires 3 "dummy bytes" before it's put - * on the wire. - */ - buf[0] = EPCS_READ_ID; - buf[1] = 0; - buf[2] = 0; - buf[3] = 0; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rcv (buf,1); - if (epcs_cs (0) == -1) - return (NULL); - id = buf[0]; - - /* Find the info struct */ - i = 0; - while (devinfo[i].name) { - if (id == devinfo[i].id) { - dev = &devinfo[i]; - break; - } - i++; - } - - return (dev); -} - -/*********************************************************************** - * Misc Utilities - ***********************************************************************/ -int epcs_cfgsz (void) -{ - int sz = 0; - unsigned char buf[128]; - unsigned char *p; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - /* Read in the first 128 bytes of the device */ - buf[0] = EPCS_READ_BYTES; - buf[1] = 0; - buf[2] = 0; - buf[3] = 0; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rrcv (buf, sizeof(buf)); - epcs_cs (0); - - /* Search for the starting 0x6a which is followed by the - * 4-byte 'register' and 4-byte bit-count. - */ - p = buf; - while (p < buf + sizeof(buf)-8) { - if ( *p == 0x6a ) { - /* Point to bit count and extract */ - p += 5; - sz = *p++; - sz |= *p++ << 8; - sz |= *p++ << 16; - sz |= *p++ << 24; - /* Convert to byte count */ - sz += 7; - sz >>= 3; - } else if (*p == 0xff) { - /* 0xff is ok ... just skip */ - p++; - continue; - } else { - /* Not 0xff or 0x6a ... something's not - * right ... report 'unknown' (sz=0). - */ - break; - } - } - return (sz); -} - -int epcs_erase (unsigned start, unsigned end) -{ - unsigned off, sectsz; - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev || (start>end)) - return (-1); - - /* Erase the requested sectors. An address is required - * that lies within the requested sector -- we'll just - * use the first address in the sector. - */ - printf ("epcs erasing sector %d ", start); - if (start != end) - printf ("to %d ", end); - sectsz = (1 << dev->sz_sect); - while (start <= end) { - off = start * sectsz; - start++; - - buf[0] = EPCS_ERASE_SECT; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_wr_enable (); - epcs_cs (1); - epcs_snd (buf,4); - epcs_cs (0); - - printf ("."); /* Some user feedback */ - - /* Wait for erase to complete */ - while (epcs_status_rd() & EPCS_STATUS_WIP) - ; - } - printf (" done.\n"); - return (0); -} - -int epcs_read (ulong addr, ulong off, ulong cnt) -{ - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - buf[0] = EPCS_READ_BYTES; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_cs (1); - epcs_snd (buf,4); - epcs_rrcv ((unsigned char *)addr, cnt); - epcs_cs (0); - - return (0); -} - -int epcs_write (ulong addr, ulong off, ulong cnt) -{ - ulong wrcnt; - unsigned pgsz; - unsigned char buf[4]; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) - return (-1); - - pgsz = (1<sz_page); - while (cnt) { - if (off % pgsz) - wrcnt = pgsz - (off % pgsz); - else - wrcnt = pgsz; - wrcnt = (wrcnt > cnt) ? cnt : wrcnt; - - buf[0] = EPCS_WRITE_BYTES; - buf[1] = off >> 16; - buf[2] = off >> 8; - buf[3] = off; - - epcs_wr_enable (); - epcs_cs (1); - epcs_snd (buf,4); - epcs_rsnd ((unsigned char *)addr, wrcnt); - epcs_cs (0); - - /* Wait for write to complete */ - while (epcs_status_rd() & EPCS_STATUS_WIP) - ; - - cnt -= wrcnt; - off += wrcnt; - addr += wrcnt; - } - - return (0); -} - -int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err) -{ - ulong rdcnt; - unsigned char buf[256]; - unsigned char *start,*end; - int i; - - start = end = (unsigned char *)addr; - while (cnt) { - rdcnt = (cnt>sizeof(buf)) ? sizeof(buf) : cnt; - epcs_read ((ulong)buf, off, rdcnt); - for (i=0; isz_sect); - off = sectsz * sect; - end = off + sectsz; - - while (off < end) { - epcs_read ((ulong)buf, off, sizeof(buf)); - for (i=0; i < sizeof(buf); i++) { - if (buf[i] != 0xff) { - *offset = off + i; - return (0); - } - } - off += sizeof(buf); - } - return (1); -} - - -/*********************************************************************** - * Commands - ***********************************************************************/ -static -void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - int i; - unsigned char stat; - unsigned tmp; - int erased; - - /* Basic device info */ - printf ("%s: %d kbytes (%d sectors x %d kbytes," - " %d bytes/page)\n", - dev->name, 1 << (dev->size-10), - dev->num_sects, 1 << (dev->sz_sect-10), - 1 << dev->sz_page ); - - /* Status -- for now protection is all-or-nothing */ - stat = epcs_status_rd(); - printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n", - stat, - (stat & EPCS_STATUS_WIP) ? 1 : 0, - (stat & EPCS_STATUS_WEL) ? 1 : 0, - (stat & dev->prot_mask) ? "on" : "off" ); - - /* Configuration */ - tmp = epcs_cfgsz (); - if (tmp) { - printf ("config: 0x%06x (%d) bytes\n", tmp, tmp ); - } else { - printf ("config: unknown\n" ); - } - - /* Sector info */ - for (i=0; inum_sects; i++) { - erased = epcs_sect_erased (i, &tmp, dev); - printf (" %d: %06x ", - i, i*(1<sz_sect) ); - if (erased) - printf ("erased\n"); - else - printf ("data @ 0x%06x\n", tmp); - } - - return; -} - -static -void do_epcs_erase (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - unsigned start,end; - - if ((argc < 3) || (argc > 4)) { - printf ("USAGE: epcs erase sect [end]\n"); - return; - } - if ((epcs_status_rd() & dev->prot_mask) != 0) { - printf ( "epcs: device protected.\n"); - return; - } - - start = simple_strtoul (argv[2], NULL, 10); - if (argc > 3) - end = simple_strtoul (argv[3], NULL, 10); - else - end = start; - if ((start >= dev->num_sects) || (start > end)) { - printf ("epcs: invalid sector range: [%d:%d]\n", - start, end ); - return; - } - - epcs_erase (start, end); - - return; -} - -static -void do_epcs_protect (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - unsigned char stat; - - /* For now protection is all-or-nothing to keep things - * simple. The protection bits don't map in a linear - * fashion ... and we would rather protect the bottom - * of the device since it contains the config data and - * leave the top unprotected for app use. But unfortunately - * protection works from top-to-bottom so it does - * really help very much from a software app point-of-view. - */ - if (argc < 3) { - printf ("USAGE: epcs protect on | off\n"); - return; - } - if (!dev) - return; - - /* Protection on/off is just a matter of setting/clearing - * all protection bits in the status register. - */ - stat = epcs_status_rd (); - if (strcmp ("on", argv[2]) == 0) { - stat |= dev->prot_mask; - } else if (strcmp ("off", argv[2]) == 0 ) { - stat &= ~dev->prot_mask; - } else { - printf ("epcs: unknown protection: %s\n", argv[2]); - return; - } - epcs_status_wr (stat); - return; -} - -static -void do_epcs_read (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - ulong addr,off,cnt; - ulong sz; - - if (argc < 5) { - printf ("USAGE: epcs read addr offset count\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: read %08lx <- %06lx (0x%lx bytes)\n", - addr, off, cnt); - epcs_read (addr, off, cnt); - - return; -} - -static -void do_epcs_write (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - ulong addr,off,cnt; - ulong sz; - ulong err; - - if (argc < 5) { - printf ("USAGE: epcs write addr offset count\n"); - return; - } - if ((epcs_status_rd() & dev->prot_mask) != 0) { - printf ( "epcs: device protected.\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: write %08lx -> %06lx (0x%lx bytes)\n", - addr, off, cnt); - epcs_write (addr, off, cnt); - if (epcs_verify (addr, off, cnt, &err) != 0) - printf ("epcs: write error at offset %06lx\n", err); - - return; -} - -static -void do_epcs_verify (struct epcs_devinfo_t *dev, int argc, char *argv[]) -{ - ulong addr,off,cnt; - ulong sz; - ulong err; - - if (argc < 5) { - printf ("USAGE: epcs verify addr offset count\n"); - return; - } - - sz = 1 << dev->size; - addr = simple_strtoul (argv[2], NULL, 16); - off = simple_strtoul (argv[3], NULL, 16); - cnt = simple_strtoul (argv[4], NULL, 16); - if (off > sz) { - printf ("offset is greater than device size" - "... aborting.\n"); - return; - } - if ((off + cnt) > sz) { - printf ("request exceeds device size" - "... truncating.\n"); - cnt = sz - off; - } - printf ("epcs: verify %08lx -> %06lx (0x%lx bytes)\n", - addr, off, cnt); - if (epcs_verify (addr, off, cnt, &err) != 0) - printf ("epcs: verify error at offset %06lx\n", err); - - return; -} - -/*-----------------------------------------------------------------------*/ -int do_epcs (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int len; - struct epcs_devinfo_t *dev = epcs_dev_find (); - - if (!dev) { - printf ("epcs: device not found.\n"); - return (-1); - } - - if (argc < 2) { - do_epcs_info (dev, argc, argv); - return (0); - } - - len = strlen (argv[1]); - if (strncmp ("info", argv[1], len) == 0) { - do_epcs_info (dev, argc, argv); - } else if (strncmp ("erase", argv[1], len) == 0) { - do_epcs_erase (dev, argc, argv); - } else if (strncmp ("protect", argv[1], len) == 0) { - do_epcs_protect (dev, argc, argv); - } else if (strncmp ("read", argv[1], len) == 0) { - do_epcs_read (dev, argc, argv); - } else if (strncmp ("write", argv[1], len) == 0) { - do_epcs_write (dev, argc, argv); - } else if (strncmp ("verify", argv[1], len) == 0) { - do_epcs_verify (dev, argc, argv); - } else { - printf ("epcs: unknown operation: %s\n", argv[1]); - } - - return (0); -} - -/*-----------------------------------------------------------------------*/ - - -U_BOOT_CMD( epcs, 5, 0, do_epcs, SHORT_HELP, LONG_HELP ); - -#endif /* CONFIG_NIOS_EPCS */ diff --git a/cpu/nios2/exceptions.S b/cpu/nios2/exceptions.S deleted file mode 100644 index d3b95cf..0000000 --- a/cpu/nios2/exceptions.S +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - - .text - .align 4 - - .global _exception - -_exception: - /* SAVE ALL REGS -- this allows trap and unimplemented - * instruction handlers to be coded conveniently in C - */ - addi sp, sp, -(33*4) - stw r0, 0(sp) - stw r1, 4(sp) - stw r2, 8(sp) - stw r3, 12(sp) - stw r4, 16(sp) - stw r5, 20(sp) - stw r6, 24(sp) - stw r7, 28(sp) - stw r8, 32(sp) - stw r9, 36(sp) - stw r10, 40(sp) - stw r11, 44(sp) - stw r12, 48(sp) - stw r13, 52(sp) - stw r14, 56(sp) - stw r15, 60(sp) - stw r16, 64(sp) - stw r17, 68(sp) - stw r19, 72(sp) - stw r19, 76(sp) - stw r20, 80(sp) - stw r21, 84(sp) - stw r22, 88(sp) - stw r23, 92(sp) - stw r24, 96(sp) - stw r25, 100(sp) - stw r26, 104(sp) - stw r27, 108(sp) - stw r28, 112(sp) - stw r29, 116(sp) - stw r30, 120(sp) - stw r31, 124(sp) - rdctl et, estatus - stw et, 128(sp) - - /* If interrupts are disabled -- software interrupt */ - rdctl et, estatus - andi et, et, 1 - beq et, r0, 0f - - /* If no interrupts are pending -- software interrupt */ - rdctl et, ipending - beq et, r0, 0f - - /* HARDWARE INTERRUPT: Call interrupt handler */ - movhi r3, %hi(external_interrupt) - ori r3, r3, %lo(external_interrupt) - mov r4, sp /* ptr to regs */ - callr r3 - - /* Return address fixup: execution resumes by re-issue of - * interrupted instruction at ea-4 (ea == r29). Here we do - * simple fixup to allow common exception return. - */ - ldw r3, 116(sp) - addi r3, r3, -4 - stw r3, 116(sp) - br _exception_return - -0: - /* TRAP EXCEPTION */ - movhi r3, %hi(OPC_TRAP) - ori r3, r3, %lo(OPC_TRAP) - addi r1, ea, -4 - ldw r1, 0(r1) - bne r1, r3, 1f - movhi r3, %hi(trap_handler) - ori r3, r3, %lo(trap_handler) - mov r4, sp /* ptr to regs */ - callr r3 - br _exception_return - -1: - /* UNIMPLEMENTED INSTRUCTION EXCEPTION */ - movhi r3, %hi(soft_emulation) - ori r3, r3, %lo(soft_emulation) - mov r4, sp /* ptr to regs */ - callr r3 - - /* Restore regsisters and return from exception*/ -_exception_return: - ldw r1, 4(sp) - ldw r2, 8(sp) - ldw r3, 12(sp) - ldw r4, 16(sp) - ldw r5, 20(sp) - ldw r6, 24(sp) - ldw r7, 28(sp) - ldw r8, 32(sp) - ldw r9, 36(sp) - ldw r10, 40(sp) - ldw r11, 44(sp) - ldw r12, 48(sp) - ldw r13, 52(sp) - ldw r14, 56(sp) - ldw r15, 60(sp) - ldw r16, 64(sp) - ldw r17, 68(sp) - ldw r19, 72(sp) - ldw r19, 76(sp) - ldw r20, 80(sp) - ldw r21, 84(sp) - ldw r22, 88(sp) - ldw r23, 92(sp) - ldw r24, 96(sp) - ldw r25, 100(sp) - ldw r26, 104(sp) - ldw r27, 108(sp) - ldw r28, 112(sp) - ldw r29, 116(sp) - ldw r30, 120(sp) - ldw r31, 124(sp) - addi sp, sp, (33*4) - eret -/*-------------------------------------------------------------*/ diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c deleted file mode 100644 index 4a6da58..0000000 --- a/cpu/nios2/interrupts.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif - -#if defined(CFG_NIOS_TMRBASE) && !defined(CFG_NIOS_TMRIRQ) -#error CFG_NIOS_TMRIRQ not defined (see documentation) -#endif - -/****************************************************************************/ - -struct irq_action { - interrupt_handler_t *handler; - void *arg; - int count; -}; - -static struct irq_action vecs[32]; - -/*************************************************************************/ -volatile ulong timestamp = 0; - -void reset_timer (void) -{ - timestamp = 0; -} - -ulong get_timer (ulong base) -{ - WATCHDOG_RESET (); - return (timestamp - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} - - -/* The board must handle this interrupt if a timer is not - * provided. - */ -#if defined(CFG_NIOS_TMRBASE) -void tmr_isr (void *arg) -{ - nios_timer_t *tmr = (nios_timer_t *)arg; - /* Interrupt is cleared by writing anything to the - * status register. - */ - tmr->status = 0; - timestamp += CFG_NIOS_TMRMS; -#ifdef CONFIG_STATUS_LED - status_led_tick(timestamp); -#endif -} - -static void tmr_init (void) -{ - nios_timer_t *tmr =(nios_timer_t *)CACHE_BYPASS(CFG_NIOS_TMRBASE); - - tmr->control &= ~(NIOS_TIMER_START | NIOS_TIMER_ITO); - tmr->control |= NIOS_TIMER_STOP; -#if defined(CFG_NIOS_TMRCNT) - tmr->periodl = CFG_NIOS_TMRCNT & 0xffff; - tmr->periodh = (CFG_NIOS_TMRCNT >> 16) & 0xffff; -#endif - tmr->control |= ( NIOS_TIMER_ITO | - NIOS_TIMER_CONT | - NIOS_TIMER_START ); - irq_install_handler (CFG_NIOS_TMRIRQ, tmr_isr, (void *)tmr); -} - -#endif /* CFG_NIOS_TMRBASE */ - -/*************************************************************************/ -int disable_interrupts (void) -{ - int val = rdctl (CTL_STATUS); - wrctl (CTL_STATUS, val & ~STATUS_IE); - return (val & STATUS_IE); -} - -void enable_interrupts( void ) -{ - int val = rdctl (CTL_STATUS); - wrctl (CTL_STATUS, val | STATUS_IE); -} - -void external_interrupt (struct pt_regs *regs) -{ - unsigned irqs; - struct irq_action *act; - - /* Evaluate only irqs that are both enabled AND pending */ - irqs = rdctl (CTL_IENABLE) & rdctl (CTL_IPENDING); - act = vecs; - - /* Assume (as does the Nios2 HAL) that bit 0 is highest - * priority. NOTE: There is ALWAYS a handler assigned - * (the default if no other). - */ - while (irqs) { - if (irqs & 1) { - act->handler (act->arg); - act->count++; - } - irqs >>=1; - act++; - } -} - -static void def_hdlr (void *arg) -{ - unsigned irqs = rdctl (CTL_IENABLE); - - /* Disable the individual interrupt -- with gratuitous - * warning. - */ - irqs &= ~(1 << (int)arg); - wrctl (CTL_IENABLE, irqs); - printf ("WARNING: Disabling unhandled interrupt: %d\n", - (int)arg); -} - -/*************************************************************************/ -void irq_install_handler (int irq, interrupt_handler_t *hdlr, void *arg) -{ - - int flag; - struct irq_action *act; - unsigned ena = rdctl (CTL_IENABLE); - - if ((irq < 0) || (irq > 31)) - return; - act = &vecs[irq]; - - flag = disable_interrupts (); - if (hdlr) { - act->handler = hdlr; - act->arg = arg; - ena |= (1 << irq); /* enable */ - } else { - act->handler = def_hdlr; - act->arg = (void *)irq; - ena &= ~(1 << irq); /* disable */ - } - wrctl (CTL_IENABLE, ena); - if (flag) enable_interrupts (); -} - - -int interrupt_init (void) -{ - int i; - - /* Assign the default handler to all */ - for (i = 0; i < 32; i++) { - vecs[i].handler = def_hdlr; - vecs[i].arg = (void *)i; - vecs[i].count = 0; - } - -#if defined(CFG_NIOS_TMRBASE) - tmr_init (); -#endif - - enable_interrupts (); - return (0); -} - - -/*************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) -int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int i; - struct irq_action *act = vecs; - - printf ("\nInterrupt-Information:\n\n"); - printf ("Nr Routine Arg Count\n"); - printf ("-----------------------------\n"); - - for (i=0; i<32; i++) { - if (act->handler != def_hdlr) { - printf ("%02d %08lx %08lx %d\n", - i, - (ulong)act->handler, - (ulong)act->arg, - act->count); - } - act++; - } - printf ("\n"); - - return (0); -} -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c deleted file mode 100644 index 2d08c93..0000000 --- a/cpu/nios2/serial.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include - -/*------------------------------------------------------------------ - * JTAG acts as the serial port - *-----------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) - -static nios_jtag_t *jtag = - (nios_jtag_t *)CACHE_BYPASS(CFG_NIOS_CONSOLE); - -void serial_setbrg( void ){ return; } -int serial_init( void ) { return(0);} - -void serial_putc (char c) -{ - unsigned val; - - while (NIOS_JTAG_WSPACE (jtag->control) == 0) - WATCHDOG_RESET (); - jtag->data = (unsigned char)c; -} - -void serial_puts (const char *s) -{ - while (*s != 0) - serial_putc (*s++); -} - -int serial_tstc (void) -{ - return (jtag->control & NIOS_JTAG_RRDY); -} - -int serial_getc (void) -{ - int c; - unsigned val; - - while (1) { - WATCHDOG_RESET (); - val = jtag->data; - if (val & NIOS_JTAG_RVALID) - break; - } - c = val & 0x0ff; - return (c); -} - -/*------------------------------------------------------------------ - * UART the serial port - *-----------------------------------------------------------------*/ -#else - -static nios_uart_t *uart = (nios_uart_t *) - CACHE_BYPASS(CFG_NIOS_CONSOLE); - -#if defined(CFG_NIOS_FIXEDBAUD) - -/* Everything's already setup for fixed-baud PTF - * assignment - */ -void serial_setbrg (void){ return; } -int serial_init (void) { return (0);} - -#else - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned div; - - div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; - uart->divisor = div; - return; -} - -int serial_init (void) -{ - serial_setbrg (); - return (0); -} - -#endif /* CFG_NIOS_FIXEDBAUD */ - - -/*----------------------------------------------------------------------- - * UART CONSOLE - *---------------------------------------------------------------------*/ -void serial_putc (char c) -{ - if (c == '\n') - serial_putc ('\r'); - while ((uart->status & NIOS_UART_TRDY) == 0) - WATCHDOG_RESET (); - uart->txdata = (unsigned char)c; -} - -void serial_puts (const char *s) -{ - while (*s != 0) { - serial_putc (*s++); - } -} - -int serial_tstc (void) -{ - return (uart->status & NIOS_UART_RRDY); -} - -int serial_getc (void) -{ - while (serial_tstc () == 0) - WATCHDOG_RESET (); - return( uart->rxdata & 0x00ff ); -} - -#endif /* CONFIG_JTAG_CONSOLE */ diff --git a/cpu/nios2/start.S b/cpu/nios2/start.S deleted file mode 100644 index 4c6e470..0000000 --- a/cpu/nios2/start.S +++ /dev/null @@ -1,216 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -/************************************************************************* - * RESTART - ************************************************************************/ - - .text - .global _start - -_start: - /* ICACHE INIT -- only the icache line at the reset address - * is invalidated at reset. So the init must stay within - * the cache line size (8 words). If GERMS is used, we'll - * just be invalidating the cache a second time. If cache - * is not implemented initi behaves as nop. - */ - ori r4, r0, %lo(CFG_ICACHELINE_SIZE) - movhi r5, %hi(CFG_ICACHE_SIZE) - ori r5, r5, %lo(CFG_ICACHE_SIZE) - mov r6, r0 -0: initi r6 - add r6, r6, r4 - bltu r6, r5, 0b - br _except_end /* Skip the tramp */ - - /* EXCEPTION TRAMPOLINE -- the following gets copied - * to the exception address (below), but is otherwise at the - * default exception vector offset (0x0020). - */ -_except_start: - movhi et, %hi(_exception) - ori et, et, %lo(_exception) - jmp et -_except_end: - - /* INTERRUPTS -- for now, all interrupts masked and globally - * disabled. - */ - wrctl status, r0 /* Disable interrupts */ - wrctl ienable, r0 /* All disabled */ - - /* DCACHE INIT -- if dcache not implemented, initd behaves as - * nop. - */ - movhi r4, %hi(CFG_DCACHELINE_SIZE) - ori r4, r4, %lo(CFG_DCACHELINE_SIZE) - movhi r5, %hi(CFG_DCACHE_SIZE) - ori r5, r5, %lo(CFG_DCACHE_SIZE) - mov r6, r0 -1: initd 0(r6) - add r6, r6, r4 - bltu r6, r5, 1b - - /* RELOCATE CODE, DATA & COMMAND TABLE -- the following code - * assumes code, data and the command table are all - * contiguous. This lets us relocate everything as a single - * block. Make sure the linker script matches this ;-) - */ - nextpc r4 -_cur: movhi r5, %hi(_cur - _start) - ori r5, r5, %lo(_cur - _start) - sub r4, r4, r5 /* r4 <- cur _start */ - mov r8, r4 - movhi r5, %hi(_start) - ori r5, r5, %lo(_start) /* r5 <- linked _start */ - beq r4, r5, 3f - - movhi r6, %hi(_edata) - ori r6, r6, %lo(_edata) -2: ldwio r7, 0(r4) - addi r4, r4, 4 - stwio r7, 0(r5) - addi r5, r5, 4 - bne r5, r6, 2b -3: - - /* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent - * and between __bss_start and _end. - */ - movhi r5, %hi(__bss_start) - ori r5, r5, %lo(__bss_start) - movhi r6, %hi(_end) - ori r6, r6, %lo(_end) - beq r5, r6, 5f - -4: stwio r0, 0(r5) - addi r5, r5, 4 - bne r5, r6, 4b -5: - - /* GLOBAL POINTER -- the global pointer is used to reference - * "small data" (see -G switch). The linker script must - * provide the gp address. - */ - movhi gp, %hi(_gp) - ori gp, gp, %lo(_gp) - - /* JUMP TO RELOC ADDR */ - movhi r4, %hi(_reloc) - ori r4, r4, %lo(_reloc) - jmp r4 -_reloc: - - /* COPY EXCEPTION TRAMPOLINE -- copy the tramp to the - * exception address. Define CONFIG_ROM_STUBS to prevent - * the copy (e.g. exception in flash or in other - * softare/firmware component). - */ -#if !defined(CONFIG_ROM_STUBS) - movhi r4, %hi(_except_start) - ori r4, r4, %lo(_except_start) - movhi r5, %hi(_except_end) - ori r5, r5, %lo(_except_end) - movhi r6, %hi(CFG_EXCEPTION_ADDR) - ori r6, r6, %lo(CFG_EXCEPTION_ADDR) - beq r4, r6, 7f /* Skip if at proper addr */ - -6: ldwio r7, 0(r4) - stwio r7, 0(r6) - addi r4, r4, 4 - addi r6, r6, 4 - bne r4, r5, 6b -7: -#endif - - /* STACK INIT -- zero top two words for call back chain. - */ - movhi sp, %hi(CFG_INIT_SP) - ori sp, sp, %lo(CFG_INIT_SP) - addi sp, sp, -8 - stw r0, 0(sp) - stw r0, 4(sp) - mov fp, sp - - /* - * Call board_init -- never returns - */ - movhi r4, %hi(board_init@h) - ori r4, r4, %lo(board_init@h) - callr r4 - - /* NEVER RETURNS -- but branch to the _start just - * in case ;-) - */ - br _start - - -/* - * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in - * the core. For simple delay loops, we do our best by counting - * instruction cycles. - * - * Instruction performance varies based on the core. For cores - * with icache and static/dynamic branch prediction (II/f, II/s): - * - * Normal ALU (e.g. add, cmp, etc): 1 cycle - * Branch (correctly predicted, taken): 2 cycles - * Negative offset is predicted (II/s). - * - * For cores without icache and no branch prediction (II/e): - * - * Normal ALU (e.g. add, cmp, etc): 6 cycles - * Branch (no prediction): 6 cycles - * - * For simplicity, if an instruction cache is implemented we - * assume II/f or II/s. Otherwise, we use the II/e. - * - */ - .globl dly_clks - -dly_clks: - -#if (CFG_ICACHE_SIZE > 0) - subi r4, r4, 3 /* 3 clocks/loop */ -#else - subi r4, r4, 12 /* 12 clocks/loop */ -#endif - bge r4, r0, dly_clks - ret - - -#if !defined(CONFIG_IDENT_STRING) -#define CONFIG_IDENT_STRING "" -#endif - .data - .globl version_string - -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c deleted file mode 100644 index 2b7a569..0000000 --- a/cpu/nios2/sysid.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if defined (CFG_NIOS_SYSID_BASE) - -#include -#include -#include -#include - -void display_sysid (void) -{ - struct nios_sysid_t *sysid = - (struct nios_sysid_t *)CACHE_BYPASS(CFG_NIOS_SYSID_BASE); - struct tm t; - char asc[32]; - - localtime_r ((time_t *)&sysid->timestamp, &t); - asctime_r (&t, asc); - printf ("SYSID : %08x, %s", sysid->id, asc); - -} - -int do_sysid (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - display_sysid (); - return (0); -} - -U_BOOT_CMD( - sysid, 1, 1, do_sysid, - "sysid - display Nios-II system id\n\n", - "\n - display Nios-II system id\n" -); -#endif /* CFG_NIOS_SYSID_BASE */ diff --git a/cpu/nios2/traps.c b/cpu/nios2/traps.c deleted file mode 100644 index 3f1517d..0000000 --- a/cpu/nios2/traps.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -void trap_handler (struct pt_regs *regs) -{ - /* Just issue warning */ - printf ("\n\n*** WARNING: unimplemented trap @ %08x\n\n", - regs->reg[29] - 4); -} - -void soft_emulation (struct pt_regs *regs) -{ - /* TODO: Software emulation of mul/div etc. Until this is - * implemented, generate warning and hang. - */ - printf ("\n\n*** ERROR: unimplemented instruction @ %08x\n", - regs->reg[29] - 4); - hang (); -} diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c deleted file mode 100644 index 64431ab..0000000 --- a/cpu/ppc4xx/405gp_pci.c +++ /dev/null @@ -1,553 +0,0 @@ -/*-----------------------------------------------------------------------------+ - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *-----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ - * - * File Name: 405gp_pci.c - * - * Function: Initialization code for the 405GP PCI Configuration regs. - * - * Author: Mark Game - * - * Change Activity- - * - * Date Description of Change BY - * --------- --------------------- --- - * 09-Sep-98 Created MCG - * 02-Nov-98 Removed External arbiter selected message JWB - * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB - * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG - * from (0 to n) to (1 to n). - * 17-May-99 Port to Walnut JWB - * 17-Jun-99 Updated for VGA support JWB - * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB - * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG - * target latency timer values are not supported). - * Should be fixed in pass 2. - * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB - * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS. - * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB - * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not - * really required after a reset since PMMxMAs are already - * disabled but is a good practice nonetheless. JWB - * 12-Jun-01 stefan.roese@esd-electronics.com - * - PCI host/adapter handling reworked - * 09-Jul-01 stefan.roese@esd-electronics.com - * - PCI host now configures from device 0 (not 1) to max_dev, - * (host configures itself) - * - On CPCI-405 pci base address and size is generated from - * SDRAM and FLASH size (CFG regs not used anymore) - * - Some minor changes for CPCI-405-A (adapter version) - * 14-Sep-01 stefan.roese@esd-electronics.com - * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup - * 28-Sep-01 stefan.roese@esd-electronics.com - * - Changed pci master configuration for linux compatibility - * (no need for bios_fixup() anymore) - * 26-Feb-02 stefan.roese@esd-electronics.com - * - Bug fixed in pci configuration (Andrew May) - * - Removed pci class code init for CPCI405 board - * 15-May-02 stefan.roese@esd-electronics.com - * - New vga device handling - * 29-May-02 stefan.roese@esd-electronics.com - * - PCI class code init added (if defined) - *----------------------------------------------------------------------------*/ - -#include -#include -#if !defined(CONFIG_440) -#include <405gp_pci.h> -#endif -#include -#include - -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) - -#ifdef CONFIG_PCI - -/*#define DEBUG*/ - -/*-----------------------------------------------------------------------------+ - * pci_init. Initializes the 405GP PCI Configuration regs. - *-----------------------------------------------------------------------------*/ -void pci_405gp_init(struct pci_controller *hose) -{ - DECLARE_GLOBAL_DATA_PTR; - - int i, reg_num = 0; - bd_t *bd = gd->bd; - - unsigned short temp_short; - unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI}; -#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) - unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart}; - unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1}; - char *ptmla_str, *ptmms_str; -#else - unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA}; - unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS}; -#endif -#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) - unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; - unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; - unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0}; - unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0}; -#else - unsigned long pmmla[3] = {0x80000000, 0,0}; - unsigned long pmmma[3] = {0xC0000001, 0,0}; - unsigned long pmmpcila[3] = {0x80000000, 0,0}; - unsigned long pmmpciha[3] = {0x00000000, 0,0}; -#endif -#ifdef CONFIG_PCI_PNP -#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) - char *s; -#endif -#endif - -#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) - ptmla_str = getenv("ptm1la"); - ptmms_str = getenv("ptm1ms"); - if(NULL != ptmla_str && NULL != ptmms_str ) { - ptmla[0] = simple_strtoul (ptmla_str, NULL, 16); - ptmms[0] = simple_strtoul (ptmms_str, NULL, 16); - } - - ptmla_str = getenv("ptm2la"); - ptmms_str = getenv("ptm2ms"); - if(NULL != ptmla_str && NULL != ptmms_str ) { - ptmla[1] = simple_strtoul (ptmla_str, NULL, 16); - ptmms[1] = simple_strtoul (ptmms_str, NULL, 16); - } -#endif - - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + reg_num++, - MIN_PCI_PCI_IOADDR, - MIN_PLB_PCI_IOADDR, - 0x10000, - PCI_REGION_IO); - - /* PCI I/O space */ - pci_set_region(hose->regions + reg_num++, - 0x00800000, - 0xe8800000, - 0x03800000, - PCI_REGION_IO); - - reg_num = 2; - - /* Memory spaces */ - for (i=0; i<2; i++) - if (ptmms[i] & 1) - { - if (!i) hose->pci_fb = hose->regions + reg_num; - - pci_set_region(hose->regions + reg_num++, - ptmpcila[i], ptmla[i], - ~(ptmms[i] & 0xfffff000) + 1, - PCI_REGION_MEM | - PCI_REGION_MEMORY); - } - - /* PCI memory spaces */ - for (i=0; i<3; i++) - if (pmmma[i] & 1) - { - pci_set_region(hose->regions + reg_num++, - pmmpcila[i], pmmla[i], - ~(pmmma[i] & 0xfffff000) + 1, - PCI_REGION_MEM); - } - - hose->region_count = reg_num; - - pci_setup_indirect(hose, - PCICFGADR, - PCICFGDATA); - - if (hose->pci_fb) - pciauto_region_init(hose->pci_fb); - - pci_register_hose(hose); - - /*--------------------------------------------------------------------------+ - * 405GP PCI Master configuration. - * Map one 512 MB range of PLB/processor addresses to PCI memory space. - * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF - * Use byte reversed out routines to handle endianess. - *--------------------------------------------------------------------------*/ - out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */ - out32r(PMM0LA, pmmla[0]); - out32r(PMM0PCILA, pmmpcila[0]); - out32r(PMM0PCIHA, pmmpciha[0]); - out32r(PMM0MA, pmmma[0]); - - /*--------------------------------------------------------------------------+ - * PMM1 is not used. Initialize them to zero. - *--------------------------------------------------------------------------*/ - out32r(PMM1MA, (pmmma[1]&~0x1)); - out32r(PMM1LA, pmmla[1]); - out32r(PMM1PCILA, pmmpcila[1]); - out32r(PMM1PCIHA, pmmpciha[1]); - out32r(PMM1MA, pmmma[1]); - - /*--------------------------------------------------------------------------+ - * PMM2 is not used. Initialize them to zero. - *--------------------------------------------------------------------------*/ - out32r(PMM2MA, (pmmma[2]&~0x1)); - out32r(PMM2LA, pmmla[2]); - out32r(PMM2PCILA, pmmpcila[2]); - out32r(PMM2PCIHA, pmmpciha[2]); - out32r(PMM2MA, pmmma[2]); - - /*--------------------------------------------------------------------------+ - * 405GP PCI Target configuration. (PTM1) - * Note: PTM1MS is hardwire enabled but we set the enable bit anyway. - *--------------------------------------------------------------------------*/ - out32r(PTM1LA, ptmla[0]); /* insert address */ - out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */ - pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]); - - /*--------------------------------------------------------------------------+ - * 405GP PCI Target configuration. (PTM2) - *--------------------------------------------------------------------------*/ - out32r(PTM2LA, ptmla[1]); /* insert address */ - pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]); - - if (ptmms[1] == 0) - { - out32r(PTM2MS, 0x00000001); /* set enable bit */ - pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000); - out32r(PTM2MS, 0x00000000); /* disable */ - } - else - { - out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */ - } - - /* - * Insert Subsystem Vendor and Device ID - */ - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); -#ifdef CONFIG_CPCI405 - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); - else - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2); -#else - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); -#endif - - /* - * Insert Class-code - */ -#ifdef CFG_PCI_CLASSCODE - pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE); -#endif /* CFG_PCI_CLASSCODE */ - - /*--------------------------------------------------------------------------+ - * If PCI speed = 66Mhz, set 66Mhz capable bit. - *--------------------------------------------------------------------------*/ - if (bd->bi_pci_busfreq >= 66000000) { - pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short); - pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ)); - } - -#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER) -#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) - if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || - (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) -#endif - { - /*--------------------------------------------------------------------------+ - * Write the 405GP PCI Configuration regs. - * Enable 405GP to be a master on the PCI bus (PMM). - * Enable 405GP to act as a PCI memory target (PTM). - *--------------------------------------------------------------------------*/ - pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short); - pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short | - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - } -#endif - -#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */ - pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */ -#endif - - /* - * Set HCE bit (Host Configuration Enabled) - */ - pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short); - pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001)); - -#ifdef CONFIG_PCI_PNP - /*--------------------------------------------------------------------------+ - * Scan the PCI bus and configure devices found. - *--------------------------------------------------------------------------*/ -#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) - if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || - (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) -#endif - { -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - - hose->last_busno = pci_hose_scan(hose); - } -#endif /* CONFIG_PCI_PNP */ - -} - -/* - * drivers/pci.c skips every host bridge but the 405GP since it could - * be set as an Adapter. - * - * I (Andrew May) don't know what we should do here, but I don't want - * the auto setup of a PCI device disabling what is done pci_405gp_init - * as has happened before. - */ -void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *entry) -{ -#ifdef DEBUG - printf("405gp_setup_bridge\n"); -#endif -} - -/* - * - */ - -void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line = 0xff; - - /* - * Write pci interrupt line register (cpci405 specific) - */ - switch (PCI_DEV(dev) & 0x03) - { - case 0: - int_line = 27 + 2; - break; - case 1: - int_line = 27 + 3; - break; - case 2: - int_line = 27 + 0; - break; - case 3: - int_line = 27 + 1; - break; - } - - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); -} - -void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *entry) -{ - unsigned int cmdstat = 0; - - pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); - - /* always enable io space on vga boards */ - pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); - cmdstat |= PCI_COMMAND_IO; - pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); -} - -#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) - -/* - *As is these functs get called out of flash Not a horrible - *thing, but something to keep in mind. (no statics?) - */ -static struct pci_config_table pci_405gp_config_table[] = { -/*if VendID is 0 it terminates the table search (ie Walnut)*/ -#ifdef CFG_PCI_SUBSYS_VENDORID - {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge}, -#endif - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, - - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, - - { } -}; - -static struct pci_controller hose = { - fixup_irq: pci_405gp_fixup_irq, - config_table: pci_405gp_config_table, -}; - -void pci_init_board(void) -{ - /*we want the ptrs to RAM not flash (ie don't use init list)*/ - hose.fixup_irq = pci_405gp_fixup_irq; - hose.config_table = pci_405gp_config_table; - pci_405gp_init(&hose); -} - -#endif - -#endif /* CONFIG_PCI */ - -#endif /* CONFIG_405GP */ - -/*-----------------------------------------------------------------------------+ - * CONFIG_440 - *-----------------------------------------------------------------------------*/ -#if defined(CONFIG_440) && defined(CONFIG_PCI) - -static struct pci_controller ppc440_hose = {0}; - - -void pci_440_init (struct pci_controller *hose) -{ - int reg_num = 0; - -#ifndef CONFIG_DISABLE_PISE_TEST - /*--------------------------------------------------------------------------+ - * The PCI initialization sequence enable bit must be set ... if not abort - * pci setup since updating the bit requires chip reset. - *--------------------------------------------------------------------------*/ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) - unsigned long strap; - - mfsdr(sdr_sdstp1,strap); - if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { - printf("PCI: SDR0_STRP1[PISE] not set.\n"); - printf("PCI: Configuration aborted.\n"); - return; - } -#elif defined(CONFIG_440GP) - unsigned long strap; - - strap = mfdcr(cpc0_strp1); - if ((strap & CPC0_STRP1_PISE_MASK) == 0) { - printf("PCI: CPC0_STRP1[PISE] not set.\n"); - printf("PCI: Configuration aborted.\n"); - return; - } -#endif -#endif /* CONFIG_DISABLE_PISE_TEST */ - - /*--------------------------------------------------------------------------+ - * PCI controller init - *--------------------------------------------------------------------------*/ - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + reg_num++, - 0x00000000, - PCIX0_IOBASE, - 0x10000, - PCI_REGION_IO); - - pci_set_region(hose->regions + reg_num++, - CFG_PCI_TARGBASE, - CFG_PCI_MEMBASE, - 0x10000000, - PCI_REGION_MEM ); - hose->region_count = reg_num; - - pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); - -#if defined(CFG_PCI_PRE_INIT) - /* Let board change/modify hose & do initial checks */ - if (pci_pre_init (hose) == 0) { - printf("PCI: Board-specific initialization failed.\n"); - printf("PCI: Configuration aborted.\n"); - return; - } -#endif - - pci_register_hose( hose ); - - /*--------------------------------------------------------------------------+ - * PCI target init - *--------------------------------------------------------------------------*/ -#if defined(CFG_PCI_TARGET_INIT) - pci_target_init(hose); /* Let board setup pci target */ -#else - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID ); - out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ -#endif - -#if defined(CONFIG_440GX) - out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ - out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ -#elif defined(PCIX0_BRDGOPT1) - out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ - out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ -#endif - - /*--------------------------------------------------------------------------+ - * PCI master init: default is one 256MB region for PCI memory: - * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE - *--------------------------------------------------------------------------*/ -#if defined(CFG_PCI_MASTER_INIT) - pci_master_init(hose); /* Let board setup pci master */ -#else - out32r( PCIX0_POM0SA, 0 ); /* disable */ - out32r( PCIX0_POM1SA, 0 ); /* disable */ - out32r( PCIX0_POM2SA, 0 ); /* disable */ - out32r( PCIX0_POM0LAL, 0x00000000 ); - out32r( PCIX0_POM0LAH, 0x00000003 ); - out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE ); - out32r( PCIX0_POM0PCIAH, 0x00000000 ); - out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ - out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); -#endif - - /*--------------------------------------------------------------------------+ - * PCI host configuration -- we don't make any assumptions here ... the - * _board_must_indicate_ what to do -- there's just too many runtime - * scenarios in environments like cPCI, PPMC, etc. to make a determination - * based on hard-coded values or state of arbiter enable. - *--------------------------------------------------------------------------*/ - if (is_pci_host(hose)) { -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif -#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) - out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); -#endif - hose->last_busno = pci_hose_scan(hose); - } -} - - -void pci_init_board(void) -{ - pci_440_init (&ppc440_hose); -} - -#endif /* CONFIG_440 & CONFIG_PCI */ diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c deleted file mode 100644 index 86dc2d0..0000000 --- a/cpu/ppc4xx/4xx_enet.c +++ /dev/null @@ -1,1564 +0,0 @@ -/*-----------------------------------------------------------------------------+ - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *-----------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------+ - * - * File Name: enetemac.c - * - * Function: Device driver for the ethernet EMAC3 macro on the 405GP. - * - * Author: Mark Wisner - * - * Change Activity- - * - * Date Description of Change BY - * --------- --------------------- --- - * 05-May-99 Created MKW - * 27-Jun-99 Clean up JWB - * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW - * 29-Jul-99 Added Full duplex support MKW - * 06-Aug-99 Changed names for Mal CR reg MKW - * 23-Aug-99 Turned off SYE when running at 10Mbs MKW - * 24-Aug-99 Marked descriptor empty after call_xlc MKW - * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG - * to avoid chaining maximum sized packets. Push starting - * RX descriptor address up to the next cache line boundary. - * 16-Jan-00 Added support for booting with IP of 0x0 MKW - * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the - * EMAC_RXM register. JWB - * 12-Mar-01 anne-sophie.harnois@nextream.fr - * - Variables are compatible with those already defined in - * include/net.h - * - Receive buffer descriptor ring is used to send buffers - * to the user - * - Info print about send/received/handled packet number if - * INFO_405_ENET is set - * 17-Apr-01 stefan.roese@esd-electronics.com - * - MAL reset in "eth_halt" included - * - Enet speed and duplex output now in one line - * 08-May-01 stefan.roese@esd-electronics.com - * - MAL error handling added (eth_init called again) - * 13-Nov-01 stefan.roese@esd-electronics.com - * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex - * 04-Jan-02 stefan.roese@esd-electronics.com - * - Wait for PHY auto negotiation to complete added - * 06-Feb-02 stefan.roese@esd-electronics.com - * - Bug fixed in waiting for auto negotiation to complete - * 26-Feb-02 stefan.roese@esd-electronics.com - * - rx and tx buffer descriptors now allocated (no fixed address - * used anymore) - * 17-Jun-02 stefan.roese@esd-electronics.com - * - MAL error debug printf 'M' removed (rx de interrupt may - * occur upon many incoming packets with only 4 rx buffers). - *-----------------------------------------------------------------------------* - * 17-Nov-03 travis.sawyer@sandburst.com - * - ported from 405gp_enet.c to utilized upto 4 EMAC ports - * in the 440GX. This port should work with the 440GP - * (2 EMACs) also - * 15-Aug-05 sr@denx.de - * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c - now handling all 4xx cpu's. - *-----------------------------------------------------------------------------*/ - -#include -#include -#include -#include -#include -#include -#include -#include <405_mal.h> -#include -#include -#include "vecnum.h" - -/* - * Only compile for platform with AMCC EMAC ethernet controller and - * network support enabled. - * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller! - */ -#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) - -#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) -#error "CONFIG_MII has to be defined!" -#endif - -#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI) -#error "CONFIG_NET_MULTI has to be defined for NetConsole" -#endif - -#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ -#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ - -/* Ethernet Transmit and Receive Buffers */ -/* AS.HARNOIS - * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from - * PKTSIZE and PKTSIZE_ALIGN (include/net.h) - */ -#define ENET_MAX_MTU PKTSIZE -#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN - -/*-----------------------------------------------------------------------------+ - * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal - * Interrupt Controller). - *-----------------------------------------------------------------------------*/ -#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) -#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) -#define EMAC_UIC_DEF UIC_ENET -#define EMAC_UIC_DEF1 UIC_ENET1 -#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET ) - -#undef INFO_4XX_ENET - -#define BI_PHYMODE_NONE 0 -#define BI_PHYMODE_ZMII 1 -#define BI_PHYMODE_RGMII 2 - - -/*-----------------------------------------------------------------------------+ - * Global variables. TX and RX descriptors and buffers. - *-----------------------------------------------------------------------------*/ -/* IER globals */ -static uint32_t mal_ier; - -#if !defined(CONFIG_NET_MULTI) -struct eth_device *emac0_dev = NULL; -#endif - -/* - * Get count of EMAC devices (doesn't have to be the max. possible number - * supported by the cpu) - */ -#if defined(CONFIG_HAS_ETH3) -#define LAST_EMAC_NUM 4 -#elif defined(CONFIG_HAS_ETH2) -#define LAST_EMAC_NUM 3 -#elif defined(CONFIG_HAS_ETH1) -#define LAST_EMAC_NUM 2 -#else -#define LAST_EMAC_NUM 1 -#endif - -/*-----------------------------------------------------------------------------+ - * Prototypes and externals. - *-----------------------------------------------------------------------------*/ -static void enet_rcv (struct eth_device *dev, unsigned long malisr); - -int enetInt (struct eth_device *dev); -static void mal_err (struct eth_device *dev, unsigned long isr, - unsigned long uic, unsigned long maldef, - unsigned long mal_errr); -static void emac_err (struct eth_device *dev, unsigned long isr); - -extern int phy_setup_aneg (char *devname, unsigned char addr); -extern int emac4xx_miiphy_read (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -extern int emac4xx_miiphy_write (char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -/*-----------------------------------------------------------------------------+ -| ppc_4xx_eth_halt -| Disable MAL channel, and EMACn -+-----------------------------------------------------------------------------*/ -static void ppc_4xx_eth_halt (struct eth_device *dev) -{ - EMAC_4XX_HW_PST hw_p = dev->priv; - uint32_t failsafe = 10000; - - out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ - - /* 1st reset MAL channel */ - /* Note: writing a 0 to a channel has no effect */ -#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); -#else - mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum)); -#endif - mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); - - /* wait for reset */ - while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { - udelay (1000); /* Delay 1 MS so as not to hammer the register */ - failsafe--; - if (failsafe == 0) - break; - } - - /* EMAC RESET */ - out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); - -#ifndef CONFIG_NETCONSOLE - hw_p->print_speed = 1; /* print speed message again next time */ -#endif - - return; -} - -#if defined (CONFIG_440GX) -int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) -{ - unsigned long pfc1; - unsigned long zmiifer; - unsigned long rmiifer; - - mfsdr(sdr_pfc1, pfc1); - pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); - - zmiifer = 0; - rmiifer = 0; - - switch (pfc1) { - case 1: - zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); - zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); - zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); - zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); - bis->bi_phymode[0] = BI_PHYMODE_ZMII; - bis->bi_phymode[1] = BI_PHYMODE_ZMII; - bis->bi_phymode[2] = BI_PHYMODE_ZMII; - bis->bi_phymode[3] = BI_PHYMODE_ZMII; - break; - case 2: - zmiifer = ZMII_FER_SMII << ZMII_FER_V(0); - zmiifer = ZMII_FER_SMII << ZMII_FER_V(1); - zmiifer = ZMII_FER_SMII << ZMII_FER_V(2); - zmiifer = ZMII_FER_SMII << ZMII_FER_V(3); - bis->bi_phymode[0] = BI_PHYMODE_ZMII; - bis->bi_phymode[1] = BI_PHYMODE_ZMII; - bis->bi_phymode[2] = BI_PHYMODE_ZMII; - bis->bi_phymode[3] = BI_PHYMODE_ZMII; - break; - case 3: - zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); - rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); - bis->bi_phymode[0] = BI_PHYMODE_ZMII; - bis->bi_phymode[1] = BI_PHYMODE_NONE; - bis->bi_phymode[2] = BI_PHYMODE_RGMII; - bis->bi_phymode[3] = BI_PHYMODE_NONE; - break; - case 4: - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); - rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2); - rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3); - bis->bi_phymode[0] = BI_PHYMODE_ZMII; - bis->bi_phymode[1] = BI_PHYMODE_ZMII; - bis->bi_phymode[2] = BI_PHYMODE_RGMII; - bis->bi_phymode[3] = BI_PHYMODE_RGMII; - break; - case 5: - zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); - zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); - zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2); - rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); - bis->bi_phymode[0] = BI_PHYMODE_ZMII; - bis->bi_phymode[1] = BI_PHYMODE_ZMII; - bis->bi_phymode[2] = BI_PHYMODE_ZMII; - bis->bi_phymode[3] = BI_PHYMODE_RGMII; - break; - case 6: - zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); - zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); - rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); - bis->bi_phymode[0] = BI_PHYMODE_ZMII; - bis->bi_phymode[1] = BI_PHYMODE_ZMII; - bis->bi_phymode[2] = BI_PHYMODE_RGMII; - break; - case 0: - default: - zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum); - rmiifer = 0x0; - bis->bi_phymode[0] = BI_PHYMODE_ZMII; - bis->bi_phymode[1] = BI_PHYMODE_ZMII; - bis->bi_phymode[2] = BI_PHYMODE_ZMII; - bis->bi_phymode[3] = BI_PHYMODE_ZMII; - break; - } - - /* Ensure we setup mdio for this devnum and ONLY this devnum */ - zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - - out32 (ZMII_FER, zmiifer); - out32 (RGMII_FER, rmiifer); - - return ((int)pfc1); - -} -#endif - -static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) -{ - int i, j; - unsigned long reg = 0; - unsigned long msr; - unsigned long speed; - unsigned long duplex; - unsigned long failsafe; - unsigned mode_reg; - unsigned short devnum; - unsigned short reg_short; -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) - sys_info_t sysinfo; -#if defined(CONFIG_440GX) - int ethgroup = -1; -#endif -#endif - - EMAC_4XX_HW_PST hw_p = dev->priv; - - /* before doing anything, figure out if we have a MAC address */ - /* if not, bail */ - if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) { - printf("ERROR: ethaddr not set!\n"); - return -1; - } - -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) - /* Need to get the OPB frequency so we can access the PHY */ - get_sys_info (&sysinfo); -#endif - - msr = mfmsr (); - mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ - - devnum = hw_p->devnum; - -#ifdef INFO_4XX_ENET - /* AS.HARNOIS - * We should have : - * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX - * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it - * is possible that new packets (without relationship with - * current transfer) have got the time to arrived before - * netloop calls eth_halt - */ - printf ("About preceeding transfer (eth%d):\n" - "- Sent packet number %d\n" - "- Received packet number %d\n" - "- Handled packet number %d\n", - hw_p->devnum, - hw_p->stats.pkts_tx, - hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); - - hw_p->stats.pkts_tx = 0; - hw_p->stats.pkts_rx = 0; - hw_p->stats.pkts_handled = 0; -#endif - - hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ - hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ - - hw_p->rx_slot = 0; /* MAL Receive Slot */ - hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ - hw_p->rx_u_index = 0; /* Receive User Queue Index */ - - hw_p->tx_slot = 0; /* MAL Transmit Slot */ - hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ - hw_p->tx_u_index = 0; /* Transmit User Queue Index */ - -#if defined(CONFIG_440) && !defined(CONFIG_440SP) - /* set RMII mode */ - /* NOTE: 440GX spec states that mode is mutually exclusive */ - /* NOTE: Therefore, disable all other EMACS, since we handle */ - /* NOTE: only one emac at a time */ - reg = 0; - out32 (ZMII_FER, 0); - udelay (100); - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) - out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); -#elif defined(CONFIG_440GX) - ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); -#elif defined(CONFIG_440GP) - /* set RMII mode */ - out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); -#else - if ((devnum == 0) || (devnum == 1)) { - out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); - } - else { /* ((devnum == 2) || (devnum == 3)) */ - out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); - out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | - (RGMII_FER_RGMII << RGMII_FER_V (3)))); - } -#endif - - out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); -#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ - - __asm__ volatile ("eieio"); - - /* reset emac so we have access to the phy */ - - out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); - __asm__ volatile ("eieio"); - - failsafe = 1000; - while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { - udelay (1000); - failsafe--; - } - -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) - /* Whack the M1 register */ - mode_reg = 0x0; - mode_reg &= ~0x00000038; - if (sysinfo.freqOPB <= 50000000); - else if (sysinfo.freqOPB <= 66666667) - mode_reg |= EMAC_M1_OBCI_66; - else if (sysinfo.freqOPB <= 83333333) - mode_reg |= EMAC_M1_OBCI_83; - else if (sysinfo.freqOPB <= 100000000) - mode_reg |= EMAC_M1_OBCI_100; - else - mode_reg |= EMAC_M1_OBCI_GT100; - - out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); -#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ - - /* wait for PHY to complete auto negotiation */ - reg_short = 0; -#ifndef CONFIG_CS8952_PHY - switch (devnum) { - case 0: - reg = CONFIG_PHY_ADDR; - break; -#if defined (CONFIG_PHY1_ADDR) - case 1: - reg = CONFIG_PHY1_ADDR; - break; -#endif -#if defined (CONFIG_440GX) - case 2: - reg = CONFIG_PHY2_ADDR; - break; - case 3: - reg = CONFIG_PHY3_ADDR; - break; -#endif - default: - reg = CONFIG_PHY_ADDR; - break; - } - - bis->bi_phynum[devnum] = reg; - -#if defined(CONFIG_PHY_RESET) - /* - * Reset the phy, only if its the first time through - * otherwise, just check the speeds & feeds - */ - if (hw_p->first_init == 0) { - miiphy_reset (dev->name, reg); - -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) -#if defined(CONFIG_CIS8201_PHY) - /* - * Cicada 8201 PHY needs to have an extended register whacked - * for RGMII mode. - */ - if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) { -#if defined(CONFIG_CIS8201_SHORT_ETCH) - miiphy_write (dev->name, reg, 23, 0x1300); -#else - miiphy_write (dev->name, reg, 23, 0x1000); -#endif - /* - * Vitesse VSC8201/Cicada CIS8201 errata: - * Interoperability problem with Intel 82547EI phys - * This work around (provided by Vitesse) changes - * the default timer convergence from 8ms to 12ms - */ - miiphy_write (dev->name, reg, 0x1f, 0x2a30); - miiphy_write (dev->name, reg, 0x08, 0x0200); - miiphy_write (dev->name, reg, 0x1f, 0x52b5); - miiphy_write (dev->name, reg, 0x02, 0x0004); - miiphy_write (dev->name, reg, 0x01, 0x0671); - miiphy_write (dev->name, reg, 0x00, 0x8fae); - miiphy_write (dev->name, reg, 0x1f, 0x2a30); - miiphy_write (dev->name, reg, 0x08, 0x0000); - miiphy_write (dev->name, reg, 0x1f, 0x0000); - /* end Vitesse/Cicada errata */ - } -#endif -#endif - /* Start/Restart autonegotiation */ - phy_setup_aneg (dev->name, reg); - udelay (1000); - } -#endif /* defined(CONFIG_PHY_RESET) */ - - miiphy_read (dev->name, reg, PHY_BMSR, ®_short); - - /* - * Wait if PHY is capable of autonegotiation and autonegotiation is not complete - */ - if ((reg_short & PHY_BMSR_AUTN_ABLE) - && !(reg_short & PHY_BMSR_AUTN_COMP)) { - puts ("Waiting for PHY auto negotiation to complete"); - i = 0; - while (!(reg_short & PHY_BMSR_AUTN_COMP)) { - /* - * Timeout reached ? - */ - if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts (" TIMEOUT !\n"); - break; - } - - if ((i++ % 1000) == 0) { - putc ('.'); - } - udelay (1000); /* 1 ms */ - miiphy_read (dev->name, reg, PHY_BMSR, ®_short); - - } - puts (" done\n"); - udelay (500000); /* another 500 ms (results in faster booting) */ - } -#endif /* #ifndef CONFIG_CS8952_PHY */ - - speed = miiphy_speed (dev->name, reg); - duplex = miiphy_duplex (dev->name, reg); - - if (hw_p->print_speed) { - hw_p->print_speed = 0; - printf ("ENET Speed is %d Mbps - %s duplex connection\n", - (int) speed, (duplex == HALF) ? "HALF" : "FULL"); - } - -#if defined(CONFIG_440) && !defined(CONFIG_440SP) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) - mfsdr(sdr_mfr, reg); - if (speed == 100) { - reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; - } else { - reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; - } - mtsdr(sdr_mfr, reg); -#endif - - /* Set ZMII/RGMII speed according to the phy link speed */ - reg = in32 (ZMII_SSR); - if ( (speed == 100) || (speed == 1000) ) - out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); - else - out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); - - if ((devnum == 2) || (devnum == 3)) { - if (speed == 1000) - reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); - else if (speed == 100) - reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); - else - reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); - - out32 (RGMII_SSR, reg); - } -#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ - - /* set the Mal configuration reg */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | - MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); -#else - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); - /* Errata 1.12: MAL_1 -- Disable MAL bursting */ - if (get_pvr() == PVR_440GP_RB) { - mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); - } -#endif - - /* Free "old" buffers */ - if (hw_p->alloc_tx_buf) - free (hw_p->alloc_tx_buf); - if (hw_p->alloc_rx_buf) - free (hw_p->alloc_rx_buf); - - /* - * Malloc MAL buffer desciptors, make sure they are - * aligned on cache line boundary size - * (401/403/IOP480 = 16, 405 = 32) - * and doesn't cross cache block boundaries. - */ - hw_p->alloc_tx_buf = - (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) + - ((2 * CFG_CACHELINE_SIZE) - 2)); - if (NULL == hw_p->alloc_tx_buf) - return -1; - if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) { - hw_p->tx = - (mal_desc_t *) ((int) hw_p->alloc_tx_buf + - CFG_CACHELINE_SIZE - - ((int) hw_p-> - alloc_tx_buf & CACHELINE_MASK)); - } else { - hw_p->tx = hw_p->alloc_tx_buf; - } - - hw_p->alloc_rx_buf = - (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) + - ((2 * CFG_CACHELINE_SIZE) - 2)); - if (NULL == hw_p->alloc_rx_buf) { - free(hw_p->alloc_tx_buf); - hw_p->alloc_tx_buf = NULL; - return -1; - } - - if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) { - hw_p->rx = - (mal_desc_t *) ((int) hw_p->alloc_rx_buf + - CFG_CACHELINE_SIZE - - ((int) hw_p-> - alloc_rx_buf & CACHELINE_MASK)); - } else { - hw_p->rx = hw_p->alloc_rx_buf; - } - - for (i = 0; i < NUM_TX_BUFF; i++) { - hw_p->tx[i].ctrl = 0; - hw_p->tx[i].data_len = 0; - if (hw_p->first_init == 0) { - hw_p->txbuf_ptr = - (char *) malloc (ENET_MAX_MTU_ALIGNED); - if (NULL == hw_p->txbuf_ptr) { - free(hw_p->alloc_rx_buf); - free(hw_p->alloc_tx_buf); - hw_p->alloc_rx_buf = NULL; - hw_p->alloc_tx_buf = NULL; - for(j = 0; j < i; j++) { - free(hw_p->tx[i].data_ptr); - hw_p->tx[i].data_ptr = NULL; - } - } - } - hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; - if ((NUM_TX_BUFF - 1) == i) - hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; - hw_p->tx_run[i] = -1; -#if 0 - printf ("TX_BUFF %d @ 0x%08lx\n", i, - (ulong) hw_p->tx[i].data_ptr); -#endif - } - - for (i = 0; i < NUM_RX_BUFF; i++) { - hw_p->rx[i].ctrl = 0; - hw_p->rx[i].data_len = 0; - /* rx[i].data_ptr = (char *) &rx_buff[i]; */ - hw_p->rx[i].data_ptr = (char *) NetRxPackets[i]; - if ((NUM_RX_BUFF - 1) == i) - hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; - hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; - hw_p->rx_ready[i] = -1; -#if 0 - printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr); -#endif - } - - reg = 0x00000000; - - reg |= dev->enetaddr[0]; /* set high address */ - reg = reg << 8; - reg |= dev->enetaddr[1]; - - out32 (EMAC_IAH + hw_p->hw_addr, reg); - - reg = 0x00000000; - reg |= dev->enetaddr[2]; /* set low address */ - reg = reg << 8; - reg |= dev->enetaddr[3]; - reg = reg << 8; - reg |= dev->enetaddr[4]; - reg = reg << 8; - reg |= dev->enetaddr[5]; - - out32 (EMAC_IAL + hw_p->hw_addr, reg); - - switch (devnum) { - case 1: - /* setup MAL tx & rx channel pointers */ -#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) - mtdcr (maltxctp2r, hw_p->tx); -#else - mtdcr (maltxctp1r, hw_p->tx); -#endif -#if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); -#endif - mtdcr (malrxctp1r, hw_p->rx); - /* set RX buffer size */ - mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); - break; -#if defined (CONFIG_440GX) - case 2: - /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp2r, hw_p->tx); - mtdcr (malrxctp2r, hw_p->rx); - /* set RX buffer size */ - mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); - break; - case 3: - /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (maltxctp3r, hw_p->tx); - mtdcr (malrxbattr, 0x0); - mtdcr (malrxctp3r, hw_p->rx); - /* set RX buffer size */ - mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); - break; -#endif /* CONFIG_440GX */ - case 0: - default: - /* setup MAL tx & rx channel pointers */ -#if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); -#endif - mtdcr (maltxctp0r, hw_p->tx); - mtdcr (malrxctp0r, hw_p->rx); - /* set RX buffer size */ - mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); - break; - } - - /* Enable MAL transmit and receive channels */ -#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); -#else - mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); -#endif - mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); - - /* set transmit enable & receive enable */ - out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); - - /* set receive fifo to 4k and tx fifo to 2k */ - mode_reg = in32 (EMAC_M1 + hw_p->hw_addr); - mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; - - /* set speed */ - if (speed == _1000BASET) { -#if defined(CONFIG_440SP) -#define SDR0_PFC1_EM_1000 0x00200000 - unsigned long pfc1; - mfsdr (sdr_pfc1, pfc1); - pfc1 |= SDR0_PFC1_EM_1000; - mtsdr (sdr_pfc1, pfc1); -#endif - mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; - } else if (speed == _100BASET) - mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; - else - mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ - if (duplex == FULL) - mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; - - out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); - - /* Enable broadcast and indvidual address */ - /* TBS: enabling runts as some misbehaved nics will send runts */ - out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); - - /* we probably need to set the tx mode1 reg? maybe at tx time */ - - /* set transmit request threshold register */ - out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ - - /* set receive low/high water mark register */ -#if defined(CONFIG_440) - /* 440GP has a 64 byte burst length */ - out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); -#else - /* 405s have a 16 byte burst length */ - out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); -#endif /* defined(CONFIG_440) */ - out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); - - /* Set fifo limit entry in tx mode 0 */ - out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003); - /* Frame gap set */ - out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); - - /* Set EMAC IER */ - hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; - if (speed == _100BASET) - hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; - - out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ - out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); - - if (hw_p->first_init == 0) { - /* - * Connect interrupt service routines - */ - irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2), - (interrupt_handler_t *) enetInt, dev); - } - - mtmsr (msr); /* enable interrupts again */ - - hw_p->bis = bis; - hw_p->first_init = 1; - - return (1); -} - - -static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, - int len) -{ - struct enet_frame *ef_ptr; - ulong time_start, time_now; - unsigned long temp_txm0; - EMAC_4XX_HW_PST hw_p = dev->priv; - - ef_ptr = (struct enet_frame *) ptr; - - /*-----------------------------------------------------------------------+ - * Copy in our address into the frame. - *-----------------------------------------------------------------------*/ - (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); - - /*-----------------------------------------------------------------------+ - * If frame is too long or too short, modify length. - *-----------------------------------------------------------------------*/ - /* TBS: where does the fragment go???? */ - if (len > ENET_MAX_MTU) - len = ENET_MAX_MTU; - - /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ - memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); - - /*-----------------------------------------------------------------------+ - * set TX Buffer busy, and send it - *-----------------------------------------------------------------------*/ - hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | - EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & - ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); - if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) - hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; - - hw_p->tx[hw_p->tx_slot].data_len = (short) len; - hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; - - __asm__ volatile ("eieio"); - - out32 (EMAC_TXM0 + hw_p->hw_addr, - in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); -#ifdef INFO_4XX_ENET - hw_p->stats.pkts_tx++; -#endif - - /*-----------------------------------------------------------------------+ - * poll unitl the packet is sent and then make sure it is OK - *-----------------------------------------------------------------------*/ - time_start = get_timer (0); - while (1) { - temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr); - /* loop until either TINT turns on or 3 seconds elapse */ - if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { - /* transmit is done, so now check for errors - * If there is an error, an interrupt should - * happen when we return - */ - time_now = get_timer (0); - if ((time_now - time_start) > 3000) { - return (-1); - } - } else { - return (len); - } - } -} - - -#if defined (CONFIG_440) - -#if defined(CONFIG_440SP) -/* - * Hack: On 440SP all enet irq sources are located on UIC1 - * Needs some cleanup. --sr - */ -#define UIC0MSR uic1msr -#define UIC0SR uic1sr -#else -#define UIC0MSR uic0msr -#define UIC0SR uic0sr -#endif - -int enetInt (struct eth_device *dev) -{ - int serviced; - int rc = -1; /* default to not us */ - unsigned long mal_isr; - unsigned long emac_isr = 0; - unsigned long mal_rx_eob; - unsigned long my_uic0msr, my_uic1msr; - -#if defined(CONFIG_440GX) - unsigned long my_uic2msr; -#endif - EMAC_4XX_HW_PST hw_p; - - /* - * Because the mal is generic, we need to get the current - * eth device - */ -#if defined(CONFIG_NET_MULTI) - dev = eth_get_dev(); -#else - dev = emac0_dev; -#endif - - hw_p = dev->priv; - - /* enter loop that stays in interrupt code until nothing to service */ - do { - serviced = 0; - - my_uic0msr = mfdcr (UIC0MSR); - my_uic1msr = mfdcr (uic1msr); -#if defined(CONFIG_440GX) - my_uic2msr = mfdcr (uic2msr); -#endif - if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) - && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) { - /* not for us */ - return (rc); - } -#if defined (CONFIG_440GX) - if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) - && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) { - /* not for us */ - return (rc); - } -#endif - /* get and clear controller status interrupts */ - /* look at Mal and EMAC interrupts */ - if ((my_uic0msr & (UIC_MRE | UIC_MTE)) - || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { - /* we have a MAL interrupt */ - mal_isr = mfdcr (malesr); - /* look for mal error */ - if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) { - mal_err (dev, mal_isr, my_uic0msr, - MAL_UIC_DEF, MAL_UIC_ERR); - serviced = 1; - rc = 0; - } - } - - /* port by port dispatch of emac interrupts */ - if (hw_p->devnum == 0) { - if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); - if ((hw_p->emac_ier & emac_isr) != 0) { - emac_err (dev, emac_isr); - serviced = 1; - rc = 0; - } - } - if ((hw_p->emac_ier & emac_isr) - || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { - mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - return (rc); /* we had errors so get out */ - } - } - -#if !defined(CONFIG_440SP) - if (hw_p->devnum == 1) { - if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); - if ((hw_p->emac_ier & emac_isr) != 0) { - emac_err (dev, emac_isr); - serviced = 1; - rc = 0; - } - } - if ((hw_p->emac_ier & emac_isr) - || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { - mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - return (rc); /* we had errors so get out */ - } - } -#if defined (CONFIG_440GX) - if (hw_p->devnum == 2) { - if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); - if ((hw_p->emac_ier & emac_isr) != 0) { - emac_err (dev, emac_isr); - serviced = 1; - rc = 0; - } - } - if ((hw_p->emac_ier & emac_isr) - || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { - mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - mtdcr (uic2sr, UIC_ETH2); - return (rc); /* we had errors so get out */ - } - } - - if (hw_p->devnum == 3) { - if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); - if ((hw_p->emac_ier & emac_isr) != 0) { - emac_err (dev, emac_isr); - serviced = 1; - rc = 0; - } - } - if ((hw_p->emac_ier & emac_isr) - || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { - mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - mtdcr (uic2sr, UIC_ETH3); - return (rc); /* we had errors so get out */ - } - } -#endif /* CONFIG_440GX */ -#endif /* !CONFIG_440SP */ - - /* handle MAX TX EOB interrupt from a tx */ - if (my_uic0msr & UIC_MTE) { - mal_rx_eob = mfdcr (maltxeobisr); - mtdcr (maltxeobisr, mal_rx_eob); - mtdcr (UIC0SR, UIC_MTE); - } - /* handle MAL RX EOB interupt from a receive */ - /* check for EOB on valid channels */ - if (my_uic0msr & UIC_MRE) { - mal_rx_eob = mfdcr (malrxeobisr); - if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ - /* clear EOB - mtdcr(malrxeobisr, mal_rx_eob); */ - enet_rcv (dev, emac_isr); - /* indicate that we serviced an interrupt */ - serviced = 1; - rc = 0; - } - } - - mtdcr (UIC0SR, UIC_MRE); /* Clear */ - mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - switch (hw_p->devnum) { - case 0: - mtdcr (uic1sr, UIC_ETH0); - break; - case 1: - mtdcr (uic1sr, UIC_ETH1); - break; -#if defined (CONFIG_440GX) - case 2: - mtdcr (uic2sr, UIC_ETH2); - break; - case 3: - mtdcr (uic2sr, UIC_ETH3); - break; -#endif /* CONFIG_440GX */ - default: - break; - } - } while (serviced); - - return (rc); -} - -#else /* CONFIG_440 */ - -int enetInt (struct eth_device *dev) -{ - int serviced; - int rc = -1; /* default to not us */ - unsigned long mal_isr; - unsigned long emac_isr = 0; - unsigned long mal_rx_eob; - unsigned long my_uicmsr; - - EMAC_4XX_HW_PST hw_p; - - /* - * Because the mal is generic, we need to get the current - * eth device - */ -#if defined(CONFIG_NET_MULTI) - dev = eth_get_dev(); -#else - dev = emac0_dev; -#endif - - hw_p = dev->priv; - - /* enter loop that stays in interrupt code until nothing to service */ - do { - serviced = 0; - - my_uicmsr = mfdcr (uicmsr); - - if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */ - return (rc); - } - /* get and clear controller status interrupts */ - /* look at Mal and EMAC interrupts */ - if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */ - mal_isr = mfdcr (malesr); - /* look for mal error */ - if ((my_uicmsr & MAL_UIC_ERR) != 0) { - mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR); - serviced = 1; - rc = 0; - } - } - - /* port by port dispatch of emac interrupts */ - - if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); - if ((hw_p->emac_ier & emac_isr) != 0) { - emac_err (dev, emac_isr); - serviced = 1; - rc = 0; - } - } - if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) { - mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */ - return (rc); /* we had errors so get out */ - } - - /* handle MAX TX EOB interrupt from a tx */ - if (my_uicmsr & UIC_MAL_TXEOB) { - mal_rx_eob = mfdcr (maltxeobisr); - mtdcr (maltxeobisr, mal_rx_eob); - mtdcr (uicsr, UIC_MAL_TXEOB); - } - /* handle MAL RX EOB interupt from a receive */ - /* check for EOB on valid channels */ - if (my_uicmsr & UIC_MAL_RXEOB) - { - mal_rx_eob = mfdcr (malrxeobisr); - if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ - /* clear EOB - mtdcr(malrxeobisr, mal_rx_eob); */ - enet_rcv (dev, emac_isr); - /* indicate that we serviced an interrupt */ - serviced = 1; - rc = 0; - } - } - mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ - } - while (serviced); - - return (rc); -} - -#endif /* CONFIG_440 */ - -/*-----------------------------------------------------------------------------+ - * MAL Error Routine - *-----------------------------------------------------------------------------*/ -static void mal_err (struct eth_device *dev, unsigned long isr, - unsigned long uic, unsigned long maldef, - unsigned long mal_errr) -{ - EMAC_4XX_HW_PST hw_p = dev->priv; - - mtdcr (malesr, isr); /* clear interrupt */ - - /* clear DE interrupt */ - mtdcr (maltxdeir, 0xC0000000); - mtdcr (malrxdeir, 0x80000000); - -#ifdef INFO_4XX_ENET - printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); -#endif - - eth_init (hw_p->bis); /* start again... */ -} - -/*-----------------------------------------------------------------------------+ - * EMAC Error Routine - *-----------------------------------------------------------------------------*/ -static void emac_err (struct eth_device *dev, unsigned long isr) -{ - EMAC_4XX_HW_PST hw_p = dev->priv; - - printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); - out32 (EMAC_ISR + hw_p->hw_addr, isr); -} - -/*-----------------------------------------------------------------------------+ - * enet_rcv() handles the ethernet receive data - *-----------------------------------------------------------------------------*/ -static void enet_rcv (struct eth_device *dev, unsigned long malisr) -{ - struct enet_frame *ef_ptr; - unsigned long data_len; - unsigned long rx_eob_isr; - EMAC_4XX_HW_PST hw_p = dev->priv; - - int handled = 0; - int i; - int loop_count = 0; - - rx_eob_isr = mfdcr (malrxeobisr); - if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) { - /* clear EOB */ - mtdcr (malrxeobisr, rx_eob_isr); - - /* EMAC RX done */ - while (1) { /* do all */ - i = hw_p->rx_slot; - - if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) - || (loop_count >= NUM_RX_BUFF)) - break; - loop_count++; - hw_p->rx_slot++; - if (NUM_RX_BUFF == hw_p->rx_slot) - hw_p->rx_slot = 0; - handled++; - data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */ - if (data_len) { - if (data_len > ENET_MAX_MTU) /* Check len */ - data_len = 0; - else { - if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ - data_len = 0; - hw_p->stats.rx_err_log[hw_p-> - rx_err_index] - = hw_p->rx[i].ctrl; - hw_p->rx_err_index++; - if (hw_p->rx_err_index == - MAX_ERR_LOG) - hw_p->rx_err_index = - 0; - } /* emac_erros */ - } /* data_len < max mtu */ - } /* if data_len */ - if (!data_len) { /* no data */ - hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ - - hw_p->stats.data_len_err++; /* Error at Rx */ - } - - /* !data_len */ - /* AS.HARNOIS */ - /* Check if user has already eaten buffer */ - /* if not => ERROR */ - else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { - if (hw_p->is_receiving) - printf ("ERROR : Receive buffers are full!\n"); - break; - } else { - hw_p->stats.rx_frames++; - hw_p->stats.rx += data_len; - ef_ptr = (struct enet_frame *) hw_p->rx[i]. - data_ptr; -#ifdef INFO_4XX_ENET - hw_p->stats.pkts_rx++; -#endif - /* AS.HARNOIS - * use ring buffer - */ - hw_p->rx_ready[hw_p->rx_i_index] = i; - hw_p->rx_i_index++; - if (NUM_RX_BUFF == hw_p->rx_i_index) - hw_p->rx_i_index = 0; - - /* AS.HARNOIS - * free receive buffer only when - * buffer has been handled (eth_rx) - rx[i].ctrl |= MAL_RX_CTRL_EMPTY; - */ - } /* if data_len */ - } /* while */ - } /* if EMACK_RXCHL */ -} - - -static int ppc_4xx_eth_rx (struct eth_device *dev) -{ - int length; - int user_index; - unsigned long msr; - EMAC_4XX_HW_PST hw_p = dev->priv; - - hw_p->is_receiving = 1; /* tell driver */ - - for (;;) { - /* AS.HARNOIS - * use ring buffer and - * get index from rx buffer desciptor queue - */ - user_index = hw_p->rx_ready[hw_p->rx_u_index]; - if (user_index == -1) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - msr = mfmsr (); - mtmsr (msr & ~(MSR_EE)); - - length = hw_p->rx[user_index].data_len; - - /* Pass the packet up to the protocol layers. */ - /* NetReceive(NetRxPackets[rxIdx], length - 4); */ - /* NetReceive(NetRxPackets[i], length); */ - NetReceive (NetRxPackets[user_index], length - 4); - /* Free Recv Buffer */ - hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; - /* Free rx buffer descriptor queue */ - hw_p->rx_ready[hw_p->rx_u_index] = -1; - hw_p->rx_u_index++; - if (NUM_RX_BUFF == hw_p->rx_u_index) - hw_p->rx_u_index = 0; - -#ifdef INFO_4XX_ENET - hw_p->stats.pkts_handled++; -#endif - - mtmsr (msr); /* Enable IRQ's */ - } - - hw_p->is_receiving = 0; /* tell driver */ - - return length; -} - -int ppc_4xx_eth_initialize (bd_t * bis) -{ - static int virgin = 0; - struct eth_device *dev; - int eth_num = 0; - EMAC_4XX_HW_PST hw = NULL; - -#if defined(CONFIG_440GX) - unsigned long pfc1; - - mfsdr (sdr_pfc1, pfc1); - pfc1 &= ~(0x01e00000); - pfc1 |= 0x01200000; - mtsdr (sdr_pfc1, pfc1); -#endif - /* set phy num and mode */ - bis->bi_phynum[0] = CONFIG_PHY_ADDR; -#if defined(CONFIG_PHY1_ADDR) - bis->bi_phynum[1] = CONFIG_PHY1_ADDR; -#endif -#if defined(CONFIG_440GX) - bis->bi_phynum[2] = CONFIG_PHY2_ADDR; - bis->bi_phynum[3] = CONFIG_PHY3_ADDR; - bis->bi_phymode[0] = 0; - bis->bi_phymode[1] = 0; - bis->bi_phymode[2] = 2; - bis->bi_phymode[3] = 2; - -#if defined (CONFIG_440GX) - ppc_4xx_eth_setup_bridge(0, bis); -#endif -#endif - - for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { - - /* See if we can actually bring up the interface, otherwise, skip it */ - switch (eth_num) { - default: /* fall through */ - case 0: - if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) { - bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; - continue; - } - break; -#ifdef CONFIG_HAS_ETH1 - case 1: - if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) { - bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; - continue; - } - break; -#endif -#ifdef CONFIG_HAS_ETH2 - case 2: - if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) { - bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; - continue; - } - break; -#endif -#ifdef CONFIG_HAS_ETH3 - case 3: - if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) { - bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; - continue; - } - break; -#endif - } - - /* Allocate device structure */ - dev = (struct eth_device *) malloc (sizeof (*dev)); - if (dev == NULL) { - printf ("ppc_4xx_eth_initialize: " - "Cannot allocate eth_device %d\n", eth_num); - return (-1); - } - memset(dev, 0, sizeof(*dev)); - - /* Allocate our private use data */ - hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw)); - if (hw == NULL) { - printf ("ppc_4xx_eth_initialize: " - "Cannot allocate private hw data for eth_device %d", - eth_num); - free (dev); - return (-1); - } - memset(hw, 0, sizeof(*hw)); - - switch (eth_num) { - default: /* fall through */ - case 0: - hw->hw_addr = 0; - memcpy (dev->enetaddr, bis->bi_enetaddr, 6); - break; -#ifdef CONFIG_HAS_ETH1 - case 1: - hw->hw_addr = 0x100; - memcpy (dev->enetaddr, bis->bi_enet1addr, 6); - break; -#endif -#ifdef CONFIG_HAS_ETH2 - case 2: - hw->hw_addr = 0x400; - memcpy (dev->enetaddr, bis->bi_enet2addr, 6); - break; -#endif -#ifdef CONFIG_HAS_ETH3 - case 3: - hw->hw_addr = 0x600; - memcpy (dev->enetaddr, bis->bi_enet3addr, 6); - break; -#endif - } - - hw->devnum = eth_num; - hw->print_speed = 1; - - sprintf (dev->name, "ppc_4xx_eth%d", eth_num); - dev->priv = (void *) hw; - dev->init = ppc_4xx_eth_init; - dev->halt = ppc_4xx_eth_halt; - dev->send = ppc_4xx_eth_send; - dev->recv = ppc_4xx_eth_rx; - - if (0 == virgin) { - /* set the MAL IER ??? names may change with new spec ??? */ - mal_ier = - MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | - MAL_IER_OPBE | MAL_IER_PLBE; - mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ - mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ - mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ - mtdcr (malier, mal_ier); - - /* install MAL interrupt handler */ - irq_install_handler (VECNUM_MS, - (interrupt_handler_t *) enetInt, - dev); - irq_install_handler (VECNUM_MTE, - (interrupt_handler_t *) enetInt, - dev); - irq_install_handler (VECNUM_MRE, - (interrupt_handler_t *) enetInt, - dev); - irq_install_handler (VECNUM_TXDE, - (interrupt_handler_t *) enetInt, - dev); - irq_install_handler (VECNUM_RXDE, - (interrupt_handler_t *) enetInt, - dev); - virgin = 1; - } - -#if defined(CONFIG_NET_MULTI) - eth_register (dev); -#else - emac0_dev = dev; -#endif -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) - miiphy_register (dev->name, - emac4xx_miiphy_read, emac4xx_miiphy_write); -#endif - - } /* end for each supported device */ - return (1); -} - - -#if !defined(CONFIG_NET_MULTI) -void eth_halt (void) { - if (emac0_dev) { - ppc_4xx_eth_halt(emac0_dev); - free(emac0_dev); - emac0_dev = NULL; - } -} - -int eth_init (bd_t *bis) -{ - ppc_4xx_eth_initialize(bis); - if (emac0_dev) { - return ppc_4xx_eth_init(emac0_dev, bis); - } else { - printf("ERROR: ethaddr not set!\n"); - return -1; - } -} - -int eth_send(volatile void *packet, int length) -{ - return (ppc_4xx_eth_send(emac0_dev, packet, length)); -} - -int eth_rx(void) -{ - return (ppc_4xx_eth_rx(emac0_dev)); -} - -int emac4xx_miiphy_initialize (bd_t * bis) -{ -#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) - miiphy_register ("ppc_4xx_eth0", - emac4xx_miiphy_read, emac4xx_miiphy_write); -#endif - - return 0; -} -#endif /* !defined(CONFIG_NET_MULTI) */ - -#endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile deleted file mode 100644 index c563457..0000000 --- a/cpu/ppc4xx/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o resetvec.o kgdb.o -AOBJS = dcr.o -COBJS = 405gp_pci.o 4xx_enet.o \ - bedbug_405.o commproc.o \ - cpu.o cpu_init.o i2c.o interrupts.o \ - miiphy.o sdram.o serial.o \ - spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o - -OBJS = $(AOBJS) $(COBJS) - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/ppc4xx/bedbug_405.c b/cpu/ppc4xx/bedbug_405.c deleted file mode 100644 index a3c2119..0000000 --- a/cpu/ppc4xx/bedbug_405.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * Bedbug Functions specific to the PPC405 chip - */ - -#include -#include -#include -#include -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_4xx) - -#define MAX_BREAK_POINTS 4 - -extern CPU_DEBUG_CTX bug_ctx; - -void bedbug405_init __P ((void)); -void bedbug405_do_break __P ((cmd_tbl_t *, int, int, char *[])); -void bedbug405_break_isr __P ((struct pt_regs *)); -int bedbug405_find_empty __P ((void)); -int bedbug405_set __P ((int, unsigned long)); -int bedbug405_clear __P ((int)); - - -/* ====================================================================== - * Initialize the global bug_ctx structure for the AMCC PPC405. Clear all - * of the breakpoints. - * ====================================================================== */ - -void bedbug405_init (void) -{ - int i; - - /* -------------------------------------------------- */ - - bug_ctx.hw_debug_enabled = 0; - bug_ctx.stopped = 0; - bug_ctx.current_bp = 0; - bug_ctx.regs = NULL; - - bug_ctx.do_break = bedbug405_do_break; - bug_ctx.break_isr = bedbug405_break_isr; - bug_ctx.find_empty = bedbug405_find_empty; - bug_ctx.set = bedbug405_set; - bug_ctx.clear = bedbug405_clear; - - for (i = 1; i <= MAX_BREAK_POINTS; ++i) - (*bug_ctx.clear) (i); - - puts ("BEDBUG:ready\n"); - return; -} /* bedbug_init_breakpoints */ - - - -/* ====================================================================== - * Set/clear/show one of the hardware breakpoints for the 405. The "off" - * string will disable a specific breakpoint. The "show" string will - * display the current breakpoints. Otherwise an address will set a - * breakpoint at that address. Setting a breakpoint uses the CPU-specific - * set routine which will assign a breakpoint number. - * ====================================================================== */ - -void bedbug405_do_break (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - long addr = 0; /* Address to break at */ - int which_bp; /* Breakpoint number */ - - /* -------------------------------------------------- */ - - if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); - return; - } - - /* Turn off a breakpoint */ - - if (strcmp (argv[1], "off") == 0) { - if (bug_ctx.hw_debug_enabled == 0) { - printf ("No breakpoints enabled\n"); - return; - } - - which_bp = simple_strtoul (argv[2], NULL, 10); - - if (bug_ctx.clear) - (*bug_ctx.clear) (which_bp); - - printf ("Breakpoint %d removed\n", which_bp); - return; - } - - /* Show a list of breakpoints */ - - if (strcmp (argv[1], "show") == 0) { - for (which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp) { - - switch (which_bp) { - case 1: - addr = GET_IAC1 (); - break; - case 2: - addr = GET_IAC2 (); - break; - case 3: - addr = GET_IAC3 (); - break; - case 4: - addr = GET_IAC4 (); - break; - } - - printf ("Breakpoint [%d]: ", which_bp); - if (addr == 0) - printf ("NOT SET\n"); - else - disppc ((unsigned char *) addr, 0, 1, bedbug_puts, - F_RADHEX); - } - return; - } - - /* Set a breakpoint at the address */ - - if (!isdigit (argv[1][0])) { - printf ("Usage:\n%s\n", cmdtp->usage); - return; - } - - addr = simple_strtoul (argv[1], NULL, 16) & 0xfffffffc; - - if ((bug_ctx.set) && (which_bp = (*bug_ctx.set) (0, addr)) > 0) { - printf ("Breakpoint [%d]: ", which_bp); - disppc ((unsigned char *) addr, 0, 1, bedbug_puts, F_RADHEX); - } - - return; -} /* bedbug405_do_break */ - - - -/* ====================================================================== - * Handle a breakpoint. First determine which breakpoint was hit by - * looking at the DeBug Status Register (DBSR), clear the breakpoint - * and enter a mini main loop. Stay in the loop until the stopped flag - * in the debug context is cleared. - * ====================================================================== */ - -void bedbug405_break_isr (struct pt_regs *regs) -{ - unsigned long dbsr_val; /* Value of the DBSR */ - unsigned long addr = 0; /* Address stopped at */ - - /* -------------------------------------------------- */ - - dbsr_val = GET_DBSR (); - - if (dbsr_val & DBSR_IA1) { - bug_ctx.current_bp = 1; - addr = GET_IAC1 (); - SET_DBSR (DBSR_IA1); /* Write a 1 to clear */ - } else if (dbsr_val & DBSR_IA2) { - bug_ctx.current_bp = 2; - addr = GET_IAC2 (); - SET_DBSR (DBSR_IA2); /* Write a 1 to clear */ - } else if (dbsr_val & DBSR_IA3) { - bug_ctx.current_bp = 3; - addr = GET_IAC3 (); - SET_DBSR (DBSR_IA3); /* Write a 1 to clear */ - } else if (dbsr_val & DBSR_IA4) { - bug_ctx.current_bp = 4; - addr = GET_IAC4 (); - SET_DBSR (DBSR_IA4); /* Write a 1 to clear */ - } - - bedbug_main_loop (addr, regs); - return; -} /* bedbug405_break_isr */ - - - -/* ====================================================================== - * Look through all of the hardware breakpoints available to see if one - * is unused. - * ====================================================================== */ - -int bedbug405_find_empty (void) -{ - /* -------------------------------------------------- */ - - if (GET_IAC1 () == 0) - return 1; - - if (GET_IAC2 () == 0) - return 2; - - if (GET_IAC3 () == 0) - return 3; - - if (GET_IAC4 () == 0) - return 4; - - return 0; -} /* bedbug405_find_empty */ - - - -/* ====================================================================== - * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint - * number, otherwise reassign the given breakpoint. If hardware debugging - * is not enabled, then turn it on via the MSR and DBCR0. Set the break - * address in the appropriate IACx register and enable proper address - * beakpoint in DBCR0. - * ====================================================================== */ - -int bedbug405_set (int which_bp, unsigned long addr) -{ - /* -------------------------------------------------- */ - - /* Only look if which_bp == 0, else use which_bp */ - if ((bug_ctx.find_empty) && (!which_bp) && - (which_bp = (*bug_ctx.find_empty) ()) == 0) { - printf ("All breakpoints in use\n"); - return 0; - } - - if (which_bp < 1 || which_bp > MAX_BREAK_POINTS) { - printf ("Invalid break point # %d\n", which_bp); - return 0; - } - - if (!bug_ctx.hw_debug_enabled) { - SET_MSR (GET_MSR () | 0x200); /* set MSR[ DE ] */ - SET_DBCR0 (GET_DBCR0 () | DBCR0_IDM); - bug_ctx.hw_debug_enabled = 1; - } - - switch (which_bp) { - case 1: - SET_IAC1 (addr); - SET_DBCR0 (GET_DBCR0 () | DBCR0_IA1); - break; - - case 2: - SET_IAC2 (addr); - SET_DBCR0 (GET_DBCR0 () | DBCR0_IA2); - break; - - case 3: - SET_IAC3 (addr); - SET_DBCR0 (GET_DBCR0 () | DBCR0_IA3); - break; - - case 4: - SET_IAC4 (addr); - SET_DBCR0 (GET_DBCR0 () | DBCR0_IA4); - break; - } - - return which_bp; -} /* bedbug405_set */ - - - -/* ====================================================================== - * Disable a specific breakoint by setting the appropriate IACx register - * to zero and claring the instruction address breakpoint in DBCR0. - * ====================================================================== */ - -int bedbug405_clear (int which_bp) -{ - /* -------------------------------------------------- */ - - if (which_bp < 1 || which_bp > MAX_BREAK_POINTS) { - printf ("Invalid break point # (%d)\n", which_bp); - return -1; - } - - switch (which_bp) { - case 1: - SET_IAC1 (0); - SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA1); - break; - - case 2: - SET_IAC2 (0); - SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA2); - break; - - case 3: - SET_IAC3 (0); - SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA3); - break; - - case 4: - SET_IAC4 (0); - SET_DBCR0 (GET_DBCR0 () & ~DBCR0_IA4); - break; - } - - return 0; -} /* bedbug405_clear */ - - -/* ====================================================================== */ -#endif diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c deleted file mode 100644 index 68aab5b..0000000 --- a/cpu/ppc4xx/commproc.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - * Atapted for ppc4XX by Denis Peter - */ - -#include -#include - - -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - -void post_word_store (ulong a) -{ - volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); - *(volatile ulong *) save_addr = a; -} - -ulong post_word_load (void) -{ - volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); - return *(volatile ulong *) save_addr; -} - -#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR); - - save_addr[0] = a; - save_addr[1] = BOOTCOUNT_MAGIC; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR); - - if (save_addr[1] != BOOTCOUNT_MAGIC) - return 0; - else - return save_addr[0]; -} - -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk deleted file mode 100644 index 119e061..0000000 --- a/cpu/ppc4xx/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing - -PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -Wa,-m405 -mcpu=405 -msoft-float diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c deleted file mode 100644 index a26533c..0000000 --- a/cpu/ppc4xx/cpu.c +++ /dev/null @@ -1,371 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - * - * written or collected and sometimes rewritten by - * Magnus Damm - * - * minor modifications by - * Wolfgang Denk - */ - -#include -#include -#include -#include -#include - - -#if defined(CONFIG_440) -#define FREQ_EBC (sys_info.freqEPB) -#else -#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv) -#endif - -#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - -#define PCI_ASYNC - -int pci_async_enabled(void) -{ -#if defined(CONFIG_405GP) - return (mfdcr(strap) & PSR_PCI_ASYNC_EN); -#endif - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) - unsigned long val; - - mfsdr(sdr_sdstp1, val); - return (val & SDR0_SDSTP1_PAME_MASK); -#endif -} -#endif - -#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405) -int pci_arbiter_enabled(void) -{ -#if defined(CONFIG_405GP) - return (mfdcr(strap) & PSR_PCI_ARBIT_EN); -#endif - -#if defined(CONFIG_405EP) - return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN); -#endif - -#if defined(CONFIG_440GP) - return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); -#endif - -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) - unsigned long val; - - mfsdr(sdr_sdstp1, val); - return (val & SDR0_SDSTP1_PAE_MASK); -#endif -} -#endif - -#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440GX) || defined(CONFIG_440SP) - -#define I2C_BOOTROM - -int i2c_bootrom_enabled(void) -{ -#if defined(CONFIG_405EP) - return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); -#endif - -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) - unsigned long val; - - mfsdr(sdr_sdcs, val); - return (val & SDR0_SDCS_SDD); -#endif -} -#endif - - -#if defined(CONFIG_440) -static int do_chip_reset(unsigned long sys0, unsigned long sys1); -#endif - - -int checkcpu (void) -{ -#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */ - DECLARE_GLOBAL_DATA_PTR; - uint pvr = get_pvr(); - ulong clock = gd->cpu_clk; - char buf[32]; - -#if !defined(CONFIG_IOP480) - sys_info_t sys_info; - - puts ("CPU: "); - - get_sys_info(&sys_info); - - puts("AMCC PowerPC 4"); - -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) - puts("05"); -#endif -#if defined(CONFIG_440) - puts("40"); -#endif - - switch (pvr) { - case PVR_405GP_RB: - puts("GP Rev. B"); - break; - - case PVR_405GP_RC: - puts("GP Rev. C"); - break; - - case PVR_405GP_RD: - puts("GP Rev. D"); - break; - -#ifdef CONFIG_405GP - case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ - puts("GP Rev. E"); - break; -#endif - - case PVR_405CR_RA: - puts("CR Rev. A"); - break; - - case PVR_405CR_RB: - puts("CR Rev. B"); - break; - -#ifdef CONFIG_405CR - case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ - puts("CR Rev. C"); - break; -#endif - - case PVR_405GPR_RB: - puts("GPr Rev. B"); - break; - - case PVR_405EP_RB: - puts("EP Rev. B"); - break; - -#if defined(CONFIG_440) - case PVR_440GP_RB: - puts("GP Rev. B"); - /* See errata 1.12: CHIP_4 */ - if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) || - (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){ - puts ( "\n\t CPC0_SYSx DCRs corrupted. " - "Resetting chip ...\n"); - udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ - do_chip_reset ( mfdcr(cpc0_strp0), - mfdcr(cpc0_strp1) ); - } - break; - - case PVR_440GP_RC: - puts("GP Rev. C"); - break; - - case PVR_440GX_RA: - puts("GX Rev. A"); - break; - - case PVR_440GX_RB: - puts("GX Rev. B"); - break; - - case PVR_440GX_RC: - puts("GX Rev. C"); - break; - - case PVR_440GX_RF: - puts("GX Rev. F"); - break; - - case PVR_440EP_RA: - puts("EP Rev. A"); - break; - -#ifdef CONFIG_440EP - case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */ - puts("EP Rev. B"); - break; -#endif /* CONFIG_440EP */ - -#ifdef CONFIG_440GR - case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */ - puts("GR Rev. A"); - break; -#endif /* CONFIG_440GR */ -#endif /* CONFIG_440 */ - - case PVR_440SP_RA: - puts("SP Rev. A"); - break; - - case PVR_440SP_RB: - puts("SP Rev. B"); - break; - - default: - printf (" UNKNOWN (PVR=%08x)", pvr); - break; - } - - printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), - sys_info.freqPLB / 1000000, - sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, - FREQ_EBC / 1000000); - -#if defined(I2C_BOOTROM) - printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); -#endif - -#if defined(CONFIG_PCI) - printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); -#endif - -#if defined(PCI_ASYNC) - if (pci_async_enabled()) { - printf (", PCI async ext clock used"); - } else { - printf (", PCI sync clock at %lu MHz", - sys_info.freqPLB / sys_info.pllPciDiv / 1000000); - } -#endif - -#if defined(CONFIG_PCI) - putc('\n'); -#endif - -#if defined(CONFIG_405EP) - printf (" 16 kB I-Cache 16 kB D-Cache"); -#elif defined(CONFIG_440) - printf (" 32 kB I-Cache 32 kB D-Cache"); -#else - printf (" 16 kB I-Cache %d kB D-Cache", - ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); -#endif -#endif /* !defined(CONFIG_IOP480) */ - -#if defined(CONFIG_IOP480) - printf ("PLX IOP480 (PVR=%08x)", pvr); - printf (" at %s MHz:", strmhz(buf, clock)); - printf (" %u kB I-Cache", 4); - printf (" %u kB D-Cache", 2); -#endif - -#endif /* !defined(CONFIG_405) */ - - putc ('\n'); - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ -#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE) - /*give reset to BCSR*/ - *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09; - -#else - - /* - * Initiate system reset in debug control register DBCR - */ - __asm__ __volatile__("lis 3, 0x3000" ::: "r3"); -#if defined(CONFIG_440) - __asm__ __volatile__("mtspr 0x134, 3"); -#else - __asm__ __volatile__("mtspr 0x3f2, 3"); -#endif - -#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/ - return 1; -} - -#if defined(CONFIG_440) -static int do_chip_reset (unsigned long sys0, unsigned long sys1) -{ - /* Changes to cpc0_sys0 and cpc0_sys1 require chip - * reset. - */ - mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ - mtdcr (cpc0_sys0, sys0); - mtdcr (cpc0_sys1, sys1); - mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ - mtspr (dbcr0, 0x20000000); /* Reset the chip */ - - return 1; -} -#endif - - -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk (void) -{ -#if !defined(CONFIG_IOP480) - sys_info_t sys_info; - - get_sys_info(&sys_info); - return (sys_info.freqProcessor); -#else - return (66000000); -#endif - -} - - -#if defined(CONFIG_WATCHDOG) -void -watchdog_reset(void) -{ - int re_enable = disable_interrupts(); - reset_4xx_watchdog(); - if (re_enable) enable_interrupts(); -} - -void -reset_4xx_watchdog(void) -{ - /* - * Clear TSR(WIS) bit - */ - mtspr(tsr, 0x40000000); -} -#endif /* CONFIG_WATCHDOG */ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c deleted file mode 100644 index 79cfba3..0000000 --- a/cpu/ppc4xx/cpu_init.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - - -#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) - -#ifdef CFG_INIT_DCACHE_CS -# if (CFG_INIT_DCACHE_CS == 0) -# define PBxAP pb0ap -# define PBxCR pb0cr -# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) -# define PBxAP_VAL CFG_EBC_PB0AP -# define PBxCR_VAL CFG_EBC_PB0CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 1) -# define PBxAP pb1ap -# define PBxCR pb1cr -# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) -# define PBxAP_VAL CFG_EBC_PB1AP -# define PBxCR_VAL CFG_EBC_PB1CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 2) -# define PBxAP pb2ap -# define PBxCR pb2cr -# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) -# define PBxAP_VAL CFG_EBC_PB2AP -# define PBxCR_VAL CFG_EBC_PB2CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 3) -# define PBxAP pb3ap -# define PBxCR pb3cr -# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) -# define PBxAP_VAL CFG_EBC_PB3AP -# define PBxCR_VAL CFG_EBC_PB3CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 4) -# define PBxAP pb4ap -# define PBxCR pb4cr -# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) -# define PBxAP_VAL CFG_EBC_PB4AP -# define PBxCR_VAL CFG_EBC_PB4CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 5) -# define PBxAP pb5ap -# define PBxCR pb5cr -# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) -# define PBxAP_VAL CFG_EBC_PB5AP -# define PBxCR_VAL CFG_EBC_PB5CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 6) -# define PBxAP pb6ap -# define PBxCR pb6cr -# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) -# define PBxAP_VAL CFG_EBC_PB6AP -# define PBxCR_VAL CFG_EBC_PB6CR -# endif -# endif -# if (CFG_INIT_DCACHE_CS == 7) -# define PBxAP pb7ap -# define PBxCR pb7cr -# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) -# define PBxAP_VAL CFG_EBC_PB7AP -# define PBxCR_VAL CFG_EBC_PB7CR -# endif -# endif -#endif /* CFG_INIT_DCACHE_CS */ - - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers - */ -void -cpu_init_f (void) -{ -#if defined(CONFIG_405EP) - /* - * GPIO0 setup (select GPIO or alternate function) - */ - out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ - out32(GPIO0_OSRL, CFG_GPIO0_OSRL); - out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ - out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); - out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ - out32(GPIO0_TSRL, CFG_GPIO0_TSRL); - out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ - - /* - * Set EMAC noise filter bits - */ - mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); -#endif /* CONFIG_405EP */ - - /* - * External Bus Controller (EBC) Setup - */ -#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) - /* - * Move the next instructions into icache, since these modify the flash - * we are running from! - */ - asm volatile(" bl 0f" ::: "lr"); - asm volatile("0: mflr 3" ::: "r3"); - asm volatile(" addi 4, 0, 14" ::: "r4"); - asm volatile(" mtctr 4" ::: "ctr"); - asm volatile("1: icbt 0, 3"); - asm volatile(" addi 3, 3, 32" ::: "r3"); - asm volatile(" bdnz 1b" ::: "ctr", "cr0"); - asm volatile(" addis 3, 0, 0x0" ::: "r3"); - asm volatile(" ori 3, 3, 0xA000" ::: "r3"); - asm volatile(" mtctr 3" ::: "ctr"); - asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); - - mtebc(pb0ap, CFG_EBC_PB0AP); - mtebc(pb0cr, CFG_EBC_PB0CR); -#endif - -#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1)) - mtebc(pb1ap, CFG_EBC_PB1AP); - mtebc(pb1cr, CFG_EBC_PB1CR); -#endif - -#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2)) - mtebc(pb2ap, CFG_EBC_PB2AP); - mtebc(pb2cr, CFG_EBC_PB2CR); -#endif - -#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3)) - mtebc(pb3ap, CFG_EBC_PB3AP); - mtebc(pb3cr, CFG_EBC_PB3CR); -#endif - -#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4)) - mtebc(pb4ap, CFG_EBC_PB4AP); - mtebc(pb4cr, CFG_EBC_PB4CR); -#endif - -#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5)) - mtebc(pb5ap, CFG_EBC_PB5AP); - mtebc(pb5cr, CFG_EBC_PB5CR); -#endif - -#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6)) - mtebc(pb6ap, CFG_EBC_PB6AP); - mtebc(pb6cr, CFG_EBC_PB6CR); -#endif - -#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7)) - mtebc(pb7ap, CFG_EBC_PB7AP); - mtebc(pb7cr, CFG_EBC_PB7CR); -#endif - -#if defined(CONFIG_WATCHDOG) - unsigned long val; - - val = mfspr(tcr); -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) - val |= 0xb8000000; /* generate system reset after 1.34 seconds */ -#else - val |= 0xf0000000; /* generate system reset after 2.684 seconds */ -#endif - mtspr(tcr, val); - - val = mfspr(tsr); - val |= 0x80000000; /* enable watchdog timer */ - mtspr(tsr, val); - - reset_4xx_watchdog(); -#endif /* CONFIG_WATCHDOG */ -} - -/* - * initialize higher level parts of CPU like time base and timers - */ -int cpu_init_r (void) -{ -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) - DECLARE_GLOBAL_DATA_PTR; - - bd_t *bd = gd->bd; - unsigned long reg; -#if defined(CONFIG_405GP) - uint pvr = get_pvr(); -#endif - -#ifdef CFG_INIT_DCACHE_CS - /* - * Flush and invalidate dcache, then disable CS for temporary stack. - * Afterwards, this CS can be used for other purposes - */ - dcache_disable(); /* flush and invalidate dcache */ - mtebc(PBxAP, 0); - mtebc(PBxCR, 0); /* disable CS for temporary stack */ - -#if (defined(PBxAP_VAL) && defined(PBxCR_VAL)) - /* - * Write new value into CS register - */ - mtebc(PBxAP, PBxAP_VAL); - mtebc(PBxCR, PBxCR_VAL); -#endif -#endif /* CFG_INIT_DCACHE_CS */ - - /* - * Write Ethernetaddress into on-chip register - */ - reg = 0x00000000; - reg |= bd->bi_enetaddr[0]; /* set high address */ - reg = reg << 8; - reg |= bd->bi_enetaddr[1]; - out32 (EMAC_IAH, reg); - - reg = 0x00000000; - reg |= bd->bi_enetaddr[2]; /* set low address */ - reg = reg << 8; - reg |= bd->bi_enetaddr[3]; - reg = reg << 8; - reg |= bd->bi_enetaddr[4]; - reg = reg << 8; - reg |= bd->bi_enetaddr[5]; - out32 (EMAC_IAL, reg); - -#if defined(CONFIG_405GP) - /* - * Set edge conditioning circuitry on PPC405GPr - * for compatibility to existing PPC405GP designs. - */ - if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { - mtdcr(ecr, 0x60606000); - } -#endif /* defined(CONFIG_405GP) */ -#endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */ - return (0); -} diff --git a/cpu/ppc4xx/dcr.S b/cpu/ppc4xx/dcr.S deleted file mode 100644 index 7102364..0000000 --- a/cpu/ppc4xx/dcr.S +++ /dev/null @@ -1,198 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include - -#if defined(CONFIG_4xx) && defined(CFG_CMD_SETGETDCR) - -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#define _ASMLANGUAGE - -/***************************************************************************** - * - * XXX - DANGER - * These routines make use of self modifying code. DO NOT CALL THEM - * UNTIL THEY ARE RELOCATED TO RAM. Additionally, I do not - * recommend them for use in anything other than an interactive - * debugging environment. This is mainly due to performance reasons. - * - ****************************************************************************/ - -/* - * static void _create_MFDCR(unsigned short dcrn) - * - * Builds a 'mfdcr' instruction for get_dcr - * function. - */ - .section ".text" - .align 2 - .type _create_MFDCR,@function -_create_MFDCR: - /* - * Build up a 'mfdcr' instruction formatted as follows: - * - * OPCD | RT | DCRF | XO | CR | - * ---------------|--------------|--------------|----| - * 0 5 | 6 10 | 11 20 | 21 30 | 31 | - * | | DCRN | | | - * 31 | %r3 | (5..9|0..4) | 323 | 0 | - * - * Where: - * OPCD = opcode - 31 - * RT = destination register - %r3 return register - * DCRF = DCRN # with upper and lower halves swapped - * XO = extended opcode - 323 - * CR = CR[CR0] NOT undefined - 0 - */ - rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */ - rlwinm r3, r3, 5, 22, 26 - or r3, r3, r0 - slwi r3, r3, 10 - oris r3, r3, 0x3e30 /* RT = %r3 */ - ori r3, r3, 323 /* XO = 323 */ - slwi r3, r3, 1 /* CR = 0 */ - - mflr r4 - stw r3, 0(r4) /* Store instr in get_dcr() */ - dcbst r0, r4 /* Make sure val is written out */ - sync /* Wait for write to complete */ - icbi r0, r4 /* Make sure old instr is dumped */ - isync /* Wait for icbi to complete */ - - blr -.Lfe1: .size _create_MFDCR,.Lfe1-_create_MFDCR -/* end _create_MFDCR() */ - -/* - * static void _create_MTDCR(unsigned short dcrn, unsigned long value) - * - * Builds a 'mtdcr' instruction for set_dcr - * function. - */ - .section ".text" - .align 2 - .type _create_MTDCR,@function -_create_MTDCR: - /* - * Build up a 'mtdcr' instruction formatted as follows: - * - * OPCD | RS | DCRF | XO | CR | - * ---------------|--------------|--------------|----| - * 0 5 | 6 10 | 11 20 | 21 30 | 31 | - * | | DCRN | | | - * 31 | %r3 | (5..9|0..4) | 451 | 0 | - * - * Where: - * OPCD = opcode - 31 - * RS = source register - %r4 - * DCRF = dest. DCRN # with upper and lower halves swapped - * XO = extended opcode - 451 - * CR = CR[CR0] NOT undefined - 0 - */ - rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */ - rlwinm r3, r3, 5, 22, 26 - or r3, r3, r0 - slwi r3, r3, 10 - oris r3, r3, 0x3e40 /* RS = %r4 */ - ori r3, r3, 451 /* XO = 451 */ - slwi r3, r3, 1 /* CR = 0 */ - - mflr r5 - stw r3, 0(r5) /* Store instr in set_dcr() */ - dcbst r0, r5 /* Make sure val is written out */ - sync /* Wait for write to complete */ - icbi r0, r5 /* Make sure old instr is dumped */ - isync /* Wait for icbi to complete */ - - blr -.Lfe2: .size _create_MTDCR,.Lfe2-_create_MTDCR -/* end _create_MTDCR() */ - - -/* - * unsigned long get_dcr(unsigned short dcrn) - * - * Return a given DCR's value. - */ - /* */ - /* XXX - This is self modifying code, hence */ - /* it is in the data section. */ - /* */ - .section ".data" - .align 2 - .globl get_dcr - .type get_dcr,@function -get_dcr: - mflr r0 /* Get link register */ - stwu r1, -32(r1) /* Save back chain and move SP */ - stw r0, +36(r1) /* Save link register */ - - bl _create_MFDCR /* Build following instruction */ - /* XXX - we build this instuction up on the fly. */ - .long 0 /* Get DCR's value */ - - lwz r0, +36(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - addi r1, r1, +32 /* Remove frame from stack */ - blr /* Return to calling function */ -.Lfe3: .size get_dcr,.Lfe3-get_dcr -/* end get_dcr() */ - - -/* - * unsigned void set_dcr(unsigned short dcrn, unsigned long value) - * - * Return a given DCR's value. - */ - /* - * XXX - This is self modifying code, hence - * it is in the data section. - */ - .section ".data" - .align 2 - .globl set_dcr - .type set_dcr,@function -set_dcr: - mflr r0 /* Get link register */ - stwu r1, -32(r1) /* Save back chain and move SP */ - stw r0, +36(r1) /* Save link register */ - - bl _create_MTDCR /* Build following instruction */ - /* XXX - we build this instuction up on the fly. */ - .long 0 /* Set DCR's value */ - - lwz r0, +36(r1) /* Get saved link register */ - mtlr r0 /* Restore link register */ - addi r1, r1, +32 /* Remove frame from stack */ - blr /* Return to calling function */ -.Lfe4: .size set_dcr,.Lfe4-set_dcr -/* end set_dcr() */ -#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */ diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c deleted file mode 100644 index be94b57..0000000 --- a/cpu/ppc4xx/i2c.c +++ /dev/null @@ -1,445 +0,0 @@ -/*****************************************************************************/ -/* I2C Bus interface initialisation and I2C Commands */ -/* for PPC405GP */ -/* Author : AS HARNOIS */ -/* Date : 13.Dec.00 */ -/*****************************************************************************/ - -#include -#include -#if defined(CONFIG_440) -# include <440_i2c.h> -#else -# include <405gp_i2c.h> -#endif -#include - -#ifdef CONFIG_HARD_I2C - -#define IIC_OK 0 -#define IIC_NOK 1 -#define IIC_NOK_LA 2 /* Lost arbitration */ -#define IIC_NOK_ICT 3 /* Incomplete transfer */ -#define IIC_NOK_XFRA 4 /* Transfer aborted */ -#define IIC_NOK_DATA 5 /* No data in buffer */ -#define IIC_NOK_TOUT 6 /* Transfer timeout */ - -#define IIC_TIMEOUT 1 /* 1 seconde */ - - -static void _i2c_bus_reset (void) -{ - int i, status; - - /* Reset status register */ - /* write 1 in SCMP and IRQA to clear these fields */ - out8 (IIC_STS, 0x0A); - - /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ - out8 (IIC_EXTSTS, 0x8F); - __asm__ volatile ("eieio"); - - /* - * Get current state, reset bus - * only if no transfers are pending. - */ - i = 10; - do { - /* Get status */ - status = in8 (IIC_STS); - udelay (500); /* 500us */ - i--; - } while ((status & IIC_STS_PT) && (i > 0)); - /* Soft reset controller */ - status = in8 (IIC_XTCNTLSS); - out8 (IIC_XTCNTLSS, (status | IIC_XTCNTLSS_SRST)); - __asm__ volatile ("eieio"); - - /* make sure where in initial state, data hi, clock hi */ - out8 (IIC_DIRECTCNTL, 0xC); - for (i = 0; i < 10; i++) { - if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) { - /* clock until we get to known state */ - out8 (IIC_DIRECTCNTL, 0x8); /* clock lo */ - udelay (100); /* 100us */ - out8 (IIC_DIRECTCNTL, 0xC); /* clock hi */ - udelay (100); /* 100us */ - } else { - break; - } - } - /* send start condition */ - out8 (IIC_DIRECTCNTL, 0x4); - udelay (1000); /* 1ms */ - /* send stop condition */ - out8 (IIC_DIRECTCNTL, 0xC); - udelay (1000); /* 1ms */ - /* Unreset controller */ - out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST)); - udelay (1000); /* 1ms */ -} - -void i2c_init (int speed, int slaveadd) -{ - sys_info_t sysInfo; - unsigned long freqOPB; - int val, divisor; - -#ifdef CFG_I2C_INIT_BOARD - /* call board specific i2c bus reset routine before accessing the */ - /* environment, which might be in a chip on that bus. For details */ - /* about this problem see doc/I2C_Edge_Conditions. */ - i2c_init_board(); -#endif - - /* Handle possible failed I2C state */ - /* FIXME: put this into i2c_init_board()? */ - _i2c_bus_reset (); - - /* clear lo master address */ - out8 (IIC_LMADR, 0); - - /* clear hi master address */ - out8 (IIC_HMADR, 0); - - /* clear lo slave address */ - out8 (IIC_LSADR, 0); - - /* clear hi slave address */ - out8 (IIC_HSADR, 0); - - /* Clock divide Register */ - /* get OPB frequency */ - get_sys_info (&sysInfo); - freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv; - /* set divisor according to freqOPB */ - divisor = (freqOPB - 1) / 10000000; - if (divisor == 0) - divisor = 1; - out8 (IIC_CLKDIV, divisor); - - /* no interrupts */ - out8 (IIC_INTRMSK, 0); - - /* clear transfer count */ - out8 (IIC_XFRCNT, 0); - - /* clear extended control & stat */ - /* write 1 in SRC SRS SWC SWS to clear these fields */ - out8 (IIC_XTCNTLSS, 0xF0); - - /* Mode Control Register - Flush Slave/Master data buffer */ - out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); - __asm__ volatile ("eieio"); - - - val = in8(IIC_MDCNTL); - __asm__ volatile ("eieio"); - - /* Ignore General Call, slave transfers are ignored, - disable interrupts, exit unknown bus state, enable hold - SCL - 100kHz normaly or FastMode for 400kHz and above - */ - - val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL; - if( speed >= 400000 ){ - val |= IIC_MDCNTL_FSM; - } - out8 (IIC_MDCNTL, val); - - /* clear control reg */ - out8 (IIC_CNTL, 0x00); - __asm__ volatile ("eieio"); - -} - -/* - This code tries to use the features of the 405GP i2c - controller. It will transfer up to 4 bytes in one pass - on the loop. It only does out8(lbz) to the buffer when it - is possible to do out16(lhz) transfers. - - cmd_type is 0 for write 1 for read. - - addr_len can take any value from 0-255, it is only limited - by the char, we could make it larger if needed. If it is - 0 we skip the address write cycle. - - Typical case is a Write of an addr followd by a Read. The - IBM FAQ does not cover this. On the last byte of the write - we don't set the creg CHT bit, and on the first bytes of the - read we set the RPST bit. - - It does not support address only transfers, there must be - a data part. If you want to write the address yourself, put - it in the data pointer. - - It does not support transfer to/from address 0. - - It does not check XFRCNT. -*/ -static -int i2c_transfer(unsigned char cmd_type, - unsigned char chip, - unsigned char addr[], - unsigned char addr_len, - unsigned char data[], - unsigned short data_len ) -{ - unsigned char* ptr; - int reading; - int tran,cnt; - int result; - int status; - int i; - uchar creg; - - if( data == 0 || data_len == 0 ){ - /*Don't support data transfer of no length or to address 0*/ - printf( "i2c_transfer: bad call\n" ); - return IIC_NOK; - } - if( addr && addr_len ){ - ptr = addr; - cnt = addr_len; - reading = 0; - }else{ - ptr = data; - cnt = data_len; - reading = cmd_type; - } - - /*Clear Stop Complete Bit*/ - out8(IIC_STS,IIC_STS_SCMP); - /* Check init */ - i=10; - do { - /* Get status */ - status = in8(IIC_STS); - __asm__ volatile("eieio"); - i--; - } while ((status & IIC_STS_PT) && (i>0)); - - if (status & IIC_STS_PT) { - result = IIC_NOK_TOUT; - return(result); - } - /*flush the Master/Slave Databuffers*/ - out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB)); - /*need to wait 4 OPB clocks? code below should take that long*/ - - /* 7-bit adressing */ - out8(IIC_HMADR,0); - out8(IIC_LMADR, chip); - __asm__ volatile("eieio"); - - tran = 0; - result = IIC_OK; - creg = 0; - - while ( tran != cnt && (result == IIC_OK)) { - int bc,j; - - /* Control register = - Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start, - Transfer is a sequence of transfers - */ - creg |= IIC_CNTL_PT; - - bc = (cnt - tran) > 4 ? 4 : - cnt - tran; - creg |= (bc-1)<<4; - /* if the real cmd type is write continue trans*/ - if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) ) - creg |= IIC_CNTL_CHT; - - if (reading) - creg |= IIC_CNTL_READ; - else { - for(j=0; j0)); - - if (status & IIC_STS_ERR) { - result = IIC_NOK; - status = in8 (IIC_EXTSTS); - /* Lost arbitration? */ - if (status & IIC_EXTSTS_LA) - result = IIC_NOK_LA; - /* Incomplete transfer? */ - if (status & IIC_EXTSTS_ICT) - result = IIC_NOK_ICT; - /* Transfer aborted? */ - if (status & IIC_EXTSTS_XFRA) - result = IIC_NOK_XFRA; - } else if ( status & IIC_STS_PT) { - result = IIC_NOK_TOUT; - } - /* Command is reading => get buffer */ - if ((reading) && (result == IIC_OK)) { - /* Are there data in buffer */ - if (status & IIC_STS_MDBS) { - /* - even if we have data we have to wait 4OPB clocks - for it to hit the front of the FIFO, after that - we can just read. We should check XFCNT here and - if the FIFO is full there is no need to wait. - */ - udelay (1); - for(j=0;jed (i.e. there was a chip at that address which - * drove the data line low). - */ - return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0); -} - - -int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - uchar xaddr[4]; - int ret; - DECLARE_GLOBAL_DATA_PTR; - - if ( alen > 4 ) { - printf ("I2C read: addr len %d not supported\n", alen); - return 1; - } - - if ( alen > 0 ) { - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - } - - -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if( alen > 0 ) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); -#endif - if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { - if (gd->have_console) - printf( "I2c read: failed %d\n", ret); - return 1; - } - return 0; -} - -int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - uchar xaddr[4]; - - if ( alen > 4 ) { - printf ("I2C write: addr len %d not supported\n", alen); - return 1; - - } - if ( alen > 0 ) { - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - } - -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - if( alen > 0 ) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); -#endif - - return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); -} - -/*----------------------------------------------------------------------- - * Read a register - */ -uchar i2c_reg_read(uchar i2c_addr, uchar reg) -{ - uchar buf; - - i2c_read(i2c_addr, reg, 1, &buf, 1); - - return(buf); -} - -/*----------------------------------------------------------------------- - * Write a register - */ -void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write(i2c_addr, reg, 1, &val, 1); -} -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c deleted file mode 100644 index 1d8dc7c..0000000 --- a/cpu/ppc4xx/interrupts.c +++ /dev/null @@ -1,571 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 (440 port) - * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com - * - * (C) Copyright 2003 (440GX port) - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include "vecnum.h" - -/****************************************************************************/ - -/* - * CPM interrupt vector functions. - */ -struct irq_action { - interrupt_handler_t *handler; - void *arg; - int count; -}; - -static struct irq_action irq_vecs[32]; - -#if defined(CONFIG_440) -static struct irq_action irq_vecs1[32]; /* For UIC1 */ - -void uic1_interrupt( void * parms); /* UIC1 handler */ - -#if defined(CONFIG_440GX) -static struct irq_action irq_vecs2[32]; /* For UIC2 */ - -void uic0_interrupt( void * parms); /* UIC0 handler */ -void uic2_interrupt( void * parms); /* UIC2 handler */ -#endif /* CONFIG_440GX */ - -#endif /* CONFIG_440 */ - -/****************************************************************************/ -#if defined(CONFIG_440) - -/* SPRN changed in 440 */ -static __inline__ void set_evpr(unsigned long val) -{ - asm volatile("mtspr 0x03f,%0" : : "r" (val)); -} - -#else /* !defined(CONFIG_440) */ - -static __inline__ void set_pit(unsigned long val) -{ - asm volatile("mtpit %0" : : "r" (val)); -} - - -static __inline__ void set_tcr(unsigned long val) -{ - asm volatile("mttcr %0" : : "r" (val)); -} - - -static __inline__ void set_evpr(unsigned long val) -{ - asm volatile("mtevpr %0" : : "r" (val)); -} -#endif /* defined(CONFIG_440 */ - -/****************************************************************************/ - -int interrupt_init_cpu (unsigned *decrementer_count) -{ - DECLARE_GLOBAL_DATA_PTR; - - int vec; - unsigned long val; - - /* decrementer is automatically reloaded */ - *decrementer_count = 0; - - /* - * Mark all irqs as free - */ - for (vec=0; vec<32; vec++) { - irq_vecs[vec].handler = NULL; - irq_vecs[vec].arg = NULL; - irq_vecs[vec].count = 0; -#if defined(CONFIG_440) - irq_vecs1[vec].handler = NULL; - irq_vecs1[vec].arg = NULL; - irq_vecs1[vec].count = 0; -#if defined(CONFIG_440GX) - irq_vecs2[vec].handler = NULL; - irq_vecs2[vec].arg = NULL; - irq_vecs2[vec].count = 0; -#endif /* CONFIG_440GX */ -#endif - } - -#ifdef CONFIG_4xx - /* - * Init PIT - */ -#if defined(CONFIG_440) - val = mfspr( tcr ); - val &= (~0x04400000); /* clear DIS & ARE */ - mtspr( tcr, val ); - mtspr( dec, 0 ); /* Prevent exception after TSR clear*/ - mtspr( decar, 0 ); /* clear reload */ - mtspr( tsr, 0x08000000 ); /* clear DEC status */ - val = gd->bd->bi_intfreq/1000; /* 1 msec */ - mtspr( decar, val ); /* Set auto-reload value */ - mtspr( dec, val ); /* Set inital val */ -#else - set_pit(gd->bd->bi_intfreq / 1000); -#endif -#endif /* CONFIG_4xx */ - -#ifdef CONFIG_ADCIOP - /* - * Init PIT - */ - set_pit(66000); -#endif - - /* - * Enable PIT - */ - val = mfspr(tcr); - val |= 0x04400000; - mtspr(tcr, val); - - /* - * Set EVPR to 0 - */ - set_evpr(0x00000000); - -#if defined(CONFIG_440) -#if !defined(CONFIG_440GX) - /* Install the UIC1 handlers */ - irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0); - irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0); -#endif -#endif - -#if defined(CONFIG_440GX) - /* Take the GX out of compatibility mode - * Travis Sawyer, 9 Mar 2004 - * NOTE: 440gx user manual inconsistency here - * Compatibility mode and Ethernet Clock select are not - * correct in the manual - */ - mfsdr(sdr_mfr, val); - val &= ~0x10000000; - mtsdr(sdr_mfr,val); - - /* Enable UIC interrupts via UIC Base Enable Register */ - mtdcr(uicb0sr, UICB0_ALL); - mtdcr(uicb0er, 0x54000000); - /* None are critical */ - mtdcr(uicb0cr, 0); -#endif - - return (0); -} - -/****************************************************************************/ - -/* - * Handle external interrupts - */ -#if defined(CONFIG_440GX) -void external_interrupt(struct pt_regs *regs) -{ - ulong uic_msr; - - /* - * Read masked interrupt status register to determine interrupt source - */ - /* 440 GX uses base uic register */ - uic_msr = mfdcr(uicb0msr); - - if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) ) - uic0_interrupt(0); - - if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) ) - uic1_interrupt(0); - - if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) ) - uic2_interrupt(0); - - mtdcr(uicb0sr, uic_msr); - - return; - -} /* external_interrupt CONFIG_440GX */ - -#else - -void external_interrupt(struct pt_regs *regs) -{ - ulong uic_msr; - ulong msr_shift; - int vec; - - /* - * Read masked interrupt status register to determine interrupt source - */ - uic_msr = mfdcr(uicmsr); - msr_shift = uic_msr; - vec = 0; - - while (msr_shift != 0) { - if (msr_shift & 0x80000000) { - /* - * Increment irq counter (for debug purpose only) - */ - irq_vecs[vec].count++; - - if (irq_vecs[vec].handler != NULL) { - /* call isr */ - (*irq_vecs[vec].handler)(irq_vecs[vec].arg); - } else { - mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec)); - printf ("Masking bogus interrupt vector 0x%x\n", vec); - } - - /* - * After servicing the interrupt, we have to remove the status indicator. - */ - mtdcr(uicsr, (0x80000000 >> vec)); - } - - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } -} -#endif - -#if defined(CONFIG_440GX) -/* Handler for UIC0 interrupt */ -void uic0_interrupt( void * parms) -{ - ulong uic_msr; - ulong msr_shift; - int vec; - - /* - * Read masked interrupt status register to determine interrupt source - */ - uic_msr = mfdcr(uicmsr); - msr_shift = uic_msr; - vec = 0; - - while (msr_shift != 0) { - if (msr_shift & 0x80000000) { - /* - * Increment irq counter (for debug purpose only) - */ - irq_vecs[vec].count++; - - if (irq_vecs[vec].handler != NULL) { - /* call isr */ - (*irq_vecs[vec].handler)(irq_vecs[vec].arg); - } else { - mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec)); - printf ("Masking bogus interrupt vector (uic0) 0x%x\n", vec); - } - - /* - * After servicing the interrupt, we have to remove the status indicator. - */ - mtdcr(uicsr, (0x80000000 >> vec)); - } - - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } -} - -#endif /* CONFIG_440GX */ - -#if defined(CONFIG_440) -/* Handler for UIC1 interrupt */ -void uic1_interrupt( void * parms) -{ - ulong uic1_msr; - ulong msr_shift; - int vec; - - /* - * Read masked interrupt status register to determine interrupt source - */ - uic1_msr = mfdcr(uic1msr); - msr_shift = uic1_msr; - vec = 0; - - while (msr_shift != 0) { - if (msr_shift & 0x80000000) { - /* - * Increment irq counter (for debug purpose only) - */ - irq_vecs1[vec].count++; - - if (irq_vecs1[vec].handler != NULL) { - /* call isr */ - (*irq_vecs1[vec].handler)(irq_vecs1[vec].arg); - } else { - mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec)); - printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec); - } - - /* - * After servicing the interrupt, we have to remove the status indicator. - */ - mtdcr(uic1sr, (0x80000000 >> vec)); - } - - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } -} -#endif /* defined(CONFIG_440) */ - -#if defined(CONFIG_440GX) -/* Handler for UIC1 interrupt */ -void uic2_interrupt( void * parms) -{ - ulong uic2_msr; - ulong msr_shift; - int vec; - - /* - * Read masked interrupt status register to determine interrupt source - */ - uic2_msr = mfdcr(uic2msr); - msr_shift = uic2_msr; - vec = 0; - - while (msr_shift != 0) { - if (msr_shift & 0x80000000) { - /* - * Increment irq counter (for debug purpose only) - */ - irq_vecs2[vec].count++; - - if (irq_vecs2[vec].handler != NULL) { - /* call isr */ - (*irq_vecs2[vec].handler)(irq_vecs2[vec].arg); - } else { - mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec)); - printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec); - } - - /* - * After servicing the interrupt, we have to remove the status indicator. - */ - mtdcr(uic2sr, (0x80000000 >> vec)); - } - - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } -} -#endif /* defined(CONFIG_440GX) */ - -/****************************************************************************/ - -/* - * Install and free a interrupt handler. - */ - -void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) -{ - struct irq_action *irqa = irq_vecs; - int i = vec; - -#if defined(CONFIG_440) -#if defined(CONFIG_440GX) - if ((vec > 31) && (vec < 64)) { - i = vec - 32; - irqa = irq_vecs1; - } else if (vec > 63) { - i = vec - 64; - irqa = irq_vecs2; - } -#else /* CONFIG_440GX */ - if (vec > 31) { - i = vec - 32; - irqa = irq_vecs1; - } -#endif /* CONFIG_440GX */ -#endif /* CONFIG_440 */ - - /* - * print warning when replacing with a different irq vector - */ - if ((irqa[i].handler != NULL) && (irqa[i].handler != handler)) { - printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n", - vec, (uint) handler, (uint) irqa[i].handler); - } - irqa[i].handler = handler; - irqa[i].arg = arg; - -#if defined(CONFIG_440) -#if defined(CONFIG_440GX) - if ((vec > 31) && (vec < 64)) - mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); - else if (vec > 63) - mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i)); - else -#endif /* CONFIG_440GX */ - if (vec > 31) - mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); - else -#endif - mtdcr (uicer, mfdcr (uicer) | (0x80000000 >> i)); -#if 0 - printf ("Install interrupt for vector %d ==> %p\n", vec, handler); -#endif -} - -void irq_free_handler (int vec) -{ - struct irq_action *irqa = irq_vecs; - int i = vec; - -#if defined(CONFIG_440) -#if defined(CONFIG_440GX) - if ((vec > 31) && (vec < 64)) { - irqa = irq_vecs1; - i = vec - 32; - } else if (vec > 63) { - irqa = irq_vecs2; - i = vec - 64; - } -#endif /* CONFIG_440GX */ - if (vec > 31) { - irqa = irq_vecs1; - i = vec - 32; - } -#endif - -#if 0 - printf ("Free interrupt for vector %d ==> %p\n", - vec, irq_vecs[vec].handler); -#endif - -#if defined(CONFIG_440) -#if defined(CONFIG_440GX) - if ((vec > 31) && (vec < 64)) - mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); - else if (vec > 63) - mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i)); - else -#endif /* CONFIG_440GX */ - if (vec > 31) - mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); - else -#endif - mtdcr (uicer, mfdcr (uicer) & ~(0x80000000 >> i)); - - irqa[i].handler = NULL; - irqa[i].arg = NULL; -} - -/****************************************************************************/ - -void timer_interrupt_cpu (struct pt_regs *regs) -{ - /* nothing to do here */ - return; -} - -/****************************************************************************/ - -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) - -/******************************************************************************* - * - * irqinfo - print information about PCI devices - * - */ -int -do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int vec; - - printf ("\nInterrupt-Information:\n"); -#if defined(CONFIG_440) - printf ("\nUIC 0\n"); -#endif - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec<32; vec++) { - if (irq_vecs[vec].handler != NULL) { - printf ("%02d %08lx %08lx %d\n", - vec, - (ulong)irq_vecs[vec].handler, - (ulong)irq_vecs[vec].arg, - irq_vecs[vec].count); - } - } - -#if defined(CONFIG_440) - printf ("\nUIC 1\n"); - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec<32; vec++) { - if (irq_vecs1[vec].handler != NULL) - printf ("%02d %08lx %08lx %d\n", - vec+31, (ulong)irq_vecs1[vec].handler, - (ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count); - } - printf("\n"); -#endif - -#if defined(CONFIG_440GX) - printf ("\nUIC 2\n"); - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec<32; vec++) { - if (irq_vecs2[vec].handler != NULL) - printf ("%02d %08lx %08lx %d\n", - vec+63, (ulong)irq_vecs2[vec].handler, - (ulong)irq_vecs2[vec].arg, irq_vecs2[vec].count); - } - printf("\n"); -#endif - - return 0; -} -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S deleted file mode 100644 index be28340..0000000 --- a/cpu/ppc4xx/kgdb.S +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2000 Murray Jensen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define CONFIG_405GP 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - /* - * cache flushing routines for kgdb - */ - - .globl kgdb_flush_cache_all -kgdb_flush_cache_all: - /* icache */ - iccci r0,r0 /* iccci invalidates the entire I cache */ - /* dcache */ - addi r6,0,0x0000 /* clear GPR 6 */ - addi r7,r0, 128 /* do loop for # of dcache lines */ - /* NOTE: dccci invalidates both */ - mtctr r7 /* ways in the D cache */ -..dcloop: - dccci 0,r6 /* invalidate line */ - addi r6,r6, 32 /* bump to next line */ - bdnz ..dcloop - blr - - .globl kgdb_flush_cache_range -kgdb_flush_cache_range: - li r5,CFG_CACHELINE_SIZE-1 - andc r3,r3,r5 - subf r4,r3,r4 - add r4,r4,r5 - srwi. r4,r4,CFG_CACHELINE_SHIFT - beqlr - mtctr r4 - mr r6,r3 -1: dcbst 0,r3 - addi r3,r3,CFG_CACHELINE_SIZE - bdnz 1b - sync /* wait for dcbst's to get to ram */ - mtctr r4 -2: icbi 0,r6 - addi r6,r6,CFG_CACHELINE_SIZE - bdnz 2b - SYNC - blr - -#endif /* CFG_CMD_KGDB */ diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c deleted file mode 100644 index f26f2a2..0000000 --- a/cpu/ppc4xx/miiphy.c +++ /dev/null @@ -1,260 +0,0 @@ -/*-----------------------------------------------------------------------------+ - | - | This source code has been made available to you by IBM on an AS-IS - | basis. Anyone receiving this source is licensed under IBM - | copyrights to use it in any way he or she deems fit, including - | copying it, modifying it, compiling it, and redistributing it either - | with or without modifications. No license under IBM patents or - | patent applications is to be implied by the copyright license. - | - | Any user of this software should understand that IBM cannot provide - | technical support for this software and will not be responsible for - | any consequences resulting from the use of this software. - | - | Any person who transfers this source code or any derivative work - | must include the IBM copyright notice, this paragraph, and the - | preceding two paragraphs in the transferred software. - | - | COPYRIGHT I B M CORPORATION 1995 - | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - +-----------------------------------------------------------------------------*/ -/*-----------------------------------------------------------------------------+ - | - | File Name: miiphy.c - | - | Function: This module has utilities for accessing the MII PHY through - | the EMAC3 macro. - | - | Author: Mark Wisner - | - | Change Activity- - | - | Date Description of Change BY - | --------- --------------------- --- - | 05-May-99 Created MKW - | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to - | better match OPB speed. Also modified delay times. JWB - | 29-Jul-99 Added Full duplex support MKW - | 24-Aug-99 Removed printf from dp83843_duplex() JWB - | 19-Jul-00 Ported to esd cpci405 sr - | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS - | - | - +-----------------------------------------------------------------------------*/ - -#include -#include -#include -#include -#include -#include <405_mal.h> -#include - - -/***********************************************************/ -/* Dump out to the screen PHY regs */ -/***********************************************************/ - -void miiphy_dump (char *devname, unsigned char addr) -{ - unsigned long i; - unsigned short data; - - - for (i = 0; i < 0x1A; i++) { - if (miiphy_read (devname, addr, i, &data)) { - printf ("read error for reg %lx\n", i); - return; - } - printf ("Phy reg %lx ==> %4x\n", i, data); - - /* jump to the next set of regs */ - if (i == 0x07) - i = 0x0f; - - } /* end for loop */ -} /* end dump */ - - -/***********************************************************/ -/* (Re)start autonegotiation */ -/***********************************************************/ -int phy_setup_aneg (char *devname, unsigned char addr) -{ - unsigned short ctl, adv; - - /* Setup standard advertise */ - miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | - PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | - PHY_ANLPAR_10); - miiphy_write (devname, addr, PHY_ANAR, adv); - - /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &ctl); - ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, ctl); - - return 0; -} - - -/***********************************************************/ -/* read a phy reg and return the value with a rc */ -/***********************************************************/ -unsigned int miiphy_getemac_offset (void) -{ -#if (defined(CONFIG_440) && !defined(CONFIG_440SP)) && defined(CONFIG_NET_MULTI) - unsigned long zmii; - unsigned long eoffset; - - /* Need to find out which mdi port we're using */ - zmii = in32 (ZMII_FER); - - if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) { - /* using port 0 */ - eoffset = 0; - } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) { - /* using port 1 */ - eoffset = 0x100; - } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) { - /* using port 2 */ - eoffset = 0x400; - } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) { - /* using port 3 */ - eoffset = 0x600; - } else { - /* None of the mdi ports are enabled! */ - /* enable port 0 */ - zmii |= ZMII_FER_MDI << ZMII_FER_V (0); - out32 (ZMII_FER, zmii); - eoffset = 0; - /* need to soft reset port 0 */ - zmii = in32 (EMAC_M0); - zmii |= EMAC_M0_SRST; - out32 (EMAC_M0, zmii); - } - - return (eoffset); -#else - return 0; -#endif -} - - -int emac4xx_miiphy_read (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - unsigned long sta_reg; /* STA scratch area */ - unsigned long i; - unsigned long emac_reg; - - - emac_reg = miiphy_getemac_offset (); - /* see if it is ready for 1000 nsec */ - i = 0; - - /* see if it is ready for sec */ - while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) { - udelay (7); - if (i > 5) { -#if 0 - printf ("read err 1\n"); -#endif - return -1; - } - i++; - } - sta_reg = reg; /* reg address */ - /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) - sta_reg |= EMAC_STACR_READ; -#else - sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; -#endif - -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) - sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; -#endif - sta_reg = sta_reg | (addr << 5); /* Phy address */ - - out32 (EMAC_STACR + emac_reg, sta_reg); -#if 0 /* test-only */ - printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ -#endif - - sta_reg = in32 (EMAC_STACR + emac_reg); - i = 0; - while ((sta_reg & EMAC_STACR_OC) == 0) { - udelay (7); - if (i > 5) { - return -1; - } - i++; - sta_reg = in32 (EMAC_STACR + emac_reg); - } - if ((sta_reg & EMAC_STACR_PHYE) != 0) { - return -1; - } - - *value = *(short *) (&sta_reg); - return 0; - - -} /* phy_read */ - - -/***********************************************************/ -/* write a phy reg and return the value with a rc */ -/***********************************************************/ - -int emac4xx_miiphy_write (char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - unsigned long sta_reg; /* STA scratch area */ - unsigned long i; - unsigned long emac_reg; - - emac_reg = miiphy_getemac_offset (); - /* see if it is ready for 1000 nsec */ - i = 0; - - while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) { - if (i > 5) - return -1; - udelay (7); - i++; - } - sta_reg = 0; - sta_reg = reg; /* reg address */ - /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) - sta_reg |= EMAC_STACR_WRITE; -#else - sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; -#endif - -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) - sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ -#endif - sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */ - memcpy (&sta_reg, &value, 2); /* put in data */ - - out32 (EMAC_STACR + emac_reg, sta_reg); - - /* wait for completion */ - i = 0; - sta_reg = in32 (EMAC_STACR + emac_reg); - while ((sta_reg & EMAC_STACR_OC) == 0) { - udelay (7); - if (i > 5) - return -1; - i++; - sta_reg = in32 (EMAC_STACR + emac_reg); - } - - if ((sta_reg & EMAC_STACR_PHYE) != 0) - return -1; - return 0; - -} /* phy_write */ diff --git a/cpu/ppc4xx/resetvec.S b/cpu/ppc4xx/resetvec.S deleted file mode 100644 index b3308bd..0000000 --- a/cpu/ppc4xx/resetvec.S +++ /dev/null @@ -1,12 +0,0 @@ -/* Copyright MontaVista Software Incorporated, 2000 */ -#include - .section .resetvec,"ax" -#if defined(CONFIG_440) - b _start_440 -#else -#if defined(CONFIG_BOOT_PCI) && defined(CONFIG_MIP405) - b _start_pci -#else - b _start -#endif -#endif diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c deleted file mode 100644 index e9548cd..0000000 --- a/cpu/ppc4xx/sdram.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - - -#ifdef CONFIG_SDRAM_BANK0 - - -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) - - -struct sdram_conf_s { - unsigned long size; - unsigned long reg; -}; - -typedef struct sdram_conf_s sdram_conf_t; - -#ifndef CFG_SDRAM_TABLE -sdram_conf_t mb0cf[] = { - {(128 << 20), 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */ - {(64 << 20), 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */ - {(32 << 20), 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */ - {(16 << 20), 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */ - {(4 << 20), 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */ -}; -#else -sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE; -#endif - -#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) - - -#ifndef CONFIG_440 - -/* - * Autodetect onboard SDRAM on 405 platforms - */ -void sdram_init(void) -{ - ulong sdtr1; - ulong rtr; - int i; - - /* - * Support for 100MHz and 133MHz SDRAM - */ - if (get_bus_freq(0) > 100000000) { - /* - * 133 MHz SDRAM - */ - sdtr1 = 0x01074015; - rtr = 0x07f00000; - } else { - /* - * default: 100 MHz SDRAM - */ - sdtr1 = 0x0086400d; - rtr = 0x05f00000; - } - - for (i=0; i all done - */ - return; - } - } -} - -#else /* CONFIG_440 */ - -/* - * Autodetect onboard DDR SDRAM on 440 platforms - * - * NOTE: Some of the hardcoded values are hardware dependant, - * so this should be extended for other future boards - * using this routine! - */ -long int initdram(int board_type) -{ - int i; - - for (i=0; i all done - */ - return mb0cf[i].size; - } - } - - return 0; /* nothing found ! */ -} - -#endif /* CONFIG_440 */ - -#endif /* CONFIG_SDRAM_BANK0 */ diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c deleted file mode 100644 index e7f6bcb..0000000 --- a/cpu/ppc4xx/serial.c +++ /dev/null @@ -1,1064 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/*------------------------------------------------------------------------------+ */ -/* - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - */ -/*------------------------------------------------------------------------------- */ -/* - * Travis Sawyer 15 September 2004 - * Added CONFIG_SERIAL_MULTI support - */ -#include -#include -#include -#include -#include "vecnum.h" - -#ifdef CONFIG_SERIAL_MULTI -#include -#endif - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -#include -#endif - -/*****************************************************************************/ -#ifdef CONFIG_IOP480 - -#define SPU_BASE 0x40000000 - -#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */ -#define spu_LineStat_w 0x04 /* Line Status Register (Set) */ -#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */ -#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */ -#define spu_BRateDivh 0x10 /* Baud rate divisor high */ -#define spu_BRateDivl 0x14 /* Baud rate divisor low */ -#define spu_CtlReg 0x18 /* Control Register */ -#define spu_RxCmd 0x1c /* Rx Command Register */ -#define spu_TxCmd 0x20 /* Tx Command Register */ -#define spu_RxBuff 0x24 /* Rx data buffer */ -#define spu_TxBuff 0x24 /* Tx data buffer */ - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncLSRport1 0x40000000 -#define asyncLSRport1set 0x40000004 -#define asyncLSRDataReady 0x80 -#define asyncLSRFramingError 0x40 -#define asyncLSROverrunError 0x20 -#define asyncLSRParityError 0x10 -#define asyncLSRBreakInterrupt 0x08 -#define asyncLSRTxHoldEmpty 0x04 -#define asyncLSRTxShiftEmpty 0x02 - -/*-----------------------------------------------------------------------------+ - | Handshake Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncHSRport1 0x40000008 -#define asyncHSRport1set 0x4000000c -#define asyncHSRDsr 0x80 -#define asyncLSRCts 0x40 - -/*-----------------------------------------------------------------------------+ - | Control Register. - +-----------------------------------------------------------------------------*/ -#define asyncCRport1 0x40000018 -#define asyncCRNormal 0x00 -#define asyncCRLoopback 0x40 -#define asyncCRAutoEcho 0x80 -#define asyncCRDtr 0x20 -#define asyncCRRts 0x10 -#define asyncCRWordLength7 0x00 -#define asyncCRWordLength8 0x08 -#define asyncCRParityDisable 0x00 -#define asyncCRParityEnable 0x04 -#define asyncCREvenParity 0x00 -#define asyncCROddParity 0x02 -#define asyncCRStopBitsOne 0x00 -#define asyncCRStopBitsTwo 0x01 -#define asyncCRDisableDtrRts 0x00 - -/*-----------------------------------------------------------------------------+ - | Receiver Command Register. - +-----------------------------------------------------------------------------*/ -#define asyncRCRport1 0x4000001c -#define asyncRCRDisable 0x00 -#define asyncRCREnable 0x80 -#define asyncRCRIntDisable 0x00 -#define asyncRCRIntEnabled 0x20 -#define asyncRCRDMACh2 0x40 -#define asyncRCRDMACh3 0x60 -#define asyncRCRErrorInt 0x10 -#define asyncRCRPauseEnable 0x08 - -/*-----------------------------------------------------------------------------+ - | Transmitter Command Register. - +-----------------------------------------------------------------------------*/ -#define asyncTCRport1 0x40000020 -#define asyncTCRDisable 0x00 -#define asyncTCREnable 0x80 -#define asyncTCRIntDisable 0x00 -#define asyncTCRIntEnabled 0x20 -#define asyncTCRDMACh2 0x40 -#define asyncTCRDMACh3 0x60 -#define asyncTCRTxEmpty 0x10 -#define asyncTCRErrorInt 0x08 -#define asyncTCRStopPause 0x04 -#define asyncTCRBreakGen 0x02 - -/*-----------------------------------------------------------------------------+ - | Miscellanies defines. - +-----------------------------------------------------------------------------*/ -#define asyncTxBufferport1 0x40000024 -#define asyncRxBufferport1 0x40000024 -#define asyncDLABLsbport1 0x40000014 -#define asyncDLABMsbport1 0x40000010 -#define asyncXOFFchar 0x13 -#define asyncXONchar 0x11 - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -int serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile char val; - unsigned short br_reg; - - br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); - - /* - * Init onboard UART - */ - out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */ - out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ - out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ - out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */ - out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */ - out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */ - out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */ - - return (0); -} - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned short br_reg; - - br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); - - out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ - out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ -} - -void serial_putc (const char c) -{ - if (c == '\n') - serial_putc ('\r'); - - /* load status from handshake register */ - if (in8 (SPU_BASE + spu_Handshk_rc) != 00) - out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - - out8 (SPU_BASE + spu_TxBuff, c); /* Put char */ - - while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) { - if (in8 (SPU_BASE + spu_Handshk_rc) != 00) - out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - } -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc () -{ - unsigned char status = 0; - - while (1) { - status = in8 (asyncLSRport1); - if ((status & asyncLSRDataReady) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt )) != 0) { - (void) out8 (asyncLSRport1, - asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt ); - } - } - return (0x000000ff & (int) in8 (asyncRxBufferport1)); -} - -int serial_tstc () -{ - unsigned char status; - - status = in8 (asyncLSRport1); - if ((status & asyncLSRDataReady) != 0x0) { - return (1); - } - if ((status & ( asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt )) != 0) { - (void) out8 (asyncLSRport1, - asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt); - } - return 0; -} - -#endif /* CONFIG_IOP480 */ - -/*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP) - -#if defined(CONFIG_440) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) -#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 -#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 -#else -#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200 -#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 -#endif - -#if defined(CONFIG_440SP) -#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 -#endif - -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) -#define CR0_MASK 0xdfffffff -#define CR0_EXTCLK_ENA 0x00800000 -#define CR0_UDIV_POS 0 -#else -#define CR0_MASK 0x3fff0000 -#define CR0_EXTCLK_ENA 0x00600000 -#define CR0_UDIV_POS 16 -#endif /* CONFIG_440GX */ -#elif defined(CONFIG_405EP) -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 -#define UCR0_MASK 0x0000007f -#define UCR1_MASK 0x00007f00 -#define UCR0_UDIV_POS 0 -#define UCR1_UDIV_POS 8 -#define UDIV_MAX 127 -#else /* CONFIG_405GP || CONFIG_405CR */ -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 -#define CR0_MASK 0x00001fff -#define CR0_EXTCLK_ENA 0x000000c0 -#define CR0_UDIV_POS 1 -#define UDIV_MAX 32 -#endif - -/* using serial port 0 or 1 as U-Boot console ? */ -#if defined(CONFIG_UART1_CONSOLE) -#define ACTING_UART0_BASE UART1_BASE -#define ACTING_UART1_BASE UART0_BASE -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) -#define UART0_SDR sdr_uart1 -#define UART1_SDR sdr_uart0 -#endif /* CONFIG_440GX */ -#else -#define ACTING_UART0_BASE UART0_BASE -#define ACTING_UART1_BASE UART1_BASE -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 -#endif /* CONFIG_440GX */ -#endif - -#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) -#error "External serial clock not supported on AMCC PPC405EP!" -#endif - -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */ -#define asyncLSRDataReady1 0x01 -#define asyncLSROverrunError1 0x02 -#define asyncLSRParityError1 0x04 -#define asyncLSRFramingError1 0x08 -#define asyncLSRBreakInterrupt1 0x10 -#define asyncLSRTxHoldEmpty1 0x20 -#define asyncLSRTxShiftEmpty1 0x40 -#define asyncLSRRxFifoError1 0x80 - -/*-----------------------------------------------------------------------------+ - | Miscellanies defines. - +-----------------------------------------------------------------------------*/ -/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */ -/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */ - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -/*-----------------------------------------------------------------------------+ - | Fifo - +-----------------------------------------------------------------------------*/ -typedef struct { - char *rx_buffer; - ulong rx_put; - ulong rx_get; -} serial_buffer_t; - -volatile static serial_buffer_t buf_info; -#endif - -#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK) -static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv ) -{ - sys_info_t sysinfo; - unsigned long div; /* total divisor udiv * bdiv */ - unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ - unsigned long i; - unsigned long est; /* current estimate */ - - get_sys_info( &sysinfo ); - - udiv = 32; /* Assume lowest possible serial clk */ - div = sysinfo.freqPLB/(16*baudrate); /* total divisor */ - umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */ - diff = 32; /* highest possible */ - - /* i is the test udiv value -- start with the largest - * possible (32) to minimize serial clock and constrain - * search to umin. - */ - for( i = 32; i > umin; i-- ){ - ibdiv = div/i; - est = i * ibdiv; - idiff = (est > div) ? (est-div) : (div-est); - if( idiff == 0 ){ - udiv = i; - break; /* can't do better */ - } - else if( idiff < diff ){ - udiv = i; /* best so far */ - diff = idiff; /* update lowest diff*/ - } - } - - *pudiv = udiv; - *pbdiv = div/udiv; - -} -#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */ - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -#if defined(CONFIG_440) -#if defined(CONFIG_SERIAL_MULTI) -int serial_init_dev (unsigned long dev_base) -#else -int serial_init(void) -#endif -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned long reg; - unsigned long udiv; - unsigned short bdiv; - volatile char val; -#ifdef CFG_EXT_SERIAL_CLOCK - unsigned long tmp; -#endif - -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) -#if defined(CONFIG_SERIAL_MULTI) - if (UART0_BASE == dev_base) { - mfsdr(UART0_SDR,reg); - reg &= ~CR0_MASK; - } else { - mfsdr(UART1_SDR,reg); - reg &= ~CR0_MASK; - } -#else - mfsdr(UART0_SDR,reg); - reg &= ~CR0_MASK; -#endif -#else - reg = mfdcr(cntrl0) & ~CR0_MASK; -#endif /* CONFIG_440GX */ -#ifdef CFG_EXT_SERIAL_CLOCK - reg |= CR0_EXTCLK_ENA; - udiv = 1; - tmp = gd->baudrate * 16; - bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; -#else - /* For 440, the cpu clock is on divider chain A, UART on divider - * chain B ... so cpu clock is irrelevant. Get the "optimized" - * values that are subject to the 1/2 opb clock constraint - */ - serial_divs (gd->baudrate, &udiv, &bdiv); -#endif - -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) - reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */ -#if defined(CONFIG_SERIAL_MULTI) - if (UART0_BASE == dev_base) { - mtsdr (UART0_SDR,reg); - } else { - mtsdr (UART1_SDR,reg); - } -#else - mtsdr (UART0_SDR,reg); -#endif -#else - reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (cntrl0, reg); -#endif - -#if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ - out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */ - out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (dev_base + UART_LSR); /* clear line status */ - val = in8 (dev_base + UART_RBR); /* read receive buffer */ - out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */ - out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */ -#else - out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ - val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ - out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ -#endif - return (0); -} - -#else /* !defined(CONFIG_440) */ - -#if defined(CONFIG_SERIAL_MULTI) -int serial_init_dev (unsigned long dev_base) -#else -int serial_init (void) -#endif -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned long reg; - unsigned long tmp; - unsigned long clk; - unsigned long udiv; - unsigned short bdiv; - volatile char val; - -#ifdef CONFIG_405EP - reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); - clk = gd->cpu_clk; - tmp = CFG_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; - reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ - reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ - mtdcr (cpc0_ucr, reg); -#else /* CONFIG_405EP */ - reg = mfdcr(cntrl0) & ~CR0_MASK; -#ifdef CFG_EXT_SERIAL_CLOCK - clk = CFG_EXT_SERIAL_CLOCK; - udiv = 1; - reg |= CR0_EXTCLK_ENA; -#else - clk = gd->cpu_clk; -#ifdef CFG_405_UART_ERRATA_59 - udiv = 31; /* Errata 59: stuck at 31 */ -#else - tmp = CFG_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; -#endif -#endif - reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (cntrl0, reg); -#endif /* CONFIG_405EP */ - - tmp = gd->baudrate * udiv * 16; - bdiv = (clk + tmp / 2) / tmp; - -#if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ - out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */ - out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (dev_base + UART_LSR); /* clear line status */ - val = in8 (dev_base + UART_RBR); /* read receive buffer */ - out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */ - out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */ -#else - out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ - val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ - out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ -#endif - return (0); -} - -#endif /* if defined(CONFIG_440) */ - -#if defined(CONFIG_SERIAL_MULTI) -void serial_setbrg_dev (unsigned long dev_base) -#else -void serial_setbrg (void) -#endif -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned long tmp; - unsigned long clk; - unsigned long udiv; - unsigned short bdiv; - -#ifdef CFG_EXT_SERIAL_CLOCK - clk = CFG_EXT_SERIAL_CLOCK; -#else - clk = gd->cpu_clk; -#endif - -#ifdef CONFIG_405EP - udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS); -#else - udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1; -#endif /* CONFIG_405EP */ - tmp = gd->baudrate * udiv * 16; - bdiv = (clk + tmp / 2) / tmp; - -#if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ - out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ -#else - out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ -#endif -} - -#if defined(CONFIG_SERIAL_MULTI) -void serial_putc_dev (unsigned long dev_base, const char c) -#else -void serial_putc (const char c) -#endif -{ - int i; - - if (c == '\n') -#if defined(CONFIG_SERIAL_MULTI) - serial_putc_dev (dev_base, '\r'); -#else - serial_putc ('\r'); -#endif - - /* check THRE bit, wait for transmiter available */ - for (i = 1; i < 3500; i++) { -#if defined(CONFIG_SERIAL_MULTI) - if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20) -#else - if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20) -#endif - break; - udelay (100); - } -#if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_THR, c); /* put character out */ -#else - out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */ -#endif -} - -#if defined(CONFIG_SERIAL_MULTI) -void serial_puts_dev (unsigned long dev_base, const char *s) -#else -void serial_puts (const char *s) -#endif -{ - while (*s) { -#if defined(CONFIG_SERIAL_MULTI) - serial_putc_dev (dev_base, *s++); -#else - serial_putc (*s++); -#endif - } -} - -#if defined(CONFIG_SERIAL_MULTI) -int serial_getc_dev (unsigned long dev_base) -#else -int serial_getc (void) -#endif -{ - unsigned char status = 0; - - while (1) { -#if defined(CONFIG_HW_WATCHDOG) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ -#endif /* CONFIG_HW_WATCHDOG */ -#if defined(CONFIG_SERIAL_MULTI) - status = in8 (dev_base + UART_LSR); -#else - status = in8 (ACTING_UART0_BASE + UART_LSR); -#endif - if ((status & asyncLSRDataReady1) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { -#if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_LSR, -#else - out8 (ACTING_UART0_BASE + UART_LSR, -#endif - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - } -#if defined(CONFIG_SERIAL_MULTI) - return (0x000000ff & (int) in8 (dev_base)); -#else - return (0x000000ff & (int) in8 (ACTING_UART0_BASE)); -#endif -} - -#if defined(CONFIG_SERIAL_MULTI) -int serial_tstc_dev (unsigned long dev_base) -#else -int serial_tstc (void) -#endif -{ - unsigned char status; - -#if defined(CONFIG_SERIAL_MULTI) - status = in8 (dev_base + UART_LSR); -#else - status = in8 (ACTING_UART0_BASE + UART_LSR); -#endif - if ((status & asyncLSRDataReady1) != 0x0) { - return (1); - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { -#if defined(CONFIG_SERIAL_MULTI) - out8 (dev_base + UART_LSR, -#else - out8 (ACTING_UART0_BASE + UART_LSR, -#endif - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - return 0; -} - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - -void serial_isr (void *arg) -{ - int space; - int c; - const int rx_get = buf_info.rx_get; - int rx_put = buf_info.rx_put; - - if (rx_get <= rx_put) { - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - } else { - space = rx_get - rx_put; - } - while (serial_tstc_dev (ACTING_UART0_BASE)) { - c = serial_getc_dev (ACTING_UART0_BASE); - if (space) { - buf_info.rx_buffer[rx_put++] = c; - space--; - } - if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) - rx_put = 0; - if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { - /* Stop flow by setting RTS inactive */ - out8 (ACTING_UART0_BASE + UART_MCR, - in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02)); - } - } - buf_info.rx_put = rx_put; -} - -void serial_buffered_init (void) -{ - serial_puts ("Switching to interrupt driven serial input mode.\n"); - buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); - buf_info.rx_put = 0; - buf_info.rx_get = 0; - - if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) { - serial_puts ("Check CTS signal present on serial port: OK.\n"); - } else { - serial_puts ("WARNING: CTS signal not present on serial port.\n"); - } - - irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , - serial_isr /*interrupt_handler_t *handler */ , - (void *) &buf_info /*void *arg */ ); - - /* Enable "RX Data Available" Interrupt on UART */ - /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */ - out8 (ACTING_UART0_BASE + UART_IER, 0x01); - /* Set DTR active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01); - /* Start flow by setting RTS active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); - /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */ - out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); -} - -void serial_buffered_putc (const char c) -{ - /* Wait for CTS */ -#if defined(CONFIG_HW_WATCHDOG) - while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)) - WATCHDOG_RESET (); -#else - while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)); -#endif - serial_putc (c); -} - -void serial_buffered_puts (const char *s) -{ - serial_puts (s); -} - -int serial_buffered_getc (void) -{ - int space; - int c; - int rx_get = buf_info.rx_get; - int rx_put; - -#if defined(CONFIG_HW_WATCHDOG) - while (rx_get == buf_info.rx_put) - WATCHDOG_RESET (); -#else - while (rx_get == buf_info.rx_put); -#endif - c = buf_info.rx_buffer[rx_get++]; - if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) - rx_get = 0; - buf_info.rx_get = rx_get; - - rx_put = buf_info.rx_put; - if (rx_get <= rx_put) { - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - } else { - space = rx_get - rx_put; - } - if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { - /* Start flow by setting RTS active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); - } - - return c; -} - -int serial_buffered_tstc (void) -{ - return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; -} - -#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -/* - AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port - number 0 or number 1 - - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : - configuration has been already done - - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : - configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE -*/ -#if (CONFIG_KGDB_SER_INDEX & 2) -void kgdb_serial_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - volatile char val; - unsigned short br_reg; - - get_clocks (); - br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) + - 5) / 10; - /* - * Init onboard 16550 UART - */ - out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ - out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ - out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ - out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */ - val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ - out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ -} - -void putDebugChar (const char c) -{ - if (c == '\n') - serial_putc ('\r'); - - out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */ - - /* check THRE bit, wait for transfer done */ - while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); -} - -void putDebugStr (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int getDebugChar (void) -{ - unsigned char status = 0; - - while (1) { - status = in8 (ACTING_UART1_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out8 (ACTING_UART1_BASE + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - } - return (0x000000ff & (int) in8 (ACTING_UART1_BASE)); -} - -void kgdb_interruptible (int yes) -{ - return; -} - -#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ - -void kgdb_serial_init (void) -{ - serial_printf ("[on serial] "); -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ -#endif /* CFG_CMD_KGDB */ - - -#if defined(CONFIG_SERIAL_MULTI) -int serial0_init(void) -{ - return (serial_init_dev(UART0_BASE)); -} - -int serial1_init(void) -{ - return (serial_init_dev(UART1_BASE)); -} -void serial0_setbrg (void) -{ - serial_setbrg_dev(UART0_BASE); -} -void serial1_setbrg (void) -{ - serial_setbrg_dev(UART1_BASE); -} - -void serial0_putc(const char c) -{ - serial_putc_dev(UART0_BASE,c); -} - -void serial1_putc(const char c) -{ - serial_putc_dev(UART1_BASE, c); -} -void serial0_puts(const char *s) -{ - serial_puts_dev(UART0_BASE, s); -} - -void serial1_puts(const char *s) -{ - serial_puts_dev(UART1_BASE, s); -} - -int serial0_getc(void) -{ - return(serial_getc_dev(UART0_BASE)); -} - -int serial1_getc(void) -{ - return(serial_getc_dev(UART1_BASE)); -} -int serial0_tstc(void) -{ - return (serial_tstc_dev(UART0_BASE)); -} - -int serial1_tstc(void) -{ - return (serial_tstc_dev(UART1_BASE)); -} - -struct serial_device serial0_device = -{ - "serial0", - "UART0", - serial0_init, - serial0_setbrg, - serial0_getc, - serial0_tstc, - serial0_putc, - serial0_puts, -}; - -struct serial_device serial1_device = -{ - "serial1", - "UART1", - serial1_init, - serial1_setbrg, - serial1_getc, - serial1_tstc, - serial1_putc, - serial1_puts, -}; -#endif /* CONFIG_SERIAL_MULTI */ - -#endif /* CONFIG_405GP || CONFIG_405CR */ diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c deleted file mode 100644 index ebd5f39..0000000 --- a/cpu/ppc4xx/spd_sdram.c +++ /dev/null @@ -1,1831 +0,0 @@ -/* - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com - * - * Based on code by: - * - * Kenneth Johansson ,Ericsson AB. - * kenneth.johansson@etx.ericsson.se - * - * hacked up by bill hunter. fixed so we could run before - * serial_init and console_init. previous version avoided this by - * running out of cache memory during serial/console init, then running - * this code later. - * - * (C) Copyright 2002 - * Jun Gu, Artesyn Technology, jung@artesyncp.com - * Support for AMCC 440 based on OpenBIOS draminit.c from IBM. - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#ifdef CONFIG_SPD_EEPROM - -/* - * Set default values - */ -#ifndef CFG_I2C_SPEED -#define CFG_I2C_SPEED 50000 -#endif - -#ifndef CFG_I2C_SLAVE -#define CFG_I2C_SLAVE 0xFE -#endif - -#define ONE_BILLION 1000000000 - -#ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */ - -#define SDRAM0_CFG_DCE 0x80000000 -#define SDRAM0_CFG_SRE 0x40000000 -#define SDRAM0_CFG_PME 0x20000000 -#define SDRAM0_CFG_MEMCHK 0x10000000 -#define SDRAM0_CFG_REGEN 0x08000000 -#define SDRAM0_CFG_ECCDD 0x00400000 -#define SDRAM0_CFG_EMDULR 0x00200000 -#define SDRAM0_CFG_DRW_SHIFT (31-6) -#define SDRAM0_CFG_BRPF_SHIFT (31-8) - -#define SDRAM0_TR_CASL_SHIFT (31-8) -#define SDRAM0_TR_PTA_SHIFT (31-13) -#define SDRAM0_TR_CTP_SHIFT (31-15) -#define SDRAM0_TR_LDF_SHIFT (31-17) -#define SDRAM0_TR_RFTA_SHIFT (31-29) -#define SDRAM0_TR_RCD_SHIFT (31-31) - -#define SDRAM0_RTR_SHIFT (31-15) -#define SDRAM0_ECCCFG_SHIFT (31-11) - -/* SDRAM0_CFG enable macro */ -#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT ) - -#define SDRAM0_BXCR_SZ_MASK 0x000e0000 -#define SDRAM0_BXCR_AM_MASK 0x0000e000 - -#define SDRAM0_BXCR_SZ_SHIFT (31-14) -#define SDRAM0_BXCR_AM_SHIFT (31-18) - -#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) ) -#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) ) - -#ifdef CONFIG_SPDDRAM_SILENT -# define SPD_ERR(x) do { return 0; } while (0) -#else -# define SPD_ERR(x) do { printf(x); return(0); } while (0) -#endif - -#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) - -/* function prototypes */ -int spd_read(uint addr); - - -/* - * This function is reading data from the DIMM module EEPROM over the SPD bus - * and uses that to program the sdram controller. - * - * This works on boards that has the same schematics that the AMCC walnut has. - * - * Input: null for default I2C spd functions or a pointer to a custom function - * returning spd_data. - */ - -long int spd_sdram(int(read_spd)(uint addr)) -{ - int tmp,row,col; - int total_size,bank_size,bank_code; - int ecc_on; - int mode; - int bank_cnt; - - int sdram0_pmit=0x07c00000; -#ifndef CONFIG_405EP /* not on PPC405EP */ - int sdram0_besr0=-1; - int sdram0_besr1=-1; - int sdram0_eccesr=-1; -#endif - int sdram0_ecccfg; - - int sdram0_rtr=0; - int sdram0_tr=0; - - int sdram0_b0cr; - int sdram0_b1cr; - int sdram0_b2cr; - int sdram0_b3cr; - - int sdram0_cfg=0; - - int t_rp; - int t_rcd; - int t_ras; - int t_rc; - int min_cas; - - PPC405_SYS_INFO sys_info; - unsigned long bus_period_x_10; - - /* - * get the board info - */ - get_sys_info(&sys_info); - bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); - - if (read_spd == 0){ - read_spd=spd_read; - /* - * Make sure I2C controller is initialized - * before continuing. - */ - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); - } - - /* Make shure we are using SDRAM */ - if (read_spd(2) != 0x04) { - SPD_ERR("SDRAM - non SDRAM memory module found\n"); - } - - /* ------------------------------------------------------------------ - * configure memory timing register - * - * data from DIMM: - * 27 IN Row Precharge Time ( t RP) - * 29 MIN RAS to CAS Delay ( t RCD) - * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS - * -------------------------------------------------------------------*/ - - /* - * first figure out which cas latency mode to use - * use the min supported mode - */ - - tmp = read_spd(127) & 0x6; - if (tmp == 0x02) { /* only cas = 2 supported */ - min_cas = 2; -/* t_ck = read_spd(9); */ -/* t_ac = read_spd(10); */ - } else if (tmp == 0x04) { /* only cas = 3 supported */ - min_cas = 3; -/* t_ck = read_spd(9); */ -/* t_ac = read_spd(10); */ - } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */ - min_cas = 2; -/* t_ck = read_spd(23); */ -/* t_ac = read_spd(24); */ - } else { - SPD_ERR("SDRAM - unsupported CAS latency \n"); - } - - /* get some timing values, t_rp,t_rcd,t_ras,t_rc - */ - t_rp = read_spd(27); - t_rcd = read_spd(29); - t_ras = read_spd(30); - t_rc = t_ras + t_rp; - - /* The following timing calcs subtract 1 before deviding. - * this has effect of using ceiling instead of floor rounding, - * and also subtracting 1 to convert number to reg value - */ - /* set up CASL */ - sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT; - /* set up PTA */ - sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT; - /* set up CTP */ - tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3; - if (tmp < 1) - tmp = 1; - sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT; - /* set LDF = 2 cycles, reg value = 1 */ - sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT; - /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */ - tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3; - if (tmp < 0) - tmp = 0; - if (tmp > 6) - tmp = 6; - sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT; - /* set RCD = t_rcd/bus_period*/ - sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ; - - - /*------------------------------------------------------------------ - * configure RTR register - * -------------------------------------------------------------------*/ - row = read_spd(3); - col = read_spd(4); - tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */ - switch (tmp) { - case 0x00: - tmp = 15625; - break; - case 0x01: - tmp = 15625 / 4; - break; - case 0x02: - tmp = 15625 / 2; - break; - case 0x03: - tmp = 15625 * 2; - break; - case 0x04: - tmp = 15625 * 4; - break; - case 0x05: - tmp = 15625 * 8; - break; - default: - SPD_ERR("SDRAM - Bad refresh period \n"); - } - /* convert from nsec to bus cycles */ - tmp = (tmp * 10) / bus_period_x_10; - sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT; - - /*------------------------------------------------------------------ - * determine the number of banks used - * -------------------------------------------------------------------*/ - /* byte 7:6 is module data width */ - if (read_spd(7) != 0) - SPD_ERR("SDRAM - unsupported module width\n"); - tmp = read_spd(6); - if (tmp < 32) - SPD_ERR("SDRAM - unsupported module width\n"); - else if (tmp < 64) - bank_cnt = 1; /* one bank per sdram side */ - else if (tmp < 73) - bank_cnt = 2; /* need two banks per side */ - else if (tmp < 161) - bank_cnt = 4; /* need four banks per side */ - else - SPD_ERR("SDRAM - unsupported module width\n"); - - /* byte 5 is the module row count (refered to as dimm "sides") */ - tmp = read_spd(5); - if (tmp == 1) - ; - else if (tmp==2) - bank_cnt *= 2; - else if (tmp==4) - bank_cnt *= 4; - else - bank_cnt = 8; /* 8 is an error code */ - - if (bank_cnt > 4) /* we only have 4 banks to work with */ - SPD_ERR("SDRAM - unsupported module rows for this width\n"); - - /* now check for ECC ability of module. We only support ECC - * on 32 bit wide devices with 8 bit ECC. - */ - if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) { - sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT; - ecc_on = 1; - } else { - sdram0_ecccfg = 0; - ecc_on = 0; - } - - /*------------------------------------------------------------------ - * calculate total size - * -------------------------------------------------------------------*/ - /* calculate total size and do sanity check */ - tmp = read_spd(31); - total_size = 1 << 22; /* total_size = 4MB */ - /* now multiply 4M by the smallest device row density */ - /* note that we don't support asymetric rows */ - while (((tmp & 0x0001) == 0) && (tmp != 0)) { - total_size = total_size << 1; - tmp = tmp >> 1; - } - total_size *= read_spd(5); /* mult by module rows (dimm sides) */ - - /*------------------------------------------------------------------ - * map rows * cols * banks to a mode - * -------------------------------------------------------------------*/ - - switch (row) { - case 11: - switch (col) { - case 8: - mode=4; /* mode 5 */ - break; - case 9: - case 10: - mode=0; /* mode 1 */ - break; - default: - SPD_ERR("SDRAM - unsupported mode\n"); - } - break; - case 12: - switch (col) { - case 8: - mode=3; /* mode 4 */ - break; - case 9: - case 10: - mode=1; /* mode 2 */ - break; - default: - SPD_ERR("SDRAM - unsupported mode\n"); - } - break; - case 13: - switch (col) { - case 8: - mode=5; /* mode 6 */ - break; - case 9: - case 10: - if (read_spd(17) == 2) - mode = 6; /* mode 7 */ - else - mode = 2; /* mode 3 */ - break; - case 11: - mode = 2; /* mode 3 */ - break; - default: - SPD_ERR("SDRAM - unsupported mode\n"); - } - break; - default: - SPD_ERR("SDRAM - unsupported mode\n"); - } - - /*------------------------------------------------------------------ - * using the calculated values, compute the bank - * config register values. - * -------------------------------------------------------------------*/ - sdram0_b1cr = 0; - sdram0_b2cr = 0; - sdram0_b3cr = 0; - - /* compute the size of each bank */ - bank_size = total_size / bank_cnt; - /* convert bank size to bank size code for ppc4xx - by takeing log2(bank_size) - 22 */ - tmp = bank_size; /* start with tmp = bank_size */ - bank_code = 0; /* and bank_code = 0 */ - while (tmp > 1) { /* this takes log2 of tmp */ - bank_code++; /* and stores result in bank_code */ - tmp = tmp >> 1; - } /* bank_code is now log2(bank_size) */ - bank_code -= 22; /* subtract 22 to get the code */ - - tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1; - sdram0_b0cr = (bank_size * 0) | tmp; -#ifndef CONFIG_405EP /* not on PPC405EP */ - if (bank_cnt > 1) - sdram0_b2cr = (bank_size * 1) | tmp; - if (bank_cnt > 2) - sdram0_b1cr = (bank_size * 2) | tmp; - if (bank_cnt > 3) - sdram0_b3cr = (bank_size * 3) | tmp; -#else - /* PPC405EP chip only supports two SDRAM banks */ - if (bank_cnt > 1) - sdram0_b1cr = (bank_size * 1) | tmp; - if (bank_cnt > 2) - total_size = 2 * bank_size; -#endif - - /* - * enable sdram controller DCE=1 - * enable burst read prefetch to 32 bytes BRPF=2 - * leave other functions off - */ - - /*------------------------------------------------------------------ - * now that we've done our calculations, we are ready to - * program all the registers. - * -------------------------------------------------------------------*/ - -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) - /* disable memcontroller so updates work */ - mtsdram0( mem_mcopt1, 0 ); - -#ifndef CONFIG_405EP /* not on PPC405EP */ - mtsdram0( mem_besra , sdram0_besr0 ); - mtsdram0( mem_besrb , sdram0_besr1 ); - mtsdram0( mem_ecccf , sdram0_ecccfg ); - mtsdram0( mem_eccerr, sdram0_eccesr ); -#endif - mtsdram0( mem_rtr , sdram0_rtr ); - mtsdram0( mem_pmit , sdram0_pmit ); - mtsdram0( mem_mb0cf , sdram0_b0cr ); - mtsdram0( mem_mb1cf , sdram0_b1cr ); -#ifndef CONFIG_405EP /* not on PPC405EP */ - mtsdram0( mem_mb2cf , sdram0_b2cr ); - mtsdram0( mem_mb3cf , sdram0_b3cr ); -#endif - mtsdram0( mem_sdtr1 , sdram0_tr ); - - /* SDRAM have a power on delay, 500 micro should do */ - udelay(500); - sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; - if (ecc_on) - sdram0_cfg |= SDRAM0_CFG_MEMCHK; - mtsdram0(mem_mcopt1, sdram0_cfg); - - return (total_size); -} - -int spd_read(uint addr) -{ - uchar data[2]; - - if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0) - return (int)data[0]; - else - return 0; -} - -#else /* CONFIG_440 */ - -/*----------------------------------------------------------------------------- - | Memory Controller Options 0 - +-----------------------------------------------------------------------------*/ -#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ -#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ -#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ -#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ -#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ -#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ -#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ -#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ -#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ -#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ -#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ -#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ - -/*----------------------------------------------------------------------------- - | Memory Controller Options 1 - +-----------------------------------------------------------------------------*/ -#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ -#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ - -/*-----------------------------------------------------------------------------+ - | SDRAM DEVPOT Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_DEVOPT_DLL 0x80000000 -#define SDRAM_DEVOPT_DS 0x40000000 - -/*-----------------------------------------------------------------------------+ - | SDRAM MCSTS Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_MCSTS_MRSC 0x80000000 -#define SDRAM_MCSTS_SRMS 0x40000000 -#define SDRAM_MCSTS_CIS 0x20000000 - -/*----------------------------------------------------------------------------- - | SDRAM Refresh Timer Register - +-----------------------------------------------------------------------------*/ -#define SDRAM_RTR_RINT_MASK 0xFFFF0000 -#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK) -#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) - -/*-----------------------------------------------------------------------------+ - | SDRAM UABus Base Address Reg - +-----------------------------------------------------------------------------*/ -#define SDRAM_UABBA_UBBA_MASK 0x0000000F - -/*-----------------------------------------------------------------------------+ - | Memory Bank 0-7 configuration - +-----------------------------------------------------------------------------*/ -#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ -#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ -#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ -#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ -#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ -#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ -#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ -#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ -#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ -#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ -#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ -#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ -#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ -#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ -#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ - -/*-----------------------------------------------------------------------------+ - | SDRAM TR0 Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_TR0_SDWR_MASK 0x80000000 -#define SDRAM_TR0_SDWR_2_CLK 0x00000000 -#define SDRAM_TR0_SDWR_3_CLK 0x80000000 -#define SDRAM_TR0_SDWD_MASK 0x40000000 -#define SDRAM_TR0_SDWD_0_CLK 0x00000000 -#define SDRAM_TR0_SDWD_1_CLK 0x40000000 -#define SDRAM_TR0_SDCL_MASK 0x01800000 -#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 -#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 -#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 -#define SDRAM_TR0_SDPA_MASK 0x000C0000 -#define SDRAM_TR0_SDPA_2_CLK 0x00040000 -#define SDRAM_TR0_SDPA_3_CLK 0x00080000 -#define SDRAM_TR0_SDPA_4_CLK 0x000C0000 -#define SDRAM_TR0_SDCP_MASK 0x00030000 -#define SDRAM_TR0_SDCP_2_CLK 0x00000000 -#define SDRAM_TR0_SDCP_3_CLK 0x00010000 -#define SDRAM_TR0_SDCP_4_CLK 0x00020000 -#define SDRAM_TR0_SDCP_5_CLK 0x00030000 -#define SDRAM_TR0_SDLD_MASK 0x0000C000 -#define SDRAM_TR0_SDLD_1_CLK 0x00000000 -#define SDRAM_TR0_SDLD_2_CLK 0x00004000 -#define SDRAM_TR0_SDRA_MASK 0x0000001C -#define SDRAM_TR0_SDRA_6_CLK 0x00000000 -#define SDRAM_TR0_SDRA_7_CLK 0x00000004 -#define SDRAM_TR0_SDRA_8_CLK 0x00000008 -#define SDRAM_TR0_SDRA_9_CLK 0x0000000C -#define SDRAM_TR0_SDRA_10_CLK 0x00000010 -#define SDRAM_TR0_SDRA_11_CLK 0x00000014 -#define SDRAM_TR0_SDRA_12_CLK 0x00000018 -#define SDRAM_TR0_SDRA_13_CLK 0x0000001C -#define SDRAM_TR0_SDRD_MASK 0x00000003 -#define SDRAM_TR0_SDRD_2_CLK 0x00000001 -#define SDRAM_TR0_SDRD_3_CLK 0x00000002 -#define SDRAM_TR0_SDRD_4_CLK 0x00000003 - -/*-----------------------------------------------------------------------------+ - | SDRAM TR1 Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_TR1_RDSS_MASK 0xC0000000 -#define SDRAM_TR1_RDSS_TR0 0x00000000 -#define SDRAM_TR1_RDSS_TR1 0x40000000 -#define SDRAM_TR1_RDSS_TR2 0x80000000 -#define SDRAM_TR1_RDSS_TR3 0xC0000000 -#define SDRAM_TR1_RDSL_MASK 0x00C00000 -#define SDRAM_TR1_RDSL_STAGE1 0x00000000 -#define SDRAM_TR1_RDSL_STAGE2 0x00400000 -#define SDRAM_TR1_RDSL_STAGE3 0x00800000 -#define SDRAM_TR1_RDCD_MASK 0x00000800 -#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 -#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 -#define SDRAM_TR1_RDCT_MASK 0x000001FF -#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) -#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) -#define SDRAM_TR1_RDCT_MIN 0x00000000 -#define SDRAM_TR1_RDCT_MAX 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM WDDCTR Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 -#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 -#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 -#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 -#define SDRAM_WDDCTR_DCD_MASK 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM CLKTR Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 -#define SDRAM_CLKTR_CLKP_0DEG 0x00000000 -#define SDRAM_CLKTR_CLKP_90DEG 0x40000000 -#define SDRAM_CLKTR_CLKP_180DEG 0x80000000 -#define SDRAM_CLKTR_DCDT_MASK 0x000001FF - -/*-----------------------------------------------------------------------------+ - | SDRAM DLYCAL Options - +-----------------------------------------------------------------------------*/ -#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC -#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) -#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) - -/*-----------------------------------------------------------------------------+ - | General Definition - +-----------------------------------------------------------------------------*/ -#define DEFAULT_SPD_ADDR1 0x53 -#define DEFAULT_SPD_ADDR2 0x52 -#define MAXBANKS 4 /* at most 4 dimm banks */ -#define MAX_SPD_BYTES 256 -#define NUMHALFCYCLES 4 -#define NUMMEMTESTS 8 -#define NUMMEMWORDS 8 -#define MAXBXCR 4 -#define TRUE 1 -#define FALSE 0 - -const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { - {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF}, - {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000}, - {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555}, - {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA}, - {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A}, - {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5}, - {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA}, - {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55} -}; - -/* bank_parms is used to sort the bank sizes by descending order */ -struct bank_param { - unsigned long cr; - unsigned long bank_size_bytes; -}; - -typedef struct bank_param BANKPARMS; - -#ifdef CFG_SIMULATE_SPD_EEPROM -extern unsigned char cfg_simulate_spd_eeprom[128]; -#endif - -unsigned char spd_read(uchar chip, uint addr); - -void get_spd_info(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void check_mem_type -(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void check_volt_type -(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void program_cfg0(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void program_cfg1(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void program_rtr (unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void program_tr0 (unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -void program_tr1 (void); - -void program_ecc (unsigned long num_bytes); - -unsigned -long program_bxcr(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks); - -/* - * This function is reading data from the DIMM module EEPROM over the SPD bus - * and uses that to program the sdram controller. - * - * This works on boards that has the same schematics that the AMCC walnut has. - * - * BUG: Don't handle ECC memory - * BUG: A few values in the TR register is currently hardcoded - */ - -long int spd_sdram(void) { - unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; - unsigned long dimm_populated[sizeof(iic0_dimm_addr)]; - unsigned long total_size; - unsigned long cfg0; - unsigned long mcsts; - unsigned long num_dimm_banks; /* on board dimm banks */ - - num_dimm_banks = sizeof(iic0_dimm_addr); - - /* - * Make sure I2C controller is initialized - * before continuing. - */ - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); - - /* - * Read the SPD information using I2C interface. Check to see if the - * DIMM slots are populated. - */ - get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * Check the memory type for the dimms plugged. - */ - check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * Check the voltage type for the dimms plugged. - */ - check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); - -#if defined(CONFIG_440GX) - /* - * Soft-reset SDRAM controller. - */ - mtsdr(sdr_srst, SDR0_SRST_DMC); - mtsdr(sdr_srst, 0x00000000); -#endif - - /* - * program 440GP SDRAM controller options (SDRAM0_CFG0) - */ - program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * program 440GP SDRAM controller options (SDRAM0_CFG1) - */ - program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * program SDRAM refresh register (SDRAM0_RTR) - */ - program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * program SDRAM Timing Register 0 (SDRAM0_TR0) - */ - program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks); - - /* - * program the BxCR registers to find out total sdram installed - */ - total_size = program_bxcr(dimm_populated, iic0_dimm_addr, - num_dimm_banks); - - /* - * program SDRAM Clock Timing Register (SDRAM0_CLKTR) - */ - mtsdram(mem_clktr, 0x40000000); - - /* - * delay to ensure 200 usec has elapsed - */ - udelay(400); - - /* - * enable the memory controller - */ - mfsdram(mem_cfg0, cfg0); - mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN); - - /* - * wait for SDRAM_CFG0_DC_EN to complete - */ - while (1) { - mfsdram(mem_mcsts, mcsts); - if ((mcsts & SDRAM_MCSTS_MRSC) != 0) { - break; - } - } - - /* - * program SDRAM Timing Register 1, adding some delays - */ - program_tr1(); - - /* - * if ECC is enabled, initialize parity bits - */ - - return total_size; -} - -unsigned char spd_read(uchar chip, uint addr) -{ - unsigned char data[2]; - -#ifdef CFG_SIMULATE_SPD_EEPROM - if (chip == CFG_SIMULATE_SPD_EEPROM) { - /* - * Onboard spd eeprom requested -> simulate values - */ - return cfg_simulate_spd_eeprom[addr]; - } -#endif /* CFG_SIMULATE_SPD_EEPROM */ - - if (i2c_probe(chip) == 0) { - if (i2c_read(chip, addr, 1, data, 1) == 0) { - return data[0]; - } - } - - return 0; -} - -void get_spd_info(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long dimm_found; - unsigned char num_of_bytes; - unsigned char total_size; - - dimm_found = FALSE; - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - num_of_bytes = 0; - total_size = 0; - - num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); - total_size = spd_read(iic0_dimm_addr[dimm_num], 1); - - if ((num_of_bytes != 0) && (total_size != 0)) { - dimm_populated[dimm_num] = TRUE; - dimm_found = TRUE; -#if 0 - printf("DIMM slot %lu: populated\n", dimm_num); -#endif - } else { - dimm_populated[dimm_num] = FALSE; -#if 0 - printf("DIMM slot %lu: Not populated\n", dimm_num); -#endif - } - } - - if (dimm_found == FALSE) { - printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); - hang(); - } -} - -void check_mem_type(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned char dimm_type; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); - switch (dimm_type) { - case 7: -#if 0 - printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num); -#endif - break; - default: - printf("ERROR: Unsupported DIMM detected in slot %lu.\n", - dimm_num); - printf("Only DDR SDRAM DIMMs are supported.\n"); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); - break; - } - } - } -} - - -void check_volt_type(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long voltage_type; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); - if (voltage_type != 0x04) { - printf("ERROR: DIMM %lu with unsupported voltage level.\n", - dimm_num); - hang(); - } else { -#if 0 - printf("DIMM %lu voltage level supported.\n", dimm_num); -#endif - } - break; - } - } -} - -void program_cfg0(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long cfg0; - unsigned long ecc_enabled; - unsigned char ecc; - unsigned char attributes; - unsigned long data_width; - unsigned long dimm_32bit; - unsigned long dimm_64bit; - - /* - * get Memory Controller Options 0 data - */ - mfsdram(mem_cfg0, cfg0); - - /* - * clear bits - */ - cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK | - SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD | - SDRAM_CFG0_DMWD_MASK | - SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP); - - - /* - * FIXME: assume the DDR SDRAMs in both banks are the same - */ - ecc_enabled = TRUE; - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - ecc = spd_read(iic0_dimm_addr[dimm_num], 11); - if (ecc != 0x02) { - ecc_enabled = FALSE; - } - - /* - * program Registered DIMM Enable - */ - attributes = spd_read(iic0_dimm_addr[dimm_num], 21); - if ((attributes & 0x02) != 0x00) { - cfg0 |= SDRAM_CFG0_RDEN; - } - - /* - * program DDR SDRAM Data Width - */ - data_width = - (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) + - (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8); - if (data_width == 64 || data_width == 72) { - dimm_64bit = TRUE; - cfg0 |= SDRAM_CFG0_DMWD_64; - } else if (data_width == 32 || data_width == 40) { - dimm_32bit = TRUE; - cfg0 |= SDRAM_CFG0_DMWD_32; - } else { - printf("WARNING: DIMM with datawidth of %lu bits.\n", - data_width); - printf("Only DIMMs with 32 or 64 bit datawidths supported.\n"); - hang(); - } - break; - } - } - - /* - * program Memory Data Error Checking - */ - if (ecc_enabled == TRUE) { - cfg0 |= SDRAM_CFG0_MCHK_GEN; - } else { - cfg0 |= SDRAM_CFG0_MCHK_NON; - } - - /* - * program Page Management Unit - */ - cfg0 |= SDRAM_CFG0_PMUD; - - /* - * program Memory Controller Options 0 - * Note: DCEN must be enabled after all DDR SDRAM controller - * configuration registers get initialized. - */ - mtsdram(mem_cfg0, cfg0); -} - -void program_cfg1(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long cfg1; - mfsdram(mem_cfg1, cfg1); - - /* - * Self-refresh exit, disable PM - */ - cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN); - - /* - * program Memory Controller Options 1 - */ - mtsdram(mem_cfg1, cfg1); -} - -void program_rtr (unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long bus_period_x_10; - unsigned long refresh_rate = 0; - unsigned char refresh_rate_type; - unsigned long refresh_interval; - unsigned long sdram_rtr; - PPC440_SYS_INFO sys_info; - - /* - * get the board info - */ - get_sys_info(&sys_info); - bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); - - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12); - switch (refresh_rate_type) { - case 0x00: - refresh_rate = 15625; - break; - case 0x01: - refresh_rate = 15625/4; - break; - case 0x02: - refresh_rate = 15625/2; - break; - case 0x03: - refresh_rate = 15626*2; - break; - case 0x04: - refresh_rate = 15625*4; - break; - case 0x05: - refresh_rate = 15625*8; - break; - default: - printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n", - dimm_num); - printf("Replace the DIMM module with a supported DIMM.\n"); - break; - } - - break; - } - } - - refresh_interval = refresh_rate * 10 / bus_period_x_10; - sdram_rtr = (refresh_interval & 0x3ff8) << 16; - - /* - * program Refresh Timer Register (SDRAM0_RTR) - */ - mtsdram(mem_rtr, sdram_rtr); -} - -void program_tr0 (unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long tr0; - unsigned char wcsbc; - unsigned char t_rp_ns; - unsigned char t_rcd_ns; - unsigned char t_ras_ns; - unsigned long t_rp_clk; - unsigned long t_ras_rcd_clk; - unsigned long t_rcd_clk; - unsigned long t_rfc_clk; - unsigned long plb_check; - unsigned char cas_bit; - unsigned long cas_index; - unsigned char cas_2_0_available; - unsigned char cas_2_5_available; - unsigned char cas_3_0_available; - unsigned long cycle_time_ns_x_10[3]; - unsigned long tcyc_3_0_ns_x_10; - unsigned long tcyc_2_5_ns_x_10; - unsigned long tcyc_2_0_ns_x_10; - unsigned long tcyc_reg; - unsigned long bus_period_x_10; - PPC440_SYS_INFO sys_info; - unsigned long residue; - - /* - * get the board info - */ - get_sys_info(&sys_info); - bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); - - /* - * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits - */ - mfsdram(mem_tr0, tr0); - tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK | - SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK | - SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK | - SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK); - - /* - * initialization - */ - wcsbc = 0; - t_rp_ns = 0; - t_rcd_ns = 0; - t_ras_ns = 0; - cas_2_0_available = TRUE; - cas_2_5_available = TRUE; - cas_3_0_available = TRUE; - tcyc_2_0_ns_x_10 = 0; - tcyc_2_5_ns_x_10 = 0; - tcyc_3_0_ns_x_10 = 0; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15); - t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; - t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2; - t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30); - cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); - - for (cas_index = 0; cas_index < 3; cas_index++) { - switch (cas_index) { - case 0: - tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); - break; - case 1: - tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23); - break; - default: - tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25); - break; - } - - if ((tcyc_reg & 0x0F) >= 10) { - printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n", - dimm_num); - hang(); - } - - cycle_time_ns_x_10[cas_index] = - (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F); - } - - cas_index = 0; - - if ((cas_bit & 0x80) != 0) { - cas_index += 3; - } else if ((cas_bit & 0x40) != 0) { - cas_index += 2; - } else if ((cas_bit & 0x20) != 0) { - cas_index += 1; - } - - if (((cas_bit & 0x10) != 0) && (cas_index < 3)) { - tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; - cas_index++; - } else { - if (cas_index != 0) { - cas_index++; - } - cas_3_0_available = FALSE; - } - - if (((cas_bit & 0x08) != 0) || (cas_index < 3)) { - tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index]; - cas_index++; - } else { - if (cas_index != 0) { - cas_index++; - } - cas_2_5_available = FALSE; - } - - if (((cas_bit & 0x04) != 0) || (cas_index < 3)) { - tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; - cas_index++; - } else { - if (cas_index != 0) { - cas_index++; - } - cas_2_0_available = FALSE; - } - - break; - } - } - - /* - * Program SD_WR and SD_WCSBC fields - */ - tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */ - switch (wcsbc) { - case 0: - tr0 |= SDRAM_TR0_SDWD_0_CLK; - break; - default: - tr0 |= SDRAM_TR0_SDWD_1_CLK; - break; - } - - /* - * Program SD_CASL field - */ - if ((cas_2_0_available == TRUE) && - (bus_period_x_10 >= tcyc_2_0_ns_x_10)) { - tr0 |= SDRAM_TR0_SDCL_2_0_CLK; - } else if ((cas_2_5_available == TRUE) && - (bus_period_x_10 >= tcyc_2_5_ns_x_10)) { - tr0 |= SDRAM_TR0_SDCL_2_5_CLK; - } else if ((cas_3_0_available == TRUE) && - (bus_period_x_10 >= tcyc_3_0_ns_x_10)) { - tr0 |= SDRAM_TR0_SDCL_3_0_CLK; - } else { - printf("ERROR: No supported CAS latency with the installed DIMMs.\n"); - printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); - printf("Make sure the PLB speed is within the supported range.\n"); - hang(); - } - - /* - * Calculate Trp in clock cycles and round up if necessary - * Program SD_PTA field - */ - t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION; - plb_check = ONE_BILLION * t_rp_clk / t_rp_ns; - if (sys_info.freqPLB != plb_check) { - t_rp_clk++; - } - switch ((unsigned long)t_rp_clk) { - case 0: - case 1: - case 2: - tr0 |= SDRAM_TR0_SDPA_2_CLK; - break; - case 3: - tr0 |= SDRAM_TR0_SDPA_3_CLK; - break; - default: - tr0 |= SDRAM_TR0_SDPA_4_CLK; - break; - } - - /* - * Program SD_CTP field - */ - t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION; - plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns); - if (sys_info.freqPLB != plb_check) { - t_ras_rcd_clk++; - } - switch (t_ras_rcd_clk) { - case 0: - case 1: - case 2: - tr0 |= SDRAM_TR0_SDCP_2_CLK; - break; - case 3: - tr0 |= SDRAM_TR0_SDCP_3_CLK; - break; - case 4: - tr0 |= SDRAM_TR0_SDCP_4_CLK; - break; - default: - tr0 |= SDRAM_TR0_SDCP_5_CLK; - break; - } - - /* - * Program SD_LDF field - */ - tr0 |= SDRAM_TR0_SDLD_2_CLK; - - /* - * Program SD_RFTA field - * FIXME tRFC hardcoded as 75 nanoseconds - */ - t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75); - residue = sys_info.freqPLB % (ONE_BILLION / 75); - if (residue >= (ONE_BILLION / 150)) { - t_rfc_clk++; - } - switch (t_rfc_clk) { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - tr0 |= SDRAM_TR0_SDRA_6_CLK; - break; - case 7: - tr0 |= SDRAM_TR0_SDRA_7_CLK; - break; - case 8: - tr0 |= SDRAM_TR0_SDRA_8_CLK; - break; - case 9: - tr0 |= SDRAM_TR0_SDRA_9_CLK; - break; - case 10: - tr0 |= SDRAM_TR0_SDRA_10_CLK; - break; - case 11: - tr0 |= SDRAM_TR0_SDRA_11_CLK; - break; - case 12: - tr0 |= SDRAM_TR0_SDRA_12_CLK; - break; - default: - tr0 |= SDRAM_TR0_SDRA_13_CLK; - break; - } - - /* - * Program SD_RCD field - */ - t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION; - plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns; - if (sys_info.freqPLB != plb_check) { - t_rcd_clk++; - } - switch (t_rcd_clk) { - case 0: - case 1: - case 2: - tr0 |= SDRAM_TR0_SDRD_2_CLK; - break; - case 3: - tr0 |= SDRAM_TR0_SDRD_3_CLK; - break; - default: - tr0 |= SDRAM_TR0_SDRD_4_CLK; - break; - } - -#if 0 - printf("tr0: %x\n", tr0); -#endif - mtsdram(mem_tr0, tr0); -} - -void program_tr1 (void) -{ - unsigned long tr0; - unsigned long tr1; - unsigned long cfg0; - unsigned long ecc_temp; - unsigned long dlycal; - unsigned long dly_val; - unsigned long i, j, k; - unsigned long bxcr_num; - unsigned long max_pass_length; - unsigned long current_pass_length; - unsigned long current_fail_length; - unsigned long current_start; - unsigned long rdclt; - unsigned long rdclt_offset; - long max_start; - long max_end; - long rdclt_average; - unsigned char window_found; - unsigned char fail_found; - unsigned char pass_found; - unsigned long * membase; - PPC440_SYS_INFO sys_info; - - /* - * get the board info - */ - get_sys_info(&sys_info); - - /* - * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits - */ - mfsdram(mem_tr1, tr1); - tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK | - SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK); - - mfsdram(mem_tr0, tr0); - if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) && - (sys_info.freqPLB > 100000000)) { - tr1 |= SDRAM_TR1_RDSS_TR2; - tr1 |= SDRAM_TR1_RDSL_STAGE3; - tr1 |= SDRAM_TR1_RDCD_RCD_1_2; - } else { - tr1 |= SDRAM_TR1_RDSS_TR1; - tr1 |= SDRAM_TR1_RDSL_STAGE2; - tr1 |= SDRAM_TR1_RDCD_RCD_0_0; - } - - /* - * save CFG0 ECC setting to a temporary variable and turn ECC off - */ - mfsdram(mem_cfg0, cfg0); - ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK; - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON); - - /* - * get the delay line calibration register value - */ - mfsdram(mem_dlycal, dlycal); - dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2; - - max_pass_length = 0; - max_start = 0; - max_end = 0; - current_pass_length = 0; - current_fail_length = 0; - current_start = 0; - rdclt_offset = 0; - window_found = FALSE; - fail_found = FALSE; - pass_found = FALSE; -#ifdef DEBUG - printf("Starting memory test "); -#endif - for (k = 0; k < NUMHALFCYCLES; k++) { - for (rdclt = 0; rdclt < dly_val; rdclt++) { - /* - * Set the timing reg for the test. - */ - mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); - - for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { - mtdcr(memcfga, mem_b0cr + (bxcr_num<<2)); - if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { - /* Bank is enabled */ - membase = (unsigned long*) - (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK); - - /* - * Run the short memory test - */ - for (i = 0; i < NUMMEMTESTS; i++) { - for (j = 0; j < NUMMEMWORDS; j++) { - membase[j] = test[i][j]; - ppcDcbf((unsigned long)&(membase[j])); - } - - for (j = 0; j < NUMMEMWORDS; j++) { - if (membase[j] != test[i][j]) { - ppcDcbf((unsigned long)&(membase[j])); - break; - } - ppcDcbf((unsigned long)&(membase[j])); - } - - if (j < NUMMEMWORDS) { - break; - } - } - - /* - * see if the rdclt value passed - */ - if (i < NUMMEMTESTS) { - break; - } - } - } - - if (bxcr_num == MAXBXCR) { - if (fail_found == TRUE) { - pass_found = TRUE; - if (current_pass_length == 0) { - current_start = rdclt_offset + rdclt; - } - - current_fail_length = 0; - current_pass_length++; - - if (current_pass_length > max_pass_length) { - max_pass_length = current_pass_length; - max_start = current_start; - max_end = rdclt_offset + rdclt; - } - } - } else { - current_pass_length = 0; - current_fail_length++; - - if (current_fail_length >= (dly_val>>2)) { - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { - window_found = TRUE; - break; - } - } - } - } -#ifdef DEBUG - printf("."); -#endif - if (window_found == TRUE) { - break; - } - - tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; - rdclt_offset += dly_val; - } -#ifdef DEBUG - printf("\n"); -#endif - - /* - * make sure we find the window - */ - if (window_found == FALSE) { - printf("ERROR: Cannot determine a common read delay.\n"); - hang(); - } - - /* - * restore the orignal ECC setting - */ - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp); - - /* - * set the SDRAM TR1 RDCD value - */ - tr1 &= ~SDRAM_TR1_RDCD_MASK; - if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) { - tr1 |= SDRAM_TR1_RDCD_RCD_1_2; - } else { - tr1 |= SDRAM_TR1_RDCD_RCD_0_0; - } - - /* - * set the SDRAM TR1 RDCLT value - */ - tr1 &= ~SDRAM_TR1_RDCT_MASK; - while (max_end >= (dly_val << 1)) { - max_end -= (dly_val << 1); - max_start -= (dly_val << 1); - } - - rdclt_average = ((max_start + max_end) >> 1); - if (rdclt_average >= 0x60) - while (1) - ; - - if (rdclt_average < 0) { - rdclt_average = 0; - } - - if (rdclt_average >= dly_val) { - rdclt_average -= dly_val; - tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; - } - tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average); - -#if 0 - printf("tr1: %x\n", tr1); -#endif - /* - * program SDRAM Timing Register 1 TR1 - */ - mtsdram(mem_tr1, tr1); -} - -unsigned long program_bxcr(unsigned long* dimm_populated, - unsigned char* iic0_dimm_addr, - unsigned long num_dimm_banks) -{ - unsigned long dimm_num; - unsigned long bank_base_addr; - unsigned long cr; - unsigned long i; - unsigned long j; - unsigned long temp; - unsigned char num_row_addr; - unsigned char num_col_addr; - unsigned char num_banks; - unsigned char bank_size_id; - unsigned long ctrl_bank_num[MAXBANKS]; - unsigned long bx_cr_num; - unsigned long largest_size_index; - unsigned long largest_size; - unsigned long current_size_index; - BANKPARMS bank_parms[MAXBXCR]; - unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */ - unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/ - - /* - * Set the BxCR regs. First, wipe out the bank config registers. - */ - for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { - mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2)); - mtdcr(memcfgd, 0x00000000); - bank_parms[bx_cr_num].bank_size_bytes = 0; - } - -#ifdef CONFIG_BAMBOO - /* - * This next section is hardware dependent and must be programmed - * to match the hardware. For bammboo, the following holds... - * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 - * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1 - * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1 - * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3 - * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM - */ - ctrl_bank_num[0] = 0; - ctrl_bank_num[1] = 1; - ctrl_bank_num[2] = 3; -#else - ctrl_bank_num[0] = 0; - ctrl_bank_num[1] = 1; - ctrl_bank_num[2] = 2; - ctrl_bank_num[3] = 3; -#endif - - /* - * reset the bank_base address - */ - bank_base_addr = CFG_SDRAM_BASE; - - for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { - num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3); - num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); - num_banks = spd_read(iic0_dimm_addr[dimm_num], 5); - bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31); - - /* - * Set the SDRAM0_BxCR regs - */ - cr = 0; - switch (bank_size_id) { - case 0x02: - cr |= SDRAM_BXCR_SDSZ_8; - break; - case 0x04: - cr |= SDRAM_BXCR_SDSZ_16; - break; - case 0x08: - cr |= SDRAM_BXCR_SDSZ_32; - break; - case 0x10: - cr |= SDRAM_BXCR_SDSZ_64; - break; - case 0x20: - cr |= SDRAM_BXCR_SDSZ_128; - break; - case 0x40: - cr |= SDRAM_BXCR_SDSZ_256; - break; - case 0x80: - cr |= SDRAM_BXCR_SDSZ_512; - break; - default: - printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", - dimm_num); - printf("ERROR: Unsupported value for the banksize: %d.\n", - bank_size_id); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); - } - - switch (num_col_addr) { - case 0x08: - cr |= SDRAM_BXCR_SDAM_1; - break; - case 0x09: - cr |= SDRAM_BXCR_SDAM_2; - break; - case 0x0A: - cr |= SDRAM_BXCR_SDAM_3; - break; - case 0x0B: - cr |= SDRAM_BXCR_SDAM_4; - break; - default: - printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", - dimm_num); - printf("ERROR: Unsupported value for number of " - "column addresses: %d.\n", num_col_addr); - printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); - } - - /* - * enable the bank - */ - cr |= SDRAM_BXCR_SDBE; - - for (i = 0; i < num_banks; i++) { - bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = - (4 * 1024 * 1024) * bank_size_id; - bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; - } - } - } - - /* Initialize sort tables */ - for (i = 0; i < MAXBXCR; i++) { - sorted_bank_num[i] = i; - sorted_bank_size[i] = bank_parms[i].bank_size_bytes; - } - - for (i = 0; i < MAXBXCR-1; i++) { - largest_size = sorted_bank_size[i]; - largest_size_index = 255; - - /* Find the largest remaining value */ - for (j = i + 1; j < MAXBXCR; j++) { - if (sorted_bank_size[j] > largest_size) { - /* Save largest remaining value and its index */ - largest_size = sorted_bank_size[j]; - largest_size_index = j; - } - } - - if (largest_size_index != 255) { - /* Swap the current and largest values */ - current_size_index = sorted_bank_num[largest_size_index]; - sorted_bank_size[largest_size_index] = sorted_bank_size[i]; - sorted_bank_size[i] = largest_size; - sorted_bank_num[largest_size_index] = sorted_bank_num[i]; - sorted_bank_num[i] = current_size_index; - } - } - - /* Set the SDRAM0_BxCR regs thanks to sort tables */ - for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { - if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { - mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); - temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | - SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); - temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | - bank_parms[sorted_bank_num[bx_cr_num]].cr; - mtdcr(memcfgd, temp); - bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes; - } - } - - return(bank_base_addr); -} - -void program_ecc (unsigned long num_bytes) -{ - unsigned long bank_base_addr; - unsigned long current_address; - unsigned long end_address; - unsigned long address_increment; - unsigned long cfg0; - - /* - * get Memory Controller Options 0 data - */ - mfsdram(mem_cfg0, cfg0); - - /* - * reset the bank_base address - */ - bank_base_addr = CFG_SDRAM_BASE; - - if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | - SDRAM_CFG0_MCHK_GEN); - - if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) { - address_increment = 4; - } else { - address_increment = 8; - } - - current_address = (unsigned long)(bank_base_addr); - end_address = (unsigned long)(bank_base_addr) + num_bytes; - - while (current_address < end_address) { - *((unsigned long*)current_address) = 0x00000000; - current_address += address_increment; - } - - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | - SDRAM_CFG0_MCHK_CHK); - } -} - -#endif /* CONFIG_440 */ - -#endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c deleted file mode 100644 index 553c491..0000000 --- a/cpu/ppc4xx/speed.c +++ /dev/null @@ -1,568 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#define ONE_BILLION 1000000000 - - -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) - -void get_sys_info (PPC405_SYS_INFO * sysInfo) -{ - unsigned long pllmr; - unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000); - uint pvr = get_pvr(); - unsigned long psr; - unsigned long m; - - /* - * Read PLL Mode register - */ - pllmr = mfdcr (pllmd); - - /* - * Read Pin Strapping register - */ - psr = mfdcr (strap); - - /* - * Determine FWD_DIV. - */ - sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29); - - /* - * Determine FBK_DIV. - */ - sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25); - if (sysInfo->pllFbkDiv == 0) { - sysInfo->pllFbkDiv = 16; - } - - /* - * Determine PLB_DIV. - */ - sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1; - - /* - * Determine PCI_DIV. - */ - sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1; - - /* - * Determine EXTBUS_DIV. - */ - sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2; - - /* - * Determine OPB_DIV. - */ - sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1; - - /* - * Check if PPC405GPr used (mask minor revision field) - */ - if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { - /* - * Determine FWD_DIV B (only PPC405GPr with new mode strapping). - */ - sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK); - - /* - * Determine factor m depending on PLL feedback clock source - */ - if (!(psr & PSR_PCI_ASYNC_EN)) { - if (psr & PSR_NEW_MODE_EN) { - /* - * sync pci clock used as feedback (new mode) - */ - m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv; - } else { - /* - * sync pci clock used as feedback (legacy mode) - */ - m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv; - } - } else if (psr & PSR_NEW_MODE_EN) { - if (psr & PSR_PERCLK_SYNC_MODE_EN) { - /* - * PerClk used as feedback (new mode) - */ - m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv; - } else { - /* - * CPU clock used as feedback (new mode) - */ - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv; - } - } else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) { - /* - * PerClk used as feedback (legacy mode) - */ - m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv; - } else { - /* - * PLB clock used as feedback (legacy mode) - */ - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv; - } - - sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / - (unsigned long long)sysClkPeriodPs; - sysInfo->freqProcessor = sysInfo->freqVCOHz / sysInfo->pllFwdDiv; - sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDivB * sysInfo->pllPlbDiv); - } else { - /* - * Check pllFwdDiv to see if running in bypass mode where the CPU speed - * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO - * to make sure it is within the proper range. - * spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV - * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding. - */ - if (sysInfo->pllFwdDiv == 1) { - sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ; - sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv; - } else { - sysInfo->freqVCOHz = ( 1000000000000LL * - (unsigned long long)sysInfo->pllFwdDiv * - (unsigned long long)sysInfo->pllFbkDiv * - (unsigned long long)sysInfo->pllPlbDiv - ) / (unsigned long long)sysClkPeriodPs; - sysInfo->freqPLB = (ONE_BILLION / ((sysClkPeriodPs * 10) / - sysInfo->pllFbkDiv)) * 10000; - sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv; - } - } -} - - -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC405_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB / sys_info.pllOpbDiv; - - return val; -} - - -/******************************************** - * get_PCI_freq - * return PCI bus freq in Hz - *********************************************/ -ulong get_PCI_freq (void) -{ - ulong val; - PPC405_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB / sys_info.pllPciDiv; - return val; -} - - -#elif defined(CONFIG_440) - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) -void get_sys_info (sys_info_t *sysInfo) -{ - unsigned long temp; - unsigned long reg; - unsigned long lfdiv; - unsigned long m; - unsigned long prbdv0; - /* - WARNING: ASSUMES the following: - ENG=1 - PRADV0=1 - PRBDV0=1 - */ - - /* Decode CPR0_PLLD0 for divisors */ - mfclk(clk_plld, reg); - temp = (reg & PLLD_FWDVA_MASK) >> 16; - sysInfo->pllFwdDivA = temp ? temp : 16; - temp = (reg & PLLD_FWDVB_MASK) >> 8; - sysInfo->pllFwdDivB = temp ? temp: 8 ; - temp = (reg & PLLD_FBDV_MASK) >> 24; - sysInfo->pllFbkDiv = temp ? temp : 32; - lfdiv = reg & PLLD_LFBDV_MASK; - - mfclk(clk_opbd, reg); - temp = (reg & OPBDDV_MASK) >> 24; - sysInfo->pllOpbDiv = temp ? temp : 4; - - mfclk(clk_perd, reg); - temp = (reg & PERDV_MASK) >> 24; - sysInfo->pllExtBusDiv = temp ? temp : 8; - - mfclk(clk_primbd, reg); - temp = (reg & PRBDV_MASK) >> 24; - prbdv0 = temp ? temp : 8; - - mfclk(clk_spcid, reg); - temp = (reg & SPCID_MASK) >> 24; - sysInfo->pllPciDiv = temp ? temp : 4; - - /* Calculate 'M' based on feedback source */ - mfsdr(sdr_sdstp0, reg); - temp = (reg & PLLSYS0_SEL_MASK) >> 27; - if (temp == 0) { /* PLL output */ - /* Figure which pll to use */ - mfclk(clk_pllc, reg); - temp = (reg & PLLC_SRC_MASK) >> 29; - if (!temp) /* PLLOUTA */ - m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA; - else /* PLLOUTB */ - m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB; - } - else if (temp == 1) /* CPU output */ - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA; - else /* PerClk */ - m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB; - - /* Now calculate the individual clocks */ - sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1); - sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; - sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; - sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv; - sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv; - - /* Figure which timer source to use */ - if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */ - temp = sysInfo->freqProcessor / 2; /* Max extern clock speed */ - if (CONFIG_SYS_CLK_FREQ > temp) - sysInfo->freqTmrClk = temp; - else - sysInfo->freqTmrClk = CONFIG_SYS_CLK_FREQ; - } - else /* Internal clock */ - sysInfo->freqTmrClk = sysInfo->freqProcessor; -} -/******************************************** - * get_PCI_freq - * return PCI bus freq in Hz - *********************************************/ -ulong get_PCI_freq (void) -{ - sys_info_t sys_info; - get_sys_info (&sys_info); - return sys_info.freqPCI; -} - -#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) -void get_sys_info (sys_info_t * sysInfo) -{ - unsigned long strp0; - unsigned long temp; - unsigned long m; - - /* Extract configured divisors */ - strp0 = mfdcr( cpc0_strp0 ); - sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15); - sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12); - temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18; - sysInfo->pllFbkDiv = temp ? temp : 16; - sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10); - sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8); - - /* Calculate 'M' based on feedback source */ - if( strp0 & PLLSYS0_EXTSL_MASK ) - m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB; - else - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA; - - /* Now calculate the individual clocks */ - sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1); - sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; - sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB; - if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */ - sysInfo->freqPLB >>= 1; - sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; - -} -#else -void get_sys_info (sys_info_t * sysInfo) -{ - unsigned long strp0; - unsigned long strp1; - unsigned long temp; - unsigned long temp1; - unsigned long lfdiv; - unsigned long m; - unsigned long prbdv0; - - /* Extract configured divisors */ - mfsdr( sdr_sdstp0,strp0 ); - mfsdr( sdr_sdstp1,strp1 ); - - temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8); - sysInfo->pllFwdDivA = temp ? temp : 16 ; - temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5); - sysInfo->pllFwdDivB = temp ? temp: 8 ; - temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12; - sysInfo->pllFbkDiv = temp ? temp : 32; - temp = (strp0 & PLLSYS0_OPB_DIV_MASK); - sysInfo->pllOpbDiv = temp ? temp : 4; - temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24; - sysInfo->pllExtBusDiv = temp ? temp : 4; - prbdv0 = (strp0 >> 2) & 0x7; - - /* Calculate 'M' based on feedback source */ - temp = (strp0 & PLLSYS0_SEL_MASK) >> 27; - temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26; - lfdiv = temp1 ? temp1 : 64; - if (temp == 0) { /* PLL output */ - /* Figure which pll to use */ - temp = (strp0 & PLLSYS0_SRC_MASK) >> 30; - if (!temp) - m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA; - else - m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB; - } - else if (temp == 1) /* CPU output */ - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA; - else /* PerClk */ - m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB; - - /* Now calculate the individual clocks */ - sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1); - sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; - sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; - sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; - -} -#endif - -ulong get_OPB_freq (void) -{ - - sys_info_t sys_info; - get_sys_info (&sys_info); - return sys_info.freqOPB; -} - -#elif defined(CONFIG_XILINX_ML300) -extern void get_sys_info (sys_info_t * sysInfo); -extern ulong get_PCI_freq (void); - -#elif defined(CONFIG_AP1000) -void get_sys_info (sys_info_t * sysInfo) { - sysInfo->freqProcessor = 240 * 1000 * 1000; - sysInfo->freqPLB = 80 * 1000 * 1000; - sysInfo->freqPCI = 33 * 1000 * 1000; -} - -#elif defined(CONFIG_405) - -void get_sys_info (sys_info_t * sysInfo) { - - sysInfo->freqVCOMhz=3125000; - sysInfo->freqProcessor=12*1000*1000; - sysInfo->freqPLB=50*1000*1000; - sysInfo->freqPCI=66*1000*1000; - -} - -#elif defined(CONFIG_405EP) -void get_sys_info (PPC405_SYS_INFO * sysInfo) -{ - unsigned long pllmr0; - unsigned long pllmr1; - unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000); - unsigned long m; - unsigned long pllmr0_ccdv; - - /* - * Read PLL Mode registers - */ - pllmr0 = mfdcr (cpc0_pllmr0); - pllmr1 = mfdcr (cpc0_pllmr1); - - /* - * Determine forward divider A - */ - sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16); - - /* - * Determine forward divider B (should be equal to A) - */ - sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12); - - /* - * Determine FBK_DIV. - */ - sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20); - if (sysInfo->pllFbkDiv == 0) { - sysInfo->pllFbkDiv = 16; - } - - /* - * Determine PLB_DIV. - */ - sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1; - - /* - * Determine PCI_DIV. - */ - sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1; - - /* - * Determine EXTBUS_DIV. - */ - sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2; - - /* - * Determine OPB_DIV. - */ - sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1; - - /* - * Determine the M factor - */ - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB; - - /* - * Determine VCO clock frequency - */ - sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / - (unsigned long long)sysClkPeriodPs; - - /* - * Determine CPU clock frequency - */ - pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1; - if (pllmr1 & PLLMR1_SSCS_MASK) { - /* - * This is true if FWDVA == FWDVB: - * sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) - * / pllmr0_ccdv; - */ - sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB) - / sysInfo->pllFwdDiv / pllmr0_ccdv; - } else { - sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv; - } - - /* - * Determine PLB clock frequency - */ - sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv; -} - - -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC405_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB / sys_info.pllOpbDiv; - - return val; -} - - -/******************************************** - * get_PCI_freq - * return PCI bus freq in Hz - *********************************************/ -ulong get_PCI_freq (void) -{ - ulong val; - PPC405_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB / sys_info.pllPciDiv; - return val; -} - -#endif - -int get_clocks (void) -{ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP) - DECLARE_GLOBAL_DATA_PTR; - - sys_info_t sys_info; - - get_sys_info (&sys_info); - gd->cpu_clk = sys_info.freqProcessor; - gd->bus_clk = sys_info.freqPLB; - -#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */ - -#ifdef CONFIG_IOP480 - DECLARE_GLOBAL_DATA_PTR; - - gd->cpu_clk = 66000000; - gd->bus_clk = 66000000; -#endif - return (0); -} - - -/******************************************** - * get_bus_freq - * return PLB bus freq in Hz - *********************************************/ -ulong get_bus_freq (ulong dummy) -{ - ulong val; - -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP) - sys_info_t sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB; - -#elif defined(CONFIG_IOP480) - - val = 66; - -#else -# error get_bus_freq() not implemented -#endif - - return val; -} diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S deleted file mode 100644 index 48b430d..0000000 --- a/cpu/ppc4xx/start.S +++ /dev/null @@ -1,1687 +0,0 @@ -/* - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000,2001,2002 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/*------------------------------------------------------------------------------+ */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ - -/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards - * - * - * The processor starts at 0xfffffffc and the code is executed - * from flash/rom. - * in memory, but as long we don't jump around before relocating. - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - * This works because the cpu gives the FLASH (CS0) the whole - * address space at startup, and board_init lies as a echo of - * the flash somewhere up there in the memorymap. - * - * board_init will change CS0 to be positioned at the correct - * address and (s)dram will be positioned at address 0 - */ -#include -#include -#include -#include - -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -#include -#include - -#include -#include - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -#ifdef CFG_INIT_DCACHE_CS -# if (CFG_INIT_DCACHE_CS == 0) -# define PBxAP pb0ap -# define PBxCR pb0cr -# endif -# if (CFG_INIT_DCACHE_CS == 1) -# define PBxAP pb1ap -# define PBxCR pb1cr -# endif -# if (CFG_INIT_DCACHE_CS == 2) -# define PBxAP pb2ap -# define PBxCR pb2cr -# endif -# if (CFG_INIT_DCACHE_CS == 3) -# define PBxAP pb3ap -# define PBxCR pb3cr -# endif -# if (CFG_INIT_DCACHE_CS == 4) -# define PBxAP pb4ap -# define PBxCR pb4cr -# endif -# if (CFG_INIT_DCACHE_CS == 5) -# define PBxAP pb5ap -# define PBxCR pb5cr -# endif -# if (CFG_INIT_DCACHE_CS == 6) -# define PBxAP pb6ap -# define PBxCR pb6cr -# endif -# if (CFG_INIT_DCACHE_CS == 7) -# define PBxAP pb7ap -# define PBxCR pb7cr -# endif -#endif /* CFG_INIT_DCACHE_CS */ - -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ - - - .extern ext_bus_cntlr_init - .extern sdram_init - -/* - * Set up GOT: Global Offset Table - * - * Use r14 to access the GOT - */ - START_GOT - GOT_ENTRY(_GOT2_TABLE_) - GOT_ENTRY(_FIXUP_TABLE_) - - GOT_ENTRY(_start) - GOT_ENTRY(_start_of_vectors) - GOT_ENTRY(_end_of_vectors) - GOT_ENTRY(transfer_to_handler) - - GOT_ENTRY(__init_end) - GOT_ENTRY(_end) - GOT_ENTRY(__bss_start) - END_GOT - -/* - * 440 Startup -- on reset only the top 4k of the effective - * address space is mapped in by an entry in the instruction - * and data shadow TLB. The .bootpg section is located in the - * top 4k & does only what's necessary to map in the the rest - * of the boot rom. Once the boot rom is mapped in we can - * proceed with normal startup. - * - * NOTE: CS0 only covers the top 2MB of the effective address - * space after reset. - */ - -#if defined(CONFIG_440) - .section .bootpg,"ax" - .globl _start_440 - -/**************************************************************************/ -_start_440: - /*----------------------------------------------------------------*/ - /* Clear and set up some registers. */ - /*----------------------------------------------------------------*/ - iccci r0,r0 /* NOTE: operands not used for 440 */ - dccci r0,r0 /* NOTE: operands not used for 440 */ - sync - li r0,0 - mtspr srr0,r0 - mtspr srr1,r0 - mtspr csrr0,r0 - mtspr csrr1,r0 -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) /* NOTE: 440GX adds machine check status regs */ - mtspr mcsrr0,r0 - mtspr mcsrr1,r0 - mfspr r1, mcsr - mtspr mcsr,r1 -#endif - /*----------------------------------------------------------------*/ - /* Initialize debug */ - /*----------------------------------------------------------------*/ - mtspr dbcr0,r0 - mtspr dbcr1,r0 - mtspr dbcr2,r0 - mtspr iac1,r0 - mtspr iac2,r0 - mtspr iac3,r0 - mtspr dac1,r0 - mtspr dac2,r0 - mtspr dvc1,r0 - mtspr dvc2,r0 - - mfspr r1,dbsr - mtspr dbsr,r1 /* Clear all valid bits */ - - /*----------------------------------------------------------------*/ - /* CCR0 init */ - /*----------------------------------------------------------------*/ - /* Disable store gathering & broadcast, guarantee inst/data - * cache block touch, force load/store alignment - * (see errata 1.12: 440_33) - */ - lis r1,0x0030 /* store gathering & broadcast disable */ - ori r1,r1,0x6000 /* cache touch */ - mtspr ccr0,r1 - - /*----------------------------------------------------------------*/ - /* Setup interrupt vectors */ - /*----------------------------------------------------------------*/ - mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */ - li r1,0x0100 - mtspr ivor0,r1 /* Critical input */ - li r1,0x0200 - mtspr ivor1,r1 /* Machine check */ - li r1,0x0300 - mtspr ivor2,r1 /* Data storage */ - li r1,0x0400 - mtspr ivor3,r1 /* Instruction storage */ - li r1,0x0500 - mtspr ivor4,r1 /* External interrupt */ - li r1,0x0600 - mtspr ivor5,r1 /* Alignment */ - li r1,0x0700 - mtspr ivor6,r1 /* Program check */ - li r1,0x0800 - mtspr ivor7,r1 /* Floating point unavailable */ - li r1,0x0c00 - mtspr ivor8,r1 /* System call */ - li r1,0x1000 - mtspr ivor10,r1 /* Decrementer (PIT for 440) */ - li r1,0x1400 - mtspr ivor13,r1 /* Data TLB error */ - li r1,0x1300 - mtspr ivor14,r1 /* Instr TLB error */ - li r1,0x2000 - mtspr ivor15,r1 /* Debug */ - - /*----------------------------------------------------------------*/ - /* Configure cache regions */ - /*----------------------------------------------------------------*/ - mtspr inv0,r0 - mtspr inv1,r0 - mtspr inv2,r0 - mtspr inv3,r0 - mtspr dnv0,r0 - mtspr dnv1,r0 - mtspr dnv2,r0 - mtspr dnv3,r0 - mtspr itv0,r0 - mtspr itv1,r0 - mtspr itv2,r0 - mtspr itv3,r0 - mtspr dtv0,r0 - mtspr dtv1,r0 - mtspr dtv2,r0 - mtspr dtv3,r0 - - /*----------------------------------------------------------------*/ - /* Cache victim limits */ - /*----------------------------------------------------------------*/ - /* floors 0, ceiling max to use the entire cache -- nothing locked - */ - lis r1,0x0001 - ori r1,r1,0xf800 - mtspr ivlim,r1 - mtspr dvlim,r1 - - /*----------------------------------------------------------------*/ - /* Clear all TLB entries -- TID = 0, TS = 0 */ - /*----------------------------------------------------------------*/ - mtspr mmucr,r0 - li r1,0x003f /* 64 TLB entries */ - mtctr r1 -0: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ - subi r1,r1,0x0001 - bdnz 0b - - /*----------------------------------------------------------------*/ - /* TLB entry setup -- step thru tlbtab */ - /*----------------------------------------------------------------*/ - bl tlbtab /* Get tlbtab pointer */ - mr r5,r0 - li r1,0x003f /* 64 TLB entries max */ - mtctr r1 - li r4,0 /* TLB # */ - - addi r5,r5,-4 -1: lwzu r0,4(r5) - cmpwi r0,0 - beq 2f /* 0 marks end */ - lwzu r1,4(r5) - lwzu r2,4(r5) - tlbwe r0,r4,0 /* TLB Word 0 */ - tlbwe r1,r4,1 /* TLB Word 1 */ - tlbwe r2,r4,2 /* TLB Word 2 */ - addi r4,r4,1 /* Next TLB */ - bdnz 1b - - /*----------------------------------------------------------------*/ - /* Continue from 'normal' start */ - /*----------------------------------------------------------------*/ -2: bl 3f - b _start - -3: li r0,0 - mtspr srr1,r0 /* Keep things disabled for now */ - mflr r1 - mtspr srr0,r1 - rfi -#endif /* CONFIG_440 */ - -/* - * r3 - 1st arg to board_init(): IMMP pointer - * r4 - 2nd arg to board_init(): boot flag - */ - .text - .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" - -/* - * Maybe this should be moved somewhere else because the current - * location (0x100) is where the CriticalInput Execption should be. - */ - . = EXC_OFF_SYS_RESET - .globl _start -_start: - -/*****************************************************************************/ -#if defined(CONFIG_440) - - /*----------------------------------------------------------------*/ - /* Clear and set up some registers. */ - /*----------------------------------------------------------------*/ - li r0,0x0000 - lis r1,0xffff - mtspr dec,r0 /* prevent dec exceptions */ - mtspr tbl,r0 /* prevent fit & wdt exceptions */ - mtspr tbu,r0 - mtspr tsr,r1 /* clear all timer exception status */ - mtspr tcr,r0 /* disable all */ - mtspr esr,r0 /* clear exception syndrome register */ - mtxer r0 /* clear integer exception register */ -#if !defined(CONFIG_440GX) - lis r1,0x0002 /* set CE bit (Critical Exceptions) */ - ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */ - mtmsr r1 /* change MSR */ -#elif !defined(CONFIG_440EP) && !defined(CONFIG_440GR) - bl __440gx_msr_set - b __440gx_msr_continue - -__440gx_msr_set: - lis r1, 0x0002 /* set CE bit (Critical Exceptions) */ - ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */ - mtspr srr1,r1 - mflr r1 - mtspr srr0,r1 - rfi -__440gx_msr_continue: -#endif - - /*----------------------------------------------------------------*/ - /* Debug setup -- some (not very good) ice's need an event*/ - /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */ - /* value you need in this case 0x8cff 0000 should do the trick */ - /*----------------------------------------------------------------*/ -#if defined(CFG_INIT_DBCR) - lis r1,0xffff - ori r1,r1,0xffff - mtspr dbsr,r1 /* Clear all status bits */ - lis r0,CFG_INIT_DBCR@h - ori r0,r0,CFG_INIT_DBCR@l - mtspr dbcr0,r0 - isync -#endif - - /*----------------------------------------------------------------*/ - /* Setup the internal SRAM */ - /*----------------------------------------------------------------*/ - li r0,0 -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) - /* Clear Dcache to use as RAM */ - addis r3,r0,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l - addis r4,r0,CFG_INIT_RAM_END@h - ori r4,r4,CFG_INIT_RAM_END@l - rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ran - addi r5,r5,0x0001 -..d_ran: - mtctr r5 -..d_ag: - dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag -#else -#if defined (CONFIG_440GX) || defined(CONFIG_440SP) - mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */ -#endif - mtdcr isram0_sb1cr,r0 /* Disable bank 1 */ - - li r2,0x7fff - ori r2,r2,0xffff - mfdcr r1,isram0_dpc - and r1,r1,r2 /* Disable parity check */ - mtdcr isram0_dpc,r1 - mfdcr r1,isram0_pmeg - andis. r1,r1,r2 /* Disable pwr mgmt */ - mtdcr isram0_pmeg,r1 - - lis r1,0x8000 /* BAS = 8000_0000 */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) - ori r1,r1,0x0980 /* first 64k */ - mtdcr isram0_sb0cr,r1 - lis r1,0x8001 - ori r1,r1,0x0980 /* second 64k */ - mtdcr isram0_sb1cr,r1 - lis r1, 0x8002 - ori r1,r1, 0x0980 /* third 64k */ - mtdcr isram0_sb2cr,r1 - lis r1, 0x8003 - ori r1,r1, 0x0980 /* fourth 64k */ - mtdcr isram0_sb3cr,r1 -#else - ori r1,r1,0x0380 /* 8k rw */ - mtdcr isram0_sb0cr,r1 -#endif -#endif - - /*----------------------------------------------------------------*/ - /* Setup the stack in internal SRAM */ - /*----------------------------------------------------------------*/ - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l - li r0,0 - stwu r0,-4(r1) - stwu r0,-4(r1) /* Terminate call chain */ - - stwu r1,-8(r1) /* Save back chain and move SP */ - lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0, RESET_VECTOR@l - stwu r1,-8(r1) /* Save back chain and move SP */ - stw r0,+12(r1) /* Save return addr (underflow vect) */ - - GET_GOT - - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - bl board_init_f - -#endif /* CONFIG_440 */ - -/*****************************************************************************/ -#ifdef CONFIG_IOP480 - /*----------------------------------------------------------------------- */ - /* Set up some machine state registers. */ - /*----------------------------------------------------------------------- */ - addi r0,r0,0x0000 /* initialize r0 to zero */ - mtspr esr,r0 /* clear Exception Syndrome Reg */ - mttcr r0 /* timer control register */ - mtexier r0 /* disable all interrupts */ - addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */ - oris r4,r4,0x2 /* set CE bit (Critical Exceptions) */ - mtmsr r4 /* change MSR */ - addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ - ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ - mtdbsr r4 /* clear/reset the dbsr */ - mtexisr r4 /* clear all pending interrupts */ - addis r4,r0,0x8000 - mtexier r4 /* enable critical exceptions */ - addis r4,r0,0x0000 /* assume 403GCX - enable core clk */ - ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */ - mtiocr r4 /* since bit not used) & DRC to latch */ - /* data bus on rising edge of CAS */ - /*----------------------------------------------------------------------- */ - /* Clear XER. */ - /*----------------------------------------------------------------------- */ - mtxer r0 - /*----------------------------------------------------------------------- */ - /* Invalidate i-cache and d-cache TAG arrays. */ - /*----------------------------------------------------------------------- */ - addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */ - addi r4,0,1024 /* 1/4 of I-cache */ -..cloop: - iccci 0,r3 - iccci r4,r3 - dccci 0,r3 - addic. r3,r3,-16 /* move back one cache line */ - bne ..cloop /* loop back to do rest until r3 = 0 */ - - /* */ - /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */ - /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */ - /* */ - - /* first copy IOP480 register base address into r3 */ - addis r3,0,0x5000 /* IOP480 register base address hi */ -/* ori r3,r3,0x0000 / IOP480 register base address lo */ - -#ifdef CONFIG_ADCIOP - /* use r4 as the working variable */ - /* turn on CS3 (LOCCTL.7) */ - lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ - andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */ - stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ -#endif - -#ifdef CONFIG_DASA_SIM - /* use r4 as the working variable */ - /* turn on MA17 (LOCCTL.7) */ - lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ - ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */ - stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ -#endif - - /* turn on MA16..13 (LCS0BRD.12 = 0) */ - lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ - andi. r4,r4,0xefff /* make bit 12 = 0 */ - stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ - - /* make sure above stores all comlete before going on */ - sync - - /* last thing, set local init status done bit (DEVINIT.31) */ - lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */ - oris r4,r4,0x8000 /* make bit 31 = 1 */ - stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */ - - /* clear all pending interrupts and disable all interrupts */ - li r4,-1 /* set p1 to 0xffffffff */ - stw r4,0x1b0(r3) /* clear all pending interrupts */ - stw r4,0x1b8(r3) /* clear all pending interrupts */ - li r4,0 /* set r4 to 0 */ - stw r4,0x1b4(r3) /* disable all interrupts */ - stw r4,0x1bc(r3) /* disable all interrupts */ - - /* make sure above stores all comlete before going on */ - sync - - /*----------------------------------------------------------------------- */ - /* Enable two 128MB cachable regions. */ - /*----------------------------------------------------------------------- */ - addis r1,r0,0x8000 - addi r1,r1,0x0001 - mticcr r1 /* instruction cache */ - - addis r1,r0,0x0000 - addi r1,r1,0x0000 - mtdccr r1 /* data cache */ - - addis r1,r0,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - - GET_GOT /* initialize GOT access */ - - bl board_init_f /* run first part of init code (from Flash) */ - -#endif /* CONFIG_IOP480 */ - -/*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP) - /*----------------------------------------------------------------------- */ - /* Clear and set up some registers. */ - /*----------------------------------------------------------------------- */ - addi r4,r0,0x0000 - mtspr sgr,r4 - mtspr dcwr,r4 - mtesr r4 /* clear Exception Syndrome Reg */ - mttcr r4 /* clear Timer Control Reg */ - mtxer r4 /* clear Fixed-Point Exception Reg */ - mtevpr r4 /* clear Exception Vector Prefix Reg */ - addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */ - oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */ - mtmsr r4 /* change MSR */ - addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ - /* dbsr is cleared by setting bits to 1) */ - mtdbsr r4 /* clear/reset the dbsr */ - - /*----------------------------------------------------------------------- */ - /* Invalidate I and D caches. Enable I cache for defined memory regions */ - /* to speed things up. Leave the D cache disabled for now. It will be */ - /* enabled/left disabled later based on user selected menu options. */ - /* Be aware that the I cache may be disabled later based on the menu */ - /* options as well. See miscLib/main.c. */ - /*----------------------------------------------------------------------- */ - bl invalidate_icache - bl invalidate_dcache - - /*----------------------------------------------------------------------- */ - /* Enable two 128MB cachable regions. */ - /*----------------------------------------------------------------------- */ - addis r4,r0,0x8000 - addi r4,r4,0x0001 - mticcr r4 /* instruction cache */ - isync - - addis r4,r0,0x0000 - addi r4,r4,0x0000 - mtdccr r4 /* data cache */ - -#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) - /*----------------------------------------------------------------------- */ - /* Tune the speed and size for flash CS0 */ - /*----------------------------------------------------------------------- */ - bl ext_bus_cntlr_init -#endif - -#if defined(CONFIG_405EP) - /*----------------------------------------------------------------------- */ - /* DMA Status, clear to come up clean */ - /*----------------------------------------------------------------------- */ - addis r3,r0, 0xFFFF /* Clear all existing DMA status */ - ori r3,r3, 0xFFFF - mtdcr dmasr, r3 - - bl ppc405ep_init /* do ppc405ep specific init */ -#endif /* CONFIG_405EP */ - -#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE) - /******************************************************************** - * Setup OCM - On Chip Memory - *******************************************************************/ - /* Setup OCM */ - lis r0, 0x7FFF - ori r0, r0, 0xFFFF - mfdcr r3, ocmiscntl /* get instr-side IRAM config */ - mfdcr r4, ocmdscntl /* get data-side IRAM config */ - and r3, r3, r0 /* disable data-side IRAM */ - and r4, r4, r0 /* disable data-side IRAM */ - mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ - mtdcr ocmdscntl, r4 /* set data-side IRAM config */ - isync - - addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */ - mtdcr ocmdsarc, r3 - addis r4, 0, 0xC000 /* OCM data area enabled */ - mtdcr ocmdscntl, r4 - isync -#endif - - /*----------------------------------------------------------------------- */ - /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ - /*----------------------------------------------------------------------- */ -#ifdef CFG_INIT_DCACHE_CS - /*----------------------------------------------------------------------- */ - /* Memory Bank x (nothingness) initialization 1GB+64MEG */ - /* used as temporary stack pointer for stage0 */ - /*----------------------------------------------------------------------- */ - li r4,PBxAP - mtdcr ebccfga,r4 - lis r4,0x0380 - ori r4,r4,0x0480 - mtdcr ebccfgd,r4 - - addi r4,0,PBxCR - mtdcr ebccfga,r4 - lis r4,0x400D - ori r4,r4,0xa000 - mtdcr ebccfgd,r4 - - /* turn on data chache for this region */ - lis r4,0x0080 - mtdccr r4 - - /* set stack pointer and clear stack to known value */ - - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l - - li r4,2048 /* we store 2048 words to stack */ - mtctr r4 - - lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */ - ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */ - - lis r4,0xdead /* we store 0xdeaddead in the stack */ - ori r4,r4,0xdead - -..stackloop: - stwu r4,-4(r2) - bdnz ..stackloop - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - /* - * Set up a dummy frame to store reset vector as return address. - * this causes stack underflow to reset board. - */ - stwu r1, -8(r1) /* Save back chain and move SP */ - addis r0, 0, RESET_VECTOR@h /* Address of reset vector */ - ori r0, r0, RESET_VECTOR@l - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save return addr (underflow vect) */ - -#elif defined(CFG_TEMP_STACK_OCM) && \ - (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)) - /* - * Stack in OCM. - */ - - /* Set up Stack at top of OCM */ - lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l - - /* Set up a zeroized stack frame so that backtrace works right */ - li r0, 0 - stwu r0, -4(r1) - stwu r0, -4(r1) - - /* - * Set up a dummy frame to store reset vector as return address. - * this causes stack underflow to reset board. - */ - stwu r1, -8(r1) /* Save back chain and move SP */ - lis r0, RESET_VECTOR@h /* Address of reset vector */ - ori r0, r0, RESET_VECTOR@l - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save return addr (underflow vect) */ -#endif /* CFG_INIT_DCACHE_CS */ - - /*----------------------------------------------------------------------- */ - /* Initialize SDRAM Controller */ - /*----------------------------------------------------------------------- */ - bl sdram_init - - /* - * Setup temporary stack pointer only for boards - * that do not use SDRAM SPD I2C stuff since it - * is already initialized to use DCACHE or OCM - * stacks. - */ -#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) - lis r1, CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - /* - * Set up a dummy frame to store reset vector as return address. - * this causes stack underflow to reset board. - */ - stwu r1, -8(r1) /* Save back chain and move SP */ - lis r0, RESET_VECTOR@h /* Address of reset vector */ - ori r0, r0, RESET_VECTOR@l - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save return addr (underflow vect) */ -#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */ - - GET_GOT /* initialize GOT access */ - - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - - /* NEVER RETURNS! */ - bl board_init_f /* run first part of init code (from Flash) */ - -#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ - /*----------------------------------------------------------------------- */ - - -/*****************************************************************************/ - .globl _start_of_vectors -_start_of_vectors: - -#if 0 -/*TODO Fixup _start above so we can do this*/ -/* Critical input. */ - CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException) -#endif - -/* Machine check */ - CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - - /* No FPU on MPC8xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - /* On the MPC8xx, this is a software emulation interrupt. It occurs - * for all unimplemented and illegal instructions. - */ - STD_EXCEPTION(0x1000, PIT, PITException) - - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - - CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x2100 - -/* - * This code finishes saving the registers to the exception frame - * and jumps to the appropriate handler for the exception. - * Register r21 is pointer into trap frame, r1 has new stack pointer. - */ - .globl transfer_to_handler -transfer_to_handler: - stw r22,_NIP(r21) - lis r22,MSR_POW@h - andc r23,r23,r22 - stw r23,_MSR(r21) - SAVE_GPR(7, r21) - SAVE_4GPRS(8, r21) - SAVE_8GPRS(12, r21) - SAVE_8GPRS(24, r21) -#if 0 - andi. r23,r23,MSR_PR - mfspr r23,SPRG3 /* if from user, fix up tss.regs */ - beq 2f - addi r24,r1,STACK_FRAME_OVERHEAD - stw r24,PT_REGS(r23) -2: addi r2,r23,-TSS /* set r2 to current */ - tovirt(r2,r2,r23) -#endif - mflr r23 - andi. r24,r23,0x3f00 /* get vector offset */ - stw r24,TRAP(r21) - li r22,0 - stw r22,RESULT(r21) - mtspr SPRG2,r22 /* r1 is now kernel sp */ -#if 0 - addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */ - cmplw 0,r1,r2 - cmplw 1,r1,r24 - crand 1,1,4 - bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */ -#endif - lwz r24,0(r23) /* virtual address of handler */ - lwz r23,4(r23) /* where to go when done */ - mtspr SRR0,r24 - mtspr SRR1,r20 - mtlr r23 - SYNC - rfi /* jump to handler, enable MMU */ - -int_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SRR0,r2 - mtspr SRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfi - -crit_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr 990,r2 /* SRR2 */ - mtspr 991,r0 /* SRR3 */ - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfci - -/* Cache functions. -*/ -invalidate_icache: - iccci r0,r0 /* for 405, iccci invalidates the */ - blr /* entire I cache */ - -invalidate_dcache: - addi r6,0,0x0000 /* clear GPR 6 */ - /* Do loop for # of dcache congruence classes. */ - lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */ - ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l - /* NOTE: dccci invalidates both */ - mtctr r7 /* ways in the D cache */ -..dcloop: - dccci 0,r6 /* invalidate line */ - addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */ - bdnz ..dcloop - blr - -flush_dcache: - addis r9,r0,0x0002 /* set mask for EE and CE msr bits */ - ori r9,r9,0x8000 - mfmsr r12 /* save msr */ - andc r9,r12,r9 - mtmsr r9 /* disable EE and CE */ - addi r10,r0,0x0001 /* enable data cache for unused memory */ - mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */ - or r10,r10,r9 /* bit 31 in dccr */ - mtdccr r10 - - /* do loop for # of congruence classes. */ - lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */ - ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l - lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */ - ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */ - mtctr r10 - addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */ - add r11,r10,r11 /* add to get to other side of cache line */ -..flush_dcache_loop: - lwz r3,0(r10) /* least recently used side */ - lwz r3,0(r11) /* the other side */ - dccci r0,r11 /* invalidate both sides */ - addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */ - addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */ - bdnz ..flush_dcache_loop - sync /* allow memory access to complete */ - mtdccr r9 /* restore dccr */ - mtmsr r12 /* restore msr */ - blr - - .globl icache_enable -icache_enable: - mflr r8 - bl invalidate_icache - mtlr r8 - isync - addis r3,r0, 0x8000 /* set bit 0 */ - mticcr r3 - blr - - .globl icache_disable -icache_disable: - addis r3,r0, 0x0000 /* clear bit 0 */ - mticcr r3 - isync - blr - - .globl icache_status -icache_status: - mficcr r3 - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl dcache_enable -dcache_enable: - mflr r8 - bl invalidate_dcache - mtlr r8 - isync - addis r3,r0, 0x8000 /* set bit 0 */ - mtdccr r3 - blr - - .globl dcache_disable -dcache_disable: - mflr r8 - bl flush_dcache - mtlr r8 - addis r3,r0, 0x0000 /* clear bit 0 */ - mtdccr r3 - blr - - .globl dcache_status -dcache_status: - mfdccr r3 - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - -#if !defined(CONFIG_440) - .globl wr_pit -wr_pit: - mtspr pit, r3 - blr -#endif - - .globl wr_tcr -wr_tcr: - mtspr tcr, r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out16 */ -/* Description: Output 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl out16 -out16: - sth r4,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out16r */ -/* Description: Byte reverse and output 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl out16r -out16r: - sthbrx r4,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out32r */ -/* Description: Byte reverse and output 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl out32r -out32r: - stwbrx r4,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in16 */ -/* Description: Input 16 bits */ -/*------------------------------------------------------------------------------- */ - .globl in16 -in16: - lhz r3,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in16r */ -/* Description: Input 16 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ - .globl in16r -in16r: - lhbrx r3,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0x0000(3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in32r */ -/* Description: Input 32 bits and byte reverse */ -/*------------------------------------------------------------------------------- */ - .globl in32r -in32r: - lwbrx r3,r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcSync */ -/* Description: Processor Synchronize */ -/* Input: none. */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcSync -ppcSync: - sync - blr - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ - .globl relocate_code -relocate_code: -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) - dccci 0,0 /* Invalidate data cache, now no longer our stack */ - sync - addi r1,r0,0x0000 /* TLB entry #0 */ - tlbre r0,r1,0x0002 /* Read contents */ - ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ - tlbwe r0,r1,0x0002 /* Save it out */ - isync -#endif - mr r1, r3 /* Set new stack pointer */ - mr r9, r4 /* Save copy of Init Data pointer */ - mr r10, r5 /* Save copy of Destination Address */ - - mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l - lwz r5, GOT(__init_end) - sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ - - /* - * Fix GOT pointer: - * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address - * - * Offset: - */ - sub r15, r10, r4 - - /* First our own GOT */ - add r14, r14, r15 - /* the the one used by the C code */ - add r30, r30, r15 - - /* - * Now relocate code - */ - - cmplw cr1,r3,r4 - addi r0,r5,3 - srwi. r0,r0,2 - beq cr1,4f /* In place copy is not necessary */ - beq 7f /* Protect against 0 count */ - mtctr r0 - bge cr1,2f - - la r8,-4(r4) - la r7,-4(r3) -1: lwzu r0,4(r8) - stwu r0,4(r7) - bdnz 1b - b 4f - -2: slwi r0,r0,2 - add r8,r4,r0 - add r7,r3,r0 -3: lwzu r0,-4(r8) - stwu r0,-4(r7) - bdnz 3b - -/* - * Now flush the cache: note that we must start from a cache aligned - * address. Otherwise we might miss one cache line. - */ -4: cmpwi r6,0 - add r5,r3,r5 - beq 7f /* Always flush prefetch queue in any case */ - subi r0,r6,1 - andc r3,r3,r0 - mr r4,r3 -5: dcbst 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 5b - sync /* Wait for all dcbst to complete on bus */ - mr r4,r3 -6: icbi 0,r4 - add r4,r4,r6 - cmplw r4,r5 - blt 6b -7: sync /* Wait for all icbi to complete on bus */ - isync - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET - mtlr r0 - blr /* NEVER RETURNS! */ - -in_ram: - - /* - * Relocation Function, r14 point to got2+0x8000 - * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. - */ - li r0,__got2_entries@sectoff@l - la r3,GOT(_GOT2_TABLE_) - lwz r11,GOT(_GOT2_TABLE_) - mtctr r0 - sub r11,r3,r11 - addi r3,r3,-4 -1: lwzu r0,4(r3) - add r0,r0,r11 - stw r0,0(r3) - bdnz 1b - - /* - * Now adjust the fixups and the pointers to the fixups - * in case we need to move ourselves again. - */ -2: li r0,__fixup_entries@sectoff@l - lwz r3,GOT(_FIXUP_TABLE_) - cmpwi r0,0 - mtctr r0 - addi r3,r3,-4 - beq 4f -3: lwzu r4,4(r3) - lwzux r0,r4,r11 - add r0,r0,r11 - stw r10,0(r3) - stw r0,0(r4) - bdnz 3b -4: -clear_bss: - /* - * Now clear BSS segment - */ - lwz r3,GOT(__bss_start) - lwz r4,GOT(_end) - - cmplw 0, r3, r4 - beq 6f - - li r0, 0 -5: - stw r0, 0(r3) - addi r3, r3, 4 - cmplw 0, r3, r4 - bne 5b -6: - - mr r3, r9 /* Init Data pointer */ - mr r4, r10 /* Destination Address */ - bl board_init_r - - /* - * Copy exception vector code to low memory - * - * r3: dest_addr - * r7: source address, r8: end address, r9: target address - */ - .globl trap_init -trap_init: - lwz r7, GOT(_start) - lwz r8, GOT(_end_of_vectors) - - li r9, 0x100 /* reset vector always at 0x100 */ - - cmplw 0, r7, r8 - bgelr /* return if r7>=r8 - just in case */ - - mflr r4 /* save link register */ -1: - lwz r0, 0(r7) - stw r0, 0(r9) - addi r7, r7, 4 - addi r9, r9, 4 - cmplw 0, r7, r8 - bne 1b - - /* - * relocate `hdlr' and `int_return' entries - */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET -2: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 2b - - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET - bl trap_reloc - - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b - - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b - - mtlr r4 /* restore link register */ - blr - - /* - * Function: relocate entries for one exception vector - */ -trap_reloc: - lwz r0, 0(r7) /* hdlr ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 0(r7) - - lwz r0, 4(r7) /* int_return ... */ - add r0, r0, r3 /* ... += dest_addr */ - stw r0, 4(r7) - - blr - - -/**************************************************************************/ -/* PPC405EP specific stuff */ -/**************************************************************************/ -#ifdef CONFIG_405EP -ppc405ep_init: - -#ifdef CONFIG_BUBINGA - /* - * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate - * function) to support FPGA and NVRAM accesses below. - */ - - lis r3,GPIO0_OSRH@h /* config GPIO output select */ - ori r3,r3,GPIO0_OSRH@l - lis r4,CFG_GPIO0_OSRH@h - ori r4,r4,CFG_GPIO0_OSRH@l - stw r4,0(r3) - lis r3,GPIO0_OSRL@h - ori r3,r3,GPIO0_OSRL@l - lis r4,CFG_GPIO0_OSRL@h - ori r4,r4,CFG_GPIO0_OSRL@l - stw r4,0(r3) - - lis r3,GPIO0_ISR1H@h /* config GPIO input select */ - ori r3,r3,GPIO0_ISR1H@l - lis r4,CFG_GPIO0_ISR1H@h - ori r4,r4,CFG_GPIO0_ISR1H@l - stw r4,0(r3) - lis r3,GPIO0_ISR1L@h - ori r3,r3,GPIO0_ISR1L@l - lis r4,CFG_GPIO0_ISR1L@h - ori r4,r4,CFG_GPIO0_ISR1L@l - stw r4,0(r3) - - lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ - ori r3,r3,GPIO0_TSRH@l - lis r4,CFG_GPIO0_TSRH@h - ori r4,r4,CFG_GPIO0_TSRH@l - stw r4,0(r3) - lis r3,GPIO0_TSRL@h - ori r3,r3,GPIO0_TSRL@l - lis r4,CFG_GPIO0_TSRL@h - ori r4,r4,CFG_GPIO0_TSRL@l - stw r4,0(r3) - - lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ - ori r3,r3,GPIO0_TCR@l - lis r4,CFG_GPIO0_TCR@h - ori r4,r4,CFG_GPIO0_TCR@l - stw r4,0(r3) - - li r3,pb1ap /* program EBC bank 1 for RTC access */ - mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB1AP@h - ori r3,r3,CFG_EBC_PB1AP@l - mtdcr ebccfgd,r3 - li r3,pb1cr - mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB1CR@h - ori r3,r3,CFG_EBC_PB1CR@l - mtdcr ebccfgd,r3 - - li r3,pb1ap /* program EBC bank 1 for RTC access */ - mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB1AP@h - ori r3,r3,CFG_EBC_PB1AP@l - mtdcr ebccfgd,r3 - li r3,pb1cr - mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB1CR@h - ori r3,r3,CFG_EBC_PB1CR@l - mtdcr ebccfgd,r3 - - li r3,pb4ap /* program EBC bank 4 for FPGA access */ - mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB4AP@h - ori r3,r3,CFG_EBC_PB4AP@l - mtdcr ebccfgd,r3 - li r3,pb4cr - mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB4CR@h - ori r3,r3,CFG_EBC_PB4CR@l - mtdcr ebccfgd,r3 -#endif - - addi r3,0,CPC0_PCI_HOST_CFG_EN -#ifdef CONFIG_BUBINGA - /* - !----------------------------------------------------------------------- - ! Check FPGA for PCI internal/external arbitration - ! If board is set to internal arbitration, update cpc0_pci - !----------------------------------------------------------------------- - */ - addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */ - ori r5,r5,FPGA_REG1@l - lbz r5,0x0(r5) /* read to get PCI arb selection */ - andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/ - beq ..pci_cfg_set /* if not set, then bypass reg write*/ -#endif - ori r3,r3,CPC0_PCI_ARBIT_EN -..pci_cfg_set: - mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/ - - /* - !----------------------------------------------------------------------- - ! Check to see if chip is in bypass mode. - ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a - ! CPU reset Otherwise, skip this step and keep going. - ! Note: Running BIOS in bypass mode is not supported since PLB speed - ! will not be fast enough for the SDRAM (min 66MHz) - !----------------------------------------------------------------------- - */ - mfdcr r5, CPC0_PLLMR1 - rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ - cmpi cr0,0,r4,0x1 - - beq pll_done /* if SSCS =b'1' then PLL has */ - /* already been set */ - /* and CPU has been reset */ - /* so skip to next section */ - -#ifdef CONFIG_BUBINGA - /* - !----------------------------------------------------------------------- - ! Read NVRAM to get value to write in PLLMR. - ! If value has not been correctly saved, write default value - ! Default config values (assuming on-board 33MHz SYS_CLK) are above. - ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above. - ! - ! WARNING: This code assumes the first three words in the nvram_t - ! structure in openbios.h. Changing the beginning of - ! the structure will break this code. - ! - !----------------------------------------------------------------------- - */ - addis r3,0,NVRAM_BASE@h - addi r3,r3,NVRAM_BASE@l - - lwz r4, 0(r3) - addis r5,0,NVRVFY1@h - addi r5,r5,NVRVFY1@l - cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ - bne ..no_pllset - addi r3,r3,4 - lwz r4, 0(r3) - addis r5,0,NVRVFY2@h - addi r5,r5,NVRVFY2@l - cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ - bne ..no_pllset - addi r3,r3,8 /* Skip over conf_size */ - lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ - lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */ - rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */ - cmpi cr0,0,r5,1 /* See if PLL is locked */ - beq pll_write -..no_pllset: -#endif /* CONFIG_BUBINGA */ - - addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ - ori r3,r3,PLLMR0_DEFAULT@l /* */ - addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ - ori r4,r4,PLLMR1_DEFAULT@l /* */ - - b pll_write /* Write the CPC0_PLLMR with new value */ - -pll_done: - /* - !----------------------------------------------------------------------- - ! Clear Soft Reset Register - ! This is needed to enable PCI if not booting from serial EPROM - !----------------------------------------------------------------------- - */ - addi r3, 0, 0x0 - mtdcr CPC0_SRR, r3 - - addis r3,0,0x0010 - mtctr r3 -pci_wait: - bdnz pci_wait - - blr /* return to main code */ - -/* -!----------------------------------------------------------------------------- -! Function: pll_write -! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation -! That is: -! 1. Pll is first disabled (de-activated by putting in bypass mode) -! 2. PLL is reset -! 3. Clock dividers are set while PLL is held in reset and bypassed -! 4. PLL Reset is cleared -! 5. Wait 100us for PLL to lock -! 6. A core reset is performed -! Input: r3 = Value to write to CPC0_PLLMR0 -! Input: r4 = Value to write to CPC0_PLLMR1 -! Output r3 = none -!----------------------------------------------------------------------------- -*/ -pll_write: - mfdcr r5, CPC0_UCR - andis. r5,r5,0xFFFF - ori r5,r5,0x0101 /* Stop the UART clocks */ - mtdcr CPC0_UCR,r5 /* Before changing PLL */ - - mfdcr r5, CPC0_PLLMR1 - rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ - mtdcr CPC0_PLLMR1,r5 - oris r5,r5,0x4000 /* Set PLL Reset */ - mtdcr CPC0_PLLMR1,r5 - - mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ - rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ - oris r5,r5,0x4000 /* Set PLL Reset */ - mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ - rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ - mtdcr CPC0_PLLMR1,r5 - - /* - ! Wait min of 100us for PLL to lock. - ! See CMOS 27E databook for more info. - ! At 200MHz, that means waiting 20,000 instructions - */ - addi r3,0,20000 /* 2000 = 0x4e20 */ - mtctr r3 -pll_wait: - bdnz pll_wait - - oris r5,r5,0x8000 /* Enable PLL */ - mtdcr CPC0_PLLMR1,r5 /* Engage */ - - /* - * Reset CPU to guarantee timings are OK - * Not sure if this is needed... - */ - addis r3,0,0x1000 - mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ - /* execution will continue from the poweron */ - /* vector of 0xfffffffc */ -#endif /* CONFIG_405EP */ diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c deleted file mode 100644 index 6aecca2..0000000 --- a/cpu/ppc4xx/traps.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * linux/arch/ppc/kernel/traps.c - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) - * - * Modified by Cort Dougan (cort@cs.nmt.edu) - * and Paul Mackerras (paulus@cs.anu.edu.au) - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file handles the architecture-dependent parts of hardware exceptions - */ - -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -int (*debugger_exception_handler)(struct pt_regs *) = 0; -#endif - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - -/* THIS NEEDS CHANGING to use the board info structure. - */ -#define END_OF_MEM 0x00400000 - - -static __inline__ void set_tsr(unsigned long val) -{ -#if defined(CONFIG_440) - asm volatile("mtspr 0x150, %0" : : "r" (val)); -#else - asm volatile("mttsr %0" : : "r" (val)); -#endif -} - -static __inline__ unsigned long get_esr(void) -{ - unsigned long val; - -#if defined(CONFIG_440) - asm volatile("mfspr %0, 0x03e" : "=r" (val) :); -#else - asm volatile("mfesr %0" : "=r" (val) :); -#endif - return val; -} - -#define ESR_MCI 0x80000000 -#define ESR_PIL 0x08000000 -#define ESR_PPR 0x04000000 -#define ESR_PTR 0x02000000 -#define ESR_DST 0x00800000 -#define ESR_DIZ 0x00400000 -#define ESR_U0F 0x00008000 - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - -/* - * Trap & Exception support - */ - -void -print_backtrace(unsigned long *sp) -{ - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); -} - -void show_regs(struct pt_regs * regs) -{ - int i; - - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, - regs->msr&MSR_IR ? 1 : 0, - regs->msr&MSR_DR ? 1 : 0); - - printf("\n"); - for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { - printf("GPR%02d: ", i); - } - - printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { - printf("\n"); - } - } -} - - -void -_exception(int signr, struct pt_regs *regs) -{ - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); -} - -void -MachineCheckException(struct pt_regs *regs) -{ - unsigned long fixup; - - /* Probing PCI using config cycles cause this exception - * when a device is not present. Catch it and return to - * the PCI exception handler. - */ - if ((fixup = search_exception_table(regs->nip)) != 0) { - regs->nip = fixup; - return; - } - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Machine check in kernel mode.\n"); - printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); - } - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("machine check"); -} - -void -AlignmentException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Alignment Exception"); -} - -void -ProgramCheckException(struct pt_regs *regs) -{ - long esr_val; - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - show_regs(regs); - - esr_val = get_esr(); - if( esr_val & ESR_PIL ) - printf( "** Illegal Instruction **\n" ); - else if( esr_val & ESR_PPR ) - printf( "** Privileged Instruction **\n" ); - else if( esr_val & ESR_PTR ) - printf( "** Trap Instruction **\n" ); - - print_backtrace((unsigned long *)regs->gpr[1]); - panic("Program Check Exception"); -} - -void -PITException(struct pt_regs *regs) -{ - /* - * Reset PIT interrupt - */ - set_tsr(0x08000000); - - /* - * Call timer_interrupt routine in interrupts.c - */ - timer_interrupt(NULL); -} - - -void -UnknownException(struct pt_regs *regs) -{ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", - regs->nip, regs->msr, regs->trap); - _exception(0, regs); -} - -void -DebugException(struct pt_regs *regs) -{ - printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif -} - -/* Probe an address by reading. If not present, return -1, otherwise - * return 0. - */ -int -addr_probe(uint *addr) -{ -#if 0 - int retval; - - __asm__ __volatile__( \ - "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); - - return (retval); -#endif - return 0; -} diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c deleted file mode 100644 index bb57658..0000000 --- a/cpu/ppc4xx/usb_ohci.c +++ /dev/null @@ -1,1642 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB on the PPC440EP. - * - * (C) Copyright 2003-2004 - * Gary Jennejohn, DENX Software Engineering - * - * (C) Copyright 2004 - * Pierre Aubert, Staubli Faverges - * - * Note: Much of this code has been derived from Linux 2.4 - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2002 David Brownell - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* - * IMPORTANT NOTES - * 1 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! - */ - -#include - -#ifdef CONFIG_USB_OHCI - -#include -#include -#include "usb_ohci.h" - -#include "usbdev.h" - -#define OHCI_USE_NPS /* force NoPowerSwitching mode */ -#undef OHCI_VERBOSE_DEBUG /* not always helpful */ -#undef DEBUG -#undef SHOW_INFO -#undef OHCI_FILL_TRACE - -/* For initializing controller (mask in an HCFS mode too) */ -#define OHCI_CONTROL_INIT \ - (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE - -#define readl(a) (*((vu_long *)(a))) -#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) - -#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) - -#ifdef DEBUG -#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) -#else -#define dbg(format, arg...) do {} while(0) -#endif /* DEBUG */ -#define err(format, arg...) printf("ERROR: " format "\n", ## arg) -#ifdef SHOW_INFO -#define info(format, arg...) printf("INFO: " format "\n", ## arg) -#else -#define info(format, arg...) do {} while(0) -#endif - -#define m16_swap(x) swap_16(x) -#define m32_swap(x) swap_32(x) - -#ifdef CONFIG_440EP -#define ohci_cpu_to_le16(x) (x) -#define ohci_cpu_to_le32(x) (x) -#else -#define ohci_cpu_to_le16(x) swap_16(x) -#define ohci_cpu_to_le32(x) swap_32(x) -#endif - -/* global ohci_t */ -static ohci_t gohci; -/* this must be aligned to a 256 byte boundary */ -struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* urb_priv */ -urb_priv_t urb_priv; -/* RHSC flag */ -int got_rhsc; -/* device which was disconnected */ -struct usb_device *devgone; -/* flag guarding URB transation */ -int urb_finished = 0; - -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a (struct ohci *hc) - { return read_roothub (hc, a, 0xfc0fe000); } -static inline u32 roothub_b (struct ohci *hc) - { return readl (&hc->regs->roothub.b); } -static inline u32 roothub_status (struct ohci *hc) - { return readl (&hc->regs->roothub.status); } -static u32 roothub_portstatus (struct ohci *hc, int i) - { return read_roothub (hc, portstatus [i], 0xffe0fce0); } - - -/* forward declaration */ -static int hc_interrupt (void); -static void -td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); - -/*-------------------------------------------------------------------------* - * URB support functions - *-------------------------------------------------------------------------*/ - -/* free HCD-private data associated with this URB */ - -static void urb_free_priv (urb_priv_t * urb) -{ - int i; - int last; - struct td * td; - - last = urb->length - 1; - if (last >= 0) { - for (i = 0; i <= last; i++) { - td = urb->td[i]; - if (td) { - td->usb_dev = NULL; - urb->td[i] = NULL; - } - } - } -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -static int sohci_get_current_frame_number (struct usb_device * dev); - -/* debug| print the main components of an URB - * small: 0) header + data packets 1) just header */ - -static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, char * str, int small) -{ - urb_priv_t * purb = &urb_priv; - - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", - str, - sohci_get_current_frame_number (dev), - usb_pipedevice (pipe), - usb_pipeendpoint (pipe), - usb_pipeout (pipe)? 'O': 'I', - usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): - (usb_pipecontrol (pipe)? "CTRL": "BULK"), - purb->actual_length, - transfer_len, dev->status); -#ifdef OHCI_VERBOSE_DEBUG - if (!small) { - int i, len; - - if (usb_pipecontrol (pipe)) { - printf (__FILE__ ": cmd(8):"); - for (i = 0; i < 8 ; i++) - printf (" %02x", ((__u8 *) setup) [i]); - printf ("\n"); - } - if (transfer_len > 0 && buffer) { - printf (__FILE__ ": data(%d/%d):", - purb->actual_length, - transfer_len); - len = usb_pipeout (pipe)? - transfer_len: purb->actual_length; - for (i = 0; i < 16 && i < len; i++) - printf (" %02x", ((__u8 *) buffer) [i]); - printf ("%s\n", i < len? "...": ""); - } - } -#endif -} - -/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ -void ep_print_int_eds (ohci_t *ohci, char * str) { - int i, j; - __u32 * ed_p; - for (i= 0; i < 32; i++) { - j = 5; - ed_p = &(ohci->hcca->int_table [i]); - if (*ed_p == 0) - continue; - printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); - while (*ed_p != 0 && j--) { - ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p); - printf (" ed: %4x;", ed->hwINFO); - ed_p = &ed->hwNextED; - } - printf ("\n"); - } -} - -static void ohci_dump_intr_mask (char *label, __u32 mask) -{ - dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", - label, - mask, - (mask & OHCI_INTR_MIE) ? " MIE" : "", - (mask & OHCI_INTR_OC) ? " OC" : "", - (mask & OHCI_INTR_RHSC) ? " RHSC" : "", - (mask & OHCI_INTR_FNO) ? " FNO" : "", - (mask & OHCI_INTR_UE) ? " UE" : "", - (mask & OHCI_INTR_RD) ? " RD" : "", - (mask & OHCI_INTR_SF) ? " SF" : "", - (mask & OHCI_INTR_WDH) ? " WDH" : "", - (mask & OHCI_INTR_SO) ? " SO" : "" - ); -} - -static void maybe_print_eds (char *label, __u32 value) -{ - ed_t *edp = (ed_t *)value; - - if (value) { - dbg ("%s %08x", label, value); - dbg ("%08x", edp->hwINFO); - dbg ("%08x", edp->hwTailP); - dbg ("%08x", edp->hwHeadP); - dbg ("%08x", edp->hwNextED); - } -} - -static char * hcfs2string (int state) -{ - switch (state) { - case OHCI_USB_RESET: return "reset"; - case OHCI_USB_RESUME: return "resume"; - case OHCI_USB_OPER: return "operational"; - case OHCI_USB_SUSPEND: return "suspend"; - } - return "?"; -} - -/* dump control and status registers */ -static void ohci_dump_status (ohci_t *controller) -{ - struct ohci_regs *regs = controller->regs; - __u32 temp; - - temp = readl (®s->revision) & 0xff; - if (temp != 0x10) - dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); - - temp = readl (®s->control); - dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, - (temp & OHCI_CTRL_RWE) ? " RWE" : "", - (temp & OHCI_CTRL_RWC) ? " RWC" : "", - (temp & OHCI_CTRL_IR) ? " IR" : "", - hcfs2string (temp & OHCI_CTRL_HCFS), - (temp & OHCI_CTRL_BLE) ? " BLE" : "", - (temp & OHCI_CTRL_CLE) ? " CLE" : "", - (temp & OHCI_CTRL_IE) ? " IE" : "", - (temp & OHCI_CTRL_PLE) ? " PLE" : "", - temp & OHCI_CTRL_CBSR - ); - - temp = readl (®s->cmdstatus); - dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, - (temp & OHCI_SOC) >> 16, - (temp & OHCI_OCR) ? " OCR" : "", - (temp & OHCI_BLF) ? " BLF" : "", - (temp & OHCI_CLF) ? " CLF" : "", - (temp & OHCI_HCR) ? " HCR" : "" - ); - - ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); - ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); - - maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); - - maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); - maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); - - maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); - maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); - - maybe_print_eds ("donehead", readl (®s->donehead)); -} - -static void ohci_dump_roothub (ohci_t *controller, int verbose) -{ - __u32 temp, ndp, i; - - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - - if (verbose) { - dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, - ((temp & RH_A_POTPGT) >> 24) & 0xff, - (temp & RH_A_NOCP) ? " NOCP" : "", - (temp & RH_A_OCPM) ? " OCPM" : "", - (temp & RH_A_DT) ? " DT" : "", - (temp & RH_A_NPS) ? " NPS" : "", - (temp & RH_A_PSM) ? " PSM" : "", - ndp - ); - temp = roothub_b (controller); - dbg ("roothub.b: %08x PPCM=%04x DR=%04x", - temp, - (temp & RH_B_PPCM) >> 16, - (temp & RH_B_DR) - ); - temp = roothub_status (controller); - dbg ("roothub.status: %08x%s%s%s%s%s%s", - temp, - (temp & RH_HS_CRWE) ? " CRWE" : "", - (temp & RH_HS_OCIC) ? " OCIC" : "", - (temp & RH_HS_LPSC) ? " LPSC" : "", - (temp & RH_HS_DRWE) ? " DRWE" : "", - (temp & RH_HS_OCI) ? " OCI" : "", - (temp & RH_HS_LPS) ? " LPS" : "" - ); - } - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", - i, - temp, - (temp & RH_PS_PRSC) ? " PRSC" : "", - (temp & RH_PS_OCIC) ? " OCIC" : "", - (temp & RH_PS_PSSC) ? " PSSC" : "", - (temp & RH_PS_PESC) ? " PESC" : "", - (temp & RH_PS_CSC) ? " CSC" : "", - - (temp & RH_PS_LSDA) ? " LSDA" : "", - (temp & RH_PS_PPS) ? " PPS" : "", - (temp & RH_PS_PRS) ? " PRS" : "", - (temp & RH_PS_POCI) ? " POCI" : "", - (temp & RH_PS_PSS) ? " PSS" : "", - - (temp & RH_PS_PES) ? " PES" : "", - (temp & RH_PS_CCS) ? " CCS" : "" - ); - } -} - -static void ohci_dump (ohci_t *controller, int verbose) -{ - dbg ("OHCI controller usb-%s state", controller->slot_name); - - /* dumps some of the state we know about */ - ohci_dump_status (controller); - if (verbose) - ep_print_int_eds (controller, "hcca"); - dbg ("hcca frame #%04x", controller->hcca->frame_no); - ohci_dump_roothub (controller, 1); -} - - -#endif /* DEBUG */ - -/*-------------------------------------------------------------------------* - * Interface functions (URB) - *-------------------------------------------------------------------------*/ - -/* get a transfer request */ - -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - ohci_t *ohci; - ed_t * ed; - urb_priv_t *purb_priv; - int i, size = 0; - - ohci = &gohci; - - /* when controller's hung, permit only roothub cleanup attempts - * such as powering down ports */ - if (ohci->disabled) { - err("sohci_submit_job: EPIPE"); - return -1; - } - - /* if we have an unfinished URB from previous transaction let's - * fail and scream as quickly as possible so as not to corrupt - * further communication */ - if (!urb_finished) { - err("sohci_submit_job: URB NOT FINISHED"); - return -1; - } - /* we're about to begin a new transaction here so mark the URB unfinished */ - urb_finished = 0; - - /* every endpoint has a ed, locate and fill it */ - if (!(ed = ep_add_ed (dev, pipe))) { - err("sohci_submit_job: ENOMEM"); - return -1; - } - - /* for the private part of the URB we need the number of TDs (size) */ - switch (usb_pipetype (pipe)) { - case PIPE_BULK: /* one TD for every 4096 Byte */ - size = (transfer_len - 1) / 4096 + 1; - break; - case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ - size = (transfer_len == 0)? 2: - (transfer_len - 1) / 4096 + 3; - break; - } - - if (size >= (N_URB_TD - 1)) { - err("need %d TDs, only have %d", size, N_URB_TD); - return -1; - } - purb_priv = &urb_priv; - purb_priv->pipe = pipe; - - /* fill the private part of the URB */ - purb_priv->length = size; - purb_priv->ed = ed; - purb_priv->actual_length = 0; - - /* allocate the TDs */ - /* note that td[0] was allocated in ep_add_ed */ - for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc (dev); - if (!purb_priv->td[i]) { - purb_priv->length = i; - urb_free_priv (purb_priv); - err("sohci_submit_job: ENOMEM"); - return -1; - } - } - - if (ed->state == ED_NEW || (ed->state & ED_DEL)) { - urb_free_priv (purb_priv); - err("sohci_submit_job: EINVAL"); - return -1; - } - - /* link the ed into a chain if is not already */ - if (ed->state != ED_OPER) - ep_link (ohci, ed); - - /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -/* tell us the current USB frame number */ - -static int sohci_get_current_frame_number (struct usb_device *usb_dev) -{ - ohci_t *ohci = &gohci; - - return ohci_cpu_to_le16 (ohci->hcca->frame_no); -} -#endif - -/*-------------------------------------------------------------------------* - * ED handling functions - *-------------------------------------------------------------------------*/ - -/* link an ed into one of the HC chains */ - -static int ep_link (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->state = ED_OPER; - - switch (ed->type) { - case PIPE_CONTROL: - ed->hwNextED = 0; - if (ohci->ed_controltail == NULL) { - writel (ed, &ohci->regs->ed_controlhead); - } else { - ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); - } - ed->ed_prev = ohci->ed_controltail; - if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_controltail = edi; - break; - - case PIPE_BULK: - ed->hwNextED = 0; - if (ohci->ed_bulktail == NULL) { - writel (ed, &ohci->regs->ed_bulkhead); - } else { - ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed); - } - ed->ed_prev = ohci->ed_bulktail; - if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_bulktail = edi; - break; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* unlink an ed from one of the HC chains. - * just the link to the ed is unlinked. - * the link from the ed still points to another operational ed or 0 - * so the HC can eventually finish the processing of the unlinked ed */ - -static int ep_unlink (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP); - - switch (ed->type) { - case PIPE_CONTROL: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_controltail == ed) { - ohci->ed_controltail = ed->ed_prev; - } else { - ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - - case PIPE_BULK: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_bulktail == ed) { - ohci->ed_bulktail = ed->ed_prev; - } else { - ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - } - ed->state = ED_UNLINK; - return 0; -} - - -/*-------------------------------------------------------------------------*/ - -/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, - * but the USB stack is a little bit stateless so we do it at every transaction - * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK - * in all other cases the state is left unchanged - * the ed info fields are setted anyway even though most of them should not change */ - -static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) -{ - td_t *td; - ed_t *ed_ret; - volatile ed_t *ed; - - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | - (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; - - if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { - err("ep_add_ed: pending delete"); - /* pending delete request */ - return NULL; - } - - if (ed->state == ED_NEW) { - ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */ - /* dummy td; end of td list for ed */ - td = td_alloc (usb_dev); - ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td); - ed->hwHeadP = ed->hwTailP; - ed->state = ED_UNLINK; - ed->type = usb_pipetype (pipe); - ohci_dev.ed_cnt++; - } - - ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe) - | usb_pipeendpoint (pipe) << 7 - | (usb_pipeisoc (pipe)? 0x8000: 0) - | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | usb_pipeslow (pipe) << 13 - | usb_maxpacket (usb_dev, pipe) << 16); - - return ed_ret; -} - -/*-------------------------------------------------------------------------* - * TD handling functions - *-------------------------------------------------------------------------*/ - -/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ - -static void td_fill (ohci_t *ohci, unsigned int info, - void *data, int len, - struct usb_device *dev, int index, urb_priv_t *urb_priv) -{ - volatile td_t *td, *td_pt; -#ifdef OHCI_FILL_TRACE - int i; -#endif - - if (index > urb_priv->length) { - err("index > length"); - return; - } - /* use this td as the next dummy */ - td_pt = urb_priv->td [index]; - td_pt->hwNextTD = 0; - - /* fill the old dummy TD */ - td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf); - - td->ed = urb_priv->ed; - td->next_dl_td = NULL; - td->index = index; - td->data = (__u32)data; -#ifdef OHCI_FILL_TRACE - if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { - for (i = 0; i < len; i++) - printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); - printf("\n"); - } -#endif - if (!len) - data = 0; - - td->hwINFO = ohci_cpu_to_le32 (info); - td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data); - if (data) - td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1)); - else - td->hwBE = 0; - td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt); - - /* append to queue */ - td->ed->hwTailP = td->hwNextTD; -} - -/*-------------------------------------------------------------------------*/ - -/* prepare all TDs of a transfer */ -static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) -{ - ohci_t *ohci = &gohci; - int data_len = transfer_len; - void *data; - int cnt = 0; - __u32 info = 0; - unsigned int toggle = 0; - - /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ - if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { - toggle = TD_T_TOGGLE; - } else { - toggle = TD_T_DATA0; - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); - } - urb->td_cnt = 0; - if (data_len) - data = buffer; - else - data = 0; - - switch (usb_pipetype (pipe)) { - case PIPE_BULK: - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; - while(data_len > 4096) { - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); - data += 4096; data_len -= 4096; cnt++; - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); - cnt++; - - if (!ohci->sleeping) - writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ - break; - - case PIPE_CONTROL: - info = TD_CC | TD_DP_SETUP | TD_T_DATA0; - td_fill (ohci, info, setup, 8, dev, cnt++, urb); - if (data_len > 0) { - info = usb_pipeout (pipe)? - TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; - /* NOTE: mishandles transfers >8K, some >4K */ - td_fill (ohci, info, data, data_len, dev, cnt++, urb); - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; - td_fill (ohci, info, data, 0, dev, cnt++, urb); - if (!ohci->sleeping) - writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ - break; - } - if (urb->length != cnt) - dbg("TD LENGTH %d != CNT %d", urb->length, cnt); -} - -/*-------------------------------------------------------------------------* - * Done List handling functions - *-------------------------------------------------------------------------*/ - - -/* calculate the transfer length and update the urb */ - -static void dl_transfer_length(td_t * td) -{ - __u32 tdINFO, tdBE, tdCBP; - urb_priv_t *lurb_priv = &urb_priv; - - tdINFO = ohci_cpu_to_le32 (td->hwINFO); - tdBE = ohci_cpu_to_le32 (td->hwBE); - tdCBP = ohci_cpu_to_le32 (td->hwCBP); - - - if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && - ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { - if (tdBE != 0) { - if (td->hwCBP == 0) - lurb_priv->actual_length += tdBE - td->data + 1; - else - lurb_priv->actual_length += tdCBP - td->data; - } - } -} - -/*-------------------------------------------------------------------------*/ - -/* replies to the request have to be on a FIFO basis so - * we reverse the reversed done-list */ - -static td_t * dl_reverse_done_list (ohci_t *ohci) -{ - __u32 td_list_hc; - td_t *td_rev = NULL; - td_t *td_list = NULL; - urb_priv_t *lurb_priv = NULL; - - td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0; - ohci->hcca->done_head = 0; - - while (td_list_hc) { - td_list = (td_t *)td_list_hc; - - if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) { - lurb_priv = &urb_priv; - dbg(" USB-error/status: %x : %p", - TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list); - if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) { - if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { - td_list->ed->hwHeadP = - (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) | - (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2)); - lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; - } else - td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2); - } -#ifdef CONFIG_MPC5200 - td_list->hwNextTD = 0; -#endif - } - - td_list->next_dl_td = td_rev; - td_rev = td_list; - td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0; - } - return td_list; -} - -/*-------------------------------------------------------------------------*/ - -/* td done list */ -static int dl_done_list (ohci_t *ohci, td_t *td_list) -{ - td_t *td_list_next = NULL; - ed_t *ed; - int cc = 0; - int stat = 0; - /* urb_t *urb; */ - urb_priv_t *lurb_priv; - __u32 tdINFO, edHeadP, edTailP; - - while (td_list) { - td_list_next = td_list->next_dl_td; - - lurb_priv = &urb_priv; - tdINFO = ohci_cpu_to_le32 (td_list->hwINFO); - - ed = td_list->ed; - - dl_transfer_length(td_list); - - /* error code of transfer */ - cc = TD_CC_GET (tdINFO); - if (++(lurb_priv->td_cnt) == lurb_priv->length) { - if ((ed->state & (ED_OPER | ED_UNLINK)) - && (lurb_priv->state != URB_DEL)) { - dbg("ConditionCode %#x", cc); - stat = cc_to_error[cc]; - urb_finished = 1; - } - } - - if (ed->state != ED_NEW) { - edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0; - edTailP = ohci_cpu_to_le32 (ed->hwTailP); - - /* unlink eds if they are not busy */ - if ((edHeadP == edTailP) && (ed->state == ED_OPER)) - ep_unlink (ohci, ed); - } - - td_list = td_list_next; - } - return stat; -} - -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ - -/* Device descriptor */ -static __u8 root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - -/* Hub class-specific descriptor is constructed dynamically */ - - -/*-------------------------------------------------------------------------*/ - -#define OK(x) len = (x); break -#ifdef DEBUG -#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} -#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} -#else -#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) -#endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) - -/* request to virtual root hub */ - -int rh_check_port_status(ohci_t *controller) -{ - __u32 temp, ndp, i; - int res; - - res = -1; - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - /* check for a device disconnect */ - if (((temp & (RH_PS_PESC | RH_PS_CSC)) == - (RH_PS_PESC | RH_PS_CSC)) && - ((temp & RH_PS_CCS) == 0)) { - res = i; - break; - } - } - return res; -} - -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *cmd) -{ - void * data = buffer; - int leni = transfer_len; - int len = 0; - int stat = 0; - __u32 datab[4]; - __u8 *data_buf = (__u8 *)datab; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; - -#ifdef DEBUG -urb_priv.actual_length = 0; -pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); -#endif - if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { - info("Root-Hub submit IRQ: NOT implemented"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = m16_swap (cmd->value); - wIndex = m16_swap (cmd->index); - wLength = m16_swap (cmd->length); - - info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", - dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(__u16 *) data_buf = m16_swap (1); OK (2); - case RH_GET_STATUS | RH_INTERFACE: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_ENDPOINT: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_CLASS: - *(__u32 *) data_buf = m32_swap ( - RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); - OK (4); - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); - - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case RH_C_HUB_LOCAL_POWER: - OK(0); - case (RH_C_HUB_OVER_CURRENT): - WR_RH_STAT(RH_HS_OCIC); OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_POCI); OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); - case (RH_C_PORT_CONNECTION): - WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); - case (RH_C_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_PESC); OK (0); - case (RH_C_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); - case (RH_C_PORT_OVER_CURRENT): - WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); - case (RH_C_PORT_RESET): - WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); - } - break; - - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); - case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PRS); - OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); - case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PES ); - OK (0); - } - break; - - case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_dev_des), - wLength)); - data_buf = root_hub_dev_des; OK(len); - case (0x02): /* configuration descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_config_des), - wLength)); - data_buf = root_hub_config_des; OK(len); - case (0x03): /* string descriptors */ - if(wValue==0x0300) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index0), - wLength)); - data_buf = root_hub_str_index0; - OK(len); - } - if(wValue==0x0301) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index1), - wLength)); - data_buf = root_hub_str_index1; - OK(len); - } - default: - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - { - __u32 temp = roothub_a (&gohci); - - data_buf [0] = 9; /* min length; */ - data_buf [1] = 0x29; - data_buf [2] = temp & RH_A_NDP; - data_buf [3] = 0; - if (temp & RH_A_PSM) /* per-port power switching? */ - data_buf [3] |= 0x1; - if (temp & RH_A_NOCP) /* no overcurrent reporting? */ - data_buf [3] |= 0x10; - else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ - data_buf [3] |= 0x8; - - /* corresponds to data_buf[4-7] */ - datab [1] = 0; - data_buf [5] = (temp & RH_A_POTPGT) >> 24; - temp = roothub_b (&gohci); - data_buf [7] = temp & RH_B_DR; - if (data_buf [2] < 7) { - data_buf [8] = 0xff; - } else { - data_buf [0] += 2; - data_buf [8] = (temp & RH_B_DR) >> 8; - data_buf [10] = data_buf [9] = 0xff; - } - - len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf [0], wLength)); - OK (len); - } - - case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); - - case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); - - default: - dbg ("unsupported root hub command"); - stat = USB_ST_STALLED; - } - -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - - len = min_t(int, len, leni); - if (data != data_buf) - memcpy (data, data_buf, len); - dev->act_len = len; - dev->status = stat; - -#ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); -#endif - - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/* common code for handling submit messages - used for all but root hub */ -/* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; - - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } - -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#endif - if (!maxsize) { - err("submit_common_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { - err("sohci_submit_job failed"); - return -1; - } - - /* allow more time for a BULK device to react - some are slow */ -#define BULK_TO 5000 /* timeout in milliseconds */ - if (usb_pipetype (pipe) == PIPE_BULK) - timeout = BULK_TO; - else - timeout = 100; - - /* wait for it to complete */ - for (;;) { - /* check whether the controller is done */ - stat = hc_interrupt(); - if (stat < 0) { - stat = USB_ST_CRC_ERR; - break; - } - - /* NOTE: since we are not interrupt driven in U-Boot and always - * handle only one URB at a time, we cannot assume the - * transaction finished on the first successful return from - * hc_interrupt().. unless the flag for current URB is set, - * meaning that all TD's to/from device got actually - * transferred and processed. If the current URB is not - * finished we need to re-iterate this loop so as - * hc_interrupt() gets called again as there needs to be some - * more TD's to process still */ - if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { - /* 0xff is returned for an SF-interrupt */ - break; - } - - if (--timeout) { - wait_ms(1); - if (!urb_finished) - dbg("\%"); - - } else { - err("CTL:TIMEOUT "); - dbg("submit_common_msg: TO status %x\n", stat); - stat = USB_ST_CRC_ERR; - urb_finished = 1; - break; - } - } -#if 0 - /* we got an Root Hub Status Change interrupt */ - if (got_rhsc) { -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - got_rhsc = 0; - /* abuse timeout */ - timeout = rh_check_port_status(&gohci); - if (timeout >= 0) { -#if 0 /* this does nothing useful, but leave it here in case that changes */ - /* the called routine adds 1 to the passed value */ - usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); -#endif - /* - * XXX - * This is potentially dangerous because it assumes - * that only one device is ever plugged in! - */ - devgone = dev; - } - } -#endif - - dev->status = stat; - dev->act_len = transfer_len; - -#ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); -#endif - - /* free TDs in urb_priv */ - urb_free_priv (&urb_priv); - return 0; -} - -/* submit routines called from usb.c */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) -{ - info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) -{ - int maxsize = usb_maxpacket(dev, pipe); - - info("submit_control_msg"); -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#endif - if (!maxsize) { - err("submit_control_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; - /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); - } - - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return -1; -} - -/*-------------------------------------------------------------------------* - * HC functions - *-------------------------------------------------------------------------*/ - -/* reset the HC and BUS */ - -static int hc_reset (ohci_t *ohci) -{ - int timeout = 30; - int smm_timeout = 50; /* 0,5 sec */ - - if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ - writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ - info("USB HC TakeOver from SMM"); - while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms (10); - if (--smm_timeout == 0) { - err("USB HC TakeOver failed!"); - return -1; - } - } - } - - /* Disable HC interrupts */ - writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); - - dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", - ohci->slot_name, - readl (&ohci->regs->control)); - - /* Reset USB (needed by some controllers) */ - ohci->hc_control = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* HC Reset requires max 10 us delay */ - writel (OHCI_HCR, &ohci->regs->cmdstatus); - while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { - if (--timeout == 0) { - err("USB HC reset timed out!"); - return -1; - } - udelay (1); - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* Start an OHCI controller, set the BUS operational - * enable interrupts - * connect the virtual root hub */ - -static int hc_start (ohci_t * ohci) -{ - __u32 mask; - unsigned int fminterval; - - ohci->disabled = 1; - - /* Tell the controller where the control and bulk lists are - * The lists are empty now. */ - - writel (0, &ohci->regs->ed_controlhead); - writel (0, &ohci->regs->ed_bulkhead); - - writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ - - fminterval = 0x2edf; - writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); - fminterval |= ((((fminterval - 210) * 6) / 7) << 16); - writel (fminterval, &ohci->regs->fminterval); - writel (0x628, &ohci->regs->lsthresh); - - /* start controller operations */ - ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; - ohci->disabled = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* disable all interrupts */ - mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | - OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | - OHCI_INTR_OC | OHCI_INTR_MIE); - writel (mask, &ohci->regs->intrdisable); - /* clear all interrupts */ - mask &= ~OHCI_INTR_MIE; - writel (mask, &ohci->regs->intrstatus); - /* Choose the interrupts we care about now - but w/o MIE */ - mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; - writel (mask, &ohci->regs->intrenable); - -#ifdef OHCI_USE_NPS - /* required for AMD-756 and some Mac platforms */ - writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, - &ohci->regs->roothub.a); - writel (RH_HS_LPSC, &ohci->regs->roothub.status); -#endif /* OHCI_USE_NPS */ - -#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay ((roothub_a (ohci) >> 23) & 0x1fe); - - /* connect the virtual root hub */ - ohci->rh.devnum = 0; - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* an interrupt happens */ - -static int -hc_interrupt (void) -{ - ohci_t *ohci = &gohci; - struct ohci_regs *regs = ohci->regs; - int ints; - int stat = -1; - - if ((ohci->hcca->done_head != 0) && - !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) { - - ints = OHCI_INTR_WDH; - - } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) { - ohci->disabled++; - err ("%s device removed!", ohci->slot_name); - return -1; - - } else if ((ints &= readl (®s->intrenable)) == 0) { - dbg("hc_interrupt: returning..\n"); - return 0xff; - } - - /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ - - if (ints & OHCI_INTR_RHSC) { - got_rhsc = 1; - stat = 0xff; - } - - if (ints & OHCI_INTR_UE) { - ohci->disabled++; - err ("OHCI Unrecoverable Error, controller usb-%s disabled", - ohci->slot_name); - /* e.g. due to PCI Master/Target Abort */ - -#ifdef DEBUG - ohci_dump (ohci, 1); -#endif - /* FIXME: be optimistic, hope that bug won't repeat often. */ - /* Make some non-interrupt context restart the controller. */ - /* Count and limit the retries though; either hardware or */ - /* software errors can go forever... */ - hc_reset (ohci); - return -1; - } - - if (ints & OHCI_INTR_WDH) { - writel (OHCI_INTR_WDH, ®s->intrdisable); - stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); - writel (OHCI_INTR_WDH, ®s->intrenable); - } - - if (ints & OHCI_INTR_SO) { - dbg("USB Schedule overrun\n"); - writel (OHCI_INTR_SO, ®s->intrenable); - stat = -1; - } - - /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ - if (ints & OHCI_INTR_SF) { - unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1; - wait_ms(1); - writel (OHCI_INTR_SF, ®s->intrdisable); - if (ohci->ed_rm_list[frame] != NULL) - writel (OHCI_INTR_SF, ®s->intrenable); - stat = 0xff; - } - - writel (ints, ®s->intrstatus); - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -/* De-allocate all resources.. */ - -static void hc_release_ohci (ohci_t *ohci) -{ - dbg ("USB HC release ohci usb-%s", ohci->slot_name); - - if (!ohci->disabled) - hc_reset (ohci); -} - -/*-------------------------------------------------------------------------*/ - -/* - * low level initalisation routine, called from usb.c - */ -static char ohci_inited = 0; - -int usb_lowlevel_init(void) -{ - memset (&gohci, 0, sizeof (ohci_t)); - memset (&urb_priv, 0, sizeof (urb_priv_t)); - - /* align the storage */ - if ((__u32)&ghcca[0] & 0xff) { - err("HCCA not aligned!!"); - return -1; - } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32)&ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); - if ((__u32)gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset (phcca, 0, sizeof (struct ohci_hcca)); - - gohci.disabled = 1; - gohci.sleeping = 0; - gohci.irq = -1; - gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); - - gohci.flags = 0; - gohci.slot_name = "ppc440"; - - if (hc_reset (&gohci) < 0) { - hc_release_ohci (&gohci); - return -1; - } - - if (hc_start (&gohci) < 0) { - err ("can't start usb-%s", gohci.slot_name); - hc_release_ohci (&gohci); - return -1; - } - -#ifdef DEBUG - ohci_dump (&gohci, 1); -#endif - ohci_inited = 1; - urb_finished = 1; - - /* init the device driver */ - usb_dev_init(); - - return 0; -} - -int usb_lowlevel_stop(void) -{ - /* this gets called really early - before the controller has */ - /* even been initialized! */ - if (!ohci_inited) - return 0; - /* TODO release any interrupts, etc. */ - /* call hc_release_ohci() here ? */ - hc_reset (&gohci); - return 0; -} - -#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/ppc4xx/usb_ohci.h b/cpu/ppc4xx/usb_ohci.h deleted file mode 100644 index 706e05e..0000000 --- a/cpu/ppc4xx/usb_ohci.h +++ /dev/null @@ -1,410 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB. - * - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2001 David Brownell - * - * usb-ohci.h - */ - -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -/* ED States */ - -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 -#define ED_OPER 0x02 -#define ED_DEL 0x04 -#define ED_URB_DEL 0x08 - -/* usb_ohci_ed */ -struct ed { - __u32 hwINFO; - __u32 hwTailP; - __u32 hwHeadP; - __u32 hwNextED; - - struct ed *ed_prev; - __u8 int_period; - __u8 int_branch; - __u8 int_load; - __u8 int_interval; - __u8 state; - __u8 type; - __u16 last_iso; - struct ed *ed_rm_list; - - struct usb_device *usb_dev; - __u32 unused[3]; -} __attribute((aligned(16))); -typedef struct ed ed_t; - -/* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 - -/* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F - -#define MAXPSW 1 - -struct td { - __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u16 hwPSW[MAXPSW]; - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; - struct usb_device *usb_dev; - int transfer_len; - __u32 data; - - __u32 unused2[2]; -} __attribute((aligned(32))); -typedef struct td td_t; - -#define OHCI_ED_SKIP (1 << 14) - -/* - * The HCCA (Host Controller Communications Area) is a 256 byte - * structure defined in the OHCI spec. that the host controller is - * told the base address of. It must be 256-byte aligned. - */ - -#define NUM_INTS 32 /* part of the OHCI standard */ -struct ohci_hcca { - __u32 int_table[NUM_INTS]; /* Interrupt ED table */ -#if defined(CONFIG_MPC5200) - __u16 pad1; /* set to 0 on each frame_no change */ - __u16 frame_no; /* current frame number */ -#else - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ -#endif - __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; -} __attribute((aligned(256))); - -/* - * Maximum number of root hub ports. - */ -#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ - -/* - * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and - * writel() macros defined in asm/io.h to access these!! - */ -struct ohci_regs { - /* control and status registers */ - __u32 revision; - __u32 control; - __u32 cmdstatus; - __u32 intrstatus; - __u32 intrenable; - __u32 intrdisable; - /* memory pointers */ - __u32 hcca; - __u32 ed_periodcurrent; - __u32 ed_controlhead; - __u32 ed_controlcurrent; - __u32 ed_bulkhead; - __u32 ed_bulkcurrent; - __u32 donehead; - /* frame counters */ - __u32 fminterval; - __u32 fmremaining; - __u32 fmnumber; - __u32 periodicstart; - __u32 lsthresh; - /* Root hub ports */ - struct ohci_roothub_regs { - __u32 a; - __u32 b; - __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; - } roothub; -} __attribute((aligned(32))); - -/* OHCI CONTROL AND STATUS REGISTER MASKS */ - -/* - * HcControl (control) register masks - */ -#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ -#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ - -/* pre-shifted values for HCFS */ -# define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) -# define OHCI_USB_OPER (2 << 6) -# define OHCI_USB_SUSPEND (3 << 6) - -/* - * HcCommandStatus (cmdstatus) register masks - */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ - -/* - * masks used with interrupt registers: - * HcInterruptStatus (intrstatus) - * HcInterruptEnable (intrenable) - * HcInterruptDisable (intrdisable) - */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ - -/* Virtual Root HUB */ -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - void *dev; /* was urb */ - void *int_addr; - int send; - int interval; -}; - -/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ - -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - -/* OHCI ROOT HUB REGISTER MASKS */ - -/* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status */ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ - -/* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ - -/* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ - -/* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ - -/* urb */ -#define N_URB_TD 48 -typedef struct { - ed_t *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ - int state; - unsigned long pipe; - int actual_length; - td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ -} urb_priv_t; -#define URB_DEL 1 - -/* - * This is the full ohci controller description - * - * Note how the "proper" USB information is just - * a subset of what the full implementation needs. (Linus) - */ - -typedef struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma; */ - - int irq; - int disabled; /* e.g. got a UE, we're hung */ - int sleeping; - unsigned long flags; /* for HC bugs */ - - struct ohci_regs *regs; /* OHCI controller's memory */ - - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ - int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ - struct usb_device *dev[32]; - struct virt_root_hub rh; - - const char *slot_name; -} ohci_t; - -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - ed_t ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(ohci_t * ohci, ed_t * ed); -static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -td_t gtd[NUM_TD + 1]; -/* pointers to aligned storage */ -td_t *ptd; - -/* TDs ... */ -static inline struct td *td_alloc(struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) { - if (ptd[i].usb_dev == NULL) { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - - return td; -} - -static inline void ed_free(struct ed *ed) -{ - ed->usb_dev = NULL; -} diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c deleted file mode 100644 index 8262c54..0000000 --- a/cpu/ppc4xx/usbdev.c +++ /dev/null @@ -1,214 +0,0 @@ -/*USB 1.1,2.0 device*/ - -#include -#include - -#ifdef CONFIG_440EP - -#include -#include "usbdev.h" -#include "vecnum.h" - -#define USB_DT_DEVICE 0x01 -#define USB_DT_CONFIG 0x02 -#define USB_DT_STRING 0x03 -#define USB_DT_INTERFACE 0x04 -#define USB_DT_ENDPOINT 0x05 - -int set_value = -1; - -void process_endpoints(unsigned short usb2d0_intrin) -{ - /*will hold the packet received */ - struct usb_device_descriptor usb_device_packet; - struct usb_config_descriptor usb_config_packet; - struct usb_string_descriptor usb_string_packet; - struct devrequest setup_packet; - unsigned int *setup_packet_pt; - unsigned char *packet_pt = NULL; - int temp, temp1; - - int i; - - /*printf("{USB device} - endpoint 0x%X \n", usb2d0_intrin); */ - - /*set usb address, seems to not work unless it is done in the next - interrupt, so that is why it is done this way */ - if (set_value != -1) - *(unsigned char *)USB2D0_FADDR_8 = (unsigned char)set_value; - - /*endpoint 1 */ - if (usb2d0_intrin & 0x01) { - setup_packet_pt = (unsigned int *)&setup_packet; - - /*copy packet */ - setup_packet_pt[0] = *(unsigned int *)USB2D0_FIFO_0; - setup_packet_pt[1] = *(unsigned int *)USB2D0_FIFO_0; - temp = *(unsigned int *)USB2D0_FIFO_0; - temp1 = *(unsigned int *)USB2D0_FIFO_0; - - /*do some swapping */ - setup_packet.value = swap_16(setup_packet.value); - setup_packet.index = swap_16(setup_packet.index); - setup_packet.length = swap_16(setup_packet.length); - - /*clear rx packet */ - *(unsigned short *)USB2D0_INCSR0_8 = 0x48; - - /*printf("0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n", setup_packet.requesttype, - setup_packet.request, setup_packet.value, - setup_packet.index, setup_packet.length, temp, temp1 ); */ - - switch (setup_packet.request) { - case USB_REQ_GET_DESCRIPTOR: - - switch (setup_packet.value >> 8) { - case USB_DT_DEVICE: - /*create packet */ - usb_device_packet.bLength = 18; - usb_device_packet.bDescriptorType = - USB_DT_DEVICE; -#ifdef USB_2_0_DEVICE - usb_device_packet.bcdUSB = swap_16(0x200); -#else - usb_device_packet.bcdUSB = swap_16(0x110); -#endif - usb_device_packet.bDeviceClass = 0xff; - usb_device_packet.bDeviceSubClass = 0; - usb_device_packet.bDeviceProtocol = 0; - usb_device_packet.bMaxPacketSize0 = 32; - usb_device_packet.idVendor = swap_16(1); - usb_device_packet.idProduct = swap_16(2); - usb_device_packet.bcdDevice = swap_16(0x300); - usb_device_packet.iManufacturer = 1; - usb_device_packet.iProduct = 1; - usb_device_packet.iSerialNumber = 1; - usb_device_packet.bNumConfigurations = 1; - - /*put packet in fifo */ - packet_pt = (unsigned char *)&usb_device_packet; - break; - - case USB_DT_CONFIG: - /*create packet */ - usb_config_packet.bLength = 9; - usb_config_packet.bDescriptorType = - USB_DT_CONFIG; - usb_config_packet.wTotalLength = swap_16(25); - usb_config_packet.bNumInterfaces = 1; - usb_config_packet.bConfigurationValue = 1; - usb_config_packet.iConfiguration = 0; - usb_config_packet.bmAttributes = 0x40; - usb_config_packet.MaxPower = 0; - - /*put packet in fifo */ - packet_pt = (unsigned char *)&usb_config_packet; - break; - - case USB_DT_STRING: - /*create packet */ - usb_string_packet.bLength = 2; - usb_string_packet.bDescriptorType = - USB_DT_STRING; - usb_string_packet.wData[0] = 0x0094; - - /*put packet in fifo */ - packet_pt = (unsigned char *)&usb_string_packet; - break; - } - - /*put packet in fifo */ - for (i = 0; i < (setup_packet.length); i++) { - *(unsigned char *)USB2D0_FIFO_0 = packet_pt[i]; - } - - /*give tx command */ - *(unsigned short *)USB2D0_INCSR0_8 = 0x0a; - - break; - - case USB_REQ_SET_ADDRESS: - - /*copy usb address */ - set_value = setup_packet.value; - - break; - } - - } -} - -void process_other(unsigned char usb2d0_intrusb) -{ - - /*check for sof */ - if (usb2d0_intrusb & 0x08) { - /*printf("{USB device} - sof detected\n"); */ - } - - /*check for reset */ - if (usb2d0_intrusb & 0x04) { - /*printf("{USB device} - reset detected\n"); */ - - /*copy usb address of zero, need to do this when usb reset */ - set_value = 0; - } - - if (usb2d0_intrusb & 0x02) { - /*printf("{USB device} - resume detected\n"); */ - } - - if (usb2d0_intrusb & 0x01) { - /*printf("{USB device} - suspend detected\n"); */ - } -} - -int usbInt(void) -{ - /*Must read these 2 registers and use values to clear interrupts. If you - do not read them then the interrupt will not be cleared. If you do not - use the variable the optimizer will not do a read. */ - volatile unsigned short usb2d0_intrin = - *(unsigned short *)USB2D0_INTRIN_16; - volatile unsigned char usb2d0_intrusb = - *(unsigned char *)USB2D0_INTRUSB_8; - - /*check if there was an endpoint interrupt */ - if (usb2d0_intrin != 0) { - process_endpoints(usb2d0_intrin); - } - - /*check for other interrupts */ - if (usb2d0_intrusb != 0) { - process_other(usb2d0_intrusb); - } - - return 0; -} - -void usb_dev_init() -{ -#ifdef USB_2_0_DEVICE - printf("USB 2.0 Device init\n"); - /*select 2.0 device */ - mtsdr(sdr_usb0, 0x0); /* 2.0 */ - - /*usb dev init */ - *(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */ -#else - printf("USB 1.1 Device init\n"); - /*select 1.1 device */ - mtsdr(sdr_usb0, 0x2); /* 1.1 */ - - /*usb dev init */ - *(unsigned char *)USB2D0_POWER_8 = 0xc0; /* 1.1 */ -#endif - - /*enable interrupts */ - *(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f; - - irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt, - NULL); -} - -#endif /*CONFIG_440EP */ diff --git a/cpu/ppc4xx/usbdev.h b/cpu/ppc4xx/usbdev.h deleted file mode 100644 index 3446d98..0000000 --- a/cpu/ppc4xx/usbdev.h +++ /dev/null @@ -1,31 +0,0 @@ -#include - -/*Common Registers*/ -#define USB2D0_INTRIN_16 (CFG_USB_DEVICE | 0x100) -#define USB2D0_POWER_8 (CFG_USB_DEVICE | 0x102) -#define USB2D0_FADDR_8 (CFG_USB_DEVICE | 0x103) -#define USB2D0_INTRINE_16 (CFG_USB_DEVICE | 0x104) -#define USB2D0_INTROUT_16 (CFG_USB_DEVICE | 0x106) -#define USB2D0_INTRUSBE_8 (CFG_USB_DEVICE | 0x108) -#define USB2D0_INTRUSB_8 (CFG_USB_DEVICE | 0x109) -#define USB2D0_INTROUTE_16 (CFG_USB_DEVICE | 0x10a) -#define USB2D0_TSTMODE_8 (CFG_USB_DEVICE | 0x10c) -#define USB2D0_INDEX_8 (CFG_USB_DEVICE | 0x10d) -#define USB2D0_FRAME_16 (CFG_USB_DEVICE | 0x10e) - -/*Indexed Registers*/ -#define USB2D0_INCSR0_8 (CFG_USB_DEVICE | 0x110) -#define USB2D0_INCSR_16 (CFG_USB_DEVICE | 0x110) -#define USB2D0_INMAXP_16 (CFG_USB_DEVICE | 0x112) -#define USB2D0_OUTCSR_16 (CFG_USB_DEVICE | 0x114) -#define USB2D0_OUTMAXP_16 (CFG_USB_DEVICE | 0x116) -#define USB2D0_OUTCOUNT0_8 (CFG_USB_DEVICE | 0x11a) -#define USB2D0_OUTCOUNT_16 (CFG_USB_DEVICE | 0x11a) - -/*FIFOs*/ -#define USB2D0_FIFO_0 (CFG_USB_DEVICE | 0x120) -#define USB2D0_FIFO_1 (CFG_USB_DEVICE | 0x124) -#define USB2D0_FIFO_2 (CFG_USB_DEVICE | 0x128) -#define USB2D0_FIFO_3 (CFG_USB_DEVICE | 0x12c) - -void usb_dev_init(void); diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h deleted file mode 100644 index cbfe41d..0000000 --- a/cpu/ppc4xx/vecnum.h +++ /dev/null @@ -1,129 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -/* - * Interrupt vector number definitions to ease the - * 405 -- 440 porting pain ;-) - * - * NOTE: They're not all here yet ... update as needed. - * - */ - -#ifndef _VECNUMS_H_ -#define _VECNUMS_H_ - -#if defined(CONFIG_440SP) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */ -#define VECNUM_MS (32 + 1) /* MAL SERR */ -#define VECNUM_TXDE (32 + 2) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 3) /* MAL RXDE */ -#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */ -#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */ -#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */ -#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ - -#elif defined(CONFIG_440) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 7 /* PCI MSI level 0 */ -#define VECNUM_MSI1 8 /* PCI MSI level 0 */ -#define VECNUM_MSI2 9 /* PCI MSI level 0 */ -#define VECNUM_MTE 10 /* MAL TXEOB */ -#define VECNUM_MRE 11 /* MAL RXEOB */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_CT0 18 /* GPT compare timer 0 */ -#define VECNUM_CT1 19 /* GPT compare timer 1 */ -#define VECNUM_CT2 20 /* GPT compare timer 2 */ -#define VECNUM_CT3 21 /* GPT compare timer 3 */ -#define VECNUM_CT4 22 /* GPT compare timer 4 */ -#define VECNUM_EIR0 23 /* External interrupt 0 */ -#define VECNUM_EIR1 24 /* External interrupt 1 */ -#define VECNUM_EIR2 25 /* External interrupt 2 */ -#define VECNUM_EIR3 26 /* External interrupt 3 */ -#define VECNUM_EIR4 27 /* External interrupt 4 */ -#define VECNUM_EIR5 28 /* External interrupt 5 */ -#define VECNUM_EIR6 29 /* External interrupt 6 */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_MS (32 + 0 ) /* MAL SERR */ -#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */ -#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ - -#else /* !defined(CONFIG_440) */ - -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_D0 5 /* DMA channel 0 */ -#define VECNUM_D1 6 /* DMA channel 1 */ -#define VECNUM_D2 7 /* DMA channel 2 */ -#define VECNUM_D3 8 /* DMA channel 3 */ -#define VECNUM_EWU0 9 /* Ethernet wakeup */ -#define VECNUM_MS 10 /* MAL SERR */ -#define VECNUM_MTE 11 /* MAL TXEOB */ -#define VECNUM_MRE 12 /* MAL RXEOB */ -#define VECNUM_TXDE 13 /* MAL TXDE */ -#define VECNUM_RXDE 14 /* MAL RXDE */ -#define VECNUM_ETH0 15 /* Ethernet interrupt status */ -#define VECNUM_EIR0 25 /* External interrupt 0 */ -#define VECNUM_EIR1 26 /* External interrupt 1 */ -#define VECNUM_EIR2 27 /* External interrupt 2 */ -#define VECNUM_EIR3 28 /* External interrupt 3 */ -#define VECNUM_EIR4 29 /* External interrupt 4 */ -#define VECNUM_EIR5 30 /* External interrupt 5 */ -#define VECNUM_EIR6 31 /* External interrupt 6 */ - -#endif /* defined(CONFIG_440) */ - -#endif /* _VECNUMS_H_ */ diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile deleted file mode 100644 index 1af53d6..0000000 --- a/cpu/pxa/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk deleted file mode 100644 index fb810ca..0000000 --- a/cpu/pxa/config.mk +++ /dev/null @@ -1,36 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float - -#PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 -PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c deleted file mode 100644 index d1551dd..0000000 --- a/cpu/pxa/cpu.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include -#include - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - DECLARE_GLOBAL_DATA_PTR; - - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * just disable everything that can disturb booting linux - */ - - unsigned long i; - - disable_interrupts (); - - /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf ("resetting ...\n"); - - udelay (50000); /* wait 50 ms */ - disable_interrupts (); - reset_cpu (0); - - /*NOTREACHED*/ - return (0); -} - -/* taken from blob */ -void icache_enable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* set i-cache */ - i |= 0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void icache_disable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* clear i-cache */ - i &= ~0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush i-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -} - -int icache_status (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* return bit */ - return (i & 0x1000); -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} - -void set_GPIO_mode(int gpio_mode) -{ - int gpio = gpio_mode & GPIO_MD_MASK_NR; - int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; - int gafr; - - if (gpio_mode & GPIO_MD_MASK_DIR) - { - GPDR(gpio) |= GPIO_bit(gpio); - } - else - { - GPDR(gpio) &= ~GPIO_bit(gpio); - } - gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); - GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); -} diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c deleted file mode 100644 index b6155b1..0000000 --- a/cpu/pxa/i2c.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2003 Pengutronix e.K. - * Robert Schwebel - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Back ported to the 8xx platform (from the 8260 platform) by - * Murray.Jensen@cmst.csiro.au, 27-Jan-01. - */ - -/* FIXME: this file is PXA255 specific! What about other XScales? */ - -#include - -#ifdef CONFIG_HARD_I2C - -/* - * - CFG_I2C_SPEED - * - I2C_PXA_SLAVE_ADDR - */ - -#include -#include -#include - -/*#define DEBUG_I2C 1 /###* activate local debugging output */ -#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ -#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) -#define I2C_ISR_INIT 0x7FF - -#ifdef DEBUG_I2C -#define PRINTD(x) printf x -#else -#define PRINTD(x) -#endif - - -/* Shall the current transfer have a start/stop condition? */ -#define I2C_COND_NORMAL 0 -#define I2C_COND_START 1 -#define I2C_COND_STOP 2 - -/* Shall the current transfer be ack/nacked or being waited for it? */ -#define I2C_ACKNAK_WAITACK 1 -#define I2C_ACKNAK_SENDACK 2 -#define I2C_ACKNAK_SENDNAK 4 - -/* Specify who shall transfer the data (master or slave) */ -#define I2C_READ 0 -#define I2C_WRITE 1 - -/* All transfers are described by this data structure */ -struct i2c_msg { - u8 condition; - u8 acknack; - u8 direction; - u8 data; -}; - - -/** - * i2c_pxa_reset: - reset the host controller - * - */ - -static void i2c_reset( void ) -{ - ICR &= ~ICR_IUE; /* disable unit */ - ICR |= ICR_UR; /* reset the unit */ - udelay(100); - ICR &= ~ICR_IUE; /* disable unit */ - CKEN |= CKEN14_I2C; /* set the global I2C clock on */ - ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */ - ICR = I2C_ICR_INIT; /* set control register values */ - ISR = I2C_ISR_INIT; /* set clear interrupt bits */ - ICR |= ICR_IUE; /* enable unit */ - udelay(100); -} - - -/** - * i2c_isr_set_cleared: - wait until certain bits of the I2C status register - * are set and cleared - * - * @return: 0 in case of success, 1 means timeout (no match within 10 ms). - */ - -static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask ) -{ - int timeout = 10000; - - while( ((ISR & set_mask)!=set_mask) || ((ISR & cleared_mask)!=0) ){ - udelay( 10 ); - if( timeout-- < 0 ) return 0; - } - - return 1; -} - - -/** - * i2c_transfer: - Transfer one byte over the i2c bus - * - * This function can tranfer a byte over the i2c bus in both directions. - * It is used by the public API functions. - * - * @return: 0: transfer successful - * -1: message is empty - * -2: transmit timeout - * -3: ACK missing - * -4: receive timeout - * -5: illegal parameters - * -6: bus is busy and couldn't be aquired - */ -int i2c_transfer(struct i2c_msg *msg) -{ - int ret; - - if (!msg) - goto transfer_error_msg_empty; - - switch(msg->direction) { - - case I2C_WRITE: - - /* check if bus is not busy */ - if (!i2c_isr_set_cleared(0,ISR_IBB)) - goto transfer_error_bus_busy; - - /* start transmission */ - ICR &= ~ICR_START; - ICR &= ~ICR_STOP; - IDBR = msg->data; - if (msg->condition == I2C_COND_START) ICR |= ICR_START; - if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; - if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; - if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; - ICR &= ~ICR_ALDIE; - ICR |= ICR_TB; - - /* transmit register empty? */ - if (!i2c_isr_set_cleared(ISR_ITE,0)) - goto transfer_error_transmit_timeout; - - /* clear 'transmit empty' state */ - ISR |= ISR_ITE; - - /* wait for ACK from slave */ - if (msg->acknack == I2C_ACKNAK_WAITACK) - if (!i2c_isr_set_cleared(0,ISR_ACKNAK)) - goto transfer_error_ack_missing; - break; - - case I2C_READ: - - /* check if bus is not busy */ - if (!i2c_isr_set_cleared(0,ISR_IBB)) - goto transfer_error_bus_busy; - - /* start receive */ - ICR &= ~ICR_START; - ICR &= ~ICR_STOP; - if (msg->condition == I2C_COND_START) ICR |= ICR_START; - if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; - if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; - if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; - ICR &= ~ICR_ALDIE; - ICR |= ICR_TB; - - /* receive register full? */ - if (!i2c_isr_set_cleared(ISR_IRF,0)) - goto transfer_error_receive_timeout; - - msg->data = IDBR; - - /* clear 'receive empty' state */ - ISR |= ISR_IRF; - - break; - - default: - - goto transfer_error_illegal_param; - - } - - return 0; - -transfer_error_msg_empty: - PRINTD(("i2c_transfer: error: 'msg' is empty\n")); - ret = -1; goto i2c_transfer_finish; - -transfer_error_transmit_timeout: - PRINTD(("i2c_transfer: error: transmit timeout\n")); - ret = -2; goto i2c_transfer_finish; - -transfer_error_ack_missing: - PRINTD(("i2c_transfer: error: ACK missing\n")); - ret = -3; goto i2c_transfer_finish; - -transfer_error_receive_timeout: - PRINTD(("i2c_transfer: error: receive timeout\n")); - ret = -4; goto i2c_transfer_finish; - -transfer_error_illegal_param: - PRINTD(("i2c_transfer: error: illegal parameters\n")); - ret = -5; goto i2c_transfer_finish; - -transfer_error_bus_busy: - PRINTD(("i2c_transfer: error: bus is busy\n")); - ret = -6; goto i2c_transfer_finish; - -i2c_transfer_finish: - PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR)); - i2c_reset(); - return ret; - -} - -/* ------------------------------------------------------------------------ */ -/* API Functions */ -/* ------------------------------------------------------------------------ */ - -void i2c_init(int speed, int slaveaddr) -{ -#ifdef CFG_I2C_INIT_BOARD - /* call board specific i2c bus reset routine before accessing the */ - /* environment, which might be in a chip on that bus. For details */ - /* about this problem see doc/I2C_Edge_Conditions. */ - i2c_init_board(); -#endif -} - - -/** - * i2c_probe: - Test if a chip answers for a given i2c address - * - * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise - */ - -int i2c_probe(uchar chip) -{ - struct i2c_msg msg; - - i2c_reset(); - - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1) + 1; - if (i2c_transfer(&msg)) return -1; - - msg.condition = I2C_COND_STOP; - msg.acknack = I2C_ACKNAK_SENDNAK; - msg.direction = I2C_READ; - msg.data = 0x00; - if (i2c_transfer(&msg)) return -1; - - return 0; -} - - -/** - * i2c_read: - Read multiple bytes from an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be read - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to write the data - * @len: how much byte do we want to read - * @return: 0 in case of success - */ - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - struct i2c_msg msg; - u8 addr_bytes[3]; /* lowest...highest byte of data address */ - int ret; - - PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); - - i2c_reset(); - - /* dummy chip address write */ - PRINTD(("i2c_read: dummy chip address write\n")); - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1); - msg.data &= 0xFE; - if ((ret=i2c_transfer(&msg))) return -1; - - /* - * send memory address bytes; - * alen defines how much bytes we have to send. - */ - /*addr &= ((1 << CFG_EEPROM_PAGE_WRITE_BITS)-1); */ - addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); - addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); - addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); - - while (--alen >= 0) { - - PRINTD(("i2c_read: send memory word address byte %1d\n",alen)); - msg.condition = I2C_COND_NORMAL; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = addr_bytes[alen]; - if ((ret=i2c_transfer(&msg))) return -1; - } - - - /* start read sequence */ - PRINTD(("i2c_read: start read sequence\n")); - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1); - msg.data |= 0x01; - if ((ret=i2c_transfer(&msg))) return -1; - - /* read bytes; send NACK at last byte */ - while (len--) { - - if (len==0) { - msg.condition = I2C_COND_STOP; - msg.acknack = I2C_ACKNAK_SENDNAK; - } else { - msg.condition = I2C_COND_NORMAL; - msg.acknack = I2C_ACKNAK_SENDACK; - } - - msg.direction = I2C_READ; - msg.data = 0x00; - if ((ret=i2c_transfer(&msg))) return -1; - - *(buffer++) = msg.data; - - PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); - - } - - i2c_reset(); - - return 0; -} - - -/** - * i2c_write: - Write multiple bytes to an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be written - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to find the data to be written - * @len: how much byte do we want to read - * @return: 0 in case of success - */ - -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - struct i2c_msg msg; - u8 addr_bytes[3]; /* lowest...highest byte of data address */ - - PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); - - i2c_reset(); - - /* chip address write */ - PRINTD(("i2c_write: chip address write\n")); - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1); - msg.data &= 0xFE; - if (i2c_transfer(&msg)) return -1; - - /* - * send memory address bytes; - * alen defines how much bytes we have to send. - */ - addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); - addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); - addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); - - while (--alen >= 0) { - - PRINTD(("i2c_write: send memory word address\n")); - msg.condition = I2C_COND_NORMAL; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = addr_bytes[alen]; - if (i2c_transfer(&msg)) return -1; - } - - /* write bytes; send NACK at last byte */ - while (len--) { - - PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); - - if (len==0) - msg.condition = I2C_COND_STOP; - else - msg.condition = I2C_COND_NORMAL; - - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = *(buffer++); - - if (i2c_transfer(&msg)) return -1; - - } - - i2c_reset(); - - return 0; - -} - -uchar i2c_reg_read (uchar chip, uchar reg) -{ - char buf; - - PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg)); - i2c_read(chip, reg, 1, &buf, 1); - return (buf); -} - -void i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - PRINTD(("i2c_reg_write(chip=0x%02x, reg=0x%02x, val=0x%02x)\n",chip,reg,val)); - i2c_write(chip, reg, 1, &val, 1); -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c deleted file mode 100644 index 0479a10..0000000 --- a/cpu/pxa/interrupts.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifdef CONFIG_USE_IRQ -/* enable IRQ/FIQ interrupts */ -void enable_interrupts (void) -{ -#error: interrupts not implemented yet -} - - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ -#error: interrupts not implemented yet -} -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32" - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - - -int interrupt_init (void) -{ - /* nothing happens here - we don't setup any IRQs */ - return (0); -} - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - /* nop */ -} - -void udelay (unsigned long usec) -{ - udelay_masked (usec); -} - - -void reset_timer_masked (void) -{ - OSCR = 0; -} - -ulong get_timer_masked (void) -{ - return OSCR; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CFG_HZ; - tmo /= 1000; - } else { - tmo = usec * CFG_HZ; - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - tbclk = CFG_HZ; - return tbclk; -} diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c deleted file mode 100644 index f7020ee..0000000 --- a/cpu/pxa/mmc.c +++ /dev/null @@ -1,489 +0,0 @@ -/* - * (C) Copyright 2003 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_MMC - -extern int -fat_register_device(block_dev_desc_t *dev_desc, int part_no); - -static block_dev_desc_t mmc_dev; - -block_dev_desc_t * mmc_get_dev(int dev) -{ - return ((block_dev_desc_t *)&mmc_dev); -} - -/* - * FIXME needs to read cid and csd info to determine block size - * and other parameters - */ -static uchar mmc_buf[MMC_BLOCK_SIZE]; -static mmc_csd_t mmc_csd; -static int mmc_ready = 0; - - -static uchar * -/****************************************************/ -mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat) -/****************************************************/ -{ - static uchar resp[20]; - ulong status; - int words, i; - - debug("mmc_cmd %x %x %x %x\n", cmd, argh, argl, cmdat); - MMC_STRPCL = MMC_STRPCL_STOP_CLK; - MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF; - while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)); - MMC_CMD = cmd; - MMC_ARGH = argh; - MMC_ARGL = argl; - MMC_CMDAT = cmdat; - MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES; - MMC_STRPCL = MMC_STRPCL_START_CLK; - while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)); - - status = MMC_STAT; - debug("MMC status %x\n", status); - if (status & MMC_STAT_TIME_OUT_RESPONSE) { - return 0; - } - - switch (cmdat & 0x3) { - case MMC_CMDAT_R1: - case MMC_CMDAT_R3: - words = 3; - break; - - case MMC_CMDAT_R2: - words = 8; - break; - - default: - return 0; - } - for (i = words-1; i >= 0; i--) { - ulong res_fifo = MMC_RES; - int offset = i << 1; - - resp[offset] = ((uchar *)&res_fifo)[0]; - resp[offset+1] = ((uchar *)&res_fifo)[1]; - } -#ifdef MMC_DEBUG - for (i=0; i> 16; - argl = len & 0xffff; - - /* set block len */ - resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); - - /* send read command */ - argh = src >> 16; - argl = src & 0xffff; - MMC_STRPCL = MMC_STRPCL_STOP_CLK; - MMC_RDTO = 0xffff; - MMC_NOB = 1; - MMC_BLKLEN = len; - resp = mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl, - MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN); - - - MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ; - while (len) { - if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) { -#ifdef CONFIG_PXA27X - int i; - for (i=min(len,32); i; i--) { - *dst++ = * ((volatile uchar *) &MMC_RXFIFO); - len--; - } -#else - *dst++ = MMC_RXFIFO; - len--; -#endif - } - status = MMC_STAT; - if (status & MMC_STAT_ERRORS) { - printf("MMC_STAT error %lx\n", status); - return -1; - } - } - MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE; - while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)); - status = MMC_STAT; - if (status & MMC_STAT_ERRORS) { - printf("MMC_STAT error %lx\n", status); - return -1; - } - return 0; -} - -int -/****************************************************/ -mmc_block_write(ulong dst, uchar *src, int len) -/****************************************************/ -{ - uchar *resp; - ushort argh, argl; - ulong status; - - if (len == 0) { - return 0; - } - - debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong)src, len); - - argh = len >> 16; - argl = len & 0xffff; - - /* set block len */ - resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); - - /* send write command */ - argh = dst >> 16; - argl = dst & 0xffff; - MMC_STRPCL = MMC_STRPCL_STOP_CLK; - MMC_NOB = 1; - MMC_BLKLEN = len; - resp = mmc_cmd(MMC_CMD_WRITE_BLOCK, argh, argl, - MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN); - - MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ; - while (len) { - if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) { - int i, bytes = min(32,len); - - for (i=0; iid[0], cid->id[1], cid->id[2]); - printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev); - cid->hwrev = cid->fwrev = 0; /* null terminate string */ - printf("Product Name = %s\n",cid->name); - printf("Serial Number = %02x%02x%02x\n", - cid->sn[0], cid->sn[1], cid->sn[2]); - printf("Month = %d\n",cid->month); - printf("Year = %d\n",1997 + cid->year); - } - /* fill in device description */ - mmc_dev.if_type = IF_TYPE_MMC; - mmc_dev.part_type = PART_TYPE_DOS; - mmc_dev.dev = 0; - mmc_dev.lun = 0; - mmc_dev.type = 0; - /* FIXME fill in the correct size (is set to 32MByte) */ - mmc_dev.blksz = 512; - mmc_dev.lba = 0x10000; - sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", - cid->id[0], cid->id[1], cid->id[2], - cid->sn[0], cid->sn[1], cid->sn[2]); - sprintf(mmc_dev.product,"%s",cid->name); - sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); - mmc_dev.removable = 0; - mmc_dev.block_read = mmc_bread; - - /* MMC exists, get CSD too */ - resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1); - resp = mmc_cmd(MMC_CMD_SEND_CSD, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R2); - if (resp) { - mmc_csd_t *csd = (mmc_csd_t *)resp; - memcpy(&mmc_csd, csd, sizeof(csd)); - rc = 0; - mmc_ready = 1; - /* FIXME add verbose printout for csd */ - } - } - -#ifdef CONFIG_PXA27X - MMC_CLKRT = 1; /* 10 MHz - see Intel errata */ -#else - MMC_CLKRT = 0; /* 20 MHz */ -#endif - resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1); - - fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ - - return rc; -} - -int -mmc_ident(block_dev_desc_t *dev) -{ - return 0; -} - -int -mmc2info(ulong addr) -{ - /* FIXME hard codes to 32 MB device */ - if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) { - return 1; - } - return 0; -} - -#endif /* CONFIG_MMC */ diff --git a/cpu/pxa/pxafb.c b/cpu/pxa/pxafb.c deleted file mode 100644 index b2caa73..0000000 --- a/cpu/pxa/pxafb.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * PXA LCD Controller - * - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering -- wd@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* #define DEBUG */ - -#ifdef CONFIG_LCD - -/*----------------------------------------------------------------------*/ -/* - * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for - * your display. - */ - -#ifdef CONFIG_PXA_VGA -/* LCD outputs connected to a video DAC */ -# define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x003008f8 -# define REG_LCCR3 0x0300FF01 - -/* 640x480x16 @ 61 Hz */ -vidinfo_t panel_info = { - vl_col: 640, - vl_row: 480, - vl_width: 640, - vl_height: 480, - vl_clkp: CFG_HIGH, - vl_oep: CFG_HIGH, - vl_hsp: CFG_HIGH, - vl_vsp: CFG_HIGH, - vl_dp: CFG_HIGH, - vl_bpix: LCD_BPP, - vl_lbw: 0, - vl_splt: 0, - vl_clor: 0, - vl_tft: 1, - vl_hpw: 40, - vl_blw: 56, - vl_elw: 56, - vl_vpw: 20, - vl_bfw: 8, - vl_efw: 8, -}; -#endif /* CONFIG_PXA_VIDEO */ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_SHARP_LM8V31 - -# define LCD_BPP LCD_COLOR8 -# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */ - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x0030087C -# define REG_LCCR3 0x0340FF08 - -vidinfo_t panel_info = { - vl_col: 640, - vl_row: 480, - vl_width: 157, - vl_height: 118, - vl_clkp: CFG_HIGH, - vl_oep: CFG_HIGH, - vl_hsp: CFG_HIGH, - vl_vsp: CFG_HIGH, - vl_dp: CFG_HIGH, - vl_bpix: LCD_BPP, - vl_lbw: 0, - vl_splt: 1, - vl_clor: 1, - vl_tft: 0, - vl_hpw: 1, - vl_blw: 3, - vl_elw: 3, - vl_vpw: 1, - vl_bfw: 0, - vl_efw: 0, -}; -#endif /* CONFIG_SHARP_LM8V31 */ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_HITACHI_SX14 -/* Hitachi SX14Q004-ZZA color STN LCD */ -#define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -#define REG_LCCR0 0x00301079 -#define REG_LCCR3 0x0340FF20 - -vidinfo_t panel_info = { - vl_col: 320, - vl_row: 240, - vl_width: 167, - vl_height: 109, - vl_clkp: CFG_HIGH, - vl_oep: CFG_HIGH, - vl_hsp: CFG_HIGH, - vl_vsp: CFG_HIGH, - vl_dp: CFG_HIGH, - vl_bpix: LCD_BPP, - vl_lbw: 1, - vl_splt: 0, - vl_clor: 1, - vl_tft: 0, - vl_hpw: 1, - vl_blw: 1, - vl_elw: 1, - vl_vpw: 7, - vl_bfw: 0, - vl_efw: 0, -}; -#endif /* CONFIG_HITACHI_SX14 */ - -/*----------------------------------------------------------------------*/ - -#if LCD_BPP == LCD_COLOR8 -void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue); -#endif -#if LCD_BPP == LCD_MONOCHROME -void lcd_initcolregs (void); -#endif - -#ifdef NOT_USED_SO_FAR -void lcd_disable (void); -void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue); -#endif /* NOT_USED_SO_FAR */ - -void lcd_ctrl_init (void *lcdbase); -void lcd_enable (void); - -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; - -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - -static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid); -static void pxafb_setup_gpio (vidinfo_t *vid); -static void pxafb_enable_controller (vidinfo_t *vid); -static int pxafb_init (vidinfo_t *vid); -/************************************************************************/ - -/************************************************************************/ -/* --------------- PXA chipset specific functions ------------------- */ -/************************************************************************/ - -void lcd_ctrl_init (void *lcdbase) -{ - pxafb_init_mem(lcdbase, &panel_info); - pxafb_init(&panel_info); - pxafb_setup_gpio(&panel_info); - pxafb_enable_controller(&panel_info); -} - -/*----------------------------------------------------------------------*/ -#ifdef NOT_USED_SO_FAR -void -lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue) -{ -} -#endif /* NOT_USED_SO_FAR */ - -/*----------------------------------------------------------------------*/ -#if LCD_BPP == LCD_COLOR8 -void -lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) -{ - struct pxafb_info *fbi = &panel_info.pxa; - unsigned short *palette = (unsigned short *)fbi->palette; - u_int val; - - if (regno < fbi->palette_size) { - val = ((red << 8) & 0xf800); - val |= ((green << 4) & 0x07e0); - val |= (blue & 0x001f); - -#ifdef LCD_INVERT_COLORS - palette[regno] = ~val; -#else - palette[regno] = val; -#endif - } - - debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n", - regno, &palette[regno], - red, green, blue, - palette[regno]); -} -#endif /* LCD_COLOR8 */ - -/*----------------------------------------------------------------------*/ -#if LCD_BPP == LCD_MONOCHROME -void lcd_initcolregs (void) -{ - struct pxafb_info *fbi = &panel_info.pxa; - cmap = (ushort *)fbi->palette; - ushort regno; - - for (regno = 0; regno < 16; regno++) { - cmap[regno * 2] = 0; - cmap[(regno * 2) + 1] = regno & 0x0f; - } -} -#endif /* LCD_MONOCHROME */ - -/*----------------------------------------------------------------------*/ -void lcd_enable (void) -{ -} - -/*----------------------------------------------------------------------*/ -#ifdef NOT_USED_SO_FAR -static void lcd_disable (void) -{ -} -#endif /* NOT_USED_SO_FAR */ - -/*----------------------------------------------------------------------*/ - -/************************************************************************/ -/* ** PXA255 specific routines */ -/************************************************************************/ - -/* - * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb, - * descriptors and palette areas. - */ -ulong calc_fbsize (void) -{ - ulong size; - int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; - - size = line_length * panel_info.vl_row; - size += PAGE_SIZE; - - return size; -} - -static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid) -{ - u_long palette_mem_size; - struct pxafb_info *fbi = &vid->pxa; - int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; - - fbi->screen = (u_long)lcdbase; - - fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16; - palette_mem_size = fbi->palette_size * sizeof(u16); - - debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); - /* locate palette and descs at end of page following fb */ - fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; - - return 0; -} - -static void pxafb_setup_gpio (vidinfo_t *vid) -{ - u_long lccr0; - - /* - * setup is based on type of panel supported - */ - - lccr0 = vid->pxa.reg_lccr0; - - /* 4 bit interface */ - if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD)) - { - debug("Setting GPIO for 4 bit data\n"); - /* bits 58-61 */ - GPDR1 |= (0xf << 26); - GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20); - - /* bits 74-77 */ - GPDR2 |= (0xf << 10); - GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20); - } - - /* 8 bit interface */ - else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) || - (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS))) - { - debug("Setting GPIO for 8 bit data\n"); - /* bits 58-65 */ - GPDR1 |= (0x3f << 26); - GPDR2 |= (0x3); - - GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20); - GAFR2_L = (GAFR2_L & ~0xf) | (0xa); - - /* bits 74-77 */ - GPDR2 |= (0xf << 10); - GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20); - } - - /* 16 bit interface */ - else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS))) - { - debug("Setting GPIO for 16 bit data\n"); - /* bits 58-77 */ - GPDR1 |= (0x3f << 26); - GPDR2 |= 0x00003fff; - - GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20); - GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa; - } - else - { - printf("pxafb_setup_gpio: unable to determine bits per pixel\n"); - } -} - -static void pxafb_enable_controller (vidinfo_t *vid) -{ - debug("Enabling LCD controller\n"); - - /* Sequence from 11.7.10 */ - LCCR3 = vid->pxa.reg_lccr3; - LCCR2 = vid->pxa.reg_lccr2; - LCCR1 = vid->pxa.reg_lccr1; - LCCR0 = vid->pxa.reg_lccr0 & ~LCCR0_ENB; - FDADR0 = vid->pxa.fdadr0; - FDADR1 = vid->pxa.fdadr1; - LCCR0 |= LCCR0_ENB; - - CKEN |= CKEN16_LCD; - - debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0); - debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1); - debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0); - debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1); - debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2); - debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3); -} - -static int pxafb_init (vidinfo_t *vid) -{ - struct pxafb_info *fbi = &vid->pxa; - - debug("Configuring PXA LCD\n"); - - fbi->reg_lccr0 = REG_LCCR0; - fbi->reg_lccr3 = REG_LCCR3; - - debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n", - vid->vl_col, vid->vl_hpw, - vid->vl_blw, vid->vl_elw); - debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n", - vid->vl_row, vid->vl_vpw, - vid->vl_bfw, vid->vl_efw); - - fbi->reg_lccr1 = - LCCR1_DisWdth(vid->vl_col) + - LCCR1_HorSnchWdth(vid->vl_hpw) + - LCCR1_BegLnDel(vid->vl_blw) + - LCCR1_EndLnDel(vid->vl_elw); - - fbi->reg_lccr2 = - LCCR2_DisHght(vid->vl_row) + - LCCR2_VrtSnchWdth(vid->vl_vpw) + - LCCR2_BegFrmDel(vid->vl_bfw) + - LCCR2_EndFrmDel(vid->vl_efw); - - fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP); - fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH) - | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH); - - - /* setup dma descriptors */ - fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); - fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); - fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); - - #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \ - (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \ - (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)) - - /* populate descriptors */ - fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow; - fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL; - fbi->dmadesc_fblow->fidr = 0; - fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL; - - fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */ - - fbi->dmadesc_fbhigh->fsadr = fbi->screen; - fbi->dmadesc_fbhigh->fidr = 0; - fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL; - - fbi->dmadesc_palette->fsadr = fbi->palette; - fbi->dmadesc_palette->fidr = 0; - fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL; - - if( NBITS(vid->vl_bpix) < 12) - { - /* assume any mode with <12 bpp is palette driven */ - fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh; - fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette; - /* flips back and forth between pal and fbhigh */ - fbi->fdadr0 = (u_long)fbi->dmadesc_palette; - } - else - { - /* palette shouldn't be loaded in true-color mode */ - fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh; - fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */ - } - - debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow); - debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh); - debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette); - - debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr); - debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr); - debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr); - - debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr); - debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr); - debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr); - - debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd); - debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd); - debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd); - - return 0; -} - -/************************************************************************/ -/************************************************************************/ - -#endif /* CONFIG_LCD */ diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c deleted file mode 100644 index cedebfe..0000000 --- a/cpu/pxa/serial.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include -#include - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned int quot = 0; - - if (gd->baudrate == 1200) - quot = 768; - else if (gd->baudrate == 9600) - quot = 96; - else if (gd->baudrate == 19200) - quot = 48; - else if (gd->baudrate == 38400) - quot = 24; - else if (gd->baudrate == 57600) - quot = 16; - else if (gd->baudrate == 115200) - quot = 8; - else - hang (); - -#ifdef CONFIG_FFUART - CKEN |= CKEN6_FFUART; - - FFIER = 0; /* Disable for now */ - FFFCR = 0; /* No fifos enabled */ - - /* set baud rate */ - FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - FFDLL = quot & 0xff; - FFDLH = quot >> 8; - FFLCR = LCR_WLS0 | LCR_WLS1; - - FFIER = IER_UUE; /* Enable FFUART */ - -#elif defined(CONFIG_BTUART) - CKEN |= CKEN7_BTUART; - - BTIER = 0; - BTFCR = 0; - - /* set baud rate */ - BTLCR = LCR_DLAB; - BTDLL = quot & 0xff; - BTDLH = quot >> 8; - BTLCR = LCR_WLS0 | LCR_WLS1; - - BTIER = IER_UUE; /* Enable BFUART */ - -#elif defined(CONFIG_STUART) - CKEN |= CKEN5_STUART; - - STIER = 0; - STFCR = 0; - - /* set baud rate */ - STLCR = LCR_DLAB; - STDLL = quot & 0xff; - STDLH = quot >> 8; - STLCR = LCR_WLS0 | LCR_WLS1; - - STIER = IER_UUE; /* Enable STUART */ - -#else -#error "Bad: you didn't configure serial ..." -#endif -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ -#ifdef CONFIG_FFUART - /* wait for room in the tx FIFO on FFUART */ - while ((FFLSR & LSR_TEMT) == 0) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - FFTHR = c; -#elif defined(CONFIG_BTUART) - while ((BTLSR & LSR_TEMT ) == 0 ) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - BTTHR = c; -#elif defined(CONFIG_STUART) - while ((STLSR & LSR_TEMT ) == 0 ) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - STTHR = c; -#endif - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_tstc (void) -{ -#ifdef CONFIG_FFUART - return FFLSR & LSR_DR; -#elif defined(CONFIG_BTUART) - return BTLSR & LSR_DR; -#elif defined(CONFIG_STUART) - return STLSR & LSR_DR; -#endif -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ -#ifdef CONFIG_FFUART - while (!(FFLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) FFRBR & 0xff; -#elif defined(CONFIG_BTUART) - while (!(BTLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) BTRBR & 0xff; -#elif defined(CONFIG_STUART) - while (!(STLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) STRBR & 0xff; -#endif -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S deleted file mode 100644 index a8cc080..0000000 --- a/cpu/pxa/start.S +++ /dev/null @@ -1,453 +0,0 @@ -/* - * armboot - Startup Code for XScale - * - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000 Wolfgang Denk - * Copyright (C) 2001 Alex Zuepke - * Copyright (C) 2002 Kyle Harris - * Copyright (C) 2003 Robert Schwebel - * Copyright (C) 2003 Kai-Uwe Bloem - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - * Startup Code (reset vector) - * - * do important init only if we don't start from RAM! - * - relocate armboot to ram - * - setup stack - * - jump to second stage - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - - -/****************************************************************************/ -/* */ -/* the actual reset code */ -/* */ -/****************************************************************************/ - -reset: - mrs r0,cpsr /* set the cpu to SVC32 mode */ - bic r0,r0,#0x1f /* (superviser mode, M=10011) */ - orr r0,r0,#0x13 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit /* we do sys-critical inits */ -#endif - -#ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - - -/****************************************************************************/ -/* */ -/* CPU_init_critical registers */ -/* */ -/* - setup important registers */ -/* - setup memory timing */ -/* */ -/****************************************************************************/ - -/* Interrupt-Controller base address */ -IC_BASE: .word 0x40d00000 -#define ICMR 0x04 - -/* Reset-Controller */ -RST_BASE: .word 0x40f00030 -#define RCSR 0x00 - -/* Operating System Timer */ -OSTIMER_BASE: .word 0x40a00000 -#define OSMR3 0x0C -#define OSCR 0x10 -#define OWER 0x18 -#define OIER 0x1C - -/* Clock Manager Registers */ -#ifdef CFG_CPUSPEED -CC_BASE: .word 0x41300000 -#define CCCR 0x00 -cpuspeed: .word CFG_CPUSPEED -#else -#error "You have to define CFG_CPUSPEED!!" -#endif - - - /* RS: ??? */ - .macro CPWAIT - mrc p15,0,r0,c2,c0,0 - mov r0,r0 - sub pc,pc,#4 - .endm - - -cpu_init_crit: - - /* mask all IRQs */ - ldr r0, IC_BASE - mov r1, #0x00 - str r1, [r0, #ICMR] - -#if defined(CFG_CPUSPEED) - - /* set clock speed */ - ldr r0, CC_BASE - ldr r1, cpuspeed - str r1, [r0, #CCCR] - mov r0, #2 - mcr p14, 0, r0, c6, c0, 0 - -setspeed_done: -#endif - - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - mov ip, lr - bl lowlevel_init - mov lr, ip - - /* Memory interfaces are working. Disable MMU and enable I-cache. */ - - ldr r0, =0x2001 /* enable access to all coproc. */ - mcr p15, 0, r0, c15, c1, 0 - CPWAIT - - mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */ - CPWAIT - - mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */ - CPWAIT - - mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */ - CPWAIT - - /* Enable the Icache */ -/* - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0x1800 - mcr p15, 0, r0, c1, c0, 0 - CPWAIT -*/ - mov pc, lr - - -/****************************************************************************/ -/* */ -/* Interrupt handling */ -/* */ -/****************************************************************************/ - -/* IRQ stack frame */ - -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 - - /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - - ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ - add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ - mov r0, sp - .endm - - - /* use irq_save_user_regs / irq_restore_user_regs for */ - /* IRQ/FIQ handling */ - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ /* Calling SP, LR */ - str lr, [r8, #0] /* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] /* Save CPSR */ - str r0, [r8, #8] /* Save OLD_R0 */ - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - - -/****************************************************************************/ -/* */ -/* exception handlers */ -/* */ -/****************************************************************************/ - - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - irq_save_user_regs /* someone ought to write a more */ - bl do_fiq /* effiction fiq_save_user_regs */ - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -/****************************************************************************/ -/* */ -/* Reset function: the PXA250 doesn't have a reset function, so we have to */ -/* perform a watchdog timeout for a soft reset. */ -/* */ -/****************************************************************************/ - - .align 5 -.globl reset_cpu - - /* FIXME: this code is PXA250 specific. How is this handled on */ - /* other XScale processors? */ - -reset_cpu: - - /* We set OWE:WME (watchdog enable) and wait until timeout happens */ - - ldr r0, OSTIMER_BASE - ldr r1, [r0, #OWER] - orr r1, r1, #0x0001 /* bit0: WME */ - str r1, [r0, #OWER] - - /* OS timer does only wrap every 1165 seconds, so we have to set */ - /* the match register as well. */ - - ldr r1, [r0, #OSCR] /* read OS timer */ - add r1, r1, #0x800 /* let OSMR3 match after */ - add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ - str r1, [r0, #OSMR3] - -reset_endless: - - b reset_endless diff --git a/cpu/s3c44b0/Makefile b/cpu/s3c44b0/Makefile deleted file mode 100644 index d43c73e..0000000 --- a/cpu/s3c44b0/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = serial.o interrupts.o cpu.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/s3c44b0/config.mk b/cpu/s3c44b0/config.mk deleted file mode 100644 index 6dc9c46..0000000 --- a/cpu/s3c44b0/config.mk +++ /dev/null @@ -1,35 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c deleted file mode 100644 index 5d50b3c..0000000 --- a/cpu/s3c44b0/cpu.c +++ /dev/null @@ -1,509 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * S3C44B0 CPU specific code - */ - -#include -#include -#include - -static void s3c44b0_flush_cache(void) -{ - volatile int i; - /* flush cycle */ - for(i=0x10002000;i<0x10004800;i+=16) - { - *((int *)i)=0x0; - } -} - - -int cpu_init (void) -{ - icache_enable(); - - return 0; -} - -int cleanup_before_linux (void) -{ - /* - cache memory should be enabled before calling - Linux to make the kernel uncompression faster - */ - icache_enable(); - - disable_interrupts (); - - return 0; -} - -void reset_cpu (ulong addr) -{ - /* - reset the cpu using watchdog - */ - - /* Disable the watchdog.*/ - WTCON&=~(1<<5); - - /* set the timeout value to a short time... */ - WTCNT = 0x1; - - /* Enable the watchdog. */ - WTCON|=1; - WTCON|=(1<<5); - - while(1) { - /*NOP*/ - } -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - - /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - s3c44b0_flush_cache(); - - /* - Init cache - Non-cacheable area (everything outside RAM) - 0x0000:0000 - 0x0C00:0000 - */ - NCACHBE0 = 0xC0000000; - NCACHBE1 = 0x00000000; - - /* - Enable chache - */ - reg = SYSCFG; - reg |= 0x00000006; /* 8kB */ - SYSCFG = reg; -} - -void icache_disable (void) -{ - ulong reg; - - reg = SYSCFG; - reg &= ~0x00000006; /* 8kB */ - SYSCFG = reg; -} - -int icache_status (void) -{ - return 0; -} - -void dcache_enable (void) -{ - icache_enable(); -} - -void dcache_disable (void) -{ - icache_disable(); -} - -int dcache_status (void) -{ - return dcache_status(); -} - -/* - RTC stuff -*/ -#include -#ifndef BCD2HEX - #define BCD2HEX(n) ((n>>4)*10+(n&0x0f)) -#endif -#ifndef HEX2BCD - #define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10) -#endif - -void rtc_get (struct rtc_time* tm) -{ - RTCCON |= 1; - tm->tm_year = BCD2HEX(BCDYEAR); - tm->tm_mon = BCD2HEX(BCDMON); - tm->tm_wday = BCD2HEX(BCDDATE); - tm->tm_mday = BCD2HEX(BCDDAY); - tm->tm_hour = BCD2HEX(BCDHOUR); - tm->tm_min = BCD2HEX(BCDMIN); - tm->tm_sec = BCD2HEX(BCDSEC); - - if (tm->tm_sec==0) { - /* we have to re-read the rtc data because of the "one second deviation" problem */ - /* see RTC datasheet for more info about it */ - tm->tm_year = BCD2HEX(BCDYEAR); - tm->tm_mon = BCD2HEX(BCDMON); - tm->tm_mday = BCD2HEX(BCDDAY); - tm->tm_wday = BCD2HEX(BCDDATE); - tm->tm_hour = BCD2HEX(BCDHOUR); - tm->tm_min = BCD2HEX(BCDMIN); - tm->tm_sec = BCD2HEX(BCDSEC); - } - - RTCCON &= ~1; - - if(tm->tm_year >= 70) - tm->tm_year += 1900; - else - tm->tm_year += 2000; -} - -void rtc_set (struct rtc_time* tm) -{ - if(tm->tm_year < 2000) - tm->tm_year -= 1900; - else - tm->tm_year -= 2000; - - RTCCON |= 1; - BCDYEAR = HEX2BCD(tm->tm_year); - BCDMON = HEX2BCD(tm->tm_mon); - BCDDAY = HEX2BCD(tm->tm_mday); - BCDDATE = HEX2BCD(tm->tm_wday); - BCDHOUR = HEX2BCD(tm->tm_hour); - BCDMIN = HEX2BCD(tm->tm_min); - BCDSEC = HEX2BCD(tm->tm_sec); - RTCCON &= 1; -} - -void rtc_reset (void) -{ - RTCCON |= 1; - BCDYEAR = 0; - BCDMON = 0; - BCDDAY = 0; - BCDDATE = 0; - BCDHOUR = 0; - BCDMIN = 0; - BCDSEC = 0; - RTCCON &= 1; -} - - -/* - I2C stuff -*/ - -/* - * Initialization, must be called once on start up, may be called - * repeatedly to change the speed and slave addresses. - */ -void i2c_init(int speed, int slaveaddr) -{ - /* - setting up I2C support - */ - unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF; - - save_F = PCONF; - save_PF = PUPF; - - rPCONF = ((save_F & ~(0xF))| 0xa); - rPUPF = (save_PF | 0x3); - PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/ - PUPF = rPUPF; /* Disable pull-up */ - - /* Configuring pin for WC pin of EEprom */ - rPCONA = PCONA; - rPCONA &= ~(1<<9); - PCONA = rPCONA; - - rPDATA = PDATA; - rPDATA &= ~(1<<9); - PDATA = rPDATA; - - /* - Enable ACK, IICCLK=MCLK/16, enable interrupt - 75Mhz/16/(12+1) = 390625 Hz - */ - rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC); - IICCON = rIICCON; - - IICADD = slaveaddr; -} - -/* - * Probe the given I2C chip address. Returns 0 if a chip responded, - * not 0 on failure. - */ -int i2c_probe(uchar chip) -{ - /* - not implemented - */ - - printf("i2c_probe chip %d\n", (int) chip); - return -1; -} - -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ - -#define S3C44B0X_rIIC_INTPEND (1<<4) -#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0) -#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5) -#define S3C44B0_IIC_TIMEOUT 100 - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - - int k, j, temp; - u32 rIICSTAT; - - /* - send the device offset - */ - - rIICSTAT = 0xD0; - IICSTAT = rIICSTAT; - - IICDS = chip; /* this is a write operation... */ - - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - for(k=0; k -#include - -#include - -/* we always count down the max. */ -#define TIMER_LOAD_VAL 0xffff - -/* macro to read the 16 bit timer */ -#define READ_TIMER (TCNTO1 & 0xffff) - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ NOT supported -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = - { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26", - "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26", - "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", - "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32", - "UK14_32", "SYS_32" - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -static ulong timestamp; -static ulong lastdec; - -int interrupt_init (void) -{ - TCFG0 = 0x000000E9; - TCFG1 = 0x00000004; - TCON = 0x00000900; - TCNTB1 = TIMER_LOAD_VAL; - TCMPB1 = 0; - TCON = 0x00000B00; - TCON = 0x00000900; - - - lastdec = TCNTB1 = TIMER_LOAD_VAL; - timestamp = 0; - return 0; -} - -/* - * timer without interrupts - */ - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void set_timer (ulong t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= CFG_HZ; - tmo /= 8; - - tmo += get_timer (0); - - while (get_timer_masked () < tmo) - /*NOP*/; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; - timestamp = 0; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CFG_HZ; - tmo /= 8; - } else { - tmo = usec * CFG_HZ; - tmo /= (1000*8); - } - - endtime = get_timer(0) + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} diff --git a/cpu/s3c44b0/serial.c b/cpu/s3c44b0/serial.c deleted file mode 100644 index 70b4ee8..0000000 --- a/cpu/s3c44b0/serial.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -/* flush serial input queue. returns 0 on success or negative error - * number otherwise - */ -static int serial_flush_input(void) -{ - volatile u32 tmp; - - /* keep on reading as long as the receiver is not empty */ - while(UTRSTAT0&0x01) { - tmp = REGB(URXH0); - } - - return 0; -} - - -/* flush output queue. returns 0 on success or negative error number - * otherwise - */ -static int serial_flush_output(void) -{ - /* wait until the transmitter is no longer busy */ - while(!(UTRSTAT0 & 0x02)) { - } - - return 0; -} - - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - u32 divisor = 0; - - /* get correct divisor */ - switch(gd->baudrate) { - - case 1200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 3124; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 3905; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 9600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 390; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 487; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 19200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 194; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 243; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 38400: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 97; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 121; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 57600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 64; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 80; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 115200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 32; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 40; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - } - - serial_flush_output(); - serial_flush_input(); - UFCON0 = 0x0; - ULCON0 = 0x03; - UCON0 = 0x05; - UBRDIV0 = divisor; - - UFCON1 = 0x0; - ULCON1 = 0x03; - UCON1 = 0x05; - UBRDIV1 = divisor; - - for(divisor=0; divisor<100; divisor++) { - /* NOP */ - } -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ - /* wait for room in the transmit FIFO */ - while(!(UTRSTAT0 & 0x02)); - - UTXH0 = (unsigned char)c; - - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n') - serial_putc('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_tstc (void) -{ - return (UTRSTAT0 & 0x01); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ - int rv; - - for(;;) { - rv = serial_tstc(); - - if(rv > 0) - return URXH0; - } -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} diff --git a/cpu/s3c44b0/start.S b/cpu/s3c44b0/start.S deleted file mode 100644 index 7affe87..0000000 --- a/cpu/s3c44b0/start.S +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Startup Code for S3C44B0 CPU-core - * - * (C) Copyright 2004 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* - * Jump vector table - */ - - -.globl _start -_start: b reset - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - add pc, pc, #0x0c000000 - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * relocate u-boot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0x13 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - bl lowlevel_init -#endif - -#ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop - -/* - now copy to sram the interrupt vector -*/ - adr r0, real_vectors - add r2, r0, #1024 - ldr r1, =0x0c000000 - add r1, r1, #0x08 -vector_copy_loop: - ldmia r0!, {r3-r10} - stmia r1!, {r3-r10} - cmp r0, r2 - ble vector_copy_loop -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -#define INTCON (0x01c00000+0x200000) -#define INTMSK (0x01c00000+0x20000c) -#define LOCKTIME (0x01c00000+0x18000c) -#define PLLCON (0x01c00000+0x180000) -#define CLKCON (0x01c00000+0x180004) -#define WTCON (0x01c00000+0x130000) -cpu_init_crit: - /* disable watch dog */ - ldr r0, =WTCON - ldr r1, =0x0 - str r1, [r0] - - /* - * mask all IRQs by clearing all bits in the INTMRs - */ - ldr r1,=INTMSK - ldr r0, =0x03fffeff - str r0, [r1] - - ldr r1, =INTCON - ldr r0, =0x05 - str r0, [r1] - - /* Set Clock Control Register */ - ldr r1, =LOCKTIME - ldrb r0, =800 - strb r0, [r1] - - ldr r1, =PLLCON - -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */ -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */ -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - - str r0, [r1] - - ldr r1,=CLKCON - ldr r0, =0x7ff8 - str r0, [r1] - - mov pc, lr - - -/*************************************************/ -/* interrupt vectors */ -/*************************************************/ -real_vectors: - b reset - b undefined_instruction - b software_interrupt - b prefetch_abort - b data_abort - b not_used - b irq - b fiq - -/*************************************************/ - -undefined_instruction: - mov r6, #3 - b reset - -software_interrupt: - mov r6, #4 - b reset - -prefetch_abort: - mov r6, #5 - b reset - -data_abort: - mov r6, #6 - b reset - -not_used: - /* we *should* never reach this */ - mov r6, #7 - b reset - -irq: - mov r6, #8 - b reset - -fiq: - mov r6, #9 - b reset diff --git a/cpu/sa1100/Makefile b/cpu/sa1100/Makefile deleted file mode 100644 index 8c950da..0000000 --- a/cpu/sa1100/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(CPU).a - -START = start.o -OBJS = serial.o interrupts.o cpu.o - -all: .depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/cpu/sa1100/config.mk b/cpu/sa1100/config.mk deleted file mode 100644 index 5be7dfb..0000000 --- a/cpu/sa1100/config.mk +++ /dev/null @@ -1,35 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c deleted file mode 100644 index 17e5b0d..0000000 --- a/cpu/sa1100/cpu.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include - -int cpu_init (void) -{ - /* - * setup up stacks if necessary - */ -#ifdef CONFIG_USE_IRQ - DECLARE_GLOBAL_DATA_PTR; - - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; - FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; -#endif - return 0; -} - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * just disable everything that can disturb booting linux - */ - - unsigned long i; - - disable_interrupts (); - - /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf ("resetting ...\n"); - - udelay (50000); /* wait 50 ms */ - disable_interrupts (); - reset_cpu (0); - - /*NOTREACHED*/ - return (0); -} - -/* taken from blob */ -void icache_enable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* set i-cache */ - i |= 0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void icache_disable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* clear i-cache */ - i &= ~0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush i-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -} - -int icache_status (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* return bit */ - return (i & 0x1000); -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} diff --git a/cpu/sa1100/interrupts.c b/cpu/sa1100/interrupts.c deleted file mode 100644 index b393e0d..0000000 --- a/cpu/sa1100/interrupts.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include - -#ifdef CONFIG_USE_IRQ -/* enable IRQ/FIQ interrupts */ -void enable_interrupts (void) -{ - unsigned long temp; - __asm__ __volatile__ ("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); -} - - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ - unsigned long old, temp; - __asm__ __volatile__ ("mrs %0, cpsr\n" - "orr %1, %0, #0x80\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); - - return (old & 0x80) == 0; -} -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32" - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - - -int interrupt_init (void) -{ - /* nothing happens here - we don't setup any IRQs */ - return (0); -} - -void reset_timer (void) -{ - reset_timer_masked (); -} - -ulong get_timer (ulong base) -{ - return get_timer_masked (); -} - -void set_timer (ulong t) -{ - /* nop */ -} - -void udelay (unsigned long usec) -{ - udelay_masked (usec); -} - - -void reset_timer_masked (void) -{ - OSCR = 0; -} - -ulong get_timer_masked (void) -{ - return OSCR; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CFG_HZ; - tmo /= 1000; - } else { - tmo = usec * CFG_HZ; - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = CFG_HZ; - return tbclk; -} diff --git a/cpu/sa1100/serial.c b/cpu/sa1100/serial.c deleted file mode 100644 index a598489..0000000 --- a/cpu/sa1100/serial.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -void serial_setbrg (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - unsigned int reg = 0; - - if (gd->baudrate == 1200) - reg = 191; - else if (gd->baudrate == 9600) - reg = 23; - else if (gd->baudrate == 19200) - reg = 11; - else if (gd->baudrate == 38400) - reg = 5; - else if (gd->baudrate == 57600) - reg = 3; - else if (gd->baudrate == 115200) - reg = 1; - else - hang (); - -#ifdef CONFIG_SERIAL1 - /* SA1110 uart function */ - Ser1SDCR0 |= SDCR0_SUS; - - /* Wait until port is ready ... */ - while(Ser1UTSR1 & UTSR1_TBY) {} - - /* init serial serial 1 */ - Ser1UTCR3 = 0x00; - Ser1UTSR0 = 0xff; - Ser1UTCR0 = ( UTCR0_1StpBit | UTCR0_8BitData ); - Ser1UTCR1 = 0; - Ser1UTCR2 = (u32)reg; - Ser1UTCR3 = ( UTCR3_RXE | UTCR3_TXE ); -#elif defined(CONFIG_SERIAL3) - /* Wait until port is ready ... */ - while (Ser3UTSR1 & UTSR1_TBY) { - } - - /* init serial serial 3 */ - Ser3UTCR3 = 0x00; - Ser3UTSR0 = 0xff; - Ser3UTCR0 = (UTCR0_1StpBit | UTCR0_8BitData); - Ser3UTCR1 = 0; - Ser3UTCR2 = (u32) reg; - Ser3UTCR3 = (UTCR3_RXE | UTCR3_TXE); -#else -#error "Bad: you didn't configured serial ..." -#endif -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -void serial_putc (const char c) -{ -#ifdef CONFIG_SERIAL1 - /* wait for room in the tx FIFO on SERIAL1 */ - while ((Ser1UTSR0 & UTSR0_TFS) == 0); - - Ser1UTDR = c; -#elif defined(CONFIG_SERIAL3) - /* wait for room in the tx FIFO on SERIAL3 */ - while ((Ser3UTSR0 & UTSR0_TFS) == 0); - - Ser3UTDR = c; -#endif - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_tstc (void) -{ -#ifdef CONFIG_SERIAL1 - return Ser1UTSR1 & UTSR1_RNE; -#elif defined(CONFIG_SERIAL3) - return Ser3UTSR1 & UTSR1_RNE; -#endif -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -int serial_getc (void) -{ -#ifdef CONFIG_SERIAL1 - while (!(Ser1UTSR1 & UTSR1_RNE)); - - return (char) Ser1UTDR & 0xff; -#elif defined(CONFIG_SERIAL3) - while (!(Ser3UTSR1 & UTSR1_RNE)); - - return (char) Ser3UTDR & 0xff; -#endif -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} diff --git a/cpu/sa1100/start.S b/cpu/sa1100/start.S deleted file mode 100644 index 431ee65..0000000 --- a/cpu/sa1100/start.S +++ /dev/null @@ -1,419 +0,0 @@ -/* - * armboot - Startup Code for SA1100 CPU - * - * Copyright (C) 1998 Dan Malek - * Copyright (C) 1999 Magnus Damm - * Copyright (C) 2000 Wolfgang Denk - * Copyright (c) 2001 Alex Züpke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * relocate armboot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0x13 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - -#ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ -#ifdef CONFIG_USE_IRQ - sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - ble clbss_l - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - - -/* Interupt-Controller base address */ -IC_BASE: .word 0x90050000 -#define ICMR 0x04 - - -/* Reset-Controller */ -RST_BASE: .word 0x90030000 -#define RSRR 0x00 -#define RCSR 0x04 - - -/* PWR */ -PWR_BASE: .word 0x90020000 -#define PSPR 0x08 -#define PPCR 0x14 -cpuspeed: .word CFG_CPUSPEED - - -cpu_init_crit: - /* - * mask all IRQs - */ - ldr r0, IC_BASE - mov r1, #0x00 - str r1, [r0, #ICMR] - - /* set clock speed */ - ldr r0, PWR_BASE - ldr r1, cpuspeed - str r1, [r0, #PPCR] - - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - mov ip, lr - bl lowlevel_init - mov lr, ip - - /* - * disable MMU stuff and enable I-cache - */ - mrc p15,0,r0,c1,c0 - bic r0, r0, #0x00002000 @ clear bit 13 (X) - bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) - orr r0, r0, #0x00001000 @ set bit 12 (I) Icache - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - mcr p15,0,r0,c1,c0 - - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - mov pc, lr - - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - - ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r0, RST_BASE - mov r1, #0x0 @ set bit 3-0 ... - str r1, [r0, #RCSR] @ ... to clear in RCSR - mov r1, #0x1 - str r1, [r0, #RSRR] @ and perform reset - b reset_cpu @ silly, but repeat endlessly diff --git a/create_all_imagesDD.sh b/create_all_imagesDD.sh new file mode 100644 index 0000000..4bee9c7 --- /dev/null +++ b/create_all_imagesDD.sh @@ -0,0 +1,105 @@ +TOPDIR=`pwd` +rm -rf ../images +mkdir -p ../images/DB-78XX0-A-BP/LE/NAND +mkdir -p ../images/DB-78XX0-A-BP/BE +mkdir -p ../images/DB-78200-A-BP/LE/NAND +mkdir -p ../images/DB-78200-A-BP/LE/CV +mkdir -p ../images/DB-78200-A-BP/LE/DUAL_LINUX +mkdir -p ../images/DB-78200-A-BP/BE/CV +mkdir -p ../images/DB-78200-A-BP/BE/DUAL_LINUX +mkdir -p ../images/RD-78200-A-AMC/LE +mkdir -p ../images/DB-88F86323-BP/LE/NAND/DUAL_LINUX_SHARED_MEM +mkdir -p ../images/DB-88F86323-BP/LE/SPI/DUAL_LINUX + +make mrproper +make db78XX0_config LE=1 +make -s +cp u-boot-db78XX0.bin ../images/DB-78XX0-A-BP/LE/ +cp u-boot-db78XX0.srec ../images/DB-78XX0-A-BP/LE/ +cp u-boot-db78XX0 ../images/DB-78XX0-A-BP/LE/ + +make mrproper +make db78XX0_config LE=1 NBOOT=1 +make -s +make nboot +cp u-boot-db78XX0.bin ../images/DB-78XX0-A-BP/LE/NAND +cp u-boot-db78XX0.srec ../images/DB-78XX0-A-BP/LE/NAND +cp u-boot-db78XX0 ../images/DB-78XX0-A-BP/LE/NAND +cp nboot.bin ../images/DB-78XX0-A-BP/LE/NAND + +make mrproper +make db78XX0_config BE=1 +make -s +cp u-boot-db78XX0.bin ../images/DB-78XX0-A-BP/BE/ +cp u-boot-db78XX0.srec ../images/DB-78XX0-A-BP/BE/ +cp u-boot-db78XX0 ../images/DB-78XX0-A-BP/BE/ + +make mrproper +make db78200_MP_config LE=1 +make -s +cp u-boot-db78200_MP.bin ../images/DB-78200-A-BP/LE/CV +cp u-boot-db78200_MP.srec ../images/DB-78200-A-BP/LE/CV +cp u-boot-db78200_MP ../images/DB-78200-A-BP/LE/CV + +make mrproper +make db78200_MP_config LE=1 NBOOT=1 +make -s +make nboot +cp u-boot-db78200_MP.bin ../images/DB-78200-A-BP/LE/NAND +cp u-boot-db78200_MP.srec ../images/DB-78200-A-BP/LE/NAND +cp u-boot-db78200_MP ../images/DB-78200-A-BP/LE/NAND +cp nboot.bin ../images/DB-78200-A-BP/LE/NAND + +make mrproper +make db78200_MP_config LE=1 LNX=1 +make -s +cp u-boot-db78200_MP.bin ../images/DB-78200-A-BP/LE/DUAL_LINUX +cp u-boot-db78200_MP.srec ../images/DB-78200-A-BP/LE/DUAL_LINUX +cp u-boot-db78200_MP ../images/DB-78200-A-BP/LE/DUAL_LINUX + +make mrproper +make db78200_MP_config BE=1 +make -s +cp u-boot-db78200_MP.bin ../images/DB-78200-A-BP/BE/CV +cp u-boot-db78200_MP.srec ../images/DB-78200-A-BP/BE/CV +cp u-boot-db78200_MP ../images/DB-78200-A-BP/BE/CV + +make mrproper +make db78200_MP_config BE=1 LNX=1 +make -s +cp u-boot-db78200_MP.bin ../images/DB-78200-A-BP/BE/DUAL_LINUX +cp u-boot-db78200_MP.srec ../images/DB-78200-A-BP/BE/DUAL_LINUX +cp u-boot-db78200_MP ../images/DB-78200-A-BP/BE/DUAL_LINUX + +make mrproper +make rd78200_MP_AMC_config LE=1 SPIBOOT=1 +make -s +cp u-boot-rd78200_MP_AMC.bin ../images/RD-78200-A-AMC/LE/ +cp u-boot-rd78200_MP_AMC.srec ../images/RD-78200-A-AMC/LE/ +cp u-boot-rd78200_MP_AMC ../images/RD-78200-A-AMC/LE/ + + +make mrproper +make db88f632x_config SPIBOOT=1 LE=1 LNX=1 +make -s +cp u-boot-db88f632x.bin ../images/DB-88F86323-BP/LE/SPI/DUAL_LINUX +cp u-boot-db88f632x.srec ../images/DB-88F86323-BP/LE/SPI/DUAL_LINUX +cp u-boot-db88f632x ../images/DB-88F86323-BP/LE/SPI/DUAL_LINUX + +make mrproper +make db88f632x_config NBOOT=1 LE=1 +make -s +make nboot +cp u-boot-db88f632x.bin ../images/DB-88F86323-BP/LE/NAND +cp u-boot-db88f632x.srec ../images/DB-88F86323-BP/LE/NAND +cp u-boot-db88f632x ../images/DB-88F86323-BP/LE/NAND +cp nboot.bin ../images/DB-88F86323-BP/LE/NAND + +make mrproper +make db88f632x_config NBOOT=1 LE=1 LNX_SHARED=1 +make -s +make nboot +cp u-boot-db88f632x.bin ../images/DB-88F86323-BP/LE/NAND/DUAL_LINUX_SHARED_MEM +cp u-boot-db88f632x.srec ../images/DB-88F86323-BP/LE/NAND/DUAL_LINUX_SHARED_MEM +cp u-boot-db88f632x ../images/DB-88F86323-BP/LE/NAND/DUAL_LINUX_SHARED_MEM +cp nboot.bin ../images/DB-88F86323-BP/LE/NAND/DUAL_LINUX_SHARED_MEM diff --git a/create_all_imagesKW.sh b/create_all_imagesKW.sh new file mode 100644 index 0000000..000c6e0 --- /dev/null +++ b/create_all_imagesKW.sh @@ -0,0 +1,339 @@ +cd .. +mkdir images +cd images +mkdir DB-6281A-BP +mkdir DB-6192A-BP +mkdir RD-6281A +mkdir RD-6192A +mkdir DB-6180A-BP +mkdir DB-6280A-BP +mkdir DB-6282A-BP +cd DB-6281A-BP +mkdir LE +mkdir BE +cd LE +mkdir NAND +mkdir SPI +mkdir SPI+NAND +cd ../BE +mkdir NAND +mkdir SPI +mkdir SPI+NAND +cd ../../DB-6192A-BP +mkdir LE +mkdir BE +cd LE +mkdir NAND +mkdir SPI +mkdir SPI+NAND +cd ../BE +mkdir NAND +mkdir SPI +mkdir SPI+NAND +cd ../../RD-6281A +mkdir LE +mkdir BE +cd LE +mkdir NAND +mkdir SPI +mkdir SPI+NAND +cd ../BE +mkdir NAND +mkdir SPI +mkdir SPI+NAND +cd ../../RD-6192A +mkdir LE +mkdir BE +cd LE +mkdir SPI +cd ../BE +mkdir SPI +cd ../../DB-6180A-BP +mkdir LE +mkdir BE +cd LE +mkdir NAND +mkdir SPI +cd ../BE +mkdir NAND +mkdir SPI +cd ../../DB-6280A-BP +mkdir LE +mkdir BE +cd LE +mkdir NAND +mkdir SPI +mkdir SPI+NAND +cd ../BE +mkdir NAND +mkdir SPI +mkdir SPI+NAND +cd ../../DB-6282A-BP +mkdir LE +mkdir BE +cd LE +mkdir NAND +mkdir SPI +mkdir SPI+NAND +cd ../BE +mkdir NAND +mkdir SPI +mkdir SPI+NAND +cd ../../../u-boot-x.x.x + +make mrproper +make db88f6281abp_config LE=1 NBOOT=1 +make -s +cp u-boot-db88f6281abp_400db_nand.bin ../images/DB-6281A-BP/LE/NAND/ +cp u-boot-db88f6281abp_400db_uart.bin ../images/DB-6281A-BP/LE/NAND/ +cp u-boot-db88f6281abp ../images/DB-6281A-BP/LE/NAND/ + +make mrproper +make db88f6281abp_config LE=1 SPIBOOT=1 +make -s +cp u-boot-db88f6281abp_400db_flash.bin ../images/DB-6281A-BP/LE/SPI +cp u-boot-db88f6281abp_400db_uart.bin ../images/DB-6281A-BP/LE/SPI +cp u-boot-db88f6281abp ../images/DB-6281A-BP/LE/SPI + +make mrproper +make db88f6281abp_config LE=1 SPIBOOT=1 NAND=1 +make -s +cp u-boot-db88f6281abp_400db_flash.bin ../images/DB-6281A-BP/LE/SPI+NAND +cp u-boot-db88f6281abp_400db_uart.bin ../images/DB-6281A-BP/LE/SPI+NAND +cp u-boot-db88f6281abp ../images/DB-6281A-BP/LE/SPI+NAND + + +make mrproper +make db88f6281abp_config BE=1 NBOOT=1 +make -s +cp u-boot-db88f6281abp_400db_nand.bin ../images/DB-6281A-BP/BE/NAND +cp u-boot-db88f6281abp_400db_uart.bin ../images/DB-6281A-BP/BE/NAND +cp u-boot-db88f6281abp ../images/DB-6281A-BP/BE/NAND + +make mrproper +make db88f6281abp_config BE=1 SPIBOOT=1 +make -s +cp u-boot-db88f6281abp_400db_flash.bin ../images/DB-6281A-BP/BE/SPI +cp u-boot-db88f6281abp_400db_uart.bin ../images/DB-6281A-BP/BE/SPI +cp u-boot-db88f6281abp ../images/DB-6281A-BP/BE/SPI + +make mrproper +make db88f6281abp_config BE=1 SPIBOOT=1 NAND=1 +make -s +cp u-boot-db88f6281abp_400db_flash.bin ../images/DB-6281A-BP/BE/SPI+NAND +cp u-boot-db88f6281abp_400db_uart.bin ../images/DB-6281A-BP/BE/SPI+NAND +cp u-boot-db88f6281abp ../images/DB-6281A-BP/BE/SPI+NAND + +make mrproper +make db88f6192abp_config LE=1 NBOOT=1 +make -s +cp u-boot-db88f6192abp_200db619x_nand.bin ../images/DB-6192A-BP/LE/NAND +cp u-boot-db88f6192abp_200db619x_uart.bin ../images/DB-6192A-BP/LE/NAND +cp u-boot-db88f6192abp ../images/DB-6192A-BP/LE/NAND + +make mrproper +make db88f6192abp_config LE=1 SPIBOOT=1 +make -s +cp u-boot-db88f6192abp_200db619x_flash.bin ../images/DB-6192A-BP/LE/SPI +cp u-boot-db88f6192abp_200db619x_uart.bin ../images/DB-6192A-BP/LE/SPI +cp u-boot-db88f6192abp ../images/DB-6192A-BP/LE/SPI + +make mrproper +make db88f6192abp_config LE=1 SPIBOOT=1 NAND=1 +make -s +cp u-boot-db88f6192abp_200db619x_flash.bin ../images/DB-6192A-BP/LE/SPI+NAND +cp u-boot-db88f6192abp_200db619x_uart.bin ../images/DB-6192A-BP/LE/SPI+NAND +cp u-boot-db88f6192abp ../images/DB-6192A-BP/LE/SPI+NAND + +make mrproper +make db88f6192abp_config BE=1 NBOOT=1 +make -s +cp u-boot-db88f6192abp_200db619x_nand.bin ../images/DB-6192A-BP/BE/NAND +cp u-boot-db88f6192abp_200db619x_uart.bin ../images/DB-6192A-BP/BE/NAND +cp u-boot-db88f6192abp ../images/DB-6192A-BP/BE/NAND + +make mrproper +make db88f6192abp_config BE=1 SPIBOOT=1 +make -s +cp u-boot-db88f6192abp_200db619x_flash.bin ../images/DB-6192A-BP/BE/SPI +cp u-boot-db88f6192abp_200db619x_uart.bin ../images/DB-6192A-BP/BE/SPI +cp u-boot-db88f6192abp ../images/DB-6192A-BP/BE/SPI + +make mrproper +make db88f6192abp_config BE=1 SPIBOOT=1 NAND=1 +make -s +cp u-boot-db88f6192abp_200db619x_flash.bin ../images/DB-6192A-BP/BE/SPI+NAND +cp u-boot-db88f6192abp_200db619x_uart.bin ../images/DB-6192A-BP/BE/SPI+NAND +cp u-boot-db88f6192abp ../images/DB-6192A-BP/BE/SPI+NAND + +make mrproper +make rd88f6281a_config LE=1 NBOOT=1 +make -s +cp u-boot-rd88f6281a_400rd_nand.bin ../images/RD-6281A/LE/NAND +cp u-boot-rd88f6281a_400rd_uart.bin ../images/RD-6281A/LE/NAND +cp u-boot-rd88f6281a ../images/RD-6281A/LE/NAND + +make mrproper +make rd88f6281a_config LE=1 SPIBOOT=1 +make -s +cp u-boot-rd88f6281a_400rd_flash.bin ../images/RD-6281A/LE/SPI +cp u-boot-rd88f6281a_400rd_uart.bin ../images/RD-6281A/LE/SPI +cp u-boot-rd88f6281a ../images/RD-6281A/LE/SPI + +make mrproper +make rd88f6281a_config LE=1 SPIBOOT=1 NAND=1 +make -s +cp u-boot-rd88f6281a_400rd_flash.bin ../images/RD-6281A/LE/SPI+NAND +cp u-boot-rd88f6281a_400rd_uart.bin ../images/RD-6281A/LE/SPI+NAND +cp u-boot-rd88f6281a ../images/RD-6281A/LE/SPI+NAND + +make mrproper +make rd88f6281a_config BE=1 NBOOT=1 +make -s +cp u-boot-rd88f6281a_400rd_nand.bin ../images/RD-6281A/BE/NAND +cp u-boot-rd88f6281a_400rd_uart.bin ../images/RD-6281A/BE/NAND +cp u-boot-rd88f6281a ../images/RD-6281A/BE/NAND + +make mrproper +make rd88f6281a_config BE=1 SPIBOOT=1 +make -s +cp u-boot-rd88f6281a_400rd_flash.bin ../images/RD-6281A/BE/SPI +cp u-boot-rd88f6281a_400rd_uart.bin ../images/RD-6281A/BE/SPI +cp u-boot-rd88f6281a ../images/RD-6281A/BE/SPI + +make mrproper +make rd88f6281a_config BE=1 SPIBOOT=1 NAND=1 +make -s +cp u-boot-rd88f6281a_400rd_flash.bin ../images/RD-6281A/BE/SPI+NAND +cp u-boot-rd88f6281a_400rd_uart.bin ../images/RD-6281A/BE/SPI+NAND +cp u-boot-rd88f6281a ../images/RD-6281A/BE/SPI+NAND + +make mrproper +make mrproper +make rd88f6192a_config LE=1 SPIBOOT=1 +make -s +cp u-boot-rd88f6192a_200rd_flash.bin ../images/RD-6192A/LE/SPI +cp u-boot-rd88f6192a_200rd_uart.bin ../images/RD-6192A/LE/SPI +cp u-boot-rd88f6192a ../images/RD-6192A/LE/SPI + +make mrproper +make rd88f6192a_config BE=1 SPIBOOT=1 +make -s +cp u-boot-rd88f6192a_200rd_flash.bin ../images/RD-6192A/BE/SPI +cp u-boot-rd88f6192a_200rd_uart.bin ../images/RD-6192A/BE/SPI +cp u-boot-rd88f6192a ../images/RD-6192A/BE/SPI + +make mrproper +make db88f6180abp_config LE=1 NBOOT=1 +make -s +cp u-boot-db88f6180abp_200db_nand.bin ../images/DB-6180A-BP/LE/NAND/ +cp u-boot-db88f6180abp_200db_uart.bin ../images/DB-6180A-BP/LE/NAND/ +cp u-boot-db88f6180abp ../images/DB-6180A-BP/LE/NAND/ + +make mrproper +make db88f6180abp_config LE=1 SPIBOOT=1 +make -s +cp u-boot-db88f6180abp_200db_flash.bin ../images/DB-6180A-BP/LE/SPI +cp u-boot-db88f6180abp_200db_uart.bin ../images/DB-6180A-BP/LE/SPI +cp u-boot-db88f6180abp ../images/DB-6180A-BP/LE/SPI + +make mrproper +make db88f6180abp_config BE=1 NBOOT=1 +make -s +cp u-boot-db88f6180abp_200db_nand.bin ../images/DB-6180A-BP/BE/NAND +cp u-boot-db88f6180abp_200db_uart.bin ../images/DB-6180A-BP/BE/NAND +cp u-boot-db88f6180abp ../images/DB-6180A-BP/BE/NAND + +make mrproper +make db88f6180abp_config BE=1 SPIBOOT=1 +make -s +cp u-boot-db88f6180abp_200db_flash.bin ../images/DB-6180A-BP/BE/SPI +cp u-boot-db88f6180abp_200db_uart.bin ../images/DB-6180A-BP/BE/SPI +cp u-boot-db88f6180abp ../images/DB-6180A-BP/BE/SPI + +make mrproper +make db88f6280abp_config LE=1 NBOOT=1 +make -s +cp u-boot-db88f6280abp_200db6280_nand.bin ../images/DB-6280A-BP/LE/NAND/ +cp u-boot-db88f6280abp_200db6280_uart.bin ../images/DB-6280A-BP/LE/NAND/ +cp u-boot-db88f6280abp ../images/DB-6280A-BP/LE/NAND/ + +make mrproper +make db88f6280abp_config LE=1 SPIBOOT=1 +make -s +cp u-boot-db88f6280abp_200db6280_flash.bin ../images/DB-6280A-BP/LE/SPI +cp u-boot-db88f6280abp_200db6280_uart.bin ../images/DB-6280A-BP/LE/SPI +cp u-boot-db88f6280abp ../images/DB-6280A-BP/LE/SPI + +make mrproper +make db88f6280abp_config LE=1 SPIBOOT=1 NAND=1 +make -s +cp u-boot-db88f6280abp_200db6280_flash.bin ../images/DB-6280A-BP/LE/SPI+NAND +cp u-boot-db88f6280abp_200db6280_uart.bin ../images/DB-6280A-BP/LE/SPI+NAND +cp u-boot-db88f6280abp ../images/DB-6280A-BP/LE/SPI+NAND + + +make mrproper +make db88f6280abp_config BE=1 NBOOT=1 +make -s +cp u-boot-db88f6280abp_200db6280_nand.bin ../images/DB-6280A-BP/BE/NAND +cp u-boot-db88f6280abp_200db6280_uart.bin ../images/DB-6280A-BP/BE/NAND +cp u-boot-db88f6280abp ../images/DB-6280A-BP/BE/NAND + +make mrproper +make db88f6280abp_config BE=1 SPIBOOT=1 +make -s +cp u-boot-db88f6280abp_200db6280_flash.bin ../images/DB-6280A-BP/BE/SPI +cp u-boot-db88f6280abp_200db6280_uart.bin ../images/DB-6280A-BP/BE/SPI +cp u-boot-db88f6280abp ../images/DB-6280A-BP/BE/SPI + +make mrproper +make db88f6280abp_config BE=1 SPIBOOT=1 NAND=1 +make -s +cp u-boot-db88f6280abp_200db6280_flash.bin ../images/DB-6280A-BP/BE/SPI+NAND +cp u-boot-db88f6280abp_200db6280_uart.bin ../images/DB-6280A-BP/BE/SPI+NAND +cp u-boot-db88f6280abp ../images/DB-6280A-BP/BE/SPI+NAND + +make mrproper +make db88f6282abp_config LE=1 NBOOT=1 +make -s +cp u-boot-db88f6282abp_400db_nand.bin ../images/DB-6282A-BP/LE/NAND/ +cp u-boot-db88f6282abp_400db_uart.bin ../images/DB-6282A-BP/LE/NAND/ +cp u-boot-db88f6282abp ../images/DB-6282A-BP/LE/NAND/ + +make mrproper +make db88f6282abp_config LE=1 SPIBOOT=1 +make -s +cp u-boot-db88f6282abp_400db_flash.bin ../images/DB-6282A-BP/LE/SPI +cp u-boot-db88f6282abp_400db_uart.bin ../images/DB-6282A-BP/LE/SPI +cp u-boot-db88f6282abp ../images/DB-6282A-BP/LE/SPI + +make mrproper +make db88f6282abp_config LE=1 SPIBOOT=1 NAND=1 +make -s +cp u-boot-db88f6282abp_400db_flash.bin ../images/DB-6282A-BP/LE/SPI+NAND +cp u-boot-db88f6282abp_400db_uart.bin ../images/DB-6282A-BP/LE/SPI+NAND +cp u-boot-db88f6282abp ../images/DB-6282A-BP/LE/SPI+NAND + + +make mrproper +make db88f6282abp_config BE=1 NBOOT=1 +make -s +cp u-boot-db88f6282abp_400db_nand.bin ../images/DB-6282A-BP/BE/NAND +cp u-boot-db88f6282abp_400db_uart.bin ../images/DB-6282A-BP/BE/NAND +cp u-boot-db88f6282abp ../images/DB-6282A-BP/BE/NAND + +make mrproper +make db88f6282abp_config BE=1 SPIBOOT=1 +make -s +cp u-boot-db88f6282abp_400db_flash.bin ../images/DB-6282A-BP/BE/SPI +cp u-boot-db88f6282abp_400db_uart.bin ../images/DB-6282A-BP/BE/SPI +cp u-boot-db88f6282abp ../images/DB-6282A-BP/BE/SPI + +make mrproper +make db88f6282abp_config BE=1 SPIBOOT=1 NAND=1 +make -s +cp u-boot-db88f6282abp_400db_flash.bin ../images/DB-6282A-BP/BE/SPI+NAND +cp u-boot-db88f6282abp_400db_uart.bin ../images/DB-6282A-BP/BE/SPI+NAND +cp u-boot-db88f6282abp ../images/DB-6282A-BP/BE/SPI+NAND + diff --git a/diag/Makefile b/diag/Makefile new file mode 100644 index 0000000..6b7c6c1 --- /dev/null +++ b/diag/Makefile @@ -0,0 +1,7 @@ + +include $(TOPDIR)/board/mv_feroceon/config_kw/mvRules.mk + +LIB = libdiag.a +COBJS = main.o diag_memory.o diag_rtc.o diag_nand.o diag_gbe.o + +include $(TOPDIR)/diag/rules.mk diff --git a/diag/diag.h b/diag/diag.h new file mode 100644 index 0000000..6645fc6 --- /dev/null +++ b/diag/diag.h @@ -0,0 +1,36 @@ +#ifndef _DIAG_H +#define _DIAG_H + +#define DIAG_BAUD_RATE 115200 +#define DIAG_SERIAL_CONSOLE_PORT 0 + +#define DIAG_PASS (0x00) +#define DIAG_FAIL (0x01) + +#define PAGES_PER_BLOCK 64 + +typedef int (diag_func_t) (void); +extern unsigned int *mem_test_start_offset; +extern unsigned int *mem_test_end_offset; + +/* Function prototypes */ +int mem_data_bus_test(void); +int mem_address_bus_test(void); +int mem_device_test(void); +int gbe_link_detect_test(void); +int gbe_mac_loopback_test(void); +int gbe_external_loopback_test(void); +int rtc_test(void); +int mvNandDetectTest(void); +int mvNandBadBlockTest(void); +int mvNandReadWriteTest(void); + +void diag_init(char *); +void diag_board_init(char *); +void diag_serial_init(int, int); +void diag_get_mem_detail(unsigned int **, unsigned int **); +void diag_int_lpbk(int, int); +void diag_uart_putc(int, unsigned char); +int diag_uart_getc(int, unsigned char *); + +#endif /* _DIAG_H */ diff --git a/diag/diag_gbe.c b/diag/diag_gbe.c new file mode 100644 index 0000000..523af00 --- /dev/null +++ b/diag/diag_gbe.c @@ -0,0 +1,100 @@ +#include + +#include "diag.h" +#include "eth-phy/mvEthPhy.h" +#include "mvBoardEnvLib.h" + +/******************************************************************************* +* +* Name : gbe_link_detect_test +* Description : GbE Link Detection Test +* +* Input arg : None +* Output arg : None +* Return : Returns 1 on failure, else 0 +*******************************************************************************/ + +int gbe_link_detect_test() +{ + unsigned int val = 0; + unsigned int result = 0; + + /* read specific status reg */ + if( mvEthPhyRegRead( mvBoardPhyAddrGet(0), ETH_PHY_SPEC_STATUS_REG, &val) != MV_OK ) + return MV_ERROR; + + switch (val & ETH_PHY_SPEC_STATUS_SPEED_MASK) + { + case ETH_PHY_SPEC_STATUS_SPEED_1000MBPS: + printf( "\tSpeed: 1000 Mbps, " ); + break; + case ETH_PHY_SPEC_STATUS_SPEED_100MBPS: + printf( "\tSpeed: 100 Mbps, " ); + break; + case ETH_PHY_SPEC_STATUS_SPEED_10MBPS: + printf( "\tSpeed: 10 Mbps, " ); + default: + printf( "\tSpeed: Uknown, " ); + break; + } + + if( val & ETH_PHY_SPEC_STATUS_DUPLEX_MASK ) + { + printf( "Duplex: Full, " ); + } + else + { + printf( "Duplex: Half, " ); + } + + if( val & ETH_PHY_SPEC_STATUS_LINK_MASK ) + { + printf("Link: up\n"); + result = 1; + } + else + { + printf("Link: down\n"); + result = 0; + } + printf("\tGbE link detect test "); + printf(((result)? "PASSED\n":"FAILED\n")); + + return 0; +} + +/******************************************************************************* +* +* Name : gbe_mac_loopback_test +* Description : GbE MAC Loopback Test +* +* Input arg : None +* Output arg : None +* Return : Returns 1 on failure, else 0 +*******************************************************************************/ + +int gbe_mac_loopback_test(void) +{ + printf("\tGbE mac loopback test "); + + printf("PASSED\n"); + return 0; +} + +/******************************************************************************* +* +* Name : gbe_external_loopback_test +* Description : GbE External Loopback Test +* Input arg : None +* Output arg : None +* Return : Returns 1 on failure, else 0 +*******************************************************************************/ + +int gbe_external_loopback_test(void) +{ + printf("\tGbE external loopback test "); + + printf("PASSED\n"); + return 0; +} + diff --git a/diag/diag_memory.c b/diag/diag_memory.c new file mode 100644 index 0000000..4ca6450 --- /dev/null +++ b/diag/diag_memory.c @@ -0,0 +1,166 @@ + +#include + +#include "diag.h" + +/******************************************************************************* +* +* Name : mem_data_bus_test +* Description : The function tests data bus of the DRAM. It writes walking one +* pattern to a fixed memory location. +* Input arg : None +* Output arg : None +* Return : Returns 1 on failure, else 0 +*******************************************************************************/ + +int mem_data_bus_test(void) +{ + unsigned int pattern = 1; + unsigned int *address = mem_test_start_offset; + + printf("\tDDR2 data bus test "); + + for(; pattern != 0; pattern <<= 1) + { + *address = pattern; + + if(pattern != *address) + { + printf("FAILED\n"); + printf("\t\tTest failed at offset = 0x%X\n" + "\t\tData written = 0x%X\n" + "\t\tData read = 0x%X\n", address, + pattern, *address); + return 1; + } + } + printf("PASSED\n"); + return 0; +} + +/******************************************************************************* +* +* Name : mem_address_bus_test +* Description : The function tests address bus of the DRAM. It writes walking +* one pattern while changes the addresses in the same way. i.e. +* write 1 to offset 1, 8 to offset 8, etc. Verify the data after +* writting to the buffer with length MEM_ADD_TEST_SIZE. +* Input arg : None +* Output arg : None +* Return : Returns 1 on failure, else 0 +*******************************************************************************/ + +int mem_address_bus_test(void) +{ + unsigned int offset = 1, size; + unsigned int *base_address = mem_test_start_offset; + + size = mem_test_end_offset - mem_test_start_offset; + + printf("\tDDR2 address bus test "); + + /* We should start with pattern = 1. As we want to use offset and + * pattern the same variable, we will decrement base address by 1. + * So, even if we start with offset = pattern = 1, we have actually + * started from the given base address. */ + base_address--; + + for(; offset < size; offset <<= 1) + { + base_address[offset] = offset; + } + + for(offset = 1; offset < size; offset <<= 1) + { + if(base_address[offset] != offset) + { + printf("FAILED\n"); + printf("\t\tTest failed at offset = 0x%X\n" + "\t\tData written = 0x%X\n" + "\t\tData read = 0x%X\n", base_address + + offset, offset, base_address[offset]); + return 1; + } + } + printf("PASSED\n"); + return 0; +} + +/******************************************************************************* +* +* Name : mem_device_test +* Description : The function tests address bus of the DRAM. It writes walking +* one pattern while changes the addresses in the same way. i.e. +* write 1 to offset 1, 8 to offset 8, etc. Verify the data after +* writting to the buffer with length MEM_ADD_TEST_SIZE. +* Input arg : None +* Output arg : None +* Return : Returns 1 on failure, else 0 +*******************************************************************************/ + +int mem_device_test(void) +{ + unsigned int offset = 1, size; + unsigned int *base_address = mem_test_start_offset; + + size = mem_test_end_offset - mem_test_start_offset; + + printf("\tDDR2 device test "); + + /* Debug print */ +#ifdef DEBUG + printf("Start address = %#X\n", base_address); + printf("size = %#X\n", size); +#endif + + /* We should start with pattern = 1. As we want to use offset and + * pattern the same variable, we will decrement base address by 1. + * So, even if we start with offset = pattern = 1, we have actually + * started from the given base address. */ + base_address--; + + for(; offset < size; offset++) + { + base_address[offset] = offset; + } + + /* Check previously written pattern and write anti-pattern */ + for(offset = 1; offset < size; offset++) + { + if(base_address[offset] != offset) + { + printf("FAILED\n"); + printf("\t\tTest failed at offset = 0x%X\n" + "\t\tData written = 0x%X\n" + "\t\tData read = 0x%X\n", base_address + + offset, offset, base_address[offset]); + return 1; + } + + /* Write anti-pattern */ + base_address[offset] = ~offset; + } + + /* Debug print */ +#ifdef DEBUG + printf("Checking anti-pattern\n"); +#endif + + /* Check anti-pattern */ + for(offset = 1; offset < size; offset++) + { + if(base_address[offset] != ~offset) + { + printf("FAILED\n"); + printf("\t\tTest failed at offset = 0x%X\n" + "\t\tData written = 0x%X\n" + "\t\tData read = 0x%X\n", base_address + + offset, ~offset, base_address[offset]); + return 1; + } + } + + printf("PASSED\n"); + return 0; +} + diff --git a/diag/diag_nand.c b/diag/diag_nand.c new file mode 100644 index 0000000..8d4caa7 --- /dev/null +++ b/diag/diag_nand.c @@ -0,0 +1,203 @@ + +#include + +#include +#include "diag.h" + +extern nand_info_t nand_info[]; + +/******************************************************************************* + * mvNandDetectTest - Detect NAND flash with it’s geometry and prints details. + * + * DESCRIPTION: + * This routine prints NAND detection status. Also displays NAND flash size, + * page size, number of blocks if detected. + * + * INPUT: + * None. + * + * OUTPUT: + * None. + * + * RETURN: + * Returns 1 on failure, else 0 + *******************************************************************************/ +int mvNandDetectTest(void) +{ + int testFlag; + testFlag = DIAG_PASS; + + if(NULL != nand_info[0].name) + { + printf("\tDevice: 0, Size: %lu MB, Page Size: %d KB, Block Size: %d KB\n", \ + (nand_info[0].size/1024)/1024, nand_info[0].oobblock/1024, \ + nand_info[0].erasesize/1024); + } + else + { + printf("\tError: NAND not detected!"); + testFlag = DIAG_FAIL; + } + + printf("\tNAND detection test "); + printf(((testFlag==DIAG_PASS)?"PASSED\n":"FAIL\n")); + + return testFlag; +} + +/******************************************************************************* + * mvNandBadBlockTest - Prints all bad blocks on NAND memory + * + * DESCRIPTION: + * This routine checks all blocks against bad block table and prints the + * block if it is marked as bad. + * + * INPUT: + * None. + * + * OUTPUT: + * None. + * + * RETURN: + * Returns 1 on failure, else 0 + *******************************************************************************/ +int mvNandBadBlockTest(void) +{ + int testFlag; + unsigned int off; + testFlag = DIAG_PASS; + + for (off=0; off < nand_info[0].size; off += nand_info[0].erasesize) + { + if (nand_block_isbad(&nand_info[0], off)) + { + printf("\tBad Block: %08x\n", off); + } + } + printf("\tNAND bad-block detection test "); + printf((testFlag==DIAG_PASS)?"PASSED\n":"FAIL\n"); + + return testFlag; +} + +/******************************************************************************* + * mvNandReadWriteTest - Performs read-write test on NAND chip. + * + * DESCRIPTION: + * This routine writes pattern 0x55,0xaa in 16 blocks at offset immediately + * after ENV section and reads them back and verifies. + * + * INPUT: + * None. + * + * OUTPUT: + * None. + * + * RETURN: + * Returns 1 on failure, else 0 + *******************************************************************************/ +int mvNandReadWriteTest(void) +{ + int i,j,ret; + int testFlag; + unsigned int pageSize; + unsigned char rbuf[2048]; + nand_write_options_t wr_opts; + nand_erase_options_t er_opts; + nand_read_options_t rd_opts; + testFlag = DIAG_PASS; + + printf("\tNAND read/write test "); + + do + { + pageSize = nand_info[0].oobblock; + + /***************** ERASE ***********************/ + memset(&er_opts, 0, sizeof(er_opts)); + er_opts.offset = CFG_ENV_OFFSET + CFG_ENV_SIZE; + er_opts.length = pageSize * PAGES_PER_BLOCK * 16; + er_opts.quiet = 1; + ret = nand_erase_opts(&nand_info[0], &er_opts); + if (ret) + { + printf("\tError: NAND Erase faild!\n"); + testFlag = DIAG_FAIL; + break; + } + if(DIAG_PASS != testFlag) + { + break; + } + + /***************** WRITE ***********************/ + memset(&wr_opts, 0, sizeof(wr_opts)); + for(i=0; i < pageSize; i=i+2) + { + wr_opts.buffer[i] = 0x55; + wr_opts.buffer[i+1] = 0xaa; + } + wr_opts.length = pageSize; + wr_opts.offset = CFG_ENV_OFFSET + CFG_ENV_SIZE; + /* opts.forcejffs2 = 1; */ + wr_opts.pad = 1; + wr_opts.blockalign = 1; + wr_opts.quiet = 1; + + for(i=0; i < PAGES_PER_BLOCK * 16;i++) + { + ret = nand_write_opts(&nand_info[0], &wr_opts); + if (ret) + { + printf("\tError: NAND write faild!\n"); + testFlag = DIAG_FAIL; + break; + } + wr_opts.offset += pageSize; + } + if(DIAG_PASS != testFlag) + { + break; + } + + /**************** READ *************************/ + memset(&rd_opts, 0, sizeof(rd_opts)); + rd_opts.buffer = rbuf; + rd_opts.length = (ulong)pageSize; + rd_opts.offset = CFG_ENV_OFFSET + CFG_ENV_SIZE; + rd_opts.quiet = 1; + + for(i=0; i < PAGES_PER_BLOCK * 16;i++) + { + ret = nand_read_opts(&nand_info[0], &rd_opts); + if (ret) + { + printf("\tError: NAND read faild!\n"); + testFlag = DIAG_FAIL; + break; + } + + for(j=0; j < pageSize; j=j+4) + { + if (rbuf[j] != 0x55 && rbuf[j+1] != 0xaa && rbuf[j+2] != 0x55 && rbuf[j+3] != 0xaa) + { + printf("\tError: Data verify failed\n"); + testFlag = DIAG_FAIL; + break; + } + } + rd_opts.offset += pageSize; + } + if(DIAG_PASS != testFlag) + { + break; + } + + }while(0); + + printf((testFlag==DIAG_PASS)?"PASSED\n":"FAIL\n"); + + return testFlag; +} + + diff --git a/diag/diag_rtc.c b/diag/diag_rtc.c new file mode 100644 index 0000000..4c24d52 --- /dev/null +++ b/diag/diag_rtc.c @@ -0,0 +1,51 @@ + +#include + +#include "diag.h" + +int rtc_test(void) +{ + int hour1, minute1, second1; + int hour2, minute2, second2; + int ret_val = 0; + + printf("\tRTC test "); + + diag_get_rtc_time(&hour1, &minute1, &second1); + + /* FIXME: Observation says RTC requires additional udelay(1) to + * read proper value + */ + udelay(1000000); + + /* Set a time that changes all the digits after a second */ + diag_set_rtc_time(9, 59, 59); + + /* Wait for 1 second */ + /* Observation says RTC takes additional one second when new time is set */ + udelay(2000000); + + diag_get_rtc_time(&hour2, &minute2, &second2); + + if(hour2 != 10 || + minute2 != 0 || + second2 > 1) + { + /* Second should be 0 or max 1 (if error in udealy), not > 1 */ + + printf("FAILED\n"); + printf("\t\tGot: hour %02d minute %02d second %02d\n", hour2, minute2, second2); + printf("\t\tExpected: hour 10 minute 00 second 00\n"); + ret_val = 1; + } + else + { + printf("\t\t\t\t\t PASSED\n"); + } + + /* As incrementing a second here will require complex calculation, + * we will ignore that passed second */ + diag_set_rtc_time(hour1, minute1, second1); + + return ret_val; +} diff --git a/diag/main.c b/diag/main.c new file mode 100644 index 0000000..4fa38c7 --- /dev/null +++ b/diag/main.c @@ -0,0 +1,59 @@ + +#include +#include + +diag_func_t *diag_sequence[] = +{ + mem_data_bus_test, /* DRAM Data bus test */ + mem_address_bus_test, /* DRAM Address bus test */ + mem_device_test, /* DRAM device test */ + mvNandDetectTest, + mvNandBadBlockTest, + gbe_link_detect_test, + //gbe_mac_loopback_test, + //gbe_external_loopback_test, + mvNandReadWriteTest, + rtc_test, /* RTC test */ + NULL, +}; + +unsigned int *mem_test_start_offset; +unsigned int *mem_test_end_offset; + +void run_diag(void) +{ + char board_name[30]; + diag_func_t **diag_func_ptr; + + printf("\n\nRunning diagnostics ...\n"); + + /* Get the start and the end memory address offset for memory test */ + diag_get_mem_detail(&mem_test_start_offset, &mem_test_end_offset); + + for (diag_func_ptr = diag_sequence; *diag_func_ptr; ++diag_func_ptr) + { + printf("\n"); + if((*diag_func_ptr)()) + break; + } + + if(*diag_func_ptr == NULL) + printf("\nDiag completed\n"); + else + printf("\nDiag FAILED\n"); +} + +void diag_init(char *board_name) +{ + /* Init interrupts - we would need this as we use timer interrupt in udelay */ + interrupt_init(); + + /* Initialize board so that all the GPIO are set & we are good to init serial */ + diag_board_init(board_name); + + /* Get the start and the end memory address offset for memory test */ + diag_get_mem_detail(&mem_test_start_offset, &mem_test_end_offset); + + /* Serial init */ + diag_serial_init(DIAG_SERIAL_CONSOLE_PORT, DIAG_BAUD_RATE); +} diff --git a/diag/rules.mk b/diag/rules.mk new file mode 100644 index 0000000..cdf9474 --- /dev/null +++ b/diag/rules.mk @@ -0,0 +1,22 @@ + + +include $(TOPDIR)/config.mk +include $(TOPDIR)/board/mv_feroceon/config_kw/mvRules.mk + +OBJS = $(AOBJS) $(COBJS) + +CFLAGS += -I$(TOPDIR)/diag + +all: $(LIB) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > .depend + +sinclude .depend + +######################################################################### diff --git a/disk/.depend b/disk/.depend new file mode 100644 index 0000000..673cc8d --- /dev/null +++ b/disk/.depend @@ -0,0 +1,184 @@ +part.o: part.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h \ + part_efi.h diff --git a/disk/Makefile b/disk/Makefile index 39677f1..6dfffdc 100644 --- a/disk/Makefile +++ b/disk/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = libdisk.a -OBJS = part.o part_mac.o part_dos.o part_iso.o part_amiga.o +OBJS = part.o part_mac.o part_dos.o part_iso.o part_amiga.o part_efi.o all: $(LIB) diff --git a/disk/part.c b/disk/part.c index 2255e72..d517c1b 100644 --- a/disk/part.c +++ b/disk/part.c @@ -120,6 +120,34 @@ void dev_print (block_dev_desc_t *dev_desc) } else { puts (" Capacity: not available\n"); } + + +#if 0 /*def CONFIG_BUFFALO_PLATFORM*/ + + if ((dev_desc->lba * dev_desc->blksz)>0L) { + unsigned char string_dev_p[50] ; + ulong mb, mb_quot, mb_rem, gb, gb_quot, gb_rem; + lbaint_t lba; + + lba = dev_desc->lba; + + lba512 = (lba * (dev_desc->blksz/512)); + mb = (10 * lba512) / 2048; /* 2048 = (1024 * 1024) / 512 MB */ + /* round to 1 digit */ + mb_quot = mb / 10; + mb_rem = mb - (10 * mb_quot); + + gb = mb / 1024; + gb_quot = gb / 10; + gb_rem = gb - (10 * gb_quot); + sprintf(string_dev_p,"%s16.16Capa.:%ld GB ",dev_desc->vendor,gb_quot) ; +/* "0123456789012345601234567890123456"*/ + micon_printf(0,string_dev_p) ; + +} +#endif + + } #endif /* CFG_CMD_IDE || CFG_CMD_SCSI || CFG_CMD_USB || CONFIG_MMC */ @@ -131,7 +159,8 @@ void dev_print (block_dev_desc_t *dev_desc) #if defined(CONFIG_MAC_PARTITION) || \ defined(CONFIG_DOS_PARTITION) || \ defined(CONFIG_ISO_PARTITION) || \ - defined(CONFIG_AMIGA_PARTITION) + defined(CONFIG_AMIGA_PARTITION) || \ + defined(CONFIG_EFI_PARTITION) void init_part (block_dev_desc_t * dev_desc) { @@ -149,6 +178,14 @@ void init_part (block_dev_desc_t * dev_desc) } #endif +/* must be placed before DOS partition detection */ +#ifdef CONFIG_EFI_PARTITION + if (test_part_efi(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_EFI; + return; + } +#endif + #ifdef CONFIG_DOS_PARTITION if (test_part_dos(dev_desc) == 0) { dev_desc->part_type = PART_TYPE_DOS; @@ -204,6 +241,15 @@ int get_partition_info (block_dev_desc_t *dev_desc, int part, disk_partition_t * } break; #endif + +#ifdef CONFIG_EFI_PARTITION + case PART_TYPE_EFI: + if (get_partition_info_efi(dev_desc,part,info) == 0) { + PRINTF ("## Valid EFI partition found ##\n"); + return (0); + } + break; +#endif default: break; } @@ -265,13 +311,22 @@ void print_part (block_dev_desc_t * dev_desc) print_part_amiga (dev_desc); return; #endif + +#ifdef CONFIG_EFI_PARTITION + case PART_TYPE_EFI: + PRINTF ("## Testing for valid EFI partition ##\n"); + print_part_header ("EFI", dev_desc); + print_part_efi (dev_desc); + return; +#endif } puts ("## Unknown partition table\n"); } -#else /* neither MAC nor DOS nor ISO partition configured */ -# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION nor CONFIG_ISO_PARTITION configured! +#else /* neither MAC nor DOS nor ISO nor EFI partition configured */ +# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION +# error nor CONFIG_ISO_PARTITION nor CONFIG_EFI_PARTITION configured! #endif #endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) || CONFIG_COMMANDS & CFG_CMD_SCSI) */ diff --git a/disk/part_dos.c b/disk/part_dos.c index 133ee79..45cbb35 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "part_dos.h" #if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ @@ -45,6 +46,7 @@ */ static inline int le32_to_int(unsigned char *le32) { + return ((le32[3] << 24) + (le32[2] << 16) + (le32[1] << 8) + @@ -71,8 +73,8 @@ static void print_one_part (dos_partition_t *p, int ext_part_sector, int part_nu static int test_block_type(unsigned char *buffer) { - if((buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) || - (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) { + if((buffer[DOS_PART_MAGIC_OFFSET + 0] != MBR_MAGIC_BYTE0) || + (buffer[DOS_PART_MAGIC_OFFSET + 1] != MBR_MAGIC_BYTE1) ) { return (-1); } /* no DOS Signature at all */ if(strncmp((char *)&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0) @@ -84,10 +86,9 @@ static int test_block_type(unsigned char *buffer) int test_part_dos (block_dev_desc_t *dev_desc) { unsigned char buffer[DEFAULT_SECTOR_SIZE]; - if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) || - (buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) || - (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) { + (buffer[DOS_PART_MAGIC_OFFSET + 0] != MBR_MAGIC_BYTE0) || + (buffer[DOS_PART_MAGIC_OFFSET + 1] != MBR_MAGIC_BYTE1) ) { return (-1); } return (0); @@ -171,14 +172,24 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part dev_desc->dev, ext_part_sector); return -1; } - if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || - buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) { + + i = test_block_type(buffer); + if (i == -1) { printf ("bad MBR sector signature 0x%02x%02x\n", buffer[DOS_PART_MAGIC_OFFSET], buffer[DOS_PART_MAGIC_OFFSET + 1]); return -1; } + if(i==DOS_PBR) { + info->boot_ind = 0; + info->blksz = 512; + info->start = 0; + info->size = dev_desc->lba; + sprintf (info->name, "usbd01"); + return 0; + } + /* Print all primary/logical partitions */ pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); for (i = 0; i < 4; i++, pt++) { @@ -189,6 +200,7 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part if ((pt->sys_ind != 0) && (part_num == which_part) && (is_extended(pt->sys_ind) == 0)) { + info->boot_ind = (pt->boot_ind == 0x80) ? 1 : 0; info->blksz = 512; info->start = ext_part_sector + le32_to_int (pt->start4); info->size = le32_to_int (pt->size4); @@ -206,6 +218,9 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part case IF_TYPE_DOC: sprintf ((char *)info->name, "docd%c%d\n", 'a' + dev_desc->dev, part_num); break; + case IF_TYPE_MMC: + sprintf ((char *)info->name, "mmc%c%d\n", 'a' + dev_desc->dev, part_num); + break; default: sprintf ((char *)info->name, "xx%c%d\n", 'a' + dev_desc->dev, part_num); break; diff --git a/disk/part_dos.h b/disk/part_dos.h index ac93f20..cc9e8f5 100644 --- a/disk/part_dos.h +++ b/disk/part_dos.h @@ -34,11 +34,15 @@ #endif #define DOS_PART_TBL_OFFSET 0x1be #define DOS_PART_MAGIC_OFFSET 0x1fe -#define DOS_PBR_FSTYPE_OFFSET 0x36 +#define DOS_PBR_FSTYPE_OFFSET 0x52 #define DOS_PBR_MEDIA_TYPE_OFFSET 0x15 #define DOS_MBR 0 #define DOS_PBR 1 +#define MBR_MAGIC_BYTE0 0x55 +#define MBR_MAGIC_BYTE1 0xAA + + typedef struct dos_partition { unsigned char boot_ind; /* 0x80 - active */ unsigned char head; /* starting head */ diff --git a/disk/part_efi.c b/disk/part_efi.c new file mode 100644 index 0000000..134c5cc --- /dev/null +++ b/disk/part_efi.c @@ -0,0 +1,424 @@ +/* + * Copyright (C) 2008 RuggedCom, Inc. + * Richard Retanubun RuggedCom.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Problems with CFG_64BIT_LBA: + * + * struct disk_partition.start in include/part.h is sized as ulong. + * When CFG_64BIT_LBA is activated, lbaint_t changes from ulong to uint64_t. + * For now, it is cast back to ulong at assignment. + * + * This limits the maximum size of addressable storage to < 2 Terra Bytes + */ +#include +#include +#include +#include +#include "part_efi.h" + +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + defined(CONFIG_MMC) || \ + defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_EFI_PARTITION) + +/* Convert char[2] in little endian format to the host format integer + */ +static inline unsigned short le16_to_int(unsigned char *le16) +{ + return ((le16[1] << 8) + le16[0]); +} + +/* Convert char[4] in little endian format to the host format integer + */ +static inline unsigned long le32_to_int(unsigned char *le32) +{ + return ((le32[3] << 24) + (le32[2] << 16) + (le32[1] << 8) + le32[0]); +} + +/* Convert char[8] in little endian format to the host format integer + */ +static inline unsigned long long le64_to_int(unsigned char *le64) +{ + return (((unsigned long long)le64[7] << 56) + + ((unsigned long long)le64[6] << 48) + + ((unsigned long long)le64[5] << 40) + + ((unsigned long long)le64[4] << 32) + + ((unsigned long long)le64[3] << 24) + + ((unsigned long long)le64[2] << 16) + + ((unsigned long long)le64[1] << 8) + + (unsigned long long)le64[0]); +} + +/** + * efi_crc32() - EFI version of crc32 function + * @buf: buffer to calculate crc32 of + * @len - length of buf + * + * Description: Returns EFI-style CRC32 value for @buf + */ +static inline unsigned long efi_crc32(const void *buf, unsigned long len) +{ + return crc32(0, buf, len); +} + +/* + * Private function prototypes + */ + +static int pmbr_part_valid(struct partition *part); +static int is_pmbr_valid(legacy_mbr * mbr); + +static int is_gpt_valid(block_dev_desc_t * dev_desc, unsigned long long lba, + gpt_header * pgpt_head, gpt_entry ** pgpt_pte); + +static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc, + gpt_header * pgpt_head); + +static int is_pte_valid(gpt_entry * pte); + +/* + * Public Functions (include/part.h) + */ + +void print_part_efi(block_dev_desc_t * dev_desc) +{ + gpt_header gpt_head; + gpt_entry **pgpt_pte = NULL; + int i = 0; + + if (!dev_desc) { + printf("%s: Invalid Argument(s)\n", __FUNCTION__); + return; + } + /* This function validates AND fills in the GPT header and PTE */ + if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, + &(gpt_head), pgpt_pte) != 1) { + printf("%s: *** ERROR: Invalid GPT ***\n", __FUNCTION__); + return; + } + + debug("%s: gpt-entry at 0x%08X\n", __FUNCTION__, (unsigned int)*pgpt_pte); + + printf("Part Start LBA End LBA\n"); + for (i = 0; i < le32_to_int(gpt_head.num_partition_entries); i++) { + + if (is_pte_valid(&(*pgpt_pte)[i])) { + printf("%s%d 0x%llX 0x%llX\n", GPT_ENTRY_NAME, + (i + 1), + le64_to_int((*pgpt_pte)[i].starting_lba), + le64_to_int((*pgpt_pte)[i].ending_lba)); + } else { + break; /* Stop at the first non valid PTE */ + } + } + + /* Remember to free pte */ + if (*pgpt_pte != NULL) { + debug("%s: Freeing pgpt_pte\n", __FUNCTION__); + free(*pgpt_pte); + } + return; +} + +int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, + disk_partition_t * info) +{ + gpt_header gpt_head; + gpt_entry **pgpt_pte = NULL; + + /* "part" argument must be at least 1 */ + if (!dev_desc || !info || part < 1) { + printf("%s: Invalid Argument(s)\n", __FUNCTION__); + return -1; + } + + /* This function validates AND fills in the GPT header and PTE */ + if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, + &(gpt_head), pgpt_pte) != 1) { + printf("%s: *** ERROR: Invalid GPT ***\n", __FUNCTION__); + return -1; + } + + /* The ulong casting limits the maximum disk size to 2 TB */ + info->start = (ulong) le64_to_int((*pgpt_pte)[part - 1].starting_lba); + info->size = (ulong) le64_to_int((*pgpt_pte)[part - 1].ending_lba) - info->start; + info->blksz = GPT_BLOCK_SIZE; + + sprintf((char *)info->name, "%s%d\n", GPT_ENTRY_NAME, part); + sprintf((char *)info->type, "U-Boot"); + + debug("%s: start 0x%lX, size 0x%lX, name %s", __FUNCTION__, + info->start, info->size, info->name); + + /* Remember to free pte */ + if (*pgpt_pte != NULL) { + debug("%s: Freeing pgpt_pte\n", __FUNCTION__); + free(*pgpt_pte); + } + return 0; +} + +int test_part_efi(block_dev_desc_t * dev_desc) +{ + legacy_mbr legacymbr; + + /* Read legacy MBR from block 0 and validate it */ + if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) & legacymbr) != 1) + || (is_pmbr_valid(&legacymbr) != 1)) { + return -1; + } + return 0; +} + +/* + * Private functions + */ +/* + * pmbr_part_valid(): Check for EFI partition signature + * + * Returns: 1 if EFI GPT partition type is found. + */ +static int pmbr_part_valid(struct partition *part) +{ + if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT && + le32_to_int(part->start_sect) == 1UL) { + return 1; + } + + return 0; +} + +/* + * is_pmbr_valid(): test Protective MBR for validity + * + * Returns: 1 if PMBR is valid, 0 otherwise. + * Validity depends on two things: + * 1) MSDOS signature is in the last two bytes of the MBR + * 2) One partition of type 0xEE is found, checked by pmbr_part_valid() + */ +static int is_pmbr_valid(legacy_mbr * mbr) +{ + int i = 0; + + if (!mbr || le16_to_int(mbr->signature) != MSDOS_MBR_SIGNATURE) { + return 0; + } + + for (i = 0; i < 4; i++) { + if (pmbr_part_valid(&mbr->partition_record[i])) { + return 1; + } + } + return 0; +} + +/** + * is_gpt_valid() - tests one GPT header and PTEs for validity + * + * lba is the logical block address of the GPT header to test + * gpt is a GPT header ptr, filled on return. + * ptes is a PTEs ptr, filled on return. + * + * Description: returns 1 if valid, 0 on error. + * If valid, returns pointers to PTEs. + */ +static int is_gpt_valid(block_dev_desc_t * dev_desc, unsigned long long lba, + gpt_header * pgpt_head, gpt_entry ** pgpt_pte) +{ + unsigned char crc32_backup[4] = { 0 }; + unsigned long calc_crc32; + unsigned long long lastlba; + + if (!dev_desc || !pgpt_head) { + printf("%s: Invalid Argument(s)\n", __FUNCTION__); + return 0; + } + + /* Read GPT Header from device */ + if (dev_desc->block_read(dev_desc->dev, lba, 1, pgpt_head) != 1) { + printf("*** ERROR: Can't read GPT header ***\n"); + return 0; + } + + /* Check the GPT header signature */ + if (le64_to_int(pgpt_head->signature) != GPT_HEADER_SIGNATURE) { + printf("GUID Partition Table Header signature is wrong:" + "0x%llX != 0x%llX\n", + (unsigned long long)le64_to_int(pgpt_head->signature), + (unsigned long long)GPT_HEADER_SIGNATURE); + return 0; + } + + /* Check the GUID Partition Table CRC */ + memcpy(crc32_backup, pgpt_head->header_crc32, sizeof(crc32_backup)); + memset(pgpt_head->header_crc32, 0, sizeof(pgpt_head->header_crc32)); + + calc_crc32 = efi_crc32((const unsigned char *)pgpt_head, + le32_to_int(pgpt_head->header_size)); + + memcpy(pgpt_head->header_crc32, crc32_backup, sizeof(crc32_backup)); + + if (calc_crc32 != le32_to_int(crc32_backup)) { + printf("GUID Partition Table Header CRC is wrong:" + "0x%08lX != 0x%08lX\n", + le32_to_int(crc32_backup), calc_crc32); + return 0; + } + + /* Check that the my_lba entry points to the LBA that contains the GPT */ + if (le64_to_int(pgpt_head->my_lba) != lba) { + printf("GPT: my_lba incorrect: %llX != %llX\n", + (unsigned long long)le64_to_int(pgpt_head->my_lba), + (unsigned long long)lba); + return 0; + } + + /* Check the first_usable_lba and last_usable_lba are within the disk. */ + lastlba = (unsigned long long)dev_desc->lba; + if (le64_to_int(pgpt_head->first_usable_lba) > lastlba) { + printf("GPT: first_usable_lba incorrect: %llX > %llX\n", + le64_to_int(pgpt_head->first_usable_lba), lastlba); + return 0; + } + if (le64_to_int(pgpt_head->last_usable_lba) > lastlba) { + printf("GPT: last_usable_lba incorrect: %llX > %llX\n", + le64_to_int(pgpt_head->last_usable_lba), lastlba); + return 0; + } + + debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %llX\n", + le64_to_int(pgpt_head->first_usable_lba), + le64_to_int(pgpt_head->last_usable_lba), lastlba); + + /* Read and allocate Partition Table Entries */ + *pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head); + if (*pgpt_pte == NULL) { + printf("GPT: Failed to allocate memory for PTE\n"); + return 0; + } + + /* Check the GUID Partition Table Entry Array CRC */ + calc_crc32 = efi_crc32((const unsigned char *)*pgpt_pte, + le32_to_int(pgpt_head->num_partition_entries) * + le32_to_int(pgpt_head->sizeof_partition_entry)); + + if (calc_crc32 != le32_to_int(pgpt_head->partition_entry_array_crc32)) { + printf("GUID Partition Table Entry Array CRC is wrong:" + "0x%08lX != 0x%08lX\n", + le32_to_int(pgpt_head->partition_entry_array_crc32), + calc_crc32); + + if (*pgpt_pte != NULL) { + free(*pgpt_pte); + } + return 0; + } + + /* We're done, all's well */ + return 1; +} + +/** + * alloc_read_gpt_entries(): reads partition entries from disk + * @dev_desc + * @gpt - GPT header + * + * Description: Returns ptes on success, NULL on error. + * Allocates space for PTEs based on information found in @gpt. + * Notes: remember to free pte when you're done! + */ +static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc, + gpt_header * pgpt_head) +{ + size_t count = 0; + gpt_entry *pte = NULL; + + if (!dev_desc || !pgpt_head) { + printf("%s: Invalid Argument(s)\n", __FUNCTION__); + return NULL; + } + + count = le32_to_int(pgpt_head->num_partition_entries) * + le32_to_int(pgpt_head->sizeof_partition_entry); + + debug("%s: count = %lu * %lu = %u\n", __FUNCTION__, + le32_to_int(pgpt_head->num_partition_entries), + le32_to_int(pgpt_head->sizeof_partition_entry), count); + + /* Allocate memory for PTE, remember to FREE */ + if (count != 0) { + pte = malloc(count); + } + + if (count == 0 || pte == NULL) { + printf("%s: ERROR: Can't allocate 0x%X bytes for GPT Entries\n", + __FUNCTION__, count); + return NULL; + } + + /* Read GPT Entries from device */ + if (dev_desc->block_read (dev_desc->dev, + (unsigned long)le64_to_int(pgpt_head->partition_entry_lba), + (lbaint_t) (count / GPT_BLOCK_SIZE), pte) + != (count / GPT_BLOCK_SIZE)) { + + printf("*** ERROR: Can't read GPT Entries ***\n"); + free(pte); + return NULL; + } + return pte; +} + +/** + * is_pte_valid(): validates a single Partition Table Entry + * @gpt_entry - Pointer to a single Partition Table Entry + * + * Description: returns 1 if valid, 0 on error. + */ +static int is_pte_valid(gpt_entry * pte) +{ + efi_guid_t unused_guid; + + if (!pte) { + printf("%s: Invalid Argument(s)\n", __FUNCTION__); + return 0; + } + + /* Only one validation for now: + * The GUID Partition Type != Unused Entry (ALL-ZERO) + */ + memset(unused_guid.b, 0, sizeof(unused_guid.b)); + + if (memcmp(pte->partition_type_guid.b, unused_guid.b, + sizeof(unused_guid.b)) == 0) { + + debug("%s: Found an unused PTE GUID at 0x%08X\n", __FUNCTION__, + (unsigned int)pte); + + return 0; + } else { + return 1; + } +} +#endif diff --git a/disk/part_efi.h b/disk/part_efi.h new file mode 100644 index 0000000..29d9406 --- /dev/null +++ b/disk/part_efi.h @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2008 RuggedCom, Inc. + * Richard Retanubun RuggedCom.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * See also linux/fs/partitions/efi.h + * + * EFI GUID Partition Table + * Per Intel EFI Specification v1.02 + * http://developer.intel.com/technology/efi/efi.htm +*/ + +#ifndef _DISK_PART_EFI_H +#define _DISK_PART_EFI_H + +#define MSDOS_MBR_SIGNATURE 0xAA55 +#define EFI_PMBR_OSTYPE_EFI 0xEF +#define EFI_PMBR_OSTYPE_EFI_GPT 0xEE + +#define GPT_BLOCK_SIZE 512 +#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL +#define GPT_HEADER_REVISION_V1 0x00010000 +#define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL +#define GPT_ENTRY_NAME "gpt" + +#define EFI_GUID(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7) \ +((efi_guid_t) \ +{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ + (b) & 0xff, ((b) >> 8) & 0xff, \ + (c) & 0xff, ((c) >> 8) & 0xff, \ + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }}) + +#define PARTITION_SYSTEM_GUID \ + EFI_GUID( 0xC12A7328, 0xF81F, 0x11d2, \ + 0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B) +#define LEGACY_MBR_PARTITION_GUID \ + EFI_GUID( 0x024DEE41, 0x33E7, 0x11d3, \ + 0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F) +#define PARTITION_MSFT_RESERVED_GUID \ + EFI_GUID( 0xE3C9E316, 0x0B5C, 0x4DB8, \ + 0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE) +#define PARTITION_BASIC_DATA_GUID \ + EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \ + 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7) +#define PARTITION_LINUX_RAID_GUID \ + EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \ + 0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e) +#define PARTITION_LINUX_SWAP_GUID \ + EFI_GUID( 0x0657fd6d, 0xa4ab, 0x43c4, \ + 0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f) +#define PARTITION_LINUX_LVM_GUID \ + EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \ + 0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28) + +/* linux/include/efi.h */ +typedef unsigned short efi_char16_t; + +typedef struct { + unsigned char b[16]; +} efi_guid_t; + +/* based on linux/include/genhd.h */ +struct partition { + unsigned char boot_ind; /* 0x80 - active */ + unsigned char head; /* starting head */ + unsigned char sector; /* starting sector */ + unsigned char cyl; /* starting cylinder */ + unsigned char sys_ind; /* What partition type */ + unsigned char end_head; /* end head */ + unsigned char end_sector; /* end sector */ + unsigned char end_cyl; /* end cylinder */ + unsigned char start_sect[4]; /* starting sector counting from 0 */ + unsigned char nr_sects[4]; /* nr of sectors in partition */ +} __attribute__ ((packed)); + +/* based on linux/fs/partitions/efi.h */ +typedef struct _gpt_header { + unsigned char signature[8]; + unsigned char revision[4]; + unsigned char header_size[4]; + unsigned char header_crc32[4]; + unsigned char reserved1[4]; + unsigned char my_lba[8]; + unsigned char alternate_lba[8]; + unsigned char first_usable_lba[8]; + unsigned char last_usable_lba[8]; + efi_guid_t disk_guid; + unsigned char partition_entry_lba[8]; + unsigned char num_partition_entries[4]; + unsigned char sizeof_partition_entry[4]; + unsigned char partition_entry_array_crc32[4]; + unsigned char reserved2[GPT_BLOCK_SIZE - 92]; +} __attribute__ ((packed)) gpt_header; + +typedef struct _gpt_entry_attributes { + unsigned long long required_to_function:1; + unsigned long long reserved:47; + unsigned long long type_guid_specific:16; +} __attribute__ ((packed)) gpt_entry_attributes; + +typedef struct _gpt_entry { + efi_guid_t partition_type_guid; + efi_guid_t unique_partition_guid; + unsigned char starting_lba[8]; + unsigned char ending_lba[8]; + gpt_entry_attributes attributes; + efi_char16_t partition_name[72 / sizeof(efi_char16_t)]; +} +__attribute__ ((packed)) gpt_entry; + +typedef struct _legacy_mbr { + unsigned char boot_code[440]; + unsigned char unique_mbr_signature[4]; + unsigned char unknown[2]; + struct partition partition_record[4]; + unsigned char signature[2]; +} __attribute__ ((packed)) legacy_mbr; + +#endif /* _DISK_PART_EFI_H */ diff --git a/do_mvlsxh_2_bymarvell.txt b/do_mvlsxh_2_bymarvell.txt new file mode 100644 index 0000000..168db82 --- /dev/null +++ b/do_mvlsxh_2_bymarvell.txt @@ -0,0 +1,33 @@ +0xFFD100e0 0x1b1b9b9b +0xFFD20134 0xbbbbbbbb +0xFFD20138 0x00bbbbbb +0xFFD20154 0x00000200 +0xFFD2014C 0x00001C00 +0xFFD20148 0x00000001 +0xFFD01500 0x00000000 +0xFFD01504 0x0FFFFFF1 +0xFFD01508 0x00000000 +0xFFD0150C 0x00000000 +0xFFD01510 0x00000000 +0xFFD01514 0x00000000 +0xFFD01518 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01400 0x43000618 +0xFFD01404 0x39543010 +0xFFD01408 0x22125441 +0xFFD0140C 0x00000832 +0xFFD01410 0x0000000C +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000652 +0xFFD01420 0x00000006 +0xFFD01424 0x0000F1FF +0xFFD01428 0x00085520 +0xFFD0147C 0x00008552 +0xFFD01494 0x00010000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E40F +0xFFD01480 0x00000001 +0x0 0x0 + + diff --git a/do_mvlsxh_2_bymarvell_512mb.txt b/do_mvlsxh_2_bymarvell_512mb.txt new file mode 100644 index 0000000..13de491 --- /dev/null +++ b/do_mvlsxh_2_bymarvell_512mb.txt @@ -0,0 +1,33 @@ +0xFFD100e0 0x1b1b9b9b +0xFFD20134 0xbbbbbbbb +0xFFD20138 0x00bbbbbb +0xFFD20154 0x00000200 +0xFFD2014C 0x00001C00 +0xFFD20148 0x00000001 +0xFFD01500 0x00000000 +0xFFD01504 0x07FFFFF1 +0xFFD01508 0x00000000 +0xFFD0150C 0x00000000 +0xFFD01510 0x00000000 +0xFFD01514 0x00000000 +0xFFD01518 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01400 0x43000618 +0xFFD01404 0x39543010 +0xFFD01408 0x22125441 +0xFFD0140C 0x00000832 +0xFFD01410 0x00000004 +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000652 +0xFFD01420 0x00000006 +0xFFD01424 0x0000F1FF +0xFFD01428 0x00085520 +0xFFD0147C 0x00008552 +0xFFD01494 0x00010000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E40F +0xFFD01480 0x00000001 +0x0 0x0 + + diff --git a/dramregs_200db619x_A.txt b/dramregs_200db619x_A.txt new file mode 100644 index 0000000..85bd024 --- /dev/null +++ b/dramregs_200db619x_A.txt @@ -0,0 +1,24 @@ +0xFFD100e0 0x1b1b1b9b +0xFFD01400 0x43000618 +0xFFD01404 0x34143000 +0xFFD01408 0x11012227 +0xFFD0140C 0x00000819 +0xFFD01410 0x000000cc +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000632 +0xFFD01420 0x00000040 +0xFFD01424 0x0000F07F +0xFFD01504 0x0FFFFFF1 +0xFFD01508 0x10000000 +0xFFD0150C 0x0FFFFFF5 +0xFFD01514 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01494 0x00030000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E803 +0xFFD01480 0x00000001 +0xFFD01620 0x00465000 +0xFFD20134 0x66666666 +0xFFD20138 0x66666666 +0x0 0x0 diff --git a/dramregs_200db6280_A.txt b/dramregs_200db6280_A.txt new file mode 100644 index 0000000..607bfd2 --- /dev/null +++ b/dramregs_200db6280_A.txt @@ -0,0 +1,39 @@ +0xFFD014C0 0x80010000 +0xFFD014C0 0x800032CB +0xFFD014C0 0x800032CB +0xFFD014C0 0x000032CB +0xFFD014C4 0x80010000 +0xFFD014C4 0x800032CB +0xFFD014C4 0x800032CB +0xFFD014C4 0x000032CB +0xFFD014C8 0x80010000 +0xFFD014C8 0x800032CB +0xFFD014C8 0x800032CB +0xFFD014C8 0x000032CB +0xFFD100e0 0x1b1b1b9b +0xFFD01400 0x43000618 +0xFFD01404 0x35243000 +0xFFD01408 0x11012227 +0xFFD0140C 0x00000819 +0xFFD01410 0x000000cc +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000632 +0xFFD01420 0x00000040 +0xFFD01424 0x0000F07F +0xFFD01504 0x0FFFFFF1 +0xFFD01508 0x10000000 +0xFFD0150C 0x00000000 +0xFFD01514 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01494 0x00010000 +0xFFD01498 0x00000000 +0xFFD0149C 0x00008801 +0xFFD01400 0x03000618 +0xFFD01400 0x43000618 +0xFFD01480 0x00000001 +0xFFD20134 0x66666666 +0xFFD20138 0x66666666 +0xFFD01620 0x00380000 +0x0 0x0 + diff --git a/dramregs_200db_A.txt b/dramregs_200db_A.txt new file mode 100644 index 0000000..6707ba9 --- /dev/null +++ b/dramregs_200db_A.txt @@ -0,0 +1,24 @@ +0xFFD100e0 0x1b1b1b9b +0xFFD01400 0x43000618 +0xFFD01404 0x34143000 +0xFFD01408 0x11012227 +0xFFD0140C 0x00000819 +0xFFD01410 0x000000cc +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000632 +0xFFD01420 0x00000040 +0xFFD01424 0x0000F07F +0xFFD01504 0x0FFFFFF1 +0xFFD01508 0x10000000 +0xFFD0150C 0x0FFFFFF5 +0xFFD01514 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01494 0x00030000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E803 +0xFFD01480 0x00000001 +0xFFD20134 0x66666666 +0xFFD20138 0x66666666 +0xFFD01620 0x005B7000 +0x0 0x0 diff --git a/dramregs_200pcac_A.txt b/dramregs_200pcac_A.txt new file mode 100644 index 0000000..d2394f5 --- /dev/null +++ b/dramregs_200pcac_A.txt @@ -0,0 +1,23 @@ +0xFFD100e0 0x1b1b1b9b +0xFFD01400 0x43000a25 +0xFFD01404 0x38543000 +0xFFD01408 0x2202444e +0xFFD0140C 0x00000822 +0xFFD01410 0x000000cd +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000652 +0xFFD01420 0x00000004 +0xFFD01424 0x0000F07F +0xFFD01504 0x07FFFFF1 +0xFFD01508 0x00000000 +0xFFD0150C 0x00000000 +0xFFD01514 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01494 0x00120012 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E40F +0xFFD01480 0x00000001 +0xFFD20134 0x66666666 +0xFFD20138 0x66666666 +0x0 0x0 diff --git a/dramregs_200rd_A.txt b/dramregs_200rd_A.txt new file mode 100644 index 0000000..b2e7ee4 --- /dev/null +++ b/dramregs_200rd_A.txt @@ -0,0 +1,24 @@ +0xFFD100e0 0x1b1b1b9b +0xFFD01400 0x43000618 +0xFFD01404 0x34143000 +0xFFD01408 0x11012227 +0xFFD0140C 0x00000819 +0xFFD01410 0x000000c9 +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000632 +0xFFD01420 0x00000006 +0xFFD01424 0x0000F07F +0xFFD01504 0x03FFFFF1 +0xFFD01508 0x00000000 +0xFFD0150C 0x00000000 +0xFFD01514 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01494 0x00010000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E403 +0xFFD01480 0x00000001 +0xFFD01620 0x00465000 +0xFFD20134 0x66666666 +0xFFD20138 0x66666666 +0x0 0x0 diff --git a/dramregs_300wxl_A.txt b/dramregs_300wxl_A.txt new file mode 100644 index 0000000..e5c935f --- /dev/null +++ b/dramregs_300wxl_A.txt @@ -0,0 +1,25 @@ +0xFFD100e0 0x1b1b9b9b +0xFFD20134 0xbbbbbbbb +0xFFD20138 0x00bbbbbb +0xFFD01400 0x43000618 +0xFFD01404 0x39543000 +0xFFD01408 0x3302444f +0xFFD0140C 0x00000823 +0xFFD01410 0x00000099 +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000652 +0xFFD01420 0x00000042 +0xFFD01424 0x0000F1FF +0xFFD01504 0x03FFFFF1 +0xFFD01508 0x04000000 +0xFFD0150C 0x03FFFFF5 +0xFFD01514 0x00000000 +0xFFD0151C 0x00000000 +0xFFD0147C 0x00008552 +0xFFD01494 0x003C0000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E80F +0xFFD01480 0x00000001 +0x0 0x0 + diff --git a/dramregs_300xl_A.txt b/dramregs_300xl_A.txt new file mode 100644 index 0000000..c4ab0e8 --- /dev/null +++ b/dramregs_300xl_A.txt @@ -0,0 +1,24 @@ +0xFFD100e0 0x1b1b1b9b +0xFFD20134 0xbbbbbbbb +0xFFD20138 0x00bbbbbb +0xFFD01400 0x43000618 +0xFFD01404 0x39543000 +0xFFD01408 0x3302444f +0xFFD0140C 0x00000823 +0xFFD01410 0x00000009 +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000652 +0xFFD01420 0x00000042 +0xFFD01424 0x0000F1FF +0xFFD01504 0x03FFFFF1 +0xFFD01508 0x00000000 +0xFFD0150C 0x00000000 +0xFFD01514 0x00000000 +0xFFD0151C 0x00000000 +0xFFD0147C 0x00008552 +0xFFD01494 0x003C0000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E80F +0xFFD01480 0x00000001 +0x0 0x0 diff --git a/dramregs_400db_A.txt b/dramregs_400db_A.txt new file mode 100644 index 0000000..a316d21 --- /dev/null +++ b/dramregs_400db_A.txt @@ -0,0 +1,26 @@ +0xFFD100e0 0x1b1b1b9b +0xFFD01400 0x43010c30 +0xFFD01404 0x37543000 +0xFFD01408 0x22125451 +0xFFD0140C 0x00000a33 +0xFFD01410 0x000000cc +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000652 +0xFFD01420 0x00000040 +0xFFD01424 0x0000F17F +0xFFD01428 0x00085520 +0xFFD0147C 0x00008552 +0xFFD01504 0x0FFFFFF1 +0xFFD01508 0x10000000 +0xFFD0150C 0x0FFFFFF5 +0xFFD01514 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01494 0x00030000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E803 +0xFFD01480 0x00000001 +0xFFD20134 0x66666666 +0xFFD20138 0x66666666 +0x0 0x0 + diff --git a/dramregs_400mvlsxh_A.txt b/dramregs_400mvlsxh_A.txt new file mode 100644 index 0000000..ba94422 --- /dev/null +++ b/dramregs_400mvlsxh_A.txt @@ -0,0 +1,31 @@ +0xFFD100e0 0x1b1b9b9b +0xFFD20134 0xbbbbbbbb +0xFFD20138 0x00bbbbbb +0xFFD01500 0x00000000 +0xFFD01504 0x0FFFFFF1 +0xFFD01508 0x00000000 +0xFFD0150C 0x00000000 +0xFFD01510 0x00000000 +0xFFD01514 0x00000000 +0xFFD01518 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01400 0x43000618 +0xFFD01404 0x39543010 +0xFFD01408 0x22125441 +0xFFD0140C 0x00000832 +0xFFD01410 0x0000000C +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000652 +0xFFD01420 0x00000006 +0xFFD01424 0x0000F17F +0xFFD01428 0x00085520 +0xFFD0142C 0x00000000 +0xFFD0147C 0x00008552 +0xFFD01480 0x00000001 +0xFFD01494 0x00010000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E80F +0x0 0x0 + + diff --git a/dramregs_400mvlsxh_ICE.txt b/dramregs_400mvlsxh_ICE.txt new file mode 100644 index 0000000..fc8a731 --- /dev/null +++ b/dramregs_400mvlsxh_ICE.txt @@ -0,0 +1,33 @@ +0xFFD100e0 0x1b1b9b9b +0xFFD20134 0xbbbbbbbb +0xFFD20138 0x00bbbbbb +0xFFD20154 0x00000200 +0xFFD2014C 0x00001C00 +0xFFD20148 0x00000001 +0xFFD01500 0x00000000 +0xFFD01504 0x0FFFFFF1 +0xFFD01508 0x00000000 +0xFFD0150C 0x00000000 +0xFFD01510 0x00000000 +0xFFD01514 0x00000000 +0xFFD01518 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01400 0x43000618 +0xFFD01404 0x39543000 +0xFFD01408 0x22125441 +0xFFD0140C 0x00000832 +0xFFD01410 0x0000000C +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000652 +0xFFD01420 0x00000006 +0xFFD01424 0x0000F1FF +0xFFD01428 0x00085520 +0xFFD0147C 0x00008552 +0xFFD01494 0x00010000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E40F +0xFFD01480 0x00000001 +0x0 0x0 + + diff --git a/dramregs_400rd_A.txt b/dramregs_400rd_A.txt new file mode 100644 index 0000000..de16a71 --- /dev/null +++ b/dramregs_400rd_A.txt @@ -0,0 +1,26 @@ +0xFFD100e0 0x1b1b1b9b +0xFFD01400 0x43010c30 +0xFFD01404 0x37543000 +0xFFD01408 0x22125451 +0xFFD0140C 0x00000a33 +0xFFD01410 0x000000cc +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000652 +0xFFD01420 0x00000004 +0xFFD01424 0x0000F17F +0xFFD01428 0x00085520 +0xFFD0147C 0x00008552 +0xFFD01504 0x0FFFFFF1 +0xFFD01508 0x10000000 +0xFFD0150C 0x0FFFFFF5 +0xFFD01514 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01494 0x00120012 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E403 +0xFFD01480 0x00000001 +0xFFD20134 0x66666666 +0xFFD20138 0x66666666 +0x0 0x0 + diff --git a/dramregs_533ddr3db_A.txt b/dramregs_533ddr3db_A.txt new file mode 100644 index 0000000..549b3da --- /dev/null +++ b/dramregs_533ddr3db_A.txt @@ -0,0 +1,33 @@ +0xFFD100e0 0x1b1b1b9b +0xFFD01400 0x4301503E +0xFFD01404 0xB9843000 +0xFFD01408 0x33137773 +0xFFD0140C 0x16000C3A +0xFFD01410 0x040F00cc +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000672 +0xFFD01420 0x00000040 +0xFFD01424 0x0000F14F +0xFFD01428 0x000C6720 +0xFFD0147C 0x0000B571 +0xFFD01504 0x0FFFFFF1 +0xFFD01508 0x10000000 +0xFFD0150C 0x0FFFFFF5 +0xFFD01514 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01494 0x00110000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E803 +0xFFD015D0 0x00000630 +0xFFD015D4 0x00000046 +0xFFD015D8 0x00000008 +0xFFD015DC 0x00000000 +0xFFD015E0 0x00000023 +0xFFD015E4 0x00203C18 +0xFFD01620 0x00680000 +0xFFD01480 0x00000001 +0xFFD20134 0x66666666 +0xFFD20138 0x66666666 +0x0 0x0 + diff --git a/dramregs_533ddr3db_A_buf.txt b/dramregs_533ddr3db_A_buf.txt new file mode 100644 index 0000000..8094cb0 --- /dev/null +++ b/dramregs_533ddr3db_A_buf.txt @@ -0,0 +1,35 @@ +0xFFD100e0 0x1b1b1b9b +0xFFD01400 0x4301503E +0xFFD01404 0xB9843000 +0xFFD01408 0x33137773 +0xFFD0140C 0x16000C3A +0xFFD01410 0x040F00cc +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000672 +0xFFD01420 0x00000040 +0xFFD01424 0x0000F14F +0xFFD01428 0x000C6720 +0xFFD0147C 0x0000B571 +0xFFD01500 0x00000000 +0xFFD01504 0x0FFFFFF1 +0xFFD01508 0x00000000 +0xFFD0150C 0x00000000 +0xFFD01514 0x00000000 +0xFFD01518 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01494 0x00110000 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E803 +0xFFD015D0 0x00000630 +0xFFD015D4 0x00000044 +0xFFD015D8 0x00000008 +0xFFD015DC 0x00000000 +0xFFD015E0 0x00000023 +0xFFD015E4 0x00203C18 +0xFFD01620 0x0068A800 +0xFFD01480 0x00000001 +0xFFD20134 0x66666666 +0xFFD20138 0x66666666 +0x0 0x0 + diff --git a/dramregs_customer_A.txt b/dramregs_customer_A.txt new file mode 100644 index 0000000..de16a71 --- /dev/null +++ b/dramregs_customer_A.txt @@ -0,0 +1,26 @@ +0xFFD100e0 0x1b1b1b9b +0xFFD01400 0x43010c30 +0xFFD01404 0x37543000 +0xFFD01408 0x22125451 +0xFFD0140C 0x00000a33 +0xFFD01410 0x000000cc +0xFFD01414 0x00000000 +0xFFD01418 0x00000000 +0xFFD0141C 0x00000652 +0xFFD01420 0x00000004 +0xFFD01424 0x0000F17F +0xFFD01428 0x00085520 +0xFFD0147C 0x00008552 +0xFFD01504 0x0FFFFFF1 +0xFFD01508 0x10000000 +0xFFD0150C 0x0FFFFFF5 +0xFFD01514 0x00000000 +0xFFD0151C 0x00000000 +0xFFD01494 0x00120012 +0xFFD01498 0x00000000 +0xFFD0149C 0x0000E403 +0xFFD01480 0x00000001 +0xFFD20134 0x66666666 +0xFFD20138 0x66666666 +0x0 0x0 + diff --git a/dramregs_lsxlv2_128mb.txt b/dramregs_lsxlv2_128mb.txt new file mode 100644 index 0000000..8faa9db --- /dev/null +++ b/dramregs_lsxlv2_128mb.txt @@ -0,0 +1,23 @@ +0xffd01400 0x43000618 +0xffd01404 0x34143000 +0xffd01408 0x11012227 +0xffd0140c 0x00000819 +0xffd01410 0x000000cd +0xffd01414 0x00000000 +0xffd01418 0x00000000 +0xffd0141c 0x00000632 +0xffd01420 0x00000006 +0xffd01424 0x0000f07f +0xffd01504 0x07fffff1 +0xffd01508 0x00000000 +0xffd0150c 0x00000000 +0xffd01514 0x00000000 +0xffd0151c 0x00000000 +0xffd01494 0x00010000 +0xffd01498 0x00000000 +0xffd0149c 0x0000e403 +0xffd01480 0x00000001 +0xffd01620 0x00465000 +0xffd20134 0x66666666 +0xffd20138 0x66666666 +0x0 0x0 diff --git a/dramregs_lsxlv2_64mb.txt b/dramregs_lsxlv2_64mb.txt new file mode 100644 index 0000000..322f9d4 --- /dev/null +++ b/dramregs_lsxlv2_64mb.txt @@ -0,0 +1,23 @@ +0xffd01400 0x43000618 +0xffd01404 0x34143000 +0xffd01408 0x11012227 +0xffd0140c 0x00000819 +0xffd01410 0x000000c9 +0xffd01414 0x00000000 +0xffd01418 0x00000000 +0xffd0141c 0x00000632 +0xffd01420 0x00000006 +0xffd01424 0x0000f07f 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +usbdcore_omap1510.o: usbdcore_omap1510.c \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +usbtty.o: usbtty.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +videomodes.o: videomodes.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + videomodes.h +w83c553f.o: w83c553f.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +ks8695eth.o: ks8695eth.c diff --git a/drivers/Makefile b/drivers/Makefile index e6176ed..549182a 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -38,13 +38,13 @@ OBJS = 3c589.o 5701rls.o ali512x.o \ omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \ pcnet.o plb2800_eth.o \ ps2ser.o ps2mult.o pc_keyb.o \ - rtl8019.o rtl8139.o rtl8169.o \ + rtl8029.o rtl8019.o rtl8139.o rtl8169.o \ s3c4510b_eth.o s3c4510b_uart.o \ sed13806.o sed156x.o \ serial.o serial_max3100.o \ serial_pl010.o serial_pl011.o serial_xuartlite.o \ sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ - status_led.o sym53c8xx.o \ + status_led.o sym53c8xx.o ahci.o\ ti_pci1410a.o tigon3.o tsec.o \ usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ videomodes.o w83c553f.o \ diff --git a/drivers/ahci.c b/drivers/ahci.c new file mode 100644 index 0000000..fb7867f --- /dev/null +++ b/drivers/ahci.c @@ -0,0 +1,760 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Author: Jason Jin + * Zhang Wei + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference on libata and ahci drvier in kernel + * + */ +/* #define DEBUG */ +#include + +#ifdef CONFIG_SCSI_AHCI + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct ahci_probe_ent *probe_ent = NULL; +hd_driveid_t *ataid[AHCI_MAX_PORTS]; + +#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) + + +static inline u32 ahci_port_base(u32 base, u32 port) +{ + return base + 0x100 + (port * 0x80); +} + + +static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, + unsigned int port_idx) +{ + base = ahci_port_base(base, port_idx); + + port->cmd_addr = base; + port->scr_addr = base + PORT_SCR; +} + + +#define msleep(a) udelay(a * 1000) +#define ssleep(a) msleep(a * 1000) + +static int waiting_for_cmd_completed(volatile u8 *offset, + int timeout_msec, + u32 sign) +{ + int i; + u32 status; + + for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) + msleep(1); + + return (i < timeout_msec) ? 0 : -1; +} + + +static int ahci_host_init(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + u32 tmp, cap_save; + u16 tmp16; + int i, j; + volatile u8 *port_mmio; + unsigned short vendor; + + cap_save = readl(mmio + HOST_CAP); + cap_save &= ((1 << 28) | (1 << 17)); + cap_save |= (1 << 27); + + /* global controller reset */ + tmp = readl(mmio + HOST_CTL); + if ((tmp & HOST_RESET) == 0) + writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); + + /* reset must complete within 1 second, or + * the hardware should be considered fried. + */ + ssleep(1); + + tmp = readl(mmio + HOST_CTL); + if (tmp & HOST_RESET) { + debug("controller reset failed (0x%x) addr (0x%x) \n", tmp, (mmio + HOST_CTL)); + return -1; + } + + writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); + writel(cap_save, mmio + HOST_CAP); + writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); + + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + + if (vendor == PCI_VENDOR_ID_INTEL) { + u16 tmp16; + pci_read_config_word(pdev, 0x92, &tmp16); + tmp16 |= 0xf; + pci_write_config_word(pdev, 0x92, tmp16); + } + + probe_ent->cap = readl(mmio + HOST_CAP); + probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); + probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; + + debug("cap 0x%x port_map 0x%x n_ports %d\n", + probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); + + for (i = 0; i < probe_ent->n_ports; i++) { + probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); + port_mmio = (u8 *) probe_ent->port[i].port_mmio; + ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); + + /* make sure port is not active */ + tmp = readl(port_mmio + PORT_CMD); + if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START)) { + tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | + PORT_CMD_FIS_RX | PORT_CMD_START); + writel_with_flush(tmp, port_mmio + PORT_CMD); + + /* spec says 500 msecs for each bit, so + * this is slightly incorrect. + */ + msleep(500); + } + + /* writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); Yotam */ + + j = 0; + while (j < 100) { + msleep(10); + tmp = readl(port_mmio + PORT_SCR_STAT); + if ((tmp & 0xf) == 0x3) + break; + j++; + } + + tmp = readl(port_mmio + PORT_SCR_ERR); + debug("PORT_SCR_ERR 0x%x\n", tmp); + writel(tmp, port_mmio + PORT_SCR_ERR); + + /* ack any pending irq events for this port */ + tmp = readl(port_mmio + PORT_IRQ_STAT); + debug("PORT_IRQ_STAT 0x%x\n", tmp); + if (tmp) + writel(tmp, port_mmio + PORT_IRQ_STAT); + + writel(1 << i, mmio + HOST_IRQ_STAT); + + /* set irq mask (enables interrupts) */ + /* writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); yotam */ + + /*register linkup ports */ + tmp = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: 0x%x\n", i, tmp); + if ((tmp & 0xf) == 0x03) + probe_ent->link_port_map |= (0x01 << i); + } + + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + /* writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); yotam */ + tmp = readl(mmio + HOST_CTL); + debug("HOST_CTL 0x%x\n", tmp); + + pci_read_config_word(pdev, PCI_COMMAND, &tmp16); + tmp |= PCI_COMMAND_MASTER; + pci_write_config_word(pdev, PCI_COMMAND, tmp16); + + return 0; +} + + +static void ahci_print_info(struct ahci_probe_ent *probe_ent) +{ + pci_dev_t pdev = probe_ent->dev; + volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + u32 vers, cap, impl, speed; + const char *speed_s; + u16 cc; + const char *scc_s; + + vers = readl(mmio + HOST_VERSION); + cap = probe_ent->cap; + impl = probe_ent->port_map; + + speed = (cap >> 20) & 0xf; + if (speed == 1) + speed_s = "1.5"; + else if (speed == 2) + speed_s = "3"; + else + speed_s = "?"; + + pci_read_config_word(pdev, 0x0a, &cc); + if (cc == 0x0101) + scc_s = "IDE"; + else if (cc == 0x0106) + scc_s = "SATA"; + else if (cc == 0x0104) + scc_s = "RAID"; + else + scc_s = "unknown"; + + printf("AHCI %02x%02x.%02x%02x " + "%u slots %u ports %s Gbps 0x%x impl %s mode\n", + (vers >> 24) & 0xff, + (vers >> 16) & 0xff, + (vers >> 8) & 0xff, + vers & 0xff, + ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); + + printf("flags: " + "%s%s%s%s%s%s" + "%s%s%s%s%s%s%s\n", + cap & (1 << 31) ? "64bit " : "", + cap & (1 << 30) ? "ncq " : "", + cap & (1 << 28) ? "ilck " : "", + cap & (1 << 27) ? "stag " : "", + cap & (1 << 26) ? "pm " : "", + cap & (1 << 25) ? "led " : "", + cap & (1 << 24) ? "clo " : "", + cap & (1 << 19) ? "nz " : "", + cap & (1 << 18) ? "only " : "", + cap & (1 << 17) ? "pmp " : "", + cap & (1 << 15) ? "pio " : "", + cap & (1 << 14) ? "slum " : "", + cap & (1 << 13) ? "part " : ""); +} + +#if (defined(CONFIG_MARVELL) && defined(__ARM__)) +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)pdev, a) +#define phys_to_bus(a) (a) +#else +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)pdev, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)pdev, a) +#endif + +static int ahci_init_one(pci_dev_t pdev) +{ + u32 iobase, vendor, device, rmw; + int rc; + + memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); + + probe_ent = malloc(sizeof(probe_ent)); + memset(probe_ent, 0, sizeof(probe_ent)); + probe_ent->dev = pdev; + + pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase); + iobase &= ~0xf; + + probe_ent->host_flags = ATA_FLAG_SATA + | ATA_FLAG_NO_LEGACY + | ATA_FLAG_MMIO + | ATA_FLAG_PIO_DMA + | ATA_FLAG_NO_ATAPI; + probe_ent->pio_mask = 0x1f; + probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ + + probe_ent->mmio_base = bus_to_phys (iobase); + + /* Take from kernel: + * JMicron-specific fixup: + * make sure we're in AHCI mode + */ + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + if (vendor == 0x197b) + pci_write_config_byte(pdev, 0x41, 0xa1); + + /* Take from kernel: + * Marvell specific fixup: + * Change SATA phy to scontroller mode + */ +/* + pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); + printf ("ahci_match : vendor 0x%x\n",vendor); + if (vendor == 0x11ab) + { + pci_read_config_word(pdev, PCI_DEVICE_ID, &device); + device &= 0xffff; + printf ("ahci_match : device 0x%x\n",device); + + if ((device == 0x6121) || (device == 0x6145)) + { + printf ("ahci_match : Switching SATA phy to be controlled by Scontrol\n"); + pci_read_config_word(pdev, PCI_CB_SUBSYSTEM_VENDOR_ID, &rmw); + printf ("ahci_match addr 0x40 value 0x%x\n", rmw); +*/ +// rmw = rmw & 0xff3fffff; /* Clear bit 22 and 23 */ +/* printf ("ahci_match addr 0x40 value 0x%x\n", rmw); + pci_write_config_byte(pdev, PCI_CB_SUBSYSTEM_VENDOR_ID, rmw); + } + } +*/ + /* initialize adapter */ + rc = ahci_host_init(probe_ent); + if (rc) + goto err_out; + + ahci_print_info(probe_ent); + + return 0; + + err_out: + return rc; +} + + +#define MAX_DATA_BYTE_COUNT (4*1024*1024) + +static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; + u32 sg_count; + int i; + + sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; + if (sg_count > AHCI_MAX_SG) { + printf("Error:Too much sg!\n"); + return -1; + } + + for (i = 0; i < sg_count; i++) { + ahci_sg->addr = + cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); + ahci_sg->addr_hi = 0; + ahci_sg->flags_size = cpu_to_le32(0x3fffff & + (buf_len < MAX_DATA_BYTE_COUNT + ? (buf_len - 1) + : (MAX_DATA_BYTE_COUNT - 1))); + ahci_sg++; + buf_len -= MAX_DATA_BYTE_COUNT; + } + + return sg_count; +} + + +static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) +{ + pp->cmd_slot->opts = cpu_to_le32(opts); + pp->cmd_slot->status = 0; + pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); + pp->cmd_slot->tbl_addr_hi = 0; +} + + +static void ahci_set_feature(u8 port) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 cmd_fis_len = 5; /* five dwords */ + u8 fis[20]; + + /*set feature */ + memset(fis, 0, 20); + fis[0] = 0x27; + fis[1] = 1 << 7; + fis[2] = ATA_CMD_SETF; + fis[3] = SETFEATURES_XFER; + fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; + + memcpy((unsigned char *)pp->cmd_tbl, fis, 20); + ahci_fill_cmd_slot(pp, cmd_fis_len); + writel(1, port_mmio + PORT_CMD_ISSUE); + readl(port_mmio + PORT_CMD_ISSUE); + + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + printf("set feature error!\n"); + } +} + + +static int ahci_port_start(u8 port) +{ + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 port_status; + u32 mem; + + debug("Enter start port: %d\n", port); + port_status = readl(port_mmio + PORT_SCR_STAT); + debug("Port %d status: %x\n", port, port_status); + if ((port_status & 0xf) != 0x03) { + printf("No Link on this port!\n"); + return -1; + } + + mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 4096); + if (!mem) { + free(pp); + printf("No mem for table!\n"); + return -ENOMEM; + } + + mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ + memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); + + /* + * First item in chunk of DMA memory: 32-slot command table, + * 32 bytes each in size + */ + pp->cmd_slot = (struct ahci_cmd_hdr *)mem; + debug("cmd_slot = 0x%x\n", pp->cmd_slot); + /* mem += (AHCI_CMD_SLOT_SZ + 224); */ + mem += 2048; + + /* + * Second item: Received-FIS area + */ + pp->rx_fis = mem; + /* mem += AHCI_RX_FIS_SZ; */ + mem += 1024; + + /* + * Third item: data area for storing a single command + * and its scatter-gather table + */ + pp->cmd_tbl = mem; + debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); + + mem += AHCI_CMD_TBL_HDR; + pp->cmd_tbl_sg = (struct ahci_sg *)mem; + + writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); + + writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); + +/* writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | + PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | + PORT_CMD_START, port_mmio + PORT_CMD); +*/ + writel_with_flush(PORT_CMD_FIS_RX | PORT_CMD_START | 0x20, port_mmio + PORT_CMD); + debug("Exit start port %d\n", port); + + return 0; +} + + +static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, + int buf_len) +{ + + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 opts; + u32 port_status; + int sg_count; + int i; + + debug("Enter get_ahci_device_data: for port %d addr mmio 0x%x\n", port, port_mmio); + + if (port > probe_ent->n_ports) { + printf("Invaild port number %d\n", port); + return -1; + } + + port_status = readl(port_mmio + PORT_SCR_STAT); + if ((port_status & 0xf) != 0x03) { + debug("No Link on port %d!\n", port); + return -1; + } + + debug("Enter get_ahci_device_data: fis data\n"); + for (i=0; i < fis_len; i++) + { + debug("%p:%02x\n", &fis[i], fis[i]); + } + + memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); + + debug("Enter get_ahci_device_data: pp->cmd_tbl 0x%p \n",pp->cmd_tbl ); + for (i=0; i < fis_len; i++) + { + debug("%p:%02x\n", &(((unsigned char *)(pp->cmd_tbl))[i]), ((unsigned char *)(pp->cmd_tbl))[i]); + } + debug("Enter get_ahci_device_data: buf 0x%x buf_len 0x%x\n",buf,buf_len ); + sg_count = ahci_fill_sg(port, buf, buf_len); + opts = (fis_len >> 2) | (sg_count << 16); + ahci_fill_cmd_slot(pp, opts); + + writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); + + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 1500, 0x1)) { + printf("timeout exit!\n"); + return -1; + } + debug("get_ahci_device_data: %d byte transferred.\n", + pp->cmd_slot->status); + + return 0; +} + + +static char *ata_id_strcpy(u16 *target, u16 *src, int len) +{ + int i; + for (i = 0; i < len / 2; i++) + /* Swap 16bit for display - on memory this data is */ + /* in big endian */ + target[i] = __swab16(src[i]); + return (char *)target; +} + + +static void dump_ataid(hd_driveid_t *ataid) +{ + debug("(49)ataid->capability = 0x%x\n", ataid->capability); + debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); + debug("(60)ataid->lba_capacity =0x%x\n", ataid->lba_capacity); + debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); + debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); + debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); + debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); + debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); + debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); + debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); + debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); + debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); + debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); + debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); + debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); + debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); +} + + +/* + * SCSI INQUIRY command operation. + */ +static int ata_scsiop_inquiry(ccb *pccb) +{ + u8 hdr[] = { + 0, + 0, + 0x5, /* claim SPC-3 version compatibility */ + 2, + 95 - 4, + }; + u8 fis[20]; + u8 *tmpid; + u8 port; + u16 i; + + /* Clean ccb data buffer */ + memset(pccb->pdata, 0, pccb->datalen); + + memcpy(pccb->pdata, hdr, sizeof(hdr)); + + if (pccb->datalen <= 35) + return 0; + + memset(fis, 0, 20); + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_IDENT; /* Command byte. */ + + /* Read id from sata */ + port = pccb->target; + if (!(tmpid = malloc(sizeof(hd_driveid_t)))) + return -ENOMEM; + + if (get_ahci_device_data(port, (u8 *) & fis, 20, + tmpid, sizeof(hd_driveid_t))) { + debug("scsi_ahci: SCSI inquiry command failure.\n"); + return -EIO; + } + + if (ataid[port]) + free(ataid[port]); + ataid[port] = (hd_driveid_t *) tmpid; + + short* tmp = (short *)tmpid; + + memcpy(&pccb->pdata[8], "ATA ", 8); + ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); + ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); + + dump_ataid(ataid[port]); + return 0; +} + + +/* + * SCSI READ10 command operation. + */ +static int ata_scsiop_read10(ccb * pccb) +{ + u64 lba = 0; + u32 len = 0; + u8 fis[20]; + + lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16) + | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]); + len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]); + + /* For 10-byte and 16-byte SCSI R/W commands, transfer + * length 0 means transfer 0 block of data. + * However, for ATA R/W commands, sector count 0 means + * 256 or 65536 sectors, not 0 sectors as in SCSI. + * + * WARNING: one or two older ATA drives treat 0 as 0... + */ + if (!len) + return 0; + memset(fis, 0, 20); + + /* Construct the FIS */ + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ + + /* LBA address, only support LBA28 in this driver */ + fis[4] = pccb->cmd[5]; + fis[5] = pccb->cmd[4]; + fis[6] = pccb->cmd[3]; + fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0; + + /* Sector Count */ + fis[12] = pccb->cmd[8]; + fis[13] = pccb->cmd[7]; + + /* Read from ahci */ + if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20, + pccb->pdata, pccb->datalen)) { + debug("scsi_ahci: SCSI READ10 command failure.\n"); + return -EIO; + } + + return 0; +} + + +/* + * SCSI READ CAPACITY10 command operation. + */ +static int ata_scsiop_read_capacity10(ccb *pccb) +{ + u8 buf[8]; + + if (!ataid[pccb->target]) { + printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " + "\tNo ATA info!\n" + "\tPlease run SCSI commmand INQUIRY firstly!\n"); + return -EPERM; + } + + memset(buf, 0, 8); + + /* Swap 32bit for display - on memory this data is */ + /* in little endian but this field in the buffer is in big endian format */ + *(u32 *) buf = __swab32(ataid[pccb->target]->lba_capacity); + + buf[6] = 512 >> 8; + buf[7] = 512 & 0xff; + + memcpy(pccb->pdata, buf, 8); + + return 0; +} + + +/* + * SCSI TEST UNIT READY command operation. + */ +static int ata_scsiop_test_unit_ready(ccb *pccb) +{ + return (ataid[pccb->target]) ? 0 : -EPERM; +} + + +int scsi_exec(ccb *pccb) +{ + int ret; + + switch (pccb->cmd[0]) { + case SCSI_READ10: + ret = ata_scsiop_read10(pccb); + break; + case SCSI_RD_CAPAC: + ret = ata_scsiop_read_capacity10(pccb); + break; + case SCSI_TST_U_RDY: + ret = ata_scsiop_test_unit_ready(pccb); + break; + case SCSI_INQUIRY: + ret = ata_scsiop_inquiry(pccb); + break; + default: + printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); + return FALSE; + } + + if (ret) { + debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); + return FALSE; + } + return TRUE; + +} + + +void scsi_low_level_init(int busdevfunc) +{ + int i; + u32 linkmap; + + ahci_init_one(busdevfunc); + + linkmap = probe_ent->link_port_map; + + for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) { + if (((linkmap >> i) & 0x01)) { + if (ahci_port_start((u8) i)) { + printf("Can not start port %d\n", i); + continue; + } + /* ahci_set_feature((u8) i); yotam */ + } + } +} + + +void scsi_bus_reset(void) +{ + /*Not implement*/ +} + + +void scsi_print_error(ccb * pccb) +{ + /*The ahci error info can be read in the ahci driver*/ +} +#endif diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index 4b7a110..f07c7e5 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -41,8 +41,9 @@ * */ + /* The DEBUG define must be before common to enable debugging */ -/* #define DEBUG */ +/* #define DEBUG */ #include #include @@ -61,14 +62,10 @@ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * AMD CFI Specification, Release 2.0 December 1, 2001 + * AMD/Spansion Application Note: Migration from Single-byte to Three-byte + * Device IDs, Publication Number 25538 Revision A, November 8, 2001 * - * TODO - * - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query - * Table (ALT) to determine if protection is available - * - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. */ #ifndef CFG_FLASH_BANKS_LIST @@ -104,6 +101,8 @@ #define AMD_CMD_ERASE_SECTOR 0x30 #define AMD_CMD_UNLOCK_START 0xAA #define AMD_CMD_UNLOCK_ACK 0x55 +#define AMD_CMD_WRITE_TO_BUFFER 0x25 +#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 #define AMD_STATUS_TOGGLE 0x40 #define AMD_STATUS_ERROR 0x20 @@ -111,9 +110,14 @@ #define AMD_ADDR_START 0x555 #define AMD_ADDR_ACK 0x2AA +#define FLASH_OFFSET_MANUFACTURER_ID 0x00 +#define FLASH_OFFSET_DEVICE_ID 0x01 +#define FLASH_OFFSET_DEVICE_ID2 0x0E +#define FLASH_OFFSET_DEVICE_ID3 0x0F #define FLASH_OFFSET_CFI 0x55 #define FLASH_OFFSET_CFI_RESP 0x10 #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 +#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 /* extended query table primary addr */ #define FLASH_OFFSET_WTOUT 0x1F #define FLASH_OFFSET_WBTOUT 0x20 #define FLASH_OFFSET_ETOUT 0x21 @@ -131,18 +135,14 @@ #define FLASH_OFFSET_USER_PROTECTION 0x85 #define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -#define CFI_CMDSET_NONE 0 -#define CFI_CMDSET_INTEL_EXTENDED 1 -#define CFI_CMDSET_AMD_STANDARD 2 -#define CFI_CMDSET_INTEL_STANDARD 3 -#define CFI_CMDSET_AMD_EXTENDED 4 -#define CFI_CMDSET_MITSU_STANDARD 256 -#define CFI_CMDSET_MITSU_EXTENDED 257 -#define CFI_CMDSET_SST 258 - +#define CFI_CMDSET_NONE 0 +#define CFI_CMDSET_INTEL_EXTENDED 1 +#define CFI_CMDSET_AMD_STANDARD 2 +#define CFI_CMDSET_INTEL_STANDARD 3 +#define CFI_CMDSET_AMD_EXTENDED 4 +#define CFI_CMDSET_MITSU_STANDARD 256 +#define CFI_CMDSET_MITSU_EXTENDED 257 +#define CFI_CMDSET_SST 258 #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ # undef FLASH_CMD_RESET @@ -164,7 +164,7 @@ typedef union { volatile unsigned long long *llp; } cfiptr_t; -#define NUM_ERASE_REGIONS 4 +#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ /* use CFG_MAX_FLASH_BANKS_DETECT if defined */ #ifdef CFG_MAX_FLASH_BANKS_DETECT @@ -179,9 +179,13 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */ /*----------------------------------------------------------------------- * Functions */ - +extern int mv_flash_erase (flash_info_t *info, int s_first, int s_last); +extern void mv_flash_print_info (flash_info_t *info); +extern int mv_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); +extern int mv_flash_real_protect(flash_info_t *info, long sector, int prot); typedef unsigned long flash_sect_t; +unsigned long flash_add_base_addr (uint flash_index, ulong flash_base_addr); static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf); static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); @@ -189,11 +193,12 @@ static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static void flash_read_jedec_ids (flash_info_t * info); static int flash_detect_cfi (flash_info_t * info); -ulong flash_get_size (ulong base, int banknum); static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, ulong tout, char *prompt); +ulong flash_get_size (ulong base, int banknum); #if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) static flash_info_t *flash_get_info(ulong base); #endif @@ -201,12 +206,27 @@ static flash_info_t *flash_get_info(ulong base); static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len); #endif +/*----------------------------------------------------------------------- + * Add base address to nor flash base address bank + */ +unsigned long flash_add_base_addr (uint flash_index, ulong flash_base_addr) +{ + bank_base[flash_index] = flash_base_addr; + + return 0; +} + /*----------------------------------------------------------------------- * create an address based on the offset and the port width */ inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset) { - return ((uchar *) (info->start[sect] + (offset * info->portwidth))); +#if defined(AMD_FLASH_16BIT_IN_8BIT_MODE) + int shift = 2; +#else + int shift = info->portwidth; +#endif + return ((uchar *) (info->start[sect] + (offset * shift))); } #ifdef DEBUG @@ -226,8 +246,13 @@ static void flash_printqry (flash_info_t * info, flash_sect_t sect) { cfiptr_t cptr; int x, y; +#if defined(AMD_FLASH_16BIT_IN_8BIT_MODE) + int shift = 2; +#else + int shift = info->portwidth; +#endif - for (x = 0; x < 0x40; x += 16U / info->portwidth) { + for (x = 0; x < 0x40; x += 16U / shift) { cptr.cp = flash_make_addr (info, sect, x + FLASH_OFFSET_CFI_RESP); @@ -256,8 +281,20 @@ inline uchar flash_read_uchar (flash_info_t * info, uint offset) { uchar *cp; +#ifdef DEBUG + int x; +#endif cp = flash_make_addr (info, 0, offset); -#if defined(__LITTLE_ENDIAN) + +#ifdef DEBUG + debug ("uchar addr is at %p info->portwidth = %d\n", cp, + info->portwidth); + for (x = 0; x < 1 * info->portwidth; x++) { + debug ("addr[%x] = 0x%x\n", x, cp[x]); + } +#endif + +#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) return (cp[0]); #else return (cp[info->portwidth - 1]); @@ -271,6 +308,11 @@ ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset) { uchar *addr; ushort retval; +#if defined(AMD_FLASH_16BIT_IN_8BIT_MODE) + int shift = 2; +#else + int shift = info->portwidth; +#endif #ifdef DEBUG int x; @@ -280,15 +322,15 @@ ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset) #ifdef DEBUG debug ("ushort addr is at %p info->portwidth = %d\n", addr, info->portwidth); - for (x = 0; x < 2 * info->portwidth; x++) { + for (x = 0; x < 2 * shift; x += shift) { debug ("addr[%x] = 0x%x\n", x, addr[x]); } #endif -#if defined(__LITTLE_ENDIAN) - retval = ((addr[(info->portwidth)] << 8) | addr[0]); +#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) + retval = ((addr[(shift)] << 8) | addr[0]); #else - retval = ((addr[(2 * info->portwidth) - 1] << 8) | - addr[info->portwidth - 1]); + retval = ((addr[(2 * shift) - 1] << 8) | + addr[shift - 1]); #endif debug ("retval = 0x%x\n", retval); @@ -296,7 +338,7 @@ ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset) } /*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum + * read a long word by picking the least significant byte of each maximum * port size word. Swap for ppc format. */ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) @@ -304,6 +346,12 @@ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) uchar *addr; ulong retval; +#if defined(AMD_FLASH_16BIT_IN_8BIT_MODE) + int shift = 2; +#else + int shift = info->portwidth; +#endif + #ifdef DEBUG int x; #endif @@ -312,18 +360,18 @@ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) #ifdef DEBUG debug ("long addr is at %p info->portwidth = %d\n", addr, info->portwidth); - for (x = 0; x < 4 * info->portwidth; x++) { + for (x = 0; x < 4 * shift; x += shift) { debug ("addr[%x] = 0x%x\n", x, addr[x]); } #endif -#if defined(__LITTLE_ENDIAN) - retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) | - (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8); +#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) + retval = (addr[0] << 16) | (addr[(shift)] << 24) | + (addr[(2 * shift)]) | (addr[(3 * shift)] << 8); #else - retval = (addr[(2 * info->portwidth) - 1] << 24) | - (addr[(info->portwidth) - 1] << 16) | - (addr[(4 * info->portwidth) - 1] << 8) | - addr[(3 * info->portwidth) - 1]; + retval = (addr[(2 * shift) - 1] << 24) | + (addr[(shift) - 1] << 16) | + (addr[(4 * shift) - 1] << 8) | + addr[(3 * shift) - 1]; #endif return retval; } @@ -334,7 +382,7 @@ unsigned long flash_init (void) { unsigned long size = 0; int i; - + /* Init: no FLASHes known */ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; @@ -343,6 +391,14 @@ unsigned long flash_init (void) #ifndef CFG_FLASH_QUIET_TEST printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", i, flash_info[i].size, flash_info[i].size << 20); +#endif /* CFG_FLASH_QUIET_TEST */ + } + else + { +#ifndef CFG_FLASH_QUIET_TEST + printf("******************************************************\n"); + printf ("## FLASH 0x%08lx on Bank %d - Size = 0x%08lx = %ld MB\n", + i, flash_info[i].flash_id, flash_info[i].size, flash_info[i].size << 20); #endif /* CFG_FLASH_QUIET_TEST */ } } @@ -401,7 +457,11 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_sect_t sect; if (info->flash_id != FLASH_MAN_CFI) { - puts ("Can't erase unknown flash type - aborted\n"); +#if defined (CONFIG_MARVELL) + return mv_flash_erase(info, s_first, s_last); +#else + printf("missing or unknown FLASH type\n"); +#endif return 1; } if ((s_first < 0) || (s_first > s_last)) { @@ -463,14 +523,48 @@ void flash_print_info (flash_info_t * info) int i; if (info->flash_id != FLASH_MAN_CFI) { - puts ("missing or unknown FLASH type\n"); + +#if defined (CONFIG_MARVELL) + mv_flash_print_info(info); +#else + printf("missing or unknown FLASH type\n"); +#endif return; } printf ("CFI conformant FLASH (%d x %d)", (info->portwidth << 3), (info->chipwidth << 3)); - printf (" Size: %ld MB in %d Sectors\n", + + /* Check if flash size is less then 1 MB */ + if ( (info->size >> 20) == 0) + { + printf (" Size: %ld kB in %d Sectors\n", + info->size >> 10, info->sector_count); + } + else + { + printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + } + + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + printf ("Intel Standard"); + break; + case CFI_CMDSET_INTEL_EXTENDED: + printf ("Intel Extended"); + break; + case CFI_CMDSET_AMD_STANDARD: + printf ("AMD Standard"); + break; + case CFI_CMDSET_AMD_EXTENDED: + printf ("AMD Extended"); + break; + default: + printf ("Unknown (%d)", info->vendor); + break; + } + printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, @@ -537,6 +631,15 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) #ifdef CFG_FLASH_USE_BUFFER_WRITE int buffered_size; #endif + + if (info->flash_id != FLASH_MAN_CFI) { +#if defined (CONFIG_MARVELL) + return mv_write_buff(info, src, addr, cnt); +#else + printf("missing or unknown FLASH type\n"); +#endif + return 0; + } /* get lower aligned address */ /* get lower aligned address */ wp = (addr & ~(info->portwidth - 1)); @@ -611,6 +714,15 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) int flash_real_protect (flash_info_t * info, long sector, int prot) { int retcode = 0; + + if (info->flash_id != FLASH_MAN_CFI) { +#if defined (CONFIG_MARVELL) + mv_flash_real_protect(info, sector, prot); +#else + printf("missing or unknown FLASH type\n"); +#endif + return retcode; + } flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); @@ -624,15 +736,6 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) prot ? "protect" : "unprotect")) == 0) { info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if (prot == 0) { - flash_sect_t i; - - for (i = 0; i < info->sector_count; i++) { - if (info->protect[i]) - flash_real_protect (info, i, 1); - } - } } return retcode; } @@ -729,7 +832,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, switch (info->vendor) { case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: - if ((retcode != ERR_OK) + if ((retcode == ERR_OK) && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { retcode = ERR_INVAL; printf ("Flash %s error at address %lx\n", prompt, @@ -761,7 +864,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, */ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) { -#if defined(__LITTLE_ENDIAN) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) unsigned short w; unsigned int l; unsigned long long ll; @@ -772,7 +875,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) cword->c = c; break; case FLASH_CFI_16BIT: -#if defined(__LITTLE_ENDIAN) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) w = c; w <<= 8; cword->w = (cword->w >> 8) | w; @@ -781,7 +884,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) #endif break; case FLASH_CFI_32BIT: -#if defined(__LITTLE_ENDIAN) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) l = c; l <<= 24; cword->l = (cword->l >> 8) | l; @@ -790,7 +893,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) #endif break; case FLASH_CFI_64BIT: -#if defined(__LITTLE_ENDIAN) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) ll = c; ll <<= 56; cword->ll = (cword->ll >> 8) | ll; @@ -810,7 +913,7 @@ static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) int i; uchar *cp = (uchar *) cmdbuf; -#if defined(__LITTLE_ENDIAN) +#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) for (i = info->portwidth; i > 0; i--) #else for (i = 1; i <= info->portwidth; i++) @@ -976,6 +1079,55 @@ static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uc return retval; } +/*----------------------------------------------------------------------- + * read jedec ids from device and set corresponding fields in info struct + * + * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct + * +*/ +static void flash_read_jedec_ids (flash_info_t * info) +{ + info->manufacturer_id = 0; + info->device_id = 0; + info->device_id2 = 0; + + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); + udelay(1000); /* some flash are slow to respond */ + info->manufacturer_id = flash_read_uchar (info, + FLASH_OFFSET_MANUFACTURER_ID); + info->device_id = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID); + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + flash_unlock_seq(info, 0); + flash_write_cmd(info, 0, AMD_ADDR_START, FLASH_CMD_READ_ID); + udelay(1000); /* some flash are slow to respond */ + info->manufacturer_id = flash_read_uchar (info, + FLASH_OFFSET_MANUFACTURER_ID); + info->device_id = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID); + if (info->device_id == 0x7E) { + /* AMD 3-byte (expanded) device ids */ + info->device_id2 = flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID2); + info->device_id2 <<= 8; + info->device_id2 |= flash_read_uchar (info, + FLASH_OFFSET_DEVICE_ID3); + } + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + break; + default: + break; + } +} + /*----------------------------------------------------------------------- * detect if flash is compatible with the Common Flash Interface (CFI) * http://www.jedec.org/download/search/jesd68.pdf @@ -988,7 +1140,7 @@ static int flash_detect_cfi (flash_info_t * info) for (info->portwidth = FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { for (info->chipwidth = FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; + info->chipwidth <= (info->portwidth); info->chipwidth <<= 1) { flash_write_cmd (info, 0, 0, info->cmd_reset); flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); @@ -1026,11 +1178,31 @@ ulong flash_get_size (ulong base, int banknum) uchar num_erase_regions; int erase_region_size; int erase_region_count; + int geometry_reversed = 0; + + info->ext_addr = 0; + info->cfi_version = 0; +#ifdef CFG_FLASH_PROTECTION + info->legacy_unlock = 0; +#endif info->start[0] = base; if (flash_detect_cfi (info)) { - info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR); + info->vendor = flash_read_ushort (info, 0, + FLASH_OFFSET_PRIMARY_VENDOR); + flash_read_jedec_ids (info); + flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + num_erase_regions = flash_read_uchar (info, + FLASH_OFFSET_NUM_ERASE_REGIONS); + info->ext_addr = flash_read_ushort (info, 0, + FLASH_OFFSET_EXT_QUERY_T_P_ADDR); + if (info->ext_addr) { + info->cfi_version = (ushort) flash_read_uchar (info, + info->ext_addr + 3) << 8; + info->cfi_version |= (ushort) flash_read_uchar (info, + info->ext_addr + 4); + } #ifdef DEBUG flash_printqry (info, 0); #endif @@ -1039,21 +1211,52 @@ ulong flash_get_size (ulong base, int banknum) case CFI_CMDSET_INTEL_EXTENDED: default: info->cmd_reset = FLASH_CMD_RESET; +#ifdef CFG_FLASH_PROTECTION + /* read legacy lock/unlock bit from intel flash */ + if (info->ext_addr) { + info->legacy_unlock = flash_read_uchar (info, + info->ext_addr + 5) & 0x08; + } +#endif break; case CFI_CMDSET_AMD_STANDARD: case CFI_CMDSET_AMD_EXTENDED: info->cmd_reset = AMD_CMD_RESET; + /* check if flash geometry needs reversal */ + if (num_erase_regions <= 1) + break; + /* reverse geometry if top boot part */ + if (info->cfi_version < 0x3131) { + /* CFI < 1.1, try to guess from device id */ + if ((info->device_id & 0x80) != 0) { + geometry_reversed = 1; + } + break; + } + /* CFI >= 1.1, deduct from top/bottom flag */ + /* note: ext_addr is valid since cfi_version > 0 */ + if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { + geometry_reversed = 1; + } break; } debug ("manufacturer is %d\n", info->vendor); + debug ("manufacturer id is 0x%x\n", info->manufacturer_id); + debug ("device id is 0x%x\n", info->device_id); + debug ("device id2 is 0x%x\n", info->device_id2); + debug ("cfi version is 0x%04x\n", info->cfi_version); + size_ratio = info->portwidth / info->chipwidth; + +#if !defined(AMD_FLASH_16BIT_IN_8BIT_MODE) /* if the chip is x8/x16 reduce the ratio by half */ if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { size_ratio >>= 1; } - num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS); +#endif + debug ("size_ratio %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); @@ -1066,7 +1269,12 @@ ulong flash_get_size (ulong base, int banknum) num_erase_regions, NUM_ERASE_REGIONS); break; } - tmp = flash_read_long (info, 0, + if (geometry_reversed) + tmp = flash_read_long (info, 0, + FLASH_OFFSET_ERASE_REGIONS + + (num_erase_regions - 1 - i) * 4); + else + tmp = flash_read_long (info, 0, FLASH_OFFSET_ERASE_REGIONS + i * 4); erase_region_size = @@ -1104,20 +1312,41 @@ ulong flash_get_size (ulong base, int banknum) info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE)); tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000; + tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT)) * + (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)); + info->buffer_write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */ + tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) * + (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT)); + info->write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */ info->flash_id = FLASH_MAN_CFI; + +#if !defined(AMD_FLASH_16BIT_IN_8BIT_MODE) if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */ } +#endif } flash_write_cmd (info, 0, 0, info->cmd_reset); + debug ("info->size = %d\n", + info->size); return (info->size); } +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static flash_sect_t find_sector (flash_info_t * info, ulong addr) +{ + flash_sect_t sector; + + for (sector = info->sector_count - 1; sector >= 0; sector--) { + if (addr >= info->start[sector]) + break; + } + return sector; +} /*----------------------------------------------------------------------- */ @@ -1188,26 +1417,12 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, if (flag) enable_interrupts (); - return flash_full_status_check (info, 0, info->write_tout, "write"); + return flash_full_status_check (info, find_sector (info, dest), + info->write_tout, "write"); } #ifdef CFG_FLASH_USE_BUFFER_WRITE -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static flash_sect_t find_sector (flash_info_t * info, ulong addr) -{ - flash_sect_t sector; - - for (sector = info->sector_count - 1; sector >= 0; sector--) { - if (addr >= info->start[sector]) - break; - } - return sector; -} - static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len) { @@ -1216,66 +1431,106 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int retcode; volatile cfiptr_t src; volatile cfiptr_t dst; - /* buffered writes in the AMD chip set is not supported yet */ - if((info->vendor == CFI_CMDSET_AMD_STANDARD) || - (info->vendor == CFI_CMDSET_AMD_EXTENDED)) - return ERR_INVAL; - src.cp = cp; - dst.cp = (uchar *) dest; - sector = find_sector (info, dest); - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if ((retcode = - flash_status_check (info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - /* reduce the number of loops by the width of the port */ - switch (info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - case FLASH_CFI_64BIT: - cnt = len >> 3; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) { + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + src.cp = cp; + dst.cp = (uchar *) dest; + sector = find_sector (info, dest); + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if ((retcode = flash_status_check (info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + /* reduce the number of loops by the width of the port */ switch (info->portwidth) { case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; + cnt = len; break; case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; + cnt = len >> 1; break; case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; + cnt = len >> 2; break; case FLASH_CFI_64BIT: - *dst.llp++ = *src.llp++; + cnt = len >> 3; break; default: return ERR_INVAL; break; } + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + case FLASH_CFI_64BIT: + *dst.llp++ = *src.llp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd (info, sector, 0, + FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check (info, sector, + info->buffer_write_tout, + "buffer write"); } - flash_write_cmd (info, sector, 0, - FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = - flash_full_status_check (info, sector, - info->buffer_write_tout, - "buffer write"); + return retcode; + + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + src.cp = cp; + dst.cp = (uchar *) dest; + sector = find_sector (info, dest); + + flash_unlock_seq(info,0); + flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER); + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.lp++ = *src.lp++; + break; + case FLASH_CFI_64BIT: + cnt = len >> 3; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.llp++ = *src.llp++; + break; + default: + return ERR_INVAL; + } + + flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check (info, sector, info->buffer_write_tout, + "buffer write"); + return retcode; + + default: + debug ("Unknown Command Set\n"); + return ERR_INVAL; } - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; } #endif /* CFG_FLASH_USE_BUFFER_WRITE */ #endif /* CFG_FLASH_CFI */ diff --git a/drivers/eepro100.c b/drivers/eepro100.c index 04c17f6..dcaca63 100644 --- a/drivers/eepro100.c +++ b/drivers/eepro100.c @@ -249,9 +249,12 @@ static int eepro100_send (struct eth_device *dev, volatile void *packet, static int eepro100_recv (struct eth_device *dev); static void eepro100_halt (struct eth_device *dev); -#if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460) -#define bus_to_phys(a) (a) +#if defined(CONFIG_E500) || (defined(CONFIG_MARVELL) && defined(__ARM__)) +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) #define phys_to_bus(a) (a) +#elif defined(CONFIG_MARVELL) && defined(__MIPS__) +#define bus_to_phys(a) (a | (0xa0000000)) +#define phys_to_bus(a) (a & ~(0xa0000000)) #else #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) diff --git a/drivers/nand/.depend b/drivers/nand/.depend new file mode 100644 index 0000000..7c6ab4b --- /dev/null +++ b/drivers/nand/.depend @@ -0,0 +1,196 @@ +nand.o: nand.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +nand_base.o: nand_base.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +nand_ids.o: nand_ids.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +nand_ecc.o: nand_ecc.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +nand_ecc_rs.o: nand_ecc_rs.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +nand_bbt.o: nand_bbt.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +nand_util.o: nand_util.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h diff --git a/drivers/nand/Makefile b/drivers/nand/Makefile new file mode 100644 index 0000000..87678a6 --- /dev/null +++ b/drivers/nand/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libnand.a + +COBJS := nand.o nand_base.o nand_ids.o nand_ecc.o nand_ecc_rs.o nand_bbt.o nand_util.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/nand/diskonchip.c b/drivers/nand/diskonchip.c new file mode 100644 index 0000000..e17af70 --- /dev/null +++ b/drivers/nand/diskonchip.c @@ -0,0 +1,1787 @@ +/* + * drivers/mtd/nand/diskonchip.c + * + * (C) 2003 Red Hat, Inc. + * (C) 2004 Dan Brown + * (C) 2004 Kalev Lember + * + * Author: David Woodhouse + * Additional Diskonchip 2000 and Millennium support by Dan Brown + * Diskonchip Millennium Plus support by Kalev Lember + * + * Error correction code lifted from the old docecc code + * Author: Fabrice Bellard (fabrice.bellard@netgem.com) + * Copyright (C) 2000 Netgem S.A. + * converted to the generic Reed-Solomon library by Thomas Gleixner + * + * Interface to generic NAND code for M-Systems DiskOnChip devices + * + * $Id: diskonchip.c,v 1.45 2005/01/05 18:05:14 dwmw2 Exp $ + */ + +#include + +#if !defined(CFG_NAND_LEGACY) + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* Where to look for the devices? */ +#ifndef CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS +#define CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS 0 +#endif + +static unsigned long __initdata doc_locations[] = { +#if defined (__alpha__) || defined(__i386__) || defined(__x86_64__) +#ifdef CONFIG_MTD_DISKONCHIP_PROBE_HIGH + 0xfffc8000, 0xfffca000, 0xfffcc000, 0xfffce000, + 0xfffd0000, 0xfffd2000, 0xfffd4000, 0xfffd6000, + 0xfffd8000, 0xfffda000, 0xfffdc000, 0xfffde000, + 0xfffe0000, 0xfffe2000, 0xfffe4000, 0xfffe6000, + 0xfffe8000, 0xfffea000, 0xfffec000, 0xfffee000, +#else /* CONFIG_MTD_DOCPROBE_HIGH */ + 0xc8000, 0xca000, 0xcc000, 0xce000, + 0xd0000, 0xd2000, 0xd4000, 0xd6000, + 0xd8000, 0xda000, 0xdc000, 0xde000, + 0xe0000, 0xe2000, 0xe4000, 0xe6000, + 0xe8000, 0xea000, 0xec000, 0xee000, +#endif /* CONFIG_MTD_DOCPROBE_HIGH */ +#elif defined(__PPC__) + 0xe4000000, +#elif defined(CONFIG_MOMENCO_OCELOT) + 0x2f000000, + 0xff000000, +#elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C) + 0xff000000, +##else +#warning Unknown architecture for DiskOnChip. No default probe locations defined +#endif + 0xffffffff }; + +static struct mtd_info *doclist = NULL; + +struct doc_priv { + void __iomem *virtadr; + unsigned long physadr; + u_char ChipID; + u_char CDSNControl; + int chips_per_floor; /* The number of chips detected on each floor */ + int curfloor; + int curchip; + int mh0_page; + int mh1_page; + struct mtd_info *nextdoc; +}; + +/* Max number of eraseblocks to scan (from start of device) for the (I)NFTL + MediaHeader. The spec says to just keep going, I think, but that's just + silly. */ +#define MAX_MEDIAHEADER_SCAN 8 + +/* This is the syndrome computed by the HW ecc generator upon reading an empty + page, one with all 0xff for data and stored ecc code. */ +static u_char empty_read_syndrome[6] = { 0x26, 0xff, 0x6d, 0x47, 0x73, 0x7a }; +/* This is the ecc value computed by the HW ecc generator upon writing an empty + page, one with all 0xff for data. */ +static u_char empty_write_ecc[6] = { 0x4b, 0x00, 0xe2, 0x0e, 0x93, 0xf7 }; + +#define INFTL_BBT_RESERVED_BLOCKS 4 + +#define DoC_is_MillenniumPlus(doc) ((doc)->ChipID == DOC_ChipID_DocMilPlus16 || (doc)->ChipID == DOC_ChipID_DocMilPlus32) +#define DoC_is_Millennium(doc) ((doc)->ChipID == DOC_ChipID_DocMil) +#define DoC_is_2000(doc) ((doc)->ChipID == DOC_ChipID_Doc2k) + +static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd); +static void doc200x_select_chip(struct mtd_info *mtd, int chip); + +static int debug=0; +module_param(debug, int, 0); + +static int try_dword=1; +module_param(try_dword, int, 0); + +static int no_ecc_failures=0; +module_param(no_ecc_failures, int, 0); + +#ifdef CONFIG_MTD_PARTITIONS +static int no_autopart=0; +module_param(no_autopart, int, 0); +#endif + +#ifdef MTD_NAND_DISKONCHIP_BBTWRITE +static int inftl_bbt_write=1; +#else +static int inftl_bbt_write=0; +#endif +module_param(inftl_bbt_write, int, 0); + +static unsigned long doc_config_location = CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS; +module_param(doc_config_location, ulong, 0); +MODULE_PARM_DESC(doc_config_location, "Physical memory address at which to probe for DiskOnChip"); + + +/* Sector size for HW ECC */ +#define SECTOR_SIZE 512 +/* The sector bytes are packed into NB_DATA 10 bit words */ +#define NB_DATA (((SECTOR_SIZE + 1) * 8 + 6) / 10) +/* Number of roots */ +#define NROOTS 4 +/* First consective root */ +#define FCR 510 +/* Number of symbols */ +#define NN 1023 + +/* the Reed Solomon control structure */ +static struct rs_control *rs_decoder; + +/* + * The HW decoder in the DoC ASIC's provides us a error syndrome, + * which we must convert to a standard syndrom usable by the generic + * Reed-Solomon library code. + * + * Fabrice Bellard figured this out in the old docecc code. I added + * some comments, improved a minor bit and converted it to make use + * of the generic Reed-Solomon libary. tglx + */ +static int doc_ecc_decode (struct rs_control *rs, uint8_t *data, uint8_t *ecc) +{ + int i, j, nerr, errpos[8]; + uint8_t parity; + uint16_t ds[4], s[5], tmp, errval[8], syn[4]; + + /* Convert the ecc bytes into words */ + ds[0] = ((ecc[4] & 0xff) >> 0) | ((ecc[5] & 0x03) << 8); + ds[1] = ((ecc[5] & 0xfc) >> 2) | ((ecc[2] & 0x0f) << 6); + ds[2] = ((ecc[2] & 0xf0) >> 4) | ((ecc[3] & 0x3f) << 4); + ds[3] = ((ecc[3] & 0xc0) >> 6) | ((ecc[0] & 0xff) << 2); + parity = ecc[1]; + + /* Initialize the syndrom buffer */ + for (i = 0; i < NROOTS; i++) + s[i] = ds[0]; + /* + * Evaluate + * s[i] = ds[3]x^3 + ds[2]x^2 + ds[1]x^1 + ds[0] + * where x = alpha^(FCR + i) + */ + for(j = 1; j < NROOTS; j++) { + if(ds[j] == 0) + continue; + tmp = rs->index_of[ds[j]]; + for(i = 0; i < NROOTS; i++) + s[i] ^= rs->alpha_to[rs_modnn(rs, tmp + (FCR + i) * j)]; + } + + /* Calc s[i] = s[i] / alpha^(v + i) */ + for (i = 0; i < NROOTS; i++) { + if (syn[i]) + syn[i] = rs_modnn(rs, rs->index_of[s[i]] + (NN - FCR - i)); + } + /* Call the decoder library */ + nerr = decode_rs16(rs, NULL, NULL, 1019, syn, 0, errpos, 0, errval); + + /* Incorrectable errors ? */ + if (nerr < 0) + return nerr; + + /* + * Correct the errors. The bitpositions are a bit of magic, + * but they are given by the design of the de/encoder circuit + * in the DoC ASIC's. + */ + for(i = 0;i < nerr; i++) { + int index, bitpos, pos = 1015 - errpos[i]; + uint8_t val; + if (pos >= NB_DATA && pos < 1019) + continue; + if (pos < NB_DATA) { + /* extract bit position (MSB first) */ + pos = 10 * (NB_DATA - 1 - pos) - 6; + /* now correct the following 10 bits. At most two bytes + can be modified since pos is even */ + index = (pos >> 3) ^ 1; + bitpos = pos & 7; + if ((index >= 0 && index < SECTOR_SIZE) || + index == (SECTOR_SIZE + 1)) { + val = (uint8_t) (errval[i] >> (2 + bitpos)); + parity ^= val; + if (index < SECTOR_SIZE) + data[index] ^= val; + } + index = ((pos >> 3) + 1) ^ 1; + bitpos = (bitpos + 10) & 7; + if (bitpos == 0) + bitpos = 8; + if ((index >= 0 && index < SECTOR_SIZE) || + index == (SECTOR_SIZE + 1)) { + val = (uint8_t)(errval[i] << (8 - bitpos)); + parity ^= val; + if (index < SECTOR_SIZE) + data[index] ^= val; + } + } + } + /* If the parity is wrong, no rescue possible */ + return parity ? -1 : nerr; +} + +static void DoC_Delay(struct doc_priv *doc, unsigned short cycles) +{ + volatile char dummy; + int i; + + for (i = 0; i < cycles; i++) { + if (DoC_is_Millennium(doc)) + dummy = ReadDOC(doc->virtadr, NOP); + else if (DoC_is_MillenniumPlus(doc)) + dummy = ReadDOC(doc->virtadr, Mplus_NOP); + else + dummy = ReadDOC(doc->virtadr, DOCStatus); + } + +} + +#define CDSN_CTRL_FR_B_MASK (CDSN_CTRL_FR_B0 | CDSN_CTRL_FR_B1) + +/* DOC_WaitReady: Wait for RDY line to be asserted by the flash chip */ +static int _DoC_WaitReady(struct doc_priv *doc) +{ + void __iomem *docptr = doc->virtadr; + unsigned long timeo = jiffies + (HZ * 10); + + if(debug) printk("_DoC_WaitReady...\n"); + /* Out-of-line routine to wait for chip response */ + if (DoC_is_MillenniumPlus(doc)) { + while ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) { + if (time_after(jiffies, timeo)) { + printk("_DoC_WaitReady timed out.\n"); + return -EIO; + } + udelay(1); + cond_resched(); + } + } else { + while (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) { + if (time_after(jiffies, timeo)) { + printk("_DoC_WaitReady timed out.\n"); + return -EIO; + } + udelay(1); + cond_resched(); + } + } + + return 0; +} + +static inline int DoC_WaitReady(struct doc_priv *doc) +{ + void __iomem *docptr = doc->virtadr; + int ret = 0; + + if (DoC_is_MillenniumPlus(doc)) { + DoC_Delay(doc, 4); + + if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) + /* Call the out-of-line routine to wait */ + ret = _DoC_WaitReady(doc); + } else { + DoC_Delay(doc, 4); + + if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) + /* Call the out-of-line routine to wait */ + ret = _DoC_WaitReady(doc); + DoC_Delay(doc, 2); + } + + if(debug) printk("DoC_WaitReady OK\n"); + return ret; +} + +static void doc2000_write_byte(struct mtd_info *mtd, u_char datum) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + if(debug)printk("write_byte %02x\n", datum); + WriteDOC(datum, docptr, CDSNSlowIO); + WriteDOC(datum, docptr, 2k_CDSN_IO); +} + +static u_char doc2000_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + u_char ret; + + ReadDOC(docptr, CDSNSlowIO); + DoC_Delay(doc, 2); + ret = ReadDOC(docptr, 2k_CDSN_IO); + if (debug) printk("read_byte returns %02x\n", ret); + return ret; +} + +static void doc2000_writebuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + if (debug)printk("writebuf of %d bytes: ", len); + for (i=0; i < len; i++) { + WriteDOC_(buf[i], docptr, DoC_2k_CDSN_IO + i); + if (debug && i < 16) + printk("%02x ", buf[i]); + } + if (debug) printk("\n"); +} + +static void doc2000_readbuf(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("readbuf of %d bytes: ", len); + + for (i=0; i < len; i++) { + buf[i] = ReadDOC(docptr, 2k_CDSN_IO + i); + } +} + +static void doc2000_readbuf_dword(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug) printk("readbuf_dword of %d bytes: ", len); + + if (unlikely((((unsigned long)buf)|len) & 3)) { + for (i=0; i < len; i++) { + *(uint8_t *)(&buf[i]) = ReadDOC(docptr, 2k_CDSN_IO + i); + } + } else { + for (i=0; i < len; i+=4) { + *(uint32_t*)(&buf[i]) = readl(docptr + DoC_2k_CDSN_IO + i); + } + } +} + +static int doc2000_verifybuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + for (i=0; i < len; i++) + if (buf[i] != ReadDOC(docptr, 2k_CDSN_IO)) + return -EFAULT; + return 0; +} + +static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + uint16_t ret; + + doc200x_select_chip(mtd, nr); + doc200x_hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_READID); + doc200x_hwcontrol(mtd, NAND_CTL_CLRCLE); + doc200x_hwcontrol(mtd, NAND_CTL_SETALE); + this->write_byte(mtd, 0); + doc200x_hwcontrol(mtd, NAND_CTL_CLRALE); + + ret = this->read_byte(mtd) << 8; + ret |= this->read_byte(mtd); + + if (doc->ChipID == DOC_ChipID_Doc2k && try_dword && !nr) { + /* First chip probe. See if we get same results by 32-bit access */ + union { + uint32_t dword; + uint8_t byte[4]; + } ident; + void __iomem *docptr = doc->virtadr; + + doc200x_hwcontrol(mtd, NAND_CTL_SETCLE); + doc2000_write_byte(mtd, NAND_CMD_READID); + doc200x_hwcontrol(mtd, NAND_CTL_CLRCLE); + doc200x_hwcontrol(mtd, NAND_CTL_SETALE); + doc2000_write_byte(mtd, 0); + doc200x_hwcontrol(mtd, NAND_CTL_CLRALE); + + ident.dword = readl(docptr + DoC_2k_CDSN_IO); + if (((ident.byte[0] << 8) | ident.byte[1]) == ret) { + printk(KERN_INFO "DiskOnChip 2000 responds to DWORD access\n"); + this->read_buf = &doc2000_readbuf_dword; + } + } + + return ret; +} + +static void __init doc2000_count_chips(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + uint16_t mfrid; + int i; + + /* Max 4 chips per floor on DiskOnChip 2000 */ + doc->chips_per_floor = 4; + + /* Find out what the first chip is */ + mfrid = doc200x_ident_chip(mtd, 0); + + /* Find how many chips in each floor. */ + for (i = 1; i < 4; i++) { + if (doc200x_ident_chip(mtd, i) != mfrid) + break; + } + doc->chips_per_floor = i; + printk(KERN_DEBUG "Detected %d chips per floor.\n", i); +} + +static int doc200x_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + struct doc_priv *doc = this->priv; + + int status; + + DoC_WaitReady(doc); + this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); + DoC_WaitReady(doc); + status = (int)this->read_byte(mtd); + + return status; +} + +static void doc2001_write_byte(struct mtd_info *mtd, u_char datum) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + WriteDOC(datum, docptr, CDSNSlowIO); + WriteDOC(datum, docptr, Mil_CDSN_IO); + WriteDOC(datum, docptr, WritePipeTerm); +} + +static u_char doc2001_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /*ReadDOC(docptr, CDSNSlowIO); */ + /* 11.4.5 -- delay twice to allow extended length cycle */ + DoC_Delay(doc, 2); + ReadDOC(docptr, ReadPipeInit); + /*return ReadDOC(docptr, Mil_CDSN_IO); */ + return ReadDOC(docptr, LastDataRead); +} + +static void doc2001_writebuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + for (i=0; i < len; i++) + WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i); + /* Terminate write pipeline */ + WriteDOC(0x00, docptr, WritePipeTerm); +} + +static void doc2001_readbuf(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + /* Start read pipeline */ + ReadDOC(docptr, ReadPipeInit); + + for (i=0; i < len-1; i++) + buf[i] = ReadDOC(docptr, Mil_CDSN_IO + (i & 0xff)); + + /* Terminate read pipeline */ + buf[i] = ReadDOC(docptr, LastDataRead); +} + +static int doc2001_verifybuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + /* Start read pipeline */ + ReadDOC(docptr, ReadPipeInit); + + for (i=0; i < len-1; i++) + if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { + ReadDOC(docptr, LastDataRead); + return i; + } + if (buf[i] != ReadDOC(docptr, LastDataRead)) + return i; + return 0; +} + +static u_char doc2001plus_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + u_char ret; + + ReadDOC(docptr, Mplus_ReadPipeInit); + ReadDOC(docptr, Mplus_ReadPipeInit); + ret = ReadDOC(docptr, Mplus_LastDataRead); + if (debug) printk("read_byte returns %02x\n", ret); + return ret; +} + +static void doc2001plus_writebuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("writebuf of %d bytes: ", len); + for (i=0; i < len; i++) { + WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i); + if (debug && i < 16) + printk("%02x ", buf[i]); + } + if (debug) printk("\n"); +} + +static void doc2001plus_readbuf(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("readbuf of %d bytes: ", len); + + /* Start read pipeline */ + ReadDOC(docptr, Mplus_ReadPipeInit); + ReadDOC(docptr, Mplus_ReadPipeInit); + + for (i=0; i < len-2; i++) { + buf[i] = ReadDOC(docptr, Mil_CDSN_IO); + if (debug && i < 16) + printk("%02x ", buf[i]); + } + + /* Terminate read pipeline */ + buf[len-2] = ReadDOC(docptr, Mplus_LastDataRead); + if (debug && i < 16) + printk("%02x ", buf[len-2]); + buf[len-1] = ReadDOC(docptr, Mplus_LastDataRead); + if (debug && i < 16) + printk("%02x ", buf[len-1]); + if (debug) printk("\n"); +} + +static int doc2001plus_verifybuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("verifybuf of %d bytes: ", len); + + /* Start read pipeline */ + ReadDOC(docptr, Mplus_ReadPipeInit); + ReadDOC(docptr, Mplus_ReadPipeInit); + + for (i=0; i < len-2; i++) + if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { + ReadDOC(docptr, Mplus_LastDataRead); + ReadDOC(docptr, Mplus_LastDataRead); + return i; + } + if (buf[len-2] != ReadDOC(docptr, Mplus_LastDataRead)) + return len-2; + if (buf[len-1] != ReadDOC(docptr, Mplus_LastDataRead)) + return len-1; + return 0; +} + +static void doc2001plus_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int floor = 0; + + if(debug)printk("select chip (%d)\n", chip); + + if (chip == -1) { + /* Disable flash internally */ + WriteDOC(0, docptr, Mplus_FlashSelect); + return; + } + + floor = chip / doc->chips_per_floor; + chip -= (floor * doc->chips_per_floor); + + /* Assert ChipEnable and deassert WriteProtect */ + WriteDOC((DOC_FLASH_CE), docptr, Mplus_FlashSelect); + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + doc->curchip = chip; + doc->curfloor = floor; +} + +static void doc200x_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int floor = 0; + + if(debug)printk("select chip (%d)\n", chip); + + if (chip == -1) + return; + + floor = chip / doc->chips_per_floor; + chip -= (floor * doc->chips_per_floor); + + /* 11.4.4 -- deassert CE before changing chip */ + doc200x_hwcontrol(mtd, NAND_CTL_CLRNCE); + + WriteDOC(floor, docptr, FloorSelect); + WriteDOC(chip, docptr, CDSNDeviceSelect); + + doc200x_hwcontrol(mtd, NAND_CTL_SETNCE); + + doc->curchip = chip; + doc->curfloor = floor; +} + +static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + switch(cmd) { + case NAND_CTL_SETNCE: + doc->CDSNControl |= CDSN_CTRL_CE; + break; + case NAND_CTL_CLRNCE: + doc->CDSNControl &= ~CDSN_CTRL_CE; + break; + case NAND_CTL_SETCLE: + doc->CDSNControl |= CDSN_CTRL_CLE; + break; + case NAND_CTL_CLRCLE: + doc->CDSNControl &= ~CDSN_CTRL_CLE; + break; + case NAND_CTL_SETALE: + doc->CDSNControl |= CDSN_CTRL_ALE; + break; + case NAND_CTL_CLRALE: + doc->CDSNControl &= ~CDSN_CTRL_ALE; + break; + case NAND_CTL_SETWP: + doc->CDSNControl |= CDSN_CTRL_WP; + break; + case NAND_CTL_CLRWP: + doc->CDSNControl &= ~CDSN_CTRL_WP; + break; + } + if (debug)printk("hwcontrol(%d): %02x\n", cmd, doc->CDSNControl); + WriteDOC(doc->CDSNControl, docptr, CDSNControl); + /* 11.4.3 -- 4 NOPs after CSDNControl write */ + DoC_Delay(doc, 4); +} + +static void doc2001plus_command (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /* + * Must terminate write pipeline before sending any commands + * to the device. + */ + if (command == NAND_CMD_PAGEPROG) { + WriteDOC(0x00, docptr, Mplus_WritePipeTerm); + WriteDOC(0x00, docptr, Mplus_WritePipeTerm); + } + + /* + * Write out the command to the device. + */ + if (command == NAND_CMD_SEQIN) { + int readcmd; + + if (column >= mtd->oobblock) { + /* OOB area */ + column -= mtd->oobblock; + readcmd = NAND_CMD_READOOB; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + readcmd = NAND_CMD_READ0; + } else { + column -= 256; + readcmd = NAND_CMD_READ1; + } + WriteDOC(readcmd, docptr, Mplus_FlashCmd); + } + WriteDOC(command, docptr, Mplus_FlashCmd); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + + if (column != -1 || page_addr != -1) { + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + WriteDOC(column, docptr, Mplus_FlashAddress); + } + if (page_addr != -1) { + WriteDOC((unsigned char) (page_addr & 0xff), docptr, Mplus_FlashAddress); + WriteDOC((unsigned char) ((page_addr >> 8) & 0xff), docptr, Mplus_FlashAddress); + /* One more address cycle for higher density devices */ + if (this->chipsize & 0x0c000000) { + WriteDOC((unsigned char) ((page_addr >> 16) & 0x0f), docptr, Mplus_FlashAddress); + printk("high density\n"); + } + } + WriteDOC(0, docptr, Mplus_WritePipeTerm); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + /* deassert ALE */ + if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || command == NAND_CMD_READOOB || command == NAND_CMD_READID) + WriteDOC(0, docptr, Mplus_FlashControl); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_SEQIN: + case NAND_CMD_STATUS: + return; + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + WriteDOC(NAND_CMD_STATUS, docptr, Mplus_FlashCmd); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + +static int doc200x_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + if (DoC_is_MillenniumPlus(doc)) { + /* 11.4.2 -- must NOP four times before checking FR/B# */ + DoC_Delay(doc, 4); + if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) { + if(debug) + printk("not ready\n"); + return 0; + } + if (debug)printk("was ready\n"); + return 1; + } else { + /* 11.4.2 -- must NOP four times before checking FR/B# */ + DoC_Delay(doc, 4); + if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) { + if(debug) + printk("not ready\n"); + return 0; + } + /* 11.4.2 -- Must NOP twice if it's ready */ + DoC_Delay(doc, 2); + if (debug)printk("was ready\n"); + return 1; + } +} + +static int doc200x_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + /* This is our last resort if we couldn't find or create a BBT. Just + pretend all blocks are good. */ + return 0; +} + +static void doc200x_enable_hwecc(struct mtd_info *mtd, int mode) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /* Prime the ECC engine */ + switch(mode) { + case NAND_ECC_READ: + WriteDOC(DOC_ECC_RESET, docptr, ECCConf); + WriteDOC(DOC_ECC_EN, docptr, ECCConf); + break; + case NAND_ECC_WRITE: + WriteDOC(DOC_ECC_RESET, docptr, ECCConf); + WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, ECCConf); + break; + } +} + +static void doc2001plus_enable_hwecc(struct mtd_info *mtd, int mode) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /* Prime the ECC engine */ + switch(mode) { + case NAND_ECC_READ: + WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf); + WriteDOC(DOC_ECC_EN, docptr, Mplus_ECCConf); + break; + case NAND_ECC_WRITE: + WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf); + WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, Mplus_ECCConf); + break; + } +} + +/* This code is only called on write */ +static int doc200x_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + unsigned char *ecc_code) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + int emptymatch = 1; + + /* flush the pipeline */ + if (DoC_is_2000(doc)) { + WriteDOC(doc->CDSNControl & ~CDSN_CTRL_FLASH_IO, docptr, CDSNControl); + WriteDOC(0, docptr, 2k_CDSN_IO); + WriteDOC(0, docptr, 2k_CDSN_IO); + WriteDOC(0, docptr, 2k_CDSN_IO); + WriteDOC(doc->CDSNControl, docptr, CDSNControl); + } else if (DoC_is_MillenniumPlus(doc)) { + WriteDOC(0, docptr, Mplus_NOP); + WriteDOC(0, docptr, Mplus_NOP); + WriteDOC(0, docptr, Mplus_NOP); + } else { + WriteDOC(0, docptr, NOP); + WriteDOC(0, docptr, NOP); + WriteDOC(0, docptr, NOP); + } + + for (i = 0; i < 6; i++) { + if (DoC_is_MillenniumPlus(doc)) + ecc_code[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i); + else + ecc_code[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i); + if (ecc_code[i] != empty_write_ecc[i]) + emptymatch = 0; + } + if (DoC_is_MillenniumPlus(doc)) + WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf); + else + WriteDOC(DOC_ECC_DIS, docptr, ECCConf); +#if 0 + /* If emptymatch=1, we might have an all-0xff data buffer. Check. */ + if (emptymatch) { + /* Note: this somewhat expensive test should not be triggered + often. It could be optimized away by examining the data in + the writebuf routine, and remembering the result. */ + for (i = 0; i < 512; i++) { + if (dat[i] == 0xff) continue; + emptymatch = 0; + break; + } + } + /* If emptymatch still =1, we do have an all-0xff data buffer. + Return all-0xff ecc value instead of the computed one, so + it'll look just like a freshly-erased page. */ + if (emptymatch) memset(ecc_code, 0xff, 6); +#endif + return 0; +} + +static int doc200x_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + int i, ret = 0; + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + volatile u_char dummy; + int emptymatch = 1; + + /* flush the pipeline */ + if (DoC_is_2000(doc)) { + dummy = ReadDOC(docptr, 2k_ECCStatus); + dummy = ReadDOC(docptr, 2k_ECCStatus); + dummy = ReadDOC(docptr, 2k_ECCStatus); + } else if (DoC_is_MillenniumPlus(doc)) { + dummy = ReadDOC(docptr, Mplus_ECCConf); + dummy = ReadDOC(docptr, Mplus_ECCConf); + dummy = ReadDOC(docptr, Mplus_ECCConf); + } else { + dummy = ReadDOC(docptr, ECCConf); + dummy = ReadDOC(docptr, ECCConf); + dummy = ReadDOC(docptr, ECCConf); + } + + /* Error occured ? */ + if (dummy & 0x80) { + for (i = 0; i < 6; i++) { + if (DoC_is_MillenniumPlus(doc)) + calc_ecc[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i); + else + calc_ecc[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i); + if (calc_ecc[i] != empty_read_syndrome[i]) + emptymatch = 0; + } + /* If emptymatch=1, the read syndrome is consistent with an + all-0xff data and stored ecc block. Check the stored ecc. */ + if (emptymatch) { + for (i = 0; i < 6; i++) { + if (read_ecc[i] == 0xff) continue; + emptymatch = 0; + break; + } + } + /* If emptymatch still =1, check the data block. */ + if (emptymatch) { + /* Note: this somewhat expensive test should not be triggered + often. It could be optimized away by examining the data in + the readbuf routine, and remembering the result. */ + for (i = 0; i < 512; i++) { + if (dat[i] == 0xff) continue; + emptymatch = 0; + break; + } + } + /* If emptymatch still =1, this is almost certainly a freshly- + erased block, in which case the ECC will not come out right. + We'll suppress the error and tell the caller everything's + OK. Because it is. */ + if (!emptymatch) ret = doc_ecc_decode (rs_decoder, dat, calc_ecc); + if (ret > 0) + printk(KERN_ERR "doc200x_correct_data corrected %d errors\n", ret); + } + if (DoC_is_MillenniumPlus(doc)) + WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf); + else + WriteDOC(DOC_ECC_DIS, docptr, ECCConf); + if (no_ecc_failures && (ret == -1)) { + printk(KERN_ERR "suppressing ECC failure\n"); + ret = 0; + } + return ret; +} + +/*u_char mydatabuf[528]; */ + +static struct nand_oobinfo doc200x_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 6, + .eccpos = {0, 1, 2, 3, 4, 5}, + .oobfree = { {8, 8} } +}; + +/* Find the (I)NFTL Media Header, and optionally also the mirror media header. + On sucessful return, buf will contain a copy of the media header for + further processing. id is the string to scan for, and will presumably be + either "ANAND" or "BNAND". If findmirror=1, also look for the mirror media + header. The page #s of the found media headers are placed in mh0_page and + mh1_page in the DOC private structure. */ +static int __init find_media_headers(struct mtd_info *mtd, u_char *buf, + const char *id, int findmirror) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + unsigned offs, end = (MAX_MEDIAHEADER_SCAN << this->phys_erase_shift); + int ret; + size_t retlen; + + end = min(end, mtd->size); /* paranoia */ + for (offs = 0; offs < end; offs += mtd->erasesize) { + ret = mtd->read(mtd, offs, mtd->oobblock, &retlen, buf); + if (retlen != mtd->oobblock) continue; + if (ret) { + printk(KERN_WARNING "ECC error scanning DOC at 0x%x\n", + offs); + } + if (memcmp(buf, id, 6)) continue; + printk(KERN_INFO "Found DiskOnChip %s Media Header at 0x%x\n", id, offs); + if (doc->mh0_page == -1) { + doc->mh0_page = offs >> this->page_shift; + if (!findmirror) return 1; + continue; + } + doc->mh1_page = offs >> this->page_shift; + return 2; + } + if (doc->mh0_page == -1) { + printk(KERN_WARNING "DiskOnChip %s Media Header not found.\n", id); + return 0; + } + /* Only one mediaheader was found. We want buf to contain a + mediaheader on return, so we'll have to re-read the one we found. */ + offs = doc->mh0_page << this->page_shift; + ret = mtd->read(mtd, offs, mtd->oobblock, &retlen, buf); + if (retlen != mtd->oobblock) { + /* Insanity. Give up. */ + printk(KERN_ERR "Read DiskOnChip Media Header once, but can't reread it???\n"); + return 0; + } + return 1; +} + +static inline int __init nftl_partscan(struct mtd_info *mtd, + struct mtd_partition *parts) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + int ret = 0; + u_char *buf; + struct NFTLMediaHeader *mh; + const unsigned psize = 1 << this->page_shift; + unsigned blocks, maxblocks; + int offs, numheaders; + + buf = kmalloc(mtd->oobblock, GFP_KERNEL); + if (!buf) { + printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n"); + return 0; + } + if (!(numheaders=find_media_headers(mtd, buf, "ANAND", 1))) goto out; + mh = (struct NFTLMediaHeader *) buf; + +/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */ +/* if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */ + printk(KERN_INFO " DataOrgID = %s\n" + " NumEraseUnits = %d\n" + " FirstPhysicalEUN = %d\n" + " FormattedSize = %d\n" + " UnitSizeFactor = %d\n", + mh->DataOrgID, mh->NumEraseUnits, + mh->FirstPhysicalEUN, mh->FormattedSize, + mh->UnitSizeFactor); +/*#endif */ + + blocks = mtd->size >> this->phys_erase_shift; + maxblocks = min(32768U, mtd->erasesize - psize); + + if (mh->UnitSizeFactor == 0x00) { + /* Auto-determine UnitSizeFactor. The constraints are: + - There can be at most 32768 virtual blocks. + - There can be at most (virtual block size - page size) + virtual blocks (because MediaHeader+BBT must fit in 1). + */ + mh->UnitSizeFactor = 0xff; + while (blocks > maxblocks) { + blocks >>= 1; + maxblocks = min(32768U, (maxblocks << 1) + psize); + mh->UnitSizeFactor--; + } + printk(KERN_WARNING "UnitSizeFactor=0x00 detected. Correct value is assumed to be 0x%02x.\n", mh->UnitSizeFactor); + } + + /* NOTE: The lines below modify internal variables of the NAND and MTD + layers; variables with have already been configured by nand_scan. + Unfortunately, we didn't know before this point what these values + should be. Thus, this code is somewhat dependant on the exact + implementation of the NAND layer. */ + if (mh->UnitSizeFactor != 0xff) { + this->bbt_erase_shift += (0xff - mh->UnitSizeFactor); + mtd->erasesize <<= (0xff - mh->UnitSizeFactor); + printk(KERN_INFO "Setting virtual erase size to %d\n", mtd->erasesize); + blocks = mtd->size >> this->bbt_erase_shift; + maxblocks = min(32768U, mtd->erasesize - psize); + } + + if (blocks > maxblocks) { + printk(KERN_ERR "UnitSizeFactor of 0x%02x is inconsistent with device size. Aborting.\n", mh->UnitSizeFactor); + goto out; + } + + /* Skip past the media headers. */ + offs = max(doc->mh0_page, doc->mh1_page); + offs <<= this->page_shift; + offs += mtd->erasesize; + + /*parts[0].name = " DiskOnChip Boot / Media Header partition"; */ + /*parts[0].offset = 0; */ + /*parts[0].size = offs; */ + + parts[0].name = " DiskOnChip BDTL partition"; + parts[0].offset = offs; + parts[0].size = (mh->NumEraseUnits - numheaders) << this->bbt_erase_shift; + + offs += parts[0].size; + if (offs < mtd->size) { + parts[1].name = " DiskOnChip Remainder partition"; + parts[1].offset = offs; + parts[1].size = mtd->size - offs; + ret = 2; + goto out; + } + ret = 1; +out: + kfree(buf); + return ret; +} + +/* This is a stripped-down copy of the code in inftlmount.c */ +static inline int __init inftl_partscan(struct mtd_info *mtd, + struct mtd_partition *parts) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + int ret = 0; + u_char *buf; + struct INFTLMediaHeader *mh; + struct INFTLPartition *ip; + int numparts = 0; + int blocks; + int vshift, lastvunit = 0; + int i; + int end = mtd->size; + + if (inftl_bbt_write) + end -= (INFTL_BBT_RESERVED_BLOCKS << this->phys_erase_shift); + + buf = kmalloc(mtd->oobblock, GFP_KERNEL); + if (!buf) { + printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n"); + return 0; + } + + if (!find_media_headers(mtd, buf, "BNAND", 0)) goto out; + doc->mh1_page = doc->mh0_page + (4096 >> this->page_shift); + mh = (struct INFTLMediaHeader *) buf; + + mh->NoOfBootImageBlocks = le32_to_cpu(mh->NoOfBootImageBlocks); + mh->NoOfBinaryPartitions = le32_to_cpu(mh->NoOfBinaryPartitions); + mh->NoOfBDTLPartitions = le32_to_cpu(mh->NoOfBDTLPartitions); + mh->BlockMultiplierBits = le32_to_cpu(mh->BlockMultiplierBits); + mh->FormatFlags = le32_to_cpu(mh->FormatFlags); + mh->PercentUsed = le32_to_cpu(mh->PercentUsed); + +/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */ +/* if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */ + printk(KERN_INFO " bootRecordID = %s\n" + " NoOfBootImageBlocks = %d\n" + " NoOfBinaryPartitions = %d\n" + " NoOfBDTLPartitions = %d\n" + " BlockMultiplerBits = %d\n" + " FormatFlgs = %d\n" + " OsakVersion = %d.%d.%d.%d\n" + " PercentUsed = %d\n", + mh->bootRecordID, mh->NoOfBootImageBlocks, + mh->NoOfBinaryPartitions, + mh->NoOfBDTLPartitions, + mh->BlockMultiplierBits, mh->FormatFlags, + ((unsigned char *) &mh->OsakVersion)[0] & 0xf, + ((unsigned char *) &mh->OsakVersion)[1] & 0xf, + ((unsigned char *) &mh->OsakVersion)[2] & 0xf, + ((unsigned char *) &mh->OsakVersion)[3] & 0xf, + mh->PercentUsed); +/*#endif */ + + vshift = this->phys_erase_shift + mh->BlockMultiplierBits; + + blocks = mtd->size >> vshift; + if (blocks > 32768) { + printk(KERN_ERR "BlockMultiplierBits=%d is inconsistent with device size. Aborting.\n", mh->BlockMultiplierBits); + goto out; + } + + blocks = doc->chips_per_floor << (this->chip_shift - this->phys_erase_shift); + if (inftl_bbt_write && (blocks > mtd->erasesize)) { + printk(KERN_ERR "Writeable BBTs spanning more than one erase block are not yet supported. FIX ME!\n"); + goto out; + } + + /* Scan the partitions */ + for (i = 0; (i < 4); i++) { + ip = &(mh->Partitions[i]); + ip->virtualUnits = le32_to_cpu(ip->virtualUnits); + ip->firstUnit = le32_to_cpu(ip->firstUnit); + ip->lastUnit = le32_to_cpu(ip->lastUnit); + ip->flags = le32_to_cpu(ip->flags); + ip->spareUnits = le32_to_cpu(ip->spareUnits); + ip->Reserved0 = le32_to_cpu(ip->Reserved0); + +/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */ +/* if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */ + printk(KERN_INFO " PARTITION[%d] ->\n" + " virtualUnits = %d\n" + " firstUnit = %d\n" + " lastUnit = %d\n" + " flags = 0x%x\n" + " spareUnits = %d\n", + i, ip->virtualUnits, ip->firstUnit, + ip->lastUnit, ip->flags, + ip->spareUnits); +/*#endif */ + +/* + if ((i == 0) && (ip->firstUnit > 0)) { + parts[0].name = " DiskOnChip IPL / Media Header partition"; + parts[0].offset = 0; + parts[0].size = mtd->erasesize * ip->firstUnit; + numparts = 1; + } +*/ + + if (ip->flags & INFTL_BINARY) + parts[numparts].name = " DiskOnChip BDK partition"; + else + parts[numparts].name = " DiskOnChip BDTL partition"; + parts[numparts].offset = ip->firstUnit << vshift; + parts[numparts].size = (1 + ip->lastUnit - ip->firstUnit) << vshift; + numparts++; + if (ip->lastUnit > lastvunit) lastvunit = ip->lastUnit; + if (ip->flags & INFTL_LAST) break; + } + lastvunit++; + if ((lastvunit << vshift) < end) { + parts[numparts].name = " DiskOnChip Remainder partition"; + parts[numparts].offset = lastvunit << vshift; + parts[numparts].size = end - parts[numparts].offset; + numparts++; + } + ret = numparts; +out: + kfree(buf); + return ret; +} + +static int __init nftl_scan_bbt(struct mtd_info *mtd) +{ + int ret, numparts; + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + struct mtd_partition parts[2]; + + memset((char *) parts, 0, sizeof(parts)); + /* On NFTL, we have to find the media headers before we can read the + BBTs, since they're stored in the media header eraseblocks. */ + numparts = nftl_partscan(mtd, parts); + if (!numparts) return -EIO; + this->bbt_td->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT | + NAND_BBT_SAVECONTENT | NAND_BBT_WRITE | + NAND_BBT_VERSION; + this->bbt_td->veroffs = 7; + this->bbt_td->pages[0] = doc->mh0_page + 1; + if (doc->mh1_page != -1) { + this->bbt_md->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT | + NAND_BBT_SAVECONTENT | NAND_BBT_WRITE | + NAND_BBT_VERSION; + this->bbt_md->veroffs = 7; + this->bbt_md->pages[0] = doc->mh1_page + 1; + } else { + this->bbt_md = NULL; + } + + /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set. + At least as nand_bbt.c is currently written. */ + if ((ret = nand_scan_bbt(mtd, NULL))) + return ret; + add_mtd_device(mtd); +#ifdef CONFIG_MTD_PARTITIONS + if (!no_autopart) + add_mtd_partitions(mtd, parts, numparts); +#endif + return 0; +} + +static int __init inftl_scan_bbt(struct mtd_info *mtd) +{ + int ret, numparts; + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + struct mtd_partition parts[5]; + + if (this->numchips > doc->chips_per_floor) { + printk(KERN_ERR "Multi-floor INFTL devices not yet supported.\n"); + return -EIO; + } + + if (DoC_is_MillenniumPlus(doc)) { + this->bbt_td->options = NAND_BBT_2BIT | NAND_BBT_ABSPAGE; + if (inftl_bbt_write) + this->bbt_td->options |= NAND_BBT_WRITE; + this->bbt_td->pages[0] = 2; + this->bbt_md = NULL; + } else { + this->bbt_td->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | + NAND_BBT_VERSION; + if (inftl_bbt_write) + this->bbt_td->options |= NAND_BBT_WRITE; + this->bbt_td->offs = 8; + this->bbt_td->len = 8; + this->bbt_td->veroffs = 7; + this->bbt_td->maxblocks = INFTL_BBT_RESERVED_BLOCKS; + this->bbt_td->reserved_block_code = 0x01; + this->bbt_td->pattern = "MSYS_BBT"; + + this->bbt_md->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | + NAND_BBT_VERSION; + if (inftl_bbt_write) + this->bbt_md->options |= NAND_BBT_WRITE; + this->bbt_md->offs = 8; + this->bbt_md->len = 8; + this->bbt_md->veroffs = 7; + this->bbt_md->maxblocks = INFTL_BBT_RESERVED_BLOCKS; + this->bbt_md->reserved_block_code = 0x01; + this->bbt_md->pattern = "TBB_SYSM"; + } + + /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set. + At least as nand_bbt.c is currently written. */ + if ((ret = nand_scan_bbt(mtd, NULL))) + return ret; + memset((char *) parts, 0, sizeof(parts)); + numparts = inftl_partscan(mtd, parts); + /* At least for now, require the INFTL Media Header. We could probably + do without it for non-INFTL use, since all it gives us is + autopartitioning, but I want to give it more thought. */ + if (!numparts) return -EIO; + add_mtd_device(mtd); +#ifdef CONFIG_MTD_PARTITIONS + if (!no_autopart) + add_mtd_partitions(mtd, parts, numparts); +#endif + return 0; +} + +static inline int __init doc2000_init(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + + this->write_byte = doc2000_write_byte; + this->read_byte = doc2000_read_byte; + this->write_buf = doc2000_writebuf; + this->read_buf = doc2000_readbuf; + this->verify_buf = doc2000_verifybuf; + this->scan_bbt = nftl_scan_bbt; + + doc->CDSNControl = CDSN_CTRL_FLASH_IO | CDSN_CTRL_ECC_IO; + doc2000_count_chips(mtd); + mtd->name = "DiskOnChip 2000 (NFTL Model)"; + return (4 * doc->chips_per_floor); +} + +static inline int __init doc2001_init(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + + this->write_byte = doc2001_write_byte; + this->read_byte = doc2001_read_byte; + this->write_buf = doc2001_writebuf; + this->read_buf = doc2001_readbuf; + this->verify_buf = doc2001_verifybuf; + + ReadDOC(doc->virtadr, ChipID); + ReadDOC(doc->virtadr, ChipID); + ReadDOC(doc->virtadr, ChipID); + if (ReadDOC(doc->virtadr, ChipID) != DOC_ChipID_DocMil) { + /* It's not a Millennium; it's one of the newer + DiskOnChip 2000 units with a similar ASIC. + Treat it like a Millennium, except that it + can have multiple chips. */ + doc2000_count_chips(mtd); + mtd->name = "DiskOnChip 2000 (INFTL Model)"; + this->scan_bbt = inftl_scan_bbt; + return (4 * doc->chips_per_floor); + } else { + /* Bog-standard Millennium */ + doc->chips_per_floor = 1; + mtd->name = "DiskOnChip Millennium"; + this->scan_bbt = nftl_scan_bbt; + return 1; + } +} + +static inline int __init doc2001plus_init(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + + this->write_byte = NULL; + this->read_byte = doc2001plus_read_byte; + this->write_buf = doc2001plus_writebuf; + this->read_buf = doc2001plus_readbuf; + this->verify_buf = doc2001plus_verifybuf; + this->scan_bbt = inftl_scan_bbt; + this->hwcontrol = NULL; + this->select_chip = doc2001plus_select_chip; + this->cmdfunc = doc2001plus_command; + this->enable_hwecc = doc2001plus_enable_hwecc; + + doc->chips_per_floor = 1; + mtd->name = "DiskOnChip Millennium Plus"; + + return 1; +} + +static inline int __init doc_probe(unsigned long physadr) +{ + unsigned char ChipID; + struct mtd_info *mtd; + struct nand_chip *nand; + struct doc_priv *doc; + void __iomem *virtadr; + unsigned char save_control; + unsigned char tmp, tmpb, tmpc; + int reg, len, numchips; + int ret = 0; + + virtadr = ioremap(physadr, DOC_IOREMAP_LEN); + if (!virtadr) { + printk(KERN_ERR "Diskonchip ioremap failed: 0x%x bytes at 0x%lx\n", DOC_IOREMAP_LEN, physadr); + return -EIO; + } + + /* It's not possible to cleanly detect the DiskOnChip - the + * bootup procedure will put the device into reset mode, and + * it's not possible to talk to it without actually writing + * to the DOCControl register. So we store the current contents + * of the DOCControl register's location, in case we later decide + * that it's not a DiskOnChip, and want to put it back how we + * found it. + */ + save_control = ReadDOC(virtadr, DOCControl); + + /* Reset the DiskOnChip ASIC */ + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, + virtadr, DOCControl); + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, + virtadr, DOCControl); + + /* Enable the DiskOnChip ASIC */ + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, + virtadr, DOCControl); + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, + virtadr, DOCControl); + + ChipID = ReadDOC(virtadr, ChipID); + + switch(ChipID) { + case DOC_ChipID_Doc2k: + reg = DoC_2k_ECCStatus; + break; + case DOC_ChipID_DocMil: + reg = DoC_ECCConf; + break; + case DOC_ChipID_DocMilPlus16: + case DOC_ChipID_DocMilPlus32: + case 0: + /* Possible Millennium Plus, need to do more checks */ + /* Possibly release from power down mode */ + for (tmp = 0; (tmp < 4); tmp++) + ReadDOC(virtadr, Mplus_Power); + + /* Reset the Millennium Plus ASIC */ + tmp = DOC_MODE_RESET | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | + DOC_MODE_BDECT; + WriteDOC(tmp, virtadr, Mplus_DOCControl); + WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm); + + mdelay(1); + /* Enable the Millennium Plus ASIC */ + tmp = DOC_MODE_NORMAL | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | + DOC_MODE_BDECT; + WriteDOC(tmp, virtadr, Mplus_DOCControl); + WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm); + mdelay(1); + + ChipID = ReadDOC(virtadr, ChipID); + + switch (ChipID) { + case DOC_ChipID_DocMilPlus16: + reg = DoC_Mplus_Toggle; + break; + case DOC_ChipID_DocMilPlus32: + printk(KERN_ERR "DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n"); + default: + ret = -ENODEV; + goto notfound; + } + break; + + default: + ret = -ENODEV; + goto notfound; + } + /* Check the TOGGLE bit in the ECC register */ + tmp = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; + tmpb = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; + tmpc = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; + if ((tmp == tmpb) || (tmp != tmpc)) { + printk(KERN_WARNING "Possible DiskOnChip at 0x%lx failed TOGGLE test, dropping.\n", physadr); + ret = -ENODEV; + goto notfound; + } + + for (mtd = doclist; mtd; mtd = doc->nextdoc) { + unsigned char oldval; + unsigned char newval; + nand = mtd->priv; + doc = nand->priv; + /* Use the alias resolution register to determine if this is + in fact the same DOC aliased to a new address. If writes + to one chip's alias resolution register change the value on + the other chip, they're the same chip. */ + if (ChipID == DOC_ChipID_DocMilPlus16) { + oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution); + newval = ReadDOC(virtadr, Mplus_AliasResolution); + } else { + oldval = ReadDOC(doc->virtadr, AliasResolution); + newval = ReadDOC(virtadr, AliasResolution); + } + if (oldval != newval) + continue; + if (ChipID == DOC_ChipID_DocMilPlus16) { + WriteDOC(~newval, virtadr, Mplus_AliasResolution); + oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution); + WriteDOC(newval, virtadr, Mplus_AliasResolution); /* restore it */ + } else { + WriteDOC(~newval, virtadr, AliasResolution); + oldval = ReadDOC(doc->virtadr, AliasResolution); + WriteDOC(newval, virtadr, AliasResolution); /* restore it */ + } + newval = ~newval; + if (oldval == newval) { + printk(KERN_DEBUG "Found alias of DOC at 0x%lx to 0x%lx\n", doc->physadr, physadr); + goto notfound; + } + } + + printk(KERN_NOTICE "DiskOnChip found at 0x%lx\n", physadr); + + len = sizeof(struct mtd_info) + + sizeof(struct nand_chip) + + sizeof(struct doc_priv) + + (2 * sizeof(struct nand_bbt_descr)); + mtd = kmalloc(len, GFP_KERNEL); + if (!mtd) { + printk(KERN_ERR "DiskOnChip kmalloc (%d bytes) failed!\n", len); + ret = -ENOMEM; + goto fail; + } + memset(mtd, 0, len); + + nand = (struct nand_chip *) (mtd + 1); + doc = (struct doc_priv *) (nand + 1); + nand->bbt_td = (struct nand_bbt_descr *) (doc + 1); + nand->bbt_md = nand->bbt_td + 1; + + mtd->priv = nand; + mtd->owner = THIS_MODULE; + + nand->priv = doc; + nand->select_chip = doc200x_select_chip; + nand->hwcontrol = doc200x_hwcontrol; + nand->dev_ready = doc200x_dev_ready; + nand->waitfunc = doc200x_wait; + nand->block_bad = doc200x_block_bad; + nand->enable_hwecc = doc200x_enable_hwecc; + nand->calculate_ecc = doc200x_calculate_ecc; + nand->correct_data = doc200x_correct_data; + + nand->autooob = &doc200x_oobinfo; + nand->eccmode = NAND_ECC_HW6_512; + nand->options = NAND_USE_FLASH_BBT | NAND_HWECC_SYNDROME; + + doc->physadr = physadr; + doc->virtadr = virtadr; + doc->ChipID = ChipID; + doc->curfloor = -1; + doc->curchip = -1; + doc->mh0_page = -1; + doc->mh1_page = -1; + doc->nextdoc = doclist; + + if (ChipID == DOC_ChipID_Doc2k) + numchips = doc2000_init(mtd); + else if (ChipID == DOC_ChipID_DocMilPlus16) + numchips = doc2001plus_init(mtd); + else + numchips = doc2001_init(mtd); + + if ((ret = nand_scan(mtd, numchips))) { + /* DBB note: i believe nand_release is necessary here, as + buffers may have been allocated in nand_base. Check with + Thomas. FIX ME! */ + /* nand_release will call del_mtd_device, but we haven't yet + added it. This is handled without incident by + del_mtd_device, as far as I can tell. */ + nand_release(mtd); + kfree(mtd); + goto fail; + } + + /* Success! */ + doclist = mtd; + return 0; + +notfound: + /* Put back the contents of the DOCControl register, in case it's not + actually a DiskOnChip. */ + WriteDOC(save_control, virtadr, DOCControl); +fail: + iounmap(virtadr); + return ret; +} + +static void release_nanddoc(void) +{ + struct mtd_info *mtd, *nextmtd; + struct nand_chip *nand; + struct doc_priv *doc; + + for (mtd = doclist; mtd; mtd = nextmtd) { + nand = mtd->priv; + doc = nand->priv; + + nextmtd = doc->nextdoc; + nand_release(mtd); + iounmap(doc->virtadr); + kfree(mtd); + } +} + +static int __init init_nanddoc(void) +{ + int i, ret = 0; + + /* We could create the decoder on demand, if memory is a concern. + * This way we have it handy, if an error happens + * + * Symbolsize is 10 (bits) + * Primitve polynomial is x^10+x^3+1 + * first consecutive root is 510 + * primitve element to generate roots = 1 + * generator polinomial degree = 4 + */ + rs_decoder = init_rs(10, 0x409, FCR, 1, NROOTS); + if (!rs_decoder) { + printk (KERN_ERR "DiskOnChip: Could not create a RS decoder\n"); + return -ENOMEM; + } + + if (doc_config_location) { + printk(KERN_INFO "Using configured DiskOnChip probe address 0x%lx\n", doc_config_location); + ret = doc_probe(doc_config_location); + if (ret < 0) + goto outerr; + } else { + for (i=0; (doc_locations[i] != 0xffffffff); i++) { + doc_probe(doc_locations[i]); + } + } + /* No banner message any more. Print a message if no DiskOnChip + found, so the user knows we at least tried. */ + if (!doclist) { + printk(KERN_INFO "No valid DiskOnChip devices found\n"); + ret = -ENODEV; + goto outerr; + } + return 0; +outerr: + free_rs(rs_decoder); + return ret; +} + +static void __exit cleanup_nanddoc(void) +{ + /* Cleanup the nand/DoC resources */ + release_nanddoc(); + + /* Free the reed solomon resources */ + if (rs_decoder) { + free_rs(rs_decoder); + } +} + +module_init(init_nanddoc); +module_exit(cleanup_nanddoc); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("David Woodhouse "); +MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n"); +#endif diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c new file mode 100644 index 0000000..7cd6391 --- /dev/null +++ b/drivers/nand/nand.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2005 + * 2N Telekomunikace, a.s. + * Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include +#include + +#ifndef CFG_NAND_BASE_LIST +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#endif + +int nand_curr_device = -1; +nand_info_t nand_info[CFG_MAX_NAND_DEVICE]; + +static struct nand_chip nand_chip[CFG_MAX_NAND_DEVICE]; +static ulong base_address[CFG_MAX_NAND_DEVICE] = CFG_NAND_BASE_LIST; + +static const char default_nand_name[] = "nand"; + +extern int board_nand_init(struct nand_chip *nand); + +static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand, + ulong base_addr) +{ + mtd->priv = nand; + + nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; + if (board_nand_init(nand) == 0) { + if (nand_scan(mtd, 1) == 0) { + if (!mtd->name) + mtd->name = (char *)default_nand_name; + } else + mtd->name = NULL; + } else { + mtd->name = NULL; + mtd->size = 0; + } +} + +void nand_init(void) +{ + int i; + unsigned int size = 0; + for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) { + nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]); + size += nand_info[i].size; + if (nand_curr_device == -1) + nand_curr_device = i; + } + printf("%lu MB\n", size / (1024 * 1024)); + +#ifdef CFG_NAND_SELECT_DEVICE + /* + * Select the chip in the board/cpu specific driver + */ + board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device); +#endif +} + +#endif diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c new file mode 100644 index 0000000..dcfcfdf --- /dev/null +++ b/drivers/nand/nand_base.c @@ -0,0 +1,3007 @@ +/* + * drivers/mtd/nand.c + * + * Overview: + * This is the generic MTD driver for NAND flash devices. It should be + * capable of working with almost all NAND chips currently available. + * Basic support for AG-AND chips is provided. + * + * Additional technical information is available on + * http://www.linux-mtd.infradead.org/tech/nand.html + * + * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) + * 2002 Thomas Gleixner (tglx@linutronix.de) + * + * 02-08-2004 tglx: support for strange chips, which cannot auto increment + * pages on read / read_oob + * + * 03-17-2004 tglx: Check ready before auto increment check. Simon Bayes + * pointed this out, as he marked an auto increment capable chip + * as NOAUTOINCR in the board driver. + * Make reads over block boundaries work too + * + * 04-14-2004 tglx: first working version for 2k page size chips + * + * 05-19-2004 tglx: Basic support for Renesas AG-AND chips + * + * 09-24-2004 tglx: add support for hardware controllers (e.g. ECC) shared + * among multiple independend devices. Suggestions and initial patch + * from Ben Dooks + * + * Credits: + * David Woodhouse for adding multichip support + * + * Aleph One Ltd. and Toby Churchill Ltd. for supporting the + * rework for 2K page size chips + * + * TODO: + * Enable cached programming for 2k page size chips + * Check, if mtd->ecctype should be set to MTD_ECC_HW + * if we have HW ecc support. + * The AG-AND chips have nice features for speed improvement, + * which are not supported yet. Read / program 4 pages in one go. + * + * $Id: nand_base.c,v 1.126 2004/12/13 11:22:25 lavinen Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/* XXX U-BOOT XXX */ +#if 0 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MTD_PARTITIONS +#include +#endif + +#endif + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_JFFS2_NAND +#include +#endif + +/* Define default oob placement schemes for large and small page devices */ +static struct nand_oobinfo nand_oob_8 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 3, + .eccpos = {0, 1, 2}, + .oobfree = { {3, 2}, {6, 2} } +}; + +static struct nand_oobinfo nand_oob_16 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 6, + .eccpos = {0, 1, 2, 3, 6, 7}, + .oobfree = { {8, 8} } +}; + +static struct nand_oobinfo nand_oob_64 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 24, + .eccpos = { + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63}, + .oobfree = { {2, 38} } /* {2, 38} {6, 34}*/ +}; + +/* RS 64 ECC */ +static struct nand_oobinfo nand_oob_64_rs = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 40, + .eccpos = { + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63}, + .oobfree = { {6,18} } +}; + +static struct nand_oobinfo nand_oob_128 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 48, + .eccpos = { + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127}, + .oobfree = { {2, 78} } +}; + +/* RS 128 ECC */ +static struct nand_oobinfo nand_oob_128_rs = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 80, + .eccpos = { + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127}, + .oobfree = { {2, 46} } +}; + +static struct nand_oobinfo nand_oob_218 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 48, + .eccpos = { + 170, 171, 172, 173, 174, 175, 176, 177, + 178, 179, 180, 181, 182, 183, 184, 185, + 186, 187, 188, 189, 190, 191, 192, 193, + 194, 195, 196, 197, 198, 199, 200, 201, + 202, 203, 204, 205, 206, 207, 208, 209, + 210, 211, 212, 213, 214, 215, 216, 217}, + .oobfree = {{6,164}} +}; +/* RS 218 ECC */ +static struct nand_oobinfo nand_oob_218_rs = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 80, + .eccpos = { + 138, 139, 140, 141, 142, 143, 144, 145, + 146, 147, 148, 149, 150, 151, 152, 153, + 154, 155, 156, 157, 158, 159, 160, 161, + 162, 163, 164, 165, 166, 167, 168, 169, + 170, 171, 172, 173, 174, 175, 176, 177, + 178, 179, 180, 181, 182, 183, 184, 185, + 186, 187, 188, 189, 190, 191, 192, 193, + 194, 195, 196, 197, 198, 199, 200, 201, + 202, 203, 204, 205, 206, 207, 208, 209, + 210, 211, 212, 213, 214, 215, 216, 217}, + .oobfree = {{6,132}} +}; +/* This is used for padding purposes in nand_write_oob */ +static u_char ffchars[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +}; + +/* + * NAND low-level MTD interface functions + */ +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len); + +static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf); +static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, + size_t * retlen, u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel); +static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf); +static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf); +static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, + size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel); +static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char *buf); +/* XXX U-BOOT XXX */ +#if 0 +static int nand_writev (struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t * retlen); +static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); +#endif +static int nand_erase (struct mtd_info *mtd, struct erase_info *instr); +static void nand_sync (struct mtd_info *mtd); + +/* Some internal functions */ +static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf, + struct nand_oobinfo *oobsel, int mode); +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE +static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int page, int numpages, + u_char *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode); +#else +#define nand_verify_pages(...) (0) +#endif + +static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state); + +int nandenv = 0; +extern int nandenvECC; +/** + * nand_release_device - [GENERIC] release chip + * @mtd: MTD device structure + * + * Deselect, release chip lock and wake up anyone waiting on the device + */ +/* XXX U-BOOT XXX */ +#if 0 +static void nand_release_device (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + /* De-select the NAND device */ + this->select_chip(mtd, -1); + /* Do we have a hardware controller ? */ + if (this->controller) { + spin_lock(&this->controller->lock); + this->controller->active = NULL; + spin_unlock(&this->controller->lock); + } + /* Release the chip */ + spin_lock (&this->chip_lock); + this->state = FL_READY; + wake_up (&this->wq); + spin_unlock (&this->chip_lock); +} +#else +static void nand_release_device (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + this->select_chip(mtd, -1); /* De-select the NAND device */ +} +#endif + +/** + * nand_read_byte - [DEFAULT] read one byte from the chip + * @mtd: MTD device structure + * + * Default read function for 8bit buswith + */ +static u_char nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return readb(this->IO_ADDR_R); +} + +/** + * nand_write_byte - [DEFAULT] write one byte to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + * + * Default write function for 8it buswith + */ +static void nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *this = mtd->priv; + writeb(byte, this->IO_ADDR_W); +} + +/** + * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip + * @mtd: MTD device structure + * + * Default read function for 16bit buswith with + * endianess conversion + */ +static u_char nand_read_byte16(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); +} + +/** + * nand_write_byte16 - [DEFAULT] write one byte endianess aware to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + * + * Default write function for 16bit buswith with + * endianess conversion + */ +static void nand_write_byte16(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *this = mtd->priv; + writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); +} + +/** + * nand_read_word - [DEFAULT] read one word from the chip + * @mtd: MTD device structure + * + * Default read function for 16bit buswith without + * endianess conversion + */ +static u16 nand_read_word(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return readw(this->IO_ADDR_R); +} + +/** + * nand_write_word - [DEFAULT] write one word to the chip + * @mtd: MTD device structure + * @word: data word to write + * + * Default write function for 16bit buswith without + * endianess conversion + */ +static void nand_write_word(struct mtd_info *mtd, u16 word) +{ + struct nand_chip *this = mtd->priv; + writew(word, this->IO_ADDR_W); +} + +/** + * nand_select_chip - [DEFAULT] control CE line + * @mtd: MTD device structure + * @chip: chipnumber to select, -1 for deselect + * + * Default select function for 1 chip devices. + */ +static void nand_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *this = mtd->priv; +#if defined(MV78XX0) + unsigned int *p = (unsigned int *)CFG_PT_BASE(whoAmI()) + 6; +#else + unsigned int *p = (unsigned int *)CFG_PT_BASE + 6; +#endif + unsigned int dummy = 0, dummy1 = 0; + static char *env = NULL, *env1 = NULL; + + if(!env) + env = getenv("enaMonExt"); + if(env != NULL && (strcmp(env,"yes") == 0 || strcmp(env,"YES") == 0)) + { + dummy = 1; + if(!env1) + env1 = getenv("nandEccAcc"); + if(env1 != NULL && (strcmp(env1,"yes") == 0 || strcmp(env1,"YES") == 0)) + dummy1 = 1; + } + + switch(chip) { + case -1: + this->hwcontrol(mtd, NAND_CTL_CLRNCE); + if(dummy == 1 && dummy1 == 1) + { + /* Change Uboot PTE to non cacheable when done */ + *p = (0xc12 | (6 << 20)); + dummy = (unsigned int)p; + /* Flush TLB and cache */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c14, 1\n":: "r" (dummy)); /* Flush D cache PTE */ + __asm__ __volatile__("mcr p15, 1, %0, c15, c10, 1\n":: "r" (dummy)); /* L2 flush */ + dummy= 0x600000; + dummy1= 0x700000; + __asm__ __volatile__("mcr p15, 5, %0, c15, c15, 0\n":: "r" (dummy)); + __asm__ __volatile__("mcr p15, 5, %0, c15, c15, 1\n":: "r" (dummy1)); + __asm__ __volatile__("mcr p15, 1, %0, c15, c9, 4\n":: "r" (dummy)); + __asm__ __volatile__("mcr p15, 1, %0, c15, c9, 5\n":: "r" (dummy1)); + __asm__ __volatile__("mcr p15, 1, %0, c15, c11, 4\n":: "r" (dummy)); + __asm__ __volatile__("mcr p15, 1, %0, c15, c11, 5\n":: "r" (dummy1)); + __asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0\n":: "r" (dummy)); /* TLB invalidate */ + } + break; + case 0: + this->hwcontrol(mtd, NAND_CTL_SETNCE); + if(dummy == 1 && dummy1 == 1) + { + /* Change Uboot PTE to cacheable to accelerate ECC calculation */ + *p = (0xc1e | (6 << 20)); + dummy= (unsigned int)p; + /* Flush TLB and cache */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c14, 1\n":: "r" (dummy)); + __asm__ __volatile__("mcr p15, 1, %0, c15, c10, 1\n":: "r" (dummy)); /* L2 flush */ + dummy= 0x600000; + dummy1= 0x700000; + __asm__ __volatile__("mcr p15, 5, %0, c15, c15, 0\n":: "r" (dummy)); + __asm__ __volatile__("mcr p15, 5, %0, c15, c15, 1\n":: "r" (dummy1)); + __asm__ __volatile__("mcr p15, 1, %0, c15, c9, 4\n":: "r" (dummy)); + __asm__ __volatile__("mcr p15, 1, %0, c15, c9, 5\n":: "r" (dummy1)); + __asm__ __volatile__("mcr p15, 1, %0, c15, c11, 4\n":: "r" (dummy)); + __asm__ __volatile__("mcr p15, 1, %0, c15, c11, 5\n":: "r" (dummy1)); + __asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0\n":: "r" (dummy)); + } + break; + + default: + BUG(); + } +} + +/** + * nand_write_buf - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 8bit buswith + */ +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; iIO_ADDR_W); +} + +/** + * nand_read_buf - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 8bit buswith + */ +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u32 *p = (u32 *) buf; + + if(((u32)buf % 4) == 0 && (len % 4) == 0) + { + len >>= 2; + for (i=0; iIO_ADDR_R)); + } + else + { + for (i=0; iIO_ADDR_R); + } +} + +/** + * nand_verify_buf - [DEFAULT] Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + * + * Default verify function for 8bit buswith + */ +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u32 *p = (u32 *) buf; + + if(((u32)buf % 4) == 0 && (len % 4) == 0) + { + len >>= 2; + for (i=0; iIO_ADDR_R))) + return -EFAULT; + } + else + { + for (i=0; iIO_ADDR_R)) + return -EFAULT; + } + return 0; +} + +/** + * nand_write_buf16 - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 16bit buswith + */ +static void nand_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + len >>= 1; + + for (i=0; iIO_ADDR_W); + +} + +/** + * nand_read_buf16 - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 16bit buswith + */ +static void nand_read_buf16(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + len >>= 1; + + for (i=0; iIO_ADDR_R); +} + +/** + * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + * + * Default verify function for 16bit buswith + */ +static int nand_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + len >>= 1; + + for (i=0; iIO_ADDR_R)) + return -EFAULT; + + return 0; +} + +/** + * nand_block_bad - [DEFAULT] Read bad block marker from the chip + * @mtd: MTD device structure + * @ofs: offset from device start + * @getchip: 0, if the chip is already selected + * + * Check, if the block is bad. + */ +static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + int page, chipnr, res = 0; + struct nand_chip *this = mtd->priv; + u16 bad; + + if (getchip) { + page = (int)(ofs >> this->page_shift); + chipnr = (int)(ofs >> this->chip_shift); + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_READING); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + } else + page = (int) ofs; + + if (this->options & NAND_BUSWIDTH_16) { + this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos & 0xFE, page & this->pagemask); + bad = cpu_to_le16(this->read_word(mtd)); + if (this->badblockpos & 0x1) + bad >>= 1; + if ((bad & 0xFF) != 0xff) + res = 1; + } else { + this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos, page & this->pagemask); + if (this->read_byte(mtd) != 0xff) + res = 1; + } + + if (getchip) { + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + } + + return res; +} + +/** + * nand_default_block_markbad - [DEFAULT] mark a block bad + * @mtd: MTD device structure + * @ofs: offset from device start + * + * This is the default implementation, which can be overridden by + * a hardware specific driver. +*/ +static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) +{ + struct nand_chip *this = mtd->priv; + u_char buf[2] = {0, 0}; + size_t retlen; + int block; + + /* Get block number */ + block = ((int) ofs) >> this->bbt_erase_shift; + this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); + + /* Do we have a flash based bad block table ? */ + if (this->options & NAND_USE_FLASH_BBT) + return nand_update_bbt (mtd, ofs); + + /* We write two bytes, so we dont have to mess with 16 bit access */ + ofs += mtd->oobsize + (this->badblockpos & ~0x01); + ofs &= ~(mtd->erasesize-1); + return nand_write_oob (mtd, ofs , 2, &retlen, buf); +} + +/** + * nand_check_wp - [GENERIC] check if the chip is write protected + * @mtd: MTD device structure + * Check, if the device is write protected + * + * The function expects, that the device is already selected + */ +static int nand_check_wp (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + /* Check the WP bit */ + this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1); + return (this->read_byte(mtd) & 0x80) ? 0 : 1; +} + +/** + * nand_block_checkbad - [GENERIC] Check if a block is marked bad + * @mtd: MTD device structure + * @ofs: offset from device start + * @getchip: 0, if the chip is already selected + * @allowbbt: 1, if its allowed to access the bbt area + * + * Check, if the block is bad. Either by reading the bad block table or + * calling of the scan function. + */ +static int nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt) +{ + struct nand_chip *this = mtd->priv; + + if (!this->bbt) + return this->block_bad(mtd, ofs, getchip); + + /* Return info from the table */ + return nand_isbad_bbt (mtd, ofs, allowbbt); +} + +/** + * nand_command - [DEFAULT] Send command to NAND device + * @mtd: MTD device structure + * @command: the command to be sent + * @column: the column address for this command, -1 if none + * @page_addr: the page address for this command, -1 if none + * + * Send command to NAND device. This function is used for small page + * devices (256/512 Bytes per page) + */ +static void nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + register struct nand_chip *this = mtd->priv; + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* + * Write out the command to the device. + */ + if (command == NAND_CMD_SEQIN) { + int readcmd; + + if (column >= mtd->oobblock) { + /* OOB area */ + column -= mtd->oobblock; + readcmd = NAND_CMD_READOOB; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + readcmd = NAND_CMD_READ0; + } else { + column -= 256; + readcmd = NAND_CMD_READ1; + } + this->write_byte(mtd, readcmd); + } + this->write_byte(mtd, command); + + /* Set ALE and clear CLE to start address cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column); + } + if (page_addr != -1) { + this->write_byte(mtd, (unsigned char) (page_addr & 0xff)); + this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff)); + /* One more address cycle for devices > 32MiB */ + if (this->chipsize > (32 << 20)) + this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0x0f)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_SEQIN: + case NAND_CMD_STATUS: + return; + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_STATUS); + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + +/** + * nand_command_lp - [DEFAULT] Send command to NAND large page device + * @mtd: MTD device structure + * @command: the command to be sent + * @column: the column address for this command, -1 if none + * @page_addr: the page address for this command, -1 if none + * + * Send command to NAND device. This is the version for the new large page devices + * We dont have the seperate regions as we have in the small page devices. + * We must emulate NAND_CMD_READOOB to keep the code compatible. + * + */ +static void nand_command_lp (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + register struct nand_chip *this = mtd->priv; + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + column += mtd->oobblock; + command = NAND_CMD_READ0; + } + + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the command to the device. */ + this->write_byte(mtd, command); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column & 0xff); + this->write_byte(mtd, column >> 8); + } + if (page_addr != -1) { + this->write_byte(mtd, (unsigned char) (page_addr & 0xff)); + this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff)); + /* One more address cycle for devices > 128MiB */ + if (this->chipsize > (128 << 20)) + this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0xff)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + + case NAND_CMD_CACHEDPROG: + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_SEQIN: + case NAND_CMD_STATUS: + return; + + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_STATUS); + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + case NAND_CMD_READ0: + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the start read command */ + this->write_byte(mtd, NAND_CMD_READSTART); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + /* Fall through into ready check */ + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + +/** + * nand_get_device - [GENERIC] Get chip for selected access + * @this: the nand chip descriptor + * @mtd: MTD device structure + * @new_state: the state which is requested + * + * Get the device and lock it for exclusive access + */ +/* XXX U-BOOT XXX */ +#if 0 +static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state) +{ + struct nand_chip *active = this; + + DECLARE_WAITQUEUE (wait, current); + + /* + * Grab the lock and see if the device is available + */ +retry: + /* Hardware controller shared among independend devices */ + if (this->controller) { + spin_lock (&this->controller->lock); + if (this->controller->active) + active = this->controller->active; + else + this->controller->active = this; + spin_unlock (&this->controller->lock); + } + + if (active == this) { + spin_lock (&this->chip_lock); + if (this->state == FL_READY) { + this->state = new_state; + spin_unlock (&this->chip_lock); + return; + } + } + set_current_state (TASK_UNINTERRUPTIBLE); + add_wait_queue (&active->wq, &wait); + spin_unlock (&active->chip_lock); + schedule (); + remove_wait_queue (&active->wq, &wait); + goto retry; +} +#else +static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state) {} +#endif + +/** + * nand_wait - [DEFAULT] wait until the command is done + * @mtd: MTD device structure + * @this: NAND chip structure + * @state: state to select the max. timeout value + * + * Wait for command done. This applies to erase and program only + * Erase can take up to 400ms and program up to 20ms according to + * general NAND and SmartMedia specs + * +*/ +/* XXX U-BOOT XXX */ +#if 0 +static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long timeo = jiffies; + int status; + + if (state == FL_ERASING) + timeo += (HZ * 400) / 1000; + else + timeo += (HZ * 20) / 1000; + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + + if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) + this->cmdfunc (mtd, NAND_CMD_STATUS_MULTI, -1, -1); + else + this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1); + + while (time_before(jiffies, timeo)) { + /* Check, if we were interrupted */ + if (this->state != state) + return 0; + + if (this->dev_ready) { + if (this->dev_ready(mtd)) + break; + } else { + if (this->read_byte(mtd) & NAND_STATUS_READY) + break; + } + yield (); + } + status = (int) this->read_byte(mtd); + return status; + + return 0; +} +#else +static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long timeo; + + if (state == FL_ERASING) + timeo = (CFG_HZ * 400) / 1000; + else + timeo = (CFG_HZ * 20) / 1000; + + if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) + this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); + else + this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); + + reset_timer(); + + while (1) { + if (get_timer(0) > timeo) { + printf("Timeout!"); + return 0x01; + } + + if (this->dev_ready) { + if (this->dev_ready(mtd)) + break; + } else { + if (this->read_byte(mtd) & NAND_STATUS_READY) + break; + } + } +#ifdef PPCHAMELON_NAND_TIMER_HACK + reset_timer(); + while (get_timer(0) < 10); +#endif /* PPCHAMELON_NAND_TIMER_HACK */ + + return this->read_byte(mtd); +} +#endif + +/** + * nand_write_page - [GENERIC] write one page + * @mtd: MTD device structure + * @this: NAND chip structure + * @page: startpage inside the chip, must be called with (page & this->pagemask) + * @oob_buf: out of band data buffer + * @oobsel: out of band selecttion structre + * @cached: 1 = enable cached programming if supported by chip + * + * Nand_page_program function is used for write and writev ! + * This function will always program a full page of data + * If you call it with a non page aligned buffer, you're lost :) + * + * Cached programming is not supported yet. + */ +static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, + u_char *oob_buf, struct nand_oobinfo *oobsel, int cached) +{ + int i, status; + u_char ecc_code[NAND_MAX_OOBSIZE]; + int eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE; + uint *oob_config = oobsel->eccpos; + int datidx = 0, eccidx = 0, eccsteps = this->eccsteps; + int eccbytes = 0; + + /* FIXME: Enable cached programming */ + cached = 0; + + /* Send command to begin auto page programming */ + this->cmdfunc (mtd, NAND_CMD_SEQIN, 0x00, page); + + /* Write out complete page of data, take care of eccmode */ + switch (eccmode) { + /* No ecc, write all */ + case NAND_ECC_NONE: + printk (KERN_WARNING "Writing data without ECC to NAND-FLASH is not recommended\n"); + this->write_buf(mtd, this->data_poi, mtd->oobblock); + break; + /* Software ecc 3/256, write all */ + case NAND_ECC_SOFT: + for (; eccsteps; eccsteps--) { + this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code); + for (i = 0; i < this->eccbytes; i++, eccidx++) /*RS ECC */ + oob_buf[oob_config[eccidx]] = ecc_code[i]; + datidx += this->eccsize; + } + this->write_buf(mtd, this->data_poi, mtd->oobblock); + break; + default: + eccbytes = this->eccbytes; + for (; eccsteps; eccsteps--) { + /* enable hardware ecc logic for write */ + this->enable_hwecc(mtd, NAND_ECC_WRITE); + this->write_buf(mtd, &this->data_poi[datidx], this->eccsize); + this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code); + for (i = 0; i < eccbytes; i++, eccidx++) + oob_buf[oob_config[eccidx]] = ecc_code[i]; + /* If the hardware ecc provides syndromes then + * the ecc code must be written immidiately after + * the data bytes (words) */ + if (this->options & NAND_HWECC_SYNDROME) + this->write_buf(mtd, ecc_code, eccbytes); + datidx += this->eccsize; + } + break; + } + /* Write out OOB data */ + if (this->options & NAND_HWECC_SYNDROME) + this->write_buf(mtd, &oob_buf[oobsel->eccbytes], mtd->oobsize - oobsel->eccbytes); + else + this->write_buf(mtd, oob_buf, mtd->oobsize); + + /* Send command to actually program the data */ + this->cmdfunc (mtd, cached ? NAND_CMD_CACHEDPROG : NAND_CMD_PAGEPROG, -1, -1); + + if (!cached) { + /* call wait ready function */ + status = this->waitfunc (mtd, this, FL_WRITING); + /* See if device thinks it succeeded */ + if (status & 0x01) { + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page); + return -EIO; + } + } else { + /* FIXME: Implement cached programming ! */ + /* wait until cache is ready*/ + /* status = this->waitfunc (mtd, this, FL_CACHEDRPG); */ + } + return 0; +} + +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE +/** + * nand_verify_pages - [GENERIC] verify the chip contents after a write + * @mtd: MTD device structure + * @this: NAND chip structure + * @page: startpage inside the chip, must be called with (page & this->pagemask) + * @numpages: number of pages to verify + * @oob_buf: out of band data buffer + * @oobsel: out of band selecttion structre + * @chipnr: number of the current chip + * @oobmode: 1 = full buffer verify, 0 = ecc only + * + * The NAND device assumes that it is always writing to a cleanly erased page. + * Hence, it performs its internal write verification only on bits that + * transitioned from 1 to 0. The device does NOT verify the whole page on a + * byte by byte basis. It is possible that the page was not completely erased + * or the page is becoming unusable due to wear. The read with ECC would catch + * the error later when the ECC page check fails, but we would rather catch + * it early in the page write stage. Better to write no data than invalid data. + */ +static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int page, int numpages, + u_char *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode) +{ + int i, j, datidx = 0, oobofs = 0, res = -EIO; + int eccsteps = this->eccsteps; + int hweccbytes; + u_char oobdata[64]; + + hweccbytes = (this->options & NAND_HWECC_SYNDROME) ? (oobsel->eccbytes / eccsteps) : 0; + + /* Send command to read back the first page */ + this->cmdfunc (mtd, NAND_CMD_READ0, 0, page); + + for(;;) { + for (j = 0; j < eccsteps; j++) { + /* Loop through and verify the data */ + if (this->verify_buf(mtd, &this->data_poi[datidx], mtd->eccsize)) { + printf ("Failed write verify, nand offset 0x%08x. Suggest to erase block and repeat write operation!\n " + "If problem persists suggest marking block as bad (nand markbad ) and repeating the operation!\n", page * mtd->oobblock); + goto out; + } + datidx += mtd->eccsize; + /* Have we a hw generator layout ? */ + if (!hweccbytes) + continue; + if (this->verify_buf(mtd, &this->oob_buf[oobofs], hweccbytes)) { + printf ("Failed write verify, nand offset 0x%08x. Suggest to erase block and repeat write operation!\n " + "If problem persists suggest marking block as bad (nand markbad ) and repeating the operation!\n", page * mtd->oobblock); + goto out; + } + oobofs += hweccbytes; + } + + /* check, if we must compare all data or if we just have to + * compare the ecc bytes + */ + if (oobmode) { + if (this->verify_buf(mtd, &oob_buf[oobofs], mtd->oobsize - hweccbytes * eccsteps)) { + printf ("Failed write verify, nand offset 0x%08x. Suggest to erase block and repeat write operation!\n " + "If problem persists suggest marking block as bad (nand markbad ) and repeating the operation!\n", page * mtd->oobblock); + goto out; + } + } else { + /* Read always, else autoincrement fails */ + this->read_buf(mtd, oobdata, mtd->oobsize - hweccbytes * eccsteps); + + if (oobsel->useecc != MTD_NANDECC_OFF && !hweccbytes) { + int ecccnt = oobsel->eccbytes; + + for (i = 0; i < ecccnt; i++) { + int idx = oobsel->eccpos[i]; + if (oobdata[idx] != oob_buf[oobofs + idx] ) { + printf("%s: Failed ECC write \ + verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i); + goto out; + } + } + } + } + oobofs += mtd->oobsize - hweccbytes * eccsteps; + page++; + numpages--; + + /* Apply delay or wait for ready/busy pin + * Do this before the AUTOINCR check, so no problems + * arise if a chip which does auto increment + * is marked as NOAUTOINCR by the board driver. + * Do this also before returning, so the chip is + * ready for the next command. + */ + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + /* All done, return happy */ + if (!numpages) + return 0; + + + /* Check, if the chip supports auto page increment */ + if (!NAND_CANAUTOINCR(this)) + this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page); + } + /* + * Terminate the read command. We come here in case of an error + * So we must issue a reset command. + */ +out: + this->cmdfunc (mtd, NAND_CMD_RESET, -1, -1); + return res; +} +#endif + +/** + * nand_read - [MTD Interface] MTD compability function for nand_read_ecc + * @mtd: MTD device structure + * @from: offset to read from + * @len: number of bytes to read + * @retlen: pointer to variable to store the number of read bytes + * @buf: the databuffer to put data + * + * This function simply calls nand_read_ecc with oob buffer and oobsel = NULL +*/ +static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf) +{ + return nand_read_ecc (mtd, from, len, retlen, buf, NULL, NULL); +} + + +/** + * nand_read_ecc - [MTD Interface] Read data with ECC + * @mtd: MTD device structure + * @from: offset to read from + * @len: number of bytes to read + * @retlen: pointer to variable to store the number of read bytes + * @buf: the databuffer to put data + * @oob_buf: filesystem supplied oob data buffer + * @oobsel: oob selection structure + * + * NAND read with ECC + */ +static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, + size_t * retlen, u_char * buf, u_char * oob_buf, struct nand_oobinfo *oobsel) +{ + int i, j, col, realpage, page, end, ecc, chipnr, sndcmd = 1; + int read = 0, oob = 0, ecc_status = 0, ecc_failed = 0; + struct nand_chip *this = mtd->priv; + u_char *data_poi, *oob_data = oob_buf; + u_char ecc_calc[NAND_MAX_OOBSIZE]; + u_char ecc_code[NAND_MAX_OOBSIZE]; + int eccmode, eccsteps; + unsigned *oob_config; + int datidx; + int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; + int eccbytes; + int compareecc = 1; + int oobreadlen; + char *env; + DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + + /* Do not allow reads past end of device */ + if ((from + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n"); + *retlen = 0; + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd ,FL_READING); + /* Select ECC function according to nandEcc environemnt variable */ + env = getenv("nandEcc"); + if(nandenvECC == 0 && env != NULL) + { + if(strcmp(env,"1bit") == 0) + { + nandenv = 1; /* 1bit ecc */ + } + else + { + nandenv = 4; /* 4bit ecc */ + } + } + else if(nandenvECC == 1) + nandenv = 4; /* 4bit ecc */ + + if (mtd->oobblock < 2048 || (nandenv == 1)) + { + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + this->eccbytes = 3; + this->eccsize = 256; + this->eccsteps = mtd->oobblock / 256; + mtd->eccsize = this->eccsize; + switch (mtd->oobsize) + { + case 8: + this->autooob = &nand_oob_8; + break; + case 16: + this->autooob = &nand_oob_16; + break; + case 64: + this->autooob = &nand_oob_64; + break; + } + } + else if(mtd->oobblock >= 2048) + { + /* ECC RS, 512B DATA, 10B ECC */ + this->calculate_ecc = nand_calculate_ecc_rs; + this->correct_data = nand_correct_data_rs; + this->eccsteps = mtd->oobblock / 512; + this->eccbytes = 10; + this->eccsize = 512; + mtd->eccsize = this->eccsize; + switch (mtd->oobsize) + { + case 64: + this->autooob = &nand_oob_64_rs; + break; + case 128: + this->autooob = &nand_oob_128_rs; + break; + case 218: + this->autooob = &nand_oob_218_rs; + break; + } + } + + /* The number of bytes available for the filesystem to place fs dependend + * oob data */ + mtd->oobavail = 0; + for (i=0; this->autooob->oobfree[i][1]; i++) + mtd->oobavail += this->autooob->oobfree[i][1]; + + nandenv = 0; + + /* use userspace supplied oobinfo, if zero */ + if (oobsel == NULL) + oobsel = &mtd->oobinfo; + + /* Autoplace of oob data ? Use the default placement scheme */ + if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) + oobsel = this->autooob; + + eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE; + oob_config = oobsel->eccpos; + + /* Select the NAND device */ + chipnr = (int)(from >> this->chip_shift); + this->select_chip(mtd, chipnr); + + /* First we calculate the starting page */ + realpage = (int) (from >> this->page_shift); + page = realpage & this->pagemask; + + /* Get raw starting column */ + col = from & (mtd->oobblock - 1); + + end = mtd->oobblock; + ecc = this->eccsize; + eccbytes = this->eccbytes; + + if ((eccmode == NAND_ECC_NONE) || (this->options & NAND_HWECC_SYNDROME)) + compareecc = 0; + + oobreadlen = mtd->oobsize; + if (this->options & NAND_HWECC_SYNDROME) + oobreadlen -= oobsel->eccbytes; + + /* Loop until all data read */ + while (read < len) { + + int aligned = (!col && (len - read) >= end); + /* + * If the read is not page aligned, we have to read into data buffer + * due to ecc, else we read into return buffer direct + */ + if (aligned) + data_poi = &buf[read]; + else + data_poi = this->data_buf; + + /* Check, if we have this page in the buffer + * + * FIXME: Make it work when we must provide oob data too, + * check the usage of data_buf oob field + */ + if (realpage == this->pagebuf && !oob_buf) { + /* aligned read ? */ + if (aligned) + memcpy (data_poi, this->data_buf, end); + goto readdata; + } + + /* Check, if we must send the read command */ + if (sndcmd) { + this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page); + sndcmd = 0; + } + + /* get oob area, if we have no oob buffer from fs-driver */ + if (!oob_buf || oobsel->useecc == MTD_NANDECC_AUTOPLACE || + oobsel->useecc == MTD_NANDECC_AUTOPL_USR) + oob_data = &this->data_buf[end]; + + eccsteps = this->eccsteps; + switch (eccmode) { + case NAND_ECC_NONE: { /* No ECC, Read in a page */ +/* XXX U-BOOT XXX */ +#if 0 + static unsigned long lastwhinge = 0; + if ((lastwhinge / HZ) != (jiffies / HZ)) { + printk (KERN_WARNING "Reading data from NAND FLASH without ECC is not recommended\n"); + lastwhinge = jiffies; + } +#else + puts("Reading data from NAND FLASH without ECC is not recommended\n"); +#endif + this->read_buf(mtd, data_poi, end); + break; + } + case NAND_ECC_SOFT: /* Software ECC 3/256: Read in a page + oob data */ + this->read_buf(mtd, data_poi, end); + /*for (i = 0, datidx = 0; eccsteps; eccsteps--, i+=3, datidx += ecc) */ + for (i = 0, datidx = 0; eccsteps; eccsteps--, i+=eccbytes, datidx += ecc) /*RS ECC */ + this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]); + break; + default: + for (i = 0, datidx = 0; eccsteps; eccsteps--, i+=eccbytes, datidx += ecc) { + this->enable_hwecc(mtd, NAND_ECC_READ); + this->read_buf(mtd, &data_poi[datidx], ecc); + + /* HW ecc with syndrome calculation must read the + * syndrome from flash immidiately after the data */ + if (!compareecc) { + /* Some hw ecc generators need to know when the + * syndrome is read from flash */ + this->enable_hwecc(mtd, NAND_ECC_READSYN); + this->read_buf(mtd, &oob_data[i], eccbytes); + /* We calc error correction directly, it checks the hw + * generator for an error, reads back the syndrome and + * does the error correction on the fly */ + if (this->correct_data(mtd, &data_poi[datidx], &oob_data[i], &ecc_code[i]) == -1) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " + "Failed ECC read, page 0x%08x on chip %d\n", page, chipnr); + ecc_failed++; + } + } else { + this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]); + } + } + break; + } + + /* read oobdata */ + this->read_buf(mtd, &oob_data[mtd->oobsize - oobreadlen], oobreadlen); + + /* Skip ECC check, if not requested (ECC_NONE or HW_ECC with syndromes) */ + if (!compareecc) + goto readoob; + + /* Pick the ECC bytes out of the oob data */ + for (j = 0; j < oobsel->eccbytes; j++) + ecc_code[j] = oob_data[oob_config[j]]; + + /* correct data, if neccecary */ + for (i = 0, j = 0, datidx = 0; i < this->eccsteps; i++, datidx += ecc) { + ecc_status = this->correct_data(mtd, &data_poi[datidx], &ecc_code[j], &ecc_calc[j]); + /* Get next chunk of ecc bytes */ + j += eccbytes; + + /* Check, if we have a fs supplied oob-buffer, + * This is the legacy mode. Used by YAFFS1 + * Should go away some day + */ + if (oob_buf && oobsel->useecc == MTD_NANDECC_PLACE) { + int *p = (int *)(&oob_data[mtd->oobsize]); + p[i] = ecc_status; + } + + if (ecc_status == -1) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page); + ecc_failed++; + } + } + + readoob: + /* check, if we have a fs supplied oob-buffer */ + if (oob_buf) { + /* without autoplace. Legacy mode used by YAFFS1 */ + switch(oobsel->useecc) { + case MTD_NANDECC_AUTOPLACE: + case MTD_NANDECC_AUTOPL_USR: + /* Walk through the autoplace chunks */ + for (i = 0, j = 0; j < mtd->oobavail; i++) { + int from = oobsel->oobfree[i][0]; + int num = oobsel->oobfree[i][1]; + memcpy(&oob_buf[oob+j], &oob_data[from], num); + j+= num; + } + oob += mtd->oobavail; + break; + case MTD_NANDECC_PLACE: + /* YAFFS1 legacy mode */ + oob_data += this->eccsteps * sizeof (int); + default: + oob_data += mtd->oobsize; + } + } + readdata: + /* Partial page read, transfer data into fs buffer */ + if (!aligned) { + for (j = col; j < end && read < len; j++) + buf[read++] = data_poi[j]; + this->pagebuf = realpage; + } else + read += mtd->oobblock; + + /* Apply delay or wait for ready/busy pin + * Do this before the AUTOINCR check, so no problems + * arise if a chip which does auto increment + * is marked as NOAUTOINCR by the board driver. + */ + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + if (read == len) + break; + + /* For subsequent reads align to page boundary. */ + col = 0; + /* Increment page address */ + realpage++; + + page = realpage & this->pagemask; + /* Check, if we cross a chip boundary */ + if (!page) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + /* Check, if the chip supports auto page increment + * or if we have hit a block boundary. + */ + if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) + sndcmd = 1; + } + + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + /* + * Return success, if no ECC failures, else -EBADMSG + * fs driver will take care of that, because + * retlen == desired len and result == -EBADMSG + */ + *retlen = read; + return ecc_failed ? -EBADMSG : 0; +} + +/** + * nand_read_oob - [MTD Interface] NAND read out-of-band + * @mtd: MTD device structure + * @from: offset to read from + * @len: number of bytes to read + * @retlen: pointer to variable to store the number of read bytes + * @buf: the databuffer to put data + * + * NAND read out-of-band data from the spare area + */ +static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf) +{ + int i, col, page, chipnr; + struct nand_chip *this = mtd->priv; + int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; + + DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + + /* Shift to get page */ + page = (int)(from >> this->page_shift); + chipnr = (int)(from >> this->chip_shift); + + /* Mask to get column */ + col = from & (mtd->oobsize - 1); + + /* Initialize return length value */ + *retlen = 0; + + /* Do not allow reads past end of device */ + if ((from + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: Attempt read beyond end of device\n"); + *retlen = 0; + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd , FL_READING); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Send the read command */ + this->cmdfunc (mtd, NAND_CMD_READOOB, col, page & this->pagemask); + /* + * Read the data, if we read more than one page + * oob data, let the device transfer the data ! + */ + i = 0; + while (i < len) { + int thislen = mtd->oobsize - col; + thislen = min_t(int, thislen, len); + this->read_buf(mtd, &buf[i], thislen); + i += thislen; + + /* Apply delay or wait for ready/busy pin + * Do this before the AUTOINCR check, so no problems + * arise if a chip which does auto increment + * is marked as NOAUTOINCR by the board driver. + */ + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + /* Read more ? */ + if (i < len) { + page++; + col = 0; + + /* Check, if we cross a chip boundary */ + if (!(page & this->pagemask)) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + + /* Check, if the chip supports auto page increment + * or if we have hit a block boundary. + */ + if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) { + /* For subsequent page reads set offset to 0 */ + this->cmdfunc (mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask); + } + } + } + + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + /* Return happy */ + *retlen = len; + return 0; +} + +/** + * nand_read_raw - [GENERIC] Read raw data including oob into buffer + * @mtd: MTD device structure + * @buf: temporary buffer + * @from: offset to read from + * @len: number of bytes to read + * @ooblen: number of oob data bytes to read + * + * Read raw data including oob into buffer + */ +int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen) +{ + struct nand_chip *this = mtd->priv; + int page = (int) (from >> this->page_shift); + int chip = (int) (from >> this->chip_shift); + int sndcmd = 1; + int cnt = 0; + int pagesize = mtd->oobblock + mtd->oobsize; + int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; + + /* Do not allow reads past end of device */ + if ((from + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt read beyond end of device\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd , FL_READING); + + this->select_chip (mtd, chip); + + /* Add requested oob length */ + len += ooblen; + + while (len) { + if (sndcmd) + this->cmdfunc (mtd, NAND_CMD_READ0, 0, page & this->pagemask); + sndcmd = 0; + + this->read_buf (mtd, &buf[cnt], pagesize); + + len -= pagesize; + cnt += pagesize; + page++; + + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + /* Check, if the chip supports auto page increment */ + if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) + sndcmd = 1; + } + + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + return 0; +} + + +/** + * nand_prepare_oobbuf - [GENERIC] Prepare the out of band buffer + * @mtd: MTD device structure + * @fsbuf: buffer given by fs driver + * @oobsel: out of band selection structre + * @autoplace: 1 = place given buffer into the oob bytes + * @numpages: number of pages to prepare + * + * Return: + * 1. Filesystem buffer available and autoplacement is off, + * return filesystem buffer + * 2. No filesystem buffer or autoplace is off, return internal + * buffer + * 3. Filesystem buffer is given and autoplace selected + * put data from fs buffer into internal buffer and + * retrun internal buffer + * + * Note: The internal buffer is filled with 0xff. This must + * be done only once, when no autoplacement happens + * Autoplacement sets the buffer dirty flag, which + * forces the 0xff fill before using the buffer again. + * +*/ +static u_char * nand_prepare_oobbuf (struct mtd_info *mtd, u_char *fsbuf, struct nand_oobinfo *oobsel, + int autoplace, int numpages) +{ + struct nand_chip *this = mtd->priv; + int i, len, ofs; + + /* Zero copy fs supplied buffer */ + if (fsbuf && !autoplace) + return fsbuf; + + /* Check, if the buffer must be filled with ff again */ + if (this->oobdirty) { + memset (this->oob_buf, 0xff, + mtd->oobsize << (this->phys_erase_shift - this->page_shift)); + this->oobdirty = 0; + } + + /* If we have no autoplacement or no fs buffer use the internal one */ + if (!autoplace || !fsbuf) + return this->oob_buf; + + /* Walk through the pages and place the data */ + this->oobdirty = 1; + ofs = 0; + while (numpages--) { + for (i = 0, len = 0; len < mtd->oobavail; i++) { + int to = ofs + oobsel->oobfree[i][0]; + int num = oobsel->oobfree[i][1]; + memcpy (&this->oob_buf[to], fsbuf, num); + len += num; + fsbuf += num; + } + ofs += mtd->oobavail; + } + return this->oob_buf; +} + +#define NOTALIGNED(x) (x & (mtd->oobblock-1)) != 0 + +/** + * nand_write - [MTD Interface] compability function for nand_write_ecc + * @mtd: MTD device structure + * @to: offset to write to + * @len: number of bytes to write + * @retlen: pointer to variable to store the number of written bytes + * @buf: the data to write + * + * This function simply calls nand_write_ecc with oob buffer and oobsel = NULL + * +*/ +static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf) +{ + return (nand_write_ecc (mtd, to, len, retlen, buf, NULL, NULL)); +} + +/** + * nand_write_ecc - [MTD Interface] NAND write with ECC + * @mtd: MTD device structure + * @to: offset to write to + * @len: number of bytes to write + * @retlen: pointer to variable to store the number of written bytes + * @buf: the data to write + * @eccbuf: filesystem supplied oob data buffer + * @oobsel: oob selection structure + * + * NAND write with ECC + */ +static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, + size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel) +{ + int i,startpage, page, ret = -EIO, oob = 0, written = 0, chipnr; + int autoplace = 0, numpages, totalpages; + struct nand_chip *this = mtd->priv; + u_char *oobbuf, *bufstart; + int ppblock = (1 << (this->phys_erase_shift - this->page_shift)); + char *env; + + DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + + /* Initialize retlen, in case of early exit */ + *retlen = 0; + + /* Do not allow write past end of device */ + if ((to + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Attempt to write past end of page\n"); + return -EINVAL; + } + + /* reject writes, which are not page aligned */ + if (NOTALIGNED (to) || NOTALIGNED(len)) { + printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_WRITING); + + /* Calculate chipnr */ + chipnr = (int)(to >> this->chip_shift); + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) + goto out; + /* Select ECC function according to nandEcc environemnt variable */ + env = getenv("nandEcc"); + if(nandenvECC == 0 && env != NULL) + { + if(strcmp(env,"1bit") == 0) + { + nandenv = 1; /* 1bit ecc */ + } + else + { + nandenv = 4; /* 4bit ecc */ + } + } + else if(nandenvECC == 1) + nandenv = 4; /* 4bit ecc */ + + if (mtd->oobblock < 2048 || (nandenv == 1)) + { + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + this->eccsteps = mtd->oobblock / 256; + this->eccbytes = 3; + this->eccsize = 256; + mtd->eccsize = this->eccsize; + switch (mtd->oobsize) + { + case 8: + this->autooob = &nand_oob_8; + break; + case 16: + this->autooob = &nand_oob_16; + break; + case 64: + this->autooob = &nand_oob_64; + break; + } + } + else if(mtd->oobblock >= 2048) //"4bit" + { + this->calculate_ecc = nand_calculate_ecc_rs; + this->correct_data = nand_correct_data_rs; + this->eccbytes = 10; + this->eccsteps = mtd->oobblock / 512; + this->eccsize = 512; + mtd->eccsize = this->eccsize; + switch (mtd->oobsize) + { + case 64: + this->autooob = &nand_oob_64_rs; + break; + case 128: + this->autooob = &nand_oob_128_rs; + break; + case 218: + this->autooob = &nand_oob_218_rs; + break; + } + } + + /* The number of bytes available for the filesystem to place fs dependend + * oob data */ + mtd->oobavail = 0; + for (i=0; this->autooob->oobfree[i][1]; i++) + mtd->oobavail += this->autooob->oobfree[i][1]; + + nandenv = 0; + + /* if oobsel is NULL, use chip defaults */ + if (oobsel == NULL) + oobsel = &mtd->oobinfo; + + /* Autoplace of oob data ? Use the default placement scheme */ + if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) { + oobsel = this->autooob; + autoplace = 1; + } + if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR) + autoplace = 1; + + /* Setup variables and oob buffer */ + totalpages = len >> this->page_shift; + page = (int) (to >> this->page_shift); + /* Invalidate the page cache, if we write to the cached page */ + if (page <= this->pagebuf && this->pagebuf < (page + totalpages)) + this->pagebuf = -1; + + /* Set it relative to chip */ + page &= this->pagemask; + startpage = page; + /* Calc number of pages we can write in one go */ + numpages = min (ppblock - (startpage & (ppblock - 1)), totalpages); + oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel, autoplace, numpages); + bufstart = (u_char *)buf; + + /* Loop until all data is written */ + while (written < len) { + + this->data_poi = (u_char*) &buf[written]; + /* Write one page. If this is the last page to write + * or the last page in this block, then use the + * real pageprogram command, else select cached programming + * if supported by the chip. + */ + ret = nand_write_page (mtd, this, page, &oobbuf[oob], oobsel, (--numpages > 0)); + if (ret) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: write_page failed %d\n", ret); + goto out; + } + /* Next oob page */ + oob += mtd->oobsize; + /* Update written bytes count */ + written += mtd->oobblock; + if (written == len) + goto cmp; + + /* Increment page address */ + page++; + + /* Have we hit a block boundary ? Then we have to verify and + * if verify is ok, we have to setup the oob buffer for + * the next pages. + */ + if (!(page & (ppblock - 1))){ + int ofs; + this->data_poi = bufstart; + ret = nand_verify_pages (mtd, this, startpage, + page - startpage, + oobbuf, oobsel, chipnr, (eccbuf != NULL)); + if (ret) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret); + goto out; + } + *retlen = written; + bufstart = (u_char*) &buf[written]; + + ofs = autoplace ? mtd->oobavail : mtd->oobsize; + if (eccbuf) + eccbuf += (page - startpage) * ofs; + totalpages -= page - startpage; + numpages = min (totalpages, ppblock); + page &= this->pagemask; + startpage = page; + oob = 0; + this->oobdirty = 1; + oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel, + autoplace, numpages); + /* Check, if we cross a chip boundary */ + if (!page) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + } + } + /* Verify the remaining pages */ +cmp: + this->data_poi = bufstart; + ret = nand_verify_pages (mtd, this, startpage, totalpages, + oobbuf, oobsel, chipnr, (eccbuf != NULL)); + if (!ret) + *retlen = written; + else + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret); + +out: + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + return ret; +} + + +/** + * nand_write_oob - [MTD Interface] NAND write out-of-band + * @mtd: MTD device structure + * @to: offset to write to + * @len: number of bytes to write + * @retlen: pointer to variable to store the number of written bytes + * @buf: the data to write + * + * NAND write out-of-band + */ +static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf) +{ + int column, page, status, ret = -EIO, chipnr; + struct nand_chip *this = mtd->priv; + + DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + + /* Shift to get page */ + page = (int) (to >> this->page_shift); + chipnr = (int) (to >> this->chip_shift); + + /* Mask to get column */ + column = to & (mtd->oobsize - 1); + + /* Initialize return length value */ + *retlen = 0; + + /* Do not allow write past end of page */ + if ((column + len) > mtd->oobsize) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_WRITING); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Reset the chip. Some chips (like the Toshiba TC5832DC found + in one of my DiskOnChip 2000 test units) will clear the whole + data page too if we don't do this. I have no clue why, but + I seem to have 'fixed' it in the doc2000 driver in + August 1999. dwmw2. */ + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) + goto out; + + /* Invalidate the page cache, if we write to the cached page */ + if (page == this->pagebuf) + this->pagebuf = -1; + + if (NAND_MUST_PAD(this)) { + /* Write out desired data */ + this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page & this->pagemask); + /* prepad 0xff for partial programming */ + this->write_buf(mtd, ffchars, column); + /* write data */ + this->write_buf(mtd, buf, len); + /* postpad 0xff for partial programming */ + this->write_buf(mtd, ffchars, mtd->oobsize - (len+column)); + } else { + /* Write out desired data */ + this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock + column, page & this->pagemask); + /* write data */ + this->write_buf(mtd, buf, len); + } + /* Send command to program the OOB data */ + this->cmdfunc (mtd, NAND_CMD_PAGEPROG, -1, -1); + + status = this->waitfunc (mtd, this, FL_WRITING); + + /* See if device thinks it succeeded */ + if (status & 0x01) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page); + ret = -EIO; + goto out; + } + /* Return happy */ + *retlen = len; + +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* Send command to read back the data */ + this->cmdfunc (mtd, NAND_CMD_READOOB, column, page & this->pagemask); + + if (this->verify_buf(mtd, buf, len)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write verify, page 0x%08x\n", page); + ret = -EIO; + goto out; + } +#endif + ret = 0; +out: + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + return ret; +} + +/* XXX U-BOOT XXX */ +#if 0 +/** + * nand_writev - [MTD Interface] compabilty function for nand_writev_ecc + * @mtd: MTD device structure + * @vecs: the iovectors to write + * @count: number of vectors + * @to: offset to write to + * @retlen: pointer to variable to store the number of written bytes + * + * NAND write with kvec. This just calls the ecc function + */ +static int nand_writev (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, + loff_t to, size_t * retlen) +{ + return (nand_writev_ecc (mtd, vecs, count, to, retlen, NULL, NULL)); +} + +/** + * nand_writev_ecc - [MTD Interface] write with iovec with ecc + * @mtd: MTD device structure + * @vecs: the iovectors to write + * @count: number of vectors + * @to: offset to write to + * @retlen: pointer to variable to store the number of written bytes + * @eccbuf: filesystem supplied oob data buffer + * @oobsel: oob selection structure + * + * NAND write with iovec with ecc + */ +static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, + loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel) +{ + int i, page, len, total_len, ret = -EIO, written = 0, chipnr; + int oob, numpages, autoplace = 0, startpage; + struct nand_chip *this = mtd->priv; + int ppblock = (1 << (this->phys_erase_shift - this->page_shift)); + u_char *oobbuf, *bufstart; + + /* Preset written len for early exit */ + *retlen = 0; + + /* Calculate total length of data */ + total_len = 0; + for (i = 0; i < count; i++) + total_len += (int) vecs[i].iov_len; + + DEBUG (MTD_DEBUG_LEVEL3, + "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count); + + /* Do not allow write past end of page */ + if ((to + total_len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n"); + return -EINVAL; + } + + /* reject writes, which are not page aligned */ + if (NOTALIGNED (to) || NOTALIGNED(total_len)) { + printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_WRITING); + + /* Get the current chip-nr */ + chipnr = (int) (to >> this->chip_shift); + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) + goto out; + + /* if oobsel is NULL, use chip defaults */ + if (oobsel == NULL) + oobsel = &mtd->oobinfo; + + /* Autoplace of oob data ? Use the default placement scheme */ + if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) { + oobsel = this->autooob; + autoplace = 1; + } + if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR) + autoplace = 1; + + /* Setup start page */ + page = (int) (to >> this->page_shift); + /* Invalidate the page cache, if we write to the cached page */ + if (page <= this->pagebuf && this->pagebuf < ((to + total_len) >> this->page_shift)) + this->pagebuf = -1; + + startpage = page & this->pagemask; + + /* Loop until all kvec' data has been written */ + len = 0; + while (count) { + /* If the given tuple is >= pagesize then + * write it out from the iov + */ + if ((vecs->iov_len - len) >= mtd->oobblock) { + /* Calc number of pages we can write + * out of this iov in one go */ + numpages = (vecs->iov_len - len) >> this->page_shift; + /* Do not cross block boundaries */ + numpages = min (ppblock - (startpage & (ppblock - 1)), numpages); + oobbuf = nand_prepare_oobbuf (mtd, NULL, oobsel, autoplace, numpages); + bufstart = (u_char *)vecs->iov_base; + bufstart += len; + this->data_poi = bufstart; + oob = 0; + for (i = 1; i <= numpages; i++) { + /* Write one page. If this is the last page to write + * then use the real pageprogram command, else select + * cached programming if supported by the chip. + */ + ret = nand_write_page (mtd, this, page & this->pagemask, + &oobbuf[oob], oobsel, i != numpages); + if (ret) + goto out; + this->data_poi += mtd->oobblock; + len += mtd->oobblock; + oob += mtd->oobsize; + page++; + } + /* Check, if we have to switch to the next tuple */ + if (len >= (int) vecs->iov_len) { + vecs++; + len = 0; + count--; + } + } else { + /* We must use the internal buffer, read data out of each + * tuple until we have a full page to write + */ + int cnt = 0; + while (cnt < mtd->oobblock) { + if (vecs->iov_base != NULL && vecs->iov_len) + this->data_buf[cnt++] = ((u_char *) vecs->iov_base)[len++]; + /* Check, if we have to switch to the next tuple */ + if (len >= (int) vecs->iov_len) { + vecs++; + len = 0; + count--; + } + } + this->pagebuf = page; + this->data_poi = this->data_buf; + bufstart = this->data_poi; + numpages = 1; + oobbuf = nand_prepare_oobbuf (mtd, NULL, oobsel, autoplace, numpages); + ret = nand_write_page (mtd, this, page & this->pagemask, + oobbuf, oobsel, 0); + if (ret) + goto out; + page++; + } + + this->data_poi = bufstart; + ret = nand_verify_pages (mtd, this, startpage, numpages, oobbuf, oobsel, chipnr, 0); + if (ret) + goto out; + + written += mtd->oobblock * numpages; + /* All done ? */ + if (!count) + break; + + startpage = page & this->pagemask; + /* Check, if we cross a chip boundary */ + if (!startpage) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + } + ret = 0; +out: + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + *retlen = written; + return ret; +} +#endif + +/** + * single_erease_cmd - [GENERIC] NAND standard block erase command function + * @mtd: MTD device structure + * @page: the page address of the block which will be erased + * + * Standard erase command for NAND chips + */ +static void single_erase_cmd (struct mtd_info *mtd, int page) +{ + struct nand_chip *this = mtd->priv; + /* Send commands to erase a block */ + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page); + this->cmdfunc (mtd, NAND_CMD_ERASE2, -1, -1); +} + +/** + * multi_erease_cmd - [GENERIC] AND specific block erase command function + * @mtd: MTD device structure + * @page: the page address of the block which will be erased + * + * AND multi block erase command function + * Erase 4 consecutive blocks + */ +static void multi_erase_cmd (struct mtd_info *mtd, int page) +{ + struct nand_chip *this = mtd->priv; + /* Send commands to erase a block */ + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++); + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++); + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++); + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page); + this->cmdfunc (mtd, NAND_CMD_ERASE2, -1, -1); +} + +/** + * nand_erase - [MTD Interface] erase block(s) + * @mtd: MTD device structure + * @instr: erase instruction + * + * Erase one ore more blocks + */ +static int nand_erase (struct mtd_info *mtd, struct erase_info *instr) +{ + return nand_erase_nand (mtd, instr, 0); +} + +/** + * nand_erase_intern - [NAND Interface] erase block(s) + * @mtd: MTD device structure + * @instr: erase instruction + * @allowbbt: allow erasing the bbt area + * + * Erase one ore more blocks + */ +int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt) +{ + int page, len, status, pages_per_block, ret, chipnr; + struct nand_chip *this = mtd->priv; + + DEBUG (MTD_DEBUG_LEVEL3, + "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); + + /* Start address must align on block boundary */ + if (instr->addr & ((1 << this->phys_erase_shift) - 1)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); + return -EINVAL; + } + /* Length must align on block boundary */ + if (instr->len & ((1 << this->phys_erase_shift) - 1)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n"); + return -EINVAL; + } + /* Do not allow erase past end of device */ + if ((instr->len + instr->addr) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n"); + return -EINVAL; + } + + instr->fail_addr = 0xffffffff; + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_ERASING); + /* Shift to get first page */ + page = (int) (instr->addr >> this->page_shift); + chipnr = (int) (instr->addr >> this->chip_shift); + + /* Calculate pages in each block */ + pages_per_block = 1 << (this->phys_erase_shift - this->page_shift); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + /* Check the WP bit */ + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n"); + instr->state = MTD_ERASE_FAILED; + goto erase_exit; + } + + /* Loop through the pages */ + len = instr->len; + + instr->state = MTD_ERASING; + + while (len) { +#ifndef NAND_ALLOW_ERASE_ALL + /* Check if we have a bad block, we do not erase bad blocks ! */ + if (nand_block_checkbad(mtd, ((loff_t) page) << this->page_shift, 0, allowbbt)) { + printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page); + instr->state = MTD_ERASE_FAILED; + goto erase_exit; + } +#endif + /* Invalidate the page cache, if we erase the block which contains + the current cached page */ + if (page <= this->pagebuf && this->pagebuf < (page + pages_per_block)) + this->pagebuf = -1; + this->erase_cmd (mtd, page & this->pagemask); + status = this->waitfunc (mtd, this, FL_ERASING); + /* See if block erase succeeded */ + if (status & 0x01) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page); + instr->state = MTD_ERASE_FAILED; + instr->fail_addr = (page << this->page_shift); + goto erase_exit; + } + /* Increment page address and decrement length */ + len -= (1 << this->phys_erase_shift); + page += pages_per_block; + + /* Check, if we cross a chip boundary */ + if (len && !(page & this->pagemask)) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + } + instr->state = MTD_ERASE_DONE; + +erase_exit: + + ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; + /* Do call back function */ + if (!ret) + mtd_erase_callback(instr); + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + /* Return more or less happy */ + return ret; +} + +/** + * nand_sync - [MTD Interface] sync + * @mtd: MTD device structure + * + * Sync is actually a wait for chip ready function + */ +static void nand_sync (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n"); + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_SYNCING); + /* Release it and go back */ + nand_release_device (mtd); +} + + +/** + * nand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad + * @mtd: MTD device structure + * @ofs: offset relative to mtd start + */ +static int nand_block_isbad (struct mtd_info *mtd, loff_t ofs) +{ + /* Check for invalid offset */ + if (ofs > mtd->size) + return -EINVAL; + + return nand_block_checkbad (mtd, ofs, 1, 0); +} + +/** + * nand_block_markbad - [MTD Interface] Mark the block at the given offset as bad + * @mtd: MTD device structure + * @ofs: offset relative to mtd start + */ +static int nand_block_markbad (struct mtd_info *mtd, loff_t ofs) +{ + struct nand_chip *this = mtd->priv; + int ret; + + if ((ret = nand_block_isbad(mtd, ofs))) { + /* If it was bad already, return success and do nothing. */ + if (ret > 0) + return 0; + return ret; + } + + return this->block_markbad(mtd, ofs); +} + +/** + * nand_scan - [NAND Interface] Scan for the NAND device + * @mtd: MTD device structure + * @maxchips: Number of chips to scan for + * + * This fills out all the not initialized function pointers + * with the defaults. + * The flash ID is read and the mtd/chip structures are + * filled with the appropriate values. Buffers are allocated if + * they are not provided by the board driver + * + */ +int nand_scan (struct mtd_info *mtd, int maxchips) +{ + int i, j, nand_maf_id, nand_dev_id, busw; + struct nand_chip *this = mtd->priv; + char *env; + + /* Get buswidth to select the correct functions */ + busw = this->options & NAND_BUSWIDTH_16; + + /* check for proper chip_delay setup, set 20us if not */ + if (!this->chip_delay) + this->chip_delay = 30; + + /* check, if a user supplied command function given */ + if (this->cmdfunc == NULL) + this->cmdfunc = nand_command; + + /* check, if a user supplied wait function given */ + if (this->waitfunc == NULL) + this->waitfunc = nand_wait; + + if (!this->select_chip) + this->select_chip = nand_select_chip; + if (!this->write_byte) + this->write_byte = busw ? nand_write_byte16 : nand_write_byte; + if (!this->read_byte) + this->read_byte = busw ? nand_read_byte16 : nand_read_byte; + if (!this->write_word) + this->write_word = nand_write_word; + if (!this->read_word) + this->read_word = nand_read_word; + if (!this->block_bad) + this->block_bad = nand_block_bad; + if (!this->block_markbad) + this->block_markbad = nand_default_block_markbad; + if (!this->write_buf) + this->write_buf = busw ? nand_write_buf16 : nand_write_buf; + if (!this->read_buf) + this->read_buf = busw ? nand_read_buf16 : nand_read_buf; + if (!this->verify_buf) + this->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; + if (!this->scan_bbt) + this->scan_bbt = nand_default_bbt; + + /* Select the device */ + this->select_chip(mtd, 0); + + /* Send the command for reading device ID */ + this->cmdfunc (mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + nand_maf_id = this->read_byte(mtd); + nand_dev_id = this->read_byte(mtd); + /* Print and store flash device information */ + for (i = 0; nand_flash_ids[i].name != NULL; i++) { + + if (nand_dev_id != nand_flash_ids[i].id) + continue; + + if (!mtd->name) mtd->name = nand_flash_ids[i].name; + this->chipsize = nand_flash_ids[i].chipsize << 20; + + /* New devices have all the information in additional id bytes */ + if (!nand_flash_ids[i].pagesize) { + int extid; + /* The 3rd id byte contains non relevant data ATM */ + extid = this->read_byte(mtd); + /* The 4th id byte is the important one */ + extid = this->read_byte(mtd); + /* Calc pagesize */ + mtd->oobblock = 1024 << (extid & 0x3); + extid >>= 2; + /* Calc oobsize */ + mtd->oobsize = (8 << (extid & 0x01)) * (mtd->oobblock / 512); + extid >>= 2; + /* Calc blocksize. Blocksize is multiples of 64KiB */ + mtd->erasesize = (64 * 1024) << (extid & 0x03); + extid >>= 2; + /* Get buswidth information */ + busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + + } else { + /* Old devices have this data hardcoded in the + * device id table */ + mtd->erasesize = nand_flash_ids[i].erasesize; + mtd->oobblock = nand_flash_ids[i].pagesize; + mtd->oobsize = mtd->oobblock / 32; + busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16; + } + + /* Check, if buswidth is correct. Hardware drivers should set + * this correct ! */ + if (busw != (this->options & NAND_BUSWIDTH_16)) { + printk (KERN_INFO "NAND device: Manufacturer ID:" + " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id, + nand_manuf_ids[i].name , mtd->name); + printk (KERN_WARNING + "NAND bus width %d instead %d bit\n", + (this->options & NAND_BUSWIDTH_16) ? 16 : 8, + busw ? 16 : 8); + this->select_chip(mtd, -1); + return 1; + } + + /* Calculate the address shift from the page size */ + this->page_shift = ffs(mtd->oobblock) - 1; + this->bbt_erase_shift = this->phys_erase_shift = ffs(mtd->erasesize) - 1; + this->chip_shift = ffs(this->chipsize) - 1; + + /* Set the bad block position */ + this->badblockpos = mtd->oobblock > 512 ? + NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; + + /* Get chip options, preserve non chip based options */ + this->options &= ~NAND_CHIPOPTIONS_MSK; + this->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK; + /* Set this as a default. Board drivers can override it, if neccecary */ + this->options |= NAND_NO_AUTOINCR; + /* Check if this is a not a samsung device. Do not clear the options + * for chips which are not having an extended id. + */ + if (nand_maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize) + this->options &= ~NAND_SAMSUNG_LP_OPTIONS; + + /* Check for AND chips with 4 page planes */ + if (this->options & NAND_4PAGE_ARRAY) + this->erase_cmd = multi_erase_cmd; + else + this->erase_cmd = single_erase_cmd; + + /* Do not replace user supplied command function ! */ + if (mtd->oobblock > 512 && this->cmdfunc == nand_command) + this->cmdfunc = nand_command_lp; + + /* Try to identify manufacturer */ + for (j = 0; nand_manuf_ids[j].id != 0x0; j++) { + if (nand_manuf_ids[j].id == nand_maf_id) + break; + } + break; + } + + if (!nand_flash_ids[i].name) { +#ifndef CFG_NAND_QUIET_TEST + printk (KERN_WARNING "No NAND device found!!!\n"); +#endif + this->select_chip(mtd, -1); + return 1; + } + + for (i=1; i < maxchips; i++) { + this->select_chip(mtd, i); + + /* Send the command for reading device ID */ + this->cmdfunc (mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + if (nand_maf_id != this->read_byte(mtd) || + nand_dev_id != this->read_byte(mtd)) + break; + } + if (i > 1) + printk(KERN_INFO "%d NAND chips detected\n", i); + + /* Allocate buffers, if neccecary */ + if (!this->oob_buf) { + size_t len; + len = mtd->oobsize << (this->phys_erase_shift - this->page_shift); + this->oob_buf = kmalloc (len, GFP_KERNEL); + if (!this->oob_buf) { + printk (KERN_ERR "nand_scan(): Cannot allocate oob_buf\n"); + return -ENOMEM; + } + this->options |= NAND_OOBBUF_ALLOC; + } + + if (!this->data_buf) { + size_t len; + len = mtd->oobblock + mtd->oobsize; + this->data_buf = kmalloc (len, GFP_KERNEL); + if (!this->data_buf) { + if (this->options & NAND_OOBBUF_ALLOC) + kfree (this->oob_buf); + printk (KERN_ERR "nand_scan(): Cannot allocate data_buf\n"); + return -ENOMEM; + } + this->options |= NAND_DATABUF_ALLOC; + } + + /* Store the number of chips and calc total size for mtd */ + this->numchips = i; + mtd->size = i * this->chipsize; + /* Convert chipsize to number of pages per chip -1. */ + this->pagemask = (this->chipsize >> this->page_shift) - 1; + /* Preset the internal oob buffer */ + memset(this->oob_buf, 0xff, mtd->oobsize << (this->phys_erase_shift - this->page_shift)); + + env = getenv("nandEcc"); + if(env) + { + if(strcmp(env,"1bit") == 0) + { + nandenv = 1; /* 1bit ecc */ + } + else + { + nandenv = 4; /* 4bit ecc */ + } + } + else + { + if(mtd->oobsize < 64) + { + nandenv = 1; /* 1bit ecc */ + } + else + { + nandenv = 4; /* 4bit ecc */ + } + } + + /* If no default placement scheme is given, select an + * appropriate one */ + if (!this->autooob) { + /* Select the appropriate default oob placement scheme for + * placement agnostic filesystems */ + switch (mtd->oobsize) { + case 8: + this->autooob = &nand_oob_8; + break; + case 16: + this->autooob = &nand_oob_16; + break; + case 64: + if(nandenv == 4) + /* RS ECC */ + this->autooob = &nand_oob_64_rs; + else + this->autooob = &nand_oob_64; + break; + case 128: + if(nandenv == 4) + /* RS ECC */ + this->autooob = &nand_oob_128_rs; + else + this->autooob = &nand_oob_128; + break; + case 218: + if(nandenv == 4) + /* RS ECC */ + this->autooob = &nand_oob_218_rs; + else + this->autooob = &nand_oob_218; + break; + default: + printk (KERN_WARNING "No oob scheme defined for oobsize %d\n", + mtd->oobsize); +/* BUG(); */ + } + } + + /* The number of bytes available for the filesystem to place fs dependend + * oob data */ + mtd->oobavail = 0; + for (i=0; this->autooob->oobfree[i][1]; i++) + mtd->oobavail += this->autooob->oobfree[i][1]; + + /* + * check ECC mode, default to software + * if 3byte/512byte hardware ECC is selected and we have 256 byte pagesize + * fallback to software ECC + */ + this->eccsize = 256; /* set default eccsize */ + this->eccbytes = 3; + + switch (this->eccmode) { + case NAND_ECC_HW12_2048: + if (mtd->oobblock < 2048) { + printk(KERN_WARNING "2048 byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", + mtd->oobblock); + this->eccmode = NAND_ECC_SOFT; + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + } else + this->eccsize = 2048; + break; + + case NAND_ECC_HW3_512: + case NAND_ECC_HW6_512: + case NAND_ECC_HW8_512: + if (mtd->oobblock == 256) { + printk (KERN_WARNING "512 byte HW ECC not possible on 256 Byte pagesize, fallback to SW ECC \n"); + this->eccmode = NAND_ECC_SOFT; + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + } else + this->eccsize = 512; /* set eccsize to 512 */ + break; + + case NAND_ECC_HW3_256: + break; + + case NAND_ECC_NONE: + printk (KERN_WARNING "NAND_ECC_NONE selected by board driver. This is not recommended !!\n"); + this->eccmode = NAND_ECC_NONE; + break; + + case NAND_ECC_SOFT: + /* RS ECC */ + if (mtd->oobblock < 2048) + { + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + } + else //mtd->oobblock >=2048 + { + if(nandenv == 4) + { + this->calculate_ecc = nand_calculate_ecc_rs; + this->correct_data = nand_correct_data_rs; + this->eccbytes = 10; + this->eccsize = 512; + } + else + { + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + /*this->eccbytes = nand_oob_64.eccbytes;*/ + } + } + break; + default: + printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode); +/* BUG(); */ + } + + /* Check hardware ecc function availability and adjust number of ecc bytes per + * calculation step + */ + switch (this->eccmode) { + case NAND_ECC_HW12_2048: + this->eccbytes += 4; + case NAND_ECC_HW8_512: + this->eccbytes += 2; + case NAND_ECC_HW6_512: + this->eccbytes += 3; + case NAND_ECC_HW3_512: + case NAND_ECC_HW3_256: + if (this->calculate_ecc && this->correct_data && this->enable_hwecc) + break; + printk (KERN_WARNING "No ECC functions supplied, Hardware ECC not possible\n"); +/* BUG(); */ + } + + mtd->eccsize = this->eccsize; + + /* Set the number of read / write steps for one page to ensure ECC generation */ + switch (this->eccmode) { + case NAND_ECC_HW12_2048: + this->eccsteps = mtd->oobblock / 2048; + break; + case NAND_ECC_HW3_512: + case NAND_ECC_HW6_512: + case NAND_ECC_HW8_512: + this->eccsteps = mtd->oobblock / 512; + break; + case NAND_ECC_HW3_256: + case NAND_ECC_SOFT: + /* RS ECC */ + if (mtd->oobblock < 2048) + this->eccsteps = mtd->oobblock / 256; + else + { + if(nandenv == 4) + this->eccsteps = mtd->oobblock / 512; + else + this->eccsteps = mtd->oobblock / 256; + } + break; + + case NAND_ECC_NONE: + this->eccsteps = 1; + break; + } + nandenv = 0; +/* XXX U-BOOT XXX */ +#if 0 + /* Initialize state, waitqueue and spinlock */ + this->state = FL_READY; + init_waitqueue_head (&this->wq); + spin_lock_init (&this->chip_lock); +#endif + + /* De-select the device */ + this->select_chip(mtd, -1); + + /* Invalidate the pagebuffer reference */ + this->pagebuf = -1; + + /* Fill in remaining MTD driver data */ + mtd->type = MTD_NANDFLASH; + mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC; + mtd->ecctype = MTD_ECC_SW; + mtd->erase = nand_erase; + mtd->point = NULL; + mtd->unpoint = NULL; + mtd->read = nand_read; + mtd->write = nand_write; + mtd->read_ecc = nand_read_ecc; + mtd->write_ecc = nand_write_ecc; + mtd->read_oob = nand_read_oob; + mtd->write_oob = nand_write_oob; +/* XXX U-BOOT XXX */ +#if 0 + mtd->readv = NULL; + mtd->writev = nand_writev; + mtd->writev_ecc = nand_writev_ecc; +#endif + mtd->sync = nand_sync; +/* XXX U-BOOT XXX */ +#if 0 + mtd->lock = NULL; + mtd->unlock = NULL; + mtd->suspend = NULL; + mtd->resume = NULL; +#endif + mtd->block_isbad = nand_block_isbad; + mtd->block_markbad = nand_block_markbad; + + /* and make the autooob the default one */ + memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo)); +/* XXX U-BOOT XXX */ +#if 0 + mtd->owner = THIS_MODULE; +#endif + /* Build bad block table */ + return this->scan_bbt (mtd); +} + +/** + * nand_release - [NAND Interface] Free resources held by the NAND device + * @mtd: MTD device structure + */ +void nand_release (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + +#ifdef CONFIG_MTD_PARTITIONS + /* Deregister partitions */ + del_mtd_partitions (mtd); +#endif + /* Deregister the device */ +/* XXX U-BOOT XXX */ +#if 0 + del_mtd_device (mtd); +#endif + /* Free bad block table memory, if allocated */ + if (this->bbt) + kfree (this->bbt); + /* Buffer allocated by nand_scan ? */ + if (this->options & NAND_OOBBUF_ALLOC) + kfree (this->oob_buf); + /* Buffer allocated by nand_scan ? */ + if (this->options & NAND_DATABUF_ALLOC) + kfree (this->data_buf); +} + +#endif diff --git a/drivers/nand/nand_bbt.c b/drivers/nand/nand_bbt.c new file mode 100644 index 0000000..aaa9400 --- /dev/null +++ b/drivers/nand/nand_bbt.c @@ -0,0 +1,1052 @@ +/* + * drivers/mtd/nand_bbt.c + * + * Overview: + * Bad block table support for the NAND driver + * + * Copyright (C) 2004 Thomas Gleixner (tglx@linutronix.de) + * + * $Id: nand_bbt.c,v 1.28 2004/11/13 10:19:09 gleixner Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Description: + * + * When nand_scan_bbt is called, then it tries to find the bad block table + * depending on the options in the bbt descriptor(s). If a bbt is found + * then the contents are read and the memory based bbt is created. If a + * mirrored bbt is selected then the mirror is searched too and the + * versions are compared. If the mirror has a greater version number + * than the mirror bbt is used to build the memory based bbt. + * If the tables are not versioned, then we "or" the bad block information. + * If one of the bbt's is out of date or does not exist it is (re)created. + * If no bbt exists at all then the device is scanned for factory marked + * good / bad blocks and the bad block tables are created. + * + * For manufacturer created bbts like the one found on M-SYS DOC devices + * the bbt is searched and read but never created + * + * The autogenerated bad block table is located in the last good blocks + * of the device. The table is mirrored, so it can be updated eventually. + * The table is marked in the oob area with an ident pattern and a version + * number which indicates which of both tables is more up to date. + * + * The table uses 2 bits per block + * 11b: block is good + * 00b: block is factory marked bad + * 01b, 10b: block is marked bad due to wear + * + * The memory bad block table uses the following scheme: + * 00b: block is good + * 01b: block is marked bad due to wear + * 10b: block is reserved (to protect the bbt area) + * 11b: block is factory marked bad + * + * Multichip devices like DOC store the bad block info per floor. + * + * Following assumptions are made: + * - bbts start at a page boundary, if autolocated on a block boundary + * - the space neccecary for a bbt in FLASH does not exceed a block boundary + * + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include +#include +#include +#include + +#include + +/** + * check_pattern - [GENERIC] check if a pattern is in the buffer + * @buf: the buffer to search + * @len: the length of buffer to search + * @paglen: the pagelength + * @td: search pattern descriptor + * + * Check for a pattern at the given place. Used to search bad block + * tables and good / bad block identifiers. + * If the SCAN_EMPTY option is set then check, if all bytes except the + * pattern area contain 0xff + * +*/ +static int check_pattern (uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td) +{ + int i, end; + uint8_t *p = buf; + + end = paglen + td->offs; + if (td->options & NAND_BBT_SCANEMPTY) { + for (i = 0; i < end; i++) { + if (p[i] != 0xff) + return -1; + } + } + p += end; + + /* Compare the pattern */ + for (i = 0; i < td->len; i++) { + if (p[i] != td->pattern[i]) + return -1; + } + + p += td->len; + end += td->len; + if (td->options & NAND_BBT_SCANEMPTY) { + for (i = end; i < len; i++) { + if (*p++ != 0xff) + return -1; + } + } + return 0; +} + +/** + * read_bbt - [GENERIC] Read the bad block table starting from page + * @mtd: MTD device structure + * @buf: temporary buffer + * @page: the starting page + * @num: the number of bbt descriptors to read + * @bits: number of bits per block + * @offs: offset in the memory table + * @reserved_block_code: Pattern to identify reserved blocks + * + * Read the bad block table starting from page. + * + */ +static int read_bbt (struct mtd_info *mtd, uint8_t *buf, int page, int num, + int bits, int offs, int reserved_block_code) +{ + int res, i, j, act = 0; + struct nand_chip *this = mtd->priv; + size_t retlen, len, totlen; + loff_t from; + uint8_t msk = (uint8_t) ((1 << bits) - 1); + + totlen = (num * bits) >> 3; + from = ((loff_t)page) << this->page_shift; + + while (totlen) { + len = min (totlen, (size_t) (1 << this->bbt_erase_shift)); + res = mtd->read_ecc (mtd, from, len, &retlen, buf, NULL, this->autooob); + if (res < 0) { + if (retlen != len) { + printk (KERN_INFO "nand_bbt: Error reading bad block table\n"); + return res; + } + printk (KERN_WARNING "nand_bbt: ECC error while reading bad block table\n"); + } + + /* Analyse data */ + for (i = 0; i < len; i++) { + uint8_t dat = buf[i]; + for (j = 0; j < 8; j += bits, act += 2) { + uint8_t tmp = (dat >> j) & msk; + if (tmp == msk) + continue; + if (reserved_block_code && + (tmp == reserved_block_code)) { + printk (KERN_DEBUG "nand_read_bbt: Reserved block at 0x%08x\n", + ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06); + continue; + } + /* Leave it for now, if its matured we can move this + * message to MTD_DEBUG_LEVEL0 */ + printk (KERN_DEBUG "nand_read_bbt: Bad block at 0x%08x\n", + ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + /* Factory marked bad or worn out ? */ + if (tmp == 0) + this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06); + else + this->bbt[offs + (act >> 3)] |= 0x1 << (act & 0x06); + } + } + totlen -= len; + from += len; + } + return 0; +} + +/** + * read_abs_bbt - [GENERIC] Read the bad block table starting at a given page + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @chip: read the table for a specific chip, -1 read all chips. + * Applies only if NAND_BBT_PERCHIP option is set + * + * Read the bad block table for all chips starting at a given page + * We assume that the bbt bits are in consecutive order. +*/ +static int read_abs_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip) +{ + struct nand_chip *this = mtd->priv; + int res = 0, i; + int bits; + + bits = td->options & NAND_BBT_NRBITS_MSK; + if (td->options & NAND_BBT_PERCHIP) { + int offs = 0; + for (i = 0; i < this->numchips; i++) { + if (chip == -1 || chip == i) + res = read_bbt (mtd, buf, td->pages[i], this->chipsize >> this->bbt_erase_shift, bits, offs, td->reserved_block_code); + if (res) + return res; + offs += this->chipsize >> (this->bbt_erase_shift + 2); + } + } else { + res = read_bbt (mtd, buf, td->pages[0], mtd->size >> this->bbt_erase_shift, bits, 0, td->reserved_block_code); + if (res) + return res; + } + return 0; +} + +/** + * read_abs_bbts - [GENERIC] Read the bad block table(s) for all chips starting at a given page + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @md: descriptor for the bad block table mirror + * + * Read the bad block table(s) for all chips starting at a given page + * We assume that the bbt bits are in consecutive order. + * +*/ +static int read_abs_bbts (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, + struct nand_bbt_descr *md) +{ + struct nand_chip *this = mtd->priv; + + /* Read the primary version, if available */ + if (td->options & NAND_BBT_VERSION) { + nand_read_raw (mtd, buf, td->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize); + td->version[0] = buf[mtd->oobblock + td->veroffs]; + printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", td->pages[0], td->version[0]); + } + + /* Read the mirror version, if available */ + if (md && (md->options & NAND_BBT_VERSION)) { + nand_read_raw (mtd, buf, md->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize); + md->version[0] = buf[mtd->oobblock + md->veroffs]; + printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", md->pages[0], md->version[0]); + } + + return 1; +} + +/** + * create_bbt - [GENERIC] Create a bad block table by scanning the device + * @mtd: MTD device structure + * @buf: temporary buffer + * @bd: descriptor for the good/bad block search pattern + * @chip: create the table for a specific chip, -1 read all chips. + * Applies only if NAND_BBT_PERCHIP option is set + * + * Create a bad block table by scanning the device + * for the given good/bad block identify pattern + */ +static void create_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd, int chip) +{ + struct nand_chip *this = mtd->priv; + int i, j, numblocks, len, scanlen; + int startblock; + loff_t from; + size_t readlen, ooblen; + + if (bd->options & NAND_BBT_SCANALLPAGES) + len = 1 << (this->bbt_erase_shift - this->page_shift); + else { + if (bd->options & NAND_BBT_SCAN2NDPAGE) + len = 2; + else + len = 1; + } + scanlen = mtd->oobblock + mtd->oobsize; + readlen = len * mtd->oobblock; + ooblen = len * mtd->oobsize; + + if (chip == -1) { + /* Note that numblocks is 2 * (real numblocks) here, see i+=2 below as it + * makes shifting and masking less painful */ + numblocks = mtd->size >> (this->bbt_erase_shift - 1); + startblock = 0; + from = 0; + } else { + if (chip >= this->numchips) { + printk (KERN_WARNING "create_bbt(): chipnr (%d) > available chips (%d)\n", + chip + 1, this->numchips); + return; + } + numblocks = this->chipsize >> (this->bbt_erase_shift - 1); + startblock = chip * numblocks; + numblocks += startblock; + from = startblock << (this->bbt_erase_shift - 1); + } + + for (i = startblock; i < numblocks;) { + nand_read_raw (mtd, buf, from, readlen, ooblen); + for (j = 0; j < len; j++) { + if (check_pattern (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) { + this->bbt[i >> 3] |= 0x03 << (i & 0x6); + break; + } + } + i += 2; + from += (1 << this->bbt_erase_shift); + } +} + +/** + * search_bbt - [GENERIC] scan the device for a specific bad block table + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * + * Read the bad block table by searching for a given ident pattern. + * Search is preformed either from the beginning up or from the end of + * the device downwards. The search starts always at the start of a + * block. + * If the option NAND_BBT_PERCHIP is given, each chip is searched + * for a bbt, which contains the bad block information of this chip. + * This is neccecary to provide support for certain DOC devices. + * + * The bbt ident pattern resides in the oob area of the first page + * in a block. + */ +static int search_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td) +{ + struct nand_chip *this = mtd->priv; + int i, chips; + int bits, startblock, block, dir; + int scanlen = mtd->oobblock + mtd->oobsize; + int bbtblocks; + + /* Search direction top -> down ? */ + if (td->options & NAND_BBT_LASTBLOCK) { + startblock = (mtd->size >> this->bbt_erase_shift) -1; + dir = -1; + } else { + startblock = 0; + dir = 1; + } + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) { + chips = this->numchips; + bbtblocks = this->chipsize >> this->bbt_erase_shift; + startblock &= bbtblocks - 1; + } else { + chips = 1; + bbtblocks = mtd->size >> this->bbt_erase_shift; + } + + /* Number of bits for each erase block in the bbt */ + bits = td->options & NAND_BBT_NRBITS_MSK; + + for (i = 0; i < chips; i++) { + /* Reset version information */ + td->version[i] = 0; + td->pages[i] = -1; + /* Scan the maximum number of blocks */ + for (block = 0; block < td->maxblocks; block++) { + int actblock = startblock + dir * block; + /* Read first page */ + nand_read_raw (mtd, buf, actblock << this->bbt_erase_shift, mtd->oobblock, mtd->oobsize); + if (!check_pattern(buf, scanlen, mtd->oobblock, td)) { + td->pages[i] = actblock << (this->bbt_erase_shift - this->page_shift); + if (td->options & NAND_BBT_VERSION) { + td->version[i] = buf[mtd->oobblock + td->veroffs]; + } + break; + } + } + startblock += this->chipsize >> this->bbt_erase_shift; + } + /* Check, if we found a bbt for each requested chip */ + for (i = 0; i < chips; i++) { + if (td->pages[i] == -1) + printk (KERN_WARNING "Bad block table not found for chip %d\n", i); + else + printk (KERN_DEBUG "Bad block table found at page %d, version 0x%02X\n", td->pages[i], td->version[i]); + } + return 0; +} + +/** + * search_read_bbts - [GENERIC] scan the device for bad block table(s) + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @md: descriptor for the bad block table mirror + * + * Search and read the bad block table(s) +*/ +static int search_read_bbts (struct mtd_info *mtd, uint8_t *buf, + struct nand_bbt_descr *td, struct nand_bbt_descr *md) +{ + /* Search the primary table */ + search_bbt (mtd, buf, td); + + /* Search the mirror table */ + if (md) + search_bbt (mtd, buf, md); + + /* Force result check */ + return 1; +} + + +/** + * write_bbt - [GENERIC] (Re)write the bad block table + * + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @md: descriptor for the bad block table mirror + * @chipsel: selector for a specific chip, -1 for all + * + * (Re)write the bad block table + * +*/ +static int write_bbt (struct mtd_info *mtd, uint8_t *buf, + struct nand_bbt_descr *td, struct nand_bbt_descr *md, int chipsel) +{ + struct nand_chip *this = mtd->priv; + struct nand_oobinfo oobinfo; + struct erase_info einfo; + int i, j, res, chip = 0; + int bits, startblock, dir, page, offs, numblocks, sft, sftmsk; + int nrchips, bbtoffs, pageoffs; + uint8_t msk[4]; + uint8_t rcode = td->reserved_block_code; + size_t retlen, len = 0; + loff_t to; + + if (!rcode) + rcode = 0xff; + /* Write bad block table per chip rather than per device ? */ + if (td->options & NAND_BBT_PERCHIP) { + numblocks = (int) (this->chipsize >> this->bbt_erase_shift); + /* Full device write or specific chip ? */ + if (chipsel == -1) { + nrchips = this->numchips; + } else { + nrchips = chipsel + 1; + chip = chipsel; + } + } else { + numblocks = (int) (mtd->size >> this->bbt_erase_shift); + nrchips = 1; + } + + /* Loop through the chips */ + for (; chip < nrchips; chip++) { + + /* There was already a version of the table, reuse the page + * This applies for absolute placement too, as we have the + * page nr. in td->pages. + */ + if (td->pages[chip] != -1) { + page = td->pages[chip]; + goto write; + } + + /* Automatic placement of the bad block table */ + /* Search direction top -> down ? */ + if (td->options & NAND_BBT_LASTBLOCK) { + startblock = numblocks * (chip + 1) - 1; + dir = -1; + } else { + startblock = chip * numblocks; + dir = 1; + } + + for (i = 0; i < td->maxblocks; i++) { + int block = startblock + dir * i; + /* Check, if the block is bad */ + switch ((this->bbt[block >> 2] >> (2 * (block & 0x03))) & 0x03) { + case 0x01: + case 0x03: + continue; + } + page = block << (this->bbt_erase_shift - this->page_shift); + /* Check, if the block is used by the mirror table */ + if (!md || md->pages[chip] != page) + goto write; + } + printk (KERN_ERR "No space left to write bad block table\n"); + return -ENOSPC; +write: + + /* Set up shift count and masks for the flash table */ + bits = td->options & NAND_BBT_NRBITS_MSK; + switch (bits) { + case 1: sft = 3; sftmsk = 0x07; msk[0] = 0x00; msk[1] = 0x01; msk[2] = ~rcode; msk[3] = 0x01; break; + case 2: sft = 2; sftmsk = 0x06; msk[0] = 0x00; msk[1] = 0x01; msk[2] = ~rcode; msk[3] = 0x03; break; + case 4: sft = 1; sftmsk = 0x04; msk[0] = 0x00; msk[1] = 0x0C; msk[2] = ~rcode; msk[3] = 0x0f; break; + case 8: sft = 0; sftmsk = 0x00; msk[0] = 0x00; msk[1] = 0x0F; msk[2] = ~rcode; msk[3] = 0xff; break; + default: return -EINVAL; + } + + bbtoffs = chip * (numblocks >> 2); + + to = ((loff_t) page) << this->page_shift; + + memcpy (&oobinfo, this->autooob, sizeof(oobinfo)); + oobinfo.useecc = MTD_NANDECC_PLACEONLY; + + /* Must we save the block contents ? */ + if (td->options & NAND_BBT_SAVECONTENT) { + /* Make it block aligned */ + to &= ~((loff_t) ((1 << this->bbt_erase_shift) - 1)); + len = 1 << this->bbt_erase_shift; + res = mtd->read_ecc (mtd, to, len, &retlen, buf, &buf[len], &oobinfo); + if (res < 0) { + if (retlen != len) { + printk (KERN_INFO "nand_bbt: Error reading block for writing the bad block table\n"); + return res; + } + printk (KERN_WARNING "nand_bbt: ECC error while reading block for writing bad block table\n"); + } + /* Calc the byte offset in the buffer */ + pageoffs = page - (int)(to >> this->page_shift); + offs = pageoffs << this->page_shift; + /* Preset the bbt area with 0xff */ + memset (&buf[offs], 0xff, (size_t)(numblocks >> sft)); + /* Preset the bbt's oob area with 0xff */ + memset (&buf[len + pageoffs * mtd->oobsize], 0xff, + ((len >> this->page_shift) - pageoffs) * mtd->oobsize); + if (td->options & NAND_BBT_VERSION) { + buf[len + (pageoffs * mtd->oobsize) + td->veroffs] = td->version[chip]; + } + } else { + /* Calc length */ + len = (size_t) (numblocks >> sft); + /* Make it page aligned ! */ + len = (len + (mtd->oobblock-1)) & ~(mtd->oobblock-1); + /* Preset the buffer with 0xff */ + memset (buf, 0xff, len + (len >> this->page_shift) * mtd->oobsize); + offs = 0; + /* Pattern is located in oob area of first page */ + memcpy (&buf[len + td->offs], td->pattern, td->len); + if (td->options & NAND_BBT_VERSION) { + buf[len + td->veroffs] = td->version[chip]; + } + } + + /* walk through the memory table */ + for (i = 0; i < numblocks; ) { + uint8_t dat; + dat = this->bbt[bbtoffs + (i >> 2)]; + for (j = 0; j < 4; j++ , i++) { + int sftcnt = (i << (3 - sft)) & sftmsk; + /* Do not store the reserved bbt blocks ! */ + buf[offs + (i >> sft)] &= ~(msk[dat & 0x03] << sftcnt); + dat >>= 2; + } + } + + memset (&einfo, 0, sizeof (einfo)); + einfo.mtd = mtd; + einfo.addr = (unsigned long) to; + einfo.len = 1 << this->bbt_erase_shift; + res = nand_erase_nand (mtd, &einfo, 1); + if (res < 0) { + printk (KERN_WARNING "nand_bbt: Error during block erase: %d\n", res); + return res; + } + + res = mtd->write_ecc (mtd, to, len, &retlen, buf, &buf[len], &oobinfo); + if (res < 0) { + printk (KERN_WARNING "nand_bbt: Error while writing bad block table %d\n", res); + return res; + } + printk (KERN_DEBUG "Bad block table written to 0x%08x, version 0x%02X\n", + (unsigned int) to, td->version[chip]); + + /* Mark it as used */ + td->pages[chip] = page; + } + return 0; +} + +/** + * nand_memory_bbt - [GENERIC] create a memory based bad block table + * @mtd: MTD device structure + * @bd: descriptor for the good/bad block search pattern + * + * The function creates a memory based bbt by scanning the device + * for manufacturer / software marked good / bad blocks +*/ +static int nand_memory_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd) +{ + struct nand_chip *this = mtd->priv; + + /* Ensure that we only scan for the pattern and nothing else */ + bd->options = 0; + create_bbt (mtd, this->data_buf, bd, -1); + return 0; +} + +/** + * check_create - [GENERIC] create and write bbt(s) if neccecary + * @mtd: MTD device structure + * @buf: temporary buffer + * @bd: descriptor for the good/bad block search pattern + * + * The function checks the results of the previous call to read_bbt + * and creates / updates the bbt(s) if neccecary + * Creation is neccecary if no bbt was found for the chip/device + * Update is neccecary if one of the tables is missing or the + * version nr. of one table is less than the other +*/ +static int check_create (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd) +{ + int i, chips, writeops, chipsel, res; + struct nand_chip *this = mtd->priv; + struct nand_bbt_descr *td = this->bbt_td; + struct nand_bbt_descr *md = this->bbt_md; + struct nand_bbt_descr *rd, *rd2; + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) + chips = this->numchips; + else + chips = 1; + + for (i = 0; i < chips; i++) { + writeops = 0; + rd = NULL; + rd2 = NULL; + /* Per chip or per device ? */ + chipsel = (td->options & NAND_BBT_PERCHIP) ? i : -1; + /* Mirrored table avilable ? */ + if (md) { + if (td->pages[i] == -1 && md->pages[i] == -1) { + writeops = 0x03; + goto create; + } + + if (td->pages[i] == -1) { + rd = md; + td->version[i] = md->version[i]; + writeops = 1; + goto writecheck; + } + + if (md->pages[i] == -1) { + rd = td; + md->version[i] = td->version[i]; + writeops = 2; + goto writecheck; + } + + if (td->version[i] == md->version[i]) { + rd = td; + if (!(td->options & NAND_BBT_VERSION)) + rd2 = md; + goto writecheck; + } + + if (((int8_t) (td->version[i] - md->version[i])) > 0) { + rd = td; + md->version[i] = td->version[i]; + writeops = 2; + } else { + rd = md; + td->version[i] = md->version[i]; + writeops = 1; + } + + goto writecheck; + + } else { + if (td->pages[i] == -1) { + writeops = 0x01; + goto create; + } + rd = td; + goto writecheck; + } +create: + /* Create the bad block table by scanning the device ? */ + if (!(td->options & NAND_BBT_CREATE)) + continue; + + /* Create the table in memory by scanning the chip(s) */ + create_bbt (mtd, buf, bd, chipsel); + + td->version[i] = 1; + if (md) + md->version[i] = 1; +writecheck: + /* read back first ? */ + if (rd) + read_abs_bbt (mtd, buf, rd, chipsel); + /* If they weren't versioned, read both. */ + if (rd2) + read_abs_bbt (mtd, buf, rd2, chipsel); + + /* Write the bad block table to the device ? */ + if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, td, md, chipsel); + if (res < 0) + return res; + } + + /* Write the mirror bad block table to the device ? */ + if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, md, td, chipsel); + if (res < 0) + return res; + } + } + return 0; +} + +/** + * mark_bbt_regions - [GENERIC] mark the bad block table regions + * @mtd: MTD device structure + * @td: bad block table descriptor + * + * The bad block table regions are marked as "bad" to prevent + * accidental erasures / writes. The regions are identified by + * the mark 0x02. +*/ +static void mark_bbt_region (struct mtd_info *mtd, struct nand_bbt_descr *td) +{ + struct nand_chip *this = mtd->priv; + int i, j, chips, block, nrblocks, update; + uint8_t oldval, newval; + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) { + chips = this->numchips; + nrblocks = (int)(this->chipsize >> this->bbt_erase_shift); + } else { + chips = 1; + nrblocks = (int)(mtd->size >> this->bbt_erase_shift); + } + + for (i = 0; i < chips; i++) { + if ((td->options & NAND_BBT_ABSPAGE) || + !(td->options & NAND_BBT_WRITE)) { + if (td->pages[i] == -1) continue; + block = td->pages[i] >> (this->bbt_erase_shift - this->page_shift); + block <<= 1; + oldval = this->bbt[(block >> 3)]; + newval = oldval | (0x2 << (block & 0x06)); + this->bbt[(block >> 3)] = newval; + if ((oldval != newval) && td->reserved_block_code) + nand_update_bbt(mtd, block << (this->bbt_erase_shift - 1)); + continue; + } + update = 0; + if (td->options & NAND_BBT_LASTBLOCK) + block = ((i + 1) * nrblocks) - td->maxblocks; + else + block = i * nrblocks; + block <<= 1; + for (j = 0; j < td->maxblocks; j++) { + oldval = this->bbt[(block >> 3)]; + newval = oldval | (0x2 << (block & 0x06)); + this->bbt[(block >> 3)] = newval; + if (oldval != newval) update = 1; + block += 2; + } + /* If we want reserved blocks to be recorded to flash, and some + new ones have been marked, then we need to update the stored + bbts. This should only happen once. */ + if (update && td->reserved_block_code) + nand_update_bbt(mtd, (block - 2) << (this->bbt_erase_shift - 1)); + } +} + +/** + * nand_scan_bbt - [NAND Interface] scan, find, read and maybe create bad block table(s) + * @mtd: MTD device structure + * @bd: descriptor for the good/bad block search pattern + * + * The function checks, if a bad block table(s) is/are already + * available. If not it scans the device for manufacturer + * marked good / bad blocks and writes the bad block table(s) to + * the selected place. + * + * The bad block table memory is allocated here. It must be freed + * by calling the nand_free_bbt function. + * +*/ +int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd) +{ + struct nand_chip *this = mtd->priv; + int len, res = 0; + uint8_t *buf; + struct nand_bbt_descr *td = this->bbt_td; + struct nand_bbt_descr *md = this->bbt_md; + + len = mtd->size >> (this->bbt_erase_shift + 2); + /* Allocate memory (2bit per block) */ + this->bbt = kmalloc (len, GFP_KERNEL); + if (!this->bbt) { + printk (KERN_ERR "nand_scan_bbt: Out of memory\n"); + return -ENOMEM; + } + /* Clear the memory bad block table */ + memset (this->bbt, 0x00, len); + + /* If no primary table decriptor is given, scan the device + * to build a memory based bad block table + */ + if (!td) + return nand_memory_bbt(mtd, bd); + + /* Allocate a temporary buffer for one eraseblock incl. oob */ + len = (1 << this->bbt_erase_shift); + len += (len >> this->page_shift) * mtd->oobsize; + buf = kmalloc (len, GFP_KERNEL); + if (!buf) { + printk (KERN_ERR "nand_bbt: Out of memory\n"); + kfree (this->bbt); + this->bbt = NULL; + return -ENOMEM; + } + + /* Is the bbt at a given page ? */ + if (td->options & NAND_BBT_ABSPAGE) { + res = read_abs_bbts (mtd, buf, td, md); + } else { + /* Search the bad block table using a pattern in oob */ + res = search_read_bbts (mtd, buf, td, md); + } + + if (res) + res = check_create (mtd, buf, bd); + + /* Prevent the bbt regions from erasing / writing */ + mark_bbt_region (mtd, td); + if (md) + mark_bbt_region (mtd, md); + + kfree (buf); + return res; +} + + +/** + * nand_update_bbt - [NAND Interface] update bad block table(s) + * @mtd: MTD device structure + * @offs: the offset of the newly marked block + * + * The function updates the bad block table(s) +*/ +int nand_update_bbt (struct mtd_info *mtd, loff_t offs) +{ + struct nand_chip *this = mtd->priv; + int len, res = 0, writeops = 0; + int chip, chipsel; + uint8_t *buf; + struct nand_bbt_descr *td = this->bbt_td; + struct nand_bbt_descr *md = this->bbt_md; + + if (!this->bbt || !td) + return -EINVAL; + + len = mtd->size >> (this->bbt_erase_shift + 2); + /* Allocate a temporary buffer for one eraseblock incl. oob */ + len = (1 << this->bbt_erase_shift); + len += (len >> this->page_shift) * mtd->oobsize; + buf = kmalloc (len, GFP_KERNEL); + if (!buf) { + printk (KERN_ERR "nand_update_bbt: Out of memory\n"); + return -ENOMEM; + } + + writeops = md != NULL ? 0x03 : 0x01; + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) { + chip = (int) (offs >> this->chip_shift); + chipsel = chip; + } else { + chip = 0; + chipsel = -1; + } + + td->version[chip]++; + if (md) + md->version[chip]++; + + /* Write the bad block table to the device ? */ + if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, td, md, chipsel); + if (res < 0) + goto out; + } + /* Write the mirror bad block table to the device ? */ + if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, md, td, chipsel); + } + +out: + kfree (buf); + return res; +} + +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks + * + * The memory based patterns just + */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr smallpage_memorybased = { + .options = 0, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr smallpage_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +static uint8_t scan_agand_pattern[] = { 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7 }; + +static struct nand_bbt_descr agand_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 0x20, + .len = 6, + .pattern = scan_agand_pattern +}; + +/* Generic flash bbt decriptors +*/ +static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 8, + .len = 4, + .veroffs = 12, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 8, + .len = 4, + .veroffs = 12, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +/** + * nand_default_bbt - [NAND Interface] Select a default bad block table for the device + * @mtd: MTD device structure + * + * This function selects the default bad block table + * support for the device and calls the nand_scan_bbt function + * +*/ +int nand_default_bbt (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + /* Default for AG-AND. We must use a flash based + * bad block table as the devices have factory marked + * _good_ blocks. Erasing those blocks leads to loss + * of the good / bad information, so we _must_ store + * this information in a good / bad table during + * startup + */ + if (this->options & NAND_IS_AND) { + /* Use the default pattern descriptors */ + if (!this->bbt_td) { + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + } + this->options |= NAND_USE_FLASH_BBT; + return nand_scan_bbt (mtd, &agand_flashbased); + } + + + /* Is a flash based bad block table requested ? */ + if (this->options & NAND_USE_FLASH_BBT) { + /* Use the default pattern descriptors */ + if (!this->bbt_td) { + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + } + if (!this->badblock_pattern) { + this->badblock_pattern = (mtd->oobblock > 512) ? + &largepage_flashbased : &smallpage_flashbased; + } + } else { + this->bbt_td = NULL; + this->bbt_md = NULL; + if (!this->badblock_pattern) { + this->badblock_pattern = (mtd->oobblock > 512) ? + &largepage_memorybased : &smallpage_memorybased; + } + } + return nand_scan_bbt (mtd, this->badblock_pattern); +} + +/** + * nand_isbad_bbt - [NAND Interface] Check if a block is bad + * @mtd: MTD device structure + * @offs: offset in the device + * @allowbbt: allow access to bad block table region + * + */ +int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt) +{ + struct nand_chip *this = mtd->priv; + int block; + uint8_t res; + + /* Get block number * 2 */ + block = (int) (offs >> (this->bbt_erase_shift - 1)); + res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03; + + DEBUG (MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n", + (unsigned int)offs, res, block >> 1); + + switch ((int)res) { + case 0x00: return 0; + case 0x01: return 1; + case 0x02: return allowbbt ? 0 : 1; + } + return 1; +} + +#endif diff --git a/drivers/nand/nand_ecc.c b/drivers/nand/nand_ecc.c new file mode 100644 index 0000000..f33be96 --- /dev/null +++ b/drivers/nand/nand_ecc.c @@ -0,0 +1,244 @@ +/* + * This file contains an ECC algorithm from Toshiba that detects and + * corrects 1 bit errors in a 256 byte block of data. + * + * drivers/mtd/nand/nand_ecc.c + * + * Copyright (C) 2000-2004 Steven J. Hill (sjhill@realitydiluted.com) + * Toshiba America Electronics Components, Inc. + * + * $Id: nand_ecc.c,v 1.14 2004/06/16 15:34:37 gleixner Exp $ + * + * This file is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 or (at your option) any + * later version. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this file; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * As a special exception, if other files instantiate templates or use + * macros or inline functions from these files, or you compile these + * files and link them with other works to produce a work based on these + * files, these files do not by themselves cause the resulting work to be + * covered by the GNU General Public License. However the source code for + * these files must still be made available in accordance with section (3) + * of the GNU General Public License. + * + * This exception does not invalidate any other reasons why a work based on + * this file might be covered by the GNU General Public License. + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include +/* + * Pre-calculated 256-way 1 byte column parity + */ +static const u_char nand_ecc_precalc_table[] = { + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 +}; + + +/** + * nand_trans_result - [GENERIC] create non-inverted ECC + * @reg2: line parity reg 2 + * @reg3: line parity reg 3 + * @ecc_code: ecc + * + * Creates non-inverted ECC code from line parity + */ +static void nand_trans_result(u_char reg2, u_char reg3, + u_char *ecc_code) +{ + u_char a, b, i, tmp1, tmp2; + + /* Initialize variables */ + a = b = 0x80; + tmp1 = tmp2 = 0; + + /* Calculate first ECC byte */ + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + a >>= 1; + } + + /* Calculate second ECC byte */ + b = 0x80; + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + a >>= 1; + } + + /* Store two of the ECC bytes */ + ecc_code[0] = tmp1; + ecc_code[1] = tmp2; +} + +/** + * nand_calculate_ecc - [NAND Interface] Calculate 3 byte ECC code for 256 byte block + * @mtd: MTD block structure + * @dat: raw data + * @ecc_code: buffer for ECC + */ +int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) +{ + u_char idx, reg1, reg2, reg3; + int j; + + /* Initialize variables */ + reg1 = reg2 = reg3 = 0; + ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; + + /* Build up column parity */ + for(j = 0; j < 256; j++) { + + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[dat[j]]; + reg1 ^= (idx & 0x3f); + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (u_char) j; + reg2 ^= ~((u_char) j); + } + } + + /* Create non-inverted ECC code from line parity */ + nand_trans_result(reg2, reg3, ecc_code); + + /* Calculate final ECC code */ + ecc_code[0] = ~ecc_code[0]; + ecc_code[1] = ~ecc_code[1]; + ecc_code[2] = ((~reg1) << 2) | 0x03; + return 0; +} + +/** + * nand_correct_data - [NAND Interface] Detect and correct bit error(s) + * @mtd: MTD block structure + * @dat: raw data read from the chip + * @read_ecc: ECC from the chip + * @calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256 byte block + */ +int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + u_char a, b, c, d1, d2, d3, add, bit, i; + + /* Do error detection */ + d1 = calc_ecc[0] ^ read_ecc[0]; + d2 = calc_ecc[1] ^ read_ecc[1]; + d3 = calc_ecc[2] ^ read_ecc[2]; + + if ((d1 | d2 | d3) == 0) { + /* No errors */ + return 0; + } + else { + a = (d1 ^ (d1 >> 1)) & 0x55; + b = (d2 ^ (d2 >> 1)) & 0x55; + c = (d3 ^ (d3 >> 1)) & 0x54; + + /* Found and will correct single bit error in the data */ + if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { + c = 0x80; + add = 0; + a = 0x80; + for (i=0; i<4; i++) { + if (d1 & c) + add |= a; + c >>= 2; + a >>= 1; + } + c = 0x80; + for (i=0; i<4; i++) { + if (d2 & c) + add |= a; + c >>= 2; + a >>= 1; + } + bit = 0; + b = 0x04; + c = 0x80; + for (i=0; i<3; i++) { + if (d3 & c) + bit |= b; + c >>= 2; + b >>= 1; + } + b = 0x01; + a = dat[add]; + a ^= (b << bit); + dat[add] = a; + return 1; + } else { + i = 0; + while (d1) { + if (d1 & 0x01) + ++i; + d1 >>= 1; + } + while (d2) { + if (d2 & 0x01) + ++i; + d2 >>= 1; + } + while (d3) { + if (d3 & 0x01) + ++i; + d3 >>= 1; + } + if (i == 1) { + /* ECC Code Error Correction */ + read_ecc[0] = calc_ecc[0]; + read_ecc[1] = calc_ecc[1]; + read_ecc[2] = calc_ecc[2]; + return 2; + } + else { + /* Uncorrectable Error */ + return -1; + } + } + } + + /* Should never happen */ + return -1; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ diff --git a/drivers/nand/nand_ecc_rs.c b/drivers/nand/nand_ecc_rs.c new file mode 100644 index 0000000..f20e146 --- /dev/null +++ b/drivers/nand/nand_ecc_rs.c @@ -0,0 +1,535 @@ +/* + * This file contains an ECC algorithm from Toshiba that detects and + * corrects 1 bit errors in a 256 byte block of data. + * + * drivers/mtd/nand/nand_ecc.c + * + * Copyright (C) 2000-2004 Steven J. Hill (sjhill@realitydiluted.com) + * Toshiba America Electronics Components, Inc. + * + * $Id: nand_ecc.c,v 1.14 2004/06/16 15:34:37 gleixner Exp $ + * + * This file is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 or (at your option) any + * later version. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this file; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * As a special exception, if other files instantiate templates or use + * macros or inline functions from these files, or you compile these + * files and link them with other works to produce a work based on these + * files, these files do not by themselves cause the resulting work to be + * covered by the GNU General Public License. However the source code for + * these files must still be made available in accordance with section (3) + * of the GNU General Public License. + * + * This exception does not invalidate any other reasons why a work based on + * this file might be covered by the GNU General Public License. + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include +#include + +#define mm 10 /* RS code over GF(2**mm) - the size in bits of a symbol*/ +#define nn 1023 /* nn=2^mm -1 length of codeword */ +#define tt 4 /* number of errors that can be corrected */ +#define kk 1015 /* kk = number of information symbols kk = nn-2*tt */ + + +static char rs_initialized = 0; + +//typedef unsigned int gf; +typedef u_short tgf; /* data type of Galois Functions */ + +/* Primitive polynomials - irriducibile polynomial [ 1+x^3+x^10 ]*/ +short pp[mm+1] = { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1 }; + + +/* index->polynomial form conversion table */ +tgf alpha_to[nn + 1]; + +/* Polynomial->index form conversion table */ +tgf index_of[nn + 1]; + +/* Generator polynomial g(x) = 2*tt with roots @, @^2, .. ,@^(2*tt) */ +tgf Gg[nn - kk + 1]; + + +#define minimum(a,b) ((a) < (b) ? (a) : (b)) + +#define BLANK(a,n) {\ + short ci;\ + for(ci=0; ci<(n); ci++)\ + (a)[ci] = 0;\ + } + +#define COPY(a,b,n) {\ + short ci;\ + for(ci=(n)-1;ci >=0;ci--)\ + (a)[ci] = (b)[ci];\ + } +#define COPYDOWN(a,b,n) {\ + short ci;\ + for(ci=(n)-1;ci >=0;ci--)\ + (a)[ci] = (b)[ci];\ + } + + +/* generate GF(2^m) from the irreducible polynomial p(X) in p[0]..p[mm] + lookup tables: index->polynomial form alpha_to[] contains j=alpha^i; + polynomial form -> index form index_of[j=alpha^i] = i + alpha=2 is the primitive element of GF(2^m) +*/ + +void generate_gf(void) +{ + register int i, mask; + + mask = 1; + alpha_to[mm] = 0; + for (i = 0; i < mm; i++) { + alpha_to[i] = mask; + index_of[alpha_to[i]] = i; + if (pp[i] != 0) + alpha_to[mm] ^= mask; + mask <<= 1; + } + index_of[alpha_to[mm]] = mm; + + mask >>= 1; + for (i = mm + 1; i < nn; i++) { + if (alpha_to[i - 1] >= mask) + alpha_to[i] = alpha_to[mm] ^ ((alpha_to[i - 1] ^ mask) << 1); + else + alpha_to[i] = alpha_to[i - 1] << 1; + index_of[alpha_to[i]] = i; + } + index_of[0] = nn; + alpha_to[nn] = 0; +} + + +/* + * Obtain the generator polynomial of the tt-error correcting, + * length nn = (2^mm -1) + * Reed Solomon code from the product of (X + @^i), i=1..2*tt +*/ +void gen_poly(void) +{ + register int i, j; + + Gg[0] = alpha_to[1]; /* primitive element*/ + Gg[1] = 1; /* g(x) = (X+@^1) initially */ + for (i = 2; i <= nn - kk; i++) { + Gg[i] = 1; + /* + * Below multiply (Gg[0]+Gg[1]*x + ... +Gg[i]x^i) by + * (@^i + x) + */ + for (j = i - 1; j > 0; j--) + if (Gg[j] != 0) + Gg[j] = Gg[j - 1] ^ alpha_to[((index_of[Gg[j]]) + i)%nn]; + else + Gg[j] = Gg[j - 1]; + Gg[0] = alpha_to[((index_of[Gg[0]]) + i) % nn]; + } + /* convert Gg[] to index form for quicker encoding */ + for (i = 0; i <= nn - kk; i++) + Gg[i] = index_of[Gg[i]]; +} + + +/* + * take the string of symbols in data[i], i=0..(k-1) and encode + * systematically to produce nn-kk parity symbols in bb[0]..bb[nn-kk-1] data[] + * is input and bb[] is output in polynomial form. Encoding is done by using + * a feedback shift register with appropriate connections specified by the + * elements of Gg[], which was generated above. Codeword is c(X) = + * data(X)*X**(nn-kk)+ b(X) + */ +char encode_rs(dtype data[kk], dtype bb[nn-kk]) +{ + register int i, j; + tgf feedback; + + BLANK(bb,nn-kk); + for (i = kk - 1; i >= 0; i--) { + if(data[i] > nn) + return -1; /* Illegal symbol */ + feedback = index_of[data[i] ^ bb[nn - kk - 1]]; + if (feedback != nn) { /* feedback term is non-zero */ + for (j = nn - kk - 1; j > 0; j--) + if (Gg[j] != nn) + bb[j] = bb[j - 1] ^ alpha_to[(Gg[j] + feedback)%nn]; + else + bb[j] = bb[j - 1]; + bb[0] = alpha_to[(Gg[0] + feedback)%nn]; + } else { + for (j = nn - kk - 1; j > 0; j--) + bb[j] = bb[j - 1]; + bb[0] = 0; + } + } + return 0; +} + + + + +/* assume we have received bits grouped into mm-bit symbols in data[i], + i=0..(nn-1), We first compute the 2*tt syndromes, then we use the + Berlekamp iteration to find the error location polynomial elp[i]. + If the degree of the elp is >tt, we cannot correct all the errors + and hence just put out the information symbols uncorrected. If the + degree of elp is <=tt, we get the roots, hence the inverse roots, + the error location numbers. If the number of errors located does not + equal the degree of the elp, we have more than tt errors and cannot + correct them. Otherwise, we then solve for the error value at the + error location and correct the error.The procedure is that found in + Lin and Costello.*/ + +int decode_rs(dtype data[nn]) +{ + int deg_lambda, el, deg_omega; + int i, j, r; + tgf q,tmp,num1,num2,den,discr_r; + tgf recd[nn]; + tgf lambda[nn-kk + 1], s[nn-kk + 1]; /* Err+Eras Locator poly + * and syndrome poly */ + tgf b[nn-kk + 1], t[nn-kk + 1], omega[nn-kk + 1]; + tgf root[nn-kk], reg[nn-kk + 1], loc[nn-kk]; + int syn_error, count; + + + + /* data[] is in polynomial form, copy and convert to index form */ + for (i = nn-1; i >= 0; i--){ + + if(data[i] > nn) + return -1; /* Illegal symbol */ + + recd[i] = index_of[data[i]]; + } + + /* first form the syndromes; i.e., evaluate recd(x) at roots of g(x) + * namely @**(1+i), i = 0, ... ,(nn-kk-1) + */ + + syn_error = 0; + + for (i = 1; i <= nn-kk; i++) { + tmp = 0; + + for (j = 0; j < nn; j++) + if (recd[j] != nn) /* recd[j] in index form */ + tmp ^= alpha_to[(recd[j] + (1+i-1)*j)%nn]; + + syn_error |= tmp; /* set flag if non-zero syndrome => + * error */ + /* store syndrome in index form */ + s[i] = index_of[tmp]; + } + + if (!syn_error) { + /* + * if syndrome is zero, data[] is a codeword and there are no + * errors to correct. So return data[] unmodified + */ + return 0; + } + + BLANK(&lambda[1],nn-kk); + + lambda[0] = 1; + + for(i=0;i 0; j--) + if (reg[j] != nn) { + //reg[j] = modnn(reg[j] + j); + reg[j] = (reg[j] + j)%nn; + q ^= alpha_to[reg[j]]; + } + if (!q) { + /* store root (index-form) and error location number */ + root[count] = i; + loc[count] = nn - i; + count++; + } + } + +#ifdef DEBUG +/* + printf("\n Final error positions:\t"); + for (i = 0; i < count; i++) + printf("%d ", loc[i]); + printf("\n"); +*/ +#endif + + + + if (deg_lambda != count) { + /* + * deg(lambda) unequal to number of roots => uncorrectable + * error detected + */ + return -1; + } + /* + * Compute err evaluator poly omega(x) = s(x)*lambda(x) (modulo + * x**(nn-kk)). in index form. Also find deg(omega). + */ + + deg_omega = 0; + for (i = 0; i < nn-kk;i++){ + tmp = 0; + j = (deg_lambda < i) ? deg_lambda : i; + for(;j >= 0; j--){ + if ((s[i + 1 - j] != nn) && (lambda[j] != nn)) + //tmp ^= alpha_to[modnn(s[i + 1 - j] + lambda[j])]; + tmp ^= alpha_to[(s[i + 1 - j] + lambda[j])%nn]; + } + if(tmp != 0) + deg_omega = i; + omega[i] = index_of[tmp]; + } + omega[nn-kk] = nn; + + + + + /* + * Compute error values in poly-form. num1 = omega(inv(X(l))), num2 = + * inv(X(l))**(1-1) and den = lambda_pr(inv(X(l))) all in poly-form + */ + for (j = count-1; j >=0; j--) { + num1 = 0; + for (i = deg_omega; i >= 0; i--) { + if (omega[i] != nn) + //num1 ^= alpha_to[modnn(omega[i] + i * root[j])]; + num1 ^= alpha_to[(omega[i] + i * root[j])%nn]; + } + //num2 = alpha_to[modnn(root[j] * (1 - 1) + nn)]; + num2 = alpha_to[(root[j] * (1 - 1) + nn)%nn]; + den = 0; + + /* lambda[i+1] for i even is the formal derivative lambda_pr of lambda[i] */ + for (i = minimum(deg_lambda,nn-kk-1) & ~1; i >= 0; i -=2) { + if(lambda[i+1] != nn) + //den ^= alpha_to[modnn(lambda[i+1] + i * root[j])]; + den ^= alpha_to[(lambda[i+1] + i * root[j])%nn]; + } + if (den == 0) { +#ifdef DEBUG + printf("\n ERROR: denominator = 0\n"); +#endif + return -1; + } + /* Apply error to data */ + if (num1 != 0) { + //data[loc[j]] ^= alpha_to[modnn(index_of[num1] + index_of[num2] + nn - index_of[den])]; + data[loc[j]] ^= alpha_to[(index_of[num1] + index_of[num2] + nn - index_of[den])%nn]; + } + } + return count; +} + +/** + * nand_calculate_ecc - [NAND Interface] Calculate 3 byte ECC code for 256 byte block + * @mtd: MTD block structure + * @dat: raw data + * @ecc_code: buffer for ECC + */ +int nand_calculate_ecc_rs(struct mtd_info *mtd, const u_char *data, u_char *ecc_code) +{ + int i; + u_short rsdata[nn]; + + /* Generate Tables in first run */ + if (!rs_initialized) { + generate_gf(); + gen_poly(); + rs_initialized = 1; + } + + for(i=512; i> 8) | ((rsdata[0x3F7+1]) << 2); + *(ecc_code+2) = ((rsdata[0x3F7+1]) >> 6) | ((rsdata[0x3F7+2]) << 4); + *(ecc_code+3) = ((rsdata[0x3F7+2]) >> 4) | ((rsdata[0x3F7+3]) << 6); + *(ecc_code+4) = ((rsdata[0x3F7+3]) >> 2); + *(ecc_code+5) = (unsigned char) rsdata[kk+4]; + *(ecc_code+6) = ((rsdata[0x3F7+4]) >> 8) | ((rsdata[0x3F7+1+4]) << 2); + *(ecc_code+7) = ((rsdata[0x3F7+1+4]) >> 6) | ((rsdata[0x3F7+2+4]) << 4); + *(ecc_code+8) = ((rsdata[0x3F7+2+4]) >> 4) | ((rsdata[0x3F7+3+4]) << 6); + *(ecc_code+9) = ((rsdata[0x3F7+3+4]) >> 2); + + return 0; +} + +/** + * nand_correct_data - [NAND Interface] Detect and correct bit error(s) + * @mtd: MTD block structure + * @dat: raw data read from the chip + * @store_ecc: ECC from the chip + * @calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256 byte block + */ +int nand_correct_data_rs(struct mtd_info *mtd, u_char *data, u_char *store_ecc, u_char *calc_ecc) +{ + int ret,i; + u_short rsdata[nn]; + + /* Generate Tables in first run */ + if (!rs_initialized) { + generate_gf(); + gen_poly(); + rs_initialized = 1; + } + + /* is decode needed ? */ + if ( (*(u16*)store_ecc == *(u16*)calc_ecc) && + (*(u16*)(store_ecc + 2) == *(u16*)(calc_ecc + 2)) && + (*(u16*)(store_ecc + 4) == *(u16*)(calc_ecc + 4)) && + (*(u16*)(store_ecc + 6) == *(u16*)(calc_ecc + 6)) && + (*(u16*)(store_ecc + 8) == *(u16*)(calc_ecc + 8))) + { + return 0; + } + /* did we read an erased page ? */ + for(i = 0; i < 512 ;i += 4) + { + if(*(u32*)(data+i) != 0xFFFFFFFF) + { + goto correct; + } + } + + /* page was erased, return gracefully */ + return 0; + + +correct: + for(i=512; i>2); + rsdata[kk+2] = ( (*(store_ecc+3) & 0x3F) <<4) | (*(store_ecc+2)>>4); + rsdata[kk+3] = (*(store_ecc+4) <<2) | (*(store_ecc+3)>>6); + + rsdata[kk+4] = ( (*(store_ecc+1+5) & 0x03) <<8) | (*(store_ecc+5)); + rsdata[kk+5] = ( (*(store_ecc+2+5) & 0x0F) <<6) | (*(store_ecc+1+5)>>2); + rsdata[kk+6] = ( (*(store_ecc+3+5) & 0x3F) <<4) | (*(store_ecc+2+5)>>4); + rsdata[kk+7] = (*(store_ecc+4+5) <<2) | (*(store_ecc+3+5)>>6); + + ret = decode_rs(rsdata); + + /* Check for excessive errors */ + if ((ret > tt) || (ret < 0)) + return -1; + + /* Copy corrected data */ + for (i=0; i<512; i++) + data[i] = (unsigned char) rsdata[i]; + + return 0; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c new file mode 100644 index 0000000..01b2d6b --- /dev/null +++ b/drivers/nand/nand_ids.c @@ -0,0 +1,129 @@ +/* + * drivers/mtd/nandids.c + * + * Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de) + * + * $Id: nand_ids.c,v 1.10 2004/05/26 13:40:12 gleixner Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include + +/* +* Chip ID list +* +* Name. ID code, pagesize, chipsize in MegaByte, eraseblock size, +* options +* +* Pagesize; 0, 256, 512 +* 0 get this information from the extended chip ID ++ 256 256 Byte page size +* 512 512 Byte page size +*/ +struct nand_flash_dev nand_flash_ids[] = { + {"NAND 1MB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0}, + {"NAND 2MB 5V 8-bit", 0x64, 256, 2, 0x1000, 0}, + {"NAND 4MB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0}, + {"NAND 1MB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0}, + {"NAND 1MB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, + {"NAND 2MB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0}, + {"NAND 4MB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0}, + {"NAND 4MB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0}, + {"NAND 4MB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0}, + {"NAND 8MB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0}, + + {"NAND 8MB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0}, + {"NAND 8MB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0}, + {"NAND 8MB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16}, + {"NAND 8MB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16}, + + {"NAND 16MB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0}, + {"NAND 16MB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0}, + {"NAND 16MB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 16MB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 32MB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0}, + {"NAND 32MB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0}, + {"NAND 32MB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 32MB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 64MB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0}, + {"NAND 64MB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0}, + {"NAND 64MB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 64MB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 128MB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0}, + {"NAND 128MB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0}, + {"NAND 128MB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 128MB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 256MB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0}, + + /* These are the new chips with large page size. The pagesize + * and the erasesize is determined from the extended id bytes + */ + /* 1 Gigabit */ + {"NAND 128MB 1,8V 8-bit", 0xA1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 128MB 3,3V 8-bit", 0xF1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 128MB 1,8V 16-bit", 0xB1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 128MB 3,3V 16-bit", 0xC1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 2 Gigabit */ + {"NAND 256MB 1,8V 8-bit", 0xAA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 256MB 3,3V 8-bit", 0xDA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 256MB 1,8V 16-bit", 0xBA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 256MB 3,3V 16-bit", 0xCA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 4 Gigabit */ + {"NAND 512MB 1,8V 8-bit", 0xAC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 512MB 3,3V 8-bit", 0xDC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 512MB 1,8V 16-bit", 0xBC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 512MB 3,3V 16-bit", 0xCC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 8 Gigabit */ + {"NAND 1GB 1,8V 8-bit", 0xA3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 1GB 3,3V 8-bit", 0xD3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 1GB 1,8V 16-bit", 0xB3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 1GB 3,3V 16-bit", 0xC3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 16 Gigabit */ + {"NAND 2GB 1,8V 8-bit", 0xA5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 2GB 3,3V 8-bit", 0xD5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 2GB 1,8V 16-bit", 0xB5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 2GB 3,3V 16-bit", 0xC5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* Renesas AND 1 Gigabit. Those chips do not support extended id and have a strange page/block layout ! + * The chosen minimum erasesize is 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page planes + * 1 block = 2 pages, but due to plane arrangement the blocks 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 + * Anyway JFFS2 would increase the eraseblock size so we chose a combined one which can be erased in one go + * There are more speed improvements for reads and writes possible, but not implemented now + */ + {"AND 128MB 3,3V 8-bit", 0x01, 2048, 128, 0x4000, NAND_IS_AND | NAND_NO_AUTOINCR | NAND_4PAGE_ARRAY}, + + {NULL,} +}; + +/* +* Manufacturer ID list +*/ +struct nand_manufacturers nand_manuf_ids[] = { + {NAND_MFR_TOSHIBA, "Toshiba"}, + {NAND_MFR_SAMSUNG, "Samsung"}, + {NAND_MFR_FUJITSU, "Fujitsu"}, + {NAND_MFR_NATIONAL, "National"}, + {NAND_MFR_RENESAS, "Renesas"}, + {NAND_MFR_STMICRO, "ST Micro"}, + {NAND_MFR_HYNIX, "Hynix"}, + {NAND_MFR_MICRON, "Micron"}, + {NAND_MFR_AMD, "AMD"}, + {0x0, "Unknown"} +}; +#endif diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c new file mode 100644 index 0000000..3db6af1 --- /dev/null +++ b/drivers/nand/nand_util.c @@ -0,0 +1,872 @@ +/* + * drivers/nand/nand_util.c + * + * Copyright (C) 2006 by Weiss-Electronic GmbH. + * All rights reserved. + * + * @author: Guido Classen + * @descr: NAND Flash support + * @references: borrowed heavily from Linux mtd-utils code: + * flash_eraseall.c by Arcom Control System Ltd + * nandwrite.c by Steven J. Hill (sjhill@realitydiluted.com) + * and Thomas Gleixner (tglx@linutronix.de) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include +#include +#include +#include + +#include +#include + +typedef struct erase_info erase_info_t; +typedef struct mtd_info mtd_info_t; + +/* support only for native endian JFFS2 */ +#define cpu_to_je16(x) (x) +#define cpu_to_je32(x) (x) + +/*****************************************************************************/ +static int nand_block_bad_scrub(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + return 0; +} + +/** + * nand_erase_opts: - erase NAND flash with support for various options + * (jffs2 formating) + * + * @param meminfo NAND device to erase + * @param opts options, @see struct nand_erase_options + * @return 0 in case of success + * + * This code is ported from flash_eraseall.c from Linux mtd utils by + * Arcom Control System Ltd. + */ +int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) +{ + struct jffs2_unknown_node cleanmarker; + int clmpos = 0; + int clmlen = 8; + erase_info_t erase; + ulong erase_length; + int isNAND; + int bbtest = 1; + int result; + int percent_complete = -1; + int (*nand_block_bad_old)(struct mtd_info *, loff_t, int) = NULL; + const char *mtd_device = meminfo->name; + + memset(&erase, 0, sizeof(erase)); + + erase.mtd = meminfo; + erase.len = meminfo->erasesize; + erase.addr = opts->offset; + erase_length = opts->length; + + isNAND = meminfo->type == MTD_NANDFLASH ? 1 : 0; + + if (opts->jffs2) { + cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK); + cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER); + if (isNAND) { + struct nand_oobinfo *oobinfo = &meminfo->oobinfo; + + /* check for autoplacement */ + if (oobinfo->useecc == MTD_NANDECC_AUTOPLACE) { + /* get the position of the free bytes */ + if (!oobinfo->oobfree[0][1]) { + printf(" Eeep. Autoplacement selected " + "and no empty space in oob\n"); + return -1; + } + clmpos = oobinfo->oobfree[0][0]; + clmlen = oobinfo->oobfree[0][1]; + if (clmlen > 8) + clmlen = 8; + } else { + /* legacy mode */ + switch (meminfo->oobsize) { + case 8: + clmpos = 6; + clmlen = 2; + break; + case 16: + clmpos = 8; + clmlen = 8; + break; + case 64: + clmpos = 16; + clmlen = 8; + break; + } + } + + cleanmarker.totlen = cpu_to_je32(8); + } else { + cleanmarker.totlen = + cpu_to_je32(sizeof(struct jffs2_unknown_node)); + } + cleanmarker.hdr_crc = cpu_to_je32( + crc32_no_comp(0, (unsigned char *) &cleanmarker, + sizeof(struct jffs2_unknown_node) - 4)); + } + /* scrub option allows to erase badblock. To prevent internal + * check from erase() method, set block check method to dummy + * and disable bad block table while erasing. + */ + if (opts->scrub) { + struct nand_chip *priv_nand = meminfo->priv; + + nand_block_bad_old = priv_nand->block_bad; + priv_nand->block_bad = nand_block_bad_scrub; + /* we don't need the bad block table anymore... + * after scrub, there are no bad blocks left! + */ + if (priv_nand->bbt) { + kfree(priv_nand->bbt); + } + priv_nand->bbt = NULL; + } + + if (erase_length < meminfo->erasesize) { + printf("Warning: Erase size 0x%08lx smaller than one " \ + "erase block 0x%08x\n",erase_length, meminfo->erasesize); + printf(" Erasing 0x%08x instead\n", meminfo->erasesize); + erase_length = meminfo->erasesize; + } + + for (; + erase.addr < opts->offset + erase_length; + erase.addr += meminfo->erasesize) { + WATCHDOG_RESET (); + + if (!opts->scrub && bbtest) { + int ret = meminfo->block_isbad(meminfo, erase.addr); + if (ret > 0) { + if (!opts->quiet) + printf("\rSkipping bad block at " + "0x%08x " + " \n", + erase.addr); + continue; + + } else if (ret < 0) { + printf("\n%s: MTD get bad block failed: %d\n", + mtd_device, + ret); + return -1; + } + } + result = meminfo->erase(meminfo, &erase); + if (result != 0) { + printf("\n%s: MTD Erase failure: %d\n", + mtd_device, result); + continue; + } + /* format for JFFS2 ? */ + if (opts->jffs2) { + /* write cleanmarker */ + if (isNAND) { + size_t written; + result = meminfo->write_oob(meminfo, + erase.addr + clmpos, + clmlen, + &written, + (unsigned char *) + &cleanmarker); + if (result != 0) { + printf("\n%s: MTD writeoob failure: %d\n", + mtd_device, result); + continue; + } + } else { + printf("\n%s: this erase routine only supports" + " NAND devices!\n", + mtd_device); + } + } + if (!opts->quiet) { + unsigned long long n =(unsigned long long) + (erase.addr + meminfo->erasesize - opts->offset) + * 100; + int percent; + + do_div(n, erase_length); + percent = (int)n; + + /* output progress message only at whole percent + * steps to reduce the number of messages printed + * on (slow) serial consoles + */ + if (percent != percent_complete) { + percent_complete = percent; + + printf("\rErasing at 0x%x -- %3d%% complete.", + erase.addr, percent); + + if (opts->jffs2 && result == 0) + printf(" Cleanmarker written at 0x%x.", + erase.addr); + } + } + } + if (!opts->quiet) + printf("\n"); + + if (nand_block_bad_old) { + struct nand_chip *priv_nand = meminfo->priv; + + priv_nand->block_bad = nand_block_bad_old; + priv_nand->scan_bbt(meminfo); + } + return 0; +} + +#define MAX_PAGE_SIZE 4096 +#define MAX_OOB_SIZE 218 + +/* + * buffer array used for writing data + */ +static unsigned char data_buf[MAX_PAGE_SIZE]; +static unsigned char oob_buf[MAX_OOB_SIZE]; + +/* OOB layouts to pass into the kernel as default */ +static struct nand_oobinfo none_oobinfo = { + .useecc = MTD_NANDECC_OFF, +}; + +static struct nand_oobinfo jffs2_oobinfo = { + .useecc = MTD_NANDECC_PLACE, + .eccbytes = 6, + .eccpos = { 0, 1, 2, 3, 6, 7 } +}; + +static struct nand_oobinfo yaffs_oobinfo = { + .useecc = MTD_NANDECC_PLACE, + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15} +}; + +static struct nand_oobinfo autoplace_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE +}; + +/** + * nand_write_opts: - write image to NAND flash with support for various options + * + * @param meminfo NAND device to erase + * @param opts write options (@see nand_write_options) + * @return 0 in case of success + * + * This code is ported from nandwrite.c from Linux mtd utils by + * Steven J. Hill and Thomas Gleixner. + */ +int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts) +{ + int imglen = 0; + int pagelen; + int baderaseblock; + int blockstart = -1; + loff_t offs; + int readlen; + int oobinfochanged = 0; + int percent_complete = -1; + struct nand_oobinfo old_oobinfo; + ulong mtdoffset = opts->offset; + ulong erasesize_blockalign; + u_char *buffer = opts->buffer; + size_t written; + int result; + + if (opts->pad && opts->writeoob) { + printf("Can't pad when oob data is present.\n"); + return -1; + } + + /* set erasesize to specified number of blocks - to match + * jffs2 (virtual) block size */ + if (opts->blockalign == 0) { + erasesize_blockalign = meminfo->erasesize; + } else { + erasesize_blockalign = meminfo->erasesize * opts->blockalign; + } + + /* make sure device page sizes are valid */ + if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512) + && !(meminfo->oobsize == 8 && meminfo->oobblock == 256) + && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) { + printf("Unknown flash (not normal NAND)\n"); + return -1; + } + + /* read the current oob info */ + memcpy(&old_oobinfo, &meminfo->oobinfo, sizeof(old_oobinfo)); + + /* write without ecc? */ + if (opts->noecc) { + memcpy(&meminfo->oobinfo, &none_oobinfo, + sizeof(meminfo->oobinfo)); + oobinfochanged = 1; + } + + /* autoplace ECC? */ + if (opts->autoplace && (old_oobinfo.useecc != MTD_NANDECC_AUTOPLACE)) { + + memcpy(&meminfo->oobinfo, &autoplace_oobinfo, + sizeof(meminfo->oobinfo)); + oobinfochanged = 1; + } + + /* force OOB layout for jffs2 or yaffs? */ + if (opts->forcejffs2 || opts->forceyaffs) { + struct nand_oobinfo *oobsel = + opts->forcejffs2 ? &jffs2_oobinfo : &yaffs_oobinfo; + + if (meminfo->oobsize == 8) { + if (opts->forceyaffs) { + printf("YAFSS cannot operate on " + "256 Byte page size\n"); + goto restoreoob; + } + /* Adjust number of ecc bytes */ + jffs2_oobinfo.eccbytes = 3; + } + + memcpy(&meminfo->oobinfo, oobsel, sizeof(meminfo->oobinfo)); + } + + /* get image length */ + imglen = opts->length; + pagelen = meminfo->oobblock + + ((opts->writeoob != 0) ? meminfo->oobsize : 0); + + /* check, if file is pagealigned */ + if ((!opts->pad) && ((imglen % pagelen) != 0)) { + printf("Input block length is not page aligned\n"); + goto restoreoob; + } + + /* check, if length fits into device */ + if (((imglen / pagelen) * meminfo->oobblock) + > (meminfo->size - opts->offset)) { + printf("Image %d bytes, NAND page %d bytes, " + "OOB area %u bytes, device size %u bytes\n", + imglen, pagelen, meminfo->oobblock, meminfo->size); + printf("Input block does not fit into device\n"); + goto restoreoob; + } + + if (!opts->quiet) + printf("\n"); + + /* get data from input and write to the device */ + while (imglen && (mtdoffset < meminfo->size)) { + + WATCHDOG_RESET (); + + /* + * new eraseblock, check for bad block(s). Stay in the + * loop to be sure if the offset changes because of + * a bad block, that the next block that will be + * written to is also checked. Thus avoiding errors if + * the block(s) after the skipped block(s) is also bad + * (number of blocks depending on the blockalign + */ + while (blockstart != (mtdoffset & (~erasesize_blockalign+1))) { + blockstart = mtdoffset & (~erasesize_blockalign+1); + offs = blockstart; + baderaseblock = 0; + + /* check all the blocks in an erase block for + * bad blocks */ + do { + int ret = meminfo->block_isbad(meminfo, offs); + + if (ret < 0) { + printf("Bad block check failed\n"); + goto restoreoob; + } + if (ret == 1) { + baderaseblock = 1; + if (!opts->quiet) + printf("\rBad block at 0x%lx " + "in erase block from " + "0x%x will be skipped\n", + (long) offs, + blockstart); + } + + if (baderaseblock) { + mtdoffset = blockstart + + erasesize_blockalign; + } + offs += erasesize_blockalign + / opts->blockalign; + } while (offs < blockstart + erasesize_blockalign); + } + + readlen = meminfo->oobblock; + if (opts->pad && (imglen < readlen)) { + readlen = imglen; + memset(data_buf + readlen, 0xff, + meminfo->oobblock - readlen); + } + + /* read page data from input memory buffer */ + memcpy(data_buf, buffer, readlen); + buffer += readlen; + + if (opts->writeoob) { + /* read OOB data from input memory block, exit + * on failure */ + memcpy(oob_buf, buffer, meminfo->oobsize); + buffer += meminfo->oobsize; + + /* write OOB data first, as ecc will be placed + * in there*/ + result = meminfo->write_oob(meminfo, + mtdoffset, + meminfo->oobsize, + &written, + (unsigned char *) + &oob_buf); + + if (result != 0) { + printf("\nMTD writeoob failure: %d\n", + result); + goto restoreoob; + } + imglen -= meminfo->oobsize; + } + + /* write out the page data */ + result = meminfo->write(meminfo, + mtdoffset, + meminfo->oobblock, + &written, + (unsigned char *) &data_buf); + + if (result != 0) { + printf("writing NAND page at offset 0x%lx failed\n", + mtdoffset); + goto restoreoob; + } + imglen -= readlen; + + if (!opts->quiet) { + unsigned long long n = (unsigned long long) + (opts->length-imglen) * 100; + int percent; + + do_div(n, opts->length); + percent = (int)n; + + /* output progress message only at whole percent + * steps to reduce the number of messages printed + * on (slow) serial consoles + */ + if (percent != percent_complete) { + printf("\rWriting data at 0x%lx " + "-- %3d%% complete.", + mtdoffset, percent); + percent_complete = percent; + } + } + + mtdoffset += meminfo->oobblock; + } + + if (!opts->quiet) + printf("\n"); + +restoreoob: + if (oobinfochanged) { + memcpy(&meminfo->oobinfo, &old_oobinfo, + sizeof(meminfo->oobinfo)); + } + + if (imglen > 0) { + printf("Data did not fit into device, due to bad blocks\n"); + return -1; + } + + /* return happy */ + return 0; +} + +/** + * nand_read_opts: - read image from NAND flash with support for various options + * + * @param meminfo NAND device to erase + * @param opts read options (@see struct nand_read_options) + * @return 0 in case of success + * + */ +int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts) +{ + int imglen = opts->length; + int pagelen; + int baderaseblock; + int blockstart = -1; + int percent_complete = -1; + loff_t offs; + size_t readlen; + ulong mtdoffset = opts->offset; + u_char *buffer = opts->buffer; + int result; + + /* make sure device page sizes are valid */ + if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512) + && !(meminfo->oobsize == 8 && meminfo->oobblock == 256) + && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) { + printf("Unknown flash (not normal NAND)\n"); + return -1; + } + + pagelen = meminfo->oobblock + + ((opts->readoob != 0) ? meminfo->oobsize : 0); + + /* check, if length is not larger than device */ + if (((imglen / pagelen) * meminfo->oobblock) + > (meminfo->size - opts->offset)) { + printf("Image %d bytes, NAND page %d bytes, " + "OOB area %u bytes, device size %u bytes\n", + imglen, pagelen, meminfo->oobblock, meminfo->size); + printf("Input block is larger than device\n"); + return -1; + } + + if (!opts->quiet) + printf("\n"); + + /* get data from input and write to the device */ + while (imglen && (mtdoffset < meminfo->size)) { + + WATCHDOG_RESET (); + + /* + * new eraseblock, check for bad block(s). Stay in the + * loop to be sure if the offset changes because of + * a bad block, that the next block that will be + * written to is also checked. Thus avoiding errors if + * the block(s) after the skipped block(s) is also bad + * (number of blocks depending on the blockalign + */ + while (blockstart != (mtdoffset & (~meminfo->erasesize+1))) { + blockstart = mtdoffset & (~meminfo->erasesize+1); + offs = blockstart; + baderaseblock = 0; + + /* check all the blocks in an erase block for + * bad blocks */ + do { + int ret = meminfo->block_isbad(meminfo, offs); + + if (ret < 0) { + printf("Bad block check failed\n"); + return -1; + } + if (ret == 1) { + baderaseblock = 1; + if (!opts->quiet) + printf("\rBad block at 0x%lx " + "in erase block from " + "0x%x will be skipped\n", + (long) offs, + blockstart); + } + + if (baderaseblock) { + mtdoffset = blockstart + + meminfo->erasesize; + } + offs += meminfo->erasesize; + + } while (offs < blockstart + meminfo->erasesize); + } + + + /* read page data to memory buffer */ + result = meminfo->read(meminfo, + mtdoffset, + meminfo->oobblock, + &readlen, + (unsigned char *) &data_buf); + + if (result != 0) { + printf("reading NAND page at offset 0x%lx failed\n", + mtdoffset); + return -1; + } + + if (imglen < readlen) { + readlen = imglen; + } + + memcpy(buffer, data_buf, readlen); + buffer += readlen; + imglen -= readlen; + + if (opts->readoob) { + result = meminfo->read_oob(meminfo, + mtdoffset, + meminfo->oobsize, + &readlen, + (unsigned char *) + &oob_buf); + + if (result != 0) { + printf("\nMTD readoob failure: %d\n", + result); + return -1; + } + + + if (imglen < readlen) { + readlen = imglen; + } + + memcpy(buffer, oob_buf, readlen); + + buffer += readlen; + imglen -= readlen; + } + + if (!opts->quiet) { + unsigned long long n = (unsigned long long) + (opts->length-imglen) * 100; + int percent; + + do_div(n, opts->length); + percent = (int)n; + + /* output progress message only at whole percent + * steps to reduce the number of messages printed + * on (slow) serial consoles + */ + if (percent != percent_complete) { + if (!opts->quiet) + printf("\rReading data from 0x%lx " + "-- %3d%% complete.", + mtdoffset, percent); + percent_complete = percent; + } + } + + mtdoffset += meminfo->oobblock; + } + + if (!opts->quiet) + printf("\n"); + + if (imglen > 0) { + printf("Could not read entire image due to bad blocks\n"); + return -1; + } + + /* return happy */ + return 0; +} + +/****************************************************************************** + * Support for locking / unlocking operations of some NAND devices + *****************************************************************************/ + +#define NAND_CMD_LOCK 0x2a +#define NAND_CMD_LOCK_TIGHT 0x2c +#define NAND_CMD_UNLOCK1 0x23 +#define NAND_CMD_UNLOCK2 0x24 +#define NAND_CMD_LOCK_STATUS 0x7a + +/** + * nand_lock: Set all pages of NAND flash chip to the LOCK or LOCK-TIGHT + * state + * + * @param meminfo nand mtd instance + * @param tight bring device in lock tight mode + * + * @return 0 on success, -1 in case of error + * + * The lock / lock-tight command only applies to the whole chip. To get some + * parts of the chip lock and others unlocked use the following sequence: + * + * - Lock all pages of the chip using nand_lock(mtd, 0) (or the lockpre pin) + * - Call nand_unlock() once for each consecutive area to be unlocked + * - If desired: Bring the chip to the lock-tight state using nand_lock(mtd, 1) + * + * If the device is in lock-tight state software can't change the + * current active lock/unlock state of all pages. nand_lock() / nand_unlock() + * calls will fail. It is only posible to leave lock-tight state by + * an hardware signal (low pulse on _WP pin) or by power down. + */ +int nand_lock(nand_info_t *meminfo, int tight) +{ + int ret = 0; + int status; + struct nand_chip *this = meminfo->priv; + + /* select the NAND device */ + this->select_chip(meminfo, 0); + + this->cmdfunc(meminfo, + (tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK), + -1, -1); + + /* call wait ready function */ + status = this->waitfunc(meminfo, this, FL_WRITING); + + /* see if device thinks it succeeded */ + if (status & 0x01) { + ret = -1; + } + + /* de-select the NAND device */ + this->select_chip(meminfo, -1); + return ret; +} + +/** + * nand_get_lock_status: - query current lock state from one page of NAND + * flash + * + * @param meminfo nand mtd instance + * @param offset page address to query (muss be page aligned!) + * + * @return -1 in case of error + * >0 lock status: + * bitfield with the following combinations: + * NAND_LOCK_STATUS_TIGHT: page in tight state + * NAND_LOCK_STATUS_LOCK: page locked + * NAND_LOCK_STATUS_UNLOCK: page unlocked + * + */ +int nand_get_lock_status(nand_info_t *meminfo, ulong offset) +{ + int ret = 0; + int chipnr; + int page; + struct nand_chip *this = meminfo->priv; + + /* select the NAND device */ + chipnr = (int)(offset >> this->chip_shift); + this->select_chip(meminfo, chipnr); + + + if ((offset & (meminfo->oobblock - 1)) != 0) { + printf ("nand_get_lock_status: " + "Start address must be beginning of " + "nand page!\n"); + ret = -1; + goto out; + } + + /* check the Lock Status */ + page = (int)(offset >> this->page_shift); + this->cmdfunc(meminfo, NAND_CMD_LOCK_STATUS, -1, page & this->pagemask); + + ret = this->read_byte(meminfo) & (NAND_LOCK_STATUS_TIGHT + | NAND_LOCK_STATUS_LOCK + | NAND_LOCK_STATUS_UNLOCK); + + out: + /* de-select the NAND device */ + this->select_chip(meminfo, -1); + return ret; +} + +/** + * nand_unlock: - Unlock area of NAND pages + * only one consecutive area can be unlocked at one time! + * + * @param meminfo nand mtd instance + * @param start start byte address + * @param length number of bytes to unlock (must be a multiple of + * page size nand->oobblock) + * + * @return 0 on success, -1 in case of error + */ +int nand_unlock(nand_info_t *meminfo, ulong start, ulong length) +{ + int ret = 0; + int chipnr; + int status; + int page; + struct nand_chip *this = meminfo->priv; + printf ("nand_unlock: start: %08x, length: %d!\n", + (int)start, (int)length); + + /* select the NAND device */ + chipnr = (int)(start >> this->chip_shift); + this->select_chip(meminfo, chipnr); + + /* check the WP bit */ + this->cmdfunc(meminfo, NAND_CMD_STATUS, -1, -1); + if ((this->read_byte(meminfo) & 0x80) == 0) { + printf ("nand_unlock: Device is write protected!\n"); + ret = -1; + goto out; + } + + if ((start & (meminfo->oobblock - 1)) != 0) { + printf ("nand_unlock: Start address must be beginning of " + "nand page!\n"); + ret = -1; + goto out; + } + + if (length == 0 || (length & (meminfo->oobblock - 1)) != 0) { + printf ("nand_unlock: Length must be a multiple of nand page " + "size!\n"); + ret = -1; + goto out; + } + + /* submit address of first page to unlock */ + page = (int)(start >> this->page_shift); + this->cmdfunc(meminfo, NAND_CMD_UNLOCK1, -1, page & this->pagemask); + + /* submit ADDRESS of LAST page to unlock */ + page += (int)(length >> this->page_shift) - 1; + this->cmdfunc(meminfo, NAND_CMD_UNLOCK2, -1, page & this->pagemask); + + /* call wait ready function */ + status = this->waitfunc(meminfo, this, FL_WRITING); + /* see if device thinks it succeeded */ + if (status & 0x01) { + /* there was an error */ + ret = -1; + goto out; + } + + out: + /* de-select the NAND device */ + this->select_chip(meminfo, -1); + return ret; +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) */ diff --git a/drivers/pci.c b/drivers/pci.c index 5360030..ad9ae41 100644 --- a/drivers/pci.c +++ b/drivers/pci.c @@ -28,15 +28,21 @@ * PCI routines */ +/* #define DEBUG */ #include - #ifdef CONFIG_PCI - #include #include #include #include +/* #define DEBUG */ +#ifdef DEBUG +#define debug(x...) printf(x) +#else +#define debug(x...) +#endif /* DEBUG */ + #define PCI_HOSE_OP(rw, size, type) \ int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ pci_dev_t dev, \ @@ -141,8 +147,9 @@ struct pci_controller *pci_bus_to_hose (int bus) for (hose = hose_head; hose; hose = hose->next) if (bus >= hose->first_busno && bus <= hose->last_busno) return hose; - +#ifndef CONFIG_MARVELL printf("pci_bus_to_hose() failed\n"); +#endif return NULL; } @@ -423,6 +430,8 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); dev += PCI_BDF(0,0,1)) { + +#ifndef CONFIG_MARVELL /* Skip our host bridge */ if ( dev == PCI_BDF(hose->first_busno,0,0) ) { #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */ @@ -436,7 +445,7 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) continue; /* Skip our host bridge */ #endif } - +#endif /* CONFIG_MARVELL */ if (PCI_FUNC(dev) && !found_multi) continue; diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 3302457..9171be7 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -19,7 +19,7 @@ #include -#undef DEBUG +/* #define DEBUG */ #ifdef DEBUG #define DEBUGF(x...) printf(x) #else @@ -53,14 +53,16 @@ int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned addr = ((res->bus_lower - 1) | (size - 1)) + 1; + DEBUGF("addr 0x%x size 0x%x\n",addr, size); + DEBUGF("res->bus_start 0x%x res->size 0x%x\n",res->bus_start, res->size); if (addr - res->bus_start + size > res->size) { - DEBUGF("No room in resource"); + DEBUGF("No room in resource\n"); goto error; } res->bus_lower = addr + size; - DEBUGF("address=0x%lx", addr); + DEBUGF("address=0x%lx\n", addr); *bar = addr; return 0; diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c index e8f19f5..8860650 100644 --- a/drivers/pci_indirect.c +++ b/drivers/pci_indirect.c @@ -12,7 +12,8 @@ #include #ifdef CONFIG_PCI -#if (!defined(__I386__) && !defined(CONFIG_IXDP425)) +#ifndef __I386__ +#ifndef __ARM__ #include #include @@ -118,5 +119,6 @@ void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) hose->cfg_data = (unsigned char *) cfg_data; } +#endif /* __ARM__ */ #endif /* !__I386__ && !CONFIG_IXDP425 */ #endif /* CONFIG_PCI */ diff --git a/drivers/rtl8029.c b/drivers/rtl8029.c new file mode 100644 index 0000000..b883f3d --- /dev/null +++ b/drivers/rtl8029.c @@ -0,0 +1,356 @@ +/* + * Realtek 8029AS Ethernet + * (C) Copyright 2002-2003 + * Xue Ligong(lgxue@hotmail.com),Wang Kehao, ESLAB, whut.edu.cn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This code works in 8bit mode. + * If you need to work in 16bit mode, PLS change it! + */ + +#include +#include +#include +#include "rtl8029.h" +#include +#include "pci.h" + +#ifdef CONFIG_DRIVER_RTL8029 + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +struct eth_device *rtl8029_dev; + +/* packet page register access functions */ + + +static unsigned char get_reg (unsigned int regno) +{ + return (*(volatile unsigned char *) regno); +} + + +static void put_reg (unsigned int regno, unsigned char val) +{ + *(volatile unsigned char *) regno = val; +} + +static void eth_reset (void) +{ + unsigned char ucTemp; + + /* reset NIC */ + ucTemp = get_reg (RTL8029_RESET); + put_reg (RTL8029_RESET, ucTemp); + put_reg (RTL8029_INTERRUPTSTATUS, 0xff); + udelay (2000); /* wait for 2ms */ +} + +void rtl8029_get_enetaddr (uchar * addr) +{ + unsigned char i; + unsigned char temp; + + eth_reset (); + + put_reg (RTL8029_COMMAND, RTL8029_REMOTEDMARD); + put_reg (RTL8029_DATACONFIGURATION, 0x48); + put_reg (RTL8029_REMOTESTARTADDRESS0, 0x00); + put_reg (RTL8029_REMOTESTARTADDRESS1, 0x00); + put_reg (RTL8029_REMOTEBYTECOUNT0, 12); + put_reg (RTL8029_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8029_COMMAND, RTL8029_REMOTEDMARD); + printf ("MAC: "); + for (i = 0; i < 6; i++) { + temp = get_reg (RTL8029_DMA_DATA); + *addr++ = temp; + temp = get_reg (RTL8029_DMA_DATA); + printf ("%x:", temp); + } + + while ((!get_reg (RTL8029_INTERRUPTSTATUS) & 0x40)); + printf ("\b \n"); + put_reg (RTL8029_REMOTEBYTECOUNT0, 0x00); + put_reg (RTL8029_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8029_COMMAND, RTL8029_PAGE0); +} + + +void rtl8029_eth_halt (struct eth_device *dev) +{ + put_reg (RTL8029_COMMAND, 0x01); +} + +int rtl8029_eth_init (struct eth_device *dev,bd_t * bd) +{ + uchar *mac = (uchar *)dev->enetaddr; + + rtl8029_get_enetaddr(mac); + + eth_reset (); + put_reg (RTL8029_COMMAND, RTL8029_PAGE0STOP); + put_reg (RTL8029_DATACONFIGURATION, 0x48); + put_reg (RTL8029_REMOTEBYTECOUNT0, 0x00); + put_reg (RTL8029_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8029_RECEIVECONFIGURATION, 0x00); /*00; */ + put_reg (RTL8029_TRANSMITPAGE, RTL8029_TPSTART); + put_reg (RTL8029_TRANSMITCONFIGURATION, 0x02); + put_reg (RTL8029_PAGESTART, RTL8029_PSTART); + put_reg (RTL8029_BOUNDARY, RTL8029_PSTART); + put_reg (RTL8029_PAGESTOP, RTL8029_PSTOP); + put_reg (RTL8029_INTERRUPTSTATUS, 0xff); + put_reg (RTL8029_INTERRUPTMASK, 0x11); /*b; */ + put_reg (RTL8029_COMMAND, RTL8029_PAGE1STOP); + put_reg (RTL8029_PHYSICALADDRESS0, dev->enetaddr[0]); + put_reg (RTL8029_PHYSICALADDRESS1, dev->enetaddr[1]); + put_reg (RTL8029_PHYSICALADDRESS2, dev->enetaddr[2]); + put_reg (RTL8029_PHYSICALADDRESS3, dev->enetaddr[3]); + put_reg (RTL8029_PHYSICALADDRESS4, dev->enetaddr[4]); + put_reg (RTL8029_PHYSICALADDRESS5, dev->enetaddr[5]); + put_reg (RTL8029_MULTIADDRESS0, 0x00); + put_reg (RTL8029_MULTIADDRESS1, 0x00); + put_reg (RTL8029_MULTIADDRESS2, 0x00); + put_reg (RTL8029_MULTIADDRESS3, 0x00); + put_reg (RTL8029_MULTIADDRESS4, 0x00); + put_reg (RTL8029_MULTIADDRESS5, 0x00); + put_reg (RTL8029_MULTIADDRESS6, 0x00); + put_reg (RTL8029_MULTIADDRESS7, 0x00); + put_reg (RTL8029_CURRENT, RTL8029_PSTART); + put_reg (RTL8029_COMMAND, RTL8029_PAGE0); + put_reg (RTL8029_TRANSMITCONFIGURATION, 0xe0); /*58; */ + + + + return 1; +} + + +static unsigned char nic_to_pc (void) +{ + unsigned char rec_head_status; + unsigned char next_packet_pointer; + unsigned char packet_length0; + unsigned char packet_length1; + unsigned short rxlen = 0; + unsigned int i = 4; + unsigned char current_point; + unsigned char *addr; + + /* + * The RTL8029's first 4B is packet status,page of next packet + * and packet length(2B).So we receive the fist 4B. + */ + put_reg (RTL8029_REMOTESTARTADDRESS1, get_reg (RTL8029_BOUNDARY)); + put_reg (RTL8029_REMOTESTARTADDRESS0, 0x00); + put_reg (RTL8029_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8029_REMOTEBYTECOUNT0, 0x04); + + + + put_reg (RTL8029_COMMAND, RTL8029_REMOTEDMARD); + + rec_head_status = get_reg (RTL8029_DMA_DATA); + next_packet_pointer = get_reg (RTL8029_DMA_DATA); + packet_length0 = get_reg (RTL8029_DMA_DATA); + packet_length1 = get_reg (RTL8029_DMA_DATA); + + put_reg (RTL8029_COMMAND, RTL8029_PAGE0); + /*Packet length is in two 8bit registers */ + rxlen = packet_length1; + rxlen = (((rxlen << 8) & 0xff00) + packet_length0); + rxlen -= 4; + + + if (rxlen > PKTSIZE_ALIGN + PKTALIGN) + printf ("packet too big!\n"); + + /*Receive the packet */ + put_reg (RTL8029_REMOTESTARTADDRESS0, 0x04); + put_reg (RTL8029_REMOTESTARTADDRESS1, get_reg (RTL8029_BOUNDARY)); + + put_reg (RTL8029_REMOTEBYTECOUNT0, (rxlen & 0xff)); + put_reg (RTL8029_REMOTEBYTECOUNT1, ((rxlen >> 8) & 0xff)); + + + put_reg (RTL8029_COMMAND, RTL8029_REMOTEDMARD); + + for (addr = (unsigned char *) NetRxPackets[0], i = rxlen; i > 0; i--) + { + + *addr++ = get_reg (RTL8029_DMA_DATA); + } + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], rxlen); + + while (!(get_reg (RTL8029_INTERRUPTSTATUS)) & 0x40); /* wait for the op. */ + + /* + * To test whether the packets are all received,get the + * location of current point + */ + put_reg (RTL8029_COMMAND, RTL8029_PAGE1); + current_point = get_reg (RTL8029_CURRENT); + put_reg (RTL8029_COMMAND, RTL8029_PAGE0); + put_reg (RTL8029_BOUNDARY, next_packet_pointer); + return current_point; +} + +/* Get a data block via Ethernet */ +extern int rtl8029_eth_rx (struct eth_device *dev) +{ + unsigned char temp, current_point; + + put_reg (RTL8029_COMMAND, RTL8029_PAGE0); + + + while (1) { + temp = get_reg (RTL8029_INTERRUPTSTATUS); + + + if (temp & 0x90) { + /*overflow */ + put_reg (RTL8029_COMMAND, RTL8029_PAGE0STOP); + udelay (2000); + put_reg (RTL8029_REMOTEBYTECOUNT0, 0); + put_reg (RTL8029_REMOTEBYTECOUNT1, 0); + put_reg (RTL8029_TRANSMITCONFIGURATION, 2); + do { + current_point = nic_to_pc (); + } while (get_reg (RTL8029_BOUNDARY) != current_point); + + put_reg (RTL8029_TRANSMITCONFIGURATION, 0xe0); + } + + if (temp & 0x1) { + udelay (10 * 1000); + + /*packet received */ + do { + put_reg (RTL8029_INTERRUPTSTATUS, 0x01); + current_point = nic_to_pc (); + } while (get_reg (RTL8029_BOUNDARY) != current_point); + } + + if (!(temp & 0x1)) + return 0; + + + + + /* done and exit. */ + } +} + +/* Send a data block via Ethernet. */ +extern int rtl8029_eth_send (struct eth_device *dev,volatile void *packet, int length) +{ + volatile unsigned char *p; + unsigned int pn; + + pn = length; + p = (volatile unsigned char *) packet; + + while (get_reg (RTL8029_COMMAND) == RTL8029_TRANSMIT); + + put_reg (RTL8029_REMOTESTARTADDRESS0, 0); + put_reg (RTL8029_REMOTESTARTADDRESS1, RTL8029_TPSTART); + put_reg (RTL8029_REMOTEBYTECOUNT0, (pn & 0xff)); + put_reg (RTL8029_REMOTEBYTECOUNT1, ((pn >> 8) & 0xff)); + + put_reg (RTL8029_COMMAND, RTL8029_REMOTEDMAWR); + while (pn > 0) { + put_reg (RTL8029_DMA_DATA, *p++); + pn--; + } + + pn = length; + + while (pn < 60) { /*Padding */ + put_reg (RTL8029_DMA_DATA, 0); + pn++; + } + + while (!(get_reg (RTL8029_INTERRUPTSTATUS)) & 0x40); + + put_reg (RTL8029_INTERRUPTSTATUS, 0x40); + put_reg (RTL8029_TRANSMITPAGE, RTL8029_TPSTART); + put_reg (RTL8029_TRANSMITBYTECOUNT0, (pn & 0xff)); + put_reg (RTL8029_TRANSMITBYTECOUNT1, ((pn >> 8 & 0xff))); + put_reg (RTL8029_COMMAND, RTL8029_TRANSMIT); + + udelay (10 * 1000); + + return 0; +} + + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8029}, + {} +}; + +int rtl8029_initialize(bd_t *bis) +{ + pci_dev_t devno; + int card_number = 0; + + u32 iobase; + int idx=0; + + while(1){ + /* Find RTL8029 */ + if ((devno = pci_find_devices(supported, idx++)) < 0) + break; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); + iobase &= ~0xf; + + + debug ("rtl8029: REALTEK RTL8029 @0x%x\n", iobase); + + rtl8029_dev = (struct eth_device *)malloc(sizeof *rtl8029_dev); + + sprintf (rtl8029_dev->name, "RTL8029#%d", card_number); + + rtl8029_dev->priv = (void *) devno; + rtl8029_dev->iobase = (int)iobase; + rtl8029_dev->init = rtl8029_eth_init; + rtl8029_dev->halt = rtl8029_eth_halt; + rtl8029_dev->send = rtl8029_eth_send; + rtl8029_dev->recv = rtl8029_eth_rx; + + eth_register (rtl8029_dev); + + card_number++; + + pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); + + udelay (10 * 1000); + } + + return card_number; +} + + +#endif /* COMMANDS & CFG_NET */ + +#endif /* CONFIG_DRIVER_RTL8029 */ diff --git a/drivers/rtl8029.h b/drivers/rtl8029.h new file mode 100644 index 0000000..93f3ef9 --- /dev/null +++ b/drivers/rtl8029.h @@ -0,0 +1,119 @@ +/* + * Realtek 8029AS Ethernet + * (C) Copyright 2002-2003 + * Xue Ligong(lgxue@hotmail.com),Wang Kehao, ESLAB, whut.edu.cn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This code works in 8bit mode. + * If you need to work in 16bit mode, PLS change it! + */ + +#include +#include + + +#ifdef CONFIG_DRIVER_RTL8029 + +#define RTL8029_BASE rtl8029_dev->iobase + +#define RTL8029_REG_00 (RTL8029_BASE + 0x00) +#define RTL8029_REG_01 (RTL8029_BASE + 0x01) +#define RTL8029_REG_02 (RTL8029_BASE + 0x02) +#define RTL8029_REG_03 (RTL8029_BASE + 0x03) +#define RTL8029_REG_04 (RTL8029_BASE + 0x04) +#define RTL8029_REG_05 (RTL8029_BASE + 0x05) +#define RTL8029_REG_06 (RTL8029_BASE + 0x06) +#define RTL8029_REG_07 (RTL8029_BASE + 0x07) +#define RTL8029_REG_08 (RTL8029_BASE + 0x08) +#define RTL8029_REG_09 (RTL8029_BASE + 0x09) +#define RTL8029_REG_0a (RTL8029_BASE + 0x0a) +#define RTL8029_REG_0b (RTL8029_BASE + 0x0b) +#define RTL8029_REG_0c (RTL8029_BASE + 0x0c) +#define RTL8029_REG_0d (RTL8029_BASE + 0x0d) +#define RTL8029_REG_0e (RTL8029_BASE + 0x0e) +#define RTL8029_REG_0f (RTL8029_BASE + 0x0f) +#define RTL8029_REG_10 (RTL8029_BASE + 0x10) +#define RTL8029_REG_1f (RTL8029_BASE + 0x1f) + +#define RTL8029_COMMAND RTL8029_REG_00 +#define RTL8029_PAGESTART RTL8029_REG_01 +#define RTL8029_PAGESTOP RTL8029_REG_02 +#define RTL8029_BOUNDARY RTL8029_REG_03 +#define RTL8029_TRANSMITSTATUS RTL8029_REG_04 +#define RTL8029_TRANSMITPAGE RTL8029_REG_04 +#define RTL8029_TRANSMITBYTECOUNT0 RTL8029_REG_05 +#define RTL8029_NCR RTL8029_REG_05 +#define RTL8029_TRANSMITBYTECOUNT1 RTL8029_REG_06 +#define RTL8029_INTERRUPTSTATUS RTL8029_REG_07 +#define RTL8029_CURRENT RTL8029_REG_07 +#define RTL8029_REMOTESTARTADDRESS0 RTL8029_REG_08 +#define RTL8029_CRDMA0 RTL8029_REG_08 +#define RTL8029_REMOTESTARTADDRESS1 RTL8029_REG_09 +#define RTL8029_CRDMA1 RTL8029_REG_09 +#define RTL8029_REMOTEBYTECOUNT0 RTL8029_REG_0a +#define RTL8029_REMOTEBYTECOUNT1 RTL8029_REG_0b +#define RTL8029_RECEIVESTATUS RTL8029_REG_0c +#define RTL8029_RECEIVECONFIGURATION RTL8029_REG_0c +#define RTL8029_TRANSMITCONFIGURATION RTL8029_REG_0d +#define RTL8029_FAE_TALLY RTL8029_REG_0d +#define RTL8029_DATACONFIGURATION RTL8029_REG_0e +#define RTL8029_CRC_TALLY RTL8029_REG_0e +#define RTL8029_INTERRUPTMASK RTL8029_REG_0f +#define RTL8029_MISS_PKT_TALLY RTL8029_REG_0f +#define RTL8029_PHYSICALADDRESS0 RTL8029_REG_01 +#define RTL8029_PHYSICALADDRESS1 RTL8029_REG_02 +#define RTL8029_PHYSICALADDRESS2 RTL8029_REG_03 +#define RTL8029_PHYSICALADDRESS3 RTL8029_REG_04 +#define RTL8029_PHYSICALADDRESS4 RTL8029_REG_05 +#define RTL8029_PHYSICALADDRESS5 RTL8029_REG_06 +#define RTL8029_MULTIADDRESS0 RTL8029_REG_08 +#define RTL8029_MULTIADDRESS1 RTL8029_REG_09 +#define RTL8029_MULTIADDRESS2 RTL8029_REG_0a +#define RTL8029_MULTIADDRESS3 RTL8029_REG_0b +#define RTL8029_MULTIADDRESS4 RTL8029_REG_0c +#define RTL8029_MULTIADDRESS5 RTL8029_REG_0d +#define RTL8029_MULTIADDRESS6 RTL8029_REG_0e +#define RTL8029_MULTIADDRESS7 RTL8029_REG_0f +#define RTL8029_DMA_DATA RTL8029_REG_10 +#define RTL8029_RESET RTL8029_REG_1f + + +#define RTL8029_PAGE0 0x22 +#define RTL8029_PAGE1 0x62 +#define RTL8029_PAGE0DMAWRITE 0x12 +#define RTL8029_PAGE2DMAWRITE 0x92 +#define RTL8029_REMOTEDMAWR 0x12 +#define RTL8029_REMOTEDMARD 0x0A +#define RTL8029_ABORTDMAWR 0x32 +#define RTL8029_ABORTDMARD 0x2A +#define RTL8029_PAGE0STOP 0x21 +#define RTL8029_PAGE1STOP 0x61 +#define RTL8029_TRANSMIT 0x26 +#define RTL8029_TXINPROGRESS 0x04 +#define RTL8029_SEND 0x1A + +#define RTL8029_PSTART 0x4c +#define RTL8029_PSTOP 0x80 +#define RTL8029_TPSTART 0x40 + + +#endif /*end of CONFIG_DRIVER_RTL8029*/ diff --git a/drivers/sk98lin/.depend b/drivers/sk98lin/.depend new file mode 100644 index 0000000..d3cf1e2 --- /dev/null +++ b/drivers/sk98lin/.depend @@ -0,0 +1,113 @@ +uboot_drv.o: uboot_drv.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +uboot_skb.o: uboot_skb.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +sky2.o: sky2.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +skge.o: skge.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +sky2le.o: sky2le.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +skdim.o: skdim.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +skaddr.o: skaddr.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +skgehwt.o: skgehwt.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +skgeinit.o: skgeinit.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +skgesirq.o: skgesirq.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +sktwsi.o: sktwsi.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +sklm80.o: sklm80.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +skqueue.o: skqueue.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +skrlmt.o: skrlmt.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +sktimer.o: sktimer.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +skvpd.o: skvpd.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +skxmac2.o: skxmac2.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +skcsum.o: skcsum.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h diff --git a/drivers/sk98lin/Makefile b/drivers/sk98lin/Makefile index 8ee0e21..a125998 100644 --- a/drivers/sk98lin/Makefile +++ b/drivers/sk98lin/Makefile @@ -1,38 +1,82 @@ +#****************************************************************************** # -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Name: skge.c +# Project: GEnesis, PCI Gigabit Ethernet Adapter +# Version: $Revision: 1.9 $ +# Date: $Date: 2004/07/13 15:54:50 $ +# Purpose: The main driver source module # -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# File: drivers/sk98lin/Makefile -# -# Makefile for the SysKonnect SK-98xx device driver. -# -include $(TOPDIR)/config.mk +#****************************************************************************** +#****************************************************************************** +# +# (C)Copyright 1998-2002 SysKonnect GmbH. +# (C)Copyright 2002-2004 Marvell. +# +# Makefile for Marvell Yukon chipset and SysKonnect Gigabit Ethernet +# Server Adapter driver. (Kernel 2.4) +# +# Author: Mirko Lindner (mlindner@syskonnect.de) +# Ralph Roesler (rroesler@syskonnect.de) +# +# Address all question to: linux@syskonnect.de +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# The information in this file is provided "AS IS" without warranty. +# +#****************************************************************************** + +#****************************************************************************** +# +# History: +# +# $Log: Makefile2.4,v $ +# Revision 1.9 2004/07/13 15:54:50 rroesler +# Add: file skethtool.c +# Fix: corrected header regarding copyright +# Fix: minor typos corrected +# +# Revision 1.8 2004/06/08 08:40:36 mlindner +# Fix: Add CONFIG_SK98LIN_ZEROCOPY as default value +# +# Revision 1.7 2004/06/03 16:06:56 mlindner +# Fix: Added compile flag SK_DIAG_SUPPORT +# +# Revision 1.6 2004/06/02 08:02:59 mlindner +# Add: Changed header information and inserted a GPL statement +# +# +#****************************************************************************** + + +include $(TOPDIR)/config.mk + LIB := libsk98lin.a -OBJS := skge.o skaddr.o skgehwt.o skgeinit.o skgepnmi.o skgesirq.o \ - ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \ - skxmac2.o skcsum.o #skproc.o - -OBJS += uboot_skb.o uboot_drv.o +OBJS := \ + uboot_drv.o \ + uboot_skb.o \ + sky2.o \ + skge.o \ + sky2le.o \ + skdim.o \ + skaddr.o \ + skgehwt.o \ + skgeinit.o \ + skgesirq.o \ + sktwsi.o \ + sklm80.o \ + skqueue.o \ + skrlmt.o \ + sktimer.o \ + skvpd.o \ + skxmac2.o \ + skcsum.o \ +# skgepnmi.o # DBGDEF = \ # -DDEBUG @@ -81,21 +125,24 @@ endif # SK_DBGCAT_DRV_INT_SRC 0x04000000 interrupts sources # SK_DBGCAT_DRV_EVENT 0x08000000 driver events -EXTRA_CFLAGS += -I. -DSK_USE_CSUM $(DBGDEF) +#EXTRA_CFLAGS += -I. -DYUK2 -DYUKON -DGENESIS #-DSK_DIAG_SUPPORT $(DBGDEF) $(SKPARAM) +EXTRA_CFLAGS += -I. -DYUK2 -DYUKON #-DGENESIS -DSK_DIAG_SUPPORT $(DBGDEF) $(SKPARAM) CFLAGS += $(EXTRA_CFLAGS) - - -all: $(LIB) - -$(LIB): $(OBJS) + + +all: $(LIB) + +$(LIB): $(OBJS) $(AR) crv $@ $(OBJS) - + ######################################################################### - -.depend: Makefile $(OBJS:.o=.c) + +.depend: Makefile $(OBJS:.o=.c) $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - + sinclude .depend - + ######################################################################### + + diff --git a/drivers/sk98lin/h/lm80.h b/drivers/sk98lin/h/lm80.h index 981a4ca..d75e75b 100644 --- a/drivers/sk98lin/h/lm80.h +++ b/drivers/sk98lin/h/lm80.h @@ -1,9 +1,9 @@ /****************************************************************************** * - * Name: lm80.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.4 $ - * Date: $Date: 2002/04/25 11:04:10 $ + * Name: lm80.h + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 2.2 $ + * Date: $Date: 2005/12/14 16:11:35 $ * Purpose: Contains all defines for the LM80 Chip * (National Semiconductor). * @@ -11,7 +11,9 @@ /****************************************************************************** * - * (C)Copyright 1998-2002 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,25 +21,7 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * $Log: lm80.h,v $ - * Revision 1.4 2002/04/25 11:04:10 rschmidt - * Editorial changes - * - * Revision 1.3 1999/11/22 13:41:19 cgoos - * Changed license header to GPL. - * - * Revision 1.2 1999/03/12 13:26:51 malthoff - * remove __STDC__. - * - * Revision 1.1 1998/06/19 09:28:31 malthoff - * created. - * + * /LICENSE * ******************************************************************************/ @@ -55,8 +39,8 @@ extern "C" { * * All registers are 8 bit wide */ -#define LM80_CFG 0x00 /* Configuration Register */ -#define LM80_ISRC_1 0x01 /* Interrupt Status Register 1 */ +#define LM80_CFG 0x00 /* Configuration Register */ +#define LM80_ISRC_1 0x01 /* Interrupt Status Register 1 */ #define LM80_ISRC_2 0x02 /* Interrupt Status Register 2 */ #define LM80_IMSK_1 0x03 /* Interrupt Mask Register 1 */ #define LM80_IMSK_2 0x04 /* Interrupt Mask Register 2 */ @@ -93,8 +77,8 @@ extern "C" { #define LM80_THOT_LIM_LO 0x39 /* hot temperature limit (low) */ #define LM80_TOS_LIM_UP 0x3a /* OS temperature limit (high) */ #define LM80_TOS_LIM_LO 0x3b /* OS temperature limit (low) */ -#define LM80_FAN1_COUNT_LIM 0x3c /* Fan 1 count limit (high) */ -#define LM80_FAN2_COUNT_LIM 0x3d /* Fan 2 count limit (low) */ +#define LM80_FAN1_COUNT_LIM 0x3c /* Fan 1 count limit (high) */ +#define LM80_FAN2_COUNT_LIM 0x3d /* Fan 2 count limit (low) */ /* 0x3e - 0x3f reserved */ /* @@ -124,7 +108,7 @@ extern "C" { /* LM80_ISRC_2 Interrupt Status Register 2 */ /* LM80_IMSK_2 Interrupt Mask Register 2 */ -#define LM80_IS_TEMP (1<<0) /* HOT temperature limit exceeded */ +#define LM80_IS_TEMP (1<<0) /* HOT temperature limit exceeded */ #define LM80_IS_BTI (1<<1) /* state of BTI# pin */ #define LM80_IS_FAN1 (1<<2) /* count limit exceeded for Fan 1 */ #define LM80_IS_FAN2 (1<<3) /* count limit exceeded for Fan 2 */ @@ -143,7 +127,7 @@ extern "C" { #define LM80_FAN_RST_ENA (1<<7) /* sets RST_OUT#/OS# pins in RST mode */ /* LM80_TEMP_CTRL OS# Config, Temp Res. Reg */ -#define LM80_TEMP_OS_STAT (1<<0) /* mirrors the state of RST_OUT#/OS# */ +#define LM80_TEMP_OS_STAT (1<<0) /* mirrors the state of RST_OUT#/OS# */ #define LM80_TEMP_OS_POL (1<<1) /* select OS# polarity */ #define LM80_TEMP_OS_MODE (1<<2) /* selects Interrupt mode */ #define LM80_TEMP_RES (1<<3) /* selects 9 or 11 bit temp resulution*/ diff --git a/drivers/sk98lin/h/skaddr.h b/drivers/sk98lin/h/skaddr.h index 711f873..1141782 100644 --- a/drivers/sk98lin/h/skaddr.h +++ b/drivers/sk98lin/h/skaddr.h @@ -1,16 +1,18 @@ /****************************************************************************** * * Name: skaddr.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.26 $ - * Date: $Date: 2002/11/15 07:24:42 $ + * Project: Gigabit Ethernet Adapters, ADDR-Modul + * Version: $Revision: 2.3 $ + * Date: $Date: 2005/12/21 08:55:06 $ * Purpose: Header file for Address Management (MC, UC, Prom). * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2001 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,102 +20,7 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: skaddr.h,v $ - * Revision 1.26 2002/11/15 07:24:42 tschilli - * SK_ADDR_EQUAL macro fixed. - * - * Revision 1.25 2002/06/10 13:55:18 tschilli - * Changes for handling YUKON. - * All changes are internally and not visible to the programmer - * using this module. - * - * Revision 1.24 2001/01/22 13:41:34 rassmann - * Supporting two nets on dual-port adapters. - * - * Revision 1.23 2000/08/10 11:27:50 rassmann - * Editorial changes. - * Preserving 32-bit alignment in structs for the adapter context. - * - * Revision 1.22 2000/08/07 11:10:40 rassmann - * Editorial changes. - * - * Revision 1.21 2000/05/04 09:39:59 rassmann - * Editorial changes. - * Corrected multicast address hashing. - * - * Revision 1.20 1999/11/22 13:46:14 cgoos - * Changed license header to GPL. - * Allowing overwrite for SK_ADDR_EQUAL. - * - * Revision 1.19 1999/05/28 10:56:07 rassmann - * Editorial changes. - * - * Revision 1.18 1999/04/06 17:22:04 rassmann - * Added private "ActivePort". - * - * Revision 1.17 1999/01/14 16:18:19 rassmann - * Corrected multicast initialization. - * - * Revision 1.16 1999/01/04 10:30:36 rassmann - * SkAddrOverride only possible after SK_INIT_IO phase. - * - * Revision 1.15 1998/12/29 13:13:11 rassmann - * An address override is now preserved in the SK_INIT_IO phase. - * All functions return an int now. - * Extended parameter checking. - * - * Revision 1.14 1998/11/24 12:39:45 rassmann - * Reserved multicast entry for BPDU address. - * 13 multicast entries left for protocol. - * - * Revision 1.13 1998/11/13 17:24:32 rassmann - * Changed return value of SkAddrOverride to int. - * - * Revision 1.12 1998/11/13 16:56:19 rassmann - * Added macro SK_ADDR_COMPARE. - * Changed return type of SkAddrOverride to SK_BOOL. - * - * Revision 1.11 1998/10/28 18:16:35 rassmann - * Avoiding I/Os before SK_INIT_RUN level. - * Aligning InexactFilter. - * - * Revision 1.10 1998/10/22 11:39:10 rassmann - * Corrected signed/unsigned mismatches. - * - * Revision 1.9 1998/10/15 15:15:49 rassmann - * Changed Flags Parameters from SK_U8 to int. - * Checked with lint. - * - * Revision 1.8 1998/09/24 19:15:12 rassmann - * Code cleanup. - * - * Revision 1.7 1998/09/18 20:22:13 rassmann - * Added HW access. - * - * Revision 1.6 1998/09/04 19:40:20 rassmann - * Interface enhancements. - * - * Revision 1.5 1998/09/04 12:40:57 rassmann - * Interface cleanup. - * - * Revision 1.4 1998/09/04 12:14:13 rassmann - * Interface cleanup. - * - * Revision 1.3 1998/09/02 16:56:40 rassmann - * Updated interface. - * - * Revision 1.2 1998/08/27 14:26:09 rassmann - * Updated interface. - * - * Revision 1.1 1998/08/21 08:31:08 rassmann - * First public version. + * /LICENSE * ******************************************************************************/ @@ -140,7 +47,6 @@ #define __INC_SKADDR_H #ifdef __cplusplus -#error C++ is not yet supported. extern "C" { #endif /* cplusplus */ @@ -206,7 +112,7 @@ extern "C" { /* Macros */ -#if 0 +#ifdef OLD_STUFF #ifndef SK_ADDR_EQUAL /* * "&" instead of "&&" allows better optimization on IA-64. @@ -231,16 +137,18 @@ extern "C" { #ifndef SK_ADDR_EQUAL #ifndef SK_ADDR_DWORD_COMPARE #define SK_ADDR_EQUAL(A1,A2) ( \ - (((SK_U8 *)(A1))[5] == ((SK_U8 *)(A2))[5]) & \ - (((SK_U8 *)(A1))[4] == ((SK_U8 *)(A2))[4]) & \ - (((SK_U8 *)(A1))[3] == ((SK_U8 *)(A2))[3]) & \ - (((SK_U8 *)(A1))[2] == ((SK_U8 *)(A2))[2]) & \ - (((SK_U8 *)(A1))[1] == ((SK_U8 *)(A2))[1]) & \ - (((SK_U8 *)(A1))[0] == ((SK_U8 *)(A2))[0])) + (((SK_U8 SK_FAR *)(A1))[5] == ((SK_U8 SK_FAR *)(A2))[5]) & \ + (((SK_U8 SK_FAR *)(A1))[4] == ((SK_U8 SK_FAR *)(A2))[4]) & \ + (((SK_U8 SK_FAR *)(A1))[3] == ((SK_U8 SK_FAR *)(A2))[3]) & \ + (((SK_U8 SK_FAR *)(A1))[2] == ((SK_U8 SK_FAR *)(A2))[2]) & \ + (((SK_U8 SK_FAR *)(A1))[1] == ((SK_U8 SK_FAR *)(A2))[1]) & \ + (((SK_U8 SK_FAR *)(A1))[0] == ((SK_U8 SK_FAR *)(A2))[0])) #else /* SK_ADDR_DWORD_COMPARE */ #define SK_ADDR_EQUAL(A1,A2) ( \ - (*(SK_U16 *)&(((SK_U8 *)(A1))[4]) == *(SK_U16 *)&(((SK_U8 *)(A2))[4])) && \ - (*(SK_U32 *)&(((SK_U8 *)(A1))[0]) == *(SK_U32 *)&(((SK_U8 *)(A2))[0]))) + (*(SK_U16 SK_FAR *)&(((SK_U8 SK_FAR *)(A1))[4]) == \ + *(SK_U16 SK_FAR *)&(((SK_U8 SK_FAR *)(A2))[4])) && \ + (*(SK_U32 SK_FAR *)&(((SK_U8 SK_FAR *)(A1))[0]) == \ + *(SK_U32 SK_FAR *)&(((SK_U8 SK_FAR *)(A2))[0]))) #endif /* SK_ADDR_DWORD_COMPARE */ #endif /* SK_ADDR_EQUAL */ @@ -356,6 +264,9 @@ extern int SkAddrXmacMcAdd( SK_MAC_ADDR *pMc, int Flags); +extern SK_U32 SkXmacMcHash( + unsigned char *pMc); + extern int SkAddrGmacMcAdd( SK_AC *pAC, SK_IOC IoC, @@ -363,6 +274,9 @@ extern int SkAddrGmacMcAdd( SK_MAC_ADDR *pMc, int Flags); +extern SK_U32 SkGmacMcHash( + unsigned char *pMc); + extern int SkAddrMcUpdate( SK_AC *pAC, SK_IOC IoC, @@ -382,7 +296,7 @@ extern int SkAddrOverride( SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber, - SK_MAC_ADDR *pNewAddr, + SK_MAC_ADDR SK_FAR *pNewAddr, int Flags); extern int SkAddrPromiscuousChange( @@ -401,13 +315,15 @@ extern int SkAddrGmacPromiscuousChange( SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber, - int NewPromMode); + int NewPromMode); +#ifndef SK_SLIM extern int SkAddrSwap( SK_AC *pAC, SK_IOC IoC, SK_U32 FromPortNumber, SK_U32 ToPortNumber); +#endif #else /* defined(SK_KR_PROTO)) */ diff --git a/drivers/sk98lin/h/skcsum.h b/drivers/sk98lin/h/skcsum.h index 2acae32..2a51603 100644 --- a/drivers/sk98lin/h/skcsum.h +++ b/drivers/sk98lin/h/skcsum.h @@ -2,14 +2,15 @@ * * Name: skcsum.h * Project: GEnesis - SysKonnect SK-NET Gigabit Ethernet (SK-98xx) - * Version: $Revision: 1.9 $ - * Date: $Date: 2001/02/06 11:21:39 $ + * Version: $Revision: 2.3 $ + * Date: $Date: 2005/12/14 16:11:27 $ * Purpose: Store/verify Internet checksum in send/receive packets. * ******************************************************************************/ /****************************************************************************** * + * LICENSE: * (C)Copyright 1998-2001 SysKonnect GmbH. * * This program is free software; you can redistribute it and/or modify @@ -18,48 +19,7 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: skcsum.h,v $ - * Revision 1.9 2001/02/06 11:21:39 rassmann - * Editorial changes. - * - * Revision 1.8 2001/02/06 11:15:36 rassmann - * Supporting two nets on dual-port adapters. - * - * Revision 1.7 2000/06/29 13:17:05 rassmann - * Corrected reception of a packet with UDP checksum == 0 (which means there - * is no UDP checksum). - * - * Revision 1.6 2000/02/28 12:33:44 cgoos - * Changed C++ style comments to C style. - * - * Revision 1.5 2000/02/21 12:10:05 cgoos - * Fixed license comment. - * - * Revision 1.4 2000/02/21 11:08:37 cgoos - * Merged changes back into common source. - * - * Revision 1.1 1999/07/26 14:47:49 mkarl - * changed from common source to windows specific source - * added return SKCS_STATUS_IP_CSUM_ERROR_UDP and - * SKCS_STATUS_IP_CSUM_ERROR_TCP to pass the NidsTester - * changes for Tx csum offload - * - * Revision 1.2 1998/09/04 12:16:34 mhaveman - * Checked in for Stephan to allow compilation. - * -Added definition SK_CSUM_EVENT_CLEAR_PROTO_STATS to clear statistic - * -Added prototype for SkCsEvent() - * - * Revision 1.1 1998/09/01 15:36:53 swolf - * initial revision - * - * 01-Sep-1998 sw Created. + * /LICENSE * ******************************************************************************/ @@ -130,7 +90,7 @@ * SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok). * SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok. * SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok. - * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum. + * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum. */ #ifndef SKCS_OVERWRITE_STATUS /* User overwrite? */ #define SKCS_STATUS int /* Define status type. */ @@ -199,9 +159,7 @@ typedef struct s_CsProtocolStatistics { typedef struct s_Csum { /* Enabled receive SK_PROTO_XXX bit flags. */ unsigned ReceiveFlags[SK_MAX_NETS]; -#ifdef TX_CSUM unsigned TransmitFlags[SK_MAX_NETS]; -#endif /* TX_CSUM */ /* The protocol statistics structure; one per supported protocol. */ SKCS_PROTO_STATS ProtoStats[SK_MAX_NETS][SKCS_NUM_PROTOCOLS]; @@ -226,11 +184,11 @@ typedef struct s_CsPacketInfo { /* function prototypes ********************************************************/ -#ifndef SkCsCalculateChecksum +#ifndef SK_CS_CALCULATE_CHECKSUM extern unsigned SkCsCalculateChecksum( void *pData, unsigned Length); -#endif +#endif /* SK_CS_CALCULATE_CHECKSUM */ extern int SkCsEvent( SK_AC *pAc, diff --git a/drivers/sk98lin/h/skdebug.h b/drivers/sk98lin/h/skdebug.h index cf5b5ad..1663f43 100644 --- a/drivers/sk98lin/h/skdebug.h +++ b/drivers/sk98lin/h/skdebug.h @@ -1,81 +1,38 @@ /****************************************************************************** * * Name: skdebug.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.12 $ - * Date: $Date: 2002/07/15 15:37:13 $ + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 2.4 $ + * Date: $Date: 2005/12/14 16:11:35 $ * Purpose: SK specific DEBUG support * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2002 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2005 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * $Log: skdebug.h,v $ - * Revision 1.12 2002/07/15 15:37:13 rschmidt - * Power Management support - * Editorial changes - * - * Revision 1.11 2002/04/25 11:04:39 rschmidt - * Editorial changes - * - * Revision 1.10 1999/11/22 13:47:40 cgoos - * Changed license header to GPL. - * - * Revision 1.9 1999/09/14 14:02:43 rwahl - * Added SK_DBGMOD_PECP. - * - * Revision 1.8 1998/11/25 08:31:54 gklug - * fix: no C++ comments allowed in common sources - * - * Revision 1.7 1998/11/24 16:47:24 swolf - * Driver may now define its own SK_DBG_MSG() (eg. in "h/skdrv1st.h"). - * - * Revision 1.6 1998/10/28 10:23:55 rassmann - * ADDED SK_DBGMOD_ADDR. - * - * Revision 1.5 1998/10/22 09:43:55 gklug - * add: CSUM module - * - * Revision 1.4 1998/10/01 07:54:44 gklug - * add: PNMI debug module - * - * Revision 1.3 1998/09/18 08:32:34 afischer - * Macros changed according ssr-spec.: - * SK_DBG_MODCHK -> SK_DBG_CHKMOD - * SK_DBG_CATCHK -> SK_DBG_CHKCAT - * - * Revision 1.2 1998/07/03 14:38:25 malthoff - * Add category SK_DBGCAT_FATAL. - * - * Revision 1.1 1998/06/19 13:39:01 malthoff - * created. - * + * /LICENSE * ******************************************************************************/ #ifndef __INC_SKDEBUG_H #define __INC_SKDEBUG_H +/* #define DEBUG */ #ifdef DEBUG #ifndef SK_DBG_MSG #define SK_DBG_MSG(pAC,comp,cat,arg) \ - if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \ - ((cat) & SK_DBG_CHKCAT(pAC)) ) { \ - SK_DBG_PRINTF arg ; \ + if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \ + ((cat) & SK_DBG_CHKCAT(pAC)) ) { \ + SK_DBG_PRINTF arg; \ } #endif #else @@ -103,6 +60,13 @@ #define SK_DBGMOD_ADDR 0x00000080L /* ADDR module */ #define SK_DBGMOD_PECP 0x00000100L /* PECP module */ #define SK_DBGMOD_POWM 0x00000200L /* Power Management module */ +#ifdef SK_ASF +#define SK_DBGMOD_ASF 0x00000400L /* ASF module */ +#endif +#ifdef SK_LBFO +#define SK_DBGMOD_LACP 0x00000800L /* link aggregation control protocol */ +#define SK_DBGMOD_FD 0x00001000L /* frame distributor (link aggregation) */ +#endif /* SK_LBFO */ /* Debug events */ diff --git a/drivers/sk98lin/h/skdrv1st.h b/drivers/sk98lin/h/skdrv1st.h index af34d7b..1a65f7f 100644 --- a/drivers/sk98lin/h/skdrv1st.h +++ b/drivers/sk98lin/h/skdrv1st.h @@ -2,15 +2,16 @@ * * Name: skdrv1st.h * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.11 $ - * Date: $Date: 2003/02/25 14:16:40 $ + * Version: $Revision: 1.5.2.6 $ + * Date: $Date: 2005/08/09 07:14:29 $ * Purpose: First header file for driver and all other modules * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2005 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,125 +22,51 @@ * ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: skdrv1st.h,v $ - * Revision 1.11 2003/02/25 14:16:40 mlindner - * Fix: Copyright statement - * - * Revision 1.10 2002/10/02 12:46:02 mlindner - * Add: Support for Yukon - * - * Revision 1.9.2.2 2001/12/07 12:06:42 mlindner - * Fix: malloc -> slab changes - * - * Revision 1.9.2.1 2001/03/12 16:50:59 mlindner - * chg: kernel 2.4 adaption - * - * Revision 1.9 2001/01/22 14:16:04 mlindner - * added ProcFs functionality - * Dual Net functionality integrated - * Rlmt networks added - * - * Revision 1.8 2000/02/21 12:19:18 cgoos - * Added default for SK_DEBUG_CHKMOD/_CHKCAT - * - * Revision 1.7 1999/11/22 13:50:00 cgoos - * Changed license header to GPL. - * Added overwrite for several functions. - * Removed linux 2.0.x definitions. - * Removed PCI vendor ID definition (now in kernel). - * - * Revision 1.6 1999/07/27 08:03:33 cgoos - * Changed SK_IN/OUT macros to readX/writeX instead of memory - * accesses (necessary for ALPHA). - * - * Revision 1.5 1999/07/23 12:10:21 cgoos - * Removed SK_RLMT_SLOW_LOOKAHEAD define. - * - * Revision 1.4 1999/07/14 12:31:13 cgoos - * Added SK_RLMT_SLOW_LOOKAHEAD define. - * - * Revision 1.3 1999/04/07 10:12:54 cgoos - * Added check for KERNEL and OPTIMIZATION defines. - * - * Revision 1.2 1999/03/01 08:51:47 cgoos - * Fixed pcibios_read/write definitions. - * - * Revision 1.1 1999/02/16 07:40:49 cgoos - * First version. - * - * - * - ******************************************************************************/ - -/****************************************************************************** - * - * Description: - * - * This is the first include file of the driver, which includes all - * neccessary system header files and some of the GEnesis header files. - * It also defines some basic items. - * - * Include File Hierarchy: - * - * see skge.c - * - ******************************************************************************/ - #ifndef __INC_SKDRV1ST_H #define __INC_SKDRV1ST_H -#if 0 +#if 0 /* uboot */ /* Check kernel version */ #include -#if (LINUX_VERSION_CODE > 0x020300) -#endif #endif typedef struct s_AC SK_AC; +/* Set card versions */ +#define SK_FAR + /* override some default functions with optimized linux functions */ #define SK_PNMI_STORE_U16(p,v) memcpy((char*)(p),(char*)&(v),2) #define SK_PNMI_STORE_U32(p,v) memcpy((char*)(p),(char*)&(v),4) #define SK_PNMI_STORE_U64(p,v) memcpy((char*)(p),(char*)&(v),8) #define SK_PNMI_READ_U16(p,v) memcpy((char*)&(v),(char*)(p),2) -#define SK_PNMI_READ_U32(p,v) memcpy((char*)&(v),(char*)(p),2) -#define SK_PNMI_READ_U64(p,v) memcpy((char*)&(v),(char*)(p),2) - -#define SkCsCalculateChecksum(p,l) ((~ip_compute_csum(p, l)) & 0xffff) +#define SK_PNMI_READ_U32(p,v) memcpy((char*)&(v),(char*)(p),4) +#define SK_PNMI_READ_U64(p,v) memcpy((char*)&(v),(char*)(p),8) #define SK_ADDR_EQUAL(a1,a2) (!memcmp(a1,a2,6)) +#define SK_STRNCMP(s1,s2,len) strncmp(s1,s2,len) +#define SK_STRCPY(dest,src) strcpy(dest,src) -#if !defined(__OPTIMIZE__) || !defined(__KERNEL__) -#warning You must compile this file with the correct options! -#warning See the last lines of the source file. -#error You must compile this driver with "-O". -#endif - -#if 0 -#include -#endif #include -#if 0 +#if 0 /* uboot */ #include #endif #include -#if 0 +#if 0 /* uboot */ #include #include #include #include #include #endif + #include #include #include -#if 0 + +#if 0 /* uboot */ #include #include #include @@ -149,6 +76,13 @@ typedef struct s_AC SK_AC; #include #endif +#define SK_CS_CALCULATE_CHECKSUM +#ifndef CONFIG_X86_64 +#define SkCsCalculateChecksum(p,l) ((~ip_compute_csum(p, l)) & 0xffff) +#else +#define SkCsCalculateChecksum(p,l) ((~ip_fast_csum(p, l)) & 0xffff) +#endif + #include "h/sktypes.h" #include "h/skerror.h" #include "h/skdebug.h" @@ -157,29 +91,30 @@ typedef struct s_AC SK_AC; #include "u-boot_compat.h" +#ifndef SK_BMU_RX_WM_PEX +#define SK_BMU_RX_WM_PEX 0x80 +#endif + #ifdef __LITTLE_ENDIAN #define SK_LITTLE_ENDIAN #else #define SK_BIG_ENDIAN +#define SK_USE_REV_DESC #endif -#if 0 +#if 0 /* uboot */ #define SK_NET_DEVICE net_device #else -#define SK_NET_DEVICE eth_device +#define SK_NET_DEVICE eth_device #endif /* we use gethrtime(), return unit: nanoseconds */ -#if 0 -#define SK_TICKS_PER_SEC HZ -#else -#define SK_TICKS_PER_SEC CFG_HZ -#endif +#define SK_TICKS_PER_SEC 100 #define SK_MEM_MAPPED_IO -/* #define SK_RLMT_SLOW_LOOKAHEAD */ +// #define SK_RLMT_SLOW_LOOKAHEAD #define SK_MAX_MACS 2 #define SK_MAX_NETS 2 @@ -199,9 +134,9 @@ typedef struct s_DrvRlmtMbuf SK_MBUF; #define SK_STRCMP(pStr1,pStr2) strcmp((char*)(pStr1),(char*)(pStr2)) /* macros to access the adapter */ -#define SK_OUT8(b,a,v) writeb((v), ((b)+(a))) -#define SK_OUT16(b,a,v) writew((v), ((b)+(a))) -#define SK_OUT32(b,a,v) writel((v), ((b)+(a))) +#define SK_OUT8(b,a,v) writeb((v), ((b)+(a))) +#define SK_OUT16(b,a,v) writew((v), ((b)+(a))) +#define SK_OUT32(b,a,v) writel((v), ((b)+(a))) #define SK_IN8(b,a,pv) (*(pv) = readb((b)+(a))) #define SK_IN16(b,a,pv) (*(pv) = readw((b)+(a))) #define SK_IN32(b,a,pv) (*(pv) = readl((b)+(a))) @@ -225,6 +160,7 @@ typedef struct s_DrvRlmtMbuf SK_MBUF; #define UINT32_C(a) __CONCAT__(a,UL) #define UINT64_C(a) __CONCAT__(a,ULL) +#define DEBUG #ifdef DEBUG #define SK_DBG_PRINTF printk #ifndef SK_DEBUG_CHKMOD @@ -262,3 +198,9 @@ extern void SkDbgPrintf(const char *format,...); extern void SkErrorLog(SK_AC*, int, int, char*); #endif + +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ diff --git a/drivers/sk98lin/h/skdrv2nd.h b/drivers/sk98lin/h/skdrv2nd.h index a311827..7ade8f7 100644 --- a/drivers/sk98lin/h/skdrv2nd.h +++ b/drivers/sk98lin/h/skdrv2nd.h @@ -1,16 +1,17 @@ /****************************************************************************** * - * Name: skdrv2nd.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.15 $ - * Date: $Date: 2003/02/25 14:16:40 $ - * Purpose: Second header file for driver and all other modules + * Name: skdrv2nd.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.29.2.28 $ + * Date: $Date: 2005/11/14 15:22:08 $ + * Purpose: Second header file for driver and all other modules * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2005 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,76 +22,6 @@ * ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: skdrv2nd.h,v $ - * Revision 1.15 2003/02/25 14:16:40 mlindner - * Fix: Copyright statement - * - * Revision 1.14 2003/02/25 13:26:26 mlindner - * Add: Support for various vendors - * - * Revision 1.13 2002/10/02 12:46:02 mlindner - * Add: Support for Yukon - * - * Revision 1.12.2.2 2001/09/05 12:14:50 mlindner - * add: New hardware revision int - * - * Revision 1.12.2.1 2001/03/12 16:50:59 mlindner - * chg: kernel 2.4 adaption - * - * Revision 1.12 2001/03/01 12:52:15 mlindner - * Fixed ring size - * - * Revision 1.11 2001/02/19 13:28:02 mlindner - * Changed PNMI parameter values - * - * Revision 1.10 2001/01/22 14:16:04 mlindner - * added ProcFs functionality - * Dual Net functionality integrated - * Rlmt networks added - * - * Revision 1.1 2000/10/05 19:46:50 phargrov - * Add directory src/vipk_devs_nonlbl/vipk_sk98lin/ - * This is the SysKonnect SK-98xx Gigabit Ethernet driver, - * contributed by SysKonnect. - * - * Revision 1.9 2000/02/21 10:39:55 cgoos - * Added flag for jumbo support usage. - * - * Revision 1.8 1999/11/22 13:50:44 cgoos - * Changed license header to GPL. - * Fixed two comments. - * - * Revision 1.7 1999/09/28 12:38:21 cgoos - * Added CheckQueue to SK_AC. - * - * Revision 1.6 1999/07/27 08:04:05 cgoos - * Added checksumming variables to SK_AC. - * - * Revision 1.5 1999/03/29 12:33:26 cgoos - * Rreversed to fine lock granularity. - * - * Revision 1.4 1999/03/15 12:14:02 cgoos - * Added DriverLock to SK_AC. - * Removed other locks. - * - * Revision 1.3 1999/03/01 08:52:27 cgoos - * Changed pAC->PciDev declaration. - * - * Revision 1.2 1999/02/18 10:57:14 cgoos - * Removed SkDrvTimeStamp prototype. - * Fixed SkGeOsGetTime prototype. - * - * Revision 1.1 1999/02/16 07:41:01 cgoos - * First version. - * - * - * - ******************************************************************************/ - /****************************************************************************** * * Description: @@ -111,10 +42,11 @@ #include "h/skqueue.h" #include "h/skgehwt.h" #include "h/sktimer.h" -#include "h/ski2c.h" +#include "h/sktwsi.h" #include "h/skgepnmi.h" #include "h/skvpd.h" #include "h/skgehw.h" +#include "h/sky2le.h" #include "h/skgeinit.h" #include "h/skaddr.h" #include "h/skgesirq.h" @@ -122,123 +54,198 @@ #include "h/skrlmt.h" #include "h/skgedrv.h" -#define SK_PCI_ISCOMPLIANT(result, pdev) { \ - result = SK_FALSE; /* default */ \ - /* 3Com (0x10b7) */ \ - if (pdev->vendor == 0x10b7) { \ - /* Gigabit Ethernet Adapter (0x1700) */ \ - if ((pdev->device == 0x1700)) { \ - result = SK_TRUE; \ - } \ - /* SysKonnect (0x1148) */ \ - } else if (pdev->vendor == 0x1148) { \ - /* SK-98xx Gigabit Ethernet Server Adapter (0x4300) */ \ - /* SK-98xx V2 Gigabit Ethernet Adapter (0x4320) */ \ - if ((pdev->device == 0x4300) || \ - (pdev->device == 0x4320)) { \ - result = SK_TRUE; \ - } \ - /* D-Link (0x1186) */ \ - } else if (pdev->vendor == 0x1186) { \ - /* Gigabit Ethernet Adapter (0x4c00) */ \ - if ((pdev->device == 0x4c00)) { \ - result = SK_TRUE; \ - } \ - /* CNet (0x1371) */ \ - } else if (pdev->vendor == 0x1371) { \ - /* GigaCard Network Adapter (0x434e) */ \ - if ((pdev->device == 0x434e)) { \ - result = SK_TRUE; \ - } \ - /* Linksys (0x1737) */ \ - } else if (pdev->vendor == 0x1737) { \ - /* Gigabit Network Adapter (0x1032) */ \ - /* Gigabit Network Adapter (0x1064) */ \ - if ((pdev->device == 0x1032) || \ - (pdev->device == 0x1064)) { \ - result = SK_TRUE; \ - } \ - } else { \ - result = SK_FALSE; \ - } \ -} +/* Defines for the poll cotroller */ +#define SK_NETDUMP_POLL + +#ifdef SK_NETDUMP_POLL +#ifdef HAVE_POLL_CONTROLLER +#define SK_POLL_CONTROLLER +#define CONFIG_SK98LIN_NAPI +#elif CONFIG_NET_POLL_CONTROLLER +#define SK_POLL_CONTROLLER +#define CONFIG_SK98LIN_NAPI +#endif +#endif -extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned); -extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*); -extern SK_U64 SkOsGetTime(SK_AC*); -extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*); -extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*); -extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*); -extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32); -extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16); -extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8); -extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA); - -struct s_DrvRlmtMbuf { - SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */ - SK_U8 *pData; /* Data buffer (virtually contig.). */ - unsigned Size; /* Data buffer size. */ - unsigned Length; /* Length of packet (<= Size). */ - SK_U32 PortIdx; /* Receiving/transmitting port. */ -#ifdef SK_RLMT_MBUF_PRIVATE - SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */ -#endif /* SK_RLMT_MBUF_PRIVATE */ - struct sk_buff *pOs; /* Pointer to message block */ -}; +/****************************************************************************** + * + * Generic driver defines + * + ******************************************************************************/ +#define USE_TIST_FOR_RESET /* Use timestamp for reset */ +#define Y2_RECOVERY /* use specific recovery yukon2 functions */ +#if 0 // u-boot +#define Y2_LE_CHECK /* activate check for LE order */ +#define Y2_SYNC_CHECK /* activate check for receiver in sync */ +#endif +#define SK_YUKON2 /* Enable Yukon2 dual net support */ +#define USE_SK_TX_CHECKSUM /* use the tx hw checksum driver functionality */ +#define USE_SK_RX_CHECKSUM /* use the rx hw checksum driver functionality */ +#define USE_SK_TSO_FEATURE /* use TCP segmentation offload if possible */ +#define SK_COPY_THRESHOLD 50 /* threshold for copying small RX frames; + * 0 avoids copying, 9001 copies all */ +#define SK_MAX_CARD_PARAM 16 /* number of adapters that can be configured via + * command line params */ +//#define USE_TX_COMPLETE /* use of a transmit complete interrupt */ +#define Y2_RX_CHECK /* RX Check timestamp */ /* - * ioctl definitions + * use those defines for a compile-in version of the driver instead + * of command line parameters */ -#define SK_IOCTL_BASE (SIOCDEVPRIVATE) -#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0) -#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1) -#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2) +// #define LINK_SPEED_A {"Auto",} +// #define LINK_SPEED_B {"Auto",} +// #define AUTO_NEG_A {"Sense",} +// #define AUTO_NEG_B {"Sense"} +// #define DUP_CAP_A {"Both",} +// #define DUP_CAP_B {"Both",} +// #define FLOW_CTRL_A {"SymOrRem",} +// #define FLOW_CTRL_B {"SymOrRem",} +// #define ROLE_A {"Auto",} +// #define ROLE_B {"Auto",} +// #define PREF_PORT {"A",} +// #define CON_TYPE {"Auto",} +// #define RLMT_MODE {"CheckLinkState",} -typedef struct s_IOCTL SK_GE_IOCTL; +#ifdef Y2_RECOVERY +#define CHECK_TRANSMIT_TIMEOUT +#define Y2_RESYNC_WATERMARK 1000000L +#endif + +/****************************************************************************** + * + * Generic ISR defines + * + ******************************************************************************/ + +#define SkIsrRetVar void +#define SkIsrRetNone NULL +#define SkIsrRetHandled NULL + +#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb) +#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb) +#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb) + +/****************************************************************************** + * + * Global function prototypes + * + ******************************************************************************/ + +extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned); +extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*); +extern SK_U64 SkOsGetTime(SK_AC*); +extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*); +extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*); +extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*); +extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32); +extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16); +extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8); +extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA); +extern int SkDrvEnterDiagMode(SK_AC *pAc); +extern int SkDrvLeaveDiagMode(SK_AC *pAc); + +/****************************************************************************** + * + * Linux specific RLMT buffer structure (SK_MBUF typedef in skdrv1st)! + * + ******************************************************************************/ + +struct s_DrvRlmtMbuf { + SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */ + SK_U8 *pData; /* Data buffer (virtually contig.). */ + unsigned Size; /* Data buffer size. */ + unsigned Length; /* Length of packet (<= Size). */ + SK_U32 PortIdx; /* Receiving/transmitting port. */ +#ifdef SK_RLMT_MBUF_PRIVATE + SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */ +#endif + struct sk_buff *pOs; /* Pointer to message block */ +}; + +/****************************************************************************** + * + * Linux specific TIME defines + * + ******************************************************************************/ + +#if SK_TICKS_PER_SEC == 100 +#define SK_PNMI_HUNDREDS_SEC(t) (t) +#else +#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t)*100)/(SK_TICKS_PER_SEC)) +#endif + +#define SkOsGetTimeCurrent(pAC, pUsec) {\ + static struct timeval prev_t; \ + struct timeval t;\ + do_gettimeofday(&t);\ + if (prev_t.tv_sec == t.tv_sec) { \ + if (prev_t.tv_usec > t.tv_usec) { \ + t.tv_usec = prev_t.tv_usec; \ + } else { \ + prev_t.tv_usec = t.tv_usec; \ + } \ + } else { \ + prev_t = t; \ + } \ + *pUsec = ((t.tv_sec*100L)+(t.tv_usec/10000));\ +} + +/****************************************************************************** + * + * Linux specific IOCTL defines and typedefs + * + ******************************************************************************/ + +#define SK_IOCTL_BASE (SIOCDEVPRIVATE) +#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0) +#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1) +#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2) +#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3) +#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4) + +typedef struct s_IOCTL SK_GE_IOCTL; struct s_IOCTL { char* pData; unsigned int Len; }; +/****************************************************************************** + * + * Generic sizes and length definitions + * + ******************************************************************************/ -/* - * define sizes of descriptor rings in bytes - */ - -#if 0 -#define TX_RING_SIZE (8*1024) -#define RX_RING_SIZE (24*1024) +#if 0 /* uboot */ +#define TX_RING_SIZE (24*1024) /* GEnesis/Yukon */ +#define RX_RING_SIZE (24*1024) /* GEnesis/Yukon */ #else -#define TX_RING_SIZE (10 * 40) -#define RX_RING_SIZE (10 * 40) +#define TX_RING_SIZE (10 * 40) +#define RX_RING_SIZE (10 * 40) #endif +#define RX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */ +#define TX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */ +#define MAXIMUM_LOW_ADDRESS 0xFFFFFFFF /* Max. low address */ -/* - * Buffer size for ethernet packets - */ -#define ETH_BUF_SIZE 1540 -#define ETH_MAX_MTU 1514 -#define ETH_MIN_MTU 60 -#define ETH_MULTICAST_BIT 0x01 -#define SK_JUMBO_MTU 9000 +#define ETH_BUF_SIZE 1560 /* multiples of 8 bytes */ +#define ETH_MAX_MTU 1514 +#define ETH_MIN_MTU 60 +#define ETH_MULTICAST_BIT 0x01 +#define SK_JUMBO_MTU 9000 -/* - * transmit priority selects the queue: LOW=asynchron, HIGH=synchron - */ -#define TX_PRIO_LOW 0 -#define TX_PRIO_HIGH 1 +#define TX_PRIO_LOW 0 /* asynchronous queue */ +#define TX_PRIO_HIGH 1 /* synchronous queue */ +#define DESCR_ALIGN 64 /* alignment of Rx/Tx descriptors */ -/* - * alignment of rx/tx descriptors - */ -#define DESCR_ALIGN 8 +/****************************************************************************** + * + * PNMI related definitions + * + ******************************************************************************/ -/* - * definitions for pnmi. TODO - */ #define SK_DRIVER_RESET(pAC, IoC) 0 #define SK_DRIVER_SENDEVENT(pAC, IoC) 0 #define SK_DRIVER_SELFTEST(pAC, IoC) 0 @@ -248,314 +255,665 @@ struct s_IOCTL { #define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0 -/* TX and RX descriptors *****************************************************/ +/****************************************************************************** + * + * Various offsets and sizes + * + ******************************************************************************/ + +#define SK_DRV_MODERATION_TIMER 1 /* id */ +#define SK_DRV_MODERATION_TIMER_LENGTH 1 /* 1 second */ + +#define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6 +#define C_LEN_ETHERMAC_HEADER_SRC_ADDR 6 +#define C_LEN_ETHERMAC_HEADER_LENTYPE 2 +#define C_LEN_ETHERMAC_HEADER ( (C_LEN_ETHERMAC_HEADER_DEST_ADDR) + \ + (C_LEN_ETHERMAC_HEADER_SRC_ADDR) + \ + (C_LEN_ETHERMAC_HEADER_LENTYPE) ) + +#define C_LEN_ETHERMTU_MINSIZE 46 +#define C_LEN_ETHERMTU_MAXSIZE_STD 1500 +#define C_LEN_ETHERMTU_MAXSIZE_JUMBO 9000 + +#define C_LEN_ETHERNET_MINSIZE ( (C_LEN_ETHERMAC_HEADER) + \ + (C_LEN_ETHERMTU_MINSIZE) ) + +#define C_OFFSET_IPHEADER C_LEN_ETHERMAC_HEADER +#define C_OFFSET_IPHEADER_IPPROTO 9 +#define C_OFFSET_TCPHEADER_TCPCS 16 +#define C_OFFSET_UDPHEADER_UDPCS 6 + +#define C_OFFSET_IPPROTO ( (C_LEN_ETHERMAC_HEADER) + \ + (C_OFFSET_IPHEADER_IPPROTO) ) + +#define C_PROTO_ID_UDP 17 /* refer to RFC 790 or Stevens' */ +#define C_PROTO_ID_TCP 6 /* TCP/IP illustrated for details */ + +/****************************************************************************** + * + * Tx and Rx descriptor definitions + * + ******************************************************************************/ typedef struct s_RxD RXD; /* the receive descriptor */ - struct s_RxD { - volatile SK_U32 RBControl; /* Receive Buffer Control */ - SK_U32 VNextRxd; /* Next receive descriptor,low dword */ - SK_U32 VDataLow; /* Receive buffer Addr, low dword */ - SK_U32 VDataHigh; /* Receive buffer Addr, high dword */ - SK_U32 FrameStat; /* Receive Frame Status word */ - SK_U32 TimeStamp; /* Time stamp from XMAC */ - SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */ - SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */ - RXD *pNextRxd; /* Pointer to next Rxd */ - struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ + volatile SK_U32 RBControl; /* Receive Buffer Control */ + SK_U32 VNextRxd; /* Next receive descriptor,low dword */ + SK_U32 VDataLow; /* Receive buffer Addr, low dword */ + SK_U32 VDataHigh; /* Receive buffer Addr, high dword */ + SK_U32 FrameStat; /* Receive Frame Status word */ + SK_U32 TimeStamp; /* Time stamp from XMAC */ + SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */ + SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */ + RXD *pNextRxd; /* Pointer to next Rxd */ + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ }; typedef struct s_TxD TXD; /* the transmit descriptor */ - struct s_TxD { - volatile SK_U32 TBControl; /* Transmit Buffer Control */ - SK_U32 VNextTxd; /* Next transmit descriptor,low dword */ - SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */ - SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */ - SK_U32 FrameStat; /* Transmit Frame Status Word */ - SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */ - SK_U16 TcpSumSt; /* TCP Sum Start */ - SK_U16 TcpSumWr; /* TCP Sum Write */ - SK_U32 TcpReserved; /* not used */ - TXD *pNextTxd; /* Pointer to next Txd */ - struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ + volatile SK_U32 TBControl; /* Transmit Buffer Control */ + SK_U32 VNextTxd; /* Next transmit descriptor,low dword */ + SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */ + SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */ + SK_U32 FrameStat; /* Transmit Frame Status Word */ + SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */ + SK_U16 TcpSumSt; /* TCP Sum Start */ + SK_U16 TcpSumWr; /* TCP Sum Write */ + SK_U32 TcpReserved; /* not used */ + TXD *pNextTxd; /* Pointer to next Txd */ + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ }; +/****************************************************************************** + * + * Generic Yukon-II defines + * + ******************************************************************************/ -/* definition of flags in descriptor control field */ -#define RX_CTRL_OWN_BMU UINT32_C(0x80000000) -#define RX_CTRL_STF UINT32_C(0x40000000) -#define RX_CTRL_EOF UINT32_C(0x20000000) -#define RX_CTRL_EOB_IRQ UINT32_C(0x10000000) -#define RX_CTRL_EOF_IRQ UINT32_C(0x08000000) -#define RX_CTRL_DEV_NULL UINT32_C(0x04000000) -#define RX_CTRL_STAT_VALID UINT32_C(0x02000000) -#define RX_CTRL_TIME_VALID UINT32_C(0x01000000) -#define RX_CTRL_CHECK_DEFAULT UINT32_C(0x00550000) -#define RX_CTRL_CHECK_CSUM UINT32_C(0x00560000) -#define RX_CTRL_LEN_MASK UINT32_C(0x0000FFFF) +#define LE_SIZE sizeof(SK_HWLE) +#if 1 /* uboot */ +#define MAX_SKB_FRAGS 10 +#endif +#define MAX_NUM_FRAGS (MAX_SKB_FRAGS + 1) +#define MIN_LEN_OF_LE_TAB 128 +#define MAX_LEN_OF_LE_TAB 4096 +#define MAX_UNUSED_RX_LE_WORKING 8 +#if 1 /* Marvell - uboot:this increases the RX packets to 128-120 = 8*/ +#ifdef MAX_FRAG_OVERHEAD +#undef MAX_FRAG_OVERHEAD +#define MAX_FRAG_OVERHEAD 120 +#endif +#endif +// as we have a maximum of 16 physical fragments, +// maximum 1 ADDR64 per physical fragment +// maximum 4 LEs for VLAN, Csum, LargeSend, Packet +#define MIN_LE_FREE_REQUIRED ((16*2) + 4) +#define IS_GMAC(pAc) (!pAc->GIni.GIGenesis) +#ifdef USE_SYNC_TX_QUEUE +#define TXS_MAX_LE 256 +#else /* !USE_SYNC_TX_QUEUE */ +#define TXS_MAX_LE 0 +#endif -#define TX_CTRL_OWN_BMU UINT32_C(0x80000000) -#define TX_CTRL_STF UINT32_C(0x40000000) -#define TX_CTRL_EOF UINT32_C(0x20000000) -#define TX_CTRL_EOB_IRQ UINT32_C(0x10000000) -#define TX_CTRL_EOF_IRQ UINT32_C(0x08000000) -#define TX_CTRL_ST_FWD UINT32_C(0x04000000) -#define TX_CTRL_DISAB_CRC UINT32_C(0x02000000) -#define TX_CTRL_SOFTWARE UINT32_C(0x01000000) -#define TX_CTRL_CHECK_DEFAULT UINT32_C(0x00550000) -#define TX_CTRL_CHECK_CSUM UINT32_C(0x00560000) -#define TX_CTRL_LEN_MASK UINT32_C(0x0000FFFF) +#define ETHER_MAC_HDR_LEN (6+6+2) // MAC SRC ADDR, MAC DST ADDR, TYPE +#define IP_HDR_LEN 20 +#define TCP_CSUM_OFFS 0x10 +#define UDP_CSUM_OFFS 0x06 +#define TXA_MAX_LE 256 +#if 0 /* Marvell - uboot : set the RX LE to 128 */ +#define RX_MAX_LE 256 +#else +#define RX_MAX_LE 128 +#endif +#define ST_MAX_LE (SK_MAX_MACS)*((3*RX_MAX_LE)+(TXA_MAX_LE)+(TXS_MAX_LE)) + +#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK)) +/* event for recovery from tx hang or rx out of sync */ +#define SK_DRV_RECOVER 17 +#endif +/****************************************************************************** + * + * Structures specific for Yukon-II + * + ******************************************************************************/ + +typedef struct s_frag SK_FRAG; +struct s_frag { + SK_FRAG *pNext; + char *pVirt; + SK_U64 pPhys; + unsigned int FragLen; +}; + +typedef struct s_packet SK_PACKET; +struct s_packet { + /* Common infos: */ + SK_PACKET *pNext; /* pointer for packet queues */ + unsigned int PacketLen; /* length of packet */ + unsigned int NumFrags; /* nbr of fragments (for Rx always 1) */ + SK_FRAG *pFrag; /* fragment list */ + SK_FRAG FragArray[MAX_NUM_FRAGS]; /* TX fragment array */ + unsigned int NextLE; /* next LE to use for the next packet */ + + /* Private infos: */ + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ +}; + +typedef struct s_queue SK_PKT_QUEUE; +struct s_queue { + SK_PACKET *pHead; + SK_PACKET *pTail; +#if 0 /* uboot */ + spinlock_t QueueLock; /* serialize packet accesses */ +#endif +}; + +/******************************************************************************* + * + * Macros specific for Yukon-II queues + * + ******************************************************************************/ + +#define IS_Q_EMPTY(pQueue) ((pQueue)->pHead != NULL) ? SK_FALSE : SK_TRUE +#define IS_Q_LOCKED(pQueue) spin_is_locked(&((pQueue)->QueueLock)) + +#define PLAIN_POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \ + if ((pQueue)->pHead != NULL) { \ + (pPacket) = (pQueue)->pHead; \ + (pQueue)->pHead = (pPacket)->pNext; \ + if ((pQueue)->pHead == NULL) { \ + (pQueue)->pTail = NULL; \ + } \ + (pPacket)->pNext = NULL; \ + } else { \ + (pPacket) = NULL; \ + } \ +} + +#define PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \ + if ((pQueue)->pHead != NULL) { \ + (pPacket)->pNext = (pQueue)->pHead; \ + } else { \ + (pPacket)->pNext = NULL; \ + (pQueue)->pTail = (pPacket); \ + } \ + (pQueue)->pHead = (pPacket); \ +} + +#define PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \ + (pPacket)->pNext = NULL; \ + if ((pQueue)->pTail != NULL) { \ + (pQueue)->pTail->pNext = (pPacket); \ + } else { \ + (pQueue)->pHead = (pPacket); \ + } \ + (pQueue)->pTail = (pPacket); \ +} + +#define PLAIN_PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \ + if ((pPktGrpStart) != NULL) { \ + if ((pQueue)->pTail != NULL) { \ + (pQueue)->pTail->pNext = (pPktGrpStart); \ + } else { \ + (pQueue)->pHead = (pPktGrpStart); \ + } \ + (pQueue)->pTail = (pPktGrpEnd); \ + } \ +} + +/* Required: 'Flags' */ +#define POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \ + spin_lock_irqsave(&((pQueue)->QueueLock), Flags); \ + if ((pQueue)->pHead != NULL) { \ + (pPacket) = (pQueue)->pHead; \ + (pQueue)->pHead = (pPacket)->pNext; \ + if ((pQueue)->pHead == NULL) { \ + (pQueue)->pTail = NULL; \ + } \ + (pPacket)->pNext = NULL; \ + } else { \ + (pPacket) = NULL; \ + } \ + spin_unlock_irqrestore(&((pQueue)->QueueLock), Flags); \ +} + +/* Required: 'Flags' */ +#define PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \ + spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \ + if ((pQueue)->pHead != NULL) { \ + (pPacket)->pNext = (pQueue)->pHead; \ + } else { \ + (pPacket)->pNext = NULL; \ + (pQueue)->pTail = (pPacket); \ + } \ + (pQueue)->pHead = (pPacket); \ + spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \ +} + +/* Required: 'Flags' */ +#define PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \ + (pPacket)->pNext = NULL; \ + spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \ + if ((pQueue)->pTail != NULL) { \ + (pQueue)->pTail->pNext = (pPacket); \ + } else { \ + (pQueue)->pHead = (pPacket); \ + } \ + (pQueue)->pTail = (pPacket); \ + spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \ +} + +/* Required: 'Flags' */ +#define PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \ + if ((pPktGrpStart) != NULL) { \ + spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \ + if ((pQueue)->pTail != NULL) { \ + (pQueue)->pTail->pNext = (pPktGrpStart); \ + } else { \ + (pQueue)->pHead = (pPktGrpStart); \ + } \ + (pQueue)->pTail = (pPktGrpEnd); \ + spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \ + } \ +} + +/* + *Check if the low address (32 bit) is near the 4G limit or over it. + * Set the high address to a wrong value. + * Doing so we force to write the ADDR64 LE. + */ +#define CHECK_LOW_ADDRESS( _HighAddress, _LowAddress , _Length) { \ + if ((~0-_LowAddress) <_Length) { \ + _HighAddress= MAXIMUM_LOW_ADDRESS; \ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, \ + ("High Address must be set for HW. LowAddr = %d Length = %d\n", \ + _LowAddress, _Length)); \ + } \ +} + +/******************************************************************************* + * + * Macros specific for Yukon-II queues (tist) + * + ******************************************************************************/ + +#ifdef USE_TIST_FOR_RESET +/* port is fully operational */ +#define SK_PSTATE_NOT_WAITING_FOR_TIST 0 +/* port in reset until any tist LE */ +#define SK_PSTATE_WAITING_FOR_ANY_TIST BIT_0 +/* port in reset until timer reaches pAC->MinTistLo */ +#define SK_PSTATE_WAITING_FOR_SPECIFIC_TIST BIT_1 +#define SK_PSTATE_PORT_SHIFT 4 +#define SK_PSTATE_PORT_MASK ((1 << SK_PSTATE_PORT_SHIFT) - 1) + +/* use this + Port to build OP_MOD_TXINDEX_NO_PORT_A|B */ +#define OP_MOD_TXINDEX 0x71 +/* opcode for a TX_INDEX LE in which Port A has to be ignored */ +#define OP_MOD_TXINDEX_NO_PORT_A 0x71 +/* opcode for a TX_INDEX LE in which Port B has to be ignored */ +#define OP_MOD_TXINDEX_NO_PORT_B 0x72 +/* opcode for LE to be ignored because port is still in reset */ +#define OP_MOD_LE 0x7F + +/* set tist wait mode Bit for port */ +#define SK_SET_WAIT_BIT_FOR_PORT(pAC, Bit, Port) \ + { \ + (pAC)->AdapterResetState |= ((Bit) << (SK_PSTATE_PORT_SHIFT * Port)); \ + } + +/* reset tist waiting for specified port */ +#define SK_CLR_STATE_FOR_PORT(pAC, Port) \ + { \ + (pAC)->AdapterResetState &= \ + ~(SK_PSTATE_PORT_MASK << (SK_PSTATE_PORT_SHIFT * Port)); \ + } + +/* return SK_TRUE when port is in reset waiting for tist */ +#define SK_PORT_WAITING_FOR_TIST(pAC, Port) \ + ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \ + SK_PSTATE_PORT_MASK) != SK_PSTATE_NOT_WAITING_FOR_TIST) + +/* return SK_TRUE when port is in reset waiting for any tist */ +#define SK_PORT_WAITING_FOR_ANY_TIST(pAC, Port) \ + ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \ + SK_PSTATE_WAITING_FOR_ANY_TIST) == SK_PSTATE_WAITING_FOR_ANY_TIST) + +/* return SK_TRUE when port is in reset waiting for a specific tist */ +#define SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, Port) \ + ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \ + SK_PSTATE_WAITING_FOR_SPECIFIC_TIST) == \ + SK_PSTATE_WAITING_FOR_SPECIFIC_TIST) + +/* return whether adapter is expecting a tist LE */ +#define SK_ADAPTER_WAITING_FOR_TIST(pAC) ((pAC)->AdapterResetState != 0) + +/* enable timestamp timer and force creation of tist LEs */ +#define Y2_ENABLE_TIST(IoC) \ + SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_START) + +/* disable timestamp timer and stop creation of tist LEs */ +#define Y2_DISABLE_TIST(IoC) \ + SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_STOP) + +/* get current value of timestamp timer */ +#define Y2_GET_TIST_LOW_VAL(IoC, pVal) \ + SK_IN32(IoC, GMAC_TI_ST_VAL, pVal) + +#endif -/* The offsets of registers in the TX and RX queue control io area ***********/ +/******************************************************************************* + * + * Used interrupt bits in the interrupts source register + * + ******************************************************************************/ -#define RX_Q_BUF_CTRL_CNT 0x00 -#define RX_Q_NEXT_DESCR_LOW 0x04 -#define RX_Q_BUF_ADDR_LOW 0x08 -#define RX_Q_BUF_ADDR_HIGH 0x0c -#define RX_Q_FRAME_STAT 0x10 -#define RX_Q_TIME_STAMP 0x14 -#define RX_Q_CSUM_1_2 0x18 -#define RX_Q_CSUM_START_1_2 0x1c -#define RX_Q_CUR_DESCR_LOW 0x20 -#define RX_Q_DESCR_HIGH 0x24 -#define RX_Q_CUR_ADDR_LOW 0x28 -#define RX_Q_CUR_ADDR_HIGH 0x2c -#define RX_Q_CUR_BYTE_CNT 0x30 -#define RX_Q_CTRL 0x34 -#define RX_Q_FLAG 0x38 -#define RX_Q_TEST1 0x3c -#define RX_Q_TEST2 0x40 -#define RX_Q_TEST3 0x44 +#define DRIVER_IRQS ((IS_IRQ_SW) | \ + (IS_R1_F) | (IS_R2_F) | \ + (IS_XS1_F) | (IS_XA1_F) | \ + (IS_XS2_F) | (IS_XA2_F)) -#define TX_Q_BUF_CTRL_CNT 0x00 -#define TX_Q_NEXT_DESCR_LOW 0x04 -#define TX_Q_BUF_ADDR_LOW 0x08 -#define TX_Q_BUF_ADDR_HIGH 0x0c -#define TX_Q_FRAME_STAT 0x10 -#define TX_Q_CSUM_START 0x14 -#define TX_Q_CSUM_START_POS 0x18 -#define TX_Q_RESERVED 0x1c -#define TX_Q_CUR_DESCR_LOW 0x20 -#define TX_Q_DESCR_HIGH 0x24 -#define TX_Q_CUR_ADDR_LOW 0x28 -#define TX_Q_CUR_ADDR_HIGH 0x2c -#define TX_Q_CUR_BYTE_CNT 0x30 -#define TX_Q_CTRL 0x34 -#define TX_Q_FLAG 0x38 -#define TX_Q_TEST1 0x3c -#define TX_Q_TEST2 0x40 -#define TX_Q_TEST3 0x44 +#define TX_COMPL_IRQS ((IS_XS1_B) | (IS_XS1_F) | \ + (IS_XA1_B) | (IS_XA1_F) | \ + (IS_XS2_B) | (IS_XS2_F) | \ + (IS_XA2_B) | (IS_XA2_F)) -/* definition of flags in the queue control field */ -#define RX_Q_CTRL_POLL_ON 0x00000080 -#define RX_Q_CTRL_POLL_OFF 0x00000040 -#define RX_Q_CTRL_STOP 0x00000020 -#define RX_Q_CTRL_START 0x00000010 -#define RX_Q_CTRL_CLR_I_PAR 0x00000008 -#define RX_Q_CTRL_CLR_I_EOB 0x00000004 -#define RX_Q_CTRL_CLR_I_EOF 0x00000002 -#define RX_Q_CTRL_CLR_I_ERR 0x00000001 +#define NAPI_DRV_IRQS ((IS_R1_F) | (IS_R2_F) | \ + (IS_XS1_F) | (IS_XA1_F)| \ + (IS_XS2_F) | (IS_XA2_F)) -#define TX_Q_CTRL_POLL_ON 0x00000080 -#define TX_Q_CTRL_POLL_OFF 0x00000040 -#define TX_Q_CTRL_STOP 0x00000020 -#define TX_Q_CTRL_START 0x00000010 -#define TX_Q_CTRL_CLR_I_EOB 0x00000004 -#define TX_Q_CTRL_CLR_I_EOF 0x00000002 -#define TX_Q_CTRL_CLR_I_ERR 0x00000001 +#define Y2_DRIVER_IRQS ((Y2_IS_STAT_BMU) | (Y2_IS_IRQ_SW) | (Y2_IS_POLL_CHK)) +#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \ + (IS_EXT_REG) |(IS_TIMINT) | \ + (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \ + (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \ + (IS_MAC1) |(IS_LNK_SYNC_M1)| \ + (IS_MAC2) |(IS_LNK_SYNC_M2)| \ + (IS_R1_C) |(IS_R2_C) | \ + (IS_XS1_C) |(IS_XA1_C) | \ + (IS_XS2_C) |(IS_XA2_C)) -/* Interrupt bits in the interrupts source register **************************/ -#define IRQ_HW_ERROR 0x80000000 -#define IRQ_RESERVED 0x40000000 -#define IRQ_PKT_TOUT_RX1 0x20000000 -#define IRQ_PKT_TOUT_RX2 0x10000000 -#define IRQ_PKT_TOUT_TX1 0x08000000 -#define IRQ_PKT_TOUT_TX2 0x04000000 -#define IRQ_I2C_READY 0x02000000 -#define IRQ_SW 0x01000000 -#define IRQ_EXTERNAL_REG 0x00800000 -#define IRQ_TIMER 0x00400000 -#define IRQ_MAC1 0x00200000 -#define IRQ_LINK_SYNC_C_M1 0x00100000 -#define IRQ_MAC2 0x00080000 -#define IRQ_LINK_SYNC_C_M2 0x00040000 -#define IRQ_EOB_RX1 0x00020000 -#define IRQ_EOF_RX1 0x00010000 -#define IRQ_CHK_RX1 0x00008000 -#define IRQ_EOB_RX2 0x00004000 -#define IRQ_EOF_RX2 0x00002000 -#define IRQ_CHK_RX2 0x00001000 -#define IRQ_EOB_SY_TX1 0x00000800 -#define IRQ_EOF_SY_TX1 0x00000400 -#define IRQ_CHK_SY_TX1 0x00000200 -#define IRQ_EOB_AS_TX1 0x00000100 -#define IRQ_EOF_AS_TX1 0x00000080 -#define IRQ_CHK_AS_TX1 0x00000040 -#define IRQ_EOB_SY_TX2 0x00000020 -#define IRQ_EOF_SY_TX2 0x00000010 -#define IRQ_CHK_SY_TX2 0x00000008 -#define IRQ_EOB_AS_TX2 0x00000004 -#define IRQ_EOF_AS_TX2 0x00000002 -#define IRQ_CHK_AS_TX2 0x00000001 +#define Y2_SPECIAL_IRQS ((Y2_IS_HW_ERR) |(Y2_IS_ASF) | \ + (Y2_IS_TWSI_RDY) |(Y2_IS_TIMINT) | \ + (Y2_IS_IRQ_PHY2) |(Y2_IS_IRQ_MAC2) | \ + (Y2_IS_CHK_RX2) |(Y2_IS_CHK_TXS2) | \ + (Y2_IS_CHK_TXA2) |(Y2_IS_IRQ_PHY1) | \ + (Y2_IS_IRQ_MAC1) |(Y2_IS_CHK_RX1) | \ + (Y2_IS_CHK_TXS1) |(Y2_IS_CHK_TXA1)) -#define DRIVER_IRQS (IRQ_SW | IRQ_EOF_RX1 | IRQ_EOF_RX2 | \ - IRQ_EOF_SY_TX1 | IRQ_EOF_AS_TX1 | \ - IRQ_EOF_SY_TX2 | IRQ_EOF_AS_TX2) +#define IRQ_MASK ((IS_IRQ_SW) | \ + (IS_R1_F) |(IS_R2_F) | \ + (IS_XS1_F) |(IS_XA1_F) | \ + (IS_XS2_F) |(IS_XA2_F) | \ + (IS_HW_ERR) |(IS_I2C_READY)| \ + (IS_EXT_REG) |(IS_TIMINT) | \ + (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \ + (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \ + (IS_MAC1) |(IS_MAC2) | \ + (IS_R1_C) |(IS_R2_C) | \ + (IS_XS1_C) |(IS_XA1_C) | \ + (IS_XS2_C) |(IS_XA2_C)) -#define SPECIAL_IRQS (IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \ - IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \ - IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \ - IRQ_MAC1 | IRQ_LINK_SYNC_C_M1 | \ - IRQ_MAC2 | IRQ_LINK_SYNC_C_M2 | \ - IRQ_CHK_RX1 | IRQ_CHK_RX2 | \ - IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \ - IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2) +#define Y2_IRQ_MASK ((Y2_DRIVER_IRQS) | (Y2_SPECIAL_IRQS)) -#define IRQ_MASK (IRQ_SW | IRQ_EOB_RX1 | IRQ_EOF_RX1 | \ - IRQ_EOB_RX2 | IRQ_EOF_RX2 | \ - IRQ_EOB_SY_TX1 | IRQ_EOF_SY_TX1 | \ - IRQ_EOB_AS_TX1 | IRQ_EOF_AS_TX1 | \ - IRQ_EOB_SY_TX2 | IRQ_EOF_SY_TX2 | \ - IRQ_EOB_AS_TX2 | IRQ_EOF_AS_TX2 | \ - IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \ - IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \ - IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \ - IRQ_MAC1 | \ - IRQ_MAC2 | \ - IRQ_CHK_RX1 | IRQ_CHK_RX2 | \ - IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \ - IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2) - -#define IRQ_HWE_MASK 0x00000FFF /* enable all HW irqs */ +#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */ +#define Y2_IRQ_HWE_MASK (Y2_HWE_ALL_MSK) /* enable all HW irqs */ typedef struct s_DevNet DEV_NET; struct s_DevNet { - int PortNr; - int NetNr; - int Mtu; - int Up; - SK_AC *pAC; -}; - -typedef struct s_TxPort TX_PORT; - -struct s_TxPort { - /* the transmit descriptor rings */ - caddr_t pTxDescrRing; /* descriptor area memory */ - SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */ - TXD *pTxdRingHead; /* Head of Tx rings */ - TXD *pTxdRingTail; /* Tail of Tx rings */ - TXD *pTxdRingPrev; /* descriptor sent previously */ - int TxdRingFree; /* # of free entrys */ -#if 0 - spinlock_t TxDesRingLock; /* serialize descriptor accesses */ + struct proc_dir_entry *proc; + int PortNr; + int NetNr; + int Mtu; + int Up; + char InitialDevName[20]; + SK_BOOL NetConsoleMode; +#ifdef Y2_RECOVERY +#if 0 // u-boot + struct timer_list KernelTimer; /* Kernel timer struct */ #endif - caddr_t HwAddr; /* bmu registers address */ - int PortIndex; /* index number of port (0 or 1) */ -}; - -typedef struct s_RxPort RX_PORT; - -struct s_RxPort { - /* the receive descriptor rings */ - caddr_t pRxDescrRing; /* descriptor area memory */ - SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */ - RXD *pRxdRingHead; /* Head of Rx rings */ - RXD *pRxdRingTail; /* Tail of Rx rings */ - RXD *pRxdRingPrev; /* descriptor given to BMU previously */ - int RxdRingFree; /* # of free entrys */ -#if 0 - spinlock_t RxDesRingLock; /* serialize descriptor accesses */ + int TransmitTimeoutTimer; /* Transmit timer */ + SK_BOOL TimerExpired; /* Transmit timer */ + SK_BOOL InRecover; /* Recover flag */ +#ifdef Y2_RX_CHECK + SK_U32 PreviousMACFifoRP; /* Backup of the FRP */ + SK_U32 PreviousMACFifoRLev; /* Backup of the FRL */ + SK_U32 PreviousRXFifoRP; /* Backup of the RX FRP */ + SK_U8 PreviousRXFifoRLev; /* Backup of the RX FRL */ + SK_U32 LastJiffies; /* Backup of the jiffies*/ #endif - int RxFillLimit; /* limit for buffers in ring */ - caddr_t HwAddr; /* bmu registers address */ - int PortIndex; /* index number of port (0 or 1) */ +#endif + SK_AC *pAC; +}; + +/******************************************************************************* + * + * Rx/Tx Port structures + * + ******************************************************************************/ + +typedef struct s_TxPort TX_PORT; +struct s_TxPort { /* the transmit descriptor rings */ + caddr_t pTxDescrRing; /* descriptor area memory */ + SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */ + TXD *pTxdRingHead; /* Head of Tx rings */ + TXD *pTxdRingTail; /* Tail of Tx rings */ + TXD *pTxdRingPrev; /* descriptor sent previously */ + int TxdRingPrevFree;/* previously # of free entrys */ + int TxdRingFree; /* # of free entrys */ +#if 0 /* uboot */ + spinlock_t TxDesRingLock; /* serialize descriptor accesses */ +#endif + caddr_t HwAddr; /* bmu registers address */ + int PortIndex; /* index number of port (0 or 1) */ + SK_PACKET *TransmitPacketTable; + SK_LE_TABLE TxALET; /* tx (async) list element table */ + SK_LE_TABLE TxSLET; /* tx (sync) list element table */ + SK_PKT_QUEUE TxQ_free; + SK_PKT_QUEUE TxAQ_waiting; + SK_PKT_QUEUE TxSQ_waiting; + SK_PKT_QUEUE TxAQ_working; + SK_PKT_QUEUE TxSQ_working; + unsigned LastDone; }; -typedef struct s_PerStrm PER_STRM; +typedef struct s_RxPort RX_PORT; +struct s_RxPort { /* the receive descriptor rings */ + caddr_t pRxDescrRing; /* descriptor area memory */ + SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */ + RXD *pRxdRingHead; /* Head of Rx rings */ + RXD *pRxdRingTail; /* Tail of Rx rings */ + RXD *pRxdRingPrev; /* descr given to BMU previously */ + int RxdRingFree; /* # of free entrys */ +#if 0 /* uboot */ + spinlock_t RxDesRingLock; /* serialize descriptor accesses */ +#endif + int RxFillLimit; /* limit for buffers in ring */ + caddr_t HwAddr; /* bmu registers address */ + int PortIndex; /* index number of port (0 or 1) */ + SK_BOOL UseRxCsum; /* use Rx checksumming (yes/no) */ + SK_PACKET *ReceivePacketTable; + SK_LE_TABLE RxLET; /* rx list element table */ + SK_PKT_QUEUE RxQ_working; + SK_PKT_QUEUE RxQ_waiting; + int RxBufSize; +}; + +/******************************************************************************* + * + * Interrupt masks used in combination with interrupt moderation + * + ******************************************************************************/ + +#define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F)) +#define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F)) +#define IRQ_MASK_TX_ONLY ((IRQ_EOF_AS_TX)| (IRQ_EOF_SY_TX)) +#define IRQ_MASK_RX_ONLY ((IS_R1_F) | (IS_R2_F)) +#define IRQ_MASK_SP_ONLY (SPECIAL_IRQS) +#define IRQ_MASK_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY)) +#define IRQ_MASK_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY)) +#define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY)) +#define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX)) + +#define IRQ_MASK_Y2_TX_ONLY (Y2_IS_STAT_BMU) +#define IRQ_MASK_Y2_RX_ONLY (Y2_IS_STAT_BMU) +#define IRQ_MASK_Y2_SP_ONLY (SPECIAL_IRQS) +#define IRQ_MASK_Y2_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY)) +#define IRQ_MASK_Y2_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY)) +#define IRQ_MASK_Y2_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY)) +#define IRQ_MASK_Y2_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX)) + +/******************************************************************************* + * + * Defines and typedefs regarding interrupt moderation + * + ******************************************************************************/ + +#define C_INT_MOD_NONE 1 +#define C_INT_MOD_STATIC 2 +#define C_INT_MOD_DYNAMIC 4 + +#define C_CLK_FREQ_GENESIS 53215000 /* or: 53.125 MHz */ +#define C_CLK_FREQ_YUKON 78215000 /* or: 78.125 MHz */ +#define C_CLK_FREQ_YUKON_EC 125000000 /* or: 125.000 MHz */ + +#define C_Y2_INTS_PER_SEC_DEFAULT 5000 +#define C_INTS_PER_SEC_DEFAULT 2000 +#define C_INT_MOD_IPS_LOWER_RANGE 30 /* in IRQs/second */ +#define C_INT_MOD_IPS_UPPER_RANGE 40000 /* in IRQs/second */ + +typedef struct s_DynIrqModInfo { + SK_U64 PrevPort0RxIntrCts; + SK_U64 PrevPort1RxIntrCts; + SK_U64 PrevPort0TxIntrCts; + SK_U64 PrevPort1TxIntrCts; + SK_U64 PrevPort0StatusLeIntrCts; + SK_U64 PrevPort1StatusLeIntrCts; + int MaxModIntsPerSec; /* Moderation Threshold */ + int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */ + int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */ + long MaskIrqModeration; /* IRQ Mask (eg. 'TxRx') */ + int IntModTypeSelect; /* Type (eg. 'dynamic') */ + int DynIrqModSampleInterval; /* expressed in seconds! */ + SK_TIMER ModTimer; /* Timer for dynamic mod. */ +} DIM_INFO; + +/******************************************************************************* + * + * Defines and typedefs regarding wake-on-lan + * + ******************************************************************************/ + +typedef struct s_WakeOnLanInfo { + SK_U32 SupportedWolOptions; /* e.g. WAKE_PHY... */ + SK_U32 ConfiguredWolOptions; /* e.g. WAKE_PHY... */ +} WOL_INFO; #define SK_ALLOC_IRQ 0x00000001 +#define DIAG_ACTIVE 1 +#define DIAG_NOTACTIVE 0 /**************************************************************************** + * * Per board structure / Adapter Context structure: - * Allocated within attach(9e) and freed within detach(9e). - * Contains all 'per device' necessary handles, flags, locks etc.: - */ + * Contains all 'per device' necessary handles, flags, locks etc.: + * + ******************************************************************************/ + struct s_AC { - SK_GEINIT GIni; /* GE init struct */ - SK_PNMI Pnmi; /* PNMI data struct */ - SK_VPD vpd; /* vpd data struct */ - SK_QUEUE Event; /* Event queue */ - SK_HWT Hwt; /* Hardware Timer control struct */ - SK_TIMCTRL Tim; /* Software Timer control struct */ - SK_I2C I2c; /* I2C relevant data structure */ - SK_ADDR Addr; /* for Address module */ - SK_CSUM Csum; /* for checksum module */ - SK_RLMT Rlmt; /* for rlmt module */ -#if 0 - spinlock_t SlowPathLock; /* Normal IRQ lock */ + SK_GEINIT GIni; /* GE init struct */ + SK_PNMI Pnmi; /* PNMI data struct */ + SK_VPD vpd; /* vpd data struct */ + SK_QUEUE Event; /* Event queue */ + SK_HWT Hwt; /* Hardware Timer ctrl struct */ + SK_TIMCTRL Tim; /* Software Timer ctrl struct */ + SK_I2C I2c; /* I2C relevant data structure*/ + SK_ADDR Addr; /* for Address module */ + SK_CSUM Csum; /* for checksum module */ + SK_RLMT Rlmt; /* for rlmt module */ +#if 0 /* uboot */ + spinlock_t SlowPathLock; /* Normal IRQ lock */ + spinlock_t InitLock; /* Init lock */ + spinlock_t TxQueueLock; /* TX Queue lock */ #endif - SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */ - int RlmtMode; /* link check mode to set */ - int RlmtNets; /* Number of nets */ - - SK_IOC IoBase; /* register set of adapter */ - int BoardLevel; /* level of active hw init (0-2) */ - char DeviceStr[80]; /* adapter string from vpd */ - SK_U32 AllocFlag; /* flag allocation of resources */ -#if 0 - struct pci_dev *PciDev; /* for access to pci config space */ - SK_U32 PciDevId; /* pci device id */ + SK_PNMI_STRUCT_DATA PnmiStruct; /* struct for all Pnmi-Data */ + int RlmtMode; /* link check mode to set */ + int RlmtNets; /* Number of nets */ + SK_IOC IoBase; /* register set of adapter */ + int BoardLevel; /* level of hw init (0-2) */ + char DeviceStr[80]; /* adapter string from vpd */ + SK_U32 AllocFlag; /* alloc flag of resources */ +#if 0 /* uboot */ + struct pci_dev *PciDev; /* for access to pci cfg space*/ + SK_U32 PciDevId; /* pci device id */ #else - int PciDev; + int PciDev; #endif - struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */ - char Name[30]; /* driver name */ - struct SK_NET_DEVICE *Next; /* link all devices (for clearing) */ - int RxBufSize; /* length of receive buffers */ -#if 0 - struct net_device_stats stats; /* linux 'netstat -i' statistics */ + struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */ + char Name[30]; /* driver name */ + struct SK_NET_DEVICE *Next; /* link all devs for cleanup */ + int RxBufSize; /* length of receive buffers */ +#if 0 /* uboot */ + struct net_device_stats stats; /* linux 'netstat -i' stats */ +#endif + int Index; /* internal board idx number */ + int RxQueueSize; /* memory used for RX queue */ + int TxSQueueSize; /* memory used for TXS queue */ + int TxAQueueSize; /* memory used for TXA queue */ + int PromiscCount; /* promiscuous mode counter */ + int AllMultiCount; /* allmulticast mode counter */ + int MulticCount; /* number of MC addresses used*/ + int HWRevision; /* Hardware revision */ + int ActivePort; /* the active XMAC port */ + int MaxPorts; /* number of activated ports */ + int TxDescrPerRing;/* # of descriptors TX ring */ + int RxDescrPerRing;/* # of descriptors RX ring */ + caddr_t pDescrMem; /* Ptr to the descriptor area */ + dma_addr_t pDescrMemDMA; /* PCI DMA address of area */ + SK_U32 PciState[16]; /* PCI state */ + TX_PORT TxPort[SK_MAX_MACS][2]; + RX_PORT RxPort[SK_MAX_MACS]; + SK_LE_TABLE StatusLETable; + unsigned SizeOfAlignedLETables; +#if 0 /* uboot */ + spinlock_t SetPutIndexLock; +#endif + int MaxUnusedRxLeWorking; + unsigned int CsOfs1; /* for checksum calculation */ + unsigned int CsOfs2; /* for checksum calculation */ + SK_U32 CsOfs; /* for checksum calculation */ + SK_BOOL CheckQueue; /* check event queue soon */ + DIM_INFO DynIrqModInfo; /* all data related to IntMod */ + WOL_INFO WolInfo; /* all info regarding WOL */ + int ChipsetType; /* 0=GENESIS; 1=Yukon */ + SK_BOOL LowLatency; /* LowLatency optimization on?*/ + SK_U32 DiagModeActive;/* is diag active? */ + SK_BOOL DiagFlowCtrl; /* for control purposes */ + SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for PNMI */ + SK_BOOL WasIfUp[SK_MAX_MACS]; +#ifdef USE_TIST_FOR_RESET + int AdapterResetState; + SK_U32 MinTistLo; + SK_U32 MinTistHi; +#endif +#ifdef Y2_RECOVERY + int LastPort; /* port for curr. handled rx */ + int LastOpc; /* last rx LEs opcode */ +#endif +#ifdef Y2_SYNC_CHECK + unsigned long FramesWithoutSyncCheck; /* since last check */ #endif - int Index; /* internal board index number */ - - /* adapter RAM sizes for queues of active port */ - int RxQueueSize; /* memory used for receive queue */ - int TxSQueueSize; /* memory used for sync. tx queue */ - int TxAQueueSize; /* memory used for async. tx queue */ - - int PromiscCount; /* promiscuous mode counter */ - int AllMultiCount; /* allmulticast mode counter */ - int MulticCount; /* number of different MC */ - /* addresses for this board */ - /* (may be more than HW can)*/ - - int HWRevision; /* Hardware revision */ - int ActivePort; /* the active XMAC port */ - int MaxPorts; /* number of activated ports */ - int TxDescrPerRing; /* # of descriptors per tx ring */ - int RxDescrPerRing; /* # of descriptors per rx ring */ - - caddr_t pDescrMem; /* Pointer to the descriptor area */ - dma_addr_t pDescrMemDMA; /* PCI DMA address of area */ - - /* the port structures with descriptor rings */ - TX_PORT TxPort[SK_MAX_MACS][2]; - RX_PORT RxPort[SK_MAX_MACS]; - - unsigned int CsOfs1; /* for checksum calculation */ - unsigned int CsOfs2; /* for checksum calculation */ - SK_U32 CsOfs; /* for checksum calculation */ - - SK_BOOL CheckQueue; /* check event queue soon */ - - /* Only for tests */ - int PortUp; - int PortDown; - }; -#endif /* __INC_SKDRV2ND_H */ + + +#endif + +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ diff --git a/drivers/sk98lin/h/skerror.h b/drivers/sk98lin/h/skerror.h index a454d9d..45d9bfa 100644 --- a/drivers/sk98lin/h/skerror.h +++ b/drivers/sk98lin/h/skerror.h @@ -1,49 +1,25 @@ /****************************************************************************** * * Name: skerror.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.5 $ - * Date: $Date: 2002/04/25 11:05:10 $ + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 2.3 $ + * Date: $Date: 2005/12/14 16:11:35 $ * Purpose: SK specific Error log support * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2002 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * $Log: skerror.h,v $ - * Revision 1.5 2002/04/25 11:05:10 rschmidt - * Editorial changes - * - * Revision 1.4 1999/11/22 13:51:59 cgoos - * Changed license header to GPL. - * - * Revision 1.3 1999/09/14 14:04:42 rwahl - * Added error base SK_ERRBASE_PECP. - * Changed error base for driver. - * - * Revision 1.2 1998/08/11 11:15:41 gklug - * chg: comments - * - * Revision 1.1 1998/08/11 11:09:38 gklug - * add: error bases - * add: error Classes - * first version - * - * + * /LICENSE * ******************************************************************************/ @@ -61,7 +37,6 @@ #define SK_ERRCL_HW (1L<<4) /* Hardware Failure */ #define SK_ERRCL_COMM (1L<<5) /* Communication error */ - /* * Define Error Code Bases */ @@ -74,7 +49,9 @@ #define SK_ERRBASE_I2C 700 /* Base Error number for I2C module */ #define SK_ERRBASE_QUEUE 800 /* Base Error number for Scheduler */ #define SK_ERRBASE_ADDR 900 /* Base Error number for Address module */ -#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */ +#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */ #define SK_ERRBASE_DRV 1100 /* Base Error number for Driver */ +#define SK_ERRBASE_ASF 1200 /* Base Error number for ASF */ #endif /* _INC_SKERROR_H_ */ + diff --git a/drivers/sk98lin/h/skgedrv.h b/drivers/sk98lin/h/skgedrv.h index 72ba9ce..331c900 100644 --- a/drivers/sk98lin/h/skgedrv.h +++ b/drivers/sk98lin/h/skgedrv.h @@ -1,50 +1,25 @@ /****************************************************************************** * * Name: skgedrv.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.6 $ - * Date: $Date: 2002/07/15 15:38:01 $ + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 2.4 $ + * Date: $Date: 2006/01/19 14:02:08 $ * Purpose: Interface with the driver * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2002 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2006 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: skgedrv.h,v $ - * Revision 1.6 2002/07/15 15:38:01 rschmidt - * Power Management support - * Editorial changes - * - * Revision 1.5 2002/04/25 11:05:47 rschmidt - * Editorial changes - * - * Revision 1.4 1999/11/22 13:52:46 cgoos - * Changed license header to GPL. - * - * Revision 1.3 1998/12/01 13:31:39 cgoos - * SWITCH INTERN Event added. - * - * Revision 1.2 1998/11/25 08:28:38 gklug - * rmv: PORT SWITCH Event - * - * Revision 1.1 1998/09/29 06:14:07 gklug - * add: driver events (initial version) - * + * /LICENSE * ******************************************************************************/ @@ -59,7 +34,7 @@ * In case of the driver we put the definition of the events here. */ #define SK_DRV_PORT_RESET 1 /* The port needs to be reset */ -#define SK_DRV_NET_UP 2 /* The net is operational */ +#define SK_DRV_NET_UP 2 /* The net is operational */ #define SK_DRV_NET_DOWN 3 /* The net is down */ #define SK_DRV_SWITCH_SOFT 4 /* Ports switch with both links connected */ #define SK_DRV_SWITCH_HARD 5 /* Port switch due to link failure */ @@ -68,5 +43,13 @@ #define SK_DRV_PORT_FAIL 8 /* One port fails */ #define SK_DRV_SWITCH_INTERN 9 /* Port switch by the driver itself */ #define SK_DRV_POWER_DOWN 10 /* Power down mode */ - -#endif /* __INC_SKGEDRV_H_ */ +#define SK_DRV_TIMER 11 /* Timer for free use */ +#ifdef SK_NO_RLMT +#define SK_DRV_LINK_UP 12 /* Link Up event for driver */ +#define SK_DRV_LINK_DOWN 13 /* Link Down event for driver */ +#endif +#define SK_DRV_DOWNSHIFT_DET 14 /* Downshift 4-Pair / 2-Pair (YUKON only) */ +#define SK_DRV_RX_OVERFLOW 15 /* Receive Overflow */ +#define SK_DRV_LIPA_NOT_AN_ABLE 16 /* Link Partner not Auto-Negotiation able */ +#define SK_DRV_PEX_LINK_WIDTH 17 /* PEX negotiated Link width not maximum */ +#endif /* __INC_SKGEDRV_H_ */ diff --git a/drivers/sk98lin/h/skgehw.h b/drivers/sk98lin/h/skgehw.h index 2c98427..de5bfa4 100644 --- a/drivers/sk98lin/h/skgehw.h +++ b/drivers/sk98lin/h/skgehw.h @@ -1,226 +1,25 @@ /****************************************************************************** * * Name: skgehw.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.49 $ - * Date: $Date: 2003/01/28 09:43:49 $ + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 2.66 $ + * Date: $Date: 2006/04/05 13:43:07 $ * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2006 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * $Log: skgehw.h,v $ - * Revision 1.49 2003/01/28 09:43:49 rschmidt - * Added defines for PCI-Spec. 2.3 IRQ - * Added defines for CLK_RUN (YUKON-Lite) - * Editorial changes - * - * Revision 1.48 2002/12/05 10:25:11 rschmidt - * Added defines for Half Duplex Burst Mode On/Off - * Added defines for Rx GMAC FIFO Flush feature - * Editorial changes - * - * Revision 1.47 2002/11/12 17:01:31 rschmidt - * Added defines for WOL_CTL_DEFAULT - * Editorial changes - * - * Revision 1.46 2002/10/14 14:47:57 rschmidt - * Corrected bit mask for HW self test results - * Added defines for WOL Registers - * Editorial changes - * - * Revision 1.45 2002/10/11 09:25:22 mkarl - * Added bit mask for HW self test results. - * - * Revision 1.44 2002/08/16 14:44:36 rschmidt - * Added define GPC_HWCFG_GMII_FIB for YUKON Fiber - * - * Revision 1.43 2002/08/12 13:31:50 rschmidt - * Corrected macros for GMAC Address Registers: GM_INADDR(), - * GM_OUTADDR(), GM_INHASH, GM_OUTHASH. - * Editorial changes - * - * Revision 1.42 2002/08/08 15:37:56 rschmidt - * Added defines for Power Management Capabilities - * Editorial changes - * - * Revision 1.41 2002/07/23 16:02:25 rschmidt - * Added macro WOL_REG() to access WOL reg. (HW-Bug in YUKON 1st rev.) - * - * Revision 1.40 2002/07/15 15:41:37 rschmidt - * Added new defines for Power Management Cap. & Control - * Editorial changes - * - * Revision 1.39 2002/06/10 09:37:07 rschmidt - * Added macros for the ADDR-Modul - * - * Revision 1.38 2002/06/05 08:15:19 rschmidt - * Added defines for WOL Registers - * Editorial changes - * - * Revision 1.37 2002/04/25 11:39:23 rschmidt - * Added new defines for PCI Our Register 1 - * Added new registers and defines for YUKON (Rx FIFO, Tx FIFO, - * Time Stamp Timer, GMAC Control, GPHY Control,Link Control, - * GMAC IRQ Source and Mask, Wake-up Frame Pattern Match); - * Added new defines for Control/Status (VAUX available) - * Added Chip ID for YUKON - * Added define for descriptors with UDP ext. for YUKON - * Added macros to access the GMAC - * Added new Phy Type for Marvell 88E1011S (GPHY) - * Editorial changes - * - * Revision 1.36 2000/11/09 12:32:49 rassmann - * Renamed variables. - * - * Revision 1.35 2000/05/19 10:17:13 cgoos - * Added inactivity check in PHY_READ (in DEBUG mode only). - * - * Revision 1.34 1999/11/22 13:53:40 cgoos - * Changed license header to GPL. - * - * Revision 1.33 1999/08/27 11:17:10 malthoff - * It's more savely to put brackets around macro parameters. - * Brackets added for PHY_READ and PHY_WRITE. - * - * Revision 1.32 1999/05/19 07:31:01 cgoos - * Changes for 1000Base-T. - * Added HWAC_LINK_LED macro. - * - * Revision 1.31 1999/03/12 13:27:40 malthoff - * Remove __STDC__. - * - * Revision 1.30 1999/02/09 09:28:20 malthoff - * Add PCI_ERRBITS. - * - * Revision 1.29 1999/01/26 08:55:48 malthoff - * Bugfix: The 16 bit field relations inside the descriptor are - * endianess dependend if the descriptor reversal feature - * (PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled. - * Drivers which use this feature has to set the define - * SK_USE_REV_DESC. - * - * Revision 1.28 1998/12/10 11:10:22 malthoff - * bug fix: IS_IRQ_STAT and IS_IRQ_MST_ERR has been twisted. - * - * Revision 1.27 1998/11/13 14:19:21 malthoff - * Bug Fix: The bit definition of B3_PA_CTRL has completely - * changed from HW Spec v1.3 to v1.5. - * - * Revision 1.26 1998/11/04 08:31:48 cgoos - * Fixed byte ordering in XM_OUTADDR/XM_OUTHASH macros. - * - * Revision 1.25 1998/11/04 07:16:25 cgoos - * Changed byte ordering in XM_INADDR/XM_INHASH again. - * - * Revision 1.24 1998/11/02 11:08:43 malthoff - * RxCtrl and TxCtrl must be volatile. - * - * Revision 1.23 1998/10/28 13:50:45 malthoff - * Fix: Endian support missing in XM_IN/OUT-ADDR/HASH macros. - * - * Revision 1.22 1998/10/26 08:01:36 malthoff - * RX_MFF_CTRL1 is split up into RX_MFF_CTRL1, - * RX_MFF_STAT_TO, and RX_MFF_TIST_TO. - * TX_MFF_CTRL1 is split up TX_MFF_CTRL1 and TX_MFF_WAF. - * - * Revision 1.21 1998/10/20 07:43:10 malthoff - * Fix: XM_IN/OUT/ADDR/HASH macros: - * The pointer must be casted. - * - * Revision 1.20 1998/10/19 15:53:59 malthoff - * Remove ML proto definitions. - * - * Revision 1.19 1998/10/16 14:40:17 gklug - * fix: typo B0_XM_IMSK regs - * - * Revision 1.18 1998/10/16 09:46:54 malthoff - * Remove temp defines for ML diag prototype. - * Fix register definition for B0_XM1_PHY_DATA, B0_XM1_PHY_DATA - * B0_XM2_PHY_DATA, B0_XM2_PHY_ADDR, B0_XA1_CSR, B0_XS1_CSR, - * B0_XS2_CSR, and B0_XA2_CSR. - * - * Revision 1.17 1998/10/14 06:03:14 cgoos - * Changed shifted constant to ULONG. - * - * Revision 1.16 1998/10/09 07:05:41 malthoff - * Rename ALL_PA_ENA_TO to PA_ENA_TO_ALL. - * - * Revision 1.15 1998/10/05 07:54:23 malthoff - * Split up RB_CTRL and it's bit definition into - * RB_CTRL, RB_TST1, and RB_TST2. - * Rename RB_RX_HTPP to RB_RX_LTPP. - * Add ALL_PA_ENA_TO. Modify F_WATER_MARK - * according to HW Spec. v1.5. - * Add MFF_TX_CTRL_DEF. - * - * Revision 1.14 1998/09/28 13:31:16 malthoff - * bug fix: B2_MAC_3 is 0x110 not 0x114 - * - * Revision 1.13 1998/09/24 14:42:56 malthoff - * Split the RX_MFF_TST into RX_MFF_CTRL2, - * RX_MFF_TST1, and RX_MFF_TST2. - * Rename RX_MFF_CTRL to RX_MFF_CTRL1. - * Add BMU bit CSR_SV_IDLE. - * Add macros PHY_READ() and PHY_WRITE(). - * Rename macro SK_ADDR() to SK_HW_ADDR() - * because of conflicts with the Address Module. - * - * Revision 1.12 1998/09/16 07:25:33 malthoff - * Change the parameter order in the XM_INxx and XM_OUTxx macros, - * to have the IoC as first parameter. - * - * Revision 1.11 1998/09/03 09:58:41 malthoff - * Rework the XM_xxx macros. Use {} instead of () to - * be compatible with SK_xxx macros which are defined - * with {}. - * - * Revision 1.10 1998/09/02 11:16:39 malthoff - * Temporary modify B2_I2C_SW to make tests with - * the GE/ML prototype. - * - * Revision 1.9 1998/08/19 09:11:49 gklug - * fix: struct are removed from c-source (see CCC) - * add: typedefs for all structs - * - * Revision 1.8 1998/08/18 08:27:27 malthoff - * Add some temporary workarounds to test GE - * sources with the ML. - * - * Revision 1.7 1998/07/03 14:42:26 malthoff - * bug fix: Correct macro XMA(). - * Add temporary workaround to access the PCI config space over I/O - * - * Revision 1.6 1998/06/23 11:30:36 malthoff - * Remove ';' with ',' in macors. - * - * Revision 1.5 1998/06/22 14:20:57 malthoff - * Add macro SK_ADDR(Base,Addr). - * - * Revision 1.4 1998/06/19 13:35:43 malthoff - * change 'pGec' with 'pAC' - * - * Revision 1.3 1998/06/17 14:58:16 cvs - * Lost keywords reinserted. - * - * Revision 1.1 1998/06/17 14:16:36 cvs - * created - * + * /LICENSE * ******************************************************************************/ @@ -316,6 +115,16 @@ extern "C" { #define SHIFT1(x) ((x) << 1) #define SHIFT0(x) ((x) << 0) +/* Macro for arbitrary alignment of a given pointer */ +#define ALIGN_ADDR( ADDRESS, GRANULARITY ) { \ + SK_UPTR addr = (SK_UPTR)(ADDRESS); \ + if (addr & ((GRANULARITY)-1)) { \ + addr += (GRANULARITY); \ + addr &= ~(SK_UPTR)((GRANULARITY)-1); \ + ADDRESS = (void *)addr; \ + }\ +} + /* * Configuration Space header * Since this module is used for different OS', those may be @@ -327,7 +136,7 @@ extern "C" { #define PCI_COMMAND 0x04 /* 16 bit Command */ #define PCI_STATUS 0x06 /* 16 bit Status */ #define PCI_REV_ID 0x08 /* 8 bit Revision ID */ -#if 0 +#if 0 /* uboot */ #define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */ #endif #define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */ @@ -336,32 +145,81 @@ extern "C" { #define PCI_BIST 0x0f /* 8 bit Built-in selftest */ #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ - /* Byte 0x18..0x2b: reserved */ + /* Bytes 0x18..0x2b: reserved */ #define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */ #define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */ #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */ -#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */ - /* Byte 35..3b: reserved */ +#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Pointer */ + /* Bytes 0x35..0x3b: reserved */ #define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */ #define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */ #define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */ #define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */ /* Device Dependent Region */ -#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ -#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ +#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ +#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ /* Power Management Region */ -#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */ -#define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */ -#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */ -#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */ +#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */ +#define PCI_PM_NITEM 0x49 /* 8 bit PM Next Item Pointer */ +#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */ +#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */ /* Byte 0x4e: reserved */ -#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */ +#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */ /* VPD Region */ -#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */ -#define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */ -#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */ -#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */ - /* Byte 0x58..0xff: reserved */ +#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */ +#define PCI_VPD_NITEM 0x51 /* 8 bit VPD Next Item Pointer */ +#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */ +#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */ + /* Bytes 0x58..0x59: reserved */ +#define PCI_SER_LD_CTRL 0x5a /* 16 bit SEEPROM Loader Ctrl (YUKON only) */ + /* Bytes 0x5c..0xfc: used by Yukon-2 */ +#define PCI_MSI_CAP_ID 0x5c /* 8 bit MSI Capability ID Register */ +#define PCI_MSI_NITEM 0x5d /* 8 bit MSI Next Item Pointer */ +#define PCI_MSI_CTRL 0x5e /* 16 bit MSI Message Control */ +#define PCI_MSI_ADR_LO 0x60 /* 32 bit MSI Message Address (Lower) */ +#define PCI_MSI_ADR_HI 0x64 /* 32 bit MSI Message Address (Upper) */ +#define PCI_MSI_DATA 0x68 /* 16 bit MSI Message Data */ + /* Bytes 0x6a..0x6b: reserved */ +#define PCI_X_CAP_ID 0x6c /* 8 bit PCI-X Capability ID Register */ +#define PCI_X_NITEM 0x6d /* 8 bit PCI-X Next Item Pointer */ +#define PCI_X_COMMAND 0x6e /* 16 bit PCI-X Command */ +#define PCI_X_PE_STAT 0x70 /* 32 bit PCI-X / PE Status */ +#define PCI_CAL_CTRL 0x74 /* 16 bit PCI Calibration Control Register */ +#define PCI_CAL_STAT 0x76 /* 16 bit PCI Calibration Status Register */ +#define PCI_DISC_CNT 0x78 /* 16 bit PCI Discard Counter */ +#define PCI_RETRY_CNT 0x7a /* 8 bit PCI Retry Counter */ + /* Byte 0x7b: reserved */ +#define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */ +#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 (Yukon-ECU only) */ +#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 (Yukon-ECU only) */ +#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 (Yukon-ECU only) */ + /* Bytes 0x8c..0xdf: reserved */ + +/* PCI Express Capability */ +#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */ +#define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */ +#define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */ +#define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */ +#define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */ +#define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */ +#define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */ +#define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */ +#define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */ + /* Bytes 0xf4..0xff: reserved */ + +/* PCI Express Extended Capabilities */ +#define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */ +#define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */ +#define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */ +#define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */ +#define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */ +#define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */ +#define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */ +#define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */ + +/* PCI Express Ack Timer for 1x Link */ +#define PEX_ACK_LAT_TOX1 0x228 /* 16 bit PEX Ack Latency Timeout x1 */ +#define PEX_ACK_RPLY_TOX1 0x22a /* 16 bit PEX Ack Reply Timeout val x1 */ /* * I2C Address (PCI Config) @@ -369,7 +227,7 @@ extern "C" { * Note: The temperature and voltage sensors are relocated on a different * I2C bus. */ -#define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */ +#define I2C_ADDR_VPD 0xa0 /* I2C address for the VPD EEPROM */ /* * Define Bits and Values of the registers @@ -382,13 +240,13 @@ extern "C" { #define PCI_ADSTEP BIT_7S /* Address Stepping */ #define PCI_PERREN BIT_6S /* Parity Report Response enable */ #define PCI_VGA_SNOOP BIT_5S /* VGA palette snoop */ -#define PCI_MWIEN BIT_4S /* Memory write an inv cycl ena */ +#define PCI_MWIEN BIT_4S /* Memory write an inv cycl enable */ #define PCI_SCYCEN BIT_3S /* Special Cycle enable */ #define PCI_BMEN BIT_2S /* Bus Master enable */ #define PCI_MEMEN BIT_1S /* Memory Space Access enable */ #define PCI_IOEN BIT_0S /* I/O Space Access enable */ -#define PCI_COMMAND_VAL (PCI_FBTEN | PCI_SERREN | PCI_PERREN | PCI_MWIEN |\ +#define PCI_COMMAND_VAL (PCI_INT_DIS | PCI_SERREN | PCI_PERREN | \ PCI_BMEN | PCI_MEMEN | PCI_IOEN) /* PCI_STATUS 16 bit Status */ @@ -422,7 +280,7 @@ extern "C" { /* PCI_HEADER_T 8 bit Header Type */ #define PCI_HD_MF_DEV BIT_7S /* 0= single, 1= multi-func dev */ -#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */ +#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout (0=normal) */ /* PCI_BIST 8 bit Built-in selftest */ /* Built-in Self test not supported (optional) */ @@ -431,33 +289,42 @@ extern "C" { #define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */ #define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */ #define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */ -#define PCI_PREFEN BIT_3 /* Prefetchable */ -#define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */ +#define PCI_PREFEN BIT_3 /* Prefetch enable */ +#define PCI_MEM_TYP_MSK (3L<<1) /* Bit 2.. 1: Memory Type Mask */ +#define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */ + #define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */ #define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */ #define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */ -#define PCI_MEMSPACE BIT_0 /* Memory Space Indic. */ /* PCI_BASE_2ND 32 bit 2nd Base address */ #define PCI_IOBASE 0xffffff00L /* Bit 31.. 8: I/O Base address */ #define PCI_IOSIZE 0x000000fcL /* Bit 7.. 2: I/O Size Requirements */ - /* Bit 1: reserved */ + /* Bit 1: reserved */ #define PCI_IOSPACE BIT_0 /* I/O Space Indicator */ /* PCI_BASE_ROM 32 bit Expansion ROM Base Address */ -#define PCI_ROMBASE 0xfffe0000L /* Bit 31..17: ROM BASE address (1st)*/ -#define PCI_ROMBASZ (0x1cL<<14) /* Bit 16..14: Treat as BASE or SIZE */ +#define PCI_ROMBASE_MSK 0xfffe0000L /* Bit 31..17: ROM Base address */ +#define PCI_ROMBASE_SIZ (0x1cL<<14) /* Bit 16..14: Treat as Base or Size */ #define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */ - /* Bit 10.. 1: reserved */ + /* Bit 10.. 1: reserved */ #define PCI_ROMEN BIT_0 /* Address Decode enable */ /* Device Dependent Region */ /* PCI_OUR_REG_1 32 bit Our Register 1 */ - /* Bit 31..29: reserved */ -#define PCI_PHY_COMA BIT_28 /* Set PHY to Coma Mode */ -#define PCI_EN_CAL BIT_27 /* Enable PCI buffer strength calibr. */ -#define PCI_DIS_CAL BIT_26 /* Disable PCI buffer strength calibr. */ + /* Bit 31..29: reserved */ +#define PCI_PHY_COMA BIT_28 /* Set PHY to Coma Mode (YUKON only) */ +#define PCI_TEST_CAL BIT_27 /* Test PCI buffer calib. (YUKON only) */ +#define PCI_EN_CAL BIT_26 /* Enable PCI buffer calib. (YUKON only) */ #define PCI_VIO BIT_25 /* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */ +/* Yukon-2 */ +#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */ +#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */ +#define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */ +#define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */ +#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */ +#define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */ + /* Bit 25: reserved */ #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ #define PCI_EN_IO BIT_23 /* Mapping to I/O space */ #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ @@ -468,9 +335,10 @@ extern "C" { #define PCI_PAGE_32K (1L<<20) /* 32 k pages */ #define PCI_PAGE_64K (2L<<20) /* 64 k pages */ #define PCI_PAGE_128K (3L<<20) /* 128 k pages */ - /* Bit 19: reserved */ -#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */ + /* Bit 19: reserved */ +#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */ #define PCI_NOTAR BIT_15 /* No turnaround cycle */ +#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */ #define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ @@ -480,13 +348,21 @@ extern "C" { #define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ #define PCI_SKEW_DAS (0xfL<<4) /* Bit 7.. 4: Skew Ctrl, DAS Ext */ #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ +#define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */ +/* Yukon-EC Ultra only */ + /* Bit 14..10: reserved */ +#define PCI_PHY_LNK_TIM_MSK (3L<<8) /* Bit 9.. 8: GPHY Link Trigger Timer */ +#define PCI_ENA_L1_EVENT BIT_7 /* Enable PEX L1 Event */ +#define PCI_ENA_GPHY_LNK BIT_6 /* Enable PEX L1 on GPHY Link down */ +#define PCI_FORCE_PEX_L1 BIT_5 /* Force to PEX L1 */ + /* Bit 4.. 0: reserved */ /* PCI_OUR_REG_2 32 bit Our Register 2 */ #define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */ #define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */ #define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */ - /* Bit 13..12: reserved */ + /* Bit 13..12: reserved */ #define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ #define PCI_PATCH_DIR_3 BIT_11 #define PCI_PATCH_DIR_2 BIT_10 @@ -498,22 +374,21 @@ extern "C" { #define PCI_EXT_PATCH_1 BIT_5 #define PCI_EXT_PATCH_0 BIT_4 #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ -#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ - /* Bit 1: reserved */ +#define PCI_REV_DESC BIT_2 /* Reverse Descriptor Bytes */ + /* Bit 1: reserved */ #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ - -/* Power Management Region */ +/* Power Management (PM) Region */ /* PCI_PM_CAP_REG 16 bit Power Management Capabilities */ -#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event Support Mask */ -#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if Vaux) */ +#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event (PME) Supp. Mask */ +#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if VAUX) */ #define PCI_PME_D3H_SUP BIT_14S /* PME from D3hot Support */ #define PCI_PME_D2_SUP BIT_13S /* PME from D2 Support */ #define PCI_PME_D1_SUP BIT_12S /* PME from D1 Support */ #define PCI_PME_D0_SUP BIT_11S /* PME from D0 Support */ #define PCI_PM_D2_SUP BIT_10S /* D2 Support in 33 MHz mode */ #define PCI_PM_D1_SUP BIT_9S /* D1 Support */ - /* Bit 8.. 6: reserved */ + /* Bit 8.. 6: reserved */ #define PCI_PM_DSI BIT_5S /* Device Specific Initialization */ #define PCI_PM_APS BIT_4S /* Auxialiary Power Source */ #define PCI_PME_CLOCK BIT_3S /* PM Event Clock */ @@ -524,7 +399,7 @@ extern "C" { #define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: Data Reg. scaling factor */ #define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field */ #define PCI_PME_EN BIT_8S /* Enable PME# generation (YUKON only) */ - /* Bit 7.. 2: reserved */ + /* Bit 7.. 2: reserved */ #define PCI_PM_STATE_MSK 3 /* Bit 1.. 0: Power Management State */ #define PCI_PM_STATE_D0 0 /* D0: Operational (default) */ @@ -535,7 +410,151 @@ extern "C" { /* VPD Region */ /* PCI_VPD_ADR_REG 16 bit VPD Address Register */ #define PCI_VPD_FLAG BIT_15S /* starts VPD rd/wr cycle */ -#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD address mask */ +#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD Address Mask */ + +/* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */ +#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */ +#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */ +#define PCI_OS_MODE_MSK (3L<<28) /* Bit 29..28: PCI-X Bus Mode Mask */ +#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */ +#define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */ +#define PCI_OS_DLLE_MSK (3L<<24) /* Bit 25..24: DLL Status Indication */ +#define PCI_OS_DLLR_MSK (0xfL<<20) /* Bit 23..20: DLL Row Counters Values */ +#define PCI_OS_DLLC_MSK (0xfL<<16) /* Bit 19..16: DLL Col. Counters Values */ + /* Bit 15.. 8: reserved */ + +#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ +/* possible values for the speed field of the register */ +#define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */ +#define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */ +#define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */ +#define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */ + +/* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */ + /* Bit 31..18: reserved */ +#define P_CLK_COR_REGS_D0_DIS BIT_17 /* Disable Clock Core Regs in D0 */ +#define P_CLK_PCI_REGS_D0_DIS BIT_16 /* Disable Clock PCI Regs in D0 */ +#define P_CLK_COR_YTB_ARB_DIS BIT_15 /* Disable Clock YTB Arbiter */ +#define P_CLK_MAC_LNK1_D3_DIS BIT_14 /* Disable Clock MAC Link1 in D3 */ +#define P_CLK_COR_LNK1_D0_DIS BIT_13 /* Disable Clock Core Link1 in D0 */ +#define P_CLK_MAC_LNK1_D0_DIS BIT_12 /* Disable Clock MAC Link1 in D0 */ +#define P_CLK_COR_LNK1_D3_DIS BIT_11 /* Disable Clock Core Link1 in D3 */ +#define P_CLK_PCI_MST_ARB_DIS BIT_10 /* Disable Clock PCI Master Arb. */ +#define P_CLK_COR_REGS_D3_DIS BIT_9 /* Disable Clock Core Regs in D3 */ +#define P_CLK_PCI_REGS_D3_DIS BIT_8 /* Disable Clock PCI Regs in D3 */ +#define P_CLK_REF_LNK1_GM_DIS BIT_7 /* Disable Clock Ref. Link1 GMAC */ +#define P_CLK_COR_LNK1_GM_DIS BIT_6 /* Disable Clock Core Link1 GMAC */ +#define P_CLK_PCI_COMMON_DIS BIT_5 /* Disable Clock PCI Common */ +#define P_CLK_COR_COMMON_DIS BIT_4 /* Disable Clock Core Common */ +#define P_CLK_PCI_LNK1_BMU_DIS BIT_3 /* Disable Clock PCI Link1 BMU */ +#define P_CLK_COR_LNK1_BMU_DIS BIT_2 /* Disable Clock Core Link1 BMU */ +#define P_CLK_PCI_LNK1_BIU_DIS BIT_1 /* Disable Clock PCI Link1 BIU */ +#define P_CLK_COR_LNK1_BIU_DIS BIT_0 /* Disable Clock Core Link1 BIU */ + +/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ +#define P_PEX_LTSSM_STAT_MSK (0x7fL<<25) /* Bit 31..25: PEX LTSSM Mask */ + /* (Link Training & Status State Machine) */ + /* Bit 24: reserved */ +#define P_TIMER_VALUE_MSK (0xffL<<16) /* Bit 23..16: Timer Value Mask */ +#define P_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */ + /* (Active State Power Management) */ + /* Bit 14..12: Force ASPM on Event */ +#define P_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */ +#define P_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */ +#define P_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */ + /* Bit 11.. 8: reserved */ +#define P_ASPM_FORCE_ASPM_L1 BIT_7 /* Force ASPM L1 Enable (A1b only) */ +#define P_ASPM_FORCE_ASPM_L0S BIT_6 /* Force ASPM L0s Enable (A1b only) */ +#define P_ASPM_FORCE_CLKREQ_PIN BIT_5 /* Force CLKREQn pin low (A1b only) */ +#define P_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */ +#define P_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */ +#define P_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */ +#define P_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */ +#define P_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */ + +#define P_PEX_LTSSM_STAT(x) (SHIFT25(x) & P_PEX_LTSSM_STAT_MSK) +#define P_PEX_LTSSM_L1_STAT 0x34 +#define P_PEX_LTSSM_DET_STAT 0x01 + +#define P_ASPM_CONTROL_MSK (P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN | \ + P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY) + +/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ + /* Bit 31..27: reserved */ + /* Bit 26..16: Release Clock on Event */ +#define P_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */ +#define P_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */ +#define P_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */ +#define P_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */ +#define P_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */ +#define P_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */ +#define P_REL_PME_ASSERTED BIT_20 /* PME Asserted */ +#define P_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */ +#define P_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */ +#define P_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */ +#define P_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */ + /* Bit 15..11: reserved */ + /* Bit 10.. 0: Mask for Gate Clock */ +#define P_GAT_PCIE_RST_DE_ASS BIT_10 /* PCIe Reset De-Asserted */ +#define P_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */ +#define P_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */ +#define P_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */ +#define P_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */ +#define P_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */ +#define P_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */ +#define P_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */ +#define P_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */ +#define P_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */ +#define P_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */ + +/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */ + /* Bit 15 reserved */ +#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */ +#define PEX_DC_EN_NO_SNOOP BIT_11S /* Enable No Snoop */ +#define PEX_DC_EN_AUX_POW BIT_10S /* Enable AUX Power */ +#define PEX_DC_EN_PHANTOM BIT_9S /* Enable Phantom Functions */ +#define PEX_DC_EN_EXT_TAG BIT_8S /* Enable Extended Tag Field */ +#define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */ +#define PEX_DC_EN_REL_ORD BIT_4S /* Enable Relaxed Ordering */ +#define PEX_DC_EN_UNS_RQ_RP BIT_3S /* Enable Unsupported Request Reporting */ +#define PEX_DC_EN_FAT_ER_RP BIT_2S /* Enable Fatal Error Reporting */ +#define PEX_DC_EN_NFA_ER_RP BIT_1S /* Enable Non-Fatal Error Reporting */ +#define PEX_DC_EN_COR_ER_RP BIT_0S /* Enable Correctable Error Reporting */ + +#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) + +/* PEX_LNK_CAP 32 bit PEX Link Capabilities */ +#define PEX_CAP_MAX_WI_MSK (0x3f<<4) /* Bit 9.. 4: Max. Link Width Mask */ +#define PEX_CAP_MAX_SP_MSK 0x0f /* Bit 3.. 0: Max. Link Speed Mask */ + +/* PEX_LNK_CTRL 16 bit PEX Link Control (Yukon-2) */ +#define PEX_LC_CLK_PM_ENA BIT_8S /* Enable Clock Power Management (CLKREQ) */ + +/* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */ + /* Bit 15..13 reserved */ +#define PEX_LS_SLOT_CLK_CFG BIT_12S /* Slot Clock Config */ +#define PEX_LS_LINK_TRAIN BIT_11S /* Link Training */ +#define PEX_LS_TRAIN_ERROR BIT_10S /* Training Error */ +#define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */ +#define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */ + +/* PEX_UNC_ERR_STAT 16 bit PEX Uncorrectable Errors Status (Yukon-2) */ + /* Bit 31..21 reserved */ +#define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */ + /* ECRC Error (not supported) */ +#define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */ +#define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */ +#define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */ + /* Completer Abort (not supported) */ +#define PEX_COMP_TO BIT_14 /* Completion Timeout */ +#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */ +#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */ + /* Bit 11.. 5: reserved */ +#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */ + /* Bit 3.. 1: reserved */ + /* Training Error (not supported) */ + +#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P) /* Control Register File (Address Map) */ @@ -544,15 +563,21 @@ extern "C" { */ #define B0_RAP 0x0000 /* 8 bit Register Address Port */ /* 0x0001 - 0x0003: reserved */ -#define B0_CTST 0x0004 /* 16 bit Control/Status register */ -#define B0_LED 0x0006 /* 8 Bit LED register */ +#define B0_CTST 0x0004 /* 16 bit Control/Status Register */ +#define B0_LED 0x0006 /* 8 Bit LED Register */ #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ -#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */ - /* 0x001c: reserved */ +#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */ + +/* Special ISR registers (Yukon-2 only) */ +#define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */ +#define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */ +#define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Register */ +#define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Register */ +#define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Register */ /* B0 XMAC 1 registers (GENESIS only) */ #define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/ @@ -574,7 +599,7 @@ extern "C" { #define B0_XM2_PHY_DATA 0x0054 /* 16 bit r/w XMAC 2 PHY Data Register */ /* 0x0056 - 0x005f: reserved */ -/* BMU Control Status Registers */ +/* BMU Control Status Registers (Yukon and Genesis) */ #define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */ #define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */ #define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ @@ -592,7 +617,7 @@ extern "C" { /* * Bank 2 */ -/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */ +/* NA reg = 48 bit Network Address Register, 3x16 or 6x8 bit readable */ #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ /* 0x0106 - 0x0107: reserved */ #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ @@ -602,21 +627,30 @@ extern "C" { #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ -#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ - /* Eprom registers are currently of no use */ +#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ + /* Eprom registers */ #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ +/* Yukon and Genesis */ #define B2_E_1 0x011d /* 8 bit EPROM Byte 1 (PHY type) */ #define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */ +/* Yukon-2 */ +#define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ +#define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */ + #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ + +/* Yukon and Genesis */ #define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */ #define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */ +/* Yukon-2 */ +#define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */ /* 0x0125 - 0x0127: reserved */ -#define B2_LD_CRTL 0x0128 /* 8 bit EPROM loader control register */ +#define B2_LD_CTRL 0x0128 /* 8 bit EPROM loader control register */ #define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */ /* 0x012a - 0x012f: reserved */ #define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ #define B2_TI_VAL 0x0134 /* 32 bit Timer Value */ -#define B2_TI_CRTL 0x0138 /* 8 bit Timer Control */ +#define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */ #define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ /* 0x013a - 0x013f: reserved */ #define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ @@ -641,6 +675,10 @@ extern "C" { #define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */ #define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */ #define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */ + +/* Yukon-2 */ +#define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */ +#define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */ /* 0x017c - 0x017f: reserved */ /* @@ -650,9 +688,14 @@ extern "C" { #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ +#define B3_RAM_PARITY 0x018c /* 8 bit RAM Parity (Yukon-ECU A1) */ + +#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */ + /* 0x018c - 0x018f: reserved */ /* RAM Interface Registers */ +/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */ /* * The HW-Spec. calls this registers Timeout Value 0..11. But this names are * not usable in SW. Please notice these are NOT real timeouts, these are @@ -719,8 +762,8 @@ extern "C" { /* 0x01ea - 0x01eb: reserved */ #define B3_PA_TOVAL_TX2 0x01ec /* 16 bit Timeout Val Tx Path MAC 2 */ /* 0x01ee - 0x01ef: reserved */ -#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */ -#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */ +#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */ +#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */ /* 0x01f4 - 0x01ff: reserved */ /* @@ -734,7 +777,16 @@ extern "C" { #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ - /* 0x0213 - 0x027f: reserved */ + /* 0x0213 - 0x021f: reserved */ + + /* RSS key registers for Yukon-2 Family */ +#define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */ + /* RSS key register offsets */ +#define KEY_IDX_0 0 /* offset for location of KEY 0 */ +#define KEY_IDX_1 4 /* offset for location of KEY 1 */ +#define KEY_IDX_2 8 /* offset for location of KEY 2 */ +#define KEY_IDX_3 12 /* offset for location of KEY 3 */ + /* 0x0280 - 0x0292: MAC 2 */ /* 0x0213 - 0x027f: reserved */ @@ -758,10 +810,10 @@ extern "C" { /* Queue Register Offsets, use Q_ADDR() to access */ #define Q_D 0x00 /* 8*32 bit Current Descriptor */ -#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ -#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High dWord */ -#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ -#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ +#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low DWord */ +#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High DWord */ +#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low DWord */ +#define Q_AC_H 0x2c /* 32 bit Current Address Counter High DWord */ #define Q_BC 0x30 /* 32 bit Current Byte Counter */ #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ #define Q_F 0x38 /* 32 bit Flag Register */ @@ -772,8 +824,56 @@ extern "C" { #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ #define Q_T2 0x40 /* 32 bit Test Register 2 */ #define Q_T3 0x44 /* 32 bit Test Register 3 */ + +/* Yukon-2 */ +#define Q_DONE 0x24 /* 16 bit Done Index */ + +#define Q_WM 0x40 /* 16 bit FIFO Watermark */ +#define Q_AL 0x42 /* 8 bit FIFO Alignment */ + /* 0x43: reserved */ +/* RX Queue */ +#define Q_RX_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */ +#define Q_RX_RSL 0x46 /* 8 bit FIFO Read Shadow Level */ + /* 0x47: reserved */ +#define Q_RX_RP 0x48 /* 8 bit FIFO Read Pointer */ + /* 0x49: reserved */ +#define Q_RX_RL 0x4a /* 8 bit FIFO Read Level */ + /* 0x4b: reserved */ +#define Q_RX_WP 0x4c /* 8 bit FIFO Write Pointer */ +#define Q_RX_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */ +#define Q_RX_WL 0x4e /* 8 bit FIFO Write Level */ +#define Q_RX_WSL 0x4f /* 8 bit FIFO Write Shadow Level */ +/* TX Queue */ +#define Q_TX_WSP 0x44 /* 16 bit FIFO Write Shadow Pointer */ +#define Q_TX_WSL 0x46 /* 8 bit FIFO Write Shadow Level */ + /* 0x47: reserved */ +#define Q_TX_WP 0x48 /* 8 bit FIFO Write Pointer */ + /* 0x49: reserved */ +#define Q_TX_WL 0x4a /* 8 bit FIFO Write Level */ + /* 0x4b: reserved */ +#define Q_TX_RP 0x4c /* 8 bit FIFO Read Pointer */ + /* 0x4d: reserved */ +#define Q_TX_RL 0x4e /* 8 bit FIFO Read Level */ + /* 0x4f: reserved */ + /* 0x48 - 0x7f: reserved */ +/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/ +#define Y2_B8_PREF_REGS 0x0450 + +#define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */ +#define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */ +#define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */ +#define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/ +#define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */ +#define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */ +#define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */ +#define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */ +#define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */ +#define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */ + +#define PREF_UNIT_MASK_IDX 0x0fff + /* * Bank 16 - 23 */ @@ -785,17 +885,17 @@ extern "C" { #define RB_END 0x04 /* 32 bit RAM Buffer End Address */ #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ -#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Pack */ -#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Pack */ +#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */ +#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */ #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ -#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ +#define RB_CTRL 0x28 /* 32 bit RAM Buffer Control Register */ #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ -#define RB_TST2 0x2A /* 8 bit RAM Buffer Test Register 2 */ - /* 0x2c - 0x7f: reserved */ +#define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */ + /* 0x2b - 0x7f: reserved */ /* * Bank 24 @@ -805,7 +905,7 @@ extern "C" { * use MR_ADDR() to access */ #define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */ -#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */ +#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */ /* 0x0c08 - 0x0c0b: reserved */ #define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */ #define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */ @@ -830,20 +930,23 @@ extern "C" { #define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */ /* 0x0c3d - 0x0c3f: reserved */ -/* Receive GMAC FIFO (YUKON only), use MR_ADDR() to access */ +/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ - /* 0x0c54 - 0x0c5f: reserved */ -#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ +#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ +#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ +#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ +#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ +#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ /* 0x0c64 - 0x0c67: reserved */ -#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ +#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ /* 0x0c6c - 0x0c6f: reserved */ -#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ +#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ /* 0x0c74 - 0x0c77: reserved */ -#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ +#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ /* 0x0c7c - 0x0c7f: reserved */ /* @@ -860,7 +963,7 @@ extern "C" { * use MR_ADDR() to access */ #define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */ -#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */ +#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */ #define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Ptr */ #define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */ #define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */ @@ -878,18 +981,19 @@ extern "C" { #define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Reg */ /* 0x0d2a - 0x0d3f: reserved */ -/* Transmit GMAC FIFO (YUKON only), use MR_ADDR() to access */ +/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ -#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ +#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh. */ #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ - /* 0x0d4c - 0x0d5f: reserved */ -#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ -#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ -#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ + /* 0x0d4c - 0x0d5b: reserved */ +#define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */ +#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ +#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */ +#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ /* 0x0d6c - 0x0d6f: reserved */ -#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ -#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ -#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ +#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ +#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ +#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ /* 0x0d7c - 0x0d7f: reserved */ /* @@ -915,12 +1019,84 @@ extern "C" { #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ /* 0x0e19: reserved */ #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ - /* 0x0e1b - 0x0e7f: reserved */ + /* 0x0e1b - 0x0e1f: reserved */ + +/* Polling Unit Registers (Yukon-2 only) */ +#define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */ +#define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */ + /* 0x0e26 - 0x0e27: reserved */ +#define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */ +#define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */ + /* 0x0e30 - 0x0e3f: reserved */ + +/* ASF Subsystem Registers (Yukon-2 only) */ +#define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ +#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ + /* 0x0e48 - 0x0e5f: reserved */ +#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ + /* 0x0e64 - 0x0e67: reserved */ +#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ +#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */ +#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */ +#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */ +#define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */ +#define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */ /* * Bank 29 */ - /* 0x0e80 - 0x0efc: reserved */ + +/* Status BMU Registers (Yukon-2 only)*/ +#define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */ +#define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */ + /* 0x0e85 - 0x0e86: reserved */ +#define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */ +#define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */ +#define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */ +#define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */ +#define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */ +#define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */ +#define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */ + /* 0x0e9a - 0x0e9b: reserved */ +#define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */ + /* 0x0e9e - 0x0e9f: reserved */ + +/* FIFO Control/Status Registers (Yukon-2 only) */ +#define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */ + /* 0x0ea1 - 0x0ea3: reserved */ +#define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */ + /* 0x0ea5: reserved */ +#define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */ + /* 0x0ea7: reserved */ +#define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */ + /* 0x0ea9: reserved */ +#define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */ + /* 0x0eab: reserved */ +#define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */ +#define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */ + /* 0x0eae - 0x0eaf: reserved */ + +/* Level and ISR Timer Registers (Yukon-2 only) */ +#define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */ +#define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */ +#define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */ +#define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */ + /* 0x0eba - 0x0ebf: reserved */ +#define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */ +#define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */ +#define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */ +#define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */ + /* 0x0eca - 0x0ecf: reserved */ +#define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */ +#define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */ +#define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */ +#define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */ + /* 0x0eda - 0x0eff: reserved */ + +#define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */ +#define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */ +#define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */ +#define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */ /* * Bank 30 @@ -944,11 +1120,9 @@ extern "C" { #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ -#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Ptr */ - -/* use this macro to access above registers */ -#define WOL_REG(Reg) ((Reg) + (pAC->GIni.GIWolOffs)) - +#define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */ +#define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */ +#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */ /* WOL Pattern Length Registers (YUKON only) */ @@ -966,11 +1140,22 @@ extern "C" { */ /* 0x0f80 - 0x0fff: reserved */ +/* WOL registers link 2 */ + +/* use this macro to access WOL registers */ +#define WOL_REG(Port, Reg) ((Reg) + ((Port)*0x80) + (pAC->GIni.GIWolOffs)) + /* * Bank 32 - 33 */ #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ +#define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */ +/* use this macro to retrieve the pattern ram base address */ +#define WOL_PATT_RAM_BASE(Port) (WOL_PATT_RAM_1 + (Port)*0x400) + +/* offset to configuration space on Yukon-2 */ +#define Y2_CFG_SPC 0x1c00 /* * Bank 0x22 - 0x3f */ @@ -1002,13 +1187,27 @@ extern "C" { */ /* B0_RAP 8 bit Register Address Port */ /* Bit 7: reserved */ -#define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0,..,6f = block 6f */ +#define RAP_MSK 0x7f /* Bit 6..0: 0 = block 0,..,6f = block 6f */ -/* B0_CTST 16 bit Control/Status register */ +/* B0_CTST 24 bit Control/Status register */ + /* Bit 23..18: reserved */ +#define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */ +#define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */ +#define Y2_HW_WOL_ON BIT_15S /* HW WOL On (Yukon-EC Ultra A1 only) */ +#define Y2_HW_WOL_OFF BIT_14S /* HW WOL Off (Yukon-EC Ultra A1 only) */ +#define Y2_ASF_ENABLE BIT_13S /* ASF Unit Enable (YUKON-2 only) */ +#define Y2_ASF_DISABLE BIT_12S /* ASF Unit Disable (YUKON-2 only) */ +#define Y2_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-2 only) */ +#define Y2_CLK_RUN_DIS BIT_10S /* CLK_RUN Disable (YUKON-2 only) */ +#define Y2_LED_STAT_ON BIT_9S /* Status LED On (YUKON-2 only) */ +#define Y2_LED_STAT_OFF BIT_8S /* Status LED Off (YUKON-2 only) */ + /* Bit 7.. 0: same as below */ + +/* B0_CTST 16 bit Control/Status register */ /* Bit 15..14: reserved */ -#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN hot m. (YUKON-Lite only) */ -#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN reset (YUKON-Lite only) */ -#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN enable (YUKON-Lite only) */ +#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN Hot m. (YUKON-Lite only) */ +#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN Reset (YUKON-Lite only) */ +#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-Lite only) */ #define CS_VAUX_AVAIL BIT_10S /* VAUX available (YUKON only) */ #define CS_BUS_CLOCK BIT_9S /* Bus Clock 0/1 = 33/66 MHz */ #define CS_BUS_SLOT_SZ BIT_8S /* Slot Size 0/1 = 32/64 bit slot */ @@ -1016,31 +1215,32 @@ extern "C" { #define CS_CL_SW_IRQ BIT_6S /* Clear IRQ SW Request */ #define CS_STOP_DONE BIT_5S /* Stop Master is finished */ #define CS_STOP_MAST BIT_4S /* Command Bit to stop the master */ -#define CS_MRST_CLR BIT_3S /* Clear Master reset */ -#define CS_MRST_SET BIT_2S /* Set Master reset */ -#define CS_RST_CLR BIT_1S /* Clear Software reset */ -#define CS_RST_SET BIT_0S /* Set Software reset */ +#define CS_MRST_CLR BIT_3S /* Clear Master Reset */ +#define CS_MRST_SET BIT_2S /* Set Master Reset */ +#define CS_RST_CLR BIT_1S /* Clear Software Reset */ +#define CS_RST_SET BIT_0S /* Set Software Reset */ -/* B0_LED 8 Bit LED register */ +/* B0_LED 8 Bit LED register (GENESIS only)*/ /* Bit 7.. 2: reserved */ -#define LED_STAT_ON BIT_1S /* Status LED on */ -#define LED_STAT_OFF BIT_0S /* Status LED off */ +#define LED_STAT_ON BIT_1S /* Status LED On */ +#define LED_STAT_OFF BIT_0S /* Status LED Off */ /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ -#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ -#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ -#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ -#define PC_VAUX_ON BIT_3 /* Switch VAUX On */ -#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ -#define PC_VCC_ON BIT_1 /* Switch VCC On */ -#define PC_VCC_OFF BIT_0 /* Switch VCC Off */ +#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ +#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ +#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ +#define PC_VAUX_ON BIT_3 /* Switch VAUX On */ +#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ +#define PC_VCC_ON BIT_1 /* Switch VCC On */ +#define PC_VCC_OFF BIT_0 /* Switch VCC Off */ -/* B0_ISRC 32 bit Interrupt Source Register */ -/* B0_IMSK 32 bit Interrupt Mask Register */ -/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ +/* Yukon and Genesis */ +/* B0_ISRC 32 bit Interrupt Source Register */ +/* B0_IMSK 32 bit Interrupt Mask Register */ +/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ -#define IS_ALL_MSK 0xbfffffffL /* All Interrupt bits */ +#define IS_ALL_MSK 0xbfffffffUL /* All Interrupt bits */ #define IS_HW_ERR BIT_31 /* Interrupt HW Error */ /* Bit 30: reserved */ #define IS_PA_TO_RX1 BIT_29 /* Packet Arb Timeout Rx1 */ @@ -1081,12 +1281,58 @@ extern "C" { #define IS_XA2_F BIT_1 /* Q_XA2 End of Frame */ #define IS_XA2_C BIT_0 /* Q_XA2 Encoding Error */ +/* Yukon-2 */ +/* B0_ISRC 32 bit Interrupt Source Register */ +/* B0_IMSK 32 bit Interrupt Mask Register */ +/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ +/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ +/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ +/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ +/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ +#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) +#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */ +#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */ +#define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */ + /* Bit 28: reserved */ +#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */ +#define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */ +#define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */ +#define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */ + /* Bit 23..16 reserved */ + /* Link 2 Interrupts */ +#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */ +#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */ +#define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ +#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ +#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ + /* Bit 7.. 5 reserved */ + /* Link 1 interrupts */ +#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ +#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ +#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ +#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */ +#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */ -/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ -/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ -/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ +#define Y2_IS_L1_MASK 0x0000001fUL /* IRQ Mask for port 1 */ + +#define Y2_IS_L2_MASK 0x00001f00UL /* IRQ Mask for port 2 */ + +#define Y2_IS_ALL_MSK 0xef001f1fUL /* All Interrupt bits */ + +/* B0_Y2_SP_ICR 32 bit Interrupt Control Register */ + /* Bit 31.. 4: reserved */ +#define Y2_IC_ISR_MASK BIT_3 /* ISR mask flag */ +#define Y2_IC_ISR_STAT BIT_2 /* ISR status flag */ +#define Y2_IC_LEAVE_ISR BIT_1 /* Leave ISR */ +#define Y2_IC_ENTER_ISR BIT_0 /* Enter ISR */ + +/* Yukon and Genesis */ +/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ +/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ #define IS_ERR_MSK 0x00000fffL /* All Error bits */ - /* Bit 31..14: reserved */ + /* Bit 31..14: reserved */ #define IS_IRQ_TIST_OV BIT_13 /* Time Stamp Timer Overflow (YUKON only) */ #define IS_IRQ_SENSOR BIT_12 /* IRQ from Sensor (YUKON only) */ #define IS_IRQ_MST_ERR BIT_11 /* IRQ master error detected */ @@ -1102,27 +1348,125 @@ extern "C" { #define IS_R1_PAR_ERR BIT_1 /* Queue R1 Parity Error */ #define IS_R2_PAR_ERR BIT_0 /* Queue R2 Parity Error */ -/* B2_CONN_TYP 8 bit Connector type */ -/* B2_PMD_TYP 8 bit PMD type */ +/* Yukon-2 */ +/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ +/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ + /* Bit: 31..30 reserved */ +#define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */ +#define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */ +#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */ +#define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */ +#define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */ +#define Y2_IS_PCI_NEXP BIT_24 /* Bus Abort detected */ + /* Bit: 23..14 reserved */ + /* Link 2 */ +#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */ +#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */ +#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */ +#define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */ +#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */ +#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */ + /* Bit: 9.. 6 reserved */ + /* Link 1 */ +#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */ +#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */ +#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */ +#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */ +#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */ +#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */ + +#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\ + Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1) +#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\ + Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2) + +#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\ + Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP |\ + Y2_HWE_L1_MASK | Y2_HWE_L2_MASK) + +/* B2_CONN_TYP 8 bit Connector type */ +/* B2_PMD_TYP 8 bit PMD type */ /* Values of connector and PMD type comply to SysKonnect internal std */ -/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ +/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ #define CFG_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */ /* Bit 3.. 2: reserved */ #define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */ -#define CFG_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/ +#define CFG_SNG_MAC BIT_0S /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */ -/* B2_CHIP_ID 8 bit Chip Identification Number */ -#define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ -#define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ +/* B2_CHIP_ID 8 bit Chip Identification Number */ +#define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ +#define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ +#define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */ +#define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */ +#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */ +#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ +#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ +#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ -/* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */ -#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address mask */ +#define CHIP_REV_YU_LITE_A1 3 /* Chip Rev. for YUKON-Lite A1,A2 */ +#define CHIP_REV_YU_LITE_A3 7 /* Chip Rev. for YUKON-Lite A3 */ -/* B2_LD_CRTL 8 bit EPROM loader control register */ +#define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ +#define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ +#define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */ +#define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */ + +#define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A0,A1 */ +#define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */ +#define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */ + +#define CHIP_REV_YU_EC_U_A0 1 /* Chip Rev. for Yukon-EC Ultra A0 */ +#define CHIP_REV_YU_EC_U_A1 2 /* Chip Rev. for Yukon-EC Ultra A1 */ + +/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ +#define Y2_STATUS_LNK2_INAC BIT_7S /* Status Link 2 inactiv (0 = activ) */ +#define Y2_CLK_GAT_LNK2_DIS BIT_6S /* Disable PHY clock for Link 2 */ +#define Y2_COR_CLK_LNK2_DIS BIT_5S /* Disable Core clock Link 2 */ +#define Y2_PCI_CLK_LNK2_DIS BIT_4S /* Disable PCI clock Link 2 */ +#define Y2_STATUS_LNK1_INAC BIT_3S /* Status Link 1 inactiv (0 = activ) */ +#define Y2_CLK_GAT_LNK1_DIS BIT_2S /* Disable PHY clock for Link 1 */ +#define Y2_COR_CLK_LNK1_DIS BIT_1S /* Disable Core clock Link 1 */ +#define Y2_PCI_CLK_LNK1_DIS BIT_0S /* Disable PCI clock Link 1 */ + +/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ + /* Bit 7.. 6: reserved */ +#define CFG_PEX_PME_NATIVE BIT_5S /* PCI-E PME native mode select */ +#define CFG_LED_MODE_MSK (7<<2) /* Bit 4.. 2: LED Mode Mask */ +#define CFG_LINK_2_AVAIL BIT_1S /* Link 2 available */ +#define CFG_LINK_1_AVAIL BIT_0S /* Link 1 available */ + +#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) +#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) + +#define CFG_LED_DUAL_ACT_LNK 1 /* Dual LED ACT/LNK mode */ +#define CFG_LED_LINK_MUX_P60 2 /* Link LED on pin 60 (Yukon-EC Ultra) */ + +/* B2_E_3 8 bit lower 4 bits used for HW self test result */ +#define B2_E3_RES_MASK 0x0f + +/* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */ +#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address Mask */ + +/* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */ + /* Bit 31..24: reserved */ +/* Yukon-EC/FE */ +#define Y2_CLK_DIV_VAL_MSK (0xffL<<16) /* Bit 23..16: Clock Divisor Value */ +#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK) +/* Yukon-2 */ +#define Y2_CLK_DIV_VAL2_MSK (7L<<21) /* Bit 23..21: Clock Divisor Value */ +#define Y2_CLK_SELECT2_MSK (0x1fL<<16) /* Bit 20..16: Clock Select */ +#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK) +#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK) + /* Bit 15.. 2: reserved */ +#define Y2_CLK_DIV_ENA BIT_1S /* Enable Core Clock Division */ +#define Y2_CLK_DIV_DIS BIT_0S /* Disable Core Clock Division */ + +/* B2_LD_CTRL 8 bit EPROM loader control register */ /* Bits are currently reserved */ -/* B2_LD_TEST 8 bit EPROM loader test register */ +/* B2_LD_TEST 8 bit EPROM loader test register */ /* Bit 7.. 4: reserved */ #define LD_T_ON BIT_3S /* Loader Test mode on */ #define LD_T_OFF BIT_2S /* Loader Test mode off */ @@ -1132,16 +1476,16 @@ extern "C" { /* * Timer Section */ -/* B2_TI_CRTL 8 bit Timer control */ +/* B2_TI_CTRL 8 bit Timer control */ /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ /* Bit 7.. 3: reserved */ #define TIM_START BIT_2S /* Start Timer */ #define TIM_STOP BIT_1S /* Stop Timer */ #define TIM_CLR_IRQ BIT_0S /* Clear Timer IRQ (!IRQM) */ -/* B2_TI_TEST 8 Bit Timer Test */ +/* B2_TI_TEST 8 Bit Timer Test */ /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ -/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ +/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ /* Bit 7.. 3: reserved */ #define TIM_T_ON BIT_2S /* Test mode on */ #define TIM_T_OFF BIT_1S /* Test mode off */ @@ -1157,9 +1501,6 @@ extern "C" { #define DPT_START BIT_1S /* Start Descriptor Poll Timer */ #define DPT_STOP BIT_0S /* Stop Descriptor Poll Timer */ -/* B2_E_3 8 bit lower 4 bits used for HW self test result */ -#define B2_E3_RES_MASK 0x0f - /* B2_TST_CTRL1 8 bit Test Control Register 1 */ #define TST_FRC_DPERR_MR BIT_7S /* force DATAPERR on MST RD */ #define TST_FRC_DPERR_MW BIT_6S /* force DATAPERR on MST WR */ @@ -1172,24 +1513,24 @@ extern "C" { /* B2_TST_CTRL2 8 bit Test Control Register 2 */ /* Bit 7.. 4: reserved */ - /* force the following error on the next master read/write */ + /* force the following error on the next master read/write */ #define TST_FRC_DPERR_MR64 BIT_3S /* DataPERR RD 64 */ #define TST_FRC_DPERR_MW64 BIT_2S /* DataPERR WR 64 */ #define TST_FRC_APERR_1M64 BIT_1S /* AddrPERR on 1. phase */ #define TST_FRC_APERR_2M64 BIT_0S /* AddrPERR on 2. phase */ -/* B2_GP_IO 32 bit General Purpose I/O Register */ - /* Bit 31..26: reserved */ -#define GP_DIR_9 BIT_25 /* IO_9 direct, 0=I/1=O */ -#define GP_DIR_8 BIT_24 /* IO_8 direct, 0=I/1=O */ -#define GP_DIR_7 BIT_23 /* IO_7 direct, 0=I/1=O */ -#define GP_DIR_6 BIT_22 /* IO_6 direct, 0=I/1=O */ -#define GP_DIR_5 BIT_21 /* IO_5 direct, 0=I/1=O */ -#define GP_DIR_4 BIT_20 /* IO_4 direct, 0=I/1=O */ -#define GP_DIR_3 BIT_19 /* IO_3 direct, 0=I/1=O */ -#define GP_DIR_2 BIT_18 /* IO_2 direct, 0=I/1=O */ -#define GP_DIR_1 BIT_17 /* IO_1 direct, 0=I/1=O */ -#define GP_DIR_0 BIT_16 /* IO_0 direct, 0=I/1=O */ +/* B2_GP_IO 32 bit General Purpose I/O Register */ + /* Bit 31..26: reserved */ +#define GP_DIR_9 BIT_25 /* IO_9 direct, 0=In/1=Out */ +#define GP_DIR_8 BIT_24 /* IO_8 direct, 0=In/1=Out */ +#define GP_DIR_7 BIT_23 /* IO_7 direct, 0=In/1=Out */ +#define GP_DIR_6 BIT_22 /* IO_6 direct, 0=In/1=Out */ +#define GP_DIR_5 BIT_21 /* IO_5 direct, 0=In/1=Out */ +#define GP_DIR_4 BIT_20 /* IO_4 direct, 0=In/1=Out */ +#define GP_DIR_3 BIT_19 /* IO_3 direct, 0=In/1=Out */ +#define GP_DIR_2 BIT_18 /* IO_2 direct, 0=In/1=Out */ +#define GP_DIR_1 BIT_17 /* IO_1 direct, 0=In/1=Out */ +#define GP_DIR_0 BIT_16 /* IO_0 direct, 0=In/1=Out */ /* Bit 15..10: reserved */ #define GP_IO_9 BIT_9 /* IO_9 pin */ #define GP_IO_8 BIT_8 /* IO_8 pin */ @@ -1202,68 +1543,70 @@ extern "C" { #define GP_IO_1 BIT_1 /* IO_1 pin */ #define GP_IO_0 BIT_0 /* IO_0 pin */ -/* B2_I2C_CTRL 32 bit I2C HW Control Register */ +/* B2_I2C_CTRL 32 bit I2C HW Control Register */ #define I2C_FLAG BIT_31 /* Start read/write if WR */ #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */ #define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */ - /* Bit 8.. 5: reserved */ + /* Bit 8.. 5: reserved */ #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ -#define I2C_DEV_SIZE (7L<<1) /* Bit 3.. 1: I2C Device Size */ -#define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smal. */ -#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */ -#define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */ -#define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */ -#define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */ -#define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */ -#define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */ -#define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */ +#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */ +#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smaller */ +#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */ +#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */ +#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */ +#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */ +#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */ +#define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */ +#define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */ #define I2C_STOP BIT_0 /* Interrupt I2C transfer */ -/* B2_I2C_IRQ 32 bit I2C HW IRQ Register */ +/* B2_I2C_IRQ 32 bit I2C HW IRQ Register */ /* Bit 31.. 1 reserved */ #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ -/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */ +/* B2_I2C_SW 32 bit (8 bit access) I2C SW Port Register */ /* Bit 7.. 3: reserved */ #define I2C_DATA_DIR BIT_2S /* direction of I2C_DATA */ -#define I2C_DATA BIT_1S /* I2C Data Port */ -#define I2C_CLK BIT_0S /* I2C Clock Port */ +#define I2C_DATA BIT_1S /* I2C Data Port */ +#define I2C_CLK BIT_0S /* I2C Clock Port */ -/* - * I2C Address - */ -#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address, (Volt and Temp)*/ +/* I2C Address */ +#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */ -/* B2_BSC_CTRL 8 bit Blink Source Counter Control */ +/* B2_BSC_CTRL 8 bit Blink Source Counter Control */ /* Bit 7.. 2: reserved */ #define BSC_START BIT_1S /* Start Blink Source Counter */ #define BSC_STOP BIT_0S /* Stop Blink Source Counter */ -/* B2_BSC_STAT 8 bit Blink Source Counter Status */ +/* B2_BSC_STAT 8 bit Blink Source Counter Status */ /* Bit 7.. 1: reserved */ #define BSC_SRC BIT_0S /* Blink Source, 0=Off / 1=On */ -/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ +/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ #define BSC_T_ON BIT_2S /* Test mode on */ #define BSC_T_OFF BIT_1S /* Test mode off */ #define BSC_T_STEP BIT_0S /* Test step */ +/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ +#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */ +#define PEX_DB_ACCESS BIT_30 /* Access to debug register */ -/* B3_RAM_ADDR 32 bit RAM Address, to read or write */ + +/* B3_RAM_ADDR 32 bit RAM Address, to read or write */ /* Bit 31..19: reserved */ #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ /* RAM Interface Registers */ -/* B3_RI_CTRL 16 bit RAM Iface Control Register */ +/* B3_RI_CTRL 16 bit RAM Interface Control Register */ /* Bit 15..10: reserved */ -#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */ -#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err*/ +#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */ +#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err */ /* Bit 7.. 2: reserved */ #define RI_RST_CLR BIT_1S /* Clear RAM Interface Reset */ #define RI_RST_SET BIT_0S /* Set RAM Interface Reset */ -/* B3_RI_TEST 8 bit RAM Iface Test Register */ +/* B3_RI_TEST 8 bit RAM Iface Test Register */ /* Bit 15.. 4: reserved */ #define RI_T_EV BIT_3S /* Timeout Event occured */ #define RI_T_ON BIT_2S /* Timeout Timer Test On */ @@ -1290,7 +1633,7 @@ extern "C" { #define MA_DIS_REC_RX1 BIT_0S /* Disable Recovery Timer RX1 */ /* Packet Arbiter Registers */ -/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */ +/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */ /* Bit 15..14: reserved */ #define PA_CLR_TO_TX2 BIT_13S /* Clear IRQ Packet Timeout TX2 */ #define PA_CLR_TO_TX1 BIT_12S /* Clear IRQ Packet Timeout TX1 */ @@ -1313,7 +1656,7 @@ extern "C" { /* Rx/Tx Path related Arbiter Test Registers */ /* B3_MA_TO_TEST 16 bit MAC Arbiter Timeout Test Reg */ /* B3_MA_RC_TEST 16 bit MAC Arbiter Recovery Test Reg */ -/* B3_PA_TEST 16 bit Packet Arbiter Test Register */ +/* B3_PA_TEST 16 bit Packet Arbiter Test Register */ /* Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */ #define TX2_T_EV BIT_15S /* TX2 Timeout/Recv Event occured */ #define TX2_T_ON BIT_14S /* TX2 Timeout/Recv Timer Test On */ @@ -1334,14 +1677,14 @@ extern "C" { /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ -/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ -/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ -/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ -/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ +/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ +/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ +/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ +/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ /* Bit 31..24: reserved */ -#define TXA_MAX_VAL 0x00ffffffL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ +#define TXA_MAX_VAL 0x00ffffffUL/* Bit 23.. 0: Max TXA Timer/Cnt Val */ -/* TXA_CTRL 8 bit Tx Arbiter Control Register */ +/* TXA_CTRL 8 bit Tx Arbiter Control Register */ #define TXA_ENA_FSYNC BIT_7S /* Enable force of sync Tx queue */ #define TXA_DIS_FSYNC BIT_6S /* Disable force of sync Tx queue */ #define TXA_ENA_ALLOC BIT_5S /* Enable alloc of free bandwidth */ @@ -1351,7 +1694,7 @@ extern "C" { #define TXA_ENA_ARB BIT_1S /* Enable Tx Arbiter */ #define TXA_DIS_ARB BIT_0S /* Disable Tx Arbiter */ -/* TXA_TEST 8 bit Tx Arbiter Test Register */ +/* TXA_TEST 8 bit Tx Arbiter Test Register */ /* Bit 7.. 6: reserved */ #define TXA_INT_T_ON BIT_5S /* Tx Arb Interval Timer Test On */ #define TXA_INT_T_OFF BIT_4S /* Tx Arb Interval Timer Test Off */ @@ -1360,22 +1703,22 @@ extern "C" { #define TXA_LIM_T_OFF BIT_1S /* Tx Arb Limit Timer Test Off */ #define TXA_LIM_T_STEP BIT_0S /* Tx Arb Limit Timer Step */ -/* TXA_STAT 8 bit Tx Arbiter Status Register */ +/* TXA_STAT 8 bit Tx Arbiter Status Register */ /* Bit 7.. 1: reserved */ #define TXA_PRIO_XS BIT_0S /* sync queue has prio to send */ -/* Q_BC 32 bit Current Byte Counter */ +/* Q_BC 32 bit Current Byte Counter */ /* Bit 31..16: reserved */ #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ -/* BMU Control Status Registers */ -/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ -/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ -/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ -/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ -/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ -/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ -/* Q_CSR 32 bit BMU Control/Status Register */ +/* BMU Control / Status Registers (Yukon and Genesis) */ +/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ +/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ +/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ +/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ +/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ +/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ +/* Q_CSR 32 bit BMU Control/Status Register */ /* Bit 31..25: reserved */ #define CSR_SV_IDLE BIT_24 /* BMU SM Idle */ /* Bit 23..22: reserved */ @@ -1409,28 +1752,63 @@ extern "C" { CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\ CSR_TRANS_RUN) -/* Q_F 32 bit Flag Register */ +/* Rx BMU Control / Status Registers (Yukon-2) */ +#define BMU_IDLE BIT_31 /* BMU Idle State */ +#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */ +#define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */ + /* Bit 28..16: reserved */ +#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */ +#define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */ +#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */ +#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */ +#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */ +#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */ +#define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */ +#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */ +#define BMU_START BIT_8 /* Start Rx/Tx Queue */ +#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */ +#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */ +#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */ +#define BMU_FIFO_RST BIT_4 /* Reset FIFO */ +#define BMU_OP_ON BIT_3 /* BMU Operational On */ +#define BMU_OP_OFF BIT_2 /* BMU Operational Off */ +#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */ +#define BMU_RST_SET BIT_0 /* Set BMU Reset */ + +#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR) +#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | \ + BMU_FIFO_ENA | BMU_OP_ON) + +/* Tx BMU Control / Status Registers (Yukon-2) */ + /* Bit 31: same as for Rx */ + /* Bit 30..14: reserved */ +#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */ +#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */ +#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */ + /* Bit 10..0: same as for Rx */ + +/* Q_F 32 bit Flag Register */ /* Bit 31..28: reserved */ #define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */ #define F_EMPTY BIT_27 /* Tx FIFO: empty flag */ #define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ #define F_WM_REACHED BIT_25 /* Watermark reached */ - /* reserved */ +#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */ #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */ /* Bit 15..11: reserved */ #define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */ -/* Q_T1 32 bit Test Register 1 */ +/* Q_T1 32 bit Test Register 1 */ /* Holds four State Machine control Bytes */ -#define SM_CRTL_SV_MSK (0xffL<<24) /* Bit 31..24: Control Supervisor SM */ -#define SM_CRTL_RD_MSK (0xffL<<16) /* Bit 23..16: Control Read Desc SM */ -#define SM_CRTL_WR_MSK (0xffL<<8) /* Bit 15.. 8: Control Write Desc SM */ -#define SM_CRTL_TR_MSK 0xffL /* Bit 7.. 0: Control Transfer SM */ +#define SM_CTRL_SV_MSK (0xffL<<24) /* Bit 31..24: Control Supervisor SM */ +#define SM_CTRL_RD_MSK (0xffL<<16) /* Bit 23..16: Control Read Desc SM */ +#define SM_CTRL_WR_MSK (0xffL<<8) /* Bit 15.. 8: Control Write Desc SM */ +#define SM_CTRL_TR_MSK 0xffL /* Bit 7.. 0: Control Transfer SM */ -/* Q_T1_TR 8 bit Test Register 1 Transfer SM */ -/* Q_T1_WR 8 bit Test Register 1 Write Descriptor SM */ -/* Q_T1_RD 8 bit Test Register 1 Read Descriptor SM */ -/* Q_T1_SV 8 bit Test Register 1 Supervisor SM */ +/* Q_T1_TR 8 bit Test Register 1 Transfer SM */ +/* Q_T1_WR 8 bit Test Register 1 Write Descriptor SM */ +/* Q_T1_RD 8 bit Test Register 1 Read Descriptor SM */ +/* Q_T1_SV 8 bit Test Register 1 Supervisor SM */ /* The control status byte of each machine looks like ... */ #define SM_STATE 0xf0 /* Bit 7.. 4: State which shall be loaded */ @@ -1440,7 +1818,7 @@ extern "C" { #define SM_STEP BIT_0S /* Step the State Machine */ /* The encoding of the states is not supported by the Diagnostics Tool */ -/* Q_T2 32 bit Test Register 2 */ +/* Q_T2 32 bit Test Register 2 */ /* Bit 31.. 8: reserved */ #define T2_AC_T_ON BIT_7 /* Address Counter Test Mode on */ #define T2_AC_T_OFF BIT_6 /* Address Counter Test Mode off */ @@ -1451,45 +1829,52 @@ extern "C" { #define T2_STEP02 BIT_1 /* Inc AC/Dec BC by 2 */ #define T2_STEP01 BIT_0 /* Inc AC/Dec BC by 1 */ -/* Q_T3 32 bit Test Register 3 */ +/* Q_T3 32 bit Test Register 3 */ /* Bit 31.. 7: reserved */ #define T3_MUX_MSK (7<<4) /* Bit 6.. 4: Mux Position */ /* Bit 3: reserved */ #define T3_VRAM_MSK 7 /* Bit 2.. 0: Virtual RAM Buffer Address */ +/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/ +/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */ +#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */ +#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */ +#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */ +#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */ + /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ -/* RB_START 32 bit RAM Buffer Start Address */ -/* RB_END 32 bit RAM Buffer End Address */ -/* RB_WP 32 bit RAM Buffer Write Pointer */ -/* RB_RP 32 bit RAM Buffer Read Pointer */ -/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ -/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ -/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ -/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ -/* RB_PC 32 bit RAM Buffer Packet Counter */ -/* RB_LEV 32 bit RAM Buffer Level Register */ +/* RB_START 32 bit RAM Buffer Start Address */ +/* RB_END 32 bit RAM Buffer End Address */ +/* RB_WP 32 bit RAM Buffer Write Pointer */ +/* RB_RP 32 bit RAM Buffer Read Pointer */ +/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ +/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ +/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ +/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ +/* RB_PC 32 bit RAM Buffer Packet Counter */ +/* RB_LEV 32 bit RAM Buffer Level Register */ /* Bit 31..19: reserved */ #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ /* RB_TST2 8 bit RAM Buffer Test Register 2 */ - /* Bit 7.. 4: reserved */ -#define RB_PC_DEC BIT_3S /* Packet Counter Decrem */ + /* Bit 7.. 4: reserved */ +#define RB_PC_DEC BIT_3S /* Packet Counter Decrement */ #define RB_PC_T_ON BIT_2S /* Packet Counter Test On */ -#define RB_PC_T_OFF BIT_1S /* Packet Counter Tst Off */ -#define RB_PC_INC BIT_0S /* Packet Counter Increm */ +#define RB_PC_T_OFF BIT_1S /* Packet Counter Test Off */ +#define RB_PC_INC BIT_0S /* Packet Counter Increment */ /* RB_TST1 8 bit RAM Buffer Test Register 1 */ /* Bit 7: reserved */ #define RB_WP_T_ON BIT_6S /* Write Pointer Test On */ #define RB_WP_T_OFF BIT_5S /* Write Pointer Test Off */ -#define RB_WP_INC BIT_4S /* Write Pointer Increm */ +#define RB_WP_INC BIT_4S /* Write Pointer Increment */ /* Bit 3: reserved */ #define RB_RP_T_ON BIT_2S /* Read Pointer Test On */ #define RB_RP_T_OFF BIT_1S /* Read Pointer Test Off */ -#define RB_RP_DEC BIT_0S /* Read Pointer Decrement */ +#define RB_RP_INC BIT_0S /* Read Pointer Increment */ /* RB_CTRL 8 bit RAM Buffer Control Register */ - /* Bit 7.. 6: reserved */ + /* Bit 7.. 6: reserved */ #define RB_ENA_STFWD BIT_5S /* Enable Store & Forward */ #define RB_DIS_STFWD BIT_4S /* Disable Store & Forward */ #define RB_ENA_OP_MD BIT_3S /* Enable Operation Mode */ @@ -1497,20 +1882,35 @@ extern "C" { #define RB_RST_CLR BIT_1S /* Clear RAM Buf STM Reset */ #define RB_RST_SET BIT_0S /* Set RAM Buf STM Reset */ +/* Yukon-2 */ + /* Bit 31..20: reserved */ +#define RB_CNT_DOWN BIT_19 /* Packet Counter Decrement */ +#define RB_CNT_TST_ON BIT_18 /* Packet Counter Test On */ +#define RB_CNT_TST_OFF BIT_17 /* Packet Counter Test Off */ +#define RB_CNT_UP BIT_16 /* Packet Counter Increment */ + /* Bit 15: reserved */ +#define RB_WP_TST_ON BIT_14 /* Write Pointer Test On */ +#define RB_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ +#define RB_WP_UP BIT_12 /* Write Pointer Increment */ + /* Bit 11: reserved */ +#define RB_RP_TST_ON BIT_10 /* Read Pointer Test On */ +#define RB_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ +#define RB_RP_UP BIT_8 /* Read Pointer Increment */ + /* Receive and Transmit MAC FIFO Registers (GENESIS only) */ -/* RX_MFF_EA 32 bit Receive MAC FIFO End Address */ -/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */ -/* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */ -/* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter */ -/* RX_MFF_LEV 32 bit Receive MAC FIFO Level */ -/* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */ -/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */ -/* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pointer */ -/* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */ -/* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */ -/* TX_MFF_LEV 32 bit Transmit MAC FIFO Level */ +/* RX_MFF_EA 32 bit Receive MAC FIFO End Address */ +/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */ +/* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */ +/* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter */ +/* RX_MFF_LEV 32 bit Receive MAC FIFO Level */ +/* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */ +/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */ +/* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pointer */ +/* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */ +/* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */ +/* TX_MFF_LEV 32 bit Transmit MAC FIFO Level */ /* Bit 31.. 6: reserved */ #define MFF_MSK 0x007fL /* Bit 5.. 0: MAC FIFO Address/Ptr Bits */ @@ -1556,9 +1956,9 @@ extern "C" { /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */ /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */ /* Bit 7: reserved */ -#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Ptr TestOn */ -#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Ptr TstOff */ -#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Ptr Increment */ +#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Pointer Test On */ +#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Pointer Test Off */ +#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Pointer Increment */ #define MFF_PC_DEC BIT_3S /* Packet Counter Decrement */ #define MFF_PC_T_ON BIT_2S /* Packet Counter Test On */ #define MFF_PC_T_OFF BIT_1S /* Packet Counter Test Off */ @@ -1569,7 +1969,7 @@ extern "C" { /* Bit 7: reserved */ #define MFF_WP_T_ON BIT_6S /* Write Pointer Test On */ #define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */ -#define MFF_WP_INC BIT_4S /* Write Pointer Increm */ +#define MFF_WP_INC BIT_4S /* Write Pointer Increment */ /* Bit 3: reserved */ #define MFF_RP_T_ON BIT_2S /* Read Pointer Test On */ #define MFF_RP_T_OFF BIT_1S /* Read Pointer Test Off */ @@ -1588,12 +1988,16 @@ extern "C" { /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */ /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */ + /* Bit 7.. 3: reserved */ +#define LED_START BIT_2S /* Start Counter */ +#define LED_STOP BIT_1S /* Stop Counter */ +#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED On */ + /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */ /* Bit 7.. 3: reserved */ -#define LED_START BIT_2S /* Start Timer */ -#define LED_STOP BIT_1S /* Stop Timer */ -#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED on */ -#define LED_CLR_IRQ BIT_0S /* Lnk: Clear Link IRQ */ +#define LNK_START BIT_2S /* Start Counter */ +#define LNK_STOP BIT_1S /* Stop Counter */ +#define LNK_CLR_IRQ BIT_0S /* Clear Link IRQ */ /* RX_LED_TST 8 bit Receive LED Cnt Test Register */ /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */ @@ -1604,86 +2008,142 @@ extern "C" { #define LED_T_STEP BIT_0S /* LED Counter Step */ /* LNK_LED_REG 8 bit Link LED Register */ - /* Bit 7.. 6: reserved */ + /* Bit 7.. 6: reserved */ #define LED_BLK_ON BIT_5S /* Link LED Blinking On */ #define LED_BLK_OFF BIT_4S /* Link LED Blinking Off */ #define LED_SYNC_ON BIT_3S /* Use Sync Wire to switch LED */ #define LED_SYNC_OFF BIT_2S /* Disable Sync Wire Input */ -#define LED_ON BIT_1S /* switch LED on */ -#define LED_OFF BIT_0S /* switch LED off */ +#define LED_ON BIT_1S /* Switch LED On */ +#define LED_OFF BIT_0S /* Switch LED Off */ /* Receive and Transmit GMAC FIFO Registers (YUKON only) */ /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */ /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */ -/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ -/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ -/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ -/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ +/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ +/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ +/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ +/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ -/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ -/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Ptr. */ -/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ -/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ -/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ -/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ +/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ +/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */ +/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ +/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ +/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ +/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ - /* Bits 31..15: reserved */ -#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ -#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ -#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ + /* Bit 31..28 reserved */ +#define RX_TRUNC_ON BIT_27 /* Enable Packet Truncation */ +#define RX_TRUNC_OFF BIT_26 /* Disable Packet Truncation */ +#define RX_VLAN_STRIP_ON BIT_25 /* Enable VLAN Stripping */ +#define RX_VLAN_STRIP_OFF BIT_24 /* Disable VLAN Stripping */ + /* Bit 23..15 reserved */ +#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ +#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ +#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ /* Bit 11: reserved */ -#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ -#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ -#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ -#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ -#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ -#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ -#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ -#define GMF_OPER_ON BIT_3 /* Operational Mode On */ -#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ -#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ -#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ +#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ +#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ +#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ +#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ +#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ +#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ +#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ +#define GMF_OPER_ON BIT_3 /* Operational Mode On */ +#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ +#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ +#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ -/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ - /* Bits 31..19: reserved */ -#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ -#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ -#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ - /* Bits 15..7: same as for RX_GMF_CTRL_T */ -#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ -#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ -#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ +/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */ +#define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */ +#define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */ + /* Bits 29..26: reserved */ +#define TX_VLAN_TAG_ON BIT_25 /* Enable VLAN tagging */ +#define TX_VLAN_TAG_OFF BIT_24 /* Disable VLAN tagging */ +#define TX_PCI_JUM_ENA BIT_23 /* Enable PCI Jumbo Mode (Yukon-EC Ultra) */ +#define TX_PCI_JUM_DIS BIT_22 /* Disable PCI Jumbo Mode (Yukon-EC Ultra) */ + /* Bits 21..19: reserved */ +#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ +#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ +#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ + /* Bits 15..8: same as for RX_GMF_CTRL_T */ + /* Bit 7: reserved */ +#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ +#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ +#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ /* Bits 3..0: same as for RX_GMF_CTRL_T */ #define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) #define GMF_TX_CTRL_DEF GMF_OPER_ON +#define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */ #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ -/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ - /* Bit 7.. 3: reserved */ -#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */ -#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */ -#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */ +/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ + /* Bit 7.. 3: reserved */ +#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */ +#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */ +#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */ +/* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */ + /* Bit 31.. 6: reserved */ +#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */ +#define PC_POLL_RQ BIT_4 /* Poll Request Start */ +#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */ +#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */ +#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */ +#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */ + + +/* The bit definition of the following registers is still missing! */ +/* B28_Y2_SMB_CONFIG 32 bit ASF SMBus Config Register */ +/* B28_Y2_SMB_CSD_REG 32 bit ASF SMB Control/Status/Data */ +/* B28_Y2_ASF_IRQ_V_BASE 32 bit ASF IRQ Vector Base */ + +/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ +/* This register is used by the host driver software */ + /* Bit 31.. 5 reserved */ +#define Y2_ASF_OS_PRES BIT_4S /* ASF operation system present */ +#define Y2_ASF_RESET BIT_3S /* ASF system in reset state */ +#define Y2_ASF_RUNNING BIT_2S /* ASF system operational */ +#define Y2_ASF_CLR_HSTI BIT_1S /* Clear ASF IRQ */ +#define Y2_ASF_IRQ BIT_0S /* Issue an IRQ to ASF system */ + +#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */ +#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */ + +/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ +/* This register is used by the ASF firmware */ + /* Bit 31.. 2 reserved */ +#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */ +#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */ + + +/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ + /* Bit 7.. 5: reserved */ +#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */ +#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */ +#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */ +#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */ +#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */ + /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ /* Bits 31.. 8: reserved */ -#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ -#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ -#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ -#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ -#define GMC_PAUSE_ON BIT_3 /* Pause On */ -#define GMC_PAUSE_OFF BIT_2 /* Pause Off */ -#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ -#define GMC_RST_SET BIT_0 /* Set GMAC Reset */ +#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ +#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ +#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ +#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ +#define GMC_PAUSE_ON BIT_3 /* Pause On */ +#define GMC_PAUSE_OFF BIT_2 /* Pause Off */ +#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ +#define GMC_RST_SET BIT_0 /* Set GMAC Reset */ /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ /* Bits 31..29: reserved */ #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ -#define GPC_INT_POL_HI BIT_27 /* IRQ Polarity is Active HIGH */ +#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */ #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ @@ -1698,15 +2158,24 @@ extern "C" { #define GPC_ANEG_2 BIT_15 /* ANEG[2] */ #define GPC_ANEG_1 BIT_14 /* ANEG[1] */ #define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ -#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ -#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ -#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ -#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ -#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ +#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of PHY Addr */ +#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of PHY Addr */ +#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of PHY Addr */ +#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of PHY Addr */ +#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of PHY Addr */ /* Bits 7..2: reserved */ #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ #define GPC_RST_SET BIT_0 /* Set GPHY Reset */ +/* Yukon-EC Ultra only */ +#define GPC_LED_CONF_MSK (7<<6) /* Bit 8.. 6: GPHY LED Config */ +#define GPC_PD_125M_CLK_OFF BIT_5 /* Disable Power Down Clock 125 MHz */ +#define GPC_PD_125M_CLK_ON BIT_4 /* Enable Power Down Clock 125 MHz */ +#define GPC_DPLL_RST_SET BIT_3 /* Set GPHY's DPLL Reset */ +#define GPC_DPLL_RST_CLR BIT_2 /* Clear GPHY's DPLL Reset */ + /* (DPLL = Digital Phase Lock Loop) */ +#define GPC_LED_CONF_VAL(x) (SHIFT6(x) & GPC_LED_CONF_MSK) + #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | \ GPC_HWCFG_M_1 | GPC_HWCFG_M_0) @@ -1737,23 +2206,23 @@ extern "C" { /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ -#define GM_IS_TX_CO_OV BIT_5 /* Transmit Counter Overflow IRQ */ -#define GM_IS_RX_CO_OV BIT_4 /* Receive Counter Overflow IRQ */ -#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ -#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ -#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ -#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ +#define GM_IS_RX_CO_OV BIT_5S /* Receive Counter Overflow IRQ */ +#define GM_IS_TX_CO_OV BIT_4S /* Transmit Counter Overflow IRQ */ +#define GM_IS_TX_FF_UR BIT_3S /* Transmit FIFO Underrun */ +#define GM_IS_TX_COMPL BIT_2S /* Frame Transmission Complete */ +#define GM_IS_RX_FF_OR BIT_1S /* Receive FIFO Overrun */ +#define GM_IS_RX_COMPL BIT_0S /* Frame Reception Complete */ -#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | \ +#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | \ GM_IS_TX_FF_UR) -/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ +/* GMAC_LINK_CTRL 16 bit Link Control Reg (YUKON only) */ /* Bits 15.. 2: reserved */ -#define GMLC_RST_CLR BIT_1S /* Clear GMAC Link Reset */ -#define GMLC_RST_SET BIT_0S /* Set GMAC Link Reset */ +#define GMLC_RST_CLR BIT_1S /* Clear Link Reset */ +#define GMLC_RST_SET BIT_0S /* Set Link Reset */ -/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ +/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ #define WOL_CTL_LINK_CHG_OCC BIT_15S #define WOL_CTL_MAGIC_PKT_OCC BIT_14S #define WOL_CTL_PATTERN_OCC BIT_13S @@ -1776,15 +2245,19 @@ extern "C" { #define WOL_CTL_DEFAULT \ (WOL_CTL_DIS_PME_ON_LINK_CHG | \ - WOL_CTL_DIS_PME_ON_PATTERN | \ - WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ - WOL_CTL_DIS_LINK_CHG_UNIT | \ - WOL_CTL_DIS_PATTERN_UNIT | \ - WOL_CTL_DIS_MAGIC_PKT_UNIT) + WOL_CTL_DIS_PME_ON_PATTERN | \ + WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ + WOL_CTL_DIS_LINK_CHG_UNIT | \ + WOL_CTL_DIS_PATTERN_UNIT | \ + WOL_CTL_DIS_MAGIC_PKT_UNIT) -/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ +/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) +/* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */ +#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */ +#define WOL_PATT_MATCH_PME_ALL 0x7f + #define SK_NUM_WOL_PATTERN 7 #define SK_PATTERN_PER_WORD 4 #define SK_BITMASK_PATTERN 7 @@ -1794,60 +2267,296 @@ extern "C" { #define WOL_LENGTH_SHIFT 8 +/* typedefs ******************************************************************/ + /* Receive and Transmit Descriptors ******************************************/ /* Transmit Descriptor struct */ typedef struct s_HwTxd { SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */ SK_U32 TxNext; /* Physical Address Pointer to the next TxD */ - SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower dword */ - SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper dword */ + SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower DWord */ + SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper DWord */ SK_U32 TxStat; /* Transmit Frame Status Word */ -#ifndef SK_USE_REV_DESC +#ifndef SK_USE_REV_DESC SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */ SK_U16 TxRes1; /* 16 bit reserved field */ SK_U16 TxTcpWp; /* TCP Checksum Write Position */ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ -#else /* SK_USE_REV_DESC */ +#else /* SK_USE_REV_DESC */ SK_U16 TxRes1; /* 16 bit reserved field */ SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ SK_U16 TxTcpWp; /* TCP Checksum Write Position */ -#endif /* SK_USE_REV_DESC */ +#endif /* SK_USE_REV_DESC */ SK_U32 TxRes2; /* 32 bit reserved field */ -} SK_HWTXD; +} __attribute__ ((packed)) SK_HWTXD; /* Marvell - uboot: should be packed */ /* Receive Descriptor struct */ typedef struct s_HwRxd { SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */ SK_U32 RxNext; /* Physical Address Pointer to the next RxD */ - SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower dword */ - SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper dword */ + SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower DWord */ + SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper DWord */ SK_U32 RxStat; /* Receive Frame Status Word */ SK_U32 RxTiSt; /* Receive Time Stamp (from XMAC on GENESIS) */ -#ifndef SK_USE_REV_DESC - SK_U16 RxTcpSum1; /* TCP Checksum 1 */ - SK_U16 RxTcpSum2; /* TCP Checksum 2 */ +#ifndef SK_USE_REV_DESC + SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */ + SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ -#else /* SK_USE_REV_DESC */ - SK_U16 RxTcpSum2; /* TCP Checksum 2 */ - SK_U16 RxTcpSum1; /* TCP Checksum 1 */ +#else /* SK_USE_REV_DESC */ + SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */ + SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ -#endif /* SK_USE_REV_DESC */ -} SK_HWRXD; +#endif /* SK_USE_REV_DESC */ +} __attribute__ ((packed)) SK_HWRXD;/* Marvell - uboot: should be packed */ /* * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2) * should set the define SK_USE_REV_DESC. - * Structures are 'normaly' not endianess dependent. But in - * this case the SK_U16 fields are bound to bit positions inside the - * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord. + * Structures are 'normally' not endianess dependent. But in this case + * the SK_U16 fields are bound to bit positions inside the descriptor. + * RxTcpSum1 e.g. must start at bit 0 within the 7.th DWord. * The bit positions inside a DWord are of course endianess dependent and - * swaps if the DWord is swapped by the hardware. + * swap if the DWord is swapped by the hardware. */ +/* YUKON-2 descriptors ******************************************************/ + +typedef struct _TxChksum { +#ifndef SK_USE_REV_DESC + SK_U16 TxTcpWp; /* TCP Checksum Write Position */ + SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ +#else /* SK_USE_REV_DESC */ + SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ + SK_U16 TxTcpWp; /* TCP Checksum Write Position */ +#endif /* SK_USE_REV_DESC */ +} __attribute__ ((packed)) SK_HWTXCS;/* Marvell - uboot: should be packed */ + +typedef struct _LargeSend { +#ifndef SK_USE_REV_DESC + SK_U16 Length; /* Large Send Segment Length */ + SK_U16 Reserved; /* reserved */ +#else /* SK_USE_REV_DESC */ + SK_U16 Reserved; /* reserved */ + SK_U16 Length; /* Large Send Segment Length */ +#endif /* SK_USE_REV_DESC */ +} __attribute__ ((packed)) SK_HWTXLS;/* Marvell - uboot: should be packed */ + +typedef union u_HwTxBuf { + SK_U16 BufLen; /* Tx Buffer Length */ + SK_U16 VlanTag; /* VLAN Tag */ + SK_U16 InitCsum; /* Init. Checksum */ +} __attribute__ ((packed)) SK_HWTXBUF;/* Marvell - uboot: should be packed */ + + +/* Tx List Element structure */ +typedef struct s_HwLeTx { + union { + SK_U32 BufAddr; /* Tx LE Buffer Address high/low */ + SK_HWTXCS ChkSum; /* Tx LE TCP Checksum parameters */ + SK_HWTXLS LargeSend;/* Large Send length */ + } __attribute__ ((packed)) TxUn;/* Marvell - uboot: should be packed */ +#ifndef SK_USE_REV_DESC + SK_HWTXBUF Send; + SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */ + SK_U8 Opcode; /* Tx LE Opcode field */ +#else /* SK_USE_REV_DESC */ + SK_U8 Opcode; /* Tx LE Opcode field */ + SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */ + SK_HWTXBUF Send; +#endif /* SK_USE_REV_DESC */ +} __attribute__ ((packed)) SK_HWLETX;/* Marvell - uboot: should be packed */ + +typedef struct _RxChkSum{ +#ifndef SK_USE_REV_DESC + SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ + SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ +#else /* SK_USE_REV_DESC */ + SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ + SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ +#endif /* SK_USE_REV_DESC */ +} __attribute__ ((packed)) SK_HWRXCS;/* Marvell - uboot: should be packed */ + +/* Rx List Element structure */ +typedef struct s_HwLeRx { + union { + SK_U32 BufAddr; /* Rx LE Buffer Address high/low */ + SK_HWRXCS ChkSum; /* Rx LE TCP Checksum parameters */ + } __attribute__ ((packed))RxUn;/* Marvell - uboot: should be packed */ +#ifndef SK_USE_REV_DESC + SK_U16 BufferLength; /* Rx LE Buffer Length field */ + SK_U8 ControlFlags; /* Rx LE Control field */ + SK_U8 Opcode; /* Rx LE Opcode field */ +#else /* SK_USE_REV_DESC */ + SK_U8 Opcode; /* Rx LE Opcode field */ + SK_U8 ControlFlags; /* Rx LE Control field */ + SK_U16 BufferLength; /* Rx LE Buffer Length field */ +#endif /* SK_USE_REV_DESC */ +} __attribute__ ((packed)) SK_HWLERX;/* Marvell - uboot: should be packed */ + +typedef struct s_StRxTCPChkSum { +#ifndef SK_USE_REV_DESC + SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */ + SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */ +#else /* SK_USE_REV_DESC */ + SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */ + SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */ +#endif /* SK_USE_REV_DESC */ +} __attribute__ ((packed)) SK_HWSTCS;/* Marvell - uboot: should be packed */ + +typedef struct s_StRxRssFlags { +#ifndef SK_USE_REV_DESC + SK_U8 FlagField; /* contains TCP and IP flags */ + SK_U8 reserved; /* reserved */ +#else /* SK_USE_REV_DESC */ + SK_U8 reserved; /* reserved */ + SK_U8 FlagField; /* contains TCP and IP flags */ +#endif /* SK_USE_REV_DESC */ +} __attribute__ ((packed)) SK_HWSTRSS;/* Marvell - uboot: should be packed */ + +/* bit definition of RSS LE bit 32/33 (SK_HWSTRSS.FlagField) */ + /* bit 7..2 reserved */ +#define RSS_TCP_FLAG BIT_1S /* RSS value related to TCP area */ +#define RSS_IP_FLAG BIT_0S /* RSS value related to IP area */ +/* StRxRssValue is valid if at least RSS_IP_FLAG is set */ +/* For protocol errors or other protocols an empty RSS LE is generated */ + +typedef union u_HwStBuf { + SK_U16 BufLen; /* Rx Buffer Length */ + SK_U16 VlanTag; /* VLAN Tag */ + SK_U16 StTxStatHi; /* Tx Queue Status (high) */ + SK_HWSTRSS Rss; /* Flag Field for TCP and IP protocol */ +} __attribute__ ((packed)) SK_HWSTBUF;/* Marvell - uboot: should be packed */ + +/* Status List Element structure */ +typedef struct s_HwLeSt { + union { + SK_U32 StRxStatWord; /* Rx Status Dword */ + SK_U32 StRxTimeStamp; /* Rx Timestamp */ + SK_HWSTCS StRxTCPCSum; /* Rx TCP Checksum */ + SK_U32 StTxStatLow; /* Tx Queue Status (low) */ + SK_U32 StRxRssValue; /* Rx RSS value */ + } __attribute__ ((packed)) StUn;/* Marvell - uboot: should be packed */ +#ifndef SK_USE_REV_DESC + SK_HWSTBUF Stat; + SK_U8 Link; /* Status LE Link field */ + SK_U8 Opcode; /* Status LE Opcode field */ +#else /* SK_USE_REV_DESC */ + SK_U8 Opcode; /* Status LE Opcode field */ + SK_U8 Link; /* Status LE Link field */ + SK_HWSTBUF Stat; +#endif /* SK_USE_REV_DESC */ +} __attribute__ ((packed)) SK_HWLEST;/* Marvell - uboot: should be packed */ + +/* Special Action List Element */ +typedef struct s_HwLeSa { +#ifndef SK_USE_REV_DESC + SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */ + SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */ + SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */ + SK_U8 Link; /* Special Action LE Link field */ + SK_U8 Opcode; /* Special Action LE Opcode field */ +#else /* SK_USE_REV_DESC */ + SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */ + SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */ + SK_U8 Opcode; /* Special Action LE Opcode field */ + SK_U8 Link; /* Special Action LE Link field */ + SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */ +#endif /* SK_USE_REV_DESC */ +} __attribute__ ((packed)) SK_HWLESA;/* Marvell - uboot: should be packed */ + +/* Common List Element union */ +typedef union u_HwLeTxRxSt { + /* Transmit List Element Structure */ + SK_HWLETX Tx; + /* Receive List Element Structure */ + SK_HWLERX Rx; + /* Status List Element Structure */ + SK_HWLEST St; + /* Special Action List Element Structure */ + SK_HWLESA Sa; + /* Full List Element */ + SK_U64 Full; +} SK_HWLE;__attribute__ ((packed)) SK_HWLE;/* Marvell - uboot: should be packed */ + +/* mask and shift value to get Tx async queue status for port 1 */ +#define STLE_TXA1_MSKL 0x00000fff +#define STLE_TXA1_SHIFTL 0 + +/* mask and shift value to get Tx sync queue status for port 1 */ +#define STLE_TXS1_MSKL 0x00fff000 +#define STLE_TXS1_SHIFTL 12 + +/* mask and shift value to get Tx async queue status for port 2 */ +#define STLE_TXA2_MSKL 0xff000000 +#define STLE_TXA2_SHIFTL 24 +#define STLE_TXA2_MSKH 0x000f +/* this one shifts up */ +#define STLE_TXA2_SHIFTH 8 + +/* mask and shift value to get Tx sync queue status for port 2 */ +#define STLE_TXS2_MSKL 0x00000000 +#define STLE_TXS2_SHIFTL 0 +#define STLE_TXS2_MSKH 0xfff0 +#define STLE_TXS2_SHIFTH 4 + +/* YUKON-2 bit values */ +#define HW_OWNER BIT_7 +#define SW_OWNER 0 + +#define PU_PUTIDX_VALID BIT_12 + +/* YUKON-2 Control flags */ +#define UDPTCP BIT_0S +#define CALSUM BIT_1S +#define WR_SUM BIT_2S +#define INIT_SUM BIT_3S +#define LOCK_SUM BIT_4S +#define INS_VLAN BIT_5S +#define FRC_STAT BIT_6S +#define EOP BIT_7S + +#define TX_LOCK BIT_8S +#define BUF_SEND BIT_9S +#define PACKET_SEND BIT_10S + +#define NO_WARNING BIT_14S +#define NO_UPDATE BIT_15S + +/* YUKON-2 Rx/Tx opcodes defines */ +#define OP_TCPWRITE 0x11 +#define OP_TCPSTART 0x12 +#define OP_TCPINIT 0x14 +#define OP_TCPLCK 0x18 +#define OP_TCPCHKSUM OP_TCPSTART +#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART) +#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE) +#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE) +#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE) +#define OP_ADDR64 0x21 +#define OP_VLAN 0x22 +#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) +#define OP_LRGLEN 0x24 +#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) +#define OP_BUFFER 0x40 +#define OP_PACKET 0x41 +#define OP_LARGESEND 0x43 + +/* YUKON-2 STATUS opcodes defines */ +#define OP_RXSTAT 0x60 +#define OP_RXTIMESTAMP 0x61 +#define OP_RXVLAN 0x62 +#define OP_RXCHKS 0x64 +#define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN) +#define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN) +#define OP_RSS_HASH 0x65 +#define OP_TXINDEXLE 0x68 + +/* YUKON-2 SPECIAL opcodes defines */ +#define OP_PUTIDX 0x70 /* Descriptor Bit Definition */ /* TxCtrl Transmit Buffer Control Field */ @@ -1869,7 +2578,7 @@ typedef struct s_HwRxd { #define BMU_CHECK (0x55L<<16) /* Default BMU check */ #define BMU_TCP_CHECK (0x56L<<16) /* Descr with TCP ext */ #define BMU_UDP_CHECK (0x57L<<16) /* Descr with UDP ext (YUKON only) */ -#define BMU_BBC 0xFFFFL /* Bit 15.. 0: Buffer Byte Counter */ +#define BMU_BBC 0xffffL /* Bit 15.. 0: Buffer Byte Counter */ /* TxStat Transmit Frame Status Word */ /* RxStat Receive Frame Status Word */ @@ -1880,20 +2589,13 @@ typedef struct s_HwRxd { * (see XMR_FS bits) */ -/* other defines *************************************************************/ - -/* - * FlashProm specification - */ -#define MAX_PAGES 0x20000L /* Every byte has a single page */ -#define MAX_FADDR 1 /* 1 byte per page */ -#define SKFDDI_PSZ 8 /* address PROM size */ - /* macros ********************************************************************/ -/* - * Receive and Transmit Queues - */ +/* Macro for accessing the key registers */ +#define RSS_KEY_ADDR(Port, KeyIndex) \ + ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex)) + +/* Receive and Transmit Queues */ #define Q_R1 0x0000 /* Receive Queue 1 */ #define Q_R2 0x0080 /* Receive Queue 2 */ #define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ @@ -1901,6 +2603,10 @@ typedef struct s_HwRxd { #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ +#define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */ +#define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */ +#define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */ +#define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */ /* * Macro Q_ADDR() * @@ -1912,10 +2618,26 @@ typedef struct s_HwRxd { * Offs Queue register offset. * Values: Q_D, Q_DA_L ... Q_T2, Q_T3 * - * usage SK_IN32(pAC, Q_ADDR(Q_R2, Q_BC), pVal) + * usage SK_IN32(IoC, Q_ADDR(Q_R2, Q_BC), pVal) */ #define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) +/* + * Macro Y2_PREF_Q_ADDR() + * + * Use this macro to access the Prefetch Units of the receive and + * transmit queues of Yukon-2. + * + * para: + * Queue Queue to access. + * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, Q_XA2, + * Offs Queue register offset. + * Values: PREF_UNIT_CTRL_REG ... PREF_UNIT_FIFO_LEV_REG + * + * usage SK_IN16(IoC, Y2_Q_ADDR(Q_R2, PREF_UNIT_GET_IDX_REG), pVal) + */ +#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs)) + /* * Macro RB_ADDR() * @@ -1927,16 +2649,14 @@ typedef struct s_HwRxd { * Offs Queue register offset. * Values: RB_START, RB_END ... RB_LEV, RB_CTRL * - * usage SK_IN32(pAC, RB_ADDR(Q_R2, RB_RP), pVal) + * usage SK_IN32(IoC, RB_ADDR(Q_R2, RB_RP), pVal) */ #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) -/* - * MAC Related Registers - */ -#define MAC_1 0 /* belongs to the port near the slot */ -#define MAC_2 1 /* belongs to the port far away from the slot */ +/* MAC Related Registers */ +#define MAC_1 0 /* 1st port */ +#define MAC_2 1 /* 2nd port */ /* * Macro MR_ADDR() @@ -1950,19 +2670,10 @@ typedef struct s_HwRxd { * Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG, * TX_MFF_EA, TX_MFF_WP ... TX_LED_TST * - * usage SK_IN32(pAC, MR_ADDR(MAC_1, TX_MFF_EA), pVal) + * usage SK_IN32(IoC, MR_ADDR(MAC_1, TX_MFF_EA), pVal) */ #define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) -#ifdef SK_LITTLE_ENDIAN -#define XM_WORD_LO 0 -#define XM_WORD_HI 1 -#else /* !SK_LITTLE_ENDIAN */ -#define XM_WORD_LO 1 -#define XM_WORD_HI 0 -#endif /* !SK_LITTLE_ENDIAN */ - - /* * macros to access the XMAC (GENESIS only) * @@ -1987,22 +2698,31 @@ typedef struct s_HwRxd { #define XMA(Mac, Reg) \ ((BASE_XMAC_1 + (Mac) * (BASE_XMAC_2 - BASE_XMAC_1)) | ((Reg) << 1)) -#define XM_IN16(IoC, Mac, Reg, pVal) \ - SK_IN16((IoC), XMA((Mac), (Reg)), (pVal)) +#define XM_IN16(IoC, Mac, Reg, pVal) \ + SK_IN16(IoC, XMA(Mac, Reg), pVal) -#define XM_OUT16(IoC, Mac, Reg, Val) \ - SK_OUT16((IoC), XMA((Mac), (Reg)), (Val)) +#define XM_OUT16(IoC, Mac, Reg, Val) \ + SK_OUT16(IoC, XMA(Mac, Reg), Val) -#define XM_IN32(IoC, Mac, Reg, pVal) { \ - SK_IN16((IoC), XMA((Mac), (Reg)), \ - (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_LO]); \ - SK_IN16((IoC), XMA((Mac), (Reg+2)), \ - (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_HI]); \ +#ifdef SK_LITTLE_ENDIAN + +#define XM_IN32(IoC, Mac, Reg, pVal) { \ + SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal)); \ + SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal) + 1); \ } +#else /* !SK_LITTLE_ENDIAN */ + +#define XM_IN32(IoC, Mac, Reg, pVal) { \ + SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1); \ + SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal)); \ +} + +#endif /* !SK_LITTLE_ENDIAN */ + #define XM_OUT32(IoC, Mac, Reg, Val) { \ - SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \ - SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16)(((Val) >> 16) & 0xffffL));\ + SK_OUT16(IoC, XMA(Mac, Reg), (SK_U16)((Val) & 0xffffL)); \ + SK_OUT16(IoC, XMA(Mac, (Reg) + 2), (SK_U16)(((Val) >> 16) & 0xffffL)); \ } /* Remember: we are always writing to / reading from LITTLE ENDIAN memory */ @@ -2012,61 +2732,61 @@ typedef struct s_HwRxd { SK_U8 *pByte; \ pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \ - pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ - SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \ - pByte[2] = (SK_U8)(Word & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ - SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \ - pByte[4] = (SK_U8)(Word & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ } #define XM_OUTADDR(IoC, Mac, Reg, pVal) { \ - SK_U8 *pByte; \ - pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_U8 SK_FAR *pByte; \ + pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \ SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \ (((SK_U16)(pByte[0]) & 0x00ff) | \ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ - SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \ + SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16) \ (((SK_U16)(pByte[2]) & 0x00ff) | \ (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ - SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \ + SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16) \ (((SK_U16)(pByte[4]) & 0x00ff) | \ (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ } #define XM_INHASH(IoC, Mac, Reg, pVal) { \ SK_U16 Word; \ - SK_U8 *pByte; \ - pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_U8 SK_FAR *pByte; \ + pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \ SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \ - pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ - SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \ - pByte[2] = (SK_U8)(Word & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ - SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \ - pByte[4] = (SK_U8)(Word & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ - SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word); \ - pByte[6] = (SK_U8)(Word & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg) + 6), &Word); \ + pByte[6] = (SK_U8)(Word & 0x00ff); \ pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \ } #define XM_OUTHASH(IoC, Mac, Reg, pVal) { \ - SK_U8 *pByte; \ - pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_U8 SK_FAR *pByte; \ + pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \ SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \ (((SK_U16)(pByte[0]) & 0x00ff)| \ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ - SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \ + SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16) \ (((SK_U16)(pByte[2]) & 0x00ff)| \ (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ - SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \ + SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16) \ (((SK_U16)(pByte[4]) & 0x00ff)| \ (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ - SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \ + SK_OUT16((IoC), XMA((Mac), (Reg) + 6), (SK_U16) \ (((SK_U16)(pByte[6]) & 0x00ff)| \ (((SK_U16)(pByte[7]) << 8) & 0xff00))); \ } @@ -2076,12 +2796,12 @@ typedef struct s_HwRxd { * * GM_IN16(), to read a 16 bit register (e.g. GM_GP_STAT) * GM_OUT16(), to write a 16 bit register (e.g. GM_GP_CTRL) - * GM_IN32(), to read a 32 bit register (e.g. GM_) - * GM_OUT32(), to write a 32 bit register (e.g. GM_) + * GM_IN32(), to read a 32 bit register (e.g. GM_RXF_UC_OK) + * GM_OUT32(), to write a 32 bit register * GM_INADDR(), to read a network address register (e.g. GM_SRC_ADDR_1L) * GM_OUTADDR(), to write a network address register (e.g. GM_SRC_ADDR_2L) - * GM_INHASH(), to read the GM_MC_ADDR_H1 register - * GM_OUTHASH() to write the GM_MC_ADDR_H1 register + * GM_INHASH(), to read the hash registers (e.g. GM_MC_ADDR_H1..4) + * GM_OUTHASH() to write the hash registers (e.g. GM_MC_ADDR_H1..4) * * para: * Mac GMAC to access values: MAC_1 or MAC_2 @@ -2095,22 +2815,31 @@ typedef struct s_HwRxd { #define GMA(Mac, Reg) \ ((BASE_GMAC_1 + (Mac) * (BASE_GMAC_2 - BASE_GMAC_1)) | (Reg)) -#define GM_IN16(IoC, Mac, Reg, pVal) \ - SK_IN16((IoC), GMA((Mac), (Reg)), (pVal)) +#define GM_IN16(IoC, Mac, Reg, pVal) \ + SK_IN16(IoC, GMA(Mac, Reg), pVal) -#define GM_OUT16(IoC, Mac, Reg, Val) \ - SK_OUT16((IoC), GMA((Mac), (Reg)), (Val)) +#define GM_OUT16(IoC, Mac, Reg, Val) \ + SK_OUT16(IoC, GMA(Mac, Reg), Val) -#define GM_IN32(IoC, Mac, Reg, pVal) { \ - SK_IN16((IoC), GMA((Mac), (Reg)), \ - (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_LO]); \ - SK_IN16((IoC), GMA((Mac), (Reg+4)), \ - (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_HI]); \ +#ifdef SK_LITTLE_ENDIAN + +#define GM_IN32(IoC, Mac, Reg, pVal) { \ + SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal)); \ + SK_IN16((IoC), GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal) + 1); \ } +#else /* !SK_LITTLE_ENDIAN */ + +#define GM_IN32(IoC, Mac, Reg, pVal) { \ + SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1); \ + SK_IN16(IoC, GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal)); \ +} + +#endif /* !SK_LITTLE_ENDIAN */ + #define GM_OUT32(IoC, Mac, Reg, Val) { \ - SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \ - SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16)(((Val) >> 16) & 0xffffL));\ + SK_OUT16(IoC, GMA(Mac, Reg), (SK_U16)((Val) & 0xffffL)); \ + SK_OUT16(IoC, GMA(Mac, (Reg) + 4), (SK_U16)(((Val) >> 16) & 0xffffL)); \ } #define GM_INADDR(IoC, Mac, Reg, pVal) { \ @@ -2118,26 +2847,26 @@ typedef struct s_HwRxd { SK_U8 *pByte; \ pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \ - pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ - SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \ - pByte[2] = (SK_U8)(Word & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ - SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \ - pByte[4] = (SK_U8)(Word & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ } #define GM_OUTADDR(IoC, Mac, Reg, pVal) { \ - SK_U8 *pByte; \ - pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_U8 SK_FAR *pByte; \ + pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \ SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \ (((SK_U16)(pByte[0]) & 0x00ff) | \ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ - SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \ + SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16) \ (((SK_U16)(pByte[2]) & 0x00ff) | \ (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ - SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \ + SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16) \ (((SK_U16)(pByte[4]) & 0x00ff) | \ (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ } @@ -2147,16 +2876,16 @@ typedef struct s_HwRxd { SK_U8 *pByte; \ pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \ - pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ - SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \ - pByte[2] = (SK_U8)(Word & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ - SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \ - pByte[4] = (SK_U8)(Word & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ - SK_IN16((IoC), GMA((Mac), (Reg+12)), &Word); \ - pByte[6] = (SK_U8)(Word & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg) + 12), &Word); \ + pByte[6] = (SK_U8)(Word & 0x00ff); \ pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \ } @@ -2166,13 +2895,13 @@ typedef struct s_HwRxd { SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \ (((SK_U16)(pByte[0]) & 0x00ff)| \ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ - SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \ + SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16) \ (((SK_U16)(pByte[2]) & 0x00ff)| \ (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ - SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \ + SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16) \ (((SK_U16)(pByte[4]) & 0x00ff)| \ (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ - SK_OUT16((IoC), GMA((Mac), (Reg+12)), (SK_U16) \ + SK_OUT16((IoC), GMA((Mac), (Reg) + 12), (SK_U16) \ (((SK_U16)(pByte[6]) & 0x00ff)| \ (((SK_U16)(pByte[7]) << 8) & 0xff00))); \ } @@ -2190,8 +2919,8 @@ typedef struct s_HwRxd { #define SK_PHY_BCOM 1 /* Broadcom BCM5400 */ #define SK_PHY_LONE 2 /* Level One LXT1000 */ #define SK_PHY_NAT 3 /* National DP83891 */ -#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1011S */ -#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1011S working on fiber */ +#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1040S */ +#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1040S working on fiber */ /* * PHY addresses (bits 12..8 of PHY address reg) @@ -2220,30 +2949,30 @@ typedef struct s_HwRxd { * * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value); * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never - * comes back. This is checked in DEBUG mode. + * comes back. This is checked in DEBUG mode. */ #ifndef DEBUG #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \ - SK_U16 Mmu; \ + SK_U16 Mmu; \ \ XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ if ((pPort)->PhyType != SK_PHY_XMAC) { \ - do { \ + do { \ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ } while ((Mmu & XM_MMU_PHY_RDY) == 0); \ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ - } \ + } \ } #else #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \ - SK_U16 Mmu; \ + SK_U16 Mmu; \ int __i = 0; \ \ XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ if ((pPort)->PhyType != SK_PHY_XMAC) { \ - do { \ + do { \ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ __i++; \ if (__i > 100000) { \ @@ -2254,7 +2983,7 @@ typedef struct s_HwRxd { } \ } while ((Mmu & XM_MMU_PHY_RDY) == 0); \ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ - } \ + } \ } #endif /* DEBUG */ @@ -2262,17 +2991,17 @@ typedef struct s_HwRxd { SK_U16 Mmu; \ \ if ((pPort)->PhyType != SK_PHY_XMAC) { \ - do { \ + do { \ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \ - } \ + } \ XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \ if ((pPort)->PhyType != SK_PHY_XMAC) { \ - do { \ + do { \ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \ - } \ + } \ } /* @@ -2281,12 +3010,14 @@ typedef struct s_HwRxd { * Use this macro to access PCI config register from the I/O space. * * para: + * pAC Pointer to adapter context * Addr PCI configuration register to access. * Values: PCI_VENDOR_ID ... PCI_VPD_ADR_REG, * - * usage SK_IN16(pAC, PCI_C(PCI_VENDOR_ID), pVal); + * usage SK_IN16(IoC, PCI_C(pAC, PCI_VENDOR_ID), pVal); */ -#define PCI_C(Addr) (B7_CFG_SPC + (Addr)) /* PCI Config Space */ +#define PCI_C(p, Addr) \ + (((CHIP_ID_YUKON_2(p)) ? Y2_CFG_SPC : B7_CFG_SPC) + (Addr)) /* * Macro SK_HW_ADDR(Base, Addr) @@ -2298,15 +3029,15 @@ typedef struct s_HwRxd { * Addr Address offset * * usage: May be used in SK_INxx and SK_OUTxx macros - * #define SK_IN8(pAC, Addr, pVal) ...\ + * #define SK_IN8(IoC, Addr, pVal) ...\ * *pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr))) */ -#ifdef SK_MEM_MAPPED_IO +#ifdef SK_MEM_MAPPED_IO #define SK_HW_ADDR(Base, Addr) ((Base) + (Addr)) -#else /* SK_MEM_MAPPED_IO */ +#else /* SK_MEM_MAPPED_IO */ #define SK_HW_ADDR(Base, Addr) \ ((Base) + (((Addr) & 0x7f) | (((Addr) >> 7 > 0) ? 0x80 : 0))) -#endif /* SK_MEM_MAPPED_IO */ +#endif /* SK_MEM_MAPPED_IO */ #define SZ_LONG (sizeof(SK_U32)) @@ -2317,20 +3048,31 @@ typedef struct s_HwRxd { * para: * pAC Pointer to adapter context struct * IoC I/O context needed for SK I/O macros - * Port Port number + * Port Port number * Mode Mode to set for this LED */ #define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \ SK_OUT8(IoC, MR_ADDR(Port, LNK_LED_REG), Mode); +#define SK_SET_GP_IO(IoC, Bit) { \ + SK_U32 DWord; \ + SK_IN32(IoC, B2_GP_IO, &DWord); \ + DWord |= ((GP_DIR_0 | GP_IO_0) << (Bit));\ + SK_OUT32(IoC, B2_GP_IO, DWord); \ +} -/* typedefs *******************************************************************/ +#define SK_CLR_GP_IO(IoC, Bit) { \ + SK_U32 DWord; \ + SK_IN32(IoC, B2_GP_IO, &DWord); \ + DWord &= ~((GP_DIR_0 | GP_IO_0) << (Bit));\ + SK_OUT32(IoC, B2_GP_IO, DWord); \ +} - -/* function prototypes ********************************************************/ +#define SK_GE_PCI_FIFO_SIZE 1600 /* PCI FIFO Size */ #ifdef __cplusplus } #endif /* __cplusplus */ #endif /* __INC_SKGEHW_H */ + diff --git a/drivers/sk98lin/h/skgehwt.h b/drivers/sk98lin/h/skgehwt.h index 8aa9edd..5c5e5b3 100644 --- a/drivers/sk98lin/h/skgehwt.h +++ b/drivers/sk98lin/h/skgehwt.h @@ -1,17 +1,17 @@ /****************************************************************************** * * Name: skhwt.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.5 $ - * Date: $Date: 1999/11/22 13:54:24 $ + * Project: Gigabit Ethernet Adapters, Event Scheduler Module + * Version: $Revision: 2.1 $ + * Date: $Date: 2003/10/27 14:16:09 $ * Purpose: Defines for the hardware timer functions * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998,1999 SysKonnect, - * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,32 +22,6 @@ * ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: skgehwt.h,v $ - * Revision 1.5 1999/11/22 13:54:24 cgoos - * Changed license header to GPL. - * - * Revision 1.4 1998/08/19 09:50:58 gklug - * fix: remove struct keyword from c-code (see CCC) add typedefs - * - * Revision 1.3 1998/08/14 07:09:29 gklug - * fix: chg pAc -> pAC - * - * Revision 1.2 1998/08/07 12:54:21 gklug - * fix: first compiled version - * - * Revision 1.1 1998/08/07 09:32:58 gklug - * first version - * - * - * - * - * - ******************************************************************************/ - /* * SKGEHWT.H contains all defines and types for the timer functions */ @@ -61,14 +35,14 @@ * - use in Adapters context name pAC->Hwt */ typedef struct s_Hwt { - SK_U32 TStart ; /* HWT start */ - SK_U32 TStop ; /* HWT stop */ - int TActive ; /* HWT: flag : active/inactive */ + SK_U32 TStart; /* HWT start */ + SK_U32 TStop; /* HWT stop */ + int TActive; /* HWT: flag : active/inactive */ } SK_HWT; extern void SkHwtInit(SK_AC *pAC, SK_IOC Ioc); extern void SkHwtStart(SK_AC *pAC, SK_IOC Ioc, SK_U32 Time); extern void SkHwtStop(SK_AC *pAC, SK_IOC Ioc); -extern SK_U32 SkHwtRead(SK_AC *pAC,SK_IOC Ioc); +extern SK_U32 SkHwtRead(SK_AC *pAC, SK_IOC Ioc); extern void SkHwtIsr(SK_AC *pAC, SK_IOC Ioc); #endif /* _SKGEHWT_H_ */ diff --git a/drivers/sk98lin/h/skgeinit.h b/drivers/sk98lin/h/skgeinit.h index cdddef9..77bce5d 100644 --- a/drivers/sk98lin/h/skgeinit.h +++ b/drivers/sk98lin/h/skgeinit.h @@ -1,329 +1,25 @@ /****************************************************************************** * * Name: skgeinit.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.75 $ - * Date: $Date: 2003/02/05 13:36:39 $ + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 2.51 $ + * Date: $Date: 2006/04/05 13:37:16 $ * Purpose: Structures and prototypes for the GE Init Module * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2006 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: skgeinit.h,v $ - * Revision 1.75 2003/02/05 13:36:39 rschmidt - * Added define SK_FACT_78 for YUKON's Host Clock of 78.12 MHz - * Editorial changes - * - * Revision 1.74 2003/01/28 09:39:16 rschmidt - * Added entry GIYukonLite in s_GeInit structure - * Editorial changes - * - * Revision 1.73 2002/11/15 12:47:25 rschmidt - * Replaced error message SKERR_HWI_E024 for Cable Diagnostic with - * Rx queue error in SkGeStopPort(). - * - * Revision 1.72 2002/11/12 17:08:35 rschmidt - * Added entries for Cable Diagnostic to Port structure - * Added entries GIPciSlot64 and GIPciClock66 in s_GeInit structure - * Added error message for Cable Diagnostic - * Added prototypes for SkGmCableDiagStatus() - * Editorial changes - * - * Revision 1.71 2002/10/21 11:26:10 mkarl - * Changed interface of SkGeInitAssignRamToQueues(). - * - * Revision 1.70 2002/10/14 08:21:32 rschmidt - * Changed type of GICopperType, GIVauxAvail to SK_BOOL - * Added entry PRxOverCnt to Port structure - * Added entry GIYukon32Bit in s_GeInit structure - * Editorial changes - * - * Revision 1.69 2002/10/09 16:57:15 mkarl - * Added some constants and macros for SkGeInitAssignRamToQueues(). - * - * Revision 1.68 2002/09/12 08:58:51 rwahl - * Retrieve counters needed for XMAC errata workarounds directly because - * PNMI returns corrected counter values (e.g. #10620). - * - * Revision 1.67 2002/08/16 14:40:30 rschmidt - * Added entries GIGenesis and GICopperType in s_GeInit structure - * Added prototypes for SkMacHashing() - * Editorial changes - * - * Revision 1.66 2002/08/12 13:27:21 rschmidt - * Added defines for Link speed capabilities - * Added entry PLinkSpeedCap to Port structure - * Added entry GIVauxAvail in s_GeInit structure - * Added prototypes for SkMacPromiscMode() - * Editorial changes - * - * Revision 1.65 2002/08/08 15:46:18 rschmidt - * Added define SK_PHY_ACC_TO for PHY access timeout - * Added define SK_XM_RX_HI_WM for XMAC Rx High Watermark - * Added define SK_MIN_TXQ_SIZE for Min RAM Buffer Tx Queue Size - * Added entry PhyId1 to Port structure - * - * Revision 1.64 2002/07/23 16:02:56 rschmidt - * Added entry GIWolOffs in s_GeInit struct (HW-Bug in YUKON 1st rev.) - * Added prototypes for: SkGePhyRead(), SkGePhyWrite() - * - * Revision 1.63 2002/07/18 08:17:38 rwahl - * Corrected definitions for SK_LSPEED_xxx & SK_LSPEED_STAT_xxx. - * - * Revision 1.62 2002/07/17 18:21:55 rwahl - * Added SK_LSPEED_INDETERMINATED define. - * - * Revision 1.61 2002/07/17 17:16:03 rwahl - * - MacType now member of GIni struct. - * - Struct alignment to 32bit. - * - Editorial change. - * - * Revision 1.60 2002/07/15 18:23:39 rwahl - * Added GeMacFunc to GE Init structure. - * Added prototypes for SkXmUpdateStats(), SkGmUpdateStats(), - * SkXmMacStatistic(), SkGmMacStatistic(), SkXmResetCounter(), - * SkGmResetCounter(), SkXmOverflowStatus(), SkGmOverflowStatus(). - * Added defines for current link speed state. - * Added ERRMSG defintions for MacUpdateStat() & MacStatistics(). - * - * Revision 1.59 2002/07/15 15:40:22 rschmidt - * Added entry PLinkSpeedUsed to Port structure - * Editorial changes - * - * Revision 1.58 2002/06/10 09:36:30 rschmidt - * Editorial changes. - * - * Revision 1.57 2002/06/05 08:18:00 rschmidt - * Corrected alignment in Port Structure - * Added new prototypes for GMAC - * Editorial changes - * - * Revision 1.56 2002/04/25 11:38:12 rschmidt - * Added defines for Link speed values - * Added defines for Loopback parameters for MAC and PHY - * Removed entry PRxCmd from Port structure - * Added entry PLinkSpeed to Port structure - * Added entries GIChipId and GIChipRev to GE Init structure - * Removed entry GIAnyPortAct from GE Init structure - * Added prototypes for: SkMacInit(), SkMacInitPhy(), - * SkMacRxTxDisable(), SkMacSoftRst(), SkMacHardRst(), SkMacIrq(), - * SkMacIrqDisable(), SkMacFlushTxFifo(), SkMacFlushRxFifo(), - * SkMacAutoNegDone(), SkMacAutoNegLipaPhy(), SkMacSetRxTxEn(), - * SkXmPhyRead(), SkXmPhyRead(), SkGmPhyWrite(), SkGmPhyWrite(); - * Removed prototypes for static functions in SkXmac2.c - * Editorial changes - * - * Revision 1.55 2002/02/26 15:24:53 rwahl - * Fix: no link with manual configuration (#10673). The previous fix for - * #10639 was removed. So for RLMT mode = CLS the RLMT may switch to - * misconfigured port. It should not occur for the other RLMT modes. - * - * Revision 1.54 2002/01/18 16:52:52 rwahl - * Editorial corrections. - * - * Revision 1.53 2001/11/20 09:19:58 rwahl - * Reworked bugfix #10639 (no dependency to RLMT mode). - * - * Revision 1.52 2001/10/26 07:52:23 afischer - * Port switching bug in `check local link` mode - * - * Revision 1.51 2001/02/09 12:26:38 cgoos - * Inserted #ifdef DIAG for half duplex workaround timer. - * - * Revision 1.50 2001/02/07 07:56:40 rassmann - * Corrected copyright. - * - * Revision 1.49 2001/01/31 15:32:18 gklug - * fix: problem with autosensing an SR8800 switch - * add: counter for autoneg timeouts - * - * Revision 1.48 2000/11/09 11:30:10 rassmann - * WA: Waiting after releasing reset until BCom chip is accessible. - * - * Revision 1.47 2000/10/18 12:22:40 cgoos - * Added workaround for half duplex hangup. - * - * Revision 1.46 2000/08/10 11:28:00 rassmann - * Editorial changes. - * Preserving 32-bit alignment in structs for the adapter context. - * - * Revision 1.45 1999/11/22 13:56:19 cgoos - * Changed license header to GPL. - * - * Revision 1.44 1999/10/26 07:34:15 malthoff - * The define SK_LNK_ON has been lost in v1.41. - * - * Revision 1.43 1999/10/06 09:30:16 cgoos - * Changed SK_XM_THR_JUMBO. - * - * Revision 1.42 1999/09/16 12:58:26 cgoos - * Changed SK_LED_STANDY macro to be independent of HW link sync. - * - * Revision 1.41 1999/07/30 06:56:14 malthoff - * Correct comment for SK_MS_STAT_UNSET. - * - * Revision 1.40 1999/05/27 13:38:46 cgoos - * Added SK_BMU_TX_WM. - * Made SK_BMU_TX_WM and SK_BMU_RX_WM user-definable. - * Changed XMAC Tx treshold to max. values. - * - * Revision 1.39 1999/05/20 14:35:26 malthoff - * Remove prototypes for SkGeLinkLED(). - * - * Revision 1.38 1999/05/19 11:59:12 cgoos - * Added SK_MS_CAP_INDETERMINATED define. - * - * Revision 1.37 1999/05/19 07:32:33 cgoos - * Changes for 1000Base-T. - * LED-defines for HWAC_LINK_LED macro. - * - * Revision 1.36 1999/04/08 14:00:24 gklug - * add:Port struct field PLinkResCt - * - * Revision 1.35 1999/03/25 07:43:07 malthoff - * Add error string for SKERR_HWI_E018MSG. - * - * Revision 1.34 1999/03/12 16:25:57 malthoff - * Remove PPollRxD and PPollTxD. - * Add SKERR_HWI_E017MSG. and SK_DPOLL_MAX. - * - * Revision 1.33 1999/03/12 13:34:41 malthoff - * Add Autonegotiation error codes. - * Change defines for parameter Mode in SkXmSetRxCmd(). - * Replace __STDC__ by SK_KR_PROTO. - * - * Revision 1.32 1999/01/25 14:40:20 mhaveman - * Added new return states for the virtual management port if multiple - * ports are active but differently configured. - * - * Revision 1.31 1998/12/11 15:17:02 gklug - * add: Link partnet autoneg states : Unknown Manual and Auto-negotiation - * - * Revision 1.30 1998/12/07 12:17:04 gklug - * add: Link Partner auto-negotiation flag - * - * Revision 1.29 1998/12/01 10:54:42 gklug - * add: variables for XMAC Errata - * - * Revision 1.28 1998/12/01 10:14:15 gklug - * add: PIsave saves the Interrupt status word - * - * Revision 1.27 1998/11/26 15:24:52 mhaveman - * Added link status states SK_LMODE_STAT_AUTOHALF and - * SK_LMODE_STAT_AUTOFULL which are used by PNMI. - * - * Revision 1.26 1998/11/26 14:53:01 gklug - * add:autoNeg Timeout variable - * - * Revision 1.25 1998/11/26 08:58:50 gklug - * add: Link Mode configuration (AUTO Sense mode) - * - * Revision 1.24 1998/11/24 13:30:27 gklug - * add: PCheckPar to port struct - * - * Revision 1.23 1998/11/18 13:23:26 malthoff - * Add SK_PKT_TO_MAX. - * - * Revision 1.22 1998/11/18 13:19:54 gklug - * add: PPrevShorts and PLinkBroken to port struct for WA XMAC Errata #C1 - * - * Revision 1.21 1998/10/26 08:02:57 malthoff - * Add GIRamOffs. - * - * Revision 1.20 1998/10/19 07:28:37 malthoff - * Add prototype for SkGeInitRamIface(). - * - * Revision 1.19 1998/10/14 14:47:48 malthoff - * SK_TIMER should not be defined for Diagnostics. - * Add SKERR_HWI_E015MSG and SKERR_HWI_E016MSG. - * - * Revision 1.18 1998/10/14 14:00:03 gklug - * add: timer to port struct for workaround of Errata #2 - * - * Revision 1.17 1998/10/14 11:23:09 malthoff - * Add prototype for SkXmAutoNegDone(). - * Fix SkXmSetRxCmd() prototype statement. - * - * Revision 1.16 1998/10/14 05:42:29 gklug - * add: HWLinkUp flag to Port struct - * - * Revision 1.15 1998/10/09 08:26:33 malthoff - * Rename SK_RB_ULPP_B to SK_RB_LLPP_B. - * - * Revision 1.14 1998/10/09 07:11:13 malthoff - * bug fix: SK_FACT_53 is 85 not 117. - * Rework time out init values. - * Add GIPortUsage and corresponding defines. - * Add some error log messages. - * - * Revision 1.13 1998/10/06 14:13:14 malthoff - * Add prototype for SkGeLoadLnkSyncCnt(). - * - * Revision 1.12 1998/10/05 11:29:53 malthoff - * bug fix: A comment was not closed. - * - * Revision 1.11 1998/10/05 08:01:59 malthoff - * Add default Timeout- Threshold- and - * Watermark constants. Add QRam start and end - * variables. Also add vars to store the polling - * mode and receive command. Add new Error Log - * Messages and function prototypes. - * - * Revision 1.10 1998/09/28 13:34:48 malthoff - * Add mode bits for LED functions. - * Move Autoneg and Flow Ctrl bits from shgesirq.h - * Add the required Error Log Entries - * and Function Prototypes. - * - * Revision 1.9 1998/09/16 14:38:41 malthoff - * Rework the SK_LNK_xxx defines. - * Add error log message defines. - * Add prototypes for skxmac2.c - * - * Revision 1.8 1998/09/11 05:29:18 gklug - * add: init state of a port - * - * Revision 1.7 1998/09/08 08:35:52 gklug - * add: defines of the Init Levels - * - * Revision 1.6 1998/09/03 13:48:42 gklug - * add: Link strati, capabilities to Port struct - * - * Revision 1.5 1998/09/03 13:30:59 malthoff - * Add SK_LNK_BLINK and SK_LNK_PERM. - * - * Revision 1.4 1998/09/03 09:55:31 malthoff - * Add constants for parameters Dir and RstMode - * when calling SkGeStopPort(). - * Rework the prototype section. - * Add Queue Address offsets PRxQOff, PXsQOff, and PXaQOff. - * Remove Ioc with IoC. - * - * Revision 1.3 1998/08/19 09:11:54 gklug - * fix: struct are removed from c-source (see CCC) - * add: typedefs for all structs - * - * Revision 1.2 1998/07/28 12:38:26 malthoff - * The prototypes got the parameter 'IoC'. - * - * Revision 1.1 1998/07/23 09:50:24 malthoff - * Created. + * /LICENSE * ******************************************************************************/ @@ -336,6 +32,8 @@ extern "C" { /* defines ********************************************************************/ +#define SK_TEST_VAL 0x11335577UL + /* modifying Link LED behaviour (used with SkGeLinkLED()) */ #define SK_LNK_OFF LED_OFF #define SK_LNK_ON (LED_ON | LED_BLK_OFF | LED_SYNC_OFF) @@ -360,17 +58,20 @@ extern "C" { #define SK_LED_TST 2 /* Counter and Timer constants, for a host clock of 62.5 MHz */ -#define SK_XMIT_DUR 0x002faf08L /* 50 ms */ -#define SK_BLK_DUR 0x01dcd650L /* 500 ms */ +#define SK_XMIT_DUR 0x002faf08UL /* 50 ms */ +#define SK_BLK_DUR 0x01dcd650UL /* 500 ms */ -#define SK_DPOLL_DEF 0x00ee6b28L /* 250 ms at 62.5 MHz */ +#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz (Genesis) */ +#define SK_DPOLL_DEF_Y2 0x0000124fUL /* 75 us (Yukon-2) */ -#define SK_DPOLL_MAX 0x00ffffffL /* 268 ms at 62.5 MHz */ - /* 215 ms at 78.12 MHz */ +#define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */ + /* 215 ms at 78.12 MHz (Yukon) */ #define SK_FACT_62 100 /* is given in percent */ -#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */ +#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */ #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */ +#define SK_FACT_100 161 /* on YUKON-FE: 100 MHz */ +#define SK_FACT_125 202 /* on YUKON-EC: 125 MHz */ /* Timeout values */ #define SK_MAC_TO_53 72 /* MAC arbiter timeout */ @@ -385,11 +86,23 @@ extern "C" { #define SK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ #define SK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ +/* Threshold values for Yukon-EC Ultra */ +#define SK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */ +#define SK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */ +#define SK_ECU_AE_THR 0x0180 /* Almost Empty Threshold */ +#define SK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */ + #ifndef SK_BMU_RX_WM -#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ +#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ #endif + #ifndef SK_BMU_TX_WM -#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ +#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ +#endif + +/* performance sensitive drivers should set this define to 0x80 */ +#ifndef SK_BMU_RX_WM_PEX +#define SK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */ #endif /* XMAC II Rx High Watermark */ @@ -401,37 +114,31 @@ extern "C" { #define SK_XM_THR_MULL 0x01fb /* .. for multiple link usage */ #define SK_XM_THR_JUMBO 0x03fc /* .. for jumbo frame usage */ -/* values for GIPortUsage */ +/* values for PortUsage */ #define SK_RED_LINK 1 /* redundant link usage */ #define SK_MUL_LINK 2 /* multiple link usage */ #define SK_JUMBO_LINK 3 /* driver uses jumbo frames */ /* Minimum RAM Buffer Rx Queue Size */ -#define SK_MIN_RXQ_SIZE 16 /* 16 kB */ +#define SK_MIN_RXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */ /* Minimum RAM Buffer Tx Queue Size */ -#define SK_MIN_TXQ_SIZE 16 /* 16 kB */ +#define SK_MIN_TXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */ -/* Queue Size units */ -#define QZ_UNITS 0x7 +/* Queue Size units (Genesis/Yukon) */ +#define QZ_UNITS 7 #define QZ_STEP 8 +/* Queue Size units (Yukon-2) */ +#define QZ_STEP_Y2 1 + /* Percentage of queue size from whole memory */ /* 80 % for receive */ -#define RAM_QUOTA_RX 80L -/* 0% for sync transfer */ -#define RAM_QUOTA_SYNC 0L +#define RAM_QUOTA_RX 80 +/* 0 % for sync transfer */ +#define RAM_QUOTA_SYNC 0 /* the rest (20%) is taken for async transfer */ -/* Get the rounded queue size in Bytes in 8k steps */ -#define ROUND_QUEUE_SIZE(SizeInBytes) \ - ((((unsigned long) (SizeInBytes) + (QZ_STEP*1024L)-1) / 1024) & \ - ~(QZ_STEP-1)) - -/* Get the rounded queue size in KBytes in 8k steps */ -#define ROUND_QUEUE_SIZE_KB(Kilobytes) \ - ROUND_QUEUE_SIZE((Kilobytes) * 1024L) - /* Types of RAM Buffer Queues */ #define SK_RX_SRAM_Q 1 /* small receive queue */ #define SK_RX_BRAM_Q 2 /* big receive queue */ @@ -470,11 +177,11 @@ extern "C" { /* Link Speed Capabilities */ -#define SK_LSPEED_CAP_AUTO (1<<0) /* Automatic resolution */ -#define SK_LSPEED_CAP_10MBPS (1<<1) /* 10 Mbps */ -#define SK_LSPEED_CAP_100MBPS (1<<2) /* 100 Mbps */ -#define SK_LSPEED_CAP_1000MBPS (1<<3) /* 1000 Mbps */ -#define SK_LSPEED_CAP_INDETERMINATED (1<<4) /* indeterminated */ +#define SK_LSPEED_CAP_AUTO BIT_0S /* Automatic resolution */ +#define SK_LSPEED_CAP_10MBPS BIT_1S /* 10 Mbps */ +#define SK_LSPEED_CAP_100MBPS BIT_2S /* 100 Mbps */ +#define SK_LSPEED_CAP_1000MBPS BIT_3S /* 1000 Mbps */ +#define SK_LSPEED_CAP_INDETERMINATED BIT_4S /* indeterminated */ /* Link Speed Parameter */ #define SK_LSPEED_AUTO 1 /* Automatic resolution */ @@ -492,11 +199,11 @@ extern "C" { /* Link Capability Parameter */ -#define SK_LMODE_CAP_HALF (1<<0) /* Half Duplex Mode */ -#define SK_LMODE_CAP_FULL (1<<1) /* Full Duplex Mode */ -#define SK_LMODE_CAP_AUTOHALF (1<<2) /* AutoHalf Duplex Mode */ -#define SK_LMODE_CAP_AUTOFULL (1<<3) /* AutoFull Duplex Mode */ -#define SK_LMODE_CAP_INDETERMINATED (1<<4) /* indeterminated */ +#define SK_LMODE_CAP_HALF BIT_0S /* Half Duplex Mode */ +#define SK_LMODE_CAP_FULL BIT_1S /* Full Duplex Mode */ +#define SK_LMODE_CAP_AUTOHALF BIT_2S /* AutoHalf Duplex Mode */ +#define SK_LMODE_CAP_AUTOFULL BIT_3S /* AutoFull Duplex Mode */ +#define SK_LMODE_CAP_INDETERMINATED BIT_4S /* indeterminated */ /* Link Mode Current State */ #define SK_LMODE_STAT_UNKNOWN 1 /* Unknown Duplex Mode */ @@ -507,7 +214,7 @@ extern "C" { #define SK_LMODE_STAT_INDETERMINATED 6 /* indeterminated */ /* Flow Control Mode Parameter (and capabilities) */ -#define SK_FLOW_MODE_NONE 1 /* No Flow-Control */ +#define SK_FLOW_MODE_NONE 1 /* No Flow Control */ #define SK_FLOW_MODE_LOC_SEND 2 /* Local station sends PAUSE */ #define SK_FLOW_MODE_SYMMETRIC 3 /* Both stations may send PAUSE */ #define SK_FLOW_MODE_SYM_OR_REM 4 /* Both stations may send PAUSE or @@ -523,10 +230,10 @@ extern "C" { #define SK_FLOW_STAT_INDETERMINATED 5 /* indeterminated */ /* Master/Slave Mode Capabilities */ -#define SK_MS_CAP_AUTO (1<<0) /* Automatic resolution */ -#define SK_MS_CAP_MASTER (1<<1) /* This station is master */ -#define SK_MS_CAP_SLAVE (1<<2) /* This station is slave */ -#define SK_MS_CAP_INDETERMINATED (1<<3) /* indeterminated */ +#define SK_MS_CAP_AUTO BIT_0S /* Automatic resolution */ +#define SK_MS_CAP_MASTER BIT_1S /* This station is master */ +#define SK_MS_CAP_SLAVE BIT_2S /* This station is slave */ +#define SK_MS_CAP_INDETERMINATED BIT_3S /* indeterminated */ /* Set Master/Slave Mode Parameter (and capabilities) */ #define SK_MS_MODE_AUTO 1 /* Automatic resolution */ @@ -536,30 +243,30 @@ extern "C" { /* Master/Slave Status Parameter */ #define SK_MS_STAT_UNSET 1 /* The M/S status is not set */ -#define SK_MS_STAT_MASTER 2 /* This station is Master */ -#define SK_MS_STAT_SLAVE 3 /* This station is Dlave */ +#define SK_MS_STAT_MASTER 2 /* This station is master */ +#define SK_MS_STAT_SLAVE 3 /* This station is slave */ #define SK_MS_STAT_FAULT 4 /* M/S resolution failed */ #define SK_MS_STAT_INDETERMINATED 5 /* indeterminated */ -/* parameter 'Mode' when calling SkXmSetRxCmd() */ -#define SK_STRIP_FCS_ON (1<<0) /* Enable FCS stripping of Rx frames */ -#define SK_STRIP_FCS_OFF (1<<1) /* Disable FCS stripping of Rx frames */ -#define SK_STRIP_PAD_ON (1<<2) /* Enable pad byte stripping of Rx fr */ -#define SK_STRIP_PAD_OFF (1<<3) /* Disable pad byte stripping of Rx fr */ -#define SK_LENERR_OK_ON (1<<4) /* Don't chk fr for in range len error */ -#define SK_LENERR_OK_OFF (1<<5) /* Check frames for in range len error */ -#define SK_BIG_PK_OK_ON (1<<6) /* Don't set Rx Error bit for big frames */ -#define SK_BIG_PK_OK_OFF (1<<7) /* Set Rx Error bit for big frames */ -#define SK_SELF_RX_ON (1<<8) /* Enable Rx of own packets */ -#define SK_SELF_RX_OFF (1<<9) /* Disable Rx of own packets */ +/* parameter 'Mode' when calling SkMacSetRxCmd() */ +#define SK_STRIP_FCS_ON BIT_0S /* Enable FCS stripping of Rx frames */ +#define SK_STRIP_FCS_OFF BIT_1S /* Disable FCS stripping of Rx frames */ +#define SK_STRIP_PAD_ON BIT_2S /* Enable pad byte stripping of Rx fr */ +#define SK_STRIP_PAD_OFF BIT_3S /* Disable pad byte stripping of Rx fr */ +#define SK_LENERR_OK_ON BIT_4S /* Don't chk fr for in range len error */ +#define SK_LENERR_OK_OFF BIT_5S /* Check frames for in range len error */ +#define SK_BIG_PK_OK_ON BIT_6S /* Don't set Rx Error bit for big frames */ +#define SK_BIG_PK_OK_OFF BIT_7S /* Set Rx Error bit for big frames */ +#define SK_SELF_RX_ON BIT_8S /* Enable Rx of own packets */ +#define SK_SELF_RX_OFF BIT_9S /* Disable Rx of own packets */ /* parameter 'Para' when calling SkMacSetRxTxEn() */ -#define SK_MAC_LOOPB_ON (1<<0) /* Enable MAC Loopback Mode */ -#define SK_MAC_LOOPB_OFF (1<<1) /* Disable MAC Loopback Mode */ -#define SK_PHY_LOOPB_ON (1<<2) /* Enable PHY Loopback Mode */ -#define SK_PHY_LOOPB_OFF (1<<3) /* Disable PHY Loopback Mode */ -#define SK_PHY_FULLD_ON (1<<4) /* Enable GMII Full Duplex */ -#define SK_PHY_FULLD_OFF (1<<5) /* Disable GMII Full Duplex */ +#define SK_MAC_LOOPB_ON BIT_0S /* Enable MAC Loopback Mode */ +#define SK_MAC_LOOPB_OFF BIT_1S /* Disable MAC Loopback Mode */ +#define SK_PHY_LOOPB_ON BIT_2S /* Enable PHY Loopback Mode */ +#define SK_PHY_LOOPB_OFF BIT_3S /* Disable PHY Loopback Mode */ +#define SK_PHY_FULLD_ON BIT_4S /* Enable GMII Full Duplex */ +#define SK_PHY_FULLD_OFF BIT_5S /* Disable GMII Full Duplex */ /* States of PState */ #define SK_PRT_RESET 0 /* the port is reset */ @@ -567,9 +274,28 @@ extern "C" { #define SK_PRT_INIT 2 /* the port is initialized */ #define SK_PRT_RUN 3 /* the port has an active link */ +/* PHY power down modes */ +#define PHY_PM_OPERATIONAL_MODE 0 /* PHY operational mode */ +#define PHY_PM_DEEP_SLEEP 1 /* Coma mode --> minimal power */ +#define PHY_PM_IEEE_POWER_DOWN 2 /* IEEE 22.2.4.1.5 compl. power down */ +#define PHY_PM_ENERGY_DETECT 3 /* Energy detect */ +#define PHY_PM_ENERGY_DETECT_PLUS 4 /* Energy detect plus */ + +/* PCI Bus Types */ +#define SK_PCI_BUS BIT_0S /* normal PCI bus */ +#define SK_PCIX_BUS BIT_1S /* PCI-X bus */ +#define SK_PEX_BUS BIT_2S /* PCI-Express bus */ + /* Default receive frame limit for Workaround of XMAC Errata */ #define SK_DEF_RX_WA_LIM SK_CONSTU64(100) +/* values for GILedBlinkCtrl (LED Blink Control) */ +#define SK_ACT_LED_BLINK BIT_0S /* Active LED blinking */ +#define SK_DUP_LED_NORMAL BIT_1S /* Duplex LED normal */ +#define SK_LED_LINK100_ON BIT_2S /* Link 100M LED on */ +#define SK_DUAL_LED_ACT_LNK BIT_3S /* Dual LED ACT/LNK configuration */ +#define SK_LED_LINK_MUX_P60 BIT_4S /* Link LED muxed to pin 60 */ + /* Link Partner Status */ #define SK_LIPA_UNKNOWN 0 /* Link partner is in unknown state */ #define SK_LIPA_MANUAL 1 /* Link partner is in detected manual state */ @@ -581,18 +307,174 @@ extern "C" { /* Max. Auto-neg. timeouts before link detection in sense mode is reset */ #define SK_MAX_ANEG_TO 10 /* Max. 10 times the sense mode is reset */ + +/****************************************************************************** + * + * HW_FEATURE() macro + */ + +/* DWORD 0: Features */ +#define HWF_FORCE_AUTO_NEG 0x04000000UL /* Force Auto-Negotiation */ +#define HWF_CLK_GATING_ENABLE 0x02000000UL /* Enable Clock Gating */ +#define HWF_RED_CORE_CLK_SUP 0x01000000UL /* Reduced Core Clock supp. */ +#define HWF_SYNC_TX_SUP 0x00800000UL /* Synch. Tx Queue available */ +#define HWF_SINGLE_PORT_DEVICE 0x00400000UL /* Device has only one LAN IF */ +#define HWF_JUMBO_FRAMES_SUP 0x00200000UL /* Jumbo Frames supported */ +#define HWF_TX_TCP_CSUM_SUP 0x00100000UL /* TCP Tx checksum supported */ +#define HWF_TX_UDP_CSUM_SUP 0x00080000UL /* UDP Tx checksum supported */ +#define HWF_RX_CSUM_SUP 0x00040000UL /* RX checksum supported */ +#define HWF_TCP_SEGM_SUP 0x00020000UL /* TCP segmentation supported */ +#define HWF_RSS_HASH_SUP 0x00010000UL /* RSS Hash supported */ +#define HWF_PORT_VLAN_SUP 0x00008000UL /* VLAN can be config per port*/ +#define HWF_ROLE_PARAM_SUP 0x00004000UL /* Role parameter supported */ +#define HWF_LOW_PMODE_SUP 0x00002000UL /* Low Power Mode supported */ +#define HWF_ENERGIE_DEMO_SUP 0x00001000UL /* Energy Detect mode supp. */ +#define HWF_SPEED1000_SUP 0x00000800UL /* Line Speed 1000 supported */ +#define HWF_SPEED100_SUP 0x00000400UL /* Line Speed 100 supported */ +#define HWF_SPEED10_SUP 0x00000200UL /* Line Speed 10 supported */ +#define HWF_AUTONEGSENSE_SUP 0x00000100UL /* Autoneg Sense supported */ +#define HWF_PHY_LOOPB_MD_SUP 0x00000080UL /* PHY loopback mode supp. */ +#define HWF_ASF_SUP 0x00000040UL /* ASF support possible */ +#define HWF_QS_STEPS_1KB 0x00000020UL /* The Rx/Tx queues can be */ + /* configured with 1 kB res. */ +#define HWF_OWN_RAM_PER_PORT 0x00000010UL /* Each port has a separate */ + /* RAM buffer */ +#define HWF_MIN_LED_IF 0x00000008UL /* Minimal LED interface */ + /* (e.g. for Yukon-EC) */ +#define HWF_LIST_ELEMENTS_USED 0x00000004UL /* HW uses list elements */ + /* (otherwise desc. are used) */ +#define HWF_GMAC_INSIDE 0x00000002UL /* Device contains GMAC */ +#define HWF_TWSI_PRESENT 0x00000001UL /* TWSI sensor bus present */ + +/*-RMV- DWORD 1: Deviations */ +#define HWF_WA_DEV_4200 0x10200000UL /*-RMV- 4.200 (D3 Blue Screen)*/ +#define HWF_WA_DEV_4185CS 0x10100000UL /*-RMV- 4.185 (ECU 100 CS cal)*/ +#define HWF_WA_DEV_4185 0x10080000UL /*-RMV- 4.185 (ECU Tx h check)*/ +#define HWF_WA_DEV_4167 0x10040000UL /*-RMV- 4.167 (Rx OvSize Hang)*/ +#define HWF_WA_DEV_4152 0x10020000UL /*-RMV- 4.152 (RSS issue) */ +#define HWF_WA_DEV_4115 0x10010000UL /*-RMV- 4.115 (Rx MAC FIFO) */ +#define HWF_WA_DEV_4109 0x10008000UL /*-RMV- 4.109 (BIU hang) */ +#define HWF_WA_DEV_483 0x10004000UL /*-RMV- 4.83 (Rx TCP wrong) */ +#define HWF_WA_DEV_479 0x10002000UL /*-RMV- 4.79 (Rx BMU hang II) */ +#define HWF_WA_DEV_472 0x10001000UL /*-RMV- 4.72 (GPHY2 MDC clk) */ +#define HWF_WA_DEV_463 0x10000800UL /*-RMV- 4.63 (Rx BMU hang I) */ +#define HWF_WA_DEV_427 0x10000400UL /*-RMV- 4.27 (Tx Done Rep) */ +#define HWF_WA_DEV_42 0x10000200UL /*-RMV- 4.2 (pref unit burst) */ +#define HWF_WA_DEV_46 0x10000100UL /*-RMV- 4.6 (CPU crash II) */ +#define HWF_WA_DEV_43_418 0x10000080UL /*-RMV- 4.3 & 4.18 (PCI unexp */ + /*-RMV- compl&Stat BMU deadl) */ +#define HWF_WA_DEV_420 0x10000040UL /*-RMV- 4.20 (Status BMU ov) */ +#define HWF_WA_DEV_423 0x10000020UL /*-RMV- 4.23 (TCP Segm Hang) */ +#define HWF_WA_DEV_424 0x10000010UL /*-RMV- 4.24 (MAC reg overwr) */ +#define HWF_WA_DEV_425 0x10000008UL /*-RMV- 4.25 (Magic packet */ + /*-RMV- with odd offset) */ +#define HWF_WA_DEV_428 0x10000004UL /*-RMV- 4.28 (Poll-U &BigEndi)*/ +#define HWF_WA_FIFO_FLUSH_YLA0 0x10000002UL /*-RMV- dis Rx GMAC FIFO Flush*/ + /*-RMV- for Yu-L Rev. A0 only */ +#define HWF_WA_COMA_MODE 0x10000001UL /*-RMV- Coma Mode WA req */ + +/* DWORD 2: still unused */ +/* DWORD 3: still unused */ + + +/* + * HW_FEATURE() - returns whether the feature is serviced or not + */ +#define HW_FEATURE(pAC, ReqFeature) \ + (((pAC)->GIni.HwF.Features[((ReqFeature) & 0x30000000UL) >> 28] &\ + ((ReqFeature) & 0x0fffffffUL)) != 0) + +#define HW_FEAT_LIST 0 +#define HW_DEV_LIST 1 + +#define SET_HW_FEATURE_MASK(pAC, List, OffMaskValue, OnMaskValue) { \ + if ((List) == HW_FEAT_LIST || (List) == HW_DEV_LIST) { \ + (pAC)->GIni.HwF.OffMask[List] = (OffMaskValue); \ + (pAC)->GIni.HwF.OnMask[List] = (OnMaskValue); \ + } \ +} + +/* driver access macros for GIni structure ***********************************/ + +#define CHIP_ID_YUKON_2(pAC) ((pAC)->GIni.GIYukon2) + +#define HW_SYNC_TX_SUPPORTED(pAC) \ + ((pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC && \ + (pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE && \ + (pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC_U) + +#define HW_MS_TO_TICKS(pAC, MsTime) \ + ((MsTime) * (62500L/100) * (pAC)->GIni.GIHstClkFact) + +#if 0 +/* still under construction */ +#define HW_IS_SINGLE_PORT(pAC) ((pAC)->GIni.GIMacsFound == 1) +#define HW_NUMBER_OF_PORTS(pAC) ((pAC)->GIni.GIMacsFound) + +#define HW_TX_UDP_CSUM_SUPPORTED(pAC) \ + ((((pAC)->GIni.GIChipId >= CHIP_ID_YUKON) && ((pAC)->GIni.GIChipRev != 0)) + +#define HW_DEFAULT_LINESPEED(pAC) \ + ((!(pAC)->GIni.GIGenesis && (pAC)->GIni.GICopperType) ? \ + SK_LSPEED_AUTO : SK_LSPEED_1000MBPS) + +#define HW_ROLE_PARAM_SUPPORTED(pAC) ((pAC)->GIni.GICopperType) + +#define HW_SPEED1000_SUPPORTED(pAC, Port) \ + ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) + +#define HW_SPEED100_SUPPORTED(pAC, Port) \ + ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_100MBPS) + +#define HW_SPEED10_SUPPORTED(pAC, Port) \ + ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_10MBPS) + +#define HW_AUTONEGSENSE_SUPPORTED(pAC) ((pAC)->GIni.GP[0].PhyType==SK_PHY_XMAC) + +#define HW_FREQ_TO_CARD_TICKS(pAC, AdapterClkSpeed, Freq) \ + (((AdapterClkSpeed / 100) * (pAC)->GIni.GIHstClkFact) / Freq) + +#define HW_IS_LINK_UP(pAC, Port) ((pAC)->GIni.GP[Port].PHWLinkUp) +#define HW_LINK_SPEED_USED(pAC, Port) ((pAC)->GIni.GP[Port].PLinkSpeedUsed) +#define HW_RAM_SIZE(pAC) ((pAC)->GIni.GIRamSize) + +#define HW_PHY_LP_MODE_SUPPORTED(pAC) (pAC0->??? +#define HW_ASF_ACTIVE(pAC) ??? +#define RAWIO_OUT32(pAC, pAC->RegIrqMask, pAC->GIni.GIValIrqMask)... + +/* macro to check whether Tx checksum is supported */ +#define HW_TX_CSUM_SUPPORTED(pAC) ((pAC)->GIni.GIChipId != CHIP_ID_GENESIS) + +BMU_UDP_CHECK : BMU_TCP_CHECK; + +/* macro for - Own Bit mirrored to DWORD7 (Yukon LP receive descriptor) */ +#endif /* 0 */ + + /* structures *****************************************************************/ +/* + * HW Feature structure + */ +typedef struct s_HwFeatures { + SK_U32 Features[4]; /* Feature list */ + SK_U32 OffMask[4]; /* Off Mask */ + SK_U32 OnMask[4]; /* On Mask */ +} SK_HW_FEATURES; + /* * MAC specific functions */ typedef struct s_GeMacFunc { - int (*pFnMacUpdateStats)(SK_AC *pAC, SK_IOC IoC, unsigned int Port); - int (*pFnMacStatistic)(SK_AC *pAC, SK_IOC IoC, unsigned int Port, - SK_U16 StatAddr, SK_U32 *pVal); - int (*pFnMacResetCounter)(SK_AC *pAC, SK_IOC IoC, unsigned int Port); - int (*pFnMacOverflow)(SK_AC *pAC, SK_IOC IoC, unsigned int Port, - SK_U16 IStatus, SK_U64 *pVal); + int (*pFnMacUpdateStats)(SK_AC *, SK_IOC, unsigned int); + int (*pFnMacStatistic)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U32 SK_FAR *); + int (*pFnMacResetCounter)(SK_AC *, SK_IOC, unsigned int); + int (*pFnMacOverflow)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U64 SK_FAR *); + void (*pSkGeSirqIsr)(SK_AC *, SK_IOC, SK_U32); +#ifdef SK_DIAG + int (*pFnMacPhyRead)(SK_AC *, SK_IOC, int, int, SK_U16 SK_FAR *); + int (*pFnMacPhyWrite)(SK_AC *, SK_IOC, int, int, SK_U16); +#endif /* SK_DIAG */ } SK_GEMACFUNC; /* @@ -602,8 +484,8 @@ typedef struct s_GePort { #ifndef SK_DIAG SK_TIMER PWaTimer; /* Workaround Timer */ SK_TIMER HalfDupChkTimer; -#endif /* SK_DIAG */ - SK_U32 PPrevShorts; /* Previous short Counter checking */ +#endif /* !SK_DIAG */ + SK_U32 PPrevShorts; /* Previous Short Counter checking */ SK_U32 PPrevFcs; /* Previous FCS Error Counter checking */ SK_U64 PPrevRx; /* Previous RxOk Counter checking */ SK_U64 PRxLim; /* Previous RxOk Counter checking */ @@ -625,12 +507,14 @@ typedef struct s_GePort { int PXsQOff; /* Synchronous Tx Queue Address Offset */ int PXaQOff; /* Asynchronous Tx Queue Address Offset */ int PhyType; /* PHY used on this port */ + int PState; /* Port status (reset, stop, init, run) */ + int PPortUsage; /* Driver Port Usage */ SK_U16 PhyId1; /* PHY Id1 on this port */ SK_U16 PhyAddr; /* MDIO/MDC PHY address */ SK_U16 PIsave; /* Saved Interrupt status word */ SK_U16 PSsave; /* Saved PHY status word */ + SK_U16 PGmANegAdv; /* Saved GPhy AutoNegAdvertisment register */ SK_BOOL PHWLinkUp; /* The hardware Link is up (wiring) */ - SK_BOOL PState; /* Is port initialized ? */ SK_BOOL PLinkBroken; /* Is Link broken ? */ SK_BOOL PCheckPar; /* Do we check for parity errors ? */ SK_BOOL HalfDupTimerActive; @@ -638,7 +522,7 @@ typedef struct s_GePort { SK_U8 PLinkModeConf; /* Link Mode configured */ SK_U8 PLinkMode; /* Link Mode currently used */ SK_U8 PLinkModeStatus;/* Link Mode Status */ - SK_U8 PLinkSpeedCap; /* Link Speed Capabilities(10/100/1000 Mbps) */ + SK_U8 PLinkSpeedCap; /* Link Speed Capabilities (10/100/1000 Mbps) */ SK_U8 PLinkSpeed; /* configured Link Speed (10/100/1000 Mbps) */ SK_U8 PLinkSpeedUsed; /* current Link Speed (10/100/1000 Mbps) */ SK_U8 PFlowCtrlCap; /* Flow Control Capabilities */ @@ -647,11 +531,21 @@ typedef struct s_GePort { SK_U8 PMSCap; /* Master/Slave Capabilities */ SK_U8 PMSMode; /* Master/Slave Mode */ SK_U8 PMSStatus; /* Master/Slave Status */ - SK_U8 PAutoNegFail; /* Auto-negotiation fail flag */ + SK_BOOL PAutoNegFail; /* Auto-negotiation fail flag */ SK_U8 PLipaAutoNeg; /* Auto-negotiation possible with Link Partner */ SK_U8 PCableLen; /* Cable Length */ SK_U8 PMdiPairLen[4]; /* MDI[0..3] Pair Length */ SK_U8 PMdiPairSts[4]; /* MDI[0..3] Pair Diagnostic Status */ + SK_U8 PPhyPowerState; /* PHY current power state */ + int PMacColThres; /* MAC Collision Threshold */ + int PMacJamLen; /* MAC Jam length */ + int PMacJamIpgVal; /* MAC Jam IPG */ + int PMacJamIpgData; /* MAC IPG Jam to Data */ + int PMacBackOffLim; /* MAC Back-off Limit */ + int PMacDataBlind; /* MAC Data Blinder */ + int PMacIpgData; /* MAC Data IPG */ + SK_U16 PMacAddr[3]; /* MAC address */ + SK_BOOL PMacLimit4; /* reset collision counter and backoff algorithm */ } SK_GEPORT; /* @@ -659,26 +553,41 @@ typedef struct s_GePort { * (has to be included in the adapter context) */ typedef struct s_GeInit { + int GIChipId; /* Chip Identification Number */ + int GIChipRev; /* Chip Revision Number */ SK_U8 GIPciHwRev; /* PCI HW Revision Number */ - SK_U8 GIChipId; /* Chip Identification Number */ - SK_U8 GIChipRev; /* Chip Revision Number */ + SK_U8 GIPciBus; /* PCI Bus Type (PCI / PCI-X / PCI-Express) */ + SK_U8 GIPciMode; /* PCI / PCI-X Mode @ Clock */ + SK_U8 GIPexWidth; /* PCI-Express Negotiated Link Width */ SK_BOOL GIGenesis; /* Genesis adapter ? */ + SK_BOOL GIYukon; /* YUKON family (1 and 2) */ + SK_BOOL GIYukonLite; /* YUKON-Lite chip */ + SK_BOOL GIYukon2; /* YUKON-2 chip (-XL, -EC or -FE) */ + SK_U8 GIConTyp; /* Connector Type */ + SK_U8 GIPmdTyp; /* PMD Type */ SK_BOOL GICopperType; /* Copper Type adapter ? */ SK_BOOL GIPciSlot64; /* 64-bit PCI Slot */ SK_BOOL GIPciClock66; /* 66 MHz PCI Clock */ SK_BOOL GIVauxAvail; /* VAUX available (YUKON) */ SK_BOOL GIYukon32Bit; /* 32-Bit YUKON adapter */ - SK_BOOL GIYukonLite; /* YUKON-Lite chip */ + SK_BOOL GIAsfEnabled; /* ASF subsystem enabled */ + SK_BOOL GIAsfRunning; /* ASF subsystem running */ + SK_U16 GILedBlinkCtrl; /* LED Blink Control */ int GIMacsFound; /* Number of MACs found on this adapter */ int GIMacType; /* MAC Type used on this adapter */ - int GIHstClkFact; /* Host Clock Factor (62.5 / HstClk * 100) */ - int GIPortUsage; /* Driver Port Usage */ + int GIChipCap; /* Adapter's Capabilities */ + int GIHwResInfo; /* HW Resources / Application Information */ + int GIHstClkFact; /* Host Clock Factor (HstClk / 62.5 * 100) */ int GILevel; /* Initialization Level completed */ int GIRamSize; /* The RAM size of the adapter in kB */ int GIWolOffs; /* WOL Register Offset (HW-Bug in Rev. A) */ SK_U32 GIRamOffs; /* RAM Address Offset for addr calculation */ SK_U32 GIPollTimerVal; /* Descr. Poll Timer Init Val (HstClk ticks) */ + SK_U32 GIValIrqMask; /* Value for Interrupt Mask */ + SK_U32 GIValHwIrqMask; /* Value for HWE Interrupt Mask */ + SK_U32 GITimeStampCnt; /* Time Stamp High Counter (YUKON only) */ SK_GEPORT GP[SK_MAX_MACS];/* Port Dependent Information */ + SK_HW_FEATURES HwF; /* HW Features struct */ SK_GEMACFUNC GIFunc; /* MAC depedent functions */ } SK_GEINIT; @@ -696,7 +605,7 @@ typedef struct s_GeInit { #define SKERR_HWI_E005 (SKERR_HWI_E004+1) #define SKERR_HWI_E005MSG "SkGeInitPort(): cannot init running ports" #define SKERR_HWI_E006 (SKERR_HWI_E005+1) -#define SKERR_HWI_E006MSG "SkGeMacInit(): PState does not match HW state" +#define SKERR_HWI_E006MSG "SkGeInit() called with illegal Chip Id" #define SKERR_HWI_E007 (SKERR_HWI_E006+1) #define SKERR_HWI_E007MSG "SkXmInitDupMd() called with invalid Dup Mode" #define SKERR_HWI_E008 (SKERR_HWI_E007+1) @@ -712,11 +621,11 @@ typedef struct s_GeInit { #define SKERR_HWI_E013 (SKERR_HWI_E012+1) #define SKERR_HWI_E013MSG "SkGeInitPort(): cfg changed for running queue" #define SKERR_HWI_E014 (SKERR_HWI_E013+1) -#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown GIPortUsage specified" +#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown PortUsage specified" #define SKERR_HWI_E015 (SKERR_HWI_E014+1) -#define SKERR_HWI_E015MSG "Illegal Link mode parameter" +#define SKERR_HWI_E015MSG "Illegal Link Mode parameter" #define SKERR_HWI_E016 (SKERR_HWI_E015+1) -#define SKERR_HWI_E016MSG "Illegal Flow control mode parameter" +#define SKERR_HWI_E016MSG "Illegal Flow Control Mode parameter" #define SKERR_HWI_E017 (SKERR_HWI_E016+1) #define SKERR_HWI_E017MSG "Illegal value specified for GIPollTimerVal" #define SKERR_HWI_E018 (SKERR_HWI_E017+1) @@ -726,15 +635,19 @@ typedef struct s_GeInit { #define SKERR_HWI_E020 (SKERR_HWI_E019+1) #define SKERR_HWI_E020MSG "Illegal Master/Slave parameter" #define SKERR_HWI_E021 (SKERR_HWI_E020+1) -#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter" -#define SKERR_HWI_E022 (SKERR_HWI_E021+1) -#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address" +#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter" +#define SKERR_HWI_E022 (SKERR_HWI_E021+1) +#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address" #define SKERR_HWI_E023 (SKERR_HWI_E022+1) #define SKERR_HWI_E023MSG "SkGeInitPort(): Transmit Queue Size too small" #define SKERR_HWI_E024 (SKERR_HWI_E023+1) #define SKERR_HWI_E024MSG "FATAL: SkGeStopPort() does not terminate (Rx)" #define SKERR_HWI_E025 (SKERR_HWI_E024+1) -#define SKERR_HWI_E025MSG "" +#define SKERR_HWI_E025MSG "Link Partner not Auto-Neg. able" +#define SKERR_HWI_E026 (SKERR_HWI_E025+1) +#define SKERR_HWI_E026MSG "PEX negotiated Link width not max." +#define SKERR_HWI_E027 (SKERR_HWI_E026+1) +#define SKERR_HWI_E027MSG "" /* function prototypes ********************************************************/ @@ -743,6 +656,24 @@ typedef struct s_GeInit { /* * public functions in skgeinit.c */ +extern void SkGePortVlan( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); + +extern void SkGeRxRss( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); + +extern void SkGeRxCsum( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); + extern void SkGePollRxD( SK_AC *pAC, SK_IOC IoC, @@ -807,9 +738,22 @@ extern void SkGeInitRamIface( extern int SkGeInitAssignRamToQueues( SK_AC *pAC, - int ActivePort, + int Port, SK_BOOL DualNet); +extern void DoInitRamQueue( + SK_AC *pAC, + SK_IOC IoC, + int QuIoOffs, + SK_U32 QuStartAddr, + SK_U32 QuEndAddr, + int QuType); + +extern int SkYuk2RestartRxBmu( + SK_AC *pAC, + SK_IOC IoC, + int Port); + /* * public functions in skxmac2.c */ @@ -828,6 +772,11 @@ extern void SkMacHardRst( SK_IOC IoC, int Port); +extern void SkMacClearRst( + SK_AC *pAC, + SK_IOC IoC, + int Port); + extern void SkXmInitMac( SK_AC *pAC, SK_IOC IoC, @@ -875,13 +824,13 @@ extern void SkMacAutoNegLipaPhy( int Port, SK_U16 IStatus); -extern void SkMacSetRxTxEn( +extern void SkMacSetRxTxEn( SK_AC *pAC, SK_IOC IoC, int Port, int Para); -extern int SkMacRxTxEnable( +extern int SkMacRxTxEnable( SK_AC *pAC, SK_IOC IoC, int Port); @@ -898,42 +847,28 @@ extern void SkMacHashing( int Port, SK_BOOL Enable); -extern void SkXmPhyRead( +extern int SkXmPhyRead( SK_AC *pAC, SK_IOC IoC, int Port, int Addr, - SK_U16 *pVal); + SK_U16 SK_FAR *pVal); -extern void SkXmPhyWrite( +extern int SkXmPhyWrite( SK_AC *pAC, SK_IOC IoC, int Port, int Addr, SK_U16 Val); -extern void SkGmPhyRead( +extern int SkGmPhyRead( SK_AC *pAC, SK_IOC IoC, int Port, int Addr, - SK_U16 *pVal); + SK_U16 SK_FAR *pVal); -extern void SkGmPhyWrite( - SK_AC *pAC, - SK_IOC IoC, - int Port, - int Addr, - SK_U16 Val); - -extern void SkGePhyRead( - SK_AC *pAC, - SK_IOC IoC, - int Port, - int Addr, - SK_U16 *pVal); - -extern void SkGePhyWrite( +extern int SkGmPhyWrite( SK_AC *pAC, SK_IOC IoC, int Port, @@ -978,14 +913,14 @@ extern int SkXmMacStatistic( SK_IOC IoC, unsigned int Port, SK_U16 StatAddr, - SK_U32 *pVal); + SK_U32 SK_FAR *pVal); extern int SkGmMacStatistic( SK_AC *pAC, SK_IOC IoC, unsigned int Port, SK_U16 StatAddr, - SK_U32 *pVal); + SK_U32 SK_FAR *pVal); extern int SkXmResetCounter( SK_AC *pAC, @@ -1001,15 +936,15 @@ extern int SkXmOverflowStatus( SK_AC *pAC, SK_IOC IoC, unsigned int Port, - SK_U16 IStatus, - SK_U64 *pStatus); + SK_U16 IStatus, + SK_U64 SK_FAR *pStatus); extern int SkGmOverflowStatus( SK_AC *pAC, SK_IOC IoC, unsigned int Port, SK_U16 MacStatus, - SK_U64 *pStatus); + SK_U64 SK_FAR *pStatus); extern int SkGmCableDiagStatus( SK_AC *pAC, @@ -1017,7 +952,34 @@ extern int SkGmCableDiagStatus( int Port, SK_BOOL StartTest); +#ifdef SK_PHY_LP_MODE +extern int SkGmEnterLowPowerMode( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_U8 Mode); + +extern int SkGmLeaveLowPowerMode( + SK_AC *pAC, + SK_IOC IoC, + int Port); +#endif /* SK_PHY_LP_MODE */ + #ifdef SK_DIAG +extern void SkGePhyRead( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 *pVal); + +extern void SkGePhyWrite( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 Val); + extern void SkMacSetRxCmd( SK_AC *pAC, SK_IOC IoC, @@ -1057,32 +1019,36 @@ extern int SkGeInitPort(); extern void SkGeXmitLED(); extern void SkGeInitRamIface(); extern int SkGeInitAssignRamToQueues(); +extern void SkGePortVlan(); +extern void SkGeRxCsum(); +extern void SkGeRxRss(); +extern void DoInitRamQueue(); +extern int SkYuk2RestartRxBmu(); /* * public functions in skxmac2.c */ -extern void SkMacRxTxDisable(); +extern void SkMacRxTxDisable(); extern void SkMacSoftRst(); extern void SkMacHardRst(); -extern void SkMacInitPhy(); -extern int SkMacRxTxEnable(); -extern void SkMacPromiscMode(); -extern void SkMacHashing(); -extern void SkMacIrqDisable(); +extern void SkMacClearRst(); +extern void SkMacInitPhy(); +extern int SkMacRxTxEnable(); +extern void SkMacPromiscMode(); +extern void SkMacHashing(); +extern void SkMacIrqDisable(); extern void SkMacFlushTxFifo(); extern void SkMacFlushRxFifo(); extern void SkMacIrq(); extern int SkMacAutoNegDone(); extern void SkMacAutoNegLipaPhy(); -extern void SkMacSetRxTxEn(); -extern void SkGePhyRead(); -extern void SkGePhyWrite(); +extern void SkMacSetRxTxEn(); extern void SkXmInitMac(); -extern void SkXmPhyRead(); -extern void SkXmPhyWrite(); +extern int SkXmPhyRead(); +extern int SkXmPhyWrite(); extern void SkGmInitMac(); -extern void SkGmPhyRead(); -extern void SkGmPhyWrite(); +extern int SkGmPhyRead(); +extern int SkGmPhyWrite(); extern void SkXmClrExactAddr(); extern void SkXmInitDupMd(); extern void SkXmInitPauseMd(); @@ -1096,18 +1062,25 @@ extern int SkGmResetCounter(); extern int SkXmOverflowStatus(); extern int SkGmOverflowStatus(); extern int SkGmCableDiagStatus(); +#ifdef SK_PHY_LP_MODE +extern int SkGmEnterLowPowerMode(); +extern int SkGmLeaveLowPowerMode(); +#endif /* SK_PHY_LP_MODE */ #ifdef SK_DIAG +extern void SkGePhyRead(); +extern void SkGePhyWrite(); extern void SkMacSetRxCmd(); extern void SkMacCrcGener(); extern void SkMacTimeStamp(); extern void SkXmSendCont(); #endif /* SK_DIAG */ -#endif /* SK_KR_PROTO */ +#endif /* SK_KR_PROTO */ #ifdef __cplusplus } -#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif /* __INC_SKGEINIT_H_ */ -#endif /* __INC_SKGEINIT_H_ */ diff --git a/drivers/sk98lin/h/skgepnm2.h b/drivers/sk98lin/h/skgepnm2.h index 5c44f47..ddf8f56 100644 --- a/drivers/sk98lin/h/skgepnm2.h +++ b/drivers/sk98lin/h/skgepnm2.h @@ -2,15 +2,17 @@ * * Name: skgepnm2.h * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.34 $ - * Date: $Date: 2002/12/16 09:05:18 $ + * Version: $Revision: 2.5 $ + * Date: $Date: 2005/12/14 16:11:19 $ * Purpose: Defines for Private Network Management Interface * ****************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2001 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,148 +20,23 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. + * /LICENSE * ******************************************************************************/ -/***************************************************************************** - * - * History: - * - * $Log: skgepnm2.h,v $ - * Revision 1.34 2002/12/16 09:05:18 tschilli - * Code for VCT handling added. - * - * Revision 1.33 2002/09/10 09:00:03 rwahl - * Adapted boolean definitions according sktypes. - * - * Revision 1.32 2002/08/09 09:47:01 rwahl - * Added write-only flag to oid access defines. - * Editorial changes. - * - * Revision 1.31 2002/07/17 19:23:18 rwahl - * - Replaced MAC counter definitions by enumeration. - * - Added definition SK_PNMI_MAC_TYPES. - * - Added chipset defnition for Yukon. - * - * Revision 1.30 2001/02/06 10:03:41 mkunz - * - Pnmi V4 dual net support added. Interface functions and macros extended - * - Vpd bug fixed - * - OID_SKGE_MTU added - * - * Revision 1.29 2001/01/22 13:41:37 rassmann - * Supporting two nets on dual-port adapters. - * - * Revision 1.28 2000/08/03 15:12:48 rwahl - * - Additional comment for MAC statistic data structure. - * - * Revision 1.27 2000/08/01 16:10:18 rwahl - * - Added mac statistic data structure for StatRxLongFrame counter. - * - * Revision 1.26 2000/03/31 13:51:34 rwahl - * Added SK_UPTR cast to offset calculation for PNMI struct fields; - * missing cast caused compiler warnings by Win64 compiler. - * - * Revision 1.25 1999/11/22 13:57:41 cgoos - * Changed license header to GPL. - * Allowing overwrite for SK_PNMI_STORE/_READ defines. - * - * Revision 1.24 1999/04/13 15:11:11 mhaveman - * Changed copyright. - * - * Revision 1.23 1999/01/28 15:07:12 mhaveman - * Changed default threshold for port switches per hour from 10 - * to 240 which means 4 switches per minute. This fits better - * the granularity of 32 for the port switch estimate - * counter. - * - * Revision 1.22 1999/01/05 12:52:30 mhaveman - * Removed macro SK_PNMI_MICRO_SEC. - * - * Revision 1.21 1999/01/05 12:50:34 mhaveman - * Enlarged macro definition SK_PNMI_HUNDREDS_SEC() so that no 64-bit - * arithmetic is necessary if SK_TICKS_PER_SEC is 100. - * - * Revision 1.20 1998/12/09 14:02:53 mhaveman - * Defined macro SK_PNMI_DEF_RLMT_CHG_THRES for default port switch - * threshold. - * - * Revision 1.19 1998/12/03 11:28:41 mhaveman - * Removed SK_PNMI_CHECKPTR macro. - * - * Revision 1.18 1998/12/03 11:21:00 mhaveman - * -Added pointer check macro SK_PNMI_CHECKPTR - * -Added macros SK_PNMI_VPD_ARR_SIZE and SK_PNMI_VPD_STR_SIZE for - * VPD key evaluation. - * - * Revision 1.17 1998/11/20 13:20:33 mhaveman - * Fixed bug in SK_PNMI_SET_STAT macro. ErrorStatus was not correctly set. - * - * Revision 1.16 1998/11/20 08:08:49 mhaveman - * Macro SK_PNMI_CHECKFLAGS has got a if clause. - * - * Revision 1.15 1998/11/03 13:53:40 mhaveman - * Fixed alignment problem in macor SK_PNMI_SET_STAT macro. - * - * Revision 1.14 1998/10/30 15:50:13 mhaveman - * Added macro SK_PNMI_MICRO_SEC() - * - * Revision 1.13 1998/10/30 12:32:20 mhaveman - * Added forgotten cast in SK_PNMI_READ_U32 macro. - * - * Revision 1.12 1998/10/29 15:40:26 mhaveman - * -Changed SK_PNMI_TRAP_SENSOR_LEN because SensorDescr has now - * variable string length. - * -Defined SK_PNMI_CHECKFLAGS macro - * - * Revision 1.11 1998/10/29 08:53:34 mhaveman - * Removed SK_PNMI_RLM_XXX table indexed because these counters need - * not been saved over XMAC resets. - * - * Revision 1.10 1998/10/28 08:48:20 mhaveman - * -Added macros for storage according to alignment - * -Changed type of Instance to SK_U32 because of VPD - * -Removed trap structures. Not needed because of alignment problem - * -Changed type of Action form SK_U8 to int - * - * Revision 1.9 1998/10/21 13:34:45 mhaveman - * Shit, mismatched calculation of SK_PNMI_HUNDREDS_SEC. Corrected. - * - * Revision 1.8 1998/10/21 13:24:58 mhaveman - * Changed calculation of hundreds of seconds. - * - * Revision 1.7 1998/10/20 07:31:41 mhaveman - * Made type changes to unsigned int where possible. - * - * Revision 1.6 1998/09/04 17:04:05 mhaveman - * Added Sync counters to offset storage to provided settled values on - * port switch. - * - * Revision 1.5 1998/09/04 12:45:35 mhaveman - * Removed dummies for SK_DRIVER_ macros. They should be added by driver - * writer in skdrv2nd.h. - * - * Revision 1.4 1998/09/04 11:59:50 mhaveman - * Everything compiles now. Driver Macros for counting still missing. - * - * Revision 1.3 1998/08/24 12:01:35 mhaveman - * Intermediate state. - * - * Revision 1.2 1998/08/17 07:51:40 mhaveman - * Intermediate state. - * - * Revision 1.1 1998/08/11 09:08:40 mhaveman - * Intermediate state. - * - ****************************************************************************/ - #ifndef _SKGEPNM2_H_ #define _SKGEPNM2_H_ /* * General definitions */ -#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */ -#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */ +#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */ +#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */ +#define SK_PNMI_CHIPSET_YUKON_LITE 3 /* YUKON-Lite (Rev. A1-A3) */ +#define SK_PNMI_CHIPSET_YUKON_LP 4 /* YUKON-LP */ +#define SK_PNMI_CHIPSET_YUKON_XL 5 /* YUKON-2 XL */ +#define SK_PNMI_CHIPSET_YUKON_EC 6 /* YUKON-2 EC */ +#define SK_PNMI_CHIPSET_YUKON_FE 7 /* YUKON-2 FE */ #define SK_PNMI_BUS_PCI 1 /* PCI bus*/ @@ -200,9 +77,9 @@ /* * VCT internal status values */ -#define SK_PNMI_VCT_PENDING 32 -#define SK_PNMI_VCT_TEST_DONE 64 -#define SK_PNMI_VCT_LINK 128 +#define SK_PNMI_VCT_PENDING 0x20 +#define SK_PNMI_VCT_TEST_DONE 0x40 +#define SK_PNMI_VCT_LINK 0x80 /* * Internal table definitions @@ -277,7 +154,7 @@ enum SK_MACSTATS { SK_PNMI_HTX_SYNC, SK_PNMI_HTX_SYNC_OCTET, SK_PNMI_HTX_RESERVED, - + SK_PNMI_HRX, SK_PNMI_HRX_OCTET, SK_PNMI_HRX_OCTETHIGH = SK_PNMI_HRX_OCTET, @@ -315,9 +192,9 @@ enum SK_MACSTATS { SK_PNMI_HRX_1023, SK_PNMI_HRX_MAX, SK_PNMI_HRX_LONGFRAMES, - + SK_PNMI_HRX_RESERVED, - + SK_PNMI_MAX_IDX /* NOTE: Ensure SK_PNMI_CNT_NO is set to this value */ }; @@ -359,11 +236,13 @@ typedef struct s_PnmiStatAddr { /* * Time macros */ +#ifndef SK_PNMI_HUNDREDS_SEC #if SK_TICKS_PER_SEC == 100 #define SK_PNMI_HUNDREDS_SEC(t) (t) #else #define SK_PNMI_HUNDREDS_SEC(t) (((t) * 100) / (SK_TICKS_PER_SEC)) -#endif +#endif /* !SK_TICKS_PER_SEC */ +#endif /* !SK_PNMI_HUNDREDS_SEC */ /* * Macros to work around alignment problems @@ -451,7 +330,7 @@ typedef struct s_PnmiStatAddr { vSt, \ pAC->Pnmi.MacUpdatedFlag, \ pAC->Pnmi.RlmtUpdatedFlag, \ - pAC->Pnmi.SirqUpdatedFlag))}} + pAC->Pnmi.SirqUpdatedFlag));}} #else /* !DEBUG */ diff --git a/drivers/sk98lin/h/skgepnmi.h b/drivers/sk98lin/h/skgepnmi.h index 7532313..bed28e0 100644 --- a/drivers/sk98lin/h/skgepnmi.h +++ b/drivers/sk98lin/h/skgepnmi.h @@ -1,16 +1,18 @@ /***************************************************************************** * * Name: skgepnmi.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.59 $ - * Date: $Date: 2002/12/16 14:03:50 $ + * Project: Gigabit Ethernet Adapters, PNMI-Module + * Version: $Revision: 2.12 $ + * Date: $Date: 2005/12/14 16:11:19 $ * Purpose: Defines for Private Network Management Interface * ****************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2001 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,218 +20,10 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. + * /LICENSE * ******************************************************************************/ -/***************************************************************************** - * - * History: - * - * $Log: skgepnmi.h,v $ - * Revision 1.59 2002/12/16 14:03:50 tschilli - * New defines for VCT added. - * - * Revision 1.58 2002/12/16 09:04:59 tschilli - * Code for VCT handling added. - * - * Revision 1.57 2002/09/26 12:41:05 tschilli - * SK_PNMI_PORT BufPort entry in struct SK_PNMI added. - * - * Revision 1.56 2002/08/16 11:10:41 rwahl - * - Replaced c++ comment. - * - * Revision 1.55 2002/08/09 15:40:21 rwahl - * Editorial change (renamed ConfSpeedCap). - * - * Revision 1.54 2002/08/09 11:06:07 rwahl - * Added OID_SKGE_SPEED_CAP. - * - * Revision 1.53 2002/08/09 09:45:28 rwahl - * Added support for NDIS OID_PNP_xxx. - * Editorial changes. - * - * Revision 1.52 2002/08/06 17:54:07 rwahl - * - Added speed cap to PNMI config struct. - * - * Revision 1.51 2002/07/17 19:19:26 rwahl - * - Added OID_SKGE_SPEED_MODE and OID_SKGE_SPEED_STATUS. - * - Added SK_PNMI_CNT_RX_PMACC_ERR() & SK_PNMI_CNT_RX_LONGFRAMES(). - * - Added speed mode & status to PNMI config struct. - * - Editorial changes. - * - * Revision 1.50 2002/05/22 08:59:37 rwahl - * Added string definitions for error msgs. - * - * Revision 1.49 2001/11/20 09:23:50 rwahl - * - pnmi struct: reordered and aligned to 32bit. - * - * Revision 1.48 2001/02/23 14:34:24 mkunz - * Changed macro PHYS2INST. Added pAC to Interface - * - * Revision 1.47 2001/02/07 08:28:23 mkunz - * - Added Oids: OID_SKGE_DIAG_ACTION - * OID_SKGE_DIAG_RESULT - * OID_SKGE_MULTICAST_LIST - * OID_SKGE_CURRENT_PACKET_FILTER - * OID_SKGE_INTERMEDIATE_SUPPORT - * - Changed value of OID_SKGE_MTU - * - * Revision 1.46 2001/02/06 10:01:41 mkunz - * - Pnmi V4 dual net support added. Interface functions and macros extended - * - Vpd bug fixed - * - OID_SKGE_MTU added - * - * Revision 1.45 2001/01/22 13:41:37 rassmann - * Supporting two nets on dual-port adapters. - * - * Revision 1.44 2000/09/07 07:35:27 rwahl - * - removed NDIS counter specific data type. - * - fixed spelling for OID_SKGE_RLMT_PORT_PREFERRED. - * - * Revision 1.43 2000/08/04 11:41:08 rwahl - * - Fixed compiler warning (port is always >= 0) for macros - * SK_PNMI_CNT_RX_LONGFRAMES & SK_PNMI_CNT_SYNC_OCTETS - * - * Revision 1.42 2000/08/03 15:14:07 rwahl - * - Corrected error in driver macros addressing a physical port. - * - * Revision 1.41 2000/08/01 16:22:29 rwahl - * - Changed MDB version to 3.1. - * - Added definitions for StatRxLongFrames counter. - * - Added macro to be used by driver to count long frames received. - * - Added directive to control width (default = 32bit) of NDIS statistic - * counters (SK_NDIS_64BIT_CTR). - * - * Revision 1.40 2000/03/31 13:51:34 rwahl - * Added SK_UPTR cast to offset calculation for PNMI struct fields; - * missing cast caused compiler warnings by Win64 compiler. - * - * Revision 1.39 1999/12/06 10:09:47 rwahl - * Added new error log message. - * - * Revision 1.38 1999/11/22 13:57:55 cgoos - * Changed license header to GPL. - * - * Revision 1.37 1999/09/14 14:25:32 rwahl - * Set MDB version for 1000Base-T (sensors, Master/Slave) changes. - * - * Revision 1.36 1999/05/20 09:24:56 cgoos - * Changes for 1000Base-T (sensors, Master/Slave). - * - * Revision 1.35 1999/04/13 15:10:51 mhaveman - * Replaced RLMT macros SK_RLMT_CHECK_xxx again by those of PNMI to - * grant unified interface. But PNMI macros will store the same - * value as RLMT macros. - * - * Revision 1.34 1999/04/13 15:03:49 mhaveman - * -Changed copyright - * -Removed SK_PNMI_RLMT_MODE_CHK_xxx macros. Those of RLMT should be - * used. - * - * Revision 1.33 1999/03/23 10:41:02 mhaveman - * Changed comments. - * - * Revision 1.32 1999/01/25 15:01:33 mhaveman - * Added support for multiple simultaniously active ports. - * - * Revision 1.31 1999/01/19 10:06:26 mhaveman - * Added new error log message. - * - * Revision 1.30 1999/01/05 10:34:49 mhaveman - * Fixed little error in RlmtChangeEstimate calculation. - * - * Revision 1.29 1999/01/05 09:59:41 mhaveman - * Redesigned port switch average calculation to avoid 64bit - * arithmetic. - * - * Revision 1.28 1998/12/08 10:05:48 mhaveman - * Defined macro SK_PNMI_MIN_STRUCT_SIZE. - * - * Revision 1.27 1998/12/03 14:39:35 mhaveman - * Fixed problem that LSTAT was enumerated wrong. - * - * Revision 1.26 1998/12/03 11:19:51 mhaveman - * Changed contents of errlog message SK_PNMI_ERR016MSG - * - * Revision 1.25 1998/12/01 10:40:04 mhaveman - * Changed size of SensorNumber, ChecksumNumber and RlmtPortNumber in - * SK_PNMI_STRUCT_DATA to be conform with OID definition. - * - * Revision 1.24 1998/11/20 08:09:27 mhaveman - * Added macros to convert between logical, physical port indexes and - * instances. - * - * Revision 1.23 1998/11/10 13:41:13 mhaveman - * Needed to change interface, because NT driver needs a return value - * of needed buffer space on TOO_SHORT errors. Therefore all - * SkPnmiGet/Preset/Set functions now have a pointer to the length - * parameter, where the needed space on error is returned. - * - * Revision 1.22 1998/11/03 12:05:51 mhaveman - * Added pAC parameter to counter macors. - * - * Revision 1.21 1998/11/02 10:47:36 mhaveman - * Added syslog messages for internal errors. - * - * Revision 1.20 1998/10/30 15:49:36 mhaveman - * -Removed unused SK_PNMI_UTILIZATION_BASE and EstOldCnt. - * -Redefined SK_PNMI_CHG_EST_BASE to hundreds of seconds. - * - * Revision 1.19 1998/10/29 15:38:44 mhaveman - * Changed string lengths of PNMI_STRUCT_DATA structure because - * string OIDs are now encoded with leading length ocetet. - * - * Revision 1.18 1998/10/29 08:52:27 mhaveman - * -Added byte to strings in PNMI_STRUCT_DATA structure. - * -Shortened SK_PNMI_RLMT structure to SK_MAX_MACS elements. - * - * Revision 1.17 1998/10/28 08:49:50 mhaveman - * -Changed type of Instance back to SK_U32 because of VPD - * -Changed type from SK_U8 to char of PciBusSpeed, PciBusWidth, PMD, - * and Connector. - * - * Revision 1.16 1998/10/22 10:42:31 mhaveman - * -Removed (SK_U32) casts for OIDs - * -excluded NDIS OIDs when they are already defined with ifndef _NDIS_ - * - * Revision 1.15 1998/10/20 13:56:28 mhaveman - * Headerfile includes now directly other header files to comile correctly. - * - * Revision 1.14 1998/10/20 07:31:09 mhaveman - * Made type changes to unsigned int where possible. - * - * Revision 1.13 1998/10/19 10:53:13 mhaveman - * -Casted OID definitions to SK_U32 - * -Renamed RlmtMAC... to RlmtPort... - * -Changed wrong type of VpdEntriesList from SK_U32 to char * - * - * Revision 1.12 1998/10/13 07:42:27 mhaveman - * -Added OIDs OID_SKGE_TRAP_NUMBER and OID_SKGE_ALL_DATA - * -Removed old cvs history entries - * -Renamed MacNumber to PortNumber - * - * Revision 1.11 1998/10/07 10:55:24 mhaveman - * -Added OID_MDB_VERSION. Therefore was a renumbering of the VPD OIDs - * necessary. - * -Added OID_GEN_ Ids to support the windows driver. - * - * Revision 1.10 1998/09/30 13:41:10 mhaveman - * Renamed some OIDs to reduce usage of 'MAC' which is replaced by 'PORT'. - * - * Revision 1.9 1998/09/04 17:06:17 mhaveman - * -Added SyncCounter as macro. - * -Renamed OID_SKGE_.._NO_DESCR_CTS to OID_SKGE_.._NO_BUF_CTS. - * -Added macros for driver description and version strings. - * - * Revision 1.8 1998/09/04 14:36:52 mhaveman - * Added OIDs and Structure to access value of macro counters which are - * counted by the driver. - * - * Revision 1.7 1998/09/04 11:59:36 mhaveman - * Everything compiles now. Driver Macros for counting still missing. - * - ****************************************************************************/ - #ifndef _SKGEPNMI_H_ #define _SKGEPNMI_H_ @@ -239,7 +33,7 @@ #include "h/sktypes.h" #include "h/skerror.h" #include "h/sktimer.h" -#include "h/ski2c.h" +#include "h/sktwsi.h" #include "h/skaddr.h" #include "h/skrlmt.h" #include "h/skvpd.h" @@ -249,7 +43,6 @@ */ #define SK_PNMI_MDB_VERSION 0x00030001 /* 3.1 */ - /* * Event definitions */ @@ -262,16 +55,13 @@ #define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */ #define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */ #define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */ - #define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */ #define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */ #define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */ #define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */ #define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */ -#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* 1. Parameter is number of nets - 1 = single net; 2 = dual net */ -#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */ - +#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* Number of nets (1 or 2). */ +#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */ /* * Return values @@ -284,7 +74,7 @@ #define SK_PNMI_ERR_UNKNOWN_OID 5 #define SK_PNMI_ERR_UNKNOWN_INST 6 #define SK_PNMI_ERR_UNKNOWN_NET 7 - +#define SK_PNMI_ERR_NOT_SUPPORTED 10 /* * Return values of driver reset function SK_DRIVER_RESET() and @@ -293,19 +83,17 @@ #define SK_PNMI_ERR_OK 0 #define SK_PNMI_ERR_FAIL 1 - /* * Return values of driver test function SK_DRIVER_SELFTEST() */ #define SK_PNMI_TST_UNKNOWN (1 << 0) -#define SK_PNMI_TST_TRANCEIVER (1 << 1) +#define SK_PNMI_TST_TRANCEIVER (1 << 1) #define SK_PNMI_TST_ASIC (1 << 2) #define SK_PNMI_TST_SENSOR (1 << 3) -#define SK_PNMI_TST_POWERMGMT (1 << 4) +#define SK_PNMI_TST_POWERMGMT (1 << 4) #define SK_PNMI_TST_PCI (1 << 5) #define SK_PNMI_TST_MAC (1 << 6) - /* * RLMT specific definitions */ @@ -355,7 +143,7 @@ /* #define OID_802_3_MULTICAST_LIST 0x01010103 */ /* #define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 */ /* #define OID_802_3_MAC_OPTIONS 0x01010105 */ - + #define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101 #define OID_802_3_XMIT_ONE_COLLISION 0x01020102 #define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103 @@ -389,7 +177,7 @@ #define OID_SKGE_VPD_VALUE 0xFF010106 #define OID_SKGE_VPD_ACCESS 0xFF010107 #define OID_SKGE_VPD_ACTION 0xFF010108 - + #define OID_SKGE_PORT_NUMBER 0xFF010110 #define OID_SKGE_DEVICE_TYPE 0xFF010111 #define OID_SKGE_DRIVER_DESCR 0xFF010112 @@ -430,13 +218,25 @@ #define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141 #define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142 #define OID_SKGE_RLMT_PORT_PREFERRED 0xFF010143 -#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160 + +#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150 +#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151 +#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152 +#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153 +#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154 +#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155 + +#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160 +#define OID_SKGE_SET_TEAM_MAC_ADDRESS 0xFF010161 +#define OID_SKGE_DEVICE_INFORMATION 0xFF010162 #define OID_SKGE_SPEED_CAP 0xFF010170 #define OID_SKGE_SPEED_MODE 0xFF010171 #define OID_SKGE_SPEED_STATUS 0xFF010172 -#define OID_SKGE_SENSOR_NUMBER 0xFF020100 +#define OID_SKGE_BOARDLEVEL 0xFF010180 + +#define OID_SKGE_SENSOR_NUMBER 0xFF020100 #define OID_SKGE_SENSOR_INDEX 0xFF020101 #define OID_SKGE_SENSOR_DESCR 0xFF020102 #define OID_SKGE_SENSOR_TYPE 0xFF020103 @@ -527,13 +327,6 @@ #define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168 #define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169 -#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150 -#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151 -#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152 -#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153 -#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154 -#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155 - #define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170 #define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171 #define OID_SKGE_TX_RETRY 0xFF020172 @@ -554,27 +347,98 @@ #define OID_SKGE_ALL_DATA 0xFF020190 /* Defines for VCT. */ -#define OID_SKGE_VCT_GET 0xFF020200 -#define OID_SKGE_VCT_SET 0xFF020201 -#define OID_SKGE_VCT_STATUS 0xFF020202 +#define OID_SKGE_VCT_GET 0xFF020200 +#define OID_SKGE_VCT_SET 0xFF020201 +#define OID_SKGE_VCT_STATUS 0xFF020202 +#define OID_SKGE_VCT_CAPABILITIES 0xFF020203 + +#ifdef SK_DIAG_SUPPORT +/* Defines for driver DIAG mode. */ +#define OID_SKGE_DIAG_MODE 0xFF020204 +#endif /* SK_DIAG_SUPPORT */ + +/* New OIDs */ +#define OID_SKGE_DRIVER_RELDATE 0xFF020210 +#define OID_SKGE_DRIVER_FILENAME 0xFF020211 +#define OID_SKGE_CHIPID 0xFF020212 +#define OID_SKGE_RAMSIZE 0xFF020213 +#define OID_SKGE_VAUXAVAIL 0xFF020214 +#define OID_SKGE_PHY_TYPE 0xFF020215 +#define OID_SKGE_PHY_LP_MODE 0xFF020216 + +/* + * Added for new DualNet IM driver V2 + * these OIDs should later be in pnmi.h + */ +#define OID_SKGE_MAC_COUNT 0xFF020217 +#define OID_SKGE_DUALNET_MODE 0xFF020218 +#define OID_SKGE_SET_TAGHEADER 0xFF020219 + +#ifdef SK_ASF +/* Defines for ASF */ +#define OID_SKGE_ASF 0xFF02021a +#define OID_SKGE_ASF_STORE_CONFIG 0xFF02021b +#define OID_SKGE_ASF_ENA 0xFF02021c +#define OID_SKGE_ASF_RETRANS 0xFF02021d +#define OID_SKGE_ASF_RETRANS_INT 0xFF02021e +#define OID_SKGE_ASF_HB_ENA 0xFF02021f +#define OID_SKGE_ASF_HB_INT 0xFF020220 +#define OID_SKGE_ASF_WD_ENA 0xFF020221 +#define OID_SKGE_ASF_WD_TIME 0xFF020222 +#define OID_SKGE_ASF_IP_SOURCE 0xFF020223 +#define OID_SKGE_ASF_MAC_SOURCE 0xFF020224 +#define OID_SKGE_ASF_IP_DEST 0xFF020225 +#define OID_SKGE_ASF_MAC_DEST 0xFF020226 +#define OID_SKGE_ASF_COMMUNITY_NAME 0xFF020227 +#define OID_SKGE_ASF_RSP_ENA 0xFF020228 +#define OID_SKGE_ASF_RETRANS_COUNT_MIN 0xFF020229 +#define OID_SKGE_ASF_RETRANS_COUNT_MAX 0xFF02022a +#define OID_SKGE_ASF_RETRANS_INT_MIN 0xFF02022b +#define OID_SKGE_ASF_RETRANS_INT_MAX 0xFF02022c +#define OID_SKGE_ASF_HB_INT_MIN 0xFF02022d +#define OID_SKGE_ASF_HB_INT_MAX 0xFF02022e +#define OID_SKGE_ASF_WD_TIME_MIN 0xFF02022f +#define OID_SKGE_ASF_WD_TIME_MAX 0xFF020230 +#define OID_SKGE_ASF_HB_CAP 0xFF020231 +#define OID_SKGE_ASF_WD_TIMER_RES 0xFF020232 +#define OID_SKGE_ASF_GUID 0xFF020233 +#define OID_SKGE_ASF_KEY_OP 0xFF020234 +#define OID_SKGE_ASF_KEY_ADM 0xFF020235 +#define OID_SKGE_ASF_KEY_GEN 0xFF020236 +#define OID_SKGE_ASF_CAP 0xFF020237 +#define OID_SKGE_ASF_PAR_1 0xFF020238 +#define OID_SKGE_ASF_OVERALL_OID 0xFF020239 +#endif /* SK_ASF */ + + +// Defined for yukon2 path only +#define OID_SKGE_UPPER_MINIPORT 0xFF02023D + + +#ifdef SK_ASF +/* Defines for ASF */ +#define OID_SKGE_ASF_FWVER_OID 0xFF020240 +#define OID_SKGE_ASF_ACPI_OID 0xFF020241 +#define OID_SKGE_ASF_SMBUS_OID 0xFF020242 +#endif /* SK_ASF */ /* VCT struct to store a backup copy of VCT data after a port reset. */ typedef struct s_PnmiVct { SK_U8 VctStatus; - SK_U8 PCableLen; - SK_U32 PMdiPairLen[4]; - SK_U8 PMdiPairSts[4]; + SK_U8 CableLen; + SK_U32 MdiPairLen[4]; + SK_U8 MdiPairSts[4]; } SK_PNMI_VCT; /* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */ -#define SK_PNMI_VCT_NONE 0 -#define SK_PNMI_VCT_OLD_VCT_DATA 1 -#define SK_PNMI_VCT_NEW_VCT_DATA 2 -#define SK_PNMI_VCT_OLD_DSP_DATA 4 -#define SK_PNMI_VCT_NEW_DSP_DATA 8 -#define SK_PNMI_VCT_RUNNING 16 +#define SK_PNMI_VCT_NONE 0x00 +#define SK_PNMI_VCT_OLD_VCT_DATA 0x01 +#define SK_PNMI_VCT_NEW_VCT_DATA 0x02 +#define SK_PNMI_VCT_OLD_DSP_DATA 0x04 +#define SK_PNMI_VCT_NEW_DSP_DATA 0x08 +#define SK_PNMI_VCT_RUNNING 0x10 /* VCT cable test status. */ @@ -582,7 +446,12 @@ typedef struct s_PnmiVct { #define SK_PNMI_VCT_SHORT_CABLE 1 #define SK_PNMI_VCT_OPEN_CABLE 2 #define SK_PNMI_VCT_TEST_FAIL 3 -#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4 +#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4 +#define SK_PNMI_VCT_NOT_PRESENT 5 + +/* VCT capabilities (needed for OID_SKGE_VCT_CAPABILITIES. */ +#define SK_PNMI_VCT_SUPPORTED 1 +#define SK_PNMI_VCT_NOT_SUPPORTED 0 #define OID_SKGE_TRAP_SEN_WAR_LOW 500 #define OID_SKGE_TRAP_SEN_WAR_UPP 501 @@ -594,6 +463,22 @@ typedef struct s_PnmiVct { #define OID_SKGE_TRAP_RLMT_PORT_UP 523 #define OID_SKGE_TRAP_RLMT_SEGMENTATION 524 +#ifdef SK_DIAG_SUPPORT +/* Defines for driver DIAG mode. */ +#define SK_DIAG_ATTACHED 2 +#define SK_DIAG_RUNNING 1 +#define SK_DIAG_IDLE 0 +#endif /* SK_DIAG_SUPPORT */ + +/* + * Generic PNMI IOCTL subcommand definitions. + */ +#define SK_GET_SINGLE_VAR 1 +#define SK_SET_SINGLE_VAR 2 +#define SK_PRESET_SINGLE_VAR 3 +#define SK_GET_FULL_MIB 4 +#define SK_SET_FULL_MIB 5 +#define SK_PRESET_FULL_MIB 6 /* * Define error numbers and messages for syslog @@ -627,7 +512,7 @@ typedef struct s_PnmiVct { #define SK_PNMI_ERR014 (SK_ERRBASE_PNMI + 14) #define SK_PNMI_ERR014MSG "Vpd: Cannot read VPD keys" #define SK_PNMI_ERR015 (SK_ERRBASE_PNMI + 15) -#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys to small" +#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys too small" #define SK_PNMI_ERR016 (SK_ERRBASE_PNMI + 16) #define SK_PNMI_ERR016MSG "Vpd: Key string too long" #define SK_PNMI_ERR017 (SK_ERRBASE_PNMI + 17) @@ -669,9 +554,9 @@ typedef struct s_PnmiVct { #define SK_PNMI_ERR036 (SK_ERRBASE_PNMI + 36) #define SK_PNMI_ERR036MSG "" #define SK_PNMI_ERR037 (SK_ERRBASE_PNMI + 37) -#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event return not 0" +#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event returned not 0" #define SK_PNMI_ERR038 (SK_ERRBASE_PNMI + 38) -#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event return not 0" +#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event returned not 0" #define SK_PNMI_ERR039 (SK_ERRBASE_PNMI + 39) #define SK_PNMI_ERR039MSG "RlmtStat: Unknown OID" #define SK_PNMI_ERR040 (SK_ERRBASE_PNMI + 40) @@ -689,9 +574,9 @@ typedef struct s_PnmiVct { #define SK_PNMI_ERR046 (SK_ERRBASE_PNMI + 46) #define SK_PNMI_ERR046MSG "Monitor: Unknown OID" #define SK_PNMI_ERR047 (SK_ERRBASE_PNMI + 47) -#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returns not 0" +#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returned not 0" #define SK_PNMI_ERR048 (SK_ERRBASE_PNMI + 48) -#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returns not 0" +#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returned not 0" #define SK_PNMI_ERR049 (SK_ERRBASE_PNMI + 49) #define SK_PNMI_ERR049MSG "SkPnmiInit: Invalid size of 'CounterOffset' struct!!" #define SK_PNMI_ERR050 (SK_ERRBASE_PNMI + 50) @@ -700,6 +585,14 @@ typedef struct s_PnmiVct { #define SK_PNMI_ERR051MSG "SkPnmiEvent: Port switch suspicious" #define SK_PNMI_ERR052 (SK_ERRBASE_PNMI + 52) #define SK_PNMI_ERR052MSG "" +#define SK_PNMI_ERR053 (SK_ERRBASE_PNMI + 53) +#define SK_PNMI_ERR053MSG "General: Driver release date not initialized" +#define SK_PNMI_ERR054 (SK_ERRBASE_PNMI + 54) +#define SK_PNMI_ERR054MSG "General: Driver release date string too long" +#define SK_PNMI_ERR055 (SK_ERRBASE_PNMI + 55) +#define SK_PNMI_ERR055MSG "General: Driver file name not initialized" +#define SK_PNMI_ERR056 (SK_ERRBASE_PNMI + 56) +#define SK_PNMI_ERR056MSG "General: Driver file name string too long" /* * Management counter macros called by the driver @@ -710,6 +603,11 @@ typedef struct s_PnmiVct { #define SK_PNMI_SET_DRIVER_VER(pAC,v) ((pAC)->Pnmi.pDriverVersion = \ (char *)(v)) +#define SK_PNMI_SET_DRIVER_RELDATE(pAC,v) ((pAC)->Pnmi.pDriverReleaseDate = \ + (char *)(v)) + +#define SK_PNMI_SET_DRIVER_FILENAME(pAC,v) ((pAC)->Pnmi.pDriverFileName = \ + (char *)(v)) #define SK_PNMI_CNT_TX_QUEUE_LEN(pAC,v,p) \ { \ @@ -886,6 +784,8 @@ typedef struct s_PnmiConf { char ConfMacFactoryAddr[6]; SK_U8 ConfPMD; SK_U8 ConfConnector; + SK_U32 ConfPhyType; + SK_U32 ConfPhyMode; SK_U8 ConfLinkCapability; SK_U8 ConfLinkMode; SK_U8 ConfLinkModeStatus; @@ -934,9 +834,14 @@ typedef struct s_PnmiStrucData { SK_U32 DeviceType; char DriverDescr[SK_PNMI_STRINGLEN1]; char DriverVersion[SK_PNMI_STRINGLEN2]; + char DriverReleaseDate[SK_PNMI_STRINGLEN1]; + char DriverFileName[SK_PNMI_STRINGLEN1]; char HwDescr[SK_PNMI_STRINGLEN1]; char HwVersion[SK_PNMI_STRINGLEN2]; SK_U16 Chipset; + SK_U32 ChipId; + SK_U8 VauxAvail; + SK_U32 RamSize; SK_U32 MtuSize; SK_U32 Action; SK_U32 TestResult; @@ -981,23 +886,25 @@ typedef struct s_PnmiStrucData { } SK_PNMI_STRUCT_DATA; #define SK_PNMI_STRUCT_SIZE (sizeof(SK_PNMI_STRUCT_DATA)) + +/* The ReturnStatus field must be located before VpdFreeBytes! */ #define SK_PNMI_MIN_STRUCT_SIZE ((unsigned int)(SK_UPTR)\ &(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes)) - /* - * ReturnStatus field - * must be located - * before VpdFreeBytes - */ /* * Various definitions */ +#define SK_PNMI_EVT_TIMER_CHECK 28125000L /* 28125 ms */ + +#define SK_PNMI_VCT_TIMER_CHECK 4000000L /* 4 sec. */ + #define SK_PNMI_MAX_PROTOS 3 -#define SK_PNMI_CNT_NO 66 /* Must have the value of the enum - * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK - * for check while init phase 1 - */ +/* + * SK_PNMI_CNT_NO must have the value of the enum SK_PNMI_MAX_IDX. + * Define SK_PNMI_CHECK to check this during init level SK_INIT_IO. + */ +#define SK_PNMI_CNT_NO 66 /* * Estimate data structure @@ -1010,14 +917,6 @@ typedef struct s_PnmiEstimate { } SK_PNMI_ESTIMATE; -/* - * VCT timer data structure - */ -typedef struct s_VctTimer { - SK_TIMER VctTimer; -} SK_PNMI_VCT_TIMER; - - /* * PNMI specific adapter context structure */ @@ -1060,6 +959,8 @@ typedef struct s_PnmiData { char *pDriverDescription; char *pDriverVersion; + char *pDriverReleaseDate; + char *pDriverFileName; int MacUpdatedFlag; int RlmtUpdatedFlag; @@ -1086,29 +987,35 @@ typedef struct s_PnmiData { unsigned int TrapQueueEnd; unsigned int TrapBufPad; unsigned int TrapUnique; - SK_U8 VctStatus[SK_MAX_MACS]; - SK_PNMI_VCT VctBackup[SK_MAX_MACS]; - SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS]; + SK_U8 VctStatus[SK_MAX_MACS]; + SK_PNMI_VCT VctBackup[SK_MAX_MACS]; + SK_TIMER VctTimeout[SK_MAX_MACS]; +#ifdef SK_DIAG_SUPPORT + SK_U32 DiagAttached; +#endif /* SK_DIAG_SUPPORT */ + SK_BOOL VpdKeyReadError; } SK_PNMI; /* * Function prototypes */ -extern int SkPnmiInit(SK_AC *pAc, SK_IOC IoC, int level); -extern int SkPnmiGetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id, void* pBuf, +extern int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int Level); +extern int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf, unsigned int* pLen, SK_U32 Instance, SK_U32 NetIndex); -extern int SkPnmiPreSetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id, +extern int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); -extern int SkPnmiSetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id, void* pBuf, +extern int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); -extern int SkPnmiGetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf, +extern int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf, unsigned int *pLen, SK_U32 NetIndex); -extern int SkPnmiPreSetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf, +extern int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf, unsigned int *pLen, SK_U32 NetIndex); -extern int SkPnmiSetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf, +extern int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf, unsigned int *pLen, SK_U32 NetIndex); -extern int SkPnmiEvent(SK_AC *pAc, SK_IOC IoC, SK_U32 Event, +extern int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param); +extern int SkPnmiGenIoctl(SK_AC *pAC, SK_IOC IoC, void * pBuf, + unsigned int * pLen, SK_U32 NetIndex); #endif diff --git a/drivers/sk98lin/h/skgesirq.h b/drivers/sk98lin/h/skgesirq.h index fc001b2..e7f7191 100644 --- a/drivers/sk98lin/h/skgesirq.h +++ b/drivers/sk98lin/h/skgesirq.h @@ -1,124 +1,40 @@ /****************************************************************************** * * Name: skgesirq.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.26 $ - * Date: $Date: 2002/10/14 09:52:36 $ - * Purpose: SK specific Gigabit Ethernet special IRQ functions + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 2.5 $ + * Date: $Date: 2005/12/14 16:11:35 $ + * Purpose: Gigabit Ethernet special IRQ functions * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2002 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2005 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * $Log: skgesirq.h,v $ - * Revision 1.26 2002/10/14 09:52:36 rschmidt - * Added SKERR_SIRQ_E023 and SKERR_SIRQ_E023 for GPHY (Yukon) - * Editorial changes - * - * Revision 1.25 2002/07/15 18:15:52 rwahl - * Editorial changes. - * - * Revision 1.24 2002/07/15 15:39:21 rschmidt - * Corrected define for SKERR_SIRQ_E022 - * Editorial changes - * - * Revision 1.23 2002/04/25 11:09:45 rschmidt - * Removed declarations for SkXmInitPhy(), SkXmRxTxEnable() - * Editorial changes - * - * Revision 1.22 2000/11/09 11:30:10 rassmann - * WA: Waiting after releasing reset until BCom chip is accessible. - * - * Revision 1.21 2000/10/18 12:22:40 cgoos - * Added workaround for half duplex hangup. - * - * Revision 1.20 1999/12/06 10:00:44 cgoos - * Added SET event for role. - * - * Revision 1.19 1999/11/22 13:58:26 cgoos - * Changed license header to GPL. - * - * Revision 1.18 1999/05/19 07:32:59 cgoos - * Changes for 1000Base-T. - * - * Revision 1.17 1999/03/12 13:29:31 malthoff - * Move Autonegotiation Error Codes to skgeinit.h. - * - * Revision 1.16 1999/03/08 10:11:28 gklug - * add: AutoNegDone return codes - * - * Revision 1.15 1998/11/18 13:20:53 gklug - * add: different timeouts for active and non-active links - * - * Revision 1.14 1998/11/04 07:18:14 cgoos - * Added prototype for SkXmRxTxEnable. - * - * Revision 1.13 1998/10/21 05:52:23 gklug - * add: parameter DoLoop to InitPhy function - * - * Revision 1.12 1998/10/19 06:45:03 cgoos - * Added prototype for SkXmInitPhy. - * - * Revision 1.11 1998/10/15 14:34:10 gklug - * add: WA_TIME is 500 msec - * - * Revision 1.10 1998/10/14 14:49:41 malthoff - * Remove err log defines E021 and E022. They are - * defined in skgeinit.h now. - * - * Revision 1.9 1998/10/14 14:00:39 gklug - * add: error logs for init phys - * - * Revision 1.8 1998/10/14 05:44:05 gklug - * add: E020 - * - * Revision 1.7 1998/10/02 06:24:58 gklug - * add: error messages - * - * Revision 1.6 1998/10/01 07:54:45 gklug - * add: PNMI debug module - * - * Revision 1.5 1998/09/28 13:36:31 malthoff - * Move the bit definitions for Autonegotiation - * and Flow Control to skgeinit.h. - * - * Revision 1.4 1998/09/15 12:29:34 gklug - * add: error logs - * - * Revision 1.3 1998/09/03 13:54:02 gklug - * add: function prototypes - * - * Revision 1.2 1998/09/03 10:24:36 gklug - * add: Events send by PNMI - * add: parameter definition for Flow Control etc. - * - * Revision 1.1 1998/08/27 11:50:27 gklug - * initial revision - * + * /LICENSE * ******************************************************************************/ #ifndef _INC_SKGESIRQ_H_ #define _INC_SKGESIRQ_H_ +/* Define return codes of SkGePortCheckUp and CheckShort */ +#define SK_HW_PS_NONE 0 /* No action needed */ +#define SK_HW_PS_RESTART 1 /* Restart needed */ +#define SK_HW_PS_LINK 2 /* Link Up actions needed */ + /* * Define the Event the special IRQ/INI module can handle */ -#define SK_HWEV_WATIM 1 /* Timeout for WA errata #2 XMAC */ +#define SK_HWEV_WATIM 1 /* Timeout for WA Errata #2 XMAC */ #define SK_HWEV_PORT_START 2 /* Port Start Event by RLMT */ #define SK_HWEV_PORT_STOP 3 /* Port Stop Event by RLMT */ #define SK_HWEV_CLEAR_STAT 4 /* Clear Statistics by PNMI */ @@ -129,10 +45,10 @@ #define SK_HWEV_SET_SPEED 9 /* Set Link Speed by PNMI */ #define SK_HWEV_HALFDUP_CHK 10 /* Half Duplex Hangup Workaround */ -#define SK_WA_ACT_TIME (5000000L) /* 5 sec */ -#define SK_WA_INA_TIME (100000L) /* 100 msec */ +#define SK_WA_ACT_TIME 1000000UL /* 1000 msec (1 sec) */ +#define SK_WA_INA_TIME 100000UL /* 100 msec */ -#define SK_HALFDUP_CHK_TIME (10000L) /* 10 msec */ +#define SK_HALFDUP_CHK_TIME 10000UL /* 10 msec */ /* * Define the error numbers and messages @@ -160,9 +76,9 @@ #define SKERR_SIRQ_E011 (SKERR_SIRQ_E010+1) #define SKERR_SIRQ_E011MSG "CHECK failure XA2" #define SKERR_SIRQ_E012 (SKERR_SIRQ_E011+1) -#define SKERR_SIRQ_E012MSG "unexpected IRQ Master error" +#define SKERR_SIRQ_E012MSG "Unexpected IRQ Master error" #define SKERR_SIRQ_E013 (SKERR_SIRQ_E012+1) -#define SKERR_SIRQ_E013MSG "unexpected IRQ Status error" +#define SKERR_SIRQ_E013MSG "Unexpected IRQ Status error" #define SKERR_SIRQ_E014 (SKERR_SIRQ_E013+1) #define SKERR_SIRQ_E014MSG "Parity error on RAM (read)" #define SKERR_SIRQ_E015 (SKERR_SIRQ_E014+1) @@ -185,10 +101,37 @@ #define SKERR_SIRQ_E023MSG "Auto-negotiation error" #define SKERR_SIRQ_E024 (SKERR_SIRQ_E023+1) #define SKERR_SIRQ_E024MSG "FIFO overflow error" +#define SKERR_SIRQ_E025 (SKERR_SIRQ_E024+1) +#define SKERR_SIRQ_E025MSG "2 Pair Downshift detected" +#define SKERR_SIRQ_E026 (SKERR_SIRQ_E025+1) +#define SKERR_SIRQ_E026MSG "Uncorrectable PCI Express error" +#define SKERR_SIRQ_E027 (SKERR_SIRQ_E026+1) +#define SKERR_SIRQ_E027MSG "PCI Bus Abort detected" +#define SKERR_SIRQ_E028 (SKERR_SIRQ_E027+1) +#define SKERR_SIRQ_E028MSG "Parity error on RAM 1 (read)" +#define SKERR_SIRQ_E029 (SKERR_SIRQ_E028+1) +#define SKERR_SIRQ_E029MSG "Parity error on RAM 1 (write)" +#define SKERR_SIRQ_E030 (SKERR_SIRQ_E029+1) +#define SKERR_SIRQ_E030MSG "Parity error on RAM 2 (read)" +#define SKERR_SIRQ_E031 (SKERR_SIRQ_E030+1) +#define SKERR_SIRQ_E031MSG "Parity error on RAM 2 (write)" +#define SKERR_SIRQ_E032 (SKERR_SIRQ_E031+1) +#define SKERR_SIRQ_E032MSG "TCP segmentation error async. queue 1" +#define SKERR_SIRQ_E033 (SKERR_SIRQ_E032+1) +#define SKERR_SIRQ_E033MSG "TCP segmentation error sync. queue 1" +#define SKERR_SIRQ_E034 (SKERR_SIRQ_E033+1) +#define SKERR_SIRQ_E034MSG "TCP segmentation error async. queue 2" +#define SKERR_SIRQ_E035 (SKERR_SIRQ_E034+1) +#define SKERR_SIRQ_E035MSG "TCP segmentation error sync. queue 2" +#define SKERR_SIRQ_E036 (SKERR_SIRQ_E035+1) +#define SKERR_SIRQ_E036MSG "CHECK failure polling unit" extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus); extern int SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para); extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port); extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port); +extern void SkGeYuSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus); +extern void SkYuk2SirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus); #endif /* _INC_SKGESIRQ_H_ */ + diff --git a/drivers/sk98lin/h/skgetwsi.h b/drivers/sk98lin/h/skgetwsi.h new file mode 100644 index 0000000..c12133a --- /dev/null +++ b/drivers/sk98lin/h/skgetwsi.h @@ -0,0 +1,243 @@ +/****************************************************************************** + * + * Name: skgetwsi.h + * Project: Gigabit Ethernet Adapters, TWSI-Module + * Version: $Revision: 1.8 $ + * Date: $Date: 2005/12/14 16:10:53 $ + * Purpose: Special defines for TWSI + * + ******************************************************************************/ + +/****************************************************************************** + * + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2004 Marvell. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * The information in this file is provided "AS IS" without warranty. + * /LICENSE + * + ******************************************************************************/ + +/* + * SKGETWSI.H contains all SK-98xx specific defines for the TWSI handling + */ + +#ifndef _INC_SKGETWSI_H_ +#define _INC_SKGETWSI_H_ + +/* + * Macros to access the B2_I2C_CTRL + */ +#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \ + SK_OUT32(IoC, B2_I2C_CTRL,\ + (flag ? 0x80000000UL : 0x0L) | \ + (((SK_U32)reg << 16) & I2C_ADDR) | \ + (((SK_U32)dev << 9) & I2C_DEV_SEL) | \ + (dev_size & I2C_DEV_SIZE) | \ + ((burst << 4) & I2C_BURST_LEN)) + +#define SK_I2C_STOP(IoC) { \ + SK_U32 I2cCtrl; \ + SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \ + SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \ +} + +#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl) + +/* + * Macros to access the TWSI SW Registers + */ +#define SK_I2C_SET_BIT(IoC, SetBits) { \ + SK_U8 OrgBits; \ + SK_IN8(IoC, B2_I2C_SW, &OrgBits); \ + SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \ +} + +#define SK_I2C_CLR_BIT(IoC, ClrBits) { \ + SK_U8 OrgBits; \ + SK_IN8(IoC, B2_I2C_SW, &OrgBits); \ + SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \ +} + +#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw) + +/* + * define the possible sensor states + */ +#define SK_SEN_IDLE 0 /* Idle: sensor not read */ +#define SK_SEN_VALUE 1 /* Value Read cycle */ +#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */ + +/* + * Conversion factor to convert read Voltage sensor to milli Volt + * Conversion factor to convert read Temperature sensor to 10th degree Celsius + */ +#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */ +#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */ +#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */ + +/* + * formula: counter = (22500*60)/(rpm * divisor * pulses/2) + * assuming: 6500rpm, 4 pulses, divisor 1 + */ +#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2)) + +/* + * Define sensor management data + * Maximum is reached on Genesis copper dual port and Yukon-64 + * Board specific maximum is in pAC->I2c.MaxSens + */ +#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */ +#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */ + +/* + * To watch the state machine (SM) use the timer in two ways + * instead of one as hitherto + */ +#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */ +#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */ + +/* + * Defines for the individual thresholds + */ + +#define C_PLUS_20 120 / 100 +#define C_PLUS_15 115 / 100 +#define C_PLUS_10 110 / 100 +#define C_PLUS_5 105 / 100 +#define C_MINUS_5 95 / 100 +#define C_MINUS_10 90 / 100 +#define C_MINUS_15 85 / 100 + +/* Temperature sensor */ +#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */ +#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */ +#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */ +#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */ + +/* VCC which should be 5 V */ +#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */ +#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */ +#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */ +#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */ + +/* + * VIO may be 5 V or 3.3 V. Initialization takes two parts: + * 1. Initialize lowest lower limit and highest higher limit. + * 2. After the first value is read correct the upper or the lower limit to + * the appropriate C constant. + * + * Warning limits are +-5% of the exepected voltage. + * Error limits are +-10% of the expected voltage. + */ + +/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */ + +#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */ +#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */ + /* 5000 mVolt */ +#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */ +#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */ + +#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */ + +/* correction values for the second pass */ +#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */ +#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */ + /* 3300 mVolt */ +#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */ +#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */ + +/* + * VDD voltage + */ +#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */ +#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */ +#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */ +#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */ + +/* + * PHY PLL 3V3 voltage + */ +#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */ +#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */ +#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */ +#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */ + +/* + * VAUX (YUKON only) + */ +#define SK_SEN_VAUX_3V3_VAL 3300 /* Voltage VAUX 3.3 Volt */ + +#define SK_SEN_VAUX_3V3_HIGH_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_10) +#define SK_SEN_VAUX_3V3_HIGH_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_5) +#define SK_SEN_VAUX_3V3_LOW_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_5) +#define SK_SEN_VAUX_3V3_LOW_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_10) + +#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */ + +/* + * PHY 2V5 voltage + */ +#define SK_SEN_PHY_2V5_VAL 2500 /* Voltage PHY 2.5 Volt */ + +#define SK_SEN_PHY_2V5_HIGH_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_10) +#define SK_SEN_PHY_2V5_HIGH_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_5) +#define SK_SEN_PHY_2V5_LOW_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_5) +#define SK_SEN_PHY_2V5_LOW_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_10) + +/* + * ASIC Core 1V5 voltage (YUKON only) + */ +#define SK_SEN_CORE_1V5_VAL 1500 /* Voltage ASIC Core 1.5 Volt */ + +#define SK_SEN_CORE_1V5_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_10) +#define SK_SEN_CORE_1V5_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_5) +#define SK_SEN_CORE_1V5_LOW_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_5) +#define SK_SEN_CORE_1V5_LOW_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_10) + +/* + * ASIC Core 1V2 (1V3) voltage (YUKON-2 only) + */ +#define SK_SEN_CORE_1V2_VAL 1200 /* Voltage ASIC Core 1.2 Volt */ + +#define SK_SEN_CORE_1V2_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_20) +#define SK_SEN_CORE_1V2_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_15) +#define SK_SEN_CORE_1V2_LOW_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_5) +#define SK_SEN_CORE_1V2_LOW_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_10) + +#define SK_SEN_CORE_1V3_VAL 1300 /* Voltage ASIC Core 1.3 Volt */ + +#define SK_SEN_CORE_1V3_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_15) +#define SK_SEN_CORE_1V3_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_10) +#define SK_SEN_CORE_1V3_LOW_WARN (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_5) +#define SK_SEN_CORE_1V3_LOW_ERR (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_10) + +/* + * FAN 1 speed + */ +/* assuming: 6500rpm +-15%, 4 pulses, + * warning at: 80 % + * error at: 70 % + * no upper limit + */ +#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */ +#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */ +#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */ +#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */ + +/* + * Some Voltages need dynamic thresholds + */ +#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */ +#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */ +#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */ + +extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen); +#endif /* n_INC_SKGETWSI_H */ + diff --git a/drivers/sk98lin/h/skqueue.h b/drivers/sk98lin/h/skqueue.h index bce20a7..53b56c7 100644 --- a/drivers/sk98lin/h/skqueue.h +++ b/drivers/sk98lin/h/skqueue.h @@ -1,17 +1,17 @@ /****************************************************************************** * * Name: skqueue.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.14 $ - * Date: $Date: 2002/03/15 10:52:13 $ + * Project: Gigabit Ethernet Adapters, Event Scheduler Module + * Version: $Revision: 2.3 $ + * Date: $Date: 2004/05/14 13:39:15 $ * Purpose: Defines for the Event queue * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998,1999 SysKonnect, - * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,60 +22,6 @@ * ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: skqueue.h,v $ - * Revision 1.14 2002/03/15 10:52:13 mkunz - * Added event classes for link aggregation - * - * Revision 1.13 1999/11/22 13:59:05 cgoos - * Changed license header to GPL. - * - * Revision 1.12 1998/09/08 08:48:01 gklug - * add: init level handling - * - * Revision 1.11 1998/09/03 14:15:11 gklug - * add: CSUM and HWAC Eventclass and function. - * fix: pParaPtr according to CCC - * - * Revision 1.10 1998/08/20 12:43:03 gklug - * add: typedef SK_QUEUE - * - * Revision 1.9 1998/08/19 09:50:59 gklug - * fix: remove struct keyword from c-code (see CCC) add typedefs - * - * Revision 1.8 1998/08/18 07:00:01 gklug - * fix: SK_PTR not defined use void * instead. - * - * Revision 1.7 1998/08/17 13:43:19 gklug - * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR - * - * Revision 1.6 1998/08/14 07:09:30 gklug - * fix: chg pAc -> pAC - * - * Revision 1.5 1998/08/11 14:26:44 gklug - * chg: Event Dispatcher returns now int. - * - * Revision 1.4 1998/08/11 12:15:21 gklug - * add: Error numbers of skqueue module - * - * Revision 1.3 1998/08/07 12:54:23 gklug - * fix: first compiled version - * - * Revision 1.2 1998/08/07 09:34:00 gklug - * adapt structure defs to CCC - * add: prototypes for functions - * - * Revision 1.1 1998/07/30 14:52:12 gklug - * Initial version. - * Defines Event Classes, Event structs and queue management variables. - * - * - * - ******************************************************************************/ - /* * SKQUEUE.H contains all defines and types for the event queue */ @@ -89,7 +35,7 @@ */ #define SKGE_DRV 1 /* Driver Event Class */ #define SKGE_RLMT 2 /* RLMT Event Class */ -#define SKGE_I2C 3 /* i2C Event Class */ +#define SKGE_I2C 3 /* I2C Event Class */ #define SKGE_PNMI 4 /* PNMI Event Class */ #define SKGE_CSUM 5 /* Checksum Event Class */ #define SKGE_HWAC 6 /* Hardware Access Event Class */ @@ -99,6 +45,9 @@ #define SKGE_RSF 11 /* RSF Aggregation Event Class */ #define SKGE_MARKER 12 /* MARKER Aggregation Event Class */ #define SKGE_FD 13 /* FD Distributor Event Class */ +#ifdef SK_ASF +#define SKGE_ASF 14 /* ASF Event Class */ +#endif /* * define event queue as circular buffer @@ -118,25 +67,25 @@ typedef union u_EvPara { * Event Queue * skqueue.c * events are class/value pairs - * class is addressee, e.g. RMT, PCM etc. + * class is addressee, e.g. RLMT, PNMI etc. * value is command, e.g. line state change, ring op change etc. */ typedef struct s_EventElem { - SK_U32 Class ; /* Event class */ - SK_U32 Event ; /* Event value */ - SK_EVPARA Para ; /* Event parameter */ + SK_U32 Class; /* Event class */ + SK_U32 Event; /* Event value */ + SK_EVPARA Para; /* Event parameter */ } SK_EVENTELEM; typedef struct s_Queue { SK_EVENTELEM EvQueue[SK_MAX_EVENT]; - SK_EVENTELEM *EvPut ; - SK_EVENTELEM *EvGet ; + SK_EVENTELEM *EvPut; + SK_EVENTELEM *EvGet; } SK_QUEUE; extern void SkEventInit(SK_AC *pAC, SK_IOC Ioc, int Level); extern void SkEventQueue(SK_AC *pAC, SK_U32 Class, SK_U32 Event, SK_EVPARA Para); -extern int SkEventDispatcher(SK_AC *pAC,SK_IOC Ioc); +extern int SkEventDispatcher(SK_AC *pAC, SK_IOC Ioc); /* Define Error Numbers and messages */ @@ -144,4 +93,11 @@ extern int SkEventDispatcher(SK_AC *pAC,SK_IOC Ioc); #define SKERR_Q_E001MSG "Event queue overflow" #define SKERR_Q_E002 (SKERR_Q_E001+1) #define SKERR_Q_E002MSG "Undefined event class" +#define SKERR_Q_E003 (SKERR_Q_E001+2) +#define SKERR_Q_E003MSG "Event queued in Init Level 0" +#define SKERR_Q_E004 (SKERR_Q_E001+3) +#define SKERR_Q_E004MSG "Error Reported from Event Fuction (Queue Blocked)" +#define SKERR_Q_E005 (SKERR_Q_E001+4) +#define SKERR_Q_E005MSG "Event scheduler called in Init Level 0 or 1" #endif /* _SKQUEUE_H_ */ + diff --git a/drivers/sk98lin/h/skrlmt.h b/drivers/sk98lin/h/skrlmt.h index 04d025b..36f6fca 100644 --- a/drivers/sk98lin/h/skrlmt.h +++ b/drivers/sk98lin/h/skrlmt.h @@ -2,15 +2,17 @@ * * Name: skrlmt.h * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.35 $ - * Date: $Date: 2003/01/31 14:12:41 $ + * Version: $Revision: 2.2 $ + * Date: $Date: 2005/12/14 16:11:10 $ * Purpose: Header file for Redundant Link ManagemenT. * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2001 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,131 +20,7 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: skrlmt.h,v $ - * Revision 1.35 2003/01/31 14:12:41 mkunz - * single port adapter runs now with two identical MAC addresses - * - * Revision 1.34 2002/09/23 15:13:41 rwahl - * Editorial changes. - * - * Revision 1.33 2001/07/03 12:16:48 mkunz - * New Flag ChgBcPrio (Change priority of last broadcast received) - * - * Revision 1.32 2001/02/14 14:06:31 rassmann - * Editorial changes. - * - * Revision 1.31 2001/02/05 14:25:26 rassmann - * Prepared RLMT for transparent operation. - * - * Revision 1.30 2001/01/22 13:41:39 rassmann - * Supporting two nets on dual-port adapters. - * - * Revision 1.29 2000/11/17 08:58:00 rassmann - * Moved CheckSwitch from SK_RLMT_PACKET_RECEIVED to SK_RLMT_TIM event. - * - * Revision 1.28 2000/11/09 12:24:34 rassmann - * Editorial changes. - * - * Revision 1.27 1999/11/22 13:59:56 cgoos - * Changed license header to GPL. - * - * Revision 1.26 1999/10/04 14:01:19 rassmann - * Corrected reaction to reception of BPDU frames (#10441). - * - * Revision 1.25 1999/07/20 12:53:39 rassmann - * Fixed documentation errors for lookahead macros. - * - * Revision 1.24 1999/05/28 11:15:56 rassmann - * Changed behaviour to reflect Design Spec v1.2. - * Controlling Link LED(s). - * Introduced RLMT Packet Version field in RLMT Packet. - * Newstyle lookahead macros (checking meta-information before looking at - * the packet). - * - * Revision 1.23 1999/01/28 12:50:42 rassmann - * Not using broadcast time stamps in CheckLinkState mode. - * - * Revision 1.22 1999/01/27 14:13:04 rassmann - * Monitoring broadcast traffic. - * Switching more reliably and not too early if switch is - * configured for spanning tree. - * - * Revision 1.21 1998/12/08 13:11:25 rassmann - * Stopping SegTimer at RlmtStop. - * - * Revision 1.20 1998/11/24 12:37:33 rassmann - * Implemented segmentation check. - * - * Revision 1.19 1998/11/17 13:43:06 rassmann - * Handling (logical) tx failure. - * Sending packet on logical address after PORT_SWITCH. - * - * Revision 1.18 1998/11/13 16:56:56 rassmann - * Added macro version of SkRlmtLookaheadPacket. - * - * Revision 1.17 1998/11/06 18:06:05 rassmann - * Corrected timing when RLMT checks fail. - * Clearing tx counter earlier in periodical checks. - * - * Revision 1.16 1998/11/03 13:53:50 rassmann - * RLMT should switch now (at least in mode 3). - * - * Revision 1.15 1998/10/22 11:39:52 rassmann - * Corrected signed/unsigned mismatches. - * Corrected receive list handling and address recognition. - * - * Revision 1.14 1998/10/15 15:16:36 rassmann - * Finished Spanning Tree checking. - * Checked with lint. - * - * Revision 1.13 1998/09/24 19:16:08 rassmann - * Code cleanup. - * Introduced Timer for PORT_DOWN due to no RX. - * - * Revision 1.12 1998/09/16 11:09:52 rassmann - * Syntax corrections. - * - * Revision 1.11 1998/09/15 11:28:50 rassmann - * Syntax corrections. - * - * Revision 1.10 1998/09/14 17:07:38 rassmann - * Added code for port checking via LAN. - * Changed Mbuf definition. - * - * Revision 1.9 1998/09/07 11:14:15 rassmann - * Syntax corrections. - * - * Revision 1.8 1998/09/07 09:06:08 rassmann - * Syntax corrections. - * - * Revision 1.7 1998/09/04 19:41:34 rassmann - * Syntax corrections. - * Started entering code for checking local links. - * - * Revision 1.6 1998/09/04 12:14:28 rassmann - * Interface cleanup. - * - * Revision 1.5 1998/09/02 16:55:29 rassmann - * Updated to reflect new DRV/HWAC/RLMT interface. - * - * Revision 1.4 1998/09/02 07:26:02 afischer - * typedef for SK_RLMT_PORT - * - * Revision 1.3 1998/08/27 14:29:03 rassmann - * Code cleanup. - * - * Revision 1.2 1998/08/27 14:26:25 rassmann - * Updated interface. - * - * Revision 1.1 1998/08/21 08:29:10 rassmann - * First public version. + * /LICENSE * ******************************************************************************/ @@ -169,7 +47,6 @@ #define __INC_SKRLMT_H #ifdef __cplusplus -#error C++ is not yet supported. extern "C" { #endif /* cplusplus */ @@ -296,28 +173,28 @@ unsigned *pNumBytes /* #Bytes to present to SK_RLMT_LOOKAHEAD */ *(pNumBytes) = 0; \ } \ else {\ - if ((_pAC->Rlmt.Port[_PortNum].Net->RlmtMode & SK_RLMT_TRANSPARENT) != 0) { \ - *(pNumBytes) = 0; \ - } \ - else if (IsBc) { \ - if (_pAC->Rlmt.Port[_PortNum].Net->RlmtMode != SK_RLMT_MODE_CLS) { \ - *(pNumBytes) = 6; \ - *(pOffset) = 6; \ - } \ - else { \ - *(pNumBytes) = 0; \ - } \ - } \ - else { \ - if ((PktLen) > SK_RLMT_MAX_TX_BUF_SIZE) { \ - /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \ - *(pNumBytes) = 0; \ - } \ - else { \ - *(pNumBytes) = 6; \ - *(pOffset) = 0; \ - } \ - } \ + if ((_pAC->Rlmt.Port[_PortNum].Net->RlmtMode & SK_RLMT_TRANSPARENT) != 0) { \ + *(pNumBytes) = 0; \ + } \ + else if (IsBc) { \ + if (_pAC->Rlmt.Port[_PortNum].Net->RlmtMode != SK_RLMT_MODE_CLS) { \ + *(pNumBytes) = 6; \ + *(pOffset) = 6; \ + } \ + else { \ + *(pNumBytes) = 0; \ + } \ + } \ + else { \ + if ((PktLen) > SK_RLMT_MAX_TX_BUF_SIZE) { \ + /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \ + *(pNumBytes) = 0; \ + } \ + else { \ + *(pNumBytes) = 6; \ + *(pOffset) = 0; \ + } \ + } \ } \ } @@ -516,9 +393,9 @@ typedef struct s_Rlmt { /* ----- Private part ----- */ SK_BOOL CheckSwitch; - SK_BOOL RlmtOff; /* set to zero if the Mac addresses - are equal or the second one - is zero */ + SK_BOOL RlmtOff; /* set to zero if the Mac addresses + are equal or the second one + is zero */ SK_U16 Align01; } SK_RLMT; diff --git a/drivers/sk98lin/h/sktimer.h b/drivers/sk98lin/h/sktimer.h index 36f8ccb..0addb02 100644 --- a/drivers/sk98lin/h/sktimer.h +++ b/drivers/sk98lin/h/sktimer.h @@ -1,17 +1,17 @@ /****************************************************************************** * * Name: sktimer.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.9 $ - * Date: $Date: 1999/11/22 14:00:29 $ + * Project: Gigabit Ethernet Adapters, Event Scheduler Module + * Version: $Revision: 2.1 $ + * Date: $Date: 2003/10/27 14:16:09 $ * Purpose: Defines for the timer functions * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998,1999 SysKonnect, - * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,42 +22,6 @@ * ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: sktimer.h,v $ - * Revision 1.9 1999/11/22 14:00:29 cgoos - * Changed license header to GPL. - * - * Revision 1.8 1998/09/08 08:48:02 gklug - * add: init level handling - * - * Revision 1.7 1998/08/20 12:31:29 gklug - * fix: SK_TIMCTRL needs to be defined - * - * Revision 1.6 1998/08/19 09:51:00 gklug - * fix: remove struct keyword from c-code (see CCC) add typedefs - * - * Revision 1.5 1998/08/17 13:43:21 gklug - * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR - * - * Revision 1.4 1998/08/14 07:09:31 gklug - * fix: chg pAc -> pAC - * - * Revision 1.3 1998/08/07 12:54:24 gklug - * fix: first compiled version - * - * Revision 1.2 1998/08/07 09:35:29 gklug - * add: Timer control struct for Adapters context - * add: function prototypes - * - * Revision 1.1 1998/08/05 11:27:01 gklug - * First version: adapted from SMT - * - * - ******************************************************************************/ - /* * SKTIMER.H contains all defines and types for the timer functions */ @@ -75,25 +39,25 @@ typedef struct s_Timer SK_TIMER; struct s_Timer { - SK_TIMER *TmNext ; /* linked list */ - SK_U32 TmClass ; /* Timer Event class */ - SK_U32 TmEvent ; /* Timer Event value */ - SK_EVPARA TmPara ; /* Timer Event parameter */ - SK_U32 TmDelta ; /* delta time */ - int TmActive ; /* flag : active/inactive */ -} ; + SK_TIMER *TmNext; /* linked list */ + SK_U32 TmClass; /* Timer Event class */ + SK_U32 TmEvent; /* Timer Event value */ + SK_EVPARA TmPara; /* Timer Event parameter */ + SK_U32 TmDelta; /* delta time */ + int TmActive; /* flag: active/inactive */ +}; /* * Timer control struct. * - use in Adapters context name pAC->Tim */ typedef struct s_TimCtrl { - SK_TIMER *StQueue ; /* Head of Timer queue */ -} SK_TIMCTRL ; + SK_TIMER *StQueue; /* Head of Timer queue */ +} SK_TIMCTRL; -extern void SkTimerInit(SK_AC *pAC,SK_IOC Ioc, int Level); -extern void SkTimerStop(SK_AC *pAC,SK_IOC Ioc,SK_TIMER *pTimer); -extern void SkTimerStart(SK_AC *pAC,SK_IOC Ioc,SK_TIMER *pTimer, - SK_U32 Time,SK_U32 Class,SK_U32 Event,SK_EVPARA Para); -extern void SkTimerDone(SK_AC *pAC,SK_IOC Ioc); +extern void SkTimerInit(SK_AC *pAC, SK_IOC Ioc, int Level); +extern void SkTimerStop(SK_AC *pAC, SK_IOC Ioc, SK_TIMER *pTimer); +extern void SkTimerStart(SK_AC *pAC, SK_IOC Ioc, SK_TIMER *pTimer, + SK_U32 Time, SK_U32 Class, SK_U32 Event, SK_EVPARA Para); +extern void SkTimerDone(SK_AC *pAC, SK_IOC Ioc); #endif /* _SKTIMER_H_ */ diff --git a/drivers/sk98lin/h/sktwsi.h b/drivers/sk98lin/h/sktwsi.h new file mode 100644 index 0000000..019987e --- /dev/null +++ b/drivers/sk98lin/h/sktwsi.h @@ -0,0 +1,179 @@ +/****************************************************************************** + * + * Name: sktwsi.h + * Project: Gigabit Ethernet Adapters, TWSI-Module + * Version: $Revision: 1.2 $ + * Date: $Date: 2005/12/14 16:10:53 $ + * Purpose: Defines to access Voltage and Temperature Sensor + * + ******************************************************************************/ + +/****************************************************************************** + * + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2003 Marvell. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * /LICENSE + * + ******************************************************************************/ + +/* + * SKTWSI.H contains all TWSI specific defines + */ + +#ifndef _SKTWSI_H_ +#define _SKTWSI_H_ + +typedef struct s_Sensor SK_SENSOR; + +#include "h/skgetwsi.h" + +/* + * Define the TWSI events. + */ +#define SK_I2CEV_IRQ 1 /* IRQ happened Event */ +#define SK_I2CEV_TIM 2 /* Timeout event */ +#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */ + +/* + * Define READ and WRITE Constants. + */ +#define I2C_READ 0 +#define I2C_WRITE 1 +#define I2C_BURST 1 +#define I2C_SINGLE 0 + +#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0) +#define SKERR_I2C_E001MSG "Sensor index unknown" +#define SKERR_I2C_E002 (SKERR_I2C_E001+1) +#define SKERR_I2C_E002MSG "TWSI: transfer does not complete" +#define SKERR_I2C_E003 (SKERR_I2C_E002+1) +#define SKERR_I2C_E003MSG "LM80: NAK on device send" +#define SKERR_I2C_E004 (SKERR_I2C_E003+1) +#define SKERR_I2C_E004MSG "LM80: NAK on register send" +#define SKERR_I2C_E005 (SKERR_I2C_E004+1) +#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send" +#define SKERR_I2C_E006 (SKERR_I2C_E005+1) +#define SKERR_I2C_E006MSG "Unknown event" +#define SKERR_I2C_E007 (SKERR_I2C_E006+1) +#define SKERR_I2C_E007MSG "LM80 read out of state" +#define SKERR_I2C_E008 (SKERR_I2C_E007+1) +#define SKERR_I2C_E008MSG "Unexpected sensor read completed" +#define SKERR_I2C_E009 (SKERR_I2C_E008+1) +#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range" +#define SKERR_I2C_E010 (SKERR_I2C_E009+1) +#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range" +#define SKERR_I2C_E011 (SKERR_I2C_E010+1) +#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range" +#define SKERR_I2C_E012 (SKERR_I2C_E011+1) +#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range" +#define SKERR_I2C_E013 (SKERR_I2C_E012+1) +#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor" +#define SKERR_I2C_E014 (SKERR_I2C_E013+1) +#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range" +#define SKERR_I2C_E015 (SKERR_I2C_E014+1) +#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range" +#define SKERR_I2C_E016 (SKERR_I2C_E015+1) +#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete" + +/* + * Define Timeout values + */ +#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */ +#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */ +#define SK_I2C_TIM_WATCH 1000000L /* 1 second */ + +/* + * Define trap and error log hold times + */ +#ifndef SK_SEN_ERR_TR_HOLD +#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_ERR_LOG_HOLD +#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_WARN_TR_HOLD +#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_WARN_LOG_HOLD +#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC) +#endif + +/* + * Defines for SenType + */ +#define SK_SEN_UNKNOWN 0 +#define SK_SEN_TEMP 1 +#define SK_SEN_VOLT 2 +#define SK_SEN_FAN 3 + +/* + * Define for the SenErrorFlag + */ +#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */ +#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */ +#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */ +#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */ +#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */ + +/* + * Define the Sensor struct + */ +struct s_Sensor { + char *SenDesc; /* Description */ + int SenType; /* Voltage or Temperature */ + SK_I32 SenValue; /* Current value of the sensor */ + SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */ + SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */ + SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */ + SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */ + int SenErrFlag; /* Sensor indicated an error */ + SK_BOOL SenInit; /* Is sensor initialized ? */ + SK_U64 SenErrCts; /* Error trap counter */ + SK_U64 SenWarnCts; /* Warning trap counter */ + SK_U64 SenBegErrTS; /* Begin error timestamp */ + SK_U64 SenBegWarnTS; /* Begin warning timestamp */ + SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */ + SK_U64 SenLastErrLogTS; /* Last error log timestamp */ + SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */ + SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */ + int SenState; /* Sensor State (see HW specific include) */ + int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen); + /* Sensors read function */ + SK_U16 SenReg; /* Register Address for this sensor */ + SK_U8 SenDev; /* Device Selection for this sensor */ +}; + +typedef struct s_I2c { + SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */ + int CurrSens; /* Which sensor is currently queried */ + int MaxSens; /* Max. number of sensors */ + int TimerMode; /* Use the timer also to watch the state machine */ + int InitLevel; /* Initialized Level */ +#ifndef SK_DIAG + int DummyReads; /* Number of non-checked dummy reads */ + SK_TIMER SenTimer; /* Sensors timer */ +#endif /* !SK_DIAG */ +} SK_I2C; + +extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level); +extern int SkI2cWrite(SK_AC *pAC, SK_IOC IoC, SK_U32 Data, int Dev, int Size, + int Reg, int Burst); +extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen); +#ifdef SK_DIAG +extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg, + int Burst); +#else /* !SK_DIAG */ +extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para); +extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC); +extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC); +#endif /* !SK_DIAG */ +#endif /* n_SKTWSI_H */ + diff --git a/drivers/sk98lin/h/sktypes.h b/drivers/sk98lin/h/sktypes.h index e657016..1451ebd 100644 --- a/drivers/sk98lin/h/sktypes.h +++ b/drivers/sk98lin/h/sktypes.h @@ -2,15 +2,16 @@ * * Name: sktypes.h * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.3 $ - * Date: $Date: 2003/02/25 14:16:40 $ + * Version: $Revision: 1.2.2.1 $ + * Date: $Date: 2005/04/11 09:00:53 $ * Purpose: Define data types for Linux * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2005 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,68 +21,29 @@ * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ - - /***************************************************************************** - * - * History: - * - * $Log: sktypes.h,v $ - * Revision 1.3 2003/02/25 14:16:40 mlindner - * Fix: Copyright statement - * - * Revision 1.2 1999/11/22 14:01:58 cgoos - * Changed license header to GPL. - * Now using Linux' fixed size types instead of standard types. - * - * Revision 1.1 1999/02/16 07:41:40 cgoos - * First version. - * - * - * - *****************************************************************************/ - -/****************************************************************************** - * - * Description: - * - * In this file, all data types that are needed by the common modules - * are mapped to Linux data types. - * - * - * Include File Hierarchy: - * - * - ******************************************************************************/ - + #ifndef __INC_SKTYPES_H #define __INC_SKTYPES_H +#define SK_I8 s8 /* 8 bits (1 byte) signed */ +#define SK_U8 u8 /* 8 bits (1 byte) unsigned */ +#define SK_I16 s16 /* 16 bits (2 bytes) signed */ +#define SK_U16 u16 /* 16 bits (2 bytes) unsigned */ +#define SK_I32 s32 /* 32 bits (4 bytes) signed */ +#define SK_U32 u32 /* 32 bits (4 bytes) unsigned */ +#define SK_I64 s64 /* 64 bits (8 bytes) signed */ +#define SK_U64 u64 /* 64 bits (8 bytes) unsigned */ -/* defines *******************************************************************/ +#define SK_UPTR ulong /* casting pointer <-> integral */ -/* - * Data types with a specific size. 'I' = signed, 'U' = unsigned. - */ -#define SK_I8 s8 -#define SK_U8 u8 -#define SK_I16 s16 -#define SK_U16 u16 -#define SK_I32 s32 -#define SK_U32 u32 -#define SK_I64 s64 -#define SK_U64 u64 - -#define SK_UPTR ulong /* casting pointer <-> integral */ - -/* -* Boolean type. -*/ -#define SK_BOOL SK_U8 -#define SK_FALSE 0 -#define SK_TRUE (!SK_FALSE) - -/* typedefs *******************************************************************/ - -/* function prototypes ********************************************************/ +#define SK_BOOL SK_U8 +#define SK_FALSE 0 +#define SK_TRUE (!SK_FALSE) #endif /* __INC_SKTYPES_H */ + +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ diff --git a/drivers/sk98lin/h/skversion.h b/drivers/sk98lin/h/skversion.h index ef46685..3e110ff 100644 --- a/drivers/sk98lin/h/skversion.h +++ b/drivers/sk98lin/h/skversion.h @@ -1,16 +1,17 @@ /****************************************************************************** * - * Name: version.h + * Name: skversion.h * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.4 $ - * Date: $Date: 2003/02/25 14:16:40 $ - * Purpose: SK specific Error log support + * Version: $Revision: 1.3.2.1 $ + * Date: $Date: 2005/04/11 09:00:53 $ + * Purpose: specific version strings and numbers * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2005 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,32 +22,15 @@ * ******************************************************************************/ -/****************************************************************************** - * - * History: - * $Log: skversion.h,v $ - * Revision 1.4 2003/02/25 14:16:40 mlindner - * Fix: Copyright statement - * - * Revision 1.3 2003/02/25 13:30:18 mlindner - * Add: Support for various vendors - * - * Revision 1.1.2.1 2001/09/05 13:38:30 mlindner - * Removed FILE description - * - * Revision 1.1 2001/03/06 09:25:00 mlindner - * first version - * +#define BOOT_STRING "sk98lin: Network Device Driver v8.32.2.3\n" \ + "(C)Copyright 1999-2006 Marvell(R)." +#define VER_STRING "8.32.2.3" +#define PATCHLEVEL "02" +#define DRIVER_FILE_NAME "sk98lin" +#define DRIVER_REL_DATE "Apr-27-2006" + +/******************************************************************************* * + * End of file * ******************************************************************************/ - - -static const char SysKonnectFileId[] = "@(#) (C) SysKonnect GmbH."; -static const char SysKonnectBuildNumber[] = - "@(#)SK-BUILD: 6.05 PL: 01"; - -#define BOOT_STRING "sk98lin: Network Device Driver v6.05\n" \ - "(C)Copyright 1999-2003 Marvell(R)." - -#define VER_STRING "6.05" diff --git a/drivers/sk98lin/h/skvpd.h b/drivers/sk98lin/h/skvpd.h index 1be34c5..bb67613 100644 --- a/drivers/sk98lin/h/skvpd.h +++ b/drivers/sk98lin/h/skvpd.h @@ -1,90 +1,26 @@ /****************************************************************************** * * Name: skvpd.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.15 $ - * Date: $Date: 2003/01/13 10:39:38 $ + * Project: Gigabit Ethernet Adapters, VPD-Module + * Version: $Revision: 2.6 $ + * Date: $Date: 2004/11/09 15:18:00 $ * Purpose: Defines and Macros for VPD handling * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: skvpd.h,v $ - * Revision 1.15 2003/01/13 10:39:38 rschmidt - * Replaced define for PCI device Id for YUKON with GENESIS - * Editorial changes - * - * Revision 1.14 2002/11/14 15:18:10 gheinig - * Added const specifier to key and buf parameters for VpdPara,VpdRead - * and VpdWrite. This is necessary for the Diag 7 GUI API - * - * Revision 1.13 2002/10/14 15:58:18 rschmidt - * Added entry in rom_size struct s_vpd - * Editorial changes - * - * Revision 1.12 2002/09/09 14:43:51 mkarl - * added PCI Id of Yukon for reading VPD in diag before the adapter has - * been initialized - * editorial changes - * - * Revision 1.11 2002/07/26 13:19:16 mkarl - * added support for Yukon - * added vpd_size to VPD struct - * - * Revision 1.10 2000/08/10 11:29:07 rassmann - * Editorial changes. - * Preserving 32-bit alignment in structs for the adapter context. - * Removed unused function VpdWriteDword() (#if 0). - * Made VpdReadKeyword() available for SKDIAG only. - * - * Revision 1.9 1999/11/22 14:02:27 cgoos - * Changed license header to GPL. - * - * Revision 1.8 1999/03/11 14:26:40 malthoff - * Replace __STDC__ with SK_KR_PROTO. - * - * Revision 1.7 1998/10/28 07:27:17 gklug - * rmv: SWAP macros - * add: VPD_IN/OUT8 macros - * chg: interface definition - * - * Revision 1.6 1998/10/22 10:03:44 gklug - * fix: use SK_OUT16 instead of SK_OUTW - * - * Revision 1.5 1998/10/14 07:05:31 cgoos - * Changed constants in SK_SWAP_32 to UL. - * - * Revision 1.4 1998/08/19 08:14:09 gklug - * fix: remove struct keyword as much as possible from the C-code (see CCC) - * - * Revision 1.3 1998/08/18 08:18:56 malthoff - * Modify VPD in and out macros for SK_DIAG - * - * Revision 1.2 1998/07/03 14:49:08 malthoff - * Add VPD_INxx() and VPD_OUTxx() macros for the Diagnostics tool. - * - * Revision 1.1 1998/06/19 14:08:03 malthoff - * Created. - * - * - ******************************************************************************/ - /* * skvpd.h contains Diagnostic specific defines for VPD handling */ @@ -95,7 +31,7 @@ /* * Define Resource Type Identifiers and VPD keywords */ -#define RES_ID 0x82 /* Resource Type ID String (Product Name) */ +#define RES_ID 0x82 /* Resource Type ID String (Product Name) */ #define RES_VPD_R 0x90 /* start of VPD read only area */ #define RES_VPD_W 0x91 /* start of VPD read/write area */ #define RES_END 0x78 /* Resource Type End Tag */ @@ -104,14 +40,16 @@ #define VPD_NAME "Name" /* Product Name, VPD name of RES_ID */ #endif /* VPD_NAME */ #define VPD_PN "PN" /* Adapter Part Number */ -#define VPD_EC "EC" /* Adapter Engineering Level */ +#define VPD_EC "EC" /* Adapter Engineering Level */ #define VPD_MN "MN" /* Manufacture ID */ #define VPD_SN "SN" /* Serial Number */ #define VPD_CP "CP" /* Extended Capability */ #define VPD_RV "RV" /* Checksum and Reserved */ -#define VPD_YA "YA" /* Asset Tag Identifier */ +#define VPD_YA "YA" /* Asset Tag Identifier */ #define VPD_VL "VL" /* First Error Log Message (SK specific) */ #define VPD_VF "VF" /* Second Error Log Message (SK specific) */ +#define VPD_VB "VB" /* Boot Agent ROM Configuration (SK specific) */ +#define VPD_VE "VE" /* EFI UNDI Configuration (SK specific) */ #define VPD_RW "RW" /* Remaining Read / Write Area */ /* 'type' values for vpd_setup_para() */ @@ -119,7 +57,7 @@ #define VPD_RW_KEY 2 /* RW keys are "Yx", "Vx", and "RW" */ /* 'op' values for vpd_setup_para() */ -#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */ +#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */ #define OWR_KEY 2 /* overwrite key if already exists */ /* @@ -128,18 +66,18 @@ #define VPD_DEV_ID_GENESIS 0x4300 -#define VPD_SIZE_YUKON 256 -#define VPD_SIZE_GENESIS 512 -#define VPD_SIZE 512 +#define VPD_SIZE_YUKON 256 +#define VPD_SIZE_GENESIS 512 +#define VPD_SIZE 512 #define VPD_READ 0x0000 #define VPD_WRITE 0x8000 #define VPD_STOP(pAC,IoC) VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG,VPD_WRITE) -#define VPD_GET_RES_LEN(p) ((unsigned int) \ - (* (SK_U8 *)&(p)[1]) |\ - ((* (SK_U8 *)&(p)[2]) << 8)) -#define VPD_GET_VPD_LEN(p) ((unsigned int)(* (SK_U8 *)&(p)[2])) +#define VPD_GET_RES_LEN(p) ((unsigned int)\ + (*(SK_U8 *)&(p)[1]) |\ + ((*(SK_U8 *)&(p)[2]) << 8)) +#define VPD_GET_VPD_LEN(p) ((unsigned int)(*(SK_U8 *)&(p)[2])) #define VPD_GET_VAL(p) ((char *)&(p)[3]) #define VPD_MAX_LEN 50 @@ -190,7 +128,7 @@ typedef struct s_vpd_key { /* * System specific VPD macros */ -#ifndef SKDIAG +#ifndef SK_DIAG #ifndef VPD_DO_IO #define VPD_OUT8(pAC,IoC,Addr,Val) (void)SkPciWriteCfgByte(pAC,Addr,Val) #define VPD_OUT16(pAC,IoC,Addr,Val) (void)SkPciWriteCfgWord(pAC,Addr,Val) @@ -199,61 +137,61 @@ typedef struct s_vpd_key { #define VPD_IN16(pAC,IoC,Addr,pVal) (void)SkPciReadCfgWord(pAC,Addr,pVal) #define VPD_IN32(pAC,IoC,Addr,pVal) (void)SkPciReadCfgDWord(pAC,Addr,pVal) #else /* VPD_DO_IO */ -#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(Addr),Val) -#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(Addr),Val) -#define VPD_OUT32(pAC,IoC,Addr,Val) SK_OUT32(IoC,PCI_C(Addr),Val) -#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(Addr),pVal) -#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(Addr),pVal) -#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(Addr),pVal) +#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(pAC,Addr),Val) +#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(pAC,Addr),Val) +#define VPD_OUT32(pAC,IoC,Addr,Val) SK_OUT32(IoC,PCI_C(pAC,Addr),Val) +#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(pAC,Addr),pVal) +#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(pAC,Addr),pVal) +#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(pAC,Addr),pVal) #endif /* VPD_DO_IO */ -#else /* SKDIAG */ +#else /* SK_DIAG */ #define VPD_OUT8(pAC,Ioc,Addr,Val) { \ if ((pAC)->DgT.DgUseCfgCycle) \ SkPciWriteCfgByte(pAC,Addr,Val); \ else \ - SK_OUT8(pAC,PCI_C(Addr),Val); \ + SK_OUT8(pAC,PCI_C(pAC,Addr),Val); \ } #define VPD_OUT16(pAC,Ioc,Addr,Val) { \ if ((pAC)->DgT.DgUseCfgCycle) \ SkPciWriteCfgWord(pAC,Addr,Val); \ else \ - SK_OUT16(pAC,PCI_C(Addr),Val); \ + SK_OUT16(pAC,PCI_C(pAC,Addr),Val); \ } #define VPD_OUT32(pAC,Ioc,Addr,Val) { \ if ((pAC)->DgT.DgUseCfgCycle) \ SkPciWriteCfgDWord(pAC,Addr,Val); \ else \ - SK_OUT32(pAC,PCI_C(Addr),Val); \ + SK_OUT32(pAC,PCI_C(pAC,Addr),Val); \ } #define VPD_IN8(pAC,Ioc,Addr,pVal) { \ - if ((pAC)->DgT.DgUseCfgCycle) \ + if ((pAC)->DgT.DgUseCfgCycle) \ SkPciReadCfgByte(pAC,Addr,pVal); \ else \ - SK_IN8(pAC,PCI_C(Addr),pVal); \ + SK_IN8(pAC,PCI_C(pAC,Addr),pVal); \ } #define VPD_IN16(pAC,Ioc,Addr,pVal) { \ - if ((pAC)->DgT.DgUseCfgCycle) \ + if ((pAC)->DgT.DgUseCfgCycle) \ SkPciReadCfgWord(pAC,Addr,pVal); \ else \ - SK_IN16(pAC,PCI_C(Addr),pVal); \ + SK_IN16(pAC,PCI_C(pAC,Addr),pVal); \ } #define VPD_IN32(pAC,Ioc,Addr,pVal) { \ if ((pAC)->DgT.DgUseCfgCycle) \ SkPciReadCfgDWord(pAC,Addr,pVal); \ else \ - SK_IN32(pAC,PCI_C(Addr),pVal); \ + SK_IN32(pAC,PCI_C(pAC,Addr),pVal); \ } -#endif /* nSKDIAG */ +#endif /* SK_DIAG */ /* function prototypes ********************************************************/ #ifndef SK_KR_PROTO -#ifdef SKDIAG +#ifdef SK_DIAG extern SK_U32 VpdReadDWord( SK_AC *pAC, SK_IOC IoC, int addr); -#endif /* SKDIAG */ +#endif /* SK_DIAG */ extern int VpdSetupPara( SK_AC *pAC, @@ -304,7 +242,12 @@ extern void VpdErrLog( SK_IOC IoC, char *msg); -#ifdef SKDIAG +int VpdInit( + SK_AC *pAC, + SK_IOC IoC); + +#if defined(SK_DIAG) || defined(SK_ASF) + extern int VpdReadBlock( SK_AC *pAC, SK_IOC IoC, @@ -318,7 +261,9 @@ extern int VpdWriteBlock( char *buf, int addr, int len); -#endif /* SKDIAG */ + +#endif /* SK_DIAG || SK_ASF */ + #else /* SK_KR_PROTO */ extern SK_U32 VpdReadDWord(); extern int VpdSetupPara(); @@ -333,3 +278,4 @@ extern void VpdErrLog(); #endif /* SK_KR_PROTO */ #endif /* __INC_SKVPD_H_ */ + diff --git a/drivers/sk98lin/h/sky2le.h b/drivers/sk98lin/h/sky2le.h new file mode 100644 index 0000000..a8cda90 --- /dev/null +++ b/drivers/sk98lin/h/sky2le.h @@ -0,0 +1,893 @@ +/****************************************************************************** + * + * Name: sky2le.h + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 1.10 $ + * Date: $Date: 2005/12/14 16:11:35 $ + * Purpose: Common list element definitions and access macros. + * + ******************************************************************************/ + +/****************************************************************************** + * + * LICENSE: + * (C)Copyright 2003-2004 Marvell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * The information in this file is provided "AS IS" without warranty. + * /LICENSE + * + ******************************************************************************/ + +#ifndef __INC_SKY2LE_H +#define __INC_SKY2LE_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines ********************************************************************/ + +#define MIN_LEN_OF_LE_TAB 128 +#define MAX_LEN_OF_LE_TAB 4096 +#ifdef USE_POLLING_UNIT +#define NUM_LE_POLLING_UNIT 2 +#endif +#define MAX_FRAG_OVERHEAD 10 + +/* Macro for aligning a given value */ +#define SK_ALIGN_SIZE(Value, Alignment, AlignedVal) { \ + (AlignedVal) = (((Value) + (Alignment) - 1) & (~((Alignment) - 1)));\ +} + +/****************************************************************************** + * + * LE2DWord() - Converts the given Little Endian value to machine order value + * + * Description: + * This function converts the Little Endian value received as an argument to + * the machine order value. + * + * Returns: + * The converted value + * + */ + +#ifdef SK_LITTLE_ENDIAN + +#ifndef SK_USE_REV_DESC +#define LE2DWord(value) (value) +#else /* SK_USE_REV_DESC */ +#define LE2DWord(value) \ + ((((value)<<24L) & 0xff000000L) + \ + (((value)<< 8L) & 0x00ff0000L) + \ + (((value)>> 8L) & 0x0000ff00L) + \ + (((value)>>24L) & 0x000000ffL)) +#endif /* SK_USE_REV_DESC */ + +#else /* !SK_LITTLE_ENDIAN */ + +#ifndef SK_USE_REV_DESC +#define LE2DWord(value) \ + ((((value)<<24L) & 0xff000000L) + \ + (((value)<< 8L) & 0x00ff0000L) + \ + (((value)>> 8L) & 0x0000ff00L) + \ + (((value)>>24L) & 0x000000ffL)) +#else /* SK_USE_REV_DESC */ +#define LE2DWord(value) (value) +#endif /* SK_USE_REV_DESC */ + +#endif /* !SK_LITTLE_ENDIAN */ + +/****************************************************************************** + * + * DWord2LE() - Converts the given value to a Little Endian value + * + * Description: + * This function converts the value received as an argument to a Little Endian + * value on Big Endian machines. If the machine running the code is Little + * Endian, then no conversion is done. + * + * Returns: + * The converted value + * + */ + +#ifdef SK_LITTLE_ENDIAN + +#ifndef SK_USE_REV_DESC +#define DWord2LE(value) (value) +#else /* SK_USE_REV_DESC */ +#define DWord2LE(value) \ + ((((value)<<24L) & 0xff000000L) + \ + (((value)<< 8L) & 0x00ff0000L) + \ + (((value)>> 8L) & 0x0000ff00L) + \ + (((value)>>24L) & 0x000000ffL)) +#endif /* SK_USE_REV_DESC */ + +#else /* !SK_LITTLE_ENDIAN */ + +#ifndef SK_USE_REV_DESC +#define DWord2LE(value) \ + ((((value)<<24L) & 0xff000000L) + \ + (((value)<< 8L) & 0x00ff0000L) + \ + (((value)>> 8L) & 0x0000ff00L) + \ + (((value)>>24L) & 0x000000ffL)) +#else /* SK_USE_REV_DESC */ +#define DWord2LE(value) (value) +#endif /* SK_USE_REV_DESC */ +#endif /* !SK_LITTLE_ENDIAN */ + +/****************************************************************************** + * + * LE2Word() - Converts the given Little Endian value to machine order value + * + * Description: + * This function converts the Little Endian value received as an argument to + * the machine order value. + * + * Returns: + * The converted value + * + */ + +#ifdef SK_LITTLE_ENDIAN +#ifndef SK_USE_REV_DESC +#define LE2Word(value) (value) +#else /* SK_USE_REV_DESC */ +#define LE2Word(value) \ + ((((value)<< 8L) & 0xff00) + \ + (((value)>> 8L) & 0x00ff)) +#endif /* SK_USE_REV_DESC */ + +#else /* !SK_LITTLE_ENDIAN */ +#ifndef SK_USE_REV_DESC +#define LE2Word(value) \ + ((((value)<< 8L) & 0xff00) + \ + (((value)>> 8L) & 0x00ff)) +#else /* SK_USE_REV_DESC */ +#define LE2Word(value) (value) +#endif /* SK_USE_REV_DESC */ +#endif /* !SK_LITTLE_ENDIAN */ + +/****************************************************************************** + * + * Word2LE() - Converts the given value to a Little Endian value + * + * Description: + * This function converts the value received as an argument to a Little Endian + * value on Big Endian machines. If the machine running the code is Little + * Endian, then no conversion is done. + * + * Returns: + * The converted value + * + */ + +#ifdef SK_LITTLE_ENDIAN +#ifndef SK_USE_REV_DESC +#define Word2LE(value) (value) +#else /* SK_USE_REV_DESC */ +#define Word2LE(value) \ + ((((value)<< 8L) & 0xff00) + \ + (((value)>> 8L) & 0x00ff)) +#endif /* SK_USE_REV_DESC */ + +#else /* !SK_LITTLE_ENDIAN */ +#ifndef SK_USE_REV_DESC +#define Word2LE(value) \ + ((((value)<< 8L) & 0xff00) + \ + (((value)>> 8L) & 0x00ff)) +#else /* SK_USE_REV_DESC */ +#define Word2LE(value) (value) +#endif /* SK_USE_REV_DESC */ +#endif /* !SK_LITTLE_ENDIAN */ + +/****************************************************************************** + * + * Transmit list element macros + * + */ + +#define TXLE_SET_ADDR(pLE, Addr) \ + ((pLE)->Tx.TxUn.BufAddr = DWord2LE(Addr)) +#define TXLE_SET_LSLEN(pLE, Len) \ + ((pLE)->Tx.TxUn.LargeSend.Length = Word2LE(Len)) +#define TXLE_SET_STACS(pLE, Start) \ + ((pLE)->Tx.TxUn.ChkSum.TxTcpSp = Word2LE(Start)) +#define TXLE_SET_WRICS(pLE, Write) \ + ((pLE)->Tx.TxUn.ChkSum.TxTcpWp = Word2LE(Write)) +#define TXLE_SET_INICS(pLE, Ini) ((pLE)->Tx.Send.InitCsum = Word2LE(Ini)) +#define TXLE_SET_LEN(pLE, Len) ((pLE)->Tx.Send.BufLen = Word2LE(Len)) +#define TXLE_SET_VLAN(pLE, Vlan) ((pLE)->Tx.Send.VlanTag = Word2LE(Vlan)) +#define TXLE_SET_LCKCS(pLE, Lock) ((pLE)->Tx.ControlFlags = (Lock)) +#define TXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Tx.ControlFlags = (Ctrl)) +#define TXLE_SET_OPC(pLE, Opc) ((pLE)->Tx.Opcode = (Opc)) + +#define TXLE_GET_ADDR(pLE) LE2DWord((pLE)->Tx.TxUn.BufAddr) +#define TXLE_GET_LSLEN(pLE) LE2Word((pLE)->Tx.TxUn.LargeSend.Length) +#define TXLE_GET_STACS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpSp) +#define TXLE_GET_WRICS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpWp) +#define TXLE_GET_INICS(pLE) LE2Word((pLE)->Tx.Send.InitCsum) +#define TXLE_GET_LEN(pLE) LE2Word((pLE)->Tx.Send.BufLen) +#define TXLE_GET_VLAN(pLE) LE2Word((pLE)->Tx.Send.VlanTag) +#define TXLE_GET_LCKCS(pLE) ((pLE)->Tx.ControlFlags) +#define TXLE_GET_CTRL(pLE) ((pLE)->Tx.ControlFlags) +#define TXLE_GET_OPC(pLE) ((pLE)->Tx.Opcode) + +/****************************************************************************** + * + * Receive list element macros + * + */ + +#define RXLE_SET_ADDR(pLE, Addr) \ + ((pLE)->Rx.RxUn.BufAddr = (SK_U32) DWord2LE(Addr)) +#define RXLE_SET_STACS2(pLE, Offs) \ + ((pLE)->Rx.RxUn.ChkSum.RxTcpSp2 = Word2LE(Offs)) +#define RXLE_SET_STACS1(pLE, Offs) \ + ((pLE)->Rx.RxUn.ChkSum.RxTcpSp1 = Word2LE(Offs)) +#define RXLE_SET_LEN(pLE, Len) ((pLE)->Rx.BufferLength = Word2LE(Len)) +#define RXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Rx.ControlFlags = (Ctrl)) +#define RXLE_SET_OPC(pLE, Opc) ((pLE)->Rx.Opcode = (Opc)) + +#define RXLE_GET_ADDR(pLE) LE2DWord((pLE)->Rx.RxUn.BufAddr) +#define RXLE_GET_STACS2(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp2) +#define RXLE_GET_STACS1(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp1) +#define RXLE_GET_LEN(pLE) LE2Word((pLE)->Rx.BufferLength) +#define RXLE_GET_CTRL(pLE) ((pLE)->Rx.ControlFlags) +#define RXLE_GET_OPC(pLE) ((pLE)->Rx.Opcode) + +/****************************************************************************** + * + * Status list element macros + * + */ + +#define STLE_SET_OPC(pLE, Opc) ((pLE)->St.Opcode = (Opc)) + +#define STLE_GET_FRSTATUS(pLE) LE2DWord((pLE)->St.StUn.StRxStatWord) +#define STLE_GET_TIST(pLE) LE2DWord((pLE)->St.StUn.StRxTimeStamp) +#define STLE_GET_TCP1(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum1) +#define STLE_GET_TCP2(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum2) +#define STLE_GET_LEN(pLE) LE2Word((pLE)->St.Stat.BufLen) +#define STLE_GET_VLAN(pLE) LE2Word((pLE)->St.Stat.VlanTag) +#define STLE_GET_LINK(pLE) ((pLE)->St.Link) +#define STLE_GET_OPC(pLE) ((pLE)->St.Opcode) +#define STLE_GET_DONE_IDX(pLE,LowVal,HighVal) { \ + (LowVal) = LE2DWord((pLE)->St.StUn.StTxStatLow); \ + (HighVal) = LE2Word((pLE)->St.Stat.StTxStatHi); \ +} + +#define STLE_GET_RSS(pLE) LE2DWord((pLE)->St.StUn.StRxRssValue) +#define STLE_GET_IPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_IP_FLAG) +#define STLE_GET_TCPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_TCP_FLAG) + + +/* I always take both values as a paramter to avoid typos */ +#define STLE_GET_DONE_IDX_TXA1(LowVal,HighVal) \ + (((LowVal) & STLE_TXA1_MSKL) >> STLE_TXA1_SHIFTL) +#define STLE_GET_DONE_IDX_TXS1(LowVal,HighVal) \ + ((LowVal & STLE_TXS1_MSKL) >> STLE_TXS1_SHIFTL) +#define STLE_GET_DONE_IDX_TXA2(LowVal,HighVal) \ + (((LowVal & STLE_TXA2_MSKL) >> STLE_TXA2_SHIFTL) + \ + ((HighVal & STLE_TXA2_MSKH) << STLE_TXA2_SHIFTH)) +#define STLE_GET_DONE_IDX_TXS2(LowVal,HighVal) \ + ((HighVal & STLE_TXS2_MSKH) >> STLE_TXS2_SHIFTH) + + +#define SK_Y2_RXSTAT_CHECK_PKT(Len, RxStat, IsOk) { \ + (IsOk) = (((RxStat) & GMR_FS_RX_OK) != 0) && \ + (((RxStat) & GMR_FS_ANY_ERR) == 0); \ + \ + if ((IsOk) && ((SK_U16)(((RxStat) & GMR_FS_LEN_MSK) >> \ + GMR_FS_LEN_SHIFT) != (Len))) { \ + /* length in MAC status differs from length in LE */\ + (IsOk) = SK_FALSE; \ + } \ +} + + +/****************************************************************************** + * + * Polling unit list element macros + * + * NOTE: the Idx must be <= 0xfff and PU_PUTIDX_VALID makes them valid + * + */ + +#ifdef USE_POLLING_UNIT + +#define POLE_SET_OPC(pLE, Opc) ((pLE)->Sa.Opcode = (Opc)) +#define POLE_SET_LINK(pLE, Port) ((pLE)->Sa.Link = (Port)) +#define POLE_SET_RXIDX(pLE, Idx) ((pLE)->Sa.RxIdxVld = Word2LE(Idx)) +#define POLE_SET_TXAIDX(pLE, Idx) ((pLE)->Sa.TxAIdxVld = Word2LE(Idx)) +#define POLE_SET_TXSIDX(pLE, Idx) ((pLE)->Sa.TxSIdxVld = Word2LE(Idx)) + +#define POLE_GET_OPC(pLE) ((pLE)->Sa.Opcode) +#define POLE_GET_LINK(pLE) ((pLE)->Sa.Link) +#define POLE_GET_RXIDX(pLE) LE2Word((pLE)->Sa.RxIdxVld) +#define POLE_GET_TXAIDX(pLE) LE2Word((pLE)->Sa.TxAIdxVld) +#define POLE_GET_TXSIDX(pLE) LE2Word((pLE)->Sa.TxSIdxVld) + +#endif /* USE_POLLING_UNIT */ + +/****************************************************************************** + * + * Debug macros for list elements + * + */ + +#ifdef DEBUG + +#define SK_DBG_DUMP_RX_LE(pLE) { \ + SK_U8 Opcode; \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=== RX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \ + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\ + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \ + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (16bit) %04x %04x %04x %04x\n", \ + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \ + ((SK_U16 *) pLE)[3])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (32bit) %08x %08x\n", \ + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \ + Opcode = RXLE_GET_OPC(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \ + "Hardware" : "Software")); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOpc: 0x%x ",Opcode)); \ + switch (Opcode & (~HW_OWNER)) { \ + case OP_BUFFER: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_BUFFER\n")); \ + break; \ + case OP_PACKET: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_PACKET\n")); \ + break; \ + case OP_ADDR64: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_ADDR64\n")); \ + break; \ + case OP_TCPSTART: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPPAR\n")); \ + break; \ + case SW_OWNER: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunused LE\n")); \ + break; \ + default: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunknown Opcode!!!\n")); \ + break; \ + } \ + if ((Opcode & OP_BUFFER) == OP_BUFFER) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tControl: 0x%x\n", RXLE_GET_CTRL(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tBufLen: 0x%x\n", RXLE_GET_LEN(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tLowAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \ + } \ + if ((Opcode & OP_ADDR64) == OP_ADDR64) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tHighAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \ + } \ + if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Start 1 : 0x%x\n", RXLE_GET_STACS1(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Start 2 : 0x%x\n", RXLE_GET_STACS2(pLE))); \ + } \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=====================\n")); \ +} + +#define SK_DBG_DUMP_TX_LE(pLE) { \ + SK_U8 Opcode; \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=== TX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \ + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\ + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \ + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (16bit) %04x %04x %04x %04x\n", \ + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \ + ((SK_U16 *) pLE)[3])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (32bit) %08x %08x\n", \ + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \ + Opcode = TXLE_GET_OPC(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \ + "Hardware" : "Software")); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOpc: 0x%x ",Opcode)); \ + switch (Opcode & (~HW_OWNER)) { \ + case OP_TCPCHKSUM: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPCHKSUM\n")); \ + break; \ + case OP_TCPIS: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPIS\n")); \ + break; \ + case OP_TCPLCK: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPLCK\n")); \ + break; \ + case OP_TCPLW: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPLW\n")); \ + break; \ + case OP_TCPLSW: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPLSW\n")); \ + break; \ + case OP_TCPLISW: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TCPLISW\n")); \ + break; \ + case OP_ADDR64: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_ADDR64\n")); \ + break; \ + case OP_VLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_VLAN\n")); \ + break; \ + case OP_ADDR64VLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_ADDR64VLAN\n")); \ + break; \ + case OP_LRGLEN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_LRGLEN\n")); \ + break; \ + case OP_LRGLENVLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_LRGLENVLAN\n")); \ + break; \ + case OP_BUFFER: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_BUFFER\n")); \ + break; \ + case OP_PACKET: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_PACKET\n")); \ + break; \ + case OP_LARGESEND: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_LARGESEND\n")); \ + break; \ + case SW_OWNER: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunused LE\n")); \ + break; \ + default: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunknown Opcode!!!\n")); \ + break; \ + } \ + if ((Opcode & OP_BUFFER) == OP_BUFFER) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tControl: 0x%x\n", TXLE_GET_CTRL(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tBufLen: 0x%x\n", TXLE_GET_LEN(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tLowAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \ + } \ + if ((Opcode & OP_ADDR64) == OP_ADDR64) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tHighAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \ + } \ + if ((Opcode & OP_VLAN) == OP_VLAN) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tVLAN Id: 0x%x\n", TXLE_GET_VLAN(pLE))); \ + } \ + if ((Opcode & OP_LRGLEN) == OP_LRGLEN) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tLarge send length: 0x%x\n", TXLE_GET_LSLEN(pLE))); \ + } \ + if ((Opcode &(~HW_OWNER)) <= OP_ADDR64) { \ + if ((Opcode & OP_TCPWRITE) == OP_TCPWRITE) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Write: 0x%x\n", TXLE_GET_WRICS(pLE))); \ + } \ + if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Start: 0x%x\n", TXLE_GET_STACS(pLE))); \ + } \ + if ((Opcode & OP_TCPINIT) == OP_TCPINIT) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Init: 0x%x\n", TXLE_GET_INICS(pLE))); \ + } \ + if ((Opcode & OP_TCPLCK) == OP_TCPLCK) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP Sum Lock: 0x%x\n", TXLE_GET_LCKCS(pLE))); \ + } \ + } \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=====================\n")); \ +} + +#define SK_DBG_DUMP_ST_LE(pLE) { \ + SK_U8 Opcode; \ + SK_U16 HighVal; \ + SK_U32 LowVal; \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=== ST_LIST_ELEMENT @addr: %p contains: %02x %02x %02x %02x %02x %02x %02x %02x\n",\ + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\ + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \ + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (16bit) %04x %04x %04x %04x\n", \ + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \ + ((SK_U16 *) pLE)[3])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (32bit) %08x %08x\n", \ + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \ + Opcode = STLE_GET_OPC(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == SW_OWNER) ? \ + "Hardware" : "Software")); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOpc: 0x%x", Opcode)); \ + Opcode &= (~HW_OWNER); \ + switch (Opcode) { \ + case OP_RXSTAT: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXSTAT\n")); \ + break; \ + case OP_RXTIMESTAMP: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXTIMESTAMP\n")); \ + break; \ + case OP_RXVLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXVLAN\n")); \ + break; \ + case OP_RXCHKS: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXCHKS\n")); \ + break; \ + case OP_RXCHKSVLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXCHKSVLAN\n")); \ + break; \ + case OP_RXTIMEVLAN: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RXTIMEVLAN\n")); \ + break; \ + case OP_RSS_HASH: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_RSS_HASH\n")); \ + break; \ + case OP_TXINDEXLE: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_TXINDEXLE\n")); \ + break; \ + case HW_OWNER: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunused LE\n")); \ + break; \ + default: \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunknown status list element!!!\n")); \ + break; \ + } \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tPort: %c\n", 'A' + STLE_GET_LINK(pLE))); \ + if (Opcode == OP_RXSTAT) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tFrameLen: 0x%x\n", STLE_GET_LEN(pLE))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tFrameStat: 0x%x\n", STLE_GET_FRSTATUS(pLE))); \ + } \ + if ((Opcode & OP_RXVLAN) == OP_RXVLAN) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tVLAN Id: 0x%x\n", STLE_GET_VLAN(pLE))); \ + } \ + if ((Opcode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTimestamp: 0x%x\n", STLE_GET_TIST(pLE))); \ + } \ + if ((Opcode & OP_RXCHKS) == OP_RXCHKS) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTCP: 0x%x 0x%x\n", STLE_GET_TCP1(pLE), \ + STLE_GET_TCP2(pLE))); \ + } \ + if (Opcode == OP_TXINDEXLE) { \ + STLE_GET_DONE_IDX(pLE, LowVal, HighVal); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTx Index TxA1: 0x%x\n", \ + STLE_GET_DONE_IDX_TXA1(LowVal,HighVal))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTx Index TxS1: 0x%x\n", \ + STLE_GET_DONE_IDX_TXS1(LowVal,HighVal))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTx Index TxA2: 0x%x\n", \ + STLE_GET_DONE_IDX_TXA2(LowVal,HighVal))); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTx Index TxS2: 0x%x\n", \ + STLE_GET_DONE_IDX_TXS2(LowVal,HighVal))); \ + } \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=====================\n")); \ +} + +#ifdef USE_POLLING_UNIT +#define SK_DBG_DUMP_PO_LE(pLE) { \ + SK_U8 Opcode; \ + SK_U16 Idx; \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=== PO_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \ + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\ + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \ + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (16bit) %04x %04x %04x %04x\n", \ + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \ + ((SK_U16 *) pLE)[3])); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\t (32bit) %08x %08x\n", \ + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \ + Opcode = POLE_GET_OPC(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \ + "Hardware" : "Software")); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOpc: 0x%x ",Opcode)); \ + if ((Opcode & ~HW_OWNER) == OP_PUTIDX) { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tOP_PUTIDX\n")); \ + } \ + else { \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tunknown Opcode!!!\n")); \ + } \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tPort %c\n", 'A' + POLE_GET_LINK(pLE))); \ + Idx = POLE_GET_TXAIDX(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTxA Index is 0x%X and %svalid\n", Idx, \ + (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \ + Idx = POLE_GET_TXSIDX(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tTxS Index is 0x%X and %svalid\n", Idx, \ + (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \ + Idx = POLE_GET_RXIDX(pLE); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("\tRx Index is 0x%X and %svalid\n", Idx, \ + (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \ + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \ + ("=====================\n")); \ +} +#endif /* USE_POLLING_UNIT */ + +#else /* !DEBUG */ + +#define SK_DBG_DUMP_RX_LE(pLE) +#define SK_DBG_DUMP_TX_LE(pLE) +#define SK_DBG_DUMP_ST_LE(pLE) +#define SK_DBG_DUMP_PO_LE(pLE) + +#endif /* !DEBUG */ + +/****************************************************************************** + * + * Macros for listelement tables + * + * + */ + +#define LE_SIZE sizeof(SK_HWLE) +#define LE_TAB_SIZE(NumElements) ((NumElements) * LE_SIZE) + +/* Number of unused list elements in table + * this macro always returns the number of free listelements - 1 + * this way we want to guarantee that always one LE remains unused + */ +#define NUM_FREE_LE_IN_TABLE(pTable) \ + ( ((pTable)->Put >= (pTable)->Done) ? \ + (NUM_LE_IN_TABLE(pTable) - (pTable)->Put + (pTable)->Done - 1) :\ + ((pTable)->Done - (pTable)->Put - 1) ) + +/* total number of list elements in table */ +#define NUM_LE_IN_TABLE(pTable) ((pTable)->Num) + +/* get next unused Rx list element */ +#define GET_RX_LE(pLE, pTable) { \ + pLE = &(pTable)->pLETab[(pTable)->Put]; \ + (pTable)->Put = ((pTable)->Put + 1) & (NUM_LE_IN_TABLE(pTable) - 1);\ +} + +/* get next unused Tx list element */ +#define GET_TX_LE(pLE, pTable) GET_RX_LE(pLE, pTable) + +/* get next status list element expected to be finished by hw */ +#define GET_ST_LE(pLE, pTable) { \ + pLE = &(pTable)->pLETab[(pTable)->Done]; \ + (pTable)->Done = ((pTable)->Done +1) & (NUM_LE_IN_TABLE(pTable) - 1);\ +} + +#ifdef USE_POLLING_UNIT +/* get next polling unit list element for port */ +#define GET_PO_LE(pLE, pTable, Port) { \ + pLE = &(pTable)->pLETab[(Port)]; \ +} +#endif /* USE_POLLING_UNIT */ + +#define GET_PUT_IDX(pTable) ((pTable)->Put) + +#define UPDATE_HWPUT_IDX(pTable) {(pTable)->HwPut = (pTable)->Put; } + +/* + * get own bit of next status LE + * if the result is != 0 there has been at least one status LE finished + */ +#define OWN_OF_FIRST_LE(pTable) \ + (STLE_GET_OPC(&(pTable)->pLETab[(pTable)->Done]) & HW_OWNER) + +#define SET_DONE_INDEX(pTable, Idx) (pTable)->Done = (Idx); + +#define GET_DONE_INDEX(pTable) ((pTable)->Done) + +#ifdef SAFE_BUT_SLOW + +/* check own bit of LE before current done idx */ +#define CHECK_STLE_OVERFLOW(pTable, IsOk) { \ + unsigned i; \ + if ((i = (pTable)->Done) == 0) { \ + i = NUM_LE_IN_TABLE(pTable); \ + } \ + else { \ + i = i - 1; \ + } \ + if (STLE_GET_OPC(&(pTable)->pLETab[i]) == HW_OWNER) { \ + (IsOk) = SK_TRUE; \ + } \ + else { \ + (IsOk) = SK_FALSE; \ + } \ + } + + +/* + * for Yukon-2 the hardware is not polling the list elements, so it + * is not necessary to change the own-bit of Rx or Tx LEs before + * reusing them + * but it might make debugging easier if one simply can see whether + * a LE has been worked on + */ + +#define CLEAR_LE_OWN(pTable, Idx) \ + STLE_SET_OPC(&(pTable)->pLETab[(Idx)], SW_OWNER) + +/* + * clear all own bits starting from old done index up to the LE before + * the new done index + */ +#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To) { \ + int i; \ + i = (pTable)->Done; \ + while (i != To) { \ + CLEAR_LE_OWN(pTable, i); \ + i = (i + 1) & (NUM_LE_IN_TABLE(pTable) - 1); \ + } \ + } + +#else /* !SAFE_BUT_SLOW */ + +#define CHECK_STLE_OVERFLOW(pTable, IsOk) +#define CLEAR_LE_OWN(pTable, Idx) +#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To) + +#endif /* !SAFE_BUT_SLOW */ + + +/* typedefs *******************************************************************/ + +typedef struct s_LetRxTx { + SK_U16 VlanId; /* VLAN Id given down last time */ + SK_U16 TcpWp; /* TCP Checksum Write Position */ + SK_U16 TcpSp1; /* TCP Checksum Calculation Start Position 1 */ + SK_U16 TcpSp2; /* TCP Checksum Calculation Start Position 2 */ + SK_U16 MssValue; /* Maximum Segment Size */ + SK_U16 Reserved1; /* reserved word for furture extensions */ + SK_U16 Reserved2; /* reserved word for furture extensions */ + SK_U16 Reserved3; /* reserved word for furture extensions */ +} SK_LET_RX_TX; + +typedef struct s_LetStat { + SK_U32 RxTimeStamp; /* Receive Timestamp */ + SK_U32 RssHashValue; /* RSS Hash Value */ + SK_BOOL RssIsIp; /* RSS Hash Value: IP packet detected */ + SK_BOOL RssIsTcp; /* RSS Hash Value: IP+TCP packet detected */ + SK_U16 VlanId; /* VLAN Id given received by Status BMU */ + SK_U16 TcpSum1; /* TCP checksum 1 (status BMU) */ + SK_U16 TcpSum2; /* TCP checksum 2 (status BMU) */ +} SK_LET_STAT; + +typedef union s_LetBmuSpec { + SK_LET_RX_TX RxTx; /* Rx/Tx BMU specific variables */ + SK_LET_STAT Stat; /* Status BMU specific variables */ +} SK_LET_BMU_S; + +typedef struct s_le_table { + /* all LE's between Done and HWPut are owned by the hardware */ + /* all LE's between Put and Done can be used from Software */ + /* all LE's between HWPut and Put are currently processed in DriverSend */ + unsigned Done; /* done index - consumed from HW and available */ + unsigned Put; /* put index - to be given to hardware */ + unsigned HwPut; /* put index actually given to hardware */ + unsigned Num; /* total number of list elements */ + SK_HWLE *pLETab; /* virtual address of list element table */ + SK_U32 pPhyLETABLow; /* physical address of list element table */ + SK_U32 pPhyLETABHigh; /* physical address of list element table */ + /* values to remember in order to save some LEs */ + SK_U32 BufHighAddr; /* high addr given down last time */ + SK_LET_BMU_S Bmu; /* contains BMU specific information */ + SK_U32 private; /* driver private variable free usable */ + SK_U16 TcpInitCsum; /* Init. Checksum */ +} SK_LE_TABLE; + +/* function prototypes ********************************************************/ + +#ifndef SK_KR_PROTO + +/* + * public functions in sky2le.c + */ +extern void SkGeY2SetPutIndex( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 StartAddrPrefetchUnit, + SK_LE_TABLE *pLETab); + +extern void SkGeY2InitPrefetchUnit( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Queue, + SK_LE_TABLE *pLETab); + +extern void SkGeY2InitStatBmu( + SK_AC *pAC, + SK_IOC IoC, + SK_LE_TABLE *pLETab); + +extern void SkGeY2InitPollUnit( + SK_AC *pAC, + SK_IOC IoC, + SK_LE_TABLE *pLETab); + +extern void SkGeY2InitSingleLETable( + SK_AC *pAC, + SK_LE_TABLE *pLETab, + unsigned int NumLE, + void *pVMem, + SK_U32 PMemLowAddr, + SK_U32 PMemHighAddr); + +#else /* SK_KR_PROTO */ +extern void SkGeY2SetPutIndex(); +extern void SkGeY2InitPrefetchUnit(); +extern void SkGeY2InitStatBmu(); +extern void SkGeY2InitPollUnit(); +extern void SkGeY2InitSingleLETable(); +#endif /* SK_KR_PROTO */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_SKY2LE_H */ + diff --git a/drivers/sk98lin/h/xmac_ii.h b/drivers/sk98lin/h/xmac_ii.h index 2ef903a..fb87a37 100644 --- a/drivers/sk98lin/h/xmac_ii.h +++ b/drivers/sk98lin/h/xmac_ii.h @@ -1,201 +1,25 @@ /****************************************************************************** * * Name: xmac_ii.h - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.46 $ - * Date: $Date: 2003/01/28 09:47:45 $ + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 2.15 $ + * Date: $Date: 2006/02/16 14:27:02 $ * Purpose: Defines and Macros for Gigabit Ethernet Controller * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2006 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: xmac_ii.h,v $ - * Revision 1.46 2003/01/28 09:47:45 rschmidt - * Added defines for copper MDI/MDIX configuration - * Added defines for LED Control Register - * Editorial changes - * - * Revision 1.45 2002/12/10 14:35:13 rschmidt - * Corrected defines for Extended PHY Specific Control - * Added defines for Ext. PHY Specific Ctrl 2 Reg. (Fiber specific) - * - * Revision 1.44 2002/12/09 14:58:41 rschmidt - * Added defines for Ext. PHY Specific Ctrl Reg. (downshift feature) - * Added 'GMR_FS_UN_SIZE'-Bit to Rx GMAC FIFO Flush Mask - * - * Revision 1.43 2002/12/05 10:14:45 rschmidt - * Added define for GMAC's Half Duplex Burst Mode - * Added define for Rx GMAC FIFO Flush Mask (default) - * - * Revision 1.42 2002/11/12 16:48:19 rschmidt - * Added defines for Cable Diagnostic Register (GPHY) - * Editorial changes - * - * Revision 1.41 2002/10/21 11:20:22 rschmidt - * Added bit GMR_FS_GOOD_FC to GMR_FS_ANY_ERR - * Editorial changes - * - * Revision 1.40 2002/10/14 14:54:14 rschmidt - * Added defines for GPHY Specific Status and GPHY Interrupt Status - * Added bits PHY_M_IS_AN_ERROR and PHY_M_IS_FIFO_ERROR to PHY_M_DEF_MSK - * Editorial changes - * - * Revision 1.39 2002/10/10 15:53:44 mkarl - * added some bit definitions for link speed status and LED's - * - * Revision 1.38 2002/08/21 16:23:46 rschmidt - * Added defines for PHY Specific Ctrl Reg - * Editorial changes - * - * Revision 1.37 2002/08/16 14:50:33 rschmidt - * Added defines for Auto-Neg. Advertisement YUKON Fiber (88E1011S only) - * Changed define PHY_M_DEF_MSK for GPHY IRQ Mask - * Editorial changes - * - * Revision 1.36 2002/08/12 13:21:10 rschmidt - * Added defines for different Broadcom PHY Ids - * - * Revision 1.35 2002/08/08 15:58:01 rschmidt - * Added defines for Manual LED Override register (YUKON) - * Editorial changes - * - * Revision 1.34 2002/07/31 17:23:36 rwahl - * Added define GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR). - * - * Revision 1.33 2002/07/23 16:03:37 rschmidt - * Added defines for GPHY registers - * Editorial changes - * - * Revision 1.32 2002/07/15 18:14:37 rwahl - * Added GMAC MIB counters definitions. - * Editorial changes. - * - * Revision 1.31 2002/07/15 15:42:50 rschmidt - * Removed defines from PHY specific reg. which are - * common to all PHYs - * Added defines for GMAC MIB Counters - * Editorial changes - * - * Revision 1.30 2002/06/05 08:22:12 rschmidt - * Changed defines for GMAC Rx Control Register and Rx Status - * Editorial changes - * - * Revision 1.29 2002/04/25 11:43:56 rschmidt - * Added define PHY_B_AS_PAUSE_MSK for BCom Pause Res. - * Added new registers and defines for YUKON (GMAC, GPHY) - * Added Receive Frame Status Encoding for YUKON - * Editorial changes - * - * Revision 1.28 2000/11/09 12:32:49 rassmann - * Renamed variables. - * - * Revision 1.27 2000/05/17 11:00:46 malthoff - * Add bit for enable/disable power management in BCOM chip. - * - * Revision 1.26 1999/11/22 14:03:00 cgoos - * Changed license header to GPL. - * - * Revision 1.25 1999/08/12 19:19:38 malthoff - * Add PHY_B_AC_TX_TST bit according to BCOM A1 errata sheet. - * - * Revision 1.24 1999/07/30 11:27:21 cgoos - * Fixed a missing end-of-comment. - * - * Revision 1.23 1999/07/30 07:03:31 malthoff - * Cut some long comments. - * Correct the XMAC PHY ID definitions. - * - * Revision 1.22 1999/05/19 07:33:18 cgoos - * Changes for 1000Base-T. - * - * Revision 1.21 1999/03/25 07:46:11 malthoff - * Add XM_HW_CFG, XM_TS_READ, and XM_TS_LOAD registers. - * - * Revision 1.20 1999/03/12 13:36:09 malthoff - * Remove __STDC__. - * - * Revision 1.19 1998/12/10 12:22:54 gklug - * fix: RX_PAGE must be in interrupt mask - * - * Revision 1.18 1998/12/10 10:36:36 gklug - * fix: swap of pause bits - * - * Revision 1.17 1998/11/18 13:21:45 gklug - * fix: Default interrupt mask - * - * Revision 1.16 1998/10/29 15:53:21 gklug - * fix: Default mask uses ASS (GP0) signal - * - * Revision 1.15 1998/10/28 13:52:52 malthoff - * Add new bits in RX_CMD register. - * - * Revision 1.14 1998/10/19 15:34:53 gklug - * fix: typos - * - * Revision 1.13 1998/10/14 07:19:03 malthoff - * bug fix: Every define which describes bit 31 - * must be declared as unsigned long 'UL'. - * fix bit definitions of PHY_AN_RFB and PHY_AN_PAUSE. - * Remove ANP defines. Rework the RFB defines. - * - * Revision 1.12 1998/10/14 06:22:44 cgoos - * Changed shifted constant to ULONG. - * - * Revision 1.11 1998/10/14 05:43:26 gklug - * add: shift pause coding - * fix: PAUSE bits definition - * - * Revision 1.10 1998/10/13 09:19:21 malthoff - * Again change XMR_FS_ANY_ERR because of new info from XaQti. - * - * Revision 1.9 1998/10/09 07:58:30 malthoff - * Add XMR_FS_FCS_ERR to XMR_FS_ANY_ERR. - * - * Revision 1.8 1998/10/09 07:18:17 malthoff - * bug fix of a bug fix: XM_PAUSE_MODE and XM_DEF_MODE - * are not inverted! Bug XM_DEF_MSK is inverted. - * - * Revision 1.7 1998/10/05 08:04:32 malthoff - * bug fix: XM_PAUSE_MODE and XM_DEF_MODE - * must be inverted declarations. - * - * Revision 1.6 1998/09/28 13:38:18 malthoff - * Add default modes and masks XM_DEF_MSK, - * XM_PAUSE_MODE and XM_DEF_MODE - * - * Revision 1.5 1998/09/16 14:42:04 malthoff - * Bug Fix: XM_GP_PORT is a 32 bit (not a 16 bit) register. - * - * Revision 1.4 1998/08/20 14:59:47 malthoff - * Rework this file after reading the XaQti data sheet - * "Differences between Rev. B2 & Rev. C XMAC II". - * This file is now 100% XMAC II Rev. C complained. - * - * Revision 1.3 1998/06/29 12:18:23 malthoff - * Correct XMR_FS_ANY_ERR definition. - * - * Revision 1.2 1998/06/29 12:10:56 malthoff - * Add define XMR_FS_ANY_ERR. - * - * Revision 1.1 1998/06/19 13:37:17 malthoff - * created. - * + * /LICENSE * ******************************************************************************/ @@ -548,18 +372,18 @@ extern "C" { /* Bit 16..6: reserved */ #define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */ #define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */ -#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */ +#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */ #define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */ #define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */ -#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */ +#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */ /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */ /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */ -#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/ -#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/ -#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/ -#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/ +#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov */ +#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov */ +#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov */ +#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov */ #define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */ #define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */ #define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */ @@ -567,9 +391,9 @@ extern "C" { #define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */ /* Bit 22: reserved */ #define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */ -#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/ +#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov */ #define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */ -#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/ +#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov */ #define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */ /* Bit 16: reserved */ #define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */ @@ -578,57 +402,57 @@ extern "C" { #define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */ #define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */ #define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */ -#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/ +#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov */ #define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */ #define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */ -#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/ -#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/ +#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov */ +#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame Cnt Ov */ #define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */ #define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */ -#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/ -#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/ -#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */ +#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low Cnt Ov */ +#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK High Cnt Ov */ +#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received OK Ov */ #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV) /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */ /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */ /* Bit 31..26: reserved */ -#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/ -#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/ -#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/ -#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/ +#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov */ +#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov */ +#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov */ +#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov */ #define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */ #define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */ #define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */ #define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */ -#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/ +#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov */ #define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */ #define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */ #define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */ #define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */ -#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/ +#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov */ #define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */ #define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */ -#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/ -#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/ +#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov */ +#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov */ #define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */ #define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */ #define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */ #define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */ #define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */ -#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/ -#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/ -#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */ +#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low Cnt Ov */ +#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK High Cnt Ov */ +#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx OK Ov */ #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV) /* * Receive Frame Status Encoding */ -#define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */ -#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/ -#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/ +#define XMR_FS_LEN_MSK (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */ +#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: Tagged wh 2Lev VLAN ID */ +#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: Tagged wh 1Lev VLAN ID */ #define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */ #define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */ #define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */ @@ -646,6 +470,8 @@ extern "C" { #define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */ #define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */ +#define XMR_FS_LEN_SHIFT 18 + /* * XMR_FS_ERR will be set if * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT, @@ -665,10 +491,10 @@ extern "C" { #define PHY_XMAC_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ #define PHY_XMAC_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ #define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ -#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Abi Reg */ +#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */ #define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ #define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */ -#define PHY_XMAC_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */ +#define PHY_XMAC_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ /* 0x09 - 0x0e: reserved */ #define PHY_XMAC_EXT_STAT 0x0f /* 16 bit r/o Ext Status Register */ #define PHY_XMAC_RES_ABI 0x10 /* 16 bit r/o PHY Resolved Ability */ @@ -682,19 +508,19 @@ extern "C" { #define PHY_BCOM_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ #define PHY_BCOM_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ #define PHY_BCOM_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ -#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ +#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */ #define PHY_BCOM_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ #define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */ -#define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */ +#define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ /* Broadcom-specific registers */ -#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */ +#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ #define PHY_BCOM_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ /* 0x0b - 0x0e: reserved */ #define PHY_BCOM_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ #define PHY_BCOM_P_EXT_CTRL 0x10 /* 16 bit r/w PHY Extended Ctrl Reg */ #define PHY_BCOM_P_EXT_STAT 0x11 /* 16 bit r/o PHY Extended Stat Reg */ #define PHY_BCOM_RE_CTR 0x12 /* 16 bit r/w Receive Error Counter */ -#define PHY_BCOM_FC_CTR 0x13 /* 16 bit r/w False Carr Sense Cnt */ +#define PHY_BCOM_FC_CTR 0x13 /* 16 bit r/w False Carrier Sense Cnt */ #define PHY_BCOM_RNO_CTR 0x14 /* 16 bit r/w Receiver NOT_OK Cnt */ /* 0x15 - 0x17: reserved */ #define PHY_BCOM_AUX_CTRL 0x18 /* 16 bit r/w Auxiliary Control Reg */ @@ -713,29 +539,37 @@ extern "C" { #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ -#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ +#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */ #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ -#define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */ +#define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ /* Marvel-specific registers */ -#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */ +#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ /* 0x0b - 0x0e: reserved */ #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ -#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Ctrl Reg */ -#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Stat Reg */ +#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */ +#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */ #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ - /* 0x17: reserved */ +#define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */ #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ - /* 0x1d - 0x1f: reserved */ +#define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */ +#define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */ + +/* for 10/100 Fast Ethernet PHY (88E3082 only) */ +#define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */ +#define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */ +#define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */ +#define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */ +#define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */ /*----------------------------------------------------------------------------*/ /* @@ -746,14 +580,14 @@ extern "C" { #define PHY_LONE_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ #define PHY_LONE_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ #define PHY_LONE_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ -#define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ +#define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */ #define PHY_LONE_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ #define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */ -#define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner*/ +#define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ /* Level One-specific registers */ -#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/ +#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ #define PHY_LONE_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ - /* 0x0b -0x0e: reserved */ + /* 0x0b - 0x0e: reserved */ #define PHY_LONE_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ #define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/ #define PHY_LONE_Q_STAT 0x11 /* 16 bit r/o Quick Status Reg */ @@ -762,7 +596,7 @@ extern "C" { #define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */ #define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */ #define PHY_LONE_CIM 0x16 /* 16 bit r/o CIM Reg */ - /* 0x17 -0x1c: reserved */ + /* 0x17 - 0x1c: reserved */ /*----------------------------------------------------------------------------*/ /* @@ -780,14 +614,14 @@ extern "C" { /* National-specific registers */ #define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ #define PHY_NAT_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ - /* 0x0b -0x0e: reserved */ + /* 0x0b - 0x0e: reserved */ #define PHY_NAT_EXT_STAT 0x0f /* 16 bit r/o Extended Status Register */ #define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit r/o Extended Control Reg1 */ #define PHY_NAT_Q_STAT1 0x11 /* 16 bit r/o Quick Status Reg1 */ #define PHY_NAT_10B_OP 0x12 /* 16 bit r/o 10Base-T Operations Reg */ #define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit r/o Extended Control Reg1 */ #define PHY_NAT_Q_STAT2 0x14 /* 16 bit r/o Quick Status Reg2 */ - /* 0x15 -0x18: reserved */ + /* 0x15 - 0x18: reserved */ #define PHY_NAT_PHY_ADDR 0x19 /* 16 bit r/o PHY Address Register */ @@ -795,24 +629,25 @@ extern "C" { /* * PHY bit definitions - * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are - * Xmac/Broadcom/LevelOne/National-specific. + * Bits defined as PHY_X_..., PHY_B_..., PHY_L_..., PHY_N_... or PHY_M_... are + * XMAC/Broadcom/LevelOne/National/Marvell-specific. * All other are general. */ /***** PHY_XMAC_CTRL 16 bit r/w PHY Control Register *****/ /***** PHY_BCOM_CTRL 16 bit r/w PHY Control Register *****/ +/***** PHY_MARV_CTRL 16 bit r/w PHY Status Register *****/ /***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/ #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ -#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */ +#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */ #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ -#define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */ -#define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */ -#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ +#define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */ +#define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */ +#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ -#define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collision Test enabled */ -#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */ +#define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */ +#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */ /* Bit 5..0: reserved */ #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ @@ -825,25 +660,25 @@ extern "C" { /***** PHY_MARV_STAT 16 bit r/w PHY Status Register *****/ /***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/ /* Bit 15..9: reserved */ - /* (BC/L1) 100/10 Mbps cap bits ignored*/ + /* (BC/L1) 100/10 Mbps cap bits ignored */ #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ /* Bit 7: reserved */ -#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: (BC/L1) preamble suppression */ +#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */ #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */ #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ -#define PHY_ST_JAB_DET (1<<1) /* Bit 1: (BC/L1) Jabber Detected */ +#define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */ #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ -/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */ -/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */ -/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */ -/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */ +/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */ +/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */ +/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */ +/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */ #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ -#define PHY_I1_REV_MSK 0x0f /* Bit 3.. 0: Revision Number */ +#define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */ /* different Broadcom PHY Ids */ #define PHY_BCOM_ID1_A1 0x6041 @@ -851,11 +686,21 @@ extern "C" { #define PHY_BCOM_ID1_C0 0x6044 #define PHY_BCOM_ID1_C5 0x6047 +/* different Marvell PHY Ids */ +#define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */ + +#define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1040 Rev.C0) */ +#define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1040 Rev.D0) */ +#define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111 Rev.B1) */ +#define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-XL (PHY 88E1112 Rev.B0) */ +#define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */ +#define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-ECU (PHY 88E1149 Rev.B2?) */ + /***** PHY_XMAC_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ /***** PHY_XMAC_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ #define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */ -#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */ +#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */ #define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remote Fault Bits */ /* Bit 11.. 9: reserved */ #define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */ @@ -901,27 +746,20 @@ extern "C" { /***** PHY_XMAC_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ /* Bit 15..4: reserved */ -#define PHY_AN_LP_NP (1<<3) /* Bit 3: Link Partner can Next Page */ -#define PHY_AN_LOC_NP (1<<2) /* Bit 2: Local PHY can Next Page */ -#define PHY_AN_RX_PG (1<<1) /* Bit 1: Page Received */ +#define PHY_ANE_LP_NP (1<<3) /* Bit 3: Link Partner can Next Page */ +#define PHY_ANE_LOC_NP (1<<2) /* Bit 2: Local PHY can Next Page */ +#define PHY_ANE_RX_PG (1<<1) /* Bit 1: Page Received */ /* Bit 0: reserved */ /***** PHY_BCOM_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ - /* Bit 15..5: reserved */ -#define PHY_B_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */ -/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */ -/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */ -/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */ -#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */ - /***** PHY_LONE_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ -#define PHY_L_AN_BP (1<<5) /* Bit 5: Base Page Indication */ -#define PHY_L_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */ -/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */ -/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */ -/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */ -#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */ - +/***** PHY_MARV_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ + /* Bit 15..5: reserved */ +#define PHY_ANE_PAR_DF (1<<4) /* Bit 4: Parallel Detection Fault */ +/* PHY_ANE_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */ +/* PHY_ANE_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */ +/* PHY_ANE_RX_PG (see XMAC) Bit 1: Page Received */ +#define PHY_ANE_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Able */ /***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/ /***** PHY_BCOM_NEPG 16 bit r/w Next Page Register *****/ @@ -930,9 +768,9 @@ extern "C" { /***** PHY_BCOM_NEPG_LP 16 bit r/o Next Page Link Partner *****/ /***** PHY_LONE_NEPG_LP 16 bit r/o Next Page Link Partner *****/ #define PHY_NP_MORE (1<<15) /* Bit 15: More, Next Pages to follow */ -#define PHY_NP_ACK1 (1<<14) /* Bit 14: (ro) Ack 1, for receiving a message*/ +#define PHY_NP_ACK1 (1<<14) /* Bit 14: (ro) Ack1, for receiving a message */ #define PHY_NP_MSG_VAL (1<<13) /* Bit 13: Message Page valid */ -#define PHY_NP_ACK2 (1<<12) /* Bit 12: Ack 2, comply with msg content*/ +#define PHY_NP_ACK2 (1<<12) /* Bit 12: Ack2, comply with msg content */ #define PHY_NP_TOG (1<<11) /* Bit 11: Toggle Bit, ensure sync */ #define PHY_NP_MSG 0x07ff /* Bit 10..0: Message from/to Link Partner */ @@ -950,7 +788,7 @@ extern "C" { #define PHY_X_RS_HD (1<<6) /* Bit 6: Half Duplex Mode selected */ #define PHY_X_RS_FD (1<<5) /* Bit 5: Full Duplex Mode selected */ #define PHY_X_RS_ABLMIS (1<<4) /* Bit 4: duplex or pause cap mismatch */ -#define PHY_X_RS_PAUMIS (1<<3) /* Bit 3: pause capability missmatch */ +#define PHY_X_RS_PAUMIS (1<<3) /* Bit 3: pause capability mismatch */ /* Bit 2..0: reserved */ /* * Remote Fault Bits (PHY_X_AN_RFB) encoding @@ -982,6 +820,7 @@ extern "C" { /* Bit 7..0: reserved */ /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ +/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ #define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ #define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ #define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ @@ -1009,7 +848,7 @@ extern "C" { #define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */ #define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */ #define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */ -#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */ +#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Enable LED Traffic Mode */ #define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */ #define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */ #define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */ @@ -1123,7 +962,7 @@ extern "C" { #define PHY_L_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ #define PHY_L_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ #define PHY_L_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ -#define PHY_L_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/ +#define PHY_L_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ #define PHY_L_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ #define PHY_L_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ /* Bit 9..8: reserved */ @@ -1163,7 +1002,7 @@ extern "C" { #define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */ #define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */ #define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */ -#define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */ +#define PHY_L_QS_LLE (7<<4) /* Bit 6..4: Line Length Estim. */ #define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */ #define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */ #define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */ @@ -1175,8 +1014,8 @@ extern "C" { #define PHY_L_IS_AN_F (1<<13) /* Bit 13: Auto-Negotiation fault */ /* Bit 12: not described */ #define PHY_L_IS_CROSS (1<<11) /* Bit 11: Crossover used */ -#define PHY_L_IS_POL (1<<10) /* Bit 10: Polarity correct. used*/ -#define PHY_L_IS_SS (1<<9) /* Bit 9: Smart Speed Downgrade*/ +#define PHY_L_IS_POL (1<<10) /* Bit 10: Polarity correct. used */ +#define PHY_L_IS_SS (1<<9) /* Bit 9: Smart Speed Downgrade */ #define PHY_L_IS_CFULL (1<<8) /* Bit 8: Counter Full */ #define PHY_L_IS_AN_C (1<<7) /* Bit 7: AutoNeg Complete */ #define PHY_L_IS_SPEED (1<<6) /* Bit 6: Speed Changed */ @@ -1211,9 +1050,8 @@ extern "C" { /* Bit 9..0: not described */ /***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/ -#define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */ -#define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */ - +#define PHY_L_CIM_ISOL (0xff<<8) /* Bit 15..8: Isolate Count */ +#define PHY_L_CIM_FALSE_CAR 0xff /* Bit 7..0: False Carrier Count */ /* * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding @@ -1223,7 +1061,6 @@ extern "C" { #define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */ #define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */ - /* * National-Specific */ @@ -1267,23 +1104,25 @@ extern "C" { * Marvell-Specific */ /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ -/***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ -#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ -#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ -#define PHY_M_AN_RF BIT_13 /* Remote Fault */ - /* Bit 12: reserved */ -#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ -#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ -#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ -#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ -#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ -#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ +/***** PHY_MARV_AUNE_LP 16 bit r/w Link Partner Ability Reg *****/ +#define PHY_M_AN_NXT_PG BIT_15S /* Request Next Page */ +#define PHY_M_AN_ACK BIT_14S /* (ro) Acknowledge Received */ +#define PHY_M_AN_RF BIT_13S /* Remote Fault */ + /* Bit 12: reserved */ +#define PHY_M_AN_ASP BIT_11S /* Asymmetric Pause */ +#define PHY_M_AN_PC BIT_10S /* MAC Pause implemented */ +#define PHY_M_AN_100_T4 BIT_9S /* Not cap. 100Base-T4 (always 0) */ +#define PHY_M_AN_100_FD BIT_8S /* Advertise 100Base-TX Full Duplex */ +#define PHY_M_AN_100_HD BIT_7S /* Advertise 100Base-TX Half Duplex */ +#define PHY_M_AN_10_FD BIT_6S /* Advertise 10Base-TX Full Duplex */ +#define PHY_M_AN_10_HD BIT_5S /* Advertise 10Base-TX Half Duplex */ +#define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */ -/* special defines for FIBER (88E1011S only) */ -#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ -#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ -#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ -#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ +/* special defines for FIBER (88E1040S only) */ +#define PHY_M_AN_ASP_X BIT_8S /* Asymmetric Pause */ +#define PHY_M_AN_PC_X BIT_7S /* MAC Pause implemented */ +#define PHY_M_AN_1000X_AHD BIT_6S /* Advertise 10000Base-X Half Duplex */ +#define PHY_M_AN_1000X_AFD BIT_5S /* Advertise 10000Base-X Full Duplex */ /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ @@ -1293,102 +1132,168 @@ extern "C" { /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ -#define PHY_M_1000C_MSE (1<<12) /* Bit 12: Manual Master/Slave Enable */ -#define PHY_M_1000C_MSC (1<<11) /* Bit 11: M/S Configuration (1=Master) */ -#define PHY_M_1000C_MPD (1<<10) /* Bit 10: Multi-Port Device */ -#define PHY_M_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ -#define PHY_M_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ +#define PHY_M_1000C_MSE BIT_12S /* Manual Master/Slave Enable */ +#define PHY_M_1000C_MSC BIT_11S /* M/S Configuration (1=Master) */ +#define PHY_M_1000C_MPD BIT_10S /* Multi-Port Device */ +#define PHY_M_1000C_AFD BIT_9S /* Advertise Full Duplex */ +#define PHY_M_1000C_AHD BIT_8S /* Advertise Half Duplex */ /* Bit 7..0: reserved */ /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ +#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ +#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ +#define PHY_M_PC_ASS_CRS_TX BIT_11S /* Assert CRS on Transmit */ +#define PHY_M_PC_FL_GOOD BIT_10S /* Force Link Good */ +#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ +#define PHY_M_PC_ENA_EXT_D BIT_7S /* Enable Ext. Distance (10BT) */ +#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ +#define PHY_M_PC_DIS_125CLK BIT_4S /* Disable 125 CLK */ +#define PHY_M_PC_MAC_POW_UP BIT_3S /* MAC Power up */ +#define PHY_M_PC_SQE_T_ENA BIT_2S /* SQE Test Enabled */ +#define PHY_M_PC_POL_R_DIS BIT_1S /* Polarity Reversal Disabled */ +#define PHY_M_PC_DIS_JABBER BIT_0S /* Disable Jabber */ -#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ -#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ -#define PHY_M_PC_ASS_CRS_TX (1<<11) /* Bit 11: Assert CRS on Transmit */ -#define PHY_M_PC_FL_GOOD (1<<10) /* Bit 10: Force Link Good */ -#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ -#define PHY_M_PC_ENA_EXT_D (1<<7) /* Bit 7: Enable Ext. Distance (10BT) */ -#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ -#define PHY_M_PC_DIS_125CLK (1<<4) /* Bit 4: Disable 125 CLK */ -#define PHY_M_PC_MAC_POW_UP (1<<3) /* Bit 3: MAC Power up */ -#define PHY_M_PC_SQE_T_ENA (1<<2) /* Bit 2: SQE Test Enabled */ -#define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */ -#define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */ +#define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ +#define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ -#define PHY_M_PC_MDI_XMODE(x) SHIFT5(x) -#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ +#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK) + +#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ +/* for Yukon-2/-EC Ultra Gigabit Ethernet PHY (88E1112/88E1149 only) */ +#define PHY_M_PC_DIS_LINK_P BIT_15S /* Disable Link Pulses */ +#define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */ +#define PHY_M_PC_DOWN_S_ENA BIT_11S /* Downshift Enable */ + /* !!! Errata in spec. (1 = disable) */ + +#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK) + /* 000=1x; 001=2x; 010=3x; 011=4x */ + /* 100=5x; 101=6x; 110=7x; 111=8x */ + +/* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */ + /* Bit 4: reserved */ +#define PHY_M_PC_COP_TX_DIS BIT_3S /* Copper Transmitter Disable */ +#define PHY_M_PC_POW_D_ENA BIT_2S /* Power Down Enable */ + +/* for 10/100 Fast Ethernet PHY (88E3082 only) */ +#define PHY_M_PC_ENA_DTE_DT BIT_15S /* Enable Data Terminal Equ. (DTE) Detect */ +#define PHY_M_PC_ENA_ENE_DT BIT_14S /* Enable Energy Detect (sense & pulse) */ +#define PHY_M_PC_DIS_NLP_CK BIT_13S /* Disable Normal Link Puls (NLP) Check */ +#define PHY_M_PC_ENA_LIP_NP BIT_12S /* Enable Link Partner Next Page Reg. */ +#define PHY_M_PC_DIS_NLP_GN BIT_11S /* Disable Normal Link Puls Generation */ + +#define PHY_M_PC_DIS_SCRAMB BIT_9S /* Disable Scrambler */ +#define PHY_M_PC_DIS_FEFI BIT_8S /* Disable Far End Fault Indic. (FEFI) */ + +#define PHY_M_PC_SH_TP_SEL BIT_6S /* Shielded Twisted Pair Select */ +#define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */ + /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ -#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ -#define PHY_M_PS_SPEED_1000 (1<<15) /* 10 = 1000 Mbps */ -#define PHY_M_PS_SPEED_100 (1<<14) /* 01 = 100 Mbps */ -#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ -#define PHY_M_PS_FULL_DUP (1<<13) /* Bit 13: Full Duplex */ -#define PHY_M_PS_PAGE_REC (1<<12) /* Bit 12: Page Received */ -#define PHY_M_PS_SPDUP_RES (1<<11) /* Bit 11: Speed & Duplex Resolved */ -#define PHY_M_PS_LINK_UP (1<<10) /* Bit 10: Link Up */ -#define PHY_M_PS_CABLE_MSK (3<<7) /* Bit 9.. 7: Cable Length Mask */ -#define PHY_M_PS_MDI_X_STAT (1<<6) /* Bit 6: MDI Crossover Stat (1=MDIX) */ -#define PHY_M_PS_DOWNS_STAT (1<<5) /* Bit 5: Downshift Status (1=downsh.) */ -#define PHY_M_PS_ENDET_STAT (1<<4) /* Bit 4: Energy Detect Status (1=act) */ -#define PHY_M_PS_TX_P_EN (1<<3) /* Bit 3: Tx Pause Enabled */ -#define PHY_M_PS_RX_P_EN (1<<2) /* Bit 2: Rx Pause Enabled */ -#define PHY_M_PS_POL_REV (1<<1) /* Bit 1: Polarity Reversed */ -#define PHY_M_PC_JABBER (1<<0) /* Bit 0: Jabber */ +#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ +#define PHY_M_PS_SPEED_1000 BIT_15S /* 10 = 1000 Mbps */ +#define PHY_M_PS_SPEED_100 BIT_14S /* 01 = 100 Mbps */ +#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ +#define PHY_M_PS_FULL_DUP BIT_13S /* Full Duplex */ +#define PHY_M_PS_PAGE_REC BIT_12S /* Page Received */ +#define PHY_M_PS_SPDUP_RES BIT_11S /* Speed & Duplex Resolved */ +#define PHY_M_PS_LINK_UP BIT_10S /* Link Up */ +#define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */ +#define PHY_M_PS_MDI_X_STAT BIT_6S /* MDI Crossover Stat (1=MDIX) */ +#define PHY_M_PS_DOWNS_STAT BIT_5S /* Downshift Status (1=downsh.) */ +#define PHY_M_PS_ENDET_STAT BIT_4S /* Energy Detect Status (1=act) */ +#define PHY_M_PS_TX_P_EN BIT_3S /* Tx Pause Enabled */ +#define PHY_M_PS_RX_P_EN BIT_2S /* Rx Pause Enabled */ +#define PHY_M_PS_POL_REV BIT_1S /* Polarity Reversed */ +#define PHY_M_PS_JABBER BIT_0S /* Jabber */ #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) +/* for 10/100 Fast Ethernet PHY (88E3082 only) */ +#define PHY_M_PS_DTE_DETECT BIT_15S /* Data Terminal Equipment (DTE) Detected */ +#define PHY_M_PS_RES_SPEED BIT_14S /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ + /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ -#define PHY_M_IS_AN_ERROR (1<<15) /* Bit 15: Auto-Negotiation Error */ -#define PHY_M_IS_LSP_CHANGE (1<<14) /* Bit 14: Link Speed Changed */ -#define PHY_M_IS_DUP_CHANGE (1<<13) /* Bit 13: Duplex Mode Changed */ -#define PHY_M_IS_AN_PR (1<<12) /* Bit 12: Page Received */ -#define PHY_M_IS_AN_COMPL (1<<11) /* Bit 11: Auto-Negotiation Completed */ -#define PHY_M_IS_LST_CHANGE (1<<10) /* Bit 10: Link Status Changed */ -#define PHY_M_IS_SYMB_ERROR (1<<9) /* Bit 9: Symbol Error */ -#define PHY_M_IS_FALSE_CARR (1<<8) /* Bit 8: False Carrier */ -#define PHY_M_IS_FIFO_ERROR (1<<7) /* Bit 7: FIFO Overflow/Underrun Error */ -#define PHY_M_IS_MDI_CHANGE (1<<6) /* Bit 6: MDI Crossover Changed */ -#define PHY_M_IS_DOWNSH_DET (1<<5) /* Bit 5: Downshift Detected */ -#define PHY_M_IS_END_CHANGE (1<<4) /* Bit 4: Energy Detect Changed */ - /* Bit 3..2: reserved */ -#define PHY_M_IS_POL_CHANGE (1<<1) /* Bit 1: Polarity Changed */ -#define PHY_M_IS_JABBER (1<<0) /* Bit 0: Jabber */ +#define PHY_M_IS_AN_ERROR BIT_15S /* Auto-Negotiation Error */ +#define PHY_M_IS_LSP_CHANGE BIT_14S /* Link Speed Changed */ +#define PHY_M_IS_DUP_CHANGE BIT_13S /* Duplex Mode Changed */ +#define PHY_M_IS_AN_PR BIT_12S /* Page Received */ +#define PHY_M_IS_AN_COMPL BIT_11S /* Auto-Negotiation Completed */ +#define PHY_M_IS_LST_CHANGE BIT_10S /* Link Status Changed */ +#define PHY_M_IS_SYMB_ERROR BIT_9S /* Symbol Error */ +#define PHY_M_IS_FALSE_CARR BIT_8S /* False Carrier */ +#define PHY_M_IS_FIFO_ERROR BIT_7S /* FIFO Overflow/Underrun Error */ +#define PHY_M_IS_MDI_CHANGE BIT_6S /* MDI Crossover Changed */ +#define PHY_M_IS_DOWNSH_DET BIT_5S /* Downshift Detected */ +#define PHY_M_IS_END_CHANGE BIT_4S /* Energy Detect Changed */ + /* Bit 3: reserved */ +#define PHY_M_IS_DTE_CHANGE BIT_2S /* DTE Power Det. Status Changed */ + /* (88E1111 only) */ +#define PHY_M_IS_POL_CHANGE BIT_1S /* Polarity Changed */ +#define PHY_M_IS_JABBER BIT_0S /* Jabber */ #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ - PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) + PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR | \ + PHY_M_IS_END_CHANGE) /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ -#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master downshift counter */ -#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave downshift counter */ +#define PHY_M_EC_ENA_BC_EXT BIT_15S /* Enable Block Carr. Ext. (88E1111 only) */ +#define PHY_M_EC_ENA_LIN_LB BIT_14S /* Enable Line Loopback (88E1111 only) */ + /* Bit 13: reserved */ +#define PHY_M_EC_DIS_LINK_P BIT_12S /* Disable Link Pulses (88E1111 only) */ +#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */ + /* (88E1040 Rev.C0 only) */ +#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */ + /* (88E1040 Rev.C0 only) */ +#define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */ + /* (88E1040 Rev.D0 and higher) */ +#define PHY_M_EC_DOWN_S_ENA BIT_8S /* Downshift Enable (88E1040 Rev.D0 and */ + /* 88E1111 !!! Errata in spec. (1=dis.) */ +#define PHY_M_EC_RX_TIM_CT BIT_7S /* RGMII Rx Timing Control*/ #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ +#define PHY_M_EC_FIB_AN_ENA BIT_3S /* Fiber Auto-Neg. Enable 88E1040S only) */ +#define PHY_M_EC_DTE_D_ENA BIT_2S /* DTE Detect Enable (88E1111 only) */ +#define PHY_M_EC_TX_TIM_CT BIT_1S /* RGMII Tx Timing Control */ +#define PHY_M_EC_TRANS_DIS BIT_0S /* Transmitter Disable (88E1111 only) */ -#define PHY_M_EC_M_DSC(x) SHIFT10(x) /* 00=1x; 01=2x; 10=3x; 11=4x */ -#define PHY_M_EC_S_DSC(x) SHIFT8(x) /* 00=dis; 01=1x; 10=2x; 11=3x */ -#define PHY_M_EC_MAC_S(x) SHIFT4(x) /* 01X=0; 110=2.5; 111=25 (MHz) */ +#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK) + /* 00=1x; 01=2x; 10=3x; 11=4x */ +#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK) + /* 00=dis; 01=1x; 10=2x; 11=3x */ +#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK) + /* 01X=0; 110=2.5; 111=25 (MHz) */ +#define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2) + /* 000=1x; 001=2x; 010=3x; 011=4x */ + /* 100=5x; 101=6x; 110=7x; 111=8x */ #define MAC_TX_CLK_0_MHZ 2 #define MAC_TX_CLK_2_5_MHZ 6 #define MAC_TX_CLK_25_MHZ 7 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ -#define PHY_M_LEDC_DIS_LED (1<<15) /* Bit 15: Disable LED */ -#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ -#define PHY_M_LEDC_F_INT (1<<11) /* Bit 11: Force Interrupt */ -#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ - /* Bit 7.. 5: reserved */ -#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ -#define PHY_M_LEDC_DP_CTRL (1<<2) /* Bit 2: Duplex Control */ -#define PHY_M_LEDC_RX_CTRL (1<<1) /* Bit 1: Rx activity / Link */ -#define PHY_M_LEDC_TX_CTRL (1<<0) /* Bit 0: Tx activity / Link */ +#define PHY_M_LEDC_DIS_LED BIT_15S /* Disable LED */ +#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ +#define PHY_M_LEDC_F_INT BIT_11S /* Force Interrupt */ +#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ +#define PHY_M_LEDC_DP_C_LSB BIT_7S /* Duplex Control (LSB, 88E1111 only) */ +#define PHY_M_LEDC_TX_C_LSB BIT_6S /* Tx Control (LSB, 88E1111 only) */ +#define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */ + /* (88E1111 only) */ + /* Bit 7.. 5: reserved (88E1040 only) */ +#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ + /* (88E1040 only) */ +#define PHY_M_LEDC_DP_CTRL BIT_2S /* Duplex Control */ +#define PHY_M_LEDC_DP_C_MSB BIT_2S /* Duplex Control (MSB, 88E1111 only) */ +#define PHY_M_LEDC_RX_CTRL BIT_1S /* Rx Activity / Link */ +#define PHY_M_LEDC_TX_CTRL BIT_0S /* Tx Activity / Link */ +#define PHY_M_LEDC_TX_C_MSB BIT_0S /* Tx Control (MSB, 88E1111 only) */ -#define PHY_M_LED_PULS_DUR(x) SHIFT12(x) /* Pulse Stretch Duration */ +#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) -#define PULS_NO_STR 0 /* no pulse stretching */ -#define PULS_21MS 1 /* 21 ms to 42 ms */ +#define PULS_NO_STR 0 /* no pulse stretching */ +#define PULS_21MS 1 /* 21 ms to 42 ms */ #define PULS_42MS 2 /* 42 ms to 84 ms */ #define PULS_84MS 3 /* 84 ms to 170 ms */ #define PULS_170MS 4 /* 170 ms to 340 ms */ @@ -1396,7 +1301,7 @@ extern "C" { #define PULS_670MS 6 /* 670 ms to 1.3 s */ #define PULS_1300MS 7 /* 1.3 s to 2.7 s */ -#define PHY_M_LED_BLINK_RT(x) SHIFT8(x) /* Blink Rate */ +#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) #define BLINK_42MS 0 /* 42 ms */ #define BLINK_84MS 1 /* 84 ms */ @@ -1406,6 +1311,8 @@ extern "C" { /* values 5 - 7: reserved */ /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ +#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ + /* Bit 13..12: reserved */ #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ @@ -1419,18 +1326,35 @@ extern "C" { #define MO_LED_ON 3 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ - /* Bit 15.. 7: reserved */ -#define PHY_M_EC2_FI_IMPED (1<<6) /* Bit 6: Fiber Input Impedance */ -#define PHY_M_EC2_FO_IMPED (1<<5) /* Bit 5: Fiber Output Impedance */ -#define PHY_M_EC2_FO_M_CLK (1<<4) /* Bit 4: Fiber Mode Clock Enable */ -#define PHY_M_EC2_FO_BOOST (1<<3) /* Bit 3: Fiber Output Boost */ + /* Bit 15.. 7: reserved */ +#define PHY_M_EC2_FI_IMPED BIT_6S /* Fiber Input Impedance */ +#define PHY_M_EC2_FO_IMPED BIT_5S /* Fiber Output Impedance */ +#define PHY_M_EC2_FO_M_CLK BIT_4S /* Fiber Mode Clock Enable */ +#define PHY_M_EC2_FO_BOOST BIT_3S /* Fiber Output Boost */ #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ +/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ +#define PHY_M_FC_AUTO_SEL BIT_15S /* Fiber/Copper Auto Sel. Dis. */ +#define PHY_M_FC_AN_REG_ACC BIT_14S /* Fiber/Copper AN Reg. Access */ +#define PHY_M_FC_RESOLUTION BIT_13S /* Fiber/Copper Resolution */ +#define PHY_M_SER_IF_AN_BP BIT_12S /* Ser. IF AN Bypass Enable */ +#define PHY_M_SER_IF_BP_ST BIT_11S /* Ser. IF AN Bypass Status */ +#define PHY_M_IRQ_POLARITY BIT_10S /* IRQ polarity */ +#define PHY_M_DIS_AUT_MED BIT_9S /* Disable Aut. Medium Reg. Selection */ + /* (88E1111 only) */ + /* Bit 9.. 4: reserved (88E1040 only) */ +#define PHY_M_UNDOC1 BIT_7S /* undocumented bit !! */ +#define PHY_M_DTE_POW_STAT BIT_4S /* DTE Power Status (88E1111 only) */ +#define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ + /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ -#define PHY_M_CABD_ENA_TEST (1<<15) /* Bit 15: Enable Test */ -#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status */ - /* Bit 12.. 8: reserved */ -#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance */ +#define PHY_M_CABD_ENA_TEST BIT_15S /* Enable Test (Page 0) */ +#define PHY_M_CABD_DIS_WAIT BIT_15S /* Disable Waiting Period (Page 1) */ + /* (88E1111 only) */ +#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */ +#define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */ + /* (88E1111 only) */ +#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */ /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ #define CABD_STAT_NORMAL 0 @@ -1438,6 +1362,79 @@ extern "C" { #define CABD_STAT_OPEN 2 #define CABD_STAT_FAIL 3 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */ +/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ + /* Bit 15..12: reserved (used internally) */ +#define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */ +#define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */ +#define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */ + +#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK) +#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK) +#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK) + +#define LED_PAR_CTRL_COLX 0x00 +#define LED_PAR_CTRL_ERROR 0x01 +#define LED_PAR_CTRL_DUPLEX 0x02 +#define LED_PAR_CTRL_DP_COL 0x03 +#define LED_PAR_CTRL_SPEED 0x04 +#define LED_PAR_CTRL_LINK 0x05 +#define LED_PAR_CTRL_TX 0x06 +#define LED_PAR_CTRL_RX 0x07 +#define LED_PAR_CTRL_ACT 0x08 +#define LED_PAR_CTRL_LNK_RX 0x09 +#define LED_PAR_CTRL_LNK_AC 0x0a +#define LED_PAR_CTRL_ACT_BL 0x0b +#define LED_PAR_CTRL_TX_BL 0x0c +#define LED_PAR_CTRL_RX_BL 0x0d +#define LED_PAR_CTRL_COL_BL 0x0e +#define LED_PAR_CTRL_INACT 0x0f + +/***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ +#define PHY_M_FESC_DIS_WAIT BIT_2S /* Disable TDR Waiting Period */ +#define PHY_M_FESC_ENA_MCLK BIT_1S /* Enable MAC Rx Clock in sleep mode */ +#define PHY_M_FESC_SEL_CL_A BIT_0S /* Select Class A driver (100B-TX) */ + +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ +/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ +#define PHY_M_FIB_FORCE_LNK BIT_10S /* Force Link Good */ +#define PHY_M_FIB_SIGD_POL BIT_9S /* SIGDET Polarity */ +#define PHY_M_FIB_TX_DIS BIT_3S /* Transmitter Disable */ + +/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ +#define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */ +#define PHY_M_MAC_GMIF_PUP BIT_3S /* GMII Power Up (88E1149 only) */ + +#define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */ +#define PHY_M_MAC_MD_COPPER 5 /* Copper only */ +#define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */ +#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK) + +/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ +#define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */ +#define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */ +#define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */ +#define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ + +#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK) +#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK) +#define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK) +#define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK) + +/***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/ +#define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */ +#define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ +#define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ +#define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ +#define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ +#define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ + +#define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK) +#define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK) +#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK) +#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK) +#define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK) +#define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK) /* * GMAC registers @@ -1460,7 +1457,7 @@ extern "C" { #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ -#define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow Control */ +#define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */ #define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ #define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ @@ -1523,7 +1520,7 @@ extern "C" { #define GM_RXF_SHT \ (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ #define GM_RXE_FRAG \ - (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Receeived with FCS Err */ + (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */ #define GM_RXF_64B \ (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ #define GM_RXF_127B \ @@ -1598,133 +1595,159 @@ extern "C" { */ /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ - -#define GM_GPSR_SPEED (1<<15) /* Bit 15: Port Speed (1 = 100 Mbps) */ -#define GM_GPSR_DUPLEX (1<<14) /* Bit 14: Duplex Mode (1 = Full) */ -#define GM_GPSR_FC_TX_DIS (1<<13) /* Bit 13: Tx Flow Control Mode Disabled */ -#define GM_GPSR_LINK_UP (1<<12) /* Bit 12: Link Up Status */ -#define GM_GPSR_PAUSE (1<<11) /* Bit 11: Pause State */ -#define GM_GPSR_TX_ACTIVE (1<<10) /* Bit 10: Tx in Progress */ -#define GM_GPSR_EXC_COL (1<<9) /* Bit 9: Excessive Collisions Occured */ -#define GM_GPSR_LAT_COL (1<<8) /* Bit 8: Late Collisions Occured */ - /* Bit 7..6: reserved */ -#define GM_GPSR_PHY_ST_CH (1<<5) /* Bit 5: PHY Status Change */ -#define GM_GPSR_GIG_SPEED (1<<4) /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ -#define GM_GPSR_PART_MODE (1<<3) /* Bit 3: Partition mode */ -#define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow Control Mode Disabled */ -#define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */ - /* Bit 0: reserved */ +#define GM_GPSR_SPEED BIT_15S /* Port Speed (1 = 100 Mbps) */ +#define GM_GPSR_DUPLEX BIT_14S /* Duplex Mode (1 = Full) */ +#define GM_GPSR_FC_TX_DIS BIT_13S /* Tx Flow-Control Mode Disabled */ +#define GM_GPSR_LINK_UP BIT_12S /* Link Up Status */ +#define GM_GPSR_PAUSE BIT_11S /* Pause State */ +#define GM_GPSR_TX_ACTIVE BIT_10S /* Tx in Progress */ +#define GM_GPSR_EXC_COL BIT_9S /* Excessive Collisions Occured */ +#define GM_GPSR_LAT_COL BIT_8S /* Late Collisions Occured */ + /* Bit 7.. 6: reserved */ +#define GM_GPSR_PHY_ST_CH BIT_5S /* PHY Status Change */ +#define GM_GPSR_GIG_SPEED BIT_4S /* Gigabit Speed (1 = 1000 Mbps) */ +#define GM_GPSR_PART_MODE BIT_3S /* Partition mode */ +#define GM_GPSR_FC_RX_DIS BIT_2S /* Rx Flow-Control Mode Disabled */ + /* Bit 2.. 0: reserved */ /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ - /* Bit 15: reserved */ -#define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */ -#define GM_GPCR_FC_TX_DIS (1<<13) /* Bit 13: Disable Tx Flow Control Mode */ -#define GM_GPCR_TX_ENA (1<<12) /* Bit 12: Enable Transmit */ -#define GM_GPCR_RX_ENA (1<<11) /* Bit 11: Enable Receive */ -#define GM_GPCR_BURST_ENA (1<<10) /* Bit 10: Enable Burst Mode */ -#define GM_GPCR_LOOP_ENA (1<<9) /* Bit 9: Enable MAC Loopback Mode */ -#define GM_GPCR_PART_ENA (1<<8) /* Bit 8: Enable Partition Mode */ -#define GM_GPCR_GIGS_ENA (1<<7) /* Bit 7: Gigabit Speed (1000 Mbps) */ -#define GM_GPCR_FL_PASS (1<<6) /* Bit 6: Force Link Pass */ -#define GM_GPCR_DUP_FULL (1<<5) /* Bit 5: Full Duplex Mode */ -#define GM_GPCR_FC_RX_DIS (1<<4) /* Bit 4: Disable Rx Flow Control Mode */ -#define GM_GPCR_SPEED_100 (1<<3) /* Bit 3: Port Speed 100 Mbps */ -#define GM_GPCR_AU_DUP_DIS (1<<2) /* Bit 2: Disable Auto-Update for Duplex */ -#define GM_GPCR_AU_FCT_DIS (1<<1) /* Bit 1: Disable Auto-Update for Flow-c. */ -#define GM_GPCR_AU_SPD_DIS (1<<0) /* Bit 0: Disable Auto-Update for Speed */ +#define GM_GPCR_RMII_PH_ENA BIT_15S /* Enable RMII for PHY (Yukon-FE only) */ +#define GM_GPCR_RMII_LB_ENA BIT_14S /* Enable RMII Loopback (Yukon-FE only) */ +#define GM_GPCR_FC_TX_DIS BIT_13S /* Disable Tx Flow-Control Mode */ +#define GM_GPCR_TX_ENA BIT_12S /* Enable Transmit */ +#define GM_GPCR_RX_ENA BIT_11S /* Enable Receive */ + /* Bit 10: reserved */ +#define GM_GPCR_LOOP_ENA BIT_9S /* Enable MAC Loopback Mode */ +#define GM_GPCR_PART_ENA BIT_8S /* Enable Partition Mode */ +#define GM_GPCR_GIGS_ENA BIT_7S /* Gigabit Speed (1000 Mbps) */ +#define GM_GPCR_FL_PASS BIT_6S /* Force Link Pass */ +#define GM_GPCR_DUP_FULL BIT_5S /* Full Duplex Mode */ +#define GM_GPCR_FC_RX_DIS BIT_4S /* Disable Rx Flow-Control Mode */ +#define GM_GPCR_SPEED_100 BIT_3S /* Port Speed 100 Mbps */ +#define GM_GPCR_AU_DUP_DIS BIT_2S /* Disable Auto-Update Duplex */ +#define GM_GPCR_AU_FCT_DIS BIT_1S /* Disable Auto-Update Flow-C. */ +#define GM_GPCR_AU_SPD_DIS BIT_0S /* Disable Auto-Update Speed */ #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ GM_GPCR_AU_SPD_DIS) /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ +#define GM_TXCR_FORCE_JAM BIT_15S /* Force Jam / Flow-Control */ +#define GM_TXCR_CRC_DIS BIT_14S /* Disable insertion of CRC */ +#define GM_TXCR_PAD_DIS BIT_13S /* Disable padding of packets */ +#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */ + /* Bit 9.. 8: reserved */ +#define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */ + /* (Yukon-2 only) */ -#define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */ -#define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */ -#define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */ -#define GM_TXCR_COL_THR (4<<10) /* Bit 12..10: Collision Threshold */ +#define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) + +#define TX_COL_DEF 0x04 /* GM_RX_CTRL 16 bit r/w Receive Control Register */ -#define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */ -#define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */ -#define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */ -#define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */ +#define GM_RXCR_UCF_ENA BIT_15S /* Enable Unicast filtering */ +#define GM_RXCR_MCF_ENA BIT_14S /* Enable Multicast filtering */ +#define GM_RXCR_CRC_DIS BIT_13S /* Remove 4-byte CRC */ +#define GM_RXCR_PASS_FC BIT_12S /* Pass FC packets to FIFO (Yukon-1 only) */ + /* Bit 11.. 0: reserved */ /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ -#define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */ -#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */ -#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8..4: IPG Jam to Data */ - /* Bit 3..0: reserved */ -#define JAM_LEN_VAL(x) SHIFT14(x) -#define JAM_IPG_VAL(x) SHIFT9(x) -#define IPG_JAM_DATA(x) SHIFT4(x) +#define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */ +#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */ +#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */ +#define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */ + /* (Yukon-2 only) */ + +#define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) +#define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) +#define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) +#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) + +#define TX_JAM_LEN_DEF 0x03 +#define TX_JAM_IPG_DEF 0x0b +#define TX_IPG_JAM_DEF 0x1c +#define TX_BOF_LIM_DEF 0x04 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ #define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ -#define GM_SMOD_LIMIT_4 (1<<10) /* Bit 10: 4 consecutive transmit trials */ -#define GM_SMOD_VLAN_ENA (1<<9) /* Bit 9: Enable VLAN (Max. Frame Length) */ -#define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Length) */ - /* Bit 7..5: reserved */ -#define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ + /* r/o on Yukon, r/w on Yukon-EC */ +#define GM_SMOD_LIMIT_4 BIT_10S /* 4 consecutive Tx trials */ +#define GM_SMOD_VLAN_ENA BIT_9S /* Enable VLAN (Max. Frame Len) */ +#define GM_SMOD_JUMBO_ENA BIT_8S /* Enable Jumbo (Max. Frame Len) */ + /* Bit 7.. 5: reserved */ +#define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */ -#define DATA_BLIND_VAL(x) SHIFT11(x) -#define DATA_BLIND_FAST_ETH 0x1c -#define DATA_BLIND_GIGABIT 4 +#define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK) +#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK) -#define IPG_VAL_FAST_ETH 0x1e -#define IPG_VAL_GIGABIT 6 +#define DATA_BLIND_DEF 0x04 +#define IPG_DATA_DEF 0x1e /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ +#define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ +#define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ +#define GM_SMI_CT_OP_RD BIT_5S /* OpCode Read (0=Write)*/ +#define GM_SMI_CT_RD_VAL BIT_4S /* Read Valid (Read completed) */ +#define GM_SMI_CT_BUSY BIT_3S /* Busy (Operation in progress) */ + /* Bit 2.. 0: reserved */ -#define GM_SMI_CT_PHY_AD(x) SHIFT11(x) -#define GM_SMI_CT_REG_AD(x) SHIFT6(x) -#define GM_SMI_CT_OP_RD (1<<5) /* Bit 5: OpCode Read (0=Write)*/ -#define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */ -#define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */ - /* Bit 2..0: reserved */ +#define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) +#define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ - /* Bit 15..6: reserved */ -#define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */ -#define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */ - /* Bit 3..0: reserved */ + /* Bit 15.. 6: reserved */ +#define GM_PAR_MIB_CLR BIT_5S /* Set MIB Clear Counter Mode */ +#define GM_PAR_MIB_TST BIT_4S /* MIB Load Counter (Test Mode) */ + /* Bit 3.. 0: reserved */ /* Receive Frame Status Encoding */ -#define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */ +#define GMR_FS_LEN_MSK (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */ /* Bit 15..14: reserved */ -#define GMR_FS_VLAN (1L<<13) /* Bit 13: VLAN Packet */ -#define GMR_FS_JABBER (1L<<12) /* Bit 12: Jabber Packet */ -#define GMR_FS_UN_SIZE (1L<<11) /* Bit 11: Undersize Packet */ -#define GMR_FS_MC (1L<<10) /* Bit 10: Multicast Packet */ -#define GMR_FS_BC (1L<<9) /* Bit 9: Broadcast Packet */ -#define GMR_FS_RX_OK (1L<<8) /* Bit 8: Receive OK (Good Packet) */ -#define GMR_FS_GOOD_FC (1L<<7) /* Bit 7: Good Flow-Control Packet */ -#define GMR_FS_BAD_FC (1L<<6) /* Bit 6: Bad Flow-Control Packet */ -#define GMR_FS_MII_ERR (1L<<5) /* Bit 5: MII Error */ -#define GMR_FS_LONG_ERR (1L<<4) /* Bit 4: Too Long Packet */ -#define GMR_FS_FRAGMENT (1L<<3) /* Bit 3: Fragment */ +#define GMR_FS_VLAN BIT_13 /* VLAN Packet */ +#define GMR_FS_JABBER BIT_12 /* Jabber Packet */ +#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */ +#define GMR_FS_MC BIT_10 /* Multicast Packet */ +#define GMR_FS_BC BIT_9 /* Broadcast Packet */ +#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */ +#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */ +#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */ +#define GMR_FS_MII_ERR BIT_5 /* MII Error */ +#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */ +#define GMR_FS_FRAGMENT BIT_3 /* Fragment */ /* Bit 2: reserved */ -#define GMR_FS_CRC_ERR (1L<<1) /* Bit 1: CRC Error */ -#define GMR_FS_RX_FF_OV (1L<<0) /* Bit 0: Rx FIFO Overflow */ +#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */ +#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */ + +#define GMR_FS_LEN_SHIFT 16 /* * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR) */ -#define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \ - GMR_FS_LONG_ERR | \ +#ifdef SK_DIAG +#define GMR_FS_ANY_ERR ( \ + GMR_FS_RX_FF_OV | \ + GMR_FS_CRC_ERR | \ + GMR_FS_FRAGMENT | \ GMR_FS_MII_ERR | \ GMR_FS_BAD_FC | \ GMR_FS_GOOD_FC | \ GMR_FS_JABBER) - -/* Rx GMAC FIFO Flush Mask (default) */ -#define RX_FF_FL_DEF_MSK (GMR_FS_CRC_ERR | \ +#else +#define GMR_FS_ANY_ERR ( \ GMR_FS_RX_FF_OV | \ + GMR_FS_CRC_ERR | \ + GMR_FS_FRAGMENT | \ + GMR_FS_LONG_ERR | \ GMR_FS_MII_ERR | \ GMR_FS_BAD_FC | \ GMR_FS_GOOD_FC | \ GMR_FS_UN_SIZE | \ GMR_FS_JABBER) +#endif + +/* Rx GMAC FIFO Flush Mask (default) */ +#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR /* typedefs *******************************************************************/ @@ -1736,3 +1759,4 @@ extern "C" { #endif /* __cplusplus */ #endif /* __INC_XMAC_H */ + diff --git a/drivers/sk98lin/skaddr.c b/drivers/sk98lin/skaddr.c index ed79c04..84f545a 100644 --- a/drivers/sk98lin/skaddr.c +++ b/drivers/sk98lin/skaddr.c @@ -1,16 +1,18 @@ /****************************************************************************** * * Name: skaddr.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.48 $ - * Date: $Date: 2003/02/12 17:09:37 $ + * Project: Gigabit Ethernet Adapters, ADDR-Module + * Version: $Revision: 2.9 $ + * Date: $Date: 2005/12/14 16:11:44 $ * Purpose: Manage Addresses (Multicast and Unicast) and Promiscuous Mode. * ******************************************************************************/ /****************************************************************************** * + * LICENSE: * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2005 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,183 +20,7 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: skaddr.c,v $ - * Revision 1.48 2003/02/12 17:09:37 tschilli - * Fix in SkAddrOverride() to set both (physical and logical) MAC addresses - * in case that both addresses are identical. - * - * Revision 1.47 2002/09/17 06:31:10 tschilli - * Handling of SK_PROM_MODE_ALL_MC flag in SkAddrGmacMcUpdate() - * and SkAddrGmacPromiscuousChange() fixed. - * Editorial changes. - * - * Revision 1.46 2002/08/22 07:55:41 tschilli - * New function SkGmacMcHash() for GMAC multicast hashing algorithm added. - * Editorial changes. - * - * Revision 1.45 2002/08/15 12:29:35 tschilli - * SkAddrGmacMcUpdate() and SkAddrGmacPromiscuousChange() changed. - * - * Revision 1.44 2002/08/14 12:18:03 rschmidt - * Replaced direct handling of MAC Hashing (XMAC and GMAC) - * with routine SkMacHashing(). - * Replaced wrong 3rd para 'i' with 'PortNumber' in SkMacPromiscMode(). - * - * Revision 1.43 2002/08/13 09:37:43 rschmidt - * Corrected some SK_DBG_MSG outputs. - * Replaced wrong 2nd para pAC with IoC in SkMacPromiscMode(). - * Editorial changes. - * - * Revision 1.42 2002/08/12 11:24:36 rschmidt - * Remove setting of logical MAC address GM_SRC_ADDR_2 in SkAddrInit(). - * Replaced direct handling of MAC Promiscuous Mode (XMAC and GMAC) - * with routine SkMacPromiscMode(). - * Editorial changes. - * - * Revision 1.41 2002/06/10 13:52:18 tschilli - * Changes for handling YUKON. - * All changes are internally and not visible to the programmer - * using this module. - * - * Revision 1.40 2001/02/14 14:04:59 rassmann - * Editorial changes. - * - * Revision 1.39 2001/01/30 10:30:04 rassmann - * Editorial changes. - * - * Revision 1.38 2001/01/25 16:26:52 rassmann - * Ensured that logical address overrides are done on net's active port. - * - * Revision 1.37 2001/01/22 13:41:34 rassmann - * Supporting two nets on dual-port adapters. - * - * Revision 1.36 2000/08/07 11:10:39 rassmann - * Editorial changes. - * - * Revision 1.35 2000/05/04 09:38:41 rassmann - * Editorial changes. - * Corrected multicast address hashing. - * - * Revision 1.34 1999/11/22 13:23:44 cgoos - * Changed license header to GPL. - * - * Revision 1.33 1999/05/28 10:56:06 rassmann - * Editorial changes. - * - * Revision 1.32 1999/03/31 10:59:20 rassmann - * Returning Success instead of DupAddr if address shall be overridden - * with same value. - * - * Revision 1.31 1999/01/14 16:18:17 rassmann - * Corrected multicast initialization. - * - * Revision 1.30 1999/01/04 10:30:35 rassmann - * SkAddrOverride only possible after SK_INIT_IO phase. - * - * Revision 1.29 1998/12/29 13:13:10 rassmann - * An address override is now preserved in the SK_INIT_IO phase. - * All functions return an int now. - * Extended parameter checking. - * - * Revision 1.28 1998/12/01 11:45:53 rassmann - * Code cleanup. - * - * Revision 1.27 1998/12/01 09:22:49 rassmann - * SkAddrMcAdd and SkAddrMcUpdate returned SK_MC_FILTERING_INEXACT - * too often. - * - * Revision 1.26 1998/11/24 12:39:44 rassmann - * Reserved multicast entry for BPDU address. - * 13 multicast entries left for protocol. - * - * Revision 1.25 1998/11/17 16:54:23 rassmann - * Using exact match for up to 14 multicast addresses. - * Still receiving all multicasts if more addresses are added. - * - * Revision 1.24 1998/11/13 17:24:31 rassmann - * Changed return value of SkAddrOverride to int. - * - * Revision 1.23 1998/11/13 16:56:18 rassmann - * Added macro SK_ADDR_COMPARE. - * Changed return type of SkAddrOverride to SK_BOOL. - * - * Revision 1.22 1998/11/04 17:06:17 rassmann - * Corrected McUpdate and PromiscuousChange functions. - * - * Revision 1.21 1998/10/29 14:34:04 rassmann - * Clearing SK_ADDR struct at startup. - * - * Revision 1.20 1998/10/28 18:16:34 rassmann - * Avoiding I/Os before SK_INIT_RUN level. - * Aligning InexactFilter. - * - * Revision 1.19 1998/10/28 11:29:28 rassmann - * Programming physical address in SkAddrMcUpdate. - * Corrected programming of exact match entries. - * - * Revision 1.18 1998/10/28 10:34:48 rassmann - * Corrected reading of physical addresses. - * - * Revision 1.17 1998/10/28 10:26:13 rassmann - * Getting ports' current MAC addresses from EPROM now. - * Added debug output. - * - * Revision 1.16 1998/10/27 16:20:12 rassmann - * Reading MAC address byte by byte. - * - * Revision 1.15 1998/10/22 11:39:09 rassmann - * Corrected signed/unsigned mismatches. - * - * Revision 1.14 1998/10/19 17:12:35 rassmann - * Syntax corrections. - * - * Revision 1.13 1998/10/19 17:02:19 rassmann - * Now reading permanent MAC addresses from CRF. - * - * Revision 1.12 1998/10/15 15:15:48 rassmann - * Changed Flags Parameters from SK_U8 to int. - * Checked with lint. - * - * Revision 1.11 1998/09/24 19:15:12 rassmann - * Code cleanup. - * - * Revision 1.10 1998/09/18 20:18:54 rassmann - * Added HW access. - * Implemented swapping. - * - * Revision 1.9 1998/09/16 11:32:00 rassmann - * Including skdrv1st.h again. :( - * - * Revision 1.8 1998/09/16 11:09:34 rassmann - * Syntax corrections. - * - * Revision 1.7 1998/09/14 17:06:34 rassmann - * Minor changes. - * - * Revision 1.6 1998/09/07 08:45:41 rassmann - * Syntax corrections. - * - * Revision 1.5 1998/09/04 19:40:19 rassmann - * Interface enhancements. - * - * Revision 1.4 1998/09/04 12:14:12 rassmann - * Interface cleanup. - * - * Revision 1.3 1998/09/02 16:56:40 rassmann - * Updated interface. - * - * Revision 1.2 1998/08/27 14:26:09 rassmann - * Updated interface. - * - * Revision 1.1 1998/08/21 08:30:22 rassmann - * First public version. + * /LICENSE * ******************************************************************************/ @@ -219,18 +45,17 @@ ******************************************************************************/ #include - + #ifdef CONFIG_SK98 -#ifndef lint +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) static const char SysKonnectFileId[] = - "@(#) $Id: skaddr.c,v 1.48 2003/02/12 17:09:37 tschilli Exp $ (C) SysKonnect."; -#endif /* !defined(lint) */ + "@(#) $Id: skaddr.c,v 2.9 2005/12/14 16:11:44 ibrueder Exp $ (C) Marvell."; +#endif /* DEBUG ||!LINT || !SK_SLIM */ #define __SKADDR_C #ifdef __cplusplus -#error C++ is not yet supported. extern "C" { #endif /* cplusplus */ @@ -239,11 +64,10 @@ extern "C" { /* defines ********************************************************************/ - #define XMAC_POLY 0xEDB88320UL /* CRC32-Poly - XMAC: Little Endian */ #define GMAC_POLY 0x04C11DB7L /* CRC16-Poly - GMAC: Little Endian */ #define HASH_BITS 6 /* #bits in hash */ -#define SK_MC_BIT 0x01 +#define SK_MC_BIT 0x01 /* Error numbers and messages. */ @@ -260,12 +84,12 @@ extern "C" { /* 64-bit hash values with all bits set. */ -SK_U16 OnesHash[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF}; +SK_U16 OnesHash[4] = {0xffff, 0xffff, 0xffff, 0xffff}; /* local variables ************************************************************/ #ifdef DEBUG -static int Next0[SK_MAX_MACS] = {0, 0}; +static int Next0[SK_MAX_MACS] = {0}; #endif /* DEBUG */ /* functions ******************************************************************/ @@ -317,7 +141,7 @@ int Level) /* initialization level */ switch (Level) { case SK_INIT_DATA: - SK_MEMSET((char *) &pAC->Addr, 0, sizeof(SK_ADDR)); + SK_MEMSET((char *)&pAC->Addr, (SK_U8)0, (SK_U16)sizeof(SK_ADDR)); for (i = 0; i < SK_MAX_MACS; i++) { pAPort = &pAC->Addr.Port[i]; @@ -340,9 +164,58 @@ int Level) /* initialization level */ break; case SK_INIT_IO: +#ifdef CONFIG_MARVELL + + /* marvell update the mac address */ + /* we will do this change only if we are prpmc board + and that is only when pci arbiter is disabled */ + + { + extern int mvBoardNameGet(char *pNameBuff); + + static char boardName[30]; + mvBoardNameGet(boardName); + + if ((strcmp(boardName,"DB-88F5181-DDR1-PRPMC") == 0) || + (strcmp(boardName,"DB-88F5181-DDR1-MNG") == 0) || + (strcmp(boardName,"DB-88F5X81-DDR1-MNG") == 0) || + (strcmp(boardName,"DB-88F6183L-BP") == 0) || + (strcmp(boardName,"RD-MV78X00-H3C") == 0) || + (strcmp(boardName,"DB-88F1281-DDR2") == 0)) + { + extern unsigned char yuk_enetaddr[6]; + + int i; + + /* enable write*/ + SK_OUT8(pAC->IoBase, B2_TST_CTRL1, 0x2); + + for (i=0 ; i< 6 ; i++) + { + + SK_OUT8(pAC->IoBase, B2_MAC_1 + i, (SK_U8)yuk_enetaddr[i]); + SK_OUT8(pAC->IoBase, B2_MAC_2 + i, (SK_U8)yuk_enetaddr[i]); + SK_OUT8(pAC->IoBase, B2_MAC_3 + i, (SK_U8)yuk_enetaddr[i]); + + pAC->Addr.Net[0].CurrentMacAddress.a[i] = yuk_enetaddr[i]; + pAC->Addr.Net[0].PermanentMacAddress.a[i] = yuk_enetaddr[i]; + + } + + /* disable write*/ + SK_OUT8(pAC->IoBase, B2_TST_CTRL1, 0x1); + + + } + } + +#endif + +#ifndef SK_NO_RLMT for (i = 0; i < SK_MAX_NETS; i++) { pAC->Addr.Net[i].ActivePort = pAC->Rlmt.Net[i].ActivePort; } +#endif /* !SK_NO_RLMT */ #ifdef xDEBUG for (i = 0; i < SK_MAX_MACS; i++) { if (pAC->Addr.Port[i].NextExactMatchRlmt < @@ -369,11 +242,11 @@ int Level) /* initialization level */ pAC->Addr.Port[pAC->Addr.Net[0].ActivePort].Exact[0] = pAC->Addr.Net[0].CurrentMacAddress; #if SK_MAX_NETS > 1 - /* Set logical MAC address for net 2 to (log | 3). */ + /* Set logical MAC address for net 2 to. */ if (!pAC->Addr.Net[1].CurrentMacAddressSet) { pAC->Addr.Net[1].PermanentMacAddress = pAC->Addr.Net[0].PermanentMacAddress; - pAC->Addr.Net[1].PermanentMacAddress.a[5] |= 3; + pAC->Addr.Net[1].PermanentMacAddress.a[5] += 1; /* Set the current logical MAC address to the permanent one. */ pAC->Addr.Net[1].CurrentMacAddress = pAC->Addr.Net[1].PermanentMacAddress; @@ -391,7 +264,7 @@ int Level) /* initialization level */ pAC->Addr.Net[i].PermanentMacAddress.a[2], pAC->Addr.Net[i].PermanentMacAddress.a[3], pAC->Addr.Net[i].PermanentMacAddress.a[4], - pAC->Addr.Net[i].PermanentMacAddress.a[5])) + pAC->Addr.Net[i].PermanentMacAddress.a[5])); SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, ("Logical MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n", @@ -401,7 +274,7 @@ int Level) /* initialization level */ pAC->Addr.Net[i].CurrentMacAddress.a[2], pAC->Addr.Net[i].CurrentMacAddress.a[3], pAC->Addr.Net[i].CurrentMacAddress.a[4], - pAC->Addr.Net[i].CurrentMacAddress.a[5])) + pAC->Addr.Net[i].CurrentMacAddress.a[5])); } #endif /* DEBUG */ @@ -426,13 +299,16 @@ int Level) /* initialization level */ /* Set port's current physical MAC address. */ OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0]; - - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { XM_OUTADDR(IoC, i, XM_SA, OutAddr); } - else { +#endif /* GENESIS */ +#ifdef YUKON + if (!pAC->GIni.GIGenesis) { GM_OUTADDR(IoC, i, GM_SRC_ADDR_1L, OutAddr); } +#endif /* YUKON */ #ifdef DEBUG SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, ("SkAddrInit: Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", @@ -441,7 +317,7 @@ int Level) /* initialization level */ pAPort->PermanentMacAddress.a[2], pAPort->PermanentMacAddress.a[3], pAPort->PermanentMacAddress.a[4], - pAPort->PermanentMacAddress.a[5])) + pAPort->PermanentMacAddress.a[5])); SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, ("SkAddrInit: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", @@ -450,13 +326,62 @@ int Level) /* initialization level */ pAPort->CurrentMacAddress.a[2], pAPort->CurrentMacAddress.a[3], pAPort->CurrentMacAddress.a[4], - pAPort->CurrentMacAddress.a[5])) -#endif /* DEBUG */ + pAPort->CurrentMacAddress.a[5])); +#endif /* DEBUG */ } /* pAC->Addr.InitDone = SK_INIT_IO; */ break; case SK_INIT_RUN: + + #ifdef CONFIG_MARVELL + + /* marvell update the mac address */ + /* we will do this change only if we are prpmc board + and that is only when pci arbiter is disabled */ + + { + extern int mvBoardNameGet(char *pNameBuff); + + static char boardName[30]; + mvBoardNameGet(boardName); + + if ((strcmp(boardName,"DB-88F5181-DDR1-PRPMC") == 0) || + (strcmp(boardName,"DB-88F5181-DDR1-MNG") == 0) || + (strcmp(boardName,"DB-88F5X81-DDR1-MNG") == 0) || + (strcmp(boardName,"DB-88F6183L-BP") == 0) || + (strcmp(boardName,"RD-MV78X00-H3C") == 0) || + (strcmp(boardName,"DB-88F1281-DDR2") == 0)) + { + extern unsigned char yuk_enetaddr[6]; + + int i; + + /* enable write*/ + SK_OUT8(pAC->IoBase, B2_TST_CTRL1, 0x2); + + for (i=0 ; i< 6 ; i++) + { + + SK_OUT8(pAC->IoBase, B2_MAC_1 + i, (SK_U8)yuk_enetaddr[i]); + SK_OUT8(pAC->IoBase, B2_MAC_2 + i, (SK_U8)yuk_enetaddr[i]); + SK_OUT8(pAC->IoBase, B2_MAC_3 + i, (SK_U8)yuk_enetaddr[i]); + + pAC->Addr.Net[0].CurrentMacAddress.a[i] = yuk_enetaddr[i]; + pAC->Addr.Net[0].PermanentMacAddress.a[i] = yuk_enetaddr[i]; + + } + + /* disable write*/ + SK_OUT8(pAC->IoBase, B2_TST_CTRL1, 0x1); + + + } + } + + + #endif + #ifdef xDEBUG for (i = 0; i < SK_MAX_MACS; i++) { if (pAC->Addr.Port[i].NextExactMatchRlmt < @@ -477,6 +402,7 @@ int Level) /* initialization level */ } /* SkAddrInit */ +#ifndef SK_SLIM /****************************************************************************** * @@ -512,18 +438,25 @@ int Flags) /* permanent/non-perm, sw-only */ return (SK_ADDR_ILLEGAL_PORT); } - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + if (pAC->GIni.GIGenesis) { +#ifdef GENESIS ReturnCode = SkAddrXmacMcClear(pAC, IoC, PortNumber, Flags); +#endif } else { +#ifdef YUKON ReturnCode = SkAddrGmacMcClear(pAC, IoC, PortNumber, Flags); +#endif } return (ReturnCode); } /* SkAddrMcClear */ +#endif /* !SK_SLIM */ +#ifndef SK_SLIM +#ifdef GENESIS /****************************************************************************** * * SkAddrXmacMcClear - clear the multicast table @@ -575,8 +508,11 @@ int Flags) /* permanent/non-perm, sw-only */ return (SK_ADDR_SUCCESS); } /* SkAddrXmacMcClear */ +#endif /* GENESIS */ +#endif /* !SK_SLIM */ - +#ifndef SK_SLIM +#ifdef YUKON /****************************************************************************** * * SkAddrGmacMcClear - clear the multicast table @@ -615,7 +551,7 @@ int Flags) /* permanent/non-perm, sw-only */ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4], pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5], pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6], - pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])) + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])); #endif /* DEBUG */ /* Clear InexactFilter */ @@ -632,7 +568,6 @@ int Flags) /* permanent/non-perm, sw-only */ /* Clear InexactRlmtFilter. */ pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i] = 0; - } } else { /* not permanent => DRV */ @@ -657,7 +592,7 @@ int Flags) /* permanent/non-perm, sw-only */ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4], pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5], pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6], - pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])) + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])); #endif /* DEBUG */ if (!(Flags & SK_MC_SW_ONLY)) { @@ -667,9 +602,10 @@ int Flags) /* permanent/non-perm, sw-only */ return (SK_ADDR_SUCCESS); } /* SkAddrGmacMcClear */ +#endif /* YUKON */ #ifndef SK_ADDR_CHEAT - +#ifdef GENESIS /****************************************************************************** * * SkXmacMcHash - hash multicast address @@ -706,8 +642,9 @@ unsigned char *pMc) /* Multicast address */ return (Crc & ((1 << HASH_BITS) - 1)); } /* SkXmacMcHash */ +#endif /* GENESIS */ - +#ifdef YUKON /****************************************************************************** * * SkGmacMcHash - hash multicast address @@ -765,8 +702,8 @@ unsigned char *pMc) /* Multicast address */ return (Crc & ((1 << HASH_BITS) - 1)); } /* SkGmacMcHash */ - -#endif /* not SK_ADDR_CHEAT */ +#endif /* YUKON */ +#endif /* !SK_ADDR_CHEAT */ /****************************************************************************** * @@ -805,18 +742,22 @@ int Flags) /* permanent/non-permanent */ return (SK_ADDR_ILLEGAL_PORT); } - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + if (pAC->GIni.GIGenesis) { +#ifdef GENESIS ReturnCode = SkAddrXmacMcAdd(pAC, IoC, PortNumber, pMc, Flags); +#endif } else { +#ifdef YUKON ReturnCode = SkAddrGmacMcAdd(pAC, IoC, PortNumber, pMc, Flags); +#endif } return (ReturnCode); } /* SkAddrMcAdd */ - +#ifdef GENESIS /****************************************************************************** * * SkAddrXmacMcAdd - add a multicast address to a port @@ -896,7 +837,7 @@ int Flags) /* permanent/non-permanent */ } else { if (!(pMc->a[0] & SK_MC_BIT)) { - /* Hashing only possible with multicast addresses. */ + /* Hashing only possible with multicast addresses */ return (SK_MC_ILLEGAL_ADDRESS); } #ifndef SK_ADDR_CHEAT @@ -926,8 +867,9 @@ int Flags) /* permanent/non-permanent */ } } /* SkAddrXmacMcAdd */ +#endif /* GENESIS */ - +#ifdef YUKON /****************************************************************************** * * SkAddrGmacMcAdd - add a multicast address to a port @@ -959,7 +901,7 @@ int Flags) /* permanent/non-permanent */ #endif /* !defined(SK_ADDR_CHEAT) */ if (!(pMc->a[0] & SK_MC_BIT)) { - /* Hashing only possible with multicast addresses. */ + /* Hashing only possible with multicast addresses */ return (SK_MC_ILLEGAL_ADDRESS); } @@ -979,6 +921,7 @@ int Flags) /* permanent/non-permanent */ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |= pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i]; } + #ifdef DEBUG SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, ("GMAC InexactRlmtFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n", @@ -989,7 +932,7 @@ int Flags) /* permanent/non-permanent */ pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[4], pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[5], pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[6], - pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7])) + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7])); #endif /* DEBUG */ } else { /* not permanent => DRV */ @@ -1003,6 +946,7 @@ int Flags) /* permanent/non-permanent */ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |= pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i]; } + #ifdef DEBUG SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, ("GMAC InexactDrvFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n", @@ -1013,7 +957,7 @@ int Flags) /* permanent/non-permanent */ pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[4], pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[5], pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[6], - pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7])) + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7])); #endif /* DEBUG */ } @@ -1028,7 +972,8 @@ int Flags) /* permanent/non-permanent */ return (SK_MC_FILTERING_INEXACT); } /* SkAddrGmacMcAdd */ - +#endif /* YUKON */ +#endif /* !SK_SLIM */ /****************************************************************************** * @@ -1059,24 +1004,31 @@ SK_AC *pAC, /* adapter context */ SK_IOC IoC, /* I/O context */ SK_U32 PortNumber) /* Port Number */ { - int ReturnCode; + int ReturnCode = SK_ADDR_ILLEGAL_PORT; +#if (!defined(SK_SLIM) || defined(DEBUG)) if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { return (SK_ADDR_ILLEGAL_PORT); } +#endif /* !SK_SLIM || DEBUG */ - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { ReturnCode = SkAddrXmacMcUpdate(pAC, IoC, PortNumber); } - else { +#endif /* GENESIS */ +#ifdef YUKON + if (!pAC->GIni.GIGenesis) { ReturnCode = SkAddrGmacMcUpdate(pAC, IoC, PortNumber); } - +#endif /* YUKON */ return (ReturnCode); } /* SkAddrMcUpdate */ +#ifdef GENESIS + /****************************************************************************** * * SkAddrXmacMcUpdate - update the HW MC address table and set the MAC address @@ -1109,14 +1061,14 @@ SK_U32 PortNumber) /* Port Number */ SK_ADDR_PORT *pAPort; SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, - ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber)) + ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber)); pAPort = &pAC->Addr.Port[PortNumber]; #ifdef DEBUG SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, - ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])) -#endif /* DEBUG */ + ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])); +#endif /* DEBUG */ /* Start with 0 to also program the logical MAC address. */ for (i = 0; i < pAPort->NextExactMatchRlmt; i++) { @@ -1154,7 +1106,7 @@ SK_U32 PortNumber) /* Port Number */ XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash); /* Enable Hashing */ - SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE); } else if (Inexact != 0) { @@ -1162,11 +1114,11 @@ SK_U32 PortNumber) /* Port Number */ XM_OUTHASH(IoC, PortNumber, XM_HSM, &pAPort->InexactFilter.Bytes[0]); /* Enable Hashing */ - SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE); } else { /* Disable Hashing */ - SkMacHashing(pAC, IoC, PortNumber, SK_FALSE); + SkMacHashing(pAC, IoC, (int) PortNumber, SK_FALSE); } if (pAPort->PromMode != SK_PROM_MODE_NONE) { @@ -1204,9 +1156,9 @@ SK_U32 PortNumber) /* Port Number */ pAPort->Exact[i].a[2], pAPort->Exact[i].a[3], pAPort->Exact[i].a[4], - pAPort->Exact[i].a[5])) + pAPort->Exact[i].a[5])); } -#endif /* DEBUG */ +#endif /* DEBUG */ /* Determine return value. */ if (Inexact == 0 && pAPort->PromMode == 0) { @@ -1218,6 +1170,9 @@ SK_U32 PortNumber) /* Port Number */ } /* SkAddrXmacMcUpdate */ +#endif /* GENESIS */ + +#ifdef YUKON /****************************************************************************** * @@ -1245,21 +1200,24 @@ SK_AC *pAC, /* adapter context */ SK_IOC IoC, /* I/O context */ SK_U32 PortNumber) /* Port Number */ { +#ifndef SK_SLIM SK_U32 i; SK_U8 Inexact; +#endif /* not SK_SLIM */ SK_U16 *OutAddr; SK_ADDR_PORT *pAPort; SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, - ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber)) + ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber)); pAPort = &pAC->Addr.Port[PortNumber]; #ifdef DEBUG SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, - ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])) -#endif /* DEBUG */ + ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])); +#endif /* DEBUG */ +#ifndef SK_SLIM for (Inexact = 0, i = 0; i < 8; i++) { Inexact |= pAPort->InexactFilter.Bytes[i]; } @@ -1274,16 +1232,27 @@ SK_U32 PortNumber) /* Port Number */ GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash); /* Enable Hashing */ - SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE); } else { /* Enable Hashing. */ - SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE); } if (pAPort->PromMode != SK_PROM_MODE_NONE) { (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode); } +#else /* SK_SLIM */ + + /* Set all bits in 64-bit hash register. */ + GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE); + + (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode); + +#endif /* SK_SLIM */ /* Set port's current physical MAC address. */ OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0]; @@ -1301,7 +1270,7 @@ SK_U32 PortNumber) /* Port Number */ pAPort->Exact[0].a[2], pAPort->Exact[0].a[3], pAPort->Exact[0].a[4], - pAPort->Exact[0].a[5])) + pAPort->Exact[0].a[5])); SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, ("SkAddrGmacMcUpdate: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", @@ -1310,9 +1279,10 @@ SK_U32 PortNumber) /* Port Number */ pAPort->CurrentMacAddress.a[2], pAPort->CurrentMacAddress.a[3], pAPort->CurrentMacAddress.a[4], - pAPort->CurrentMacAddress.a[5])) -#endif /* DEBUG */ + pAPort->CurrentMacAddress.a[5])); +#endif /* DEBUG */ +#ifndef SK_SLIM /* Determine return value. */ if (Inexact == 0 && pAPort->PromMode == 0) { return (SK_MC_FILTERING_EXACT); @@ -1320,9 +1290,15 @@ SK_U32 PortNumber) /* Port Number */ else { return (SK_MC_FILTERING_INEXACT); } +#else /* SK_SLIM */ + return (SK_MC_FILTERING_INEXACT); +#endif /* SK_SLIM */ } /* SkAddrGmacMcUpdate */ +#endif /* YUKON */ + +#ifndef SK_NO_MAO /****************************************************************************** * @@ -1342,23 +1318,29 @@ SK_U32 PortNumber) /* Port Number */ * SK_ADDR_TOO_EARLY if SK_INIT_IO was not executed before. */ int SkAddrOverride( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* I/O context */ -SK_U32 PortNumber, /* Port Number */ -SK_MAC_ADDR *pNewAddr, /* new MAC address */ -int Flags) /* logical/physical MAC address */ +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Port Number */ +SK_MAC_ADDR SK_FAR *pNewAddr, /* new MAC address */ +int Flags) /* logical/physical MAC address */ { +#ifndef SK_NO_RLMT SK_EVPARA Para; +#endif /* !SK_NO_RLMT */ SK_U32 NetNumber; SK_U32 i; - SK_U16 *OutAddr; + SK_U16 SK_FAR *OutAddr; +#ifndef SK_NO_RLMT NetNumber = pAC->Rlmt.Port[PortNumber].Net->NetNumber; - +#else + NetNumber = 0; +#endif /* SK_NO_RLMT */ +#if (!defined(SK_SLIM) || defined(DEBUG)) if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { return (SK_ADDR_ILLEGAL_PORT); } - +#endif /* !SK_SLIM || DEBUG */ if (pNewAddr != NULL && (pNewAddr->a[0] & SK_MC_BIT) != 0) { return (SK_ADDR_MULTICAST_ADDRESS); } @@ -1374,11 +1356,11 @@ int Flags) /* logical/physical MAC address */ return (SK_ADDR_TOO_EARLY); } } - +#ifndef SK_NO_RLMT /* Set PortNumber to number of net's active port. */ PortNumber = pAC->Rlmt.Net[NetNumber]. Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber; - +#endif /* !SK_NO_RLMT */ pAC->Addr.Port[PortNumber].Exact[0] = pAC->Addr.Net[NetNumber].CurrentMacAddress; @@ -1393,11 +1375,11 @@ int Flags) /* logical/physical MAC address */ return (SK_ADDR_TOO_EARLY); } } - +#ifndef SK_NO_RLMT /* Set PortNumber to number of net's active port. */ PortNumber = pAC->Rlmt.Net[NetNumber]. Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber; - +#endif /* !SK_NO_RLMT */ for (i = 0; i < SK_MAC_ADDR_LEN; i++ ) { pAC->Addr.Port[PortNumber].Exact[0].a[i] = 0; } @@ -1406,45 +1388,70 @@ int Flags) /* logical/physical MAC address */ (void) SkAddrMcUpdate(pAC, IoC, PortNumber); } else if (Flags & SK_ADDR_PHYSICAL_ADDRESS) { /* Physical MAC address. */ - if (SK_ADDR_EQUAL(pNewAddr->a, - pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) { - return (SK_ADDR_DUPLICATE_ADDRESS); - } - for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { if (!pAC->Addr.Port[i].CurrentMacAddressSet) { return (SK_ADDR_TOO_EARLY); } + } + /* + * In dual net mode it should be possible to set all MAC + * addresses independently. Therefore the equality checks + * against the locical address of the same port and the + * physical address of the other port are suppressed here. + */ +#ifndef SK_NO_RLMT + if (pAC->Rlmt.NumNets == 1) { +#endif /* SK_NO_RLMT */ if (SK_ADDR_EQUAL(pNewAddr->a, - pAC->Addr.Port[i].CurrentMacAddress.a)) { - if (i == PortNumber) { - return (SK_ADDR_SUCCESS); - } - else { - return (SK_ADDR_DUPLICATE_ADDRESS); + pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) { + return (SK_ADDR_DUPLICATE_ADDRESS); + } + + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + if (SK_ADDR_EQUAL(pNewAddr->a, + pAC->Addr.Port[i].CurrentMacAddress.a)) { + if (i == PortNumber) { + return (SK_ADDR_SUCCESS); + } + else { + return (SK_ADDR_DUPLICATE_ADDRESS); + } } } +#ifndef SK_NO_RLMT } + else { + if (SK_ADDR_EQUAL(pNewAddr->a, + pAC->Addr.Port[PortNumber].CurrentMacAddress.a)) { + return (SK_ADDR_SUCCESS); + } + } +#endif /* SK_NO_RLMT */ pAC->Addr.Port[PortNumber].PreviousMacAddress = pAC->Addr.Port[PortNumber].CurrentMacAddress; pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr; /* Change port's physical MAC address. */ - OutAddr = (SK_U16 *) pNewAddr; - - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + OutAddr = (SK_U16 SK_FAR *) pNewAddr; +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr); } - else { +#endif /* GENESIS */ +#ifdef YUKON + if (!pAC->GIni.GIGenesis) { GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr); } +#endif /* YUKON */ +#ifndef SK_NO_RLMT /* Report address change to RLMT. */ Para.Para32[0] = PortNumber; Para.Para32[0] = -1; SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para); +#endif /* !SK_NO_RLMT */ } else { /* Logical MAC address. */ if (SK_ADDR_EQUAL(pNewAddr->a, @@ -1456,13 +1463,27 @@ int Flags) /* logical/physical MAC address */ if (!pAC->Addr.Port[i].CurrentMacAddressSet) { return (SK_ADDR_TOO_EARLY); } - - if (SK_ADDR_EQUAL(pNewAddr->a, - pAC->Addr.Port[i].CurrentMacAddress.a)) { - return (SK_ADDR_DUPLICATE_ADDRESS); - } } + /* + * In dual net mode on Yukon-2 adapters the physical address + * of port 0 and the logical address of port 1 are equal - in + * this case the equality check of the physical address leads + * to an error and is suppressed here. + */ +#ifndef SK_NO_RLMT + if (pAC->Rlmt.NumNets == 1) { +#endif /* SK_NO_RLMT */ + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + if (SK_ADDR_EQUAL(pNewAddr->a, + pAC->Addr.Port[i].CurrentMacAddress.a)) { + return (SK_ADDR_DUPLICATE_ADDRESS); + } + } +#ifndef SK_NO_RLMT + } +#endif /* SK_NO_RLMT */ + /* * In case that the physical and the logical MAC addresses are equal * we must also change the physical MAC address here. @@ -1476,16 +1497,19 @@ int Flags) /* logical/physical MAC address */ pAC->Addr.Port[PortNumber].CurrentMacAddress; pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr; +#ifndef SK_NO_RLMT /* Report address change to RLMT. */ Para.Para32[0] = PortNumber; Para.Para32[0] = -1; SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para); +#endif /* !SK_NO_RLMT */ } +#ifndef SK_NO_RLMT /* Set PortNumber to number of net's active port. */ PortNumber = pAC->Rlmt.Net[NetNumber]. Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber; - +#endif /* !SK_NO_RLMT */ pAC->Addr.Net[NetNumber].CurrentMacAddress = *pNewAddr; pAC->Addr.Port[PortNumber].Exact[0] = *pNewAddr; #ifdef DEBUG @@ -1496,7 +1520,7 @@ int Flags) /* logical/physical MAC address */ pAC->Addr.Net[NetNumber].PermanentMacAddress.a[2], pAC->Addr.Net[NetNumber].PermanentMacAddress.a[3], pAC->Addr.Net[NetNumber].PermanentMacAddress.a[4], - pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5])) + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5])); SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, ("SkAddrOverride: New logical MAC Address: %02X %02X %02X %02X %02X %02X\n", @@ -1505,17 +1529,18 @@ int Flags) /* logical/physical MAC address */ pAC->Addr.Net[NetNumber].CurrentMacAddress.a[2], pAC->Addr.Net[NetNumber].CurrentMacAddress.a[3], pAC->Addr.Net[NetNumber].CurrentMacAddress.a[4], - pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5])) -#endif /* DEBUG */ + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5])); +#endif /* DEBUG */ - /* Write address to first exact match entry of active port. */ - (void) SkAddrMcUpdate(pAC, IoC, PortNumber); + /* Write address to first exact match entry of active port. */ + (void)SkAddrMcUpdate(pAC, IoC, PortNumber); } return (SK_ADDR_SUCCESS); } /* SkAddrOverride */ +#endif /* SK_NO_MAO */ /****************************************************************************** * @@ -1545,23 +1570,32 @@ SK_IOC IoC, /* I/O context */ SK_U32 PortNumber, /* port whose promiscuous mode changes */ int NewPromMode) /* new promiscuous mode */ { - int ReturnCode; + int ReturnCode = SK_ADDR_ILLEGAL_PORT; +#if (!defined(SK_SLIM) || defined(DEBUG)) if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { return (SK_ADDR_ILLEGAL_PORT); } +#endif /* !SK_SLIM || DEBUG */ - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { - ReturnCode = SkAddrXmacPromiscuousChange(pAC, IoC, PortNumber, NewPromMode); +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { + ReturnCode = + SkAddrXmacPromiscuousChange(pAC, IoC, PortNumber, NewPromMode); } - else { - ReturnCode = SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, NewPromMode); +#endif /* GENESIS */ +#ifdef YUKON + if (!pAC->GIni.GIGenesis) { + ReturnCode = + SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, NewPromMode); } +#endif /* YUKON */ return (ReturnCode); } /* SkAddrPromiscuousChange */ +#ifdef GENESIS /****************************************************************************** * @@ -1606,6 +1640,7 @@ int NewPromMode) /* new promiscuous mode */ for (Inexact = 0xFF, i = 0; i < 8; i++) { Inexact &= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i]; } + if (Inexact == 0xFF) { CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC); } @@ -1640,7 +1675,7 @@ int NewPromMode) /* new promiscuous mode */ XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash); /* Enable Hashing */ - SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE); } else if ((CurPromMode & SK_PROM_MODE_ALL_MC) && !(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm MC. */ @@ -1649,7 +1684,7 @@ int NewPromMode) /* new promiscuous mode */ } if (Inexact == 0) { /* Disable Hashing */ - SkMacHashing(pAC, IoC, PortNumber, SK_FALSE); + SkMacHashing(pAC, IoC, (int) PortNumber, SK_FALSE); } else { /* Set 64-bit hash register to InexactFilter. */ @@ -1657,25 +1692,28 @@ int NewPromMode) /* new promiscuous mode */ &pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0]); /* Enable Hashing */ - SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE); } } if ((NewPromMode & SK_PROM_MODE_LLC) && !(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */ /* Set the MAC in Promiscuous Mode */ - SkMacPromiscMode(pAC, IoC, PortNumber, SK_TRUE); + SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_TRUE); } else if ((CurPromMode & SK_PROM_MODE_LLC) && !(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC. */ /* Clear Promiscuous Mode */ - SkMacPromiscMode(pAC, IoC, PortNumber, SK_FALSE); + SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE); } return (SK_ADDR_SUCCESS); } /* SkAddrXmacPromiscuousChange */ +#endif /* GENESIS */ + +#ifdef YUKON /****************************************************************************** * @@ -1717,6 +1755,9 @@ int NewPromMode) /* new promiscuous mode */ CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC); } + /* dummy read after GM_IN16() */ + SK_IN16(IoC, B0_RAP, &ReceiveControl); + pAC->Addr.Port[PortNumber].PromMode = NewPromMode; if (NewPromMode == CurPromMode) { @@ -1730,7 +1771,7 @@ int NewPromMode) /* new promiscuous mode */ GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash); /* Enable Hashing */ - SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE); } if ((CurPromMode & SK_PROM_MODE_ALL_MC) && @@ -1741,26 +1782,29 @@ int NewPromMode) /* new promiscuous mode */ &pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0]); /* Enable Hashing. */ - SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE); } if ((NewPromMode & SK_PROM_MODE_LLC) && !(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */ /* Set the MAC to Promiscuous Mode. */ - SkMacPromiscMode(pAC, IoC, PortNumber, SK_TRUE); + SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_TRUE); } else if ((CurPromMode & SK_PROM_MODE_LLC) && !(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC */ /* Clear Promiscuous Mode. */ - SkMacPromiscMode(pAC, IoC, PortNumber, SK_FALSE); + SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE); } return (SK_ADDR_SUCCESS); } /* SkAddrGmacPromiscuousChange */ +#endif /* YUKON */ + +#ifndef SK_SLIM /****************************************************************************** * @@ -1832,7 +1876,7 @@ SK_U32 ToPortNumber) /* Port2 Index */ pAC->Addr.Port[FromPortNumber].PromMode = pAC->Addr.Port[ToPortNumber].PromMode; pAC->Addr.Port[ToPortNumber].PromMode = i; - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + if (pAC->GIni.GIGenesis) { DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt; pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt = pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt; @@ -1872,8 +1916,10 @@ SK_U32 ToPortNumber) /* Port2 Index */ } /* SkAddrSwap */ +#endif /* !SK_SLIM */ + #ifdef __cplusplus } #endif /* __cplusplus */ -#endif /* CONFIG_SK98 */ +#endif diff --git a/drivers/sk98lin/skcsum.c b/drivers/sk98lin/skcsum.c index a5dc572..26716bf 100644 --- a/drivers/sk98lin/skcsum.c +++ b/drivers/sk98lin/skcsum.c @@ -2,15 +2,16 @@ * * Name: skcsum.c * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.10 $ - * Date: $Date: 2002/04/11 10:02:04 $ + * Version: $Revision: 2.2 $ + * Date: $Date: 2005/12/14 16:11:26 $ * Purpose: Store/verify Internet checksum in send/receive packets. * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2001 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2003 SysKonnect GmbH. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,68 +19,19 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. + * /LICENSE * ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: skcsum.c,v $ - * Revision 1.10 2002/04/11 10:02:04 rwahl - * Fix in SkCsGetSendInfo(): - * - function did not return ProtocolFlags in every case. - * - pseudo header csum calculated wrong for big endian. - * - * Revision 1.9 2001/06/13 07:42:08 gklug - * fix: NetNumber was wrong in CLEAR_STAT event - * add: check for good NetNumber in Clear STAT - * - * Revision 1.8 2001/02/06 11:15:36 rassmann - * Supporting two nets on dual-port adapters. - * - * Revision 1.7 2000/06/29 13:17:05 rassmann - * Corrected reception of a packet with UDP checksum == 0 (which means there - * is no UDP checksum). - * - * Revision 1.6 2000/02/21 12:35:10 cgoos - * Fixed license header comment. - * - * Revision 1.5 2000/02/21 11:05:19 cgoos - * Merged changes back to common source. - * Fixed rx path for BIG ENDIAN architecture. - * - * Revision 1.1 1999/07/26 15:28:12 mkarl - * added return SKCS_STATUS_IP_CSUM_ERROR_UDP and - * SKCS_STATUS_IP_CSUM_ERROR_TCP to pass the NidsTester - * changed from common source to windows specific source - * therefore restarting with v1.0 - * - * Revision 1.3 1999/05/10 08:39:33 mkarl - * prevent overflows in SKCS_HTON16 - * fixed a bug in pseudo header checksum calculation - * added some comments - * - * Revision 1.2 1998/10/22 11:53:28 swolf - * Now using SK_DBG_MSG. - * - * Revision 1.1 1998/09/01 15:35:41 swolf - * initial revision - * - * 13-May-1998 sw Created. - * - ******************************************************************************/ - #include - + #ifdef CONFIG_SK98 + #ifdef SK_USE_CSUM /* Check if CSUM is to be used. */ #ifndef lint -static const char SysKonnectFileId[] = "@(#)" - "$Id: skcsum.c,v 1.10 2002/04/11 10:02:04 rwahl Exp $" - " (C) SysKonnect."; +static const char SysKonnectFileId[] = + "@(#) $Id: skcsum.c,v 2.2 2005/12/14 16:11:26 ibrueder Exp $ (C) SysKonnect."; #endif /* !lint */ /****************************************************************************** @@ -111,8 +63,8 @@ static const char SysKonnectFileId[] = "@(#)" * * "h/skdrv1st.h" * "h/skcsum.h" - * "h/sktypes.h" - * "h/skqueue.h" + * "h/sktypes.h" + * "h/skqueue.h" * "h/skdrv2nd.h" * ******************************************************************************/ @@ -177,7 +129,7 @@ static const char SysKonnectFileId[] = "@(#)" * little/big endian conversion on little endian machines only. */ #ifdef SK_LITTLE_ENDIAN -#define SKCS_HTON16(Val16) (((unsigned) (Val16) >> 8) | (((Val16) & 0xFF) << 8)) +#define SKCS_HTON16(Val16) (((unsigned) (Val16) >> 8) | (((Val16) & 0xff) << 8)) #endif /* SK_LITTLE_ENDIAN */ #ifdef SK_BIG_ENDIAN #define SKCS_HTON16(Val16) (Val16) @@ -208,7 +160,7 @@ static const char SysKonnectFileId[] = "@(#)" * zero.) * * Note: - * There is a bug in the ASIC which may lead to wrong checksums. + * There is a bug in the GENESIS ASIC which may lead to wrong checksums. * * Arguments: * pAc - A pointer to the adapter context struct. @@ -261,7 +213,6 @@ static const char SysKonnectFileId[] = "@(#)" * has been specified in the 'ProtocolFlags', the 16-bit Internet Checksum * of the TCP or UDP pseudo header is returned here. */ -#if 0 void SkCsGetSendInfo( SK_AC *pAc, /* Adapter context struct. */ void *pIpHeader, /* IP header. */ @@ -427,7 +378,7 @@ int NetNumber) /* Net number */ SKCS_OFS_IP_DESTINATION_ADDRESS + 2) + (unsigned long) SKCS_HTON16(NextLevelProtocol) + (unsigned long) SKCS_HTON16(IpDataLength); - + /* Add-in any carries. */ SKCS_OC_ADD(PseudoHeaderChecksum, PseudoHeaderChecksum, 0); @@ -602,13 +553,13 @@ int NetNumber) /* Net number */ * us to check upper-layer checksums, because we cannot do any further * processing of the packet without a valid IP checksum. */ - + /* Get the next level protocol identifier. */ - + NextLevelProtocol = *(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL); - if (IpHeaderChecksum != 0xFFFF) { + if (IpHeaderChecksum != 0xffff) { pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++; /* the NDIS tester wants to know the upper level protocol too */ if (NextLevelProtocol == SKCS_PROTO_ID_TCP) { @@ -680,7 +631,7 @@ int NetNumber) /* Net number */ *(SK_U16*)SKCS_IDX(pIpHeader, IpHeaderLength + 6) == 0x0000) { NextLevelProtoStats->RxOkCts++; - + return (SKCS_STATUS_IP_CSUM_OK_NO_UDP); } @@ -726,7 +677,7 @@ int NetNumber) /* Net number */ /* Check if the TCP/UDP checksum is ok. */ - if ((unsigned) NextLevelProtocolChecksum == 0xFFFF) { + if ((unsigned) NextLevelProtocolChecksum == 0xffff) { /* TCP/UDP checksum ok. */ @@ -735,7 +686,7 @@ int NetNumber) /* Net number */ return (NextLevelProtocol == SKCS_PROTO_ID_TCP ? SKCS_STATUS_TCP_CSUM_OK : SKCS_STATUS_UDP_CSUM_OK); } - + /* TCP/UDP checksum error. */ NextLevelProtoStats->RxErrCts++; @@ -743,7 +694,6 @@ int NetNumber) /* Net number */ return (NextLevelProtocol == SKCS_PROTO_ID_TCP ? SKCS_STATUS_TCP_CSUM_ERROR : SKCS_STATUS_UDP_CSUM_ERROR); } /* SkCsGetReceiveInfo */ -#endif /****************************************************************************** @@ -794,7 +744,7 @@ int NetNumber) *pChecksum2Offset = SKCS_MAC_HEADER_SIZE + SKCS_IP_HEADER_SIZE; } /* SkCsSetReceiveFlags */ -#ifndef SkCsCalculateChecksum +#ifndef SK_CS_CALCULATE_CHECKSUM /****************************************************************************** * @@ -859,7 +809,7 @@ unsigned Length) /* Length of data. */ return ((unsigned) Checksum); } /* SkCsCalculateChecksum */ -#endif /* SkCsCalculateChecksum */ +#endif /* SK_CS_CALCULATE_CHECKSUM */ /****************************************************************************** * @@ -909,12 +859,12 @@ SK_EVPARA Param) /* Event dependent parameter. */ NetNumber = (int)Param.Para32[0]; if (ProtoIndex < 0) { /* Clear for all protocols. */ if (NetNumber >= 0) { - memset(&pAc->Csum.ProtoStats[NetNumber][0], 0, + SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][0], 0, sizeof(pAc->Csum.ProtoStats[NetNumber])); } } else { /* Clear for individual protocol. */ - memset(&pAc->Csum.ProtoStats[NetNumber][ProtoIndex], 0, + SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][ProtoIndex], 0, sizeof(pAc->Csum.ProtoStats[NetNumber][ProtoIndex])); } break; @@ -926,4 +876,4 @@ SK_EVPARA Param) /* Event dependent parameter. */ #endif /* SK_USE_CSUM */ -#endif /* CONFIG_SK98 */ +#endif diff --git a/drivers/sk98lin/skdim.c b/drivers/sk98lin/skdim.c new file mode 100644 index 0000000..545bf73 --- /dev/null +++ b/drivers/sk98lin/skdim.c @@ -0,0 +1,400 @@ +/****************************************************************************** + * + * Name: skdim.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.5.2.2 $ + * Date: $Date: 2005/05/23 13:47:33 $ + * Purpose: All functions regardig interrupt moderation + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2005 Marvell. + * + * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet + * Server Adapters. + * + * Author: Ralph Roesler (rroesler@syskonnect.de) + * Mirko Lindner (mlindner@syskonnect.de) + * + * Address all question to: linux@syskonnect.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + *****************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + +/****************************************************************************** + * + * Local Function Prototypes + * + *****************************************************************************/ + +static SK_U64 getIsrCalls(SK_AC *pAC); +static SK_BOOL isIntModEnabled(SK_AC *pAC); +static void setCurrIntCtr(SK_AC *pAC); +static void enableIntMod(SK_AC *pAC); +static void disableIntMod(SK_AC *pAC); + +#define M_DIMINFO pAC->DynIrqModInfo + +/****************************************************************************** + * + * Global Functions + * + *****************************************************************************/ + +/***************************************************************************** + * + * SkDimModerate - Moderates the IRQs depending on the current needs + * + * Description: + * Moderation of IRQs depends on the number of occurred IRQs with + * respect to the previous moderation cycle. + * + * Returns: N/A + * + */ +void SkDimModerate( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_U64 IsrCalls = getIsrCalls(pAC); + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> SkDimModerate\n")); + + if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) { + if (isIntModEnabled(pAC)) { + if (IsrCalls < M_DIMINFO.MaxModIntsPerSecLowerLimit) { + disableIntMod(pAC); + } + } else { + if (IsrCalls > M_DIMINFO.MaxModIntsPerSecUpperLimit) { + enableIntMod(pAC); + } + } + } + setCurrIntCtr(pAC); + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== SkDimModerate\n")); +} + +/***************************************************************************** + * + * SkDimStartModerationTimer - Starts the moderation timer + * + * Description: + * Dynamic interrupt moderation is regularly checked using the + * so-called moderation timer. This timer is started with this function. + * + * Returns: N/A + */ +void SkDimStartModerationTimer( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_EVPARA EventParam; /* Event struct for timer event */ + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("==> SkDimStartModerationTimer\n")); + + if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) { + SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam)); + EventParam.Para32[0] = SK_DRV_MODERATION_TIMER; + SkTimerStart(pAC, pAC->IoBase, + &pAC->DynIrqModInfo.ModTimer, + pAC->DynIrqModInfo.DynIrqModSampleInterval * 1000000, + SKGE_DRV, SK_DRV_TIMER, EventParam); + } + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== SkDimStartModerationTimer\n")); +} + +/***************************************************************************** + * + * SkDimEnableModerationIfNeeded - Enables or disables any moderationtype + * + * Description: + * This function effectively initializes the IRQ moderation of a network + * adapter. Depending on the configuration, this might be either static + * or dynamic. If no moderation is configured, this function will do + * nothing. + * + * Returns: N/A + */ +void SkDimEnableModerationIfNeeded( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("==> SkDimEnableModerationIfNeeded\n")); + + if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) { + if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) { + enableIntMod(pAC); + } else { /* must be C_INT_MOD_DYNAMIC */ + SkDimStartModerationTimer(pAC); + } + } + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== SkDimEnableModerationIfNeeded\n")); +} + +/***************************************************************************** + * + * SkDimDisableModeration - disables moderation if it is enabled + * + * Description: + * Disabling of the moderation requires that is enabled already. + * + * Returns: N/A + */ +void SkDimDisableModeration( +SK_AC *pAC, /* pointer to adapter control context */ +int CurrentModeration) /* type of current moderation */ +{ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("==> SkDimDisableModeration\n")); + + if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) { + if (CurrentModeration == C_INT_MOD_STATIC) { + disableIntMod(pAC); + } else { /* must be C_INT_MOD_DYNAMIC */ + SkTimerStop(pAC, pAC->IoBase, &M_DIMINFO.ModTimer); + disableIntMod(pAC); + } + } + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== SkDimDisableModeration\n")); +} + +/****************************************************************************** + * + * Local Functions + * + *****************************************************************************/ + +/***************************************************************************** + * + * getIsrCalls - evaluate the number of IRQs handled in mod interval + * + * Description: + * Depending on the selected moderation mask, this function will return + * the number of interrupts handled in the previous moderation interval. + * This evaluated number is based on the current number of interrupts + * stored in PNMI-context and the previous stored interrupts. + * + * Returns: + * the number of IRQs handled + */ +static SK_U64 getIsrCalls( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_U64 RxPort0IntDiff = 0, RxPort1IntDiff = 0; + SK_U64 TxPort0IntDiff = 0, TxPort1IntDiff = 0; + SK_U64 StatusPort0IntDiff = 0, StatusPort1IntDiff = 0; + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>getIsrCalls\n")); + + if (!CHIP_ID_YUKON_2(pAC)) { + if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_TX_ONLY) || + (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_TX)) { + if (pAC->GIni.GIMacsFound == 2) { + TxPort1IntDiff = + pAC->Pnmi.Port[1].TxIntrCts - + M_DIMINFO.PrevPort1TxIntrCts; + } + TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts - + M_DIMINFO.PrevPort0TxIntrCts; + } else if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_RX_ONLY) || + (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_RX)) { + if (pAC->GIni.GIMacsFound == 2) { + RxPort1IntDiff = + pAC->Pnmi.Port[1].RxIntrCts - + M_DIMINFO.PrevPort1RxIntrCts; + } + RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts - + M_DIMINFO.PrevPort0RxIntrCts; + } else { + if (pAC->GIni.GIMacsFound == 2) { + RxPort1IntDiff = + pAC->Pnmi.Port[1].RxIntrCts - + M_DIMINFO.PrevPort1RxIntrCts; + TxPort1IntDiff = + pAC->Pnmi.Port[1].TxIntrCts - + M_DIMINFO.PrevPort1TxIntrCts; + } + RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts - + M_DIMINFO.PrevPort0RxIntrCts; + TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts - + M_DIMINFO.PrevPort0TxIntrCts; + } + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("==>getIsrCalls (!CHIP_ID_YUKON_2)\n")); + return (RxPort0IntDiff + RxPort1IntDiff + + TxPort0IntDiff + TxPort1IntDiff); + } + + /* + ** We have a Yukon2 compliant chipset if we come up to here + ** + if (pAC->GIni.GIMacsFound == 2) { + StatusPort1IntDiff = pAC->Pnmi.Port[1].StatusLeIntrCts - + M_DIMINFO.PrevPort1StatusIntrCts; + } + StatusPort0IntDiff = pAC->Pnmi.Port[0].StatusLeIntrCts - + M_DIMINFO.PrevPort0StatusIntrCts; + */ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("==>getIsrCalls (CHIP_ID_YUKON_2)\n")); + return (StatusPort0IntDiff + StatusPort1IntDiff); +} + +/***************************************************************************** + * + * setCurrIntCtr - stores the current number of interrupts + * + * Description: + * Stores the current number of occurred interrupts in the adapter + * context. This is needed to evaluate the umber of interrupts within + * the moderation interval. + * + * Returns: N/A + * + */ +static void setCurrIntCtr( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>setCurrIntCtr\n")); + + if (!CHIP_ID_YUKON_2(pAC)) { + if (pAC->GIni.GIMacsFound == 2) { + M_DIMINFO.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts; + M_DIMINFO.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts; + } + M_DIMINFO.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts; + M_DIMINFO.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts; + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== setCurrIntCtr (!CHIP_ID_YUKON_2)\n")); + return; + } + + /* + ** We have a Yukon2 compliant chipset if we come up to here + ** + if (pAC->GIni.GIMacsFound == 2) { + M_DIMINFO.PrevPort1StatusIntrCts = pAC->Pnmi.Port[1].StatusLeIntrCts; + } + M_DIMINFO.PrevPort0StatusIntrCts = pAC->Pnmi.Port[0].StatusLeIntrCts; + */ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== setCurrIntCtr (CHIP_ID_YUKON_2)\n")); +} + +/***************************************************************************** + * + * isIntModEnabled - returns the current state of interrupt moderation + * + * Description: + * This function retrieves the current value of the interrupt moderation + * command register. Its content determines whether any moderation is + * running or not. + * + * Returns: + * SK_TRUE : IRQ moderation is currently active + * SK_FALSE: No IRQ moderation is active + */ +static SK_BOOL isIntModEnabled( +SK_AC *pAC) /* pointer to adapter control context */ +{ + unsigned long CtrCmd; + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>isIntModEnabled\n")); + + SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd); + if ((CtrCmd & TIM_START) == TIM_START) { + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== isIntModEnabled (SK_TRUE)\n")); + return SK_TRUE; + } + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG, + ("<== isIntModEnabled (SK_FALSE)\n")); + return SK_FALSE; +} + +/***************************************************************************** + * + * enableIntMod - enables the interrupt moderation + * + * Description: + * Enabling the interrupt moderation is done by putting the desired + * moderation interval in the B2_IRQM_INI register, specifying the + * desired maks in the B2_IRQM_MSK register and finally starting the + * IRQ moderation timer using the B2_IRQM_CTRL register. + * + * Returns: N/A + * + */ +static void enableIntMod( +SK_AC *pAC) /* pointer to adapter control context */ +{ + unsigned long ModBase; + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> enableIntMod\n")); + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + ModBase = C_CLK_FREQ_GENESIS / M_DIMINFO.MaxModIntsPerSec; + } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) { + ModBase = C_CLK_FREQ_YUKON_EC / M_DIMINFO.MaxModIntsPerSec; + } else { + ModBase = C_CLK_FREQ_YUKON / M_DIMINFO.MaxModIntsPerSec; + } + + SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase); + SK_OUT32(pAC->IoBase, B2_IRQM_MSK, M_DIMINFO.MaskIrqModeration); + SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START); + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== enableIntMod\n")); +} + +/***************************************************************************** + * + * disableIntMod - disables the interrupt moderation + * + * Description: + * Disabling the interrupt moderation is done by stopping the + * IRQ moderation timer using the B2_IRQM_CTRL register. + * + * Returns: N/A + * + */ +static void disableIntMod( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> disableIntMod\n")); + + SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP); + + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== disableIntMod\n")); +} + +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ + +#endif diff --git a/drivers/sk98lin/skethtool.c b/drivers/sk98lin/skethtool.c new file mode 100644 index 0000000..9ca3ff0 --- /dev/null +++ b/drivers/sk98lin/skethtool.c @@ -0,0 +1,1364 @@ +/****************************************************************************** + * + * Name: skethtool.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.3.2.11 $ + * Date: $Date: 2005/10/27 12:42:34 $ + * Purpose: All functions regarding ethtool handling + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2005 Marvell. + * + * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet + * Server Adapters. + * + * Author: Ralph Roesler (rroesler@syskonnect.de) + * Mirko Lindner (mlindner@syskonnect.de) + * + * Address all question to: linux@syskonnect.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + *****************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" +#include "h/skversion.h" +#if 0 /* uboot */ +#include +#include +#include +#endif + +/****************************************************************************** + * + * External Functions and Data + * + *****************************************************************************/ + +extern void SkDimDisableModeration(SK_AC *pAC, int CurrentModeration); +extern void SkDimEnableModerationIfNeeded(SK_AC *pAC); + +/****************************************************************************** + * + * Defines + * + *****************************************************************************/ + +#ifndef ETHT_STATSTRING_LEN +#define ETHT_STATSTRING_LEN 32 +#endif + +#define SK98LIN_STAT(m) sizeof(((SK_AC *)0)->m),offsetof(SK_AC, m) + +#define SUPP_COPPER_ALL (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \ + SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \ + SUPPORTED_1000baseT_Half| SUPPORTED_1000baseT_Full| \ + SUPPORTED_TP) + +#define ADV_COPPER_ALL (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ + ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ + ADVERTISED_1000baseT_Half| ADVERTISED_1000baseT_Full| \ + ADVERTISED_TP) + +#define SUPP_FIBRE_ALL (SUPPORTED_1000baseT_Full | \ + SUPPORTED_FIBRE | \ + SUPPORTED_Autoneg) + +#define ADV_FIBRE_ALL (ADVERTISED_1000baseT_Full | \ + ADVERTISED_FIBRE | \ + ADVERTISED_Autoneg) + +/****************************************************************************** + * + * Local Function Prototypes + * + *****************************************************************************/ + +#ifdef ETHTOOL_GSET +static void getSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd); +#endif +#ifdef ETHTOOL_SSET +static int setSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd); +#endif +#ifdef ETHTOOL_GPAUSEPARAM +static void getPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause); +#endif +#ifdef ETHTOOL_SPAUSEPARAM +static int setPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause); +#endif +#ifdef ETHTOOL_GDRVINFO +static void getDriverInfo(SK_AC *pAC, int port, struct ethtool_drvinfo *edrvinfo); +#endif +#ifdef ETHTOOL_PHYS_ID +static int startLocateNIC(SK_AC *pAC, int port, struct ethtool_value *blinkSecs); +static void toggleLeds(unsigned long ptr); +#endif +#ifdef ETHTOOL_GCOALESCE +static void getModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc); +#endif +#ifdef ETHTOOL_SCOALESCE +static int setModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc); +#endif +#ifdef ETHTOOL_GWOL +static void getWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol); +#endif +#ifdef ETHTOOL_SWOL +static int setWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol); +#endif + +static int getPortNumber(struct net_device *netdev, struct ifreq *ifr); + +/****************************************************************************** + * + * Local Variables + * + *****************************************************************************/ + +struct sk98lin_stats { + char stat_string[ETHT_STATSTRING_LEN]; + int sizeof_stat; + int stat_offset; +}; + +static struct sk98lin_stats sk98lin_etht_stats_port0[] = { + { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOkCts) }, + { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOkCts) }, + { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOctetsOkCts) }, + { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOctetsOkCts) }, + { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) }, + { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) }, + { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) }, + { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) }, + { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMulticastOkCts) }, + { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) }, + { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxRuntCts) }, + { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFifoOverflowCts) }, + { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFcsCts) }, + { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFramingCts) }, + { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxShortsCts) }, + { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxTooLongCts) }, + { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCextCts) }, + { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxSymbolCts) }, + { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxIRLengthCts) }, + { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCarrierCts) }, + { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxJabberCts) }, + { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMissedCts) }, + { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) }, + { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) }, + { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxFifoUnderrunCts) }, + { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) } , + { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) } +}; + +static struct sk98lin_stats sk98lin_etht_stats_port1[] = { + { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOkCts) }, + { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOkCts) }, + { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOctetsOkCts) }, + { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOctetsOkCts) }, + { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) }, + { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) }, + { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) }, + { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) }, + { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMulticastOkCts) }, + { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) }, + { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxRuntCts) }, + { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFifoOverflowCts) }, + { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFcsCts) }, + { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFramingCts) }, + { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxShortsCts) }, + { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxTooLongCts) }, + { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCextCts) }, + { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxSymbolCts) }, + { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxIRLengthCts) }, + { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCarrierCts) }, + { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxJabberCts) }, + { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMissedCts) }, + { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) }, + { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) }, + { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxFifoUnderrunCts) }, + { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) } , + { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) } +}; + +#define SK98LIN_STATS_LEN sizeof(sk98lin_etht_stats_port0) / sizeof(struct sk98lin_stats) + +static int nbrBlinkQuarterSeconds; +static int currentPortIndex; +static SK_BOOL isLocateNICrunning = SK_FALSE; +static SK_BOOL isDualNetCard = SK_FALSE; +static SK_BOOL doSwitchLEDsOn = SK_FALSE; +static SK_BOOL boardWasDown[2] = { SK_FALSE, SK_FALSE }; +static struct timer_list locateNICtimer; + +/****************************************************************************** + * + * Global Functions + * + *****************************************************************************/ + +/***************************************************************************** + * + * SkEthIoctl - IOCTL entry point for all ethtool queries + * + * Description: + * Any IOCTL request that has to deal with the ethtool command tool is + * dispatched via this function. + * + * Returns: + * ==0: everything fine, no error + * !=0: the return value is the error code of the failure + */ +int SkEthIoctl( +struct net_device *netdev, /* the pointer to netdev structure */ +struct ifreq *ifr) /* what interface the request refers to? */ +{ + DEV_NET *pNet = (DEV_NET*) netdev->priv; + SK_AC *pAC = pNet->pAC; + void *pAddr = ifr->ifr_data; + int port = getPortNumber(netdev, ifr); + SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct; + SK_U32 Size = sizeof(SK_PNMI_STRUCT_DATA); + SK_U32 cmd; + struct sk98lin_stats *sk98lin_etht_stats = + (port == 0) ? sk98lin_etht_stats_port0 : sk98lin_etht_stats_port1; + + if (get_user(cmd, (uint32_t *) pAddr)) { + return -EFAULT; + } + + switch(cmd) { +#ifdef ETHTOOL_GSET + case ETHTOOL_GSET: { + struct ethtool_cmd ecmd = { ETHTOOL_GSET }; + getSettings(pAC, port, &ecmd); + if(copy_to_user(pAddr, &ecmd, sizeof(ecmd))) { + return -EFAULT; + } + return 0; + } + break; +#endif +#ifdef ETHTOOL_SSET + case ETHTOOL_SSET: { + struct ethtool_cmd ecmd; + if(copy_from_user(&ecmd, pAddr, sizeof(ecmd))) { + return -EFAULT; + } + return setSettings(pAC, port, &ecmd); + } + break; +#endif +#ifdef ETHTOOL_GLINK + case ETHTOOL_GLINK: { + struct ethtool_value edata = { ETHTOOL_GLINK }; + edata.data = netif_carrier_ok(netdev); + if (copy_to_user(pAddr, &edata, sizeof(edata))) + return -EFAULT; + return 0; + } +#endif +#ifdef ETHTOOL_GDRVINFO + case ETHTOOL_GDRVINFO: { + struct ethtool_drvinfo drvinfo = { ETHTOOL_GDRVINFO }; + getDriverInfo(pAC, port, &drvinfo); + if(copy_to_user(pAddr, &drvinfo, sizeof(drvinfo))) { + return -EFAULT; + } + return 0; + } + break; +#endif +#ifdef ETHTOOL_GSTRINGS + case ETHTOOL_GSTRINGS: { + struct ethtool_gstrings gstrings = { ETHTOOL_GSTRINGS }; + char *strings = NULL; + int err = 0; + if(copy_from_user(&gstrings, pAddr, sizeof(gstrings))) { + return -EFAULT; + } + switch(gstrings.string_set) { +#ifdef ETHTOOL_GSTATS + case ETH_SS_STATS: { + int i; + gstrings.len = SK98LIN_STATS_LEN; + if ((strings = kmalloc(SK98LIN_STATS_LEN*ETHT_STATSTRING_LEN,GFP_KERNEL)) == NULL) { + return -ENOMEM; + } + for(i=0; i < SK98LIN_STATS_LEN; i++) { + memcpy(&strings[i * ETHT_STATSTRING_LEN], + &(sk98lin_etht_stats[i].stat_string), + ETHT_STATSTRING_LEN); + } + } + break; +#endif + default: + return -EOPNOTSUPP; + } + if(copy_to_user(pAddr, &gstrings, sizeof(gstrings))) { + err = -EFAULT; + } + pAddr = (void *) ((unsigned long int) pAddr + offsetof(struct ethtool_gstrings, data)); + if(!err && copy_to_user(pAddr, strings, gstrings.len * ETH_GSTRING_LEN)) { + err = -EFAULT; + } + kfree(strings); + return err; + } +#endif +#ifdef ETHTOOL_GSTATS + case ETHTOOL_GSTATS: { + struct { + struct ethtool_stats eth_stats; + uint64_t data[SK98LIN_STATS_LEN]; + } stats = { {ETHTOOL_GSTATS, SK98LIN_STATS_LEN} }; + int i; + + if (netif_running(pAC->dev[port])) { + SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, port); + } + for(i = 0; i < SK98LIN_STATS_LEN; i++) { + if (netif_running(pAC->dev[port])) { + stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat == + sizeof(uint64_t)) ? + *(uint64_t *)((char *)pAC + + sk98lin_etht_stats[i].stat_offset) : + *(uint32_t *)((char *)pAC + + sk98lin_etht_stats[i].stat_offset); + } else { + stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat == + sizeof(uint64_t)) ? (uint64_t) 0 : (uint32_t) 0; + } + } + if(copy_to_user(pAddr, &stats, sizeof(stats))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_PHYS_ID + case ETHTOOL_PHYS_ID: { + struct ethtool_value blinkSecs; + if(copy_from_user(&blinkSecs, pAddr, sizeof(blinkSecs))) { + return -EFAULT; + } + return startLocateNIC(pAC, port, &blinkSecs); + } +#endif +#ifdef ETHTOOL_GPAUSEPARAM + case ETHTOOL_GPAUSEPARAM: { + struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM }; + getPauseParams(pAC, port, &epause); + if(copy_to_user(pAddr, &epause, sizeof(epause))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_SPAUSEPARAM + case ETHTOOL_SPAUSEPARAM: { + struct ethtool_pauseparam epause; + if(copy_from_user(&epause, pAddr, sizeof(epause))) { + return -EFAULT; + } + return setPauseParams(pAC, port, &epause); + } +#endif +#ifdef ETHTOOL_GSG + case ETHTOOL_GSG: { + struct ethtool_value edata = { ETHTOOL_GSG }; + edata.data = (netdev->features & NETIF_F_SG) != 0; + if (copy_to_user(pAddr, &edata, sizeof(edata))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_SSG + case ETHTOOL_SSG: { + struct ethtool_value edata; + if (copy_from_user(&edata, pAddr, sizeof(edata))) { + return -EFAULT; + } + if (pAC->ChipsetType) { /* Don't handle if Genesis */ + if (edata.data) { + netdev->features |= NETIF_F_SG; + } else { + netdev->features &= ~NETIF_F_SG; + } + } + return 0; + } +#endif +#ifdef ETHTOOL_GRXCSUM + case ETHTOOL_GRXCSUM: { + struct ethtool_value edata = { ETHTOOL_GRXCSUM }; + edata.data = pAC->RxPort[port].UseRxCsum; + if (copy_to_user(pAddr, &edata, sizeof(edata))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_SRXCSUM + case ETHTOOL_SRXCSUM: { + struct ethtool_value edata; + if (copy_from_user(&edata, pAddr, sizeof(edata))) { + return -EFAULT; + } + pAC->RxPort[port].UseRxCsum = edata.data; + return 0; + } +#endif +#ifdef ETHTOOL_GTXCSUM + case ETHTOOL_GTXCSUM: { + struct ethtool_value edata = { ETHTOOL_GTXCSUM }; + edata.data = ((netdev->features & NETIF_F_IP_CSUM) != 0); + if (copy_to_user(pAddr, &edata, sizeof(edata))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_STXCSUM + case ETHTOOL_STXCSUM: { + struct ethtool_value edata; + if (copy_from_user(&edata, pAddr, sizeof(edata))) { + return -EFAULT; + } + if (pAC->ChipsetType) { /* Don't handle if Genesis */ + if (edata.data) { + netdev->features |= NETIF_F_IP_CSUM; + } else { + netdev->features &= ~NETIF_F_IP_CSUM; + } + } + return 0; + } +#endif +#ifdef ETHTOOL_NWAY_RST + case ETHTOOL_NWAY_RST: { + if(netif_running(netdev)) { + (*netdev->stop)(netdev); + (*netdev->open)(netdev); + } + return 0; + } +#endif +#ifdef NETIF_F_TSO +#ifdef ETHTOOL_GTSO + case ETHTOOL_GTSO: { + struct ethtool_value edata = { ETHTOOL_GTSO }; + edata.data = (netdev->features & NETIF_F_TSO) != 0; + if (copy_to_user(pAddr, &edata, sizeof(edata))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_STSO + case ETHTOOL_STSO: { + struct ethtool_value edata; + if (CHIP_ID_YUKON_2(pAC)) { + if (copy_from_user(&edata, pAddr, sizeof(edata))) { + return -EFAULT; + } + if (edata.data) { + netdev->features |= NETIF_F_TSO; + } else { + netdev->features &= ~NETIF_F_TSO; + } + return 0; + } + return -EOPNOTSUPP; + } +#endif +#endif +#ifdef ETHTOOL_GCOALESCE + case ETHTOOL_GCOALESCE: { + struct ethtool_coalesce ecoalesc = { ETHTOOL_GCOALESCE }; + getModerationParams(pAC, port, &ecoalesc); + if(copy_to_user(pAddr, &ecoalesc, sizeof(ecoalesc))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_SCOALESCE + case ETHTOOL_SCOALESCE: { + struct ethtool_coalesce ecoalesc; + if(copy_from_user(&ecoalesc, pAddr, sizeof(ecoalesc))) { + return -EFAULT; + } + return setModerationParams(pAC, port, &ecoalesc); + } +#endif +#ifdef ETHTOOL_GWOL + case ETHTOOL_GWOL: { + struct ethtool_wolinfo ewol = { ETHTOOL_GWOL }; + getWOLsettings(pAC, port, &ewol); + if(copy_to_user(pAddr, &ewol, sizeof(ewol))) { + return -EFAULT; + } + return 0; + } +#endif +#ifdef ETHTOOL_SWOL + case ETHTOOL_SWOL: { + struct ethtool_wolinfo ewol; + if(copy_from_user(&ewol, pAddr, sizeof(ewol))) { + return -EFAULT; + } + return setWOLsettings(pAC, port, &ewol); + } +#endif + default: + return -EOPNOTSUPP; + } +} /* SkEthIoctl() */ + +/****************************************************************************** + * + * Local Functions + * + *****************************************************************************/ + +#ifdef ETHTOOL_GSET +/***************************************************************************** + * + * getSettings - retrieves the current settings of the selected adapter + * + * Description: + * The current configuration of the selected adapter is returned. + * This configuration involves a)speed, b)duplex and c)autoneg plus + * a number of other variables. + * + * Returns: N/A + * + */ +static void getSettings( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_cmd *ecmd) /* mandatory command structure for results */ +{ + SK_GEPORT *pPort = &pAC->GIni.GP[port]; + + static int DuplexAutoNegConfMap[9][3]= { + { -1 , -1 , -1 }, + { 0 , -1 , -1 }, + { SK_LMODE_HALF , DUPLEX_HALF, AUTONEG_DISABLE }, + { SK_LMODE_FULL , DUPLEX_FULL, AUTONEG_DISABLE }, + { SK_LMODE_AUTOHALF , DUPLEX_HALF, AUTONEG_ENABLE }, + { SK_LMODE_AUTOFULL , DUPLEX_FULL, AUTONEG_ENABLE }, + { SK_LMODE_AUTOBOTH , DUPLEX_FULL, AUTONEG_ENABLE }, + { SK_LMODE_AUTOSENSE , -1 , -1 }, + { SK_LMODE_INDETERMINATED, -1 , -1 } + }; + + static int SpeedConfMap[6][2] = { + { 0 , -1 }, + { SK_LSPEED_AUTO , -1 }, + { SK_LSPEED_10MBPS , SPEED_10 }, + { SK_LSPEED_100MBPS , SPEED_100 }, + { SK_LSPEED_1000MBPS , SPEED_1000 }, + { SK_LSPEED_INDETERMINATED, -1 } + }; + + static int AdvSpeedMap[6][2] = { + { 0 , -1 }, + { SK_LSPEED_AUTO , -1 }, + { SK_LSPEED_10MBPS , ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full }, + { SK_LSPEED_100MBPS , ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full }, + { SK_LSPEED_1000MBPS , ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full}, + { SK_LSPEED_INDETERMINATED, -1 } + }; + + ecmd->phy_address = port; + ecmd->speed = SpeedConfMap[pPort->PLinkSpeedUsed][1]; + ecmd->duplex = DuplexAutoNegConfMap[pPort->PLinkModeStatus][1]; + ecmd->autoneg = DuplexAutoNegConfMap[pPort->PLinkModeStatus][2]; + ecmd->transceiver = XCVR_INTERNAL; + + if (pAC->GIni.GICopperType) { + ecmd->port = PORT_TP; + ecmd->supported = (SUPP_COPPER_ALL|SUPPORTED_Autoneg); + if (pAC->GIni.GIGenesis) { + ecmd->supported &= ~(SUPPORTED_10baseT_Half); + ecmd->supported &= ~(SUPPORTED_10baseT_Full); + ecmd->supported &= ~(SUPPORTED_100baseT_Half); + ecmd->supported &= ~(SUPPORTED_100baseT_Full); + } else { + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + ecmd->supported &= ~(SUPPORTED_1000baseT_Half); + } + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) { + ecmd->supported &= ~(SUPPORTED_1000baseT_Half); + ecmd->supported &= ~(SUPPORTED_1000baseT_Full); + } + } + if (pAC->GIni.GP[0].PLinkSpeed != SK_LSPEED_AUTO) { + ecmd->advertising = AdvSpeedMap[pPort->PLinkSpeed][1]; + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + ecmd->advertising &= ~(SUPPORTED_1000baseT_Half); + } + } else { + ecmd->advertising = ecmd->supported; + } + if (ecmd->autoneg == AUTONEG_ENABLE) { + ecmd->advertising |= ADVERTISED_Autoneg; + } else { + ecmd->advertising = ADVERTISED_TP; + } + } else { + ecmd->port = PORT_FIBRE; + ecmd->supported = (SUPP_FIBRE_ALL); + ecmd->advertising = (ADV_FIBRE_ALL); + } +} +#endif + +#ifdef ETHTOOL_SSET +/***************************************************************************** + * + * setSettings - configures the settings of a selected adapter + * + * Description: + * Possible settings that may be altered are a)speed, b)duplex or + * c)autonegotiation. + * + * Returns: + * ==0: everything fine, no error + * !=0: the return value is the error code of the failure + */ +static int setSettings( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_cmd *ecmd) /* command structure containing settings */ +{ + DEV_NET *pNet = (DEV_NET *) pAC->dev[port]->priv; + SK_U32 Instance; + char Buf[4]; + unsigned int Len = 1; + int Ret; + + if (port == 0) { + Instance = (pAC->RlmtNets == 2) ? 1 : 2; + } else { + Instance = (pAC->RlmtNets == 2) ? 2 : 3; + } + + if (((ecmd->autoneg == AUTONEG_DISABLE) || (ecmd->autoneg == AUTONEG_ENABLE)) && + ((ecmd->duplex == DUPLEX_FULL) || (ecmd->duplex == DUPLEX_HALF))) { + if (ecmd->autoneg == AUTONEG_DISABLE) { + if (ecmd->duplex == DUPLEX_FULL) { + *Buf = (char) SK_LMODE_FULL; + } else { + *Buf = (char) SK_LMODE_HALF; + } + } else { + if (ecmd->duplex == DUPLEX_FULL) { + *Buf = (char) SK_LMODE_AUTOFULL; + } else { + *Buf = (char) SK_LMODE_AUTOHALF; + } + } + + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE, + &Buf, &Len, Instance, pNet->NetNr); + + if (Ret != SK_PNMI_ERR_OK) { + return -EINVAL; + } + } else if (ecmd->autoneg == AUTONEG_ENABLE) { + /* Set default values */ + *Buf = (char) SK_LMODE_AUTOFULL; + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE, + &Buf, &Len, Instance, pNet->NetNr); + } + + if ((ecmd->speed == SPEED_1000) || + (ecmd->speed == SPEED_100) || + (ecmd->speed == SPEED_10)) { + if (ecmd->autoneg == AUTONEG_ENABLE) { + *Buf = (char) SK_LSPEED_AUTO; + } else if (ecmd->speed == SPEED_1000) { + *Buf = (char) SK_LSPEED_1000MBPS; + } else if (ecmd->speed == SPEED_100) { + *Buf = (char) SK_LSPEED_100MBPS; + } else { + *Buf = (char) SK_LSPEED_10MBPS; + } + + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE, + &Buf, &Len, Instance, pNet->NetNr); + + if (Ret != SK_PNMI_ERR_OK) { + return -EINVAL; + } + } else if (ecmd->autoneg == AUTONEG_ENABLE) { + *Buf = (char) SK_LSPEED_AUTO; + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE, + &Buf, &Len, Instance, pNet->NetNr); + } else { + return -EINVAL; + } + + return 0; +} +#endif + +#ifdef ETHTOOL_GPAUSEPARAM +/***************************************************************************** + * + * getPauseParams - retrieves the pause parameters + * + * Description: + * All current pause parameters of a selected adapter are placed + * in the passed ethtool_pauseparam structure and are returned. + * + * Returns: N/A + * + */ +static void getPauseParams( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_pauseparam *epause) /* pause parameter struct for result */ +{ + SK_GEPORT *pPort = &pAC->GIni.GP[port]; + + epause->rx_pause = 0; + epause->tx_pause = 0; + + if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) { + epause->tx_pause = 1; + } + if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) || + (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) { + epause->tx_pause = 1; + epause->rx_pause = 1; + } + + if ((epause->rx_pause == 0) && (epause->tx_pause == 0)) { + epause->autoneg = SK_FALSE; + } else { + epause->autoneg = SK_TRUE; + } +} +#endif + +#ifdef ETHTOOL_SPAUSEPARAM +/***************************************************************************** + * + * setPauseParams - configures the pause parameters of an adapter + * + * Description: + * This function sets the Rx or Tx pause parameters + * + * Returns: + * ==0: everything fine, no error + * !=0: the return value is the error code of the failure + */ +static int setPauseParams( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_pauseparam *epause) /* pause parameter struct with params */ +{ + SK_GEPORT *pPort = &pAC->GIni.GP[port]; + DEV_NET *pNet = (DEV_NET *) pAC->dev[port]->priv; + int PrevSpeedVal = pPort->PLinkSpeedUsed; + + SK_U32 Instance; + char Buf[4]; + int Ret; + SK_BOOL prevAutonegValue = SK_TRUE; + int prevTxPause = 0; + int prevRxPause = 0; + unsigned int Len = 1; + + if (port == 0) { + Instance = (pAC->RlmtNets == 2) ? 1 : 2; + } else { + Instance = (pAC->RlmtNets == 2) ? 2 : 3; + } + + /* + ** we have to determine the current settings to see if + ** the operator requested any modification of the flow + ** control parameters... + */ + if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) { + prevTxPause = 1; + } + if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) || + (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) { + prevTxPause = 1; + prevRxPause = 1; + } + + if ((prevRxPause == 0) && (prevTxPause == 0)) { + prevAutonegValue = SK_FALSE; + } + + + /* + ** perform modifications regarding the changes + ** requested by the operator + */ + if (epause->autoneg != prevAutonegValue) { + if (epause->autoneg == AUTONEG_DISABLE) { + *Buf = (char) SK_FLOW_MODE_NONE; + } else { + *Buf = (char) SK_FLOW_MODE_SYMMETRIC; + } + } else { + if(epause->rx_pause && epause->tx_pause) { + *Buf = (char) SK_FLOW_MODE_SYMMETRIC; + } else if (epause->rx_pause && !epause->tx_pause) { + *Buf = (char) SK_FLOW_MODE_SYM_OR_REM; + } else if(!epause->rx_pause && epause->tx_pause) { + *Buf = (char) SK_FLOW_MODE_LOC_SEND; + } else { + *Buf = (char) SK_FLOW_MODE_NONE; + } + } + + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE, + &Buf, &Len, Instance, pNet->NetNr); + + if (Ret != SK_PNMI_ERR_OK) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL, + ("ethtool (sk98lin): error changing rx/tx pause (%i)\n", Ret)); + } else { + Len = 1; /* set buffer length to correct value */ + } + + /* + ** It may be that autoneg has been disabled! Therefore + ** set the speed to the previously used value... + */ + *Buf = (char) PrevSpeedVal; + + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE, + &Buf, &Len, Instance, pNet->NetNr); + + if (Ret != SK_PNMI_ERR_OK) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL, + ("ethtool (sk98lin): error setting speed (%i)\n", Ret)); + } + return 0; +} +#endif + +#ifdef ETHTOOL_GCOALESCE +/***************************************************************************** + * + * getModerationParams - retrieves the IRQ moderation settings + * + * Description: + * All current IRQ moderation settings of a selected adapter are placed + * in the passed ethtool_coalesce structure and are returned. + * + * Returns: N/A + * + */ +static void getModerationParams( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct for results */ +{ + DIM_INFO *Info = &pAC->DynIrqModInfo; + SK_BOOL UseTxIrqModeration = SK_FALSE; + SK_BOOL UseRxIrqModeration = SK_FALSE; + + if (Info->IntModTypeSelect != C_INT_MOD_NONE) { + if (CHIP_ID_YUKON_2(pAC)) { + UseRxIrqModeration = SK_TRUE; + UseTxIrqModeration = SK_TRUE; + } else { + if ((Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) || + (Info->MaskIrqModeration == IRQ_MASK_SP_RX) || + (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) { + UseRxIrqModeration = SK_TRUE; + } + if ((Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) || + (Info->MaskIrqModeration == IRQ_MASK_SP_TX) || + (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) { + UseTxIrqModeration = SK_TRUE; + } + } + + if (UseRxIrqModeration) { + ecoalesc->rx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec; + } + if (UseTxIrqModeration) { + ecoalesc->tx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec; + } + if (Info->IntModTypeSelect == C_INT_MOD_DYNAMIC) { + ecoalesc->rate_sample_interval = Info->DynIrqModSampleInterval; + if (UseRxIrqModeration) { + ecoalesc->use_adaptive_rx_coalesce = 1; + ecoalesc->rx_coalesce_usecs_low = + 1000000 / Info->MaxModIntsPerSecLowerLimit; + ecoalesc->rx_coalesce_usecs_high = + 1000000 / Info->MaxModIntsPerSecUpperLimit; + } + if (UseTxIrqModeration) { + ecoalesc->use_adaptive_tx_coalesce = 1; + ecoalesc->tx_coalesce_usecs_low = + 1000000 / Info->MaxModIntsPerSecLowerLimit; + ecoalesc->tx_coalesce_usecs_high = + 1000000 / Info->MaxModIntsPerSecUpperLimit; + } + } + } +} +#endif + +#ifdef ETHTOOL_SCOALESCE +/***************************************************************************** + * + * setModerationParams - configures the IRQ moderation of an adapter + * + * Description: + * Depending on the desired IRQ moderation parameters, either a) static, + * b) dynamic or c) no moderation is configured. + * + * Returns: + * ==0: everything fine, no error + * !=0: the return value is the error code of the failure + * + * Notes: + * The supported timeframe for the coalesced interrupts ranges from + * 33.333us (30 IntsPerSec) down to 25us (40.000 IntsPerSec). + * Any requested value that is not in this range will abort the request! + */ +static int setModerationParams( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct with params */ +{ + DIM_INFO *Info = &pAC->DynIrqModInfo; + int PrevModeration = Info->IntModTypeSelect; + + Info->IntModTypeSelect = C_INT_MOD_NONE; /* initial default */ + + if ((ecoalesc->rx_coalesce_usecs) || (ecoalesc->tx_coalesce_usecs)) { + if (ecoalesc->rx_coalesce_usecs) { + if ((ecoalesc->rx_coalesce_usecs < 25) || + (ecoalesc->rx_coalesce_usecs > 33333)) { + return -EINVAL; + } + } + if (ecoalesc->tx_coalesce_usecs) { + if ((ecoalesc->tx_coalesce_usecs < 25) || + (ecoalesc->tx_coalesce_usecs > 33333)) { + return -EINVAL; + } + } + if (!CHIP_ID_YUKON_2(pAC)) { + if ((Info->MaskIrqModeration == IRQ_MASK_SP_RX) || + (Info->MaskIrqModeration == IRQ_MASK_SP_TX) || + (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) { + Info->MaskIrqModeration = IRQ_MASK_SP_ONLY; + } + } + Info->IntModTypeSelect = C_INT_MOD_STATIC; + if (ecoalesc->rx_coalesce_usecs) { + Info->MaxModIntsPerSec = + 1000000 / ecoalesc->rx_coalesce_usecs; + if (!CHIP_ID_YUKON_2(pAC)) { + if (Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) { + Info->MaskIrqModeration = IRQ_MASK_TX_RX; + } + if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) { + Info->MaskIrqModeration = IRQ_MASK_SP_RX; + } + if (Info->MaskIrqModeration == IRQ_MASK_SP_TX) { + Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP; + } + } else { + Info->MaskIrqModeration = Y2_IRQ_MASK; + } + } + if (ecoalesc->tx_coalesce_usecs) { + Info->MaxModIntsPerSec = + 1000000 / ecoalesc->tx_coalesce_usecs; + if (!CHIP_ID_YUKON_2(pAC)) { + if (Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) { + Info->MaskIrqModeration = IRQ_MASK_TX_RX; + } + if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) { + Info->MaskIrqModeration = IRQ_MASK_SP_TX; + } + if (Info->MaskIrqModeration == IRQ_MASK_SP_RX) { + Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP; + } + } else { + Info->MaskIrqModeration = Y2_IRQ_MASK; + } + } + } + if ((ecoalesc->rate_sample_interval) || + (ecoalesc->rx_coalesce_usecs_low) || + (ecoalesc->tx_coalesce_usecs_low) || + (ecoalesc->rx_coalesce_usecs_high)|| + (ecoalesc->tx_coalesce_usecs_high)) { + if (ecoalesc->rate_sample_interval) { + if ((ecoalesc->rate_sample_interval < 1) || + (ecoalesc->rate_sample_interval > 10)) { + return -EINVAL; + } + } + if (ecoalesc->rx_coalesce_usecs_low) { + if ((ecoalesc->rx_coalesce_usecs_low < 25) || + (ecoalesc->rx_coalesce_usecs_low > 33333)) { + return -EINVAL; + } + } + if (ecoalesc->rx_coalesce_usecs_high) { + if ((ecoalesc->rx_coalesce_usecs_high < 25) || + (ecoalesc->rx_coalesce_usecs_high > 33333)) { + return -EINVAL; + } + } + if (ecoalesc->tx_coalesce_usecs_low) { + if ((ecoalesc->tx_coalesce_usecs_low < 25) || + (ecoalesc->tx_coalesce_usecs_low > 33333)) { + return -EINVAL; + } + } + if (ecoalesc->tx_coalesce_usecs_high) { + if ((ecoalesc->tx_coalesce_usecs_high < 25) || + (ecoalesc->tx_coalesce_usecs_high > 33333)) { + return -EINVAL; + } + } + + Info->IntModTypeSelect = C_INT_MOD_DYNAMIC; + if (ecoalesc->rate_sample_interval) { + Info->DynIrqModSampleInterval = + ecoalesc->rate_sample_interval; + } + if (ecoalesc->rx_coalesce_usecs_low) { + Info->MaxModIntsPerSecLowerLimit = + 1000000 / ecoalesc->rx_coalesce_usecs_low; + } + if (ecoalesc->tx_coalesce_usecs_low) { + Info->MaxModIntsPerSecLowerLimit = + 1000000 / ecoalesc->tx_coalesce_usecs_low; + } + if (ecoalesc->rx_coalesce_usecs_high) { + Info->MaxModIntsPerSecUpperLimit = + 1000000 / ecoalesc->rx_coalesce_usecs_high; + } + if (ecoalesc->tx_coalesce_usecs_high) { + Info->MaxModIntsPerSecUpperLimit = + 1000000 / ecoalesc->tx_coalesce_usecs_high; + } + } + + if ((PrevModeration == C_INT_MOD_NONE) && + (Info->IntModTypeSelect != C_INT_MOD_NONE)) { + SkDimEnableModerationIfNeeded(pAC); + } + if (PrevModeration != C_INT_MOD_NONE) { + SkDimDisableModeration(pAC, PrevModeration); + if (Info->IntModTypeSelect != C_INT_MOD_NONE) { + SkDimEnableModerationIfNeeded(pAC); + } + } + + return 0; +} +#endif + +#ifdef ETHTOOL_GWOL +/***************************************************************************** + * + * getWOLsettings - retrieves the WOL settings of the selected adapter + * + * Description: + * All current WOL settings of a selected adapter are placed in the + * passed ethtool_wolinfo structure and are returned to the caller. + * + * Returns: N/A + * + */ +static void getWOLsettings( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_wolinfo *ewol) /* mandatory WOL structure for results */ +{ + ewol->supported = pAC->WolInfo.SupportedWolOptions; + ewol->wolopts = pAC->WolInfo.ConfiguredWolOptions; + + return; +} +#endif + +#ifdef ETHTOOL_SWOL +/***************************************************************************** + * + * setWOLsettings - configures the WOL settings of a selected adapter + * + * Description: + * The WOL settings of a selected adapter are configured regarding + * the parameters in the passed ethtool_wolinfo structure. + * Note that currently only wake on magic packet is supported! + * + * Returns: + * ==0: everything fine, no error + * !=0: the return value is the error code of the failure + */ +static int setWOLsettings( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_wolinfo *ewol) /* WOL structure containing settings */ +{ + if (((ewol->wolopts & WAKE_MAGIC) == WAKE_MAGIC) || (ewol->wolopts == 0)) { + pAC->WolInfo.ConfiguredWolOptions = ewol->wolopts; + return 0; + } + return -EFAULT; +} +#endif + +#ifdef ETHTOOL_GDRVINFO +/***************************************************************************** + * + * getDriverInfo - returns generic driver and adapter information + * + * Description: + * Generic driver information is returned via this function, such as + * the name of the driver, its version and and firmware version. + * In addition to this, the location of the selected adapter is + * returned as a bus info string (e.g. '01:05.0'). + * + * Returns: N/A + * + */ +static void getDriverInfo( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_drvinfo *edrvinfo) /* mandatory info structure for results */ +{ + char versionString[32]; + + snprintf(versionString, 32, "%s (%s)", VER_STRING, PATCHLEVEL); + strncpy(edrvinfo->driver, DRIVER_FILE_NAME , 32); + strncpy(edrvinfo->version, versionString , 32); + strncpy(edrvinfo->fw_version, "N/A", 32); + strncpy(edrvinfo->bus_info, pci_name(pAC->PciDev), 32); + +#ifdef ETHTOOL_GSTATS + edrvinfo->n_stats = SK98LIN_STATS_LEN; +#endif +} +#endif + +#ifdef ETHTOOL_PHYS_ID +/***************************************************************************** + * + * startLocateNIC - start the locate NIC feature of the elected adapter + * + * Description: + * This function is used if the user want to locate a particular NIC. + * All LEDs are regularly switched on and off, so the NIC can easily + * be identified. + * + * Returns: + * ==0: everything fine, no error, locateNIC test was started + * !=0: one locateNIC test runs already + * + */ +static int startLocateNIC( +SK_AC *pAC, /* pointer to adapter control context */ +int port, /* the port of the selected adapter */ +struct ethtool_value *blinkSecs) /* how long the LEDs should blink in seconds */ +{ + struct SK_NET_DEVICE *pDev = pAC->dev[port]; + int OtherPort = (port) ? 0 : 1; + struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort]; + + if (isLocateNICrunning) { + return -EFAULT; + } + isLocateNICrunning = SK_TRUE; + currentPortIndex = port; + isDualNetCard = (pDev != pOtherDev) ? SK_TRUE : SK_FALSE; + + if (netif_running(pAC->dev[port])) { + boardWasDown[0] = SK_FALSE; + } else { + (*pDev->open)(pDev); + boardWasDown[0] = SK_TRUE; + } + + if (isDualNetCard) { + if (netif_running(pAC->dev[OtherPort])) { + boardWasDown[1] = SK_FALSE; + } else { + (*pOtherDev->open)(pOtherDev); + boardWasDown[1] = SK_TRUE; + } + } + + if ((blinkSecs->data < 1) || (blinkSecs->data > 30)) { + blinkSecs->data = 3; /* three seconds default */ + } + nbrBlinkQuarterSeconds = 4*blinkSecs->data; + + init_timer(&locateNICtimer); + locateNICtimer.function = toggleLeds; + locateNICtimer.data = (unsigned long) pAC; + locateNICtimer.expires = jiffies + HZ; /* initially 1sec */ + add_timer(&locateNICtimer); + + return 0; +} + +/***************************************************************************** + * + * toggleLeds - Changes the LED state of an adapter + * + * Description: + * This function changes the current state of all LEDs of an adapter so + * that it can be located by a user. If the requested time interval for + * this test has elapsed, this function cleans up everything that was + * temporarily setup during the locate NIC test. This involves of course + * also closing or opening any adapter so that the initial board state + * is recovered. + * + * Returns: N/A + * + */ +static void toggleLeds( +unsigned long ptr) /* holds the pointer to adapter control context */ +{ + SK_AC *pAC = (SK_AC *) ptr; + int port = currentPortIndex; + SK_IOC IoC = pAC->IoBase; + struct SK_NET_DEVICE *pDev = pAC->dev[port]; + int OtherPort = (port) ? 0 : 1; + struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort]; + + SK_U16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON) | + PHY_M_LED_MO_10(MO_LED_ON) | + PHY_M_LED_MO_100(MO_LED_ON) | + PHY_M_LED_MO_1000(MO_LED_ON) | + PHY_M_LED_MO_RX(MO_LED_ON)); + SK_U16 YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF) | + PHY_M_LED_MO_10(MO_LED_OFF) | + PHY_M_LED_MO_100(MO_LED_OFF) | + PHY_M_LED_MO_1000(MO_LED_OFF) | + PHY_M_LED_MO_RX(MO_LED_OFF)); + + nbrBlinkQuarterSeconds--; + if (nbrBlinkQuarterSeconds <= 0) { + (*pDev->stop)(pDev); + if (isDualNetCard) { + (*pOtherDev->stop)(pOtherDev); + } + + if (!boardWasDown[0]) { + (*pDev->open)(pDev); + } + if (isDualNetCard) { + (*pOtherDev->open)(pOtherDev); + } + isDualNetCard = SK_FALSE; + isLocateNICrunning = SK_FALSE; + return; + } + + doSwitchLEDsOn = (doSwitchLEDsOn) ? SK_FALSE : SK_TRUE; + if (doSwitchLEDsOn) { + if (pAC->GIni.GIGenesis) { + SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_ON); + SkGeYellowLED(pAC,IoC,LED_ON >> 1); + SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_TST); + if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) { + SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_ON); + } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) { + SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,0x0800); + } else { + SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_TST); + } + } else { + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0); + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOn); + } + } else { + if (pAC->GIni.GIGenesis) { + SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_OFF); + SkGeYellowLED(pAC,IoC,LED_OFF >> 1); + SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_DIS); + if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) { + SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_OFF); + } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) { + SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,PHY_L_LC_LEDT); + } else { + SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_DIS); + } + } else { + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0); + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOff); + } + } + + locateNICtimer.function = toggleLeds; + locateNICtimer.data = (unsigned long) pAC; + locateNICtimer.expires = jiffies + (HZ/4); /* 250ms */ + add_timer(&locateNICtimer); +} +#endif + +/***************************************************************************** + * + * getPortNumber - evaluates the port number of an interface + * + * Description: + * It may be that the current interface refers to one which is located + * on a dual net adapter. Hence, this function will return the correct + * port for further use. + * + * Returns: + * the port number that corresponds to the selected adapter + * + */ +static int getPortNumber( +struct net_device *netdev, /* the pointer to netdev structure */ +struct ifreq *ifr) /* what interface the request refers to? */ +{ + DEV_NET *pNet = (DEV_NET*) netdev->priv; + SK_AC *pAC = pNet->pAC; + + if (pAC->dev[1] != pAC->dev[0]) { + if (!strcmp(pAC->dev[1]->name, ifr->ifr_name)) { + return 1; /* port index 1 */ + } + } + return 0; +} + +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ + +#endif diff --git a/drivers/sk98lin/skge.c b/drivers/sk98lin/skge.c index 61a6094..1b96476 100644 --- a/drivers/sk98lin/skge.c +++ b/drivers/sk98lin/skge.c @@ -1,47 +1,26 @@ /****************************************************************************** * - * Name: skge.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.46 $ - * Date: $Date: 2003/02/25 14:16:36 $ - * Purpose: The main driver source module + * Name: skge.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.60.2.68 $ + * Date: $Date: 2005/11/14 15:22:08 $ + * Purpose: The main driver source module * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2005 Marvell. * - * Driver for SysKonnect Gigabit Ethernet Server Adapters: + * Driver for Marvell Yukon chipset and SysKonnect Gigabit Ethernet + * Server Adapters. * - * SK-9871 (single link 1000Base-ZX) - * SK-9872 (dual link 1000Base-ZX) - * SK-9861 (single link 1000Base-SX, VF45 Volition Plug) - * SK-9862 (dual link 1000Base-SX, VF45 Volition Plug) - * SK-9841 (single link 1000Base-LX) - * SK-9842 (dual link 1000Base-LX) - * SK-9843 (single link 1000Base-SX) - * SK-9844 (dual link 1000Base-SX) - * SK-9821 (single link 1000Base-T) - * SK-9822 (dual link 1000Base-T) - * SK-9881 (single link 1000Base-SX V2 LC) - * SK-9871 (single link 1000Base-ZX V2) - * SK-9861 (single link 1000Base-SX V2, VF45 Volition Plug) - * SK-9841 (single link 1000Base-LX V2) - * SK-9843 (single link 1000Base-SX V2) - * SK-9821 (single link 1000Base-T V2) - * - * Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and - * SysKonnects GEnesis Solaris driver - * Author: Christoph Goos (cgoos@syskonnect.de) - * Mirko Lindner (mlindner@syskonnect.de) + * Author: Mirko Lindner (mlindner@syskonnect.de) + * Ralph Roesler (rroesler@syskonnect.de) * * Address all question to: linux@syskonnect.de * - * The technical manual for the adapters is available from SysKonnect's - * web pages: www.syskonnect.com - * Goto "Support" and search Knowledge Base for "manual". - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -51,368 +30,106 @@ * ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: skge.c,v $ - * Revision 1.46 2003/02/25 14:16:36 mlindner - * Fix: Copyright statement - * - * Revision 1.45 2003/02/25 13:25:55 mlindner - * Add: Performance improvements - * Add: Support for various vendors - * Fix: Init function - * - * Revision 1.44 2003/01/09 09:25:26 mlindner - * Fix: Remove useless init_module/cleanup_module forward declarations - * - * Revision 1.43 2002/11/29 08:42:41 mlindner - * Fix: Boot message - * - * Revision 1.42 2002/11/28 13:30:23 mlindner - * Add: New frame check - * - * Revision 1.41 2002/11/27 13:55:18 mlindner - * Fix: Drop wrong csum packets - * Fix: Initialize proc_entry after hw check - * - * Revision 1.40 2002/10/31 07:50:37 tschilli - * Function SkGeInitAssignRamToQueues() from common module inserted. - * Autonegotiation is set to ON for all adapters. - * LinkSpeedUsed is used in link up status report. - * Role parameter will show up for 1000 Mbps links only. - * GetConfiguration() inserted after init level 1 in SkGeChangeMtu(). - * All return values of SkGeInit() and SkGeInitPort() are checked. - * - * Revision 1.39 2002/10/02 12:56:05 mlindner - * Add: Support for Yukon - * Add: Support for ZEROCOPY, scatter-gather and hw checksum - * Add: New transmit ring function (use SG and TCP/UDP hardware checksumming) - * Add: New init function - * Add: Speed check and setup - * Add: Merge source for kernel 2.2.x and 2.4.x - * Add: Opcode check for tcp - * Add: Frame length check - * Fix: Transmit complete interrupt - * Fix: Interrupt moderation - * - * Revision 1.29.2.13 2002/01/14 12:44:52 mlindner - * Fix: Rlmt modes - * - * Revision 1.29.2.12 2001/12/07 12:06:18 mlindner - * Fix: malloc -> slab changes - * - * Revision 1.29.2.11 2001/12/06 15:19:20 mlindner - * Add: DMA attributes - * Fix: Module initialisation - * Fix: pci_map_single and pci_unmap_single replaced - * - * Revision 1.29.2.10 2001/12/06 09:56:50 mlindner - * Corrected some printk's - * - * Revision 1.29.2.9 2001/09/05 12:15:34 mlindner - * Add: LBFO Changes - * Fix: Counter Errors (Jumbo == to long errors) - * Fix: Changed pAC->PciDev declaration - * Fix: too short counters - * - * Revision 1.29.2.8 2001/06/25 12:10:44 mlindner - * fix: ReceiveIrq() changed. - * - * Revision 1.29.2.7 2001/06/25 08:07:05 mlindner - * fix: RLMT locking in ReceiveIrq() changed. - * - * Revision 1.29.2.6 2001/05/21 07:59:29 mlindner - * fix: MTU init problems - * - * Revision 1.29.2.5 2001/05/08 11:25:08 mlindner - * fix: removed VLAN error message - * - * Revision 1.29.2.4 2001/05/04 13:31:43 gklug - * fix: do not handle eth_copy on bad fragments received. - * - * Revision 1.29.2.3 2001/04/23 08:06:43 mlindner - * Fix: error handling - * - * Revision 1.29.2.2 2001/03/15 12:04:54 mlindner - * Fixed memory problem - * - * Revision 1.29.2.1 2001/03/12 16:41:44 mlindner - * add: procfs function - * add: dual-net function - * add: RLMT networks - * add: extended PNMI features - * - * Kernel 2.4.x specific: - * Revision 1.xx 2000/09/12 13:31:56 cgoos - * Fixed missign "dev=NULL in skge_probe. - * Added counting for jumbo frames (corrects error statistic). - * Removed VLAN tag check (enables VLAN support). - * - * Kernel 2.2.x specific: - * Revision 1.29 2000/02/21 13:31:56 cgoos - * Fixed "unused" warning for UltraSPARC change. - * - * Partially kernel 2.2.x specific: - * Revision 1.28 2000/02/21 10:32:36 cgoos - * Added fixes for UltraSPARC. - * Now printing RlmtMode and PrefPort setting at startup. - * Changed XmitFrame return value. - * Fixed rx checksum calculation for BIG ENDIAN systems. - * Fixed rx jumbo frames counted as ierrors. - * - * - * Revision 1.27 1999/11/25 09:06:28 cgoos - * Changed base_addr to unsigned long. - * - * Revision 1.26 1999/11/22 13:29:16 cgoos - * Changed license header to GPL. - * Changes for inclusion in linux kernel (2.2.13). - * Removed 2.0.x defines. - * Changed SkGeProbe to skge_probe. - * Added checks in SkGeIoctl. - * - * Revision 1.25 1999/10/07 14:47:52 cgoos - * Changed 984x to 98xx. - * - * Revision 1.24 1999/09/30 07:21:01 cgoos - * Removed SK_RLMT_SLOW_LOOKAHEAD option. - * Giving spanning tree packets also to OS now. - * - * Revision 1.23 1999/09/29 07:36:50 cgoos - * Changed assignment for IsBc/IsMc. - * - * Revision 1.22 1999/09/28 12:57:09 cgoos - * Added CheckQueue also to Single-Port-ISR. - * - * Revision 1.21 1999/09/28 12:42:41 cgoos - * Changed parameter strings for RlmtMode. - * - * Revision 1.20 1999/09/28 12:37:57 cgoos - * Added CheckQueue for fast delivery of RLMT frames. - * - * Revision 1.19 1999/09/16 07:57:25 cgoos - * Copperfield changes. - * - * Revision 1.18 1999/09/03 13:06:30 cgoos - * Fixed RlmtMode=CheckSeg bug: wrong DEV_KFREE_SKB in RLMT_SEND caused - * double allocated skb's. - * FrameStat in ReceiveIrq was accessed via wrong Rxd. - * Queue size for async. standby Tx queue was zero. - * FillRxLimit of 0 could cause problems with ReQueue, changed to 1. - * Removed debug output of checksum statistic. - * - * Revision 1.17 1999/08/11 13:55:27 cgoos - * Transmit descriptor polling was not reenabled after SkGePortInit. - * - * Revision 1.16 1999/07/27 15:17:29 cgoos - * Added some "\n" in output strings (removed while debuging...). - * - * Revision 1.15 1999/07/23 12:09:30 cgoos - * Performance optimization, rx checksumming, large frame support. - * - * Revision 1.14 1999/07/14 11:26:27 cgoos - * Removed Link LED settings (now in RLMT). - * Added status output at NET UP. - * Fixed SMP problems with Tx and SWITCH running in parallel. - * Fixed return code problem at RLMT_SEND event. - * - * Revision 1.13 1999/04/07 10:11:42 cgoos - * Fixed Single Port problems. - * Fixed Multi-Adapter problems. - * Always display startup string. - * - * Revision 1.12 1999/03/29 12:26:37 cgoos - * Reversed locking to fine granularity. - * Fixed skb double alloc problem (caused by incorrect xmit return code). - * Enhanced function descriptions. - * - * Revision 1.11 1999/03/15 13:10:51 cgoos - * Changed device identifier in output string to ethX. - * - * Revision 1.10 1999/03/15 12:12:34 cgoos - * Changed copyright notice. - * - * Revision 1.9 1999/03/15 12:10:17 cgoos - * Changed locking to one driver lock. - * Added check of SK_AC-size (for consistency with library). - * - * Revision 1.8 1999/03/08 11:44:02 cgoos - * Fixed missing dev->tbusy in SkGeXmit. - * Changed large frame (jumbo) buffer number. - * Added copying of short frames. - * - * Revision 1.7 1999/03/04 13:26:57 cgoos - * Fixed spinlock calls for SMP. - * - * Revision 1.6 1999/03/02 09:53:51 cgoos - * Added descriptor revertion for big endian machines. - * - * Revision 1.5 1999/03/01 08:50:59 cgoos - * Fixed SkGeChangeMtu. - * Fixed pci config space accesses. - * - * Revision 1.4 1999/02/18 15:48:44 cgoos - * Corrected some printk's. - * - * Revision 1.3 1999/02/18 12:45:55 cgoos - * Changed SK_MAX_CARD_PARAM to default 16 - * - * Revision 1.2 1999/02/18 10:55:32 cgoos - * Removed SkGeDrvTimeStamp function. - * Printing "ethX:" before adapter type at adapter init. - * - * - * 10-Feb-1999 cg Created, based on Linux' acenic.c, 3c59x.c and - * SysKonnects GEnesis Solaris driver - * - ******************************************************************************/ - -/****************************************************************************** - * - * Possible compiler options (#define xxx / -Dxxx): - * - * debugging can be enable by changing SK_DEBUG_CHKMOD and - * SK_DEBUG_CHKCAT in makefile (described there). - * - ******************************************************************************/ - /****************************************************************************** * * Description: * - * This is the main module of the Linux GE driver. + * All source files in this sk98lin directory except of the sk98lin + * Linux specific files * - * All source files except skge.c, skdrv1st.h, skdrv2nd.h and sktypes.h - * are part of SysKonnect's COMMON MODULES for the SK-98xx adapters. - * Those are used for drivers on multiple OS', so some thing may seem - * unnecessary complicated on Linux. Please do not try to 'clean up' - * them without VERY good reasons, because this will make it more - * difficult to keep the Linux driver in synchronisation with the - * other versions. + * - skdim.c + * - skethtool.c + * - skge.c + * - skproc.c + * - sky2.c + * - Makefile + * - h/skdrv1st.h + * - h/skdrv2nd.h + * - h/sktypes.h + * - h/skversion.h * - * Include file hierarchy: + * are part of SysKonnect's common modules for the SK-9xxx adapters. * - * + * Those common module files which are not Linux specific are used to + * build drivers on different OS' (e.g. Windows, MAC OS) so that those + * drivers are based on the same set of files * - * "h/skdrv1st.h" - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * those three depending on kernel version used: - * - * - * - * - * - * "h/skerror.h" - * "h/skdebug.h" - * "h/sktypes.h" - * "h/lm80.h" - * "h/xmac_ii.h" - * - * "h/skdrv2nd.h" - * "h/skqueue.h" - * "h/skgehwt.h" - * "h/sktimer.h" - * "h/ski2c.h" - * "h/skgepnmi.h" - * "h/skvpd.h" - * "h/skgehw.h" - * "h/skgeinit.h" - * "h/skaddr.h" - * "h/skgesirq.h" - * "h/skcsum.h" - * "h/skrlmt.h" + * At a first glance, this seems to complicate things unnescessarily on + * Linux, but please do not try to 'clean up' them without VERY good + * reasons, because this will make it more difficult to keep the sk98lin + * driver for Linux in synchronisation with the other drivers running on + * other operating systems. * ******************************************************************************/ - +/*#define DEBUG*/ #include - #ifdef CONFIG_SK98 #include "h/skversion.h" -#if 0 + +#if 0 /* uboot */ #include #include +#include +#endif + +#ifdef CONFIG_PROC_FS #include #endif + #include "h/skdrv1st.h" #include "h/skdrv2nd.h" -/* defines ******************************************************************/ +/******************************************************************************* + * + * Defines + * + ******************************************************************************/ + /* for debuging on x86 only */ /* #define BREAKPOINT() asm(" int $3"); */ -/* use the scatter-gather functionality with sendfile() */ -#if 0 -#define SK_ZEROCOPY + +/* Set blink mode*/ +#define OEM_CONFIG_VALUE ( SK_ACT_LED_BLINK | \ + SK_DUP_LED_NORMAL | \ + SK_LED_LINK100_ON) + +#define CLEAR_AND_START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START | CSR_IRQ_CL_F) +#define CLEAR_TX_IRQ(Port,Prio) SK_OUT8(pAC->IoBase, TxQueueAddr[(Port)][(Prio)]+Q_CSR, CSR_IRQ_CL_F) + + +/******************************************************************************* + * + * Local Function Prototypes + * + ******************************************************************************/ + +#if 0 /* uboot */ +static int __devinit sk98lin_init_device(struct pci_dev *pdev, const struct pci_device_id *ent); +static void sk98lin_remove_device(struct pci_dev *pdev); +#endif +#ifdef CONFIG_PM +static int sk98lin_suspend(struct pci_dev *pdev, u32 state); +static int sk98lin_resume(struct pci_dev *pdev); +static void SkEnableWOMagicPacket(SK_AC *pAC, SK_IOC IoC, SK_MAC_ADDR MacAddr); +#endif +#ifdef Y2_RECOVERY +static void SkGeHandleKernelTimer(unsigned long ptr); +void SkGeCheckTimer(DEV_NET *pNet); +static SK_BOOL CheckRXCounters(DEV_NET *pNet); +static void CheckRxPath(DEV_NET *pNet); #endif - -/* use of a transmit complete interrupt */ -#define USE_TX_COMPLETE - -/* use interrupt moderation (for tx complete only) */ -#define USE_INT_MOD -#define INTS_PER_SEC 1000 - -/* - * threshold for copying small receive frames - * set to 0 to avoid copying, set to 9001 to copy all frames - */ -#define SK_COPY_THRESHOLD 50 - -/* number of adapters that can be configured via command line params */ -#define SK_MAX_CARD_PARAM 16 - - -/* - * use those defines for a compile-in version of the driver instead - * of command line parameters - */ -/* #define LINK_SPEED_A {"Auto", } */ -/* #define LINK_SPEED_B {"Auto", } */ -/* #define AUTO_NEG_A {"Sense", } */ -/* #define AUTO_NEG_B {"Sense", } */ -/* #define DUP_CAP_A {"Both", } */ -/* #define DUP_CAP_B {"Both", } */ -/* #define FLOW_CTRL_A {"SymOrRem", } */ -/* #define FLOW_CTRL_B {"SymOrRem", } */ -/* #define ROLE_A {"Auto", } */ -/* #define ROLE_B {"Auto", } */ -/* #define PREF_PORT {"A", } */ -/* #define RLMT_MODE {"CheckLinkState", } */ - -#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb) -#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb) -#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb) - -/* function prototypes ******************************************************/ static void FreeResources(struct SK_NET_DEVICE *dev); static int SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC); static SK_BOOL BoardAllocMem(SK_AC *pAC); static void BoardFreeMem(SK_AC *pAC); static void BoardInitMem(SK_AC *pAC); -static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, - int*, SK_BOOL); - -#if 0 -static void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); -static void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); +static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, int*, SK_BOOL); +#if 0 /* uboot */ +static SkIsrRetVar SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); +static SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); static int SkGeOpen(struct SK_NET_DEVICE *dev); static int SkGeClose(struct SK_NET_DEVICE *dev); static int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev); @@ -421,439 +138,1368 @@ static void SkGeSetRxMode(struct SK_NET_DEVICE *dev); static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev); static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd); #else -void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); -void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); +SkIsrRetVar SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); +SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); int SkGeOpen(struct SK_NET_DEVICE *dev); int SkGeClose(struct SK_NET_DEVICE *dev); int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev); #endif static void GetConfiguration(SK_AC*); +#if 0 /* uboot */ static void ProductStr(SK_AC*); +#endif static int XmitFrame(SK_AC*, TX_PORT*, struct sk_buff*); static void FreeTxDescriptors(SK_AC*pAC, TX_PORT*); static void FillRxRing(SK_AC*, RX_PORT*); static SK_BOOL FillRxDescriptor(SK_AC*, RX_PORT*); -#if 0 +#ifdef CONFIG_SK98LIN_NAPI +static int SkGePoll(struct net_device *dev, int *budget); +static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL, int*, int); +#else +#if 0 /* uboot */ static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL); #else void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL); #endif -static void ClearAndStartRx(SK_AC*, int); -static void ClearTxIrq(SK_AC*, int, int); +#endif +#ifdef SK_POLL_CONTROLLER +static void SkGeNetPoll(struct SK_NET_DEVICE *dev); +#endif static void ClearRxRing(SK_AC*, RX_PORT*); static void ClearTxRing(SK_AC*, TX_PORT*); -#if 0 -static void SetQueueSizes(SK_AC *pAC); - +#if 0 /* uboot */ static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int new_mtu); #endif static void PortReInitBmu(SK_AC*, int); -#if 0 +#if 0 /* uboot */ static int SkGeIocMib(DEV_NET*, unsigned int, int); +static int SkGeInitPCI(SK_AC *pAC); +static SK_U32 ParseDeviceNbrFromSlotName(const char *SlotName); +#endif +static int SkDrvInitAdapter(SK_AC *pAC, int devNbr); +static int SkDrvDeInitAdapter(SK_AC *pAC, int devNbr); +extern void SkLocalEventQueue( SK_AC *pAC, + SK_U32 Class, + SK_U32 Event, + SK_U32 Param1, + SK_U32 Param2, + SK_BOOL Flag); +extern void SkLocalEventQueue64( SK_AC *pAC, + SK_U32 Class, + SK_U32 Event, + SK_U64 Param, + SK_BOOL Flag); +#if 0 /* uboot */ static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*); #endif -/*Extern */ +/******************************************************************************* + * + * Extern Function Prototypes + * + ******************************************************************************/ -/* external Proc function */ -extern int proc_read( - char *buffer, - char **buffer_location, - off_t offset, - int buffer_length, - int *eof, - void *data); +extern SK_BOOL SkY2AllocateResources(SK_AC *pAC); +extern void SkY2FreeResources(SK_AC *pAC); +extern void SkY2AllocateRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port); +extern void SkY2FreeRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port); +extern void SkY2FreeTxBuffers(SK_AC *pAC,SK_IOC IoC,int Port); +extern SkIsrRetVar SkY2Isr(int irq,void *dev_id,struct pt_regs *ptregs); +extern int SkY2Xmit(struct sk_buff *skb,struct SK_NET_DEVICE *dev); +extern void SkY2PortStop(SK_AC *pAC,SK_IOC IoC,int Port,int Dir,int RstMode); +extern void SkY2PortStart(SK_AC *pAC,SK_IOC IoC,int Port); +extern int SkY2RlmtSend(SK_AC *pAC,int PortNr,struct sk_buff *pMessage); +extern void SkY2RestartStatusUnit(SK_AC *pAC); +extern void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port); +#ifdef CONFIG_SK98LIN_NAPI +extern int SkY2Poll(struct net_device *dev, int *budget); +#endif + +extern void SkDimEnableModerationIfNeeded(SK_AC *pAC); +extern void SkDimStartModerationTimer(SK_AC *pAC); +extern void SkDimModerate(SK_AC *pAC); + + +#if 0/* uboot */ +extern int SkEthIoctl(struct net_device *netdev, struct ifreq *ifr); +#endif + +#ifdef CONFIG_PROC_FS +static const char SK_Root_Dir_entry[] = "sk98lin"; +static struct proc_dir_entry *pSkRootDir; +extern struct file_operations sk_proc_fops; +#endif #ifdef DEBUG static void DumpMsg(struct sk_buff*, char*); static void DumpData(char*, int); static void DumpLong(char*, int); #endif -void dump_frag( SK_U8 *data, int length); /* global variables *********************************************************/ -#if 0 +#if 0 /* uboot */ static const char *BootString = BOOT_STRING; #endif struct SK_NET_DEVICE *SkGeRootDev = NULL; -static int probed __initdata = 0; +static SK_BOOL DoPrintInterfaceChange = SK_TRUE; /* local variables **********************************************************/ static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}}; static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480}; +#if 0 /* uboot */ +static int sk98lin_max_boards_found = 0; +#endif - -/* local variables **********************************************************/ -const char SK_Root_Dir_entry[8]; - -#if 0 +#ifdef CONFIG_PROC_FS static struct proc_dir_entry *pSkRootDir; #endif -static struct pci_device_id supported[] = { - {PCI_VENDOR_ID_3COM, 0x1700}, - {PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE}, - {PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU}, - {} + + +#if 0 /* uboot */ +static struct pci_device_id sk98lin_pci_tbl[] __devinitdata = { +/* { pci_vendor_id, pci_device_id, * SAMPLE ENTRY! * + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, */ + { 0x10b7, 0x1700, /* 3Com (10b7), Gigabit Ethernet Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x10b7, 0x80eb, /* 3Com (10b7), 3Com 3C940B Gigabit LOM Ethernet Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1148, 0x4300, /* SysKonnect (1148), SK-98xx Gigabit Ethernet Server Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1148, 0x4320, /* SysKonnect (1148), SK-98xx V2.0 Gigabit Ethernet Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1148, 0x9000, /* SysKonnect (1148), SK-9Sxx 10/100/1000Base-T Server Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1148, 0x9E00, /* SysKonnect (1148), SK-9Exx 10/100/1000Base-T Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1186, 0x4b00, /* D-Link (1186), Gigabit Ethernet Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1186, 0x4b01, /* D-Link (1186), Gigabit Ethernet Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1186, 0x4b02, /* D-Link (1186), Gigabit Ethernet Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1186, 0x4c00, /* D-Link (1186), Gigabit Ethernet Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4320, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4340, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4341, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4342, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4343, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4344, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4345, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4346, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4347, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4350, /* Marvell (11ab), Fast Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4351, /* Marvell (11ab), Fast Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4352, /* Marvell (11ab), Fast Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4356, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4360, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4361, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4362, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4363, /* Marvell (11ab), Marvell */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4364, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4366, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4367, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x4368, /* Marvell (11ab), Gigabit Ethernet Controller */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x11ab, 0x5005, /* Marvell (11ab), Belkin */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1371, 0x434e, /* CNet (1371), GigaCard Network Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1737, 0x1032, /* Linksys (1737), Gigabit Network Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0x1737, 0x1064, /* Linksys (1737), Gigabit Network Adapter */ + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, sk98lin_pci_tbl); + +static struct pci_driver sk98lin_driver = { + .name = DRIVER_FILE_NAME, + .id_table = sk98lin_pci_tbl, + .probe = sk98lin_init_device, + .remove = __devexit_p(sk98lin_remove_device), +#ifdef CONFIG_PM + .suspend = sk98lin_suspend, + .resume = sk98lin_resume +#endif }; +#else + +static struct pci_device_id supported[] = { +/* { pci_vendor_id, pci_device_id, * SAMPLE ENTRY! * + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, */ + { 0x10b7, 0x1700, /* 3Com (10b7), Gigabit Ethernet Adapter */}, + { 0x1148, 0x4300, /* SysKonnect (1148), SK-98xx Gigabit Ethernet Server Adapter */}, + { 0x1148, 0x4320, /* SysKonnect (1148), SK-98xx V2.0 Gigabit Ethernet Adapter */}, + { 0x1148, 0x4340, /* SysKonnect (1148), SK-9Sxx 10/100/1000Base-T Server Adapter */}, + { 0x1148, 0x9000, /* SysKonnect (1148), SK-9Sxx 10/100/1000Base-T Server Adapter */}, + { 0x1148, 0x9E00, /* SysKonnect (1148), SK-9Exx 10/100/1000Base-T Adapter */}, + { 0x1186, 0x4c00, /* D-Link (1186), Gigabit Ethernet Adapter */}, + { 0x11ab, 0x4320, /* Marvell (11ab), Gigabit Ethernet Controller */}, + { 0x11ab, 0x4350, /* Marvell (11ab), Fast Ethernet Controller */}, + { 0x11ab, 0x4351, /* Marvell (11ab), Fast Ethernet Controller */}, + { 0x11ab, 0x4360, /* Marvell (11ab), Gigabit Ethernet Controller */}, + { 0x11ab, 0x4361, /* Marvell (11ab), Gigabit Ethernet Controller */}, + { 0x11ab, 0x4362, /* Marvell (11ab), Gigabit Ethernet Controller */}, + { 0x11ab, 0x4363, /* Marvell (11ab), Gigabit Ethernet Controller */}, + { 0x11ab, 0x5005, /* Marvell (11ab), Belkin */}, + { 0x1371, 0x434e, /* CNet (1371), GigaCard Network Adapter */}, + { 0x1737, 0x1032, /* Linksys (1737), Gigabit Network Adapter */}, + { 0x1737, 0x1064, /* Linksys (1737), Gigabit Network Adapter */}, + { } +}; + +#endif + +#if 0 /***************************************************************************** * - * skge_probe - find all SK-98xx adapters + * sk98lin_init_device - initialize the adapter * * Description: - * This function scans the PCI bus for SK-98xx adapters. Resources for - * each adapter are allocated and the adapter is brought into Init 1 + * This function initializes the adapter. Resources for + * the adapter are allocated and the adapter is brought into Init 1 * state. * * Returns: * 0, if everything is ok * !=0, on error */ -#if 0 -static int __init skge_probe (void) -#else -int skge_probe (struct eth_device ** ret_dev) -#endif +static int __devinit sk98lin_init_device(struct pci_dev *pdev, + const struct pci_device_id *ent) + { -#if 0 - int proc_root_initialized = 0; -#endif - int boards_found = 0; -#if 0 - int vendor_flag = SK_FALSE; -#endif + static SK_BOOL sk98lin_boot_string = SK_FALSE; + static SK_BOOL sk98lin_proc_entry = SK_FALSE; + static int sk98lin_boards_found = 0; SK_AC *pAC; DEV_NET *pNet = NULL; -#if 0 - struct proc_dir_entry *pProcFile; - struct pci_dev *pdev = NULL; - unsigned long base_address; -#else - u32 base_address; -#endif struct SK_NET_DEVICE *dev = NULL; -#if 0 - SK_BOOL DeviceFound = SK_FALSE; + int retval; +#ifdef CONFIG_PROC_FS + struct proc_dir_entry *pProcFile; #endif - SK_BOOL BootStringCount = SK_FALSE; -#if 1 - pci_dev_t devno; + int pci_using_dac; + +#if 0 /* uboot */ + retval = pci_enable_device(pdev); + if (retval) { + printk(KERN_ERR "Cannot enable PCI device, " + "aborting.\n"); + return retval; + } #endif - if (probed) + dev = NULL; + pNet = NULL; + + + /* INSERT * We have to find the power-management capabilities */ + /* Find power-management capability. */ + + pci_using_dac = 0; /* Set 32 bit DMA per default */ + /* Configure DMA attributes. */ + retval = pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL); + if (!retval) { + pci_using_dac = 1; + } else { + retval = pci_set_dma_mask(pdev, (u64) 0xffffffff); + if (retval) { + printk(KERN_ERR "No usable DMA configuration, " + "aborting.\n"); + return retval; + } + } + + + if ((dev = alloc_etherdev(sizeof(DEV_NET))) == NULL) { + printk(KERN_ERR "Unable to allocate etherdev " + "structure!\n"); return -ENODEV; - probed++; + } - if (!pci_present()) /* is PCI support present? */ + pNet = dev->priv; + pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL); + if (pNet->pAC == NULL){ + free_netdev(dev); + printk(KERN_ERR "Unable to allocate adapter " + "structure!\n"); return -ENODEV; + } -#if 0 - while((pdev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET << 8, pdev))) -#else - while((devno = pci_find_devices (supported, boards_found)) >= 0) + + /* Print message */ + if (!sk98lin_boot_string) { + /* set display flag to TRUE so that */ + /* we only display this string ONCE */ + sk98lin_boot_string = SK_TRUE; + printk("%s\n", BootString); + } + + memset(pNet->pAC, 0, sizeof(SK_AC)); + pAC = pNet->pAC; + pAC->PciDev = pdev; + pAC->PciDevId = pdev->device; + pAC->dev[0] = dev; + pAC->dev[1] = dev; + sprintf(pAC->Name, "SysKonnect SK-98xx"); + pAC->CheckQueue = SK_FALSE; + + dev->irq = pdev->irq; + retval = SkGeInitPCI(pAC); + if (retval) { + printk("SKGE: PCI setup failed: %i\n", retval); + free_netdev(dev); + return -ENODEV; + } + + SET_MODULE_OWNER(dev); + + dev->open = &SkGeOpen; + dev->stop = &SkGeClose; + dev->get_stats = &SkGeStats; + dev->set_multicast_list = &SkGeSetRxMode; + dev->set_mac_address = &SkGeSetMacAddr; + dev->do_ioctl = &SkGeIoctl; + dev->change_mtu = &SkGeChangeMtu; + dev->flags &= ~IFF_RUNNING; +#ifdef SK_POLL_CONTROLLER + dev->poll_controller = SkGeNetPoll; #endif - { + SET_NETDEV_DEV(dev, &pdev->dev); - dev = NULL; - pNet = NULL; + pAC->Index = sk98lin_boards_found; + if (SkGeBoardInit(dev, pAC)) { + free_netdev(dev); + return -ENODEV; + } else { + ProductStr(pAC); + } -#if 0 - SK_PCI_ISCOMPLIANT(vendor_flag, pdev); - if (!vendor_flag) - continue; + if (pci_using_dac) + dev->features |= NETIF_F_HIGHDMA; + + /* shifter to later moment in time... */ + if (CHIP_ID_YUKON_2(pAC)) { + dev->hard_start_xmit = &SkY2Xmit; +#ifdef CONFIG_SK98LIN_NAPI + dev->poll = &SkY2Poll; + dev->weight = 64; #endif - -/* if ((pdev->vendor != PCI_VENDOR_ID_SYSKONNECT) && - ((pdev->device != PCI_DEVICE_ID_SYSKONNECT_GE) || - (pdev->device != PCI_DEVICE_ID_SYSKONNECT_YU))){ - continue; - } -*/ -#if 0 - /* Configure DMA attributes. */ - if (pci_set_dma_mask(pdev, (u64) 0xffffffffffffffff) && - pci_set_dma_mask(pdev, (u64) 0xffffffff)) - continue; -#endif - - -#if 0 - if ((dev = init_etherdev(dev, sizeof(DEV_NET))) == NULL) { - printk(KERN_ERR "Unable to allocate etherdev " - "structure!\n"); - break; - } -#else - dev = malloc (sizeof *dev); - memset(dev, 0, sizeof(*dev)); - dev->priv = malloc(sizeof(DEV_NET)); -#endif - - if (dev->priv == NULL) { - printk(KERN_ERR "Unable to allocate adapter " - "structure!\n"); - break; - } - - pNet = dev->priv; - pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL); - if (pNet->pAC == NULL){ - kfree(dev->priv); - printk(KERN_ERR "Unable to allocate adapter " - "structure!\n"); - break; - } - - /* Print message */ - if (!BootStringCount) { - /* set display flag to TRUE so that */ - /* we only display this string ONCE */ - BootStringCount = SK_TRUE; -#ifdef SK98_INFO - printk("%s\n", BootString); -#endif - } - - memset(pNet->pAC, 0, sizeof(SK_AC)); - pAC = pNet->pAC; -#if 0 - pAC->PciDev = pdev; - pAC->PciDevId = pdev->device; - pAC->dev[0] = dev; - pAC->dev[1] = dev; -#else - pAC->PciDev = devno; - ret_dev[0] = pAC->dev[0] = dev; - ret_dev[1] = pAC->dev[1] = dev; -#endif - sprintf(pAC->Name, "SysKonnect SK-98xx"); - pAC->CheckQueue = SK_FALSE; - - pNet->Mtu = 1500; - pNet->Up = 0; -#if 0 - dev->irq = pdev->irq; - - dev->open = &SkGeOpen; - dev->stop = &SkGeClose; + } else { dev->hard_start_xmit = &SkGeXmit; - dev->get_stats = &SkGeStats; - dev->set_multicast_list = &SkGeSetRxMode; - dev->set_mac_address = &SkGeSetMacAddr; - dev->do_ioctl = &SkGeIoctl; - dev->change_mtu = &SkGeChangeMtu; - dev->flags &= ~IFF_RUNNING; -#endif - -#ifdef SK_ZEROCOPY - if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { - /* Use only if yukon hardware */ - /* SK and ZEROCOPY - fly baby... */ - dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; - } -#endif - -#if 0 - /* - * Dummy value. - */ - dev->base_addr = 42; - pci_set_master(pdev); - - pci_set_master(pdev); - base_address = pci_resource_start (pdev, 0); -#else - pci_write_config_dword(devno, - PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, - &base_address); -#endif - -#ifdef SK_BIG_ENDIAN - /* - * On big endian machines, we use the adapter's aibility of - * reading the descriptors as big endian. - */ - { - SK_U32 our2; - SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2); - our2 |= PCI_REV_DESC; - SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2); - } -#endif - - /* - * Remap the regs into kernel space. - */ -#if 0 - pAC->IoBase = (char*)ioremap(base_address, 0x4000); -#else - pAC->IoBase = (char*)pci_mem_to_phys(devno, base_address); -#endif - - if (!pAC->IoBase){ - printk(KERN_ERR "%s: Unable to map I/O register, " - "SK 98xx No. %i will be disabled.\n", - dev->name, boards_found); - kfree(dev); - break; - } - - pAC->Index = boards_found; - if (SkGeBoardInit(dev, pAC)) { - FreeResources(dev); - kfree(dev); - continue; - } - -#if 0 - memcpy((caddr_t) &dev->dev_addr, - (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6); -#else - memcpy((caddr_t) &dev->enetaddr, - (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6); -#endif - -#if 0 - /* First adapter... Create proc and print message */ - if (!DeviceFound) { - DeviceFound = SK_TRUE; - SK_MEMCPY(&SK_Root_Dir_entry, BootString, - sizeof(SK_Root_Dir_entry) - 1); - - /*Create proc (directory)*/ - if(!proc_root_initialized) { - pSkRootDir = create_proc_entry(SK_Root_Dir_entry, - S_IFDIR | S_IWUSR | S_IRUGO | S_IXUGO, proc_net); - proc_root_initialized = 1; - } - - pSkRootDir->owner = THIS_MODULE; - } - - - /* Create proc file */ - pProcFile = create_proc_entry(dev->name, - S_IFREG | S_IXUSR | S_IWGRP | S_IROTH, - pSkRootDir); - - - pProcFile->read_proc = proc_read; - pProcFile->write_proc = NULL; - pProcFile->nlink = 1; - pProcFile->size = sizeof(dev->name + 1); - pProcFile->data = (void *)pProcFile; -#endif - - pNet->PortNr = 0; - pNet->NetNr = 0; - -#ifdef SK_ZEROCOPY - if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { - /* SG and ZEROCOPY - fly baby... */ - dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; - } -#endif - - boards_found++; - - /* More then one port found */ - if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { -#if 0 - if ((dev = init_etherdev(NULL, sizeof(DEV_NET))) == 0) { - printk(KERN_ERR "Unable to allocate etherdev " - "structure!\n"); - break; - } -#else - dev = malloc (sizeof *dev); - memset(dev, 0, sizeof(*dev)); - dev->priv = malloc(sizeof(DEV_NET)); -#endif - - pAC->dev[1] = dev; - pNet = dev->priv; - pNet->PortNr = 1; - pNet->NetNr = 1; - pNet->pAC = pAC; - pNet->Mtu = 1500; - pNet->Up = 0; - -#if 0 - dev->open = &SkGeOpen; - dev->stop = &SkGeClose; - dev->hard_start_xmit = &SkGeXmit; - dev->get_stats = &SkGeStats; - dev->set_multicast_list = &SkGeSetRxMode; - dev->set_mac_address = &SkGeSetMacAddr; - dev->do_ioctl = &SkGeIoctl; - dev->change_mtu = &SkGeChangeMtu; - dev->flags &= ~IFF_RUNNING; -#endif - -#ifdef SK_ZEROCOPY - if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { - /* SG and ZEROCOPY - fly baby... */ - dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; - } -#endif - -#if 0 - pProcFile = create_proc_entry(dev->name, - S_IFREG | S_IXUSR | S_IWGRP | S_IROTH, - pSkRootDir); - - - pProcFile->read_proc = proc_read; - pProcFile->write_proc = NULL; - pProcFile->nlink = 1; - pProcFile->size = sizeof(dev->name + 1); - pProcFile->data = (void *)pProcFile; -#endif - -#if 0 - memcpy((caddr_t) &dev->dev_addr, - (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6); -#else - memcpy((caddr_t) &dev->enetaddr, - (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6); -#endif - - printk("%s: %s\n", dev->name, pAC->DeviceStr); - printk(" PrefPort:B RlmtMode:Dual Check Link State\n"); - - } - - - /* Save the hardware revision */ - pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) + - (pAC->GIni.GIPciHwRev & 0x0F); - - /* - * This is bollocks, but we need to tell the net-init - * code that it shall go for the next device. - */ -#if 0 -#ifndef MODULE - dev->base_addr = 0; -#endif +#ifdef CONFIG_SK98LIN_NAPI + dev->poll = &SkGePoll; + dev->weight = 64; #endif } - /* - * If we're at this point we're going through skge_probe() for - * the first time. Return success (0) if we've initialized 1 - * or more boards. Otherwise, return failure (-ENODEV). - */ +#ifdef NETIF_F_TSO +#ifdef USE_SK_TSO_FEATURE + if ((CHIP_ID_YUKON_2(pAC)) && + (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) { + dev->features |= NETIF_F_TSO; + } +#endif +#endif +#ifdef CONFIG_SK98LIN_ZEROCOPY + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) + dev->features |= NETIF_F_SG; +#endif +#ifdef USE_SK_TX_CHECKSUM + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) + dev->features |= NETIF_F_IP_CSUM; +#endif +#ifdef USE_SK_RX_CHECKSUM + pAC->RxPort[0].UseRxCsum = SK_TRUE; + if (pAC->GIni.GIMacsFound == 2 ) { + pAC->RxPort[1].UseRxCsum = SK_TRUE; + } +#endif - return boards_found; + /* Save the hardware revision */ + pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) + + (pAC->GIni.GIPciHwRev & 0x0F); + + /* Set driver globals */ + pAC->Pnmi.pDriverFileName = DRIVER_FILE_NAME; + pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE; + + SK_MEMSET(&(pAC->PnmiBackup), 0, sizeof(SK_PNMI_STRUCT_DATA)); + SK_MEMCPY(&(pAC->PnmiBackup), &(pAC->PnmiStruct), + sizeof(SK_PNMI_STRUCT_DATA)); + + /* Register net device */ + retval = register_netdev(dev); + if (retval) { + printk(KERN_ERR "SKGE: Could not register device.\n"); + FreeResources(dev); + free_netdev(dev); + return retval; + } + + /* Save initial device name */ + strcpy(pNet->InitialDevName, dev->name); + + /* Set network to off */ + netif_stop_queue(dev); + netif_carrier_off(dev); + + /* Print adapter specific string from vpd and config settings */ + printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr); + printk(" PrefPort:%c RlmtMode:%s\n", + 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber, + (pAC->RlmtMode==0) ? "Check Link State" : + ((pAC->RlmtMode==1) ? "Check Link State" : + ((pAC->RlmtMode==3) ? "Check Local Port" : + ((pAC->RlmtMode==7) ? "Check Segmentation" : + ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error"))))); + + SkGeYellowLED(pAC, pAC->IoBase, 1); + + memcpy((caddr_t) &dev->dev_addr, + (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6); + + /* First adapter... Create proc and print message */ +#ifdef CONFIG_PROC_FS + if (!sk98lin_proc_entry) { + sk98lin_proc_entry = SK_TRUE; + SK_MEMCPY(&SK_Root_Dir_entry, BootString, + sizeof(SK_Root_Dir_entry) - 1); + + /*Create proc (directory)*/ + if(!pSkRootDir) { + pSkRootDir = proc_mkdir(SK_Root_Dir_entry, proc_net); + if (!pSkRootDir) { + printk(KERN_WARNING "%s: Unable to create /proc/net/%s", + dev->name, SK_Root_Dir_entry); + } else { + pSkRootDir->owner = THIS_MODULE; + } + } + } + + /* Create proc file */ + if (pSkRootDir && + (pProcFile = create_proc_entry(pNet->InitialDevName, S_IRUGO, + pSkRootDir))) { + pProcFile->proc_fops = &sk_proc_fops; + pProcFile->data = dev; + } + +#endif + + pNet->PortNr = 0; + pNet->NetNr = 0; + + sk98lin_boards_found++; + pci_set_drvdata(pdev, dev); + + /* More then one port found */ + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { + if ((dev = alloc_etherdev(sizeof(DEV_NET))) == 0) { + printk(KERN_ERR "Unable to allocate etherdev " + "structure!\n"); + return -ENODEV; + } + + pAC->dev[1] = dev; + pNet = dev->priv; + pNet->PortNr = 1; + pNet->NetNr = 1; + pNet->pAC = pAC; + + if (CHIP_ID_YUKON_2(pAC)) { + dev->hard_start_xmit = &SkY2Xmit; +#ifdef CONFIG_SK98LIN_NAPI + dev->poll = &SkY2Poll; + dev->weight = 64; +#endif + } else { + dev->hard_start_xmit = &SkGeXmit; +#ifdef CONFIG_SK98LIN_NAPI + dev->poll = &SkGePoll; + dev->weight = 64; +#endif + } + dev->open = &SkGeOpen; + dev->stop = &SkGeClose; + dev->get_stats = &SkGeStats; + dev->set_multicast_list = &SkGeSetRxMode; + dev->set_mac_address = &SkGeSetMacAddr; + dev->do_ioctl = &SkGeIoctl; + dev->change_mtu = &SkGeChangeMtu; + dev->flags &= ~IFF_RUNNING; +#ifdef SK_POLL_CONTROLLER + dev->poll_controller = SkGeNetPoll; +#endif + +#ifdef NETIF_F_TSO +#ifdef USE_SK_TSO_FEATURE + if ((CHIP_ID_YUKON_2(pAC)) && + (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) { + dev->features |= NETIF_F_TSO; + } +#endif +#endif +#ifdef CONFIG_SK98LIN_ZEROCOPY + /* Don't handle if Genesis chipset */ + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) + dev->features |= NETIF_F_SG; +#endif +#ifdef USE_SK_TX_CHECKSUM + /* Don't handle if Genesis chipset */ + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) + dev->features |= NETIF_F_IP_CSUM; +#endif + + if (register_netdev(dev)) { + printk(KERN_ERR "SKGE: Could not register device.\n"); + free_netdev(dev); + pAC->dev[1] = pAC->dev[0]; + } else { + + /* Save initial device name */ + strcpy(pNet->InitialDevName, dev->name); + + /* Set network to off */ + netif_stop_queue(dev); + netif_carrier_off(dev); + + +#ifdef CONFIG_PROC_FS + if (pSkRootDir + && (pProcFile = create_proc_entry(pNet->InitialDevName, + S_IRUGO, pSkRootDir))) { + pProcFile->proc_fops = &sk_proc_fops; + pProcFile->data = dev; + } +#endif + + memcpy((caddr_t) &dev->dev_addr, + (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6); + + printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr); + printk(" PrefPort:B RlmtMode:Dual Check Link State\n"); + } + } + + pAC->Index = sk98lin_boards_found; + sk98lin_max_boards_found = sk98lin_boards_found; + return 0; +} + + + +/***************************************************************************** + * + * SkGeInitPCI - Init the PCI resources + * + * Description: + * This function initialize the PCI resources and IO + * + * Returns: N/A + * + */ +int SkGeInitPCI(SK_AC *pAC) +{ + struct SK_NET_DEVICE *dev = pAC->dev[0]; + struct pci_dev *pdev = pAC->PciDev; + int retval; + + if (pci_enable_device(pdev) != 0) { + return 1; + } + + dev->mem_start = pci_resource_start (pdev, 0); + pci_set_master(pdev); + + if (pci_request_regions(pdev, DRIVER_FILE_NAME) != 0) { + retval = 2; + goto out_disable; + } + +#if defined (SK_BIG_ENDIAN) + + /* + * On big endian machines, we use the adapter's aibility of + * reading the descriptors as big endian. + */ + if (CHIP_ID_YUKON_2(pAC)) + { + SK_U32 our2; + SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2); + our2 |= PCI_REV_DESC; + SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2); + } + else + { + SK_U32 our2; + SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2); + our2 |= PCI_REV_DESC; + SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2); + } +#else + + { + SK_U32 our2; + SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2); + our2 &= ~PCI_REV_DESC; + SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2); + } + + +#endif + + /* + * Remap the regs into kernel space. + */ + pAC->IoBase = (char*)ioremap_nocache(dev->mem_start, 0x4000); + + if (!pAC->IoBase){ + retval = 3; + goto out_release; + } + + return 0; + + out_release: + pci_release_regions(pdev); + out_disable: + pci_disable_device(pdev); + return retval; +} + +#else +/***************************************************************************** + * + * skge_probe - find all SK-98xx adapters + * + * Description: + * This function scans the PCI bus for SK-98xx adapters. Resources for + * each adapter are allocated and the adapter is brought into Init 1 + * state. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int probed __initdata = 0; + +int skge_probe (struct eth_device ** ret_dev) +{ + int boards_found = 0; + SK_AC *pAC; + DEV_NET *pNet = NULL; + u32 base_address; + struct SK_NET_DEVICE *dev = NULL; + SK_BOOL BootStringCount = SK_FALSE; + pci_dev_t devno; + + if (probed) + return -ENODEV; + probed++; + + if (!pci_present()) /* is PCI support present? */ + return -ENODEV; + + while(1) + { + if((devno = pci_find_devices (supported, boards_found)) < 0) { + break; + } + + + dev = NULL; + pNet = NULL; + + + dev = malloc (sizeof (struct SK_NET_DEVICE)); + memset(dev, 0, sizeof(struct SK_NET_DEVICE)); + dev->priv = malloc(sizeof(DEV_NET)); + + if (dev->priv == NULL) { + printk(KERN_ERR "Unable to allocate adapter " + "structure!\n"); + break; + } + + pNet = dev->priv; + pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL); + if (pNet->pAC == NULL){ + kfree(dev->priv); + printf("kfree: dev->priv1=0x%x\n",dev->priv); + printk(KERN_ERR "Unable to allocate adapter " + "structure!\n"); + + #if 1 /* Marvell - uboot */ + return -ENODEV; + #endif + /*break;*/ + } + + /* Print message */ + if (!BootStringCount) { + /* set display flag to TRUE so that */ + /* we only display this string ONCE */ + BootStringCount = SK_TRUE; +#ifdef SK98_INFO + printk("%s\n", BootString); +#endif + } + + memset(pNet->pAC, 0, sizeof(SK_AC)); + pAC = pNet->pAC; + pAC->PciDev = devno; + ret_dev[boards_found] = pAC->dev[0] = dev; + sprintf(pAC->Name, "SysKonnect SK-98xx"); + pAC->CheckQueue = SK_FALSE; + + pNet->Mtu = 1500; + pNet->Up = 0; + +#ifdef SK_ZEROCOPY + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + /* Use only if yukon hardware */ + /* SK and ZEROCOPY - fly baby... */ + dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; + } +#endif + + pci_write_config_dword(devno, + PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, + &base_address); + + + /* + * Remap the regs into kernel space. + */ + pAC->IoBase =((char*)pci_mem_to_phys(devno, base_address)); + + #if 1/* Marvell - uboot : make it aligned */ + pAC->IoBase = (SK_IOC)((unsigned int)pAC->IoBase & 0xFFFFFFF0); + #endif + + + + if (!pAC->IoBase){ + printk(KERN_ERR "%s: Unable to map I/O register, " + "SK 98xx No. %i will be disabled.\n", + dev->name, boards_found); + kfree(dev); + printf("kfree: dev3=0x%x\n",dev); + break; + } + + + + pAC->Index = boards_found; + if (SkGeBoardInit(dev, pAC)) { + FreeResources(dev); + kfree(dev); + printf("kfree: dev4=0x%x\n",dev); + continue; + } + + + memcpy((caddr_t) &dev->enetaddr, + (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6); + + + + + pNet->PortNr = 0; + pNet->NetNr = 0; + + boards_found++; + + /* More then one port found */ + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { + printk(" NEVER TESTED \n"); + dev = malloc (sizeof(struct SK_NET_DEVICE)); + memcpy(dev, pAC->dev[0], sizeof(struct SK_NET_DEVICE)); + dev->priv = malloc(sizeof(DEV_NET)); + memcpy(dev->priv, pAC->dev[0]->priv, sizeof(DEV_NET)); + + ret_dev[1] = pAC->dev[1] = dev; + boards_found++; + + pNet = dev->priv; + pNet->PortNr = 1; + pNet->NetNr = 1; + pNet->pAC = pAC; + pNet->Mtu = 1500; + pNet->Up = 0; + + memcpy((caddr_t) &dev->enetaddr, + (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6); + + printk("%s: %s\n", dev->name, pAC->DeviceStr); + printk(" PrefPort:B RlmtMode:Dual Check Link State\n"); + + } + + + + + + /* Save the hardware revision */ + pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) + + (pAC->GIni.GIPciHwRev & 0x0F); +#if 0 + + printk(" PrefPort:%c RlmtMode:%s\n", + 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber, + (pAC->RlmtMode==0) ? "Check Link State" : + ((pAC->RlmtMode==1) ? "Check Link State" : + ((pAC->RlmtMode==3) ? "Check Local Port" : + ((pAC->RlmtMode==7) ? "Check Segmentation" : + ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error"))))); + + SkGeYellowLED(pAC, pAC->IoBase, 1); +#endif + +#if defined (SK_BIG_ENDIAN) + + /* + * On big endian machines, we use the adapter's aibility of + * reading the descriptors as big endian. + */ + if (CHIP_ID_YUKON_2(pAC)) + { + SK_U32 our2; + SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2); + our2 |= PCI_REV_DESC; + SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2); + } + else + { + SK_U32 our2; + SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2); + our2 |= PCI_REV_DESC; + SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2); + } +#else + + { + SK_U32 our2; + SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2); + our2 &= ~PCI_REV_DESC; + SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2); + } + + +#endif + + + } + + + + /* + * If we're at this point we're going through skge_probe() for + * the first time. Return success (0) if we've initialized 1 + * or more boards. Otherwise, return failure (-ENODEV). + */ + + return boards_found; } /* skge_probe */ +#endif + +#ifdef Y2_RECOVERY +/***************************************************************************** + * + * SkGeHandleKernelTimer - Handle the kernel timer requests + * + * Description: + * If the requested time interval for the timer has elapsed, + * this function checks the link state. + * + * Returns: N/A + * + */ +static void SkGeHandleKernelTimer( +unsigned long ptr) /* holds the pointer to adapter control context */ +{ + DEV_NET *pNet = (DEV_NET*) ptr; + SkGeCheckTimer(pNet); +} + +/***************************************************************************** + * + * sk98lin_check_timer - Resume the the card + * + * Description: + * This function checks the kernel timer + * + * Returns: N/A + * + */ +void SkGeCheckTimer( +DEV_NET *pNet) /* holds the pointer to adapter control context */ +{ + SK_AC *pAC = pNet->pAC; + SK_BOOL StartTimer = SK_TRUE; + + if (pNet->InRecover) + return; + if (pNet->TimerExpired) + return; + pNet->TimerExpired = SK_TRUE; + +#define TXPORT pAC->TxPort[pNet->PortNr][TX_PRIO_LOW] +#define RXPORT pAC->RxPort[pNet->PortNr] + + if ( (CHIP_ID_YUKON_2(pAC)) && + (netif_running(pAC->dev[pNet->PortNr]))) { + +#ifdef Y2_RX_CHECK + if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) { + /* Checks the RX path */ + CheckRxPath(pNet); + } +#endif + + /* Checkthe transmitter */ + if (!(IS_Q_EMPTY(&TXPORT.TxAQ_working))) { + if (TXPORT.LastDone != TXPORT.TxALET.Done) { + TXPORT.LastDone = TXPORT.TxALET.Done; + pNet->TransmitTimeoutTimer = 0; + } else { + pNet->TransmitTimeoutTimer++; + if (pNet->TransmitTimeoutTimer >= 10) { + pNet->TransmitTimeoutTimer = 0; +#ifdef CHECK_TRANSMIT_TIMEOUT + StartTimer = SK_FALSE; + SkLocalEventQueue(pAC, SKGE_DRV, + SK_DRV_RECOVER,pNet->PortNr,-1,SK_FALSE); +#endif + } + } + } + +#ifdef CHECK_TRANSMIT_TIMEOUT +// if (!timer_pending(&pNet->KernelTimer)) { +#if 0 //u-boot + pNet->KernelTimer.expires = jiffies + (HZ/4); /* 100ms */ + add_timer(&pNet->KernelTimer); +#endif + pNet->TimerExpired = SK_FALSE; + +// } +#endif + } +} + + +/***************************************************************************** +* +* CheckRXCounters - Checks the the statistics for RX path hang +* +* Description: +* This function is called periodical by a timer. +* +* Notes: +* +* Function Parameters: +* +* Returns: +* Traffic status +* +*/ +static SK_BOOL CheckRXCounters( +DEV_NET *pNet) /* holds the pointer to adapter control context */ +{ +#if 0 // u-boot + SK_AC *pAC = pNet->pAC; +#endif + SK_BOOL bStatus = SK_FALSE; + + /* Variable used to store the MAC RX FIFO RP, RPLev*/ + SK_U32 MACFifoRP = 0; + SK_U32 MACFifoRLev = 0; + + /* Variable used to store the PCI RX FIFO RP, RPLev*/ + SK_U32 RXFifoRP = 0; + SK_U8 RXFifoRLev = 0; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("==> CheckRXCounters()\n")); + + /*Check if statistic counters hangs*/ +#if 0 // u-boot + if (pNet->LastJiffies == pAC->dev[pNet->PortNr]->last_rx) { + /* Now read the values of read pointer/level from MAC RX FIFO again */ + SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RP), &MACFifoRP); + SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RLEV), &MACFifoRLev); + + /* Now read the values of read pointer/level from RX FIFO again */ + SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RP), &RXFifoRP); + SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RL), &RXFifoRLev); + + /* Check if the MAC RX hang */ + if ((MACFifoRP == pNet->PreviousMACFifoRP) && + (pNet->PreviousMACFifoRP != 0) && + (MACFifoRLev >= pNet->PreviousMACFifoRLev)){ + bStatus = SK_TRUE; + } + + /* Check if the PCI RX hang */ + if ((RXFifoRP == pNet->PreviousRXFifoRP) && + (pNet->PreviousRXFifoRP != 0) && + (RXFifoRLev >= pNet->PreviousRXFifoRLev)){ + /*Set the flag to indicate that the RX FIFO hangs*/ + bStatus = SK_TRUE; + } + } + + /* Store now the values of counters for next check */ + pNet->LastJiffies = pAC->dev[pNet->PortNr]->last_rx; +#endif + + + /* Store the values of read pointer/level from MAC RX FIFO for next test */ + pNet->PreviousMACFifoRP = MACFifoRP; + pNet->PreviousMACFifoRLev = MACFifoRLev; + + /* Store the values of read pointer/level from RX FIFO for next test */ + pNet->PreviousRXFifoRP = RXFifoRP; + pNet->PreviousRXFifoRLev = RXFifoRLev; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("<== CheckRXCounters()\n")); + + return bStatus; +} + +/***************************************************************************** +* +* CheckRxPath - Checks if the RX path +* +* Description: +* This function is called periodical by a timer. +* +* Notes: +* +* Function Parameters: +* +* Returns: +* None. +* +*/ +static void CheckRxPath( +DEV_NET *pNet) /* holds the pointer to adapter control context */ +{ + unsigned long Flags; /* for the spin locks */ + /* Initialize the pAC structure.*/ + SK_AC *pAC = pNet->pAC; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("==> CheckRxPath()\n")); + + /*If the statistics are not changed then could be an RX problem */ + if (CheckRXCounters(pNet)){ + /* + * First we try the simple solution by resetting the Level Timer + */ + + /* Stop Level Timer of Status BMU */ + SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_STOP); + + /* Start Level Timer of Status BMU */ + SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_START); + + if (!CheckRXCounters(pNet)) { + return; + } + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + SkLocalEventQueue(pAC, SKGE_DRV, + SK_DRV_RECOVER,pNet->PortNr,-1,SK_TRUE); + + /* Reset the fifo counters */ + pNet->PreviousMACFifoRP = 0; + pNet->PreviousMACFifoRLev = 0; + pNet->PreviousRXFifoRP = 0; + pNet->PreviousRXFifoRLev = 0; + + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("<== CheckRxPath()\n")); +} + + + +#endif + + +#ifdef CONFIG_PM +/***************************************************************************** + * + * sk98lin_resume - Resume the the card + * + * Description: + * This function resumes the card into the D0 state + * + * Returns: N/A + * + */ +static int sk98lin_resume( +struct pci_dev *pdev) /* the device that is to resume */ +{ + struct net_device *dev = pci_get_drvdata(pdev); + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + SK_U16 PmCtlSts; + + /* Set the power state to D0 */ + pci_set_power_state(pdev, 0); + pci_restore_state(pdev, pAC->PciState); + + pci_enable_device(pdev); + pci_set_master(pdev); + + pci_enable_wake(pdev, 3, 0); + pci_enable_wake(pdev, 4, 0); + + SK_OUT8(pAC->IoBase, RX_GMF_CTRL_T, (SK_U8)GMF_RST_CLR); + + /* Set the adapter power state to D0 */ + SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts); + PmCtlSts &= ~(PCI_PM_STATE_D3); /* reset all DState bits */ + PmCtlSts |= PCI_PM_STATE_D0; + SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PmCtlSts); + + /* Reinit the adapter and start the port again */ + pAC->BoardLevel = SK_INIT_DATA; + SkDrvLeaveDiagMode(pAC); + + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) || + (CHIP_ID_YUKON_2(pAC)) ) { + pAC->StatusLETable.Done = 0; + pAC->StatusLETable.Put = 0; + pAC->StatusLETable.HwPut = 0; + SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable); + } + + return 0; +} + +/***************************************************************************** + * + * sk98lin_suspend - Suspend the card + * + * Description: + * This function suspends the card into a defined state + * + * Returns: N/A + * + */ +static int sk98lin_suspend( +struct pci_dev *pdev, /* pointer to the device that is to suspend */ +u32 state) /* what power state is desired by Linux? */ +{ + struct net_device *dev = pci_get_drvdata(pdev); + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + SK_U16 PciPMControlStatus; + SK_U16 PciPMCapabilities; + SK_MAC_ADDR MacAddr; + int i; + + /* GEnesis and first yukon revs do not support power management */ + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + if (pAC->GIni.GIChipRev == 0) { + return 0; /* power management not supported */ + } + } + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + return 0; /* not supported for this chipset */ + } + + if (pAC->WolInfo.ConfiguredWolOptions == 0) { + return 0; /* WOL possible, but disabled via ethtool */ + } + + if(netif_running(dev)) { + netif_stop_queue(dev); /* stop device if running */ + } + + /* read the PM control/status register from the PCI config space */ + SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CTL_STS), &PciPMControlStatus); + + /* read the power management capabilities from the config space */ + SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CAP_REG), &PciPMCapabilities); + + /* Enable WakeUp with Magic Packet - get MAC address from adapter */ + for (i = 0; i < SK_MAC_ADDR_LEN; i++) { + /* virtual address: will be used for data */ + SK_IN8(pAC->IoBase, (B2_MAC_1 + i), &MacAddr.a[i]); + } + + SkDrvEnterDiagMode(pAC); + SkEnableWOMagicPacket(pAC, pAC->IoBase, MacAddr); + + pci_enable_wake(pdev, 3, 1); + pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */ + pci_save_state(pdev, pAC->PciState); + pci_disable_device(pdev); // NEW + pci_set_power_state(pdev, state); /* set the state */ + + return 0; +} + + +/****************************************************************************** + * + * SkEnableWOMagicPacket - Enable Wake on Magic Packet on the adapter + * + * Context: + * init, pageable + * the adapter should be de-initialized before calling this function + * + * Returns: + * nothing + */ + +static void SkEnableWOMagicPacket( +SK_AC *pAC, /* Adapter Control Context */ +SK_IOC IoC, /* I/O control context */ +SK_MAC_ADDR MacAddr) /* MacAddr expected in magic packet */ +{ + SK_U16 Word; + SK_U32 DWord; + int i; + int HwPortIndex; + int Port = 0; + + /* use Port 0 as long as we do not have any dual port cards which support WOL */ + HwPortIndex = 0; + DWord = 0; + + SK_OUT16(IoC, 0x0004, 0x0002); /* clear S/W Reset */ + SK_OUT16(IoC, 0x0f10, 0x0002); /* clear Link Reset */ + + /* + * PHY Configuration: + * Autonegotioation is enalbed, advertise 10 HD, 10 FD, + * 100 HD, and 100 FD. + */ + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) || + (pAC->GIni.GIChipId == CHIP_ID_YUKON) || + (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) || + (CHIP_ID_YUKON_2(pAC)) ) { + + SK_OUT8(IoC, 0x0007, 0xa9); /* enable VAUX */ + + /* WA code for COMA mode */ + /* Only for yukon plus based chipsets rev A3 */ + if (pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) { + SK_IN32(IoC, B2_GP_IO, &DWord); + DWord |= GP_DIR_9; /* set to output */ + DWord &= ~GP_IO_9; /* clear PHY reset (active high) */ + SK_OUT32(IoC, B2_GP_IO, DWord); /* clear PHY reset */ + } + + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) || + (pAC->GIni.GIChipId == CHIP_ID_YUKON)) { + SK_OUT32(IoC, 0x0f04, 0x01f04001); /* set PHY reset */ + SK_OUT32(IoC, 0x0f04, 0x01f04002); /* clear PHY reset */ + } else { + SK_OUT8(IoC, 0x0f04, 0x02); /* clear PHY reset */ + } + + SK_OUT8(IoC, 0x0f00, 0x02); /* clear MAC reset */ + SkGmPhyWrite(pAC, IoC, Port, 4, 0x01e1); /* advertise 10/100 HD/FD */ + SkGmPhyWrite(pAC, IoC, Port, 9, 0x0000); /* do not advertise 1000 HD/FD */ + SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300); /* 100 MBit, disable Autoneg */ + } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) { + SK_OUT8(IoC, 0x0007, 0xa9); /* enable VAUX */ + SK_OUT8(IoC, 0x0f04, 0x02); /* clear PHY reset */ + SK_OUT8(IoC, 0x0f00, 0x02); /* clear MAC reset */ + SkGmPhyWrite(pAC, IoC, Port, 16, 0x0130); /* Enable Automatic Crossover */ + SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300); /* 100 MBit, disable Autoneg */ + } + + + /* + * MAC Configuration: + * Set the MAC to 100 HD and enable the auto update features + * for Speed, Flow Control and Duplex Mode. + * If autonegotiation completes successfully the + * MAC takes the link parameters from the PHY. + * If the link partner doesn't support autonegotiation + * the MAC can receive magic packets if the link partner + * uses 100 HD. + */ + SK_OUT16(IoC, 0x2804, 0x3832); + + + /* + * Set Up Magic Packet parameters + */ + for (i = 0; i < 6; i+=2) { /* set up magic packet MAC address */ + SK_IN16(IoC, 0x100 + i, &Word); + SK_OUT16(IoC, 0xf24 + i, Word); + } + + SK_OUT16(IoC, 0x0f20, 0x0208); /* enable PME on magic packet */ + /* and on wake up frame */ + + /* + * Set up PME generation + */ + /* set PME legacy mode */ + /* Only for PCI express based chipsets */ + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) || + (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) || + (CHIP_ID_YUKON_2(pAC))) { + SkPciReadCfgDWord(pAC, 0x40, &DWord); + DWord |= 0x8000; + SkPciWriteCfgDWord(pAC, 0x40, DWord); + } + + SK_OUT8(IoC, RX_GMF_CTRL_T, (SK_U8)GMF_RST_SET); + + /* clear PME status and switch adapter to DState */ + SkPciReadCfgWord(pAC, 0x4c, &Word); + Word |= 0x103; + SkPciWriteCfgWord(pAC, 0x4c, Word); +} /* SkEnableWOMagicPacket */ +#endif + /***************************************************************************** * @@ -864,7 +1510,7 @@ int skge_probe (struct eth_device ** ret_dev) * frees the desriptor ring. * * Returns: N/A - * + * */ static void FreeResources(struct SK_NET_DEVICE *dev) { @@ -876,7 +1522,11 @@ SK_AC *pAC; pNet = (DEV_NET*) dev->priv; pAC = pNet->pAC; AllocFlag = pAC->AllocFlag; -#if 0 +#if 0 /* uboot */ + if (pAC->PciDev) { + pci_release_regions(pAC->PciDev); + } + if (AllocFlag & SK_ALLOC_IRQ) { free_irq(dev->irq, dev); } @@ -884,43 +1534,40 @@ SK_AC *pAC; iounmap(pAC->IoBase); } #endif - if (pAC->pDescrMem) { + +#if 0 /* Marvell- uboot */ + + if (CHIP_ID_YUKON_2(pAC)) { + SkY2FreeResources(pAC); + } else { BoardFreeMem(pAC); } + +#else + if (CHIP_ID_YUKON_2(pAC)) { + SkY2FreeResources(pAC); + } else { + BoardFreeMem(pAC); } - +#endif + } + } /* FreeResources */ -#if 0 +#if 0 /* uboot */ MODULE_AUTHOR("Mirko Lindner "); MODULE_DESCRIPTION("SysKonnect SK-NET Gigabit Ethernet SK-98xx driver"); MODULE_LICENSE("GPL"); -MODULE_PARM(Speed_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(Speed_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(AutoNeg_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(AutoNeg_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(DupCap_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(DupCap_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(FlowCtrl_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(FlowCtrl_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(Role_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(Role_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(PrefPort, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -MODULE_PARM(RlmtMode, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); -/* not used, just there because every driver should have them: */ -MODULE_PARM(options, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i"); -MODULE_PARM(debug, "i"); #endif - #ifdef LINK_SPEED_A -static char *Speed_A[SK_MAX_CARD_PARAM] = LINK_SPEED_A; +static char *Speed_A[SK_MAX_CARD_PARAM] = LINK_SPEED; #else static char *Speed_A[SK_MAX_CARD_PARAM] = {"", }; #endif #ifdef LINK_SPEED_B -static char *Speed_B[SK_MAX_CARD_PARAM] = LINK_SPEED_B; +static char *Speed_B[SK_MAX_CARD_PARAM] = LINK_SPEED; #else static char *Speed_B[SK_MAX_CARD_PARAM] = {"", }; #endif @@ -973,6 +1620,12 @@ static char *Role_B[SK_MAX_CARD_PARAM] = ROLE_B; static char *Role_B[SK_MAX_CARD_PARAM] = {"", }; #endif +#ifdef CON_TYPE +static char *ConType[SK_MAX_CARD_PARAM] = CON_TYPE; +#else +static char *ConType[SK_MAX_CARD_PARAM] = {"", }; +#endif + #ifdef PREF_PORT static char *PrefPort[SK_MAX_CARD_PARAM] = PREF_PORT; #else @@ -985,42 +1638,16 @@ static char *RlmtMode[SK_MAX_CARD_PARAM] = RLMT_MODE; static char *RlmtMode[SK_MAX_CARD_PARAM] = {"", }; #endif +static int IntsPerSec[SK_MAX_CARD_PARAM]; +static char *Moderation[SK_MAX_CARD_PARAM]; +static char *ModerationMask[SK_MAX_CARD_PARAM]; + +static char *LowLatency[SK_MAX_CARD_PARAM]; + #if 0 -static int debug = 0; /* not used */ -static int options[SK_MAX_CARD_PARAM] = {0, }; /* not used */ - - /***************************************************************************** * - * skge_init_module - module initialization function - * - * Description: - * Very simple, only call skge_probe and return approriate result. - * - * Returns: - * 0, if everything is ok - * !=0, on error - */ -static int __init skge_init_module(void) -{ - int cards; - SkGeRootDev = NULL; - - /* just to avoid warnings ... */ - debug = 0; - options[0] = 0; - - cards = skge_probe(); - if (cards == 0) { - printk("sk98lin: No adapter found.\n"); - } - return cards ? 0 : -ENODEV; -} /* skge_init_module */ - - -/***************************************************************************** - * - * skge_cleanup_module - module unload function + * sk98lin_remove_device - device deinit function * * Description: * Disable adapter if it is still running, free resources, @@ -1028,73 +1655,84 @@ static int __init skge_init_module(void) * * Returns: N/A */ -static void __exit skge_cleanup_module(void) + +static void sk98lin_remove_device(struct pci_dev *pdev) { DEV_NET *pNet; SK_AC *pAC; struct SK_NET_DEVICE *next; unsigned long Flags; -SK_EVPARA EvPara; +struct net_device *dev = pci_get_drvdata(pdev); - while (SkGeRootDev) { - pNet = (DEV_NET*) SkGeRootDev->priv; - pAC = pNet->pAC; - next = pAC->Next; - netif_stop_queue(SkGeRootDev); - SkGeYellowLED(pAC, pAC->IoBase, 0); + /* Device not available. Return. */ + if (!dev) + return; - if(pAC->BoardLevel == 2) { - /* board is still alive */ - spin_lock_irqsave(&pAC->SlowPathLock, Flags); - EvPara.Para32[0] = 0; - EvPara.Para32[1] = -1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); - EvPara.Para32[0] = 1; - EvPara.Para32[1] = -1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); - SkEventDispatcher(pAC, pAC->IoBase); - /* disable interrupts */ - SK_OUT32(pAC->IoBase, B0_IMSK, 0); - SkGeDeInit(pAC, pAC->IoBase); - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - pAC->BoardLevel = 0; - /* We do NOT check here, if IRQ was pending, of course*/ - } + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + next = pAC->Next; - if(pAC->BoardLevel == 1) { - /* board is still alive */ - SkGeDeInit(pAC, pAC->IoBase); - pAC->BoardLevel = 0; - } + netif_stop_queue(dev); + SkGeYellowLED(pAC, pAC->IoBase, 0); - if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){ - unregister_netdev(pAC->dev[1]); - kfree(pAC->dev[1]); - } + if(pAC->BoardLevel == SK_INIT_RUN) { + /* board is still alive */ + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, + 0, -1, SK_FALSE); + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, + 1, -1, SK_TRUE); - FreeResources(SkGeRootDev); - - SkGeRootDev->get_stats = NULL; - /* - * otherwise unregister_netdev calls get_stats with - * invalid IO ... :-( - */ - unregister_netdev(SkGeRootDev); - kfree(SkGeRootDev); - kfree(pAC); - SkGeRootDev = next; + /* disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + SkGeDeInit(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + pAC->BoardLevel = SK_INIT_DATA; + /* We do NOT check here, if IRQ was pending, of course*/ } - /* clear proc-dir */ - remove_proc_entry(pSkRootDir->name, proc_net); + if(pAC->BoardLevel == SK_INIT_IO) { + /* board is still alive */ + SkGeDeInit(pAC, pAC->IoBase); + pAC->BoardLevel = SK_INIT_DATA; + } -} /* skge_cleanup_module */ + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){ + unregister_netdev(pAC->dev[1]); + free_netdev(pAC->dev[1]); + } -module_init(skge_init_module); -module_exit(skge_cleanup_module); + FreeResources(dev); + +#ifdef CONFIG_PROC_FS + /* Remove the sk98lin procfs device entries */ + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){ + remove_proc_entry(pAC->dev[1]->name, pSkRootDir); + } + remove_proc_entry(pNet->InitialDevName, pSkRootDir); #endif + dev->get_stats = NULL; + /* + * otherwise unregister_netdev calls get_stats with + * invalid IO ... :-( + */ + unregister_netdev(dev); + free_netdev(dev); + kfree(pAC); + sk98lin_max_boards_found--; + +#ifdef CONFIG_PROC_FS + /* Remove all Proc entries if last device */ + if (sk98lin_max_boards_found == 0) { + /* clear proc-dir */ + remove_proc_entry(pSkRootDir->name, proc_net); + } +#endif + +} +#endif /***************************************************************************** * @@ -1115,7 +1753,7 @@ short i; unsigned long Flags; char *DescrString = "sk98lin: Driver for Linux"; /* this is given to PNMI */ char *VerStr = VER_STRING; -#if 0 +#if 0 /* uboot */ int Ret; /* return code of request_irq */ #endif SK_BOOL DualNet; @@ -1134,121 +1772,173 @@ SK_BOOL DualNet; spin_lock_init(&pAC->TxPort[i][0].TxDesRingLock); spin_lock_init(&pAC->RxPort[i].RxDesRingLock); } + + spin_lock_init(&pAC->InitLock); /* Init lock */ spin_lock_init(&pAC->SlowPathLock); + spin_lock_init(&pAC->TxQueueLock); /* for Yukon2 chipsets */ + spin_lock_init(&pAC->SetPutIndexLock); /* for Yukon2 chipsets */ /* level 0 init common modules here */ - + spin_lock_irqsave(&pAC->SlowPathLock, Flags); /* Does a RESET on board ...*/ - if (SkGeInit(pAC, pAC->IoBase, 0) != 0) { + if (SkGeInit(pAC, pAC->IoBase, SK_INIT_DATA) != 0) { printk("HWInit (0) failed.\n"); spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); return(-EAGAIN); } - SkI2cInit( pAC, pAC->IoBase, 0); - SkEventInit(pAC, pAC->IoBase, 0); - SkPnmiInit( pAC, pAC->IoBase, 0); - SkAddrInit( pAC, pAC->IoBase, 0); - SkRlmtInit( pAC, pAC->IoBase, 0); - SkTimerInit(pAC, pAC->IoBase, 0); + SkI2cInit( pAC, pAC->IoBase, SK_INIT_DATA); + SkEventInit(pAC, pAC->IoBase, SK_INIT_DATA); +#ifdef SK_PNMI_SUPPORT + SkPnmiInit( pAC, pAC->IoBase, SK_INIT_DATA); +#endif + SkAddrInit( pAC, pAC->IoBase, SK_INIT_DATA); + SkRlmtInit( pAC, pAC->IoBase, SK_INIT_DATA); + SkTimerInit(pAC, pAC->IoBase, SK_INIT_DATA); - pAC->BoardLevel = 0; - pAC->RxBufSize = ETH_BUF_SIZE; + pAC->BoardLevel = SK_INIT_DATA; + pAC->RxPort[0].RxBufSize = ETH_BUF_SIZE; + pAC->RxPort[1].RxBufSize = ETH_BUF_SIZE; SK_PNMI_SET_DRIVER_DESCR(pAC, DescrString); SK_PNMI_SET_DRIVER_VER(pAC, VerStr); - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - /* level 1 init common modules here (HW init) */ - spin_lock_irqsave(&pAC->SlowPathLock, Flags); - if (SkGeInit(pAC, pAC->IoBase, 1) != 0) { - printk("HWInit (1) failed.\n"); + if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) { + printk("sk98lin: HWInit (1) failed.\n"); spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); return(-EAGAIN); } - SkI2cInit( pAC, pAC->IoBase, 1); - SkEventInit(pAC, pAC->IoBase, 1); - SkPnmiInit( pAC, pAC->IoBase, 1); - SkAddrInit( pAC, pAC->IoBase, 1); - SkRlmtInit( pAC, pAC->IoBase, 1); - SkTimerInit(pAC, pAC->IoBase, 1); + SkI2cInit( pAC, pAC->IoBase, SK_INIT_IO); + SkEventInit(pAC, pAC->IoBase, SK_INIT_IO); +#ifdef SK_PNMI_SUPPORT + SkPnmiInit( pAC, pAC->IoBase, SK_INIT_IO); +#endif + SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO); + SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO); + SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO); +#ifdef Y2_RECOVERY + /* mark entries invalid */ + pAC->LastPort = 3; + pAC->LastOpc = 0xFF; +#endif + + /* Set chipset type support */ + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON) || + (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) || + (pAC->GIni.GIChipId == CHIP_ID_YUKON_LP)) { + pAC->ChipsetType = 1; /* Yukon chipset (descriptor logic) */ + } else if (CHIP_ID_YUKON_2(pAC)) { + pAC->ChipsetType = 2; /* Yukon2 chipset (list logic) */ + } else { + pAC->ChipsetType = 0; /* Genesis chipset (descriptor logic) */ + } + + /* wake on lan support */ + pAC->WolInfo.SupportedWolOptions = 0; +#if defined (ETHTOOL_GWOL) && defined (ETHTOOL_SWOL) + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) { + pAC->WolInfo.SupportedWolOptions = WAKE_MAGIC; + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + if (pAC->GIni.GIChipRev == 0) { + pAC->WolInfo.SupportedWolOptions = 0; + } + } + } +#endif + pAC->WolInfo.ConfiguredWolOptions = pAC->WolInfo.SupportedWolOptions; GetConfiguration(pAC); if (pAC->RlmtNets == 2) { - pAC->GIni.GIPortUsage = SK_MUL_LINK; + pAC->GIni.GP[0].PPortUsage = SK_MUL_LINK; + pAC->GIni.GP[1].PPortUsage = SK_MUL_LINK; } - pAC->BoardLevel = 1; + pAC->BoardLevel = SK_INIT_IO; spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); -#if 0 - if (pAC->GIni.GIMacsFound == 2) { - Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, pAC->Name, dev); - } else if (pAC->GIni.GIMacsFound == 1) { - Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, - pAC->Name, dev); - } else { - printk(KERN_WARNING "%s: Illegal number of ports: %d\n", - dev->name, pAC->GIni.GIMacsFound); - return -EAGAIN; + if (!CHIP_ID_YUKON_2(pAC)) { +#ifdef CONFIG_SK98LIN_NAPI + dev->poll = &SkGePoll; + dev->weight = 64; +#endif +#if 0 /* uboot */ + if (pAC->GIni.GIMacsFound == 2) { + Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, dev->name, dev); + } else if (pAC->GIni.GIMacsFound == 1) { + Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, dev->name, dev); + } else { + printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n", + pAC->GIni.GIMacsFound); + return -EAGAIN; + } + } + else { + Ret = request_irq(dev->irq, SkY2Isr, SA_SHIRQ, dev->name, dev); } if (Ret) { - printk(KERN_WARNING "%s: Requested IRQ %d is busy.\n", - dev->name, dev->irq); + printk(KERN_WARNING "sk98lin: Requested IRQ %d is busy.\n", + dev->irq); return -EAGAIN; } #endif - pAC->AllocFlag |= SK_ALLOC_IRQ; - - /* Alloc memory for this board (Mem for RxD/TxD) : */ - if(!BoardAllocMem(pAC)) { - printk("No memory for descriptor rings.\n"); - return(-EAGAIN); } + + pAC->AllocFlag |= SK_ALLOC_IRQ; + + /* + ** Alloc descriptor/LETable memory for this board (both RxD/TxD) + */ + if (CHIP_ID_YUKON_2(pAC)) { + if (!SkY2AllocateResources(pAC)) { + printk("No memory for Yukon2 settings\n"); + return(-EAGAIN); + } + } else { + if(!BoardAllocMem(pAC)) { + printk("No memory for descriptor rings.\n"); + return(-EAGAIN); + } + } + +#ifdef SK_USE_CSUM SkCsSetReceiveFlags(pAC, SKCS_PROTO_IP | SKCS_PROTO_TCP | SKCS_PROTO_UDP, &pAC->CsOfs1, &pAC->CsOfs2, 0); pAC->CsOfs = (pAC->CsOfs2 << 16) | pAC->CsOfs1; +#endif + /* + ** Function BoardInitMem() for Yukon dependent settings... + */ BoardInitMem(pAC); -#if 0 - SetQueueSizes(pAC); -#else /* tschilling: New common function with minimum size check. */ DualNet = SK_FALSE; if (pAC->RlmtNets == 2) { DualNet = SK_TRUE; } - + if (SkGeInitAssignRamToQueues( pAC, pAC->ActivePort, DualNet)) { +#if 0 /* Marvell - uboot */ BoardFreeMem(pAC); - printk("SkGeInitAssignRamToQueues failed.\n"); +#else + if (CHIP_ID_YUKON_2(pAC)) { + SkY2FreeResources(pAC); + } else { + BoardFreeMem(pAC); + } +#endif + + + + printk("sk98lin: SkGeInitAssignRamToQueues failed.\n"); return(-EAGAIN); } -#endif - - /* Print adapter specific string from vpd */ - ProductStr(pAC); -#ifdef SK98_INFO - printk("%s: %s\n", dev->name, pAC->DeviceStr); - - /* Print configuration settings */ - printk(" PrefPort:%c RlmtMode:%s\n", - 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber, - (pAC->RlmtMode==0) ? "Check Link State" : - ((pAC->RlmtMode==1) ? "Check Link State" : - ((pAC->RlmtMode==3) ? "Check Local Port" : - ((pAC->RlmtMode==7) ? "Check Segmentation" : - ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error"))))); -#endif - - SkGeYellowLED(pAC, pAC->IoBase, 1); /* * Register the device here @@ -1282,7 +1972,7 @@ size_t AllocLength; /* length of complete descriptor area */ int i; /* loop counter */ unsigned long BusAddr; - + /* rings plus one for alignment (do not cross 4 GB boundary) */ /* RX_RING_SIZE is assumed bigger than TX_RING_SIZE */ #if (BITS_PER_LONG == 32) @@ -1313,7 +2003,7 @@ unsigned long BusAddr; pAC->TxPort[i][0].VTxDescrRing = BusAddr; pDescrMem += TX_RING_SIZE; BusAddr += TX_RING_SIZE; - + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, ("RX%d: pDescrMem: %lX, PhysDescrMem: %lX\n", i, (unsigned long) pDescrMem, @@ -1323,7 +2013,7 @@ unsigned long BusAddr; pDescrMem += RX_RING_SIZE; BusAddr += RX_RING_SIZE; } /* for */ - + return (SK_TRUE); } /* BoardAllocMem */ @@ -1345,16 +2035,20 @@ size_t AllocLength; /* length of complete descriptor area */ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("BoardFreeMem\n")); + + if (pAC->pDescrMem) { + #if (BITS_PER_LONG == 32) - AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8; + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8; #else - AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound - + RX_RING_SIZE + 8; + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + + RX_RING_SIZE + 8; #endif - pci_free_consistent(pAC->PciDev, AllocLength, + pci_free_consistent(pAC->PciDev, AllocLength, pAC->pDescrMem, pAC->pDescrMemDMA); - pAC->pDescrMem = NULL; + pAC->pDescrMem = NULL; + } } /* BoardFreeMem */ @@ -1363,7 +2057,7 @@ size_t AllocLength; /* length of complete descriptor area */ * BoardInitMem - initiate the descriptor rings * * Description: - * This function sets the descriptor rings up in memory. + * This function sets the descriptor rings or LETables up in memory. * The adapter is initialized with the descriptor start addresses. * * Returns: N/A @@ -1378,34 +2072,37 @@ int TxDescrSize; /* the size of a tx descriptor rounded up to alignment*/ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("BoardInitMem\n")); - RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; - pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize; - TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; - pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize; - - for (i=0; iGIni.GIMacsFound; i++) { - SetupRing( - pAC, - pAC->TxPort[i][0].pTxDescrRing, - pAC->TxPort[i][0].VTxDescrRing, - (RXD**)&pAC->TxPort[i][0].pTxdRingHead, - (RXD**)&pAC->TxPort[i][0].pTxdRingTail, - (RXD**)&pAC->TxPort[i][0].pTxdRingPrev, - &pAC->TxPort[i][0].TxdRingFree, - SK_TRUE); - SetupRing( - pAC, - pAC->RxPort[i].pRxDescrRing, - pAC->RxPort[i].VRxDescrRing, - &pAC->RxPort[i].pRxdRingHead, - &pAC->RxPort[i].pRxdRingTail, - &pAC->RxPort[i].pRxdRingPrev, - &pAC->RxPort[i].RxdRingFree, - SK_FALSE); + if (!pAC->GIni.GIYukon2) { + RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; + pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize; + TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; + pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize; + + for (i=0; iGIni.GIMacsFound; i++) { + SetupRing( + pAC, + pAC->TxPort[i][0].pTxDescrRing, + pAC->TxPort[i][0].VTxDescrRing, + (RXD**)&pAC->TxPort[i][0].pTxdRingHead, + (RXD**)&pAC->TxPort[i][0].pTxdRingTail, + (RXD**)&pAC->TxPort[i][0].pTxdRingPrev, + &pAC->TxPort[i][0].TxdRingFree, + &pAC->TxPort[i][0].TxdRingPrevFree, + SK_TRUE); + SetupRing( + pAC, + pAC->RxPort[i].pRxDescrRing, + pAC->RxPort[i].VRxDescrRing, + &pAC->RxPort[i].pRxdRingHead, + &pAC->RxPort[i].pRxdRingTail, + &pAC->RxPort[i].pRxdRingPrev, + &pAC->RxPort[i].RxdRingFree, + &pAC->RxPort[i].RxdRingFree, + SK_FALSE); + } } } /* BoardInitMem */ - /***************************************************************************** * * SetupRing - create one descriptor ring @@ -1425,6 +2122,7 @@ RXD **ppRingHead, /* address where the head should be written */ RXD **ppRingTail, /* address where the tail should be written */ RXD **ppRingPrev, /* address where the tail should be written */ int *pRingFree, /* address where the # of free descr. goes */ +int *pRingPrevFree, /* address where the # of free descr. goes */ SK_BOOL IsTx) /* flag: is this a tx ring */ { int i; /* loop counter */ @@ -1444,11 +2142,11 @@ uintptr_t VNextDescr; /* the virtual bus address of the next descriptor */ DESCR_ALIGN; DescrNum = RX_RING_SIZE / DescrSize; } - + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, ("Descriptor size: %d Descriptor Number: %d\n", DescrSize,DescrNum)); - + pDescr = (RXD*) pMemArea; pPrevDescr = NULL; pNextDescr = (RXD*) (((char*)pDescr) + DescrSize); @@ -1467,11 +2165,12 @@ uintptr_t VNextDescr; /* the virtual bus address of the next descriptor */ } pPrevDescr->pNextRxd = (RXD*) pMemArea; pPrevDescr->VNextRxd = VMemArea; - pDescr = (RXD*) pMemArea; - *ppRingHead = (RXD*) pMemArea; - *ppRingTail = *ppRingHead; - *ppRingPrev = pPrevDescr; - *pRingFree = DescrNum; + pDescr = (RXD*) pMemArea; + *ppRingHead = (RXD*) pMemArea; + *ppRingTail = *ppRingHead; + *ppRingPrev = pPrevDescr; + *pRingFree = DescrNum; + *pRingPrevFree = DescrNum; } /* SetupRing */ @@ -1495,24 +2194,22 @@ int PortIndex) /* index of the port for which to re-init */ ("PortReInitBmu ")); /* set address of first descriptor of ring in BMU */ - SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+ - TX_Q_CUR_DESCR_LOW, + SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+ Q_DA_L, (uint32_t)(((caddr_t) (pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxdRingHead) - pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxDescrRing + pAC->TxPort[PortIndex][TX_PRIO_LOW].VTxDescrRing) & 0xFFFFFFFF)); - SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+ - TX_Q_DESCR_HIGH, + SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+ Q_DA_H, (uint32_t)(((caddr_t) (pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxdRingHead) - pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxDescrRing + pAC->TxPort[PortIndex][TX_PRIO_LOW].VTxDescrRing) >> 32)); - SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_CUR_DESCR_LOW, + SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+Q_DA_L, (uint32_t)(((caddr_t)(pAC->RxPort[PortIndex].pRxdRingHead) - pAC->RxPort[PortIndex].pRxDescrRing + pAC->RxPort[PortIndex].VRxDescrRing) & 0xFFFFFFFF)); - SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_DESCR_HIGH, + SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+Q_DA_H, (uint32_t)(((caddr_t)(pAC->RxPort[PortIndex].pRxdRingHead) - pAC->RxPort[PortIndex].pRxDescrRing + pAC->RxPort[PortIndex].VRxDescrRing) >> 32)); @@ -1531,8 +2228,8 @@ int PortIndex) /* index of the port for which to re-init */ * Returns: N/A * */ -#if 0 -static void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs) +#if 0 /* uboot */ +static SkIsrRetVar SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs) #else void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs) #endif @@ -1540,98 +2237,111 @@ void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs) struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id; DEV_NET *pNet; SK_AC *pAC; -SK_U32 IntSrc; /* interrupts source register contents */ +SK_U32 IntSrc; /* interrupts source register contents */ pNet = (DEV_NET*) dev->priv; pAC = pNet->pAC; - + /* * Check and process if its our interrupt */ SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc); - if (IntSrc == 0) { + if ((IntSrc == 0) && (!pNet->NetConsoleMode)) { return; } +#ifdef CONFIG_SK98LIN_NAPI + if (netif_rx_schedule_prep(dev)) { + pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS); + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); + __netif_rx_schedule(dev); + } + +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IS_XA1_F) { + CLEAR_TX_IRQ(0, TX_PRIO_LOW); + } + if (IntSrc & IS_XA2_F) { + CLEAR_TX_IRQ(1, TX_PRIO_LOW); + } +#endif + + +#else while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) { #if 0 /* software irq currently not used */ - if (IntSrc & IRQ_SW) { + if (IntSrc & IS_IRQ_SW) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("Software IRQ\n")); } #endif - if (IntSrc & IRQ_EOF_RX1) { + if (IntSrc & IS_R1_F) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF RX1 IRQ\n")); ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + CLEAR_AND_START_RX(0); SK_PNMI_CNT_RX_INTR(pAC, 0); } - if (IntSrc & IRQ_EOF_RX2) { + if (IntSrc & IS_R2_F) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF RX2 IRQ\n")); ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE); + CLEAR_AND_START_RX(1); SK_PNMI_CNT_RX_INTR(pAC, 1); } #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ - if (IntSrc & IRQ_EOF_AS_TX1) { + if (IntSrc & IS_XA1_F) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF AS TX1 IRQ\n")); + CLEAR_TX_IRQ(0, TX_PRIO_LOW); SK_PNMI_CNT_TX_INTR(pAC, 0); spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]); spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); } - if (IntSrc & IRQ_EOF_AS_TX2) { + if (IntSrc & IS_XA2_F) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF AS TX2 IRQ\n")); + CLEAR_TX_IRQ(1, TX_PRIO_LOW); SK_PNMI_CNT_TX_INTR(pAC, 1); spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock); FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]); spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock); } #if 0 /* only if sync. queues used */ - if (IntSrc & IRQ_EOF_SY_TX1) { + if (IntSrc & IS_XS1_F) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF SY TX1 IRQ\n")); + CLEAR_TX_IRQ(0, TX_PRIO_HIGH); SK_PNMI_CNT_TX_INTR(pAC, 1); spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH); spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); - ClearTxIrq(pAC, 0, TX_PRIO_HIGH); } - if (IntSrc & IRQ_EOF_SY_TX2) { + if (IntSrc & IS_XS2_F) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF SY TX2 IRQ\n")); + CLEAR_TX_IRQ(1, TX_PRIO_HIGH); SK_PNMI_CNT_TX_INTR(pAC, 1); spin_lock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock); FreeTxDescriptors(pAC, 1, TX_PRIO_HIGH); spin_unlock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock); - ClearTxIrq(pAC, 1, TX_PRIO_HIGH); } #endif #endif - /* do all IO at once */ - if (IntSrc & IRQ_EOF_RX1) - ClearAndStartRx(pAC, 0); - if (IntSrc & IRQ_EOF_RX2) - ClearAndStartRx(pAC, 1); -#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ - if (IntSrc & IRQ_EOF_AS_TX1) - ClearTxIrq(pAC, 0, TX_PRIO_LOW); - if (IntSrc & IRQ_EOF_AS_TX2) - ClearTxIrq(pAC, 1, TX_PRIO_LOW); -#endif SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc); } /* while (IntSrc & IRQ_MASK != 0) */ +#endif + IntSrc &= pAC->GIni.GIValIrqMask; if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("SPECIAL IRQ DP-Cards => %x\n", IntSrc)); @@ -1643,14 +2353,12 @@ SK_U32 IntSrc; /* interrupts source register contents */ SkEventDispatcher(pAC, pAC->IoBase); spin_unlock(&pAC->SlowPathLock); } - /* - * do it all again is case we cleared an interrupt that - * came in after handling the ring (OUTs may be delayed - * in hardware buffers, but are through after IN) - */ +#ifndef CONFIG_SK98LIN_NAPI + /* Handle interrupts */ ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE); +#endif if (pAC->CheckQueue) { pAC->CheckQueue = SK_FALSE; @@ -1659,11 +2367,10 @@ SK_U32 IntSrc; /* interrupts source register contents */ spin_unlock(&pAC->SlowPathLock); } - /* IRQ is processed - Enable IRQs again*/ - SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); - return; + return; } /* SkGeIsr */ @@ -1680,102 +2387,112 @@ SK_U32 IntSrc; /* interrupts source register contents */ * Returns: N/A * */ -#if 0 -static void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs) +#if 0 /* uboot */ +static SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs) #else -void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs) +SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs) #endif { struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id; DEV_NET *pNet; SK_AC *pAC; -SK_U32 IntSrc; /* interrupts source register contents */ +SK_U32 IntSrc; /* interrupts source register contents */ pNet = (DEV_NET*) dev->priv; pAC = pNet->pAC; - + /* * Check and process if its our interrupt */ SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc); - if (IntSrc == 0) { + if ((IntSrc == 0) && (!pNet->NetConsoleMode)) { return; } + +#ifdef CONFIG_SK98LIN_NAPI + if (netif_rx_schedule_prep(dev)) { + CLEAR_AND_START_RX(0); + CLEAR_TX_IRQ(0, TX_PRIO_LOW); + pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS); + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); + __netif_rx_schedule(dev); + } +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IS_XA1_F) { + CLEAR_TX_IRQ(0, TX_PRIO_LOW); + } +#endif +#else while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) { #if 0 /* software irq currently not used */ - if (IntSrc & IRQ_SW) { + if (IntSrc & IS_IRQ_SW) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("Software IRQ\n")); } #endif - if (IntSrc & IRQ_EOF_RX1) { + if (IntSrc & IS_R1_F) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF RX1 IRQ\n")); ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + CLEAR_AND_START_RX(0); SK_PNMI_CNT_RX_INTR(pAC, 0); } #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ - if (IntSrc & IRQ_EOF_AS_TX1) { + if (IntSrc & IS_XA1_F) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF AS TX1 IRQ\n")); + CLEAR_TX_IRQ(0, TX_PRIO_LOW); SK_PNMI_CNT_TX_INTR(pAC, 0); spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]); spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); } #if 0 /* only if sync. queues used */ - if (IntSrc & IRQ_EOF_SY_TX1) { + if (IntSrc & IS_XS1_F) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("EOF SY TX1 IRQ\n")); + CLEAR_TX_IRQ(0, TX_PRIO_HIGH); SK_PNMI_CNT_TX_INTR(pAC, 0); spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH); spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); - ClearTxIrq(pAC, 0, TX_PRIO_HIGH); } #endif #endif - /* do all IO at once */ - if (IntSrc & IRQ_EOF_RX1) - ClearAndStartRx(pAC, 0); -#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ - if (IntSrc & IRQ_EOF_AS_TX1) - ClearTxIrq(pAC, 0, TX_PRIO_LOW); -#endif SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc); } /* while (IntSrc & IRQ_MASK != 0) */ - +#endif + + IntSrc &= pAC->GIni.GIValIrqMask; if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, ("SPECIAL IRQ SP-Cards => %x\n", IntSrc)); pAC->CheckQueue = SK_FALSE; spin_lock(&pAC->SlowPathLock); if (IntSrc & SPECIAL_IRQS) + SkGeSirqIsr(pAC, pAC->IoBase, IntSrc); SkEventDispatcher(pAC, pAC->IoBase); spin_unlock(&pAC->SlowPathLock); } - /* - * do it all again is case we cleared an interrupt that - * came in after handling the ring (OUTs may be delayed - * in hardware buffers, but are through after IN) - */ + +#ifndef CONFIG_SK98LIN_NAPI ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); +#endif /* IRQ is processed - Enable IRQs again*/ - SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); - return; + return; } /* SkGeIsrOnePort */ - /**************************************************************************** * * SkGeOpen - handle start of initialized adapter @@ -1792,101 +2509,142 @@ SK_U32 IntSrc; /* interrupts source register contents */ * 0 on success * != 0 on error */ -#if 0 +#if 0 /* uboot */ static int SkGeOpen( #else int SkGeOpen( #endif -struct SK_NET_DEVICE *dev) +struct SK_NET_DEVICE *dev) /* the device that is to be opened */ { - DEV_NET *pNet; - SK_AC *pAC; - unsigned long Flags; /* for spin lock */ - int i; - SK_EVPARA EvPara; /* an event parameter union */ - - pNet = (DEV_NET*) dev->priv; - pAC = pNet->pAC; + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + unsigned long Flags; /* for the spin locks */ + unsigned long InitFlags; /* for the spin locks */ + int CurrMac; /* loop ctr for ports */ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC)); + spin_lock_irqsave(&pAC->InitLock, InitFlags); +#if 0 /* uboot */ - if (pAC->BoardLevel == 0) { + if (pAC->DiagModeActive == DIAG_ACTIVE) { + if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) { + return (-1); /* still in use by diag; deny actions */ + } + } + + if (!try_module_get(THIS_MODULE)) { + return (-1); /* increase of usage count not possible */ + } + + /* Set blink mode */ + if ((pAC->PciDev->vendor == 0x1186) || (pAC->PciDev->vendor == 0x11ab )) + pAC->GIni.GILedBlinkCtrl = OEM_CONFIG_VALUE; +#endif + + + + if (pAC->BoardLevel == SK_INIT_DATA) { /* level 1 init common modules here */ - if (SkGeInit(pAC, pAC->IoBase, 1) != 0) { + if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) { printk("%s: HWInit (1) failed.\n", pAC->dev[pNet->PortNr]->name); return (-1); } - SkI2cInit (pAC, pAC->IoBase, 1); - SkEventInit (pAC, pAC->IoBase, 1); - SkPnmiInit (pAC, pAC->IoBase, 1); - SkAddrInit (pAC, pAC->IoBase, 1); - SkRlmtInit (pAC, pAC->IoBase, 1); - SkTimerInit (pAC, pAC->IoBase, 1); - pAC->BoardLevel = 1; + SkI2cInit (pAC, pAC->IoBase, SK_INIT_IO); + SkEventInit (pAC, pAC->IoBase, SK_INIT_IO); + +#ifdef SK_PNMI_SUPPORT + SkPnmiInit (pAC, pAC->IoBase, SK_INIT_IO); +#endif + + SkAddrInit (pAC, pAC->IoBase, SK_INIT_IO); + SkRlmtInit (pAC, pAC->IoBase, SK_INIT_IO); + SkTimerInit (pAC, pAC->IoBase, SK_INIT_IO); + pAC->BoardLevel = SK_INIT_IO; +#ifdef Y2_RECOVERY + /* mark entries invalid */ + pAC->LastPort = 3; + pAC->LastOpc = 0xFF; +#endif } - if (pAC->BoardLevel != 2) { + if (pAC->BoardLevel != SK_INIT_RUN) { /* tschilling: Level 2 init modules here, check return value. */ - if (SkGeInit(pAC, pAC->IoBase, 2) != 0) { + if (SkGeInit(pAC, pAC->IoBase, SK_INIT_RUN) != 0) { printk("%s: HWInit (2) failed.\n", pAC->dev[pNet->PortNr]->name); return (-1); } - SkI2cInit (pAC, pAC->IoBase, 2); - SkEventInit (pAC, pAC->IoBase, 2); - SkPnmiInit (pAC, pAC->IoBase, 2); - SkAddrInit (pAC, pAC->IoBase, 2); - SkRlmtInit (pAC, pAC->IoBase, 2); - SkTimerInit (pAC, pAC->IoBase, 2); - pAC->BoardLevel = 2; - } + SkI2cInit (pAC, pAC->IoBase, SK_INIT_RUN); + SkEventInit (pAC, pAC->IoBase, SK_INIT_RUN); - for (i=0; iGIni.GIMacsFound; i++) { - /* Enable transmit descriptor polling. */ - SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE); - FillRxRing(pAC, &pAC->RxPort[i]); - } - SkGeYellowLED(pAC, pAC->IoBase, 1); - -#ifdef USE_INT_MOD -/* moderate only TX complete interrupts (these are not time critical) */ -#define IRQ_MOD_MASK (IRQ_EOF_AS_TX1 | IRQ_EOF_AS_TX2) - { - unsigned long ModBase; - ModBase = 53125000 / INTS_PER_SEC; - SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase); - SK_OUT32(pAC->IoBase, B2_IRQM_MSK, IRQ_MOD_MASK); - SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START); - } +#ifdef SK_PNMI_SUPPORT + SkPnmiInit (pAC, pAC->IoBase, SK_INIT_RUN); #endif - /* enable Interrupts */ - SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); - SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK); + SkAddrInit (pAC, pAC->IoBase, SK_INIT_RUN); + SkRlmtInit (pAC, pAC->IoBase, SK_INIT_RUN); + SkTimerInit (pAC, pAC->IoBase, SK_INIT_RUN); + pAC->BoardLevel = SK_INIT_RUN; + } + + for (CurrMac=0; CurrMacGIni.GIMacsFound; CurrMac++) { + if (!CHIP_ID_YUKON_2(pAC)) { + /* Enable transmit descriptor polling. */ + SkGePollTxD(pAC, pAC->IoBase, CurrMac, SK_TRUE); + FillRxRing(pAC, &pAC->RxPort[CurrMac]); + SkMacRxTxEnable(pAC, pAC->IoBase, pNet->PortNr); + } + } + + SkGeYellowLED(pAC, pAC->IoBase, 1); + SkDimEnableModerationIfNeeded(pAC); + + if (!CHIP_ID_YUKON_2(pAC)) { + /* + ** Has been setup already at SkGeInit(SK_INIT_IO), + ** but additional masking added for Genesis & Yukon + ** chipsets -> modify it... + */ + pAC->GIni.GIValIrqMask &= IRQ_MASK; +#ifndef USE_TX_COMPLETE + pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS); +#endif + } spin_lock_irqsave(&pAC->SlowPathLock, Flags); if ((pAC->RlmtMode != 0) && (pAC->MaxPorts == 0)) { - EvPara.Para32[0] = pAC->RlmtNets; - EvPara.Para32[1] = -1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, - EvPara); - EvPara.Para32[0] = pAC->RlmtMode; - EvPara.Para32[1] = 0; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE, - EvPara); + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, + pAC->RlmtNets, -1, SK_FALSE); + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE, + pAC->RlmtMode, 0, SK_FALSE); } - EvPara.Para32[0] = pNet->NetNr; - EvPara.Para32[1] = -1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); - SkEventDispatcher(pAC, pAC->IoBase); + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, + pNet->NetNr, -1, SK_TRUE); spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - pAC->MaxPorts++; - pNet->Up = 1; +#ifdef Y2_RECOVERY + pNet->TimerExpired = SK_FALSE; + pNet->InRecover = SK_FALSE; + pNet->NetConsoleMode = SK_FALSE; - MOD_INC_USE_COUNT; + /* Initialize the kernel timer */ +#if 0 // u-boot + init_timer(&pNet->KernelTimer); + pNet->KernelTimer.function = SkGeHandleKernelTimer; + pNet->KernelTimer.data = (unsigned long) pNet; + pNet->KernelTimer.expires = jiffies + (HZ/4); /* initially 250ms */ + add_timer(&pNet->KernelTimer); +#endif +#endif + + /* enable Interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); + SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK); + + pAC->MaxPorts++; + spin_unlock_irqrestore(&pAC->InitLock, InitFlags); SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeOpen suceeded\n")); @@ -1906,33 +2664,62 @@ struct SK_NET_DEVICE *dev) * 0 - on success * error code - on error */ -#if 0 +#if 0 /* uboot */ static int SkGeClose( #else int SkGeClose( #endif -struct SK_NET_DEVICE *dev) +struct SK_NET_DEVICE *dev) /* the device that is to be closed */ { - DEV_NET *pNet; - SK_AC *pAC; + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + DEV_NET *newPtrNet; + unsigned long Flags; /* for the spin locks */ + unsigned long InitFlags; /* for the spin locks */ + int CurrMac; /* loop ctr for the current MAC */ + int PortIdx; +#ifdef CONFIG_SK98LIN_NAPI + int WorkToDo = 1; /* min(*budget, dev->quota); */ + int WorkDone = 0; +#endif + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeClose: pAC=0x%lX ", (unsigned long)pAC)); + spin_lock_irqsave(&pAC->InitLock, InitFlags); - unsigned long Flags; /* for spin lock */ - int i; - int PortIdx; - SK_EVPARA EvPara; +#ifdef Y2_RECOVERY + pNet->InRecover = SK_TRUE; +#if 0 /* uboot */ + del_timer(&pNet->KernelTimer); +#endif +#endif + + if (pAC->DiagModeActive == DIAG_ACTIVE) { + if (pAC->DiagFlowCtrl == SK_FALSE) { + MOD_DEC_USE_COUNT; + /* + ** notify that the interface which has been closed + ** by operator interaction must not be started up + ** again when the DIAG has finished. + */ + newPtrNet = (DEV_NET *) pAC->dev[0]->priv; + if (newPtrNet == pNet) { + pAC->WasIfUp[0] = SK_FALSE; + } else { + pAC->WasIfUp[1] = SK_FALSE; + } + return 0; /* return to system everything is fine... */ + } else { + pAC->DiagFlowCtrl = SK_FALSE; + } + } netif_stop_queue(dev); - pNet = (DEV_NET*) dev->priv; - pAC = pNet->pAC; if (pAC->RlmtNets == 1) PortIdx = pAC->ActivePort; else PortIdx = pNet->NetNr; - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, - ("SkGeClose: pAC=0x%lX ", (unsigned long)pAC)); - /* * Clear multicast table, promiscuous mode .... */ @@ -1944,53 +2731,116 @@ struct SK_NET_DEVICE *dev) spin_lock_irqsave(&pAC->SlowPathLock, Flags); /* disable interrupts */ SK_OUT32(pAC->IoBase, B0_IMSK, 0); - EvPara.Para32[0] = pNet->NetNr; - EvPara.Para32[1] = -1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); - SkEventDispatcher(pAC, pAC->IoBase); + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, + pNet->NetNr, -1, SK_TRUE); SK_OUT32(pAC->IoBase, B0_IMSK, 0); /* stop the hardware */ - SkGeDeInit(pAC, pAC->IoBase); - pAC->BoardLevel = 0; + + + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 1)) { + /* RLMT check link state mode */ + for (CurrMac=0; CurrMacGIni.GIMacsFound; CurrMac++) { + if (CHIP_ID_YUKON_2(pAC)) + SkY2PortStop( pAC, + pAC->IoBase, + CurrMac, + SK_STOP_ALL, + SK_HARD_RST); + else + SkGeStopPort( pAC, + pAC->IoBase, + CurrMac, + SK_STOP_ALL, + SK_HARD_RST); + } /* for */ + } else { + /* Single link or single port */ + if (CHIP_ID_YUKON_2(pAC)) + SkY2PortStop( pAC, + pAC->IoBase, + PortIdx, + SK_STOP_ALL, + SK_HARD_RST); + else + SkGeStopPort( pAC, + pAC->IoBase, + PortIdx, + SK_STOP_ALL, + SK_HARD_RST); + } spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); } else { - spin_lock_irqsave(&pAC->SlowPathLock, Flags); - EvPara.Para32[0] = pNet->NetNr; - EvPara.Para32[1] = -1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); - SkEventDispatcher(pAC, pAC->IoBase); + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, + pNet->NetNr, -1, SK_FALSE); + SkLocalEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET, + pNet->NetNr, -1, SK_TRUE); spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - + /* Stop port */ spin_lock_irqsave(&pAC->TxPort[pNet->PortNr] [TX_PRIO_LOW].TxDesRingLock, Flags); - SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, - SK_STOP_ALL, SK_HARD_RST); + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr, + SK_STOP_ALL, SK_HARD_RST); + } + else { + SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, + SK_STOP_ALL, SK_HARD_RST); + } spin_unlock_irqrestore(&pAC->TxPort[pNet->PortNr] [TX_PRIO_LOW].TxDesRingLock, Flags); } if (pAC->RlmtNets == 1) { /* clear all descriptor rings */ - for (i=0; iGIni.GIMacsFound; i++) { - ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE); - ClearRxRing(pAC, &pAC->RxPort[i]); - ClearTxRing(pAC, &pAC->TxPort[i][TX_PRIO_LOW]); + for (CurrMac=0; CurrMacGIni.GIMacsFound; CurrMac++) { + if (!CHIP_ID_YUKON_2(pAC)) { +#ifdef CONFIG_SK98LIN_NAPI + WorkToDo = 1; + ReceiveIrq(pAC,&pAC->RxPort[CurrMac], + SK_TRUE,&WorkDone,WorkToDo); +#else + ReceiveIrq(pAC,&pAC->RxPort[CurrMac],SK_TRUE); +#endif + ClearRxRing(pAC, &pAC->RxPort[CurrMac]); + ClearTxRing(pAC, &pAC->TxPort[CurrMac][TX_PRIO_LOW]); + } else { + SkY2FreeRxBuffers(pAC, pAC->IoBase, CurrMac); + SkY2FreeTxBuffers(pAC, pAC->IoBase, CurrMac); + } } } else { /* clear port descriptor rings */ - ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE); - ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]); - ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]); + if (!CHIP_ID_YUKON_2(pAC)) { +#ifdef CONFIG_SK98LIN_NAPI + WorkToDo = 1; + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo); +#else + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE); +#endif + ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]); + ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]); + } + else { + SkY2FreeRxBuffers(pAC, pAC->IoBase, pNet->PortNr); + SkY2FreeTxBuffers(pAC, pAC->IoBase, pNet->PortNr); + } } SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeClose: done ")); + SK_MEMSET(&(pAC->PnmiBackup), 0, sizeof(SK_PNMI_STRUCT_DATA)); + SK_MEMCPY(&(pAC->PnmiBackup), &(pAC->PnmiStruct), + sizeof(SK_PNMI_STRUCT_DATA)); + pAC->MaxPorts--; - pNet->Up = 0; - MOD_DEC_USE_COUNT; + +#ifdef Y2_RECOVERY + pNet->InRecover = SK_FALSE; +#endif + spin_unlock_irqrestore(&pAC->InitLock, InitFlags); return (0); } /* SkGeClose */ @@ -2024,14 +2874,13 @@ int Rc; /* return code of XmitFrame */ pNet = (DEV_NET*) dev->priv; pAC = pNet->pAC; -#if 0 +#if 0 /* uboot */ if ((!skb_shinfo(skb)->nr_frags) || #else - if (1 || + if(1 || #endif (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) { /* Don't activate scatter-gather and hardware checksum */ - if (pAC->RlmtNets == 2) Rc = XmitFrame( pAC, @@ -2043,7 +2892,7 @@ int Rc; /* return code of XmitFrame */ &pAC->TxPort[pAC->ActivePort][TX_PRIO_LOW], skb); } else { -#if 0 +#if 0 /* uboot */ /* scatter-gather and hardware TCP checksumming anabled*/ if (pAC->RlmtNets == 2) Rc = XmitFrameSG( @@ -2059,9 +2908,11 @@ int Rc; /* return code of XmitFrame */ } /* Transmitter out of resources? */ +#ifdef USE_TX_COMPLETE if (Rc <= 0) { netif_stop_queue(dev); } +#endif /* If not taken, give buffer ownership back to the * queueing layer. @@ -2069,12 +2920,112 @@ int Rc; /* return code of XmitFrame */ if (Rc < 0) return (1); -#if 0 +#if 0 /* uboot */ dev->trans_start = jiffies; #endif return (0); } /* SkGeXmit */ +#ifdef CONFIG_SK98LIN_NAPI +/***************************************************************************** + * + * SkGePoll - NAPI Rx polling callback for GEnesis and Yukon chipsets + * + * Description: + * Called by the Linux system in case NAPI polling is activated + * + * Returns: + * The number of work data still to be handled + */ +static int SkGePoll(struct net_device *dev, int *budget) +{ + SK_AC *pAC = ((DEV_NET*)(dev->priv))->pAC; /* pointer to adapter context */ + int WorkToDo = min(*budget, dev->quota); + int WorkDone = 0; + unsigned long Flags; + + + if (pAC->dev[0] != pAC->dev[1]) { + spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock); + FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]); + spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock); + + ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE, &WorkDone, WorkToDo); + CLEAR_AND_START_RX(1); + } + spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); + FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]); + spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); + + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE, &WorkDone, WorkToDo); + CLEAR_AND_START_RX(0); + + *budget -= WorkDone; + dev->quota -= WorkDone; + + if(WorkDone < WorkToDo) { + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + netif_rx_complete(dev); + pAC->GIni.GIValIrqMask |= (NAPI_DRV_IRQS); +#ifndef USE_TX_COMPLETE + pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS); +#endif + /* enable interrupts again */ + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + } + return (WorkDone >= WorkToDo); +} /* SkGePoll */ +#endif + +/* uboot */ +unsigned long xchg(volatile int * m, unsigned long val) +{ + unsigned int retval; + retval = *m; + *m = val; + return retval; +} + + +#ifdef SK_POLL_CONTROLLER +/***************************************************************************** + * + * SkGeNetPoll - Polling "interrupt" + * + * Description: + * Polling 'interrupt' - used by things like netconsole and netdump + * to send skbs without having to re-enable interrupts. + * It's not called while the interrupt routine is executing. + */ +static void SkGeNetPoll( +struct SK_NET_DEVICE *dev) +{ +DEV_NET *pNet; +SK_AC *pAC; + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + pNet->NetConsoleMode = SK_TRUE; + + /* Prevent any reconfiguration while handling + the 'interrupt' */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + + if (!CHIP_ID_YUKON_2(pAC)) { + /* Handle the GENESIS Isr */ + if (pAC->GIni.GIMacsFound == 2) + SkGeIsr(dev->irq, dev, NULL); + else + SkGeIsrOnePort(dev->irq, dev, NULL); + } else { + /* Handle the Yukon2 Isr */ + SkY2Isr(dev->irq, dev, NULL); + } + +} +#endif + /***************************************************************************** * @@ -2099,24 +3050,35 @@ int Rc; /* return code of XmitFrame */ * < 0 - on failure: other problems ( -> return failure to upper layers) */ static int XmitFrame( -SK_AC *pAC, /* pointer to adapter context */ +SK_AC *pAC, /* pointer to adapter context */ TX_PORT *pTxPort, /* pointer to struct of port to send to */ -struct sk_buff *pMessage) /* pointer to send-message */ +struct sk_buff *pMessage) /* pointer to send-message */ { -TXD *pTxd; /* the rxd to fill */ -unsigned long Flags; -SK_U64 PhysAddr; -int BytesSend; + TXD *pTxd; /* the rxd to fill */ + TXD *pOldTxd; + unsigned long Flags; + SK_U64 PhysAddr; +#if 0 /* uboot */ - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, - ("X")); + int Protocol; + int IpHeaderLength; +#endif + int BytesSend = pMessage->len; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, ("X")); spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags); #ifndef USE_TX_COMPLETE - FreeTxDescriptors(pAC, pTxPort); + if ((pTxPort->TxdRingPrevFree - pTxPort->TxdRingFree) > 6) { + FreeTxDescriptors(pAC, pTxPort); + pTxPort->TxdRingPrevFree = pTxPort->TxdRingFree; + } #endif if (pTxPort->TxdRingFree == 0) { - /* no enough free descriptors in ring at the moment */ + /* + ** not enough free descriptors in ring at the moment. + ** Maybe free'ing some old one help? + */ FreeTxDescriptors(pAC, pTxPort); if (pTxPort->TxdRingFree == 0) { spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); @@ -2124,63 +3086,118 @@ int BytesSend; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, ("XmitFrame failed\n")); - /* this message can not be sent now */ - /* Because tbusy seems to be set, the message should not be freed here */ - /* It will be used by the scheduler of the ethernet handler */ + /* + ** the desired message can not be sent + ** Because tbusy seems to be set, the message + ** should not be freed here. It will be used + ** by the scheduler of the ethernet handler + */ return (-1); } } - /* advance head counter behind descriptor needed for this frame */ + +#if 0 /* uboot*/ + /* + ** If the passed socket buffer is of smaller MTU-size than 60, + ** copy everything into new buffer and fill all bytes between + ** the original packet end and the new packet end of 60 with 0x00. + ** This is to resolve faulty padding by the HW with 0xaa bytes. + */ + if (BytesSend < C_LEN_ETHERNET_MINSIZE) { + if ((pMessage = skb_padto(pMessage, C_LEN_ETHERNET_MINSIZE)) == NULL) { + spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); + return 0; + } + pMessage->len = C_LEN_ETHERNET_MINSIZE; + } +#endif + + /* + ** advance head counter behind descriptor needed for this frame, + ** so that needed descriptor is reserved from that on. The next + ** action will be to add the passed buffer to the TX-descriptor + */ pTxd = pTxPort->pTxdRingHead; pTxPort->pTxdRingHead = pTxd->pNextTxd; pTxPort->TxdRingFree--; - /* the needed descriptor is reserved now */ - - /* - * everything allocated ok, so add buffer to descriptor - */ #ifdef SK_DUMP_TX DumpMsg(pMessage, "XmitFrame"); #endif - /* set up descriptor and CONTROL dword */ -#if 0 + /* + ** First step is to map the data to be sent via the adapter onto + ** the DMA memory. Kernel 2.2 uses virt_to_bus(), but kernels 2.4 + ** and 2.6 need to use pci_map_page() for that mapping. + */ +#if 0 /* uboot */ PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, - virt_to_page(pMessage->data), - ((unsigned long) pMessage->data & - ~PAGE_MASK), - pMessage->len, - PCI_DMA_TODEVICE); + virt_to_page(pMessage->data), + ((unsigned long) pMessage->data & ~PAGE_MASK), + pMessage->len, + PCI_DMA_TODEVICE); #else - PhysAddr = (SK_U64) pci_phys_to_mem(pAC->PciDev, (u32) pMessage->data); + PhysAddr = (SK_U64)(SK_U32)pMessage->data; #endif - pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32); - pTxd->pMBuf = pMessage; - pTxd->TBControl = TX_CTRL_OWN_BMU | TX_CTRL_STF | - TX_CTRL_CHECK_DEFAULT | TX_CTRL_SOFTWARE | + pTxd->pMBuf = pMessage; + +#if 0 /* uboot */ + if (pMessage->ip_summed == CHECKSUM_HW) { + Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff); + if ((Protocol == C_PROTO_ID_UDP) && + (pAC->GIni.GIChipRev == 0) && + (pAC->GIni.GIChipId == CHIP_ID_YUKON)) { + pTxd->TBControl = BMU_TCP_CHECK; + } else { + pTxd->TBControl = BMU_UDP_CHECK; + } + + IpHeaderLength = (SK_U8)pMessage->data[C_OFFSET_IPHEADER]; + IpHeaderLength = (IpHeaderLength & 0xf) * 4; + pTxd->TcpSumOfs = 0; /* PH-Checksum already calculated */ + pTxd->TcpSumSt = C_LEN_ETHERMAC_HEADER + IpHeaderLength + + (Protocol == C_PROTO_ID_UDP ? + C_OFFSET_UDPHEADER_UDPCS : + C_OFFSET_TCPHEADER_TCPCS); + pTxd->TcpSumWr = C_LEN_ETHERMAC_HEADER + IpHeaderLength; + + pTxd->TBControl |= BMU_OWN | BMU_STF | + BMU_SW | BMU_EOF | #ifdef USE_TX_COMPLETE - TX_CTRL_EOF | TX_CTRL_EOF_IRQ | pMessage->len; -#else - TX_CTRL_EOF | pMessage->len; + BMU_IRQ_EOF | #endif - - if ((pTxPort->pTxdRingPrev->TBControl & TX_CTRL_OWN_BMU) == 0) { - /* previous descriptor already done, so give tx start cmd */ - /* StartTx(pAC, pTxPort->HwAddr); */ - SK_OUT8(pTxPort->HwAddr, TX_Q_CTRL, TX_Q_CTRL_START); + pMessage->len; + } else +#endif + { + pTxd->TBControl = BMU_OWN | BMU_STF | BMU_CHECK | + BMU_SW | BMU_EOF | +#ifdef USE_TX_COMPLETE + BMU_IRQ_EOF | +#endif + pMessage->len; } - pTxPort->pTxdRingPrev = pTxd; + /* + ** If previous descriptor already done, give TX start cmd + */ + /* uboot */ + pOldTxd = (TXD *)xchg((int *)&pTxPort->pTxdRingPrev, (unsigned int)pTxd); + if ((pOldTxd->TBControl & BMU_OWN) == 0) { + SK_OUT8(pTxPort->HwAddr, Q_CSR, CSR_START); + } - BytesSend = pMessage->len; + /* + ** after releasing the lock, the skb may immediately be free'd + */ spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); - /* after releasing the lock, the skb may be immidiately freed */ - if (pTxPort->TxdRingFree != 0) + if (pTxPort->TxdRingFree != 0) { return (BytesSend); - else + } else { return (0); + } } /* XmitFrame */ @@ -2199,23 +3216,23 @@ int BytesSend; * the ring is full ( -> set tbusy) * < 0 - on failure: other problems ( -> return failure to upper layers) */ -#if 0 +#if 0 /* uboot */ static int XmitFrameSG( -SK_AC *pAC, /* pointer to adapter context */ -TX_PORT *pTxPort, /* pointer to struct of port to send to */ -struct sk_buff *pMessage) /* pointer to send-message */ +SK_AC *pAC, /* pointer to adapter context */ +TX_PORT *pTxPort, /* pointer to struct of port to send to */ +struct sk_buff *pMessage) /* pointer to send-message */ { - int i; - int BytesSend; - int hlength; - int protocol; - skb_frag_t *sk_frag; - TXD *pTxd; - TXD *pTxdFst; - TXD *pTxdLst; - SK_U64 PhysAddr; - unsigned long Flags; + TXD *pTxd; + TXD *pTxdFst; + TXD *pTxdLst; + int CurrFrag; + int BytesSend; + int IpHeaderLength; + int Protocol; + skb_frag_t *sk_frag; + SK_U64 PhysAddr; + unsigned long Flags; spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags); #ifndef USE_TX_COMPLETE @@ -2234,114 +3251,123 @@ struct sk_buff *pMessage) /* pointer to send-message */ } } - - pTxd = pTxPort->pTxdRingHead; - pTxdFst = pTxd; - pTxdLst = pTxd; + pTxd = pTxPort->pTxdRingHead; + pTxdFst = pTxd; + pTxdLst = pTxd; BytesSend = 0; - protocol = 0; + Protocol = 0; - /* map first fragment (header) */ + /* + ** Map the first fragment (header) into the DMA-space + */ PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, virt_to_page(pMessage->data), ((unsigned long) pMessage->data & ~PAGE_MASK), skb_headlen(pMessage), PCI_DMA_TODEVICE); - pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32); - /* HW checksum? */ + /* + ** Does the HW need to evaluate checksum for TCP or UDP packets? + */ if (pMessage->ip_summed == CHECKSUM_HW) { - pTxd->TBControl = TX_CTRL_STF | - TX_CTRL_ST_FWD | - skb_headlen(pMessage); + pTxd->TBControl = BMU_STF | BMU_STFWD | skb_headlen(pMessage); + /* + ** We have to use the opcode for tcp here, because the + ** opcode for udp is not working in the hardware yet + ** (Revision 2.0) + */ + Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff); + if ((Protocol == C_PROTO_ID_UDP) && + (pAC->GIni.GIChipRev == 0) && + (pAC->GIni.GIChipId == CHIP_ID_YUKON)) { + pTxd->TBControl |= BMU_TCP_CHECK; + } else { + pTxd->TBControl |= BMU_UDP_CHECK; + } - /* We have to use the opcode for tcp here because the opcode for - udp is not working in the hardware yet (revision 2.0)*/ - protocol = ((SK_U8)pMessage->data[23] & 0xf); - if ((protocol == 17) && (pAC->GIni.GIChipRev != 0)) - pTxd->TBControl |= BMU_UDP_CHECK; - else - pTxd->TBControl |= BMU_TCP_CHECK ; - - hlength = ((SK_U8)pMessage->data[14] & 0xf) * 4; + IpHeaderLength = ((SK_U8)pMessage->data[C_OFFSET_IPHEADER] & 0xf)*4; pTxd->TcpSumOfs = 0; /* PH-Checksum already claculated */ - pTxd->TcpSumSt = 14+hlength+16; - pTxd->TcpSumWr = 14+hlength; - + pTxd->TcpSumSt = C_LEN_ETHERMAC_HEADER + IpHeaderLength + + (Protocol == C_PROTO_ID_UDP ? + C_OFFSET_UDPHEADER_UDPCS : + C_OFFSET_TCPHEADER_TCPCS); + pTxd->TcpSumWr = C_LEN_ETHERMAC_HEADER + IpHeaderLength; } else { - pTxd->TBControl = TX_CTRL_CHECK_DEFAULT | - TX_CTRL_SOFTWARE | - TX_CTRL_STF | - skb_headlen(pMessage); + pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_STF | + skb_headlen(pMessage); } pTxd = pTxd->pNextTxd; pTxPort->TxdRingFree--; BytesSend += skb_headlen(pMessage); - - /* Map SG fragments */ - for (i = 0; i < skb_shinfo(pMessage)->nr_frags; i++) { - sk_frag = &skb_shinfo(pMessage)->frags[i]; - - /* we already have the proper value in entry */ + /* + ** Browse over all SG fragments and map each of them into the DMA space + */ + for (CurrFrag = 0; CurrFrag < skb_shinfo(pMessage)->nr_frags; CurrFrag++) { + sk_frag = &skb_shinfo(pMessage)->frags[CurrFrag]; + /* + ** we already have the proper value in entry + */ PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, sk_frag->page, sk_frag->page_offset, sk_frag->size, PCI_DMA_TODEVICE); - pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32); - pTxd->pMBuf = pMessage; - - /* HW checksum */ + pTxd->pMBuf = pMessage; + + /* + ** Does the HW need to evaluate checksum for TCP or UDP packets? + */ if (pMessage->ip_summed == CHECKSUM_HW) { - pTxd->TBControl = TX_CTRL_OWN_BMU | - TX_CTRL_SOFTWARE | - TX_CTRL_ST_FWD; - - /* We have to use the opcode for tcp here because the opcode for - udp is not working in the hardware yet (revision 2.0)*/ - if ((protocol == 17) && (pAC->GIni.GIChipRev != 0)) - pTxd->TBControl |= BMU_UDP_CHECK ; - else - pTxd->TBControl |= BMU_TCP_CHECK ; - + pTxd->TBControl = BMU_OWN | BMU_SW | BMU_STFWD; + /* + ** We have to use the opcode for tcp here because the + ** opcode for udp is not working in the hardware yet + ** (revision 2.0) + */ + if ((Protocol == C_PROTO_ID_UDP) && + (pAC->GIni.GIChipRev == 0) && + (pAC->GIni.GIChipId == CHIP_ID_YUKON)) { + pTxd->TBControl |= BMU_TCP_CHECK; + } else { + pTxd->TBControl |= BMU_UDP_CHECK; + } } else { - pTxd->TBControl = TX_CTRL_CHECK_DEFAULT | - TX_CTRL_SOFTWARE | - TX_CTRL_OWN_BMU; + pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_OWN; } - /* Last fragment */ - if( (i+1) == skb_shinfo(pMessage)->nr_frags ) { + /* + ** Do we have the last fragment? + */ + if( (CurrFrag+1) == skb_shinfo(pMessage)->nr_frags ) { #ifdef USE_TX_COMPLETE - pTxd->TBControl |= TX_CTRL_EOF | - TX_CTRL_EOF_IRQ | - sk_frag->size; + pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF | sk_frag->size; #else - pTxd->TBControl |= TX_CTRL_EOF | - sk_frag->size; + pTxd->TBControl |= BMU_EOF | sk_frag->size; #endif - pTxdFst->TBControl |= TX_CTRL_OWN_BMU | - TX_CTRL_SOFTWARE; + pTxdFst->TBControl |= BMU_OWN | BMU_SW; } else { pTxd->TBControl |= sk_frag->size; } pTxdLst = pTxd; - pTxd = pTxd->pNextTxd; + pTxd = pTxd->pNextTxd; pTxPort->TxdRingFree--; BytesSend += sk_frag->size; } - if ((pTxPort->pTxdRingPrev->TBControl & TX_CTRL_OWN_BMU) == 0) { - /* previous descriptor already done, so give tx start cmd */ - /* StartTx(pAC, pTxPort->HwAddr); */ - SK_OUT8(pTxPort->HwAddr, TX_Q_CTRL, TX_Q_CTRL_START); + /* + ** If previous descriptor already done, give TX start cmd + */ + if ((pTxPort->pTxdRingPrev->TBControl & BMU_OWN) == 0) { + SK_OUT8(pTxPort->HwAddr, Q_CSR, CSR_START); } pTxPort->pTxdRingPrev = pTxdLst; @@ -2349,29 +3375,14 @@ struct sk_buff *pMessage) /* pointer to send-message */ spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); - if (pTxPort->TxdRingFree > 0) + if (pTxPort->TxdRingFree > 0) { return (BytesSend); - else + } else { return (0); -} -#endif - - -void dump_frag( SK_U8 *data, int length) -{ - int i; - - printk("Length: %d\n", length); - for( i=0; i < length; i++ ) { - printk(" %02x", (SK_U8)*(data + i) ); - if( !((i+1) % 20) ) - printk("\n"); } - printk("\n\n"); - } - +#endif /***************************************************************************** * * FreeTxDescriptors - release descriptors from the descriptor ring @@ -2400,44 +3411,48 @@ SK_U32 Control; /* TBControl field of descriptor */ SK_U64 PhysAddr; /* address of DMA mapping */ pNewTail = pTxPort->pTxdRingTail; - pTxd = pNewTail; + pTxd = pNewTail; /* - * loop forever; exits if TX_CTRL_SOFTWARE bit not set in start frame - * or TX_CTRL_OWN_BMU bit set in any frame - */ + ** loop forever; exits if BMU_SW bit not set in start frame + ** or BMU_OWN bit set in any frame + */ while (1) { Control = pTxd->TBControl; - if ((Control & TX_CTRL_SOFTWARE) == 0) { + if ((Control & BMU_SW) == 0) { /* - * software controllable bit is set in first - * fragment when given to BMU. Not set means that - * this fragment was never sent or is already - * freed ( -> ring completely free now). - */ + ** software controllable bit is set in first + ** fragment when given to BMU. Not set means that + ** this fragment was never sent or is already + ** freed ( -> ring completely free now). + */ pTxPort->pTxdRingTail = pTxd; netif_wake_queue(pAC->dev[pTxPort->PortIndex]); return; } - if (Control & TX_CTRL_OWN_BMU) { + if (Control & BMU_OWN) { pTxPort->pTxdRingTail = pTxd; if (pTxPort->TxdRingFree > 0) { netif_wake_queue(pAC->dev[pTxPort->PortIndex]); } return; } - - /* release the DMA mapping */ + + /* + ** release the DMA mapping, because until not unmapped + ** this buffer is considered being under control of the + ** adapter card! + */ PhysAddr = ((SK_U64) pTxd->VDataHigh) << (SK_U64) 32; PhysAddr |= (SK_U64) pTxd->VDataLow; pci_unmap_page(pAC->PciDev, PhysAddr, pTxd->pMBuf->len, PCI_DMA_TODEVICE); - if (Control & TX_CTRL_EOF) + if (Control & BMU_EOF) DEV_KFREE_SKB_ANY(pTxd->pMBuf); /* free message */ pTxPort->TxdRingFree++; - pTxd->TBControl &= ~TX_CTRL_SOFTWARE; + pTxd->TBControl &= ~BMU_SW; pTxd = pTxd->pNextTxd; /* point behind fragment with EOF */ } /* while(forever) */ } /* FreeTxDescriptors */ @@ -2455,7 +3470,7 @@ SK_U64 PhysAddr; /* address of DMA mapping */ * Description of rx ring structure: * head - points to the descriptor which will be used next by the BMU * tail - points to the next descriptor to give to the BMU - * + * * Returns: N/A */ static void FillRxRing( @@ -2495,7 +3510,7 @@ RXD *pRxd; /* the rxd to fill */ SK_U16 Length; /* data fragment length */ SK_U64 PhysAddr; /* physical address of a rx buffer */ - pMsgBlock = alloc_skb(pAC->RxBufSize, GFP_ATOMIC); + pMsgBlock = alloc_skb(pRxPort->RxBufSize, GFP_ATOMIC); if (pMsgBlock == NULL) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, @@ -2509,22 +3524,26 @@ SK_U64 PhysAddr; /* physical address of a rx buffer */ pRxd = pRxPort->pRxdRingTail; pRxPort->pRxdRingTail = pRxd->pNextRxd; pRxPort->RxdRingFree--; - Length = pAC->RxBufSize; -#if 0 + Length = pRxPort->RxBufSize; +#if 0 /* uboot */ PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, virt_to_page(pMsgBlock->data), ((unsigned long) pMsgBlock->data & ~PAGE_MASK), - pAC->RxBufSize - 2, + pRxPort->RxBufSize - 2, PCI_DMA_FROMDEVICE); + #else - PhysAddr = (SK_U64) pci_phys_to_mem(pAC->PciDev, (u32)pMsgBlock->data); + PhysAddr = (SK_U64)(SK_U32)pMsgBlock->data; #endif - pRxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pRxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); pRxd->VDataHigh = (SK_U32) (PhysAddr >> 32); - pRxd->pMBuf = pMsgBlock; - pRxd->RBControl = RX_CTRL_OWN_BMU | RX_CTRL_STF | - RX_CTRL_EOF_IRQ | RX_CTRL_CHECK_CSUM | Length; + pRxd->pMBuf = pMsgBlock; + pRxd->RBControl = BMU_OWN | + BMU_STF | + BMU_IRQ_EOF | + BMU_TCP_CHECK | + Length; return (SK_TRUE); } /* FillRxDescriptor */ @@ -2554,16 +3573,19 @@ SK_U16 Length; /* data fragment length */ pRxd = pRxPort->pRxdRingTail; pRxPort->pRxdRingTail = pRxd->pNextRxd; pRxPort->RxdRingFree--; - Length = pAC->RxBufSize; - pRxd->VDataLow = PhysLow; + Length = pRxPort->RxBufSize; + + pRxd->VDataLow = PhysLow; pRxd->VDataHigh = PhysHigh; - pRxd->pMBuf = pMsg; - pRxd->RBControl = RX_CTRL_OWN_BMU | RX_CTRL_STF | - RX_CTRL_EOF_IRQ | RX_CTRL_CHECK_CSUM | Length; + pRxd->pMBuf = pMsg; + pRxd->RBControl = BMU_OWN | + BMU_STF | + BMU_IRQ_EOF | + BMU_TCP_CHECK | + Length; return; } /* ReQueueRxBuffer */ - /***************************************************************************** * * ReceiveIrq - handle a receive IRQ @@ -2575,42 +3597,50 @@ SK_U16 Length; /* data fragment length */ * * Returns: N/A */ -#if 0 +#if 0 /* uboot */ static void ReceiveIrq( #else void ReceiveIrq( #endif - SK_AC *pAC, /* pointer to adapter context */ - RX_PORT *pRxPort, /* pointer to receive port struct */ - SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */ -{ -RXD *pRxd; /* pointer to receive descriptors */ -SK_U32 Control; /* control field of descriptor */ -struct sk_buff *pMsg; /* pointer to message holding frame */ -struct sk_buff *pNewMsg; /* pointer to a new message for copying frame */ -int FrameLength; /* total length of received frame */ -SK_MBUF *pRlmtMbuf; /* ptr to a buffer for giving a frame to rlmt */ -SK_EVPARA EvPara; /* an event parameter union */ -unsigned long Flags; /* for spin lock */ -int PortIndex = pRxPort->PortIndex; -unsigned int Offset; -unsigned int NumBytes; -unsigned int ForRlmt; -SK_BOOL IsBc; -SK_BOOL IsMc; -SK_BOOL IsBadFrame; /* Bad frame */ - -SK_U32 FrameStat; -unsigned short Csum1; -unsigned short Csum2; -unsigned short Type; -#if 0 -int Result; +#ifdef CONFIG_SK98LIN_NAPI +SK_AC *pAC, /* pointer to adapter context */ +RX_PORT *pRxPort, /* pointer to receive port struct */ +SK_BOOL SlowPathLock, /* indicates if SlowPathLock is needed */ +int *WorkDone, +int WorkToDo) +#else +SK_AC *pAC, /* pointer to adapter context */ +RX_PORT *pRxPort, /* pointer to receive port struct */ +SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */ #endif -SK_U64 PhysAddr; +{ + RXD *pRxd; /* pointer to receive descriptors */ + struct sk_buff *pMsg; /* pointer to message holding frame */ + struct sk_buff *pNewMsg; /* pointer to new message for frame copy */ + SK_MBUF *pRlmtMbuf; /* ptr to buffer for giving frame to RLMT */ + SK_EVPARA EvPara; /* an event parameter union */ + SK_U32 Control; /* control field of descriptor */ + unsigned long Flags; /* for spin lock handling */ + int PortIndex = pRxPort->PortIndex; + int FrameLength; /* total length of received frame */ + int IpFrameLength; /* IP length of the received frame */ + unsigned int Offset; + unsigned int NumBytes; + unsigned int RlmtNotifier; + SK_BOOL IsBc; /* we received a broadcast packet */ + SK_BOOL IsMc; /* we received a multicast packet */ + SK_BOOL IsBadFrame; /* the frame received is bad! */ + SK_U32 FrameStat; + unsigned short Csum1; + unsigned short Csum2; + unsigned short Type; +#if 0 /* uboot */ + int Result; +#endif + SK_U64 PhysAddr; -rx_start: - /* do forever; exit if RX_CTRL_OWN_BMU found */ +rx_start: + /* do forever; exit if BMU_OWN found */ for ( pRxd = pRxPort->pRxdRingHead ; pRxPort->RxdRingFree < pAC->RxDescrPerRing ; pRxd = pRxd->pNextRxd, @@ -2628,9 +3658,16 @@ rx_start: */ Control = pRxd->RBControl; + +#ifdef CONFIG_SK98LIN_NAPI + if (*WorkDone >= WorkToDo) { + break; + } + (*WorkDone)++; +#endif /* check if this descriptor is ready */ - if ((Control & RX_CTRL_OWN_BMU) != 0) { + if ((Control & BMU_OWN) != 0) { /* this descriptor is not yet ready */ /* This is the usual end of the loop */ /* We don't need to start the ring again */ @@ -2639,14 +3676,13 @@ rx_start: } /* get length of frame and check it */ - FrameLength = Control & RX_CTRL_LEN_MASK; - if (FrameLength > pAC->RxBufSize) { + FrameLength = Control & BMU_BBC; + if (FrameLength > pRxPort->RxBufSize) { goto rx_failed; } /* check for STF and EOF */ - if ((Control & (RX_CTRL_STF | RX_CTRL_EOF)) != - (RX_CTRL_STF | RX_CTRL_EOF)) { + if ((Control & (BMU_STF | BMU_EOF)) != (BMU_STF | BMU_EOF)) { goto rx_failed; } @@ -2656,8 +3692,8 @@ rx_start: FrameStat = pRxd->FrameStat; /* check for frame length mismatch */ -#define XMR_FS_LEN_SHIFT 18 -#define GMR_FS_LEN_SHIFT 16 +#define XMR_FS_LEN_SHIFT 18 +#define GMR_FS_LEN_SHIFT 16 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { if (FrameLength != (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, @@ -2667,8 +3703,7 @@ rx_start: (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT))); goto rx_failed; } - } - else { + } else { if (FrameLength != (SK_U32) (FrameStat >> GMR_FS_LEN_SHIFT)) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, @@ -2700,8 +3735,7 @@ rx_start: pRxPort->RxdRingFree)); /* DumpMsg(pMsg, "Rx"); */ - if ((Control & RX_CTRL_STAT_VALID) != RX_CTRL_STAT_VALID || - (IsBadFrame)) { + if ((Control & BMU_STAT_VAL) != BMU_STAT_VAL || (IsBadFrame)) { #if 0 (FrameStat & (XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0) { #endif @@ -2737,7 +3771,6 @@ rx_start: skb_put(pNewMsg, FrameLength); PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; PhysAddr |= (SK_U64) pRxd->VDataLow; - pci_dma_sync_single(pAC->PciDev, (dma_addr_t) PhysAddr, FrameLength, @@ -2746,111 +3779,100 @@ rx_start: FrameLength, 0); ReQueueRxBuffer(pAC, pRxPort, pMsg, pRxd->VDataHigh, pRxd->VDataLow); + pMsg = pNewMsg; - } - else { + } else { /* * if large frame, or SKB allocation failed, pass * the SKB directly to the networking */ - PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; PhysAddr |= (SK_U64) pRxd->VDataLow; /* release the DMA mapping */ pci_unmap_single(pAC->PciDev, PhysAddr, - pAC->RxBufSize - 2, + pRxPort->RxBufSize - 2, PCI_DMA_FROMDEVICE); - - /* set length in message */ - skb_put(pMsg, FrameLength); - /* hardware checksum */ - Type = ntohs(*((short*)&pMsg->data[12])); - if (Type == 0x800) { - Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff); - Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff); -#if 0 - if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) && - (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) || - (pAC->GIni.GIChipId == CHIP_ID_YUKON)) { - Result = SkCsGetReceiveInfo(pAC, - &pMsg->data[14], - Csum1, Csum2, pRxPort->PortIndex); - if (Result == - SKCS_STATUS_IP_FRAGMENT || - Result == - SKCS_STATUS_IP_CSUM_OK || - Result == - SKCS_STATUS_TCP_CSUM_OK || - Result == - SKCS_STATUS_UDP_CSUM_OK) { - pMsg->ip_summed = - CHECKSUM_UNNECESSARY; - } else { - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, - SK_DBGCAT_DRV_RX_PROGRESS, - ("skge: CRC error. Frame dropped!\n")); - goto rx_failed; - } - }/* checksumControl calculation valid */ + skb_put(pMsg, FrameLength); /* set message len */ +#if 0 /* uboot */ + pMsg->ip_summed = CHECKSUM_NONE; /* initial default */ #endif - } /* IP frame */ + + if (pRxPort->UseRxCsum) { + Type = ntohs(*((short*)&pMsg->data[12])); + if (Type == 0x800) { + IpFrameLength = (int) ntohs((unsigned short) + ((unsigned short *) pMsg->data)[8]); + if ((FrameLength - IpFrameLength) == 0xe) { + Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff); + Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff); +#if 0 /* uboot */ + if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) && + (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) || + (pAC->ChipsetType)) { + Result = SkCsGetReceiveInfo(pAC, &pMsg->data[14], + Csum1, Csum2, PortIndex); + if ((Result == SKCS_STATUS_IP_FRAGMENT) || + (Result == SKCS_STATUS_IP_CSUM_OK) || + (Result == SKCS_STATUS_TCP_CSUM_OK) || + (Result == SKCS_STATUS_UDP_CSUM_OK)) { + pMsg->ip_summed = CHECKSUM_UNNECESSARY; + } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR) || + (Result == SKCS_STATUS_UDP_CSUM_ERROR) || + (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) || + (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) || + (Result == SKCS_STATUS_IP_CSUM_ERROR)) { + /* HW Checksum error */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("skge: CRC error. Frame dropped!\n")); + goto rx_failed; + } else { + pMsg->ip_summed = CHECKSUM_NONE; + } + }/* checksumControl calculation valid */ +#endif + } /* Frame length check */ + } /* IP frame */ + } /* pRxPort->UseRxCsum */ } /* frame > SK_COPY_TRESHOLD */ - + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("V")); - ForRlmt = SK_RLMT_RX_PROTOCOL; -#if 0 - IsBc = (FrameStat & XMR_FS_BC)==XMR_FS_BC; -#endif + RlmtNotifier = SK_RLMT_RX_PROTOCOL; SK_RLMT_PRE_LOOKAHEAD(pAC, PortIndex, FrameLength, - IsBc, &Offset, &NumBytes); + IsBc, &Offset, &NumBytes); if (NumBytes != 0) { -#if 0 - IsMc = (FrameStat & XMR_FS_MC)==XMR_FS_MC; -#endif - SK_RLMT_LOOKAHEAD(pAC, PortIndex, - &pMsg->data[Offset], - IsBc, IsMc, &ForRlmt); + SK_RLMT_LOOKAHEAD(pAC,PortIndex,&pMsg->data[Offset], + IsBc,IsMc,&RlmtNotifier); } - if (ForRlmt == SK_RLMT_RX_PROTOCOL) { - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W")); + if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W")); /* send up only frames from active port */ - if ((PortIndex == pAC->ActivePort) || - (pAC->RlmtNets == 2)) { - /* frame for upper layer */ + if ((PortIndex == pAC->ActivePort)||(pAC->RlmtNets == 2)) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("U")); #ifdef xDEBUG DumpMsg(pMsg, "Rx"); #endif - SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC, - FrameLength, pRxPort->PortIndex); - -#if 0 - pMsg->dev = pAC->dev[pRxPort->PortIndex]; - pMsg->protocol = eth_type_trans(pMsg, - pAC->dev[pRxPort->PortIndex]); - netif_rx(pMsg); - pAC->dev[pRxPort->PortIndex]->last_rx = jiffies; +#if 0 /* uboot */ + SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,FrameLength,PortIndex); + pMsg->dev = pAC->dev[PortIndex]; + pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]); + netif_rx(pMsg); /* frame for upper layer */ + pAC->dev[PortIndex]->last_rx = jiffies; #else - NetReceive(pMsg->data, pMsg->len); - dev_kfree_skb_any(pMsg); + NetReceive(pMsg->data, pMsg->len); + dev_kfree_skb_any(pMsg); #endif - } - else { - /* drop frame */ + } else { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, - SK_DBGCAT_DRV_RX_PROGRESS, - ("D")); - DEV_KFREE_SKB(pMsg); + SK_DBGCAT_DRV_RX_PROGRESS,("D")); + DEV_KFREE_SKB(pMsg); /* drop frame */ } - - } /* if not for rlmt */ - else { - /* packet for rlmt */ + } else { /* packet for RLMT stack */ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, - SK_DBGCAT_DRV_RX_PROGRESS, ("R")); + SK_DBGCAT_DRV_RX_PROGRESS,("R")); pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC, pAC->IoBase, FrameLength); if (pRlmtMbuf != NULL) { @@ -2878,37 +3900,26 @@ rx_start: } SK_DBG_MSG(NULL, SK_DBGMOD_DRV, - SK_DBGCAT_DRV_RX_PROGRESS, - ("Q")); + SK_DBGCAT_DRV_RX_PROGRESS,("Q")); } -#if 0 - if ((pAC->dev[pRxPort->PortIndex]->flags & - (IFF_PROMISC | IFF_ALLMULTI)) != 0 || - (ForRlmt & SK_RLMT_RX_PROTOCOL) == - SK_RLMT_RX_PROTOCOL) { - pMsg->dev = pAC->dev[pRxPort->PortIndex]; - pMsg->protocol = eth_type_trans(pMsg, - pAC->dev[pRxPort->PortIndex]); +#if 0 /* uboot */ + if ((pAC->dev[PortIndex]->flags & (IFF_PROMISC | IFF_ALLMULTI)) || + (RlmtNotifier & SK_RLMT_RX_PROTOCOL)) { + pMsg->dev = pAC->dev[PortIndex]; + pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]); netif_rx(pMsg); - pAC->dev[pRxPort->PortIndex]->last_rx = jiffies; - } + pAC->dev[PortIndex]->last_rx = jiffies; #else if (0) { - } #endif - else { + } else { DEV_KFREE_SKB(pMsg); } - - } /* if packet for rlmt */ + } /* if packet for RLMT stack */ } /* for ... scanning the RXD ring */ /* RXD ring is empty -> fill and restart */ FillRxRing(pAC, pRxPort); - /* do not start if called from Close */ - if (pAC->BoardLevel > 0) { - ClearAndStartRx(pAC, PortIndex); - } return; rx_failed: @@ -2922,7 +3933,7 @@ rx_failed: PhysAddr |= (SK_U64) pRxd->VDataLow; pci_unmap_page(pAC->PciDev, PhysAddr, - pAC->RxBufSize - 2, + pRxPort->RxBufSize - 2, PCI_DMA_FROMDEVICE); DEV_KFREE_SKB_IRQ(pRxd->pMBuf); pRxd->pMBuf = NULL; @@ -2932,47 +3943,6 @@ rx_failed: } /* ReceiveIrq */ - -/***************************************************************************** - * - * ClearAndStartRx - give a start receive command to BMU, clear IRQ - * - * Description: - * This function sends a start command and a clear interrupt - * command for one receive queue to the BMU. - * - * Returns: N/A - * none - */ -static void ClearAndStartRx( -SK_AC *pAC, /* pointer to the adapter context */ -int PortIndex) /* index of the receive port (XMAC) */ -{ - SK_OUT8(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_CTRL, - RX_Q_CTRL_START | RX_Q_CTRL_CLR_I_EOF); -} /* ClearAndStartRx */ - - -/***************************************************************************** - * - * ClearTxIrq - give a clear transmit IRQ command to BMU - * - * Description: - * This function sends a clear tx IRQ command for one - * transmit queue to the BMU. - * - * Returns: N/A - */ -static void ClearTxIrq( -SK_AC *pAC, /* pointer to the adapter context */ -int PortIndex, /* index of the transmit port (XMAC) */ -int Prio) /* priority or normal queue */ -{ - SK_OUT8(pAC->IoBase, TxQueueAddr[PortIndex][Prio]+TX_Q_CTRL, - TX_Q_CTRL_CLR_I_EOF); -} /* ClearTxIrq */ - - /***************************************************************************** * * ClearRxRing - remove all buffers from the receive ring @@ -3003,12 +3973,12 @@ SK_U64 PhysAddr; PhysAddr |= (SK_U64) pRxd->VDataLow; pci_unmap_page(pAC->PciDev, PhysAddr, - pAC->RxBufSize - 2, + pRxPort->RxBufSize - 2, PCI_DMA_FROMDEVICE); DEV_KFREE_SKB(pRxd->pMBuf); pRxd->pMBuf = NULL; } - pRxd->RBControl &= RX_CTRL_OWN_BMU; + pRxd->RBControl &= BMU_OWN; pRxd = pRxd->pNextRxd; pRxPort->RxdRingFree++; } while (pRxd != pRxPort->pRxdRingTail); @@ -3016,7 +3986,6 @@ SK_U64 PhysAddr; spin_unlock_irqrestore(&pRxPort->RxDesRingLock, Flags); } /* ClearRxRing */ - /***************************************************************************** * * ClearTxRing - remove all buffers from the transmit ring @@ -3041,108 +4010,14 @@ unsigned long Flags; spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags); pTxd = pTxPort->pTxdRingHead; for (i=0; iTxDescrPerRing; i++) { - pTxd->TBControl &= ~TX_CTRL_OWN_BMU; + pTxd->TBControl &= ~BMU_OWN; pTxd = pTxd->pNextTxd; } FreeTxDescriptors(pAC, pTxPort); spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); } /* ClearTxRing */ - -#if 0 -/***************************************************************************** - * - * SetQueueSizes - configure the sizes of rx and tx queues - * - * Description: - * This function assigns the sizes for active and passive port - * to the appropriate HWinit structure variables. - * The passive port(s) get standard values, all remaining RAM - * is given to the active port. - * The queue sizes are in kbyte and must be multiple of 8. - * The limits for the number of buffers filled into the rx rings - * is also set in this routine. - * - * Returns: - * none - */ -static void SetQueueSizes( -SK_AC *pAC) /* pointer to the adapter context */ -{ -int StandbyRam; /* adapter RAM used for a standby port */ -int RemainingRam; /* adapter RAM available for the active port */ -int RxRam; /* RAM used for the active port receive queue */ -int i; /* loop counter */ - -if (pAC->RlmtNets == 1) { - StandbyRam = SK_RLMT_STANDBY_QRXSIZE + SK_RLMT_STANDBY_QXASIZE + - SK_RLMT_STANDBY_QXSSIZE; - RemainingRam = pAC->GIni.GIRamSize - - (pAC->GIni.GIMacsFound-1) * StandbyRam; - for (i=0; iGIni.GIMacsFound; i++) { - pAC->GIni.GP[i].PRxQSize = SK_RLMT_STANDBY_QRXSIZE; - pAC->GIni.GP[i].PXSQSize = SK_RLMT_STANDBY_QXSSIZE; - pAC->GIni.GP[i].PXAQSize = SK_RLMT_STANDBY_QXASIZE; - } - RxRam = (RemainingRam * 8 / 10) & ~7; - pAC->GIni.GP[pAC->ActivePort].PRxQSize = RxRam; - pAC->GIni.GP[pAC->ActivePort].PXSQSize = 0; - pAC->GIni.GP[pAC->ActivePort].PXAQSize = - (RemainingRam - RxRam) & ~7; - pAC->RxQueueSize = RxRam; - pAC->TxSQueueSize = 0; - pAC->TxAQueueSize = (RemainingRam - RxRam) & ~7; - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, - ("queue sizes settings - rx:%d txA:%d txS:%d\n", - pAC->RxQueueSize,pAC->TxAQueueSize, pAC->TxSQueueSize)); -} else { - RemainingRam = pAC->GIni.GIRamSize/pAC->GIni.GIMacsFound; - RxRam = (RemainingRam * 8 / 10) & ~7; - for (i=0; iGIni.GIMacsFound; i++) { - pAC->GIni.GP[i].PRxQSize = RxRam; - pAC->GIni.GP[i].PXSQSize = 0; - pAC->GIni.GP[i].PXAQSize = (RemainingRam - RxRam) & ~7; - } - - pAC->RxQueueSize = RxRam; - pAC->TxSQueueSize = 0; - pAC->TxAQueueSize = (RemainingRam - RxRam) & ~7; -} - for (i=0; iRxPort[i].RxFillLimit = pAC->RxDescrPerRing; - } - - if (pAC->RlmtNets == 2) { - for (i=0; iGIni.GIMacsFound; i++) { - pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing - 100; - } - } else { - for (i=0; iGIni.GIMacsFound; i++) { - pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing - 100; - } - /* - * Do not set the Limit to 0, because this could cause - * wrap around with ReQueue'ed buffers (a buffer could - * be requeued in the same position, made accessable to - * the hardware, and the hardware could change its - * contents! - */ - pAC->RxPort[pAC->ActivePort].RxFillLimit = 1; - } - -#ifdef DEBUG - for (i=0; iGIni.GIMacsFound; i++) { - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, - ("i: %d, RxQSize: %d, PXSQsize: %d, PXAQSize: %d\n", - i, - pAC->GIni.GP[i].PRxQSize, - pAC->GIni.GP[i].PXSQSize, - pAC->GIni.GP[i].PXAQSize)); - } -#endif -} /* SetQueueSizes */ - - +#if 0 /* uboot */ /***************************************************************************** * * SkGeSetMacAddr - Set the hardware MAC address @@ -3159,31 +4034,32 @@ static int SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p) DEV_NET *pNet = (DEV_NET*) dev->priv; SK_AC *pAC = pNet->pAC; +int Ret; struct sockaddr *addr = p; unsigned long Flags; - + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeSetMacAddr starts now...\n")); - if(netif_running(dev)) - return -EBUSY; memcpy(dev->dev_addr, addr->sa_data,dev->addr_len); - + spin_lock_irqsave(&pAC->SlowPathLock, Flags); if (pAC->RlmtNets == 2) - SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr, + Ret = SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr, (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS); else - SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort, + Ret = SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort, (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS); - - + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + if (Ret != SK_ADDR_OVERRIDE_SUCCESS) + return -EBUSY; + return 0; } /* SkGeSetMacAddr */ -#endif /***************************************************************************** @@ -3200,7 +4076,6 @@ unsigned long Flags; * 0, if everything is ok * !=0, on error */ -#if 0 static void SkGeSetRxMode(struct SK_NET_DEVICE *dev) { @@ -3240,7 +4115,7 @@ unsigned long Flags; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("Number of MC entries: %d ", dev->mc_count)); - + pMcList = dev->mc_list; for (i=0; imc_count; i++, pMcList = pMcList->next) { SkAddrMcAdd(pAC, pAC->IoBase, PortIdx, @@ -3257,11 +4132,50 @@ unsigned long Flags; SkAddrMcUpdate(pAC, pAC->IoBase, PortIdx); } spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - + return; } /* SkGeSetRxMode */ +/***************************************************************************** + * + * SkSetMtuBufferSize - set the MTU buffer to another value + * + * Description: + * This function sets the new buffers and is called whenever the MTU + * size is changed + * + * Returns: + * N/A + */ + +static void SkSetMtuBufferSize( +SK_AC *pAC, /* pointer to adapter context */ +int PortNr, /* Port number */ +int Mtu) /* pointer to tx prt struct */ +{ + pAC->RxPort[PortNr].RxBufSize = Mtu + 32; + + /* RxBufSize must be a multiple of 8 */ + while (pAC->RxPort[PortNr].RxBufSize % 8) { + pAC->RxPort[PortNr].RxBufSize = + pAC->RxPort[PortNr].RxBufSize + 1; + } + + if (Mtu > 1500) { + pAC->GIni.GP[PortNr].PPortUsage = SK_JUMBO_LINK; + } else { + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { + pAC->GIni.GP[PortNr].PPortUsage = SK_MUL_LINK; + } else { + pAC->GIni.GP[PortNr].PPortUsage = SK_RED_LINK; + } + } + + return; +} + + /***************************************************************************** * * SkGeChangeMtu - set the MTU to another value @@ -3277,212 +4191,107 @@ unsigned long Flags; */ static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int NewMtu) { -DEV_NET *pNet; -DEV_NET *pOtherNet; -SK_AC *pAC; -unsigned long Flags; -int i; -SK_EVPARA EvPara; +DEV_NET *pNet; +SK_AC *pAC; +unsigned long Flags; +#ifdef CONFIG_SK98LIN_NAPI +int WorkToDo = 1; // min(*budget, dev->quota); +int WorkDone = 0; +#endif SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeChangeMtu starts now...\n")); pNet = (DEV_NET*) dev->priv; - pAC = pNet->pAC; + pAC = pNet->pAC; + /* MTU size outside the spec */ if ((NewMtu < 68) || (NewMtu > SK_JUMBO_MTU)) { return -EINVAL; } - if(pAC->BoardLevel != 2) { + /* MTU > 1500 on yukon ulra not allowed */ + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) + && (NewMtu > 1500)){ return -EINVAL; } - pNet->Mtu = NewMtu; - pOtherNet = (DEV_NET*)pAC->dev[1 - pNet->NetNr]->priv; - if ((pOtherNet->Mtu > 1500) && (NewMtu <= 1500) && (pOtherNet->Up==1)) { - return(0); + /* Diag access active */ + if (pAC->DiagModeActive == DIAG_ACTIVE) { + if (pAC->DiagFlowCtrl == SK_FALSE) { + return -1; /* still in use, deny any actions of MTU */ + } else { + pAC->DiagFlowCtrl = SK_FALSE; + } } - EvPara.Para32[0] = pNet->NetNr; - EvPara.Para32[1] = -1; - - pAC->RxBufSize = NewMtu + 32; dev->mtu = NewMtu; + SkSetMtuBufferSize(pAC, pNet->PortNr, NewMtu); - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, - ("New MTU: %d\n", NewMtu)); + if(!netif_running(dev)) { + /* Preset MTU size if device not ready/running */ + return 0; + } - /* prevent reconfiguration while changing the MTU */ - - /* disable interrupts */ + /* Prevent any reconfiguration while changing the MTU + by disabling any interrupts */ SK_OUT32(pAC->IoBase, B0_IMSK, 0); spin_lock_irqsave(&pAC->SlowPathLock, Flags); - /* Found more than one port */ - if ((pAC->GIni.GIMacsFound == 2 ) && - (pAC->RlmtNets == 2)) { - /* Stop both ports */ - EvPara.Para32[0] = 0; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); - EvPara.Para32[0] = 1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + /* Notify RLMT that the port has to be stopped */ + netif_stop_queue(dev); + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, + pNet->PortNr, -1, SK_TRUE); + spin_lock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock); + + + /* Change RxFillLimit to 1 */ + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { + pAC->RxPort[pNet->PortNr].RxFillLimit = 1; } else { - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + pAC->RxPort[1 - pNet->PortNr].RxFillLimit = 1; + pAC->RxPort[pNet->PortNr].RxFillLimit = pAC->RxDescrPerRing - + (pAC->RxDescrPerRing / 4); } - SkEventDispatcher(pAC, pAC->IoBase); - - for (i=0; iGIni.GIMacsFound; i++) { - spin_lock_irqsave( - &pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock, Flags); - netif_stop_queue(pAC->dev[i]); - - } - - /* - * adjust number of rx buffers allocated - */ - if (NewMtu > 1500) { - /* use less rx buffers */ - for (i=0; iGIni.GIMacsFound; i++) { - /* Found more than one port */ - if ((pAC->GIni.GIMacsFound == 2 ) && - (pAC->RlmtNets == 2)) { - pAC->RxPort[i].RxFillLimit = - pAC->RxDescrPerRing - 100; - } else { - if (i == pAC->ActivePort) - pAC->RxPort[i].RxFillLimit = - pAC->RxDescrPerRing - 100; - else - pAC->RxPort[i].RxFillLimit = - pAC->RxDescrPerRing - 10; - } - } - } - else { - /* use normal amount of rx buffers */ - for (i=0; iGIni.GIMacsFound; i++) { - /* Found more than one port */ - if ((pAC->GIni.GIMacsFound == 2 ) && - (pAC->RlmtNets == 2)) { - pAC->RxPort[i].RxFillLimit = 1; - } else { - if (i == pAC->ActivePort) - pAC->RxPort[i].RxFillLimit = 1; - else - pAC->RxPort[i].RxFillLimit = - pAC->RxDescrPerRing - 100; - } - } - } - - SkGeDeInit(pAC, pAC->IoBase); - - /* - * enable/disable hardware support for long frames - */ - if (NewMtu > 1500) { -/* pAC->JumboActivated = SK_TRUE; /#* is never set back !!! */ - pAC->GIni.GIPortUsage = SK_JUMBO_LINK; - } - else { - if ((pAC->GIni.GIMacsFound == 2 ) && - (pAC->RlmtNets == 2)) { - pAC->GIni.GIPortUsage = SK_MUL_LINK; - } else { - pAC->GIni.GIPortUsage = SK_RED_LINK; - } - } - - SkGeInit( pAC, pAC->IoBase, 1); - SkI2cInit( pAC, pAC->IoBase, 1); - SkEventInit(pAC, pAC->IoBase, 1); - SkPnmiInit( pAC, pAC->IoBase, 1); - SkAddrInit( pAC, pAC->IoBase, 1); - SkRlmtInit( pAC, pAC->IoBase, 1); - SkTimerInit(pAC, pAC->IoBase, 1); - - /* - * tschilling: - * Speed and others are set back to default in level 1 init! - */ - GetConfiguration(pAC); - - SkGeInit( pAC, pAC->IoBase, 2); - SkI2cInit( pAC, pAC->IoBase, 2); - SkEventInit(pAC, pAC->IoBase, 2); - SkPnmiInit( pAC, pAC->IoBase, 2); - SkAddrInit( pAC, pAC->IoBase, 2); - SkRlmtInit( pAC, pAC->IoBase, 2); - SkTimerInit(pAC, pAC->IoBase, 2); - - /* - * clear and reinit the rx rings here - */ - for (i=0; iGIni.GIMacsFound; i++) { - ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE); - ClearRxRing(pAC, &pAC->RxPort[i]); - FillRxRing(pAC, &pAC->RxPort[i]); - - /* Enable transmit descriptor polling. */ - SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE); - FillRxRing(pAC, &pAC->RxPort[i]); - }; - - SkGeYellowLED(pAC, pAC->IoBase, 1); - -#ifdef USE_INT_MOD - { - unsigned long ModBase; - ModBase = 53125000 / INTS_PER_SEC; - SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase); - SK_OUT32(pAC->IoBase, B2_IRQM_MSK, IRQ_MOD_MASK); - SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START); - } + /* clear and reinit the rx rings here, because of new MTU size */ + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST); + SkY2AllocateRxBuffers(pAC, pAC->IoBase, pNet->PortNr); + SkY2PortStart(pAC, pAC->IoBase, pNet->PortNr); + } else { +// SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST); +#ifdef CONFIG_SK98LIN_NAPI + WorkToDo = 1; + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo); +#else + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE); #endif + ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]); + FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]); + + /* Enable transmit descriptor polling */ + SkGePollTxD(pAC, pAC->IoBase, pNet->PortNr, SK_TRUE); + FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]); + } netif_start_queue(pAC->dev[pNet->PortNr]); - for (i=pAC->GIni.GIMacsFound-1; i>=0; i--) { - spin_unlock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock); - } - /* enable Interrupts */ - SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); + spin_unlock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock); + + + /* Notify RLMT about the changing and restarting one (or more) ports */ + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, + pNet->PortNr, -1, SK_TRUE); + + /* Enable Interrupts again */ + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK); - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); - SkEventDispatcher(pAC, pAC->IoBase); - - /* Found more than one port */ - if ((pAC->GIni.GIMacsFound == 2 ) && - (pAC->RlmtNets == 2)) { - /* Start both ports */ - EvPara.Para32[0] = pAC->RlmtNets; - EvPara.Para32[1] = -1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, - EvPara); - - - EvPara.Para32[1] = -1; - EvPara.Para32[0] = pNet->PortNr; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); - - if (pOtherNet->Up) { - EvPara.Para32[0] = pOtherNet->PortNr; - SkEventQueue(pAC, SKGE_RLMT, - SK_RLMT_START, EvPara); - } - } else { - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); - } - - SkEventDispatcher(pAC, pAC->IoBase); spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - return 0; -} /* SkGeChangeMtu */ + +} /***************************************************************************** @@ -3498,66 +4307,67 @@ SK_EVPARA EvPara; */ static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev) { -DEV_NET *pNet = (DEV_NET*) dev->priv; -SK_AC *pAC = pNet->pAC; -SK_PNMI_STRUCT_DATA *pPnmiStruct; /* structure for all Pnmi-Data */ -SK_PNMI_STAT *pPnmiStat; /* pointer to virtual XMAC stat. data */ -SK_PNMI_CONF *pPnmiConf; /* pointer to virtual link config. */ -unsigned int Size; /* size of pnmi struct */ -unsigned long Flags; /* for spin lock */ + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + unsigned long LateCollisions, ExcessiveCollisions, RxTooLong; + unsigned long Flags; /* for spin lock */ + SK_U32 MaxNumOidEntries, Oid, Len; + char Buf[8]; + struct { + SK_U32 Oid; + unsigned long *pVar; + } Vars[] = { + { OID_SKGE_STAT_TX_LATE_COL, &LateCollisions }, + { OID_SKGE_STAT_TX_EXCESS_COL, &ExcessiveCollisions }, + { OID_SKGE_STAT_RX_TOO_LONG, &RxTooLong }, + { OID_SKGE_STAT_RX, &pAC->stats.rx_packets }, + { OID_SKGE_STAT_TX, &pAC->stats.tx_packets }, + { OID_SKGE_STAT_RX_OCTETS, &pAC->stats.rx_bytes }, + { OID_SKGE_STAT_TX_OCTETS, &pAC->stats.tx_bytes }, + { OID_SKGE_RX_NO_BUF_CTS, &pAC->stats.rx_dropped }, + { OID_SKGE_TX_NO_BUF_CTS, &pAC->stats.tx_dropped }, + { OID_SKGE_STAT_RX_MULTICAST, &pAC->stats.multicast }, + { OID_SKGE_STAT_RX_RUNT, &pAC->stats.rx_length_errors }, + { OID_SKGE_STAT_RX_FCS, &pAC->stats.rx_crc_errors }, + { OID_SKGE_STAT_RX_FRAMING, &pAC->stats.rx_frame_errors }, + { OID_SKGE_STAT_RX_OVERFLOW, &pAC->stats.rx_over_errors }, + { OID_SKGE_STAT_RX_MISSED, &pAC->stats.rx_missed_errors }, + { OID_SKGE_STAT_TX_CARRIER, &pAC->stats.tx_carrier_errors }, + { OID_SKGE_STAT_TX_UNDERRUN, &pAC->stats.tx_fifo_errors }, + }; + + if ((pAC->DiagModeActive == DIAG_NOTACTIVE) && + (pAC->BoardLevel == SK_INIT_RUN)) { + memset(&pAC->stats, 0x00, sizeof(pAC->stats)); /* clean first */ + spin_lock_irqsave(&pAC->SlowPathLock, Flags); - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, - ("SkGeStats starts now...\n")); - pPnmiStruct = &pAC->PnmiStruct; - memset(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA)); - spin_lock_irqsave(&pAC->SlowPathLock, Flags); - Size = SK_PNMI_STRUCT_SIZE; - SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, pNet->NetNr); - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - pPnmiStat = &pPnmiStruct->Stat[0]; - pPnmiConf = &pPnmiStruct->Conf[0]; + MaxNumOidEntries = sizeof(Vars) / sizeof(Vars[0]); + for (Oid = 0; Oid < MaxNumOidEntries; Oid++) { + if (SkPnmiGetVar(pAC,pAC->IoBase, Vars[Oid].Oid, + &Buf, &Len, 1, pNet->NetNr) != SK_PNMI_ERR_OK) { + memset(Buf, 0x00, sizeof(Buf)); + } + *Vars[Oid].pVar = (unsigned long) (*((SK_U64 *) Buf)); + } + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - pAC->stats.rx_packets = (SK_U32) pPnmiStruct->RxDeliveredCts & 0xFFFFFFFF; - pAC->stats.tx_packets = (SK_U32) pPnmiStat->StatTxOkCts & 0xFFFFFFFF; - pAC->stats.rx_bytes = (SK_U32) pPnmiStruct->RxOctetsDeliveredCts; - pAC->stats.tx_bytes = (SK_U32) pPnmiStat->StatTxOctetsOkCts; + pAC->stats.collisions = LateCollisions + ExcessiveCollisions; + pAC->stats.tx_errors = pAC->stats.tx_carrier_errors + + pAC->stats.tx_fifo_errors; + pAC->stats.rx_errors = pAC->stats.rx_length_errors + + pAC->stats.rx_crc_errors + + pAC->stats.rx_frame_errors + + pAC->stats.rx_over_errors + + pAC->stats.rx_missed_errors; - if (pNet->Mtu <= 1500) { - pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF; - } else { - pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts - - pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF); + if (dev->mtu > 1500) { + pAC->stats.rx_errors = pAC->stats.rx_errors - RxTooLong; + } } - - if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && pAC->HWRevision < 12) - pAC->stats.rx_errors = pAC->stats.rx_errors - pPnmiStat->StatRxShortsCts; - - pAC->stats.tx_errors = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF; - pAC->stats.rx_dropped = (SK_U32) pPnmiStruct->RxNoBufCts & 0xFFFFFFFF; - pAC->stats.tx_dropped = (SK_U32) pPnmiStruct->TxNoBufCts & 0xFFFFFFFF; - pAC->stats.multicast = (SK_U32) pPnmiStat->StatRxMulticastOkCts & 0xFFFFFFFF; - pAC->stats.collisions = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF; - - /* detailed rx_errors: */ - pAC->stats.rx_length_errors = (SK_U32) pPnmiStat->StatRxRuntCts & 0xFFFFFFFF; - pAC->stats.rx_over_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF; - pAC->stats.rx_crc_errors = (SK_U32) pPnmiStat->StatRxFcsCts & 0xFFFFFFFF; - pAC->stats.rx_frame_errors = (SK_U32) pPnmiStat->StatRxFramingCts & 0xFFFFFFFF; - pAC->stats.rx_fifo_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF; - pAC->stats.rx_missed_errors = (SK_U32) pPnmiStat->StatRxMissedCts & 0xFFFFFFFF; - - /* detailed tx_errors */ - pAC->stats.tx_aborted_errors = (SK_U32) 0; - pAC->stats.tx_carrier_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF; - pAC->stats.tx_fifo_errors = (SK_U32) pPnmiStat->StatTxFifoUnderrunCts & 0xFFFFFFFF; - pAC->stats.tx_heartbeat_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF; - pAC->stats.tx_window_errors = (SK_U32) 0; - return(&pAC->stats); } /* SkGeStats */ - /***************************************************************************** * * SkGeIoctl - IO-control function @@ -3571,30 +4381,37 @@ unsigned long Flags; /* for spin lock */ * 0, if everything is ok * !=0, on error */ -static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd) +static int SkGeIoctl( +struct SK_NET_DEVICE *dev, /* the device the IOCTL is to be performed on */ +struct ifreq *rq, /* additional request structure containing data */ +int cmd) /* requested IOCTL command number */ { -DEV_NET *pNet; -SK_AC *pAC; - -SK_GE_IOCTL Ioctl; -unsigned int Err = 0; -int Size; + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + struct pci_dev *pdev = NULL; + void *pMemBuf; + SK_GE_IOCTL Ioctl; + unsigned long Flags; /* for spin lock */ + unsigned int Err = 0; + unsigned int Length = 0; + int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32); + int Size = 0; + int Ret = 0; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeIoctl starts now...\n")); - pNet = (DEV_NET*) dev->priv; - pAC = pNet->pAC; - if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) { return -EFAULT; } switch(cmd) { - case SK_IOCTL_SETMIB: - case SK_IOCTL_PRESETMIB: + case SIOCETHTOOL: + return SkEthIoctl(dev, rq); + case SK_IOCTL_SETMIB: /* FALL THRU */ + case SK_IOCTL_PRESETMIB: /* FALL THRU (if capable!) */ if (!capable(CAP_NET_ADMIN)) return -EPERM; - case SK_IOCTL_GETMIB: + case SK_IOCTL_GETMIB: if(copy_from_user(&pAC->PnmiStruct, Ioctl.pData, Ioctl.LenPnmiStruct)? Ioctl.Len : sizeof(pAC->PnmiStruct))) { @@ -3610,10 +4427,80 @@ int Size; return -EFAULT; } break; + case SK_IOCTL_GEN: + if (Ioctl.Len < (sizeof(pAC->PnmiStruct) + HeaderLength)) { + Length = Ioctl.Len; + } else { + Length = sizeof(pAC->PnmiStruct) + HeaderLength; + } + if (NULL == (pMemBuf = kmalloc(Length, GFP_KERNEL))) { + return -ENOMEM; + } + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + if(copy_from_user(pMemBuf, Ioctl.pData, Length)) { + Err = -EFAULT; + goto fault_gen; + } + if ((Ret = SkPnmiGenIoctl(pAC, pAC->IoBase, pMemBuf, &Length, 0)) < 0) { + Err = -EFAULT; + goto fault_gen; + } + if(copy_to_user(Ioctl.pData, pMemBuf, Length) ) { + Err = -EFAULT; + goto fault_gen; + } + Ioctl.Len = Length; + if(copy_to_user(rq->ifr_data, &Ioctl, sizeof(SK_GE_IOCTL))) { + Err = -EFAULT; + goto fault_gen; + } +fault_gen: + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + kfree(pMemBuf); /* cleanup everything */ + break; + case SK_IOCTL_DIAG: + if (!capable(CAP_NET_ADMIN)) return -EPERM; + if (Ioctl.Len < (sizeof(pAC->PnmiStruct) + HeaderLength)) { + Length = Ioctl.Len; + } else { + Length = sizeof(pAC->PnmiStruct) + HeaderLength; + } + if (NULL == (pMemBuf = kmalloc(Length, GFP_KERNEL))) { + return -ENOMEM; + } + if(copy_from_user(pMemBuf, Ioctl.pData, Length)) { + Err = -EFAULT; + goto fault_diag; + } + pdev = pAC->PciDev; + Length = 3 * sizeof(SK_U32); /* Error, Bus and Device */ + /* + ** While coding this new IOCTL interface, only a few lines of code + ** are to to be added. Therefore no dedicated function has been + ** added. If more functionality is added, a separate function + ** should be used... + */ + * ((SK_U32 *)pMemBuf) = 0; + * ((SK_U32 *)pMemBuf + 1) = pdev->bus->number; + * ((SK_U32 *)pMemBuf + 2) = ParseDeviceNbrFromSlotName(pci_name(pdev)); + if(copy_to_user(Ioctl.pData, pMemBuf, Length) ) { + Err = -EFAULT; + goto fault_diag; + } + Ioctl.Len = Length; + if(copy_to_user(rq->ifr_data, &Ioctl, sizeof(SK_GE_IOCTL))) { + Err = -EFAULT; + goto fault_diag; + } +fault_diag: + kfree(pMemBuf); /* cleanup everything */ + break; default: Err = -EOPNOTSUPP; } + return(Err); + } /* SkGeIoctl */ @@ -3639,12 +4526,12 @@ DEV_NET *pNet, /* pointer to the adapter context */ unsigned int Size, /* length of ioctl data */ int mode) /* flag for set/preset */ { -unsigned long Flags; /* for spin lock */ -SK_AC *pAC; + SK_AC *pAC = pNet->pAC; + unsigned long Flags; /* for spin lock */ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeIocMib starts now...\n")); - pAC = pNet->pAC; + /* access MIB */ spin_lock_irqsave(&pAC->SlowPathLock, Flags); switch(mode) { @@ -3670,7 +4557,6 @@ SK_AC *pAC; } /* SkGeIocMib */ #endif - /***************************************************************************** * * GetConfiguration - read configuration information @@ -3686,12 +4572,20 @@ static void GetConfiguration( SK_AC *pAC) /* pointer to the adapter context structure */ { SK_I32 Port; /* preferred port */ -int LinkSpeed; /* Link speed */ -int AutoNeg; /* auto negotiation off (0) or on (1) */ -int DuplexCap; /* duplex capabilities (0=both, 1=full, 2=half */ -int MSMode; /* master / slave mode selection */ SK_BOOL AutoSet; SK_BOOL DupSet; +int LinkSpeed = SK_LSPEED_AUTO; /* Link speed */ +int AutoNeg = 1; /* autoneg off (0) or on (1) */ +int DuplexCap = 0; /* 0=both,1=full,2=half */ +int FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; /* FlowControl */ +int MSMode = SK_MS_MODE_AUTO; /* master/slave mode */ +int IrqModMaskOffset = 6; /* all ints moderated=default */ + +SK_BOOL IsConTypeDefined = SK_TRUE; +SK_BOOL IsLinkSpeedDefined = SK_TRUE; +SK_BOOL IsFlowCtrlDefined = SK_TRUE; +SK_BOOL IsRoleDefined = SK_TRUE; +SK_BOOL IsModeDefined = SK_TRUE; /* * The two parameters AutoNeg. and DuplexCap. map to one configuration * parameter. The mapping is described by this table: @@ -3705,399 +4599,732 @@ SK_BOOL DupSet; * Sense | AutoSense | AutoSense | AutoSense | */ int Capabilities[3][3] = - { { -1, SK_LMODE_FULL, SK_LMODE_HALF}, - {SK_LMODE_AUTOBOTH, SK_LMODE_AUTOFULL, SK_LMODE_AUTOHALF}, + { { -1, SK_LMODE_FULL , SK_LMODE_HALF }, + {SK_LMODE_AUTOBOTH , SK_LMODE_AUTOFULL , SK_LMODE_AUTOHALF }, {SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} }; +SK_U32 IrqModMask[7][2] = + { { IRQ_MASK_RX_ONLY , Y2_DRIVER_IRQS }, + { IRQ_MASK_TX_ONLY , Y2_DRIVER_IRQS }, + { IRQ_MASK_SP_ONLY , Y2_SPECIAL_IRQS }, + { IRQ_MASK_SP_RX , Y2_IRQ_MASK }, + { IRQ_MASK_TX_RX , Y2_DRIVER_IRQS }, + { IRQ_MASK_SP_TX , Y2_IRQ_MASK }, + { IRQ_MASK_RX_TX_SP, Y2_IRQ_MASK } }; + #define DC_BOTH 0 #define DC_FULL 1 #define DC_HALF 2 #define AN_OFF 0 #define AN_ON 1 #define AN_SENS 2 +#define M_CurrPort pAC->GIni.GP[Port] - /* settings for port A */ - /* settings link speed */ - LinkSpeed = SK_LSPEED_AUTO; /* default: do auto select */ + + /* + ** Set the default values first for both ports! + */ + for (Port = 0; Port < SK_MAX_MACS; Port++) { + M_CurrPort.PLinkModeConf = Capabilities[AN_ON][DC_BOTH]; + M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + M_CurrPort.PMSMode = SK_MS_MODE_AUTO; + M_CurrPort.PLinkSpeed = SK_LSPEED_AUTO; + } + + /* + ** Check merged parameter ConType. If it has not been used, + ** verify any other parameter (e.g. AutoNeg) and use default values. + ** + ** Stating both ConType and other lowlevel link parameters is also + ** possible. If this is the case, the passed ConType-parameter is + ** overwritten by the lowlevel link parameter. + ** + ** The following settings are used for a merged ConType-parameter: + ** + ** ConType DupCap AutoNeg FlowCtrl Role Speed + ** ------- ------ ------- -------- ---------- ----- + ** Auto Both On SymOrRem Auto Auto + ** 1000FD Full Off None 1000 + ** 100FD Full Off None 100 + ** 100HD Half Off None 100 + ** 10FD Full Off None 10 + ** 10HD Half Off None 10 + ** + ** This ConType parameter is used for all ports of the adapter! + */ + if ( (ConType != NULL) && + (pAC->Index < SK_MAX_CARD_PARAM) && + (ConType[pAC->Index] != NULL) ) { + + /* Check chipset family */ + if ((!pAC->ChipsetType) && + (strcmp(ConType[pAC->Index],"Auto")!=0) && + (strcmp(ConType[pAC->Index],"")!=0)) { + /* Set the speed parameter back */ + printk("sk98lin: Illegal value \"%s\" " + "for ConType." + " Using Auto.\n", + ConType[pAC->Index]); + + sprintf(ConType[pAC->Index], "Auto"); + } + + if ((pAC->GIni.GICopperType != SK_TRUE) && + (strcmp(ConType[pAC->Index],"1000FD") != 0)) { + /* Set the speed parameter back */ + printk("sk98lin: Illegal value \"%s\" " + "for ConType." + " Using Auto.\n", + ConType[pAC->Index]); + + sprintf(ConType[pAC->Index], "Auto"); + } + + if (strcmp(ConType[pAC->Index],"")==0) { + IsConTypeDefined = SK_FALSE; /* No ConType defined */ + } else if (strcmp(ConType[pAC->Index],"Auto")==0) { + for (Port = 0; Port < SK_MAX_MACS; Port++) { + M_CurrPort.PLinkModeConf = Capabilities[AN_ON][DC_BOTH]; + M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + M_CurrPort.PMSMode = SK_MS_MODE_AUTO; + M_CurrPort.PLinkSpeed = SK_LSPEED_AUTO; + } + } else if (strcmp(ConType[pAC->Index],"1000FD")==0) { + for (Port = 0; Port < SK_MAX_MACS; Port++) { + M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL]; + M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE; + M_CurrPort.PMSMode = SK_MS_MODE_AUTO; + M_CurrPort.PLinkSpeed = SK_LSPEED_1000MBPS; + } + } else if (strcmp(ConType[pAC->Index],"100FD")==0) { + for (Port = 0; Port < SK_MAX_MACS; Port++) { + M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL]; + M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE; + M_CurrPort.PMSMode = SK_MS_MODE_AUTO; + M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS; + } + } else if (strcmp(ConType[pAC->Index],"100HD")==0) { + for (Port = 0; Port < SK_MAX_MACS; Port++) { + M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF]; + M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE; + M_CurrPort.PMSMode = SK_MS_MODE_AUTO; + M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS; + } + } else if (strcmp(ConType[pAC->Index],"10FD")==0) { + for (Port = 0; Port < SK_MAX_MACS; Port++) { + M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL]; + M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE; + M_CurrPort.PMSMode = SK_MS_MODE_AUTO; + M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS; + } + } else if (strcmp(ConType[pAC->Index],"10HD")==0) { + for (Port = 0; Port < SK_MAX_MACS; Port++) { + M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF]; + M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE; + M_CurrPort.PMSMode = SK_MS_MODE_AUTO; + M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS; + } + } else { + printk("sk98lin: Illegal value \"%s\" for ConType\n", + ConType[pAC->Index]); + IsConTypeDefined = SK_FALSE; /* Wrong ConType defined */ + } + } else { + IsConTypeDefined = SK_FALSE; /* No ConType defined */ + } + + /* + ** Parse any parameter settings for port A: + ** a) any LinkSpeed stated? + */ if (Speed_A != NULL && pAC->IndexIndex] != NULL) { if (strcmp(Speed_A[pAC->Index],"")==0) { - LinkSpeed = SK_LSPEED_AUTO; + IsLinkSpeedDefined = SK_FALSE; + } else if (strcmp(Speed_A[pAC->Index],"Auto")==0) { + LinkSpeed = SK_LSPEED_AUTO; + } else if (strcmp(Speed_A[pAC->Index],"10")==0) { + LinkSpeed = SK_LSPEED_10MBPS; + } else if (strcmp(Speed_A[pAC->Index],"100")==0) { + LinkSpeed = SK_LSPEED_100MBPS; + } else if (strcmp(Speed_A[pAC->Index],"1000")==0) { +#if 0 /* uboot */ + if ((pAC->PciDev->vendor == 0x11ab ) && + (pAC->PciDev->device == 0x4350)) { + LinkSpeed = SK_LSPEED_100MBPS; + printk("sk98lin: Illegal value \"%s\" for Speed_A.\n" + "Gigabit speed not possible with this chip revision!", + Speed_A[pAC->Index]); + } else +#endif + { + LinkSpeed = SK_LSPEED_1000MBPS; + } + } else { + printk("sk98lin: Illegal value \"%s\" for Speed_A\n", + Speed_A[pAC->Index]); + IsLinkSpeedDefined = SK_FALSE; } - else if (strcmp(Speed_A[pAC->Index],"Auto")==0) { - LinkSpeed = SK_LSPEED_AUTO; - } - else if (strcmp(Speed_A[pAC->Index],"10")==0) { - LinkSpeed = SK_LSPEED_10MBPS; - } - else if (strcmp(Speed_A[pAC->Index],"100")==0) { + } else { +#if 0 /* uboot */ + if ((pAC->PciDev->vendor == 0x11ab ) && + (pAC->PciDev->device == 0x4350)) { + /* Gigabit speed not supported + * Swith to speed 100 + */ LinkSpeed = SK_LSPEED_100MBPS; + } else +#endif + { + IsLinkSpeedDefined = SK_FALSE; } - else if (strcmp(Speed_A[pAC->Index],"1000")==0) { - LinkSpeed = SK_LSPEED_1000MBPS; - } - else printk("%s: Illegal value for Speed_A\n", - pAC->dev[0]->name); } - /* Check speed parameter */ - /* Only copper type adapter and GE V2 cards */ - if (((pAC->GIni.GIChipId != CHIP_ID_YUKON) || - (pAC->GIni.GICopperType != SK_TRUE)) && + /* + ** Check speed parameter: + ** Only copper type adapter and GE V2 cards + */ + if (((!pAC->ChipsetType) || (pAC->GIni.GICopperType != SK_TRUE)) && ((LinkSpeed != SK_LSPEED_AUTO) && (LinkSpeed != SK_LSPEED_1000MBPS))) { - printk("%s: Illegal value for Speed_A. " + printk("sk98lin: Illegal value for Speed_A. " "Not a copper card or GE V2 card\n Using " - "speed 1000\n", pAC->dev[0]->name); + "speed 1000\n"); LinkSpeed = SK_LSPEED_1000MBPS; } - pAC->GIni.GP[0].PLinkSpeed = LinkSpeed; + + /* + ** Decide whether to set new config value if somethig valid has + ** been received. + */ + if (IsLinkSpeedDefined) { + pAC->GIni.GP[0].PLinkSpeed = LinkSpeed; + } - /* Autonegotiation */ + /* + ** b) Any Autonegotiation and DuplexCapabilities set? + ** Please note that both belong together... + */ AutoNeg = AN_ON; /* tschilling: Default: Autonegotiation on! */ AutoSet = SK_FALSE; if (AutoNeg_A != NULL && pAC->IndexIndex] != NULL) { AutoSet = SK_TRUE; if (strcmp(AutoNeg_A[pAC->Index],"")==0) { - AutoSet = SK_FALSE; + AutoSet = SK_FALSE; + } else if (strcmp(AutoNeg_A[pAC->Index],"On")==0) { + AutoNeg = AN_ON; + } else if (strcmp(AutoNeg_A[pAC->Index],"Off")==0) { + AutoNeg = AN_OFF; + } else if (strcmp(AutoNeg_A[pAC->Index],"Sense")==0) { + AutoNeg = AN_SENS; + } else { + printk("sk98lin: Illegal value \"%s\" for AutoNeg_A\n", + AutoNeg_A[pAC->Index]); } - else if (strcmp(AutoNeg_A[pAC->Index],"On")==0) { - AutoNeg = AN_ON; - } - else if (strcmp(AutoNeg_A[pAC->Index],"Off")==0) { - AutoNeg = AN_OFF; - } - else if (strcmp(AutoNeg_A[pAC->Index],"Sense")==0) { - AutoNeg = AN_SENS; - } - else printk("%s: Illegal value for AutoNeg_A\n", - pAC->dev[0]->name); } DuplexCap = DC_BOTH; - DupSet = SK_FALSE; + DupSet = SK_FALSE; if (DupCap_A != NULL && pAC->IndexIndex] != NULL) { DupSet = SK_TRUE; if (strcmp(DupCap_A[pAC->Index],"")==0) { - DupSet = SK_FALSE; + DupSet = SK_FALSE; + } else if (strcmp(DupCap_A[pAC->Index],"Both")==0) { + DuplexCap = DC_BOTH; + } else if (strcmp(DupCap_A[pAC->Index],"Full")==0) { + DuplexCap = DC_FULL; + } else if (strcmp(DupCap_A[pAC->Index],"Half")==0) { + DuplexCap = DC_HALF; + } else { + printk("sk98lin: Illegal value \"%s\" for DupCap_A\n", + DupCap_A[pAC->Index]); } - else if (strcmp(DupCap_A[pAC->Index],"Both")==0) { - DuplexCap = DC_BOTH; - } - else if (strcmp(DupCap_A[pAC->Index],"Full")==0) { - DuplexCap = DC_FULL; - } - else if (strcmp(DupCap_A[pAC->Index],"Half")==0) { - DuplexCap = DC_HALF; - } - else printk("%s: Illegal value for DupCap_A\n", - pAC->dev[0]->name); } - /* check for illegal combinations */ - if (AutoSet && AutoNeg==AN_SENS && DupSet) { - printk("%s, Port A: DuplexCapabilities" - " ignored using Sense mode\n", pAC->dev[0]->name); + /* + ** Check for illegal combinations + */ + if ((LinkSpeed == SK_LSPEED_1000MBPS) && + ((DuplexCap == SK_LMODE_STAT_AUTOHALF) || + (DuplexCap == SK_LMODE_STAT_HALF)) && + (pAC->ChipsetType)) { + printk("sk98lin: Half Duplex not possible with Gigabit speed!\n" + " Using Full Duplex.\n"); + DuplexCap = DC_FULL; } + + if ( AutoSet && AutoNeg==AN_SENS && DupSet) { + printk("sk98lin, Port A: DuplexCapabilities" + " ignored using Sense mode\n"); + } + if (AutoSet && AutoNeg==AN_OFF && DupSet && DuplexCap==DC_BOTH){ - printk("%s, Port A: Illegal combination" + printk("sk98lin: Port A: Illegal combination" " of values AutoNeg. and DuplexCap.\n Using " - "Full Duplex\n", pAC->dev[0]->name); - + "Full Duplex\n"); DuplexCap = DC_FULL; } + if (AutoSet && AutoNeg==AN_OFF && !DupSet) { DuplexCap = DC_FULL; } - + if (!AutoSet && DupSet) { - printk("%s, Port A: Duplex setting not" - " possible in\n default AutoNegotiation mode" - " (Sense).\n Using AutoNegotiation On\n", - pAC->dev[0]->name); AutoNeg = AN_ON; } - - /* set the desired mode */ - pAC->GIni.GP[0].PLinkModeConf = - Capabilities[AutoNeg][DuplexCap]; - - pAC->GIni.GP[0].PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + + /* + ** set the desired mode + */ + if (AutoSet || DupSet) { + pAC->GIni.GP[0].PLinkModeConf = Capabilities[AutoNeg][DuplexCap]; + } + + /* + ** c) Any Flowcontrol-parameter set? + */ if (FlowCtrl_A != NULL && pAC->IndexIndex] != NULL) { if (strcmp(FlowCtrl_A[pAC->Index],"") == 0) { + IsFlowCtrlDefined = SK_FALSE; + } else if (strcmp(FlowCtrl_A[pAC->Index],"SymOrRem") == 0) { + FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; + } else if (strcmp(FlowCtrl_A[pAC->Index],"Sym")==0) { + FlowCtrl = SK_FLOW_MODE_SYMMETRIC; + } else if (strcmp(FlowCtrl_A[pAC->Index],"LocSend")==0) { + FlowCtrl = SK_FLOW_MODE_LOC_SEND; + } else if (strcmp(FlowCtrl_A[pAC->Index],"None")==0) { + FlowCtrl = SK_FLOW_MODE_NONE; + } else { + printk("sk98lin: Illegal value \"%s\" for FlowCtrl_A\n", + FlowCtrl_A[pAC->Index]); + IsFlowCtrlDefined = SK_FALSE; } - else if (strcmp(FlowCtrl_A[pAC->Index],"SymOrRem") == 0) { - pAC->GIni.GP[0].PFlowCtrlMode = - SK_FLOW_MODE_SYM_OR_REM; - } - else if (strcmp(FlowCtrl_A[pAC->Index],"Sym")==0) { - pAC->GIni.GP[0].PFlowCtrlMode = - SK_FLOW_MODE_SYMMETRIC; - } - else if (strcmp(FlowCtrl_A[pAC->Index],"LocSend")==0) { - pAC->GIni.GP[0].PFlowCtrlMode = - SK_FLOW_MODE_LOC_SEND; - } - else if (strcmp(FlowCtrl_A[pAC->Index],"None")==0) { - pAC->GIni.GP[0].PFlowCtrlMode = - SK_FLOW_MODE_NONE; - } - else printk("Illegal value for FlowCtrl_A\n"); - } - if (AutoNeg==AN_OFF && pAC->GIni.GP[0].PFlowCtrlMode!= - SK_FLOW_MODE_NONE) { - printk("%s, Port A: FlowControl" - " impossible without AutoNegotiation," - " disabled\n", pAC->dev[0]->name); - pAC->GIni.GP[0].PFlowCtrlMode = SK_FLOW_MODE_NONE; + } else { + IsFlowCtrlDefined = SK_FALSE; } - MSMode = SK_MS_MODE_AUTO; /* default: do auto select */ + if (IsFlowCtrlDefined) { + if ((AutoNeg == AN_OFF) && (FlowCtrl != SK_FLOW_MODE_NONE)) { + printk("sk98lin: Port A: FlowControl" + " impossible without AutoNegotiation," + " disabled\n"); + FlowCtrl = SK_FLOW_MODE_NONE; + } + pAC->GIni.GP[0].PFlowCtrlMode = FlowCtrl; + } + + /* + ** d) What is with the RoleParameter? + */ if (Role_A != NULL && pAC->IndexIndex] != NULL) { if (strcmp(Role_A[pAC->Index],"")==0) { + IsRoleDefined = SK_FALSE; + } else if (strcmp(Role_A[pAC->Index],"Auto")==0) { + MSMode = SK_MS_MODE_AUTO; + } else if (strcmp(Role_A[pAC->Index],"Master")==0) { + MSMode = SK_MS_MODE_MASTER; + } else if (strcmp(Role_A[pAC->Index],"Slave")==0) { + MSMode = SK_MS_MODE_SLAVE; + } else { + printk("sk98lin: Illegal value \"%s\" for Role_A\n", + Role_A[pAC->Index]); + IsRoleDefined = SK_FALSE; } - else if (strcmp(Role_A[pAC->Index],"Auto")==0) { - MSMode = SK_MS_MODE_AUTO; - } - else if (strcmp(Role_A[pAC->Index],"Master")==0) { - MSMode = SK_MS_MODE_MASTER; - } - else if (strcmp(Role_A[pAC->Index],"Slave")==0) { - MSMode = SK_MS_MODE_SLAVE; - } - else printk("%s: Illegal value for Role_A\n", - pAC->dev[0]->name); + } else { + IsRoleDefined = SK_FALSE; } - pAC->GIni.GP[0].PMSMode = MSMode; + if (IsRoleDefined == SK_TRUE) { + pAC->GIni.GP[0].PMSMode = MSMode; + } + + + + /* + ** Parse any parameter settings for port B: + ** a) any LinkSpeed stated? + */ + IsConTypeDefined = SK_TRUE; + IsLinkSpeedDefined = SK_TRUE; + IsFlowCtrlDefined = SK_TRUE; + IsModeDefined = SK_TRUE; - /* settings for port B */ - /* settings link speed */ - LinkSpeed = SK_LSPEED_AUTO; /* default: do auto select */ if (Speed_B != NULL && pAC->IndexIndex] != NULL) { if (strcmp(Speed_B[pAC->Index],"")==0) { - LinkSpeed = SK_LSPEED_AUTO; + IsLinkSpeedDefined = SK_FALSE; + } else if (strcmp(Speed_B[pAC->Index],"Auto")==0) { + LinkSpeed = SK_LSPEED_AUTO; + } else if (strcmp(Speed_B[pAC->Index],"10")==0) { + LinkSpeed = SK_LSPEED_10MBPS; + } else if (strcmp(Speed_B[pAC->Index],"100")==0) { + LinkSpeed = SK_LSPEED_100MBPS; + } else if (strcmp(Speed_B[pAC->Index],"1000")==0) { + LinkSpeed = SK_LSPEED_1000MBPS; + } else { + printk("sk98lin: Illegal value \"%s\" for Speed_B\n", + Speed_B[pAC->Index]); + IsLinkSpeedDefined = SK_FALSE; } - else if (strcmp(Speed_B[pAC->Index],"Auto")==0) { - LinkSpeed = SK_LSPEED_AUTO; - } - else if (strcmp(Speed_B[pAC->Index],"10")==0) { - LinkSpeed = SK_LSPEED_10MBPS; - } - else if (strcmp(Speed_B[pAC->Index],"100")==0) { - LinkSpeed = SK_LSPEED_100MBPS; - } - else if (strcmp(Speed_B[pAC->Index],"1000")==0) { - LinkSpeed = SK_LSPEED_1000MBPS; - } - else printk("%s: Illegal value for Speed_B\n", - pAC->dev[1]->name); + } else { + IsLinkSpeedDefined = SK_FALSE; } - /* Check speed parameter */ - /* Only copper type adapter and GE V2 cards */ - if (((pAC->GIni.GIChipId != CHIP_ID_YUKON) || - (pAC->GIni.GICopperType != SK_TRUE)) && + /* + ** Check speed parameter: + ** Only copper type adapter and GE V2 cards + */ + if (((!pAC->ChipsetType) || (pAC->GIni.GICopperType != SK_TRUE)) && ((LinkSpeed != SK_LSPEED_AUTO) && (LinkSpeed != SK_LSPEED_1000MBPS))) { - printk("%s: Illegal value for Speed_B. " + printk("sk98lin: Illegal value for Speed_B. " "Not a copper card or GE V2 card\n Using " - "speed 1000\n", pAC->dev[1]->name); + "speed 1000\n"); LinkSpeed = SK_LSPEED_1000MBPS; } - pAC->GIni.GP[1].PLinkSpeed = LinkSpeed; - /* Auto negotiation */ + /* + ** Decide whether to set new config value if somethig valid has + ** been received. + */ + if (IsLinkSpeedDefined) { + pAC->GIni.GP[1].PLinkSpeed = LinkSpeed; + } + + /* + ** b) Any Autonegotiation and DuplexCapabilities set? + ** Please note that both belong together... + */ AutoNeg = AN_SENS; /* default: do auto Sense */ AutoSet = SK_FALSE; if (AutoNeg_B != NULL && pAC->IndexIndex] != NULL) { AutoSet = SK_TRUE; if (strcmp(AutoNeg_B[pAC->Index],"")==0) { - AutoSet = SK_FALSE; + AutoSet = SK_FALSE; + } else if (strcmp(AutoNeg_B[pAC->Index],"On")==0) { + AutoNeg = AN_ON; + } else if (strcmp(AutoNeg_B[pAC->Index],"Off")==0) { + AutoNeg = AN_OFF; + } else if (strcmp(AutoNeg_B[pAC->Index],"Sense")==0) { + AutoNeg = AN_SENS; + } else { + printk("sk98lin: Illegal value \"%s\" for AutoNeg_B\n", + AutoNeg_B[pAC->Index]); } - else if (strcmp(AutoNeg_B[pAC->Index],"On")==0) { - AutoNeg = AN_ON; - } - else if (strcmp(AutoNeg_B[pAC->Index],"Off")==0) { - AutoNeg = AN_OFF; - } - else if (strcmp(AutoNeg_B[pAC->Index],"Sense")==0) { - AutoNeg = AN_SENS; - } - else printk("Illegal value for AutoNeg_B\n"); } DuplexCap = DC_BOTH; - DupSet = SK_FALSE; + DupSet = SK_FALSE; if (DupCap_B != NULL && pAC->IndexIndex] != NULL) { DupSet = SK_TRUE; if (strcmp(DupCap_B[pAC->Index],"")==0) { - DupSet = SK_FALSE; + DupSet = SK_FALSE; + } else if (strcmp(DupCap_B[pAC->Index],"Both")==0) { + DuplexCap = DC_BOTH; + } else if (strcmp(DupCap_B[pAC->Index],"Full")==0) { + DuplexCap = DC_FULL; + } else if (strcmp(DupCap_B[pAC->Index],"Half")==0) { + DuplexCap = DC_HALF; + } else { + printk("sk98lin: Illegal value \"%s\" for DupCap_B\n", + DupCap_B[pAC->Index]); } - else if (strcmp(DupCap_B[pAC->Index],"Both")==0) { - DuplexCap = DC_BOTH; - } - else if (strcmp(DupCap_B[pAC->Index],"Full")==0) { - DuplexCap = DC_FULL; - } - else if (strcmp(DupCap_B[pAC->Index],"Half")==0) { - DuplexCap = DC_HALF; - } - else printk("Illegal value for DupCap_B\n"); } - /* check for illegal combinations */ + + /* + ** Check for illegal combinations + */ + if ((LinkSpeed == SK_LSPEED_1000MBPS) && + ((DuplexCap == SK_LMODE_STAT_AUTOHALF) || + (DuplexCap == SK_LMODE_STAT_HALF)) && + (pAC->ChipsetType)) { + printk("sk98lin: Half Duplex not possible with Gigabit speed!\n" + " Using Full Duplex.\n"); + DuplexCap = DC_FULL; + } + if (AutoSet && AutoNeg==AN_SENS && DupSet) { - printk("%s, Port B: DuplexCapabilities" - " ignored using Sense mode\n", pAC->dev[1]->name); + printk("sk98lin, Port B: DuplexCapabilities" + " ignored using Sense mode\n"); } - if (AutoSet && AutoNeg==AN_OFF && DupSet && DuplexCap==DC_BOTH){ - printk("%s, Port B: Illegal combination" - " of values AutoNeg. and DuplexCap.\n Using " - "Full Duplex\n", pAC->dev[1]->name); + if (AutoSet && AutoNeg==AN_OFF && DupSet && DuplexCap==DC_BOTH){ + printk("sk98lin: Port B: Illegal combination" + " of values AutoNeg. and DuplexCap.\n Using " + "Full Duplex\n"); DuplexCap = DC_FULL; } + if (AutoSet && AutoNeg==AN_OFF && !DupSet) { DuplexCap = DC_FULL; } - + if (!AutoSet && DupSet) { - printk("%s, Port B: Duplex setting not" - " possible in\n default AutoNegotiation mode" - " (Sense).\n Using AutoNegotiation On\n", - pAC->dev[1]->name); AutoNeg = AN_ON; } - /* set the desired mode */ - pAC->GIni.GP[1].PLinkModeConf = - Capabilities[AutoNeg][DuplexCap]; + /* + ** set the desired mode + */ + if (AutoSet || DupSet) { + pAC->GIni.GP[1].PLinkModeConf = Capabilities[AutoNeg][DuplexCap]; + } - pAC->GIni.GP[1].PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + /* + ** c) Any FlowCtrl parameter set? + */ if (FlowCtrl_B != NULL && pAC->IndexIndex] != NULL) { if (strcmp(FlowCtrl_B[pAC->Index],"") == 0) { + IsFlowCtrlDefined = SK_FALSE; + } else if (strcmp(FlowCtrl_B[pAC->Index],"SymOrRem") == 0) { + FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; + } else if (strcmp(FlowCtrl_B[pAC->Index],"Sym")==0) { + FlowCtrl = SK_FLOW_MODE_SYMMETRIC; + } else if (strcmp(FlowCtrl_B[pAC->Index],"LocSend")==0) { + FlowCtrl = SK_FLOW_MODE_LOC_SEND; + } else if (strcmp(FlowCtrl_B[pAC->Index],"None")==0) { + FlowCtrl = SK_FLOW_MODE_NONE; + } else { + printk("sk98lin: Illegal value \"%s\" for FlowCtrl_B\n", + FlowCtrl_B[pAC->Index]); + IsFlowCtrlDefined = SK_FALSE; } - else if (strcmp(FlowCtrl_B[pAC->Index],"SymOrRem") == 0) { - pAC->GIni.GP[1].PFlowCtrlMode = - SK_FLOW_MODE_SYM_OR_REM; - } - else if (strcmp(FlowCtrl_B[pAC->Index],"Sym")==0) { - pAC->GIni.GP[1].PFlowCtrlMode = - SK_FLOW_MODE_SYMMETRIC; - } - else if (strcmp(FlowCtrl_B[pAC->Index],"LocSend")==0) { - pAC->GIni.GP[1].PFlowCtrlMode = - SK_FLOW_MODE_LOC_SEND; - } - else if (strcmp(FlowCtrl_B[pAC->Index],"None")==0) { - pAC->GIni.GP[1].PFlowCtrlMode = - SK_FLOW_MODE_NONE; - } - else printk("Illegal value for FlowCtrl_B\n"); - } - if (AutoNeg==AN_OFF && pAC->GIni.GP[1].PFlowCtrlMode!= - SK_FLOW_MODE_NONE) { - printk("%s, Port B: FlowControl" - " impossible without AutoNegotiation," - " disabled\n", pAC->dev[1]->name); - pAC->GIni.GP[1].PFlowCtrlMode = SK_FLOW_MODE_NONE; + } else { + IsFlowCtrlDefined = SK_FALSE; } - MSMode = SK_MS_MODE_AUTO; /* default: do auto select */ + if (IsFlowCtrlDefined) { + if ((AutoNeg == AN_OFF) && (FlowCtrl != SK_FLOW_MODE_NONE)) { + printk("sk98lin: Port B: FlowControl" + " impossible without AutoNegotiation," + " disabled\n"); + FlowCtrl = SK_FLOW_MODE_NONE; + } + pAC->GIni.GP[1].PFlowCtrlMode = FlowCtrl; + } + + /* + ** d) What is the RoleParameter? + */ if (Role_B != NULL && pAC->IndexIndex] != NULL) { if (strcmp(Role_B[pAC->Index],"")==0) { + IsRoleDefined = SK_FALSE; + } else if (strcmp(Role_B[pAC->Index],"Auto")==0) { + MSMode = SK_MS_MODE_AUTO; + } else if (strcmp(Role_B[pAC->Index],"Master")==0) { + MSMode = SK_MS_MODE_MASTER; + } else if (strcmp(Role_B[pAC->Index],"Slave")==0) { + MSMode = SK_MS_MODE_SLAVE; + } else { + printk("sk98lin: Illegal value \"%s\" for Role_B\n", + Role_B[pAC->Index]); + IsRoleDefined = SK_FALSE; } - else if (strcmp(Role_B[pAC->Index],"Auto")==0) { - MSMode = SK_MS_MODE_AUTO; - } - else if (strcmp(Role_B[pAC->Index],"Master")==0) { - MSMode = SK_MS_MODE_MASTER; - } - else if (strcmp(Role_B[pAC->Index],"Slave")==0) { - MSMode = SK_MS_MODE_SLAVE; - } - else printk("%s: Illegal value for Role_B\n", - pAC->dev[1]->name); + } else { + IsRoleDefined = SK_FALSE; } - pAC->GIni.GP[1].PMSMode = MSMode; - - /* settings for both ports */ + if (IsRoleDefined) { + pAC->GIni.GP[1].PMSMode = MSMode; + } + + /* + ** Evaluate settings for both ports + */ pAC->ActivePort = 0; if (PrefPort != NULL && pAC->IndexIndex] != NULL) { if (strcmp(PrefPort[pAC->Index],"") == 0) { /* Auto */ - pAC->ActivePort = 0; + pAC->ActivePort = 0; pAC->Rlmt.Net[0].Preference = -1; /* auto */ - pAC->Rlmt.Net[0].PrefPort = 0; - } - else if (strcmp(PrefPort[pAC->Index],"A") == 0) { + pAC->Rlmt.Net[0].PrefPort = 0; + } else if (strcmp(PrefPort[pAC->Index],"A") == 0) { /* - * do not set ActivePort here, thus a port - * switch is issued after net up. - */ - Port = 0; + ** do not set ActivePort here, thus a port + ** switch is issued after net up. + */ + Port = 0; pAC->Rlmt.Net[0].Preference = Port; - pAC->Rlmt.Net[0].PrefPort = Port; - } - else if (strcmp(PrefPort[pAC->Index],"B") == 0) { + pAC->Rlmt.Net[0].PrefPort = Port; + } else if (strcmp(PrefPort[pAC->Index],"B") == 0) { /* - * do not set ActivePort here, thus a port - * switch is issued after net up. - */ - Port = 1; - pAC->Rlmt.Net[0].Preference = Port; - pAC->Rlmt.Net[0].PrefPort = Port; + ** do not set ActivePort here, thus a port + ** switch is issued after net up. + */ + if (pAC->GIni.GIMacsFound == 1) { + printk("sk98lin: Illegal value \"B\" for PrefPort.\n" + " Port B not available on single port adapters.\n"); + + pAC->ActivePort = 0; + pAC->Rlmt.Net[0].Preference = -1; /* auto */ + pAC->Rlmt.Net[0].PrefPort = 0; + } else { + Port = 1; + pAC->Rlmt.Net[0].Preference = Port; + pAC->Rlmt.Net[0].PrefPort = Port; + } + } else { + printk("sk98lin: Illegal value \"%s\" for PrefPort\n", + PrefPort[pAC->Index]); } - else printk("%s: Illegal value for PrefPort\n", - pAC->dev[0]->name); } pAC->RlmtNets = 1; + pAC->RlmtMode = 0; if (RlmtMode != NULL && pAC->IndexIndex] != NULL) { if (strcmp(RlmtMode[pAC->Index], "") == 0) { - pAC->RlmtMode = 0; - } - else if (strcmp(RlmtMode[pAC->Index], "CheckLinkState") == 0) { - pAC->RlmtMode = SK_RLMT_CHECK_LINK; - } - else if (strcmp(RlmtMode[pAC->Index], "CheckLocalPort") == 0) { - pAC->RlmtMode = SK_RLMT_CHECK_LINK | - SK_RLMT_CHECK_LOC_LINK; - } - else if (strcmp(RlmtMode[pAC->Index], "CheckSeg") == 0) { - pAC->RlmtMode = SK_RLMT_CHECK_LINK | - SK_RLMT_CHECK_LOC_LINK | - SK_RLMT_CHECK_SEG; - } - else if ((strcmp(RlmtMode[pAC->Index], "DualNet") == 0) && - (pAC->GIni.GIMacsFound == 2)) { + if (pAC->GIni.GIMacsFound == 2) { pAC->RlmtMode = SK_RLMT_CHECK_LINK; pAC->RlmtNets = 2; - } - else { - printk("%s: Illegal value for" - " RlmtMode, using default\n", pAC->dev[0]->name); + } + } else if (strcmp(RlmtMode[pAC->Index], "CheckLinkState") == 0) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK; + } else if (strcmp(RlmtMode[pAC->Index], "CheckLocalPort") == 0) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK | + SK_RLMT_CHECK_LOC_LINK; + } else if (strcmp(RlmtMode[pAC->Index], "CheckSeg") == 0) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK | + SK_RLMT_CHECK_LOC_LINK | + SK_RLMT_CHECK_SEG; + } else if ((strcmp(RlmtMode[pAC->Index], "DualNet") == 0) && + (pAC->GIni.GIMacsFound == 2)) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK; + pAC->RlmtNets = 2; + } else { + printk("sk98lin: Illegal value \"%s\" for" + " RlmtMode, using default\n", + RlmtMode[pAC->Index]); pAC->RlmtMode = 0; } + } else { + if (pAC->GIni.GIMacsFound == 2) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK; + pAC->RlmtNets = 2; + } } - else { - pAC->RlmtMode = 0; + +#ifdef SK_YUKON2 + /* + ** use dualnet config per default + * + pAC->RlmtMode = SK_RLMT_CHECK_LINK; + pAC->RlmtNets = 2; + */ +#endif + + + /* + ** Check the LowLatance parameters + */ + pAC->LowLatency = SK_FALSE; + if (LowLatency[pAC->Index] != NULL) { + if (strcmp(LowLatency[pAC->Index], "On") == 0) { + pAC->LowLatency = SK_TRUE; + } } + + + /* + ** Check the interrupt moderation parameters + */ + pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE; + if (Moderation[pAC->Index] != NULL) { + if (strcmp(Moderation[pAC->Index], "") == 0) { + pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE; + } else if (strcmp(Moderation[pAC->Index], "Static") == 0) { + pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_STATIC; + } else if (strcmp(Moderation[pAC->Index], "Dynamic") == 0) { + pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_DYNAMIC; + } else if (strcmp(Moderation[pAC->Index], "None") == 0) { + pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE; + } else { + printk("sk98lin: Illegal value \"%s\" for Moderation.\n" + " Disable interrupt moderation.\n", + Moderation[pAC->Index]); + } + } else { +/* Set interrupt moderation if wished */ +#ifdef CONFIG_SK98LIN_STATINT + pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_STATIC; +#endif + } + + if (ModerationMask[pAC->Index] != NULL) { + if (strcmp(ModerationMask[pAC->Index], "Rx") == 0) { + IrqModMaskOffset = 0; + } else if (strcmp(ModerationMask[pAC->Index], "Tx") == 0) { + IrqModMaskOffset = 1; + } else if (strcmp(ModerationMask[pAC->Index], "Sp") == 0) { + IrqModMaskOffset = 2; + } else if (strcmp(ModerationMask[pAC->Index], "RxSp") == 0) { + IrqModMaskOffset = 3; + } else if (strcmp(ModerationMask[pAC->Index], "SpRx") == 0) { + IrqModMaskOffset = 3; + } else if (strcmp(ModerationMask[pAC->Index], "RxTx") == 0) { + IrqModMaskOffset = 4; + } else if (strcmp(ModerationMask[pAC->Index], "TxRx") == 0) { + IrqModMaskOffset = 4; + } else if (strcmp(ModerationMask[pAC->Index], "TxSp") == 0) { + IrqModMaskOffset = 5; + } else if (strcmp(ModerationMask[pAC->Index], "SpTx") == 0) { + IrqModMaskOffset = 5; + } else { /* some rubbish stated */ + // IrqModMaskOffset = 6; ->has been initialized + // already at the begin of this function... + } + } + if (!CHIP_ID_YUKON_2(pAC)) { + pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][0]; + } else { + pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][1]; + } + + if (!CHIP_ID_YUKON_2(pAC)) { + pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT; + } else { + pAC->DynIrqModInfo.MaxModIntsPerSec = C_Y2_INTS_PER_SEC_DEFAULT; + } + if (IntsPerSec[pAC->Index] != 0) { + if ((IntsPerSec[pAC->Index]< C_INT_MOD_IPS_LOWER_RANGE) || + (IntsPerSec[pAC->Index] > C_INT_MOD_IPS_UPPER_RANGE)) { + printk("sk98lin: Illegal value \"%d\" for IntsPerSec. (Range: %d - %d)\n" + " Using default value of %i.\n", + IntsPerSec[pAC->Index], + C_INT_MOD_IPS_LOWER_RANGE, + C_INT_MOD_IPS_UPPER_RANGE, + pAC->DynIrqModInfo.MaxModIntsPerSec); + } else { + pAC->DynIrqModInfo.MaxModIntsPerSec = IntsPerSec[pAC->Index]; + } + } + + /* + ** Evaluate upper and lower moderation threshold + */ + pAC->DynIrqModInfo.MaxModIntsPerSecUpperLimit = + pAC->DynIrqModInfo.MaxModIntsPerSec + + (pAC->DynIrqModInfo.MaxModIntsPerSec / 5); + + pAC->DynIrqModInfo.MaxModIntsPerSecLowerLimit = + pAC->DynIrqModInfo.MaxModIntsPerSec - + (pAC->DynIrqModInfo.MaxModIntsPerSec / 5); + + pAC->DynIrqModInfo.DynIrqModSampleInterval = + SK_DRV_MODERATION_TIMER_LENGTH; + } /* GetConfiguration */ - +#if 0 /* uboot */ /***************************************************************************** * * ProductStr - return a adapter identification string from vpd @@ -4108,28 +5335,23 @@ int Capabilities[3][3] = * * Returns: N/A */ -static void ProductStr( -SK_AC *pAC /* pointer to adapter context */ -) +static void ProductStr(SK_AC *pAC) { -int StrLen = 80; /* length of the string, defined in SK_AC */ -char Keyword[] = VPD_NAME; /* vpd productname identifier */ -int ReturnCode; /* return code from vpd_read */ -unsigned long Flags; + char Default[] = "Generic Marvell Yukon chipset Ethernet device"; + char Key[] = VPD_NAME; /* VPD productname key */ + int StrLen = 80; /* stringlen */ + unsigned long Flags; spin_lock_irqsave(&pAC->SlowPathLock, Flags); - ReturnCode = VpdRead(pAC, pAC->IoBase, Keyword, pAC->DeviceStr, - &StrLen); - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - if (ReturnCode != 0) { - /* there was an error reading the vpd data */ + if (VpdRead(pAC, pAC->IoBase, Key, pAC->DeviceStr, &StrLen)) { SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR, ("Error reading VPD data: %d\n", ReturnCode)); - pAC->DeviceStr[0] = '\0'; + strcpy(pAC->DeviceStr, Default); } + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); } /* ProductStr */ - +#endif /****************************************************************************/ /* functions for common modules *********************************************/ /****************************************************************************/ @@ -4217,10 +5439,14 @@ SK_MBUF *pNextMbuf; */ SK_U64 SkOsGetTime(SK_AC *pAC) { -#if 0 - return jiffies; +#if 0 /* uboot */ + SK_U64 PrivateJiffies; + + SkOsGetTimeCurrent(pAC, &PrivateJiffies); + + return PrivateJiffies; #else - return get_timer(0); + return (get_timer(0)/(CFG_TCLK/1000)); #endif } /* SkOsGetTime */ @@ -4372,34 +5598,30 @@ SK_U8 Val) /* pointer to store the read value */ * Returns: * 0 if everything ok * < 0 on error - * + * */ int SkDrvEvent( -SK_AC *pAC, /* pointer to adapter context */ -SK_IOC IoC, /* io-context */ -SK_U32 Event, /* event-id */ -SK_EVPARA Param) /* event-parameter */ +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* IO control context */ +SK_U32 Event, /* event-id */ +SK_EVPARA Param) /* event-parameter */ { -SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */ -struct sk_buff *pMsg; /* pointer to a message block */ -int FromPort; /* the port from which we switch away */ -int ToPort; /* the port we switch to */ -SK_EVPARA NewPara; /* parameter for further events */ -#if 0 -int Stat; + SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */ + struct sk_buff *pMsg; /* pointer to a message block */ + SK_BOOL DualNet; + SK_U32 Reason; + unsigned long Flags; + unsigned long InitFlags; + int FromPort; /* the port from which we switch away */ + int ToPort; /* the port we switch to */ + int Stat; + DEV_NET *pNet = NULL; +#ifdef CONFIG_SK98LIN_NAPI + int WorkToDo = 1; /* min(*budget, dev->quota); */ + int WorkDone = 0; #endif -unsigned long Flags; -SK_BOOL DualNet; switch (Event) { - case SK_DRV_ADAP_FAIL: - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, - ("ADAPTER FAIL EVENT\n")); - printk("%s: Adapter failed.\n", pAC->dev[0]->name); - /* disable interrupts */ - SK_OUT32(pAC->IoBase, B0_IMSK, 0); - /* cgoos */ - break; case SK_DRV_PORT_FAIL: FromPort = Param.Para32[0]; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, @@ -4409,193 +5631,308 @@ SK_BOOL DualNet; } else { printk("%s: Port B failed.\n", pAC->dev[1]->name); } - /* cgoos */ break; - case SK_DRV_PORT_RESET: /* SK_U32 PortIdx */ - /* action list 4 */ + case SK_DRV_PORT_RESET: FromPort = Param.Para32[0]; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, ("PORT RESET EVENT, Port: %d ", FromPort)); - NewPara.Para64 = FromPort; - SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara); + SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET, + FromPort, SK_FALSE); spin_lock_irqsave( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); - SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST); -#if 0 + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST); + } else { + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST); + } +#if 0 /* uboot */ pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING; #endif spin_unlock_irqrestore( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); - - /* clear rx ring from received frames */ - ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); - - ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); + + if (!CHIP_ID_YUKON_2(pAC)) { +#ifdef CONFIG_SK98LIN_NAPI + WorkToDo = 1; + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo); +#else + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); +#endif + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); + } spin_lock_irqsave( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); - /* tschilling: Handling of return value inserted. */ - if (SkGeInitPort(pAC, IoC, FromPort)) { - if (FromPort == 0) { - printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name); - } else { - printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name); +#ifdef USE_TIST_FOR_RESET + if (pAC->GIni.GIYukon2) { +#ifdef Y2_RECOVERY + /* for Yukon II we want to have tist enabled all the time */ + if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) { + Y2_ENABLE_TIST(pAC->IoBase); } +#else + /* make sure that we do not accept any status LEs from now on */ + if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) { +#endif + /* port already waiting for tist */ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP, + ("Port %c is now waiting for specific Tist\n", + 'A' + FromPort)); + SK_SET_WAIT_BIT_FOR_PORT( + pAC, + SK_PSTATE_WAITING_FOR_SPECIFIC_TIST, + FromPort); + /* get current timestamp */ + Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo); + pAC->MinTistHi = pAC->GIni.GITimeStampCnt; +#ifndef Y2_RECOVERY + } else { + /* nobody is waiting yet */ + SK_SET_WAIT_BIT_FOR_PORT( + pAC, + SK_PSTATE_WAITING_FOR_ANY_TIST, + FromPort); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP, + ("Port %c is now waiting for any Tist (0x%X)\n", + 'A' + FromPort, pAC->AdapterResetState)); + /* start tist */ + Y2_ENABLE_TIST(pAC-IoBase); + } +#endif + } +#endif + +#ifdef Y2_LE_CHECK + /* mark entries invalid */ + pAC->LastPort = 3; + pAC->LastOpc = 0xFF; +#endif + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStart(pAC, IoC, FromPort); + } else { + /* tschilling: Handling of return value inserted. */ + if (SkGeInitPort(pAC, IoC, FromPort)) { + if (FromPort == 0) { + printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name); + } else { + printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name); + } + } + SkAddrMcUpdate(pAC,IoC, FromPort); + PortReInitBmu(pAC, FromPort); + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); + CLEAR_AND_START_RX(FromPort); } - SkAddrMcUpdate(pAC,IoC, FromPort); - PortReInitBmu(pAC, FromPort); - SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); - ClearAndStartRx(pAC, FromPort); spin_unlock_irqrestore( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); break; - case SK_DRV_NET_UP: /* SK_U32 PortIdx */ - /* action list 5 */ + case SK_DRV_NET_UP: + spin_lock_irqsave(&pAC->InitLock, InitFlags); FromPort = Param.Para32[0]; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, - ("NET UP EVENT, Port: %d ", Param.Para32[0])); -#ifdef SK98_INFO - printk("%s: network connection up using" - " port %c\n", pAC->dev[Param.Para32[0]]->name, 'A'+Param.Para32[0]); + ("NET UP EVENT, Port: %d ", FromPort)); + SkAddrMcUpdate(pAC,IoC, FromPort); /* Mac update */ + if (DoPrintInterfaceChange) { + printk("%s: network connection up using port %c\n", + pAC->dev[FromPort]->name, 'A'+FromPort); - /* tschilling: Values changed according to LinkSpeedUsed. */ - Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed; - if (Stat == SK_LSPEED_STAT_10MBPS) { - printk(" speed: 10\n"); - } else if (Stat == SK_LSPEED_STAT_100MBPS) { - printk(" speed: 100\n"); - } else if (Stat == SK_LSPEED_STAT_1000MBPS) { - printk(" speed: 1000\n"); - } else { - printk(" speed: unknown\n"); - } - - Stat = pAC->GIni.GP[FromPort].PLinkModeStatus; - if (Stat == SK_LMODE_STAT_AUTOHALF || - Stat == SK_LMODE_STAT_AUTOFULL) { - printk(" autonegotiation: yes\n"); - } - else { - printk(" autonegotiation: no\n"); - } - if (Stat == SK_LMODE_STAT_AUTOHALF || - Stat == SK_LMODE_STAT_HALF) { - printk(" duplex mode: half\n"); - } - else { - printk(" duplex mode: full\n"); - } - Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus; - if (Stat == SK_FLOW_STAT_REM_SEND ) { - printk(" flowctrl: remote send\n"); - } - else if (Stat == SK_FLOW_STAT_LOC_SEND ){ - printk(" flowctrl: local send\n"); - } - else if (Stat == SK_FLOW_STAT_SYMMETRIC ){ - printk(" flowctrl: symmetric\n"); - } - else { - printk(" flowctrl: none\n"); - } - - /* tschilling: Check against CopperType now. */ - if ((pAC->GIni.GICopperType == SK_TRUE) && - (pAC->GIni.GP[FromPort].PLinkSpeedUsed == - SK_LSPEED_STAT_1000MBPS)) { - Stat = pAC->GIni.GP[FromPort].PMSStatus; - if (Stat == SK_MS_STAT_MASTER ) { - printk(" role: master\n"); + /* tschilling: Values changed according to LinkSpeedUsed. */ + Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed; + if (Stat == SK_LSPEED_STAT_10MBPS) { + printk(" speed: 10\n"); + } else if (Stat == SK_LSPEED_STAT_100MBPS) { + printk(" speed: 100\n"); + } else if (Stat == SK_LSPEED_STAT_1000MBPS) { + printk(" speed: 1000\n"); + } else { + printk(" speed: unknown\n"); } - else if (Stat == SK_MS_STAT_SLAVE ) { - printk(" role: slave\n"); - } - else { - printk(" role: ???\n"); - } - } -#ifdef SK_ZEROCOPY - if (pAC->GIni.GIChipId == CHIP_ID_YUKON) - printk(" scatter-gather: enabled\n"); - else - printk(" scatter-gather: disabled\n"); + Stat = pAC->GIni.GP[FromPort].PLinkModeStatus; + if ((Stat == SK_LMODE_STAT_AUTOHALF) || + (Stat == SK_LMODE_STAT_AUTOFULL)) { + printk(" autonegotiation: yes\n"); + } else { + printk(" autonegotiation: no\n"); + } -#else - printk(" scatter-gather: disabled\n"); + if ((Stat == SK_LMODE_STAT_AUTOHALF) || + (Stat == SK_LMODE_STAT_HALF)) { + printk(" duplex mode: half\n"); + } else { + printk(" duplex mode: full\n"); + } + + Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus; + if (Stat == SK_FLOW_STAT_REM_SEND ) { + printk(" flowctrl: remote send\n"); + } else if (Stat == SK_FLOW_STAT_LOC_SEND ) { + printk(" flowctrl: local send\n"); + } else if (Stat == SK_FLOW_STAT_SYMMETRIC ) { + printk(" flowctrl: symmetric\n"); + } else { + printk(" flowctrl: none\n"); + } + + /* tschilling: Check against CopperType now. */ + if ((pAC->GIni.GICopperType == SK_TRUE) && + (pAC->GIni.GP[FromPort].PLinkSpeedUsed == + SK_LSPEED_STAT_1000MBPS)) { + Stat = pAC->GIni.GP[FromPort].PMSStatus; + if (Stat == SK_MS_STAT_MASTER ) { + printk(" role: master\n"); + } else if (Stat == SK_MS_STAT_SLAVE ) { + printk(" role: slave\n"); + } else { + printk(" role: ???\n"); + } + } + + /* Display interrupt moderation informations */ + if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) { + printk(" irq moderation: static (%d ints/sec)\n", + pAC->DynIrqModInfo.MaxModIntsPerSec); + } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) { + printk(" irq moderation: dynamic (%d ints/sec)\n", + pAC->DynIrqModInfo.MaxModIntsPerSec); + } else { + printk(" irq moderation: disabled\n"); + } + +#ifdef NETIF_F_TSO + if (CHIP_ID_YUKON_2(pAC)) { + if (pAC->dev[FromPort]->features & NETIF_F_TSO) { + printk(" tcp offload: enabled\n"); + } else { + printk(" tcp offload: disabled\n"); + } + } #endif -#endif /* SK98_INFO */ - if ((Param.Para32[0] != pAC->ActivePort) && - (pAC->RlmtNets == 1)) { - NewPara.Para32[0] = pAC->ActivePort; - NewPara.Para32[1] = Param.Para32[0]; - SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN, - NewPara); +#if 0 /* uboot */ + if (pAC->dev[FromPort]->features & NETIF_F_SG) { + printk(" scatter-gather: enabled\n"); + } else { + printk(" scatter-gather: disabled\n"); + } + + if (pAC->dev[FromPort]->features & NETIF_F_IP_CSUM) { + printk(" tx-checksum: enabled\n"); + } else { + printk(" tx-checksum: disabled\n"); + } + + if (pAC->RxPort[FromPort].UseRxCsum) { + printk(" rx-checksum: enabled\n"); + } else { + printk(" rx-checksum: disabled\n"); + } +#ifdef CONFIG_SK98LIN_NAPI + printk(" rx-polling: enabled\n"); +#endif +#endif + if (pAC->LowLatency) { + printk(" low latency: enabled\n"); + } + } else { + DoPrintInterfaceChange = SK_TRUE; + } + + if ((FromPort != pAC->ActivePort)&&(pAC->RlmtNets == 1)) { + SkLocalEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN, + pAC->ActivePort, FromPort, SK_FALSE); } /* Inform the world that link protocol is up. */ -#if 0 - pAC->dev[Param.Para32[0]]->flags |= IFF_RUNNING; + netif_wake_queue(pAC->dev[FromPort]); +#if 0 //u-boot + netif_carrier_on(pAC->dev[FromPort]); + pAC->dev[FromPort]->flags |= IFF_RUNNING; #endif - + spin_unlock_irqrestore(&pAC->InitLock, InitFlags); break; - case SK_DRV_NET_DOWN: /* SK_U32 Reason */ - /* action list 7 */ + case SK_DRV_NET_DOWN: + Reason = Param.Para32[0]; + FromPort = Param.Para32[1]; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, ("NET DOWN EVENT ")); -#ifdef SK98_INFO - printk("%s: network connection down\n", pAC->dev[Param.Para32[1]]->name); + +#if 0 //u-boot + /* Stop queue and carrier */ + netif_stop_queue(pAC->dev[FromPort]); + netif_carrier_off(pAC->dev[FromPort]); #endif -#if 0 - pAC->dev[Param.Para32[1]]->flags &= ~IFF_RUNNING; + + /* Print link change */ + if (DoPrintInterfaceChange) { +#if 0 /* uboot */ + if (pAC->dev[FromPort]->flags & IFF_RUNNING) { + printk("%s: network connection down\n", + pAC->dev[FromPort]->name); + } +#endif + } else { + DoPrintInterfaceChange = SK_TRUE; + } +#if 0 /* uboot */ + pAC->dev[FromPort]->flags &= ~IFF_RUNNING; #endif break; - case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, - ("PORT SWITCH HARD ")); - case SK_DRV_SWITCH_SOFT: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ - /* action list 6 */ - printk("%s: switching to port %c\n", pAC->dev[0]->name, - 'A'+Param.Para32[1]); - case SK_DRV_SWITCH_INTERN: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ + case SK_DRV_SWITCH_HARD: /* FALL THRU */ + case SK_DRV_SWITCH_SOFT: /* FALL THRU */ + case SK_DRV_SWITCH_INTERN: FromPort = Param.Para32[0]; - ToPort = Param.Para32[1]; + ToPort = Param.Para32[1]; + printk("%s: switching from port %c to port %c\n", + pAC->dev[0]->name, 'A'+FromPort, 'A'+ToPort); SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, ("PORT SWITCH EVENT, From: %d To: %d (Pref %d) ", FromPort, ToPort, pAC->Rlmt.Net[0].PrefPort)); - NewPara.Para64 = FromPort; - SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara); - NewPara.Para64 = ToPort; - SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara); + SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET, + FromPort, SK_FALSE); + SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET, + ToPort, SK_FALSE); spin_lock_irqsave( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); - spin_lock_irqsave( - &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); - SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST); - SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST); - spin_unlock_irqrestore( - &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock); + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST); + SkY2PortStop(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST); + } + else { + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST); + SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST); + } + spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock); spin_unlock_irqrestore( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); - ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */ - ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */ + + if (!CHIP_ID_YUKON_2(pAC)) { +#ifdef CONFIG_SK98LIN_NAPI + WorkToDo = 1; + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo); + ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE, &WorkDone, WorkToDo); +#else + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */ + ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */ +#endif + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); + ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]); + } - ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); - ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]); spin_lock_irqsave( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); - spin_lock_irqsave( - &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock); pAC->ActivePort = ToPort; + #if 0 SetQueueSizes(pAC); #else @@ -4604,13 +5941,12 @@ SK_BOOL DualNet; if (pAC->RlmtNets == 2) { DualNet = SK_TRUE; } - + if (SkGeInitAssignRamToQueues( pAC, pAC->ActivePort, DualNet)) { - spin_unlock_irqrestore( - &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock); spin_unlock_irqrestore( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); @@ -4618,40 +5954,215 @@ SK_BOOL DualNet; break; } #endif - /* tschilling: Handling of return values inserted. */ - if (SkGeInitPort(pAC, IoC, FromPort) || - SkGeInitPort(pAC, IoC, ToPort)) { - printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name); + if (!CHIP_ID_YUKON_2(pAC)) { + /* tschilling: Handling of return values inserted. */ + if (SkGeInitPort(pAC, IoC, FromPort) || + SkGeInitPort(pAC, IoC, ToPort)) { + printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name); + } } - if (Event == SK_DRV_SWITCH_SOFT) { - SkMacRxTxEnable(pAC, IoC, FromPort); + if (!CHIP_ID_YUKON_2(pAC)) { + if (Event == SK_DRV_SWITCH_SOFT) { + SkMacRxTxEnable(pAC, IoC, FromPort); + } + SkMacRxTxEnable(pAC, IoC, ToPort); } - SkMacRxTxEnable(pAC, IoC, ToPort); + SkAddrSwap(pAC, IoC, FromPort, ToPort); SkAddrMcUpdate(pAC, IoC, FromPort); SkAddrMcUpdate(pAC, IoC, ToPort); - PortReInitBmu(pAC, FromPort); - PortReInitBmu(pAC, ToPort); - SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); - SkGePollTxD(pAC, IoC, ToPort, SK_TRUE); - ClearAndStartRx(pAC, FromPort); - ClearAndStartRx(pAC, ToPort); - spin_unlock_irqrestore( - &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + +#ifdef USE_TIST_FOR_RESET + if (pAC->GIni.GIYukon2) { + /* make sure that we do not accept any status LEs from now on */ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP, + ("both Ports now waiting for specific Tist\n")); + SK_SET_WAIT_BIT_FOR_PORT( + pAC, + SK_PSTATE_WAITING_FOR_ANY_TIST, + 0); + SK_SET_WAIT_BIT_FOR_PORT( + pAC, + SK_PSTATE_WAITING_FOR_ANY_TIST, + 1); + + /* start tist */ + Y2_ENABLE_TIST(pAC->IoBase); + } +#endif + if (!CHIP_ID_YUKON_2(pAC)) { + PortReInitBmu(pAC, FromPort); + PortReInitBmu(pAC, ToPort); + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); + SkGePollTxD(pAC, IoC, ToPort, SK_TRUE); + CLEAR_AND_START_RX(FromPort); + CLEAR_AND_START_RX(ToPort); + } else { + SkY2PortStart(pAC, IoC, FromPort); + SkY2PortStart(pAC, IoC, ToPort); +#ifdef SK_YUKON2 + /* in yukon-II always port 0 has to be started first */ + // SkY2PortStart(pAC, IoC, 0); + // SkY2PortStart(pAC, IoC, 1); +#endif + } + spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock); spin_unlock_irqrestore( &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, Flags); break; case SK_DRV_RLMT_SEND: /* SK_MBUF *pMb */ - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, - ("RLS ")); + SK_DBG_MSG(NULL,SK_DBGMOD_DRV,SK_DBGCAT_DRV_EVENT,("RLS ")); pRlmtMbuf = (SK_MBUF*) Param.pParaPtr; pMsg = (struct sk_buff*) pRlmtMbuf->pOs; skb_put(pMsg, pRlmtMbuf->Length); - if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW], - pMsg) < 0) + if (!CHIP_ID_YUKON_2(pAC)) { + if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW], + pMsg) < 0) { + DEV_KFREE_SKB_ANY(pMsg); + } + } else { + if (SkY2RlmtSend(pAC, pRlmtMbuf->PortIdx, pMsg) < 0) { + DEV_KFREE_SKB_ANY(pMsg); + } + } + break; + case SK_DRV_TIMER: + if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) { + /* check what IRQs are to be moderated */ + SkDimStartModerationTimer(pAC); + SkDimModerate(pAC); + } else { + printk("Expiration of unknown timer\n"); + } + break; + case SK_DRV_ADAP_FAIL: +#if (!defined (Y2_RECOVERY) && !defined (Y2_LE_CHECK)) + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("ADAPTER FAIL EVENT\n")); + printk("%s: Adapter failed.\n", pAC->dev[0]->name); + SK_OUT32(pAC->IoBase, B0_IMSK, 0); /* disable interrupts */ + break; +#endif - DEV_KFREE_SKB_ANY(pMsg); +#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK)) + case SK_DRV_RECOVER: + spin_lock_irqsave(&pAC->InitLock, InitFlags); + pNet = (DEV_NET *) pAC->dev[Param.Para32[0]]->priv; + + /* Recover already in progress */ + if (pNet->InRecover) { + break; + } + + netif_stop_queue(pAC->dev[Param.Para32[0]]); /* stop device if running */ + pNet->InRecover = SK_TRUE; + + FromPort = Param.Para32[0]; + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("PORT RESET EVENT, Port: %d ", FromPort)); + + /* Disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + SK_OUT32(pAC->IoBase, B0_HWE_IMSK, 0); + + SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET, + FromPort, SK_FALSE); + spin_lock_irqsave( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST); + } else { + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST); + } +#if 0 //u-boot + pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING; +#endif + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + + if (!CHIP_ID_YUKON_2(pAC)) { +#ifdef CONFIG_SK98LIN_NAPI + WorkToDo = 1; + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo); +#else + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); +#endif + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); + } + spin_lock_irqsave( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + +#ifdef USE_TIST_FOR_RESET + if (pAC->GIni.GIYukon2) { +#if 0 + /* make sure that we do not accept any status LEs from now on */ + Y2_ENABLE_TIST(pAC->IoBase); + + /* get current timestamp */ + Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo); + pAC->MinTistHi = pAC->GIni.GITimeStampCnt; + + SK_SET_WAIT_BIT_FOR_PORT( + pAC, + SK_PSTATE_WAITING_FOR_SPECIFIC_TIST, + FromPort); +#endif + SK_SET_WAIT_BIT_FOR_PORT( + pAC, + SK_PSTATE_WAITING_FOR_ANY_TIST, + FromPort); + + /* start tist */ + Y2_ENABLE_TIST(pAC->IoBase); + } +#endif + + /* Restart Receive BMU on Yukon-2 */ + if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) { + SkYuk2RestartRxBmu(pAC, IoC, FromPort); + } + +#ifdef Y2_LE_CHECK + /* mark entries invalid */ + pAC->LastPort = 3; + pAC->LastOpc = 0xFF; +#endif + +#endif + /* Restart ports but do not initialize PHY. */ + if (CHIP_ID_YUKON_2(pAC)) { + SkY2PortStart(pAC, IoC, FromPort); + } else { + /* tschilling: Handling of return value inserted. */ + if (SkGeInitPort(pAC, IoC, FromPort)) { + if (FromPort == 0) { + printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name); + } else { + printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name); + } + } + SkAddrMcUpdate(pAC,IoC, FromPort); + PortReInitBmu(pAC, FromPort); + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); + CLEAR_AND_START_RX(FromPort); + } + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + + /* Map any waiting RX buffers to HW */ + FillReceiveTableYukon2(pAC, pAC->IoBase, FromPort); + + pNet->InRecover = SK_FALSE; + /* enable Interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); + SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK); + netif_wake_queue(pAC->dev[FromPort]); + spin_unlock_irqrestore(&pAC->InitLock, InitFlags); break; default: break; @@ -4663,6 +6174,103 @@ SK_BOOL DualNet; } /* SkDrvEvent */ +/****************************************************************************** + * + * SkLocalEventQueue() - add event to queue + * + * Description: + * This function adds an event to the event queue and run the + * SkEventDispatcher. At least Init Level 1 is required to queue events, + * but will be scheduled add Init Level 2. + * + * returns: + * nothing + */ +void SkLocalEventQueue( +SK_AC *pAC, /* Adapters context */ +SK_U32 Class, /* Event Class */ +SK_U32 Event, /* Event to be queued */ +SK_U32 Param1, /* Event parameter 1 */ +SK_U32 Param2, /* Event parameter 2 */ +SK_BOOL Dispatcher) /* Dispatcher flag: + * TRUE == Call SkEventDispatcher + * FALSE == Don't execute SkEventDispatcher + */ +{ + SK_EVPARA EvPara; + EvPara.Para32[0] = Param1; + EvPara.Para32[1] = Param2; + + + if (Class == SKGE_PNMI) { + #ifdef SK_PNMI_SUPPORT + SkPnmiEvent( pAC, + pAC->IoBase, + Event, + EvPara); + #endif + } else { + SkEventQueue( pAC, + Class, + Event, + EvPara); + } + + /* Run the dispatcher */ + if (Dispatcher) { + SkEventDispatcher(pAC, pAC->IoBase); + } + +} + +/****************************************************************************** + * + * SkLocalEventQueue64() - add event to queue (64bit version) + * + * Description: + * This function adds an event to the event queue and run the + * SkEventDispatcher. At least Init Level 1 is required to queue events, + * but will be scheduled add Init Level 2. + * + * returns: + * nothing + */ +void SkLocalEventQueue64( +SK_AC *pAC, /* Adapters context */ +SK_U32 Class, /* Event Class */ +SK_U32 Event, /* Event to be queued */ +SK_U64 Param, /* Event parameter */ +SK_BOOL Dispatcher) /* Dispatcher flag: + * TRUE == Call SkEventDispatcher + * FALSE == Don't execute SkEventDispatcher + */ +{ + SK_EVPARA EvPara; + EvPara.Para64 = Param; + + + if (Class == SKGE_PNMI) { + #ifdef SK_PNMI_SUPPORT + SkPnmiEvent( pAC, + pAC->IoBase, + Event, + EvPara); + #endif + } else { + SkEventQueue( pAC, + Class, + Event, + EvPara); + } + + /* Run the dispatcher */ + if (Dispatcher) { + SkEventDispatcher(pAC, pAC->IoBase); + } + +} + + /***************************************************************************** * * SkErrorLog - log errors @@ -4673,7 +6281,7 @@ SK_BOOL DualNet; * Returns: * 0 if everything ok * < 0 on error - * + * */ void SkErrorLog( SK_AC *pAC, @@ -4712,12 +6320,258 @@ char ClassStr[80]; } /* SkErrorLog */ +/***************************************************************************** + * + * SkDrvEnterDiagMode - handles DIAG attach request + * + * Description: + * Notify the kernel to NOT access the card any longer due to DIAG + * Deinitialize the Card + * + * Returns: + * int + */ +int SkDrvEnterDiagMode( +SK_AC *pAc) /* pointer to adapter context */ +{ + SK_AC *pAC = NULL; + DEV_NET *pNet = NULL; + + pNet = (DEV_NET *) pAc->dev[0]->priv; + pAC = pNet->pAC; + + SK_MEMCPY(&(pAc->PnmiBackup), &(pAc->PnmiStruct), + sizeof(SK_PNMI_STRUCT_DATA)); + + pAC->DiagModeActive = DIAG_ACTIVE; + if (pAC->BoardLevel > SK_INIT_DATA) { + if (netif_running(pAC->dev[0])) { + pAC->WasIfUp[0] = SK_TRUE; + pAC->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */ + DoPrintInterfaceChange = SK_FALSE; + SkDrvDeInitAdapter(pAC, 0); /* performs SkGeClose */ + } else { + pAC->WasIfUp[0] = SK_FALSE; + } + + if (pNet != (DEV_NET *) pAc->dev[1]->priv) { + pNet = (DEV_NET *) pAc->dev[1]->priv; + if (netif_running(pAC->dev[1])) { + pAC->WasIfUp[1] = SK_TRUE; + pAC->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */ + DoPrintInterfaceChange = SK_FALSE; + SkDrvDeInitAdapter(pAC, 1); /* do SkGeClose */ + } else { + pAC->WasIfUp[1] = SK_FALSE; + } + } + pAC->BoardLevel = SK_INIT_DATA; + } + return(0); +} + +#ifdef DSK_DIAG_SUPPORT +/***************************************************************************** + * + * SkDrvLeaveDiagMode - handles DIAG detach request + * + * Description: + * Notify the kernel to may access the card again after use by DIAG + * Initialize the Card + * + * Returns: + * int + */ +int SkDrvLeaveDiagMode( +SK_AC *pAc) /* pointer to adapter control context */ +{ + SK_MEMCPY(&(pAc->PnmiStruct), &(pAc->PnmiBackup), + sizeof(SK_PNMI_STRUCT_DATA)); + pAc->DiagModeActive = DIAG_NOTACTIVE; + #ifdef SK_DIAG_SUPPORT + + pAc->Pnmi.DiagAttached = SK_DIAG_IDLE; + #endif //SK_DIAG_SUPPORT + + if (pAc->WasIfUp[0] == SK_TRUE) { + pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */ + DoPrintInterfaceChange = SK_FALSE; + SkDrvInitAdapter(pAc, 0); /* first device */ + } + if (pAc->WasIfUp[1] == SK_TRUE) { + pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */ + DoPrintInterfaceChange = SK_FALSE; + SkDrvInitAdapter(pAc, 1); /* second device */ + } + return(0); +} +#endif /* DSK_DIAG_SUPPORT */ + +#if 0 /* uboot */ +/***************************************************************************** + * + * ParseDeviceNbrFromSlotName - Evaluate PCI device number + * + * Description: + * This function parses the PCI slot name information string and will + * retrieve the devcie number out of it. The slot_name maintianed by + * linux is in the form of '02:0a.0', whereas the first two characters + * represent the bus number in hex (in the sample above this is + * pci bus 0x02) and the next two characters the device number (0x0a). + * + * Returns: + * SK_U32: The device number from the PCI slot name + */ + +static SK_U32 ParseDeviceNbrFromSlotName( +const char *SlotName) /* pointer to pci slot name eg. '02:0a.0' */ +{ + char *CurrCharPos = (char *) SlotName; + int FirstNibble = -1; + int SecondNibble = -1; + SK_U32 Result = 0; + + while (*CurrCharPos != '\0') { + if (*CurrCharPos == ':') { + while (*CurrCharPos != '.') { + CurrCharPos++; + if ( (*CurrCharPos >= '0') && + (*CurrCharPos <= '9')) { + if (FirstNibble == -1) { + /* dec. value for '0' */ + FirstNibble = *CurrCharPos - 48; + } else { + SecondNibble = *CurrCharPos - 48; + } + } else if ( (*CurrCharPos >= 'a') && + (*CurrCharPos <= 'f') ) { + if (FirstNibble == -1) { + FirstNibble = *CurrCharPos - 87; + } else { + SecondNibble = *CurrCharPos - 87; + } + } else { + Result = 0; + } + } + + Result = FirstNibble; + Result = Result << 4; /* first nibble is higher one */ + Result = Result | SecondNibble; + } + CurrCharPos++; /* next character */ + } + return (Result); +} +#endif +/**************************************************************************** + * + * SkDrvDeInitAdapter - deinitialize adapter (this function is only + * called if Diag attaches to that card) + * + * Description: + * Close initialized adapter. + * + * Returns: + * 0 - on success + * error code - on error + */ +static int SkDrvDeInitAdapter( +SK_AC *pAC, /* pointer to adapter context */ +int devNbr) /* what device is to be handled */ +{ + struct SK_NET_DEVICE *dev; + + dev = pAC->dev[devNbr]; + + /* + ** Function SkGeClose() uses MOD_DEC_USE_COUNT (2.2/2.4) + ** or module_put() (2.6) to decrease the number of users for + ** a device, but if a device is to be put under control of + ** the DIAG, that count is OK already and does not need to + ** be adapted! Hence the opposite MOD_INC_USE_COUNT or + ** try_module_get() needs to be used again to correct that. + */ + MOD_INC_USE_COUNT; + + if (SkGeClose(dev) != 0) { + MOD_DEC_USE_COUNT; + return (-1); + } + return (0); + +} /* SkDrvDeInitAdapter() */ + +#if 0 /* uboot*/ +/**************************************************************************** + * + * SkDrvInitAdapter - Initialize adapter (this function is only + * called if Diag deattaches from that card) + * + * Description: + * Close initialized adapter. + * + * Returns: + * 0 - on success + * error code - on error + */ +static int SkDrvInitAdapter( +SK_AC *pAC, /* pointer to adapter context */ +int devNbr) /* what device is to be handled */ +{ + struct SK_NET_DEVICE *dev; + + dev = pAC->dev[devNbr]; + + if (SkGeOpen(dev) != 0) { + return (-1); + } else { + /* + ** Function SkGeOpen() uses MOD_INC_USE_COUNT (2.2/2.4) + ** or try_module_get() (2.6) to increase the number of + ** users for a device, but if a device was just under + ** control of the DIAG, that count is OK already and + ** does not need to be adapted! Hence the opposite + ** MOD_DEC_USE_COUNT or module_put() needs to be used + ** again to correct that. + */ + module_put(THIS_MODULE); + } + + /* + ** Use correct MTU size and indicate to kernel TX queue can be started + */ +#if 0 /* uboot */ + if (SkGeChangeMtu(dev, dev->mtu) != 0) { + return (-1); + } +#endif + return (0); + +} /* SkDrvInitAdapter */ + +#endif +#if 0 /* uboot */ +static int __init sk98lin_init(void) +{ + return pci_module_init(&sk98lin_driver); +} + +static void __exit sk98lin_cleanup(void) +{ + pci_unregister_driver(&sk98lin_driver); +} + +module_init(sk98lin_init); +module_exit(sk98lin_cleanup); + +#endif + #ifdef DEBUG /****************************************************************************/ /* "debug only" section *****************************************************/ /****************************************************************************/ - /***************************************************************************** * * DumpMsg - print a frame @@ -4726,11 +6580,13 @@ char ClassStr[80]; * This function prints frames to the system logfile/to the console. * * Returns: N/A - * + * */ -static void DumpMsg(struct sk_buff *skb, char *str) +static void DumpMsg( +struct sk_buff *skb, /* linux' socket buffer */ +char *str) /* additional msg string */ { - int msglen; + int msglen = (skb->len > 64) ? 64 : skb->len; if (skb == NULL) { printk("DumpMsg(): NULL-Message\n"); @@ -4741,19 +6597,16 @@ static void DumpMsg(struct sk_buff *skb, char *str) printk("DumpMsg(): Message empty\n"); return; } - - msglen = skb->len; - if (msglen > 64) - msglen = 64; - - printk("--- Begin of message from %s , len %d (from %d) ----\n", str, msglen, skb->len); - +#if 0 /* uboot */ + printk("DumpMsg: PhysPage: %p\n", + page_address(virt_to_page(skb->data))); +#endif + printk("--- Begin of message from %s , len %d (from %d) ----\n", + str, msglen, skb->len); DumpData((char *)skb->data, msglen); - printk("------- End of message ---------\n"); } /* DumpMsg */ - /***************************************************************************** * * DumpData - print a data area @@ -4763,25 +6616,24 @@ static void DumpMsg(struct sk_buff *skb, char *str) * console. * * Returns: N/A - * + * */ -static void DumpData(char *p, int size) +static void DumpData( +char *p, /* pointer to area containing the data */ +int size) /* the size of that data area in bytes */ { -register int i; -int haddr, addr; -char hex_buffer[180]; -char asc_buffer[180]; -char HEXCHAR[] = "0123456789ABCDEF"; + register int i; + int haddr = 0, addr = 0; + char hex_buffer[180] = { '\0' }; + char asc_buffer[180] = { '\0' }; + char HEXCHAR[] = "0123456789ABCDEF"; - addr = 0; - haddr = 0; - hex_buffer[0] = 0; - asc_buffer[0] = 0; for (i=0; i < size; ) { - if (*p >= '0' && *p <='z') + if (*p >= '0' && *p <='z') { asc_buffer[addr] = *p; - else + } else { asc_buffer[addr] = '.'; + } addr++; asc_buffer[addr] = 0; hex_buffer[haddr] = HEXCHAR[(*p & 0xf0) >> 4]; @@ -4807,27 +6659,24 @@ char HEXCHAR[] = "0123456789ABCDEF"; * DumpLong - print a data area as long values * * Description: - * This function prints a area of data to the system logfile/to the + * This function prints a long variable to the system logfile/to the * console. * * Returns: N/A - * + * */ -static void DumpLong(char *pc, int size) +static void DumpLong( +char *pc, /* location of the variable to print */ +int size) /* how large is the variable? */ { -register int i; -int haddr, addr; -char hex_buffer[180]; -char asc_buffer[180]; -char HEXCHAR[] = "0123456789ABCDEF"; -long *p; -int l; + register int i; + int haddr = 0, addr = 0; + char hex_buffer[180] = { '\0' }; + char asc_buffer[180] = { '\0' }; + char HEXCHAR[] = "0123456789ABCDEF"; + long *p = (long*) pc; + int l; - addr = 0; - haddr = 0; - hex_buffer[0] = 0; - asc_buffer[0] = 0; - p = (long*) pc; for (i=0; i < size; ) { l = (long) *p; hex_buffer[haddr] = HEXCHAR[(l >> 28) & 0xf]; @@ -4861,4 +6710,11 @@ int l; #endif -#endif /* CONFIG_SK98 */ +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ + +#endif + diff --git a/drivers/sk98lin/skgehwt.c b/drivers/sk98lin/skgehwt.c index f8681a8..555a41b 100644 --- a/drivers/sk98lin/skgehwt.c +++ b/drivers/sk98lin/skgehwt.c @@ -1,17 +1,17 @@ /****************************************************************************** * * Name: skgehwt.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.13 $ - * Date: $Date: 1999/11/22 13:31:12 $ - * Purpose: Hardware Timer. + * Project: Gigabit Ethernet Adapters, Event Scheduler Module + * Version: $Revision: 2.2 $ + * Date: $Date: 2004/05/28 13:39:04 $ + * Purpose: Hardware Timer * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998,1999 SysKonnect, - * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,76 +22,24 @@ * ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: skgehwt.c,v $ - * Revision 1.13 1999/11/22 13:31:12 cgoos - * Changed license header to GPL. - * - * Revision 1.12 1998/10/15 15:11:34 gklug - * fix: ID_sccs to SysKonnectFileId - * - * Revision 1.11 1998/10/08 15:27:51 gklug - * chg: correction factor is host clock dependent - * - * Revision 1.10 1998/09/15 14:18:31 cgoos - * Changed more BOOLEANs to SK_xxx - * - * Revision 1.9 1998/09/15 14:16:06 cgoos - * Changed line 107: FALSE to SK_FALSE - * - * Revision 1.8 1998/08/24 13:04:44 gklug - * fix: typo - * - * Revision 1.7 1998/08/19 09:50:49 gklug - * fix: remove struct keyword from c-code (see CCC) add typedefs - * - * Revision 1.6 1998/08/17 09:59:02 gklug - * fix: typos - * - * Revision 1.5 1998/08/14 07:09:10 gklug - * fix: chg pAc -> pAC - * - * Revision 1.4 1998/08/10 14:14:52 gklug - * rmv: unneccessary SK_ADDR macro - * - * Revision 1.3 1998/08/07 12:53:44 gklug - * fix: first compiled version - * - * Revision 1.2 1998/08/07 09:19:29 gklug - * adapt functions to the C coding conventions - * rmv unneccessary functions. - * - * Revision 1.1 1998/08/05 11:28:36 gklug - * first version: adapted from SMT/FDDI - * - * - * - * - ******************************************************************************/ - - #include - + #ifdef CONFIG_SK98 /* - Event queue and dispatcher -*/ + * Event queue and dispatcher + */ +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) static const char SysKonnectFileId[] = - "$Header: /usr56/projects/ge/schedule/skgehwt.c,v 1.13 1999/11/22 13:31:12 cgoos Exp $" ; + "@(#) $Id: skgehwt.c,v 2.2 2004/05/28 13:39:04 rschmidt Exp $ (C) Marvell."; +#endif #include "h/skdrv1st.h" /* Driver Specific Definitions */ #include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ #ifdef __C2MAN__ /* - Hardware Timer function queue management. - - General Description: - + * Hardware Timer function queue management. */ intro() {} @@ -100,10 +48,10 @@ intro() /* * Prototypes of local functions. */ -#define SK_HWT_MAX (65000) +#define SK_HWT_MAX 65000UL * 160 /* ca. 10 sec. */ /* correction factor */ -#define SK_HWT_FAC (1000 * (SK_U32)pAC->GIni.GIHstClkFact / 100) +#define SK_HWT_FAC (10 * (SK_U32)pAC->GIni.GIHstClkFact / 16) /* * Initialize hardware timer. @@ -116,9 +64,9 @@ SK_IOC Ioc) /* IoContext */ { pAC->Hwt.TStart = 0 ; pAC->Hwt.TStop = 0 ; - pAC->Hwt.TActive = SK_FALSE ; + pAC->Hwt.TActive = SK_FALSE; - SkHwtStop(pAC,Ioc) ; + SkHwtStop(pAC, Ioc); } /* @@ -129,30 +77,23 @@ SK_IOC Ioc) /* IoContext */ void SkHwtStart( SK_AC *pAC, /* Adapters context */ SK_IOC Ioc, /* IoContext */ -SK_U32 Time) /* Time in units of 16us to load the timer with. */ +SK_U32 Time) /* Time in usec to load the timer */ { - SK_U32 Cnt ; - if (Time > SK_HWT_MAX) - Time = SK_HWT_MAX ; + Time = SK_HWT_MAX; - pAC->Hwt.TStart = Time ; - pAC->Hwt.TStop = 0L ; + pAC->Hwt.TStart = Time; + pAC->Hwt.TStop = 0L; - Cnt = Time ; - - /* - * if time < 16 us - * time = 16 us - */ - if (!Cnt) { - Cnt++ ; + if (!Time) { + Time = 1L; } - SK_OUT32(Ioc, B2_TI_INI, Cnt * SK_HWT_FAC) ; - SK_OUT16(Ioc, B2_TI_CRTL, TIM_START) ; /* Start timer. */ + SK_OUT32(Ioc, B2_TI_INI, Time * SK_HWT_FAC); - pAC->Hwt.TActive = SK_TRUE ; + SK_OUT16(Ioc, B2_TI_CTRL, TIM_START); /* Start timer */ + + pAC->Hwt.TActive = SK_TRUE; } /* @@ -163,13 +104,13 @@ void SkHwtStop( SK_AC *pAC, /* Adapters context */ SK_IOC Ioc) /* IoContext */ { - SK_OUT16(Ioc, B2_TI_CRTL, TIM_STOP) ; - SK_OUT16(Ioc, B2_TI_CRTL, TIM_CLR_IRQ) ; + SK_OUT16(Ioc, B2_TI_CTRL, TIM_STOP); - pAC->Hwt.TActive = SK_FALSE ; + SK_OUT16(Ioc, B2_TI_CTRL, TIM_CLR_IRQ); + + pAC->Hwt.TActive = SK_FALSE; } - /* * Stop hardware timer and read time elapsed since last start. * @@ -181,26 +122,34 @@ SK_U32 SkHwtRead( SK_AC *pAC, /* Adapters context */ SK_IOC Ioc) /* IoContext */ { - SK_U32 TRead ; - SK_U32 IStatus ; + SK_U32 TRead; + SK_U32 IStatus; + SK_U32 TimerInt; + + TimerInt = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TIMINT : IS_TIMINT; if (pAC->Hwt.TActive) { - SkHwtStop(pAC,Ioc) ; + + SkHwtStop(pAC, Ioc); SK_IN32(Ioc, B2_TI_VAL, &TRead); TRead /= SK_HWT_FAC; SK_IN32(Ioc, B0_ISRC, &IStatus); - /* Check if timer expired (or wraparound). */ - if ((TRead > pAC->Hwt.TStart) || (IStatus & IS_TIMINT)) { - SkHwtStop(pAC,Ioc) ; - pAC->Hwt.TStop = pAC->Hwt.TStart ; - } else { - pAC->Hwt.TStop = pAC->Hwt.TStart - TRead ; + /* Check if timer expired (or wrapped around) */ + if ((TRead > pAC->Hwt.TStart) || ((IStatus & TimerInt) != 0)) { + + SkHwtStop(pAC, Ioc); + + pAC->Hwt.TStop = pAC->Hwt.TStart; + } + else { + + pAC->Hwt.TStop = pAC->Hwt.TStart - TRead; } } - return (pAC->Hwt.TStop) ; + return(pAC->Hwt.TStop); } /* @@ -210,11 +159,13 @@ void SkHwtIsr( SK_AC *pAC, /* Adapters context */ SK_IOC Ioc) /* IoContext */ { - SkHwtStop(pAC,Ioc); + SkHwtStop(pAC, Ioc); + pAC->Hwt.TStop = pAC->Hwt.TStart; - SkTimerDone(pAC,Ioc) ; + + SkTimerDone(pAC, Ioc); } -#endif /* CONFIG_SK98 */ - /* End of file */ + +#endif diff --git a/drivers/sk98lin/skgeinit.c b/drivers/sk98lin/skgeinit.c index a18dc0a..7d89134 100644 --- a/drivers/sk98lin/skgeinit.c +++ b/drivers/sk98lin/skgeinit.c @@ -1,398 +1,29 @@ /****************************************************************************** * * Name: skgeinit.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.85 $ - * Date: $Date: 2003/02/05 15:30:33 $ - * Purpose: Contains functions to initialize the GE HW + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 2.99 $ + * Date: $Date: 2006/04/27 07:45:23 $ + * Purpose: Contains functions to initialize the adapter * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2006 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. + * /LICENSE * ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: skgeinit.c,v $ - * Revision 1.85 2003/02/05 15:30:33 rschmidt - * Corrected setting of GIHstClkFact (Host Clock Factor) and - * GIPollTimerVal (Descr. Poll Timer Init Value) for YUKON. - * Editorial changes. - * - * Revision 1.84 2003/01/28 09:57:25 rschmidt - * Added detection of YUKON-Lite Rev. A0 (stored in GIYukonLite). - * Disabled Rx GMAC FIFO Flush for YUKON-Lite Rev. A0. - * Added support for CLK_RUN (YUKON-Lite). - * Added additional check of PME from D3cold for setting GIVauxAvail. - * Editorial changes. - * - * Revision 1.83 2002/12/17 16:15:41 rschmidt - * Added default setting of PhyType (Copper) for YUKON. - * Added define around check for HW self test results. - * Editorial changes. - * - * Revision 1.82 2002/12/05 13:40:21 rschmidt - * Added setting of Rx GMAC FIFO Flush Mask register. - * Corrected PhyType with new define SK_PHY_MARV_FIBER when - * YUKON Fiber board was found. - * Editorial changes. - * - * Revision 1.81 2002/11/15 12:48:35 rschmidt - * Replaced message SKERR_HWI_E018 with SKERR_HWI_E024 for Rx queue error - * in SkGeStopPort(). - * Added init for pAC->GIni.GIGenesis with SK_FALSE in YUKON-branch. - * Editorial changes. - * - * Revision 1.80 2002/11/12 17:28:30 rschmidt - * Initialized GIPciSlot64 and GIPciClock66 in SkGeInit1(). - * Reduced PCI FIFO watermarks for 32bit/33MHz bus in SkGeInitBmu(). - * Editorial changes. - * - * Revision 1.79 2002/10/21 09:31:02 mkarl - * Changed SkGeInitAssignRamToQueues(), removed call to - * SkGeInitAssignRamToQueues in SkGeInit1 and fixed compiler warning in - * SkGeInit1. - * - * Revision 1.78 2002/10/16 15:55:07 mkarl - * Fixed a bug in SkGeInitAssignRamToQueues. - * - * Revision 1.77 2002/10/14 15:07:22 rschmidt - * Corrected timeout handling for Rx queue in SkGeStopPort() (#10748) - * Editorial changes. - * - * Revision 1.76 2002/10/11 09:24:38 mkarl - * Added check for HW self test results. - * - * Revision 1.75 2002/10/09 16:56:44 mkarl - * Now call SkGeInitAssignRamToQueues() in Init Level 1 in order to assign - * the adapter memory to the queues. This default assignment is not suitable - * for dual net mode. - * - * Revision 1.74 2002/09/12 08:45:06 rwahl - * Set defaults for PMSCap, PLinkSpeed & PLinkSpeedCap dependent on PHY. - * - * Revision 1.73 2002/08/16 15:19:45 rschmidt - * Corrected check for Tx queues in SkGeCheckQSize(). - * Added init for new entry GIGenesis and GICopperType - * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis. - * Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros. - * - * Revision 1.72 2002/08/12 13:38:55 rschmidt - * Added check if VAUX is available (stored in GIVauxAvail) - * Initialized PLinkSpeedCap in Port struct with SK_LSPEED_CAP_1000MBPS - * Editorial changes. - * - * Revision 1.71 2002/08/08 16:32:58 rschmidt - * Added check for Tx queues in SkGeCheckQSize(). - * Added start of Time Stamp Timer (YUKON) in SkGeInit2(). - * Editorial changes. - * - * Revision 1.70 2002/07/23 16:04:26 rschmidt - * Added init for GIWolOffs (HW-Bug in YUKON 1st rev.) - * Minor changes - * - * Revision 1.69 2002/07/17 17:07:08 rwahl - * - SkGeInit1(): fixed PHY type debug output; corrected init of GIFunc - * table & GIMacType. - * - Editorial changes. - * - * Revision 1.68 2002/07/15 18:38:31 rwahl - * Added initialization for MAC type dependent function table. - * - * Revision 1.67 2002/07/15 15:45:39 rschmidt - * Added Tx Store & Forward for YUKON (GMAC Tx FIFO is only 1 kB) - * Replaced SK_PHY_MARV by SK_PHY_MARV_COPPER - * Editorial changes - * - * Revision 1.66 2002/06/10 09:35:08 rschmidt - * Replaced C++ comments (//) - * Editorial changes - * - * Revision 1.65 2002/06/05 08:33:37 rschmidt - * Changed GIRamSize and Reset sequence for YUKON. - * SkMacInit() replaced by SkXmInitMac() resp. SkGmInitMac() - * - * Revision 1.64 2002/04/25 13:03:20 rschmidt - * Changes for handling YUKON. - * Removed reference to xmac_ii.h (not necessary). - * Moved all defines into header file. - * Replaced all SkXm...() functions with SkMac...() to handle also - * YUKON's GMAC. - * Added handling for GMAC FIFO in SkGeInitMacFifo(), SkGeStopPort(). - * Removed 'goto'-directive from SkGeCfgSync(), SkGeCheckQSize(). - * Replaced all XMAC-access macros by functions: SkMacRxTxDisable(), - * SkMacFlushTxFifo(). - * Optimized timeout handling in SkGeStopPort(). - * Initialized PLinkSpeed in Port struct with SK_LSPEED_AUTO. - * Release of GMAC Link Control reset in SkGeInit1(). - * Initialized GIChipId and GIChipRev in GE Init structure. - * Added GIRamSize and PhyType values for YUKON. - * Removed use of PRxCmd to setup XMAC. - * Moved setting of XM_RX_DIS_CEXT to SkXmInitMac(). - * Use of SkGeXmitLED() only for GENESIS. - * Changes for V-CPU support. - * Editorial changes. - * - * Revision 1.63 2001/04/05 11:02:09 rassmann - * Stop Port check of the STOP bit did not take 2/18 sec as wanted. - * - * Revision 1.62 2001/02/07 07:54:21 rassmann - * Corrected copyright. - * - * Revision 1.61 2001/01/31 15:31:40 gklug - * fix: problem with autosensing an SR8800 switch - * - * Revision 1.60 2000/10/18 12:22:21 cgoos - * Added workaround for half duplex hangup. - * - * Revision 1.59 2000/10/10 11:22:06 gklug - * add: in manual half duplex mode ignore carrier extension errors - * - * Revision 1.58 2000/10/02 14:10:27 rassmann - * Reading BCOM PHY after releasing reset until it returns a valid value. - * - * Revision 1.57 2000/08/03 14:55:28 rassmann - * Waiting for I2C to be ready before de-initializing adapter - * (prevents sensors from hanging up). - * - * Revision 1.56 2000/07/27 12:16:48 gklug - * fix: Stop Port check of the STOP bit does now take 2/18 sec as wanted - * - * Revision 1.55 1999/11/22 13:32:26 cgoos - * Changed license header to GPL. - * - * Revision 1.54 1999/10/26 07:32:54 malthoff - * Initialize PHWLinkUp with SK_FALSE. Required for Diagnostics. - * - * Revision 1.53 1999/08/12 19:13:50 malthoff - * Fix for 1000BT. Do not owerwrite XM_MMU_CMD when - * disabling receiver and transmitter. Other bits - * may be lost. - * - * Revision 1.52 1999/07/01 09:29:54 gklug - * fix: DoInitRamQueue needs pAC - * - * Revision 1.51 1999/07/01 08:42:21 gklug - * chg: use Store & forward for RAM buffer when Jumbos are used - * - * Revision 1.50 1999/05/27 13:19:38 cgoos - * Added Tx PCI watermark initialization. - * Removed Tx RAM queue Store & Forward setting. - * - * Revision 1.49 1999/05/20 14:32:45 malthoff - * SkGeLinkLED() is completly removed now. - * - * Revision 1.48 1999/05/19 07:28:24 cgoos - * SkGeLinkLED no more available for drivers. - * Changes for 1000Base-T. - * - * Revision 1.47 1999/04/08 13:57:45 gklug - * add: Init of new port struct fiels PLinkResCt - * chg: StopPort Timer check - * - * Revision 1.46 1999/03/25 07:42:15 malthoff - * SkGeStopPort(): Add workaround for cache incoherency. - * Create error log entry, disable port, and - * exit loop if it does not terminate. - * Add XM_RX_LENERR_OK to the default value for the - * XMAC receive command register. - * - * Revision 1.45 1999/03/12 16:24:47 malthoff - * Remove PPollRxD and PPollTxD. - * Add check for GIPollTimerVal. - * - * Revision 1.44 1999/03/12 13:40:23 malthoff - * Fix: SkGeXmitLED(), SK_LED_TST mode does not work. - * Add: Jumbo frame support. - * Chg: Resolution of parameter IntTime in SkGeCfgSync(). - * - * Revision 1.43 1999/02/09 10:29:46 malthoff - * Bugfix: The previous modification again also for the second location. - * - * Revision 1.42 1999/02/09 09:35:16 malthoff - * Bugfix: The bits '66 MHz Capable' and 'NEWCAP are reset while - * clearing the error bits in the PCI status register. - * - * Revision 1.41 1999/01/18 13:07:02 malthoff - * Bugfix: Do not use CFG cycles after during Init- or Runtime, because - * they may not be available after Boottime. - * - * Revision 1.40 1999/01/11 12:40:49 malthoff - * Bug fix: PCI_STATUS: clearing error bits sets the UDF bit. - * - * Revision 1.39 1998/12/11 15:17:33 gklug - * chg: Init LipaAutoNeg with Unknown - * - * Revision 1.38 1998/12/10 11:02:57 malthoff - * Disable Error Log Message when calling SkGeInit(level 2) - * more than once. - * - * Revision 1.37 1998/12/07 12:18:25 gklug - * add: refinement of autosense mode: take into account the autoneg cap of LiPa - * - * Revision 1.36 1998/12/07 07:10:39 gklug - * fix: init values of LinkBroken/ Capabilities for management - * - * Revision 1.35 1998/12/02 10:56:20 gklug - * fix: do NOT init LoinkSync Counter. - * - * Revision 1.34 1998/12/01 10:53:21 gklug - * add: init of additional Counters for workaround - * - * Revision 1.33 1998/12/01 10:00:49 gklug - * add: init PIsave var in Port struct - * - * Revision 1.32 1998/11/26 14:50:40 gklug - * chg: Default is autosensing with AUTOFULL mode - * - * Revision 1.31 1998/11/25 15:36:16 gklug - * fix: do NOT stop LED Timer when port should be stopped - * - * Revision 1.30 1998/11/24 13:15:28 gklug - * add: Init PCkeckPar struct member - * - * Revision 1.29 1998/11/18 13:19:27 malthoff - * Disable packet arbiter timeouts on receive side. - * Use maximum timeout value for packet arbiter - * transmit timeouts. - * Add TestStopBit() function to handle stop RX/TX - * problem with active descriptor poll timers. - * Bug Fix: Descriptor Poll Timer not started, because - * GIPollTimerVal was initialized with 0. - * - * Revision 1.28 1998/11/13 14:24:26 malthoff - * Bug Fix: SkGeStopPort() may hang if a Packet Arbiter Timout - * is pending or occurs while waiting for TX_STOP and RX_STOP. - * The PA timeout is cleared now while waiting for TX- or RX_STOP. - * - * Revision 1.27 1998/11/02 11:04:36 malthoff - * fix the last fix - * - * Revision 1.26 1998/11/02 10:37:03 malthoff - * Fix: SkGePollTxD() enables always the synchronounous poll timer. - * - * Revision 1.25 1998/10/28 07:12:43 cgoos - * Fixed "LED_STOP" in SkGeLnkSyncCnt, "== SK_INIT_IO" in SkGeInit. - * Removed: Reset of RAM Interface in SkGeStopPort. - * - * Revision 1.24 1998/10/27 08:13:12 malthoff - * Remove temporary code. - * - * Revision 1.23 1998/10/26 07:45:03 malthoff - * Add Address Calculation Workaround: If the EPROM byte - * Id is 3, the address offset is 512 kB. - * Initialize default values for PLinkMode and PFlowCtrlMode. - * - * Revision 1.22 1998/10/22 09:46:47 gklug - * fix SysKonnectFileId typo - * - * Revision 1.21 1998/10/20 12:11:56 malthoff - * Don't dendy the Queue config if the size of the unused - * Rx qeueu is zero. - * - * Revision 1.20 1998/10/19 07:27:58 malthoff - * SkGeInitRamIface() is public to be called by diagnostics. - * - * Revision 1.19 1998/10/16 13:33:45 malthoff - * Fix: enabling descriptor polling is not allowed until - * the descriptor addresses are set. Descriptor polling - * must be handled by the driver. - * - * Revision 1.18 1998/10/16 10:58:27 malthoff - * Remove temp. code for Diag prototype. - * Remove lint warning for dummy reads. - * Call SkGeLoadLnkSyncCnt() during SkGeInitPort(). - * - * Revision 1.17 1998/10/14 09:16:06 malthoff - * Change parameter LimCount and programming of - * the limit counter in SkGeCfgSync(). - * - * Revision 1.16 1998/10/13 09:21:16 malthoff - * Don't set XM_RX_SELF_RX in RxCmd Reg, because it's - * like a Loopback Mode in half duplex. - * - * Revision 1.15 1998/10/09 06:47:40 malthoff - * SkGeInitMacArb(): set recovery counters init value - * to zero although this counters are not uesd. - * Bug fix in Rx Upper/Lower Pause Threshold calculation. - * Add XM_RX_SELF_RX to RxCmd. - * - * Revision 1.14 1998/10/06 15:15:53 malthoff - * Make sure no pending IRQ is cleared in SkGeLoadLnkSyncCnt(). - * - * Revision 1.13 1998/10/06 14:09:36 malthoff - * Add SkGeLoadLnkSyncCnt(). Modify - * the 'port stopped' condition according - * to the current problem report. - * - * Revision 1.12 1998/10/05 08:17:21 malthoff - * Add functions: SkGePollRxD(), SkGePollTxD(), - * DoCalcAddr(), SkGeCheckQSize(), - * DoInitRamQueue(), and SkGeCfgSync(). - * Add coding for SkGeInitMacArb(), SkGeInitPktArb(), - * SkGeInitMacFifo(), SkGeInitRamBufs(), - * SkGeInitRamIface(), and SkGeInitBmu(). - * - * Revision 1.11 1998/09/29 08:26:29 malthoff - * bug fix: SkGeInit0() 'i' should be increment. - * - * Revision 1.10 1998/09/28 13:19:01 malthoff - * Coding time: Save the done work. - * Modify SkGeLinkLED(), add SkGeXmitLED(), - * define SkGeCheckQSize(), SkGeInitMacArb(), - * SkGeInitPktArb(), SkGeInitMacFifo(), - * SkGeInitRamBufs(), SkGeInitRamIface(), - * and SkGeInitBmu(). Do coding for SkGeStopPort(), - * SkGeInit1(), SkGeInit2(), and SkGeInit3(). - * Do coding for SkGeDinit() and SkGeInitPort(). - * - * Revision 1.9 1998/09/16 14:29:05 malthoff - * Some minor changes. - * - * Revision 1.8 1998/09/11 05:29:14 gklug - * add: init state of a port - * - * Revision 1.7 1998/09/04 09:26:25 malthoff - * Short temporary modification. - * - * Revision 1.6 1998/09/04 08:27:59 malthoff - * Remark the do-while in StopPort() because it never ends - * without a GE adapter. - * - * Revision 1.5 1998/09/03 14:05:45 malthoff - * Change comment for SkGeInitPort(). Do not - * repair the queue sizes if invalid. - * - * Revision 1.4 1998/09/03 10:03:19 malthoff - * Implement the new interface according to the - * reviewed interface specification. - * - * Revision 1.3 1998/08/19 09:11:25 gklug - * fix: struct are removed from c-source (see CCC) - * - * Revision 1.2 1998/07/28 12:33:58 malthoff - * Add 'IoC' parameter in function declaration and SK IO macros. - * - * Revision 1.1 1998/07/23 09:48:57 malthoff - * Creation. First dummy 'C' file. - * SkGeInit(Level 0) is card_start for GE. - * SkGeDeInit() is card_stop for GE. - * - * - ******************************************************************************/ - +/*#define DEBUG*/ #include #ifdef CONFIG_SK98 @@ -404,18 +35,125 @@ /* local variables ************************************************************/ +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) static const char SysKonnectFileId[] = - "@(#)$Id: skgeinit.c,v 1.85 2003/02/05 15:30:33 rschmidt Exp $ (C) SK "; + "@(#) $Id: skgeinit.c,v 2.99 2006/04/27 07:45:23 malthoff Exp $ (C) Marvell."; +#endif struct s_QOffTab { int RxQOff; /* Receive Queue Address Offset */ int XsQOff; /* Sync Tx Queue Address Offset */ int XaQOff; /* Async Tx Queue Address Offset */ }; + static struct s_QOffTab QOffTab[] = { {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2} }; +struct s_Config { + char ScanString[8]; + SK_U32 Value; +}; + +static struct s_Config OemConfig = { + {'O','E','M','_','C','o','n','f'}, +#ifdef SK_OEM_CONFIG + OEM_CONFIG_VALUE, +#else + 0, +#endif +}; + +#ifndef SK_SLIM +/****************************************************************************** + * + * SkGePortVlan() - Enable / Disable VLAN support + * + * Description: + * Enable or disable the VLAN support of the selected port. + * The new configuration is *not* saved over any SkGeStopPort() and + * SkGeInitPort() calls. + * Currently this function is only supported on Yukon-2/EC adapters. + * + * Returns: + * nothing + */ +void SkGePortVlan( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port number */ +SK_BOOL Enable) /* Flag */ +{ + SK_U32 RxCtrl; + SK_U32 TxCtrl; + + if (CHIP_ID_YUKON_2(pAC)) { + if (Enable) { + RxCtrl = RX_VLAN_STRIP_ON; + TxCtrl = TX_VLAN_TAG_ON; + } + else { + RxCtrl = RX_VLAN_STRIP_OFF; + TxCtrl = TX_VLAN_TAG_OFF; + } + + SK_OUT32(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), RxCtrl); + SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TxCtrl); + } +} /* SkGePortVlan */ + + +/****************************************************************************** + * + * SkGeRxRss() - Enable / Disable RSS Hash Calculation + * + * Description: + * Enable or disable the RSS hash calculation of the selected port. + * The new configuration is *not* saved over any SkGeStopPort() and + * SkGeInitPort() calls. + * Currently this function is only supported on Yukon-2/EC adapters. + * + * Returns: + * nothing + */ +void SkGeRxRss( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port number */ +SK_BOOL Enable) /* Flag */ +{ + if (CHIP_ID_YUKON_2(pAC)) { + SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR), + Enable ? BMU_ENA_RX_RSS_HASH : BMU_DIS_RX_RSS_HASH); + } +} /* SkGeRxRss */ + + +/****************************************************************************** + * + * SkGeRxCsum() - Enable / Disable Receive Checksum + * + * Description: + * Enable or disable the checksum of the selected port. + * The new configuration is *not* saved over any SkGeStopPort() and + * SkGeInitPort() calls. + * Currently this function is only supported on Yukon-2/EC adapters. + * + * Returns: + * nothing + */ +void SkGeRxCsum( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port number */ +SK_BOOL Enable) /* Flag */ +{ + if (CHIP_ID_YUKON_2(pAC)) { + SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR), + Enable ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); + } +} /* SkGeRxCsum */ +#endif /* !SK_SLIM */ /****************************************************************************** * @@ -431,8 +169,8 @@ static struct s_QOffTab QOffTab[] = { * nothing */ void SkGePollRxD( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ { @@ -440,8 +178,8 @@ SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ pPrt = &pAC->GIni.GP[Port]; - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (PollRxD) ? - CSR_ENA_POL : CSR_DIS_POL); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (SK_U32)((PollRxD) ? + CSR_ENA_POL : CSR_DIS_POL)); } /* SkGePollRxD */ @@ -459,8 +197,8 @@ SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ * nothing */ void SkGePollTxD( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ { @@ -469,7 +207,7 @@ SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ pPrt = &pAC->GIni.GP[Port]; - DWord = (PollTxD) ? CSR_ENA_POL : CSR_DIS_POL; + DWord = (SK_U32)(PollTxD ? CSR_ENA_POL : CSR_DIS_POL); if (pPrt->PXSQSize != 0) { SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord); @@ -480,7 +218,7 @@ SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ } } /* SkGePollTxD */ - +#ifndef SK_SLIM /****************************************************************************** * * SkGeYellowLED() - Switch the yellow LED on or off. @@ -495,21 +233,32 @@ SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ * nothing */ void SkGeYellowLED( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int State) /* yellow LED state, 0 = OFF, 0 != ON */ { - if (State == 0) { - /* Switch yellow LED OFF */ - SK_OUT8(IoC, B0_LED, LED_STAT_OFF); + int LedReg; + + if (CHIP_ID_YUKON_2(pAC)) { + /* different mapping on Yukon-2 */ + LedReg = B0_CTST + 1; } else { - /* Switch yellow LED ON */ - SK_OUT8(IoC, B0_LED, LED_STAT_ON); + LedReg = B0_LED; + } + + if (State == 0) { + /* Switch state LED OFF */ + SK_OUT8(IoC, LedReg, LED_STAT_OFF); + } + else { + /* Switch state LED ON */ + SK_OUT8(IoC, LedReg, LED_STAT_ON); } } /* SkGeYellowLED */ +#endif /* !SK_SLIM */ - +#if (!defined(SK_SLIM) || defined(GENESIS)) /****************************************************************************** * * SkGeXmitLED() - Modify the Operational Mode of a transmission LED. @@ -528,8 +277,8 @@ int State) /* yellow LED state, 0 = OFF, 0 != ON */ * nothing */ void SkGeXmitLED( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Led, /* offset to the LED Init Value register */ int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */ { @@ -554,17 +303,17 @@ int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */ */ SK_OUT32(IoC, Led + XMIT_LED_CNT, 0); SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF); - break; } /* - * 1000BT: The Transmit LED is driven by the PHY. + * 1000BT: the Transmit LED is driven by the PHY. * But the default LED configuration is used for * Level One and Broadcom PHYs. - * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.) - * (In this case it has to be added here. But we will see. XXX) + * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set. + * In this case it has to be added here.) */ } /* SkGeXmitLED */ +#endif /* !SK_SLIM || GENESIS */ /****************************************************************************** @@ -585,12 +334,12 @@ int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */ * 1: configuration error */ static int DoCalcAddr( -SK_AC *pAC, /* adapter context */ -SK_GEPORT *pPrt, /* port index */ -int QuSize, /* size of the queue to configure in kB */ -SK_U32 *StartVal, /* start value for address calculation */ -SK_U32 *QuStartAddr, /* start addr to calculate */ -SK_U32 *QuEndAddr) /* end address to calculate */ +SK_AC *pAC, /* Adapter Context */ +SK_GEPORT SK_FAR *pPrt, /* port index */ +int QuSize, /* size of the queue to configure in kB */ +SK_U32 SK_FAR *StartVal, /* start value for address calculation */ +SK_U32 SK_FAR *QuStartAddr,/* start addr to calculate */ +SK_U32 SK_FAR *QuEndAddr) /* end address to calculate */ { SK_U32 EndVal; SK_U32 NextStart; @@ -620,6 +369,29 @@ SK_U32 *QuEndAddr) /* end address to calculate */ return(Rtv); } /* DoCalcAddr */ +/****************************************************************************** + * + * SkGeRoundQueueSize() - Round the given queue size to the adpaters QZ units + * + * Description: + * This function rounds the given queue size in kBs to adapter specific + * queue size units (Genesis and Yukon: 8 kB, Yukon-2/EC: 1 kB). + * + * Returns: + * the rounded queue size in kB + */ +static int SkGeRoundQueueSize( +SK_AC *pAC, /* Adapter Context */ +int QueueSizeKB) /* Queue size in kB */ +{ + int QueueSizeSteps; + + QueueSizeSteps = (CHIP_ID_YUKON_2(pAC)) ? QZ_STEP_Y2 : QZ_STEP; + + return((QueueSizeKB + QueueSizeSteps - 1) & ~(QueueSizeSteps - 1)); +} /* SkGeRoundQueueSize */ + + /****************************************************************************** * * SkGeInitAssignRamToQueues() - allocate default queue sizes @@ -627,7 +399,7 @@ SK_U32 *QuEndAddr) /* end address to calculate */ * Description: * This function assigns the memory to the different queues and ports. * When DualNet is set to SK_TRUE all ports get the same amount of memory. - * Otherwise the first port gets most of the memory and all the + * Otherwise the first port gets most of the memory and all the * other ports just the required minimum. * This function can only be called when pAC->GIni.GIRamSize and * pAC->GIni.GIMacsFound have been initialized, usually this happens @@ -640,103 +412,146 @@ SK_U32 *QuEndAddr) /* end address to calculate */ */ int SkGeInitAssignRamToQueues( -SK_AC *pAC, /* Adapter context */ +SK_AC *pAC, /* Adapter Context */ int ActivePort, /* Active Port in RLMT mode */ -SK_BOOL DualNet) /* adapter context */ +SK_BOOL DualNet) /* Dual Net active */ { int i; int UsedKilobytes; /* memory already assigned */ int ActivePortKilobytes; /* memory available for active port */ - SK_GEPORT *pGePort; - - UsedKilobytes = 0; + int MinQueueSize; /* min. memory for queues */ + int TotalRamSize; /* total memory for queues */ + SK_BOOL DualPortYukon2; + SK_GEPORT *pPrt; if (ActivePort >= pAC->GIni.GIMacsFound) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n", ActivePort)); return(1); } - if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) + - ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) { + + DualPortYukon2 = (CHIP_ID_YUKON_2(pAC) && pAC->GIni.GIMacsFound == 2); + + TotalRamSize = pAC->GIni.GIRamSize; + + if (DualPortYukon2) { + TotalRamSize *= 2; + } + + MinQueueSize = SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE; + + if (MinQueueSize > pAC->GIni.GIRamSize) { + MinQueueSize = pAC->GIni.GIRamSize; + } + + if ((pAC->GIni.GIMacsFound * MinQueueSize + + RAM_QUOTA_SYNC * SK_MIN_TXQ_SIZE) > TotalRamSize) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n", - pAC->GIni.GIRamSize)); + TotalRamSize)); return(2); } - if (DualNet) { /* every port gets the same amount of memory */ - ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound; + ActivePortKilobytes = TotalRamSize / pAC->GIni.GIMacsFound; + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { - pGePort = &pAC->GIni.GP[i]; + pPrt = &pAC->GIni.GP[i]; + if (DualPortYukon2) { + ActivePortKilobytes = pAC->GIni.GIRamSize; + } /* take away the minimum memory for active queues */ - ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE); + ActivePortKilobytes -= MinQueueSize; /* receive queue gets the minimum + 80% of the rest */ - pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB(( - ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100)) + pPrt->PRxQSize = SkGeRoundQueueSize(pAC, + (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100) + SK_MIN_RXQ_SIZE; - ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE); + ActivePortKilobytes -= (pPrt->PRxQSize - SK_MIN_RXQ_SIZE); /* synchronous transmit queue */ - pGePort->PXSQSize = 0; + pPrt->PXSQSize = 0; /* asynchronous transmit queue */ - pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes + - SK_MIN_TXQ_SIZE); + pPrt->PXAQSize = SkGeRoundQueueSize(pAC, + ActivePortKilobytes + SK_MIN_TXQ_SIZE); } } - else { - /* Rlmt Mode or single link adapter */ + else { /* RLMT Mode or single link adapter */ - /* Set standby queue size defaults for all standby ports */ + UsedKilobytes = 0; + + /* set standby queue size defaults for all standby ports */ for (i = 0; i < pAC->GIni.GIMacsFound; i++) { if (i != ActivePort) { - pGePort = &pAC->GIni.GP[i]; + pPrt = &pAC->GIni.GP[i]; - pGePort->PRxQSize = SK_MIN_RXQ_SIZE; - pGePort->PXAQSize = SK_MIN_TXQ_SIZE; - pGePort->PXSQSize = 0; + if (DualPortYukon2) { + pPrt->PRxQSize = SkGeRoundQueueSize(pAC, + (int)((long)(pAC->GIni.GIRamSize - MinQueueSize) * + RAM_QUOTA_RX) / 100) + SK_MIN_RXQ_SIZE; + + pPrt->PXAQSize = pAC->GIni.GIRamSize - pPrt->PRxQSize; + } + else { + pPrt->PRxQSize = SK_MIN_RXQ_SIZE; + pPrt->PXAQSize = SK_MIN_TXQ_SIZE; + } + pPrt->PXSQSize = 0; /* Count used RAM */ - UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize; + UsedKilobytes += pPrt->PRxQSize + pPrt->PXAQSize; } } /* what's left? */ - ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes; + ActivePortKilobytes = TotalRamSize - UsedKilobytes; /* assign it to the active port */ /* first take away the minimum memory */ - ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE); - pGePort = &pAC->GIni.GP[ActivePort]; + ActivePortKilobytes -= MinQueueSize; + pPrt = &pAC->GIni.GP[ActivePort]; - /* receive queue get's the minimum + 80% of the rest */ - pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes * - (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE; + /* receive queue gets 80% of the rest */ + pPrt->PRxQSize = SkGeRoundQueueSize(pAC, + (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100); - ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE); + ActivePortKilobytes -= pPrt->PRxQSize; + + /* add the minimum memory for Rx queue */ + pPrt->PRxQSize += MinQueueSize/2; /* synchronous transmit queue */ - pGePort->PXSQSize = 0; + pPrt->PXSQSize = 0; - /* asynchronous transmit queue */ - pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) + - SK_MIN_TXQ_SIZE; + /* asynchronous transmit queue gets 20% of the rest */ + pPrt->PXAQSize = SkGeRoundQueueSize(pAC, ActivePortKilobytes) + + /* add the minimum memory for Tx queue */ + MinQueueSize/2; } -#ifdef VCPU - VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n", - pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize); -#endif /* VCPU */ + +#ifdef DEBUG + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + + pPrt = &pAC->GIni.GP[i]; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Port %d: RxQSize=%u, TxAQSize=%u, TxSQSize=%u\n", + i, pPrt->PRxQSize, pPrt->PXAQSize, pPrt->PXSQSize)); + } +#endif /* DEBUG */ return(0); } /* SkGeInitAssignRamToQueues */ + /****************************************************************************** * * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration @@ -747,12 +562,12 @@ SK_BOOL DualNet) /* adapter context */ * used ports. * This requirements must be fullfilled to have a valid configuration: * - The size of all queues must not exceed GIRamSize. - * - The queue sizes must be specified in units of 8 kB. + * - The queue sizes must be specified in units of 8 kB (Genesis & Yukon). * - The size of Rx queues of available ports must not be - * smaller than 16 kB. + * smaller than 16 kB (Genesis & Yukon) resp. 10 kB (Yukon-2). * - The size of at least one Tx queue (synch. or asynch.) - * of available ports must not be smaller than 16 kB - * when Jumbo Frames are used. + * of available ports must not be smaller than 16 kB (Genesis & Yukon), + * resp. 10 kB (Yukon-2) when Jumbo Frames are used. * - The RAM start and end addresses must not be changed * for ports which are already initialized. * Furthermore SkGeCheckQSize() defines the Start and End Addresses @@ -763,30 +578,41 @@ SK_BOOL DualNet) /* adapter context */ * 1: Queue Size Configuration invalid */ static int SkGeCheckQSize( -SK_AC *pAC, /* adapter context */ +SK_AC *pAC, /* Adapter Context */ int Port) /* port index */ { SK_GEPORT *pPrt; - int UsedMem; /* total memory used (max. found ports) */ int i; int Rtv; int Rtv2; SK_U32 StartAddr; +#ifndef SK_SLIM + int UsedMem; /* total memory used (max. found ports) */ +#endif + + Rtv = 0; + +#ifndef SK_SLIM UsedMem = 0; - Rtv = 0; + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { pPrt = &pAC->GIni.GP[i]; - if ((pPrt->PRxQSize & QZ_UNITS) != 0 || - (pPrt->PXSQSize & QZ_UNITS) != 0 || - (pPrt->PXAQSize & QZ_UNITS) != 0) { + if (CHIP_ID_YUKON_2(pAC)) { + UsedMem = 0; + } + else if (((pPrt->PRxQSize & QZ_UNITS) != 0 || + (pPrt->PXSQSize & QZ_UNITS) != 0 || + (pPrt->PXAQSize & QZ_UNITS) != 0)) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); return(1); } - if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) { +#ifndef SK_DIAG + if (i == Port && pAC->GIni.GIRamSize > SK_MIN_RXQ_SIZE && + pPrt->PRxQSize < SK_MIN_RXQ_SIZE) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG); return(1); } @@ -796,26 +622,34 @@ int Port) /* port index */ * if Jumbo Frames are used, this size has to be >= 16 kB. */ if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) || - (pAC->GIni.GIPortUsage == SK_JUMBO_LINK && - ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) || + (pPrt->PPortUsage == SK_JUMBO_LINK && + ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) || (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG); return(1); } +#endif /* !SK_DIAG */ UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize; + + if (UsedMem > pAC->GIni.GIRamSize) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); + return(1); + } } - if (UsedMem > pAC->GIni.GIRamSize) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); - return(1); - } +#endif /* !SK_SLIM */ /* Now start address calculation */ StartAddr = pAC->GIni.GIRamOffs; for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + pPrt = &pAC->GIni.GP[i]; + if (CHIP_ID_YUKON_2(pAC)) { + StartAddr = 0; + } + /* Calculate/Check values for the receive queue */ Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr, &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd); @@ -841,6 +675,7 @@ int Port) /* port index */ } /* SkGeCheckQSize */ +#ifdef GENESIS /****************************************************************************** * * SkGeInitMacArb() - Initialize the MAC Arbiter @@ -854,8 +689,8 @@ int Port) /* port index */ * nothing */ static void SkGeInitMacArb( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC) /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ { /* release local reset */ SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR); @@ -894,8 +729,8 @@ SK_IOC IoC) /* IO context */ * nothing */ static void SkGeInitPktArb( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC) /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ { /* release local reset */ SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR); @@ -911,7 +746,8 @@ SK_IOC IoC) /* IO context */ * NOTE: the packet arbiter timeout interrupt is needed for * half duplex hangup workaround */ - if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) { + if (pAC->GIni.GP[MAC_1].PPortUsage != SK_JUMBO_LINK && + pAC->GIni.GP[MAC_2].PPortUsage != SK_JUMBO_LINK) { if (pAC->GIni.GIMacsFound == 1) { SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1); } @@ -920,6 +756,7 @@ SK_IOC IoC) /* IO context */ } } } /* SkGeInitPktArb */ +#endif /* GENESIS */ /****************************************************************************** @@ -933,14 +770,11 @@ SK_IOC IoC) /* IO context */ * nothing */ static void SkGeInitMacFifo( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_U16 Word; -#ifdef VCPU - SK_U32 DWord; -#endif /* VCPU */ /* * For each FIFO: * - release local reset @@ -949,55 +783,106 @@ int Port) /* Port Index (MAC_1 + n) */ * - enable the FIFO */ - Word = GMF_RX_CTRL_DEF; - +#ifdef GENESIS if (pAC->GIni.GIGenesis) { - /* Configure Rx MAC FIFO */ + /* configure Rx MAC FIFO */ SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR); SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF); SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD); - /* Configure Tx MAC FIFO */ + /* configure Tx MAC FIFO */ SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR); SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD); - /* Enable frame flushing if jumbo frames used */ - if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + /* enable frame flushing if jumbo frames used */ + if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) { SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH); } } - else { - /* set Rx GMAC FIFO Flush Mask */ - SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK); +#endif /* GENESIS */ - if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) { +#ifdef YUKON + if (pAC->GIni.GIYukon) { + + Word = (SK_U16)GMF_RX_CTRL_DEF; + + /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */ + if (pAC->GIni.GIYukonLite /* && pAC->GIni.GIChipId == CHIP_ID_YUKON */) { Word &= ~GMF_RX_F_FL_ON; } - /* Configure Rx MAC FIFO */ + /* configure Rx GMAC FIFO */ SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR); SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word); - /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */ - SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); + Word = RX_FF_FL_DEF_MSK; - /* Configure Tx MAC FIFO */ +#ifndef SK_DIAG + if (HW_FEATURE(pAC, HWF_WA_DEV_4115)) { + /* + * Flushing must be enabled (needed for ASF see dev. #4.29), + * but the flushing mask should be disabled (see dev. #4.115) + */ + Word = 0; + } +#endif /* !SK_DIAG */ + + /* set Rx GMAC FIFO Flush Mask (after clearing reset) */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), Word); + + /* default: 0x0a -> 56 bytes on Yukon-1 and 64 bytes on Yukon-2 */ + Word = (SK_U16)RX_GMF_FL_THR_DEF; + + if (CHIP_ID_YUKON_2(pAC)) { + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC && + pAC->GIni.GIAsfEnabled) { + /* WA for dev. #4.30 (reduce to 0x08 -> 48 bytes) */ + Word -= 2; + } + } + else { + /* + * because Pause Packet Truncation in GMAC is not working + * we have to increase the Flush Threshold to 64 bytes + * in order to flush pause packets in Rx FIFO on Yukon-1 + */ + Word++; + } + + /* set Rx GMAC FIFO Flush Threshold (after clearing reset) */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), Word); + + /* configure Tx GMAC FIFO */ SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR); SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF); -#ifdef VCPU - SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord); - SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord); -#endif /* VCPU */ + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) { + /* set Rx Pause Threshold */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_LP_THR), (SK_U16)SK_ECU_LLPP); + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_UP_THR), (SK_U16)SK_ECU_ULPP); - /* set Tx GMAC FIFO Almost Empty Threshold */ -/* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */ + if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) { + /* set Tx GMAC FIFO Almost Empty Threshold */ + SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_AE_THR), + (SK_U16)SK_ECU_AE_THR); + /* disable Store & Forward mode for TX */ + SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_DIS); + } +#ifdef TEST_ONLY + else { + /* enable Store & Forward mode for TX */ + SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_ENA); + } +#endif /* TEST_ONLY */ + } } +#endif /* YUKON */ + } /* SkGeInitMacFifo */ - +#ifdef SK_LNK_SYNC_CNT /****************************************************************************** * * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting @@ -1018,8 +903,8 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ void SkGeLoadLnkSyncCnt( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_U32 CntVal) /* Counter value */ { @@ -1029,7 +914,7 @@ SK_U32 CntVal) /* Counter value */ SK_BOOL IrqPend; /* stop counter */ - SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP); + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_STOP); /* * ASIC problem: @@ -1042,6 +927,7 @@ SK_U32 CntVal) /* Counter value */ IrqPend = SK_FALSE; SK_IN32(IoC, B0_ISRC, &ISrc); SK_IN32(IoC, B0_IMSK, &OrgIMsk); + if (Port == MAC_1) { NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1; if ((ISrc & IS_LNK_SYNC_M1) != 0) { @@ -1054,6 +940,7 @@ SK_U32 CntVal) /* Counter value */ IrqPend = SK_TRUE; } } + if (!IrqPend) { SK_OUT32(IoC, B0_IMSK, NewIMsk); } @@ -1062,16 +949,19 @@ SK_U32 CntVal) /* Counter value */ SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal); /* start counter */ - SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START); + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_START); if (!IrqPend) { - /* clear the unexpected IRQ, and restore the interrupt mask */ - SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ); + /* clear the unexpected IRQ */ + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_CLR_IRQ); + + /* restore the interrupt mask */ SK_OUT32(IoC, B0_IMSK, OrgIMsk); } } /* SkGeLoadLnkSyncCnt*/ +#endif /* SK_LNK_SYNC_CNT */ - +#if defined(SK_DIAG) || defined(SK_CFG_SYNC) /****************************************************************************** * * SkGeCfgSync() - Configure synchronous bandwidth for this port. @@ -1101,8 +991,8 @@ SK_U32 CntVal) /* Counter value */ * synchronous queue is configured */ int SkGeCfgSync( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_U32 IntTime, /* Interval Timer Value in units of 8ns */ SK_U32 LimCount, /* Number of bytes to transfer during IntTime */ @@ -1160,6 +1050,7 @@ int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */ return(0); } /* SkGeCfgSync */ +#endif /* SK_DIAG || SK_CFG_SYNC*/ /****************************************************************************** @@ -1173,10 +1064,10 @@ int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */ * Returns: * nothing */ -static void DoInitRamQueue( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -int QuIoOffs, /* Queue IO Address Offset */ +void DoInitRamQueue( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int QuIoOffs, /* Queue I/O Address Offset */ SK_U32 QuStartAddr, /* Queue Start Address */ SK_U32 QuEndAddr, /* Queue End Address */ int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */ @@ -1209,8 +1100,7 @@ int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */ /* continue with SK_RX_BRAM_Q */ case SK_RX_BRAM_Q: - /* write threshold for Rx Queue */ - + /* write threshold for Rx Queue (Pause packets) */ SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal); SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal); @@ -1224,8 +1114,9 @@ int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */ * or YUKON is used ((GMAC Tx FIFO is only 1 kB) * we NEED Store & Forward of the RAM buffer. */ - if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK || - !pAC->GIni.GIGenesis) { + if (pAC->GIni.GP[MAC_1].PPortUsage == SK_JUMBO_LINK || + pAC->GIni.GP[MAC_2].PPortUsage == SK_JUMBO_LINK || + pAC->GIni.GIYukon) { /* enable Store & Forward Mode for the Tx Side */ SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD); } @@ -1253,8 +1144,8 @@ int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */ * nothing */ static void SkGeInitRamBufs( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; @@ -1262,8 +1153,8 @@ int Port) /* Port Index (MAC_1 + n) */ pPrt = &pAC->GIni.GP[Port]; - if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) { - RxQType = SK_RX_SRAM_Q; /* small Rx Queue */ + if (pPrt->PRxQSize <= SK_MIN_RXQ_SIZE) { + RxQType = SK_RX_SRAM_Q; /* small Rx Queue */ } else { RxQType = SK_RX_BRAM_Q; /* big Rx Queue */ @@ -1295,26 +1186,37 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ void SkGeInitRamIface( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC) /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ { - /* release local reset */ - SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR); + int i; + int RamBuffers; - /* configure timeout values */ - SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53); - SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53); + if (CHIP_ID_YUKON_2(pAC)) { + RamBuffers = pAC->GIni.GIMacsFound; + } + else { + RamBuffers = 1; + } + for (i = 0; i < RamBuffers; i++) { + /* release local reset */ + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_CTRL), (SK_U8)RI_RST_CLR); + + /* configure timeout values */ + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); + } } /* SkGeInitRamIface */ @@ -1329,41 +1231,91 @@ SK_IOC IoC) /* IO context */ * nothing */ static void SkGeInitBmu( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; - SK_U32 RxWm; - SK_U32 TxWm; + SK_U16 RxWm; + SK_U16 TxWm; pPrt = &pAC->GIni.GP[Port]; RxWm = SK_BMU_RX_WM; TxWm = SK_BMU_TX_WM; - if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) { - /* for better performance */ - RxWm /= 2; - TxWm /= 2; + if (CHIP_ID_YUKON_2(pAC)) { + + if (pAC->GIni.GIPciBus == SK_PEX_BUS) { + /* for better performance set it to 128 */ + RxWm = SK_BMU_RX_WM_PEX; + } + + /* Rx Queue: Release all local resets and set the watermark */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_OPER_INIT); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_FIFO_OP_ON); + + SK_OUT16(IoC, Q_ADDR(pPrt->PRxQOff, Q_WM), RxWm); + + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U && + pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) { + /* MAC Rx RAM Read is controlled by hardware */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), F_M_RX_RAM_DIS); + } + + /* + * Tx Queue: Release all local resets if the queue is used ! + * set watermark + */ + if (pPrt->PXSQSize != 0 && HW_SYNC_TX_SUPPORTED(pAC)) { + /* Yukon-EC doesn't have a synchronous Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_OPER_INIT); + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_FIFO_OP_ON); + + SK_OUT16(IoC, Q_ADDR(pPrt->PXsQOff, Q_WM), TxWm); + } + + if (pPrt->PXAQSize != 0) { + + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_OPER_INIT); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_FIFO_OP_ON); + + SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_WM), TxWm); + + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U && + pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) { + /* fix for Yukon-EC Ultra: set BMU FIFO level */ + SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_AL), SK_ECU_TXFF_LEV); + } + } } + else { + if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) { + /* for better performance */ + RxWm /= 2; + TxWm /= 2; + } - /* Rx Queue: Release all local resets and set the watermark */ - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET); - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm); + /* Rx Queue: Release all local resets and set the watermark */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm); - /* - * Tx Queue: Release all local resets if the queue is used ! - * set watermark - */ - if (pPrt->PXSQSize != 0) { - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET); - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm); - } + /* + * Tx Queue: Release all local resets if the queue is used ! + * set watermark + */ + if (pPrt->PXSQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm); + } - if (pPrt->PXAQSize != 0) { - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET); - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm); + if (pPrt->PXAQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm); + } } /* * Do NOT enable the descriptor poll timers here, because @@ -1387,20 +1339,29 @@ int Port) /* Port Index (MAC_1 + n) */ */ static SK_U32 TestStopBit( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO Context */ -int QuIoOffs) /* Queue IO Address Offset */ +SK_IOC IoC, /* I/O Context */ +int QuIoOffs) /* Queue I/O Address Offset */ { SK_U32 QuCsr; /* CSR contents */ SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); - if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) { - /* Stop Descriptor overridden by start command */ - SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP); + if (CHIP_ID_YUKON_2(pAC)) { + if ((QuCsr & (BMU_STOP | BMU_IDLE)) == 0) { + /* Stop Descriptor overridden by start command */ + SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), BMU_STOP); - SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); + SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); + } } + else { + if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) { + /* Stop Descriptor overridden by start command */ + SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP); + SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); + } + } return(QuCsr); } /* TestStopBit */ @@ -1424,13 +1385,13 @@ int QuIoOffs) /* Queue IO Address Offset */ * has to be stopped once before. * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX * - * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive. - * SK_HARD_RST Resets the MAC and the PHY. + * RstMode = SK_SOFT_RST Resets the MAC, the PHY is still alive. + * SK_HARD_RST Resets the MAC and the PHY. * * Example: * 1) A Link Down event was signaled for a port. Therefore the activity * of this port should be stopped and a hardware reset should be issued - * to enable the workaround of XMAC errata #2. But the received frames + * to enable the workaround of XMAC Errata #2. But the received frames * should not be discarded. * ... * SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST); @@ -1484,56 +1445,82 @@ int QuIoOffs) /* Queue IO Address Offset */ * SWITCH_PORT. */ void SkGeStopPort( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* I/O context */ -int Port, /* port to stop (MAC_1 + n) */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port to stop (MAC_1 + n) */ int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */ int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ { -#ifndef SK_DIAG - SK_EVPARA Para; -#endif /* !SK_DIAG */ SK_GEPORT *pPrt; - SK_U32 DWord; + SK_U32 RxCsr; SK_U32 XsCsr; SK_U32 XaCsr; SK_U64 ToutStart; + SK_U32 CsrStart; + SK_U32 CsrStop; + SK_U32 CsrIdle; + SK_U32 CsrTest; + SK_U8 rsl; /* FIFO read shadow level */ + SK_U8 rl; /* FIFO read level */ int i; int ToutCnt; pPrt = &pAC->GIni.GP[Port]; + /* set the proper values of Q_CSR register layout depending on the chip */ + if (CHIP_ID_YUKON_2(pAC)) { + CsrStart = BMU_START; + CsrStop = BMU_STOP; + CsrIdle = BMU_IDLE; + CsrTest = BMU_IDLE; + } + else { + CsrStart = CSR_START; + CsrStop = CSR_STOP; + CsrIdle = CSR_SV_IDLE; + CsrTest = CSR_SV_IDLE | CSR_STOP; + } + if ((Dir & SK_STOP_TX) != 0) { - /* disable receiver and transmitter */ - SkMacRxTxDisable(pAC, IoC, Port); + + if (!pAC->GIni.GIAsfEnabled) { + /* disable receiver and transmitter */ + SkMacRxTxDisable(pAC, IoC, Port); + } /* stop both transmit queues */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStop); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStop); /* * If the BMU is in the reset state CSR_STOP will terminate * immediately. */ - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP); - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP); ToutStart = SkOsGetTime(pAC); ToutCnt = 0; do { - /* - * Clear packet arbiter timeout to make sure - * this loop will terminate. - */ - SK_OUT16(IoC, B3_PA_CTRL, (Port == MAC_1) ? PA_CLR_TO_TX1 : - PA_CLR_TO_TX2); +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { + /* clear Tx packet arbiter timeout IRQ */ + SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ? + PA_CLR_TO_TX1 : PA_CLR_TO_TX2)); + /* + * If the transfer stucks at the XMAC the STOP command will not + * terminate if we don't flush the XMAC's transmit FIFO ! + */ + SkMacFlushTxFifo(pAC, IoC, Port); + } +#endif /* GENESIS */ - /* - * If the transfer stucks at the MAC the STOP command will not - * terminate if we don't flush the XMAC's transmit FIFO ! - */ - SkMacFlushTxFifo(pAC, IoC, Port); - - XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff); XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff); + if (HW_SYNC_TX_SUPPORTED(pAC)) { + XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff); + } + else { + XsCsr = XaCsr; + } + if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) { /* * Timeout of 1/18 second reached. @@ -1541,49 +1528,80 @@ int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ */ ToutCnt++; if (ToutCnt > 1) { - /* Might be a problem when the driver event handler - * calls StopPort again. XXX. + /* + * If BMU stop doesn't terminate, we assume that + * we have a stable state and can reset the BMU, + * the Prefetch Unit, and RAM buffer now. */ - - /* Fatal Error, Loop aborted */ - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018, - SKERR_HWI_E018MSG); -#ifndef SK_DIAG - Para.Para64 = Port; - SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); -#endif /* !SK_DIAG */ - return; + break; /* ===> leave do/while loop here */ } /* - * Cache incoherency workaround: Assume a start command + * Cache incoherency workaround: assume a start command * has been lost while sending the frame. */ ToutStart = SkOsGetTime(pAC); - if ((XsCsr & CSR_STOP) != 0) { - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START); + if ((XsCsr & CsrStop) != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStart); } - if ((XaCsr & CSR_STOP) != 0) { - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START); + + if ((XaCsr & CsrStop) != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStart); + } + + /* + * After the previous operations the X(s|a)Csr does no + * longer contain the proper values + */ + XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff); + + if (HW_SYNC_TX_SUPPORTED(pAC)) { + XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff); + } + else { + XsCsr = XaCsr; } } - /* * Because of the ASIC problem report entry from 21.08.1998 it is * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set. + * (valid for GENESIS only) */ - } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE || - (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE); + } while (((XsCsr & CsrTest) != CsrIdle || + (XaCsr & CsrTest) != CsrIdle)); - /* Reset the MAC depending on the RstMode */ - if (RstMode == SK_SOFT_RST) { - SkMacSoftRst(pAC, IoC, Port); + if (pAC->GIni.GIAsfEnabled) { + + pPrt->PState = (RstMode == SK_SOFT_RST) ? SK_PRT_STOP : + SK_PRT_RESET; } else { - SkMacHardRst(pAC, IoC, Port); + /* Reset the MAC depending on the RstMode */ + if (RstMode == SK_SOFT_RST) { + + SkMacSoftRst(pAC, IoC, Port); + } + else { +#ifdef SK_DIAG + if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_1 && + pAC->GIni.GP[MAC_2].PState == SK_PRT_RUN) { + + pAC->GIni.GP[MAC_1].PState = SK_PRT_RESET; + + /* set GPHY Control reset */ + SK_OUT8(IoC, MR_ADDR(MAC_1, GPHY_CTRL), (SK_U8)GPC_RST_SET); + } + else { + + SkMacHardRst(pAC, IoC, Port); + } +#else /* !SK_DIAG */ + SkMacHardRst(pAC, IoC, Port); +#endif /* !SK_DIAG */ + } } - /* Disable Force Sync bit and Enable Alloc bit */ + /* disable Force Sync bit and Enable Alloc bit */ SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); @@ -1592,17 +1610,35 @@ int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L); /* Perform a local reset of the port's Tx path */ + if (CHIP_ID_YUKON_2(pAC)) { + /* Reset the PCI FIFO of the async Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), + BMU_RST_SET | BMU_FIFO_RST); + + /* Reset the PCI FIFO of the sync Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), + BMU_RST_SET | BMU_FIFO_RST); + + /* Reset the Tx prefetch units */ + SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXaQOff, PREF_UNIT_CTRL_REG), + PREF_UNIT_RST_SET); + SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXsQOff, PREF_UNIT_CTRL_REG), + PREF_UNIT_RST_SET); + } + else { + /* Reset the PCI FIFO of the async Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET); + /* Reset the PCI FIFO of the sync Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET); + } - /* Reset the PCI FIFO of the async Tx queue */ - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET); - /* Reset the PCI FIFO of the sync Tx queue */ - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET); /* Reset the RAM Buffer async Tx queue */ SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET); /* Reset the RAM Buffer sync Tx queue */ SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET); /* Reset Tx MAC FIFO */ +#ifdef GENESIS if (pAC->GIni.GIGenesis) { /* Note: MFF_RST_SET does NOT reset the XMAC ! */ SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_SET); @@ -1611,56 +1647,106 @@ int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ /* Link LED is switched off by the RLMT and the Diag itself */ SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS); } - else { - /* Reset TX MAC FIFO */ - SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET); +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { + /* do the reset only if ASF is not enabled */ + if (!pAC->GIni.GIAsfEnabled) { + /* Reset Tx MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET); + } + + /* set Pause Off */ + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_PAUSE_OFF); } +#endif /* YUKON */ } if ((Dir & SK_STOP_RX) != 0) { - /* - * The RX Stop Command will not terminate if no buffers - * are queued in the RxD ring. But it will always reach - * the Idle state. Therefore we can use this feature to - * stop the transfer of received packets. - */ - /* stop the port's receive queue */ - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP); - i = 100; - do { + if (CHIP_ID_YUKON_2(pAC)) { /* - * Clear packet arbiter timeout to make sure - * this loop will terminate + * The RX Stop command will not work for Yukon-2 if the BMU does not + * reach the end of packet and since we can't make sure that we have + * incoming data, we must reset the BMU while it is not during a DMA + * transfer. Since it is possible that the RX path is still active, + * the RX RAM buffer will be stopped first, so any possible incoming + * data will not trigger a DMA. After the RAM buffer is stopped, the + * BMU is polled until any DMA in progress is ended and only then it + * will be reset. */ - SK_OUT16(IoC, B3_PA_CTRL, (Port == MAC_1) ? PA_CLR_TO_RX1 : - PA_CLR_TO_RX2); - DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff); + /* disable the RAM Buffer receive queue */ + SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_DIS_OP_MD); - /* timeout if i==0 (bug fix for #10748) */ - if (--i == 0) { - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024, - SKERR_HWI_E024MSG); - break; + i = 0xffff; + while (--i) { + SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RSL), &rsl); + SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RL), &rl); + + if (rsl == rl) { + break; + } } + /* - * because of the ASIC problem report entry from 21.08.98 - * it is required to wait until CSR_STOP is reset and - * CSR_SV_IDLE is set. + * If the Rx side is blocked, the above loop cannot terminate. + * But, if there was any traffic it should be terminated, now. + * However, stop the Rx BMU and the Prefetch Unit ! */ - } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), + BMU_RST_SET | BMU_FIFO_RST); + /* reset the Rx prefetch unit */ + SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PRxQOff, PREF_UNIT_CTRL_REG), + PREF_UNIT_RST_SET); + } + else { + /* + * The RX Stop Command will not terminate if no buffers + * are queued in the RxD ring. But it will always reach + * the Idle state. Therefore we can use this feature to + * stop the transfer of received packets. + */ + /* stop the port's receive queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CsrStop); - /* The path data transfer activity is fully stopped now */ + i = 100; + do { +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { + /* clear Rx packet arbiter timeout IRQ */ + SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ? + PA_CLR_TO_RX1 : PA_CLR_TO_RX2)); + } +#endif /* GENESIS */ - /* Perform a local reset of the port's Rx path */ + RxCsr = TestStopBit(pAC, IoC, pPrt->PRxQOff); + + /* timeout if i==0 (bug fix for #10748) */ + if (--i == 0) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024, + SKERR_HWI_E024MSG); + break; + } + /* + * Because of the ASIC problem report entry from 21.08.1998 it is + * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set. + * (valid for GENESIS only) + */ + } while ((RxCsr & CsrTest) != CsrIdle); + /* The path data transfer activity is fully stopped now */ + + /* Perform a local reset of the port's Rx path */ + /* Reset the PCI FIFO of the Rx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET); + } - /* Reset the PCI FIFO of the Rx queue */ - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET); /* Reset the RAM Buffer receive queue */ SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET); /* Reset Rx MAC FIFO */ +#ifdef GENESIS if (pAC->GIni.GIGenesis) { SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET); @@ -1668,10 +1754,27 @@ int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ /* switch Rx LED off, stop the LED counter */ SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon && !pAC->GIni.GIAsfEnabled) { /* Reset Rx MAC FIFO */ SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET); } + +#ifndef NDIS_MINIPORT_DRIVER /* temp. ifndef, remove after PM module rework*/ + /* WA for Dev. #4.169 */ + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON || + pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) && + RstMode == SK_HARD_RST) { + /* set Link Control reset */ + SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET); + + /* clear Link Control reset */ + SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR); + } +#endif /* !NDIS_MINIPORT */ +#endif /* YUKON */ } } /* SkGeStopPort */ @@ -1687,8 +1790,8 @@ int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ * nothing */ static void SkGeInit0( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC) /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ { int i; SK_GEPORT *pPrt; @@ -1697,6 +1800,7 @@ SK_IOC IoC) /* IO context */ pPrt = &pAC->GIni.GP[i]; pPrt->PState = SK_PRT_RESET; + pPrt->PPortUsage = SK_RED_LINK; pPrt->PRxQOff = QOffTab[i].RxQOff; pPrt->PXsQOff = QOffTab[i].XsQOff; pPrt->PXaQOff = QOffTab[i].XaQOff; @@ -1708,32 +1812,47 @@ SK_IOC IoC) /* IO context */ pPrt->PPrevRx = 0; pPrt->PPrevFcs = 0; pPrt->PRxLim = SK_DEF_RX_WA_LIM; - pPrt->PLinkMode = SK_LMODE_AUTOFULL; - pPrt->PLinkSpeedCap = SK_LSPEED_CAP_1000MBPS; - pPrt->PLinkSpeed = SK_LSPEED_1000MBPS; - pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_UNKNOWN; - pPrt->PLinkModeConf = SK_LMODE_AUTOSENSE; - pPrt->PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; - pPrt->PLinkBroken = SK_TRUE; /* See WA code */ - pPrt->PLinkCap = (SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL | - SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL); - pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; - pPrt->PFlowCtrlCap = SK_FLOW_MODE_SYM_OR_REM; - pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + pPrt->PLinkMode = (SK_U8)SK_LMODE_AUTOFULL; + pPrt->PLinkSpeedCap = (SK_U8)SK_LSPEED_CAP_1000MBPS; + pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_1000MBPS; + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_UNKNOWN; + pPrt->PLinkModeConf = (SK_U8)SK_LMODE_AUTOSENSE; + pPrt->PFlowCtrlMode = (SK_U8)SK_FLOW_MODE_SYM_OR_REM; + pPrt->PLinkCap = (SK_U8)(SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL | + SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL); + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN; + pPrt->PFlowCtrlCap = (SK_U8)SK_FLOW_MODE_SYM_OR_REM; + pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE; pPrt->PMSCap = 0; - pPrt->PMSMode = SK_MS_MODE_AUTO; - pPrt->PMSStatus = SK_MS_STAT_UNSET; + pPrt->PMSMode = (SK_U8)SK_MS_MODE_AUTO; + pPrt->PMSStatus = (SK_U8)SK_MS_STAT_UNSET; + pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN; pPrt->PAutoNegFail = SK_FALSE; - pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN; pPrt->PHWLinkUp = SK_FALSE; + pPrt->PLinkBroken = SK_TRUE; /* See WA code */ + pPrt->PPhyPowerState = PHY_PM_OPERATIONAL_MODE; + pPrt->PMacColThres = TX_COL_DEF; + pPrt->PMacJamLen = TX_JAM_LEN_DEF; + pPrt->PMacJamIpgVal = TX_JAM_IPG_DEF; + pPrt->PMacJamIpgData = TX_IPG_JAM_DEF; + pPrt->PMacBackOffLim = TX_BOF_LIM_DEF; + pPrt->PMacDataBlind = DATA_BLIND_DEF; + pPrt->PMacIpgData = IPG_DATA_DEF; + pPrt->PMacLimit4 = SK_FALSE; } - pAC->GIni.GIPortUsage = SK_RED_LINK; + pAC->GIni.GILedBlinkCtrl = (SK_U16)OemConfig.Value; + pAC->GIni.GIChipCap = 0; + + for (i = 0; i < 4; i++) { + pAC->GIni.HwF.Features[i]= 0x00000000; + pAC->GIni.HwF.OnMask[i] = 0x00000000; + pAC->GIni.HwF.OffMask[i] = 0x00000000; + } } /* SkGeInit0*/ #ifdef SK_PCI_RESET - /****************************************************************************** * * SkGePciReset() - Reset PCI interface @@ -1749,8 +1868,8 @@ SK_IOC IoC) /* IO context */ * 1: Power state could not be changed to 3. */ static int SkGePciReset( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC) /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ { int i; SK_U16 PmCtlSts; @@ -1792,7 +1911,20 @@ SK_IOC IoC) /* IO context */ SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd); SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls); SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1); - SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2); + + /* + * Compute the location in PCI config space of BAR2 + * relativ to the location of BAR1 + */ + if ((Bp1 & PCI_MEM_TYP_MSK) == PCI_MEM64BIT) { + /* BAR1 is 64 bits wide */ + i = 8; + } + else { + i = 4; + } + + SkPciReadCfgDWord(pAC, PCI_BASE_1ST + i, &Bp2); SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat); if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 || @@ -1807,9 +1939,116 @@ SK_IOC IoC) /* IO context */ return(0); } /* SkGePciReset */ - #endif /* SK_PCI_RESET */ + +#ifndef SK_SLIM +/****************************************************************************** + * + * SkGeSetUpSupFeatures() - Collect Feature List for HW_FEATURE Macro + * + * Description: + * This function collects the available features and required + * deviation services of the Adapter and provides these + * information in the GIHwF struct. This information is used as + * default value and may be overritten by the driver using the + * SET_HW_FEATURE_MASK() macro in its Init0 phase. + * + * Notice: + * Using the On and Off mask: Never switch on the same bit in both + * masks simultaneously. However, if doing the Off mask will win. + * + * Returns: + * nothing + */ +static void SkGeSetUpSupFeatures( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + int i; + SK_U16 Word; + + switch (pAC->GIni.GIChipId) { + case CHIP_ID_YUKON_EC: + if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_A1) { + /* A0/A1 */ + pAC->GIni.HwF.Features[HW_DEV_LIST] = + HWF_WA_DEV_42 | HWF_WA_DEV_46 | HWF_WA_DEV_43_418 | + HWF_WA_DEV_420 | HWF_WA_DEV_423 | + HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 | + HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 | + HWF_WA_DEV_4152| HWF_WA_DEV_4167; + } + else { + /* A2/A3 */ + pAC->GIni.HwF.Features[HW_DEV_LIST] = + HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 | + HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 | + HWF_WA_DEV_4152| HWF_WA_DEV_4167; + } + break; + case CHIP_ID_YUKON_FE: + pAC->GIni.HwF.Features[HW_DEV_LIST] = + HWF_WA_DEV_427 | HWF_WA_DEV_4109 | + HWF_WA_DEV_4152| HWF_WA_DEV_4167; + break; + case CHIP_ID_YUKON_XL: + switch (pAC->GIni.GIChipRev) { + case CHIP_REV_YU_XL_A0: /* still needed for Diag */ + pAC->GIni.HwF.Features[HW_DEV_LIST] = + HWF_WA_DEV_427 | HWF_WA_DEV_463 | HWF_WA_DEV_472 | + HWF_WA_DEV_479 | HWF_WA_DEV_483 | HWF_WA_DEV_4115 | + HWF_WA_DEV_4152| HWF_WA_DEV_4167; + break; + + case CHIP_REV_YU_XL_A1: + pAC->GIni.HwF.Features[HW_DEV_LIST] = + HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 | + HWF_WA_DEV_4115| HWF_WA_DEV_4152| HWF_WA_DEV_4167; + break; + + case CHIP_REV_YU_XL_A2: + pAC->GIni.HwF.Features[HW_DEV_LIST] = + HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 | + HWF_WA_DEV_4115 | HWF_WA_DEV_4167; + break; + + case CHIP_REV_YU_XL_A3: + pAC->GIni.HwF.Features[HW_DEV_LIST] = + HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 | + HWF_WA_DEV_4115; + break; + } + break; + case CHIP_ID_YUKON_EC_U: + if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) { + pAC->GIni.HwF.Features[HW_DEV_LIST] = + HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109; + } + else if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) { + pAC->GIni.HwF.Features[HW_DEV_LIST] = + HWF_WA_DEV_427 | HWF_WA_DEV_4109 | HWF_WA_DEV_4185; + + /* check for Rev. A1 */ + SK_IN16(IoC, Q_ADDR(Q_XA1, Q_WM), &Word); + + if (Word == 0) { + pAC->GIni.HwF.Features[HW_DEV_LIST] |= + HWF_WA_DEV_4185CS | HWF_WA_DEV_4200; + } + } + break; + } + + for (i = 0; i < 4; i++) { + pAC->GIni.HwF.Features[i] = + (pAC->GIni.HwF.Features[i] | pAC->GIni.HwF.OnMask[i]) & + ~pAC->GIni.HwF.OffMask[i]; + } +} /* SkGeSetUpSupFeatures */ +#endif /* !SK_SLIM */ + + /****************************************************************************** * * SkGeInit1() - Level 1 Initialization @@ -1832,75 +2071,253 @@ SK_IOC IoC) /* IO context */ * 6: HW self test failed */ static int SkGeInit1( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC) /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ { SK_U8 Byte; SK_U16 Word; - SK_U16 CtrlStat; - SK_U32 FlashAddr; + SK_U32 CtrlStat; + SK_U32 VauxAvail; + SK_U32 DWord; + SK_U32 Our1; + SK_U32 PowerDownBit; + SK_BOOL FiberType; + SK_GEPORT *pPrt; int RetVal; - int i; + int i, j; RetVal = 0; - /* save CLK_RUN bits (YUKON-Lite) */ - SK_IN16(IoC, B0_CTST, &CtrlStat); + /* save CLK_RUN & ASF_ENABLE bits (YUKON-Lite, YUKON-EC) */ + SK_IN32(IoC, B0_CTST, &CtrlStat); #ifdef SK_PCI_RESET (void)SkGePciReset(pAC, IoC); #endif /* SK_PCI_RESET */ - /* do the SW-reset */ - SK_OUT8(IoC, B0_CTST, CS_RST_SET); - /* release the SW-reset */ + /* Important: SW-reset has to be cleared here, to ensure + * the CHIP_ID can be read IO-mapped based, too - + * remember the RAP register can only be written if + * SW-reset is cleared. + */ SK_OUT8(IoC, B0_CTST, CS_RST_CLR); + /* read Chip Identification Number */ + SK_IN8(IoC, B2_CHIP_ID, &Byte); + pAC->GIni.GIChipId = Byte; + + pAC->GIni.GIAsfEnabled = SK_FALSE; + + /* ASF support only for Yukon-2 */ + if ((pAC->GIni.GIChipId >= CHIP_ID_YUKON_XL) && + (pAC->GIni.GIChipId <= CHIP_ID_YUKON_EC)) { +#ifdef SK_ASF + if ((CtrlStat & Y2_ASF_ENABLE) != 0) { + /* do the SW-reset only if ASF is not enabled */ + pAC->GIni.GIAsfEnabled = SK_TRUE; + } +#else /* !SK_ASF */ + + SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Byte); + + pAC->GIni.GIAsfRunning = Byte & Y2_ASF_RUNNING; + + /* put ASF system in reset state */ + SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_RESET); + + /* disable ASF Unit */ + SK_OUT16(IoC, B0_CTST, Y2_ASF_DISABLE); +#endif /* !SK_ASF */ + } + + if (!pAC->GIni.GIAsfEnabled) { + /* Yukon-2: required for Diag and Power Management */ + /* set the SW-reset */ + SK_OUT8(IoC, B0_CTST, CS_RST_SET); + + /* release the SW-reset */ + SK_OUT8(IoC, B0_CTST, CS_RST_CLR); + } + + /* enable Config Write */ + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + /* reset all error bits in the PCI STATUS register */ /* * Note: PCI Cfg cycles cannot be used, because they are not * available on some platforms after 'boot time'. */ - SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); + SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word); - SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); - SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS); - SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS); /* release Master Reset */ SK_OUT8(IoC, B0_CTST, CS_MRST_CLR); #ifdef CLK_RUN CtrlStat |= CS_CLK_RUN_ENA; -#endif /* CLK_RUN */ /* restore CLK_RUN bits */ - SK_OUT16(IoC, B0_CTST, CtrlStat & - (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA)); + SK_OUT16(IoC, B0_CTST, (SK_U16)(CtrlStat & + (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA))); +#endif /* CLK_RUN */ - /* read Chip Identification Number */ - SK_IN8(IoC, B2_CHIP_ID, &Byte); - pAC->GIni.GIChipId = Byte; + if ((pAC->GIni.GIChipId >= CHIP_ID_YUKON_XL) && + (pAC->GIni.GIChipId <= CHIP_ID_YUKON_FE)) { - /* read number of MACs */ - SK_IN8(IoC, B2_MAC_CFG, &Byte); - pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2; + pAC->GIni.GIYukon2 = SK_TRUE; + pAC->GIni.GIValIrqMask = Y2_IS_ALL_MSK; + pAC->GIni.GIValHwIrqMask = Y2_HWE_ALL_MSK; + + VauxAvail = Y2_VAUX_AVAIL; + + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_STATUS), &DWord); + + if ((DWord & PCI_OS_PCI_X) != 0) { +#ifndef SK_SLIM + /* this is a PCI / PCI-X bus */ + if ((DWord & PCI_OS_PCIX) != 0) { + /* this is a PCI-X bus */ + pAC->GIni.GIPciBus = SK_PCIX_BUS; + + /* PCI-X is always 64-bit wide */ + pAC->GIni.GIPciSlot64 = SK_TRUE; + + pAC->GIni.GIPciMode = (SK_U8)(PCI_OS_SPEED(DWord)); + } + else { + /* this is a conventional PCI bus */ + pAC->GIni.GIPciBus = SK_PCI_BUS; + + SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_2), &Word); + + /* check if 64-bit width is used */ + pAC->GIni.GIPciSlot64 = (SK_BOOL) + (((DWord & PCI_OS_PCI64B) != 0) && + ((Word & PCI_USEDATA64) != 0)); + + /* check if 66 MHz PCI Clock is active */ + pAC->GIni.GIPciClock66 = (SK_BOOL)((DWord & PCI_OS_PCI66M) != 0); + } +#endif /* !SK_SLIM */ + } + else { + /* this is a PEX bus */ + pAC->GIni.GIPciBus = SK_PEX_BUS; + + /* clear any PEX errors */ + SK_OUT32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), 0xffffffffUL); + + SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord); + + if ((DWord & PEX_RX_OV) != 0) { + /* Dev #4.205 occured */ + pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP; + pAC->GIni.GIValIrqMask &= ~Y2_IS_HW_ERR; + } + + SK_IN16(IoC, PCI_C(pAC, PEX_LNK_STAT), &Word); + + pAC->GIni.GIPexWidth = (SK_U8)((Word & PEX_LS_LINK_WI_MSK) >> 4); + } + /* + * Yukon-2 chips family has a different way of providing + * the number of MACs available + */ + pAC->GIni.GIMacsFound = 1; + + /* get HW Resources */ + SK_IN8(IoC, B2_Y2_HW_RES, &Byte); + + if (CHIP_ID_YUKON_2(pAC)) { + /* + * OEM config value is overwritten and should not + * be used for Yukon-2 + */ + pAC->GIni.GILedBlinkCtrl |= SK_ACT_LED_BLINK; + +#ifndef SK_SLIM + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) { + /* LED Configuration is stored in GPIO */ + SK_IN8(IoC, B2_GP_IO, &Byte); + + if (CFG_LED_MODE(Byte) == CFG_LED_LINK_MUX_P60) { + + pAC->GIni.GILedBlinkCtrl |= SK_LED_LINK_MUX_P60; + } + } +#endif /* !SK_SLIM */ + + if (CFG_LED_MODE(Byte) == CFG_LED_DUAL_ACT_LNK) { + + pAC->GIni.GILedBlinkCtrl |= SK_DUAL_LED_ACT_LNK; + } + } + + /* save HW Resources / Application Information */ + pAC->GIni.GIHwResInfo = Byte; + + if ((Byte & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { + + SK_IN8(IoC, B2_Y2_CLK_GATE, &Byte); + + if (!(Byte & Y2_STATUS_LNK2_INAC)) { + /* Link 2 activ */ + pAC->GIni.GIMacsFound++; + } + } + +#ifdef VCPU + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) { + /* temporary WA for reported number of links */ + pAC->GIni.GIMacsFound = 2; + } +#endif /* VCPU */ + + /* read Chip Revision */ + SK_IN8(IoC, B2_MAC_CFG, &Byte); + + pAC->GIni.GIChipCap = Byte & 0x0f; + } + else { + pAC->GIni.GIYukon2 = SK_FALSE; + pAC->GIni.GIValIrqMask = IS_ALL_MSK; + pAC->GIni.GIValHwIrqMask = 0; /* not activated */ + + VauxAvail = CS_VAUX_AVAIL; + + /* read number of MACs and Chip Revision */ + SK_IN8(IoC, B2_MAC_CFG, &Byte); + + pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2; + } /* get Chip Revision Number */ pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4); - /* get diff. PCI parameters */ - SK_IN16(IoC, B0_CTST, &CtrlStat); +#ifndef SK_DIAG + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL && + pAC->GIni.GIChipRev == CHIP_REV_YU_XL_A0) { + /* Yukon-2 Chip Rev. A0 */ + return(6); + } +#endif /* !SK_DIAG */ /* read the adapters RAM size */ SK_IN8(IoC, B2_E_0, &Byte); + pAC->GIni.GIGenesis = SK_FALSE; + pAC->GIni.GIYukon = SK_FALSE; + pAC->GIni.GIYukonLite = SK_FALSE; + pAC->GIni.GIVauxAvail = SK_FALSE; + +#ifdef GENESIS if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { pAC->GIni.GIGenesis = SK_TRUE; - if (Byte == 3) { + if (Byte == (SK_U8)3) { /* special case: 4 x 64k x 36, offset = 0x80000 */ pAC->GIni.GIRamSize = 1024; pAC->GIni.GIRamOffs = (SK_U32)512 * 1024; @@ -1909,161 +2326,385 @@ SK_IOC IoC) /* IO context */ pAC->GIni.GIRamSize = (int)Byte * 512; pAC->GIni.GIRamOffs = 0; } - /* all GE adapters work with 53.125 MHz host clock */ + /* all GENESIS adapters work with 53.125 MHz host clock */ pAC->GIni.GIHstClkFact = SK_FACT_53; /* set Descr. Poll Timer Init Value to 250 ms */ pAC->GIni.GIPollTimerVal = SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100; } - else { - pAC->GIni.GIGenesis = SK_FALSE; +#endif /* GENESIS */ -#ifndef VCPU - pAC->GIni.GIRamSize = (Byte == 0) ? 128 : (int)Byte * 4; -#else - pAC->GIni.GIRamSize = 128; -#endif +#ifdef YUKON + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) { + + pAC->GIni.GIYukon = SK_TRUE; + + pAC->GIni.GIRamSize = (Byte == (SK_U8)0) ? 128 : (int)Byte * 4; + +#ifndef SK_SLIM pAC->GIni.GIRamOffs = 0; - /* WA for chip Rev. A */ - pAC->GIni.GIWolOffs = (pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0; + /* WA for Yukon chip Rev. A */ + pAC->GIni.GIWolOffs = (pAC->GIni.GIChipId == CHIP_ID_YUKON && + pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0; /* get PM Capabilities of PCI config space */ - SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word); + SK_IN16(IoC, PCI_C(pAC, PCI_PM_CAP_REG), &Word); /* check if VAUX is available */ - if (((CtrlStat & CS_VAUX_AVAIL) != 0) && + if (((CtrlStat & VauxAvail) != 0) && /* check also if PME from D3cold is set */ ((Word & PCI_PME_D3C_SUP) != 0)) { /* set entry in GE init struct */ pAC->GIni.GIVauxAvail = SK_TRUE; } +#endif /* !SK_SLIM */ - /* save Flash-Address Register */ - SK_IN32(IoC, B2_FAR, &FlashAddr); + if (!CHIP_ID_YUKON_2(pAC)) { - /* test Flash-Address Register */ - SK_OUT8(IoC, B2_FAR + 3, 0xff); - SK_IN8(IoC, B2_FAR + 3, &Byte); + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) { + /* this is Rev. A1 */ + pAC->GIni.GIYukonLite = SK_TRUE; + } +#ifndef SK_SLIM + else { + /* save Flash-Address Register */ + SK_IN32(IoC, B2_FAR, &DWord); - pAC->GIni.GIYukonLite = (SK_BOOL)(Byte != 0); + /* test Flash-Address Register */ + SK_OUT8(IoC, B2_FAR + 3, 0xff); + SK_IN8(IoC, B2_FAR + 3, &Byte); - /* restore Flash-Address Register */ - SK_OUT32(IoC, B2_FAR, FlashAddr); + if (Byte != 0) { + /* this is Rev. A0 */ + pAC->GIni.GIYukonLite = SK_TRUE; - for (i = 0; i < pAC->GIni.GIMacsFound; i++) { - /* set GMAC Link Control reset */ - SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET); - - /* clear GMAC Link Control reset */ - SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR); + /* restore Flash-Address Register */ + SK_OUT32(IoC, B2_FAR, DWord); + } + } +#endif /* !SK_SLIM */ } - /* all YU chips work with 78.125 MHz host clock */ - pAC->GIni.GIHstClkFact = SK_FACT_78; + else { + /* Check for CLS = 0 (dev. #4.55) */ + if (pAC->GIni.GIPciBus != SK_PEX_BUS) { + /* PCI and PCI-X */ + SK_IN8(IoC, PCI_C(pAC, PCI_CACHE_LSZ), &Byte); - pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */ + if (Byte == 0) { + /* set CLS to 2 if configured to 0 */ + SK_OUT8(IoC, PCI_C(pAC, PCI_CACHE_LSZ), 2); + } + + if (pAC->GIni.GIPciBus == SK_PCIX_BUS) { + /* set Cache Line Size opt. */ + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord); + DWord |= PCI_CLS_OPT; + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord); + } + } + } + + /* switch power to VCC (WA for VAUX problem) */ + SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA | + PC_VAUX_OFF | PC_VCC_ON)); + + Byte = 0; + + if (CHIP_ID_YUKON_2(pAC)) { + switch (pAC->GIni.GIChipId) { + /* PEX adapters work with different host clock */ + case CHIP_ID_YUKON_EC: + case CHIP_ID_YUKON_EC_U: + /* Yukon-EC works with 125 MHz host clock */ + pAC->GIni.GIHstClkFact = SK_FACT_125; + break; + case CHIP_ID_YUKON_FE: + /* Yukon-FE works with 100 MHz host clock */ + pAC->GIni.GIHstClkFact = SK_FACT_100; + break; + case CHIP_ID_YUKON_XL: + /* all Yukon-2 adapters work with 156 MHz host clock */ + pAC->GIni.GIHstClkFact = 2 * SK_FACT_78; + + if (pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) { + /* enable bits are inverted */ + Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); + } + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E006, + SKERR_HWI_E006MSG); + } + + pAC->GIni.GIPollTimerVal = + SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100; + + /* set power down bit */ + PowerDownBit = PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; + + /* disable Core Clock Division, set Clock Select to 0 (Yukon-2) */ + SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); + + /* enable MAC/PHY, PCI and Core Clock for both Links */ + SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte); + } + else { + /* YUKON adapters work with 78 MHz host clock */ + pAC->GIni.GIHstClkFact = SK_FACT_78; + + pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */ + + /* read the Interrupt source */ + SK_IN32(IoC, B0_ISRC, &DWord); + + if ((DWord & IS_HW_ERR) != 0) { + /* read the HW Error Interrupt source */ + SK_IN32(IoC, B0_HWE_ISRC, &DWord); + + if ((DWord & IS_IRQ_SENSOR) != 0) { + /* disable HW Error IRQ */ + pAC->GIni.GIValIrqMask &= ~IS_HW_ERR; + } + } + /* set power down bit */ + PowerDownBit = PCI_PHY_COMA; + } + + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Our1); + + Our1 &= ~PowerDownBit; + + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL && + pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) { + /* deassert Low Power for 1st PHY */ + Our1 |= PCI_Y2_PHY1_COMA; + + if (pAC->GIni.GIMacsFound > 1) { + /* deassert Low Power for 2nd PHY */ + Our1 |= PCI_Y2_PHY2_COMA; + } + } + else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) { + /* enable HW WOL */ + SK_OUT16(IoC, B0_CTST, (SK_U16)Y2_HW_WOL_ON); + + /* enable all clocks */ + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_3), 0); + + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord); + + DWord &= P_ASPM_CONTROL_MSK; + /* set all bits to 0 except bits 15..12 */ + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord); + + /* set to default value */ + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), 0); + } + + /* release PHY from PowerDown/COMA Mode */ + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), Our1); + + if (!pAC->GIni.GIAsfEnabled) { + + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + /* set Link Control reset */ + SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET); + + /* clear Link Control reset */ + SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR); + } + } + } +#endif /* YUKON */ + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + +#ifndef SK_SLIM + if (!CHIP_ID_YUKON_2(pAC)) { + /* this is a conventional PCI bus */ + pAC->GIni.GIPciBus = SK_PCI_BUS; + + /* check if 64-bit PCI Slot is present */ + pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0); + + /* check if 66 MHz PCI Clock is active */ + pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0); } - /* check if 64-bit PCI Slot is present */ - pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0); - - /* check if 66 MHz PCI Clock is active */ - pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0); - /* read PCI HW Revision Id. */ - SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte); + SK_IN8(IoC, PCI_C(pAC, PCI_REV_ID), &Byte); pAC->GIni.GIPciHwRev = Byte; + /* read connector type */ + SK_IN8(IoC, B2_CONN_TYP, &pAC->GIni.GIConTyp); +#endif /* !SK_SLIM */ + /* read the PMD type */ SK_IN8(IoC, B2_PMD_TYP, &Byte); - pAC->GIni.GICopperType = (SK_U8)(Byte == 'T'); - /* read the PHY type */ + pAC->GIni.GIPmdTyp = Byte; + + FiberType = (Byte == 'L' || Byte == 'S' || Byte == 'P'); + + pAC->GIni.GICopperType = (SK_BOOL)(Byte == 'T' || Byte == '1' || + (pAC->GIni.GIYukon2 && !FiberType)); + + /* read the PHY type (Yukon and Genesis) */ SK_IN8(IoC, B2_E_1, &Byte); Byte &= 0x0f; /* the PHY type is stored in the lower nibble */ for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + pPrt = &pAC->GIni.GP[i]; + + /* get the MAC addresses */ + for (j = 0; j < 3; j++) { + SK_IN16(IoC, B2_MAC_1 + i * 8 + j * 2, &pPrt->PMacAddr[j]); + } + +#ifdef GENESIS if (pAC->GIni.GIGenesis) { switch (Byte) { case SK_PHY_XMAC: - pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC; + pPrt->PhyAddr = PHY_ADDR_XMAC; break; case SK_PHY_BCOM: - pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM; - pAC->GIni.GP[i].PMSCap = - SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE; + pPrt->PhyAddr = PHY_ADDR_BCOM; + pPrt->PMSCap = (SK_U8)(SK_MS_CAP_AUTO | + SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE); break; #ifdef OTHER_PHY case SK_PHY_LONE: - pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE; + pPrt->PhyAddr = PHY_ADDR_LONE; break; case SK_PHY_NAT: - pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT; + pPrt->PhyAddr = PHY_ADDR_NAT; break; #endif /* OTHER_PHY */ default: /* ERROR: unexpected PHY type detected */ RetVal = 5; - break; } } - else { - if (Byte == 0) { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { + + if (((Byte < (SK_U8)SK_PHY_MARV_COPPER) || pAC->GIni.GIYukon2) && + !FiberType) { /* if this field is not initialized */ - Byte = SK_PHY_MARV_COPPER; + Byte = (SK_U8)SK_PHY_MARV_COPPER; + pAC->GIni.GICopperType = SK_TRUE; } - pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV; + + pPrt->PhyAddr = PHY_ADDR_MARV; if (pAC->GIni.GICopperType) { - pAC->GIni.GP[i].PLinkSpeedCap = SK_LSPEED_CAP_AUTO | - SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS | - SK_LSPEED_CAP_1000MBPS; - pAC->GIni.GP[i].PLinkSpeed = SK_LSPEED_AUTO; - pAC->GIni.GP[i].PMSCap = - SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE; + + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE || + (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC && + pAC->GIni.GIChipCap == 2)) { + + pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_100MBPS | + SK_LSPEED_CAP_10MBPS); + + pAC->GIni.GIRamSize = 4; + } + else { + pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_1000MBPS | + SK_LSPEED_CAP_100MBPS | SK_LSPEED_CAP_10MBPS | + SK_LSPEED_CAP_AUTO); + } + + pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_AUTO; + + pPrt->PMSCap = (SK_U8)(SK_MS_CAP_AUTO | + SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE); } else { - Byte = SK_PHY_MARV_FIBER; + Byte = (SK_U8)SK_PHY_MARV_FIBER; } } - pAC->GIni.GP[i].PhyType = Byte; + /* clear TWSI IRQ */ + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); + +#endif /* YUKON */ + + pPrt->PhyType = (int)Byte; SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, - ("PHY type: %d PHY addr: %04x\n", Byte, - pAC->GIni.GP[i].PhyAddr)); + ("PHY type: %d PHY addr: %04x\n", + Byte, pPrt->PhyAddr)); } - /* get Mac Type & set function pointers dependent on */ + /* get MAC Type & set function pointers dependent on */ +#ifdef GENESIS if (pAC->GIni.GIGenesis) { + pAC->GIni.GIMacType = SK_MAC_XMAC; pAC->GIni.GIFunc.pFnMacUpdateStats = SkXmUpdateStats; pAC->GIni.GIFunc.pFnMacStatistic = SkXmMacStatistic; pAC->GIni.GIFunc.pFnMacResetCounter = SkXmResetCounter; pAC->GIni.GIFunc.pFnMacOverflow = SkXmOverflowStatus; +#ifdef SK_DIAG + pAC->GIni.GIFunc.pFnMacPhyRead = SkXmPhyRead; + pAC->GIni.GIFunc.pFnMacPhyWrite = SkXmPhyWrite; +#else /* SK_DIAG */ + pAC->GIni.GIFunc.pSkGeSirqIsr = SkGeYuSirqIsr; +#endif /* !SK_DIAG */ } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { + +#ifndef SK_SLIM pAC->GIni.GIMacType = SK_MAC_GMAC; pAC->GIni.GIFunc.pFnMacUpdateStats = SkGmUpdateStats; pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic; pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter; pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus; +#endif /* !SK_SLIM */ + +#ifdef SK_DIAG + pAC->GIni.GIFunc.pFnMacPhyRead = SkGmPhyRead; + pAC->GIni.GIFunc.pFnMacPhyWrite = SkGmPhyWrite; +#else /* SK_DIAG */ + if (CHIP_ID_YUKON_2(pAC)) { + pAC->GIni.GIFunc.pSkGeSirqIsr = SkYuk2SirqIsr; + } + else { + pAC->GIni.GIFunc.pSkGeSirqIsr = SkGeYuSirqIsr; + } +#endif /* !SK_DIAG */ #ifdef SPECIAL_HANDLING if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { /* check HW self test result */ SK_IN8(IoC, B2_E_3, &Byte); - if ((Byte & B2_E3_RES_MASK) != 0) { + if (Byte & B2_E3_RES_MASK) { RetVal = 6; } } #endif } +#endif /* YUKON */ + +#ifndef SK_SLIM + + SkGeSetUpSupFeatures(pAC, IoC); + +#endif /* !SK_SLIM */ + return(RetVal); } /* SkGeInit1 */ @@ -2084,10 +2725,18 @@ SK_IOC IoC) /* IO context */ * nothing */ static void SkGeInit2( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC) /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ { +#ifdef YUKON + SK_U16 Word; +#if (!defined(SK_SLIM) && !defined(SK_DIAG)) + SK_EVPARA Para; +#endif /* !SK_SLIM && !SK_DIAG */ +#endif /* YUKON */ +#ifdef GENESIS SK_U32 DWord; +#endif /* GENESIS */ int i; /* start the Descriptor Poll Timer */ @@ -2101,6 +2750,7 @@ SK_IOC IoC) /* IO context */ SK_OUT8(IoC, B28_DPT_CTRL, DPT_START); } +#ifdef GENESIS if (pAC->GIni.GIGenesis) { /* start the Blink Source Counter */ DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100; @@ -2116,10 +2766,14 @@ SK_IOC IoC) /* IO context */ SkGeInitPktArb(pAC, IoC); } - else { +#endif /* GENESIS */ + +#ifdef xSK_DIAG + if (pAC->GIni.GIYukon) { /* start Time Stamp Timer */ SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START); } +#endif /* SK_DIAG */ /* enable the Tx Arbiters */ for (i = 0; i < pAC->GIni.GIMacsFound; i++) { @@ -2129,8 +2783,62 @@ SK_IOC IoC) /* IO context */ /* enable the RAM Interface Arbiter */ SkGeInitRamIface(pAC, IoC); +#ifdef YUKON + if (CHIP_ID_YUKON_2(pAC)) { + + if (pAC->GIni.GIPciBus == SK_PEX_BUS) { + + SK_IN16(IoC, PCI_C(pAC, PEX_DEV_CTRL), &Word); + + /* change Max. Read Request Size to 2048 bytes */ + Word &= ~PEX_DC_MAX_RRS_MSK; + Word |= PEX_DC_MAX_RD_RQ_SIZE(4); + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + + SK_OUT16(IoC, PCI_C(pAC, PEX_DEV_CTRL), Word); + +#ifdef REPLAY_TIMER + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) { + /* PEX Ack Reply Timeout to 40 us */ + SK_OUT16(IoC, PCI_C(pAC, PEX_ACK_RPLY_TOX1), 0x2710); + } +#endif + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + +#if (!defined(SK_SLIM) && !defined(SK_DIAG)) + SK_IN16(IoC, PCI_C(pAC, PEX_LNK_CAP), &Word); + + Word = (Word & PEX_CAP_MAX_WI_MSK) >> 4; + + /* compare PEX Negotiated Link Width against max. capabil */ + if (pAC->GIni.GIPexWidth != (SK_U8)Word) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PEX negotiated Link width is: %d, exp.: %d\n", + pAC->GIni.GIPexWidth, Word)); + +#ifndef NDIS_MINIPORT_DRIVER + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E026, + SKERR_HWI_E026MSG); +#endif + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PEX_LINK_WIDTH, Para); + } +#endif /* !SK_SLIM && !SK_DIAG */ + } + + /* + * Writing the HW Error Mask Reg. will not generate an IRQ + * as long as the B0_IMSK is not set by the driver. + */ + SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask); + } +#endif /* YUKON */ } /* SkGeInit2 */ + /****************************************************************************** * * SkGeInit() - Initialize the GE Adapter with the specified level. @@ -2152,7 +2860,7 @@ SK_IOC IoC) /* IO context */ * if Number of MACs > SK_MAX_MACS * * After returning from Level 0 the adapter - * may be accessed with IO operations. + * may be accessed with I/O operations. * * Level 2: start the Blink Source Counter * @@ -2161,14 +2869,14 @@ SK_IOC IoC) /* IO context */ * 1: Number of MACs exceeds SK_MAX_MACS (after level 1) * 2: Adapter not present or not accessible * 3: Illegal initialization level - * 4: Initialization Level 1 Call missing + * 4: Initialization level 1 call missing * 5: Unexpected PHY type detected * 6: HW self test failed */ int SkGeInit( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -int Level) /* initialization level */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Level) /* Initialization Level */ { int RetVal; /* return value */ SK_U32 DWord; @@ -2192,20 +2900,22 @@ int Level) /* initialization level */ } /* check if the adapter seems to be accessible */ - SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L); + SK_OUT32(IoC, B2_IRQM_INI, SK_TEST_VAL); SK_IN32(IoC, B2_IRQM_INI, &DWord); SK_OUT32(IoC, B2_IRQM_INI, 0L); - if (DWord != 0x11335577L) { + if (DWord != SK_TEST_VAL) { RetVal = 2; break; } +#ifdef DEBUG /* check if the number of GIMacsFound matches SK_MAX_MACS */ if (pAC->GIni.GIMacsFound > SK_MAX_MACS) { RetVal = 1; break; } +#endif /* DEBUG */ /* Level 1 successfully passed */ pAC->GIni.GILevel = SK_INIT_IO; @@ -2220,6 +2930,7 @@ int Level) /* initialization level */ RetVal = 4; break; } + SkGeInit2(pAC, IoC); /* Level 2 successfully passed */ @@ -2248,39 +2959,83 @@ int Level) /* initialization level */ * nothing */ void SkGeDeInit( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC) /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ { int i; SK_U16 Word; -#ifndef VCPU +#ifdef SK_PHY_LP_MODE_DEEP_SLEEP + SK_U16 PmCtlSts; +#endif + +#if (!defined(SK_SLIM) && !defined(VCPU)) /* ensure I2C is ready */ SkI2cWaitIrq(pAC, IoC); #endif - /* stop all current transfer activity */ - for (i = 0; i < pAC->GIni.GIMacsFound; i++) { - if (pAC->GIni.GP[i].PState != SK_PRT_STOP && - pAC->GIni.GP[i].PState != SK_PRT_RESET) { +#ifdef SK_PHY_LP_MODE_DEEP_SLEEP + /* + * for power saving purposes within mobile environments + * we set the PHY to coma mode. + */ +#ifdef XXX + if (pAC->GIni.GIVauxAvail) { + /* switch power to VAUX */ + SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA | + PC_VAUX_ON | PC_VCC_OFF)); + } +#endif /* XXX */ - SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST); + if (CHIP_ID_YUKON_2(pAC) && /* pAC->GIni.GIMacsFound == 1 && */ + !pAC->GIni.GIAsfEnabled +#ifdef XXX + || (pAC->GIni.GIYukonLite && pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) +#endif /* XXX */ + ) { + + /* flag for SkGmEnterLowPowerMode() that the call was from here */ + pAC->GIni.GILevel = SK_INIT_IO; + + /* for all ports switch PHY to coma mode */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + + (void)SkGmEnterLowPowerMode(pAC, IoC, i, PHY_PM_DEEP_SLEEP); + } + } +#else /* !SK_PHY_LP_MODE_DEEP_SLEEP */ + + if (!pAC->GIni.GIAsfEnabled) { + /* stop all current transfer activity */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + if (pAC->GIni.GP[i].PState != SK_PRT_STOP && + pAC->GIni.GP[i].PState != SK_PRT_RESET) { + + SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST); + } } } - /* Reset all bits in the PCI STATUS register */ + /* reset all bits in the PCI STATUS register */ /* * Note: PCI Cfg cycles cannot be used, because they are not * available on some platforms after 'boot time'. */ - SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); + SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word); SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); - SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS); + + SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS); + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); - /* do the reset, all LEDs are switched off now */ - SK_OUT8(IoC, B0_CTST, CS_RST_SET); + if (!pAC->GIni.GIAsfEnabled) { + /* set the SW-reset */ + SK_OUT8(IoC, B0_CTST, CS_RST_SET); + } +#endif /* !SK_PHY_LP_MODE_DEEP_SLEEP */ + + pAC->GIni.GILevel = SK_INIT_DATA; } /* SkGeDeInit */ @@ -2313,8 +3068,8 @@ SK_IOC IoC) /* IO context */ * 2: The port has to be stopped before it can be initialized again. */ int SkGeInitPort( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port to configure */ { SK_GEPORT *pPrt; @@ -2326,17 +3081,18 @@ int Port) /* Port to configure */ return(1); } - if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) { + if (pPrt->PState >= SK_PRT_INIT) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG); return(2); } /* configuration ok, initialize the Port now */ +#ifdef GENESIS if (pAC->GIni.GIGenesis) { /* initialize Rx, Tx and Link LED */ /* - * If 1000BT Phy needs LED initialization than swap + * If 1000BT PHY needs LED initialization than swap * LED and XMAC initialization order */ SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA); @@ -2345,10 +3101,14 @@ int Port) /* Port to configure */ SkXmInitMac(pAC, IoC, Port); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { SkGmInitMac(pAC, IoC, Port); } +#endif /* YUKON */ /* do NOT initialize the Link Sync Counter */ @@ -2369,4 +3129,214 @@ int Port) /* Port to configure */ return(0); } /* SkGeInitPort */ -#endif /* CONFIG_SK98 */ + +#if (defined(YUK2) && !defined(SK_SLIM)) +/****************************************************************************** + * + * SkGeRamWrite() - Writes One quadword to RAM + * + * Returns: + * 0 + */ +static void SkGeRamWrite( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Addr, /* Address to be written to (in quadwords) */ +SK_U32 LowDword, /* Lower Dword to be written */ +SK_U32 HighDword, /* Upper Dword to be written */ +int Port) /* Select RAM buffer (Yukon-2 has 2 RAM buffers) */ +{ + SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_ADDR), Addr); + + /* Write Access is initiated by writing the upper Dword */ + SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_DATA_LO), LowDword); + SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_DATA_HI), HighDword); +} + +/****************************************************************************** + * + * SkYuk2RestartRxBmu() - Restart Receive BMU on Yukon-2 + * + * return: + * 0 o.k. + * 1 timeout + */ +int SkYuk2RestartRxBmu( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 Word; + SK_U16 MacCtrl; + SK_U16 RxCtrl; + SK_U16 FlushMask; + SK_U16 FlushTrsh; + SK_U32 RamAdr; + SK_U32 StartTime; + SK_U32 CurrTime; + SK_U32 Delta; + SK_U32 TimeOut; + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Rtv; + SK_U16 WordBuffer[4]; /* Buffer to handle MAC address */ + + Rtv = 0; + + pPrt = &pAC->GIni.GP[Port]; + +/* + 1. save Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold + 2. save GMAC Rx Control Register + 3. re-initialize MAC Rx FIFO, Rx RAM Buffer Queue, PCI Rx FIFO, + Rx BMU and Rx Prefetch Unit of the link. + 4. set Rx MAC FIFO Flush Mask to 0xffff + set Rx MAC FIFO Flush Threshold to a high value, e.g. 0x20 + 5. set GMAC to loopback mode and switch GMAC back to Rx/Tx enable + 6. clear Rx/Tx Frame Complete IRQ in Rx/T MAC FIFO Control Register + 7. send one packet with a size of 64bytes (size below flush threshold) + from TXA RAM Buffer Queue to set the rx_sop flop: + - set TxAQ Write Pointer to (packet size in qwords + 2) + - set TxAQ Level to (packet size in qwords + 2) + - write Internal Status Word 1 and 2 to TxAQ RAM Buffer Queue QWord 0,1 + according to figure 61 on page 330 of Yukon-2 Spec. + - write MAC header with Destination Address = own MAC address to + TxAQ RAM Buffer Queue QWords 2 and 3 + - set TxAQ Packet Counter to 1 -> packet is transmitted immediately + 8. poll GMAC IRQ Source Register for IRQ Rx/Tx Frame Complete + 9. restore GMAC Rx Control Register +10. restore Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold +11. set GMAC back to GMII mode +*/ + + /* save Rx GMAC FIFO Flush Mask */ + SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), &FlushMask); + + /* save Rx GMAC FIFO Flush Threshold */ + SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), &FlushTrsh); + + /* save GMAC Rx Control Register */ + GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl); + + /* configure the GMAC FIFOs */ + SkGeInitMacFifo(pAC, IoC, Port); + + SkGeInitRamBufs(pAC, IoC, Port); + + SkGeInitBmu(pAC, IoC, Port); + + /* configure Rx GMAC FIFO */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), GMF_RX_CTRL_DEF); + + /* set Rx GMAC FIFO Flush Mask */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), 0xffff); + + /* set Rx GMAC FIFO Flush Threshold */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), 0x20); + + /* set to promiscuous mode */ + Word = RxCtrl & ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); + + /* set GMAC Rx Control Register */ + GM_OUT16(IoC, Port, GM_RX_CTRL, Word); + + /* get General Purpose Control */ + GM_IN16(IoC, Port, GM_GP_CTRL, &MacCtrl); + + /* enable MAC Loopback Mode*/ + GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl | GM_GPCR_LOOP_ENA); + + /* enable MAC Loopback Mode and Rx/Tx */ + GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl | GM_GPCR_LOOP_ENA | + GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); + + /* clear GMAC IRQ Rx Frame Complete */ + SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FC); + + /* clear GMAC IRQ Tx Frame Complete */ + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_CLI_TX_FC); + + /* send one packet with a size of 64bytes from RAM buffer*/ + + RamAdr = pPrt->PXaQRamStart / 8; + + SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_WP), RamAdr + 10); + + SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_LEV), 10); + + /* write 1st status quad word (packet end address in RAM, packet length */ + SkGeRamWrite(pAC, IoC, RamAdr, (RamAdr + 9) << 16, 64, Port); + + /* write 2nd status quad word */ + SkGeRamWrite(pAC, IoC, RamAdr + 1, 0, 0, Port); + + WordBuffer[0] = pPrt->PMacAddr[0]; + WordBuffer[1] = pPrt->PMacAddr[1]; + WordBuffer[2] = pPrt->PMacAddr[2]; + WordBuffer[3] = pPrt->PMacAddr[0]; + + /* write DA to MAC header */ + SkGeRamWrite(pAC, IoC, RamAdr + 2, *(SK_U32 *)&WordBuffer[0], + *(SK_U32 *)&WordBuffer[2], Port); + + WordBuffer[0] = pPrt->PMacAddr[1]; + WordBuffer[1] = pPrt->PMacAddr[2]; + WordBuffer[2] = 0x3200; /* len / type field (big endian) */ + WordBuffer[3] = 0x00; + + SkGeRamWrite(pAC, IoC, RamAdr + 3, *(SK_U32 *)&WordBuffer[0], + *(SK_U32 *)&WordBuffer[2], Port); + + SkGeRamWrite(pAC, IoC, RamAdr + 4, 0x4c56524d, /* "MRVL" */ + 0x00464d2d, Port); /* "-MF" */ + + SkGeRamWrite(pAC, IoC, RamAdr + 5, 0x00000000, 0x00000000, Port); + SkGeRamWrite(pAC, IoC, RamAdr + 6, 0x00000000, 0x00000000, Port); + SkGeRamWrite(pAC, IoC, RamAdr + 7, 0x00000000, 0x00000000, Port); + SkGeRamWrite(pAC, IoC, RamAdr + 8, 0x00000000, 0x00000000, Port); + SkGeRamWrite(pAC, IoC, RamAdr + 9, 0x00000000, 0x00000000, Port); + + SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_PC), 1); + + SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime); + + /* set timeout to 10 ms */ + TimeOut = HW_MS_TO_TICKS(pAC, 10); + + do { + SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime); + + if (CurrTime >= StartTime) { + Delta = CurrTime - StartTime; + } + else { + Delta = CurrTime + ~StartTime + 1; + } + + if (Delta > TimeOut) { + Rtv = 1; + break; + } + + /* read the GMAC Interrupt source register */ + SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &Word); + + } while ((Word & (GM_IS_TX_COMPL | GM_IS_RX_COMPL)) != + (GM_IS_TX_COMPL | GM_IS_RX_COMPL)); + + /* disable MAC Loopback Mode and Rx/Tx */ + GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl); + + /* restore GMAC Rx Control Register */ + GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl); + + /* restore Rx GMAC FIFO Flush Mask */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), FlushMask); + + /* restore Rx GMAC FIFO Flush Threshold */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), FlushTrsh); + + return(Rtv); + +} /* SkYuk2RestartRxBmu */ +#endif /* YUK2 && !SK_SLIM */ +#endif diff --git a/drivers/sk98lin/skgemib.c b/drivers/sk98lin/skgemib.c index 4a9e9e6..b5cb834 100644 --- a/drivers/sk98lin/skgemib.c +++ b/drivers/sk98lin/skgemib.c @@ -2,15 +2,17 @@ * * Name: skgemib.c * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.7 $ - * Date: $Date: 2002/12/16 09:04:34 $ + * Version: $Revision: 2.9 $ + * Date: $Date: 2005/12/21 09:49:48 $ * Purpose: Private Network Management Interface Management Database * ****************************************************************************/ /****************************************************************************** * - * (C)Copyright 2002 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,40 +20,11 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. + * /LICENSE * ******************************************************************************/ - -/***************************************************************************** - * - * History: - * - * $Log: skgemib.c,v $ - * Revision 1.7 2002/12/16 09:04:34 tschilli - * Code for VCT handling added. - * - * Revision 1.6 2002/08/09 15:40:21 rwahl - * Editorial change (renamed ConfSpeedCap). - * - * Revision 1.5 2002/08/09 11:05:34 rwahl - * Added oid handling for link speed cap. - * - * Revision 1.4 2002/08/09 09:40:27 rwahl - * Added support for NDIS OID_PNP_xxx. - * - * Revision 1.3 2002/07/17 19:39:54 rwahl - * Added handler for OID_SKGE_SPEED_MODE & OID_SKGE_SPEED_STATUS. - * - * Revision 1.2 2002/05/22 08:59:00 rwahl - * - static functions only for release build. - * - Source file must be included. - * - * Revision 1.1 2002/05/22 08:12:42 rwahl - * Initial version. - * - ****************************************************************************/ - #include - + #ifdef CONFIG_SK98 /* @@ -104,7 +77,19 @@ PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, PNMI_STATIC int PowerManagement(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance, unsigned int TableIndex, SK_U32 NetIndex); -#endif +#endif /* SK_POWER_MGMT */ + +#ifdef SK_DIAG_SUPPORT +PNMI_STATIC int DiagActions(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +#endif /* SK_DIAG_SUPPORT */ + +#ifdef SK_ASF +PNMI_STATIC int Asf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +#endif /* SK_ASF */ /* defines *******************************************************************/ @@ -270,6 +255,190 @@ PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = { 0, SK_PNMI_RW, PowerManagement, 0}, #endif /* SK_POWER_MGMT */ +#ifdef SK_DIAG_SUPPORT + {OID_SKGE_DIAG_MODE, + 0, + 0, + 0, + SK_PNMI_RW, DiagActions, 0}, +#endif /* SK_DIAG_SUPPORT */ +#ifdef SK_ASF + {OID_SKGE_ASF, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_STORE_CONFIG, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_ENA, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_RETRANS, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_RETRANS_INT, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_HB_ENA, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_HB_INT, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_WD_ENA, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_WD_TIME, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_IP_SOURCE, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_MAC_SOURCE, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_IP_DEST, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_MAC_DEST, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_COMMUNITY_NAME, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_RSP_ENA, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_RETRANS_COUNT_MIN, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_RETRANS_COUNT_MAX, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_RETRANS_INT_MIN, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_RETRANS_INT_MAX, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_HB_INT_MIN, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_HB_INT_MAX, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_WD_TIME_MIN, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_WD_TIME_MAX, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_HB_CAP, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_WD_TIMER_RES, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_GUID, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_KEY_OP, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_KEY_ADM, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_KEY_GEN, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_CAP, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_PAR_1, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_OVERALL_OID, + 0, + 0, + 0, + SK_PNMI_RW, Asf, 0}, + {OID_SKGE_ASF_FWVER_OID, + 0, + 0, + 0, + SK_PNMI_RO, Asf, 0}, + {OID_SKGE_ASF_ACPI_OID, + 0, + 0, + 0, + SK_PNMI_RO, Asf, 0}, + {OID_SKGE_ASF_SMBUS_OID, + 0, + 0, + 0, + SK_PNMI_RO, Asf, 0}, +#endif /* SK_ASF */ {OID_SKGE_MDB_VERSION, 1, 0, @@ -320,7 +489,7 @@ PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = { sizeof(SK_PNMI_VPD), SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAction), SK_PNMI_RW, Vpd, 0}, - {OID_SKGE_PORT_NUMBER, + {OID_SKGE_PORT_NUMBER, 1, 0, SK_PNMI_MAI_OFF(PortNumber), @@ -340,6 +509,16 @@ PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = { 0, SK_PNMI_MAI_OFF(DriverVersion), SK_PNMI_RO, General, 0}, + {OID_SKGE_DRIVER_RELDATE, + 1, + 0, + SK_PNMI_MAI_OFF(DriverReleaseDate), + SK_PNMI_RO, General, 0}, + {OID_SKGE_DRIVER_FILENAME, + 1, + 0, + SK_PNMI_MAI_OFF(DriverFileName), + SK_PNMI_RO, General, 0}, {OID_SKGE_HW_DESCR, 1, 0, @@ -355,6 +534,21 @@ PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = { 0, SK_PNMI_MAI_OFF(Chipset), SK_PNMI_RO, General, 0}, + {OID_SKGE_CHIPID, + 1, + 0, + SK_PNMI_MAI_OFF(ChipId), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RAMSIZE, + 1, + 0, + SK_PNMI_MAI_OFF(RamSize), + SK_PNMI_RO, General, 0}, + {OID_SKGE_VAUXAVAIL, + 1, + 0, + SK_PNMI_MAI_OFF(VauxAvail), + SK_PNMI_RO, General, 0}, {OID_SKGE_ACTION, 1, 0, @@ -860,6 +1054,18 @@ PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = { sizeof(SK_PNMI_CONF), SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfConnector), SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_PHY_TYPE, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyType), + SK_PNMI_RO, MacPrivateConf, 0}, +#ifdef SK_PHY_LP_MODE + {OID_SKGE_PHY_LP_MODE, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyMode), + SK_PNMI_RW, MacPrivateConf, 0}, +#endif {OID_SKGE_LINK_CAP, SK_PNMI_MAC_ENTRIES, sizeof(SK_PNMI_CONF), @@ -1055,6 +1261,15 @@ PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = { 0, 0, SK_PNMI_RO, Vct, 0}, + {OID_SKGE_VCT_CAPABILITIES, + 0, + 0, + 0, + SK_PNMI_RO, Vct, 0}, + {OID_SKGE_BOARDLEVEL, + 0, + 0, + 0, + SK_PNMI_RO, General, 0}, }; - -#endif /* CONFIG_SK98 */ +#endif diff --git a/drivers/sk98lin/skgepnmi.c b/drivers/sk98lin/skgepnmi.c index b5d32b0..3cbd12e 100644 --- a/drivers/sk98lin/skgepnmi.c +++ b/drivers/sk98lin/skgepnmi.c @@ -1,16 +1,18 @@ /***************************************************************************** * * Name: skgepnmi.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.102 $ - * Date: $Date: 2002/12/16 14:03:24 $ + * Project: Gigabit Ethernet Adapters, PNMI-Module + * Version: $Revision: 2.26 $ + * Date: $Date: 2005/12/21 09:53:21 $ * Purpose: Private Network Management Interface * ****************************************************************************/ /****************************************************************************** * + * LICENSE: * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,427 +20,17 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. + * /LICENSE * ******************************************************************************/ - -/***************************************************************************** - * - * History: - * - * $Log: skgepnmi.c,v $ - * Revision 1.102 2002/12/16 14:03:24 tschilli - * VCT code in Vct() changed. - * - * Revision 1.101 2002/12/16 09:04:10 tschilli - * Code for VCT handling added. - * - * Revision 1.100 2002/09/26 14:28:13 tschilli - * For XMAC the values in the SK_PNMI_PORT Port struct are copied to - * the new SK_PNMI_PORT BufPort struct during a MacUpdate() call. - * These values are used when GetPhysStatVal() is called. With this - * mechanism you get the best results when software corrections for - * counters are needed. Example: RX_LONGFRAMES. - * - * Revision 1.99 2002/09/17 12:31:19 tschilli - * OID_SKGE_TX_HW_ERROR_CTS, OID_SKGE_OUT_ERROR_CTS, OID_GEN_XMIT_ERROR: - * Double count of SK_PNMI_HTX_EXCESS_COL in function General() removed. - * OID_PNP_CAPABILITIES: sizeof(SK_PM_WAKE_UP_CAPABILITIES) changed to - * sizeof(SK_PNP_CAPABILITIES) in function PowerManagement(). - * - * Revision 1.98 2002/09/10 09:00:03 rwahl - * Adapted boolean definitions according sktypes. - * - * Revision 1.97 2002/09/05 15:07:03 rwahl - * Editorial changes. - * - * Revision 1.96 2002/09/05 11:04:14 rwahl - * - Rx/Tx packets statistics of virtual port were zero on link down (#10750) - * - For GMAC the overflow IRQ for Rx longframe counter was not counted. - * - Incorrect calculation for oids OID_SKGE_RX_HW_ERROR_CTS, - * OID_SKGE_IN_ERRORS_CTS, OID_GEN_RCV_ERROR. - * - Moved correction for OID_SKGE_STAT_RX_TOO_LONG to GetPhysStatVal(). - * - Editorial changes. - * - * Revision 1.95 2002/09/04 08:53:37 rwahl - * - Incorrect statistics for Rx_too_long counter with jumbo frame (#10751) - * - StatRxFrameTooLong & StatRxPMaccErr counters were not reset. - * - Fixed compiler warning for debug msg arg types. - * - * Revision 1.94 2002/08/09 15:42:14 rwahl - * - Fixed StatAddr table for GMAC. - * - VirtualConf(): returned indeterminated status for speed oids if no - * active port. - * - * Revision 1.93 2002/08/09 11:04:59 rwahl - * Added handler for link speed caps. - * - * Revision 1.92 2002/08/09 09:43:03 rwahl - * - Added handler for NDIS OID_PNP_xxx ids. - * - * Revision 1.91 2002/07/17 19:53:03 rwahl - * - Added StatOvrflwBit table for XMAC & GMAC. - * - Extended StatAddr table for GMAC. Added check of number of counters - * in enumeration and size of StatAddr table on init level. - * - Added use of GIFunc table. - * - ChipSet is not static anymore, - * - Extended SIRQ event handler for both mac types. - * - Fixed rx short counter bug (#10620) - * - Added handler for oids SKGE_SPEED_MODE & SKGE_SPEED_STATUS. - * - Extendet GetPhysStatVal() for GMAC. - * - Editorial changes. - * - * Revision 1.90 2002/05/22 08:56:25 rwahl - * - Moved OID table to separate source file. - * - Fix: TX_DEFFERAL counter incremented in full-duplex mode. - * - Use string definitions for error msgs. - * - * Revision 1.89 2001/09/18 10:01:30 mkunz - * some OID's fixed for dualnetmode - * - * Revision 1.88 2001/08/02 07:58:08 rwahl - * - Fixed NetIndex to csum module at ResetCounter(). - * - * Revision 1.87 2001/04/06 13:35:09 mkunz - * -Bugs fixed in handling of OID_SKGE_MTU and the VPD OID's - * - * Revision 1.86 2001/03/09 09:18:03 mkunz - * Changes in SK_DBG_MSG - * - * Revision 1.85 2001/03/08 09:37:31 mkunz - * Bugfix in ResetCounter for Pnmi.Port structure - * - * Revision 1.84 2001/03/06 09:04:55 mkunz - * Made some changes in instance calculation - * - * Revision 1.83 2001/02/15 09:15:32 mkunz - * Necessary changes for dual net mode added - * - * Revision 1.82 2001/02/07 08:24:19 mkunz - * -Made changes in handling of OID_SKGE_MTU - * - * Revision 1.81 2001/02/06 09:58:00 mkunz - * -Vpd bug fixed - * -OID_SKGE_MTU added - * -pnmi support for dual net mode. Interface function and macros extended - * - * Revision 1.80 2001/01/22 13:41:35 rassmann - * Supporting two nets on dual-port adapters. - * - * Revision 1.79 2000/12/05 14:57:40 cgoos - * SetStruct failed before first Link Up (link mode of virtual - * port "INDETERMINATED"). - * - * Revision 1.78 2000/09/12 10:44:58 cgoos - * Fixed SK_PNMI_STORE_U32 calls with typecasted argument. - * - * Revision 1.77 2000/09/07 08:10:19 rwahl - * - Modified algorithm for 64bit NDIS statistic counters; - * returns 64bit or 32bit value depending on passed buffer - * size. Indicate capability for 64bit NDIS counter, if passed - * buffer size is zero. OID_GEN_XMIT_ERROR, OID_GEN_RCV_ERROR, - * and OID_GEN_RCV_NO_BUFFER handled as 64bit counter, too. - * - corrected OID_SKGE_RLMT_PORT_PREFERRED. - * - * Revision 1.76 2000/08/03 15:23:39 rwahl - * - Correction for FrameTooLong counter has to be moved to OID handling - * routines (instead of statistic counter routine). - * - Fix in XMAC Reset Event handling: Only offset counter for hardware - * statistic registers are updated. - * - * Revision 1.75 2000/08/01 16:46:05 rwahl - * - Added StatRxLongFrames counter and correction of FrameTooLong counter. - * - Added directive to control width (default = 32bit) of NDIS statistic - * counters (SK_NDIS_64BIT_CTR). - * - * Revision 1.74 2000/07/04 11:41:53 rwahl - * - Added volition connector type. - * - * Revision 1.73 2000/03/15 16:33:10 rwahl - * Fixed bug 10510; wrong reset of virtual port statistic counters. - * - * Revision 1.72 1999/12/06 16:15:53 rwahl - * Fixed problem of instance range for current and factory MAC address. - * - * Revision 1.71 1999/12/06 10:14:20 rwahl - * Fixed bug 10476; set operation for PHY_OPERATION_MODE. - * - * Revision 1.70 1999/11/22 13:33:34 cgoos - * Changed license header to GPL. - * - * Revision 1.69 1999/10/18 11:42:15 rwahl - * Added typecasts for checking event dependent param (debug only). - * - * Revision 1.68 1999/10/06 09:35:59 cgoos - * Added state check to PHY_READ call (hanged if called during startup). - * - * Revision 1.67 1999/09/22 09:53:20 rwahl - * - Read Broadcom register for updating fcs error counter (1000Base-T). - * - * Revision 1.66 1999/08/26 13:47:56 rwahl - * Added SK_DRIVER_SENDEVENT when queueing RLMT_CHANGE_THRES trap. - * - * Revision 1.65 1999/07/26 07:49:35 cgoos - * Added two typecasts to avoid compiler warnings. - * - * Revision 1.64 1999/05/20 09:24:12 cgoos - * Changes for 1000Base-T (sensors, Master/Slave). - * - * Revision 1.63 1999/04/13 15:11:58 mhaveman - * Moved include of rlmt.h to header skgepnmi.h because some macros - * are needed there. - * - * Revision 1.62 1999/04/13 15:08:07 mhaveman - * Replaced again SK_RLMT_CHECK_LINK with SK_PNMI_RLMT_MODE_CHK_LINK - * to grant unified interface by only using the PNMI header file. - * SK_PNMI_RLMT_MODE_CHK_LINK is defined the same as SK_RLMT_CHECK_LINK. - * - * Revision 1.61 1999/04/13 15:02:48 mhaveman - * Changes caused by review: - * -Changed some comments - * -Removed redundant check for OID_SKGE_PHYS_FAC_ADDR - * -Optimized PRESET check. - * -Meaning of error SK_ADDR_DUPLICATE_ADDRESS changed. Set of same - * address will now not cause this error. Removed corresponding check. - * - * Revision 1.60 1999/03/23 10:41:23 mhaveman - * Added comments. - * - * Revision 1.59 1999/02/19 08:01:28 mhaveman - * Fixed bug 10372 that after counter reset all ports were displayed - * as inactive. - * - * Revision 1.58 1999/02/16 18:04:47 mhaveman - * Fixed problem of twisted OIDs SENSOR_WAR_TIME and SENSOR_ERR_TIME. - * - * Revision 1.56 1999/01/27 12:29:11 mhaveman - * SkTimerStart was called with time value in milli seconds but needs - * micro seconds. - * - * Revision 1.55 1999/01/25 15:00:38 mhaveman - * Added support to allow multiple ports to be active. If this feature in - * future will be used, the Management Data Base variables PORT_ACTIVE - * and PORT_PREFERED should be moved to the port specific part of RLMT. - * Currently they return the values of the first active physical port - * found. A set to the virtual port will actually change all active - * physical ports. A get returns the melted values of all active physical - * ports. If the port values differ a return value INDETERMINATED will - * be returned. This effects especially the CONF group. - * - * Revision 1.54 1999/01/19 10:10:22 mhaveman - * -Fixed bug 10354: Counter values of virtual port were wrong after port - * switches - * -Added check if a switch to the same port is notified. - * - * Revision 1.53 1999/01/07 09:25:21 mhaveman - * Forgot to initialize a variable. - * - * Revision 1.52 1999/01/05 10:34:33 mhaveman - * Fixed little error in RlmtChangeEstimate calculation. - * - * Revision 1.51 1999/01/05 09:59:07 mhaveman - * -Moved timer start to init level 2 - * -Redesigned port switch average calculation to avoid 64bit - * arithmetic. - * - * Revision 1.50 1998/12/10 15:13:59 mhaveman - * -Fixed: PHYS_CUR_ADDR returned wrong addresses - * -Fixed: RLMT_PORT_PREFERED and RLMT_CHANGE_THRES preset returned - * always BAD_VALUE. - * -Fixed: TRAP buffer seemed to sometimes suddenly empty - * - * Revision 1.49 1998/12/09 16:17:07 mhaveman - * Fixed: Couldnot delete VPD keys on UNIX. - * - * Revision 1.48 1998/12/09 14:11:10 mhaveman - * -Add: Debugmessage for XMAC_RESET supressed to minimize output. - * -Fixed: RlmtChangeThreshold will now be initialized. - * -Fixed: VPD_ENTRIES_LIST extended value with unnecessary space char. - * -Fixed: On VPD key creation an invalid key name could be created - * (e.g. A5) - * -Some minor changes in comments and code. - * - * Revision 1.47 1998/12/08 16:00:31 mhaveman - * -Fixed: For RLMT_PORT_ACTIVE will now be returned a 0 if no port - * is active. - * -Fixed: For the RLMT statistics group only the last value was - * returned and the rest of the buffer was filled with 0xff - * -Fixed: Mysteriously the preset on RLMT_MODE still returned - * BAD_VALUE. - * Revision 1.46 1998/12/08 10:04:56 mhaveman - * -Fixed: Preset on RLMT_MODE returned always BAD_VALUE error. - * -Fixed: Alignment error in GetStruct - * -Fixed: If for Get/Preset/SetStruct the buffer size is equal or - * larger than SK_PNMI_MIN_STRUCT_SIZE the return value is stored - * to the buffer. In this case the caller should always return - * ok to its upper routines. Only if the buffer size is less - * than SK_PNMI_MIN_STRUCT_SIZE and the return value is unequal - * to 0, an error should be returned by the caller. - * -Fixed: Wrong number of instances with RLMT statistic. - * -Fixed: Return now SK_LMODE_STAT_UNKNOWN if the LinkModeStatus is 0. - * - * Revision 1.45 1998/12/03 17:17:24 mhaveman - * -Removed for VPD create action the buffer size limitation to 4 bytes. - * -Pass now physical/active physical port to ADDR for CUR_ADDR set - * - * Revision 1.44 1998/12/03 15:14:35 mhaveman - * Another change to Vpd instance evaluation. - * - * Revision 1.43 1998/12/03 14:18:10 mhaveman - * -Fixed problem in PnmiSetStruct. It was impossible to set any value. - * -Removed VPD key evaluation for VPD_FREE_BYTES and VPD_ACTION. - * - * Revision 1.42 1998/12/03 11:31:47 mhaveman - * Inserted cast to satisfy lint. - * - * Revision 1.41 1998/12/03 11:28:16 mhaveman - * Removed SK_PNMI_CHECKPTR - * - * Revision 1.40 1998/12/03 11:19:07 mhaveman - * Fixed problems - * -A set to virtual port will now be ignored. A set with broadcast - * address to any port will be ignored. - * -GetStruct function made VPD instance calculation wrong. - * -Prefered port returned -1 instead of 0. - * - * Revision 1.39 1998/11/26 15:30:29 mhaveman - * Added sense mode to link mode. - * - * Revision 1.38 1998/11/23 15:34:00 mhaveman - * -Fixed bug for RX counters. On an RX overflow interrupt the high - * words of all RX counters were incremented. - * -SET operations on FLOWCTRL_MODE and LINK_MODE accept now the - * value 0, which has no effect. It is usefull for multiple instance - * SETs. - * - * Revision 1.37 1998/11/20 08:02:04 mhaveman - * -Fixed: Ports were compared with MAX_SENSORS - * -Fixed: Crash in GetTrapEntry with MEMSET macro - * -Fixed: Conversions between physical, logical port index and instance - * - * Revision 1.36 1998/11/16 07:48:53 mhaveman - * Casted SK_DRIVER_SENDEVENT with (void) to eleminate compiler warnings - * on Solaris. - * - * Revision 1.35 1998/11/16 07:45:34 mhaveman - * SkAddrOverride now returns value and will be checked. - * - * Revision 1.34 1998/11/10 13:40:37 mhaveman - * Needed to change interface, because NT driver needs a return value - * of needed buffer space on TOO_SHORT errors. Therefore all - * SkPnmiGet/Preset/Set functions now have a pointer to the length - * parameter, where the needed space on error is returned. - * - * Revision 1.33 1998/11/03 13:52:46 mhaveman - * Made file lint conform. - * - * Revision 1.32 1998/11/03 13:19:07 mhaveman - * The events SK_HWEV_SET_LMODE and SK_HWEV_SET_FLOWMODE pass now in - * Para32[0] the physical MAC index and in Para32[1] the new mode. - * - * Revision 1.31 1998/11/03 12:30:40 gklug - * fix: compiler warning memset - * - * Revision 1.30 1998/11/03 12:04:46 mhaveman - * Fixed problem in SENSOR_VALUE, which wrote beyond the buffer end - * Fixed alignment problem with CHIPSET. - * - * Revision 1.29 1998/11/02 11:23:54 mhaveman - * Corrected SK_ERROR_LOG to SK_ERR_LOG. Sorry. - * - * Revision 1.28 1998/11/02 10:47:16 mhaveman - * Added syslog messages for internal errors. - * - * Revision 1.27 1998/10/30 15:48:06 mhaveman - * Fixed problems after simulation of SK_PNMI_EVT_CHG_EST_TIMER and - * RlmtChangeThreshold calculation. - * - * Revision 1.26 1998/10/29 15:36:55 mhaveman - * -Fixed bug in trap buffer handling. - * -OID_SKGE_DRIVER_DESCR, OID_SKGE_DRIVER_VERSION, OID_SKGE_HW_DESCR, - * OID_SKGE_HW_VERSION, OID_SKGE_VPD_ENTRIES_LIST, OID_SKGE_VPD_KEY, - * OID_SKGE_VPD_VALUE, and OID_SKGE_SENSOR_DESCR return values with - * a leading octet before each string storing the string length. - * -Perform a RlmtUpdate during SK_PNMI_EVT_XMAC_RESET to minimize - * RlmtUpdate calls in GetStatVal. - * -Inserted SK_PNMI_CHECKFLAGS macro increase readability. - * - * Revision 1.25 1998/10/29 08:50:36 mhaveman - * Fixed problems after second event simulation. - * - * Revision 1.24 1998/10/28 08:44:37 mhaveman - * -Fixed alignment problem - * -Fixed problems during event simulation - * -Fixed sequence of error return code (INSTANCE -> ACCESS -> SHORT) - * -Changed type of parameter Instance back to SK_U32 because of VPD - * -Updated new VPD function calls - * - * Revision 1.23 1998/10/23 10:16:37 mhaveman - * Fixed bugs after buffer test simulation. - * - * Revision 1.22 1998/10/21 13:23:52 mhaveman - * -Call syntax of SkOsGetTime() changed to SkOsGetTime(pAc). - * -Changed calculation of hundrets of seconds. - * - * Revision 1.20 1998/10/20 07:30:45 mhaveman - * Made type changes to unsigned integer where possible. - * - * Revision 1.19 1998/10/19 10:51:30 mhaveman - * -Made Bug fixes after simulation run - * -Renamed RlmtMAC... to RlmtPort... - * -Marked workarounds with Errata comments - * - * Revision 1.18 1998/10/14 07:50:08 mhaveman - * -For OID_SKGE_LINK_STATUS the link down detection has moved from RLMT - * to HWACCESS. - * -Provided all MEMCPY/MEMSET macros with (char *) pointers, because - * Solaris throwed warnings when mapping to bcopy/bset. - * - * Revision 1.17 1998/10/13 07:42:01 mhaveman - * -Added OIDs OID_SKGE_TRAP_NUMBER and OID_SKGE_ALL_DATA - * -Removed old cvs history entries - * -Renamed MacNumber to PortNumber - * - * Revision 1.16 1998/10/07 10:52:49 mhaveman - * -Inserted handling of some OID_GEN_ Ids for windows - * -Fixed problem with 803.2 statistic. - * - * Revision 1.15 1998/10/01 09:16:29 mhaveman - * Added Debug messages for function call and UpdateFlag tracing. - * - * Revision 1.14 1998/09/30 13:39:09 mhaveman - * -Reduced namings of 'MAC' by replacing them with 'PORT'. - * -Completed counting of OID_SKGE_RX_HW_ERROR_CTS, - * OID_SKGE_TX_HW_ERROR_CTS, - * OID_SKGE_IN_ERRORS_CTS, and OID_SKGE_OUT_ERROR_CTS. - * -SET check for RlmtMode - * - * Revision 1.13 1998/09/28 13:13:08 mhaveman - * Hide strcmp, strlen, and strncpy behind macros SK_STRCMP, SK_STRLEN, - * and SK_STRNCPY. (Same reasons as for mem.. and MEM..) - * - * Revision 1.12 1998/09/16 08:18:36 cgoos - * Fix: XM_INxx and XM_OUTxx called with different parameter order: - * sometimes IoC,Mac,... sometimes Mac,IoC,... Now always first variant. - * Fix: inserted "Pnmi." into some pAC->pDriverDescription / Version. - * Change: memset, memcpy to makros SK_MEMSET, SK_MEMCPY - * - * Revision 1.11 1998/09/04 17:01:45 mhaveman - * Added SyncCounter as macro and OID_SKGE_.._NO_DESCR_CTS to - * OID_SKGE_RX_NO_BUF_CTS. - * - * Revision 1.10 1998/09/04 14:35:35 mhaveman - * Added macro counters, that are counted by driver. - * - ****************************************************************************/ - - #include - + #ifdef CONFIG_SK98 +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) static const char SysKonnectFileId[] = - "@(#) $Id: skgepnmi.c,v 1.102 2002/12/16 14:03:24 tschilli Exp $" - " (C) SysKonnect."; + "@(#) $Id: skgepnmi.c,v 2.26 2005/12/21 09:53:21 tschilli Exp $ (C) Marvell."; +#endif #include "h/skdrv1st.h" #include "h/sktypes.h" @@ -450,12 +42,14 @@ static const char SysKonnectFileId[] = #include "h/skcsum.h" #include "h/skvpd.h" #include "h/skgehw.h" +#include "h/sky2le.h" #include "h/skgeinit.h" #include "h/skdrv2nd.h" #include "h/skgepnm2.h" #ifdef SK_POWER_MGMT #include "h/skgepmgt.h" -#endif +#endif /* SK_POWER_MGMT */ + /* defines *******************************************************************/ #ifndef DEBUG @@ -464,25 +58,6 @@ static const char SysKonnectFileId[] = #define PNMI_STATIC #endif /* DEBUG */ -/* - * Public Function prototypes - */ -int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int level); -int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf, - unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); -int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf, - unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); -int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf, - unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); -int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, - unsigned int *pLen, SK_U32 NetIndex); -int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, - unsigned int *pLen, SK_U32 NetIndex); -int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, - unsigned int *pLen, SK_U32 NetIndex); -int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param); - - /* * Private Function prototypes */ @@ -519,9 +94,8 @@ PNMI_STATIC void ResetCounter(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex); PNMI_STATIC int RlmtUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex); PNMI_STATIC int SirqUpdate(SK_AC *pAC, SK_IOC IoC); PNMI_STATIC void VirtualConf(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, char *pBuf); -PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id, char *pBuf, - unsigned int *pLen, SK_U32 Instance, unsigned int TableIndex, SK_U32 NetIndex); PNMI_STATIC void CheckVctStatus(SK_AC *, SK_IOC, char *, SK_U32, SK_U32); +PNMI_STATIC void VctGetResults(SK_AC *, SK_IOC, SK_U32); /* * Table to correlate OID with handler function and index to @@ -698,7 +272,7 @@ PNMI_STATIC const SK_PNMI_STATADDR StatAddr[SK_PNMI_MAX_IDX][SK_PNMI_MAC_TYPES] /* SK_PNMI_HRX_FRAMING */ {{XM_RXF_FRA_ERR, SK_TRUE}, {0, SK_FALSE}}, /* SK_PNMI_HRX_UNDERSIZE */ - {{0, SK_FALSE},{GM_RXF_SHT, SK_TRUE}}, + {{0, SK_FALSE}, {GM_RXF_SHT, SK_TRUE}}, /* SK_PNMI_HRX_OVERFLOW */ {{XM_RXE_FIFO_OV, SK_TRUE}, {GM_RXE_FIFO_OV, SK_TRUE}}, /* SK_PNMI_HRX_JABBER */ @@ -763,18 +337,13 @@ PNMI_STATIC const SK_PNMI_STATADDR StatAddr[SK_PNMI_MAX_IDX][SK_PNMI_MAC_TYPES] * Always 0 */ int SkPnmiInit( -SK_AC *pAC, /* Pointer to adapter context */ -SK_IOC IoC, /* IO context handle */ -int Level) /* Initialization level */ +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Level) /* Initialization level */ { unsigned int PortMax; /* Number of ports */ unsigned int PortIndex; /* Current port index in loop */ - SK_U16 Val16; /* Multiple purpose 16 bit variable */ - SK_U8 Val8; /* Mulitple purpose 8 bit variable */ - SK_EVPARA EventParam; /* Event struct for timer event */ - SK_GEPORT *pPrt; - SK_PNMI_VCT *pVctBackupData; - + SK_EVPARA EventParam; /* Event struct for timer event */ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, ("PNMI: SkPnmiInit: Called, level=%d\n", Level)); @@ -783,30 +352,35 @@ int Level) /* Initialization level */ case SK_INIT_DATA: SK_MEMSET((char *)&pAC->Pnmi, 0, sizeof(pAC->Pnmi)); + pAC->Pnmi.TrapBufFree = SK_PNMI_TRAP_QUEUE_LEN; pAC->Pnmi.StartUpTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC)); pAC->Pnmi.RlmtChangeThreshold = SK_PNMI_DEF_RLMT_CHG_THRES; + for (PortIndex = 0; PortIndex < SK_MAX_MACS; PortIndex ++) { pAC->Pnmi.Port[PortIndex].ActiveFlag = SK_FALSE; pAC->Pnmi.DualNetActiveFlag = SK_FALSE; + + /* Initialize DSP variables for Vct() to 0xff => Never written! */ + pAC->GIni.GP[PortIndex].PCableLen = 0xff; + pAC->Pnmi.VctBackup[PortIndex].CableLen = 0xff; } #ifdef SK_PNMI_CHECK if (SK_PNMI_MAX_IDX != SK_PNMI_CNT_NO) { - + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR049, SK_PNMI_ERR049MSG); SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL, ("CounterOffset struct size (%d) differs from" "SK_PNMI_MAX_IDX (%d)\n", SK_PNMI_CNT_NO, SK_PNMI_MAX_IDX)); - BRK; } if (SK_PNMI_MAX_IDX != (sizeof(StatAddr) / (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES))) { - + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR050, SK_PNMI_ERR050MSG); SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL, @@ -815,15 +389,13 @@ int Level) /* Initialization level */ (sizeof(StatAddr) / (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES)), SK_PNMI_MAX_IDX)); - BRK; } #endif /* SK_PNMI_CHECK */ break; case SK_INIT_IO: - /* - * Reset MAC counters - */ + + /* Reset MAC counters. */ PortMax = pAC->GIni.GIMacsFound; for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) { @@ -831,42 +403,27 @@ int Level) /* Initialization level */ pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PortIndex); } - /* Initialize DSP variables for Vct() to 0xff => Never written! */ - for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) { - pPrt = &pAC->GIni.GP[PortIndex]; - pPrt->PCableLen =0xff; - pVctBackupData = &pAC->Pnmi.VctBackup[PortIndex]; - pVctBackupData->PCableLen = 0xff; - } + /* Get PCI bus speed. */ + if (pAC->GIni.GIPciClock66) { - /* - * Get pci bus speed - */ - SK_IN16(IoC, B0_CTST, &Val16); - if ((Val16 & CS_BUS_CLOCK) == 0) { - - pAC->Pnmi.PciBusSpeed = 33; - } - else { pAC->Pnmi.PciBusSpeed = 66; } - - /* - * Get pci bus width - */ - SK_IN16(IoC, B0_CTST, &Val16); - if ((Val16 & CS_BUS_SLOT_SZ) == 0) { - - pAC->Pnmi.PciBusWidth = 32; - } else { + pAC->Pnmi.PciBusSpeed = 33; + } + + /* Get PCI bus width. */ + if (pAC->GIni.GIPciSlot64) { + pAC->Pnmi.PciBusWidth = 64; } + else { + pAC->Pnmi.PciBusWidth = 32; + } - /* - * Get chipset - */ + /* Get chipset. */ switch (pAC->GIni.GIChipId) { + case CHIP_ID_GENESIS: pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_XMAC; break; @@ -875,57 +432,51 @@ int Level) /* Initialization level */ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON; break; + case CHIP_ID_YUKON_LITE: + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LITE; + break; + + case CHIP_ID_YUKON_LP: + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LP; + break; + + case CHIP_ID_YUKON_XL: + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_XL; + break; + + case CHIP_ID_YUKON_EC: + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_EC; + break; + + case CHIP_ID_YUKON_FE: + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_FE; + break; + default: break; } - /* - * Get PMD and DeviceType - */ - SK_IN8(IoC, B2_PMD_TYP, &Val8); - switch (Val8) { + /* Get PMD and Device Type. */ + switch (pAC->GIni.GIPmdTyp) { + case 'S': pAC->Pnmi.PMD = 3; - if (pAC->GIni.GIMacsFound > 1) { - - pAC->Pnmi.DeviceType = 0x00020002; - } - else { - pAC->Pnmi.DeviceType = 0x00020001; - } + pAC->Pnmi.DeviceType = 0x00020001; break; case 'L': pAC->Pnmi.PMD = 2; - if (pAC->GIni.GIMacsFound > 1) { - - pAC->Pnmi.DeviceType = 0x00020004; - } - else { - pAC->Pnmi.DeviceType = 0x00020003; - } + pAC->Pnmi.DeviceType = 0x00020003; break; case 'C': pAC->Pnmi.PMD = 4; - if (pAC->GIni.GIMacsFound > 1) { - - pAC->Pnmi.DeviceType = 0x00020006; - } - else { - pAC->Pnmi.DeviceType = 0x00020005; - } + pAC->Pnmi.DeviceType = 0x00020005; break; case 'T': pAC->Pnmi.PMD = 5; - if (pAC->GIni.GIMacsFound > 1) { - - pAC->Pnmi.DeviceType = 0x00020008; - } - else { - pAC->Pnmi.DeviceType = 0x00020007; - } + pAC->Pnmi.DeviceType = 0x00020007; break; default : @@ -934,11 +485,14 @@ int Level) /* Initialization level */ break; } - /* - * Get connector - */ - SK_IN8(IoC, B2_CONN_TYP, &Val8); - switch (Val8) { + if (pAC->GIni.GIMacsFound > 1) { + + pAC->Pnmi.DeviceType++; + } + + /* Get connector type. */ + switch (pAC->GIni.GIConTyp) { + case 'C': pAC->Pnmi.Connector = 2; break; @@ -966,17 +520,17 @@ int Level) /* Initialization level */ break; case SK_INIT_RUN: - /* - * Start timer for RLMT change counter - */ - SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam)); + + /* Start timer for RLMT change counter. */ + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer, - 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER, + SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER, EventParam); break; default: - break; /* Nothing todo */ + break; /* Nothing to do. */ } return (0); @@ -998,17 +552,17 @@ int Level) /* Initialization level */ * the data. * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ int SkPnmiGetVar( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ SK_U32 Id, /* Object ID that is to be processed */ -void *pBuf, /* Buffer to which to mgmt data will be retrieved */ +void *pBuf, /* Buffer to which the management data will be copied */ unsigned int *pLen, /* On call: buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, ("PNMI: SkPnmiGetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n", @@ -1026,8 +580,8 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * Calls a general sub-function for all this stuff. The preset does * the same as a set, but returns just before finally setting the * new value. This is usefull to check if a set might be successfull. - * If as instance a -1 is passed, an array of values is supposed and - * all instance of the OID will be set. + * If the instance -1 is passed, an array of values is supposed and + * all instances of the OID will be set. * * Returns: * SK_PNMI_ERR_OK The request was successfully performed. @@ -1040,23 +594,22 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown. * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ int SkPnmiPreSetVar( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ SK_U32 Id, /* Object ID that is to be processed */ -void *pBuf, /* Buffer which stores the mgmt data to be set */ -unsigned int *pLen, /* Total length of mgmt data */ +void *pBuf, /* Buffer to which the management data will be copied */ +unsigned int *pLen, /* Total length of management data */ SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, ("PNMI: SkPnmiPreSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n", Id, *pLen, Instance, NetIndex)); - return (PnmiVar(pAC, IoC, SK_PNMI_PRESET, Id, (char *)pBuf, pLen, Instance, NetIndex)); } @@ -1069,8 +622,8 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * Calls a general sub-function for all this stuff. The preset does * the same as a set, but returns just before finally setting the * new value. This is usefull to check if a set might be successfull. - * If as instance a -1 is passed, an array of values is supposed and - * all instance of the OID will be set. + * If the instance -1 is passed, an array of values is supposed and + * all instances of the OID will be set. * * Returns: * SK_PNMI_ERR_OK The request was successfully performed. @@ -1083,17 +636,17 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown. * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ int SkPnmiSetVar( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ SK_U32 Id, /* Object ID that is to be processed */ -void *pBuf, /* Buffer which stores the mgmt data to be set */ -unsigned int *pLen, /* Total length of mgmt data */ +void *pBuf, /* Buffer to which the management data will be copied */ +unsigned int *pLen, /* Total length of management data */ SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, ("PNMI: SkPnmiSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n", @@ -1125,9 +678,9 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ int SkPnmiGetStruct( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -void *pBuf, /* Buffer which will store the retrieved data */ +void *pBuf, /* Buffer to which the management data will be copied. */ unsigned int *pLen, /* Length of buffer */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { int Ret; unsigned int TableIndex; @@ -1138,7 +691,6 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ unsigned int TmpLen; char KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE]; - SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, ("PNMI: SkPnmiGetStruct: Called, BufLen=%d, NetIndex=%d\n", *pLen, NetIndex)); @@ -1147,22 +699,19 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) { - SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, - (SK_U32)(-1)); + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1)); } *pLen = SK_PNMI_STRUCT_SIZE; return (SK_PNMI_ERR_TOO_SHORT); } - /* - * Check NetIndex - */ + /* Check NetIndex. */ if (NetIndex >= pAC->Rlmt.NumNets) { return (SK_PNMI_ERR_UNKNOWN_NET); } - /* Update statistic */ + /* Update statistics. */ SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On call"); if ((Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1)) != @@ -1187,35 +736,37 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (Ret); } - /* - * Increment semaphores to indicate that an update was - * already done - */ + /* Increment semaphores to indicate that an update was already done. */ pAC->Pnmi.MacUpdatedFlag ++; pAC->Pnmi.RlmtUpdatedFlag ++; pAC->Pnmi.SirqUpdatedFlag ++; - /* Get vpd keys for instance calculation */ - Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen); - if (Ret != SK_PNMI_ERR_OK) { + /* + * Get VPD keys for instance calculation. + * Please read comment in Vpd(). + */ + if (pAC->Pnmi.VpdKeyReadError == SK_FALSE) { + Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen); + if (Ret != SK_PNMI_ERR_OK) { - pAC->Pnmi.MacUpdatedFlag --; - pAC->Pnmi.RlmtUpdatedFlag --; - pAC->Pnmi.SirqUpdatedFlag --; + pAC->Pnmi.MacUpdatedFlag --; + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; - SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return"); - SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); - *pLen = SK_PNMI_MIN_STRUCT_SIZE; - return (SK_PNMI_ERR_GENERAL); + SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return"); + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (SK_PNMI_ERR_GENERAL); + } } - /* Retrieve values */ + /* Retrieve values. */ SK_MEMSET((char *)pBuf, 0, SK_PNMI_STRUCT_SIZE); + for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) { InstanceNo = IdTable[TableIndex].InstanceNo; - for (InstanceCnt = 1; InstanceCnt <= InstanceNo; - InstanceCnt ++) { + for (InstanceCnt = 1; InstanceCnt <= InstanceNo; InstanceCnt ++) { DstOffset = IdTable[TableIndex].Offset + (InstanceCnt - 1) * @@ -1250,7 +801,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ */ if (Ret == SK_PNMI_ERR_UNKNOWN_INST) { - break; + break; } if (Ret != SK_PNMI_ERR_OK) { @@ -1305,14 +856,14 @@ SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ void *pBuf, /* Buffer which contains the data to be set */ unsigned int *pLen, /* Length of buffer */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, ("PNMI: SkPnmiPreSetStruct: Called, BufLen=%d, NetIndex=%d\n", *pLen, NetIndex)); return (PnmiStruct(pAC, IoC, SK_PNMI_PRESET, (char *)pBuf, - pLen, NetIndex)); + pLen, NetIndex)); } /***************************************************************************** @@ -1343,14 +894,14 @@ SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ void *pBuf, /* Buffer which contains the data to be set */ unsigned int *pLen, /* Length of buffer */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, ("PNMI: SkPnmiSetStruct: Called, BufLen=%d, NetIndex=%d\n", *pLen, NetIndex)); return (PnmiStruct(pAC, IoC, SK_PNMI_SET, (char *)pBuf, - pLen, NetIndex)); + pLen, NetIndex)); } /***************************************************************************** @@ -1396,9 +947,9 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * is now an active port. PNMI will now * add the statistic data of this port to * the virtual port. - * SK_PNMI_EVT_RLMT_SET_NETS Notifies PNMI about the net mode. The first Parameter + * SK_PNMI_EVT_RLMT_SET_NETS Notifies PNMI about the net mode. The first parameter * contains the number of nets. 1 means single net, 2 means - * dual net. The second Parameter is -1 + * dual net. The second parameter is -1 * * Returns: * Always 0 @@ -1410,9 +961,8 @@ SK_U32 Event, /* Event-Id */ SK_EVPARA Param) /* Event dependent parameter */ { unsigned int PhysPortIndex; - unsigned int MaxNetNumber; + unsigned int MaxNetNumber; int CounterIndex; - int Ret; SK_U16 MacStatus; SK_U64 OverflowStatus; SK_U64 Mask; @@ -1426,12 +976,7 @@ SK_EVPARA Param) /* Event dependent parameter */ SK_U64 Delta; SK_PNMI_ESTIMATE *pEst; SK_U32 NetIndex; - SK_GEPORT *pPrt; - SK_PNMI_VCT *pVctBackupData; SK_U32 RetCode; - int i; - SK_U32 CableLength; - #ifdef DEBUG if (Event != SK_PNMI_EVT_XMAC_RESET) { @@ -1440,11 +985,11 @@ SK_EVPARA Param) /* Event dependent parameter */ ("PNMI: SkPnmiEvent: Called, Event=0x%x, Param=0x%x\n", (unsigned int)Event, (unsigned int)Param.Para64)); } -#endif +#endif /* DEBUG */ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On call"); MacType = pAC->GIni.GIMacType; - + switch (Event) { case SK_PNMI_EVT_SIRQ_OVERFLOW: @@ -1459,14 +1004,12 @@ SK_EVPARA Param) /* Event dependent parameter */ PhysPortIndex)); return (0); } -#endif +#endif /* DEBUG */ OverflowStatus = 0; - /* - * Check which source caused an overflow interrupt. - */ - if ((pAC->GIni.GIFunc.pFnMacOverflow( - pAC, IoC, PhysPortIndex, MacStatus, &OverflowStatus) != 0) || + /* Check which source caused an overflow interrupt. */ + if ((pAC->GIni.GIFunc.pFnMacOverflow(pAC, IoC, PhysPortIndex, + MacStatus, &OverflowStatus) != 0) || (OverflowStatus == 0)) { SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); @@ -1482,7 +1025,6 @@ SK_EVPARA Param) /* Event dependent parameter */ Mask = (SK_U64)1 << CounterIndex; if ((OverflowStatus & Mask) == 0) { - continue; } @@ -1490,20 +1032,20 @@ SK_EVPARA Param) /* Event dependent parameter */ case SK_PNMI_HTX_UTILUNDER: case SK_PNMI_HTX_UTILOVER: - XM_IN16(IoC, PhysPortIndex, XM_TX_CMD, - &Register); - Register |= XM_TX_SAM_LINE; - XM_OUT16(IoC, PhysPortIndex, XM_TX_CMD, - Register); + if (MacType == SK_MAC_XMAC) { + XM_IN16(IoC, PhysPortIndex, XM_TX_CMD, &Register); + Register |= XM_TX_SAM_LINE; + XM_OUT16(IoC, PhysPortIndex, XM_TX_CMD, Register); + } break; case SK_PNMI_HRX_UTILUNDER: case SK_PNMI_HRX_UTILOVER: - XM_IN16(IoC, PhysPortIndex, XM_RX_CMD, - &Register); - Register |= XM_RX_SAM_LINE; - XM_OUT16(IoC, PhysPortIndex, XM_RX_CMD, - Register); + if (MacType == SK_MAC_XMAC) { + XM_IN16(IoC, PhysPortIndex, XM_RX_CMD, &Register); + Register |= XM_RX_SAM_LINE; + XM_OUT16(IoC, PhysPortIndex, XM_RX_CMD, Register); + } break; case SK_PNMI_HTX_OCTETHIGH: @@ -1513,10 +1055,8 @@ SK_EVPARA Param) /* Event dependent parameter */ case SK_PNMI_HRX_OCTETLOW: case SK_PNMI_HRX_IRLENGTH: case SK_PNMI_HRX_RESERVED: - - /* - * the following counters aren't be handled (id > 63) - */ + + /* The following counters aren't be handled (id > 63). */ case SK_PNMI_HTX_SYNC: case SK_PNMI_HTX_SYNC_OCTET: break; @@ -1544,7 +1084,8 @@ SK_EVPARA Param) /* Event dependent parameter */ (unsigned int)Param.Para64)); return (0); } -#endif +#endif /* DEBUG */ + /* * Store a trap message in the trap buffer and generate * an event for user space applications with the @@ -1560,11 +1101,12 @@ SK_EVPARA Param) /* Event dependent parameter */ if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) { SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, - ("PNMI: ERR:SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_UPP parameter wrong, SensorIndex=%d\n", + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_UPP parameter wrong, SensorIndex=%d\n", (unsigned int)Param.Para64)); return (0); } -#endif +#endif /* DEBUG */ + /* * Store a trap message in the trap buffer and generate * an event for user space applications with the @@ -1584,7 +1126,8 @@ SK_EVPARA Param) /* Event dependent parameter */ (unsigned int)Param.Para64)); return (0); } -#endif +#endif /* DEBUG */ + /* * Store a trap message in the trap buffer and generate * an event for user space applications with the @@ -1594,17 +1137,18 @@ SK_EVPARA Param) /* Event dependent parameter */ (unsigned int)Param.Para64); (void)SK_DRIVER_SENDEVENT(pAC, IoC); break; - + case SK_PNMI_EVT_SEN_ERR_UPP: #ifdef DEBUG if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) { SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, - ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n", + ("PNMI: ERR: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n", (unsigned int)Param.Para64)); return (0); } -#endif +#endif /* DEBUG */ + /* * Store a trap message in the trap buffer and generate * an event for user space applications with the @@ -1618,16 +1162,14 @@ SK_EVPARA Param) /* Event dependent parameter */ case SK_PNMI_EVT_CHG_EST_TIMER: /* * Calculate port switch average on a per hour basis - * Time interval for check : 28125 ms + * Time interval for check : 28125 ms (SK_PNMI_EVT_TIMER_CHECK) * Number of values for average : 8 * * Be careful in changing these values, on change check * - typedef of SK_PNMI_ESTIMATE (Size of EstValue * array one less than value number) - * - Timer initilization SkTimerStart() in SkPnmiInit - * - Delta value below must be multiplicated with - * power of 2 - * + * - Timer initialization SkTimerStart() in SkPnmiInit + * - Delta value below must be multiplicated with power of 2 */ pEst = &pAC->Pnmi.RlmtChangeEstimate; CounterIndex = pEst->EstValueIndex + 1; @@ -1650,7 +1192,7 @@ SK_EVPARA Param) /* Event dependent parameter */ Delta = NewestValue - OldestValue; } else { - /* Overflow situation */ + /* Overflow situation. */ Delta = (SK_U64)(0 - OldestValue) + NewestValue; } @@ -1675,9 +1217,10 @@ SK_EVPARA Param) /* Event dependent parameter */ (void)SK_DRIVER_SENDEVENT(pAC, IoC); } - SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam)); + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer, - 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER, + SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER, EventParam); break; @@ -1697,13 +1240,14 @@ SK_EVPARA Param) /* Event dependent parameter */ return (0); } -#endif +#endif /* DEBUG */ /* - * Set all counters and timestamps to zero + * Set all counters and timestamps to zero. + * The according NetIndex is required as a + * parameter of the event. */ - ResetCounter(pAC, IoC, NetIndex); /* the according NetIndex is required - as a Parameter of the Event */ + ResetCounter(pAC, IoC, NetIndex); break; case SK_PNMI_EVT_XMAC_RESET: @@ -1720,37 +1264,32 @@ SK_EVPARA Param) /* Event dependent parameter */ (unsigned int)Param.Para64)); return (0); } -#endif +#endif /* DEBUG */ + PhysPortIndex = (unsigned int)Param.Para64; - /* - * Update XMAC statistic to get fresh values - */ - Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1); - if (Ret != SK_PNMI_ERR_OK) { + /* Update XMAC statistic to get fresh values. */ + if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) != + SK_PNMI_ERR_OK) { SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); return (0); } - /* - * Increment semaphore to indicate that an update was - * already done - */ + + /* Increment semaphore to indicate that an update was already done. */ pAC->Pnmi.MacUpdatedFlag ++; for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX; CounterIndex ++) { if (!StatAddr[CounterIndex][MacType].GetOffset) { - continue; } - pAC->Pnmi.Port[PhysPortIndex]. - CounterOffset[CounterIndex] = GetPhysStatVal( - pAC, IoC, PhysPortIndex, CounterIndex); - pAC->Pnmi.Port[PhysPortIndex]. - CounterHigh[CounterIndex] = 0; + pAC->Pnmi.Port[PhysPortIndex].CounterOffset[CounterIndex] = + GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex); + + pAC->Pnmi.Port[PhysPortIndex].CounterHigh[CounterIndex] = 0; } pAC->Pnmi.MacUpdatedFlag --; @@ -1763,11 +1302,12 @@ SK_EVPARA Param) /* Event dependent parameter */ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_UP parameter" - " wrong, PhysPortIndex=%d\n", PhysPortIndex)); + " wrong, PhysPortIndex=%d\n", PhysPortIndex)); return (0); } -#endif +#endif /* DEBUG */ + /* * Store a trap message in the trap buffer and generate an event for * user space applications with the SK_DRIVER_SENDEVENT macro. @@ -1775,21 +1315,21 @@ SK_EVPARA Param) /* Event dependent parameter */ QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_UP, PhysPortIndex); (void)SK_DRIVER_SENDEVENT(pAC, IoC); - /* Bugfix for XMAC errata (#10620)*/ - if (pAC->GIni.GIMacType == SK_MAC_XMAC){ - - /* Add incremental difference to offset (#10620)*/ + /* Bugfix for XMAC errata (#10620). */ + if (MacType == SK_MAC_XMAC) { + /* Add incremental difference to offset (#10620). */ (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex, XM_RXE_SHT_ERR, &Val32); - + Value = (((SK_U64)pAC->Pnmi.Port[PhysPortIndex]. CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32); + pAC->Pnmi.Port[PhysPortIndex].CounterOffset[SK_PNMI_HRX_SHORTS] += Value - pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark; } - + /* Tell VctStatus() that a link was up meanwhile. */ - pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_LINK; + pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_LINK; break; case SK_PNMI_EVT_RLMT_PORT_DOWN: @@ -1800,11 +1340,12 @@ SK_EVPARA Param) /* Event dependent parameter */ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_DOWN parameter" - " wrong, PhysPortIndex=%d\n", PhysPortIndex)); + " wrong, PhysPortIndex=%d\n", PhysPortIndex)); return (0); } -#endif +#endif /* DEBUG */ + /* * Store a trap message in the trap buffer and generate an event for * user space applications with the SK_DRIVER_SENDEVENT macro. @@ -1812,11 +1353,12 @@ SK_EVPARA Param) /* Event dependent parameter */ QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_DOWN, PhysPortIndex); (void)SK_DRIVER_SENDEVENT(pAC, IoC); - /* Bugfix #10620 - get zero level for incremental difference */ - if ((pAC->GIni.GIMacType == SK_MAC_XMAC)) { + /* Bugfix #10620 - get zero level for incremental difference. */ + if (MacType == SK_MAC_XMAC) { (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex, XM_RXE_SHT_ERR, &Val32); + pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark = (((SK_U64)pAC->Pnmi.Port[PhysPortIndex]. CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32); @@ -1841,18 +1383,15 @@ SK_EVPARA Param) /* Event dependent parameter */ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, NetIndex=%d\n", NetIndex)); } -#endif - /* - * For now, ignore event if NetIndex != 0. - */ +#endif /* DEBUG */ + + /* For now, ignore event if NetIndex != 0. */ if (Param.Para32[1] != 0) { return (0); } - /* - * Nothing to do if port is already inactive - */ + /* Nothing to do if port is already inactive. */ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { return (0); @@ -1883,7 +1422,6 @@ SK_EVPARA Param) /* Event dependent parameter */ CounterIndex ++) { if (!StatAddr[CounterIndex][MacType].GetOffset) { - continue; } @@ -1892,9 +1430,7 @@ SK_EVPARA Param) /* Event dependent parameter */ pAC->Pnmi.VirtualCounterOffset[CounterIndex] += Value; } - /* - * Set port to inactive - */ + /* Set port to inactive. */ pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_FALSE; pAC->Pnmi.MacUpdatedFlag --; @@ -1918,26 +1454,21 @@ SK_EVPARA Param) /* Event dependent parameter */ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, NetIndex=%d\n", NetIndex)); } -#endif - /* - * For now, ignore event if NetIndex != 0. - */ +#endif /* DEBUG */ + + /* For now, ignore event if NetIndex != 0. */ if (Param.Para32[1] != 0) { return (0); } - /* - * Nothing to do if port is already active - */ + /* Nothing to do if port is already inactive. */ if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { return (0); } - /* - * Statistic maintenance - */ + /* Statistic maintenance. */ pAC->Pnmi.RlmtChangeCts ++; pAC->Pnmi.RlmtChangeTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC)); @@ -1971,7 +1502,6 @@ SK_EVPARA Param) /* Event dependent parameter */ CounterIndex ++) { if (!StatAddr[CounterIndex][MacType].GetOffset) { - continue; } @@ -1980,18 +1510,14 @@ SK_EVPARA Param) /* Event dependent parameter */ pAC->Pnmi.VirtualCounterOffset[CounterIndex] -= Value; } - /* - * Set port to active - */ + /* Set port to active. */ pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_TRUE; pAC->Pnmi.MacUpdatedFlag --; break; case SK_PNMI_EVT_RLMT_SEGMENTATION: - /* - * Para.Para32[0] contains the NetIndex. - */ + /* Para.Para32[0] contains the NetIndex. */ /* * Store a trap message in the trap buffer and generate an event for @@ -2006,65 +1532,56 @@ SK_EVPARA Param) /* Event dependent parameter */ * Param.Para32[0] contains the number of Nets. * Param.Para32[1] is reserved, contains -1. */ - /* - * Check number of nets - */ + /* Check number of nets. */ MaxNetNumber = pAC->GIni.GIMacsFound; - if (((unsigned int)Param.Para32[0] < 1) - || ((unsigned int)Param.Para32[0] > MaxNetNumber)) { + + if (((unsigned int)Param.Para32[0] < 1) || + ((unsigned int)Param.Para32[0] > MaxNetNumber)) { + return (SK_PNMI_ERR_UNKNOWN_NET); } - if ((unsigned int)Param.Para32[0] == 1) { /* single net mode */ - pAC->Pnmi.DualNetActiveFlag = SK_FALSE; - } - else { /* dual net mode */ - pAC->Pnmi.DualNetActiveFlag = SK_TRUE; - } - break; + if ((unsigned int)Param.Para32[0] == 1) { /* SingleNet mode. */ + pAC->Pnmi.DualNetActiveFlag = SK_FALSE; + } + else { /* DualNet mode. */ + pAC->Pnmi.DualNetActiveFlag = SK_TRUE; + } + break; case SK_PNMI_EVT_VCT_RESET: - PhysPortIndex = Param.Para32[0]; - pPrt = &pAC->GIni.GP[PhysPortIndex]; - pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex]; - - if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) { - RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE); - if (RetCode == 2) { - /* - * VCT test is still running. - * Start VCT timer counter again. - */ - SK_MEMSET((char *) &Param, 0, sizeof(Param)); - Param.Para32[0] = PhysPortIndex; - Param.Para32[1] = -1; - SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer, - 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param); - break; - } - pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING; - pAC->Pnmi.VctStatus[PhysPortIndex] |= - (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE); - - /* Copy results for later use to PNMI struct. */ - for (i = 0; i < 4; i++) { - if (pPrt->PMdiPairLen[i] > 35) { - CableLength = 1000 * (((175 * pPrt->PMdiPairLen[i]) / 210) - 28); + PhysPortIndex = Param.Para32[0]; + + if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) { + + RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE); + + if (RetCode == 2) { + /* + * VCT test is still running. + * Start VCT timer counter again. + */ + SK_MEMSET((char *)&Param, 0, sizeof(Param)); + + Param.Para32[0] = PhysPortIndex; + Param.Para32[1] = -1; + + SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex], + SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param); + + break; } - else { - CableLength = 0; - } - pVctBackupData->PMdiPairLen[i] = CableLength; - pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i]; + + VctGetResults(pAC, IoC, PhysPortIndex); + + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = -1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, EventParam); + + /* SkEventDispatcher(pAC, IoC); */ } - - Param.Para32[0] = PhysPortIndex; - Param.Para32[1] = -1; - SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Param); - SkEventDispatcher(pAC, IoC); - } - - break; + + break; default: break; @@ -2092,33 +1609,30 @@ SK_EVPARA Param) /* Event dependent parameter */ * SkGePnmiPreSetVar, or SkGePnmiSetVar. * * Returns: - * SK_PNMI_ERR_XXX. For details have a look to the description of the + * SK_PNMI_ERR_XXX. For details have a look at the description of the * calling functions. * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist */ PNMI_STATIC int PnmiVar( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer which stores the mgmt data to be set */ -unsigned int *pLen, /* Total length of mgmt data */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* Total length of pBuf management data */ SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { unsigned int TableIndex; int Ret; - if ((TableIndex = LookupId(Id)) == (unsigned int)(-1)) { *pLen = 0; return (SK_PNMI_ERR_UNKNOWN_OID); } - - /* - * Check NetIndex - */ + + /* Check NetIndex. */ if (NetIndex >= pAC->Rlmt.NumNets) { return (SK_PNMI_ERR_UNKNOWN_NET); } @@ -2154,10 +1668,10 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ PNMI_STATIC int PnmiStruct( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Set action to be performed */ -char *pBuf, /* Buffer which contains the data to be set */ -unsigned int *pLen, /* Length of buffer */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +int Action, /* PRESET/SET action to be performed */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* Length of pBuf management data buffer */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { int Ret; unsigned int TableIndex; @@ -2168,28 +1682,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ SK_U32 Instance; SK_U32 Id; - - /* Check if the passed buffer has the right size */ + /* Check if the passed buffer has the right size. */ if (*pLen < SK_PNMI_STRUCT_SIZE) { - /* Check if we can return the error within the buffer */ + /* Check if we can return the error within the buffer. */ if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) { - SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, - (SK_U32)(-1)); + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1)); } *pLen = SK_PNMI_STRUCT_SIZE; return (SK_PNMI_ERR_TOO_SHORT); } - - /* - * Check NetIndex - */ + + /* Check NetIndex. */ if (NetIndex >= pAC->Rlmt.NumNets) { return (SK_PNMI_ERR_UNKNOWN_NET); } - + SK_PNMI_CHECKFLAGS("PnmiStruct: On call"); /* @@ -2213,12 +1723,11 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ pAC->Pnmi.RlmtUpdatedFlag ++; pAC->Pnmi.SirqUpdatedFlag ++; - /* Preset/Set values */ + /* PRESET/SET values. */ for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) { if ((IdTable[TableIndex].Access != SK_PNMI_RW) && (IdTable[TableIndex].Access != SK_PNMI_WO)) { - continue; } @@ -2229,8 +1738,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ InstanceCnt ++) { DstOffset = IdTable[TableIndex].Offset + - (InstanceCnt - 1) * - IdTable[TableIndex].StructSize; + (InstanceCnt - 1) * IdTable[TableIndex].StructSize; /* * Because VPD multiple instance variables are @@ -2240,9 +1748,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ */ Instance = (SK_U32)InstanceCnt; - /* - * Evaluate needed buffer length - */ + /* Evaluate needed buffer length. */ Len = 0; Ret = IdTable[TableIndex].Func(pAC, IoC, SK_PNMI_GET, IdTable[TableIndex].Id, @@ -2258,8 +1764,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ pAC->Pnmi.SirqUpdatedFlag --; SK_PNMI_CHECKFLAGS("PnmiStruct: On return"); - SK_PNMI_SET_STAT(pBuf, - SK_PNMI_ERR_GENERAL, DstOffset); + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_GENERAL, DstOffset); *pLen = SK_PNMI_MIN_STRUCT_SIZE; return (SK_PNMI_ERR_GENERAL); } @@ -2281,7 +1786,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } } - /* Call the OID handler function */ + /* Call the OID handler function. */ Ret = IdTable[TableIndex].Func(pAC, IoC, Action, IdTable[TableIndex].Id, pBuf + DstOffset, &Len, Instance, TableIndex, NetIndex); @@ -2292,8 +1797,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ pAC->Pnmi.SirqUpdatedFlag --; SK_PNMI_CHECKFLAGS("PnmiStruct: On return"); - SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE, - DstOffset); + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE, DstOffset); *pLen = SK_PNMI_MIN_STRUCT_SIZE; return (SK_PNMI_ERR_BAD_VALUE); } @@ -2327,7 +1831,7 @@ SK_U32 Id) /* Object identifier to be searched */ if (IdTable[i].Id == Id) { - return i; + return (i); } } @@ -2352,32 +1856,29 @@ SK_U32 Id) /* Object identifier to be searched */ * value range. * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int OidStruct( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { if (Id != OID_SKGE_ALL_DATA) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003, - SK_PNMI_ERR003MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003, SK_PNMI_ERR003MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); } - /* - * Check instance. We only handle single instance variables - */ + /* Check instance. We only handle single instance variables. */ if (Instance != (SK_U32)(-1) && Instance != 1) { *pLen = 0; @@ -2419,27 +1920,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * value range. * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int Perform( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { int Ret; SK_U32 ActionOp; - - /* - * Check instance. We only handle single instance variables - */ + /* Check instance. We only handle single instance variables. */ if (Instance != (SK_U32)(-1) && Instance != 1) { *pLen = 0; @@ -2452,10 +1950,10 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_TOO_SHORT); } - /* Check if a get should be performed */ + /* Check if a GET should be performed. */ if (Action == SK_PNMI_GET) { - /* A get is easy. We always return the same value */ + /* A GET is easy. We always return the same value. */ ActionOp = (SK_U32)SK_PNMI_ACT_IDLE; SK_PNMI_STORE_U32(pBuf, ActionOp); *pLen = sizeof(SK_U32); @@ -2463,13 +1961,13 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_OK); } - /* Continue with PRESET/SET action */ + /* Continue with PRESET/SET action. */ if (*pLen > sizeof(SK_U32)) { return (SK_PNMI_ERR_BAD_VALUE); } - /* Check if the command is a known one */ + /* Check if the command is a known one. */ SK_PNMI_READ_U32(pBuf, ActionOp); if (*pLen > sizeof(SK_U32) || (ActionOp != SK_PNMI_ACT_IDLE && @@ -2481,7 +1979,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_BAD_VALUE); } - /* A preset ends here */ + /* A PRESET ends here. */ if (Action == SK_PNMI_PRESET) { return (SK_PNMI_ERR_OK); @@ -2490,19 +1988,15 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ switch (ActionOp) { case SK_PNMI_ACT_IDLE: - /* Nothing to do */ + /* Nothing to do. */ break; case SK_PNMI_ACT_RESET: - /* - * Perform a driver reset or something that comes near - * to this. - */ + /* Perform a driver reset or something that comes near to this. */ Ret = SK_DRIVER_RESET(pAC, IoC); if (Ret != 0) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005, - SK_PNMI_ERR005MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005, SK_PNMI_ERR005MSG); return (SK_PNMI_ERR_GENERAL); } @@ -2519,13 +2013,12 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case SK_PNMI_ACT_RESETCNT: - /* Set all counters and timestamps to zero */ + /* Set all counters and timestamps to zero. */ ResetCounter(pAC, IoC, NetIndex); break; default: - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006, - SK_PNMI_ERR006MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006, SK_PNMI_ERR006MSG); return (SK_PNMI_ERR_GENERAL); } @@ -2550,46 +2043,40 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * the correct data (e.g. a 32bit value is * needed, but a 16 bit value was passed). * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int Mac8023Stat( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { int Ret; SK_U64 StatVal; SK_U32 StatVal32; SK_BOOL Is64BitReq = SK_FALSE; - /* - * Only the active Mac is returned - */ + /* Only the active MAC is returned. */ if (Instance != (SK_U32)(-1) && Instance != 1) { *pLen = 0; return (SK_PNMI_ERR_UNKNOWN_INST); } - /* - * Check action type - */ + /* Check action type. */ if (Action != SK_PNMI_GET) { *pLen = 0; return (SK_PNMI_ERR_READ_ONLY); } - /* - * Check length - */ + /* Check length. */ switch (Id) { case OID_802_3_PERMANENT_ADDRESS: @@ -2610,14 +2097,12 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ #else /* SK_NDIS_64BIT_CTR */ - /* - * for compatibility, at least 32bit are required for oid - */ + /* For compatibility, at least 32 bits are required for OID. */ if (*pLen < sizeof(SK_U32)) { /* - * but indicate handling for 64bit values, - * if insufficient space is provided - */ + * Indicate handling for 64 bit values, + * if insufficient space is provided. + */ *pLen = sizeof(SK_U64); return (SK_PNMI_ERR_TOO_SHORT); } @@ -2633,16 +2118,14 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * to indicate that an update was already done. */ Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1); - if ( Ret != SK_PNMI_ERR_OK) { + if (Ret != SK_PNMI_ERR_OK) { *pLen = 0; return (Ret); } pAC->Pnmi.MacUpdatedFlag ++; - /* - * Get value (MAC Index 0 identifies the virtual MAC) - */ + /* Get value (MAC index 0 identifies the virtual MAC). */ switch (Id) { case OID_802_3_PERMANENT_ADDRESS: @@ -2658,9 +2141,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ default: StatVal = GetStatVal(pAC, IoC, 0, IdTable[TableIndex].Param, NetIndex); - /* - * by default 32bit values are evaluated - */ + /* By default 32 bit values are evaluated. */ if (!Is64BitReq) { StatVal32 = (SK_U32)StatVal; SK_PNMI_STORE_U32(pBuf, StatVal32); @@ -2683,7 +2164,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * MacPrivateStat - OID handler function of OID_SKGE_STAT_XXX * * Description: - * Retrieves the XMAC statistic data. + * Retrieves the MAC statistic data. * * Returns: * SK_PNMI_ERR_OK The request was successfully performed. @@ -2692,42 +2173,41 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * the correct data (e.g. a 32bit value is * needed, but a 16 bit value was passed). * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int MacPrivateStat( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { unsigned int LogPortMax; unsigned int LogPortIndex; unsigned int PhysPortMax; unsigned int Limit; unsigned int Offset; + int MacType; int Ret; SK_U64 StatVal; - - /* - * Calculate instance if wished. MAC index 0 is the virtual - * MAC. - */ + /* Calculate instance if wished. MAC index 0 is the virtual MAC. */ PhysPortMax = pAC->GIni.GIMacsFound; LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); + + MacType = pAC->GIni.GIMacType; - if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */ LogPortMax--; } - if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */ - /* Check instance range */ + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */ + /* Check instance range. */ if ((Instance < 1) || (Instance > LogPortMax)) { *pLen = 0; @@ -2737,25 +2217,20 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Limit = LogPortIndex + 1; } - else { /* Instance == (SK_U32)(-1), get all Instances of that OID */ + else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */ LogPortIndex = 0; Limit = LogPortMax; } - - /* - * Check action - */ + /* Check action. */ if (Action != SK_PNMI_GET) { *pLen = 0; return (SK_PNMI_ERR_READ_ONLY); } - /* - * Check length - */ + /* Check length. */ if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U64)) { *pLen = (Limit - LogPortIndex) * sizeof(SK_U64); @@ -2763,7 +2238,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } /* - * Update XMAC statistic and increment semaphore to indicate that + * Update MAC statistic and increment semaphore to indicate that * an update was already done. */ Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1); @@ -2774,9 +2249,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } pAC->Pnmi.MacUpdatedFlag ++; - /* - * Get value - */ + /* Get value. */ Offset = 0; for (; LogPortIndex < Limit; LogPortIndex ++) { @@ -2791,51 +2264,44 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_GENERAL); */ case OID_SKGE_STAT_RX: - case OID_SKGE_STAT_TX: - switch (pAC->GIni.GIMacType) { - case SK_MAC_XMAC: + if (MacType == SK_MAC_GMAC) { + StatVal = + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_BROADCAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_MULTICAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_UNICAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_UNDERSIZE, NetIndex); + } + else { StatVal = GetStatVal(pAC, IoC, LogPortIndex, IdTable[TableIndex].Param, NetIndex); - break; - - case SK_MAC_GMAC: - if (Id == OID_SKGE_STAT_TX) { - - StatVal = - GetStatVal(pAC, IoC, LogPortIndex, - SK_PNMI_HTX_BROADCAST, NetIndex) + - GetStatVal(pAC, IoC, LogPortIndex, - SK_PNMI_HTX_MULTICAST, NetIndex) + - GetStatVal(pAC, IoC, LogPortIndex, - SK_PNMI_HTX_UNICAST, NetIndex); - } - else { - StatVal = - GetStatVal(pAC, IoC, LogPortIndex, - SK_PNMI_HRX_BROADCAST, NetIndex) + - GetStatVal(pAC, IoC, LogPortIndex, - SK_PNMI_HRX_MULTICAST, NetIndex) + - GetStatVal(pAC, IoC, LogPortIndex, - SK_PNMI_HRX_UNICAST, NetIndex) + - GetStatVal(pAC, IoC, LogPortIndex, - SK_PNMI_HRX_UNDERSIZE, NetIndex); - } - break; - - default: - StatVal = 0; - break; } + break; - SK_PNMI_STORE_U64(pBuf + Offset, StatVal); + case OID_SKGE_STAT_TX: + if (MacType == SK_MAC_GMAC) { + StatVal = + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HTX_BROADCAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HTX_MULTICAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HTX_UNICAST, NetIndex); + } + else { + StatVal = GetStatVal(pAC, IoC, LogPortIndex, + IdTable[TableIndex].Param, NetIndex); + } break; default: StatVal = GetStatVal(pAC, IoC, LogPortIndex, IdTable[TableIndex].Param, NetIndex); - SK_PNMI_STORE_U64(pBuf + Offset, StatVal); - break; } + SK_PNMI_STORE_U64(pBuf + Offset, StatVal); Offset += sizeof(SK_U64); } @@ -2867,19 +2333,19 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * value range. * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int Addr( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { int Ret; unsigned int LogPortMax; @@ -2889,19 +2355,16 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ unsigned int Limit; unsigned int Offset = 0; - /* - * Calculate instance if wished. MAC index 0 is the virtual - * MAC. - */ + /* Calculate instance if wished. MAC index 0 is the virtual MAC. */ PhysPortMax = pAC->GIni.GIMacsFound; LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); - if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */ LogPortMax--; } - if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */ - /* Check instance range */ + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */ + /* Check instance range. */ if ((Instance < 1) || (Instance > LogPortMax)) { *pLen = 0; @@ -2910,30 +2373,23 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance); Limit = LogPortIndex + 1; } - - else { /* Instance == (SK_U32)(-1), get all Instances of that OID */ + else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */ LogPortIndex = 0; Limit = LogPortMax; } - /* - * Perform Action - */ + /* Perform action. */ if (Action == SK_PNMI_GET) { - /* - * Check length - */ + /* Check length. */ if (*pLen < (Limit - LogPortIndex) * 6) { *pLen = (Limit - LogPortIndex) * 6; return (SK_PNMI_ERR_TOO_SHORT); } - /* - * Get value - */ + /* Get value. */ for (; LogPortIndex < Limit; LogPortIndex ++) { switch (Id) { @@ -2957,8 +2413,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ &pAC->Addr.Net[NetIndex].PermanentMacAddress); } else { - PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( - pAC, LogPortIndex); + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex); CopyMac(pBuf + Offset, &pAC->Addr.Port[PhysPortIndex].PermanentMacAddress); @@ -2967,8 +2422,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; default: - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008, - SK_PNMI_ERR008MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008, SK_PNMI_ERR008MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -2979,8 +2433,8 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } else { /* - * The logical MAC address may not be changed only - * the physical ones + * The logical MAC address may not be changed, + * only the physical ones. */ if (Id == OID_SKGE_PHYS_FAC_ADDR) { @@ -2988,21 +2442,16 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_READ_ONLY); } - /* - * Only the current address may be changed - */ + /* Only the current address may be changed. */ if (Id != OID_SKGE_PHYS_CUR_ADDR) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009, - SK_PNMI_ERR009MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009, SK_PNMI_ERR009MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); } - /* - * Check length - */ + /* Check length. */ if (*pLen < (Limit - LogPortIndex) * 6) { *pLen = (Limit - LogPortIndex) * 6; @@ -3014,32 +2463,26 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_BAD_VALUE); } - /* - * Check Action - */ + /* Check action. */ if (Action == SK_PNMI_PRESET) { *pLen = 0; return (SK_PNMI_ERR_OK); } - /* - * Set OID_SKGE_MAC_CUR_ADDR - */ + /* Set OID_SKGE_MAC_CUR_ADDR. */ for (; LogPortIndex < Limit; LogPortIndex ++, Offset += 6) { /* * A set to virtual port and set of broadcast - * address will be ignored + * address will be ignored. */ if (LogPortIndex == 0 || SK_MEMCMP(pBuf + Offset, "\xff\xff\xff\xff\xff\xff", 6) == 0) { - continue; } - PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, - LogPortIndex); + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex); Ret = SkAddrOverride(pAC, IoC, PhysPortIndex, (SK_MAC_ADDR *)(pBuf + Offset), @@ -3073,29 +2516,26 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * the correct data (e.g. a 32bit value is * needed, but a 16 bit value was passed). * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int CsumStat( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { unsigned int Index; unsigned int Limit; unsigned int Offset = 0; SK_U64 StatVal; - - /* - * Calculate instance if wished - */ + /* Calculate instance if wished. */ if (Instance != (SK_U32)(-1)) { if ((Instance < 1) || (Instance > SKCS_NUM_PROTOCOLS)) { @@ -3111,27 +2551,21 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Limit = SKCS_NUM_PROTOCOLS; } - /* - * Check action - */ + /* Check action. */ if (Action != SK_PNMI_GET) { *pLen = 0; return (SK_PNMI_ERR_READ_ONLY); } - /* - * Check length - */ + /* Check length. */ if (*pLen < (Limit - Index) * sizeof(SK_U64)) { *pLen = (Limit - Index) * sizeof(SK_U64); return (SK_PNMI_ERR_TOO_SHORT); } - /* - * Get value - */ + /* Get value. */ for (; Index < Limit; Index ++) { switch (Id) { @@ -3157,8 +2591,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; default: - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010, - SK_PNMI_ERR010MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010, SK_PNMI_ERR010MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -3168,9 +2601,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Offset += sizeof(SK_U64); } - /* - * Store used buffer space - */ + /* Store used buffer space. */ *pLen = Offset; return (SK_PNMI_ERR_OK); @@ -3191,19 +2622,19 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * the correct data (e.g. a 32bit value is * needed, but a 16 bit value was passed). * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int SensorStat( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { unsigned int i; unsigned int Index; @@ -3213,10 +2644,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ SK_U32 Val32; SK_U64 Val64; - - /* - * Calculate instance if wished - */ + /* Calculate instance if wished. */ if ((Instance != (SK_U32)(-1))) { if ((Instance < 1) || (Instance > (SK_U32)pAC->I2c.MaxSens)) { @@ -3233,18 +2661,14 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Limit = (unsigned int) pAC->I2c.MaxSens; } - /* - * Check action - */ + /* Check action. */ if (Action != SK_PNMI_GET) { *pLen = 0; return (SK_PNMI_ERR_READ_ONLY); } - /* - * Check length - */ + /* Check length. */ switch (Id) { case OID_SKGE_SENSOR_VALUE: @@ -3303,38 +2727,33 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; default: - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012, - SK_PNMI_ERR012MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012, SK_PNMI_ERR012MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); } - /* - * Get value - */ + /* Get value. */ for (Offset = 0; Index < Limit; Index ++) { switch (Id) { case OID_SKGE_SENSOR_INDEX: *(pBuf + Offset) = (char)Index; - Offset += sizeof(char); + Offset ++; break; case OID_SKGE_SENSOR_DESCR: Len = SK_STRLEN(pAC->I2c.SenTable[Index].SenDesc); - SK_MEMCPY(pBuf + Offset + 1, - pAC->I2c.SenTable[Index].SenDesc, Len); + SK_MEMCPY(pBuf + Offset + 1, pAC->I2c.SenTable[Index].SenDesc, Len); *(pBuf + Offset) = (char)Len; Offset += Len + 1; break; case OID_SKGE_SENSOR_TYPE: - *(pBuf + Offset) = - (char)pAC->I2c.SenTable[Index].SenType; - Offset += sizeof(char); + *(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenType; + Offset ++; break; case OID_SKGE_SENSOR_VALUE: @@ -3371,9 +2790,8 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_SENSOR_STATUS: - *(pBuf + Offset) = - (char)pAC->I2c.SenTable[Index].SenErrFlag; - Offset += sizeof(char); + *(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenErrFlag; + Offset ++; break; case OID_SKGE_SENSOR_WAR_CTS: @@ -3410,9 +2828,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } } - /* - * Store used buffer space - */ + /* Store used buffer space. */ *pLen = Offset; return (SK_PNMI_ERR_OK); @@ -3438,19 +2854,19 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * value range. * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int Vpd( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { SK_VPD_STATUS *pVpdStatus; unsigned int BufLen; @@ -3467,10 +2883,30 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ SK_U32 Val32; /* - * Get array of all currently stored VPD keys - */ - Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), - &KeyNo); + * VpdKeyReadError will be set in GetVpdKeyArr() if an error occurs. + * Due to the fact that some drivers use SkPnmiGetStruct() to retrieve + * all statistical data, an error in GetVpdKeyArr() will generate a PNMI + * error and terminate SkPnmiGetStruct() without filling in statistical + * data into the PNMI struct. In this case the driver will get no values + * for statistical purposes (netstat, ifconfig etc.). GetVpdKeyArr() is + * the first function to be called in SkPnmiGetStruct(), so any error + * will terminate SkPnmiGetStruct() immediately. Hence, VpdKeyReadError will + * be set during the first call to GetVpdKeyArr() to make successful calls + * to SkPnmiGetStruct() possible. But there is another point to consider: + * When filling in the statistical data into the PNMI struct, the VPD + * handler Vpd() will also be called. If GetVpdKeyArr() in Vpd() would + * return with SK_PNMI_ERR_GENERAL, SkPnmiGetStruct() would fail again. + * For this reason VpdKeyReadError is checked here and, if set, Vpd() + * will return without doing anything and the return value SK_PNMI_ERR_OK. + * Therefore SkPnmiGetStruct() is able to continue and fill in all other + * statistical data. + */ + if (pAC->Pnmi.VpdKeyReadError == SK_TRUE) { + return (SK_PNMI_ERR_OK); + } + + /* Get array of all currently stored VPD keys. */ + Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &KeyNo); if (Ret != SK_PNMI_ERR_OK) { *pLen = 0; return (Ret); @@ -3514,46 +2950,44 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } } - /* - * Get value, if a query should be performed - */ + /* Get value, if a query should be performed. */ if (Action == SK_PNMI_GET) { switch (Id) { case OID_SKGE_VPD_FREE_BYTES: - /* Check length of buffer */ + /* Check length of buffer. */ if (*pLen < sizeof(SK_U32)) { *pLen = sizeof(SK_U32); return (SK_PNMI_ERR_TOO_SHORT); } - /* Get number of free bytes */ + /* Get number of free bytes. */ pVpdStatus = VpdStat(pAC, IoC); if (pVpdStatus == NULL) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR017, - SK_PNMI_ERR017MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR017MSG)); *pLen = 0; return (SK_PNMI_ERR_GENERAL); } if ((pVpdStatus->vpd_status & VPD_VALID) == 0) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR018, - SK_PNMI_ERR018MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR018MSG)); *pLen = 0; return (SK_PNMI_ERR_GENERAL); } - + Val32 = (SK_U32)pVpdStatus->vpd_free_rw; SK_PNMI_STORE_U32(pBuf, Val32); *pLen = sizeof(SK_U32); break; case OID_SKGE_VPD_ENTRIES_LIST: - /* Check length */ + /* Check length. */ for (Len = 0, Index = 0; Index < KeyNo; Index ++) { Len += SK_STRLEN(KeyArr[Index]) + 1; @@ -3564,7 +2998,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_TOO_SHORT); } - /* Get value */ + /* Get value. */ *(pBuf) = (char)Len - 1; for (Offset = 1, Index = 0; Index < KeyNo; Index ++) { @@ -3583,7 +3017,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_VPD_ENTRIES_NUMBER: - /* Check length */ + /* Check length. */ if (*pLen < sizeof(SK_U32)) { *pLen = sizeof(SK_U32); @@ -3596,7 +3030,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_VPD_KEY: - /* Check buffer length, if it is large enough */ + /* Check buffer length, if it is large enough. */ for (Len = 0, Index = FirstIndex; Index < LastIndex; Index ++) { @@ -3612,32 +3046,28 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * Get the key to an intermediate buffer, because * we have to prepend a length byte. */ - for (Offset = 0, Index = FirstIndex; - Index < LastIndex; Index ++) { + for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) { Len = SK_STRLEN(KeyArr[Index]); *(pBuf + Offset) = (char)Len; - SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index], - Len); + SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index], Len); Offset += Len + 1; } *pLen = Offset; break; case OID_SKGE_VPD_VALUE: - /* Check the buffer length if it is large enough */ - for (Offset = 0, Index = FirstIndex; - Index < LastIndex; Index ++) { + /* Check the buffer length if it is large enough. */ + for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) { BufLen = 256; if (VpdRead(pAC, IoC, KeyArr[Index], Buf, (int *)&BufLen) > 0 || BufLen >= SK_PNMI_VPD_DATALEN) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, - SK_PNMI_ERR021, - SK_PNMI_ERR021MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR021MSG)); return (SK_PNMI_ERR_GENERAL); } @@ -3653,17 +3083,15 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * Get the value to an intermediate buffer, because * we have to prepend a length byte. */ - for (Offset = 0, Index = FirstIndex; - Index < LastIndex; Index ++) { + for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) { BufLen = 256; if (VpdRead(pAC, IoC, KeyArr[Index], Buf, (int *)&BufLen) > 0 || BufLen >= SK_PNMI_VPD_DATALEN) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, - SK_PNMI_ERR022, - SK_PNMI_ERR022MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR022MSG)); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -3683,8 +3111,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_TOO_SHORT); } - for (Offset = 0, Index = FirstIndex; - Index < LastIndex; Index ++) { + for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) { if (VpdMayWrite(KeyArr[Index])) { @@ -3710,15 +3137,15 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; default: - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR023, - SK_PNMI_ERR023MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR023MSG)); *pLen = 0; return (SK_PNMI_ERR_GENERAL); } } else { - /* The only OID which can be set is VPD_ACTION */ + /* The only OID which can be set is VPD_ACTION. */ if (Id != OID_SKGE_VPD_ACTION) { if (Id == OID_SKGE_VPD_FREE_BYTES || @@ -3732,8 +3159,8 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_READ_ONLY); } - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR024, - SK_PNMI_ERR024MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR024MSG)); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -3749,14 +3176,11 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_TOO_SHORT); } - /* - * The first byte contains the VPD action type we should - * perform. - */ + /* The first byte contains the VPD action type we should perform. */ switch (*pBuf) { case SK_PNMI_VPD_IGNORE: - /* Nothing to do */ + /* Nothing to do. */ break; case SK_PNMI_VPD_CREATE: @@ -3788,13 +3212,13 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ SK_MEMCPY(Buf, pBuf + 4, Offset); Buf[Offset] = 0; - /* A preset ends here */ + /* A PRESET ends here. */ if (Action == SK_PNMI_PRESET) { return (SK_PNMI_ERR_OK); } - /* Write the new entry or modify an existing one */ + /* Write the new entry or modify an existing one .*/ Ret = VpdWrite(pAC, IoC, KeyStr, Buf); if (Ret == SK_PNMI_VPD_NOWRITE ) { @@ -3803,8 +3227,8 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } else if (Ret != SK_PNMI_VPD_OK) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR025, - SK_PNMI_ERR025MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR025MSG)); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -3817,8 +3241,8 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Ret = VpdUpdate(pAC, IoC); if (Ret != SK_PNMI_VPD_OK) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR026, - SK_PNMI_ERR026MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR026MSG)); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -3826,7 +3250,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case SK_PNMI_VPD_DELETE: - /* Check if the buffer size is plausible */ + /* Check if the buffer size is plausible. */ if (*pLen < 3) { *pLen = 3; @@ -3841,7 +3265,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ KeyStr[1] = pBuf[2]; KeyStr[2] = 0; - /* Find the passed key in the array */ + /* Find the passed key in the array. */ for (Index = 0; Index < KeyNo; Index ++) { if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) { @@ -3849,6 +3273,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; } } + /* * If we cannot find the key it is wrong, so we * return an appropriate error value. @@ -3864,12 +3289,12 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_OK); } - /* Ok, you wanted it and you will get it */ + /* Ok, you wanted it and you will get it. */ Ret = VpdDelete(pAC, IoC, KeyStr); if (Ret != SK_PNMI_VPD_OK) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR027, - SK_PNMI_ERR027MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR027MSG)); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -3882,8 +3307,8 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Ret = VpdUpdate(pAC, IoC); if (Ret != SK_PNMI_VPD_OK) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR028, - SK_PNMI_ERR028MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR028MSG)); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -3913,19 +3338,19 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * the correct data (e.g. a 32bit value is * needed, but a 16 bit value was passed). * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int General( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +char *pBuf, /* Buffer used for the management data transfer */ unsigned int *pLen, /* On call: buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { int Ret; unsigned int Index; @@ -3937,34 +3362,30 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ SK_U32 Val32; SK_U64 Val64; SK_U64 Val64RxHwErrs = 0; + SK_U64 Val64RxRunt = 0; + SK_U64 Val64RxFcs = 0; SK_U64 Val64TxHwErrs = 0; SK_BOOL Is64BitReq = SK_FALSE; char Buf[256]; int MacType; - /* - * Check instance. We only handle single instance variables - */ + /* Check instance. We only handle single instance variables. */ if (Instance != (SK_U32)(-1) && Instance != 1) { *pLen = 0; return (SK_PNMI_ERR_UNKNOWN_INST); } - /* - * Check action. We only allow get requests. - */ + /* Check action. We only allow get requests. */ if (Action != SK_PNMI_GET) { *pLen = 0; return (SK_PNMI_ERR_READ_ONLY); } - + MacType = pAC->GIni.GIMacType; - - /* - * Check length for the various supported OIDs - */ + + /* Check length for the various supported OIDs. */ switch (Id) { case OID_GEN_XMIT_ERROR: @@ -3978,14 +3399,12 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ #else /* SK_NDIS_64BIT_CTR */ - /* - * for compatibility, at least 32bit are required for oid - */ + /* For compatibility, at least 32bit are required for OID. */ if (*pLen < sizeof(SK_U32)) { /* - * but indicate handling for 64bit values, - * if insufficient space is provided - */ + * Indicate handling for 64bit values, + * if insufficient space is provided. + */ *pLen = sizeof(SK_U64); return (SK_PNMI_ERR_TOO_SHORT); } @@ -4001,6 +3420,9 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ case OID_GEN_TRANSMIT_QUEUE_LENGTH: case OID_SKGE_TRAP_NUMBER: case OID_SKGE_MDB_VERSION: + case OID_SKGE_BOARDLEVEL: + case OID_SKGE_CHIPID: + case OID_SKGE_RAMSIZE: if (*pLen < sizeof(SK_U32)) { *pLen = sizeof(SK_U32); @@ -4021,6 +3443,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ case OID_SKGE_BUS_WIDTH: case OID_SKGE_SENSOR_NUMBER: case OID_SKGE_CHKSM_NUMBER: + case OID_SKGE_VAUXAVAIL: if (*pLen < sizeof(SK_U8)) { *pLen = sizeof(SK_U8); @@ -4052,11 +3475,11 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; default: - /* Checked later */ + /* Checked later. */ break; } - /* Update statistic */ + /* Update statistics. */ if (Id == OID_SKGE_RX_HW_ERROR_CTS || Id == OID_SKGE_TX_HW_ERROR_CTS || Id == OID_SKGE_IN_ERRORS_CTS || @@ -4064,7 +3487,8 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Id == OID_GEN_XMIT_ERROR || Id == OID_GEN_RCV_ERROR) { - /* Force the XMAC to update its statistic counters and + /* + * Force the XMAC to update its statistic counters and * Increment semaphore to indicate that an update was * already done. */ @@ -4089,33 +3513,46 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Val64RxHwErrs = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_MISSED, NetIndex) + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FRAMING, NetIndex) + - GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex)+ + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex) + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_JABBER, NetIndex) + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CARRIER, NetIndex) + - GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_IRLENGTH, NetIndex)+ + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_IRLENGTH, NetIndex) + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SYMBOL, NetIndex) + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SHORTS, NetIndex) + - GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex) + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_TOO_LONG, NetIndex) + - GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex) + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CEXT, NetIndex); - break; + + + /* + * In some cases the runt and fcs counters are incremented when collisions + * occur. We have to correct those counters here. + */ + Val64RxRunt = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex); + Val64RxFcs = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex); + + if (Val64RxRunt > Val64RxFcs) { + Val64RxRunt -= Val64RxFcs; + Val64RxHwErrs += Val64RxRunt; + } + else { + Val64RxFcs -= Val64RxRunt; + Val64RxHwErrs += Val64RxFcs; + } + break; case OID_SKGE_TX_HW_ERROR_CTS: case OID_SKGE_OUT_ERROR_CTS: case OID_GEN_XMIT_ERROR: Val64TxHwErrs = GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_EXCESS_COL, NetIndex) + - GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_LATE_COL, NetIndex)+ - GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_UNDERRUN, NetIndex)+ + GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_LATE_COL, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_UNDERRUN, NetIndex) + GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_CARRIER, NetIndex); break; } } - /* - * Retrieve value - */ + /* Retrieve value. */ switch (Id) { case OID_SKGE_SUPPORTED_LIST: @@ -4125,15 +3562,21 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ *pLen = Len; return (SK_PNMI_ERR_TOO_SHORT); } - for (Offset = 0, Index = 0; Offset < Len; - Offset += sizeof(SK_U32), Index ++) { + for (Offset = 0, Index = 0; Offset < Len; Index ++) { Val32 = (SK_U32)IdTable[Index].Id; SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); } *pLen = Len; break; + case OID_SKGE_BOARDLEVEL: + Val32 = (SK_U32)pAC->GIni.GILevel; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + case OID_SKGE_PORT_NUMBER: Val32 = (SK_U32)pAC->GIni.GIMacsFound; SK_PNMI_STORE_U32(pBuf, Val32); @@ -4149,8 +3592,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ case OID_SKGE_DRIVER_DESCR: if (pAC->Pnmi.pDriverDescription == NULL) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007, - SK_PNMI_ERR007MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007, SK_PNMI_ERR007MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -4159,8 +3601,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Len = SK_STRLEN(pAC->Pnmi.pDriverDescription) + 1; if (Len > SK_PNMI_STRINGLEN1) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029, - SK_PNMI_ERR029MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029, SK_PNMI_ERR029MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -4179,8 +3620,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ case OID_SKGE_DRIVER_VERSION: if (pAC->Pnmi.pDriverVersion == NULL) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030, - SK_PNMI_ERR030MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030, SK_PNMI_ERR030MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -4189,8 +3629,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Len = SK_STRLEN(pAC->Pnmi.pDriverVersion) + 1; if (Len > SK_PNMI_STRINGLEN1) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031, - SK_PNMI_ERR031MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031, SK_PNMI_ERR031MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -4206,18 +3645,78 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ *pLen = Len; break; + case OID_SKGE_DRIVER_RELDATE: + if (pAC->Pnmi.pDriverReleaseDate == NULL) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR053, SK_PNMI_ERR053MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + Len = SK_STRLEN(pAC->Pnmi.pDriverReleaseDate) + 1; + if (Len > SK_PNMI_STRINGLEN1) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR054, SK_PNMI_ERR054MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + *pBuf = (char)(Len - 1); + SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverReleaseDate, Len - 1); + *pLen = Len; + break; + + case OID_SKGE_DRIVER_FILENAME: + if (pAC->Pnmi.pDriverFileName == NULL) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR055, SK_PNMI_ERR055MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + Len = SK_STRLEN(pAC->Pnmi.pDriverFileName) + 1; + if (Len > SK_PNMI_STRINGLEN1) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR056, SK_PNMI_ERR056MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + *pBuf = (char)(Len - 1); + SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverFileName, Len - 1); + *pLen = Len; + break; + case OID_SKGE_HW_DESCR: /* * The hardware description is located in the VPD. This * query may move to the initialisation routine. But * the VPD data is cached and therefore a call here * will not make much difference. + * Please read comment in Vpd(). */ + if (pAC->Pnmi.VpdKeyReadError == SK_TRUE) { + return (SK_PNMI_ERR_OK); + } + Len = 256; if (VpdRead(pAC, IoC, VPD_NAME, Buf, (int *)&Len) > 0) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032, - SK_PNMI_ERR032MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032, SK_PNMI_ERR032MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -4225,8 +3724,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Len ++; if (Len > SK_PNMI_STRINGLEN1) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033, - SK_PNMI_ERR033MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033, SK_PNMI_ERR033MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -4242,7 +3740,6 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_HW_VERSION: - /* Oh, I love to do some string manipulation */ if (*pLen < 5) { *pLen = 5; @@ -4251,9 +3748,9 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Val8 = (SK_U8)pAC->GIni.GIPciHwRev; pBuf[0] = 4; pBuf[1] = 'v'; - pBuf[2] = (char)(0x30 | ((Val8 >> 4) & 0x0F)); + pBuf[2] = (char)('0' | ((Val8 >> 4) & 0x0f)); pBuf[3] = '.'; - pBuf[4] = (char)(0x30 | (Val8 & 0x0F)); + pBuf[4] = (char)('0' | (Val8 & 0x0f)); *pLen = 5; break; @@ -4263,6 +3760,23 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ *pLen = sizeof(SK_U16); break; + case OID_SKGE_CHIPID: + Val32 = pAC->GIni.GIChipId; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_RAMSIZE: + Val32 = pAC->GIni.GIRamSize; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_VAUXAVAIL: + *pBuf = (char)pAC->GIni.GIVauxAvail; + *pLen = sizeof(char); + break; + case OID_SKGE_BUS_TYPE: *pBuf = (char)SK_PNMI_BUS_PCI; *pLen = sizeof(char); @@ -4313,35 +3827,35 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_RLMT_MONITOR_NUMBER: -/* XXX Not yet implemented by RLMT therefore we return zero elements */ + /* Not yet implemented by RLMT, therefore we return zero elements. */ Val32 = 0; SK_PNMI_STORE_U32(pBuf, Val32); *pLen = sizeof(SK_U32); break; case OID_SKGE_TX_SW_QUEUE_LEN: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueLen; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.BufPort[0].TxSwQueueLen + pAC->Pnmi.BufPort[1].TxSwQueueLen; - } + } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueLen; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.Port[0].TxSwQueueLen + pAC->Pnmi.Port[1].TxSwQueueLen; - } + } } SK_PNMI_STORE_U64(pBuf, Val64); *pLen = sizeof(SK_U64); @@ -4349,24 +3863,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ case OID_SKGE_TX_SW_QUEUE_MAX: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueMax; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.BufPort[0].TxSwQueueMax + pAC->Pnmi.BufPort[1].TxSwQueueMax; } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueMax; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.Port[0].TxSwQueueMax + pAC->Pnmi.Port[1].TxSwQueueMax; @@ -4377,24 +3891,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_TX_RETRY: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.BufPort[NetIndex].TxRetryCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.BufPort[0].TxRetryCts + pAC->Pnmi.BufPort[1].TxRetryCts; } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.Port[NetIndex].TxRetryCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.Port[0].TxRetryCts + pAC->Pnmi.Port[1].TxRetryCts; @@ -4405,24 +3919,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_RX_INTR_CTS: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.BufPort[NetIndex].RxIntrCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.BufPort[0].RxIntrCts + pAC->Pnmi.BufPort[1].RxIntrCts; } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.Port[NetIndex].RxIntrCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.Port[0].RxIntrCts + pAC->Pnmi.Port[1].RxIntrCts; @@ -4433,24 +3947,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_TX_INTR_CTS: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.BufPort[NetIndex].TxIntrCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.BufPort[0].TxIntrCts + pAC->Pnmi.BufPort[1].TxIntrCts; } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.Port[NetIndex].TxIntrCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.Port[0].TxIntrCts + pAC->Pnmi.Port[1].TxIntrCts; @@ -4461,24 +3975,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_RX_NO_BUF_CTS: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.BufPort[0].RxNoBufCts + pAC->Pnmi.BufPort[1].RxNoBufCts; } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.Port[0].RxNoBufCts + pAC->Pnmi.Port[1].RxNoBufCts; @@ -4489,24 +4003,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_TX_NO_BUF_CTS: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.BufPort[NetIndex].TxNoBufCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.BufPort[0].TxNoBufCts + pAC->Pnmi.BufPort[1].TxNoBufCts; } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.Port[NetIndex].TxNoBufCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.Port[0].TxNoBufCts + pAC->Pnmi.Port[1].TxNoBufCts; @@ -4517,24 +4031,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_TX_USED_DESCR_NO: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.BufPort[NetIndex].TxUsedDescrNo; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.BufPort[0].TxUsedDescrNo + pAC->Pnmi.BufPort[1].TxUsedDescrNo; } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.Port[NetIndex].TxUsedDescrNo; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.Port[0].TxUsedDescrNo + pAC->Pnmi.Port[1].TxUsedDescrNo; @@ -4545,24 +4059,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_RX_DELIVERED_CTS: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.BufPort[NetIndex].RxDeliveredCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.BufPort[0].RxDeliveredCts + pAC->Pnmi.BufPort[1].RxDeliveredCts; } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.Port[NetIndex].RxDeliveredCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.Port[0].RxDeliveredCts + pAC->Pnmi.Port[1].RxDeliveredCts; @@ -4573,24 +4087,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_RX_OCTETS_DELIV_CTS: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.BufPort[NetIndex].RxOctetsDeliveredCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.BufPort[0].RxOctetsDeliveredCts + pAC->Pnmi.BufPort[1].RxOctetsDeliveredCts; } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.Port[0].RxOctetsDeliveredCts + pAC->Pnmi.Port[1].RxOctetsDeliveredCts; @@ -4611,13 +4125,13 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_IN_ERRORS_CTS: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[0].RxNoBufCts + @@ -4625,11 +4139,11 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = Val64RxHwErrs + pAC->Pnmi.Port[0].RxNoBufCts + @@ -4641,13 +4155,13 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_OUT_ERROR_CTS: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[0].TxNoBufCts + @@ -4655,11 +4169,11 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = Val64TxHwErrs + pAC->Pnmi.Port[0].TxNoBufCts + @@ -4671,24 +4185,24 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_ERR_RECOVERY_CTS: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.BufPort[NetIndex].ErrRecoveryCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.BufPort[0].ErrRecoveryCts + pAC->Pnmi.BufPort[1].ErrRecoveryCts; } } else { - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { Val64 = pAC->Pnmi.Port[NetIndex].ErrRecoveryCts; } - /* Single net mode */ + /* SingleNet mode. */ else { Val64 = pAC->Pnmi.Port[0].ErrRecoveryCts + pAC->Pnmi.Port[1].ErrRecoveryCts; @@ -4712,7 +4226,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_GEN_RCV_ERROR: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; } @@ -4721,7 +4235,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } /* - * by default 32bit values are evaluated + * By default 32bit values are evaluated. */ if (!Is64BitReq) { Val32 = (SK_U32)Val64; @@ -4735,7 +4249,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_GEN_XMIT_ERROR: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts; } @@ -4744,7 +4258,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } /* - * by default 32bit values are evaluated + * By default 32bit values are evaluated. */ if (!Is64BitReq) { Val32 = (SK_U32)Val64; @@ -4758,16 +4272,19 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_GEN_RCV_NO_BUFFER: - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ if (MacType == SK_MAC_XMAC) { - Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; + Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex); + } else { - Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts; + Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex); } /* - * by default 32bit values are evaluated + * By default 32bit values are evaluated. */ if (!Is64BitReq) { Val32 = (SK_U32)Val64; @@ -4787,8 +4304,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; default: - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034, - SK_PNMI_ERR034MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034, SK_PNMI_ERR034MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -4824,19 +4340,19 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * value range. * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int Rlmt( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { int Ret; unsigned int PhysPortIndex; @@ -4845,25 +4361,17 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ SK_U32 Val32; SK_U64 Val64; - - /* - * Check instance. Only single instance OIDs are allowed here. - */ + /* Check instance. Only single instance OIDs are allowed here. */ if (Instance != (SK_U32)(-1) && Instance != 1) { *pLen = 0; return (SK_PNMI_ERR_UNKNOWN_INST); } - /* - * Perform the requested action - */ + /* Perform the requested action. */ if (Action == SK_PNMI_GET) { - /* - * Check if the buffer length is large enough. - */ - + /* Check if the buffer length is large enough. */ switch (Id) { case OID_SKGE_RLMT_MODE: @@ -4896,8 +4404,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; default: - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035, - SK_PNMI_ERR035MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035, SK_PNMI_ERR035MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -4916,9 +4423,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } pAC->Pnmi.RlmtUpdatedFlag ++; - /* - * Retrieve Value - */ + /* Retrieve value. */ switch (Id) { case OID_SKGE_RLMT_MODE: @@ -4996,17 +4501,17 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ pAC->Pnmi.RlmtUpdatedFlag --; } else { - /* Perform a preset or set */ + /* Perform a PRESET or SET. */ switch (Id) { case OID_SKGE_RLMT_MODE: - /* Check if the buffer length is plausible */ + /* Check if the buffer length is plausible. */ if (*pLen < sizeof(char)) { *pLen = sizeof(char); return (SK_PNMI_ERR_TOO_SHORT); } - /* Check if the value range is correct */ + /* Check if the value range is correct. */ if (*pLen != sizeof(char) || (*pBuf & SK_PNMI_RLMT_MODE_CHK_LINK) == 0 || *(SK_U8 *)pBuf > 15) { @@ -5014,21 +4519,21 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ *pLen = 0; return (SK_PNMI_ERR_BAD_VALUE); } - /* The preset ends here */ + /* The PRESET ends here. */ if (Action == SK_PNMI_PRESET) { *pLen = 0; return (SK_PNMI_ERR_OK); } - /* Send an event to RLMT to change the mode */ + /* Send an event to RLMT to change the mode. */ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + EventParam.Para32[0] |= (SK_U32)(*pBuf); EventParam.Para32[1] = 0; if (SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE, EventParam) > 0) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037, - SK_PNMI_ERR037MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037, SK_PNMI_ERR037MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -5036,20 +4541,25 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_RLMT_PORT_PREFERRED: - /* Check if the buffer length is plausible */ + /* PRESET/SET action makes no sense in Dual Net mode. */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + break; + } + + /* Check if the buffer length is plausible. */ if (*pLen < sizeof(char)) { *pLen = sizeof(char); return (SK_PNMI_ERR_TOO_SHORT); } - /* Check if the value range is correct */ + /* Check if the value range is correct. */ if (*pLen != sizeof(char) || *(SK_U8 *)pBuf > (SK_U8)pAC->GIni.GIMacsFound) { *pLen = 0; return (SK_PNMI_ERR_BAD_VALUE); } - /* The preset ends here */ + /* The PRESET ends here. */ if (Action == SK_PNMI_PRESET) { *pLen = 0; @@ -5062,13 +4572,13 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * make the decision which is the preferred port. */ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + EventParam.Para32[0] = (SK_U32)(*pBuf) - 1; EventParam.Para32[1] = NetIndex; if (SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE, EventParam) > 0) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038, - SK_PNMI_ERR038MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038, SK_PNMI_ERR038MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -5076,22 +4586,20 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_SKGE_RLMT_CHANGE_THRES: - /* Check if the buffer length is plausible */ + /* Check if the buffer length is plausible. */ if (*pLen < sizeof(SK_U64)) { *pLen = sizeof(SK_U64); return (SK_PNMI_ERR_TOO_SHORT); } - /* - * There are not many restrictions to the - * value range. - */ + + /* There are not many restrictions to the value range. */ if (*pLen != sizeof(SK_U64)) { *pLen = 0; return (SK_PNMI_ERR_BAD_VALUE); } - /* A preset ends here */ + /* The PRESET ends here. */ if (Action == SK_PNMI_PRESET) { *pLen = 0; @@ -5106,7 +4614,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; default: - /* The other OIDs are not be able for set */ + /* The other OIDs are not be able for set. */ *pLen = 0; return (SK_PNMI_ERR_READ_ONLY); } @@ -5129,19 +4637,19 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * the correct data (e.g. a 32bit value is * needed, but a 16 bit value was passed). * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int RlmtStat( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { unsigned int PhysPortMax; unsigned int PhysPortIndex; @@ -5151,54 +4659,49 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ SK_U32 Val32; SK_U64 Val64; - /* - * Calculate the port indexes from the instance - */ + + /* Calculate the port indexes from the instance. */ PhysPortMax = pAC->GIni.GIMacsFound; if ((Instance != (SK_U32)(-1))) { - /* Check instance range */ + /* Check instance range. */ if ((Instance < 1) || (Instance > PhysPortMax)) { *pLen = 0; return (SK_PNMI_ERR_UNKNOWN_INST); } - /* Single net mode */ + /* SingleNet mode. */ PhysPortIndex = Instance - 1; - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { PhysPortIndex = NetIndex; } - /* Both net modes */ + /* Both net modes. */ Limit = PhysPortIndex + 1; } else { - /* Single net mode */ + /* SingleNet mode. */ PhysPortIndex = 0; Limit = PhysPortMax; - /* Dual net mode */ + /* DualNet mode. */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { PhysPortIndex = NetIndex; Limit = PhysPortIndex + 1; } } - /* - * Currently only get requests are allowed. - */ + /* Currently only GET requests are allowed. */ if (Action != SK_PNMI_GET) { *pLen = 0; return (SK_PNMI_ERR_READ_ONLY); } - /* - * Check if the buffer length is large enough. - */ + /* Check if the buffer length is large enough. */ switch (Id) { case OID_SKGE_RLMT_PORT_INDEX: @@ -5222,8 +4725,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; default: - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039, - SK_PNMI_ERR039MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039, SK_PNMI_ERR039MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -5241,9 +4743,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } pAC->Pnmi.RlmtUpdatedFlag ++; - /* - * Get value - */ + /* Get value. */ Offset = 0; for (; PhysPortIndex < Limit; PhysPortIndex ++) { @@ -5331,19 +4831,19 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * value range. * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int MacPrivateConf( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { unsigned int PhysPortMax; unsigned int PhysPortIndex; @@ -5352,24 +4852,25 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ unsigned int Limit; unsigned int Offset; char Val8; - int Ret; + char *pBufPtr; + int Ret; SK_EVPARA EventParam; SK_U32 Val32; +#ifdef SK_PHY_LP_MODE + SK_U8 CurrentPhyPowerState; +#endif /* SK_PHY_LP_MODE */ - /* - * Calculate instance if wished. MAC index 0 is the virtual - * MAC. - */ + /* Calculate instance if wished. MAC index 0 is the virtual MAC. */ PhysPortMax = pAC->GIni.GIMacsFound; LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); - if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */ LogPortMax--; } - if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */ - /* Check instance range */ + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */ + /* Check instance range. */ if ((Instance < 1) || (Instance > LogPortMax)) { *pLen = 0; @@ -5379,20 +4880,16 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Limit = LogPortIndex + 1; } - else { /* Instance == (SK_U32)(-1), get all Instances of that OID */ + else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */ LogPortIndex = 0; Limit = LogPortMax; } - /* - * Perform action - */ + /* Perform action. */ if (Action == SK_PNMI_GET) { - /* - * Check length - */ + /* Check length. */ switch (Id) { case OID_SKGE_PMD: @@ -5410,25 +4907,27 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ case OID_SKGE_SPEED_CAP: case OID_SKGE_SPEED_MODE: case OID_SKGE_SPEED_STATUS: +#ifdef SK_PHY_LP_MODE + case OID_SKGE_PHY_LP_MODE: +#endif if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U8)) { - *pLen = (Limit - LogPortIndex) * - sizeof(SK_U8); + *pLen = (Limit - LogPortIndex) * sizeof(SK_U8); return (SK_PNMI_ERR_TOO_SHORT); } break; - case OID_SKGE_MTU: - if (*pLen < sizeof(SK_U32)) { + case OID_SKGE_MTU: + case OID_SKGE_PHY_TYPE: + if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U32)) { - *pLen = sizeof(SK_U32); + *pLen = (Limit - LogPortIndex) * sizeof(SK_U32); return (SK_PNMI_ERR_TOO_SHORT); } break; default: - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041, - SK_PNMI_ERR041MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041, SK_PNMI_ERR041MSG); *pLen = 0; return (SK_PNMI_ERR_GENERAL); } @@ -5444,349 +4943,336 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } pAC->Pnmi.SirqUpdatedFlag ++; - /* - * Get value - */ + /* Get value. */ Offset = 0; for (; LogPortIndex < Limit; LogPortIndex ++) { + pBufPtr = pBuf + Offset; + switch (Id) { case OID_SKGE_PMD: - *(pBuf + Offset) = pAC->Pnmi.PMD; - Offset += sizeof(char); + *pBufPtr = pAC->Pnmi.PMD; + Offset ++; break; case OID_SKGE_CONNECTOR: - *(pBuf + Offset) = pAC->Pnmi.Connector; - Offset += sizeof(char); + *pBufPtr = pAC->Pnmi.Connector; + Offset ++; break; - case OID_SKGE_LINK_CAP: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + case OID_SKGE_PHY_TYPE: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { + continue; + } + /* Get value for physical port. */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex); + Val32 = pAC->GIni.GP[PhysPortIndex].PhyType; + } + else { /* DualNet mode. */ + + Val32 = pAC->GIni.GP[NetIndex].PhyType; + } + SK_PNMI_STORE_U32(pBufPtr, Val32); + Offset += sizeof(SK_U32); + break; - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + - Offset); +#ifdef SK_PHY_LP_MODE + case OID_SKGE_PHY_LP_MODE: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ + if (LogPortIndex == 0) { + continue; + } + /* Get value for physical port. */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex); + *pBufPtr = (SK_U8)pAC->GIni.GP[PhysPortIndex].PPhyPowerState; + } + else { /* DualNet mode. */ + + *pBufPtr = (SK_U8)pAC->GIni.GP[NetIndex].PPhyPowerState; + } + Offset += sizeof(SK_U8); + break; +#endif + + case OID_SKGE_LINK_CAP: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ + if (LogPortIndex == 0) { + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical ports */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - *(pBuf + Offset) = pAC->GIni.GP[ - PhysPortIndex].PLinkCap; + *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkCap; } - Offset += sizeof(char); } - else { /* DualNetMode */ - - *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkCap; - Offset += sizeof(char); + else { /* DualNet mode. */ + + *pBufPtr = pAC->GIni.GP[NetIndex].PLinkCap; } + Offset ++; break; case OID_SKGE_LINK_MODE: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + - Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical ports */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - *(pBuf + Offset) = pAC->GIni.GP[ - PhysPortIndex].PLinkModeConf; + *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkModeConf; } - Offset += sizeof(char); } - else { /* DualNetMode */ - - *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkModeConf; - Offset += sizeof(char); + else { /* DualNet mode. */ + + *pBufPtr = pAC->GIni.GP[NetIndex].PLinkModeConf; } + Offset ++; break; case OID_SKGE_LINK_MODE_STATUS: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + - Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical port */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - *(pBuf + Offset) = - CalculateLinkModeStatus(pAC, - IoC, PhysPortIndex); + *pBufPtr = + CalculateLinkModeStatus(pAC, IoC, PhysPortIndex); } - Offset += sizeof(char); } - else { /* DualNetMode */ - *(pBuf + Offset) = CalculateLinkModeStatus(pAC, IoC, NetIndex); - Offset += sizeof(char); + else { /* DualNet mode. */ + + *pBufPtr = CalculateLinkModeStatus(pAC, IoC, NetIndex); } + Offset ++; break; case OID_SKGE_LINK_STATUS: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + - Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical ports */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - - *(pBuf + Offset) = - CalculateLinkStatus(pAC, - IoC, PhysPortIndex); + + *pBufPtr = CalculateLinkStatus(pAC, IoC, PhysPortIndex); } - Offset += sizeof(char); } - else { /* DualNetMode */ + else { /* DualNet mode. */ - *(pBuf + Offset) = CalculateLinkStatus(pAC, IoC, NetIndex); - Offset += sizeof(char); + *pBufPtr = CalculateLinkStatus(pAC, IoC, NetIndex); } + Offset ++; break; case OID_SKGE_FLOWCTRL_CAP: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + - Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical ports */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - - *(pBuf + Offset) = pAC->GIni.GP[ - PhysPortIndex].PFlowCtrlCap; + + *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap; } - Offset += sizeof(char); } - else { /* DualNetMode */ - - *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PFlowCtrlCap; - Offset += sizeof(char); + else { /* DualNet mode. */ + + *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlCap; } + Offset ++; break; case OID_SKGE_FLOWCTRL_MODE: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + - Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical port */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - - *(pBuf + Offset) = pAC->GIni.GP[ - PhysPortIndex].PFlowCtrlMode; + + *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode; } - Offset += sizeof(char); } - else { /* DualNetMode */ + else { /* DualNet mode. */ - *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PFlowCtrlMode; - Offset += sizeof(char); + *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlMode; } + Offset ++; break; case OID_SKGE_FLOWCTRL_STATUS: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + - Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical port */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - - *(pBuf + Offset) = pAC->GIni.GP[ - PhysPortIndex].PFlowCtrlStatus; + + *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus; } - Offset += sizeof(char); } - else { /* DualNetMode */ + else { /* DualNet mode. */ - *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PFlowCtrlStatus; - Offset += sizeof(char); + *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlStatus; } + Offset ++; break; case OID_SKGE_PHY_OPERATION_CAP: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet Mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + - Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical ports */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - - *(pBuf + Offset) = pAC->GIni.GP[ - PhysPortIndex].PMSCap; + + *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSCap; } - Offset += sizeof(char); } - else { /* DualNetMode */ - - *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSCap; - Offset += sizeof(char); + else { /* DualNet mode. */ + + *pBufPtr = pAC->GIni.GP[NetIndex].PMSCap; } + Offset ++; break; case OID_SKGE_PHY_OPERATION_MODE: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical port */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - *(pBuf + Offset) = pAC->GIni.GP[ - PhysPortIndex].PMSMode; + *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSMode; } - Offset += sizeof(char); } - else { /* DualNetMode */ - - *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSMode; - Offset += sizeof(char); + else { /* DualNet mode. */ + + *pBufPtr = pAC->GIni.GP[NetIndex].PMSMode; } + Offset ++; break; case OID_SKGE_PHY_OPERATION_STATUS: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical port */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - - *(pBuf + Offset) = pAC->GIni.GP[ - PhysPortIndex].PMSStatus; + + *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSStatus; } - Offset += sizeof(char); } else { - - *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSStatus; - Offset += sizeof(char); + + *pBufPtr = pAC->GIni.GP[NetIndex].PMSStatus; } + Offset ++; break; case OID_SKGE_SPEED_CAP: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + - Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical ports */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - - *(pBuf + Offset) = pAC->GIni.GP[ - PhysPortIndex].PLinkSpeedCap; + + *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedCap; } - Offset += sizeof(char); } - else { /* DualNetMode */ - - *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkSpeedCap; - Offset += sizeof(char); + else { /* DualNet mode. */ + + *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedCap; } + Offset ++; break; case OID_SKGE_SPEED_MODE: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical port */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - - *(pBuf + Offset) = pAC->GIni.GP[ - PhysPortIndex].PLinkSpeed; + + *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeed; } - Offset += sizeof(char); } - else { /* DualNetMode */ + else { /* DualNet mode. */ - *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkSpeed; - Offset += sizeof(char); + *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeed; } + Offset ++; break; case OID_SKGE_SPEED_STATUS: - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ if (LogPortIndex == 0) { - - /* Get value for virtual port */ - VirtualConf(pAC, IoC, Id, pBuf + Offset); + /* Get value for virtual port. */ + VirtualConf(pAC, IoC, Id, pBufPtr); } else { - /* Get value for physical port */ + /* Get value for physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( pAC, LogPortIndex); - - *(pBuf + Offset) = pAC->GIni.GP[ - PhysPortIndex].PLinkSpeedUsed; + + *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed; } - Offset += sizeof(char); } - else { /* DualNetMode */ + else { /* DualNet mode. */ - *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkSpeedUsed; - Offset += sizeof(char); + *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedUsed; } + Offset ++; break; - + case OID_SKGE_MTU: Val32 = SK_DRIVER_GET_MTU(pAC, IoC, NetIndex); - SK_PNMI_STORE_U32(pBuf + Offset, Val32); + SK_PNMI_STORE_U32(pBufPtr, Val32); Offset += sizeof(SK_U32); break; @@ -5826,38 +5312,41 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } break; - case OID_SKGE_MTU: - if (*pLen < sizeof(SK_U32)) { +#ifdef SK_PHY_LP_MODE + case OID_SKGE_PHY_LP_MODE: + if (*pLen < Limit - LogPortIndex) { - *pLen = sizeof(SK_U32); + *pLen = Limit - LogPortIndex; return (SK_PNMI_ERR_TOO_SHORT); } - if (*pLen != sizeof(SK_U32)) { + break; +#endif /* SK_PHY_LP_MODE */ - *pLen = 0; - return (SK_PNMI_ERR_BAD_VALUE); + case OID_SKGE_MTU: + if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U32)) { + + *pLen = (Limit - LogPortIndex) * sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); } break; - + default: *pLen = 0; return (SK_PNMI_ERR_READ_ONLY); } - /* - * Perform preset or set - */ + /* Perform PRESET or SET. */ Offset = 0; for (; LogPortIndex < Limit; LogPortIndex ++) { + Val8 = *(pBuf + Offset); + switch (Id) { case OID_SKGE_LINK_MODE: - /* Check the value range */ - Val8 = *(pBuf + Offset); + /* Check the value range. */ if (Val8 == 0) { - - Offset += sizeof(char); + Offset++; break; } if (Val8 < SK_LMODE_HALF || @@ -5868,51 +5357,68 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_BAD_VALUE); } - /* The preset ends here */ + /* The PRESET ends here. */ if (Action == SK_PNMI_PRESET) { return (SK_PNMI_ERR_OK); } - if (LogPortIndex == 0) { + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ + if (LogPortIndex == 0) { + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with the new link mode to SIRQ. + */ + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { - /* - * The virtual port consists of all currently - * active ports. Find them and send an event - * with the new link mode to SIRQ. - */ - for (PhysPortIndex = 0; - PhysPortIndex < PhysPortMax; - PhysPortIndex ++) { - - if (!pAC->Pnmi.Port[PhysPortIndex]. - ActiveFlag) { - - continue; - } - - EventParam.Para32[0] = PhysPortIndex; + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + continue; + } + + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_LMODE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR043, + SK_PNMI_ERR043MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } /* for */ + } + else { + /* + * Send an event with the new link mode to + * the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); EventParam.Para32[1] = (SK_U32)Val8; - if (SkGeSirqEvent(pAC, IoC, - SK_HWEV_SET_LMODE, + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE, EventParam) > 0) { - + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR043, SK_PNMI_ERR043MSG); - + *pLen = 0; return (SK_PNMI_ERR_GENERAL); } } } - else { + else { /* DualNet mode. */ + /* * Send an event with the new link mode to * the SIRQ module. */ - EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( - pAC, LogPortIndex); + EventParam.Para32[0] = NetIndex; EventParam.Para32[1] = (SK_U32)Val8; if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE, EventParam) > 0) { @@ -5925,15 +5431,13 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_GENERAL); } } - Offset += sizeof(char); + Offset++; break; case OID_SKGE_FLOWCTRL_MODE: - /* Check the value range */ - Val8 = *(pBuf + Offset); + /* Check the value range. */ if (Val8 == 0) { - - Offset += sizeof(char); + Offset++; break; } if (Val8 < SK_FLOW_MODE_NONE || @@ -5944,30 +5448,48 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_BAD_VALUE); } - /* The preset ends here */ + /* The PRESET ends here. */ if (Action == SK_PNMI_PRESET) { return (SK_PNMI_ERR_OK); } - if (LogPortIndex == 0) { + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ + if (LogPortIndex == 0) { + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with the new flow control mode to SIRQ. + */ + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { - /* - * The virtual port consists of all currently - * active ports. Find them and send an event - * with the new flow control mode to SIRQ. - */ - for (PhysPortIndex = 0; - PhysPortIndex < PhysPortMax; - PhysPortIndex ++) { + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + continue; + } - if (!pAC->Pnmi.Port[PhysPortIndex]. - ActiveFlag) { + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_FLOWMODE, + EventParam) > 0) { - continue; + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR044, + SK_PNMI_ERR044MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } } - - EventParam.Para32[0] = PhysPortIndex; + } + else { + /* + * Send an event with the new flow control + * mode to the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); EventParam.Para32[1] = (SK_U32)Val8; if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_FLOWMODE, @@ -5982,17 +5504,16 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } } } - else { + else { /* DualNet mode. */ + /* - * Send an event with the new flow control - * mode to the SIRQ module. + * Send an event with the new link mode to + * the SIRQ module. */ - EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( - pAC, LogPortIndex); + EventParam.Para32[0] = NetIndex; EventParam.Para32[1] = (SK_U32)Val8; - if (SkGeSirqEvent(pAC, IoC, - SK_HWEV_SET_FLOWMODE, EventParam) - > 0) { + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_FLOWMODE, + EventParam) > 0) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR044, @@ -6002,15 +5523,14 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_GENERAL); } } - Offset += sizeof(char); + Offset++; break; case OID_SKGE_PHY_OPERATION_MODE : - /* Check the value range */ - Val8 = *(pBuf + Offset); + /* Check the value range. */ if (Val8 == 0) { - /* mode of this port remains unchanged */ - Offset += sizeof(char); + /* Mode of this port remains unchanged. */ + Offset++; break; } if (Val8 < SK_MS_MODE_AUTO || @@ -6021,34 +5541,51 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_BAD_VALUE); } - /* The preset ends here */ + /* The PRESET ends here. */ if (Action == SK_PNMI_PRESET) { return (SK_PNMI_ERR_OK); } - if (LogPortIndex == 0) { + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ + if (LogPortIndex == 0) { + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with new master/slave (role) mode to SIRQ. + */ + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { - /* - * The virtual port consists of all currently - * active ports. Find them and send an event - * with new master/slave (role) mode to SIRQ. - */ - for (PhysPortIndex = 0; - PhysPortIndex < PhysPortMax; - PhysPortIndex ++) { + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + continue; + } - if (!pAC->Pnmi.Port[PhysPortIndex]. - ActiveFlag) { + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_ROLE, + EventParam) > 0) { - continue; + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR042, + SK_PNMI_ERR042MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } } - - EventParam.Para32[0] = PhysPortIndex; + } + else { + /* + * Send an event with the new master/slave + * (role) mode to the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); EventParam.Para32[1] = (SK_U32)Val8; if (SkGeSirqEvent(pAC, IoC, - SK_HWEV_SET_ROLE, - EventParam) > 0) { + SK_HWEV_SET_ROLE, EventParam) > 0) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR042, @@ -6059,16 +5596,16 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } } } - else { + else { /* DualNet mode. */ + /* - * Send an event with the new master/slave - * (role) mode to the SIRQ module. + * Send an event with the new link mode to + * the SIRQ module. */ - EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( - pAC, LogPortIndex); + EventParam.Para32[0] = NetIndex; EventParam.Para32[1] = (SK_U32)Val8; - if (SkGeSirqEvent(pAC, IoC, - SK_HWEV_SET_ROLE, EventParam) > 0) { + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_ROLE, + EventParam) > 0) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR042, @@ -6078,16 +5615,13 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_GENERAL); } } - - Offset += sizeof(char); + Offset++; break; case OID_SKGE_SPEED_MODE: - /* Check the value range */ - Val8 = *(pBuf + Offset); + /* Check the value range. */ if (Val8 == 0) { - - Offset += sizeof(char); + Offset++; break; } if (Val8 < (SK_LSPEED_AUTO) || @@ -6098,29 +5632,49 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_BAD_VALUE); } - /* The preset ends here */ + /* The PRESET ends here. */ if (Action == SK_PNMI_PRESET) { return (SK_PNMI_ERR_OK); } - if (LogPortIndex == 0) { + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ + if (LogPortIndex == 0) { - /* - * The virtual port consists of all currently - * active ports. Find them and send an event - * with the new flow control mode to SIRQ. - */ - for (PhysPortIndex = 0; - PhysPortIndex < PhysPortMax; - PhysPortIndex ++) { + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with the new flow control mode to SIRQ. + */ + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { - if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + continue; + } - continue; + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_SPEED, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR045, + SK_PNMI_ERR045MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } } - - EventParam.Para32[0] = PhysPortIndex; + } + else { + /* + * Send an event with the new flow control + * mode to the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); EventParam.Para32[1] = (SK_U32)Val8; if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_SPEED, @@ -6135,16 +5689,15 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ } } } - else { + else { /* DualNet mode. */ + /* - * Send an event with the new flow control - * mode to the SIRQ module. + * Send an event with the new link mode to + * the SIRQ module. */ - EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( - pAC, LogPortIndex); + EventParam.Para32[0] = NetIndex; EventParam.Para32[1] = (SK_U32)Val8; - if (SkGeSirqEvent(pAC, IoC, - SK_HWEV_SET_SPEED, + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_SPEED, EventParam) > 0) { SK_ERR_LOG(pAC, SK_ERRCL_SW, @@ -6155,23 +5708,25 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (SK_PNMI_ERR_GENERAL); } } - Offset += sizeof(char); + Offset++; break; - case OID_SKGE_MTU : - /* Check the value range */ - Val32 = *(SK_U32*)(pBuf + Offset); + case OID_SKGE_MTU: + /* Check the value range. */ + SK_PNMI_READ_U32((pBuf + Offset), Val32); + if (Val32 == 0) { - /* mtu of this port remains unchanged */ + /* MTU of this port remains unchanged. */ Offset += sizeof(SK_U32); break; } + if (SK_DRIVER_PRESET_MTU(pAC, IoC, NetIndex, Val32) != 0) { *pLen = 0; return (SK_PNMI_ERR_BAD_VALUE); } - /* The preset ends here */ + /* The PRESET ends here. */ if (Action == SK_PNMI_PRESET) { return (SK_PNMI_ERR_OK); } @@ -6183,9 +5738,72 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Offset += sizeof(SK_U32); break; +#ifdef SK_PHY_LP_MODE + case OID_SKGE_PHY_LP_MODE: + /* The PRESET ends here. */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */ + if (LogPortIndex == 0) { + Offset = 0; + continue; + } + } + /* Set value for physical port. */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex); + CurrentPhyPowerState = pAC->GIni.GP[PhysPortIndex].PPhyPowerState; + + switch (Val8) { + case PHY_PM_OPERATIONAL_MODE: + /* If LowPowerMode is active, we can leave it. */ + if (CurrentPhyPowerState) { + + Val32 = SkGmLeaveLowPowerMode(pAC, IoC, PhysPortIndex); + + if ((CurrentPhyPowerState == PHY_PM_DEEP_SLEEP) || + (CurrentPhyPowerState == PHY_PM_IEEE_POWER_DOWN)) { + + SkDrvInitAdapter(pAC); + } + break; + } + else { + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + case PHY_PM_DEEP_SLEEP: + case PHY_PM_IEEE_POWER_DOWN: + /* If no LowPowerMode is active, we can enter it. */ + if (!CurrentPhyPowerState) { + SkDrvDeInitAdapter(pAC); + } + + case PHY_PM_ENERGY_DETECT: + case PHY_PM_ENERGY_DETECT_PLUS: + /* If no LowPowerMode is active, we can enter it. */ + if (!CurrentPhyPowerState) { + + Val32 = SkGmEnterLowPowerMode(pAC, IoC, PhysPortIndex, *pBuf); + break; + } + else { + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + default: + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + Offset++; + break; +#endif /* SK_PHY_LP_MODE */ + default: - SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, - ("MacPrivateConf: Unknown OID should be handled before set")); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, + ("MacPrivateConf: Unknown OID should be handled before set")); *pLen = 0; return (SK_PNMI_ERR_GENERAL); @@ -6213,32 +5831,29 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * value range. * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter. */ PNMI_STATIC int Monitor( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which to mgmt data will be retrieved */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ -SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ { unsigned int Index; unsigned int Limit; unsigned int Offset; unsigned int Entries; - - - /* - * Calculate instance if wished. - */ -/* XXX Not yet implemented. Return always an empty table. */ + + /* Not implemented yet. Return always an empty table. */ Entries = 0; + /* Calculate instance if wished. */ if ((Instance != (SK_U32)(-1))) { if ((Instance < 1) || (Instance > Entries)) { @@ -6255,12 +5870,10 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ Limit = Entries; } - /* - * Get/Set value - */ + /* GET/SET value. */ if (Action == SK_PNMI_GET) { - for (Offset=0; Index < Limit; Index ++) { + for (Offset = 0; Index < Limit; Index ++) { switch (Id) { @@ -6282,32 +5895,29 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ *pLen = Offset; } else { - /* Only MONITOR_ADMIN can be set */ + /* Only MONITOR_ADMIN can be set. */ if (Id != OID_SKGE_RLMT_MONITOR_ADMIN) { *pLen = 0; return (SK_PNMI_ERR_READ_ONLY); } - /* Check if the length is plausible */ + /* Check if the length is plausible. */ if (*pLen < (Limit - Index)) { return (SK_PNMI_ERR_TOO_SHORT); } - /* Okay, we have a wide value range */ + /* Okay, we have a wide value range. */ if (*pLen != (Limit - Index)) { *pLen = 0; return (SK_PNMI_ERR_BAD_VALUE); } -/* - for (Offset=0; Index < Limit; Index ++) { - } -*/ -/* - * XXX Not yet implemented. Return always BAD_VALUE, because the table - * is empty. - */ + + /* + * Not yet implemented. Return always BAD_VALUE, + * because the table is empty. + */ *pLen = 0; return (SK_PNMI_ERR_BAD_VALUE); } @@ -6335,24 +5945,25 @@ PNMI_STATIC void VirtualConf( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf) /* Buffer to which to mgmt data will be retrieved */ +char *pBuf) /* Buffer used for the management data transfer */ { unsigned int PhysPortMax; unsigned int PhysPortIndex; SK_U8 Val8; + SK_U32 Val32; SK_BOOL PortActiveFlag; - + SK_GEPORT *pPrt; *pBuf = 0; PortActiveFlag = SK_FALSE; PhysPortMax = pAC->GIni.GIMacsFound; + + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; PhysPortIndex ++) { - for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; - PhysPortIndex ++) { + pPrt = &pAC->GIni.GP[PhysPortIndex]; - /* Check if the physical port is active */ + /* Check if the physical port is active. */ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { - continue; } @@ -6360,6 +5971,15 @@ char *pBuf) /* Buffer to which to mgmt data will be retrieved */ switch (Id) { + case OID_SKGE_PHY_TYPE: + /* Check if it is the first active port. */ + if (*pBuf == 0) { + Val32 = pPrt->PhyType; + SK_PNMI_STORE_U32(pBuf, Val32); + continue; + } + break; + case OID_SKGE_LINK_CAP: /* @@ -6368,34 +5988,32 @@ char *pBuf) /* Buffer to which to mgmt data will be retrieved */ * From a curious point of view the virtual port * is capable of all found capabilities. */ - *pBuf |= pAC->GIni.GP[PhysPortIndex].PLinkCap; + *pBuf |= pPrt->PLinkCap; break; case OID_SKGE_LINK_MODE: - /* Check if it is the first active port */ + /* Check if it is the first active port. */ if (*pBuf == 0) { - *pBuf = pAC->GIni.GP[PhysPortIndex].PLinkModeConf; + *pBuf = pPrt->PLinkModeConf; continue; } /* - * If we find an active port with a different link - * mode than the first one we return a value that - * indicates that the link mode is indeterminated. + * If we find an active port with a different link mode + * than the first one we return indeterminated. */ - if (*pBuf != pAC->GIni.GP[PhysPortIndex].PLinkModeConf - ) { + if (*pBuf != pPrt->PLinkModeConf) { *pBuf = SK_LMODE_INDETERMINATED; } break; case OID_SKGE_LINK_MODE_STATUS: - /* Get the link mode of the physical port */ + /* Get the link mode of the physical port. */ Val8 = CalculateLinkModeStatus(pAC, IoC, PhysPortIndex); - /* Check if it is the first active port */ + /* Check if it is the first active port. */ if (*pBuf == 0) { *pBuf = Val8; @@ -6403,10 +6021,8 @@ char *pBuf) /* Buffer to which to mgmt data will be retrieved */ } /* - * If we find an active port with a different link - * mode status than the first one we return a value - * that indicates that the link mode status is - * indeterminated. + * If we find an active port with a different link mode status + * than the first one we return indeterminated. */ if (*pBuf != Val8) { @@ -6415,10 +6031,10 @@ char *pBuf) /* Buffer to which to mgmt data will be retrieved */ break; case OID_SKGE_LINK_STATUS: - /* Get the link status of the physical port */ + /* Get the link status of the physical port. */ Val8 = CalculateLinkStatus(pAC, IoC, PhysPortIndex); - /* Check if it is the first active port */ + /* Check if it is the first active port. */ if (*pBuf == 0) { *pBuf = Val8; @@ -6426,10 +6042,8 @@ char *pBuf) /* Buffer to which to mgmt data will be retrieved */ } /* - * If we find an active port with a different link - * status than the first one, we return a value - * that indicates that the link status is - * indeterminated. + * If we find an active port with a different link status + * than the first one we return indeterminated. */ if (*pBuf != Val8) { @@ -6438,10 +6052,10 @@ char *pBuf) /* Buffer to which to mgmt data will be retrieved */ break; case OID_SKGE_FLOWCTRL_CAP: - /* Check if it is the first active port */ + /* Check if it is the first active port. */ if (*pBuf == 0) { - *pBuf = pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap; + *pBuf = pPrt->PFlowCtrlCap; continue; } @@ -6449,53 +6063,50 @@ char *pBuf) /* Buffer to which to mgmt data will be retrieved */ * From a curious point of view the virtual port * is capable of all found capabilities. */ - *pBuf |= pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap; + *pBuf |= pPrt->PFlowCtrlCap; break; case OID_SKGE_FLOWCTRL_MODE: - /* Check if it is the first active port */ + /* Check if it is the first active port. */ if (*pBuf == 0) { - *pBuf = pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode; + *pBuf = pPrt->PFlowCtrlMode; continue; } /* - * If we find an active port with a different flow - * control mode than the first one, we return a value - * that indicates that the mode is indeterminated. + * If we find an active port with a different flow-control mode + * than the first one we return indeterminated. */ - if (*pBuf != pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode) { + if (*pBuf != pPrt->PFlowCtrlMode) { *pBuf = SK_FLOW_MODE_INDETERMINATED; } break; case OID_SKGE_FLOWCTRL_STATUS: - /* Check if it is the first active port */ + /* Check if it is the first active port. */ if (*pBuf == 0) { - *pBuf = pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus; + *pBuf = pPrt->PFlowCtrlStatus; continue; } /* - * If we find an active port with a different flow - * control status than the first one, we return a - * value that indicates that the status is - * indeterminated. + * If we find an active port with a different flow-control status + * than the first one we return indeterminated. */ - if (*pBuf != pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus) { + if (*pBuf != pPrt->PFlowCtrlStatus) { *pBuf = SK_FLOW_STAT_INDETERMINATED; } break; - + case OID_SKGE_PHY_OPERATION_CAP: - /* Check if it is the first active port */ + /* Check if it is the first active port. */ if (*pBuf == 0) { - *pBuf = pAC->GIni.GP[PhysPortIndex].PMSCap; + *pBuf = pPrt->PMSCap; continue; } @@ -6503,82 +6114,76 @@ char *pBuf) /* Buffer to which to mgmt data will be retrieved */ * From a curious point of view the virtual port * is capable of all found capabilities. */ - *pBuf |= pAC->GIni.GP[PhysPortIndex].PMSCap; + *pBuf |= pPrt->PMSCap; break; case OID_SKGE_PHY_OPERATION_MODE: - /* Check if it is the first active port */ + /* Check if it is the first active port. */ if (*pBuf == 0) { - *pBuf = pAC->GIni.GP[PhysPortIndex].PMSMode; + *pBuf = pPrt->PMSMode; continue; } /* - * If we find an active port with a different master/ - * slave mode than the first one, we return a value - * that indicates that the mode is indeterminated. + * If we find an active port with a different master/slave mode + * than the first one we return indeterminated. */ - if (*pBuf != pAC->GIni.GP[PhysPortIndex].PMSMode) { + if (*pBuf != pPrt->PMSMode) { *pBuf = SK_MS_MODE_INDETERMINATED; } break; case OID_SKGE_PHY_OPERATION_STATUS: - /* Check if it is the first active port */ + /* Check if it is the first active port. */ if (*pBuf == 0) { - *pBuf = pAC->GIni.GP[PhysPortIndex].PMSStatus; + *pBuf = pPrt->PMSStatus; continue; } /* - * If we find an active port with a different master/ - * slave status than the first one, we return a - * value that indicates that the status is - * indeterminated. + * If we find an active port with a different master/slave status + * than the first one we return indeterminated. */ - if (*pBuf != pAC->GIni.GP[PhysPortIndex].PMSStatus) { + if (*pBuf != pPrt->PMSStatus) { *pBuf = SK_MS_STAT_INDETERMINATED; } break; - + case OID_SKGE_SPEED_MODE: - /* Check if it is the first active port */ + /* Check if it is the first active port. */ if (*pBuf == 0) { - *pBuf = pAC->GIni.GP[PhysPortIndex].PLinkSpeed; + *pBuf = pPrt->PLinkSpeed; continue; } /* - * If we find an active port with a different flow - * control mode than the first one, we return a value - * that indicates that the mode is indeterminated. + * If we find an active port with a different link speed + * than the first one we return indeterminated. */ - if (*pBuf != pAC->GIni.GP[PhysPortIndex].PLinkSpeed) { + if (*pBuf != pPrt->PLinkSpeed) { *pBuf = SK_LSPEED_INDETERMINATED; } break; - + case OID_SKGE_SPEED_STATUS: - /* Check if it is the first active port */ + /* Check if it is the first active port. */ if (*pBuf == 0) { - *pBuf = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed; + *pBuf = pPrt->PLinkSpeedUsed; continue; } /* - * If we find an active port with a different flow - * control status than the first one, we return a - * value that indicates that the status is - * indeterminated. + * If we find an active port with a different link speed used + * than the first one we return indeterminated. */ - if (*pBuf != pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed) { + if (*pBuf != pPrt->PLinkSpeedUsed) { *pBuf = SK_LSPEED_STAT_INDETERMINATED; } @@ -6586,9 +6191,7 @@ char *pBuf) /* Buffer to which to mgmt data will be retrieved */ } } - /* - * If no port is active return an indeterminated answer - */ + /* If no port is active return an indeterminated answer. */ if (!PortActiveFlag) { switch (Id) { @@ -6617,7 +6220,7 @@ char *pBuf) /* Buffer to which to mgmt data will be retrieved */ case OID_SKGE_FLOWCTRL_STATUS: *pBuf = SK_FLOW_STAT_INDETERMINATED; break; - + case OID_SKGE_PHY_OPERATION_CAP: *pBuf = SK_MS_CAP_INDETERMINATED; break; @@ -6666,7 +6269,6 @@ unsigned int PhysPortIndex) /* Physical port index */ { SK_U8 Result; - if (!pAC->GIni.GP[PhysPortIndex].PHWLinkUp) { Result = SK_PNMI_RLMT_LSTAT_PHY_DOWN; @@ -6706,17 +6308,15 @@ unsigned int PhysPortIndex) /* Physical port index */ { SK_U8 Result; - - /* Get the current mode, which can be full or half duplex */ + /* Get the current mode, which can be full or half duplex. */ Result = pAC->GIni.GP[PhysPortIndex].PLinkModeStatus; - /* Check if no valid mode could be found (link is down) */ + /* Check if no valid mode could be found (link is down). */ if (Result < SK_LMODE_STAT_HALF) { Result = SK_LMODE_STAT_UNKNOWN; } else if (pAC->GIni.GP[PhysPortIndex].PLinkMode >= SK_LMODE_AUTOHALF) { - /* * Auto-negotiation was used to bring up the link. Change * the already found duplex status that it indicates @@ -6761,22 +6361,22 @@ unsigned int *pKeyNo) /* Number of keys */ int Index; int Ret; - SK_MEMSET(pKeyArr, 0, KeyArrLen); - /* - * Get VPD key list - */ - Ret = VpdKeys(pAC, IoC, (char *)&BufKeys, (int *)&BufKeysLen, + /* Get VPD key list. */ + Ret = VpdKeys(pAC, IoC, BufKeys, (int *)&BufKeysLen, (int *)pKeyNo); + if (Ret > 0) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR014, - SK_PNMI_ERR014MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR014MSG)); + /* Please read comment in Vpd(). */ + pAC->Pnmi.VpdKeyReadError = SK_TRUE; return (SK_PNMI_ERR_GENERAL); } - /* If no keys are available return now */ + /* If no keys are available return now. */ if (*pKeyNo == 0 || BufKeysLen == 0) { return (SK_PNMI_ERR_OK); @@ -6784,12 +6384,12 @@ unsigned int *pKeyNo) /* Number of keys */ /* * If the key list is too long for us trunc it and give a * errorlog notification. This case should not happen because - * the maximum number of keys is limited due to RAM limitations + * the maximum number of keys is limited due to RAM limitations. */ if (*pKeyNo > SK_PNMI_VPD_ENTRIES) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR015, - SK_PNMI_ERR015MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR015MSG)); *pKeyNo = SK_PNMI_VPD_ENTRIES; } @@ -6802,14 +6402,14 @@ unsigned int *pKeyNo) /* Number of keys */ Offset ++) { if (BufKeys[Offset] != 0) { - continue; } if (Offset - StartOffset > SK_PNMI_VPD_KEY_SIZE) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR016, - SK_PNMI_ERR016MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + (SK_PNMI_ERR016MSG)); + return (SK_PNMI_ERR_GENERAL); } @@ -6820,7 +6420,7 @@ unsigned int *pKeyNo) /* Number of keys */ StartOffset = Offset + 1; } - /* Last key not zero terminated? Get it anyway */ + /* Last key not zero terminated? Get it anyway. */ if (StartOffset < Offset) { SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE, @@ -6849,19 +6449,18 @@ SK_IOC IoC) /* IO context handle */ { SK_EVPARA EventParam; - /* Was the module already updated during the current PNMI call? */ if (pAC->Pnmi.SirqUpdatedFlag > 0) { return (SK_PNMI_ERR_OK); } - /* Send an synchronuous update event to the module */ + /* Send an synchronuous update event to the module. */ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); - if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam) > 0) { + + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam)) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047, - SK_PNMI_ERR047MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047, SK_PNMI_ERR047MSG); return (SK_PNMI_ERR_GENERAL); } @@ -6889,21 +6488,19 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ { SK_EVPARA EventParam; - /* Was the module already updated during the current PNMI call? */ if (pAC->Pnmi.RlmtUpdatedFlag > 0) { return (SK_PNMI_ERR_OK); } - /* Send an synchronuous update event to the module */ + /* Send an synchronuous update event to the module. */ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); EventParam.Para32[0] = NetIndex; EventParam.Para32[1] = (SK_U32)-1; if (SkRlmtEvent(pAC, IoC, SK_RLMT_STATS_UPDATE, EventParam) > 0) { - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048, - SK_PNMI_ERR048MSG); + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048, SK_PNMI_ERR048MSG); return (SK_PNMI_ERR_GENERAL); } @@ -6917,8 +6514,8 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * * Description: * The XMAC holds its statistic internally. To obtain the current - * values we send a command so that the statistic data will - * be written to apredefined memory area on the adapter. + * values we must send a command so that the statistic data will + * be written to a predefined memory area on the adapter. * * Returns: * SK_PNMI_ERR_OK Task successfully performed. @@ -6941,20 +6538,20 @@ unsigned int LastMac) /* Index of the last Mac to be updated */ return (SK_PNMI_ERR_OK); } - /* Send an update command to all MACs specified */ + /* Send an update command to all MACs specified. */ for (MacIndex = FirstMac; MacIndex <= LastMac; MacIndex ++) { /* - * 2002-09-13 pweber: Freeze the current sw counters. + * 2002-09-13 pweber: Freeze the current SW counters. * (That should be done as close as * possible to the update of the - * hw counters) + * HW counters). */ if (pAC->GIni.GIMacType == SK_MAC_XMAC) { pAC->Pnmi.BufPort[MacIndex] = pAC->Pnmi.Port[MacIndex]; } - - /* 2002-09-13 pweber: Update the hw counter */ + + /* 2002-09-13 pweber: Update the HW counter. */ if (pAC->GIni.GIFunc.pFnMacUpdateStats(pAC, IoC, MacIndex) != 0) { return (SK_PNMI_ERR_GENERAL); @@ -6992,34 +6589,35 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ SK_U64 Val = 0; - if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */ PhysPortIndex = NetIndex; + Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex); } - else { /* Single Net mode */ + else { /* SingleNet mode. */ if (LogPortIndex == 0) { PhysPortMax = pAC->GIni.GIMacsFound; - /* Add counter of all active ports */ + /* Add counter of all active ports. */ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; PhysPortIndex ++) { if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { - Val += GetPhysStatVal(pAC, IoC, PhysPortIndex, - StatIndex); + Val += GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex); } } - /* Correct value because of port switches */ + /* Correct value because of port switches. */ Val += pAC->Pnmi.VirtualCounterOffset[StatIndex]; } else { - /* Get counter value of physical port */ + /* Get counter value of physical port. */ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex); + Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex); } } @@ -7053,33 +6651,68 @@ unsigned int StatIndex) /* Index to statistic value */ SK_U32 HighVal = 0; SK_U16 Word; int MacType; - + unsigned int HelpIndex; + SK_GEPORT *pPrt; + SK_PNMI_PORT *pPnmiPrt; SK_GEMACFUNC *pFnMac; - + + pPrt = &pAC->GIni.GP[PhysPortIndex]; + MacType = pAC->GIni.GIMacType; - - /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ - if (pAC->GIni.GIMacType == SK_MAC_XMAC) { + + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */ + if (MacType == SK_MAC_XMAC) { pPnmiPrt = &pAC->Pnmi.BufPort[PhysPortIndex]; } else { pPnmiPrt = &pAC->Pnmi.Port[PhysPortIndex]; } - + pFnMac = &pAC->GIni.GIFunc; switch (StatIndex) { case SK_PNMI_HTX: - case SK_PNMI_HRX: - /* Not supported by GMAC */ if (MacType == SK_MAC_GMAC) { - return (Val); + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[SK_PNMI_HTX_BROADCAST][MacType].Reg, + &LowVal); + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[SK_PNMI_HTX_MULTICAST][MacType].Reg, + &HighVal); + LowVal += HighVal; + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[SK_PNMI_HTX_UNICAST][MacType].Reg, + &HighVal); + LowVal += HighVal; + } + else { + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + } + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + case SK_PNMI_HRX: + if (MacType == SK_MAC_GMAC) { + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[SK_PNMI_HRX_BROADCAST][MacType].Reg, + &LowVal); + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[SK_PNMI_HRX_MULTICAST][MacType].Reg, + &HighVal); + LowVal += HighVal; + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[SK_PNMI_HRX_UNICAST][MacType].Reg, + &HighVal); + LowVal += HighVal; + } + else { + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); } - - (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, - StatAddr[StatIndex][MacType].Reg, - &LowVal); HighVal = pPnmiPrt->CounterHigh[StatIndex]; break; @@ -7096,7 +6729,7 @@ unsigned int StatIndex) /* Index to statistic value */ case SK_PNMI_HTX_BURST: case SK_PNMI_HTX_EXCESS_DEF: case SK_PNMI_HTX_CARRIER: - /* Not supported by GMAC */ + /* Not supported by GMAC. */ if (MacType == SK_MAC_GMAC) { return (Val); } @@ -7108,22 +6741,24 @@ unsigned int StatIndex) /* Index to statistic value */ break; case SK_PNMI_HTX_MACC: - /* GMAC only supports PAUSE MAC control frames */ + /* GMAC only supports PAUSE MAC control frames. */ if (MacType == SK_MAC_GMAC) { - Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, SK_PNMI_HTX_PMACC); - - return (Val); + HelpIndex = SK_PNMI_HTX_PMACC; } - + else { + HelpIndex = StatIndex; + } + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, - StatAddr[StatIndex][MacType].Reg, - &LowVal); + StatAddr[HelpIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; break; case SK_PNMI_HTX_COL: case SK_PNMI_HRX_UNDERSIZE: - /* Not supported by XMAC */ + /* Not supported by XMAC. */ if (MacType == SK_MAC_XMAC) { return (Val); } @@ -7134,21 +6769,20 @@ unsigned int StatIndex) /* Index to statistic value */ HighVal = pPnmiPrt->CounterHigh[StatIndex]; break; - case SK_PNMI_HTX_DEFFERAL: - /* Not supported by GMAC */ + /* Not supported by GMAC. */ if (MacType == SK_MAC_GMAC) { return (Val); } - + /* * XMAC counts frames with deferred transmission * even in full-duplex mode. * * In full-duplex mode the counter remains constant! */ - if ((pAC->GIni.GP[PhysPortIndex].PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) || - (pAC->GIni.GP[PhysPortIndex].PLinkModeStatus == SK_LMODE_STAT_FULL)) { + if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) || + (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL)) { LowVal = 0; HighVal = 0; @@ -7156,14 +6790,14 @@ unsigned int StatIndex) /* Index to statistic value */ else { /* Otherwise get contents of hardware register. */ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, - StatAddr[SK_PNMI_HTX_DEFFERAL][MacType].Reg, + StatAddr[StatIndex][MacType].Reg, &LowVal); HighVal = pPnmiPrt->CounterHigh[StatIndex]; } break; case SK_PNMI_HRX_BADOCTET: - /* Not supported by XMAC */ + /* Not supported by XMAC. */ if (MacType == SK_MAC_XMAC) { return (Val); } @@ -7173,7 +6807,7 @@ unsigned int StatIndex) /* Index to statistic value */ &HighVal); (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, StatAddr[StatIndex + 1][MacType].Reg, - &LowVal); + &LowVal); break; case SK_PNMI_HTX_OCTETLOW: @@ -7182,32 +6816,30 @@ unsigned int StatIndex) /* Index to statistic value */ return (Val); case SK_PNMI_HRX_LONGFRAMES: - /* For XMAC the SW counter is managed by PNMI */ + /* For XMAC the SW counter is managed by PNMI. */ if (MacType == SK_MAC_XMAC) { return (pPnmiPrt->StatRxLongFrameCts); } - + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, StatAddr[StatIndex][MacType].Reg, &LowVal); HighVal = pPnmiPrt->CounterHigh[StatIndex]; break; - + case SK_PNMI_HRX_TOO_LONG: (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, - StatAddr[StatIndex][MacType].Reg, + StatAddr[StatIndex][MacType].Reg, &LowVal); HighVal = pPnmiPrt->CounterHigh[StatIndex]; - + Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal); - switch (MacType) { - case SK_MAC_GMAC: - /* For GMAC the SW counter is additionally managed by PNMI */ + if (MacType == SK_MAC_GMAC) { + /* For GMAC the SW counter is additionally managed by PNMI. */ Val += pPnmiPrt->StatRxFrameTooLongCts; - break; - - case SK_MAC_XMAC: + } + else { /* * Frames longer than IEEE 802.3 frame max size are counted * by XMAC in frame_too_long counter even reception of long @@ -7215,31 +6847,26 @@ unsigned int StatIndex) /* Index to statistic value */ * So correct the value by subtracting RxLongFrame counter. */ Val -= pPnmiPrt->StatRxLongFrameCts; - break; - - default: - break; } LowVal = (SK_U32)Val; HighVal = (SK_U32)(Val >> 32); break; - + case SK_PNMI_HRX_SHORTS: - /* Not supported by GMAC */ + /* Not supported by GMAC. */ if (MacType == SK_MAC_GMAC) { /* GM_RXE_FRAG?? */ return (Val); } - + /* - * XMAC counts short frame errors even if link down (#10620) - * - * If link-down the counter remains constant + * XMAC counts short frame errors even if link down (#10620). + * If the link is down, the counter remains constant. */ - if (pAC->GIni.GP[PhysPortIndex].PLinkModeStatus != SK_LMODE_STAT_UNKNOWN) { + if (pPrt->PLinkModeStatus != SK_LMODE_STAT_UNKNOWN) { - /* Otherwise get incremental difference */ + /* Otherwise get incremental difference. */ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, StatAddr[StatIndex][MacType].Reg, &LowVal); @@ -7262,9 +6889,8 @@ unsigned int StatIndex) /* Index to statistic value */ case SK_PNMI_HRX_IRLENGTH: case SK_PNMI_HRX_SYMBOL: case SK_PNMI_HRX_CEXT: - /* Not supported by GMAC */ + /* Not supported by GMAC. */ if (MacType == SK_MAC_GMAC) { - /* GM_RXE_FRAG?? */ return (Val); } @@ -7275,24 +6901,24 @@ unsigned int StatIndex) /* Index to statistic value */ break; case SK_PNMI_HRX_PMACC_ERR: - /* For GMAC the SW counter is managed by PNMI */ + /* For GMAC the SW counter is managed by PNMI. */ if (MacType == SK_MAC_GMAC) { return (pPnmiPrt->StatRxPMaccErr); } - + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, StatAddr[StatIndex][MacType].Reg, &LowVal); HighVal = pPnmiPrt->CounterHigh[StatIndex]; break; - /* SW counter managed by PNMI */ + /* SW counter managed by PNMI. */ case SK_PNMI_HTX_SYNC: LowVal = (SK_U32)pPnmiPrt->StatSyncCts; HighVal = (SK_U32)(pPnmiPrt->StatSyncCts >> 32); break; - /* SW counter managed by PNMI */ + /* SW counter managed by PNMI. */ case SK_PNMI_HTX_SYNC_OCTET: LowVal = (SK_U32)pPnmiPrt->StatSyncOctetsCts; HighVal = (SK_U32)(pPnmiPrt->StatSyncOctetsCts >> 32); @@ -7300,19 +6926,19 @@ unsigned int StatIndex) /* Index to statistic value */ case SK_PNMI_HRX_FCS: /* - * Broadcom filters fcs errors and counts it in - * Receive Error Counter register + * Broadcom filters FCS errors and counts them in + * Receive Error Counter register. */ - if (pAC->GIni.GP[PhysPortIndex].PhyType == SK_PHY_BCOM) { - /* do not read while not initialized (PHY_READ hangs!)*/ - if (pAC->GIni.GP[PhysPortIndex].PState) { - PHY_READ(IoC, &pAC->GIni.GP[PhysPortIndex], - PhysPortIndex, PHY_BCOM_RE_CTR, - &Word); - + if (pPrt->PhyType == SK_PHY_BCOM) { +#ifdef GENESIS + /* Do not read while not initialized (PHY_READ hangs!). */ + if (pPrt->PState != SK_PRT_RESET) { + SkXmPhyRead(pAC, IoC, PhysPortIndex, PHY_BCOM_RE_CTR, &Word); + LowVal = Word; } HighVal = pPnmiPrt->CounterHigh[StatIndex]; +#endif /* GENESIS */ } else { (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, @@ -7332,7 +6958,7 @@ unsigned int StatIndex) /* Index to statistic value */ Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal); - /* Correct value because of possible XMAC reset. XMAC Errata #2 */ + /* Correct value because of possible XMAC reset (XMAC Errata #2). */ Val += pPnmiPrt->CounterOffset[StatIndex]; return (Val); @@ -7357,30 +6983,29 @@ SK_U32 NetIndex) unsigned int PhysPortIndex; SK_EVPARA EventParam; - SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); - /* Notify sensor module */ + /* Notify sensor module. */ SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_CLEAR, EventParam); - /* Notify RLMT module */ + /* Notify RLMT module. */ EventParam.Para32[0] = NetIndex; EventParam.Para32[1] = (SK_U32)-1; SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STATS_CLEAR, EventParam); EventParam.Para32[1] = 0; - /* Notify SIRQ module */ + /* Notify SIRQ module. */ SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_CLEAR_STAT, EventParam); - /* Notify CSUM module */ + /* Notify CSUM module. */ #ifdef SK_USE_CSUM EventParam.Para32[0] = NetIndex; EventParam.Para32[1] = (SK_U32)-1; SkEventQueue(pAC, SKGE_CSUM, SK_CSUM_EVENT_CLEAR_PROTO_STATS, EventParam); -#endif - - /* Clear XMAC statistic */ +#endif /* SK_USE_CSUM */ + + /* Clear XMAC statistics. */ for (PhysPortIndex = 0; PhysPortIndex < (unsigned int)pAC->GIni.GIMacsFound; PhysPortIndex ++) { @@ -7407,13 +7032,13 @@ SK_U32 NetIndex) PhysPortIndex].StatRxPMaccErr)); } - /* - * Clear local statistics - */ + /* Clear local statistics. */ SK_MEMSET((char *)&pAC->Pnmi.VirtualCounterOffset, 0, sizeof(pAC->Pnmi.VirtualCounterOffset)); + pAC->Pnmi.RlmtChangeCts = 0; pAC->Pnmi.RlmtChangeTime = 0; + SK_MEMSET((char *)&pAC->Pnmi.RlmtChangeEstimate.EstValue[0], 0, sizeof(pAC->Pnmi.RlmtChangeEstimate.EstValue)); pAC->Pnmi.RlmtChangeEstimate.EstValueIndex = 0; @@ -7450,23 +7075,21 @@ SK_AC *pAC, /* Pointer to adapter context */ SK_U32 TrapId, /* SNMP ID of the trap */ unsigned int Size) /* Space needed for trap entry */ { - unsigned int BufPad = pAC->Pnmi.TrapBufPad; - unsigned int BufFree = pAC->Pnmi.TrapBufFree; - unsigned int Beg = pAC->Pnmi.TrapQueueBeg; - unsigned int End = pAC->Pnmi.TrapQueueEnd; + unsigned int BufPad = pAC->Pnmi.TrapBufPad; + unsigned int BufFree = pAC->Pnmi.TrapBufFree; + unsigned int Beg = pAC->Pnmi.TrapQueueBeg; + unsigned int End = pAC->Pnmi.TrapQueueEnd; char *pBuf = &pAC->Pnmi.TrapBuf[0]; int Wrap; - unsigned int NeededSpace; - unsigned int EntrySize; + unsigned int NeededSpace; + unsigned int EntrySize; SK_U32 Val32; SK_U64 Val64; - - /* Last byte of entry will get a copy of the entry length */ + /* Last byte of entry will get a copy of the entry length. */ Size ++; - /* - * Calculate needed buffer space */ + /* Calculate needed buffer space. */ if (Beg >= Size) { NeededSpace = Size; @@ -7481,7 +7104,7 @@ unsigned int Size) /* Space needed for trap entry */ * Check if enough buffer space is provided. Otherwise * free some entries. Leave one byte space between begin * and end of buffer to make it possible to detect whether - * the buffer is full or empty + * the buffer is full or empty. */ while (BufFree < NeededSpace + 1) { @@ -7495,11 +7118,11 @@ unsigned int Size) /* Space needed for trap entry */ End -= EntrySize; #ifdef DEBUG SK_MEMSET(pBuf + End, (char)(-1), EntrySize); -#endif +#endif /* DEBUG */ if (End == BufPad) { #ifdef DEBUG SK_MEMSET(pBuf, (char)(-1), End); -#endif +#endif /* DEBUG */ BufFree += End; End = 0; BufPad = 0; @@ -7520,13 +7143,13 @@ unsigned int Size) /* Space needed for trap entry */ } BufFree -= NeededSpace; - /* Save the current offsets */ + /* Save the current offsets. */ pAC->Pnmi.TrapQueueBeg = Beg; pAC->Pnmi.TrapQueueEnd = End; pAC->Pnmi.TrapBufPad = BufPad; pAC->Pnmi.TrapBufFree = BufFree; - /* Initialize the trap entry */ + /* Initialize the trap entry. */ *(pBuf + Beg + Size - 1) = (char)Size; *(pBuf + Beg) = (char)Size; Val32 = (pAC->Pnmi.TrapUnique) ++; @@ -7561,7 +7184,6 @@ char *pDstBuf) /* Buffer to which the queued traps will be copied */ unsigned int Len; unsigned int DstOff = 0; - while (Trap != End) { Len = (unsigned int)*(pBuf + Trap); @@ -7606,7 +7228,6 @@ unsigned int *pEntries) /* Returns number of trapes stored in queue */ unsigned int Entries = 0; unsigned int TotalLen = 0; - while (Trap != End) { Len = (unsigned int)*(pBuf + Trap); @@ -7663,21 +7284,21 @@ unsigned int SensorIndex) /* Index of sensor which caused the trap */ unsigned int DescrLen; SK_U32 Val32; - - /* Get trap buffer entry */ + /* Get trap buffer entry. */ DescrLen = SK_STRLEN(pAC->I2c.SenTable[SensorIndex].SenDesc); + pBuf = GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_SENSOR_LEN_BASE + DescrLen); Offset = SK_PNMI_TRAP_SIMPLE_LEN; - /* Store additionally sensor trap related data */ + /* Store additionally sensor trap related data. */ Val32 = OID_SKGE_SENSOR_INDEX; SK_PNMI_STORE_U32(pBuf + Offset, Val32); *(pBuf + Offset + 4) = 4; Val32 = (SK_U32)SensorIndex; SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32); Offset += 9; - + Val32 = (SK_U32)OID_SKGE_SENSOR_DESCR; SK_PNMI_STORE_U32(pBuf + Offset, Val32); *(pBuf + Offset + 4) = (char)DescrLen; @@ -7715,7 +7336,6 @@ unsigned int ActiveMac) /* Index (0..n) of the currently active port */ char *pBuf; SK_U32 Val32; - pBuf = GetTrapEntry(pAC, OID_SKGE_TRAP_RLMT_CHANGE_PORT, SK_PNMI_TRAP_RLMT_CHANGE_LEN); @@ -7743,7 +7363,6 @@ unsigned int PortIndex) /* Index of the port, which changed its state */ char *pBuf; SK_U32 Val32; - pBuf = GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_RLMT_PORT_LEN); Val32 = OID_SKGE_RLMT_PORT_INDEX; @@ -7763,19 +7382,17 @@ unsigned int PortIndex) /* Index of the port, which changed its state */ * Nothing */ PNMI_STATIC void CopyMac( -char *pDst, /* Pointer to destination buffer */ +char *pDst, /* Pointer to destination buffer */ SK_MAC_ADDR *pMac) /* Pointer of Source */ { int i; - for (i = 0; i < sizeof(SK_MAC_ADDR); i ++) { *(pDst + i) = pMac->a[i]; } } - #ifdef SK_POWER_MGMT /***************************************************************************** * @@ -7806,60 +7423,64 @@ SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ unsigned int TableIndex, /* Index to the Id table */ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ { - + + int i; + unsigned int HwPortIndex; + SK_U32 RetCode = SK_PNMI_ERR_GENERAL; - /* - * Check instance. We only handle single instance variables - */ - if (Instance != (SK_U32)(-1) && Instance != 1) { + /* Check instance. We only handle single instance variables. */ + if ((Instance != (SK_U32)(-1))) { *pLen = 0; return (SK_PNMI_ERR_UNKNOWN_INST); } - /* - * Perform action - */ + /* Get hardware port index */ + HwPortIndex = NetIndex; + + /* Check length. */ + switch (Id) { + + case OID_PNP_CAPABILITIES: + if (*pLen < sizeof(SK_PNP_CAPABILITIES)) { + + *pLen = sizeof(SK_PNP_CAPABILITIES); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_PNP_SET_POWER: + case OID_PNP_QUERY_POWER: + if (*pLen < sizeof(SK_DEVICE_POWER_STATE)) + { + *pLen = sizeof(SK_DEVICE_POWER_STATE); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_PNP_ADD_WAKE_UP_PATTERN: + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + if (*pLen < sizeof(SK_PM_PACKET_PATTERN)) { + + *pLen = sizeof(SK_PM_PACKET_PATTERN); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_PNP_ENABLE_WAKE_UP: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + } + + /* Perform action. */ if (Action == SK_PNMI_GET) { - /* - * Check length - */ - switch (Id) { - - case OID_PNP_CAPABILITIES: - if (*pLen < sizeof(SK_PNP_CAPABILITIES)) { - - *pLen = sizeof(SK_PNP_CAPABILITIES); - return (SK_PNMI_ERR_TOO_SHORT); - } - break; - - case OID_PNP_QUERY_POWER: - case OID_PNP_ENABLE_WAKE_UP: - if (*pLen < sizeof(SK_U32)) { - - *pLen = sizeof(SK_U32); - return (SK_PNMI_ERR_TOO_SHORT); - } - break; - - case OID_PNP_SET_POWER: - case OID_PNP_ADD_WAKE_UP_PATTERN: - case OID_PNP_REMOVE_WAKE_UP_PATTERN: - break; - - default: - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR040, - SK_PNMI_ERR040MSG); - *pLen = 0; - return (SK_PNMI_ERR_GENERAL); - } - - /* - * Get value - */ + /* Get value. */ switch (Id) { case OID_PNP_CAPABILITIES: @@ -7867,27 +7488,31 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ break; case OID_PNP_QUERY_POWER: - /* The Windows DDK describes: An OID_PNP_QUERY_POWER requests - the miniport to indicate whether it can transition its NIC - to the low-power state. - A miniport driver must always return NDIS_STATUS_SUCCESS - to a query of OID_PNP_QUERY_POWER. */ - RetCode = SK_PNMI_ERR_OK; + /* + * The Windows DDK describes: An OID_PNP_QUERY_POWER requests + * the miniport to indicate whether it can transition its NIC + * to the low-power state. + * A miniport driver must always return NDIS_STATUS_SUCCESS + * to a query of OID_PNP_QUERY_POWER. + */ + *pLen = sizeof(SK_DEVICE_POWER_STATE); + RetCode = SK_PNMI_ERR_OK; break; - /* NDIS handles these OIDs as write-only. + /* + * NDIS handles these OIDs as write-only. * So in case of get action the buffer with written length = 0 - * is returned + * is returned. */ case OID_PNP_SET_POWER: case OID_PNP_ADD_WAKE_UP_PATTERN: case OID_PNP_REMOVE_WAKE_UP_PATTERN: - *pLen = 0; - RetCode = SK_PNMI_ERR_OK; + *pLen = 0; + RetCode = SK_PNMI_ERR_NOT_SUPPORTED; break; case OID_PNP_ENABLE_WAKE_UP: - RetCode = SkPowerGetEnableWakeUp(pAC, IoC, pBuf, pLen); + RetCode = SkPowerGetEnableWakeUp(pAC, IoC, HwPortIndex, pBuf, pLen); break; default: @@ -7897,78 +7522,256 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ return (RetCode); } + + /* Perform PRESET or SET. */ + + /* The POWER module does not support PRESET action. */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + /* */ + i= HwPortIndex; - /* - * From here SET or PRESET action. Check if the passed - * buffer length is plausible. - */ switch (Id) { case OID_PNP_SET_POWER: + /* Dual net mode? */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + if (RetCode = SkPowerSetPower(pAC, IoC, i, pBuf, pLen)) { + break; + } + } + break; + + case OID_PNP_ADD_WAKE_UP_PATTERN: + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + if (RetCode = SkPowerAddWakeUpPattern(pAC, IoC, i, pBuf, pLen)) { + break; + } + } + break; + + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + if (RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, i, pBuf, pLen)) { + break; + } + } + break; + case OID_PNP_ENABLE_WAKE_UP: + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + if (RetCode = SkPowerSetEnableWakeUp(pAC, IoC, i, pBuf, pLen)) { + break; + } + } + break; + + default: + RetCode = SK_PNMI_ERR_READ_ONLY; + } + + return (RetCode); +} +#endif /* SK_POWER_MGMT */ + +#ifdef SK_DIAG_SUPPORT +/***************************************************************************** + * + * DiagActions - OID handler function of Diagnostic driver + * + * Description: + * The code is simple. No description necessary. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ + +PNMI_STATIC int DiagActions( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* GET/PRESET/SET action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ +{ + SK_U32 DiagStatus; + SK_U32 RetCode = SK_PNMI_ERR_GENERAL; + + /* Check instance. We only handle single instance variables. */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* Check length. */ + switch (Id) { + + case OID_SKGE_DIAG_MODE: if (*pLen < sizeof(SK_U32)) { *pLen = sizeof(SK_U32); return (SK_PNMI_ERR_TOO_SHORT); } - if (*pLen != sizeof(SK_U32)) { - - *pLen = 0; - return (SK_PNMI_ERR_BAD_VALUE); - } - break; - - case OID_PNP_ADD_WAKE_UP_PATTERN: - case OID_PNP_REMOVE_WAKE_UP_PATTERN: - if (*pLen < sizeof(SK_PM_PACKET_PATTERN)) { - - *pLen = 0; - return (SK_PNMI_ERR_BAD_VALUE); - } - break; - - default: - *pLen = 0; - return (SK_PNMI_ERR_READ_ONLY); - } - - /* - * Perform preset or set - */ - - /* POWER module does not support PRESET action */ - if (Action == SK_PNMI_PRESET) { - return (SK_PNMI_ERR_OK); - } - - switch (Id) { - case OID_PNP_SET_POWER: - RetCode = SkPowerSetPower(pAC, IoC, pBuf, pLen); - break; - - case OID_PNP_ADD_WAKE_UP_PATTERN: - RetCode = SkPowerAddWakeUpPattern(pAC, IoC, pBuf, pLen); - break; - - case OID_PNP_REMOVE_WAKE_UP_PATTERN: - RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, pBuf, pLen); - break; - - case OID_PNP_ENABLE_WAKE_UP: - RetCode = SkPowerSetEnableWakeUp(pAC, IoC, pBuf, pLen); break; default: - RetCode = SK_PNMI_ERR_GENERAL; + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR040, SK_PNMI_ERR040MSG); + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); } + /* Perform action. */ + if (Action == SK_PNMI_GET) { + + /* Get value. */ + switch (Id) { + + case OID_SKGE_DIAG_MODE: + DiagStatus = pAC->Pnmi.DiagAttached; + SK_PNMI_STORE_U32(pBuf, DiagStatus); + *pLen = sizeof(SK_U32); + RetCode = SK_PNMI_ERR_OK; + break; + + default: + *pLen = 0; + RetCode = SK_PNMI_ERR_GENERAL; + break; + } + return (RetCode); + } + + /* From here SET or PRESET value. */ + + /* PRESET value is not supported. */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + /* SET value. */ + switch (Id) { + case OID_SKGE_DIAG_MODE: + + /* Handle the SET. */ + switch (*pBuf) { + + /* Attach the DIAG to this adapter. */ + case SK_DIAG_ATTACHED: + /* Check if we come from running. */ + if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) { + + RetCode = SkDrvLeaveDiagMode(pAC); + + } + else if (pAC->Pnmi.DiagAttached == SK_DIAG_IDLE) { + + RetCode = SK_PNMI_ERR_OK; + } + + else { + + RetCode = SK_PNMI_ERR_GENERAL; + + } + + if (RetCode == SK_PNMI_ERR_OK) { + + pAC->Pnmi.DiagAttached = SK_DIAG_ATTACHED; + } + break; + + /* Enter the DIAG mode in the driver. */ + case SK_DIAG_RUNNING: + RetCode = SK_PNMI_ERR_OK; + + /* + * If DiagAttached is set, we can tell the driver + * to enter the DIAG mode. + */ + if (pAC->Pnmi.DiagAttached == SK_DIAG_ATTACHED) { + /* If DiagMode is not active, we can enter it. */ + if (!pAC->DiagModeActive) { + + RetCode = SkDrvEnterDiagMode(pAC); + } + else { + + RetCode = SK_PNMI_ERR_GENERAL; + } + } + else { + + RetCode = SK_PNMI_ERR_GENERAL; + } + + if (RetCode == SK_PNMI_ERR_OK) { + + pAC->Pnmi.DiagAttached = SK_DIAG_RUNNING; + } + break; + + case SK_DIAG_IDLE: + /* Check if we come from running. */ + if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) { + + RetCode = SkDrvLeaveDiagMode(pAC); + + } + else if (pAC->Pnmi.DiagAttached == SK_DIAG_ATTACHED) { + + RetCode = SK_PNMI_ERR_OK; + } + + else { + + RetCode = SK_PNMI_ERR_GENERAL; + + } + + if (RetCode == SK_PNMI_ERR_OK) { + + pAC->Pnmi.DiagAttached = SK_DIAG_IDLE; + } + break; + + default: + RetCode = SK_PNMI_ERR_BAD_VALUE; + break; + } + break; + + default: + RetCode = SK_PNMI_ERR_GENERAL; + } + + if (RetCode == SK_PNMI_ERR_OK) { + *pLen = sizeof(SK_U32); + } + else { + + *pLen = 0; + } return (RetCode); } -#endif /* SK_POWER_MGMT */ - +#endif /* SK_DIAG_SUPPORT */ /***************************************************************************** * - * Vct - OID handler function of OIDs + * Vct - OID handler function of OIDs for Virtual Cable Tester (VCT) * * Description: * The code is simple. No description necessary. @@ -7980,7 +7783,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ * the correct data (e.g. a 32bit value is * needed, but a 16 bit value was passed). * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't - * exist (e.g. port instance 3 on a two port + * exist (e.g. port instance 3 on a two port * adapter). * SK_PNMI_ERR_READ_ONLY Only the Get action is allowed. * @@ -7989,10 +7792,10 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ PNMI_STATIC int Vct( SK_AC *pAC, /* Pointer to adapter context */ SK_IOC IoC, /* IO context handle */ -int Action, /* Get/PreSet/Set action */ +int Action, /* GET/PRESET/SET action */ SK_U32 Id, /* Object ID that is to be processed */ -char *pBuf, /* Buffer to which the mgmt data will be copied */ -unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ SK_U32 Instance, /* Instance (-1,2..n) that is to be queried */ unsigned int TableIndex, /* Index to the Id table */ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ @@ -8004,15 +7807,13 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ SK_U32 PhysPortIndex; SK_U32 Limit; SK_U32 Offset; - SK_BOOL Link; - SK_U32 RetCode = SK_PNMI_ERR_GENERAL; - int i; + SK_U32 RetCode; + int i; SK_EVPARA Para; - SK_U32 CableLength; - /* - * Calculate the port indexes from the instance. - */ + RetCode = SK_PNMI_ERR_GENERAL; + + /* Calculate the port indexes from the instance. */ PhysPortMax = pAC->GIni.GIMacsFound; LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); @@ -8022,55 +7823,43 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ } if ((Instance != (SK_U32) (-1))) { - /* Check instance range. */ - if ((Instance < 2) || (Instance > LogPortMax)) { - *pLen = 0; - return (SK_PNMI_ERR_UNKNOWN_INST); - } - + /* + * Get one instance of that OID, so check the instance range: + * There is no virtual port with an Instance == 1, so we get + * the values from one physical port only. + */ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { PhysPortIndex = NetIndex; } else { + if ((Instance < 2) || (Instance > LogPortMax)) { + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } PhysPortIndex = Instance - 2; } Limit = PhysPortIndex + 1; } - else { /* - * Instance == (SK_U32) (-1), get all Instances of that OID. - * - * Not implemented yet. May be used in future releases. + else { + /* + * Instance == (SK_U32) (-1), so get all instances of that OID. + * There is no virtual port with an Instance == 1, so we get + * the values from all physical ports. */ PhysPortIndex = 0; Limit = PhysPortMax; } - pPrt = &pAC->GIni.GP[PhysPortIndex]; - if (pPrt->PHWLinkUp) { - Link = SK_TRUE; - } - else { - Link = SK_FALSE; - } - - /* - * Check MAC type. - */ - if (pPrt->PhyType != SK_PHY_MARV_COPPER) { + /* Check MAC type. */ + if ((Id != OID_SKGE_VCT_CAPABILITIES) && + (pAC->GIni.GP[PhysPortIndex].PhyType != SK_PHY_MARV_COPPER)) { *pLen = 0; - return (SK_PNMI_ERR_GENERAL); + return (SK_PNMI_ERR_NOT_SUPPORTED); } - /* Initialize backup data pointer. */ - pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex]; - - /* - * Check action type. - */ + /* Check action type. */ if (Action == SK_PNMI_GET) { - /* - * Check length. - */ + /* Check length. */ switch (Id) { case OID_SKGE_VCT_GET: @@ -8081,6 +7870,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ break; case OID_SKGE_VCT_STATUS: + case OID_SKGE_VCT_CAPABILITIES: if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U8)) { *pLen = (Limit - PhysPortIndex) * sizeof(SK_U8); return (SK_PNMI_ERR_TOO_SHORT); @@ -8090,63 +7880,53 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ default: *pLen = 0; return (SK_PNMI_ERR_GENERAL); - } + } - /* - * Get value. - */ + /* Get value. */ Offset = 0; for (; PhysPortIndex < Limit; PhysPortIndex++) { + + pPrt = &pAC->GIni.GP[PhysPortIndex]; + switch (Id) { case OID_SKGE_VCT_GET: - if ((Link == SK_FALSE) && + if (!pPrt->PHWLinkUp && (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING)) { - RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE); - if (RetCode == 0) { - pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING; - pAC->Pnmi.VctStatus[PhysPortIndex] |= - (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE); - /* Copy results for later use to PNMI struct. */ - for (i = 0; i < 4; i++) { - if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) { - if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] < 0xff)) { - pPrt->PMdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH; - } - } - if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] != 0xff)) { - CableLength = 1000 * (((175 * pPrt->PMdiPairLen[i]) / 210) - 28); - } - else { - CableLength = 0; - } - pVctBackupData->PMdiPairLen[i] = CableLength; - pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i]; - } + RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE); + + if (RetCode == 0) { + + /* VCT test is finished, so save the data. */ + VctGetResults(pAC, IoC, PhysPortIndex); Para.Para32[0] = PhysPortIndex; Para.Para32[1] = -1; SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para); - SkEventDispatcher(pAC, IoC); - } - else { - ; /* VCT test is running. */ + + /* SkEventDispatcher(pAC, IoC); */ } } + /* Initialize backup data pointer. */ + pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex]; + /* Get all results. */ CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex); - Offset += sizeof(SK_U8); + + Offset++; *(pBuf + Offset) = pPrt->PCableLen; - Offset += sizeof(SK_U8); + Offset++; for (i = 0; i < 4; i++) { - SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->PMdiPairLen[i]); + + SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->MdiPairLen[i]); Offset += sizeof(SK_U32); } for (i = 0; i < 4; i++) { - *(pBuf + Offset) = pVctBackupData->PMdiPairSts[i]; - Offset += sizeof(SK_U8); + + *(pBuf + Offset) = pVctBackupData->MdiPairSts[i]; + Offset++; } RetCode = SK_PNMI_ERR_OK; @@ -8154,7 +7934,20 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ case OID_SKGE_VCT_STATUS: CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex); - Offset += sizeof(SK_U8); + + Offset++; + RetCode = SK_PNMI_ERR_OK; + break; + + case OID_SKGE_VCT_CAPABILITIES: + if (pPrt->PhyType != SK_PHY_MARV_COPPER) { + *(pBuf + Offset) = SK_PNMI_VCT_NOT_SUPPORTED; + } + else { + *(pBuf + Offset) = SK_PNMI_VCT_SUPPORTED; + } + Offset++; + RetCode = SK_PNMI_ERR_OK; break; @@ -8173,9 +7966,7 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ * buffer length is plausible. */ - /* - * Check length. - */ + /* Check length. */ switch (Id) { case OID_SKGE_VCT_SET: if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) { @@ -8189,36 +7980,39 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ return (SK_PNMI_ERR_GENERAL); } - /* - * Perform preset or set. - */ + /* Perform PRESET or SET. */ /* VCT does not support PRESET action. */ if (Action == SK_PNMI_PRESET) { + return (SK_PNMI_ERR_OK); } Offset = 0; for (; PhysPortIndex < Limit; PhysPortIndex++) { + + pPrt = &pAC->GIni.GP[PhysPortIndex]; + switch (Id) { case OID_SKGE_VCT_SET: /* Start VCT test. */ - if (Link == SK_FALSE) { + if (!pPrt->PHWLinkUp) { SkGeStopPort(pAC, IoC, PhysPortIndex, SK_STOP_ALL, SK_SOFT_RST); RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_TRUE); + if (RetCode == 0) { /* RetCode: 0 => Start! */ pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_PENDING; - pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_NEW_VCT_DATA; - pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_LINK; + pAC->Pnmi.VctStatus[PhysPortIndex] &= + ~(SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_LINK); - /* - * Start VCT timer counter. - */ - SK_MEMSET((char *) &Para, 0, sizeof(Para)); + /* Start VCT timer counter. */ + SK_MEMSET((char *)&Para, 0, sizeof(Para)); Para.Para32[0] = PhysPortIndex; Para.Para32[1] = -1; - SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer, - 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para); + + SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex], + SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para); + SK_PNMI_STORE_U32((pBuf + Offset), RetCode); RetCode = SK_PNMI_ERR_OK; } @@ -8246,6 +8040,65 @@ SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ } /* Vct */ +PNMI_STATIC void VctGetResults( +SK_AC *pAC, +SK_IOC IoC, +SK_U32 Port) +{ + SK_GEPORT *pPrt; + int i; + SK_U8 PairLen; + SK_U8 PairSts; + SK_U32 MinLength; + SK_U32 CableLength; + + pPrt = &pAC->GIni.GP[Port]; + + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) { + MinLength = 25; + } + else { + MinLength = 35; + } + + /* Copy results for later use to PNMI struct. */ + for (i = 0; i < 4; i++) { + + PairLen = pPrt->PMdiPairLen[i]; + + if (((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) == 0) && (i > 1)) { + PairSts = SK_PNMI_VCT_NOT_PRESENT; + } + else { + PairSts = pPrt->PMdiPairSts[i]; + } + + if ((PairSts == SK_PNMI_VCT_NORMAL_CABLE) && + (PairLen > 28) && (PairLen < 0xff)) { + + PairSts = SK_PNMI_VCT_IMPEDANCE_MISMATCH; + } + + /* Ignore values <= MinLength, the linear factor is 4/5. */ + if ((PairLen > MinLength) && (PairLen < 0xff)) { + + CableLength = 1000UL * (PairLen - MinLength) * 4 / 5; + } + else { + /* No cable or short cable. */ + CableLength = 0; + } + + pAC->Pnmi.VctBackup[Port].MdiPairLen[i] = CableLength; + pAC->Pnmi.VctBackup[Port].MdiPairSts[i] = PairSts; + } + + pAC->Pnmi.VctStatus[Port] &= ~SK_PNMI_VCT_PENDING; + pAC->Pnmi.VctStatus[Port] |= (SK_PNMI_VCT_NEW_VCT_DATA | + SK_PNMI_VCT_TEST_DONE); + +} /* GetVctResults */ + PNMI_STATIC void CheckVctStatus( SK_AC *pAC, SK_IOC IoC, @@ -8255,19 +8108,21 @@ SK_U32 PhysPortIndex) { SK_GEPORT *pPrt; SK_PNMI_VCT *pVctData; + SK_U8 VctStatus; SK_U32 RetCode; - SK_U8 LinkSpeedUsed; pPrt = &pAC->GIni.GP[PhysPortIndex]; pVctData = (SK_PNMI_VCT *) (pBuf + Offset); pVctData->VctStatus = SK_PNMI_VCT_NONE; + VctStatus = pAC->Pnmi.VctStatus[PhysPortIndex]; + if (!pPrt->PHWLinkUp) { /* Was a VCT test ever made before? */ - if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) { - if ((pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_LINK)) { + if (VctStatus & SK_PNMI_VCT_TEST_DONE) { + if (VctStatus & SK_PNMI_VCT_LINK) { pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA; } else { @@ -8277,11 +8132,12 @@ SK_U32 PhysPortIndex) /* Check VCT test status. */ RetCode = SkGmCableDiagStatus(pAC,IoC, PhysPortIndex, SK_FALSE); + if (RetCode == 2) { /* VCT test is running. */ pVctData->VctStatus |= SK_PNMI_VCT_RUNNING; } else { /* VCT data was copied to pAC here. Check PENDING state. */ - if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) { + if (VctStatus & SK_PNMI_VCT_PENDING) { pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA; } } @@ -8291,20 +8147,185 @@ SK_U32 PhysPortIndex) } } else { - /* Was a VCT test ever made before? */ - if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) { + if (VctStatus & SK_PNMI_VCT_TEST_DONE) { pVctData->VctStatus &= ~SK_PNMI_VCT_NEW_VCT_DATA; pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA; } /* DSP only valid in 100/1000 modes. */ - LinkSpeedUsed = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed; - if (LinkSpeedUsed != SK_LSPEED_STAT_10MBPS) { + if (pPrt->PLinkSpeedUsed != SK_LSPEED_STAT_10MBPS) { pVctData->VctStatus |= SK_PNMI_VCT_NEW_DSP_DATA; } } } /* CheckVctStatus */ -#endif /* CONFIG_SK98 */ + +/***************************************************************************** + * + * SkPnmiGenIoctl - Handles new generic PNMI IOCTL, calls the needed + * PNMI function depending on the subcommand and + * returns all data belonging to the complete database + * or OID request. + * + * Description: + * Looks up the requested subcommand, calls the corresponding handler + * function and passes all required parameters to it. + * The function is called by the driver. It is needed to handle the new + * generic PNMI IOCTL. This IOCTL is given to the driver and contains both + * the OID and a subcommand to decide what kind of request has to be done. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed + * SK_PNMI_ERR_GENERAL A general severe internal error occured + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take + * the data. + * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +int SkPnmiGenIoctl( +SK_AC *pAC, /* Pointer to adapter context struct */ +SK_IOC IoC, /* I/O context */ +void *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* Length of buffer */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ +{ +SK_I32 Mode; /* Store value of subcommand. */ +SK_U32 Oid; /* Store value of OID. */ +int ReturnCode; /* Store return value to show status of PNMI action. */ +int HeaderLength; /* Length of desired action plus OID. */ + + ReturnCode = SK_PNMI_ERR_GENERAL; + + SK_MEMCPY(&Mode, pBuf, sizeof(SK_I32)); + SK_MEMCPY(&Oid, (char *)pBuf + sizeof(SK_I32), sizeof(SK_U32)); + HeaderLength = sizeof(SK_I32) + sizeof(SK_U32); + *pLen = *pLen - HeaderLength; + SK_MEMCPY((char *)pBuf + sizeof(SK_I32), (char *)pBuf + HeaderLength, *pLen); + + switch(Mode) { + case SK_GET_SINGLE_VAR: + ReturnCode = SkPnmiGetVar(pAC, IoC, Oid, + (char *)pBuf + sizeof(SK_I32), pLen, + ((SK_U32) (-1)), NetIndex); + SK_PNMI_STORE_U32(pBuf, ReturnCode); + *pLen = *pLen + sizeof(SK_I32); + break; + case SK_PRESET_SINGLE_VAR: + ReturnCode = SkPnmiPreSetVar(pAC, IoC, Oid, + (char *)pBuf + sizeof(SK_I32), pLen, + ((SK_U32) (-1)), NetIndex); + SK_PNMI_STORE_U32(pBuf, ReturnCode); + *pLen = *pLen + sizeof(SK_I32); + break; + case SK_SET_SINGLE_VAR: + ReturnCode = SkPnmiSetVar(pAC, IoC, Oid, + (char *)pBuf + sizeof(SK_I32), pLen, + ((SK_U32) (-1)), NetIndex); + SK_PNMI_STORE_U32(pBuf, ReturnCode); + *pLen = *pLen + sizeof(SK_I32); + break; + case SK_GET_FULL_MIB: + ReturnCode = SkPnmiGetStruct(pAC, IoC, pBuf, pLen, NetIndex); + break; + case SK_PRESET_FULL_MIB: + ReturnCode = SkPnmiPreSetStruct(pAC, IoC, pBuf, pLen, NetIndex); + break; + case SK_SET_FULL_MIB: + ReturnCode = SkPnmiSetStruct(pAC, IoC, pBuf, pLen, NetIndex); + break; + default: + break; + } + + return (ReturnCode); + +} /* SkGeIocGen */ + +#ifdef SK_ASF +/***************************************************************************** + * + * Asf + * + * Description: + * The code is simple. No description necessary. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ + +PNMI_STATIC int Asf( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* GET/PRESET/SET action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer used for the management data transfer */ +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ +{ + SK_U32 RetCode = SK_PNMI_ERR_GENERAL; + + /* + * Check instance. We only handle single instance variables. + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* Perform action. */ + /* GET value. */ + if (Action == SK_PNMI_GET) { + switch (Id) { + case OID_SKGE_ASF: + RetCode = SkAsfGet(pAC, IoC, (SK_U8 *) pBuf, pLen); + break; + default: + RetCode = SkAsfGetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen ); + break; + } + + return (RetCode); + } + + /* PRESET value. */ + if (Action == SK_PNMI_PRESET) { + switch (Id) { + case OID_SKGE_ASF: + RetCode = SkAsfPreSet(pAC, IoC, (SK_U8 *) pBuf, pLen); + break; + default: + RetCode = SkAsfPreSetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen ); + break; + } + } + + /* SET value. */ + if (Action == SK_PNMI_SET) { + switch (Id) { + case OID_SKGE_ASF: + RetCode = SkAsfSet(pAC, IoC, (SK_U8 *) pBuf, pLen); + break; + default: + RetCode = SkAsfSetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen ); + break; + } + } + return (RetCode); +} +#endif /* SK_ASF */ + +#endif diff --git a/drivers/sk98lin/skgesirq.c b/drivers/sk98lin/skgesirq.c index e5a4f7e..157cd41 100644 --- a/drivers/sk98lin/skgesirq.c +++ b/drivers/sk98lin/skgesirq.c @@ -1,346 +1,28 @@ /****************************************************************************** * * Name: skgesirq.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.83 $ - * Date: $Date: 2003/02/05 15:10:59 $ + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 2.30 $ + * Date: $Date: 2006/04/27 07:52:20 $ * Purpose: Special IRQ module * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2006 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. + * /LICENSE * ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: skgesirq.c,v $ - * Revision 1.83 2003/02/05 15:10:59 rschmidt - * Fixed setting of PLinkSpeedUsed in SkHWLinkUp() when - * auto-negotiation is disabled. - * Editorial changes. - * - * Revision 1.82 2003/01/29 13:34:33 rschmidt - * Added some typecasts to avoid compiler warnings. - * - * Revision 1.81 2002/12/05 10:49:51 rschmidt - * Fixed missing Link Down Event for fiber (Bug Id #10768) - * Added reading of cable length when link is up - * Removed testing of unused error bits in PHY ISR - * Editorial changes. - * - * Revision 1.80 2002/11/12 17:15:21 rschmidt - * Replaced SkPnmiGetVar() by ...MacStatistic() in SkMacParity(). - * Editorial changes. - * - * Revision 1.79 2002/10/14 15:14:51 rschmidt - * Changed clearing of IS_M1_PAR_ERR (MAC 1 Parity Error) in - * SkMacParity() depending on GIChipRev (HW-Bug #8). - * Added error messages for GPHY Auto-Negotiation Error and - * FIFO Overflow/Underrun in SkPhyIsrGmac(). - * Editorial changes. - * - * Revision 1.78 2002/10/10 15:54:29 mkarl - * changes for PLinkSpeedUsed - * - * Revision 1.77 2002/09/12 08:58:51 rwahl - * Retrieve counters needed for XMAC errata workarounds directly because - * PNMI returns corrected counter values (e.g. #10620). - * - * Revision 1.76 2002/08/16 15:21:54 rschmidt - * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis. - * Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros. - * Editorial changes. - * - * Revision 1.75 2002/08/12 13:50:47 rschmidt - * Changed clearing of IS_M1_PAR_ERR (MAC 1 Parity Error) in - * SkMacParity() by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE (HW-Bug #8). - * Added clearing of IS_IRQ_TIST_OV and IS_IRQ_SENSOR in SkGeHwErr(). - * Corrected handling of Link Up and Auto-Negotiation Over for GPHY. - * in SkGePortCheckUpGmac(). - * Editorial changes. - * - * Revision 1.74 2002/08/08 16:17:04 rschmidt - * Added PhyType check for SK_HWEV_SET_ROLE event (copper only) - * Changed Link Up check reading PHY Specific Status (YUKON) - * Editorial changes - * - * Revision 1.73 2002/07/15 18:36:53 rwahl - * Editorial changes. - * - * Revision 1.72 2002/07/15 15:46:26 rschmidt - * Added new event: SK_HWEV_SET_SPEED - * Editorial changes - * - * Revision 1.71 2002/06/10 09:34:19 rschmidt - * Editorial changes - * - * Revision 1.70 2002/06/05 08:29:18 rschmidt - * SkXmRxTxEnable() replaced by SkMacRxTxEnable(). - * Editorial changes. - * - * Revision 1.69 2002/04/25 13:03:49 rschmidt - * Changes for handling YUKON. - * Use of #ifdef OTHER_PHY to eliminate code for unused Phy types. - * Replaced all XMAC-access macros by functions: SkMacRxTxDisable(), - * SkMacIrqDisable(). - * Added handling for GMAC FIFO in SkMacParity(). - * Replaced all SkXm...() functions with SkMac...() to handle also - * YUKON's GMAC. - * Macros for XMAC PHY access PHY_READ(), PHY_WRITE() replaced - * by functions SkXmPhyRead(), SkXmPhyWrite(). - * Disabling all PHY interrupts moved to SkMacIrqDisable(). - * Added handling for GPHY IRQ in SkGeSirqIsr(). - * Removed status parameter from MAC IRQ handler SkMacIrq(). - * Added SkGePortCheckUpGmac(), SkPhyIsrGmac() for GMAC. - * Editorial changes - * - * Revision 1.68 2002/02/26 15:24:53 rwahl - * Fix: no link with manual configuration (#10673). The previous fix for - * #10639 was removed. So for RLMT mode = CLS the RLMT may switch to - * misconfigured port. It should not occur for the other RLMT modes. - * - * Revision 1.67 2001/11/20 09:19:58 rwahl - * Reworked bugfix #10639 (no dependency to RLMT mode). - * - * Revision 1.66 2001/10/26 07:52:53 afischer - * Port switching bug in `check local link` mode - * - * Revision 1.65 2001/02/23 13:41:51 gklug - * fix: PHYS2INST should be used correctly for Dual Net operation - * chg: do no longer work with older PNMI - * - * Revision 1.64 2001/02/15 11:27:04 rassmann - * Working with RLMT v1 if SK_MAX_NETS undefined. - * - * Revision 1.63 2001/02/06 10:44:23 mkunz - * - NetIndex added to interface functions of pnmi V4 with dual net support - * - * Revision 1.62 2001/01/31 15:31:41 gklug - * fix: problem with autosensing an SR8800 switch - * - * Revision 1.61 2000/11/09 11:30:09 rassmann - * WA: Waiting after releasing reset until BCom chip is accessible. - * - * Revision 1.60 2000/10/18 12:37:48 cgoos - * Reinserted the comment for version 1.56. - * - * Revision 1.59 2000/10/18 12:22:20 cgoos - * Added workaround for half duplex hangup. - * - * Revision 1.58 2000/09/28 13:06:04 gklug - * fix: BCom may NOT be touched if XMAC is in RESET state - * - * Revision 1.57 2000/09/08 12:38:39 cgoos - * Added forgotten variable declaration. - * - * Revision 1.56 2000/09/08 08:12:13 cgoos - * Changed handling of parity errors in SkGeHwErr (correct reset of error). - * - * Revision 1.55 2000/06/19 08:36:25 cgoos - * Changed comment. - * - * Revision 1.54 2000/05/22 08:45:57 malthoff - * Fix: #10523 is valid for all BCom PHYs. - * - * Revision 1.53 2000/05/19 10:20:30 cgoos - * Removed Solaris debug output code. - * - * Revision 1.52 2000/05/19 10:19:37 cgoos - * Added PHY state check in HWLinkDown. - * Move PHY interrupt code to IS_EXT_REG case in SkGeSirqIsr. - * - * Revision 1.51 2000/05/18 05:56:20 cgoos - * Fixed typo. - * - * Revision 1.50 2000/05/17 12:49:49 malthoff - * Fixes BCom link bugs (#10523). - * - * Revision 1.49 1999/12/17 11:02:50 gklug - * fix: read PHY_STAT of Broadcom chip more often to assure good status - * - * Revision 1.48 1999/12/06 10:01:17 cgoos - * Added SET function for Role. - * - * Revision 1.47 1999/11/22 13:34:24 cgoos - * Changed license header to GPL. - * - * Revision 1.46 1999/09/16 10:30:07 cgoos - * Removed debugging output statement from Linux. - * - * Revision 1.45 1999/09/16 07:32:55 cgoos - * Fixed dual-port copperfield bug (PHY_READ from resetted port). - * Removed some unused variables. - * - * Revision 1.44 1999/08/03 15:25:04 cgoos - * Removed workaround for disabled interrupts in half duplex mode. - * - * Revision 1.43 1999/08/03 14:27:58 cgoos - * Removed SENSE mode code from SkGePortCheckUpBcom. - * - * Revision 1.42 1999/07/26 09:16:54 cgoos - * Added some typecasts to avoid compiler warnings. - * - * Revision 1.41 1999/05/19 07:28:59 cgoos - * Changes for 1000Base-T. - * - * Revision 1.40 1999/04/08 13:59:39 gklug - * fix: problem with 3Com switches endless RESTARTs - * - * Revision 1.39 1999/03/08 10:10:52 gklug - * fix: AutoSensing did switch to next mode even if LiPa indicated offline - * - * Revision 1.38 1999/03/08 09:49:03 gklug - * fix: Bug using pAC instead of IoC, causing AIX problems - * fix: change compare for Linux compiler bug workaround - * - * Revision 1.37 1999/01/28 14:51:33 gklug - * fix: monitor for autosensing and extra RESETS the RX on wire counters - * - * Revision 1.36 1999/01/22 09:19:55 gklug - * fix: Init DupMode and InitPauseMd are now called in RxTxEnable - * - * Revision 1.35 1998/12/11 15:22:59 gklug - * chg: autosensing: check for receive if manual mode was guessed - * chg: simplified workaround for XMAC errata - * chg: wait additional 100 ms before link goes up. - * chg: autoneg timeout to 600 ms - * chg: restart autoneg even if configured to autonegotiation - * - * Revision 1.34 1998/12/10 10:33:14 gklug - * add: more debug messages - * fix: do a new InitPhy if link went down (AutoSensing problem) - * chg: Check for zero shorts if link is NOT up - * chg: reset Port if link goes down - * chg: wait additional 100 ms when link comes up to check shorts - * fix: dummy read extended autoneg status to prevent link going down immediately - * - * Revision 1.33 1998/12/07 12:18:29 gklug - * add: refinement of autosense mode: take into account the autoneg cap of LiPa - * - * Revision 1.32 1998/12/07 07:11:21 gklug - * fix: compiler warning - * - * Revision 1.31 1998/12/02 09:29:05 gklug - * fix: WA XMAC Errata: FCSCt check was not correct. - * fix: WA XMAC Errata: Prec Counter were NOT updated in case of short checks. - * fix: Clear Stat : now clears the Prev counters of all known Ports - * - * Revision 1.30 1998/12/01 10:54:15 gklug - * dd: workaround for XMAC errata changed. Check RX count and CRC err Count, too. - * - * Revision 1.29 1998/12/01 10:01:53 gklug - * fix: if MAC IRQ occurs during port down, this will be handled correctly - * - * Revision 1.28 1998/11/26 16:22:11 gklug - * fix: bug in autosense if manual modes are used - * - * Revision 1.27 1998/11/26 15:50:06 gklug - * fix: PNMI needs to set PLinkModeConf - * - * Revision 1.26 1998/11/26 14:51:58 gklug - * add: AutoSensing functionalty - * - * Revision 1.25 1998/11/26 07:34:37 gklug - * fix: Init PrevShorts when restarting port due to Link connection - * - * Revision 1.24 1998/11/25 10:57:32 gklug - * fix: remove unreferenced local vars - * - * Revision 1.23 1998/11/25 08:26:40 gklug - * fix: don't do a RESET on a starting or stopping port - * - * Revision 1.22 1998/11/24 13:29:44 gklug - * add: Workaround for MAC parity errata - * - * Revision 1.21 1998/11/18 15:31:06 gklug - * fix: lint bugs - * - * Revision 1.20 1998/11/18 12:58:54 gklug - * fix: use PNMI query instead of hardware access - * - * Revision 1.19 1998/11/18 12:54:55 gklug - * chg: add new workaround for XMAC Errata - * add: short event counter monitoring on active link too - * - * Revision 1.18 1998/11/13 14:27:41 malthoff - * Bug Fix: Packet Arbiter Timeout was not cleared correctly - * for timeout on TX1 and TX2. - * - * Revision 1.17 1998/11/04 07:01:59 cgoos - * Moved HW link poll sequence. - * Added call to SkXmRxTxEnable. - * - * Revision 1.16 1998/11/03 13:46:03 gklug - * add: functionality of SET_LMODE and SET_FLOW_MODE - * fix: send RLMT LinkDown event when Port stop is given with LinkUp - * - * Revision 1.15 1998/11/03 12:56:47 gklug - * fix: Needs more events - * - * Revision 1.14 1998/10/30 07:36:35 gklug - * rmv: unnecessary code - * - * Revision 1.13 1998/10/29 15:21:57 gklug - * add: Poll link feature for activating HW link - * fix: Deactivate HWLink when Port STOP is given - * - * Revision 1.12 1998/10/28 07:38:57 cgoos - * Checking link status at begin of SkHWLinkUp. - * - * Revision 1.11 1998/10/22 09:46:50 gklug - * fix SysKonnectFileId typo - * - * Revision 1.10 1998/10/14 13:57:47 gklug - * add: Port start/stop event - * - * Revision 1.9 1998/10/14 05:48:29 cgoos - * Added definition for Para. - * - * Revision 1.8 1998/10/14 05:40:09 gklug - * add: Hardware Linkup signal used - * - * Revision 1.7 1998/10/09 06:50:20 malthoff - * Remove ID_sccs by SysKonnectFileId. - * - * Revision 1.6 1998/10/08 09:11:49 gklug - * add: clear IRQ commands - * - * Revision 1.5 1998/10/02 14:27:35 cgoos - * Fixed some typos and wrong event names. - * - * Revision 1.4 1998/10/02 06:24:17 gklug - * add: HW error function - * fix: OUT macros - * - * Revision 1.3 1998/10/01 07:03:00 gklug - * add: ISR for the usual interrupt source register - * - * Revision 1.2 1998/09/03 13:50:33 gklug - * add: function prototypes - * - * Revision 1.1 1998/08/27 11:50:21 gklug - * initial revision - * - * - * - ******************************************************************************/ - -#include - -#ifdef CONFIG_SK98 - /* * Special Interrupt handler * @@ -357,34 +39,48 @@ * right after this ISR. * * The Interrupt source register of the adapter is NOT read by this module. - * SO if the drivers implementor needs a while loop around the + * SO if the drivers implementor needs a while loop around the * slow data paths interrupt bits, he needs to call the SkGeSirqIsr() for * each loop entered. * * However, the MAC Interrupt status registers are read in a while loop. * */ - -static const char SysKonnectFileId[] = - "$Id: skgesirq.c,v 1.83 2003/02/05 15:10:59 rschmidt Exp $" ; +#include + +#ifdef CONFIG_SK98 #include "h/skdrv1st.h" /* Driver Specific Definitions */ +#ifndef SK_SLIM #include "h/skgepnmi.h" /* PNMI Definitions */ #include "h/skrlmt.h" /* RLMT Definitions */ +#endif #include "h/skdrv2nd.h" /* Adapter Control and Driver specific Def. */ +/* local variables ************************************************************/ + +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) +static const char SysKonnectFileId[] = + "@(#) $Id: skgesirq.c,v 2.30 2006/04/27 07:52:20 malthoff Exp $ (C) Marvell."; +#endif + /* local function prototypes */ -static int SkGePortCheckUpXmac(SK_AC*, SK_IOC, int); -static int SkGePortCheckUpBcom(SK_AC*, SK_IOC, int); -static int SkGePortCheckUpGmac(SK_AC*, SK_IOC, int); +#ifdef GENESIS +static int SkGePortCheckUpXmac(SK_AC*, SK_IOC, int, SK_BOOL); +static int SkGePortCheckUpBcom(SK_AC*, SK_IOC, int, SK_BOOL); static void SkPhyIsrBcom(SK_AC*, SK_IOC, int, SK_U16); +#endif /* GENESIS */ +#ifdef YUKON +static int SkGePortCheckUpGmac(SK_AC*, SK_IOC, int, SK_BOOL); static void SkPhyIsrGmac(SK_AC*, SK_IOC, int, SK_U16); +#endif /* YUKON */ #ifdef OTHER_PHY -static int SkGePortCheckUpLone(SK_AC*, SK_IOC, int); -static int SkGePortCheckUpNat(SK_AC*, SK_IOC, int); +static int SkGePortCheckUpLone(SK_AC*, SK_IOC, int, SK_BOOL); +static int SkGePortCheckUpNat(SK_AC*, SK_IOC, int, SK_BOOL); static void SkPhyIsrLone(SK_AC*, SK_IOC, int, SK_U16); #endif /* OTHER_PHY */ +#ifdef GENESIS /* * array of Rx counter from XMAC which are checked * in AutoSense mode to check whether a link is not able to auto-negotiate. @@ -396,7 +92,8 @@ static const SK_U16 SkGeRxRegs[]= { XM_RXF_511B, XM_RXF_1023B, XM_RXF_MAX_SZ -} ; +}; +#endif /* GENESIS */ #ifdef __C2MAN__ /* @@ -409,11 +106,6 @@ intro() {} #endif -/* Define return codes of SkGePortCheckUp and CheckShort */ -#define SK_HW_PS_NONE 0 /* No action needed */ -#define SK_HW_PS_RESTART 1 /* Restart needed */ -#define SK_HW_PS_LINK 2 /* Link Up actions needed */ - /****************************************************************************** * * SkHWInitDefSense() - Default Autosensing mode initialization @@ -423,8 +115,8 @@ intro() * Returns: N/A */ static void SkHWInitDefSense( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; /* GIni Port struct pointer */ @@ -433,7 +125,7 @@ int Port) /* Port Index (MAC_1 + n) */ pPrt->PAutoNegTimeOut = 0; - if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) { + if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) { pPrt->PLinkMode = pPrt->PLinkModeConf; return; } @@ -442,12 +134,13 @@ int Port) /* Port Index (MAC_1 + n) */ ("AutoSensing: First mode %d on Port %d\n", (int)SK_LMODE_AUTOFULL, Port)); - pPrt->PLinkMode = SK_LMODE_AUTOFULL; + pPrt->PLinkMode = (SK_U8)SK_LMODE_AUTOFULL; return; } /* SkHWInitDefSense */ +#ifdef GENESIS /****************************************************************************** * * SkHWSenseGetNext() - Get Next Autosensing Mode @@ -457,9 +150,9 @@ int Port) /* Port Index (MAC_1 + n) */ * Note: * */ -SK_U8 SkHWSenseGetNext( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +static SK_U8 SkHWSenseGetNext( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; /* GIni Port struct pointer */ @@ -468,18 +161,18 @@ int Port) /* Port Index (MAC_1 + n) */ pPrt->PAutoNegTimeOut = 0; - if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) { + if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) { /* Leave all as configured */ return(pPrt->PLinkModeConf); } - if (pPrt->PLinkMode == SK_LMODE_AUTOFULL) { + if (pPrt->PLinkMode == (SK_U8)SK_LMODE_AUTOFULL) { /* Return next mode AUTOBOTH */ - return(SK_LMODE_AUTOBOTH); + return((SK_U8)SK_LMODE_AUTOBOTH); } /* Return default autofull */ - return(SK_LMODE_AUTOFULL); + return((SK_U8)SK_LMODE_AUTOFULL); } /* SkHWSenseGetNext */ @@ -491,9 +184,9 @@ int Port) /* Port Index (MAC_1 + n) */ * * Returns: N/A */ -void SkHWSenseSetNext( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +static void SkHWSenseSetNext( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O context */ int Port, /* Port Index (MAC_1 + n) */ SK_U8 NewMode) /* New Mode to be written in sense mode */ { @@ -503,7 +196,7 @@ SK_U8 NewMode) /* New Mode to be written in sense mode */ pPrt->PAutoNegTimeOut = 0; - if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) { + if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) { return; } @@ -515,6 +208,7 @@ SK_U8 NewMode) /* New Mode to be written in sense mode */ return; } /* SkHWSenseSetNext */ +#endif /* GENESIS */ /****************************************************************************** @@ -526,8 +220,8 @@ SK_U8 NewMode) /* New Mode to be written in sense mode */ * Returns: N/A */ void SkHWLinkDown( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; /* GIni Port struct pointer */ @@ -547,18 +241,20 @@ int Port) /* Port Index (MAC_1 + n) */ return; } - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, ("Link down Port %d\n", Port)); /* Set Link to DOWN */ pPrt->PHWLinkUp = SK_FALSE; +#ifndef SK_SLIM /* Reset Port stati */ - pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; - pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; - pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_INDETERMINATED; + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN; + pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE; + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_INDETERMINATED; +#endif /* !SK_SLIM */ - /* Re-init Phy especially when the AutoSense default is set now */ + /* Re-init PHY especially when the AutoSense default is set now */ SkMacInitPhy(pAC, IoC, Port, SK_FALSE); /* GP0: used for workaround of Rev. C Errata 2 */ @@ -578,8 +274,8 @@ int Port) /* Port Index (MAC_1 + n) */ * Returns: N/A */ void SkHWLinkUp( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; /* GIni Port struct pointer */ @@ -592,12 +288,14 @@ int Port) /* Port Index (MAC_1 + n) */ } pPrt->PHWLinkUp = SK_TRUE; - pPrt->PAutoNegFail = SK_FALSE; - pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; - if (pPrt->PLinkMode != SK_LMODE_AUTOHALF && - pPrt->PLinkMode != SK_LMODE_AUTOFULL && - pPrt->PLinkMode != SK_LMODE_AUTOBOTH) { +#ifndef SK_SLIM + pPrt->PAutoNegFail = SK_FALSE; + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN; + + if (pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOHALF && + pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOFULL && + pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOBOTH) { /* Link is up and no Auto-negotiation should be done */ /* Link speed should be the configured one */ @@ -605,30 +303,32 @@ int Port) /* Port Index (MAC_1 + n) */ case SK_LSPEED_AUTO: /* default is 1000 Mbps */ case SK_LSPEED_1000MBPS: - pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; + pPrt->PLinkSpeedUsed = (SK_U8) + ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ? + SK_LSPEED_STAT_1000MBPS : SK_LSPEED_STAT_100MBPS; break; case SK_LSPEED_100MBPS: - pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_100MBPS; + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS; break; case SK_LSPEED_10MBPS: - pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_10MBPS; + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS; break; } /* Set Link Mode Status */ - if (pPrt->PLinkMode == SK_LMODE_FULL) { - pPrt->PLinkModeStatus = SK_LMODE_STAT_FULL; - } - else { - pPrt->PLinkModeStatus = SK_LMODE_STAT_HALF; - } + pPrt->PLinkModeStatus = (SK_U8) + ((pPrt->PLinkMode == (SK_U8)SK_LMODE_FULL) ? + SK_LMODE_STAT_FULL : SK_LMODE_STAT_HALF); /* No flow control without auto-negotiation */ - pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE; +#endif /* !SK_SLIM */ /* enable Rx/Tx */ - SkMacRxTxEnable(pAC, IoC, Port); + (void)SkMacRxTxEnable(pAC, IoC, Port); +#ifndef SK_SLIM } +#endif /* !SK_SLIM */ } /* SkHWLinkUp */ @@ -641,27 +341,37 @@ int Port) /* Port Index (MAC_1 + n) */ * Returns: N/A */ static void SkMacParity( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -int Port) /* Port Index of the port failed */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O context */ +int Port) /* Port Index (MAC_1 + n) */ { SK_EVPARA Para; SK_GEPORT *pPrt; /* GIni Port struct pointer */ - SK_U32 TxMax; /* TxMax Counter */ + SK_U32 TxMax; /* Tx Max Size Counter */ + + TxMax = 0; pPrt = &pAC->GIni.GP[Port]; /* Clear IRQ Tx Parity Error */ +#ifdef GENESIS if (pAC->GIni.GIGenesis) { + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_PERR); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), - (SK_U8)((pAC->GIni.GIChipRev == 0) ? GMF_CLI_TX_FC : GMF_CLI_TX_PE)); + (SK_U8)((pAC->GIni.GIChipId == CHIP_ID_YUKON && + pAC->GIni.GIChipRev == 0) ? GMF_CLI_TX_FC : GMF_CLI_TX_PE)); } +#endif /* YUKON */ if (pPrt->PCheckPar) { + if (Port == MAC_1) { SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E016, SKERR_SIRQ_E016MSG); } @@ -670,6 +380,7 @@ int Port) /* Port Index of the port failed */ } Para.Para64 = Port; SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = Port; SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); @@ -677,15 +388,21 @@ int Port) /* Port Index of the port failed */ } /* Check whether frames with a size of 1k were sent */ +#ifdef GENESIS if (pAC->GIni.GIGenesis) { /* Snap statistic counters */ (void)SkXmUpdateStats(pAC, IoC, Port); (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXF_MAX_SZ, &TxMax); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { + (void)SkGmMacStatistic(pAC, IoC, Port, GM_TXF_1518B, &TxMax); } +#endif /* YUKON */ if (TxMax > 0) { /* From now on check the parity */ @@ -696,15 +413,15 @@ int Port) /* Port Index of the port failed */ /****************************************************************************** * - * SkGeHwErr() - Hardware Error service routine + * SkGeYuHwErr() - Hardware Error service routine (Genesis and Yukon) * * Description: handles all HW Error interrupts * * Returns: N/A */ -static void SkGeHwErr( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +static void SkGeYuHwErr( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O context */ SK_U32 HwStatus) /* Interrupt status word */ { SK_EVPARA Para; @@ -720,17 +437,19 @@ SK_U32 HwStatus) /* Interrupt status word */ } /* Reset all bits in the PCI STATUS register */ - SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); + SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word); SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); - SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS); + SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS)); SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); Para.Para64 = 0; SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); } +#ifdef GENESIS if (pAC->GIni.GIGenesis) { + if ((HwStatus & IS_NO_STAT_M1) != 0) { /* Ignore it */ /* This situation is also indicated in the descriptor */ @@ -755,28 +474,42 @@ SK_U32 HwStatus) /* Interrupt status word */ SK_OUT16(IoC, MR_ADDR(MAC_2, RX_MFF_CTRL1), MFF_CLR_INTIST); } } - else { /* YUKON */ +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { /* This is necessary only for Rx timing measurements */ if ((HwStatus & IS_IRQ_TIST_OV) != 0) { + /* increment Time Stamp Timer counter (high) */ + pAC->GIni.GITimeStampCnt++; + /* Clear Time Stamp Timer IRQ */ SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_CLR_IRQ); } if ((HwStatus & IS_IRQ_SENSOR) != 0) { - /* Clear I2C IRQ */ - SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); + /* no sensors on 32-bit Yukon */ + if (pAC->GIni.GIYukon32Bit) { + /* disable HW Error IRQ */ + pAC->GIni.GIValIrqMask &= ~IS_HW_ERR; + } } } +#endif /* YUKON */ if ((HwStatus & IS_RAM_RD_PAR) != 0) { + SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_RD_PERR); + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E014, SKERR_SIRQ_E014MSG); Para.Para64 = 0; SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); } if ((HwStatus & IS_RAM_WR_PAR) != 0) { + SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_WR_PERR); + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E015, SKERR_SIRQ_E015MSG); Para.Para64 = 0; SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); @@ -797,6 +530,7 @@ SK_U32 HwStatus) /* Interrupt status word */ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG); Para.Para64 = MAC_1; SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_1; SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); } @@ -808,39 +542,297 @@ SK_U32 HwStatus) /* Interrupt status word */ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG); Para.Para64 = MAC_2; SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_2; SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); } -} /* SkGeHwErr */ +} /* SkGeYuHwErr */ +#ifdef YUK2 +/****************************************************************************** + * + * SkYuk2HwPortErr() - Service HW Errors for specified port (Yukon-2 only) + * + * Description: handles the HW Error interrupts for a specific port. + * + * Returns: N/A + */ +static void SkYuk2HwPortErr( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 HwStatus, /* Interrupt status word */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_EVPARA Para; + int Queue; + + if (Port == MAC_2) { + HwStatus >>= 8; + } + + if ((HwStatus & Y2_HWE_L1_MASK) == 0) { + return; + } + + if ((HwStatus & Y2_IS_PAR_RD1) != 0) { + /* Clear IRQ */ + SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_RD_PERR); + + if (Port == MAC_1) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E028, SKERR_SIRQ_E028MSG); + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E030, SKERR_SIRQ_E030MSG); + } + } + + if ((HwStatus & Y2_IS_PAR_WR1) != 0) { + /* Clear IRQ */ + SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_WR_PERR); + + if (Port == MAC_1) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E029, SKERR_SIRQ_E029MSG); + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E031, SKERR_SIRQ_E031MSG); + } + } + + if ((HwStatus & Y2_IS_PAR_MAC1) != 0) { + /* Clear IRQ */ + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); + + if (Port == MAC_1) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E016, SKERR_SIRQ_E016MSG); + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E017, SKERR_SIRQ_E017MSG); + } + } + + if ((HwStatus & Y2_IS_PAR_RX1) != 0) { + if (Port == MAC_1) { + Queue = Q_R1; + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG); + } + else { + Queue = Q_R2; + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG); + } + /* Clear IRQ */ + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_PAR); + } + + if ((HwStatus & Y2_IS_TCP_TXS1) != 0) { + if (Port == MAC_1) { + Queue = Q_XS1; + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E033, SKERR_SIRQ_E033MSG); + } + else { + Queue = Q_XS2; + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E035, SKERR_SIRQ_E035MSG); + } + /* Clear IRQ */ + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP); + } + + if ((HwStatus & Y2_IS_TCP_TXA1) != 0) { + if (Port == MAC_1) { + Queue = Q_XA1; + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E032, SKERR_SIRQ_E032MSG); + } + else { + Queue = Q_XA2; + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E034, SKERR_SIRQ_E034MSG); + } + /* Clear IRQ */ + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP); + } + + Para.Para64 = Port; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + + Para.Para32[0] = Port; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + +} /* SkYuk2HwPortErr */ /****************************************************************************** * - * SkGeSirqIsr() - Special Interrupt Service Routine + * SkYuk2HwErr() - Hardware Error service routine (Yukon-2 only) + * + * Description: handles all HW Error interrupts + * + * Returns: N/A + */ +static void SkYuk2HwErr( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 HwStatus) /* Interrupt status word */ +{ + SK_EVPARA Para; + SK_U16 Word; + SK_U32 DWord; + SK_U32 TlpHead[4]; + int i; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("HW-Error Status: 0x%08lX\n", HwStatus)); + + /* This is necessary only for Rx timing measurements */ + if ((HwStatus & Y2_IS_TIST_OV) != 0) { + /* increment Time Stamp Timer counter (high) */ + pAC->GIni.GITimeStampCnt++; + + /* Clear Time Stamp Timer IRQ */ + SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_CLR_IRQ); + } + + /* Evaluate Y2_IS_PCI_NEXP before Y2_IS_MST_ERR or Y2_IS_IRQ_STAT */ + if ((HwStatus & Y2_IS_PCI_NEXP) != 0) { + /* + * This error is also mapped either to Master Abort (Y2_IS_MST_ERR) + * or Target Abort (Y2_IS_IRQ_STAT) bit and can only be cleared there. + * Therefore handle this event just by printing an error log entry. + */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E027, SKERR_SIRQ_E027MSG); + } + + if ((HwStatus & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { + /* PCI Errors occured */ + if ((HwStatus & Y2_IS_IRQ_STAT) != 0) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E013, SKERR_SIRQ_E013MSG); + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E012, SKERR_SIRQ_E012MSG); + } + + /* Reset all bits in the PCI STATUS register */ + SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word); + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS)); + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); + } + + /* check for PCI-Express Uncorrectable Error */ + if ((HwStatus & Y2_IS_PCI_EXP) != 0) { + /* + * On PCI-Express bus bridges are called root complexes (RC). + * PCI-Express errors are recognized by the root complex too, + * which requests the system to handle the problem. After error + * occurence it may be that no access to the adapter may be performed + * any longer. + */ + + /* Get uncorrectable error status */ + SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("PEX Uncorr.Error Status: 0x%08lX\n", DWord)); + + if (DWord != PEX_UNSUP_REQ) { + /* ignore Unsupported Request Errors */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E026, SKERR_SIRQ_E026MSG); + } + + if ((DWord & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { + /* + * Stop only, if the uncorrectable error is fatal or + * Poisoned TLP occured + */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("Header Log:")); + + for (i = 0; i < 4; i++) { + /* get TLP Header from Log Registers */ + SK_IN32(IoC, PCI_C(pAC, PEX_HEADER_LOG + i*4), &TlpHead[i]); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + (" 0x%08lX", TlpHead[i])); + } + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("\n")); + + /* check for vendor defined broadcast message */ + if (TlpHead[0] == 0x73004001 && (SK_U8)TlpHead[1] == 0x7f) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Vendor defined broadcast message\n")); + } + else { + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); + + pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP; + /* Rewrite HW IRQ mask */ + SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask); + } + } + + /* clear any PEX errors */ + SK_OUT32(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + SK_OUT32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), 0xffffffffUL); + SK_OUT32(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + + SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord); + + if ((DWord & PEX_RX_OV) != 0) { + /* Dev #4.205 occured */ + pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP; + pAC->GIni.GIValIrqMask &= ~Y2_IS_HW_ERR; + } + } + + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + + SkYuk2HwPortErr(pAC, IoC, HwStatus, i); + } + +} /* SkYuk2HwErr */ +#endif /* YUK2 */ + +/****************************************************************************** + * + * SkGeSirqIsr() - Wrapper for Special Interrupt Service Routine + * + * Description: calls the preselected special ISR (slow path) + * + * Returns: N/A + */ +void SkGeSirqIsr( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O context */ +SK_U32 Istatus) /* Interrupt status word */ +{ + pAC->GIni.GIFunc.pSkGeSirqIsr(pAC, IoC, Istatus); +} + +/****************************************************************************** + * + * SkGeYuSirqIsr() - Special Interrupt Service Routine * * Description: handles all non data transfer specific interrupts (slow path) * * Returns: N/A */ -void SkGeSirqIsr( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +void SkGeYuSirqIsr( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ SK_U32 Istatus) /* Interrupt status word */ { SK_EVPARA Para; SK_U32 RegVal32; /* Read register value */ SK_GEPORT *pPrt; /* GIni Port struct pointer */ - unsigned Len; - SK_U64 Octets; - SK_U16 PhyInt; - SK_U16 PhyIMsk; + SK_U16 PhyInt; int i; - if ((Istatus & IS_HW_ERR) != 0) { + if (((Istatus & IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) { /* read the HW Error Interrupt source */ SK_IN32(IoC, B0_HWE_ISRC, &RegVal32); - SkGeHwErr(pAC, IoC, RegVal32); + SkGeYuHwErr(pAC, IoC, RegVal32); } /* @@ -855,7 +847,7 @@ SK_U32 Istatus) /* Interrupt status word */ } if (((Istatus & (IS_PA_TO_RX2 | IS_PA_TO_TX2)) != 0) && - pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) { + pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) { /* MAC 2 was not initialized but Packet timeout occured */ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E005, SKERR_SIRQ_E005MSG); @@ -877,69 +869,86 @@ SK_U32 Istatus) /* Interrupt status word */ if ((Istatus & IS_PA_TO_TX1) != 0) { - pPrt = &pAC->GIni.GP[0]; + pPrt = &pAC->GIni.GP[MAC_1]; /* May be a normal situation in a server with a slow network */ SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX1); - /* - * workaround: if in half duplex mode, check for Tx hangup. - * Read number of TX'ed bytes, wait for 10 ms, then compare - * the number with current value. If nothing changed, we assume - * that Tx is hanging and do a FIFO flush (see event routine). - */ - if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || - pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) && - !pPrt->HalfDupTimerActive) { +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { /* - * many more pack. arb. timeouts may come in between, - * we ignore those + * workaround: if in half duplex mode, check for Tx hangup. + * Read number of TX'ed bytes, wait for 10 ms, then compare + * the number with current value. If nothing changed, we assume + * that Tx is hanging and do a FIFO flush (see event routine). */ - pPrt->HalfDupTimerActive = SK_TRUE; + if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) && + !pPrt->HalfDupTimerActive) { + /* + * many more pack. arb. timeouts may come in between, + * we ignore those + */ + pPrt->HalfDupTimerActive = SK_TRUE; - Len = sizeof(SK_U64); - SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets, - &Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(pAC, 0), - pAC->Rlmt.Port[0].Net->NetNumber); + /* Snap statistic counters */ + (void)SkXmUpdateStats(pAC, IoC, 0); - pPrt->LastOctets = Octets; + (void)SkXmMacStatistic(pAC, IoC, 0, XM_TXO_OK_HI, &RegVal32); - Para.Para32[0] = 0; - SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME, - SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para); + pPrt->LastOctets = (SK_U64)RegVal32 << 32; + + (void)SkXmMacStatistic(pAC, IoC, 0, XM_TXO_OK_LO, &RegVal32); + + pPrt->LastOctets += RegVal32; + + Para.Para32[0] = 0; + SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME, + SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para); + } } +#endif /* GENESIS */ } if ((Istatus & IS_PA_TO_TX2) != 0) { - pPrt = &pAC->GIni.GP[1]; + pPrt = &pAC->GIni.GP[MAC_2]; /* May be a normal situation in a server with a slow network */ SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX2); - /* workaround: see above */ - if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || - pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) && - !pPrt->HalfDupTimerActive) { - pPrt->HalfDupTimerActive = SK_TRUE; +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { + /* workaround: see above */ + if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) && + !pPrt->HalfDupTimerActive) { + pPrt->HalfDupTimerActive = SK_TRUE; - Len = sizeof(SK_U64); - SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets, - &Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(pAC, 1), - pAC->Rlmt.Port[1].Net->NetNumber); + /* Snap statistic counters */ + (void)SkXmUpdateStats(pAC, IoC, 1); - pPrt->LastOctets = Octets; + (void)SkXmMacStatistic(pAC, IoC, 1, XM_TXO_OK_HI, &RegVal32); - Para.Para32[0] = 1; - SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME, - SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para); + pPrt->LastOctets = (SK_U64)RegVal32 << 32; + + (void)SkXmMacStatistic(pAC, IoC, 1, XM_TXO_OK_LO, &RegVal32); + + pPrt->LastOctets += RegVal32; + + Para.Para32[0] = 1; + SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME, + SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para); + } } +#endif /* GENESIS */ } /* Check interrupts of the particular queues */ if ((Istatus & IS_R1_C) != 0) { /* Clear IRQ */ SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E006, SKERR_SIRQ_E006MSG); Para.Para64 = MAC_1; @@ -951,6 +960,7 @@ SK_U32 Istatus) /* Interrupt status word */ if ((Istatus & IS_R2_C) != 0) { /* Clear IRQ */ SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E007, SKERR_SIRQ_E007MSG); Para.Para64 = MAC_2; @@ -962,6 +972,7 @@ SK_U32 Istatus) /* Interrupt status word */ if ((Istatus & IS_XS1_C) != 0) { /* Clear IRQ */ SK_OUT32(IoC, B0_XS1_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E008, SKERR_SIRQ_E008MSG); Para.Para64 = MAC_1; @@ -973,8 +984,10 @@ SK_U32 Istatus) /* Interrupt status word */ if ((Istatus & IS_XA1_C) != 0) { /* Clear IRQ */ SK_OUT32(IoC, B0_XA1_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E009, SKERR_SIRQ_E009MSG); + Para.Para64 = MAC_1; SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); Para.Para32[0] = MAC_1; @@ -984,6 +997,7 @@ SK_U32 Istatus) /* Interrupt status word */ if ((Istatus & IS_XS2_C) != 0) { /* Clear IRQ */ SK_OUT32(IoC, B0_XS2_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E010, SKERR_SIRQ_E010MSG); Para.Para64 = MAC_2; @@ -995,6 +1009,7 @@ SK_U32 Istatus) /* Interrupt status word */ if ((Istatus & IS_XA2_C) != 0) { /* Clear IRQ */ SK_OUT32(IoC, B0_XA2_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E011, SKERR_SIRQ_E011MSG); Para.Para64 = MAC_2; @@ -1014,59 +1029,66 @@ SK_U32 Istatus) /* Interrupt status word */ continue; } - switch (pPrt->PhyType) { +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { - case SK_PHY_XMAC: - break; + switch (pPrt->PhyType) { - case SK_PHY_BCOM: - SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_STAT, &PhyInt); - SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_MASK, &PhyIMsk); + case SK_PHY_XMAC: + break; - if ((PhyInt & ~PhyIMsk) != 0) { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, - ("Port %d Bcom Int: 0x%04X Mask: 0x%04X\n", - i, PhyInt, PhyIMsk)); - SkPhyIsrBcom(pAC, IoC, i, PhyInt); + case SK_PHY_BCOM: + SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_STAT, &PhyInt); + + if ((PhyInt & ~PHY_B_DEF_MSK) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Port %d PHY Int: 0x%04X\n", i, PhyInt)); + SkPhyIsrBcom(pAC, IoC, i, PhyInt); + } + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_STAT, &PhyInt); + + if ((PhyInt & PHY_L_DEF_MSK) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Port %d PHY Int: 0x%04X\n", i, PhyInt)); + SkPhyIsrLone(pAC, IoC, i, PhyInt); + } + break; +#endif /* OTHER_PHY */ } - break; + } +#endif /* GENESIS */ - case SK_PHY_MARV_COPPER: - case SK_PHY_MARV_FIBER: +#ifdef YUKON + if (pAC->GIni.GIYukon) { + /* Read PHY Interrupt Status */ SkGmPhyRead(pAC, IoC, i, PHY_MARV_INT_STAT, &PhyInt); - SkGmPhyRead(pAC, IoC, i, PHY_MARV_INT_MASK, &PhyIMsk); - if ((PhyInt & PhyIMsk) != 0) { + if ((PhyInt & PHY_M_DEF_MSK) != 0) { SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, - ("Port %d Marv Int: 0x%04X Mask: 0x%04X\n", - i, PhyInt, PhyIMsk)); + ("Port %d PHY Int: 0x%04X\n", i, PhyInt)); SkPhyIsrGmac(pAC, IoC, i, PhyInt); } - break; - -#ifdef OTHER_PHY - case SK_PHY_LONE: - SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_STAT, &PhyInt); - SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_ENAB, &PhyIMsk); - - if ((PhyInt & PhyIMsk) != 0) { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, - ("Port %d Lone Int: %x Mask: %x\n", - i, PhyInt, PhyIMsk)); - SkPhyIsrLone(pAC, IoC, i, PhyInt); - } - break; - case SK_PHY_NAT: - /* todo: National */ - break; -#endif /* OTHER_PHY */ } +#endif /* YUKON */ } } - /* I2C Ready interrupt */ + /* TWSI Ready interrupt */ if ((Istatus & IS_I2C_READY) != 0) { +#ifdef SK_SLIM + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); +#else SkI2cIsr(pAC, IoC); +#endif + } + + /* SW forced interrupt */ + if ((Istatus & IS_IRQ_SW) != 0) { + /* clear the software IRQ */ + SK_OUT8(IoC, B0_CTST, CS_CL_SW_IRQ); } if ((Istatus & IS_LNK_SYNC_M1) != 0) { @@ -1075,7 +1097,7 @@ SK_U32 Istatus) /* Interrupt status word */ * us only a link going down. */ /* clear interrupt */ - SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LED_CLR_IRQ); + SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LNK_CLR_IRQ); } /* Check MAC after link sync counter */ @@ -1090,7 +1112,7 @@ SK_U32 Istatus) /* Interrupt status word */ * us only a link going down. */ /* clear interrupt */ - SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LED_CLR_IRQ); + SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LNK_CLR_IRQ); } /* Check MAC after link sync counter */ @@ -1101,11 +1123,211 @@ SK_U32 Istatus) /* Interrupt status word */ /* Timer interrupt (served last) */ if ((Istatus & IS_TIMINT) != 0) { + /* check for HW Errors */ + if (((Istatus & IS_HW_ERR) & ~pAC->GIni.GIValIrqMask) != 0) { + /* read the HW Error Interrupt source */ + SK_IN32(IoC, B0_HWE_ISRC, &RegVal32); + + SkGeYuHwErr(pAC, IoC, RegVal32); + } + SkHwtIsr(pAC, IoC); } -} /* SkGeSirqIsr */ + +} /* SkGeYuSirqIsr */ + +#ifdef YUK2 +/****************************************************************************** + * + * SkYuk2PortSirq() - Service HW Errors for specified port (Yukon-2 only) + * + * Description: handles the HW Error interrupts for a specific port. + * + * Returns: N/A + */ +static void SkYuk2PortSirq( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 IStatus, /* Interrupt status word */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_EVPARA Para; + int Queue; + SK_U16 PhyInt; + + if (Port == MAC_2) { + IStatus >>= 8; + } + + /* Interrupt from PHY */ + if ((IStatus & Y2_IS_IRQ_PHY1) != 0) { + /* Read PHY Interrupt Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyInt); + + if ((PhyInt & PHY_M_DEF_MSK) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Port %d PHY Int: 0x%04X\n", Port, PhyInt)); + SkPhyIsrGmac(pAC, IoC, Port, PhyInt); + } + } + + /* Interrupt from MAC */ + if ((IStatus & Y2_IS_IRQ_MAC1) != 0) { + SkMacIrq(pAC, IoC, Port); + } + + if ((IStatus & (Y2_IS_CHK_RX1 | Y2_IS_CHK_TXS1 | Y2_IS_CHK_TXA1)) != 0) { + if ((IStatus & Y2_IS_CHK_RX1) != 0) { + if (Port == MAC_1) { + Queue = Q_R1; + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E006, + SKERR_SIRQ_E006MSG); + } + else { + Queue = Q_R2; + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E007, + SKERR_SIRQ_E007MSG); + } + /* Clear IRQ */ + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK); + } + + if ((IStatus & Y2_IS_CHK_TXS1) != 0) { + if (Port == MAC_1) { + Queue = Q_XS1; + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E008, + SKERR_SIRQ_E008MSG); + } + else { + Queue = Q_XS2; + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E010, + SKERR_SIRQ_E010MSG); + } + /* Clear IRQ */ + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK); + } + + if ((IStatus & Y2_IS_CHK_TXA1) != 0) { + if (Port == MAC_1) { + Queue = Q_XA1; + + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E009, + SKERR_SIRQ_E009MSG); + + } + else { + Queue = Q_XA2; + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E011, + SKERR_SIRQ_E011MSG); + } + /* Clear IRQ */ + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK); + } + + Para.Para64 = Port; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + + Para.Para32[0] = Port; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } +} /* SkYuk2PortSirq */ +#endif /* YUK2 */ + +/****************************************************************************** + * + * SkYuk2SirqIsr() - Special Interrupt Service Routine (Yukon-2 only) + * + * Description: handles all non data transfer specific interrupts (slow path) + * + * Returns: N/A + */ +void SkYuk2SirqIsr( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Istatus) /* Interrupt status word */ +{ +#ifdef YUK2 + SK_EVPARA Para; + SK_U32 RegVal32; /* Read register value */ + SK_U8 Value; + + /* HW Error indicated ? */ + if (((Istatus & Y2_IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) { + /* read the HW Error Interrupt source */ + SK_IN32(IoC, B0_HWE_ISRC, &RegVal32); + + SkYuk2HwErr(pAC, IoC, RegVal32); + } + + /* Interrupt from ASF Subsystem */ + if ((Istatus & Y2_IS_ASF) != 0) { + /* clear IRQ */ + /* later on clearing should be done in ASF ISR handler */ + SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Value); + Value |= Y2_ASF_CLR_HSTI; + SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, Value); + /* Call IRQ handler in ASF Module */ + /* TBD */ + } + + /* Check IRQ from polling unit */ + if ((Istatus & Y2_IS_POLL_CHK) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, POLL_CTRL, PC_CLR_IRQ_CHK); + + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E036, + SKERR_SIRQ_E036MSG); + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); + } + + /* TWSI Ready interrupt */ + if ((Istatus & Y2_IS_TWSI_RDY) != 0) { +#ifdef SK_SLIM + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); +#else + SkI2cIsr(pAC, IoC); +#endif + } + + /* SW forced interrupt */ + if ((Istatus & Y2_IS_IRQ_SW) != 0) { + /* clear the software IRQ */ + SK_OUT8(IoC, B0_CTST, CS_CL_SW_IRQ); + } + + if ((Istatus & Y2_IS_L1_MASK) != 0) { + SkYuk2PortSirq(pAC, IoC, Istatus, MAC_1); + } + + if ((Istatus & Y2_IS_L2_MASK) != 0) { + SkYuk2PortSirq(pAC, IoC, Istatus, MAC_2); + } + + /* Timer interrupt (served last) */ + if ((Istatus & Y2_IS_TIMINT) != 0) { + + if (((Istatus & Y2_IS_HW_ERR) & ~pAC->GIni.GIValIrqMask) != 0) { + /* read the HW Error Interrupt source */ + SK_IN32(IoC, B0_HWE_ISRC, &RegVal32); + + /* otherwise we would generate error log entries periodically */ + RegVal32 &= pAC->GIni.GIValHwIrqMask; + if (RegVal32 != 0) { + SkYuk2HwErr(pAC, IoC, RegVal32); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Timer Int: 0x%08lX\n", Istatus)); + SkHwtIsr(pAC, IoC); + } +#endif /* YUK2 */ + +} /* SkYuk2SirqIsr */ +#ifdef GENESIS /****************************************************************************** * * SkGePortCheckShorts() - Implementing XMAC Workaround Errata # 2 @@ -1114,10 +1336,10 @@ SK_U32 Istatus) /* Interrupt status word */ * 0 o.k. nothing needed * 1 Restart needed on this port */ -static int SkGePortCheckShorts( +static int SkGePortCheckShorts( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO Context */ -int Port) /* Which port should be checked */ +SK_IOC IoC, /* I/O Context */ +int Port) /* Port Index (MAC_1 + n) */ { SK_U32 Shorts; /* Short Event Counter */ SK_U32 CheckShorts; /* Check value for Short Event Counter */ @@ -1139,13 +1361,15 @@ int Port) /* Which port should be checked */ (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXE_SHT_ERR, &Shorts); /* - * Read Rx counter (packets seen on the network and not necessarily + * Read Rx counters (packets seen on the network and not necessarily * really received. */ RxCts = 0; for (i = 0; i < sizeof(SkGeRxRegs)/sizeof(SkGeRxRegs[0]); i++) { + (void)SkXmMacStatistic(pAC, IoC, Port, SkGeRxRegs[i], &RxTmp); + RxCts += (SK_U64)RxTmp; } @@ -1163,10 +1387,10 @@ int Port) /* Which port should be checked */ (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXF_FCS_ERR, &FcsErrCts); - if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && - pPrt->PLipaAutoNeg == SK_LIPA_UNKNOWN && - (pPrt->PLinkMode == SK_LMODE_HALF || - pPrt->PLinkMode == SK_LMODE_FULL)) { + if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_UNKNOWN && + (pPrt->PLinkMode == (SK_U8)SK_LMODE_HALF || + pPrt->PLinkMode == (SK_U8)SK_LMODE_FULL)) { /* * This is autosensing and we are in the fallback * manual full/half duplex mode. @@ -1179,12 +1403,12 @@ int Port) /* Which port should be checked */ return(SK_HW_PS_RESTART); } else { - pPrt->PLipaAutoNeg = SK_LIPA_MANUAL; + pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_MANUAL; } } if (((RxCts - pPrt->PPrevRx) > pPrt->PRxLim) || - (!(FcsErrCts - pPrt->PPrevFcs))) { + (!(FcsErrCts - pPrt->PPrevFcs))) { /* * Note: The compare with zero above has to be done the way shown, * otherwise the Linux driver will have a problem. @@ -1215,6 +1439,7 @@ int Port) /* Which port should be checked */ return(Rtv); } /* SkGePortCheckShorts */ +#endif /* GENESIS */ /****************************************************************************** @@ -1226,30 +1451,57 @@ int Port) /* Which port should be checked */ * 1 Restart needed on this port * 2 Link came up */ -static int SkGePortCheckUp( +static int SkGePortCheckUp( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO Context */ -int Port) /* Which port should be checked */ +SK_IOC IoC, /* I/O Context */ +int Port) /* Port Index (MAC_1 + n) */ { - switch (pAC->GIni.GP[Port].PhyType) { - case SK_PHY_XMAC: - return(SkGePortCheckUpXmac(pAC, IoC, Port)); - case SK_PHY_BCOM: - return(SkGePortCheckUpBcom(pAC, IoC, Port)); - case SK_PHY_MARV_COPPER: - case SK_PHY_MARV_FIBER: - return(SkGePortCheckUpGmac(pAC, IoC, Port)); + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ + int Rtv; /* Return value */ + + Rtv = SK_HW_PS_NONE; + + pPrt = &pAC->GIni.GP[Port]; + + AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF && + pPrt->PLinkMode != SK_LMODE_FULL; + +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { + + switch (pPrt->PhyType) { + + case SK_PHY_XMAC: + Rtv = SkGePortCheckUpXmac(pAC, IoC, Port, AutoNeg); + break; + case SK_PHY_BCOM: + Rtv = SkGePortCheckUpBcom(pAC, IoC, Port, AutoNeg); + break; #ifdef OTHER_PHY - case SK_PHY_LONE: - return(SkGePortCheckUpLone(pAC, IoC, Port)); - case SK_PHY_NAT: - return(SkGePortCheckUpNat(pAC, IoC, Port)); + case SK_PHY_LONE: + Rtv = SkGePortCheckUpLone(pAC, IoC, Port, AutoNeg); + break; + case SK_PHY_NAT: + Rtv = SkGePortCheckUpNat(pAC, IoC, Port, AutoNeg); + break; #endif /* OTHER_PHY */ + } } - return(SK_HW_PS_NONE); +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { + + Rtv = SkGePortCheckUpGmac(pAC, IoC, Port, AutoNeg); + } +#endif /* YUKON */ + + return(Rtv); } /* SkGePortCheckUp */ +#ifdef GENESIS /****************************************************************************** * * SkGePortCheckUpXmac() - Implementing of the Workaround Errata # 2 @@ -1261,8 +1513,9 @@ int Port) /* Which port should be checked */ */ static int SkGePortCheckUpXmac( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO Context */ -int Port) /* Which port should be checked */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */ { SK_U32 Shorts; /* Short Event Counter */ SK_GEPORT *pPrt; /* GIni Port struct pointer */ @@ -1273,7 +1526,6 @@ int Port) /* Which port should be checked */ SK_U16 LpAb; /* Link Partner Ability */ SK_U16 ResAb; /* Resolved Ability */ SK_U16 ExtStat; /* Extended Status Register */ - SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ SK_U8 NextMode; /* Next AutoSensing Mode */ pPrt = &pAC->GIni.GP[Port]; @@ -1291,13 +1543,6 @@ int Port) /* Which port should be checked */ pPrt->PIsave = 0; /* Now wait for each port's link */ - if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { - AutoNeg = SK_FALSE; - } - else { - AutoNeg = SK_TRUE; - } - if (pPrt->PLinkBroken) { /* Link was broken */ XM_IN32(IoC, Port, XM_GP_PORT, &GpReg); @@ -1326,7 +1571,7 @@ int Port) /* Which port should be checked */ * Link Restart Workaround: * it may be possible that the other Link side * restarts its link as well an we detect - * another LinkBroken. To prevent this + * another PLinkBroken. To prevent this * happening we check for a maximum number * of consecutive restart. If those happens, * we do NOT restart the active link and @@ -1374,7 +1619,7 @@ int Port) /* Which port should be checked */ if ((Isrc & XM_IS_INP_ASS) != 0) { pPrt->PLinkBroken = SK_TRUE; /* Re-Init Link partner Autoneg flag */ - pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN; + pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN; SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("Link broken Port %d\n", Port)); @@ -1387,6 +1632,7 @@ int Port) /* Which port should be checked */ } else { SkXmAutoNegLipaXmac(pAC, IoC, Port, Isrc); + if (SkGePortCheckShorts(pAC, IoC, Port) == SK_HW_PS_RESTART) { return(SK_HW_PS_RESTART); } @@ -1418,20 +1664,26 @@ int Port) /* Which port should be checked */ } if (AutoNeg) { + /* Auto-Negotiation Done ? */ if ((IsrcSum & XM_IS_AND) != 0) { + SkHWLinkUp(pAC, IoC, Port); + Done = SkMacAutoNegDone(pAC, IoC, Port); + if (Done != SK_AND_OK) { /* Get PHY parameters, for debugging only */ SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LpAb); SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb); - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("AutoNeg FAIL Port %d (LpAb %x, ResAb %x)\n", - Port, LpAb, ResAb)); + Port, LpAb, ResAb)); /* Try next possible mode */ NextMode = SkHWSenseGetNext(pAC, IoC, Port); + SkHWLinkDown(pAC, IoC, Port); + if (Done == SK_AND_DUP_CAP) { /* GoTo next mode */ SkHWSenseSetNext(pAC, IoC, Port, NextMode); @@ -1444,43 +1696,41 @@ int Port) /* Which port should be checked */ * (clear Page Received bit if set) */ SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_EXP, &ExtStat); - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNeg done Port %d\n", Port)); + return(SK_HW_PS_LINK); } /* AutoNeg not done, but HW link is up. Check for timeouts */ - pPrt->PAutoNegTimeOut++; - if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) { + if (pPrt->PAutoNegTimeOut++ >= SK_AND_MAX_TO) { /* Increase the Timeout counter */ pPrt->PAutoNegTOCt++; /* Timeout occured */ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("AutoNeg timeout Port %d\n", Port)); - if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && - pPrt->PLipaAutoNeg != SK_LIPA_AUTO) { + if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg != (SK_U8)SK_LIPA_AUTO) { /* Set Link manually up */ SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("Set manual full duplex Port %d\n", Port)); } - if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && - pPrt->PLipaAutoNeg == SK_LIPA_AUTO && + if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO && pPrt->PAutoNegTOCt >= SK_MAX_ANEG_TO) { /* * This is rather complicated. * we need to check here whether the LIPA_AUTO * we saw before is false alert. We saw at one - * switch ( SR8800) that on boot time it sends + * switch (SR8800) that on boot time it sends * just one auto-neg packet and does no further * auto-negotiation. * Solution: we restart the autosensing after * a few timeouts. */ pPrt->PAutoNegTOCt = 0; - pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN; + pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN; SkHWInitDefSense(pAC, IoC, Port); } @@ -1491,8 +1741,8 @@ int Port) /* Which port should be checked */ else { /* Link is up and we don't need more */ #ifdef DEBUG - if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("ERROR: Lipa auto detected on port %d\n", Port)); } #endif /* DEBUG */ @@ -1501,8 +1751,8 @@ int Port) /* Which port should be checked */ SkHWLinkUp(pAC, IoC, Port); /* - * Link sync (GP) and so assume a good connection. But if not received - * a bunch of frames received in a time slot (maybe broken tx cable) + * Link sync (GP) and so assume a good connection. But if no + * bunch of frames received in a time slot (maybe broken Tx cable) * the port is restart. */ return(SK_HW_PS_LINK); @@ -1522,95 +1772,27 @@ int Port) /* Which port should be checked */ * 2 Link came up */ static int SkGePortCheckUpBcom( -SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO Context */ -int Port) /* Which port should be checked */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */ { SK_GEPORT *pPrt; /* GIni Port struct pointer */ int Done; SK_U16 Isrc; /* Interrupt source register */ - SK_U16 PhyStat; /* Phy Status Register */ + SK_U16 PhyStat; /* PHY Status Register */ SK_U16 ResAb; /* Master/Slave resolution */ SK_U16 Ctrl; /* Broadcom control flags */ #ifdef DEBUG SK_U16 LpAb; SK_U16 ExtStat; #endif /* DEBUG */ - SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ pPrt = &pAC->GIni.GP[Port]; /* Check for No HCD Link events (#10523) */ SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &Isrc); -#ifdef xDEBUG - if ((Isrc & ~(PHY_B_IS_HCT | PHY_B_IS_LCT) == - (PHY_B_IS_SCR_S_ER | PHY_B_IS_RRS_CHANGE | PHY_B_IS_LRS_CHANGE)) { - - SK_U32 Stat1, Stat2, Stat3; - - Stat1 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1); - CMSMPrintString( - pAC->pConfigTable, - MSG_TYPE_RUNTIME_INFO, - "CheckUp1 - Stat: %x, Mask: %x", - (void *)Isrc, - (void *)Stat1); - - Stat1 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1); - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &Stat2); - Stat1 = Stat1 << 16 | Stat2; - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2); - Stat3 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3); - Stat2 = Stat2 << 16 | Stat3; - CMSMPrintString( - pAC->pConfigTable, - MSG_TYPE_RUNTIME_INFO, - "Ctrl/Stat: %x, AN Adv/LP: %x", - (void *)Stat1, - (void *)Stat2); - - Stat1 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1); - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2); - Stat1 = Stat1 << 16 | Stat2; - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2); - Stat3 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &Stat3); - Stat2 = Stat2 << 16 | Stat3; - CMSMPrintString( - pAC->pConfigTable, - MSG_TYPE_RUNTIME_INFO, - "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x", - (void *)Stat1, - (void *)Stat2); - - Stat1 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1); - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2); - Stat1 = Stat1 << 16 | Stat2; - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2); - Stat3 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3); - Stat2 = Stat2 << 16 | Stat3; - CMSMPrintString( - pAC->pConfigTable, - MSG_TYPE_RUNTIME_INFO, - "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x", - (void *)Stat1, - (void *)Stat2); - } -#endif /* DEBUG */ - if ((Isrc & (PHY_B_IS_NO_HDCL /* | PHY_B_IS_NO_HDC */)) != 0) { /* * Workaround BCom Errata: @@ -1623,14 +1805,6 @@ int Port) /* Which port should be checked */ (SK_U16)(Ctrl & ~PHY_CT_LOOP)); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, ("No HCD Link event, Port %d\n", Port)); -#ifdef xDEBUG - CMSMPrintString( - pAC->pConfigTable, - MSG_TYPE_RUNTIME_INFO, - "No HCD link event, port %d.", - (void *)Port, - (void *)NULL); -#endif /* DEBUG */ } /* Not obsolete: link status bit is latched to 0 and autoclearing! */ @@ -1640,80 +1814,6 @@ int Port) /* Which port should be checked */ return(SK_HW_PS_NONE); } -#ifdef xDEBUG - { - SK_U32 Stat1, Stat2, Stat3; - - Stat1 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1); - CMSMPrintString( - pAC->pConfigTable, - MSG_TYPE_RUNTIME_INFO, - "CheckUp1a - Stat: %x, Mask: %x", - (void *)Isrc, - (void *)Stat1); - - Stat1 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1); - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat); - Stat1 = Stat1 << 16 | PhyStat; - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2); - Stat3 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3); - Stat2 = Stat2 << 16 | Stat3; - CMSMPrintString( - pAC->pConfigTable, - MSG_TYPE_RUNTIME_INFO, - "Ctrl/Stat: %x, AN Adv/LP: %x", - (void *)Stat1, - (void *)Stat2); - - Stat1 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1); - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2); - Stat1 = Stat1 << 16 | Stat2; - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2); - Stat3 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb); - Stat2 = Stat2 << 16 | ResAb; - CMSMPrintString( - pAC->pConfigTable, - MSG_TYPE_RUNTIME_INFO, - "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x", - (void *)Stat1, - (void *)Stat2); - - Stat1 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1); - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2); - Stat1 = Stat1 << 16 | Stat2; - Stat2 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2); - Stat3 = 0; - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3); - Stat2 = Stat2 << 16 | Stat3; - CMSMPrintString( - pAC->pConfigTable, - MSG_TYPE_RUNTIME_INFO, - "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x", - (void *)Stat1, - (void *)Stat2); - } -#endif /* DEBUG */ - - /* Now wait for each port's link */ - if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { - AutoNeg = SK_FALSE; - } - else { - AutoNeg = SK_TRUE; - } - /* * Here we usually can check whether the link is in sync and * auto-negotiation is done. @@ -1724,14 +1824,15 @@ int Port) /* Which port should be checked */ SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat)); + ("CheckUp Port %d, PhyStat: 0x%04X\n", Port, PhyStat)); SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb); if ((ResAb & PHY_B_1000S_MSF) != 0) { /* Error */ - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("Master/Slave Fault port %d\n", Port)); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("Master/Slave Fault, ResAb: 0x%04X\n", ResAb)); + pPrt->PAutoNegFail = SK_TRUE; pPrt->PMSStatus = SK_MS_STAT_FAULT; @@ -1746,158 +1847,7 @@ int Port) /* Which port should be checked */ SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE; SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat)); - - if (AutoNeg) { - if ((PhyStat & PHY_ST_AN_OVER) != 0) { - SkHWLinkUp(pAC, IoC, Port); - Done = SkMacAutoNegDone(pAC, IoC, Port); - if (Done != SK_AND_OK) { -#ifdef DEBUG - /* Get PHY parameters, for debugging only */ - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LpAb); - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ExtStat); - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n", - Port, LpAb, ExtStat)); -#endif /* DEBUG */ - return(SK_HW_PS_RESTART); - } - else { -#ifdef xDEBUG - /* Dummy read ISR to prevent extra link downs/ups */ - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat); - - if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) { - CMSMPrintString( - pAC->pConfigTable, - MSG_TYPE_RUNTIME_INFO, - "CheckUp2 - Stat: %x", - (void *)ExtStat, - (void *)NULL); - } -#endif /* DEBUG */ - - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNeg done Port %d\n", Port)); - return(SK_HW_PS_LINK); - } - } - } - else { /* !AutoNeg */ - /* Link is up and we don't need more. */ -#ifdef DEBUG - if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("ERROR: Lipa auto detected on port %d\n", Port)); - } -#endif /* DEBUG */ - -#ifdef xDEBUG - /* Dummy read ISR to prevent extra link downs/ups */ - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat); - - if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) { - CMSMPrintString( - pAC->pConfigTable, - MSG_TYPE_RUNTIME_INFO, - "CheckUp3 - Stat: %x", - (void *)ExtStat, - (void *)NULL); - } -#endif /* DEBUG */ - - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, - ("Link sync(GP), Port %d\n", Port)); - SkHWLinkUp(pAC, IoC, Port); - return(SK_HW_PS_LINK); - } - - return(SK_HW_PS_NONE); -} /* SkGePortCheckUpBcom */ - - -/****************************************************************************** - * - * SkGePortCheckUpGmac() - Check if the link is up on Marvell PHY - * - * return: - * 0 o.k. nothing needed - * 1 Restart needed on this port - * 2 Link came up - */ -static int SkGePortCheckUpGmac( -SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO Context */ -int Port) /* Which port should be checked */ -{ - SK_GEPORT *pPrt; /* GIni Port struct pointer */ - int Done; - SK_U16 Isrc; /* Interrupt source */ - SK_U16 PhyStat; /* Phy Status */ - SK_U16 PhySpecStat;/* Phy Specific Status */ - SK_U16 ResAb; /* Master/Slave resolution */ - SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ - - pPrt = &pAC->GIni.GP[Port]; - - /* Read PHY Interrupt Status */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &Isrc); - - if ((Isrc & PHY_M_IS_AN_COMPL) != 0) { - /* TBD */ - } - - if ((Isrc & PHY_M_IS_DOWNSH_DET) != 0) { - /* TBD */ - } - - if (pPrt->PHWLinkUp) { - return(SK_HW_PS_NONE); - } - - /* Now wait for each port's link */ - if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { - AutoNeg = SK_FALSE; - } - else { - AutoNeg = SK_TRUE; - } - - /* Read PHY Status */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat); - - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat)); - - SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat); - - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb); - - if ((ResAb & PHY_B_1000S_MSF) != 0) { - /* Error */ - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("Master/Slave Fault port %d\n", Port)); - pPrt->PAutoNegFail = SK_TRUE; - pPrt->PMSStatus = SK_MS_STAT_FAULT; - - return(SK_HW_PS_RESTART); - } - - /* Read PHY Specific Status */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat); - - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNeg: %d, PhySpecStat: 0x%04x\n", AutoNeg, PhySpecStat)); - - if ((PhySpecStat & PHY_M_PS_LINK_UP) == 0) { - return(SK_HW_PS_NONE); - } - - pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? - SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE; - - pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7); + ("Port %d, ResAb: 0x%04X\n", Port, ResAb)); if (AutoNeg) { /* Auto-Negotiation Over ? */ @@ -1908,23 +1858,211 @@ int Port) /* Which port should be checked */ Done = SkMacAutoNegDone(pAC, IoC, Port); if (Done != SK_AND_OK) { +#ifdef DEBUG + /* Get PHY parameters, for debugging only */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LpAb); + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ExtStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n", + Port, LpAb, ExtStat)); +#endif /* DEBUG */ return(SK_HW_PS_RESTART); } - - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNeg done Port %d\n", Port)); - return(SK_HW_PS_LINK); + else { + return(SK_HW_PS_LINK); + } } } else { /* !AutoNeg */ /* Link is up and we don't need more */ #ifdef DEBUG - if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("ERROR: Lipa auto detected on port %d\n", Port)); } #endif /* DEBUG */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link sync(GP), Port %d\n", Port)); + SkHWLinkUp(pAC, IoC, Port); + + return(SK_HW_PS_LINK); + } + + return(SK_HW_PS_NONE); +} /* SkGePortCheckUpBcom */ +#endif /* GENESIS */ + + +#ifdef YUKON +/****************************************************************************** + * + * SkGePortCheckUpGmac() - Check if the link is up on Marvell PHY + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUpGmac( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Done; + SK_U16 PhyStat; /* PHY Status */ + SK_U16 PhySpecStat;/* PHY Specific Status */ + SK_U16 ResAb; /* Master/Slave resolution */ +#ifndef SK_SLIM + SK_EVPARA Para; +#endif /* !SK_SLIM */ +#ifdef DEBUG + SK_U16 Word; /* I/O helper */ +#endif /* DEBUG */ + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PHWLinkUp) { + return(SK_HW_PS_NONE); + } + + /* Read PHY Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("CheckUp Port %d, PhyStat: 0x%04X\n", Port, PhyStat)); + + SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat); + + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) { + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb); + + if ((ResAb & PHY_B_1000S_MSF) != 0) { + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("Master/Slave Fault, ResAb: 0x%04X\n", ResAb)); + + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + + return(SK_HW_PS_RESTART); + } + } + + /* Read PHY Specific Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Phy1000BT: 0x%04X, PhySpecStat: 0x%04X\n", ResAb, PhySpecStat)); + +#if (defined(DEBUG) && !defined(SK_SLIM)) + /* Read PHY Auto-Negotiation Expansion */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &Word); + + if (pAC->GIni.GICopperType && (Word & PHY_ANE_LP_CAP) == 0) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n", Word)); + } + + if ((Word & PHY_ANE_RX_PG) != 0 || + (PhySpecStat & PHY_M_PS_PAGE_REC) != 0) { + /* Read PHY Next Page Link Partner */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_NEPG_LP, &Word); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Page received, NextPage: 0x%04X\n", Word)); + } +#endif /* DEBUG && !SK_SLIM */ + + if ((PhySpecStat & PHY_M_PS_LINK_UP) == 0) { + /* Link down */ + return(SK_HW_PS_NONE); + } + +#ifdef XXX + SK_U16 PhyInt; + /* Read PHY Interrupt Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyInt); + + /* cross check that the link is really up */ + if ((PhyInt & PHY_M_IS_LST_CHANGE) == 0) { + /* Link Status unchanged */ + return(SK_HW_PS_NONE); + } +#endif /* XXX */ + +#ifndef SK_SLIM + if (pAC->GIni.GICopperType) { + + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) { + + if ((PhySpecStat & PHY_M_PS_DOWNS_STAT) != 0) { + /* Downshift detected */ + Para.Para64 = Port; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_DOWNSHIFT_DET, Para); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Downshift detected, PhySpecStat: 0x%04X\n", PhySpecStat)); + + SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_SIRQ_E025, + SKERR_SIRQ_E025MSG); + } + + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? + SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE; + } + + if ((PhySpecStat & PHY_M_PS_MDI_X_STAT) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("MDI Xover detected, PhyStat: 0x%04X\n", PhySpecStat)); + } + + /* on PHY 88E1112 & 88E1145 cable length is in Reg. 26, Page 5 */ + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL || + pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) { + /* select page 5 to access VCT DSP distance register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5); + + /* get VCT DSP distance */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, &PhySpecStat); + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0); + + pPrt->PCableLen = (SK_U8)(PhySpecStat & PHY_M_EC2_FO_AM_MSK); + } + else { + pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7); + } + } +#endif /* !SK_SLIM */ + + if (AutoNeg) { + /* Auto-Negotiation Complete ? */ + if ((PhyStat & PHY_ST_AN_OVER) != 0) { + + SkHWLinkUp(pAC, IoC, Port); + + Done = SkMacAutoNegDone(pAC, IoC, Port); + + if (Done != SK_AND_OK) { + return(SK_HW_PS_RESTART); + } + + return(SK_HW_PS_LINK); + } + } + else { /* !AutoNeg */ +#if (defined(DEBUG) && !defined(SK_SLIM)) + if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("ERROR: Lipa auto detected on port %d\n", Port)); + } +#endif /* DEBUG && !SK_SLIM */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("Link sync, Port %d\n", Port)); SkHWLinkUp(pAC, IoC, Port); @@ -1935,6 +2073,8 @@ int Port) /* Which port should be checked */ return(SK_HW_PS_NONE); } /* SkGePortCheckUpGmac */ +#endif /* YUKON */ + #ifdef OTHER_PHY /****************************************************************************** @@ -1948,17 +2088,17 @@ int Port) /* Which port should be checked */ */ static int SkGePortCheckUpLone( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO Context */ -int Port) /* Which port should be checked */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */ { SK_GEPORT *pPrt; /* GIni Port struct pointer */ int Done; SK_U16 Isrc; /* Interrupt source register */ SK_U16 LpAb; /* Link Partner Ability */ SK_U16 ExtStat; /* Extended Status Register */ - SK_U16 PhyStat; /* Phy Status Register */ + SK_U16 PhyStat; /* PHY Status Register */ SK_U16 StatSum; - SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ SK_U8 NextMode; /* Next AutoSensing Mode */ pPrt = &pAC->GIni.GP[Port]; @@ -1970,14 +2110,6 @@ int Port) /* Which port should be checked */ StatSum = pPrt->PIsave; pPrt->PIsave = 0; - /* Now wait for each ports link */ - if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { - AutoNeg = SK_FALSE; - } - else { - AutoNeg = SK_TRUE; - } - /* * here we usually can check whether the link is in sync and * auto-negotiation is done. @@ -2000,20 +2132,26 @@ int Port) /* Which port should be checked */ } if (AutoNeg) { + /* Auto-Negotiation Over ? */ if ((StatSum & PHY_ST_AN_OVER) != 0) { + SkHWLinkUp(pAC, IoC, Port); + Done = SkMacAutoNegDone(pAC, IoC, Port); + if (Done != SK_AND_OK) { /* Get PHY parameters, for debugging only */ SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LpAb); SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ExtStat); - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n", Port, LpAb, ExtStat)); /* Try next possible mode */ NextMode = SkHWSenseGetNext(pAC, IoC, Port); + SkHWLinkDown(pAC, IoC, Port); + if (Done == SK_AND_DUP_CAP) { /* GoTo next mode */ SkHWSenseSetNext(pAC, IoC, Port, NextMode); @@ -2028,20 +2166,17 @@ int Port) /* Which port should be checked */ * extra link down/ups */ SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat); - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNeg done Port %d\n", Port)); return(SK_HW_PS_LINK); } } /* AutoNeg not done, but HW link is up. Check for timeouts */ - pPrt->PAutoNegTimeOut++; - if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) { + if (pPrt->PAutoNegTimeOut++ >= SK_AND_MAX_TO) { /* Timeout occured */ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("AutoNeg timeout Port %d\n", Port)); - if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && - pPrt->PLipaAutoNeg != SK_LIPA_AUTO) { + if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg != (SK_U8)SK_LIPA_AUTO) { /* Set Link manually up */ SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, @@ -2055,8 +2190,8 @@ int Port) /* Which port should be checked */ else { /* Link is up and we don't need more */ #ifdef DEBUG - if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("ERROR: Lipa auto detected on port %d\n", Port)); } #endif /* DEBUG */ @@ -2069,7 +2204,9 @@ int Port) /* Which port should be checked */ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("Link sync(GP), Port %d\n", Port)); + SkHWLinkUp(pAC, IoC, Port); + return(SK_HW_PS_LINK); } @@ -2088,8 +2225,9 @@ int Port) /* Which port should be checked */ */ static int SkGePortCheckUpNat( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO Context */ -int Port) /* Which port should be checked */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */ { /* todo: National */ return(SK_HW_PS_NONE); @@ -2107,32 +2245,39 @@ int Port) /* Which port should be checked */ */ int SkGeSirqEvent( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* Io Context */ +SK_IOC IoC, /* I/O Context */ SK_U32 Event, /* Module specific Event */ SK_EVPARA Para) /* Event specific Parameter */ { - SK_U64 Octets; SK_GEPORT *pPrt; /* GIni Port struct pointer */ - SK_U32 Port; - SK_U32 Time; - unsigned Len; + int Port; + SK_U32 Val32; int PortStat; +#ifndef SK_SLIM SK_U8 Val8; +#endif +#ifdef GENESIS + SK_U64 Octets; +#endif /* GENESIS */ - Port = Para.Para32[0]; + Port = (int)Para.Para32[0]; pPrt = &pAC->GIni.GP[Port]; switch (Event) { case SK_HWEV_WATIM: - /* Check whether port came up */ - PortStat = SkGePortCheckUp(pAC, IoC, Port); + if (pPrt->PState == SK_PRT_RESET) { + + PortStat = SK_HW_PS_NONE; + } + else { + /* Check whether port came up */ + PortStat = SkGePortCheckUp(pAC, IoC, Port); + } switch (PortStat) { case SK_HW_PS_RESTART: if (pPrt->PHWLinkUp) { - /* - * Set Link to down. - */ + /* Set Link to down */ SkHWLinkDown(pAC, IoC, Port); /* @@ -2150,24 +2295,29 @@ SK_EVPARA Para) /* Event specific Parameter */ /* Signal to RLMT */ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_UP, Para); break; - } /* Start again the check Timer */ if (pPrt->PHWLinkUp) { - Time = SK_WA_ACT_TIME; + + Val32 = SK_WA_ACT_TIME; } else { - Time = SK_WA_INA_TIME; - } + Val32 = SK_WA_INA_TIME; - /* Todo: still needed for non-XMAC PHYs??? */ + if (pAC->GIni.GIYukon) { + Val32 *= 5; + } + } /* Start workaround Errata #2 timer */ - SkTimerStart(pAC, IoC, &pPrt->PWaTimer, Time, + SkTimerStart(pAC, IoC, &pPrt->PWaTimer, Val32, SKGE_HWAC, SK_HWEV_WATIM, Para); + break; case SK_HWEV_PORT_START: + +#ifndef SK_SLIM if (pPrt->PHWLinkUp) { /* * Signal directly to RLMT to ensure correct @@ -2175,6 +2325,7 @@ SK_EVPARA Para) /* Event specific Parameter */ */ SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para); } +#endif /* !SK_SLIM */ SkHWLinkDown(pAC, IoC, Port); @@ -2184,9 +2335,11 @@ SK_EVPARA Para) /* Event specific Parameter */ /* Start workaround Errata #2 timer */ SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME, SKGE_HWAC, SK_HWEV_WATIM, Para); + break; case SK_HWEV_PORT_STOP: +#ifndef SK_SLIM if (pPrt->PHWLinkUp) { /* * Signal directly to RLMT to ensure correct @@ -2194,6 +2347,7 @@ SK_EVPARA Para) /* Event specific Parameter */ */ SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para); } +#endif /* !SK_SLIM */ /* Stop Workaround Timer */ SkTimerStop(pAC, IoC, &pPrt->PWaTimer); @@ -2201,13 +2355,14 @@ SK_EVPARA Para) /* Event specific Parameter */ SkHWLinkDown(pAC, IoC, Port); break; +#ifndef SK_SLIM case SK_HWEV_UPDATE_STAT: /* We do NOT need to update any statistics */ break; case SK_HWEV_CLEAR_STAT: /* We do NOT need to clear any statistics */ - for (Port = 0; Port < (SK_U32)pAC->GIni.GIMacsFound; Port++) { + for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) { pPrt->PPrevRx = 0; pPrt->PPrevFcs = 0; pPrt->PPrevShorts = 0; @@ -2245,7 +2400,7 @@ SK_EVPARA Para) /* Event specific Parameter */ } Val8 = (SK_U8)Para.Para32[1]; if (pPrt->PMSMode != Val8) { - /* Set New link mode */ + /* Set New Role (Master/Slave) mode */ pPrt->PMSMode = Val8; /* Restart Port */ @@ -2268,27 +2423,38 @@ SK_EVPARA Para) /* Event specific Parameter */ SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para); } break; +#endif /* !SK_SLIM */ +#ifdef GENESIS case SK_HWEV_HALFDUP_CHK: - /* - * half duplex hangup workaround. - * See packet arbiter timeout interrupt for description - */ - pPrt->HalfDupTimerActive = SK_FALSE; - if (pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || - pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) { + if (pAC->GIni.GIGenesis) { + /* + * half duplex hangup workaround. + * See packet arbiter timeout interrupt for description + */ + pPrt->HalfDupTimerActive = SK_FALSE; + if (pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) { - Len = sizeof(SK_U64); - SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets, - &Len, (SK_U32)SK_PNMI_PORT_PHYS2INST(pAC, Port), - pAC->Rlmt.Port[Port].Net->NetNumber); + /* Snap statistic counters */ + (void)SkXmUpdateStats(pAC, IoC, Port); - if (pPrt->LastOctets == Octets) { - /* Tx hanging, a FIFO flush restarts it */ - SkMacFlushTxFifo(pAC, IoC, Port); + (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXO_OK_HI, &Val32); + + Octets = (SK_U64)Val32 << 32; + + (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXO_OK_LO, &Val32); + + Octets += Val32; + + if (pPrt->LastOctets == Octets) { + /* Tx hanging, a FIFO flush restarts it */ + SkMacFlushTxFifo(pAC, IoC, Port); + } } } break; +#endif /* GENESIS */ default: SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_SIRQ_E001, SKERR_SIRQ_E001MSG); @@ -2299,6 +2465,7 @@ SK_EVPARA Para) /* Event specific Parameter */ } /* SkGeSirqEvent */ +#ifdef GENESIS /****************************************************************************** * * SkPhyIsrBcom() - PHY interrupt service routine @@ -2309,8 +2476,8 @@ SK_EVPARA Para) /* Event specific Parameter */ */ static void SkPhyIsrBcom( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* Io Context */ -int Port, /* Port Num = PHY Num */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ SK_U16 IStatus) /* Interrupt Status */ { SK_GEPORT *pPrt; /* GIni Port struct pointer */ @@ -2320,15 +2487,15 @@ SK_U16 IStatus) /* Interrupt Status */ if ((IStatus & PHY_B_IS_PSE) != 0) { /* Incorrectable pair swap error */ - SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E022, + SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E022, SKERR_SIRQ_E022MSG); } if ((IStatus & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) != 0) { - Para.Para32[0] = (SK_U32)Port; SkHWLinkDown(pAC, IoC, Port); + Para.Para32[0] = (SK_U32)Port; /* Signal to RLMT */ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); @@ -2338,8 +2505,10 @@ SK_U16 IStatus) /* Interrupt Status */ } } /* SkPhyIsrBcom */ +#endif /* GENESIS */ +#ifdef YUKON /****************************************************************************** * * SkPhyIsrGmac() - PHY interrupt service routine @@ -2350,38 +2519,85 @@ SK_U16 IStatus) /* Interrupt Status */ */ static void SkPhyIsrGmac( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* Io Context */ -int Port, /* Port Num = PHY Num */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ SK_U16 IStatus) /* Interrupt Status */ { - SK_GEPORT *pPrt; /* GIni Port struct pointer */ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ SK_EVPARA Para; +#ifdef XXX + SK_U16 Word; +#endif /* XXX */ pPrt = &pAC->GIni.GP[Port]; - if ((IStatus & (PHY_M_IS_AN_PR | PHY_M_IS_LST_CHANGE)) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Port %d PHY IRQ, PhyIsrc: 0x%04X\n", Port, IStatus)); + + if ((IStatus & PHY_M_IS_LST_CHANGE) != 0) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Link Status changed\n")); + Para.Para32[0] = (SK_U32)Port; - SkHWLinkDown(pAC, IoC, Port); + if (pPrt->PHWLinkUp) { - /* Signal to RLMT */ - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + SkHWLinkDown(pAC, IoC, Port); + +#ifdef XXX + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &Word); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg.Adv: 0x%04X\n", Word)); + + /* Set Auto-negotiation advertisement */ + if (pAC->GIni.GIChipId != CHIP_ID_YUKON_FE && + pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) { + /* restore Asymmetric Pause bit */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, + (SK_U16)(Word | PHY_M_AN_ASP)); + } +#endif /* XXX */ + + /* Signal to RLMT */ + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + else { + if ((IStatus & PHY_M_IS_AN_COMPL) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Auto-Negotiation completed\n")); + } + + if ((IStatus & PHY_M_IS_LSP_CHANGE) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Link Speed changed\n")); + } + + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_WATIM, Para); + } } if ((IStatus & PHY_M_IS_AN_ERROR) != 0) { - /* Auto-Negotiation Error */ - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG); - } - - if ((IStatus & PHY_M_IS_LSP_CHANGE) != 0) { - /* TBD */ + /* the copper PHY makes 1 retry */ + if (pAC->GIni.GICopperType) { + /* not logged as error, it might be the first attempt */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Auto-Negotiation Error\n")); + } + else { + /* Auto-Negotiation Error */ + SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG); + } } if ((IStatus & PHY_M_IS_FIFO_ERROR) != 0) { /* FIFO Overflow/Underrun Error */ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E024, SKERR_SIRQ_E024MSG); } + } /* SkPhyIsrGmac */ +#endif /* YUKON */ #ifdef OTHER_PHY @@ -2395,23 +2611,24 @@ SK_U16 IStatus) /* Interrupt Status */ */ static void SkPhyIsrLone( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* Io Context */ -int Port, /* Port Num = PHY Num */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ SK_U16 IStatus) /* Interrupt Status */ { SK_EVPARA Para; if (IStatus & (PHY_L_IS_DUP | PHY_L_IS_ISOL)) { + SkHWLinkDown(pAC, IoC, Port); - /* Signal to RLMT */ Para.Para32[0] = (SK_U32)Port; + /* Signal to RLMT */ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); } } /* SkPhyIsrLone */ #endif /* OTHER_PHY */ -#endif /* CONFIG_SK98 */ - /* End of File */ + +#endif diff --git a/drivers/sk98lin/sklm80.c b/drivers/sk98lin/sklm80.c index 687572b..9fc1b37 100644 --- a/drivers/sk98lin/sklm80.c +++ b/drivers/sk98lin/sklm80.c @@ -1,16 +1,18 @@ /****************************************************************************** * * Name: sklm80.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.20 $ - * Date: $Date: 2002/08/13 09:16:27 $ - * Purpose: Funktions to access Voltage and Temperature Sensor (LM80) + * Project: Gigabit Ethernet Adapters, TWSI-Module + * Version: $Revision: 1.2 $ + * Date: $Date: 2005/12/14 16:10:53 $ + * Purpose: Functions to access Voltage and Temperature Sensor (LM80) * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2002 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,95 +20,20 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. + * /LICENSE * ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: sklm80.c,v $ - * Revision 1.20 2002/08/13 09:16:27 rschmidt - * Changed return value for SkLm80ReadSensor() back to 'int' - * Editorial changes - * - * Revision 1.19 2002/08/06 09:43:31 jschmalz - * Extensions and changes for Yukon - * - * Revision 1.18 2002/08/02 12:26:57 rschmidt - * Editorial changes - * - * Revision 1.17 1999/11/22 13:35:51 cgoos - * Changed license header to GPL. - * - * Revision 1.16 1999/05/27 14:05:47 malthoff - * Fans: Set SenVal to 0 if the fan value is 0 or 0xff. Both values - * are outside the limits (0: div zero error, 0xff: value not in - * range, assume 0). - * - * Revision 1.15 1999/05/27 13:38:51 malthoff - * Pervent from Division by zero errors. - * - * Revision 1.14 1999/05/20 09:20:01 cgoos - * Changes for 1000Base-T (Fan sensors). - * - * Revision 1.13 1998/10/22 09:48:14 gklug - * fix: SysKonnectFileId typo - * - * Revision 1.12 1998/10/09 06:12:06 malthoff - * Remove ID_sccs by SysKonnectFileId. - * - * Revision 1.11 1998/09/04 08:33:48 malthoff - * bug fix: SenState = SK_SEN_IDLE when - * leaving SK_SEN_VALEXT state - * - * Revision 1.10 1998/08/20 12:02:10 gklug - * fix: compiler warnings type mismatch - * - * Revision 1.9 1998/08/20 11:37:38 gklug - * chg: change Ioc to IoC - * - * Revision 1.8 1998/08/19 12:20:58 gklug - * fix: remove struct from C files (see CCC) - * - * Revision 1.7 1998/08/17 07:04:57 malthoff - * Take SkLm80RcvReg() function from ski2c.c. - * Add IoC parameter to BREAK_OR_WAIT() macro. - * - * Revision 1.6 1998/08/14 07:11:28 malthoff - * remove pAc with pAC. - * - * Revision 1.5 1998/08/14 06:46:55 gklug - * fix: temperature can get negative - * - * Revision 1.4 1998/08/13 08:27:04 gklug - * add: temperature reading now o.k. - * fix: pSen declaration, SK_ERR_LOG call, ADDR macro - * - * Revision 1.3 1998/08/13 07:28:21 gklug - * fix: pSen was wrong initialized - * add: correct conversion for voltage readings - * - * Revision 1.2 1998/08/11 07:52:14 gklug - * add: Lm80 read sensor function - * - * Revision 1.1 1998/07/17 09:57:12 gklug - * initial version - * - * - * - ******************************************************************************/ - - #include - + #ifdef CONFIG_SK98 /* LM80 functions */ +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) static const char SysKonnectFileId[] = - "$Id: sklm80.c,v 1.20 2002/08/13 09:16:27 rschmidt Exp $" ; + "@(#) $Id: sklm80.c,v 1.2 2005/12/14 16:10:53 ibrueder Exp $ (C) Marvell. "; +#endif #include "h/skdrv1st.h" /* Driver Specific Definitions */ #include "h/lm80.h" @@ -158,9 +85,9 @@ int Reg) /* register to read */ } Val = Val * SK_LM80_TEMP_LSB; SkI2cStop(IoC); - + TempExt = (int)SkLm80RcvReg(IoC, LM80_ADDR, LM80_TEMP_CTRL); - + if (Val > 0) { Val += ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB); } @@ -175,7 +102,7 @@ int Reg) /* register to read */ case LM80_VT3_IN: Val = (int)SkI2cRcvByte(IoC, 1) * SK_LM80_VT_LSB; break; - + default: Val = (int)SkI2cRcvByte(IoC, 1); break; @@ -189,12 +116,12 @@ int Reg) /* register to read */ /* * read a sensors value (LM80 specific) * - * This function reads a sensors value from the I2C sensor chip LM80. + * This function reads a sensors value from the TWSI sensor chip LM80. * The sensor is defined by its index into the sensors database in the struct * pAC points to. * * Returns 1 if the read is completed - * 0 if the read must be continued (I2C Bus still allocated) + * 0 if the read must be continued (TWSI Bus still allocated) */ int SkLm80ReadSensor( SK_AC *pAC, /* Adapter Context */ @@ -206,15 +133,15 @@ SK_SENSOR *pSen) /* Sensor to be read */ switch (pSen->SenState) { case SK_SEN_IDLE: /* Send address to ADDR register */ - SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, pSen->SenReg, 0); + SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, I2C_025K_DEV, pSen->SenReg, 0); pSen->SenState = SK_SEN_VALUE ; BREAK_OR_WAIT(pAC, IoC, I2C_READ); - + case SK_SEN_VALUE: /* Read value from data register */ SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value)); - + Value &= 0xff; /* only least significant byte is valid */ /* Do NOT check the Value against the thresholds */ @@ -254,11 +181,11 @@ SK_SENSOR *pSen) /* Sensor to be read */ (pSen->SenValue % SK_LM80_TEMP_LSB); /* Send address to ADDR register */ - SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, LM80_TEMP_CTRL, 0); + SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, I2C_025K_DEV, LM80_TEMP_CTRL, 0); pSen->SenState = SK_SEN_VALEXT ; BREAK_OR_WAIT(pAC, IoC, I2C_READ); - + case SK_SEN_VALEXT: /* Read value from data register */ SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value)); @@ -279,7 +206,7 @@ SK_SENSOR *pSen) /* Sensor to be read */ pSen->SenState = SK_SEN_IDLE ; return(1); - + default: SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E007, SKERR_I2C_E007MSG); return(1); @@ -289,4 +216,4 @@ SK_SENSOR *pSen) /* Sensor to be read */ return(0); } -#endif /* CONFIG_SK98 */ +#endif diff --git a/drivers/sk98lin/skproc.c b/drivers/sk98lin/skproc.c index 4e34073..af03e0c 100644 --- a/drivers/sk98lin/skproc.c +++ b/drivers/sk98lin/skproc.c @@ -1,139 +1,104 @@ /****************************************************************************** * - * Name: skproc.c + * Name: skproc.c * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.4 $ - * Date: $Date: 2003/02/25 14:16:37 $ - * Purpose: Funktions to display statictic data + * Version: $Revision: 1.14.2.4 $ + * Date: $Date: 2005/05/23 13:47:33 $ + * Purpose: Functions to display statictic data * ******************************************************************************/ - + /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2005 Marvell. + * + * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet + * Server Adapters. + * + * Author: Ralph Roesler (rroesler@syskonnect.de) + * Mirko Lindner (mlindner@syskonnect.de) + * + * Address all question to: linux@syskonnect.de * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * - * Created 22-Nov-2000 - * Author: Mirko Lindner (mlindner@syskonnect.de) - * * The information in this file is provided "AS IS" without warranty. * - ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: skproc.c,v $ - * Revision 1.4 2003/02/25 14:16:37 mlindner - * Fix: Copyright statement - * - * Revision 1.3 2002/10/02 12:59:51 mlindner - * Add: Support for Yukon - * Add: Speed check and setup - * Add: Merge source for kernel 2.2.x and 2.4.x - * Add: Read sensor names directly from VPD - * Fix: Volt values - * - * Revision 1.2.2.7 2002/01/14 12:45:15 mlindner - * Fix: Editorial changes - * - * Revision 1.2.2.6 2001/12/06 15:26:07 mlindner - * Fix: Return value of proc_read - * - * Revision 1.2.2.5 2001/12/06 09:57:39 mlindner - * New ProcFs entries - * - * Revision 1.2.2.4 2001/09/05 12:16:02 mlindner - * Add: New ProcFs entries - * Fix: Counter Errors (Jumbo == to long errors) - * Fix: Kernel error compilation - * Fix: too short counters - * - * Revision 1.2.2.3 2001/06/25 07:26:26 mlindner - * Add: More error messages - * - * Revision 1.2.2.2 2001/03/15 12:50:13 mlindner - * fix: ProcFS owner protection - * - * Revision 1.2.2.1 2001/03/12 16:43:48 mlindner - * chg: 2.4 requirements for procfs - * - * Revision 1.1 2001/01/22 14:15:31 mlindner - * added ProcFs functionality - * Dual Net functionality integrated - * Rlmt networks added - * - * - ******************************************************************************/ - + *****************************************************************************/ #include - + #ifdef CONFIG_SK98 +#if 0 /* uboot */ #include +#endif #include "h/skdrv1st.h" #include "h/skdrv2nd.h" -#define ZEROPAD 1 /* pad with zero */ -#define SIGN 2 /* unsigned/signed long */ -#define PLUS 4 /* show plus */ -#define SPACE 8 /* space if plus */ -#define LEFT 16 /* left justified */ -#define SPECIALX 32 /* 0x */ -#define LARGE 64 +#include "h/skversion.h" -extern SK_AC *pACList; -extern struct net_device *SkGeRootDev; +extern struct SK_NET_DEVICE *SkGeRootDev; -extern char * SkNumber( - char * str, - long long num, - int base, - int size, - int precision, - int type); +/****************************************************************************** + * + * Local Function Prototypes and Local Variables + * + *****************************************************************************/ +static int sk_proc_print(void *writePtr, char *format, ...); +static void sk_gen_browse(void *buffer); +static int len; + +static int sk_seq_show(struct seq_file *seq, void *v); +static int sk_proc_open(struct inode *inode, struct file *file); +struct file_operations sk_proc_fops = { + .owner = THIS_MODULE, + .open = sk_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; +struct net_device *currDev = NULL; /***************************************************************************** * - * proc_read - print "summaries" entry + * sk_gen_browse -generic print "summaries" entry * * Description: - * This function fills the proc entry with statistic data about - * the ethernet device. - * - * - * Returns: buffer with statistic data - * + * This function fills the proc entry with statistic data about + * the ethernet device. + * + * Returns: N/A + * */ -int proc_read(char *buffer, -char **buffer_location, -off_t offset, -int buffer_length, -int *eof, -void *data) +static void sk_gen_browse( +void *buffer) /* buffer where the statistics will be stored in */ { - int len = 0; - int t; - int i; - DEV_NET *pNet; - SK_AC *pAC; - char test_buf[100]; - char sens_msg[50]; - unsigned long Flags; - unsigned int Size; - struct SK_NET_DEVICE *next; - struct SK_NET_DEVICE *SkgeProcDev = SkGeRootDev; - + struct SK_NET_DEVICE *SkgeProcDev = SkGeRootDev; + struct SK_NET_DEVICE *next; + SK_BOOL DisableStatistic = 0; SK_PNMI_STRUCT_DATA *pPnmiStruct; SK_PNMI_STAT *pPnmiStat; - struct proc_dir_entry *file = (struct proc_dir_entry*) data; + unsigned long Flags; + unsigned int Size; + DEV_NET *pNet; + SK_AC *pAC; + char sens_msg[50]; + int card_type; + int MaxSecurityCount = 0; + int t; + int i; while (SkgeProcDev) { + MaxSecurityCount++; + if (MaxSecurityCount > 100) { + printk("Max limit for sk_proc_read security counter!\n"); + return; + } pNet = (DEV_NET*) SkgeProcDev->priv; pAC = pNet->pAC; next = pAC->Next; @@ -146,370 +111,373 @@ void *data) spin_lock_irqsave(&pAC->SlowPathLock, Flags); Size = SK_PNMI_STRUCT_SIZE; - SkPnmiGetStruct(pAC, pAC->IoBase, - pPnmiStruct, &Size, t-1); + DisableStatistic = 0; + if (pAC->BoardLevel == SK_INIT_DATA) { + SK_MEMCPY(&(pAC->PnmiStruct), &(pAC->PnmiBackup), sizeof(SK_PNMI_STRUCT_DATA)); + if (pAC->DiagModeActive == DIAG_NOTACTIVE) { + pAC->Pnmi.DiagAttached = SK_DIAG_IDLE; + } + } else { + SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, t-1); + } spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + if (strcmp(pAC->dev[t-1]->name, currDev->name) == 0) { + if (!pAC->GIni.GIYukon32Bit) + card_type = 64; + else + card_type = 32; - if (strcmp(pAC->dev[t-1]->name, file->name) == 0) { pPnmiStat = &pPnmiStruct->Stat[0]; - len = sprintf(buffer, + len = sk_proc_print(buffer, "\nDetailed statistic for device %s\n", pAC->dev[t-1]->name); - len += sprintf(buffer + len, + len += sk_proc_print(buffer, "=======================================\n"); - + /* Board statistics */ - len += sprintf(buffer + len, + len += sk_proc_print(buffer, "\nBoard statistics\n\n"); - len += sprintf(buffer + len, + len += sk_proc_print(buffer, + "Card name %s\n", + pAC->DeviceStr); + len += sk_proc_print(buffer, + "Vendor/Device ID %x/%x\n", + pAC->PciDev->vendor, + pAC->PciDev->device); + len += sk_proc_print(buffer, + "Card type (Bit) %d\n", + card_type); + + len += sk_proc_print(buffer, "Active Port %c\n", 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt. Net[t-1].PrefPort]->PortNumber); - len += sprintf(buffer + len, + len += sk_proc_print(buffer, "Preferred Port %c\n", 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt. Net[t-1].PrefPort]->PortNumber); - len += sprintf(buffer + len, - "Bus speed (MHz) %d\n", - pPnmiStruct->BusSpeed); + if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) { + len += sk_proc_print(buffer, + "Interrupt Moderation static (%d ints/sec)\n", + pAC->DynIrqModInfo.MaxModIntsPerSec); + } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) { + len += sk_proc_print(buffer, + "Interrupt Moderation dynamic (%d ints/sec)\n", + pAC->DynIrqModInfo.MaxModIntsPerSec); + } else { + len += sk_proc_print(buffer, + "Interrupt Moderation disabled\n"); + } - len += sprintf(buffer + len, - "Bus width (Bit) %d\n", - pPnmiStruct->BusWidth); - len += sprintf(buffer + len, + if (pAC->GIni.GIPciBus == SK_PEX_BUS) { + len += sk_proc_print(buffer, + "Bus type PCI-Express\n"); + len += sk_proc_print(buffer, + "Bus width (Lanes) %d\n", + pAC->GIni.GIPexWidth); + } else { + if (pAC->GIni.GIPciBus == SK_PCIX_BUS) { + len += sk_proc_print(buffer, + "Bus type PCI-X\n"); + if (pAC->GIni.GIPciMode == PCI_OS_SPD_X133) { + len += sk_proc_print(buffer, + "Bus speed (MHz) 133\n"); + } else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X100) { + len += sk_proc_print(buffer, + "Bus speed (MHz) 100\n"); + } else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X66) { + len += sk_proc_print(buffer, + "Bus speed (MHz) 66\n"); + } else { + len += sk_proc_print(buffer, + "Bus speed (MHz) 33\n"); + } + } else { + len += sk_proc_print(buffer, + "Bus type PCI\n"); + len += sk_proc_print(buffer, + "Bus speed (MHz) %d\n", + pPnmiStruct->BusSpeed); + } + len += sk_proc_print(buffer, + "Bus width (Bit) %d\n", + pPnmiStruct->BusWidth); + } + + len += sk_proc_print(buffer, + "Driver version %s (%s)\n", + VER_STRING, PATCHLEVEL); + len += sk_proc_print(buffer, + "Driver release date %s\n", + pAC->Pnmi.pDriverReleaseDate); + len += sk_proc_print(buffer, "Hardware revision v%d.%d\n", (pAC->GIni.GIPciHwRev >> 4) & 0x0F, pAC->GIni.GIPciHwRev & 0x0F); + if (!netif_running(pAC->dev[t-1])) { + len += sk_proc_print(buffer, + "\n Device %s is down.\n" + " Therefore no statistics are available.\n" + " After bringing the device up (ifconfig)" + " statistics will\n" + " be displayed.\n", + pAC->dev[t-1]->name); + DisableStatistic = 1; + } + + /* Display only if statistic info available */ /* Print sensor informations */ - for (i=0; i < pAC->I2c.MaxSens; i ++) { - /* Check type */ - switch (pAC->I2c.SenTable[i].SenType) { - case 1: - strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); - strcat(sens_msg, " (C)"); - len += sprintf(buffer + len, - "%-25s %d.%02d\n", - sens_msg, - pAC->I2c.SenTable[i].SenValue / 10, - pAC->I2c.SenTable[i].SenValue % 10); + if (!DisableStatistic) { + for (i=0; i < pAC->I2c.MaxSens; i ++) { + /* Check type */ + switch (pAC->I2c.SenTable[i].SenType) { + case 1: + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (C)"); + len += sk_proc_print(buffer, + "%-25s %d.%02d\n", + sens_msg, + pAC->I2c.SenTable[i].SenValue / 10, + pAC->I2c.SenTable[i].SenValue % + 10); - strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); - strcat(sens_msg, " (F)"); - len += sprintf(buffer + len, - "%-25s %d.%02d\n", - sens_msg, - ((((pAC->I2c.SenTable[i].SenValue) - *10)*9)/5 + 3200)/100, - ((((pAC->I2c.SenTable[i].SenValue) - *10)*9)/5 + 3200) % 10); - break; - case 2: - strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); - strcat(sens_msg, " (V)"); - len += sprintf(buffer + len, - "%-25s %d.%03d\n", - sens_msg, - pAC->I2c.SenTable[i].SenValue / 1000, - pAC->I2c.SenTable[i].SenValue % 1000); - break; - case 3: - strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); - strcat(sens_msg, " (rpm)"); - len += sprintf(buffer + len, - "%-25s %d\n", - sens_msg, - pAC->I2c.SenTable[i].SenValue); - break; - default: - break; + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (F)"); + len += sk_proc_print(buffer, + "%-25s %d.%02d\n", + sens_msg, + ((((pAC->I2c.SenTable[i].SenValue) + *10)*9)/5 + 3200)/100, + ((((pAC->I2c.SenTable[i].SenValue) + *10)*9)/5 + 3200) % 10); + break; + case 2: + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (V)"); + len += sk_proc_print(buffer, + "%-25s %d.%03d\n", + sens_msg, + pAC->I2c.SenTable[i].SenValue / 1000, + pAC->I2c.SenTable[i].SenValue % 1000); + break; + case 3: + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (rpm)"); + len += sk_proc_print(buffer, + "%-25s %d\n", + sens_msg, + pAC->I2c.SenTable[i].SenValue); + break; + default: + break; + } } - } + + /*Receive statistics */ + len += sk_proc_print(buffer, + "\nReceive statistics\n\n"); - /*Receive statistics */ - len += sprintf(buffer + len, - "\nReceive statistics\n\n"); - - len += sprintf(buffer + len, - "Received bytes %s\n", - SkNumber(test_buf, pPnmiStat->StatRxOctetsOkCts, - 10,0,-1,0)); - len += sprintf(buffer + len, - "Received packets %s\n", - SkNumber(test_buf, pPnmiStat->StatRxOkCts, - 10,0,-1,0)); + len += sk_proc_print(buffer, + "Received bytes %Lu\n", + (unsigned long long) pPnmiStat->StatRxOctetsOkCts); + len += sk_proc_print(buffer, + "Received packets %Lu\n", + (unsigned long long) pPnmiStat->StatRxOkCts); #if 0 - if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && - pAC->HWRevision < 12) { - pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts - - pPnmiStat->StatRxShortsCts; - pPnmiStat->StatRxShortsCts = 0; - } + if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && + pAC->HWRevision < 12) { + pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts - + pPnmiStat->StatRxShortsCts; + pPnmiStat->StatRxShortsCts = 0; + } #endif - if (pNet->Mtu > 1500) - pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts - - pPnmiStat->StatRxTooLongCts; + if (pAC->dev[t-1]->mtu > 1500) + pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts - + pPnmiStat->StatRxTooLongCts; - len += sprintf(buffer + len, - "Receive errors %s\n", - SkNumber(test_buf, pPnmiStruct->InErrorsCts, - 10,0,-1,0)); - len += sprintf(buffer + len, - "Receive drops %s\n", - SkNumber(test_buf, pPnmiStruct->RxNoBufCts, - 10,0,-1,0)); - len += sprintf(buffer + len, - "Received multicast %s\n", - SkNumber(test_buf, pPnmiStat->StatRxMulticastOkCts, - 10,0,-1,0)); - len += sprintf(buffer + len, - "Receive error types\n"); - len += sprintf(buffer + len, - " length %s\n", - SkNumber(test_buf, pPnmiStat->StatRxRuntCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " buffer overflow %s\n", - SkNumber(test_buf, pPnmiStat->StatRxFifoOverflowCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " bad crc %s\n", - SkNumber(test_buf, pPnmiStat->StatRxFcsCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " framing %s\n", - SkNumber(test_buf, pPnmiStat->StatRxFramingCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " missed frames %s\n", - SkNumber(test_buf, pPnmiStat->StatRxMissedCts, - 10, 0, -1, 0)); + len += sk_proc_print(buffer, + "Receive errors %Lu\n", + (unsigned long long) pPnmiStruct->InErrorsCts); + len += sk_proc_print(buffer, + "Receive dropped %Lu\n", + (unsigned long long) pPnmiStruct->RxNoBufCts); + len += sk_proc_print(buffer, + "Received multicast %Lu\n", + (unsigned long long) pPnmiStat->StatRxMulticastOkCts); +#ifdef ADVANCED_STATISTIC_OUTPUT + len += sk_proc_print(buffer, + "Receive error types\n"); + len += sk_proc_print(buffer, + " length %Lu\n", + (unsigned long long) pPnmiStat->StatRxRuntCts); + len += sk_proc_print(buffer, + " buffer overflow %Lu\n", + (unsigned long long) pPnmiStat->StatRxFifoOverflowCts); + len += sk_proc_print(buffer, + " bad crc %Lu\n", + (unsigned long long) pPnmiStat->StatRxFcsCts); + len += sk_proc_print(buffer, + " framing %Lu\n", + (unsigned long long) pPnmiStat->StatRxFramingCts); + len += sk_proc_print(buffer, + " missed frames %Lu\n", + (unsigned long long) pPnmiStat->StatRxMissedCts); - if (pNet->Mtu > 1500) - pPnmiStat->StatRxTooLongCts = 0; + if (pAC->dev[t-1]->mtu > 1500) + pPnmiStat->StatRxTooLongCts = 0; - len += sprintf(buffer + len, - " too long %s\n", - SkNumber(test_buf, pPnmiStat->StatRxTooLongCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " carrier extension %s\n", - SkNumber(test_buf, pPnmiStat->StatRxCextCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " too short %s\n", - SkNumber(test_buf, pPnmiStat->StatRxShortsCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " symbol %s\n", - SkNumber(test_buf, pPnmiStat->StatRxSymbolCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " LLC MAC size %s\n", - SkNumber(test_buf, pPnmiStat->StatRxIRLengthCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " carrier event %s\n", - SkNumber(test_buf, pPnmiStat->StatRxCarrierCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " jabber %s\n", - SkNumber(test_buf, pPnmiStat->StatRxJabberCts, - 10, 0, -1, 0)); + len += sk_proc_print(buffer, + " too long %Lu\n", + (unsigned long long) pPnmiStat->StatRxTooLongCts); + len += sk_proc_print(buffer, + " carrier extension %Lu\n", + (unsigned long long) pPnmiStat->StatRxCextCts); + len += sk_proc_print(buffer, + " too short %Lu\n", + (unsigned long long) pPnmiStat->StatRxShortsCts); + len += sk_proc_print(buffer, + " symbol %Lu\n", + (unsigned long long) pPnmiStat->StatRxSymbolCts); + len += sk_proc_print(buffer, + " LLC MAC size %Lu\n", + (unsigned long long) pPnmiStat->StatRxIRLengthCts); + len += sk_proc_print(buffer, + " carrier event %Lu\n", + (unsigned long long) pPnmiStat->StatRxCarrierCts); + len += sk_proc_print(buffer, + " jabber %Lu\n", + (unsigned long long) pPnmiStat->StatRxJabberCts); +#endif - - /*Transmit statistics */ - len += sprintf(buffer + len, - "\nTransmit statistics\n\n"); - - len += sprintf(buffer + len, - "Transmited bytes %s\n", - SkNumber(test_buf, pPnmiStat->StatTxOctetsOkCts, - 10,0,-1,0)); - len += sprintf(buffer + len, - "Transmited packets %s\n", - SkNumber(test_buf, pPnmiStat->StatTxOkCts, - 10,0,-1,0)); - len += sprintf(buffer + len, - "Transmit errors %s\n", - SkNumber(test_buf, pPnmiStat->StatTxSingleCollisionCts, - 10,0,-1,0)); - len += sprintf(buffer + len, - "Transmit dropped %s\n", - SkNumber(test_buf, pPnmiStruct->TxNoBufCts, - 10,0,-1,0)); - len += sprintf(buffer + len, - "Transmit collisions %s\n", - SkNumber(test_buf, pPnmiStat->StatTxSingleCollisionCts, - 10,0,-1,0)); - len += sprintf(buffer + len, - "Transmit errors types\n"); - len += sprintf(buffer + len, - " excessive collision %ld\n", - pAC->stats.tx_aborted_errors); - len += sprintf(buffer + len, - " carrier %s\n", - SkNumber(test_buf, pPnmiStat->StatTxCarrierCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " fifo underrun %s\n", - SkNumber(test_buf, pPnmiStat->StatTxFifoUnderrunCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " heartbeat %s\n", - SkNumber(test_buf, pPnmiStat->StatTxCarrierCts, - 10, 0, -1, 0)); - len += sprintf(buffer + len, - " window %ld\n", - pAC->stats.tx_window_errors); - - } + /*Transmit statistics */ + len += sk_proc_print(buffer, + "\nTransmit statistics\n\n"); + + len += sk_proc_print(buffer, + "Transmitted bytes %Lu\n", + (unsigned long long) pPnmiStat->StatTxOctetsOkCts); + len += sk_proc_print(buffer, + "Transmitted packets %Lu\n", + (unsigned long long) pPnmiStat->StatTxOkCts); + len += sk_proc_print(buffer, + "Transmit errors %Lu\n", + (unsigned long long) pPnmiStat->StatTxSingleCollisionCts); + len += sk_proc_print(buffer, + "Transmit dropped %Lu\n", + (unsigned long long) pPnmiStruct->TxNoBufCts); + len += sk_proc_print(buffer, + "Transmit collisions %Lu\n", + (unsigned long long) pPnmiStat->StatTxSingleCollisionCts); +#ifdef ADVANCED_STATISTIC_OUTPUT + len += sk_proc_print(buffer, + "Transmit error types\n"); + len += sk_proc_print(buffer, + " excessive collision %ld\n", + pAC->stats.tx_aborted_errors); + len += sk_proc_print(buffer, + " carrier %Lu\n", + (unsigned long long) pPnmiStat->StatTxCarrierCts); + len += sk_proc_print(buffer, + " fifo underrun %Lu\n", + (unsigned long long) pPnmiStat->StatTxFifoUnderrunCts); + len += sk_proc_print(buffer, + " heartbeat %Lu\n", + (unsigned long long) pPnmiStat->StatTxCarrierCts); + len += sk_proc_print(buffer, + " window %ld\n", + pAC->stats.tx_window_errors); +#endif + } /* if (!DisableStatistic) */ + + } /* if (strcmp(pACname, currDeviceName) == 0) */ } SkgeProcDev = next; } - if (offset >= len) { - *eof = 1; - return 0; - } - - *buffer_location = buffer + offset; - if (buffer_length >= len - offset) { - *eof = 1; - } - return (min_t(int, buffer_length, len - offset)); } - /***************************************************************************** * - * SkDoDiv - convert 64bit number + * sk_proc_print - generic line print * * Description: - * This function "converts" a long long number. - * + * This function fills the proc entry with statistic data about the + * ethernet device. + * * Returns: - * remainder of division - */ -static long SkDoDiv (long long Dividend, int Divisor, long long *pErg) -{ - long Rest; - long long Ergebnis; - long Akku; + * the number of bytes written + * + */ +static int sk_proc_print( +void *writePtr, /* the buffer pointer */ +char *format, /* the format of the string */ +...) /* variable list of arguments */ +{ +#define MAX_LEN_SINGLE_LINE 256 + char str[MAX_LEN_SINGLE_LINE]; + va_list a_start; + int lenght = 0; + struct seq_file *seq = (struct seq_file *) writePtr; - Akku = Dividend >> 32; + SK_MEMSET(str, 0, MAX_LEN_SINGLE_LINE); - Ergebnis = ((long long) (Akku / Divisor)) << 32; - Rest = Akku % Divisor ; + va_start(a_start, format); + vsprintf(str, format, a_start); + va_end(a_start); - Akku = Rest << 16; - Akku |= ((Dividend & 0xFFFF0000) >> 16); + lenght = strlen(str); - - Ergebnis += ((long long) (Akku / Divisor)) << 16; - Rest = Akku % Divisor ; - - Akku = Rest << 16; - Akku |= (Dividend & 0xFFFF); - - Ergebnis += (Akku / Divisor); - Rest = Akku % Divisor ; - - *pErg = Ergebnis; - return (Rest); + seq_printf(seq, str); + return lenght; } +/***************************************************************************** + * + * sk_seq_show - show proc information of a particular adapter + * + * Description: + * This function fills the proc entry with statistic data about the + * ethernet device. It invokes the generic sk_gen_browse() to print + * out all items one per one. + * + * Returns: + * the number of bytes written + * + */ +static int sk_seq_show( +struct seq_file *seq, /* the sequence pointer */ +void *v) /* additional pointer */ +{ + void *castedBuffer = (void *) seq; + currDev = seq->private; + sk_gen_browse(castedBuffer); + return 0; +} -#if 0 -#define do_div(n,base) ({ \ -long long __res; \ -__res = ((unsigned long long) n) % (unsigned) base; \ -n = ((unsigned long long) n) / (unsigned) base; \ -__res; }) +/***************************************************************************** + * + * sk_proc_open - register the show function when proc is open'ed + * + * Description: + * This function is called whenever a sk98lin proc file is queried. + * + * Returns: + * the return value of single_open() + * + */ +static int sk_proc_open( +struct inode *inode, /* the inode of the file */ +struct file *file) /* the file pointer itself */ +{ + return single_open(file, sk_seq_show, PDE(inode)->data); +} + +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ #endif - - -/***************************************************************************** - * - * SkNumber - Print results - * - * Description: - * This function converts a long long number into a string. - * - * Returns: - * number as string - */ -char * SkNumber(char * str, long long num, int base, int size, int precision - ,int type) -{ - char c,sign,tmp[66], *strorg = str; - const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; - int i; - - if (type & LARGE) - digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; - if (type & LEFT) - type &= ~ZEROPAD; - if (base < 2 || base > 36) - return 0; - c = (type & ZEROPAD) ? '0' : ' '; - sign = 0; - if (type & SIGN) { - if (num < 0) { - sign = '-'; - num = -num; - size--; - } else if (type & PLUS) { - sign = '+'; - size--; - } else if (type & SPACE) { - sign = ' '; - size--; - } - } - if (type & SPECIALX) { - if (base == 16) - size -= 2; - else if (base == 8) - size--; - } - i = 0; - if (num == 0) - tmp[i++]='0'; - else while (num != 0) - tmp[i++] = digits[SkDoDiv(num,base, &num)]; - - if (i > precision) - precision = i; - size -= precision; - if (!(type&(ZEROPAD+LEFT))) - while(size-->0) - *str++ = ' '; - if (sign) - *str++ = sign; - if (type & SPECIALX) { - if (base==8) - *str++ = '0'; - else if (base==16) { - *str++ = '0'; - *str++ = digits[33]; - } - } - if (!(type & LEFT)) - while (size-- > 0) - *str++ = c; - while (i < precision--) - *str++ = '0'; - while (i-- > 0) - *str++ = tmp[i]; - while (size-- > 0) - *str++ = ' '; - - str[0] = '\0'; - - return strorg; -} - -#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skqueue.c b/drivers/sk98lin/skqueue.c index c49baed..46e169e 100644 --- a/drivers/sk98lin/skqueue.c +++ b/drivers/sk98lin/skqueue.c @@ -1,17 +1,17 @@ /****************************************************************************** * * Name: skqueue.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.18 $ - * Date: $Date: 2002/05/07 14:11:11 $ + * Project: Gigabit Ethernet Adapters, Event Scheduler Module + * Version: $Revision: 2.3 $ + * Date: $Date: 2004/05/14 13:28:18 $ * Purpose: Management of an event queue. * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998,1999 SysKonnect, - * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,80 +22,17 @@ * ******************************************************************************/ -/****************************************************************************** - * - * History: - * - * $Log: skqueue.c,v $ - * Revision 1.18 2002/05/07 14:11:11 rwahl - * Fixed Watcom Precompiler error. - * - * Revision 1.17 2002/03/25 10:06:41 mkunz - * SkIgnoreEvent deleted - * - * Revision 1.16 2002/03/15 10:51:59 mkunz - * Added event classes for link aggregation - * - * Revision 1.15 1999/11/22 13:36:29 cgoos - * Changed license header to GPL. - * - * Revision 1.14 1998/10/15 15:11:35 gklug - * fix: ID_sccs to SysKonnectFileId - * - * Revision 1.13 1998/09/08 08:47:52 gklug - * add: init level handling - * - * Revision 1.12 1998/09/08 07:43:20 gklug - * fix: Sirq Event function name - * - * Revision 1.11 1998/09/08 05:54:34 gklug - * chg: define SK_CSUM is replaced by SK_USE_CSUM - * - * Revision 1.10 1998/09/03 14:14:49 gklug - * add: CSUM and HWAC Eventclass and function. - * - * Revision 1.9 1998/08/19 09:50:50 gklug - * fix: remove struct keyword from c-code (see CCC) add typedefs - * - * Revision 1.8 1998/08/17 13:43:11 gklug - * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR - * - * Revision 1.7 1998/08/14 07:09:11 gklug - * fix: chg pAc -> pAC - * - * Revision 1.6 1998/08/11 12:13:14 gklug - * add: return code feature of Event service routines - * add: correct Error log calls - * - * Revision 1.5 1998/08/07 12:53:45 gklug - * fix: first compiled version - * - * Revision 1.4 1998/08/07 09:20:48 gklug - * adapt functions to C coding conventions. - * - * Revision 1.3 1998/08/05 11:29:32 gklug - * rmv: Timer event entry. Timer will queue event directly - * - * Revision 1.2 1998/07/31 11:22:40 gklug - * Initial version - * - * Revision 1.1 1998/07/30 15:14:01 gklug - * Initial version. Adapted from SMT - * - * - * - ******************************************************************************/ - - #include - + #ifdef CONFIG_SK98 /* - Event queue and dispatcher -*/ + * Event queue and dispatcher + */ +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) static const char SysKonnectFileId[] = - "$Header: /usr56/projects/ge/schedule/skqueue.c,v 1.18 2002/05/07 14:11:11 rwahl Exp $" ; + "@(#) $Id: skqueue.c,v 2.3 2004/05/14 13:28:18 malthoff Exp $ (C) Marvell."; +#endif #include "h/skdrv1st.h" /* Driver Specific Definitions */ #include "h/skqueue.h" /* Queue Definitions */ @@ -114,27 +51,42 @@ intro() #define PRINTF(a,b,c) -/* - * init event queue management +/****************************************************************************** * - * Must be called during init level 0. + * SkEventInit() - init event queue management + * + * Description: + * This function initializes event queue management. + * It must be called during init level 0. + * + * Returns: + * nothing */ void SkEventInit( SK_AC *pAC, /* Adapter context */ SK_IOC Ioc, /* IO context */ -int Level) /* Init level */ +int Level) /* Init level */ { switch (Level) { case SK_INIT_DATA: - pAC->Event.EvPut = pAC->Event.EvGet = pAC->Event.EvQueue ; + pAC->Event.EvPut = pAC->Event.EvGet = pAC->Event.EvQueue; break; default: break; } } -/* - * add event to queue +/****************************************************************************** + * + * SkEventQueue() - add event to queue + * + * Description: + * This function adds an event to the event queue. + * At least Init Level 1 is required to queue events, + * but will be scheduled add Init Level 2. + * + * returns: + * nothing */ void SkEventQueue( SK_AC *pAC, /* Adapters context */ @@ -142,101 +94,154 @@ SK_U32 Class, /* Event Class */ SK_U32 Event, /* Event to be queued */ SK_EVPARA Para) /* Event parameter */ { - pAC->Event.EvPut->Class = Class ; - pAC->Event.EvPut->Event = Event ; - pAC->Event.EvPut->Para = Para ; - if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT]) - pAC->Event.EvPut = pAC->Event.EvQueue ; - if (pAC->Event.EvPut == pAC->Event.EvGet) { - SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG) ; + if (pAC->GIni.GILevel == SK_INIT_DATA) { + SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E003, SKERR_Q_E003MSG); + } + else { + pAC->Event.EvPut->Class = Class; + pAC->Event.EvPut->Event = Event; + pAC->Event.EvPut->Para = Para; + + if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT]) + pAC->Event.EvPut = pAC->Event.EvQueue; + + if (pAC->Event.EvPut == pAC->Event.EvGet) { + SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG); + } } } -/* - * event dispatcher - * while event queue is not empty - * get event from queue - * send command to state machine - * end - * return error reported by individual Event function - * 0 if no error occured. +/****************************************************************************** + * + * SkEventDispatcher() - Event Dispatcher + * + * Description: + * The event dispatcher performs the following operations: + * o while event queue is not empty + * - get event from queue + * - send event to state machine + * end + * + * CAUTION: + * The event functions MUST report an error if performing a reinitialization + * of the event queue, e.g. performing level Init 0..2 while in dispatcher + * call! + * ANY OTHER return value delays scheduling the other events in the + * queue. In this case the event blocks the queue until + * the error condition is cleared! + * + * Returns: + * The return value error reported by individual event function */ int SkEventDispatcher( SK_AC *pAC, /* Adapters Context */ SK_IOC Ioc) /* Io context */ { - SK_EVENTELEM *pEv ; /* pointer into queue */ - SK_U32 Class ; - int Rtv ; + SK_EVENTELEM *pEv; /* pointer into queue */ + SK_U32 Class; + int Rtv; - pEv = pAC->Event.EvGet ; - PRINTF("dispatch get %x put %x\n",pEv,pAC->Event.ev_put) ; + if (pAC->GIni.GILevel != SK_INIT_RUN) { + SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E005, SKERR_Q_E005MSG); + } + + pEv = pAC->Event.EvGet; + + PRINTF("dispatch get %x put %x\n", pEv, pAC->Event.ev_put); + while (pEv != pAC->Event.EvPut) { - PRINTF("dispatch Class %d Event %d\n",pEv->Class,pEv->Event) ; - switch(Class = pEv->Class) { + PRINTF("dispatch Class %d Event %d\n", pEv->Class, pEv->Event); + + switch (Class = pEv->Class) { #ifndef SK_USE_LAC_EV - case SKGE_RLMT : /* RLMT Event */ - Rtv = SkRlmtEvent(pAC,Ioc,pEv->Event,pEv->Para); - break ; - case SKGE_I2C : /* I2C Event */ - Rtv = SkI2cEvent(pAC,Ioc,pEv->Event,pEv->Para); - break ; - case SKGE_PNMI : - Rtv = SkPnmiEvent(pAC,Ioc,pEv->Event,pEv->Para); - break ; -#endif /* SK_USE_LAC_EV */ - case SKGE_DRV : /* Driver Event */ - Rtv = SkDrvEvent(pAC,Ioc,pEv->Event,pEv->Para); - break ; +#ifndef SK_SLIM + case SKGE_RLMT: /* RLMT Event */ + Rtv = SkRlmtEvent(pAC, Ioc, pEv->Event, pEv->Para); + break; + case SKGE_I2C: /* I2C Event */ + Rtv = SkI2cEvent(pAC, Ioc, pEv->Event, pEv->Para); + break; + +#ifdef SK_PNMI_SUPPORT + case SKGE_PNMI: /* PNMI Event */ + Rtv = SkPnmiEvent(pAC, Ioc, pEv->Event, pEv->Para); + break; +#endif /* SK_PNMI_SUPPORT */ + +#endif /* not SK_SLIM */ +#endif /* not SK_USE_LAC_EV */ + case SKGE_DRV: /* Driver Event */ + Rtv = SkDrvEvent(pAC, Ioc, pEv->Event, pEv->Para); + break; #ifndef SK_USE_SW_TIMER - case SKGE_HWAC : - Rtv = SkGeSirqEvent(pAC,Ioc,pEv->Event,pEv->Para); - break ; + case SKGE_HWAC: + Rtv = SkGeSirqEvent(pAC, Ioc, pEv->Event, pEv->Para); + break; #else /* !SK_USE_SW_TIMER */ - case SKGE_SWT : - Rtv = SkSwtEvent(pAC,Ioc,pEv->Event,pEv->Para); - break ; + case SKGE_SWT : + Rtv = SkSwtEvent(pAC, Ioc, pEv->Event, pEv->Para); + break; #endif /* !SK_USE_SW_TIMER */ #ifdef SK_USE_LAC_EV case SKGE_LACP : - Rtv = SkLacpEvent(pAC,Ioc,pEv->Event,pEv->Para); - break ; + Rtv = SkLacpEvent(pAC, Ioc, pEv->Event, pEv->Para); + break; case SKGE_RSF : - Rtv = SkRsfEvent(pAC,Ioc,pEv->Event,pEv->Para); - break ; + Rtv = SkRsfEvent(pAC, Ioc, pEv->Event, pEv->Para); + break; case SKGE_MARKER : - Rtv = SkMarkerEvent(pAC,Ioc,pEv->Event,pEv->Para); - break ; + Rtv = SkMarkerEvent(pAC, Ioc, pEv->Event, pEv->Para); + break; case SKGE_FD : - Rtv = SkFdEvent(pAC,Ioc,pEv->Event,pEv->Para); - break ; + Rtv = SkFdEvent(pAC, Ioc, pEv->Event, pEv->Para); + break; #endif /* SK_USE_LAC_EV */ +#ifdef SK_ASF + case SKGE_ASF : + Rtv = SkAsfEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#endif #ifdef SK_USE_CSUM case SKGE_CSUM : - Rtv = SkCsEvent(pAC,Ioc,pEv->Event,pEv->Para); - break ; + Rtv = SkCsEvent(pAC, Ioc, pEv->Event, pEv->Para); + break; #endif /* SK_USE_CSUM */ default : - SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E002, - SKERR_Q_E002MSG) ; + #if 0 // u-boot + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E002, SKERR_Q_E002MSG); + #endif Rtv = 0; } if (Rtv != 0) { - return(Rtv) ; + /* + * Special Case: See CAUTION statement above. + * We assume the event queue is reset. + */ + if (pAC->Event.EvGet != pAC->Event.EvQueue && + pAC->Event.EvGet != pEv) { + /* + * Create an error log entry if the + * event queue isn't reset. + * In this case it may be blocked. + */ + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E004, SKERR_Q_E004MSG); + } + + return(Rtv); } if (++pEv == &pAC->Event.EvQueue[SK_MAX_EVENT]) - pEv = pAC->Event.EvQueue ; + pEv = pAC->Event.EvQueue; /* Renew get: it is used in queue_events to detect overruns */ pAC->Event.EvGet = pEv; } - return(0) ; + return(0); } -#endif /* CONFIG_SK98 */ - /* End of file */ + +#endif diff --git a/drivers/sk98lin/skrlmt.c b/drivers/sk98lin/skrlmt.c index f8a3b41..11753c1 100644 --- a/drivers/sk98lin/skrlmt.c +++ b/drivers/sk98lin/skrlmt.c @@ -2,15 +2,17 @@ * * Name: skrlmt.c * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.68 $ - * Date: $Date: 2003/01/31 15:26:56 $ + * Version: $Revision: 2.4 $ + * Date: $Date: 2005/12/14 16:11:10 $ * Purpose: Manage links on SK-NET Adapters, esp. redundant ones. * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2001 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,250 +20,7 @@ * (at your option) any later version. * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: skrlmt.c,v $ - * Revision 1.68 2003/01/31 15:26:56 rschmidt - * Added init for local variables in RlmtInit(). - * - * Revision 1.67 2003/01/31 14:12:41 mkunz - * single port adapter runs now with two identical MAC addresses - * - * Revision 1.66 2002/09/23 15:14:19 rwahl - * - Reset broadcast timestamp on link down. - * - Editorial corrections. - * - * Revision 1.65 2002/07/22 14:29:48 rwahl - * - Removed BRK statement from debug check. - * - * Revision 1.64 2001/11/28 19:36:14 rwahl - * - RLMT Packets sent to an invalid MAC address in CLP/CLPSS mode - * (#10650). - * - Reworked fix for port switching in CLS mode (#10639) - * (no dependency to RLMT module). - * - Enabled dbg output for entry/exit of event functions. - * - Editorial changes. - * - * Revision 1.63 2001/10/26 07:53:18 afischer - * Port switching bug in `check local link` mode - * - * Revision 1.62 2001/07/03 12:16:30 mkunz - * New Flag ChgBcPrio (Change priority of last broadcast received) - * - * Revision 1.61 2001/03/14 12:52:08 rassmann - * Fixed reporting of active port up/down to PNMI. - * - * Revision 1.60 2001/02/21 16:02:25 gklug - * fix: when RLMT starts set Active Port for PNMI - * - * Revision 1.59 2001/02/16 14:38:19 rassmann - * Initializing some pointers earlier in the init phase. - * Rx Mbufs are freed if the net which they belong to is stopped. - * - * Revision 1.58 2001/02/14 14:06:31 rassmann - * Editorial changes. - * - * Revision 1.57 2001/02/05 14:25:26 rassmann - * Prepared RLMT for transparent operation. - * - * Revision 1.56 2001/01/30 10:29:09 rassmann - * Not checking switching befor RlmtStart. - * Editorial changes. - * - * Revision 1.55 2001/01/22 13:41:38 rassmann - * Supporting two nets on dual-port adapters. - * - * Revision 1.54 2000/11/30 13:25:07 rassmann - * Setting SK_TICK_INCR to 1 by default. - * - * Revision 1.53 2000/11/30 10:48:07 cgoos - * Changed definition of SK_RLMT_BC_DELTA. - * - * Revision 1.52 2000/11/27 12:50:03 rassmann - * Checking ports after receiving broadcasts. - * - * Revision 1.51 2000/11/17 08:58:00 rassmann - * Moved CheckSwitch from SK_RLMT_PACKET_RECEIVED to SK_RLMT_TIM event. - * - * Revision 1.50 2000/11/09 12:24:34 rassmann - * Indicating that segmentation check is not running anymore after - * SkRlmtCheckSeg(). - * Restarting segmentation timer after segmentation log. - * Editorial changes. - * - * Revision 1.49 1999/11/22 13:38:02 cgoos - * Changed license header to GPL. - * Added initialization to some variables to avoid compiler warnings. - * - * Revision 1.48 1999/10/04 14:01:17 rassmann - * Corrected reaction to reception of BPDU frames (#10441). - * - * Revision 1.47 1999/07/20 12:53:36 rassmann - * Fixed documentation errors for lookahead macros. - * - * Revision 1.46 1999/05/28 13:29:16 rassmann - * Replaced C++-style comment. - * - * Revision 1.45 1999/05/28 13:28:08 rassmann - * Corrected syntax error (xxx). - * - * Revision 1.44 1999/05/28 11:15:54 rassmann - * Changed behaviour to reflect Design Spec v1.2. - * Controlling Link LED(s). - * Introduced RLMT Packet Version field in RLMT Packet. - * Newstyle lookahead macros (checking meta-information before looking at - * the packet). - * - * Revision 1.43 1999/01/28 13:12:43 rassmann - * Corrected Lookahead (bug introduced in previous Rev.). - * - * Revision 1.42 1999/01/28 12:50:41 rassmann - * Not using broadcast time stamps in CheckLinkState mode. - * - * Revision 1.41 1999/01/27 14:13:02 rassmann - * Monitoring broadcast traffic. - * Switching more reliably and not too early if switch is - * configured for spanning tree. - * - * Revision 1.40 1999/01/22 13:17:30 rassmann - * Informing PNMI of NET_UP. - * Clearing RLMT multicast addresses before setting them for the first time. - * Reporting segmentation earlier, setting a "quiet time" - * after a report. - * - * Revision 1.39 1998/12/10 15:29:53 rassmann - * Corrected SuspectStatus in SkRlmtBuildCheckChain(). - * Corrected CHECK_SEG mode. - * - * Revision 1.38 1998/12/08 13:11:23 rassmann - * Stopping SegTimer at RlmtStop. - * - * Revision 1.37 1998/12/07 16:51:42 rassmann - * Corrected comments. - * - * Revision 1.36 1998/12/04 10:58:56 rassmann - * Setting next pointer to NULL when receiving. - * - * Revision 1.35 1998/12/03 16:12:42 rassmann - * Ignoring/correcting illegal PrefPort values. - * - * Revision 1.34 1998/12/01 11:45:35 rassmann - * Code cleanup. - * - * Revision 1.33 1998/12/01 10:29:32 rassmann - * Starting standby ports before getting the net up. - * Checking if a port is started when the link comes up. - * - * Revision 1.32 1998/11/30 16:19:50 rassmann - * New default for PortNoRx. - * - * Revision 1.31 1998/11/27 19:17:13 rassmann - * Corrected handling of LINK_DOWN coming shortly after LINK_UP. - * - * Revision 1.30 1998/11/24 12:37:31 rassmann - * Implemented segmentation check. - * - * Revision 1.29 1998/11/18 13:04:32 rassmann - * Secured PortUpTimer event. - * Waiting longer before starting standby port(s). - * - * Revision 1.28 1998/11/17 13:43:04 rassmann - * Handling (logical) tx failure. - * Sending packet on logical address after PORT_SWITCH. - * - * Revision 1.27 1998/11/13 17:09:50 rassmann - * Secured some events against being called in wrong state. - * - * Revision 1.26 1998/11/13 16:56:54 rassmann - * Added macro version of SkRlmtLookaheadPacket. - * - * Revision 1.25 1998/11/06 18:06:04 rassmann - * Corrected timing when RLMT checks fail. - * Clearing tx counter earlier in periodical checks. - * - * Revision 1.24 1998/11/05 10:37:27 rassmann - * Checking destination address in Lookahead. - * - * Revision 1.23 1998/11/03 13:53:49 rassmann - * RLMT should switch now (at least in mode 3). - * - * Revision 1.22 1998/10/29 14:34:49 rassmann - * Clearing SK_RLMT struct at startup. - * Initializing PortsUp during SK_RLMT_START. - * - * Revision 1.21 1998/10/28 11:30:17 rassmann - * Default mode is now SK_RLMT_CHECK_LOC_LINK. - * - * Revision 1.20 1998/10/26 16:02:03 rassmann - * Ignoring LINK_DOWN for links that are down. - * - * Revision 1.19 1998/10/22 15:54:01 rassmann - * Corrected EtherLen. - * Starting Link Check when second port comes up. - * - * Revision 1.18 1998/10/22 11:39:50 rassmann - * Corrected signed/unsigned mismatches. - * Corrected receive list handling and address recognition. - * - * Revision 1.17 1998/10/19 17:01:20 rassmann - * More detailed checking of received packets. - * - * Revision 1.16 1998/10/15 15:16:34 rassmann - * Finished Spanning Tree checking. - * Checked with lint. - * - * Revision 1.15 1998/09/24 19:16:07 rassmann - * Code cleanup. - * Introduced Timer for PORT_DOWN due to no RX. - * - * Revision 1.14 1998/09/18 20:27:14 rassmann - * Added address override. - * - * Revision 1.13 1998/09/16 11:31:48 rassmann - * Including skdrv1st.h again. :( - * - * Revision 1.12 1998/09/16 11:09:50 rassmann - * Syntax corrections. - * - * Revision 1.11 1998/09/15 12:32:03 rassmann - * Syntax correction. - * - * Revision 1.10 1998/09/15 11:28:49 rassmann - * Syntax corrections. - * - * Revision 1.9 1998/09/14 17:07:37 rassmann - * Added code for port checking via LAN. - * Changed Mbuf definition. - * - * Revision 1.8 1998/09/07 11:14:14 rassmann - * Syntax corrections. - * - * Revision 1.7 1998/09/07 09:06:07 rassmann - * Syntax corrections. - * - * Revision 1.6 1998/09/04 19:41:33 rassmann - * Syntax corrections. - * Started entering code for checking local links. - * - * Revision 1.5 1998/09/04 12:14:27 rassmann - * Interface cleanup. - * - * Revision 1.4 1998/09/02 16:55:28 rassmann - * Updated to reflect new DRV/HWAC/RLMT interface. - * - * Revision 1.3 1998/08/27 14:29:03 rassmann - * Code cleanup. - * - * Revision 1.2 1998/08/27 14:26:24 rassmann - * Updated interface. - * - * Revision 1.1 1998/08/21 08:26:49 rassmann - * First public version. + * /LICENSE * ******************************************************************************/ @@ -279,20 +38,18 @@ * "skdrv2nd.h" * ******************************************************************************/ - #include - + #ifdef CONFIG_SK98 #ifndef lint static const char SysKonnectFileId[] = - "@(#) $Id: skrlmt.c,v 1.68 2003/01/31 15:26:56 rschmidt Exp $ (C) SysKonnect."; + "@(#) $Id: skrlmt.c,v 2.4 2005/12/14 16:11:10 ibrueder Exp $ (C) Marvell."; #endif /* !defined(lint) */ #define __SKRLMT_C #ifdef __cplusplus -#error C++ is not yet supported. extern "C" { #endif /* cplusplus */ @@ -598,7 +355,7 @@ int Level) /* Initialization Level */ SK_BOOL PhysicalAMacAddressSet; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT, - ("RLMT Init level %d.\n", Level)) + ("RLMT Init level %d.\n", Level)); switch (Level) { case SK_INIT_DATA: /* Initialize data structures. */ @@ -638,7 +395,7 @@ int Level) /* Initialization Level */ case SK_INIT_IO: /* GIMacsFound first available here. */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT, - ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound)) + ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound)); pAC->Rlmt.Net[0].NumPorts = pAC->GIni.GIMacsFound; @@ -668,7 +425,7 @@ int Level) /* Initialization Level */ } (void)SkAddrMcClear(pAC, IoC, i, SK_ADDR_PERMANENT | SK_MC_SW_ONLY); - + /* Add RLMT MC address. */ (void)SkAddrMcAdd(pAC, IoC, i, &SkRlmtMcAddr, SK_ADDR_PERMANENT); @@ -680,34 +437,34 @@ int Level) /* Initialization Level */ (void)SkAddrMcUpdate(pAC, IoC, i); } - VirtualMacAddressSet = SK_FALSE; + VirtualMacAddressSet = SK_FALSE; /* Read virtual MAC address from Control Register File. */ for (j = 0; j < SK_MAC_ADDR_LEN; j++) { - - SK_IN8(IoC, B2_MAC_1 + j, &VirtualMacAddress.a[j]); - VirtualMacAddressSet |= VirtualMacAddress.a[j]; + + SK_IN8(IoC, B2_MAC_1 + j, &VirtualMacAddress.a[j]); + VirtualMacAddressSet |= VirtualMacAddress.a[j]; } - - PhysicalAMacAddressSet = SK_FALSE; + + PhysicalAMacAddressSet = SK_FALSE; /* Read physical MAC address for MAC A from Control Register File. */ for (j = 0; j < SK_MAC_ADDR_LEN; j++) { - - SK_IN8(IoC, B2_MAC_2 + j, &PhysicalAMacAddress.a[j]); - PhysicalAMacAddressSet |= PhysicalAMacAddress.a[j]; + + SK_IN8(IoC, B2_MAC_2 + j, &PhysicalAMacAddress.a[j]); + PhysicalAMacAddressSet |= PhysicalAMacAddress.a[j]; } - /* check if the two mac addresses contain reasonable values */ - if (!VirtualMacAddressSet || !PhysicalAMacAddressSet) { + /* check if the two mac addresses contain reasonable values */ + if (!VirtualMacAddressSet || !PhysicalAMacAddressSet) { - pAC->Rlmt.RlmtOff = SK_TRUE; - } + pAC->Rlmt.RlmtOff = SK_TRUE; + } - /* if the two mac addresses are equal switch off the RLMT_PRE_LOOKAHEAD - and the RLMT_LOOKAHEAD macros */ - else if (SK_ADDR_EQUAL(PhysicalAMacAddress.a, VirtualMacAddress.a)) { + /* if the two mac addresses are equal switch off the RLMT_PRE_LOOKAHEAD + and the RLMT_LOOKAHEAD macros */ + else if (SK_ADDR_EQUAL(PhysicalAMacAddress.a, VirtualMacAddress.a)) { - pAC->Rlmt.RlmtOff = SK_TRUE; - } + pAC->Rlmt.RlmtOff = SK_TRUE; + } else { pAC->Rlmt.RlmtOff = SK_FALSE; } @@ -751,16 +508,16 @@ SK_U32 NetIdx) /* Net Number */ FirstMacUp = NULL; PrevMacUp = NULL; - + if (!(pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_CHECK_LOC_LINK)) { for (i = 0; i < pAC->Rlmt.Net[i].NumPorts; i++) { pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked = 0; } return; /* Done. */ } - + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SkRlmtBuildCheckChain.\n")) + ("SkRlmtBuildCheckChain.\n")); NumMacsUp = 0; @@ -806,7 +563,7 @@ SK_U32 NetIdx) /* Net Number */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("Port %d checks %d other ports: %2X.\n", i, pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked, - pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5])) + pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5])); } #endif /* DEBUG */ @@ -843,7 +600,7 @@ SK_MAC_ADDR *DestAddr) /* Destination address */ #ifdef DEBUG SK_U8 CheckSrc = 0; SK_U8 CheckDest = 0; - + for (i = 0; i < SK_MAC_ADDR_LEN; ++i) { CheckSrc |= SrcAddr->a[i]; CheckDest |= DestAddr->a[i]; @@ -852,7 +609,7 @@ SK_MAC_ADDR *DestAddr) /* Destination address */ if ((CheckSrc == 0) || (CheckDest == 0)) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_ERR, ("SkRlmtBuildPacket: Invalid %s%saddr.\n", - (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : ""))) + (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : ""))); } #endif @@ -878,7 +635,7 @@ SK_MAC_ADDR *DestAddr) /* Destination address */ for (i = 0; i < 4; i++) { pPacket->Random[i] = pAC->Rlmt.Port[PortNumber].Random[i]; } - + SK_U16_TO_NETWORK_ORDER( SK_RLMT_PACKET_VERSION, &pPacket->RlmtPacketVersion[0]); @@ -1044,7 +801,7 @@ SK_U32 PortNumber) /* Sending port */ SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_TX, - ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber)) + ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber)); } } return; @@ -1083,7 +840,7 @@ SK_U32 PortNumber) /* Port to check */ * Bring it up. */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Received on PortDown.\n")) + ("SkRlmtPacketReceive: Received on PortDown.\n")); pRPort->PortState = SK_RLMT_PS_GOING_UP; pRPort->GuTimeStamp = SkOsGetTime(pAC); @@ -1097,7 +854,7 @@ SK_U32 PortNumber) /* Port to check */ } /* PortDown && !SuspectTx */ else if (pRPort->CheckingState & SK_RLMT_PCS_RX) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Stop bringing port down.\n")) + ("SkRlmtPacketReceive: Stop bringing port down.\n")); SkTimerStop(pAC, IoC, &pRPort->DownRxTimer); pRPort->CheckingState &= ~SK_RLMT_PCS_RX; /* pAC->Rlmt.CheckSwitch = SK_TRUE; */ @@ -1144,7 +901,7 @@ SK_MBUF *pMb) /* Received packet */ pRPort = &pAC->Rlmt.Port[PortNumber]; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber)) + ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber)); pRPacket = (SK_RLMT_PACKET*)pMb->pData; pSPacket = (SK_SPTREE_PACKET*)pRPacket; @@ -1156,7 +913,7 @@ SK_MBUF *pMb) /* Received packet */ if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) != 0) { SkRlmtPortReceives(pAC, IoC, PortNumber); } - + /* Check destination address. */ if (!SK_ADDR_EQUAL(pAPort->CurrentMacAddress.a, pRPacket->DstAddr) && @@ -1165,7 +922,7 @@ SK_MBUF *pMb) /* Received packet */ /* Not sent to current MAC or registered MC address => Trash it. */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Not for me.\n")) + ("SkRlmtPacketReceive: Not for me.\n")); SkDrvFreeRlmtMbuf(pAC, IoC, pMb); return; @@ -1203,7 +960,7 @@ SK_MBUF *pMb) /* Received packet */ pRPacket->Indicator[5] == SK_RLMT_INDICATOR5 && pRPacket->Indicator[6] == SK_RLMT_INDICATOR6) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Duplicate MAC Address.\n")) + ("SkRlmtPacketReceive: Duplicate MAC Address.\n")); /* Error Log entry. */ SK_ERR_LOG(pAC, SK_ERRCL_COMM, SKERR_RLMT_E006, SKERR_RLMT_E006_MSG); @@ -1211,7 +968,7 @@ SK_MBUF *pMb) /* Received packet */ else { /* Simply trash it. */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Sent by me.\n")) + ("SkRlmtPacketReceive: Sent by me.\n")); } SkDrvFreeRlmtMbuf(pAC, IoC, pMb); @@ -1255,7 +1012,7 @@ SK_MBUF *pMb) /* Received packet */ #endif /* 0 */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Announce.\n")) + ("SkRlmtPacketReceive: Announce.\n")); SkDrvFreeRlmtMbuf(pAC, IoC, pMb); break; @@ -1263,7 +1020,7 @@ SK_MBUF *pMb) /* Received packet */ case SK_PACKET_ALIVE: if (pRPacket->SSap & LLC_COMMAND_RESPONSE_BIT) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Alive Reply.\n")) + ("SkRlmtPacketReceive: Alive Reply.\n")); if (!(pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_LLC) || SK_ADDR_EQUAL( @@ -1294,7 +1051,7 @@ SK_MBUF *pMb) /* Received packet */ } else { /* Alive Request Packet. */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Alive Request.\n")) + ("SkRlmtPacketReceive: Alive Request.\n")); pRPort->RxHelloCts++; @@ -1313,7 +1070,7 @@ SK_MBUF *pMb) /* Received packet */ case SK_PACKET_CHECK_TX: SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Check your tx line.\n")) + ("SkRlmtPacketReceive: Check your tx line.\n")); /* A port checking us requests us to check our tx line. */ pRPort->CheckingState |= SK_RLMT_PCS_TX; @@ -1336,7 +1093,7 @@ SK_MBUF *pMb) /* Received packet */ case SK_PACKET_ADDR_CHANGED: SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Address Change.\n")) + ("SkRlmtPacketReceive: Address Change.\n")); /* Build the check chain. */ SkRlmtBuildCheckChain(pAC, pRPort->Net->NetNumber); @@ -1345,7 +1102,7 @@ SK_MBUF *pMb) /* Received packet */ default: SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Unknown RLMT packet.\n")) + ("SkRlmtPacketReceive: Unknown RLMT packet.\n")); /* RA;:;: ??? */ SkDrvFreeRlmtMbuf(pAC, IoC, pMb); @@ -1355,7 +1112,7 @@ SK_MBUF *pMb) /* Received packet */ pSPacket->Ctrl == SK_RLMT_SPT_CTRL && (pSPacket->SSap & ~LLC_COMMAND_RESPONSE_BIT) == SK_RLMT_SPT_SSAP) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: BPDU Packet.\n")) + ("SkRlmtPacketReceive: BPDU Packet.\n")); /* Spanning Tree packet. */ pRPort->RxSpHelloCts++; @@ -1387,7 +1144,7 @@ SK_MBUF *pMb) /* Received packet */ pRPort->Root.Id[0], pRPort->Root.Id[1], pRPort->Root.Id[2], pRPort->Root.Id[3], pRPort->Root.Id[4], pRPort->Root.Id[5], - pRPort->Root.Id[6], pRPort->Root.Id[7])) + pRPort->Root.Id[6], pRPort->Root.Id[7])); } SkDrvFreeRlmtMbuf(pAC, IoC, pMb); @@ -1398,7 +1155,7 @@ SK_MBUF *pMb) /* Received packet */ } else { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, - ("SkRlmtPacketReceive: Unknown Packet Type.\n")) + ("SkRlmtPacketReceive: Unknown Packet Type.\n")); /* Unknown packet. */ SkDrvFreeRlmtMbuf(pAC, IoC, pMb); @@ -1480,7 +1237,7 @@ SK_U32 PortNumber) /* Port to check */ if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) == 0) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("SkRlmtCheckPort %d: No (%d) receives in last time slot.\n", - PortNumber, pRPort->PacketsPerTimeSlot)) + PortNumber, pRPort->PacketsPerTimeSlot)); /* * Check segmentation if there was no receive at least twice @@ -1497,7 +1254,7 @@ SK_U32 PortNumber) /* Port to check */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("SkRlmtCheckPort: PortsSuspect %d, PcsRx %d.\n", - pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX)) + pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX)); if (pRPort->PortState != SK_RLMT_PS_DOWN) { NewTimeout = TO_SHORTEN(pAC->Rlmt.Port[PortNumber].Net->TimeoutValue); @@ -1543,8 +1300,8 @@ SK_U32 PortNumber) /* Port to check */ ("SkRlmtCheckPort %d: %d (%d) receives in last time slot.\n", PortNumber, pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot, - pRPort->PacketsPerTimeSlot)) - + pRPort->PacketsPerTimeSlot)); + SkRlmtPortReceives(pAC, IoC, PortNumber); if (pAC->Rlmt.CheckSwitch) { SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); @@ -1584,16 +1341,16 @@ SK_U32 *pSelect) /* New active port */ BcTimeStamp = 0; /* Not totally necessary, but feeling better. */ PortFound = SK_FALSE; - + /* Select port with the latest TimeStamp. */ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("TimeStamp Port %d (Down: %d, NoRx: %d): %08x %08x.\n", i, - pAC->Rlmt.Port[i].PortDown, pAC->Rlmt.Port[i].PortNoRx, + pAC->Rlmt.Port[i].PortDown, pAC->Rlmt.Port[i].PortNoRx, *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_HI32), - *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32))) + *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32))); if (!pAC->Rlmt.Port[i].PortDown && !pAC->Rlmt.Port[i].PortNoRx) { if (!PortFound || pAC->Rlmt.Port[i].BcTimeStamp > BcTimeStamp) { @@ -1606,7 +1363,7 @@ SK_U32 *pSelect) /* New active port */ if (PortFound) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Port %d received the last broadcast.\n", *pSelect)) + ("Port %d received the last broadcast.\n", *pSelect)); /* Look if another port's time stamp is similar. */ for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { @@ -1619,9 +1376,9 @@ SK_U32 *pSelect) /* New active port */ pAC->Rlmt.Port[i].BcTimeStamp + SK_RLMT_BC_DELTA > BcTimeStamp)) { PortFound = SK_FALSE; - + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Port %d received a broadcast at a similar time.\n", i)) + ("Port %d received a broadcast at a similar time.\n", i)); break; } } @@ -1633,7 +1390,7 @@ SK_U32 *pSelect) /* New active port */ ("SK_RLMT_SELECT_BCRX found Port %d receiving the substantially " "latest broadcast (%u).\n", *pSelect, - BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp)) + BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp)); } #endif /* DEBUG */ @@ -1682,7 +1439,7 @@ SK_U32 *pSelect) /* New active port */ PortFound = SK_TRUE; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("SK_RLMT_SELECT_NOTSUSPECT found Port %d up and not check RX.\n", - *pSelect)) + *pSelect)); break; } } @@ -1731,7 +1488,7 @@ SK_BOOL AutoNegDone) /* Successfully auto-negotiated? */ } PortFound = SK_TRUE; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect)) + ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect)); break; } } @@ -1792,7 +1549,7 @@ SK_BOOL AutoNegDone) /* Successfully auto-negotiated? */ } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect)) + ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect)); return (SK_TRUE); } /* SkRlmtSelectGoingUp */ @@ -1838,7 +1595,7 @@ SK_BOOL AutoNegDone) /* Successfully auto-negotiated? */ } PortFound = SK_TRUE; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect)) + ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect)); break; } } @@ -1928,16 +1685,19 @@ SK_U32 NetIdx) /* Net index */ Para.Para32[1] = NetIdx; SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_UP, Para); - if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 && - (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, - pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber, - SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx]. - CurrentMacAddress, &SkRlmtMcAddr)) != NULL) { - /* - * Send announce packet to RLMT multicast address to force - * switches to learn the new location of the logical MAC address. - */ - SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + if (pAC->Rlmt.NumNets == 1) { + if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 && + (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, + pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber, + SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx]. + CurrentMacAddress, &SkRlmtMcAddr)) != NULL) { + + /* + * Send announce packet to RLMT multicast address to force + * switches to learn the new location of the logical MAC address. + */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } } } else { @@ -1974,7 +1734,7 @@ SK_U32 NetIdx) /* Net index */ /* check of ChgBcPrio flag added */ if ((pAC->Rlmt.Net[0].RlmtMode != SK_RLMT_MODE_CLS) && (!pAC->Rlmt.Net[0].ChgBcPrio)) { - + if (!PortFound) { PortFound = SkRlmtSelectBcRx( pAC, IoC, Active, PrefPort, &Para.Para32[1]); @@ -2036,7 +1796,7 @@ SK_U32 NetIdx) /* Net index */ if (Para.Para32[1] != Active) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Active: %d, Para1: %d.\n", Active, Para.Para32[1])) + ("Active: %d, Para1: %d.\n", Active, Para.Para32[1])); pAC->Rlmt.Net[NetIdx].ActivePort = Para.Para32[1]; Para.Para32[0] = pAC->Rlmt.Net[NetIdx]. Port[Para.Para32[0]]->PortNumber; @@ -2116,7 +1876,7 @@ SK_U32 NetIdx) /* Net number */ pNet->Port[i]->Root.Id[0], pNet->Port[i]->Root.Id[1], pNet->Port[i]->Root.Id[2], pNet->Port[i]->Root.Id[3], pNet->Port[i]->Root.Id[4], pNet->Port[i]->Root.Id[5], - pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7])) + pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7])); if (!pNet->RootIdSet) { pNet->Root = pNet->Port[i]->Root; @@ -2130,7 +1890,7 @@ SK_U32 NetIdx) /* Net number */ break; } } - + if (!Equal) { SK_ERR_LOG(pAC, SK_ERRCL_COMM, SKERR_RLMT_E005, SKERR_RLMT_E005_MSG); Para.Para32[0] = NetIdx; @@ -2211,13 +1971,13 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ SK_U32 i; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0])) + ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0])); if (Para.Para32[1] != (SK_U32)-1) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad Parameter.\n")) + ("Bad Parameter.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n")) + ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n")); return; } @@ -2238,7 +1998,7 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n")) + ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n")); } /* SkRlmtEvtPortStartTim */ @@ -2266,21 +2026,21 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 Undefined */ SK_EVPARA Para2; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0])) + ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0])); pRPort = &pAC->Rlmt.Port[Para.Para32[0]]; if (!pRPort->PortStarted) { SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E008, SKERR_RLMT_E008_MSG); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_LINK_UP Event EMPTY.\n")) + ("SK_RLMT_LINK_UP Event EMPTY.\n")); return; } if (!pRPort->LinkDown) { /* RA;:;: Any better solution? */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_LINK_UP Event EMPTY.\n")) + ("SK_RLMT_LINK_UP Event EMPTY.\n")); return; } @@ -2332,14 +2092,17 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 Undefined */ SKGE_RLMT, SK_RLMT_PORTUP_TIM, Para2); /* Later: if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) && */ - if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 && - (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 && - (Para2.pParaPtr = - SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE, - &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr) - ) != NULL) { - /* Send "new" packet to RLMT multicast address. */ - SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2); + if (pAC->Rlmt.NumNets == 1) { + if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 && + (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 && + (Para2.pParaPtr = + SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE, + &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr) + ) != NULL) { + + /* Send "new" packet to RLMT multicast address. */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2); + } } if (pRPort->Net->RlmtMode & SK_RLMT_CHECK_SEG) { @@ -2358,7 +2121,7 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 Undefined */ } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_LINK_UP Event END.\n")) + ("SK_RLMT_LINK_UP Event END.\n")); } /* SkRlmtEvtLinkUp */ @@ -2384,20 +2147,20 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ SK_RLMT_PORT *pRPort; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0])) + ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0])); if (Para.Para32[1] != (SK_U32)-1) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad Parameter.\n")) + ("Bad Parameter.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORTUP_TIM Event EMPTY.\n")) + ("SK_RLMT_PORTUP_TIM Event EMPTY.\n")); return; } pRPort = &pAC->Rlmt.Port[Para.Para32[0]]; if (pRPort->LinkDown || (pRPort->PortState == SK_RLMT_PS_UP)) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0])) + ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0])); return; } @@ -2412,7 +2175,7 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORTUP_TIM Event END.\n")) + ("SK_RLMT_PORTUP_TIM Event END.\n")); } /* SkRlmtEvtPortUpTim */ @@ -2440,13 +2203,13 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("SK_RLMT_PORTDOWN* Port %d Event (%d) BEGIN.\n", - Para.Para32[0], Event)) + Para.Para32[0], Event)); if (Para.Para32[1] != (SK_U32)-1) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad Parameter.\n")) + ("Bad Parameter.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORTDOWN* Event EMPTY.\n")) + ("SK_RLMT_PORTDOWN* Event EMPTY.\n")); return; } @@ -2454,10 +2217,10 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ if (!pRPort->PortStarted || (Event == SK_RLMT_PORTDOWN_TX_TIM && !(pRPort->CheckingState & SK_RLMT_PCS_TX))) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event)) + ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event)); return; } - + /* Stop port's timers. */ SkTimerStop(pAC, IoC, &pRPort->UpTimer); SkTimerStop(pAC, IoC, &pRPort->DownRxTimer); @@ -2491,7 +2254,7 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event)) + ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event)); } /* SkRlmtEvtPortDownX */ @@ -2518,7 +2281,7 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 Undefined */ pRPort = &pAC->Rlmt.Port[Para.Para32[0]]; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0])) + ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0])); if (!pAC->Rlmt.Port[Para.Para32[0]].LinkDown) { pRPort->Net->LinksUp--; @@ -2537,7 +2300,7 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 Undefined */ } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_LINK_DOWN Event END.\n")) + ("SK_RLMT_LINK_DOWN Event END.\n")); } /* SkRlmtEvtLinkDown */ @@ -2566,13 +2329,13 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ SK_MAC_ADDR *pNewMacAddr; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0])) + ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0])); if (Para.Para32[1] != (SK_U32)-1) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad Parameter.\n")) + ("Bad Parameter.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORT_ADDR Event EMPTY.\n")) + ("SK_RLMT_PORT_ADDR Event EMPTY.\n")); return; } @@ -2596,7 +2359,7 @@ SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PORT_ADDR Event END.\n")) + ("SK_RLMT_PORT_ADDR Event END.\n")); } /* SkRlmtEvtPortAddr */ @@ -2624,35 +2387,35 @@ SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ SK_U32 PortNumber; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0])) + ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0])); if (Para.Para32[1] != (SK_U32)-1) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad Parameter.\n")) + ("Bad Parameter.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_START Event EMPTY.\n")) + ("SK_RLMT_START Event EMPTY.\n")); return; } if (Para.Para32[0] >= pAC->Rlmt.NumNets) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad NetNumber %d.\n", Para.Para32[0])) + ("Bad NetNumber %d.\n", Para.Para32[0])); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_START Event EMPTY.\n")) + ("SK_RLMT_START Event EMPTY.\n")); return; } if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState != SK_RLMT_RS_INIT) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_START Event EMPTY.\n")) + ("SK_RLMT_START Event EMPTY.\n")); return; } if (pAC->Rlmt.NetsStarted >= pAC->Rlmt.NumNets) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("All nets should have been started.\n")) + ("All nets should have been started.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_START Event EMPTY.\n")) + ("SK_RLMT_START Event EMPTY.\n")); return; } @@ -2686,7 +2449,7 @@ SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ pAC->Rlmt.NetsStarted++; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_START Event END.\n")) + ("SK_RLMT_START Event END.\n")); } /* SkRlmtEvtStart */ @@ -2714,35 +2477,35 @@ SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ SK_U32 i; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0])) + ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0])); if (Para.Para32[1] != (SK_U32)-1) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad Parameter.\n")) + ("Bad Parameter.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STOP Event EMPTY.\n")) + ("SK_RLMT_STOP Event EMPTY.\n")); return; } if (Para.Para32[0] >= pAC->Rlmt.NumNets) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad NetNumber %d.\n", Para.Para32[0])) + ("Bad NetNumber %d.\n", Para.Para32[0])); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STOP Event EMPTY.\n")) + ("SK_RLMT_STOP Event EMPTY.\n")); return; } if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState == SK_RLMT_RS_INIT) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STOP Event EMPTY.\n")) + ("SK_RLMT_STOP Event EMPTY.\n")); return; } if (pAC->Rlmt.NetsStarted == 0) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("All nets are stopped.\n")) + ("All nets are stopped.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STOP Event EMPTY.\n")) + ("SK_RLMT_STOP Event EMPTY.\n")); return; } @@ -2777,7 +2540,7 @@ SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ pAC->Rlmt.NetsStarted--; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STOP Event END.\n")) + ("SK_RLMT_STOP Event END.\n")); } /* SkRlmtEvtStop */ @@ -2807,13 +2570,13 @@ SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ SK_U32 i; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_TIM Event BEGIN.\n")) + ("SK_RLMT_TIM Event BEGIN.\n")); if (Para.Para32[1] != (SK_U32)-1) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad Parameter.\n")) + ("Bad Parameter.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_TIM Event EMPTY.\n")) + ("SK_RLMT_TIM Event EMPTY.\n")); return; } @@ -2885,7 +2648,7 @@ SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_TIM Event END.\n")) + ("SK_RLMT_TIM Event END.\n")); } /* SkRlmtEvtTim */ @@ -2913,13 +2676,13 @@ SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ #endif /* DEBUG */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SEG_TIM Event BEGIN.\n")) + ("SK_RLMT_SEG_TIM Event BEGIN.\n")); if (Para.Para32[1] != (SK_U32)-1) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad Parameter.\n")) + ("Bad Parameter.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SEG_TIM Event EMPTY.\n")) + ("SK_RLMT_SEG_TIM Event EMPTY.\n")); return; } @@ -2943,15 +2706,15 @@ SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ InAddr8[3], InAddr8[4], InAddr8[5], pAPort->Exact[k].a[0], pAPort->Exact[k].a[1], pAPort->Exact[k].a[2], pAPort->Exact[k].a[3], - pAPort->Exact[k].a[4], pAPort->Exact[k].a[5])) + pAPort->Exact[k].a[4], pAPort->Exact[k].a[5])); } } #endif /* xDEBUG */ - + SkRlmtCheckSeg(pAC, IoC, Para.Para32[0]); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SEG_TIM Event END.\n")) + ("SK_RLMT_SEG_TIM Event END.\n")); } /* SkRlmtEvtSegTim */ @@ -2978,20 +2741,20 @@ SK_EVPARA Para) /* SK_MBUF *pMb */ SK_MBUF *pNextMb; SK_U32 NetNumber; - + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n")) + ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n")); /* Should we ignore frames during port switching? */ #ifdef DEBUG pMb = Para.pParaPtr; if (pMb == NULL) { - SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n")); } else if (pMb->pNext != NULL) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("More than one mbuf or pMb->pNext not set.\n")) + ("More than one mbuf or pMb->pNext not set.\n")); } #endif /* DEBUG */ @@ -3009,7 +2772,7 @@ SK_EVPARA Para) /* SK_MBUF *pMb */ } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PACKET_RECEIVED Event END.\n")) + ("SK_RLMT_PACKET_RECEIVED Event END.\n")); } /* SkRlmtEvtPacketRx */ @@ -3036,21 +2799,21 @@ SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ SK_RLMT_PORT *pRPort; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STATS_CLEAR Event BEGIN.\n")) + ("SK_RLMT_STATS_CLEAR Event BEGIN.\n")); if (Para.Para32[1] != (SK_U32)-1) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad Parameter.\n")) + ("Bad Parameter.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STATS_CLEAR Event EMPTY.\n")) + ("SK_RLMT_STATS_CLEAR Event EMPTY.\n")); return; } if (Para.Para32[0] >= pAC->Rlmt.NumNets) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad NetNumber %d.\n", Para.Para32[0])) + ("Bad NetNumber %d.\n", Para.Para32[0])); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STATS_CLEAR Event EMPTY.\n")) + ("SK_RLMT_STATS_CLEAR Event EMPTY.\n")); return; } @@ -3065,7 +2828,7 @@ SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STATS_CLEAR Event END.\n")) + ("SK_RLMT_STATS_CLEAR Event END.\n")); } /* SkRlmtEvtStatsClear */ @@ -3089,28 +2852,28 @@ SK_IOC IoC, /* I/O Context */ SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STATS_UPDATE Event BEGIN.\n")) + ("SK_RLMT_STATS_UPDATE Event BEGIN.\n")); if (Para.Para32[1] != (SK_U32)-1) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad Parameter.\n")) + ("Bad Parameter.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STATS_UPDATE Event EMPTY.\n")) + ("SK_RLMT_STATS_UPDATE Event EMPTY.\n")); return; } if (Para.Para32[0] >= pAC->Rlmt.NumNets) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad NetNumber %d.\n", Para.Para32[0])) + ("Bad NetNumber %d.\n", Para.Para32[0])); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STATS_UPDATE Event EMPTY.\n")) + ("SK_RLMT_STATS_UPDATE Event EMPTY.\n")); return; } /* Update statistics - currently always up-to-date. */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_STATS_UPDATE Event END.\n")) + ("SK_RLMT_STATS_UPDATE Event END.\n")); } /* SkRlmtEvtStatsUpdate */ @@ -3134,13 +2897,13 @@ SK_IOC IoC, /* I/O Context */ SK_EVPARA Para) /* SK_U32 PortIndex; SK_U32 NetNumber */ { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0])) + ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0])); if (Para.Para32[1] >= pAC->Rlmt.NumNets) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad NetNumber %d.\n", Para.Para32[1])) + ("Bad NetNumber %d.\n", Para.Para32[1])); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n")) + ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n")); return; } @@ -3153,7 +2916,7 @@ SK_EVPARA Para) /* SK_U32 PortIndex; SK_U32 NetNumber */ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E010, SKERR_RLMT_E010_MSG); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n")) + ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n")); return; } @@ -3167,7 +2930,7 @@ SK_EVPARA Para) /* SK_U32 PortIndex; SK_U32 NetNumber */ } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_PREFPORT_CHANGE Event END.\n")) + ("SK_RLMT_PREFPORT_CHANGE Event END.\n")); } /* SkRlmtEvtPrefportChange */ @@ -3193,37 +2956,37 @@ SK_EVPARA Para) /* SK_U32 NumNets; SK_U32 -1 */ int i; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SET_NETS Event BEGIN.\n")) + ("SK_RLMT_SET_NETS Event BEGIN.\n")); if (Para.Para32[1] != (SK_U32)-1) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad Parameter.\n")) + ("Bad Parameter.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SET_NETS Event EMPTY.\n")) + ("SK_RLMT_SET_NETS Event EMPTY.\n")); return; } if (Para.Para32[0] == 0 || Para.Para32[0] > SK_MAX_NETS || Para.Para32[0] > (SK_U32)pAC->GIni.GIMacsFound) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad number of nets: %d.\n", Para.Para32[0])) + ("Bad number of nets: %d.\n", Para.Para32[0])); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SET_NETS Event EMPTY.\n")) + ("SK_RLMT_SET_NETS Event EMPTY.\n")); return; } if (Para.Para32[0] == pAC->Rlmt.NumNets) { /* No change. */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SET_NETS Event EMPTY.\n")) + ("SK_RLMT_SET_NETS Event EMPTY.\n")); return; } /* Entering and leaving dual mode only allowed while nets are stopped. */ if (pAC->Rlmt.NetsStarted > 0) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Changing dual mode only allowed while all nets are stopped.\n")) + ("Changing dual mode only allowed while all nets are stopped.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SET_NETS Event EMPTY.\n")) + ("SK_RLMT_SET_NETS Event EMPTY.\n")); return; } @@ -3254,14 +3017,15 @@ SK_EVPARA Para) /* SK_U32 NumNets; SK_U32 -1 */ SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("RLMT: Changed to one net with two ports.\n")) + ("RLMT: Changed to one net with two ports.\n")); } else if (Para.Para32[0] == 2) { + pAC->Rlmt.RlmtOff = SK_TRUE; pAC->Rlmt.Port[1].Net= &pAC->Rlmt.Net[1]; pAC->Rlmt.Net[1].NumPorts = pAC->GIni.GIMacsFound - 1; pAC->Rlmt.Net[0].NumPorts = pAC->GIni.GIMacsFound - pAC->Rlmt.Net[1].NumPorts; - + pAC->Rlmt.NumNets = Para.Para32[0]; for (i = 0; (SK_U32)i < pAC->Rlmt.NumNets; i++) { pAC->Rlmt.Net[i].RlmtState = SK_RLMT_RS_INIT; @@ -3283,19 +3047,19 @@ SK_EVPARA Para) /* SK_U32 NumNets; SK_U32 -1 */ SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("RLMT: Changed to two nets with one port each.\n")) + ("RLMT: Changed to two nets with one port each.\n")); } else { /* Not implemented for more than two nets. */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SetNets not implemented for more than two nets.\n")) + ("SetNets not implemented for more than two nets.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SET_NETS Event EMPTY.\n")) + ("SK_RLMT_SET_NETS Event EMPTY.\n")); return; } SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_SET_NETS Event END.\n")) + ("SK_RLMT_SET_NETS Event END.\n")); } /* SkRlmtSetNets */ @@ -3323,13 +3087,13 @@ SK_EVPARA Para) /* SK_U32 NewMode; SK_U32 NetNumber */ SK_U32 PrevRlmtMode; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_MODE_CHANGE Event BEGIN.\n")) + ("SK_RLMT_MODE_CHANGE Event BEGIN.\n")); if (Para.Para32[1] >= pAC->Rlmt.NumNets) { SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Bad NetNumber %d.\n", Para.Para32[1])) + ("Bad NetNumber %d.\n", Para.Para32[1])); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_MODE_CHANGE Event EMPTY.\n")) + ("SK_RLMT_MODE_CHANGE Event EMPTY.\n")); return; } @@ -3339,9 +3103,9 @@ SK_EVPARA Para) /* SK_U32 NewMode; SK_U32 NetNumber */ Para.Para32[0] != SK_RLMT_MODE_CLS) { pAC->Rlmt.Net[Para.Para32[1]].RlmtMode = SK_RLMT_MODE_CLS; SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Forced RLMT mode to CLS on single port net.\n")) + ("Forced RLMT mode to CLS on single port net.\n")); SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_MODE_CHANGE Event EMPTY.\n")) + ("SK_RLMT_MODE_CHANGE Event EMPTY.\n")); return; } @@ -3407,7 +3171,7 @@ SK_EVPARA Para) /* SK_U32 NewMode; SK_U32 NetNumber */ } /* SK_RLMT_CHECK_SEG bit changed. */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("SK_RLMT_MODE_CHANGE Event END.\n")) + ("SK_RLMT_MODE_CHANGE Event END.\n")); } /* SkRlmtEvtModeChange */ @@ -3432,7 +3196,7 @@ SK_U32 Event, /* Event code */ SK_EVPARA Para) /* Event-specific parameter */ { switch (Event) { - + /* ----- PORT events ----- */ case SK_RLMT_PORTSTART_TIM: /* From RLMT via TIME. */ @@ -3493,7 +3257,7 @@ SK_EVPARA Para) /* Event-specific parameter */ default: /* Create error log entry. */ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, - ("Unknown RLMT Event %d.\n", Event)) + ("Unknown RLMT Event %d.\n", Event)); SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E003, SKERR_RLMT_E003_MSG); break; } /* switch() */ @@ -3505,4 +3269,4 @@ SK_EVPARA Para) /* Event-specific parameter */ } #endif /* __cplusplus */ -#endif /* CONFIG_SK98 */ +#endif diff --git a/drivers/sk98lin/sktimer.c b/drivers/sk98lin/sktimer.c index 37cd4c9..c54f8b8 100644 --- a/drivers/sk98lin/sktimer.c +++ b/drivers/sk98lin/sktimer.c @@ -1,17 +1,17 @@ /****************************************************************************** * * Name: sktimer.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.12 $ - * Date: $Date: 1999/11/22 13:38:51 $ + * Project: Gigabit Ethernet Adapters, Event Scheduler Module + * Version: $Revision: 2.2 $ + * Date: $Date: 2004/05/28 13:44:39 $ * Purpose: High level timer functions. * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998,1999 SysKonnect, - * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,66 +21,17 @@ * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: sktimer.c,v $ - * Revision 1.12 1999/11/22 13:38:51 cgoos - * Changed license header to GPL. - * - * Revision 1.11 1998/12/17 13:24:13 gklug - * fix: restart problem: do NOT destroy timer queue if init 1 is done - * - * Revision 1.10 1998/10/15 15:11:36 gklug - * fix: ID_sccs to SysKonnectFileId - * - * Revision 1.9 1998/09/15 15:15:04 cgoos - * Changed TRUE/FALSE to SK_TRUE/SK_FALSE - * - * Revision 1.8 1998/09/08 08:47:55 gklug - * add: init level handling - * - * Revision 1.7 1998/08/19 09:50:53 gklug - * fix: remove struct keyword from c-code (see CCC) add typedefs - * - * Revision 1.6 1998/08/17 13:43:13 gklug - * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR - * - * Revision 1.5 1998/08/14 07:09:14 gklug - * fix: chg pAc -> pAC - * - * Revision 1.4 1998/08/07 12:53:46 gklug - * fix: first compiled version - * - * Revision 1.3 1998/08/07 09:31:53 gklug - * fix: delta spelling - * - * Revision 1.2 1998/08/07 09:31:02 gklug - * adapt functions to new c coding conventions - * rmv: "fast" handling - * chg: inserting of new timer in queue. - * chg: event queue generation when timer runs out - * - * Revision 1.1 1998/08/05 11:27:55 gklug - * first version: adapted from SMT - * - * - * - * - ******************************************************************************/ - - #include - + #ifdef CONFIG_SK98 /* - Event queue and dispatcher -*/ + * Event queue and dispatcher + */ +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) static const char SysKonnectFileId[] = - "$Header: /usr56/projects/ge/schedule/sktimer.c,v 1.12 1999/11/22 13:38:51 cgoos Exp $" ; + "@(#) $Id: sktimer.c,v 2.2 2004/05/28 13:44:39 rschmidt Exp $ (C) Marvell."; +#endif #include "h/skdrv1st.h" /* Driver Specific Definitions */ #include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ @@ -109,14 +60,14 @@ static void timer_done(SK_AC *pAC,SK_IOC Ioc,int Restart); void SkTimerInit( SK_AC *pAC, /* Adapters context */ SK_IOC Ioc, /* IoContext */ -int Level) /* Init Level */ +int Level) /* Init Level */ { switch (Level) { case SK_INIT_DATA: - pAC->Tim.StQueue = 0 ; + pAC->Tim.StQueue = 0; break; case SK_INIT_IO: - SkHwtInit(pAC,Ioc) ; + SkHwtInit(pAC, Ioc); SkTimerDone(pAC, Ioc); break; default: @@ -133,31 +84,32 @@ SK_AC *pAC, /* Adapters context */ SK_IOC Ioc, /* IoContext */ SK_TIMER *pTimer) /* Timer Pointer to be started */ { - SK_TIMER **ppTimPrev ; - SK_TIMER *pTm ; + SK_TIMER **ppTimPrev; + SK_TIMER *pTm; + + /* remove timer from queue */ + pTimer->TmActive = SK_FALSE; - /* - * remove timer from queue - */ - pTimer->TmActive = SK_FALSE ; if (pAC->Tim.StQueue == pTimer && !pTimer->TmNext) { - SkHwtStop(pAC,Ioc) ; + SkHwtStop(pAC, Ioc); } - for (ppTimPrev = &pAC->Tim.StQueue ; (pTm = *ppTimPrev) ; + + for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev); ppTimPrev = &pTm->TmNext ) { + if (pTm == pTimer) { /* * Timer found in queue - * - dequeue it and + * - dequeue it * - correct delta of the next timer */ - *ppTimPrev = pTm->TmNext ; + *ppTimPrev = pTm->TmNext; if (pTm->TmNext) { /* correct delta of next timer in queue */ - pTm->TmNext->TmDelta += pTm->TmDelta ; + pTm->TmNext->TmDelta += pTm->TmDelta; } - return ; + return; } } } @@ -169,70 +121,60 @@ void SkTimerStart( SK_AC *pAC, /* Adapters context */ SK_IOC Ioc, /* IoContext */ SK_TIMER *pTimer, /* Timer Pointer to be started */ -SK_U32 Time, /* Time value */ +SK_U32 Time, /* Time Value (in microsec.) */ SK_U32 Class, /* Event Class for this timer */ SK_U32 Event, /* Event Value for this timer */ SK_EVPARA Para) /* Event Parameter for this timer */ { - SK_TIMER **ppTimPrev ; - SK_TIMER *pTm ; - SK_U32 Delta ; + SK_TIMER **ppTimPrev; + SK_TIMER *pTm; + SK_U32 Delta; - Time /= 16 ; /* input is uS, clock ticks are 16uS */ - if (!Time) - Time = 1 ; + SkTimerStop(pAC, Ioc, pTimer); - SkTimerStop(pAC,Ioc,pTimer) ; - - pTimer->TmClass = Class ; - pTimer->TmEvent = Event ; - pTimer->TmPara = Para ; - pTimer->TmActive = SK_TRUE ; + pTimer->TmClass = Class; + pTimer->TmEvent = Event; + pTimer->TmPara = Para; + pTimer->TmActive = SK_TRUE; if (!pAC->Tim.StQueue) { - /* First Timer to be started */ - pAC->Tim.StQueue = pTimer ; - pTimer->TmNext = 0 ; - pTimer->TmDelta = Time ; - SkHwtStart(pAC,Ioc,Time) ; - return ; + /* first Timer to be started */ + pAC->Tim.StQueue = pTimer; + pTimer->TmNext = 0; + pTimer->TmDelta = Time; + + SkHwtStart(pAC, Ioc, Time); + + return; } - /* - * timer correction - */ - timer_done(pAC,Ioc,0) ; + /* timer correction */ + timer_done(pAC, Ioc, 0); - /* - * find position in queue - */ - Delta = 0 ; - for (ppTimPrev = &pAC->Tim.StQueue ; (pTm = *ppTimPrev) ; + /* find position in queue */ + Delta = 0; + for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev); ppTimPrev = &pTm->TmNext ) { + if (Delta + pTm->TmDelta > Time) { - /* Position found */ - /* Here the timer needs to be inserted. */ - break ; + /* the timer needs to be inserted here */ + break; } - Delta += pTm->TmDelta ; + Delta += pTm->TmDelta; } /* insert in queue */ - *ppTimPrev = pTimer ; - pTimer->TmNext = pTm ; - pTimer->TmDelta = Time - Delta ; + *ppTimPrev = pTimer; + pTimer->TmNext = pTm; + pTimer->TmDelta = Time - Delta; if (pTm) { - /* There is a next timer - * -> correct its Delta value. - */ - pTm->TmDelta -= pTimer->TmDelta ; + /* there is a next timer: correct its Delta value */ + pTm->TmDelta -= pTimer->TmDelta; } - /* - * start new with first - */ - SkHwtStart(pAC,Ioc,pAC->Tim.StQueue->TmDelta) ; + /* restart with first */ + SkHwtStart(pAC, Ioc, pAC->Tim.StQueue->TmDelta); } @@ -240,58 +182,59 @@ void SkTimerDone( SK_AC *pAC, /* Adapters context */ SK_IOC Ioc) /* IoContext */ { - timer_done(pAC,Ioc,1) ; + timer_done(pAC, Ioc, 1); } static void timer_done( SK_AC *pAC, /* Adapters context */ SK_IOC Ioc, /* IoContext */ -int Restart) /* Do we need to restart the Hardware timer ? */ +int Restart) /* Do we need to restart the Hardware timer ? */ { - SK_U32 Delta ; - SK_TIMER *pTm ; - SK_TIMER *pTComp ; /* Timer completed now now */ - SK_TIMER **ppLast ; /* Next field of Last timer to be deq */ - int Done = 0 ; + SK_U32 Delta; + SK_TIMER *pTm; + SK_TIMER *pTComp; /* Timer completed now now */ + SK_TIMER **ppLast; /* Next field of Last timer to be deq */ + int Done = 0; - Delta = SkHwtRead(pAC,Ioc) ; - ppLast = &pAC->Tim.StQueue ; - pTm = pAC->Tim.StQueue ; + Delta = SkHwtRead(pAC, Ioc); + + ppLast = &pAC->Tim.StQueue; + pTm = pAC->Tim.StQueue; while (pTm && !Done) { if (Delta >= pTm->TmDelta) { /* Timer ran out */ - pTm->TmActive = SK_FALSE ; - Delta -= pTm->TmDelta ; - ppLast = &pTm->TmNext ; - pTm = pTm->TmNext ; - } else { + pTm->TmActive = SK_FALSE; + Delta -= pTm->TmDelta; + ppLast = &pTm->TmNext; + pTm = pTm->TmNext; + } + else { /* We found the first timer that did not run out */ - pTm->TmDelta -= Delta ; - Delta = 0 ; - Done = 1 ; + pTm->TmDelta -= Delta; + Delta = 0; + Done = 1; } } - *ppLast = 0 ; + *ppLast = 0; /* * pTm points to the first Timer that did not run out. * StQueue points to the first Timer that run out. */ - for ( pTComp = pAC->Tim.StQueue ; pTComp ; pTComp = pTComp->TmNext) { - SkEventQueue(pAC,pTComp->TmClass, pTComp->TmEvent, - pTComp->TmPara) ; + for (pTComp = pAC->Tim.StQueue; pTComp; pTComp = pTComp->TmNext) { + SkEventQueue(pAC,pTComp->TmClass, pTComp->TmEvent, pTComp->TmPara); } /* Set head of timer queue to the first timer that did not run out */ - pAC->Tim.StQueue = pTm ; + pAC->Tim.StQueue = pTm; if (Restart && pAC->Tim.StQueue) { /* Restart HW timer */ - SkHwtStart(pAC,Ioc,pAC->Tim.StQueue->TmDelta) ; + SkHwtStart(pAC, Ioc, pAC->Tim.StQueue->TmDelta); } } -#endif /* CONFIG_SK98 */ - /* End of file */ + +#endif diff --git a/drivers/sk98lin/sktwsi.c b/drivers/sk98lin/sktwsi.c new file mode 100644 index 0000000..6870904 --- /dev/null +++ b/drivers/sk98lin/sktwsi.c @@ -0,0 +1,1365 @@ +/****************************************************************************** + * + * Name: sktwsi.c + * Project: Gigabit Ethernet Adapters, TWSI-Module + * Version: $Revision: 1.12 $ + * Date: $Date: 2005/12/14 16:10:53 $ + * Purpose: Functions to access Voltage and Temperature Sensor + * + ******************************************************************************/ + +/****************************************************************************** + * + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2005 Marvell. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * The information in this file is provided "AS IS" without warranty. + * /LICENSE + * + ******************************************************************************/ +#include + +#ifdef CONFIG_SK98 + +/* + * TWSI Protocol + */ +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) +static const char SysKonnectFileId[] = + "@(#) $Id: sktwsi.c,v 1.12 2005/12/14 16:10:53 ibrueder Exp $ (C) Marvell."; +#endif + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/lm80.h" +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ + +#ifdef __C2MAN__ +/* + TWSI protocol implementation. + + General Description: + + The TWSI protocol is used for the temperature sensors and for + the serial EEPROM which hold the configuration. + + This file covers functions that allow to read write and do + some bulk requests a specified TWSI address. + + The Genesis has 2 TWSI buses. One for the EEPROM which holds + the VPD Data and one for temperature and voltage sensor. + The following picture shows the TWSI buses, TWSI devices and + their control registers. + + Note: The VPD functions are in skvpd.c +. +. PCI Config TWSI Bus for VPD Data: +. +. +------------+ +. | VPD EEPROM | +. +------------+ +. | +. | <-- TWSI +. | +. +-----------+-----------+ +. | | +. +-----------------+ +-----------------+ +. | PCI_VPD_ADR_REG | | PCI_VPD_DAT_REG | +. +-----------------+ +-----------------+ +. +. +. TWSI Bus for LM80 sensor: +. +. +-----------------+ +. | Temperature and | +. | Voltage Sensor | +. | LM80 | +. +-----------------+ +. | +. | +. TWSI --> | +. | +. +----+ +. +-------------->| OR |<--+ +. | +----+ | +. +------+------+ | +. | | | +. +--------+ +--------+ +----------+ +. | B2_I2C | | B2_I2C | | B2_I2C | +. | _CTRL | | _DATA | | _SW | +. +--------+ +--------+ +----------+ +. + The TWSI bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL + and B2_I2C_DATA registers. + For driver software it is recommended to use the TWSI control and + data register, because TWSI bus timing is done by the ASIC and + an interrupt may be received when the TWSI request is completed. + + Clock Rate Timing: MIN MAX generated by + VPD EEPROM: 50 kHz 100 kHz HW + LM80 over TWSI Ctrl/Data reg. 50 kHz 100 kHz HW + LM80 over B2_I2C_SW register 0 400 kHz SW + + Note: The clock generated by the hardware is dependend on the + PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD + clock is 50 kHz. + */ +intro() +{} +#endif + +#ifdef SK_DIAG +/* + * TWSI Fast Mode timing values used by the LM80. + * If new devices are added to the TWSI bus the timing values have to be checked. + */ +#ifndef I2C_SLOW_TIMING +#define T_CLK_LOW 1300L /* clock low time in ns */ +#define T_CLK_HIGH 600L /* clock high time in ns */ +#define T_DATA_IN_SETUP 100L /* data in Set-up Time */ +#define T_START_HOLD 600L /* start condition hold time */ +#define T_START_SETUP 600L /* start condition Set-up time */ +#define T_STOP_SETUP 600L /* stop condition Set-up time */ +#define T_BUS_IDLE 1300L /* time the bus must free after Tx */ +#define T_CLK_2_DATA_OUT 900L /* max. clock low to data output valid */ +#else /* I2C_SLOW_TIMING */ +/* TWSI Standard Mode Timing */ +#define T_CLK_LOW 4700L /* clock low time in ns */ +#define T_CLK_HIGH 4000L /* clock high time in ns */ +#define T_DATA_IN_SETUP 250L /* data in Set-up Time */ +#define T_START_HOLD 4000L /* start condition hold time */ +#define T_START_SETUP 4700L /* start condition Set-up time */ +#define T_STOP_SETUP 4000L /* stop condition Set-up time */ +#define T_BUS_IDLE 4700L /* time the bus must free after Tx */ +#endif /* !I2C_SLOW_TIMING */ + +#define NS2BCLK(x) (((x)*125)/10000) + +/* + * TWSI Wire Operations + * + * About I2C_CLK_LOW(): + * + * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting + * clock to low, to prevent the ASIC and the TWSI data client from driving the + * serial data line simultaneously (ASIC: last bit of a byte = '1', TWSI client + * send an 'ACK'). See also Concentrator Bugreport No. 10192. + */ +#define I2C_DATA_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA) +#define I2C_DATA_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA) +#define I2C_DATA_OUT(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA_DIR) +#define I2C_DATA_IN(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA) +#define I2C_CLK_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_CLK) +#define I2C_CLK_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR) +#define I2C_START_COND(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK) + +#define NS2CLKT(x) ((x*125L)/10000) + +/*--------------- TWSI Interface Register Functions --------------- */ + +/* + * sending one bit + */ +void SkI2cSndBit( +SK_IOC IoC, /* I/O Context */ +SK_U8 Bit) /* Bit to send */ +{ + I2C_DATA_OUT(IoC); + if (Bit) { + I2C_DATA_HIGH(IoC); + } + else { + I2C_DATA_LOW(IoC); + } + SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP)); + I2C_CLK_HIGH(IoC); + SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH)); + I2C_CLK_LOW(IoC); +} /* SkI2cSndBit*/ + + +/* + * Signal a start to the TWSI Bus. + * + * A start is signaled when data goes to low in a high clock cycle. + * + * Ends with Clock Low. + * + * Status: not tested + */ +void SkI2cStart( +SK_IOC IoC) /* I/O Context */ +{ + /* Init data and Clock to output lines */ + /* Set Data high */ + I2C_DATA_OUT(IoC); + I2C_DATA_HIGH(IoC); + /* Set Clock high */ + I2C_CLK_HIGH(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP)); + + /* Set Data Low */ + I2C_DATA_LOW(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD)); + + /* Clock low without Data to Input */ + I2C_START_COND(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW)); +} /* SkI2cStart */ + + +void SkI2cStop( +SK_IOC IoC) /* I/O Context */ +{ + /* Init data and Clock to output lines */ + /* Set Data low */ + I2C_DATA_OUT(IoC); + I2C_DATA_LOW(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT)); + + /* Set Clock high */ + I2C_CLK_HIGH(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP)); + + /* + * Set Data High: Do it by setting the Data Line to Input. + * Because of a pull up resistor the Data Line + * floods to high. + */ + I2C_DATA_IN(IoC); + + /* + * When TWSI activity is stopped + * o DATA should be set to input and + * o CLOCK should be set to high! + */ + SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE)); +} /* SkI2cStop */ + + +/* + * Receive just one bit via the TWSI bus. + * + * Note: Clock must be set to LOW before calling this function. + * + * Returns The received bit. + */ +int SkI2cRcvBit( +SK_IOC IoC) /* I/O Context */ +{ + int Bit; + SK_U8 I2cSwCtrl; + + /* Init data as input line */ + I2C_DATA_IN(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT)); + + I2C_CLK_HIGH(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH)); + + SK_I2C_GET_SW(IoC, &I2cSwCtrl); + + Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0; + + I2C_CLK_LOW(IoC); + SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT)); + + return(Bit); +} /* SkI2cRcvBit */ + + +/* + * Receive an ACK. + * + * returns 0 If acknowledged + * 1 in case of an error + */ +int SkI2cRcvAck( +SK_IOC IoC) /* I/O Context */ +{ + /* + * Received bit must be zero. + */ + return(SkI2cRcvBit(IoC) != 0); +} /* SkI2cRcvAck */ + + +/* + * Send an NACK. + */ +void SkI2cSndNAck( +SK_IOC IoC) /* I/O Context */ +{ + /* + * Received bit must be zero. + */ + SkI2cSndBit(IoC, 1); +} /* SkI2cSndNAck */ + + +/* + * Send an ACK. + */ +void SkI2cSndAck( +SK_IOC IoC) /* I/O Context */ +{ + /* + * Received bit must be zero. + */ + SkI2cSndBit(IoC, 0); +} /* SkI2cSndAck */ + + +/* + * Send one byte to the TWSI device and wait for ACK. + * + * Return acknowleged status. + */ +int SkI2cSndByte( +SK_IOC IoC, /* I/O Context */ +int Byte) /* byte to send */ +{ + int i; + + for (i = 0; i < 8; i++) { + if (Byte & (1<<(7-i))) { + SkI2cSndBit(IoC, 1); + } + else { + SkI2cSndBit(IoC, 0); + } + } + + return(SkI2cRcvAck(IoC)); +} /* SkI2cSndByte */ + + +/* + * Receive one byte and ack it. + * + * Return byte. + */ +int SkI2cRcvByte( +SK_IOC IoC, /* I/O Context */ +int Last) /* Last Byte Flag */ +{ + int i; + int Byte = 0; + + for (i = 0; i < 8; i++) { + Byte <<= 1; + Byte |= SkI2cRcvBit(IoC); + } + + if (Last) { + SkI2cSndNAck(IoC); + } + else { + SkI2cSndAck(IoC); + } + + return(Byte); +} /* SkI2cRcvByte */ + + +/* + * Start dialog and send device address + * + * Return 0 if acknowleged, 1 in case of an error + */ +int SkI2cSndDev( +SK_IOC IoC, /* I/O Context */ +int Addr, /* Device Address */ +int Rw) /* Read / Write Flag */ +{ + SkI2cStart(IoC); + Rw = ~Rw; + Rw &= I2C_WRITE; + return(SkI2cSndByte(IoC, (Addr << 1) | Rw)); +} /* SkI2cSndDev */ + +#endif /* SK_DIAG */ + +/*----------------- TWSI CTRL Register Functions ----------*/ + +/* + * waits for a completion of a TWSI transfer + * + * returns 0: success, transfer completes + * 1: error, transfer does not complete, TWSI transfer + * killed, wait loop terminated. + */ +int SkI2cWait( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Event) /* complete event to wait for (I2C_READ or I2C_WRITE) */ +{ + SK_U64 StartTime; + SK_U64 CurrentTime; + SK_U32 I2cCtrl; + + StartTime = SkOsGetTime(pAC); + + do { + CurrentTime = SkOsGetTime(pAC); + + if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) { + + SK_I2C_STOP(IoC); +#ifndef SK_DIAG + if (pAC->I2c.InitLevel > SK_INIT_DATA) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG); + } +#endif /* !SK_DIAG */ + return(1); + } + + SK_I2C_GET_CTL(IoC, &I2cCtrl); + +#ifdef xYUKON_DBG + printf("StartTime=%lu, CurrentTime=%lu\n", + StartTime, CurrentTime); + if (kbhit()) { + return(1); + } +#endif /* YUKON_DBG */ + + } while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31); + + return(0); +} /* SkI2cWait */ + + +/* + * waits for a completion of a TWSI transfer + * + * Returns + * Nothing + */ +void SkI2cWaitIrq( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + SK_SENSOR *pSen; + SK_U64 StartTime; + SK_U32 IrqSrc; + SK_U32 IsTwsiReadyBit; + + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + + if (pSen->SenState == SK_SEN_IDLE) { + return; + } + + IsTwsiReadyBit = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TWSI_RDY : IS_I2C_READY; + + StartTime = SkOsGetTime(pAC); + + do { + if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) { + + SK_I2C_STOP(IoC); +#ifndef SK_DIAG + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG); +#endif /* !SK_DIAG */ + return; + } + + SK_IN32(IoC, B0_ISRC, &IrqSrc); + + } while ((IrqSrc & IsTwsiReadyBit) == 0); + + pSen->SenState = SK_SEN_IDLE; + return; +} /* SkI2cWaitIrq */ + +/* + * writes a single byte or 4 bytes into the TWSI device + * + * returns 0: success + * 1: error + */ +int SkI2cWrite( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 I2cData, /* TWSI Data to write */ +int I2cDev, /* TWSI Device Address */ +int I2cDevSize, /* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */ +int I2cReg, /* TWSI Device Register Address */ +int I2cBurst) /* TWSI Burst Flag */ +{ + SK_OUT32(IoC, B2_I2C_DATA, I2cData); + + SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cDevSize, I2cReg, I2cBurst); + + return(SkI2cWait(pAC, IoC, I2C_WRITE)); +} /* SkI2cWrite*/ + + +#ifdef SK_DIAG +/* + * reads a single byte or 4 bytes from the TWSI device + * + * returns the word read + */ +SK_U32 SkI2cRead( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int I2cDev, /* TWSI Device Address */ +int I2cDevSize, /* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */ +int I2cReg, /* TWSI Device Register Address */ +int I2cBurst) /* TWSI Burst Flag */ +{ + SK_U32 Data; + + SK_OUT32(IoC, B2_I2C_DATA, 0); + + SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cDevSize, I2cReg, I2cBurst); + + if (SkI2cWait(pAC, IoC, I2C_READ) != 0) { + w_print("%s\n", SKERR_I2C_E002MSG); + } + + SK_IN32(IoC, B2_I2C_DATA, &Data); + + return(Data); +} /* SkI2cRead */ +#endif /* SK_DIAG */ + + +/* + * read a sensor's value + * + * This function reads a sensor's value from the TWSI sensor chip. The sensor + * is defined by its index into the sensors database in the struct pAC points + * to. + * Returns + * 1 if the read is completed + * 0 if the read must be continued (TWSI Bus still allocated) + */ +int SkI2cReadSensor( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_SENSOR *pSen) /* Sensor to be read */ +{ + if (pSen->SenRead != NULL) { + return((*pSen->SenRead)(pAC, IoC, pSen)); + } + + return(0); /* no success */ +} /* SkI2cReadSensor */ + +/* + * Do the Init state 0 initialization + */ +static int SkI2cInit0( +SK_AC *pAC) /* Adapter Context */ +{ + int i; + SK_SENSOR *pSen; + + /* Begin with first sensor */ + pAC->I2c.CurrSens = 0; + + /* Begin with timeout control for state machine */ + pAC->I2c.TimerMode = SK_TIMER_WATCH_SM; + + /* Set sensor number to zero */ + pAC->I2c.MaxSens = 0; + +#ifndef SK_DIAG + /* Initialize Number of Dummy Reads */ + pAC->I2c.DummyReads = SK_MAX_SENSORS; +#endif /* !SK_DIAG */ + + for (i = 0; i < SK_MAX_SENSORS; i++) { + pSen = &pAC->I2c.SenTable[i]; + + pSen->SenDesc = "unknown"; + pSen->SenType = SK_SEN_UNKNOWN; + pSen->SenThreErrHigh = 0; + pSen->SenThreErrLow = 0; + pSen->SenThreWarnHigh = 0; + pSen->SenThreWarnLow = 0; + pSen->SenReg = LM80_FAN2_IN; + pSen->SenInit = SK_SEN_DYN_INIT_NONE; + pSen->SenValue = 0; + pSen->SenErrFlag = SK_SEN_ERR_NOT_PRESENT; + pSen->SenErrCts = 0; + pSen->SenBegErrTS = 0; + pSen->SenState = SK_SEN_IDLE; + pSen->SenRead = NULL; + pSen->SenDev = 0; + } + + /* Now we are "INIT data"ed */ + pAC->I2c.InitLevel = SK_INIT_DATA; + return(0); +} /* SkI2cInit0*/ + + +/* + * Do the init state 1 initialization + * + * initialize the following register of the LM80: + * Configuration register: + * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT + * + * Interrupt Mask Register 1: + * - all interrupts are Disabled (0xff) + * + * Interrupt Mask Register 2: + * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter. + * + * Fan Divisor/RST_OUT register: + * - Divisors set to 1 (bits 00), all others 0s. + * + * OS# Configuration/Temperature resolution Register: + * - all 0s + * + */ +static int SkI2cInit1( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + int i; + SK_U8 I2cSwCtrl; + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + SK_SENSOR *pSen; + + if (pAC->I2c.InitLevel != SK_INIT_DATA) { + /* Re-init not needed in TWSI module */ + return(0); + } + + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC || + pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) { + /* No sensors on Yukon-EC and Yukon-FE */ + return(0); + } + + /* Set the Direction of TWSI-Data Pin to IN */ + SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA); + + /* Check for 32-Bit Yukon with Low at TWSI-Data Pin */ + SK_I2C_GET_SW(IoC, &I2cSwCtrl); + + if ((I2cSwCtrl & I2C_DATA) == 0) { + /* this is a 32-Bit board */ + pAC->GIni.GIYukon32Bit = SK_TRUE; + return(0); + } + + /* Check for 64 Bit Yukon without sensors */ + if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_CFG, 0) != 0) { + return(0); + } + + (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_1, 0); + + (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_2, 0); + + (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_FAN_CTRL, 0); + + (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_TEMP_CTRL, 0); + + (void)SkI2cWrite(pAC, IoC, (SK_U32)LM80_CFG_START, LM80_ADDR, I2C_025K_DEV, + LM80_CFG, 0); + + /* + * MaxSens has to be updated here, because PhyType is not + * set when performing Init Level 0 + */ + pAC->I2c.MaxSens = 5; + + pPrt = &pAC->GIni.GP[0]; + + if (pAC->GIni.GIGenesis) { + if (pPrt->PhyType == SK_PHY_BCOM) { + if (pAC->GIni.GIMacsFound == 1) { + pAC->I2c.MaxSens += 1; + } + else { + pAC->I2c.MaxSens += 3; + } + } + } + else { + pAC->I2c.MaxSens += 3; + } + + for (i = 0; i < pAC->I2c.MaxSens; i++) { + pSen = &pAC->I2c.SenTable[i]; + switch (i) { + case 0: + pSen->SenDesc = "Temperature"; + pSen->SenType = SK_SEN_TEMP; + pSen->SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN; + pSen->SenThreWarnLow = SK_SEN_TEMP_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_TEMP_LOW_ERR; + pSen->SenReg = LM80_TEMP_IN; + break; + case 1: + pSen->SenDesc = "Voltage PCI"; + pSen->SenType = SK_SEN_VOLT; + pSen->SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN; + if (pAC->GIni.GIPciBus != SK_PEX_BUS) { + pSen->SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR; + } + else { + pSen->SenThreWarnLow = 0; + pSen->SenThreErrLow = 0; + } + pSen->SenReg = LM80_VT0_IN; + break; + case 2: + pSen->SenDesc = "Voltage PCI-IO"; + pSen->SenType = SK_SEN_VOLT; + pSen->SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN; + if (pAC->GIni.GIPciBus != SK_PEX_BUS) { + pSen->SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR; + } + else { + pSen->SenThreWarnLow = 0; + pSen->SenThreErrLow = 0; + } + pSen->SenReg = LM80_VT1_IN; + pSen->SenInit = SK_SEN_DYN_INIT_PCI_IO; + break; + case 3: + if (pAC->GIni.GIGenesis) { + pSen->SenDesc = "Voltage ASIC"; + } + else { + pSen->SenDesc = "Voltage VMAIN"; + } + pSen->SenType = SK_SEN_VOLT; + pSen->SenThreErrHigh = SK_SEN_VDD_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN; + pSen->SenThreWarnLow = SK_SEN_VDD_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_VDD_LOW_ERR; + pSen->SenReg = LM80_VT2_IN; + break; + case 4: + if (pAC->GIni.GIGenesis) { + if (pPrt->PhyType == SK_PHY_BCOM) { + pSen->SenDesc = "Voltage PHY A PLL"; + pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN; + pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR; + } + else { + pSen->SenDesc = "Voltage PMA"; + pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN; + pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR; + } + } + else { + pSen->SenDesc = "Voltage VAUX"; + pSen->SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN; + if (pAC->GIni.GIVauxAvail) { + pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR; + } + else { + pSen->SenThreErrLow = 0; + pSen->SenThreWarnLow = 0; + } + } + pSen->SenType = SK_SEN_VOLT; + pSen->SenReg = LM80_VT3_IN; + break; + case 5: + if (CHIP_ID_YUKON_2(pAC)) { + if (pAC->GIni.GIChipRev == CHIP_REV_YU_XL_A0) { + pSen->SenDesc = "Voltage Core 1V3"; + pSen->SenThreErrHigh = SK_SEN_CORE_1V3_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_CORE_1V3_HIGH_WARN; + pSen->SenThreWarnLow = SK_SEN_CORE_1V3_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_CORE_1V3_LOW_ERR; + } + else { + pSen->SenDesc = "Voltage Core 1V2"; + pSen->SenThreErrHigh = SK_SEN_CORE_1V2_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_CORE_1V2_HIGH_WARN; + pSen->SenThreWarnLow = SK_SEN_CORE_1V2_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_CORE_1V2_LOW_ERR; + } + } + else { + if (pAC->GIni.GIGenesis) { + pSen->SenDesc = "Voltage PHY 2V5"; + pSen->SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN; + pSen->SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR; + } + else { + pSen->SenDesc = "Voltage Core 1V5"; + pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN; + pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR; + } + } + pSen->SenType = SK_SEN_VOLT; + pSen->SenReg = LM80_VT4_IN; + break; + case 6: + if (CHIP_ID_YUKON_2(pAC)) { + pSen->SenDesc = "Voltage PHY 1V5"; + pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN; + if (pAC->GIni.GIPciBus == SK_PEX_BUS) { + pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR; + } + else { + pSen->SenThreWarnLow = 0; + pSen->SenThreErrLow = 0; + } + } + else { + if (pAC->GIni.GIGenesis) { + pSen->SenDesc = "Voltage PHY B PLL"; + } + else { + pSen->SenDesc = "Voltage PHY 3V3"; + } + pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN; + pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR; + } + pSen->SenType = SK_SEN_VOLT; + pSen->SenReg = LM80_VT5_IN; + break; + case 7: + if (pAC->GIni.GIGenesis) { + pSen->SenDesc = "Speed Fan"; + pSen->SenType = SK_SEN_FAN; + pSen->SenThreErrHigh = SK_SEN_FAN_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_FAN_HIGH_WARN; + pSen->SenThreWarnLow = SK_SEN_FAN_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_FAN_LOW_ERR; + pSen->SenReg = LM80_FAN2_IN; + } + else { + pSen->SenDesc = "Voltage PHY 2V5"; + pSen->SenType = SK_SEN_VOLT; + pSen->SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR; + pSen->SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN; + pSen->SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR; + pSen->SenReg = LM80_VT6_IN; + } + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW, + SKERR_I2C_E001, SKERR_I2C_E001MSG); + break; + } + + pSen->SenValue = 0; + pSen->SenErrFlag = SK_SEN_ERR_OK; + pSen->SenErrCts = 0; + pSen->SenBegErrTS = 0; + pSen->SenState = SK_SEN_IDLE; + if (pSen->SenThreWarnLow != 0) { + pSen->SenRead = SkLm80ReadSensor; + } + pSen->SenDev = LM80_ADDR; + } + +#ifndef SK_DIAG + pAC->I2c.DummyReads = pAC->I2c.MaxSens; +#endif /* !SK_DIAG */ + + /* Clear TWSI IRQ */ + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); + + /* Now we are I/O initialized */ + pAC->I2c.InitLevel = SK_INIT_IO; + return(0); +} /* SkI2cInit1 */ + + +/* + * Init level 2: Start first sensor read. + */ +static int SkI2cInit2( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + int ReadComplete; + SK_SENSOR *pSen; + + if (pAC->I2c.InitLevel != SK_INIT_IO) { + /* ReInit not needed in TWSI module */ + /* Init0 and Init2 not permitted */ + return(0); + } + + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen); + + if (ReadComplete) { + SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG); + } + + /* Now we are correctly initialized */ + pAC->I2c.InitLevel = SK_INIT_RUN; + + return(0); +} /* SkI2cInit2*/ + + +/* + * Initialize TWSI devices + * + * Get the first voltage value and discard it. + * Go into temperature read mode. A default pointer is not set. + * + * The things to be done depend on the init level in the parameter list: + * Level 0: + * Initialize only the data structures. Do NOT access hardware. + * Level 1: + * Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts. + * Level 2: + * Everything is possible. Interrupts may be used from now on. + * + * return: + * 0 = success + * other = error. + */ +int SkI2cInit( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context needed in levels 1 and 2 */ +int Level) /* Init Level */ +{ + + switch (Level) { + case SK_INIT_DATA: + return(SkI2cInit0(pAC)); + case SK_INIT_IO: + return(SkI2cInit1(pAC, IoC)); + case SK_INIT_RUN: + return(SkI2cInit2(pAC, IoC)); + default: + break; + } + + return(0); +} /* SkI2cInit */ + + +#ifndef SK_DIAG +/* + * Interrupt service function for the TWSI Interface + * + * Clears the Interrupt source + * + * Reads the register and check it for sending a trap. + * + * Starts the timer if necessary. + */ +void SkI2cIsr( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + SK_EVPARA Para; + + /* Clear TWSI IRQ */ + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); + + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para); +} /* SkI2cIsr */ + + +/* + * Check this sensors Value against the threshold and send events. + */ +static void SkI2cCheckSensor( +SK_AC *pAC, /* Adapter Context */ +SK_SENSOR *pSen) +{ + SK_EVPARA ParaLocal; + SK_BOOL TooHigh; /* Is sensor too high? */ + SK_BOOL TooLow; /* Is sensor too low? */ + SK_U64 CurrTime; /* Current Time */ + SK_BOOL DoTrapSend; /* We need to send a trap */ + SK_BOOL DoErrLog; /* We need to log the error */ + SK_BOOL IsError; /* Error occured */ + + /* Check Dummy Reads first */ + if (pAC->I2c.DummyReads > 0) { + pAC->I2c.DummyReads--; + return; + } + + /* Get the current time */ + CurrTime = SkOsGetTime(pAC); + + /* Set para to the most useful setting: The current sensor. */ + ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens; + + /* Check the Value against the thresholds. First: Error Thresholds */ + TooHigh = pSen->SenValue > pSen->SenThreErrHigh; + TooLow = pSen->SenValue < pSen->SenThreErrLow; + + IsError = SK_FALSE; + + if (TooHigh || TooLow) { + /* Error condition is satisfied */ + DoTrapSend = SK_TRUE; + DoErrLog = SK_TRUE; + + /* Now error condition is satisfied */ + IsError = SK_TRUE; + + if (pSen->SenErrFlag == SK_SEN_ERR_ERR) { + /* This state is the former one */ + + /* So check first whether we have to send a trap */ + if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD > CurrTime) { + /* + * Do NOT send the Trap. The hold back time + * has to run out first. + */ + DoTrapSend = SK_FALSE; + } + + /* Check now whether we have to log an Error */ + if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD > CurrTime) { + /* + * Do NOT log the error. The hold back time + * has to run out first. + */ + DoErrLog = SK_FALSE; + } + } + else { + /* We came from a different state -> Set Begin Time Stamp */ + pSen->SenBegErrTS = CurrTime; + pSen->SenErrFlag = SK_SEN_ERR_ERR; + } + + if (DoTrapSend) { + /* Set current Time */ + pSen->SenLastErrTrapTS = CurrTime; + pSen->SenErrCts++; + + /* Queue PNMI Event */ + SkEventQueue(pAC, SKGE_PNMI, TooHigh ? + SK_PNMI_EVT_SEN_ERR_UPP : SK_PNMI_EVT_SEN_ERR_LOW, + ParaLocal); + } + + if (DoErrLog) { + /* Set current Time */ + pSen->SenLastErrLogTS = CurrTime; + + if (pSen->SenType == SK_SEN_TEMP) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, SKERR_I2C_E011MSG); + } + else if (pSen->SenType == SK_SEN_VOLT) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, SKERR_I2C_E012MSG); + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, SKERR_I2C_E015MSG); + } + } + } + + /* Check the Value against the thresholds */ + /* 2nd: Warning thresholds */ + TooHigh = pSen->SenValue > pSen->SenThreWarnHigh; + TooLow = pSen->SenValue < pSen->SenThreWarnLow; + + if (!IsError && (TooHigh || TooLow)) { + /* Error condition is satisfied */ + DoTrapSend = SK_TRUE; + DoErrLog = SK_TRUE; + + if (pSen->SenErrFlag == SK_SEN_ERR_WARN) { + /* This state is the former one */ + + /* So check first whether we have to send a trap */ + if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > CurrTime) { + /* + * Do NOT send the Trap. The hold back time + * has to run out first. + */ + DoTrapSend = SK_FALSE; + } + + /* Check now whether we have to log an Error */ + if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > CurrTime) { + /* + * Do NOT log the error. The hold back time + * has to run out first. + */ + DoErrLog = SK_FALSE; + } + } + else { + /* We came from a different state -> Set Begin Time Stamp */ + pSen->SenBegWarnTS = CurrTime; + pSen->SenErrFlag = SK_SEN_ERR_WARN; + } + + if (DoTrapSend) { + /* Set current Time */ + pSen->SenLastWarnTrapTS = CurrTime; + pSen->SenWarnCts++; + + /* Queue PNMI Event */ + SkEventQueue(pAC, SKGE_PNMI, TooHigh ? + SK_PNMI_EVT_SEN_WAR_UPP : SK_PNMI_EVT_SEN_WAR_LOW, ParaLocal); + } + + if (DoErrLog) { + /* Set current Time */ + pSen->SenLastWarnLogTS = CurrTime; + + if (pSen->SenType == SK_SEN_TEMP) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, SKERR_I2C_E009MSG); + } + else if (pSen->SenType == SK_SEN_VOLT) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, SKERR_I2C_E010MSG); + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, SKERR_I2C_E014MSG); + } + } + } + + /* Check for NO error at all */ + if (!IsError && !TooHigh && !TooLow) { + /* Set o.k. Status if no error and no warning condition */ + pSen->SenErrFlag = SK_SEN_ERR_OK; + } + + /* End of check against the thresholds */ + + if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) { + /* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */ + pSen->SenInit = SK_SEN_DYN_INIT_NONE; + + if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) { + /* 5V PCI-IO Voltage */ + pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR; + } + else { + /* 3.3V PCI-IO Voltage */ + pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN; + pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR; + } + } + +#ifdef TEST_ONLY + /* Dynamic thresholds also for VAUX of LM80 sensor */ + if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) { + + pSen->SenInit = SK_SEN_DYN_INIT_NONE; + + /* 3.3V VAUX Voltage */ + if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) { + pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR; + } + /* 0V VAUX Voltage */ + else { + pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR; + pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR; + } + } + + /* Check initialization state: the VIO Thresholds need adaption */ + if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN && + pSen->SenValue > SK_SEN_WARNLOW2C && + pSen->SenValue < SK_SEN_WARNHIGH2) { + + pSen->SenThreErrLow = SK_SEN_ERRLOW2C; + pSen->SenThreWarnLow = SK_SEN_WARNLOW2C; + pSen->SenInit = SK_TRUE; + } + + if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN && + pSen->SenValue > SK_SEN_WARNLOW2 && + pSen->SenValue < SK_SEN_WARNHIGH2C) { + + pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C; + pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C; + pSen->SenInit = SK_TRUE; + } +#endif + + if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG); + } +} /* SkI2cCheckSensor */ + + +/* + * The only Event to be served is the timeout event + * + */ +int SkI2cEvent( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Event, /* Module specific Event */ +SK_EVPARA Para) /* Event specific Parameter */ +{ + int ReadComplete; + SK_SENSOR *pSen; + SK_U32 Time; + SK_EVPARA ParaLocal; + int i; + + /* New case: no sensors */ + if (pAC->I2c.MaxSens == 0) { + return(0); + } + + switch (Event) { + case SK_I2CEV_IRQ: + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen); + + if (ReadComplete) { + /* Check sensor against defined thresholds */ + SkI2cCheckSensor(pAC, pSen); + + /* Increment Current sensor and set appropriate Timeout */ + pAC->I2c.CurrSens++; + if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) { + pAC->I2c.CurrSens = 0; + Time = SK_I2C_TIM_LONG; + } + else { + Time = SK_I2C_TIM_SHORT; + } + + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + else { + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_WATCH_SM; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + break; + case SK_I2CEV_TIM: + if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) { + + ParaLocal.Para64 = (SK_U64)0; + SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer); + + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen); + + if (ReadComplete) { + /* Check sensor against defined thresholds */ + SkI2cCheckSensor(pAC, pSen); + + /* Increment Current sensor and set appropriate Timeout */ + pAC->I2c.CurrSens++; + if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) { + pAC->I2c.CurrSens = 0; + Time = SK_I2C_TIM_LONG; + } + else { + Time = SK_I2C_TIM_SHORT; + } + + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + } + else { + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + pSen->SenErrFlag = SK_SEN_ERR_FAULTY; + SK_I2C_STOP(IoC); + + /* Increment Current sensor and set appropriate Timeout */ + pAC->I2c.CurrSens++; + if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) { + pAC->I2c.CurrSens = 0; + Time = SK_I2C_TIM_LONG; + } + else { + Time = SK_I2C_TIM_SHORT; + } + + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + break; + case SK_I2CEV_CLEAR: + for (i = 0; i < SK_MAX_SENSORS; i++) { + pSen = &pAC->I2c.SenTable[i]; + + pSen->SenErrFlag = SK_SEN_ERR_OK; + pSen->SenErrCts = 0; + pSen->SenWarnCts = 0; + pSen->SenBegErrTS = 0; + pSen->SenBegWarnTS = 0; + pSen->SenLastErrTrapTS = (SK_U64)0; + pSen->SenLastErrLogTS = (SK_U64)0; + pSen->SenLastWarnTrapTS = (SK_U64)0; + pSen->SenLastWarnLogTS = (SK_U64)0; + } + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG); + } + + return(0); +} /* SkI2cEvent*/ + +#endif /* !SK_DIAG */ + +#endif diff --git a/drivers/sk98lin/skvpd.c b/drivers/sk98lin/skvpd.c index 3b81e67..65ab271 100644 --- a/drivers/sk98lin/skvpd.c +++ b/drivers/sk98lin/skvpd.c @@ -1,174 +1,34 @@ /****************************************************************************** * * Name: skvpd.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.37 $ - * Date: $Date: 2003/01/13 10:42:45 $ - * Purpose: Shared software to read and write VPD data + * Project: Gigabit Ethernet Adapters, VPD-Module + * Version: $Revision: 2.6 $ + * Date: $Date: 2004/11/02 10:47:39 $ + * Purpose: Shared software to read and write VPD * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2004 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. * ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: skvpd.c,v $ - * Revision 1.37 2003/01/13 10:42:45 rschmidt - * Replaced check for PCI device Id from YUKON with GENESIS - * to set the VPD size in VpdInit() - * Editorial changes - * - * Revision 1.36 2002/11/14 15:16:56 gheinig - * Added const specifier to key and buf parameters for VpdPara, VpdRead - * and VpdWrite for Diag 7 GUI - * - * Revision 1.35 2002/10/21 14:31:59 gheinig - * Took out CVS web garbage at head of file - * - * Revision 1.34 2002/10/21 11:47:24 gheinig - * Reverted to version 1.32 due to unwanted commit - * - * Revision 1.32 2002/10/14 16:04:29 rschmidt - * Added saving of VPD ROM Size from PCI_OUR_REG_2 - * Avoid reading of PCI_OUR_REG_2 in VpdTransferBlock() - * Editorial changes - * - * Revision 1.31 2002/09/10 09:21:32 mkarl - * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis - * - * Revision 1.30 2002/09/09 14:43:03 mkarl - * changes for diagnostics in order to read VPD data before the adapter - * has been initialized - * editorial changes - * - * Revision 1.29 2002/07/26 13:20:43 mkarl - * added Yukon support - * save size of VPD in pAC->vpd.vpd_size - * - * Revision 1.28 2002/04/02 15:31:47 afischer - * Bug fix in VpdWait() - * - * Revision 1.27 2000/08/10 11:29:06 rassmann - * Editorial changes. - * Preserving 32-bit alignment in structs for the adapter context. - * Removed unused function VpdWriteDword() (#if 0). - * Made VpdReadKeyword() available for SKDIAG only. - * - * Revision 1.26 2000/06/13 08:00:01 mkarl - * additional cast to avoid compile problems in 64 bit environment - * - * Revision 1.25 1999/11/22 13:39:32 cgoos - * Changed license header to GPL. - * - * Revision 1.24 1999/03/11 14:25:49 malthoff - * Replace __STDC__ with SK_KR_PROTO. - * - * Revision 1.23 1999/01/11 15:13:11 gklug - * fix: syntax error - * - * Revision 1.22 1998/10/30 06:41:15 gklug - * rmv: WARNING - * - * Revision 1.21 1998/10/29 07:15:14 gklug - * fix: Write Stream function needs verify. - * - * Revision 1.20 1998/10/28 18:05:08 gklug - * chg: no DEBUG in VpdMayWrite - * - * Revision 1.19 1998/10/28 15:56:11 gklug - * fix: Return len at end of ReadStream - * fix: Write even less than 4 bytes correctly - * - * Revision 1.18 1998/10/28 09:00:47 gklug - * fix: unreferenced local vars - * - * Revision 1.17 1998/10/28 08:25:45 gklug - * fix: WARNING - * - * Revision 1.16 1998/10/28 08:17:30 gklug - * fix: typo - * - * Revision 1.15 1998/10/28 07:50:32 gklug - * fix: typo - * - * Revision 1.14 1998/10/28 07:20:38 gklug - * chg: Interface functions to use IoC as parameter as well - * fix: VpdRead/WriteDWord now returns SK_U32 - * chg: VPD_IN/OUT names conform to SK_IN/OUT - * add: usage of VPD_IN/OUT8 macros - * add: VpdRead/Write Stream functions to r/w a stream of data - * fix: VpdTransferBlock swapped illegal - * add: VpdMayWrite - * - * Revision 1.13 1998/10/22 10:02:37 gklug - * fix: SysKonnectFileId typo - * - * Revision 1.12 1998/10/20 10:01:01 gklug - * fix: parameter to SkOsGetTime - * - * Revision 1.11 1998/10/15 12:51:48 malthoff - * Remove unrequired parameter p in vpd_setup_para(). - * - * Revision 1.10 1998/10/08 14:52:43 malthoff - * Remove CvsId by SysKonnectFileId. - * - * Revision 1.9 1998/09/16 07:33:52 malthoff - * replace memcmp() by SK_MEMCMP and - * memcpy() by SK_MEMCPY() to be - * independent from the 'C' Standard Library. - * - * Revision 1.8 1998/08/19 12:52:35 malthoff - * compiler fix: use SK_VPD_KEY instead of S_VPD. - * - * Revision 1.7 1998/08/19 08:14:01 gklug - * fix: remove struct keyword as much as possible from the C-code (see CCC) - * - * Revision 1.6 1998/08/18 13:03:58 gklug - * SkOsGetTime now returns SK_U64 - * - * Revision 1.5 1998/08/18 08:17:29 malthoff - * Ensure we issue a VPD read in vpd_read_dword(). - * Discard all VPD keywords other than Vx or Yx, where - * x is '0..9' or 'A..Z'. - * - * Revision 1.4 1998/07/03 14:52:19 malthoff - * Add category SK_DBGCAT_FATAL to some debug macros. - * bug fix: correct the keyword name check in vpd_write(). - * - * Revision 1.3 1998/06/26 11:16:53 malthoff - * Correct the modified File Identifier. - * - * Revision 1.2 1998/06/26 11:13:43 malthoff - * Modify the File Identifier. - * - * Revision 1.1 1998/06/19 14:11:08 malthoff - * Created, Tests with AIX were performed successfully - * - * - ******************************************************************************/ - #include - + #ifdef CONFIG_SK98 /* Please refer skvpd.txt for infomation how to include this module */ static const char SysKonnectFileId[] = - "@(#)$Id: skvpd.c,v 1.37 2003/01/13 10:42:45 rschmidt Exp $ (C) SK"; + "@(#) $Id: skvpd.c,v 2.6 2004/11/02 10:47:39 rschmidt Exp $ (C) Marvell."; #include "h/skdrv1st.h" #include "h/sktypes.h" @@ -202,9 +62,10 @@ int event) /* event to wait for (VPD_READ / VPD_write) completion*/ SK_U64 start_time; SK_U16 state; - SK_DBG_MSG(pAC,SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, ("VPD wait for %s\n", event?"Write":"Read")); start_time = SkOsGetTime(pAC); + do { if (SkOsGetTime(pAC) - start_time > SK_TICKS_PER_SEC) { @@ -229,12 +90,13 @@ int event) /* event to wait for (VPD_READ / VPD_write) completion*/ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, ("state = %x, event %x\n",state,event)); - } while((int)(state & PCI_VPD_FLAG) == event); + } while ((int)(state & PCI_VPD_FLAG) == event); return(0); } -#ifdef SKDIAG + +#ifdef SK_DIAG /* * Read the dword at address 'addr' from the VPD EEPROM. @@ -272,8 +134,7 @@ int addr) /* VPD address */ ("VPD read dword data = 0x%x\n",Rtv)); return(Rtv); } - -#endif /* SKDIAG */ +#endif /* SK_DIAG */ #if 0 @@ -294,7 +155,6 @@ int addr) /* VPD address */ . over all 3.8 ms 13.2 ms . - Returns 0: success 1: error, I2C transfer does not terminate 2: error, data verify error @@ -334,6 +194,7 @@ SK_U32 data) /* VPD data to write */ #endif /* 0 */ + /* * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from * or to the I2C EEPROM. @@ -358,7 +219,7 @@ int Len) /* number of bytes to read / to write */ pComp = (SK_U8 *) buf; for (i = 0; i < Len; i++, buf++) { - if ((i%sizeof(SK_U32)) == 0) { + if ((i % SZ_LONG) == 0) { /* * At the begin of each cycle read the Data Reg * So it is initialized even if only a few bytes @@ -376,14 +237,13 @@ int Len) /* number of bytes to read / to write */ } } - /* Write current Byte */ - VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)), - *(SK_U8*)buf); + /* Write current byte */ + VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i % SZ_LONG), *(SK_U8*)buf); - if (((i%sizeof(SK_U32)) == 3) || (i == (Len - 1))) { + if (((i % SZ_LONG) == 3) || (i == (Len - 1))) { /* New Address needs to be written to VPD_ADDR reg */ AdrReg = (SK_U16) Addr; - Addr += sizeof(SK_U32); + Addr += SZ_LONG; AdrReg |= VPD_WRITE; /* WRITE operation */ VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg); @@ -393,7 +253,7 @@ int Len) /* number of bytes to read / to write */ if (Rtv != 0) { SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("Write Timed Out\n")); - return(i - (i%sizeof(SK_U32))); + return(i - (i % SZ_LONG)); } /* @@ -408,10 +268,10 @@ int Len) /* number of bytes to read / to write */ if (Rtv != 0) { SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("Verify Timed Out\n")); - return(i - (i%sizeof(SK_U32))); + return(i - (i % SZ_LONG)); } - for (j = 0; j <= (int)(i%sizeof(SK_U32)); j++, pComp++) { + for (j = 0; j <= (int)(i % SZ_LONG); j++, pComp++) { VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + j, &Data); @@ -419,7 +279,7 @@ int Len) /* number of bytes to read / to write */ /* Verify Error */ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("WriteStream Verify Error\n")); - return(i - (i%sizeof(SK_U32)) + j); + return(i - (i % SZ_LONG) + j); } } } @@ -447,10 +307,10 @@ int Len) /* number of bytes to read / to write */ int Rtv; for (i = 0; i < Len; i++, buf++) { - if ((i%sizeof(SK_U32)) == 0) { + if ((i % SZ_LONG) == 0) { /* New Address needs to be written to VPD_ADDR reg */ AdrReg = (SK_U16) Addr; - Addr += sizeof(SK_U32); + Addr += SZ_LONG; AdrReg &= ~VPD_WRITE; /* READ operation */ VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg); @@ -461,13 +321,13 @@ int Len) /* number of bytes to read / to write */ return(i); } } - VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)), - (SK_U8 *)buf); + VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i % SZ_LONG), (SK_U8 *)buf); } return(Len); } + /* * Read ore writes 'len' bytes of VPD data, starting at 'addr' from * or to the I2C EEPROM. @@ -517,8 +377,8 @@ int dir) /* transfer direction may be VPD_READ or VPD_WRITE */ return(Rtv); } -#ifdef SKDIAG +#if defined (SK_DIAG) || defined (SK_ASF) /* * Read 'len' bytes of VPD data, starting at 'addr'. * @@ -534,6 +394,7 @@ int len) /* number of bytes to read */ return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_READ)); } + /* * Write 'len' bytes of *but to the VPD EEPROM, starting at 'addr'. * @@ -548,18 +409,27 @@ int len) /* number of bytes to write */ { return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_WRITE)); } -#endif /* SKDIAG */ +#endif /* SK_DIAG */ -/* - * (re)initialize the VPD buffer + +/****************************************************************************** * - * Reads the VPD data from the EEPROM into the VPD buffer. - * Get the remaining read only and read / write space. + * VpdInit() - (re)initialize the VPD buffer * - * return 0: success - * 1: fatal VPD error + * Description: + * Reads the VPD data from the EEPROM into the VPD buffer. + * Get the remaining read only and read / write space. + * + * Note: + * This is a local function and should be used locally only. + * However, the ASF module needs to use this function also. + * Therfore it has been published. + * + * Returns: + * 0: success + * 1: fatal VPD error */ -static int VpdInit( +int VpdInit( SK_AC *pAC, /* Adapters context */ SK_IOC IoC) /* IO Context */ { @@ -570,7 +440,7 @@ SK_IOC IoC) /* IO Context */ SK_U16 dev_id; SK_U32 our_reg2; - SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit .. ")); + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit ... ")); VPD_IN16(pAC, IoC, PCI_DEVICE_ID, &dev_id); @@ -611,6 +481,13 @@ SK_IOC IoC) /* IO Context */ pAC->vpd.vpd_size = vpd_size; + /* Asus K8V Se Deluxe bugfix. Correct VPD content */ + i = 62; + if (!SK_STRNCMP(pAC->vpd.vpd_buf + i, " 8vpd.vpd_buf[i + 2] = '8'; + } + /* find the end tag of the RO area */ if (!(r = vpd_find_para(pAC, VPD_RV, &rp))) { SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, @@ -619,7 +496,7 @@ SK_IOC IoC) /* IO Context */ } if (r->p_val + r->p_len > pAC->vpd.vpd_buf + vpd_size/2) { - SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + SK_DBG_MSG(pAC, SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL, ("Encoding Error: Invalid VPD struct size\n")); return(1); } @@ -663,6 +540,7 @@ SK_IOC IoC) /* IO Context */ return(0); } + /* * find the Keyword 'key' in the VPD buffer and fills the * parameter struct 'p' with it's values @@ -673,7 +551,7 @@ SK_IOC IoC) /* IO Context */ static SK_VPD_PARA *vpd_find_para( SK_AC *pAC, /* common data base */ const char *key, /* keyword to find (e.g. "MN") */ -SK_VPD_PARA *p) /* parameter description struct */ +SK_VPD_PARA *p) /* parameter description struct */ { char *v ; /* points to VPD buffer */ int max; /* Maximum Number of Iterations */ @@ -691,7 +569,7 @@ SK_VPD_PARA *p) /* parameter description struct */ return(0); } - if (strcmp(key, VPD_NAME) == 0) { + if (SK_STRCMP(key, VPD_NAME) == 0) { p->p_len = VPD_GET_RES_LEN(v); p->p_val = VPD_GET_VAL(v); SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, @@ -701,7 +579,7 @@ SK_VPD_PARA *p) /* parameter description struct */ v += 3 + VPD_GET_RES_LEN(v) + 3; for (;; ) { - if (SK_MEMCMP(key,v,2) == 0) { + if (SK_MEMCMP(key, v, 2) == 0) { p->p_len = VPD_GET_VPD_LEN(v); p->p_val = VPD_GET_VAL(v); SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, @@ -711,11 +589,11 @@ SK_VPD_PARA *p) /* parameter description struct */ /* exit when reaching the "RW" Tag or the maximum of itera. */ max--; - if (SK_MEMCMP(VPD_RW,v,2) == 0 || max == 0) { + if (SK_MEMCMP(VPD_RW, v, 2) == 0 || max == 0) { break; } - if (SK_MEMCMP(VPD_RV,v,2) == 0) { + if (SK_MEMCMP(VPD_RV, v, 2) == 0) { v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */ } else { @@ -735,6 +613,7 @@ SK_VPD_PARA *p) /* parameter description struct */ return(0); } + /* * Move 'n' bytes. Begin with the last byte if 'n' is > 0, * Start with the last byte if n is < 0. @@ -769,6 +648,7 @@ int n) /* number of bytes the memory block has to be moved */ } } + /* * setup the VPD keyword 'key' at 'ip'. * @@ -785,10 +665,11 @@ char *ip) /* inseration point */ p = (SK_VPD_KEY *) ip; p->p_key[0] = key[0]; p->p_key[1] = key[1]; - p->p_len = (unsigned char) len; - SK_MEMCPY(&p->p_val,buf,len); + p->p_len = (unsigned char)len; + SK_MEMCPY(&p->p_val, buf, len); } + /* * Setup the VPD end tag "RV" / "RW". * Also correct the remaining space variables vpd_free_ro / vpd_free_rw. @@ -814,7 +695,7 @@ char *etp) /* end pointer input position */ if (p->p_key[0] != 'R' || (p->p_key[1] != 'V' && p->p_key[1] != 'W')) { /* something wrong here, encoding error */ - SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, ("Encoding Error: invalid end tag\n")); return(1); } @@ -846,6 +727,7 @@ char *etp) /* end pointer input position */ return(0); } + /* * Insert a VPD keyword into the VPD buffer. * @@ -1007,18 +889,18 @@ int *elements) /* number of keywords returned */ } } - if ((signed)strlen(VPD_NAME) + 1 <= *len) { + if ((signed)SK_STRLEN(VPD_NAME) + 1 <= *len) { v = pAC->vpd.vpd_buf; - strcpy(buf,VPD_NAME); - n = strlen(VPD_NAME) + 1; + SK_STRCPY(buf, VPD_NAME); + n = SK_STRLEN(VPD_NAME) + 1; buf += n; *elements = 1; SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, - ("'%c%c' ",v[0],v[1])); + ("'%c%c' ", v[0], v[1])); } else { *len = 0; - SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR, + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("buffer overflow\n")); return(2); } @@ -1026,17 +908,17 @@ int *elements) /* number of keywords returned */ v += 3 + VPD_GET_RES_LEN(v) + 3; for (;; ) { /* exit when reaching the "RW" Tag */ - if (SK_MEMCMP(VPD_RW,v,2) == 0) { + if (SK_MEMCMP(VPD_RW, v, 2) == 0) { break; } - if (SK_MEMCMP(VPD_RV,v,2) == 0) { + if (SK_MEMCMP(VPD_RV, v, 2) == 0) { v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */ continue; } if (n+3 <= *len) { - SK_MEMCPY(buf,v,2); + SK_MEMCPY(buf, v, 2); buf += 2; *buf++ = '\0'; n += 3; @@ -1123,13 +1005,14 @@ char *key) /* keyword to write (allowed values "Yx", "Vx") */ { if ((*key != 'Y' && *key != 'V') || key[1] < '0' || key[1] > 'Z' || - (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) { + (key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) { return(SK_FALSE); } return(SK_TRUE); } + /* * Read the contents of the VPD EEPROM and copy it to the VPD * buffer if not already done. Insert/overwrite the keyword 'key' @@ -1158,7 +1041,7 @@ const char *buf) /* buffer where the keyword value can be read from */ if ((*key != 'Y' && *key != 'V') || key[1] < '0' || key[1] > 'Z' || - (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) { + (key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) { SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("illegal key tag, keyword not written\n")); @@ -1174,13 +1057,13 @@ const char *buf) /* buffer where the keyword value can be read from */ } rtv = 0; - len = strlen(buf); + len = SK_STRLEN(buf); if (len > VPD_MAX_LEN) { /* cut it */ len = VPD_MAX_LEN; rtv = 2; SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, - ("keyword too long, cut after %d bytes\n",VPD_MAX_LEN)); + ("keyword too long, cut after %d bytes\n", VPD_MAX_LEN)); } if ((rtv2 = VpdSetupPara(pAC, key, buf, len, VPD_RW_KEY, OWR_KEY)) != 0) { SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, @@ -1191,6 +1074,7 @@ const char *buf) /* buffer where the keyword value can be read from */ return(rtv); } + /* * Read the contents of the VPD EEPROM and copy it to the * VPD buffer if not already done. Remove the VPD keyword @@ -1214,7 +1098,7 @@ char *key) /* keyword to read (e.g. "MN") */ vpd_size = pAC->vpd.vpd_size; - SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("VPD delete key %s\n",key)); + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("VPD delete key %s\n", key)); if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { if (VpdInit(pAC, IoC) != 0) { SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, @@ -1251,6 +1135,7 @@ char *key) /* keyword to read (e.g. "MN") */ return(0); } + /* * If the VPD buffer contains valid data write the VPD * read/write area back to the VPD EEPROM. @@ -1309,7 +1194,7 @@ char *msg) /* error log message */ } } - len = strlen(msg); + len = SK_STRLEN(msg); if (len > VPD_MAX_LEN) { /* cut it */ len = VPD_MAX_LEN; @@ -1326,4 +1211,4 @@ char *msg) /* error log message */ (void)VpdUpdate(pAC, IoC); } -#endif /* CONFIG_SK98 */ +#endif diff --git a/drivers/sk98lin/skxmac2.c b/drivers/sk98lin/skxmac2.c index e6b5a95..efc5f9f 100644 --- a/drivers/sk98lin/skxmac2.c +++ b/drivers/sk98lin/skxmac2.c @@ -1,417 +1,30 @@ /****************************************************************************** * * Name: skxmac2.c - * Project: GEnesis, PCI Gigabit Ethernet Adapter - * Version: $Revision: 1.91 $ - * Date: $Date: 2003/02/05 15:09:34 $ + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 2.56 $ + * Date: $Date: 2006/04/27 07:50:32 $ * Purpose: Contains functions to initialize the MACs and PHYs * ******************************************************************************/ /****************************************************************************** * - * (C)Copyright 1998-2003 SysKonnect GmbH. + * LICENSE: + * (C)Copyright 1998-2002 SysKonnect. + * (C)Copyright 2002-2006 Marvell. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * * The information in this file is provided "AS IS" without warranty. - * - ******************************************************************************/ - -/****************************************************************************** - * - * History: - * - * $Log: skxmac2.c,v $ - * Revision 1.91 2003/02/05 15:09:34 rschmidt - * Removed setting of 'Collision Test'-bit in SkGmInitPhyMarv(). - * Disabled auto-update for speed, duplex and flow-control when - * auto-negotiation is not enabled (Bug Id #10766). - * Editorial changes. - * - * Revision 1.90 2003/01/29 13:35:19 rschmidt - * Increment Rx FIFO Overflow counter only in DEBUG-mode. - * Corrected define for blinking active LED. - * - * Revision 1.89 2003/01/28 16:37:45 rschmidt - * Changed init for blinking active LED - * - * Revision 1.88 2003/01/28 10:09:38 rschmidt - * Added debug outputs in SkGmInitMac(). - * Added customized init of LED registers in SkGmInitPhyMarv(), - * for blinking active LED (#ifdef ACT_LED_BLINK) and - * for normal duplex LED (#ifdef DUP_LED_NORMAL). - * Editorial changes. - * - * Revision 1.87 2002/12/10 14:39:05 rschmidt - * Improved initialization of GPHY in SkGmInitPhyMarv(). - * Editorial changes. - * - * Revision 1.86 2002/12/09 15:01:12 rschmidt - * Added setup of Ext. PHY Specific Ctrl Reg (downshift feature). - * - * Revision 1.85 2002/12/05 14:09:16 rschmidt - * Improved avoiding endless loop in SkGmPhyWrite(), SkGmPhyWrite(). - * Added additional advertising for 10Base-T when 100Base-T is selected. - * Added case SK_PHY_MARV_FIBER for YUKON Fiber adapter. - * Editorial changes. - * - * Revision 1.84 2002/11/15 12:50:09 rschmidt - * Changed SkGmCableDiagStatus() when getting results. - * - * Revision 1.83 2002/11/13 10:28:29 rschmidt - * Added some typecasts to avoid compiler warnings. - * - * Revision 1.82 2002/11/13 09:20:46 rschmidt - * Replaced for(..) with do {} while (...) in SkXmUpdateStats(). - * Replaced 2 macros GM_IN16() with 1 GM_IN32() in SkGmMacStatistic(). - * Added SkGmCableDiagStatus() for Virtual Cable Test (VCT). - * Editorial changes. - * - * Revision 1.81 2002/10/28 14:28:08 rschmidt - * Changed MAC address setup for GMAC in SkGmInitMac(). - * Optimized handling of counter overflow IRQ in SkGmOverflowStatus(). - * Editorial changes. - * - * Revision 1.80 2002/10/14 15:29:44 rschmidt - * Corrected disabling of all PHY IRQs. - * Added WA for deviation #16 (address used for pause packets). - * Set Pause Mode in SkMacRxTxEnable() only for Genesis. - * Added IRQ and counter for Receive FIFO Overflow in DEBUG-mode. - * SkXmTimeStamp() replaced by SkMacTimeStamp(). - * Added clearing of GMAC Tx FIFO Underrun IRQ in SkGmIrq(). - * Editorial changes. - * - * Revision 1.79 2002/10/10 15:55:36 mkarl - * changes for PLinkSpeedUsed - * - * Revision 1.78 2002/09/12 09:39:51 rwahl - * Removed deactivate code for SIRQ overflow event separate for TX/RX. - * - * Revision 1.77 2002/09/09 12:26:37 mkarl - * added handling for Yukon to SkXmTimeStamp - * - * Revision 1.76 2002/08/21 16:41:16 rschmidt - * Added bit GPC_ENA_XC (Enable MDI crossover) in HWCFG_MODE. - * Added forced speed settings in SkGmInitPhyMarv(). - * Added settings of full/half duplex capabilities for YUKON Fiber. - * Editorial changes. - * - * Revision 1.75 2002/08/16 15:12:01 rschmidt - * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis. - * Added function SkMacHashing() for ADDR-Module. - * Removed functions SkXmClrSrcCheck(), SkXmClrHashAddr() (calls replaced - * with macros). - * Removed functions SkGmGetMuxConfig(). - * Added HWCFG_MODE init for YUKON Fiber. - * Changed initialization of GPHY in SkGmInitPhyMarv(). - * Changed check of parameter in SkXmMacStatistic(). - * Editorial changes. - * - * Revision 1.74 2002/08/12 14:00:17 rschmidt - * Replaced usage of Broadcom PHY Ids with defines. - * Corrected error messages in SkGmMacStatistic(). - * Made SkMacPromiscMode() public for ADDR-Modul. - * Editorial changes. - * - * Revision 1.73 2002/08/08 16:26:24 rschmidt - * Improved reset sequence for YUKON in SkGmHardRst() and SkGmInitMac(). - * Replaced XMAC Rx High Watermark init value with SK_XM_RX_HI_WM. - * Editorial changes. - * - * Revision 1.72 2002/07/24 15:11:19 rschmidt - * Fixed wrong placement of parenthesis. - * Editorial changes. - * - * Revision 1.71 2002/07/23 16:05:18 rschmidt - * Added global functions for PHY: SkGePhyRead(), SkGePhyWrite(). - * Fixed Tx Counter Overflow IRQ (Bug ID #10730). - * Editorial changes. - * - * Revision 1.70 2002/07/18 14:27:27 rwahl - * Fixed syntax error. - * - * Revision 1.69 2002/07/17 17:08:47 rwahl - * Fixed check in SkXmMacStatistic(). - * - * Revision 1.68 2002/07/16 07:35:24 rwahl - * Removed check for cleared mib counter in SkGmResetCounter(). - * - * Revision 1.67 2002/07/15 18:35:56 rwahl - * Added SkXmUpdateStats(), SkGmUpdateStats(), SkXmMacStatistic(), - * SkGmMacStatistic(), SkXmResetCounter(), SkGmResetCounter(), - * SkXmOverflowStatus(), SkGmOverflowStatus(). - * Changes to SkXmIrq() & SkGmIrq(): Combined SIRQ Overflow for both - * RX & TX. - * Changes to SkGmInitMac(): call to SkGmResetCounter(). - * Editorial changes. - * - * Revision 1.66 2002/07/15 15:59:30 rschmidt - * Added PHY Address in SkXmPhyRead(), SkXmPhyWrite(). - * Added MIB Clear Counter in SkGmInitMac(). - * Added Duplex and Flow-Control settings. - * Reset all Multicast filtering Hash reg. in SkGmInitMac(). - * Added new function: SkGmGetMuxConfig(). - * Editorial changes. - * - * Revision 1.65 2002/06/10 09:35:39 rschmidt - * Replaced C++ comments (//). - * Added #define VCPU around VCPUwaitTime. - * Editorial changes. - * - * Revision 1.64 2002/06/05 08:41:10 rschmidt - * Added function for XMAC2: SkXmTimeStamp(). - * Added function for YUKON: SkGmSetRxCmd(). - * Changed SkGmInitMac() resp. SkGmHardRst(). - * Fixed wrong variable in SkXmAutoNegLipaXmac() (debug mode). - * SkXmRxTxEnable() replaced by SkMacRxTxEnable(). - * Editorial changes. - * - * Revision 1.63 2002/04/25 13:04:44 rschmidt - * Changes for handling YUKON. - * Use of #ifdef OTHER_PHY to eliminate code for unused Phy types. - * Macros for XMAC PHY access PHY_READ(), PHY_WRITE() replaced - * by functions SkXmPhyRead(), SkXmPhyWrite(); - * Removed use of PRxCmd to setup XMAC. - * Added define PHY_B_AS_PAUSE_MSK for BCom Pause Res. - * Added setting of XM_RX_DIS_CEXT in SkXmInitMac(). - * Removed status parameter from MAC IRQ handler SkMacIrq(), - * SkXmIrq() and SkGmIrq(). - * SkXmAutoNegLipa...() for ext. Phy replaced by SkMacAutoNegLipaPhy(). - * Added SkMac...() functions to handle both XMAC and GMAC. - * Added functions for YUKON: SkGmHardRst(), SkGmSoftRst(), - * SkGmSetRxTxEn(), SkGmIrq(), SkGmInitMac(), SkGmInitPhyMarv(), - * SkGmAutoNegDoneMarv(), SkGmPhyRead(), SkGmPhyWrite(). - * Changes for V-CPU support. - * Editorial changes. - * - * Revision 1.62 2001/08/06 09:50:14 rschmidt - * Workaround BCOM Errata #1 for the C5 type. - * Editorial changes. - * - * Revision 1.61 2001/02/09 15:40:59 rassmann - * Editorial changes. - * - * Revision 1.60 2001/02/07 15:02:01 cgoos - * Added workaround for Fujitsu switch link down. - * - * Revision 1.59 2001/01/10 09:38:06 cgoos - * Fixed Broadcom C0/A1 Id check for workaround. - * - * Revision 1.58 2000/11/29 11:30:38 cgoos - * Changed DEBUG sections with NW output to xDEBUG - * - * Revision 1.57 2000/11/27 12:40:40 rassmann - * Suppressing preamble after first access to BCom, not before (#10556). - * - * Revision 1.56 2000/11/09 12:32:48 rassmann - * Renamed variables. - * - * Revision 1.55 2000/11/09 11:30:10 rassmann - * WA: Waiting after releasing reset until BCom chip is accessible. - * - * Revision 1.54 2000/10/02 14:10:27 rassmann - * Reading BCOM PHY after releasing reset until it returns a valid value. - * - * Revision 1.53 2000/07/27 12:22:11 gklug - * fix: possible endless loop in XmHardRst. - * - * Revision 1.52 2000/05/22 08:48:31 malthoff - * Fix: #10523 errata valid for all BCOM PHYs. - * - * Revision 1.51 2000/05/17 12:52:18 malthoff - * Fixes BCom link errata (#10523). - * - * Revision 1.50 1999/11/22 13:40:14 cgoos - * Changed license header to GPL. - * - * Revision 1.49 1999/11/22 08:12:13 malthoff - * Add workaround for power consumption feature of BCom C0 chip. - * - * Revision 1.48 1999/11/16 08:39:01 malthoff - * Fix: MDIO preamble suppression is port dependent. - * - * Revision 1.47 1999/08/27 08:55:35 malthoff - * 1000BT: Optimizing MDIO transfer by oppressing MDIO preamble. - * - * Revision 1.46 1999/08/13 11:01:12 malthoff - * Fix for 1000BT: pFlowCtrlMode was not set correctly. - * - * Revision 1.45 1999/08/12 19:18:28 malthoff - * 1000BT Fixes: Do not owerwrite XM_MMU_CMD. - * Do not execute BCOM A1 workaround for B1 chips. - * Fix pause frame setting. - * Always set PHY_B_AC_TX_TST in PHY_BCOM_AUX_CTRL. - * - * Revision 1.44 1999/08/03 15:23:48 cgoos - * Fixed setting of PHY interrupt mask in half duplex mode. - * - * Revision 1.43 1999/08/03 15:22:17 cgoos - * Added some debug output. - * Disabled XMac GP0 interrupt for external PHYs. - * - * Revision 1.42 1999/08/02 08:39:23 malthoff - * BCOM PHY: TX LED: To get the mono flop behaviour it is required - * to set the LED Traffic Mode bit in PHY_BCOM_P_EXT_CTRL. - * - * Revision 1.41 1999/07/30 06:54:31 malthoff - * Add temp. workarounds for the BCOM Phy revision A1. - * - * Revision 1.40 1999/06/01 07:43:26 cgoos - * Changed Link Mode Status in SkXmAutoNegDone... from FULL/HALF to - * AUTOFULL/AUTOHALF. - * - * Revision 1.39 1999/05/19 07:29:51 cgoos - * Changes for 1000Base-T. - * - * Revision 1.38 1999/04/08 14:35:10 malthoff - * Add code for enabling signal detect. Enabling signal detect is disabled. - * - * Revision 1.37 1999/03/12 13:42:54 malthoff - * Add: Jumbo Frame Support. - * Add: Receive modes SK_LENERR_OK_ON/OFF and - * SK_BIG_PK_OK_ON/OFF in SkXmSetRxCmd(). - * - * Revision 1.36 1999/03/08 10:10:55 gklug - * fix: AutoSensing did switch to next mode even if LiPa indicated offline - * - * Revision 1.35 1999/02/22 15:16:41 malthoff - * Remove some compiler warnings. - * - * Revision 1.34 1999/01/22 09:19:59 gklug - * fix: Init DupMode and InitPauseMd are now called in RxTxEnable - * - * Revision 1.33 1998/12/11 15:19:11 gklug - * chg: lipa autoneg stati - * chg: debug messages - * chg: do NOT use spurious XmIrq - * - * Revision 1.32 1998/12/10 11:08:44 malthoff - * bug fix: pAC has been used for IOs in SkXmHardRst(). - * SkXmInitPhy() is also called for the Diag in SkXmInitMac(). - * - * Revision 1.31 1998/12/10 10:39:11 gklug - * fix: do 4 RESETS of the XMAC at the beginning - * fix: dummy read interrupt source register BEFORE initializing the Phy - * add: debug messages - * fix: Linkpartners autoneg capability cannot be shown by TX_PAGE interrupt - * - * Revision 1.30 1998/12/07 12:18:32 gklug - * add: refinement of autosense mode: take into account the autoneg cap of LiPa - * - * Revision 1.29 1998/12/07 07:12:29 gklug - * fix: if page is received the link is down. - * - * Revision 1.28 1998/12/01 10:12:47 gklug - * chg: if spurious IRQ from XMAC encountered, save it - * - * Revision 1.27 1998/11/26 07:33:38 gklug - * add: InitPhy call is now in XmInit function - * - * Revision 1.26 1998/11/18 13:38:24 malthoff - * 'Imsk' is also unused in SkXmAutoNegDone. - * - * Revision 1.25 1998/11/18 13:28:01 malthoff - * Remove unused variable 'Reg' in SkXmAutoNegDone(). - * - * Revision 1.24 1998/11/18 13:18:45 gklug - * add: workaround for xmac errata #1 - * add: detect Link Down also when Link partner requested config - * chg: XMIrq is only used when link is up - * - * Revision 1.23 1998/11/04 07:07:04 cgoos - * Added function SkXmRxTxEnable. - * - * Revision 1.22 1998/10/30 07:35:54 gklug - * fix: serve LinkDown interrupt when link is already down - * - * Revision 1.21 1998/10/29 15:32:03 gklug - * fix: Link Down signaling - * - * Revision 1.20 1998/10/29 11:17:27 gklug - * fix: AutoNegDone bug - * - * Revision 1.19 1998/10/29 10:14:43 malthoff - * Add endainesss comment for reading/writing MAC addresses. - * - * Revision 1.18 1998/10/28 07:48:55 cgoos - * Fix: ASS somtimes signaled although link is up. - * - * Revision 1.17 1998/10/26 07:55:39 malthoff - * Fix in SkXmInitPauseMd(): Pause Mode - * was disabled and not enabled. - * Fix in SkXmAutoNegDone(): Checking Mode bits - * always failed, becaues of some missing braces. - * - * Revision 1.16 1998/10/22 09:46:52 gklug - * fix SysKonnectFileId typo - * - * Revision 1.15 1998/10/21 05:51:37 gklug - * add: para DoLoop to InitPhy function for loopback set-up - * - * Revision 1.14 1998/10/16 10:59:23 malthoff - * Remove Lint warning for dummy reads. - * - * Revision 1.13 1998/10/15 14:01:20 malthoff - * Fix: SkXmAutoNegDone() is (int) but does not return a value. - * - * Revision 1.12 1998/10/14 14:45:04 malthoff - * Remove SKERR_SIRQ_E0xx and SKERR_SIRQ_E0xxMSG by - * SKERR_HWI_Exx and SKERR_HWI_E0xxMSG to be independent - * from the Sirq module. - * - * Revision 1.11 1998/10/14 13:59:01 gklug - * add: InitPhy function - * - * Revision 1.10 1998/10/14 11:20:57 malthoff - * Make SkXmAutoNegDone() public, because it's - * used in diagnostics, too. - * The Link Up event to the RLMT is issued in SkXmIrq(). - * SkXmIrq() is not available in diagnostics. - * Use PHY_READ when reading PHY registers. - * - * Revision 1.9 1998/10/14 05:50:10 cgoos - * Added definition for Para. - * - * Revision 1.8 1998/10/14 05:41:28 gklug - * add: Xmac IRQ - * add: auto-negotiation done function - * - * Revision 1.7 1998/10/09 06:55:20 malthoff - * The configuration of the XMACs Tx Request Threshold - * depends from the drivers port usage now. The port - * usage is configured in GIPortUsage. - * - * Revision 1.6 1998/10/05 07:48:00 malthoff - * minor changes - * - * Revision 1.5 1998/10/01 07:03:54 gklug - * add: dummy function for XMAC ISR - * - * Revision 1.4 1998/09/30 12:37:44 malthoff - * Add SkXmSetRxCmd() and related code. - * - * Revision 1.3 1998/09/28 13:26:40 malthoff - * Add SkXmInitMac(), SkXmInitDupMd(), and SkXmInitPauseMd() - * - * Revision 1.2 1998/09/16 14:34:21 malthoff - * Add SkXmClrExactAddr(), SkXmClrSrcCheck(), - * SkXmClrHashAddr(), SkXmFlushTxFifo(), - * SkXmFlushRxFifo(), and SkXmHardRst(). - * Finish Coding of SkXmSoftRst(). - * The sources may be compiled now. - * - * Revision 1.1 1998/09/04 10:05:56 malthoff - * Created. - * + * /LICENSE * ******************************************************************************/ #include - + #ifdef CONFIG_SK98 #include "h/skdrv1st.h" @@ -421,14 +34,18 @@ /* BCOM PHY magic pattern list */ typedef struct s_PhyHack { - int PhyReg; /* Phy register */ + int PhyReg; /* PHY register */ SK_U16 PhyVal; /* Value to write */ } BCOM_HACK; /* local variables ************************************************************/ -static const char SysKonnectFileId[] = - "@(#)$Id: skxmac2.c,v 1.91 2003/02/05 15:09:34 rschmidt Exp $ (C) SK "; +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) +static const char SysKonnectFileId[] = + "@(#) $Id: skxmac2.c,v 2.56 2006/04/27 07:50:32 malthoff Exp $ (C) Marvell."; +#endif + +#ifdef GENESIS BCOM_HACK BcomRegA1Hack[] = { { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, @@ -440,14 +57,19 @@ BCOM_HACK BcomRegC0Hack[] = { { 0x15, 0x0A04 }, { 0x18, 0x0420 }, { 0, 0 } }; +#endif /* function prototypes ********************************************************/ +#ifdef GENESIS static void SkXmInitPhyXmac(SK_AC*, SK_IOC, int, SK_BOOL); static void SkXmInitPhyBcom(SK_AC*, SK_IOC, int, SK_BOOL); -static void SkGmInitPhyMarv(SK_AC*, SK_IOC, int, SK_BOOL); static int SkXmAutoNegDoneXmac(SK_AC*, SK_IOC, int); static int SkXmAutoNegDoneBcom(SK_AC*, SK_IOC, int); +#endif /* GENESIS */ +#ifdef YUKON +static void SkGmInitPhyMarv(SK_AC*, SK_IOC, int, SK_BOOL); static int SkGmAutoNegDoneMarv(SK_AC*, SK_IOC, int); +#endif /* YUKON */ #ifdef OTHER_PHY static void SkXmInitPhyLone(SK_AC*, SK_IOC, int, SK_BOOL); static void SkXmInitPhyNat (SK_AC*, SK_IOC, int, SK_BOOL); @@ -456,6 +78,7 @@ static int SkXmAutoNegDoneNat (SK_AC*, SK_IOC, int); #endif /* OTHER_PHY */ +#ifdef GENESIS /****************************************************************************** * * SkXmPhyRead() - Read from XMAC PHY register @@ -465,12 +88,12 @@ static int SkXmAutoNegDoneNat (SK_AC*, SK_IOC, int); * Returns: * nothing */ -void SkXmPhyRead( -SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* I/O Context */ -int Port, /* Port Index (MAC_1 + n) */ -int PhyReg, /* Register Address (Offset) */ -SK_U16 *pVal) /* Pointer to Value */ +int SkXmPhyRead( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 SK_FAR *pVal) /* Pointer to Value */ { SK_U16 Mmu; SK_GEPORT *pPrt; @@ -492,6 +115,8 @@ SK_U16 *pVal) /* Pointer to Value */ /* get the PHY register's value */ XM_IN16(IoC, Port, XM_PHY_DATA, pVal); } + + return(0); } /* SkXmPhyRead */ @@ -504,7 +129,7 @@ SK_U16 *pVal) /* Pointer to Value */ * Returns: * nothing */ -void SkXmPhyWrite( +int SkXmPhyWrite( SK_AC *pAC, /* Adapter Context */ SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ @@ -535,9 +160,13 @@ SK_U16 Val) /* Value */ /* wait until 'Busy' is cleared */ } while ((Mmu & XM_MMU_PHY_BUSY) != 0); } + + return(0); } /* SkXmPhyWrite */ +#endif /* GENESIS */ +#ifdef YUKON /****************************************************************************** * * SkGmPhyRead() - Read from GPHY register @@ -545,62 +174,97 @@ SK_U16 Val) /* Value */ * Description: reads a 16-bit word from GPHY through MDIO * * Returns: - * nothing + * 0 o.k. + * 1 error during MDIO read + * 2 timeout */ -void SkGmPhyRead( -SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* I/O Context */ -int Port, /* Port Index (MAC_1 + n) */ -int PhyReg, /* Register Address (Offset) */ -SK_U16 *pVal) /* Pointer to Value */ +int SkGmPhyRead( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 SK_FAR *pVal) /* Pointer to Value */ { + SK_U16 Word; SK_U16 Ctrl; SK_GEPORT *pPrt; -#ifdef VCPU - u_long SimCyle; - u_long SimLowTime; + SK_U32 StartTime; + SK_U32 CurrTime; + SK_U32 Delta; + SK_U32 TimeOut; + int Rtv; - VCPUgetTime(&SimCyle, &SimLowTime); - VCPUprintf(0, "SkGmPhyRead(%u), SimCyle=%u, SimLowTime=%u\n", - PhyReg, SimCyle, SimLowTime); -#endif /* VCPU */ + Rtv = 0; + + *pVal = 0xffff; pPrt = &pAC->GIni.GP[Port]; /* set PHY-Register offset and 'Read' OpCode (= 1) */ - *pVal = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | + Word = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | GM_SMI_CT_REG_AD(PhyReg) | GM_SMI_CT_OP_RD); - GM_OUT16(IoC, Port, GM_SMI_CTRL, *pVal); - - GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); + GM_OUT16(IoC, Port, GM_SMI_CTRL, Word); /* additional check for MDC/MDIO activity */ - if ((Ctrl & GM_SMI_CT_BUSY) == 0) { - *pVal = 0; - return; + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); + + if (Ctrl == 0xffff || (Ctrl & GM_SMI_CT_OP_RD) == 0) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("PHY read impossible on Port %d (Ctrl=0x%04x)\n", Port, Ctrl)); + + return(1); } - *pVal |= GM_SMI_CT_BUSY; + Word |= GM_SMI_CT_BUSY; - do { + SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime); + + /* set timeout to 10 ms */ + TimeOut = HW_MS_TO_TICKS(pAC, 10); + + do { /* wait until 'Busy' is cleared and 'ReadValid' is set */ #ifdef VCPU VCPUwaitTime(1000); #endif /* VCPU */ + SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime); + + if (CurrTime >= StartTime) { + Delta = CurrTime - StartTime; + } + else { + Delta = CurrTime + ~StartTime + 1; + } + + if (Delta > TimeOut) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("PHY read timeout on Port %d (Ctrl=0x%04x)\n", Port, Ctrl)); + Rtv = 2; + break; + } + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); - /* wait until 'ReadValid' is set */ - } while (Ctrl == *pVal); + /* Error on reading SMI Control Register */ + if (Ctrl == 0xffff) { + return(1); + } + + } while ((Ctrl ^ Word) != (GM_SMI_CT_RD_VAL | GM_SMI_CT_BUSY)); - /* get the PHY register's value */ GM_IN16(IoC, Port, GM_SMI_DATA, pVal); -#ifdef VCPU - VCPUgetTime(&SimCyle, &SimLowTime); - VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n", - SimCyle, SimLowTime); -#endif /* VCPU */ + /* dummy read after GM_IN16() */ + SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("SkGmPhyRead Port:%d, Reg=%d, Val = 0x%04X\n", + Port, PhyReg, *pVal)); + + return(Rtv); } /* SkGmPhyRead */ @@ -611,9 +275,11 @@ SK_U16 *pVal) /* Pointer to Value */ * Description: writes a 16-bit word to GPHY through MDIO * * Returns: - * nothing + * 0 o.k. + * 1 error during MDIO read + * 2 timeout */ -void SkGmPhyWrite( +int SkGmPhyWrite( SK_AC *pAC, /* Adapter Context */ SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ @@ -622,56 +288,83 @@ SK_U16 Val) /* Value */ { SK_U16 Ctrl; SK_GEPORT *pPrt; -#ifdef VCPU - SK_U32 DWord; - u_long SimCyle; - u_long SimLowTime; + SK_U32 StartTime; + SK_U32 CurrTime; + SK_U32 Delta; + SK_U32 TimeOut; - VCPUgetTime(&SimCyle, &SimLowTime); - VCPUprintf(0, "SkGmPhyWrite(Reg=%u, Val=0x%04x), SimCyle=%u, SimLowTime=%u\n", - PhyReg, Val, SimCyle, SimLowTime); -#endif /* VCPU */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("SkGmPhyWrite Port:%d, Reg=%d, Val = 0x%04X\n", + Port, PhyReg, Val)); pPrt = &pAC->GIni.GP[Port]; /* write the PHY register's value */ GM_OUT16(IoC, Port, GM_SMI_DATA, Val); - /* set PHY-Register offset and 'Write' OpCode (= 0) */ - Val = GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | GM_SMI_CT_REG_AD(PhyReg); - - GM_OUT16(IoC, Port, GM_SMI_CTRL, Val); - - GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); - +#ifdef DEBUG /* additional check for MDC/MDIO activity */ - if ((Ctrl & GM_SMI_CT_BUSY) == 0) { - return; + GM_IN16(IoC, Port, GM_SMI_DATA, &Ctrl); + + if (Ctrl != Val) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("PHY write impossible on Port %d (Val=0x%04x)\n", Port, Ctrl)); + + return(1); } +#endif /* DEBUG */ - Val |= GM_SMI_CT_BUSY; + /* set PHY-Register offset and 'Write' OpCode (= 0) */ + Ctrl = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | + GM_SMI_CT_REG_AD(PhyReg)); - do { + GM_OUT16(IoC, Port, GM_SMI_CTRL, Ctrl); + + SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime); + + /* set timeout to 10 ms */ + TimeOut = HW_MS_TO_TICKS(pAC, 10); + + do { /* wait until 'Busy' is cleared */ #ifdef VCPU - /* read Timer value */ - SK_IN32(IoC, B2_TI_VAL, &DWord); - VCPUwaitTime(1000); #endif /* VCPU */ + SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime); + + if (CurrTime >= StartTime) { + Delta = CurrTime - StartTime; + } + else { + Delta = CurrTime + ~StartTime + 1; + } + + if (Delta > TimeOut) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("PHY write timeout on Port %d (Ctrl=0x%04x)\n", Port, Ctrl)); + return(2); + } + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); - /* wait until 'Busy' is cleared */ - } while (Ctrl == Val); + /* Error on reading SMI Control Register */ + if (Ctrl == 0xffff) { + return(1); + } -#ifdef VCPU - VCPUgetTime(&SimCyle, &SimLowTime); - VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n", - SimCyle, SimLowTime); -#endif /* VCPU */ + } while ((Ctrl & GM_SMI_CT_BUSY) != 0); + + /* dummy read after GM_IN16() */ + SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime); + + return(0); } /* SkGmPhyWrite */ +#endif /* YUKON */ +#ifdef SK_DIAG /****************************************************************************** * * SkGePhyRead() - Read from PHY register @@ -688,16 +381,8 @@ int Port, /* Port Index (MAC_1 + n) */ int PhyReg, /* Register Address (Offset) */ SK_U16 *pVal) /* Pointer to Value */ { - void (*r_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 *pVal); - if (pAC->GIni.GIGenesis) { - r_func = SkXmPhyRead; - } - else { - r_func = SkGmPhyRead; - } - - r_func(pAC, IoC, Port, PhyReg, pVal); + pAC->GIni.GIFunc.pFnMacPhyRead(pAC, IoC, Port, PhyReg, pVal); } /* SkGePhyRead */ @@ -717,17 +402,10 @@ int Port, /* Port Index (MAC_1 + n) */ int PhyReg, /* Register Address (Offset) */ SK_U16 Val) /* Value */ { - void (*w_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 Val); - if (pAC->GIni.GIGenesis) { - w_func = SkXmPhyWrite; - } - else { - w_func = SkGmPhyWrite; - } - - w_func(pAC, IoC, Port, PhyReg, Val); + pAC->GIni.GIFunc.pFnMacPhyWrite(pAC, IoC, Port, PhyReg, Val); } /* SkGePhyWrite */ +#endif /* SK_DIAG */ /****************************************************************************** @@ -735,21 +413,26 @@ SK_U16 Val) /* Value */ * SkMacPromiscMode() - Enable / Disable Promiscuous Mode * * Description: - * enables / disables promiscuous mode by setting Mode Register (XMAC) or - * Receive Control Register (GMAC) dep. on board type + * enables / disables promiscuous mode by setting Mode Register (XMAC) or + * Receive Control Register (GMAC) dep. on board type * * Returns: * nothing */ void SkMacPromiscMode( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_BOOL Enable) /* Enable / Disable */ { +#ifdef YUKON SK_U16 RcReg; +#endif +#ifdef GENESIS SK_U32 MdReg; +#endif +#ifdef GENESIS if (pAC->GIni.GIGenesis) { XM_IN32(IoC, Port, XM_MODE, &MdReg); @@ -763,7 +446,10 @@ SK_BOOL Enable) /* Enable / Disable */ /* setup Mode Register */ XM_OUT32(IoC, Port, XM_MODE, MdReg); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg); @@ -777,6 +463,8 @@ SK_BOOL Enable) /* Enable / Disable */ /* setup Receive Control Register */ GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg); } +#endif /* YUKON */ + } /* SkMacPromiscMode*/ @@ -785,21 +473,26 @@ SK_BOOL Enable) /* Enable / Disable */ * SkMacHashing() - Enable / Disable Hashing * * Description: - * enables / disables hashing by setting Mode Register (XMAC) or - * Receive Control Register (GMAC) dep. on board type + * enables / disables hashing by setting Mode Register (XMAC) or + * Receive Control Register (GMAC) dep. on board type * * Returns: * nothing */ void SkMacHashing( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_BOOL Enable) /* Enable / Disable */ { +#ifdef YUKON SK_U16 RcReg; +#endif +#ifdef GENESIS SK_U32 MdReg; +#endif +#ifdef GENESIS if (pAC->GIni.GIGenesis) { XM_IN32(IoC, Port, XM_MODE, &MdReg); @@ -813,7 +506,10 @@ SK_BOOL Enable) /* Enable / Disable */ /* setup Mode Register */ XM_OUT32(IoC, Port, XM_MODE, MdReg); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg); @@ -827,6 +523,8 @@ SK_BOOL Enable) /* Enable / Disable */ /* setup Receive Control Register */ GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg); } +#endif /* YUKON */ + } /* SkMacHashing*/ @@ -842,8 +540,8 @@ SK_BOOL Enable) /* Enable / Disable */ * - don't set XMR_FS_ERR in status SK_LENERR_OK_ON/OFF * for inrange length error frames * - don't set XMR_FS_ERR in status SK_BIG_PK_OK_ON/OFF - * for frames > 1514 bytes - * - enable Rx of own packets SK_SELF_RX_ON/OFF + * for frames > 1514 bytes + * - enable Rx of own packets SK_SELF_RX_ON/OFF * * for incoming packets may be enabled/disabled by this function. * Additional modes may be added later. @@ -854,11 +552,11 @@ SK_BOOL Enable) /* Enable / Disable */ * nothing */ static void SkXmSetRxCmd( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF, - SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */ + SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */ { SK_U16 OldRxCmd; SK_U16 RxCmd; @@ -927,8 +625,8 @@ int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF, * The features * - FCS (CRC) stripping, SK_STRIP_FCS_ON/OFF * - don't set GMR_FS_LONG_ERR SK_BIG_PK_OK_ON/OFF - * for frames > 1514 bytes - * - enable Rx of own packets SK_SELF_RX_ON/OFF + * for frames > 1514 bytes + * - enable Rx of own packets SK_SELF_RX_ON/OFF * * for incoming packets may be enabled/disabled by this function. * Additional modes may be added later. @@ -939,20 +637,17 @@ int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF, * nothing */ static void SkGmSetRxCmd( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF, - SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */ + SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */ { - SK_U16 OldRxCmd; SK_U16 RxCmd; if ((Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) != 0) { - GM_IN16(IoC, Port, GM_RX_CTRL, &OldRxCmd); - - RxCmd = OldRxCmd; + GM_IN16(IoC, Port, GM_RX_CTRL, &RxCmd); if ((Mode & SK_STRIP_FCS_ON) != 0) { RxCmd |= GM_RXCR_CRC_DIS; @@ -960,17 +655,13 @@ int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF, else { RxCmd &= ~GM_RXCR_CRC_DIS; } - /* Write the new mode to the Rx control register if required */ - if (OldRxCmd != RxCmd) { - GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd); - } + /* Write the new mode to the Rx Control register */ + GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd); } if ((Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) != 0) { - GM_IN16(IoC, Port, GM_SERIAL_MODE, &OldRxCmd); - - RxCmd = OldRxCmd; + GM_IN16(IoC, Port, GM_SERIAL_MODE, &RxCmd); if ((Mode & SK_BIG_PK_OK_ON) != 0) { RxCmd |= GM_SMOD_JUMBO_ENA; @@ -978,10 +669,8 @@ int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF, else { RxCmd &= ~GM_SMOD_JUMBO_ENA; } - /* Write the new mode to the Rx control register if required */ - if (OldRxCmd != RxCmd) { - GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd); - } + /* Write the new mode to the Serial Mode register */ + GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd); } } /* SkGmSetRxCmd */ @@ -996,8 +685,8 @@ int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF, * nothing */ void SkMacSetRxCmd( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ int Mode) /* Rx Mode */ { @@ -1009,6 +698,7 @@ int Mode) /* Rx Mode */ SkGmSetRxCmd(pAC, IoC, Port, Mode); } + } /* SkMacSetRxCmd */ @@ -1022,8 +712,8 @@ int Mode) /* Rx Mode */ * nothing */ void SkMacCrcGener( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_BOOL Enable) /* Enable / Disable */ { @@ -1040,7 +730,7 @@ SK_BOOL Enable) /* Enable / Disable */ Word |= XM_TX_NO_CRC; } /* setup Tx Command Register */ - XM_OUT16(pAC, Port, XM_TX_CMD, Word); + XM_OUT16(IoC, Port, XM_TX_CMD, Word); } else { @@ -1055,11 +745,13 @@ SK_BOOL Enable) /* Enable / Disable */ /* setup Tx Control Register */ GM_OUT16(IoC, Port, GM_TX_CTRL, Word); } + } /* SkMacCrcGener*/ #endif /* SK_DIAG */ +#ifdef GENESIS /****************************************************************************** * * SkXmClrExactAddr() - Clear Exact Match Address Registers @@ -1073,14 +765,14 @@ SK_BOOL Enable) /* Enable / Disable */ * nothing */ void SkXmClrExactAddr( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ int StartNum, /* Begin with this Address Register Index (0..15) */ int StopNum) /* Stop after finished with this Register Idx (0..15) */ { int i; - SK_U16 ZeroAddr[3] = {0x0000, 0x0000, 0x0000}; + SK_U16 ZeroAddr[3] = {0, 0, 0}; if ((unsigned)StartNum > 15 || (unsigned)StopNum > 15 || StartNum > StopNum) { @@ -1090,9 +782,10 @@ int StopNum) /* Stop after finished with this Register Idx (0..15) */ } for (i = StartNum; i <= StopNum; i++) { - XM_OUTADDR(IoC, Port, XM_EXM(i), &ZeroAddr[0]); + XM_OUTADDR(IoC, Port, XM_EXM(i), ZeroAddr); } } /* SkXmClrExactAddr */ +#endif /* GENESIS */ /****************************************************************************** @@ -1106,10 +799,11 @@ int StopNum) /* Stop after finished with this Register Idx (0..15) */ * nothing */ void SkMacFlushTxFifo( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { +#ifdef GENESIS SK_U32 MdReg; if (pAC->GIni.GIGenesis) { @@ -1118,10 +812,15 @@ int Port) /* Port Index (MAC_1 + n) */ XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FTF); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { /* no way to flush the FIFO we have to issue a reset */ /* TBD */ } +#endif /* YUKON */ + } /* SkMacFlushTxFifo */ @@ -1136,10 +835,11 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ void SkMacFlushRxFifo( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { +#ifdef GENESIS SK_U32 MdReg; if (pAC->GIni.GIGenesis) { @@ -1148,13 +848,19 @@ int Port) /* Port Index (MAC_1 + n) */ XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FRF); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { /* no way to flush the FIFO we have to issue a reset */ /* TBD */ } +#endif /* YUKON */ + } /* SkMacFlushRxFifo */ +#ifdef GENESIS /****************************************************************************** * * SkXmSoftRst() - Do a XMAC software reset @@ -1191,11 +897,11 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ static void SkXmSoftRst( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { - SK_U16 ZeroAddr[4] = {0x0000, 0x0000, 0x0000, 0x0000}; + SK_U16 ZeroAddr[4] = {0, 0, 0, 0}; /* reset the statistics module */ XM_OUT32(IoC, Port, XM_GP_PORT, XM_GP_RES_STAT); @@ -1225,13 +931,13 @@ int Port) /* Port Index (MAC_1 + n) */ } /* clear the Hash Register */ - XM_OUTHASH(IoC, Port, XM_HSM, &ZeroAddr); + XM_OUTHASH(IoC, Port, XM_HSM, ZeroAddr); /* clear the Exact Match Address registers */ SkXmClrExactAddr(pAC, IoC, Port, 0, 15); /* clear the Source Check Address registers */ - XM_OUTHASH(IoC, Port, XM_SRC_CHK, &ZeroAddr); + XM_OUTHASH(IoC, Port, XM_SRC_CHK, ZeroAddr); } /* SkXmSoftRst */ @@ -1243,7 +949,7 @@ int Port) /* Port Index (MAC_1 + n) */ * Description: * The XMAC of the specified 'Port' and all connected devices * (PHY and SERDES) will receive a reset signal on its *Reset pins. - * External PHYs must be reset be clearing a bit in the GPIO register + * External PHYs must be reset by clearing a bit in the GPIO register * (Timing requirements: Broadcom: 400ns, Level One: none, National: 80ns). * * ATTENTION: @@ -1254,8 +960,8 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ static void SkXmHardRst( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_U32 Reg; @@ -1286,25 +992,66 @@ int Port) /* Port Index (MAC_1 + n) */ /* For external PHYs there must be special handling */ if (pAC->GIni.GP[Port].PhyType != SK_PHY_XMAC) { - /* reset external PHY */ + SK_IN32(IoC, B2_GP_IO, &Reg); + if (Port == 0) { - Reg |= GP_DIR_0; /* set to output */ - Reg &= ~GP_IO_0; + Reg |= GP_DIR_0; /* set to output */ + Reg &= ~GP_IO_0; /* set PHY reset (active low) */ } else { - Reg |= GP_DIR_2; /* set to output */ - Reg &= ~GP_IO_2; + Reg |= GP_DIR_2; /* set to output */ + Reg &= ~GP_IO_2; /* set PHY reset (active low) */ } + /* reset external PHY */ SK_OUT32(IoC, B2_GP_IO, Reg); /* short delay */ SK_IN32(IoC, B2_GP_IO, &Reg); } - } /* SkXmHardRst */ +/****************************************************************************** + * + * SkXmClearRst() - Release the PHY & XMAC reset + * + * Description: + * + * Returns: + * nothing + */ +static void SkXmClearRst( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U32 DWord; + + /* clear HW reset */ + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); + + if (pAC->GIni.GP[Port].PhyType != SK_PHY_XMAC) { + + SK_IN32(IoC, B2_GP_IO, &DWord); + + if (Port == 0) { + DWord |= (GP_DIR_0 | GP_IO_0); /* set to output */ + } + else { + DWord |= (GP_DIR_2 | GP_IO_2); /* set to output */ + } + /* Clear PHY reset */ + SK_OUT32(IoC, B2_GP_IO, DWord); + + /* enable GMII interface */ + XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_GMII_MD); + } +} /* SkXmClearRst */ +#endif /* GENESIS */ + + +#ifdef YUKON /****************************************************************************** * * SkGmSoftRst() - Do a GMAC software reset @@ -1317,17 +1064,17 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ static void SkGmSoftRst( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { - SK_U16 EmptyHash[4] = {0x0000, 0x0000, 0x0000, 0x0000}; - SK_U16 RxCtrl; + SK_U16 EmptyHash[4] = { 0x0000, 0x0000, 0x0000, 0x0000 }; + SK_U16 RxCtrl; /* reset the statistics module */ /* disable all GMAC IRQs */ - SK_OUT8(IoC, GMAC_IRQ_MSK, 0); + SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0); /* disable all PHY IRQs */ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0); @@ -1335,11 +1082,10 @@ int Port) /* Port Index (MAC_1 + n) */ /* clear the Hash Register */ GM_OUTHASH(IoC, Port, GM_MC_ADDR_H1, EmptyHash); - /* Enable Unicast and Multicast filtering */ + /* enable Unicast and Multicast filtering */ GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl); - GM_OUT16(IoC, Port, GM_RX_CTRL, - RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); + GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); } /* SkGmSoftRst */ @@ -1350,27 +1096,162 @@ int Port) /* Port Index (MAC_1 + n) */ * * Description: * - * ATTENTION: - * It is absolutely necessary to reset the SW_RST Bit first - * before calling this function. - * * Returns: * nothing */ static void SkGmHardRst( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { + SK_U32 DWord; + + /* WA code for COMA mode */ + if (pAC->GIni.GIYukonLite && + pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) { + + SK_IN32(IoC, B2_GP_IO, &DWord); + + DWord |= (GP_DIR_9 | GP_IO_9); + + /* set PHY reset */ + SK_OUT32(IoC, B2_GP_IO, DWord); + } + /* set GPHY Control reset */ - SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET); + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET); /* set GMAC Control reset */ - SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET); + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET); } /* SkGmHardRst */ +/****************************************************************************** + * + * SkGmClearRst() - Release the GPHY & GMAC reset + * + * Description: + * + * Returns: + * nothing + */ +static void SkGmClearRst( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U32 DWord; +#ifdef SK_DIAG + SK_U16 PhyId0; + SK_U16 PhyId1; +#endif /* SK_DIAG */ + +#if defined(SK_DIAG) || defined(DEBUG) + SK_U16 Word; +#endif /* SK_DIAG || DEBUG */ + + /* WA code for COMA mode */ + if (pAC->GIni.GIYukonLite && + pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) { + + SK_IN32(IoC, B2_GP_IO, &DWord); + + DWord |= GP_DIR_9; /* set to output */ + DWord &= ~GP_IO_9; /* clear PHY reset (active high) */ + + /* clear PHY reset */ + SK_OUT32(IoC, B2_GP_IO, DWord); + } + +#ifdef VCPU + /* set MAC Reset before PHY reset is set */ + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET); +#endif /* VCPU */ + + if (CHIP_ID_YUKON_2(pAC)) { + /* set GPHY Control reset */ + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET); + + /* release GPHY Control reset */ + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR); + +#ifdef DEBUG + /* additional check for PEX */ + SK_IN16(IoC, GPHY_CTRL, &Word); + + if (pAC->GIni.GIPciBus == SK_PEX_BUS && Word != GPC_RST_CLR) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("Error on PEX-bus after GPHY reset\n")); + } +#endif /* DEBUG */ + } + else { + /* set HWCFG_MODE */ + DWord = GPC_INT_POL | GPC_DIS_FC | GPC_DIS_SLEEP | + GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE | + (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP : + GPC_HWCFG_GMII_FIB); + + /* set GPHY Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET); + + /* release GPHY Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR); + } + +#ifdef VCPU + /* wait for internal initialization of GPHY */ + VCPUprintf(0, "Waiting until PHY %d is ready to initialize\n", Port); + VCpuWait(10000); + + /* release GMAC reset */ + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR); + + /* wait for stable GMAC clock */ + VCpuWait(9000); +#endif /* VCPU */ + + /* clear GMAC Control reset */ + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR); + +#ifdef SK_DIAG + if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_2) { + + /* clear GMAC 1 Control reset */ + SK_OUT8(IoC, MR_ADDR(MAC_1, GMAC_CTRL), (SK_U8)GMC_RST_CLR); + + do { + /* set GMAC 2 Control reset */ + SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_SET); + + /* clear GMAC 2 Control reset */ + SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_CLR); + + SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID0, &PhyId0); + + SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID1, &PhyId1); + + SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_INT_MASK, &Word); + + } while (Word != 0 || PhyId0 != PHY_MARV_ID0_VAL || + PhyId1 != PHY_MARV_ID1_Y2); + } +#endif /* SK_DIAG */ + +#ifdef VCPU + VCpuWait(2000); + + SK_IN32(IoC, MR_ADDR(Port, GPHY_CTRL), &DWord); + + SK_IN32(IoC, B0_ISRC, &DWord); +#endif /* VCPU */ + +} /* SkGmClearRst */ +#endif /* YUKON */ + + /****************************************************************************** * * SkMacSoftRst() - Do a MAC software reset @@ -1381,32 +1262,33 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ void SkMacSoftRst( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { - SK_GEPORT *pPrt; - - pPrt = &pAC->GIni.GP[Port]; - /* disable receiver and transmitter */ SkMacRxTxDisable(pAC, IoC, Port); +#ifdef GENESIS if (pAC->GIni.GIGenesis) { SkXmSoftRst(pAC, IoC, Port); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { SkGmSoftRst(pAC, IoC, Port); } +#endif /* YUKON */ /* flush the MAC's Rx and Tx FIFOs */ SkMacFlushTxFifo(pAC, IoC, Port); SkMacFlushRxFifo(pAC, IoC, Port); - pPrt->PState = SK_PRT_STOP; + pAC->GIni.GP[Port].PState = SK_PRT_STOP; } /* SkMacSoftRst */ @@ -1421,25 +1303,65 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ void SkMacHardRst( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { +#ifdef GENESIS if (pAC->GIni.GIGenesis) { SkXmHardRst(pAC, IoC, Port); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { SkGmHardRst(pAC, IoC, Port); } +#endif /* YUKON */ + + pAC->GIni.GP[Port].PHWLinkUp = SK_FALSE; pAC->GIni.GP[Port].PState = SK_PRT_RESET; } /* SkMacHardRst */ +#ifndef SK_SLIM +/****************************************************************************** + * + * SkMacClearRst() - Clear the MAC reset + * + * Description: calls a clear MAC reset routine dep. on board type + * + * Returns: + * nothing + */ +void SkMacClearRst( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port) /* Port Index (MAC_1 + n) */ +{ +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { + + SkXmClearRst(pAC, IoC, Port); + } +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { + + SkGmClearRst(pAC, IoC, Port); + } +#endif /* YUKON */ + +} /* SkMacClearRst */ +#endif /* !SK_SLIM */ + +#ifdef GENESIS /****************************************************************************** * * SkXmInitMac() - Initialize the XMAC II @@ -1455,57 +1377,34 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ void SkXmInitMac( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; - SK_U32 Reg; int i; SK_U16 SWord; pPrt = &pAC->GIni.GP[Port]; if (pPrt->PState == SK_PRT_STOP) { - /* Port State: SK_PRT_STOP */ /* Verify that the reset bit is cleared */ SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord); if ((SWord & MFF_SET_MAC_RST) != 0) { /* PState does not match HW state */ - SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("SkXmInitMac: PState does not match HW state")); /* Correct it */ pPrt->PState = SK_PRT_RESET; } } if (pPrt->PState == SK_PRT_RESET) { - /* - * clear HW reset - * Note: The SW reset is self clearing, therefore there is - * nothing to do here. - */ - SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); - /* Ensure that XMAC reset release is done (errata from LReinbold?) */ - SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord); + SkXmClearRst(pAC, IoC, Port); - /* Clear PHY reset */ if (pPrt->PhyType != SK_PHY_XMAC) { - - SK_IN32(IoC, B2_GP_IO, &Reg); - - if (Port == 0) { - Reg |= (GP_DIR_0 | GP_IO_0); /* set to output */ - } - else { - Reg |= (GP_DIR_2 | GP_IO_2); /* set to output */ - } - SK_OUT32(IoC, B2_GP_IO, Reg); - - /* Enable GMII interface */ - XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_GMII_MD); - /* read Id from external PHY (all have the same address) */ SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_ID1, &pPrt->PhyId1); @@ -1563,12 +1462,6 @@ int Port) /* Port Index (MAC_1 + n) */ * started by the SIRQ, therefore stop it here immediately. */ SkMacInitPhy(pAC, IoC, Port, SK_FALSE); - -#if 0 - /* temp. code: enable signal detect */ - /* WARNING: do not override GMII setting above */ - XM_OUT16(pAC, Port, XM_HW_CFG, XM_HW_COM4SIG); -#endif } /* @@ -1600,7 +1493,7 @@ int Port) /* Port Index (MAC_1 + n) */ SWord = SK_XM_THR_SL; /* for single port */ if (pAC->GIni.GIMacsFound > 1) { - switch (pAC->GIni.GIPortUsage) { + switch (pPrt->PPortUsage) { case SK_RED_LINK: SWord = SK_XM_THR_REDL; /* redundant link */ break; @@ -1623,11 +1516,11 @@ int Port) /* Port Index (MAC_1 + n) */ /* setup register defaults for the Rx Command Register */ SWord = XM_RX_STRIP_FCS | XM_RX_LENERR_OK; - if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + if (pPrt->PPortUsage == SK_JUMBO_LINK) { SWord |= XM_RX_BIG_PK_OK; } - if (pPrt->PLinkModeConf == SK_LMODE_HALF) { + if (pPrt->PLinkMode == SK_LMODE_HALF) { /* * If in manual half duplex mode the other side might be in * full duplex mode, so ignore if a carrier extension is not seen @@ -1673,7 +1566,10 @@ int Port) /* Port Index (MAC_1 + n) */ * has been completed successfully. */ } /* SkXmInitMac */ +#endif /* GENESIS */ + +#ifdef YUKON /****************************************************************************** * * SkGmInitMac() - Initialize the GMAC @@ -1689,8 +1585,8 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ void SkGmInitMac( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; @@ -1701,112 +1597,116 @@ int Port) /* Port Index (MAC_1 + n) */ pPrt = &pAC->GIni.GP[Port]; if (pPrt->PState == SK_PRT_STOP) { - /* Port State: SK_PRT_STOP */ /* Verify that the reset bit is cleared */ SK_IN32(IoC, MR_ADDR(Port, GMAC_CTRL), &DWord); if ((DWord & GMC_RST_SET) != 0) { /* PState does not match HW state */ - SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("SkGmInitMac: PState does not match HW state")); /* Correct it */ pPrt->PState = SK_PRT_RESET; } + else { + /* enable PHY interrupts */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, + (SK_U16)PHY_M_DEF_MSK); + } } if (pPrt->PState == SK_PRT_RESET) { - /* set GPHY Control reset */ - SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET); - /* set GMAC Control reset */ - SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET); + SkGmHardRst(pAC, IoC, Port); - /* clear GMAC Control reset */ - SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_CLR); + SkGmClearRst(pAC, IoC, Port); - /* set GMAC Control reset */ - SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET); +#ifndef SK_SLIM + if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) && + pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) { + /* Force Auto-Negotiation */ + pPrt->PLinkMode = (pPrt->PLinkModeConf == SK_LMODE_FULL) ? + SK_LMODE_AUTOBOTH : SK_LMODE_AUTOHALF; + } +#endif /* !SK_SLIM */ - /* set HWCFG_MODE */ - DWord = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | - GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE | - (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP : - GPC_HWCFG_GMII_FIB); + /* Auto-negotiation ? */ + if (pPrt->PLinkMode == SK_LMODE_HALF || + pPrt->PLinkMode == SK_LMODE_FULL) { + /* Auto-negotiation disabled */ - /* set GPHY Control reset */ - SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET); + /* get General Purpose Control */ + GM_IN16(IoC, Port, GM_GP_CTRL, &SWord); - /* release GPHY Control reset */ - SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR); + /* disable auto-update for speed, duplex and flow-control */ + SWord |= GM_GPCR_AU_ALL_DIS; - /* clear GMAC Control reset */ - SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); + /* setup General Purpose Control Register */ + GM_OUT16(IoC, Port, GM_GP_CTRL, SWord); - /* Dummy read the Interrupt source register */ - SK_IN16(IoC, GMAC_IRQ_SRC, &SWord); + SWord = GM_GPCR_AU_ALL_DIS; + } + else { + SWord = 0; + } + + /* speed settings */ + switch (pPrt->PLinkSpeed) { + case SK_LSPEED_AUTO: + case SK_LSPEED_1000MBPS: + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) { + + SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100; + } + break; + case SK_LSPEED_100MBPS: + SWord |= GM_GPCR_SPEED_100; + break; + case SK_LSPEED_10MBPS: + break; + } + + /* duplex settings */ + if (pPrt->PLinkMode != SK_LMODE_HALF) { + /* set full duplex */ + SWord |= GM_GPCR_DUP_FULL; + } + + /* flow-control settings */ + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + /* disable Tx & Rx flow-control */ + SWord |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; + break; + case SK_FLOW_MODE_LOC_SEND: + /* disable Rx flow-control */ + SWord |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; + break; + case SK_FLOW_MODE_SYMMETRIC: + case SK_FLOW_MODE_SYM_OR_REM: + /* enable Tx & Rx flow-control */ + break; + } + + /* setup General Purpose Control Register */ + GM_OUT16(IoC, Port, GM_GP_CTRL, SWord); + + /* dummy read the Interrupt Source Register */ + SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &SWord); #ifndef VCPU - /* read Id from PHY */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1); - SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE); -#endif /* VCPU */ +#endif /* !VCPU */ } (void)SkGmResetCounter(pAC, IoC, Port); - SWord = 0; - - /* speed settings */ - switch (pPrt->PLinkSpeed) { - case SK_LSPEED_AUTO: - case SK_LSPEED_1000MBPS: - SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100; - break; - case SK_LSPEED_100MBPS: - SWord |= GM_GPCR_SPEED_100; - break; - case SK_LSPEED_10MBPS: - break; - } - - /* duplex settings */ - if (pPrt->PLinkMode != SK_LMODE_HALF) { - /* set full duplex */ - SWord |= GM_GPCR_DUP_FULL; - } - - /* flow control settings */ - switch (pPrt->PFlowCtrlMode) { - case SK_FLOW_MODE_NONE: - /* disable auto-negotiation for flow-control */ - SWord |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS; - break; - case SK_FLOW_MODE_LOC_SEND: - SWord |= GM_GPCR_FC_RX_DIS; - break; - case SK_FLOW_MODE_SYMMETRIC: - /* TBD */ - case SK_FLOW_MODE_SYM_OR_REM: - /* enable auto-negotiation for flow-control and */ - /* enable Rx and Tx of pause frames */ - break; - } - - /* Auto-negotiation ? */ - if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { - /* disable auto-update for speed, duplex and flow-control */ - SWord |= GM_GPCR_AU_ALL_DIS; - } - - /* setup General Purpose Control Register */ - GM_OUT16(IoC, Port, GM_GP_CTRL, SWord); - /* setup Transmit Control Register */ - GM_OUT16(IoC, Port, GM_TX_CTRL, GM_TXCR_COL_THR); + GM_OUT16(IoC, Port, GM_TX_CTRL, (SK_U16)TX_COL_THR(pPrt->PMacColThres)); /* setup Receive Control Register */ - GM_OUT16(IoC, Port, GM_RX_CTRL, GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA | - GM_RXCR_CRC_DIS); + SWord = GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA | GM_RXCR_CRC_DIS; + + GM_OUT16(IoC, Port, GM_RX_CTRL, SWord); /* setup Transmit Flow Control Register */ GM_OUT16(IoC, Port, GM_TX_FLOW_CTRL, 0xffff); @@ -1816,18 +1716,23 @@ int Port) /* Port Index (MAC_1 + n) */ GM_IN16(IoC, Port, GM_TX_PARAM, &SWord); #endif /* VCPU */ - SWord = JAM_LEN_VAL(3) | JAM_IPG_VAL(11) | IPG_JAM_DATA(26); + SWord = (SK_U16)(TX_JAM_LEN_VAL(pPrt->PMacJamLen) | + TX_JAM_IPG_VAL(pPrt->PMacJamIpgVal) | + TX_IPG_JAM_DATA(pPrt->PMacJamIpgData) | + TX_BACK_OFF_LIM(pPrt->PMacBackOffLim)); GM_OUT16(IoC, Port, GM_TX_PARAM, SWord); /* configure the Serial Mode Register */ -#ifdef VCPU - GM_IN16(IoC, Port, GM_SERIAL_MODE, &SWord); -#endif /* VCPU */ + SWord = (SK_U16)(DATA_BLIND_VAL(pPrt->PMacDataBlind) | + GM_SMOD_VLAN_ENA | IPG_DATA_VAL(pPrt->PMacIpgData)); - SWord = GM_SMOD_VLAN_ENA | IPG_VAL_FAST_ETH; + if (pPrt->PMacLimit4) { + /* reset of collision counter after 4 consecutive collisions */ + SWord |= GM_SMOD_LIMIT_4; + } - if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + if (pPrt->PPortUsage == SK_JUMBO_LINK) { /* enable jumbo mode (Max. Frame Length = 9018) */ SWord |= GM_SMOD_JUMBO_ENA; } @@ -1852,7 +1757,7 @@ int Port) /* Port Index (MAC_1 + n) */ #ifdef WA_DEV_16 /* WA for deviation #16 */ - if (pAC->GIni.GIChipRev == 0) { + if (pAC->GIni.GIChipId == CHIP_ID_YUKON && pAC->GIni.GIChipRev == 0) { /* swap the address bytes */ SWord = ((SWord & 0xff00) >> 8) | ((SWord & 0x00ff) << 8); @@ -1872,7 +1777,7 @@ int Port) /* Port Index (MAC_1 + n) */ GM_OUT16(IoC, Port, (GM_SRC_ADDR_2L + i * 4), SWord); /* reset Multicast filtering Hash registers 1-3 */ - GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + 4*i, 0); + GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + i * 4, 0); } /* reset Multicast filtering Hash register 4 */ @@ -1883,19 +1788,11 @@ int Port) /* Port Index (MAC_1 + n) */ GM_OUT16(IoC, Port, GM_RX_IRQ_MSK, 0); GM_OUT16(IoC, Port, GM_TR_IRQ_MSK, 0); - /* read General Purpose Status */ - GM_IN16(IoC, Port, GM_GP_STAT, &SWord); - - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("MAC Stat Reg=0x%04X\n", SWord)); - -#ifdef SK_DIAG - c_print("MAC Stat Reg=0x%04X\n", SWord); -#endif /* SK_DIAG */ - } /* SkGmInitMac */ +#endif /* YUKON */ +#ifdef GENESIS /****************************************************************************** * * SkXmInitDupMd() - Initialize the XMACs Duplex Mode @@ -1909,8 +1806,8 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ void SkXmInitDupMd( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { switch (pAC->GIni.GP[Port].PLinkModeStatus) { @@ -1957,8 +1854,8 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ void SkXmInitPauseMd( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; @@ -1972,7 +1869,7 @@ int Port) /* Port Index (MAC_1 + n) */ if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE || pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) { - /* Disable Pause Frame Reception */ + /* disable Pause Frame Reception */ Word |= XM_MMU_IGN_PF; } else { @@ -1980,7 +1877,7 @@ int Port) /* Port Index (MAC_1 + n) */ * enabling pause frame reception is required for 1000BT * because the XMAC is not reset if the link is going down */ - /* Enable Pause Frame Reception */ + /* enable Pause Frame Reception */ Word &= ~XM_MMU_IGN_PF; } @@ -2006,10 +1903,10 @@ int Port) /* Port Index (MAC_1 + n) */ /* remember this value is defined in big endian (!) */ XM_OUT16(IoC, Port, XM_MAC_PTIME, 0xffff); - /* Set Pause Mode in Mode Register */ + /* set Pause Mode in Mode Register */ DWord |= XM_PAUSE_MODE; - /* Set Pause Mode in MAC Rx FIFO */ + /* set Pause Mode in MAC Rx FIFO */ SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_PAUSE); } else { @@ -2017,10 +1914,10 @@ int Port) /* Port Index (MAC_1 + n) */ * disable pause frame generation is required for 1000BT * because the XMAC is not reset if the link is going down */ - /* Disable Pause Mode in Mode Register */ + /* disable Pause Mode in Mode Register */ DWord &= ~XM_PAUSE_MODE; - /* Disable Pause Mode in MAC Rx FIFO */ + /* disable Pause Mode in MAC Rx FIFO */ SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_DIS_PAUSE); } @@ -2030,9 +1927,9 @@ int Port) /* Port Index (MAC_1 + n) */ /****************************************************************************** * - * SkXmInitPhyXmac() - Initialize the XMAC Phy registers + * SkXmInitPhyXmac() - Initialize the XMAC PHY registers * - * Description: initializes all the XMACs Phy registers + * Description: initializes all the XMACs PHY registers * * Note: * @@ -2040,10 +1937,10 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ static void SkXmInitPhyXmac( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */ { SK_GEPORT *pPrt; SK_U16 Ctrl; @@ -2055,7 +1952,7 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, ("InitPhyXmac: no auto-negotiation Port %d\n", Port)); - /* Set DuplexMode in Config register */ + /* set DuplexMode in Config register */ if (pPrt->PLinkMode == SK_LMODE_FULL) { Ctrl |= PHY_CT_DUP_MD; } @@ -2068,9 +1965,9 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ else { SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, ("InitPhyXmac: with auto-negotiation Port %d\n", Port)); - /* Set Auto-negotiation advertisement */ + /* set Auto-negotiation advertisement */ - /* Set Full/half duplex capabilities */ + /* set Full/half duplex capabilities */ switch (pPrt->PLinkMode) { case SK_LMODE_AUTOHALF: Ctrl |= PHY_X_AN_HD; @@ -2086,6 +1983,7 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ SKERR_HWI_E015MSG); } + /* set Flow-control capabilities */ switch (pPrt->PFlowCtrlMode) { case SK_FLOW_MODE_NONE: Ctrl |= PHY_X_P_NO_PAUSE; @@ -2112,20 +2010,20 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ } if (DoLoop) { - /* Set the Phy Loopback bit, too */ + /* set the PHY Loopback bit, too */ Ctrl |= PHY_CT_LOOP; } - /* Write to the Phy control register */ + /* Write to the PHY control register */ SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_CTRL, Ctrl); } /* SkXmInitPhyXmac */ /****************************************************************************** * - * SkXmInitPhyBcom() - Initialize the Broadcom Phy registers + * SkXmInitPhyBcom() - Initialize the Broadcom PHY registers * - * Description: initializes all the Broadcom Phy registers + * Description: initializes all the Broadcom PHY registers * * Note: * @@ -2133,10 +2031,10 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ * nothing */ static void SkXmInitPhyBcom( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */ { SK_GEPORT *pPrt; SK_U16 Ctrl1; @@ -2165,8 +2063,10 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, ("InitPhyBcom: no auto-negotiation Port %d\n", Port)); - /* Set DuplexMode in Config register */ - Ctrl1 |= (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0); + /* set DuplexMode in Config register */ + if (pPrt->PLinkMode == SK_LMODE_FULL) { + Ctrl1 |= PHY_CT_DUP_MD; + } /* Determine Master/Slave manually if not already done */ if (pPrt->PMSMode == SK_MS_MODE_AUTO) { @@ -2181,7 +2081,7 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ else { SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, ("InitPhyBcom: with auto-negotiation Port %d\n", Port)); - /* Set Auto-negotiation advertisement */ + /* set Auto-negotiation advertisement */ /* * Workaround BCOM Errata #1 for the C5 type. @@ -2190,7 +2090,7 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ */ Ctrl2 |= PHY_B_1000C_RD; - /* Set Full/half duplex capabilities */ + /* set Full/half duplex capabilities */ switch (pPrt->PLinkMode) { case SK_LMODE_AUTOHALF: Ctrl2 |= PHY_B_1000C_AHD; @@ -2206,6 +2106,7 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ SKERR_HWI_E015MSG); } + /* set Flow-control capabilities */ switch (pPrt->PFlowCtrlMode) { case SK_FLOW_MODE_NONE: Ctrl3 |= PHY_B_P_NO_PAUSE; @@ -2230,24 +2131,24 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ /* Initialize LED register here? */ /* No. Please do it in SkDgXmitLed() (if required) and swap - init order of LEDs and XMAC. (MAl) */ + init order of LEDs and XMAC. (MAl) */ /* Write 1000Base-T Control Register */ SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, Ctrl2); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2)); + ("Set 1000B-T Ctrl Reg = 0x%04X\n", Ctrl2)); /* Write AutoNeg Advertisement Register */ SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, Ctrl3); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("Auto-Neg. Adv. Reg=0x%04X\n", Ctrl3)); + ("Set Auto-Neg.Adv.Reg = 0x%04X\n", Ctrl3)); if (DoLoop) { - /* Set the Phy Loopback bit, too */ + /* set the PHY Loopback bit, too */ Ctrl1 |= PHY_CT_LOOP; } - if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + if (pPrt->PPortUsage == SK_JUMBO_LINK) { /* configure FIFO to high latency for transmission of ext. packets */ Ctrl4 |= PHY_B_PEC_HIGH_LA; @@ -2260,18 +2161,533 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ /* Configure LED Traffic Mode and Jumbo Frame usage if specified */ SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, Ctrl4); - /* Write to the Phy control register */ + /* Write to the PHY control register */ SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, Ctrl1); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("PHY Control Reg=0x%04X\n", Ctrl1)); + ("PHY Control Reg = 0x%04X\n", Ctrl1)); } /* SkXmInitPhyBcom */ +#endif /* GENESIS */ +#ifdef YUKON +#ifdef SK_PHY_LP_MODE +/****************************************************************************** + * + * SkGmEnterLowPowerMode() + * + * Description: + * This function sets the Marvell Alaska PHY to the low power mode + * given by parameter mode. + * The following low power modes are available: + * + * - COMA Mode (Deep Sleep): + * The PHY cannot wake up on its own. + * + * - IEEE 22.2.4.1.5 compatible power down mode + * The PHY cannot wake up on its own. + * + * - energy detect mode + * The PHY can wake up on its own by detecting activity + * on the CAT 5 cable. + * + * - energy detect plus mode + * The PHY can wake up on its own by detecting activity + * on the CAT 5 cable. + * Connected devices can be woken up by sending normal link + * pulses every second. + * + * Note: + * + * Returns: + * 0: ok + * 1: error + */ +int SkGmEnterLowPowerMode( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (e.g. MAC_1) */ +SK_U8 Mode) /* low power mode */ +{ + SK_U8 LastMode; + SK_U8 Byte; + SK_U16 Word; + SK_U16 ClkDiv; + SK_U32 DWord; + SK_U32 PowerDownBit; + int ChipId; + int Ret = 0; + + if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite && + pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) { + + return(1); + } + + /* save current power mode */ + LastMode = pAC->GIni.GP[Port].PPhyPowerState; + pAC->GIni.GP[Port].PPhyPowerState = Mode; + + ChipId = pAC->GIni.GIChipId; + + SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL, + ("SkGmEnterLowPowerMode: %u\n", Mode)); + + /* release GPHY Control reset */ + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR); + + /* release GMAC reset */ + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR); + + if (ChipId == CHIP_ID_YUKON_EC_U) { + /* select page 2 to access MAC control register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2); + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word); + /* allow GMII Power Down */ + Word &= ~PHY_M_MAC_GMIF_PUP; + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word); + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0); + } + + switch (Mode) { + /* COMA mode (deep sleep) */ + case PHY_PM_DEEP_SLEEP: + /* setup General Purpose Control Register */ + GM_OUT16(IoC, Port, GM_GP_CTRL, GM_GPCR_FL_PASS | + GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS); + + if (CHIP_ID_YUKON_2(pAC)) { + /* set power down bit */ + PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD : + PCI_Y2_PHY2_POWD; + + if (ChipId != CHIP_ID_YUKON_EC) { + + if (ChipId == CHIP_ID_YUKON_EC_U) { + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word); + /* enable Power Down */ + Word |= PHY_M_PC_POW_D_ENA; + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word); + } + + /* set IEEE compatible Power Down Mode (dev. #4.99) */ + Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_PDOWN); + } + } + else { + /* apply COMA mode workaround */ + (void)SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 0x001f); + + Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xfff3); + + PowerDownBit = PCI_PHY_COMA; + } + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord); + + /* set PHY to PowerDown/COMA Mode */ + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord | PowerDownBit); + + /* check if this routine was called from a for() loop */ + if (pAC->GIni.GIMacsFound == 1 || Port == MAC_2) { + + /* ASF system clock stopped */ + SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_CLK_HALT); + + if (ChipId == CHIP_ID_YUKON_EC_U) { + /* set GPHY Control reset */ + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET); + + /* additional power saving measurements */ + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord); + + /* set gating core clock for LTSSM in L1 state */ + DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) | + /* auto clock gated scheme controlled by CLKREQ */ + P_ASPM_A1_MODE_SELECT | + /* enable Gate Root Core Clock */ + P_CLK_GATE_ROOT_COR_ENA); + + if (HW_FEATURE(pAC, HWF_WA_DEV_4200)) { + /* enable Clock Power Management (CLKREQ) */ + SK_IN16(IoC, PCI_C(pAC, PEX_LNK_CTRL), &Word); + Word |= PEX_LC_CLK_PM_ENA; + SK_OUT16(IoC, PCI_C(pAC, PEX_LNK_CTRL), Word); + } + else { + /* force CLKREQ Enable in Our4 (A1b only) */ + DWord |= P_ASPM_FORCE_CLKREQ_ENA; + } + + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord); + + /* set Mask Register for Release/Gate Clock */ + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), + P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST | + P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE | + P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN); + } + + if (HW_FEATURE(pAC, HWF_RED_CORE_CLK_SUP)) { + /* divide clock by 4 only for Yukon-EC */ + ClkDiv = (ChipId == CHIP_ID_YUKON_EC) ? 1 : 0; + + /* on Yukon-2 clock select value is 31 */ + DWord = (ChipId == CHIP_ID_YUKON_XL) ? + (Y2_CLK_DIV_VAL_2(0) | Y2_CLK_SEL_VAL_2(31)) : + Y2_CLK_DIV_VAL(ClkDiv); + + /* check for Yukon-2 dual port PCI-Express adapter */ + if (!(pAC->GIni.GIMacsFound == 2 && + pAC->GIni.GIPciBus == SK_PEX_BUS)) { + /* enable Core Clock Division */ + DWord |= Y2_CLK_DIV_ENA; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Set Core Clock: 0x%08X\n", DWord)); + + /* reduce Core Clock Frequency */ + SK_OUT32(IoC, B2_Y2_CLK_CTRL, DWord); + } + + if (HW_FEATURE(pAC, HWF_CLK_GATING_ENABLE)) { + /* check for Yukon-2 Rev. A2 */ + if (ChipId == CHIP_ID_YUKON_XL && + pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) { + /* enable bits are inverted */ + Byte = 0; + } + else { + Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Set Clock Gating: 0x%02X\n", Byte)); + + /* disable MAC/PHY, PCI and Core Clock for both Links */ + SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte); + } + + if (pAC->GIni.GIVauxAvail) { + /* switch power to VAUX */ + SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA | + PC_VAUX_ON | PC_VCC_OFF)); + } +#ifdef DEBUG + SK_IN32(IoC, B0_CTST, &DWord); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Ctrl/Stat & Switch: 0x%08x\n", DWord)); +#endif /* DEBUG */ + + if (pAC->GIni.GILevel != SK_INIT_IO && + pAC->GIni.GIMacsFound == 1 && + pAC->GIni.GIPciBus == SK_PEX_BUS) { + + if (ChipId == CHIP_ID_YUKON_EC_U) { + +#ifdef PCI_E_L1_STATE + SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Word); + /* force to PCIe L1 */ + Word |= (SK_U16)PCI_FORCE_PEX_L1; + SK_OUT16(IoC, PCI_C(pAC, PCI_OUR_REG_1), Word); +#endif /* PCI_E_L1_STATE */ + } + else { + /* switch to D1 state */ + SK_OUT8(IoC, PCI_C(pAC, PCI_PM_CTL_STS), PCI_PM_STATE_D1); + } + } + } + + break; + + /* IEEE 22.2.4.1.5 compatible power down mode */ + case PHY_PM_IEEE_POWER_DOWN: + + Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word); + + if (!CHIP_ID_YUKON_2(pAC)) { + /* disable MAC 125 MHz clock */ + Word |= PHY_M_PC_DIS_125CLK; + Word &= ~PHY_M_PC_MAC_POW_UP; + } + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word); + + /* these register changes must be followed by a software reset */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word); + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word | PHY_CT_RESET); + + /* switch IEEE compatible power down mode on */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word | PHY_CT_PDOWN); + + break; + + /* energy detect and energy detect plus mode */ + case PHY_PM_ENERGY_DETECT: + case PHY_PM_ENERGY_DETECT_PLUS: + + Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word); + + /* disable Polarity Reversal */ + Word |= PHY_M_PC_POL_R_DIS; + + if (!CHIP_ID_YUKON_2(pAC)) { + /* disable MAC 125 MHz clock */ + Word |= PHY_M_PC_DIS_125CLK; + } + + if (ChipId == CHIP_ID_YUKON_FE) { + /* enable Energy Detect (sense & pulse) */ + Word |= PHY_M_PC_ENA_ENE_DT; + } + else { + /* clear energy detect mode bits */ + Word &= ~PHY_M_PC_EN_DET_MSK; + + Word |= (Mode == PHY_PM_ENERGY_DETECT) ? PHY_M_PC_EN_DET : + PHY_M_PC_EN_DET_PLUS; + } + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word); + + /* these register changes must be followed by a software reset */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word); + Word |= PHY_CT_RESET; + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word); + + if (ChipId == CHIP_ID_YUKON_EC_U) { + /* additional power saving measurements */ + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord); + + /* set gating core clock for LTSSM in L1 state */ + DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) | + /* Enable Gate Root Core Clock */ + P_CLK_GATE_ROOT_COR_ENA); + + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord); + + /* set Mask Register for Release/Gate Clock */ + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), + P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST | + P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE | + P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN); + +#ifdef PCI_E_L1_STATE + SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Word); + /* enable PCIe L1 on GPHY link down */ + Word |= (SK_U16)PCI_ENA_GPHY_LNK; + SK_OUT16(IoC, PCI_C(pAC, PCI_OUR_REG_1), Word); +#endif /* PCI_E_L1_STATE */ + } + + break; + + /* don't change current power mode */ + default: + pAC->GIni.GP[Port].PPhyPowerState = LastMode; + Ret = 1; + } + + return(Ret); + +} /* SkGmEnterLowPowerMode */ + /****************************************************************************** * - * SkGmInitPhyMarv() - Initialize the Marvell Phy registers + * SkGmLeaveLowPowerMode() * - * Description: initializes all the Marvell Phy registers + * Description: + * Leave the current low power mode and switch to normal mode + * + * Note: + * + * Returns: + * 0: ok + * 1: error + */ +int SkGmLeaveLowPowerMode( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port) /* Port Index (e.g. MAC_1) */ +{ + SK_U32 DWord; + SK_U32 PowerDownBit; + SK_U16 Word; + SK_U8 LastMode; + int ChipId; + int Ret = 0; + + if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite && + pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) { + + return(1); + } + + /* save current power mode */ + LastMode = pAC->GIni.GP[Port].PPhyPowerState; + pAC->GIni.GP[Port].PPhyPowerState = PHY_PM_OPERATIONAL_MODE; + + ChipId = pAC->GIni.GIChipId; + + SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL, + ("SkGmLeaveLowPowerMode: %u\n", LastMode)); + + switch (LastMode) { + /* COMA mode (deep sleep) */ + case PHY_PM_DEEP_SLEEP: + + if (ChipId == CHIP_ID_YUKON_EC_U) { +#ifdef PCI_E_L1_STATE + /* set to default value (leave PCIe L1) */ + SkPciWriteCfgWord(pAC, PCI_OUR_REG_1, 0); +#endif /* PCI_E_L1_STATE */ + + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord); + + DWord &= P_ASPM_CONTROL_MSK; + /* set all bits to 0 except bits 15..12 */ + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord); + + /* set to default value */ + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), 0); + } + else { + SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &Word); + + /* reset all DState bits */ + Word &= ~PCI_PM_STATE_MSK; + + /* switch to D0 state */ + SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, Word); + } + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + + if (CHIP_ID_YUKON_2(pAC)) { + /* disable Core Clock Division */ + SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); + + /* set power down bit */ + PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD : + PCI_Y2_PHY2_POWD; + } + else { + PowerDownBit = PCI_PHY_COMA; + } + + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord); + + /* Release PHY from PowerDown/COMA Mode */ + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord & ~PowerDownBit); + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + + if (CHIP_ID_YUKON_2(pAC)) { + + if (ChipId == CHIP_ID_YUKON_FE) { + /* release IEEE compatible Power Down Mode */ + Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_ANE); + } + else if (ChipId == CHIP_ID_YUKON_EC_U) { + /* release GPHY Control reset */ + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR); + } + } + else { + SK_IN32(IoC, B2_GP_IO, &DWord); + + /* set to output */ + DWord |= (GP_DIR_9 | GP_IO_9); + + /* set PHY reset */ + SK_OUT32(IoC, B2_GP_IO, DWord); + + DWord &= ~GP_IO_9; /* clear PHY reset (active high) */ + + /* clear PHY reset */ + SK_OUT32(IoC, B2_GP_IO, DWord); + } + + break; + + /* IEEE 22.2.4.1.5 compatible power down mode */ + case PHY_PM_IEEE_POWER_DOWN: + + if (ChipId != CHIP_ID_YUKON_XL) { + + Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word); + Word &= ~PHY_M_PC_DIS_125CLK; /* enable MAC 125 MHz clock */ + Word |= PHY_M_PC_MAC_POW_UP; /* set MAC power up */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word); + + /* these register changes must be followed by a software reset */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word); + Word |= PHY_CT_RESET; + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word); + } + + /* switch IEEE compatible power down mode off */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word); + Word &= ~PHY_CT_PDOWN; + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word); + + break; + + /* energy detect and energy detect plus mode */ + case PHY_PM_ENERGY_DETECT: + case PHY_PM_ENERGY_DETECT_PLUS: + + if (ChipId != CHIP_ID_YUKON_XL) { + + Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word); + + if (ChipId == CHIP_ID_YUKON_FE) { + /* disable Energy Detect */ + Word &= ~PHY_M_PC_ENA_ENE_DT; + } + else { + /* disable energy detect mode & enable MAC 125 MHz clock */ + Word &= ~(PHY_M_PC_EN_DET_MSK | PHY_M_PC_DIS_125CLK); + } + + /* enable Polarity Reversal */ + Word &= ~PHY_M_PC_POL_R_DIS; + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word); + + /* these register changes must be followed by a software reset */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word); + Word |= PHY_CT_RESET; + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word); + } + break; + + /* don't change current power mode */ + default: + pAC->GIni.GP[Port].PPhyPowerState = LastMode; + Ret = 1; + } + + return(Ret); + +} /* SkGmLeaveLowPowerMode */ +#endif /* SK_PHY_LP_MODE */ + +/****************************************************************************** + * + * SkGmInitPhyMarv() - Initialize the Marvell PHY registers + * + * Description: initializes all the Marvell PHY registers * * Note: * @@ -2279,64 +2695,216 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ * nothing */ static void SkGmInitPhyMarv( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */ { SK_GEPORT *pPrt; + SK_BOOL AutoNeg; SK_U16 PhyCtrl; SK_U16 C1000BaseT; SK_U16 AutoNegAdv; + SK_U8 PauseMode; + int ChipId; + int Mode; +#ifndef VCPU + SK_U16 Word; + SK_U16 PageReg; +#ifndef SK_SLIM + SK_U16 LoopSpeed; +#endif /* !SK_SLIM */ SK_U16 ExtPhyCtrl; + SK_U16 BlinkCtrl; + SK_U16 LedCtrl; + SK_U16 LedConf; + SK_U16 LedOver; +#ifndef SK_DIAG + SK_EVPARA Para; +#endif /* !SK_DIAG */ +#if defined(SK_DIAG) || defined(DEBUG) SK_U16 PhyStat; SK_U16 PhyStat1; SK_U16 PhySpecStat; - SK_U16 LedCtrl; - SK_BOOL AutoNeg; +#endif /* SK_DIAG || DEBUG */ +#endif /* !VCPU */ -#ifdef VCPU - VCPUprintf(0, "SkGmInitPhyMarv(), Port=%u, DoLoop=%u\n", - Port, DoLoop); -#else /* VCPU */ + /* set Pause On */ + PauseMode = (SK_U8)GMC_PAUSE_ON; pPrt = &pAC->GIni.GP[Port]; + ChipId = pAC->GIni.GIChipId; + /* Auto-negotiation ? */ - if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { - AutoNeg = SK_FALSE; - } - else { - AutoNeg = SK_TRUE; + AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF && + pPrt->PLinkMode != SK_LMODE_FULL; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyMarv: Port %d, Auto-neg. %s, LMode %d, LSpeed %d, FlowC %d\n", + Port, AutoNeg ? "ON" : "OFF", + pPrt->PLinkMode, pPrt->PLinkSpeed, pPrt->PFlowCtrlMode)); + +#ifndef VCPU + /* read Id from PHY */ + if (SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1) != 0) { + +#ifndef SK_DIAG + Para.Para64 = Port; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); +#endif /* !SK_DIAG */ + + return; } - if (!DoLoop) { - /* Read Ext. PHY Specific Control */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl); + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) { - ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | - PHY_M_EC_MAC_S_MSK); +#ifndef SK_SLIM + if (DoLoop) { + /* special setup for PHY 88E1112 */ + if (ChipId == CHIP_ID_YUKON_XL) { - ExtPhyCtrl |= PHY_M_EC_M_DSC(1) | PHY_M_EC_S_DSC(1) | - PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); + LoopSpeed = pPrt->PLinkSpeed; - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl); - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("Ext.PHYCtrl=0x%04X\n", ExtPhyCtrl)); + if (LoopSpeed == SK_LSPEED_AUTO) { + /* force 1000 Mbps */ + LoopSpeed = SK_LSPEED_1000MBPS; + } + LoopSpeed += 2; - /* Read PHY Control */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl); + /* save page register */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg); - /* Assert software reset */ - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, - (SK_U16)(PhyCtrl | PHY_CT_RESET)); + /* select page 2 to access MAC control register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2); + + /* set MAC interface speed */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, LoopSpeed << 4); + + /* restore page register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg); + + /* disable link pulses */ + Word = PHY_M_PC_DIS_LINK_P; + } + else { + /* set 'MAC Power up'-bit, set Manual MDI configuration */ + Word = PHY_M_PC_MAC_POW_UP; + } + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word); + } + else +#endif /* !SK_SLIM */ + if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO && + !(ChipId == CHIP_ID_YUKON_XL || ChipId == CHIP_ID_YUKON_EC_U)) { + /* Read Ext. PHY Specific Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl); + + ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | + PHY_M_EC_MAC_S_MSK); + + ExtPhyCtrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); + + /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ + if (pAC->GIni.GIYukonLite || ChipId == CHIP_ID_YUKON_EC) { + /* set downshift counter to 3x and enable downshift */ + ExtPhyCtrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; + } + else { + /* set master & slave downshift counter to 1x */ + ExtPhyCtrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); + } + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Set Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl)); + } } -#endif /* VCPU */ + + if (CHIP_ID_YUKON_2(pAC)) { + /* Read PHY Specific Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhyCtrl); + + if (!DoLoop && pAC->GIni.GICopperType) { + + if (ChipId == CHIP_ID_YUKON_FE) { + /* enable Automatic Crossover (!!! Bits 5..4) */ + PhyCtrl |= (SK_U16)(PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1); + } + else { +#ifndef SK_DIAG + /* disable Energy Detect Mode */ + PhyCtrl &= ~PHY_M_PC_EN_DET_MSK; +#endif /* !SK_DIAG */ + + /* enable Automatic Crossover */ + PhyCtrl |= (SK_U16)PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); + + /* downshift on PHY 88E1112 and 88E1149 is changed */ + if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO && + (ChipId == CHIP_ID_YUKON_XL || + ChipId == CHIP_ID_YUKON_EC_U)) { + /* set downshift counter to 3x and enable downshift */ + PhyCtrl &= ~PHY_M_PC_DSC_MSK; + PhyCtrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; + } + } + } + /* workaround for deviation #4.88 (CRC errors) */ + else { + /* disable Automatic Crossover */ + PhyCtrl &= ~PHY_M_PC_MDIX_MSK; + } + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhyCtrl); + } + + /* special setup for PHY 88E1112 Fiber */ + if (ChipId == CHIP_ID_YUKON_XL && !pAC->GIni.GICopperType) { + /* select 1000BASE-X only mode in MAC Specific Ctrl Reg. */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2); + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word); + + Word &= ~PHY_M_MAC_MD_MSK; + Word |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word); + + /* select page 1 to access Fiber registers */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1); + + if (pAC->GIni.GIPmdTyp == 'P') { + /* for SFP-module set SIGDET polarity to low */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word); + + Word |= PHY_M_FIB_SIGD_POL; + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word); + } + } + + /* Read PHY Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl); + +#ifndef SK_SLIM + if (!AutoNeg) { + /* disable Auto-negotiation */ + PhyCtrl &= ~PHY_CT_ANE; + } +#endif /* !SK_SLIM */ + + PhyCtrl |= PHY_CT_RESET; + /* assert software reset */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl); +#endif /* !VCPU */ PhyCtrl = 0 /* PHY_CT_COL_TST */; C1000BaseT = 0; AutoNegAdv = PHY_SEL_TYPE; +#ifndef SK_SLIM /* manually Master/Slave ? */ if (pPrt->PMSMode != SK_MS_MODE_AUTO) { /* enable Manual Master/Slave */ @@ -2346,27 +2914,28 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ C1000BaseT |= PHY_M_1000C_MSC; /* set it to Master */ } } +#endif /* !SK_SLIM */ /* Auto-negotiation ? */ if (!AutoNeg) { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("InitPhyMarv: no auto-negotiation Port %d\n", Port)); +#ifndef SK_SLIM if (pPrt->PLinkMode == SK_LMODE_FULL) { - /* Set Full Duplex Mode */ + /* set Full Duplex Mode */ PhyCtrl |= PHY_CT_DUP_MD; } - /* Set Master/Slave manually if not already done */ + /* set Master/Slave manually if not already done */ if (pPrt->PMSMode == SK_MS_MODE_AUTO) { C1000BaseT |= PHY_M_1000C_MSE; /* set it to Slave */ } - /* Set Speed */ + /* set Speed */ switch (pPrt->PLinkSpeed) { case SK_LSPEED_AUTO: case SK_LSPEED_1000MBPS: - PhyCtrl |= PHY_CT_SP1000; + PhyCtrl |= (((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ? + PHY_CT_SP1000 : PHY_CT_SP100); break; case SK_LSPEED_100MBPS: PhyCtrl |= PHY_CT_SP100; @@ -2378,44 +2947,67 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ SKERR_HWI_E019MSG); } + if ((pPrt->PFlowCtrlMode == SK_FLOW_STAT_NONE) || + /* disable Pause also for 10/100 Mbps in half duplex mode */ + ((ChipId != CHIP_ID_YUKON_EC_U) && + (pPrt->PLinkMode == SK_LMODE_HALF) && + ((pPrt->PLinkSpeed == SK_LSPEED_STAT_100MBPS) || + (pPrt->PLinkSpeed == SK_LSPEED_STAT_10MBPS)))) { + + /* set Pause Off */ + PauseMode = (SK_U8)GMC_PAUSE_OFF; + } + + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode); + if (!DoLoop) { + /* assert software reset */ PhyCtrl |= PHY_CT_RESET; } - /* - * Do NOT enable Auto-negotiation here. This would hold - * the link down because no IDLES are transmitted - */ +#endif /* !SK_SLIM */ } else { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("InitPhyMarv: with auto-negotiation Port %d\n", Port)); - - PhyCtrl |= PHY_CT_ANE; + /* set Auto-negotiation advertisement */ if (pAC->GIni.GICopperType) { - /* Set Speed capabilities */ + /* set Speed capabilities */ switch (pPrt->PLinkSpeed) { case SK_LSPEED_AUTO: - C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD; + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) { + C1000BaseT |= PHY_M_1000C_AFD; +#ifdef xSK_DIAG + C1000BaseT |= PHY_M_1000C_AHD; +#endif /* SK_DIAG */ + } AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD | PHY_M_AN_10_FD | PHY_M_AN_10_HD; break; case SK_LSPEED_1000MBPS: - C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD; + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) { + C1000BaseT |= PHY_M_1000C_AFD; +#ifdef xSK_DIAG + C1000BaseT |= PHY_M_1000C_AHD; +#endif /* SK_DIAG */ + } break; case SK_LSPEED_100MBPS: - AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD | - PHY_M_AN_10_FD | PHY_M_AN_10_HD; + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_100MBPS) != 0) { + AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD | + /* advertise 10Base-T also */ + PHY_M_AN_10_FD | PHY_M_AN_10_HD; + } break; case SK_LSPEED_10MBPS: - AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD; + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_10MBPS) != 0) { + AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD; + } break; default: SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019, SKERR_HWI_E019MSG); } - /* Set Full/half duplex capabilities */ + /* set Full/half duplex capabilities */ switch (pPrt->PLinkMode) { case SK_LMODE_AUTOHALF: C1000BaseT &= ~PHY_M_1000C_AFD; @@ -2432,7 +3024,7 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ SKERR_HWI_E015MSG); } - /* Set Auto-negotiation advertisement */ + /* set Flow-control capabilities */ switch (pPrt->PFlowCtrlMode) { case SK_FLOW_MODE_NONE: AutoNegAdv |= PHY_B_P_NO_PAUSE; @@ -2451,9 +3043,9 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ SKERR_HWI_E016MSG); } } - else { /* special defines for FIBER (88E1011S only) */ + else { /* special defines for FIBER (88E1040S only) */ - /* Set Full/half duplex capabilities */ + /* set Full/half duplex capabilities */ switch (pPrt->PLinkMode) { case SK_LMODE_AUTOHALF: AutoNegAdv |= PHY_M_AN_1000X_AHD; @@ -2469,7 +3061,7 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ SKERR_HWI_E015MSG); } - /* Set Auto-negotiation advertisement */ + /* set Flow-control capabilities */ switch (pPrt->PFlowCtrlMode) { case SK_FLOW_MODE_NONE: AutoNegAdv |= PHY_M_P_NO_PAUSE_X; @@ -2491,7 +3083,7 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ if (!DoLoop) { /* Restart Auto-negotiation */ - PhyCtrl |= PHY_CT_RE_CFG; + PhyCtrl |= PHY_CT_ANE | PHY_CT_RE_CFG; } } @@ -2501,126 +3093,246 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ */ /* Program PHY register 30 as 16'h0708 for simulation speed up */ - SkGmPhyWrite(pAC, IoC, Port, 30, 0x0708); + SkGmPhyWrite(pAC, IoC, Port, 30, 0x0700 /* 0x0708 */); VCpuWait(2000); -#else /* VCPU */ +#else /* !VCPU */ - /* Write 1000Base-T Control Register */ - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT); - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("1000B-T Ctrl=0x%04X\n", C1000BaseT)); + if (ChipId != CHIP_ID_YUKON_FE) { + /* Write 1000Base-T Control Register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Set 1000B-T Ctrl = 0x%04X\n", C1000BaseT)); + } /* Write AutoNeg Advertisement Register */ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, AutoNegAdv); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("Auto-Neg.Ad.=0x%04X\n", AutoNegAdv)); -#endif /* VCPU */ + ("Set Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv)); +#endif /* !VCPU */ +#ifndef SK_SLIM if (DoLoop) { - /* Set the PHY Loopback bit */ + /* set the PHY Loopback bit */ PhyCtrl |= PHY_CT_LOOP; - - /* Program PHY register 16 as 16'h0400 to force link good */ - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_FL_GOOD); - -#if 0 - if (pPrt->PLinkSpeed != SK_LSPEED_AUTO) { - /* Write Ext. PHY Specific Control */ - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, - (SK_U16)((pPrt->PLinkSpeed + 2) << 4)); - } - } - else if (pPrt->PLinkSpeed == SK_LSPEED_10MBPS) { - /* Write PHY Specific Control */ - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_EN_DET_MSK); - } -#endif /* 0 */ } +#endif /* !SK_SLIM */ /* Write to the PHY Control register */ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Set PHY Ctrl Reg. = 0x%04X\n", PhyCtrl)); #ifdef VCPU VCpuWait(2000); -#else +#else /* !VCPU */ - LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS) | PHY_M_LED_BLINK_RT(BLINK_84MS); + LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS); -#ifdef ACT_LED_BLINK - LedCtrl |= PHY_M_LEDC_RX_CTRL | PHY_M_LEDC_TX_CTRL; -#endif /* ACT_LED_BLINK */ + LedOver = 0; -#ifdef DUP_LED_NORMAL - LedCtrl |= PHY_M_LEDC_DP_CTRL; -#endif /* DUP_LED_NORMAL */ + BlinkCtrl = pAC->GIni.GILedBlinkCtrl; - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl); + if ((BlinkCtrl & SK_ACT_LED_BLINK) != 0) { -#endif /* VCPU */ + if (ChipId == CHIP_ID_YUKON_FE) { + /* on 88E3082 these bits are at 11..9 (shifted left) */ + LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, &Word); + + /* delete ACT LED control bits */ + Word &= ~PHY_M_FELP_LED1_MSK; + /* change ACT LED control to blink mode */ + Word |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, Word); + } + else if (ChipId == CHIP_ID_YUKON_XL || ChipId == CHIP_ID_YUKON_EC_U) { + /* save page register */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg); + + /* select page 3 to access LED control register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 3); + + LedConf = PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ + PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ + PHY_M_LEDC_STA0_CTRL(7); /* 1000 Mbps */ + + Mode = 7; /* 10 Mbps: On */ + + if (ChipId == CHIP_ID_YUKON_XL) { + /* set Polarity Control register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_STAT, (SK_U16) + (PHY_M_POLC_LS1_P_MIX(4) | PHY_M_POLC_IS0_P_MIX(4) | + PHY_M_POLC_LOS_CTRL(2) | PHY_M_POLC_INIT_CTRL(2) | + PHY_M_POLC_STA1_CTRL(2) | PHY_M_POLC_STA0_CTRL(2))); + } + else if (ChipId == CHIP_ID_YUKON_EC_U) { + /* check for LINK_LED mux */ + if ((BlinkCtrl & SK_LED_LINK_MUX_P60) != 0) { + + SK_IN16(pAC, GPHY_CTRL, &Word); + + Word |= GPC_LED_CONF_VAL(4); + + /* set GPHY LED Config */ + SK_OUT16(pAC, GPHY_CTRL, Word); + } + else { + Mode = 8; /* Forced Off */ + } + + /* set Blink Rate in LED Timer Control Register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, + LedCtrl | (SK_U16)PHY_M_LED_BLINK_RT(BLINK_84MS)); + } + + LedConf |= PHY_M_LEDC_INIT_CTRL(Mode); + + /* set LED Function Control register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, LedConf); + +#if (defined(SK_DIAG) || (defined(DEBUG) && !defined(SK_SLIM))) + /* select page 6 to access Packet Generation register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6); + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhyCtrl); + + PhyCtrl |= BIT_4S; /* enable CRC checker */ + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhyCtrl); +#endif /* SK_DIAG || (DEBUG && !SK_SLIM) */ + + /* restore page register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg); + } + else { + /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ + LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; + + /* on PHY 88E1111 there is a change for LED control */ + if (ChipId == CHIP_ID_YUKON_EC && + (BlinkCtrl & SK_DUAL_LED_ACT_LNK) != 0) { + /* Yukon-EC needs setting of 2 bits: 0,6=11) */ + LedCtrl |= PHY_M_LEDC_TX_C_LSB; + } + /* turn off the Rx LED (LED_RX) */ + LedOver |= PHY_M_LED_MO_RX(MO_LED_OFF); + } + } + + if ((BlinkCtrl & SK_DUP_LED_NORMAL) != 0) { + /* disable blink mode (LED_DUPLEX) on collisions */ + LedCtrl |= PHY_M_LEDC_DP_CTRL; + } + + if (ChipId == CHIP_ID_YUKON_EC_U) { + if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) { + /* apply fixes in PHY AFE */ + SkGmPhyWrite(pAC, IoC, Port, 22, 255); + /* increase differential signal amplitude in 10BASE-T */ + SkGmPhyWrite(pAC, IoC, Port, 24, 0xaa99); + SkGmPhyWrite(pAC, IoC, Port, 23, 0x2011); + + /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ + SkGmPhyWrite(pAC, IoC, Port, 24, 0xa204); + SkGmPhyWrite(pAC, IoC, Port, 23, 0x2002); + + /* set page register to 0 */ + SkGmPhyWrite(pAC, IoC, Port, 22, 0); + } + } + else { + /* no effect on Yukon-XL */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl); + +#ifndef SK_SLIM + if ((BlinkCtrl & SK_LED_LINK100_ON) != 0) { + /* only in forced 100 Mbps mode */ + if (!AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_100MBPS) { + /* turn on 100 Mbps LED (LED_LINK100) */ + LedOver |= PHY_M_LED_MO_100(MO_LED_ON); + } + } +#endif /* !SK_SLIM */ + + if (LedOver != 0) { + /* set Manual LED Override */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_OVER, LedOver); + } + } #ifdef SK_DIAG - c_print("Set PHY Ctrl=0x%04X\n", PhyCtrl); - c_print("Set 1000 B-T=0x%04X\n", C1000BaseT); - c_print("Set Auto-Neg=0x%04X\n", AutoNegAdv); - c_print("Set Ext Ctrl=0x%04X\n", ExtPhyCtrl); + c_print("Set PHY Ctrl = 0x%04X\n", PhyCtrl); + c_print("Set 1000 B-T = 0x%04X\n", C1000BaseT); + c_print("Set Auto-Neg = 0x%04X\n", AutoNegAdv); + c_print("Set Ext Ctrl = 0x%04X\n", ExtPhyCtrl); #endif /* SK_DIAG */ -#ifndef xDEBUG +#if (defined(SK_DIAG) || (defined(DEBUG) && !defined(SK_SLIM))) /* Read PHY Control */ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("PHY Ctrl Reg.=0x%04X\n", PhyCtrl)); - - /* Read 1000Base-T Control Register */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT); - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("1000B-T Ctrl =0x%04X\n", C1000BaseT)); + ("PHY Ctrl Reg. = 0x%04X\n", PhyCtrl)); /* Read AutoNeg Advertisement Register */ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &AutoNegAdv); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("Auto-Neg. Ad.=0x%04X\n", AutoNegAdv)); + ("Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv)); - /* Read Ext. PHY Specific Control */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl); - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("Ext PHY Ctrl=0x%04X\n", ExtPhyCtrl)); + if (ChipId != CHIP_ID_YUKON_FE) { + /* Read 1000Base-T Control Register */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("1000B-T Ctrl = 0x%04X\n", C1000BaseT)); + + /* Read Ext. PHY Specific Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl)); + } /* Read PHY Status */ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("PHY Stat Reg.=0x%04X\n", PhyStat)); + ("PHY Stat Reg. = 0x%04X\n", PhyStat)); + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat1); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("PHY Stat Reg.=0x%04X\n", PhyStat1)); + ("PHY Stat Reg. = 0x%04X\n", PhyStat1)); /* Read PHY Specific Status */ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("PHY Spec Stat=0x%04X\n", PhySpecStat)); -#endif /* DEBUG */ + ("PHY Spec Stat = 0x%04X\n", PhySpecStat)); +#endif /* SK_DIAG || (DEBUG && !SK_SLIM) */ #ifdef SK_DIAG - c_print("PHY Ctrl Reg=0x%04X\n", PhyCtrl); - c_print("PHY 1000 Reg=0x%04X\n", C1000BaseT); - c_print("PHY AnAd Reg=0x%04X\n", AutoNegAdv); - c_print("Ext Ctrl Reg=0x%04X\n", ExtPhyCtrl); - c_print("PHY Stat Reg=0x%04X\n", PhyStat); - c_print("PHY Stat Reg=0x%04X\n", PhyStat1); - c_print("PHY Spec Reg=0x%04X\n", PhySpecStat); + c_print("PHY Ctrl Reg = 0x%04X\n", PhyCtrl); + c_print("PHY 1000 Reg = 0x%04X\n", C1000BaseT); + c_print("PHY AnAd Reg = 0x%04X\n", AutoNegAdv); + c_print("Ext Ctrl Reg = 0x%04X\n", ExtPhyCtrl); + c_print("PHY Stat Reg = 0x%04X\n", PhyStat); + c_print("PHY Stat Reg = 0x%04X\n", PhyStat1); + c_print("PHY Spec Reg = 0x%04X\n", PhySpecStat); #endif /* SK_DIAG */ + /* enable PHY interrupts */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, (SK_U16)PHY_M_DEF_MSK); +#endif /* !VCPU */ + } /* SkGmInitPhyMarv */ +#endif /* YUKON */ #ifdef OTHER_PHY /****************************************************************************** * - * SkXmInitPhyLone() - Initialize the Level One Phy registers + * SkXmInitPhyLone() - Initialize the Level One PHY registers * - * Description: initializes all the Level One Phy registers + * Description: initializes all the Level One PHY registers * * Note: * @@ -2628,10 +3340,10 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ * nothing */ static void SkXmInitPhyLone( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */ { SK_GEPORT *pPrt; SK_U16 Ctrl1; @@ -2655,19 +3367,20 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ /* Auto-negotiation ? */ if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { /* - * level one spec say: "1000Mbps: manual mode not allowed" + * level one spec say: "1000 Mbps: manual mode not allowed" * but lets see what happens... */ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, ("InitPhyLone: no auto-negotiation Port %d\n", Port)); - /* Set DuplexMode in Config register */ - Ctrl1 = (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0); + /* set DuplexMode in Config register */ + if (pPrt->PLinkMode == SK_LMODE_FULL) { + Ctrl1 |= PHY_CT_DUP_MD; + } /* Determine Master/Slave manually if not already done */ if (pPrt->PMSMode == SK_MS_MODE_AUTO) { Ctrl2 |= PHY_L_1000C_MSE; /* set it to Slave */ } - /* * Do NOT enable Auto-negotiation here. This would hold * the link down because no IDLES are transmitted @@ -2676,9 +3389,9 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ else { SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, ("InitPhyLone: with auto-negotiation Port %d\n", Port)); - /* Set Auto-negotiation advertisement */ + /* set Auto-negotiation advertisement */ - /* Set Full/half duplex capabilities */ + /* set Full/half duplex capabilities */ switch (pPrt->PLinkMode) { case SK_LMODE_AUTOHALF: Ctrl2 |= PHY_L_1000C_AHD; @@ -2694,6 +3407,7 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ SKERR_HWI_E015MSG); } + /* set Flow-control capabilities */ switch (pPrt->PFlowCtrlMode) { case SK_FLOW_MODE_NONE: Ctrl3 |= PHY_L_P_NO_PAUSE; @@ -2714,41 +3428,35 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ /* Restart Auto-negotiation */ Ctrl1 = PHY_CT_ANE | PHY_CT_RE_CFG; - } - /* Initialize LED register here ? */ - /* No. Please do it in SkDgXmitLed() (if required) and swap - init order of LEDs and XMAC. (MAl) */ - /* Write 1000Base-T Control Register */ SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_1000T_CTRL, Ctrl2); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2)); + ("1000B-T Ctrl Reg = 0x%04X\n", Ctrl2)); /* Write AutoNeg Advertisement Register */ SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_AUNE_ADV, Ctrl3); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("Auto-Neg. Adv. Reg=0x%04X\n", Ctrl3)); - + ("Auto-Neg.Adv.Reg = 0x%04X\n", Ctrl3)); if (DoLoop) { - /* Set the Phy Loopback bit, too */ + /* set the PHY Loopback bit, too */ Ctrl1 |= PHY_CT_LOOP; } - /* Write to the Phy control register */ + /* Write to the PHY control register */ SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_CTRL, Ctrl1); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("PHY Control Reg=0x%04X\n", Ctrl1)); + ("PHY Control Reg = 0x%04X\n", Ctrl1)); } /* SkXmInitPhyLone */ /****************************************************************************** * - * SkXmInitPhyNat() - Initialize the National Phy registers + * SkXmInitPhyNat() - Initialize the National PHY registers * - * Description: initializes all the National Phy registers + * Description: initializes all the National PHY registers * * Note: * @@ -2756,10 +3464,10 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ * nothing */ static void SkXmInitPhyNat( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */ { /* todo: National */ } /* SkXmInitPhyNat */ @@ -2778,98 +3486,48 @@ SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ * nothing */ void SkMacInitPhy( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */ { SK_GEPORT *pPrt; pPrt = &pAC->GIni.GP[Port]; - switch (pPrt->PhyType) { - case SK_PHY_XMAC: - SkXmInitPhyXmac(pAC, IoC, Port, DoLoop); - break; - case SK_PHY_BCOM: - SkXmInitPhyBcom(pAC, IoC, Port, DoLoop); - break; - case SK_PHY_MARV_COPPER: - case SK_PHY_MARV_FIBER: - SkGmInitPhyMarv(pAC, IoC, Port, DoLoop); - break; +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { + + switch (pPrt->PhyType) { + case SK_PHY_XMAC: + SkXmInitPhyXmac(pAC, IoC, Port, DoLoop); + break; + case SK_PHY_BCOM: + SkXmInitPhyBcom(pAC, IoC, Port, DoLoop); + break; #ifdef OTHER_PHY - case SK_PHY_LONE: - SkXmInitPhyLone(pAC, IoC, Port, DoLoop); - break; - case SK_PHY_NAT: - SkXmInitPhyNat(pAC, IoC, Port, DoLoop); - break; + case SK_PHY_LONE: + SkXmInitPhyLone(pAC, IoC, Port, DoLoop); + break; + case SK_PHY_NAT: + SkXmInitPhyNat(pAC, IoC, Port, DoLoop); + break; #endif /* OTHER_PHY */ + } } +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { + + SkGmInitPhyMarv(pAC, IoC, Port, DoLoop); + } +#endif /* YUKON */ + } /* SkMacInitPhy */ -#ifndef SK_DIAG -/****************************************************************************** - * - * SkXmAutoNegLipaXmac() - Decides whether Link Partner could do auto-neg - * - * This function analyses the Interrupt status word. If any of the - * Auto-negotiating interrupt bits are set, the PLipaAutoNeg variable - * is set true. - */ -void SkXmAutoNegLipaXmac( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -int Port, /* Port Index (MAC_1 + n) */ -SK_U16 IStatus) /* Interrupt Status word to analyse */ -{ - SK_GEPORT *pPrt; - - pPrt = &pAC->GIni.GP[Port]; - - if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO && - (IStatus & (XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND)) != 0) { - - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNegLipa: AutoNeg detected on Port %d, IStatus=0x%04x\n", - Port, IStatus)); - pPrt->PLipaAutoNeg = SK_LIPA_AUTO; - } -} /* SkXmAutoNegLipaXmac */ - - -/****************************************************************************** - * - * SkMacAutoNegLipaPhy() - Decides whether Link Partner could do auto-neg - * - * This function analyses the PHY status word. - * If any of the Auto-negotiating bits are set, the PLipaAutoNeg variable - * is set true. - */ -void SkMacAutoNegLipaPhy( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -int Port, /* Port Index (MAC_1 + n) */ -SK_U16 PhyStat) /* PHY Status word to analyse */ -{ - SK_GEPORT *pPrt; - - pPrt = &pAC->GIni.GP[Port]; - - if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO && - (PhyStat & PHY_ST_AN_OVER) != 0) { - - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat=0x%04x\n", - Port, PhyStat)); - pPrt->PLipaAutoNeg = SK_LIPA_AUTO; - } -} /* SkMacAutoNegLipaPhy */ -#endif /* SK_DIAG */ - - +#ifdef GENESIS /****************************************************************************** * * SkXmAutoNegDoneXmac() - Auto-negotiation handling @@ -2879,48 +3537,49 @@ SK_U16 PhyStat) /* PHY Status word to analyse */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ static int SkXmAutoNegDoneXmac( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; SK_U16 ResAb; /* Resolved Ability */ - SK_U16 LPAb; /* Link Partner Ability */ + SK_U16 LinkPartAb; /* Link Partner Ability */ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNegDoneXmac, Port %d\n",Port)); + ("AutoNegDoneXmac, Port %d\n", Port)); pPrt = &pAC->GIni.GP[Port]; /* Get PHY parameters */ - SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LPAb); + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LinkPartAb); SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb); - if ((LPAb & PHY_X_AN_RFB) != 0) { + if ((LinkPartAb & PHY_X_AN_RFB) != 0) { /* At least one of the remote fault bit is set */ - /* Error */ - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("AutoNegFail: Remote fault bit set Port %d\n", Port)); pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); } /* Check Duplex mismatch */ if ((ResAb & (PHY_X_RS_HD | PHY_X_RS_FD)) == PHY_X_RS_FD) { - pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOFULL; } else if ((ResAb & (PHY_X_RS_HD | PHY_X_RS_FD)) == PHY_X_RS_HD) { - pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOHALF; } else { /* Error */ - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("AutoNegFail: Duplex mode mismatch Port %d\n", Port)); pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_DUP_CAP); } @@ -2928,26 +3587,27 @@ int Port) /* Port Index (MAC_1 + n) */ /* We are NOT using chapter 4.23 of the Xaqti manual */ /* We are using IEEE 802.3z/D5.0 Table 37-4 */ if ((pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC || - pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) && - (LPAb & PHY_X_P_SYM_MD) != 0) { + pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) && + (LinkPartAb & PHY_X_P_SYM_MD) != 0) { /* Symmetric PAUSE */ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; } else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM && - (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) { - /* Enable PAUSE receive, disable PAUSE transmit */ + (LinkPartAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) { + /* enable PAUSE receive, disable PAUSE transmit */ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; } else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND && - (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) { - /* Disable PAUSE receive, enable PAUSE transmit */ + (LinkPartAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) { + /* disable PAUSE receive, enable PAUSE transmit */ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; } else { /* PAUSE mismatch -> no PAUSE */ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; } - pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; + + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS; return(SK_AND_OK); } /* SkXmAutoNegDoneXmac */ @@ -2962,64 +3622,63 @@ int Port) /* Port Index (MAC_1 + n) */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ static int SkXmAutoNegDoneBcom( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; - SK_U16 LPAb; /* Link Partner Ability */ +#ifdef TEST_ONLY + SK_U16 ResAb; /* Resolved Ability */ +#endif + SK_U16 LinkPartAb; /* Link Partner Ability */ SK_U16 AuxStat; /* Auxiliary Status */ -#if 0 -01-Sep-2000 RA;:;: - SK_U16 ResAb; /* Resolved Ability */ -#endif /* 0 */ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, ("AutoNegDoneBcom, Port %d\n", Port)); pPrt = &pAC->GIni.GP[Port]; /* Get PHY parameters */ - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LPAb); -#if 0 -01-Sep-2000 RA;:;: + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LinkPartAb); +#ifdef TEST_ONLY SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb); -#endif /* 0 */ +#endif SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &AuxStat); - if ((LPAb & PHY_B_AN_RF) != 0) { + if ((LinkPartAb & PHY_B_AN_RF) != 0) { /* Remote fault bit is set: Error */ - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("AutoNegFail: Remote fault bit set Port %d\n", Port)); pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); } /* Check Duplex mismatch */ if ((AuxStat & PHY_B_AS_AN_RES_MSK) == PHY_B_RES_1000FD) { - pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOFULL; } else if ((AuxStat & PHY_B_AS_AN_RES_MSK) == PHY_B_RES_1000HD) { - pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOHALF; } else { /* Error */ - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("AutoNegFail: Duplex mode mismatch Port %d\n", Port)); pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_DUP_CAP); } -#if 0 -01-Sep-2000 RA;:;: +#ifdef TEST_ONLY /* Check Master/Slave resolution */ if ((ResAb & PHY_B_1000S_MSF) != 0) { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("Master/Slave Fault Port %d\n", Port)); pPrt->PAutoNegFail = SK_TRUE; pPrt->PMSStatus = SK_MS_STAT_FAULT; @@ -3028,32 +3687,35 @@ int Port) /* Port Index (MAC_1 + n) */ pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE; -#endif /* 0 */ +#endif - /* Check PAUSE mismatch */ + /* Check PAUSE mismatch ??? */ /* We are using IEEE 802.3z/D5.0 Table 37-4 */ if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PAUSE_MSK) { /* Symmetric PAUSE */ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; } else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRR) { - /* Enable PAUSE receive, disable PAUSE transmit */ + /* enable PAUSE receive, disable PAUSE transmit */ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; } else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRT) { - /* Disable PAUSE receive, enable PAUSE transmit */ + /* disable PAUSE receive, enable PAUSE transmit */ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; } else { /* PAUSE mismatch -> no PAUSE */ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; } - pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; + + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS; return(SK_AND_OK); } /* SkXmAutoNegDoneBcom */ +#endif /* GENESIS */ +#ifdef YUKON /****************************************************************************** * * SkGmAutoNegDoneMarv() - Auto-negotiation handling @@ -3063,99 +3725,184 @@ int Port) /* Port Index (MAC_1 + n) */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ static int SkGmAutoNegDoneMarv( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; - SK_U16 LPAb; /* Link Partner Ability */ SK_U16 ResAb; /* Resolved Ability */ SK_U16 AuxStat; /* Auxiliary Status */ + SK_U8 PauseMode; /* Pause Mode */ +#ifndef SK_SLIM + SK_U16 LinkPartAb; /* Link Partner Ability */ +#ifndef SK_DIAG + SK_EVPARA Para; +#endif /* !SK_DIAG */ +#endif /* !SK_SLIM */ + + /* set Pause On */ + PauseMode = (SK_U8)GMC_PAUSE_ON; SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, ("AutoNegDoneMarv, Port %d\n", Port)); + pPrt = &pAC->GIni.GP[Port]; /* Get PHY parameters */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LPAb); + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LinkPartAb); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Link P.Abil. = 0x%04X\n", LinkPartAb)); - if ((LPAb & PHY_M_AN_RF) != 0) { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + if ((LinkPartAb & PHY_M_AN_RF) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("AutoNegFail: Remote fault bit set Port %d\n", Port)); pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); } - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb); +#ifndef SK_SLIM + if (pAC->GIni.GICopperType) { + /* Read PHY Auto-Negotiation Expansion */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &LinkPartAb); - /* Check Master/Slave resolution */ - if ((ResAb & PHY_B_1000S_MSF) != 0) { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("Master/Slave Fault Port %d\n", Port)); - pPrt->PAutoNegFail = SK_TRUE; - pPrt->PMSStatus = SK_MS_STAT_FAULT; - return(SK_AND_OTHER); + if ((LinkPartAb & PHY_ANE_LP_CAP) == 0) { + +#ifndef SK_DIAG + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n", + LinkPartAb)); + +#ifndef NDIS_MINIPORT_DRIVER + SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_HWI_E025, SKERR_HWI_E025MSG); +#endif + + Para.Para64 = Port; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_LIPA_NOT_AN_ABLE, Para); +#else + c_print("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n", + LinkPartAb); +#endif /* !SK_DIAG */ + + if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) && + pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) { + /* set used link speed */ + pPrt->PLinkSpeedUsed = pPrt->PLinkSpeed; + + /* Set Link Mode Status */ + pPrt->PLinkModeStatus = (pPrt->PLinkModeConf == SK_LMODE_FULL) ? + SK_LMODE_STAT_FULL : SK_LMODE_STAT_HALF; + + return(SK_AND_OK); + } + } } +#endif /* !SK_SLIM */ - pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? - (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE; + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) { + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb); + + /* Check Master/Slave resolution */ + if ((ResAb & PHY_B_1000S_MSF) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("Master/Slave Fault Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + return(SK_AND_OTHER); + } + + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? + (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE; + } /* Read PHY Specific Status */ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &AuxStat); /* Check Speed & Duplex resolved */ if ((AuxStat & PHY_M_PS_SPDUP_RES) == 0) { - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNegFail: Speed & Duplex not resolved Port %d\n", Port)); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("AutoNegFail: Speed & Duplex not resolved, Port %d\n", Port)); pPrt->PAutoNegFail = SK_TRUE; - pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN; + return(SK_AND_DUP_CAP); } - if ((AuxStat & PHY_M_PS_FULL_DUP) != 0) { - pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + pPrt->PLinkModeStatus = (SK_U8)(((AuxStat & PHY_M_PS_FULL_DUP) != 0) ? + SK_LMODE_STAT_AUTOFULL : SK_LMODE_STAT_AUTOHALF); + + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) { + /* set used link speed */ + pPrt->PLinkSpeedUsed = (SK_U8)(((AuxStat & PHY_M_PS_SPEED_100) != 0) ? + SK_LSPEED_STAT_100MBPS : SK_LSPEED_STAT_10MBPS); } else { - pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + /* set used link speed */ + switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) { + case (unsigned)PHY_M_PS_SPEED_1000: + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS; + break; + case PHY_M_PS_SPEED_100: + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS; + break; + default: + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS; + } + + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL || + pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) { + /* Tx & Rx Pause Enabled bits are at 9..8 */ + AuxStat >>= 6; + + if (!pAC->GIni.GICopperType) { + /* always 1000 Mbps on fiber */ + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS; + } + } + + AuxStat &= PHY_M_PS_PAUSE_MSK; + /* We are using IEEE 802.3z/D5.0 Table 37-4 */ + if (AuxStat == PHY_M_PS_PAUSE_MSK) { + /* Symmetric PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; + } + else if (AuxStat == PHY_M_PS_RX_P_EN) { + /* enable PAUSE receive, disable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; + } + else if (AuxStat == PHY_M_PS_TX_P_EN) { + /* disable PAUSE receive, enable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; + } + else { + /* PAUSE mismatch -> no PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + } } - /* Check PAUSE mismatch */ - /* We are using IEEE 802.3z/D5.0 Table 37-4 */ - if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_PAUSE_MSK) { - /* Symmetric PAUSE */ - pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; - } - else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_RX_P_EN) { - /* Enable PAUSE receive, disable PAUSE transmit */ - pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; - } - else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_TX_P_EN) { - /* Disable PAUSE receive, enable PAUSE transmit */ - pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; - } - else { - /* PAUSE mismatch -> no PAUSE */ - pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("LinkSpeedUsed = %d\n", pPrt->PLinkSpeedUsed)); + + if ((pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE) || + /* disable Pause also for 10/100 Mbps in half duplex mode */ + ((pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U) && + (pPrt->PLinkSpeedUsed < (SK_U8)SK_LSPEED_STAT_1000MBPS) && + pPrt->PLinkModeStatus == (SK_U8)SK_LMODE_STAT_AUTOHALF)) { + + /* set Pause Off */ + PauseMode = (SK_U8)GMC_PAUSE_OFF; } - /* set used link speed */ - switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) { - case (unsigned)PHY_M_PS_SPEED_1000: - pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; - break; - case PHY_M_PS_SPEED_100: - pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_100MBPS; - break; - default: - pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_10MBPS; - } + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode); return(SK_AND_OK); } /* SkGmAutoNegDoneMarv */ +#endif /* YUKON */ #ifdef OTHER_PHY @@ -3168,65 +3915,63 @@ int Port) /* Port Index (MAC_1 + n) */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ static int SkXmAutoNegDoneLone( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; SK_U16 ResAb; /* Resolved Ability */ - SK_U16 LPAb; /* Link Partner Ability */ + SK_U16 LinkPartAb; /* Link Partner Ability */ SK_U16 QuickStat; /* Auxiliary Status */ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("AutoNegDoneLone, Port %d\n",Port)); + ("AutoNegDoneLone, Port %d\n", Port)); pPrt = &pAC->GIni.GP[Port]; /* Get PHY parameters */ - SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LPAb); + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LinkPartAb); SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ResAb); SkXmPhyRead(pAC, IoC, Port, PHY_LONE_Q_STAT, &QuickStat); - if ((LPAb & PHY_L_AN_RF) != 0) { + if ((LinkPartAb & PHY_L_AN_RF) != 0) { /* Remote fault bit is set */ - /* Error */ - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("AutoNegFail: Remote fault bit set Port %d\n", Port)); pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); } /* Check Duplex mismatch */ if ((QuickStat & PHY_L_QS_DUP_MOD) != 0) { - pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOFULL; } else { - pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOHALF; } /* Check Master/Slave resolution */ if ((ResAb & PHY_L_1000S_MSF) != 0) { /* Error */ - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, ("Master/Slave Fault Port %d\n", Port)); pPrt->PAutoNegFail = SK_TRUE; pPrt->PMSStatus = SK_MS_STAT_FAULT; return(SK_AND_OTHER); } - else if (ResAb & PHY_L_1000S_MSR) { - pPrt->PMSStatus = SK_MS_STAT_MASTER; - } - else { - pPrt->PMSStatus = SK_MS_STAT_SLAVE; - } + + pPrt->PMSStatus = ((ResAb & PHY_L_1000S_MSR) != 0) ? + (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE; /* Check PAUSE mismatch */ /* We are using IEEE 802.3z/D5.0 Table 37-4 */ /* we must manually resolve the abilities here */ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + switch (pPrt->PFlowCtrlMode) { case SK_FLOW_MODE_NONE: /* default */ @@ -3234,7 +3979,7 @@ int Port) /* Port Index (MAC_1 + n) */ case SK_FLOW_MODE_LOC_SEND: if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) == (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) { - /* Disable PAUSE receive, enable PAUSE transmit */ + /* disable PAUSE receive, enable PAUSE transmit */ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; } break; @@ -3247,7 +3992,7 @@ int Port) /* Port Index (MAC_1 + n) */ case SK_FLOW_MODE_SYM_OR_REM: if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) == PHY_L_QS_AS_PAUSE) { - /* Enable PAUSE receive, disable PAUSE transmit */ + /* enable PAUSE receive, disable PAUSE transmit */ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; } else if ((QuickStat & PHY_L_QS_PAUSE) != 0) { @@ -3273,12 +4018,12 @@ int Port) /* Port Index (MAC_1 + n) */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ static int SkXmAutoNegDoneNat( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { /* todo: National */ @@ -3295,46 +4040,60 @@ int Port) /* Port Index (MAC_1 + n) */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ -int SkMacAutoNegDone( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +int SkMacAutoNegDone( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; int Rtv; + Rtv = SK_AND_OK; + pPrt = &pAC->GIni.GP[Port]; - switch (pPrt->PhyType) { - case SK_PHY_XMAC: - Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port); - break; - case SK_PHY_BCOM: - Rtv = SkXmAutoNegDoneBcom(pAC, IoC, Port); - break; - case SK_PHY_MARV_COPPER: - case SK_PHY_MARV_FIBER: - Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port); - break; +#ifdef GENESIS + if (pAC->GIni.GIGenesis) { + + switch (pPrt->PhyType) { + + case SK_PHY_XMAC: + Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port); + break; + case SK_PHY_BCOM: + Rtv = SkXmAutoNegDoneBcom(pAC, IoC, Port); + break; #ifdef OTHER_PHY - case SK_PHY_LONE: - Rtv = SkXmAutoNegDoneLone(pAC, IoC, Port); - break; - case SK_PHY_NAT: - Rtv = SkXmAutoNegDoneNat(pAC, IoC, Port); - break; + case SK_PHY_LONE: + Rtv = SkXmAutoNegDoneLone(pAC, IoC, Port); + break; + case SK_PHY_NAT: + Rtv = SkXmAutoNegDoneNat(pAC, IoC, Port); + break; #endif /* OTHER_PHY */ - default: - return(SK_AND_OTHER); + default: + return(SK_AND_OTHER); + } } +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { + + Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port); + } +#endif /* YUKON */ if (Rtv != SK_AND_OK) { return(Rtv); } + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done Port %d\n", Port)); + /* We checked everything and may now enable the link */ pPrt->PAutoNegFail = SK_FALSE; @@ -3344,6 +4103,8 @@ int Port) /* Port Index (MAC_1 + n) */ } /* SkMacAutoNegDone */ +#ifndef SK_SLIM +#ifdef GENESIS /****************************************************************************** * * SkXmSetRxTxEn() - Special Set Rx/Tx Enable and some features in XMAC @@ -3356,7 +4117,7 @@ int Port) /* Port Index (MAC_1 + n) */ */ static void SkXmSetRxTxEn( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ int Para) /* Parameter to set: MAC or PHY LoopBack, Duplex Mode */ { @@ -3397,8 +4158,10 @@ int Para) /* Parameter to set: MAC or PHY LoopBack, Duplex Mode */ XM_IN16(IoC, Port, XM_MMU_CMD, &Word); } /* SkXmSetRxTxEn */ +#endif /* GENESIS */ +#ifdef YUKON /****************************************************************************** * * SkGmSetRxTxEn() - Special Set Rx/Tx Enable and some features in GMAC @@ -3411,7 +4174,7 @@ int Para) /* Parameter to set: MAC or PHY LoopBack, Duplex Mode */ */ static void SkGmSetRxTxEn( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ int Para) /* Parameter to set: MAC LoopBack, Duplex Mode */ { @@ -3439,10 +4202,8 @@ int Para) /* Parameter to set: MAC LoopBack, Duplex Mode */ GM_OUT16(IoC, Port, GM_GP_CTRL, Ctrl | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); - /* dummy read to ensure writing */ - GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl); - } /* SkGmSetRxTxEn */ +#endif /* YUKON */ /****************************************************************************** @@ -3455,20 +4216,26 @@ int Para) /* Parameter to set: MAC LoopBack, Duplex Mode */ */ void SkMacSetRxTxEn( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ int Para) { +#ifdef GENESIS if (pAC->GIni.GIGenesis) { SkXmSetRxTxEn(pAC, IoC, Port, Para); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { SkGmSetRxTxEn(pAC, IoC, Port, Para); } +#endif /* YUKON */ } /* SkMacSetRxTxEn */ +#endif /* !SK_SLIM */ /****************************************************************************** @@ -3482,14 +4249,16 @@ int Para) * != 0 Error happened */ int SkMacRxTxEnable( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; SK_U16 Reg; /* 16-bit register value */ SK_U16 IntMask; /* MAC interrupt mask */ +#ifdef GENESIS SK_U16 SWord; +#endif pPrt = &pAC->GIni.GP[Port]; @@ -3499,13 +4268,14 @@ int Port) /* Port Index (MAC_1 + n) */ } if ((pPrt->PLinkMode == SK_LMODE_AUTOHALF || - pPrt->PLinkMode == SK_LMODE_AUTOFULL || - pPrt->PLinkMode == SK_LMODE_AUTOBOTH) && - pPrt->PAutoNegFail) { + pPrt->PLinkMode == SK_LMODE_AUTOFULL || + pPrt->PLinkMode == SK_LMODE_AUTOBOTH) && + pPrt->PAutoNegFail) { /* Auto-negotiation is not done or failed */ return(0); } +#ifdef GENESIS if (pAC->GIni.GIGenesis) { /* set Duplex Mode and Pause Mode */ SkXmInitDupMd(pAC, IoC, Port); @@ -3532,6 +4302,7 @@ int Port) /* Port Index (MAC_1 + n) */ /* disable GP0 interrupt bit */ IntMask |= XM_IS_INP_ASS; } + XM_OUT16(IoC, Port, XM_IMSK, IntMask); /* get MMU Command Reg. */ @@ -3553,7 +4324,8 @@ int Port) /* Port Index (MAC_1 + n) */ SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord); SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, (SK_U16)(SWord & ~PHY_B_AC_DIS_PM)); - SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK, + (SK_U16)PHY_B_DEF_MSK); break; #ifdef OTHER_PHY case SK_PHY_LONE: @@ -3570,7 +4342,10 @@ int Port) /* Port Index (MAC_1 + n) */ /* enable Rx/Tx */ XM_OUT16(IoC, Port, XM_MMU_CMD, Reg | XM_MMU_ENA_RX | XM_MMU_ENA_TX); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { /* * Initialize the Interrupt Mask Register. Default IRQs are... * - Rx Counter Event Overflow @@ -3579,12 +4354,12 @@ int Port) /* Port Index (MAC_1 + n) */ */ IntMask = GMAC_DEF_MSK; -#ifdef DEBUG +#if (defined(DEBUG) || defined(YUK2)) && (!defined(SK_SLIM)) /* add IRQ for Receive FIFO Overrun */ IntMask |= GM_IS_RX_FF_OR; -#endif /* DEBUG */ +#endif - SK_OUT8(IoC, GMAC_IRQ_MSK, (SK_U8)IntMask); + SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), (SK_U8)IntMask); /* get General Purpose Control */ GM_IN16(IoC, Port, GM_GP_CTRL, &Reg); @@ -3593,16 +4368,31 @@ int Port) /* Port Index (MAC_1 + n) */ pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) { /* set to Full Duplex */ Reg |= GM_GPCR_DUP_FULL; + +#ifndef SK_SLIM + if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) && + pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) { + /* disable auto-update for speed, duplex and flow-control */ + Reg |= GM_GPCR_AU_ALL_DIS; + } +#endif /* !SK_SLIM */ + } + + /* WA for dev. #4.209 */ + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U && + pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) { + /* enable/disable Store & Forward mode for TX */ + SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), + pPrt->PLinkSpeedUsed != (SK_U8)SK_LSPEED_STAT_1000MBPS ? + TX_STFW_ENA : TX_STFW_DIS); } /* enable Rx/Tx */ GM_OUT16(IoC, Port, GM_GP_CTRL, Reg | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); - -#ifndef VCPU - /* Enable all PHY interrupts */ - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); -#endif /* VCPU */ } +#endif /* YUKON */ + + pAC->GIni.GP[Port].PState = SK_PRT_RUN; return(0); @@ -3619,29 +4409,36 @@ int Port) /* Port Index (MAC_1 + n) */ */ void SkMacRxTxDisable( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_U16 Word; +#ifdef GENESIS if (pAC->GIni.GIGenesis) { XM_IN16(IoC, Port, XM_MMU_CMD, &Word); - XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); + Word &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); + + XM_OUT16(IoC, Port, XM_MMU_CMD, Word); /* dummy read to ensure writing */ XM_IN16(IoC, Port, XM_MMU_CMD, &Word); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { GM_IN16(IoC, Port, GM_GP_CTRL, &Word); - GM_OUT16(IoC, Port, GM_GP_CTRL, Word & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)); + Word &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); - /* dummy read to ensure writing */ - GM_IN16(IoC, Port, GM_GP_CTRL, &Word); + GM_OUT16(IoC, Port, GM_GP_CTRL, Word); } +#endif /* YUKON */ + } /* SkMacRxTxDisable */ @@ -3655,27 +4452,30 @@ int Port) /* Port Index (MAC_1 + n) */ */ void SkMacIrqDisable( SK_AC *pAC, /* Adapter Context */ -SK_IOC IoC, /* IO context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; +#ifdef GENESIS SK_U16 Word; +#endif pPrt = &pAC->GIni.GP[Port]; +#ifdef GENESIS if (pAC->GIni.GIGenesis) { /* disable all XMAC IRQs */ XM_OUT16(IoC, Port, XM_IMSK, 0xffff); - /* Disable all PHY interrupts */ + /* disable all PHY interrupts */ switch (pPrt->PhyType) { case SK_PHY_BCOM: /* Make sure that PHY is initialized */ if (pPrt->PState != SK_PRT_RESET) { /* NOT allowed if BCOM is in RESET state */ /* Workaround BCOM Errata (#10523) all BCom */ - /* Disable Power Management if link is down */ + /* disable Power Management if link is down */ SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Word); SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, (SK_U16)(Word | PHY_B_AC_DIS_PM)); @@ -3693,15 +4493,20 @@ int Port) /* Port Index (MAC_1 + n) */ #endif /* OTHER_PHY */ } } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { /* disable all GMAC IRQs */ - SK_OUT8(IoC, GMAC_IRQ_MSK, 0); + SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0); #ifndef VCPU - /* Disable all PHY interrupts */ + /* disable all PHY interrupts */ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0); -#endif /* VCPU */ +#endif /* !VCPU */ } +#endif /* YUKON */ + } /* SkMacIrqDisable */ @@ -3710,31 +4515,75 @@ int Port) /* Port Index (MAC_1 + n) */ * * SkXmSendCont() - Enable / Disable Send Continuous Mode * - * Description: enable / disable Send Continuous Mode on XMAC + * Description: enable / disable Send Continuous Mode on XMAC resp. + * Packet Generation on GPHY * * Returns: * nothing */ void SkXmSendCont( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_BOOL Enable) /* Enable / Disable */ { + SK_U16 Reg; + SK_U16 Save; SK_U32 MdReg; - XM_IN32(IoC, Port, XM_MODE, &MdReg); + if (pAC->GIni.GIGenesis) { + XM_IN32(IoC, Port, XM_MODE, &MdReg); - if (Enable) { - MdReg |= XM_MD_TX_CONT; + if (Enable) { + MdReg |= XM_MD_TX_CONT; + } + else { + MdReg &= ~XM_MD_TX_CONT; + } + /* setup Mode Register */ + XM_OUT32(IoC, Port, XM_MODE, MdReg); } else { - MdReg &= ~XM_MD_TX_CONT; - } - /* setup Mode Register */ - XM_OUT32(IoC, Port, XM_MODE, MdReg); + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) { + /* select page 18 */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 18); + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PAGE_DATA, &Reg); + + Reg &= ~0x003c; /* clear bits 5..2 */ + + if (Enable) { + /* enable packet generation, 1518 byte length */ + Reg |= (BIT_5S | BIT_3S); + } + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, Reg); + } + else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) { + /* save page register */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &Save); + + /* select page 6 to access Packet Generation register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6); + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Reg); + + Reg &= ~0x003f; /* clear bits 5..0 */ + + if (Enable) { + /* enable packet generation, 1518 byte length */ + Reg |= (BIT_3S | BIT_1S); + } + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Reg); + + /* restore page register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, Save); + } + } + +} /* SkXmSendCont */ -} /* SkXmSendCont*/ /****************************************************************************** * @@ -3746,8 +4595,8 @@ SK_BOOL Enable) /* Enable / Disable */ * nothing */ void SkMacTimeStamp( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_BOOL Enable) /* Enable / Disable */ { @@ -3775,12 +4624,76 @@ SK_BOOL Enable) /* Enable / Disable */ TimeCtrl = GMT_ST_STOP | GMT_ST_CLR_IRQ; } /* Start/Stop Time Stamp Timer */ - SK_OUT8(pAC, GMAC_TI_ST_CTRL, TimeCtrl); + SK_OUT8(IoC, GMAC_TI_ST_CTRL, TimeCtrl); } + } /* SkMacTimeStamp*/ -#else /* SK_DIAG */ +#else /* !SK_DIAG */ +#ifdef GENESIS +/****************************************************************************** + * + * SkXmAutoNegLipaXmac() - Decides whether Link Partner could do auto-neg + * + * This function analyses the Interrupt status word. If any of the + * Auto-negotiating interrupt bits are set, the PLipaAutoNeg variable + * is set true. + */ +void SkXmAutoNegLipaXmac( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U16 IStatus) /* Interrupt Status word to analyse */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO && + (IStatus & (XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND)) != 0) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegLipa: AutoNeg detected on Port %d, IStatus = 0x%04X\n", + Port, IStatus)); + + pPrt->PLipaAutoNeg = SK_LIPA_AUTO; + } +} /* SkXmAutoNegLipaXmac */ +#endif /* GENESIS */ + + +/****************************************************************************** + * + * SkMacAutoNegLipaPhy() - Decides whether Link Partner could do auto-neg + * + * This function analyses the PHY status word. + * If any of the Auto-negotiating bits are set, the PLipaAutoNeg variable + * is set true. + */ +void SkMacAutoNegLipaPhy( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U16 PhyStat) /* PHY Status word to analyse */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO && + (PhyStat & PHY_ST_AN_OVER) != 0) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat = 0x%04X\n", + Port, PhyStat)); + + pPrt->PLipaAutoNeg = SK_LIPA_AUTO; + } +} /* SkMacAutoNegLipaPhy */ + + +#ifdef GENESIS /****************************************************************************** * * SkXmIrq() - Interrupt Service Routine @@ -3789,7 +4702,7 @@ SK_BOOL Enable) /* Enable / Disable */ * * Note: * With an external PHY, some interrupt bits are not meaningfull any more: - * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE + * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE * - LinkPartnerReqConfig (bit #10) XM_IS_LIPA_RC * - Page Received (bit #9) XM_IS_RX_PAGE * - NextPageLoadedForXmt (bit #8) XM_IS_TX_PAGE @@ -3800,15 +4713,19 @@ SK_BOOL Enable) /* Enable / Disable */ * Returns: * nothing */ -void SkXmIrq( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +static void SkXmIrq( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; - SK_EVPARA Para; SK_U16 IStatus; /* Interrupt status read from the XMAC */ SK_U16 IStatus2; +#ifdef SK_SLIM + SK_U64 OverflowStatus; +#else + SK_EVPARA Para; +#endif /* SK_SLIM */ pPrt = &pAC->GIni.GP[Port]; @@ -3826,7 +4743,7 @@ int Port) /* Port Index (MAC_1 + n) */ } SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, - ("XmacIrq Port %d Isr 0x%04x\n", Port, IStatus)); + ("XmacIrq Port %d Isr 0x%04X\n", Port, IStatus)); if (!pPrt->PHWLinkUp) { /* Spurious XMAC interrupt */ @@ -3840,7 +4757,7 @@ int Port) /* Port Index (MAC_1 + n) */ XM_IN16(IoC, Port, XM_ISRC, &IStatus2); SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, - ("SkXmIrq: Link async. Double check Port %d 0x%04x 0x%04x\n", + ("SkXmIrq: Link async. Double check Port %d 0x%04X 0x%04X\n", Port, IStatus, IStatus2)); IStatus &= ~XM_IS_INP_ASS; IStatus |= IStatus2; @@ -3889,9 +4806,15 @@ int Port) /* Port Index (MAC_1 + n) */ /* Combined Tx & Rx Counter Overflow SIRQ Event */ if ((IStatus & (XM_IS_RXC_OV | XM_IS_TXC_OV)) != 0) { +#ifdef SK_SLIM + SkXmOverflowStatus(pAC, IoC, Port, IStatus, &OverflowStatus); +#else +# ifdef SK_PNMI_SUPPORT Para.Para32[0] = (SK_U32)Port; Para.Para32[1] = (SK_U32)IStatus; SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para); +# endif +#endif /* SK_SLIM */ } if ((IStatus & XM_IS_RXF_OV) != 0) { @@ -3914,8 +4837,10 @@ int Port) /* Port Index (MAC_1 + n) */ /* not served here */ } } /* SkXmIrq */ +#endif /* GENESIS */ +#ifdef YUKON /****************************************************************************** * * SkGmIrq() - Interrupt Service Routine @@ -3927,40 +4852,58 @@ int Port) /* Port Index (MAC_1 + n) */ * Returns: * nothing */ -void SkGmIrq( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +static void SkGmIrq( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; - SK_EVPARA Para; SK_U8 IStatus; /* Interrupt status */ +#ifdef SK_SLIM + SK_U64 OverflowStatus; +#else + SK_EVPARA Para; +#endif /* SK_SLIM */ pPrt = &pAC->GIni.GP[Port]; - SK_IN8(IoC, GMAC_IRQ_SRC, &IStatus); + SK_IN8(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &IStatus); +#ifdef XXX /* LinkPartner Auto-negable? */ SkMacAutoNegLipaPhy(pAC, IoC, Port, IStatus); +#endif /* XXX */ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, - ("GmacIrq Port %d Isr 0x%04x\n", Port, IStatus)); + ("GmacIrq Port %d Isr 0x%02X\n", Port, IStatus)); /* Combined Tx & Rx Counter Overflow SIRQ Event */ if (IStatus & (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV)) { /* these IRQs will be cleared by reading GMACs register */ +#ifdef SK_SLIM + SkGmOverflowStatus(pAC, IoC, Port, (SK_U16)IStatus, &OverflowStatus); +#else +# ifdef SK_PNMI_SUPPORT Para.Para32[0] = (SK_U32)Port; Para.Para32[1] = (SK_U32)IStatus; SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para); +# endif +#endif /* SK_SLIM */ } +#ifndef SK_SLIM if (IStatus & GM_IS_RX_FF_OR) { /* clear GMAC Rx FIFO Overrun IRQ */ SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FO); + + Para.Para64 = Port; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RX_OVERFLOW, Para); + #ifdef DEBUG pPrt->PRxOverCnt++; #endif /* DEBUG */ } +#endif /* !SK_SLIM */ if (IStatus & GM_IS_TX_FF_UR) { /* clear GMAC Tx FIFO Underrun IRQ */ @@ -3977,6 +4920,8 @@ int Port) /* Port Index (MAC_1 + n) */ /* not served here */ } } /* SkGmIrq */ +#endif /* YUKON */ + /****************************************************************************** * @@ -3988,23 +4933,29 @@ int Port) /* Port Index (MAC_1 + n) */ * nothing */ void SkMacIrq( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port) /* Port Index (MAC_1 + n) */ { - +#ifdef GENESIS if (pAC->GIni.GIGenesis) { /* IRQ from XMAC */ SkXmIrq(pAC, IoC, Port); } - else { +#endif /* GENESIS */ + +#ifdef YUKON + if (pAC->GIni.GIYukon) { /* IRQ from GMAC */ SkGmIrq(pAC, IoC, Port); } +#endif /* YUKON */ + } /* SkMacIrq */ #endif /* !SK_DIAG */ +#ifdef GENESIS /****************************************************************************** * * SkXmUpdateStats() - Force the XMAC to output the current statistic @@ -4019,8 +4970,8 @@ int Port) /* Port Index (MAC_1 + n) */ * 1: something went wrong */ int SkXmUpdateStats( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ unsigned int Port) /* Port Index (MAC_1 + n) */ { SK_GEPORT *pPrt; @@ -4054,24 +5005,6 @@ unsigned int Port) /* Port Index (MAC_1 + n) */ return(0); } /* SkXmUpdateStats */ -/****************************************************************************** - * - * SkGmUpdateStats() - Force the GMAC to output the current statistic - * - * Description: - * Empty function for GMAC. Statistic data is accessible in direct way. - * - * Returns: - * 0: success - * 1: something went wrong - */ -int SkGmUpdateStats( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -unsigned int Port) /* Port Index (MAC_1 + n) */ -{ - return(0); -} /****************************************************************************** * @@ -4087,11 +5020,11 @@ unsigned int Port) /* Port Index (MAC_1 + n) */ * 1: something went wrong */ int SkXmMacStatistic( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -unsigned int Port, /* Port Index (MAC_1 + n) */ -SK_U16 StatAddr, /* MIB counter base address */ -SK_U32 *pVal) /* ptr to return statistic value */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 StatAddr, /* MIB counter base address */ +SK_U32 SK_FAR *pVal) /* Pointer to return statistic value */ { if ((StatAddr < XM_TXF_OK) || (StatAddr > XM_RXF_MAX_SZ)) { @@ -4105,40 +5038,6 @@ SK_U32 *pVal) /* ptr to return statistic value */ return(0); } /* SkXmMacStatistic */ -/****************************************************************************** - * - * SkGmMacStatistic() - Get GMAC counter value - * - * Description: - * Gets the 32bit counter value. Except for the octet counters - * the lower 32bit are counted in hardware and the upper 32bit - * must be counted in software by monitoring counter overflow interrupts. - * - * Returns: - * 0: success - * 1: something went wrong - */ -int SkGmMacStatistic( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -unsigned int Port, /* Port Index (MAC_1 + n) */ -SK_U16 StatAddr, /* MIB counter base address */ -SK_U32 *pVal) /* ptr to return statistic value */ -{ - - if ((StatAddr < GM_RXF_UC_OK) || (StatAddr > GM_TXE_FIFO_UR)) { - - SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG); - - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("SkGmMacStat: wrong MIB counter 0x%04X\n", StatAddr)); - return(1); - } - - GM_IN32(IoC, Port, StatAddr, pVal); - - return(0); -} /* SkGmMacStatistic */ /****************************************************************************** * @@ -4152,55 +5051,17 @@ SK_U32 *pVal) /* ptr to return statistic value */ * 1: something went wrong */ int SkXmResetCounter( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ unsigned int Port) /* Port Index (MAC_1 + n) */ { XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC); - /* Clear two times according to Errata #3 */ + /* Clear two times according to XMAC Errata #3 */ XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC); return(0); } /* SkXmResetCounter */ -/****************************************************************************** - * - * SkGmResetCounter() - Clear MAC statistic counter - * - * Description: - * Force GMAC to clear its statistic counter. - * - * Returns: - * 0: success - * 1: something went wrong - */ -int SkGmResetCounter( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -unsigned int Port) /* Port Index (MAC_1 + n) */ -{ - SK_U16 Reg; /* Phy Address Register */ - SK_U16 Word; - int i; - - GM_IN16(IoC, Port, GM_PHY_ADDR, &Reg); - -#ifndef VCPU - /* set MIB Clear Counter Mode */ - GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg | GM_PAR_MIB_CLR); - - /* read all MIB Counters with Clear Mode set */ - for (i = 0; i < GM_MIB_CNT_SIZE; i++) { - /* the reset is performed only when the lower 16 bits are read */ - GM_IN16(IoC, Port, GM_MIB_CNT_BASE + 8*i, &Word); - } - - /* clear MIB Clear Counter Mode */ - GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg); -#endif /* !VCPU */ - - return(0); -} /* SkGmResetCounter */ /****************************************************************************** * @@ -4222,11 +5083,11 @@ unsigned int Port) /* Port Index (MAC_1 + n) */ * 1: something went wrong */ int SkXmOverflowStatus( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -unsigned int Port, /* Port Index (MAC_1 + n) */ -SK_U16 IStatus, /* Interupt Status from MAC */ -SK_U64 *pStatus) /* ptr for return overflow status value */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 IStatus, /* Interrupt Status from MAC */ +SK_U64 SK_FAR *pStatus) /* Pointer for return overflow status value */ { SK_U64 Status; /* Overflow status */ SK_U32 RegVal; @@ -4249,6 +5110,105 @@ SK_U64 *pStatus) /* ptr for return overflow status value */ return(0); } /* SkXmOverflowStatus */ +#endif /* GENESIS */ + + +#ifdef YUKON +/****************************************************************************** + * + * SkGmUpdateStats() - Force the GMAC to output the current statistic + * + * Description: + * Empty function for GMAC. Statistic data is accessible in direct way. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkGmUpdateStats( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +unsigned int Port) /* Port Index (MAC_1 + n) */ +{ + return(0); +} + + +/****************************************************************************** + * + * SkGmMacStatistic() - Get GMAC counter value + * + * Description: + * Gets the 32bit counter value. Except for the octet counters + * the lower 32bit are counted in hardware and the upper 32bit + * must be counted in software by monitoring counter overflow interrupts. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkGmMacStatistic( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 StatAddr, /* MIB counter base address */ +SK_U32 SK_FAR *pVal) /* Pointer to return statistic value */ +{ + + if ((StatAddr < GM_RXF_UC_OK) || (StatAddr > GM_TXE_FIFO_UR)) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("SkGmMacStat: wrong MIB counter 0x%04X\n", StatAddr)); + return(1); + } + + GM_IN32(IoC, Port, StatAddr, pVal); + + /* dummy read after GM_IN32() */ + SK_IN16(IoC, B0_RAP, &StatAddr); + + return(0); +} /* SkGmMacStatistic */ + + +/****************************************************************************** + * + * SkGmResetCounter() - Clear MAC statistic counter + * + * Description: + * Force GMAC to clear its statistic counter. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkGmResetCounter( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +unsigned int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 Reg; /* PHY Address Register */ + SK_U16 Word; + int i; + + GM_IN16(IoC, Port, GM_PHY_ADDR, &Reg); + + /* set MIB Clear Counter Mode */ + GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg | GM_PAR_MIB_CLR); + + /* read all MIB Counters with Clear Mode set */ + for (i = 0; i < GM_MIB_CNT_SIZE; i++) { + /* the reset is performed only when the lower 16 bits are read */ + GM_IN16(IoC, Port, GM_MIB_CNT_BASE + 8*i, &Word); + } + + /* clear MIB Clear Counter Mode */ + GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg); + + return(0); +} /* SkGmResetCounter */ /****************************************************************************** @@ -4260,52 +5220,68 @@ SK_U64 *pStatus) /* ptr for return overflow status value */ * resulting counter overflow status is written to , whereas the * the following bit coding is used: * 63:56 - unused - * 55:48 - TxRx interrupt register bit7:0 - * 32:47 - Rx interrupt register + * 55:48 - TxRx interrupt register bit 7:0 + * 47:32 - Rx interrupt register * 31:24 - unused - * 23:16 - TxRx interrupt register bit15:8 - * 15:0 - Tx interrupt register + * 23:16 - TxRx interrupt register bit 15:8 + * 15: 0 - Tx interrupt register * * Returns: * 0: success * 1: something went wrong */ int SkGmOverflowStatus( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ -unsigned int Port, /* Port Index (MAC_1 + n) */ -SK_U16 IStatus, /* Interupt Status from MAC */ -SK_U64 *pStatus) /* ptr for return overflow status value */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 IStatus, /* Interrupt Status from MAC */ +SK_U64 SK_FAR *pStatus) /* Pointer for return overflow status value */ { - SK_U64 Status; /* Overflow status */ SK_U16 RegVal; +#ifndef SK_SLIM + SK_U64 Status; /* Overflow status */ Status = 0; +#endif /* !SK_SLIM */ if ((IStatus & GM_IS_RX_CO_OV) != 0) { /* this register is self-clearing after read */ GM_IN16(IoC, Port, GM_RX_IRQ_SRC, &RegVal); + +#ifndef SK_SLIM Status |= (SK_U64)RegVal << 32; +#endif /* !SK_SLIM */ } if ((IStatus & GM_IS_TX_CO_OV) != 0) { /* this register is self-clearing after read */ GM_IN16(IoC, Port, GM_TX_IRQ_SRC, &RegVal); + +#ifndef SK_SLIM Status |= (SK_U64)RegVal; +#endif /* !SK_SLIM */ } /* this register is self-clearing after read */ GM_IN16(IoC, Port, GM_TR_IRQ_SRC, &RegVal); + +#ifndef SK_SLIM /* Rx overflow interrupt register bits (LoByte)*/ Status |= (SK_U64)((SK_U8)RegVal) << 48; /* Tx overflow interrupt register bits (HiByte)*/ Status |= (SK_U64)(RegVal >> 8) << 16; *pStatus = Status; +#endif /* !SK_SLIM */ + + /* dummy read after GM_IN16() */ + SK_IN16(IoC, B0_RAP, &RegVal); return(0); } /* SkGmOverflowStatus */ + +#ifndef SK_SLIM /****************************************************************************** * * SkGmCableDiagStatus() - Starts / Gets status of cable diagnostic test @@ -4322,12 +5298,17 @@ SK_U64 *pStatus) /* ptr for return overflow status value */ * 2: test in progress */ int SkGmCableDiagStatus( -SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ int Port, /* Port Index (MAC_1 + n) */ SK_BOOL StartTest) /* flag for start / get result */ { int i; + int CableDiagOffs; + int MdiPairs; + int Rtv; + SK_BOOL FastEthernet; + SK_BOOL Yukon2; SK_U16 RegVal; SK_GEPORT *pPrt; @@ -4338,37 +5319,96 @@ SK_BOOL StartTest) /* flag for start / get result */ return(1); } - if (StartTest) { - /* only start the cable test */ - if ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4) { - /* apply TDR workaround from Marvell */ - SkGmPhyWrite(pAC, IoC, Port, 29, 0x001e); + Yukon2 = pAC->GIni.GIChipId == CHIP_ID_YUKON_XL || + pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U; - SkGmPhyWrite(pAC, IoC, Port, 30, 0xcc00); - SkGmPhyWrite(pAC, IoC, Port, 30, 0xc800); - SkGmPhyWrite(pAC, IoC, Port, 30, 0xc400); - SkGmPhyWrite(pAC, IoC, Port, 30, 0xc000); - SkGmPhyWrite(pAC, IoC, Port, 30, 0xc100); + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) { + + CableDiagOffs = PHY_MARV_FE_VCT_TX; + FastEthernet = SK_TRUE; + MdiPairs = 2; + } + else { + CableDiagOffs = Yukon2 ? PHY_MARV_PHY_CTRL : PHY_MARV_CABLE_DIAG; + FastEthernet = SK_FALSE; + MdiPairs = 4; + } + + if (StartTest) { + + /* set to RESET to avoid PortCheckUp */ + pPrt->PState = SK_PRT_RESET; + + /* only start the cable test */ + if (!FastEthernet) { + + if ((((pPrt->PhyId1 & PHY_I1_MOD_NUM) >> 4) == 2) && + ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4)) { + /* apply TDR workaround for model 2, rev. < 4 */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 0x001e); + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xcc00); + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc800); + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc400); + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc000); + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc100); + } + +#ifdef YUKON_DBG + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) { + /* set address to 1 for page 1 */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1); + + /* disable waiting period */ + SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs, + PHY_M_CABD_DIS_WAIT); + } +#endif + if (Yukon2) { + /* set address to 5 for page 5 */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5); + +#ifdef YUKON_DBG + /* disable waiting period */ + SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs + 1, + PHY_M_CABD_DIS_WAIT); +#endif + } + else { + /* set address to 0 for MDI[0] (Page 0) */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0); + } + } + else { + RegVal = PHY_CT_RESET | PHY_CT_SP100; + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, RegVal); + +#ifdef xYUKON_DBG + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, &RegVal); + /* disable waiting period */ + RegVal |= PHY_M_FESC_DIS_WAIT; + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, RegVal); +#endif } - /* set address to 0 for MDI[0] */ - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0); - - /* Read Cable Diagnostic Reg */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal); - /* start Cable Diagnostic Test */ - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, - (SK_U16)(RegVal | PHY_M_CABD_ENA_TEST)); + SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs, PHY_M_CABD_ENA_TEST); return(0); } /* Read Cable Diagnostic Reg */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal); + Rtv = SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal); + + if (Rtv == 2) { + /* PHY read timeout */ + return(3); + } SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, - ("PHY Cable Diag.=0x%04X\n", RegVal)); + ("PHY Cable Diag. = 0x%04X\n", RegVal)); if ((RegVal & PHY_M_CABD_ENA_TEST) != 0) { /* test is running */ @@ -4376,21 +5416,31 @@ SK_BOOL StartTest) /* flag for start / get result */ } /* get the test results */ - for (i = 0; i < 4; i++) { - /* set address to i for MDI[i] */ - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i); + for (i = 0; i < MdiPairs; i++) { + + if (!FastEthernet && !Yukon2) { + /* set address to i for MDI[i] */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i); + } /* get Cable Diagnostic values */ - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal); + SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal); pPrt->PMdiPairLen[i] = (SK_U8)(RegVal & PHY_M_CABD_DIST_MSK); pPrt->PMdiPairSts[i] = (SK_U8)((RegVal & PHY_M_CABD_STAT_MSK) >> 13); + + if (FastEthernet || Yukon2) { + /* get next register */ + CableDiagOffs++; + } } return(0); } /* SkGmCableDiagStatus */ - -#endif /* CONFIG_SK98 */ +#endif /* !SK_SLIM */ +#endif /* YUKON */ /* End of file */ + +#endif diff --git a/drivers/sk98lin/sky2.c b/drivers/sk98lin/sky2.c new file mode 100644 index 0000000..3e9a34e --- /dev/null +++ b/drivers/sk98lin/sky2.c @@ -0,0 +1,2774 @@ +/****************************************************************************** + * + * Name: sky2.c + * Project: Yukon2 specific functions and implementations + * Version: $Revision: 1.35.2.39 $ + * Date: $Date: 2005/09/05 08:59:54 $ + * Purpose: The main driver source module + * + *****************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2005 Marvell. + * + * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet + * Server Adapters. + * + * Author: Ralph Roesler (rroesler@syskonnect.de) + * Mirko Lindner (mlindner@syskonnect.de) + * + * Address all question to: linux@syskonnect.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + *****************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" +#if 0 /* uboot */ +#include +#endif +/****************************************************************************** + * + * Local Function Prototypes + * + *****************************************************************************/ + +static void InitPacketQueues(SK_AC *pAC,int Port); +static void GiveTxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port); +static void GiveRxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port,SK_PACKET *pPacket); +static SK_BOOL HandleReceives(SK_AC *pAC,int Port,SK_U16 Len,SK_U32 FrameStatus,SK_U16 Tcp1,SK_U16 Tcp2,SK_U32 Tist,SK_U16 Vlan); +static void CheckForSendComplete(SK_AC *pAC,SK_IOC IoC,int Port,SK_PKT_QUEUE *pPQ,SK_LE_TABLE *pLETab,unsigned int Done); +static void UnmapAndFreeTxPktBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int TxPort); +static SK_BOOL AllocateAndInitLETables(SK_AC *pAC); +static SK_BOOL AllocatePacketBuffersYukon2(SK_AC *pAC); +static void FreeLETables(SK_AC *pAC); +static void FreePacketBuffers(SK_AC *pAC); +static SK_BOOL AllocAndMapRxBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int Port); +#ifdef CONFIG_SK98LIN_NAPI +static SK_BOOL HandleStatusLEs(SK_AC *pAC,int *WorkDone,int WorkToDo); +#else +static SK_BOOL HandleStatusLEs(SK_AC *pAC); +#endif + +extern void SkGeCheckTimer (DEV_NET *pNet); +extern void SkLocalEventQueue( SK_AC *pAC, + SK_U32 Class, + SK_U32 Event, + SK_U32 Param1, + SK_U32 Param2, + SK_BOOL Flag); +extern void SkLocalEventQueue64( SK_AC *pAC, + SK_U32 Class, + SK_U32 Event, + SK_U64 Param, + SK_BOOL Flag); + +/****************************************************************************** + * + * Local Variables + * + *****************************************************************************/ + +#define MAX_NBR_RX_BUFFERS_IN_HW 0x15 +static SK_U8 NbrRxBuffersInHW; +#define FLUSH_OPC(le) + +/****************************************************************************** + * + * Global Functions + * + *****************************************************************************/ + +int SkY2Xmit( struct sk_buff *skb, struct SK_NET_DEVICE *dev); +void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port); + +/***************************************************************************** + * + * SkY2RestartStatusUnit - restarts teh status unit + * + * Description: + * Reenables the status unit after any De-Init (e.g. when altering + * the sie of the MTU via 'ifconfig a.b.c.d mtu xxx') + * + * Returns: N/A + */ +void SkY2RestartStatusUnit( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("==> SkY2RestartStatusUnit\n")); + + /* + ** It might be that the TX timer is not started. Therefore + ** it is initialized here -> to be more investigated! + */ + SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10)); + + pAC->StatusLETable.Done = 0; + pAC->StatusLETable.Put = 0; + pAC->StatusLETable.HwPut = 0; + SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("<== SkY2RestartStatusUnit\n")); +} + +/***************************************************************************** + * + * SkY2RlmtSend - sends out a single RLMT notification + * + * Description: + * This function sends out an RLMT frame + * + * Returns: + * > 0 - on succes: the number of bytes in the message + * = 0 - on resource shortage: this frame sent or dropped, now + * the ring is full ( -> set tbusy) + * < 0 - on failure: other problems ( -> return failure to upper layers) + */ +int SkY2RlmtSend ( +SK_AC *pAC, /* pointer to adapter control context */ +int PortNr, /* index of port the packet(s) shall be send to */ +struct sk_buff *pMessage) /* pointer to send-message */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("=== SkY2RlmtSend\n")); + return -1; // temporarily do not send out RLMT frames +#if 0 + return(SkY2Xmit(pMessage, pAC->dev[PortNr])); SkY2Xmit needs device +#endif +} + +/***************************************************************************** + * + * SkY2AllocateResources - Allocates all required resources for Yukon2 + * + * Description: + * This function allocates all memory needed for the Yukon2. + * It maps also RX buffers to the LETables and initializes the + * status list element table. + * + * Returns: + * SK_TRUE, if all resources could be allocated and setup succeeded + * SK_FALSE, if an error + */ +SK_BOOL SkY2AllocateResources ( +SK_AC *pAC) /* pointer to adapter control context */ +{ + int CurrMac; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("==> SkY2AllocateResources\n")); + + /* + ** Initialize the packet queue variables first + */ + for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) { + InitPacketQueues(pAC, CurrMac); + } + + /* + ** Get sufficient memory for the LETables + */ + if (!AllocateAndInitLETables(pAC)) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR, + ("No memory for LETable.\n")); + return(SK_FALSE); + } + + /* + ** Allocate and intialize memory for both RX and TX + ** packet and fragment buffers. On an error, free + ** previously allocated LETable memory and quit. + */ + if (!AllocatePacketBuffersYukon2(pAC)) { + FreeLETables(pAC); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR, + ("No memory for Packetbuffers.\n")); + return(SK_FALSE); + } + + /* + ** Rx and Tx LE tables will be initialized in SkGeOpen() + ** + ** It might be that the TX timer is not started. Therefore + ** it is initialized here -> to be more investigated! + */ + SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10)); + SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable); + + pAC->MaxUnusedRxLeWorking = MAX_UNUSED_RX_LE_WORKING; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("<== SkY2AllocateResources\n")); + + return (SK_TRUE); +} + +/***************************************************************************** + * + * SkY2FreeResources - Frees previously allocated resources of Yukon2 + * + * Description: + * This function frees all previously allocated memory of the Yukon2. + * + * Returns: N/A + */ +void SkY2FreeResources ( +SK_AC *pAC) /* pointer to adapter control context */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("==> SkY2FreeResources\n")); + + FreeLETables(pAC); + FreePacketBuffers(pAC); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("<== SkY2FreeResources\n")); +} + +/***************************************************************************** + * + * SkY2AllocateRxBuffers - Allocates the receive buffers for a port + * + * Description: + * This function allocated all the RX buffers of the Yukon2. + * + * Returns: N/A + */ +void SkY2AllocateRxBuffers ( +SK_AC *pAC, /* pointer to adapter control context */ +SK_IOC IoC, /* I/O control context */ +int Port) /* port index of RX */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("==> SkY2AllocateRxBuffers (Port %c)\n", Port)); + + FillReceiveTableYukon2(pAC, IoC, Port); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("<== SkY2AllocateRxBuffers\n")); +} + +/***************************************************************************** + * + * SkY2FreeRxBuffers - Free's all allocates RX buffers of + * + * Description: + * This function frees all RX buffers of the Yukon2 for a single port + * + * Returns: N/A + */ +void SkY2FreeRxBuffers ( +SK_AC *pAC, /* pointer to adapter control context */ +SK_IOC IoC, /* I/O control context */ +int Port) /* port index of RX */ +{ + SK_PACKET *pSkPacket; + unsigned long Flags; /* for POP/PUSH macros */ + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("==> SkY2FreeRxBuffers (Port %c)\n", Port)); + + if (pAC->RxPort[Port].ReceivePacketTable != NULL) { + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket); + while (pSkPacket != NULL) { + if ((pSkPacket->pFrag) != NULL) { + pci_unmap_page(pAC->PciDev, + (dma_addr_t) pSkPacket->pFrag->pPhys, + pSkPacket->pFrag->FragLen - 2, + PCI_DMA_FROMDEVICE); + + DEV_KFREE_SKB_ANY(pSkPacket->pMBuf); + pSkPacket->pMBuf = NULL; + pSkPacket->pFrag->pPhys = (SK_U64) 0; + pSkPacket->pFrag->pVirt = NULL; + } + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket); + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("<== SkY2FreeRxBuffers\n")); +} + +/***************************************************************************** + * + * SkY2FreeTxBuffers - Free's any currently maintained Tx buffer + * + * Description: + * This function frees the TX buffers of the Yukon2 for a single port + * which might be in use by a transmit action + * + * Returns: N/A + */ +void SkY2FreeTxBuffers ( +SK_AC *pAC, /* pointer to adapter control context */ +SK_IOC IoC, /* I/O control context */ +int Port) /* port index of TX */ +{ + SK_PACKET *pSkPacket; + SK_FRAG *pSkFrag; + unsigned long Flags; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("==> SkY2FreeTxBuffers (Port %c)\n", Port)); + + if (pAC->TxPort[Port][0].TransmitPacketTable != NULL) { + POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket); + while (pSkPacket != NULL) { + if ((pSkFrag = pSkPacket->pFrag) != NULL) { + UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port); + } + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket); + POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket); + } +#if USE_SYNC_TX_QUEUE + POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket); + while (pSkPacket != NULL) { + if ((pSkFrag = pSkPacket->pFrag) != NULL) { + UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port); + } + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket); + POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket); + } +#endif + } + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("<== SkY2FreeTxBuffers\n")); +} + +/***************************************************************************** + * + * SkY2Isr - handle a receive IRQ for all yukon2 cards + * + * Description: + * This function is called when a receive IRQ is set. (only for yukon2) + * HandleReceives does the deferred processing of all outstanding + * interrupt operations. + * + * Returns: N/A + */ +SkIsrRetVar SkY2Isr ( +int irq, /* the irq we have received (might be shared!) */ +void *dev_id, /* current device id */ +struct pt_regs *ptregs) /* not used by our driver */ +{ + struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id; + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + SK_U32 IntSrc; + unsigned long Flags; +#ifndef CONFIG_SK98LIN_NAPI + SK_BOOL handledStatLE = SK_FALSE; +#else + SK_BOOL SetIntMask = SK_FALSE; +#endif + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("==> SkY2Isr\n")); + + SK_IN32(pAC->IoBase, B0_Y2_SP_ISRC2, &IntSrc); + + + if ((IntSrc == 0) && (!pNet->NetConsoleMode)){ + SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("No Interrupt\n ==> SkY2Isr\n")); + return; + } + +#ifdef Y2_RECOVERY + if (pNet->InRecover) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("Already in recover\n ==> SkY2Isr\n")); + SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2); + return; + } +#endif + +#ifdef CONFIG_SK98LIN_NAPI + if (netif_rx_schedule_prep(pAC->dev[0])) { + pAC->GIni.GIValIrqMask &= ~(Y2_IS_STAT_BMU); + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); + SetIntMask = SK_TRUE; + __netif_rx_schedule(pAC->dev[0]); + } + + if (netif_rx_schedule_prep(pAC->dev[1])) { + if (!SetIntMask) { + pAC->GIni.GIValIrqMask &= ~(Y2_IS_STAT_BMU); + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); + } + __netif_rx_schedule(pAC->dev[1]); + } +#else + handledStatLE = HandleStatusLEs(pAC); +#endif + + /* + ** Check for Special Interrupts + */ + if ((IntSrc & ~Y2_IS_STAT_BMU) || pAC->CheckQueue || pNet->TimerExpired) { + pAC->CheckQueue = SK_FALSE; + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + + SkGeSirqIsr(pAC, pAC->IoBase, IntSrc); + + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + } + + /* Speed enhancement for a2 chipsets */ + if (HW_FEATURE(pAC, HWF_WA_DEV_42)) { + spin_lock_irqsave(&pAC->SetPutIndexLock, Flags); + SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET); + SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), &pAC->RxPort[0].RxLET); + spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags); + } + + /* + ** Reenable interrupts and signal end of ISR + */ + SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2); + + /* + ** Stop and restart TX timer in case a Status LE was handled + */ +#ifndef CONFIG_SK98LIN_NAPI + if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) { + + SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP); + SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START); + } +#endif + + if (!(IS_Q_EMPTY(&(pAC->TxPort[0][TX_PRIO_LOW].TxAQ_waiting)))) { + GiveTxBufferToHw(pAC, pAC->IoBase, 0); + } + if (!(IS_Q_EMPTY(&(pAC->TxPort[1][TX_PRIO_LOW].TxAQ_waiting)))) { + GiveTxBufferToHw(pAC, pAC->IoBase, 1); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("<== SkY2Isr\n")); + + return; +} /* SkY2Isr */ + +/***************************************************************************** + * + * SkY2Xmit - Linux frame transmit function for Yukon2 + * + * Description: + * The system calls this function to send frames onto the wire. + * It puts the frame in the tx descriptor ring. If the ring is + * full then, the 'tbusy' flag is set. + * + * Returns: + * 0, if everything is ok + * !=0, on error + * + * WARNING: + * returning 1 in 'tbusy' case caused system crashes (double + * allocated skb's) !!! + */ +int SkY2Xmit( +struct sk_buff *skb, /* socket buffer to be sent */ +struct SK_NET_DEVICE *dev) /* via which device? */ +{ + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + SK_U8 FragIdx = 0; + SK_PACKET *pSkPacket; +#if 0 /* uboot */ + SK_FRAG *PrevFrag; + SK_FRAG *CurrFrag; +#endif + SK_PKT_QUEUE *pWorkQueue; /* corresponding TX queue */ + SK_PKT_QUEUE *pWaitQueue; + SK_PKT_QUEUE *pFreeQueue; + SK_LE_TABLE *pLETab; /* corresponding LETable */ +#if 0 /* uboot */ + skb_frag_t *sk_frag; +#endif + SK_U64 PhysAddr; + unsigned long Flags; + unsigned int Port; +#if 0 /* uboot */ + int CurrFragCtr; +#endif + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("==> SkY2Xmit\n")); + + /* + ** Get port and return if no free packet is available + */ + Port = (pAC->RlmtNets == 2) ? pNet->PortNr : pAC->ActivePort; + if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free))) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR, + ("Not free packets available for send\n")); + return 1; /* zero bytes sent! */ + } + + /* + ** Put any new packet to be sent in the waiting queue and + ** handle also any possible fragment of that packet. + */ + pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working); + pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting); + pFreeQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free); + pLETab = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET); + +#if 0 /* uboot */ + /* + ** Normal send operations require only one fragment, because + ** only one sk_buff data area is passed. + ** In contradiction to this, scatter-gather (zerocopy) send + ** operations might pass one or more additional fragments + ** where each fragment needs a separate fragment info packet. + */ + if (((skb_shinfo(skb)->nr_frags + 1) * MAX_FRAG_OVERHEAD) > + NUM_FREE_LE_IN_TABLE(pLETab)) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR, + ("Not enough LE available for send\n")); + return 1; /* zero bytes sent! */ + } + + if ((skb_shinfo(skb)->nr_frags + 1) > MAX_NUM_FRAGS) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR, + ("Not even one fragment available for send\n")); + return 1; /* zero bytes sent! */ + } +#endif + + /* + ** Get first packet from free packet queue + */ + POP_FIRST_PKT_FROM_QUEUE(pFreeQueue, pSkPacket); + if(pSkPacket == NULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR, + ("Could not obtain free packet used for xmit\n")); + return 1; /* zero bytes sent! */ + } + + pSkPacket->pFrag = &(pSkPacket->FragArray[FragIdx]); + + /* + ** map the sk_buff to be available for the adapter + */ +#if 0 /* uboot */ + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, + virt_to_page(skb->data), + ((unsigned long) skb->data & ~PAGE_MASK), + skb_headlen(skb), + PCI_DMA_TODEVICE); +#else + PhysAddr = (SK_U64)(SK_U32)skb->data; +#endif + pSkPacket->pMBuf = skb; + pSkPacket->pFrag->pPhys = PhysAddr; + pSkPacket->pFrag->FragLen = skb->len;/*skb_headlen(skb);*/ + pSkPacket->pFrag->pNext = NULL; /* initial has no next default */ + pSkPacket->NumFrags = 2; /*skb_shinfo(skb)->nr_frags + 1;*/ + #if 0 + pSkPacket->NumFrags = skb_shinfo(skb)->nr_frags + 1; + + PrevFrag = pSkPacket->pFrag; + + /* + ** Each scatter-gather fragment need to be mapped... + */ + for ( CurrFragCtr = 0; + CurrFragCtr < skb_shinfo(skb)->nr_frags; + CurrFragCtr++) { + FragIdx++; + sk_frag = &skb_shinfo(skb)->frags[CurrFragCtr]; + CurrFrag = &(pSkPacket->FragArray[FragIdx]); + + /* + ** map the sk_buff to be available for the adapter + */ + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, + sk_frag->page, + sk_frag->page_offset, + sk_frag->size, + PCI_DMA_TODEVICE); + + CurrFrag->pPhys = PhysAddr; + CurrFrag->FragLen = sk_frag->size; + CurrFrag->pNext = NULL; + + /* + ** Add the new fragment to the list of fragments + */ + PrevFrag->pNext = CurrFrag; + PrevFrag = CurrFrag; + } +#endif + /* + ** Add packet to waiting packets queue + */ + PUSH_PKT_AS_LAST_IN_QUEUE(pWaitQueue, pSkPacket); + GiveTxBufferToHw(pAC, pAC->IoBase, Port); +#if 0 /* uboot */ + dev->trans_start = jiffies; +#endif + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("<== SkY2Xmit(return 0)\n")); + return (0); +} /* SkY2Xmit */ + +#ifdef CONFIG_SK98LIN_NAPI +/***************************************************************************** + * + * SkY2Poll - NAPI Rx polling callback for Yukon2 chipsets + * + * Description: + * Called by the Linux system in case NAPI polling is activated + * + * Returns + * The number of work data still to be handled + * + * Notes + * The slowpath lock needs to be set because HW accesses may + * interfere with slowpath events (e.g. TWSI) + */ +int SkY2Poll( +struct net_device *dev, /* device that needs to be polled */ +int *budget) /* how many budget do we have? */ +{ + SK_AC *pAC = ((DEV_NET*)(dev->priv))->pAC; + int WorkToDo = min(*budget, dev->quota); + int WorkDone = 0; + SK_BOOL handledStatLE = SK_FALSE; + unsigned long Flags; + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + handledStatLE = HandleStatusLEs(pAC, &WorkDone, WorkToDo); + + *budget -= WorkDone; + dev->quota -= WorkDone; + + if(WorkDone < WorkToDo) { + netif_rx_complete(dev); + pAC->GIni.GIValIrqMask |= (Y2_IS_STAT_BMU); + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask); + if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) { + SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP); + SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START); + } + } + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + return (WorkDone >= WorkToDo); +} /* SkY2Poll */ +#endif + +/****************************************************************************** + * + * SkY2PortStop - stop a port on Yukon2 + * + * Description: + * This function stops a port of the Yukon2 chip. This stop + * stop needs to be performed in a specific order: + * + * a) Stop the Prefetch unit + * b) Stop the Port (MAC, PHY etc.) + * + * Returns: N/A + */ +void SkY2PortStop( +SK_AC *pAC, /* adapter control context */ +SK_IOC IoC, /* I/O control context (address of adapter registers) */ +int Port, /* port to stop (MAC_1 + n) */ +int Dir, /* StopDirection (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */ +int RstMode) /* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("==> SkY2PortStop (Port %c)\n", 'A' + Port)); + + /* + ** Stop the HW + */ + SkGeStopPort(pAC, IoC, Port, Dir, RstMode); + + /* + ** Move any TX packet from work queues into the free queue again + ** and initialize the TX LETable variables + */ + SkY2FreeTxBuffers(pAC, pAC->IoBase, Port); + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.TcpWp = 0; + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.MssValue = 0; + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.BufHighAddr = 0; + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done = 0; + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put = 0; + // pAC->GIni.GP[Port].PState = SK_PRT_STOP; + + /* + ** Move any RX packet from work queue into the waiting queue + ** and initialize the RX LETable variables + */ + SkY2FreeRxBuffers(pAC, pAC->IoBase, Port); + pAC->RxPort[Port].RxLET.BufHighAddr = 0; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("<== SkY2PortStop()\n")); +} + +/****************************************************************************** + * + * SkY2PortStart - start a port on Yukon2 + * + * Description: + * This function starts a port of the Yukon2 chip. This start + * action needs to be performed in a specific order: + * + * a) Initialize the LET indices (PUT/GET to 0) + * b) Initialize the LET in HW (enables also prefetch unit) + * c) Move all RX buffers from waiting queue to working queue + * which involves also setting up of RX list elements + * d) Initialize the FIFO settings of Yukon2 (Watermark etc.) + * e) Initialize the Port (MAC, PHY etc.) + * f) Initialize the MC addresses + * + * Returns: N/A + */ +void SkY2PortStart( +SK_AC *pAC, /* adapter control context */ +SK_IOC IoC, /* I/O control context (address of adapter registers) */ +int Port) /* port to start */ +{ + // SK_GEPORT *pPrt = &pAC->GIni.GP[Port]; + SK_HWLE *pLE; + SK_U32 DWord; + SK_U32 PrefetchReg; /* register for Put index */ + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("==> SkY2PortStart (Port %c)\n", 'A' + Port)); + + /* + ** Initialize the LET indices + */ + pAC->RxPort[Port].RxLET.Done = 0; + pAC->RxPort[Port].RxLET.Put = 0; + pAC->RxPort[Port].RxLET.HwPut = 0; + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done = 0; + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put = 0; + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.HwPut = 0; + if (HW_SYNC_TX_SUPPORTED(pAC)) { + pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Done = 0; + pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Put = 0; + pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.HwPut = 0; + } + + if (HW_FEATURE(pAC, HWF_WA_DEV_420)) { + /* + ** It might be that we have to limit the RX buffers + ** effectively passed to HW. Initialize the start + ** value in that case... + */ + NbrRxBuffersInHW = 0; + } + + /* + ** TODO on dual net adapters we need to check if + ** StatusLETable need to be set... + ** + ** pAC->StatusLETable.Done = 0; + ** pAC->StatusLETable.Put = 0; + ** pAC->StatusLETable.HwPut = 0; + ** SkGeY2InitPrefetchUnit(pAC, pAC->IoBase, Q_ST, &pAC->StatusLETable); + */ + + /* + ** Initialize the LET in HW (enables also prefetch unit) + */ + SkGeY2InitPrefetchUnit(pAC, IoC,(Port == 0) ? Q_R1 : Q_R2, + &pAC->RxPort[Port].RxLET); + SkGeY2InitPrefetchUnit( pAC, IoC,(Port == 0) ? Q_XA1 : Q_XA2, + &pAC->TxPort[Port][TX_PRIO_LOW].TxALET); + if (HW_SYNC_TX_SUPPORTED(pAC)) { + SkGeY2InitPrefetchUnit( pAC, IoC, (Port == 0) ? Q_XS1 : Q_XS2, + &pAC->TxPort[Port][TX_PRIO_HIGH].TxSLET); + } + + + /* + ** Using new values for the watermarks and the timer for + ** low latency optimization + */ + if (pAC->LowLatency) { + SK_OUT8(IoC, STAT_FIFO_WM, 1); + SK_OUT8(IoC, STAT_FIFO_ISR_WM, 1); + SK_OUT32(IoC, STAT_LEV_TIMER_INI, 50); + SK_OUT32(IoC, STAT_ISR_TIMER_INI, 10); + } + + + /* + ** Initialize the Port (MAC, PHY etc.) + */ + if (SkGeInitPort(pAC, IoC, Port)) { + if (Port == 0) { + printk("%s: SkGeInitPort A failed.\n",pAC->dev[0]->name); + } else { + printk("%s: SkGeInitPort B failed.\n",pAC->dev[1]->name); + } + } + + if (IS_GMAC(pAC)) { + /* disable Rx GMAC FIFO Flush Mode */ + SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8) GMF_RX_F_FL_OFF); + } + + /* + ** Initialize the MC addresses + */ + SkAddrMcUpdate(pAC,IoC, Port); + + SkMacRxTxEnable(pAC, IoC,Port); + + if (pAC->RxPort[Port].UseRxCsum) { + SkGeRxCsum(pAC, IoC, Port, SK_TRUE); + + GET_RX_LE(pLE, &pAC->RxPort[Port].RxLET); + RXLE_SET_STACS1(pLE, pAC->CsOfs1); + RXLE_SET_STACS2(pLE, pAC->CsOfs2); + RXLE_SET_CTRL(pLE, 0); + + RXLE_SET_OPC(pLE, OP_TCPSTART | HW_OWNER); + FLUSH_OPC(pLE); + if (Port == 0) { + PrefetchReg=Y2_PREF_Q_ADDR(Q_R1,PREF_UNIT_PUT_IDX_REG); + } else { + PrefetchReg=Y2_PREF_Q_ADDR(Q_R2,PREF_UNIT_PUT_IDX_REG); + } + DWord = GET_PUT_IDX(&pAC->RxPort[Port].RxLET); + SK_OUT32(IoC, PrefetchReg, DWord); + UPDATE_HWPUT_IDX(&pAC->RxPort[Port].RxLET); + } + + pAC->GIni.GP[Port].PState = SK_PRT_RUN; + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("<== SkY2PortStart()\n")); +} + +/****************************************************************************** + * + * Local Functions + * + *****************************************************************************/ + +/***************************************************************************** + * + * InitPacketQueues - initialize SW settings of packet queues + * + * Description: + * This function will initialize the packet queues for a port. + * + * Returns: N/A + */ +static void InitPacketQueues( +SK_AC *pAC, /* pointer to adapter control context */ +int Port) /* index of port to be initialized */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("==> InitPacketQueues(Port %c)\n", 'A' + Port)); + + pAC->RxPort[Port].RxQ_working.pHead = NULL; + pAC->RxPort[Port].RxQ_working.pTail = NULL; + spin_lock_init(&pAC->RxPort[Port].RxQ_working.QueueLock); + + pAC->RxPort[Port].RxQ_waiting.pHead = NULL; + pAC->RxPort[Port].RxQ_waiting.pTail = NULL; + spin_lock_init(&pAC->RxPort[Port].RxQ_waiting.QueueLock); + + pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pHead = NULL; + pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pTail = NULL; + spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.QueueLock); + + pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pHead = NULL; + pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pTail = NULL; + spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.QueueLock); + + pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pHead = NULL; + pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pTail = NULL; + spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.QueueLock); + +#if USE_SYNC_TX_QUEUE + pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pHead = NULL; + pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pTail = NULL; + spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.QueueLock); + + pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pHead = NULL; + pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pTail = NULL; + spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.QueueLock); +#endif + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("<== InitPacketQueues(Port %c)\n", 'A' + Port)); +} /* InitPacketQueues */ + +/***************************************************************************** + * + * GiveTxBufferToHw - commits a previously allocated DMA area to HW + * + * Description: + * This functions gives transmit buffers to HW. If no list elements + * are available the buffers will be queued. + * + * Notes: + * This function can run only once in a system at one time. + * + * Returns: N/A + */ +static void GiveTxBufferToHw( +SK_AC *pAC, /* pointer to adapter control context */ +SK_IOC IoC, /* I/O control context (address of registers) */ +int Port) /* port index for which the buffer is used */ +{ + SK_HWLE *pLE; + SK_PACKET *pSkPacket; + SK_FRAG *pFrag; + SK_PKT_QUEUE *pWorkQueue; /* corresponding TX queue */ + SK_PKT_QUEUE *pWaitQueue; + SK_LE_TABLE *pLETab; /* corresponding LETable */ + SK_BOOL SetOpcodePacketFlag; + SK_U32 HighAddress; + SK_U32 LowAddress; +#if 0 //uboot + SK_U16 TcpSumStart; + SK_U16 TcpSumWrite; +#endif + SK_U8 OpCode; + SK_U8 Ctrl; + unsigned long Flags; + unsigned long LockFlag; +#if 0 //uboot + int Protocol; +#endif +#ifdef NETIF_F_TSO + SK_U16 Mss; + int TcpOptLen; + int IpTcpLen; +#endif + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("==> GiveTxBufferToHw\n")); + + if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) { + return; + } + + spin_lock_irqsave(&pAC->TxQueueLock, LockFlag); + + /* + ** Initialize queue settings + */ + pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working); + pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting); + pLETab = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET); + + POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket); + while (pSkPacket != NULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("\tWe have a packet to send %p\n", pSkPacket)); + + /* + ** the first frag of a packet gets opcode OP_PACKET + */ + SetOpcodePacketFlag = SK_TRUE; + pFrag = pSkPacket->pFrag; + + /* + ** fill list elements with data from fragments + */ + while (pFrag != NULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("\tGet LE\n")); +#ifdef NETIF_F_TSO + Mss = skb_shinfo(pSkPacket->pMBuf)->tso_size; + if (Mss) { + TcpOptLen = ((pSkPacket->pMBuf->h.th->doff - 5) * 4); + IpTcpLen = ((pSkPacket->pMBuf->nh.iph->ihl * 4) + + sizeof(struct tcphdr)); + Mss += (TcpOptLen + IpTcpLen + C_LEN_ETHERMAC_HEADER); + } + if (pLETab->Bmu.RxTx.MssValue != Mss) { + pLETab->Bmu.RxTx.MssValue = Mss; + /* Take a new LE for TSO from the table */ + GET_TX_LE(pLE, pLETab); + +#if 0 + if(pSkPacket->VlanId) { + TXLE_SET_OPC(pLE, OP_LRGLENVLAN | HW_OWNER); + TXLE_SET_VLAN(pLE, pSkPacket->VlanId); + pSkPacket->VlanId = 0; + Ctrl |= INS_VLAN; + } else { +#endif + TXLE_SET_OPC(pLE, OP_LRGLEN | HW_OWNER); +#if 0 + } +#endif + /* set maximum segment size for new packet */ + TXLE_SET_LSLEN(pLE, pLETab->Bmu.RxTx.MssValue); + FLUSH_OPC(pLE) ; + } +#endif + GET_TX_LE(pLE, pLETab); + Ctrl = 0; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("\tGot empty LE %p idx %d\n", pLE, GET_PUT_IDX(pLETab))); + + SK_DBG_DUMP_TX_LE(pLE); + + LowAddress = (SK_U32) (pFrag->pPhys & 0xffffffff); + HighAddress = (SK_U32) (pFrag->pPhys >> 32); + + if (HighAddress != pLETab->BufHighAddr) { + /* set opcode high part of the address in one LE */ + OpCode = OP_ADDR64 | HW_OWNER; + + /* Set now the 32 high bits of the address */ + TXLE_SET_ADDR( pLE, HighAddress); + + /* Set the opcode into the LE */ + TXLE_SET_OPC(pLE, OpCode); + + /* Flush the LE to memory */ + FLUSH_OPC(pLE); + + /* remember the HighAddress we gave to the Hardware */ + pLETab->BufHighAddr = HighAddress; + + /* get a new LE because we filled one with high address */ + GET_TX_LE(pLE, pLETab); + } + + +#if 0 /* uboot */ + /* + ** TCP checksum offload + */ + if ((pSkPacket->pMBuf->ip_summed == CHECKSUM_HW) && + (SetOpcodePacketFlag == SK_TRUE)) { + Protocol = ((SK_U8)pSkPacket->pMBuf->data[C_OFFSET_IPPROTO] & 0xff); + /* if (Protocol & C_PROTO_ID_IP) { Ctrl = 0; } */ + if (Protocol & C_PROTO_ID_TCP) { + Ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; + /* TCP Checksum Calculation Start Position */ + TcpSumStart = C_LEN_ETHERMAC_HEADER + IP_HDR_LEN; + /* TCP Checksum Write Position */ + TcpSumWrite = TcpSumStart + TCP_CSUM_OFFS; + } else { + Ctrl = UDPTCP | CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; + /* TCP Checksum Calculation Start Position */ + TcpSumStart = ETHER_MAC_HDR_LEN + IP_HDR_LEN; + /* UDP Checksum Write Position */ + TcpSumWrite = TcpSumStart + UDP_CSUM_OFFS; + } + + if ((Ctrl) && (pLETab->Bmu.RxTx.TcpWp != TcpSumWrite)) { + /* Update the last value of the write position */ + pLETab->Bmu.RxTx.TcpWp = TcpSumWrite; + + /* Set the Lock field for this LE: */ + /* Checksum calculation for one packet only */ + TXLE_SET_LCKCS(pLE, 1); + + /* Set the start position for checksum. */ + TXLE_SET_STACS(pLE, TcpSumStart); + + /* Set the position where the checksum will be writen */ + TXLE_SET_WRICS(pLE, TcpSumWrite); + + /* Set the initial value for checksum */ + /* PseudoHeader CS passed from Linux -> 0! */ + TXLE_SET_INICS(pLE, 0); + + /* Set the opcode for tcp checksum */ + TXLE_SET_OPC(pLE, OP_TCPLISW | HW_OWNER); + + /* Flush the LE to memory */ + FLUSH_OPC(pLE); + + /* get a new LE because we filled one with data for checksum */ + GET_TX_LE(pLE, pLETab); + } + } /* end TCP offload handling */ + +#endif + + TXLE_SET_ADDR(pLE, LowAddress); + TXLE_SET_LEN(pLE, pFrag->FragLen); + + if (SetOpcodePacketFlag){ +#ifdef NETIF_F_TSO + if (Mss) { + OpCode = OP_LARGESEND | HW_OWNER; + } else { +#endif + OpCode = OP_PACKET| HW_OWNER; +#ifdef NETIF_F_TSO + } +#endif + SetOpcodePacketFlag = SK_FALSE; + } else { + /* Follow packet in a sequence has always OP_BUFFER */ + OpCode = OP_BUFFER | HW_OWNER; + } + + /* Check if the low address is near the upper limit. */ + CHECK_LOW_ADDRESS(pLETab->BufHighAddr, LowAddress, pFrag->FragLen); + + pFrag = pFrag->pNext; + if (pFrag == NULL) { + /* mark last fragment */ + Ctrl |= EOP; + } + TXLE_SET_CTRL(pLE, Ctrl); + TXLE_SET_OPC(pLE, OpCode); + FLUSH_OPC(pLE); + + SK_DBG_DUMP_TX_LE(pLE); + } + + /* + ** Remember next LE for tx complete + */ + pSkPacket->NextLE = GET_PUT_IDX(pLETab); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("\tNext LE for pkt %p is %d\n", pSkPacket, pSkPacket->NextLE)); + + /* + ** Add packet to working packets queue + */ + PUSH_PKT_AS_LAST_IN_QUEUE(pWorkQueue, pSkPacket); + + /* + ** give transmit start command + */ + if (HW_FEATURE(pAC, HWF_WA_DEV_42)) { + spin_lock(&pAC->SetPutIndexLock); + SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET); + spin_unlock(&pAC->SetPutIndexLock); + } else { + /* write put index */ + if (Port == 0) { + SK_OUT32(pAC->IoBase, + Y2_PREF_Q_ADDR(Q_XA1,PREF_UNIT_PUT_IDX_REG), + GET_PUT_IDX(&pAC->TxPort[0][0].TxALET)); + UPDATE_HWPUT_IDX(&pAC->TxPort[0][0].TxALET); + } else { + SK_OUT32(pAC->IoBase, + Y2_PREF_Q_ADDR(Q_XA2, PREF_UNIT_PUT_IDX_REG), + GET_PUT_IDX(&pAC->TxPort[1][0].TxALET)); + UPDATE_HWPUT_IDX(&pAC->TxPort[1][0].TxALET); + } + } + + if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) { + break; /* get out of while */ + } + POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket); + } /* while (pSkPacket != NULL) */ + + spin_unlock_irqrestore(&pAC->TxQueueLock, LockFlag); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("<== GiveTxBufferToHw\n")); + return; +} /* GiveTxBufferToHw */ + +/*********************************************************************** + * + * GiveRxBufferToHw - commits a previously allocated DMA area to HW + * + * Description: + * This functions gives receive buffers to HW. If no list elements + * are available the buffers will be queued. + * + * Notes: + * This function can run only once in a system at one time. + * + * Returns: N/A + */ +static void GiveRxBufferToHw( +SK_AC *pAC, /* pointer to adapter control context */ +SK_IOC IoC, /* I/O control context (address of registers) */ +int Port, /* port index for which the buffer is used */ +SK_PACKET *pPacket) /* receive buffer(s) */ +{ + SK_HWLE *pLE; + SK_LE_TABLE *pLETab; + SK_BOOL Done = SK_FALSE; /* at least on LE changed? */ + SK_U32 LowAddress; + SK_U32 HighAddress; + SK_U32 PrefetchReg; /* register for Put index */ + unsigned NumFree; + unsigned Required; + unsigned long Flags; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("==> GiveRxBufferToHw(Port %c, Packet %p)\n", 'A' + Port, pPacket)); + + pLETab = &pAC->RxPort[Port].RxLET; + + if (Port == 0) { + PrefetchReg = Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG); + } else { + PrefetchReg = Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG); + } + + if (pPacket != NULL) { + /* + ** For the time being, we have only one packet passed + ** to this function which might be changed in future! + */ + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket); + } + + /* + ** now pPacket contains the very first waiting packet + */ + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket); + while (pPacket != NULL) { + if (HW_FEATURE(pAC, HWF_WA_DEV_420)) { + if (NbrRxBuffersInHW >= MAX_NBR_RX_BUFFERS_IN_HW) { + PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("<== GiveRxBufferToHw()\n")); + return; + } + NbrRxBuffersInHW++; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("Try to add packet %p\n", pPacket)); + + /* + ** Check whether we have enough listelements: + ** + ** we have to take into account that each fragment + ** may need an additional list element for the high + ** part of the address here I simplified it by + ** using MAX_FRAG_OVERHEAD maybe it's worth to split + ** this constant for Rx and Tx or to calculate the + ** real number of needed LE's + */ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("\tNum %d Put %d Done %d Free %d %d\n", + pLETab->Num, pLETab->Put, pLETab->Done, + NUM_FREE_LE_IN_TABLE(pLETab), + (NUM_FREE_LE_IN_TABLE(pLETab)))); + + Required = pPacket->NumFrags + MAX_FRAG_OVERHEAD; + NumFree = NUM_FREE_LE_IN_TABLE(pLETab); + if (NumFree) { + NumFree--; + } + + if (Required > NumFree ) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR, + ("\tOut of LEs have %d need %d\n", + NumFree, Required)); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("\tWaitQueue starts with packet %p\n", pPacket)); + PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket); + if (Done) { + /* + ** write Put index to BMU or Polling Unit and make the LE's + ** available for the hardware + */ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("\tWrite new Put Idx\n")); + + SK_OUT32(IoC, PrefetchReg, GET_PUT_IDX(pLETab)); + UPDATE_HWPUT_IDX(pLETab); + } + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("<== GiveRxBufferToHw()\n")); + return; + } else { + if (!AllocAndMapRxBuffer(pAC, pPacket, Port)) { + /* + ** Failure while allocating sk_buff might + ** be due to temporary short of resources + ** Maybe next time buffers are available. + ** Until this, the packet remains in the + ** RX waiting queue... + */ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR, + ("Failed to allocate Rx buffer\n")); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("WaitQueue starts with packet %p\n", pPacket)); + PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket); + if (Done) { + /* + ** write Put index to BMU or Polling + ** Unit and make the LE's + ** available for the hardware + */ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("\tWrite new Put Idx\n")); + + SK_OUT32(IoC, PrefetchReg, GET_PUT_IDX(pLETab)); + UPDATE_HWPUT_IDX(pLETab); + } + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("<== GiveRxBufferToHw()\n")); + return; + } + } + Done = SK_TRUE; + + LowAddress = (SK_U32) (pPacket->pFrag->pPhys & 0xffffffff); + HighAddress = (SK_U32) (pPacket->pFrag->pPhys >> 32); + if (HighAddress != pLETab->BufHighAddr) { + /* get a new LE for high address */ + GET_RX_LE(pLE, pLETab); + + /* Set now the 32 high bits of the address */ + RXLE_SET_ADDR(pLE, HighAddress); + + /* Set the control bits of the address */ + RXLE_SET_CTRL(pLE, 0); + + /* Set the opcode into the LE */ + RXLE_SET_OPC(pLE, (OP_ADDR64 | HW_OWNER)); + + /* Flush the LE to memory */ + FLUSH_OPC(pLE); + + /* remember the HighAddress we gave to the Hardware */ + pLETab->BufHighAddr = HighAddress; + } + + /* + ** Fill data into listelement + */ + GET_RX_LE(pLE, pLETab); + RXLE_SET_ADDR(pLE, LowAddress); + RXLE_SET_LEN(pLE, pPacket->pFrag->FragLen); + RXLE_SET_CTRL(pLE, 0); + RXLE_SET_OPC(pLE, (OP_PACKET | HW_OWNER)); + FLUSH_OPC(pLE); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("=== LE filled\n")); + + SK_DBG_DUMP_RX_LE(pLE); + + /* + ** Remember next LE for rx complete + */ + pPacket->NextLE = GET_PUT_IDX(pLETab); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("\tPackets Next LE is %d\n", pPacket->NextLE)); + + /* + ** Add packet to working receive buffer queue and get + ** any next packet out of the waiting queue + */ + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_working, pPacket); + if (IS_Q_EMPTY(&(pAC->RxPort[Port].RxQ_waiting))) { + break; /* get out of while processing */ + } + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("\tWaitQueue is empty\n")); + + if (Done) { + /* + ** write Put index to BMU or Polling Unit and make the LE's + ** available for the hardware + */ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("\tWrite new Put Idx\n")); + + /* Speed enhancement for a2 chipsets */ + if (HW_FEATURE(pAC, HWF_WA_DEV_42)) { + spin_lock_irqsave(&pAC->SetPutIndexLock, Flags); + SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), pLETab); + spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags); + } else { + /* write put index */ + if (Port == 0) { + SK_OUT32(IoC, + Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG), + GET_PUT_IDX(pLETab)); + } else { + SK_OUT32(IoC, + Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG), + GET_PUT_IDX(pLETab)); + } + + /* Update put index */ + UPDATE_HWPUT_IDX(pLETab); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("<== GiveRxBufferToHw()\n")); +} /* GiveRxBufferToHw */ + +/*********************************************************************** + * + * FillReceiveTableYukon2 - map any waiting RX buffers to HW + * + * Description: + * If the list element table contains more empty elements than + * specified this function tries to refill them. + * + * Notes: + * This function can run only once per port in a system at one time. + * + * Returns: N/A + */ +void FillReceiveTableYukon2( +SK_AC *pAC, /* pointer to adapter control context */ +SK_IOC IoC, /* I/O control context */ +int Port) /* port index of RX */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("==> FillReceiveTableYukon2 (Port %c)\n", 'A' + Port)); + + if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) > + pAC->MaxUnusedRxLeWorking) { + + /* + ** Give alle waiting receive buffers down + ** The queue holds all RX packets that + ** need a fresh allocation of the sk_buff. + */ + if (pAC->RxPort[Port].RxQ_waiting.pHead != NULL) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("Waiting queue is not empty -> give it to HW")); + GiveRxBufferToHw(pAC, IoC, Port, NULL); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("<== FillReceiveTableYukon2 ()\n")); +} /* FillReceiveTableYukon2 */ + +/****************************************************************************** + * + * + * HandleReceives - will pass any ready RX packet to kernel + * + * Description: + * This functions handles a received packet. It checks wether it is + * valid, updates the receive list element table and gives the receive + * buffer to Linux + * + * Notes: + * This function can run only once per port at one time in the system. + * + * Returns: N/A + */ +static SK_BOOL HandleReceives( +SK_AC *pAC, /* adapter control context */ +int Port, /* port on which a packet has been received */ +SK_U16 Len, /* number of bytes which was actually received */ +SK_U32 FrameStatus, /* MAC frame status word */ +SK_U16 Tcp1, /* first hw checksum */ +SK_U16 Tcp2, /* second hw checksum */ +SK_U32 Tist, /* timestamp */ +SK_U16 Vlan) /* Vlan Id */ +{ + + SK_PACKET *pSkPacket; + SK_LE_TABLE *pLETab; + SK_MBUF *pRlmtMbuf; /* buffer for giving RLMT frame */ + struct sk_buff *pMsg; /* ptr to message holding frame */ +#ifdef __ia64__ + struct sk_buff *pNewMsg; /* used when IP aligning */ +#endif + +#ifdef CONFIG_SK98LIN_NAPI + SK_BOOL SlowPathLock = SK_FALSE; +#else + SK_BOOL SlowPathLock = SK_TRUE; +#endif + SK_BOOL IsGoodPkt; + SK_BOOL IsBc; + SK_BOOL IsMc; + SK_EVPARA EvPara; /* an event parameter union */ + SK_I16 LenToFree; /* must be signed integer */ + + unsigned long Flags; /* for spin lock */ + unsigned int RlmtNotifier; +#if 0 /* uboot */ + unsigned short Type; + int IpFrameLength; +#endif + int FrameLength; /* total length of recvd frame */ + int NumBytes; +#if 0 + int Result; +#endif + int Offset = 0; + +#ifdef Y2_SYNC_CHECK +#if 0 + SK_U16 MyTcp; +#endif +#endif + + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("==> HandleReceives (Port %c)\n", 'A' + Port)); + + /* + ** initialize vars for selected port + */ + pLETab = &pAC->RxPort[Port].RxLET; + + /* + ** check whether we want to receive this packet + */ + SK_Y2_RXSTAT_CHECK_PKT(Len, FrameStatus, IsGoodPkt); + + /* + ** Remember length to free (in case of RxBuffer overruns; + ** unlikely, but might happen once in a while) + */ + LenToFree = (SK_I16) Len; + + /* + ** maybe we put these two checks into the SK_RXDESC_CHECK_PKT macro too + */ + if (Len > pAC->RxPort[Port].RxBufSize) { + IsGoodPkt = SK_FALSE; + } + + /* + ** take first receive buffer out of working queue + */ + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket); + if (pSkPacket == NULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_ERROR, + ("Packet not available. NULL pointer.\n")); + return(SK_TRUE); + } + + if (HW_FEATURE(pAC, HWF_WA_DEV_420)) { + NbrRxBuffersInHW--; + } + + /* + ** Verify the received length of the frame! Note that having + ** multiple RxBuffers being aware of one single receive packet + ** (one packet spread over multiple RxBuffers) is not supported + ** by this driver! + */ + if ((Len > pAC->RxPort[Port].RxBufSize) || + (Len > (SK_U16) pSkPacket->PacketLen)) { + IsGoodPkt = SK_FALSE; + } + + /* + ** Reset own bit in LE's between old and new Done index + ** This is not really necessary but makes debugging easier + */ + CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE); + + /* + ** Free the list elements for new Rx buffers + */ + SET_DONE_INDEX(pLETab, pSkPacket->NextLE); + pMsg = pSkPacket->pMBuf; + FrameLength = Len; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("Received frame of length %d on port %d\n",FrameLength, Port)); + + if (!IsGoodPkt) { + printf("\npacket is not good\n"); + /* + ** release the DMA mapping + */ + pci_dma_sync_single(pAC->PciDev, + (dma_addr_t) pSkPacket->pFrag->pPhys, + pSkPacket->pFrag->FragLen, + PCI_DMA_FROMDEVICE); + + DEV_KFREE_SKB_ANY(pSkPacket->pMBuf); + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("<== HandleReceives (Port %c)\n", 'A' + Port)); + + /* + ** Sanity check for RxBuffer overruns... + */ + LenToFree = LenToFree - (pSkPacket->pFrag->FragLen); + while (LenToFree > 0) { + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket); + if (HW_FEATURE(pAC, HWF_WA_DEV_420)) { + NbrRxBuffersInHW--; + } + CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE); + SET_DONE_INDEX(pLETab, pSkPacket->NextLE); + pci_dma_sync_single(pAC->PciDev, + (dma_addr_t) pSkPacket->pFrag->pPhys, + pSkPacket->pFrag->FragLen, + PCI_DMA_FROMDEVICE); + + DEV_KFREE_SKB_ANY(pSkPacket->pMBuf); + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket); + LenToFree = LenToFree - ((SK_I16)(pSkPacket->pFrag->FragLen)); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR, + ("<==HandleReceives (Port %c) drop faulty len pkt(2)\n",'A'+Port)); + } + return(SK_TRUE); + } else { + /* + ** Release the DMA mapping + */ + pci_unmap_single(pAC->PciDev, + pSkPacket->pFrag->pPhys, + pAC->RxPort[Port].RxBufSize, + PCI_DMA_FROMDEVICE); +#if 0 /* uboot */ + skb_put(pMsg, FrameLength); /* set message len */ + pMsg->ip_summed = CHECKSUM_NONE; /* initial default */ +#ifdef Y2_SYNC_CHECK + pAC->FramesWithoutSyncCheck++; + if (pAC->FramesWithoutSyncCheck > Y2_RESYNC_WATERMARK) { + if ((Tcp1 != 1) || (Tcp2 != 0)) { + pAC->FramesWithoutSyncCheck = 0; + MyTcp = (SK_U16) SkCsCalculateChecksum( + &pMsg->data[14], + FrameLength - 14); + if (MyTcp != Tcp1) { + /* Queue port reset event */ + SkLocalEventQueue(pAC, SKGE_DRV, + SK_DRV_RECOVER,Port,-1,SK_FALSE); + } + } + } +#endif +#endif + + + +#if 0 /* uboot */ + pMsg->ip_summed = CHECKSUM_NONE; /* initial default */ + if (pAC->RxPort[Port].UseRxCsum) { + Type = ntohs(*((short*)&pMsg->data[12])); + if (Type == 0x800) { + *((char *)&(IpFrameLength)) = pMsg->data[16]; + *(((char *)&(IpFrameLength))+1) = pMsg->data[17]; + IpFrameLength = ntohs(IpFrameLength); + HeaderLength = FrameLength - IpFrameLength; + if (HeaderLength == 0xe) { + Result = + SkCsGetReceiveInfo(pAC,&pMsg->data[14],Tcp1,Tcp2, Port); + if ((Result == SKCS_STATUS_IP_FRAGMENT) || + (Result == SKCS_STATUS_IP_CSUM_OK) || + (Result == SKCS_STATUS_TCP_CSUM_OK) || + (Result == SKCS_STATUS_UDP_CSUM_OK)) { + pMsg->ip_summed = CHECKSUM_UNNECESSARY; + } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR) || + (Result == SKCS_STATUS_UDP_CSUM_ERROR) || + (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) || + (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) || + (Result == SKCS_STATUS_IP_CSUM_ERROR)) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR, + ("skge: CRC error. Frame dropped!\n")); + DEV_KFREE_SKB_ANY(pMsg); + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket); + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_RX_PROGRESS, + ("<==HandleReceives(Port %c)\n",'A'+Port)); + return(SK_TRUE); + } else { + pMsg->ip_summed = CHECKSUM_NONE; + } + } /* end if (HeaderLength == valid) */ + } /* end if (Type == 0x800) -> IP frame */ + } /* end if (pRxPort->UseRxCsum) */ + +#endif + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS,("V")); + RlmtNotifier = SK_RLMT_RX_PROTOCOL; + + IsBc = (FrameStatus & GMR_FS_BC) ? SK_TRUE : SK_FALSE; + SK_RLMT_PRE_LOOKAHEAD(pAC,Port,FrameLength, + IsBc,&Offset,&NumBytes); + if (NumBytes != 0) { + IsMc = (FrameStatus & GMR_FS_MC) ? SK_TRUE : SK_FALSE; + SK_RLMT_LOOKAHEAD(pAC,Port,&pMsg->data[Offset], + IsBc,IsMc,&RlmtNotifier); + } + + if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) { + SK_DBG_MSG(NULL,SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS,("W")); + if ((Port == pAC->ActivePort)||(pAC->RlmtNets == 2)) { + /* send up only frames from active port */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS,("U")); +#ifdef xDEBUG + DumpMsg(pMsg, "Rx"); +#endif + SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC, + FrameLength, Port); + +#ifdef __ia64__ + pNewMsg = alloc_skb(pMsg->len, GFP_ATOMIC); + skb_reserve(pNewMsg, 2); /* to align IP */ + SK_MEMCPY(pNewMsg->data,pMsg->data,pMsg->len); + pNewMsg->ip_summed = pMsg->ip_summed; + skb_put(pNewMsg, pMsg->len); + DEV_KFREE_SKB_ANY(pMsg); + pMsg = pNewMsg; +#endif +#if 0 /* uboot */ + pMsg->dev = pAC->dev[Port]; + pMsg->protocol = eth_type_trans(pMsg, + pAC->dev[Port]); + netif_rx(pMsg); + pAC->dev[Port]->last_rx = jiffies; +#else /* Marvell - uboot */ + + NetReceive(pMsg->data, FrameLength); + DEV_KFREE_SKB_ANY(pMsg); + +#endif + + + } else { /* drop frame */ + SK_DBG_MSG(NULL,SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS,("D")); + DEV_KFREE_SKB_ANY(pMsg); + } + } else { /* This is an RLMT-packet! */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS,("R")); + pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC, + pAC->IoBase, FrameLength); + if (pRlmtMbuf != NULL) { + pRlmtMbuf->pNext = NULL; + pRlmtMbuf->Length = FrameLength; + pRlmtMbuf->PortIdx = Port; + EvPara.pParaPtr = pRlmtMbuf; + SK_MEMCPY((char*)(pRlmtMbuf->pData), + (char*)(pMsg->data),FrameLength); + + if (SlowPathLock == SK_TRUE) { + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + SkEventQueue(pAC, SKGE_RLMT, + SK_RLMT_PACKET_RECEIVED, + EvPara); + pAC->CheckQueue = SK_TRUE; + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + } else { + SkEventQueue(pAC, SKGE_RLMT, + SK_RLMT_PACKET_RECEIVED, + EvPara); + pAC->CheckQueue = SK_TRUE; + } + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS,("Q")); + } +#if 0 /* uboot */ + if (pAC->dev[Port]->flags & (IFF_PROMISC | IFF_ALLMULTI)) { +#ifdef __ia64__ + pNewMsg = alloc_skb(pMsg->len, GFP_ATOMIC); + skb_reserve(pNewMsg, 2); /* to align IP */ + SK_MEMCPY(pNewMsg->data,pMsg->data,pMsg->len); + pNewMsg->ip_summed = pMsg->ip_summed; + pNewMsg->len = pMsg->len; + DEV_KFREE_SKB_ANY(pMsg); + pMsg = pNewMsg; +#endif + pMsg->dev = pAC->dev[Port]; + pMsg->protocol = eth_type_trans(pMsg,pAC->dev[Port]); + netif_rx(pMsg); + pAC->dev[Port]->last_rx = jiffies; + } else +#else /* Marvell - uboot*/ + if (1) { + NetReceive(pMsg->data, FrameLength); + DEV_KFREE_SKB_ANY(pMsg); + + } else +#endif + { + + DEV_KFREE_SKB_ANY(pMsg); + } + } /* if packet for rlmt */ + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket); + } /* end if-else (IsGoodPkt) */ + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("<== HandleReceives (Port %c)\n", 'A' + Port)); + return(SK_TRUE); + +} /* HandleReceives */ + +/*********************************************************************** + * + * CheckForSendComplete - Frees any freeable Tx bufffer + * + * Description: + * This function checks the queues of a port for completed send + * packets and returns these packets back to the OS. + * + * Notes: + * This function can run simultaneously for both ports if + * the OS function OSReturnPacket() can handle this, + * + * Such a send complete does not mean, that the packet is really + * out on the wire. We just know that the adapter has copied it + * into its internal memory and the buffer in the systems memory + * is no longer needed. + * + * Returns: N/A + */ +static void CheckForSendComplete( +SK_AC *pAC, /* pointer to adapter control context */ +SK_IOC IoC, /* I/O control context */ +int Port, /* port index */ +SK_PKT_QUEUE *pPQ, /* tx working packet queue to check */ +SK_LE_TABLE *pLETab, /* corresponding list element table */ +unsigned int Done) /* done index reported for this LET */ +{ + SK_PACKET *pSkPacket; + SK_PKT_QUEUE SendCmplPktQ = { NULL, NULL /* , SPIN_LOCK_UNLOCKED uboot */}; + SK_BOOL DoWakeQueue = SK_FALSE; + unsigned long Flags; + unsigned Put; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("==> CheckForSendComplete(Port %c)\n", 'A' + Port)); + + /* + ** Reset own bit in LE's between old and new Done index + ** This is not really necessairy but makes debugging easier + */ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("Clear Own Bits in TxTable from %d to %d\n", + pLETab->Done, (Done == 0) ? + NUM_LE_IN_TABLE(pLETab) : + (Done - 1))); + + spin_lock_irqsave(&(pPQ->QueueLock), Flags); + + CLEAR_LE_OWN_FROM_DONE_TO(pLETab, Done); + + Put = GET_PUT_IDX(pLETab); + + /* + ** Check whether some packets have been completed + */ + PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket); + while (pSkPacket != NULL) { + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("Check Completion of Tx packet %p\n", pSkPacket)); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("Put %d NewDone %d NextLe of Packet %d\n", Put, Done, + pSkPacket->NextLE)); + + if ((Put > Done) && + ((pSkPacket->NextLE > Put) || (pSkPacket->NextLE <= Done))) { + PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("Packet finished (a)\n")); + } else if ((Done > Put) && + (pSkPacket->NextLE > Put) && (pSkPacket->NextLE <= Done)) { + PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("Packet finished (b)\n")); + } else if ((Done == TXA_MAX_LE-1) && (Put == 0) && (pSkPacket->NextLE == 0)) { + PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("Packet finished (b)\n")); + DoWakeQueue = SK_TRUE; + } else if (Done == Put) { + /* all packets have been sent */ + PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("Packet finished (c)\n")); + } else { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("Packet not yet finished\n")); + PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pPQ, pSkPacket); + break; + } + PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket); + } + spin_unlock_irqrestore(&(pPQ->QueueLock), Flags); + + /* + ** Set new done index in list element table + */ + SET_DONE_INDEX(pLETab, Done); + + /* + ** All TX packets that are send complete should be added to + ** the free queue again for new sents to come + */ + pSkPacket = SendCmplPktQ.pHead; + while (pSkPacket != NULL) { + while (pSkPacket->pFrag != NULL) { + pci_unmap_page(pAC->PciDev, + (dma_addr_t) pSkPacket->pFrag->pPhys, + pSkPacket->pFrag->FragLen, + PCI_DMA_FROMDEVICE); + pSkPacket->pFrag = pSkPacket->pFrag->pNext; + } + + DEV_KFREE_SKB_ANY(pSkPacket->pMBuf); + pSkPacket->pMBuf = NULL; + pSkPacket = pSkPacket->pNext; /* get next packet */ + } + + /* + ** Append the available TX packets back to free queue + */ + if (SendCmplPktQ.pHead != NULL) { + spin_lock_irqsave(&(pAC->TxPort[Port][0].TxQ_free.QueueLock), Flags); + if (pAC->TxPort[Port][0].TxQ_free.pTail != NULL) { + pAC->TxPort[Port][0].TxQ_free.pTail->pNext = SendCmplPktQ.pHead; + pAC->TxPort[Port][0].TxQ_free.pTail = SendCmplPktQ.pTail; + if (pAC->TxPort[Port][0].TxQ_free.pHead->pNext == NULL) { + netif_wake_queue(pAC->dev[Port]); + } + } else { + pAC->TxPort[Port][0].TxQ_free.pHead = SendCmplPktQ.pHead; + pAC->TxPort[Port][0].TxQ_free.pTail = SendCmplPktQ.pTail; + netif_wake_queue(pAC->dev[Port]); + } + if (Done == Put) { + netif_wake_queue(pAC->dev[Port]); + } + if (DoWakeQueue) { + netif_wake_queue(pAC->dev[Port]); + DoWakeQueue = SK_FALSE; + } + spin_unlock_irqrestore(&pAC->TxPort[Port][0].TxQ_free.QueueLock, Flags); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("<== CheckForSendComplete()\n")); + + return; +} /* CheckForSendComplete */ + +/***************************************************************************** + * + * UnmapAndFreeTxPktBuffer + * + * Description: + * This function free any allocated space of receive buffers + * + * Arguments: + * pAC - A pointer to the adapter context struct. + * + */ +static void UnmapAndFreeTxPktBuffer( +SK_AC *pAC, /* pointer to adapter context */ +SK_PACKET *pSkPacket, /* pointer to port struct of ring to fill */ +int TxPort) /* TX port index */ +{ + SK_FRAG *pFrag = pSkPacket->pFrag; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("--> UnmapAndFreeTxPktBuffer\n")); + + while (pFrag != NULL) { + pci_unmap_page(pAC->PciDev, + (dma_addr_t) pFrag->pPhys, + pFrag->FragLen, + PCI_DMA_FROMDEVICE); + pFrag = pFrag->pNext; + } + + DEV_KFREE_SKB_ANY(pSkPacket->pMBuf); + pSkPacket->pMBuf = NULL; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("<-- UnmapAndFreeTxPktBuffer\n")); +} + +/***************************************************************************** + * + * HandleStatusLEs + * + * Description: + * This function checks for any new status LEs that may have been + * received. Those status LEs may either be Rx or Tx ones. + * + * Returns: N/A + */ +static SK_BOOL HandleStatusLEs( +#ifdef CONFIG_SK98LIN_NAPI +SK_AC *pAC, /* pointer to adapter context */ +int *WorkDone, /* Done counter needed for NAPI */ +int WorkToDo) /* ToDo counter for NAPI */ +#else +SK_AC *pAC) /* pointer to adapter context */ +#endif +{ + int DoneTxA[SK_MAX_MACS]; + int DoneTxS[SK_MAX_MACS]; + int Port; + SK_BOOL handledStatLE = SK_FALSE; + SK_BOOL NewDone = SK_FALSE; + SK_HWLE *pLE; + SK_U16 HighVal; + SK_U32 LowVal; + SK_U8 OpCode; + int i; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("==> HandleStatusLEs\n")); + + do { + if (OWN_OF_FIRST_LE(&pAC->StatusLETable) != HW_OWNER) + break; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("Check next Own Bit of ST-LE[%d]: 0x%li \n", + (pAC->StatusLETable.Done + 1) % NUM_LE_IN_TABLE(&pAC->StatusLETable), + OWN_OF_FIRST_LE(&pAC->StatusLETable))); + + while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) { + GET_ST_LE(pLE, &pAC->StatusLETable); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("Working on finished status LE[%d]:\n", + GET_DONE_INDEX(&pAC->StatusLETable))); + SK_DBG_DUMP_ST_LE(pLE); + handledStatLE = SK_TRUE; + OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER; + Port = STLE_GET_LINK(pLE); + +#ifdef USE_TIST_FOR_RESET + if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) { + /* do we just have a tist LE ? */ + if ((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) { + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + if (SK_PORT_WAITING_FOR_ANY_TIST(pAC, i)) { + /* if a port is waiting for any tist it is done */ + SK_CLR_STATE_FOR_PORT(pAC, i); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP, + ("Got any Tist on port %c (now 0x%X!!!)\n", + 'A' + i, pAC->AdapterResetState)); + } + if (SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, i)) { + Y2_GET_TIST_LOW_VAL(pAC->IoBase, &LowVal); + if ((pAC->MinTistHi != pAC->GIni.GITimeStampCnt) || + (pAC->MinTistLo < LowVal)) { + /* time is up now */ + SK_CLR_STATE_FOR_PORT(pAC, i); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP, + ("Got expected Tist on Port %c (now 0x%X)!!!\n", + 'A' + i, pAC->AdapterResetState)); +#ifdef Y2_SYNC_CHECK + pAC->FramesWithoutSyncCheck = + Y2_RESYNC_WATERMARK; +#endif + } else { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP, + ("Got Tist %l:%l on Port %c but still waiting\n", + pAC->GIni.GITimeStampCnt, pAC->MinTistLo, + 'A' + i)); + } + } + } +#ifndef Y2_RECOVERY + if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) { + /* nobody needs tist anymore - turn it off */ + Y2_DISABLE_TIST(pAC->IoBase); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP, + ("Turn off Tist !!!\n")); + } +#endif + } else if (OpCode == OP_TXINDEXLE) { + /* + * change OpCode to notify the folowing code + * to ignore the done index from this LE + * unfortunately tist LEs will be generated only + * for RxStat LEs + * so in order to get a safe Done index for a + * port currently waiting for a tist we have to + * get the done index directly from the BMU + */ + OpCode = OP_MOD_TXINDEX; + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP, + ("Mark unusable TX_INDEX LE!!!\n")); + } else { + if (SK_PORT_WAITING_FOR_TIST(pAC, Port)) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP, + ("Ignore LE 0x%X on Port %c!!!\n", + OpCode, 'A' + Port)); + OpCode = OP_MOD_LE; +#ifdef Y2_LE_CHECK + /* mark entries invalid */ + pAC->LastOpc = 0xFF; + pAC->LastPort = 3; +#endif + } + } + } /* if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) */ +#endif + + + + + +#ifdef Y2_LE_CHECK + if (pAC->LastOpc != 0xFF) { + /* last opc is valid + * check if current opcode follows last opcode + */ + if ((((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) && (pAC->LastOpc != OP_RXSTAT)) || + (((OpCode & OP_RXCHKS) == OP_RXCHKS) && (pAC->LastOpc != OP_RXTIMESTAMP)) || + ((OpCode == OP_RXSTAT) && (pAC->LastOpc != OP_RXCHKS))) { + + /* opcode sequence broken + * current LE is invalid + */ + + if (pAC->LastOpc == OP_RXTIMESTAMP) { + /* force invalid checksum */ + pLE->St.StUn.StRxTCPCSum.RxTCPSum1 = 1; + pLE->St.StUn.StRxTCPCSum.RxTCPSum2 = 0; + OpCode = pAC->LastOpc = OP_RXCHKS; + Port = pAC->LastPort; + } else if (pAC->LastOpc == OP_RXCHKS) { + /* force invalid frame */ + Port = pAC->LastPort; + pLE->St.Stat.BufLen = 64; + pLE->St.StUn.StRxStatWord = GMR_FS_CRC_ERR; + OpCode = pAC->LastOpc = OP_RXSTAT; +#ifdef Y2_SYNC_CHECK + /* force rx sync check */ + pAC->FramesWithoutSyncCheck = Y2_RESYNC_WATERMARK; +#endif + } else if (pAC->LastOpc == OP_RXSTAT) { + /* create dont care tist */ + pLE->St.StUn.StRxTimeStamp = 0; + OpCode = pAC->LastOpc = OP_RXTIMESTAMP; + /* dont know the port yet */ + } else { +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("Unknown LastOpc %X for Timestamp on port %c.\n", + pAC->LastOpc, Port)); +#endif + } + } + } +#endif + + switch (OpCode) { + case OP_RXSTAT: +#ifdef Y2_RECOVERY + pAC->LastOpc = OP_RXSTAT; +#endif + /* + ** This is always the last Status LE belonging + ** to a received packet -> handle it... + */ + if ((Port != 0) && (Port != 1)) { + /* Unknown port */ + panic("sk98lin: Unknown port %d\n", + Port); + } + + HandleReceives( + pAC, + Port, + STLE_GET_LEN(pLE), + STLE_GET_FRSTATUS(pLE), + pAC->StatusLETable.Bmu.Stat.TcpSum1, + pAC->StatusLETable.Bmu.Stat.TcpSum2, + pAC->StatusLETable.Bmu.Stat.RxTimeStamp, + pAC->StatusLETable.Bmu.Stat.VlanId); +#ifdef CONFIG_SK98LIN_NAPI + if (*WorkDone >= WorkToDo) { + break; + } + (*WorkDone)++; +#endif + break; + case OP_RXVLAN: + /* this value will be used for next RXSTAT */ + pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE); + break; + case OP_RXTIMEVLAN: + /* this value will be used for next RXSTAT */ + pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE); + /* fall through */ + case OP_RXTIMESTAMP: + /* this value will be used for next RXSTAT */ + pAC->StatusLETable.Bmu.Stat.RxTimeStamp = STLE_GET_TIST(pLE); +#ifdef Y2_RECOVERY + pAC->LastOpc = OP_RXTIMESTAMP; + pAC->LastPort = Port; +#endif + break; + case OP_RXCHKSVLAN: + /* this value will be used for next RXSTAT */ + pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE); + /* fall through */ + case OP_RXCHKS: + /* this value will be used for next RXSTAT */ + pAC->StatusLETable.Bmu.Stat.TcpSum1 = STLE_GET_TCP1(pLE); + pAC->StatusLETable.Bmu.Stat.TcpSum2 = STLE_GET_TCP2(pLE); +#ifdef Y2_RECOVERY + pAC->LastPort = Port; + pAC->LastOpc = OP_RXCHKS; +#endif + break; + case OP_RSS_HASH: + /* this value will be used for next RXSTAT */ +#if 0 + pAC->StatusLETable.Bmu.Stat.RssHashValue = STLE_GET_RSS(pLE); +#endif + break; + case OP_TXINDEXLE: + /* + ** :;:; TODO + ** it would be possible to check for which queues + ** the index has been changed and call + ** CheckForSendComplete() only for such queues + */ + STLE_GET_DONE_IDX(pLE,LowVal,HighVal); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("LowVal: 0x%x HighVal: 0x%x\n", LowVal, HighVal)); + + /* + ** It would be possible to check whether we really + ** need the values for second port or sync queue, + ** but I think checking whether we need them is + ** more expensive than the calculation + */ + DoneTxA[0] = STLE_GET_DONE_IDX_TXA1(LowVal,HighVal); + DoneTxS[0] = STLE_GET_DONE_IDX_TXS1(LowVal,HighVal); + DoneTxA[1] = STLE_GET_DONE_IDX_TXA2(LowVal,HighVal); + DoneTxS[1] = STLE_GET_DONE_IDX_TXS2(LowVal,HighVal); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("DoneTxa1 0x%x DoneTxS1: 0x%x DoneTxa2 0x%x DoneTxS2: 0x%x\n", + DoneTxA[0], DoneTxS[0], DoneTxA[1], DoneTxS[1])); + + NewDone = SK_TRUE; + break; +#ifdef USE_TIST_FOR_RESET + case OP_MOD_TXINDEX: + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP, + ("OP_MOD_TXINDEX\n")); + SK_IN16(pAC->IoBase, Q_ADDR(Q_XA1, Q_DONE), &DoneTxA[0]); + if (pAC->GIni.GIMacsFound > 1) { + SK_IN16(pAC->IoBase, Q_ADDR(Q_XA2, Q_DONE), &DoneTxA[1]); + } + NewDone = SK_TRUE; + break; + case OP_MOD_LE: + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP, + ("Ignore marked LE on port in Reset\n")); + break; +#endif + + default: + /* + ** Have to handle the illegal Opcode in Status LE + */ + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("Unexpected OpCode\n")); + break; + } + +#ifdef Y2_RECOVERY + OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER; + STLE_SET_OPC(pLE, OpCode); +#else + /* + ** Reset own bit we have to do this in order to detect a overflow + */ + STLE_SET_OPC(pLE, SW_OWNER); +#endif + } /* while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) */ + + /* + ** Now handle any new transmit complete + */ + if (NewDone) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("Done Index for Tx BMU has been changed\n")); + for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) { + /* + ** Do we have a new Done idx ? + */ + if (DoneTxA[Port] != GET_DONE_INDEX(&pAC->TxPort[Port][0].TxALET)) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("Check TxA%d\n", Port + 1)); + CheckForSendComplete(pAC, pAC->IoBase, Port, + &(pAC->TxPort[Port][0].TxAQ_working), + &pAC->TxPort[Port][0].TxALET, + DoneTxA[Port]); + } else { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("No changes for TxA%d\n", Port + 1)); + } +#if USE_SYNC_TX_QUEUE + if (HW_SYNC_TX_SUPPORTED(pAC)) { + /* + ** Do we have a new Done idx ? + */ + if (DoneTxS[Port] != + GET_DONE_INDEX(&pAC->TxPort[Port][0].TxSLET)) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("Check TxS%d\n", Port)); + CheckForSendComplete(pAC, pAC->IoBase, Port, + &(pAC->TxPort[Port][0].TxSQ_working), + &pAC->TxPort[Port][0].TxSLET, + DoneTxS[Port]); + } else { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("No changes for TxS%d\n", Port)); + } + } +#endif + } + } + NewDone = SK_FALSE; + + /* + ** Check whether we have to refill our RX table + */ + if (HW_FEATURE(pAC, HWF_WA_DEV_420)) { + if (NbrRxBuffersInHW < MAX_NBR_RX_BUFFERS_IN_HW) { + for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("Check for refill of RxBuffers on Port %c\n", 'A' + Port)); + FillReceiveTableYukon2(pAC, pAC->IoBase, Port); + } + } + } else { + for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("Check for refill of RxBuffers on Port %c\n", 'A' + Port)); + if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) >= 64) { + FillReceiveTableYukon2(pAC, pAC->IoBase, Port); + } + } + } +#ifdef CONFIG_SK98LIN_NAPI + if (*WorkDone >= WorkToDo) { + break; + } +#endif + } while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER); + + /* + ** Clear status BMU + */ + if (handledStatLE) + SK_OUT32(pAC->IoBase, STAT_CTRL, SC_STAT_CLR_IRQ); + + return(handledStatLE); +} /* HandleStatusLEs */ + +/***************************************************************************** + * + * AllocateAndInitLETables - allocate memory for the LETable and init + * + * Description: + * This function will allocate space for the LETable and will also + * initialize them. The size of the tables must have been specified + * before. + * + * Arguments: + * pAC - A pointer to the adapter context struct. + * + * Returns: + * SK_TRUE - all LETables initialized + * SK_FALSE - failed + */ +static SK_BOOL AllocateAndInitLETables( +SK_AC *pAC) /* pointer to adapter context */ +{ + char *pVirtMemAddr; + dma_addr_t pPhysMemAddr = 0; + SK_U32 CurrMac; + unsigned Size; + unsigned Aligned; + unsigned Alignment; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("==> AllocateAndInitLETables()\n")); + + /* + ** Determine how much memory we need with respect to alignment + */ + Alignment = MAX_LEN_OF_LE_TAB; + Size = 0; + for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) { + SK_ALIGN_SIZE(LE_TAB_SIZE(RX_MAX_LE), Alignment, Aligned); + Size += Aligned; + SK_ALIGN_SIZE(LE_TAB_SIZE(TXA_MAX_LE), Alignment, Aligned); + Size += Aligned; + SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned); + Size += Aligned; + } + SK_ALIGN_SIZE(LE_TAB_SIZE(ST_MAX_LE), Alignment, Aligned); + Size += Aligned; + Size += Alignment; + pAC->SizeOfAlignedLETables = Size; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("Need %08x bytes in total\n", Size)); + + /* + ** Allocate the memory + */ + pVirtMemAddr = pci_alloc_consistent(pAC->PciDev, Size, &pPhysMemAddr); + if (pVirtMemAddr == NULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, + SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR, + ("AllocateAndInitLETables: kernel malloc failed!\n")); + return (SK_FALSE); + } + + /* + ** Initialize the memory + */ + SK_MEMSET(pVirtMemAddr, 0, Size); + ALIGN_ADDR(pVirtMemAddr, Alignment); /* Macro defined in skgew.h */ + +#if 1 /* Marvell - uboot */ + ALIGN_ADDR(pPhysMemAddr, Alignment); +#endif + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("Virtual address of LETab is %8p!\n", pVirtMemAddr)); + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("Phys address of LETab is %8p!\n", (void *) pPhysMemAddr)); + + for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) { + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("RxLeTable for Port %c", 'A' + CurrMac)); + SkGeY2InitSingleLETable( + pAC, + &pAC->RxPort[CurrMac].RxLET, + RX_MAX_LE, + pVirtMemAddr, + (SK_U32) (pPhysMemAddr & 0xffffffff), + (SK_U32) (((SK_U64) pPhysMemAddr) >> 32)); + + SK_ALIGN_SIZE(LE_TAB_SIZE(RX_MAX_LE), Alignment, Aligned); + pVirtMemAddr += Aligned; + pPhysMemAddr += Aligned; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("TxALeTable for Port %c", 'A' + CurrMac)); + SkGeY2InitSingleLETable( + pAC, + &pAC->TxPort[CurrMac][0].TxALET, + TXA_MAX_LE, + pVirtMemAddr, + (SK_U32) (pPhysMemAddr & 0xffffffff), + (SK_U32) (((SK_U64) pPhysMemAddr) >> 32)); + + SK_ALIGN_SIZE(LE_TAB_SIZE(TXA_MAX_LE), Alignment, Aligned); + pVirtMemAddr += Aligned; + pPhysMemAddr += Aligned; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("TxSLeTable for Port %c", 'A' + CurrMac)); + SkGeY2InitSingleLETable( + pAC, + &pAC->TxPort[CurrMac][0].TxSLET, + TXS_MAX_LE, + pVirtMemAddr, + (SK_U32) (pPhysMemAddr & 0xffffffff), + (SK_U32) (((SK_U64) pPhysMemAddr) >> 32)); + + SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned); + pVirtMemAddr += Aligned; + pPhysMemAddr += Aligned; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,("StLeTable")); + + SkGeY2InitSingleLETable( + pAC, + &pAC->StatusLETable, + ST_MAX_LE, + pVirtMemAddr, + (SK_U32) (pPhysMemAddr & 0xffffffff), + (SK_U32) (((SK_U64) pPhysMemAddr) >> 32)); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("<== AllocateAndInitLETables(OK)\n")); + return(SK_TRUE); +} /* AllocateAndInitLETables */ + +/***************************************************************************** + * + * AllocatePacketBuffersYukon2 - allocate packet and fragment buffers + * + * Description: + * This function will allocate space for the packets and fragments + * + * Arguments: + * pAC - A pointer to the adapter context struct. + * + * Returns: + * SK_TRUE - Memory was allocated correctly + * SK_FALSE - An error occured + */ +static SK_BOOL AllocatePacketBuffersYukon2( +SK_AC *pAC) /* pointer to adapter context */ +{ + SK_PACKET *pRxPacket; + SK_PACKET *pTxPacket; + SK_U32 CurrBuff; + SK_U32 CurrMac; + unsigned long Flags; /* needed for POP/PUSH functions */ + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("==> AllocatePacketBuffersYukon2()")); + + for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) { + /* + ** Allocate RX packet space, initialize the packets and + ** add them to the RX waiting queue. Waiting queue means + ** that packet and fragment are initialized, but no sk_buff + ** has been assigned to it yet. + */ + pAC->RxPort[CurrMac].ReceivePacketTable = + kmalloc((RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL); + + if (pAC->RxPort[CurrMac].ReceivePacketTable == NULL) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR, + ("AllocatePacketBuffersYukon2: no mem RxPkts (port %i)",CurrMac)); + break; + } else { + SK_MEMSET(pAC->RxPort[CurrMac].ReceivePacketTable, 0, + (RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET))); + + pRxPacket = pAC->RxPort[CurrMac].ReceivePacketTable; + + for (CurrBuff=0;CurrBuffpFrag = &(pRxPacket->FragArray[0]); + pRxPacket->NumFrags = 1; + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[CurrMac].RxQ_waiting, pRxPacket); + pRxPacket++; + } + } + + /* + ** Allocate TX packet space, initialize the packets and + ** add them to the TX free queue. Free queue means that + ** packet is available and initialized, but no fragment + ** has been assigned to it. (Must be done at TX side) + */ + pAC->TxPort[CurrMac][0].TransmitPacketTable = + kmalloc((TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL); + + if (pAC->TxPort[CurrMac][0].TransmitPacketTable == NULL) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR, + ("AllocatePacketBuffersYukon2: no mem TxPkts (port %i)",CurrMac)); + kfree(pAC->RxPort[CurrMac].ReceivePacketTable); + return(SK_FALSE); + } else { + SK_MEMSET(pAC->TxPort[CurrMac][0].TransmitPacketTable, 0, + (TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET))); + + pTxPacket = pAC->TxPort[CurrMac][0].TransmitPacketTable; + + for (CurrBuff=0;CurrBuffTxPort[CurrMac][0].TxQ_free, pTxPacket); + pTxPacket++; + } + } + } /* end for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) */ + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT, + ("<== AllocatePacketBuffersYukon2 (OK)\n")); + return(SK_TRUE); + +} /* AllocatePacketBuffersYukon2 */ + +/***************************************************************************** + * + * FreeLETables - release allocated memory of LETables + * + * Description: + * This function will free all resources of the LETables + * + * Arguments: + * pAC - A pointer to the adapter context struct. + * + * Returns: N/A + */ +static void FreeLETables( +SK_AC *pAC) /* pointer to adapter control context */ +{ + dma_addr_t pPhysMemAddr; + char *pVirtMemAddr; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("==> FreeLETables()\n")); + + /* + ** The RxLETable is the first of all LET. + ** Therefore we can use its address for the input + ** of the free function. + */ + pVirtMemAddr = (char *) pAC->RxPort[0].RxLET.pLETab; + pPhysMemAddr = (((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABHigh << (SK_U64) 32) | + ((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABLow)); + + /* free continuous memory */ + pci_free_consistent(pAC->PciDev, pAC->SizeOfAlignedLETables, + pVirtMemAddr, pPhysMemAddr); + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("<== FreeLETables()\n")); +} /* FreeLETables */ + +/***************************************************************************** + * + * FreePacketBuffers - free's all packet buffers of an adapter + * + * Description: + * This function will free all previously allocated memory of the + * packet buffers. + * + * Arguments: + * pAC - A pointer to the adapter context struct. + * + * Returns: N/A + */ +static void FreePacketBuffers( +SK_AC *pAC) /* pointer to adapter control context */ +{ + int Port; + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("==> FreePacketBuffers()\n")); + + for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) { + kfree(pAC->RxPort[Port].ReceivePacketTable); + kfree(pAC->TxPort[Port][0].TransmitPacketTable); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG, + ("<== FreePacketBuffers()\n")); +} /* FreePacketBuffers */ + +/***************************************************************************** + * + * AllocAndMapRxBuffer - fill one buffer into the receive packet/fragment + * + * Description: + * The function allocates a new receive buffer and assigns it to the + * the passsed receive packet/fragment + * + * Returns: + * SK_TRUE - a buffer was allocated and assigned + * SK_FALSE - a buffer could not be added + */ +static SK_BOOL AllocAndMapRxBuffer( +SK_AC *pAC, /* pointer to the adapter control context */ +SK_PACKET *pSkPacket, /* pointer to packet that is to fill */ +int Port) /* port the packet belongs to */ +{ + struct sk_buff *pMsgBlock; /* pointer to a new message block */ + SK_U64 PhysAddr; /* physical address of a rx buffer */ + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("--> AllocAndMapRxBuffer (Port: %i)\n", Port)); + + pMsgBlock = alloc_skb(pAC->RxPort[Port].RxBufSize, GFP_ATOMIC); +#if 1 /*Marvell - uboot*/ + skb_reserve(pMsgBlock, 2); /* to align IP frames */ +#endif + if (pMsgBlock == NULL) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR, + ("%s: Allocation of rx buffer failed !\n", + pAC->dev[Port]->name)); + SK_PNMI_CNT_NO_RX_BUF(pAC, pAC->RxPort[Port].PortIndex); + return(SK_FALSE); + } + skb_reserve(pMsgBlock, 8); + +#if 0 /* uboot */ + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, + virt_to_page(pMsgBlock->data), + ((unsigned long) pMsgBlock->data & + ~PAGE_MASK), + pAC->RxPort[Port].RxBufSize, + PCI_DMA_FROMDEVICE); +#else + PhysAddr = (SK_U64)(SK_U32)pMsgBlock->data; +#endif + + pSkPacket->pFrag->pVirt = pMsgBlock->data; + pSkPacket->pFrag->pPhys = PhysAddr; + pSkPacket->pFrag->FragLen = pAC->RxPort[Port].RxBufSize; /* for correct unmap */ + pSkPacket->pMBuf = pMsgBlock; + pSkPacket->PacketLen = pAC->RxPort[Port].RxBufSize; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS, + ("<-- AllocAndMapRxBuffer\n")); + + return (SK_TRUE); +} /* AllocAndMapRxBuffer */ + +/******************************************************************************* + * + * End of file + * + ******************************************************************************/ + +#endif diff --git a/drivers/sk98lin/sky2le.c b/drivers/sk98lin/sky2le.c new file mode 100644 index 0000000..16b6770 --- /dev/null +++ b/drivers/sk98lin/sky2le.c @@ -0,0 +1,511 @@ +/***************************************************************************** + * + * Name: sky2le.c + * Project: Gigabit Ethernet Adapters, Common Modules + * Version: $Revision: 1.13 $ + * Date: $Date: 2006/04/05 14:06:06 $ + * Purpose: Functions for handling List Element Tables + * + *****************************************************************************/ + +/****************************************************************************** + * + * LICENSE: + * (C)Copyright 2002-2006 Marvell. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * The information in this file is provided "AS IS" without warranty. + * /LICENSE + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM)))) +static const char SysKonnectFileId[] = "@(#)" + "$Id: sky2le.c,v 1.8 2004/06/03 15:09:29 malthoff Exp $ (C) Marvell."; +#endif /* DEBUG || (!LINT && !SK_SLIM) */ + +/***************************************************************************** + * + * Description: + * + * This module contains the code necessary for handling List Elements. + * + * Supported Gigabit Ethernet Chipsets: + * Yukon-2 (PCI, PCI-X, PCI-Express) + * + * Include File Hierarchy: + * + * + *****************************************************************************/ +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + +/* defines *******************************************************************/ +/* typedefs ******************************************************************/ +/* global variables **********************************************************/ +/* local variables ***********************************************************/ +/* function prototypes *******************************************************/ + +/***************************************************************************** + * + * SkGeY2InitSingleLETable() - initializes a list element table + * + * Description: + * This function will initialize the selected list element table. + * Should be called once during DriverInit. No InitLevel required. + * + * Arguments: + * pAC - pointer to the adapter context struct. + * pLETab - pointer to list element table structure + * NumLE - number of list elements in this table + * pVMem - virtual address of memory allocated for this LE table + * PMemLowAddr - physical address of memory to be used for the LE table + * PMemHighAddr + * + * Returns: + * nothing + */ +void SkGeY2InitSingleLETable( +SK_AC *pAC, /* pointer to adapter context */ +SK_LE_TABLE *pLETab, /* pointer to list element table to be initialized */ +unsigned int NumLE, /* number of list elements to be filled in tab */ +void *pVMem, /* virtual address of memory used for list elements */ +SK_U32 PMemLowAddr, /* physical addr of mem used for LE */ +SK_U32 PMemHighAddr) +{ + unsigned int i; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("==> SkGeY2InitSingleLETable()\n")); + +#ifdef DEBUG + if (NumLE != 2) { /* not table for polling unit */ + if ((NumLE % MIN_LEN_OF_LE_TAB) != 0 || NumLE > MAX_LEN_OF_LE_TAB) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("ERROR: Illegal number of list elements %d\n", NumLE)); + } + } +#endif /* DEBUG */ + + /* special case: unused list element table */ + if (NumLE == 0) { + PMemLowAddr = 0; + PMemHighAddr = 0; + pVMem = 0; + } + + /* + * in order to get the best possible performance the macros to access + * list elements use & instead of % + * this requires the length of LE tables to be a power of 2 + */ + + /* + * this code guarantees that we use the next power of 2 below the + * value specified for NumLe - this way some LEs in the table may + * not be used but the macros work correctly + * this code does not check for bad values below 128 because in such a + * case we cannot do anything here + */ + + if ((NumLE != 2) && (NumLE != 0)) { + /* no check for polling unit and unused sync Tx */ + i = MIN_LEN_OF_LE_TAB; + while (NumLE > i) { + i *= 2; + if (i > MAX_LEN_OF_LE_TAB) { + break; + } + } + if (NumLE != i) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("ERROR: Illegal number of list elements %d adjusted to %d\n", + NumLE, (i / 2))); + NumLE = i / 2; + } + } + + /* set addresses */ + pLETab->pPhyLETABLow = PMemLowAddr; + pLETab->pPhyLETABHigh = PMemHighAddr; + pLETab->pLETab = pVMem; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("contains %d LEs", NumLE)); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + (" and starts at virt %08lx and phys %08lx:%08lx\n", + pVMem, PMemHighAddr, PMemLowAddr)); + + /* initialize indexes */ + pLETab->Done = 0; + pLETab->Put = 0; + pLETab->HwPut = 0; + /* initialize size */ + pLETab->Num = NumLE; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("<== SkGeY2InitSingleLETable()\n")); +} /* SkGeY2InitSingleLETable */ + +/***************************************************************************** + * + * SkGeY2InitPrefetchUnit() - Initialize a Prefetch Unit + * + * Description: + * Calling this function requires an already configured list element + * table. The prefetch unit to be configured is specified in the parameter + * 'Queue'. The function is able to initialze the prefetch units of + * the following queues: Q_R1, Q_R2, Q_XS1, Q_XS2, Q_XA1, Q_XA2. + * The funcution should be called before SkGeInitPort(). + * + * Arguments: + * pAC - pointer to the adapter context struct. + * IoC - I/O context. + * Queue - I/O offset of queue e.g. Q_XA1. + * pLETab - pointer to list element table to be initialized + * + * Returns: N/A + */ +void SkGeY2InitPrefetchUnit( +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* I/O context */ +unsigned int Queue, /* Queue offset for finding the right registers */ +SK_LE_TABLE *pLETab) /* pointer to list element table to be initialized */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("==> SkGeY2InitPrefetchUnit()\n")); + +#ifdef DEBUG + if (Queue != Q_R1 && Queue != Q_R2 && Queue != Q_XS1 && + Queue != Q_XS2 && Queue != Q_XA1 && Queue != Q_XA2) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR, + ("ERROR: Illegal queue identifier %x\n", Queue)); + } +#endif /* DEBUG */ + + /* disable the prefetch unit */ + SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET); + SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_CLR); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Base address: %08lx:%08lx\n", pLETab->pPhyLETABHigh, + pLETab->pPhyLETABLow)); + + /* Set the list base address high part*/ + SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_HI_REG), + pLETab->pPhyLETABHigh); + + /* Set the list base address low part */ + SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_LOW_REG), + pLETab->pPhyLETABLow); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Last index: %d\n", pLETab->Num-1)); + + /* Set the list last index */ + SK_OUT16(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_LAST_IDX_REG), + (SK_U16)(pLETab->Num - 1)); + + /* turn on prefetch unit */ + SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_OP_ON); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("<== SkGeY2InitPrefetchUnit()\n")); +} /* SkGeY2InitPrefetchUnit */ + + +/***************************************************************************** + * + * SkGeY2InitStatBmu() - Initialize the Status BMU + * + * Description: + * Calling this function requires an already configured list element + * table. Ensure the status BMU is only initialized once during + * DriverInit - InitLevel2 required. + * + * Arguments: + * pAC - pointer to the adapter context struct. + * IoC - I/O context. + * pLETab - pointer to status LE table to be initialized + * + * Returns: N/A + */ +void SkGeY2InitStatBmu( +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* I/O context */ +SK_LE_TABLE *pLETab) /* pointer to status LE table */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("==> SkGeY2InitStatBmu()\n")); + + /* disable the prefetch unit */ + SK_OUT32(IoC, STAT_CTRL, SC_STAT_RST_SET); + SK_OUT32(IoC, STAT_CTRL, SC_STAT_RST_CLR); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Base address Low: %08lX\n", pLETab->pPhyLETABLow)); + + /* Set the list base address */ + SK_OUT32(IoC, STAT_LIST_ADDR_LO, pLETab->pPhyLETABLow); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Base address High: %08lX\n", pLETab->pPhyLETABHigh)); + + SK_OUT32(IoC, STAT_LIST_ADDR_HI, pLETab->pPhyLETABHigh); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Last index: %d\n", pLETab->Num - 1)); + + /* Set the list last index */ + SK_OUT16(IoC, STAT_LAST_IDX, (SK_U16)(pLETab->Num - 1)); + + if (HW_FEATURE(pAC, HWF_WA_DEV_43_418)) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Set Tx index threshold\n")); + /* WA for dev. #4.3 */ + SK_OUT16(IoC, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); + + /* set Status-FIFO watermark */ + SK_OUT8(IoC, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */ + + /* set Status-FIFO ISR watermark */ + SK_OUT8(IoC, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */ + + /* WA for dev. #4.3 and #4.18 */ + /* set Status-FIFO Tx timer init value */ + SK_OUT32(IoC, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC, 10)); + } + else { + /* + * Further settings may be added if required... + * 1) Status-FIFO watermark (STAT_FIFO_WM, STAT_FIFO_ISR_WM) + * 2) Status-FIFO timer values (STAT_TX_TIMER_INI, + * STAT_LEV_TIMER_INI and STAT_ISR_TIMER_INI) + * but tests shows that the default values give the best results, + * therefore the defaults are used. + */ + + /* + * Theses settings should avoid the temporary hang of the status BMU. + * May be not all required... still under investigation... + */ + SK_OUT16(IoC, STAT_TX_IDX_TH, 0x000a); + + /* set Status-FIFO watermark */ + SK_OUT8(IoC, STAT_FIFO_WM, 0x10); + + /* set Status-FIFO ISR watermark */ + SK_OUT8(IoC, STAT_FIFO_ISR_WM, + HW_FEATURE(pAC, HWF_WA_DEV_4109) ? 0x10 : 0x04); + + /* set ISR Timer Init Value to 400 (3.2 us on Yukon-EC) */ + SK_OUT32(IoC, STAT_ISR_TIMER_INI, 0x0190); + } + + /* start Status-FIFO timer */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Start Status FiFo timer\n")); + + /* enable the prefetch unit */ + /* operational bit not functional for Yukon-EC, but fixed in Yukon-2 */ + SK_OUT32(IoC, STAT_CTRL, SC_STAT_OP_ON); + + /* start Status-FIFO timer */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Start Status FiFo timer\n")); + + SK_OUT8(IoC, STAT_TX_TIMER_CTRL, TIM_START); + SK_OUT8(IoC, STAT_LEV_TIMER_CTRL, TIM_START); + SK_OUT8(IoC, STAT_ISR_TIMER_CTRL, TIM_START); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("<== SkGeY2InitStatBmu()\n")); +} /* SkGeY2InitStatBmu */ + +#ifdef USE_POLLING_UNIT +/***************************************************************************** + * + * SkGeY2InitPollUnit() - Initialize the Polling Unit + * + * Description: + * This function will write the data of one polling LE table into the + * adapter. + * + * Arguments: + * pAC - pointer to the adapter context struct. + * IoC - I/O context. + * pLETab - pointer to polling LE table to be initialized + * + * Returns: N/A + */ +void SkGeY2InitPollUnit( +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* I/O context */ +SK_LE_TABLE *pLETab) /* pointer to polling LE table */ +{ + SK_HWLE *pLE; + int i; +#ifdef VCPU + VCPU_VARS(); +#endif /* VCPU */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("==> SkGeY2InitPollUnit()\n")); + +#ifdef VCPU + for (i = 0; i < SK_MAX_MACS; i++) { + GET_PO_LE(pLE, pLETab, i); + VCPU_START_AND_COPY_LE(); + /* initialize polling LE but leave indexes invalid */ + POLE_SET_OPC(pLE, OP_PUTIDX | HW_OWNER); + POLE_SET_LINK(pLE, i); + POLE_SET_RXIDX(pLE, 0); + POLE_SET_TXAIDX(pLE, 0); + POLE_SET_TXSIDX(pLE, 0); + VCPU_WRITE_LE(); + SK_DBG_DUMP_PO_LE(pLE); + } +#endif /* VCPU */ + + /* disable the polling unit */ + SK_OUT32(IoC, POLL_CTRL, PC_POLL_RST_SET); + SK_OUT32(IoC, POLL_CTRL, PC_POLL_RST_CLR); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Base address Low: %08lX\n", pLETab->pPhyLETABLow)); + + /* Set the list base address */ + SK_OUT32(IoC, POLL_LIST_ADDR_LO, pLETab->pPhyLETABLow); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("Base address High: %08lX\n", pLETab->pPhyLETABHigh)); + + SK_OUT32(IoC, POLL_LIST_ADDR_HI, pLETab->pPhyLETABHigh); + + /* we don't need to write the last index - it is hardwired to 1 */ + + /* enable the prefetch unit */ + SK_OUT32(IoC, POLL_CTRL, PC_POLL_OP_ON); + + /* + * now we have to start the descriptor poll timer because it triggers + * the polling unit + */ + + /* + * still playing with the value (timer runs at 125 MHz) + * descriptor poll timer is enabled by GeInit + */ + SK_OUT32(IoC, B28_DPT_INI, + (SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100)); + + SK_OUT8(IoC, B28_DPT_CTRL, TIM_START); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("<== SkGeY2InitPollUnit()\n")); +} /* SkGeY2InitPollUnit */ +#endif /* USE_POLLING_UNIT */ + + +/****************************************************************************** + * + * SkGeY2SetPutIndex + * + * Description: + * This function is writing the Done index of a transmit + * list element table. + * + * Notes: + * Dev. Issue 4.2 + * + * Returns: N/A + */ +void SkGeY2SetPutIndex( +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* pointer to the IO context */ +SK_U32 StartAddrPrefetchUnit, /* start address of the prefetch unit */ +SK_LE_TABLE *pLETab) /* list element table to work with */ +{ + unsigned int Put; + SK_U16 EndOfListIndex; + SK_U16 HwGetIndex; + SK_U16 HwPutIndex; + + /* set put index we would like to write */ + Put = GET_PUT_IDX(pLETab); + + /* + * in this case we wrap around + * new put is lower than last put given to HW + */ + if (Put < pLETab->HwPut) { + + /* set put index = last index of list */ + EndOfListIndex = (NUM_LE_IN_TABLE(pLETab)-1); + + /* read get index of hw prefetch unit */ + SK_IN16(IoC, (StartAddrPrefetchUnit + PREF_UNIT_GET_IDX_REG), + &HwGetIndex); + + /* read put index of hw prefetch unit */ + SK_IN16(IoC, (StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG), + &HwPutIndex); + + /* prefetch unit reached end of list */ + /* prefetch unit reached first list element */ + if (HwGetIndex == 0) { + /* restore watermark */ + SK_OUT8(IoC, StartAddrPrefetchUnit + PREF_UNIT_FIFO_WM_REG, 0xe0U); + /* write put index */ + SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG, + (SK_U16)Put); + + /* remember put index we wrote to hw */ + pLETab->HwPut = Put; + } + else if (HwGetIndex == EndOfListIndex) { + /* set watermark to one list element */ + SK_OUT8(IoC, StartAddrPrefetchUnit + PREF_UNIT_FIFO_WM_REG, 8); + /* set put index to first list element */ + SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG, 0); + } + /* prefetch unit did not reach end of list yet */ + /* and we did not write put index to end of list yet */ + else if ((HwPutIndex != EndOfListIndex) && + (HwGetIndex != EndOfListIndex)) { + /* write put index */ + SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG, + EndOfListIndex); + } + else { + /* do nothing */ + } + } + else { +#ifdef XXX /* leads in to problems in the Windows Driver */ + if (Put != pLETab->HwPut) { + /* write put index */ + SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG, + (SK_U16)Put); + /* update put index */ + UPDATE_HWPUT_IDX(pLETab); + } +#else + /* write put index */ + SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG, + (SK_U16)Put); + /* update put index */ + UPDATE_HWPUT_IDX(pLETab); +#endif + } +} /* SkGeY2SetPutIndex */ + +#endif diff --git a/drivers/sk98lin/uboot_drv.c b/drivers/sk98lin/uboot_drv.c index 263dac8..8e6bd04 100644 --- a/drivers/sk98lin/uboot_drv.c +++ b/drivers/sk98lin/uboot_drv.c @@ -33,15 +33,19 @@ #include "u-boot_compat.h" -#define SKGE_MAX_CARDS 2 +#define SKGE_MAX_CARDS 4 extern int skge_probe(struct eth_device **); extern void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); extern void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); +/* Marvell - Yukon2 support*/ +extern void SkY2Isr(int irq, void *dev_id, struct pt_regs *ptregs); extern int SkGeOpen(struct eth_device *); extern int SkGeClose(struct eth_device *); extern int SkGeXmit(struct sk_buff *skb, struct eth_device *dev); +/* Marvell - Yukon2 support*/ +extern int SkY2Xmit(struct sk_buff *skb, struct eth_device *dev); extern void ReceiveIrq(SK_AC *pAC, RX_PORT *pRxPort, SK_BOOL SlowPathLock); static int skge_init(struct eth_device *dev, bd_t * bis); @@ -51,7 +55,7 @@ static void skge_halt(struct eth_device *dev); int skge_initialize(bd_t * bis) { - int numdev, i; + int numdev,i ; struct eth_device *dev[SKGE_MAX_CARDS]; numdev = skge_probe(&dev[0]); @@ -69,39 +73,92 @@ int skge_initialize(bd_t * bis) dev[i]->halt = skge_halt; dev[i]->send = skge_send; dev[i]->recv = skge_recv; - + eth_register(dev[i]); } - return numdev; } +/* ronen - since if we try to halt the dev after it was halted it cause a stuck I add this + global variable */ +int sk98_inited = 0; static int skge_init(struct eth_device *dev, bd_t * bis) { int ret; SK_AC * pAC = ((DEV_NET*)dev->priv)->pAC; - int i; + int i = 0; + + /* ronen */ + if(sk98_inited == 1) + skge_halt(dev); ret = SkGeOpen(dev); while (pAC->Rlmt.Port[0].PortState != SK_RLMT_PS_GOING_UP) { - SkGeIsrOnePort (0, pAC->dev[0], 0); + /* ronen - since if the link on the sk98 is down we don't want to wait here for ever */ + /* so I adde a counter */ + i++; + + /* Marvell - Yukon2 support*/ + if (CHIP_ID_YUKON_2(pAC)) { + SkY2Isr (0, pAC->dev[0], 0); + if(i > 1500000){ + ret = 1; + break; + } + + ret = 0; + } + else { + SkGeIsrOnePort (0, pAC->dev[0], 0); + if(i > 1500000){ + ret = 1; + break; + } + + } } - for (i = 0; i < 100; i ++) - { - udelay(1000); - } +// for (i = 0; i < 100; i ++) +// { +// udelay(1000); +// } - return ret; + /* ronen - for the SkGeOpen 0 is success and 1 is fail */ + /* the return except 1 for success */ + if(ret == 0){ + sk98_inited = 1; + return 1; + } + skge_halt(dev); + return 0; } - static void skge_halt(struct eth_device *dev) { + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; + + + /* ronen */ + if(sk98_inited == 0) + return; + + + /* Marvell - Yukon2 support*/ + /* to be in the safe side we call SkY2Isr to treat any + pending rx or tx complete */ + if (CHIP_ID_YUKON_2(pAC)) + { + SkY2Isr (0, pAC->dev[0], 0); + } + SkGeClose(dev); + + + sk98_inited = 0; } @@ -109,7 +166,9 @@ static int skge_send(struct eth_device *dev, volatile void *packet, int length) { int ret = -1; - struct sk_buff * skb = alloc_skb(length, 0); + struct sk_buff * skb = alloc_skb(length,0); + DEV_NET *pNet = (DEV_NET*) dev->priv; + SK_AC *pAC = pNet->pAC; if (! skb) { @@ -118,8 +177,14 @@ static int skge_send(struct eth_device *dev, volatile void *packet, } memcpy(skb->data, (void*)packet, length); - ret = SkGeXmit(skb, dev); + /* Marvell - Yukon2 support*/ + if (CHIP_ID_YUKON_2(pAC)) { + ret = SkY2Xmit(skb,dev); + } + else { + ret = SkGeXmit(skb, dev); + } Done: return ret; } @@ -134,7 +199,15 @@ static int skge_recv(struct eth_device *dev) pNet = (DEV_NET*) dev->priv; pAC = pNet->pAC; - ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); + /* Marvell - Yukon2 support*/ + if (CHIP_ID_YUKON_2(pAC)) { + + SkY2Isr (0, pAC->dev[0], 0); + } + else { + + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); + } return 0; } diff --git a/drivers/sk98lin/uboot_skb.c b/drivers/sk98lin/uboot_skb.c index 3a487a8..eaa46f6 100644 --- a/drivers/sk98lin/uboot_skb.c +++ b/drivers/sk98lin/uboot_skb.c @@ -30,16 +30,25 @@ #include #include "u-boot_compat.h" -#define MAX_SKB 50 +#define MAX_SKB 128 -static struct sk_buff *sk_table[MAX_SKB]; +struct sk_buff *sk_table[MAX_SKB]; +unsigned int skbAlloc=0,skbFree=0; +/*unsigned int cntrMalloc=0,cntrFree=0; +unsigned int indxMalloc=0,indxFree=0; +*/ +extern int tftpCount; struct sk_buff * alloc_skb(u32 size, int dummy) { int i; struct sk_buff * ret = NULL; + if(0)/*if(tftpCount == 2)*/ + { + printf("alloc_skb , size=%d\n",size); + } for (i = 0; i < MAX_SKB; i++) { if (sk_table[i]) @@ -78,10 +87,20 @@ struct sk_buff * alloc_skb(u32 size, int dummy) ret = sk_table[i]; } + if(0)/*if(tftpCount == 2)*/ + { + printf("alloc_skb , i=%d sk_table[i]=0x%x sk_table[i]->data=0x%x\n",i,sk_table[i],sk_table[i]->data); + } + + if (! ret) { printf("Unable to allocate skb!\n"); } + else + { + skbAlloc++;; + } return ret; } @@ -90,12 +109,23 @@ void dev_kfree_skb_any(struct sk_buff *skb) { int i; + if(0)/*if(tftpCount == 2)*/ + { + printf("dev_kfree_skb_any , skb=0x%x\n",skb); + } + + for (i = 0; i < MAX_SKB; i++) { if (sk_table[i] != skb) { continue; } + if(0)/*if(tftpCount == 2)*/ + { + printf("dev_kfree_skb_any , i=%d sk_table[i]=0x%x sk_table[i]->data=0x%x\n",i,skb,skb->data_unaligned); + } + free(skb->data_unaligned); free(skb); @@ -107,6 +137,10 @@ void dev_kfree_skb_any(struct sk_buff *skb) { printf("SKB allocation error!\n"); } + else + { + skbFree++; + } } void skb_reserve(struct sk_buff *skb, unsigned int len) @@ -119,4 +153,7 @@ void skb_put(struct sk_buff *skb, unsigned int len) skb->len+=len; } + + + #endif /* CONFIG_SK98 */ diff --git a/drivers/usb/.depend b/drivers/usb/.depend new file mode 100644 index 0000000..1180283 --- /dev/null +++ b/drivers/usb/.depend @@ -0,0 +1,92 @@ +usbdcore.o: usbdcore.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/usbdcore.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/usbdescriptors.h +usbdcore_ep0.o: usbdcore_ep0.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +usb_ehci.o: usb_ehci.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/pci.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/pci_ids.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/usb.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/usb_defs.h \ + usb_ehci.h diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile new file mode 100644 index 0000000..bcd669f --- /dev/null +++ b/drivers/usb/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libusb.a + +COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o + +COBJS-y += usbdcore.o +COBJS-y += usbdcore_ep0.o +COBJS-y += usb_ehci.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/usb/usb_ehci.c b/drivers/usb/usb_ehci.c new file mode 100644 index 0000000..d0e91c8 --- /dev/null +++ b/drivers/usb/usb_ehci.c @@ -0,0 +1,757 @@ +/* Copyright (c) 2007-2008, Juniper Networks, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "usb_ehci.h" + +#undef EHCI_DEBUG +#ifdef EHCI_DEBUG +#define DBG(format, arg...) \ + printf("\rEHCI_DEBUG: %s: " format "\n", __func__, ## arg) +#else +#define DBG(format, arg...) \ + do {} while(0) +#endif /* EHCI_DEBUG */ + +static struct { + uint8_t hub[8]; + uint8_t device[18]; + uint8_t config[9]; + uint8_t interface[9]; + uint8_t endpoint[7]; +} descr = { + { /* HUB */ + sizeof(descr.hub), /* bDescLength */ + 0x29, /* bDescriptorType: hub descriptor */ + 1, /* bNrPorts -- runtime modified */ + 0, 0, /* wHubCharacteristics -- runtime modified */ + 0xff, /* bPwrOn2PwrGood */ + 0, /* bHubCntrCurrent */ + 0 /* DeviceRemovable XXX at most 7 ports! XXX */ + }, + { /* DEVICE */ + sizeof(descr.device), /* bLength */ + 1, /* bDescriptorType: UDESC_DEVICE */ + 0x00, 0x02, /* bcdUSB: v2.0 */ + 9, /* bDeviceClass: UDCLASS_HUB */ + 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ + 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ + 64, /* bMaxPacketSize: 64 bytes */ + 0x00, 0x00, /* idVendor */ + 0x00, 0x00, /* idProduct */ + 0x00, 0x01, /* bcdDevice */ + 1, /* iManufacturer */ + 2, /* iProduct */ + 0, /* iSerialNumber */ + 1 /* bNumConfigurations: 1 */ + }, + { /* CONFIG */ + sizeof(descr.config), /* bLength */ + 2, /* bDescriptorType: UDESC_CONFIG */ + sizeof(descr.config)+sizeof(descr.interface)+sizeof(descr.endpoint), 0, + /* wTotalLength */ + 1, /* bNumInterface */ + 1, /* bConfigurationValue */ + 0, /* iConfiguration */ + 0x40, /* bmAttributes: UC_SELF_POWERED */ + 0 /* bMaxPower */ + }, + { /* INTERFACE */ + sizeof(descr.interface), /* bLength */ + 4, /* bDescriptorType: UDESC_INTERFACE */ + 0, /* bInterfaceNumber */ + 0, /* bAlternateSetting */ + 1, /* bNumEndpoints */ + 9, /* bInterfaceClass: UICLASS_HUB */ + 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ + 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ + 0 /* iInterface */ + }, + { /* ENDPOINT */ + sizeof(descr.endpoint), /* bLength */ + 5, /* bDescriptorType: UDESC_ENDPOINT */ + 0x81, /* bEndpointAddress: UE_DIR_IN | EHCI_INTR_ENDPT */ + 3, /* bmAttributes: UE_INTERRUPT */ + 8, 0, /* wMaxPacketSize */ + 255 /* bInterval */ + } +}; + +static struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ +static volatile struct ehci_hcor *hcor; +static struct QH qh_list __attribute__((aligned(32))); +static int rootdev; +static uint16_t portreset; + +#ifdef EHCI_DEBUG +static void +dump_pci_reg(pci_dev_t dev, int ofs) +{ + uint32_t reg; + + pci_read_config_dword(dev, ofs, ®); + printf("\t0x%02x: %08x\n", ofs, reg); +} + +static void +dump_pci(int enh, pci_dev_t dev) +{ + int ofs; + + DBG("\n%s", (enh) ? "EHCI" : "OHCI"); + for (ofs = 0; ofs < 0x44; ofs += 4) + dump_pci_reg(dev, ofs); + if (enh) + dump_pci_reg(dev, 0x60); + dump_pci_reg(dev, 0xdc); + dump_pci_reg(dev, 0xe0); + if (enh) { + dump_pci_reg(dev, 0xe4); + dump_pci_reg(dev, 0xe8); + } +} + +static void +dump_regs(void) +{ + + DBG("usbcmd=%#x, usbsts=%#x, usbintr=%#x,\n\tfrindex=%#x, " + "ctrldssegment=%#x, periodiclistbase=%#x,\n\tasynclistaddr=%#x, " + "configflag=%#x,\n\tportsc[1]=%#x, portsc[2]=%#x, usbcmd=%#x", + swap_32(hcor->or_usbcmd), swap_32(hcor->or_usbsts), + swap_32(hcor->or_usbintr), swap_32(hcor->or_frindex), + swap_32(hcor->or_ctrldssegment), + swap_32(hcor->or_periodiclistbase), + swap_32(hcor->or_asynclistaddr), swap_32(hcor->or_configflag), + swap_32(hcor->or_portsc[0]), swap_32(hcor->or_portsc[1]), + swap_32(hcor->or_usbmode)); +} + +static void +dump_TD(struct qTD *td) +{ + + DBG("%p: qt_next=%#x, qt_altnext=%#x, qt_token=%#x, " + "qt_buffer={%#x,%#x,%#x,%#x,%#x}", td, swap_32(td->qt_next), + swap_32(td->qt_altnext), swap_32(td->qt_token), + swap_32(td->qt_buffer[0]), swap_32(td->qt_buffer[1]), + swap_32(td->qt_buffer[2]), swap_32(td->qt_buffer[3]), + swap_32(td->qt_buffer[4])); +} + +static void +dump_QH(struct QH *qh) +{ + + DBG("%p: qh_link=%#x, qh_endpt1=%#x, qh_endpt2=%#x, qh_curtd=%#x", + qh, swap_32(qh->qh_link), swap_32(qh->qh_endpt1), + swap_32(qh->qh_endpt2), swap_32(qh->qh_curtd)); + dump_TD(&qh->qh_overlay); +} +#endif + +static __inline int +min3(int a, int b, int c) +{ + + if (b < a) + a = b; + if (c < a) + a = c; + return (a); +} + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int +usb_lowlevel_init(void) +{ + pci_dev_t dev; + uint32_t addr, reg; + +#ifndef CONFIG_MARVELL + dev = pci_find_device(0x1131, 0x1561, 0); + if (dev != -1) { + volatile uint32_t *hcreg; + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &addr); + hcreg = (uint32_t *)(addr + 8); + *hcreg = swap_32(1); + udelay(100); + } + + dev = pci_find_device(0x1131, 0x1562, 0); + if (dev == -1) { + printf("EHCI host controller not found\n"); + return (-1); + } + + pci_read_config_dword(dev, EHCI_PCICS_USBBASE, &addr); +#else + addr = 0xF1050100; +#endif /* CONFIG_MARVELL */ + hccr = (void *)addr; + addr += hccr->cr_caplength; + hcor = (void *)addr; + /* Reset the device */ + hcor->or_usbcmd |= swap_32(2); + udelay(1000); + while (hcor->or_usbcmd & swap_32(2)) + udelay(1000); + + reg = swap_32(hccr->cr_hcsparams); + descr.hub[2] = reg & 0xf; + if (reg & 0x10000) /* Port Indicators */ + descr.hub[3] |= 0x80; + if (reg & 0x10) /* Port Power Control */ + descr.hub[3] |= 0x01; + + /* Marvell USB controller Host mode set */ + hcor->or_usbmode |= swap_32(3); + + /* take control over the ports */ +// hcor->or_configflag |= swap_32(1); + + /* Set head of reclaim list */ + memset(&qh_list, 0, sizeof(qh_list)); + qh_list.qh_link = swap_32((uint32_t)&qh_list | QH_LINK_TYPE_QH); + qh_list.qh_endpt1 = swap_32((1 << 15) | (USB_SPEED_HIGH << 12)); + qh_list.qh_curtd = swap_32(QT_NEXT_TERMINATE); + qh_list.qh_overlay.qt_next = swap_32(QT_NEXT_TERMINATE); + qh_list.qh_overlay.qt_altnext = swap_32(QT_NEXT_TERMINATE); + qh_list.qh_overlay.qt_token = swap_32(0x40); + + /* Set async. queue head pointer. */ + hcor->or_asynclistaddr = swap_32((uint32_t)&qh_list); + + /* Start the host controller. */ + hcor->or_usbcmd |= swap_32(1); + + rootdev = 0; + + return (0); +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int +usb_lowlevel_stop(void) +{ + return (0); +} + +static void * +ehci_alloc(size_t sz, size_t align) +{ + static struct QH qh __attribute__((aligned(32))); + static struct qTD td[4] __attribute__((aligned(32))); + static int ntds = 0; + void *p; + + switch (sz) { + case sizeof(struct QH): + p = &qh; + ntds = 0; + break; + case sizeof(struct qTD): + if (ntds == 3) { + DBG("out of TDs"); + return (NULL); + } + p = &td[ntds]; + ntds++; + break; + default: + DBG("unknown allocation size"); + return (NULL); + } + + memset(p, sz , 0); + return (p); +} + +static void +ehci_free(void *p, size_t sz) +{ +} + +static int +ehci_td_buffer(struct qTD *td, void *buf, size_t sz) +{ + uint32_t addr, delta, next; + int idx; + + addr = (uint32_t)buf; + idx = 0; + while (idx < 5) { + td->qt_buffer[idx] = swap_32(addr); + next = (addr + 4096) & ~4095; + delta = next - addr; + if (delta >= sz) + break; + sz -= delta; + addr = next; + idx++; + } + + if (idx == 5) { + DBG("out of buffer pointers (%u bytes left)", sz); + return (-1); + } + + return (0); +} + +static int +ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, + int length, struct devrequest *req) +{ + struct QH *qh; + struct qTD *td; + volatile struct qTD *vtd; + unsigned long ts; + uint32_t *tdp; + uint32_t endpt, token, usbsts; + uint32_t c, toggle; + + DBG("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p", dev, pipe, + buffer, length, req); + if (req != NULL) + DBG("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u", + req->request, req->request, + req->requesttype, req->requesttype, + swap_16(req->value), swap_16(req->value), + swap_16(req->index), swap_16(req->index)); + + qh = ehci_alloc(sizeof(struct QH), 32); + if (qh == NULL) { + DBG("unable to allocate QH"); + return (-1); + } + qh->qh_link = swap_32((uint32_t)&qh_list | QH_LINK_TYPE_QH); + c = (usb_pipespeed(pipe) != USB_SPEED_HIGH && + usb_pipeendpoint(pipe) == 0) ? 1 : 0; + endpt = (8 << 28) | + (c << 27) | + (usb_maxpacket(dev, pipe) << 16) | + (0 << 15) | + (1 << 14) | + (usb_pipespeed(pipe) << 12) | + (usb_pipeendpoint(pipe) << 8) | + (0 << 7) | + (usb_pipedevice(pipe) << 0); + qh->qh_endpt1 = swap_32(endpt); + endpt = (1 << 30) | + (dev->portnr << 23) | + (dev->parent->devnum << 16) | + (0 << 8) | + (0 << 0); + qh->qh_endpt2 = swap_32(endpt); + qh->qh_overlay.qt_next = swap_32(QT_NEXT_TERMINATE); + qh->qh_overlay.qt_altnext = swap_32(QT_NEXT_TERMINATE); + + td = NULL; + tdp = &qh->qh_overlay.qt_next; + + toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); + + if (req != NULL) { + td = ehci_alloc(sizeof(struct qTD), 32); + if (td == NULL) { + DBG("unable to allocate SETUP td"); + goto fail; + } + td->qt_next = swap_32(QT_NEXT_TERMINATE); + td->qt_altnext = swap_32(QT_NEXT_TERMINATE); + token = (0 << 31) | + (sizeof(*req) << 16) | + (0 << 15) | + (0 << 12) | + (3 << 10) | + (2 << 8) | + (0x80 << 0); + td->qt_token = swap_32(token); + if (ehci_td_buffer(td, req, sizeof(*req)) != 0) { + DBG("unable construct SETUP td"); + ehci_free(td, sizeof(*td)); + goto fail; + } + *tdp = swap_32((uint32_t)td); + tdp = &td->qt_next; + toggle = 1; + } + + if (length > 0 || req == NULL) { + td = ehci_alloc(sizeof(struct qTD), 32); + if (td == NULL) { + DBG("unable to allocate DATA td"); + goto fail; + } + td->qt_next = swap_32(QT_NEXT_TERMINATE); + td->qt_altnext = swap_32(QT_NEXT_TERMINATE); + token = (toggle << 31) | + (length << 16) | + ((req == NULL ? 1 : 0) << 15) | + (0 << 12) | + (3 << 10) | + ((usb_pipein(pipe) ? 1 : 0) << 8) | + (0x80 << 0); + td->qt_token = swap_32(token); + if (ehci_td_buffer(td, buffer, length) != 0) { + DBG("unable construct DATA td"); + ehci_free(td, sizeof(*td)); + goto fail; + } + *tdp = swap_32((uint32_t)td); + tdp = &td->qt_next; + } + + if (req != NULL) { + td = ehci_alloc(sizeof(struct qTD), 32); + if (td == NULL) { + DBG("unable to allocate ACK td"); + goto fail; + } + td->qt_next = swap_32(QT_NEXT_TERMINATE); + td->qt_altnext = swap_32(QT_NEXT_TERMINATE); + token = (toggle << 31) | + (0 << 16) | + (1 << 15) | + (0 << 12) | + (3 << 10) | + ((usb_pipein(pipe) ? 0 : 1) << 8) | + (0x80 << 0); + td->qt_token = swap_32(token); + *tdp = swap_32((uint32_t)td); + tdp = &td->qt_next; + } + + qh_list.qh_link = swap_32((uint32_t)qh | QH_LINK_TYPE_QH); + + usbsts = swap_32(hcor->or_usbsts); + hcor->or_usbsts = swap_32(usbsts & 0x3f); + + /* Enable async. schedule. */ + hcor->or_usbcmd |= swap_32(0x20); + while ((hcor->or_usbsts & swap_32(0x8000)) == 0) + udelay(1); + + /* Wait for TDs to be processed. */ + ts = get_timer(0); + vtd = td; + do { + token = swap_32(vtd->qt_token); + if (!(token & 0x80)) + break; + } while (get_timer(ts) < CFG_HZ); + + /* Disable async schedule. */ + hcor->or_usbcmd &= ~swap_32(0x20); + while ((hcor->or_usbsts & swap_32(0x8000)) != 0) + udelay(1); + + qh_list.qh_link = swap_32((uint32_t)&qh_list | QH_LINK_TYPE_QH); + + token = swap_32(qh->qh_overlay.qt_token); + /*printf("TOKEN=%#x\n", token);*/ + if (!(token & 0x80)) { + switch (token & 0xfc) { + case 0: + toggle = token >> 31; + usb_settoggle(dev, usb_pipeendpoint(pipe), + usb_pipeout(pipe), toggle); + dev->status = 0; + break; + case 0x40: + dev->status = USB_ST_STALLED; + break; + case 0xa0: + case 0x20: + dev->status = USB_ST_BUF_ERR; + break; + case 0x50: + case 0x10: + dev->status = USB_ST_BABBLE_DET; + break; + default: + dev->status = USB_ST_CRC_ERR; + break; + } + dev->act_len = length - ((token >> 16) & 0x7fff); + } else { + printf("T "); + dev->act_len = 0; + DBG("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x", + dev->devnum, swap_32(hcor->or_usbsts), + swap_32(hcor->or_portsc[0]), swap_32(hcor->or_portsc[1])); + } + + return ((dev->status != USB_ST_NOT_PROC) ? 0 : -1); + + fail: + td = (void *)swap_32(qh->qh_overlay.qt_next); + while (td != (void *)QT_NEXT_TERMINATE) { + qh->qh_overlay.qt_next = td->qt_next; + ehci_free(td, sizeof(*td)); + td = (void *)swap_32(qh->qh_overlay.qt_next); + } + ehci_free(qh, sizeof(*qh)); + return (-1); +} + +static int +ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, + int length, struct devrequest *req) +{ + uint8_t tmpbuf[4]; + void *srcptr; + int len, srclen; + uint32_t reg; + + srclen = 0; + srcptr = NULL; + + DBG("req=%u (%#x), type=%u (%#x), value=%u, index=%u", + req->request, req->request, + req->requesttype, req->requesttype, + swap_16(req->value), swap_16(req->index)); + +#define C(a,b) (((b) << 8) | (a)) + + switch (C(req->request, req->requesttype)) { + case C(USB_REQ_GET_DESCRIPTOR, USB_DIR_IN | USB_RECIP_DEVICE): + switch(swap_16(req->value) >> 8) { + case USB_DT_DEVICE: + srcptr = descr.device; + srclen = sizeof(descr.device); + break; + case USB_DT_CONFIG: + srcptr = descr.config; + srclen = sizeof(descr.config) + + sizeof(descr.interface) + sizeof(descr.endpoint); + break; + case USB_DT_STRING: + switch (swap_16(req->value) & 0xff) { + case 0: /* Language */ + srcptr = "\4\3\1\0"; + srclen = 4; + break; + case 1: /* Vendor */ + srcptr = "\20\3M\0a\0r\0v\0e\0l\0l\0"; + srclen = 16; + break; + case 2: /* Product */ + srcptr = "\12\3E\0H\0C\0I\0"; + srclen = 10; + break; + default: + goto unknown; + } + break; + default: + DBG("+unknown value %x", swap_16(req->value)); + goto unknown; + } + break; + case C(USB_REQ_GET_DESCRIPTOR, USB_DIR_IN | USB_RT_HUB): + switch (swap_16(req->value) >> 8) { + case USB_DT_HUB: + srcptr = descr.hub; + srclen = sizeof(descr.hub); + break; + default: + DBG("-unknown value %x", swap_16(req->value)); + goto unknown; + } + break; + case C(USB_REQ_SET_ADDRESS, USB_RECIP_DEVICE): + rootdev = swap_16(req->value); + break; + case C(USB_REQ_SET_CONFIGURATION, USB_RECIP_DEVICE): + /* Nothing to do */ + break; + case C(USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_HUB): + tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ + tmpbuf[1] = 0; + srcptr = tmpbuf; + srclen = 2; + break; + case C(USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_PORT): + memset(tmpbuf, 0, 4); + reg = swap_32(hcor->or_portsc[swap_16(req->index) - 1]); + if (reg & EHCI_PS_CS) + tmpbuf[0] |= USB_PORT_STAT_CONNECTION; + if (reg & EHCI_PS_PE) + tmpbuf[0] |= USB_PORT_STAT_ENABLE; + if (reg & EHCI_PS_SUSP) + tmpbuf[0] |= USB_PORT_STAT_SUSPEND; + if (reg & EHCI_PS_OCA) + tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; + if (reg & EHCI_PS_PR) + tmpbuf[0] |= USB_PORT_STAT_RESET; + if (reg & EHCI_PS_PP) + tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; + if (reg & EHCI_PS_PSPD == 0x08000000) + tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED;// >> 8; + else if (reg & EHCI_PS_PSPD == 0x04000000 || reg & EHCI_PS_PSPD == 0x00000000) + tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED;// >> 8; + + if (reg & EHCI_PS_CSC) + tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; + if (reg & EHCI_PS_PEC) + tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; + if (reg & EHCI_PS_OCC) + tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; + if (portreset & (1 << swap_16(req->index))) + tmpbuf[2] |= USB_PORT_STAT_C_RESET; + srcptr = tmpbuf; + srclen = 4; + break; + case C(USB_REQ_SET_FEATURE, USB_DIR_OUT | USB_RT_PORT): + reg = swap_32(hcor->or_portsc[swap_16(req->index) - 1]); + reg |= EHCI_PS_CLEAR; + switch (swap_16(req->value)) { + case USB_PORT_FEAT_POWER: + reg |= EHCI_PS_PP; + break; + case USB_PORT_FEAT_RESET: + if (EHCI_PS_IS_LOWSPEED(reg)) { + /* Low speed device, give up ownership. */ + reg |= EHCI_PS_PO; + break; + } + /* Start reset sequence. */ + reg &= ~EHCI_PS_PE; + reg |= EHCI_PS_PR; + hcor->or_portsc[swap_16(req->index) - 1] = swap_32(reg); + /* Wait for reset to complete. */ + udelay(250000); + /* Terminate reset sequence. */ + /* reg &= ~EHCI_PS_PR; + hcor->or_portsc[swap_16(req->index) - 1] = swap_32(reg);*/ + /* Wait for HC to complete reset. */ + udelay(2000); + + reg = swap_32(hcor->or_portsc[swap_16(req->index) - 1]); + reg |= EHCI_PS_CLEAR; + //reg &= ~EHCI_PS_CLEAR; + if ((reg & EHCI_PS_PE) == 0) { + /* Not a high speed device, give up ownership.*/ + reg |= EHCI_PS_PO; + break; + } + portreset |= 1 << swap_16(req->index); + break; + default: + DBG("unknown feature %x", swap_16(req->value)); + goto unknown; + } + hcor->or_portsc[swap_16(req->index) - 1] = swap_32(reg); + break; + case C(USB_REQ_CLEAR_FEATURE, USB_DIR_OUT | USB_RT_PORT): + reg = swap_32(hcor->or_portsc[swap_16(req->index) - 1]); + reg &= ~EHCI_PS_CLEAR; + switch (swap_16(req->value)) { + case USB_PORT_FEAT_ENABLE: + reg &= ~EHCI_PS_PE; + break; + case USB_PORT_FEAT_C_CONNECTION: + reg |= EHCI_PS_CSC; + break; + case USB_PORT_FEAT_C_RESET: + portreset &= ~(1 << swap_16(req->index)); + break; + default: + DBG("unknown feature %x", swap_16(req->value)); + goto unknown; + } + hcor->or_portsc[swap_16(req->index) - 1] = swap_32(reg); + break; + default: + DBG("Unknown request %x", C(req->request, req->requesttype)); + goto unknown; + } + +#undef C + + len = min3(srclen, swap_16(req->length), length); + if (srcptr != NULL && len > 0) + memcpy(buffer, srcptr, len); + dev->act_len = len; + dev->status = 0; + return (0); + + unknown: + DBG("requesttype=%x, request=%x, value=%x, index=%x, length=%x", + req->requesttype, req->request, swap_16(req->value), + swap_16(req->index), swap_16(req->length)); + + dev->act_len = 0; + dev->status = USB_ST_STALLED; + return (-1); +} + +int +submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int length) +{ + + if (usb_pipetype(pipe) != PIPE_BULK) { + DBG("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); + return (-1); + } + return (ehci_submit_async(dev, pipe, buffer, length, NULL)); +} + +int +submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int length, struct devrequest *setup) +{ + + if (usb_pipetype(pipe) != PIPE_CONTROL) { + DBG("non-control pipe (type=%lu)", usb_pipetype(pipe)); + return (-1); + } + + if (usb_pipedevice(pipe) == rootdev) { + if (rootdev == 0) + { + dev->speed = (0x0c000000 & (*(volatile unsigned int *)(0xf1050184))) >> 26/*USB_SPEED_HIGH*/; + } + return (ehci_submit_root(dev, pipe, buffer, length, setup)); + } + return (ehci_submit_async(dev, pipe, buffer, length, setup)); +} + +int +submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int length, int interval) +{ + + DBG("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", dev, pipe, + buffer, length, interval); + return (-1); +} + diff --git a/drivers/usb/usb_ehci.h b/drivers/usb/usb_ehci.h new file mode 100644 index 0000000..b050090 --- /dev/null +++ b/drivers/usb/usb_ehci.h @@ -0,0 +1,118 @@ +/*- + * Copyright (c) 2007-2008, Juniper Networks, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI Configuration Space. + */ +#define EHCI_PCICS_BASEC PCI_CLASS_CODE +#define EHCI_PCICS_SCC PCI_CLASS_SUB_CODE +#define EHCI_PCICS_PI PCI_CLASS_PROG +#define EHCI_PCICS_USBBASE PCI_BASE_ADDRESS_0 +#define EHCI_PCICS_SBRN 0x60 +#define EHCI_PCICS_FLADJ 0x61 +#define EHCI_PCICS_PORTWAKECAP 0x62 + +#define EHCI_PCICS_USBLEGSUP +#define EHCI_PCICS_USBLEGCTLSTS + +#define EHCI_PCI_BASEC 0x0c /* Serial Bus Controller. */ +#define EHCI_PCI_SCC 0x03 /* USB Host Controller. */ +#define EHCI_PCI_PI 0x20 /* USB 2.0 Host Controller. */ + +/* + * Register Space. + */ +struct ehci_hccr { + uint8_t cr_caplength; + uint16_t cr_hciversion; + uint32_t cr_hcsparams; + uint32_t cr_hccparams; + uint8_t cr_hcsp_portrt[8]; +}; + +struct ehci_hcor { + uint32_t or_usbcmd; + uint32_t or_usbsts; + uint32_t or_usbintr; + uint32_t or_frindex; + uint32_t or_ctrldssegment; + uint32_t or_periodiclistbase; + uint32_t or_asynclistaddr; + uint32_t _reserved_[9]; + uint32_t or_configflag; + uint32_t or_portsc[2]; + uint32_t _reserved1_[7]; + uint32_t or_usbmode; +}; + +#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current */ +#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect */ +#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect */ +#define EHCI_PS_PTC 0x000f0000 /* RW port test control */ +#define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */ +#define EHCI_PS_PO 0x00002000 /* RW port owner */ +#define EHCI_PS_PP 0x00001000 /* RW,RO port power */ +#define EHCI_PS_LS 0x00000c00 /* RO line status */ +#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400) +#define EHCI_PS_PR 0x00000100 /* RW port reset */ +#define EHCI_PS_SUSP 0x00000080 /* RW suspend */ +#define EHCI_PS_FPR 0x00000040 /* RW force port resume */ +#define EHCI_PS_OCC 0x00000020 /* RWC over current change */ +#define EHCI_PS_OCA 0x00000010 /* RO over current active */ +#define EHCI_PS_PEC 0x00000008 /* RWC port enable change */ +#define EHCI_PS_PE 0x00000004 /* RW port enable */ +#define EHCI_PS_CSC 0x00000002 /* RWC connect status change */ +#define EHCI_PS_CS 0x00000001 /* RO connect status */ +#define EHCI_PS_CLEAR (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC) +#define EHCI_PS_PSPD 0x0c000000 /* RW,RO port power */ + +/* + * Schedule Interface Space. + * + * IMPORTANT: Software must ensure that no interface data structure + * reachable by the EHCI host controller spans a 4K page boundary! + * + * Periodic transfers (i.e. isochronous and interrupt transfers) are + * not supported. + */ + +/* Queue Element Transfer Descriptor (qTD). */ +struct qTD { + uint32_t qt_next; +#define QT_NEXT_TERMINATE 1 + uint32_t qt_altnext; + uint32_t qt_token; + uint32_t qt_buffer[5]; +}; + +/* Queue Head (QH). */ +struct QH { + uint32_t qh_link; +#define QH_LINK_TERMINATE 1 +#define QH_LINK_TYPE_ITD 0 +#define QH_LINK_TYPE_QH 2 +#define QH_LINK_TYPE_SITD 4 +#define QH_LINK_TYPE_FSTN 6 + uint32_t qh_endpt1; + uint32_t qh_endpt2; + uint32_t qh_curtd; + struct qTD qh_overlay; +}; + diff --git a/drivers/usb/usbdcore.c b/drivers/usb/usbdcore.c new file mode 100644 index 0000000..53ed669 --- /dev/null +++ b/drivers/usb/usbdcore.c @@ -0,0 +1,683 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usbd/usbd.c.c - USB Device Core Layer + * + * Copyright (c) 2000, 2001, 2002 Lineo + * Copyright (c) 2001 Hewlett Packard + * + * By: + * Stuart Lynne , + * Tom Rushworth , + * Bruce Balden + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include "usbdcore.h" + +#define MAX_INTERFACES 2 + + +int maxstrings = 20; + +/* Global variables ************************************************************************** */ + +struct usb_string_descriptor **usb_strings; + +int usb_devices; + +extern struct usb_function_driver ep0_driver; + +int registered_functions; +int registered_devices; + +char *usbd_device_events[] = { + "DEVICE_UNKNOWN", + "DEVICE_INIT", + "DEVICE_CREATE", + "DEVICE_HUB_CONFIGURED", + "DEVICE_RESET", + "DEVICE_ADDRESS_ASSIGNED", + "DEVICE_CONFIGURED", + "DEVICE_SET_INTERFACE", + "DEVICE_SET_FEATURE", + "DEVICE_CLEAR_FEATURE", + "DEVICE_DE_CONFIGURED", + "DEVICE_BUS_INACTIVE", + "DEVICE_BUS_ACTIVITY", + "DEVICE_POWER_INTERRUPTION", + "DEVICE_HUB_RESET", + "DEVICE_DESTROY", + "DEVICE_FUNCTION_PRIVATE", +}; + +char *usbd_device_states[] = { + "STATE_INIT", + "STATE_CREATED", + "STATE_ATTACHED", + "STATE_POWERED", + "STATE_DEFAULT", + "STATE_ADDRESSED", + "STATE_CONFIGURED", + "STATE_UNKNOWN", +}; + +char *usbd_device_requests[] = { + "GET STATUS", /* 0 */ + "CLEAR FEATURE", /* 1 */ + "RESERVED", /* 2 */ + "SET FEATURE", /* 3 */ + "RESERVED", /* 4 */ + "SET ADDRESS", /* 5 */ + "GET DESCRIPTOR", /* 6 */ + "SET DESCRIPTOR", /* 7 */ + "GET CONFIGURATION", /* 8 */ + "SET CONFIGURATION", /* 9 */ + "GET INTERFACE", /* 10 */ + "SET INTERFACE", /* 11 */ + "SYNC FRAME", /* 12 */ +}; + +char *usbd_device_descriptors[] = { + "UNKNOWN", /* 0 */ + "DEVICE", /* 1 */ + "CONFIG", /* 2 */ + "STRING", /* 3 */ + "INTERFACE", /* 4 */ + "ENDPOINT", /* 5 */ + "DEVICE QUALIFIER", /* 6 */ + "OTHER SPEED", /* 7 */ + "INTERFACE POWER", /* 8 */ +}; + +char *usbd_device_status[] = { + "USBD_OPENING", + "USBD_OK", + "USBD_SUSPENDED", + "USBD_CLOSING", +}; + + +/* Descriptor support functions ************************************************************** */ + + +/** + * usbd_get_string - find and return a string descriptor + * @index: string index to return + * + * Find an indexed string and return a pointer to a it. + */ +struct usb_string_descriptor *usbd_get_string (__u8 index) +{ + if (index >= maxstrings) { + return NULL; + } + return usb_strings[index]; +} + + +/* Access to device descriptor functions ***************************************************** */ + + +/* * + * usbd_device_configuration_instance - find a configuration instance for this device + * @device: + * @configuration: index to configuration, 0 - N-1 + * + * Get specifed device configuration. Index should be bConfigurationValue-1. + */ +static struct usb_configuration_instance *usbd_device_configuration_instance (struct usb_device_instance *device, + unsigned int port, unsigned int configuration) +{ + if (configuration >= device->configurations) + return NULL; + + return device->configuration_instance_array + configuration; +} + + +/* * + * usbd_device_interface_instance + * @device: + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * + * Return the specified interface descriptor for the specified device. + */ +struct usb_interface_instance *usbd_device_interface_instance (struct usb_device_instance *device, int port, int configuration, int interface) +{ + struct usb_configuration_instance *configuration_instance; + + if ((configuration_instance = usbd_device_configuration_instance (device, port, configuration)) == NULL) { + return NULL; + } + if (interface >= configuration_instance->interfaces) { + return NULL; + } + return configuration_instance->interface_instance_array + interface; +} + +/* * + * usbd_device_alternate_descriptor_list + * @device: + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: alternate setting + * + * Return the specified alternate descriptor for the specified device. + */ +struct usb_alternate_instance *usbd_device_alternate_instance (struct usb_device_instance *device, int port, int configuration, int interface, int alternate) +{ + struct usb_interface_instance *interface_instance; + + if ((interface_instance = usbd_device_interface_instance (device, port, configuration, interface)) == NULL) { + return NULL; + } + + if (alternate >= interface_instance->alternates) { + return NULL; + } + + return interface_instance->alternates_instance_array + alternate; +} + + +/* * + * usbd_device_device_descriptor + * @device: which device + * @configuration: index to configuration, 0 - N-1 + * @port: which port + * + * Return the specified configuration descriptor for the specified device. + */ +struct usb_device_descriptor *usbd_device_device_descriptor (struct usb_device_instance *device, int port) +{ + return (device->device_descriptor); +} + + +/** + * usbd_device_configuration_descriptor + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * + * Return the specified configuration descriptor for the specified device. + */ +struct usb_configuration_descriptor *usbd_device_configuration_descriptor (struct + usb_device_instance + *device, int port, int configuration) +{ + struct usb_configuration_instance *configuration_instance; + if (!(configuration_instance = usbd_device_configuration_instance (device, port, configuration))) { + return NULL; + } + return (configuration_instance->configuration_descriptor); +} + + +/** + * usbd_device_interface_descriptor + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: alternate setting + * + * Return the specified interface descriptor for the specified device. + */ +struct usb_interface_descriptor *usbd_device_interface_descriptor (struct usb_device_instance + *device, int port, int configuration, int interface, int alternate) +{ + struct usb_interface_instance *interface_instance; + if (!(interface_instance = usbd_device_interface_instance (device, port, configuration, interface))) { + return NULL; + } + if ((alternate < 0) || (alternate >= interface_instance->alternates)) { + return NULL; + } + return (interface_instance->alternates_instance_array[alternate].interface_descriptor); +} + +/** + * usbd_device_endpoint_descriptor_index + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: index setting + * @index: which index + * + * Return the specified endpoint descriptor for the specified device. + */ +struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor_index (struct usb_device_instance + *device, int port, int configuration, int interface, int alternate, int index) +{ + struct usb_alternate_instance *alternate_instance; + + if (!(alternate_instance = usbd_device_alternate_instance (device, port, configuration, interface, alternate))) { + return NULL; + } + if (index >= alternate_instance->endpoints) { + return NULL; + } + return *(alternate_instance->endpoints_descriptor_array + index); +} + + +/** + * usbd_device_endpoint_transfersize + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @index: which index + * + * Return the specified endpoint transfer size; + */ +int usbd_device_endpoint_transfersize (struct usb_device_instance *device, int port, int configuration, int interface, int alternate, int index) +{ + struct usb_alternate_instance *alternate_instance; + + if (!(alternate_instance = usbd_device_alternate_instance (device, port, configuration, interface, alternate))) { + return 0; + } + if (index >= alternate_instance->endpoints) { + return 0; + } + return *(alternate_instance->endpoint_transfersize_array + index); +} + + +/** + * usbd_device_endpoint_descriptor + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: alternate setting + * @endpoint: which endpoint + * + * Return the specified endpoint descriptor for the specified device. + */ +struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor (struct usb_device_instance *device, int port, int configuration, int interface, int alternate, int endpoint) +{ + struct usb_endpoint_descriptor *endpoint_descriptor; + int i; + + for (i = 0; !(endpoint_descriptor = usbd_device_endpoint_descriptor_index (device, port, configuration, interface, alternate, i)); i++) { + if (endpoint_descriptor->bEndpointAddress == endpoint) { + return endpoint_descriptor; + } + } + return NULL; +} + +/** + * usbd_endpoint_halted + * @device: point to struct usb_device_instance + * @endpoint: endpoint to check + * + * Return non-zero if endpoint is halted. + */ +int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint) +{ + return (device->status == USB_STATUS_HALT); +} + + +/** + * usbd_rcv_complete - complete a receive + * @endpoint: + * @len: + * @urb_bad: + * + * Called from rcv interrupt to complete. + */ +void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad) +{ + if (endpoint) { + struct urb *rcv_urb; + + /*usbdbg("len: %d urb: %p\n", len, endpoint->rcv_urb); */ + + /* if we had an urb then update actual_length, dispatch if neccessary */ + if ((rcv_urb = endpoint->rcv_urb)) { + + /*usbdbg("actual: %d buffer: %d\n", */ + /*rcv_urb->actual_length, rcv_urb->buffer_length); */ + + /* check the urb is ok, are we adding data less than the packetsize */ + if (!urb_bad && (len <= endpoint->rcv_packetSize)) { + /*usbdbg("updating actual_length by %d\n",len); */ + + /* increment the received data size */ + rcv_urb->actual_length += len; + + } else { + usberr(" RECV_ERROR actual: %d buffer: %d urb_bad: %d\n", + rcv_urb->actual_length, rcv_urb->buffer_length, urb_bad); + + rcv_urb->actual_length = 0; + rcv_urb->status = RECV_ERROR; + } + } else { + usberr("no rcv_urb!"); + } + } else { + usberr("no endpoint!"); + } + +} + +/** + * usbd_tx_complete - complete a transmit + * @endpoint: + * @resetart: + * + * Called from tx interrupt to complete. + */ +void usbd_tx_complete (struct usb_endpoint_instance *endpoint) +{ + if (endpoint) { + struct urb *tx_urb; + + /* if we have a tx_urb advance or reset, finish if complete */ + if ((tx_urb = endpoint->tx_urb)) { + int sent = endpoint->last; + endpoint->sent += sent; + endpoint->last -= sent; + + if( (endpoint->tx_urb->actual_length - endpoint->sent) <= 0 ) { + tx_urb->actual_length = 0; + endpoint->sent = 0; + endpoint->last = 0; + + /* Remove from active, save for re-use */ + urb_detach(tx_urb); + urb_append(&endpoint->done, tx_urb); + /*usbdbg("done->next %p, tx_urb %p, done %p", */ + /* endpoint->done.next, tx_urb, &endpoint->done); */ + + endpoint->tx_urb = first_urb_detached(&endpoint->tx); + if( endpoint->tx_urb ) { + endpoint->tx_queue--; + usbdbg("got urb from tx list"); + } + if( !endpoint->tx_urb ) { + /*usbdbg("taking urb from done list"); */ + endpoint->tx_urb = first_urb_detached(&endpoint->done); + } + if( !endpoint->tx_urb ) { + usbdbg("allocating new urb for tx_urb"); + endpoint->tx_urb = usbd_alloc_urb(tx_urb->device, endpoint); + } + } + } + } +} + +/* URB linked list functions ***************************************************** */ + +/* + * Initialize an urb_link to be a single element list. + * If the urb_link is being used as a distinguished list head + * the list is empty when the head is the only link in the list. + */ +void urb_link_init (urb_link * ul) +{ + if (ul) { + ul->prev = ul->next = ul; + } +} + +/* + * Detach an urb_link from a list, and set it + * up as a single element list, so no dangling + * pointers can be followed, and so it can be + * joined to another list if so desired. + */ +void urb_detach (struct urb *urb) +{ + if (urb) { + urb_link *ul = &urb->link; + ul->next->prev = ul->prev; + ul->prev->next = ul->next; + urb_link_init (ul); + } +} + +/* + * Return the first urb_link in a list with a distinguished + * head "hd", or NULL if the list is empty. This will also + * work as a predicate, returning NULL if empty, and non-NULL + * otherwise. + */ +urb_link *first_urb_link (urb_link * hd) +{ + urb_link *nx; + if (NULL != hd && NULL != (nx = hd->next) && nx != hd) { + /* There is at least one element in the list */ + /* (besides the distinguished head). */ + return (nx); + } + /* The list is empty */ + return (NULL); +} + +/* + * Return the first urb in a list with a distinguished + * head "hd", or NULL if the list is empty. + */ +struct urb *first_urb (urb_link * hd) +{ + urb_link *nx; + if (NULL == (nx = first_urb_link (hd))) { + /* The list is empty */ + return (NULL); + } + return (p2surround (struct urb, link, nx)); +} + +/* + * Detach and return the first urb in a list with a distinguished + * head "hd", or NULL if the list is empty. + * + */ +struct urb *first_urb_detached (urb_link * hd) +{ + struct urb *urb; + if ((urb = first_urb (hd))) { + urb_detach (urb); + } + return urb; +} + + +/* + * Append an urb_link (or a whole list of + * urb_links) to the tail of another list + * of urb_links. + */ +void urb_append (urb_link * hd, struct urb *urb) +{ + if (hd && urb) { + urb_link *new = &urb->link; + + /* This allows the new urb to be a list of urbs, */ + /* with new pointing at the first, but the link */ + /* must be initialized. */ + /* Order is important here... */ + urb_link *pul = hd->prev; + new->prev->next = hd; + hd->prev = new->prev; + new->prev = pul; + pul->next = new; + } +} + +/* URB create/destroy functions ***************************************************** */ + +/** + * usbd_alloc_urb - allocate an URB appropriate for specified endpoint + * @device: device instance + * @endpoint: endpoint + * + * Allocate an urb structure. The usb device urb structure is used to + * contain all data associated with a transfer, including a setup packet for + * control transfers. + * + * NOTE: endpoint_address MUST contain a direction flag. + */ +struct urb *usbd_alloc_urb (struct usb_device_instance *device, + struct usb_endpoint_instance *endpoint) +{ + struct urb *urb; + + if (!(urb = (struct urb *) malloc (sizeof (struct urb)))) { + usberr (" F A T A L: malloc(%zu) FAILED!!!!", + sizeof (struct urb)); + return NULL; + } + + /* Fill in known fields */ + memset (urb, 0, sizeof (struct urb)); + urb->endpoint = endpoint; + urb->device = device; + urb->buffer = (u8 *) urb->buffer_data; + urb->buffer_length = sizeof (urb->buffer_data); + + urb_link_init (&urb->link); + + return urb; +} + +/** + * usbd_dealloc_urb - deallocate an URB and associated buffer + * @urb: pointer to an urb structure + * + * Deallocate an urb structure and associated data. + */ +void usbd_dealloc_urb (struct urb *urb) +{ + if (urb) { + free (urb); + } +} + +/* Event signaling functions ***************************************************** */ + +/** + * usbd_device_event - called to respond to various usb events + * @device: pointer to struct device + * @event: event to respond to + * + * Used by a Bus driver to indicate an event. + */ +void usbd_device_event_irq (struct usb_device_instance *device, usb_device_event_t event, int data) +{ + usb_device_state_t state; + + if (!device || !device->bus) { + usberr("(%p,%d) NULL device or device->bus", device, event); + return; + } + + state = device->device_state; + + usbinfo("%s", usbd_device_events[event]); + + switch (event) { + case DEVICE_UNKNOWN: + break; + case DEVICE_INIT: + device->device_state = STATE_INIT; + break; + + case DEVICE_CREATE: + device->device_state = STATE_ATTACHED; + break; + + case DEVICE_HUB_CONFIGURED: + device->device_state = STATE_POWERED; + break; + + case DEVICE_RESET: + device->device_state = STATE_DEFAULT; + device->address = 0; + break; + + case DEVICE_ADDRESS_ASSIGNED: + device->device_state = STATE_ADDRESSED; + break; + + case DEVICE_CONFIGURED: + device->device_state = STATE_CONFIGURED; + break; + + case DEVICE_DE_CONFIGURED: + device->device_state = STATE_ADDRESSED; + break; + + case DEVICE_BUS_INACTIVE: + if (device->status != USBD_CLOSING) { + device->status = USBD_SUSPENDED; + } + break; + case DEVICE_BUS_ACTIVITY: + if (device->status != USBD_CLOSING) { + device->status = USBD_OK; + } + break; + + case DEVICE_SET_INTERFACE: + break; + case DEVICE_SET_FEATURE: + break; + case DEVICE_CLEAR_FEATURE: + break; + + case DEVICE_POWER_INTERRUPTION: + device->device_state = STATE_POWERED; + break; + case DEVICE_HUB_RESET: + device->device_state = STATE_ATTACHED; + break; + case DEVICE_DESTROY: + device->device_state = STATE_UNKNOWN; + break; + + case DEVICE_FUNCTION_PRIVATE: + break; + + default: + usbdbg("event %d - not handled",event); + break; + } + /*usbdbg("%s event: %d oldstate: %d newstate: %d status: %d address: %d", + device->name, event, state, + device->device_state, device->status, device->address); */ + + /* tell the bus interface driver */ + if( device->event ) { + /* usbdbg("calling device->event"); */ + device->event(device, event, data); + } +} diff --git a/drivers/usb/usbdcore_ep0.c b/drivers/usb/usbdcore_ep0.c new file mode 100644 index 0000000..cf3f382 --- /dev/null +++ b/drivers/usb/usbdcore_ep0.c @@ -0,0 +1,601 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * (C) Copyright 2006 + * Bryan O'Donoghue, deckard@CodeHermit.ie + * + * Based on + * linux/drivers/usbd/ep0.c + * + * Copyright (c) 2000, 2001, 2002 Lineo + * Copyright (c) 2001 Hewlett Packard + * + * By: + * Stuart Lynne , + * Tom Rushworth , + * Bruce Balden + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +/* + * This is the builtin ep0 control function. It implements all required functionality + * for responding to control requests (SETUP packets). + * + * XXX + * + * Currently we do not pass any SETUP packets (or other) to the configured + * function driver. This may need to change. + * + * XXX + * + * As alluded to above, a simple callback cdc_recv_setup has been implemented + * in the usb_device data structure to facilicate passing + * Common Device Class packets to a function driver. + * + * XXX + */ + +#include + +#if defined(CONFIG_USB_DEVICE) +#include "usbdcore.h" + +#if 0 +#define dbg_ep0(lvl,fmt,args...) serial_printf("[%s] %s:%d: "fmt"\n",__FILE__,__FUNCTION__,__LINE__,##args) +#else +#define dbg_ep0(lvl,fmt,args...) +#endif + +/* EP0 Configuration Set ********************************************************************* */ + + +/** + * ep0_get_status - fill in URB data with appropriate status + * @device: + * @urb: + * @index: + * @requesttype: + * + */ +static int ep0_get_status (struct usb_device_instance *device, + struct urb *urb, int index, int requesttype) +{ + char *cp; + + urb->actual_length = 2; + cp = (char*)urb->buffer; + cp[0] = cp[1] = 0; + + switch (requesttype) { + case USB_REQ_RECIPIENT_DEVICE: + cp[0] = USB_STATUS_SELFPOWERED; + break; + case USB_REQ_RECIPIENT_INTERFACE: + break; + case USB_REQ_RECIPIENT_ENDPOINT: + cp[0] = usbd_endpoint_halted (device, index); + break; + case USB_REQ_RECIPIENT_OTHER: + urb->actual_length = 0; + default: + break; + } + dbg_ep0 (2, "%02x %02x", cp[0], cp[1]); + return 0; +} + +/** + * ep0_get_one + * @device: + * @urb: + * @result: + * + * Set a single byte value in the urb send buffer. Return non-zero to signal + * a request error. + */ +static int ep0_get_one (struct usb_device_instance *device, struct urb *urb, + __u8 result) +{ + urb->actual_length = 1; /* XXX 2? */ + ((char *) urb->buffer)[0] = result; + return 0; +} + +/** + * copy_config + * @urb: pointer to urb + * @data: pointer to configuration data + * @length: length of data + * + * Copy configuration data to urb transfer buffer if there is room for it. + */ +void copy_config (struct urb *urb, void *data, int max_length, + int max_buf) +{ + int available; + int length; + + /*dbg_ep0(3, "-> actual: %d buf: %d max_buf: %d max_length: %d data: %p", */ + /* urb->actual_length, urb->buffer_length, max_buf, max_length, data); */ + + if (!data) { + dbg_ep0 (1, "data is NULL"); + return; + } + length = max_length; + + if (length > max_length) { + dbg_ep0 (1, "length: %d >= max_length: %d", length, + max_length); + return; + } + /*dbg_ep0(1, " actual: %d buf: %d max_buf: %d max_length: %d length: %d", */ + /* urb->actual_length, urb->buffer_length, max_buf, max_length, length); */ + + if ((available = + /*urb->buffer_length */ max_buf - urb->actual_length) <= 0) { + return; + } + /*dbg_ep0(1, "actual: %d buf: %d max_buf: %d length: %d available: %d", */ + /* urb->actual_length, urb->buffer_length, max_buf, length, available); */ + + if (length > available) { + length = available; + } + /*dbg_ep0(1, "actual: %d buf: %d max_buf: %d length: %d available: %d", */ + /* urb->actual_length, urb->buffer_length, max_buf, length, available); */ + + memcpy (urb->buffer + urb->actual_length, data, length); + urb->actual_length += length; + + dbg_ep0 (3, + "copy_config: <- actual: %d buf: %d max_buf: %d max_length: %d available: %d", + urb->actual_length, urb->buffer_length, max_buf, max_length, + available); +} + +/** + * ep0_get_descriptor + * @device: + * @urb: + * @max: + * @descriptor_type: + * @index: + * + * Called by ep0_rx_process for a get descriptor device command. Determine what + * descriptor is being requested, copy to send buffer. Return zero if ok to send, + * return non-zero to signal a request error. + */ +static int ep0_get_descriptor (struct usb_device_instance *device, + struct urb *urb, int max, int descriptor_type, + int index) +{ + int port = 0; /* XXX compound device */ + char *cp; + + /*dbg_ep0(3, "max: %x type: %x index: %x", max, descriptor_type, index); */ + + if (!urb || !urb->buffer || !urb->buffer_length + || (urb->buffer_length < 255)) { + dbg_ep0 (2, "invalid urb %p", urb); + return -1L; + } + + /* setup tx urb */ + urb->actual_length = 0; + cp = (char*)urb->buffer; + + dbg_ep0 (2, "%s", USBD_DEVICE_DESCRIPTORS (descriptor_type)); + + switch (descriptor_type) { + case USB_DESCRIPTOR_TYPE_DEVICE: + { + struct usb_device_descriptor *device_descriptor; + if (! + (device_descriptor = + usbd_device_device_descriptor (device, port))) { + return -1; + } + /* copy descriptor for this device */ + copy_config (urb, device_descriptor, + sizeof (struct usb_device_descriptor), + max); + + /* correct the correct control endpoint 0 max packet size into the descriptor */ + device_descriptor = + (struct usb_device_descriptor *) urb->buffer; + + } + dbg_ep0(3, "copied device configuration, actual_length: 0x%x", urb->actual_length); + break; + + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + { + struct usb_configuration_descriptor + *configuration_descriptor; + struct usb_device_descriptor *device_descriptor; + if (! + (device_descriptor = + usbd_device_device_descriptor (device, port))) { + return -1; + } + /*dbg_ep0(2, "%d %d", index, device_descriptor->bNumConfigurations); */ + if (index >= device_descriptor->bNumConfigurations) { + dbg_ep0 (0, "index too large: %d >= %d", index, + device_descriptor-> + bNumConfigurations); + return -1; + } + + if (! + (configuration_descriptor = + usbd_device_configuration_descriptor (device, + port, + index))) { + dbg_ep0 (0, + "usbd_device_configuration_descriptor failed: %d", + index); + return -1; + } + dbg_ep0(0, "attempt to copy %d bytes to urb\n",cpu_to_le16(configuration_descriptor->wTotalLength)); + copy_config (urb, configuration_descriptor, + + cpu_to_le16(configuration_descriptor->wTotalLength), + max); + } + + break; + + case USB_DESCRIPTOR_TYPE_STRING: + { + struct usb_string_descriptor *string_descriptor; + if (!(string_descriptor = usbd_get_string (index))) { + serial_printf("Invalid string index %d\n", index); + return -1; + } + dbg_ep0(3, "string_descriptor: %p length %d", string_descriptor, string_descriptor->bLength); + copy_config (urb, string_descriptor, string_descriptor->bLength, max); + } + break; + case USB_DESCRIPTOR_TYPE_INTERFACE: + serial_printf("USB_DESCRIPTOR_TYPE_INTERFACE - error not implemented\n"); + return -1; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + serial_printf("USB_DESCRIPTOR_TYPE_ENDPOINT - error not implemented\n"); + return -1; + case USB_DESCRIPTOR_TYPE_HID: + { + serial_printf("USB_DESCRIPTOR_TYPE_HID - error not implemented\n"); + return -1; /* unsupported at this time */ +#if 0 + int bNumInterface = + le16_to_cpu (urb->device_request.wIndex); + int bAlternateSetting = 0; + int class = 0; + struct usb_class_descriptor *class_descriptor; + + if (!(class_descriptor = + usbd_device_class_descriptor_index (device, + port, 0, + bNumInterface, + bAlternateSetting, + class)) + || class_descriptor->descriptor.hid.bDescriptorType != USB_DT_HID) { + dbg_ep0 (3, "[%d] interface is not HID", + bNumInterface); + return -1; + } + /* copy descriptor for this class */ + copy_config (urb, class_descriptor, + class_descriptor->descriptor.hid.bLength, + max); +#endif + } + break; + case USB_DESCRIPTOR_TYPE_REPORT: + { + serial_printf("USB_DESCRIPTOR_TYPE_REPORT - error not implemented\n"); + return -1; /* unsupported at this time */ +#if 0 + int bNumInterface = + le16_to_cpu (urb->device_request.wIndex); + int bAlternateSetting = 0; + int class = 0; + struct usb_class_report_descriptor *report_descriptor; + + if (!(report_descriptor = + usbd_device_class_report_descriptor_index + (device, port, 0, bNumInterface, + bAlternateSetting, class)) + || report_descriptor->bDescriptorType != + USB_DT_REPORT) { + dbg_ep0 (3, "[%d] descriptor is not REPORT", + bNumInterface); + return -1; + } + /* copy report descriptor for this class */ + /*copy_config(urb, &report_descriptor->bData[0], report_descriptor->wLength, max); */ + if (max - urb->actual_length > 0) { + int length = + MIN (report_descriptor->wLength, + max - urb->actual_length); + memcpy (urb->buffer + urb->actual_length, + &report_descriptor->bData[0], length); + urb->actual_length += length; + } +#endif + } + break; + case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER: + { + /* If a USB device supports both a full speed and low speed operation + * we must send a Device_Qualifier descriptor here + */ + return -1; + } + default: + return -1; + } + + + dbg_ep0 (1, "urb: buffer: %p buffer_length: %2d actual_length: %2d tx_packetSize: %2d", + urb->buffer, urb->buffer_length, urb->actual_length, + device->bus->endpoint_array[0].tx_packetSize); +/* + if ((urb->actual_length < max) && !(urb->actual_length % device->bus->endpoint_array[0].tx_packetSize)) { + dbg_ep0(0, "adding null byte"); + urb->buffer[urb->actual_length++] = 0; + dbg_ep0(0, "urb: buffer_length: %2d actual_length: %2d packet size: %2d", + urb->buffer_length, urb->actual_length device->bus->endpoint_array[0].tx_packetSize); + } +*/ + return 0; + +} + +/** + * ep0_recv_setup - called to indicate URB has been received + * @urb: pointer to struct urb + * + * Check if this is a setup packet, process the device request, put results + * back into the urb and return zero or non-zero to indicate success (DATA) + * or failure (STALL). + * + */ +int ep0_recv_setup (struct urb *urb) +{ + /*struct usb_device_request *request = urb->buffer; */ + /*struct usb_device_instance *device = urb->device; */ + + struct usb_device_request *request; + struct usb_device_instance *device; + int address; + + dbg_ep0 (0, "entering ep0_recv_setup()"); + if (!urb || !urb->device) { + dbg_ep0 (3, "invalid URB %p", urb); + return -1; + } + + request = &urb->device_request; + device = urb->device; + + dbg_ep0 (3, "urb: %p device: %p", urb, urb->device); + + + /*dbg_ep0(2, "- - - - - - - - - -"); */ + + dbg_ep0 (2, + "bmRequestType:%02x bRequest:%02x wValue:%04x wIndex:%04x wLength:%04x %s", + request->bmRequestType, request->bRequest, + le16_to_cpu (request->wValue), le16_to_cpu (request->wIndex), + le16_to_cpu (request->wLength), + USBD_DEVICE_REQUESTS (request->bRequest)); + + /* handle USB Standard Request (c.f. USB Spec table 9-2) */ + if ((request->bmRequestType & USB_REQ_TYPE_MASK) != 0) { + if(device->device_state <= STATE_CONFIGURED){ + /* Attempt to handle a CDC specific request if we are + * in the configured state. + */ + return device->cdc_recv_setup(request,urb); + } + dbg_ep0 (1, "non standard request: %x", + request->bmRequestType & USB_REQ_TYPE_MASK); + return -1; /* Stall here */ + } + + switch (device->device_state) { + case STATE_CREATED: + case STATE_ATTACHED: + case STATE_POWERED: + /* It actually is important to allow requests in these states, + * Windows will request descriptors before assigning an + * address to the client. + */ + + /*dbg_ep0 (1, "request %s not allowed in this state: %s", */ + /* USBD_DEVICE_REQUESTS(request->bRequest), */ + /* usbd_device_states[device->device_state]); */ + /*return -1; */ + break; + + case STATE_INIT: + case STATE_DEFAULT: + switch (request->bRequest) { + case USB_REQ_GET_STATUS: + case USB_REQ_GET_INTERFACE: + case USB_REQ_SYNCH_FRAME: /* XXX should never see this (?) */ + case USB_REQ_CLEAR_FEATURE: + case USB_REQ_SET_FEATURE: + case USB_REQ_SET_DESCRIPTOR: + /* case USB_REQ_SET_CONFIGURATION: */ + case USB_REQ_SET_INTERFACE: + dbg_ep0 (1, + "request %s not allowed in DEFAULT state: %s", + USBD_DEVICE_REQUESTS (request->bRequest), + usbd_device_states[device->device_state]); + return -1; + + case USB_REQ_SET_CONFIGURATION: + case USB_REQ_SET_ADDRESS: + case USB_REQ_GET_DESCRIPTOR: + case USB_REQ_GET_CONFIGURATION: + break; + } + case STATE_ADDRESSED: + case STATE_CONFIGURED: + break; + case STATE_UNKNOWN: + dbg_ep0 (1, "request %s not allowed in UNKNOWN state: %s", + USBD_DEVICE_REQUESTS (request->bRequest), + usbd_device_states[device->device_state]); + return -1; + } + + /* handle all requests that return data (direction bit set on bm RequestType) */ + if ((request->bmRequestType & USB_REQ_DIRECTION_MASK)) { + + dbg_ep0 (3, "Device-to-Host"); + + switch (request->bRequest) { + + case USB_REQ_GET_STATUS: + return ep0_get_status (device, urb, request->wIndex, + request->bmRequestType & + USB_REQ_RECIPIENT_MASK); + + case USB_REQ_GET_DESCRIPTOR: + return ep0_get_descriptor (device, urb, + le16_to_cpu (request->wLength), + le16_to_cpu (request->wValue) >> 8, + le16_to_cpu (request->wValue) & 0xff); + + case USB_REQ_GET_CONFIGURATION: + serial_printf("get config %d\n", device->configuration); + return ep0_get_one (device, urb, + device->configuration); + + case USB_REQ_GET_INTERFACE: + return ep0_get_one (device, urb, device->alternate); + + case USB_REQ_SYNCH_FRAME: /* XXX should never see this (?) */ + return -1; + + case USB_REQ_CLEAR_FEATURE: + case USB_REQ_SET_FEATURE: + case USB_REQ_SET_ADDRESS: + case USB_REQ_SET_DESCRIPTOR: + case USB_REQ_SET_CONFIGURATION: + case USB_REQ_SET_INTERFACE: + return -1; + } + } + /* handle the requests that do not return data */ + else { + + + /*dbg_ep0(3, "Host-to-Device"); */ + switch (request->bRequest) { + + case USB_REQ_CLEAR_FEATURE: + case USB_REQ_SET_FEATURE: + dbg_ep0 (0, "Host-to-Device"); + switch (request-> + bmRequestType & USB_REQ_RECIPIENT_MASK) { + case USB_REQ_RECIPIENT_DEVICE: + /* XXX DEVICE_REMOTE_WAKEUP or TEST_MODE would be added here */ + /* XXX fall through for now as we do not support either */ + case USB_REQ_RECIPIENT_INTERFACE: + case USB_REQ_RECIPIENT_OTHER: + dbg_ep0 (0, "request %s not", + USBD_DEVICE_REQUESTS (request->bRequest)); + default: + return -1; + + case USB_REQ_RECIPIENT_ENDPOINT: + dbg_ep0 (0, "ENDPOINT: %x", le16_to_cpu (request->wValue)); + if (le16_to_cpu (request->wValue) == USB_ENDPOINT_HALT) { + /*return usbd_device_feature (device, le16_to_cpu (request->wIndex), */ + /* request->bRequest == USB_REQ_SET_FEATURE); */ + /* NEED TO IMPLEMENT THIS!!! */ + return -1; + } else { + dbg_ep0 (1, "request %s bad wValue: %04x", + USBD_DEVICE_REQUESTS + (request->bRequest), + le16_to_cpu (request->wValue)); + return -1; + } + } + + case USB_REQ_SET_ADDRESS: + /* check if this is a re-address, reset first if it is (this shouldn't be possible) */ + if (device->device_state != STATE_DEFAULT) { + dbg_ep0 (1, "set_address: %02x state: %s", + le16_to_cpu (request->wValue), + usbd_device_states[device->device_state]); + return -1; + } + address = le16_to_cpu (request->wValue); + if ((address & 0x7f) != address) { + dbg_ep0 (1, "invalid address %04x %04x", + address, address & 0x7f); + return -1; + } + device->address = address; + + /*dbg_ep0(2, "address: %d %d %d", */ + /* request->wValue, le16_to_cpu(request->wValue), device->address); */ + + return 0; + + case USB_REQ_SET_DESCRIPTOR: /* XXX should we support this? */ + dbg_ep0 (0, "set descriptor: NOT SUPPORTED"); + return -1; + + case USB_REQ_SET_CONFIGURATION: + /* c.f. 9.4.7 - the top half of wValue is reserved */ + device->configuration = le16_to_cpu(request->wValue) & 0xff; + + /* reset interface and alternate settings */ + device->interface = device->alternate = 0; + + /*dbg_ep0(2, "set configuration: %d", device->configuration); */ + /*serial_printf("DEVICE_CONFIGURED.. event?\n"); */ + return 0; + + case USB_REQ_SET_INTERFACE: + device->interface = le16_to_cpu (request->wIndex); + device->alternate = le16_to_cpu (request->wValue); + /*dbg_ep0(2, "set interface: %d alternate: %d", device->interface, device->alternate); */ + serial_printf ("DEVICE_SET_INTERFACE.. event?\n"); + return 0; + + case USB_REQ_GET_STATUS: + case USB_REQ_GET_DESCRIPTOR: + case USB_REQ_GET_CONFIGURATION: + case USB_REQ_GET_INTERFACE: + case USB_REQ_SYNCH_FRAME: /* XXX should never see this (?) */ + return -1; + } + } + return -1; +} + +#endif diff --git a/dtt/.depend b/dtt/.depend new file mode 100644 index 0000000..54f7d76 --- /dev/null +++ b/dtt/.depend @@ -0,0 +1,84 @@ +lm75.o: lm75.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +ds1621.o: ds1621.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +adm1021.o: adm1021.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h diff --git a/examples/Makefile b/examples/Makefile index 2f8c4c4..c441c20 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -30,7 +30,8 @@ LOAD_ADDR = 0x40000 endif ifeq ($(ARCH),arm) -LOAD_ADDR = 0xc100000 +#LOAD_ADDR = 0xc100000 +LOAD_ADDR = 0x100000 endif ifeq ($(ARCH),mips) @@ -54,6 +55,7 @@ LOAD_ADDR = 0x80F00000 endif include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk SREC = hello_world.srec BIN = hello_world.bin hello_world @@ -97,6 +99,8 @@ endif OBJS = $(SREC:.srec=.o) +STAM = $(SREC:.srec=) + LIB = libstubs.a LIBAOBJS= ifeq ($(ARCH),ppc) @@ -113,25 +117,30 @@ clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) CPPFLAGS += -I.. -all: .depend $(OBJS) $(LIB) $(SREC) $(BIN) +all: .depend $(OBJS) $(LIB) $(BIN) $(SREC) ######################################################################### $(LIB): .depend $(LIBOBJS) + echo "lib.." $(AR) crv $@ $(LIBOBJS) -%: %.o $(LIB) +hello_world: hello_world.o $(LIB) + echo "ld..." $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ -o $@ -e $(<:.o=) $< $(LIB) \ -L$(gcclibdir) -lgcc %.srec: % + echo "srec..." $(OBJCOPY) -O srec $< $@ 2>/dev/null -%.bin: % +%.bin: hello_world + echo "bin..." $(OBJCOPY) -O binary $< $@ 2>/dev/null ######################################################################### .depend: Makefile $(OBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) + echo "CC.." $(CC) -M $(CFLAGS) $(OBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) > $@ sinclude .depend diff --git a/examples/stubs.c b/examples/stubs.c index d4c6e06..61fae0b 100644 --- a/examples/stubs.c +++ b/examples/stubs.c @@ -139,16 +139,16 @@ gd_t *global_data; #if GCC_VERSION < 3004 static #endif /* GCC_VERSION */ -void __attribute__((unused)) dummy(void) +void __attribute__((used)) dummy(void) { #include <_exports.h> } +#if 1 extern unsigned long __bss_start, _end; - void app_startup(char **argv) { - unsigned long * cp = &__bss_start; + unsigned char * cp = &__bss_start; /* Zero out BSS */ while (cp < &_end) { @@ -161,5 +161,23 @@ void app_startup(char **argv) jt = global_data->jt; #endif } +#else +extern unsigned long _bss_start, _bss_end; +void app_startup(char **argv) +{ + unsigned long * cp = &_bss_start; + + /* Zero out BSS */ + while (cp < &_bss_end) { + *cp++ = 0; + } + +#if defined(CONFIG_I386) + /* x86 does not have a dedicated register for passing global_data */ + global_data = (gd_t *)argv[-1]; + jt = global_data->jt; +#endif +} +#endif #undef EXPORT_FUNC diff --git a/fs/cramfs/.depend b/fs/cramfs/.depend new file mode 100644 index 0000000..59c278a --- /dev/null +++ b/fs/cramfs/.depend @@ -0,0 +1,69 @@ +cramfs.o: cramfs.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/byteorder.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/little_endian.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/swab.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/generic.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stat.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/jffs2.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/load_kernel.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/list.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cramfs/cramfs_fs.h +uncompress.o: uncompress.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/watchdog.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/zlib.h diff --git a/fs/ext2/.depend b/fs/ext2/.depend new file mode 100644 index 0000000..dcf529f --- /dev/null +++ b/fs/ext2/.depend @@ -0,0 +1,63 @@ +ext2fs.o: ext2fs.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ext2fs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/byteorder.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/little_endian.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/swab.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/generic.h +dev.o: dev.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ext2fs.h diff --git a/fs/ext2/dev.c b/fs/ext2/dev.c index 1469e98..d725ad7 100644 --- a/fs/ext2/dev.c +++ b/fs/ext2/dev.c @@ -52,10 +52,14 @@ int ext2fs_set_blk_dev (block_dev_desc_t * rbdd, int part) } -int ext2fs_devread (int sector, int byte_offset, int byte_len, char *buf) { - char sec_buf[SECTOR_SIZE]; +int ext2fs_devread (int sector, int filesystem_block_log2, int byte_offset, int byte_len, char *buf) { + short sec_buffer[SECTOR_SIZE/sizeof(short)]; + char *sec_buf = sec_buffer; unsigned block_len; + sector = sector << filesystem_block_log2; + + /* * Check partition boundaries */ @@ -96,8 +100,23 @@ int ext2fs_devread (int sector, int byte_offset, int byte_len, char *buf) { sector++; } + if (byte_len == 0) + return 1; + /* read sector aligned part */ block_len = byte_len & ~(SECTOR_SIZE - 1); + + if (block_len == 0) { + u8 p[SECTOR_SIZE]; + + block_len = SECTOR_SIZE; + ext2fs_block_dev_desc->block_read(ext2fs_block_dev_desc->dev, + part_info.start + sector, + 1, (unsigned long *)p); + memcpy(buf, p, byte_len); + return 1; + } + if (ext2fs_block_dev_desc->block_read (ext2fs_block_dev_desc->dev, part_info.start + sector, block_len / SECTOR_SIZE, @@ -106,6 +125,7 @@ int ext2fs_devread (int sector, int byte_offset, int byte_len, char *buf) { printf (" ** ext2fs_devread() read error - block\n"); return (0); } + block_len = byte_len & ~(SECTOR_SIZE - 1); buf += block_len; byte_len -= block_len; sector += block_len / SECTOR_SIZE; diff --git a/fs/ext2/ext2fs.c b/fs/ext2/ext2fs.c index c21d2d6..ff2132a 100644 --- a/fs/ext2/ext2fs.c +++ b/fs/ext2/ext2fs.c @@ -29,8 +29,9 @@ #include #include #include +#define CFG_EXT2_SUPPORT_DYNAMIC_REV -extern int ext2fs_devread (int sector, int byte_offset, int byte_len, +extern int ext2fs_devread (int sector, int log2blksize, int byte_offset, int byte_len, char *buf); /* Magic value used to identify an ext2 filesystem. */ @@ -66,6 +67,17 @@ extern int ext2fs_devread (int sector, int byte_offset, int byte_len, /* The size of an ext2 block in bytes. */ #define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data)) +#ifdef CFG_EXT2_SUPPORT_DYNAMIC_REV +/* + * Revision levels + */ +#define EXT2_GOOD_OLD_REV 0 /* The good old (original) format */ +#define EXT2_DYNAMIC_REV 1 /* V2 format w/ dynamic inode sizes */ + +#define EXT2_GOOD_OLD_INODE_SIZE 128 +uint32_t ext2_inode_size = EXT2_GOOD_OLD_INODE_SIZE; +#endif + /* The ext2 superblock. */ struct ext2_sblock { uint32_t total_inodes; @@ -188,8 +200,8 @@ static int ext2fs_blockgroup printf ("ext2fs read blockgroup\n"); #endif return (ext2fs_devread - (((__le32_to_cpu (data->sblock.first_data_block) + - 1) << LOG2_EXT2_BLOCK_SIZE (data)), + ((__le32_to_cpu (data->sblock.first_data_block) + + 1), LOG2_EXT2_BLOCK_SIZE (data), group * sizeof (struct ext2_block_group), sizeof (struct ext2_block_group), (char *) blkgrp)); } @@ -217,7 +229,11 @@ static int ext2fs_read_inode if (status == 0) { return (0); } - inodes_per_block = EXT2_BLOCK_SIZE (data) / 128; +#ifdef CFG_EXT2_SUPPORT_DYNAMIC_REV + inodes_per_block = EXT2_BLOCK_SIZE (data) / ext2_inode_size; +#else + inodes_per_block = EXT2_BLOCK_SIZE (data) / 128; +#endif blkno = (ino % __le32_to_cpu (sblock->inodes_per_group)) / inodes_per_block; blkoff = (ino % __le32_to_cpu (sblock->inodes_per_group)) % @@ -226,10 +242,18 @@ static int ext2fs_read_inode printf ("ext2fs read inode blkno %d blkoff %d\n", blkno, blkoff); #endif /* Read the inode. */ +#ifdef CFG_EXT2_SUPPORT_DYNAMIC_REV + status = ext2fs_devread (__le32_to_cpu (blkgrp.inode_table_id) + blkno, + LOG2_EXT2_BLOCK_SIZE (data), + ext2_inode_size * blkoff, + sizeof (struct ext2_inode), (char *) inode); +#else + status = ext2fs_devread (((__le32_to_cpu (blkgrp.inode_table_id) + blkno) << LOG2_EXT2_BLOCK_SIZE (data)), sizeof (struct ext2_inode) * blkoff, sizeof (struct ext2_inode), (char *) inode); +#endif if (status == 0) { return (0); } @@ -243,8 +267,13 @@ void ext2fs_free_node (ext2fs_node_t node, ext2fs_node_t currroot) { } } +#define CFG_OPTIMIZE_EXT2_READ +#ifdef CFG_OPTIMIZE_EXT2_READ +static int ext2fs_read_block (ext2fs_node_t node, int fileblock, int *stream) { +#else static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { +#endif struct ext2_data *data = node->data; struct ext2_inode *inode = &node->inode; int blknr; @@ -252,9 +281,21 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { int log2_blksz = LOG2_EXT2_BLOCK_SIZE (data); int status; +#ifdef CFG_OPTIMIZE_EXT2_READ + *stream = 1;/* itself */ +#endif + /* Direct blocks. */ if (fileblock < INDIRECT_BLOCKS) { blknr = __le32_to_cpu (inode->b.blocks.dir_blocks[fileblock]); +#ifdef CFG_OPTIMIZE_EXT2_READ + while(((inode->b.blocks.dir_blocks[fileblock + 1] - + inode->b.blocks.dir_blocks[fileblock]) == 1) && + (fileblock < INDIRECT_BLOCKS - 1)) { + fileblock++; + *stream += 1; + } +#endif } /* Indirect. */ else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4))) { @@ -281,7 +322,7 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { } if ((__le32_to_cpu (inode->b.blocks.indir_block) << log2_blksz) != indir1_blkno) { - status = ext2fs_devread (__le32_to_cpu(inode->b.blocks.indir_block) << log2_blksz, + status = ext2fs_devread (__le32_to_cpu(inode->b.blocks.indir_block), log2_blksz, 0, blksz, (char *) indir1_block); if (status == 0) { @@ -294,6 +335,13 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { } blknr = __le32_to_cpu (indir1_block [fileblock - INDIRECT_BLOCKS]); +#ifdef CFG_OPTIMIZE_EXT2_READ + while(((__le32_to_cpu (indir1_block[fileblock - INDIRECT_BLOCKS + 1]) - \ + __le32_to_cpu (indir1_block[fileblock - INDIRECT_BLOCKS])) == 1) && (fileblock < (blksz - 1))) { + fileblock++; + *stream += 1; + } +#endif } /* Double indirect. */ else if (fileblock < @@ -301,6 +349,9 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { unsigned int perblock = blksz / 4; unsigned int rblock = fileblock - (INDIRECT_BLOCKS + blksz / 4); +#ifdef CFG_OPTIMIZE_EXT2_READ + int rbcnt = 0; +#endif if (indir1_block == NULL) { indir1_block = (uint32_t *) malloc (blksz); @@ -325,7 +376,7 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { } if ((__le32_to_cpu (inode->b.blocks.double_indir_block) << log2_blksz) != indir1_blkno) { - status = ext2fs_devread (__le32_to_cpu(inode->b.blocks.double_indir_block) << log2_blksz, + status = ext2fs_devread (__le32_to_cpu(inode->b.blocks.double_indir_block), log2_blksz, 0, blksz, (char *) indir1_block); if (status == 0) { @@ -359,7 +410,7 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { } if ((__le32_to_cpu (indir1_block[rblock / perblock]) << log2_blksz) != indir1_blkno) { - status = ext2fs_devread (__le32_to_cpu(indir1_block[rblock / perblock]) << log2_blksz, + status = ext2fs_devread (__le32_to_cpu(indir1_block[rblock / perblock]), log2_blksz, 0, blksz, (char *) indir2_block); if (status == 0) { @@ -370,6 +421,14 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { __le32_to_cpu (indir1_block[rblock / perblock]) << log2_blksz; } blknr = __le32_to_cpu (indir2_block[rblock % perblock]); +#ifdef CFG_OPTIMIZE_EXT2_READ + rbcnt = rblock % perblock; + while(((__le32_to_cpu (indir2_block[rbcnt + 1]) - \ + __le32_to_cpu (indir2_block[rbcnt])) == 1) && (rbcnt < (blksz - 1))) { + rbcnt++; + *stream += 1; + } +#endif } /* Tripple indirect. */ else { @@ -382,7 +441,57 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { return (blknr); } +#ifdef CFG_OPTIMIZE_EXT2_READ +int ext2fs_read_file + (ext2fs_node_t node, int pos, unsigned int len, char *buf) { + int log2blocksize = LOG2_EXT2_BLOCK_SIZE (node->data); + int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS); + unsigned int filesize = __le32_to_cpu(node->inode.size); + int blknr; + int blockend; + int status; + int remain = len; + char *buffer = buf; + int stream = 0; + int cur = pos / blocksize; + int blockoff = pos % blocksize; + /* Adjust len so it we can't read past the end of the file. */ + if (len > filesize) { + len = filesize; + } + + while (remain > 0) { + blknr = ext2fs_read_block (node, cur, &stream); + if (blknr < 0) { + return (-1); + } + blknr = blknr << log2blocksize; + + if(remain < blocksize * stream) { + blockend = remain; + } else { + blockend = blocksize * stream; + } + + status = ext2fs_devread (blknr, 0, blockoff, blockend, buffer); + if (status == 0) { + return (-1); + } + + remain -= blockend; + buffer += blockend; + cur += stream; + blockoff = 0; + + if(remain == 0) + return (len); + else if(remain < 0) + return (-1); + } + return (len); +} +#else int ext2fs_read_file (ext2fs_node_t node, int pos, unsigned int len, char *buf) { int i; @@ -431,17 +540,18 @@ int ext2fs_read_file if (blknr) { int status; - status = ext2fs_devread (blknr, skipfirst, blockend, buf); + status = ext2fs_devread (blknr, 0, skipfirst, blockend, buf); if (status == 0) { return (-1); } } else { - memset (buf, blocksize - skipfirst, 0); + memset (buf, 0, blocksize - skipfirst); } buf += blocksize - skipfirst; } return (len); } +#endif static int ext2fs_iterate_dir (ext2fs_node_t dir, char *name, ext2fs_node_t * fnode, int *ftype) @@ -472,7 +582,8 @@ static int ext2fs_iterate_dir (ext2fs_node_t dir, char *name, ext2fs_node_t * fn return (0); } if (dirent.namelen != 0) { - char filename[dirent.namelen + 1]; + char *filename; + filename = (char*)malloc(dirent.namelen + 1); ext2fs_node_t fdiro; int type = FILETYPE_UNKNOWN; @@ -569,6 +680,7 @@ static int ext2fs_iterate_dir (ext2fs_node_t dir, char *name, ext2fs_node_t * fn filename); } free (fdiro); + free (filename); } fpos += __le16_to_cpu (dirent.direntlen); } @@ -724,7 +836,7 @@ int ext2fs_find_file symlinknest = 0; - if (!path) { + if (!path || path[0] != '/') { return (0); } @@ -845,7 +957,7 @@ int ext2fs_mount (unsigned part_length) { return (0); } /* Read the superblock. */ - status = ext2fs_devread (1 * 2, 0, sizeof (struct ext2_sblock), + status = ext2fs_devread (1 * 2, 0, 0, sizeof (struct ext2_sblock), (char *) &data->sblock); if (status == 0) { goto fail; @@ -854,6 +966,18 @@ int ext2fs_mount (unsigned part_length) { if (__le16_to_cpu (data->sblock.magic) != EXT2_MAGIC) { goto fail; } +#ifdef CFG_EXT2_SUPPORT_DYNAMIC_REV +#ifdef DEBUG + printf("revision_level = 0x%x, inode_size = 0x%x\n", data->sblock.revision_level, data->sblock.inode_size); +#endif + if (__le32_to_cpu (data->sblock.revision_level) == EXT2_GOOD_OLD_REV) { + ext2_inode_size = EXT2_GOOD_OLD_INODE_SIZE; + } else { + ext2_inode_size = __le16_to_cpu (data->sblock.inode_size); + } +#endif + + data->diropen.data = data; data->diropen.ino = 2; data->diropen.inode_read = 1; diff --git a/fs/fat/.depend b/fs/fat/.depend new file mode 100644 index 0000000..cdda012 --- /dev/null +++ b/fs/fat/.depend @@ -0,0 +1,69 @@ +fat.o: fat.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/fat.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/byteorder.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/little_endian.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/swab.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/generic.h +file.o: file.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/fat.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/byteorder.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/little_endian.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/swab.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/generic.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stat.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/time.h diff --git a/fs/fat/fat.c b/fs/fat/fat.c index a823b5a..23c0dc6 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -59,7 +59,8 @@ int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) if (cur_dev == NULL) return -1; if (cur_dev->block_read) { - return cur_dev->block_read (cur_dev->dev, startblock, getsize, (unsigned long *)bufptr); + return cur_dev->block_read (cur_dev->dev + , startblock, getsize, (unsigned long *)bufptr); } return -1; } @@ -69,10 +70,11 @@ int fat_register_device(block_dev_desc_t *dev_desc, int part_no) { unsigned char buffer[SECTOR_SIZE]; + disk_partition_t info; if (!dev_desc->block_read) return -1; - cur_dev=dev_desc; + cur_dev = dev_desc; /* check if we have a MBR (on floppies we have only a PBR) */ if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) { printf ("** Can't read from device %d **\n", dev_desc->dev); @@ -83,33 +85,41 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no) /* no signature found */ return -1; } - if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { +#if (defined(CONFIG_CMD_IDE) || \ + defined(CONFIG_CMD_SCSI) || \ + defined(CONFIG_CMD_USB) || \ + defined(CONFIG_MMC) || \ + defined(CONFIG_SYSTEMACE) ) + /* First we assume, there is a MBR */ + if (!get_partition_info (dev_desc, part_no, &info)) { + part_offset = info.start; + cur_part = part_no; + } else if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) { /* ok, we assume we are on a PBR only */ cur_part = 1; - part_offset=0; + part_offset = 0; + } else { + printf ("** Partition %d not valid on device %d **\n", + part_no, dev_desc->dev); + return -1; } - else { -#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ - (CONFIG_COMMANDS & CFG_CMD_USB) || defined(CONFIG_SYSTEMACE) - disk_partition_t info; - if(!get_partition_info(dev_desc, part_no, &info)) { - part_offset = info.start; - cur_part = part_no; - } - else { - printf ("** Partition %d not valid on device %d **\n",part_no,dev_desc->dev); - return -1; - } + #else + if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { + /* ok, we assume we are on a PBR only */ + cur_part = 1; + part_offset = 0; + info.start = part_offset; + } else { /* FIXME we need to determine the start block of the * partition where the DOS FS resides. This can be done * by using the get_partition_info routine. For this * purpose the libpart must be included. */ - part_offset=32; + part_offset = 32; cur_part = 1; -#endif } +#endif return 0; } @@ -342,9 +352,9 @@ get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, newclust = get_fatent(mydata, endclust); if((newclust -1)!=endclust) goto getit; - if (newclust <= 0x0001 || newclust >= 0xfff0) { - FAT_DPRINT("curclust: 0x%x\n", newclust); - FAT_DPRINT("Invalid FAT entry\n"); + if (CHECK_CLUST(newclust, mydata->fatsize)) { + FAT_ERROR("curclust: 0x%08x fatsize=%d\n", newclust, mydata->fatsize); + FAT_ERROR("Invalid FAT entry\n"); return gotsize; } endclust=newclust; @@ -377,8 +387,8 @@ getit: filesize -= actsize; buffer += actsize; curclust = get_fatent(mydata, endclust); - if (curclust <= 0x0001 || curclust >= 0xfff0) { - FAT_DPRINT("curclust: 0x%x\n", curclust); + if (CHECK_CLUST(curclust, mydata->fatsize)) { + FAT_ERROR("curclust: 0x%08x fatsize=%d\n", curclust, mydata->fatsize); FAT_ERROR("Invalid FAT entry\n"); return gotsize; } @@ -449,8 +459,8 @@ get_vfatname(fsdata *mydata, int curclust, __u8 *cluster, slotptr--; curclust = get_fatent(mydata, curclust); - if (curclust <= 0x0001 || curclust >= 0xfff0) { - FAT_DPRINT("curclust: 0x%x\n", curclust); + if (CHECK_CLUST(curclust, mydata->fatsize)) { + FAT_ERROR("curclust: 0x%08x fatsize=%d\n", curclust, mydata->fatsize); FAT_ERROR("Invalid FAT entry\n"); return -1; } @@ -642,8 +652,8 @@ static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, return retdent; } curclust = get_fatent (mydata, curclust); - if (curclust <= 0x0001 || curclust >= 0xfff0) { - FAT_DPRINT ("curclust: 0x%x\n", curclust); + if (CHECK_CLUST(curclust, mydata->fatsize)) { + FAT_ERROR ("curclust: 0x%08x fatsize=%d\n", curclust, mydata->fatsize); FAT_ERROR ("Invalid FAT entry\n"); return NULL; } @@ -972,7 +982,7 @@ file_fat_detectfs(void) return 1; } #if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ - (CONFIG_COMMANDS & CFG_CMD_USB) || (CONFIG_MMC) + (CONFIG_COMMANDS & CFG_CMD_USB) || (CONFIG_COMMANDS & CFG_CMD_MMC) printf("Interface: "); switch(cur_dev->if_type) { case IF_TYPE_IDE : printf("IDE"); break; @@ -993,7 +1003,8 @@ file_fat_detectfs(void) memcpy (vol_label, volinfo.volume_label, 11); vol_label[11] = '\0'; volinfo.fs_type[5]='\0'; - printf("Partition %d: Filesystem: %s \"%s\"\n",cur_part,volinfo.fs_type,vol_label); + printf("Partition %d: Filesystem: %s \"%s\"\n" + ,cur_part,volinfo.fs_type,vol_label); return 0; } diff --git a/fs/fdos/.depend b/fs/fdos/.depend new file mode 100644 index 0000000..e596681 --- /dev/null +++ b/fs/fdos/.depend @@ -0,0 +1,172 @@ +fat.o: fat.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h diff --git a/fs/jffs2/.depend b/fs/jffs2/.depend new file mode 100644 index 0000000..8ce356f --- /dev/null +++ b/fs/jffs2/.depend @@ -0,0 +1,103 @@ +jffs2_1pass.o: jffs2_1pass.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stat.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/time.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/jffs2.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/load_kernel.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/list.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/jffs2_1pass.h \ + jffs2_private.h +compr_rtime.o: compr_rtime.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/jffs2.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/load_kernel.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/list.h +compr_rubin.o: compr_rubin.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/jffs2.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/load_kernel.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/list.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/compr_rubin.h +compr_zlib.o: compr_zlib.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/jffs2.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/load_kernel.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/list.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/mini_inflate.h +mini_inflate.o: mini_inflate.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/jffs2/mini_inflate.h +compr_lzo.o: compr_lzo.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +compr_lzari.o: compr_lzari.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h diff --git a/fs/jffs2/Makefile b/fs/jffs2/Makefile index f28b17a..ee40493 100644 --- a/fs/jffs2/Makefile +++ b/fs/jffs2/Makefile @@ -26,7 +26,13 @@ include $(TOPDIR)/config.mk LIB = libjffs2.a AOBJS = -COBJS = jffs2_1pass.o compr_rtime.o compr_rubin.o compr_zlib.o mini_inflate.o + +ifeq ($(findstring MV_NAND,$(CPPFLAGS)),) +COBJS = jffs2_1pass.o +else +COBJS = jffs2_nand_1pass.o +endif +COBJS += compr_rtime.o compr_rubin.o compr_zlib.o mini_inflate.o COBJS += compr_lzo.o compr_lzari.o OBJS = $(AOBJS) $(COBJS) diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index c6c0c2a..062ad82 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -144,6 +144,11 @@ static struct part_info *current_part; #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CFG_NAND_LEGACY) +#include +#else +#include +#endif /* * Support for jffs2 on top of NAND-flash * @@ -154,9 +159,14 @@ static struct part_info *current_part; * */ -/* this one defined in cmd_nand.c */ +#if defined(CFG_NAND_LEGACY) +/* this one defined in nand_legacy.c */ int read_jffs2_nand(size_t start, size_t len, - size_t * retlen, u_char * buf, int nanddev); + size_t * retlen, u_char * buf, int nanddev); +#else +/* info for NAND chips, defined in drivers/nand/nand.c */ +extern nand_info_t nand_info[]; +#endif #define NAND_PAGE_SIZE 512 #define NAND_PAGE_SHIFT 9 @@ -174,7 +184,11 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf) { struct mtdids *id = current_part->dev->id; u32 bytes_read = 0; +#if defined(CFG_NAND_LEGACY) size_t retlen; +#else + ulong retlen; +#endif int cpy_bytes; while (bytes_read < size) { @@ -191,6 +205,8 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf) return -1; } } + +#if defined(CFG_NAND_LEGACY) if (read_jffs2_nand(nand_cache_off, NAND_CACHE_SIZE, &retlen, nand_cache, id->num) < 0 || retlen != NAND_CACHE_SIZE) { @@ -198,6 +214,16 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf) nand_cache_off, NAND_CACHE_SIZE); return -1; } +#else + retlen = NAND_CACHE_SIZE; + if (nand_read(&nand_info[id->num], nand_cache_off, + &retlen, nand_cache) != 0 || + retlen != NAND_CACHE_SIZE) { + printf("read_nand_cached: error reading nand off %#x size %d bytes\n", + nand_cache_off, NAND_CACHE_SIZE); + return -1; + } +#endif } cpy_bytes = nand_cache_off + NAND_CACHE_SIZE - (off + bytes_read); if (cpy_bytes > size - bytes_read) @@ -637,8 +663,12 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 inode, char *dest) putLabeledWord("read_inode: dest = ", lDest); #endif switch (jNode->compr) { - case JFFS2_COMPR_NONE: + case JFFS2_COMPR_NONE: +#ifdef MV_INC_BOARD_SPI_FLASH + ret = (unsigned long) memcpyFlash(lDest, src, jNode->dsize); +#else ret = (unsigned long) ldr_memcpy(lDest, src, jNode->dsize); +#endif break; case JFFS2_COMPR_ZERO: ret = 0; @@ -1167,7 +1197,8 @@ jffs2_1pass_build_lists(struct part_info * part) if (node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) { /* if its a fragment add it */ if (node->nodetype == JFFS2_NODETYPE_INODE && - inode_crc((struct jffs2_raw_inode *) node)) { + inode_crc((struct jffs2_raw_inode *) node) && + data_crc((struct jffs2_raw_inode *) node)) { if (insert_node(&pL->frag, (u32) part->offset + offset) == NULL) { put_fl_mem(node); diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c new file mode 100644 index 0000000..e78af75 --- /dev/null +++ b/fs/jffs2/jffs2_nand_1pass.c @@ -0,0 +1,1036 @@ +#include + +#if !defined(CFG_NAND_LEGACY) && (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +#include +#include +#include + +#include +#include +#include + +#include "jffs2_nand_private.h" + +#define NODE_CHUNK 1024 /* size of memory allocation chunk in b_nodes */ + +/* Debugging switches */ +#undef DEBUG_DIRENTS /* print directory entry list after scan */ +#undef DEBUG_FRAGMENTS /* print fragment list after scan */ +#undef DEBUG /* enable debugging messages */ + +#ifdef DEBUG +# define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +# define DEBUGF(fmt,args...) +#endif + +static nand_info_t *nand; + +/* Compression names */ +static char *compr_names[] = { + "NONE", + "ZERO", + "RTIME", + "RUBINMIPS", + "COPY", + "DYNRUBIN", + "ZLIB", +#if defined(CONFIG_JFFS2_LZO_LZARI) + "LZO", + "LZARI", +#endif +}; + +/* Spinning wheel */ +static char spinner[] = { '|', '/', '-', '\\' }; + +/* Memory management */ +struct mem_block { + unsigned index; + struct mem_block *next; + char nodes[0]; +}; + +static void +free_nodes(struct b_list *list) +{ + while (list->listMemBase != NULL) { + struct mem_block *next = list->listMemBase->next; + free(list->listMemBase); + list->listMemBase = next; + } +} + +static struct b_node * +add_node(struct b_list *list, int size) +{ + u32 index = 0; + struct mem_block *memBase; + struct b_node *b; + + memBase = list->listMemBase; + if (memBase != NULL) + index = memBase->index; + + if (memBase == NULL || index >= NODE_CHUNK) { + /* we need more space before we continue */ + memBase = mmalloc(sizeof(struct mem_block) + NODE_CHUNK * size); + if (memBase == NULL) { + putstr("add_node: malloc failed\n"); + return NULL; + } + memBase->next = list->listMemBase; + index = 0; + } + /* now we have room to add it. */ + b = (struct b_node *)&memBase->nodes[size * index]; + index ++; + + memBase->index = index; + list->listMemBase = memBase; + list->listCount++; + return b; +} + +static struct b_node * +insert_node(struct b_list *list, struct b_node *new) +{ +#ifdef CFG_JFFS2_SORT_FRAGMENTS + struct b_node *b, *prev; + + if (list->listTail != NULL && list->listCompare(new, list->listTail)) + prev = list->listTail; + else if (list->listLast != NULL && list->listCompare(new, list->listLast)) + prev = list->listLast; + else + prev = NULL; + + for (b = (prev ? prev->next : list->listHead); + b != NULL && list->listCompare(new, b); + prev = b, b = b->next) { + list->listLoops++; + } + if (b != NULL) + list->listLast = prev; + + if (b != NULL) { + new->next = b; + if (prev != NULL) + prev->next = new; + else + list->listHead = new; + } else +#endif + { + new->next = (struct b_node *) NULL; + if (list->listTail != NULL) { + list->listTail->next = new; + list->listTail = new; + } else { + list->listTail = list->listHead = new; + } + } + + return new; +} + +static struct b_node * +insert_inode(struct b_list *list, struct jffs2_raw_inode *node, u32 offset) +{ + struct b_inode *new; + + if (!(new = (struct b_inode *)add_node(list, sizeof(struct b_inode)))) { + putstr("add_node failed!\r\n"); + return NULL; + } + new->offset = offset; + new->version = node->version; + new->ino = node->ino; + new->isize = node->isize; + new->csize = node->csize; + + return insert_node(list, (struct b_node *)new); +} + +static struct b_node * +insert_dirent(struct b_list *list, struct jffs2_raw_dirent *node, u32 offset) +{ + struct b_dirent *new; + + if (!(new = (struct b_dirent *)add_node(list, sizeof(struct b_dirent)))) { + putstr("add_node failed!\r\n"); + return NULL; + } + new->offset = offset; + new->version = node->version; + new->pino = node->pino; + new->ino = node->ino; + new->nhash = full_name_hash(node->name, node->nsize); + new->nsize = node->nsize; + new->type = node->type; + + return insert_node(list, (struct b_node *)new); +} + +#ifdef CFG_JFFS2_SORT_FRAGMENTS +/* Sort data entries with the latest version last, so that if there + * is overlapping data the latest version will be used. + */ +static int compare_inodes(struct b_node *new, struct b_node *old) +{ + struct jffs2_raw_inode ojNew; + struct jffs2_raw_inode ojOld; + struct jffs2_raw_inode *jNew = + (struct jffs2_raw_inode *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew); + struct jffs2_raw_inode *jOld = + (struct jffs2_raw_inode *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld); + + return jNew->version > jOld->version; +} + +/* Sort directory entries so all entries in the same directory + * with the same name are grouped together, with the latest version + * last. This makes it easy to eliminate all but the latest version + * by marking the previous version dead by setting the inode to 0. + */ +static int compare_dirents(struct b_node *new, struct b_node *old) +{ + struct jffs2_raw_dirent ojNew; + struct jffs2_raw_dirent ojOld; + struct jffs2_raw_dirent *jNew = + (struct jffs2_raw_dirent *)get_fl_mem(new->offset, sizeof(ojNew), &ojNew); + struct jffs2_raw_dirent *jOld = + (struct jffs2_raw_dirent *)get_fl_mem(old->offset, sizeof(ojOld), &ojOld); + int cmp; + + /* ascending sort by pino */ + if (jNew->pino != jOld->pino) + return jNew->pino > jOld->pino; + + /* pino is the same, so use ascending sort by nsize, so + * we don't do strncmp unless we really must. + */ + if (jNew->nsize != jOld->nsize) + return jNew->nsize > jOld->nsize; + + /* length is also the same, so use ascending sort by name + */ + cmp = strncmp(jNew->name, jOld->name, jNew->nsize); + if (cmp != 0) + return cmp > 0; + + /* we have duplicate names in this directory, so use ascending + * sort by version + */ + if (jNew->version > jOld->version) { + /* since jNew is newer, we know jOld is not valid, so + * mark it with inode 0 and it will not be used + */ + jOld->ino = 0; + return 1; + } + + return 0; +} +#endif + +static u32 +jffs_init_1pass_list(struct part_info *part) +{ + struct b_lists *pL; + + if (part->jffs2_priv != NULL) { + pL = (struct b_lists *)part->jffs2_priv; + free_nodes(&pL->frag); + free_nodes(&pL->dir); + free(pL); + } + if (NULL != (part->jffs2_priv = malloc(sizeof(struct b_lists)))) { + pL = (struct b_lists *)part->jffs2_priv; + + memset(pL, 0, sizeof(*pL)); +#ifdef CFG_JFFS2_SORT_FRAGMENTS + pL->dir.listCompare = compare_dirents; + pL->frag.listCompare = compare_inodes; +#endif + } + return 0; +} + +/* find the inode from the slashless name given a parent */ +static long +jffs2_1pass_read_inode(struct b_lists *pL, u32 ino, char *dest, + struct stat *stat) +{ + struct b_inode *jNode; + u32 totalSize = 0; + u32 latestVersion = 0; + long ret; + +#ifdef CFG_JFFS2_SORT_FRAGMENTS + /* Find file size before loading any data, so fragments that + * start past the end of file can be ignored. A fragment + * that is partially in the file is loaded, so extra data may + * be loaded up to the next 4K boundary above the file size. + * This shouldn't cause trouble when loading kernel images, so + * we will live with it. + */ + for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) { + if ((ino == jNode->ino)) { + /* get actual file length from the newest node */ + if (jNode->version >= latestVersion) { + totalSize = jNode->isize; + latestVersion = jNode->version; + } + } + } +#endif + + for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) { + if ((ino != jNode->ino)) + continue; +#ifndef CFG_JFFS2_SORT_FRAGMENTS + /* get actual file length from the newest node */ + if (jNode->version >= latestVersion) { + totalSize = jNode->isize; + latestVersion = jNode->version; + } +#endif + if (dest || stat) { + char *src, *dst; + char data[4096 + sizeof(struct jffs2_raw_inode)]; + struct jffs2_raw_inode *inode; + size_t len; + + inode = (struct jffs2_raw_inode *)&data; + len = sizeof(struct jffs2_raw_inode); + if (dest) + len += jNode->csize; + nand_read(nand, jNode->offset, &len, inode); + /* ignore data behind latest known EOF */ + if (inode->offset > totalSize) + continue; + + if (stat) { + stat->st_mtime = inode->mtime; + stat->st_mode = inode->mode; + stat->st_ino = inode->ino; + stat->st_size = totalSize; + } + + if (!dest) + continue; + + src = ((char *) inode) + sizeof(struct jffs2_raw_inode); + dst = (char *) (dest + inode->offset); + + switch (inode->compr) { + case JFFS2_COMPR_NONE: + ret = 0; + memcpy(dst, src, inode->dsize); + break; + case JFFS2_COMPR_ZERO: + ret = 0; + memset(dst, 0, inode->dsize); + break; + case JFFS2_COMPR_RTIME: + ret = 0; + rtime_decompress(src, dst, inode->csize, inode->dsize); + break; + case JFFS2_COMPR_DYNRUBIN: + /* this is slow but it works */ + ret = 0; + dynrubin_decompress(src, dst, inode->csize, inode->dsize); + break; + case JFFS2_COMPR_ZLIB: + ret = zlib_decompress(src, dst, inode->csize, inode->dsize); + break; +#if defined(CONFIG_JFFS2_LZO_LZARI) + case JFFS2_COMPR_LZO: + ret = lzo_decompress(src, dst, inode->csize, inode->dsize); + break; + case JFFS2_COMPR_LZARI: + ret = lzari_decompress(src, dst, inode->csize, inode->dsize); + break; +#endif + default: + /* unknown */ + putLabeledWord("UNKOWN COMPRESSION METHOD = ", inode->compr); + return -1; + } + } + } + + return totalSize; +} + +/* find the inode from the slashless name given a parent */ +static u32 +jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino) +{ + struct b_dirent *jDir; + int len = strlen(name); /* name is assumed slash free */ + unsigned int nhash = full_name_hash(name, len); + u32 version = 0; + u32 inode = 0; + + /* we need to search all and return the inode with the highest version */ + for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) { + if ((pino == jDir->pino) && (jDir->ino) && /* 0 for unlink */ + (len == jDir->nsize) && (nhash == jDir->nhash)) { + /* TODO: compare name */ + if (jDir->version < version) + continue; + + if (jDir->version == version && inode != 0) { + /* I'm pretty sure this isn't legal */ + putstr(" ** ERROR ** "); +/* putnstr(jDir->name, jDir->nsize); */ +/* putLabeledWord(" has dup version =", version); */ + } + inode = jDir->ino; + version = jDir->version; + } + } + return inode; +} + +char *mkmodestr(unsigned long mode, char *str) +{ + static const char *l = "xwr"; + int mask = 1, i; + char c; + + switch (mode & S_IFMT) { + case S_IFDIR: str[0] = 'd'; break; + case S_IFBLK: str[0] = 'b'; break; + case S_IFCHR: str[0] = 'c'; break; + case S_IFIFO: str[0] = 'f'; break; + case S_IFLNK: str[0] = 'l'; break; + case S_IFSOCK: str[0] = 's'; break; + case S_IFREG: str[0] = '-'; break; + default: str[0] = '?'; + } + + for(i = 0; i < 9; i++) { + c = l[i%3]; + str[9-i] = (mode & mask)?c:'-'; + mask = mask<<1; + } + + if(mode & S_ISUID) str[3] = (mode & S_IXUSR)?'s':'S'; + if(mode & S_ISGID) str[6] = (mode & S_IXGRP)?'s':'S'; + if(mode & S_ISVTX) str[9] = (mode & S_IXOTH)?'t':'T'; + str[10] = '\0'; + return str; +} + +static inline void dump_stat(struct stat *st, const char *name) +{ + char str[20]; + char s[64], *p; + + if (st->st_mtime == (time_t)(-1)) /* some ctimes really hate -1 */ + st->st_mtime = 1; + + ctime_r(&st->st_mtime, s/*,64*/); /* newlib ctime doesn't have buflen */ + + if ((p = strchr(s,'\n')) != NULL) *p = '\0'; + if ((p = strchr(s,'\r')) != NULL) *p = '\0'; + +/* + printf("%6lo %s %8ld %s %s\n", st->st_mode, mkmodestr(st->st_mode, str), + st->st_size, s, name); +*/ + + printf(" %s %8ld %s %s", mkmodestr(st->st_mode,str), st->st_size, s, name); +} + +static inline int +dump_inode(struct b_lists *pL, struct b_dirent *d, struct b_inode *i) +{ + char fname[JFFS2_MAX_NAME_LEN + 1]; + struct stat st; + size_t len; + + if(!d || !i) return -1; + len = d->nsize; + nand_read(nand, d->offset + sizeof(struct jffs2_raw_dirent), + &len, &fname); + fname[d->nsize] = '\0'; + + memset(&st, 0, sizeof(st)); + + jffs2_1pass_read_inode(pL, i->ino, NULL, &st); + + dump_stat(&st, fname); +/* FIXME + if (d->type == DT_LNK) { + unsigned char *src = (unsigned char *) (&i[1]); + putstr(" -> "); + putnstr(src, (int)i->dsize); + } +*/ + putstr("\r\n"); + + return 0; +} + +/* list inodes with the given pino */ +static u32 +jffs2_1pass_list_inodes(struct b_lists * pL, u32 pino) +{ + struct b_dirent *jDir; + u32 i_version = 0; + + for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) { + if ((pino == jDir->pino) && (jDir->ino)) { /* ino=0 -> unlink */ + struct b_inode *jNode = (struct b_inode *)pL->frag.listHead; + struct b_inode *i = NULL; + + while (jNode) { + if (jNode->ino == jDir->ino && jNode->version >= i_version) { + i_version = jNode->version; + i = jNode; + } + jNode = jNode->next; + } + dump_inode(pL, jDir, i); + } + } + return pino; +} + +static u32 +jffs2_1pass_search_inode(struct b_lists * pL, const char *fname, u32 pino) +{ + int i; + char tmp[256]; + char working_tmp[256]; + char *c; + + /* discard any leading slash */ + i = 0; + while (fname[i] == '/') + i++; + strcpy(tmp, &fname[i]); + + while ((c = (char *) strchr(tmp, '/'))) /* we are still dired searching */ + { + strncpy(working_tmp, tmp, c - tmp); + working_tmp[c - tmp] = '\0'; +#if 0 + putstr("search_inode: tmp = "); + putstr(tmp); + putstr("\r\n"); + putstr("search_inode: wtmp = "); + putstr(working_tmp); + putstr("\r\n"); + putstr("search_inode: c = "); + putstr(c); + putstr("\r\n"); +#endif + for (i = 0; i < strlen(c) - 1; i++) + tmp[i] = c[i + 1]; + tmp[i] = '\0'; +#if 0 + putstr("search_inode: post tmp = "); + putstr(tmp); + putstr("\r\n"); +#endif + + if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino))) { + putstr("find_inode failed for name="); + putstr(working_tmp); + putstr("\r\n"); + return 0; + } + } + /* this is for the bare filename, directories have already been mapped */ + if (!(pino = jffs2_1pass_find_inode(pL, tmp, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + return pino; + +} + +static u32 +jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino) +{ + struct b_dirent *jDir; + struct b_inode *jNode; + u8 jDirFoundType = 0; + u32 jDirFoundIno = 0; + u32 jDirFoundPino = 0; + char tmp[JFFS2_MAX_NAME_LEN + 1]; + u32 version = 0; + u32 pino; + + /* we need to search all and return the inode with the highest version */ + for (jDir = (struct b_dirent *)pL->dir.listHead; jDir; jDir = jDir->next) { + if (ino == jDir->ino) { + if (jDir->version < version) + continue; + + if (jDir->version == version && jDirFoundType) { + /* I'm pretty sure this isn't legal */ + putstr(" ** ERROR ** "); +/* putnstr(jDir->name, jDir->nsize); */ +/* putLabeledWord(" has dup version (resolve) = ", */ +/* version); */ + } + + jDirFoundType = jDir->type; + jDirFoundIno = jDir->ino; + jDirFoundPino = jDir->pino; + version = jDir->version; + } + } + /* now we found the right entry again. (shoulda returned inode*) */ + if (jDirFoundType != DT_LNK) + return jDirFoundIno; + + /* it's a soft link so we follow it again. */ + for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) { + if (jNode->ino == jDirFoundIno) { + size_t len = jNode->csize; + nand_read(nand, jNode->offset + sizeof(struct jffs2_raw_inode), &len, &tmp); + tmp[jNode->csize] = '\0'; + break; + } + } + /* ok so the name of the new file to find is in tmp */ + /* if it starts with a slash it is root based else shared dirs */ + if (tmp[0] == '/') + pino = 1; + else + pino = jDirFoundPino; + + return jffs2_1pass_search_inode(pL, tmp, pino); +} + +static u32 +jffs2_1pass_search_list_inodes(struct b_lists * pL, const char *fname, u32 pino) +{ + int i; + char tmp[256]; + char working_tmp[256]; + char *c; + + /* discard any leading slash */ + i = 0; + while (fname[i] == '/') + i++; + strcpy(tmp, &fname[i]); + working_tmp[0] = '\0'; + while ((c = (char *) strchr(tmp, '/'))) /* we are still dired searching */ + { + strncpy(working_tmp, tmp, c - tmp); + working_tmp[c - tmp] = '\0'; + for (i = 0; i < strlen(c) - 1; i++) + tmp[i] = c[i + 1]; + tmp[i] = '\0'; + /* only a failure if we arent looking at top level */ + if (!(pino = jffs2_1pass_find_inode(pL, working_tmp, pino)) && + (working_tmp[0])) { + putstr("find_inode failed for name="); + putstr(working_tmp); + putstr("\r\n"); + return 0; + } + } + + if (tmp[0] && !(pino = jffs2_1pass_find_inode(pL, tmp, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + /* this is for the bare filename, directories have already been mapped */ + if (!(pino = jffs2_1pass_list_inodes(pL, pino))) { + putstr("find_inode failed for name="); + putstr(tmp); + putstr("\r\n"); + return 0; + } + return pino; + +} + +unsigned char +jffs2_1pass_rescan_needed(struct part_info *part) +{ + struct b_node *b; + struct jffs2_unknown_node onode; + struct jffs2_unknown_node *node; + struct b_lists *pL = (struct b_lists *)part->jffs2_priv; + + if (part->jffs2_priv == 0){ + DEBUGF ("rescan: First time in use\n"); + return 1; + } + /* if we have no list, we need to rescan */ + if (pL->frag.listCount == 0) { + DEBUGF ("rescan: fraglist zero\n"); + return 1; + } + + /* or if we are scanning a new partition */ + if (pL->partOffset != part->offset) { + DEBUGF ("rescan: different partition\n"); + return 1; + } + + /* FIXME */ +#if 0 + /* but suppose someone reflashed a partition at the same offset... */ + b = pL->dir.listHead; + while (b) { + node = (struct jffs2_unknown_node *) get_fl_mem(b->offset, + sizeof(onode), &onode); + if (node->nodetype != JFFS2_NODETYPE_DIRENT) { + DEBUGF ("rescan: fs changed beneath me? (%lx)\n", + (unsigned long) b->offset); + return 1; + } + b = b->next; + } +#endif + return 0; +} + +#ifdef DEBUG_FRAGMENTS +static void +dump_fragments(struct b_lists *pL) +{ + struct b_node *b; + struct jffs2_raw_inode ojNode; + struct jffs2_raw_inode *jNode; + + putstr("\r\n\r\n******The fragment Entries******\r\n"); + b = pL->frag.listHead; + while (b) { + jNode = (struct jffs2_raw_inode *) get_fl_mem(b->offset, + sizeof(ojNode), &ojNode); + putLabeledWord("\r\n\tbuild_list: FLASH_OFFSET = ", b->offset); + putLabeledWord("\tbuild_list: totlen = ", jNode->totlen); + putLabeledWord("\tbuild_list: inode = ", jNode->ino); + putLabeledWord("\tbuild_list: version = ", jNode->version); + putLabeledWord("\tbuild_list: isize = ", jNode->isize); + putLabeledWord("\tbuild_list: atime = ", jNode->atime); + putLabeledWord("\tbuild_list: offset = ", jNode->offset); + putLabeledWord("\tbuild_list: csize = ", jNode->csize); + putLabeledWord("\tbuild_list: dsize = ", jNode->dsize); + putLabeledWord("\tbuild_list: compr = ", jNode->compr); + putLabeledWord("\tbuild_list: usercompr = ", jNode->usercompr); + putLabeledWord("\tbuild_list: flags = ", jNode->flags); + putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */ + b = b->next; + } +} +#endif + +#ifdef DEBUG_DIRENTS +static void +dump_dirents(struct b_lists *pL) +{ + struct b_node *b; + struct jffs2_raw_dirent *jDir; + + putstr("\r\n\r\n******The directory Entries******\r\n"); + b = pL->dir.listHead; + while (b) { + jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset); + putstr("\r\n"); + putnstr(jDir->name, jDir->nsize); + putLabeledWord("\r\n\tbuild_list: magic = ", jDir->magic); + putLabeledWord("\tbuild_list: nodetype = ", jDir->nodetype); + putLabeledWord("\tbuild_list: hdr_crc = ", jDir->hdr_crc); + putLabeledWord("\tbuild_list: pino = ", jDir->pino); + putLabeledWord("\tbuild_list: version = ", jDir->version); + putLabeledWord("\tbuild_list: ino = ", jDir->ino); + putLabeledWord("\tbuild_list: mctime = ", jDir->mctime); + putLabeledWord("\tbuild_list: nsize = ", jDir->nsize); + putLabeledWord("\tbuild_list: type = ", jDir->type); + putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc); + putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc); + putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */ + b = b->next; + put_fl_mem(jDir); + } +} +#endif + +static int +jffs2_fill_scan_buf(nand_info_t *nand, unsigned char *buf, + unsigned ofs, unsigned len) +{ + int ret; + unsigned olen; + + olen = len; + ret = nand_read(nand, ofs, &olen, buf); + if (ret) { + printf("nand_read(0x%x bytes from 0x%x) returned %d\n", len, ofs, ret); + return ret; + } + if (olen < len) { + printf("Read at 0x%x gave only 0x%x bytes\n", ofs, olen); + return -1; + } + return 0; +} + +#define EMPTY_SCAN_SIZE 1024 +static u32 +jffs2_1pass_build_lists(struct part_info * part) +{ + struct b_lists *pL; + struct jffs2_unknown_node *node; + unsigned nr_blocks, sectorsize, ofs, offset; + char *buf; + int i; + u32 counter = 0; + u32 counter4 = 0; + u32 counterF = 0; + u32 counterN = 0; + + struct mtdids *id = part->dev->id; + nand = nand_info + id->num; + + /* if we are building a list we need to refresh the cache. */ + jffs_init_1pass_list(part); + pL = (struct b_lists *)part->jffs2_priv; + pL->partOffset = part->offset; + puts ("Scanning JFFS2 FS: "); + + sectorsize = nand->erasesize; + nr_blocks = part->size / sectorsize; + buf = malloc(sectorsize); + if (!buf) + return 0; + + for (i = 0; i < nr_blocks; i++) { + printf("\b\b%c ", spinner[counter++ % sizeof(spinner)]); + + offset = part->offset + i * sectorsize; + + if (nand_block_isbad(nand, offset)) + continue; + + if (jffs2_fill_scan_buf(nand, buf, offset, EMPTY_SCAN_SIZE)) + return 0; + + ofs = 0; + /* Scan only 4KiB of 0xFF before declaring it's empty */ + while (ofs < EMPTY_SCAN_SIZE && *(uint32_t *)(&buf[ofs]) == 0xFFFFFFFF) + ofs += 4; + if (ofs == EMPTY_SCAN_SIZE) + continue; + + if (jffs2_fill_scan_buf(nand, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE)) + return 0; + offset += ofs; + + while (ofs < sectorsize - sizeof(struct jffs2_unknown_node)) { + node = (struct jffs2_unknown_node *)&buf[ofs]; + if (node->magic != JFFS2_MAGIC_BITMASK || !hdr_crc(node)) { + offset += 4; + ofs += 4; + counter4++; + continue; + } + /* if its a fragment add it */ + if (node->nodetype == JFFS2_NODETYPE_INODE && + inode_crc((struct jffs2_raw_inode *) node)) { + if (insert_inode(&pL->frag, (struct jffs2_raw_inode *) node, + offset) == NULL) { + return 0; + } + } else if (node->nodetype == JFFS2_NODETYPE_DIRENT && + dirent_crc((struct jffs2_raw_dirent *) node) && + dirent_name_crc((struct jffs2_raw_dirent *) node)) { + if (! (counterN%100)) + puts ("\b\b. "); + if (insert_dirent(&pL->dir, (struct jffs2_raw_dirent *) node, + offset) == NULL) { + return 0; + } + counterN++; + } else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) { + if (node->totlen != sizeof(struct jffs2_unknown_node)) + printf("OOPS Cleanmarker has bad size " + "%d != %d\n", node->totlen, + sizeof(struct jffs2_unknown_node)); + } else if (node->nodetype == JFFS2_NODETYPE_PADDING) { + if (node->totlen < sizeof(struct jffs2_unknown_node)) + printf("OOPS Padding has bad size " + "%d < %d\n", node->totlen, + sizeof(struct jffs2_unknown_node)); + } else { + printf("Unknown node type: %x len %d " + "offset 0x%x\n", node->nodetype, + node->totlen, offset); + } + offset += ((node->totlen + 3) & ~3); + ofs += ((node->totlen + 3) & ~3); + counterF++; + } + } + + putstr("\b\b done.\r\n"); /* close off the dots */ + +#if 0 + putLabeledWord("dir entries = ", pL->dir.listCount); + putLabeledWord("frag entries = ", pL->frag.listCount); + putLabeledWord("+4 increments = ", counter4); + putLabeledWord("+file_offset increments = ", counterF); +#endif + +#ifdef DEBUG_DIRENTS + dump_dirents(pL); +#endif + +#ifdef DEBUG_FRAGMENTS + dump_fragments(pL); +#endif + + /* give visual feedback that we are done scanning the flash */ + led_blink(0x0, 0x0, 0x1, 0x1); /* off, forever, on 100ms, off 100ms */ + free(buf); + + return 1; +} + + +static u32 +jffs2_1pass_fill_info(struct b_lists * pL, struct b_jffs2_info * piL) +{ + struct b_node *b; + struct jffs2_raw_inode ojNode; + struct jffs2_raw_inode *jNode; + int i; + + for (i = 0; i < JFFS2_NUM_COMPR; i++) { + piL->compr_info[i].num_frags = 0; + piL->compr_info[i].compr_sum = 0; + piL->compr_info[i].decompr_sum = 0; + } +/* FIXME + b = pL->frag.listHead; + while (b) { + jNode = (struct jffs2_raw_inode *) get_fl_mem(b->offset, + sizeof(ojNode), &ojNode); + if (jNode->compr < JFFS2_NUM_COMPR) { + piL->compr_info[jNode->compr].num_frags++; + piL->compr_info[jNode->compr].compr_sum += jNode->csize; + piL->compr_info[jNode->compr].decompr_sum += jNode->dsize; + } + b = b->next; + } +*/ + return 0; +} + + +static struct b_lists * +jffs2_get_list(struct part_info * part, const char *who) +{ + if (jffs2_1pass_rescan_needed(part)) { + if (!jffs2_1pass_build_lists(part)) { + printf("%s: Failed to scan JFFSv2 file structure\n", who); + return NULL; + } + } + return (struct b_lists *)part->jffs2_priv; +} + + +/* Print directory / file contents */ +u32 +jffs2_1pass_ls(struct part_info * part, const char *fname) +{ + struct b_lists *pl; + long ret = 0; + u32 inode; + + if (! (pl = jffs2_get_list(part, "ls"))) + return 0; + + if (! (inode = jffs2_1pass_search_list_inodes(pl, fname, 1))) { + putstr("ls: Failed to scan jffs2 file structure\r\n"); + return 0; + } + +#if 0 + putLabeledWord("found file at inode = ", inode); + putLabeledWord("read_inode returns = ", ret); +#endif + + return ret; +} + + +/* Load a file from flash into memory. fname can be a full path */ +u32 +jffs2_1pass_load(char *dest, struct part_info * part, const char *fname) +{ + + struct b_lists *pl; + long ret = 0; + u32 inode; + + if (! (pl = jffs2_get_list(part, "load"))) + return 0; + + if (! (inode = jffs2_1pass_search_inode(pl, fname, 1))) { + putstr("load: Failed to find inode\r\n"); + return 0; + } + + /* Resolve symlinks */ + if (! (inode = jffs2_1pass_resolve_inode(pl, inode))) { + putstr("load: Failed to resolve inode structure\r\n"); + return 0; + } + + if ((ret = jffs2_1pass_read_inode(pl, inode, dest, NULL)) < 0) { + putstr("load: Failed to read inode\r\n"); + return 0; + } + + DEBUGF ("load: loaded '%s' to 0x%lx (%ld bytes)\n", fname, + (unsigned long) dest, ret); + return ret; +} + +/* Return information about the fs on this partition */ +u32 +jffs2_1pass_info(struct part_info * part) +{ + struct b_jffs2_info info; + struct b_lists *pl; + int i; + + if (! (pl = jffs2_get_list(part, "info"))) + return 0; + + jffs2_1pass_fill_info(pl, &info); + for (i = 0; i < JFFS2_NUM_COMPR; i++) { + printf ("Compression: %s\n" + "\tfrag count: %d\n" + "\tcompressed sum: %d\n" + "\tuncompressed sum: %d\n", + compr_names[i], + info.compr_info[i].num_frags, + info.compr_info[i].compr_sum, + info.compr_info[i].decompr_sum); + } + return 1; +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/jffs2_nand_private.h b/fs/jffs2/jffs2_nand_private.h new file mode 100644 index 0000000..18cca8d --- /dev/null +++ b/fs/jffs2/jffs2_nand_private.h @@ -0,0 +1,133 @@ +#ifndef jffs2_private_h +#define jffs2_private_h + +#include + +struct b_node { + struct b_node *next; +}; + +struct b_inode { + struct b_inode *next; + u32 offset; /* physical offset to beginning of real inode */ + u32 version; + u32 ino; + u32 isize; + u32 csize; +}; + +struct b_dirent { + struct b_dirent *next; + u32 offset; /* physical offset to beginning of real dirent */ + u32 version; + u32 pino; + u32 ino; + unsigned int nhash; + unsigned char nsize; + unsigned char type; +}; + +struct b_list { + struct b_node *listTail; + struct b_node *listHead; + unsigned int listCount; + struct mem_block *listMemBase; +}; + +struct b_lists { + char *partOffset; + struct b_list dir; + struct b_list frag; +}; + +struct b_compr_info { + u32 num_frags; + u32 compr_sum; + u32 decompr_sum; +}; + +struct b_jffs2_info { + struct b_compr_info compr_info[JFFS2_NUM_COMPR]; +}; + +static inline int +hdr_crc(struct jffs2_unknown_node *node) +{ +#if 1 + u32 crc = crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4); +#else + /* what's the semantics of this? why is this here? */ + u32 crc = crc32_no_comp(~0, (unsigned char *)node, sizeof(struct jffs2_unknown_node) - 4); + + crc ^= ~0; +#endif + if (node->hdr_crc != crc) { + return 0; + } else { + return 1; + } +} + +static inline int +dirent_crc(struct jffs2_raw_dirent *node) +{ + if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_dirent) - 8)) { + return 0; + } else { + return 1; + } +} + +static inline int +dirent_name_crc(struct jffs2_raw_dirent *node) +{ + if (node->name_crc != crc32_no_comp(0, (unsigned char *)&(node->name), node->nsize)) { + return 0; + } else { + return 1; + } +} + +static inline int +inode_crc(struct jffs2_raw_inode *node) +{ + if (node->node_crc != crc32_no_comp(0, (unsigned char *)node, sizeof(struct jffs2_raw_inode) - 8)) { + return 0; + } else { + return 1; + } +} + +/* Borrowed from include/linux/dcache.h */ + +/* Name hashing routines. Initial hash value */ +/* Hash courtesy of the R5 hash in reiserfs modulo sign bits */ +#define init_name_hash() 0 + +/* partial hash update function. Assume roughly 4 bits per character */ +static inline unsigned long +partial_name_hash(unsigned long c, unsigned long prevhash) +{ + return (prevhash + (c << 4) + (c >> 4)) * 11; +} + +/* + * Finally: cut down the number of bits to a int value (and try to avoid + * losing bits) + */ +static inline unsigned long end_name_hash(unsigned long hash) +{ + return (unsigned int) hash; +} + +/* Compute the hash for a name string. */ +static inline unsigned int +full_name_hash(const unsigned char *name, unsigned int len) +{ + unsigned long hash = init_name_hash(); + while (len--) + hash = partial_name_hash(*name++, hash); + return end_name_hash(hash); +} + +#endif /* jffs2_private.h */ diff --git a/fs/jffs2/jffs2_private.h b/fs/jffs2/jffs2_private.h index 65ca6eb..46ed644 100644 --- a/fs/jffs2/jffs2_private.h +++ b/fs/jffs2/jffs2_private.h @@ -85,4 +85,16 @@ inode_crc(struct jffs2_raw_inode *node) } } +static inline int +data_crc(struct jffs2_raw_inode *node) +{ + if (node->data_crc != crc32_no_comp(0, (unsigned char *) + ((int) &node->node_crc + sizeof (node->node_crc)), + node->csize)) { + return 0; + } else { + return 1; + } +} + #endif /* jffs2_private.h */ diff --git a/fs/reiserfs/.depend b/fs/reiserfs/.depend new file mode 100644 index 0000000..f5aaeda --- /dev/null +++ b/fs/reiserfs/.depend @@ -0,0 +1,84 @@ +reiserfs.o: reiserfs.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +dev.o: dev.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +mode_string.o: mode_string.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h diff --git a/i386_config.mk b/i386_config.mk deleted file mode 100644 index 9e6d37d..0000000 --- a/i386_config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ diff --git a/include/_exports.h b/include/_exports.h index 61dcaaf..d823c95 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -12,7 +12,14 @@ EXPORT_FUNC(udelay) EXPORT_FUNC(get_timer) EXPORT_FUNC(vprintf) EXPORT_FUNC(do_reset) +#ifdef CONFIG_MARVELL +EXPORT_FUNC(realloc) +EXPORT_FUNC(calloc) +EXPORT_FUNC(memalign) +EXPORT_FUNC(mvGetRtcSec) +#endif #if (CONFIG_COMMANDS & CFG_CMD_I2C) EXPORT_FUNC(i2c_write) EXPORT_FUNC(i2c_read) #endif /* CFG_CMD_I2C */ + diff --git a/include/ahci.h b/include/ahci.h new file mode 100644 index 0000000..80701e2 --- /dev/null +++ b/include/ahci.h @@ -0,0 +1,190 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Author: Jason Jin + * Zhang Wei + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef _AHCI_H_ +#define _AHCI_H_ + +#define AHCI_PCI_BAR 0x24 +#define AHCI_MAX_SG 56 /* hardware max is 64K */ +#define AHCI_CMD_SLOT_SZ 32 +#define AHCI_RX_FIS_SZ 256 +#define AHCI_CMD_TBL_HDR 0x80 +#define AHCI_CMD_TBL_CDB 0x40 +#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) +#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \ + + AHCI_RX_FIS_SZ +#define AHCI_CMD_ATAPI (1 << 5) +#define AHCI_CMD_WRITE (1 << 6) +#define AHCI_CMD_PREFETCH (1 << 7) +#define AHCI_CMD_RESET (1 << 8) +#define AHCI_CMD_CLR_BUSY (1 << 10) + +#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ + +/* Global controller registers */ +#define HOST_CAP 0x00 /* host capabilities */ +#define HOST_CTL 0x04 /* global host control */ +#define HOST_IRQ_STAT 0x08 /* interrupt status */ +#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ +#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ + +/* HOST_CTL bits */ +#define HOST_RESET (1 << 0) /* reset controller; self-clear */ +#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ +#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ + +/* Registers for each SATA port */ +#define PORT_LST_ADDR 0x00 /* command list DMA addr */ +#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ +#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ +#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ +#define PORT_IRQ_STAT 0x10 /* interrupt status */ +#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ +#define PORT_CMD 0x18 /* port command */ +#define PORT_TFDATA 0x20 /* taskfile data */ +#define PORT_SIG 0x24 /* device TF signature */ +#define PORT_CMD_ISSUE 0x38 /* command issue */ +#define PORT_SCR 0x28 /* SATA phy register block */ +#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ +#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ +#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ +#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ + +/* PORT_IRQ_{STAT,MASK} bits */ +#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ +#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ +#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ +#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ +#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ +#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ +#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ +#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ + +#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ +#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ +#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ +#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ +#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ +#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ +#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ +#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ +#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ + +#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ + | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR + +#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ + | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ + | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ + | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ + | PORT_IRQ_D2H_REG_FIS + +/* PORT_CMD bits */ +#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ +#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ +#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ +#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ +#define PORT_CMD_CLO (1 << 3) /* Command list override */ +#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ +#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ +#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ + +#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ +#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ +#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ + +#define AHCI_MAX_PORTS 32 + +/* SETFEATURES stuff */ +#define SETFEATURES_XFER 0x03 +#define XFER_UDMA_7 0x47 +#define XFER_UDMA_6 0x46 +#define XFER_UDMA_5 0x45 +#define XFER_UDMA_4 0x44 +#define XFER_UDMA_3 0x43 +#define XFER_UDMA_2 0x42 +#define XFER_UDMA_1 0x41 +#define XFER_UDMA_0 0x40 +#define XFER_MW_DMA_2 0x22 +#define XFER_MW_DMA_1 0x21 +#define XFER_MW_DMA_0 0x20 +#define XFER_SW_DMA_2 0x12 +#define XFER_SW_DMA_1 0x11 +#define XFER_SW_DMA_0 0x10 +#define XFER_PIO_4 0x0C +#define XFER_PIO_3 0x0B +#define XFER_PIO_2 0x0A +#define XFER_PIO_1 0x09 +#define XFER_PIO_0 0x08 +#define XFER_PIO_SLOW 0x00 + +#define ATA_FLAG_SATA (1 << 3) +#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ +#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ +#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ +#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ +#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ + +struct ahci_cmd_hdr { + u32 opts; + u32 status; + u32 tbl_addr; + u32 tbl_addr_hi; + u32 reserved[4]; +}; + +struct ahci_sg { + u32 addr; + u32 addr_hi; + u32 reserved; + u32 flags_size; +}; + +struct ahci_ioports { + u32 cmd_addr; + u32 scr_addr; + u32 port_mmio; + struct ahci_cmd_hdr *cmd_slot; + struct ahci_sg *cmd_tbl_sg; + u32 cmd_tbl; + u32 rx_fis; +}; + +struct ahci_probe_ent { + pci_dev_t dev; + struct ahci_ioports port[AHCI_MAX_PORTS]; + u32 n_ports; + u32 hard_port_no; + u32 host_flags; + u32 host_set_flags; + u32 mmio_base; + u32 pio_mask; + u32 udma_mask; + u32 flags; + u32 cap; /* cache of HOST_CAP register */ + u32 port_map; /* cache of HOST_PORTS_IMPL reg */ + u32 link_port_map; /*linkup port map*/ +}; + +#endif diff --git a/include/asm b/include/asm new file mode 120000 index 0000000..a6d0b58 --- /dev/null +++ b/include/asm @@ -0,0 +1 @@ +asm-arm \ No newline at end of file diff --git a/include/asm-arm/arch b/include/asm-arm/arch new file mode 120000 index 0000000..d28b8dc --- /dev/null +++ b/include/asm-arm/arch @@ -0,0 +1 @@ +arch-arm926ejs \ No newline at end of file diff --git a/include/asm-arm/arch-arm926ejs/vfp.h b/include/asm-arm/arch-arm926ejs/vfp.h new file mode 100644 index 0000000..051a474 --- /dev/null +++ b/include/asm-arm/arch-arm926ejs/vfp.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2004 ARM Limited. + * Written by Deep Blue Solutions Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * VFP register definitions. + * First, the standard VFP set. + */ + +#define FPSID c0 +#define FPSCR c1 +#define FPEXC c8 + +/* FPSID bits */ +#define FPSID_IMPLEMENTER_BIT (24) +#define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT) +#define FPSID_SOFTWARE (1<<23) +#define FPSID_FORMAT_BIT (21) +#define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT) +#define FPSID_NODOUBLE (1<<20) +#define FPSID_ARCH_BIT (16) +#define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) +#define FPSID_PART_BIT (8) +#define FPSID_PART_MASK (0xFF << FPSID_PART_BIT) +#define FPSID_VARIANT_BIT (4) +#define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) +#define FPSID_REV_BIT (0) +#define FPSID_REV_MASK (0xF << FPSID_REV_BIT) + +/* FPEXC bits */ +#define FPEXC_EXCEPTION (1<<31) +#define FPEXC_ENABLE (1<<30) + +/* FPSCR bits */ +#define FPSCR_DEFAULT_NAN (1<<25) +#define FPSCR_FLUSHTOZERO (1<<24) +#define FPSCR_ROUND_NEAREST (0<<22) +#define FPSCR_ROUND_PLUSINF (1<<22) +#define FPSCR_ROUND_MINUSINF (2<<22) +#define FPSCR_ROUND_TOZERO (3<<22) +#define FPSCR_RMODE_BIT (22) +#define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) +#define FPSCR_STRIDE_BIT (20) +#define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) +#define FPSCR_LENGTH_BIT (16) +#define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) +#define FPSCR_IOE (1<<8) +#define FPSCR_DZE (1<<9) +#define FPSCR_OFE (1<<10) +#define FPSCR_UFE (1<<11) +#define FPSCR_IXE (1<<12) +#define FPSCR_IDE (1<<15) +#define FPSCR_IOC (1<<0) +#define FPSCR_DZC (1<<1) +#define FPSCR_OFC (1<<2) +#define FPSCR_UFC (1<<3) +#define FPSCR_IXC (1<<4) +#define FPSCR_IDC (1<<7) + +/* + * VFP9-S specific. + */ +#define FPINST c9 +#define FPINST2 c10 + +/* FPEXC bits */ +#define FPEXC_FPV2 (1<<28) +#define FPEXC_LENGTH_BIT (8) +#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT) +#define FPEXC_INV (1 << 7) +#define FPEXC_UFC (1 << 3) +#define FPEXC_OFC (1 << 2) +#define FPEXC_IOC (1 << 0) + +/* Bit patterns for decoding the packaged operation descriptors */ +#define VFPOPDESC_LENGTH_BIT (9) +#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT) +#define VFPOPDESC_UNUSED_BIT (24) +#define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT) +#define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK)) diff --git a/include/asm-arm/arch-arm926ejs/vfpinstr.h b/include/asm-arm/arch-arm926ejs/vfpinstr.h new file mode 100644 index 0000000..39cbef3 --- /dev/null +++ b/include/asm-arm/arch-arm926ejs/vfpinstr.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2004 ARM Limited. + * Written by Deep Blue Solutions Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * VFP instruction masks. + */ +#define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000) +#define INST_CPRT(inst) ((inst) & (1 << 4)) +#define INST_CPRT_L(inst) ((inst) & (1 << 20)) +#define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12) +#define INST_CPRT_OP(inst) (((inst) >> 21) & 7) +#define INST_CPNUM(inst) ((inst) & 0xf00) +#define CPNUM(cp) ((cp) << 8) + +#define FOP_MASK (0x00b00040) +#define FOP_FMAC (0x00000000) +#define FOP_FNMAC (0x00000040) +#define FOP_FMSC (0x00100000) +#define FOP_FNMSC (0x00100040) +#define FOP_FMUL (0x00200000) +#define FOP_FNMUL (0x00200040) +#define FOP_FADD (0x00300000) +#define FOP_FSUB (0x00300040) +#define FOP_FDIV (0x00800000) +#define FOP_EXT (0x00b00040) + +#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4) + +#define FEXT_MASK (0x000f0080) +#define FEXT_FCPY (0x00000000) +#define FEXT_FABS (0x00000080) +#define FEXT_FNEG (0x00010000) +#define FEXT_FSQRT (0x00010080) +#define FEXT_FCMP (0x00040000) +#define FEXT_FCMPE (0x00040080) +#define FEXT_FCMPZ (0x00050000) +#define FEXT_FCMPEZ (0x00050080) +#define FEXT_FCVT (0x00070080) +#define FEXT_FUITO (0x00080000) +#define FEXT_FSITO (0x00080080) +#define FEXT_FTOUI (0x000c0000) +#define FEXT_FTOUIZ (0x000c0080) +#define FEXT_FTOSI (0x000d0000) +#define FEXT_FTOSIZ (0x000d0080) + +#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) + +#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22) +#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12) +#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5) +#define vfp_get_dm(inst) ((inst & 0x0000000f)) +#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) +#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16) + +#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00) + +#define FPSCR_N (1 << 31) +#define FPSCR_Z (1 << 30) +#define FPSCR_C (1 << 29) +#define FPSCR_V (1 << 28) + +/* + * Since we aren't building with -mfpu=vfp, we need to code + * these instructions using their MRC/MCR equivalents. + */ +#define vfpreg(_vfp_) #_vfp_ + +#define fmrx(_vfp_) ({ \ + u32 __v; \ + asm("mrc%? p10, 7, %0, " vfpreg(_vfp_) ", c0, 0 @ fmrx %0, " #_vfp_ \ + : "=r" (__v)); \ + __v; \ + }) + +#define fmxr(_vfp_,_var_) \ + asm("mcr%? p10, 7, %0, " vfpreg(_vfp_) ", c0, 0 @ fmxr " #_vfp_ ", %0" \ + : : "r" (_var_)) + diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 4b8bab2..2859615 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -91,6 +91,15 @@ static inline int test_bit(int nr, const void * addr) return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); } +/* Return the bit position of the most significant 1 bit in a word */ +extern __inline__ int __ilog2(unsigned int x) +{ + int lz; + + asm ("clz %0,%1" : "=r" (lz) : "r" (x)); + return 31 - lz; +} + /* * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h index c2d5291..b33175c 100644 --- a/include/asm-arm/global_data.h +++ b/include/asm-arm/global_data.h @@ -45,6 +45,10 @@ typedef struct global_data { #ifdef CONFIG_VFD unsigned char vfd_type; /* display type */ #endif +#ifdef CONFIG_MARVELL + unsigned long bus_clk; + unsigned int tclk; +#endif #if 0 unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; @@ -52,6 +56,11 @@ typedef struct global_data { unsigned long reset_status; /* reset status register at boot */ #endif void **jt; /* jump table */ +#ifdef CONFIG_MARVELL + unsigned long ram_size; /* RAM size */ + unsigned int ddr_clk; +#endif + } gd_t; /* @@ -61,6 +70,7 @@ typedef struct global_data { #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") +#define DECLARE_GLOBAL_DATA_PTR +register volatile gd_t *gd asm ("r8"); #endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index c2b69fb..919c6d3 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -193,7 +193,6 @@ extern void __readwrite_bug(const char *fn); * ioremap. */ #ifdef __mem_pci - #define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) #define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) #define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) diff --git a/include/asm-arm/proc b/include/asm-arm/proc new file mode 120000 index 0000000..c7f3c20 --- /dev/null +++ b/include/asm-arm/proc @@ -0,0 +1 @@ +proc-armv \ No newline at end of file diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h index 89df4dc..2f73016 100644 --- a/include/asm-arm/setup.h +++ b/include/asm-arm/setup.h @@ -205,6 +205,27 @@ struct tag_memclk { u32 fmemclk; }; +#if defined (CONFIG_MARVELL_TAG) +/* Marvell uboot parameters */ +#define ATAG_MV_UBOOT 0x41000403 + +struct tag_mv_uboot { + u32 uboot_version; + u32 tclk; + u32 sysclk; + u32 isUsbHost; + char macAddr[4][6]; + u16 mtu[4]; + u32 fw_image_base; + u32 fw_image_size; +#if defined(CONFIG_BUFFALO_PLATFORM) + u32 env_addr; + u32 env_size; + u32 env_offset; +#endif + u32 nand_ecc; +}; +#endif struct tag { struct tag_header hdr; union { @@ -227,6 +248,12 @@ struct tag { * DC21285 specific */ struct tag_memclk memclk; +#if defined (CONFIG_MARVELL_TAG) + /* + * Marvell specific + */ + struct tag_mv_uboot mv_uboot; +#endif } u; }; diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index 9ee4849..6573b6d 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -94,7 +94,7 @@ #define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */ #define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */ #define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */ - +#define CFG_CMD_RCVR 0x8000000000000000ULL /* Recovery Support */ #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */ /* Commands that are considered "non-standard" for some reason diff --git a/include/common.h b/include/common.h index d2570a8..98e4f72 100644 --- a/include/common.h +++ b/include/common.h @@ -388,7 +388,9 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); +#ifndef CONFIG_MARVELL void reset_cpu (ulong addr); +#endif /* $(CPU)/serial.c */ int serial_init (void); diff --git a/include/config.h b/include/config.h new file mode 100644 index 0000000..5b2b35a --- /dev/null +++ b/include/config.h @@ -0,0 +1,2 @@ +/* Automatically generated - do not edit */ +#include diff --git a/include/config.mk b/include/config.mk new file mode 100644 index 0000000..f5a0ff8 --- /dev/null +++ b/include/config.mk @@ -0,0 +1,21 @@ +ARCH = arm +CPU = arm926ejs +BOARD = config_kw +VENDOR = mv_feroceon +MV_OUTPUT = buffalo_mvlsxh_6281 +MV_FLAGS += -DCONFIG_BUFFALO_PLATFORM +MV_FLAGS += -DMV88F6281 +MV_FLAGS += -DBF_MVLSXH +MV_IMAGE_FLAGS = -DMV_SEC_64K +MV_IMAGE_FLAGS += -DMV_BOOTSIZE_512K +MV_IMAGE_FLAGS += -DMV_LARGE_PAGE +MV_FLAGS += -DMV_BOOTROM +MV_FLAGS += -DTCLK_AUTO_DETECT +MV_DDR_FREQ = 400mvlsxh +CROSS_COMPILE = arm-none-linux-gnueabi- +MV_FLAGS += -DMV_USB -DCONFIG_CMD_USB +MV_USB=y +MV_FLAGS += -DMV_SPI +MV_FLAGS += -DMV_SPI_BOOT +SPI_BOOT =y +CPPFLAGS += $(MV_IMAGE_FLAGS) $(MV_FLAGS) diff --git a/include/configs/A3000.h b/include/configs/A3000.h deleted file mode 100644 index ca9592c..0000000 --- a/include/configs/A3000.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * (C) Copyright 2001, 2002, 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ -/* - * Configuration settings for the A-3000 board (Artis Microsystems Inc.). - * http://artismicro.com - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_A3000 1 - - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_BOOTDELAY 5 - -#if 0 -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BSP | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_FLASH | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_NET | \ - CFG_CMD_PCI ) -#endif - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ - -#include - - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "A3000> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) -#define CFG_MAXARGS 8 /* Max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00400000 /* Default load address */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -/* #define CONFIG_TULIP */ -/* #define CONFIG_EEPRO100 */ -#define CONFIG_NATSEMI - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 -#define PCI_ENET2_IOADDR 0x82000000 -#define PCI_ENET2_MEMADDR 0x82000000 -#define PCI_ENET3_IOADDR 0x83000000 -#define PCI_ENET3_MEMADDR 0x83000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -#define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ -#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ -#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM -#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM } - -/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the - * reset vector is actually located at FFB00100, but the 8245 - * takes care of us. - */ -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_EUMB_ADDR 0xFC000000 - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CFG_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */ - - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#undef CFG_RAMBOOT -#else -#define CFG_RAMBOOT -#endif - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* #define CFG_MONITOR_BASE TEXT_BASE */ -/*#define CFG_GBL_DATA_SIZE 256*/ -#define CFG_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CFG_HZ 1000 - - /* Bit-field values for MCCR1. - */ -#define CFG_ROMNAL 7 -#define CFG_ROMFAL 11 -#define CFG_DBUS_SIZE 0x3 - - /* Bit-field values for MCCR2. - */ -#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CFG_BSTOPRE 121 - - /* Bit-field values for MCCR3. - */ -#define CFG_REFREC 8 /* Refresh to activate interval */ - - /* Bit-field values for MCCR4. - */ -#define CFG_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ -#define CFG_ACTORW 3 /* FIXME was 2 */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 1 -#define CFG_REGDIMM 0 - -#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ - -#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff -#define CFG_BANK7_ENABLE 0 - -#define CFG_ODCR 0xff - -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors per flash */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0xFFFE0000 -#define CFG_ENV_SIZE 0x00020000 /* Size of the Environment */ -#define CFG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h deleted file mode 100644 index 821efe5..0000000 --- a/include/configs/ADCIOP.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_IOP480 1 /* This is a IOP480 CPU */ -#define CONFIG_ADCIOP 1 /* ...on a ADCIOP board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_CPUCLOCK 66 -#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK) - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ - -#undef CONFIG_BOOTARGS - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_IPADDR 10.0.18.222 -#define CONFIG_SERVERIP 10.0.18.190 - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_ASKENV ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFD0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0002 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0000 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0004 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 1 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CFG_NVRAM_BASE_ADDR 0x10000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_ENV_SIZE 0x0400 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ -#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/ - -#else /* Use FLASH for environment variables */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ - -#define CFG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */ - -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_TULIP - -#define CFG_ETH_DEV_FN 0x0000 -#define CFG_ETH_IOBASE 0x0fff0000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ -#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFE00000 /* FLASH bank #1 */ - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h deleted file mode 100644 index 2efca10..0000000 --- a/include/configs/ADNPESC1.h +++ /dev/null @@ -1,694 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************************** - * Include the whole NIOS CPU configuration. - * - * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! - * - ***********************************************************************/ - -#if defined(CONFIG_NIOS_BASE_32) -#include -#else -#error *** CFG_ERROR: you have to setup right NIOS CPU configuration -#endif - -/*------------------------------------------------------------------------ - * BOARD/CPU -- TOP-LEVEL - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS 1 /* NIOS-32 core */ -#define CONFIG_ADNPESC1 1 /* SSV ADNP/ESC1 board */ -#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */ -#define CFG_HZ 1000 /* 1 msec time tick */ -#undef CFG_CLKS_IN_HZ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_SDRAM_SIZE != 0) - -#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE -#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE - -#else -#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config -#endif - -#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE) - -#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE -#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE - -#else - -#undef CFG_SRAM_BASE -#undef CFG_SRAM_SIZE - -#endif - -#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - For the most part, you can put things pretty - * much anywhere. This is pretty flexible for Nios. So here we make some - * arbitrary choices & assume that the monitor is placed at the end of - * a memory resource (so you must make sure TEXT_BASE is chosen - * appropriately -- this is very important if you plan to move your - * memory to another place as configured at this time !!!). - * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP CFG_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_FLASH_SIZE != 0) - -#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE -#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE -#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size */ - -#else -#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * ENVIRONMENT - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_FLASH_SIZE != 0) - -#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ - -/* Mem addr of environment */ -#if defined(CONFIG_NIOS_BASE_32) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) -#else -#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR -#endif - -#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ - -#else -#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */ -#endif - -/*------------------------------------------------------------------------ - * NIOS APPLICATION CODE BASE AREA - *----------------------------------------------------------------------*/ -#if ((CFG_ENV_ADDR + CFG_ENV_SIZE) == 0x1050000) -#define CFG_ADNPESC1_UPDATE_LOAD_ADDR "0x2000100" -#define CFG_ADNPESC1_NIOS_APPL_ENTRY "0x1050000" -#define CFG_ADNPESC1_NIOS_APPL_IDENT "0x105000c" -#define CFG_ADNPESC1_NIOS_APPL_END "0x11fffff" -#define CFG_ADNPESC1_FILESYSTEM_BASE "0x1200000" -#define CFG_ADNPESC1_FILESYSTEM_END "0x17fffff" -#else -#error *** CFG_ERROR: missing right appl.code base configuration, expand your config.h -#endif -#define CFG_ADNPESC1_NIOS_IDENTIFIER "Nios" - -/*------------------------------------------------------------------------ - * BOOT ENVIRONMENT - *----------------------------------------------------------------------*/ -#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ -#define CFG_ADNPESC1_SLED_BOOT_OFF "sled boot off; " -#define CFG_ADNPESC1_SLED_RED_BLINK "sled red blink; " -#else -#define CFG_ADNPESC1_SLED_BOOT_OFF -#define CFG_ADNPESC1_SLED_RED_BLINK -#endif - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTCOMMAND \ - "if itest.s *$appl_ident_addr == \"$appl_ident_str\"; " \ - "then " \ - "wd off; " \ - CFG_ADNPESC1_SLED_BOOT_OFF \ - "go $appl_entry_addr; " \ - "else " \ - CFG_ADNPESC1_SLED_RED_BLINK \ - "echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\ - "echo *** invalid application at $appl_entry_addr; " \ - "echo *** stop bootup...; " \ - "fi" - -/*------------------------------------------------------------------------ - * EXTRA ENVIRONMENT - *----------------------------------------------------------------------*/ -#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ -#define CFG_ADNPESC1_SLED_YELLO_ON "sled yellow on; " -#define CFG_ADNPESC1_SLED_YELLO_OFF "sled yellow off; " -#else -#define CFG_ADNPESC1_SLED_YELLO_ON -#define CFG_ADNPESC1_SLED_YELLO_OFF -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_allowed=0\0" \ - "update_load_addr=" CFG_ADNPESC1_UPDATE_LOAD_ADDR "\0" \ - "appl_entry_addr=" CFG_ADNPESC1_NIOS_APPL_ENTRY "\0" \ - "appl_end_addr=" CFG_ADNPESC1_NIOS_APPL_END "\0" \ - "appl_ident_addr=" CFG_ADNPESC1_NIOS_APPL_IDENT "\0" \ - "appl_ident_str=" CFG_ADNPESC1_NIOS_IDENTIFIER "\0" \ - "appl_name=ADNPESC1/base32/linux.bin\0" \ - "appl_update=" \ - "if itest.b $update_allowed != 0; " \ - "then " \ - CFG_ADNPESC1_SLED_YELLO_ON \ - "tftp $update_load_addr $appl_name; " \ - "protect off $appl_entry_addr $appl_end_addr; " \ - "era $appl_entry_addr $appl_end_addr; " \ - "cp.b $update_load_addr $appl_entry_addr $filesize; "\ - CFG_ADNPESC1_SLED_YELLO_OFF \ - "else " \ - "echo *** update not allowed (update_allowed=$update_allowed); "\ - "fi\0" \ - "fs_base_addr=" CFG_ADNPESC1_FILESYSTEM_BASE "\0" \ - "fs_end_addr=" CFG_ADNPESC1_FILESYSTEM_END "\0" \ - "fs_name=ADNPESC1/base32/romfs.img\0" \ - "fs_update=" \ - "if itest.b $update_allowed != 0; " \ - "then " \ - CFG_ADNPESC1_SLED_YELLO_ON \ - "tftp $update_load_addr $fs_name; " \ - "protect off $fs_base_addr $fs_end_addr; " \ - "era $fs_base_addr $fs_end_addr; " \ - "cp.b $update_load_addr $fs_base_addr $filesize; "\ - CFG_ADNPESC1_SLED_YELLO_OFF \ - "else " \ - "echo *** update not allowed (update_allowed=$update_allowed); "\ - "fi\0" \ - "uboot_name=ADNPESC1/base32/u-boot.bin\0" \ - "uboot_loadnrun=" \ - "if ping $serverip; " \ - "then " \ - CFG_ADNPESC1_SLED_YELLO_ON \ - "tftp $update_load_addr $uboot_name; " \ - "wd off; " \ - "go $update_load_addr; " \ - "else " \ - "echo *** missing connection to $serverip; " \ - "echo *** check your network and try again...; "\ - "fi\0" - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_UART_NUMS != 0) - -#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */ - -#if (CFG_NIOS_CPU_UART0_BR != 0) -#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR -#else -#undef CFG_NIOS_FIXEDBAUD -#define CONFIG_BAUDRATE 115200 -#endif - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#else -#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, - * so an avalon bus timer is required. - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER) - -#if (CFG_NIOS_CPU_TICK_TIMER == 0) - -#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */ -#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ - -#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ - -#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ) -#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ) -#else -#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ -#endif - -#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */ - -#if (CFG_HZ <= 1000) -#define CFG_NIOS_TMRMS (1000 / CFG_HZ) -#else -#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 -#endif - -#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) - -#else -#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct -#endif - -#elif (CFG_NIOS_CPU_TICK_TIMER == 1) - -#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */ -#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ - -#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ - -#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ) -#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ) -#else -#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ -#endif - -#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */ - -#if (CFG_HZ <= 1000) -#define CFG_NIOS_TMRMS (1000 / CFG_HZ) -#else -#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 -#endif - -#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) - -#else -#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct -#endif - -#endif /* CFG_NIOS_CPU_TICK_TIMER */ - -#else -#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * WATCHDOG (or better MAX823 supervisory circuite access) - *----------------------------------------------------------------------*/ -#define CONFIG_HW_WATCHDOG 1 /* board specific WD */ - -#ifdef CONFIG_HW_WATCHDOG - -/* MAX823 supervisor -- watchdog enable port at: */ -#if (CFG_NIOS_CPU_WDENA_PIO == 0) -#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */ -#elif (CFG_NIOS_CPU_WDENA_PIO == 1) -#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */ -#elif (CFG_NIOS_CPU_WDENA_PIO == 2) -#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */ -#elif (CFG_NIOS_CPU_WDENA_PIO == 3) -#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */ -#elif (CFG_NIOS_CPU_WDENA_PIO == 4) -#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */ -#elif (CFG_NIOS_CPU_WDENA_PIO == 5) -#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */ -#elif (CFG_NIOS_CPU_WDENA_PIO == 6) -#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */ -#elif (CFG_NIOS_CPU_WDENA_PIO == 7) -#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */ -#elif (CFG_NIOS_CPU_WDENA_PIO == 8) -#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */ -#elif (CFG_NIOS_CPU_WDENA_PIO == 9) -#define CONFIG_HW_WDENA_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */ -#else -#error *** CFG_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config -#endif - -/* MAX823 supervisor -- watchdog trigger port at: */ -#if (CFG_NIOS_CPU_WDTOG_PIO == 0) -#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO0 /* PIO0 */ -#elif (CFG_NIOS_CPU_WDTOG_PIO == 1) -#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO1 /* PIO1 */ -#elif (CFG_NIOS_CPU_WDTOG_PIO == 2) -#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO2 /* PIO2 */ -#elif (CFG_NIOS_CPU_WDTOG_PIO == 3) -#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO3 /* PIO3 */ -#elif (CFG_NIOS_CPU_WDTOG_PIO == 4) -#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO4 /* PIO4 */ -#elif (CFG_NIOS_CPU_WDTOG_PIO == 5) -#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO5 /* PIO5 */ -#elif (CFG_NIOS_CPU_WDTOG_PIO == 6) -#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO6 /* PIO6 */ -#elif (CFG_NIOS_CPU_WDTOG_PIO == 7) -#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO7 /* PIO7 */ -#elif (CFG_NIOS_CPU_WDTOG_PIO == 8) -#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO8 /* PIO8 */ -#elif (CFG_NIOS_CPU_WDTOG_PIO == 9) -#define CONFIG_HW_WDTOG_BASE CFG_NIOS_CPU_PIO9 /* PIO9 */ -#else -#error *** CFG_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config -#endif - -#if defined(CONFIG_NIOS_BASE_32) /* NIOS CPU specifics */ -#define CONFIG_HW_WDENA_BIT 0 /* WD enable @ Bit 0 */ -#define CONFIG_HW_WDTOG_BIT 0 /* WD trigger @ Bit 0 */ -#define CONFIG_HW_WDPORT_WRONLY 1 /* each WD port wr/only*/ -#else -#error *** CFG_ERROR: missing watchdog bit configuration, expand your config.h -#endif - -#endif /* CONFIG_HW_WATCHDOG */ - -/*------------------------------------------------------------------------ - * SERIAL PERIPHAREL INTERFACE - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_SPI_NUMS == 1) - -#define CONFIG_NIOS_SPI 1 /* SPI support active */ -#define CFG_NIOS_SPIBASE CFG_NIOS_CPU_SPI0 -#define CFG_NIOS_SPIBITS CFG_NIOS_CPU_SPI0_BITS - -#define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */ -#define CFG_SPI_RTC_DEVID 0 /* as 1st SPI device */ - -#define __SPI_CMD_OFF 0 /* allow default commands: */ - /* CFG_CMD_SPI */ - /* CFG_CMD_DATE */ - -#else -#undef CONFIG_NIOS_SPI /* NO SPI support */ -#define __SPI_CMD_OFF ( CFG_CMD_SPI \ - | CFG_CMD_DATE \ - ) -#endif - -/*------------------------------------------------------------------------ - * Ethernet -- needs work! - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_LAN_NUMS == 1) - -#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) - -#if (CFG_NIOS_CPU_LAN0_BUSW == 32) -#define CONFIG_SMC_USE_32_BIT 1 -#else /* no */ -#undef CONFIG_SMC_USE_32_BIT -#endif - -#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ - - /********************************************/ - /* !!! CS8900 is __not__ tested on NIOS !!! */ - /********************************************/ -#define CONFIG_DRIVER_CS8900 /* Using CS8900 */ -#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) - -#if (CFG_NIOS_CPU_LAN0_BUSW == 32) -#undef CS8900_BUS16 -#define CS8900_BUS32 1 -#else /* no */ -#define CS8900_BUS16 1 -#undef CS8900_BUS32 -#endif - -#else -#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config -#endif - -#define CONFIG_ETHADDR 02:80:ae:20:60:6f -#define CONFIG_NETMASK 255.255.255.248 -#define CONFIG_IPADDR 192.168.161.84 -#define CONFIG_SERVERIP 192.168.161.85 - -#else -#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h -#endif - -/*------------------------------------------------------------------------ - * STATUS LEDs - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO) - -#if (CFG_NIOS_CPU_LED_PIO == 0) - -#define STATUS_LED_BASE CFG_NIOS_CPU_PIO0 -#define STATUS_LED_BITS CFG_NIOS_CPU_PIO0_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CFG_NIOS_CPU_PIO0_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CFG_NIOS_CPU_LED_PIO == 1) - -#define STATUS_LED_BASE CFG_NIOS_CPU_PIO1 -#define STATUS_LED_BITS CFG_NIOS_CPU_PIO1_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CFG_NIOS_CPU_PIO1_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CFG_NIOS_CPU_LED_PIO == 2) - -#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2 -#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CFG_NIOS_CPU_PIO2_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CFG_NIOS_CPU_LED_PIO == 3) - -#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 4) - -#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 5) - -#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 6) - -#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 7) - -#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 8) - -#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 9) - -#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h - -#else -#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case -#endif - -#define CONFIG_STATUS_LED 1 /* enable status led driver */ - -#define STATUS_LED_BIT (1 << 0) /* LED[0] */ -#define STATUS_LED_STATE STATUS_LED_BLINKING -#define STATUS_LED_BOOT_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CFG_HZ / 2) /* ca. 1 Hz */ -#define STATUS_LED_BOOT 0 /* boot LED */ - -#if (STATUS_LED_BITS > 1) -#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CFG_HZ / 10) /* ca. 5 Hz */ -#define STATUS_LED_RED 1 /* fail LED */ -#endif - -#if (STATUS_LED_BITS > 2) -#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CFG_HZ / 2) /* ca. 1 Hz */ -#define STATUS_LED_YELLOW 2 /* info LED */ -#endif - -#if (STATUS_LED_BITS > 3) -#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ -#define STATUS_LED_STATE3 STATUS_LED_OFF -#define STATUS_LED_PERIOD3 (CFG_HZ / 2) /* ca. 1 Hz */ -#define STATUS_LED_GREEN 3 /* info LED */ -#endif - -#define STATUS_LED_PAR 1 /* makes status_led.h happy */ - -#endif /* CFG_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * Diagnostics / Power On Self Tests - *----------------------------------------------------------------------*/ -#define CONFIG_POST CFG_POST_RTC -#define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_CACHE | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGDB | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_MMC | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_SCSI | \ - CFG_CMD_VFD | \ - CFG_CMD_USB | \ - CFG_CMD_XIMG | \ - __SPI_CMD_OFF ) ) - - -#include - -/*------------------------------------------------------------------------ - * KGDB - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 9600 -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_HUSH_PARSER 1 /* use "hush" command parser - undef to save memory */ -#define CFG_PROMPT "ADNPESC1 > " /* Monitor Command Prompt */ -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 64 /* max number of command args*/ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "[]> " -#endif - -/* Default load address */ -#if (CFG_SRAM_SIZE != 0) - -/* default in SRAM */ -#define CFG_LOAD_ADDR CFG_SRAM_BASE - -#elif (CFG_SDRAM_SIZE != 0) - -/* default in SDRAM */ -#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) -#if 1 -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) -#else -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x400000) -#endif -#else -#define CFG_LOAD_ADDR CFG_SDRAM_BASE -#endif - -#else -#undef CFG_LOAD_ADDR /* force error break */ -#endif - - -/* MEM test area */ -#if (CFG_SDRAM_SIZE != 0) - -/* SDRAM begin to stack area (1MB stack) */ -#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) -#if 0 -#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) -#else -#define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x400000) -#endif -#else -#define CFG_MEMTEST_START CFG_SDRAM_BASE -#endif - -#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) -#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) - -#else -#undef CFG_MEMTEST_START /* force error break */ -#undef CFG_MEMTEST_END -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h deleted file mode 100644 index 55210eb..0000000 --- a/include/configs/ADNPESC1_base_32.h +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2004, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_ADNPESC1_BASE_32_H -#define __CONFIG_ADNPESC1_BASE_32_H - -/* - * NIOS CPU configuration. (PART OF configs/ADNPESC1.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be undefined or defined with zero, example CPU without data cache / OCI: - * - * #define CFG_NIOS_CPU_ICACHE 4096 - * #define CFG_NIOS_CPU_DCACHE 0 - * #undef CFG_NIOS_CPU_OCI_BASE - * #undef CFG_NIOS_CPU_OCI_SIZE - */ - -/* CPU core */ -#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CFG_NIOS_CPU_ICACHE (0) /* instruction cache */ -#define CFG_NIOS_CPU_DCACHE (0) /* data cache */ -#define CFG_NIOS_CPU_REG_NUMS 512 /* number of register */ -#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_STACK 0x03000000 /* stack top addr */ -#define CFG_NIOS_CPU_VEC_BASE 0x02000000 /* IRQ vectors addr */ -#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CFG_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ -#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* The offset address in flash to check for the Nios signature "Ni". - * (see GM_FlashExec in germs_monitor.s) */ -#define CFG_NIOS_CPU_EXES_OFFS 0x0C - -/* on-chip extensions */ -#undef CFG_NIOS_CPU_RAM_BASE /* on chip RAM addr */ -#undef CFG_NIOS_CPU_RAM_SIZE /* 64 KB size */ - -#define CFG_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ -#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#undef CFG_NIOS_CPU_OCI_BASE /* OCI core addr */ -#undef CFG_NIOS_CPU_OCI_SIZE /* size */ - -/* timer */ -#define CFG_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ - -#define CFG_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ -#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CFG_NIOS_CPU_UART_NUMS 2 /* number of uarts */ - -#define CFG_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ -#define CFG_NIOS_CPU_UART0_IRQ 17 /* IRQ */ -#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CFG_NIOS_CPU_UART0_HS 1 /* handshake: no(0) */ - /* crts(1) */ -#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -#define CFG_NIOS_CPU_UART1 0x00000820 /* UART1 addr */ -#define CFG_NIOS_CPU_UART1_IRQ 18 /* IRQ */ -#define CFG_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ -#define CFG_NIOS_CPU_UART1_DB 8 /* data bit */ -#define CFG_NIOS_CPU_UART1_SB 1 /* stop bit */ -#define CFG_NIOS_CPU_UART1_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CFG_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CFG_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* serial peripheral i/o */ -#define CFG_NIOS_CPU_SPI_NUMS 1 /* number of spis */ - -#define CFG_NIOS_CPU_SPI0 0x000008c0 /* SPI0 addr */ -#define CFG_NIOS_CPU_SPI0_IRQ 25 /* IRQ */ -#define CFG_NIOS_CPU_SPI0_BITS 16 /* data bit */ -#define CFG_NIOS_CPU_SPI0_MA 1 /* is master: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_SPI0_SLN 1 /* num slaves */ -#define CFG_NIOS_CPU_SPI0_TCLK 250000 /* clock (Hz) */ -#define CFG_NIOS_CPU_SPI0_TDELAY 2 /* delay (usec) */ -#define CFG_NIOS_CPU_SPI0_FB 0 /* first bit msb(0) */ - /* lsb(1) */ - -/* parallel i/o */ -#define CFG_NIOS_CPU_PIO_NUMS 14 /* number of parports */ - -#define CFG_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ -#undef CFG_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO0_BITS 8 /* number of bits */ -#define CFG_NIOS_CPU_PIO0_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ -#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO1_BITS 8 /* number of bits */ -#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO2 0x00000880 /* PIO2 addr */ -#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO2_BITS 4 /* number of bits */ -#define CFG_NIOS_CPU_PIO2_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */ -#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO3_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO3 0x00000890 /* PIO3 addr */ -#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO3_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO3_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO4 0x000008a0 /* PIO4 addr */ -#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO4_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO5 0x000008b0 /* PIO5 addr */ -#undef CFG_NIOS_CPU_PIO5_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO5_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO5_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO5_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO5_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO6 0x00000900 /* PIO6 addr */ -#define CFG_NIOS_CPU_PIO6_IRQ 20 /* IRQ */ -#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO6_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO6_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO6_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO6_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO7 0x00000910 /* PIO7 addr */ -#define CFG_NIOS_CPU_PIO7_IRQ 31 /* IRQ */ -#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO7_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO7_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO7_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO7_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO8 0x00000920 /* PIO8 addr */ -#define CFG_NIOS_CPU_PIO8_IRQ 32 /* IRQ */ -#define CFG_NIOS_CPU_PIO8_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO8_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO8_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO8_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO8_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO9 0x00000930 /* PIO9 addr */ -#define CFG_NIOS_CPU_PIO9_IRQ 33 /* IRQ */ -#define CFG_NIOS_CPU_PIO9_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO9_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO9_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO9_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO9_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO10 0x00000940 /* PIO10 addr */ -#define CFG_NIOS_CPU_PIO10_IRQ 34 /* IRQ */ -#define CFG_NIOS_CPU_PIO10_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO10_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO10_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO10_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO10_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO11 0x00000950 /* PIO11 addr */ -#define CFG_NIOS_CPU_PIO11_IRQ 35 /* IRQ */ -#define CFG_NIOS_CPU_PIO11_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO11_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO11_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO11_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO11_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO12 0x00000960 /* PIO12 addr */ -#define CFG_NIOS_CPU_PIO12_IRQ 36 /* IRQ */ -#define CFG_NIOS_CPU_PIO12_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO12_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO12_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO12_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO12_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO13 0x00000970 /* PIO113 addr */ -#define CFG_NIOS_CPU_PIO13_IRQ 37 /* IRQ */ -#define CFG_NIOS_CPU_PIO13_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO13_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO13_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO13_EDGE 2 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO13_ITYPE 1 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CFG_NIOS_CPU_IDE_NUMS 2 /* number of IDE contr. */ - -#define CFG_NIOS_CPU_IDE0 0x00001000 /* IDE0 addr */ -#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */ - -#define CFG_NIOS_CPU_IDE1 0x00001020 /* IDE1 addr */ -#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */ - -/* memory accessibility */ -#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ -#undef CFG_NIOS_CPU_SRAM_SIZE /* 1 MB size */ - -#define CFG_NIOS_CPU_SDRAM_BASE 0x02000000 /* board SDRAM addr */ -#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CFG_NIOS_CPU_FLASH_BASE 0x01000000 /* board Flash addr */ -#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CFG_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ -#define CFG_NIOS_CPU_LAN0_OFFS (0) /* offset */ -#define CFG_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ -#define CFG_NIOS_CPU_LAN0_BUSW 16 /* buswidth*/ -#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: openmac(2) */ - /* ex: alteramac(3) */ - -/* external extension */ -#define CFG_NIOS_CPU_CS0_BASE 0x40000000 /* board EXT0 addr */ -#define CFG_NIOS_CPU_CS0_SIZE (16*1024*1024) /* max. 16 MB size */ - -#define CFG_NIOS_CPU_CS1_BASE 0x41000000 /* board EXT1 addr */ -#define CFG_NIOS_CPU_CS1_SIZE (16*1024*1024) /* max. 16 MB size */ - -#define CFG_NIOS_CPU_CS2_BASE 0x42000000 /* board EXT2 addr */ -#define CFG_NIOS_CPU_CS2_SIZE (16*1024*1024) /* max. 16 MB size */ - -#define CFG_NIOS_CPU_CS3_BASE 0x43000000 /* board EXT3 addr */ -#define CFG_NIOS_CPU_CS3_SIZE (16*1024*1024) /* max. 16 MB size */ - -/* symbolic redefinition (undef, if not present) */ -#define CFG_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ -#undef CFG_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ - -#define CFG_NIOS_CPU_PORTA_PIO 0 /* PIO0: Port A */ -#define CFG_NIOS_CPU_PORTB_PIO 1 /* PIO1: Port D */ -#define CFG_NIOS_CPU_PORTC_PIO 2 /* PIO2: Port C */ -#define CFG_NIOS_CPU_RCM_PIO 3 /* PIO3: RCM jumper */ -#define CFG_NIOS_CPU_WDENA_PIO 4 /* PIO4: watchdog enable*/ -#define CFG_NIOS_CPU_WDTOG_PIO 5 /* PIO5: watchdog trigg.*/ - -/* PIOx: LED bar */ -#ifdef CONFIG_DNPEVA2 /* DNP/EVA2 base board */ -#define CFG_NIOS_CPU_LED_PIO CFG_NIOS_CPU_PORTA_PIO -#else -#undef CFG_NIOS_CPU_LED_PIO /* no LED bar */ -#endif - -#endif /* __CONFIG_ADNPESC1_BASE_32_H */ diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h deleted file mode 100644 index df20965..0000000 --- a/include/configs/ADS860.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola 860 ADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * Values common to all FADS family boards are in board/fads/fads.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board type */ -#define CONFIG_ADS 1 /* Old Motorola MPC821/860ADS */ - -/* Processor type */ -#define CONFIG_MPC860 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 38400 /* Console baudrate */ - -#if 0 -#define CFG_8XX_FACT 1526 /* 32.768 kHz crystal on XTAL/EXTAL */ -#else -#define CFG_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ -#endif - -#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -#define CONFIG_DRAM_50MHZ 1 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_PCMCIA \ - | CFG_CMD_PING \ - ) - - -#include "fads.h" - -#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h deleted file mode 100644 index 14d56bf..0000000 --- a/include/configs/AMX860.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_AMX860 1 - -#undef CONFIG_8xx_CONS_SMC1 /* Console is on SCC2 */ -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_8xx_CONS_SCC2 1 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 5000000 /* 5 MHz in */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" /* autoboot command */ - -#undef CONFIG_BOOTARGS - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * U-Boot for AMX board supports two types of memory extension - * modules: one that provides 4 MB flash memory, and another one with - * 16 MB EDO DRAM. - * - * The flash module swaps the CS0 and CS1 signals: if the module is - * installed, CS0 is connected to Flash on the module and CS1 is - * connected to the on-board Flash. This means that you must intall - * U-Boot when the Flash module is plugged in, if you plan to use - * it. - * - * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT - * must be defined. The DRAM module uses CS1. - * - * Only one of these modules may be installed at a time. If U-Boot - * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not - * work if the Flash extension module is installed instead of the - * DRAM module. - */ -#define CONFIG_AMX_RAM_EXT /* 16Mb Ext. DRAM module support */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - * - * Use 4 MB for without and 8 MB with 16 MB DRAM extension module - * (CONFIG_AMX_RAM_EXT) - */ -#ifdef CONFIG_AMX_RAM_EXT -# define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#else -# define CFG_BOOTMAPSZ (4 << 20) /* Initial Memory map for Linux */ -#endif -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#ifndef CONFIG_AMX_RAM_EXT -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ -#endif - -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -/* 0x00000800 0x00000400 0x00000100 0x00000030 0x00000004 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) - -#define CFG_OR0_PRELIM 0xFFC00954 /* Real values for the board */ -#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */ - -#ifndef CONFIG_AMX_RAM_EXT -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM 0xFFC00954 /* Real values for the board */ -#define CFG_BR1_PRELIM 0x60000001 /* Real values for the board */ -#endif - -/* DSP ("Glue") Xilinx */ -#define CFG_OR6_PRELIM 0xFFFF8000 /* 32kB, 15 waits, cs after addr, no bursts */ -#define CFG_BR6_PRELIM 0x60000401 /* use GPCM for CS generation, 8 bit port */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h deleted file mode 100644 index ba4b1a2..0000000 --- a/include/configs/AP1000.h +++ /dev/null @@ -1,249 +0,0 @@ -/* - * AMIRIX.h: AMIRIX specific config options - * - * Author : Frank Smith (smith at amirix dot com) - * - * Derived from : other configuration header files in this tree - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#undef DEBUG - -#define CONFIG_405 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ - -#define CONFIG_AP1000 1 /* ...on an AP1000 board */ - -#define CONFIG_PCI 1 - -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#define CFG_PROMPT "0> " -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CONFIG_COMMAND_EDIT 1 -#define CONFIG_COMMAND_HISTORY 1 -#define CONFIG_COMPLETE_ADDRESSES 1 - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_FLASH_USE_BUFFER_WRITE - -#ifdef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#else -#ifdef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#endif -#endif - -#define CONFIG_BAUDRATE 57600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_BOOTCOMMAND "" /* autoboot command */ - -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO - -#define CONFIG_BOOTARGS "console=ttyS0,57600" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_IRQ | \ - CFG_CMD_MVENV | \ - CFG_CMD_PCI | \ - CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SYS_CLK_FREQ 30000000 - -#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -/* usually: (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) */ -#define CFG_PBSIZE (CFG_CBSIZE+4+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_ALT_MEMTEST 1 -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */ - -/* - * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CFG_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - */ -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ - -#define CFG_NS16550_CLK 40000000 -#define CFG_DUART_CHAN 0 -#define CFG_NS16550_COM1 (0x4C000000 + 0x1000) -#define CFG_NS16550_COM2 (0x4C800000 + 0x1000) -#define CFG_NS16550_REG_SIZE 4 -#define CFG_NS16550 1 -#define CFG_INIT_CHAN1 1 -#define CFG_INIT_CHAN2 0 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x00200000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x20000000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_CFI 1 -#define CFG_PROGFLASH_BASE CFG_FLASH_BASE -#define CFG_CONFFLASH_BASE 0x24000000 - -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ - -/* BEG ENVIRONNEMENT FLASH */ -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* see README - env sector total size */ -#endif -/* END ENVIRONNEMENT FLASH */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ - -#ifdef CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -#define CFG_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* JFFS2 stuff */ - -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS 1 -#define CFG_JFFS2_FIRST_SECTOR 1 - -#define CONFIG_NET_MULTI -#define CONFIG_E1000 - -#define CFG_ETH_DEV_FN 0x0800 -#define CFG_ETH_IOBASE 0x31000000 -#define CFG_ETH_MEMBASE 0x32000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/APC405.h b/include/configs/APC405.h deleted file mode 100644 index 3df99a0..0000000 --- a/include/configs/APC405.h +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_APCG405 1 /* ...on a APC405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000 ffca0000" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000" -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#if 1 /* test-only */ -#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ -#else -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#endif - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/* Only interrupt boot if space is pressed */ -/* If a long serial cable is connected but */ -/* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MONITOR_BASE 0xFFF80000 -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_BASE 0xFE000000 /* test-only...*/ -#define CFG_FLASH_INCREMENT 0x01000000 /* test-only */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ -#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ -#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define PS2_BA 0xF0000600 /* PS/2 Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ -#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */ -#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */ -#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */ -#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */ -#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ - -#define CFG_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */ -#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (PCMCIA Slot 1) initialization */ -#define CFG_EBC_PB4AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB4CR PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 5 (Epson VGA) initialization */ -#define CFG_EBC_PB5AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ -#define CFG_EBC_PB5CR VGA_BA | 0x5A000 /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 6 (PCMCIA Slot 2) initialization */ -#define CFG_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ - -/* FPGA internal regs */ -#define CFG_FPGA_CTRL 0x008 -#define CFG_FPGA_CTRL2 0x00a - -/* FPGA Control Reg */ -#define CFG_FPGA_CTRL_CF_RESET 0x0001 -#define CFG_FPGA_CTRL_WDI 0x0002 -#define CFG_FPGA_CTRL_PS2_RESET 0x0020 - -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 80*1024 /* 80kByte is enough for XC2S50 */ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * LCD Setup - */ - -#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ -#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ - -#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */ - -/* Image information... */ -#define CONFIG_LCD_USED CONFIG_LCD_BIG -#define CFG_LCD_HEADER_NAME "../common/s1d13806_640_480_16bpp.h" -#define CFG_LCD_LOGO_NAME "logo_640_480_24bpp.c" - -#define CFG_LCD_MEM CFG_LCD_BIG_MEM -#define CFG_LCD_REG CFG_LCD_BIG_REG - -#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/AR405.h b/include/configs/AR405.h deleted file mode 100644 index 1cd0280..0000000 --- a/include/configs/AR405.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_AR405 1 /* ...on a AR405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#if 1 -#define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */ -#else -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ -#endif - -#if 0 -#define CONFIG_BOOTARGS "root=/dev/nfs " \ - "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ - "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4" -#else -#define CONFIG_BOOTARGS "root=/dev/hda1 " \ - "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0" - -#endif - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_BSP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xfff00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xfff00001 /* 1MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0xFFFB0000 /* Address of Environment Sector*/ -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ -#define CFG_ENV_SIZE 0x04000 /* Size of Environment */ - -#define CFG_ENV_ADDR_REDUND 0xFFFA0000 -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (CAN0, 1, 2, 3) initialization */ -#define CFG_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */ -#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Expension Bus) initialization */ -#define CFG_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */ -#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16552) initialization */ -#define CFG_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */ -#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (FPGA regs) initialization */ -#define CFG_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */ -#define CFG_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */ - -/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */ -#define CFG_EBC_PB5AP 0x92015480 -#define CFG_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h deleted file mode 100644 index 9841893..0000000 --- a/include/configs/ASH405.h +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_ASH405 1 /* ...on a ASH405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define DUART2_BA 0xF0000410 /* DUART Base Address */ -#define DUART3_BA 0xF0000418 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define CFG_NAND_BASE 0xF4000000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CFG_GPIO0_OSRH 0x40000550 -#define CFG_GPIO0_OSRL 0x00000110 -#define CFG_GPIO0_ISR1H 0x00000000 -#define CFG_GPIO0_ISR1L 0x15555445 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FE0014 - -#define CFG_DUART_RST (0x80000000 >> 14) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/Adder.h b/include/configs/Adder.h deleted file mode 100644 index f807546..0000000 --- a/include/configs/Adder.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Analogue&Micro Adder boards family. - * Tested on AdderII and Adder87x. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T) -#define CONFIG_MPC875 -#endif - -#define CONFIG_ADDER /* Analogue&Micro Adder board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_FEC_ENET /* Ethernet is on FEC */ -#ifdef CONFIG_FEC_ENET -#define CFG_DISCOVER_PHY -#define FEC_ENET -#endif /* CONFIG_FEC_ENET */ - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 -#define CFG_8xx_CPUCLK_MIN 40000000 -#ifdef CONFIG_MPC852T -#define CFG_8xx_CPUCLK_MAX 50000000 -#else -#define CFG_8xx_CPUCLK_MAX 120000000 -#endif /* CONFIG_MPC852T */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS */ -#include - -#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* #undef to save memory */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* Max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x100000 /* Default load address */ - -#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * RAM configuration (note that CFG_SDRAM_BASE must be zero) - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ - -#define CFG_OR1_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2) -#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V) - -#define CFG_MAMR 0x00802114 - -/* - * 2048 SDRAM rows - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */ - -#define CFG_RESET_ADDRESS 0x09900000 - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 KB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ -#else -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * Flash organisation - */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ - -/* Environment is in flash */ -#define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) - -#define CFG_OR0_PRELIM 0xFF000774 -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) - -#define CFG_DIRECT_FLASH_TFTP - -/*----------------------------------------------------------------------- - * Internal Memory Map Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Configuration registers - */ -#ifdef CONFIG_WATCHDOG -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ - SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) - -/* TBSCR - Time Base Status and Control Register */ -#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) - -/* PISCR - Periodic Interrupt Status and Control */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/* PLPRCR - PLL, Low-Power, and Reset Control Register */ -/* #define CFG_PLPRCR PLPRCR_TEXPS */ - -/* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR SCCR_RTSEL - -#define CFG_DER 0 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */ - -/*----------------------------------------------------------------------- - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h deleted file mode 100644 index c08b2c3..0000000 --- a/include/configs/Alaska8220.h +++ /dev/null @@ -1,326 +0,0 @@ -/* - * (C) Copyright 2004 - * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC8220 1 -#define CONFIG_ALASKA8220 1 /* ... on Alaska board */ - -/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to - determine the CPU speed. */ -#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ -#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ - -/* Define this for PSC console -#define CONFIG_PSC_CONSOLE 1 -*/ - -#define CONFIG_EXTUART_CONSOLE 1 - -#ifdef CONFIG_EXTUART_CONSOLE -# define CONFIG_CONS_INDEX 1 -# define CFG_NS16550_SERIAL -# define CFG_NS16550 -# define CFG_NS16550_REG_SIZE 1 -# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008) -# define CFG_NS16550_CLK 18432000 -#endif - -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Supported commands - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CACHE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -#define CONFIG_NET_MULTI -#define CONFIG_MII - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTARGS "root=/dev/ram rw" -#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61 -#define CONFIG_IPADDR 192.162.1.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.162.1.1 -#define CONFIG_GATEWAYIP 192.162.1.1 -#define CONFIG_HOSTNAME Alaska -#define CONFIG_OVERWRITE_ETHADDR_ONCE - - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_MODULE 1 - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 -/* -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 256 -*/ - -/* If CFG_AMD_BOOT is defined, the the system will boot from AMD. - else undefined it will boot from Intel Strata flash */ -#define CFG_AMD_BOOT 1 - -/* - * Flexbus Chipselect configuration - */ -#if defined (CFG_AMD_BOOT) -#define CFG_CS0_BASE 0xfff0 -#define CFG_CS0_MASK 0x00080000 /* 512 KB */ -#define CFG_CS0_CTRL 0x003f0d40 - -#define CFG_CS1_BASE 0xfe00 -#define CFG_CS1_MASK 0x01000000 /* 16 MB */ -#define CFG_CS1_CTRL 0x003f1540 -#else -#define CFG_CS0_BASE 0xff00 -#define CFG_CS0_MASK 0x01000000 /* 16 MB */ -#define CFG_CS0_CTRL 0x003f1540 - -#define CFG_CS1_BASE 0xfe08 -#define CFG_CS1_MASK 0x00080000 /* 512 KB */ -#define CFG_CS1_CTRL 0x003f0d40 -#endif - -#define CFG_CS2_BASE 0xf100 -#define CFG_CS2_MASK 0x00040000 -#define CFG_CS2_CTRL 0x003f1140 - -#define CFG_CS3_BASE 0xf200 -#define CFG_CS3_MASK 0x00040000 -#define CFG_CS3_CTRL 0x003f1100 - - -#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) -#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16) - -#if defined (CFG_AMD_BOOT) -#define CFG_AMD_BASE CFG_FLASH0_BASE -#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000 -#define CFG_FLASH_BASE CFG_AMD_BASE -#else -#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000 -#define CFG_AMD_BASE CFG_FLASH1_BASE -#define CFG_FLASH_BASE CFG_INTEL_BASE -#endif - -#define CFG_CPLD_BASE (CFG_CS2_BASE << 16) -#define CFG_FPGA_BASE (CFG_CS3_BASE << 16) - - -#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ -#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */ - -#define CFG_FLASH_CHECKSUM -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#if defined (CFG_AMD_BOOT) -#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE) -#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE -#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE -#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE) -#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE -#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE -#else -#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE) -#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE -#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE -#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE) -#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE -#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE -#endif - -#define CONFIG_ENV_OVERWRITE 1 - -#if defined CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_EEPROM -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#endif - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 -#define CFG_SRAM_BASE (CFG_MBAR + 0x20000) -#define CFG_SRAM_SIZE 0x8000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) -#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* SDRAM configuration */ -#define CFG_SDRAM_TOTAL_BANKS 2 -#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */ -#define CFG_SDRAM_SPD_SIZE 0x40 -#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */ - -/* SDRAM drive strength register */ -#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \ - (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ - (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \ - (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \ - (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT)) - -/* - * Ethernet configuration - */ -#define CONFIG_MPC8220_FEC 1 -#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ -#define CONFIG_PHY_ADDR 0x18 - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition */ -/* -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0x00400000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 -*/ - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=alaska-0" -#define MTDPARTS_DEFAULT "mtdparts=alaska-0:4m(user)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h deleted file mode 100644 index ea50f41..0000000 --- a/include/configs/AmigaOneG3SE.h +++ /dev/null @@ -1,397 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the AmigaOneG3SE board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_AMIGAONEG3SE 1 - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_VERY_BIG_RAM 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passed to Linux in Hz */ - -#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=4096" - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_AMIGA_PARTITION - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_NET | \ - CFG_CMD_IDE | \ - CFG_CMD_FDC | \ - CFG_CMD_CACHE | \ - CFG_CMD_CONSOLE| \ - CFG_CMD_USB | \ - CFG_CMD_BSP | \ - CFG_CMD_PCI ) - -/* CFG_CMD_MII | \ */ - -#define CONFIG_PCI 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "] " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -/* #undef CFG_HUSH_PARSER */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - -#define CFG_MAXARGS 64 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00500000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF00000 -#define CFG_FLASH_MAX_SIZE 0x00080000 -/* Maximum amount of RAM. - */ -#define CFG_MAX_RAM_SIZE 0x80000000 /* 2G */ - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_MONITOR_LEN (768 << 10) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (2500 << 10) /* Reserve 128 kB for malloc() */ - -#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ - CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* Size in bytes reserved for initial data - */ -/* HJF: used to be 0x400000 */ -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x8000 -#define CFG_GBL_DATA_SIZE 128 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_INIT_RAM_LOCK - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR -#define CFG_SCONSOLE_SIZE 0x0002000 - -/* SDRAM 0 - 256MB - */ - -/*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_DBAT0U CFG_IBAT0U*/ - -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -/* PCI Range - */ -#define CFG_DBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) -/* HJF: -#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW) -#define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) -#define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP) -*/ - -/* Init RAM in the CPU DCache (no backing memory) - */ -#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -/* This used to be commented out */ -#define CFG_IBAT2L CFG_DBAT2L -/* This here too */ -#define CFG_IBAT2U CFG_DBAT2U - - -/* I/O and PCI memory at 0xf0000000 - */ -#define CFG_DBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - */ -#define CFG_HZ 1000 -#define CFG_BUS_HZ 133000000 /* bus speed - 100 mhz */ -#define CFG_CPU_CLK 133000000 -#define CFG_BUS_CLK 133000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 8 /* Max number of sectors in one bank */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -/* - * Environment is stored in NVRAM. - */ -#define CFG_ENV_IS_IN_NVRAM 1 -#define CFG_ENV_ADDR 0xFD0E0000 /* This should be 0xFD0E0000, but we skip bytes to - * protect softex's settings for now. - * Original 768 bytes where not enough. - */ -#define CFG_ENV_SIZE 0x8000 /* Size of the Environment. See comment above */ - -#define CFG_CONSOLE_IS_IN_ENV 1 /* stdin/stdout/stderr are in environment */ -#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 -#define CONFIG_ENV_OVERWRITE 1 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2 cache - */ -#define CFG_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * IDE ATAPI Configuration - */ - -#define CONFIG_ATAPI 1 -#define CFG_IDE_MAXBUS 2 -#define CFG_IDE_MAXDEVICE 4 -#define CONFIG_ISO_PARTITION 1 - -#define CFG_ATA_BASE_ADDR 0xFE000000 /* was: via_get_base_addr() */ -#define CFG_ATA_IDE0_OFFSET 0x1F0 -#define CFG_ATA_IDE1_OFFSET 0x170 - -#define CFG_ATA_REG_OFFSET 0 -#define CFG_ATA_DATA_OFFSET 0 -#define CFG_ATA_ALT_OFFSET 0x0200 - -/*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CFG_DOC_SUPPORT_2000 -#undef CFG_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- - RTC -*/ -#define CONFIG_RTC_MC146818 - -/*----------------------------------------------------------------------- - * NS16550 Configuration - */ - -#define CFG_NS16550 - -#define CFG_NS16550_COM1 0xFE0003F8 -#define CFG_NS16550_COM2 0xFE0002F8 - -#define CFG_NS16550_REG_SIZE 1 - -/* base address for ISA I/O - */ -#define CFG_ISA_IO_BASE_ADDRESS 0xFE000000 - -/* ISA Interrupt stuff (taken from JWL) */ - -#define ISA_INT1_OCW1 0x21 -#define ISA_INT2_OCW1 0xA1 -#define ISA_INT1_OCW2 0x20 -#define ISA_INT2_OCW2 0xA0 -#define ISA_INT1_OCW3 0x20 -#define ISA_INT2_OCW3 0xA0 - -#define ISA_INT1_ICW1 0x20 -#define ISA_INT2_ICW1 0xA0 -#define ISA_INT1_ICW2 0x21 -#define ISA_INT2_ICW2 0xA1 -#define ISA_INT1_ICW3 0x21 -#define ISA_INT2_ICW3 0xA1 -#define ISA_INT1_ICW4 0x21 -#define ISA_INT2_ICW4 0xA1 - - -/* - * misc - */ - -#define CONFIG_NET_MULTI -#define CFG_BOARD_ASM_INIT -#define CONFIG_LAST_STAGE_INIT - -/* #define CONFIG_ETHADDR 00:09:D2:10:00:76 */ -/* #define CONFIG_IPADDR 192.168.0.2 */ -/* #define CONFIG_NETMASK 255.255.255.240 */ -/* #define CONFIG_GATEWAYIP 192.168.0.3 */ - -#define CONFIG_3COM -/* #define CONFIG_BOOTP_RANDOM_DELAY */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - -/* - * USB configuration - */ -#define CONFIG_USB_UHCI 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_USB_KEYBOARD 1 -#define CFG_DEVICE_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */ - -/* - * Autoboot stuff - */ -#define CONFIG_BOOTDELAY 5 /* Boot automatically after five seconds */ -#define CONFIG_PREBOOT "" -#define CONFIG_BOOTCOMMAND "fdcboot; diskboot" -#define CONFIG_MENUPROMPT "Press any key to interrupt autoboot: %2d " -#define CONFIG_MENUKEY ' ' -#define CONFIG_MENUCOMMAND "menu" -/* #define CONFIG_AUTOBOOT_KEYED */ - -/* - * Extra ENV stuff - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdout=vga\0" \ - "stdin=ps2kbd\0" \ - "ide_doreset=on\0" \ - "ide_maxbus=2\0" \ - "ide_cd_timeout=30\0" \ - "menucmd=menu\0" \ - "pci_irqa=9\0" \ - "pci_irqa_select=edge\0" \ - "pci_irqb=10\0" \ - "pci_irqb_select=edge\0" \ - "pci_irqc=11\0" \ - "pci_irqc_select=edge\0" \ - "pci_irqd=7\0" \ - "pci_irqd_select=edge\0" - - -/* #define CONFIG_MII 1 */ -/* #define CONFIG_BITBANGMII 1 */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/B2.h b/include/configs/B2.h deleted file mode 100644 index e55858d..0000000 --- a/include/configs/B2.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * Configuation settings for the B2 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ -#define CONFIG_B2 1 /* on an B2 Board */ -#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ - -#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/ - - -#undef CONFIG_USE_IRQ /* don't need them anymore */ - - -/* - * Size of malloc() pool - */ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_ENV_SIZE 1024 /* 1024 bytes may be used for env vars*/ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024 ) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04000300 /* base address */ -#define CONFIG_SMC_USE_32_BIT -#undef CONFIG_SHOW_ACTIVITY -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_ETHADDR 00:50:c2:1e:af:fb -#define CONFIG_BOOTARGS "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \ - ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb" -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.70 -#define CONFIG_SERVERIP 192.168.0.23 -#define CONFIG_BOOTFILE "B2-rootfs/usr/B2-zImage.u-boot" -#define CONFIG_BOOTCOMMAND "bootm 20000 f0000" - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0C400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x0c700000 /* default load address */ - -#define CFG_HZ 1000 /* 1 kHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x0 /* environment starts at the beginning of the EEPROM */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (STM24C02W6) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0xFE - -#define CFG_I2C_EEPROM_ADDR 0xA8 /* EEPROM STM24C02W6 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/* Flash banks JFFS2 should use */ -/* -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_FIRST_SECTOR 2 -#define CFG_JFFS2_NUM_BANKS 1 -*/ - -/* - Linux TAGs (see lib_arm/armlinux.c) -*/ -#define CONFIG_CMDLINE_TAG -#undef CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#endif /* __CONFIG_H */ diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h deleted file mode 100644 index 46bdfa2..0000000 --- a/include/configs/BAB7xx.h +++ /dev/null @@ -1,467 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG -#define GTREGREAD(x) 0xffffffff /* needed for debug */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -#define CONFIG_ETHADDR 00:00:5b:ee:de:ad - -#define CONFIG_IPADDR 192.168.0.105 -#define CONFIG_SERVERIP 192.168.0.100 - -#define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */ - -#define CONFIG_BAUDRATE 9600 /* console baudrate */ - -#undef CONFIG_WATCHDOG - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp 1000000; " \ - "setenv bootargs root=ramfs console=ttyS00,9600 " \ - "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \ - "${netmask}:${hostname}:eth0:none; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\ - CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\ - CFG_CMD_FDC | CFG_CMD_ELF) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -/* - * choose between COM1 and COM2 as serial console - */ -#define CONFIG_CONS_INDEX 1 - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ - -#define CFG_HZ 1000 /* dec. freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -#define CFG_BOARD_ASM_INIT -#define CONFIG_MISC_INIT_R - -/* - * Choose the address mapping scheme for the MPC106 mem controller. - * Default is mapping B (CHRP), set this define to choose mapping A (PReP). - */ -#define CFG_ADDRESS_MAP_A -#ifdef CFG_ADDRESS_MAP_A - -#define CFG_PCI_MEMORY_BUS 0x80000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x80000000 - -#define CFG_PCI_MEM_BUS 0x00000000 -#define CFG_PCI_MEM_PHYS 0xc0000000 -#define CFG_PCI_MEM_SIZE 0x3f000000 - -#define CFG_ISA_MEM_BUS 0 -#define CFG_ISA_MEM_PHYS 0 -#define CFG_ISA_MEM_SIZE 0 - -#define CFG_PCI_IO_BUS 0x1000 -#define CFG_PCI_IO_PHYS 0x81000000 -#define CFG_PCI_IO_SIZE 0x01000000-CFG_PCI_IO_BUS - -#define CFG_ISA_IO_BUS 0x00000000 -#define CFG_ISA_IO_PHYS 0x80000000 -#define CFG_ISA_IO_SIZE 0x00800000 - -#else - -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x40000000 - -#define CFG_PCI_MEM_BUS 0x80000000 -#define CFG_PCI_MEM_PHYS 0x80000000 -#define CFG_PCI_MEM_SIZE 0x7d000000 - -#define CFG_ISA_MEM_BUS 0x00000000 -#define CFG_ISA_MEM_PHYS 0xfd000000 -#define CFG_ISA_MEM_SIZE 0x01000000 - -#define CFG_PCI_IO_BUS 0x00800000 -#define CFG_PCI_IO_PHYS 0xfe800000 -#define CFG_PCI_IO_SIZE 0x00400000 - -#define CFG_ISA_IO_BUS 0x00000000 -#define CFG_ISA_IO_PHYS 0xfe000000 -#define CFG_ISA_IO_SIZE 0x00800000 - -#endif /*CFG_ADDRESS_MAP_A */ - -#define CFG_60X_PCI_MEM_OFFSET 0x00000000 - -/* driver defines FDC,IDE,... */ -#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS -#define CFG_ISA_IO CFG_ISA_IO_PHYS -#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xfff00000 - -/* - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */ -#define CFG_INIT_RAM_END 0x4000 -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Flash mapping/organization on the MPC10x. - */ -#define FLASH_BASE0_PRELIM 0xff800000 -#define FLASH_BASE1_PRELIM 0xffc00000 - -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support - * - * Note: fake mtd_id used, no linux mtd map file - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=bab7xx-0" -#define MTDPARTS_DEFAULT "mtdparts=bab7xx-0:-(jffs2)" -*/ - -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */ -#undef CFG_MEMTEST - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CFG_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */ -#define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */ -/* - * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus, - * user applications can use the remaining space for other purposes. - */ -#define CFG_ENV_ADDR (CFG_NVRAM_SIZE +0x10 -0x800) -#define CFG_NV_SROM_COPY_ADDR (CFG_NVRAM_SIZE +0x10 -0x400) -#define CFG_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */ -#define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */ - -/* - * Serial devices - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 1843200 -#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) -#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO -#undef CONFIG_PCI_SCAN_SHOW - -/* - * Video console (graphic: SMI LynxEM, keyboard: i8042) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_I8042_KBD -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_TIME -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_CONSOLE_CURSOR -#define CFG_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */ - -/* - * IDE/SCSI globals - */ -#ifndef __ASSEMBLY__ -extern unsigned int eltec_board; -extern unsigned int ata_reset_time; -extern unsigned int scsi_reset_time; -extern unsigned short scsi_dev_id; -extern unsigned int scsi_max_scsi_id; -extern unsigned char scsi_sym53c8xx_ccf; -#endif - -/* - * ATAPI Support (experimental) - */ -#define CONFIG_ATAPI -#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR CFG_60X_PCI_IO_OFFSET /* base address */ -#define CFG_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */ -#define CFG_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ - -#define ATA_RESET_TIME (ata_reset_time) - -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ - -/* - * SCSI support (experimental) only SYM53C8xx supported - */ -#define CONFIG_SCSI_SYM53C8XX -#define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */ -#define CFG_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */ -#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ -#define CFG_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */ -#define CFG_SCSI_MAX_DEVICE (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */ -#define CFG_SCSI_SPIN_UP_TIME (scsi_reset_time) - -/* - * Partion suppport - */ -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION - -/* - * Winbond Configuration - */ -#define CFG_WINBOND_83C553 1 /* has a winbond bridge */ -#define CFG_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */ -#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */ -#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */ - -/* - * NS87308 Configuration - */ -#define CFG_NS87308 /* Nat Semi super-io cntr on ISA bus */ -#define CFG_NS87308_BADDR_10 1 -#define CFG_NS87308_DEVS (CFG_NS87308_UART1 | \ - CFG_NS87308_UART2 | \ - CFG_NS87308_KBC1 | \ - CFG_NS87308_MOUSE | \ - CFG_NS87308_FDC | \ - CFG_NS87308_RARP | \ - CFG_NS87308_GPIO | \ - CFG_NS87308_POWRMAN | \ - CFG_NS87308_RTC_APC ) - -#define CFG_NS87308_PS2MOD -#define CFG_NS87308_GPIO_BASE 0x0220 -#define CFG_NS87308_PWMAN_BASE 0x0460 -#define CFG_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */ - -/* - * set up the NVRAM access registers - * NVRAM's controlled by the configurable CS line from the 87308 - */ -#define CFG_NS87308_CS0_BASE 0x0076 -#define CFG_NS87308_CS0_CONF 0x40 -#define CFG_NS87308_CS1_BASE 0x0070 -#define CFG_NS87308_CS1_CONF 0x1C -#define CFG_NS87308_CS2_BASE 0x0071 -#define CFG_NS87308_CS2_CONF 0x1C - -#define CONFIG_RTC_MK48T59 - -/* - * Initial BATs - */ -#if 1 - -#define CFG_IBAT0L 0 -#define CFG_IBAT0U 0 -#define CFG_DBAT0L CFG_IBAT1L -#define CFG_DBAT0U CFG_IBAT1U - -#define CFG_IBAT1L 0 -#define CFG_IBAT1U 0 -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -#define CFG_IBAT2L 0 -#define CFG_IBAT2U 0 -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U - -#define CFG_IBAT3L 0 -#define CFG_IBAT3U 0 -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -#else - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L CFG_IBAT1L -#define CFG_DBAT0U CFG_IBAT1U - -/* address range for flashes */ -#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* ISA IO space */ -#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U - -/* ISA memory space */ -#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -#endif - -/* - * Speed settings are board specific - */ -#ifndef __ASSEMBLY__ -extern unsigned long bab7xx_get_bus_freq (void); -extern unsigned long bab7xx_get_gclk_freq (void); -#endif -#define CFG_BUS_HZ bab7xx_get_bus_freq() -#define CFG_BUS_CLK CFG_BUS_HZ -#define CFG_CPU_CLK bab7xx_get_gclk_freq() - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2 Cache Configuration is board specific for BAB740/BAB750 - * Init values read from revision srom. - */ -#undef CFG_L2 -#define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CFG_L2_BAB7xx - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ -#define CONFIG_TULIP -#define CONFIG_TULIP_SELECT_MEDIA - -#endif /* __CONFIG_H */ diff --git a/include/configs/BMW.h b/include/configs/BMW.h deleted file mode 100644 index 050054d..0000000 --- a/include/configs/BMW.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the CU824 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_BMW 1 - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CONFIG_BCM570x 1 /* Use Broadcom BCM570x Ethernet Driver */ -#define CONFIG_TIGON3 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */ -#define CONFIG_BOOTDELAY 5 - -#define CFG_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */ -#define DOC_PASSIVE_PROBE 1 -#define CFG_DOC_SUPPORT_2000 1 -#define CFG_DOC_SUPPORT_MILLENNIUM 1 -#define CFG_DOC_SHORT_TIMEOUT 1 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DOC | \ - CFG_CMD_ELF | \ - 0 ) -#if 0 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \ - CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE) - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ -#endif - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - -#define CFG_MAXARGS 8 /* Max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -#define CFG_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */ -#define CFG_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */ -#define CFG_FLASH_BASE CFG_MONITOR_BASE -#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM , CFG_FLASH_BASE1_PRELIM } - -/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the - * reset vector is actually located at FFB00100, but the 8245 - * takes care of us. - */ -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_EUMB_ADDR 0xFC000000 - -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CFG_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */ - - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#undef CFG_RAMBOOT -#else -#define CFG_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -#define CFG_HZ 1000 - -#define CFG_ETH_DEV_FN 0x7800 -#define CFG_ETH_IOBASE 0x00104000 - - /* Bit-field values for MCCR1. - */ -#define CFG_ROMNAL 0xf -#define CFG_ROMFAL 0x1f -#define CFG_DBUS_SIZE 0x3 - - /* Bit-field values for MCCR2. - */ -#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CFG_BSTOPRE 0 /* FIXME: was 192 */ - - /* Bit-field values for MCCR3. - */ -#define CFG_REFREC 2 /* Refresh to activate interval */ - - /* Bit-field values for MCCR4. - */ -#define CFG_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length */ -#define CFG_ACTORW 0xa /* FIXME was 2 */ -#define CFG_REGISTERD_TYPE_BUFFER 1 - -#define CFG_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ - -#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff -#define CFG_BANK7_ENABLE 0 - -#define CFG_ODCR 0xff - -#define CONFIG_PCI 1 /* Include PCI support */ -#undef CONFIG_PCI_PNP - -/* PCI Memory space(s) */ -#define PCI_MEM_SPACE1_START 0x80000000 -#define PCI_MEM_SPACE2_START 0xfd000000 - -/* ROM Spaces */ -#include "../board/bmw/bmw.h" - -/* BAT configuration */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 0 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CFG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_OVERWRITE 1 -#define CFG_NVRAM_ACCESS_ROUTINE 1 -#define CFG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */ -#define CFG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */ -#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ - -/* - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h deleted file mode 100644 index e0262a8..0000000 --- a/include/configs/CANBT.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * (C) Copyright 2001 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405CR 1 /* This is a PPC405CR CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CANBT 1 /* ...on a CANBT board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \ - "bootm ffe00000 ffe80000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_PCI_PNP /* no pci plug-and-play */ - -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \ - CFG_CMD_IRQ | \ - CFG_CMD_EEPROM ) & \ - ~CFG_CMD_NET) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFE0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* Use FLASH for environment variables */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ - -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -#else /* Use EEPROM for environment variables */ - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (CAN/USB) initialization */ -#define CFG_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */ -#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Misc-IO/LEDs) initialization */ -#define CFG_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */ -#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (CAN Features) initialization */ -#define CFG_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */ -#define CFG_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in RAM) - */ -#define CFG_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h deleted file mode 100644 index ffe89cb..0000000 --- a/include/configs/CATcenter.h +++ /dev/null @@ -1,787 +0,0 @@ -/* - * ueberarbeitet durch Christoph Seyfert - * - * (C) Copyright 2004-2005 DENX Software Engineering, - * Wolfgang Grandegger - * (C) Copyright 2003 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * Credits: Stefan Roese, Wolfgang Denk - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ -#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ -#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ -#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL -#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA -#endif - -/* Only one of the following two symbols must be defined (default is 25 MHz) - * CONFIG_PPCHAMELEON_CLK_25 - * CONFIG_PPCHAMELEON_CLK_33 - */ -#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_PPCHAMELEON_CLK_25 -#endif - -#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) -#error "* Two external frequencies (SysClk) are defined! *" -#endif - -#undef CONFIG_PPCHAMELEON_SMI712 - -/* - * Debug stuff - */ -#undef __DEBUG_START_FROM_SRAM__ -#define __DISABLE_MACHINE_EXCEPTION__ - -#ifdef __DEBUG_START_FROM_SRAM__ -#define CFG_DUMMY_FLASH_SIZE 1024*1024*4 -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#else -# error "* External frequency (SysClk) not defined! *" -#endif - -#define CONFIG_UART1_CONSOLE 1 /* Use second UART */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_VERSION_VARIABLE 1 /* add version variable */ -#define CONFIG_IDENT_STRING "1" - -#undef CONFIG_BOOTARGS - -/* Ethernet stuff */ -#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ -#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -#undef CONFIG_EXT_PHY -#define CONFIG_NET_MULTI 1 - -#define CONFIG_MII 1 /* MII PHY management */ -#ifndef CONFIG_EXT_PHY -#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ -#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */ -#else -#define CONFIG_PHY_ADDR 2 /* PHY address */ -#endif -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CFG_NAND0_BASE 0xFF400000 -#define CFG_NAND1_BASE 0xFF000000 - -/* For CATcenter there is only NAND on the module */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 -#define NAND_NO_RB - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ -#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ -#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ -#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ - - -#define NAND_DISABLE_CE(nand) do \ -{ \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define NAND_ENABLE_CE(nand) do \ -{ \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \ - break; \ - } \ -} while(0) - - -#define NAND_CTL_CLRALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define NAND_CTL_SETALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define NAND_CTL_CLRCLE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#define NAND_CTL_SETCLE(nandptr) do { \ - switch((unsigned long)nandptr) { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#ifdef NAND_NO_RB -/* constant delay (see also tR in the datasheet) */ -#define NAND_WAIT_READY(nand) do { \ - udelay(12); \ -} while (0) -#else -/* use the R/B pin */ -/* TBD */ -#endif - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#if 0 /* No PCI on CATcenter */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ - -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -#endif /* No PCI */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ -#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ -#define CFG_ENV_ADDR_REDUND 0xFFFFA000 -#define CFG_ENV_SIZE_REDUND 0x2000 - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (External SRAM) initialization */ -/* Since this must replace NOR Flash, we use the same settings for CS0 */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ -#define CFG_EBC_PB2AP 0x92015480 -#define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ -#define CFG_EBC_PB3AP 0x92015480 -#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ - -#ifdef CONFIG_PPCHAMELEON_SMI712 -/* - * Video console (graphic: SMI LynxEM) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_VIDEO_LOGO -/*#define CONFIG_VIDEO_BMP_LOGO*/ -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ -#define CFG_ISA_IO 0xE8000000 -/* see also drivers/videomodes.c */ -#define CFG_DEFAULT_VIDEO_MODE 0x303 -#endif - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CFG_FPGA_MODE 0x00 -#define CFG_FPGA_STATUS 0x02 -#define CFG_FPGA_TS 0x04 -#define CFG_FPGA_TS_LOW 0x06 -#define CFG_FPGA_TS_CAP0 0x10 -#define CFG_FPGA_TS_CAP0_LOW 0x12 -#define CFG_FPGA_TS_CAP1 0x14 -#define CFG_FPGA_TS_CAP1_LOW 0x16 -#define CFG_FPGA_TS_CAP2 0x18 -#define CFG_FPGA_TS_CAP2_LOW 0x1a -#define CFG_FPGA_TS_CAP3 0x1c -#define CFG_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CFG_FPGA_MODE_CF_RESET 0x0001 -#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CFG_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CFG_FPGA_STATUS_DIP0 0x0001 -#define CFG_FPGA_STATUS_DIP1 0x0002 -#define CFG_FPGA_STATUS_DIP2 0x0004 -#define CFG_FPGA_STATUS_FLASH 0x0008 -#define CFG_FPGA_STATUS_TS_IRQ 0x1000 - -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30] - EMAC0 input - * GPIO0[31] - EMAC1 reject packet as output - */ -#define CFG_GPIO0_OSRH 0x40000550 -#define CFG_GPIO0_OSRL 0x00000110 -#define CFG_GPIO0_ISR1H 0x00000000 -/*#define CFG_GPIO0_ISR1L 0x15555445*/ -#define CFG_GPIO0_ISR1L 0x15555444 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FF8014 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#define CONFIG_NO_SERIAL_EEPROM - -/*--------------------------------------------------------------------*/ - -#ifdef CONFIG_NO_SERIAL_EEPROM - -/* -!----------------------------------------------------------------------- -! Defines for entry options. -! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that -! are plugged in the board will be utilized as non-ECC DIMMs. -!----------------------------------------------------------------------- -*/ -#undef AUTO_MEMORY_CONFIG -#define DIMM_READ_ADDR 0xAB -#define DIMM_WRITE_ADDR 0xAA - -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) - -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#else -#error "* External frequency (SysClk) not defined! *" -#endif - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -/* Model HI */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 -#define CFG_OPB_FREQ 55555555 -/* Model ME */ -#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 -#define CFG_OPB_FREQ 66666666 -#else -/* Model BA (default) */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 -#define CFG_OPB_FREQ 66666666 -#endif - -#endif /* CONFIG_NO_SERIAL_EEPROM */ - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nand" -#define CONFIG_JFFS2_PART_SIZE 0x00200000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support - * - * Note: fake mtd_id used, no linux mtd map file - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nand0=catcenter" -#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CCM.h b/include/configs/CCM.h deleted file mode 100644 index e8994ff..0000000 --- a/include/configs/CCM.h +++ /dev/null @@ -1,478 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * configuration options, board specific, for Siemens Card Controller Module - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef CCM_80MHz /* define for 80 MHz CPU only */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */ -#define CONFIG_CCM 1 /* on a Card Controller Module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -/* ENVIRONMENT */ - -#define CONFIG_BAUDRATE 19200 /* console baudrate in bps */ -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ - -#define CONFIG_IPADDR 192.168.0.42 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 0.0.0.0 -#define CONFIG_SERVERIP 192.168.0.254 - -#define CONFIG_HOSTNAME CCM - -#define CONFIG_LOADADDR 40180000 - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND "setenv bootargs " \ - "mem=${mem} " \ - "root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ - "wt_8xx=timeout:3600; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -#define CONFIG_PRAM 512 /* reserve 512kB "protected RAM"*/ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_SPI /* enable SPI driver */ -#define CONFIG_SPI_X /* 16 bit EEPROM addressing */ - -/* ---------------------------------------------------------------- - * Offset to initial SPI buffers in DPRAM (used if the environment - * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to - * use at an early stage. It is used between the two initialization - * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it - * far enough from the start of the data area (as well as from the - * stack pointer). - * ---------------------------------------------------------------- */ -#define CFG_SPI_INIT_OFFSET 0xB00 - -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-byte page size */ - - -#define CONFIG_MAC_PARTITION /* nod used yet */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -/* Ethernet hardware configuration done using port pins */ -#define CFG_PA_ETH_RESET 0x0200 /* PA 6 */ -#define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */ -#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ -#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */ -#define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */ -#define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */ - -/* Ethernet settings: - * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex - */ -#define CFG_ETH_MDDIS_VALUE 0 -#define CFG_ETH_CFG1_VALUE 1 -#define CFG_ETH_CFG2_VALUE 1 -#define CFG_ETH_CFG3_VALUE 1 - -/* PUMA configuration */ -#define CFG_PC_PUMA_PROG 0x0200 /* PC 6 */ -#define CFG_PC_PUMA_DONE 0x0008 /* PC 12 */ -#define CFG_PC_PUMA_INIT 0x0004 /* PC 13 */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Address accessed to reset the board - must not be mapped/assigned - */ -#define CFG_RESET_ADDRESS 0xFEFFFFFF - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if 1 -/* Start port with environment in flash; switch to SPI EEPROM later */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#else -/* Final version: environment in EEPROM */ -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_ENV_OFFSET 2048 -#define CFG_ENV_SIZE 2048 -#endif - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * we must activate GPL5 in the SIUMCR for CAN - */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)< - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#undef CONFIG_PRAM /* no "protected RAM" */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * RTC stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_RTC_DS1337 -#define CFG_I2C_RTC_ADDR 0x68 - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CFG_RAMBOOT 1 -#else -# undef CFG_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -#define CFG_EEPROM_WREN 1 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ -#define CFG_PLD_BASE 0xf0000000 -#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ -/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ -/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ -/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CFG_GPIO0_OSRH 0x40000500 /* 0 ... 15 */ -#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ -#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ -#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ -#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ -#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ -#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ - -#define CFG_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ -#define CFG_PLD_RESET (0x80000000 >> 12) /* GPIO12 */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h deleted file mode 100644 index b882f7a..0000000 --- a/include/configs/CPC45.h +++ /dev/null @@ -1,513 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the CPC45 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_CPC45 1 - - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ - CFG_CMD_FLASH | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -#if 1 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* Print Buffer Size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ - -#define CFG_SDRAM_BASE 0x00000000 - -#if defined(CONFIG_BOOT_ROM) -#define CFG_FLASH_BASE 0xFF000000 -#else -#define CFG_FLASH_BASE 0xFF800000 -#endif - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_EUMB_ADDR 0xFCE00000 - -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/* Maximum amount of RAM. - */ -#define CFG_MAX_RAM_SIZE 0x10000000 - - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#undef CFG_RAMBOOT -#else -#define CFG_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* Size in bytes reserved for initial data - */ -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) -#define DUART_DCR (CFG_EUMB_ADDR + 0x4511) - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 -#define CFG_HZ 1000 - - -/* Bit-field values for MCCR1. - */ -#define CFG_ROMNAL 0 -#define CFG_ROMFAL 8 - -#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */ -#define CFG_BANK1_ROW 0 -#define CFG_BANK2_ROW 0 -#define CFG_BANK3_ROW 0 -#define CFG_BANK4_ROW 0 -#define CFG_BANK5_ROW 0 -#define CFG_BANK6_ROW 0 -#define CFG_BANK7_ROW 0 - -/* Bit-field values for MCCR2. - */ - -#define CFG_REFINT 0x2ec - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CFG_BSTOPRE 160 - -/* Bit-field values for MCCR3. - */ -#define CFG_REFREC 2 /* Refresh to activate interval */ -#define CFG_RDLAT 0 /* Data latancy from read command */ - -/* Bit-field values for MCCR4. - */ -#define CFG_PRETOACT 2 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CFG_ACTORW 2 -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 0 -#define CFG_REGDIMM 0 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff -#define CFG_BANK7_ENABLE 0 - -#define CFG_ODCR 0xff -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ -#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - /* Warining: environment is not EMBEDDED in the ppcboot code. - * It's stored in flash separately. - */ -#define CFG_ENV_IS_IN_FLASH 1 - -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7F8000) -#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */ -#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#define SRAM_BASE 0x80000000 /* SRAM base address */ -#define SRAM_END 0x801FFFFF - -/*----------------------------------------------------------------------*/ -/* CPC45 Memory Map */ -/*----------------------------------------------------------------------*/ -#define SRAM_BASE 0x80000000 /* SRAM base address */ -#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */ -#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */ -#define BCSR_BASE 0x80600000 /* board control / status registers */ -#define DISPLAY_BASE 0x80600040 /* DISPLAY base */ -#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */ -#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */ - - -/*---------------------------------------------------------------------*/ -/* CPC45 Control/Status Registers */ -/*---------------------------------------------------------------------*/ -#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00)) -#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01)) -#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02)) -#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03)) -#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04)) -#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05)) -#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06)) -#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06)) -#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06)) -#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07)) - -/* IRQ_ENA_1 bit definitions */ -#define I_ENA_1_IERA 0x80 /* INTA enable */ -#define I_ENA_1_IERB 0x40 /* INTB enable */ -#define I_ENA_1_IERC 0x20 /* INTC enable */ -#define I_ENA_1_IERD 0x10 /* INTD enable */ - -/* IRQ_STAT_1 bit definitions */ -#define I_STAT_1_INTA 0x80 /* INTA status */ -#define I_STAT_1_INTB 0x40 /* INTB status */ -#define I_STAT_1_INTC 0x20 /* INTC status */ -#define I_STAT_1_INTD 0x10 /* INTD status */ - -/* IRQ_ENA_2 bit definitions */ -#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */ -#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */ -#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */ -#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */ -#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */ -#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */ -#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */ -#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */ - -/* IRQ_STAT_2 bit definitions */ -#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */ -#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */ -#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */ -#define I_STAT_2_RTC 0x10 /* RTC IRQ status */ -#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */ -#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */ -#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */ -#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */ - -/* BOARD_CTRL bit definitions */ -#define USER_LEDS 2 /* 2 user LEDs */ - -#if (USER_LEDS == 4) -#define B_CTRL_WRSE 0x80 -#define B_CTRL_KRSE 0x40 -#define B_CTRL_FWRE 0x20 /* Flash write enable */ -#define B_CTRL_FWPT 0x10 /* Flash write protect */ -#define B_CTRL_LED3 0x08 /* LED 3 control */ -#define B_CTRL_LED2 0x04 /* LED 2 control */ -#define B_CTRL_LED1 0x02 /* LED 1 control */ -#define B_CTRL_LED0 0x01 /* LED 0 control */ -#else -#define B_CTRL_WRSE 0x80 -#define B_CTRL_KRSE 0x40 -#define B_CTRL_FWRE_1 0x20 /* Flash write enable */ -#define B_CTRL_FWPT_1 0x10 /* Flash write protect */ -#define B_CTRL_LED1 0x08 /* LED 1 control */ -#define B_CTRL_LED0 0x04 /* LED 0 control */ -#define B_CTRL_FWRE_0 0x02 /* Flash write enable */ -#define B_CTRL_FWPT_0 0x01 /* Flash write protect */ -#endif - -/* BOARD_STAT bit definitions */ -#define B_STAT_WDGE 0x80 -#define B_STAT_WDGS 0x40 -#define B_STAT_WRST 0x20 -#define B_STAT_KRST 0x10 -#define B_STAT_CSW3 0x08 /* sitch bit 3 status */ -#define B_STAT_CSW2 0x04 /* sitch bit 2 status */ -#define B_STAT_CSW1 0x02 /* sitch bit 1 status */ -#define B_STAT_CSW0 0x01 /* sitch bit 0 status */ - -/*---------------------------------------------------------------------*/ -/* Display addresses */ -/*---------------------------------------------------------------------*/ -#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */ -#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */ -#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */ - -#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */ -#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */ - -#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */ -#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */ -#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */ -#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */ -#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */ -#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */ -#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */ -#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP -#undef CONFIG_PCI_SCAN_SHOW - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define PCI_ENET0_IOADDR 0x82000000 -#define PCI_ENET0_MEMADDR 0x82000000 -#define PCI_PLX9030_IOADDR 0x82100000 -#define PCI_PLX9030_MEMADDR 0x82100000 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ - -#define CONFIG_I82365 - -#define CFG_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE -#define CFG_PCMCIA_MEM_SIZE 0x1000 - -#define CONFIG_PCMCIA_SLOT_A - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_RESET /* reset for IDE not supported */ -#define CONFIG_IDE_LED /* LED for IDE is supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -#define CFG_ATA_DATA_OFFSET CFG_PCMCIA_MEM_SIZE - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x400) - -#define CONFIG_DOS_PARTITION - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h deleted file mode 100644 index 756bb8c..0000000 --- a/include/configs/CPCI2DP.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * (C) Copyright 2005 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */ -#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */ -#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ - -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -#define CFG_EEPROM_WREN 1 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (PB0) initialization */ -#define CFG_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ -#define CFG_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (PB1) initialization */ -#define CFG_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */ -#define CFG_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * GPIO definitions - */ -#define CFG_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */ -#define CFG_PB_LED (0x80000000 >> 16) /* GPIO16 */ -#define CFG_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h deleted file mode 100644 index d49020d..0000000 --- a/include/configs/CPCI405.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFD0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ - -#if 1 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ - -#else /* Use EEPROM for environment variables */ - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (CompactFlash IDE) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (NVRAM) initialization */ -#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 5 (Quart) initialization */ -#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ -#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#if 1 /* test-only */ -#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#else -#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ -#endif -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h deleted file mode 100644 index 13dbe80..0000000 --- a/include/configs/CPCI4052.h +++ /dev/null @@ -1,422 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ -#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) - -#if 0 /* test-only */ -#define CONFIG_NETCONSOLE -#define CONFIG_NET_MULTI - -#ifdef CONFIG_NET_MULTI -#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ -#endif -#endif - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#if 0 /* test-only */ -#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition, use whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci4052-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)" -*/ - -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */ - -#else /* Use EEPROM for environment variables */ - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ -#endif - -#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CFG_LED_ADDR 0xF0000380 - -/* Memory Bank 3 (CompactFlash IDE) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (NVRAM/RTC) initialization */ -/*#define CFG_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ -#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 5 (optional Quart) initialization */ -#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ -#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 6 (FPGA internal) initialization */ -#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ -#define CFG_FPGA_BASE_ADDR 0xF0400000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CFG_FPGA_MODE 0x00 -#define CFG_FPGA_STATUS 0x02 -#define CFG_FPGA_TS 0x04 -#define CFG_FPGA_TS_LOW 0x06 -#define CFG_FPGA_TS_CAP0 0x10 -#define CFG_FPGA_TS_CAP0_LOW 0x12 -#define CFG_FPGA_TS_CAP1 0x14 -#define CFG_FPGA_TS_CAP1_LOW 0x16 -#define CFG_FPGA_TS_CAP2 0x18 -#define CFG_FPGA_TS_CAP2_LOW 0x1a -#define CFG_FPGA_TS_CAP3 0x1c -#define CFG_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CFG_FPGA_MODE_CF_RESET 0x0001 -#define CFG_FPGA_MODE_DUART_RESET 0x0002 -#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ -#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CFG_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CFG_FPGA_STATUS_DIP0 0x0001 -#define CFG_FPGA_STATUS_DIP1 0x0002 -#define CFG_FPGA_STATUS_DIP2 0x0004 -#define CFG_FPGA_STATUS_FLASH 0x0008 -#define CFG_FPGA_STATUS_TS_IRQ 0x1000 - -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h deleted file mode 100644 index aaaafa9..0000000 --- a/include/configs/CPCI405AB.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ -#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ -#define CONFIG_CPCI405AB 1 /* ...and special AB version */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#undef CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* - * JFFS2 partitions - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci405ab-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci405ab-0:-(jffs2)" -*/ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC32) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom used! */ -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/* Use EEPROM for environment variables */ - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC32 is 4096 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CFG_LED_ADDR 0xF0000380 - -/* Memory Bank 3 (CompactFlash IDE) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (NVRAM/RTC) initialization */ -/*#define CFG_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ -#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 5 (optional Quart) initialization */ -#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ -#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 6 (FPGA internal) initialization */ -#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ -#define CFG_FPGA_BASE_ADDR 0xF0400000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CFG_FPGA_MODE 0x00 -#define CFG_FPGA_STATUS 0x02 -#define CFG_FPGA_TS 0x04 -#define CFG_FPGA_TS_LOW 0x06 -#define CFG_FPGA_TS_CAP0 0x10 -#define CFG_FPGA_TS_CAP0_LOW 0x12 -#define CFG_FPGA_TS_CAP1 0x14 -#define CFG_FPGA_TS_CAP1_LOW 0x16 -#define CFG_FPGA_TS_CAP2 0x18 -#define CFG_FPGA_TS_CAP2_LOW 0x1a -#define CFG_FPGA_TS_CAP3 0x1c -#define CFG_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CFG_FPGA_MODE_CF_RESET 0x0001 -#define CFG_FPGA_MODE_DUART_RESET 0x0002 -#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ -#define CFG_FPGA_MODE_1WIRE_DIR 0x0100 /* dir=1 -> output */ -#define CFG_FPGA_MODE_SIM_OK_DIR 0x0200 -#define CFG_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400 -#define CFG_FPGA_MODE_1WIRE 0x1000 -#define CFG_FPGA_MODE_SIM_OK 0x2000 /* wired-or net from all devices */ -#define CFG_FPGA_MODE_TESTRIG_FAIL 0x4000 - -/* FPGA Status Reg */ -#define CFG_FPGA_STATUS_DIP0 0x0001 -#define CFG_FPGA_STATUS_DIP1 0x0002 -#define CFG_FPGA_STATUS_DIP2 0x0004 -#define CFG_FPGA_STATUS_FLASH 0x0008 -#define CFG_FPGA_STATUS_1WIRE 0x1000 -#define CFG_FPGA_STATUS_SIM_OK 0x2000 - -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S30 */ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h deleted file mode 100644 index 5cd9aba..0000000 --- a/include/configs/CPCI405DT.h +++ /dev/null @@ -1,425 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ -#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) - -#if 0 /* test-only */ -#define CONFIG_NETCONSOLE -#define CONFIG_NET_MULTI - -#ifdef CONFIG_NET_MULTI -#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ -#endif -#endif - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/* Only interrupt boot if special string is typed */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n" -#undef CONFIG_AUTOBOOT_DELAY_STR -#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ -#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* - * JFFS2 partitions - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci405dt-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci405dt-0:-(jffs2)" -*/ - -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */ - -#else /* Use EEPROM for environment variables */ - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ -#endif - -#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CFG_LED_ADDR 0xF0000380 - -/* Memory Bank 3 (CompactFlash IDE) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (NVRAM/RTC) initialization */ -/*#define CFG_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ -#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 5 (optional Quart) initialization */ -#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ -#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 6 (FPGA internal) initialization */ -#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ -#define CFG_FPGA_BASE_ADDR 0xF0400000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CFG_FPGA_MODE 0x00 -#define CFG_FPGA_STATUS 0x02 -#define CFG_FPGA_TS 0x04 -#define CFG_FPGA_TS_LOW 0x06 -#define CFG_FPGA_TS_CAP0 0x10 -#define CFG_FPGA_TS_CAP0_LOW 0x12 -#define CFG_FPGA_TS_CAP1 0x14 -#define CFG_FPGA_TS_CAP1_LOW 0x16 -#define CFG_FPGA_TS_CAP2 0x18 -#define CFG_FPGA_TS_CAP2_LOW 0x1a -#define CFG_FPGA_TS_CAP3 0x1c -#define CFG_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CFG_FPGA_MODE_CF_RESET 0x0001 -#define CFG_FPGA_MODE_DUART_RESET 0x0002 -#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ -#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CFG_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CFG_FPGA_STATUS_DIP0 0x0001 -#define CFG_FPGA_STATUS_DIP1 0x0002 -#define CFG_FPGA_STATUS_DIP2 0x0004 -#define CFG_FPGA_STATUS_FLASH 0x0008 -#define CFG_FPGA_STATUS_TS_IRQ 0x1000 - -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ - -#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h deleted file mode 100644 index a5bc773..0000000 --- a/include/configs/CPCI440.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * (C) Copyright 2002 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * board/config_CPCI440.h - configuration for esd CPCI-440 board - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_EBONY 1 /* Board is ebony */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#if 1 -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#else -#define CFG_MONITOR_BASE 0x01fc0000 /* start of monitor */ -#endif -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ - -#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) -#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#if 1 /* test-only */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#undef CFG_FLASH_BASE -#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/ - -#else /* test-only */ - -#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ -#define CFG_MAX_FLASH_SECT 32 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#endif - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#if 0 /* test-only */ -#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ - -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) -#else - -#if 0 /* test-only */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ -#else -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -#endif - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_BAUDRATE 9600 - -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#if 0 /* test-only */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_KGDB | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF ) -#else -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM ) -/* test-only: support fehlt bisher... */ -/* CFG_CMD_IDE | \*/ -/* CFG_CMD_PCI | \*/ -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#if 0 /* test-only */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#endif - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#if 0 -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h deleted file mode 100644 index 8bfd0ee..0000000 --- a/include/configs/CPCI750.h +++ /dev/null @@ -1,598 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -/************************************************************************* - * (c) 2004 esd gmbh Hannover - * - * - * from db64360.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - ************************************************************************/ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ - -#ifndef __ASSEMBLY__ -#include <../board/Marvell/include/core.h> -#endif -/*-----------------------------------------------------*/ - -#include "../board/esd/cpci750/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_750FX /* we have a 750FX (override local.h) */ - -#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ - -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ - -#undef CONFIG_ECC /* enable ECC support */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_PRE_INIT -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#define CFG_BOARD_NAME "CPCI750" -#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" - -/*#define CFG_HUSH_PARSER*/ -#undef CFG_HUSH_PARSER - -#define CFG_PROMPT_HUSH_PS2 "> " - -/* Define which ETH port will be used for connecting the network */ -#define CFG_ETH_PORT ETH_0 - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define CONFIG_NET_MULTI -#define MV_ETH_DEVS 1 -#define CONFIG_ETHER_PORT 0 - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#define CONFIG_BOOTDELAY 5 /* autoboot disabled */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS - -/* ----------------------------------------------------------------------------- - * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus - */ - -#define CONFIG_IPADDR "192.168.0.185" - -#define CONFIG_SERIAL "AA000001" -#define CONFIG_SERVERIP "10.0.0.79" -#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* ----------------------------------------------------------------------------- */ - - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ - | CFG_CMD_CACHE \ - | CFG_CMD_EEPROM \ - | CFG_CMD_PCI \ - | CFG_CMD_ELF \ - | CFG_CMD_DATE \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - | CFG_CMD_IDE \ - | CFG_CMD_FAT \ - | CFG_CMD_EXT2 \ - ) - -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_SPEED 80000 /* I2C speed default */ - -#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */ -/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ - -/* -#define CFG_DRAM_TEST - * DRAM tests - * CFG_DRAM_TEST - enables the following tests. - * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CFG_DRAM_TEST -#if defined(CFG_DRAM_TEST) -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CFG_DRAM_TEST_DATA -#define CFG_DRAM_TEST_ADDRESS -#define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ - -#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CFG_LOAD_ADDR 0x00300000 /* default load address */ - -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CFG_BUS_CLK CFG_BUS_HZ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_TCLK 133000000 - -/*#define CFG_750FX_HID0 0x8000c084*/ -#define CFG_750FX_HID0 0x80008484 -#define CFG_750FX_HID1 0x54800000 -#define CFG_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - - /* - * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#undef CFG_INIT_RAM_LOCK -/* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ -/* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ -#define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR -/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/ -#define CFG_INTERNAL_RAM_ADDR 0xf1080000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CFG_SDRAM2_BASE 0x20000000 -#define CFG_SDRAM3_BASE 0x30000000 -#define CFG_SDRAM4_BASE 0x40000000 -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE 0xfff00000 -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0x01000000 /* there is only one bank */ -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */ - -/* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the cpci750 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ - -#undef MARVEL_STANDARD_CFG -#ifndef MARVEL_STANDARD_CFG -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -/*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ -#define CFG_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ - -#define CFG_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ -#define CFG_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ -#define CFG_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ -#define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ -#define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ - -#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */ -#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */ -#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */ -#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */ -#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#endif - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */ -#define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* MPP Control MV64360 Appendix P P. 632*/ -#define CFG_MPP_CONTROL_0 0x00002222 /* */ -#define CFG_MPP_CONTROL_1 0x11110000 /* */ -#define CFG_MPP_CONTROL_2 0x11111111 /* */ -#define CFG_MPP_CONTROL_3 0x00001111 /* */ -/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */ - - -#define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ - -/* setup new config_value for MV64360 DDR-RAM To_do !! */ -/*# define CFG_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ -/*# define CFG_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ - /* GB has high prio. - idma has low prio - MPSC has low prio - pci has low prio 1 and 2 - cpu has high prio - Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices - ECC disable - non registered DRAM */ - /* 31:26 25:22 21:20 19 18 17 16 */ - /* 100001 0000 010 0 0 0 0 */ - /* refresh_count=0x400 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 0 1 0x400 */ -# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M - -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M - -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI 0x00000000 -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI 0x00000000 - -#if defined (CONFIG_750CX) -#define CFG_PCI_IDSEL 0x0 -#else -#define CFG_PCI_IDSEL 0x30 -#endif - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* no reset for ide supported */ -#define CONFIG_IDE_PREINIT /* check for units */ - -#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0 -#define CFG_ATA_IDE0_OFFSET 0 -#define CFG_ATA_IDE1_OFFSET 0 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* - * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7) - * IBAT4 and DBAT4 - * FIXME: ingo disable BATs for Linux Kernel - */ -#undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */ -/*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */ - -#ifdef SETUP_HIGH_BATS_FX750 -#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U CFG_IBAT4U - -/* IBAT5 and DBAT5 */ -#define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT5U CFG_IBAT5U - -/* IBAT6 and DBAT6 */ -#define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U CFG_IBAT6U - -/* IBAT7 and DBAT7 */ -#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT7U CFG_IBAT7U - -#else /* set em out of range for Linux !!!!!!!!!!! */ -#define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U CFG_IBAT4U - -/* IBAT5 and DBAT5 */ -#define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT5U CFG_IBAT4U - -/* IBAT6 and DBAT6 */ -#define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U CFG_IBAT4U - -/* IBAT7 and DBAT7 */ -#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT7U CFG_IBAT4U - -#endif -/* FIXME: ingo end: disable BATs for Linux Kernel */ - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x51 -#define DIMM1_I2C_ADDR 0x52 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ - -#if 0 -#define CFG_ENV_IS_IN_FLASH 0 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 -#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ -#endif - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_EEPROM_PAGE_WRITE_BITS 5 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_EEPROM_ADDR 0x050 -#define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ - -#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -/*#define CFG_L2*/ -#undef CFG_L2 - -/* #ifdef CONFIG_750CX*/ -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h deleted file mode 100644 index 93d49f3..0000000 --- a/include/configs/CPCIISER4.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "bootm fff00000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffe00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Uart 8bit) initialization */ -#define CFG_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */ -#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Uart 32bit) initialization */ -#define CFG_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */ -#define CFG_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ - -/* Memory Bank 3 (FPGA Reset) initialization */ -#define CFG_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */ -#define CFG_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ -#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h deleted file mode 100644 index 16a9ea5..0000000 --- a/include/configs/CPU86.h +++ /dev/null @@ -1,656 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_CPU86 1 /* ...on a CPU86 board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK11 - * - Tx-CLK is CLK12 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 64000000 /* in Hz */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT \ - "echo; " \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \ - "echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/*----------------------------------------------------------------------- - * I2C/EEPROM/RTC configuration - */ -#define CONFIG_SOFT_I2C /* Software I2C support enabled */ - -# define CFG_I2C_SPEED 50000 -# define CFG_I2C_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- - * Miscellaneous configuration options - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash configuration - */ - -#define CFG_BOOTROM_BASE 0xFF800000 -#define CFG_BOOTROM_SIZE 0x00080000 -#define CFG_FLASH_BASE 0xFF000000 -#define CFG_FLASH_SIZE 0x00800000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/*----------------------------------------------------------------------- - * Other areas to be mapped - */ - -/* CS3: Dual ported SRAM */ -#define CFG_DPSRAM_BASE 0x40000000 -#define CFG_DPSRAM_SIZE 0x00020000 - -/* CS4: DiskOnChip */ -#define CFG_DOC_BASE 0xF4000000 -#define CFG_DOC_SIZE 0x00100000 - -/* CS5: FDC37C78 controller */ -#define CFG_FDC37C78_BASE 0xF1000000 -#define CFG_FDC37C78_SIZE 0x00100000 - -/* CS6: Board configuration registers */ -#define CFG_BCRS_BASE 0xF2000000 -#define CFG_BCRS_SIZE 0x00010000 - -/* CS7: VME Extended Access Range */ -#define CFG_VMEEAR_BASE 0x80000000 -#define CFG_VMEEAR_SIZE 0x01000000 - -/* CS8: VME Standard Access Range */ -#define CFG_VMESAR_BASE 0xFE000000 -#define CFG_VMESAR_SIZE 0x01000000 - -/* CS9: VME Short I/O Access Range */ -#define CFG_VMESIOAR_BASE 0xFD000000 -#define CFG_VMESIOAR_SIZE 0x01000000 - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#if defined(CONFIG_BOOT_ROM) -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ - HRCW_BPS01 | HRCW_CS10PC01) -#else -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01) -#endif - -/* no slaves so just fill with zeros */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CFG_SDRAM_BASE. - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#if 0 -/* environment is in Flash */ -#define CFG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_BOOT_ROM -# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000) -# define CFG_ENV_SIZE 0x10000 -# define CFG_ENV_SECT_SIZE 0x10000 -#endif -#else -/* environment is in EEPROM */ -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_ENV_OFFSET 512 -#define CFG_ENV_SIZE (2048 - 512) -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ - HID0_DCI|HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define BCR_APD01 0x10000000 -#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ - SIUMCR_CS10PC01|SIUMCR_BCTLC10) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -#define CFG_MIN_AM_MASK 0xC0000000 -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescaler Register 10-18 - *----------------------------------------------------------------------- - */ -#define CFG_MPTPR 0x1F00 - -/*----------------------------------------------------------------------- - * PSRT - Refresh Timer Register 10-16 - *----------------------------------------------------------------------- - */ -#define CFG_PSRT 0x0f - -/*----------------------------------------------------------------------- - * PSRT - SDRAM Mode Register 10-10 - *----------------------------------------------------------------------- - */ - - /* SDRAM initialization values for 8-column chips - */ -#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit Boot ROM - * 1 60x GPCM 64 bit FLASH - * 2 60x SDRAM 64 bit SDRAM - * - */ - -#define CFG_MRS_OFFS 0x00000000 - -#ifdef CONFIG_BOOT_ROM -/* Bank 0 - Boot ROM - */ -#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 1 - FLASH - */ -#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) - -#else /* CONFIG_BOOT_ROM */ -/* Bank 0 - FLASH - */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 1 - Boot ROM - */ -#define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) - -#endif /* CONFIG_BOOT_ROM */ - - -/* Bank 2 - 60x bus SDRAM - */ -#ifndef CFG_RAMBOOT -#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_OR2_PRELIM CFG_OR2_9COL - -#define CFG_PSDMR CFG_PSDMR_9COL -#endif /* CFG_RAMBOOT */ - -/* Bank 3 - Dual Ported SRAM - */ -#define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) - -/* Bank 4 - DiskOnChip - */ -#define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 5 - FDC37C78 controller - */ -#define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_8_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 6 - Board control registers - */ -#define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\ - ORxG_CSNT |\ - ORxG_SCY_5_CLK) - -/* Bank 7 - VME Extended Access Range - */ -#define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) - -/* Bank 8 - VME Standard Access Range - */ -#define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) - -/* Bank 9 - VME Short I/O Access Range - */ -#define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h deleted file mode 100644 index a23d7e5..0000000 --- a/include/configs/CPU87.h +++ /dev/null @@ -1,682 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_CPU87 1 /* ...on a CPU87 board */ -#define CONFIG_PCI -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ - -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK11 - * - Tx-CLK is CLK12 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT \ - "echo; " \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \ - "echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/*----------------------------------------------------------------------- - * I2C/EEPROM/RTC configuration - */ -#define CONFIG_SOFT_I2C /* Software I2C support enabled */ - -# define CFG_I2C_SPEED 50000 -# define CFG_I2C_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- - * Miscellaneous configuration options - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#ifdef CONFIG_PCI -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_PCI) -#else /* ! PCI */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C ) -#endif /* CONFIG_PCI */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ - -#define CONFIG_LOOPW - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash configuration - */ - -#define CFG_BOOTROM_BASE 0xFF800000 -#define CFG_BOOTROM_SIZE 0x00080000 -#define CFG_FLASH_BASE 0xFF000000 -#define CFG_FLASH_SIZE 0x00800000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/*----------------------------------------------------------------------- - * Other areas to be mapped - */ - -/* CS3: Dual ported SRAM */ -#define CFG_DPSRAM_BASE 0x40000000 -#define CFG_DPSRAM_SIZE 0x00100000 - -/* CS4: DiskOnChip */ -#define CFG_DOC_BASE 0xF4000000 -#define CFG_DOC_SIZE 0x00100000 - -/* CS5: FDC37C78 controller */ -#define CFG_FDC37C78_BASE 0xF1000000 -#define CFG_FDC37C78_SIZE 0x00100000 - -/* CS6: Board configuration registers */ -#define CFG_BCRS_BASE 0xF2000000 -#define CFG_BCRS_SIZE 0x00010000 - -/* CS7: VME Extended Access Range */ -#define CFG_VMEEAR_BASE 0x60000000 -#define CFG_VMEEAR_SIZE 0x01000000 - -/* CS8: VME Standard Access Range */ -#define CFG_VMESAR_BASE 0xFE000000 -#define CFG_VMESAR_SIZE 0x01000000 - -/* CS9: VME Short I/O Access Range */ -#define CFG_VMESIOAR_BASE 0xFD000000 -#define CFG_VMESIOAR_SIZE 0x01000000 - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#if defined(CONFIG_BOOT_ROM) -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ - HRCW_BPS01 | HRCW_CS10PC01) -#else -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01) -#endif - -/* no slaves so just fill with zeros */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CFG_SDRAM_BASE. - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#ifdef CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#endif - -#if 0 -/* environment is in Flash */ -#define CFG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_BOOT_ROM -# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000) -# define CFG_ENV_SIZE 0x10000 -# define CFG_ENV_SECT_SIZE 0x10000 -#endif -#else -/* environment is in EEPROM */ -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_ENV_OFFSET 512 -#define CFG_ENV_SIZE (2048 - 512) -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ - HID0_DCI|HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define BCR_APD01 0x10000000 -#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ - SIUMCR_CS10PC01|SIUMCR_BCTLC10) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -#define CFG_MIN_AM_MASK 0xC0000000 - -/* - * we use the same values for 32 MB and 128 MB SDRAM - * refresh rate = 7.68 uS (100 MHz Bus Clock) - */ - -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescaler Register 10-18 - *----------------------------------------------------------------------- - */ -#define CFG_MPTPR 0x2000 - -/*----------------------------------------------------------------------- - * PSRT - Refresh Timer Register 10-16 - *----------------------------------------------------------------------- - */ -#define CFG_PSRT 0x16 - -/*----------------------------------------------------------------------- - * PSRT - SDRAM Mode Register 10-10 - *----------------------------------------------------------------------- - */ - - /* SDRAM initialization values for 8-column chips - */ -#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit Boot ROM - * 1 60x GPCM 64 bit FLASH - * 2 60x SDRAM 64 bit SDRAM - * - */ - -#define CFG_MRS_OFFS 0x00000000 - -#ifdef CONFIG_BOOT_ROM -/* Bank 0 - Boot ROM - */ -#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 1 - FLASH - */ -#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) - -#else /* CONFIG_BOOT_ROM */ -/* Bank 0 - FLASH - */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 1 - Boot ROM - */ -#define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) - -#endif /* CONFIG_BOOT_ROM */ - - -/* Bank 2 - 60x bus SDRAM - */ -#ifndef CFG_RAMBOOT -#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_OR2_PRELIM CFG_OR2_9COL - -#define CFG_PSDMR CFG_PSDMR_9COL -#endif /* CFG_RAMBOOT */ - -/* Bank 3 - Dual Ported SRAM - */ -#define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_7_CLK |\ - ORxG_SETA) - -/* Bank 4 - DiskOnChip - */ -#define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_9_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 5 - FDC37C78 controller - */ -#define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_10_CLK |\ - ORxU_EHTR_8IDLE) - -/* Bank 6 - Board control registers - */ -#define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\ - ORxG_CSNT |\ - ORxG_SCY_7_CLK) - -/* Bank 7 - VME Extended Access Range - */ -#define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_7_CLK |\ - ORxG_SETA) - -/* Bank 8 - VME Standard Access Range - */ -#define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_7_CLK |\ - ORxG_SETA) - -/* Bank 9 - VME Short I/O Access Range - */ -#define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_7_CLK |\ - ORxG_SETA) - -#endif /* __CONFIG_H */ diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h deleted file mode 100644 index 63d7a92..0000000 --- a/include/configs/CRAYL1.h +++ /dev/null @@ -1,247 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite.. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_CRAYL1 -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ -#define CONFIG_SYS_CLK_FREQ 25000000 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */ -#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */ - -/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to - * keep possible initrd ramdisk decompression out. This is in k (1024 bytes) - #define CONFIG_PRAM 16 - */ -#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */ -#undef CONFIG_BOOTARGS - -/* Bootcmd is overridden by the bootscript in board/cray/L1 - */ -#define CFG_AUTOLOAD "no" -#define CONFIG_BOOTCOMMAND "dhcp" - -/* - * ..during experiments.. - #define CONFIG_SERVERIP 10.0.0.1 - #define CONFIG_ETHADDR 00:40:a6:80:14:5 - */ -#define CONFIG_HARD_I2C 1 /* hardware support for i2c */ -#define CONFIG_SDRAM_BANK0 1 -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_IDENT_STRING "Cray L1" -#define CONFIG_ENV_OVERWRITE 1 -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " -#define CONFIG_AUTOSCRIPT 1 - - -#define CONFIG_COMMANDS (\ - CFG_CMD_BDI|\ - CFG_CMD_IMI|\ - CFG_CMD_FLASH|\ - CFG_CMD_MEMORY|\ - CFG_CMD_NET|\ - CFG_CMD_ENV|\ - CFG_CMD_CONSOLE|\ - CFG_CMD_ASKENV|\ - CFG_CMD_ECHO|\ - CFG_CMD_IMMAP|\ - CFG_CMD_REGINFO|\ - CFG_CMD_DHCP|\ - CFG_CMD_DATE|\ - CFG_CMD_RUN|\ - CFG_CMD_I2C|\ - CFG_CMD_EEPROM|\ - CFG_CMD_DIAG|\ - CFG_CMD_AUTOSCRIPT|\ - CFG_CMD_SETGETDCR) - -/* - * optional BOOTP / DHCP fields - */ -#define CONFIG_BOOTP_MASK (\ - CONFIG_BOOTP_VENDOREX|\ - CONFIG_BOOTP_SUBNETMASK|\ - CONFIG_BOOTP_GATEWAY|\ - CONFIG_BOOTP_DNS|\ - CONFIG_BOOTP_HOSTNAME|\ - CONFIG_BOOTP_BOOTFILESIZE|\ - CONFIG_BOOTP_BOOTPATH) - -/* - * how many time to fail & restart a net-TFTP before giving up & resetting - * the board hoping that a reset of net interface might help.. - */ -#define CONFIG_NET_RESET 5 - -/* - * bauds. Just to make it compile; in our case, I read the base_baud - * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn - * drives the system clock. - */ -#define CFG_BASE_BAUD 403225 -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ - - -#define CFG_LOAD_ADDR 0x100000/* where to load what we get from TFTP */ -#define CFG_TFTP_LOADADDR CFG_LOAD_ADDR -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CFG_DRAM_TEST 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFC00000 -#define CFG_MONITOR_BASE TEXT_BASE - - -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */ -#define CFG_ENV_OFFSET 0x3c8000 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment area */ -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at - * 32meg-(128k+some_malloc_space+copy-of-ENV sector).. - */ -#define CFG_SDRAM_SIZE 32 /* megs of ram */ -#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CFG_MALLOC_LEN (128 << 10) /* 128k for malloc space */ -#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ - + CFG_MALLOC_LEN \ - + CFG_ENV_SECT_SIZE \ - + CFG_STACK_USAGE ) - -#define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE) -/* END ENVIRONNEMENT FLASH */ - -/*----------------------------------------------------------------------- - * Cache Configuration. Only used to ..?? clear it, I guess.. - */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in OnChipMem ) - */ -#if 1 -/* On Chip Memory location */ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR 0xF0000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#else -#define CFG_OCM_DATA_ADDR 0xF0000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#endif - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - */ -#define EEPROM_WRITE_ADDRESS 0xA0 -#define EEPROM_READ_ADDRESS 0xA1 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CU824.h b/include/configs/CU824.h deleted file mode 100644 index acc8484..0000000 --- a/include/configs/CU824.h +++ /dev/null @@ -1,312 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the CU824 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_CU824 1 - - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - 0 /* CFG_CMD_DATE */ | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -#if 1 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* Print Buffer Size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF000000 - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_EUMB_ADDR 0xFCE00000 - -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CFG_MAX_RAM_SIZE 0x10000000 - - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#undef CFG_RAMBOOT -#else -#define CFG_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - - /* Size in bytes reserved for initial data - */ -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 4 - -#define CFG_NS16550_CLK (14745600 / 2) - -#define CFG_NS16550_COM1 0xFE800080 -#define CFG_NS16550_COM2 0xFE8000C0 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 -#define CFG_HZ 1000 - - /* Bit-field values for MCCR1. - */ -#define CFG_ROMNAL 0 -#define CFG_ROMFAL 7 - - /* Bit-field values for MCCR2. - */ -#define CFG_REFINT 430 /* Refresh interval */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CFG_BSTOPRE 192 - - /* Bit-field values for MCCR3. - */ -#define CFG_REFREC 2 /* Refresh to activate interval */ -#define CFG_RDLAT 3 /* Data latancy from read command */ - - /* Bit-field values for MCCR4. - */ -#define CFG_PRETOACT 2 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CFG_ACTORW 2 -#define CFG_REGISTERD_TYPE_BUFFER 1 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff -#define CFG_BANK7_ENABLE 0 - -#define CFG_ODCR 0xff - -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CFG_ENV_IS_IN_FLASH 1 -#if 0 -#define CFG_ENV_ADDR 0xFF008000 -#define CFG_ENV_SIZE 0x8000 /* Size of the Environment Sector */ -#else -#define CFG_ENV_ADDR 0xFFFC0000 -#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */ -#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_TULIP -#define CONFIG_TULIP_USE_IO - -#define CFG_ETH_DEV_FN 0x7800 -#define CFG_ETH_IOBASE 0x00104000 - -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define PCI_ENET0_IOADDR 0x00104000 -#define PCI_ENET0_MEMADDR 0x80000000 -#endif /* __CONFIG_H */ diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h deleted file mode 100644 index 997e1ba..0000000 --- a/include/configs/DASA_SIM.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_IOP480 1 /* This is a IOP480 CPU */ -#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_CPUCLOCK 66 -#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK) - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm ffe00000" /* autoboot command */ - -#undef CONFIG_BOOTARGS - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_IPADDR 10.0.18.222 -#define CONFIG_SERVERIP 10.0.18.190 - -#if 0 -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_BSP | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ELF ) -#else -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP ) -#endif - -#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */ -#define CONFIG_SOFT_I2C /* Software I2C support enabled */ -#endif -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFD0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 128 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0002 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0000 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0004 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ - -#if 0 -#define CFG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */ -#else -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_TULIP - -#define CFG_ETH_DEV_FN 0x0000 -#define CFG_ETH_IOBASE 0x0fff0000 -#define CFG_PCI9054_DEV_FN 0x0800 -#define CFG_PCI9054_IOBASE 0x0eff0000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ -#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h deleted file mode 100644 index bd7aff1..0000000 --- a/include/configs/DB64360.h +++ /dev/null @@ -1,596 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -/************************************************************************* - * (c) 2002 Datentechnik AG - Project: Dino - * - * - * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $ - * - ************************************************************************/ - -/************************************************************************* - * - * History: - * - * $Log: DB64360.h,v $ - * Revision 1.3 2003/04/26 04:58:13 brad - * Cosmetic changes and compiler warning cleanups - * - * Revision 1.2 2003/04/23 15:48:15 ingo - * mem. map output added - * - * Revision 1.1 2003/04/17 09:31:42 ias - * keymile changes 17_04_2003 - * - * Revision 1.10 2003/03/06 12:25:04 ias - * 750 FX CPU HID settings updated - * - * Revision 1.9 2003/03/03 16:14:36 ias - * cleanup compiler warnings of printf fuctions - * - * Revision 1.8 2003/03/03 15:11:44 ias - * Marvell MPSC-UART is working - * - * Revision 1.7 2003/02/26 12:15:45 ssu - * adapted default parameters to new board flash address - * - * Revision 1.6 2003/02/25 14:55:42 ssu - * changed default environment parameters - * - * Revision 1.5 2003/02/21 17:14:23 ias - * added extended SPD handling - * - * Revision 1.4 2003/01/14 09:16:08 ias - * PPCBoot for Marvel Beta 0.9 - * - * Revision 1.3 2002/12/03 13:56:26 ias - * Environment in flash support added - * - * Revision 1.2 2002/11/29 16:53:29 ias - * Flash support for STM added - * - * Revision 1.1 2002/11/29 13:36:31 ias - * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board - * - working DDRRAM (only 32MByte of 128MB Modul) - * - working I2C Driver for SPD EEPROM read - * - working DUART 16650 for Serial Console - * - working "console" - * - * - * - ************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_DB64360 1 /* this is an DB64360 board */ - -#ifndef __ASSEMBLY__ -#include "../board/Marvell/include/core.h" -#endif - -/*-----------------------------------------------------*/ -/* #include "../board/db64360/local.h" */ -#ifndef __LOCAL_H -#define __LOCAL_H - -/* first ethernet */ -#define CONFIG_ETHADDR 64:36:00:00:00:01 - /* next two ethernet hwaddrs */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 64:36:00:00:00:02 -/* in the atlantis 64360 we have only 2 ETH port on the board, -if we use PCI it has its own MAC addr */ - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_74xx /* we have a 750FX (override local.h) */ - -#define CONFIG_DB64360 1 /* this is an DB64360 board */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ -/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the - DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. - so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, - see sdram_init.c */ -#undef CONFIG_ECC /* enable ECC support */ -#define CONFIG_MV64360_ECC - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ -#define CONFIG_BOARD_EARLY_INIT_F - -#define CFG_BOARD_NAME "DB64360" -#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)" - -/*#define CFG_HUSH_PARSER */ -#undef CFG_HUSH_PARSER - -#define CFG_PROMPT_HUSH_PS2 "> " - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ - -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define CONFIG_NET_MULTI -#define MV_ETH_DEVS 2 - -/* #undef CONFIG_ETHER_PORT_MII */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ - -/* ronen - autoboot using tftp */ -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ - ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#endif - -/* ronen - the u-boot.bin should be ~0x30000 bytes */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ - "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ - "bootargs_root=root=/dev/nfs rw\0" \ - "bootargs_end=:::DB64360:eth0:none \0"\ - "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ -ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" - -/* --------------------------------------------------------------------------------------------------------------- */ -/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */ - -#define CONFIG_IPADDR 10.2.40.90 - -#define CONFIG_SERIAL "No. 1" -#define CONFIG_SERVERIP 10.2.1.126 -#define CONFIG_ROOTPATH /mnt/yellow_dog_mini - - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* --------------------------------------------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor1=db64360-1" -#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)" -*/ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ - | CFG_CMD_EEPROM \ - | CFG_CMD_CACHE \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_PCI \ - | CFG_CMD_NET ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_SPEED 40000 /* I2C speed default */ - -/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CFG_MEMTEST_START 0x00400000 memtest works on */ -/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ - -/* -#define CFG_DRAM_TEST - * DRAM tests - * CFG_DRAM_TEST - enables the following tests. - * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CFG_DRAM_TEST -#if defined(CFG_DRAM_TEST) -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CFG_DRAM_TEST_DATA -#define CFG_DRAM_TEST_ADDRESS -#define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ - -#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CFG_LOAD_ADDR 0x00400000 /* default load address */ - -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CFG_BUS_CLK CFG_BUS_HZ - -#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ -#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ - -/*ronen - this is the Tclk (MV64360 core) */ -#define CFG_TCLK 133000000 - - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_750FX_HID0 0x8000c084 -#define CFG_750FX_HID1 0x54800000 -#define CFG_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#define CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */ -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR - #define CFG_INTERNAL_RAM_ADDR 0xf8000000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CFG_SDRAM2_BASE 0x20000000 -#define CFG_SDRAM3_BASE 0x30000000 -#define CFG_SDRAM4_BASE 0x40000000 -#define CFG_FLASH_BASE 0xfff00000 - -#define CFG_DFL_BOOTCS_BASE 0xff800000 -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ - -#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ -#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the db64360 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CFG_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */ - -#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */ -#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ -#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ -#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */ - -#define CFG_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */ -#define CFG_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */ -#define CFG_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */ -#define CFG_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */ -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ -#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ -#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ -#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ -#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* ronen - update MPP Control MV64360*/ -#define CFG_MPP_CONTROL_0 0x02222222 -#define CFG_MPP_CONTROL_1 0x11333011 -#define CFG_MPP_CONTROL_2 0x40431111 -#define CFG_MPP_CONTROL_3 0x00000044 - -/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - - -# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ - /* gpp[31] gpp[30] gpp[29] gpp[28] */ - /* gpp[27] gpp[24]*/ - /* gpp[19:14] */ - -/* setup new config_value for MV64360 DDR-RAM !! */ -# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - -#define CFG_DUART_IO CFG_DEV2_SPACE -#define CFG_DUART_CHAN 1 /* channel to use for console */ -#define CFG_INIT_CHAN1 -#define CFG_INIT_CHAN2 - -#define SRAM_BASE CFG_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M - -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M - -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ - -#if defined (CONFIG_750CX) -#define CFG_PCI_IDSEL 0x0 -#else -#define CFG_PCI_IDSEL 0x30 -#endif -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ -#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ -#define CFG_FLASH_CFI 1 - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 -#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -#define CFG_L2 - - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else - -#define L2_INIT 0 -/* -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -*/ -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h deleted file mode 100644 index 4b72e9b..0000000 --- a/include/configs/DB64460.h +++ /dev/null @@ -1,534 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_DB64460 1 /* this is an DB64460 board */ - -#ifndef __ASSEMBLY__ -#include "../board/Marvell/include/core.h" -#endif - -/*-----------------------------------------------------*/ -/* #include "../board/db64460/local.h" */ -#ifndef __LOCAL_H -#define __LOCAL_H - -#define CONFIG_ETHADDR 64:46:00:00:00:01 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 64:46:00:00:00:02 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 64:46:00:00:00:03 - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_74xx /* we have a 750FX (override local.h) */ - -#define CONFIG_DB64460 1 /* this is an DB64460 board */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ -/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the - DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. - so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, - see sdram_init.c */ -#undef CONFIG_ECC /* enable ECC support */ -#define CONFIG_MV64460_ECC - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ -#define CONFIG_BOARD_EARLY_INIT_F - -#define CFG_BOARD_NAME "DB64460" -#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)" - -/*#define CFG_HUSH_PARSER */ -#undef CFG_HUSH_PARSER - -#define CFG_PROMPT_HUSH_PS2 "> " - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ - -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define CONFIG_NET_MULTI -#define MV_ETH_DEVS 3 - -/* #undef CONFIG_ETHER_PORT_MII */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ - -/* ronen - autoboot using tftp */ -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ - ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#endif - -/* ronen - the u-boot.bin should be ~0x30000 bytes */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ - "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ - "bootargs_root=root=/dev/nfs rw\0" \ - "bootargs_end=:::DB64460:eth0:none \0"\ - "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ -ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" - -/* --------------------------------------------------------------------------------------------------------------- */ -/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */ - -#define CONFIG_IPADDR 10.2.40.90 - -#define CONFIG_SERIAL "No. 1" -#define CONFIG_SERVERIP 10.2.1.126 -#define CONFIG_ROOTPATH /mnt/yellow_dog_mini - - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* --------------------------------------------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor1=db64460-1" -#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)" -*/ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ - | CFG_CMD_EEPROM \ - | CFG_CMD_CACHE \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_PCI \ - | CFG_CMD_NET ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_SPEED 40000 /* I2C speed default */ - -/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CFG_MEMTEST_START 0x00400000 memtest works on */ -/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ - -/* -#define CFG_DRAM_TEST - * DRAM tests - * CFG_DRAM_TEST - enables the following tests. - * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CFG_DRAM_TEST -#if defined(CFG_DRAM_TEST) -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CFG_DRAM_TEST_DATA -#define CFG_DRAM_TEST_ADDRESS -#define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ - -#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CFG_LOAD_ADDR 0x00400000 /* default load address */ - -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ -#define CFG_BUS_CLK CFG_BUS_HZ - -#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ -#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */ - -/*ronen - this is the Tclk (MV64460 core) */ -#define CFG_TCLK 133000000 - - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_750FX_HID0 0x8000c084 -#define CFG_750FX_HID1 0x54800000 -#define CFG_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#define CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */ -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR - #define CFG_INTERNAL_RAM_ADDR 0xf8000000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CFG_SDRAM2_BASE 0x20000000 -#define CFG_SDRAM3_BASE 0x30000000 -#define CFG_SDRAM4_BASE 0x40000000 -#define CFG_FLASH_BASE 0xfff00000 - -#define CFG_DFL_BOOTCS_BASE 0xff800000 -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ - -#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ -#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the db64460 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CFG_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */ - -#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */ -#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ -#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ -#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */ - -#define CFG_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */ -#define CFG_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */ -#define CFG_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */ -#define CFG_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */ -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ -#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ -#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ -#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ -#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* ronen - update MPP Control MV64460*/ -#define CFG_MPP_CONTROL_0 0x02222222 -#define CFG_MPP_CONTROL_1 0x11333011 -#define CFG_MPP_CONTROL_2 0x40431111 -#define CFG_MPP_CONTROL_3 0x00000044 - -/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - - -# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ - /* gpp[31] gpp[30] gpp[29] gpp[28] */ - /* gpp[27] gpp[24]*/ - /* gpp[19:14] */ - -/* setup new config_value for MV64460 DDR-RAM !! */ -# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - -#define CFG_DUART_IO CFG_DEV2_SPACE -#define CFG_DUART_CHAN 1 /* channel to use for console */ -#define CFG_INIT_CHAN1 -#define CFG_INIT_CHAN2 - -#define SRAM_BASE CFG_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M - -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M - -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ - -#if defined (CONFIG_750CX) -#define CFG_PCI_IDSEL 0x0 -#else -#define CFG_PCI_IDSEL 0x30 -#endif -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ -#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ -#define CFG_FLASH_CFI 1 - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 -#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -#define CFG_L2 - - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else - -#define L2_INIT 0 -/* -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -*/ -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h deleted file mode 100644 index b58846d..0000000 --- a/include/configs/DK1C20.h +++ /dev/null @@ -1,556 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * Stephan Linz - * - * CompactFlash/IDE: - * (C) Copyright 2004, Shlomo Kut - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************************** - * Include the whole NIOS CPU configuration. - * - * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! - * - ***********************************************************************/ - -#if defined(CONFIG_NIOS_SAFE_32) -#include -#elif defined(CONFIG_NIOS_STANDARD_32) -#include -#else -#error *** CFG_ERROR: you have to setup right NIOS CPU configuration -#endif - -/*------------------------------------------------------------------------ - * BOARD/CPU -- TOP-LEVEL - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS 1 /* NIOS-32 core */ -#define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/ -#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */ -#define CFG_HZ 1000 /* 1 msec time tick */ -#undef CFG_CLKS_IN_HZ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_SDRAM_SIZE != 0) - -#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE -#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE - -#else -#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config -#endif - -#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE -#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE -#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - For the most part, you can put things pretty - * much anywhere. This is pretty flexible for Nios. So here we make some - * arbitrary choices & assume that the monitor is placed at the end of - * a memory resource (so you must make sure TEXT_BASE is chosen - * appropriately). - * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP CFG_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_FLASH_SIZE != 0) - -#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE -#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE -#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ - -#else -#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * ENVIRONMENT - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_FLASH_SIZE != 0) - -#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */ -#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ - -#else -#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */ -#endif - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_UART_NUMS != 0) - -#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */ - -#if (CFG_NIOS_CPU_UART0_BR != 0) -#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR -#else -#undef CFG_NIOS_FIXEDBAUD -#define CONFIG_BAUDRATE 115200 -#endif - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#else -#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, - * so an avalon bus timer is required. - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_TIMER_NUMS != 0) - -#if (CFG_NIOS_CPU_TICK_TIMER == 0) - -#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */ -#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ - -#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ - -#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ) -#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ) -#else -#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ -#endif - -#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */ - -#if (CFG_HZ <= 1000) -#define CFG_NIOS_TMRMS (1000 / CFG_HZ) -#else -#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 -#endif - -#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) - -#else -#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct -#endif - -#elif (CFG_NIOS_CPU_TICK_TIMER == 1) - -#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */ -#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ - -#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ - -#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ) -#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ) -#else -#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ -#endif - -#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */ - -#if (CFG_HZ <= 1000) -#define CFG_NIOS_TMRMS (1000 / CFG_HZ) -#else -#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 -#endif - -#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) - -#else -#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct -#endif - -#endif /* CFG_NIOS_CPU_TICK_TIMER */ - -#else -#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * Ethernet - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_LAN_NUMS == 1) - -#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) - -#if (CFG_NIOS_CPU_LAN0_BUSW == 32) -#define CONFIG_SMC_USE_32_BIT 1 -#else /* no */ -#undef CONFIG_SMC_USE_32_BIT -#endif - -#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ - - /********************************************/ - /* !!! CS8900 is __not__ tested on NIOS !!! */ - /********************************************/ -#define CONFIG_DRIVER_CS8900 /* Using CS8900 */ -#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) - -#if (CFG_NIOS_CPU_LAN0_BUSW == 32) -#undef CS8900_BUS16 -#define CS8900_BUS32 1 -#else /* no */ -#define CS8900_BUS16 1 -#undef CS8900_BUS32 -#endif - -#else -#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config -#endif - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - -#else -#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h -#endif - -/*------------------------------------------------------------------------ - * STATUS LEDs - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_PIO_NUMS != 0) - -#if (CFG_NIOS_CPU_LED_PIO == 0) - -#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 1) - -#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 2) - -#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2 -#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CFG_NIOS_CPU_PIO2_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CFG_NIOS_CPU_LED_PIO == 3) - -#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 4) - -#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 5) - -#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 6) - -#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 7) - -#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 8) - -#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 9) - -#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h - -#else -#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case -#endif - -#define CONFIG_STATUS_LED 1 /* enable status led driver */ - -#define STATUS_LED_BIT (1 << 0) /* LED[0] */ -#define STATUS_LED_STATE STATUS_LED_BLINKING -#define STATUS_LED_BOOT_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_BOOT 0 /* boot LED */ - -#if (STATUS_LED_BITS > 1) -#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */ -#define STATUS_LED_RED 1 /* fail LED */ -#endif - -#if (STATUS_LED_BITS > 2) -#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_YELLOW 2 /* info LED */ -#endif - -#if (STATUS_LED_BITS > 3) -#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ -#define STATUS_LED_STATE3 STATUS_LED_OFF -#define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_GREEN 3 /* info LED */ -#endif - -#define STATUS_LED_PAR 1 /* makes status_led.h happy */ - -#endif /* CFG_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * SEVEN SEGMENT LED DISPLAY - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_PIO_NUMS != 0) - -#if (CFG_NIOS_CPU_SEVENSEG_PIO == 0) - -#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1) - -#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2) - -#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3) - -#define SEVENSEG_BASE CFG_NIOS_CPU_PIO3 -#define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS -#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */ - -#if (CFG_NIOS_CPU_PIO3_TYPE == 1) -#define SEVENSEG_WRONLY 1 -#else -#undef SEVENSEG_WRONLY -#endif - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4) - -#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5) - -#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6) - -#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7) - -#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8) - -#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9) - -#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h - -#else -#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case -#endif - -#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */ - -/* - * Dual 7-Segment Display pin assignment -- read more in your - * "Nios Development Board Reference Manual" - * - * - * (U8) HI:D[15..8] (U9) LO:D[7..0] - * ______ ______ - * | D14 | | D6 | - * | | | | - * D9| |D13 D1| |D5 - * |______| |______| ___ - * | D8 | | D0 | | A | - * | | | | F|___|B - * D10| |D12 D2| |D4 | G | - * |______| |______| E|___|C - * D11 * D3 * D * - * D15 D7 DP - * - */ -#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */ -#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */ -#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */ -#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */ -#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */ -#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */ -#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */ -#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */ -#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */ - -#endif /* CFG_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * ASMI - Active Serial Memory Interface. - * - * ASMI is for Cyclone devices only and only works when the configuration - * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details. - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS_ASMI /* Enable ASMI */ -#define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */ - -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGDB | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_MMC | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_REISER | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_VFD | \ - CFG_CMD_USB | \ - CFG_CMD_XIMG ) ) - - -#include - -/*------------------------------------------------------------------------ - * COMPACT FLASH - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CONFIG_IDE_PREINIT /* Implement id_preinit */ -#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0x00920a00 /* IDE/ATA base addr */ -#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ -#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ -#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */ -#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ -#define CFG_ATA_STRIDE 4 /* Width betwix addrs */ -#define CONFIG_DOS_PARTITION - -/* Board-specific cf regs */ -#define CFG_CF_PRESENT 0x009209b0 /* CF Present PIO base */ -#define CFG_CF_POWER 0x009209c0 /* CF Power FET PIO base*/ -#define CFG_CF_ATASEL 0x009209d0 /* CF ATASEL PIO base */ - -#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ - -/*------------------------------------------------------------------------ - * KGDB - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 9600 -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "DK1C20 > " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args*/ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#if (CFG_SRAM_SIZE != 0) -#define CFG_LOAD_ADDR CFG_SRAM_BASE /* Default load address */ -#else -#undef CFG_LOAD_ADDR -#endif - -#if (CFG_SDRAM_SIZE != 0) -#define CFG_MEMTEST_START CFG_SDRAM_BASE /* SDRAM til stack area */ -#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */ -#else -#undef CFG_MEMTEST_START -#undef CFG_MEMTEST_END -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/DK1C20_safe_32.h b/include/configs/DK1C20_safe_32.h deleted file mode 100644 index a483e87..0000000 --- a/include/configs/DK1C20_safe_32.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1C20_SAFE_32_H -#define __CONFIG_DK1C20_SAFE_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1C20.h) - * - * !!! TODO !!! TODO !!! - */ -#error *** CFG_ERROR: DK1C20_safe_32 have to be defined (use DK1C20_standard_32 as template) - -#endif /* __CONFIG_DK1C20_SAFE_32_H */ diff --git a/include/configs/DK1C20_standard_32.h b/include/configs/DK1C20_standard_32.h deleted file mode 100644 index ed08121..0000000 --- a/include/configs/DK1C20_standard_32.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1C20_STANDARD_32_H -#define __CONFIG_DK1C20_STANDARD_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1C20.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: - * - * #define CFG_NIOS_CPU_ICACHE 4096 - * #define CFG_NIOS_CPU_DCACHE 0 - * #define CFG_NIOS_CPU_OCI_BASE 0 - * #define CFG_NIOS_CPU_OCI_SIZE 0 - */ - -/* CPU core */ -#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ -#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ -#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ -#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ -#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ -#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ -#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* on-chip extensions */ -#define CFG_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */ -#define CFG_NIOS_CPU_RAM_SIZE 0 /* size */ - -#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ -#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ -#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ - -/* timer */ -#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ - -#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ -#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ -#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ -#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ - -#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ -#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ -#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ - -#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ -#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ -#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ -#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ -#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ -#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ -#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ -#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ -#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ -#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ -#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ -#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ -#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ -#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ -#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ - -/* active serial memory i/f */ -#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */ -#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */ -#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */ - -/* memory accessibility */ -#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ -#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ - -#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ -#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ -#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ -#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: alteramac(2) */ - -/* symbolic redefinition (undef, if not present) */ -#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ -#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ - -#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ -#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ -#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ -#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ -#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ -#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ -#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ -#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ - -#endif /* __CONFIG_DK1C20_STANDARD_32_H */ diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h deleted file mode 100644 index 3e3803c..0000000 --- a/include/configs/DK1S10.h +++ /dev/null @@ -1,565 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************************** - * Include the whole NIOS CPU configuration. - * - * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! - * - ***********************************************************************/ - -#if defined(CONFIG_NIOS_SAFE_32) -#include -#elif defined(CONFIG_NIOS_STANDARD_32) -#include -#elif defined(CONFIG_NIOS_MTX_LDK_20) -#include -#else -#error *** CFG_ERROR: you have to setup right NIOS CPU configuration -#endif - -/*------------------------------------------------------------------------ - * BOARD/CPU -- TOP-LEVEL - *----------------------------------------------------------------------*/ -#define CONFIG_NIOS 1 /* NIOS-32 core */ -#define CONFIG_DK1S10 1 /* Stratix DK-1S10 board*/ -#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */ -#define CFG_HZ 1000 /* 1 msec time tick */ -#undef CFG_CLKS_IN_HZ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_SDRAM_SIZE != 0) - -#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE -#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE - -#else -#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config -#endif - -#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE) - -#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE -#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE - -#else - -#undef CFG_SRAM_BASE -#undef CFG_SRAM_SIZE - -#endif - -#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - For the most part, you can put things pretty - * much anywhere. This is pretty flexible for Nios. So here we make some - * arbitrary choices & assume that the monitor is placed at the end of - * a memory resource (so you must make sure TEXT_BASE is chosen - * appropriately). - * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP CFG_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_FLASH_SIZE != 0) - -#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE -#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE -#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ - -#else -#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * ENVIRONMENT - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_FLASH_SIZE != 0) - -#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ - -#if defined(CONFIG_NIOS_STANDARD_32) -#define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */ -#elif defined(CONFIG_NIOS_MTX_LDK_20) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) -#else -#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR -#endif - -#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ - -#else -#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */ -#endif - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_UART_NUMS != 0) - -#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#if (CFG_NIOS_CPU_UART0_BR != 0) -#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR -#else -#undef CFG_NIOS_FIXEDBAUD -#define CONFIG_BAUDRATE 115200 -#endif - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#else -#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, - * so an avalon bus timer is required. - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER) - -#if (CFG_NIOS_CPU_TICK_TIMER == 0) - -#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */ -#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ - -#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */ - -#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ) -#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ) -#else -#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ -#endif - -#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */ - -#if (CFG_HZ <= 1000) -#define CFG_NIOS_TMRMS (1000 / CFG_HZ) -#else -#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 -#endif - -#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) - -#else -#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct -#endif - -#elif (CFG_NIOS_CPU_TICK_TIMER == 1) - -#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */ -#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ - -#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */ - -#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ) -#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ) -#else -#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ -#endif - -#undef CFG_NIOS_TMRCNT /* no preloadable counter value */ - -#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */ - -#if (CFG_HZ <= 1000) -#define CFG_NIOS_TMRMS (1000 / CFG_HZ) -#else -#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000 -#endif - -#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ) - -#else -#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct -#endif - -#endif /* CFG_NIOS_CPU_TICK_TIMER */ - -#else -#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config -#endif - -/*------------------------------------------------------------------------ - * Ethernet -- needs work! - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_LAN_NUMS == 1) - -#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) - -#if (CFG_NIOS_CPU_LAN0_BUSW == 32) -#define CONFIG_SMC_USE_32_BIT 1 -#else /* no */ -#undef CONFIG_SMC_USE_32_BIT -#endif - -#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */ - - /********************************************/ - /* !!! CS8900 is __not__ tested on NIOS !!! */ - /********************************************/ -#define CONFIG_DRIVER_CS8900 /* Using CS8900 */ -#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) - -#if (CFG_NIOS_CPU_LAN0_BUSW == 32) -#undef CS8900_BUS16 -#define CS8900_BUS32 1 -#else /* no */ -#define CS8900_BUS16 1 -#undef CS8900_BUS32 -#endif - -#else -#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config -#endif - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - -#else -#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h -#endif - -/*------------------------------------------------------------------------ - * STATUS LEDs - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO) - -#if (CFG_NIOS_CPU_LED_PIO == 0) - -#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 1) - -#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 2) - -#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2 -#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS -#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -#if (CFG_NIOS_CPU_PIO2_TYPE == 1) -#define STATUS_LED_WRONLY 1 -#else -#undef STATUS_LED_WRONLY -#endif - -#elif (CFG_NIOS_CPU_LED_PIO == 3) - -#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 4) - -#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 5) - -#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 6) - -#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 7) - -#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 8) - -#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_LED_PIO == 9) - -#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h - -#else -#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case -#endif - -#define CONFIG_STATUS_LED 1 /* enable status led driver */ - -#define STATUS_LED_BIT (1 << 0) /* LED[0] */ -#define STATUS_LED_STATE STATUS_LED_BLINKING -#define STATUS_LED_BOOT_STATE STATUS_LED_OFF -#define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_BOOT 0 /* boot LED */ - -#if (STATUS_LED_BITS > 1) -#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */ -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */ -#define STATUS_LED_RED 1 /* fail LED */ -#endif - -#if (STATUS_LED_BITS > 2) -#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */ -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_YELLOW 2 /* info LED */ -#endif - -#if (STATUS_LED_BITS > 3) -#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */ -#define STATUS_LED_STATE3 STATUS_LED_OFF -#define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */ -#define STATUS_LED_GREEN 3 /* info LED */ -#endif - -#define STATUS_LED_PAR 1 /* makes status_led.h happy */ - -#endif /* CFG_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * SEVEN SEGMENT LED DISPLAY - *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO) - -#if (CFG_NIOS_CPU_SEVENSEG_PIO == 0) - -#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1) - -#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2) - -#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3) - -#define SEVENSEG_BASE CFG_NIOS_CPU_PIO3 -#define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS -#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */ - -#if (CFG_NIOS_CPU_PIO3_TYPE == 1) -#define SEVENSEG_WRONLY 1 -#else -#undef SEVENSEG_WRONLY -#endif - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4) - -#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5) - -#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6) - -#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7) - -#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8) - -#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h - -#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9) - -#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h - -#else -#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case -#endif - -#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */ - -/* - * Dual 7-Segment Display pin assignment -- read more in your - * "Nios Development Board Reference Manual" - * - * - * (U8) HI:D[15..8] (U9) LO:D[7..0] - * ______ ______ - * | D14 | | D6 | - * | | | | - * D9| |D13 D1| |D5 - * |______| |______| ___ - * | D8 | | D0 | | A | - * | | | | F|___|B - * D10| |D12 D2| |D4 | G | - * |______| |______| E|___|C - * D11 * D3 * D * - * D15 D7 DP - * - */ -#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */ -#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */ -#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */ -#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */ -#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */ -#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */ -#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */ -#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */ -#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */ - -#endif /* CFG_NIOS_CPU_PIO_NUMS */ - -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGDB | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_MMC | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_VFD | \ - CFG_CMD_USB | \ - CFG_CMD_XIMG ) ) - - -#include - -/*------------------------------------------------------------------------ - * KGDB - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 9600 -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "DK1S10 > " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args*/ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Default load address */ -#if (CFG_SRAM_SIZE != 0) - -/* default in SRAM */ -#define CFG_LOAD_ADDR CFG_SRAM_BASE - -#elif (CFG_SDRAM_SIZE != 0) - -/* default in SDRAM */ -#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) -#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) -#else -#define CFG_LOAD_ADDR CFG_SDRAM_BASE -#endif - -#else -#undef CFG_LOAD_ADDR /* force error break */ -#endif - - -/* MEM test area */ -#if (CFG_SDRAM_SIZE != 0) - -/* SDRAM begin to stack area (1MB stack) */ -#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) -#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) -#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) -#else -#define CFG_MEMTEST_START CFG_SDRAM_BASE -#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) -#endif - -#else -#undef CFG_MEMTEST_START /* force error break */ -#undef CFG_MEMTEST_END -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h deleted file mode 100644 index 4eb9629..0000000 --- a/include/configs/DK1S10_mtx_ldk_20.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1S10_MTX_LDK_20_H -#define __CONFIG_DK1S10_MTX_LDK_20_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1S10.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: - * - * #define CFG_NIOS_CPU_ICACHE 4096 - * #define CFG_NIOS_CPU_DCACHE 0 - * #define CFG_NIOS_CPU_OCI_BASE 0 - * #define CFG_NIOS_CPU_OCI_SIZE 0 - */ - -/* CPU core */ -#define CFG_NIOS_CPU_CLK 75000000 /* NIOS CPU clock */ -#define CFG_NIOS_CPU_ICACHE (0) /* instruction cache */ -#define CFG_NIOS_CPU_DCACHE (0) /* data cache */ -#define CFG_NIOS_CPU_REG_NUMS 512 /* number of register */ -#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_STACK 0x02000000 /* stack top addr */ -#define CFG_NIOS_CPU_VEC_BASE 0x01000000 /* IRQ vectors addr */ -#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CFG_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ -#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* The offset address in flash to check for the Nios signature "Ni". - * (see GM_FlashExec in germs_monitor.s) */ -#define CFG_NIOS_CPU_EXES_OFFS 0x0C - -/* on-chip extensions */ -#undef CFG_NIOS_CPU_RAM_BASE /* on chip RAM addr */ -#undef CFG_NIOS_CPU_RAM_SIZE /* 64 KB size */ - -#define CFG_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ -#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#undef CFG_NIOS_CPU_OCI_BASE /* OCI core addr */ -#undef CFG_NIOS_CPU_OCI_SIZE /* size */ - -/* timer */ -#define CFG_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ - -#define CFG_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ -#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CFG_NIOS_CPU_UART_NUMS 2 /* number of uarts */ - -#define CFG_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ -#define CFG_NIOS_CPU_UART0_IRQ 17 /* IRQ */ -#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CFG_NIOS_CPU_UART0_SB 2 /* stop bit */ -#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -#define CFG_NIOS_CPU_UART1 0x000008a0 /* UART1 addr */ -#define CFG_NIOS_CPU_UART1_IRQ 18 /* IRQ */ -#define CFG_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ -#define CFG_NIOS_CPU_UART1_DB 8 /* data bit */ -#define CFG_NIOS_CPU_UART1_SB 1 /* stop bit */ -#define CFG_NIOS_CPU_UART1_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CFG_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CFG_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CFG_NIOS_CPU_PIO_NUMS 2 /* number of parports */ - -#define CFG_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ -#undef CFG_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO0_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO0_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ -#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO1_BITS 4 /* number of bits */ -#define CFG_NIOS_CPU_PIO1_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CFG_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */ -#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ - -/* memory accessibility */ -#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ -#undef CFG_NIOS_CPU_SRAM_SIZE /* 1 MB size */ - -#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CFG_NIOS_CPU_FLASH_BASE 0x00800000 /* board Flash addr */ -#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CFG_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ -#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CFG_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ -#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: openmac(2) */ - /* ex: alteramac(3) */ - -/* symbolic redefinition (undef, if not present) */ -#define CFG_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ -#undef CFG_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ - -#define CFG_NIOS_CPU_CFPOWER_PIO 0 /* PIO0: CF power/sw. */ -#define CFG_NIOS_CPU_BUTTON_PIO 1 /* PIO1: buttons */ -#undef CFG_NIOS_CPU_LCD_PIO /* PIOx: ASCII LCD */ -#undef CFG_NIOS_CPU_LED_PIO /* PIOx: LED bar */ -#undef CFG_NIOS_CPU_SEVENSEG_PIO /* PIOx: 7-seg. display */ -#undef CFG_NIOS_CPU_RECONF_PIO /* PIOx: reconf pin */ -#undef CFG_NIOS_CPU_CFPRESENT_PIO /* PIOx: CF present IRQ */ -#undef CFG_NIOS_CPU_CFATASEL_PIO /* PIOx: CF ATA select */ - -#endif /* __CONFIG_DK1S10_MTX_LDK_20_H */ diff --git a/include/configs/DK1S10_safe_32.h b/include/configs/DK1S10_safe_32.h deleted file mode 100644 index 8541a11..0000000 --- a/include/configs/DK1S10_safe_32.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1S10_SAFE_32_H -#define __CONFIG_DK1S10_SAFE_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1S10.h) - * - * !!! TODO !!! TODO !!! - */ -#error *** CFG_ERROR: DK1S10_safe_32 have to be defined (use DK1S10_standard_32 as template) - -#endif /* __CONFIG_DK1S10_SAFE_32_H */ diff --git a/include/configs/DK1S10_standard_32.h b/include/configs/DK1S10_standard_32.h deleted file mode 100644 index b83c315..0000000 --- a/include/configs/DK1S10_standard_32.h +++ /dev/null @@ -1,274 +0,0 @@ -/* - * (C) Copyright 2003, Li-Pro.Net - * Stephan Linz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_DK1S10_STANDARD_32_H -#define __CONFIG_DK1S10_STANDARD_32_H - -/* - * NIOS CPU configuration. (PART OF configs/DK1S10.h) - * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: - * - * #define CFG_NIOS_CPU_ICACHE 4096 - * #define CFG_NIOS_CPU_DCACHE 0 - * #define CFG_NIOS_CPU_OCI_BASE 0 - * #define CFG_NIOS_CPU_OCI_SIZE 0 - */ - -/* CPU core */ -#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ -#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ -#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ -#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ -#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ -#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ -#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* on-chip extensions */ -#define CFG_NIOS_CPU_RAM_BASE 0x00900000 /* on chip RAM addr */ -#define CFG_NIOS_CPU_RAM_SIZE (64 * 1024) /* 64 KB size */ - -#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ -#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ -#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ - -/* timer */ -#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ - -#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ -#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ -#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ -#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ - -#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ -#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ -#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ - -#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ -#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ -#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ -#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ -#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ -#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ -#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ -#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ -#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ -#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ -#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ -#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ -#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ -#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ -#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ - -/* memory accessibility */ -#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ -#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ - -#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ -#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ -#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ -#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: alteramac(2) */ - -/* symbolic redefinition (undef, if not present) */ -#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ -#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ - -#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ -#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ -#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ -#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ -#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ -#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ -#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ -#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ - -#endif /* __CONFIG_DK1S10_STANDARD_32_H */ diff --git a/include/configs/DP405.h b/include/configs/DP405.h deleted file mode 100644 index 2ae794d..0000000 --- a/include/configs/DP405.h +++ /dev/null @@ -1,341 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_DP405 1 /* ...on a DP405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CFG_RAMBOOT 1 -#else -# undef CFG_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -#if 0 /* test-only */ -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ -#endif - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ -/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ -/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ -/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CFG_GPIO0_OSRH 0x40000540 /* 0 ... 15 */ -#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ -#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ -#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ -#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ -#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ -#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/DU405.h b/include/configs/DU405.h deleted file mode 100644 index 5489a53..0000000 --- a/include/configs/DU405.h +++ /dev/null @@ -1,315 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_IDENT_STRING " $Name: $" - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_DU405 1 /* ...on a DU405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "bootm fff00000" - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_DATE | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffe00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFD0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */ -#define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART_BA 0xF0300000 /* DUART Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ -#define SRAM_BA 0xF0200000 /* SRAM Base Address */ -#define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */ -#define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */ - -#define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (DUART) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR DUART_BA | 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (CompactFlash IDE) initialization */ -#define CFG_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB4CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 5 (SRAM) initialization */ -#define CFG_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB5CR SRAM_BA | 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 6 (DURAG Bus IO Space) initialization */ -#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB6CR DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/ - -/* Memory Bank 7 (DURAG Bus Mem Space) initialization */ -#define CFG_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB7CR DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */ - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h deleted file mode 100644 index 2c99b4b..0000000 --- a/include/configs/ELPPC.h +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2002 ELTEC Elektronik AG - * Frank Gottschling - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG -#define GTREGREAD(x) 0xffffffff /* needed for debug */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -#define CONFIG_ETHADDR 00:00:5b:ee:de:ad - -#define CONFIG_IPADDR 192.168.0.105 -#define CONFIG_SERVERIP 192.168.0.100 - -#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */ - -#define CONFIG_BAUDRATE 9600 /* console baudrate */ - -#undef CONFIG_WATCHDOG - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp 1000000; " \ - "setenv bootargs root=ramfs console=ttyS00,9600 " \ - "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \ - "${netmask}:${hostname}:eth0:none; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -/* - * choose between COM1 and COM2 as serial console - */ -#define CONFIG_CONS_INDEX 1 - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ - -#define CFG_HZ 1000 /* dec. freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -#define CFG_BOARD_ASM_INIT -#define CONFIG_MISC_INIT_R - -/* - * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP) - */ -#undef CFG_ADDRESS_MAP_A - -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x40000000 - -#define CFG_PCI_MEM_BUS 0x80000000 -#define CFG_PCI_MEM_PHYS 0x80000000 -#define CFG_PCI_MEM_SIZE 0x7d000000 - -#define CFG_ISA_MEM_BUS 0x00000000 -#define CFG_ISA_MEM_PHYS 0xfd000000 -#define CFG_ISA_MEM_SIZE 0x01000000 - -#define CFG_PCI_IO_BUS 0x00800000 -#define CFG_PCI_IO_PHYS 0xfe800000 -#define CFG_PCI_IO_SIZE 0x00400000 - -#define CFG_ISA_IO_BUS 0x00000000 -#define CFG_ISA_IO_PHYS 0xfe000000 -#define CFG_ISA_IO_SIZE 0x00800000 - -/* driver defines FDC,IDE,... */ -#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS -#define CFG_ISA_IO CFG_ISA_IO_PHYS -#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -#define CFG_USR_LED_BASE 0x78000000 -#define CFG_NVRAM_BASE 0xff000000 -#define CFG_UART_BASE 0xff400000 -#define CFG_FLASH_BASE 0xfff00000 - -#define MPC107_EUMB_ADDR 0xfce00000 -#define MPC107_EUMB_PI 0xfce41090 -#define MPC107_EUMB_GCR 0xfce41020 -#define MPC107_EUMB_IACKR 0xfce600a0 -#define MPC107_I2C_ADDR 0xfce03000 - -/* - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */ -#define CFG_INIT_RAM_END 0x4000 -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Flash mapping/organization on the MPC10x. - */ -#define FLASH_BASE0_PRELIM 0xff800000 -#define FLASH_BASE1_PRELIM 0xffc00000 - -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1" -#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)" -*/ - -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */ -#undef CFG_MEMTEST - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CFG_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */ -#define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */ -#define CFG_ENV_ADDR 0x0 -#define CFG_ENV_MAP_ADRS 0xff000000 -#define CFG_NV_SROM_COPY_ADDR (CFG_ENV_ADDR + CFG_ENV_SIZE) -#define CFG_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */ -#define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */ - -/* - * Serial devices - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 24000000 -#define CFG_NS16550_COM1 (CFG_UART_BASE + 0) -#define CFG_NS16550_COM2 (CFG_UART_BASE + 8) - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO -#undef CONFIG_PCI_SCAN_SHOW - -/* - * Optional Video console (graphic: SMI LynxEM) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10)) -#define VIDEO_TSTC_FCT serial_tstc -#define VIDEO_GETC_FCT serial_getc - -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO - -/* - * Initial BATs - */ -#if 1 - -#define CFG_IBAT0L 0 -#define CFG_IBAT0U 0 -#define CFG_DBAT0L CFG_IBAT1L -#define CFG_DBAT0U CFG_IBAT1U - -#define CFG_IBAT1L 0 -#define CFG_IBAT1U 0 -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -#define CFG_IBAT2L 0 -#define CFG_IBAT2U 0 -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U - -#define CFG_IBAT3L 0 -#define CFG_IBAT3U 0 -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -#else - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L CFG_IBAT1L -#define CFG_DBAT0U CFG_IBAT1U - -/* address range for flashes */ -#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* ISA IO space */ -#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U - -/* ISA memory space */ -#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -#endif - -/* - * Speed settings are board specific - */ -#define CFG_BUS_HZ 100000000 -#define CFG_CPU_CLK 400000000 -#define CFG_BUS_CLK CFG_BUS_HZ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CFG_L2 - -#if 1 -#define L2_INIT 0 /* cpu 750 CXe*/ -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_EEPRO100_SROM_WRITE - -#endif /* __CONFIG_H */ diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h deleted file mode 100644 index e73bcec..0000000 --- a/include/configs/ELPT860.h +++ /dev/null @@ -1,390 +0,0 @@ -/* -**===================================================================== -** -** Copyright (C) 2000, 2001, 2002, 2003 -** The LEOX team , http://www.leox.org -** -** LEOX.org is about the development of free hardware and software resources -** for system on chip. -** -** Description: U-Boot port on the LEOX's ELPT860 CPU board -** ~~~~~~~~~~~ -** -**===================================================================== -** -** This program is free software; you can redistribute it and/or -** modify it under the terms of the GNU General Public License as -** published by the Free Software Foundation; either version 2 of -** the License, or (at your option) any later version. -** -** This program is distributed in the hope that it will be useful, -** but WITHOUT ANY WARRANTY; without even the implied warranty of -** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -** GNU General Public License for more details. -** -** You should have received a copy of the GNU General Public License -** along with this program; if not, write to the Free Software -** Foundation, Inc., 59 Temple Place, Suite 330, Boston, -** MA 02111-1307 USA -** -**===================================================================== -*/ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */ -#define CONFIG_MPC860T 1 -#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */ -#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* BOOT arguments */ -#define CONFIG_PREBOOT \ - "echo;" \ - "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "rootargs=setenv rootpath /tftp/${ipaddr}\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:eth0:off panic=1\0" \ - "ramboot=tftp 400000 /home/paugaml/pMulti;" \ - "run ramargs;bootm\0" \ - "nfsboot=tftp 400000 /home/paugaml/uImage;" \ - "run rootargs;run nfsargs;run addip;bootm\0" \ - "" -#define CONFIG_BOOTCOMMAND "run ramboot" - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */ -#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Environment Variables and Storages - */ -#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */ - -#undef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */ -#undef CFG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */ -#define CFG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */ - -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_ETHADDR 00:01:77:00:60:40 -#define CONFIG_IPADDR 192.168.0.30 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_GATEWAYIP 192.168.0.1 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x02000000 -#define CFG_NVRAM_BASE 0x03000000 - -#if defined(CFG_ENV_IS_IN_FLASH) -# if defined(DEBUG) -# define CFG_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */ -# else -# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -# endif -#else -# if defined(DEBUG) -# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -# else -# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -# endif -#endif - -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -# define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ -#define CFG_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */ - /* 8 top NVRAM locations */ - -#if defined(CFG_ENV_IS_IN_NVRAM) -# define CFG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ -# define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC11) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC - * enabled - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler - *----------------------------------------------------------------------- - * - */ -#ifdef DEBUG -# define CFG_DER 0xFFE7400F /* Debug Enable Register */ -#else -# define CFG_DER 0 -#endif - -/* - * Init Memory Controller: - * ~~~~~~~~~~~~~~~~~~~~~~ - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE1_PRELIM CFG_SDRAM_BASE /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */ - -/* SDRAM timing: */ -#define CFG_OR_TIMING_SDRAM 0x00000000 - -#define CFG_OR1_PRELIM ((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM ) -#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR2 and OR2 (NVRAM) - * - */ -#define NVRAM_BASE1_PRELIM CFG_NVRAM_BASE /* NVRAM bank #0 */ -#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */ - -#define CFG_OR2_PRELIM 0xFFF80160 -#define CFG_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/*----------------------------------------------------------------------- - * Internal Definitions - *----------------------------------------------------------------------- - * - */ - -/* - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h deleted file mode 100644 index c203aea..0000000 --- a/include/configs/ERIC.h +++ /dev/null @@ -1,372 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_ERIC 1 /* ...on a ERIC board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* run board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#if 1 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#endif -#if 0 -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#endif -#if 0 -#define CFG_ENV_IS_IN_EEPROM 1 /* use I2C RTC X1240 for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */ -#endif /* total size of a X1240 is 2048 bytes */ - -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x57 /* X1240 has two I2C slave addresses, one for EEPROM */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* address length for the eeprom */ -#define CONFIG_I2C_RTC 1 /* we have a Xicor X1240 RTC */ -#define CFG_I2C_RTC_ADDR 0x6F /* and one for RTC */ - -#ifdef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM -#else -#ifdef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_EEPROM -#else -#ifdef CFG_ENV_IS_IN_EEPROM -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#endif -#endif -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#if 1 -#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ -#else -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ -#endif - -#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs " \ - "nfsroot=192.168.1.2:/eric_root_devel " \ - "ip=192.168.1.22:192.168.1.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH) - -/* - * #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | \ - * CFG_CMD_KGDB | CFG_CMD_I2C | CFG_CMD_EEPROM | \ - * CFG_CMD_ENV | CFG_CMD_FLASH) - */ - -/* CFG_CMD_ENV est definie */ -/* ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB) & ~(CFG_CMD_ENV)) - */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_EXT_SERIAL_CLOCK 14318180 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ - -#define CFG_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */ -#define CFG_PCI_PTM1LA 0xFFFC0000 /* point to flash */ -#define CFG_PCI_PTM1MS 0xFFFFF001 /* 4kB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * External peripheral base address - *----------------------------------------------------------------------- - */ -/* Bank 0 - Flash/SRAM 0xFF000000 16MB 16 Bit */ -/* Bank 1 - NVRAM/RTC 0xF0000000 1MB 8 Bit */ -/* Bank 2 - A/D converter 0xF0100000 1MB 8 Bit */ -/* Bank 3 - Ethernet PHY Reset 0xF0200000 1MB 8 Bit */ -/* Bank 4 - PC-MIP PRSNT1# 0xF0300000 1MB 8 Bit */ -/* Bank 5 - PC-MIP PRSNT2# 0xF0400000 1MB 8 Bit */ -/* Bank 6 - CPU LED0 0xF0500000 1MB 8 Bit */ -/* Bank 7 - CPU LED1 0xF0600000 1MB 8 Bit */ - -/* ----------------------------------------------------------------------- */ -/* Memory Bank 0 (Flash) initialization */ -/* ----------------------------------------------------------------------- */ -#define CS0_AP 0x9B015480 -#define CS0_CR 0xFF87A000 /* BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */ -/* ----------------------------------------------------------------------- */ -/* Memory Bank 1 (NVRAM/RTC) initialization */ -/* ----------------------------------------------------------------------- */ -#define CS1_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ -#define CS1_CR 0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ - /* ----------------------------------------------------------------------- */ - /* Memory Bank 2 (A/D converter) initialization */ - /* ----------------------------------------------------------------------- */ -#define CS2_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ -#define CS2_CR 0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ -/* ----------------------------------------------------------------------- */ -/* Memory Bank 3 (Ethernet PHY Reset) initialization */ -/* ----------------------------------------------------------------------- */ -#define CS3_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ -#define CS3_CR 0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ -/* ----------------------------------------------------------------------- */ -/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */ -/* ----------------------------------------------------------------------- */ -#define CS4_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ -#define CS4_CR 0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ -/* ----------------------------------------------------------------------- */ -/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */ -/* ----------------------------------------------------------------------- */ -#define CS5_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ -#define CS5_CR 0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ -/* ----------------------------------------------------------------------- */ -/* Memory Bank 6 (CPU LED0) initialization */ -/* ----------------------------------------------------------------------- */ -#define CS6_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ -#define CS6_CR 0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ -/* ----------------------------------------------------------------------- */ -/* Memory Bank 7 (CPU LED1) initialization */ -/* ----------------------------------------------------------------------- */ -#define CS7_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */ -#define CS7_CR 0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */ - -#define CFG_NVRAM_REG_BASE_ADDR 0xF0000000 -#define CFG_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8) -#define CFG_ADC_REG_BASE_ADDR 0xF0100000 -#define CFG_PHYRES_REG_BASE_ADDR 0xF0200000 -#define CFG_PRSNT1_REG_BASE_ADDR 0xF0300000 -#define CFG_PRSNT2_REG_BASE_ADDR 0xF0400000 -#define CFG_LED0_REG_BASE_ADDR 0xF0500000 -#define CFG_LED1_REG_BASE_ADDR 0xF0600000 - - -/* SDRAM CONFIG */ -#define CFG_SDRAM_MANUALLY 1 -#define CFG_SDRAM_SINGLE_BANK 1 - -#ifdef CFG_SDRAM_MANUALLY -/*----------------------------------------------------------------------- - * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) - *----------------------------------------------------------------------*/ -#define MB0CF 0x00062001 /* 32MB @ 0 */ -/*----------------------------------------------------------------------- - * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) - *----------------------------------------------------------------------*/ -#ifdef CFG_SDRAM_SINGLE_BANK -#define MB1CF 0x0 /* 0MB @ 32MB */ -#else -#define MB1CF 0x02062001 /* 32MB @ 32MB */ -#endif -/*----------------------------------------------------------------------- - * Set MB2CF for bank 2. off - *----------------------------------------------------------------------*/ -#define MB2CF 0x0 /* 0MB */ -/*----------------------------------------------------------------------- - * Set MB3CF for bank 3. off - *----------------------------------------------------------------------*/ -#define MB3CF 0x0 /* 0MB */ - -#define SDTR_100 0x0086400D -#define RTR_100 0x05F0 -#define SDTR_66 0x00854006 /* orig U-Boot-wallnut says 0x00854006 */ -#define RTR_66 0x03f8 - -#endif /* CFG_SDRAM_MANUALLY */ - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 32 -#define CFG_FLASH_BASE 0xFF800000 /* 8 MByte Flash */ -#define CFG_MONITOR_BASE 0xFFFE0000 /* last 128kByte within Flash */ -/*#define CFG_MONITOR_LEN (192 * 1024)*/ /* Reserve 196 kB for Monitor */ -#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_FLASH_16BIT 1 /* Rom 16 bit data bus */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* BEG ENVIRONNEMENT FLASH */ -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE (128*1024) - -#if 0 /* force ENV to be NOT embedded */ -#define CFG_ENV_ADDR 0xfffa0000 -#else /* force ENV to be embedded */ -#define CFG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN - CFG_ENV_SIZE - 0x10) /* let space for reset vector */ -/* #define CFG_ENV_ADDR (CFG_MONITOR_BASE)*/ -#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) -#endif - -#endif -/* END ENVIRONNEMENT FLASH */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_REG_BASE_ADDR /* NVRAM base address */ -#define CFG_NVRAM_SIZE 0x7F8 /* NVRAM size 2kByte - 8 Byte for RTC */ - -#ifdef CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_SIZE 0x7F8 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - - -/* Configuration Port location */ -/* #define CONFIG_PORT_ADDR 0xF0000500 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h deleted file mode 100644 index b176c6f..0000000 --- a/include/configs/ESTEEM192E.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */ - -#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */ -#define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << 20) -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */ - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BAUDRATE 9600 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */ - -#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \ - "ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 " -/* - * Miscellaneous configurable options - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "BOOT: " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 8 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - - /*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#ifdef DEBUG -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) - -/*----------------------------------------------------------------------- - * SUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */ - - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (CFG_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 -/*#define CFG_DER 0x02002000 */ - - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH 0x00000160 - /*(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) */ - -#define CFG_OR0_REMAP 0x80000160 /*(CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)*/ -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ( FLASH_BASE0_PRELIM | 0x00000801 ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ( FLASH_BASE1_PRELIM | 0x00000801 ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM 0xFC000E00 -#define CFG_BR2_PRELIM (SDRAM_BASE2_PRELIM | 0x00000081) - -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM (SDRAM_BASE3_PRELIM | 0x00000081) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL 0x18803112 -#define CFG_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/ - - -/* - * Internal Definitions - * - * Boot Flags - */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h deleted file mode 100644 index d55eb7d..0000000 --- a/include/configs/ETX094.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_ETX094 1 /* ...on a ETX_094 board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 57600 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */ -#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ -#define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */ - -#define CONFIG_ETHADDR 08:00:06:00:00:00 - -#ifdef CONFIG_ETHADDR -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_RAMBOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \ - "U-Boot_version=U-Boot-1.0.x-Date " \ - "panic=1 " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#define CONFIG_NFSBOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#ifdef DEBUG -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_FLASH_16BIT -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ -#else -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \ - OR_SCY_2_CLK | OR_TRLX ) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) - -#ifdef CONFIG_FLASH_16BIT /* 16 bit data port */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) -#else /* 32 bit data port */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) -#endif /* CONFIG_FLASH_16BIT */ - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 23 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h deleted file mode 100644 index 78e5716..0000000 --- a/include/configs/EVB64260.h +++ /dev/null @@ -1,425 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef __ASSEMBLY__ -#include -#endif - -#include "../board/evb64260/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ -#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ - -#undef CONFIG_ECC /* enable ECC support */ -/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#ifndef CONFIG_EVB64260_750CX -#define CFG_BOARD_NAME "EVB64260" -#else -#define CFG_BOARD_NAME "EVB64260-750CX" -#endif - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - -#define CONFIG_NET_MULTI /* attempt all available adapters */ - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp && " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:" \ - "$netmask:$hostname:eth0:none; && " \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00300000 /* default load address */ - -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -#define CFG_BUS_HZ 100000000 /* 100 MHz */ -#define CFG_BUS_CLK CFG_BUS_HZ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_EVB64260_750CX -#define CONFIG_750CX -#define CFG_BROKEN_CL2 -#endif - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xfff00000 -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 4 -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CFG_GT_REGS 0xf8000000 -#define CFG_DEV_BASE 0xfc000000 - -#define CFG_DEV0_SPACE CFG_DEV_BASE -#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) -#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) -#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) - -#define CFG_DEV0_SIZE _8M /* evb64260 sram @ 0xfc00.0000 */ -#define CFG_DEV1_SIZE _8M /* evb64260 rtc @ 0xfc80.0000 */ -#define CFG_DEV2_SIZE _16M /* evb64260 duart @ 0xfd00.0000 */ -#define CFG_DEV3_SIZE _16M /* evb64260 flash @ 0xfe00.0000 */ - -#define CFG_DEV0_PAR 0x20205093 -#define CFG_DEV1_PAR 0xcfcfffff -#define CFG_DEV2_PAR 0xc0059bd4 -#define CFG_8BIT_BOOT_PAR 0xc00b5e7c -#define CFG_32BIT_BOOT_PAR 0xc4a8241c - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - -#if 0 /* Wrong?? NTL */ -#define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ - /* DMAAck[1:0] GNT0[1:0] */ -#else -#define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ - /* REQ0[1:0] GNT0[1:0] */ -#endif -#define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ - /* DMAReq[4] DMAAck[4] WDNMI WDE */ -#if 0 /* Wrong?? NTL */ -#define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ - /* DMAAck[1:0] GNT1[1:0] */ -#else -#define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ - /* GPP[22] (RS232IntB or PCI1Int) */ - /* GPP[21] (RS323IntA) */ - /* BClkIn */ - /* REQ1[1:0] GNT1[1:0] */ -#endif - -#if 0 /* Wrong?? NTL */ -# define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ - /* GPP[27:26] Int[1:0] */ -#else -# define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ - /* GPP[29] (PCI1Int) */ - /* BClkOut0 */ - /* GPP[27] (PCI0Int) */ - /* GPP[26] (RtcInt or PCI1Int) */ - /* CPUInt[25:24] */ -#endif - -# define CFG_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - -#if 0 /* Wrong?? - NTL */ -# define CFG_GPP_LEVEL_CONTROL 0x000002c6 -#else -# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ - /* gpp[29] */ - /* gpp[27:26] */ - /* gpp[22:21] */ - -# define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 0 - pci use buffer 1,1 - cpu use buffer 0 - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 110110 00 111 0 0 00 1 */ - /* refresh_count=0x200 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ -#endif - -#define CFG_DUART_IO CFG_DEV2_SPACE -#define CFG_DUART_CHAN 1 /* channel to use for console */ -#define CFG_INIT_CHAN1 -#define CFG_INIT_CHAN2 - -#define SRAM_BASE CFG_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M - -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M - -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI 0x00000000 -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI 0x00000000 - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 - -#define CFG_NS16550_REG_SIZE -4 - -#define CFG_NS16550_CLK 3686400 - -#define CFG_NS16550_COM1 (CFG_DUART_IO + 0) -#define CFG_NS16550_COM2 (CFG_DUART_IO + 0x20) - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* I2C speed and slave address (for compatability) defaults */ -#define CFG_I2C_SPEED 400000 -#define CFG_I2C_SLAVE 0x7F - -/* I2C addresses for the two DIMM SPD chips */ -#ifndef CONFIG_EVB64260_750CX -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 -#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ -#define DIMM0_I2C_ADDR 0x54 -#define DIMM1_I2C_ADDR 0x54 -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_CFI 1 - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 -#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CFG_L2 - -#ifdef CONFIG_750CX -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_BOARD_ASM_INIT 1 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h deleted file mode 100644 index d85be42..0000000 --- a/include/configs/EXBITGEN.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -/* I2C configuration */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 40000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ - -/* environment is in EEPROM */ -#define CFG_ENV_IS_IN_EEPROM 1 -#undef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM - -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_I2C_EEPROM_ADDR 0x56 /* 1010110 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* 8-bit internal addressing */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 1 /* ... and 1 bit in I2C address */ -#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 4 bytes per page */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* write takes up to 40 msec */ -#define CFG_ENV_OFFSET 4 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 350 /* that is 350 bytes only! */ -#endif - -#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ -/* Explanation: - autbooting is altogether disabled and cannot be - enabled if CONFIG_BOOTDELAY is negative. - If you want shorter bootdelay, then - - "setenv bootdelay " to the proper value -*/ - -#define CONFIG_BOOTCOMMAND "bootm 20400000 20800000" - -#define CONFIG_BOOTARGS "root=/dev/ram " \ - "ramdisk_size=32768 " \ - "console=ttyS0,115200 " \ - "ram=128M debug" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* UART configuration */ -#define CFG_BASE_BAUD 691200 - -/* Default baud rate */ -#define CONFIG_BAUDRATE 115200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_PCI /* no pci support */ - -/*----------------------------------------------------------------------- - * External peripheral base address - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CFG_KEY_REG_BASE_ADDR 0xF0100000 -#define CFG_IR_REG_BASE_ADDR 0xF0200000 -#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH0_BASE 0xFFF80000 -#define CFG_FLASH0_SIZE 0x00080000 -#define CFG_FLASH1_BASE 0x20000000 -#define CFG_FLASH1_SIZE 0x02000000 -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -#if CFG_MONITOR_BASE < CFG_FLASH0_BASE -#define CFG_RAMSTART -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 5 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x00060000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x00010000 /* see README - env sector total size */ -#endif - -/* On Chip Memory location/size */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -/* Global info and initial stack */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* Cache configuration */ -#define CFG_DCACHE_SIZE 8192 -#define CFG_CACHELINE_SIZE 32 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h deleted file mode 100644 index 1b562d6..0000000 --- a/include/configs/FADS823.h +++ /dev/null @@ -1,464 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* - * 1999-nov-26: The FADS is using the following physical memorymap: - * - * ff020000 -> ff02ffff : pcmcia io remapping - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot - * ff000000 -> ff00ffff : IMAP internal in the cpu - * e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia - * fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot - * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot -*/ - -#define CFG_PCMCIA_IO_ADDR 0xff020000 -#define CFG_PCMCIA_IO_SIZE 0x10000 -#define CFG_PCMCIA_MEM_ADDR 0xe0000000 -#define CFG_PCMCIA_MEM_SIZE 0x10000 -#define CFG_IMMR 0xFF000000 -#define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x02800000 -#define BCSR_ADDR ((uint) 0xff010000) -#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */ -#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */ - -#define CONFIG_VIDEO 1 /* To enable video controller support */ -#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/*Now included by CFG_CMD_PCMCIA */ -/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */ - -/* Video related */ - -#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ -#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */ -#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */ -#define CONFIG_VIDEO_SIZE (2*1024*1024) -/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */ - -/* Wireless 56Khz 4PPM keyboard on SMCx */ - -/*#define CONFIG_KEYBOARD 1 */ -#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC823 1 -#define CONFIG_MPC823FADS 1 -#define CONFIG_FADS 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 - -/* Set the CPU speed to 50Mhz on the FADS */ - -#if 0 -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 5000000 /* 5 MHz in */ -#else -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 5000000 /* 5 MHz in */ -#define CFG_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */ -#endif -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ -#define CONFIG_BOOTARGS "" -#define CONFIG_BOOTCOMMAND \ -"bootp ;" \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ -"bootm" -#else -#define CONFIG_BOOTDELAY 0 /* autoboot disabled */ -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * Also NOTE that it doesn't mean SDRAM - it means MEMORY. - */ -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#if 0 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer * - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ - -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CFG_MAMR 0x13a01114 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* values according to the manual */ - -#define BCSR0 ((uint) (BCSR_ADDR + 00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_FLASH_PD_SHIFT 28 -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT 23 -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_MODEM_EN ((uint)0x00100000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC850 -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#endif /* CONFIG_MPC850 */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_fads) - -/* - * MPC8xx CPM Options - */ -#define CONFIG_SCC_ENET 1 -#define CONFIG_SCC2_ENET 1 -#undef CONFIG_FEC_ENET -#undef CONFIG_CPM_IIC -#undef CONFIG_UCODE_PATCH - -#define CONFIG_DISK_SPINUP_TIME 1000000 - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 1 - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#define CFG_DAUGHTERBOARD - -#endif /* __CONFIG_H */ diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h deleted file mode 100644 index 2a986f0..0000000 --- a/include/configs/FADS850SAR.h +++ /dev/null @@ -1,416 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* - * 1999-nov-26: The FADS is using the following physical memorymap: - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom - * ff000000 -> ff00ffff : IMAP internal in the cpu - * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom - * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC850 1 -#define CONFIG_MPC850SAR 1 -#define CONFIG_FADS 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 - -#if 0 -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 50000000 /* 50 MHz in */ -#else -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#endif -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */ -#define CONFIG_BOOTARGS " " - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * Also NOTE that it doesn't mean SDRAM - it means MEMORY. - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */ -#define CFG_FLASH_BASE 0x02800000 -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#if 0 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer * - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (((MPC8XX_FACT-1) << 20) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - - -#define BCSR_ADDR ((uint) 0x02100000) -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ - -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ -#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CFG_MAMR 0x13a01114 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ - - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_FLASH_PD_SHIFT 28 -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT 23 -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_USB_SPEED ((uint)0x04000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VCCO ((uint)0x02000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHFDE ((uint)0x02000000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC823 -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#endif /* CONFIG_MPC860T */ -#ifdef CONFIG_MPC823 -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETHRST ((uint)0x00200000) -#endif /* CONFIG_MPC860T */ -#define BCSR4_MODEM_EN ((uint)0x00100000) -#define BCSR4_DATA_VOICE ((uint)0x00080000) - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_fads) - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 2 - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#define CFG_DAUGHTERBOARD - -#endif /* __CONFIG_H */ diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h deleted file mode 100644 index 18de6b0..0000000 --- a/include/configs/FADS860T.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * Values common to all FADS family boards are in board/fads/fads.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* board type */ -#define CONFIG_FADS 1 /* old/new FADS + new ADS */ - -/* processor type */ -#define CONFIG_MPC860T 1 /* 860T */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#if 0 /* old FADS */ -# define CFG_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ -#else /* new FADS */ -# define CFG_8XX_FACT 10 /* 5 MHz oscillator on EXTCLK */ -#endif - -#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ 1 - -#include "fads.h" - -#ifdef USE_REAL_FLASH_VALUES -/* - * These values fit our FADS860T ... - * The "default" behaviour with 1Mbyte initial doesn't work for us! - */ -#undef CFG_OR0_PRELIM -#undef CFG_BR0_PRELIM -#define CFG_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */ -#define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */ -#endif - -#define CFG_DAUGHTERBOARD /* FADS has processor-specific daughterboard */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h deleted file mode 100644 index 8babee1..0000000 --- a/include/configs/FLAGADM.h +++ /dev/null @@ -1,302 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */ -#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/ - -#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ -#define CONFIG_8xx_CONS_SMC2 1 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#undef CONFIG_CLOCKS_IN_MHZ - -#if 0 -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp" -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/ram ip=off panic=1;" \ - "bootm 40040000 400e0000" -#else -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp panic=1" -#define CONFIG_BOOTCOMMAND "bootp 0x400000; bootm 0x400000" -#endif /* 0|1*/ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CFG_CMD_BDI | CFG_CMD_IMI | CFG_CMD_CACHE | \ - CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_LOADS | \ - CFG_CMD_ENV | CFG_CMD_REGINFO | CFG_CMD_IMMAP | CFG_CMD_NET) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "EEG> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x40040000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -/* This is a litlebit wasteful, but one sector is 128kb and we have to - * assigne a whole sector for the environment, so that we can safely - * erase and write it without disturbing the boot sector - */ -#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#ifdef CONFIG_WATCHDOG -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \ - SIUMCR_MLRC01 | SIUMCR_GB5E) -#define CFG_SIUMCR (CFG_PRE_SIUMCR | SIUMCR_DLK) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit miltiplier of 0x00b i.e. operation clock is - * 4MHz * (0x00b+1) = 4MHz * 12 = 48MHz - */ -#define CFG_PLPRCR (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR ( SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -#define CFG_DER 0 - -/* - * In the Flaga DM we have: - * Flash on BR0/OR0/CS0a at 0x40000000 - * Display on BR1/OR1/CS1 at 0x20000000 - * SDRAM on BR2/OR2/CS2 at 0x00000000 - * Free BR3/OR3/CS3 - * DSP1 on BR4/OR4/CS4 at 0x80000000 - * DSP2 on BR5/OR5/CS5 at 0xa0000000 - * - * For now we just configure the Flash and the SDRAM and leave the others - * untouched. -*/ - -#define CFG_FLASH_PROTECTION 0 - -#define FLASH_BASE0 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_OR_AM 0xff000000 /* OR addr mask */ -#define CFG_OR_ATM 0x00006000 - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | \ - OR_SCY_3_CLK | OR_TRLX | OR_EHTR ) - -#define CFG_OR0_PRELIM (CFG_OR_AM | CFG_OR_ATM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR2 and OR2 (SDRAM) - * - */ -#define SDRAM_BASE2 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM ( 0x00000800 ) - -#define CFG_OR2_PRELIM (CFG_OR_AM | CFG_OR_TIMING_SDRAM) -#define CFG_BR2_PRELIM ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CFG_BR2 CFG_BR2_PRELIM -#define CFG_OR2 CFG_OR2_PRELIM - -/* - * MAMR settings for SDRAM - */ -#define CFG_MAMR_48_SDR (CFG_MAMR_PTA | MAMR_WLFA_1X | MAMR_RLFA_1X \ - | MAMR_G0CLA_A11) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 0x0F000000 - -/* - * BR4 and OR4 (DSP1) - * - * We do not wan't preliminary setup of the DSP, anyway we need the - * UPMB setup correctly before we can access the DSP. - * -*/ -#define DSP_BASE 0x80000000 - -#define CFG_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS) -#define CFG_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V ) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h deleted file mode 100644 index 0dd21bc..0000000 --- a/include/configs/FPS850L.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */ - -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 19200 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~( \ - CFG_CMD_CONSOLE | \ - CFG_CMD_BDI | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_CACHE ) ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h deleted file mode 100644 index 423d74e..0000000 --- a/include/configs/FPS860L.h +++ /dev/null @@ -1,330 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */ - -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h deleted file mode 100644 index db42fd0..0000000 --- a/include/configs/G2000.h +++ /dev/null @@ -1,426 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_G2000 1 /* ...on a PLU405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#if 0 /* test-only */ -#define CONFIG_BAUDRATE 115200 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -#define CONFIG_PREBOOT - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "panic=1\0" \ - "flash_nfs=run nfsargs addip addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addmisc;bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/g2000/pImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ff900000\0" \ - "pciconfighost=yes\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_NET_MULTI 1 - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY1_ADDR 1 /* PHY address */ - -#if 0 /* test-only */ -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -#endif - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if 0 /* test-only */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------------*/ -/* adding Ethernet setting: FTS OUI 00:11:0B */ -/*----------------------------------------------------------------------------*/ -#define CONFIG_ETHADDR 00:11:0B:00:00:01 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:11:0B:00:00:02 -#define CONFIG_IPADDR 10.48.8.178 -#define CONFIG_IP1ADDR 10.48.8.188 -#define CONFIG_NETMASK 255.255.255.128 -#define CONFIG_SERVERIP 10.48.8.138 - -/*----------------------------------------------------------------------- - * RTC stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_RTC_DS1337 -#define CFG_I2C_RTC_ADDR 0x68 - -#if 0 /* test-only */ -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#if 0 /* APC405 */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_BASE 0xFE000000 /* test-only...*/ -#define CFG_FLASH_INCREMENT 0x01000000 /* test-only */ -#else /* G2000 */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/ -#define CFG_FLASH_INCREMENT 0x01000000 /* test-only */ -#endif - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MONITOR_BASE 0xFFFC0000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#if 1 /* test-only */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#else /* DEFAULT: environment in flash, using redundand flash sectors */ - -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_ADDR 0xFFFA0000 /* environment starts before u-boot */ -#define CFG_ENV_SECT_SIZE 0x20000 /* 128k bytes may be used for env vars*/ - -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -/* CAT24WC08/16... */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Intel Strata Flash) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFF87A000 /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 1 ( Power TAU) initialization */ -/* #define CFG_EBC_PB1AP 0x04041000 */ -/* #define CFG_EBC_PB1CR 0xF0018000 */ /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#define CFG_EBC_PB1AP 0x00000000 -#define CFG_EBC_PB1CR 0x00000000 - -/* Memory Bank 2 (Intel Flash) initialization */ -#define CFG_EBC_PB2AP 0x00000000 -#define CFG_EBC_PB2CR 0x00000000 - -/* Memory Bank 3 (NAND) initialization */ -#define CFG_EBC_PB3AP 0x92015480 -#define CFG_EBC_PB3CR 0xF40B8000 /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */ - -/* Memory Bank 4 (FPGA regs) initialization */ -#define CFG_EBC_PB4AP 0x00000000 -#define CFG_EBC_PB4CR 0x00000000 /* leave it blank */ - -#define CFG_NAND_BASE 0xF4000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - * - * following GPIO setting changed for G20000, 080304 - */ -#define CFG_GPIO0_OSRH 0x40005555 -#define CFG_GPIO0_OSRL 0x40000110 -#define CFG_GPIO0_ISR1H 0x00000000 -#define CFG_GPIO0_ISR1L 0x15555445 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FF8014 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 1 -#define PLLMR0_DEFAULT PLLMR0_266_66_33_33 -#define PLLMR1_DEFAULT PLLMR1_266_66_33_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h deleted file mode 100644 index de8f7ae..0000000 --- a/include/configs/GEN860T.h +++ /dev/null @@ -1,766 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config_GEN860T.h - board specific configuration options - */ - -#ifndef __CONFIG_GEN860T_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC860 -#define CONFIG_GEN860T - -/* - * Identify the board - */ -#if !defined(CONFIG_SC) -#define CONFIG_IDENT_STRING " B2" -#else -#define CONFIG_IDENT_STRING " SC" -#endif - -/* - * Don't depend on the RTC clock to determine clock frequency - - * the 860's internal rtc uses a 32.768 KHz clock which is - * generated by the DS1337 - and the DS1337 clock can be turned off. - */ -#if !defined(CONFIG_SC) -#define CONFIG_8xx_GCLK_FREQ 66600000 -#else -#define CONFIG_8xx_GCLK_FREQ 48000000 -#endif - -/* - * The RS-232 console port is on SMC1 - */ -#define CONFIG_8xx_CONS_SMC1 -#define CONFIG_BAUDRATE 38400 - -/* - * Set allowable console baud rates - */ -#define CFG_BAUDRATE_TABLE { 9600, \ - 19200, \ - 38400, \ - 57600, \ - 115200, \ - } - -/* - * Print console information - */ -#undef CFG_CONSOLE_INFO_QUIET - -/* - * Set the autoboot delay in seconds. A delay of -1 disables autoboot - */ -#define CONFIG_BOOTDELAY 5 - -/* - * Pass the clock frequency to the Linux kernel in units of MHz - */ -#define CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_PREBOOT \ - "echo;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* - * Turn off echo for serial download by default. Allow baud rate to be changed - * for downloads - */ -#undef CONFIG_LOADS_ECHO -#define CFG_LOADS_BAUD_CHANGE - -/* - * Set default load address for tftp network downloads - */ -#define CFG_TFTP_LOADADDR 0x01000000 - -/* - * Turn off the watchdog timer - */ -#undef CONFIG_WATCHDOG - -/* - * Do not reboot if a panic occurs - */ -#define CONFIG_PANIC_HANG - -/* - * Enable the status LED - */ -#define CONFIG_STATUS_LED - -/* - * Reset address. We pick an address such that when an instruction - * is executed at that address, a machine check exception occurs - */ -#define CFG_RESET_ADDRESS ((ulong) -1) - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE \ - ) - -/* - * The GEN860T network interface uses the on-chip 10/100 FEC with - * an Intel LXT971A PHY connected to the 860T's MII. The PHY's - * MII address is hardwired on the board to zero. - */ -#define CONFIG_FEC_ENET -#define CFG_DISCOVER_PHY -#define CONFIG_MII -#define CONFIG_PHY_ADDR 0 - -/* - * Set default IP stuff just to get bootstrap entries into the - * environment so that we can autoscript the full default environment. - */ -#define CONFIG_ETHADDR 9a:52:63:15:85:25 -#define CONFIG_SERVERIP 10.0.4.201 -#define CONFIG_IPADDR 10.0.4.111 - -/* - * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to - * the MPC860T I2C interface. - */ -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */ -#define CFG_ENV_EEPROM_SIZE (32 * 1024) - -/* - * Enable I2C and select the hardware/software driver - */ -#define CONFIG_HARD_I2C 1 /* CPM based I2C */ -#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ - -#ifdef CONFIG_HARD_I2C -#define CFG_I2C_SPEED 100000 /* clock speed in Hz */ -#define CFG_I2C_SLAVE 0xFE /* I2C slave address */ -#endif - -#ifdef CONFIG_SOFT_I2C -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -/* - * Allow environment overwrites by anyone - */ -#define CONFIG_ENV_OVERWRITE - -#if !defined(CONFIG_SC) -/* - * The MPC860's internal RTC is horribly broken in rev D masks. Three - * internal MPC860T circuit nodes were inadvertently left floating; this - * causes KAPWR current in power down mode to be three orders of magnitude - * higher than specified in the datasheet (from 10 uA to 10 mA). No - * reasonable battery can keep that kind RTC running during powerdown for any - * length of time, so we use an external RTC on the I2C bus instead. - */ -#define CONFIG_RTC_DS1337 -#define CFG_I2C_RTC_ADDR 0x68 - -#else -/* - * No external RTC on SC variant, so we're stuck with the internal one. - */ -#define CONFIG_RTC_MPC8xx -#endif - -/* - * Power On Self Test support - */ -#define CONFIG_POST ( CFG_POST_CACHE | \ - CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_UART | \ - CFG_POST_SPR ) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -/* - * List of available monitor commands. Use the system default list - * plus add some of the "non-standard" commands back in. - * See ./cmd_confdefs.h - */ -#define BASE_CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_FPGA | \ - CFG_CMD_MII | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_POST_DIAG ) - -#if !defined(CONFIG_SC) -#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC ) -#else -#define CONFIG_COMMANDS BASE_CONFIG_COMMANDS -#endif - -/* - * There is no IDE/PCMCIA hardware support on the board. - */ -#undef CONFIG_IDE_PCMCIA -#undef CONFIG_IDE_LED -#undef CONFIG_IDE_RESET - -/* - * Enable the call to misc_init_r() for miscellaneous platform - * dependent initialization. - */ -#define CONFIG_MISC_INIT_R - -/* - * Enable call to last_stage_init() so we can twiddle some LEDS :) - */ -#define CONFIG_LAST_STAGE_INIT - -/* - * Virtex2 FPGA configuration support - */ -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA CFG_XILINX_VIRTEX2 -#define CFG_FPGA_PROG_FEEDBACK - - -/************************************************************************ - * This must be included AFTER the definition of any CONFIG_COMMANDS - */ -#include - -/* - * Verbose help from command monitor. - */ -#define CFG_LONGHELP -#if !defined(CONFIG_SC) -#define CFG_PROMPT "B2> " -#else -#define CFG_PROMPT "SC> " -#endif - - -/* - * Use the "hush" command parser - */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -/* - * Set buffer size for console I/O - */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 -#else -#define CFG_CBSIZE 256 -#endif - -/* - * Print buffer size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - -/* - * Maximum number of arguments that a command can accept - */ -#define CFG_MAXARGS 16 - -/* - * Boot argument buffer size - */ -#define CFG_BARGSIZE CFG_CBSIZE - -/* - * Default memory test range - */ -#define CFG_MEMTEST_START 0x0100000 -#define CFG_MEMTEST_END (CFG_MEMTEST_START + (128 * 1024)) - -/* - * Select the more full-featured memory test - */ -#define CFG_ALT_MEMTEST - -/* - * Default load address - */ -#define CFG_LOAD_ADDR 0x01000000 - -/* - * Set decrementer frequency (1 ms ticks) - */ -#define CFG_HZ 1000 - -/* - * Device memory map (after SDRAM remap to 0x0): - * - * CS Device Base Addr Size - * ---------------------------------------------------- - * CS0* Flash 0x40000000 64 M - * CS1* SDRAM 0x00000000 16 M - * CS2* Disk-On-Chip 0x50000000 32 K - * CS3* FPGA 0x60000000 64 M - * CS4* SelectMap 0x70000000 32 K - * CS5* Mil-Std 1553 I/F 0x80000000 32 K - * CS6* Unused - * CS7* Unused - * IMMR 860T Registers 0xfff00000 - */ - -/* - * Base addresses and block sizes - */ -#define CFG_IMMR 0xFF000000 - -#define SDRAM_BASE 0x00000000 -#define SDRAM_SIZE (64 * 1024 * 1024) - -#define FLASH_BASE 0x40000000 -#define FLASH_SIZE (16 * 1024 * 1024) - -#define DOC_BASE 0x50000000 -#define DOC_SIZE (32 * 1024) - -#define FPGA_BASE 0x60000000 -#define FPGA_SIZE (64 * 1024 * 1024) - -#define SELECTMAP_BASE 0x70000000 -#define SELECTMAP_SIZE (32 * 1024) - -#define M1553_BASE 0x80000000 -#define M1553_SIZE (64 * 1024) - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE SDRAM_BASE - -/* - * FLASH organization - */ -#define CFG_FLASH_BASE FLASH_BASE -#define CFG_FLASH_SIZE FLASH_SIZE -#define CFG_FLASH_SECT_SIZE (128 * 1024) -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 128 - -/* - * The timeout values are for an entire chip and are in milliseconds. - * Yes I know that the write timeout is huge. Accroding to the - * datasheet a single byte takes 630 uS (round to 1 ms) max at worst - * case VCC and temp after 100K programming cycles. It works out - * to 280 minutes (might as well be forever). - */ -#define CFG_FLASH_ERASE_TOUT (CFG_MAX_FLASH_SECT * 5000) -#define CFG_FLASH_WRITE_TOUT (CFG_MAX_FLASH_SECT * 128 * 1024 * 1) - -/* - * Allow direct writes to FLASH from tftp transfers (** dangerous **) - */ -#define CFG_DIRECT_FLASH_TFTP - -/* - * Reserve memory for U-Boot. - */ -#define CFG_MAX_UBOOT_SECTS 4 -#define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE) -#define CFG_MONITOR_BASE CFG_FLASH_BASE - -/* - * Select environment placement. NOTE that u-boot.lds must - * be edited if this is changed! - */ -#undef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_IS_IN_EEPROM - -#if defined(CFG_ENV_IS_IN_EEPROM) -#define CFG_ENV_SIZE (2 * 1024) -#define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024)) -#else -#define CFG_ENV_SIZE 0x1000 -#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE - -/* - * This ultimately gets passed right into the linker script, so we have to - * use a number :( - */ -#define CFG_ENV_OFFSET 0x060000 -#endif - -/* - * Reserve memory for malloc() - */ -#define CFG_MALLOC_LEN (128 * 1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 * 1024 * 1024) - -/* - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */ -#endif - -/*------------------------------------------------------------------------ - * SYPCR - System Protection Control UM 11-9 - * ----------------------------------------------------------------------- - * SYPCR can only be written once after reset! - * - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWE | \ - SYPCR_SWRI | \ - SYPCR_SWP \ - ) -#else -#define CFG_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWP \ - ) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration UM 11-6 - *----------------------------------------------------------------------- - * Set debug pin mux, enable SPKROUT and GPLB5*. - */ -#define CFG_SIUMCR ( SIUMCR_DBGC11 | \ - SIUMCR_DBPC11 | \ - SIUMCR_MLRC11 | \ - SIUMCR_GB5E \ - ) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control UM 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freeze enabled - */ -#define CFG_TBSCR ( TBSCR_REFA | \ - TBSCR_REFB | \ - TBSCR_TBF \ - ) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register UM 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC ( RTCSC_SEC | \ - RTCSC_ALR | \ - RTCSC_RTF | \ - RTCSC_RTE \ - ) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control UM 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR ( PISCR_PS | \ - PISCR_PITF \ - ) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit. Set MF for 1:2:1 mode. - */ -#define CFG_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \ - PLPRCR_SPLSS | \ - PLPRCR_TEXPS | \ - PLPRCR_TMIST \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register UM 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 - -#if !defined(CONFIG_SC) -#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ - SCCR_DFNL000 | \ - SCCR_DFNH000 \ - ) -#else -#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ - SCCR_DFNL000 | \ - SCCR_DFNH000 | \ - SCCR_RTDIV | \ - SCCR_RTSEL \ - ) -#endif - -/*----------------------------------------------------------------------- - * DER - Debug Enable Register UM 37-46 - *----------------------------------------------------------------------- - * Mask all events that can cause entry into debug mode - */ -#define CFG_DER 0 - -/* - * Initialize Memory Controller: - * - * BR0 and OR0 (FLASH memory) - */ -#define FLASH_BASE0_PRELIM FLASH_BASE - -/* - * Flash address mask - */ -#define CFG_PRELIM_OR_AM 0xfe000000 - -/* - * FLASH timing: - * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 - */ -#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | \ - OR_ACS_DIV2 | \ - OR_BI | \ - OR_SCY_2_CLK | \ - OR_TRLX | \ - OR_EHTR \ - ) - -#define CFG_OR0_PRELIM ( CFG_PRELIM_OR_AM | \ - CFG_OR_TIMING_FLASH \ - ) - -#define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ - BR_MS_GPCM | \ - BR_PS_8 | \ - BR_V \ - ) - -/* - * SDRAM configuration - */ -#define CFG_OR1_AM 0xfc000000 -#define CFG_OR1 ( (CFG_OR1_AM & OR_AM_MSK) | \ - OR_CSNT_SAM \ - ) - -#define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ - BR_MS_UPMA | \ - BR_PS_32 | \ - BR_V \ - ) - -/* - * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank - * of 256 MBit SDRAM - */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 - -/* - * Periodic timer for refresh @ 33 MHz system clock - */ -#define CFG_MAMR_PTA 64 - -/* - * MAMR settings for SDRAM - */ -#define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \ - MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | \ - MAMR_DSA_1_CYCL | \ - MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | \ - MAMR_WLFA_1X | \ - MAMR_TLFA_4X \ - ) - -/* - * CS2* configuration for Disk On Chip: - * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, - * no burst. - */ -#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_CSNT_SAM | \ - OR_ACS_DIV2 | \ - OR_BI | \ - OR_SCY_2_CLK | \ - OR_TRLX | \ - OR_EHTR \ - ) - -#define CFG_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V \ - ) - -/* - * CS3* configuration for FPGA: - * 33 MHz bus with SCY=15, no burst. - * The FPGA uses TA and TEA to terminate bus cycles, but we - * clear SETA and set the cycle length to a large number so that - * the cycle will still complete even if there is a configuration - * error that prevents TA from asserting on FPGA accesss. - */ -#define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ - OR_SCY_15_CLK | \ - OR_BI \ - ) - -#define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ - BR_PS_32 | \ - BR_MS_GPCM | \ - BR_V \ - ) -/* - * CS4* configuration for FPGA SelectMap configuration interface. - * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge - * of GCLK1_50 - */ -#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_G5LS | \ - OR_BI \ - ) - -#define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ - BR_PS_8 | \ - BR_MS_UPMB | \ - BR_V \ - ) - -/* - * CS5* configuration for Mil-Std 1553 databus interface. - * 33 MHz bus, GPCM, no burst. - * The 1553 interface uses TA and TEA to terminate bus cycles, - * but we clear SETA and set the cycle length to a large number so that - * the cycle will still complete even if there is a configuration - * error that prevents TA from asserting on FPGA accesss. - */ -#define CFG_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ - OR_SCY_15_CLK | \ - OR_EHTR | \ - OR_TRLX | \ - OR_CSNT_SAM | \ - OR_BI \ - ) - -#define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ - BR_PS_16 | \ - BR_MS_GPCM | \ - BR_V \ - ) - -/* - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Disk On Chip (millenium) configuration - */ -#if !defined(CONFIG_SC) -#define CFG_MAX_DOC_DEVICE 1 -#undef CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM -#undef CFG_DOC_PASSIVE_PROBE -#endif - -/* - * FEC interrupt assignment - */ -#define FEC_INTERRUPT SIU_LEVEL1 - -/* - * Sanity checks - */ -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#endif /* __CONFIG_GEN860T_H */ - -/* vim: set ts=4 tw=78 ai shiftwidth=4: */ diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h deleted file mode 100644 index 8c01d97..0000000 --- a/include/configs/GENIETV.h +++ /dev/null @@ -1,354 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* - * The GENIETV is using the following physical memorymap (copied from - * the FADS configuration): - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM - * ff000000 -> ff00ffff : IMAP internal in the cpu - * 30000000 -> 300fffff : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram setup by U-Boot - * - * CS pins are connected as follows: - * - * CS0 -512Kb boot flash - * CS1 - SDRAM #1 - * CS2 - SDRAM #2 - * CS3 - Flash #1 - * CS4 - Flash #2 - * CS5 - Lon (if present) - * CS6 - PCMCIA #1 - * CS7 - PCMCIA #2 - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */ -#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */ - -#define CFG_ALLOC_DPRAM /* Use dynamic DPRAM allocation */ - -#define CFG_AUTOLOAD "n" /* No autoload */ - -/*#define CONFIG_VIDEO 1 / To enable the video initialization */ -/*#define CONFIG_VIDEO_ADDR 0x00200000 */ -/*#define CONFIG_HARD_I2C 1 / I2C with hardware support */ -/*#define CONFIG_PCMCIA 1 / To enable the PCMCIA initialization */ - -/*#define CFG_PCMCIA_IO_ADDR 0xff020000 */ -/*#define CFG_PCMCIA_IO_SIZE 0x10000 */ -/*#define CFG_PCMCIA_MEM_ADDR 0xe0000000 */ -/*#define CFG_PCMCIA_MEM_SIZE 0x10000 */ - -/* Video related */ - -/*#define CONFIG_VIDEO_LOGO 1 / Show the logo */ -/*#define CONFIG_VIDEO_ENCODER_AD7177 1 / Enable this encoder */ -/*#define CONFIG_VIDEO_ENCODER_AD7177_ADDR 0xF4 / ALSB to ground */ - -/* Wireless 56Khz 4PPM keyboard on SMCx */ - -/*#define CONFIG_KEYBOARD 0 */ -/*#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 / SMC to use (0 indexed) */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#include - -#define CONFIG_GENIETV 1 -#define CONFIG_MPC823 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 - -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 5000000 /* 4 MHz clock */ - -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) -#define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << 20) -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_BOOTDELAY 1 /* autoboot after 2 seconds */ -#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ -#define CONFIG_BOOTARGS "" -#define CONFIG_BOOTCOMMAND \ -"bootp; tftp; " \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ -"bootm " -#else -#define CONFIG_BOOTDELAY 0 /* autoboot disabled */ -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 8 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * Also NOTE that it doesn't mean SDRAM - it means MEMORY. - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x02800000 -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#if 0 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/ - -/* values according to the manual */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - * -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer * - * interrupt status bit - leave PLL multiplication factor unchanged ! - * - * #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0(FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ - -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask (512Kb) */ - -/* FLASH timing */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX ) - -/*#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) */ -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 0xfff80ff4 */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */ - -/* - * BR1/2 and OR1/2 (SDRAM) -*/ - -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define SDRAM_MAX_SIZE 0x04000000 /* 64Mb bank */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* First bank */ -#define SDRAM_BASE2_PRELIM 0x10000000 /* Second bank */ - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MBMR_PTB 0x5d /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 -/* - * MBMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \ - | MAMR_TLFA_4X) /* 0x5d802114 */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_fads) - -/* - * MPC8xx CPM Options - */ -#define CONFIG_SCC_ENET 1 - -#define CONFIG_DISK_SPINUP_TIME 1000000 - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 1 -#define PCMCIA_SLOT_B 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/GTH.h b/include/configs/GTH.h deleted file mode 100644 index 03b9659..0000000 --- a/include/configs/GTH.h +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Parameters for GTH board - * Based on FADS860T - * by thomas.lange@corelatus.com - - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* - * ff000000 -> ff00ffff : IMAP internal in the cpu - * e0000000 -> ennnnnnn : pcmcia - * 98000000 -> 983nnnnn : FPGA 4MB - * 90000000 -> 903nnnnn : FPGA 4MB - * 80000000 -> 80nnnnnn : flash connected to CS0, final ( real ) location - * 00000000 -> nnnnnnnn : sdram - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#include - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_GTH 1 - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#define MPC8XX_FACT 3 /* Multiply by 3 */ -#define MPC8XX_XIN 16384000 /* 16.384 MHz */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_BOOTDELAY 1 /* autoboot after 0 seconds */ - -#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */ - -#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */ - -#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */ - -/* Only interrupt boot if space is pressed */ -/* If a long serial cable is connected but */ -/* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n" -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " - -#if 0 -/* Net boot */ -/* Loads a tftp image and starts it */ -#define CONFIG_BOOTCOMMAND "bootp;bootm 100000" /* autoboot command */ -#define CONFIG_BOOTARGS "panic=1" -#else -/* Compact flash boot */ -#define CONFIG_BOOTARGS "panic=1 root=/dev/hda7" -#define CONFIG_BOOTCOMMAND "disk 100000 0:5;bootm 100000" -#endif - -/* Enable watchdog */ -#define CONFIG_WATCHDOG 1 - -/* choose SCC1 ethernet (10BASET on motherboard) - * or FEC ethernet (10/100 on daughterboard) - */ -#if 1 -#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ -#undef CONFIG_FEC_ENET /* disable FEC ethernet */ -#define CFG_DISCOVER_PHY -#else -#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CFG_DISCOVER_PHY -#endif -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -/* Default location to load data from net */ -#define CFG_LOAD_ADDR 0x100000 - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -#define CFG_FLASH_BASE 0x80000000 - -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ - -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#undef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_OFFSET 0x000E0000 -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#define CFG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*---------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ - -/*FIXME dont use for now */ -/*#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -/*#define CFG_RTCSC (RTCSC_RTF) */ - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) -/* PITE */ -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ - -/* FIXME check values */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ - -#define CFG_REMAP_OR_AM 0xFF800000 /* 4 MB OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -#define FPGA_2_BASE 0x90000000 -#define FPGA_3_BASE 0x98000000 - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) - - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 ) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_ETHADDR DE:AD:BE:EF:00:01 /* Ethernet address */ - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_gth) - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#define CONFIG_PCMCIA_SLOT_A 1 -#endif - -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ - -#define PA_FRONT_LED ((u16)0x4) /* PA 13 */ -#define PA_FL_CONFIG ((u16)0x20) /* PA 10 */ -#define PA_FL_CE ((u16)0x1000) /* PA 3 */ - -#define PB_ID_GND ((u32)1) /* PB 31 */ -#define PB_REV_1 ((u32)2) /* PB 30 */ -#define PB_REV_0 ((u32)4) /* PB 29 */ -#define PB_BLUE_LED ((u32)0x400) /* PB 21 */ -#define PB_EEPROM ((u32)0x800) /* PB 20 */ -#define PB_ID_3 ((u32)0x2000) /* PB 18 */ -#define PB_ID_2 ((u32)0x4000) /* PB 17 */ -#define PB_ID_1 ((u32)0x8000) /* PB 16 */ -#define PB_ID_0 ((u32)0x10000) /* PB 15 */ - -/* NOTE. This is reset for 100Mbit port only */ -#define PC_ENET100_RESET ((ushort)0x0080) /* PC 8 */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h deleted file mode 100644 index 131c215..0000000 --- a/include/configs/HH405.h +++ /dev/null @@ -1,527 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_HH405 1 /* ...on a HH405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT "autoupd" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "pciconfighost=1\0" \ - "" - -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -/* - * Video console - */ -#define CONFIG_VIDEO /* for sm501 video support */ - -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_SM501 -#if 0 -#define CONFIG_VIDEO_SM501_32BPP -#else -#define CONFIG_VIDEO_SM501_16BPP -#endif -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CFG_CONSOLE_IS_IN_ENV -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ -#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ - -#define ADD_BMP_CMD CFG_CMD_BMP -#else -#define ADD_BMP_CMD 0 -#endif /* CONFIG_VIDEO */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_EXT2 | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_I2C | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - ADD_BMP_CMD | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#undef CFG_CONSOLE_INFO_QUIET /* print console @ startup */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * RTC stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_RTC_DS1338 -#define CFG_I2C_RTC_ADDR 0x68 - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */ - -#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CFG_RAMBOOT 1 -#else -# undef CFG_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 0x8000 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#if 0 /* test-only */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#else -#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ -#endif -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#define CFG_EEPROM_WREN 1 - -#if 1 /* test-only */ -/* CAT24WC08/16... */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#else -/* CAT24WC32/64... */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#endif -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define LCD_BA 0xF1000000 /* Epson LCD Base Address */ -#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ -#define CFG_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (Epson LCD) initialization */ -#define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ -#define CFG_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * LCD Setup - */ - -#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ -#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ -#define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ -#define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ - -/*----------------------------------------------------------------------- - * Universal Interrupt Controller (UIC) Setup - */ - -/* - * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high - */ -#define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_EXT6) - -/*----------------------------------------------------------------------- - * FPGA stuff - */ - -#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ - -/* FPGA internal regs */ -#define CFG_FPGA_CTRL 0x000 - -/* FPGA Control Reg */ -#define CFG_FPGA_CTRL_REV0 0x0001 -#define CFG_FPGA_CTRL_REV1 0x0002 -#define CFG_FPGA_CTRL_VGA0_BL 0x0004 -#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008 -#define CFG_FPGA_CTRL_CF_RESET 0x0040 -#define CFG_FPGA_CTRL_PS2_PWR 0x0080 -#define CFG_FPGA_CTRL_CF_PWR 0x0100 /* low active */ -#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200 -#define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */ - -#define LCD_CLK_OFF 0x0000 /* Off */ -#define LCD_CLK_02083 0x1000 /* 2.083 MHz */ -#define LCD_CLK_03135 0x2000 /* 3.135 MHz */ -#define LCD_CLK_04165 0x3000 /* 4.165 MHz */ -#define LCD_CLK_06250 0x4000 /* 6.250 MHz */ -#define LCD_CLK_08330 0x5000 /* 8.330 MHz */ -#define LCD_CLK_12500 0x6000 /* 12.50 MHz */ -#define LCD_CLK_25000 0x7000 /* 25.00 MHz */ - -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CFG_GPIO0_OSRH 0x40000550 -#define CFG_GPIO0_OSRL 0x00000110 -#define CFG_GPIO0_ISR1H 0x00000000 -#define CFG_GPIO0_ISR1L 0x15555440 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FE0017 - -#define CFG_LCD_ENDIAN (0x80000000 >> 7) -#define CFG_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ -#define CFG_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */ -#define CFG_LCD0_RST (0x80000000 >> 30) -#define CFG_LCD1_RST (0x80000000 >> 31) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h deleted file mode 100644 index 6864740..0000000 --- a/include/configs/HIDDEN_DRAGON.h +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2004 - * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com - * - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_HIDDEN_DRAGON 1 - -#if 0 -#define USE_DINK32 1 -#else -#undef USE_DINK32 -#endif - -#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_DRAM_SPEED 100 /* MHz */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ - CFG_CMD_PCI | \ - CFG_CMD_PING ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - -#define CONFIG_RTL8139 -#define _IO_BASE 0x00000000 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -/* Make sure the ethaddr can be overwritten - TODO: Remove this on final product -*/ -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x02000000 - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE 0x00090000 -#define CFG_RAMBOOT 1 -#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_INIT_RAM_END 0x10000 -#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#else -#undef CFG_RAMBOOT -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#endif - -#define CFG_FLASH_BASE 0xFFE00000 -#define CFG_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -#define CFG_EUMB_ADDR 0xFC000000 - -#define CFG_ISA_MEM 0xFD000000 -#define CFG_ISA_IO 0xFE000000 - -#define CFG_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */ -#define CFG_FLASH_RANGE_SIZE 0x00200000 -#define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#ifdef CONFIG_SOFT_I2C -#error "Soft I2C is not configured properly. Please review!" -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM } - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - - -#define CFG_WINBOND_83C553 1 /*has a winbond bridge */ -#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ -#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ -#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ - -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -/* TODO: Change this to VIA686A */ - -/* - * NS87308 Configuration - */ -#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ - -#define CFG_NS87308_BADDR_10 1 - -#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \ - CFG_NS87308_UART2 | \ - CFG_NS87308_POWRMAN | \ - CFG_NS87308_RTC_APC ) - -#undef CFG_NS87308_PS2MOD - -#define CFG_NS87308_CS0_BASE 0x0076 -#define CFG_NS87308_CS0_CONF 0x30 -#define CFG_NS87308_CS1_BASE 0x0075 -#define CFG_NS87308_CS1_CONF 0x30 -#define CFG_NS87308_CS2_BASE 0x0074 -#define CFG_NS87308_CS2_CONF 0x30 - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX > 2) -#define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000 -#else -#define CFG_NS16550_CLK 1843200 -#endif - -#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) -#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) -#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CFG_ROMNAL 7 /*rom/flash next access time */ -#define CFG_ROMFAL 11 /*rom/flash access time */ - -#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ - -/* the following are for SDRAM only*/ -#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CFG_REFREC 8 /* Refresh to activate interval */ -#define CFG_RDLAT 4 /* data latency from read command */ -#define CFG_PRETOACT 3 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_ACTORW 3 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#if 0 -#define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ -#endif - -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 1 -#define CFG_REGDIMM 0 - - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CFG_BANK_ENABLE 0x01 - -#define CFG_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 36 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* values according to the manual */ -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - -#define CONFIG_DISK_SPINUP_TIME 1000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h deleted file mode 100644 index 7cce876..0000000 --- a/include/configs/HMI10.h +++ /dev/null @@ -1,493 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_HMI10 -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_LCD -#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 2 /* .. on COM3 */ -#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/HMI10/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOARD_EARLY_INIT_R 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -/* Software (bit-bang) I2C driver configuration */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -#ifdef CONFIG_SPLASH_SCREEN -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BMP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#else -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0100000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4100000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8100000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC100000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -#define PCMCIA_MEM_WIN_NO 5 -#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ -#ifndef CONFIG_STATUS_LED /* Status and IDE LED's are mutually exclusive */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ -#endif - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h deleted file mode 100644 index eb627e8..0000000 --- a/include/configs/HUB405.h +++ /dev/null @@ -1,392 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_HUB405 1 /* ...on a HUB405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/* Ethernet stuff */ -#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ -#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#undef CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: UART) initialization */ -#if 0 -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#else -#define CFG_EBC_PB2AP 0x92015480 -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ -#endif - -#define DUART0_BA 0xF0000000 /* DUART Base Address */ -#define DUART1_BA 0xF0000008 /* DUART Base Address */ -#define DUART2_BA 0xF0000010 /* DUART Base Address */ -#define DUART3_BA 0xF0000018 /* DUART Base Address */ -#define CFG_NAND_BASE 0xF4000000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CFG_GPIO0_OSRH 0x40000550 -#define CFG_GPIO0_OSRL 0x00000110 -#define CFG_GPIO0_ISR1H 0x00000000 -#define CFG_GPIO0_ISR1L 0x15555445 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FE0014 - -#define CFG_DUART_RST (0x80000000 >> 14) -#define CFG_UART2_RS232 (0x80000000 >> 5) -#define CFG_UART3_RS232 (0x80000000 >> 6) -#define CFG_UART4_RS232 (0x80000000 >> 7) -#define CFG_UART5_RS232 (0x80000000 >> 8) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h deleted file mode 100644 index 35d84ae..0000000 --- a/include/configs/IAD210.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - - -# ifdef DEBUG -# warning DEBUG Defined -# endif /* DEBUG */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC860 1 -#define CONFIG_IAD210 1 /* ...on a IAD210 module */ -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#undef CONFIG_8xx_CONS_SMC1 -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_8xx_CONS_SCC2 /* V24 on SCC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 - - -# define MPC8XX_FACT 16 -# define CONFIG_8xx_GCLK_FREQ (64000000L) /* define if can't use get_gclk_freq */ -# define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 0 -# define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -# define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -/* using this define saves us updating another source file */ -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#undef CONFIG_BOOTARGS -/* #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -*/ - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs" \ - "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -# define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -# define CONFIG_MII 1 -# define CFG_DISCOVER_PHY 1 -# define CONFIG_FEC_UTOPIA 1 -# define CONFIG_ETHADDR 08:00:06:26:A2:6D -# define CONFIG_IPADDR 192.168.28.128 -# define CONFIG_SERVERIP 139.10.137.138 -# define CFG_DISCOVER_PHY 1 - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -# define CFG_I2C_SPEED 50000 -# define CFG_I2C_SLAVE 0xDD -# define CFG_I2C_EEPROM_ADDR 0x50 -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x08000000 -#define CFG_FLASH_SIZE ((uint)(4 * 1024 * 1024)) /* max 16Mbyte */ - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#if defined(DEBUG) -# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif - -# define CFG_MONITOR_BASE CFG_FLASH_BASE -# define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 - -#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 ) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ -#define CFG_RCCR 0x0020 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0xF8000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xF8000000 /* OR addr mask */ - -/* FLASH timing: - TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ - OR_SCY_3_CLK | OR_EHTR) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | OR_CSNT_SAM | OR_BI | OR_ACS_DIV4) -#define CFG_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 124 /* start with divider for 64 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h deleted file mode 100644 index cd17935..0000000 --- a/include/configs/ICU862.h +++ /dev/null @@ -1,456 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_ICU862 1 -#define CONFIG_MPC862 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#ifdef CONFIG_100MHz -#define MPC8XX_FACT 24 /* Multiply by 24 */ -#define MPC8XX_XIN 4165000 /* 4.165 MHz in */ -#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) - /* define if cant' use get_gclk_freq */ -#else -#if 1 /* for 50MHz version of processor */ -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */ -#else /* for 80MHz version of processor */ -#define MPC8XX_FACT 20 /* Multiply by 20 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */ -#endif -#endif - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CONFIG_MII 1 -#if 1 -#define CFG_DISCOVER_PHY 1 -#else -#undef CFG_DISCOVER_PHY -#endif - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -# define CFG_I2C_SPEED 50000 -# define CFG_I2C_SLAVE 0xFE -# define CFG_I2C_EEPROM_ADDR 0x50 -# define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#if 0 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#else -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00F40000 - -#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */ -#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */ -#define SCCR_MASK 0 -#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01) -#else /* up to 50 MHz we use a 1:1 clock */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 ) -#endif /* CONFIG_100MHz */ - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ -#define CFG_RCCR 0x0020 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * PCMCIA Power Switch - * - * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to - * control the voltages on the PCMCIA slot which is connected to Port B - *----------------------------------------------------------------------- - */ - /* Output pins */ -#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */ -#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */ -#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */ -#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */ -#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */ -#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \ - TPS2205_VPP_PGM | TPS2205_VPP_VCC | \ - TPS2205_SHDN) - - /* Input pins */ -#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */ -#define TPS2205_INPUTS ( TPS2205_OC ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */ - -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) - -#define CFG_OR0_PRELIM 0xFF000954 /* Real values for the board */ -#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */ - -/* - * BR1 and OR1 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -#define CFG_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */ - -#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM) -#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CFG_MAMR 0x13a01114 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h deleted file mode 100644 index aaa44c5..0000000 --- a/include/configs/IDS8247.h +++ /dev/null @@ -1,525 +0,0 @@ -/* - * (C) Copyright 2005 - * Heiko Schocher, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_IDS8247 1 -#define CPU_ID_STR "MPC8247" -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "console=ttyS0,115200\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/IDS8247/uImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ffa00000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_MISC_INIT_R 1 - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000080) -#define I2C_TRISTATE (iop->pdir &= ~0x00000080) -#define I2C_READ ((iop->pdat & 0x00000080) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \ - else iop->pdat &= ~0x00000080 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \ - else iop->pdat &= ~0x00000100 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#if 0 -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X -#endif - -/* - * select serial console configuration - * use the extern UART for the console - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK 14745600 - -#define CFG_UART_BASE 0xE0000000 -#define CFG_UART_SIZE 0x10000 - -#define CFG_NS16550_COM1 (CFG_UART_BASE + 0x8000) - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_NAND | \ - CFG_CMD_I2C | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CFG_FLASH0_BASE 0xFFF00000 -#define CFG_FLASH0_SIZE 8 - -/* Flash bank size (for preliminary settings) - */ -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Environment in flash */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x60000) -#define CFG_ENV_SIZE 0x20000 -#define CFG_ENV_SECT_SIZE 0x20000 - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - -#define CFG_NAND0_BASE 0xE1000000 - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 -#define NAND_NO_RB - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define NAND_DISABLE_CE(nand) do \ -{ \ - *(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \ -} while(0) - -#define NAND_ENABLE_CE(nand) do \ -{ \ - *(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \ -} while(0) - -#define NAND_CTL_CLRALE(nandptr) do \ -{ \ - *(((volatile __u8 *)nandptr) + 0x8) = 0; \ -} while(0) - -#define NAND_CTL_SETALE(nandptr) do \ -{ \ - *(((volatile __u8 *)nandptr) + 0x9) = 0; \ -} while(0) - -#define NAND_CTL_CLRCLE(nandptr) do \ -{ \ - *(((volatile __u8 *)nandptr) + 0x8) = 0; \ -} while(0) - -#define NAND_CTL_SETCLE(nandptr) do \ -{ \ - *(((volatile __u8 *)nandptr) + 0xa) = 0; \ -} while(0) - -#ifdef NAND_NO_RB -/* constant delay (see also tR in the datasheet) */ -#define NAND_WAIT_READY(nand) do { \ - udelay(12); \ -} while (0) -#else -/* use the R/B pin */ -#endif - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0))) - -#endif /* CFG_CMD_NAND */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000) - -/* no slaves so just fill with zeros */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CFG_SDRAM_BASE - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ - -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) -#define CFG_HID0_FINAL 0 -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR 0 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR (0x00000028 | SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 16 bit FLASH - * 1 60x GPCM 8 bit NAND - * 2 60x SDRAM 32 bit SDRAM - * 3 60x GPCM 8 bit UART - * - */ - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CFG_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */ - -#define CFG_MPTPR 0x6600 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CFG_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_SCY_6_CLK ) - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -/* Bank 1 - NAND Flash -*/ -#define CFG_NAND_BASE CFG_NAND0_BASE -#define CFG_NAND_SIZE 0x8000 - -#define CFG_OR_TIMING_NAND 0x000036 - -#define CFG_BR1_PRELIM ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) -#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND ) -#endif - -/* Bank 2 - 60x bus SDRAM - */ -#define CFG_PSRT 0x20 -#define CFG_LSRT 0x20 - -#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_OR2_PRELIM CFG_OR2 - - -/* SDRAM initialization values -*/ -#define CFG_OR2 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A10 |\ - ORxS_NUMR_12) - -#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI0_A11 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_2C |\ - PSDMR_WRC_3C |\ - PSDMR_CL_3) - -/* Bank 3 - UART -*/ - -#define CFG_BR3_PRELIM ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) -#define CFG_OR3_PRELIM (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX ) - -#endif /* __CONFIG_H */ diff --git a/include/configs/IP860.h b/include/configs/IP860.h deleted file mode 100644 index 0e20e56..0000000 --- a/include/configs/IP860.h +++ /dev/null @@ -1,462 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_IP860 1 /* ...on a IP860 board */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \ -"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -# define CFG_I2C_SPEED 50000 -# define CFG_I2C_SLAVE 0xFE -# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ -# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/*----------------------------------------------------------------------*/ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF1000000 /* Non-standard value!! */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x10000000 -#ifdef DEBUG -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#else -#if 0 /* need more space for I2C tests */ -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (256 << 10) -#endif -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#undef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_NVRAM -#undef DEBUG_I2C -#define CFG_ENV_IS_IN_EEPROM - -#ifdef CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_ADDR 0x20000000 /* use SRAM */ -#define CFG_ENV_SIZE (16<<10) /* use 16 kB */ -#endif /* CFG_ENV_IS_IN_NVRAM */ - -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */ -#define CFG_ENV_SIZE 1536 /* Use remaining space */ -#endif /* CFG_ENV_IS_IN_EEPROM */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - * +0x0004 - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * +0x0000 => 0x80600800 - */ -#define CFG_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \ - SIUMCR_DBGC11 | SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * Clock Setting - get clock frequency from Board Revision Register - *----------------------------------------------------------------------- - */ -#ifndef __ASSEMBLY__ -extern unsigned long ip860_get_clk_freq (void); -#endif -#define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq() - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - * +0x0200 => 0x00C2 - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - * +0x0240 => 0x0082 - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* +0x0286 => was: 0x0000D000 */ -#define CFG_PLPRCR \ - ( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/* +0x0220 => 0x00C3 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => TIMEP=1 */ -#define CFG_RCCR 0x0100 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CFG_RMDS 0 - -/*----------------------------------------------------------------------- - * DER - Debug Event Register - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - */ - -/* - * MAMR settings for SDRAM - 16-14 - * => 0xC3804114 - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 0xC3 - -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* - * BR1 and OR1 (FLASH) - */ -#define FLASH_BASE 0x10000000 /* FLASH bank #0 */ - -/* used to re-map FLASH - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* allow for max 8 MB of Flash */ -#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) - -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM CFG_BR0_PRELIM - -/* - * BR2/OR2 - SDRAM - */ -#define SDRAM_BASE 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CFG_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR3/OR3 - SRAM (16 bit) - */ -#define SRAM_BASE 0x20000000 -#define CFG_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */ -#define CFG_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define SRAM_SIZE (1 + (~(CFG_OR3 & BR_BA_MSK))) -#define CFG_OR3_PRELIM CFG_OR3 /* Make sure to map early */ -#define CFG_BR3_PRELIM CFG_BR3 /* in case it's used for ENV */ - -/* - * BR4/OR4 - Board Control & Status (8 bit) - */ -#define BCSR_BASE 0xFC000000 -#define CFG_OR4 0xFFFF0120 /* BI (internal) */ -#define CFG_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) - -/* - * BR5/OR5 - IP Slot A/B (16 bit) - */ -#define IP_SLOT_BASE 0x40000000 -#define CFG_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */ -#define CFG_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) - -/* - * BR6/OR6 - VME STD (16 bit) - */ -#define VME_STD_BASE 0xFE000000 -#define CFG_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */ -#define CFG_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) - -/* - * BR7/OR7 - SHORT I/O + RTC + IACK (16 bit) - */ -#define VME_SHORT_BASE 0xFF000000 -#define CFG_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */ -#define CFG_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) - -/*----------------------------------------------------------------------- - * Board Control and Status Region: - *----------------------------------------------------------------------- - */ -#ifndef __ASSEMBLY__ -typedef struct ip860_bcsr_s { - unsigned char shmem_addr; /* +00 shared memory address register */ - unsigned char reserved0; - unsigned char mbox_addr; /* +02 mailbox address register */ - unsigned char reserved1; - unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */ - unsigned char reserved2; - unsigned char vme_int_pend; /* +06 VME interrupt pending register */ - unsigned char reserved3; - unsigned char bd_int_mask; /* +08 board interrupt mask register */ - unsigned char reserved4; - unsigned char bd_int_pend; /* +0A board interrupt pending register */ - unsigned char reserved5; - unsigned char bd_ctrl; /* +0C board control register */ - unsigned char reserved6; - unsigned char bd_status; /* +0E board status register */ - unsigned char reserved7; - unsigned char vme_irq; /* +10 VME interrupt request register */ - unsigned char reserved8; - unsigned char vme_ivec; /* +12 VME interrupt vector register */ - unsigned char reserved9; - unsigned char cli_mbox; /* +14 clear mailbox irq */ - unsigned char reservedA; - unsigned char rtc; /* +16 RTC control register */ - unsigned char reservedB; - unsigned char mbox_data; /* +18 mailbox read/write register */ - unsigned char reservedC; - unsigned char wd_trigger; /* +1A Watchdog trigger register */ - unsigned char reservedD; - unsigned char rmw_req; /* +1C RMW request register */ - unsigned char reservedE; - unsigned char bd_rev; /* +1E Board Revision register */ -} ip860_bcsr_t; -#endif /* __ASSEMBLY__ */ - -/*----------------------------------------------------------------------- - * Board Control Register: bd_ctrl (Offset 0x0C) - *----------------------------------------------------------------------- - */ -#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */ -#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */ -#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */ -#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h deleted file mode 100644 index c1565fc..0000000 --- a/include/configs/IPHASE4539.h +++ /dev/null @@ -1,356 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * This file is based on similar values for other boards found in - * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG /* General debug */ - -/*----------------------------------------------------------------------- - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */ - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/*----------------------------------------------------------------------- - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -/*----------------------------------------------------------------------- - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 3 /* which channel for ether */ - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) - -/*----------------------------------------------------------------------- - * - Rx-CLK is CLK14 - * - Tx-CLK is CLK16 - * - Select bus for bd/buffers (see 28-13) - * - Half duplex - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -/* other options */ - -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#define CONFIG_BAUDRATE 19200 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ -#ifdef CONFIG_SOFT_I2C -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -#define CONFIG_COMMANDS CONFIG_CMD_DFL - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */ - /* for versions < 2.4.5-pre5 */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0x04400000 - -#define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */ - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration (Setup by the - * startup code). Please note that CFG_SDRAM_BASE _must_ start at 0. - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF800000 - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */ -#define CFG_MAX_FLASH_SIZE (CFG_MAX_FLASH_SECT * 0x10000) /* 4 MB */ - -#define CFG_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Environment in FLASH, there is little space left in Serial EEPROM */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x10000) /* 2. sector */ - - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\ - ( HRCW_L2CPC10 | HRCW_ISB110 ) |\ - ( HRCW_MMR11 | HRCW_APPC10 ) |\ - ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ - ) /* 0x14863245 */ - -/* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 /* We keep original value */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR 0xA01C0000 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR 0X4205C000 - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined (CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - *----------------------------------------------------------------------- - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/*----------------------------------------------------------------------- - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - */ - -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801) -#define CFG_OR0_PRELIM 0xFF800882 -#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041) -#define CFG_OR1_PRELIM 0xF8002CD0 - -#define CFG_PSDMR 0x404A241A -#define CFG_MPTPR 0x00007400 -#define CFG_PSRT 0x00000007 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h deleted file mode 100644 index 65056a2..0000000 --- a/include/configs/ISPAN.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * Support for Interphase iSPAN Communications Controllers - * (453x and others). Tested on 4532. - * - * Derived from iSPAN 4539 port (iphase4539) by - * Wolfgang Grandegger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC8260 /* This is an MPC8260 CPU */ -#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/*----------------------------------------------------------------------- - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * If CONFIG_CONS_NONE is defined, then the serial console routines must be - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* Define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */ -#undef CONFIG_CONS_NONE /* Define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */ - -/*----------------------------------------------------------------------- - * Select Ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC). - * - * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must - * be defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */ -#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */ - -#ifdef CONFIG_ETHER_ON_FCC - -#if CONFIG_ETHER_INDEX == 3 - -#define CFG_PHY_ADDR 0 -#define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) -#define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) - -#endif /* CONFIG_ETHER_INDEX == 3 */ - -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 3 /* Port D */ - -#define CFG_MDIO_PIN 0x00040000 /* PD13 */ -#define CFG_MDC_PIN 0x00080000 /* PD12 */ - -#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ - else iop->pdat &= ~CFG_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ - else iop->pdat &= ~CFG_MDC_PIN - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#define CONFIG_8260_CLKIN 65536000 /* in Hz */ -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_REGINFO \ - ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS */ -#include - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* #undef to save memory */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* Max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* Default load address */ - -#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0x09900000 - -#define CONFIG_MISC_INIT_R /* We need misc_init_r() */ - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#else -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_MAX_FLASH_BANKS 1 /* Max num of memory banks */ -#define CFG_MAX_FLASH_SECT 142 /* Max num of sects on one chip */ - -/* Environment is in flash, there is little space left in Serial EEPROM */ -#define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ -#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * If you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -/* 0x1686B245 */ -#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\ - HRCW_L2CPC10 | HRCW_ISB110 |\ - HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\ - HRCW_CS10PC01 | HRCW_MODCK_H0101 \ - ) -/* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0F00000 -#ifdef CFG_REV_B -#define CFG_DEFAULT_IMMR 0xFF000000 -#endif /* CFG_REV_B */ -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR 0xA01C0000 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR 0x42250000/* 0x4205C000 */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined (CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - *----------------------------------------------------------------------- - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/*----------------------------------------------------------------------- - * Init Memory Controller: - * - * Bank Bus Machine PortSize Device - * ---- --- ------- ----------------------------- ------ - * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash - * 1 60x SDRAM 64 bit SDRAM - * 2 Local SDRAM 32 bit SDRAM - */ -#define CFG_USE_FIRMWARE /* If defined - do not initialise memory - controller, rely on initialisation - performed by the Interphase boot firmware. - */ - -#define CFG_OR0_PRELIM 0xFE000882 -#ifdef CFG_REV_B -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_8 | BRx_V) -#else /* Rev. D */ -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_16 | BRx_V) -#endif /* CFG_REV_B */ - -#define CFG_MPTPR 0x7F00 - -/* Please note that 60x SDRAM MUST start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_60x_BR 0x00000041 -#define CFG_60x_OR 0xF0002CD0 -#define CFG_PSDMR 0x0049929A -#define CFG_PSRT 0x07 - -#define CFG_LSDRAM_BASE 0xF7000000 -#define CFG_LOC_BR 0x00001861 -#define CFG_LOC_OR 0xFF803280 -#define CFG_LSDMR 0x8285A552 -#define CFG_LSRT 0x07 - -#endif /* __CONFIG_H */ diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h deleted file mode 100644 index a0cb1dd..0000000 --- a/include/configs/IVML24.h +++ /dev/null @@ -1,474 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_IVML24 1 /* ...on a IVML24 board */ - -#if defined (CONFIG_IVML24_16M) -# define CONFIG_IDENT_STRING " IVML24" -#elif defined (CONFIG_IVML24_32M) -# define CONFIG_IDENT_STRING " IVML24_128" -#elif defined (CONFIG_IVML24_64M) -# define CONFIG_IDENT_STRING " IVML24_256" -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_8xx_GCLK_FREQ 50331648 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_BOOTP_MASK \ - ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CFG_PB_12V_ENABLE 0x00002000 /* PB 18 */ -#define CFG_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */ -#define CFG_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ -#define CFG_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ -#define CFG_PB_IDE_MOTOR 0x00020000 /* PB 14 */ - -#define CFG_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ -#define CFG_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR - -#if defined (CONFIG_IVML24_16M) -# define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#elif defined (CONFIG_IVML24_32M) -# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#elif defined (CONFIG_IVML24_64M) -# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#endif - -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF000000 -#ifdef DEBUG -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) - -# if defined (CONFIG_IVML24_16M) -# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -# elif defined (CONFIG_IVML24_32M) -# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWP) -# elif defined (CONFIG_IVML24_64M) -# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWP) -# endif - -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* EARB, DBGC and DBPC are initialised by the HCW */ -/* => 0x000000C0 */ -#define CFG_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00B0C0C0 */ -#define CFG_PLPRCR \ - ( (11 << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800014 */ -#define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD101 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/* 0x00C3 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* TIMEP=2 */ -#define CFG_RCCR 0x0200 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CFG_RMDS 0 - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/ -#define CFG_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */ - -#define CFG_ATA_BASE_ADDR 0xFE100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 -#undef CFG_ATA_IDE1_OFFSET /* only one IDE bus available */ - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* EPROMs are 512kb */ -#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR) - -#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \ - CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \ - CFG_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR1/OR1 - ELIC SACCO bank @ 0xFE000000 - * - * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 - */ -#define ELIC_SACCO_BASE 0xFE000000 -#define ELIC_SACCO_OR_AM 0xFFFF8000 -#define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) - -#define CFG_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - ELIC_SACCO_TIMING) -#define CFG_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR2/OR2 - ELIC EPIC bank @ 0xFE008000 - * - * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 - */ -#define ELIC_EPIC_BASE 0xFE008000 -#define ELIC_EPIC_OR_AM 0xFFFF8000 -#define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) - -#define CFG_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - ELIC_EPIC_TIMING) -#define CFG_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR3/OR3: SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) - -/* - * BR4/OR4 - HDLC Address - * - * AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0 - */ -#define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */ -#define HDLC_ADDR_OR_AM 0xFFFF8000 -#define HDLC_ADDR_TIMING OR_SCY_1_CLK - -#define CFG_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING) -#define CFG_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V ) - -/* - * BR5/OR5: SHARC ADSP-2165L - * - * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 - */ -#define SHARC_BASE 0xFE400000 -#define SHARC_OR_AM 0xFFC00000 -#define SHARC_TIMING OR_SCY_0_CLK - -#define CFG_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING ) -#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MBMR_PTB 204 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ - -#if defined (CONFIG_IVML24_16M) -# define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ -#elif defined (CONFIG_IVML24_32M) -# define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ -#elif defined (CONFIG_IVML24_64M) -# define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */ -#endif - - -/* - * MBMR settings for SDRAM - */ - -#if defined (CONFIG_IVML24_16M) - /* 8 column SDRAM */ -# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -#elif defined (CONFIG_IVML24_32M) -/* 128 MBit SDRAM */ -# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -#elif defined (CONFIG_IVML24_64M) -/* 128 MBit SDRAM */ -# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h deleted file mode 100644 index 46b4d53..0000000 --- a/include/configs/IVMS8.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */ - -#if defined (CONFIG_IVMS8_16M) -# define CONFIG_IDENT_STRING " IVMS8" -#elif defined (CONFIG_IVMS8_32M) -# define CONFIG_IDENT_STRING " IVMS8_128" -#elif defined (CONFIG_IVMS8_64M) -# define CONFIG_IDENT_STRING " IVMS8_256" -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_8xx_GCLK_FREQ 50331648 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_BOOTP_MASK \ - ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CFG_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ -#define CFG_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ -#define CFG_PB_IDE_MOTOR 0x00020000 /* PB 14 */ - -#define CFG_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ -#define CFG_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#if defined (CONFIG_IVMS8_16M) -# define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#elif defined (CONFIG_IVMS8_32M) -# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#elif defined (CONFIG_IVMS8_64M) -# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#endif - -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF000000 -#ifdef DEBUG -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -# if defined (CONFIG_IVMS8_16M) -# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -# elif defined (CONFIG_IVMS8_32M) -# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWP) -# elif defined (CONFIG_IVMS8_64M) -# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWP) -# endif -#else -# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* EARB, DBGC and DBPC are initialised by the HCW */ -/* => 0x000000C0 */ -#define CFG_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00B0C0C0 */ -#define CFG_PLPRCR \ - ( (11 << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800014 */ -#define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD101 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/* 0x00C3 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* TIMEP=2 */ -#define CFG_RCCR 0x0200 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CFG_RMDS 0 - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* The IVMS8 has only 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */ - -#define CFG_ATA_BASE_ADDR 0xFE100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 -#undef CFG_ATA_IDE1_OFFSET /* only one IDE bus available */ - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* EPROMs are 512kb */ -#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR1/OR1 - ELIC SACCO bank @ 0xFE000000 - * - * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 - */ -#define ELIC_SACCO_BASE 0xFE000000 -#define ELIC_SACCO_OR_AM 0xFFFF8000 -#define ELIC_SACCO_TIMING 0x00000F26 - -#define CFG_OR1 (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING) -#define CFG_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR2/OR2 - ELIC EPIC bank @ 0xFE008000 - * - * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 - */ -#define ELIC_EPIC_BASE 0xFE008000 -#define ELIC_EPIC_OR_AM 0xFFFF8000 -#define ELIC_EPIC_TIMING 0x00000F26 - -#define CFG_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING) -#define CFG_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR3/OR3: SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) - -/* - * BR4/OR4: not used - */ - -/* - * BR5/OR5: SHARC ADSP-2165L - * - * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 - */ -#define SHARC_BASE 0xFE400000 -#define SHARC_OR_AM 0xFFC00000 -#define SHARC_TIMING 0x00000700 - -#define CFG_OR5 (SHARC_OR_AM | SHARC_TIMING ) -#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MBMR_PTB 204 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#if defined (CONFIG_IVMS8_16M) - #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ -#elif defined (CONFIG_IVMS8_32M) -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ -#elif defined (CONFIG_IVMS8_64M) -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */ -#endif - - -/* - * MBMR settings for SDRAM - */ - -#if defined (CONFIG_IVMS8_16M) - /* 8 column SDRAM */ -# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -#elif defined (CONFIG_IVMS8_32M) -/* 128 MBit SDRAM */ -#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -#elif defined (CONFIG_IVMS8_64M) -/* 128 MBit SDRAM */ -#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) - -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h deleted file mode 100644 index afba5c6..0000000 --- a/include/configs/IceCube.h +++ /dev/null @@ -1,356 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_ICECUBE 1 /* ... on IceCube board */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CFG_XLB_PIPELINING 1 - -#define CONFIG_NET_MULTI 1 -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 - -#define ADD_PCI_CMD CFG_CMD_PCI - -#else /* MPC5100 */ - -#define CONFIG_MII 1 -#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* USB */ -#if 1 -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 -#endif - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - ADD_PCI_CMD | \ - ADD_USB_CMD ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT16 1 -#endif -#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT08 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if defined(CONFIG_MPC5200) -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ -#endif -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE 0xFF000000 -#define CFG_FLASH_SIZE 0x01000000 -#if !defined(CFG_LOWBOOT) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000) -#else /* CFG_LOWBOOT */ -#if defined(CFG_LOWBOOT08) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000 + 0x00800000) -#endif -#if defined(CFG_LOWBOOT16) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) -#endif -#endif /* CFG_LOWBOOT */ -#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ - -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ - - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#ifdef CONFIG_MPC5200_DDR -#define CFG_GPS_PORT_CONFIG 0x90000004 -#else -#define CFG_GPS_PORT_CONFIG 0x10000004 -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#ifdef CONFIG_MPC5200_DDR - -#define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE) -#define CFG_BOOTCS_SIZE 0x00800000 -#define CFG_BOOTCS_CFG 0x00047801 -#define CFG_CS1_START CFG_FLASH_BASE -#define CFG_CS1_SIZE 0x00800000 -#define CFG_CS1_CFG 0x00047800 - -#else /* !CONFIG_MPC5200_DDR */ - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00047801 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#endif /* CONFIG_MPC5200_DDR */ - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/JSE.h b/include/configs/JSE.h deleted file mode 100644 index ccd1f19..0000000 --- a/include/configs/JSE.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * (C) Copyright 2003 Picture Elements, Inc. - * Stephen Williams - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options for the JSE board - * (Theoretically easy to change, but the board is fixed.) - */ - -#define CONFIG_JSE 1 - /* JSE has a PPC405GPr */ -#define CONFIG_405GP 1 - /* ... which is a 4xxx series */ -#define CONFIG_4xx 1 - /* ... with a 33MHz OSC. connected to the SysCLK input */ -#define CONFIG_SYS_CLK_FREQ 33333333 - /* ... with on-chip memory here (4KBytes) */ -#define CFG_OCM_DATA_ADDR 0xF4000000 -#define CFG_OCM_DATA_SIZE 0x00001000 - /* Do not set up locked dcache as init ram. */ -#undef CFG_INIT_DCACHE_CS - - /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */ -#define CONFIG_SYSTEMACE 1 -#define CFG_SYSTEMACE_BASE 0xf0000000 -#define CONFIG_DOS_PARTITION 1 - - /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ -#define CFG_TEMP_STACK_OCM 1 - /* ... place INIT RAM in the OCM address */ -# define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR - /* ... give it the whole init ram */ -# define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE - /* ... Shave a bit off the end for global data */ -# define CFG_GBL_DATA_SIZE 128 -# define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - /* ... and place the stack pointer at the top of what's left. */ -# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - /* Enable board_pre_init function */ -#define CONFIG_BOARD_PRE_INIT 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 - /* Disable post-clk setup init function */ -#undef CONFIG_BOARD_POSTCLK_INIT - /* Disable call to post_init_f: late init function. */ -#undef CONFIG_POST - /* Enable DRAM test. */ -#define CFG_DRAM_TEST 1 - /* Enable misc_init_r function. */ -#define CONFIG_MISC_INIT_R 1 - - /* JSE has EEPROM chips that are good for environment. */ -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_IS_IN_EEPROM 1 -#undef CFG_ENV_IS_NOWHERE - - /* This is the 7bit address of the device, not including P. */ -#define CFG_I2C_EEPROM_ADDR 0x50 - /* After the device address, need one more address byte. */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 - /* The EEPROM is 512 bytes. */ -#define CFG_EEPROM_SIZE 512 - /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - /* Put the environment in the second half. */ -#define CFG_ENV_OFFSET 0x00 -#define CFG_ENV_SIZE 512 - - - /* The JSE connects UART1 to the console tap connector. */ -#define CONFIG_UART1_CONSOLE 1 - /* Set console baudrate to 9600 */ -#define CONFIG_BAUDRATE 9600 - -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO - -/* - * Configuration related to auto-boot. - * - * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait - * before resorting to autoboot. This value can be overridden by the - * bootdelay environment variable. - * - * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the - * user that an autoboot will happen. - * - * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will - * execute to boot the JSE. This loads the uimage and initrd.img files - * from CompactFlash into memory, then boots them from memory. - * - * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get - * it going on the JSE. - */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw" -#define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000" - - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_FLASH | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_PCI | \ - CFG_CMD_PING ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - /* watchdog disabled */ -#undef CONFIG_WATCHDOG - /* SPD EEPROM (sdram speed config) disabled */ -#undef CONFIG_SPD_EEPROM -#undef SPD_EEPROM_ADDRESS - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* - * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CFG_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - */ -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * External peripheral base address - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CFG_KEY_REG_BASE_ADDR 0xF0100000 -#define CFG_IR_REG_BASE_ADDR 0xF0200000 -#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h deleted file mode 100644 index 7bbceb0..0000000 --- a/include/configs/KAREF.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * (C) Copyright 2004 Sandburst Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference - * design. - ***********************************************************************/ - -/* - * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $ - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ -#undef CFG_DRAM_TEST /* Disable-takes long time!*/ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_VERY_BIG_RAM 1 -#define CONFIG_VERSION_VARIABLE - -#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design" - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) -#define CFG_KAREF_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000) -#define CFG_OFEM_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08400000) -#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000) -#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) - -/* Here for completeness */ -#define CFG_OFEMAC_BASE (CFG_PERIPHERAL_BASE + 0x08600000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) -#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR - -#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SERIAL_MULTI 1 -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 8 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ -#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C hardware support */ -#undef CONFIG_SOFT_I2C /* I2C !bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */ - - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ -#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ - -#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */ -#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR) - -#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Networking - *----------------------------------------------------------------------*/ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ -#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ -#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ -#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ -#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ -#define CONFIG_PHY_RESET_DELAY 1000 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ -#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ -#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ - - -/*----------------------------------------------------------------------- - * Console/Commands/Parser - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_PING | \ - CFG_CMD_DIAG | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT) - -/* Include NetConsole support */ -#define CONFIG_NETCONSOLE - -/* Include auto complete with tabs */ -#define CONFIG_AUTO_COMPLETE 1 -#define CFG_AUTO_COMPLETE 1 -#define CFG_ALT_MEMTEST 1 /* use real memory test */ - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */ -#define CFG_PROMPT_HUSH_PS2 "> " - - -/*----------------------------------------------------------------------- - * Console Buffer - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) - /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of cmd args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test - *----------------------------------------------------------------------*/ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Compact Flash (in true IDE mode) - *----------------------------------------------------------------------*/ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0000000 -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ -#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ - -#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride - to get to the correct offset */ -#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ - -/*----------------------------------------------------------------------- - * PCI - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ -#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ -#define CFG_PCI_TARGET_INIT /* let board init pci target*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ -#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ -#endif - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CFG_LOAD_ADDR 0x8000000 /* default load address */ -#define CFG_EXTBDINFO 1 /* use extended board_info */ - -#define CFG_HZ 100 /* decr freq: 1 ms ticks */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h deleted file mode 100644 index 9b950fc..0000000 --- a/include/configs/KUP4K.h +++ /dev/null @@ -1,489 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - * Derived from ../tqm8xx/tqm8xx.c - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_KUP4K 1 /* ...on a KUP4K module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ -#endif - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - - -#undef CONFIG_BOOTARGS - - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 0:1; bootm 200000\0" \ -"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 2:1; bootm 200000\0" \ -"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \ -"panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ -"ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ - ":${netmask}:${hostname}:${netdev}:off\0" \ -"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ -"netdev=eth0\0" \ -"contrast=55\0" \ -"silent=1\0" \ -"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \ -"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \ - "cp.b 200000 40050000 14000\0" - -#define CONFIG_BOOTCOMMAND \ - "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot" - - -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_MISC_INIT_F 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - - -/* - * enable I2C and select the hardware/software driver - */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - - -/*----------------------------------------------------------------------- - * I2C Configuration - */ - -#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ -#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ - - -/* List of I2C addresses to be verified by POST */ - -#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \ - CFG_I2C_RTC_ADDR, \ - } - - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -#define CFG_DISCOVER_PHY -#define CONFIG_MII - -#if 0 -#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */ -#endif -#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */ - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#if 1 -/* POST support */ - -#define CONFIG_POST (CFG_POST_CPU | \ - CFG_POST_RTC | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif -#endif - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x000400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x200000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } - -#define CFG_CONSOLE_INFO_QUIET 1 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 - -/* Address and size of Redundant Environment Sector */ -#if 0 -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#if 1 -#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P' */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */ -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#define CFG_PLPRCR ( (5-1)< ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR 0x400 - -/* - * MAMR settings for SDRAM - */ -#define CFG_MAMR 0x80802114 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#if 0 -#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" -#endif -#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ -#define CONFIG_SILENT_CONSOLE 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h deleted file mode 100644 index cd38b0f..0000000 --- a/include/configs/KUP4X.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - * Derived from ../tqm8xx/tqm8xx.c - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */ -#define CONFIG_KUP4X 1 /* ...on a KUP4X module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ -#endif - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CFG_8XX_FACT 8 /* Multiply by 8 */ -#define CFG_8XX_XIN 16000000 /* 16 MHz in */ - - -#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) - -/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ -/* in general, we always know this for FADS+new ADS anyway */ -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - - -#undef CONFIG_BOOTARGS - - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw;diskboot 200000 0:1;bootm 200000\0" \ -"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\ - run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\ - usb stop; bootm 200000\0" \ -"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \ -"panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ -"ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ - ":${netmask}:${hostname}:${netdev}:off\0" \ -"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ -"netdev=eth0\0" \ -"silent=1\0" \ -"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \ -"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \ - "cp.b 200000 40040000 14000\0" - -#define CONFIG_BOOTCOMMAND \ - "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot" - - -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_MISC_INIT_F 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* - * enable I2C and select the hardware/software driver - */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - - -/*----------------------------------------------------------------------- - * I2C Configuration - */ - -#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ -#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ - - -/* List of I2C addresses to be verified by POST */ - -#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \ - CFG_I2C_RTC_ADDR, \ - } - - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -#define CFG_DISCOVER_PHY -#define CONFIG_MII - -#if 0 -#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */ -#endif -#undef CONFIG_KUP4K_LOGO - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - - -#if 1 -/* POST support */ - -#define CONFIG_POST (CFG_POST_CPU | \ - CFG_POST_RTC | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif -#endif - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_SNTP | \ - CFG_CMD_USB ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x000400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */ -#define CFG_LOAD_ADDR 0x200000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } - -#define CFG_CONSOLE_INFO_QUIET 1 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 - -/* Address and size of Redundant Environment Sector */ -#if 0 -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#if 1 -#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P' */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */ -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS) - - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ - -/* KUP4K use both slots, SLOT_A as "primary". */ -#define CONFIG_PCMCIA_SLOT_A 1 - -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define PCMCIA_SOCKETS_NO 1 -#define PCMCIA_MEM_WIN_NO 8 -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 -#define CFG_IDE_MAXDEVICE 2 - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - - -#define CFG_MPTPR 0x400 - -/* - * MAMR settings for SDRAM - */ -#define CFG_MAMR 0x80802114 - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#if 0 -#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" -#endif -#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ -#define CONFIG_SILENT_CONSOLE 1 - -#define CONFIG_USB_STORAGE 1 -#define CONFIG_USB_SL811HS 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h deleted file mode 100644 index e44f1cc..0000000 --- a/include/configs/LANTEC.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2001 - * Torsten Stevens, FHG IMS, stevens@ims.fhg.de - * Bruno Achauer, Exet AG, bruno@exet-ag.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - * [derived from config_TQM850L.h] - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */ - -/* - * Port assignments (CONFIG_LANTEC == 1): - * - SMC1: J11 (MDB) ? - * - SMC2: J6 (Feature connector) - * - SCC2: J9 (RJ45) - * - SCC3: J8 (Sub-D9) - * - * Port assignments (CONFIG_LANTEC == 2): TBD - */ - - -#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ -#define CONFIG_8xx_CONS_SCC3 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_CMD_MINIMAL 0 -#define CONFIG_CMD_TINY (CFG_CMD_FLASH | \ - CFG_CMD_MEMORY | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB) -#define CONFIG_CMD_NORMAL (CONFIG_CMD_DFL & ~CFG_CMD_BOOTD & ~CFG_CMD_REISER) -#define CONFIG_CMD_GDB (CONFIG_CMD_NORMAL | CFG_CMD_KGDB) -#define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \ - & ~CFG_CMD_BMP \ - & ~CFG_CMD_BSP \ - & ~CFG_CMD_DISPLAY \ - & ~CFG_CMD_DOC \ - & ~CFG_CMD_DTT \ - & ~CFG_CMD_EEPROM \ - & ~CFG_CMD_ELF \ - & ~CFG_CMD_EXT2 \ - & ~CFG_CMD_FDC \ - & ~CFG_CMD_FDOS \ - & ~CFG_CMD_HWFLOW \ - & ~CFG_CMD_I2C \ - & ~CFG_CMD_IDE \ - & ~CFG_CMD_IRQ \ - & ~CFG_CMD_JFFS2 \ - & ~CFG_CMD_KGDB \ - & ~CFG_CMD_MII \ - & ~CFG_CMD_MMC \ - & ~CFG_CMD_NAND \ - & ~CFG_CMD_PCI \ - & ~CFG_CMD_PCMCIA \ - & ~CFG_CMD_REISER \ - & ~CFG_CMD_SCSI \ - & ~CFG_CMD_SPI \ - & ~CFG_CMD_UNIVERSE\ - & ~CFG_CMD_USB \ - & ~CFG_CMD_VFD \ - & ~CFG_CMD_XIMG ) - -#if CONFIG_LANTEC >= 2 -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#endif - -#if CONFIG_LANTEC >= 2 -# define CONFIG_COMMANDS CONFIG_CMD_FULL -#else -# define CONFIG_COMMANDS (CONFIG_CMD_FULL & ~CFG_CMD_DATE & ~CFG_CMD_NET) -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK) - -/*----------------------------------------------------------------------- - * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX] - *----------------------------------------------------------------------- - */ -#define CONFIG_8xx_GCLK_FREQ 33000000 - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ - /* up to 50 MHz we use a 1:1 clock */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 - /* up to 50 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/5 and OR0/5 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE5_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ - OR_SCY_5_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR5_REMAP CFG_OR0_REMAP -#define CFG_OR5_PRELIM CFG_OR0_PRELIM -#define CFG_BR5_PRELIM ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses */ -#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM) - -#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL \ - ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h deleted file mode 100644 index 5fd6a95..0000000 --- a/include/configs/M5272C3.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Configuation settings for the Motorola MC5272C3 board. - * - * (C) Copyright 2003 Josef Baumgartner - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5272C3_H -#define _M5272C3_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5272 /* define processor type */ - -#define FEC_ENET - -#define CONFIG_BAUDRATE 19200 -#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } - -#define CONFIG_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ - -#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CFG_ENV_OFFSET 0x4000 -#define CFG_ENV_SECT_SIZE 0x2000 -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_IS_EMBEDDED 1 -#else -#define CFG_ENV_ADDR 0xffe04000 -#define CFG_ENV_SECT_SIZE 0x2000 -#define CFG_ENV_IS_IN_FLASH 1 -#endif - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) | \ - CFG_CMD_MII) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#define CONFIG_BOOTDELAY 5 - -#define CFG_PROMPT "-> " -#define CFG_LONGHELP /* undef to save memory */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x20000 - -#define CFG_MEMTEST_START 0x400 -#define CFG_MEMTEST_END 0x380000 - -#define CFG_HZ 1000 -#define CFG_CLK 66000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CFG_MBAR 0x10000000 /* Register Base Addrs */ - -#define CFG_SCR 0x0003; -#define CFG_SPR 0xffff; - -#define CFG_DISCOVER_PHY -#define CFG_ENET_BD_BASE 0x380000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ -#define CFG_FLASH_BASE 0xffe00000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CFG_MONITOR_BASE 0x20000 -#else -#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) -#endif - -#define CFG_MONITOR_LEN 0x20000 -#define CFG_MALLOC_LEN (256 << 10) -#define CFG_BOOTPARAMS_LEN 64*1024 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 1000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -#define CFG_BR0_PRELIM 0xFFE00201 -#define CFG_OR0_PRELIM 0xFFE00014 - -#define CFG_BR1_PRELIM 0 -#define CFG_OR1_PRELIM 0 - -#define CFG_BR2_PRELIM 0x30000001 -#define CFG_OR2_PRELIM 0xFFF80000 - -#define CFG_BR3_PRELIM 0 -#define CFG_OR3_PRELIM 0 - -#define CFG_BR4_PRELIM 0 -#define CFG_OR4_PRELIM 0 - -#define CFG_BR5_PRELIM 0 -#define CFG_OR5_PRELIM 0 - -#define CFG_BR6_PRELIM 0 -#define CFG_OR6_PRELIM 0 - -#define CFG_BR7_PRELIM 0x00000701 -#define CFG_OR7_PRELIM 0xFFC0007C - -/*----------------------------------------------------------------------- - * Port configuration - */ -#define CFG_PACNT 0x00000000 -#define CFG_PADDR 0x0000 -#define CFG_PADAT 0x0000 -#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ -#define CFG_PBDDR 0x0000 -#define CFG_PBDAT 0x0000 -#define CFG_PDCNT 0x00000000 - -#endif /* _M5272C3_H */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h deleted file mode 100644 index cbb3e3b..0000000 --- a/include/configs/M5282EVB.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Configuation settings for the Motorola MC5282EVB board. - * - * (C) Copyright 2003 Josef Baumgartner - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _CONFIG_M5282EVB_H -#define _CONFIG_M5282EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5282 /* define processor type */ - -#define FEC_ENET - -#define CONFIG_BAUDRATE 19200 -#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } - -#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#define CFG_ENV_ADDR 0xffe04000 -#define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_IS_IN_FLASH 1 - - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#define CONFIG_BOOTDELAY 5 - -#define CFG_PROMPT "-> " -#define CFG_LONGHELP /* undef to save memory */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x20000 - -#define CFG_MEMTEST_START 0x400 -#define CFG_MEMTEST_END 0x380000 - -#define CFG_HZ 1000000 -#define CFG_CLK 64000000 - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -#define CFG_MBAR 0x40000000 - -#undef CFG_DISCOVER_PHY -#define CFG_ENET_BD_BASE 0x380000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ -#define CFG_FLASH_BASE 0xffe00000 -#define CFG_INT_FLASH_BASE 0xf0000000 - -/* If M5282 port is fully implemented the monitor base will be behind - * the vector table. */ -/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */ -#define CFG_MONITOR_BASE 0x20000 - -#define CFG_MONITOR_LEN 0x20000 -#define CFG_MALLOC_LEN (256 << 10) -#define CFG_BOOTPARAMS_LEN 64*1024 - - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_SECT 35 -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_FLASH_ERASE_TOUT 10000000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 - - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ - - -/*----------------------------------------------------------------------- - * Port configuration - */ - - -#endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/MBX.h b/include/configs/MBX.h deleted file mode 100644 index d6e3fb8..0000000 --- a/include/configs/MBX.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the MBX8xx board. - * - * ----------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * Changed 2002-10-01 - * Added PCMCIA defines mostly taken from other U-Boot boards that - * have PCMCIA already working. If you find any bugs, incorrect assumptions - * feel free to fix them yourself and submit a patch. - * Rod Boyce - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical memory map as defined by the MBX PGM - */ -#define CFG_IMMR 0xFA200000 /* Internal Memory Mapped Register*/ -#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */ -#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ -#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */ -#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ -#define CFG_PCIMEM_OR 0xA0000108 -#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ -#define CFG_PCIBRIDGE_OR 0xFFFF0108 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) -#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Offset in DPMEM where we keep the VPD data - */ -#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xfe000000 -#ifdef DEBUG -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#undef CFG_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * NVRAM Configuration - * - * Note: the MBX is special because there is already a firmware on this - * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we - * access the NVRAM at the offset 0x1000. - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ -#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000) -#define CFG_ENV_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC ) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) -#define CFG_SCCR SCCR_TBS - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6 - -#define CONFIG_PCMCIA_SLOT_A 1 - - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * Debug Entry Mode - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h deleted file mode 100644 index 0ca0970..0000000 --- a/include/configs/MBX860T.h +++ /dev/null @@ -1,407 +0,0 @@ - /* - * A collection of structures, addresses, and values associated with - * the Motorola 860T MBX board. - * Copied from the FADS stuff, which was originally copied from the MBX stuff! - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * Rob Taylor coverted it back to MBX - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#include - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MBX 1 - -#define CONFIG_8xx_CPUCLOCK 40 -#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK) -#define TARGET_SYSTEM_FREQUENCY 40 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_BAUDRATE 9600 - -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 40000000 /* 50 MHz in */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 1 -#define CONFIG_8xx_BOOTDELAY -1 /* autoboot disabled */ -#define CONFIG_8xx_TFTP_MODE -#else -#define CONFIG_8xx_BOOTDELAY 5 /* autoboot after 5 seconds */ -#undef CONFIG_8xx_TFTP_MODE -#endif - -#define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */ -#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ -#define CONFIG_BOOTARGS " " -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0800000 /* 4 ... 8 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFA00000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) -#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */ -#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ -#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */ -#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ -#define CFG_PCIMEM_OR 0xA0000108 -#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ -#define CFG_PCIBRIDGE_OR 0xFFFF0108 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) -#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Offset in DPMEM where we keep the VPD data - */ -#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x00000000 -/*0xFE000000*/ -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_HWINFO_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN) -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * NVRAM Configuration - * - * Note: the MBX is special because there is already a firmware on this - * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we - * access the NVRAM at the offset 0x1000. - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ -#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000) -#define CFG_ENV_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) -#define CFG_SCCR SCCR_TBS - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - - -#define BCSR_ADDR ((uint) 0xFF010000) -#define BCSR_SIZE ((uint)(64 * 1024)) - -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFF010000 /* FLASH bank #0 */ - -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFFF00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CFG_BR0_PRELIM (0xFE000000 | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM 0xFFC00000 | OR_ACS_DIV4 -#define CFG_BR1_PRELIM (0x00000000 | BR_MS_UPMA | BR_V ) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CFG_MAMR 0x13821000 -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ - - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define BCSR0 ((uint) (BCSR_ADDR + 00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* FADS bitvalues by Helmut Buchsbaum - * see MPC8xxADS User's Manual for a proper description - * of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT (23) -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#ifdef CONFIG_MPC823 -#define BCSR4_USB_EN ((uint)0x08000000) -#endif /* CONFIG_MPC823 */ -#ifdef CONFIG_MPC860SAR -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860SAR */ -#ifdef CONFIG_MPC860T -#define BCSR4_FETH_EN ((uint)0x08000000) -#endif /* CONFIG_MPC860T */ -#define BCSR4_USB_SPEED ((uint)0x04000000) -#define BCSR4_VCCO ((uint)0x02000000) -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#define BCSR4_MODEM_EN ((uint)0x00100000) -#define BCSR4_DATA_VOICE ((uint)0x00080000) - -#define CONFIG_DRAM_40MHZ 1 - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_fads) - -/* - * MPC8xx CPM Options - */ -#define CONFIG_SCC_ENET 1 -#define CONFIG_SCC1_ENET 1 -#define CONFIG_FEC_ENET 1 -#undef CONFIG_CPM_IIC -#undef CONFIG_UCODE_PATCH - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -/* PCMCIA configuration */ - -#define PCMCIA_MAX_SLOTS 2 - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h deleted file mode 100644 index b965571..0000000 --- a/include/configs/METROBOX.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2004 Sandburst Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * METROBOX.h - configuration Sandburst MetroBox - ***********************************************************************/ - -/* - * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $ - * - * - * $Log: METROBOX.h,v $ - * Revision 1.21 2005/06/03 15:05:25 tsawyer - * MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB - * - * Revision 1.20 2005/04/11 20:51:11 tsawyer - * fix ethernet - * - * Revision 1.19 2005/04/06 15:13:36 tsawyer - * Update appropriate files to coincide with u-boot 1.1.3 - * - * Revision 1.18 2005/03/10 14:16:02 tsawyer - * add def'n for cis8201 short etch option. - * - * Revision 1.17 2005/03/09 19:49:51 tsawyer - * Remove KGDB to allow use of 2nd serial port - * - * Revision 1.16 2004/12/02 19:00:23 tsawyer - * Add misc_init_f to turn on i2c-1 and all four fans before sdram init - * - * Revision 1.15 2004/09/15 18:04:12 tsawyer - * add multiple serial port support - * - * Revision 1.14 2004/09/03 15:27:51 tsawyer - * All metrobox boards are at 66.66 sys clock - * - * Revision 1.13 2004/08/05 20:27:46 tsawyer - * Remove system ace definitions, add net console support - * - * Revision 1.12 2004/07/29 20:00:13 tsawyer - * Add i2c bus 1 - * - * Revision 1.11 2004/07/21 13:44:18 tsawyer - * SystemACE is out, CF direct to local bus is in - * - * Revision 1.10 2004/06/29 19:08:55 tsawyer - * Add CONFIG_MISC_INIT_R - * - * Revision 1.9 2004/06/28 21:30:53 tsawyer - * Fix default BOOTARGS - * - * Revision 1.8 2004/06/17 15:51:08 tsawyer - * auto complete - * - * Revision 1.7 2004/06/17 15:08:49 tsawyer - * Add autocomplete - * - * Revision 1.6 2004/06/15 12:33:57 tsawyer - * debugging checkpoint - * - * Revision 1.5 2004/06/12 19:48:28 tsawyer - * Debugging checkpoint - * - * Revision 1.4 2004/06/02 13:03:06 tsawyer - * Fix eth addrs - * - * Revision 1.3 2004/05/18 19:56:10 tsawyer - * Change default bootcommand to pImage.metrobox - * - * Revision 1.2 2004/05/18 14:13:44 tsawyer - * Add bringup values for bootargs and bootcommand. - * Remove definition of ipaddress and serverip addresses. - * - * Revision 1.1 2004/04/16 15:08:54 tsawyer - * Initial Revision - * - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_METROBOX 1 /* Board is Metrobox */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ -#undef CFG_DRAM_TEST /* Disable-takes long time!*/ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_VERY_BIG_RAM 1 -#define CONFIG_VERSION_VARIABLE - -#define CONFIG_IDENT_STRING " Sandburst Metrobox" - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) -#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000) -#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000) -#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) -#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR - -#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SERIAL_MULTI 1 -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 8 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ -#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C hardware support */ -#undef CONFIG_SOFT_I2C /* I2C !bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */ - - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ -#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ - -#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */ -#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR) - -#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none " -#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000" -#define CONFIG_BOOTDELAY 5 /* disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Networking - *----------------------------------------------------------------------*/ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ -#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ -#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ -#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ -#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ -#define CONFIG_PHY_RESET_DELAY 1000 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ -#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ -#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ - - -/*----------------------------------------------------------------------- - * Console/Commands/Parser - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_PING | \ - CFG_CMD_DIAG | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT) - -/* tbs 09-March-2005 Removed to be able to use 2nd serial */ -/* CFG_CMD_KGDB | \ */ - - -/* Include NetConsole support */ -#define CONFIG_NETCONSOLE - -/* Include auto complete with tabs */ -#define CONFIG_AUTO_COMPLETE 1 -#define CFG_AUTO_COMPLETE 1 -#define CFG_ALT_MEMTEST 1 /* use real memory test */ - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */ -#define CFG_PROMPT_HUSH_PS2 "> " - - -/*----------------------------------------------------------------------- - * Console Buffer - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) - /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of cmd args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test - *----------------------------------------------------------------------*/ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Compact Flash (in true IDE mode) - *----------------------------------------------------------------------*/ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0000000 -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ -#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ - -#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride - to get to the correct offset */ -#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ - -/*----------------------------------------------------------------------- - * PCI - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ -#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ -#define CFG_PCI_TARGET_INIT /* let board init pci target*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ -#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ -#endif - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CFG_LOAD_ADDR 0x8000000 /* default load address */ -#define CFG_EXTBDINFO 1 /* use extended board_info */ - -#define CFG_HZ 100 /* decr freq: 1 ms ticks */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h deleted file mode 100644 index 53684ca..0000000 --- a/include/configs/MHPC.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * (C) Copyright 2001 - * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Configuation settings for the miniHiPerCam. - * - * ----------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_MHPC 1 /* on a miniHiPerCam */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */ -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ETHADDR 00:00:5b:ee:de:ad - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#undef CONFIG_UCODE_PATCH - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xFE -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE) -#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */ -#define LCD_VIDEO_COLS 640 -#define LCD_VIDEO_ROWS 480 -#define LCD_VIDEO_FG 255 -#define LCD_VIDEO_BG 0 - -#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */ -#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */ -#define CONFIG_VIDEO_LOGO - -#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */ -#define VIDEO_TSTC_FCT serial_tstc -#define VIDEO_GETC_FCT serial_getc - -#define CONFIG_BR0_WORKAROUND 1 - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_REGINFO ) - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x300000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical memory map - */ -#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xfe000000 - -#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ -#undef CFG_MONITOR_BASE /* to run U-Boot from RAM */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=mhpc-0" -#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)" -*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET CFG_MONITOR_LEN /* Offset of Environment */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_SEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 12-18 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define MPC8XX_SPEED 50000000L -#define MPC8XX_XIN 5000000L /* ref clk */ -#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) -#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ - -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */ -#define CFG_SCCR (SCCR_TBS | SCCR_DFLCD001) - - -/*----------------------------------------------------------------------- - * MAMR settings for SDRAM - 16-14 - * => 0xC080200F - *----------------------------------------------------------------------- - * periodic timer for refresh - */ -#define CFG_MAMR_PTA 0xC0 -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK) - -/* - * BR0 and OR0 (FLASH) used to re-map FLASH - */ - -/* allow for max 8 MB of Flash */ -#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/ -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/ -#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/ - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V ) - -/* - * BR1 and OR1 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ -#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */ - -/* SDRAM timing: drive GPL5 high on first cycle */ -#define CFG_OR_TIMING_SDRAM (OR_G5LS) - -#define CFG_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM ) -#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR2/OR2 - DIMM - */ -#define CFG_OR2 (OR_ACS_DIV4) -#define CFG_BR2 (BR_MS_UPMA) - -/* - * BR3/OR3 - DIMM - */ -#define CFG_OR3 (OR_ACS_DIV4) -#define CFG_BR3 (BR_MS_UPMA) - -/* - * BR4/OR4 - */ -#define CFG_OR4 0 -#define CFG_BR4 0 - -/* - * BR5/OR5 - */ -#define CFG_OR5 0 -#define CFG_BR5 0 - -/* - * BR6/OR6 - */ -#define CFG_OR6 0 -#define CFG_BR6 0 - -/* - * BR7/OR7 - */ -#define CFG_OR7 0 -#define CFG_BR7 0 - - -/*----------------------------------------------------------------------- - * Debug Entry Mode - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h deleted file mode 100644 index db2147b..0000000 --- a/include/configs/MIP405.h +++ /dev/null @@ -1,456 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************** - * High Level Configuration Options - * (easy to change) - ***********************************************************/ -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_MIP405 1 /* ...on a MIP405 board */ -/*********************************************************** - * Note that it may also be a MIP405T board which is a subset of the - * MIP405 - ***********************************************************/ -/*********************************************************** - * WARNING: - * CONFIG_BOOT_PCI is only used for first boot-up and should - * NOT be enabled for production bootloader - ***********************************************************/ -/*#define CONFIG_BOOT_PCI 1*/ -/*********************************************************** - * Clock - ***********************************************************/ -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -/*********************************************************** - * Command definitions - ***********************************************************/ -#define MIP405_COMMON_CMDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SAVES | \ - CFG_CMD_BSP ) - -#if defined(CONFIG_MIP405T) -#define CONFIG_COMMANDS \ - MIP405_COMMON_CMDS -#else -#define CONFIG_COMMANDS \ - (MIP405_COMMON_CMDS | \ - CFG_CMD_USB | \ - CFG_CMD_DOC ) - -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -/************************************************************** - * I2C Stuff: - * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address - * 0x53. - * The Atmel EEPROM uses 16Bit addressing. - ***************************************************************/ - -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#undef CFG_I2C_EEPROM_ADDR_OVERFLOW -#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ - /* 64 byte page write mode using*/ - /* last 6 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */ - -/*************************************************************** - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - ***************************************************************/ -/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 -#define SDRAM_EEPROM_READ_ADDRESS 0xA1 -*/ -/************************************************************** - * Environment definitions - **************************************************************/ -#define CONFIG_BAUDRATE 9600 /* STD Baudrate */ -#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ - -#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ -#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ - -#define CONFIG_IPADDR 10.0.0.100 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_PREBOOT -/*************************************************************** - * defines if the console is stored in the environment - ***************************************************************/ -#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ -/*************************************************************** - * defines if an overwrite_console function exists - *************************************************************/ -#define CFG_CONSOLE_OVERWRITE_ROUTINE -#define CFG_CONSOLE_INFO_QUIET -/*************************************************************** - * defines if the overwrite_console should be stored in the - * environment - **************************************************************/ -#undef CFG_CONSOLE_ENV_OVERWRITE - -/************************************************************** - * loads config - *************************************************************/ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MISC_INIT_R -/*********************************************************** - * Miscellaneous configurable options - **********************************************************/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_BASE_BAUD 916667 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ - /* resource configuration */ -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=mip405-0" -#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)" -*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * Logbuffer Configuration - */ -#undef CONFIG_LOGBUFFER /* supported but not enabled */ -/*----------------------------------------------------------------------- - * Bootcountlimit Configuration - */ -#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */ - -/*----------------------------------------------------------------------- - * POST Configuration - */ -#if 0 /* enable this if POST is desired (is supported but not enabled) */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_RTC | \ - CFG_POST_I2C) - -#endif -/* - * Init Memory Controller: - */ -#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ -#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 - -/* Peripheral Bus Mapping */ -#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ -#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/ -#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ - -#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 -#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in On Chip SRAM) - */ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR 0xF0000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -/* reserve some memory for POST and BOOT limit info */ -#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 32) - -#ifdef CONFIG_POST /* reserve one word for POST Info */ -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) -#endif - -#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ -#define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 12) -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*********************************************************************** - * External peripheral base address - ***********************************************************************/ -#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000 - -/*********************************************************************** - * Last Stage Init - ***********************************************************************/ -#define CONFIG_LAST_STAGE_INIT -/************************************************************ - * Ethernet Stuff - ***********************************************************/ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ -#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */ -/************************************************************ - * RTC - ***********************************************************/ -#define CONFIG_RTC_MC146818 -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/************************************************************ - * IDE/ATA stuff - ************************************************************/ -#if defined(CONFIG_MIP405T) -#define CFG_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */ -#else -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#endif - -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */ -#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ - -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* reset for ide supported... */ -#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ -#define CONFIG_SUPPORT_VFAT -/************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI /* enable ATAPI Support */ - -/************************************************************ - * DISK Partition support - ************************************************************/ -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION /* Experimental */ - -/************************************************************ - * Disk-On-Chip configuration - ************************************************************/ -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ -#define CFG_DOC_SHORT_TIMEOUT -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM -/************************************************************ - * Keyboard support - ************************************************************/ -#undef CONFIG_ISA_KEYBOARD - -/************************************************************ - * Video support - ************************************************************/ -#define CONFIG_VIDEO /*To enable video controller support */ -#define CONFIG_VIDEO_CT69000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#undef CONFIG_VIDEO_ONBOARD -/************************************************************ - * USB support EXPERIMENTAL - ************************************************************/ -#if !defined(CONFIG_MIP405T) -#define CONFIG_USB_UHCI -#define CONFIG_USB_KEYBOARD -#define CONFIG_USB_STORAGE - -/* Enable needed helper functions */ -#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ -#endif -/************************************************************ - * Debug support - ************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/************************************************************ - * support BZIP2 compression - ************************************************************/ -#define CONFIG_BZIP2 1 - -/************************************************************ - * Ident - ************************************************************/ - -#define VERSION_TAG "released" -#if !defined(CONFIG_MIP405T) -#define CONFIG_ISO_STRING "MEV-10072-001" -#else -#define CONFIG_ISO_STRING "MEV-10082-001" -#endif - -#if !defined(CONFIG_BOOT_PCI) -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG -#else -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version" -#endif - - -#endif /* __CONFIG_H */ diff --git a/include/configs/ML2.h b/include/configs/ML2.h deleted file mode 100644 index d8805ea..0000000 --- a/include/configs/ML2.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * ML2.h: ML2 specific config options - * - * Copyright 2002 Mind NV - * - * http://www.mind.be/ - * - * Author : Peter De Schrijver (p2@mind.be) - * - * Derived from : other configuration header files in this tree - * - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL) version 2, incorporated herein by - * reference. Drivers based on or derived from this code fall under the GPL - * and must retain the authorship, copyright and this license notice. This - * file is not a complete program and may only be used when the entire - * program is licensed under the GPL. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_ML2 1 /* ...on a ML2 board */ - - -#define CFG_ENV_IS_IN_FLASH 1 - -#ifdef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#else -#ifdef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#endif -#endif - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#if 1 -#define CONFIG_BOOTCOMMAND "bootm" /* autoboot command */ -#else -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ -#endif - -#define CONFIG_PREBOOT "fsload 0x00100000 /boot/image" - -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#if 0 -#define CONFIG_SERIAL_SOFTWARE_FIFO 4000 -#else -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#endif - -#if 0 -#define CONFIG_BOOTARGS "root=/dev/nfs " \ - "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ - "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4" -#else -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 " \ - "console=ttyS0 console=tty" - -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & \ - ~( CFG_CMD_NET | \ - CFG_CMD_RTC | \ - CFG_CMD_PCI | \ - CFG_CMD_I2C \ - ) ) | \ - CFG_CMD_IRQ | \ - CFG_CMD_KGDB | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF | \ - CFG_CMD_JFFS2 ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SYS_CLK_FREQ 50000000 - -#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* - * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CFG_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - */ -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ - -#define CFG_BASE_BAUD (3125000*16) -#define CFG_NS16550_CLK CFG_BASE_BAUD -#define CFG_DUART_CHAN 0 -#define CFG_NS16550_COM1 0xa0001003 -#define CFG_NS16550_COM2 0xa0011003 -#define CFG_NS16550_REG_SIZE -4 -#define CFG_NS16550 1 -#define CFG_INIT_CHAN1 1 -#define CFG_INIT_CHAN2 1 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x18000000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* BEG ENVIRONNEMENT FLASH */ -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ -#endif -/* END ENVIRONNEMENT FLASH */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ - -#ifdef CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -#define CFG_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00080000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=ml2-0" -#define MTDPARTS_DEFAULT "mtdparts=ml2-0:-@512k(jffs2)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h deleted file mode 100644 index 6ad2feb..0000000 --- a/include/configs/MOUSSE.h +++ /dev/null @@ -1,329 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James F. Dougherty (jfd@cs.stanford.edu) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the MOUSSE board. - * See also: http://www.vooha.com/ - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_MOUSSE 1 -#define CFG_ADDR_MAP_B 1 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#if 1 -#define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */ -#else -#define CONFIG_BOOTCOMMAND "bootm ffe10000" -#endif -#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138" -#define CONFIG_BOOTDELAY 3 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL|CFG_CMD_ASKENV|CFG_CMD_DATE) -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ETH_ADDR "00:10:18:10:00:06" - -#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */ -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include -#include "../board/mousse/mousse.h" - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) -#define CFG_MAXARGS 8 /* Max number of command args */ - -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -#ifdef DEBUG -#define CFG_MONITOR_BASE CFG_SDRAM_BASE -#else -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#endif - -#ifdef DEBUG -#define CFG_MONITOR_LEN (4 << 20) /* lots of mem ... */ -#else -#define CFG_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */ -#endif -#define CFG_MALLOC_LEN (2*(4096 << 10)) /* 2*4096kB for malloc() */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - -#define CFG_EUMB_ADDR 0xFC000000 - -#define CFG_ISA_MEM 0xFD000000 -#define CFG_ISA_IO 0xFE000000 - -#define CFG_FLASH_BASE 0xFFF00000 -#define CFG_FLASH_SIZE ((uint)(512 * 1024)) -#define CFG_RESET_ADDRESS 0xFFF00100 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/ -#define FLASH_BASE0_SIZE 0x80000 /* 512K */ -#define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB - 1MB - 64K FLASH0 SEG =960K - (size=0xf0000)*/ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK 18432000 - -#define CFG_NS16550_COM1 0xFFE08080 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 -#define CFG_HZ 1000 - -#define CFG_ETH_DEV_FN 0x00 -#define CFG_ETH_IOBASE 0x00104000 - - - /* Bit-field values for MCCR1. - */ -#define CFG_ROMNAL 8 -#define CFG_ROMFAL 8 - - /* Bit-field values for MCCR2. - */ -#define CFG_REFINT 0xf5 /* Refresh interval */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CFG_BSTOPRE 0x79 - -#ifdef INCLUDE_ECC -#define USE_ECC 1 -#else /* INCLUDE_ECC */ -#define USE_ECC 0 -#endif /* INCLUDE_ECC */ - - - /* Bit-field values for MCCR3. - */ -#define CFG_REFREC 8 /* Refresh to activate interval */ -#define CFG_RDLAT (4+USE_ECC) /* Data latancy from read command */ - - /* Bit-field values for MCCR4. - */ -#define CFG_PRETOACT 3 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CFG_ACTORW 2 -#define CFG_REGISTERD_TYPE_BUFFER (1-USE_ECC) - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ -#define CFG_RAM_SIZE 0x04000000 /* 64MB */ - - -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff -#define CFG_BANK7_ENABLE 0 - -#define CFG_ODCR 0x7f - - -#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory - see 8240 book for details*/ -#define PCI_MEM_SPACE1_START 0x80000000 -#define PCI_MEM_SPACE2_START 0xfd000000 - -/* IBAT/DBAT Configuration */ -/* Ram: 64MB, starts at address-0, r/w instruction/data */ -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT0L CFG_IBAT0L - -/* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */ -#define CFG_IBAT1U (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP) -#if 0 -#define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 | BATL_MEMCOHERENCE |\ - BATL_WRITETHROUGH | BATL_CACHEINHIBIT) -#else -#define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT) -#endif -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT1L CFG_IBAT1L - -/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */ -#define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT) -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT2L CFG_IBAT2L - -/* PCI Memory region 2: PCI Devices in 0xFD space */ -#define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) -#define CFG_DBAT3U CFG_IBAT3U -#define CFG_DBAT3L CFG_IBAT3L - - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 3 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if 0 -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Size of the Environment Sector */ -#else -#define CFG_ENV_IS_IN_NVRAM 1 -#define CFG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/ -#define CFG_ENV_OFFSET CFG_ENV_ADDR -#define CFG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* Localizations */ -#if 0 -#define CONFIG_ETHADDR 0:0:0:0:1:d -#define CONFIG_IPADDR 172.16.40.113 -#define CONFIG_SERVERIP 172.16.40.111 -#else -#define CONFIG_ETHADDR 0:0:0:0:1:d -#define CONFIG_IPADDR 209.128.93.138 -#define CONFIG_SERVERIP 209.128.93.133 -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_TULIP - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h deleted file mode 100644 index 6195bca..0000000 --- a/include/configs/MPC8260ADS.h +++ /dev/null @@ -1,509 +0,0 @@ -/* - * (C) Copyright 2001 - * Stuart Hughes - * This file is based on similar values for other boards found in other - * U-Boot config files, and some that I found in the mpc8260ads manual. - * - * Note: my board is a PILOT rev. - * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. - * - * (C) Copyright 2003-2004 Arabella Software Ltd. - * Yuli Barcohen - * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2. - * Ported to PQ2FADS-ZU and PQ2FADS-VR boards. - * Ported to MPC8272ADS board. - * - * Copyright (c) 2005 MontaVista Software, Inc. - * Vitaly Bordug - * Added support for PCI bridge on MPC8272ADS - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */ - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* - * Figure out if we are booting low via flash HRCW or high via the BCSR. - */ -#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ -# define CFG_LOWBOOT 1 -#endif - -/* ADS flavours */ -#define CFG_8260ADS 1 /* MPC8260ADS */ -#define CFG_8266ADS 2 /* MPC8266ADS */ -#define CFG_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */ -#define CFG_8272ADS 4 /* MPC8272ADS */ - -#ifndef CONFIG_ADSTYPE -#define CONFIG_ADSTYPE CFG_8260ADS -#endif /* CONFIG_ADSTYPE */ - -#if CONFIG_ADSTYPE == CFG_8272ADS -#define CONFIG_MPC8272 1 -#else -#define CONFIG_MPC8260 1 -#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* allow serial and ethaddr to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ - -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ - -#if CONFIG_ETHER_INDEX == 1 - -# define CFG_PHY_ADDR 0 -# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) -# define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) - -#elif CONFIG_ETHER_INDEX == 2 - -#if CONFIG_ADSTYPE == CFG_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */ -# define CFG_PHY_ADDR 3 -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16) -#else /* RxCLK is CLK13, TxCLK is CLK14 */ -# define CFG_PHY_ADDR 0 -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ - -# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - -#endif /* CONFIG_ETHER_INDEX */ - -#define CFG_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */ -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ - -#if CONFIG_ADSTYPE == CFG_8272ADS -#define CFG_MDIO_PIN 0x00002000 /* PC18 */ -#define CFG_MDC_PIN 0x00001000 /* PC19 */ -#else -#define CFG_MDIO_PIN 0x00400000 /* PC9 */ -#define CFG_MDC_PIN 0x00200000 /* PC10 */ -#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ - -#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ - else iop->pdat &= ~CFG_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ - else iop->pdat &= ~CFG_MDC_PIN - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#if CONFIG_ADSTYPE >= CFG_PQ2FADS -#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */ -#else -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) -#define CONFIG_SPD_ADDR 0x50 -#endif -#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ - -/*PCI*/ -#ifdef CONFIG_MPC8272 -#define CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_PCI_BOOTDELAY 0 -#define CONFIG_PCI_SCAN_SHOW -#endif - -#ifndef CONFIG_SDRAM_PBI -#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ -#endif - -#ifndef CONFIG_8260_CLKIN -#if CONFIG_ADSTYPE >= CFG_PQ2FADS -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_KGDB | \ - CFG_CMD_MMC | \ - CFG_CMD_NAND | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_REISER | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_SNTP | \ - CFG_CMD_UNIVERSE | \ - CFG_CMD_USB | \ - CFG_CMD_VFD | \ - CFG_CMD_XIMG - -#if CONFIG_ADSTYPE == CFG_8272ADS -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_SDRAM | \ - CFG_CMD_I2C | \ - CFG_EXCLUDE ) ) -#elif CONFIG_ADSTYPE >= CFG_PQ2FADS -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_SDRAM | \ - CFG_CMD_I2C | \ - CFG_CMD_PCI | \ - CFG_EXCLUDE ) ) -#else -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CMD_CFG_PCI | \ - CFG_EXCLUDE ) ) -#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock2" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_FLASH_BASE 0xff800000 -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ -#define CFG_FLASH_SIZE 8 -#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -/* - * JFFS2 partitions - * - * Note: fake mtd_id used, no linux mtd map file - */ -#define MTDIDS_DEFAULT "nor0=mpc8260ads-0" -#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)" -#define CFG_JFFS2_SORT_FRAGMENTS - -/* this is stuff came out of the Motorola docs */ -#ifndef CFG_LOWBOOT -#define CFG_DEFAULT_IMMR 0x0F010000 -#endif - -#define CFG_IMMR 0xF0000000 -#define CFG_BCSR 0xF4500000 -#if CONFIG_ADSTYPE == CFG_8272ADS -#define CFG_PCI_INT 0xF8200000 -#endif -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_LSDRAM_BASE 0xFD000000 - -#define RS232EN_1 0x02000002 -#define RS232EN_2 0x01000001 -#define FETHIEN1 0x08000008 -#define FETH1_RST 0x04000004 -#define FETHIEN2 0x10000000 -#define FETH2_RST 0x08000000 -#define BCSR_PCI_MODE 0x01000000 - -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#ifdef CFG_LOWBOOT -/* PQ2FADS flash HRCW = 0x0EB4B645 */ -#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ - ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\ - ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\ - ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ - ) -#else -/* PQ2FADS BCSR HRCW = 0x0CB23645 */ -#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ - ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\ - ( HRCW_BMS | HRCW_APPC10 ) |\ - ( HRCW_MODCK_H0101 ) \ - ) -#endif -/* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#ifdef CONFIG_BZIP2 -#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#else -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -#ifndef CFG_RAMBOOT -# define CFG_ENV_IS_IN_FLASH 1 -# define CFG_ENV_SECT_SIZE 0x40000 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE) -#else -# define CFG_ENV_IS_IN_NVRAM 1 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) -# define CFG_ENV_SIZE 0x200 -#endif /* CFG_RAMBOOT */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) - -#define CFG_HID2 0 - -#define CFG_SYPCR 0xFFFFFFC3 -#define CFG_BCR 0x100C0000 -#define CFG_SIUMCR 0x0A200000 -#define CFG_SCCR SCCR_DFBRG01 -#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801 -#define CFG_OR0_PRELIM 0xFF800876 -#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801 -#define CFG_OR1_PRELIM 0xFFFF8010 - -/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/ - -#if CONFIG_ADSTYPE == CFG_8272ADS -#define CFG_BR3_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */ -#define CFG_OR3_PRELIM 0xFFFF8010 -#endif - -#define CFG_RMR RMR_CSRE -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CFG_RCCR 0 - -#if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS) -#undef CFG_LSDRAM_BASE /* No local bus SDRAM on these boards */ -#endif /* CONFIG_ADSTYPE == CFG_8266ADS */ - -#if CONFIG_ADSTYPE == CFG_PQ2FADS -#define CFG_OR2 0xFE002EC0 -#define CFG_PSDMR 0x824B36A3 -#define CFG_PSRT 0x13 -#define CFG_LSDMR 0x828737A3 -#define CFG_LSRT 0x13 -#define CFG_MPTPR 0x2800 -#elif CONFIG_ADSTYPE == CFG_8272ADS -#define CFG_OR2 0xFC002CC0 -#define CFG_PSDMR 0x834E24A3 -#define CFG_PSRT 0x13 -#define CFG_MPTPR 0x2800 -#else -#define CFG_OR2 0xFF000CA0 -#define CFG_PSDMR 0x016EB452 -#define CFG_PSRT 0x21 -#define CFG_LSDMR 0x0086A522 -#define CFG_LSRT 0x21 -#define CFG_MPTPR 0x1900 -#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ - -#define CFG_RESET_ADDRESS 0x04400000 - -#if CONFIG_ADSTYPE == CFG_8272ADS - -/* PCI Memory map (if different from default map */ -#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ -#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ -#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ - PICMR_PREFETCH_EN) - -/* - * These are the windows that allow the CPU to access PCI address space. - * All three PCI master windows, which allow the CPU to access PCI - * prefetch, non prefetch, and IO space (see below), must all fit within - * these windows. - */ - -/* - * Master window that allows the CPU to access PCI Memory (prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ -#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) - -/* - * Master window that allows the CPU to access PCI Memory (non-prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ -#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ -#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ -#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) - -/* - * Master window that allows the CPU to access PCI IO space. - * This window will be setup with the first set of Outbound ATU registers - * in the bridge. - */ - -#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ -#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ -#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ -#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) - - -/* PCIBR0 - for PCI IO*/ -#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */ -#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ -/* PCIBR1 - prefetch and non-prefetch regions joined together */ -#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL -#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U) - -#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/ - -#if CONFIG_ADSTYPE == CFG_8272ADS -#define CONFIG_HAS_ETH1 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h deleted file mode 100644 index 4953b70..0000000 --- a/include/configs/MPC8266ADS.h +++ /dev/null @@ -1,594 +0,0 @@ -/* - * (C) Copyright 2001 - * Stuart Hughes - * This file is based on similar values for other boards found in other - * U-Boot config files, and some that I found in the mpc8260ads manual. - * - * Note: my board is a PILOT rev. - * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm - */ - -/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - !! !! - !! This configuration requires JP3 to be in position 1-2 to work !! - !! To make it work for the default, the TEXT_BASE define in !! - !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !! - !! 0xfff00000 !! - !! The CFG_HRCW_MASTER define below must also be changed to match !! - !! !! - !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* allow serial and ethaddr to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#if (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Half duplex - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - -/* other options */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR_LEN 1 - -/* PCI */ -#define CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_PCI_BOOTDELAY 0 -#undef CONFIG_PCI_SCAN_SHOW - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 - - -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#define CONFIG_BAUDRATE 115200 - - -#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGDB | \ - CFG_CMD_MMC | \ - CFG_CMD_NAND | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_REISER | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_SNTP | \ - CFG_CMD_VFD | \ - CFG_CMD_UNIVERSE | \ - CFG_CMD_USB | \ - CFG_CMD_XIMG ) ) - -/* Define a command string that is automatically executed when no character - * is read on the console interface withing "Boot Delay" after reset. - */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ - -#ifdef CONFIG_BOOT_ROOT_INITRD -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_INITRD */ - -#ifdef CONFIG_BOOT_ROOT_NFS -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_NFS */ - -/* Add support for a few extra bootp options like: - * - File size - * - DNS - */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ - /* for versions < 2.4.5-pre5 */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_FLASH_BASE 0xFE000000 -#define FLASH_BASE 0xFE000000 -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ -#define CFG_FLASH_SIZE 8 -#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ - -#undef CFG_FLASH_CHECKSUM - -/* this is stuff came out of the Motorola docs */ -/* Only change this if you also change the Hardware configuration Word */ -#define CFG_DEFAULT_IMMR 0x0F010000 - -/* Set IMMR to 0xF0000000 or above to boot Linux */ -#define CFG_IMMR 0xF0000000 -#define CFG_BCSR 0xF8000000 -#define CFG_PCI_INT 0xF8200000 /* PCI interrupt controller */ - -/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes - */ -/*#define CONFIG_VERY_BIG_RAM 1*/ - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? This will normally auto-configure via the SPD. -*/ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 16 - -#define SDRAM_SPD_ADDR 0x50 - - -/*----------------------------------------------------------------------- - * BR2,BR3 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2,OR3 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* Bank 2,3 - SDRAM DIMM - */ - -/* The BR2 is configured as follows: - * - * - Base address of 0x00000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_BR3_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 64 MB DIMM, the OR2 is configured as follows: - * - * - 64 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CFG_SDRAM_SIZE == 64) -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) -#elif (CFG_SDRAM_SIZE == 16) -#define CFG_OR2_PRELIM (0xFF000C80) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ - -#if (CFG_SDRAM_SIZE == 64) -/* With a 64 MB DIMM, the PSDMR is configured as follows: - * - * - Bank Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A14-A16 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ -#define CFG_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#elif (CFG_SDRAM_SIZE == 16) -/* With a 16 MB DIMM, the PSDMR is configured as follows: - * - * configuration parameters found in Motorola documentation - */ -#define CFG_PSDMR (0x016EB452) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - - -#define RS232EN_1 0x02000002 -#define RS232EN_2 0x01000001 -#define FETHIEN 0x08000008 -#define FETH_RST 0x04000004 - -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */ -/* 0x0EB2B645 */ -#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\ - ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\ - ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\ - ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ - ) - -/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */ -/* #define CFG_HRCW_MASTER 0x0cb23645 */ - -/* This value should actually be situated in the first 256 bytes of the FLASH - which on the standard MPC8266ADS board is at address 0xFF800000 - The linker script places it at 0xFFF00000 instead. - - It still works, however, as long as the ADS board jumper JP3 is set to - position 2-3 so the board is using the BCSR as Hardware Configuration Word - - If you want to use the one defined here instead, ust copy the first 256 bytes from - 0xfff00000 to 0xff800000 (for 8MB flash) - - - Rune - -*/ - -/* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#ifndef CFG_RAMBOOT -# define CFG_ENV_IS_IN_FLASH 1 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -# define CFG_ENV_SECT_SIZE 0x40000 -#else -# define CFG_ENV_IS_IN_NVRAM 1 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) -# define CFG_ENV_SIZE 0x200 -#endif /* CFG_RAMBOOT */ - - -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -/*#define CFG_HID0_INIT 0 */ -#define CFG_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) - -#define CFG_HID2 0 - -#define CFG_SYPCR 0xFFFFFFC3 -#define CFG_BCR 0x004C0000 -#define CFG_SIUMCR 0x4E64C000 -#define CFG_SCCR 0x00000000 - -/* local bus memory map - * - * 0x00000000-0x03FFFFFF 64MB SDRAM - * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window - * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window - * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory - * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window - * 0xF8000000-0xF8007FFF 32KB BCSR - * 0xF8100000-0xF8107FFF 32KB ATM UNI - * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller - * 0xF8300000-0xF8307FFF 32KB EEPROM - * 0xFE000000-0xFFFFFFFF 32MB flash - */ -#define CFG_BR0_PRELIM 0xFE001801 /* flash */ -#define CFG_OR0_PRELIM 0xFE000836 -#define CFG_BR1_PRELIM (CFG_BCSR | 0x1801) /* BCSR */ -#define CFG_OR1_PRELIM 0xFFFF8010 -#define CFG_BR4_PRELIM 0xF8300801 /* EEPROM */ -#define CFG_OR4_PRELIM 0xFFFF8846 -#define CFG_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */ -#define CFG_OR5_PRELIM 0xFFFF8E36 -#define CFG_BR8_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */ -#define CFG_OR8_PRELIM 0xFFFF8010 - -#define CFG_RMR 0x0001 -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CFG_RCCR 0 -#define CFG_MPTPR 0x00001900 -#define CFG_PSRT 0x00000021 - -/* This address must not exist */ -#define CFG_RESET_ADDRESS 0xFCFFFF00 - -/* PCI Memory map (if different from default map */ -#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ -#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ -#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ - PICMR_PREFETCH_EN) - -/* - * These are the windows that allow the CPU to access PCI address space. - * All three PCI master windows, which allow the CPU to access PCI - * prefetch, non prefetch, and IO space (see below), must all fit within - * these windows. - */ - -/* PCIBR0 */ -#define CFG_PCI_MSTR0_LOCAL 0x80000000 /* Local base */ -#define CFG_PCIMSK0_MASK PCIMSK_1GB /* Size of window */ -/* PCIBR1 */ -#define CFG_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ -#define CFG_PCIMSK1_MASK PCIMSK_64MB /* Size of window */ - -/* - * Master window that allows the CPU to access PCI Memory (prefetch). - * This window will be setup with the first set of Outbound ATU registers - * in the bridge. - */ - -#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ -#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ -#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL -#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ -#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) - -/* - * Master window that allows the CPU to access PCI Memory (non-prefetch). - * This window will be setup with the second set of Outbound ATU registers - * in the bridge. - */ - -#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ -#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ -#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL -#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ -#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) - -/* - * Master window that allows the CPU to access PCI IO space. - * This window will be setup with the third set of Outbound ATU registers - * in the bridge. - */ - -#define CFG_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ -#define CFG_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */ -#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL -#define CFG_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ -#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h deleted file mode 100644 index d6d2fab..0000000 --- a/include/configs/MPC8349ADS.h +++ /dev/null @@ -1,584 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8349ads board configuration file - * - * Please refer to doc/README.mpc83xxads for more info. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG - -#define CONFIG_MII - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ -#define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */ - -/* FIXME: Real PCI support will come in a follow-up update. */ -#undef CONFIG_PCI - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ - -#define PCI_66M -#ifdef PCI_66M -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef PCI_66M -#define CONFIG_SYS_CLK_FREQ 66000000 -#else -#define CONFIG_SYS_CLK_FREQ 33000000 -#endif -#endif - -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ - -#define CFG_IMMRBAR 0xE0000000 - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00000000 /* memtest region */ -#define CFG_MEMTEST_END 0x00100000 - -/* - * DDR Setup - */ - -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#undef CONFIG_DDR_2T_TIMING -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ -#else - /* - * Manually set up DDR parameters - */ - #define CFG_DDR_SIZE 256 /* Mb */ - #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) - #define CFG_DDR_TIMING_1 0x37344321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ -#endif - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * FLASH on the Local Bus - */ -#define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 8 /* FLASH size in MB */ -/* #define CFG_FLASH_USE_BUFFER_WRITE */ - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ - BR_V) /* valid */ -#define CFG_OR0_PRELIM 0xff806ff7 /* 16Mb Flash size*/ -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */ - -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MID_FLASH_JUMP 0x7F000000 -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -/* - * BCSR register on local bus 32KB, 8-bit wide for ADS config reg - */ -#define CFG_BCSR 0xF8000000 -#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ -#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ -#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ -#define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ - -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) -#define CFG_LBC_LBCR 0x00000000 - -#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CFG_LB_SDRAM -/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/ -#define CFG_LBLAWBAR2_PRELIM 0xF0000000 -#define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/ - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ - | CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR8 \ - | CFG_LBC_LSDMR_PRETOACT6 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC3 \ - | CFG_LBC_LSDMR_CL3 \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) -#endif - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 -#define CFG_I2C2_OFFSET 0x3100 - -/* TSEC */ -#define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) -#define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) - -/* IO Configuration */ -#define CFG_IO_CONF (\ - IO_CONF_UART |\ - IO_CONF_TSEC1 |\ - IO_CONF_IRQ0 |\ - IO_CONF_IRQ1 |\ - IO_CONF_IRQ2 |\ - IO_CONF_IRQ3 |\ - IO_CONF_IRQ4 |\ - IO_CONF_IRQ5 |\ - IO_CONF_IRQ6 |\ - IO_CONF_IRQ7 ) - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#define CFG_PCI2_MEM_BASE 0xA0000000 -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe3000000 -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ -#if defined(CONFIG_PCI) - -#define PCI_ALL_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#endif -#else -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII \ - ) -#endif -#endif - -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -#define CFG_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(PCI_64BIT) -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#else -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#endif - -#define CFG_HID0_INIT 0x000000000 - -#define CFG_HID0_FINAL CFG_HID0_INIT - -/* #define CFG_HID0_FINAL (\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_ENABLE_M_BIT |\ - HID0_ENABLE_ADDRESS_BROADCAST ) */ - -#define CFG_HID2 0x000000000 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:04:9f:11:22:33 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=ramfs.83xx\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h deleted file mode 100644 index 131c832..0000000 --- a/include/configs/MPC8540ADS.h +++ /dev/null @@ -1,520 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8540ads board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8540 1 /* MPC8540 specific */ -#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ - -#ifndef CONFIG_HAS_FEC -#define CONFIG_HAS_FEC 1 /* 8540 has FEC */ -#endif - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 -#endif - - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ - #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ - #define CFG_DDR_CS0_CONFIG 0x80000002 - #define CFG_DDR_TIMING_1 0x37344321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ -#endif - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ - -#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR5 \ - | CFG_LBC_LSDMR_PRETOACT3 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC2 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) - - -/* - * 32KB, 8-bit wide for ADS config reg - */ -#define CFG_BR4_PRELIM 0xf8000801 -#define CFG_OR4_PRELIM 0xffffe1f1 -#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - - -#if CONFIG_HAS_FEC -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#define FEC_PHY_ADDR 3 -#define FEC_PHYIDX 0 -#endif - -/* Options are: TSEC[0-1], FEC */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif -#endif - -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h deleted file mode 100644 index 1af9231..0000000 --- a/include/configs/MPC8540EVAL.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Modified by Lunsheng Wang, lunsheng@sohu.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* mpc8540eval board configuration file */ -/* please refer to doc/README.mpc85xxads for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8540 1 /* MPC8540 specific */ -#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */ - -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. - * Not availabe for EVAL board - */ -#undef CONFIG_RAM_AS_FLASH - -/* sysclk for MPC8540EVAL */ -#if defined(CONFIG_SYSCLK_66M) - /* - * the oscillator on board is 66Mhz - * can also get 66M clock from external PCI - */ - #define CONFIG_SYS_CLK_FREQ 66000000 -#else - #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00400000 - -#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) -#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both." -#endif - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CFG_SDRAM_SIZE 256 /* DDR is now 256MB */ - -#if defined(CONFIG_RAM_AS_FLASH) -#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ -#else -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#endif -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */ - -#if defined(CONFIG_RAM_AS_FLASH) -#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ -#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */ -#else /* Boot from real Flash */ -#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ -#define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */ -#endif - -#define CFG_OR0_PRELIM 0xff806f67 /* 8MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/ -#define CFG_FLASH_CFI 1 - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -/* Here some DDR setting should be added */ - - -#undef CONFIG_CLOCKS_IN_MHZ - -/* local bus definitions */ -#define CFG_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 - -#if defined(CONFIG_RAM_AS_FLASH) -#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ -#else -#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ -#endif -#define CFG_OR4_PRELIM 0xffffe1f1 -#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/* General PCI */ -#define CFG_PCI_MEM_BASE 0x80000000 -#define CFG_PCI_MEM_PHYS 0x80000000 -#define CFG_PCI_MEM_SIZE 0x20000000 -#define CFG_PCI_IO_BASE 0xe2000000 - -#if defined(CONFIG_PCI) -#define CONFIG_NET_MULTI -#undef CONFIG_EEPRO100 -#define CONFIG_TULIP -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#if !defined(CONFIG_PCI_PNP) -#define PCI_ENET0_IOADDR 0xe0000000 -#define PCI_ENET0_MEMADDR 0xe0000000 -#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0008 -#elif defined(CONFIG_TSEC_ENET) -#define CONFIG_NET_MULTI 1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#define TSEC1_PHY_ADDR 7 -#define TSEC2_PHY_ADDR 4 -#define FEC_PHY_ADDR 2 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 -/* Options are: TSEC[0-1], FEC */ -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ -#define INTEL_LXT971_PHY 1 -#endif - -#undef DEBUG - -/* Environment */ -#ifndef CFG_RAMBOOT -#if defined(CONFIG_RAM_AS_FLASH) -#define CFG_ENV_IS_NOWHERE -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) -#define CFG_ENV_SIZE 0x2000 -#else -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#endif -#define CFG_ENV_SIZE 0x2000 -#else -/* #define CFG_NO_FLASH 1 */ /* Flash is not usable now */ -#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) -#define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \ - | CFG_CMD_PCI | CFG_CMD_I2C ) & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS )) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \ - | CFG_CMD_I2C ) & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS )) -#endif -#else -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ - | CFG_CMD_PING | CFG_CMD_I2C ) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) -#endif -#endif - -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*****************************/ -/* Environment Configuration */ -/*****************************/ -/* The mac addresses for all ethernet interface */ -/* NOTE: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:01:af:07:9b:8a -#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b -#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c -#endif - -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.101.1 -#define CONFIG_IPADDR 192.168.101.11 -#define CONFIG_GATEWAYIP 192.168.101.0 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_HOSTNAME MPC8540EVAL - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h deleted file mode 100644 index c96b98b..0000000 --- a/include/configs/MPC8541CDS.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8541cds board configuration file - * - * Please refer to doc/README.mpc85xxcds for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8541 1 /* MPC8541 specific */ -#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - - -/* - * When initializing flash, if we cannot find the manufacturer ID, - * assume this is the AMD flash associated with the CDS board. - * This allows booting from a promjet. - */ -#define CONFIG_ASSUME_AMD_FLASH - -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -/* - * Make sure required options are set - */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ - -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ - -#define CFG_BR0_PRELIM 0xff801001 -#define CFG_BR1_PRELIM 0xff001001 - -#define CFG_OR0_PRELIM 0xff806e65 -#define CFG_OR1_PRELIM 0xff806e65 - -#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ - | CFG_LBC_LSDMR_PRETOACT7 \ - | CFG_LBC_LSDMR_ACTTORW7 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC4 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * The CADMUS registers are connected to CS3 on CDS. - * The new memory map places CADMUS at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ - -#define CADMUS_BASE_ADDR 0xf8000000 -#define CFG_BR3_PRELIM 0xf8000801 -#define CFG_OR3_PRELIM 0xfff00ff7 - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#define CFG_PCI2_MEM_BASE 0xa0000000 -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ - - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CFG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#endif -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h deleted file mode 100644 index 4ca8bc3..0000000 --- a/include/configs/MPC8548CDS.h +++ /dev/null @@ -1,521 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8548cds board configuration file - * - * Please refer to doc/README.mpc85xxcds for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ -#define CONFIG_MPC8548 1 /* MPC8548 specific */ -#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ - -#undef CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - - -/* - * When initializing flash, if we cannot find the manufacturer ID, - * assume this is the AMD flash associated with the CDS board. - * This allows booting from a promjet. - */ -#define CONFIG_ASSUME_AMD_FLASH - -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -/* - * Make sure required options are set - */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ - -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ - -#define CFG_BR0_PRELIM 0xff801001 -#define CFG_BR1_PRELIM 0xff001001 - -#define CFG_OR0_PRELIM 0xff806e65 -#define CFG_OR1_PRELIM 0xff806e65 - -#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ - | CFG_LBC_LSDMR_PRETOACT7 \ - | CFG_LBC_LSDMR_ACTTORW7 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC4 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * The CADMUS registers are connected to CS3 on CDS. - * The new memory map places CADMUS at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ - -#define CADMUS_BASE_ADDR 0xf8000000 -#define CFG_BR3_PRELIM 0xf8000801 -#define CFG_OR3_PRELIM 0xfff00ff7 - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#define CFG_PCI2_MEM_BASE 0xa0000000 -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ - - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" -#define CONFIG_MPC85XX_TSEC3 1 -#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#define CONFIG_MPC85XX_TSEC4 1 -#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" -#undef CONFIG_MPC85XX_FEC - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC3_PHY_ADDR 2 -#define TSEC4_PHY_ADDR 3 -#define FEC_PHY_ADDR 3 - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 -#define FEC_PHYIDX 0 - -/* Options are: eTSEC[0-3] */ -#define CONFIG_ETHPRIME "eTSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CFG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#endif -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h deleted file mode 100644 index a44e3ec..0000000 --- a/include/configs/MPC8555CDS.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8555cds board configuration file - * - * Please refer to doc/README.mpc85xxcds for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8555 1 /* MPC8555 specific */ -#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - - -/* - * When initializing flash, if we cannot find the manufacturer ID, - * assume this is the AMD flash associated with the CDS board. - * This allows booting from a promjet. - */ -#define CONFIG_ASSUME_AMD_FLASH - -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -/* - * Make sure required options are set - */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ - -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ - -#define CFG_BR0_PRELIM 0xff801001 -#define CFG_BR1_PRELIM 0xff001001 - -#define CFG_OR0_PRELIM 0xff806e65 -#define CFG_OR1_PRELIM 0xff806e65 - -#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ - | CFG_LBC_LSDMR_PRETOACT7 \ - | CFG_LBC_LSDMR_ACTTORW7 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC4 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * The CADMUS registers are connected to CS3 on CDS. - * The new memory map places CADMUS at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ - -#define CADMUS_BASE_ADDR 0xf8000000 -#define CFG_BR3_PRELIM 0xf8000801 -#define CFG_OR3_PRELIM 0xfff00ff7 - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#define CFG_PCI2_MEM_BASE 0xa0000000 -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ - - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CFG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#endif -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h deleted file mode 100644 index 2d5031b..0000000 --- a/include/configs/MPC8560ADS.h +++ /dev/null @@ -1,561 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8560ads board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 -#endif - - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ - #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ - #define CFG_DDR_CS0_CONFIG 0x80000002 - #define CFG_DDR_TIMING_1 0x37344321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ -#endif - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ - -#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR5 \ - | CFG_LBC_LSDMR_PRETOACT3 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC2 \ - | CFG_LBC_LSDMR_CL3 \ - | CFG_LBC_LSDMR_RFEN \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) - - -/* - * 32KB, 8-bit wide for ADS config reg - */ -#define CFG_BR4_PRELIM 0xf8000801 -#define CFG_OR4_PRELIM 0xffffe1f1 -#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#endif - - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & ~(CFG_CMD_ENV)) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif -#endif - -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h deleted file mode 100644 index 565f9bb..0000000 --- a/include/configs/MPC86xADS.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola MPC8xxADS board. Copied from the FADS config. - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * Values common to all FADS family boards are in board/fads/fads.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* board type */ -#define CONFIG_MPC86xADS 1 /* new ADS */ -#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ - -/* New MPC86xADS - pick one of these */ -#define CONFIG_MPC866T 1 -#undef CONFIG_MPC866P -#undef CONFIG_MPC859T -#undef CONFIG_MPC859DSL -#undef CONFIG_MPC852T - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ 1 - -#include "fads.h" - -#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h deleted file mode 100644 index 74318e5..0000000 --- a/include/configs/MPC885ADS.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * A collection of structures, addresses, and values associated with - * the Motorola DUET ADS board. Values common to all FADS family boards - * are in board/fads/fads.h - * - * Copyright (C) 2003 Arabella Software Ltd. - * Yuli Barcohen - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Board type */ -#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */ -#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ - -#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ - -#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) - -#define CONFIG_SDRAM_50MHZ 1 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -#include "fads.h" - -#undef CFG_SCCR -#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11) - -#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) - -#define CONFIG_HAS_ETH1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h deleted file mode 100644 index da52e0e..0000000 --- a/include/configs/MUSENKI.h +++ /dev/null @@ -1,295 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the MUSENKI board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_MUSENKI 1 - - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ - -#include - - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) -#define CFG_MAXARGS 8 /* Max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_TULIP - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -#define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ -#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ -#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM - -/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the - * reset vector is actually located at FFB00100, but the 8245 - * takes care of us. - */ -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_EUMB_ADDR 0xFC000000 - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CFG_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */ - - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#undef CFG_RAMBOOT -#else -#define CFG_RAMBOOT -#endif - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* #define CFG_MONITOR_BASE TEXT_BASE */ -/*#define CFG_GBL_DATA_SIZE 256*/ -#define CFG_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CFG_HZ 1000 - - /* Bit-field values for MCCR1. - */ -#define CFG_ROMNAL 7 -#define CFG_ROMFAL 11 -#define CFG_DBUS_SIZE 0x3 - - /* Bit-field values for MCCR2. - */ -#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CFG_BSTOPRE 121 - - /* Bit-field values for MCCR3. - */ -#define CFG_REFREC 8 /* Refresh to activate interval */ - - /* Bit-field values for MCCR4. - */ -#define CFG_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ -#define CFG_ACTORW 3 /* FIXME was 2 */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 1 -#define CFG_REGDIMM 0 - -#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ - -#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff -#define CFG_BANK7_ENABLE 0 - -#define CFG_ODCR 0xff - -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0xFFFF0000 -#define CFG_ENV_SIZE 0x00010000 /* Size of the Environment */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h deleted file mode 100644 index 88eefa1..0000000 --- a/include/configs/MVBLUE.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define MV_VERSION "v0.2.0" - -/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */ -#define ERR_NONE 0 -#define ERR_ENV 1 -#define ERR_BOOTM_BADMAGIC 2 -#define ERR_BOOTM_BADCRC 3 -#define ERR_BOOTM_GUNZIP 4 -#define ERR_BOOTP_TIMEOUT 5 -#define ERR_DHCP 6 -#define ERR_TFTP 7 -#define ERR_NOLAN 8 -#define ERR_LANDRV 9 - -#define CONFIG_BOARD_TYPES 1 -#define MVBLUE_BOARD_BOX 1 -#define MVBLUE_BOARD_LYNX 2 - -#if 0 -#define ERR_LED(code) do { if (code) \ - *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \ - else \ - *(volatile char *)(0xff000003) = ( 1 ); \ - } while(0) -#else -#define ERR_LED(code) -#endif - -#undef DEBUG - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_MVBLUE 1 - -#define CONFIG_CLOCKS_IN_MHZ 1 - -#define CONFIG_BOARD_TYPES 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOT_RETRY_TIME -1 - -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 's')...\n" -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 60 - -#define CONFIG_COMMANDS ( CFG_CMD_ASKENV | CFG_CMD_BOOTD | CFG_CMD_CACHE | CFG_CMD_DHCP | \ - CFG_CMD_ECHO | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IMI | \ - CFG_CMD_IRQ | CFG_CMD_NET | CFG_CMD_PCI | CFG_CMD_RUN ) - - -#define CONFIG_BOOTP_MASK ( 0xffffffff ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) -#define CFG_MAXARGS 16 /* Max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ - -#define CONFIG_BOOTCOMMAND "run nfsboot" -#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2" - -#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "dhcp_client_id=mvBOX-XP\0" \ - "dhcp_vendor-class-identifier=mvBOX\0" \ - "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \ - "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \ - "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \ - "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ - "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \ - "mv_version=" MV_VERSION "\0" \ - "bootretry=30\0" - -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW - -#define CONFIG_NET_MULTI -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_TULIP -#define CONFIG_TULIP_FIX_DAVICOM 1 -#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0 - -#define CONFIG_HW_WATCHDOG - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -#define CFG_FLASH_BASE 0xFFF00000 -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_RESET_ADDRESS 0xFFF00100 -#define CFG_EUMB_ADDR 0xFC000000 - -#define CFG_MONITOR_LEN 0x00100000 -#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ - -/* Maximum amount of RAM. */ -#define CFG_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */ - - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#undef CFG_RAMBOOT -#else -#define CFG_RAMBOOT -#endif - -#define CFG_ISA_IO 0xFE000000 - -/* - * serial configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 -#define CFG_HZ 10000 - -/* Bit-field values for MCCR1. */ -#define CFG_ROMNAL 7 -#define CFG_ROMFAL 11 - -/* Bit-field values for MCCR2. */ -#define CFG_TSWAIT 0x5 -#define CFG_REFINT 430 - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#define CFG_BSTOPRE 121 - -/* Bit-field values for MCCR3. */ -#define CFG_REFREC 8 - -/* Bit-field values for MCCR4. */ -#define CFG_PRETOACT 3 -#define CFG_ACTTOPRE 5 -#define CFG_ACTORW 3 -#define CFG_SDMODE_CAS_LAT 3 -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 1 -#define CFG_REGDIMM 0 -#define CFG_DBUS_SIZE2 1 -#define CFG_SDMODE_WRAP 0 - -#define CFG_PGMAX 0x32 -#define CFG_SDRAM_DSCD 0x20 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff -#define CFG_BANK7_ENABLE 0 - -#define CFG_ODCR 0xff - -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#undef CFG_FLASH_PROTECTION -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 63 /* Max number of sectors per flash */ - -#define CFG_FLASH_ERASE_TOUT 12000 -#define CFG_FLASH_WRITE_TOUT 1000 - - -#define CFG_ENV_IS_IN_FLASH - -#define CFG_ENV_OFFSET 0x00010000 -#define CFG_ENV_SIZE 0x00010000 -#define CFG_ENV_SECT_SIZE 0x00010000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h deleted file mode 100644 index 5995918..0000000 --- a/include/configs/MVS1.h +++ /dev/null @@ -1,406 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_MVS 1 /* ...on a MVsensor module */ -#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */ -#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */ -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */ - -#define CONFIG_PREBOOT "echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use \"run bootflash\";echo" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG /* watchdog disabled/enabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_VENDOREX ) - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* MVsensor uses a really minimal U-Boot ! */ -#define CONFIG_COMMANDS (CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_IMI | \ - CFG_CMD_FLASH | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_DHCP | \ - CFG_CMD_ENV | \ - CFG_CMD_BOOTD | \ - CFG_CMD_RUN ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* Hush parse for U-Boot ?? */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 - -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */ - -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 - -/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */ -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */ -#define CFG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 0 /* max. no. of IDE buses */ -#define CFG_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */ - - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#undef FLASH_BASE1_PRELIM - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - - -/* - * FLASH timing: - */ -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -/* -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) -*/ - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#ifdef CONFIG_MVS_16BIT_FLASH -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) -#else -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) -#endif - -#undef CFG_OR1_REMAP -#undef CFG_OR1_PRELIM -#undef CFG_BR1_PRELIM -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#undef SDRAM_BASE3_PRELIM -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#undef CFG_OR3_PRELIM -#undef CFG_BR3_PRELIM - - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ -#define CFG_MAMR_PTA 98 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/NC650.h b/include/configs/NC650.h deleted file mode 100644 index 371ea17..0000000 --- a/include/configs/NC650.h +++ /dev/null @@ -1,424 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC852T 1 -#define CONFIG_NC650 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -/* - * 10 MHz - PLL input clock - */ -#define CONFIG_8xx_OSCLK 10000000 - -/* - * 50 MHz - default CPU clock - */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 - -/* - * 15 MHz - CPU minimum clock - */ -#define CFG_8xx_CPUCLK_MIN 15000000 - -/* - * 133 MHz - CPU maximum clock - */ -#define CFG_8xx_CPUCLK_MAX 133000000 - -#define CFG_MEASURE_CPUCLK -#define CFG_8XX_XIN CONFIG_8xx_OSCLK - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define FEC_ENET -#define CONFIG_MII -#define CFG_DISCOVER_PHY 1 - - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7f - -/* - * Software (bit-bang) I2C driver configuration - */ -#define SCL 0x1000 /* PA 3 */ -#define SDA 0x2000 /* PA 2 */ - -#define __I2C_DIR immr->im_ioport.iop_padir -#define __I2C_DAT immr->im_ioport.iop_padat -#define __I2C_PAR immr->im_ioport.iop_papar -#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ - __I2C_DIR |= (SDA|SCL); } -#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) -#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } -#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } -#define I2C_DELAY { udelay(5); } -#define I2C_ACTIVE { __I2C_DIR |= SDA; } -#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } - -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_NAND | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00740000 - -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ -#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/* - * NAND flash support - */ -#define CFG_MAX_NAND_DEVICE 1 -#define NAND_ChipID_UNKNOWN 0x00 -#define SECTORSIZE 512 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define ADDR_COLUMN 1 -#define NAND_NO_RB - -#define NAND_WAIT_READY(nand) udelay(12) -#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND(d, adr + 2) -#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND(d, adr + 1) -#define WRITE_NAND(d, adr) (*(volatile uint8_t *)(adr) = (uint8_t)(d)) -#define READ_NAND(adr) (*(volatile uint8_t *)(adr)) -#define NAND_DISABLE_CE(nand) /* nop */ -#define NAND_ENABLE_CE(nand) /* nop */ -#define NAND_CTL_CLRALE(nandptr) /* nop */ -#define NAND_CTL_SETALE(nandptr) /* nop */ -#define NAND_CTL_CLRCLE(nandptr) /* nop */ -#define NAND_CTL_SETCLE(nandptr) /* nop */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 | SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: Default value of OR0 after reset */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V) - -/* - * BR2 and OR2 (NAND Flash) - now addressed through UPMB - */ -#define CFG_NAND_BASE 0x50000000 -#define CFG_NAND_SIZE 0x04000000 - -#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - OR_SCY_15_CLK | OR_EHTR | OR_TRLX) - -#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V ) -#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI ) - -/* - * BR3 and OR3 (SDRAM) - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - - /* - * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) - -/* - * BR5 and OR5 (SRAM) - */ -#define CFG_SRAM_BASE 0x60000000 -#define CFG_SRAM_SIZE 0x00080000 - -#define CFG_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - OR_SCY_15_CLK | OR_EHTR | OR_TRLX) - -#define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM) - - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 39 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * MBMR settings for NAND flash - */ - -#define CFG_MBMR_NAND ( MBMR_WLFB_5X ) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00400000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand" - -#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \ - "2560k(cramfs1),2560k(cramfs2)," \ - "256k(u-boot),256k(env);" \ - "nc650-nand:4m(nand1),28m(nand2)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h deleted file mode 100644 index bf4c899..0000000 --- a/include/configs/NETPHONE.h +++ /dev/null @@ -1,811 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2 -#error Unsupported CONFIG_NETPHONE version -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC870 1 /* This is a MPC885 CPU */ -#define CONFIG_NETPHONE 1 /* ...on a NetPhone board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -/* #define CONFIG_XIN 10000000 */ -#define CONFIG_XIN 50000000 -/* #define MPC8XX_HZ 120000000 */ -#define MPC8XX_HZ 66666666 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_AUTOSCRIPT -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ -#define FEC_ENET 1 /* eth.c needs it that way... */ -#undef CFG_DISCOVER_PHY -#define CONFIG_MII 1 -#define CONFIG_RMII 1 /* use RMII interface */ - -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ -#define CONFIG_FEC1_PHY_NORXERR 1 - -#define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 4 -#define CONFIG_FEC2_PHY_NORXERR 1 - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_NAND | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_MII | \ - CFG_CMD_CDP \ - ) - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#if CONFIG_NETPHONE_VERSION == 2 -#define CFG_FLASH_BASE4 0x40080000 -#endif - -#define CFG_RESET_ADDRESS 0x80000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#if CONFIG_NETPHONE_VERSION == 1 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#elif CONFIG_NETPHONE_VERSION == 2 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#endif -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x10000 - -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 0x4000 - -#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) -#define CFG_ENV_OFFSET_REDUND 0 -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -#if CONFIG_XIN == 10000000 - -#if MPC8XX_HZ == 120000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 50000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 25000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 40000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 75000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 10MHz -#endif - -#elif CONFIG_XIN == 50000000 - -#if MPC8XX_HZ == 120000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 66666666 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 50MHz -#endif - -#else - -#error unsupported XIN freq -#endif - - -/* - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: When TBS == 0 the timebase is independent of current cpu clock. - */ - -#define SCCR_MASK SCCR_EBDF11 -#if MPC8XX_HZ > 66666666 -#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) -#else -#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -#if CONFIG_NETPHONE_VERSION == 2 - -#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ - -#define CFG_OR4_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR4_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -#endif - -/* - * BR3 and OR3 (SDRAM) - * - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_MAMR_PTA 234 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_ARTOS /* include ARTOS support */ - -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ - -/****************************************************************/ - -#define DSP_SIZE 0x00010000 /* 64K */ -#define NAND_SIZE 0x00010000 /* 64K */ - -#define DSP_BASE 0xF1000000 -#define NAND_BASE 0xF1010000 - -/****************************************************************/ - -/* NAND */ -#define CFG_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_ECC_JFFS2 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_MTD_NAND_UNSAFE - -#define CFG_MAX_NAND_DEVICE 1 - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \ - } while(0) - -#if CONFIG_NETPHONE_VERSION == 1 -#define NAND_WAIT_READY(nand) \ - do { \ - int _tries = 0; \ - while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \ - if (++_tries > 100000) \ - break; \ - } while (0) -#elif CONFIG_NETPHONE_VERSION == 2 -#define NAND_WAIT_READY(nand) \ - do { \ - int _tries = 0; \ - while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \ - if (++_tries > 100000) \ - break; \ - } while (0) -#endif - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - -/*****************************************************************************/ - -#define CFG_DIRECT_FLASH_TFTP -#define CFG_DIRECT_NAND_TFTP - -/*****************************************************************************/ - -#if CONFIG_NETPHONE_VERSION == 1 -#define STATUS_LED_BIT 0x00000008 /* bit 28 */ -#elif CONFIG_NETPHONE_VERSION == 2 -#define STATUS_LED_BIT 0x00000080 /* bit 24 */ -#endif - -#define STATUS_LED_PERIOD (CFG_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifndef __ASSEMBLY__ - -/* LEDs */ - -/* led_id_t is unsigned int mask */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \ - else \ - ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ - } while(0) - -#define __led_init(msk, st) __led_set(msk, st) - -#endif - -/*********************************************************************************************************** - - ---------------------------------------------------------------------------------------------- - - (V1) version 1 of the board - (V2) version 2 of the board - - ---------------------------------------------------------------------------------------------- - - Pin definitions: - - +------+----------------+--------+------------------------------------------------------------ - | # | Name | Type | Comment - +------+----------------+--------+------------------------------------------------------------ - | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select - | PA7 | DSP_INT | Output | DSP interrupt - | PA10 | DSP_RESET | Output | DSP reset - | PA14 | USBOE | Output | USB (1) - | PA15 | USBRXD | Output | USB (1) - | PB19 | BT_RTS | Output | Bluetooth (0) - | PB23 | BT_CTS | Output | Bluetooth (0) - | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select - | PB27 | SPICS_DISP | Output | Display chip select - | PB28 | SPI_RXD_3V | Input | SPI Data Rx - | PB29 | SPI_TXD | Output | SPI Data Tx - | PB30 | SPI_CLK | Output | SPI Clock - | PC10 | DISPA0 | Output | Display A0 - | PC11 | BACKLIGHT | Output | Display backlit - | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD - | | IO_RESET | Output | (V2) General I/O reset - | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) - | | HOOK | Input | (V2) Hook input interrupt - | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK - | | F_RY_BY | Input | (V2) NAND F_RY_BY - | PE17 | F_ALE | Output | NAND F_ALE - | PE18 | F_CLE | Output | NAND F_CLE - | PE20 | F_CE | Output | NAND F_CE - | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select - | | LED | Output | (V2) LED - | PE27 | SPICS_ER | Output | External serial register CS - | PE28 | LEDIO1 | Output | (V1) LED - | | BKBR1 | Input | (V2) Keyboard input scan - | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) - | | BKBR2 | Input | (V2) Keyboard input scan - | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) - | | BKBR3 | Input | (V2) Keyboard input scan - | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY - | | BKBR4 | Input | (V2) Keyboard input scan - +------+----------------+--------+--------------------------------------------------- - - ---------------------------------------------------------------------------------------------- - - Serial register input: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | 0 | BKBR1 | (V1) Keyboard input scan - | 1 | BKBR3 | (V1) Keyboard input scan - | 2 | BKBR4 | (V1) Keyboard input scan - | 3 | BKBR2 | (V1) Keyboard input scan - | 4 | HOOK | (V1) Hook switch - | 5 | BT_LINK | (V1) Bluetooth link status - | 6 | HOST_WAKE | (V1) Bluetooth host wake up - | 7 | OK_ETH | (V1) Cisco inline power OK status - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Serial register output: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | 0 | KEY1 | Keyboard output scan - | 1 | KEY2 | Keyboard output scan - | 2 | KEY3 | Keyboard output scan - | 3 | KEY4 | Keyboard output scan - | 4 | KEY5 | Keyboard output scan - | 5 | KEY6 | Keyboard output scan - | 6 | KEY7 | Keyboard output scan - | 7 | BT_WAKE | Bluetooth wake up - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Chip selects: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | CS0 | CS0 | Boot flash - | CS1 | CS_FLASH | NAND flash - | CS2 | CS_DSP | DSP - | CS3 | DCS_DRAM | DRAM - | CS4 | CS_FLASH2 | (V2) 2nd flash - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Interrupts: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | IRQ1 | IRQ_DSP | DSP interrupt - | IRQ3 | S_INTER | DUSLIC ??? - | IRQ4 | F_RY_BY | NAND - | IRQ7 | IRQ_MAX | MAX 3100 interrupt - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Interrupts on PCMCIA pins: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface - | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface - | IP_A2| RMII1_MDINT | PHY interrupt for #1 - | IP_A3| RMII2_MDINT | PHY interrupt for #2 - | IP_A5| HOST_WAKE | (V2) Bluetooth host wake - | IP_A6| OK_ETH | (V2) Cisco inline power OK - +------+----------------+------------------------------------------------------------ - -*************************************************************************************************/ - -#define CONFIG_SED156X 1 /* use SED156X */ -#define CONFIG_SED156X_PG12864Q 1 /* type of display used */ - -/* serial interfacing macros */ - -#define SED156X_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define SED156X_SPI_RXD_MASK 0x00000008 - -#define SED156X_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define SED156X_SPI_TXD_MASK 0x00000004 - -#define SED156X_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define SED156X_SPI_CLK_MASK 0x00000002 - -#define SED156X_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define SED156X_CS_MASK 0x00000010 - -#define SED156X_A0_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) -#define SED156X_A0_MASK 0x0020 - -/*************************************************************************************************/ - -#define CFG_CONSOLE_IS_IN_ENV 1 -#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 -#define CFG_CONSOLE_ENV_OVERWRITE 1 - -/*************************************************************************************************/ - -/* use board specific hardware */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_SHOW_ACTIVITY - -/*************************************************************************************************/ - -/* phone console configuration */ - -#define PHONE_CONSOLE_POLL_HZ (CFG_HZ/200) /* poll every 5ms */ - -/*************************************************************************************************/ - -#define CONFIG_CDP_DEVICE_ID 20 -#define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */ -#define CONFIG_CDP_PORT_ID "eth%d" -#define CONFIG_CDP_CAPABILITIES 0x00000010 -#define CONFIG_CDP_VERSION "u-boot" " " __DATE__ " " __TIME__ -#define CONFIG_CDP_PLATFORM "Intracom NetPhone" -#define CONFIG_CDP_TRIGGER 0x20020001 -#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ -#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */ - -/*************************************************************************************************/ - -#define CONFIG_AUTO_COMPLETE 1 - -/*************************************************************************************************/ - -#define CONFIG_CRC32_VERIFY 1 - -/*************************************************************************************************/ - -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 - -/*************************************************************************************************/ -#endif /* __CONFIG_H */ diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h deleted file mode 100644 index 1bcd88d..0000000 --- a/include/configs/NETTA.h +++ /dev/null @@ -1,787 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ -#define CONFIG_NETTA 1 /* ...on a NetTA board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -/* #define CONFIG_XIN 10000000 */ -#define CONFIG_XIN 50000000 -#define MPC8XX_HZ 120000000 -/* #define MPC8XX_HZ 100000000 */ -/* #define MPC8XX_HZ 50000000 */ -/* #define MPC8XX_HZ 80000000 */ - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ -#define FEC_ENET 1 /* eth.c needs it that way... */ -#undef CFG_DISCOVER_PHY /* do not discover phys */ -#define CONFIG_MII 1 -#define CONFIG_RMII 1 /* use RMII interface */ - -#if defined(CONFIG_NETTA_ISDN) -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ -#define CONFIG_FEC1_PHY_NORXERR 1 -#undef CONFIG_ETHER_ON_FEC2 -#else -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ -#define CONFIG_FEC1_PHY_NORXERR 1 -#define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ -#define CONFIG_FEC2_PHY_NORXERR 1 -#endif - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -/* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CODEC | \ - CFG_POST_DSP ) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_CDP | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_FAT | \ - CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_PING | \ - 0) - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x10000 - -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 0x4000 - -#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) -#define CFG_ENV_OFFSET_REDUND 0 -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -#if CONFIG_XIN == 10000000 - -#if MPC8XX_HZ == 120000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 50000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 25000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 40000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 75000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 10MHz -#endif - -#elif CONFIG_XIN == 50000000 - -#if MPC8XX_HZ == 120000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 80000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 50000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 50MHz -#endif - -#else - -#error unsupported XIN freq -#endif - - -/* - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: When TBS == 0 the timebase is independent of current cpu clock. - */ - -#define SCCR_MASK SCCR_EBDF11 -#if MPC8XX_HZ > 66666666 -#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) -#else -#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR3 and OR3 (SDRAM) - * - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#if MPC8XX_HZ == 120000000 -#define CFG_MAMR_PTA 234 -#elif MPC8XX_HZ == 100000000 -#define CFG_MAMR_PTA 195 -#elif MPC8XX_HZ == 80000000 -#define CFG_MAMR_PTA 156 -#elif MPC8XX_HZ == 50000000 -#define CFG_MAMR_PTA 98 -#else -#error Unknown frequency -#endif - - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_ARTOS /* include ARTOS support */ - -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ - -/*********************************************************************************************************** - - Pin definitions: - - +------+----------------+--------+------------------------------------------------------------ - | # | Name | Type | Comment - +------+----------------+--------+------------------------------------------------------------ - | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK - | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK) - | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA - | PA7 | DCL1_3V | Periph | IDL1 PCM clock - | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx - | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx - | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA - | PA12 | P_SHDN | Output | TPS2211A PCMCIA - | PA13 | ETH_LOOP | Output | CISCO Loopback remote power - | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL) - | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA - | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA - | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board - | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only) - | PB16 | DREQ1 | Output | D channel request for S-interface chip 1. - | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC - | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC - | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only) - | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom - | PB21 | LEDIO | Output | Led mode indication for PHY - | PB22 | UART_CTS | Input | UART CTS - | PB23 | UART_RTS | Output | UART RTS - | PB24 | UART_RX | Periph | UART Data Rx - | PB25 | UART_TX | Periph | UART Data Tx - | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock) - | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data) - | PB28 | SPI_RXD_3V | Input | SPI Data Rx - | PB29 | SPI_TXD | Output | SPI Data Tx - | PB30 | SPI_CLK | Output | SPI Clock - | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1 - | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt) - | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt) - | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt) - | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt) - | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK) - | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt) - | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt) - | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt) - | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt) - | PC13 | F_RY_BY | Input | NAND ready signal (interrupt) - | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK) - | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request. - | PD3 | F_ALE | Output | NAND - | PD4 | F_CLE | Output | NAND - | PD5 | F_CE | Output | NAND - | PD6 | DSP_INT | Output | DSP debug interrupt - | PD7 | DSP_RESET | Output | DSP reset - | PD8 | RMII_MDC | Periph | MII mgt clock - | PD9 | SPIEN_C1 | Output | SPI CS for codec #1 - | PD10 | SPIEN_C2 | Output | SPI CS for codec #2 - | PD11 | SPIEN_C3 | Output | SPI CS for codec #3 - | PD12 | FSC2 | Periph | IDL2 frame sync - | PD13 | DGRANT2 | Input | D channel grant from S #2 - | PD14 | SPIEN_C4 | Output | SPI CS for codec #4 - | PD15 | TP700 | Output | Testpoint for software debugging - | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data - | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data - | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for - | | DCL2 | Periph | NetRoute: PCM clock #2 - | PE17 | TP703 | Output | Testpoint for software debugging - | PE18 | DGRANT1 | Input | D channel grant from S #1 - | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable - | | PCM2OUT | Periph | NetRoute: Tx data for IDL2 - | PE20 | FSC1 | Periph | IDL1 frame sync - | PE21 | RMII2-RXD0 | Periph | FEC2 receive data - | PE22 | RMII2-RXD1 | Periph | FEC2 receive data - | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC - | PE24 | U-N1 | Output | Select user/network for S #1 (0=user) - | PE25 | U-N2 | Output | Select user/network for S #2 (0=user) - | PE26 | RMII2-RXDV | Periph | FEC2 valid - | PE27 | DREQ2 | Output | D channel request for S #2. - | PE28 | FPGA_DONE | Input | FPGA done signal - | PE29 | FPGA_INIT | Output | FPGA init signal - | PE30 | UDOUT2_3V | Input | IDL2 PCM input - | PE31 | | | Free - +------+----------------+--------+--------------------------------------------------- - - Chip selects: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | CS0 | CS0 | Boot flash - | CS1 | CS_FLASH | NAND flash - | CS2 | CS_DSP | DSP - | CS3 | DCS_DRAM | DRAM - | CS4 | CS_ER1 | External output register - +------+----------------+------------------------------------------------------------ - - Interrupts: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | IRQ1 | UINTER_3V | S interupt chips interrupt (common) - | IRQ3 | IRQ_DSP | DSP interrupt - | IRQ4 | IRQ_DSP1 | Extra DSP interrupt - +------+----------------+------------------------------------------------------------ - -*************************************************************************************************/ - -#define DSP_SIZE 0x00010000 /* 64K */ -#define NAND_SIZE 0x00010000 /* 64K */ -#define ER_SIZE 0x00010000 /* 64K */ -#define DUMMY_SIZE 0x00010000 /* 64K */ - -#define DSP_BASE 0xF1000000 -#define NAND_BASE 0xF1010000 -#define ER_BASE 0xF1020000 -#define DUMMY_BASE 0xF1FF0000 - -/****************************************************************/ - -/* NAND */ -#define CFG_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_MTD_NAND_UNSAFE - -#define CFG_MAX_NAND_DEVICE 1 -/* #define NAND_NO_RB */ - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */ -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \ - } while(0) - -#ifndef NAND_NO_RB -#define NAND_WAIT_READY(nand) \ - do { \ - while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \ - WATCHDOG_RESET(); \ - } \ - } while (0) -#else -#define NAND_WAIT_READY(nand) udelay(12) -#endif - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00100000 -#define CONFIG_JFFS2_PART_OFFSET 0x00200000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nand0=netta-nand" -#define MTDPARTS_DEFAULT "mtdparts=netta-nand:1m@2m(jffs2)" -*/ - -/*****************************************************************************/ - -#define CFG_DIRECT_FLASH_TFTP -#define CFG_DIRECT_NAND_TFTP - -/*****************************************************************************/ - -#if 1 -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ - -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#endif - -/*************************************************************************************************/ - -#define CONFIG_CDP_DEVICE_ID 20 -#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */ -#define CONFIG_CDP_PORT_ID "eth%d" -#define CONFIG_CDP_CAPABILITIES 0x00000010 -#define CONFIG_CDP_VERSION "u-boot 1.0" " " __DATE__ " " __TIME__ -#define CONFIG_CDP_PLATFORM "Intracom NetTA" -#define CONFIG_CDP_TRIGGER 0x20020001 -#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ -#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */ - -/*************************************************************************************************/ - -#define CONFIG_AUTO_COMPLETE 1 - -/*************************************************************************************************/ - -#define CONFIG_CRC32_VERIFY 1 - -/*************************************************************************************************/ - -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 - -/*************************************************************************************************/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h deleted file mode 100644 index 529cb4c..0000000 --- a/include/configs/NETTA2.h +++ /dev/null @@ -1,762 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetTA4 board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2 -#error Unsupported CONFIG_NETTA2 version -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC870 1 /* This is a MPC885 CPU */ -#define CONFIG_NETTA2 1 /* ...on a NetTA2 board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -/* #define CONFIG_XIN 10000000 */ -#define CONFIG_XIN 50000000 -/* #define MPC8XX_HZ 120000000 */ -#define MPC8XX_HZ 66666666 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_AUTOSCRIPT -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ -#define FEC_ENET 1 /* eth.c needs it that way... */ -#undef CFG_DISCOVER_PHY -#define CONFIG_MII 1 -#define CONFIG_RMII 1 /* use RMII interface */ - -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ -#define CONFIG_FEC1_PHY_NORXERR 1 - -#define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 4 -#define CONFIG_FEC2_PHY_NORXERR 1 - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_NAND | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_MII | \ - CFG_CMD_CDP \ - ) - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#if CONFIG_NETTA2_VERSION == 2 -#define CFG_FLASH_BASE4 0x40080000 -#endif - -#define CFG_RESET_ADDRESS 0x80000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#if CONFIG_NETTA2_VERSION == 1 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#elif CONFIG_NETTA2_VERSION == 2 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#endif -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x10000 - -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 0x4000 - -#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) -#define CFG_ENV_OFFSET_REDUND 0 -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -#if CONFIG_XIN == 10000000 - -#if MPC8XX_HZ == 120000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 50000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 25000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 40000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 75000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 10MHz -#endif - -#elif CONFIG_XIN == 50000000 - -#if MPC8XX_HZ == 120000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 100000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 66666666 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 50MHz -#endif - -#else - -#error unsupported XIN freq -#endif - - -/* - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: When TBS == 0 the timebase is independent of current cpu clock. - */ - -#define SCCR_MASK SCCR_EBDF11 -#if MPC8XX_HZ > 66666666 -#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) -#else -#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -#if CONFIG_NETTA2_VERSION == 2 - -#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ - -#define CFG_OR4_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR4_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -#endif - -/* - * BR3 and OR3 (SDRAM) - * - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_MAMR_PTA 234 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_ARTOS /* include ARTOS support */ - -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ - -/****************************************************************/ - -#define DSP_SIZE 0x00010000 /* 64K */ -#define NAND_SIZE 0x00010000 /* 64K */ - -#define DSP_BASE 0xF1000000 -#define NAND_BASE 0xF1010000 - -/****************************************************************/ - -/* NAND */ -#define CFG_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_ECC_JFFS2 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_MTD_NAND_UNSAFE - -#define CFG_MAX_NAND_DEVICE 1 - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \ - } while(0) - -#if CONFIG_NETTA2_VERSION == 1 -#define NAND_WAIT_READY(nand) \ - do { \ - int _tries = 0; \ - while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \ - if (++_tries > 100000) \ - break; \ - } while (0) -#elif CONFIG_NETTA2_VERSION == 2 -#define NAND_WAIT_READY(nand) \ - do { \ - int _tries = 0; \ - while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \ - if (++_tries > 100000) \ - break; \ - } while (0) -#endif - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - -/*****************************************************************************/ - -#define CFG_DIRECT_FLASH_TFTP -#define CFG_DIRECT_NAND_TFTP - -/*****************************************************************************/ - -#if CONFIG_NETTA2_VERSION == 1 -#define STATUS_LED_BIT 0x00000008 /* bit 28 */ -#elif CONFIG_NETTA2_VERSION == 2 -#define STATUS_LED_BIT 0x00000080 /* bit 24 */ -#endif - -#define STATUS_LED_PERIOD (CFG_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifndef __ASSEMBLY__ - -/* LEDs */ - -/* led_id_t is unsigned int mask */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \ - else \ - ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ - } while(0) - -#define __led_init(msk, st) __led_set(msk, st) - -#endif - -/*********************************************************************************************************** - - ---------------------------------------------------------------------------------------------- - - (V1) version 1 of the board - (V2) version 2 of the board - - ---------------------------------------------------------------------------------------------- - - Pin definitions: - - +------+----------------+--------+------------------------------------------------------------ - | # | Name | Type | Comment - +------+----------------+--------+------------------------------------------------------------ - | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select - | PA7 | DSP_INT | Output | DSP interrupt - | PA10 | DSP_RESET | Output | DSP reset - | PA14 | USBOE | Output | USB (1) - | PA15 | USBRXD | Output | USB (1) - | PB19 | BT_RTS | Output | Bluetooth (0) - | PB23 | BT_CTS | Output | Bluetooth (0) - | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select - | PB27 | SPICS_DISP | Output | Display chip select - | PB28 | SPI_RXD_3V | Input | SPI Data Rx - | PB29 | SPI_TXD | Output | SPI Data Tx - | PB30 | SPI_CLK | Output | SPI Clock - | PC10 | DISPA0 | Output | Display A0 - | PC11 | BACKLIGHT | Output | Display backlit - | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD - | | IO_RESET | Output | (V2) General I/O reset - | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) - | | HOOK | Input | (V2) Hook input interrupt - | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK - | | F_RY_BY | Input | (V2) NAND F_RY_BY - | PE17 | F_ALE | Output | NAND F_ALE - | PE18 | F_CLE | Output | NAND F_CLE - | PE20 | F_CE | Output | NAND F_CE - | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select - | | LED | Output | (V2) LED - | PE27 | SPICS_ER | Output | External serial register CS - | PE28 | LEDIO1 | Output | (V1) LED - | | BKBR1 | Input | (V2) Keyboard input scan - | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) - | | BKBR2 | Input | (V2) Keyboard input scan - | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) - | | BKBR3 | Input | (V2) Keyboard input scan - | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY - | | BKBR4 | Input | (V2) Keyboard input scan - +------+----------------+--------+--------------------------------------------------- - - ---------------------------------------------------------------------------------------------- - - Serial register input: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | 4 | HOOK | Hook switch - | 5 | BT_LINK | Bluetooth link status - | 6 | HOST_WAKE | Bluetooth host wake up - | 7 | OK_ETH | Cisco inline power OK status - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Chip selects: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | CS0 | CS0 | Boot flash - | CS1 | CS_FLASH | NAND flash - | CS2 | CS_DSP | DSP - | CS3 | DCS_DRAM | DRAM - | CS4 | CS_FLASH2 | (V2) 2nd flash - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Interrupts: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | IRQ1 | IRQ_DSP | DSP interrupt - | IRQ3 | S_INTER | DUSLIC ??? - | IRQ4 | F_RY_BY | NAND - | IRQ7 | IRQ_MAX | MAX 3100 interrupt - +------+----------------+------------------------------------------------------------ - - ---------------------------------------------------------------------------------------------- - - Interrupts on PCMCIA pins: - - +------+----------------+------------------------------------------------------------ - | # | Name | Comment - +------+----------------+------------------------------------------------------------ - | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface - | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface - | IP_A2| RMII1_MDINT | PHY interrupt for #1 - | IP_A3| RMII2_MDINT | PHY interrupt for #2 - | IP_A5| HOST_WAKE | (V2) Bluetooth host wake - | IP_A6| OK_ETH | (V2) Cisco inline power OK - +------+----------------+------------------------------------------------------------ - -**************************************************************************************************/ - -#define CFG_CONSOLE_IS_IN_ENV 1 -#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 -#define CFG_CONSOLE_ENV_OVERWRITE 1 - -/*************************************************************************************************/ - -/* use board specific hardware */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_SHOW_ACTIVITY - -/*************************************************************************************************/ - -#define CONFIG_CDP_DEVICE_ID 20 -#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta2 */ -#define CONFIG_CDP_PORT_ID "eth%d" -#define CONFIG_CDP_CAPABILITIES 0x00000010 -#define CONFIG_CDP_VERSION "u-boot" " " __DATE__ " " __TIME__ -#define CONFIG_CDP_PLATFORM "Intracom NetTA2" -#define CONFIG_CDP_TRIGGER 0x20020001 -#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ -#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone ? */ - -/*************************************************************************************************/ - -#define CONFIG_AUTO_COMPLETE 1 - -/*************************************************************************************************/ - -#define CONFIG_CRC32_VERIFY 1 - -/*************************************************************************************************/ - -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 - -/*************************************************************************************************/ -#endif /* __CONFIG_H */ diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h deleted file mode 100644 index dc6b15f..0000000 --- a/include/configs/NETVIA.h +++ /dev/null @@ -1,530 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr - * U-Boot port on NetVia board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_NETVIA 1 /* ...on a NetVia board */ - -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#else -#define CONFIG_8xx_CONS_NONE -#define CONFIG_MAX3100_SERIAL -#endif - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_XIN 10000000 -#define CONFIG_8xx_GCLK_FREQ 80000000 - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ -#endif - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS_BASE ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING ) - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 -#define CONFIG_COMMANDS (CONFIG_COMMANDS_BASE | CFG_CMD_NAND) -#else -#define CONFIG_COMMANDS CONFIG_COMMANDS_BASE -#endif - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x10000 - -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 0x4000 - -#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) -#define CFG_ENV_OFFSET_REDUND 0 -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ - -#define SCCR_MASK SCCR_EBDF11 - -#if CONFIG_8xx_GCLK_FREQ == 50000000 - -#define CFG_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -#elif CONFIG_8xx_GCLK_FREQ == 80000000 - -#define CFG_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) - -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR3 and OR3 (SDRAM) - * - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 208 - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* Ethernet at SCC2 */ -#define CONFIG_SCC2_ENET - -#define CONFIG_ARTOS /* include ARTOS support */ - -/****************************************************************/ - -#define DSP_SIZE 0x00010000 /* 64K */ -#define FPGA_SIZE 0x00010000 /* 64K */ - -#define DSP0_BASE 0xF1000000 -#define DSP1_BASE (DSP0_BASE + DSP_SIZE) -#define FPGA_BASE (DSP1_BASE + DSP_SIZE) - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - -#define ER_SIZE 0x00010000 /* 64K */ -#define ER_BASE (FPGA_BASE + FPGA_SIZE) - -#define NAND_SIZE 0x00010000 /* 64K */ -#define NAND_BASE (ER_BASE + ER_SIZE) - -#endif - -/****************************************************************/ - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - -#define STATUS_LED_BIT 0x00000001 /* bit 31 */ -#define STATUS_LED_PERIOD (CFG_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING - -#define STATUS_LED_BIT1 0x00000002 /* bit 30 */ -#define STATUS_LED_PERIOD1 (CFG_HZ / 2) -#define STATUS_LED_STATE1 STATUS_LED_OFF - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#endif - -/*****************************************************************************/ - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - -/* NAND */ -#define CFG_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_ECC_JFFS2 - -#define CFG_MAX_NAND_DEVICE 1 - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0040; \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0100; \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0080; \ - } while(0) - -#define NAND_WAIT_READY(nand) \ - do { \ - while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \ - ; \ - } while (0) - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - -#endif - -/*****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - -/* LEDs */ - -/* last value written to the external register; we cannot read back */ -extern unsigned int last_er_val; - -/* led_id_t is unsigned long mask */ -typedef unsigned int led_id_t; - -static inline void __led_init(led_id_t mask, int state) -{ - unsigned int new_er_val; - - if (state) - new_er_val = last_er_val & ~mask; - else - new_er_val = last_er_val | mask; - - *(volatile unsigned int *)ER_BASE = new_er_val; - last_er_val = new_er_val; -} - -static inline void __led_toggle(led_id_t mask) -{ - unsigned int new_er_val; - - new_er_val = last_er_val ^ mask; - *(volatile unsigned int *)ER_BASE = new_er_val; - last_er_val = new_er_val; -} - -static inline void __led_set(led_id_t mask, int state) -{ - unsigned int new_er_val; - - if (state) - new_er_val = last_er_val & ~mask; - else - new_er_val = last_er_val | mask; - - *(volatile unsigned int *)ER_BASE = new_er_val; - last_er_val = new_er_val; -} - -/* MAX3100 console */ -#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define MAX3100_SPI_RXD_BIT 0x00000008 - -#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define MAX3100_SPI_TXD_BIT 0x00000004 - -#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define MAX3100_SPI_CLK_BIT 0x00000002 - -#define MAX3100_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) -#define MAX3100_CS_BIT 0x0010 - -#endif - -#endif - -/*************************************************************************************************/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h deleted file mode 100644 index d994420..0000000 --- a/include/configs/NSCU.h +++ /dev/null @@ -1,461 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ -#define CONFIG_NSCU 1 - -#define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */ - -#define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/NSCU/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -/* NSCU use both slots, SLOT_A as "primary". */ -#define CONFIG_PCMCIA_SLOT_A 1 - -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ -#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ -#undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE buses */ -#define CFG_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) /* starts @ 4th window */ - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -#ifdef CONFIG_ISP1362_USB -#define CFG_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */ -#define CFG_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR5_ISP1362 (CFG_ISP1362_OR_AM | OR_CSNT_SAM | \ - OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK) -#define CFG_BR5_ISP1362 ((CFG_ISP1362_BASE & BR_BA_MSK) | \ - BR_PS_16 | BR_MS_GPCM | BR_V ) -#endif /* CONFIG_ISP1362_USB */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#undef CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -/* #define CONFIG_ETHPRIME "FEC ETHERNET" */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/NX823.h b/include/configs/NX823.h deleted file mode 100644 index 1cb8b8f..0000000 --- a/include/configs/NX823.h +++ /dev/null @@ -1,360 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_NX823 1 /* ...on a NEXUS 823 module */ - -/*#define CONFIG_VIDEO 1 */ - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */ -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#define CONFIG_BOOTARGS "ramdisk=8000 "\ - "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\ - "nfsaddrs=10.77.77.20:10.77.77.250" -#define CONFIG_BOOTCOMMAND "bootm 400e0000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#undef CONFIG_WATCHDOG /* watchdog disabled, for now */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_AUTOSCRIPT) -#define CONFIG_AUTOSCRIPT - -/* call various generic functions */ -#define CONFIG_MISC_INIT_R - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define xEMBED -#ifdef EMBED -#define CFG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */ -#define CFG_ENV_ADDR CFG_MONITOR_BASE -#else -#define CFG_ENV_ADDR 0x40020000 /* absolute address for now */ -#define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ -#endif - -#define CFG_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */ -#define CFG_FLASH_SN_SECTOR 0x40000000 /* a serial number here */ -#define CFG_FLASH_SN_BYTES 8 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 12-30 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 12-16 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 12-18 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 12-23 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 5-7 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define MPC8XX_SPEED 66666666L -#define MPC8XX_XIN 32768 /* 32.768 kHz crystal */ -#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) -#define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) -#define CFG_PLPRCR (CFG_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 5-3 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - OR_SCY_8_CLK ) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR1/2 and OR1/2 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */ -#define CFG_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM) - -#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#define CFG_OR2_PRELIM CFG_OR1_PRELIM -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* IO and memory mapped stuff */ -#define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */ -#define NX823_IO_BASE 0xFF000000 /* start of IO */ -#define GPOUT_OFFSET (3<<16) -#define QUART_OFFSET (4<<16) -#define VIDAC_OFFSET (5<<16) -#define CPLD_OFFSET (6<<16) -#define SED1386_OFFSET (7<<16) - -/* - * BR3 and OR3 (general purpose output latches) - */ -#define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET) -#define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI) -#define CFG_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING) -#define CFG_BR3_PRELIM (GPOUT_BASE | BR_V) - -/* - * BR4 and OR4 (QUART) - */ -#define QUART_BASE (NX823_IO_BASE + QUART_OFFSET) -#define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX) -#define CFG_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI) -#define CFG_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V) - -/* - * BR5 and OR5 (Video DAC) - */ -#define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET) -#define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) -#define CFG_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI) -#define CFG_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V) - -/* - * BR6 and OR6 (CPLD) - * FIXME timing not verified for CPLD - */ -#define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET) -#define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) -#define CFG_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI) -#define CFG_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V ) - -/* - * BR7 and OR7 (SED1386) - * FIXME timing not verified for SED controller - */ -#define SED1386_BASE 0xF7000000 -#define CFG_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA) -#define CFG_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */ -#define CONFIG_ETHADDR 00:10:20:30:40:50 -#define CONFIG_IPADDR 10.77.77.20 -#define CONFIG_SERVERIP 10.77.77.250 - -#endif /* __CONFIG_H */ diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h deleted file mode 100644 index aa9d1ba..0000000 --- a/include/configs/OCRTC.h +++ /dev/null @@ -1,302 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_OCRTC 1 /* ...on a OCRTC board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "go fff00100" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ELF | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFD0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ -#define CFG_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ - -#else /* Use EEPROM for environment variables */ - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (PLD - FPGA-boot) initialization */ -#define CFG_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (PLD - OSL) initialization */ -#define CFG_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (Spartan2 1) initialization */ -#define CFG_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 5 (Spartan2 2) initialization */ -#define CFG_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 6 (Virtex 1) initialization */ -#define CFG_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 7 (Virtex 2) initialization */ -#define CFG_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ - - -#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h deleted file mode 100644 index 2e7c505..0000000 --- a/include/configs/ORSG.h +++ /dev/null @@ -1,300 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_ORSG 1 /* ...on a ORSG board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "go fff00100" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ELF | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */ -#undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFD0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ -#define CFG_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ - -#else /* Use EEPROM for environment variables */ - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (PLD - FPGA-boot) initialization */ -#define CFG_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (PLD - OSL) initialization */ -#define CFG_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (Spartan2 1) initialization */ -#define CFG_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 5 (Spartan2 2) initialization */ -#define CFG_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ - -/* Memory Bank 6 (Virtex 1) initialization */ -#define CFG_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 7 (Virtex 2) initialization */ -#define CFG_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ -#define CFG_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ - - -#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/OXC.h b/include/configs/OXC.h deleted file mode 100644 index 787407c..0000000 --- a/include/configs/OXC.h +++ /dev/null @@ -1,314 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_OXC 1 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#define CONFIG_IDENT_STRING " [oxc] " - -#define CONFIG_WATCHDOG 1 -#define CONFIG_SHOW_ACTIVITY 1 -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ - -/*----------------------------------------------------------------------- - * Boot options - */ - -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 0x10000 -#define CONFIG_BOOTFILE "/mnt/ide0/p2/usr/tftp/oxc.elf" -#define CONFIG_BOOTCOMMAND "tftp 0x10000 ; bootelf 0x10000" -#define CONFIG_BOOTDELAY 10 - -#define CFG_OXC_GENERATE_IP 1 /* Generate IP automatically */ -#define CFG_OXC_IPMASK 0x0A000000 /* 10.0.0.x */ - -/*----------------------------------------------------------------------- - * PCI stuff - */ - -#define CONFIG_PCI /* include pci support */ - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_EEPRO100 /* Ethernet Express PRO 100 */ -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - -/*----------------------------------------------------------------------- - * FLASH - */ - -#define CFG_FLASH_PRELIMBASE 0xFF800000 -#define CFG_FLASH_BASE (0-flash_info[0].size) - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * RAM - */ - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x10000000 - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN 0x00030000 - -#if (CFG_MONITOR_BASE < CFG_FLASH_PRELIMBASE) -# define CFG_RAMBOOT 1 -#else -# undef CFG_RAMBOOT -#endif - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 - -#define CFG_GBL_DATA_SIZE 128 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Memory mapping - */ - -#define CFG_CPLD_BASE 0xff000000 /* CPLD registers */ -#define CFG_CPLD_WATCHDOG (CFG_CPLD_BASE) /* Watchdog */ -#define CFG_CPLD_RESET (CFG_CPLD_BASE + 0x040000) /* Minor resets */ -#define CFG_UART_BASE (CFG_CPLD_BASE + 0x700000) /* debug UART */ - -/*----------------------------------------------------------------------- - * NS16550 Configuration - */ - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE -4 -#define CFG_NS16550_CLK 1843200 -#define CFG_NS16550_COM1 CFG_UART_BASE - -/*----------------------------------------------------------------------- - * I2C Bus - */ - -#define CONFIG_I2C 1 /* I2C support on ... */ -#define CONFIG_HARD_I2C 1 /* ... hardware one */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ - -#define CFG_I2C_EXPANDER0_ADDR 0x20 /* PCF8574 expander 0 addrerr */ -#define CFG_I2C_EXPANDER1_ADDR 0x21 /* PCF8574 expander 1 addrerr */ -#define CFG_I2C_EXPANDER2_ADDR 0x26 /* PCF8574 expander 2 addrerr */ - -/*----------------------------------------------------------------------- - * Environment - */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0xFFF30000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */ -#define CFG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */ -#define CONFIG_ENV_OVERWRITE 1 /* Allow modifying the environment */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 - -#define CFG_EUMB_ADDR 0xFC000000 - -/* MCCR1 */ -#define CFG_ROMNAL 0 /* rom/flash next access time */ -#define CFG_ROMFAL 19 /* rom/flash access time */ - -/* MCCR2 */ -#define CFG_ASRISE 15 /* ASRISE=15 clocks */ -#define CFG_ASFALL 3 /* ASFALL=3 clocks */ -#define CFG_REFINT 1000 /* REFINT=1000 clocks */ - -/* MCCR3 */ -#define CFG_BSTOPRE 0x35c /* Burst To Precharge */ -#define CFG_REFREC 7 /* Refresh to activate interval */ -#define CFG_RDLAT 4 /* data latency from read command */ - -/* MCCR4 */ -#define CFG_PRETOACT 2 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_ACTORW 2 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length 2=4, 3=8 */ -#define CFG_REGISTERD_TYPE_BUFFER 1 - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x00000000 -#define CFG_BANK1_END 0x00000000 -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x00000000 -#define CFG_BANK2_END 0x00000000 -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x00000000 -#define CFG_BANK3_END 0x00000000 -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CFG_BANK_ENABLE 0x01 - -#define CFG_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -/* PCI memory */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h deleted file mode 100644 index a933e1b..0000000 --- a/include/configs/P3G4.h +++ /dev/null @@ -1,426 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef __ASSEMBLY__ -#include -#endif - -#include "../board/evb64260/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_P3G4 1 /* this is a P3G4 board */ -#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ - -#undef CONFIG_ECC /* enable ECC support */ -/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#define CFG_BOARD_NAME "P3G4" - -#undef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - -#define CONFIG_NET_MULTI /* attempt all available adapters */ - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=p3g4\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_74xx\0" \ - "bootfile=/tftpboot/p3g4/uImage\0" \ - "kernel_addr=ff000000\0" \ - "ramdisk_addr=ff010000\0" \ - "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \ - "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ - "cp.b 100000 fff00000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_UNIVERSE| \ - CFG_CMD_BSP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00300000 /* default load address */ - -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ -#define CFG_BUS_HZ 133000000 /* 133 MHz */ -#define CFG_BUS_CLK CFG_BUS_HZ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xff000000 -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 1 -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CFG_GT_REGS 0xf8000000 -#define CFG_DEV_BASE 0xff000000 - -#define CFG_DEV0_SPACE CFG_DEV_BASE -#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) -#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) -#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) - -#define CFG_DEV0_SIZE _8M /* Flash bank */ -#define CFG_DEV1_SIZE 0 /* unused */ -#define CFG_DEV2_SIZE 0 /* unused */ -#define CFG_DEV3_SIZE 0 /* unused */ - -#define CFG_16BIT_BOOT_PAR 0xc01b5e7c -#define CFG_DEV0_PAR CFG_16BIT_BOOT_PAR - -#if 0 /* Wrong?? NTL */ -#define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ - /* DMAAck[1:0] GNT0[1:0] */ -#else -#define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ - /* REQ0[1:0] GNT0[1:0] */ -#endif -#define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ - /* DMAReq[4] DMAAck[4] WDNMI WDE */ -#if 0 /* Wrong?? NTL */ -#define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ - /* DMAAck[1:0] GNT1[1:0] */ -#else -#define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ - /* GPP[22] (RS232IntB or PCI1Int) */ - /* GPP[21] (RS323IntA) */ - /* BClkIn */ - /* REQ1[1:0] GNT1[1:0] */ -#endif - -#if 0 /* Wrong?? NTL */ -# define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ - /* GPP[27:26] Int[1:0] */ -#else -# define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ - /* GPP[29] (PCI1Int) */ - /* BClkOut0 */ - /* GPP[27] (PCI0Int) */ - /* GPP[26] (RtcInt or PCI1Int) */ - /* CPUInt[25:24] */ -#endif - -#define CFG_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */ - -#if 0 /* Wrong?? - NTL */ -# define CFG_GPP_LEVEL_CONTROL 0x000002c6 -#else -# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ - /* gpp[29] */ - /* gpp[27:26] */ - /* gpp[22:21] */ - -# define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 0 - pci use buffer 1,1 - cpu use buffer 0 - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 110110 00 111 0 0 00 1 */ - /* refresh_count=0x200 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ -#endif - -#if 0 -#define CFG_DUART_IO CFG_DEV2_SPACE -#define CFG_DUART_CHAN 1 /* channel to use for console */ -#endif -#undef CFG_INIT_CHAN1 -#undef CFG_INIT_CHAN2 -#if 0 -#define SRAM_BASE CFG_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ -#endif - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) - -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI 0x00000000 - -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI 0x00000000 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* I2C speed and slave address (for compatability) defaults */ -#define CFG_I2C_SPEED 400000 -#define CFG_I2C_SLAVE 0x7F - -/* I2C addresses for the two DIMM SPD chips */ -#ifndef CONFIG_EVB64260_750CX -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 -#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ -#define DIMM0_I2C_ADDR 0x54 -#define DIMM1_I2C_ADDR 0x54 -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_EXTRA_FLASH_DEVICE BOOT_DEVICE -#define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */ -#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_CFI 1 - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR 0xFFFE0000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CFG_L2 - -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_BOARD_ASM_INIT 1 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/PATI.h b/include/configs/PATI.h deleted file mode 100644 index d88fff3..0000000 --- a/include/configs/PATI.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, - */ - -/* - * File: PATI.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_PATI 1 /* ...On a PATI board */ -/* Serial Console Configuration */ -#define CONFIG_5xx_CONS_SCI1 -#undef CONFIG_5xx_CONS_SCI2 - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \ - CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ENV | CFG_CMD_REGINFO | \ - CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_RUN | CFG_CMD_BSP | \ - CFG_CMD_IMI | CFG_CMD_EEPROM | CFG_CMD_IRQ | CFG_CMD_MISC \ -) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "" /* autoboot command */ - -#define CONFIG_BOOTARGS "" /* */ - -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ - -/*#define CONFIG_STATUS_LED 1 */ /* Enable status led */ - -#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ - -/* - * Miscellaneous configurable options - */ -#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ -#define CONFIG_PREBOOT - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "pati=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00010000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } - - -/*********************************************************************** - * Last Stage Init - ***********************************************************************/ -#define CONFIG_LAST_STAGE_INIT - -/* - * Low Level Configuration Settings - */ - -/* - * Internal Memory Mapped (This is not the IMMR content) - */ -#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */ - -/* - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ -#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */ -/* - * Start addresses for the final memory configuration - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ -#define CFG_FLASH_BASE 0xffC00000 /* External flash */ -#define PCI_BASE 0x03000000 /* PCI Base (CS2) */ -#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ -#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ - -#define CFG_MONITOR_BASE 0xFFF00000 -/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CFG_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/*----------------------------------------------------------------------- - * FLASH organization - *----------------------------------------------------------------------- - * - */ - -#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ - - -#define CFG_ENV_IS_IN_EEPROM -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 2048 -#endif - -#undef CFG_ENV_IS_IN_FLASH -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */ -#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */ -#endif - - -#define CONFIG_SPI 1 -#define CFG_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ -#define CFG_SPI_CS_BASE 0x08 /* CS3 is active low */ -#define CFG_SPI_CS_ACT 0x00 /* CS3 is active low */ -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * SW Watchdog freeze - */ -#undef CONFIG_WATCHDOG -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ - SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration - *----------------------------------------------------------------------- - * Data show cycle - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register - *----------------------------------------------------------------------- - * Set all bits to 40 Mhz - * - */ -#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ - - -#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) - -/*----------------------------------------------------------------------- - * UMCR - UIMB Module Configuration Register - *----------------------------------------------------------------------- - * - */ -#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ - -/*----------------------------------------------------------------------- - * ICTRL - I-Bus Support Control Register - */ -#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ - -/*----------------------------------------------------------------------- - * USIU - Memory Controller Register - *----------------------------------------------------------------------- - */ -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) -#define CFG_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ -/* SDRAM */ -#define CFG_BR1_PRELIM (CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CFG_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ -/* PCI */ -#define CFG_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) -#define CFG_OR2_PRELIM (OR_ADDR_MK_FF) -/* config registers: */ -#define CFG_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CFG_OR3_PRELIM (0xffff0000) - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */ - -/*----------------------------------------------------------------------- - * DER - Timer Decrementer - *----------------------------------------------------------------------- - * Initialise to zero - */ -#define CFG_DER 0x00000000 - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#define VERSION_TAG "released" -#define CONFIG_ISO_STRING "MEV-10084-001" - -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG - -#endif /* __CONFIG_H */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h deleted file mode 100644 index 9d5c4f4..0000000 --- a/include/configs/PCI405.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $" - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PCI405 1 /* ...on a PCI405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mem_linux=14336k\0" \ - "optargs=panic=0\0" \ - "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \ - "addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ - "" -#define CONFIG_BOOTCOMMAND "run ramargs;run addcon;loadpci" - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */ -#undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */ -#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ - -#if 0 /* test-only */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -#else -#define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs */ -#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFD0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */ - -#else /* Use EEPROM for environment variables */ - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/ - /* total size of a CAT24WC08 is 1024 bytes */ -#endif - -#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (NVRAM/RTC) initialization */ -#define CFG_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ -#define CFG_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (CAN0, 1) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -/*#define CFG_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (FPGA internal) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ -#define CFG_FPGA_BASE_ADDR 0xF0400000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CFG_FPGA_MODE 0x00 -#define CFG_FPGA_STATUS 0x02 -#define CFG_FPGA_TS 0x04 -#define CFG_FPGA_TS_LOW 0x06 -#define CFG_FPGA_TS_CAP0 0x10 -#define CFG_FPGA_TS_CAP0_LOW 0x12 -#define CFG_FPGA_TS_CAP1 0x14 -#define CFG_FPGA_TS_CAP1_LOW 0x16 -#define CFG_FPGA_TS_CAP2 0x18 -#define CFG_FPGA_TS_CAP2_LOW 0x1a -#define CFG_FPGA_TS_CAP3 0x1c -#define CFG_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CFG_FPGA_MODE_CF_RESET 0x0001 -#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CFG_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CFG_FPGA_STATUS_DIP0 0x0001 -#define CFG_FPGA_STATUS_DIP1 0x0002 -#define CFG_FPGA_STATUS_DIP2 0x0004 -#define CFG_FPGA_STATUS_FLASH 0x0008 -#define CFG_FPGA_STATUS_TS_IRQ 0x1000 - -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ -/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */ -#define CFG_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -#if 0 /* test-only */ -#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ -#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#else -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h deleted file mode 100644 index 3a7f7f0..0000000 --- a/include/configs/PCI5441.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_PCI5441 1 /* PCI-5441 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ -#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP CFG_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above - * CFG_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) -#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ -#else -#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */ -#endif - -#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. - *----------------------------------------------------------------------*/ -#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ -#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) - -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* Provide extended help*/ -#define CFG_PROMPT "==> " /* Command prompt */ -#define CFG_CBSIZE 256 /* Console I/O buf size */ -#define CFG_MAXARGS 16 /* Max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ -#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ -#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ -#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h deleted file mode 100644 index d03706e..0000000 --- a/include/configs/PCIPPC2.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the PCIPPC-2 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_PREBOOT "" -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_ELF | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - -#define CFG_MAXARGS 64 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF00000 -#define CFG_FLASH_MAX_SIZE 0x00100000 -/* Maximum amount of RAM. - */ -#define CFG_MAX_RAM_SIZE 0x20000000 /* 512Mb */ - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ - CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* Size in bytes reserved for initial data - */ -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x8000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_INIT_RAM_LOCK - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR -#define CFG_SCONSOLE_SIZE 0x0002000 - -/* SDRAM 0 - 256MB - */ -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (CFG_SDRAM_BASE | \ - BATU_BL_256M | BATU_VS | BATU_VP) -/* SDRAM 1 - 256MB - */ -#define CFG_DBAT1L ((CFG_SDRAM_BASE + 0x10000000) | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT1U ((CFG_SDRAM_BASE + 0x10000000) | \ - BATU_BL_256M | BATU_VS | BATU_VP) - -/* Init RAM in the CPU DCache (no backing memory) - */ -#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | \ - BATU_BL_128K | BATU_VS | BATU_VP) - -/* I/O and PCI memory at 0xf0000000 - */ -#define CFG_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT0L CFG_DBAT0L -#define CFG_IBAT0U CFG_DBAT0U -#define CFG_IBAT1L CFG_DBAT1L -#define CFG_IBAT1U CFG_DBAT1U -#define CFG_IBAT2L CFG_DBAT2L -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_IBAT3L CFG_DBAT3L -#define CFG_IBAT3U CFG_DBAT3U - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the PCIPPC2 user's manual. - */ -#define CFG_HZ 1000 -#define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */ -#define CFG_CPU_CLK 300000000 -#define CFG_BUS_CLK 100000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -/* - * Note: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x70000) -#define CFG_ENV_SIZE 0x1000 /* Size of the Environment */ -#define CFG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2 cache - */ -#undef CFG_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CFG_DOC_SUPPORT_2000 -#undef CFG_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- - RTC m48t59 -*/ -#define CONFIG_RTC_MK48T59 - -#define CONFIG_WATCHDOG - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_TULIP - -#endif /* __CONFIG_H */ diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h deleted file mode 100644 index 92b2f7c..0000000 --- a/include/configs/PCIPPC6.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the PCIPPC-6 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_PREBOOT "" -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_ELF | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SCSI | \ - CFG_CMD_SNTP ) - - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - -#define CFG_MAXARGS 64 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF00000 -#define CFG_FLASH_MAX_SIZE 0x00100000 -/* Maximum amount of RAM. - */ -#define CFG_MAX_RAM_SIZE 0x20000000 /* 512Mb */ - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ - CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* Size in bytes reserved for initial data - */ -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x8000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_INIT_RAM_LOCK - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR -#define CFG_SCONSOLE_SIZE 0x0002000 - -/* SDRAM 0 - 256MB - */ -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (CFG_SDRAM_BASE | \ - BATU_BL_256M | BATU_VS | BATU_VP) -/* SDRAM 1 - 256MB - */ -#define CFG_DBAT1L ((CFG_SDRAM_BASE + 0x10000000) | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT1U ((CFG_SDRAM_BASE + 0x10000000) | \ - BATU_BL_256M | BATU_VS | BATU_VP) - -/* Init RAM in the CPU DCache (no backing memory) - */ -#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | \ - BATU_BL_128K | BATU_VS | BATU_VP) - -/* I/O and PCI memory at 0xf0000000 - */ -#define CFG_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT0L CFG_DBAT0L -#define CFG_IBAT0U CFG_DBAT0U -#define CFG_IBAT1L CFG_DBAT1L -#define CFG_IBAT1U CFG_DBAT1U -#define CFG_IBAT2L CFG_DBAT2L -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_IBAT3L CFG_DBAT3L -#define CFG_IBAT3U CFG_DBAT3U - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the PCIPPC2 user's manual. - */ -#define CFG_HZ 1000 -#define CFG_BUS_HZ 100000000 /* bus speed - 100 mhz */ -#define CFG_CPU_CLK 300000000 -#define CFG_BUS_CLK 100000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -/* - * Note: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x70000) -#define CFG_ENV_SIZE 0x1000 /* Size of the Environment */ -#define CFG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2 cache - */ -#undef CFG_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CFG_DOC_SUPPORT_2000 -#undef CFG_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- - RTC m48t59 -*/ -#define CONFIG_RTC_MK48T59 - -#define CONFIG_WATCHDOG - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_TULIP - - -#define CONFIG_SCSI_SYM53C8XX -#define CONFIG_SCSI_DEV_ID 0x000B /* 53c896 */ -#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ -#define CFG_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */ -#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ -#define CFG_SCSI_SPIN_UP_TIME 2 -#define CFG_SCSI_SCAN_BUS_REVERSE 0 -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION - -#endif /* __CONFIG_H */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h deleted file mode 100644 index 9668fb0..0000000 --- a/include/configs/PIP405.h +++ /dev/null @@ -1,386 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*********************************************************** - * High Level Configuration Options - * (easy to change) - ***********************************************************/ -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PIP405 1 /* ...on a PIP405 board */ -/*********************************************************** - * Clock - ***********************************************************/ -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -/*********************************************************** - * Command definitions - ***********************************************************/ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_IDE | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_CACHE | \ - CFG_CMD_IRQ | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_REGINFO | \ - CFG_CMD_FDC | \ - CFG_CMD_SCSI | \ - CFG_CMD_FAT | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_USB | \ - CFG_CMD_MII | \ - CFG_CMD_SDRAM | \ - CFG_CMD_DOC | \ - CFG_CMD_PING | \ - CFG_CMD_SAVES | \ - CFG_CMD_BSP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -/************************************************************** - * I2C Stuff: - * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address - * 0x53. - * Caution: on the same bus is the SPD (Serial Presens Detect - * EEPROM of the SDRAM - * The Atmel EEPROM uses 16Bit addressing. - ***************************************************************/ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x53 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */ - -#undef CFG_I2C_EEPROM_ADDR_OVERFLOW -#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ - /* 64 byte page write mode using*/ - /* last 6 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - - -/*************************************************************** - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - ***************************************************************/ -#define SPD_EEPROM_ADDRESS 0x50 - -#define CONFIG_BOARD_EARLY_INIT_F -/************************************************************** - * Environment definitions - **************************************************************/ -#define CONFIG_BAUDRATE 9600 /* STD Baudrate */ - - -#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ - - -#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ -#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ - -#define CONFIG_IPADDR 10.0.0.100 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_PREBOOT -/*************************************************************** - * defines if the console is stored in the environment - ***************************************************************/ -#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ -/*************************************************************** - * defines if an overwrite_console function exists - *************************************************************/ -#define CFG_CONSOLE_OVERWRITE_ROUTINE -#define CFG_CONSOLE_INFO_QUIET -/*************************************************************** - * defines if the overwrite_console should be stored in the - * environment - **************************************************************/ -#undef CFG_CONSOLE_ENV_OVERWRITE - -/************************************************************** - * loads config - *************************************************************/ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MISC_INIT_R -/*********************************************************** - * Miscellaneous configurable options - **********************************************************/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ - /* resource configuration */ -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - */ -#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ -#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ - -#define CONFIG_BOARD_EARLY_INIT_F - -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF4000000 -#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in On Chip SRAM) - */ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR 0xF0000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*********************************************************************** - * External peripheral base address - ***********************************************************************/ -#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000 - -/*********************************************************************** - * Last Stage Init - ***********************************************************************/ -#define CONFIG_LAST_STAGE_INIT -/************************************************************ - * Ethernet Stuff - ***********************************************************/ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */ -/************************************************************ - * RTC - ***********************************************************/ -#define CONFIG_RTC_MC146818 -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/************************************************************ - * IDE/ATA stuff - ************************************************************/ -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */ -#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ - -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* reset for ide supported... */ -#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ -#define CONFIG_SUPPORT_VFAT - -/************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI /* enable ATAPI Support */ - -/************************************************************ - * SCSI support (experimental) only SYM53C8xx supported - ************************************************************/ -#define CONFIG_SCSI_SYM53C8XX -#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ -#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */ -#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ -#define CFG_SCSI_SPIN_UP_TIME 2 - -/************************************************************ - * Disk-On-Chip configuration - ************************************************************/ -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ -#define CFG_DOC_SHORT_TIMEOUT -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM - -/************************************************************ - * DISK Partition support - ************************************************************/ -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION /* Experimental */ - -/************************************************************ - * Keyboard support - ************************************************************/ -#define CONFIG_ISA_KEYBOARD - -/************************************************************ - * Video support - ************************************************************/ -#define CONFIG_VIDEO /*To enable video controller support */ -#define CONFIG_VIDEO_CT69000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ - -/************************************************************ - * USB support - ************************************************************/ -#define CONFIG_USB_UHCI -#define CONFIG_USB_KEYBOARD -#define CONFIG_USB_STORAGE - -/* Enable needed helper functions */ -#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ - -/************************************************************ - * Debug support - ************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/************************************************************ - * support BZIP2 compression - ************************************************************/ -#define CONFIG_BZIP2 1 - -/************************************************************ - * Ident - ************************************************************/ -#define VERSION_TAG "released" -#define CONFIG_ISO_STRING "MEV-10066-001" -#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG - - -#endif /* __CONFIG_H */ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h deleted file mode 100644 index 91e9518..0000000 --- a/include/configs/PK1C20.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_PK1C20 1 /* PK1C20 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */ -#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ -#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP CFG_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above - * CFG_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CONSOLE_JTAG) -#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ -#else -#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */ -#endif - -#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for - * epcs device access is enabled. The base address is the epcs - * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. - * The register base is currently at offset 0x400 from the memory base. - *----------------------------------------------------------------------*/ -#define CFG_NIOS_EPCSBASE 0x00900400 /* EPCS register base */ - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, we can slow it down to 10 msec using TMRCNT. If the default - * period is acceptable, TMRCNT can be left undefined. - *----------------------------------------------------------------------*/ -#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ -#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- leds are, after all, - * board-specific, no? - *----------------------------------------------------------------------*/ -#define CFG_LEDPIO_ADDR 0x00920840 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x80910300 /* Base addr (bypass) */ -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include - -/*------------------------------------------------------------------------ - * COMPACT FLASH - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CONFIG_IDE_PREINIT /* Implement id_preinit */ -#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0x00900800 /* ATA base addr */ -#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ -#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ -#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */ -#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ -#define CFG_ATA_STRIDE 4 /* Width betwix addrs */ -#define CONFIG_DOS_PARTITION - -/* Board-specific cf regs */ -#define CFG_CF_PRESENT 0x00900880 /* CF Present PIO base */ -#define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/ -#define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ - -#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ - -/*------------------------------------------------------------------------ - * JFFS2 - *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) -#define CFG_JFFS_CUSTOM_PART /* board defined part */ -#endif - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* Provide extended help*/ -#define CFG_PROMPT "==> " /* Command prompt */ -#define CFG_CBSIZE 256 /* Console I/O buf size */ -#define CFG_MAXARGS 16 /* Max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ -#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ -#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ -#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -#endif /* __CONFIG_H */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h deleted file mode 100644 index 54ecfa4..0000000 --- a/include/configs/PLU405.h +++ /dev/null @@ -1,455 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PLU405 1 /* ...on a PLU405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if 0 /* test-only */ -#define CONFIG_NET_MULTI 1 - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY1_ADDR 1 /* PHY address */ -#else -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#endif -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -/* Only interrupt boot if space is pressed */ -/* If a long serial cable is connected but */ -/* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_AUTOBOOT_STOP_STR " " - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CFG_RAMBOOT 1 -#else -# undef CFG_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#if 1 /* test-only */ -/* CAT24WC08/16... */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#else -/* CAT24WC32/64... */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#endif -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ -#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ - -#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ - -/* FPGA internal regs */ -#define CFG_FPGA_CTRL 0x000 - -/* FPGA Control Reg */ -#define CFG_FPGA_CTRL_CF_RESET 0x0001 -#define CFG_FPGA_CTRL_WDI 0x0002 -#define CFG_FPGA_CTRL_PS2_RESET 0x0020 - -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CFG_GPIO0_OSRH 0x40000550 -#define CFG_GPIO0_OSRL 0x00000110 -#define CFG_GPIO0_ISR1H 0x00000000 -#define CFG_GPIO0_ISR1L 0x15555445 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FE0014 - -#define CFG_DUART_RST (0x80000000 >> 14) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/PM520.h b/include/configs/PM520.h deleted file mode 100644 index 9f1dec8..0000000 --- a/include/configs/PM520.h +++ /dev/null @@ -1,384 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_PM520 1 /* ... on PM520 board */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ - -#define CONFIG_MISC_INIT_R - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_NET_MULTI 1 -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#undef CONFIG_NS8382X - -#define ADD_PCI_CMD CFG_CMD_PCI - -#else /* MPC5100 */ - -#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - -#endif - -/* Partitions */ -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 1 -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 -#endif - -#if defined(CONFIG_BOOT_ROM) -#define ADD_DOC_CMD 0 -#else -#define ADD_DOC_CMD CFG_CMD_DOC -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_DOC_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=pm520\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk30/ppc_82xx\0" \ - "bootfile=/tftpboot/PM520/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if defined(CONFIG_MPC5200) -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ -#endif -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* - * Disk-On-Chip configuration - */ - -#define CFG_DOC_SHORT_TIMEOUT -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM -#define CFG_DOC_BASE 0xE0000000 -#define CFG_DOC_SIZE 0x00100000 - -#if defined(CONFIG_BOOT_ROM) -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 32 MB - * 0xFD000000 for 16 MB - * 0xFD800000 for 8 MB - */ -#define CFG_FLASH_BASE 0xfc000000 -#define CFG_FLASH_SIZE 0x02000000 -#define CFG_BOOTROM_BASE 0xFFF00000 -#define CFG_BOOTROM_SIZE 0x00080000 -#define CFG_ENV_ADDR (0xFDF00000 + 0x40000) -#else -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CFG_FLASH_BASE 0xfe000000 -#define CFG_FLASH_SIZE 0x02000000 -#define CFG_ENV_ADDR (0xFFF00000 + 0x40000) -#endif -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ - -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */ - - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CFG_MBAR 0xf0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#define CFG_GPS_PORT_CONFIG 0x10000004 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#if defined(CONFIG_BOOT_ROM) -#define CFG_BOOTCS_START CFG_BOOTROM_BASE -#define CFG_BOOTCS_SIZE CFG_BOOTROM_SIZE -#define CFG_BOOTCS_CFG 0x00047800 -#define CFG_CS0_START CFG_BOOTROM_BASE -#define CFG_CS0_SIZE CFG_BOOTROM_SIZE -#define CFG_CS1_START CFG_FLASH_BASE -#define CFG_CS1_SIZE CFG_FLASH_SIZE -#define CFG_CS1_CFG 0x0004fb00 -#else -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x0004fb00 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE -#define CFG_CS1_START CFG_DOC_BASE -#define CFG_CS1_SIZE CFG_DOC_SIZE -#define CFG_CS1_CFG 0x00047800 -#endif - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#undef CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/PM826.h b/include/configs/PM826.h deleted file mode 100644 index 6e5e3bb..0000000 --- a/include/configs/PM826.h +++ /dev/null @@ -1,576 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef CFG_RAMBOOT - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ -#define CONFIG_PM826 1 /* ...on a PM8260 module */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -# define CFG_I2C_SPEED 50000 -# define CFG_I2C_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ - -/* - * select ethernet configuration - * - * if CONFIG_ETHER_ON_SCC is selected, then - * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) - * - CONFIG_NET_MULTI must not be defined - * - * if CONFIG_ETHER_ON_FCC is selected, then - * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected - * - CONFIG_NET_MULTI must be defined - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#define CONFIG_NET_MULTI -#undef CONFIG_ETHER_NONE /* define if ether on something else */ - -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ - -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -/* - * - Rx-CLK is CLK11 - * - Tx-CLK is CLK10 - */ -#define CONFIG_ETHER_ON_FCC1 -# define CFG_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -#ifndef CONFIG_DB_CR826_J30x_ON -# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) -#else -# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) -#endif -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK14 - */ -#define CONFIG_ETHER_ON_FCC2 -# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -/* - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 64000000 /* in Hz */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#ifdef CONFIG_PCI -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) -#else /* ! PCI */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#endif /* CONFIG_PCI */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Disk-On-Chip configuration - */ - -#define CFG_DOC_SHORT_TIMEOUT -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash and Boot ROM mapping - */ -#ifdef CONFIG_FLASH_32MB -#define CFG_FLASH0_BASE 0x40000000 -#define CFG_FLASH0_SIZE 0x02000000 -#else -#define CFG_FLASH0_BASE 0xFF000000 -#define CFG_FLASH0_SIZE 0x00800000 -#endif -#define CFG_BOOTROM_BASE 0xFF800000 -#define CFG_BOOTROM_SIZE 0x00080000 -#define CFG_DOC_BASE 0xFF800000 -#define CFG_DOC_SIZE 0x00100000 - -/* Flash bank size (for preliminary settings) - */ -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#ifdef CONFIG_FLASH_32MB -#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */ -#else -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#endif -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to EEPROM later */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) -#define CFG_ENV_SIZE 0x40000 -#define CFG_ENV_SECT_SIZE 0x40000 -#else -/* Final version: environment in EEPROM */ -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_ENV_OFFSET 512 -#define CFG_ENV_SIZE (2048 - 512) -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#if defined(CONFIG_BOOT_ROM) -#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#else -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#endif - -/* no slaves so just fill with zeros */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#ifdef CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ - -#define BCR_APD01 0x10000000 -#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) -#else -#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CFG_SCCR (SCCR_DFBRG00) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CFG_INIT_LOCAL_SDRAM - - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CFG_MIN_AM_MASK 0xC0000000 - -/* - * we use the same values for 32 MB and 128 MB SDRAM - * refresh rate = 7.73 uS (64 MHz Bus Clock) - */ -#define CFG_MPTPR 0x2000 -#define CFG_PSRT 0x0E - -#define CFG_MRS_OFFS 0x00000000 - - -#if defined(CONFIG_BOOT_ROM) -/* - * Bank 0 - Boot ROM (8 bit wide) - */ -#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Flash (64 bit wide) - */ -#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#else /* ! CONFIG_BOOT_ROM */ - -/* - * Bank 0 - Flash (64 bit wide) - */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Disk-On-Chip - */ -#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#endif /* CONFIG_BOOT_ROM */ - -/* Bank 2 - SDRAM - */ - -#ifndef CFG_RAMBOOT -#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - - /* SDRAM initialization values for 8-column chips - */ -#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CFG_OR2_PRELIM CFG_OR2_9COL -#define CFG_PSDMR CFG_PSDMR_9COL - -#endif /* CFG_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/PM828.h b/include/configs/PM828.h deleted file mode 100644 index 982a1f8..0000000 --- a/include/configs/PM828.h +++ /dev/null @@ -1,570 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef CFG_RAMBOOT - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ -#define CONFIG_PM828 1 /* ...on a PM828 module */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -# define CFG_I2C_SPEED 50000 -# define CFG_I2C_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ - -/* - * select ethernet configuration - * - * if CONFIG_ETHER_ON_SCC is selected, then - * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) - * - CONFIG_NET_MULTI must not be defined - * - * if CONFIG_ETHER_ON_FCC is selected, then - * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected - * - CONFIG_NET_MULTI must be defined - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#define CONFIG_NET_MULTI -#undef CONFIG_ETHER_NONE /* define if ether on something else */ - -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ - -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -/* - * - Rx-CLK is CLK11 - * - Tx-CLK is CLK10 - */ -#define CONFIG_ETHER_ON_FCC1 -# define CFG_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -#ifndef CONFIG_DB_CR826_J30x_ON -# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) -#else -# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) -#endif -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK14 - */ -#define CONFIG_ETHER_ON_FCC2 -# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -/* - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#ifdef CONFIG_PCI -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) -#else /* ! PCI */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#endif /* CONFIG_PCI */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Disk-On-Chip configuration - */ - -#define CFG_DOC_SHORT_TIMEOUT -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash and Boot ROM mapping - */ - -#define CFG_BOOTROM_BASE 0xFF800000 -#define CFG_BOOTROM_SIZE 0x00080000 -#define CFG_FLASH0_BASE 0x40000000 -#define CFG_FLASH0_SIZE 0x02000000 -#define CFG_DOC_BASE 0xFF800000 -#define CFG_DOC_SIZE 0x00100000 - - -/* Flash bank size (for preliminary settings) - */ -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to EEPROM later */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) -#define CFG_ENV_SIZE 0x40000 -#define CFG_ENV_SECT_SIZE 0x40000 -#else -/* Final version: environment in EEPROM */ -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_ENV_OFFSET 512 -#define CFG_ENV_SIZE (2048 - 512) -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#if defined(CONFIG_BOOT_ROM) -#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#else -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) -#endif - -/* no slaves so just fill with zeros */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#ifdef CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ - -#define BCR_APD01 0x10000000 -#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) -#else -#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CFG_SCCR (SCCR_DFBRG00) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CFG_INIT_LOCAL_SDRAM - - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CFG_MIN_AM_MASK 0xC0000000 - -/* - * we use the same values for 32 MB and 128 MB SDRAM - * refresh rate = 7.68 uS (100 MHz Bus Clock) - */ -#define CFG_MPTPR 0x2000 -#define CFG_PSRT 0x16 - -#define CFG_MRS_OFFS 0x00000000 - - -#if defined(CONFIG_BOOT_ROM) -/* - * Bank 0 - Boot ROM (8 bit wide) - */ -#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Flash (64 bit wide) - */ -#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#else /* ! CONFIG_BOOT_ROM */ - -/* - * Bank 0 - Flash (64 bit wide) - */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -/* - * Bank 1 - Disk-On-Chip - */ -#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - -#endif /* CONFIG_BOOT_ROM */ - -/* Bank 2 - SDRAM - */ - -#ifndef CFG_RAMBOOT -#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - - /* SDRAM initialization values for 8-column chips - */ -#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CFG_OR2_PRELIM CFG_OR2_9COL -#define CFG_PSDMR CFG_PSDMR_9COL - -#endif /* CFG_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/PM854.h b/include/configs/PM854.h deleted file mode 100644 index da01186..0000000 --- a/include/configs/PM854.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * pm854 board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8540 1 /* MPC8540 specific */ -#define CONFIG_PM854 1 /* PM854 board specific */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF - - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif - - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */ - -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */ - #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ - #define CFG_DDR_CS0_CONFIG 0x80000102 - #define CFG_DDR_TIMING_1 0x47444321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ -#endif - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ - -#define CFG_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */ -#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */ - -#define CFG_OR0_PRELIM 0xfe006f67 /* 32 MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#define CONFIG_EEPRO100 -#define CONFIG_E1000 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#define FEC_PHY_ADDR 3 -#define FEC_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 - -#endif /* CONFIG_TSEC_ENET */ - - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_MII \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif -#endif - -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ -#define CONFIG_LOOPW - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:40:42:01:00:00 -#define CONFIG_ETH1ADDR 00:40:42:01:00:01 -#define CONFIG_ETH2ADDR 00:40:42:01:00:02 -#endif - - -#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx -#define CONFIG_BOOTFILE pm854/uImage - -#define CONFIG_HOSTNAME pm854 -#define CONFIG_IPADDR 192.168.0.103 -#define CONFIG_SERVERIP 192.168.0.64 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=pm854/uRamdisk\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h deleted file mode 100644 index 4d83487..0000000 --- a/include/configs/PM856.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MicroSys PM856 board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8560 1 /* MPC8560 specific */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ -#define CONFIG_PM856 1 /* PM856 board specific */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE -#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ -#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF - - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif - - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */ - -#else - /* - * Manually set up DDR parameters - */ - #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */ - #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ - #define CFG_DDR_CS0_CONFIG 0x80000102 - #define CFG_DDR_TIMING_1 0x47444321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ -#endif - - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ - -#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ -#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */ - -#define CFG_OR0_PRELIM 0xfe006f67 /* 32MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#endif /* CONFIG_TSEC_ENET */ - -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ - - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ -#define CONFIG_ETHER_ON_FCC3 -#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) -#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE) - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif -#endif - -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ -#define CONFIG_LOOPW - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_ETHADDR 00:40:42:01:00:00 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:40:42:01:00:01 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:40:42:01:00:02 -#endif - - -#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx -#define CONFIG_BOOTFILE pm856/uImage - -#define CONFIG_HOSTNAME pm856 -#define CONFIG_IPADDR 192.168.0.103 -#define CONFIG_SERVERIP 192.168.0.64 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=pm856/uRamdisk\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h deleted file mode 100644 index 8bcab0b..0000000 --- a/include/configs/PMC405.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PMC405 1 /* ...on a PMC405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_I2C | \ - CFG_CMD_PING | \ - CFG_CMD_UNIVERSE | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_LOOPW 1 /* enable loopw command */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MONITOR_BASE 0xFFFC0000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_INCREMENT 0x01000000 - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_PROTECTION 1 /* don't use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_FLASH_INCREMENT } -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* - * JFFS2 partitions - second bank contains u-boot - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0x01b00000 -#define CONFIG_JFFS2_PART_OFFSET 0x00400000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=pmc405-0" -#define MTDPARTS_DEFAULT "mtdparts=pmc405-0:-(jffs2)" -*/ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ -#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ -#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 2 (CAN0, 1, RTC) initialization */ -#define CFG_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ -#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */ -#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ - -#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/PN62.h b/include/configs/PN62.h deleted file mode 100644 index a717659..0000000 --- a/include/configs/PN62.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_PN62 1 - -#define CONFIG_CONS_INDEX 1 - - -#define REMOVE_COMMANDS ( CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_LOADS | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMLS ) - -#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~REMOVE_COMMANDS) |\ - CFG_CMD_PCI |\ - CFG_CMD_BSP) - -#define CONFIG_BAUDRATE 19200 /* console baudrate */ - -#define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_SERVERIP 10.0.0.201 -#define CONFIG_IPADDR 10.0.0.200 -#define CONFIG_ROOTPATH /opt/eldk/ppc_82xx -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_BOOTARGS -#if 0 -/* Boot Linux with NFS root filesystem */ -#define CONFIG_BOOTCOMMAND \ - "setenv verify y;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ - "loadp 100000; bootm" - /* "tftpboot 100000 uImage; bootm" */ -#else -/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */ -#define CONFIG_BOOTCOMMAND \ - "setenv verify n;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ - "root=/dev/ram rw " \ - "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ - "loadp 200000; bootm" -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */ - -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ - -#define CONFIG_HAS_ETH1 1 /* add support for eth1addr */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* we need Plug 'n Play */ -#if 0 -#define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */ -#endif - -/* - * Networking stuff - */ -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */ -#define CONFIG_PCNET_79C973 - -#define _IO_BASE 0xfe000000 /* points to PCI I/O space */ - - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x10000000 - -#define CFG_RESET_ADDRESS 0xfff00100 - -#undef CFG_RAMBOOT -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE TEXT_BASE - -/*#define CFG_GBL_DATA_SIZE 256*/ -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - - -#define CFG_NO_FLASH 1 /* There is no FLASH memory */ - -#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */ - -/* - * Serial port configuration - */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK 1843200 - -#define CFG_NS16550_COM1 0xff800008 -#define CFG_NS16550_COM2 0xff800000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 - -#define CFG_EUMB_ADDR 0xFCE00000 - -/* MCCR1 */ -#define CFG_ROMNAL 3 /* rom/flash next access time */ -#define CFG_ROMFAL 7 /* rom/flash access time */ - -/* MCCR2 */ -#define CFG_ASRISE 6 /* ASRISE in clocks */ -#define CFG_ASFALL 12 /* ASFALL in clocks */ -#define CFG_REFINT 5600 /* REFINT in clocks */ - -/* MCCR3 */ -#define CFG_BSTOPRE 0x3cf /* Burst To Precharge */ -#define CFG_REFREC 2 /* Refresh to activate interval */ -#define CFG_RDLAT 3 /* data latency from read command */ - -/* MCCR4 */ -#define CFG_PRETOACT 1 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 3 /* Activate to Precharge interval */ -#define CFG_ACTORW 2 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ -#define CFG_SDMODE_WRAP 0 /* SDMODE Wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ -#define CFG_REGISTERD_TYPE_BUFFER 1 - -/* Memory bank settings: - * - * only bits 20-29 are actually used from these vales to set the - * start/qend address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x00000000 -#define CFG_BANK1_END 0x00000000 -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x00000000 -#define CFG_BANK2_END 0x00000000 -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x00000000 -#define CFG_BANK3_END 0x00000000 -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 - -/* - * Memory bank enable bitmask, specifying which of the banks defined above - * are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CFG_BANK_ENABLE 0x01 - -#define CFG_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -/* PCI memory space */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h deleted file mode 100644 index 7ca827f..0000000 --- a/include/configs/PPChameleonEVB.h +++ /dev/null @@ -1,810 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2003 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * Credits: Stefan Roese, Wolfgang Denk - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */ -#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */ -#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */ -#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL -#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA -#endif - - -/* Only one of the following two symbols must be defined (default is 25 MHz) - * CONFIG_PPCHAMELEON_CLK_25 - * CONFIG_PPCHAMELEON_CLK_33 - */ -#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33)) -#define CONFIG_PPCHAMELEON_CLK_25 -#endif - -#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) -#error "* Two external frequencies (SysClk) are defined! *" -#endif - -#undef CONFIG_PPCHAMELEON_SMI712 - -/* - * Debug stuff - */ -#undef __DEBUG_START_FROM_SRAM__ -#define __DISABLE_MACHINE_EXCEPTION__ - -#ifdef __DEBUG_START_FROM_SRAM__ -#define CFG_DUMMY_FLASH_SIZE 1024*1024*4 -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) -# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#else -# error "* External frequency (SysClk) not defined! *" -#endif - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#undef CONFIG_BOOTARGS - -/* Ethernet stuff */ -#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ -#define CONFIG_ETHADDR 00:50:c2:1e:af:fe -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_EXT_PHY -#define CONFIG_NET_MULTI 1 - -#define CONFIG_MII 1 /* MII PHY management */ -#ifndef CONFIG_EXT_PHY -#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */ -#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ -#else -#define CONFIG_PHY_ADDR 2 /* PHY address */ -#endif -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */ -#define CFG_I2C_RTC_ADDR 0x68 -#define CFG_M41T11_BASE_YEAR 1900 - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CFG_NAND0_BASE 0xFF400000 -#define CFG_NAND1_BASE 0xFF000000 - -#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define SECTORSIZE 512 -#define NAND_NO_RB - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */ -#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */ -#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ -#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ - -#define NAND_DISABLE_CE(nand) do \ -{ \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define NAND_ENABLE_CE(nand) do \ -{ \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \ - break; \ - } \ -} while(0) - -#define NAND_CTL_CLRALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define NAND_CTL_SETALE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \ - break; \ - } \ -} while(0) - -#define NAND_CTL_CLRCLE(nandptr) do \ -{ \ - switch((unsigned long)nandptr) \ - { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#define NAND_CTL_SETCLE(nandptr) do { \ - switch((unsigned long)nandptr) { \ - case CFG_NAND0_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ - break; \ - case CFG_NAND1_BASE: \ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \ - break; \ - } \ -} while(0) - -#ifdef NAND_NO_RB -/* constant delay (see also tR in the datasheet) */ -#define NAND_WAIT_READY(nand) do { \ - udelay(12); \ -} while (0) -#else -/* use the R/B pin */ -/* TBD */ -#endif - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ - -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -/* Reserve 256 kB for Monitor */ -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) - -/* Reserve 320 kB for Monitor */ -/* -#define CFG_FLASH_BASE 0xFFFB0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (320 * 1024) -*/ - -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#ifdef ENVIRONMENT_IN_EEPROM - -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/ - -#else /* DEFAULT: environment in flash, using redundand flash sectors */ - -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ -#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ -#define CFG_ENV_ADDR_REDUND 0xFFFFA000 -#define CFG_ENV_SIZE_REDUND 0x2000 - -#endif /* ENVIRONMENT_IN_EEPROM */ - - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (External SRAM) initialization */ -/* Since this must replace NOR Flash, we use the same settings for CS0 */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */ -#define CFG_EBC_PB2AP 0x92015480 -#define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */ -#define CFG_EBC_PB3AP 0x92015480 -#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ - -#ifdef CONFIG_PPCHAMELEON_SMI712 -/* - * Video console (graphic: SMI LynxEM) - */ -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_VIDEO_LOGO -/*#define CONFIG_VIDEO_BMP_LOGO*/ -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ -#define CFG_ISA_IO 0xE8000000 -/* see also drivers/videomodes.c */ -#define CFG_DEFAULT_VIDEO_MODE 0x303 -#endif - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -/* FPGA internal regs */ -#define CFG_FPGA_MODE 0x00 -#define CFG_FPGA_STATUS 0x02 -#define CFG_FPGA_TS 0x04 -#define CFG_FPGA_TS_LOW 0x06 -#define CFG_FPGA_TS_CAP0 0x10 -#define CFG_FPGA_TS_CAP0_LOW 0x12 -#define CFG_FPGA_TS_CAP1 0x14 -#define CFG_FPGA_TS_CAP1_LOW 0x16 -#define CFG_FPGA_TS_CAP2 0x18 -#define CFG_FPGA_TS_CAP2_LOW 0x1a -#define CFG_FPGA_TS_CAP3 0x1c -#define CFG_FPGA_TS_CAP3_LOW 0x1e - -/* FPGA Mode Reg */ -#define CFG_FPGA_MODE_CF_RESET 0x0001 -#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100 -#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000 -#define CFG_FPGA_MODE_TS_CLEAR 0x2000 - -/* FPGA Status Reg */ -#define CFG_FPGA_STATUS_DIP0 0x0001 -#define CFG_FPGA_STATUS_DIP1 0x0002 -#define CFG_FPGA_STATUS_DIP2 0x0004 -#define CFG_FPGA_STATUS_FLASH 0x0008 -#define CFG_FPGA_STATUS_TS_IRQ 0x1000 - -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30] - EMAC0 input - * GPIO0[31] - EMAC1 reject packet as output - */ -#define CFG_GPIO0_OSRH 0x40000550 -#define CFG_GPIO0_OSRL 0x00000110 -#define CFG_GPIO0_ISR1H 0x00000000 -/*#define CFG_GPIO0_ISR1L 0x15555445*/ -#define CFG_GPIO0_ISR1L 0x15555444 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FF8014 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#define CONFIG_NO_SERIAL_EEPROM - -/*--------------------------------------------------------------------*/ - -#ifdef CONFIG_NO_SERIAL_EEPROM - -/* -!----------------------------------------------------------------------- -! Defines for entry options. -! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that -! are plugged in the board will be utilized as non-ECC DIMMs. -!----------------------------------------------------------------------- -*/ -#undef AUTO_MEMORY_CONFIG -#define DIMM_READ_ADDR 0xAB -#define DIMM_WRITE_ADDR 0xAA - -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -#ifdef CONFIG_PPCHAMELEON_CLK_25 -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) - -/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ -#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#else -#error "* External frequency (SysClk) not defined! *" -#endif - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -/* Model HI */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 -#define CFG_OPB_FREQ 55555555 -/* Model ME */ -#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 -#define CFG_OPB_FREQ 66666666 -#else -/* Model BA (default) */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 -#define CFG_OPB_FREQ 66666666 -#endif - -#endif /* CONFIG_NO_SERIAL_EEPROM */ - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00400000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand" -*/ - -/* 256 kB U-boot image */ -/* -#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ - "1792k(user),256k(u-boot);" \ - "ppchameleonevb-nand:-(nand)" -*/ - -/* 320 kB U-boot image */ -/* -#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \ - "1728k(user),320k(u-boot);" \ - "ppchameleonevb-nand:-(nand)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/QS823.h b/include/configs/QS823.h deleted file mode 100644 index 235bc48..0000000 --- a/include/configs/QS823.h +++ /dev/null @@ -1,571 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* various debug settings */ -#undef CFG_DEVICE_NULLDEV /* null device */ -#undef CONFIG_SILENT_CONSOLE /* silent console */ -#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ -#undef DEBUG /* debug output code */ -#undef DEBUG_FLASH /* debug flash code */ -#undef FLASH_DEBUG /* debug fash code */ -#undef DEBUG_ENV /* debug environment code */ - -#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ -#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_QS823 1 /* ...on a QS823 module */ -#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ - -/* Select the target clock speed */ -#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ -#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ -#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ -#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ -#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ - -#ifdef CONFIG_CLOCK_16MHZ -#define CONFIG_CLOCK_MULT 512 -#endif - -#ifdef CONFIG_CLOCK_33MHZ -#define CONFIG_CLOCK_MULT 1024 -#endif - -#ifdef CONFIG_CLOCK_50MHZ -#define CONFIG_CLOCK_MULT 1525 -#endif - -#ifdef CONFIG_CLOCK_66MHZ -#define CONFIG_CLOCK_MULT 2048 -#endif - -#ifdef CONFIG_CLOCK_80MHZ -#define CONFIG_CLOCK_MULT 2441 -#endif - -/* choose flash size, 4Mb or 8Mb */ -#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ -#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ - -#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ - -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ - -/* Define default IP addresses */ -#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ -#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ - -/* message to say directly after booting */ -#define CONFIG_PREBOOT "echo '';" \ - "echo 'type:';" \ - "echo 'run boot_nfs to boot to NFS';" \ - "echo 'run boot_flash to boot to flash';" \ - "echo '';" \ - "echo 'run flash_rootfs to install a new rootfs';" \ - "echo 'run flash_env to clear the env sector';" \ - "echo 'run flash_rw to clear the rw fs';" \ - "echo 'run flash_uboot to install a new u-boot';" \ - "echo 'run flash_kernel to install a new kernel';" - -/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTCOMMAND "run boot_nfs" - -#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ - -/* Our flash filesystem looks like this - * - * 4Mb board: - * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) - * ffec 0000 - ffed ffff read-write filesystem (ext2) - * ffee 0000 - ffef ffff environment - * fff0 0000 - fff1 ffff u-boot - * fff2 0000 - ffff ffff linux kernel - * - * 8Mb board: - * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) - * ffec 0000 - ffed ffff read-write filesystem (ext2) - * ffee 0000 - ffef ffff environment - * fff0 0000 - fff1 ffff u-boot - * fff2 0000 - ffff ffff linux kernel - * - */ - -/* environment for 4Mb board */ -#ifdef CONFIG_FLASH_4MB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=QS823\0" \ - "hostname=qs823\0" \ - "netdev=eth0\0" \ - "ethaddr=00:01:02:B4:36:56\0" \ - "rootpath=/exports/rootfs\0" \ - "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ - /* fill in variables */ \ - "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ - "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ - "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ - /* commands */ \ - "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ - "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ - /* reinstall flash parts */ \ - "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \ - "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ - "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ - "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \ - "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" -#endif /* CONFIG_FLASH_4MB */ - -/* environment for 8Mb board */ -#ifdef CONFIG_FLASH_8MB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=QS823\0" \ - "hostname=qs823\0" \ - "netdev=eth0\0" \ - "ethaddr=00:01:02:B4:36:56\0" \ - "rootpath=/exports/rootfs\0" \ - "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ - /* fill in variables */ \ - "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ - "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ - "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ - /* commands */ \ - "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ - "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ - /* reinstall flash parts */ \ - "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \ - "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ - "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ - "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \ - "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" -#endif /* CONFIG_FLASH_8MB */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_STATUS_LED /* Status LED disabled */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CONSOLE | \ - CFG_CMD_DATE | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_RUN) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------- - * Environment variable storage is in FLASH, one sector before U-boot - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ -#define CFG_ENV_SIZE 0x2000 /* 8kb */ -#define CFG_ENV_ADDR 0xffee0000 /* address of env sector */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#define CFG_PROMPT_HUSH_PS2 "> " - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ - -#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ -#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MONITOR_BASE 0xFFF00000 /* U-boot location */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * TODO flash parameters - * FLASH organization for Intel Strataflash - */ -#undef CFG_FLASH_16BIT /* 32-bit wide flash memory */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ - -#ifdef CONFIG_WATCHDOG -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - */ - -/* MF (Multiplication Factor of SPLL) */ -/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */ -#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) -#define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) -#define CFG_BRGCLK_PRESCALE 1 -#endif - -#if defined(CONFIG_CLOCK_66MHZ) -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) -#define CFG_BRGCLK_PRESCALE 4 -#endif - -#if defined(CONFIG_CLOCK_80MHZ) -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) -#define CFG_BRGCLK_PRESCALE 4 -#endif - -#define SCCR_MASK CFG_SCCR - -/*----------------------------------------------------------------------- - * Debug Enable Register - * 0x73E67C0F - All interrupts handled by BDM - * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM - *----------------------------------------------------------------------- -#define CFG_DER 0x73E67C0F -#define CFG_DER 0x0082400F - - #------------------------------------------------------------------------- - # Program the Debug Enable Register (DER). This register provides the user - # with the reason for entering into the debug mode. We want all conditions - # to end up as an exception. We don't want to enter into debug mode for - # any condition. See the back of of the Development Support section of the - # MPC860 User Manual for a description of this register. - #------------------------------------------------------------------------- -*/ -#define CFG_DER 0 - -/*----------------------------------------------------------------------- - * Memory Controller Initialization Constants - *----------------------------------------------------------------------- - */ - -/* - * BR0 and OR0 (AMD dual FLASH devices) - * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) - */ -#define CFG_PRELIM_OR_AM -#define CFG_OR_TIMING_FLASH - -/* - *----------------------------------------------------------------------- - * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) - * flash that resides on the QS823. - *----------------------------------------------------------------------- - */ - -/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ -/* represents a minumum 32K block size. */ -#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) -#define CFG_BR0_PRELIM (vBR0_BA | BR_V) - -/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ -/* which defines a 8 Mbyte memory block. */ -#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) - -#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) -/* 0101 = Add a 5 clock cycle wait state */ -#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) -#endif - -#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) -/* 0011 = Add a 3 clock cycle wait state */ -/* 29.8ns clock * (3 + 2) = 149ns cycle time */ -#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) -#endif - -#if defined(CONFIG_CLOCK_16MHZ) -/* 0010 = Add a 2 clock cycle wait state */ -#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) -#endif - -/* - * BR1 and OR1 (SDRAM) - * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) - * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) - * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) - * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) - */ - -#define SDRAM_BASE 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ - -/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which - * represents a 128 Mbyte block the DRAM in - * this address base. - */ -#define vOR1_AM ((0xF800 << 16) + (0 << 15)) -#define vBR1_BA ((0x0000 << 16) + (0 << 15)) -#define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) -#define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) - -/* Machine A Mode Register */ - -/* PTA Periodic Timer A */ - -#if defined(CONFIG_CLOCK_80MHZ) -#define vMAMR_PTA (19 << 24) -#endif - -#if defined(CONFIG_CLOCK_66MHZ) -#define vMAMR_PTA (16 << 24) -#endif - -#if defined(CONFIG_CLOCK_50MHZ) -#define vMAMR_PTA (195 << 24) -#endif - -#if defined(CONFIG_CLOCK_33MHZ) -#define vMAMR_PTA (131 << 24) -#endif - -#if defined(CONFIG_CLOCK_16MHZ) -#define vMAMR_PTA (65 << 24) -#endif - -/* For boards with 16M of SDRAM */ -#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ -MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* For boards with 32M of SDRAM */ -#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ -#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ -MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* Memory Periodic Timer Prescaler Register */ - -#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) -/* Divide by 32 */ -#define CFG_MPTPR 0x02 -#endif - -#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) -/* Divide by 16 */ -#define CFG_MPTPR 0x04 -#endif - -/* - * BR2 and OR2 (Unused) - * Base address = 0xF020_0000 - 0xF020_0FFF - * - */ -#define CFG_OR2_PRELIM 0xFFF00000 -#define CFG_BR2_PRELIM 0xF0200000 - -/* - * BR3 and OR3 (External Bus CS3) - * Base address = 0xF030_0000 - 0xF030_0FFF - * - */ -#define CFG_OR3_PRELIM 0xFFF00000 -#define CFG_BR3_PRELIM 0xF0300000 - -/* - * BR4 and OR4 (External Bus CS3) - * Base address = 0xF040_0000 - 0xF040_0FFF - * - */ -#define CFG_OR4_PRELIM 0xFFF00000 -#define CFG_BR4_PRELIM 0xF0400000 - - -/* - * BR4 and OR4 (External Bus CS3) - * Base address = 0xF050_0000 - 0xF050_0FFF - * - */ -#define CFG_OR5_PRELIM 0xFFF00000 -#define CFG_BR5_PRELIM 0xF0500000 - -/* - * BR6 and OR6 (Unused) - * Base address = 0xF060_0000 - 0xF060_0FFF - * - */ -#define CFG_OR6_PRELIM 0xFFF00000 -#define CFG_BR6_PRELIM 0xF0600000 - -/* - * BR7 and OR7 (Unused) - * Base address = 0xF070_0000 - 0xF070_0FFF - * - */ -#define CFG_OR7_PRELIM 0xFFF00000 -#define CFG_BR7_PRELIM 0xF0700000 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Sanity checks - */ -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/QS850.h b/include/configs/QS850.h deleted file mode 100644 index 967582b..0000000 --- a/include/configs/QS850.h +++ /dev/null @@ -1,571 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* various debug settings */ -#undef CFG_DEVICE_NULLDEV /* null device */ -#undef CONFIG_SILENT_CONSOLE /* silent console */ -#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ -#undef DEBUG /* debug output code */ -#undef DEBUG_FLASH /* debug flash code */ -#undef FLASH_DEBUG /* debug fash code */ -#undef DEBUG_ENV /* debug environment code */ - -#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ -#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_QS850 1 /* ...on a QS850 module */ -#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ - -/* Select the target clock speed */ -#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ -#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ -#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ -#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ -#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ - -#ifdef CONFIG_CLOCK_16MHZ -#define CONFIG_CLOCK_MULT 512 -#endif - -#ifdef CONFIG_CLOCK_33MHZ -#define CONFIG_CLOCK_MULT 1024 -#endif - -#ifdef CONFIG_CLOCK_50MHZ -#define CONFIG_CLOCK_MULT 1525 -#endif - -#ifdef CONFIG_CLOCK_66MHZ -#define CONFIG_CLOCK_MULT 2048 -#endif - -#ifdef CONFIG_CLOCK_80MHZ -#define CONFIG_CLOCK_MULT 2441 -#endif - -/* choose flash size, 4Mb or 8Mb */ -#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ -#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ - -#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ - -/* Define default IP addresses */ -#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ -#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ - -/* message to say directly after booting */ -#define CONFIG_PREBOOT "echo '';" \ - "echo 'type:';" \ - "echo 'run boot_nfs to boot to NFS';" \ - "echo 'run boot_flash to boot to flash';" \ - "echo '';" \ - "echo 'run flash_rootfs to install a new rootfs';" \ - "echo 'run flash_env to clear the env sector';" \ - "echo 'run flash_rw to clear the rw fs';" \ - "echo 'run flash_uboot to install a new u-boot';" \ - "echo 'run flash_kernel to install a new kernel';" - -/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTCOMMAND "run boot_nfs" - -#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ - -/* Our flash filesystem looks like this - * - * 4Mb board: - * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) - * ffec 0000 - ffed ffff read-write filesystem (ext2) - * ffee 0000 - ffef ffff environment - * fff0 0000 - fff1 ffff u-boot - * fff2 0000 - ffff ffff linux kernel - * - * 8Mb board: - * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) - * ffec 0000 - ffed ffff read-write filesystem (ext2) - * ffee 0000 - ffef ffff environment - * fff0 0000 - fff1 ffff u-boot - * fff2 0000 - ffff ffff linux kernel - * - */ - -/* environment for 4Mb board */ -#ifdef CONFIG_FLASH_4MB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=QS850\0" \ - "hostname=qs850\0" \ - "netdev=eth0\0" \ - "ethaddr=00:01:02:B4:36:56\0" \ - "rootpath=/exports/rootfs\0" \ - "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ - /* fill in variables */ \ - "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ - "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ - "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ - /* commands */ \ - "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ - "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ - /* reinstall flash parts */ \ - "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \ - "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ - "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ - "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \ - "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" -#endif /* CONFIG_FLASH_4MB */ - -/* environment for 8Mb board */ -#ifdef CONFIG_FLASH_8MB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=QS850\0" \ - "hostname=qs850\0" \ - "netdev=eth0\0" \ - "ethaddr=00:01:02:B4:36:56\0" \ - "rootpath=/exports/rootfs\0" \ - "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ - /* fill in variables */ \ - "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ - "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ - "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ - /* commands */ \ - "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ - "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ - /* reinstall flash parts */ \ - "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \ - "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ - "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ - "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \ - "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" -#endif /* CONFIG_FLASH_8MB */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_STATUS_LED /* Status LED disabled */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CONSOLE | \ - CFG_CMD_DATE | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_RUN) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------- - * Environment variable storage is in FLASH, one sector before U-boot - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ -#define CFG_ENV_SIZE 0x2000 /* 8kb */ -#define CFG_ENV_ADDR 0xffee0000 /* address of env sector */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#define CFG_PROMPT_HUSH_PS2 "> " - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ - -#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ -#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MONITOR_BASE 0xFFF00000 /* U-boot location */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * TODO flash parameters - * FLASH organization for Intel Strataflash - */ -#undef CFG_FLASH_16BIT /* 32-bit wide flash memory */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ - -#ifdef CONFIG_WATCHDOG -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - */ - -/* MF (Multiplication Factor of SPLL) */ -/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */ -#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) -#define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) -#define CFG_BRGCLK_PRESCALE 1 -#endif - -#if defined(CONFIG_CLOCK_66MHZ) -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) -#define CFG_BRGCLK_PRESCALE 4 -#endif - -#if defined(CONFIG_CLOCK_80MHZ) -#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) -#define CFG_BRGCLK_PRESCALE 4 -#endif - -#define SCCR_MASK CFG_SCCR - -/*----------------------------------------------------------------------- - * Debug Enable Register - * 0x73E67C0F - All interrupts handled by BDM - * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM - *----------------------------------------------------------------------- -#define CFG_DER 0x73E67C0F -#define CFG_DER 0x0082400F - - #------------------------------------------------------------------------- - # Program the Debug Enable Register (DER). This register provides the user - # with the reason for entering into the debug mode. We want all conditions - # to end up as an exception. We don't want to enter into debug mode for - # any condition. See the back of of the Development Support section of the - # MPC860 User Manual for a description of this register. - #------------------------------------------------------------------------- -*/ -#define CFG_DER 0 - -/*----------------------------------------------------------------------- - * Memory Controller Initialization Constants - *----------------------------------------------------------------------- - */ - -/* - * BR0 and OR0 (AMD dual FLASH devices) - * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) - */ -#define CFG_PRELIM_OR_AM -#define CFG_OR_TIMING_FLASH - -/* - *----------------------------------------------------------------------- - * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) - * flash that resides on the QS850. - *----------------------------------------------------------------------- - */ - -/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ -/* represents a minumum 32K block size. */ -#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) -#define CFG_BR0_PRELIM (vBR0_BA | BR_V) - -/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ -/* which defines a 8 Mbyte memory block. */ -#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) - -#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) -/* 0101 = Add a 5 clock cycle wait state */ -#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) -#endif - -#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) -/* 0011 = Add a 3 clock cycle wait state */ -/* 29.8ns clock * (3 + 2) = 149ns cycle time */ -#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) -#endif - -#if defined(CONFIG_CLOCK_16MHZ) -/* 0010 = Add a 2 clock cycle wait state */ -#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) -#endif - -/* - * BR1 and OR1 (SDRAM) - * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) - * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) - * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) - * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) - */ - -#define SDRAM_BASE 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ - -/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which - * represents a 128 Mbyte block the DRAM in - * this address base. - */ -#define vOR1_AM ((0xF800 << 16) + (0 << 15)) -#define vBR1_BA ((0x0000 << 16) + (0 << 15)) -#define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) -#define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) - -/* Machine A Mode Register */ - -/* PTA Periodic Timer A */ - -#if defined(CONFIG_CLOCK_80MHZ) -#define vMAMR_PTA (19 << 24) -#endif - -#if defined(CONFIG_CLOCK_66MHZ) -#define vMAMR_PTA (16 << 24) -#endif - -#if defined(CONFIG_CLOCK_50MHZ) -#define vMAMR_PTA (195 << 24) -#endif - -#if defined(CONFIG_CLOCK_33MHZ) -#define vMAMR_PTA (131 << 24) -#endif - -#if defined(CONFIG_CLOCK_16MHZ) -#define vMAMR_PTA (65 << 24) -#endif - -/* For boards with 16M of SDRAM */ -#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ -MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* For boards with 32M of SDRAM */ -#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ -#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ -MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* Memory Periodic Timer Prescaler Register */ - -#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) -/* Divide by 32 */ -#define CFG_MPTPR 0x02 -#endif - -#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) -/* Divide by 16 */ -#define CFG_MPTPR 0x04 -#endif - -/* - * BR2 and OR2 (Unused) - * Base address = 0xF020_0000 - 0xF020_0FFF - * - */ -#define CFG_OR2_PRELIM 0xFFF00000 -#define CFG_BR2_PRELIM 0xF0200000 - -/* - * BR3 and OR3 (External Bus CS3) - * Base address = 0xF030_0000 - 0xF030_0FFF - * - */ -#define CFG_OR3_PRELIM 0xFFF00000 -#define CFG_BR3_PRELIM 0xF0300000 - -/* - * BR4 and OR4 (External Bus CS3) - * Base address = 0xF040_0000 - 0xF040_0FFF - * - */ -#define CFG_OR4_PRELIM 0xFFF00000 -#define CFG_BR4_PRELIM 0xF0400000 - - -/* - * BR4 and OR4 (External Bus CS3) - * Base address = 0xF050_0000 - 0xF050_0FFF - * - */ -#define CFG_OR5_PRELIM 0xFFF00000 -#define CFG_BR5_PRELIM 0xF0500000 - -/* - * BR6 and OR6 (Unused) - * Base address = 0xF060_0000 - 0xF060_0FFF - * - */ -#define CFG_OR6_PRELIM 0xFFF00000 -#define CFG_BR6_PRELIM 0xF0600000 - -/* - * BR7 and OR7 (Unused) - * Base address = 0xF070_0000 - 0xF070_0FFF - * - */ -#define CFG_OR7_PRELIM 0xFFF00000 -#define CFG_BR7_PRELIM 0xF0700000 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Sanity checks - */ -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h deleted file mode 100644 index 32faa61..0000000 --- a/include/configs/QS860T.h +++ /dev/null @@ -1,410 +0,0 @@ -/* - * (C) Copyright 2003 - * MuLogic B.V. - * - * (C) Copyright 2002 - * Simple Network Magic Corporation - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* various debug settings */ -#undef CFG_DEVICE_NULLDEV /* null device */ -#undef CONFIG_SILENT_CONSOLE /* silent console */ -#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ -#undef DEBUG /* debug output code */ -#undef DEBUG_FLASH /* debug flash code */ -#undef FLASH_DEBUG /* debug fash code */ -#undef DEBUG_ENV /* debug environment code */ - -#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ -#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ - - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_QS860T 1 /* ...on a QS860T module */ - -#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */ -#define CONFIG_MII -#define FEC_INTERRUPT SIU_LEVEL1 -#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */ -#define CFG_DISCOVER_PHY - -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */ -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* Pass clocks to Linux 2.4.18 in Hz */ -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;" \ - "echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \ - "echo" - -#undef CONFIG_BOOTARGS -/* TODO compare against CADM860 */ -#define CONFIG_BOOTCOMMAND "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ASKENV | \ - CFG_CMD_NET | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - -/* TODO */ -#if 0 -/* Look at these */ -CONFIG_IPADDR -CONFIG_SERVERIP -CONFIG_I2C -CONFIG_SPI -#endif - -/* - * Environment variable storage is in NVRAM - */ -#define CFG_ENV_IS_IN_NVRAM 1 -#define CFG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */ -#define CFG_ENV_ADDR 0xD100E000 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#define CFG_PROMPT_HUSH_PS2 "> " - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* TODO - size? */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF00000 - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* TODO flash parameters */ -/*----------------------------------------------------------------------- - * FLASH organization for Intel Strataflash - */ -#define CFG_FLASH_16BIT 1 /* 16-bit wide flash memory */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#undef CFG_ENV_IS_IN_FLASH - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI) -#else -#define CFG_SYPCR 0xFFFFFF88 -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR 0x00620000 - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - */ -#define CFG_TBSCR 0x00C3 - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - */ -#define CFG_PISCR 0x0082 - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - */ -#define CFG_PLPRCR 0x0090D000 - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR 0x02000000 - - -/*----------------------------------------------------------------------- - * Debug Enable Register - * 0x73E67C0F - All interrupts handled by BDM - * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM - *----------------------------------------------------------------------- -#define CFG_DER 0x73E67C0F -*/ -#define CFG_DER 0x0082400F - - -/*----------------------------------------------------------------------- - * Memory Controller Initialization Constants - *----------------------------------------------------------------------- - */ - -/* - * BR0 and OR0 (AMD 512K Socketed FLASH) - * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) - */ -#define CFG_PRELIM_OR_AM -#define CFG_OR_TIMING_FLASH - -#define FLASH_BASE0_PRELIM 0xFFF00001 -#define CFG_OR0_PRELIM 0xFFF80D42 -#define CFG_BR0_PRELIM 0xFFF00401 - - -/* - * BR1 and OR1 (Intel 8M StrataFLASH) - * Base address = 0xD000_0000 - 0xD07F_FFFF - */ - -#define FLASH_BASE1_PRELIM 0xD0000000 -#define CFG_OR1_PRELIM 0xFF800D42 -#define CFG_BR1_PRELIM 0xD0000801 -/* #define CFG_OR1 0xFF800D42 */ -/* #define CFG_BR1 0xD0000801 */ - - -/* - * BR2 and OR2 (SDRAM) - * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) - * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) - * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) - * - */ -#define SDRAM_BASE 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ - -/* SDRAM timing */ -#define SDRAM_TIMING 0x00000A00 - -/* For boards with 16M of SDRAM */ -#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CFG_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */ - -/* For boards with 64M of SDRAM */ -#define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */ -/* TODO - determine real value */ -#define CFG_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */ - -#define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING) -#define CFG_BR2 (SDRAM_BASE | 0x000000C1) - - -/* - * BR3 and OR3 (NVRAM, Sipex, NAND Flash) - * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM) - * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register) - * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register) - * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register) - * - */ - -#define CFG_OR3_PRELIM 0xFFC00DF6 -#define CFG_BR3_PRELIM 0xD1000401 -/* #define CFG_OR3 0xFFC00DF6 */ -/* #define CFG_BR3 0xD1000401 */ - - -/* - * BR4 and OR4 (Unused) - * Base address = 0xE000_0000 - 0xE3FF_FFFF - * - */ - -#define CFG_OR4_PRELIM 0xFF000000 -#define CFG_BR4_PRELIM 0xE0000000 -/* #define CFG_OR4 0xFF000000 */ -/* #define CFG_BR4 0xE0000000 */ - - -/* - * BR5 and OR5 (Expansion bus) - * Base address = 0xE400_0000 - 0xE7FF_FFFF - * - */ - -#define CFG_OR5_PRELIM 0xFF000000 -#define CFG_BR5_PRELIM 0xE4000000 -/* #define CFG_OR5 0xFF000000 */ -/* #define CFG_BR5 0xE4000000 */ - - -/* - * BR6 and OR6 (Expansion bus) - * Base address = 0xE800_0000 - 0xEBFF_FFFF - * - */ - -#define CFG_OR6_PRELIM 0xFF000000 -#define CFG_BR6_PRELIM 0xE8000000 -/* #define CFG_OR6 0xFF000000 */ -/* #define CFG_BR6 0xE8000000 */ - - -/* - * BR7 and OR7 (Expansion bus) - * Base address = 0xEC00_0000 - 0xEFFF_FFFF - * - */ - -#define CFG_OR7_PRELIM 0xFF000000 -#define CFG_BR7_PRELIM 0xE8000000 -/* #define CFG_OR7 0xFF000000 */ -/* #define CFG_BR7 0xE8000000 */ - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Sanity checks - */ -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h deleted file mode 100644 index 82228c0..0000000 --- a/include/configs/R360MPI.h +++ /dev/null @@ -1,476 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_R360MPI 1 - -#define CONFIG_LCD -#undef CONFIG_EDT32F10 -#define CONFIG_SHARP_LQ057Q3DC02 - -#define CONFIG_SPLASH_SCREEN - -#define MPC8XX_FACT 1 /* Multiply by 1 */ -#define MPC8XX_XIN 50000000 /* 50 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate in bps */ -#if 0 -#define CONFIG_BOOTDELAY 0 /* immediate boot */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#undef CONFIG_SCC1_ENET -#define CONFIG_SCC2_ENET - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */ -#undef CONFIG_SORT_I2C /* To I2C with software support */ -#define CFG_I2C_SPEED 4700 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(50) - -#define CFG_I2C_LCD_ADDR 0x8 /* LCD Control */ -#define CFG_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */ -#define CFG_I2C_TEM_ADDR 0x49 /* Temperature Sensors */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NFS | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_DEVICE_NULLDEV 1 /* we need the null device */ -#define CFG_CONSOLE_IS_IN_ENV 1 /* must set console from env */ - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * JFFS2 partitions - */ -/* No command line, one static partition - * use all the space starting at offset 3MB*/ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00300000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=r360-0" -#define MTDPARTS_DEFAULT "mtdparts=r360-0:-@3m(user)" -*/ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ -#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)< ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ -#if defined(CONFIG_80MHz) -#define CFG_MAMR_PTA 156 -#elif defined(CONFIG_66MHz) -#define CFG_MAMR_PTA 129 -#else /* 50 MHz */ -#define CFG_MAMR_PTA 98 -#endif /*CONFIG_??MHz */ - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h deleted file mode 100644 index 242c837..0000000 --- a/include/configs/RBC823.h +++ /dev/null @@ -1,439 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Udi Finkelstein udif@udif.com - * For the RBC823 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_RBC823 1 /* ...on a RBC823 module */ - - -#if 0 -#define DEBUG 1 -#define CONFIG_LAST_STAGE_INIT -#endif -#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */ -#define CONFIG_LCD 1 /* use LCD controller ... */ -#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */ - -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_SMC1 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_8xx_GCLK_FREQ 48000000L - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#undef CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */ - -#define CONFIG_HARD_I2C -#define CFG_I2C_SPEED 40000 -#define CFG_I2C_SLAVE 0xfe -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_WRITE_BITS 4 -#define CFG_EEPROM_WRITE_DELAY_MS 10 - -#define CONFIG_COMMANDS ( CFG_CMD_ALL & \ - ~CFG_CMD_BSP & \ - ~CFG_CMD_DATE & \ - ~CFG_CMD_DISPLAY& \ - ~CFG_CMD_DTT & \ - ~CFG_CMD_EXT2 & \ - ~CFG_CMD_FDC & \ - ~CFG_CMD_FDOS & \ - ~CFG_CMD_HWFLOW & \ - ~CFG_CMD_IDE & \ - ~CFG_CMD_IRQ & \ - ~CFG_CMD_JFFS2 & \ - ~CFG_CMD_MII & \ - ~CFG_CMD_MMC & \ - ~CFG_CMD_NAND & \ - ~CFG_CMD_PCI & \ - ~CFG_CMD_PCMCIA & \ - ~CFG_CMD_REISER & \ - ~CFG_CMD_SCSI & \ - ~CFG_CMD_SETGETDCR & \ - ~CFG_CMD_SNTP & \ - ~CFG_CMD_SPI & \ - ~CFG_CMD_UNIVERSE & \ - ~CFG_CMD_USB & \ - ~CFG_CMD_VFD & \ - ~CFG_CMD_XIMG ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x0100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF00000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -/* -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -*/ -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -/* - * for 48 MHz, we use a 4 MHz clock * 12 - */ -#define CFG_PLPRCR \ - ( (12-1)< - -/* - * Miscellaneous configurable options - */ -#define CFG_RESET_ADDRESS 0x80000000 -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFA200000 - -/*----------------------------------------------------------------------------- - * I2C Configuration - *----------------------------------------------------------------------------- - */ -#define CONFIG_I2C 1 -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0x34 - - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000010) -#define I2C_TRISTATE (iop->pdir &= ~0x00000010) -#define I2C_READ ((iop->pdat & 0x00000010) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ - else iop->pdat &= ~0x00000010 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ - else iop->pdat &= ~0x00000020 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - - -# define CFG_I2C_SPEED 50000 -# define CFG_I2C_SLAVE 0x34 -# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ -# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF000000 - -#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE 0xFF000000 -/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if 0 -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x8000 -#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ -#else -#define CFG_ENV_IS_IN_NVRAM 1 -#define CFG_ENV_ADDR 0xfa000100 -#define CFG_ENV_SIZE 0x1000 -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/* #define CFG_DER 0x2002000F */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000E00 - -#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */ -#define CFG_OR3_PRELIM 0xff7f8970 -#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CFG_OR4_PRELIM 0xFFF80970 - -/* ECCX CS settings */ -#define SED13806_OR 0xFFC00108 /* - 4 Mo - - Burst inhibit - - external TA */ -#define SED13806_REG_ADDR 0xa0000000 -#define SED13806_ACCES 0x801 /* 16 bit access */ - - -/* Global definitions for the ECCX board */ -#define ECCX_CSR_ADDR (0xfac00000) -#define ECCX_CSR8_OFFSET (0x8) -#define ECCX_CSR11_OFFSET (0xB) -#define ECCX_CSR12_OFFSET (0xC) - -#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET) -#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET) -#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET) - - -#define REG_GPIO_CTRL 0x008 - -/* Definitions for CSR8 */ -#define ECCX_ENEPSON 0x80 /* Bit 0: - 0= disable and reset SED1386 - 1= enable SED1386 */ -/* Bit 1: 0= SED1386 in Big Endian mode */ -/* 1= SED1386 in little endian mode */ -#define ECCX_LE 0x40 -#define ECCX_BE 0x00 - -/* Bit 2,3: Selection */ -/* 00 = Disabled */ -/* 01 = CS2 is used for the SED1386 */ -/* 10 = CS5 is used for the SED1386 */ -/* 11 = reserved */ -#define ECCX_CS2 0x10 -#define ECCX_CS5 0x20 - -/* Definitions for CSR12 */ -#define ECCX_ID 0x02 -#define ECCX_860 0x01 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 58 - -/* - * Refresh clock Prescalar - */ -#define CFG_MPTPR MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 10 column SDRAM */ -#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ - MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* Configuration variable added by yooth. */ -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_MIIRST 0x80 -#define BCSR2_MIIPWRDWN 0x40 -#define BCSR2_MIICTL 0x08 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - - -/* - * Environment setting - */ - -/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */ -/* #define CONFIG_IPADDR 10.10.106.1 */ -/* #define CONFIG_SERVERIP 10.10.104.11 */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h deleted file mode 100644 index 6b65031..0000000 --- a/include/configs/RPXlite.h +++ /dev/null @@ -1,392 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define RPXLite_50MHz - -/* - * High Level Configuration Options - * (easy to change) - */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_RPXLITE 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFC00000 -/*%%% #define CFG_FLASH_BASE 0xFFF00000 */ -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE 0xFFF00000 -/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_COM11 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000E00 - -#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */ -#define CFG_OR3_PRELIM 0xFFFF8910 -#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CFG_OR4_PRELIM 0xFFFE0970 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 58 - -/* - * Refresh clock Prescalar - */ -#define CFG_MPTPR MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 10 column SDRAM */ -#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ - MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* Configuration variable added by yooth. */ -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - - -/* - * Environment setting - */ - -#define CONFIG_ETHADDR 00:10:EC:00:1D:0B -#define CONFIG_IPADDR 192.168.1.65 -#define CONFIG_SERVERIP 192.168.1.27 - -#endif /* __CONFIG_H */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h deleted file mode 100644 index 8cd7df1..0000000 --- a/include/configs/RPXlite_DW.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-BOOT port on RPXlite board - */ - -/* - * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn - * U-BOOT port on RPXlite DW version board--RPXlite_DW - * June 8 ,2004 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* #define DEBUG 1 */ -/* #ifdef DEPLOYMENT 1 */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */ -#define CONFIG_RPXLITE 1 /* RPXlite DW version board */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */ - -#ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ - -#ifdef DEPLOYMENT -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n" -#define CONFIG_AUTOBOOT_STOP_STR "st" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1 -#define CONFIG_BOOT_RETRY_MIN 1 -#endif /* DEPLOYMENT */ -#endif /* DEBUG */ - -/* pre-boot commands */ -#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "gatewayip=172.16.115.254\0" \ - "netmask=255.255.255.0\0" \ - "kernel_addr=ff040000\0" \ - "ramdisk_addr=ff200000\0" \ - "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \ - "${filesize};md ${kernel_addr};" \ - "echo kernel updating finished\0" \ - "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \ - "${filesize};md ff000000;" \ - "echo u-boot updating finished\0" \ - "eu=protect off 1:6;era 1:6;reset\0" \ - "lcd=setenv stdout lcd;setenv stdin lcd\0" \ - "ser=setenv stdout serial;setenv stdin serial\0" \ - "verify=no" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "u-boot>" /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF000000 - -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif - -#define CFG_MONITOR_BASE 0xFF000000 -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#ifdef CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_ADDR 0xFA000100 -#define CFG_ENV_SIZE 0x1000 -#else -#define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ -#endif /* CFG_ENV_IS_IN_NVRAM */ - -#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 32-bit 12-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif /* We can get SYPCR: 0xFFFF0689. */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 32-bit 12-30 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */ - -/*--------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 16-bit 12-16 - *--------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) -/* TBSCR: 0x00C3 [SAM] */ - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18 - *----------------------------------------------------------------------- - * [RTC enabled but not stopped on FRZ] - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */ - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 16-bit 12-23 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - * [Periodic timer enabled,Periodic timer interrupt disable. ] - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -/* up to 64 MHz we use a 1:2 clock */ -#if defined(RPXlite_64MHz) -#define CFG_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */ -#else -#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) -#endif - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 5-3 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */ -#if defined(RPXlite_64MHz) -#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */ -#else -#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ -#endif - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ -#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */ -#define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */ -#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000E00 -#define CFG_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK)) -#define CFG_OR1_PRELIM ( CFG_OR_AM_SDRAM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXlite mem setting */ -#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */ -#define CFG_OR3_PRELIM 0xFF7F8900 -#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CFG_OR4_PRELIM 0xFFFE0040 - -/* - * Memory Periodic Timer Prescaler - */ -/* periodic timer for refresh */ -#if defined(RPXlite_64MHz) -#define CFG_MAMR_PTA 32 -#else -#define CFG_MAMR_PTA 20 -#endif - -/* - * Refresh clock Prescalar - */ -#define CFG_MPTPR MPTPR_PTP_DIV2 - -/* - * MAMR settings for SDRAM - */ - -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10) -/* CFG_MAMR_9COL:0x20904000 @ 64MHz */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* Configuration variable added by yooth. */ -/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ -/* - * BCSRx - * - * Board Status and Control Registers - * - */ -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR1_SMC1CTS 0x40 /* Added by SAM. */ -#define BCSR1_SMC1TRS 0x80 /* Added by SAM. */ - -#define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */ -#define BCSR2_ENBRG1 0x04 /* Added by SAM. */ - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */ -#define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */ -#define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */ - -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - -/* - * Environment setting - */ -#define CONFIG_ETHADDR 00:10:EC:00:37:5B -#define CONFIG_IPADDR 172.16.115.7 -#define CONFIG_SERVERIP 172.16.115.6 -#define CONFIG_ROOTPATH /workspace/myfilesystem/target/ -#define CONFIG_BOOTFILE uImage.rpxusb - -#endif /* __CONFIG_H */ diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h deleted file mode 100644 index 6ae9403..0000000 --- a/include/configs/RPXsuper.h +++ /dev/null @@ -1,504 +0,0 @@ -#ifndef __CONFIG_H -#define __CONFIG_H - - -/***************************************************************************** - * - * These settings must match the way _your_ board is set up - * - *****************************************************************************/ -/* for the AY-Revision which does not use the HRCW */ -#define CFG_DEFAULT_IMMR 0x00010000 - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/* How is switch S2 set? We really only want the MODCK[1-3] bits, so - * only the 3 least significant bits are important. -*/ -#define CFG_SBC_S2 0x04 - -/* What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core - * 0x2 0x2 33 133 133 - * 0x2 0x4 33 133 200 - * 0x5 0x5 66 133 133 - * 0x5 0x7 66 133 200 - */ -#define CFG_SBC_MODCK_H 0x06 - -#define CFG_SBC_BOOT_LOW 1 /* only for HRCW */ -#undef CFG_SBC_BOOT_LOW - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#define CFG_FLASH0_BASE 0x80000000 -#define CFG_FLASH0_SIZE 16 - -/* What should the base address of the secondary FLASH be and how big - * is it (in Mbytes)? The secondary FLASH is whichever is connected - * to *CS6. U-Boot expects this to be the on board FLASH. If you don't - * want it enabled, don't define these constants. - */ -#define CFG_FLASH1_BASE 0 -#define CFG_FLASH1_SIZE 0 -#undef CFG_FLASH1_BASE -#undef CFG_FLASH1_SIZE - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CFG_SDRAM0_BASE 0x00000000 -#define CFG_SDRAM0_SIZE 64 - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CFG_SDRAM1_BASE 0x04000000 -#define CFG_SDRAM1_SIZE 32 - -/* What should be the base address of the LEDs and switch S0? - * If you don't want them enabled, don't define this. - */ -#define CFG_LED_BASE 0x00000000 - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ - -#if ( CONFIG_ETHER_INDEX == 3 ) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Half Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CFG_CPMFCR_RAMTYPE 0 -/*#define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ -# define CFG_FCC_PSMR 0 - -#else /* CONFIG_ETHER_INDEX */ -# error "on RPX Super ethernet must be FCC3" -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CFG_ENV_IN_OWN_SECT - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 115200 - -/* Ethernet MAC address */ -#define CONFIG_ETHADDR 08:00:22:50:70:63 - -#define CONFIG_IPADDR 192.168.1.99 -#define CONFIG_SERVERIP 192.168.1.3 - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY -1 - -/* undef this to save memory */ -#define CFG_LONGHELP - -/* Monitor Command Prompt */ -#define CFG_PROMPT "=> " - -/* What U-Boot subsytems do you want enabled? */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ - CFG_CMD_I2C | \ - CFG_CMD_REGINFO & \ - ~CFG_CMD_KGDB ) - -/* Where do the internal registers live? */ -#define CFG_IMMR 0xF0000000 - -/* Where do the on board registers (CS4) live? */ -#define CFG_REGS_BASE 0xFA000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) - -#define CFG_MAXARGS 8 /* max number of command args */ - -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x04000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_SDRAM_BASE CFG_SDRAM0_BASE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CFG_SBC_BOOT_LOW) -# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CFG_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CFG_SBC_BOOT_LOW) */ - -/* get the HRCW ISB field from CFG_IMMR */ -#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\ - ((CFG_IMMR & 0x01000000) >> 7) |\ - ((CFG_IMMR & 0x00100000) >> 4) ) - -#define CFG_HRCW_MASTER (HRCW_BPS11 |\ - HRCW_DPPC11 |\ - CFG_SBC_HRCW_IMMR |\ - HRCW_MMR00 |\ - HRCW_LBPC11 |\ - HRCW_APPC10 |\ - HRCW_CS10PC00 |\ - (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\ - CFG_SBC_HRCW_BOOT_FLAGS) - -/* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CFG_RAMBOOT is platform dependent. - */ -#define CFG_MONITOR_BASE (CFG_FLASH0_BASE + 0x00F00000) - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -#ifndef CFG_RAMBOOT -# define CFG_ENV_IS_IN_FLASH 1 - -# ifdef CFG_ENV_IN_OWN_SECT -# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -# define CFG_ENV_SECT_SIZE 0x40000 -# else -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) -# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CFG_ENV_IN_OWN_SECT */ -#else -# define CFG_ENV_IS_IN_NVRAM 1 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) -# define CFG_ENV_SIZE 0x200 -#endif /* CFG_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (/*HID0_ICE |*/\ - /*HID0_DCE |*/\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CFG_HID0_FINAL (/*HID0_ICE |*/\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CFG_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR (BCR_EBM |\ - BCR_PLDP |\ - BCR_EAV |\ - BCR_NPQM0) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ - -#define CFG_SIUMCR (SIUMCR_L2CPC01 |\ - SIUMCR_APPC10 |\ - SIUMCR_CS10PC01) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CFG_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CFG_SCCR (SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90) - * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60) - * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60) - * 3 unused - * 4 60x GPCM 8 bit Board Regs, LEDs, switches - * 5 unused - * 6 unused - * 7 unused - * 8 PCMCIA - * 9 unused - * 10 unused - * 11 unused -*/ - -/* Bank 0 - FLASH - * - */ -#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_6_CLK |\ - ORxG_EHTR) - -/* Bank 1 - SDRAM - * - */ -#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12 |\ - ORxS_IBID) - -#define CFG_PSDMR 0x014DA412 -#define CFG_PSRT 0x79 - - -/* Bank 2 - SDRAM - * - */ -#define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CFG_LSDMR 0x0169A512 -#define CFG_LSRT 0x79 - -#define CFG_MPTPR (0x0800 & MPTPR_PTP_MSK) - -/* Bank 4 - On board registers - * - */ -#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h deleted file mode 100644 index 3885bcd..0000000 --- a/include/configs/RRvision.h +++ /dev/null @@ -1,466 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_RRVISION 1 /* ...on a RRvision board */ - -#define CONFIG_8xx_GCLK_FREQ 64000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "setenv stdout serial" - -#undef CONFIG_BOOTARGS -#define CONFIG_ETHADDR 00:50:C2:00:E0:70 -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#define CONFIG_IPADDR 10.0.0.5 -#define CONFIG_SERVERIP 10.0.0.2 -#define CONFIG_NETMASK 255.0.0.0 -#define CONFIG_ROOTPATH /opt/eldk/ppc_8xx -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \ - ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "load=tftp 100000 /tftpboot/u-boot.bin\0" \ - "update=protect off 1:0-8;era 1:0-8;" \ - "cp.b 100000 40000000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "kernel_img=/tftpboot/uImage\0" \ - "kernel_load=tftp 200000 ${kernel_img}\0" \ - "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \ - "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" - - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* disturbs display */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -#ifndef CONFIG_LCD -#define CONFIG_VIDEO 1 /* To enable the video initialization */ - -/* Video related */ -#define CONFIG_VIDEO_LOGO 1 /* Show the logo */ -#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */ -#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */ -#endif - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C /* I2C bit-banged */ - -# define CFG_I2C_SPEED 50000 /* 50 kHz is supposed to work */ -# define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - - -#define CONFIG_COMMANDS ( ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_DATE ) & \ - ~( CFG_CMD_PCMCIA | \ - CFG_CMD_IDE ) ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -/* timeout values are in ticks = ms */ -#define CFG_FLASH_ERASE_TOUT (120*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (1 * CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ - -/* for 64 MHz, we use a 16 MHz clock * 4 */ -#define CFG_PLPRCR ( (4-1)< ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ -#define CFG_MAMR_PTA 129 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h deleted file mode 100644 index a170f29..0000000 --- a/include/configs/Rattler.h +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * U-Boot configuration for Analogue&Micro Rattler boards. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_MPC8248 -#define CPU_ID_STR "MPC8248" -#else -#define CONFIG_MPC8260 -#define CPU_ID_STR "MPC8250" -#endif /* CONFIG_MPC8248 */ - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_RATTLER /* Analogue&Micro Rattler board */ - -#undef DEBUG - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ - -#if (CONFIG_ETHER_INDEX == 1) - -/* - Rx clock is CLK11 - * - Tx clock is CLK10 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#elif (CONFIG_ETHER_INDEX == 2) - -/* - Rx clock is CLK15 - * - Tx clock is CLK14 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00800000; \ - else iop->pdat &= ~0x00800000 - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ - | CFG_CMD_IMMAP \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CFG_DIRECT_FLASH_TFTP - -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) -#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS -#define CFG_JFFS2_SORT_FRAGMENTS - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00100000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=rattler-0" -#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)" -*/ -#endif /* CFG_CMD_JFFS2 */ - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -#define CFG_ENV_IS_IN_FLASH - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#endif /* CFG_ENV_IS_IN_FLASH */ - -#define CFG_DEFAULT_IMMR 0xFF010000 - -#define CFG_IMMR 0xF0000000 - -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 32 -#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041) -#define CFG_SDRAM_OR 0xFE002EC0 - -#define CFG_BCSR 0xFC000000 - -/* Hard reset configuration word */ -#define CFG_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */ -/* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CFG_HID2 0 - -#define CFG_SIUMCR 0x0E04C000 -#define CFG_SYPCR 0xFFFFFFC3 -#define CFG_BCR 0x00000000 -#define CFG_SCCR SCCR_DFBRG01 - -#define CFG_RMR RMR_CSRE -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CFG_RCCR 0 - -#define CFG_PSDMR 0x8249A452 -#define CFG_PSRT 0x1F -#define CFG_MPTPR 0x2000 - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001001) -#define CFG_OR0_PRELIM 0xFF001ED6 -#define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801) -#define CFG_OR7_PRELIM 0xFFFF87F6 - -#define CFG_RESET_ADDRESS 0xC0000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h deleted file mode 100644 index 0451b20..0000000 --- a/include/configs/SBC8540.h +++ /dev/null @@ -1,422 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * (C) Copyright 2004 Wind River Systems Inc . - * Added support for Wind River SBC8540 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if XXX -#define DEBUG /* General debug */ -#define ET_DEBUG -#endif -#define TSEC_DEBUG - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ - - -#define CONFIG_CPM2 1 /* has CPM2 */ - -#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ - -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_PCI /* pci ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ - - -#define CONFIG_ENV_OVERWRITE - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. - */ -#undef CONFIG_RAM_AS_FLASH - -#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ - #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */ -#else - #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ -#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ - -#if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -#else /* Boot from real Flash */ - #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -#endif -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* local bus definitions */ -#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -#define CFG_OR1_PRELIM 0xfc000ff7 - -#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ -#define CFG_OR2_PRELIM 0x00000000 - -#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CFG_OR3_PRELIM 0xfc000cc1 - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -#else - #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -#endif -#define CFG_OR4_PRELIM 0xfc000cc1 - -#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ -#if 1 - #define CFG_OR5_PRELIM 0xff000ff7 -#else - #define CFG_OR5_PRELIM 0xff0000f0 -#endif - -#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -#define CFG_OR6_PRELIM 0xfc000ff7 -#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 - -/* just hijack the MOT BCSR def for SBC8560 misc devices */ -#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) -/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#if 0 -#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ -#else -#define CFG_NS16550_CLK 264000000 /* get_bus_freq(0) */ -#endif - -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#if 0 -#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) -#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) -#else -/* SBC8540 uses internal COMM controller */ -#define CFG_NS16550_COM1 ((CFG_CCSRBAR & 0xfff00000)+0x00004500) -#define CFG_NS16550_COM2 ((CFG_CCSRBAR & 0xfff00000)+0x00004600) -#endif - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -#define CFG_PCI_MEM_BASE 0xC0000000 -#define CFG_PCI_MEM_PHYS 0xC0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 - -#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ - -# define CONFIG_NET_MULTI 1 -# define CONFIG_MPC85xx_TSEC1 -# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" -# define CONFIG_MII 1 /* MII PHY management */ -# define TSEC1_PHY_ADDR 25 -# define TSEC1_PHYIDX 0 -/* Options are: TSEC0 */ -# define CONFIG_ETHPRIME "TSEC0" - - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - - #undef CONFIG_ETHER_NONE /* define if ether on something else */ - #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ - #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - - #if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) - - #elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #endif /* CONFIG_ETHER_INDEX */ - - #define CONFIG_MII /* MII PHY management */ - #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - /* - * GPIO pins used for bit-banged MII communications - */ - #define MDIO_PORT 2 /* Port C */ - #define MDIO_ACTIVE (iop->pdir |= 0x00400000) - #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) - #define MDIO_READ ((iop->pdat & 0x00400000) != 0) - - #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - - #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - - #define MIIDELAY udelay(1) - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if 0 -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_PROTECTION /* use hardware protection */ -#endif -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if 0 -/* XXX This doesn't work and I don't want to fix it */ -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) - #define CFG_RAMBOOT -#else - #undef CFG_RAMBOOT -#endif -#endif - -/* Environment */ -#if !defined(CFG_RAMBOOT) - #if defined(CONFIG_RAM_AS_FLASH) - #define CFG_ENV_IS_NOWHERE - #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) - #define CFG_ENV_SIZE 0x2000 - #else - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) - #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ - #endif -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) - #endif -#endif - -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SBC8540=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*Note: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a -# define CONFIG_HAS_ETH1 -# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b -# define CONFIG_HAS_ETH2 -# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c -#endif - -#define CONFIG_SERVERIP YourServerIP -#define CONFIG_IPADDR YourTargetIP -#define CONFIG_GATEWAYIP YourGatewayIP -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME SBC8560 -#define CONFIG_ROOTPATH YourRootPath -#define CONFIG_BOOTFILE YourImageName - -#endif /* __CONFIG_H */ diff --git a/include/configs/SBC8560.h b/include/configs/SBC8560.h deleted file mode 100644 index 8b46a17..0000000 --- a/include/configs/SBC8560.h +++ /dev/null @@ -1,410 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * (C) Copyright 2004 Wind River Systems Inc . - * Added support for Wind River SBC8560 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if XXX -#define DEBUG /* General debug */ -#define ET_DEBUG -#endif -#define TSEC_DEBUG - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ - - -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ - -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_PCI /* pci ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ - - -#define CONFIG_ENV_OVERWRITE - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. - */ -#undef CONFIG_RAM_AS_FLASH - -#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ - #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ -#else - #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ -#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ - -#if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -#else /* Boot from real Flash */ - #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -#endif -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* local bus definitions */ -#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -#define CFG_OR1_PRELIM 0xfc000ff7 - -#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ -#define CFG_OR2_PRELIM 0x00000000 - -#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CFG_OR3_PRELIM 0xfc000cc1 - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -#else - #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -#endif -#define CFG_OR4_PRELIM 0xfc000cc1 - -#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ -#if 1 - #define CFG_OR5_PRELIM 0xff000ff7 -#else - #define CFG_OR5_PRELIM 0xff0000f0 -#endif - -#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -#define CFG_OR6_PRELIM 0xfc000ff7 -#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 - -/* just hijack the MOT BCSR def for SBC8560 misc devices */ -#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) -/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) -#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -#define CFG_PCI_MEM_BASE 0xC0000000 -#define CFG_PCI_MEM_PHYS 0xC0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 - -#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ - -# define CONFIG_NET_MULTI 1 -# define CONFIG_MII 1 /* MII PHY management */ -# define CONFIG_MPC85xx_TSEC1 -# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" -# define TSEC1_PHY_ADDR 25 -# define TSEC1_PHYIDX 0 -/* Options are: TSEC0 */ -# define CONFIG_ETHPRIME "TSEC0" - - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - - #undef CONFIG_ETHER_NONE /* define if ether on something else */ - #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ - #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - - #if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) - - #elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #endif /* CONFIG_ETHER_INDEX */ - - #define CONFIG_MII /* MII PHY management */ - #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - /* - * GPIO pins used for bit-banged MII communications - */ - #define MDIO_PORT 2 /* Port C */ - #define MDIO_ACTIVE (iop->pdir |= 0x00400000) - #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) - #define MDIO_READ ((iop->pdat & 0x00400000) != 0) - - #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - - #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - - #define MIIDELAY udelay(1) - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if 0 -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_PROTECTION /* use hardware protection */ -#endif -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if 0 -/* XXX This doesn't work and I don't want to fix it */ -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) - #define CFG_RAMBOOT -#else - #undef CFG_RAMBOOT -#endif -#endif - -/* Environment */ -#if !defined(CFG_RAMBOOT) - #if defined(CONFIG_RAM_AS_FLASH) - #define CFG_ENV_IS_NOWHERE - #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) - #define CFG_ENV_SIZE 0x2000 - #else - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) - #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ - #endif -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) - #endif -#endif - -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*Note: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a -# define CONFIG_HAS_ETH1 -# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b -# define CONFIG_HAS_ETH2 -# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c -#endif - -#define CONFIG_SERVERIP YourServerIP -#define CONFIG_IPADDR YourTargetIP -#define CONFIG_GATEWAYIP YourGatewayIP -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME SBC8560 -#define CONFIG_ROOTPATH YourRootPath -#define CONFIG_BOOTFILE YourImageName - -#endif /* __CONFIG_H */ diff --git a/include/configs/SCM.h b/include/configs/SCM.h deleted file mode 100644 index e263db6..0000000 --- a/include/configs/SCM.h +++ /dev/null @@ -1,711 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ -#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ -#define CONFIG_SCM 1 /* ...on a System Controller Module */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#if (CONFIG_TQM8260 <= 100) -# error "TQM8260 module revison not supported" -#endif - -/* We use a TQM8260 module with a 300MHz CPU */ -#define CONFIG_300MHz - -/* Define 60x busmode only if your TQM8260 has L2 cache! */ -#ifdef CONFIG_L2_CACHE -# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */ -#else -# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */ -#endif - -/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */ -#ifdef CONFIG_300MHz -# define CONFIG_BUSMODE_60x -#endif - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * - * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK12 - * - Tx-CLK is CLK11 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifndef CONFIG_300MHz -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 83333000 /* in Hz */ -#endif - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_BSP) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CFG_FLASH0_BASE 0x40000000 -#define CFG_FLASH1_BASE 0x60000000 -#define CFG_FLASH0_SIZE 32 -#define CFG_FLASH1_SIZE 32 - -/* Flash bank size (for preliminary settings) - */ -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to EEPROM later */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) -#define CFG_ENV_SIZE 0x40000 -#define CFG_ENV_SECT_SIZE 0x40000 -#else -/* Final version: environment in EEPROM */ -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 2048 -#endif - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#if defined(CONFIG_266MHz) -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0111) -#elif defined(CONFIG_300MHz) -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0110) -#else -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) -#endif - -/* no slaves so just fill with zeros */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#ifdef CONFIG_BUSMODE_60x -#define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ - BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ -#else -#define BCR_APD01 0x10000000 -#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#else -#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 Local SDRAM 32 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CFG_INIT_LOCAL_SDRAM - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ -#define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ - -#define CFG_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CFG_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - - /* SDRAM on TQM8260 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CFG_PSRT 0x20 -#define CFG_LSRT 0x20 -#ifndef CFG_RAMBOOT -#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM CFG_OR1_8COL - - - /* SDRAM initialization values for 8-column chips - */ -#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CFG_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CFG_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - -/* Bank 2 - Local bus SDRAM - */ -#ifdef CFG_INIT_LOCAL_SDRAM -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -#define CFG_OR2_PRELIM CFG_OR2_8COL - -#define SDRAM_BASE2_PRELIM 0x80000000 - - /* SDRAM initialization values for 8-column chips - */ -#define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A8 |\ - ORxS_NUMR_12) - -#define CFG_LSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_13) - -#define CFG_LSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - -#endif /* CFG_INIT_LOCAL_SDRAM */ - -#endif /* CFG_RAMBOOT */ - -#define CFG_CAN0_BASE 0xc0000000 -#define CFG_CAN1_BASE 0xc0008000 -#define CFG_FIOX_BASE 0xc0010000 -#define CFG_FDOHM_BASE 0xc0018000 -#define CFG_EXTPROM_BASE 0xc2000000 - -#define CFG_CAN_SIZE 0x00000100 -#define CFG_FIOX_SIZE 0x00000020 -#define CFG_FDOHM_SIZE 0x00002000 -#define CFG_EXTPROM_BANK_SIZE 0x01000000 - -#define EXT_EEPROM_MAX_FLASH_BANKS 0x02 - -/* CS3 - CAN 0 - */ -#define CFG_CAN0_BR3 ((CFG_CAN0_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMA |\ - BRx_V) - -#define CFG_CAN0_OR3 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_4IDLE) - -/* CS4 - CAN 1 - */ -#define CFG_CAN1_BR4 ((CFG_CAN1_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMA |\ - BRx_V) - -#define CFG_CAN1_OR4 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_4IDLE) - -/* CS5 - Extended PROM (16MB optional) - */ -#define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -/* CS6 - Extended PROM (16MB optional) - */ -#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \ - CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -/* CS7 - FPGA FIOX: Glue Logic - */ -#define CFG_FIOX_BR7 ((CFG_FIOX_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_FIOX_OR7 (P2SZ_TO_AM(CFG_FIOX_SIZE) |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -/* CS8 - FPGA DOH Master - */ -#define CFG_FDOHM_BR8 ((CFG_FDOHM_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_FDOHM_OR8 (P2SZ_TO_AM(CFG_FDOHM_SIZE) |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - - -/* FPGA configuration */ -#define CFG_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */ -#define CFG_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */ -#define CFG_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */ - -#define CFG_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */ -#define CFG_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */ -#define CFG_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h deleted file mode 100644 index 61896d0..0000000 --- a/include/configs/SL8245.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * (C) Copyright 2001 - 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ -/* - * Configuration settings for the SL8245 board. - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_SL8245 1 - - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ - -#include - - -/* - * Miscellaneous configurable options - */ -#undef CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) -#define CFG_MAXARGS 32 /* Max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00400000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -#define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ -#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM -#define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM } - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_EUMB_ADDR 0xFC000000 - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CFG_MAX_RAM_SIZE 0x10000000 /* 0 .. 256 MB of (S)DRAM */ - - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#undef CFG_RAMBOOT -#else -#define CFG_RAMBOOT -#endif - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -#define CFG_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 66666666 /* external frequency to pll */ -#define CFG_HZ 1000 - - /* Bit-field values for MCCR1. - */ -#define CFG_ROMNAL 0 -#define CFG_ROMFAL 7 -#define CFG_BANK0_ROW 2 - - /* Bit-field values for MCCR2. - */ -#define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CFG_BSTOPRE 192 - - /* Bit-field values for MCCR3. - */ -#define CFG_REFREC 2 /* Refresh to activate interval */ - - /* Bit-field values for MCCR4. - */ -#define CFG_PRETOACT 2 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_ACTORW 3 /* FIXME was 2 */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 1 -#define CFG_REGDIMM 0 - -#define CFG_ODCR 0xff /* configures line driver impedances, */ - /* see 8245 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8245 retains the */ - /* currently accessed page in memory */ - /* see 8245 book for details */ - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff -#define CFG_BANK7_ENABLE 0 - -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors per flash */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0xFFFF0000 -#define CFG_ENV_SIZE 0x00010000 /* Size of the Environment */ -#define CFG_ENV_SECT_SIZE 0x00010000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI -#define CONFIG_PCI_PNP -#undef CONFIG_PCI_SCAN_SHOW - - -#define CONFIG_SK98 -#define CONFIG_NET_MULTI - - -#endif /* __CONFIG_H */ diff --git a/include/configs/SM850.h b/include/configs/SM850.h deleted file mode 100644 index 4977629..0000000 --- a/include/configs/SM850.h +++ /dev/null @@ -1,363 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_SM850 1 /*...on a MPC850 Service Module */ - -#undef CONFIG_8xx_CONS_SMC1 /* SMC1 not usable because Ethernet on SCC3 */ -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* Status LED not enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && defined(KGDB_DEBUG) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)< - -/*----------------------------------------------------------------------*/ -#define CONFIG_ETHADDR 00:D0:93:00:01:CB -#define CONFIG_IPADDR 10.0.0.98 -#define CONFIG_SERVERIP 10.0.0.1 -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000" -/*----------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF000000 -#ifdef DEBUG -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 0 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* 0x00000040 */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00b0c0c0 */ -#define CFG_PLPRCR \ - ( (11 << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800014 */ -#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD101 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register - *----------------------------------------------------------------------- - */ -/* 0x00C3 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register - *----------------------------------------------------------------------- - */ -/* TIMEP=2 */ -#define CFG_RCCR 0x0200 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CFG_RMDS 0 - -/*----------------------------------------------------------------------- - * SDSR - SDMA Status Register - *----------------------------------------------------------------------- - */ -#define CFG_SDSR ((u_char)0x83) - -/*----------------------------------------------------------------------- - * SDMR - SDMA Mask Register - *----------------------------------------------------------------------- - */ -#define CFG_SDMR ((u_char)0x00) - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xFE100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_IDE1_OFFSET 0x0C00 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* EPROMs are 512kb */ -#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -/* 16 bit, bank valid */ -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC) - * - */ -#define SRAM_BASE 0xFE200000 /* SRAM bank */ -#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */ - -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define PER8_BASE 0xFE000000 /* PER8 bank */ -#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */ - -#define SHARC_BASE 0xFE400000 /* SHARC bank */ -#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */ - -/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ - -#define CFG_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */ -#define CFG_OR2 (SRAM_OR_AM | CFG_OR_TIMING_SRAM ) -#define CFG_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ - -#define CFG_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */ -#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) - -#define CFG_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */ -#define CFG_OR4 (PER8_OR_AM | CFG_OR_TIMING_PER8 ) -#define CFG_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -#define CFG_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */ -#define CFG_OR5 (SHARC_OR_AM | CFG_OR_TIMING_SHARC ) -#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MBMR_PTB 204 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MBMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/SX1.h b/include/configs/SX1.h deleted file mode 100644 index 6ed98b8..0000000 --- a/include/configs/SX1.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ -#define CONFIG_OMAP_SX1 1 /* a SX1 Board */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000 /* the SX1 has 12MHz input clock */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SX1 */ - -/* - * USB device configuration - */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 - -#define CONFIG_USBD_VENDORID 0x1234 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Siemens" -#define CONFIG_USBD_PRODUCT_NAME "SX1" - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C -#define CFG_I2C_SPEED 100000 -#define CFG_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP1510_I2C - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \ - CFG_CMD_I2C ) & \ - ~CFG_CMD_NET) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#include - -#define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw" -#define CONFIG_PREBOOT "setenv stdout usbtty;setenv stdin usbtty" - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SX1# " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. - * This time is further subdivided by a local divisor. - */ -#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SIZE (16 << 10) /* 16 MB */ -#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ -#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ -#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE } - -/*----------------------------------------------------------------------- - * FLASH driver setup - */ -#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Total Size of Environment Sector */ -#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_SIZE_REDUND 0x20000 -#define CFG_ENV_OFFSET_REDUND 0x40000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h deleted file mode 100644 index c1c765f..0000000 --- a/include/configs/SXNI855T.h +++ /dev/null @@ -1,460 +0,0 @@ -/* - * U-Boot configuration for SIXNET SXNI855T CPU board. - * This board is based (loosely) on the Motorola FADS board, so this - * file is based (loosely) on config_FADS860T.h, see it for additional - * credits. - * - * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* - * Memory map: - * - * ff100000 -> ff13ffff : FPGA CS1 - * ff030000 -> ff03ffff : EXPANSION CS7 - * ff020000 -> ff02ffff : DATA FLASH CS4 - * ff018000 -> ff01ffff : UART B CS6/UPMB - * ff010000 -> ff017fff : UART A CS5/UPMB - * ff000000 -> ff00ffff : IMAP internal to the MPC855T - * f8000000 -> fbffffff : FLASH CS0 up to 64MB - * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB - * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#include - -#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */ - -/* The 855T is just a stripped 860T and needs code for 860, so for now - * at least define 860, 860T and 855T - */ -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC855T 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_SCC1 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_HAS_ETH1 - -/*----------------------------------------------------------------------- - * Definitions for status LED - */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */ -# define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifdef DEV /* development (debug) settings */ -#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF -#else /* production settings */ -#define CONFIG_BOOT_LED_STATE STATUS_LED_ON -#endif - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram ip=off" - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ -#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */ - -#define CONFIG_SOFT_I2C /* I2C bit-banged */ -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -# define CFG_I2C_SPEED 50000 -# define CFG_I2C_SLAVE 0xFE -# define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */ -# define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ - -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CONFIG_MII 1 - -#define CFG_DISCOVER_PHY - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NAND | \ - CFG_CMD_DATE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CFG_JFFS2_SORT_FRAGMENTS - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE - -/* -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0x00780000 -#define CONFIG_JFFS2_PART_OFFSET 0x00080000 -*/ - -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00200000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=sixnet-0,nand0=sixnet-nand" -#define MTDPARTS_DEFAULT "mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)" -*/ - -/* NAND flash support */ -#define CONFIG_MTD_NAND_ECC_JFFS2 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -/* DFBUSY is available on Port C, bit 12; 0 if busy */ -#define NAND_WAIT_READY(nand) \ - while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008)); -#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr)) -#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr)) -#define WRITE_NAND(d, adr) \ - do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0) -#define READ_NAND(adr) (*(volatile uint8_t *)(adr)) -#define CLE_LO 0x01 /* 0 selects CLE mode (CLE high) */ -#define ALE_LO 0x02 /* 0 selects ALE mode (ALE high) */ -#define CE_LO 0x04 /* 1 selects chip (CE low) */ -#define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0) -#define NAND_DISABLE_CE(nand) \ - nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO) -#define NAND_ENABLE_CE(nand) \ - nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO) -#define NAND_CTL_CLRALE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO) -#define NAND_CTL_SETALE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | CLE_LO) -#define NAND_CTL_CLRCLE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO) -#define NAND_CTL_SETCLE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | ALE_LO) - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save a little memory */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 -#define CFG_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SRAM_BASE 0xF4000000 -#define CFG_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */ - -#define CFG_FLASH_BASE 0xF8000000 -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CFG_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */ -#define CFG_DFLASH_SIZE 0x00010000 - -#define CFG_FPGA_BASE 0xFF100000 /* Xilinx FPGA */ -#define CFG_FPGA_PROG 0xFF130000 /* Programming address */ -#define CFG_FPGA_SIZE 0x00040000 /* 256KiB usable */ - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks. - * AMD 29LV641 has 128 64K sectors in 8MB - */ -#define CFG_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the - * entire address space, we have to set the memory controller - * differently. Normally, you write the option register - * first, and then enable the chip select by writing the - * base register. For CS0, you must write the base register - * first, followed by the option register. - */ - -/* - * Init Memory Controller: - * - ********************************************************** - * BR0 and OR0 (FLASH) - */ - -#define CFG_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH) - -#define CONFIG_FLASH_16BIT -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) -#define CFG_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */ - -/********************************************************** - * BR1 and OR1 (FPGA) - * These preliminary values are also the final values. - */ -#define CFG_OR_TIMING_FPGA \ - (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX) -#define CFG_BR1_PRELIM ((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CFG_OR1_PRELIM (((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA) - -/********************************************************** - * BR4 and OR4 (data flash) - * These preliminary values are also the final values. - */ -#define CFG_OR_TIMING_DFLASH \ - (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX) -#define CFG_BR4_PRELIM ((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CFG_OR4_PRELIM (((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH) - -/********************************************************** - * BR5/6 and OR5/6 (Dual UART) - */ -#define CFG_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */ -#define CFG_DUARTA_BASE 0xff010000 -#define CFG_DUARTB_BASE 0xff018000 - -#define DUART_MBMR 0 -#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI) -#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V) -#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE) -#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE) - -/********************************************************** - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_RESET_ON_PANIC /* reset if system panic() */ - -#define CFG_ENV_IS_IN_FLASH -#ifdef CFG_ENV_IS_IN_FLASH - /* environment is in FLASH */ - #define CFG_ENV_ADDR 0xF8040000 /* AM29LV641 or AM29LV800BT */ - #define CFG_ENV_ADDR_REDUND 0xF8050000 /* AM29LV641 or AM29LV800BT */ - #define CFG_ENV_SECT_SIZE 0x00010000 - #define CFG_ENV_SIZE 0x00002000 -#else - /* environment is in EEPROM */ - #define CFG_ENV_IS_IN_EEPROM 1 - #define CFG_ENV_OFFSET 0 /* at beginning of EEPROM */ - #define CFG_ENV_SIZE 1024 /* Use only a part of it*/ -#endif - -#if 1 -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" -#define CONFIG_AUTOBOOT_DELAY_STR "delayabit" -#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h deleted file mode 100644 index f4339ec..0000000 --- a/include/configs/Sandpoint8240.h +++ /dev/null @@ -1,413 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_SANDPOINT 1 - -#if 0 -#define USE_DINK32 1 -#else -#undef USE_DINK32 -#endif - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "net_self=tftp ${kernel_addr} ${bootfile};" \ - "tftp ${ramdisk_addr} ${ramdisk};" \ - "run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp ${kernel_addr} ${bootfile};" \ - "run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/SP8240/uImage\0" \ - "ramdisk=/tftpboot/SP8240/uRamdisk\0" \ - "kernel_addr=200000\0" \ - "ramdisk_addr=400000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_SDRAM | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_DRAM_SPEED 100 /* MHz */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x10000000 - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE 0x00090000 -#define CFG_RAMBOOT 1 -#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_INIT_RAM_END 0x10000 -#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#else -#undef CFG_RAMBOOT -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE TEXT_BASE - -/*#define CFG_GBL_DATA_SIZE 256*/ -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#endif - -#define CFG_FLASH_BASE 0xFFF00000 -#if 0 -#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ -#else -#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ -#endif -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - -#define CFG_EUMB_ADDR 0xFC000000 - -#define CFG_ISA_MEM 0xFD000000 -#define CFG_ISA_IO 0xFE000000 - -#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ -#define CFG_FLASH_RANGE_SIZE 0x01000000 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#ifdef CONFIG_SOFT_I2C -#error "Soft I2C is not configured properly. Please review!" -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - - -#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* write page size */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ - - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - - -#define CFG_WINBOND_83C553 1 /*has a winbond bridge */ -#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ -#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ -#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ - -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -/* - * NS87308 Configuration - */ -#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ - -#define CFG_NS87308_BADDR_10 1 - -#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \ - CFG_NS87308_UART2 | \ - CFG_NS87308_POWRMAN | \ - CFG_NS87308_RTC_APC ) - -#undef CFG_NS87308_PS2MOD - -#define CFG_NS87308_CS0_BASE 0x0076 -#define CFG_NS87308_CS0_CONF 0x30 -#define CFG_NS87308_CS1_BASE 0x0075 -#define CFG_NS87308_CS1_CONF 0x30 -#define CFG_NS87308_CS2_BASE 0x0074 -#define CFG_NS87308_CS2_CONF 0x30 - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK 1843200 - -#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) -#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1 - -#define CFG_ROMNAL 7 /*rom/flash next access time */ -#define CFG_ROMFAL 11 /*rom/flash access time */ - -#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ - -/* the following are for SDRAM only*/ -#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CFG_REFREC 8 /* Refresh to activate interval */ -#define CFG_RDLAT 4 /* data latency from read command */ -#define CFG_PRETOACT 3 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_ACTORW 3 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ - -#define CFG_REGISTERD_TYPE_BUFFER 1 - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CFG_BANK_ENABLE 0x01 - -#define CFG_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h deleted file mode 100644 index d42bd69..0000000 --- a/include/configs/Sandpoint8245.h +++ /dev/null @@ -1,392 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_SANDPOINT 1 - -#if 0 -#define USE_DINK32 1 -#else -#undef USE_DINK32 -#endif - -#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_DRAM_SPEED 100 /* MHz */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ - -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NATSEMI -#define CONFIG_NS8382X - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x10000000 - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE 0x00090000 -#define CFG_RAMBOOT 1 -#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_INIT_RAM_END 0x10000 -#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#else -#undef CFG_RAMBOOT -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE TEXT_BASE - -/*#define CFG_GBL_DATA_SIZE 256*/ -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#endif - -#define CFG_FLASH_BASE 0xFFF00000 -#if 0 -#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ -#else -#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ -#endif -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - -#define CFG_EUMB_ADDR 0xFC000000 - -#define CFG_ISA_MEM 0xFD000000 -#define CFG_ISA_IO 0xFE000000 - -#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ -#define CFG_FLASH_RANGE_SIZE 0x01000000 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#ifdef CONFIG_SOFT_I2C -#error "Soft I2C is not configured properly. Please review!" -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - - -#define CFG_WINBOND_83C553 1 /*has a winbond bridge */ -#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ -#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ -#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ - -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -/* - * NS87308 Configuration - */ -#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ - -#define CFG_NS87308_BADDR_10 1 - -#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \ - CFG_NS87308_UART2 | \ - CFG_NS87308_POWRMAN | \ - CFG_NS87308_RTC_APC ) - -#undef CFG_NS87308_PS2MOD - -#define CFG_NS87308_CS0_BASE 0x0076 -#define CFG_NS87308_CS0_CONF 0x30 -#define CFG_NS87308_CS1_BASE 0x0075 -#define CFG_NS87308_CS1_CONF 0x30 -#define CFG_NS87308_CS2_BASE 0x0074 -#define CFG_NS87308_CS2_CONF 0x30 - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX > 2) -#define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000 -#else -#define CFG_NS16550_CLK 1843200 -#endif - -#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) -#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) -#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CFG_ROMNAL 7 /*rom/flash next access time */ -#define CFG_ROMFAL 11 /*rom/flash access time */ - -#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ - -/* the following are for SDRAM only*/ -#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CFG_REFREC 8 /* Refresh to activate interval */ -#define CFG_RDLAT 4 /* data latency from read command */ -#define CFG_PRETOACT 3 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_ACTORW 3 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#if 0 -#define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ -#endif - -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 1 -#define CFG_REGDIMM 0 - - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CFG_BANK_ENABLE 0x01 - -#define CFG_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h deleted file mode 100644 index 119bc24..0000000 --- a/include/configs/TASREG.h +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Configuation settings for the esd TASREG board. - * - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _TASREG_H -#define _TASREG_H - -#ifndef __ASSEMBLY__ -#include -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5249 /* define processor type */ - -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_BAUDRATE 19200 -#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } - -#undef CONFIG_WATCHDOG - -#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C ) & \ - ~(CFG_CMD_NET)) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#define CONFIG_BOOTDELAY 3 - -#define CFG_PROMPT "=> " -#define CFG_LONGHELP /* undef to save memory */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ - -#define CFG_LOAD_ADDR 0x200000 /* default load address */ - -#define CFG_MEMTEST_START 0x400 -#define CFG_MEMTEST_END 0x380000 - -#define CFG_HZ 1000 - -/* - * Clock configuration: enable only one of the following options - */ - -#if 0 /* this setting will run the cpu at 11MHz */ -#define CFG_PLL_BYPASS 1 /* bypass PLL for test purpose */ -#undef CFG_FAST_CLK /* MCF5249 can run at 140MHz */ -#define CFG_CLK 11289600 /* PLL bypass */ -#endif - -#if 0 /* this setting will run the cpu at 70MHz */ -#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ -#undef CFG_FAST_CLK /* MCF5249 can run at 140MHz */ -#define CFG_CLK 72185018 /* The next lower speed */ -#endif - -#if 1 /* this setting will run the cpu at 140MHz */ -#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ -#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */ -#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */ -#endif - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CFG_MBAR 0x10000000 /* Register Base Addrs */ -#define CFG_MBAR2 0x80000000 - -/*----------------------------------------------------------------------- - * I2C - */ -#define CONFIG_SOFT_I2C -#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -#if defined (CONFIG_SOFT_I2C) -#if 0 /* push-pull */ -#define SDA 0x00800000 -#define SCL 0x00000008 -#define DIR0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN)) -#define DIR1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN)) -#define OUT0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT)) -#define OUT1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT)) -#define IN0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ)) -#define IN1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ)) -#define I2C_INIT {OUT1|=SDA;OUT0|=SCL;} -#define I2C_READ ((IN1&SDA)?1:0) -#define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;} -#define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;} -#define I2C_DELAY {udelay(5);} -#define I2C_ACTIVE {DIR1|=SDA;} -#define I2C_TRISTATE {DIR1&=~SDA;} -#else /* open-collector */ -#define SDA 0x00800000 -#define SCL 0x00000008 -#define DIR0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN)) -#define DIR1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN)) -#define OUT0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT)) -#define OUT1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT)) -#define IN0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ)) -#define IN1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ)) -#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;} -#define I2C_READ ((IN1&SDA)?1:0) -#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;} -#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;} -#define I2C_DELAY {udelay(5);} -#define I2C_ACTIVE {DIR1|=SDA;} -#define I2C_TRISTATE {DIR1&=~SDA;} -#endif -#endif - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/ -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CFG_FLASH_BASE 0xffc00000 - -#if 0 /* test-only */ -#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ -#endif - -#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) - -#define CFG_MONITOR_LEN 0x20000 -#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ -#define CFG_BOOTPARAMS_LEN 64*1024 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ - -/* CS0 - AMD Flash, address 0xffc00000 */ -#define CFG_CSAR0 0xffc0 -#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */ -/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ -#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ - -/* CS1 - FPGA, address 0xe0000000 */ -#define CFG_CSAR1 0xe000 -#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */ -#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ - -/*----------------------------------------------------------------------- - * Port configuration - */ -#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ -#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ - -#define CFG_GPIO1_LED 0x00400000 /* user led */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */ - -#endif /* _TASREG_H */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h deleted file mode 100644 index f41dbd0..0000000 --- a/include/configs/TOP5200.h +++ /dev/null @@ -1,418 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de - * - * TOP5200 differences from IceCube: - * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks - * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins - * 1 SDRAM/DDRAM Bank up to 256 MB - * local VPD I2C Bus is software driven and uses - * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL - * FLASH is re-located at 0xff000000 - * Internal regs are at 0xf0000000 - * Reset jumps to 0x00000100 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ -#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -# define CONFIG_PCI 1 -# define CONFIG_PCI_PNP 1 -# define CONFIG_PCI_SCAN_SHOW 1 - -# define CONFIG_PCI_MEM_BUS 0x40000000 -# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -# define CONFIG_PCI_MEM_SIZE 0x10000000 - -# define CONFIG_PCI_IO_BUS 0x50000000 -# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -# define CONFIG_PCI_IO_SIZE 0x01000000 - -# define ADD_PCI_CMD CFG_CMD_PCI - -#else /* no Evaluation board */ - -# define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - -#endif - -/* USB */ -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) - -# define CONFIG_USB_OHCI -# define CONFIG_USB_CLOCK 0x0001bbbb -# if defined (CONFIG_EVAL5200) -# define CONFIG_USB_CONFIG 0x00005100 -# else -# define CONFIG_USB_CONFIG 0x00001000 -# endif -# define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -# define CONFIG_DOS_PARTITION -# define CONFIG_USB_STORAGE - -#else - -# define ADD_USB_CMD 0 - -#endif - -/* IDE */ -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) - -# define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT -# define CONFIG_DOS_PARTITION - -#else - -# define ADD_IDE_CMD 0 - -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - ADD_IDE_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_BEDBUG \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * MUST be low boot - HIGHBOOT is not supported anymore - */ -#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT16 1 -#else -# error "TEXT_BASE must be 0xff000000" -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ - -/* - * I2C configuration - */ -/* - * EEPROM configuration - */ -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 - -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_SIZE 0x2000 - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_MISC_INIT_R - -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */ - -#if defined (CONFIG_SOFT_I2C) -# define SDA0 0x40 -# define SCL0 0x80 -# define GPIOE0 *((volatile uchar*)(CFG_MBAR+0x0c00)) -# define DDR0 *((volatile uchar*)(CFG_MBAR+0x0c08)) -# define DVO0 *((volatile uchar*)(CFG_MBAR+0x0c0c)) -# define DVI0 *((volatile uchar*)(CFG_MBAR+0x0c20)) -# define ODE0 *((volatile uchar*)(CFG_MBAR+0x0c04)) -# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);} -# define I2C_READ ((DVI0&SDA0)?1:0) -# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;} -# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;} -# define I2C_DELAY {udelay(5);} -# define I2C_ACTIVE {DDR0|=SDA0;} -# define I2C_TRISTATE {DDR0&=~SDA0;} -# define CFG_I2C_SPEED 100000 -# define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_I2C_FACT_ADDR 0x57 -#endif - -#if defined (CONFIG_HARD_I2C) -# define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ -# define CFG_I2C_SPEED 100000 /* 100 kHz */ -# define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR 0x54 -#define CFG_I2C_FACT_ADDR 0x54 -#endif - -/* - * Flash configuration, expect one 16 Megabyte Bank at most - */ -#define CFG_FLASH_BASE 0xff000000 -#define CFG_FLASH_SIZE 0x01000000 -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0) - -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ - -/* - * DRAM configuration - will be read from VPD later... TODO! - */ -#if 0 -/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */ -#define CFG_DRAM_DDR 0 -#define CFG_DRAM_EMODE 0 -#define CFG_DRAM_MODE 0x008D -#define CFG_DRAM_CONTROL 0x514F0000 -#define CFG_DRAM_CONFIG1 0xC2233A00 -#define CFG_DRAM_CONFIG2 0x88B70004 -#define CFG_DRAM_TAP_DEL 0x08 -#define CFG_DRAM_RAM_SIZE 0x19 -#endif -#if 1 -/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */ -#define CFG_DRAM_DDR 0 -#define CFG_DRAM_EMODE 0 -#define CFG_DRAM_MODE 0x00CD -#define CFG_DRAM_CONTROL 0x514F0000 -#define CFG_DRAM_CONFIG1 0xD2333A00 -#define CFG_DRAM_CONFIG2 0x8AD70004 -#define CFG_DRAM_TAP_DEL 0x08 -#define CFG_DRAM_RAM_SIZE 0x19 -#endif - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ -#define CFG_ENV_OFFSET 0x1000 -#define CFG_ENV_SIZE 0x0700 - -/* - * VPD settings - */ -#define CFG_FACT_OFFSET 0x1800 -#define CFG_FACT_SIZE 0x0800 - -/* - * Memory map - * - * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 - */ -#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ -#define CONFIG_PHY_ADDR 0x1f -#define CONFIG_PHY_TYPE 0x79c874 -/* - * GPIO configuration: - * PSC1,2,3 predefined as UART - * PCI disabled - * Ethernet 100 with MD - */ -#define CFG_GPS_PORT_CONFIG 0x00058044 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x200000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */ - #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */ - #define RTC(reg) (0xf0010000+reg) - /* setup CS2 for M48T08. Must MAP 64kB */ - #define CFG_CS2_START RTC(0) - #define CFG_CS2_SIZE 0x10000 - /* setup CS2 configuration register: */ - /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */ - /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */ - #define CFG_CS2_CFG 0x00047800 -#else - #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ -#endif - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00047801 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0x7f000000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET 1 -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005c) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h deleted file mode 100644 index 2344b96..0000000 --- a/include/configs/TOP860.h +++ /dev/null @@ -1,442 +0,0 @@ -/* - * (C) Copyright 2003 - * EMK Elektronik GmbH - * Reinhard Meyer - * - * Configuation settings for the TOP860 board. - * - * ----------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* - * TOP860 is a simple module: - * 16-bit wide FLASH on CS0 (2MB or more) - * 32-bit wide DRAM on CS2 (either 4MB or 16MB) - * FEC with Am79C874 100-Base-T and Fiber Optic - * Ports available, but we choose SMC1 for Console - * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set - * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock - * - * This config has been copied from MBX.h / MBX860T.h - */ -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/*----------------------------------------------------------------------- - * CPU and BOARD type - */ -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_MPC860T 1 /* even better... an FEC! */ -#define CONFIG_TOP860 1 /* ...on a TOP860 module */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_IDENT_STRING " EMK TOP860" - -/*----------------------------------------------------------------------- - * CLOCK settings - */ -#define CONFIG_SYSCLK 49152000 -#define CFG_XTAL 32768 -#define CONFIG_EBDF 1 -#define CONFIG_COM 3 -#define CONFIG_RTC_MPC8xx - -/*----------------------------------------------------------------------- - * Physical memory map as defined by EMK - */ -#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register */ -#define CFG_FLASH_BASE 0x80000000 /* FLASH in final mapping */ -#define CFG_DRAM_BASE 0x00000000 /* DRAM in final mapping */ -#define CFG_FLASH_MAX 0x00400000 /* max FLASH to expect */ -#define CFG_DRAM_MAX 0x01000000 /* max DRAM to expect */ - -/*----------------------------------------------------------------------- - * derived values - */ -#define CFG_MF (CONFIG_SYSCLK/CFG_XTAL) -#define CFG_CPUCLOCK CONFIG_SYSCLK -#define CFG_BRGCLOCK CONFIG_SYSCLK -#define CFG_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF) -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_CFI - -/*----------------------------------------------------------------------- - * Command interpreter - */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_BAUDRATE 9600 - -/* - * Allow partial commands to be matched to uniqueness. - */ -#define CFG_MATCH_PARTIAL_CMD - -/* - * List of available monitor commands. Use the system default list - * plus add some of the "non-standard" commands back in. - * See ./cmd_confdefs.h - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_BEDBUG \ - ) - -#define CONFIG_AUTOSCRIPT 1 -#define CFG_LOADS_BAUD_CHANGE 1 -#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* Hush parse for U-Boot */ - -#ifdef CFG_HUSH_PARSER - #define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test Command - */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Environment handler - * only the first 6k in EEPROM are available for user. Of that we use 256b - */ -#define CONFIG_SOFT_I2C -#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ -#define CFG_ENV_OFFSET 0x1000 -#define CFG_ENV_SIZE 0x0700 -#define CFG_I2C_EEPROM_ADDR 0x57 -#define CFG_FACT_OFFSET 0x1800 -#define CFG_FACT_SIZE 0x0800 -#define CFG_I2C_FACT_ADDR 0x57 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_SIZE 0x2000 -#define CFG_I2C_SPEED 100000 -#define CFG_I2C_SLAVE 0xFE -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 -#define CONFIG_ENV_OVERWRITE -#define CONFIG_MISC_INIT_R - -#if defined (CONFIG_SOFT_I2C) -#define SDA 0x00010 -#define SCL 0x00020 -#define __I2C_DIR immr->im_cpm.cp_pbdir -#define __I2C_DAT immr->im_cpm.cp_pbdat -#define __I2C_PAR immr->im_cpm.cp_pbpar -#define __I2C_ODR immr->im_cpm.cp_pbodr -#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ - __I2C_ODR &= ~(SDA|SCL); \ - __I2C_DAT |= (SDA|SCL); \ - __I2C_DIR|=(SDA|SCL); } -#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) -#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } -#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } -#define I2C_DELAY { udelay(5); } -#define I2C_ACTIVE { __I2C_DIR |= SDA; } -#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } -#endif - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/*----------------------------------------------------------------------- - * defines we need to get FEC running - */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ -#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ -#define FEC_ENET 1 /* eth.c needs it that way... */ -#define CFG_DISCOVER_PHY 1 -#define CONFIG_MII 1 -#define CONFIG_PHY_ADDR 31 - -/*----------------------------------------------------------------------- - * adresses - */ -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x80000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ -#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) -#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*----------------------------------------------------------------------- - * Debug Enable Register - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 /* used in start.S */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set up PLPRCR (PLL, Low-Power, and Reset Control Register) - * 12 MF calculated Multiplication factor - * 4 0 0000 - * 1 SPLSS 0 System PLL lock status sticky - * 1 TEXPS 1 Timer expired status - * 1 0 0 - * 1 TMIST 0 Timers interrupt status - * 1 0 0 - * 1 CSRC 0 Clock source (0=DFNH, 1=DFNL) - * 2 LPM 00 Low-power modes - * 1 CSR 0 Checkstop reset enable - * 1 LOLRE 0 Loss-of-lock reset enable - * 1 FIOPD 0 Force I/O pull down - * 5 0 00000 - */ -#define CFG_PLPRCR (PLPRCR_TEXPS | ((CFG_MF-1)<<20)) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * set up SYPCR: - * 16 SWTC 0xffff Software watchdog timer count - * 8 BMT 0xff Bus monitor timing - * 1 BME 1 Bus monitor enable - * 3 0 000 - * 1 SWF 1 Software watchdog freeze - * 1 SWE 0/1 Software watchdog enable - * 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET) - * 1 SWP 0/1 Software watchdog prescale (1=/2048) - */ -#if defined (CONFIG_WATCHDOG) - #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else - #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * set up SIUMCR - * 1 EARB 0 External arbitration - * 3 EARP 000 External arbitration request priority - * 4 0 0000 - * 1 DSHW 0 Data show cycles - * 2 DBGC 00 Debug pin configuration - * 2 DBPC 00 Debug port pins configuration - * 1 0 0 - * 1 FRC 0 FRZ pin configuration - * 1 DLK 0 Debug register lock - * 1 OPAR 0 Odd parity - * 1 PNCS 0 Parity enable for non memory controller regions - * 1 DPC 0 Data parity pins configuration - * 1 MPRE 0 Multiprocessor reservation enable - * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT) - * 1 AEME 0 Async external master enable - * 1 SEME 0 Sync external master enable - * 1 BSC 0 Byte strobe configuration - * 1 GB5E 0 GPL_B5 enable - * 1 B2DD 0 Bank 2 double drive - * 1 B3DD 0 Bank 3 double drive - * 4 0 0000 - */ -#define CFG_SIUMCR (SIUMCR_MLRC11) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * set up SCCR (System Clock and Reset Control Register) - * 1 0 0 - * 2 COM 11 Clock output module (00=full, 01=half, 11=off) - * 3 0 000 - * 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2) - * 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512) - * 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK) - * 1 CRQEN 0 CPM request enable - * 1 PRQEN 0 Power management request enable - * 2 0 00 - * 2 EBDF xx External bus division factor - * 2 0 00 - * 2 DFSYNC 00 Division factor for SYNCLK - * 2 DFBRG 00 Division factor for BRGCLK - * 3 DFNL 000 Division factor low frequency - * 3 DFNH 000 Division factor high frequency - * 5 0 00000 - */ -#define SCCR_MASK 0 -#ifdef CONFIG_EBDF - #define CFG_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01) -#else - #define CFG_SCCR (SCCR_COM11 | SCCR_TBS) -#endif - -/*----------------------------------------------------------------------- - * Chip Select 0 - FLASH - *----------------------------------------------------------------------- - * Preliminary Values - */ -/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR) -#define CFG_OR0_PRELIM (-CFG_FLASH_MAX | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V ) - -/*----------------------------------------------------------------------- - * misc - *----------------------------------------------------------------------- - * - */ -/* - * Set the autoboot delay in seconds. A delay of -1 disables autoboot - */ -#define CONFIG_BOOTDELAY 5 - -/* - * Pass the clock frequency to the Linux kernel in units of MHz - */ -#define CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_PREBOOT \ - "echo;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* - * BOOTP options - */ -#undef CONFIG_BOOTP_MASK -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE \ - ) - - -/* - * Set default IP stuff just to get bootstrap entries into the - * environment so that we can autoscript the full default environment. - */ -#define CONFIG_ETHADDR 9a:52:63:15:85:25 -#define CONFIG_SERVERIP 10.0.4.200 -#define CONFIG_IPADDR 10.0.4.111 - -/*----------------------------------------------------------------------- - * Defaults for Autoscript - */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_TFTP_LOADADDR 0x00100000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h deleted file mode 100644 index 5ad1939..0000000 --- a/include/configs/TQM5200.h +++ /dev/null @@ -1,564 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ -#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_STK52XX -#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ -#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ -#define CONFIG_BOARD_EARLY_INIT_R -#endif /* CONFIG_STK52XX */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#ifdef CONFIG_STK52XX -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_NET_MULTI 1 -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif /* CONFIG_STK52XX */ - -#ifdef CONFIG_PCI -#define ADD_PCI_CMD CFG_CMD_PCI -#else -#define ADD_PCI_CMD 0 -#endif - -/* - * Video console - */ -#if 1 -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CFG_CONSOLE_IS_IN_ENV -#endif - -#ifdef CONFIG_VIDEO -#define ADD_BMP_CMD CFG_CMD_BMP -#else -#define ADD_BMP_CMD 0 -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* USB */ -#ifdef CONFIG_STK52XX -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 -#endif - -/* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -/* IDE */ -#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) -#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) -#else -#define ADD_IDE_CMD 0 -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - ADD_IDE_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP | \ - CFG_CMD_BSP) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#if defined (CONFIG_TQM5200_AA) -# define CONFIG_U_BOOT_SUFFIX "-AA\0" -#elif defined (CONFIG_TQM5200_AB) -# define CONFIG_U_BOOT_SUFFIX "-AB\0" -#elif defined (CONFIG_TQM5200_AC) -# define CONFIG_U_BOOT_SUFFIX "-AC\0" -#else -# define CONFIG_U_BOOT_SUFFIX "\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ - -#if defined(CFG_IPBSPEED_133) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. - */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CFG_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * HW-Monitor configuration on Mini-FAP - */ -#if defined (CONFIG_MINIFAP) -#define CFG_I2C_HWMON_ADDR 0x2C -#endif - -/* List of I2C addresses to be verified by POST */ -#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB) -#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ - CFG_I2C_SLAVE } -#elif defined (CONFIG_TQM5200_AC) -#define I2C_ADDR_LIST { CFG_I2C_SLAVE } -#endif - -#if defined (CONFIG_MINIFAP) -#undef I2C_ADDR_LIST -#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ - CFG_I2C_HWMON_ADDR, \ - CFG_I2C_SLAVE } -#endif - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CFG_LOWBOOT) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CFG_LOWBOOT */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) -#endif /* CFG_LOWBOOT */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Dynamic MTD partition support */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM5200-0" -#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "16m(big-fs)," \ - "8m(misc)" - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#if defined (CONFIG_MINIFAP) -# define CFG_GPS_PORT_CONFIG 0x91000004 -#elif defined (CONFIG_STK52XX) -# if defined (CONFIG_STK52XX_REV100) -# define CFG_GPS_PORT_CONFIG 0x81500014 -# else /* STK52xx REV200 and above */ -# if defined (CONFIG_TQM5200_REV100) -# error TQM5200 REV100 not supported on STK52XX REV200 or above -# else/* TQM5200 REV200 and above */ -# define CFG_GPS_PORT_CONFIG 0x91500004 -# endif -# endif -#else /* TMQ5200 Inbetriebnahme-Board */ -# define CFG_GPS_PORT_CONFIG 0x81000004 -#endif - -/* - * RTC configuration - */ -#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100) -# define CONFIG_RTC_M41T11 1 -# define CFG_I2C_RTC_ADDR 0x68 -#else -# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CFG_ALT_MEMTEST - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 -#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -/* automatic configuration of chip selects */ -#ifdef CONFIG_CS_AUTOCONF -#define CONFIG_LAST_STAGE_INIT -#endif - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF) -#define CFG_CS2_START 0xE5000000 -#ifdef CONFIG_TQM5200_AB -#define CFG_CS2_SIZE 0x80000 /* 512 kByte */ -#else /* CONFIG_CS_AUTOCONF */ -#define CFG_CS2_SIZE 0x100000 /* 1 MByte */ -#endif -#define CFG_CS2_CFG 0x0004D930 -#endif - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \ - defined (CONFIG_CS_AUTOCONF) -#define SM501_FB_BASE 0xE0000000 -#define CFG_CS1_START (SM501_FB_BASE) -#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CFG_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 -#endif - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CFG_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h deleted file mode 100644 index b1c70f8..0000000 --- a/include/configs/TQM823L.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM823L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if defined(CONFIG_LCD) -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#ifdef CONFIG_SPLASH_SCREEN -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BMP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#else -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h deleted file mode 100644 index 9f958f5..0000000 --- a/include/configs/TQM823M.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM823M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_LCD -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h deleted file mode 100644 index 49c3872..0000000 --- a/include/configs/TQM8260.h +++ /dev/null @@ -1,639 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Imported from global configuration: - * CONFIG_MPC8255 - * CONFIG_MPC8265 - * CONFIG_200MHz - * CONFIG_266MHz - * CONFIG_300MHz - * CONFIG_L2_CACHE - * CONFIG_BUSMODE_60x - */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ - -#if 0 -#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ -#else -#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ -#endif - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/TQM8260/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */ -#if (CONFIG_TQM8260 <= 100) - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00020000) -#define I2C_TRISTATE (iop->pdir &= ~0x00020000) -#define I2C_READ ((iop->pdat & 0x00020000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#else - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * - * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) -# define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */ -# ifndef CONFIG_300MHz -# define CONFIG_8260_CLKIN 66666666 /* in Hz */ -# else -# define CONFIG_8260_CLKIN 83333000 /* in Hz */ -# endif -#endif /* CONFIG_MPC8255 */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CFG_FLASH0_BASE 0x40000000 -#define CFG_FLASH1_BASE 0x60000000 -#define CFG_FLASH0_SIZE 32 -#define CFG_FLASH1_SIZE 32 - -/* Flash bank size (for preliminary settings) - */ -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to EEPROM later */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) -#define CFG_ENV_SIZE 0x40000 -#define CFG_ENV_SECT_SIZE 0x40000 -#else -/* Final version: environment in EEPROM */ -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 2048 -#endif - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) - -#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) -# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -#else /* ! MPC8255 && !MPC8265 */ -# if defined(CONFIG_266MHz) -# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -# elif defined(CONFIG_300MHz) -# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110) -# else -# define CFG_HRCW_MASTER (__HRCW__ALL__) -# endif -#endif /* CONFIG_MPC8255 */ - -/* no slaves so just fill with zeros */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#ifdef CONFIG_BUSMODE_60x -#define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ - BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ -#else -#define BCR_APD01 0x10000000 -#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#else -#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 Local SDRAM 32 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CFG_INIT_LOCAL_SDRAM - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ -#define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ - -#define CFG_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CFG_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - - /* SDRAM on TQM8260 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CFG_PSRT 0x20 -#define CFG_LSRT 0x20 -#ifndef CFG_RAMBOOT -#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM CFG_OR1_8COL - - - /* SDRAM initialization values for 8-column chips - */ -#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CFG_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CFG_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - -/* Bank 2 - Local bus SDRAM - */ -#ifdef CFG_INIT_LOCAL_SDRAM -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -#define CFG_OR2_PRELIM CFG_OR2_8COL - -#define SDRAM_BASE2_PRELIM 0x80000000 - - /* SDRAM initialization values for 8-column chips - */ -#define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A8 |\ - ORxS_NUMR_12) - -#define CFG_LSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_13) - -#define CFG_LSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - -#endif /* CFG_INIT_LOCAL_SDRAM */ - -#endif /* CFG_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h deleted file mode 100644 index 41f44c5..0000000 --- a/include/configs/TQM834x.h +++ /dev/null @@ -1,511 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * TQM8349 board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define DEBUG -#undef DEBUG - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC834X 1 /* MPC834X specific */ -#define CONFIG_TQM834X 1 /* TQM834X board specific */ - -/* IMMR Base Addres Register, use Freescale default: 0xff400000 */ -#define CFG_IMMRBAR 0xff400000 - -/* System clock. Primary input clock when in PCI host mode */ -#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ - -/* - * Local Bus LCRR - * LCRR: DLL bypass, Clock divider is 8 - * - * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz - * - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) - -/* board pre init: do not call, nothing to do */ -#undef CONFIG_BOARD_EARLY_INIT_F - -/* detect the number of flash banks */ -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * DDR Setup - */ -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#define DDR_CASLAT_25 /* CASLAT set to 2.5 */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00000000 /* memtest region */ -#define CFG_MEMTEST_END 0x00100000 - -/* - * FLASH on the Local Bus - */ -#define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ - -/* buffered writes in the AMD chip set is not supported yet */ -#undef CFG_FLASH_USE_BUFFER_WRITE - -/* - * FLASH bank number detection - */ - -/* - * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash - * banks has to be determined at runtime and stored in a gloabl variable - * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only - * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and - * should be made sufficiently large to accomodate the number of banks that - * might actually be detected. Since most (all?) Flash related functions use - * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is - * defined as tqm834x_num_flash_banks. - */ -#define CFG_MAX_FLASH_BANKS_DETECT 2 -#ifndef __ASSEMBLY__ -extern int tqm834x_num_flash_banks; -#endif -#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks) - -#define CFG_MAX_FLASH_SECT 512 /* max sectors per device */ - -/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \ - BR_MS_GPCM | BR_PS_32 | BR_V) - -/* FLASH timing (0x0000_0c54) */ -#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ - OR_GPCM_SCY_5 | OR_GPCM_TRLX) - -#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) - -#define CFG_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */ - -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ - -/* disable remaining mappings */ -#define CFG_BR1_PRELIM 0x00000000 -#define CFG_OR1_PRELIM 0x00000000 -#define CFG_LBLAWBAR1_PRELIM 0x00000000 -#define CFG_LBLAWAR1_PRELIM 0x00000000 - -#define CFG_BR2_PRELIM 0x00000000 -#define CFG_OR2_PRELIM 0x00000000 -#define CFG_LBLAWBAR2_PRELIM 0x00000000 -#define CFG_LBLAWAR2_PRELIM 0x00000000 - -#define CFG_BR3_PRELIM 0x00000000 -#define CFG_OR3_PRELIM 0x00000000 -#define CFG_LBLAWBAR3_PRELIM 0x00000000 -#define CFG_LBLAWAR3_PRELIM 0x00000000 - -#define CFG_BR4_PRELIM 0x00000000 -#define CFG_OR4_PRELIM 0x00000000 -#define CFG_LBLAWBAR4_PRELIM 0x00000000 -#define CFG_LBLAWAR4_PRELIM 0x00000000 - -#define CFG_BR5_PRELIM 0x00000000 -#define CFG_OR5_PRELIM 0x00000000 -#define CFG_LBLAWBAR5_PRELIM 0x00000000 -#define CFG_LBLAWAR5_PRELIM 0x00000000 - -#define CFG_BR6_PRELIM 0x00000000 -#define CFG_OR6_PRELIM 0x00000000 -#define CFG_LBLAWBAR6_PRELIM 0x00000000 -#define CFG_LBLAWAR6_PRELIM 0x00000000 - -#define CFG_BR7_PRELIM 0x00000000 -#define CFG_OR7_PRELIM 0x00000000 -#define CFG_LBLAWBAR7_PRELIM 0x00000000 -#define CFG_LBLAWAR7_PRELIM 0x00000000 - -/* - * Monitor config - */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ - -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) - -/* - * I2C - */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ -#define CFG_I2C_SLAVE 0x7F /* slave address */ -#define CFG_I2C_OFFSET 0x3000 - -/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ -#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -/* - * TSEC - */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_MII - -#define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET) -#define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET) - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI -#endif - -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_PCI - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -/* PCI1 host bridge */ -#define CFG_PCI1_MEM_BASE 0xc0000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - - -#undef CONFIG_EEPRO100 -#define CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE - #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE - #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ -#endif - -#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * Environment - */ -#define CONFIG_ENV_OVERWRITE - -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* Common commands */ -#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\ - | CFG_CMD_PING | CFG_CMD_EEPROM \ - | CFG_CMD_MII | CFG_CMD_JFFS2 - -#if defined(CFG_RAMBOOT) - -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \ - | CFG_CMD_TQM8349_COMMON) \ - & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS)) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_TQM8349_COMMON) \ - & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS)) -#endif - -#else /* CFG_RAMBOOT */ - -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ - | CFG_CMD_TQM8349_COMMON) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_TQM8349_COMMON) -#endif - -#endif /* CFG_RAMBOOT */ - -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -#define CFG_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(PCI_64BIT) -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#else -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#endif - -/* i-cache and d-cache disabled */ -#define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL CFG_HID0_INIT -#define CFG_HID2 0x000000000 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR D2:DA:5E:44:BC:29 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 -#endif - -#define CONFIG_IPADDR 192.168.205.1 - -#define CONFIG_HOSTNAME tqm8349 -#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx -#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=tqm83xx\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/tqm83xx/uImage\0" \ - "kernel_addr=80060000\0" \ - "ramdisk_addr=80160000\0" \ - "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \ - "update=protect off 80000000 8003ffff; " \ - "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ - "upd=run load;run update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * JFFS2 partitions - */ -/* mtdparts command line support */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM834x-0" - -/* default mtd partition table */ -#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\ - "1m(kernel),2m(initrd),"\ - "-(user);"\ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h deleted file mode 100644 index 16b2ce3..0000000 --- a/include/configs/TQM850L.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM850L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h deleted file mode 100644 index bbc6960..0000000 --- a/include/configs/TQM850M.h +++ /dev/null @@ -1,433 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM850M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h deleted file mode 100644 index 198db19..0000000 --- a/include/configs/TQM855L.h +++ /dev/null @@ -1,441 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM855L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h deleted file mode 100644 index e25a7a2..0000000 --- a/include/configs/TQM855M.h +++ /dev/null @@ -1,476 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM855M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#if 0 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 -#endif - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h deleted file mode 100644 index 18197f2..0000000 --- a/include/configs/TQM85xx.h +++ /dev/null @@ -1,452 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Wolfgang Denk - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * TQM85xx (8560/40/55/41) board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ - -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -/* - * Only MPC8540 doesn't have CPM module - */ -#ifndef CONFIG_MPC8540 -#define CONFIG_CPM2 1 /* has CPM2 */ -#endif - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33333333 -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00000000 -#define CFG_MEMTEST_END 0x10000000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/ - -#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) -/* TQM8540 & 8560 need DLL-override */ -#define CONFIG_DDR_DLL /* DLL fix needed */ -#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ -#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */ - -#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) -#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ -#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */ - -/* - * Flash on the Local Bus - */ -#define CFG_FLASH0 0xFC000000 -#define CFG_FLASH1 0xF8000000 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } - -#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ -#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ - -#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ -#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ -#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ -#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */ - -#define CFG_FLASH_CFI /* flash is CFI compat. */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ -#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ - -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#if defined(CONFIG_TQM8560) - -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#else - -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) - -#endif /* CONFIG_TQM8560 */ - -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C EEPROM */ -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also). - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -/* RapidIO MMU */ -#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#define CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#define CONFIG_NET_MULTI 1 - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define FEC_PHY_ADDR 3 -#define FEC_PHYIDX 0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 - -/* Options are TSEC[0-1], FEC */ -#define CONFIG_ETHPRIME "TSEC0" - -#if defined(CONFIG_TQM8540) -/* - * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC. - * The FEC port is connected on the same signals as the FCC3 port - * of the TQM8560 to the baseboard (STK85xx Starterkit). - * - * On the STK85xx Starterkit the X47/X50 jumper has to be set to - * a - d (X50.2 - 3) to enable the FEC port. - */ -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#endif - -#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) -/* - * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port - * can be used at once, since only one FCC port is available on the STK85xx - * Starterkit. - * - * To use this port you have to configure U-Boot to use the FCC port 1...2 - * and set the X47/X50 jumper to: - * FCC1: a - b (X47.2 - X50.2) - * FCC2: a - c (X50.2 - 1) - */ -#define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ -#endif - -#if defined(CONFIG_TQM8560) -/* - * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port - * can be used at once, since only one FCC port is available on the STK85xx - * Starterkit. - * - * To use this port you have to configure U-Boot to use the FCC port 1...3 - * and set the X47/X50 jumper to: - * FCC1: a - b (X47.2 - X50.2) - * FCC2: a - c (X50.2 - 1) - * FCC3: a - d (X50.2 - 3) - */ -#define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) -#define CONFIG_ETHER_ON_FCC1 -#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) -#define CONFIG_ETHER_ON_FCC2 -#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) -#define CONFIG_ETHER_ON_FCC3 -#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) -#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif - -/* - * Environment - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) -#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_TIMESTAMP /* Print image info with ts */ - -#if defined(CONFIG_PCI) -# define ADD_PCI_CMD (CFG_CMD_PCI) -#else -# define ADD_PCI_CMD 0 -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - ADD_PCI_CMD | \ - CFG_CMD_I2C | \ - CFG_CMD_DATE | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DTT | \ - CFG_CMD_MII | \ - CFG_CMD_PING ) -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CFG_BOOTFILE \ - "netdev=eth0\0" \ - "consdev=ttyS0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm $kernel_addr\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp $loadaddr $bootfile;" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_85xx\0" \ - "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE100000\0" \ - "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h deleted file mode 100644 index 4a1a432..0000000 --- a/include/configs/TQM860L.h +++ /dev/null @@ -1,444 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -#define CONFIG_NETCONSOLE - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h deleted file mode 100644 index 4b754ba..0000000 --- a/include/configs/TQM860M.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h deleted file mode 100644 index 1dc9f74..0000000 --- a/include/configs/TQM862L.h +++ /dev/null @@ -1,447 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM862L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 - -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_NET_MULTI -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h deleted file mode 100644 index 3df060c..0000000 --- a/include/configs/TQM862M.h +++ /dev/null @@ -1,448 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM862M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 - -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_NET_MULTI -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h deleted file mode 100644 index 8f9c2c9..0000000 --- a/include/configs/TQM866M.h +++ /dev/null @@ -1,461 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC866 1 /* This is a MPC866 CPU */ -#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#undef CFG_MEASURE_CPUCLK /* Measure real cpu clock */ - /* (function measure_gclk() */ - /* will be called) */ -#ifdef CFG_MEASURE_CPUCLK -#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM866M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CFG_OR3_PRELIM CFG_OR2_PRELIM -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Memory Periodic Timer Prescaler - * Periodic timer for refresh, start with refresh rate for 40 MHz clock - * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) - */ -#define CFG_MAMR_PTA 39 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC ETHERNET" - -#endif /* __CONFIG_H */ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h deleted file mode 100644 index 8175703..0000000 --- a/include/configs/Total5200.h +++ /dev/null @@ -1,415 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Check valid setting of revision define. - * Total5100 and Total5200 Rev.1 are identical except for the processor. - */ -#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2) -#error CONFIG_TOTAL5200_REV must be 1 or 2 -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Video console - */ -#if 1 -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SED13806 -#define CONFIG_VIDEO_SED13806_16BPP - -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -/* #define CONFIG_VIDEO_BMP_LOGO */ -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN - -#define ADD_VIDEO_CMD CFG_CMD_BMP -#else -#define ADD_VIDEO_CMD 0 -#endif - -#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */ -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_NET_MULTI 1 -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 - -#define ADD_PCI_CMD CFG_CMD_PCI - -#else /* MGT5100 */ - -#define CONFIG_MII 1 -#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 1 -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_IDE | \ - ADD_VIDEO_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#if (TEXT_BASE == 0xFE000000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT \ - "setenv stdout serial;setenv stderr serial;" \ - "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if defined(CONFIG_MPC5200) -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * Flash configuration - */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if CONFIG_TOTAL5200_REV==2 -# define CFG_MAX_FLASH_BANKS 3 /* max num of flash banks */ -# define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START } -#else -# define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -# define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#endif -#define CFG_FLASH_EMPTY_INFO -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#if CONFIG_TOTAL5200_REV==1 -# define CFG_FLASH_BASE 0xFE000000 -# define CFG_FLASH_SIZE 0x02000000 -#elif CONFIG_TOTAL5200_REV==2 -# define CFG_FLASH_BASE 0xFA000000 -# define CFG_FLASH_SIZE 0x06000000 -#endif /* CONFIG_TOTAL5200_REV */ - -#if defined(CFG_LOWBOOT) -# define CFG_ENV_ADDR 0xFE040000 -#else /* CFG_LOWBOOT */ -# define CFG_ENV_ADDR 0xFFF40000 -#endif /* CFG_LOWBOOT */ - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x40000 -#define CFG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 -#define CFG_MBAR 0xF0000000 /* 64 kB */ -#define CFG_FPGA_BASE 0xF0010000 /* 64 kB */ -#define CFG_CPLD_BASE 0xF0020000 /* 64 kB */ -#define CFG_LCD_BASE 0xF1000000 /* 4096 kB */ - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* dummy, 7-wire FEC does not have phy address */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0 - * Reserved 0 - * ALTs: CAN1/2 on PSC2, SPI on PSC3 00 - * CS7: Interrupt GPIO on PSC3_5 0 - * CS8: Interrupt GPIO on PSC3_4 0 - * ATA: reset default, changed in ATA driver 00 - * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0 - * IRDA: reset default, changed in IrDA driver 000 - * ETHER: reset default, changed in Ethernet driver 0000 - * PCI_DIS: reset default, changed in PCI driver 0 - * USB_SE: reset default, changed in USB driver 0 - * USB: reset default, changed in USB driver 00 - * PSC3: SPI and UART functionality without CD 1100 - * Reserved 0 - * PSC2: CAN1/2 001 - * Reserved 0 - * PSC1: reset default, changed in AC'97 driver 000 - * - */ -#define CFG_GPS_PORT_CONFIG 0x00000C10 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#if defined (CONFIG_MGT5100) -# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */ -#endif - -#if CONFIG_TOTAL5200_REV==1 -# define CFG_BOOTCS_START CFG_FLASH_BASE -# define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */ -# define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CFG_CS0_START CFG_FLASH_BASE -# define CFG_CS0_SIZE 0x02000000 /* 32 MB */ -#else -# define CFG_BOOTCS_START (CFG_CS4_START + CFG_CS4_SIZE) -# define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */ -# define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CFG_CS4_START (CFG_CS5_START + CFG_CS5_SIZE) -# define CFG_CS4_SIZE 0x02000000 /* 32 MB */ -# define CFG_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -# define CFG_CS5_START CFG_FLASH_BASE -# define CFG_CS5_SIZE 0x02000000 /* 32 MB */ -# define CFG_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */ -#endif - -#define CFG_CS1_START CFG_FPGA_BASE -#define CFG_CS1_SIZE 0x00010000 /* 64 kB */ -#define CFG_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */ - -#define CFG_CS2_START CFG_LCD_BASE -#define CFG_CS2_SIZE 0x00400000 /* 4096 kB */ -#define CFG_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */ - -#if CONFIG_TOTAL5200_REV==1 -# define CFG_CS3_START CFG_CPLD_BASE -# define CFG_CS3_SIZE 0x00010000 /* 64 kB */ -# define CFG_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */ -#else -# define CFG_CS3_START CFG_CPLD_BASE -# define CFG_CS3_SIZE 0x00010000 /* 64 kB */ -# define CFG_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */ -#endif - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h deleted file mode 100644 index 3f29190..0000000 --- a/include/configs/VCMA9.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * (C) Copyright 2002, 2003 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Gary Jennejohn - * David Mueller - * - * Configuation settings for the MPL VCMA9 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ - -#define USE_920T_MMU 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/*********************************************************** - * Command definition - ***********************************************************/ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - /*CFG_CMD_JFFS2 |*/ \ - /*CFG_CMD_NAND |*/ \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_USB | \ - CFG_CMD_REGINFO | \ - CFG_CMD_FAT | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_BSP) - -/* this must be included after the definiton of CONFIG_COMMANDS */ -#include - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -/*********************************************************** - * I2C stuff: - * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at - * address 0x50 with 16bit addressing - ***********************************************************/ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ - -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ -#define CFG_ENV_SIZE 0x800 /* 2KB should be more than enough */ - -#undef CFG_I2C_EEPROM_ADDR_OVERFLOW -#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * Size of malloc() pool - */ -/*#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)*/ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CFG_MONITOR_LEN (256 * 1024) -#define CFG_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x20000300 -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ - -#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ - -/************************************************************ - * USB support - ************************************************************/ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 - -/* Enable needed helper functions */ -#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ - -/************************************************************ - * RTC - ************************************************************/ -#define CONFIG_RTC_S3C24X0 1 - - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.0.110 -#define CONFIG_SERVERIP 10.0.0.1 - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "VCMA9 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ - -#define CFG_ALT_MEMTEST -#define CFG_LOAD_ADDR 0x30800000 /* default load address */ - - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/* we configure PWM Timer 4 to 1us ~ 1MHz */ -/*#define CFG_HZ 1000000 */ -#define CFG_HZ 1562500 - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* support BZIP2 compression */ -#define CONFIG_BZIP2 1 - -/************************************************************ - * Ident - ************************************************************/ -/*#define VERSION_TAG "released"*/ -#define VERSION_TAG "unstable" -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ -#endif - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ - -#if 0 -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#endif - - -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS 1 - -#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 - -/*----------------------------------------------------------------------- - * NAND flash settings - */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define NAND_WAIT_READY(nand) NF_WaitRB() - -#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) -#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW) - - -#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d) -#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d) -#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d) -#define WRITE_NAND(d, adr) NF_Write(d) -#define READ_NAND(adr) NF_Read() -/* the following functions are NOP's because S3C24X0 handles this in hardware */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) - -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 -#define CONFIG_MTD_NAND_ECC_JFFS2 1 - -#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h deleted file mode 100644 index 3ca137e..0000000 --- a/include/configs/VOH405.h +++ /dev/null @@ -1,457 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_VOH405 1 /* ...on a VOH405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_SUPPORT_VFAT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ - -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CONFIG_ATAPI 1 /* ATAPI for Travelstar */ - -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_IDE1_OFFSET 0x0010 - -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */ - -#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CFG_RAMBOOT 1 -#else -# undef CFG_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#if 0 /* test-only */ -/* CAT24WC08/16... */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#else -/* CAT24WC32/64... */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#endif -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ -#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (Epson VGA) initialization */ -#define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ -#define CFG_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * LCD Setup - */ - -#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ -#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ -#define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ -#define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ - -#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20) - -/*----------------------------------------------------------------------- - * FPGA stuff - */ - -#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ - -/* FPGA internal regs */ -#define CFG_FPGA_CTRL 0x000 - -/* FPGA Control Reg */ -#define CFG_FPGA_CTRL_CF_RESET 0x0001 -#define CFG_FPGA_CTRL_WDI 0x0002 -#define CFG_FPGA_CTRL_PS2_RESET 0x0020 - -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO - */ -#define CFG_GPIO0_OSRH 0x40000550 -#define CFG_GPIO0_OSRL 0x00000110 -#define CFG_GPIO0_ISR1H 0x00000000 -#define CFG_GPIO0_ISR1L 0x15555440 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FE0017 - -#define CFG_DUART_RST (0x80000000 >> 14) -#define CFG_LCD_ENDIAN (0x80000000 >> 7) -#define CFG_LCD0_RST (0x80000000 >> 30) -#define CFG_LCD1_RST (0x80000000 >> 31) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 1 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h deleted file mode 100644 index f2f3ea7..0000000 --- a/include/configs/VOM405.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_VOM405 1 /* ...on a VOM405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_NET_MULTI 1 -#undef CONFIG_HAS_ETH1 - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_BSP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#undef CONFIG_PRAM /* no "protected RAM" */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM) -# define CFG_RAMBOOT 1 -#else -# undef CFG_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ -/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ -/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ -/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CFG_GPIO0_OSRH 0x40000500 /* 0 ... 15 */ -#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ -#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ -#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ -#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ -#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ -#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h deleted file mode 100644 index 92bade5..0000000 --- a/include/configs/VoVPN-GW.h +++ /dev/null @@ -1,406 +0,0 @@ -/* - * (C) Copyright 2004 - * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de) - * - * Support for the Elmeg VoVPN Gateway Module - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* define cpu used */ -#define CONFIG_MPC8272 1 - -/* define busmode: 8260 */ -#undef CONFIG_BUSMODE_60x - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifdef CONFIG_CLKIN_66MHz -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 100000000 /* in Hz */ -#endif - -/* call board_early_init_f */ -#define CONFIG_BOARD_EARLY_INIT_F 1 - -/* have misc_init_r() function */ -#define CONFIG_MISC_INIT_R 1 - -/* have reset_phy_r() function */ -#define CONFIG_RESET_PHY_R 1 - -/* have special reset function */ -#define CONFIG_HAVE_OWN_RESET 1 - -/* allow serial and ethaddr to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* watchdog disabled */ -#undef CONFIG_WATCHDOG - -/* include support for bzip2 compressed images */ -#undef CONFIG_BZIP2 - -/* status led */ -#undef CONFIG_STATUS_LED /* XXX jse */ - -/* vendor parameter protection */ -#define CONFIG_ENV_OVERWRITE - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC -#undef CONFIG_CONS_ON_SCC -#undef CONFIG_CONS_NONE -#define CONFIG_CONS_INDEX 1 - -/* serial port default baudrate */ -#define CONFIG_BAUDRATE 115200 - -/* echo on for serial download */ -#define CONFIG_LOADS_ECHO 1 - -/* don't allow baudrate change */ -#undef CFG_LOADS_BAUD_CHANGE - -/* supported baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_ON_FCC -#undef CONFIG_ETHER_NONE - -#ifdef CONFIG_ETHER_ON_FCC - -/* which SCC/FCC channel for ethernet */ -#define CONFIG_ETHER_INDEX 1 - -/* Marvell Switch SMI base addr */ -#define CFG_PHY_ADDR 0x10 - -/* FCC1 RMII REFCLK is CLK10 */ -#define CFG_CMXFCR_VALUE CMXFCR_TF1CS_CLK10 -#define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_TF1CS_MSK) - -/* BDs and buffers on 60x bus */ -#define CFG_CPMFCR_RAMTYPE 0 - -/* Local Protect, Full duplex, Flowcontrol, RMII */ -#define CFG_FCC_PSMR (FCC_PSMR_LPB|FCC_PSMR_FDE|\ - FCC_PSMR_FCE|FCC_PSMR_RMII) - -/* bit-bang MII PHY management */ -#define CONFIG_BITBANGMII - -#define MDIO_PORT 1 /* Port B */ -#define CFG_MDIO_PIN 0x00002000 /* PB18 */ -#define CFG_MDC_PIN 0x00001000 /* PB19 */ -#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) -#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ - else iop->pdat &= ~CFG_MDIO_PIN -#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ - else iop->pdat &= ~CFG_MDC_PIN -#define MIIDELAY udelay(1) - -#endif - -/* configure commands */ -#define CONFIG_COMMANDS ( CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_BDI | \ - CFG_CMD_CONSOLE | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IMLS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_RUN ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * boot options & environment - */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "run flash_self" -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ -"clean_nv=erase fff20000 ffffffff\0" \ -"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \ -"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \ -"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \ -"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \ -"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ -"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \ -"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \ -"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \ -"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \ -"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \ -"fstype=cramfs\0" \ -"rootpath=/root_fs\0" \ -"uboot=PPC/u-boot.bin\0" \ -"kernel=PPC/uImage\0" \ -"kernel_addr=ffe00000\0" \ -"fs=PPC/root_fs\0" \ -"console=ttyS0\0" \ -"netdev=eth0\0" \ -"rootdev=31:3\0" \ -"ethaddr=00:09:4f:01:02:03\0" \ -"ipaddr=10.0.0.201\0" \ -"netmask=255.255.255.0\0" \ -"serverip=10.0.0.136\0" \ -"gatewayip=10.0.0.10\0" \ -"hostname=bastard\0" \ -"" - - -/* - * miscellaneous configurable options - */ - -/* undef to save memory */ -#define CFG_LONGHELP - -/* monitor command prompt */ -#define CFG_PROMPT "=> " - -/* console i/o buffer size */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 -#else -#define CFG_CBSIZE 256 -#endif - -/* print buffer size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - -/* max number of command args */ -#define CFG_MAXARGS 16 - -/* boot argument buffer size */ -#define CFG_BARGSIZE CFG_CBSIZE - -/* memtest works on */ -#define CFG_MEMTEST_START 0x00100000 -/* 1 ... 15 MB in DRAM */ -#define CFG_MEMTEST_END 0x00f00000 -/* full featured memtest */ -#define CFG_ALT_MEMTEST - -/* default load address */ -#define CFG_LOAD_ADDR 0x00100000 - -/* decrementer freq: 1 ms ticks */ -#define CFG_HZ 1000 - -/* configure flash */ -#define CFG_FLASH_BASE 0xff800000 -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 64 -#define CFG_FLASH_SIZE 8 -#undef CFG_FLASH_16BIT -#define CFG_FLASH_ERASE_TOUT 240000 -#define CFG_FLASH_WRITE_TOUT 500 -#define CFG_FLASH_LOCK_TOUT 500 -#define CFG_FLASH_UNLOCK_TOUT 10000 -#define CFG_FLASH_PROTECTION - -/* monitor in flash */ -#define CFG_MONITOR_OFFSET 0x00700000 - -/* environment in flash */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00020000) -#define CFG_ENV_SIZE 0x00020000 -#define CFG_ENV_SECT_SIZE 0x00020000 - -/* - * Initial memory map for linux - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) - -/* hard reset configuration words */ -#ifdef CONFIG_CLKIN_66MHz -#define CFG_HRCW_MASTER 0x04643050 -#else -#error NO HRCW FOR 100MHZ SPECIFIED !!! -#endif -#define CFG_HRCW_SLAVE1 0x00000000 -#define CFG_HRCW_SLAVE2 0x00000000 -#define CFG_HRCW_SLAVE3 0x00000000 -#define CFG_HRCW_SLAVE4 0x00000000 -#define CFG_HRCW_SLAVE5 0x00000000 -#define CFG_HRCW_SLAVE6 0x00000000 -#define CFG_HRCW_SLAVE7 0x00000000 - -/* internal memory mapped register */ -#define CFG_IMMR 0xF0000000 - -/* definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2000 -#define CFG_GBL_DATA_SIZE 128 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE (32*1024*1024) -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_FLASH (CFG_FLASH_BASE + CFG_MONITOR_OFFSET) -#define CFG_MONITOR_LEN 0x00020000 -#define CFG_MALLOC_LEN 0x00020000 - -/* boot flags */ -#define BOOTFLAG_COLD 0x01 /* normal power-on */ -#define BOOTFLAG_WARM 0x02 /* software reboot */ - -/* cache configuration */ -#define CFG_CACHELINE_SIZE 32 /* for MPC8260 */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of above */ -#endif - -/* - * HIDx - Hardware Implementation-dependent Registers - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|\ - HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/* RMR - reset mode register - turn on checkstop reset enable */ -#define CFG_RMR RMR_CSRE - -/* BCR - bus configuration */ -#define CFG_BCR 0x00000000 - -/* SIUMCR - siu module configuration */ -#define CFG_SIUMCR 0x4905c000 - -/* SYPCR - system protection control */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR 0xffffff87 -#else -#define CFG_SYPCR 0xffffff83 -#endif - -/* TMCNTSC - time counter status and control */ -/* clear interrupts XXX jse */ -/*#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR) */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\ - TMCNTSC_TCF|TMCNTSC_TCE) - -/* PISCR - periodic interrupt status and control */ -/* clear interrupts XXX jse */ -/*#define CFG_PISCR (PISCR_PS) */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/* SCCR - system clock control */ -#define CFG_SCCR 0x000001a9 - -/* RCCR - risc controller configuration */ -#define CFG_RCCR 0 - -/* - * MEMORY MAP - * ---------- - * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored) - * CS1 - SDRAM 32MB/64Bit base=0x00000000 - * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000 - * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000 - * CS4 - DSP/SL3 1MB/16Bit base=0xf0300000 - * CS5 - DSP/SL4 1MB/16Bit base=0xf0400000 - * CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored) - * x - IMMR 384KB base=0xf0000000 - */ -/* XXX jse 100MHz TODO */ -#define CFG_BR0_PRELIM 0xff800801 -#define CFG_OR0_PRELIM 0xff801e44 -#define CFG_BR1_PRELIM 0x00000041 -#define CFG_OR1_PRELIM 0xfe002ec0 -#if 1 -#define CFG_BR2_PRELIM 0xf0101001 -#define CFG_OR2_PRELIM 0xfff00ef4 -#define CFG_BR3_PRELIM 0xf0201001 -#define CFG_OR3_PRELIM 0xfff00ef4 -#define CFG_BR4_PRELIM 0xf0301001 -#define CFG_OR4_PRELIM 0xfff00ef4 -#define CFG_BR5_PRELIM 0xf0401001 -#define CFG_OR5_PRELIM 0xfff00ef4 -#else -#define CFG_BR2_PRELIM 0xf0101081 -#define CFG_OR2_PRELIM 0xfff00104 -#define CFG_BR3_PRELIM 0xf0201081 -#define CFG_OR3_PRELIM 0xfff00104 -#define CFG_BR4_PRELIM 0xf0301081 -#define CFG_OR4_PRELIM 0xfff00104 -#define CFG_BR5_PRELIM 0xf0401081 -#define CFG_OR5_PRELIM 0xfff00104 -#endif -#define CFG_BR7_PRELIM 0xf0500881 -#define CFG_OR7_PRELIM 0xffff8104 -#define CFG_MPTPR 0x2700 -#define CFG_PSDMR 0x822a2452 /* optimal */ -/*#define CFG_PSDMR 0x822a48a3 */ /* relaxed */ -#define CFG_PSRT 0x1a - -/* "bad" address */ -#define CFG_RESET_ADDRESS 0x40000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h deleted file mode 100644 index 8dc623e..0000000 --- a/include/configs/W7OLMC.h +++ /dev/null @@ -1,326 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ -#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ -#define CONFIG_W7OLMC 1 /* ...specifically an LMC */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#if 1 -#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ -#else -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ -#endif - -#undef CONFIG_BOOTARGS - -#define CONFIG_LOADADDR F0080000 - -#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.1.2 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* disallow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ - CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ - -#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ -#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ -#undef CFG_HUSH_PARSER /* No hush parse for U-Boot */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CFG_BASE_BAUD 384000 - - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE {9600} - -#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -/* resource configuration */ -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Set up values for external bus controller - * used by cpu_init.c - *----------------------------------------------------------------------- - */ - /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */ -#undef CONFIG_USE_PERWE - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* bank 0 is boot flash */ -/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CFG_W7O_EBC_PB0AP 0x03050440 -/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ -#define CFG_W7O_EBC_PB0CR 0xFFE38000 - -/* bank 1 is main flash */ -/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CFG_EBC_PB1AP 0x05850240 -/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ -#define CFG_EBC_PB1CR 0xF00FC000 - -/* bank 2 is RTC/NVRAM */ -/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CFG_EBC_PB2AP 0x03000440 -/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ -#define CFG_EBC_PB2CR 0xFC018000 - -/* bank 3 is FPGA 0 */ -/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ -#define CFG_EBC_PB3AP 0x02000400 -/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ -#define CFG_EBC_PB3CR 0xFD01A000 - -/* bank 4 is FPGA 1 */ -/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ -#define CFG_EBC_PB4AP 0x02000400 -/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ -#define CFG_EBC_PB4CR 0xFD11A000 - -/* bank 5 is FPGA 2 */ -/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ -#define CFG_EBC_PB5AP 0x02000400 -/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ -#define CFG_EBC_PB5CR 0xFD21A000 - -/* bank 6 is unused */ -/* pb6ap = 0 */ -#define CFG_EBC_PB6AP 0x00000000 -/* pb6cr = 0 */ -#define CFG_EBC_PB6CR 0x00000000 - -/* bank 7 is LED register */ -/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CFG_W7O_EBC_PB7AP 0x03050440 -/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ -#define CFG_W7O_EBC_PB7CR 0xFE01C000 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ -#define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */ - -#if 1 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ -#define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -/*define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */ -#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR - -#else /* Use Boot Flash for environment variables */ -/*----------------------------------------------------------------------- - * Flash EEPROM for environment - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */ - -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_I2C_MULTI_EEPROMS -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ -#endif - -/* - * Init Memory Controller: - */ -#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in RAM) - */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * FPGA(s) configuration - */ -#define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ -#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */ -#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ -#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ -#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h deleted file mode 100644 index 2bd98b3..0000000 --- a/include/configs/W7OLMG.h +++ /dev/null @@ -1,327 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC405 family */ -#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */ -#define CONFIG_W7OLMG 1 /* ...specifically an LMG */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#if 1 -#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */ -#else -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ -#endif - -#undef CONFIG_BOOTARGS - -#define CONFIG_LOADADDR F0080000 - -#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.1.2 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* disallow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ - CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \ - CFG_CMD_DTT) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ - -#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */ -#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */ -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */ -#undef CFG_HUSH_PARSER /* No hush parse for U-Boot */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CFG_BASE_BAUD 384000 - - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE {9600} - -#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -/* resource configuration */ -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Set up values for external bus controller - * used by cpu_init.c - *----------------------------------------------------------------------- - */ - /* use PerWE instead of PCI_INT ( these functions share a pin ) */ -#define CONFIG_USE_PERWE 1 - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* bank 0 is boot flash */ -/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CFG_W7O_EBC_PB0AP 0x03050440 -/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */ -#define CFG_W7O_EBC_PB0CR 0xFFE38000 - -/* bank 1 is main flash */ -/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CFG_EBC_PB1AP 0x04850240 -/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */ -#define CFG_EBC_PB1CR 0xF00FC000 - -/* bank 2 is RTC/NVRAM */ -/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CFG_EBC_PB2AP 0x03000440 -/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ -#define CFG_EBC_PB2CR 0xFC018000 - -/* bank 3 is FPGA 0 */ -/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */ -#define CFG_EBC_PB3AP 0x02000400 -/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */ -#define CFG_EBC_PB3CR 0xFD01A000 - -/* bank 4 is SAM 8 bit range */ -/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */ -#define CFG_EBC_PB4AP 0x02840380 -/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */ -#define CFG_EBC_PB4CR 0xFE878000 - -/* bank 5 is SAM 16 bit range */ -/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */ -#define CFG_EBC_PB5AP 0x05040d80 -/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */ -#define CFG_EBC_PB5CR 0xFD87A000 - -/* bank 6 is unused */ -/* pb6ap = 0 */ -#define CFG_EBC_PB6AP 0x00000000 -/* pb6cr = 0 */ -#define CFG_EBC_PB6CR 0x00000000 - -/* bank 7 is LED register */ -/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */ -#define CFG_W7O_EBC_PB7AP 0x03050440 -/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */ -#define CFG_W7O_EBC_PB7CR 0xFE01C000 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */ -#define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */ - -#if 1 /* Use NVRAM for environment variables */ -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */ -#define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -/*define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */ -#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR - -#else /* Use Boot Flash for environment variables */ -/*----------------------------------------------------------------------- - * Flash EEPROM for environment - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */ - -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */ -#endif - -/*----------------------------------------------------------------------- - * I2C EEPROM (ATMEL 24C04N) - */ -#define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_I2C_MULTI_EEPROMS -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ -#endif - -/* - * Init Memory Controller: - */ -#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */ - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in RAM) - */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * FPGA(s) configuration - */ -#define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */ -#define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */ -#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */ -#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */ -#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h deleted file mode 100644 index d92f81f..0000000 --- a/include/configs/WUH405.h +++ /dev/null @@ -1,388 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_IDENT_STRING " $Name: $" - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_WUH405 1 /* ...on a WUH405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_PREBOOT /* enable preboot variable */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFFC0000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ - -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC16) for environment - */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ -#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CFG_EBC_PB1AP 0x92015480 -#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ -#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ -#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define DUART2_BA 0xF0000410 /* DUART Base Address */ -#define DUART3_BA 0xF0000418 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define CFG_NAND_BASE 0xF4000000 - -/*----------------------------------------------------------------------- - * FPGA stuff - */ -#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ -#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ - -/* FPGA program pin configuration */ -#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ -#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs -> GPIO - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CFG_GPIO0_OSRH 0x40000550 -#define CFG_GPIO0_OSRL 0x00000110 -#define CFG_GPIO0_ISR1H 0x00000000 -#define CFG_GPIO0_ISR1L 0x15555445 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xF7FE0014 - -#define CFG_DUART_RST (0x80000000 >> 14) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * Default speed selection (cpu_plb_opb_ebc) in mhz. - * This value will be set if iic boot eprom is disabled. - */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 1 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 -#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h deleted file mode 100644 index 9b32514..0000000 --- a/include/configs/XPEDITE1K.h +++ /dev/null @@ -1,274 +0,0 @@ -/* - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * config for XPedite1000 from XES Inc. - * Ported from EBONY config by Travis B. Sawyer - * (C) Copyright 2003 Sandburst Corporation - * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_440 1 -#define CONFIG_440GX 1 /* 440 GX */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - - -/* POST support */ -#define CONFIG_POST (CFG_POST_RTC | \ - CFG_POST_I2C) - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ - -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) -#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) - -#define USR_LED0 0x00000080 -#define USR_LED1 0x00000100 -#define USR_LED2 0x00000200 -#define USR_LED3 0x00000400 - -#ifndef __ASSEMBLY__ -extern unsigned long in32(unsigned int); -extern void out32(unsigned int, unsigned long); - -#define LED0_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED0)) -#define LED1_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED1)) -#define LED2_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED2)) -#define LED3_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED3)) - -#define LED0_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED0)) -#define LED1_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED1)) -#define LED2_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED2)) -#define LED3_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED3)) -#endif - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) -#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */ -#define CONFIG_RTC_M41T11 1 -#define CFG_I2C_RTC_ADDR 0x68 -#define CFG_M41T11_BASE_YEAR 2000 - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 8 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ -#define CONFIG_VERY_BIG_RAM 1 -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7f -#define CFG_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_ENV_SIZE 0x100 /* Size of Environment vars */ -#define CFG_ENV_OFFSET 0x100 -#define CFG_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_BOOTARGS "root=/dev/hda1 " -#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ -#define CONFIG_BOOTDELAY 5 /* disable autoboot */ -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */ -#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */ -#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ -#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ -#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_DIAG | \ - CFG_CMD_FAT ) - -/* CFG_CMD_DHCP | \ */ -/* CFG_CMD_KGDB | \ */ - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT /* let board init pci target */ - -#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -#define CFG_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h deleted file mode 100644 index 37ef105..0000000 --- a/include/configs/Yukon8220.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2004 - * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC8220 1 -#define CONFIG_YUKON8220 1 /* ... on Yukon board */ - -/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to - determine the CPU speed. */ -#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ -#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ - -/* Define this for PSC console -#define CONFIG_PSC_CONSOLE 1 -*/ - -#define CONFIG_EXTUART_CONSOLE 1 - -#ifdef CONFIG_EXTUART_CONSOLE -# define CONFIG_CONS_INDEX 1 -# define CFG_NS16550_SERIAL -# define CFG_NS16550 -# define CFG_NS16550_REG_SIZE 1 -# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008) -# define CFG_NS16550_CLK 18432000 -#endif - -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Supported commands - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CACHE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -#define CONFIG_NET_MULTI -#define CONFIG_MII - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTARGS "root=/dev/ram rw" -#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61 -#define CONFIG_IPADDR 192.162.1.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.162.1.1 -#define CONFIG_GATEWAYIP 192.162.1.1 -#define CONFIG_HOSTNAME yukon -#define CONFIG_OVERWRITE_ETHADDR_ONCE - - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_MODULE 1 - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 -/* -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 256 -*/ - -/* If CFG_AMD_BOOT is defined, the the system will boot from AMD. - else undefined it will boot from Intel Strata flash */ -#define CFG_AMD_BOOT 1 - -/* - * Flexbus Chipselect configuration - */ -#if defined (CFG_AMD_BOOT) -#define CFG_CS0_BASE 0xfff0 -#define CFG_CS0_MASK 0x00080000 /* 512 KB */ -#define CFG_CS0_CTRL 0x003f0d40 - -#define CFG_CS1_BASE 0xfe00 -#define CFG_CS1_MASK 0x01000000 /* 16 MB */ -#define CFG_CS1_CTRL 0x003f1540 -#else -#define CFG_CS0_BASE 0xff00 -#define CFG_CS0_MASK 0x01000000 /* 16 MB */ -#define CFG_CS0_CTRL 0x003f1540 - -#define CFG_CS1_BASE 0xfe08 -#define CFG_CS1_MASK 0x00080000 /* 512 KB */ -#define CFG_CS1_CTRL 0x003f0d40 -#endif - -#define CFG_CS2_BASE 0xf100 -#define CFG_CS2_MASK 0x00040000 -#define CFG_CS2_CTRL 0x003f1140 - -#define CFG_CS3_BASE 0xf200 -#define CFG_CS3_MASK 0x00040000 -#define CFG_CS3_CTRL 0x003f1100 - - -#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) -#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16) - -#if defined (CFG_AMD_BOOT) -#define CFG_AMD_BASE CFG_FLASH0_BASE -#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000 -#define CFG_FLASH_BASE CFG_AMD_BASE -#else -#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000 -#define CFG_AMD_BASE CFG_FLASH1_BASE -#define CFG_FLASH_BASE CFG_INTEL_BASE -#endif - -#define CFG_CPLD_BASE (CFG_CS2_BASE << 16) -#define CFG_FPGA_BASE (CFG_CS3_BASE << 16) - - -#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ -#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */ - -#define CFG_FLASH_CHECKSUM -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#if defined (CFG_AMD_BOOT) -#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE) -#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE -#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE -#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE) -#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE -#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE -#else -#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE) -#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE -#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE -#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE) -#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE -#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE -#endif - -#define CONFIG_ENV_OVERWRITE 1 - -#if defined CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_EEPROM -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#endif - -#ifndef CFG_JFFS2_FIRST_SECTOR -#define CFG_JFFS2_FIRST_SECTOR 0 -#endif -#ifndef CFG_JFFS2_FIRST_BANK -#define CFG_JFFS2_FIRST_BANK 0 -#endif -#ifndef CFG_JFFS2_NUM_BANKS -#define CFG_JFFS2_NUM_BANKS 1 -#endif -#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1) - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 -#define CFG_SRAM_BASE (CFG_MBAR + 0x20000) -#define CFG_SRAM_SIZE 0x8000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) -#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* SDRAM configuration */ -#define CFG_SDRAM_TOTAL_BANKS 2 -#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */ -#define CFG_SDRAM_SPD_SIZE 0x40 -#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */ - -/* SDRAM drive strength register */ -#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \ - (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ - (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \ - (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \ - (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT)) - -/* - * Ethernet configuration - */ -#define CONFIG_MPC8220_FEC 1 -#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ -#define CONFIG_PHY_ADDR 0x18 - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -#endif /* __CONFIG_H */ diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h deleted file mode 100644 index f71e691..0000000 --- a/include/configs/ZPC1900.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright (C) 2003-2004 Arabella Software Ltd. - * Yuli Barcohen - * - * U-Boot configuration for Zephyr Engineering ZPC.1900 board. - * This port was developed and tested on Revision C board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */ -#define CPU_ID_STR "MPC8265" -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#undef DEBUG - -#undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */ - -/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */ - -#if (CONFIG_ETHER_INDEX == 2) -/* - * - Rx clock is CLK13 - * - Tx clock is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Full duplex - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_FLASH_BASE 0xFFE00000 -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ - -#define CFG_DEFAULT_IMMR 0x0F010000 - -#define CFG_IMMR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 64 -#define CFG_FLSIMM_BASE 0xFC000000 -#define CFG_LSDRAM_BASE 0xFE000000 -#define CFG_BCSR 0xFEA00000 -#define CFG_EEPROM 0xFEB00000 - -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -#define BCSR_PCI_MODE 0x01 - -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\ - HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\ - HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10 |\ - HRCW_MODCK_H0101 \ - ) /* 0x16828605 */ -/* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if !defined(CFG_ENV_IS_IN_FLASH) && !defined(CFG_ENV_IS_IN_NVRAM) -#define CFG_ENV_IS_IN_NVRAM 1 -#endif - -#ifdef CFG_ENV_IS_IN_FLASH -# define CFG_ENV_SECT_SIZE 0x10000 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#else -# define CFG_ENV_ADDR (CFG_EEPROM + 0x400) -# define CFG_ENV_SIZE 0x1000 -# define CFG_NVRAM_ACCESS_ROUTINE -#endif - -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) - -#define CFG_HID2 0 - -#define CFG_SIUMCR 0x42200000 -#define CFG_SYPCR 0xFFFFFFC3 -#define CFG_BCR 0x90400000 -#define CFG_SCCR SCCR_DFBRG01 - -#define CFG_RMR RMR_CSRE -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CFG_RCCR 0 - -#define CFG_PSDMR 0x014EB45A -#define CFG_PSRT 0x0C -#define CFG_LSDMR 0x008AB552 -#define CFG_LSRT 0x0E -#define CFG_MPTPR 0x4000 - -#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801 -#define CFG_OR0_PRELIM 0xFFE00856 -#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801 -#define CFG_OR5_PRELIM 0xFFFF03F6 -#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801 -#define CFG_OR6_PRELIM 0xFE000856 -#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801 -#define CFG_OR7_PRELIM 0xFFFF83F6 - -#define CFG_RESET_ADDRESS 0xC0000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h deleted file mode 100644 index f163d00..0000000 --- a/include/configs/ZUMA.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ -#define CONFIG_ETHER_PORT_MII /* use two MII ports */ -#define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */ - -#ifndef __ASSEMBLY__ -#include -#endif - -#include "../board/evb64260/local.h" - -#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ -#define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */ - -/* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */ - -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ - -#define CONFIG_ECC /* enable ECC support */ - -#define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_EARLY_INIT_F -#define CFG_BOARD_ASM_INIT - -#define CFG_BOARD_NAME "Zuma APv2" - -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CFG_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC - -#define CONFIG_MPSC_PORT 0 - -#define CONFIG_NET_MULTI /* attempt all available adapters */ - -/* define this if you want to enable GT MAC filtering */ -#define CONFIG_GT_USE_MAC_HASH_TABLE - -#if 1 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND \ - "tftpboot && " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:" \ - "$netmask:$hostname:eth0:none panic=5 && bootm" - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MII /* enable MII commands */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BSP | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_DATE) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" -#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" -*/ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00300000 /* default load address */ - -#define CFG_HZ 1000 /* decr freq: 1ms ticks */ - -#define CFG_BUS_HZ 133000000 /* 133 MHz */ - -#define CFG_BUS_CLK CFG_BUS_HZ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_RAM_LOCK - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xfff00000 -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CFG_DRAM_BANKS 4 -#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ - -/* What to put in the bats. */ -#define CFG_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ -#define CFG_GT_REGS 0xf8000000 /* later mapped GT_REGS */ -#define CFG_DEV_BASE 0xf0000000 -#define CFG_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/ -#define CFG_DEV1_SIZE _8M /* zuma IDE @ 0xf400.0000 */ -#define CFG_DEV2_SIZE _8M /* unused */ -#define CFG_DEV3_SIZE _8M /* unused */ - -#define CFG_DEV0_PAR 0xc498243c - /* c 4 9 8 2 4 3 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */ - /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 7 | 4 */ - -#define CFG_DEV1_PAR 0xc01b6ac5 - /* c 0 1 b 6 a c 5 */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */ - /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */ - - -#define CFG_8BIT_BOOT_PAR 0xc00b5e7c - -#define CFG_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */ -#define CFG_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */ -#define CFG_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */ -#define CFG_MPP_CONTROL_3 0x00000000 /* GPP[31:28] (int[3:0]) */ - /* GPP[27:24] (27 is int4, rest are GPP) */ - -#define CFG_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */ -#define CFG_GPP_LEVEL_CONTROL 0xf8000000 /* interrupt inputs: GPP[31:27] */ - -#define CFG_SDRAM_CONFIG 0xe4e18200 /* 0x448 */ - /* idmas use buffer 1,1 - comm use buffer 1 - pci use buffer 0,0 (pci1->0 pci0->0) - cpu use buffer 1 (R*18) - normal load (see also ifdef HVL) - standard SDRAM (see also ifdef REG) - non staggered refresh */ - /* 31:26 25 23 20 19 18 16 */ - /* 111001 00 111 0 0 00 1 */ - - /* refresh count=0x200 - phy interleave disable (by default, - set later by dram config..) - virt interleave enable */ - /* 15 14 13:0 */ - /* 1 0 0x200 */ - -#define CFG_DEV0_SPACE CFG_DEV_BASE -#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) -#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) -#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) - -/*----------------------------------------------------------------------- - * PCI stuff - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -/* PCI MEMORY MAP section */ -#define CFG_PCI0_MEM_BASE 0x80000000 -#define CFG_PCI0_MEM_SIZE _128M -#define CFG_PCI1_MEM_BASE 0x88000000 -#define CFG_PCI1_MEM_SIZE _128M - -#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) -#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CFG_PCI0_IO_BASE 0xfa000000 -#define CFG_PCI0_IO_SIZE _16M -#define CFG_PCI1_IO_BASE 0xfb000000 -#define CFG_PCI1_IO_SIZE _16M - -#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) -#define CFG_PCI0_IO_SPACE_PCI 0x00000000 -#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) -#define CFG_PCI1_IO_SPACE_PCI 0x00000000 - - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT0U CFG_IBAT0U - -/* init ram */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U - -/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */ -#define CFG_IBAT2L BATL_NO_ACCESS -#define CFG_IBAT2U CFG_DBAT2U -#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 130 /* max number of sectors on one chip */ - -#define CFG_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */ -#define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_CFI 1 - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -#define CFG_ENV_ADDR (0xfff80000 - CFG_ENV_SECT_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/74xx_7xx.h for the defines used here - */ - -#define CFG_L2 - -#ifdef CONFIG_750CX -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/*------------------------------------------------------------------------ - * Real time clock - */ -#define CONFIG_RTC_DS1302 - - -/*------------------------------------------------------------------------ - * Galileo I2C driver - */ -#define CONFIG_GT_I2C - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h deleted file mode 100644 index c410891..0000000 --- a/include/configs/adsvix.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the LUBBOCK board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ -#define CONFIG_ADSVIX 1 /* on a Adsvix Board */ -#define CONFIG_MMC 1 -#define BOARD_LATE_INIT 1 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define RTC - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART on ADSVIX */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_DOS_PARTITION 1 - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_SERVERIP 192.168.1.99 -#define CONFIG_BOOTCOMMAND "run boot_flash" -#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ - " rw root=/dev/ram initrd=0xa0800000,5m" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "program_boot_cf=" \ - "mw.b 0xa0010000 0xff 0x20000; " \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0010000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x1ffff; " \ - "erase 0x0 0x1ffff; " \ - "cp.b 0xa0010000 0x0 0x20000; " \ - "fi\0" \ - "program_uzImage_cf=" \ - "mw.b 0xa0010000 0xff 0x180000; " \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0010000 uzImage; " \ - "then " \ - "protect off 0x40000 0x1bffff; " \ - "erase 0x40000 0x1bffff; " \ - "cp.b 0xa0010000 0x40000 0x180000; " \ - "fi\0" \ - "program_ramdisk_cf=" \ - "mw.b 0xa0010000 0xff 0x500000; " \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0010000 ramdisk.gz; " \ - "then " \ - "protect off 0x1c0000 0x6bffff; " \ - "erase 0x1c0000 0x6bffff; " \ - "cp.b 0xa0010000 0x1c0000 0x500000; " \ - "fi\0" \ - "boot_cf=" \ - "if pinit on && " \ - "ide reset && " \ - "fatload ide 0 0xa0030000 uzImage && " \ - "fatload ide 0 0xa0800000 ramdisk.gz; " \ - "then " \ - "bootm 0xa0030000; " \ - "fi\0" \ - "program_boot_mmc=" \ - "mw.b 0xa0010000 0xff 0x20000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x1ffff; " \ - "erase 0x0 0x1ffff; " \ - "cp.b 0xa0010000 0x0 0x20000; " \ - "fi\0" \ - "program_uzImage_mmc=" \ - "mw.b 0xa0010000 0xff 0x180000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 uzImage; " \ - "then " \ - "protect off 0x40000 0x1bffff; " \ - "erase 0x40000 0x1bffff; " \ - "cp.b 0xa0010000 0x40000 0x180000; " \ - "fi\0" \ - "program_ramdisk_mmc=" \ - "mw.b 0xa0010000 0xff 0x500000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0010000 ramdisk.gz; " \ - "then " \ - "protect off 0x1c0000 0x6bffff; " \ - "erase 0x1c0000 0x6bffff; " \ - "cp.b 0xa0010000 0x1c0000 0x500000; " \ - "fi\0" \ - "boot_mmc=" \ - "if mmcinit && " \ - "fatload mmc 0 0xa0030000 uzImage && " \ - "fatload mmc 0 0xa0800000 ramdisk.gz; " \ - "then " \ - "bootm 0xa0030000; " \ - "fi\0" \ - "boot_flash=" \ - "cp.b 0x1c0000 0xa0800000 0x500000; " \ - "bootm 0x40000\0" \ - -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -/* #define CONFIG_INITRD_TAG 1 */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_MMC_BASE 0xF0000000 - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * GPIO settings - */ - -#define CFG_GPSR0_VAL 0x00018004 -#define CFG_GPSR1_VAL 0x004F0080 -#define CFG_GPSR2_VAL 0x13EFC000 -#define CFG_GPSR3_VAL 0x0006E032 -#define CFG_GPCR0_VAL 0x084AFE1A -#define CFG_GPCR1_VAL 0x003003F2 -#define CFG_GPCR2_VAL 0x0C014000 -#define CFG_GPCR3_VAL 0x00000C00 -#define CFG_GPDR0_VAL 0xCBC3BFFC -#define CFG_GPDR1_VAL 0x00FFABF3 -#define CFG_GPDR2_VAL 0x1EEFFC00 -#define CFG_GPDR3_VAL 0x0187EC32 -#define CFG_GAFR0_L_VAL 0x84400000 -#define CFG_GAFR0_U_VAL 0xA51A8010 -#define CFG_GAFR1_L_VAL 0x699A955A -#define CFG_GAFR1_U_VAL 0x0005A0AA -#define CFG_GAFR2_L_VAL 0x40000000 -#define CFG_GAFR2_U_VAL 0x0109A400 -#define CFG_GAFR3_L_VAL 0x54000000 -#define CFG_GAFR3_U_VAL 0x00001409 - -#define CFG_PSSR_VAL 0x20 - -/* - * Clock settings - */ -#define CFG_CKEN 0x00400200 -#define CFG_CCCR 0x02000290 /* 520Mhz */ -/* #define CFG_CCCR 0x02000210 416 Mhz */ - -/* - * Memory settings - */ - -#define CFG_MSC0_VAL 0x23F2B3DB -#define CFG_MSC1_VAL 0x0000CCD1 -#define CFG_MSC2_VAL 0x0000B884 -#define CFG_MDCNFG_VAL 0x08000AC8 -#define CFG_MDREFR_VAL 0x0000001E -#define CFG_MDMRS_VAL 0x00000000 - -#define CFG_FLYCNFG_VAL 0x00010001 -#define CFG_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000002 -#define CFG_MCMEM0_VAL 0x00004204 -#define CFG_MCMEM1_VAL 0x00000000 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00000000 -#define CFG_MCIO0_VAL 0x00008407 -#define CFG_MCIO1_VAL 0x00000000 - -#define CONFIG_PXA_PCMCIA 1 -#define CONFIG_PXA_IDE 1 - -#define CONFIG_PCMCIA_SLOT_A 1 -/* just to keep build system happy */ - -#define CFG_PCMCIA_MEM_ADDR 0x28000000 -#define CFG_PCMCIA_MEM_SIZE 0x04000000 - - -#define CFG_IDE_MAXBUS 1 -/* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 -/* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR 0x20000000 - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET 0x1f0 - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET 0x1f0 - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x3f0 - -/* - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER 1 - -#define CFG_MONITOR_BASE 0 -#define CFG_MONITOR_LEN 0x20000 - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - -/* write flash less slowly */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 - -/* Flash environment locations */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/aev.h b/include/configs/aev.h deleted file mode 100644 index aa6bc91..0000000 --- a/include/configs/aev.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ -#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ -#define CONFIG_AEVFIFO 1 -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#ifdef CONFIG_AEVFIFO -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_NET_MULTI 1 -#define CONFIG_EEPRO100 1 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif /* CONFIG_AEVFIFO */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - CFG_CMD_PCI | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} " \ - "console=ttyS0,${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ - -#if defined(CFG_IPBSPEED_133) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. - */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CFG_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CFG_LOWBOOT) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CFG_LOWBOOT */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) -#endif /* CFG_LOWBOOT */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#define CFG_GPS_PORT_CONFIG 0x81500014 - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CFG_ALT_MEMTEST - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 -#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -/* automatic configuration of chip selects */ -#ifdef CONFIG_CS_AUTOCONF -#define CONFIG_LAST_STAGE_INIT -#endif - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#define CFG_CS2_START 0xE5000000 -#define CFG_CS2_SIZE 0x80000 /* 512 kByte */ -#define CFG_CS2_CFG 0x0004D930 - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#define SM501_FB_BASE 0xE0000000 -#define CFG_CS1_START (SM501_FB_BASE) -#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CFG_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CFG_RESET_ADDRESS 0xff000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h deleted file mode 100644 index 9a1c559..0000000 --- a/include/configs/armadillo.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the EP7312 board. - * - * Modified to work on Armadillo HT1070 ARM720T board - * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * If we are developing, we might want to start armboot from ram - * so we MUST NOT initialize critical regs like mem-timing ... - */ -/*#define CONFIG_INIT_CRITICAL*/ /* undef for developing */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ -#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */ -#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ - -#undef CONFIG_USE_IRQ /* don't need them anymore */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x20000300 /* armadillo board */ -#define CS8900_BUS16 1 -#undef CS8900_BUS32 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) /* | CFG_CMD_JFFS2)*/ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200" - -#define CONFIG_BOOTCOMMAND "bootm 40000 180000" - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "ARMADILLO # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/ - -#define CFG_HZ 2000 /* decrementer freq: 2 kHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB armadillo SDRAM */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#endif /* __CONFIG_H */ diff --git a/include/configs/assabet.h b/include/configs/assabet.h deleted file mode 100644 index 1a69ebe..0000000 --- a/include/configs/assabet.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * 2004 (c) MontaVista Software, Inc. - * - * Configuation settings for the Intel Assabet board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SA1110 1 /* This is an SA1100 CPU */ -#define CONFIG_ASSABET 1 /* on an Intel Assabet Board */ - -#undef CONFIG_USE_IRQ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size rsrvd for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */ -#define CONFIG_LAN91C96_BASE 0x18000000 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp" -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" -#define CFG_AUTOLOAD "n" /* No autoload */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "Intel Assabet # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ - -#define CFG_LOAD_ADDR 0xc0000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x0a /* set core clock to 206MHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ - -#if CFG_MONITOR_BASE < CFG_FLASH_BASE -#define CFG_RAMSTART -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_FLASH_SIZE PHYS_FLASH_SIZE -#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ -#undef CFG_FLASH_PROTECTION -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -#define CFG_ENV_IS_IN_FLASH 1 - -#if defined(CFG_ENV_IS_IN_FLASH) -#define CFG_ENV_IN_OWN_SECTOR 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) -#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE -#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h deleted file mode 100644 index 8fad55d..0000000 --- a/include/configs/at91rm9200dk.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Rick Bronson - * - * Configuation settings for the AT91RM9200DK board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ -#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ -/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CFG_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ - -/* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CONFIG_BAUDRATE 115200 - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_BOOTDELAY 3 -/* #define CONFIG_ENV_OVERWRITE 1 */ - -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | CFG_CMD_MII |\ - CFG_CMD_DHCP ) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_IMI | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC | \ - CFG_CMD_LOADS )) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ -#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ - -#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) -#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) - -#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) -/* the following are NOP's in our implementation */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ - -#define CFG_MEMTEST_START PHYS_SDRAM -#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 - -#define CONFIG_DRIVER_ETHER -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_AT91C_USE_RMII - -#define CONFIG_HAS_DATAFLASH 1 -#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) -#define CFG_MAX_DATAFLASH_BANKS 2 -#define CFG_MAX_DATAFLASH_PAGES 16384 -#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ -#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ - -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */ -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 256 -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#undef CFG_ENV_IS_IN_DATAFLASH - -#ifdef CFG_ENV_IS_IN_DATAFLASH -#define CFG_ENV_OFFSET 0x20000 -#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) -#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ -#else -#define CFG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ -#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */ -#else -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ -#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -#endif /* CFG_ENV_IS_IN_DATAFLASH */ - - -#define CFG_LOAD_ADDR 0x21000000 /* default load address */ - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */ -#define CFG_U_BOOT_BASE PHYS_FLASH_1 -#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */ -#else -#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ -#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) -#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } - -#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ - -#ifndef __ASSEMBLY__ -/*----------------------------------------------------------------------- - * Board specific extension for bd_info - * - * This structure is embedded in the global bd_info (bd_t) structure - * and can be used by the board specific code (eg board/...) - */ - -struct bd_info_ext { - /* helper variable for board environment handling - * - * env_crc_valid == 0 => uninitialised - * env_crc_valid > 0 => environment crc in flash is valid - * env_crc_valid < 0 => environment crc in flash is invalid - */ - int env_crc_valid; -}; -#endif - -#define CFG_HZ 1000 -#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#endif diff --git a/include/configs/atc.h b/include/configs/atc.h deleted file mode 100644 index bf6c170..0000000 --- a/include/configs/atc.h +++ /dev/null @@ -1,509 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_ATC 1 /* ...on a ATC board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ - -#define CONFIG_BAUDRATE 115200 - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_ON_FCC - -#define CONFIG_NET_MULTI -#define CONFIG_ETHER_ON_FCC2 - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#define CONFIG_ETHER_ON_FCC3 - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the local Bus (see 28-13) - * - Enable Half Duplex in FSMR - */ -# define CFG_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 64000000 /* in Hz */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */ - -#define CONFIG_PREBOOT \ - "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\ - "echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\ - "bootm" - -/*----------------------------------------------------------------------- - * Miscellaneous configuration options - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_DATE | \ - CFG_CMD_IDE) - - -#define CONFIG_DOS_PARTITION - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ - -#define CFG_ALLOC_DPRAM - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SPI - -#define CONFIG_RTC_DS12887 - -#define RTC_BASE_ADDR 0xF5000000 -#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800 -#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808 - -#define CONFIG_MISC_INIT_R - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Flash configuration - */ - -#define CFG_FLASH_BASE 0xFF000000 -#define CFG_FLASH_SIZE 0x00800000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_FLASH_16BIT - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ - HRCW_BPS10 |\ - HRCW_APPC10) - -/* no slaves so just fill with zeros */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CFG_SDRAM_BASE. - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#define CONFIG_PCI -#define CONFIG_PCI_PNP -#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ - -#if 1 -/* environment is in Flash */ -#define CFG_ENV_IS_IN_FLASH 1 -# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x30000) -# define CFG_ENV_SIZE 0x10000 -# define CFG_ENV_SECT_SIZE 0x10000 -#else -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 2048 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ -#endif -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ - HID0_DCI|HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define BCR_APD01 0x10000000 -#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\ - SIUMCR_CS10PC00|SIUMCR_BCTLC10) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -#define CFG_MIN_AM_MASK 0xC0000000 -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescaler Register 10-18 - *----------------------------------------------------------------------- - */ -#define CFG_MPTPR 0x1F00 - -/*----------------------------------------------------------------------- - * PSRT - Refresh Timer Register 10-16 - *----------------------------------------------------------------------- - */ -#define CFG_PSRT 0x0f - -/*----------------------------------------------------------------------- - * PSRT - SDRAM Mode Register 10-10 - *----------------------------------------------------------------------- - */ - - /* SDRAM initialization values for 8-column chips - */ -#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CFG_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_12) - -#define CFG_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI1_A6 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit Boot ROM - * 1 60x GPCM 64 bit FLASH - * 2 60x SDRAM 64 bit SDRAM - * - */ - -#define CFG_MRS_OFFS 0x00000000 - -/* Bank 0 - FLASH - */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) - - -/* Bank 2 - 60x bus SDRAM - */ -#ifndef CFG_RAMBOOT -#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_OR2_PRELIM CFG_OR2_8COL - -#define CFG_PSDMR CFG_PSDMR_8COL -#endif /* CFG_RAMBOOT */ - -#define CFG_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMA |\ - BRx_V) - -#define CFG_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_I82365 - -#define CFG_PCMCIA_MEM_ADDR 0x81000000 -#define CFG_PCMCIA_MEM_SIZE 0x1000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR 0xa0000000 - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET 0x100 - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET 0x100 - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x108 - -#endif /* __CONFIG_H */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h deleted file mode 100644 index eacc744..0000000 --- a/include/configs/bamboo.h +++ /dev/null @@ -1,406 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * bamboo.h - configuration for BAMBOO board - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_BAMBOO 1 /* Board is BAMBOO */ -#define CONFIG_440EP 1 /* Specific PPC440EP support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* - * Please note that, if NAND support is enabled, the 2nd ethernet port - * can't be used because of pin multiplexing. So, if you want to use the - * 2nd ethernet port you have to "undef" the following define. - */ -#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ -#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 - -/*Don't change either of these*/ -#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ -#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ -/*Don't change either of these*/ - -#define CFG_USB_DEVICE 0x50000000 -#define CFG_NVRAM_BASE_ADDR 0x80000000 -#define CFG_BOOT_BASE_ADDR 0xf0000000 -#define CFG_NAND_ADDR 0x90000000 -#define CFG_NAND2_ADDR 0x94000000 - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in SDRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CFG_INIT_RAM_END (4 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF - * The DS1558 code assumes this condition - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or EEPROM). - * Note: DENX encourages to use redundant environment in FLASH. - */ -#if 1 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#endif - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_ADDR0 0x555 -#define CFG_FLASH_ADDR1 0x2aa -#define CFG_FLASH_WORD_SIZE unsigned char - -#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ -#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * NAND-FLASH related - *----------------------------------------------------------------------*/ -#define NAND_CMD_REG (0x00) /* NandFlash Command Register */ -#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */ -#define NAND_DATA_REG (0x08) /* NandFlash Data Register */ -#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */ -#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */ -#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */ -#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */ -#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */ -#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */ -#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */ -#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */ -#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */ -#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */ -#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */ -#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */ -#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */ -#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */ -#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */ -#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */ - -/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */ -#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */ -#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */ -#define NAND0_CMD_READ2 0x50 -#define NAND0_CMD_READ_ID 0x90 -#define NAND0_CMD_READ_STATUS 0x70 -#define NAND0_CMD_RESET 0xFF -#define NAND0_CMD_PAGE_PROG 0x80 -#define NAND0_CMD_PAGE_PROG_TRUE 0x10 -#define NAND0_CMD_PAGE_PROG_DUMMY 0x11 -#define NAND0_CMD_BLOCK_ERASE 0x60 -#define NAND0_CMD_BLOCK_ERASE_END 0xD0 - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0) -#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0) -#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG)) -#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01)) - -/* not needed with 440EP NAND controller */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------------- */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#undef CONFIG_DDR_ECC /* don't use ECC */ -#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ -#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ -#define CFG_ENV_OFFSET 0x0 -#endif /* CFG_ENV_IS_IN_EEPROM */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=bamboo\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/bamboo/uImage\0" \ - "kernel_addr=fff00000\0" \ - "ramdisk_addr=fff10000\0" \ - "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \ - "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 100000 fff80000 80000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ -#define CONFIG_PHY1_ADDR 1 - -#ifndef CONFIG_BAMBOO_NAND -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#endif /* CONFIG_BAMBOO_NAND */ - -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -#ifdef CONFIG_440EP -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/*Comment this out to enable USB 1.1 device*/ -#define USB_2_0_DEVICE -#endif /*CONFIG_440EP*/ - -#ifdef CONFIG_BAMBOO_NAND -#define _CFG_CMD_NAND CFG_CMD_NAND -#else -#define _CFG_CMD_NAND 0 -#endif /* CONFIG_BAMBOO_NAND */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_USB | \ - CFG_CMD_FAT | \ - CFG_CMD_EXT2 | \ - _CFG_CMD_NAND | \ - CFG_CMD_SNTP ) - -#define CONFIG_SUPPORT_VFAT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT -#define CFG_PCI_MASTER_INIT - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/barco.h b/include/configs/barco.h deleted file mode 100644 index 624fa1d..0000000 --- a/include/configs/barco.h +++ /dev/null @@ -1,364 +0,0 @@ -/******************************************************************** - * - * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms - * - * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $ - * $Revision: 1.2 $ - * $Author: mleeman $ - * $Date: 2005/02/21 12:48:58 $ - * - * Last ChangeLog Entry - * $Log: barco.h,v $ - * Revision 1.2 2005/02/21 12:48:58 mleeman - * update of copyright years (feedback wd) - * - * Revision 1.1 2005/02/14 09:29:25 mleeman - * moved barcohydra.h to barco.h - * - * Revision 1.4 2005/02/09 12:56:23 mleeman - * add generic header to track changes in sources - * - * - *******************************************************************/ - -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_BARCOBCD_STREAMING 1 - -#undef USE_DINK32 - -#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_DRAM_SPEED 100 /* MHz */ - -#define CONFIG_BOOTARGS "mem=32M" - -/* Add support for a few extra bootp options like: - * - File size - * - DNS - */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_PCI ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_BOOTCOMMAND "boot_default" - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP -#undef CFG_CMD_NET - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 - - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x02000000 - -#define CONFIG_LOGBUFFER -#ifdef CONFIG_LOGBUFFER -#define CFG_STDOUT_ADDR 0x1FFC000 -#else -#define CFG_STDOUT_ADDR 0x2B9000 -#endif - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE 0x00090000 -#define CFG_RAMBOOT 1 -#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_INIT_RAM_END 0x10000 -#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#else -#undef CFG_RAMBOOT -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#endif - -#define CFG_FLASH_BASE 0xFFF00000 -#define CFG_FLASH_SIZE (8 * 1024 * 1024) /* Unity has onboard 1MByte flash */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x000047A4 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ -/* #define ENV_CRC 0x8BF6F24B XXX - FIXME: gets defined automatically */ - -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - -#define CFG_EUMB_ADDR 0xFDF00000 - -#define CFG_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */ -#define CFG_FLASH_RANGE_SIZE 0x00400000 -#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#ifdef CONFIG_SOFT_I2C -#error "Soft I2C is not configured properly. Please review!" -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } -#define CFG_DBUS_SIZE2 1 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - - - /* - * NS16550 Configuration (internal DUART) - */ - /* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CFG_ROMNAL 0x0F /*rom/flash next access time */ -#define CFG_ROMFAL 0x1E /*rom/flash access time */ - -#define CFG_REFINT 0x8F /* no of clock cycles between CBR refresh cycles */ - -/* the following are for SDRAM only*/ -#define CFG_BSTOPRE 0x25C /* Burst To Precharge, sets open page interval */ -#define CFG_REFREC 8 /* Refresh to activate interval */ -#define CFG_RDLAT 4 /* data latency from read command */ -#define CFG_PRETOACT 3 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_ACTORW 2 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ - -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 0 -#define CFG_REGDIMM 0 - - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END 0x01FFFFFF -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x02000000 -#define CFG_BANK1_END 0x02ffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x03f00000 -#define CFG_BANK2_END 0x03ffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x04000000 -#define CFG_BANK3_END 0x04ffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x05000000 -#define CFG_BANK4_END 0x05FFFFFF -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x06000000 -#define CFG_BANK5_END 0x06FFFFFF -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x07000000 -#define CFG_BANK6_END 0x07FFFFFF -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x08000000 -#define CFG_BANK7_END 0x08FFFFFF -#define CFG_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CFG_BANK_ENABLE 0x01 - -#define CFG_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_CHECKSUM - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#define CONFIG_DISK_SPINUP_TIME 1000000 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h deleted file mode 100644 index 4a79835..0000000 --- a/include/configs/bubinga.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405EP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_NO_SERIAL_EEPROM -/*#undef CONFIG_NO_SERIAL_EEPROM*/ -/*----------------------------------------------------------------------------*/ -#ifdef CONFIG_NO_SERIAL_EEPROM - -/* -!------------------------------------------------------------------------------- -! Defines for entry options. -! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that -! are plugged in the board will be utilized as non-ECC DIMMs. -!------------------------------------------------------------------------------- -*/ -#define AUTO_MEMORY_CONFIG -#define DIMM_READ_ADDR 0xAB -#define DIMM_WRITE_ADDR 0xAA - -/* -!------------------------------------------------------------------------------- -! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, -! assuming a 33MHz input clock to the 405EP from the C9531. -!------------------------------------------------------------------------------- -*/ -#define PLLMR0_DEFAULT PLLMR0_266_133_66 -#define PLLMR1_DEFAULT PLLMR1_266_133_66 - -#endif -/*----------------------------------------------------------------------------*/ - -/* - * Define here the location of the environment variables (FLASH or NVRAM). - * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only - * supported for backward compatibility. - */ -#if 1 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#endif - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=bubinga\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/bubinga/uImage\0" \ - "kernel_addr=fff80000\0" \ - "ramdisk_addr=fff90000\0" \ - "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* - * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CFG_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * I2C stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ - -#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) -#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#endif - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * External peripheral base address - *----------------------------------------------------------------------- - */ -#define CFG_KEY_REG_BASE_ADDR 0xF0100000 -#define CFG_IR_REG_BASE_ADDR 0xF0200000 -#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SRAM_BASE 0xFFF00000 -#define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_ADDR0 0x5555 -#define CFG_FLASH_ADDR1 0x2aaa -#define CFG_FLASH_WORD_SIZE unsigned char - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ - -#ifdef CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash/SRAM) initialization */ -#define CFG_EBC_PB0AP 0x04006000 -#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 1 (NVRAM/RTC) initialization */ -#define CFG_EBC_PB1AP 0x04041000 -#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 2 (not used) initialization */ -#define CFG_EBC_PB2AP 0x00000000 -#define CFG_EBC_PB2CR 0x00000000 - -/* Memory Bank 2 (not used) initialization */ -#define CFG_EBC_PB3AP 0x00000000 -#define CFG_EBC_PB3CR 0x00000000 - -/* Memory Bank 4 (FPGA regs) initialization */ -#define CFG_EBC_PB4AP 0x01815000 -#define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x55 - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CFG_GPIO0_OSRH 0x55555555 -#define CFG_GPIO0_OSRL 0x40000110 -#define CFG_GPIO0_ISR1H 0x00000000 -#define CFG_GPIO0_ISR1L 0x15555445 -#define CFG_GPIO0_TSRH 0x00000000 -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xFFFF8014 - -/*----------------------------------------------------------------------- - * Some BUBINGA stuff... - */ -#define NVRAM_BASE 0xF0000000 -#define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */ -#define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */ -#define NVRVFY1 0x4f532d4f /* used to determine if state data in */ -#define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/ - -#define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */ -#define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */ -#define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */ -#define FPGA_REG0_LED0 0x04 /* Turn on LED0 */ -#define FPGA_REG0_LED1 0x02 /* Turn on LED1 */ -#define FPGA_REG0_LED2 0x01 /* Turn on LED2 */ - -#define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */ -#define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */ -#define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */ -#define FPGA_REG1_CLOCK_BIT_SHIFT 4 -#define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */ -#define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */ -#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */ -#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h deleted file mode 100644 index ae75539..0000000 --- a/include/configs/c2mon.h +++ /dev/null @@ -1,418 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_C2MON 1 /* ...on a C2MON module */ - -#define CONFIG_80MHz 1 /* Running at 5 * 16 = 80 MHz */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_FEC_ENET 1 /* Use Fast Ethernet Controller */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CFG_PLPRCR \ - ( (5-1)< - -/* - * MUST be low boot - HIGHBOOT is not supported anymore - */ -#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT16 1 -#else -# error "TEXT_BASE must be 0xFE000000" -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/canmb/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ - -/* - * Flash configuration, expect one 16 Megabyte Bank at most - */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_SIZE 0x02000000 -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET (2*128*1024) -#define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_SECT_SIZE (128*1024) - -/* - * Memory map - * - * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 - */ -#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_PHY_ADDR 0x0 -/* - * GPIO configuration: - * PSC1,2,3 predefined as UART - * PCI disabled - * Ethernet 100 with MD - */ -#define CFG_GPS_PORT_CONFIG 0x00058444 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x200000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00047D01 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0x7f000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h deleted file mode 100644 index 6997c7a..0000000 --- a/include/configs/cerf250.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the CERF250 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_CERF250 1 /* on Cerf PXA Board */ -#define BOARD_LATE_INIT 1 -#define CONFIG_BAUDRATE 38400 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE 0x04000300 -#define CONFIG_SMC_USE_32_BIT - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART on CERF PXA */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.5 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_BOOTCOMMAND "bootm 0xC0000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400" -#define CONFIG_CMDLINE_TAG - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "uboot$ " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) - /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ - -#define CFG_LOAD_ADDR 0xa2000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * GPIO settings - */ - - -#define CFG_GPSR0_VAL 0x00408030 -#define CFG_GPSR1_VAL 0x00BFA882 -#define CFG_GPSR2_VAL 0x0001C000 -#define CFG_GPCR0_VAL 0xC0031100 -#define CFG_GPCR1_VAL 0xFC400300 -#define CFG_GPCR2_VAL 0x00003FFF -#define CFG_GPDR0_VAL 0xC0439330 -#define CFG_GPDR1_VAL 0xFCFFAB82 -#define CFG_GPDR2_VAL 0x0001FFFF -#define CFG_GAFR0_L_VAL 0x80000000 -#define CFG_GAFR0_U_VAL 0xA5000010 -#define CFG_GAFR1_L_VAL 0x60008018 -#define CFG_GAFR1_U_VAL 0xAAA5AAAA -#define CFG_GAFR2_L_VAL 0xAAA0000A -#define CFG_GAFR2_U_VAL 0x00000002 - -#define CFG_PSSR_VAL 0x20 - -/* - * Memory settings - */ -#define CFG_MSC0_VAL 0x12447FF0 -#define CFG_MSC1_VAL 0x12BC5554 -#define CFG_MSC2_VAL 0x7FF97FF1 -#define CFG_MDCNFG_VAL 0x00001AC9 -#define CFG_MDREFR_VAL 0x03CDC017 -#define CFG_MDMRS_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 - -#define _LED 0x08000010 /*check this */ -#define LED_BLANK 0x08000040 -#define LED_GPIO 0x10 - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_MONITOR_LEN 0x40000 /* 256 KiB */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h deleted file mode 100644 index 5947c2a..0000000 --- a/include/configs/cm4008.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) Copyright 2004 - * Greg Ungerer . - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_KS8695 1 /* it is a KS8695 CPU */ -#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CFG_ENV_IS_NOWHERE -#define CONFIG_SERIAL1 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#undef CONFIG_COMMANDS -#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV)) - -#define CONFIG_BOOTDELAY 0 -#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200" -#define CONFIG_BOOTCOMMAND "gofsk 0x02200000" - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "boot > " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00800000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x00008000 /* default load address */ - -#define CFG_HZ (1000) /* 1ms resolution ticks */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ - -#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h deleted file mode 100644 index e62fc06..0000000 --- a/include/configs/cm41xx.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer . - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_KS8695 1 /* it is a KS8695 CPU */ -#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CFG_ENV_IS_NOWHERE -#define CONFIG_SERIAL1 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#undef CONFIG_COMMANDS -#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV)) - -#define CONFIG_BOOTDELAY 0 -#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200" -#define CONFIG_BOOTCOMMAND "gofsk 0x02200000" - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "boot > " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00800000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x00008000 /* default load address */ - -#define CFG_HZ (1000) /* 1ms resolution ticks */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h deleted file mode 100644 index 46280f7..0000000 --- a/include/configs/cmc_pu2.h +++ /dev/null @@ -1,253 +0,0 @@ -/* - * 2004-2005 Gary Jennejohn - * - * Configuration settings for the CMC PU2 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ -#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CFG_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ - -/* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CONFIG_BAUDRATE 9600 - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#undef CONFIG_DBGU -#define CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_HARD_I2C - -#ifdef CONFIG_HARD_I2C -#define CFG_I2C_SPEED 0 /* not used */ -#define CFG_I2C_SLAVE 0 /* not used */ -#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ -#define CFG_I2C_RTC_ADDR 0x32 -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_I2C_EEPROM_ADDR_OVERFLOW -#endif -/* still about 20 kB free with this defined */ -#define CFG_LONGHELP - -#define CONFIG_BOOTDELAY 3 - -#ifdef CONFIG_HARD_I2C -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) & \ - ~(CFG_CMD_FPGA | CFG_CMD_MISC) ) -#else -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) & \ - ~(CFG_CMD_FPGA | CFG_CMD_MISC) ) -#define CONFIG_TIMESTAMP -#endif -#define CFG_LONGHELP - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ -#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */ - -#define CFG_MEMTEST_START PHYS_SDRAM -#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 - -#define CONFIG_DRIVER_ETHER -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_AT91C_USE_RMII - -#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) -#define CFG_MAX_DATAFLASH_BANKS 2 -#define CFG_MAX_DATAFLASH_PAGES 16384 -#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ -#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ - -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 256 -#define CFG_FLASH_ERASE_TOUT (11 * CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT ( 2 * CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */ -#define CFG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */ -#define CFG_ENV_SIZE (16 << 10) /* Use only 16 kB */ - -#define CFG_LOAD_ADDR 0x21000000 /* default load address */ - -#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } - -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_MAXARGS 32 /* max number of command args */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ - -#ifndef __ASSEMBLY__ -/*----------------------------------------------------------------------- - * Board specific extension for bd_info - * - * This structure is embedded in the global bd_info (bd_t) structure - * and can be used by the board specific code (eg board/...) - */ - -struct bd_info_ext { - /* helper variable for board environment handling - * - * env_crc_valid == 0 => uninitialised - * env_crc_valid > 0 => environment crc in flash is valid - * env_crc_valid < 0 => environment crc in flash is invalid - */ - int env_crc_valid; -}; -#endif /* __ASSEMBLY__ */ - -#define CFG_HZ 1000 -#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#define CFG_DEVICE_NULLDEV 1 /* enble null device */ -#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ - -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" -#define CONFIG_AUTOBOOT_STOP_STR "R" /* default password */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \ - "addmtd;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \ - "addcons addmtd; bootm\0" \ - "flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \ - "flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \ - "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "${hostname}::off\0" \ - "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \ - "64k(environment),768k(linux),4096k(root),-\0" \ - "load=tftp ${loadaddr} ${loadfile}\0" \ - "update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \ - "cp.b ${loadaddr} 10000000 ${filesize};" \ - "protect on 10000000 1001ffff\0" \ - "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \ - "cp.b ${loadaddr} 10030000 ${filesize}\0" \ - "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \ - "cp.b ${loadaddr} 100f0000 ${filesize}\0" \ - "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \ - "cp.b ${loadaddr} 104f0000 ${filesize}\0" \ - "cramfsimage=cramfs_cmc-pu2.img\0" \ - "jffsimage=jffs2_cmc-pu2.img\0" \ - "loadfile=u-boot_cmc-pu2.bin\0" \ - "bootfile=uImage_cmc-pu2\0" \ - "loadaddr=0x20800000\0" \ - "hostname=CMC-TC-PU2\0" \ - "bootcmd=run dhcp_start;run flash_cramfs\0" \ - "autoload=n\0" \ - "dhcp_start=echo no DHCP\0" \ - "ipaddr=192.168.0.190\0" -#endif /* __CONFIG_H */ diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h deleted file mode 100644 index e459919..0000000 --- a/include/configs/cmi_mpc5xx.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, - */ - -/* - * File: cmi_mpc5xx.h - * - * Discription: Config header file for cmi - * board using an MPC5xx CPU - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_CMI 1 /* Using the customized cmi board */ - -/* Serial Console Configuration */ -#define CONFIG_5xx_CONS_SCI1 -#undef CONFIG_5xx_CONS_SCI2 - -#define CONFIG_BAUDRATE 57600 - -#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \ - CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ASKENV | \ - CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_ENV | CFG_CMD_RUN | \ - CFG_CMD_IMI) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ - -#define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */ - -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ - -#define CONFIG_STATUS_LED 1 /* Enable status led */ - -#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ - -/* - * Miscellaneous configurable options - */ - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } - - -/* - * Low Level Configuration Settings - */ - -/* - * Internal Memory Mapped (This is not the IMMR content) - */ -#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */ - -/* - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */ -#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ - -/* - * Start addresses for the final memory configuration - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ -#define CFG_FLASH_BASE 0x02000000 /* External flash */ -#define PLD_BASE 0x03000000 /* PLD */ -#define ANYBUS_BASE 0x03010000 /* Anybus Module */ - -#define CFG_RESET_ADRESS 0x01000000 /* Adress which causes reset */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/*----------------------------------------------------------------------- - * FLASH organization - *----------------------------------------------------------------------- - * - */ - -#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_PROTECTION 1 /* Physically section protection on */ - -#define CFG_ENV_IS_IN_FLASH 1 - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ -#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ - SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration - *----------------------------------------------------------------------- - * Data show cycle - */ -#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register - *----------------------------------------------------------------------- - * Set all bits to 40 Mhz - * - */ -#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ -#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) - - -/*----------------------------------------------------------------------- - * UMCR - UIMB Module Configuration Register - *----------------------------------------------------------------------- - * - */ -#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ - -/*----------------------------------------------------------------------- - * ICTRL - I-Bus Support Control Register - */ -#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ - -/*----------------------------------------------------------------------- - * USIU - Memory Controller Register - *----------------------------------------------------------------------- - */ - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16) -#define CFG_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3) -#define CFG_BR1_PRELIM (ANYBUS_BASE) -#define CFG_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR) -#define CFG_BR2_PRELIM (CFG_SDRAM_BASE | BR_V | BR_PS_32) -#define CFG_OR2_PRELIM (OR_ADDR_MK_FF) -#define CFG_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8) -#define CFG_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \ - OR_ACS_10 | OR_ETHR | OR_CSNT) - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */ - -/*----------------------------------------------------------------------- - * DER - Timer Decrementer - *----------------------------------------------------------------------- - * Initialise to zero - */ -#define CFG_DER 0x00000000 - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h deleted file mode 100644 index 9033fa8..0000000 --- a/include/configs/cobra5272.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Configuation settings for the Sentec Cobra Board. - * - * (C) Copyright 2003 Josef Baumgartner - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* --- - * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board - * Date: 2004-03-29 - * Author: Florian Schlote - * - * For a description of configuration options please refer also to the - * general u-boot-1.x.x/README file - * --- - */ - -/* --- - * board/config.h - configuration options, board specific - * --- - */ - -#ifndef _CONFIG_COBRA5272_H -#define _CONFIG_COBRA5272_H - -/* --- - * Define processor - * possible values for Sentec board: only Coldfire M5272 processor supported - * (please do not change) - * --- - */ - -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5272 /* define processor type */ - -/* --- - * Defines processor clock - important for correct timings concerning serial - * interface etc. - * CFG_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms - * --- - */ - -#define CFG_HZ 1000 -#define CFG_CLK 66000000 -#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ - -/* --- - * Enable use of Ethernet - * --- - */ - -#define FEC_ENET - -/* --- - * Define baudrate for UART1 (console output, tftp, ...) - * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CFG_BAUDRATE_TABLE defines values that can be selected in u-boot command - * interface - * --- - */ - -#define CONFIG_BAUDRATE 19200 -#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } - -/* --- - * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change - * timeout acc. to your needs - * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 - * for 10 sec - * --- - */ - -#if 0 -#define CONFIG_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ -#endif - -/* --- - * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different - * bootloader residing in flash ('chainloading'); if you want to use - * chainloading or want to compile a u-boot binary that can be loaded into - * RAM via BDM set - * "#if 0" to "#if 1" - * You will need a first stage bootloader then, e. g. colilo or a working BDM - * cable (Background Debug Mode) - * - * Setting #if 0: u-boot will start from flash and relocate itself to RAM - * - * Please do not forget to modify the setting of TEXT_BASE - * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000) - * - * --- - */ - -#if 0 -#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */ -#endif - -/* --- - * Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - * --- - */ - -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CFG_ENV_OFFSET 0x4000 -#define CFG_ENV_SECT_SIZE 0x2000 -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_IS_EMBEDDED 1 -#else -#define CFG_ENV_ADDR 0xffe04000 -#define CFG_ENV_SECT_SIZE 0x2000 -#define CFG_ENV_IS_IN_FLASH 1 -#endif - -/* --- - * Define which commmands should be available at u-boot command prompt - * --- - */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | CFG_CMD_PING & ~(CFG_CMD_LOADS | \ -CFG_CMD_LOADB) | CFG_CMD_MII) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - *----------------------------------------------------------------------------- - * Define user parameters that have to be customized most likely - *----------------------------------------------------------------------------- - */ - -/*AUTOBOOT settings - booting images automatically by u-boot after power on*/ - -#define CONFIG_BOOTDELAY 5 /* used for autoboot, delay in -seconds u-boot will wait before starting defined (auto-)boot command, setting -to -1 disables delay, setting to 0 will too prevent access to u-boot command -interface: u-boot then has to reflashed */ - - -/* The following settings will be contained in the environment block ; if you -want to use a neutral environment all those settings can be manually set in -u-boot: 'set' command */ - -#if 0 - -#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please -enter a valid image address in flash */ - -#define CONFIG_BOOTARGS " " /* default bootargs that are -considered during boot */ - -/* User network settings */ - -#define CONFIG_ETHADDR 00:00:00:00:00:09 /* default ethernet MAC addr. */ -#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ -#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ - -#endif - -#define CFG_PROMPT "COBRA > " /* Layout of u-boot prompt*/ - -#define CFG_LOAD_ADDR 0x20000 /*Defines default RAM address -from which user programs will be started */ - -/*---*/ - -#define CFG_LONGHELP /* undef to save memory */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* - *----------------------------------------------------------------------------- - * End of user parameters to be customized - *----------------------------------------------------------------------------- - */ - -/* --- - * Defines memory range for test - * --- - */ - -#define CFG_MEMTEST_START 0x400 -#define CFG_MEMTEST_END 0x380000 - -/* --- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * --- - */ - -/* --- - * Base register address - * --- - */ - -#define CFG_MBAR 0x10000000 /* Register Base Addrs */ - -/* --- - * System Conf. Reg. & System Protection Reg. - * --- - */ - -#define CFG_SCR 0x0003; -#define CFG_SPR 0xffff; - -/* --- - * Ethernet settings - * --- - */ - -#define CFG_DISCOVER_PHY -#define CFG_ENET_BD_BASE 0x780000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in internal SRAM) - */ -#define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 - -/* - *------------------------------------------------------------------------- - * RAM SIZE (is defined above) - *----------------------------------------------------------------------- - */ - -/* #define CFG_SDRAM_SIZE 16 */ - -/* - *----------------------------------------------------------------------- - */ - -#define CFG_FLASH_BASE 0xffe00000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CFG_MONITOR_BASE 0x20000 -#else -#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) -#endif - -#define CFG_MONITOR_LEN 0x20000 -#define CFG_MALLOC_LEN (256 << 10) -#define CFG_BOOTPARAMS_LEN 64*1024 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 1000 /* flash timeout */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 - -/*----------------------------------------------------------------------- - * Memory bank definitions - * - * Please refer also to Motorola Coldfire user manual - Chapter XXX - * - */ -#define CFG_BR0_PRELIM 0xFFE00201 -#define CFG_OR0_PRELIM 0xFFE00014 - -#define CFG_BR1_PRELIM 0 -#define CFG_OR1_PRELIM 0 - -#define CFG_BR2_PRELIM 0 -#define CFG_OR2_PRELIM 0 - -#define CFG_BR3_PRELIM 0 -#define CFG_OR3_PRELIM 0 - -#define CFG_BR4_PRELIM 0 -#define CFG_OR4_PRELIM 0 - -#define CFG_BR5_PRELIM 0 -#define CFG_OR5_PRELIM 0 - -#define CFG_BR6_PRELIM 0 -#define CFG_OR6_PRELIM 0 - -#define CFG_BR7_PRELIM 0x00000701 -#define CFG_OR7_PRELIM 0xFF00007C - -/*----------------------------------------------------------------------- - * LED config - */ -#define LED_STAT_0 0xffff /*all LEDs off*/ -#define LED_STAT_1 0xfffe -#define LED_STAT_2 0xfffd -#define LED_STAT_3 0xfffb -#define LED_STAT_4 0xfff7 -#define LED_STAT_5 0xffef -#define LED_STAT_6 0xffdf -#define LED_STAT_7 0xff00 /*all LEDs on*/ - -/*----------------------------------------------------------------------- - * Port configuration (GPIO) - */ -#define CFG_PACNT 0x00000000 /* PortA control reg.: All pins are external -GPIO*/ -#define CFG_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs -(1^=output, 0^=input) */ -#define CFG_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ -#define CFG_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART -configuration */ -#define CFG_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ -#define CFG_PBDAT 0x0000 /* PortB value reg. */ -#define CFG_PDCNT 0x00000000 /* PortD control reg. */ - -#endif /* _CONFIG_COBRA5272_H */ diff --git a/include/configs/cogent_common.h b/include/configs/cogent_common.h deleted file mode 100644 index cdf5802..0000000 --- a/include/configs/cogent_common.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen, CSIRO-MST - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _CONFIG_COGENT_COMMON_H -#define _CONFIG_COGENT_COMMON_H - -/* - * Cogent Motherboard Capabilities - */ -#define CMA_MB_CAP_SERPAR 0x0001 /* has dual serial+parallel (16C552) */ -#define CMA_MB_CAP_LCD 0x0002 /* has LCD display (HD44780) */ -#define CMA_MB_CAP_FLASH 0x0004 /* has flash (E28F800B or AM29F800BB) */ -#define CMA_MB_CAP_RTC 0x0008 /* has RTC+NVRAM (MK48T02) */ -#define CMA_MB_CAP_ETHER 0x0010 /* has Ethernet (MB86964) */ -#define CMA_MB_CAP_SLOT1 0x0020 /* has CMABus slot 1 */ -#define CMA_MB_CAP_SLOT2 0x0040 /* has CMABus slot 2 */ -#define CMA_MB_CAP_SLOT3 0x0080 /* has CMABus slot 3 */ -#define CMA_MB_CAP_KBM 0x0100 /* has PS/2 keyboard+mouse (HT6542B) */ -#define CMA_MB_CAP_SER2 0x0200 /* has 2nd dual serial (16C2552) */ -#define CMA_MB_CAP_PCI 0x0400 /* has pci bridge (V360EPC) */ -#define CMA_MB_CAP_PCI_EXT 0x0800 /* can access extended pci space */ -#define CMA_MB_CAP_PCI_ETHER 0x1000 /* has 10/100 ether on PCI (GD82559) */ -#define CMA_MB_CAP_PCI_VIDEO 0x2000 /* has video int'face on PCI (B69000) */ -#define CMA_MB_CAP_PCI_CARDBUS 0x4000 /* has Cardbus Ctlr on PCI (PD6832) */ - -/* - * Cogent option sanity checking - */ - -#if defined(CONFIG_MPC821) || defined(CONFIG_MPC823) || \ - defined(CONFIG_MPC850) || defined(CONFIG_MPC860) - -/* - * check a PowerPC 8xx cpu module has been selected - */ - -# if defined(CONFIG_CMA286_21) - -# define COGENT_CPU_MODULE "CMA286-21" - -# elif defined(CONFIG_CMA286_60_OLD) - -# define COGENT_CPU_MODULE "CMA286-60 (old)" - -# elif defined(CONFIG_CMA286_60) - -# define COGENT_CPU_MODULE "CMA286-60" - -# elif defined(CONFIG_CMA286_60P) - -# define COGENT_CPU_MODULE "CMA286-60P" - -# elif defined(CONFIG_CMA287_21) - -# define COGENT_CPU_MODULE "CMA287-21" - -# elif defined(CONFIG_CMA287_50) - -# define COGENT_CPU_MODULE "CMA287-50" - -# else - -# error Cogent CPU Module must be a PowerPC MPC8xx module - -# endif - -#elif defined(CONFIG_MPC8260) - -/* - * check a PowerPC 8260 cpu module has been selected - */ - -# if defined(CONFIG_CMA282) - -# define COGENT_CPU_MODULE "CMA282" - -# else - -# error Cogent CPU Module must be a PowerPC MPC8260 module - -# endif - -#else - -# error CPU type must be PowerPC 8xx or 8260 - -#endif - -/* - * check a motherboard has been selected - * define the motherboard capabilities while we're at it - */ - -#if defined(CONFIG_CMA101) - -# define COGENT_MOTHERBOARD "CMA101" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_RTC | CMA_MB_CAP_ETHER | \ - CMA_MB_CAP_SLOT1 | CMA_MB_CAP_SLOT2 | \ - CMA_MB_CAP_SLOT3) -# define CMA_MB_NSLOTS 3 - -#elif defined(CONFIG_CMA102) - -# define COGENT_MOTHERBOARD "CMA102" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_RTC | CMA_MB_CAP_SLOT1 | \ - CMA_MB_CAP_SLOT2 | CMA_MB_CAP_SLOT3) -# define CMA_MB_NSLOTS 3 - -#elif defined(CONFIG_CMA110) - -# define COGENT_MOTHERBOARD "CMA110" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ - CMA_MB_CAP_KBM | CMA_MB_CAP_PCI) -# define CMA_MB_NSLOTS 0 - -#elif defined(CONFIG_CMA111) - -# define COGENT_MOTHERBOARD "CMA111" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ - CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \ - CMA_MB_CAP_PCI | CMA_MB_CAP_PCI_EXT | \ - CMA_MB_CAP_PCI_ETHER) -# define CMA_MB_NSLOTS 1 - -#elif defined(CONFIG_CMA120) - -# define COGENT_MOTHERBOARD "CMA120" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ - CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \ - CMA_MB_CAP_SER2 | CMA_MB_CAP_PCI | \ - CMA_MB_CAP_PCI_EXT | CMA_MB_CAP_PCI_ETHER | \ - CMA_MB_CAP_PCI_VIDEO | CMA_MB_CAP_PCI_CARDBUS) -# define CMA_MB_NSLOTS 1 - -#elif defined(CONFIG_CMA150) - -# define COGENT_MOTHERBOARD "CMA150" -# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \ - CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \ - CMA_MB_CAP_KBM) -# define CMA_MB_NSLOTS 0 - -#else - -# error Cogent Motherboard either unsupported or undefined - -#endif - -/* - * check a flash i/o module has been selected if no flash on m/b - */ - -#if defined(CONFIG_CMA302) - -# define COGENT_FLASH_MODULE "CMA302" - -#elif (CMA_MB_CAPS & CMA_MB_CAP_FLASH) == 0 - -# error Cogent Flash I/O module (e.g. CMA302) is required with this Motherboard - -#endif - -/* - * some further sanity checks - */ - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) && (CMA_MB_CAPS & CMA_MB_CAP_SLOT2) -#error Cogent Sanity Check: Both Slot2 and PCI are defined -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI) -#error Extended PCI capability defined without PCI capability -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_ETHER) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI) -#error Motherboard ethernet capability defined without PCI capability -#endif - -#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) && !(CMA_MB_CAPS & CMA_MB_CAP_SERPAR) -#error 2nd dual serial capability defined without serial/parallel capability -#endif -#include "../board/cogent/mb.h" -#endif /* _CONFIG_COGENT_COMMON_H */ diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h deleted file mode 100644 index aea2e64..0000000 --- a/include/configs/cogent_mpc8260.h +++ /dev/null @@ -1,404 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Config header file for Cogent platform using an MPC8xx CPU module - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -/* Cogent Modular Architecture options */ -#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */ -#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#define CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL|CFG_CMD_KGDB)&~CFG_CMD_NET) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/ - -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ -#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ -# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */ -# else -#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ -# endif -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Low Level Cogent settings - * if CFG_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not. - * also, make sure CONFIG_CONS_INDEX is still defined - the index will be - * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B - * (second 2 for CMA120 only) - */ -#define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */ - -#include - -#ifdef CONFIG_CONS_NONE -#define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */ -#endif -#define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */ -#define CONFIG_SHOW_ACTIVITY - -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) -/* - * flash exists on the motherboard - * set these four according to TOP dipsw: - * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low ) - * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high) - */ -#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE -#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE -#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE -#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE -#endif -#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE -#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#define CFG_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\ - HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101) -/* no slaves so just duplicate the master hrcw */ -#define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE CMA_MB_RAM_BASE -#ifdef CONFIG_CMA302 -#define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */ -#else -#define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */ -#endif -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */ -#ifdef CONFIG_CMA302 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */ -#else -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CFG_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR BCR_EBM - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR (SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -#if defined(CONFIG_CMA282) - -/* - * Init Memory Controller: - * - * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM - * and CS2 for (optional) local bus RAM on the CPU module. - * - * Note the motherboard address space (256 Mbyte in size) is connected - * to the 60x Bus and is located starting at address 0. The Hard Reset - * Configuration Word should put the 60x Bus into External Bus Mode, since - * we dont set up any memory controller maps for it (see BCR[EBM], 4-26). - * - * (the *_SIZE vars must be a power of 2) - */ - -#define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */ -#define CFG_CMA_CS0_SIZE (1 << 20) -#if 0 -#define CFG_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */ -#define CFG_CMA_CS2_SIZE (16 << 20) -#endif - -/* - * CS0 maps the EPROM on the cpu module - * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M - * - * Note: We must have already transferred control to the final location - * of the EPROM before these are used, because when BR0/OR0 are set, the - * mirror of the eprom at any other addresses will disappear. - */ - -/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */ -#define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V) -/* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */ -#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_CMA_CS0_SIZE)|\ - ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) - -/* - * CS2 enables the Local Bus SDRAM on the CPU Module - * - * Will leave this unset for the moment, because a) my CPU module has no - * SDRAM installed (it is optional); and b) it will require programming - * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right - * if you can't test it. - */ - -#if 0 -/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */ -#define CFG_BR0_PRELIM ((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V) -/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */ -#define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/) -#endif - -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h deleted file mode 100644 index 80962d3..0000000 --- a/include/configs/cogent_mpc8xx.h +++ /dev/null @@ -1,360 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Config header file for Cogent platform using an MPC8xx CPU module - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is an MPC860 CPU */ -#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -/* Cogent Modular Architecture options */ -#define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */ -#define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */ -#define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */ - -/* serial console configuration */ -#undef CONFIG_8xx_CONS_SMC1 -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */ - -#if defined(CONFIG_CMA286_60_OLD) -#define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */ -#endif - -#define CONFIG_BAUDRATE 230400 - -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/ - -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#define CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_ALLOC_DPRAM - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Low Level Cogent settings - * if CFG_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not. - * also, make sure CONFIG_CONS_INDEX is still defined - the index will be - * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B - * (second 2 for CMA120 only) - */ -#define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */ - -#include - -#define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */ -#define CONFIG_CONS_INDEX 1 -#define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */ -#define CONFIG_SHOW_ACTIVITY -#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) -/* - * flash exists on the motherboard - * set these four according to TOP dipsw: - * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low ) - * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high) - */ -#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE -#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE -#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE -#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE -#endif -#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE -#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE CMA_MB_RAM_BASE -#ifdef CONFIG_CMA302 -#define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */ -#else -#define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */ -#endif -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */ -#ifdef CONFIG_CMA302 -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */ -#else -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -#if defined(CONFIG_CMA286_60_OLD) - -/* - * Init Memory Controller: - * - * NOTE: although the names (CFG_xRn_PRELIM) suggest preliminary settings, - * they are actually the final settings for this cpu/board, because the - * flash and RAM are on the motherboard, accessed via the CMAbus, and the - * mappings are pretty much fixed. - * - * (the *_SIZE vars must be a power of 2) - */ - -#define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */ -#define CFG_CMA_CS0_SIZE (1 << 20) -#define CFG_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */ -#define CFG_CMA_CS1_SIZE (64 << 20) -#define CFG_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */ -#define CFG_CMA_CS2_SIZE (64 << 20) -#define CFG_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */ -#define CFG_CMA_CS3_SIZE (32 << 20) - -/* - * CS0 maps the EPROM on the cpu module - * Set it for 4 wait states, address CFG_MONITOR_BASE and size 1M - * - * Note: We must have already transferred control to the final location - * of the EPROM before these are used, because when BR0/OR0 are set, the - * mirror of the eprom at any other addresses will disappear. - */ - -/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */ -#define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V) -/* mask size CFG_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */ -#define CFG_OR0_PRELIM ((~(CFG_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK) - -/* - * CS1 maps motherboard DRAM and motherboard I/O slot 1 - * (each 32Mbyte in size) - */ - -/* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */ -#define CFG_BR1_PRELIM ((CFG_CMA_CS1_BASE&BR_BA_MSK)|BR_V) -/* mask size CFG_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */ -#define CFG_OR1_PRELIM ((~(CFG_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA) - -/* - * CS2 maps motherboard I/O slots 2 and 3 - * (each 32Mbyte in size) - */ - -/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */ -#define CFG_BR2_PRELIM ((CFG_CMA_CS2_BASE&BR_BA_MSK)|BR_V) -/* mask size CFG_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */ -#define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA) - -/* - * CS3 maps motherboard I/O - * (32Mbyte in size) - */ - -/* base address = CFG_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */ -#define CFG_BR3_PRELIM ((CFG_CMA_CS3_BASE&BR_BA_MSK)|BR_V) -/* mask size CFG_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */ -#define CFG_OR3_PRELIM ((~(CFG_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA) - -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h deleted file mode 100644 index f9586fb..0000000 --- a/include/configs/cpci5200.h +++ /dev/null @@ -1,417 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - - */ - -/************************************************************************* - * (c) 2005 esd gmbh Hannover - * - * - * from IceCube.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - *************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_ICECUBE 1 /* ... on IceCube board */ -#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#if 1 -#define CONFIG_PCI 1 -#if 1 -#define CONFIG_PCI_PNP 1 -#endif -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#endif - -#define CONFIG_MII -#if 0 /* test-only !!! */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_EEPRO100 1 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif - -#define ADD_PCI_CMD CFG_CMD_PCI - -#else /* MPC5100 */ - -#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 0 -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_IDE | \ - CFG_CMD_I2C | \ - CFG_CMD_BSP | \ - CFG_CMD_ELF | \ - CFG_CMD_EXT2 | \ - CFG_CMD_DATE | \ - ADD_PCI_CMD ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT16 1 -#endif -#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT08 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome to esd CPU CPCI/5200;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ - "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ - "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ - "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ - "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ - "loadaddr=01000000\0" \ - "serverip=192.168.2.99\0" \ - "gatewayip=10.0.0.79\0" \ - "user=mu\0" \ - "target=cpci5200.esd\0" \ - "script=cpci5200.bat\0" \ - "image=/tftpboot/vxWorks_cpci5200\0" \ - "ipaddr=10.0.13.196\0" \ - "netmask=255.255.0.0\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_vxworks0" - -#if defined(CONFIG_MPC5200) - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CFG_NVRAM_BASE_ADDR 0xfd010000 -#define CFG_NVRAM_SIZE 32*1024 - -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ -#endif -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 86000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_MULTI_EEPROMS 1 -/* - * Flash configuration - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_SIZE 0x02000000 -#define CFG_FLASH_INCREMENT 0x01000000 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) -#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 - -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* - * Environment settings - */ -#if 1 /* test-only */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x20000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 -#else -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ - /* total size of a CAT24WC32 is 8192 bytes */ -#define CONFIG_ENV_OVERWRITE 1 -#endif - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_UDP_CHECKSUM 1 - -/* - * GPIO configuration - */ -#define CFG_GPS_PORT_CONFIG 0x01052444 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x0004DD00 - -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CFG_CS1_START 0xfd000000 -#define CFG_CS1_SIZE 0x00010000 -#define CFG_CS1_CFG 0x10101410 - -#define CFG_CS3_START 0xfd010000 -#define CFG_CS3_SIZE 0x00010000 -#define CFG_CS3_CFG 0x10109410 - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -/*----------------------------------------------------------------------- - * CPLD stuff - */ -#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - -/* CPLD program pin configuration */ -#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ -#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ -#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ - -#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ -#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ - -#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00) -#define JTAG_GPIO_CFG_SET 0x00000000 -#define JTAG_GPIO_CFG_RESET 0x00F00000 - -#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04) -#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TMS_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C) -#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TMS_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00) -#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TCK_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08) -#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TCK_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00) -#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDI_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08) -#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ -#define JTAG_GPIO_TDI_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04) -#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDO_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C) -#define JTAG_GPIO_TDO_DDR_SET 0x00000000 -#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h deleted file mode 100644 index 776e1d2..0000000 --- a/include/configs/cradle.h +++ /dev/null @@ -1,349 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE 0x10000300 -#define CONFIG_SMC91111_EXT_PHY -#define CONFIG_SMC_USE_32_BIT - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200" -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "bootm 40000" -#define CONFIG_CMDLINE_TAG - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xa2000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ - -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0x00020000 /* absolute address for now */ -#define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ - -/****************************************************************************** - * - * CPU specific defines - * - ******************************************************************************/ - -/* - * GPIO settings - * - * GPIO pin assignments - * GPIO Name Dir Out AF - * 0 NC - * 1 NC - * 2 SIRQ1 I - * 3 SIRQ2 I - * 4 SIRQ3 I - * 5 DMAACK1 O 0 - * 6 DMAACK2 O 0 - * 7 DMAACK3 O 0 - * 8 TC1 O 0 - * 9 TC2 O 0 - * 10 TC3 O 0 - * 11 nDMAEN O 1 - * 12 AENCTRL O 0 - * 13 PLDTC O 0 - * 14 ETHIRQ I - * 15 NC - * 16 NC - * 17 NC - * 18 RDY I - * 19 DMASIO I - * 20 ETHIRQ NC - * 21 NC - * 22 PGMEN O 1 FIXME for debug only enable flash - * 23 NC - * 24 NC - * 25 NC - * 26 NC - * 27 NC - * 28 NC - * 29 NC - * 30 NC - * 31 NC - * 32 NC - * 33 NC - * 34 FFRXD I 01 - * 35 FFCTS I 01 - * 36 FFDCD I 01 - * 37 FFDSR I 01 - * 38 FFRI I 01 - * 39 FFTXD O 1 10 - * 40 FFDTR O 0 10 - * 41 FFRTS O 0 10 - * 42 RS232FOFF O 0 00 - * 43 NC - * 44 NC - * 45 IRSL0 O 0 - * 46 IRRX0 I 01 - * 47 IRTX0 O 0 10 - * 48 NC - * 49 nIOWE O 0 - * 50 NC - * 51 NC - * 52 NC - * 53 NC - * 54 NC - * 55 NC - * 56 NC - * 57 NC - * 58 DKDIRQ I - * 59 NC - * 60 NC - * 61 NC - * 62 NC - * 63 NC - * 64 COMLED O 0 - * 65 COMLED O 0 - * 66 COMLED O 0 - * 67 COMLED O 0 - * 68 COMLED O 0 - * 69 COMLED O 0 - * 70 COMLED O 0 - * 71 COMLED O 0 - * 72 NC - * 73 NC - * 74 NC - * 75 NC - * 76 NC - * 77 NC - * 78 CSIO O 1 - * 79 NC - * 80 CSETH O 1 - * - * NOTE: All NC's are defined to be outputs - * - */ -/* Pin direction control */ -/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */ -#define CFG_GPDR0_VAL 0xfff3bf02 -#define CFG_GPDR1_VAL 0xfbffbf83 -#define CFG_GPDR2_VAL 0x0001ffff -/* Set and Clear registers */ -#define CFG_GPSR0_VAL 0x00400800 -#define CFG_GPSR1_VAL 0x00000480 -#define CFG_GPSR2_VAL 0x00014000 -#define CFG_GPCR0_VAL 0x00000000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 -/* Edge detect registers (these are set by the kernel) */ -#define CFG_GRER0_VAL 0x00000000 -#define CFG_GRER1_VAL 0x00000000 -#define CFG_GRER2_VAL 0x00000000 -#define CFG_GFER0_VAL 0x00000000 -#define CFG_GFER1_VAL 0x00000000 -#define CFG_GFER2_VAL 0x00000000 -/* Alternate function registers */ -#define CFG_GAFR0_L_VAL 0x00000000 -#define CFG_GAFR0_U_VAL 0x00000010 -#define CFG_GAFR1_L_VAL 0x900a9550 -#define CFG_GAFR1_U_VAL 0x00000008 -#define CFG_GAFR2_L_VAL 0x20000000 -#define CFG_GAFR2_U_VAL 0x00000002 - -/* - * Clocks, power control and interrupts - */ -#define CFG_PSSR_VAL 0x00000020 -#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ -#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ -#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ - -/* FIXME - * - * RTC settings - * Watchdog - * - */ - -/* - * Memory settings - * - * FIXME Can ethernet be burst read and/or write?? This is set for lubbock - * Verify timings on all - */ -#define CFG_MSC0_VAL 0x000023FA /* flash bank (cs0) */ -/*#define CFG_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */ -#define CFG_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */ -#define CFG_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */ -#ifdef REDBOOT_WAY -#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ -#define CFG_MDMRS_VAL 0x00000000 -#define CFG_MDREFR_VAL 0x00018018 -#else -#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ -#define CFG_MDMRS_VAL 0x00000000 -#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */ -#endif - -/* - * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) - */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 - -/* Board specific defines */ - -/* LED defines */ -#define YELLOW 0x03 -#define RED 0x02 -#define GREEN 0x01 -#define OFF 0x00 -#define LED_IRDA0 0 -#define LED_IRDA1 2 -#define LED_IRDA2 4 -#define LED_IRDA3 6 -#define CRADLE_LED_SET_REG GPSR2 -#define CRADLE_LED_CLR_REG GPCR2 - -/* SuperIO defines */ -#define CRADLE_SIO_INDEX 0x2e -#define CRADLE_SIO_DATA 0x2f - -/* IO defines */ -#define CRADLE_CPLD_PHYS 0x08000000 -#define CRADLE_SIO1_PHYS 0x08100000 -#define CRADLE_SIO2_PHYS 0x08200000 -#define CRADLE_SIO3_PHYS 0x08300000 -#define CRADLE_ETH_PHYS 0x10000000 - -#ifndef __ASSEMBLY__ - -/* global prototypes */ -void led_code(int code, int color); - -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h deleted file mode 100644 index f04102e..0000000 --- a/include/configs/csb226.h +++ /dev/null @@ -1,472 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. - * - * Configuration for the Cogent CSB226 board. For details see - * http://www.cogcomp.com/csb_csb226.htm - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * include/configs/csb226.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define DEBUG 1 - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_CSB226 1 /* on a CSB226 board */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - /* for timer/console/ethernet */ -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 19200 -#undef CONFIG_MISC_INIT_R /* not used yet */ - -#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0" -#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.1.56 -#define CONFIG_SERVERIP 192.168.1.5 -#define CONFIG_BOOTCOMMAND "bootm 0x40000" -#define CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_CMDLINE_TAG 1 - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ - -/* - * Size of malloc() pool; this lives below the uppermost 128 KiB which are - * used for the RAM copy of the uboot code - * - */ -#define CFG_MALLOC_LEN (128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 128 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xa3000000 /* default load address */ - /* RS: where is this documented? */ - /* RS: is this where U-Boot is */ - /* RS: relocated to in RAM? */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ - /* RS: the oscillator is actually 3680130?? */ -#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ - /* 0101000001 */ - /* ^^^^^ Memory Speed 99.53 MHz */ - /* ^^ Run Mode Speed = 2x Mem Speed */ - /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ - -#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Network chip - */ -#define CONFIG_DRIVER_CS8900 1 -#define CS8900_BUS32 1 -#define CS8900_BASE 0x08000000 - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ - -#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */ -#define CFG_DRAM_SIZE 0x02000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -# if 0 -/* FIXME: switch to _documented_ registers */ -/* - * GPIO settings - * - * GP15 == nCS1 is 1 - * GP24 == SFRM is 1 - * GP25 == TXD is 1 - * GP33 == nCS5 is 1 - * GP39 == FFTXD is 1 - * GP41 == RTS is 1 - * GP47 == TXD is 1 - * GP49 == nPWE is 1 - * GP62 == LED_B is 1 - * GP63 == TDM_OE is 1 - * GP78 == nCS2 is 1 - * GP79 == nCS3 is 1 - * GP80 == nCS4 is 1 - */ -#define CFG_GPSR0_VAL 0x03008000 -#define CFG_GPSR1_VAL 0xC0028282 -#define CFG_GPSR2_VAL 0x0001C000 - -/* GP02 == DON_RST is 0 - * GP23 == SCLK is 0 - * GP45 == USB_ACT is 0 - * GP60 == PLLEN is 0 - * GP61 == LED_A is 0 - * GP73 == SWUPD_LED is 0 - */ -#define CFG_GPCR0_VAL 0x00800004 -#define CFG_GPCR1_VAL 0x30002000 -#define CFG_GPCR2_VAL 0x00000100 - -/* GP00 == DON_READY is input - * GP01 == DON_OK is input - * GP02 == DON_RST is output - * GP03 == RESET_IND is input - * GP07 == RES11 is input - * GP09 == RES12 is input - * GP11 == SWUPDATE is input - * GP14 == nPOWEROK is input - * GP15 == nCS1 is output - * GP17 == RES22 is input - * GP18 == RDY is input - * GP23 == SCLK is output - * GP24 == SFRM is output - * GP25 == TXD is output - * GP26 == RXD is input - * GP32 == RES21 is input - * GP33 == nCS5 is output - * GP34 == FFRXD is input - * GP35 == CTS is input - * GP39 == FFTXD is output - * GP41 == RTS is output - * GP42 == USB_OK is input - * GP45 == USB_ACT is output - * GP46 == RXD is input - * GP47 == TXD is output - * GP49 == nPWE is output - * GP58 == nCPUBUSINT is input - * GP59 == LANINT is input - * GP60 == PLLEN is output - * GP61 == LED_A is output - * GP62 == LED_B is output - * GP63 == TDM_OE is output - * GP64 == nDSPINT is input - * GP65 == STRAP0 is input - * GP67 == STRAP1 is input - * GP69 == STRAP2 is input - * GP70 == STRAP3 is input - * GP71 == STRAP4 is input - * GP73 == SWUPD_LED is output - * GP78 == nCS2 is output - * GP79 == nCS3 is output - * GP80 == nCS4 is output - */ -#define CFG_GPDR0_VAL 0x03808004 -#define CFG_GPDR1_VAL 0xF002A282 -#define CFG_GPDR2_VAL 0x0001C200 - -/* GP15 == nCS1 is AF10 - * GP18 == RDY is AF01 - * GP23 == SCLK is AF10 - * GP24 == SFRM is AF10 - * GP25 == TXD is AF10 - * GP26 == RXD is AF01 - * GP33 == nCS5 is AF10 - * GP34 == FFRXD is AF01 - * GP35 == CTS is AF01 - * GP39 == FFTXD is AF10 - * GP41 == RTS is AF10 - * GP46 == RXD is AF10 - * GP47 == TXD is AF01 - * GP49 == nPWE is AF10 - * GP78 == nCS2 is AF10 - * GP79 == nCS3 is AF10 - * GP80 == nCS4 is AF10 - */ -#define CFG_GAFR0_L_VAL 0x80000000 -#define CFG_GAFR0_U_VAL 0x001A8010 -#define CFG_GAFR1_L_VAL 0x60088058 -#define CFG_GAFR1_U_VAL 0x00000008 -#define CFG_GAFR2_L_VAL 0xA0000000 -#define CFG_GAFR2_U_VAL 0x00000002 - - -/* FIXME: set GPIO_RER/FER */ - -/* RDH = 1 - * PH = 1 - * VFS = 1 - * BFS = 1 - * SSS = 1 - */ -#define CFG_PSSR_VAL 0x37 - -/* - * Memory settings - * - * This is the configuration for nCS0/1 -> flash banks - * configuration for nCS1: - * [31] 0 - Slower Device - * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns - * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns - * [19] 1 - 16 Bit bus width - * [18:16] 000 - nonburst RAM or FLASH - * configuration for nCS0: - * [15] 0 - Slower Device - * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns - * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns - * [03] 1 - 16 Bit bus width - * [02:00] 000 - nonburst RAM or FLASH - */ -#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */ - -/* This is the configuration for nCS2/3 -> TDM-Switch, DSP - * configuration for nCS3: DSP - * [31] 0 - Slower Device - * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns - * [19] 1 - 16 Bit bus width - * [18:16] 100 - variable latency I/O - * configuration for nCS2: TDM-Switch - * [15] 0 - Slower Device - * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns - * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns - * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns - * [03] 1 - 16 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */ - -/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller - * - * configuration for nCS5: LAN Controller - * [31] 0 - Slower Device - * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns - * [19] 1 - 16 Bit bus width - * [18:16] 100 - variable latency I/O - * configuration for nCS4: ExtBus - * [15] 0 - Slower Device - * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns - * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns - * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns - * [03] 1 - 16 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ - -/* MDCNFG: SDRAM Configuration Register - * - * [31:29] 000 - reserved - * [28] 0 - no SA1111 compatiblity mode - * [27] 0 - latch return data with return clock - * [26] 0 - alternate addressing for pair 2/3 - * [25:24] 00 - timings - * [23] 0 - internal banks in lower partition 2/3 (not used) - * [22:21] 00 - row address bits for partition 2/3 (not used) - * [20:19] 00 - column address bits for partition 2/3 (not used) - * [18] 0 - SDRAM partition 2/3 width is 32 bit - * [17] 0 - SDRAM partition 3 disabled - * [16] 0 - SDRAM partition 2 disabled - * [15:13] 000 - reserved - * [12] 1 - SA1111 compatiblity mode - * [11] 1 - latch return data with return clock - * [10] 0 - no alternate addressing for pair 0/1 - * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk - * [7] 1 - 4 internal banks in lower partition pair - * [06:05] 10 - 13 row address bits for partition 0/1 - * [04:03] 01 - 9 column address bits for partition 0/1 - * [02] 0 - SDRAM partition 0/1 width is 32 bit - * [01] 0 - disable SDRAM partition 1 - * [00] 1 - enable SDRAM partition 0 - */ -/* use the configuration above but disable partition 0 */ -#define CFG_MDCNFG_VAL 0x000019c8 - -/* MDREFR: SDRAM Refresh Control Register - * - * [32:26] 0 - reserved - * [25] 0 - K2FREE: not free running - * [24] 0 - K1FREE: not free running - * [23] 1 - K0FREE: not free running - * [22] 0 - SLFRSH: self refresh disabled - * [21] 0 - reserved - * [20] 0 - APD: no auto power down - * [19] 0 - K2DB2: SDCLK2 is MemClk - * [18] 0 - K2RUN: disable SDCLK2 - * [17] 0 - K1DB2: SDCLK1 is MemClk - * [16] 1 - K1RUN: enable SDCLK1 - * [15] 1 - E1PIN: SDRAM clock enable - * [14] 1 - K0DB2: SDCLK0 is MemClk - * [13] 0 - K0RUN: disable SDCLK0 - * [12] 1 - E0PIN: disable SDCKE0 - * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 - */ -#define CFG_MDREFR_VAL 0x0081D018 - -/* MDMRS: Mode Register Set Configuration Register - * - * [31] 0 - reserved - * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) - * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) - * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) - * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) - * [15] 0 - reserved - * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. - * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. - * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. - * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. - */ -#define CFG_MDMRS_VAL 0x00020022 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00000000 -#define CFG_MCMEM1_VAL 0x00000000 -#define CFG_MCATT0_VAL 0x00000000 -#define CFG_MCATT1_VAL 0x00000000 -#define CFG_MCIO0_VAL 0x00000000 -#define CFG_MCIO1_VAL 0x00000000 -#endif - -/* - * GPIO settings - */ -#define CFG_GPSR0_VAL 0xFFFFFFFF -#define CFG_GPSR1_VAL 0xFFFFFFFF -#define CFG_GPSR2_VAL 0xFFFFFFFF -#define CFG_GPCR0_VAL 0x08022080 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 -#define CFG_GPDR0_VAL 0xCD82A878 -#define CFG_GPDR1_VAL 0xFCFFAB80 -#define CFG_GPDR2_VAL 0x0001FFFF -#define CFG_GAFR0_L_VAL 0x80000000 -#define CFG_GAFR0_U_VAL 0xA5254010 -#define CFG_GAFR1_L_VAL 0x599A9550 -#define CFG_GAFR1_U_VAL 0xAAA5AAAA -#define CFG_GAFR2_L_VAL 0xAAAAAAAA -#define CFG_GAFR2_U_VAL 0x00000002 - -/* FIXME: set GPIO_RER/FER */ - -#define CFG_PSSR_VAL 0x20 - -/* - * Memory settings - */ - -#define CFG_MSC0_VAL 0x2ef15af0 -#define CFG_MSC1_VAL 0x00003ff4 -#define CFG_MSC2_VAL 0x7ff07ff0 -#define CFG_MDCNFG_VAL 0x09a909a9 -#define CFG_MDREFR_VAL 0x038ff030 -#define CFG_MDMRS_VAL 0x00220022 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00000000 -#define CFG_MCMEM1_VAL 0x00000000 -#define CFG_MCATT0_VAL 0x00000000 -#define CFG_MCATT1_VAL 0x00000000 -#define CFG_MCIO0_VAL 0x00000000 -#define CFG_MCIO1_VAL 0x00000000 - -#define CSB226_USER_LED0 0x00000008 -#define CSB226_USER_LED1 0x00000010 -#define CSB226_USER_LED2 0x00000020 - - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) - /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h deleted file mode 100644 index 27d64c1..0000000 --- a/include/configs/csb272.h +++ /dev/null @@ -1,314 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ -#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -/* - * OS Bootstrap configuration - * - */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ -#endif - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ - -#if 1 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/ram rw ramdisk_size=4096 " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm fe000000 fe100000" -#endif - -#if 0 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#endif - -/* - * BOOTP/DHCP protocol configuration - * - */ -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_BOOTFILESIZE ) -/* - * U-Boot Monitor Command Line Functions Configuration - * - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_PCI | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Serial download configuration - * - */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * KGDB Configuration - * - */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - * - */ -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */ -#endif - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ -#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * watchdog configuration - * - */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * UART configuration - * - */ -#define CFG_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ -#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#undef CFG_BASE_BAUD -#define CONFIG_BAUDRATE 38400 /* Default baud rate */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * I2C configuration - * - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ - -/* - * MII PHY configuration - * - */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ - /* 32usec min. for LXT971A */ -#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ - -/* - * RTC configuration - * - * Note that DS1307 RTC is limited to 100Khz I2C bus. - * - */ -#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ - -/* - * PCI stuff - * - */ -#define CONFIG_PCI /* include pci support */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * IDE stuff - * - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -/* - * Environment configuration - * - */ -#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM - -/* - * General Memory organization - * - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_SIZE 0x02000000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ - -#if CFG_MONITOR_BASE < CFG_FLASH_BASE -#define CFG_RAMSTART -#endif - -#if defined(CFG_ENV_IS_IN_FLASH) -#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ -#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ -#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ -#endif - -/* - * FLASH Device configuration - * - */ -#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ -#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -/* - * On Chip Memory location/size - * - */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -/* - * Global info and initial stack - * - */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Cache configuration - * - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 - -/* - * Miscellaneous board specific definitions - * - */ -#define CFG_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */ -#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */ - -/* - * Internal Definitions - * - * Boot Flags - * - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h deleted file mode 100644 index 09d52de..0000000 --- a/include/configs/csb472.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ -#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -/* - * OS Bootstrap configuration - * - */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ -#endif - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ - -#if 1 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/ram rw ramdisk_size=4096 " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm ff800000 ff900000" -#endif - -#if 0 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#endif - -/* - * BOOTP/DHCP protocol configuration - * - */ -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_BOOTFILESIZE ) -/* - * U-Boot Monitor Command Line Functions Configuration - * - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_PCI | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Serial download configuration - * - */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * KGDB Configuration - * - */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - * - */ -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */ -#endif - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ -#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * watchdog configuration - * - */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * UART configuration - * - */ -#undef CFG_EXT_SERIAL_CLOCK /* use internal serial clock */ -#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 38400 /* Default baud rate */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * I2C configuration - * - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ - -/* - * MII PHY configuration - * - */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ - /* 32usec min. for LXT971A */ -#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ - -/* - * RTC configuration - * - * Note that DS1307 RTC is limited to 100Khz I2C bus. - * - */ -#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ - -/* - * PCI stuff - * - */ -#define CONFIG_PCI /* include pci support */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * IDE stuff - * - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -/* - * Environment configuration - * - */ -#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM - -/* - * General Memory organization - * - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF800000 -#define CFG_FLASH_SIZE 0x00800000 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ - -#if CFG_MONITOR_BASE < CFG_FLASH_BASE -#define CFG_RAMSTART -#endif - -#if defined(CFG_ENV_IS_IN_FLASH) -#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ -#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ -#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ -#endif - -/* - * FLASH Device configuration - * - */ -#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_MAX_FLASH_SECT 64 /* max # of sectors on one chip */ -#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -/* - * On Chip Memory location/size - * - */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -/* - * Global info and initial stack - * - */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Cache configuration - * - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 - -/* - * Miscellaneous board specific definitions - * - */ -#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */ - -/* - * Internal Definitions - * - * Boot Flags - * - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/csb637.h b/include/configs/csb637.h deleted file mode 100644 index 071d5b7..0000000 --- a/include/configs/csb637.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2005 REA Elektronik GmbH - * Anders Larsen - * - * Configuation settings for the Cogent CSB637 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */ -#define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_CSB637 1 /* on a CSB637 board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CFG_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ -#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ - -/* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CONFIG_BAUDRATE 115200 - -#define CFG_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_BOOTDELAY 3 -/* #define CONFIG_ENV_OVERWRITE 1 */ - -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING ) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_IMI | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC | \ - CFG_CMD_LOADS )) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ -#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ - -#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) -#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) - -#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) -/* the following are NOP's in our implementation */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */ - -#define CFG_MEMTEST_START PHYS_SDRAM -#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4 -#define CFG_ALT_MEMTEST 1 -#define CFG_MEMTEST_SCRATCH CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 4 - -#define CONFIG_DRIVER_ETHER -#define CONFIG_NET_RETRY_COUNT 20 -#undef CONFIG_AT91C_USE_RMII - -#undef CONFIG_HAS_DATAFLASH -#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) -#define CFG_MAX_DATAFLASH_BANKS 0 -#define CFG_MAX_DATAFLASH_PAGES 16384 -#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ -#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ - -/* - * FLASH Device configuration - */ -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ -#define CFG_MAX_FLASH_SECT 64 - -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_FIRST_SECTOR 3 -#define CFG_JFFS2_NUM_BANKS 1 - -#undef CFG_ENV_IS_IN_DATAFLASH - -#ifdef CFG_ENV_IS_IN_DATAFLASH -#define CFG_ENV_OFFSET 0x20000 -#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) -#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ -#else -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */ -#define CFG_ENV_SIZE 0x20000 /* sectors are 128K here */ -#endif /* CFG_ENV_IS_IN_DATAFLASH */ - - -#define CFG_LOAD_ADDR 0x21000000 /* default load address */ - -#define CFG_BAUDRATE_TABLE {115200, 57600, 38400, 19200, 9600 } - -#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ - -#ifndef __ASSEMBLY__ -/*----------------------------------------------------------------------- - * Board specific extension for bd_info - * - * This structure is embedded in the global bd_info (bd_t) structure - * and can be used by the board specific code (eg board/...) - */ - -struct bd_info_ext { - /* helper variable for board environment handling - * - * env_crc_valid == 0 => uninitialised - * env_crc_valid > 0 => environment crc in flash is valid - * env_crc_valid < 0 => environment crc in flash is invalid - */ - int env_crc_valid; -}; -#endif - -#define CFG_HZ 1000 -#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#endif diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h deleted file mode 100644 index 0a10e3c..0000000 --- a/include/configs/dbau1x00.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file contains the configuration parameters for the dbau1x00 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ -#define CONFIG_DBAU1X00 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ - -#ifdef CONFIG_DBAU1000 -/* Also known as Merlot */ -#define CONFIG_AU1000 1 -#else -#ifdef CONFIG_DBAU1100 -#define CONFIG_AU1100 1 -#else -#ifdef CONFIG_DBAU1500 -#define CONFIG_AU1500 1 -#else -#ifdef CONFIG_DBAU1550 -/* Cabernet */ -#define CONFIG_AU1550 1 -#else -#error "No valid board set" -#endif -#endif -#endif -#endif - -#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ - -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ - -#define CONFIG_BAUDRATE 115200 - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "panic=1\0" \ - "bootfile=/tftpboot/vmlinux.srec\0" \ - "load=tftp 80500000 ${u-boot}\0" \ - "" - -#ifdef CONFIG_DBAU1550 -/* Boot from flash by default, revert to bootp */ -#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \ - ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \ - CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \ - CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C)) -#else /* CONFIG_DBAU1550 */ -/* Boot from Compact flash partition 2 as default */ -#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;bootm" - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \ - ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \ - CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \ - CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG)) -#endif /* CONFIG_DBAU1550 */ - -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ - -#define CFG_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */ - -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args*/ - -#define CFG_MALLOC_LEN 128*1024 - -#define CFG_BOOTPARAMS_LEN 128*1024 - -#define CFG_MHZ 396 - -#if (CFG_MHZ % 12) != 0 -#error "Invalid CPU frequency - must be multiple of 12!" -#endif - -#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ - -#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ - -#define CFG_LOAD_ADDR 0x81000000 /* default load address */ - -#define CFG_MEMTEST_START 0x80100000 -#define CFG_MEMTEST_END 0x80800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#ifdef CONFIG_DBAU1550 - -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ - -#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} - -#else /* CONFIG_DBAU1550 */ - -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ - -#endif /* CONFIG_DBAU1550 */ - -#define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 - -/* The following #defines are needed to get flash environment right */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) - -#define CFG_INIT_SP_OFFSET 0x400000 - -/* We boot from this flash, selected with dip switch */ -#define CFG_FLASH_BASE PHYS_FLASH_2 - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_NOWHERE 1 - -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR 0xB0030000 -#define CFG_ENV_SIZE 0x10000 - -#define CONFIG_FLASH_16BIT - -#define CONFIG_NR_DRAM_BANKS 2 - -#define CONFIG_NET_MULTI - -#ifdef CONFIG_DBAU1550 -#define MEM_SIZE 192 -#else -#define MEM_SIZE 64 -#endif - -#define CONFIG_MEMSIZE_IN_BYTES - -#ifndef CONFIG_DBAU1550 -/*---ATA PCMCIA ------------------------------------*/ -#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ -#define CFG_PCMCIA_MEM_ADDR 0x20000000 -#define CONFIG_PCMCIA_SLOT_A - -#define CONFIG_ATAPI 1 -#define CONFIG_MAC_PARTITION 1 - -/* We run CF in "true ide" mode or a harddrive via pcmcia */ -#define CONFIG_IDE_PCMCIA 1 - -/* We only support one slot for now */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET 8 - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET 0 - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 -#endif /* CONFIG_DBAU1550 */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_ICACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 - -#endif /* __CONFIG_H */ diff --git a/include/configs/debris.h b/include/configs/debris.h deleted file mode 100644 index 8ff963f..0000000 --- a/include/configs/debris.h +++ /dev/null @@ -1,459 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Sangmoon Kim, Etin Systems, dogoil@etinsys.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Environments */ - -/* bootargs */ -#define CONFIG_BOOTARGS \ - "console=ttyS0,9600 init=/linuxrc " \ - "root=/dev/nfs rw nfsroot=192.168.0.1:" \ - "/tftpboot/target " \ - "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \ - "255.255.255.0:debris:eth0:none " \ - "mtdparts=phys:12m(root),-(kernel)" - -/* bootcmd */ -#define CONFIG_BOOTCOMMAND \ - "tftp 800000 pImage; " \ - "setenv bootargs console=ttyS0,9600 init=/linuxrc " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:eth0:none " \ - "mtdparts=phys:12m(root),-(kernel); " \ - "bootm 800000" - -/* bootdelay */ -#define CONFIG_BOOTDELAY 5 /* autoboot 5s */ - -/* baudrate */ -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ - -/* loads_echo */ -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ - -/* ethaddr */ -#undef CONFIG_ETHADDR - -/* eth2addr */ -#undef CONFIG_ETH2ADDR - -/* eth3addr */ -#undef CONFIG_ETH3ADDR - -/* ipaddr */ -#define CONFIG_IPADDR 192.168.0.2 - -/* serverip */ -#define CONFIG_SERVERIP 192.168.0.1 - -/* autoload */ -#undef CFG_AUTOLOAD - -/* rootpath */ -#define CONFIG_ROOTPATH /tftpboot/target - -/* gatewayip */ -#define CONFIG_GATEWAYIP 192.168.0.1 - -/* netmask */ -#define CONFIG_NETMASK 255.255.255.0 - -/* hostname */ -#define CONFIG_HOSTNAME debris - -/* bootfile */ -#define CONFIG_BOOTFILE pImage - -/* loadaddr */ -#define CONFIG_LOADADDR 800000 - -/* preboot */ -#undef CONFIG_PREBOOT - -/* clocks_in_mhz */ -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_DEBRIS 1 - -#if 0 -#define USE_DINK32 1 -#else -#undef USE_DINK32 -#endif - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_DRAM_SPEED 100 /* MHz */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGBD | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_SAVES | \ - CFG_CMD_SDRAM) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_EEPRO100_SROM_WRITE - -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET0_MEMADDR 0x80000000 -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET1_MEMADDR 0x81000000 -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x20000000 -#define CONFIG_VERY_BIG_RAM - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#if defined (USE_DINK32) -#define CFG_MONITOR_LEN 0x00040000 -#define CFG_MONITOR_BASE 0x00090000 -#define CFG_RAMBOOT 1 -#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_INIT_RAM_END 0x10000 -#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#else -#undef CFG_RAMBOOT -#define CFG_MONITOR_LEN 0x00040000 -#define CFG_MONITOR_BASE TEXT_BASE - -/*#define CFG_GBL_DATA_SIZE 256*/ -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -#endif - -#define CFG_FLASH_BASE 0x7C000000 -#define CFG_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */ - -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - -#define CFG_EUMB_ADDR 0xFC000000 - -#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ -#define CFG_FLASH_RANGE_SIZE 0x01000000 -#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=debris-0" -#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)" -*/ - -#define CFG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_OVERWRITE 1 -#define CFG_NVRAM_ACCESS_ROUTINE 1 -#define CFG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */ -#define CFG_ENV_SIZE 0x400 /* Size of the Environment - 8K */ -#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ - -#define CFG_NVRAM_BASE_ADDR 0xff000000 - -/* - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS = - * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET - */ -#define CFG_NVRAM_VXWORKS_OFFS 0x6900 - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#ifdef CONFIG_SOFT_I2C -#error "Soft I2C is not configured properly. Please review!" -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM } - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK 7372800 - -#define CFG_NS16550_COM1 0xFF080000 -#define CFG_NS16550_COM2 (CFG_NS16550_COM1 + 8) -#define CFG_NS16550_COM3 (CFG_NS16550_COM1 + 16) -#define CFG_NS16550_COM4 (CFG_NS16550_COM1 + 24) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 - -#define CFG_DLL_EXTEND 0x00 -#define CFG_PCI_HOLD_DEL 0x20 - -#define CFG_ROMNAL 15 /* rom/flash next access time */ -#define CFG_ROMFAL 31 /* rom/flash access time */ - -#define CFG_REFINT 430 /* # of clocks between CBR refresh cycles */ - -#define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ - -/* the following are for SDRAM only*/ -#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CFG_REFREC 8 /* Refresh to activate interval */ -#define CFG_RDLAT 4 /* data latency from read command */ -#define CFG_PRETOACT 3 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_ACTORW 3 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#if 0 -#define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ -#endif - -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 1 -#define CFG_REGDIMM 0 - - -/* memory bank settings*/ -/* - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (0x4000000 - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x04000000 -#define CFG_BANK1_END (0x8000000 - 1) -#define CFG_BANK1_ENABLE 1 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 -/* - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CFG_BANK_ENABLE 0x01 - -#define CFG_ODCR 0x75 /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#if defined(USE_DINK32) -#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) -#else -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#endif - -/* PCI memory */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ - -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#define CONFIG_DISK_SPINUP_TIME 1000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h deleted file mode 100644 index 9ac2856..0000000 --- a/include/configs/dnp1110.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Rolf Offermanns - * - * Configuation settings for the SSV DNP1110 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * If we are developing, we might want to start armboot from ram - * so we MUST NOT initialize critical regs like mem-timing ... - */ -#define CONFIG_SKIP_LOWLEVEL_INIT 1 -#undef CONFIG_SKIP_RELOCATE_UBOOT - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SA1110 1 /* This is an SA1110 CPU */ -#define CONFIG_DNP1110 1 /* on an DNP/1110 Board */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE 0x20000300 - - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" -#define CONFIG_ETHADDR 02:80:ad:20:31:b8 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 172.22.2.23 -#define CONFIG_SERVERIP 172.22.2.22 -#define CONFIG_BOOTFILE "dnp1110" -#define CONFIG_BOOTCOMMAND "tftp; bootm" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "DNP1110 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xc0200000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x0b /* set core clock to 220 MHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ -#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xF80000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h deleted file mode 100644 index a014c7c..0000000 --- a/include/configs/eXalion.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -/* #define CONFIG_MPC8240 1 */ -#define CONFIG_MPC8245 1 -#define CONFIG_EXALION 1 - -#if defined (CONFIG_MPC8240) - /* #warning ---------- eXalion with MPC8240 --------------- */ -#elif defined (CONFIG_MPC8245) - /* #warning ++++++++++ eXalion with MPC8245 +++++++++++++++ */ -#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245) -#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245) -#else -#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif -/* older kernels need clock in MHz newer in Hz */ - /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */ -#undef CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_BOOTDELAY 10 - - - /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_FLASH | \ - CFG_CMD_SDRAM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ENV | \ - CFG_CMD_PCI ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 8 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_MISC_INIT_R 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x10000000 /* 1 GBytes - initdram() will */ - /* return real value. */ - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#undef CFG_RAMBOOT -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE TEXT_BASE - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) - -#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - - -#if defined (CONFIG_MPC8240) -#define CFG_FLASH_BASE 0xFFE00000 -#define CFG_FLASH_SIZE (2 * 1024 * 1024) /* onboard 2MByte flash */ -#elif defined (CONFIG_MPC8245) -#define CFG_FLASH_BASE 0xFFC00000 -#define CFG_FLASH_SIZE (4 * 1024 * 1024) /* onboard 4MByte flash */ -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x20000 /* Size of one Flash sector */ -#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Use one Flash sector for enviroment */ -#define CFG_ENV_ADDR 0xFFFC0000 -#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ - -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -#define CFG_ALT_MEMTEST 1 /* use real memory test */ -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -#define CFG_EUMB_ADDR 0xFC000000 - -/* #define CFG_ISA_MEM 0xFD000000 */ -#define CFG_ISA_IO 0xFE000000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE -#define FLASH_BASE1_PRELIM 0 - - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI 1 /* include pci support */ -#undef CONFIG_PCI_PNP - -#define CONFIG_NET_MULTI 1 /* Multi ethernet cards support */ - -#define CONFIG_EEPRO100 1 - -#define PCI_ENET0_MEMADDR 0x80000000 /* Intel 82559ER */ -#define PCI_ENET0_IOADDR 0x80000000 -#define PCI_ENET1_MEMADDR 0x81000000 /* Intel 82559ER */ -#define PCI_ENET1_IOADDR 0x81000000 -#define PCI_ENET2_MEMADDR 0x82000000 /* Broadcom BCM569xx */ -#define PCI_ENET2_IOADDR 0x82000000 -#define PCI_ENET3_MEMADDR 0x83000000 /* Broadcom BCM56xx */ -#define PCI_ENET3_IOADDR 0x83000000 - -/*----------------------------------------------------------------------- - * NS16550 Configuration - */ -#define CFG_NS16550 1 -#define CFG_NS16550_SERIAL 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 38400 - -#define CFG_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX == 1) -#define CFG_NS16550_CLK 1843200 /* COM1 only ! */ -#else -#define CFG_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); }) -#endif - -#define CFG_NS16550_COM1 (CFG_ISA_IO + 0x3F8) -#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4600) - -/*----------------------------------------------------------------------- - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/*----------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -#define CFG_HZ 1000 - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */ - - /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */ - -#if defined (CONFIG_MPC8245) -/* Bit-field values for PMCR2. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_DLL_EXTEND 0x80 /* use DLL extended range - 133MHz only */ -#define CFG_PCI_HOLD_DEL 0x20 /* delay and hold timing - 133MHz only */ -#endif - -/* Bit-field values for MIOCR1. */ -#if !defined (CONFIG_133MHZ_DRAM) -#define CFG_DLL_MAX_DELAY 0x04 /* longer DLL delay line - 66MHz only */ -#endif -/* Bit-field values for MIOCR2. */ -#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay */ - /* - note bottom 3 bits MUST be 0 */ -#endif - -/* Bit-field values for MCCR1. */ -#define CFG_ROMNAL 7 /*rom/flash next access time */ -#define CFG_ROMFAL 11 /*rom/flash access time */ - -/* Bit-field values for MCCR2. */ -#define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_REFINT 1300 /* no of clock cycles between CBR */ -#else /* refresh cycles */ -#define CFG_REFINT 750 -#endif - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_BSTOPRE 1023 -#else -#define CFG_BSTOPRE 250 -#endif - -/* Bit-field values for MCCR3. */ -/* the following are for SDRAM only */ - -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_REFREC 9 /* Refresh to activate interval */ -#else -#define CFG_REFREC 5 /* Refresh to activate interval */ -#endif -#if defined (CONFIG_MPC8240) -#define CFG_RDLAT 2 /* data latency from read command */ -#endif - -/* Bit-field values for MCCR4. */ -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_PRETOACT 3 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 7 /* Activate to Precharge interval */ -#define CFG_ACTORW 5 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#else -#if 0 -#define CFG_PRETOACT 2 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 3 /* Activate to Precharge interval */ -#define CFG_ACTORW 3 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ -#endif -#define CFG_PRETOACT 2 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_ACTORW 3 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#endif -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ -#define CFG_REGDIMM 0 -#if defined (CONFIG_MPC8240) -#define CFG_REGISTERD_TYPE_BUFFER 0 -#elif defined (CONFIG_MPC8245) -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 0 -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - - -/*----------------------------------------------------------------------- - memory bank settings - * only bits 20-29 are actually used from these vales to set the - * start/end address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 - -/*----------------------------------------------------------------------- - * Memory bank enable bitmask, specifying which of the banks defined above - are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CFG_BANK_ENABLE 0x01 - -#if defined (CONFIG_MPC8240) -#define CFG_ODCR 0xDF /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#elif defined (CONFIG_MPC8245) -#if defined (CONFIG_133MHZ_DRAM) -#define CFG_ODCR 0xFE /* configures line driver impedances - 133MHz */ -#else -#define CFG_ODCR 0xDE /* configures line driver impedances - 66MHz */ -#endif -#else -#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) -#endif - -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/*----------------------------------------------------------------------- - * Block Address Translation (BAT) register settings. - */ -/* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -/* PCI memory */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Flash, config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/*----------------------------------------------------------------------- - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -/* values according to the manual */ -#define CONFIG_DRAM_50MHZ 1 -#define CONFIG_SDRAM_50MHZ - -#undef NR_8259_INTS -#define NR_8259_INTS 1 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - */ -#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR CFG_ISA_IO /* base address */ -#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ - -#define CONFIG_ATAPI - -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide supported... */ -#undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ - -/*----------------------------------------------------------------------- - * DISK Partition support - */ -#define CONFIG_DOS_PARTITION - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h deleted file mode 100644 index a26af69..0000000 --- a/include/configs/ebony.h +++ /dev/null @@ -1,295 +0,0 @@ -/* - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_EBONY 1 /* Board is ebony */ -#define CONFIG_440GP 1 /* Specifc GP support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -/* - * Define here the location of the environment variables (FLASH or NVRAM). - * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only - * supported for backward compatibility. - */ -#if 1 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#endif - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) -#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -#ifdef CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_NVRAM */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ -#define CFG_MAX_FLASH_SECT 32 /* sectors per device */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_FLASH_ADDR0 0x5555 -#define CFG_FLASH_ADDR1 0x2aaa -#define CFG_FLASH_WORD_SIZE unsigned char - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=ebony\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/ebony/uImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ff810000\0" \ - "load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 8 /* PHY address */ -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT /* let board init pci target */ - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h deleted file mode 100644 index bdda629..0000000 --- a/include/configs/ep7312.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the EP7312 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ -#define CONFIG_EP7312 1 /* on an EP7312 Board */ -#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ - -#undef CONFIG_USE_IRQ /* don't need them anymore */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x20000000 -#define CS8900_BUS16 1 -#undef CS8900_BUS32 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" -#define CONFIG_ETHADDR 08:00:3e:21:c7:f7 -/*#define CONFIG_NETMASK 255.255.0.0 */ -/*#define CONFIG_IPADDR 172.22.2.128 */ -/*#define CONFIG_SERVERIP 172.22.2.126 */ -/*#define CONFIG_BOOTFILE "impa7" */ -#define CONFIG_BOOTCOMMAND "bootp;bootm" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "EP7312 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xc0500000 /* default load address */ - -#define CFG_HZ 2000 /* decrementer freq: 2 kHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=ep7312-0" -#define MTDPARTS_DEFAULT "mtdparts=ep7312-0:-(jffs2)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h deleted file mode 100644 index 04147a5..0000000 --- a/include/configs/ep8248.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (C) 2004 Arabella Software Ltd. - * Yuli Barcohen - * - * U-Boot configuration for Embedded Planet EP8248 boards. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC8248 -#define CPU_ID_STR "MPC8248" - -#define CONFIG_EP8248 /* Embedded Planet EP8248 board */ - -#undef DEBUG - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ -#define CONFIG_ENV_OVERWRITE - -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ - -#define CFG_BCSR 0xFA000000 - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ -#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ - -#if (CONFIG_ETHER_INDEX == 1) - -/* - Rx clock is CLK10 - * - Tx clock is CLK11 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#elif (CONFIG_ETHER_INDEX == 2) - -/* - Rx clock is CLK13 - * - Tx clock is CLK14 - * - BDs/buffers on 60x bus - * - Full duplex - */ -#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 0 /* Not used - implemented in BCSR */ -#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB) -#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04) -#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1) - -#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \ - else *(vu_char *)(CFG_BCSR + 8) &= 0xFE - -#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \ - else *(vu_char *)(CFG_BCSR + 8) &= 0xFD - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ - | CFG_CMD_I2C \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -#endif - -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_FLASH_BASE 0xFF800000 -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CFG_DIRECT_FLASH_TFTP - -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS -#define CFG_JFFS2_FIRST_SECTOR 0 -#define CFG_JFFS2_LAST_SECTOR 62 -#define CFG_JFFS2_SORT_FRAGMENTS -#define CFG_JFFS_CUSTOM_PART -#endif /* CFG_CMD_JFFS2 */ - -#if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ -#endif /* CFG_CMD_I2C */ - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ - -#define CFG_ENV_IS_IN_FLASH - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#endif /* CFG_ENV_IS_IN_FLASH */ - -#define CFG_DEFAULT_IMMR 0x00010000 - -#define CFG_IMMR 0xF0000000 - -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */ -/* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CFG_HID2 0 - -#define CFG_SIUMCR 0x01240200 -#define CFG_SYPCR 0xFFFF0683 -#define CFG_BCR 0x00000000 -#define CFG_SCCR SCCR_DFBRG01 - -#define CFG_RMR RMR_CSRE -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -#define CFG_RCCR 0 - -#define CFG_MPTPR 0x1300 -#define CFG_PSDMR 0x82672522 -#define CFG_PSRT 0x4B - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00001841) -#define CFG_SDRAM_OR 0xFF0030C0 - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) -#define CFG_OR0_PRELIM 0xFF8008C2 -#define CFG_BR2_PRELIM (CFG_BCSR | 0x00000801) -#define CFG_OR2_PRELIM 0xFFF00864 - -#define CFG_RESET_ADDRESS 0xC0000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h deleted file mode 100644 index 6862519..0000000 --- a/include/configs/ep8260.h +++ /dev/null @@ -1,775 +0,0 @@ -/* - * (C) Copyright 2002 - * Frank Panno , Delphin Technology AG - * - * This file is based on similar values for other boards found in other - * U-Boot config files, and some that I found in the EP8260 manual. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - * - * "EP8260 H, V.1.1" - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 16M Flash (4 x AM29DL323DB90WDI) - * - 128k NVRAM with RTC - * - * "EP8260 H2, V.1.3" (CFG_EP8260_H2) - * - 300MHz/133MHz/66MHz - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 32M Flash - * - 128k NVRAM with RTC - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Define this to enable support the EP8260 H2 version */ -#define CFG_EP8260_H2 1 -/* #undef CFG_EP8260_H2 */ - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core - * ------- ---------- --- --- ---- - * 0x2 0x2 33 133 133 - * 0x2 0x3 33 133 166 - * 0x2 0x4 33 133 200 - * 0x2 0x5 33 133 233 - * 0x2 0x6 33 133 266 - * - * 0x5 0x5 66 133 133 - * 0x5 0x6 66 133 166 - * 0x5 0x7 66 133 200 * - * 0x6 0x0 66 133 233 - * 0x6 0x1 66 133 266 - * 0x6 0x2 66 133 300 - */ -#ifdef CFG_EP8260_H2 -#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110) -#else -#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110) -#endif - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -/* #define CFG_SBC_BOOT_LOW 1 */ /* only for HRCW */ -/* #undef CFG_SBC_BOOT_LOW */ - -/* The reset command will not work as expected if the reset address does - * not point to the correct address. - */ - -#define CFG_RESET_ADDRESS 0xFFF00100 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#ifdef CFG_EP8260_H2 -#define CFG_FLASH0_BASE 0xFE000000 -#define CFG_FLASH0_SIZE 32 -#else -#define CFG_FLASH0_BASE 0xFF000000 -#define CFG_FLASH0_SIZE 16 -#endif - -/* What should the base address of the secondary FLASH be and how big - * is it (in Mbytes)? The secondary FLASH is whichever is connected - * to *CS6. U-Boot expects this to be the on board FLASH. If you don't - * want it enabled, don't define these constants. - */ -#define CFG_FLASH1_BASE 0 -#define CFG_FLASH1_SIZE 0 -#undef CFG_FLASH1_BASE -#undef CFG_FLASH1_SIZE - -/* What should be the base address of SDRAM DIMM (60x bus) and how big is - * it (in Mbytes)? -*/ -#define CFG_SDRAM0_BASE 0x00000000 -#define CFG_SDRAM0_SIZE 64 - -/* define CFG_LSDRAM if you want to enable the 32M SDRAM on the - * local bus (8260 local bus is NOT cacheable!) -*/ -/* #define CFG_LSDRAM */ -#undef CFG_LSDRAM - -#ifdef CFG_LSDRAM -/* What should be the base address of SDRAM DIMM (local bus) and how big is - * it (in Mbytes)? -*/ - #define CFG_SDRAM1_BASE 0x04000000 - #define CFG_SDRAM1_SIZE 32 -#else - #define CFG_SDRAM1_BASE 0 - #define CFG_SDRAM1_SIZE 0 - #undef CFG_SDRAM1_BASE - #undef CFG_SDRAM1_SIZE -#endif /* CFG_LSDRAM */ - -/* What should be the base address of NVRAM and how big is - * it (in Bytes) - */ -#define CFG_NVRAM_BASE_ADDR 0xFA080000 -#define CFG_NVRAM_SIZE (128*1024)-16 - -/* The RTC is a Dallas DS1556 - */ -#define CONFIG_RTC_DS1556 - -/* What should be the base address of the LEDs and switch S0? - * If you don't want them enabled, don't define this. - */ -#define CFG_LED_BASE 0x00000000 -#undef CFG_LED_BASE - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */ - -#if ( CONFIG_ETHER_INDEX == 3 ) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the local Bus (see 28-13) - * - Enable Half Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) - -/* - * - RAM for BD/Buffers is on the local Bus (see 28-13) - */ -#ifdef CFG_LSDRAM - #define CFG_CPMFCR_RAMTYPE 3 -#else /* CFG_LSDRAM */ - #define CFG_CPMFCR_RAMTYPE 0 -#endif /* CFG_LSDRAM */ - -/* - Enable Half Duplex in FSMR */ -/* # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */ -# define CFG_FCC_PSMR 0 - -#else /* CONFIG_ETHER_INDEX */ -# error "on EP8260 ethernet must be FCC3" -#endif /* CONFIG_ETHER_INDEX */ - -/* - * select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ -#ifdef CONFIG_SOFT_I2C -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -/* #define CONFIG_RTC_DS174x */ - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CFG_ENV_IN_OWN_SECT - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#ifdef CFG_EP8260_H2 -#define CONFIG_BAUDRATE 9600 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -/* Ethernet MAC address */ -#define CONFIG_ETHADDR 00:10:EC:00:30:8C - -#define CONFIG_IPADDR 192.168.254.130 -#define CONFIG_SERVERIP 192.168.254.49 - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY -1 - -/* undef this to save memory */ -#define CFG_LONGHELP - -/* Monitor Command Prompt */ -#define CFG_PROMPT "=> " - -/* Define this variable to enable the "hush" shell (from - Busybox) as command line interpreter, thus enabling - powerful command line syntax like - if...then...else...fi conditionals or `&&' and '||' - constructs ("shell scripts"). - If undefined, you get the old, much simpler behaviour - with a somewhat smapper memory footprint. -*/ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " - -/* What U-Boot subsytems do you want enabled? */ -/* -*/ -#define CONFIG_COMMANDS ( CFG_CMD_ALL & \ - ~( CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_DCR | \ - CFG_CMD_DHCP | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGDB | \ - CFG_CMD_MII | \ - CFG_CMD_MMC | \ - CFG_CMD_NAND | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_REISER | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_UNIVERSE| \ - CFG_CMD_USB | \ - CFG_CMD_VFD | \ - CFG_CMD_XIMG ) ) - - -/* Where do the internal registers live? */ -#define CFG_IMMR 0xF0000000 -#define CFG_DEFAULT_IMMR 0x00010000 - -/* Where do the on board registers (CS4) live? */ -#define CFG_REGS_BASE 0xFA000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) - -#define CFG_MAXARGS 8 /* max number of command args */ - -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#ifdef CFG_LSDRAM - #define CFG_MEMTEST_START 0x04000000 /* memtest works on */ - #define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */ -#else - #define CFG_MEMTEST_START 0x00000000 /* memtest works on */ - #define CFG_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */ -#endif /* CFG_LSDRAM */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_TFTP_LOADADDR 0x00100000 /* default load address for network file downloads */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_SDRAM_BASE CFG_SDRAM0_BASE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ - -#if defined(CFG_SBC_BOOT_LOW) -# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CFG_SBC_HRCW_BOOT_FLAGS (0x00000000) -#endif /* defined(CFG_SBC_BOOT_LOW) */ - -#ifdef CFG_EP8260_H2 -/* get the HRCW ISB field from CFG_DEFAULT_IMMR */ -#define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\ - ((CFG_DEFAULT_IMMR & 0x01000000) >> 7) |\ - ((CFG_DEFAULT_IMMR & 0x00100000) >> 4) ) - -#define CFG_HRCW_MASTER (HRCW_EBM |\ - HRCW_L2CPC01 |\ - CFG_SBC_HRCW_IMMR |\ - HRCW_APPC10 |\ - HRCW_CS10PC01 |\ - CFG_SBC_MODCK_H |\ - CFG_SBC_HRCW_BOOT_FLAGS) -#else -#define CFG_HRCW_MASTER 0x10400245 -#endif - -/* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CFG_RAMBOOT is platform dependent. - */ -#define CFG_MONITOR_BASE TEXT_BASE - - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CFG_EP8260_H2 -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#else -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#endif - -#ifdef CFG_EP8260_H2 -#define CFG_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#else -#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ -#endif - -#ifndef CFG_RAMBOOT -# define CFG_ENV_IS_IN_FLASH 1 - -# ifdef CFG_ENV_IN_OWN_SECT -# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -# define CFG_ENV_SECT_SIZE 0x40000 -# else -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) -# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CFG_ENV_IN_OWN_SECT */ -#else -# define CFG_ENV_IS_IN_NVRAM 1 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) -# define CFG_ENV_SIZE 0x200 -#endif /* CFG_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) -#ifdef CFG_LSDRAM -/* 8260 local bus is NOT cacheable */ -#define CFG_HID0_FINAL (/*HID0_ICE |*/\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#else /* !CFG_LSDRAM */ -#define CFG_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#endif /* CFG_LSDRAM */ - -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CFG_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR (BCR_EBM |\ - BCR_PLDP |\ - BCR_EAV |\ - BCR_NPQM0) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_L2CPC01 |\ - SIUMCR_APPC10 |\ - SIUMCR_CS10PC01) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#ifdef CFG_EP8260_H2 -/* TBD: Find out why setting the BMT to 0xff causes the FCC to - * generate TX buffer underrun errors for large packets under - * Linux - */ -#define CFG_SYPCR_BMT 0x00000600 -#else -#define CFG_SYPCR_BMT SYPCR_BMT -#endif - -#ifdef CFG_LSDRAM -#define CFG_SYPCR (SYPCR_SWTC |\ - CFG_SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC |\ - CFG_SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#ifdef CFG_EP8260_H2 -#define CFG_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) -#else -#define CFG_PISCR 0 -#endif - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#ifdef CFG_EP8260_H2 -#define CFG_SCCR (SCCR_DFBRG00) -#else -#define CFG_SCCR (SCCR_DFBRG01) -#endif - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescale Register 10-32 - *----------------------------------------------------------------------- - */ -#define CFG_MPTPR (0x0A00 & MPTPR_PTP_MSK) - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI) - * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG) - * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG) - * 3 unused - * 4 60x GPCM 8 bit Board Regs, NVRTC - * 5 unused - * 6 unused - * 7 unused - * 8 PCMCIA - * 9 unused - * 10 unused - * 11 unused -*/ - -/*----------------------------------------------------------------------- - * BRx - Base Register - * Ref: Section 10.3.1 on page 10-14 - * ORx - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0 - FLASH - * - */ -#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_8_CLK |\ - ORxG_EHTR) - -/* Bank 1 - SDRAM - * PSDRAM - */ -#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_12) - -#ifdef CFG_EP8260_H2 -#define CFG_PSDMR 0xC34E246E -#else -#define CFG_PSDMR 0xC34E2462 -#endif - -#define CFG_PSRT 0x64 - -#ifdef CFG_LSDRAM -/* Bank 2 - SDRAM - * LSDRAM - */ - - #define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - - #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - - #define CFG_LSDMR 0x416A2562 - #define CFG_LSRT 0x64 -#else - #define CFG_LSRT 0x0 -#endif /* CFG_LSDRAM */ - -/* Bank 4 - On board registers - * NVRTC and BCSR - */ -#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) -/* -#define CFG_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_10_CLK |\ - ORxG_TRLX) -*/ -#define CFG_OR4_PRELIM 0xfff00854 - -#ifdef _NOT_USED_SINCE_NOT_WORKING_ -/* Bank 8 - On board registers - * PCMCIA (currently not working!) - */ -#define CFG_BR8_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CFG_OR8_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SETA |\ - ORxG_SCY_10_CLK) -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h deleted file mode 100644 index 88c2c74..0000000 --- a/include/configs/evb4510.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * Configuation settings for evb4510 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * If we are developing, we might want to start u-boot from ram - * so we MUST NOT initialize critical regs like mem-timing ... - * - * Also swap the flash1 and flash2 addresses during debug. - * - * #define CONFIG_SKIP_LOWLEVEL_INIT - */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ -#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ -#define CONFIG_S3C4510B 1 /* it's a S3C4510B chip */ -#define CONFIG_EVB4510 1 /* on an EVB4510 Board */ - -#define CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) -#define CONFIG_STACKSIZE_FIQ (4*1024) - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_S3C4510_ETH 1 -#define CONFIG_DRIVER_S3C4510_I2C 1 -#define CONFIG_DRIVER_S3C4510_UART 1 -#define CONFIG_DRIVER_S3C4510_FLASH 1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use Serial line 1, could also use 2 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 19200 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_ETHADDR 00:40:95:36:35:33 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.0.11 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_CMDLINE_TAG /* submit bootargs to kernel */ - -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTCOMMAND "tftp 100000 uImage" -/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "evb4510 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_CMDLINE_TAG /* allow passing of command line args to linux */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00780000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x00000000 /* default load address */ - -#define CFG_SYS_CLK_FREQ 50000000 /* CPU freq: 50 MHz */ -#define CFG_HZ 1000 /* decrementer freq: 1 KHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below -*/ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map after relocation - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ - -#define PHYS_FLASH_1 0x01000000 /* Flash Bank #1 */ -#define PHYS_FLASH_1_SIZE 0x00200000 /* 2 MB (one chip, 8bit access) */ - -#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ -#define PHYS_FLASH_2_SIZE 0x00080000 /* 512KB (one chip, 8bit access) */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_FLASH_SIZE PHYS_FLASH_1_SIZE - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ -#define CFG_MAIN_SECT_SIZE 0x00010000 /* main size of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (4*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -/* environment settings */ -#define CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_NOWHERE - -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x20000) /* environment start address */ -#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CFG_ENV_SIZE 0x1000 /* max size for environment */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h deleted file mode 100644 index b68a2dc..0000000 --- a/include/configs/gcplus.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * 2003-2004 (c) MontaVista Software, Inc. - * - * Configuation settings for the ADS GraphicsClient+ board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG - -/* - * The ADS GCPlus Linux boot ROM loads U-Boot into RAM at 0xc0200000. - * We don't actually init RAM in this case since we're using U-Boot as - * an secondary boot loader during Linux kernel development and testing, - * e.g. bootp/tftp download of the kernel is a far more convenient - * when testing new kernels on this target. However the ADS GCPlus Linux - * boot ROM leaves the MMU enabled when it passes control to U-Boot. So - * we use lowlevel_init (CONFIG_INIT_CRITICAL) to remedy that problem. - */ -#undef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SKIP_RELOCATE_UBOOT 1 - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SA1110 1 /* This is an SA1100 CPU */ -#define CONFIG_GCPLUS 1 /* on an ADS GCPlus Board */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size rsrvd for initial data */ - - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */ -#define CONFIG_LAN91C96_BASE 0x100e0000 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL3 1 /* we use SERIAL 3 on ADS GCPlus */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp" -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" -#define CFG_AUTOLOAD "n" /* No autoload */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 38400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "ADS GCPlus # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xc0000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x0a /* set core clock to 206MHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ -#define PHYS_SDRAM_2 0xc8000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */ - - -#define PHYS_FLASH_1 0x08000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ -#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#if 1 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#else -/* REVISIT: This doesn't work on ADS GCPlus just yet: */ -#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ -/*#define CFG_FLASH_PROTECTION 1 /--* hardware flash protection */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#endif - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE - -#endif /* __CONFIG_H */ diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h deleted file mode 100644 index 6c08043..0000000 --- a/include/configs/gw8260.h +++ /dev/null @@ -1,821 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Oliver Brown - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*********************************************************************/ -/* DESCRIPTION: - * This file contains the board configuartion for the GW8260 board. - * - * MODULE DEPENDENCY: - * None - * - * RESTRICTIONS/LIMITATIONS: - * None - * - * Copyright (c) 2001, Advent Networks, Inc. - */ -/*********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Enable debug prints */ -#undef DEBUG /* General debug */ -#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 - * ------- ---------- --- --- ---- ----- ----- ----- - * 0x5 0x5 66 133 133 Open Close Open - * 0x5 0x6 66 133 166 Open Open Close - * 0x5 0x7 66 133 200 Open Open Open - * 0x6 0x0 66 133 233 Close Close Close - * 0x6 0x1 66 133 266 Close Close Open - * 0x6 0x2 66 133 300 Close Open Close - */ -#define CFG_SBC_MODCK_H 0x05 - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CFG_SBC_BOOT_LOW 1 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#define CFG_FLASH0_BASE 0x40000000 -#define CFG_FLASH0_SIZE 8 - -/* Define CFG_FLASH_CHECKSUM to enable flash checksum during boot. - * Note: the 'flashchecksum' environment variable must also be set to 'y'. - */ -#define CFG_FLASH_CHECKSUM - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? - */ -#define CFG_SDRAM0_BASE 0x00000000 -#define CFG_SDRAM0_SIZE 64 - -/* - * DRAM tests - * CFG_DRAM_TEST - enables the following tests. - * - * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CFG_DRAM_TEST -#if defined(CFG_DRAM_TEST) -#define CFG_DRAM_TEST_DATA -#define CFG_DRAM_TEST_ADDRESS -#define CFG_DRAM_TEST_WALK -#endif /* CFG_DRAM_TEST */ - -/* - * GW8260 with 16 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x00F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x00F5 FFB0 Board Info Data - * 0x00F6 0000 Malloc Arena - * : CFG_ENV_SECT_SIZE, 256k - * : CFG_MALLOC_LEN, 128k - * 0x00FC 0000 RAM Copy of Monitor Code - * : CFG_MONITOR_LEN, 256k - * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 - */ - -/* - * GW8260 with 64 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x03F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x03F5 FFB0 Board Info Data - * 0x03F6 0000 Malloc Arena - * : CFG_ENV_SECT_SIZE, 256k - * : CFG_MALLOC_LEN, 128k - * 0x03FC 0000 RAM Copy of Monitor Code - * : CFG_MONITOR_LEN, 256k - * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 - */ - - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ - -#undef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_ON_FCC -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ - -#ifdef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif /* CONFIG_ETHER_ON_SCC */ - -#ifdef CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) -#endif /* CONFIG_ETHER_ON_FCC */ - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CFG_ENV_IN_OWN_SECT - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 115200 - -/* Ethernet MAC address - This is set to all zeros to force an - * an error if we use BOOTP without setting - * the MAC address - */ -#define CONFIG_ETHADDR 00:00:00:00:00:00 - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n" -#define CONFIG_AUTOBOOT_STOP_STR " " -#undef CONFIG_AUTOBOOT_DELAY_STR -#define DEBUG_BOOTKEYS 0 - -/* Add support for a few extra bootp options like: - * - File size - * - DNS - */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS) - -/* undef this to save memory */ -#define CFG_LONGHELP - -/* Monitor Command Prompt */ -#define CFG_PROMPT "=> " - -/* What U-Boot subsytems do you want enabled? */ -#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MII) - -/* Where do the internal registers live? */ -#define CFG_IMMR 0xf0000000 - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* What is the address of IO controller */ -#define CFG_IO_BASE 0xe0000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_GW8260 1 /* on an GW8260 Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) - -#define CFG_MAXARGS 8 /* max number of command args */ - -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Convert clocks to MHZ when passing board info to kernel. - * This must be defined for eariler 2.4 kernels (~2.4.4). - */ -#define CONFIG_CLOCKS_IN_MHZ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - - -/* memtest works from the end of the exception vector table - * to the end of the DRAM less monitor and malloc area - */ -#define CFG_MEMTEST_START 0x2000 - -#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ - -#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ - + CFG_MALLOC_LEN \ - + CFG_ENV_SECT_SIZE \ - + CFG_STACK_USAGE ) - -#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ - - CFG_MEM_END_USAGE ) - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE -#define CFG_SDRAM_BASE CFG_SDRAM0_BASE -#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CFG_SBC_BOOT_LOW) -# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CFG_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CFG_SBC_BOOT_LOW) */ - -/* get the HRCW ISB field from CFG_IMMR */ -#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ - ((CFG_IMMR & 0x01000000) >> 7) | \ - ((CFG_IMMR & 0x00100000) >> 4) ) - -#define CFG_HRCW_MASTER ( HRCW_BPS11 | \ - HRCW_DPPC11 | \ - CFG_SBC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC11 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \ - CFG_SBC_HRCW_BOOT_FLAGS ) - -/* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CFG_RAMBOOT is platform dependent. - */ -#define CFG_MONITOR_BASE CFG_FLASH0_BASE - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 - -#ifdef CFG_ENV_IN_OWN_SECT -# define CFG_ENV_ADDR (CFG_MONITOR_BASE + (256 * 1024)) -# define CFG_ENV_SECT_SIZE (256 * 1024) -#else -# define CFG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */ -# define CFG_ENV_ADD ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) - CFG_ENV_SIZE) -# define CFG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */ -#endif /* CFG_ENV_IN_OWN_SECT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CFG_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CFG_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_DPPC11 |\ - SIUMCR_L2CPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_MMR00) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CFG_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CFG_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Initialize Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) - * 1 60x GPCM 32 bit unused - * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB) - * 3 60x SDRAM 64 bit unused - * 4 Local GPCM 8 bit IO (on board - 64k) - * 5 60x GPCM 8 bit unused - * 6 60x GPCM 8 bit unused - * 7 60x GPCM 8 bit unused - * - */ - -/*----------------------------------------------------------------------- - * BR0 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR0 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0,1 - FLASH SIMM - * - * This expects the FLASH SIMM to be connected to *CS0 - * It consists of 4 AM29F016D parts. - * - * Note: For the 8 MB SIMM, *CS1 is unused. - */ - -/* BR0 is configured as follows: - * - * - Base address of 0x40000000 - * - 32 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR0 is configured as follows: - * - * - 8 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR2 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* Bank 2 - SDRAM DIMM - * - * 16MB DIMM: P/N - * 64MB DIMM: P/N 1W-8864X8-4-P1-EST or - * MT4LSDT864AG-10EB1 (Micron) - * - * Note: *CS3 is unused for this DIMM - */ - -/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows: - * - * - Base address of 0x00000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 16 MB DIMM, the OR2 is configured as follows: - * - * - 16 MB - * - 2 internal banks per device - * - Row start address bit is A9 with PSDMR[PBI] = 0 - * - 11 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CFG_SDRAM0_SIZE == 16) -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_2 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_11) - -/* With a 16 MB DIMM, the PSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A16-A18 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ -#define CFG_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A16_A18 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#endif /* (CFG_SDRAM0_SIZE == 16) */ - -/* With a 64 MB DIMM, the OR2 is configured as follows: - * - * - 64 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CFG_SDRAM0_SIZE == 64) -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) - -/* With a 64 MB DIMM, the PSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A14-A16 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ -#define CFG_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#endif /* (CFG_SDRAM0_SIZE == 64) */ - -#define CFG_PSRT 0x0e -#define CFG_MPTPR MPTPR_PTP_DIV32 - - -/*----------------------------------------------------------------------- - * BR4 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR4 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ -/* Bank 4 - Onboard Memory Mapped IO controller - * - * This expects the onboard IO controller to connected to *CS4 and - * the local bus. - * - Base address of 0xe0000000 - * - 8 bit port size (local bus only) - * - Read and write access - * - GPCM local bus - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - * - extended hold time - * - 11 wait states - */ - -#ifdef CFG_IO_BASE -# define CFG_BR4_PRELIM ((CFG_IO_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_L |\ - BRx_V) - -# define CFG_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_SCY_11_CLK |\ - ORxG_EHTR) -#endif /* CFG_IO_BASE */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/h2_p2_dbg_board.h b/include/configs/h2_p2_dbg_board.h deleted file mode 100644 index e0d823f..0000000 --- a/include/configs/h2_p2_dbg_board.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * TI H2 and P2 Debug Board hardware map - * - * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk) - * Author: MPC-Data Limited - * Dave Peverley - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __INCLUDED_H2_P2_DBH_BOARD_H -#define __INCLUDED_H2_P2_DBH_BOARD_H - -#include - -/* - * The Debug board is designed to function with the P2 Sample, H2 - * Sample and 1610 Innovator boards. The main difference AFAICT is - * the chip selects used with each system ; - * - * P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs - * H2 Sample : CS1a is used to select the CPLD registers. - * - */ - -/*************************************************************************** - * CPLD Registers - **************************************************************************/ - -#define H2DBG_CPLD_REVISION 0x04000010 -#define H2DBG_BOARD_REVISION 0x04000012 -#define H2DBG_GPIO_REGISTER 0x04000014 -#define H2DBG_LED_CONTROL 0x04000016 -#define H2DBG_MISC_INPUT 0x04000018 -#define H2DBG_LAN_STATUS 0x0400001A -#define H2DBG_LAN_RESET 0x0400001C -#define H2DBG_ETH_REG_BASE 0x04000300 - -/*************************************************************************** - * Ethernet Control Registers - * These are for the LAN91C96 on the debug board - **************************************************************************/ - -/* Bank 0 in IO space */ - -#define ETH_TCR (H2DBG_ETH_REG_BASE + 0x00) /* Transmit Control Register */ -#define ETH_EPH_STATUS (H2DBG_ETH_REG_BASE + 0x02) /* EPH Status Register */ -#define ETH_RCR (H2DBG_ETH_REG_BASE + 0x04) /* Receive Control Register */ -#define ETH_COUNTER (H2DBG_ETH_REG_BASE + 0x06) /* Counter Register */ -#define ETH_MIR (H2DBG_ETH_REG_BASE + 0x08) /* Memory Information Register */ -#define ETH_MCR (H2DBG_ETH_REG_BASE + 0x0A) /* Memory Configuration Register */ - -/* Bank 1 in IO space */ - -#define ETH_CONFIG (H2DBG_ETH_REG_BASE + 0x00) /* Configuration Register */ -#define ETH_BASE (H2DBG_ETH_REG_BASE + 0x02) /* Base Address Register */ -#define ETH_IA0 (H2DBG_ETH_REG_BASE + 0x04) /* Individual Address Register - 0 */ -#define ETH_IA1 (H2DBG_ETH_REG_BASE + 0x05) /* Individual Address Register - 1 */ -#define ETH_IA2 (H2DBG_ETH_REG_BASE + 0x06) /* Individual Address Register - 2 */ -#define ETH_IA3 (H2DBG_ETH_REG_BASE + 0x07) /* Individual Address Register - 3 */ -#define ETH_IA4 (H2DBG_ETH_REG_BASE + 0x08) /* Individual Address Register - 4 */ -#define ETH_IA5 (H2DBG_ETH_REG_BASE + 0x09) /* Individual Address Register - 5 */ -#define ETH_GEN_PURPOSE (H2DBG_ETH_REG_BASE + 0x0A) /* General Address Registers */ -#define ETH_CONTROL (H2DBG_ETH_REG_BASE + 0x0B) /* Control Register */ - -/* Bank 2 in IO space */ - -#define ETH_MMU (H2DBG_ETH_REG_BASE + 0x00) /* MMU Command Register */ -#define ETH_AUTO_TX_START (H2DBG_ETH_REG_BASE + 0x01) /* Auto Tx Start Register */ -#define ETH_PNR (H2DBG_ETH_REG_BASE + 0x02) /* Packet Number Register */ -#define ETH_ARR (H2DBG_ETH_REG_BASE + 0x03) /* Allocation Result Register */ -#define ETH_FIFO (H2DBG_ETH_REG_BASE + 0x04) /* FIFO Ports Register */ -#define ETH_POINTER (H2DBG_ETH_REG_BASE + 0x06) /* Pointer Register */ -#define ETH_DATA_HIGH (H2DBG_ETH_REG_BASE + 0x08) /* Data High Register */ -#define ETH_DATA_LOW (H2DBG_ETH_REG_BASE + 0x0A) /* Data Low Register */ -#define ETH_INT_STATS (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Status Register - RO */ -#define ETH_INT_ACK (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Acknowledge Register -WO */ -#define ETH_INT_MASK (H2DBG_ETH_REG_BASE + 0x0D) /* Interrupt Mask Register */ - - -#ifndef __ASSEMBLY__ - -/* - * A couple of utility inlines to aid debugging using the LED's on the - * debug board. - */ - -static inline void set_led_state(int state) -{ - static unsigned long hw_led_state = 0; - volatile unsigned short *led_address = (volatile unsigned short *)0x04000016; - - hw_led_state = ((unsigned long)state); - *((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF); -} - - -static inline void spin_up_leds(void) -{ - volatile int i, j, k; - - for (k = 0; k < 2; k++) { - for (i = 0; i < 16; i++) { - for (j = 0; j < 5000; j++) { - set_led_state(1 << i); - } - } - for (i = 15; i >= 0; i--) { - for (j = 0; j < 5000; j++) { - set_led_state(1 << i); - } - } - } -} - -#endif /* ! __ASSEMBLY__ */ - -#endif /* ! __INCLUDED_H2_P2_DBH_BOARD_H */ diff --git a/include/configs/hermes.h b/include/configs/hermes.h deleted file mode 100644 index 91117ba..0000000 --- a/include/configs/hermes.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860T CPU */ -#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_COMMANDS CONFIG_CMD_DFL - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/*----------------------------------------------------------------------*/ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_ALLOC_DPRAM 1 /* use allocation routines */ -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 /* Non-Standard value! */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFE000000 -#ifdef DEBUG -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - * +0x0004 - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * +0x0000 => 0x000000C0 - */ -#define CFG_SIUMCR 0 - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - * +0x0200 => 0x00C2 - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - * +0x0240 => 0x0082 - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* +0x0286 => 0x00B0D0C0 */ -#define CFG_PLPRCR \ - ( (11 << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ - ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* +0x0282 => 0x03800000 */ -#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/* +0x0220 => 0x00C3 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => TIMEP=1 */ -#define CFG_RCCR 0x0100 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CFG_RMDS 0 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */ - -/* used to re-map FLASH - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -/* allow for max 4 MB of Flash */ -#define CFG_REMAP_OR_AM 0xFFC00000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \ - OR_SCY_5_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -/* 8 bit, bank valid */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR1/OR1 - SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ -#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#define CFG_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide - */ -#define HPRO2_BASE 0xE0000000 -#define HPRO2_OR_AM 0xFFFF8000 -#define HPRO2_TIMING 0x00000934 - -#define CFG_OR2 (HPRO2_OR_AM | HPRO2_TIMING) -#define CFG_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) - -/* - * BR3/OR3: not used - * BR4/OR4: not used - * BR5/OR5: not used - * BR6/OR6: not used - * BR7/OR7: not used - */ - -/* - * MAMR settings for SDRAM - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h deleted file mode 100644 index cfaf153..0000000 --- a/include/configs/hmi1001.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_HMI1001 1 /* HMI1001 board */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_BOARD_EARLY_INIT_R - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ -#define CONFIG_DOS_PARTITION - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (TEXT_BASE == 0xFFF00000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_MISC_INIT_R 1 - -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE 0xFF800000 - -#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_CFI_AMD_RESET - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x4000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 -#define CFG_DISPLAY_BASE 0x80600000 -#define CFG_STATUS1_BASE 0x80600200 -#define CFG_STATUS2_BASE 0x80600300 - -/* Settings for XLB = 132 MHz */ -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#define CFG_GPS_PORT_CONFIG 0x01051004 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CFG_ALT_MEMTEST - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x0004FB00 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -/* 8Mbit SRAM @0x80100000 */ -#define CFG_CS1_START 0x80100000 -#define CFG_CS1_SIZE 0x00100000 -#define CFG_CS1_CFG 0x19B00 - -/* FRAM 32Kbyte @0x80700000 */ -#define CFG_CS2_START 0x80700000 -#define CFG_CS2_SIZE 0x00008000 -#define CFG_CS2_CFG 0x19800 - -/* Display H1, Status Inputs, EPLD @0x80600000 */ -#define CFG_CS3_START 0x80600000 -#define CFG_CS3_SIZE 0x00100000 -#define CFG_CS3_CFG 0x00019800 - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_IDE_PREINIT 1 - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - -#define CONFIG_VIDEO_SMI_LYNXEM -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_LOGO - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CFG_ISA_IO CONFIG_PCI_IO_BUS - -/*---------------------------------------------------------------------*/ -/* Display addresses */ -/*---------------------------------------------------------------------*/ - -#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38) -#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30) - -#endif /* __CONFIG_H */ diff --git a/include/configs/hymod.h b/include/configs/hymod.h deleted file mode 100644 index 8cad98d..0000000 --- a/include/configs/hymod.h +++ /dev/null @@ -1,733 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Config header file for Hymod board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_HYMOD 1 /* ...on a Hymod board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ -#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */ - -#ifdef CONFIG_ETHER_ON_FCC - -#if (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK10 - * - Tx-CLK is CLK11 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ -# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ - -#elif (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ -# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ - -#elif (CONFIG_ETHER_INDEX == 3) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ -# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK) -#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK) -#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \ - else iop->pdat &= ~MDIO_DATA_PINMASK - -#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \ - else iop->pdat &= ~MDIO_CLCK_PINMASK - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - - -/* other options */ -#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */ -#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifdef DEBUG -#define CONFIG_8260_CLKIN 33333333 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#endif - -#if defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 115200 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -/* default ip addresses - these will be overridden */ -#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */ -#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */ - -#define CONFIG_LAST_STAGE_INIT - -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DOC | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_FPGA | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NAND | \ - CFG_CMD_MMC | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_PCI | \ - CFG_CMD_USB | \ - CFG_CMD_REISER | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_UNIVERSE| \ - CFG_CMD_VFD | \ - CFG_CMD_XIMG ) ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */ -#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */ -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press to stop\n" -#define CONFIG_AUTOBOOT_STOP_STR " " -#undef CONFIG_AUTOBOOT_DELAY_STR -#define DEBUG_BOOTKEYS 0 -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ -#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ -# if defined(CONFIG_KGDB_USE_EXTC) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -# else -#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ -# endif -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -/* - * Hymod specific configurable options - */ -#undef CFG_HYMOD_DBLEDS /* walk mezz board LEDs */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ - -#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0x7e - -/* these are for the ST M24C02 2kbit serial i2c eeprom */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CFG_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ - -#define CFG_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ - -/* - * standard dtt sensor configuration - bottom bit will determine local or - * remote sensor of the ADM1021, the rest determines index into - * CFG_DTT_ADM1021 array below. - * - * On HYMOD board, the remote sensor should be connected to the MPC8260 - * temperature diode thingy, but an errata said this didn't work and - * should be disabled - so it isn't connected. - */ -#if 0 -#define CONFIG_DTT_SENSORS { 0, 1 } -#else -#define CONFIG_DTT_SENSORS { 0 } -#endif - -/* - * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). - * there will be one entry in this array for each two (dummy) sensors in - * CONFIG_DTT_SENSORS. - * - * For HYMOD board: - * - only one ADM1021 - * - i2c addr 0x2a (both ADD0 and ADD1 are N/C) - * - conversion rate 0x02 = 0.25 conversions/second - * - ALERT ouput disabled - * - local temp sensor enabled, min set to 0 deg, max set to 85 deg - * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above) - */ -#define CFG_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CFG_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CFG_SIUMCR. - */ -#ifdef DEBUG -#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ - HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ - HRCW_MODCK_H0010) -#else -#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ - HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ - HRCW_MODCK_H0101) -#endif -/* no slaves so just duplicate the master hrcw */ -#define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER -#define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE TEXT_BASE -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_FPGA_BASE 0x80000000 -/* - * unfortunately, CFG_MONITOR_LEN must include the - * (very large i.e. 256kB) environment flash sector - */ -#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#ifdef DEBUG -#define CFG_HID0_FINAL 0 -#else -#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#endif -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#ifdef DEBUG -#define CFG_RMR 0 -#else -#define CFG_RMR RMR_CSRE -#endif - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ - SIUMCR_APPC10|SIUMCR_MMR11) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CFG_SCCR (SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now) - * 2 60x SDRAM 64 bit SDRAM - * 3 Local UPMC 8 bit Main Xilinx configuration - * 4 Local GPCM 32 bit Main Xilinx register mode - * 5 Local UPMB 32 bit Main Xilinx port mode - * 6 Local UPMC 8 bit Mezz Xilinx configuration - */ - -/* - * Bank 0 - FLASH - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The flash memory is two Intel StrataFlash chips, each configured for - * 16 bit operation and connected to give a 32 bit wide port." - * - * "The chip select logic is configured to respond to both *CS0 and *CS1. - * Therefore the FLASH memory will be mapped to both bank 0 and bank 1. - * It is suggested that bank 0 be read-only and bank 1 be read/write. The - * FLASH will then appear as ROM during boot." - * - * Initially, we are only going to use bank 0 in read/write mode. - */ - -/* 32 bit, read-write, GPCM on 60x bus */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE&BRx_BA_MSK)|\ - BRx_PS_32|BRx_MS_GPCM_P|BRx_V) -/* up to 32 Mb */ -#define CFG_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) - -/* - * Bank 2 - SDRAM - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a - * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous - * dynamic random access memory organised as 4 banks by 4096 rows by 512 - * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus." - * - * "The locations in SDRAM are accessed using multiplexed address pins to - * specify row and column. The pins also act to specify commands. The state - * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP - * pin may function as a row address or as the AUTO PRECHARGE control line, - * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260 - * address lines to be configured to the required multiplexing scheme." - */ - -#define CFG_SDRAM_SIZE 64 - -/* 64 bit, read-write, SDRAM on 60x bus */ -#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE&BRx_BA_MSK)|\ - BRx_PS_64|BRx_MS_SDRAM_P|BRx_V) -/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */ -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE)|\ - ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12) - -/* - * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows: - * - * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5 - * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16 - * as bank select, A7 is output on SDA10 during an ACTIVATE command, - * earliest timing for ACTIVATE command after REFRESH command is 6 clocks, - * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE - * command is 2 clocks, earliest timing for PRECHARGE after last data - * was read is 1 clock, earliest timing for PRECHARGE after last data - * was written is 1 clock, CAS Latency is 2. - */ - -#define CFG_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ - PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\ - PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\ - PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\ - PSDMR_WRC_1C|PSDMR_CL_2) - -/* - * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh - * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register - * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer - * Prescaler, hence the P instead of the R). The refresh timer period is given - * by (note that there was a change in the 8260 UM Errata): - * - * TimerPeriod = (PSRT + 1) / Fmptc - * - * where Fmptc is the BusClock divided by PTP. i.e. - * - * TimerPeriod = (PSRT + 1) / (BusClock / PTP) - * - * or - * - * TImerPeriod = (PTP * (PSRT + 1)) / BusClock - * - * The requirement for the Toshiba TC59SM716FTL-10 is that there must be - * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096 - * = 15.625 usecs. - * - * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32 - * appear to be reasonable. - */ - -#ifdef DEBUG -#define CFG_PSRT 39 -#define CFG_MPTPR MPTPR_PTP_DIV8 -#else -#define CFG_PSRT 31 -#define CFG_MPTPR MPTPR_PTP_DIV32 -#endif - -/* - * Banks 3,4,5 and 6 - FPGA access - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made - * for configuring an optional FPGA on the mezzanine interface. - * - * Access to the FPGAs may be divided into several catagories: - * - * 1. Configuration - * 2. Register mode access - * 3. Port mode access - * - * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be - * configured only (mode 1). Consequently there are four access types. - * - * To improve interface performance and simplify software design, the four - * possible access types are separately mapped to different memory banks. - * - * All are accessed using the local bus." - * - * Device Mode Memory Bank Machine Port Size Access - * - * Main Configuration 3 UPMC 8bit R/W - * Main Register 4 GPCM 32bit R/W - * Main Port 5 UPMB 32bit R/W - * Mezzanine Configuration 6 UPMC 8bit W/O - * - * "Note that mezzanine mode 1 access is write-only." - */ - -/* all the bank sizes must be a power of two, greater or equal to 32768 */ -#define FPGA_MAIN_CFG_BASE (CFG_FPGA_BASE) -#define FPGA_MAIN_CFG_SIZE 32768 -#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE) -#define FPGA_MAIN_REG_SIZE 32768 -#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE) -#define FPGA_MAIN_PORT_SIZE 32768 -#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE) -#define FPGA_MEZZ_CFG_SIZE 32768 - -/* 8 bit, read-write, UPMC */ -#define CFG_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) -/* up to 32Kbyte, burst inhibit */ -#define CFG_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) - -/* 32 bit, read-write, GPCM */ -#define CFG_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) -/* up to 32Kbyte */ -#define CFG_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) - -/* 32 bit, read-write, UPMB */ -#define CFG_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) -/* up to 32Kbyte */ -#define CFG_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) - -/* 8 bit, write-only, UPMC */ -#define CFG_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) -/* up to 32Kbyte, burst inhibit */ -#define CFG_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) - -/*----------------------------------------------------------------------- - * MBMR - Machine B Mode 10-27 - *----------------------------------------------------------------------- - */ -#define CFG_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ - -/*----------------------------------------------------------------------- - * MCMR - Machine C Mode 10-27 - *----------------------------------------------------------------------- - */ -#define CFG_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ - -/* - * FPGA I/O Port/Bit information - */ - -#define FPGA_MAIN_PROG_PORT IOPIN_PORTA -#define FPGA_MAIN_PROG_PIN 4 /* PA4 */ -#define FPGA_MAIN_INIT_PORT IOPIN_PORTA -#define FPGA_MAIN_INIT_PIN 5 /* PA5 */ -#define FPGA_MAIN_DONE_PORT IOPIN_PORTA -#define FPGA_MAIN_DONE_PIN 6 /* PA6 */ - -#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA -#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */ -#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA -#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */ -#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA -#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */ -#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA -#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */ - -/* - * FPGA Interrupt configuration - */ -#define FPGA_MAIN_IRQ SIU_INT_IRQ2 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/impa7.h b/include/configs/impa7.h deleted file mode 100644 index 8b841ff..0000000 --- a/include/configs/impa7.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the implementa impA7 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ -#define CONFIG_IMPA7 1 /* on an impA7 Board */ -#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#define CONFIG_ARM7_REVD 1 /* enable ARM720 REV.D Workarounds */ - -#undef CONFIG_USE_IRQ /* don't need them anymore */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x20000000 -#define CS8900_BUS32 1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" -/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5a */ -/*#define CONFIG_NETMASK 255.255.0.0 */ -/*#define CONFIG_IPADDR 172.22.2.128 */ -/*#define CONFIG_SERVERIP 172.22.2.126 */ -/*#define CONFIG_BOOTFILE "impa7" */ -#define CONFIG_BOOTCOMMAND "bootp;bootm" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "impA7 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xc1000000 /* default load address */ - -#define CFG_HZ 2000 /* decrementer freq: 2 kHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ -#define PHYS_SDRAM_2 0xc1000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x10000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 16 MB */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00020000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=impA7 NOR Flash Bank #0,nor1=impA7 NOR Flash Bank #1" -#define MTDPARTS_DEFAULT "mtdparts=impA7 NOR Flash Bank #0:-(FileSystem1);impA7 NOR Flash Bank #1:-(FileSystem2)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/incaip.h b/include/configs/incaip.h deleted file mode 100644 index 1c6216b..0000000 --- a/include/configs/incaip.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file contains the configuration parameters for the INCA-IP board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ -#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */ - -#ifndef CPU_CLOCK_RATE -/* allowed values: 100000000, 133000000, and 150000000 */ -#define CPU_CLOCK_RATE 150000000 /* default: 150 MHz clock for the MIPS core */ -#endif - -#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "ethaddr=${ethaddr} " \ - "panic=1\0" \ - "flash_nfs=run nfsargs addip addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 80500000 ${bootfile};" \ - "run nfsargs addip addmisc;bootm\0" \ - "rootpath=/opt/eldk/mips_4KC\0" \ - "bootfile=/tftpboot/INCA/uImage\0" \ - "kernel_addr=B0040000\0" \ - "ramdisk_addr=B0100000\0" \ - "u-boot=/tftpboot/INCA/u-boot.bin\0" \ - "load=tftp 80500000 ${u-boot}\0" \ - "update=protect off 1:0-2;era 1:0-2;" \ - "cp.b 80500000 B0000000 ${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_SNTP ) -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "INCA-IP # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args*/ - -#define CFG_MALLOC_LEN 128*1024 - -#define CFG_BOOTPARAMS_LEN 128*1024 - -#define CFG_HZ (incaip_get_cpuclk() / 2) - -#define CFG_SDRAM_BASE 0x80000000 - -#define CFG_LOAD_ADDR 0x80100000 /* default load address */ - -#define CFG_MEMTEST_START 0x80100000 -#define CFG_MEMTEST_END 0x80800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xb0800000 /* Flash Bank #2 */ - -/* The following #defines are needed to get flash environment right */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) - -#define CFG_INIT_SP_OFFSET 0x400000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR 0xB0030000 -#define CFG_ENV_SIZE 0x10000 - -#define CONFIG_FLASH_16BIT - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_INCA_IP_SWITCH -#define CONFIG_NET_MULTI -#define CONFIG_INCA_IP_SWITCH_AMDIX - -/* - * JFFS2 partitions - */ -/* No command line, one static partition, use all space on the device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=INCA-IP Bank 0" -#define MTDPARTS_DEFAULT "mtdparts=INCA-IP Bank 0:192k(uboot)," \ - "64k(env)," \ - "768k(linux)," \ - "1m@3m(rootfs)," \ - "768k(linux2)," \ - "3m@5m(rootfs2)" -*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 4096 -#define CFG_ICACHE_SIZE 4096 -#define CFG_CACHELINE_SIZE 16 - -#endif /* __CONFIG_H */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h deleted file mode 100644 index c0cc4f1..0000000 --- a/include/configs/inka4x0.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_INKA4X0 1 /* INKA4x0 board */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CFG_XLB_PIPELINING 1 - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP | \ - CFG_CMD_USB ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (TEXT_BASE == 0xFFE00000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE 0xFFE00000 - -#define CFG_FLASH_SIZE 0x00200000 /* 2 MByte */ -#define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */ - -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) /* second sector */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -#define CONFIG_MPC5200_DDR - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use CS1 as gpio_wkup_6 output - * Bit 0 (mask: 0x80000000): 0 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, I2C1 is used for onboard EEPROM - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard - * EEPROM - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000): - * 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible. - */ -#define CFG_GPS_PORT_CONFIG 0x01001004 - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CFG_ALT_MEMTEST - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */ -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -/* 32Mbit SRAM @0x30000000 */ -#define CFG_CS1_START 0x30000000 -#define CFG_CS1_SIZE 0x00400000 -#define CFG_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */ - -/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ -#define CFG_CS2_START 0x80000000 -#define CFG_CS2_SIZE 0x0001000 -#define CFG_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */ - -/* GPIO in @0x30400000 */ -#define CFG_CS3_START 0x30400000 -#define CFG_CS3_SIZE 0x00100000 -#define CFG_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */ - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_CLOCK 0x00015555 -#define CONFIG_USB_CONFIG 0x00001000 -#define CONFIG_USB_STORAGE - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA -#define CFG_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */ -#define CFG_ATA_STRIDE 4 /* Interval between registers */ - -#define CONFIG_ATAPI 1 - -#define CFG_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h deleted file mode 100644 index 3cb9ebc..0000000 --- a/include/configs/innokom.h +++ /dev/null @@ -1,468 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. - * - * Configuration for the Auerswald Innokom CPU board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * include/configs/innokom.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - /* for timer/console/ethernet */ -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 19200 -#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ - -#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE) -/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ -#define CONFIG_BOOTARGS "console=ttyS0,19200" -#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.1.56 -#define CONFIG_SERVERIP 192.168.1.2 -#define CONFIG_BOOTCOMMAND "bootm 0x40000" -#define CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_CMDLINE_TAG 1 - -/* - * Miscellaneous configurable options - */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (256*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xa3000000 /* load kernel to this address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ - /* RS: the oscillator is actually 3680130?? */ - -#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ - /* 0101000001 */ - /* ^^^^^ Memory Speed 99.53 MHz */ - /* ^^ Run Mode Speed = 2x Mem Speed */ - /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ - -#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * I2C bus - */ -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xfe - -#define CFG_ENV_IS_IN_EEPROM 1 - -#define CFG_ENV_OFFSET 0x00 /* environment starts here */ -#define CFG_ENV_SIZE 1024 /* 1 KiB */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */ -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */ -#define CFG_EEPROM_SIZE 4096 /* size in bytes */ -#define CFG_I2C_INIT_BOARD 1 /* board has it's own init */ - -/* - * SMSC91C111 Network Card - */ -#define CONFIG_DRIVER_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */ -#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ -#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ -#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */ -#undef CONFIG_SHOW_ACTIVITY -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ - -#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */ -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * JFFS2 partitions - * - */ -/* development flash */ -#define CONFIG_MTD_INNOKOM_16MB 1 -#undef CONFIG_MTD_INNOKOM_64MB - -/* production flash */ -/* -#define CONFIG_MTD_INNOKOM_64MB 1 -#undef CONFIG_MTD_INNOKOM_16MB -*/ - -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=innokom-0" -*/ - -/* development flash */ -/* -#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)" -*/ - -/* production flash */ -/* -#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)" -*/ - -/* - * GPIO settings - * - * GP15 == nCS1 is 1 - * GP24 == SFRM is 1 - * GP25 == TXD is 1 - * GP33 == nCS5 is 1 - * GP39 == FFTXD is 1 - * GP41 == RTS is 1 - * GP47 == TXD is 1 - * GP49 == nPWE is 1 - * GP62 == LED_B is 1 - * GP63 == TDM_OE is 1 - * GP78 == nCS2 is 1 - * GP79 == nCS3 is 1 - * GP80 == nCS4 is 1 - */ -#define CFG_GPSR0_VAL 0x03008000 -#define CFG_GPSR1_VAL 0xC0028282 -#define CFG_GPSR2_VAL 0x0001C000 - -/* GP02 == DON_RST is 0 - * GP23 == SCLK is 0 - * GP45 == USB_ACT is 0 - * GP60 == PLLEN is 0 - * GP61 == LED_A is 0 - * GP73 == SWUPD_LED is 0 - */ -#define CFG_GPCR0_VAL 0x00800004 -#define CFG_GPCR1_VAL 0x30002000 -#define CFG_GPCR2_VAL 0x00000100 - -/* GP00 == DON_READY is input - * GP01 == DON_OK is input - * GP02 == DON_RST is output - * GP03 == RESET_IND is input - * GP07 == RES11 is input - * GP09 == RES12 is input - * GP11 == SWUPDATE is input - * GP14 == nPOWEROK is input - * GP15 == nCS1 is output - * GP17 == RES22 is input - * GP18 == RDY is input - * GP23 == SCLK is output - * GP24 == SFRM is output - * GP25 == TXD is output - * GP26 == RXD is input - * GP32 == RES21 is input - * GP33 == nCS5 is output - * GP34 == FFRXD is input - * GP35 == CTS is input - * GP39 == FFTXD is output - * GP41 == RTS is output - * GP42 == USB_OK is input - * GP45 == USB_ACT is output - * GP46 == RXD is input - * GP47 == TXD is output - * GP49 == nPWE is output - * GP58 == nCPUBUSINT is input - * GP59 == LANINT is input - * GP60 == PLLEN is output - * GP61 == LED_A is output - * GP62 == LED_B is output - * GP63 == TDM_OE is output - * GP64 == nDSPINT is input - * GP65 == STRAP0 is input - * GP67 == STRAP1 is input - * GP69 == STRAP2 is input - * GP70 == STRAP3 is input - * GP71 == STRAP4 is input - * GP73 == SWUPD_LED is output - * GP78 == nCS2 is output - * GP79 == nCS3 is output - * GP80 == nCS4 is output - */ -#define CFG_GPDR0_VAL 0x03808004 -#define CFG_GPDR1_VAL 0xF002A282 -#define CFG_GPDR2_VAL 0x0001C200 - -/* GP15 == nCS1 is AF10 - * GP18 == RDY is AF01 - * GP23 == SCLK is AF10 - * GP24 == SFRM is AF10 - * GP25 == TXD is AF10 - * GP26 == RXD is AF01 - * GP33 == nCS5 is AF10 - * GP34 == FFRXD is AF01 - * GP35 == CTS is AF01 - * GP39 == FFTXD is AF10 - * GP41 == RTS is AF10 - * GP46 == RXD is AF10 - * GP47 == TXD is AF01 - * GP49 == nPWE is AF10 - * GP78 == nCS2 is AF10 - * GP79 == nCS3 is AF10 - * GP80 == nCS4 is AF10 - */ -#define CFG_GAFR0_L_VAL 0x80000000 -#define CFG_GAFR0_U_VAL 0x001A8010 -#define CFG_GAFR1_L_VAL 0x60088058 -#define CFG_GAFR1_U_VAL 0x00000008 -#define CFG_GAFR2_L_VAL 0xA0000000 -#define CFG_GAFR2_U_VAL 0x00000002 - - -/* FIXME: set GPIO_RER/FER */ - -/* RDH = 1 - * PH = 1 - * VFS = 1 - * BFS = 1 - * SSS = 1 - */ -#define CFG_PSSR_VAL 0x37 - -/* - * Memory settings - * - * This is the configuration for nCS0/1 -> flash banks - * configuration for nCS1: - * [31] 0 - Slower Device - * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns - * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns - * [19] 1 - 16 Bit bus width - * [18:16] 000 - nonburst RAM or FLASH - * configuration for nCS0: - * [15] 0 - Slower Device - * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns - * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns - * [03] 1 - 16 Bit bus width - * [02:00] 000 - nonburst RAM or FLASH - */ -#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */ - -/* This is the configuration for nCS2/3 -> TDM-Switch, DSP - * configuration for nCS3: DSP - * [31] 0 - Slower Device - * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns - * [19] 1 - 16 Bit bus width - * [18:16] 100 - variable latency I/O - * configuration for nCS2: TDM-Switch - * [15] 0 - Slower Device - * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns - * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns - * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns - * [03] 1 - 16 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */ - -/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller - * - * configuration for nCS5: LAN Controller - * [31] 0 - Slower Device - * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns - * [19] 1 - 16 Bit bus width - * [18:16] 100 - variable latency I/O - * configuration for nCS4: ExtBus - * [15] 0 - Slower Device - * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns - * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns - * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns - * [03] 1 - 16 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ - -/* MDCNFG: SDRAM Configuration Register - * - * [31:29] 000 - reserved - * [28] 0 - no SA1111 compatiblity mode - * [27] 0 - latch return data with return clock - * [26] 0 - alternate addressing for pair 2/3 - * [25:24] 00 - timings - * [23] 0 - internal banks in lower partition 2/3 (not used) - * [22:21] 00 - row address bits for partition 2/3 (not used) - * [20:19] 00 - column address bits for partition 2/3 (not used) - * [18] 0 - SDRAM partition 2/3 width is 32 bit - * [17] 0 - SDRAM partition 3 disabled - * [16] 0 - SDRAM partition 2 disabled - * [15:13] 000 - reserved - * [12] 1 - SA1111 compatiblity mode - * [11] 1 - latch return data with return clock - * [10] 0 - no alternate addressing for pair 0/1 - * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk - * [7] 1 - 4 internal banks in lower partition pair - * [06:05] 10 - 13 row address bits for partition 0/1 - * [04:03] 01 - 9 column address bits for partition 0/1 - * [02] 0 - SDRAM partition 0/1 width is 32 bit - * [01] 0 - disable SDRAM partition 1 - * [00] 1 - enable SDRAM partition 0 - */ -/* use the configuration above but disable partition 0 */ -#define CFG_MDCNFG_VAL 0x000019c8 - -/* MDREFR: SDRAM Refresh Control Register - * - * [32:26] 0 - reserved - * [25] 0 - K2FREE: not free running - * [24] 0 - K1FREE: not free running - * [23] 1 - K0FREE: not free running - * [22] 0 - SLFRSH: self refresh disabled - * [21] 0 - reserved - * [20] 0 - APD: no auto power down - * [19] 0 - K2DB2: SDCLK2 is MemClk - * [18] 0 - K2RUN: disable SDCLK2 - * [17] 0 - K1DB2: SDCLK1 is MemClk - * [16] 1 - K1RUN: enable SDCLK1 - * [15] 1 - E1PIN: SDRAM clock enable - * [14] 1 - K0DB2: SDCLK0 is MemClk - * [13] 0 - K0RUN: disable SDCLK0 - * [12] 1 - E0PIN: disable SDCKE0 - * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 - */ -#define CFG_MDREFR_VAL 0x0081D018 - -/* MDMRS: Mode Register Set Configuration Register - * - * [31] 0 - reserved - * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) - * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) - * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) - * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) - * [15] 0 - reserved - * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. - * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. - * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. - * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. - */ -#define CFG_MDMRS_VAL 0x00020022 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00000000 -#define CFG_MCMEM1_VAL 0x00000000 -#define CFG_MCATT0_VAL 0x00000000 -#define CFG_MCATT1_VAL 0x00000000 -#define CFG_MCIO0_VAL 0x00000000 -#define CFG_MCIO1_VAL 0x00000000 - -/* -#define CSB226_USER_LED0 0x00000008 -#define CSB226_USER_LED1 0x00000010 -#define CSB226_USER_LED2 0x00000020 -*/ - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h deleted file mode 100644 index 2f6e399..0000000 --- a/include/configs/integratorap.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta - * Configuation settings for the TI OMAP Innovator board. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * Configuration for Integrator AP board. - *. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CFG_MEMTEST_START 0x100000 -#define CFG_MEMTEST_END 0x10000000 -#define CFG_HZ 1000 -#define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ -#define CFG_TIMERBASE 0x13000100 /* Timer1 */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ - -#undef CONFIG_INIT_CRITICAL -#define CONFIG_CM_INIT 1 -#define CONFIG_CM_REMAP 1 -#undef CONFIG_CM_SPD_DETECT - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * PL010 Configuration - */ -#define CFG_PL010_SERIAL -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 38400 -#define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) } -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_SERIAL0 0x16000000 -#define CFG_SERIAL1 0x17000000 - -/*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */ -/*#define CONFIG_NET_MULTI */ -/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ - -#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" -#define CONFIG_BOOTCOMMAND "" - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CFG_FLASH_BASE 0x24000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_ENV_IS_NOWHERE -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#define CFG_MAX_FLASH_SECT 128 -#define CFG_ENV_SIZE 32768 - -#define PHYS_FLASH_1 (CFG_FLASH_BASE) - -/*----------------------------------------------------------------------- - * PCI definitions - */ - -/*#define CONFIG_PCI /--* include pci support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define DEBUG - -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - - -#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 -#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 - -/* PCI Base area */ -#define INTEGRATOR_PCI_BASE 0x40000000 -#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF - -/* memory map as seen by the CPU on the local bus */ -#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ -#define CPU_PCI_IO_SIZE 0x10000 - -#define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */ -#define CPU_PCI_CNFG_SIZE 0x1000000 - -#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ -/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */ -#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ -/* unused (128-16)M from B1000000-B7FFFFFF */ -#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ -/* unused ((128-16)M - 64K) from XXX */ - -#define PCI_V3_BASE 0x62000000 - -/* V3 PCI bridge controller */ -#define V3_BASE 0x62000000 /* V360EPC registers */ - -#define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS) -#define PCI_ENET0_MEMADDR (PCI_MEM_BASE) - - -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CF 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC - -/* SYSTEM register bits */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) - -/* PCI_CFG bits */ -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) - -/* PCI MAP register bits (PCI -> Local bus) */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) -#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) - -/* 9 => 512M window size */ -#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 - -/* A => 1024M window size */ -#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 - -/* LB_BASE register bits (Local bus -> PCI) */ -#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 -#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) -#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 -#define V3_LB_BASE_M_PREFETCH (1 << 3) -#define V3_LB_BASE_M_ENABLE (1 << 0) - -/* PCI COMMAND REGISTER bits */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) - -#define INTEGRATOR_SC_BASE 0x11000000 -#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 -#define INTEGRATOR_SC_PCIENABLE \ - (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) - -/*----------------------------------------------------------------------- - * There are various dependencies on the core module (CM) fitted - * Users should refer to their CM user guide - * - when porting adjust u-boot/Makefile accordingly - * to define the necessary CONFIG_ s for the CM involved - * see e.g. integratorcp_CM926EJ-S_config - */ -#include "armcoremodule.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h deleted file mode 100644 index 4189f9c..0000000 --- a/include/configs/integratorcp.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta - * Configuation settings for the TI OMAP Innovator board. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * Configuration for Compact Integrator board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CFG_MEMTEST_START 0x100000 -#define CFG_MEMTEST_END 0x10000000 -#define CFG_HZ 1000 -#define CFG_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ -#define CFG_TIMERBASE 0x13000100 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC91111_BASE 0xC8000000 -#undef CONFIG_SMC91111_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CFG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 14745600 -#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 38400 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_SERIAL0 0x16000000 -#define CFG_SERIAL1 0x17000000 - -/* -#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_PCI) -*/ -#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | \ - CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV \ - ) - -/* #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#if 0 -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/nfs nfsroot=:/ mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" -#define CONFIG_BOOTCOMMAND "bootp ; bootm" -#endif -/* The kernel command line & boot command below are for a platform flashed with afu.axf - -Image 666 Block 0 End Block 0 address 0x24000000 exec 0x24000000- name u-boot -Image 667 Block 1 End Block 13 address 0x24040000 exec 0x24040000- name u-linux -Image 668 Block 14 End Block 33 address 0x24380000 exec 0x24380000- name rootfs -SIB at Block62 End Block62 address 0x24f80000 - -*/ -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0 console=ttyAMA0" -#define CONFIG_BOOTCOMMAND "cp 0x24080000 0x7fc0 0x100000; bootm" - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/ -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size*/ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - - * Top varies according to amount fitted - * Reserve top 4 blocks of flash - * - ARM Boot Monitor - * - Unused - * - SIB block - * - U-Boot environment - * - * Base is always 0x24000000 - - */ -#define CFG_FLASH_BASE 0x24000000 -#define CFG_MAX_FLASH_SECT 64 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_MONITOR_LEN 0x00100000 -#define CFG_ENV_IS_IN_FLASH (1) - -/* - * Move up the U-Boot & monitor area if more flash is fitted. - * If this U-Boot is to be run on Integrators with varying flash sizes, - * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG - * register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE - * - CFG_MONITOR_BASE is set to indicate that the environment is not - * embedded in the boot monitor(s) area - */ -#if ( PHYS_FLASH_SIZE == 0x04000000 ) - -#define CFG_ENV_ADDR 0x27F00000 -#define CFG_MONITOR_BASE 0x27F40000 - -#elif (PHYS_FLASH_SIZE == 0x02000000 ) - -#define CFG_ENV_ADDR 0x25F00000 -#define CFG_MONITOR_BASE 0x25F40000 - -#else - -#define CFG_ENV_ADDR 0x24F00000 -#define CFG_MONITOR_BASE 0x27F40000 - -#endif - -#define CFG_ENV_SECT_SIZE 0x40000 /* 256KB */ -#define CFG_ENV_SIZE 8192 /* 8KB */ -/*----------------------------------------------------------------------- - * CP control registers - */ -#define CPCR_BASE 0xCB000000 /* CP Registers*/ -#define OS_FLASHPROG 0x00000004 /* Flash register*/ -#define CPMASK_EXTRABANK 0x8 -#define CPMASK_FLASHSIZE 0x4 -#define CPMASK_FLWREN 0x2 -#define CPMASK_FLVPPEN 0x1 - -/* - * The ARM boot monitor initializes the board. - * However, the default U-Boot code also performs the initialization. - * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT - * - see documentation supplied with board for details of how to choose the - * image to run at reset/power up - * e.g. whether the ARM Boot Monitor runs before U-Boot - -#define CONFIG_SKIP_LOWLEVEL_INIT - - */ - -/* - * The ARM boot monitor does not relocate U-Boot. - * However, the default U-Boot code performs the relocation check, - * and may relocate the code if the memory map is changed. - * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT - -#define SKIP_CONFIG_RELOCATE_UBOOT - - */ -/*----------------------------------------------------------------------- - * There are various dependencies on the core module (CM) fitted - * Users should refer to their CM user guide - * - when porting adjust u-boot/Makefile accordingly - * to define the necessary CONFIG_ s for the CM involved - * see e.g. cp_926ejs_config - */ - -#include "armcoremodule.h" - -/* - * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & - * the core module has a CM_INIT register - * then the U-Boot initialisation code will - * e.g. ARM Boot Monitor or pre-loader is repeated once - * (to re-initialise any existing CM_INIT settings to safe values). - * - * This is usually not the desired behaviour since the platform - * will either reboot into the ARM monitor (or pre-loader) - * or continuously cycle thru it without U-Boot running, - * depending upon the setting of Integrator/CP switch S2-4. - * - * However it may be needed if Integrator/CP switch S2-1 - * is set OFF to boot direct into U-Boot. - * In that case comment out the line below. -#undef CONFIG_CM_INIT - */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h deleted file mode 100644 index b0a80a3..0000000 --- a/include/configs/ixdp425.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (C) Copyright 2003 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * Configuation settings for the IXDP425 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ -#define CONFIG_IXDP425 1 /* on an IXDP425 Board */ - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_PCI) - -#define CONFIG_PCI -#define CONFIG_NET_MULTI -#define CONFIG_EEPRO100 -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -/* These are u-boot generic parameters */ -#include - -#define CONFIG_BOOTDELAY 3 -/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.148 -#define CONFIG_BOOTCOMMAND "bootm 50040000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" -#define CONFIG_CMDLINE_TAG - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x00010000 /* default load address */ - -#define CFG_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */ - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*************************************************************** - * Platform/Board specific defines start here. - ***************************************************************/ - -/* - * Hardware drivers - */ - - -/* - * select serial console configuration - */ -#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ - -#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ -#define PHYS_FLASH_BANK_SIZE 0x00800000 /* 8 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ - -#define CFG_DRAM_BASE 0x00000000 -#define CFG_DRAM_SIZE 0x01000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * Expansion bus settings - */ -#define CFG_EXP_CS0 0xbcd23c42 - -/* - * SDRAM settings - */ -#define CFG_SDR_CONFIG 0xd -#define CFG_SDR_MODE_CONFIG 0x1 -#define CFG_SDRAM_REFRESH_CNT 0x81a - -/* - * GPIO settings - */ - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - -/* FIXME */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h deleted file mode 100644 index 6590f6f..0000000 --- a/include/configs/kb9202.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Rick Bronson - * - * Configuation settings for the AT91RM9200DK board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Adatped for KwikByte KB920x board from at91rm9200dk.h: 22APR2005 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */ -#define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -/* Only define one of the following, based on board type */ -/* #define CONFIG_KB9200 1 KwikByte KB9202 board */ -/* #define CONFIG_KB9201 1 KwikByte KB9202 board */ -#define CONFIG_KB9202 1 /* KwikByte KB9202 board */ - -#define CONFIG_KB920x 1 /* Any KB920x board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CFG_LONGHELP - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CONFIG_BAUDRATE 115200 - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_I2C | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP ) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC)) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ - -#define CFG_MEMTEST_START PHYS_SDRAM -#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024) - -#define CONFIG_DRIVER_ETHER -#define CONFIG_NET_RETRY_COUNT 20 - -#define CFG_FLASH_BASE 0x10000000 - -#ifdef CONFIG_KB9202 -#define PHYS_FLASH_SIZE 0x1000000 -#else -#define PHYS_FLASH_SIZE 0x200000 -#endif - -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 256 - -#define CONFIG_HARD_I2C - -#define CFG_ENV_IS_IN_EEPROM - -#ifdef CONFIG_KB9202 -#define CFG_ENV_OFFSET 0x3E00 -#define CFG_ENV_SIZE 0x0200 -#else -#define CFG_ENV_OFFSET 0x1000 -#define CFG_ENV_SIZE 0x1000 -#endif -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_EEPROM_PAGE_WRITE_BITS 6 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0 /* not used */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CFG_LOAD_ADDR 0x21000000 /* default load address */ - -#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } - -#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI - -#ifndef __ASSEMBLY__ -/*----------------------------------------------------------------------- - * Board specific extension for bd_info - * - * This structure is embedded in the global bd_info (bd_t) structure - * and can be used by the board specific code (eg board/...) - */ - -struct bd_info_ext { - /* helper variable for board environment handling - * - * env_crc_valid == 0 => uninitialised - * env_crc_valid > 0 => environment crc in flash is valid - * env_crc_valid < 0 => environment crc in flash is invalid - */ - int env_crc_valid; -}; -#endif - -#define CFG_HZ 1000 -#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#endif diff --git a/include/configs/lart.h b/include/configs/lart.h deleted file mode 100644 index a00640b..0000000 --- a/include/configs/lart.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the LART board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SA1100 1 /* This is an SA1100 CPU */ -#define CONFIG_LART 1 /* on an LART Board */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x20008300 -#define CS8900_BUS16 1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL3 1 /* we use SERIAL 3 on LART */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 172.22.2.131 -#define CONFIG_SERVERIP 172.22.2.126 -#define CONFIG_BOOTFILE "elinos-lart" -#define CONFIG_BOOTCOMMAND "tftp; bootm" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "LART # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xc8000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x0b /* set core clock to 220 MHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ -#define PHYS_SDRAM_2 0xc1000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */ -#define PHYS_SDRAM_3 0xc8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00800000 /* 8 MB */ -#define PHYS_SDRAM_4 0xc9000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00800000 /* 8 MB */ - - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (31+8) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/logodl.h b/include/configs/logodl.h deleted file mode 100644 index 715ed74..0000000 --- a/include/configs/logodl.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * (C) Copyright 2003 - * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. - * - * Configuration for the Logotronic DL board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * include/configs/logodl.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - /* for timer/console/ethernet */ -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 19200 -#undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */ - -#define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO) -/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ -#define CONFIG_BOOTARGS "console=ttyS0,19200" -#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.1.56 -#define CONFIG_SERVERIP 192.168.1.2 -#define CONFIG_BOOTCOMMAND "bootm 0x40000" -#define CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_CMDLINE_TAG 1 - -/* - * Miscellaneous configurable options - */ - -/* - * Size of malloc() pool; this lives below the uppermost 128 KiB which are - * used for the RAM copy of the uboot code - * - */ -#define CFG_MALLOC_LEN (256*1024) - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x08000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0800ffff /* 64 KiB */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x08000000 /* load kernel to this address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ - /* RS: the oscillator is actually 3680130?? */ - -#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ - /* 0101000001 */ - /* ^^^^^ Memory Speed 99.53 MHz */ - /* ^^ Run Mode Speed = 2x Mem Speed */ - /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ - -#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * SMSC91C111 Network Card - */ -#if 0 -#define CONFIG_DRIVER_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */ -#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ -#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ -#undef CONFIG_SHOW_ACTIVITY -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ -#endif - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of RAM */ -#define PHYS_SDRAM_1 0x08000000 /* SRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE (4*1024*1024) /* 4 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE (32*1024*1024) /* 32 MB */ - -#define CFG_DRAM_BASE PHYS_SDRAM_1 /* RAM starts here */ -#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE - -#define CFG_FLASH_BASE PHYS_FLASH_1 - - -/* - * GPIO settings - * - * GP?? == FOOBAR is 0/1 - */ - -#define _BIT0 0x00000001 -#define _BIT1 0x00000002 -#define _BIT2 0x00000004 -#define _BIT3 0x00000008 - -#define _BIT4 0x00000010 -#define _BIT5 0x00000020 -#define _BIT6 0x00000040 -#define _BIT7 0x00000080 - -#define _BIT8 0x00000100 -#define _BIT9 0x00000200 -#define _BIT10 0x00000400 -#define _BIT11 0x00000800 - -#define _BIT12 0x00001000 -#define _BIT13 0x00002000 -#define _BIT14 0x00004000 -#define _BIT15 0x00008000 - -#define _BIT16 0x00010000 -#define _BIT17 0x00020000 -#define _BIT18 0x00040000 -#define _BIT19 0x00080000 - -#define _BIT20 0x00100000 -#define _BIT21 0x00200000 -#define _BIT22 0x00400000 -#define _BIT23 0x00800000 - -#define _BIT24 0x01000000 -#define _BIT25 0x02000000 -#define _BIT26 0x04000000 -#define _BIT27 0x08000000 - -#define _BIT28 0x10000000 -#define _BIT29 0x20000000 -#define _BIT30 0x40000000 -#define _BIT31 0x80000000 - - -#define CFG_LED_A_BIT (_BIT18) -#define CFG_LED_A_SR GPSR0 -#define CFG_LED_A_CR GPCR0 - -#define CFG_LED_B_BIT (_BIT16) -#define CFG_LED_B_SR GPSR1 -#define CFG_LED_B_CR GPCR1 - - -/* LED A: off, LED B: off */ -#define CFG_GPSR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18) -#define CFG_GPSR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13) -#define CFG_GPSR2_VAL (_BIT14+_BIT15+_BIT16) - -#define CFG_GPCR0_VAL 0x00000000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 - -#define CFG_GPDR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18) -#define CFG_GPDR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13) -#define CFG_GPDR2_VAL (_BIT14+_BIT15+_BIT16) - -#define CFG_GAFR0_L_VAL (_BIT22+_BIT24+_BIT31) -#define CFG_GAFR0_U_VAL (_BIT15+_BIT17+_BIT19+\ - _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31) -#define CFG_GAFR1_L_VAL (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\ - _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31) -#define CFG_GAFR1_U_VAL (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31) -#define CFG_GAFR2_L_VAL (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\ - _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31) -#define CFG_GAFR2_U_VAL (_BIT1) - -#define CFG_PSSR_VAL (0x20) - -/* - * Memory settings - */ -#define CFG_MSC0_VAL 0x123c2980 -#define CFG_MSC1_VAL 0x123c2661 -#define CFG_MSC2_VAL 0x7ff87ff8 - - -/* no sdram/pcmcia here */ -#define CFG_MDCNFG_VAL 0x00000000 -#define CFG_MDREFR_VAL 0x00000000 -#define CFG_MDREFR_VAL_100 0x00000000 -#define CFG_MDMRS_VAL 0x00000000 - -/* only SRAM */ -#define SXCNFG_SETTINGS 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ - -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 - - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -/* FIXME */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/lpd7a400-10.h b/include/configs/lpd7a400-10.h deleted file mode 100644 index 3722fd2..0000000 --- a/include/configs/lpd7a400-10.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Logic LH7A400-10 card engine - */ - -#ifndef __LPD7A400_10_H -#define __LPD7A400_10_H - - -#define CONFIG_ARM920T 1 /* arm920t core */ -#define CONFIG_LH7A40X 1 /* Sharp LH7A40x SoC family */ -#define CONFIG_LH7A400 1 /* Sharp LH7A400 S0C */ - -/* The system clock PLL input frequency */ -#define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */ - -/* ticks per second */ -#define CFG_HZ (508469) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ - -/*---------------------------------------------------------------------- - * Using SMC91C111 LAN chip - * - * Default IO base of chip is 0x300, Card Engine has this address lines - * (LAN chip) tied to Vcc, so we just care about the chip select - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE (0x70000000) -#undef CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC_USE_IOFUNCS - -#endif /* __LPD7A400_10_H */ diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h deleted file mode 100644 index d7d0460..0000000 --- a/include/configs/lpd7a400.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __LPD7A400_H_ -#define __LPD7A400_H_ - -#define CONFIG_LPD7A400 /* Logic LH7A400 SDK */ - -#undef CONFIG_USE_IRQ - -/* - * This board uses the logic LH7A400-10 card engine - */ -#include - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * select serial console configuration - */ -#define CONFIG_CONSOLE_UART2 /* UART2 LH7A40x for console */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_IPADDR 192.168.1.100 -#define CONFIG_NETMASK 255.255.1.0 -#define CONFIG_SERVERIP 192.168.1.1 - -#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - -#ifndef USE_920T_MMU -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE)) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE) -#endif - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "LPD7A400> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0500000 /* 2 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xc0f00000 /* default load address */ - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* size and location of u-boot in flash */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256<<10) - -#define CFG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0xFC0000) -#define CFG_ENV_SIZE 0x40000 - -#endif /* __LPD7A400_H_ */ diff --git a/include/configs/lpd7a404-10.h b/include/configs/lpd7a404-10.h deleted file mode 100644 index a8af950..0000000 --- a/include/configs/lpd7a404-10.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Logic LH7A400-10 card engine - */ - -#ifndef __LPD7A404_10_H -#define __LPD7A404_10_H - - -#define CONFIG_ARM920T 1 /* arm920t core */ -#define CONFIG_LH7A40X 1 /* Sharp LH7A40x SoC family */ -#define CONFIG_LH7A404 1 /* Sharp LH7A404 SoC */ - -/* The system clock PLL input frequency */ -#define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */ - -/* ticks per second */ -#define CFG_HZ (508469) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ - -/*---------------------------------------------------------------------- - * Using SMC91C111 LAN chip - * - * Default IO base of chip is 0x300, Card Engine has this address lines - * (LAN chip) tied to Vcc, so we just care about the chip select - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE (0x70000000) -#undef CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC_USE_IOFUNCS - -#endif /* __LPD7A404_10_H */ diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h deleted file mode 100644 index 4002e68..0000000 --- a/include/configs/lpd7a404.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __LPD7A404_H_ -#define __LPD7A404_H_ - -#define CONFIG_LPD7A404 /* Logic LH7A400 SDK */ - -#undef CONFIG_USE_IRQ - -/* - * This board uses the logic LH7A404-10 card engine - */ -#include - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * select serial console configuration - */ -#define CONFIG_CONSOLE_UART2 /* UART2 LH7A40x for console */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_IPADDR 192.168.1.100 -#define CONFIG_NETMASK 255.255.1.0 -#define CONFIG_SERVERIP 192.168.1.1 - -#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - -#ifndef USE_920T_MMU -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE)) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE) -#endif - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "LPD7A404> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0500000 /* 2 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xc0f00000 /* default load address */ - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* size and location of u-boot in flash */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256<<10) - -#define CFG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0xFC0000) -#define CFG_ENV_SIZE 0x40000 - -#endif /* __LPD7A404_H_ */ diff --git a/include/configs/luan.h b/include/configs/luan.h deleted file mode 100644 index 0335a00..0000000 --- a/include/configs/luan.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * John Otken, jotken@softadvances.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * luan.h - configuration for LUAN board - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_LUAN 1 /* Board is Luan */ -#define CONFIG_440SP 1 /* Specific PPC440SP support */ -#define CONFIG_4xx 1 /* PPC4xx family */ -#define CONFIG_440 1 -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) -#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */ - -#define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ -#define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ -#define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ -#define CFG_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */ - -#define CFG_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */ - -#define CFG_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */ - -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ - -#if CFG_LARGE_FLASH == 0xffc00000 -#define CFG_FLASH_BASE CFG_LARGE_FLASH -#else -#define CFG_FLASH_BASE CFG_SMALL_FLASH -#endif - -#undef CFG_DRAM_TEST -#if CFG_SRAM_BASE -#define CFG_KBYTES_SDRAM 1024*2 -#else -#define CFG_KBYTES_SDRAM 1024 -#endif - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in SDRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE -#define CFG_INIT_RAM_END (8 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#undef CONFIG_SERIAL_MULTI -#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */ - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or EEPROM). - * Note: DENX encourages to use redundant environment in FLASH. - */ -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_FLASH_ADDR0 0x555 -#define CFG_FLASH_ADDR1 0x2aa -#define CFG_FLASH_WORD_SIZE unsigned char - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */ -#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */ -#define IIC0_DIMM0_ADDR 0x52 -#define IIC0_DIMM1_ADDR 0x53 - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=luan\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/luan/uImage\0" \ - "kernel_addr=fc000000\0" \ - "ramdisk_addr=fc100000\0" \ - "load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 -#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -#ifdef DEBUG -#define CONFIG_PANIC_HANG -#else -#define CONFIG_HW_WATCHDOG /* watchdog */ -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_CACHE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SETGETDCR | \ - CFG_CMD_SDRAM | \ - 0) - -/* this must be included AFTER the definition of CONFIG_COMMANDS */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#undef CONFIG_LYNXKDI /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#if (CONFIG_COMMANDS & CFG_CMD_PCI) - -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT -#undef CFG_PCI_MASTER_INIT - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */ - -#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h deleted file mode 100644 index ad1035b..0000000 --- a/include/configs/lubbock.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the LUBBOCK board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ -#define CONFIG_LCD 1 -#ifdef CONFIG_LCD -#define CONFIG_SHARP_LM8V31 -#endif -#define CONFIG_MMC 1 -#define BOARD_LATE_INIT 1 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x0C000000 - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "bootm 80000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" -#define CONFIG_CMDLINE_TAG -#define CONFIG_TIMESTAMP - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_MMC_BASE 0xF0000000 - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -#define FPGA_REGS_BASE_PHYSICAL 0x08000000 - -/* - * GPIO settings - */ -#define CFG_GPSR0_VAL 0x00008000 -#define CFG_GPSR1_VAL 0x00FC0382 -#define CFG_GPSR2_VAL 0x0001FFFF -#define CFG_GPCR0_VAL 0x00000000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 -#define CFG_GPDR0_VAL 0x0060A800 -#define CFG_GPDR1_VAL 0x00FF0382 -#define CFG_GPDR2_VAL 0x0001C000 -#define CFG_GAFR0_L_VAL 0x98400000 -#define CFG_GAFR0_U_VAL 0x00002950 -#define CFG_GAFR1_L_VAL 0x000A9558 -#define CFG_GAFR1_U_VAL 0x0005AAAA -#define CFG_GAFR2_L_VAL 0xA0000000 -#define CFG_GAFR2_U_VAL 0x00000002 - -#define CFG_PSSR_VAL 0x20 - -/* - * Memory settings - */ -#define CFG_MSC0_VAL 0x23F223F2 -#define CFG_MSC1_VAL 0x3FF1A441 -#define CFG_MSC2_VAL 0x7FF97FF1 -#define CFG_MDCNFG_VAL 0x00001AC9 -#define CFG_MDREFR_VAL 0x00018018 -#define CFG_MDMRS_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 - -#define _LED 0x08000010 -#define LED_BLANK 0x08000040 - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - -/* NOTE: many default partitioning schemes assume the kernel starts at the - * second sector, not an environment. You have been warned! - */ -#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) -#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CFG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) - - -/* - * FPGA Offsets - */ -#define WHOAMI_OFFSET 0x00 -#define HEXLED_OFFSET 0x10 -#define BLANKLED_OFFSET 0x40 -#define DISCRETELED_OFFSET 0x40 -#define CNFG_SWITCHES_OFFSET 0x50 -#define USER_SWITCHES_OFFSET 0x60 -#define MISC_WR_OFFSET 0x80 -#define MISC_RD_OFFSET 0x90 -#define INT_MASK_OFFSET 0xC0 -#define INT_CLEAR_OFFSET 0xD0 -#define GP_OFFSET 0x100 - -#endif /* __CONFIG_H */ diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h deleted file mode 100644 index 9b4c004..0000000 --- a/include/configs/lwmon.h +++ /dev/null @@ -1,612 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* External logbuffer support */ -#define CONFIG_LOGBUFFER - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823E CPU */ -#define CONFIG_LWMON 1 /* ...on a LWMON board */ - -/* Default Ethernet MAC address */ -#define CONFIG_ETHADDR 00:11:B0:00:00:00 - -/* The default Ethernet MAC address can be overwritten just once */ -#ifdef CONFIG_ETHADDR -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#endif - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ - -#define CONFIG_LCD 1 /* use LCD controller ... */ -#define CONFIG_HLD1045 1 /* ... with a HLD1045 display */ - -#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ -#define CONFIG_LCD_INFO 1 /* ... and some board info */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ - -#define CONFIG_SERIAL_MULTI 1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */ - -#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */ - -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -/* pre-boot commands */ -#define CONFIG_PREBOOT "setenv bootdelay 15" - -#undef CONFIG_BOOTARGS - -/* POST support */ -#define CONFIG_POST (CFG_POST_CACHE | \ - CFG_POST_WATCHDOG | \ - CFG_POST_RTC | \ - CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_UART | \ - CFG_POST_ETHER | \ - CFG_POST_I2C | \ - CFG_POST_SPI | \ - CFG_POST_USB | \ - CFG_POST_SPR | \ - CFG_POST_SYSMON) - -/* - * Keyboard commands: - * # = 0x28 = ENTER : enable bootmessages on LCD - * 2 = 0x3A+0x3C = F1 + F3 : enable update mode - * 3 = 0x3C+0x3F = F3 + F6 : enable test mode - */ - -#define CONFIG_BOOTCOMMAND "autoscr 40040000;saveenv" - -/* "gatewayip=10.8.211.250\0" \ */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40280000\0" \ - "netmask=255.255.192.0\0" \ - "serverip=10.8.2.101\0" \ - "ipaddr=10.8.57.0\0" \ - "magic_keys=#23\0" \ - "key_magic#=28\0" \ - "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \ - "key_magic2=3A+3C\0" \ - "key_cmd2=echo *** Entering Update Mode ***;" \ - "if fatload ide 0:3 10000 update.scr;" \ - "then autoscr 10000;" \ - "else echo *** UPDATE FAILED ***;" \ - "fi\0" \ - "key_magic3=3C+3F\0" \ - "key_cmd3=echo *** Entering Test Mode ***;" \ - "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ - "panic=1\0" \ - "add_wdt=setenv bootargs $bootargs $wdt_args\0" \ - "add_misc=setenv bootargs $bootargs runmode\0" \ - "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \ - "bootm $kernel_addr\0" \ - "flash_self=run ramargs addip add_wdt addfb add_misc;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \ - "run nfsargs addip add_wdt addfb;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "load=tftp 100000 /tftpboot/u-boot.bin\0" \ - "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \ - "wdt_args=wdt_8xx=off\0" \ - "verify=no" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ -#define CFG_WATCHDOG_FREQ (CFG_HZ / 20) - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_SNTP ) -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * When the watchdog is enabled, output must be fast enough in Linux. - */ -#ifdef CONFIG_WATCHDOG -#define CFG_BAUDRATE_TABLE { 38400, 57600, 115200 } -#else -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#endif - -/*----------------------------------------------------------------------*/ -#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */ -#undef CONFIG_MODEM_SUPPORT_DEBUG - -#define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */ -#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ -#if 0 -#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" -#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ -#endif -/*----------------------------------------------------------------------*/ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 68 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_USE_BUFFER_WRITE -#define CFG_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */ -/* Buffer size. - We have two flash devices connected in parallel. - Each device incorporates a Write Buffer of 32 bytes. - */ -#define CFG_FLASH_BUFFER_SIZE (2*32) - -/* Put environment in flash which is much faster to boot than using the EEPROM */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0x40040000 /* Address of Environment Sector */ -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */ - -/*----------------------------------------------------------------------- - * I2C/EEPROM Configuration - */ - -#define CFG_I2C_AUDIO_ADDR 0x28 /* Audio volume control */ -#define CFG_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */ -#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ -#define CFG_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */ -#define CFG_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */ -#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ -#define CFG_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */ - -#undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */ - -#ifdef CONFIG_USE_FRAM /* use FRAM */ -#define CFG_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#else /* use EEPROM */ -#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ -#endif /* CONFIG_USE_FRAM */ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 - -/* List of I2C addresses to be verified by POST */ -#ifdef CONFIG_USE_FRAM -#define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \ - CFG_I2C_SYSMON_ADDR, \ - CFG_I2C_RTC_ADDR, \ - CFG_I2C_POWER_A_ADDR, \ - CFG_I2C_POWER_B_ADDR, \ - CFG_I2C_KEYBD_ADDR, \ - CFG_I2C_PICIO_ADDR, \ - CFG_I2C_EEPROM_ADDR, \ - } -#else /* Use EEPROM - which show up on 8 consequtive addresses */ -#define I2C_ADDR_LIST { /* CFG_I2C_AUDIO_ADDR, */ \ - CFG_I2C_SYSMON_ADDR, \ - CFG_I2C_RTC_ADDR, \ - CFG_I2C_POWER_A_ADDR, \ - CFG_I2C_POWER_B_ADDR, \ - CFG_I2C_KEYBD_ADDR, \ - CFG_I2C_PICIO_ADDR, \ - CFG_I2C_EEPROM_ADDR+0, \ - CFG_I2C_EEPROM_ADDR+1, \ - CFG_I2C_EEPROM_ADDR+2, \ - CFG_I2C_EEPROM_ADDR+3, \ - CFG_I2C_EEPROM_ADDR+4, \ - CFG_I2C_EEPROM_ADDR+5, \ - CFG_I2C_EEPROM_ADDR+6, \ - CFG_I2C_EEPROM_ADDR+7, \ - } -#endif /* CONFIG_USE_FRAM */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */ -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -/* EARB, DBGC and DBPC are initialised by the HCW */ -/* => 0x000000C0 */ -#define CFG_SIUMCR (SIUMCR_GB5E) -/*#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00405000 */ -#define CFG_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */ -#define CFG_PLPRCR \ - ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ - ) - -#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*13200000) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800000 */ -#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD100 | \ - SCCR_DFALCD01) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/* 0x00C3 => 0x0003 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0x0000 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CFG_RMDS 0 - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0x50000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0x54000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0x58000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0x5C000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -#define CONFIG_SUPPORT_VFAT /* enable VFAT support */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - second Flash bank optional - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */ - -/* used to re-map FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */ - -/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK) - -#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ - CFG_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) - -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V ) - -/* - * BR3/OR3: SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */ -#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */ - -#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR5/OR5: Touch Panel - * - * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 - */ -#define TOUCHPNL_BASE 0x20000000 -#define TOUCHPNL_OR_AM 0xFFFF8000 -#define TOUCHPNL_TIMING OR_SCY_0_CLK - -#define CFG_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - TOUCHPNL_TIMING ) -#define CFG_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) - -#define CFG_MEMORY_75 -#undef CFG_MEMORY_7E -#undef CFG_MEMORY_8E - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MPTPR 0x200 - -/* - * MAMR settings for SDRAM - */ - -#define CFG_MAMR_8COL 0x80802114 -#define CFG_MAMR_9COL 0x80904114 - -/* - * MAR setting for SDRAM - */ -#define CFG_MAR 0x00000088 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ml300.h b/include/configs/ml300.h deleted file mode 100644 index 6762cd6..0000000 --- a/include/configs/ml300.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * ML300.h: ML300 specific config options - * - * http://www.xilinx.com/ml300 - * - * Derived from : ML2.h - * - * Author: Xilinx, Inc. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR - * OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx products are not intended for use in life support appliances, - * devices, or systems. Use in such applications is expressly prohibited. - * - * - * (c) Copyright 2002 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* #define DEBUG */ -/* #define ET_DEBUG 1 */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */ - -#define CONFIG_SYSTEMACE 1 -#define CONFIG_DOS_PARTITION 1 -#define CFG_SYSTEMACE_BASE XPAR_OPB_SYSACE_0_BASEADDR -#define CFG_SYSTEMACE_WIDTH XPAR_XSYSACE_MEM_WIDTH - -#define CFG_ENV_IS_IN_EEPROM 1 /* environment is in EEPROM */ - -/* following are used only if env is in EEPROM */ -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_I2C_EEPROM_ADDR XPAR_PERSISTENT_0_IIC_0_EEPROMADDR -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_ENV_OFFSET XPAR_PERSISTENT_0_IIC_0_BASEADDR -#define CONFIG_MISC_INIT_R 1 /* used to call out convert_env() */ -#define CONFIG_ENV_OVERWRITE 1 /* allow users to update ethaddr and serial# */ -#endif - -#include "../board/xilinx/ml300/xparameters.h" - -#define CFG_NO_FLASH 1 /* no flash */ -#define CFG_ENV_SIZE XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ - -#define CONFIG_BOOTARGS "console=ttyS0,9600 ip=off " \ - "root=/dev/xsysace/disc0/part3 rw" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define REMOVE_COMMANDS (CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_FAT | \ - CFG_CMD_IMLS ) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_NET) \ - & ~REMOVE_COMMANDS) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */ -/* 300000000 */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_DUART_CHAN 0 -#define CFG_NS16550_REG_SIZE -4 -#define CFG_NS16550 1 -#define CFG_INIT_CHAN1 1 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MONITOR_BASE 0x04000000 -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -#define CFG_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h deleted file mode 100644 index 2028767..0000000 --- a/include/configs/modnet50.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2004 - * IMMS, gGmbH - * Thomas Elste - * - * Configuation settings for ModNET50 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ -#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#define CONFIG_NETARM /* it's a Netsiclicon NET+ARM */ -#undef CONFIG_NETARM_NET40_REV2 /* it's a Net+40 Rev. 2 */ -#undef CONFIG_NETARM_NET40_REV4 /* it's a Net+40 Rev. 4 */ -#define CONFIG_NETARM_NET50 /* it's a Net+50 */ - -#define CONFIG_MODNET50 1 /* on an ModNET50 Board */ - -#undef CONFIG_USE_IRQ /* don't need them anymore */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_NETARMETH 1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_JFFS2)) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.30.2 -#define CONFIG_SERVERIP 192.168.30.122 -#define CFG_ETH_PHY_ADDR 0x100 -#define CONFIG_CMDLINE_TAG /* submit bootargs to kernel */ - -/*#define CONFIG_BOOTDELAY 10*/ -/* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */ -#define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000" -#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "modnet50 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x00500000 /* default load address */ - -#define CFG_HZ 900 /* decrementer freq: 2 kHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below -*/ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ -#define PHYS_SDRAM_2 0x01000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */ - -#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */ -#define PHYS_FLASH_1_SIZE 0x00200000 /* 2 MB (one chip only, 16bit access) */ - -#define PHYS_FLASH_2 0x10200001 -#define PHYS_FLASH_2_SIZE 0x00200000 - -#define CONFIG_NETARM_EEPROM -/* #ifdef CONFIG_NETARM_EEPROM */ -#define PHYS_NVRAM_1 0x20000000 /* EEPROM Bank #1 */ -#define PHYS_NVRAM_SIZE 0x00002000 /* 8 KB */ -/* #endif */ - -#define PHYS_EXT_1 0x30000000 /* Extensions Bank #1 */ -#define PHYS_EXT_SIZE 0x01000000 /* 32 MB memory mapped I/O */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_FLASH_SIZE PHYS_FLASH_1_SIZE - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ -#define CFG_MAIN_SECT_SIZE 0x00010000 /* main size of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -/* environment settings */ -#define CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_NOWHERE - -#define CFG_ENV_ADDR 0x1001C000 /* environment start address */ -#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* max size for environment */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00080000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=modnet50-0" -#define MTDPARTS_DEFAULT "mtdparts=modnet50-0:-@512k(jffs2)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h deleted file mode 100644 index 04f1f24..0000000 --- a/include/configs/mp2usb.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * 2004-2005 Gary Jennejohn - * - * Modified for the MP2USB by (C) Copyright 2005 Eric Benard - * ebenard@eukrea.com - * - * Configuration settings for the MP2USB board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* ARM asynchronous clock */ -#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */ -#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ - -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ -#define CONFIG_MP2USB 1 /* on an MP2USB Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CFG_ATMEL_PLL_INIT_BUG 1 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CFG_USE_MAIN_OSCILLATOR 1 -/* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC2_CSR_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ -#define PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */ - -/* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x3211295A /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000020 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CONFIG_BAUDRATE 115200 - -#define CFG_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */ - -/* - * Hardware drivers - */ - -/* define one of these to choose the DBGU, USART0 or USART1 as console */ -#define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 - -#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ - -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_AT91C_PQFP_UHPBUG 1 - -#undef CONFIG_HARD_I2C - -#ifdef CONFIG_HARD_I2C -#define CFG_I2C_SPEED 0 /* not used */ -#define CFG_I2C_SLAVE 0 /* not used */ -#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ -#define CFG_I2C_RTC_ADDR 0x32 -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_I2C_EEPROM_ADDR_OVERFLOW -#endif -/* still about 20 kB free with this defined */ -#define CFG_LONGHELP - -#define CONFIG_BOOTDELAY 3 - -#ifdef CONFIG_HARD_I2C -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - CFG_CMD_MISC)) -#else -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - CFG_CMD_USB | \ - CFG_CMD_CACHE) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_IMI | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC | \ - CFG_CMD_LOADS )) -#define CONFIG_TIMESTAMP -#endif -#define CFG_LONGHELP - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ - -#define CFG_MEMTEST_START PHYS_SDRAM -#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 - -#define CONFIG_DRIVER_ETHER -#define CONFIG_NET_RETRY_COUNT 20 -#undef CONFIG_AT91C_USE_RMII - -#define PHYS_FLASH_1 0x10000000 -#define PHYS_FLASH_SIZE 0x1000000 /* 16 megs main flash */ -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 256 -#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ -#define CFG_FLASH_LOCK_TOUT (10*CFG_HZ) /* Timeout for Flash Set Lock Bit */ -#define CFG_FLASH_UNLOCK_TOUT (10*CFG_HZ) /* Timeout for Flash Clear Lock Bits */ -#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_ENV_OFFSET) -#define CFG_ENV_SIZE 0x20000 - -#define CFG_LOAD_ADDR 0x21000000 /* default load address */ - -#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } - -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_MAXARGS 32 /* max number of command args */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ - -#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ - -#ifndef __ASSEMBLY__ -/*----------------------------------------------------------------------- - * Board specific extension for bd_info - * - * This structure is embedded in the global bd_info (bd_t) structure - * and can be used by the board specific code (eg board/...) - */ - -struct bd_info_ext { - /* helper variable for board environment handling - * - * env_crc_valid == 0 => uninitialised - * env_crc_valid > 0 => environment crc in flash is valid - * env_crc_valid < 0 => environment crc in flash is invalid - */ - int env_crc_valid; -}; -#endif /* __ASSEMBLY__ */ - -#define CFG_HZ 1000 -#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ - -#define CONFIG_STACKSIZE (32*1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif - -#define CFG_DEVICE_NULLDEV 1 /* enble null device */ -#undef CONFIG_SILENT_CONSOLE /* enable silent startup */ - -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" -#define CONFIG_AUTOBOOT_STOP_STR " " -#define CONFIG_AUTOBOOT_DELAY_STR "d" - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/mv_dd.h b/include/configs/mv_dd.h new file mode 100644 index 0000000..1523d33 --- /dev/null +++ b/include/configs/mv_dd.h @@ -0,0 +1,633 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "../../board/mv_feroceon/mv_dd/mvSysHwConfig.h" + +/************/ +/* VERSIONS */ +/************/ +#ifdef MV632X +#define BUILD_TAG "1.0.4" +#ifdef DUAL_OS_78200 +#define CONFIG_IDENT_STRING " Marvell version: 1.0.4 - Dual CPU" +#else +#define CONFIG_IDENT_STRING " Marvell version: 1.0.4" +#endif + +/* version number passing when loading Kernel */ +#define VER_NUM 0x01000400 /* 1.0.4 */ +#else +#define BUILD_TAG "3.3.28" +#ifdef DUAL_OS_78200 +#define CONFIG_IDENT_STRING " Marvell version: 3.3.28 - Dual CPU" +#else +#define CONFIG_IDENT_STRING " Marvell version: 3.3.28" +#endif + +/* version number passing when loading Kernel */ +#define VER_NUM 0x03031c00 /* 3.3.28 */ +#endif +/* magic word pass when booting Kernel */ +#define MV_UBOOT_MAGIC 0xa0b1c2d3 + +/********************/ +/* MV DEV SUPPORTS */ +/********************/ +#define CONFIG_PCI /* pci support */ + +/**********************************/ +/* Marvell Monitor Extension */ +/**********************************/ +#define enaMonExt() ( /*(!getenv("enaMonExt")) ||\ */ \ + ( getenv("enaMonExt") && \ + ((!strcmp(getenv("enaMonExt"),"yes")) ||\ + (!strcmp(getenv("enaMonExt"),"Yes"))) \ + )\ + ) +#define enaMP() ( /*(!getenv("enaMP")) ||\ */ \ + ( getenv("enaMP") && \ + ((!strcmp(getenv("enaMP"),"yes")) ||\ + (!strcmp(getenv("enaMP"),"Yes"))) \ + )\ + ) +/*Dual CPU support*/ +#define MASTER_CPU 0 +#define SLAVE_CPU 1 + +/********/ +/* CLKs */ +/********/ +#ifndef __ASSEMBLY__ +extern unsigned int mvSysClkGet(void); +extern unsigned int mvTclkGet(void); +extern unsigned int mvMclkGet(void); +#define UBOOT_CNTR 0 /* counter to use for uboot timer */ +#define CFG_HZ 1000 +#define CFG_TCLK mvTclkGet() +#define CFG_BUS_HZ mvSysClkGet() +#define CFG_BUS_CLK CFG_BUS_HZ +#endif + +/********************/ +/* PT settings */ +/********************/ +#define CFG_MV_PT + +#ifdef CFG_MV_PT +#define TOTAL_PAGE_TABLE (8<<20) /* 8M */ +#else +#define TOTAL_PAGE_TABLE 0 +#endif + + +/*************************************/ +/* High Level Configuration Options */ +/* (easy to change) */ +/*************************************/ +#define CONFIG_MARVELL + +/* commands */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) +#if defined(MV_TINY_IMAGE) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_FLASH\ + | CFG_CMD_ENV \ + | CFG_CMD_NET \ + | CFG_CMD_BOOTD \ + | CFG_CMD_NAND) \ + & ~CFG_CMD_MISC \ + & ~CFG_CMD_RCVR) +#elif defined(DB_MV78XX0) || defined(DB_MV88F632X) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_I2C \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_PCI \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_BSP \ + | CFG_CMD_EXT2 \ + | CFG_CMD_IDE \ + | CFG_CMD_MISC \ + | CFG_CMD_NAND \ + | CFG_CMD_USB \ + | CFG_CMD_FAT) \ + & ~CFG_CMD_RCVR) +#elif defined(RD_MV78XX0_AMC) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_I2C \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_PCI \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_BSP \ + | CFG_CMD_EXT2 \ + | CFG_CMD_IDE \ + | CFG_CMD_MISC \ + | CFG_CMD_NAND) \ + & ~CFG_CMD_RCVR) +#elif defined(RD_MV78XX0_H3C) || defined(RD_MV78XX0_PCAC) +#define CONFIG_COMMANDS (((CONFIG_CMD_DFL \ + | CFG_CMD_I2C \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_PCI \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_BSP \ + | CFG_CMD_EXT2 \ + | CFG_CMD_IDE) \ + | CFG_CMD_FLASH) \ + & ~CFG_CMD_RCVR \ + & ~CFG_CMD_IMLS \ + & ~CFG_CMD_NAND) +#elif defined(RD_MV78XX0_MASA) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_I2C \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_PCI \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_BSP \ + | CFG_CMD_EXT2 \ + | CFG_CMD_IDE \ + | CFG_CMD_NAND) \ + & ~CFG_CMD_RCVR \ + & ~CFG_CMD_IMLS \ + & ~CFG_CMD_FLASH) +#endif +/* This needs to be added to the defines above if need USB support +#if defined(MV_INCLUDE_USB) + CFG_CMD_USB + CFG_CMD_FAT +#endif +*/ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_MAXARGS 16 /* max number of command args */ + +/* which initialization functions to call for this board */ +#define CONFIG_MISC_INIT_F /* before relloc */ +#define CONFIG_MISC_INIT_R /* after relloc initialization*/ +#define CONFIG_BOARD_EARLY_INIT_F /* first c function, will initialize the board */ +#define CONFIG_BOARD_EARLY_INIT_R +#define CFG_BOARD_ASM_INIT 1 /* init in asm before moving to c code*/ +#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map*/ + +#define CONFIG_ENV_OVERWRITE /*allow to change env parameters */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_ALTIVEC /* undef to disable */ + +/* Boot Flags*/ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* L2 Cache */ +/* see also env parameter enaL2 */ +#define CFG_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2_INIT | L2CR_L2E) +#define CFG_CACHELINE_SIZE 32 /* For all CPUs */ + +/* global definetions. */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE BOOTDEV_CS_BASE +#define CFG_FLASH_SIZE BOOTDEV_CS_SIZE +#define CFG_RESET_ADDRESS 0xffff0000 + +#if defined(MV_TINY_IMAGE) +#define CFG_MONITOR_LEN (252 << 10) /* Reserve 252 kB for Monitor */ +#elif defined(MV_SEC_128K) +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#elif defined(MV_SEC_256K) +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#elif defined(MV_SEC_64K) +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#endif + +#define CFG_MONITOR_BASE (0xFFFFFFFF - CFG_MONITOR_LEN + 1) + +/* change memory map, the U-boot will sit in 7M */ +/* the malloc area will be 1M */ +#define CFG_UBOOT_TOP (8 << 20) /* 8M */ + +#define CFG_MALLOC_LEN (1 << 20) /* (default) Reserve 1MB for malloc*/ +#define CFG_MALLOC_BASE (TEXT_BASE + (1 << 20)) /* 7M */ + +#define CFG_GUNZIP_LEN (1 << 20) +#undef CONFIG_VERY_BIG_RAM + +/* + * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * To an unused memory region. The stack will remain in cache until RAM + * is initialized +*/ +#undef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x42000000 /* Internal SRAM */ + +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +#define isync() __asm__ __volatile__ ("isync") + +/********/ +/* DRAM */ +/********/ +/* we don't use the global CONFIG_ECC, since in the global ecc we initialize + the DRAM for ECC in the phase we are relocating to it, which isn't so + sufficient. + so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM + initialization phase, see sdram_init.c */ +#undef CONFIG_ECC /* enable ECC support */ +#define CONFIG_MV_ECC + +/* this defines whether we want to use the lowest CAL or the highest CAL available,*/ +/* we also check for the env parameter CASset. */ +#define MV_MIN_CAL + +#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ + +/* default values for mtest : 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x00800000 +#define CFG_MEMTEST_END 0x00C00000 + +/********/ +/* RTC */ +/********/ +#if (CONFIG_COMMANDS & CFG_CMD_DATE) +#define CFG_NVRAM_SIZE 0x00 /* dummy */ +#define CFG_NVRAM_BASE_ADDR DEVICE_CS1_BASE /* dummy */ +#define CONFIG_RTC_DS1338_DS1339 +#endif + +/********************/ +/* Serial + parser */ +/********************/ +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + */ +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#if defined(RD_MV78XX0_H3C) +#define CFG_DUART_CHAN 1 /* channel 1 to use for console */ +#else +#define CFG_DUART_CHAN 0 /* channel 0 to use for console */ +#endif +#define CFG_INIT_CHAN1 +#define CFG_INIT_CHAN2 + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#define CFG_CONSOLE_INFO_QUIET /* don't print In/Out/Err console assignment. */ + +/* parser */ +/* don't chang the parser if you want to load Linux(if you cahnge it to HUSH the cmdline will + not pass to the kernel correctlly???) */ +/*#define CFG_HUSH_PARSER */ +#undef CFG_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE + +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Marvell>> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +/************/ +/* ETHERNET */ +/************/ +/* to change the default ethernet port, use this define (options: 0, 1, 2) */ +#define CONFIG_NET_MULTI +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 + +#define ENV_ETH_PRIME "egiga0" +#if defined(RD_MV78XX0_H3C) +#define YUK_ETHADDR "00:00:00:EE:51:81" +#undef ENV_ETH_PRIME +#define ENV_ETH_PRIME "SK98#0" +#endif + +#define CONFIG_IPADDR 10.4.50.165 +#define CONFIG_SERVERIP 10.4.50.5 +#define CONFIG_NETMASK 255.255.255.0 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 4 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE CFG_IDE_MAXBUS * 8 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#undef CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_LBA48 + +/***************************************/ +/* LINUX BOOT and other ENV PARAMETERS */ +/***************************************/ +#define CFG_BOOTARGS_END ":::DB78xx0:eth0:none" +#define RCVR_IP_ADDR "169.254.100.100" +#define RCVR_LOAD_ADDR "0x00800000" + +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ + +#undef CONFIG_BOOTARGS + +/* auto boot*/ +#define CONFIG_BOOTDELAY 3 /* by default no autoboot */ + +#if (CONFIG_BOOTDELAY >= 0) +#define CONFIG_ROOTPATH /mnt/ARM_FS/ + +#if defined(DUAL_OS_SHARED_MEM_78200) +#define CONFIG_BOOTCOMMAND "lockSem 1;tftpboot 0x2000000 $(image_name);\ +setenv bootargs $(console) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ +cpu0=$(cpu0_res) cpu1=$(cpu1_res) ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x2000000; " +#else +#define CONFIG_BOOTCOMMAND "tftpboot 0x2000000 $(image_name);\ + setenv bootargs $(console) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ +cpu0=$(cpu0_res) cpu1=$(cpu1_res) ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x2000000; " +#endif +#define CONFIG_BOOTARGS "console=ttyS0,115200 mtdparts=physmapped-flash.0:32m(root)" +#endif + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ + +/********/ +/* USB */ +/********/ +#if defined(RD_MV78XX0_AMC) || defined(RD_MV78XX0_H3C) +#define ENV_USB0_MODE "device" +#define ENV_USB1_MODE "host" +#define ENV_USB2_MODE "device" +#elif RD_MV78XX0_MASA +#define ENV_USB0_MODE "host" +#define ENV_USB1_MODE "host" +#define ENV_USB2_MODE "host" +#else +#define ENV_USB0_MODE "host" +#define ENV_USB1_MODE "host" +#define ENV_USB2_MODE "device" +#endif + +#if defined(MV_INCLUDE_USB) +#define CONFIG_USB_EHCI +#define CONFIG_USB_STORAGE +#endif +/********/ +/* I2C */ +/********/ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_SPEED 100000 /* I2C speed default */ + +/* I2C addresses for the two DIMM SPD chips */ +#define DIMM0_I2C_ADDR 0x56 +#define DIMM1_I2C_ADDR 0x54 + +/* CPU I2C settings */ +#define CPU_I2C +#define I2C_CPU0_EEPROM_ADDR 0x51 + + +/********/ +/* PCI */ +/********/ +#ifdef CONFIG_PCI + #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ + #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#ifndef MV_TINY_IMAGE + #define CONFIG_EEPRO100 /* Support for Intel 82557/82559/82559ER chips */ +#endif +#endif + + +#if defined(RD_MV78XX0_AMC) +/* Disable PCI-E scan over PCI-E switch */ +#define PCI_DIS_INTERFACE 8 +#elif defined(RD_MV78XX0_H3C) +#define PCI_DIS_INTERFACE 3 +#elif defined (RD_MV78XX0_MASA) || defined(RD_MV78XX0_PCAC) +#define PCI_DIS_INTERFACE 8 +#elif defined (DB_MV78XX0) +#define PCI_DIS_INTERFACE 2 +#endif +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define CFG_PCI_IDSEL 0x30 + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *-----------------------------------------------------------------------*/ +/* Use the new NAND code. */ + +#undef CFG_NAND_LEGACY +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE +#define __mem_pci(x) x + +/* Boot from NAND settings */ +/* Duplicate defines from nBootstrap.h */ +#ifdef MV_NAND_BOOT +#define CFG_NAND_BOOT +#define CFG_ENV_IS_IN_NAND 1 + +#if defined(MV_LARGE_PAGE) +#define CFG_ENV_OFFSET (128 << 10) /* environment starts here */ +#undef CFG_ENV_SECT_SIZE +#define CFG_ENV_SECT_SIZE (128 << 10) /* environment take 1 block */ +#undef CFG_ENV_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* environment take 1 block */ +#define CFG_NBOOT_BASE 0 +#define CFG_NBOOT_LEN (4 << 10) /* Reserved 4KB for boot strap */ +#undef CFG_MONITOR_LEN +#define CFG_MONITOR_LEN (640 << 10) /* Reserve 4 * 128KB + ENV = 640KB for Monitor */ +#undef CFG_MONITOR_BASE +#define CFG_MONITOR_BASE (CFG_ENV_OFFSET) +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_MONITOR_IMAGE_OFFSET +#define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the u-boot image */ +#define CFG_MONITOR_IMAGE_DST TEXT_BASE - CFG_ENV_SECT_SIZE /* Load NUB to this addr */ +#undef CFG_ENV_ADDR +#define CFG_ENV_ADDR CFG_MONITOR_IMAGE_DST + +#else /* ! LARGE PAGE NAND */ + +#define CFG_ENV_OFFSET (16 << 10) /* environment starts here */ +#undef CFG_ENV_SECT_SIZE +#define CFG_ENV_SECT_SIZE (128 << 10) +#undef CFG_ENV_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* environment take 1 block */ +#define CFG_NBOOT_BASE 0 +#define CFG_NBOOT_LEN (4 << 10) /* Reserved 16kB for boot strap */ +#undef CFG_MONITOR_LEN +#define CFG_MONITOR_LEN (640 << 10) /* Reserve 4 * 128KB + ENV = 640KB for Monitor */ +#undef CFG_MONITOR_BASE +#define CFG_MONITOR_BASE (CFG_ENV_OFFSET) +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_MONITOR_IMAGE_OFFSET +#define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the u-boot image */ +#define CFG_MONITOR_IMAGE_DST TEXT_BASE - CFG_ENV_SECT_SIZE /* Load NUB to this addr */ +#undef CFG_ENV_ADDR +#define CFG_ENV_ADDR CFG_MONITOR_IMAGE_DST +#endif /* defined(MV_LARGE_PAGE) */ +#else /* NOT BOOT FROM NAND */ + +#define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the u-boot image */ +#endif /* MV_NAND_BOOT */ + +/***************************/ +/* CFI FLASH organization */ +/***************************/ +#ifndef CFG_NO_FLASH +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_USE_BUFFER_WRITE +#define CFG_FLASH_QUIET_TEST +#define CFG_FLASH_BANKS_LIST {BOOTDEV_CS_BASE} +#if defined(__BE) +#define CFG_WRITE_SWAPPED_DATA +#endif +#endif /* CFG_NO_FLASH */ + +/***********************/ +/* FLASH organization */ +/***********************/ + +/* + * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash + * banks has to be determined at runtime and stored in a gloabl variable + * mv_board_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only + * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and + * should be made sufficiently large to accomodate the number of banks that + * might actually be detected. Since most (all?) Flash related functions use + * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is + * defined as mv_board_num_flash_banks. + */ +#define CFG_MAX_FLASH_BANKS_DETECT 5 +#ifndef __ASSEMBLY__ +extern int mv_board_num_flash_banks; +#endif +#define CFG_MAX_FLASH_BANKS (mv_board_num_flash_banks) + +#define CFG_MAX_FLASH_SECT 300 /* max number of sectors on one chip */ +#define CFG_FLASH_PROTECTION 1 + +#ifndef MV_NAND_BOOT +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#if defined(MV_TINY_IMAGE) +#define CFG_ENV_SECT_SIZE 0x1000 +#elif defined(MV_SEC_128K) +#define CFG_ENV_SECT_SIZE 0x20000 +#elif defined(MV_SEC_256K) +#define CFG_ENV_SECT_SIZE 0x40000 +#elif defined(MV_SEC_64K) +#define CFG_ENV_SECT_SIZE 0x10000 +#endif +#define CFG_ENV_OFFSET 0x0 +#if defined(MV_TINY_IMAGE) + /* In tiny image we assume we have room for the env + * above the reset vector address */ +#define CFG_ENV_ADDR (0xFFFFFFFF - CFG_ENV_SECT_SIZE + 1) +#else +#define CFG_ENV_ADDR (0xFFFFFFFF - CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE + 1) +#endif +#endif /* MV_NAND_BOOT */ + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CONFIG_JFFS2_CMDLINE +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#define CONFIG_JFFS2_NAND +#endif +#endif + +/*****************/ +/* others */ +/*****************/ +#define CFG_INTERNAL_RAM_ADDR 0xf2400000 /* Internal RAM */ +#define CFG_DFL_MV_REGS 0xD0000000 /* boot time MV_REGS */ +#define CFG_MV_REGS 0xf1000000 /* MV Registers will be mapped here */ + +/***************************/ +/* Relevent for ARM only */ +/***************************/ +#if defined(RD_MV78XX0_H3C) +#define CONFIG_SK98 +#endif +#define CONFIG_STACKSIZE (1 << 20) /* regular stack - up to 4M (in case of exception)*/ +#define CONFIG_NR_DRAM_BANKS 4 +#undef SYSCLK_AUTO_DETECT +#define CFG_PT_BASE(cpu) (CFG_MALLOC_BASE - ((cpu+1) * 0x20000)) + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag for ramdisk data */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MARVELL_TAG 1 +#define ATAG_MARVELL 0x41000403 + +#endif /* __CONFIG_H */ diff --git a/include/configs/mv_feroceon.h b/include/configs/mv_feroceon.h new file mode 100644 index 0000000..a6ab3d5 --- /dev/null +++ b/include/configs/mv_feroceon.h @@ -0,0 +1,812 @@ +/* + * (C) Copyright 2003 + * Texas Instruments. + * Kshitij Gupta + * Configuation settings for the TI OMAP Innovator board. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * Configuration for Integrator AP board. + *. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "../../board/mv_feroceon/mv_orion/orion_sys/mvSysHwConfig.h" + +/************/ +/* VERSIONS */ +/************/ +#ifdef MV_TINY_IMAGE +#define CONFIG_IDENT_STRING " Marvell version: 2.5.10-TINY" +#else +#define CONFIG_IDENT_STRING " Marvell version: 2.5.10" +#endif /* MV_TINY_IMAGE */ +/* version number passing when loading Kernel */ +#define VER_NUM 0x02050a00 /* 2.5.10 */ + +/********************/ +/* MV DEV SUPPORTS */ +/********************/ +#define CONFIG_PCI /* pci support */ +#undef CONFIG_PCI_1 /* sec pci interface support */ + +/********************/ +/* Environment variables */ +/********************/ + + +#define CFG_ENV_IS_IN_FLASH 1 + +/**********************************/ +/* Marvell Monitor Extension */ +/**********************************/ +#define enaMonExt()( /*(!getenv("enaMonExt")) ||\*/\ + ( getenv("enaMonExt") && \ + ((!strcmp(getenv("enaMonExt"),"yes")) ||\ + (!strcmp(getenv("enaMonExt"),"Yes"))) \ + )\ + ) + +/*Dual CPU support*/ +#define MASTER_CPU 0 +#define SLAVE_CPU 1 + +/********/ +/* CLKs */ +/********/ +#ifndef __ASSEMBLY__ +extern unsigned int mvSysClkGet(void); +extern unsigned int mvTclkGet(void); +#define UBOOT_CNTR 0 /* counter to use for uboot timer */ +#define MV_TCLK_CNTR 1 /* counter to use for uboot timer */ +#define MV_REF_CLK_DEV_BIT 1000 /* Number of cycle to eanble timer */ +#define MV_REF_CLK_BIT_RATE 100000 /* Ref clock frequency */ +#define MV_REF_CLK_INPUT_GPP 6 /* Ref clock frequency input */ + +#define CFG_HZ 1000 +#define CFG_TCLK mvTclkGet() +#define CFG_BUS_HZ mvSysClkGet() +#define CFG_BUS_CLK CFG_BUS_HZ +#endif + +/********************/ +/* Dink PT settings */ +/********************/ +#define CFG_MV_PT + +#ifdef CFG_MV_PT +#define CFG_PT_BASE (CFG_MALLOC_BASE - 0x40000) +#endif /* #ifdef CFG_MV_PT */ + + +/*************************************/ +/* High Level Configuration Options */ +/* (easy to change) */ +/*************************************/ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* CPU */ + + +/* commands */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + + +/* Default U-Boot supported features */ +#if defined(MV_TINY_IMAGE) +#define CONFIG_CMD_BASIC (CFG_CMD_PCI \ + | CFG_CMD_FLASH\ + | CFG_CMD_ENV \ + | CFG_CMD_NET \ + | CFG_CMD_IDE \ + | CFG_CMD_EXT2 \ + | CFG_CMD_MEMORY\ + | CFG_CMD_BOOTD) + +#elif defined(DB_FPGA) +#define CONFIG_CMD_BASIC ( CFG_CMD_DHCP \ + | CFG_CMD_ELF \ + | CFG_CMD_I2C \ + | CFG_CMD_EEPROM \ + | CFG_CMD_PCI \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_DATE \ + | CFG_CMD_LOADS \ + | CFG_CMD_FLASH \ + | CFG_CMD_MEMORY \ + | CFG_CMD_ENV \ + | CFG_CMD_BOOTD \ + | CFG_CMD_CONSOLE \ + | CFG_CMD_RUN \ + | CFG_CMD_MISC \ + ) +#else +#define CONFIG_CMD_BASIC ( CFG_CMD_DHCP \ + | CFG_CMD_ELF \ + | CFG_CMD_I2C \ + | CFG_CMD_EEPROM \ + | CFG_CMD_PCI \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_DATE \ + | CFG_CMD_LOADS \ + | CFG_CMD_BSP \ + | CFG_CMD_FLASH \ + | CFG_CMD_MEMORY \ + | CFG_CMD_IDE \ + | CFG_CMD_EXT2 \ + | CFG_CMD_ENV \ + | CFG_CMD_BOOTD \ + | CFG_CMD_CONSOLE \ + | CFG_CMD_RUN \ + | CFG_CMD_MISC \ + ) + +#endif + +#if defined(MV_NAND) || defined(MV_NAND_BOOT) +#define CONFIG_CMD_BASIC1 (CONFIG_CMD_BASIC | CFG_CMD_NAND) +#else +#define CONFIG_CMD_BASIC1 CONFIG_CMD_BASIC +#endif + +#if (defined(MV_INCLUDE_PEX) | defined(MV_INCLUDE_PCI)) +#define CONFIG_CMD_BASIC2 CONFIG_CMD_BASIC1 +#else +#undef CONFIG_PCI +#define CONFIG_CMD_BASIC2 (CONFIG_CMD_BASIC1 & ~CFG_CMD_PCI) +#endif + + +#if (!defined (MV_INC_BOARD_NOR_FLASH) && \ + !defined(MV_INC_BOARD_SPI_FLASH) && \ + !defined(MV_INCLUDE_INTEG_MFLASH)) +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_NOWHERE +#define CFG_NO_FLASH +#define CONFIG_CMD_BASIC3 (CONFIG_CMD_BASIC2 & ~CFG_CMD_FLASH \ + & ~CFG_CMD_ENV \ + & ~CFG_CMD_JFFS2) +#else +#define CONFIG_CMD_BASIC3 CONFIG_CMD_BASIC2 +#endif + +#if !defined (MV_INC_BOARD_NAND_FLASH) +#define CONFIG_CMD_BASIC4 (CONFIG_CMD_BASIC3 & ~CFG_CMD_NAND) +#else +#define CONFIG_CMD_BASIC4 CONFIG_CMD_BASIC3 +#endif + +#if !defined (MV_INC_BOARD_PCI_SATA) && !defined (MV_INCLUDE_INTEG_SATA) +#define CONFIG_CMD_BASIC5 (CONFIG_CMD_BASIC4 & ~CFG_CMD_IDE \ + & ~CFG_CMD_EXT2) +#else +#define CONFIG_CMD_BASIC5 CONFIG_CMD_BASIC4 +#endif + +#if defined(MV_MMC) +#define CONFIG_CMD_BASIC6 (CONFIG_CMD_BASIC5 | CFG_CMD_MMC | CFG_CMD_FAT) +#else +#define CONFIG_CMD_BASIC6 CONFIG_CMD_BASIC5 +#endif +#define CONFIG_COMMANDS CONFIG_CMD_BASIC6 + + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_MAXARGS 16 /* max number of command args */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 4 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE CFG_IDE_MAXBUS * 8 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#undef CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#ifndef CONFIG_MMC +#define CONFIG_LBA48 +#endif + +/* which initialization functions to call for this board */ +#define CONFIG_MISC_INIT_R 1 /* after relloc initialization*/ +#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map*/ + +#define CONFIG_ENV_OVERWRITE /* allow to change env parameters */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* Cache */ +#define CFG_CACHELINE_SIZE 32 + + +/* global definetions. */ +#define CFG_SDRAM_BASE 0x00000000 + + +#define CFG_RESET_ADDRESS 0xffff0000 + +#define CFG_MALLOC_BASE (3 << 20) /* 3M */ + +/* + * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * To an unused memory region. The stack will remain in cache until RAM + * is initialized +*/ +#define CFG_MALLOC_LEN (1 << 20) /* (default) Reserve 1MB for malloc*/ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ + +#undef CONFIG_INIT_CRITICAL /* critical code in start.S */ + + +/********/ +/* DRAM */ +/********/ + +#define CFG_DRAM_BANKS 4 + +/* this defines whether we want to use the lowest CAL or the highest CAL available,*/ +/* we also check for the env parameter CASset. */ +#define MV_MIN_CAL + +#define CFG_MEMTEST_START 0x00400000 +#define CFG_MEMTEST_END 0x007fffff + +/********/ +/* RTC */ +/********/ +#if (CONFIG_COMMANDS & CFG_CMD_DATE) +#define CFG_NVRAM_SIZE 0x00 /* dummy */ +#define CFG_NVRAM_BASE_ADDR DEVICE_CS1_BASE /* dummy */ +#define CONFIG_RTC_DS1338_DS1339 +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_DATE) */ + +/********************/ +/* Serial + parser */ +/********************/ +/* + * The following defines let you select what serial you want to use + * for your console driver. + */ +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } + +#ifdef DB_FPGA +#define CFG_DUART_CHAN 1 /* channel to use for console */ +#else +#define CFG_DUART_CHAN 0 /* channel to use for console */ +#endif + +#define CFG_INIT_CHAN1 +#define CFG_INIT_CHAN2 + + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#define CFG_CONSOLE_INFO_QUIET /* don't print In/Out/Err console assignment. */ +#undef CONFIG_SILENT_CONSOLE /* define for Pex complince */ + +/* parser */ +/* don't chang the parser if you want to load Linux(if you cahnge it to HUSH the cmdline will + not pass to the kernel correctlly???) */ +/*#define CFG_HUSH_PARSER */ +#undef CFG_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE + +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "Marvell>> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +/************/ +/* ETHERNET */ +/************/ +/* to change the default ethernet port, use this define (options: 0, 1, 2) */ +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#define CONFIG_NET_MULTI +#define CONFIG_IPADDR 10.4.50.165 +#define CONFIG_SERVERIP 10.4.50.5 +#define CONFIG_NETMASK 255.255.255.0 +#endif + +#if defined(DB_PRPMC) || defined(DB_88F1281) || defined(DB_MNG) || defined(DB_88F6183LBP) + #define YUK_ETHADDR "00:00:00:EE:51:81" + #define ENV_ETH_PRIME "SK98#0" +#else + #define ETHADDR "00:00:00:00:51:81" + #define ETH1ADDR "00:00:00:00:51:82" + #if defined(MV_INCLUDE_GIG_ETH) + #define ENV_ETH_PRIME "egiga0" + #elif defined(MV_INCLUDE_UNM_ETH) + #define ENV_ETH_PRIME "efast0" + #else + #define ENV_ETH_PRIME "none" + #endif +#endif + +/************/ +/* PCI */ +/************/ +#if defined(MV_INCLUDE_PCI) + +#if defined(DB_PEX_PCI) +#define ENV_PCI_MODE "device" /* PCI */ +#else +#define ENV_PCI_MODE "host" /* PCI */ +#endif + +#endif + +/************/ +/* USB */ +/************/ + +#if defined(MV_INCLUDE_USB) + #if defined(RD_88F5182) || defined(RD_88F5182_3) || \ + defined(RD_88W8660) || defined(RD_88F5181_POS_NAS) || \ + defined(RD_88F5181L_FE) || defined(RD_88F5181L_GE) || defined(RD_88F5181L_FXO_GE) || \ + defined(RD_88F5181_GTWGE) || defined(RD_88F5181_GTWFE) || defined(RD_88W8660_AP82S) || \ + defined(RD_88F6082MICRO_DAS_NAS) + #define ENV_USB0_MODE "host" + #define ENV_USB1_MODE "host" + #else + #define ENV_USB0_MODE "device" + #define ENV_USB1_MODE "device" + #endif +#define CONFIG_USB_EHCI +#define CONFIG_USB_STORAGE +#endif + +/************/ +/* SDIO/MMC */ +/************/ + +#if defined(MV_88F6183) || defined(MV_88F6183L) +#define CONFIG_MMC +#define CFG_MMC_BASE 0xF0000000 +#endif + +/***************************************/ +/* LINUX BOOT and other ENV PARAMETERS */ +/***************************************/ +#if defined (DB_PRPMC) || defined(RD_88F5181L_FE) || defined(RD_88F5181L_GE) || \ + defined(MV_88W8660) || defined(RD_88F5181L_FXO_GE) || \ + defined(RD_88F5181_GTWGE) || defined (RD_88F5181_GTWFE)|| defined(MV_88F6183) || defined(MV_88F6183L) + +#define CFG_BOOTARGS_END ":::DB88FXX81:eth0:none" +#else +#define CFG_BOOTARGS_END ":::DB88FXX81:egiga0:none" +#endif + +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ + +#undef CONFIG_BOOTARGS + +/* auto boot*/ +#if defined(RD_88F6082MICRO_DAS_NAS) +#define CONFIG_BOOTDELAY 1 /* by default no autoboot */ +#else +#define CONFIG_BOOTDELAY 3 /* by default no autoboot */ +#endif + +#if (CONFIG_BOOTDELAY >= 0) +#define CONFIG_ROOTPATH /mnt/ARM_FS/ +#endif /* #if (CONFIG_BOOTDELAY >= 0) */ + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag for ramdisk data */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MARVELL_TAG 1 +#define ATAG_MARVELL 0x41000403 + +/********/ +/* I2C */ +/********/ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_SPEED 100000 /* I2C speed default */ + +/* I2C addresses for the two DIMM SPD chips */ +#define DIMM0_I2C_ADDR 0x56 +#define DIMM1_I2C_ADDR 0x54 + +/* CPU I2C settings */ +#define CPU_I2C +#define I2C_CPU0_EEPROM_ADDR 0x51 + + +/********/ +/* PCI */ +/********/ +#ifdef CONFIG_PCI + #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ + #define CONFIG_PCI_PNP /* do pci plug-and-play */ + +/* Pnp PCI Network cards */ + #define CONFIG_EEPRO100 /* Support for Intel 82557/82559/82559ER chips */ + #define CONFIG_SK98 /* yukon */ + #define CONFIG_DRIVER_RTL8029 + +/* To reduce image size... */ +#if defined (MV_USB) || defined (MV_TINY_IMAGE) || defined(RD_88W8660_AP82S) || defined(DB_PEX_PCI) || defined(__BE) + #undef CONFIG_DRIVER_RTL8029 + #undef CONFIG_EEPRO100 +#endif + +/* To reduce image size... */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if !defined (MV_NAND_BOOT) + #undef CONFIG_DRIVER_RTL8029 + #undef CONFIG_EEPRO100 + #undef CONFIG_SK98 +#endif +#endif + +/* DB_PRPMC support only Yukon */ +#if defined (DB_PRPMC) || defined (DB_MNG) + #undef CONFIG_EEPRO100 + #undef CONFIG_DRIVER_RTL8029 +#endif + +#endif /* #ifdef CONFIG_PCI */ + +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +/* for Yukon */ +#define __mem_pci(x) x +#define __io_pci(x) x +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) + + + +/***********************/ +/* FLASH organization */ +/***********************/ + +/* + * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash + * banks has to be determined at runtime and stored in a gloabl variable + * mv_board_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only + * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and + * should be made sufficiently large to accomodate the number of banks that + * might actually be detected. Since most (all?) Flash related functions use + * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is + * defined as mv_board_num_flash_banks. + */ +#define CFG_MAX_FLASH_BANKS_DETECT 5 +#ifndef __ASSEMBLY__ +extern int mv_board_num_flash_banks; +#endif +#define CFG_MAX_FLASH_BANKS (mv_board_num_flash_banks) + +#define CFG_MAX_FLASH_SECT 300 /* max number of sectors on one chip */ +#define CFG_FLASH_PROTECTION 1 + +#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ +#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ +#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */ + +#define CFG_FLASH_ERASE_TOUT 120000/1000 /* 120000 - Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* 500 - Timeout for Flash Write (in ms) */ +#define CFG_FLASH_LOCK_TOUT 500 /* 500- Timeout for Flash Lock (in ms) */ + + +/***************************/ +/* CFI FLASH organization */ +/***************************/ +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_USE_BUFFER_WRITE +#define CFG_FLASH_QUIET_TEST +#define CFG_FLASH_BANKS_LIST {BOOTDEV_CS_BASE} +#if defined(__BE) +#define CFG_WRITE_SWAPPED_DATA +#endif + +/* RD_88F5181L_FXO_GE include MXIC 16bit flash working in 8 bit mode */ +#if defined (RD_88F5181L_FXO_GE) +#define AMD_FLASH_16BIT_IN_8BIT_MODE +#endif + + +#if defined (MV_FLASH_BOOT) + + #define CFG_FLASH_BASE DEVICE_MFLASH_BASE + #define CFG_FLASH_SIZE (256 << 10) + +#elif defined (MV_SPI_BOOT) + + #define CFG_FLASH_BASE BOOTDEV_CS_BASE + #define CFG_FLASH_SIZE BOOTDEV_CS_SIZE +#else + #define CFG_FLASH_BASE BOOTDEV_CS_BASE + #define CFG_FLASH_SIZE BOOTDEV_CS_SIZE +#endif /* defined(MV_FLASH_BOOT) */ + +#define CFG_ENV_SIZE 0x1000 + +#define MONITOR_HEADER_LEN 0x200 + +#if defined(MV_SEC_4K) + +#define CFG_ENV_SECT_SIZE 0x1000 + + #if defined(MV_TINY_IMAGE) + + #define CFG_MONITOR_IMAGE_OFFSET 0x0 /* offset of the monitor from the + u-boot image */ + #define CFG_MONITOR_LEN (252 << 10) /* Reserve 252 kB for Monitor */ + #define CFG_MONITOR_BASE CFG_FLASH_BASE + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #else + #define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the + u-boot image */ + #define CFG_MONITOR_LEN (508 << 10) /* Reserve 508 kB for Monitor */ + #define CFG_MONITOR_BASE (CFG_FLASH_BASE + CFG_FLASH_SIZE \ + - CFG_MONITOR_LEN) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) + #endif + +#elif defined(MV_SEC_32K) + + #if defined(MV_TINY_IMAGE) + #define CFG_MONITOR_LEN (256 << 10) /* Reserve 252 kB for Monitor */ + #else + #if defined(MV_BOOTROM) + #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ + #else + #define CFG_MONITOR_LEN (448 << 10) /* Reserve 448 kB for Monitor */ + #endif + #endif + + #define CFG_ENV_SECT_SIZE 0x8000 /* Reserved 3kB for env */ + +#if defined(MV_BOOTROM) + #define CFG_MONITOR_IMAGE_OFFSET 0 /* offset of the monitor from the u-boot image */ +#else + #define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the */ +#endif + + #define CFG_MONITOR_BASE (CFG_FLASH_BASE + CFG_FLASH_SIZE \ + - CFG_MONITOR_LEN) +#if defined(MV_BOOTROM) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) +#else + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) +#endif + +#elif defined(MV_SEC_64K) + + #if defined(MV_TINY_IMAGE) + #define CFG_MONITOR_LEN (256 << 10) /* Reserve 252 kB for Monitor */ + #else + #if defined(MV_BOOTROM) + #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ + #else + #define CFG_MONITOR_LEN (448 << 10) /* Reserve 448 kB for Monitor */ + #endif + #endif + + #define CFG_ENV_SECT_SIZE 0x10000 + +#if defined(MV_BOOTROM) + #define CFG_MONITOR_IMAGE_OFFSET 0 /* offset of the monitor from the u-boot image */ +#else + #define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the */ +#endif + + #define CFG_MONITOR_BASE (CFG_FLASH_BASE + CFG_FLASH_SIZE \ + - CFG_MONITOR_LEN) +#if defined(MV_BOOTROM) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - (2 * CFG_ENV_SECT_SIZE)) +#else + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) +#endif + +#elif defined(MV_SEC_128K) + + #if defined(MV_TINY_IMAGE) + #define CFG_MONITOR_LEN (256 << 10) /* Reserve 252 kB for Monitor */ + #else + #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ + #endif + + #define CFG_ENV_SECT_SIZE 0x20000 + #define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the + u-boot image */ + #define CFG_MONITOR_BASE (CFG_FLASH_BASE + CFG_FLASH_SIZE \ + - CFG_MONITOR_LEN) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) + +#elif defined(MV_SEC_256K) + +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ + + #define CFG_ENV_SECT_SIZE 0x40000 + #define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the + u-boot image */ + #define CFG_MONITOR_BASE (CFG_FLASH_BASE + CFG_FLASH_SIZE \ + - CFG_MONITOR_LEN) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) + +#endif + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *-----------------------------------------------------------------------*/ +/* Use the new NAND code. */ + +#undef CFG_NAND_LEGACY +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE + +/* JFFS2 over NAND define */ +#define CONFIG_JFFS2_NAND 1 + +/* Boot from NAND settings */ +/* Duplicate defines from nBootstrap.h */ +#ifdef MV_NAND_BOOT +#define CFG_NAND_BOOT +#define CFG_ENV_IS_IN_NAND 1 + +#if defined(MV_BOOTROM) +#if defined(MV_LARGE_PAGE) +#define CFG_ENV_OFFSET (128 << 10) /* environment starts here */ +#undef CFG_ENV_SECT_SIZE +#define CFG_ENV_SECT_SIZE (128 << 10) /* environment take 1 block */ +#undef CFG_ENV_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* environment take 1 block */ +#define CFG_NBOOT_BASE 0 +#define CFG_NBOOT_LEN (4 << 10) /* Reserved 4KB for boot strap */ +#undef CFG_MONITOR_LEN +#define CFG_MONITOR_LEN (640 << 10) /* Reserve 4 * 128KB + ENV = 640KB for Monitor */ +#undef CFG_MONITOR_BASE +#define CFG_MONITOR_BASE (CFG_ENV_OFFSET) +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_MONITOR_IMAGE_OFFSET +#define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the u-boot image */ +#define CFG_MONITOR_IMAGE_DST TEXT_BASE - CFG_ENV_SECT_SIZE /* Load NUB to this addr */ +#undef CFG_ENV_ADDR +#define CFG_ENV_ADDR CFG_MONITOR_IMAGE_DST + +#else /* ! LARGE PAGE NAND */ + +#define CFG_ENV_OFFSET 0x84000 /* environment starts here */ +#define CFG_NBOOT_BASE 0 +#define CFG_NBOOT_LEN (16 << 10) /* Reserved 16kB for boot strap */ +#undef CFG_MONITOR_LEN +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#undef CFG_MONITOR_BASE +#define CFG_MONITOR_BASE (CFG_NBOOT_BASE + CFG_NBOOT_LEN) +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_SECT_SIZE +#define CFG_ENV_SECT_SIZE 0x4000 +#undef CFG_MONITOR_IMAGE_OFFSET +#define CFG_MONITOR_IMAGE_OFFSET 0 /* offset of the monitor from the u-boot image */ +#undef CFG_ENV_ADDR +#define CFG_ENV_ADDR 0x84000 /* UBOOT_IMAGE_DEST - UBOOT_IMAGE_OFFS */ + +#endif /* defined(MV_LARGE_PAGE) */ + +#else /* ! MV_BOOTROM */ + +#if defined(MV_LARGE_PAGE) +#define CFG_ENV_OFFSET (128 << 10) /* environment starts here */ +#undef CFG_ENV_SECT_SIZE +#define CFG_ENV_SECT_SIZE (128 << 10) /* environment take 1 block */ +#undef CFG_ENV_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* environment take 1 block */ +#define CFG_NBOOT_BASE 0 +#define CFG_NBOOT_LEN (4 << 10) /* Reserved 4KB for boot strap */ +#undef CFG_MONITOR_LEN +#define CFG_MONITOR_LEN (640 << 10) /* Reserve 4 * 128KB + ENV = 640KB for Monitor */ +#undef CFG_MONITOR_BASE +#define CFG_MONITOR_BASE (CFG_ENV_OFFSET) +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_MONITOR_IMAGE_OFFSET +#define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the u-boot image */ +#define CFG_MONITOR_IMAGE_DST TEXT_BASE - CFG_ENV_SECT_SIZE /* Load NUB to this addr */ +#undef CFG_ENV_ADDR +#define CFG_ENV_ADDR CFG_MONITOR_IMAGE_DST + +#else /* ! LARGE PAGE NAND */ + +#define CFG_ENV_OFFSET (16 << 10) /* environment starts here */ +#undef CFG_ENV_SECT_SIZE +#define CFG_ENV_SECT_SIZE (128 << 10) +#undef CFG_ENV_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* environment take 1 block */ +#define CFG_NBOOT_BASE 0 +#define CFG_NBOOT_LEN (4 << 10) /* Reserved 16kB for boot strap */ +#undef CFG_MONITOR_LEN +#define CFG_MONITOR_LEN (640 << 10) /* Reserve 4 * 128KB + ENV = 640KB for Monitor */ +#undef CFG_MONITOR_BASE +#define CFG_MONITOR_BASE (CFG_ENV_OFFSET) +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_MONITOR_IMAGE_OFFSET +#define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the u-boot image */ +#define CFG_MONITOR_IMAGE_DST TEXT_BASE - CFG_ENV_SECT_SIZE /* Load NUB to this addr */ +#undef CFG_ENV_ADDR +#define CFG_ENV_ADDR CFG_MONITOR_IMAGE_DST +#endif /* defined(MV_LARGE_PAGE) */ +#endif /* defined(MV_BOOTROM) */ + +#endif /* MV_NAND_BOOT */ + + +#if defined(RD_88F5181L_FE) || defined(RD_88F5181L_GE) || defined(RD_88F5181L_FXO_GE) || \ + defined(RD_88F5181_GTWGE) || defined (RD_88F5181_GTWFE) + #define BOARD_LATE_INIT +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CONFIG_JFFS2_CMDLINE +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_JFFS2) */ + + +/*****************/ +/* others */ +/*****************/ +#define CFG_DFL_MV_REGS 0xd0000000 /* boot time MV_REGS */ +#define CFG_MV_REGS INTER_REGS_BASE /* MV Registers will be mapped here */ + +#undef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE (2 << 20) /* regular stack - up to 4M (in case of exception)*/ +#define CONFIG_NR_DRAM_BANKS 4 + +#endif /* __CONFIG_H */ diff --git a/include/configs/mv_kw.h b/include/configs/mv_kw.h new file mode 100644 index 0000000..b6aeddc --- /dev/null +++ b/include/configs/mv_kw.h @@ -0,0 +1,782 @@ +/* + * (C) Copyright 2003 + * Texas Instruments. + * Kshitij Gupta + * Configuation settings for the TI OMAP Innovator board. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * Configuration for Integrator AP board. + *. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "../../board/mv_feroceon/mv_kw/mvSysHwConfig.h" + +/************/ +/* VERSIONS */ +/************/ +#ifdef MV_TINY_IMAGE +#define CONFIG_IDENT_STRING " Marvell version: 3.5.3-TINY" +#else +#define CONFIG_IDENT_STRING " Marvell version: 3.5.3" +#endif /* MV_TINY_IMAGE */ +/* version number passing when loading Kernel */ +#define VER_NUM 0x03050300 /* 3.5.3 */ + +/********************/ +/* MV DEV SUPPORTS */ +/********************/ +//#define CONFIG_PCI /* pci support */ +#undef CONFIG_PCI_1 /* sec pci interface support */ + +/********************/ +/* Environment variables */ +/********************/ + + +#define CFG_ENV_IS_IN_FLASH 1 + +/**********************************/ +/* Marvell Monitor Extension */ +/**********************************/ +#define enaMonExt()( /*(!getenv("enaMonExt")) ||\*/\ + ( getenv("enaMonExt") && \ + ((!strcmp(getenv("enaMonExt"),"yes")) ||\ + (!strcmp(getenv("enaMonExt"),"Yes"))) \ + )\ + ) + +/********/ +/* CLKs */ +/********/ +#ifndef __ASSEMBLY__ +extern unsigned int mvSysClkGet(void); +extern unsigned int mvTclkGet(void); +#define UBOOT_CNTR 0 /* counter to use for uboot timer */ +#define MV_TCLK_CNTR 1 /* counter to use for uboot timer */ +#define MV_REF_CLK_DEV_BIT 1000 /* Number of cycle to eanble timer */ +#define MV_REF_CLK_BIT_RATE 100000 /* Ref clock frequency */ +#define MV_REF_CLK_INPUT_GPP 6 /* Ref clock frequency input */ + +#define CFG_HZ 1000 +#define CFG_TCLK mvTclkGet() +#define CFG_BUS_HZ mvSysClkGet() +#define CFG_BUS_CLK CFG_BUS_HZ +#endif + +/********************/ +/* Dink PT settings */ +/********************/ +#define CFG_MV_PT + +#ifdef CFG_MV_PT +#define CFG_PT_BASE (CFG_MALLOC_BASE - 0x20000) +#endif /* #ifdef CFG_MV_PT */ + + +/*************************************/ +/* High Level Configuration Options */ +/* (easy to change) */ +/*************************************/ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* CPU */ + + +/* commands */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + + +/* Default U-Boot supported features */ +#if defined(MV_TINY_IMAGE) +#define CONFIG_CMD_BASIC (CFG_CMD_PCI \ + | CFG_CMD_FLASH\ + | CFG_CMD_ENV \ + | CFG_CMD_NET \ + | CFG_CMD_IDE \ + | CFG_CMD_EXT2 \ + | CFG_CMD_MEMORY\ + | CFG_CMD_BOOTD) + +#elif defined(DB_FPGA) +#define CONFIG_CMD_BASIC ( CFG_CMD_DHCP \ + | CFG_CMD_ELF \ + | CFG_CMD_I2C \ + | CFG_CMD_EEPROM \ + | CFG_CMD_PCI \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_DATE \ + | CFG_CMD_LOADS \ + | CFG_CMD_FLASH \ + | CFG_CMD_MEMORY \ + | CFG_CMD_ENV \ + | CFG_CMD_BOOTD \ + | CFG_CMD_CONSOLE \ + | CFG_CMD_RUN \ + | CFG_CMD_MISC \ + ) +#else +#define CONFIG_CMD_BASIC ( /* CFG_CMD_DHCP */ \ + /* | CFG_CMD_I2C */ \ + /* | CFG_CMD_EEPROM */ \ + /* | CFG_CMD_PCI */ \ + /* | */ CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_DATE \ + | CFG_CMD_BSP \ + | CFG_CMD_FLASH \ + | CFG_CMD_MEMORY \ + | CFG_CMD_IDE \ + | CFG_CMD_IMI \ + | CFG_CMD_EXT2 \ + | CFG_CMD_ENV \ + | CFG_CMD_BOOTD \ + | CFG_CMD_RUN \ + | CFG_CMD_RCVR \ + | CFG_CMD_FAT \ + | CFG_CMD_USB \ + ) + +#endif + +#ifndef MV_MMC +#define MV_MMC +#endif + +#if defined(MV_NAND) || defined(MV_NAND_BOOT) +#define CONFIG_CMD_BASIC1 (CONFIG_CMD_BASIC | CFG_CMD_NAND) +#define CONFIG_MTD_NAND_VERIFY_WRITE +#else +#define CONFIG_CMD_BASIC1 CONFIG_CMD_BASIC +#endif + +#if (defined(MV_INCLUDE_PEX) | defined(MV_INCLUDE_PCI)) +#define CONFIG_CMD_BASIC2 CONFIG_CMD_BASIC1 +#else +#undef CONFIG_PCI +#define CONFIG_CMD_BASIC2 (CONFIG_CMD_BASIC1 & ~CFG_CMD_PCI) +#endif + + +#if (!defined (MV_INC_BOARD_NOR_FLASH) && \ + !defined(MV_INC_BOARD_SPI_FLASH) && \ + !defined(MV_INCLUDE_INTEG_MFLASH)) +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_NOWHERE +#define CFG_NO_FLASH +#define CONFIG_CMD_BASIC3 (CONFIG_CMD_BASIC2 & ~CFG_CMD_FLASH \ + & ~CFG_CMD_ENV \ + & ~CFG_CMD_JFFS2) +#else +#define CONFIG_CMD_BASIC3 CONFIG_CMD_BASIC2 +#endif + +#if !defined (MV_INC_BOARD_NAND_FLASH) +#define CONFIG_CMD_BASIC4 (CONFIG_CMD_BASIC3 & ~CFG_CMD_NAND) +#else +#define CONFIG_CMD_BASIC4 CONFIG_CMD_BASIC3 +#endif + +#if !defined (MV_INC_BOARD_PCI_SATA) && !defined (MV_INCLUDE_INTEG_SATA) +#define CONFIG_CMD_BASIC5 (CONFIG_CMD_BASIC4 & ~CFG_CMD_IDE \ + & ~CFG_CMD_EXT2) +#else +#define CONFIG_CMD_BASIC5 CONFIG_CMD_BASIC4 +#endif + +#if defined(MV_MMC) +#define CONFIG_CMD_BASIC6 (CONFIG_CMD_BASIC5 | CFG_CMD_MMC | CFG_CMD_FAT) +#else +#define CONFIG_CMD_BASIC6 CONFIG_CMD_BASIC5 +#endif +#define CONFIG_COMMANDS CONFIG_CMD_BASIC6 + + + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_MAXARGS 32 /* max number of command args */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 4 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE CFG_IDE_MAXBUS * 8 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#undef CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* For 6121/6145 support */ +#define CONFIG_SCSI_AHCI +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_6121 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif + +#ifndef CONFIG_MMC +#define CONFIG_LBA48 +#endif + +/* which initialization functions to call for this board */ +#define CONFIG_MISC_INIT_R 1 /* after relloc initialization*/ +#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map*/ + +#define CONFIG_ENV_OVERWRITE /* allow to change env parameters */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* Cache */ +#define CFG_CACHELINE_SIZE 32 + + +/* global definetions. */ +#define CFG_SDRAM_BASE 0x00000000 + + +#define CFG_RESET_ADDRESS 0xffff0000 + +#define CFG_MALLOC_BASE (TEXT_BASE + (1 << 20)) /* TEXT_BASE + 1M */ + +/* + * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * To an unused memory region. The stack will remain in cache until RAM + * is initialized +*/ +#define CFG_MALLOC_LEN (1 << 20) /* (default) Reserve 1MB for malloc*/ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ + +#undef CONFIG_INIT_CRITICAL /* critical code in start.S */ + +#define MASTER_CPU 0 + +/********/ +/* DRAM */ +/********/ + +#define CFG_DRAM_BANKS 4 + +/* this defines whether we want to use the lowest CAL or the highest CAL available,*/ +/* we also check for the env parameter CASset. */ +#define MV_MIN_CAL + +#define CFG_MEMTEST_START 0x00400000 +#define CFG_MEMTEST_END 0x007fffff + +/********/ +/* RTC */ +/********/ +#if (CONFIG_COMMANDS & CFG_CMD_DATE) +#define CFG_NVRAM_SIZE 0x00 /* dummy */ +#define CFG_NVRAM_BASE_ADDR DEVICE_CS1_BASE /* dummy */ +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_DATE) */ + +/********************/ +/* Serial + parser */ +/********************/ +/* + * The following defines let you select what serial you want to use + * for your console driver. + */ +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } +#if defined(CONFIG_BUFFALO_PLATFORM) +#define CFG_DUART_CHAN 0 /* channel to use for console */ +#else +#ifdef DB_88F6280A +#define CFG_DUART_CHAN 1 /* channel to use for console */ +#else +#define CFG_DUART_CHAN 0 /* channel to use for console */ +#endif +#endif +#define CFG_INIT_CHAN1 +#define CFG_INIT_CHAN2 + + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#define CFG_CONSOLE_INFO_QUIET /* don't print In/Out/Err console assignment. */ +#undef CONFIG_SILENT_CONSOLE /* define for Pex complince */ + +/* parser */ +/* don't chang the parser if you want to load Linux(if you cahnge it to HUSH the cmdline will + not pass to the kernel correctlly???) */ +#define CFG_HUSH_PARSER +/* #undef CFG_HUSH_PARSER */ +#define CONFIG_AUTO_COMPLETE + +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#if defined(CONFIG_BUFFALO_PLATFORM) +#define CFG_PROMPT "BUFFALO>> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "Marvell>> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +/************/ +/* ETHERNET */ +/************/ +/* to change the default ethernet port, use this define (options: 0, 1, 2) */ +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#define CONFIG_NET_MULTI +#if defined(CONFIG_BUFFALO_PLATFORM) +#define CONFIG_IPADDR 192.168.11.150 +#define CONFIG_SERVERIP 192.168.11.1 +#define CONFIG_NETMASK 255.255.255.0 +#else // !defined(CONFIG_BUFFALO_PLATFORM) +#define CONFIG_IPADDR 10.4.50.165 +#define CONFIG_SERVERIP 10.4.50.5 +#define CONFIG_NETMASK 255.255.255.0 +#endif // defined(CONFIG_BUFFALO_PLATFORM) +#endif + +#define ETHADDR "00:00:00:00:51:81" +#define ETH1ADDR "00:00:00:00:51:82" +#define ENV_ETH_PRIME "egiga0" + +/************/ +/* PCI */ +/************/ +#if defined(MV_INCLUDE_PCI) + +#if defined(DB_PEX_PCI) +#define ENV_PCI_MODE "device" /* PCI */ +#else +#define ENV_PCI_MODE "host" /* PCI */ +#endif + +#endif + +/************/ +/* LCD */ +/************/ + +#define ENV_LCD0_ENABLE "1" +#define ENV_LCD0_PARAMS "640x480-16@60" +#define ENV_LCD_BOOTARGS "video-dovefb:lcd0:$(lcd0_params) clcd.lcd0_enable=$(lcd0_enable)" + +/************/ +/* USB */ +/************/ + +#if defined(MV_INCLUDE_USB) +#define ENV_USB0_MODE "host" +#define CONFIG_USB_EHCI +#if defined(CONFIG_CMD_USB) +#define CONFIG_USB_STORAGE +#endif +#endif + +/************/ +/* SDIO/MMC */ +/************/ + +#if defined(MV_88F6183) || defined(MV_88F6183L) || defined(MV88F6281) || defined(MV88F6282) || \ + defined(MV88F6192) || defined(MV88F6180) || defined(MV88F6280) +#define CONFIG_MMC +#define CFG_MMC_BASE 0xF0000000 +#endif + +/***************************************/ +/* LINUX BOOT and other ENV PARAMETERS */ +/***************************************/ +#define CFG_BOOTARGS_END ":::DB88FXX81:eth0:none" +#define CFG_BOOTARGS_END_SWITCH ":::RD88FXX81:eth0:none" +#define RCVR_IP_ADDR "169.254.100.100" +#define RCVR_LOAD_ADDR "0x02000000" + +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CFG_LOAD_ADDR 0x02000000 /* default load address */ + +#undef CONFIG_BOOTARGS + +/* auto boot*/ +#define CONFIG_BOOTDELAY 3 /* by default no autoboot */ + +#if (CONFIG_BOOTDELAY >= 0) +#define CONFIG_ROOTPATH /mnt/ARM_FS/ +#endif /* #if (CONFIG_BOOTDELAY >= 0) */ + +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag for ramdisk data */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MARVELL_TAG 1 +#define ATAG_MARVELL 0x41000403 + +/********/ +/* I2C */ +/********/ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_SPEED 100000 /* I2C speed default */ + +/* I2C addresses for the two DIMM SPD chips */ +#define DIMM0_I2C_ADDR 0x56 +#define DIMM1_I2C_ADDR 0x54 + +/* CPU I2C settings */ +#define CPU_I2C +#define I2C_CPU0_EEPROM_ADDR 0x51 + + +/********/ +/* PCI */ +/********/ +#ifdef CONFIG_PCI + #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ + #define CONFIG_PCI_PNP /* do pci plug-and-play */ + +/* Pnp PCI Network cards */ +#if !defined(CONFIG_BUFFALO_PLATFORM) + #define CONFIG_EEPRO100 /* Support for Intel 82557/82559/82559ER chips */ + #define CONFIG_SK98 /* yukon */ + #define YUK_ETHADDR "00:00:00:EE:51:81" + #define CONFIG_DRIVER_RTL8029 +#endif + + +/* To reduce image size... */ +#if defined (MV_INCLUDE_USB) || (MV_TINY_IMAGE) || defined(__BE) + #undef CONFIG_SK98 /* yukon */ + #undef CONFIG_DRIVER_RTL8029 + #undef CONFIG_EEPRO100 +#endif + +/* To reduce image size... */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if !defined (MV_NAND_BOOT) + #undef CONFIG_DRIVER_RTL8029 + #undef CONFIG_EEPRO100 + #undef CONFIG_SK98 +#endif +#endif + +/* DB_PRPMC support only Yukon */ +#if defined (DB_PRPMC) || defined (DB_MNG) + #undef CONFIG_EEPRO100 + #undef CONFIG_DRIVER_RTL8029 +#endif + +#endif /* #ifdef CONFIG_PCI */ + +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +/* for Yukon */ +#define __mem_pci(x) x +#define __io_pci(x) x +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) + + + +/***********************/ +/* FLASH organization */ +/***********************/ + +/* + * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash + * banks has to be determined at runtime and stored in a gloabl variable + * mv_board_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only + * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and + * should be made sufficiently large to accomodate the number of banks that + * might actually be detected. Since most (all?) Flash related functions use + * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is + * defined as mv_board_num_flash_banks. + */ +#define CFG_MAX_FLASH_BANKS_DETECT 5 +#ifndef __ASSEMBLY__ +extern int mv_board_num_flash_banks; +#endif +#define CFG_MAX_FLASH_BANKS (mv_board_num_flash_banks) + +#define CFG_MAX_FLASH_SECT 300 /* max number of sectors on one chip */ +#define CFG_FLASH_PROTECTION 1 + +#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ +#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */ +#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */ + +#define CFG_FLASH_ERASE_TOUT 120000/1000 /* 120000 - Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* 500 - Timeout for Flash Write (in ms) */ +#define CFG_FLASH_LOCK_TOUT 500 /* 500- Timeout for Flash Lock (in ms) */ + + +/***************************/ +/* CFI FLASH organization */ +/***************************/ +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_USE_BUFFER_WRITE +#define CFG_FLASH_QUIET_TEST +#define CFG_FLASH_BANKS_LIST {BOOTDEV_CS_BASE} +#if defined(__BE) +#define CFG_WRITE_SWAPPED_DATA +#endif + +#if defined(CONFIG_BUFFALO_PLATFORM) + +#define CFG_FLASH_BASE DEVICE_SPI_BASE +#define CFG_FLASH_SIZE _512K + +#if defined(MV_SEC_64K) +// #if defined(MV_TINY_IMAGE) + #define CFG_MONITOR_LEN (512 << 10) - 0x10000 /* Reserve 64 kB for Monitor */ +// #else +// #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +// #endif +#endif +#define CFG_ENV_SECT_SIZE 0x10000 + +#define MONITOR_HEADER_LEN 0x200 + + +#define CFG_MONITOR_IMAGE_OFFSET 0 /* offset of the monitor from the u-boot image */ +#define CFG_MONITOR_BASE (CFG_FLASH_BASE) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_FLASH_SIZE - CFG_ENV_SECT_SIZE) +#undef CFG_ENV_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* environment take 1 block */ +#define CFG_ENV_OFFSET (CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#else // !defined(CONFIG_BUFFALO_PLATFORM) + +#ifdef MV_BOOTROM +#if defined (MV_FLASH_BOOT) + #define CFG_FLASH_BASE DEVICE_MFLASH_BASE + #define CFG_FLASH_SIZE (256 << 10) +#elif defined (MV_SPI_BOOT) + #define CFG_FLASH_BASE DEVICE_SPI_BASE + #define CFG_FLASH_SIZE _16M +#endif +#else + #define CFG_FLASH_BASE BOOTDEV_CS_BASE + #define CFG_FLASH_SIZE BOOTDEV_CS_SIZE +#endif /* MV_BOOTROM */ + +#define CFG_ENV_SIZE 0x1000 +#define MONITOR_HEADER_LEN 0x200 +#if defined(MV_SEC_64K) + + #if defined(MV_TINY_IMAGE) + #define CFG_MONITOR_LEN (256 << 10) /* Reserve 252 kB for Monitor */ + #else + #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ + #endif + + #define CFG_ENV_SECT_SIZE 0x20000 + +#elif defined(MV_SEC_128K) + + #if defined(MV_TINY_IMAGE) + #define CFG_MONITOR_LEN (256 << 10) /* Reserve 252 kB for Monitor */ + #else + #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ + #endif + + #define CFG_ENV_SECT_SIZE 0x20000 + +#elif defined(MV_SEC_256K) + #if defined(MV_TINY_IMAGE) + #define CFG_MONITOR_LEN (256 << 10) /* Reserve 252 kB for Monitor */ + #else + #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ + #endif + + #define CFG_ENV_SECT_SIZE 0x40000 +#endif + +#ifdef MV_BOOTROM + #define CFG_MONITOR_IMAGE_OFFSET 0 /* offset of the monitor from the u-boot image */ + #define CFG_MONITOR_BASE (CFG_FLASH_BASE) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#else + #define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the u-boot image */ + #define CFG_MONITOR_BASE (CFG_FLASH_BASE + CFG_FLASH_SIZE \ + - CFG_MONITOR_LEN) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) +#endif +#endif // defined(CONFIG_BUFFALO_PLATFORM) + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *-----------------------------------------------------------------------*/ +/* Use the new NAND code. */ + +#undef CFG_NAND_LEGACY +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE + +/* JFFS2 over NAND define */ +#define CONFIG_JFFS2_NAND 1 + +/* Boot from NAND settings */ +/* Duplicate defines from nBootstrap.h */ +#ifdef MV_NAND_BOOT +#define CFG_NAND_BOOT +#define CFG_ENV_IS_IN_NAND 1 + +#if defined(MV_BOOTROM) +#if defined(MV_LARGE_PAGE) +#define CFG_ENV_OFFSET (640 << 10) /* environment starts here */ +#undef CFG_ENV_SECT_SIZE +#define CFG_ENV_SECT_SIZE (128 << 10) /* environment take 1 block */ +#undef CFG_ENV_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* environment take 1 block */ +#define CFG_NBOOT_BASE 0 +#define CFG_NBOOT_LEN (4 << 10) /* Reserved 4KB for boot strap */ +#undef CFG_MONITOR_LEN +#define CFG_MONITOR_LEN (640 << 10) /* Reserve 4 * 128KB + ENV = 640KB for Monitor */ +#undef CFG_MONITOR_BASE +#define CFG_MONITOR_BASE 0 +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_MONITOR_IMAGE_OFFSET +#define CFG_MONITOR_IMAGE_OFFSET 0 /* offset of the monitor from the u-boot image */ +#define CFG_MONITOR_IMAGE_DST TEXT_BASE /* Load NUB to this addr */ +#undef CFG_ENV_ADDR +#define CFG_ENV_ADDR CFG_ENV_OFFSET + +#else /* ! LARGE PAGE NAND */ + +#define CFG_ENV_OFFSET 0x84000 /* environment starts here */ +#define CFG_NBOOT_BASE 0 +#define CFG_NBOOT_LEN (16 << 10) /* Reserved 16kB for boot strap */ +#undef CFG_MONITOR_LEN +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ +#undef CFG_MONITOR_BASE +#define CFG_MONITOR_BASE 0 +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_SECT_SIZE +#define CFG_ENV_SECT_SIZE 0x4000 +#undef CFG_ENV_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* environment take 1 block */ +#undef CFG_MONITOR_IMAGE_OFFSET +#define CFG_MONITOR_IMAGE_OFFSET 0 /* offset of the monitor from the u-boot image */ +#define CFG_MONITOR_IMAGE_DST TEXT_BASE /* Load NUB to this addr */ +#undef CFG_ENV_ADDR +#define CFG_ENV_ADDR CFG_ENV_OFFSET /* UBOOT_IMAGE_DEST - UBOOT_IMAGE_OFFS */ + +#endif /* defined(MV_LARGE_PAGE) */ + +#else /* ! MV_BOOTROM */ + +#if defined(MV_LARGE_PAGE) +#define CFG_ENV_OFFSET (640 << 10) /* environment starts here */ +#undef CFG_ENV_SECT_SIZE +#define CFG_ENV_SECT_SIZE (128 << 10) /* environment take 1 block */ +#undef CFG_ENV_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* environment take 1 block */ +#define CFG_NBOOT_BASE 0 +#define CFG_NBOOT_LEN (4 << 10) /* Reserved 4KB for boot strap */ +#undef CFG_MONITOR_LEN +#define CFG_MONITOR_LEN (640 << 10) /* Reserve 4 * 128KB + ENV = 640KB for Monitor */ +#undef CFG_MONITOR_BASE +#define CFG_MONITOR_BASE 0 +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_MONITOR_IMAGE_OFFSET +#define CFG_MONITOR_IMAGE_OFFSET 0 /* offset of the monitor from the u-boot image */ +#define CFG_MONITOR_IMAGE_DST TEXT_BASE /* Load NUB to this addr */ +#undef CFG_ENV_ADDR +#define CFG_ENV_ADDR CFG_ENV_OFFSET + +#else /* ! LARGE PAGE NAND */ + +#define CFG_ENV_OFFSET (16 << 10) /* environment starts here */ +#undef CFG_ENV_SECT_SIZE +#define CFG_ENV_SECT_SIZE (128 << 10) +#undef CFG_ENV_SIZE +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* environment take 1 block */ +#define CFG_NBOOT_BASE 0 +#define CFG_NBOOT_LEN (4 << 10) /* Reserved 16kB for boot strap */ +#undef CFG_MONITOR_LEN +#define CFG_MONITOR_LEN (640 << 10) /* Reserve 4 * 128KB + ENV = 640KB for Monitor */ +#undef CFG_MONITOR_BASE +#define CFG_MONITOR_BASE (CFG_ENV_OFFSET) +#undef CFG_ENV_IS_IN_FLASH +#undef CFG_MONITOR_IMAGE_OFFSET +#define CFG_MONITOR_IMAGE_OFFSET CFG_ENV_SECT_SIZE /* offset of the monitor from the u-boot image */ +#define CFG_MONITOR_IMAGE_DST TEXT_BASE - CFG_ENV_SECT_SIZE /* Load NUB to this addr */ +#undef CFG_ENV_ADDR +#define CFG_ENV_ADDR CFG_MONITOR_IMAGE_DST +#endif /* defined(MV_LARGE_PAGE) */ +#endif /* defined(MV_BOOTROM) */ + +#endif /* MV_NAND_BOOT */ + + +#if defined(RD_88F5181L_FE) || defined(RD_88F5181L_GE) || defined(RD_88F5181L_FXO_GE) || \ + defined(RD_88F5181_GTWGE) || defined (RD_88F5181_GTWFE) || \ + defined(CONFIG_BUFFALO_PLATFORM) + #define BOARD_LATE_INIT +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CONFIG_JFFS2_CMDLINE +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_JFFS2) */ + + +/*****************/ +/* others */ +/*****************/ +#define CFG_DFL_MV_REGS 0xd0000000 /* boot time MV_REGS */ +#define CFG_MV_REGS INTER_REGS_BASE /* MV Registers will be mapped here */ + +#undef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE (1 << 20) /* regular stack - up to 4M (in case of exception)*/ +#define CONFIG_NR_DRAM_BANKS 4 + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h deleted file mode 100644 index 7f3dfd5..0000000 --- a/include/configs/mx1ads.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * include/configs/mx1ads.h - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu - * - * This is the Configuration setting for Motorola MX1ADS board - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */ -#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Select serial console configuration - */ -#define CONFIG_IMX_SERIAL1 /* internal uart 1 */ -/* #define _CONFIG_UART2 */ /* internal uart 2 */ -/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */ - -#define BOARD_LATE_INIT 1 -#define USE_920T_MMU 1 - -#if 0 -#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ -#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ -#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ -#endif - -/* - * Size of malloc() pool - */ - -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * CS8900 Ethernet drivers - */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x15000300 -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ - -/* - * select serial console configuration - */ - -/* #define CONFIG_UART1 */ -/* #define CONFIG_UART2 1 */ - -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ - -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - CFG_CMD_REGINFO | \ - CFG_CMD_ELF) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M" -#define CONFIG_BOOTFILE "mx1ads" -#define CONFIG_BOOTCOMMAND "tftp; bootm" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ - /* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ - -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CFG_LONGHELP /* undef to save memory */ - -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "MX1ADS$ " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "MX1ADS=> " /* Monitor Command Prompt */ -#endif - -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) - /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x09000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x08800000 /* default load address */ -/*#define CFG_HZ 1000 */ -#define CFG_HZ 3686400 -#define CFG_CPUSPEED 0x141 - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ -#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */ -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYNCFLASH 1 -#define PHYS_FLASH_SIZE 0x01000000 -#define CFG_MAX_FLASH_SECT (16) -#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff8000) - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x100000 - -/*----------------------------------------------------------------------- - * Enable passing ATAGS - */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 - -#define CONFIG_SYS_CLK_FREQ 16780000 -#define CONFIG_SYSPLL_CLK_FREQ 16000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h deleted file mode 100644 index 9816be8..0000000 --- a/include/configs/mx1fs2.h +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ -#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ -#define CONFIG_MX1FS2 1 /* on a mx1fs2 board */ -#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ - -/* - * Select serial console configuration - */ -#undef _CONFIG_UART1 /* internal uart 1 */ -#define _CONFIG_UART2 /* internal uart 2 */ -#undef _CONFIG_UART3 /* internal uart 3 */ -#undef _CONFIG_UART4 /* internal uart 4 */ -#undef CONFIG_SILENT_CONSOLE /* use this to disable output */ - -/* - * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if - * neccessary in include/cmd_confdefs.h file. (Un)comment for getting - * functionality or size of u-boot code. - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - & ~CFG_CMD_LOADS \ - & ~CFG_CMD_CONSOLE \ - & ~CFG_CMD_AUTOSCRIPT \ - & ~CFG_CMD_NET \ - & ~CFG_CMD_PING \ - & ~CFG_CMD_DHCP \ - | CFG_CMD_JFFS2 \ - ) - -#include - -/* - * Boot options. Setting delay to -1 stops autostart count down. - */ -#define CONFIG_BOOTDELAY 10 -#define CONFIG_BOOTARGS "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2" -#define CONFIG_BOOTCOMMAND "bootm 10080000" -#define CONFIG_SHOW_BOOT_PROGRESS - -/* - * General options for u-boot. Modify to save memory foot print - */ -#define CFG_LONGHELP /* undef saves memory */ -#define CFG_PROMPT "mx1fs2> " /* prompt string */ -#define CFG_CBSIZE 256 /* console I/O buffer */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ -#define CFG_MAXARGS 16 /* max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ - -#define CFG_MEMTEST_START 0x08100000 /* memtest test area */ -#define CFG_MEMTEST_END 0x08F00000 - -#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x141 /* core clock - register value */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BAUDRATE 115200 -/* - * Definitions related to passing arguments to kernel. - */ -#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG 1 /* send initrd params */ -#undef CONFIG_VFD /* do not send framebuffer setup */ - -/* - * Malloc pool need to host env + 128 Kb reserve for other allocations. - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CONFIG_STACKSIZE (120<<10) /* stack size */ - -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ -#endif - -/* SDRAM Setup Values - * 0x910a8300 Precharge Command CAS 3 - * 0x910a8200 Precharge Command CAS 2 - * - * 0xa10a8300 AutoRefresh Command CAS 3 - * 0xa10a8200 Set AutoRefresh Command CAS 2 - */ -#define PRECHARGE_CMD 0x910a8300 -#define AUTOREFRESH_CMD 0xa10a8300 - -#define BUS32BIT_VERSION -/* - * SDRAM Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define MX1FS2_SDRAM_1 0x08000000 /* SDRAM bank #1 */ -#ifdef BUS32BIT_VERSION -#define MX1FS2_SDRAM_1_SIZE (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */ -#else -#define MX1FS2_SDRAM_1_SIZE (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */ -#endif -/* - * Flash Controller settings - */ - -#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ - -#ifdef BUS32BIT_VERSION -#define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ -#define MX1FS2_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ -#define MX1FS2_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank*/ -#define MX1FS2_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ -#else -#define MX1FS2_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ -#define MX1FS2_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ -#define MX1FS2_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank*/ -#define MX1FS2_FLASH_SECT_SIZE 0x00010000 /* size of erase sector */ -#endif -#define MX1FS2_FLASH_BASE 0x10000000 /* location of flash memory */ -#define MX1FS2_FLASH_UNLOCK 1 /* perform hw unlock first */ - -/* This should be defined if CFI FLASH device is present. Actually benefit - is not so clear to me. In other words we can provide more informations - to user, but this expects more complex flash handling we do not provide - now.*/ -#undef CFG_FLASH_CFI - -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ - -#define CFG_FLASH_BASE MX1FS2_FLASH_BASE - -/* - * This is setting for JFFS2 support in u-boot. - * Right now there is no gain for user, but later on booting kernel might be - * possible. Consider using XIP kernel running from flash to save RAM - * footprint. - * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. - */ - -/* - * JFFS2 partitions - */ -/* No command line, one static partition, whole device */ -/* -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00050000 -*/ - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=mx1fs2-0" - -#ifdef BUS32BIT_VERSION -#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:2m@5m(part0),5m@9m(part1)" -#else -#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:-@320k(jffs2)" -#endif - -/* - * Environment setup. Definitions of monitor location and size with - * definition of environment setup ends up in 2 possibilities. - * 1. Embeded environment - in u-boot code is space for environment - * 2. Environment is read from predefined sector of flash - * Right now we support 2. possiblity, but expecting no env placed - * on mentioned address right now. This also needs to provide whole - * sector for it - for us 256Kb is really waste of memory. U-boot uses - * default env. and until kernel parameters could be sent to kernel - * env. has no sense to us. - */ - -#define CFG_MONITOR_BASE 0x10000000 -#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */ -#define CFG_ENV_SIZE 0x20000 - -#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ - -/* Setup CS4 and CS5 */ -#define CFG_GIUS_A_VAL 0x0003fffe - -/* - * CSxU_VAL: - * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 - * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | - * - * CSxL_VAL: - * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 - * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| - */ - -#define CFG_CS0U_VAL 0x00008C00 -#define CFG_CS0L_VAL 0x22222601 -#define CFG_CS1U_VAL 0x00008C00 -#define CFG_CS1L_VAL 0x22222301 -#define CFG_CS4U_VAL 0x00008C00 -#define CFG_CS4L_VAL 0x22222301 -#define CFG_CS5U_VAL 0x00008C00 -#define CFG_CS5L_VAL 0x22222301 - -/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) - f_ref=16,777MHz - - 0x002a141f: 191,9944MHz - 0x040b2007: 144MHz - 0x042a141f: 96MHz - 0x0811140d: 64MHz - 0x040e200e: 150MHz - 0x00321431: 200MHz - - 0x08001800: 64MHz mit 16er Quarz - 0x04001800: 96MHz mit 16er Quarz - 0x04002400: 144MHz mit 16er Quarz - - 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 - |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ - -#define CFG_MPCTL0_VAL 0x07E723AD -#define CFG_MPCTL1_VAL 0x00000040 -#define CFG_PCDR_VAL 0x00010005 -#define CFG_GPCR_VAL 0x00000FFB - -#define USE_16M_OSZI /* If you have one, you want to use it - The internal 32kHz oszillator jitters */ -#ifdef USE_16M_OSZI - -#define CFG_SPCTL0_VAL 0x04001401 -#define CFG_SPCTL1_VAL 0x0C000040 -#define CFG_CSCR_VAL 0x07030003 -#define CONFIG_SYS_CLK_FREQ 16780000 -#define CONFIG_SYSPLL_CLK_FREQ 16000000 - -#else - -#define CFG_SPCTL0_VAL 0x07E716D1 -#define CFG_CSCR_VAL 0x06000003 -#define CONFIG_SYS_CLK_FREQ 16780000 -#define CONFIG_SYSPLL_CLK_FREQ 16780000 - -#endif - -/* - * Well this has to be defined, but on the other hand it is used differently - * one may expect. For instance loadb command do not cares :-) - * So advice is - do not relay on this... - */ -#define CFG_LOAD_ADDR 0x08400000 - -#define CFG_FMCR_VAL 0x00000003 /* Reset Default */ - -/* Bit[0:3] contain PERCLK1DIV for UART 1 - 0x000b00b ->b<- -> 192MHz/12=16MHz - 0x000b00b ->8<- -> 144MHz/09=16MHz - 0x000b00b ->3<- -> 64MHz/4=16MHz */ - -#ifdef _CONFIG_UART1 -#define CONFIG_IMX_SERIAL1 -#elif defined _CONFIG_UART2 -#define CONFIG_IMX_SERIAL2 -#elif defined _CONFIG_UART3 | defined _CONFIG_UART4 -#define CONFIG_IMX_SERIAL_NONE -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_CLK 3686400 -#define CFG_NS16550_REG_SIZE 1 -#define CONFIG_CONS_INDEX 1 -#ifdef _CONFIG_UART3 -#define CFG_NS16550_COM1 0x15000000 -#elif defined _CONFIG_UART4 -#define CFG_NS16550_COM1 0x16000000 -#endif -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h deleted file mode 100644 index 0b1541d..0000000 --- a/include/configs/ns9750dev.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * Markus Pietrek - * - * Configuation settings for the NetSilicon NS9750 DevBoard - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */ -#define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */ - -#define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2) -#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4) -#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8) - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -/*@TODO #define CONFIG_STATUS_LED*/ -#define CONFIG_USE_IRQ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial - * data */ - -/* - * Hardware drivers - */ -#define CFG_NS9750_UART 1 /* use on-chip UART */ -#define CONFIG_DRIVER_NS9750_ETHERNET 1 /* use on-chip ethernet */ - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 1 /* Port B */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 38400 - -/*********************************************************** - * Command definition - ***********************************************************/ -#if 0 /* @TODO */ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - /*CFG_CMD_NAND |*/ \ - /*CFG_CMD_EEPROM |*/ \ - /*CFG_CMD_I2C |*/ \ - /*CFG_CMD_USB |*/ \ - CFG_CMD_REGINFO | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF) -#else -#define CONFIG_COMMANDS \ - (CONFIG_CMD_BDI | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_CONSOLE | \ - CFG_CMD_LOADB | \ - CFG_CMD_LOADS | \ - CFG_CMD_MEMORY) -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ - -#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.42.30 -#define CONFIG_SERVERIP 192.168.42.1 - -/*#define CONFIG_BOOTFILE "elinos-lart" */ -/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "NS9750DEV # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM */ /* @TODO */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x00600000 /* default load address */ /* @TODO */ - -#define CFG_HZ (CPU_CLK_FREQ/64) - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define NS9750_ETH_PHY_ADDRESS (0x0000) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -/* TODO */ -#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ -#define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */ - -#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* @TODO*/ -#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ -#endif - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ - -/* @TODO */ -/*#define CFG_ENV_IS_IN_FLASH 1*/ -#define CFG_ENV_IS_NOWHERE -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ - -#ifdef CONFIG_STATUS_LED - -extern void __led_init(led_id_t mask, int state); -extern void __led_toggle(led_id_t mask); -extern void __led_set(led_id_t mask, int state); - -#endif /* CONFIG_STATUS_LED */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h deleted file mode 100644 index 5c05a74..0000000 --- a/include/configs/o2dnt.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 -#define CONFIG_O2DNT 1 /* ... on O2DNT board */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CFG_XLB_PIPELINING 1 - -#define CONFIG_NET_MULTI 1 -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 - -#define ADD_PCI_CMD CFG_CMD_PCI - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - ADD_PCI_CMD ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CFG_LOWBOOT 1 -#else -# error "TEXT_BASE must be 0xFF000000" -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/MPC5200/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if defined(CONFIG_MPC5200) -/* - * IPB Bus clocking configuration. - */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ - -#if defined(CFG_IPBSPEED_133) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. - */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ -#endif -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration: - * - * O2DNT board is equiped with Ramtron FRAM device FM24CL16 - * 16 Kib Ferroelectric Nonvolatile serial RAM memory - * organized as 2048 x 8 bits and addressable as eight I2C devices - * 0x50 ... 0x57 each 256 bytes in size - * - */ -#define CFG_I2C_FRAM -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -/* - * There is no write delay with FRAM, write operations are performed at bus - * speed. Thus, no status polling or write delay is needed. - */ -/*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70*/ - - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE 0xFF000000 -#define CFG_FLASH_SIZE 0x01000000 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) - -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ -#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x20000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -/*#define CFG_GPS_PORT_CONFIG 0x10002004 */ -#define CFG_GPS_PORT_CONFIG 0x00002006 /* no CAN */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE - -#ifdef CFG_PCISPEED_66 -/* - * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash). - */ -#define CFG_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */ -#else -#define CFG_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */ -#endif - -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0xff000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h deleted file mode 100644 index a13d6a8..0000000 --- a/include/configs/ocotea.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * (C) Copyright 2004 Paul Reynolds - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * 1 March 2004 Travis B. Sawyer - * Adapted to current Das U-Boot source - ***********************************************************************/ - - -/************************************************************************ - * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea) - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_OCOTEA 1 /* Board is ebony */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* Disable-takes long time! */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) -#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) -#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or NVRAM). - * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only - * supported for backward compatibility. - */ -#if 1 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#endif - - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -#ifdef CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_NVRAM */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_ADDR0 0x5555 -#define CFG_FLASH_ADDR1 0x2aaa -#define CFG_FLASH_WORD_SIZE unsigned char - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=ocotea\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/ocotea/uImage\0" \ - "kernel_addr=fff00000\0" \ - "ramdisk_addr=fff10000\0" \ - "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ -#define CONFIG_PHY1_ADDR 2 -#define CONFIG_PHY2_ADDR 0x10 -#define CONFIG_PHY3_ADDR 0x18 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_RESET_DELAY 1000 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT /* let board init pci target */ - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h deleted file mode 100644 index 6787b19..0000000 --- a/include/configs/omap1510.h +++ /dev/null @@ -1,790 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * OMAP hardware map - * - * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) - * Author: RidgeRun, Inc. - * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include - -/* - There are 2 sets of general I/O --> - 1. GPIO (shared between ARM & DSP, configured by ARM) - 2. MPUIO which can be used only by the ARM. - - Base address FFFB:5000 is where the ARM accesses the MPUIO control registers - (see 7.2.2 of the TRM for MPUIO reg definitions). - - Base address E101:5000 is reserved for ARM access of the same MPUIO control - regs, but via the DSP I/O map. This address is unavailable on 1510. - - Base address FFFC:E000 is where the ARM accesses the GPIO config registers - directly via its own peripheral bus. - - Base address E101:E000 is where the ARM can access the same GPIO config - registers, but the access takes place through the ARM port interface (called - API or MPUI) via the DSP's peripheral bus (DSP I/O space). - - Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses - instead of the E101:E000 addresses. The DSP has only read access of the pin - control register, so this may explain the inability to write to E101:E018. - Try accessing pin control reg at FFFC:E018. - */ -#define OMAP1510_GPIO_BASE 0xfffce000 -#define OMAP1510_GPIO_START OMAP1510_GPIO_BASE -#define OMAP1510_GPIO_SIZE SZ_4K - -#define OMAP1510_MCBSP1_BASE 0xE1011000 -#define OMAP1510_MCBSP1_SIZE SZ_4K -#define OMAP1510_MCBSP1_START 0xE1011000 - -#define OMAP1510_MCBSP2_BASE 0xFFFB1000 - -#define OMAP1510_MCBSP3_BASE 0xE1017000 -#define OMAP1510_MCBSP3_SIZE SZ_4K -#define OMAP1510_MCBSP3_START 0xE1017000 - -/* - * Where's the flush address (for flushing D and I cache?) - */ -#define FLUSH_BASE 0xdf000000 -#define FLUSH_BASE_PHYS 0x00000000 - -#ifndef __ASSEMBLER__ - -#define PCIO_BASE 0 - -/* - * RAM definitions - */ -#define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET) -#define KERNTOPHYS(a) ((unsigned long)(&a)) -#define KERNEL_BASE (0x10008000) -#endif - -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((x)) - -/* ---------------------------------------------------------------------------- - * OMAP1510 system registers - * ---------------------------------------------------------------------------- - */ - -#define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */ -#define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */ -#define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */ -#define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */ -#define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */ -#define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */ -#define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */ - -/* - * OMAP1510 UART3 Registers - */ - -#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ - -/* UART3 Registers Maping through MPU bus */ - -#define UART3_RHR (OMAP_MPU_UART3_BASE + 0) -#define UART3_THR (OMAP_MPU_UART3_BASE + 0) -#define UART3_DLL (OMAP_MPU_UART3_BASE + 0) -#define UART3_IER (OMAP_MPU_UART3_BASE + 4) -#define UART3_DLH (OMAP_MPU_UART3_BASE + 4) -#define UART3_IIR (OMAP_MPU_UART3_BASE + 8) -#define UART3_FCR (OMAP_MPU_UART3_BASE + 8) -#define UART3_EFR (OMAP_MPU_UART3_BASE + 8) -#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) -#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) -#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) -#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) -#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) -#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) -#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) -#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) -#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) - -/* - * Configuration Registers - */ -#define FUNC_MUX_CTRL_0 0xfffe1000 -#define FUNC_MUX_CTRL_1 0xfffe1004 -#define FUNC_MUX_CTRL_2 0xfffe1008 -#define COMP_MODE_CTRL_0 0xfffe100c -#define FUNC_MUX_CTRL_3 0xfffe1010 -#define FUNC_MUX_CTRL_4 0xfffe1014 -#define FUNC_MUX_CTRL_5 0xfffe1018 -#define FUNC_MUX_CTRL_6 0xfffe101C -#define FUNC_MUX_CTRL_7 0xfffe1020 -#define FUNC_MUX_CTRL_8 0xfffe1024 -#define FUNC_MUX_CTRL_9 0xfffe1028 -#define FUNC_MUX_CTRL_A 0xfffe102C -#define FUNC_MUX_CTRL_B 0xfffe1030 -#define FUNC_MUX_CTRL_C 0xfffe1034 -#define FUNC_MUX_CTRL_D 0xfffe1038 -#define PULL_DWN_CTRL_0 0xfffe1040 -#define PULL_DWN_CTRL_1 0xfffe1044 -#define PULL_DWN_CTRL_2 0xfffe1048 -#define PULL_DWN_CTRL_3 0xfffe104c -#define GATE_INH_CTRL_0 0xfffe1050 -#define VOLTAGE_CTRL_0 0xfffe1060 -#define TEST_DBG_CTRL_0 0xfffe1070 - -#define MOD_CONF_CTRL_0 0xfffe1080 - -#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */ - -#define USB_OTG_CTRL 0xFFFB040C -#define USB_TRANSCEIVER_CTRL 0xFFFE1064 -#define PULL_DWN_CTRL_4 0xFFFE10AC -#define PU_PD_SEL_0 0xFFFE10B4 -#define PU_PD_SEL_1 0xFFFE10B8 -#define PU_PD_SEL_2 0xFFFE10BC -#define PU_PD_SEL_3 0xFFFE10C0 -#define PU_PD_SEL_4 0xFFFE10C4 - -#endif -/* - * Traffic Controller Memory Interface Registers - */ -#define TCMIF_BASE 0xfffecc00 -#define IMIF_PRIO (TCMIF_BASE + 0x00) -#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04) -#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08) -#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c) -#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) -#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) -#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) -#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) -#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) -#define EMIFF_MRS (TCMIF_BASE + 0x24) -#define TC_TIMEOUT1 (TCMIF_BASE + 0x28) -#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) -#define TC_TIMEOUT3 (TCMIF_BASE + 0x30) -#define TC_ENDIANISM (TCMIF_BASE + 0x34) -#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) -#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) - -/* - * LCD Panel - */ -#define TI925_LCD_BASE 0xFFFEC000 -#define TI925_LCD_CONTROL (TI925_LCD_BASE) -#define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4) -#define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8) -#define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc) -#define TI925_LCD_STATUS (TI925_LCD_BASE+0x10) -#define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14) - -#define OMAP_LCD_CONTROL TI925_LCD_CONTROL - -/* I2C Registers */ - -#define I2C_BASE 0xfffb3800 - -#define I2C_REV (I2C_BASE + 0x00) -#define I2C_IE (I2C_BASE + 0x04) -#define I2C_STAT (I2C_BASE + 0x08) -#define I2C_IV (I2C_BASE + 0x0c) -#define I2C_BUF (I2C_BASE + 0x14) -#define I2C_CNT (I2C_BASE + 0x18) -#define I2C_DATA (I2C_BASE + 0x1c) -#define I2C_CON (I2C_BASE + 0x24) -#define I2C_OA (I2C_BASE + 0x28) -#define I2C_SA (I2C_BASE + 0x2c) -#define I2C_PSC (I2C_BASE + 0x30) -#define I2C_SCLL (I2C_BASE + 0x34) -#define I2C_SCLH (I2C_BASE + 0x38) -#define I2C_SYSTEST (I2C_BASE + 0x3c) - -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ - -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_AD0 (1 << 8) /* Address zero */ -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Interrupt Vector Register (I2C_IV): */ - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_RM (1 << 2) /* Repeat mode (master mode only) */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -/* - * MMC/SD Host Controller Registers - */ - -#define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */ -#define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */ -#define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */ -#define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */ -#define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */ -#define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */ -#define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */ -#define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */ -#define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */ -#define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */ -#define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */ -#define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */ -#define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */ -#define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */ -#define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */ -#define OMAP_MMC_REV 0xFFFB783C /* MMC module version */ -#define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */ -#define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */ -#define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */ -#define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */ -#define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */ -#define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */ -#define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */ -#define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */ - -/* MMC masks */ - -#define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */ -#define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */ -#define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */ -#define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */ -#define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */ -#define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */ -#define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */ -#define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */ -#define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */ -#define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */ -#define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */ -#define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */ -#define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */ - -/* 2.9.2 MPUI Interface Registers FFFE:C900 */ - -#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900) -#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904) -#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908) -#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c) -#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910) -#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914) -#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918) -#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c) - -/* 2.9.6 Traffic Controller Memory Interface Registers: */ -#define OMAP_IMIF_PRIO_REG 0xfffecc00 -#define OMAP_EMIFS_PRIO_REG 0xfffecc04 -#define OMAP_EMIFF_PRIO_REG 0xfffecc08 -#define OMAP_EMIFS_CONFIG_REG 0xfffecc0c -#define OMAP_EMIFS_CS0_CONFIG 0xfffecc10 -#define OMAP_EMIFS_CS1_CONFIG 0xfffecc14 -#define OMAP_EMIFS_CS2_CONFIG 0xfffecc18 -#define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c -#define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20 -#define OMAP_EMIFF_MRS 0xfffecc24 -#define OMAP_TIMEOUT1 0xfffecc28 -#define OMAP_TIMEOUT2 0xfffecc2c -#define OMAP_TIMEOUT3 0xfffecc30 -#define OMAP_ENDIANISM 0xfffecc34 - -/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */ -#define OMAP_EMIFS_CONFIG_FR (1 << 4) -#define OMAP_EMIFS_CONFIG_PDE (1 << 3) -#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) -#define OMAP_EMIFS_CONFIG_BM (1 << 1) -#define OMAP_EMIFS_CONFIG_WP (1 << 0) - -/* - * Memory chunk set aside for the Framebuffer in SRAM - */ -#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE - - -/* - * DMA - */ - -#define OMAP1510_DMA_BASE 0xFFFED800 -#define OMAP_DMA_BASE OMAP1510_DMA_BASE - -/* Global Register selection */ -#define NO_GLOBAL_DMA_ACCESS 0 - -/* Channel select field - * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc... - */ -#define LCD_CHANNEL 0xc - -/* Register Select Field (LCD) */ -#define DMA_LCD_CTRL 0 -#define DMA_LCD_TOP_F1_L 1 -#define DMA_LCD_TOP_F1_U 2 -#define DMA_LCD_BOT_F1_L 3 -#define DMA_LCD_BOT_F1_U 4 - -#define LCD_FRAME_MODE (1<<0) -#define LCD_FRAME_IT_IE (1<<1) -#define LCD_BUS_ERROR_IT_IE (1<<2) -#define LCD_FRAME_1_IT_COND (1<<3) -#define LCD_FRAME_2_IT_COND (1<<4) -#define LCD_BUS_ERROR_IT_COND (1<<5) -#define LCD_SOURCE_IMIF (1<<6) - -/* - * Real-Time Clock - */ - -#define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00) -#define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04) -#define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08) -#define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C) -#define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10) -#define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14) -#define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40) - - -/* --------------------------------------------------------------------------- - * OMAP1510 Interrupt Handlers - * --------------------------------------------------------------------------- - * - */ -#define OMAP_IH1_BASE 0xfffecb00 -#define OMAP_IH2_BASE 0xfffe0000 -#define OMAP1510_ITR 0x0 -#define OMAP1510_MASK 0x4 - -#define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE -#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR -#define INTERRUPT_MASK_REGISTER OMAP1510_MASK - - -/* --------------------------------------------------------------------------- - * OMAP1510 TIMERS - * --------------------------------------------------------------------------- - * - */ - -#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000 - -/* 32k Timer Registers */ -#define TIMER32k_CR 0x08 -#define TIMER32k_TVR 0x00 -#define TIMER32k_TCR 0x04 - -/* 32k Timer Control Register definition */ -#define TIMER32k_TSS (1<<0) -#define TIMER32k_TRB (1<<1) -#define TIMER32k_INT (1<<2) -#define TIMER32k_ARL (1<<3) - -/* MPU Timer base addresses */ -#define OMAP1510_MPUTIMER_BASE 0xfffec500 -#define OMAP1510_MPUTIMER_OFF 0x00000100 - -#define OMAP1510_TIMER1_BASE 0xfffec500 -#define OMAP1510_TIMER2_BASE 0xfffec600 -#define OMAP1510_TIMER3_BASE 0xfffec700 - -/* MPU Timer Registers */ -#define CNTL_TIMER 0 -#define LOAD_TIM 4 -#define READ_TIM 8 - -/* CNTL_TIMER register bits */ -#define MPUTIM_FREE (1<<6) -#define MPUTIM_CLOCK_ENABLE (1<<5) -#define MPUTIM_PTV_MASK (0x7< - * Configuation settings for the TI OMAP Innovator board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ -#define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -/* -#define CONFIG_DRIVER_SMC9196 -#define CONFIG_SMC9196_BASE 0x08000300 -#define CONFIG_SMC9196_EXT_PHY -*/ -#define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x08000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp" -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" -#define CFG_AUTOLOAD "n" /* No autoload */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. - * This time is further subdivided by a local divisor. - */ -#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ -#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ -#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + PHYS_FLASH_SECT_SIZE) -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ -#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE } - -/*----------------------------------------------------------------------- - * FLASH driver setup - */ -#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ -#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h deleted file mode 100644 index c6ca689..0000000 --- a/include/configs/omap1610h2.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Kshitij Gupta - * Configuration settings for the TI OMAP 1610 H2 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* which is in a 1610 */ -#define CONFIG_H2_OMAP1610 1 /* on an H2 Board */ -#define CONFIG_MACH_OMAP_H2 /* Select board mach-type */ - -/* input clock of PLL */ -/* the OMAP1610 H2 has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 H2 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp" -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" -#define CFG_AUTOLOAD "n" /* No autoload */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "OMAP1610 H2 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ -#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ - -#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ - -#ifndef __ASSEMBLY__ -extern unsigned long omap_flash_base; /* set in flash__init */ -#endif -#define CFG_FLASH_BASE omap_flash_base - -#elif defined(CONFIG_CS0_BOOT) - -#define CFG_FLASH_BASE PHYS_FLASH_1_BM0 - -#else - -#define CFG_FLASH_BASE PHYS_FLASH_1_BM1 - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -/* addr of environment */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h deleted file mode 100644 index f28ede0..0000000 --- a/include/configs/omap1610inn.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta - * Configuation settings for the TI OMAP Innovator board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* which is in a 1610 */ -#define CONFIG_INNOVATOROMAP1610 1 /* a Innovator Board */ -#define CONFIG_MACH_OMAP_INNOVATOR /* Select board mach-type */ - -/* input clock of PLL */ -/* the OMAP1610 Innovator has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -/* -*/ -#define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 Innovator */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ - root=/dev/nfs rw nfsroot=157.87.82.48:\ - /home/a0875451/mwd/myfs/target ip=dhcp" -#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ -#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ -#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ -#define CONFIG_BOOTFILE "uImage" /* file to load */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "OMAP1610 Innovator # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ -#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ - -#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ - -#ifndef __ASSEMBLY__ -extern unsigned long omap_flash_base; /* set in flash__init */ -#endif -#define CFG_FLASH_BASE omap_flash_base - -#elif defined(CONFIG_CS0_BOOT) - -#define CFG_FLASH_BASE PHYS_FLASH_1_BM0 - -#else - -#define CFG_FLASH_BASE PHYS_FLASH_1_BM1 - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -/* addr of environment */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h deleted file mode 100644 index 12252ac..0000000 --- a/include/configs/omap2420h4.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Richard Woodruff - * Kshitij Gupta - * - * Configuration settings for the 242x TI H4 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP2420 1 /* which is in a 2420 */ -#define CONFIG_OMAP2420H4 1 /* and on a H4 board */ -/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */ -/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ - -/* Clock config to target*/ -#define PRCM_CONFIG_II 1 -/* #define PRCM_CONFIG_III 1 */ - -#include /* get chip and board defs */ - -/* On H4, NOR and NAND flash are mutual exclusive. - Define this if you want to use NAND - */ -/*#define CFG_NAND_BOOT */ - -#ifdef CONFIG_APTIX -#define V_SCLK 1500000 -#else -#define V_SCLK 12000000 -#endif - -/* input clock of PLL */ -/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ -#define CONFIG_SYS_CLK_FREQ V_SCLK - -#undef CONFIG_USE_IRQ /* no support for IRQs */ -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -/* - * Size of malloc() pool - */ -#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ - -/* - * SMC91c96 Etherent - */ -#define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300) -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#ifdef CONFIG_APTIX -#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */ -#else -#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ -#endif - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ -#define CFG_NS16550_COM1 OMAP2420_UART1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* UART1 on H4 */ - - /* - * I2C configuration - */ -#define CONFIG_HARD_I2C -#define CFG_I2C_SPEED 100000 -#define CFG_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP24XX_I2C - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} - -#ifdef CFG_NAND_BOOT -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) -#endif -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Board NAND Info. - */ -#define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) -#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0) -#define READ_NAND(adr) (*(volatile u16 *)0x6800A084) -#define NAND_WAIT_READY(nand) udelay(10) - -#define NAND_NO_RB 1 - -#define CFG_NAND_WP -#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0) -#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0) - -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) - -#define CONFIG_BOOTDELAY 3 - -#ifdef NFS_BOOT_DEFAULTS -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp" -#else -#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" -#endif - -#define CONFIG_NETMASK 255.255.254.0 -#define CONFIG_IPADDR 128.247.77.90 -#define CONFIG_SERVERIP 128.247.77.158 -#define CONFIG_BOOTFILE "uImage" - -/* - * Miscellaneous configurable options - */ -#ifdef CONFIG_APTIX -#define V_PROMPT "OMAP2420 Aptix # " -#else -#define V_PROMPT "OMAP242x H4 # " -#endif - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT V_PROMPT -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ -#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ - -/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. - */ -#ifdef CONFIG_APTIX -#define V_PVT 3 -#else -#define V_PVT 7 /* use with 12MHz/128 */ -#endif - -#define CFG_TIMERBASE OMAP2420_GPT2 -#define CFG_PVT V_PVT /* 2^(pvt+1) */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ -#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 - -#define PHYS_FLASH_SECT_SIZE SZ_128K -#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE_1 SZ_32M -#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */ -#define PHYS_FLASH_SIZE_2 SZ_32M - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ -#define CFG_MONITOR_LEN SZ_128K /* Reserve 1 sector */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 } - -#ifdef CFG_NAND_BOOT -#define CFG_ENV_IS_IN_NAND 1 -#define CFG_ENV_OFFSET 0x80000 /* environment starts here */ -#else -#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K) -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ -#endif - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_JFFS2_MEM_NAND - -/* - * JFFS2 partitions - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor1=omap2420-1" -#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h deleted file mode 100644 index 605563a..0000000 --- a/include/configs/omap5912osk.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta - * Configuation settings for the TI OMAP Innovator board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */ -#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */ - -/* input clock of PLL */ -/* the OMAP5912 OSK has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -/* -*/ -#define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04800300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart - on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ - root=/dev/nfs rw nfsroot=157.87.82.48:\ - /home/mwd/myfs/target ip=dhcp" -#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ -#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ -#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ -#define CONFIG_BOOTFILE "uImage" /* file to load */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -/* addr of environment */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap730.h b/include/configs/omap730.h deleted file mode 100644 index 03abcb3..0000000 --- a/include/configs/omap730.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * OMAP730 hardware map - * - * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk) - * Author: MPC-Data Limited - * Dave Peverley - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __INCLUDED_OMAP730_H -#define __INCLUDED_OMAP730_H - -#include - -/*************************************************************************** - * OMAP730 Configuration Registers - **************************************************************************/ - -#define PERSEUS2_MPU_DEV_ID ((unsigned int)(0xFFFE1000)) -#define PERSEUS2_GSM_DEV_ID0 ((unsigned int)(0xFFFE1000)) -#define PERSEUS2_GDM_DEV_ID1 ((unsigned int)(0xFFFE1002)) -#define DSP_CONF ((unsigned int)(0xFFFE1004)) -#define PERSEUS2_MPU_DIE_ID0 ((unsigned int)(0xFFFE1008)) -#define GSM_ASIC_CONF ((unsigned int)(0xFFFE1008)) -#define PERSEUS2_MPU_DIE_ID1 ((unsigned int)(0xFFFE100C)) -#define PERSEUS2_MODE1 ((unsigned int)(0xFFFE1010)) -#define PERSEUS2_GSM_DIE_ID0 ((unsigned int)(0xFFFE1010)) -#define PERSEUS2_GSM_DIE_ID1 ((unsigned int)(0xFFFE1012)) -#define PERSEUS2_MODE2 ((unsigned int)(0xFFFE1014)) -#define PERSEUS2_GSM_DIE_ID2 ((unsigned int)(0xFFFE1014)) -#define PERSEUS2_GSM_DIE_ID3 ((unsigned int)(0xFFFE1016)) -#define PERSEUS2_ANALOG_CELLS_CONF ((unsigned int)(0xFFFE1018)) -#define SPECCTL ((unsigned int)(0xFFFE101C)) -#define SPARE1 ((unsigned int)(0xFFFE1020)) -#define SPARE2 ((unsigned int)(0xFFFE1024)) -#define GSM_PBG_IRQ ((unsigned int)(0xFFFE1028)) -#define DMA_REQ_CONF ((unsigned int)(0xFFFE1030)) -#define PE_CONF_NO_DUAL ((unsigned int)(0xFFFE1060)) -#define PERSEUS2_IO_CONF0 ((unsigned int)(0xFFFE1070)) -#define PERSEUS2_IO_CONF1 ((unsigned int)(0xFFFE1074)) -#define PERSEUS2_IO_CONF2 ((unsigned int)(0xFFFE1078)) -#define PERSEUS2_IO_CONF3 ((unsigned int)(0xFFFE107C)) -#define PERSEUS2_IO_CONF4 ((unsigned int)(0xFFFE1080)) -#define PERSEUS2_IO_CONF5 ((unsigned int)(0xFFFE1084)) -#define PERSEUS2_IO_CONF6 ((unsigned int)(0xFFFE1088)) -#define PERSEUS2_IO_CONF7 ((unsigned int)(0xFFFE108C)) -#define PERSEUS2_IO_CONF8 ((unsigned int)(0xFFFE1090)) -#define PERSEUS2_IO_CONF9 ((unsigned int)(0xFFFE1094)) -#define PERSEUS2_IO_CONF10 ((unsigned int)(0xFFFE1098)) -#define PERSEUS2_IO_CONF11 ((unsigned int)(0xFFFE109C)) -#define PERSEUS2_IO_CONF12 ((unsigned int)(0xFFFE10A0)) -#define PERSEUS2_IO_CONF13 ((unsigned int)(0xFFFE10A4)) -#define PERSEUS_PCC_CONF_REG ((unsigned int)(0xFFFE10B4)) -#define BIST_STATUS_INTERNAL ((unsigned int)(0xFFFE10B8)) -#define BIST_CONTROL ((unsigned int)(0xFFFE10C0)) -#define BOOT_ROM_REG ((unsigned int)(0xFFFE10C4)) -#define PRODUCTION_ID_REG ((unsigned int)(0xFFFE10C8)) -#define BIST_SECROM_SIGNATURE1_INTERNAL ((unsigned int)(0xFFFE10D0)) -#define BIST_SECROM_SIGNATURE2_INTERNAL ((unsigned int)(0xFFFE10D4)) -#define BIST_CONTROL_2 ((unsigned int)(0xFFFE10D8)) -#define DEBUG1 ((unsigned int)(0xFFFE10E0)) -#define DEBUG2 ((unsigned int)(0xFFFE10E4)) -#define DEBUG_DMA_IRQ ((unsigned int)(0xFFFE10E8)) - -/*************************************************************************** - * OMAP730 EMIFS Registers (TRM 2.5.7) - **************************************************************************/ - -#define TCMIF_BASE 0xFFFECC00 - -#define EMIFS_LRUREG (TCMIF_BASE + 0x04) -#define EMIFS_CONFIG (TCMIF_BASE + 0x0C) -#define FLASH_CFG_0 (TCMIF_BASE + 0x10) -#define FLASH_CFG_1 (TCMIF_BASE + 0x14) -#define FLASH_CFG_2 (TCMIF_BASE + 0x18) -#define FLASH_CFG_3 (TCMIF_BASE + 0x1C) -#define FL_CFG_DYN_WAIT (TCMIF_BASE + 0x40) -#define EMIFS_TIMEOUT1_REG (TCMIF_BASE + 0x28) -#define EMIFS_TIMEOUT2_REG (TCMIF_BASE + 0x2C) -#define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30) -#define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44) -#define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48) -#define EMIFS_ABORT_TOUT (TCMIF_BASE + 0x4C) -#define FLASH_ACFG_0_1 (TCMIF_BASE + 0x50) -#define FLASH_ACFG_1_1 (TCMIF_BASE + 0x54) -#define FLASH_ACFG_2_1 (TCMIF_BASE + 0x58) -#define FLASH_ACFG_3_1 (TCMIF_BASE + 0x5C) - -/*************************************************************************** - * OMAP730 Interrupt handlers - **************************************************************************/ - -#define OMAP_IH1_BASE 0xFFFECB00 /* MPU Level 1 IRQ handler */ -#define OMAP_IH2_BASE 0xfffe0000 - -/*************************************************************************** - * OMAP730 Timers - * - * There are three general purpose OS timers in the 730 that can be - * configured in autoreload or one-shot modes. - **************************************************************************/ - -#define OMAP730_32kHz_TIMER_BASE 0xFFFB9000 - -/* 32k Timer Registers */ -#define TIMER32k_CR 0x08 -#define TIMER32k_TVR 0x00 -#define TIMER32k_TCR 0x04 - -/* 32k Timer Control Register definition */ -#define TIMER32k_TSS (1<<0) -#define TIMER32k_TRB (1<<1) -#define TIMER32k_INT (1<<2) -#define TIMER32k_ARL (1<<3) - -/* MPU Timer base addresses */ -#define OMAP730_MPUTIMER_BASE 0xfffec500 -#define OMAP730_MPUTIMER_OFF 0x00000100 - -#define OMAP730_TIMER1_BASE 0xFFFEC500 -#define OMAP730_TIMER2_BASE 0xFFFEC600 -#define OMAP730_TIMER3_BASE 0xFFFEC700 - -/* MPU Timer Register offsets */ -#define CNTL_TIMER 0x00 /* MPU_CNTL_TIMER */ -#define LOAD_TIM 0x04 /* MPU_LOAD_TIMER */ -#define READ_TIM 0x08 /* MPU_READ_TIMER */ - -/* MPU_CNTL_TIMER register bits */ -#define MPUTIM_FREE (1<<6) -#define MPUTIM_CLOCK_ENABLE (1<<5) -#define MPUTIM_PTV_MASK (0x7< - * - * Configuation settings for the TI OMAP Perseus 2 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP730 1 /* which is in a 730 */ -#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */ - -/* - * Input clock of PLL - * The OMAP730 Perseus 2 has 13MHz input clock - */ - -#define CONFIG_SYS_CLK_FREQ 13000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 - -/* - * Size of malloc() pool - */ - -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ - -#define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (1) -#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart - * on perseus */ - -/* - * select serial console configuration - */ - -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* - * This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ - -#include -#include -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp" - -#define CONFIG_LOADADDR 0x10000000 - -#define CONFIG_ETHADDR -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.23 -#define CONFIG_SERVERIP 192.150.0.100 -#define CONFIG_BOOTFILE "uImage" /* File to load */ - -#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x10000000 /* default load address */ - -/* The OMAP730 has 3 general purpose MPU timers, they can be driven by - * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a - * local divisor. - */ - -#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ - -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#if defined(CONFIG_CS0_BOOT) -#define PHYS_FLASH_1 0x0C000000 -#elif defined(CONFIG_CS3_BOOT) -#define PHYS_FLASH_1 0x00000000 -#else -#error Unknown Boot Chip-Select number -#endif - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -/* addr of environment */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ - -#endif /* ! __CONFIG_H */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h deleted file mode 100644 index 831d018..0000000 --- a/include/configs/p3p440.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * board/config_p3p440.h - configuration for Prodrive P3P440 - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_P3P440 1 /* Board is P3P440 */ -#define CONFIG_440GP 1 /* Specifc GP support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CFG_USB_BASE (CFG_PERIPHERAL_BASE + 0x00000000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ - -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ -#define CFG_SDRAM_TABLE { \ - {(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \ - {(64 << 20), 0x00082001}} /* 64MB mode 2, 12x9(4) */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CFG_EXT_SERIAL_CLOCK -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * I2C RTC - *----------------------------------------------------------------------*/ -#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (PCF8594C) for environment - *----------------------------------------------------------------------*/ -#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ - /* 8 byte page write mode using */ - /* last 3 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/*----------------------------------------------------------------------- - * Default configuration (environment varibles...) - *----------------------------------------------------------------------*/ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=p3p440\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/p3p440/uImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ff810000\0" \ - "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0x1c /* PHY address */ -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT /* let board init pci target */ - -#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - *----------------------------------------------------------------------*/ -#define CFG_FLASH0 0xFF800000 -#define CFG_FLASH1 0xFF000000 -#define CFG_FLASH2 0xFE800000 -#define CFG_FLASH3 0xFE000000 -#define CFG_USB 0xF0000000 - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x03050200 -#define CFG_EBC_PB0CR (CFG_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */ -#define CFG_EBC_PB1AP 0x03050200 -#define CFG_EBC_PB1CR (CFG_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */ -#define CFG_EBC_PB2AP 0x03050200 -#define CFG_EBC_PB2CR (CFG_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */ -#define CFG_EBC_PB3AP 0x03050200 -#define CFG_EBC_PB3CR (CFG_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 7 (USB controller) initialization */ -#define CFG_EBC_PB7AP 0x02015000 -#define CFG_EBC_PB7CR (CFG_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 } - -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h deleted file mode 100644 index ed1893f..0000000 --- a/include/configs/pb1x00.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file contains the configuration parameters for the dbau1x00 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ -#define CONFIG_PB1X00 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ - -#ifdef CONFIG_PB1000 -#define CONFIG_AU1000 1 -#else -#ifdef CONFIG_PB1100 -#define CONFIG_AU1100 1 -#else -#ifdef CONFIG_PB1500 -#define CONFIG_AU1500 1 -#else -#error "No valid board set" -#endif -#endif -#endif - -#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ - -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ - -#define CONFIG_BAUDRATE 115200 - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "panic=1\0" \ - "bootfile=/vmlinux.img\0" \ - "load=tftp 80500000 ${u-boot}\0" \ - "" -/* Boot from NFS root */ -#define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm" - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "Pb1x00 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args*/ - -#define CFG_MALLOC_LEN 128*1024 - -#define CFG_BOOTPARAMS_LEN 128*1024 - -#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */ - -#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ - -#define CFG_LOAD_ADDR 0x81000000 /* default load address */ - -#define CFG_MEMTEST_START 0x80100000 -#undef CFG_MEMTEST_START -#define CFG_MEMTEST_START 0x80200000 -#define CFG_MEMTEST_END 0x83800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ - -/* The following #defines are needed to get flash environment right */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) - -#define CFG_INIT_SP_OFFSET 0x4000000 - -/* We boot from this flash, selected with dip switch */ -#define CFG_FLASH_BASE PHYS_FLASH_2 - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_NOWHERE 1 - -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR 0xB0030000 -#define CFG_ENV_SIZE 0x10000 - -#define CONFIG_FLASH_16BIT - -#define CONFIG_NR_DRAM_BANKS 2 - -#define CONFIG_NET_MULTI - -#define CONFIG_MEMSIZE_IN_BYTES - - -/*---USB -------------------------------------------*/ -#if 0 -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#else -#define ADD_USB_CMD 0 -#endif - -/*---ATA PCMCIA ------------------------------------*/ -#if 0 -#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ -#define CFG_PCMCIA_MEM_ADDR 0x20000000 -#define CONFIG_PCMCIA_SLOT_A - -#define CONFIG_ATAPI 1 -#define CONFIG_MAC_PARTITION 1 - -/* We run CF in "true ide" mode or a harddrive via pcmcia */ -#define CONFIG_IDE_PCMCIA 1 - -/* We only support one slot for now */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET 8 - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET 0 - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -#endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_ICACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 - -#define CONFIG_COMMANDS \ - (((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_PING) & \ - ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | CFG_CMD_IDE | \ - CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \ - CFG_CMD_BDI | CFG_CMD_BEDBUG)) | ADD_USB_CMD) -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h deleted file mode 100644 index 73aa3a8..0000000 --- a/include/configs/pcu_e.h +++ /dev/null @@ -1,539 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Workaround for layout bug on prototype board - */ -#define PCU_E_WITH_SWAPPED_CS 1 - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860T CPU */ -#define CONFIG_MPC860T 1 -#define CONFIG_PCU_E 1 /* ...on a PCU E board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ - -#define CONFIG_BAUDRATE 9600 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_SPI /* enable SPI driver */ -#define CONFIG_SPI_X /* 16 bit EEPROM addressing */ - -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - - -/* ---------------------------------------------------------------- - * Offset to initial SPI buffers in DPRAM (used if the environment - * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to - * use at an early stage. It is used between the two initialization - * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it - * far enough from the start of the data area (as well as from the - * stack pointer). - * ---------------------------------------------------------------- */ -#define CFG_SPI_INIT_OFFSET 0xB00 - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -#define CONFIG_BOOTP_MASK \ - ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------*/ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ - -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -/* Ethernet hardware configuration done using port pins */ -#define CFG_PB_ETH_RESET 0x00000020 /* PB 26 */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */ -#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ -#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */ -#define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */ -#define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */ -#else /* XXX */ -#define CFG_PB_ETH_MDDIS 0x00000010 /* PB 27 */ -#define CFG_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */ -#define CFG_PB_ETH_CFG1 0x00000200 /* PB 22 */ -#define CFG_PB_ETH_CFG2 0x00000400 /* PB 21 */ -#define CFG_PB_ETH_CFG3 0x00000800 /* PB 20 */ -#endif /* XXX */ - -/* Ethernet settings: - * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex - */ -#define CFG_ETH_MDDIS_VALUE 0 -#define CFG_ETH_CFG1_VALUE 1 -#define CFG_ETH_CFG2_VALUE 1 -#define CFG_ETH_CFG3_VALUE 1 - -/* PUMA configuration */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_PB_PUMA_PROG 0x00000010 /* PB 27 */ -#else /* XXX */ -#define CFG_PA_PUMA_PROG 0x4000 /* PA 1 */ -#endif /* XXX */ -#define CFG_PC_PUMA_DONE 0x0008 /* PC 12 */ -#define CFG_PC_PUMA_INIT 0x0004 /* PC 13 */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFE000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Address accessed to reset the board - must not be mapped/assigned - */ -#define CFG_RESET_ADDRESS 0xFEFFFFFF - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -/* this is an ugly hack needed because of the silly non-constant address map */ -#define CFG_FLASH_BASE (0-flash_info[0].size-flash_info[1].size) - -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 160 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to SPI EEPROM later */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */ -#define CFG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */ -#define CFG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */ -#else -/* Final version: environment in EEPROM */ -#define CFG_ENV_IS_IN_EEPROM 1 -#define CFG_I2C_EEPROM_ADDR 0 -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_ENV_OFFSET 1024 -#define CFG_ENV_SIZE 1024 -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * External Arbitration max. priority (7), - * Debug pins configuration '11', - * Asynchronous external master enable. - */ -/* => 0x70600200 */ -#define CFG_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00004080 */ -#define CFG_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */ -#define CFG_PLPRCR \ - ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ - ) - -#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*50000000) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800000 */ -#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD100 | \ - SCCR_DFALCD01) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - * - * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!! - * - * Don't expect the "date" command to work without a 32kHz clock input! - */ -/* 0x00C3 => 0x0003 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0x0000 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CFG_RMDS 0 - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - second Flash bank optional - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */ -#else /* XXX */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */ -#endif /* XXX */ - -/* - * used to re-map FLASH: restrict access enough but not too much to - * meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR) - -#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \ - CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ - CFG_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_OR6_REMAP CFG_OR0_REMAP -#define CFG_OR6_PRELIM CFG_OR0_PRELIM -#define CFG_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) -#else /* XXX */ -#define CFG_OR1_REMAP CFG_OR0_REMAP -#define CFG_OR1_PRELIM CFG_OR0_PRELIM -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) -#endif /* XXX */ - -/* - * BR2/OR2: SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */ -#else /* XXX */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */ -#endif /* XXX */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */ -#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CFG_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* XXX */ -#define CFG_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#endif /* XXX */ - -/* - * BR3/OR3: CAN Controller - * BR3: 0x10000401 OR3: 0xffff818a - */ -#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */ -#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */ -#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CFG_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) -#else /* XXX */ -#define CFG_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CFG_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) -#endif /* XXX */ - -/* - * BR4/OR4: PUMA Config - * - * Memory controller will be used in 2 modes: - * - * - "read" mode: - * BR4: 0x10100801 OR4: 0xffff8530 - * - "load" mode (chip select on UPM B): - * BR4: 0x101008c1 OR4: 0xffff8630 - * - * Default initialization is in "read" mode - */ -#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */ -#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */ -#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK) -#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK) - -#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \ - BR_PS_16 | BR_MS_UPMB | BR_V) -#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING) - -#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_BR3_PRELIM PUMA_CONF_BR_READ -#define CFG_OR3_PRELIM PUMA_CONF_OR_READ -#else /* XXX */ -#define CFG_BR4_PRELIM PUMA_CONF_BR_READ -#define CFG_OR4_PRELIM PUMA_CONF_OR_READ -#endif /* XXX */ - -/* - * BR5/OR5: PUMA: SMA Bus 8 Bit - * BR5: 0x10200401 OR5: 0xffe0010a - */ -#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */ -#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */ -#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) -#else /* XXX */ -#define CFG_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CFG_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) -#endif /* XXX */ - -/* - * BR6/OR6: PUMA: SMA Bus 16 Bit - * BR6: 0x10600801 OR6: 0xffe0010a - */ -#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */ -#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */ -#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CFG_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CFG_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) -#else /* XXX */ -#define CFG_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CFG_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) -#endif /* XXX */ - -/* - * BR7/OR7: PUMA: external Flash - * BR7: 0x10a00801 OR7: 0xfe00010a - */ -#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */ -#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */ -#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#define CFG_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CFG_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MPTPR 0x0200 - -/* - * MAMR settings for SDRAM - * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10, - * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X - * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X - */ -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 0x30 /* = 48 */ - -#define CFG_MAMR ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \ - MAMR_AMA_TYPE_1 | \ - MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | \ - MAMR_WLFA_1X | \ - MAMR_TLFA_8X ) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h deleted file mode 100644 index fefdb3c..0000000 --- a/include/configs/pf5200.h +++ /dev/null @@ -1,399 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************* - * (c) 2005 esd gmbh Hannover - * - * - * from IceCube.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - *************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_ICECUBE 1 /* ... on IceCube board */ -#define CONFIG_PF5200 1 /* ... on PF5200 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#if 0 /* test-only */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#else -#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ -#endif -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_MII 1 -#if 0 /* test-only !!! */ -#define CONFIG_NET_MULTI 1 -#define CONFIG_EEPRO100 1 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif - -#define ADD_PCI_CMD CFG_CMD_PCI - -#else /* MPC5100 */ - -#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* USB */ -#if 0 -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_BSP | \ - CFG_CMD_ELF | \ - ADD_PCI_CMD ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT16 1 -#endif -#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ -# define CFG_LOWBOOT 1 -# define CFG_LOWBOOT08 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome to ParaFinder pf5200;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ - "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ - "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ - "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ - "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ - "loadaddr=01000000\0" \ - "serverip=192.168.2.99\0" \ - "gatewayip=10.0.0.79\0" \ - "user=mu\0" \ - "target=pf5200.esd\0" \ - "script=pf5200.bat\0" \ - "image=/tftpboot/vxWorks_pf5200\0" \ - "ipaddr=10.0.13.196\0" \ - "netmask=255.255.0.0\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_vxworks0" - -#if defined(CONFIG_MPC5200) -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ -#endif -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 86000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_MULTI_EEPROMS 1 -/* - * Flash configuration - */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_SIZE 0x02000000 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 512 - -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* - * Environment settings - */ -#if 1 /* test-only */ -#define CFG_ENV_IS_IN_FLASH 0 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 -#else -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ - /* total size of a CAT24WC32 is 8192 bytes */ -#define CONFIG_ENV_OVERWRITE 1 -#endif - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_UDP_CHECKSUM 1 - -/* - * GPIO configuration - */ -#define CFG_GPS_PORT_CONFIG 0x01052444 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x0004DD00 - -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -#define CFG_CS1_START 0xfd000000 -#define CFG_CS1_SIZE 0x00010000 -#define CFG_CS1_CFG 0x10101410 - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 - -#define CFG_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -/*----------------------------------------------------------------------- - * CPLD stuff - */ -#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - -/* CPLD program pin configuration */ -#define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ -#define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ -#define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ - -#define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ -#define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ -#define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ - -#define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00) -#define JTAG_GPIO_CFG_SET 0x00000000 -#define JTAG_GPIO_CFG_RESET 0x00F00000 - -#define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04) -#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TMS_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C) -#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TMS_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00) -#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ -#define JTAG_GPIO_TCK_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08) -#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ -#define JTAG_GPIO_TCK_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00) -#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDI_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08) -#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ -#define JTAG_GPIO_TDI_DDR_RESET 0x00000000 - -#define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04) -#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ -#define JTAG_GPIO_TDO_EN_RESET 0x00000000 -#define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C) -#define JTAG_GPIO_TDO_DDR_SET 0x00000000 -#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h deleted file mode 100644 index a6c2371..0000000 --- a/include/configs/pleb2.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuration settings for the PLEB 2 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA255 CPU */ -#define CONFIG_PLEB2 1 /* on an PLEB2 Board */ -#undef CONFIG_LCD -#undef CONFIG_MMC -#define BOARD_LATE_INIT 1 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ - -/* None - PLEB 2 doesn't have any of this. - #define CONFIG_DRIVER_LAN91C96 - #define CONFIG_LAN91C96_BASE 0x0C000000 */ - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART on PLEB 2 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.0.21 -#define CONFIG_SERVERIP 192.168.0.250 -#define CONFIG_BOOTCOMMAND "bootm 40000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200" - -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xa2000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 4 MB */ - -/* Not entirely sure about this - DS/CHC */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ - -#define CFG_DRAM_BASE PHYS_SDRAM_1 -#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE - -#define CFG_FLASH_BASE PHYS_FLASH_1 -#define CFG_MONITOR_BASE CFG_FLASH_BASE - -/* - * GPIO settings - */ -#define CFG_GPSR0_VAL 0x00000000 /* Don't set anything */ -#define CFG_GPSR1_VAL 0x00000080 -#define CFG_GPSR2_VAL 0x00000000 - -#define CFG_GPCR0_VAL 0x00000000 /* Don't clear anything */ -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 - -#define CFG_GPDR0_VAL 0x00000000 -#define CFG_GPDR1_VAL 0x000007C3 -#define CFG_GPDR2_VAL 0x00000000 - -/* Edge detect registers (these are set by the kernel) */ -#define CFG_GRER0_VAL 0x00000000 -#define CFG_GRER1_VAL 0x00000000 -#define CFG_GRER2_VAL 0x00000000 -#define CFG_GFER0_VAL 0x00000000 -#define CFG_GFER1_VAL 0x00000000 -#define CFG_GFER2_VAL 0x00000000 - -#define CFG_GAFR0_L_VAL 0x00000000 -#define CFG_GAFR0_U_VAL 0x00000000 -#define CFG_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */ -#define CFG_GAFR1_U_VAL 0x00000000 -#define CFG_GAFR2_L_VAL 0x00000000 -#define CFG_GAFR2_U_VAL 0x00000000 - -#define CFG_PSSR_VAL 0x20 -#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ -#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ -#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ - -/* - * Memory settings - */ -#define CFG_MSC0_VAL 0x00007FF0 /* Not properly calculated - FIXME (DS) */ -#define CFG_MSC1_VAL 0x00000000 -#define CFG_MSC2_VAL 0x00000000 - -#define CFG_MDCNFG_VAL 0x00000aC9 /* Memory timings for the SDRAM. - tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */ - -#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual */ - /* bits set in lowlevel_init.S */ -#define CFG_MDMRS_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000000 /* Hangover from Lubbock. - Needs calculating. (DS/CHC) */ -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -/* FIXME */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - -/* Flash protection */ -#define CFG_FLASH_PROTECTION 1 - -/* FIXME */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x3C000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x20000 - -/* Option added to get around byte ordering issues in the flash driver */ -#define CFG_LITTLE_ENDIAN 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h deleted file mode 100644 index 7579222..0000000 --- a/include/configs/ppmc8260.h +++ /dev/null @@ -1,1006 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * Configuation settings for the WindRiver PPMC8260 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/***************************************************************************** - * - * These settings must match the way _your_ board is set up - * - *****************************************************************************/ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 - * ------- ---------- --- --- ---- ----- ----- ----- - * 0x2 0x2 33 133 133 Close Open Close - * 0x2 0x3 33 133 166 Close Open Open - * 0x2 0x4 33 133 200 Open Close Close - * 0x2 0x5 33 133 233 Open Close Open - * 0x2 0x6 33 133 266 Open Open Close - * - * 0x5 0x5 66 133 133 Open Close Open - * 0x5 0x6 66 133 166 Open Open Close - * 0x5 0x7 66 133 200 Open Open Open - * 0x6 0x0 66 133 233 Close Close Close - * 0x6 0x1 66 133 266 Close Close Open - * 0x6 0x2 66 133 300 Close Open Close - */ -#define CFG_PPMC_MODCK_H 0x05 - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CFG_PPMC_BOOT_LOW 1 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#define CFG_FLASH0_BASE 0xFE000000 -#define CFG_FLASH0_SIZE 16 - -/* What should be the base address of the first SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CFG_SDRAM0_BASE 0x00000000 -#define CFG_SDRAM0_SIZE 128 - -/* What should be the base address of the second SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CFG_SDRAM1_BASE 0x08000000 -#define CFG_SDRAM1_SIZE 128 - -/* What should be the base address of the on board SDRAM and how big is - * it (in Mbytes)? -*/ -#define CFG_SDRAM2_BASE 0x38000000 -#define CFG_SDRAM2_SIZE 16 - -/* What should be the base address of the MAILBOX and how big is it - * (in Bytes) - * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000 - */ -#define CFG_MAILBOX_BASE 0x32000000 -#define CFG_MAILBOX_SIZE 8192 - -/* What is the base address of the I/O select lines and how big is it - * (In Mbytes)? - */ - -#define CFG_IOSELECT_BASE 0xE0000000 -#define CFG_IOSELECT_SIZE 32 - - -/* What should be the base address of the LEDs and switch S0? - * If you don't want them enabled, don't define this. - */ -#define CFG_LED_BASE 0xF1000000 - -/* - * PPMC8260 with 256 16 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x0FF5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x0FF5 FFB0 Board Info Data - * 0x0FF6 0000 Malloc Arena - * : CFG_ENV_SECT_SIZE, 256k - * : CFG_MALLOC_LEN, 128k - * 0x0FFC 0000 RAM Copy of Monitor Code - * : CFG_MONITOR_LEN, 256k - * 0x0FFF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 - */ - - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - * The console can be on SMC1 or SMC2 - */ -#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ - -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CFG_ENV_IN_OWN_SECT 1 - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 9600 - -/* Ethernet MAC address */ - -#define CONFIG_ETHADDR 00:a0:1e:90:2b:00 - -/* Define this to set the last octet of the ethernet address - * from the DS0-DS7 switch and light the leds with the result - * The DS0-DS7 switch and the leds are backwards with respect - * to each other. DS7 is on the board edge side of both the - * led strip and the DS0-DS7 switch. - */ -#define CONFIG_MISC_INIT_R - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#if 0 -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -# define CONFIG_AUTOBOOT_KEYED -# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n" -# define CONFIG_AUTOBOOT_STOP_STR " " -# undef CONFIG_AUTOBOOT_DELAY_STR -# define DEBUG_BOOTKEYS 0 -#endif - -/* Define a command string that is automatically executed when no character - * is read on the console interface withing "Boot Delay" after reset. - */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ - -#ifdef CONFIG_BOOT_ROOT_INITRD -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_INITRD */ - -#ifdef CONFIG_BOOT_ROOT_NFS -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_NFS */ - -/* Add support for a few extra bootp options like: - * - File size - * - DNS - */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS) - -/* undef this to save memory */ -#define CFG_LONGHELP - -/* Monitor Command Prompt */ -#define CFG_PROMPT "=> " - -/* What U-Boot subsytems do you want enabled? */ -#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_ELF | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ - CFG_CMD_REGINFO | \ - CFG_CMD_MEMTEST | \ - CFG_CMD_MII | \ - CFG_CMD_IMMAP) - - -/* Where do the internal registers live? */ -#define CFG_IMMR 0xf0000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) - -#define CFG_MAXARGS 32 /* max number of command args */ - -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x140000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ - + CFG_MALLOC_LEN \ - + CFG_ENV_SECT_SIZE \ - + CFG_STACK_USAGE ) - -#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ - - CFG_MEM_END_USAGE ) - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) -/* - * Attention: This is board specific - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -#define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\ - CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) -/* - * Attention: this is board-specific - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -#define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -#define CFG_CPMFCR_RAMTYPE 0 -#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) -#endif /* CONFIG_ETHER_INDEX */ - -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE -#define CFG_SDRAM_BASE CFG_SDRAM0_BASE -#define CFG_SDRAM_SIZE (CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE) - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CFG_PPMC_BOOT_LOW) -# define CFG_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CFG_PPMC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CFG_PPMC_BOOT_LOW) */ - -/* get the HRCW ISB field from CFG_IMMR */ -#define CFG_PPMC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ - ((CFG_IMMR & 0x01000000) >> 7) | \ - ((CFG_IMMR & 0x00100000) >> 4) ) - -#define CFG_HRCW_MASTER ( HRCW_EBM | \ - HRCW_BPS11 | \ - HRCW_L2CPC10 | \ - HRCW_DPPC00 | \ - CFG_PPMC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC00 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CFG_PPMC_MODCK_H & HRCW_MODCK_H1111) | \ - CFG_PPMC_HRCW_BOOT_FLAGS ) - -/* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CFG_RAMBOOT is platform dependent. - */ -#define CFG_MONITOR_BASE CFG_FLASH0_BASE - -#ifndef CFG_MONITOR_BASE -#define CFG_MONITOR_BASE 0x0ff80000 -#endif - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - - -#ifndef CFG_RAMBOOT - -# define CFG_ENV_IS_IN_FLASH 1 -# ifdef CFG_ENV_IN_OWN_SECT -# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -# define CFG_ENV_SECT_SIZE 0x40000 -# else -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) -# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ -# endif /* CFG_ENV_IN_OWN_SECT */ - -#else -# define CFG_ENV_IS_IN_FLASH 1 -# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) -#define CFG_ENV_SIZE 0x1000 -# define CFG_ENV_SECT_SIZE 0x40000 -#endif /* CFG_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CFG_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CFG_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR (BCR_EBM |\ - 0x30000000) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - * Ref Section 4.3.2.6 page 4-31 - *----------------------------------------------------------------------- - */ - -#define CFG_SIUMCR (SIUMCR_ESE |\ - SIUMCR_DPPC00 |\ - SIUMCR_L2CPC10 |\ - SIUMCR_LBPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_CS10PC00 |\ - SIUMCR_BCTLC00 |\ - SIUMCR_MMR00) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CFG_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CFG_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Initialize Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) * - * 1 unused - * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB) - * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB) - * 4 Local SDRAM 32 bit SDRAM (on board - 16MB) - * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB) - * 6 60x GPCM 8 bit FLASH (on board - 2MB) * - * 7 60x GPCM 8 bit LEDs, switches - * - * (*) This configuration requires the PPMC8260 be configured - * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to - * the on board FLASH. In other words, JP24 should have - * pins 1 and 2 jumpered and pins 3 and 4 jumpered. - * - */ - -/*----------------------------------------------------------------------- - * BR0,BR1 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR0,OR1 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0,1 - FLASH SIMM - * - * This expects the FLASH SIMM to be connected to *CS0 - * It consists of 4 AM29F080B parts. - * - * Note: For the 4 MB SIMM, *CS1 is unused. - */ - -/* BR0 is configured as follows: - * - * - Base address of 0xFE000000 - * - 32 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR0 is configured as follows: - * - * - 32 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR2,BR3 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2,OR3 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* - * Bank 2,3 - 128 MB SDRAM DIMM - */ - -/* With a 128 MB DIMM, the BR2 is configured as follows: - * - * - Base address of 0x00000000/0x08000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_BR3_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 128 MB DIMM, the OR2 is configured as follows: - * - * - 128 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 13 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ - -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CFG_OR3_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ - -/* With a 128 MB DIMM, the PSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Normal Operation - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A13-A15 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - External Address Multiplexing enabled - * - CAS Latency is 2. - */ -#define CFG_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - - -#define CFG_PSRT 0x0e -#define CFG_MPTPR MPTPR_PTP_DIV32 - - -/*----------------------------------------------------------------------- - * BR4 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR4 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* - * Bank 4 - On board SDRAM - * - */ -/* With 16 MB of onboard SDRAM BR4 is configured as follows - * - * - Base address 0x38000000 - * - 32 bit port size - * - Data error checking disabled - * - Read/Write access - * - SDRAM local bus - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - * - */ - -#define CFG_BR4_PRELIM ((CFG_SDRAM2_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_DECC_NONE |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -/* - * With 16MB SDRAM, OR4 is configured as follows - * - 4 internal banks per device - * - Row start address bit is A10 with LSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ - -#define CFG_OR4_PRELIM (MEG_TO_AM(CFG_SDRAM2_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A10 |\ - ORxS_NUMR_12) - - -/*----------------------------------------------------------------------- - * LSDMR - Local Bus SDRAM Mode Register - * Ref: Section 10.3.4 on page 10-24 - *----------------------------------------------------------------------- - */ - -/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows: - * - * - Page Based Interleaving, - * - Refresh Enable, - * - Normal Operation - * - Address Multiplexing where A5 is output on A13 pin - * (A6 on A15, and so on), - * - use address pins A15-A17 as bank select, - * - A11 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 2 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - SDRAM burst length is 8 - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - External Address Multiplexing disabled - * - CAS Latency is 2. - */ -#define CFG_LSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI0_A11 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CFG_LSRT 0x0e - -/*----------------------------------------------------------------------- - * BR5 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR5 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* - * Bank 5 EEProm and Mailbox - * - * The EEPROM and mailbox live on the same chip select. - * the eeprom is selected if the MSb of the address is set and the mailbox is - * selected if the MSb of the address is clear. - * - */ - -/* BR5 is configured as follows: - * - * - Base address of 0x32000000/0xF2000000 - * - 8 bit - * - Data error checking disabled - * - Read/Write access - * - GPCM 60x Bus - * - SDRAM local bus - * - No data pipelining is done - * - Valid - */ - -#define CFG_BR5_PRELIM ((CFG_MAILBOX_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) -/* OR5 is configured as follows - * - buffer control enabled - * - chip select negated normally - * - CS output 1/2 clock after address - * - 15 wait states - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ - -#define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_15_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR6 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR6 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 6 - I/O select - * - */ - -/* BR6 is configured as follows: - * - * - Base address of 0xE0000000 - * - 16 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CFG_BR6_PRELIM ((CFG_IOSELECT_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR6 is configured as follows - * - buffer control enabled - * - chip select negated normally - * - CS output 1/2 clock after address - * - 15 wait states - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ - -#define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_15_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - - -/*----------------------------------------------------------------------- - * BR7 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR7 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 7 - LEDs and switches - * - * LEDs are at 0x00001 (write only) - * switches are at 0x00001 (read only) - */ -#ifdef CFG_LED_BASE - -/* BR7 is configured as follows: - * - * - Base address of 0xA0000000 - * - 8 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR7 is configured as follows: - * - * - 1 byte - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 15 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CFG_OR7_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_15_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) -#endif /* CFG_LED_BASE */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/purple.h b/include/configs/purple.h deleted file mode 100644 index 2ecb7fb..0000000 --- a/include/configs/purple.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file contains the configuration parameters for the PURPLE board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MIPS32 1 /* MIPS 5Kc CPU core */ -#define CONFIG_PURPLE 1 /* on a PURPLE Board */ - -#define CPU_CLOCK_RATE 125000000 /* 125 MHz clock for the MIPS core */ -#define ASC_CLOCK_RATE 62500000 /* 62.5 MHz ASC clock */ - -#define INFINEON_EBU_BOOTCFG 0xE0CC - -#define CONFIG_STACKSIZE (128 * 1024) - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 19200 - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "ethaddr=${ethaddr} " \ - "panic=1\0" \ - "flash_nfs=run nfsargs addip addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 80500000 ${bootfile};" \ - "run nfsargs addip addmisc;bootm\0" \ - "rootpath=/opt/eldk/mips_5KC\0" \ - "bootfile=/tftpboot/purple/uImage\0" \ - "kernel_addr=B0040000\0" \ - "ramdisk_addr=B0100000\0" \ - "u-boot=/tftpboot/purple/u-boot.bin\0" \ - "load=tftp 80500000 ${u-boot}\0" \ - "update=protect off 1:0-4;era 1:0-4;" \ - "cp.b 80500000 B0000000 ${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF) -#include - -#define CFG_SDRAM_BASE 0x80000000 - -#define CFG_INIT_SP_OFFSET 0x400000 - -#define CFG_MALLOC_LEN 128*1024 - -#define CFG_BOOTPARAMS_LEN 128*1024 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "PURPLE # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_HZ (CPU_CLOCK_RATE/2) -#define CFG_MAXARGS 16 /* max number of command args*/ - -#define CFG_LOAD_ADDR 0x80500000 /* default load address */ - -#define CFG_MEMTEST_START 0x80200000 -#define CFG_MEMTEST_END 0x80800000 - -#define CONFIG_MISC_INIT_R - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (35) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */ - -/* The following #defines are needed to get flash environment right */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (6 * CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (6 * CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR 0xB0008000 -#define CFG_ENV_SIZE 0x4000 - -#define CONFIG_FLASH_32BIT -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_PLB2800_ETHER -#define CONFIG_NET_MULTI - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_ICACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CFG_SCONSOLE_ADDR (CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET - \ - CFG_DCACHE_SIZE / 2) -#define CFG_SCONSOLE_SIZE (CFG_DCACHE_SIZE / 4) - -#endif /* __CONFIG_H */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h deleted file mode 100644 index e5e2772..0000000 --- a/include/configs/pxa255_idp.h +++ /dev/null @@ -1,338 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Copied from lubbock.h - * - * (C) Copyright 2004 - * BEC Systems - * Cliff Brake - * Configuation settings for the Accelent/Vibren PXA255 IDP - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * If we are developing, we might want to start armboot from ram - * so we MUST NOT initialize critical regs like mem-timing ... - */ -#define CONFIG_INIT_CRITICAL /* undef for developing */ - -/* - * define the following to enable debug blinks. A debug blink function - * must be defined in memsetup.S - */ -#undef DEBUG_BLINK_ENABLE -#undef DEBUG_BLINKC_ENABLE - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ - -#undef CONFIG_LCD -#ifdef CONFIG_LCD -#define CONFIG_SHARP_LM8V31 -#endif - -#define CONFIG_MMC 1 -#define BOARD_LATE_INIT 1 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * PXA250 IDP memory map information - */ - -#define IDP_CS5_ETH_OFFSET 0x03400000 - - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300) -#define CONFIG_SMC_USE_32_BIT 1 -/* #define CONFIG_SMC_USE_IOFUNCS */ - -/* the following has to be set high -- suspect something is wrong with - * with the tftp timeout routines. FIXME!!! - */ -#define CONFIG_NET_RETRY_COUNT 100 - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_DHCP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "bootm 40000" -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" -#define CONFIG_CMDLINE_TAG - -/* - * Current memory map for Vibren supplied Linux images: - * - * Flash: - * 0 - 0x3ffff (size = 0x40000): bootloader - * 0x40000 - 0x13ffff (size = 0x100000): kernel - * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs - * - * RAM: - * 0xa0008000 - kernel is loaded - * 0xa3000000 - Uboot runs (48MB into RAM) - * - */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "prog_boot_mmc=" \ - "mw.b 0xa0000000 0xff 0x40000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x3ffff; " \ - "erase 0x0 0x3ffff; " \ - "cp.b 0xa0000000 0x0 0x40000; " \ - "reset;" \ - "fi\0" \ - "prog_uzImage_mmc=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 uzImage; " \ - "then " \ - "protect off 0x40000 0xfffff; " \ - "erase 0x40000 0xfffff; " \ - "cp.b 0xa0000000 0x40000 0x100000; " \ - "fi\0" \ - "prog_jffs_mmc=" \ - "mw.b 0xa0000000 0xff 0x1e00000; " \ - "if mmcinit && " \ - "fatload mmc 0 0xa0000000 root.jffs; " \ - "then " \ - "protect off 0x140000 0x1f3ffff; " \ - "erase 0x140000 0x1f3ffff; " \ - "cp.b 0xa0000000 0x140000 0x1e00000; " \ - "fi\0" \ - "boot_mmc=" \ - "if mmcinit && " \ - "fatload mmc 0 0xa1000000 uzImage && " \ - "then " \ - "bootm 0xa1000000; " \ - "fi\0" \ - "prog_boot_net=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if bootp 0xa0000000 u-boot.bin; " \ - "then " \ - "protect off 0x0 0x3ffff; " \ - "erase 0x0 0x3ffff; " \ - "cp.b 0xa0000000 0x0 0x40000; " \ - "reset; " \ - "fi\0" \ - "prog_uzImage_net=" \ - "mw.b 0xa0000000 0xff 0x100000; " \ - "if bootp 0xa0000000 uzImage; " \ - "then " \ - "protect off 0x40000 0xfffff; " \ - "erase 0x40000 0xfffff; " \ - "cp.b 0xa0000000 0x40000 0x100000; " \ - "fi\0" \ - "prog_jffs_net=" \ - "mw.b 0xa0000000 0xff 0x1e00000; " \ - "if bootp 0xa0000000 root.jffs; " \ - "then " \ - "protect off 0x140000 0x1f3ffff; " \ - "erase 0x140000 0x1f3ffff; " \ - "cp.b 0xa0000000 0x140000 0x1e00000; " \ - "fi\0" - - -/* "erase_env=" */ -/* "protect off" */ - - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xa0800000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ - -#define RTC 1 /* enable 32KHz osc */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_MMC_BASE 0xF0000000 - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * GPIO settings - */ - -#define CFG_GAFR0_L_VAL 0x80001005 -#define CFG_GAFR0_U_VAL 0xa5128012 -#define CFG_GAFR1_L_VAL 0x699a9558 -#define CFG_GAFR1_U_VAL 0xaaa5aa6a -#define CFG_GAFR2_L_VAL 0xaaaaaaaa -#define CFG_GAFR2_U_VAL 0x2 -#define CFG_GPCR0_VAL 0x1800400 -#define CFG_GPCR1_VAL 0x0 -#define CFG_GPCR2_VAL 0x0 -#define CFG_GPDR0_VAL 0xc1818440 -#define CFG_GPDR1_VAL 0xfcffab82 -#define CFG_GPDR2_VAL 0x1ffff -#define CFG_GPSR0_VAL 0x8000 -#define CFG_GPSR1_VAL 0x3f0002 -#define CFG_GPSR2_VAL 0x1c000 - -#define CFG_PSSR_VAL 0x20 - -/* - * Memory settings - */ -#define CFG_MSC0_VAL 0x29DCA4D2 -#define CFG_MSC1_VAL 0x43AC494C -#define CFG_MSC2_VAL 0x39D449D4 -#define CFG_MDCNFG_VAL 0x090009C9 -#define CFG_MDREFR_VAL 0x0085C017 -#define CFG_MDMRS_VAL 0x00220022 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000003 -#define CFG_MCMEM0_VAL 0x00014405 -#define CFG_MCMEM1_VAL 0x00014405 -#define CFG_MCATT0_VAL 0x00014405 -#define CFG_MCATT1_VAL 0x00014405 -#define CFG_MCIO0_VAL 0x00014405 -#define CFG_MCIO1_VAL 0x00014405 - -/* - * FLASH and environment organization - */ -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER 1 - -#define CFG_MONITOR_BASE 0 -#define CFG_MONITOR_LEN 0x40000 - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -#define CFG_FLASH_USE_BUFFER_WRITE 1 - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - -/* put cfg at end of flash for now */ -#define CFG_ENV_IS_IN_FLASH 1 - /* Addr of Environment Sector */ -#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000) -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x40000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/quantum.h b/include/configs/quantum.h deleted file mode 100644 index 21ec5ac..0000000 --- a/include/configs/quantum.h +++ /dev/null @@ -1,446 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - * changes for 16M board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */ -#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -/* default developmenmt environment */ - -#define CONFIG_ETHADDR 00:0B:17:00:00:00 - -#define CONFIG_IPADDR 10.10.69.10 -#define CONFIG_SERVERIP 10.10.69.49 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME QUANTUM -#define CONFIG_ROOTPATH /opt/eldk/pcc_8xx - -#define CONFIG_BOOTARGS "root=/dev/ram rw" - -#define CONFIG_BOOTCOMMAND "bootm ff000000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serial#=12345\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" - -/* - * Select the more full-featured memory test (Barr embedded systems) - */ -#define CFG_ALT_MEMTEST - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - - -/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/ -#define CONFIG_RTC_M48T35A 1 - -#if 0 -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ -#else -#undef CONFIG_WATCHDOG -#endif - -/* NVRAM and RTC */ -#define CFG_NVRAM_BASE_ADDR 0xFA000000 -#define CFG_NVRAM_SIZE 2048 - - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" -#define CONFIG_AUTOBOOT_DELAY_STR "system" -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00040000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFF000000 - -#if 1 - #define CFG_FLASH_CFI_DRIVER -#else - #undef CFG_FLASH_CFI_DRIVER -#endif - - -#ifdef CFG_FLASH_CFI_DRIVER - #define CFG_FLASH_CFI 1 - #undef CFG_FLASH_USE_BUFFER_WRITE - #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} -#endif - -/*%%% #define CFG_FLASH_BASE 0xFFF00000 */ -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE 0xFFF00000 -/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00F40000 /* Offset of Environment Sector absolute address 0xfff40000*/ -#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* FPGA */ -#define CONFIG_MISC_INIT_R -#define CFG_FPGA_SPARTAN2 -#define CFG_FPGA_PROG_FEEDBACK - - -/*----------------------------------------------------------------------- - * Reset address - */ -#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ -#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000E00 - -#define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */ -#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CFG_BR3_PRELIM 0xFA400001 /* FPGA */ -#define CFG_OR3_PRELIM 0xFFFF8910 - -#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ -#define CFG_OR4_PRELIM 0xFFFE0970 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 20 - -/* - * Refresh clock Prescalar - */ -#define CFG_MPTPR MPTPR_PTP_DIV2 - -/* - * MAMR settings for SDRAM - */ - -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 0xFA400000 -#define BCSR1 0xFA400001 -#define BCSR2 0xFA400002 -#define BCSR3 0xFA400003 - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - -#endif /* __CONFIG_H */ diff --git a/include/configs/rmu.h b/include/configs/rmu.h deleted file mode 100644 index b319cf4..0000000 --- a/include/configs/rmu.h +++ /dev/null @@ -1,420 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - - -/* - * High Level Configuration Options - * (easy to change) - */ - -#undef CONFIG_MPC860 -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_RPXLITE 1 /* RMU is the RPXlite clone */ -#define CONFIG_RMU 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -/* Software (bit-bang) I2C driver configuration */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -/* M41T11 Serial Access Timekeeper(R) SRAM */ -#define CONFIG_RTC_M41T11 1 -#define CFG_I2C_RTC_ADDR 0x68 -#define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" -#define CONFIG_AUTOBOOT_DELAY_STR "system" - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0040000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFA200000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */ -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR ((TEXT_BASE) + 0x40000) -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Reset address - */ -#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res))) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_MLRC10) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base - up to 64 MB of flash */ -#define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask - map 64 MB */ - -/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ -#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) - -/* - * BR1 and OR1 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM 0x00000E00 - -#define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */ -#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* RPXLITE mem setting */ -#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM & SRAM base */ -/* IMMR: 0xFA200000 IMMR base address - see above */ -#define CFG_BCSR_BASE 0xFA400000 /* BCSR base address */ - -#define CFG_BR3_PRELIM (CFG_BCSR_BASE | BR_V) /* BCSR */ -#define CFG_OR3_PRELIM 0xFFFF8910 -#define CFG_BR4_PRELIM (CFG_NVRAM_BASE | BR_PS_8 | BR_V) /* NVRAM & SRAM */ -#define CFG_OR4_PRELIM 0xFFFE0970 - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 20 - -/* - * Refresh clock Prescalar - */ -#define CFG_MPTPR MPTPR_PTP_DIV2 - -/* - * MAMR settings for SDRAM - */ - -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* - * BCSRx - * - * Board Status and Control Registers - * - */ - -#define BCSR0 (CFG_BCSR_BASE + 0) -#define BCSR1 (CFG_BCSR_BASE + 1) -#define BCSR2 (CFG_BCSR_BASE + 2) -#define BCSR3 (CFG_BCSR_BASE + 3) - -#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ -#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ -#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ -#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ -#define BCSR0_COLTEST 0x20 -#define BCSR0_ETHLPBK 0x40 -#define BCSR0_ETHEN 0x80 - -#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ -#define BCSR1_PCVCTL6 0x02 -#define BCSR1_PCVCTL5 0x04 -#define BCSR1_PCVCTL4 0x08 -#define BCSR1_IPB5SEL 0x10 - -#define BCSR2_ENPA5HDR 0x08 /* USB Control */ -#define BCSR2_ENUSBCLK 0x10 -#define BCSR2_USBPWREN 0x20 -#define BCSR2_USBSPD 0x40 -#define BCSR2_USBSUSP 0x80 - -#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ -#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ -#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ -#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ -#define BCSR3_D27 0x10 /* Dip Switch settings */ -#define BCSR3_D26 0x20 -#define BCSR3_D25 0x40 -#define BCSR3_D24 0x80 - -#endif /* __CONFIG_H */ diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h deleted file mode 100644 index 6c9e392..0000000 --- a/include/configs/rsdproto.h +++ /dev/null @@ -1,418 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the R&S Protocol Board board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ - -#if (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE (0) -# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ - - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* enable I2C */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 50000000 /* in Hz */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_KGDB) - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CFG_RSD_BOOT_LOW 1 - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs" -#define CONFIG_ETHADDR 08:00:3e:26:0a:5a -#define CONFIG_NETMASK 255.255.0.0 - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */ -#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */ - -#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */ -#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */ - -#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */ -#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */ - -/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */ -/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */ - -#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */ -#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */ - -/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */ -/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */ - -#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */ -#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100 - -#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */ -#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */ - -#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */ - -#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ - -#define CFG_IMMR PHYS_IMMR - -/*----------------------------------------------------------------------- - * Reset Address - * - * In order to reset the CPU, U-Boot jumps to a special address which - * causes a machine check exception. The default address for this is - * CFG_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when - * testing the monitor in RAM using a JTAG debugger. - * - * Just set CFG_RESET_ADDRESS to an address that you know is sure to - * cause a bus error on your hardware. - */ -#define CFG_RESET_ADDRESS 0x20000000 - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ - -#if defined(CFG_RSD_BOOT_LOW) -# define CFG_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CFG_RSD_HRCW_BOOT_FLAGS (0) -#endif /* defined(CFG_RSD_BOOT_LOW) */ - -/* get the HRCW ISB field from CFG_IMMR */ -#define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\ - ((CFG_IMMR & 0x01000000) >> 7) |\ - ((CFG_IMMR & 0x00100000) >> 4) ) - -#define CFG_HRCW_MASTER (HRCW_L2CPC10 | \ - HRCW_DPPC11 | \ - CFG_RSD_HRCW_IMMR |\ - HRCW_MMR00 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - HRCW_MODCK_H0000 |\ - CFG_RSD_HRCW_BOOT_FLAGS) - -/* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CFG_RAMBOOT is platform dependend. - */ -#define CFG_SDRAM_BASE PHYS_SDRAM_60X -#define CFG_FLASH_BASE PHYS_FLASH -/*#define CFG_MONITOR_BASE 0x200000 */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#if CFG_MONITOR_BASE < CFG_FLASH_BASE -#define CFG_RAMBOOT -#endif -#define CFG_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 63 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */ - -/* turn off NVRAM env feature */ -#undef CONFIG_NVRAM_ENV - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE) -#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CFG_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR 0x100c0000 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ - -#define CFG_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \ - SIUMCR_CS10PC01 | SIUMCR_BCTLC01) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \ - SYPCR_SWRI | SYPCR_SWP) - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CFG_SCCR 0x00000000 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Init Memory Controller: - */ - -#define CFG_PSDMR 0x494D2452 -#define CFG_LSDMR 0x49492552 - -/* Flash */ -#define CFG_BR0_PRELIM (PHYS_FLASH | BRx_V) -#define CFG_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \ - ORxG_BCTLD | \ - ORxG_SCY_5_CLK) - -/* DPRAM to the PCI BUS on the protocol board */ -#define CFG_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V) -#define CFG_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \ - ORxG_ACS_DIV4) - -/* 60x Bus SDRAM */ -#define CFG_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V) -#define CFG_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \ - ORxS_BPD_4 | \ - ORxS_ROWST_PBI1_A2 | \ - ORxS_NUMR_13 | \ - ORxS_IBID) - -/* Virtex-FPGA - Register */ -#define CFG_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V) -#define CFG_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \ - ORxG_SCY_1_CLK | \ - ORxG_ACS_DIV2 | \ - ORxG_CSNT ) - -/* local bus SDRAM */ -#define CFG_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V) -#define CFG_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \ - ORxS_BPD_4 | \ - ORxS_ROWST_PBI1_A4 | \ - ORxS_NUMR_13) - -/* DPRAM to the Sharc-Bus on the protocol board */ -#define CFG_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V) -#define CFG_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \ - ORxG_ACS_DIV4) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h deleted file mode 100644 index 4e0cfdb..0000000 --- a/include/configs/sacsng.h +++ /dev/null @@ -1,1074 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * Configuration settings for the WindRiver SBC8260 board. - * See http://www.windriver.com/products/html/sbc8260.html - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG /* General debug */ -#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ - -#undef CONFIG_LOGBUFFER /* External logbuffer support */ - -/***************************************************************************** - * - * These settings must match the way _your_ board is set up - * - *****************************************************************************/ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN 66666600 - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 - * ------- ---------- --- --- ---- ----- ----- ----- - * 0x1 0x5 33 100 133 Open Close Open - * 0x1 0x6 33 100 166 Open Open Close - * 0x1 0x7 33 100 200 Open Open Open - * - * 0x2 0x2 33 133 133 Close Open Close - * 0x2 0x3 33 133 166 Close Open Open - * 0x2 0x4 33 133 200 Open Close Close - * 0x2 0x5 33 133 233 Open Close Open - * 0x2 0x6 33 133 266 Open Open Close - * - * 0x5 0x5 66 133 133 Open Close Open - * 0x5 0x6 66 133 166 Open Open Close - * 0x5 0x7 66 133 200 Open Open Open - * 0x6 0x0 66 133 233 Close Close Close - * 0x6 0x1 66 133 266 Close Close Open - * 0x6 0x2 66 133 300 Close Open Close - */ -#define CFG_SBC_MODCK_H 0x05 - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CFG_SBC_BOOT_LOW 1 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain TEXT_BASE from board/sacsng/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CFG_FLASH0_BASE 0x40000000 -#define CFG_FLASH0_SIZE 2 - -/* What should the base address of the secondary FLASH be and how big - * is it (in Mbytes)? The secondary FLASH is whichever is connected - * to *CS6. - */ -#define CFG_FLASH1_BASE 0x60000000 -#define CFG_FLASH1_SIZE 2 - -/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes - */ -#define CONFIG_VERY_BIG_RAM 1 - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? This will normally auto-configure via the SPD. -*/ -#define CFG_SDRAM0_BASE 0x00000000 -#define CFG_SDRAM0_SIZE 64 - -/* - * Memory map example with 64 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x03F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x03F5 FFB0 Board Info Data - * 0x03F6 0000 Malloc Arena - * : CFG_ENV_SECT_SIZE, 16k - * : CFG_MALLOC_LEN, 128k - * 0x03FC 0000 RAM Copy of Monitor Code - * : CFG_MONITOR_LEN, 256k - * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 - */ - -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU) - - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ - -#undef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_ON_FCC -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ - -#ifdef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif /* CONFIG_ETHER_ON_SCC */ - -#ifdef CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ - -#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */ -#define MDIO_ACTIVE (iop->pdir |= 0x40000000) -#define MDIO_TRISTATE (iop->pdir &= ~0x40000000) -#define MDIO_READ ((iop->pdat & 0x40000000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \ - else iop->pdat &= ~0x40000000 - -#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \ - else iop->pdat &= ~0x80000000 - -#define MIIDELAY udelay(50) -#endif /* CONFIG_ETHER_ON_FCC */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */ - -/* - * Configure for RAM tests. - */ -#undef CFG_DRAM_TEST /* calls other tests in board.c */ - - -/* - * Status LED for power up status feedback. - */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define STATUS_LED_PAR im_ioport.iop_ppara -#define STATUS_LED_DIR im_ioport.iop_pdira -#define STATUS_LED_ODR im_ioport.iop_podra -#define STATUS_LED_DAT im_ioport.iop_pdata - -#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */ -#define STATUS_LED_PERIOD (CFG_HZ) -#define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */ -#define STATUS_LED_PERIOD1 (CFG_HZ) -#define STATUS_LED_STATE1 STATUS_LED_OFF -#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */ -#define STATUS_LED_PERIOD2 (CFG_HZ/2) -#define STATUS_LED_STATE2 STATUS_LED_ON - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ - -#define STATUS_LED_YELLOW 0 -#define STATUS_LED_GREEN 1 -#define STATUS_LED_RED 2 -#define STATUS_LED_BOOT 1 - - -/* - * Select SPI support configuration - */ -#define CONFIG_SOFT_SPI /* Enable SPI driver */ -#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */ -#undef DEBUG_SPI /* Disable SPI debugging */ - -/* - * Software (bit-bang) SPI driver configuration - */ -#ifdef CONFIG_SOFT_SPI - -/* - * Software (bit-bang) SPI driver configuration - */ -#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */ -#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */ -#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */ - -#undef SPI_INIT /* no port initialization needed */ -#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0) -#define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ - else immr->im_ioport.iop_pdatd &= ~I2C_MOSI -#define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ - else immr->im_ioport.iop_pdatd &= ~I2C_SCLK -#define SPI_DELAY /* No delay is needed */ -#endif /* CONFIG_SOFT_SPI */ - - -/* - * select I2C support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ -#ifdef CONFIG_SOFT_I2C -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -/* Define this to reserve an entire FLASH sector for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CFG_ENV_IN_OWN_SECT 1 - -/* Define this to contain any number of null terminated strings that - * will be part of the default enviroment compiled into the boot image. - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ -"quiet=0\0" \ -"serverip=192.168.123.205\0" \ -"ipaddr=192.168.123.203\0" \ -"checkhostname=VR8500\0" \ -"reprog="\ - "bootp; " \ - "tftpboot 0x140000 /bdi2000/u-boot.bin; " \ - "protect off 60000000 6003FFFF; " \ - "erase 60000000 6003FFFF; " \ - "cp.b 140000 60000000 ${filesize}; " \ - "protect on 60000000 6003FFFF\0" \ -"copyenv="\ - "protect off 60040000 6004FFFF; " \ - "erase 60040000 6004FFFF; " \ - "cp.b 40040000 60040000 10000; " \ - "protect on 60040000 6004FFFF\0" \ -"copyprog="\ - "protect off 60000000 6003FFFF; " \ - "erase 60000000 6003FFFF; " \ - "cp.b 40000000 60000000 40000; " \ - "protect on 60000000 6003FFFF\0" \ -"zapenv="\ - "protect off 40040000 4004FFFF; " \ - "erase 40040000 4004FFFF; " \ - "protect on 40040000 4004FFFF\0" \ -"zapotherenv="\ - "protect off 60040000 6004FFFF; " \ - "erase 60040000 6004FFFF; " \ - "protect on 60040000 6004FFFF\0" \ -"root-on-initrd="\ - "setenv bootcmd "\ - "version\\;" \ - "echo\\;" \ - "bootp\\;" \ - "setenv bootargs root=/dev/ram0 rw quiet " \ - "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ - "run boot-hook\\;" \ - "bootm\0" \ -"root-on-initrd-debug="\ - "setenv bootcmd "\ - "version\\;" \ - "echo\\;" \ - "bootp\\;" \ - "setenv bootargs root=/dev/ram0 rw debug " \ - "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ - "run debug-hook\\;" \ - "run boot-hook\\;" \ - "bootm\0" \ -"root-on-nfs="\ - "setenv bootcmd "\ - "version\\;" \ - "echo\\;" \ - "bootp\\;" \ - "setenv bootargs root=/dev/nfs rw quiet " \ - "nfsroot=\\${serverip}:\\${rootpath} " \ - "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ - "run boot-hook\\;" \ - "bootm\0" \ -"root-on-nfs-debug="\ - "setenv bootcmd "\ - "version\\;" \ - "echo\\;" \ - "bootp\\;" \ - "setenv bootargs root=/dev/nfs rw debug " \ - "nfsroot=\\${serverip}:\\${rootpath} " \ - "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ - "run debug-hook\\;" \ - "run boot-hook\\;" \ - "bootm\0" \ -"debug-checkout="\ - "setenv checkhostname;" \ - "setenv ethaddr 00:09:70:00:00:01;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run debug-hook;" \ - "run boot-hook;" \ - "bootm\0" \ -"debug-hook="\ - "echo ipaddr ${ipaddr};" \ - "echo serverip ${serverip};" \ - "echo gatewayip ${gatewayip};" \ - "echo netmask ${netmask};" \ - "echo hostname ${hostname}\0" \ -"ana=run adc ; run dac\0" \ -"adc=run adc-12 ; run adc-34\0" \ -"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \ -"adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \ -"dac=echo ### DAC ; imd.b 11 81 5\0" \ -"boot-hook=echo\0" - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 9600 - -/* Ethernet MAC address */ -#define CONFIG_ETHADDR 00:09:70:00:00:00 - -/* The default Ethernet MAC address can be overwritten just once */ -#ifdef CONFIG_ETHADDR -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#endif - -/* - * Define this to do some miscellaneous board-specific initialization. - */ -#define CONFIG_MISC_INIT_R - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n" -#define CONFIG_AUTOBOOT_STOP_STR " " -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define DEBUG_BOOTKEYS 0 - -/* Define a command string that is automatically executed when no character - * is read on the console interface withing "Boot Delay" after reset. - */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ - -#ifdef CONFIG_BOOT_ROOT_INITRD -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw quiet " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run boot-hook;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_INITRD */ - -#ifdef CONFIG_BOOT_ROOT_NFS -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run boot-hook;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_NFS */ - -#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */ - -/* Add support for a few extra bootp options like: - * - File size - * - DNS (up to 2 servers) - * - Send hostname to DHCP server - */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME) - -/* undef this to save memory */ -#define CFG_LONGHELP - -/* Monitor Command Prompt */ -#define CFG_PROMPT "=> " - -#undef CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time) - * of an image is printed by image commands like bootm or iminfo. - */ -#define CONFIG_TIMESTAMP - -/* If this variable is defined, an environment variable named "ver" - * is created by U-Boot showing the U-Boot version. - */ -#define CONFIG_VERSION_VARIABLE - -/* What U-Boot subsytems do you want enabled? */ -#ifdef CONFIG_ETHER_ON_FCC -# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_ELF | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ - CFG_CMD_I2C | \ - CFG_CMD_SPI | \ - CFG_CMD_SDRAM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_IRQ | \ - CFG_CMD_PING | \ - CFG_CMD_MII ) -#else -# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_ELF | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ - CFG_CMD_I2C | \ - CFG_CMD_SPI | \ - CFG_CMD_SDRAM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_IRQ | \ - CFG_CMD_PING ) -#endif /* CONFIG_ETHER_ON_FCC */ - -/* Where do the internal registers live? */ -#define CFG_IMMR 0xF0000000 - -#undef CONFIG_WATCHDOG /* disable the watchdog */ - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */ -#define CONFIG_SACSng 1 /* munged for the SACSng */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CFG_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */ - /* in the bootm command. */ -#define CFG_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */ - /* "## " from the bootm cmd */ -#define CFG_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */ - /* defined, then the hostname param */ - /* validated against checkhostname. */ -#define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */ -#define CFG_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */ - /* (limited to maximum of 1024 msec) */ -#define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1 - /* Check for abort key presses */ - /* at least once in dependent of the */ - /* CONFIG_BOOTDELAY value. */ -#define CFG_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */ -#define CFG_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */ - /* state to the fault LED. */ -#define CFG_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */ - /* the Ethernet link state. */ -#define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */ - /* until the TFTP is successful. */ -#define CFG_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */ - /* turn off the STATUS LEDs. */ -#define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */ - /* incoming data. */ -#define CFG_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */ - /* to signify that tftp is moving. */ -#define CFG_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */ - /* flash the status LED. */ -#define CFG_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */ - /* during the tftp file transfer. */ -#define CFG_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */ - /* '#'s from the tftp command. */ -#define CFG_TFTP_STATUS_QUIET 1 /* Suppress the status displays */ - /* issued during the tftp command. */ -#define CFG_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */ - /* before it gives up. */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) - -#define CFG_MAXARGS 32 /* max number of command args */ - -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_ALT_MEMTEST /* Select full-featured memory test */ -#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ - + CFG_MALLOC_LEN \ - + CFG_ENV_SECT_SIZE \ - + CFG_STACK_USAGE ) - -#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ - - CFG_MEM_END_USAGE ) - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE -#define CFG_SDRAM_BASE CFG_SDRAM0_BASE -#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CFG_SBC_BOOT_LOW) -# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CFG_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CFG_SBC_BOOT_LOW) */ - -/* get the HRCW ISB field from CFG_IMMR */ -#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ - ((CFG_IMMR & 0x01000000) >> 7) | \ - ((CFG_IMMR & 0x00100000) >> 4) ) - -#define CFG_HRCW_MASTER ( HRCW_BPS10 | \ - HRCW_DPPC11 | \ - CFG_SBC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC11 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \ - CFG_SBC_HRCW_BOOT_FLAGS ) - -/* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CFG_RAMBOOT is platform dependent. - */ -#define CFG_MONITOR_BASE CFG_FLASH0_BASE - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#undef CFG_FLASH_PROTECTION /* use hardware protection */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -#ifndef CFG_RAMBOOT -# define CFG_ENV_IS_IN_FLASH 1 - -# ifdef CFG_ENV_IN_OWN_SECT -# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -# define CFG_ENV_SECT_SIZE 0x10000 -# else -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) -# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CFG_ENV_IN_OWN_SECT */ - -#else -# define CFG_ENV_IS_IN_NVRAM 1 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) -# define CFG_ENV_SIZE 0x200 -#endif /* CFG_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CFG_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CFG_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ - -#define CFG_SIUMCR (SIUMCR_DPPC11 |\ - SIUMCR_L2CPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_MMR00) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP |\ - SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CFG_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Initialize Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 16 bit FLASH (primary flash - 2MB) - * 1 60x GPCM -- bit (Unused) - * 2 60x SDRAM 64 bit SDRAM (DIMM) - * 3 60x SDRAM 64 bit SDRAM (DIMM) - * 4 60x GPCM -- bit (Unused) - * 5 60x GPCM -- bit (Unused) - * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB) - */ - -/*----------------------------------------------------------------------- - * BR0,BR1 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR0,OR1 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0 - Primary FLASH - */ - -/* BR0 is configured as follows: - * - * - Base address of 0x40000000 - * - 16 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR0 is configured as follows: - * - * - 4 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR2,BR3 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2,OR3 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* Bank 2,3 - SDRAM DIMM - */ - -/* The BR2 is configured as follows: - * - * - Base address of 0x00000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 64 MB DIMM, the OR2 is configured as follows: - * - * - 64 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CFG_SDRAM0_SIZE == 64) -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ - -/* Address that the DIMM SPD memory lives at. - */ -#define SDRAM_SPD_ADDR 0x50 - -#if (CFG_SDRAM0_SIZE == 64) -/* With a 64 MB DIMM, the PSDMR is configured as follows: - * - * - Bank Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A14-A16 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ -#define CFG_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#else -#error "INVALID SDRAM CONFIGURATION" -#endif - -/* - * Shoot for approximately 1MHz on the prescaler. - */ -#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000)) -#define CFG_MPTPR MPTPR_PTP_DIV64 -#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000)) -#define CFG_MPTPR MPTPR_PTP_DIV32 -#else -#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK" -#define CFG_MPTPR MPTPR_PTP_DIV32 -#endif -#define CFG_PSRT 14 - - -/*----------------------------------------------------------------------- - * BR6 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR6 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 6 - Secondary FLASH - * - * The secondary FLASH is connected to *CS6 - */ -#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) - -/* BR6 is configured as follows: - * - * - Base address of 0x60000000 - * - 16 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR6 is configured as follows: - * - * - 2 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) -#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h deleted file mode 100644 index beff28a..0000000 --- a/include/configs/sbc405.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * (C) Copyright 2001 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo" - -#define CONFIG_RAMBOOT \ - "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000 ffca0000" -#define CONFIG_NFSBOOT \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */ - - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \ - "e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \ - "f=0x08 tn=sbc405 o=emac \0" \ - "env_startaddr=FF000000\0" \ - "env_endaddr=FF03FFFF\0" \ - "loadfile=vxWorks.st\0" \ - "loadaddr=0x01000000\0" \ - "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ - "uboot_startaddr=FFFC0000\0" \ - "uboot_endaddr=FFFFFFFF\0" \ - "update=tftp ${loadaddr} u-boot.bin;" \ - "protect off ${uboot_startaddr} ${uboot_endaddr};" \ - "era ${uboot_startaddr} ${uboot_endaddr};" \ - "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \ - "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \ - "zapenv=protect off ${env_startaddr} ${env_endaddr};" \ - "era ${env_startaddr} ${env_endaddr};" \ - "protect on ${env_startaddr} ${env_endaddr}\0" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_SDRAM | \ - 0 ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ -#define CONFIG_IPADDR 192.168.193.102 -#define CONFIG_NETMASK 255.255.255.224 -#define CONFIG_SERVERIP 192.168.193.119 -#define CONFIG_GATEWAYIP 192.168.193.97 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */ -#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MONITOR_BASE 0xFFFC0000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_BASE 0xFF000000 -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_INCREMENT 0x01000000 -#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CFG_ENV_ADDR CFG_FLASH_BASE /* starting right at the beginning */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ -#define FLASH0_BA CFG_FLASH_BASE /* FLASH 0 Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x92015480 -#define CFG_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x1000 - -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 -#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h deleted file mode 100644 index d891e07..0000000 --- a/include/configs/sbc8240.h +++ /dev/null @@ -1,365 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Configuration settings for the sbc8240 board. - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_WRSBC8240 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND "version;echo;tftpboot $loadaddr $loadfile;bootvx" /* autoboot command */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st " \ - "e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 " \ - "tn=sbc8240 o=fei \0" \ - "env_startaddr=FFF70000\0" \ - "env_endaddr=FFF7FFFF\0" \ - "loadfile=vxWorks.st\0" \ - "loadaddr=0x01000000\0" \ - "net_load=tftpboot $loadaddr $loadfile\0" \ - "uboot_startaddr=FFF00000\0" \ - "uboot_endaddr=FFF3FFFF\0" \ - "update=tftp $loadaddr /u-boot.bin;" \ - "protect off $uboot_startaddr $uboot_endaddr;" \ - "era $uboot_startaddr $uboot_endaddr;" \ - "cp.b $loadaddr $uboot_startaddr $filesize;" \ - "protect on $uboot_startaddr $uboot_endaddr\0" \ - "zapenv=protect off $env_startaddr $env_endaddr;" \ - "era $env_startaddr $env_endaddr;" \ - "protect on $env_startaddr $env_endaddr\0" - -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_SDRAM | \ - 0 ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -#if 1 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ -#define CONFIG_IPADDR 192.168.193.102 -#define CONFIG_NETMASK 255.255.255.248 -#define CONFIG_SERVERIP 192.168.193.99 - -#define CONFIG_STATUS_LED /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -#define STATUS_LED_BIT 0x00000001 -#define STATUS_LED_PERIOD (CFG_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifndef __ASSEMBLY__ -/* LEDs */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - *((volatile char *) (CFG_LED_BASE)) ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - *((volatile char *) (CFG_LED_BASE)) |= (_msk); \ - else \ - *((volatile char *) (CFG_LED_BASE)) &= ~(_msk); \ - } while(0) - -#define __led_init(msk, st) __led_set(msk, st) - -#endif - -#define CONFIG_MISC_INIT_R -#define CFG_LED_BASE 0xFFE80000 - -/* Print Buffer Size - */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF00000 - -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_EUMB_ADDR 0xFCE00000 - -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CFG_MAX_RAM_SIZE 0x10000000 - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#undef CFG_RAMBOOT -#else -#define CFG_RAMBOOT -#endif - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - - /* Size in bytes reserved for initial data - */ -#define CFG_GBL_DATA_SIZE 128 - -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#define CFG_NS16550_CLK 3686400 - -#define CFG_NS16550_COM1 0xFFF80000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 -#define CFG_HZ 1000 -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 - - /* Bit-field values for MCCR1. - */ -#define CFG_ROMNAL 0 -#define CFG_ROMFAL 7 - - /* Bit-field values for MCCR2. - */ -#define CFG_REFINT 430 /* Refresh interval */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CFG_BSTOPRE 192 - - /* Bit-field values for MCCR3. - */ -#define CFG_REFREC 2 /* Refresh to activate interval */ -#define CFG_RDLAT 3 /* Data latancy from read command */ - - /* Bit-field values for MCCR4. - */ -#define CFG_PRETOACT 2 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ -#define CFG_ACTORW 2 -#define CFG_REGISTERD_TYPE_BUFFER 1 - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff -#define CFG_BANK7_ENABLE 0 - -#define CFG_ODCR 0xff - -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CFG_MAX_FLASH_SECT 256 /* Max number of sectors in one bank */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - - /* Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0xFFF70000 -#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */ -#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* we need Plug 'n Play */ -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ -#define CONFIG_TULIP -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h deleted file mode 100644 index 180ce05..0000000 --- a/include/configs/sbc8260.h +++ /dev/null @@ -1,1088 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen - * - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2001 - * Advent Networks, Inc. - * Jay Monkman - * - * Configuration settings for the WindRiver SBC8260 board. - * See http://www.windriver.com/products/html/sbc8260.html - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Enable debug prints */ -#undef DEBUG /* General debug */ -#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ - -/***************************************************************************** - * - * These settings must match the way _your_ board is set up - * - *****************************************************************************/ - -/* What is the oscillator's (UX2) frequency in Hz? */ -#define CONFIG_8260_CLKIN (66 * 1000 * 1000) - -/*----------------------------------------------------------------------- - * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual - *----------------------------------------------------------------------- - * What should MODCK_H be? It is dependent on the oscillator - * frequency, MODCK[1-3], and desired CPM and core frequencies. - * Here are some example values (all frequencies are in MHz): - * - * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 - * ------- ---------- --- --- ---- ----- ----- ----- - * 0x1 0x5 33 100 133 Open Close Open - * 0x1 0x6 33 100 166 Open Open Close - * 0x1 0x7 33 100 200 Open Open Open - * - * 0x2 0x2 33 133 133 Close Open Close - * 0x2 0x3 33 133 166 Close Open Open - * 0x2 0x4 33 133 200 Open Close Close - * 0x2 0x5 33 133 233 Open Close Open - * 0x2 0x6 33 133 266 Open Open Close - * - * 0x5 0x5 66 133 133 Open Close Open - * 0x5 0x6 66 133 166 Open Open Close - * 0x5 0x7 66 133 200 Open Open Open - * 0x6 0x0 66 133 233 Close Close Close - * 0x6 0x1 66 133 266 Close Close Open - * 0x6 0x2 66 133 300 Close Open Close - */ -#define CFG_SBC_MODCK_H 0x05 - -/* Define this if you want to boot from 0x00000100. If you don't define - * this, you will need to program the bootloader to 0xfff00000, and - * get the hardware reset config words at 0xfe000000. The simplest - * way to do that is to program the bootloader at both addresses. - * It is suggested that you just let U-Boot live at 0x00000000. - */ -#define CFG_SBC_BOOT_LOW 1 - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk - * The main FLASH is whichever is connected to *CS0. U-Boot expects - * this to be the SIMM. - */ -#define CFG_FLASH0_BASE 0x40000000 -#define CFG_FLASH0_SIZE 4 - -/* What should the base address of the secondary FLASH be and how big - * is it (in Mbytes)? The secondary FLASH is whichever is connected - * to *CS6. U-Boot expects this to be the on board FLASH. If you don't - * want it enabled, don't define these constants. - */ -#define CFG_FLASH1_BASE 0x60000000 -#define CFG_FLASH1_SIZE 2 - -/* What should be the base address of SDRAM DIMM and how big is - * it (in Mbytes)? -*/ -#define CFG_SDRAM0_BASE 0x00000000 -#define CFG_SDRAM0_SIZE 64 - -/* What should be the base address of the LEDs and switch S0? - * If you don't want them enabled, don't define this. - */ -#define CFG_LED_BASE 0xa0000000 - - -/* - * SBC8260 with 16 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x00F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x00F5 FFB0 Board Info Data - * 0x00F6 0000 Malloc Arena - * : CFG_ENV_SECT_SIZE, 256k - * : CFG_MALLOC_LEN, 128k - * 0x00FC 0000 RAM Copy of Monitor Code - * : CFG_MONITOR_LEN, 256k - * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 - */ - -/* - * SBC8260 with 64 MB DIMM: - * - * 0x0000 0000 Exception Vector code, 8k - * : - * 0x0000 1FFF - * 0x0000 2000 Free for Application Use - * : - * : - * - * : - * : - * 0x03F5 FF30 Monitor Stack (Growing downward) - * Monitor Stack Buffer (0x80) - * 0x03F5 FFB0 Board Info Data - * 0x03F6 0000 Malloc Arena - * : CFG_ENV_SECT_SIZE, 256k - * : CFG_MALLOC_LEN, 128k - * 0x03FC 0000 RAM Copy of Monitor Code - * : CFG_MONITOR_LEN, 256k - * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1 - */ - - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere. - */ -#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on neither */ -#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - */ - -#undef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_ON_FCC -#undef CONFIG_ETHER_NONE /* define if ethernet on neither */ - -#ifdef CONFIG_ETHER_ON_SCC -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif /* CONFIG_ETHER_ON_SCC */ - -#ifdef CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */ -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * Port pins used for bit-banged MII communictions (if applicable). - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) -#endif /* CONFIG_ETHER_ON_FCC */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CFG_CPMFCR_RAMTYPE 0 -# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -/* - * Select SPI support configuration - */ -#undef CONFIG_SPI /* Disable SPI driver */ - -/* - * Select i2c support configuration - * - * Supported configurations are {none, software, hardware} drivers. - * If the software driver is chosen, there are some additional - * configuration items that the driver uses to drive the port pins. - */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ -#ifdef CONFIG_SOFT_I2C -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - - -/* Define this to reserve an entire FLASH sector (256 KB) for - * environment variables. Otherwise, the environment will be - * put in the same sector as U-Boot, and changing variables - * will erase U-Boot temporarily - */ -#define CFG_ENV_IN_OWN_SECT 1 - -/* Define to allow the user to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* What should the console's baud rate be? */ -#define CONFIG_BAUDRATE 9600 - -/* Ethernet MAC address - * Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx) - * http://standards.ieee.org/regauth/oui/index.shtml - */ -#define CONFIG_ETHADDR 00:a0:1e:a8:7b:cb - -/* - * Define this to set the last octet of the ethernet address from the - * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7 - * switch and the LEDs are backwards with respect to each other. DS7 - * is on the board edge side of both the LED strip and the DS0-DS7 - * switch. - */ -#undef CONFIG_MISC_INIT_R - -/* Set to a positive value to delay for running BOOTCOMMAND */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#undef CONFIG_AUTOBOOT_KEYED -#ifdef CONFIG_AUTOBOOT_KEYED -# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n" -# define CONFIG_AUTOBOOT_STOP_STR " " -# undef CONFIG_AUTOBOOT_DELAY_STR -# define DEBUG_BOOTKEYS 0 -#endif - -/* Define this to contain any number of null terminated strings that - * will be part of the default enviroment compiled into the boot image. - * - * Variable Usage - * -------------- ------------------------------------------------------- - * serverip server IP address - * ipaddr my IP address - * reprog Reload flash with a new copy of U-Boot - * zapenv Erase the environment area in flash - * root-on-initrd Set the bootcmd variable to allow booting of an initial - * ram disk. - * root-on-nfs Set the bootcmd variable to allow booting of a NFS - * mounted root filesystem. - * boot-hook Convenient stub to do something useful before the - * bootm command is executed. - * - * Example usage of root-on-initrd and root-on-nfs : - * - * Note: The lines have been wrapped to improved its readability. - * - * => printenv bootcmd - * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw - * nfsroot=${serverip}:${rootpath} - * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm - * - * => run root-on-initrd - * => printenv bootcmd - * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw - * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm - * - * => run root-on-nfs - * => printenv bootcmd - * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw - * nfsroot=${serverip}:${rootpath} - * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm - * - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "serverip=192.168.123.205\0" \ - "ipaddr=192.168.123.213\0" \ - "reprog="\ - "bootp;" \ - "tftpboot 0x140000 /bdi2000/u-boot.bin;" \ - "protect off 1:0;" \ - "erase 1:0;" \ - "cp.b 140000 40000000 ${filesize};" \ - "protect on 1:0\0" \ - "zapenv="\ - "protect off 1:1;" \ - "erase 1:1;" \ - "protect on 1:1\0" \ - "root-on-initrd="\ - "setenv bootcmd "\ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run boot-hook;" \ - "bootm\0" \ - "root-on-nfs="\ - "setenv bootcmd "\ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "run boot-hook;" \ - "bootm\0" \ - "boot-hook=echo\0" - -/* Define a command string that is automatically executed when no character - * is read on the console interface withing "Boot Delay" after reset. - */ -#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ -#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ - -#ifdef CONFIG_BOOT_ROOT_INITRD -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/ram0 rw " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_INITRD */ - -#ifdef CONFIG_BOOT_ROOT_NFS -#define CONFIG_BOOTCOMMAND \ - "version;" \ - "echo;" \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -#endif /* CONFIG_BOOT_ROOT_NFS */ - -/* Add support for a few extra bootp options like: - * - File size - * - DNS (up to 2 servers) - * - Send hostname to DHCP server - */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME) - -/* undef this to save memory */ -#define CFG_LONGHELP - -/* Monitor Command Prompt */ -#define CFG_PROMPT "=> " - -#undef CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time) - * of an image is printed by image commands like bootm or iminfo. - */ -#define CONFIG_TIMESTAMP - -/* If this variable is defined, an environment variable named "ver" - * is created by U-Boot showing the U-Boot version. - */ -#define CONFIG_VERSION_VARIABLE - -/* What U-Boot subsytems do you want enabled? */ -#ifdef CONFIG_ETHER_ON_FCC -# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM ) -#else -# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IMMAP | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM ) -#endif /* CONFIG_ETHER_ON_FCC */ - -#undef CONFIG_WATCHDOG /* disable the watchdog */ - -/* Where do the internal registers live? */ -#define CFG_IMMR 0xF0000000 - -/***************************************************************************** - * - * You should not have to modify any of the following settings - * - *****************************************************************************/ - -#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ -#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16) - -#define CFG_MAXARGS 32 /* max number of command args */ - -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_ALT_MEMTEST /* Select full-featured memory test */ -#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ - + CFG_MALLOC_LEN \ - + CFG_ENV_SECT_SIZE \ - + CFG_STACK_USAGE ) - -#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ - - CFG_MEM_END_USAGE ) - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CFG_FLASH_BASE CFG_FLASH0_BASE -#define CFG_FLASH_SIZE CFG_FLASH0_SIZE -#define CFG_SDRAM_BASE CFG_SDRAM0_BASE -#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - */ -#if defined(CFG_SBC_BOOT_LOW) -# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) -#else -# define CFG_SBC_HRCW_BOOT_FLAGS (0) -#endif /* defined(CFG_SBC_BOOT_LOW) */ - -/* get the HRCW ISB field from CFG_IMMR */ -#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ - ((CFG_IMMR & 0x01000000) >> 7) | \ - ((CFG_IMMR & 0x00100000) >> 4) ) - -#define CFG_HRCW_MASTER ( HRCW_BPS11 | \ - HRCW_DPPC11 | \ - CFG_SBC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC11 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \ - CFG_SBC_HRCW_BOOT_FLAGS ) - -/* no slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - * Note also that the logic that sets CFG_RAMBOOT is platform dependent. - */ -#define CFG_MONITOR_BASE CFG_FLASH0_BASE - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -#ifndef CFG_RAMBOOT -# define CFG_ENV_IS_IN_FLASH 1 - -# ifdef CFG_ENV_IN_OWN_SECT -# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) -# define CFG_ENV_SECT_SIZE 0x40000 -# else -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE) -# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ -# endif /* CFG_ENV_IN_OWN_SECT */ - -#else -# define CFG_ENV_IS_IN_NVRAM 1 -# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) -# define CFG_ENV_SIZE 0x200 -#endif /* CFG_RAMBOOT */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CFG_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) - -#define CFG_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) -#define CFG_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register - *----------------------------------------------------------------------- - */ -#define CFG_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CFG_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ - -#define CFG_SIUMCR (SIUMCR_DPPC11 |\ - SIUMCR_L2CPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_MMR00) - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP |\ - SYPCR_SWE) -#else -#define CFG_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CFG_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CFG_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - */ -#define CFG_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CFG_RCCR 0 - -/* - * Initialize Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) * - * 1 60x GPCM 32 bit FLASH (SIMM - Unused) - * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB) - * 3 60x SDRAM 64 bit SDRAM (DIMM - Unused) - * 4 Local SDRAM 32 bit SDRAM (on board - 4MB) - * 5 60x GPCM 8 bit EEPROM (8KB) - * 6 60x GPCM 8 bit FLASH (on board - 2MB) * - * 7 60x GPCM 8 bit LEDs, switches - * - * (*) This configuration requires the SBC8260 be configured - * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to - * the on board FLASH. In other words, JP24 should have - * pins 1 and 2 jumpered and pins 3 and 4 jumpered. - * - */ - -/*----------------------------------------------------------------------- - * BR0,BR1 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR0,OR1 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 0,1 - FLASH SIMM - * - * This expects the FLASH SIMM to be connected to *CS0 - * It consists of 4 AM29F080B parts. - * - * Note: For the 4 MB SIMM, *CS1 is unused. - */ - -/* BR0 is configured as follows: - * - * - Base address of 0x40000000 - * - 32 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR0 is configured as follows: - * - * - 4 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) - -/*----------------------------------------------------------------------- - * BR2,BR3 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR2,OR3 - Option Register - * Ref: Section 10.3.2 on page 10-16 - *----------------------------------------------------------------------- - */ - -/* Bank 2,3 - SDRAM DIMM - * - * 16MB DIMM: P/N - * 64MB DIMM: P/N 1W-8864X8-4-P1-EST - * - * Note: *CS3 is unused for this DIMM - */ - -/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows: - * - * - Base address of 0x00000000 - * - 64 bit port size (60x bus only) - * - Data errors checking is disabled - * - Read and write access - * - SDRAM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -/* With a 16 MB DIMM, the OR2 is configured as follows: - * - * - 16 MB - * - 2 internal banks per device - * - Row start address bit is A9 with PSDMR[PBI] = 0 - * - 11 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CFG_SDRAM0_SIZE == 16) -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_2 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_11) -#endif - -/* With a 64 MB DIMM, the OR2 is configured as follows: - * - * - 64 MB - * - 4 internal banks per device - * - Row start address bit is A8 with PSDMR[PBI] = 0 - * - 12 row address lines - * - Back-to-back page mode - * - Internal bank interleaving within save device enabled - */ -#if (CFG_SDRAM0_SIZE == 64) -#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) -#endif - -/*----------------------------------------------------------------------- - * PSDMR - 60x Bus SDRAM Mode Register - * Ref: Section 10.3.3 on page 10-21 - *----------------------------------------------------------------------- - */ - -/* Address that the DIMM SPD memory lives at. - */ -#define SDRAM_SPD_ADDR 0x54 - -#if (CFG_SDRAM0_SIZE == 16) -/* With a 16 MB DIMM, the PSDMR is configured as follows: - * - * - Bank Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A16-A18 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ -#define CFG_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A16_A18 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#endif - -#if (CFG_SDRAM0_SIZE == 64) -/* With a 64 MB DIMM, the PSDMR is configured as follows: - * - * - Bank Based Interleaving, - * - Refresh Enable, - * - Address Multiplexing where A5 is output on A14 pin - * (A6 on A15, and so on), - * - use address pins A14-A16 as bank select, - * - A9 is output on SDA10 during an ACTIVATE command, - * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, - * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 3 clocks, - * - earliest timing for READ/WRITE command after ACTIVATE command is - * 2 clocks, - * - earliest timing for PRECHARGE after last data was read is 1 clock, - * - earliest timing for PRECHARGE after last data was written is 1 clock, - * - CAS Latency is 2. - */ -#define CFG_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) -#endif - -/* - * Shoot for approximately 1MHz on the prescaler. - */ -#if (CONFIG_8260_CLKIN == (66 * 1000 * 1000)) -#define CFG_MPTPR MPTPR_PTP_DIV64 -#elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000)) -#define CFG_MPTPR MPTPR_PTP_DIV32 -#else -#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK" -#define CFG_MPTPR MPTPR_PTP_DIV32 -#endif -#define CFG_PSRT 14 - - -/* Bank 4 - On board SDRAM - * - * This is not implemented yet. - */ - -/*----------------------------------------------------------------------- - * BR6 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR6 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 6 - On board FLASH - * - * This expects the on board FLASH SIMM to be connected to *CS6 - * It consists of 1 AM29F016A part. - */ -#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) - -/* BR6 is configured as follows: - * - * - Base address of 0x60000000 - * - 8 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR6 is configured as follows: - * - * - 2 MB - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 5 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) -#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */ - -/*----------------------------------------------------------------------- - * BR7 - Base Register - * Ref: Section 10.3.1 on page 10-14 - * OR7 - Option Register - * Ref: Section 10.3.2 on page 10-18 - *----------------------------------------------------------------------- - */ - -/* Bank 7 - LEDs and switches - * - * LEDs are at 0x00001 (write only) - * switches are at 0x00001 (read only) - */ -#ifdef CFG_LED_BASE - -/* BR7 is configured as follows: - * - * - Base address of 0xA0000000 - * - 8 bit port size - * - Data errors checking is disabled - * - Read and write access - * - GPCM 60x bus - * - Access are handled by the memory controller according to MSEL - * - Not used for atomic operations - * - No data pipelining is done - * - Valid - */ -# define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -/* OR7 is configured as follows: - * - * - 1 byte - * - *BCTL0 is asserted upon access to the current memory bank - * - *CW / *WE are negated a quarter of a clock earlier - * - *CS is output at the same time as the address lines - * - Uses a clock cycle length of 15 - * - *PSDVAL is generated internally by the memory controller - * unless *GTA is asserted earlier externally. - * - Relaxed timing is generated by the GPCM for accesses - * initiated to this memory region. - * - One idle clock is inserted between a read access from the - * current bank and the next access. - */ -# define CFG_OR7_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_15_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) -#endif /* CFG_LED_BASE */ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h deleted file mode 100644 index 5a434dc..0000000 --- a/include/configs/sbc8560.h +++ /dev/null @@ -1,404 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * (C) Copyright 2004 Wind River Systems Inc . - * Added support for Wind River SBC8560 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ - - -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ - -/* XXX flagging this as something I might want to delete */ -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_PCI /* pci ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ - - -#define CONFIG_ENV_OVERWRITE - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. - */ -#undef CONFIG_RAM_AS_FLASH - -#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ - #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ -#else - #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ - -#if XXX - #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#else - #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ -#endif -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ -#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ - -#if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -#else /* Boot from real Flash */ - #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ - #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ - #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -#endif -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* local bus definitions */ -#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -#define CFG_OR1_PRELIM 0xfc000ff7 - -#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ -#define CFG_OR2_PRELIM 0x00000000 - -#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CFG_OR3_PRELIM 0xfc000cc1 - -#if defined(CONFIG_RAM_AS_FLASH) - #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -#else - #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -#endif -#define CFG_OR4_PRELIM 0xfc000cc1 - -#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ -#if 1 - #define CFG_OR5_PRELIM 0xff000ff7 -#else - #define CFG_OR5_PRELIM 0xff0000f0 -#endif - -#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -#define CFG_OR6_PRELIM 0xfc000ff7 -#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 - -/* just hijack the MOT BCSR def for SBC8560 misc devices */ -#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) -/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ -#define CONFIG_BAUDRATE 9600 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) -#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ - -#define CFG_PCI_MEM_BASE 0xC0000000 -#define CFG_PCI_MEM_PHYS 0xC0000000 -#define CFG_PCI_MEM_SIZE 0x10000000 - -#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ - -# define CONFIG_NET_MULTI 1 -# define CONFIG_MII 1 /* MII PHY management */ -# define CONFIG_MPC85xx_TSEC1 -# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" -# define TSEC1_PHY_ADDR 25 -# define TSEC1_PHYIDX 0 -/* Options are: TSEC0 */ -# define CONFIG_ETHPRIME "TSEC0" - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - - #undef CONFIG_ETHER_NONE /* define if ether on something else */ - #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ - #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - - #if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) - - #elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #endif /* CONFIG_ETHER_INDEX */ - - #define CONFIG_MII /* MII PHY management */ - #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - /* - * GPIO pins used for bit-banged MII communications - */ - #define MDIO_PORT 2 /* Port C */ - #define MDIO_ACTIVE (iop->pdir |= 0x00400000) - #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) - #define MDIO_READ ((iop->pdat & 0x00400000) != 0) - - #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - - #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - - #define MIIDELAY udelay(1) - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if 0 -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_PROTECTION /* use hardware protection */ -#endif -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if 0 -/* XXX This doesn't work and I don't want to fix it */ -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) - #define CFG_RAMBOOT -#else - #undef CFG_RAMBOOT -#endif -#endif - -/* Environment */ -#if !defined(CFG_RAMBOOT) - #if defined(CONFIG_RAM_AS_FLASH) - #define CFG_ENV_IS_NOWHERE - #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) - #define CFG_ENV_SIZE 0x2000 - #else - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) - #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ - #endif -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) - #endif -#endif - -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*Note: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -# define CONFIG_ETHADDR 00:01:af:07:9b:8a -# define CONFIG_HAS_ETH1 -# define CONFIG_ETH1ADDR 00:01:af:07:9b:8b -# define CONFIG_HAS_ETH2 -# define CONFIG_ETH2ADDR 00:01:af:07:9b:8c -#endif - -#define CONFIG_SERVERIP 192.168.0.131 -#define CONFIG_IPADDR 192.168.0.105 -#define CONFIG_GATEWAYIP 0.0.0.0 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME SBC8560 -#define CONFIG_ROOTPATH /home/ppc -#define CONFIG_BOOTFILE pImage - -#endif /* __CONFIG_H */ diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h deleted file mode 100644 index d7d07a6..0000000 --- a/include/configs/sc520_cdp.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_X86 1 /* This is a X86 CPU */ -#define CONFIG_SC520 1 /* Include support for AMD SC520 */ -#define CONFIG_ALI152X 1 /* Include support for Ali 152x SIO */ - -#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */ -#define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */ -#define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */ - -/* define at most one of these */ -#undef CFG_SDRAM_CAS_LATENCY_2T -#define CFG_SDRAM_CAS_LATENCY_3T - -#define CFG_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ -#define CFG_RESET_GENERIC 1 /* use tripple-fault to reset cpu */ -#undef CFG_RESET_SC520 /* use SC520 MMCR's to reset cpu */ -#undef CFG_TIMER_SC520 /* use SC520 swtimers */ -#define CFG_TIMER_GENERIC 1 /* use the i8254 PIT timers */ -#undef CFG_TIMER_TSC /* use the Pentium TSC timers */ -#define CFG_USE_SIO_UART 0 /* prefer the uarts on the SIO to those - * in the SC520 on the CDP */ - -#define CFG_STACK_SIZE 0x8000 /* Size of bootloader stack */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 -#define CONFIG_LAST_STAGE_INIT 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) - - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_EEPROM) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 15 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" -/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "boot > " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1024 /* incrementer freq: 1kHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - - -#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#define CONFIG_SPI_EEPROM /* Support for SPI EEPROMs (AT25128) */ -#define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */ - - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - - -/* Environment in EEPROM */ -#define CFG_ENV_IS_IN_EEPROM 1 -#define CONFIG_SPI -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment EEPROM 16k is SPI is used or 128 bytes if MW is used*/ -#define CFG_ENV_OFFSET 0 -#define CONFIG_SC520_CDP_USE_SPI /* Store configuration in the SPI part */ -#undef CONFIG_SC520_CDP_USE_MW /* Store configuration in the MicroWire part */ -#define CONFIG_SPI_X 1 - -/* - * JFFS2 partitions - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=SC520CDP Flash Bank #0" -#define MTDPARTS_DEFAULT "mtdparts=SC520CDP Flash Bank #0:-(jffs2)" -*/ - -/*----------------------------------------------------------------------- - * Device drivers - */ -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ -#define CONFIG_PCNET -#define CONFIG_PCNET_79C973 -#define CONFIG_PCNET_79C975 -#define PCNET_HAS_PROM 1 - -/************************************************************ - * IDE/ATA stuff - ************************************************************/ -#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -/*#define CFG_ATA_IDE1_OFFSET 0x0170 /###* ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ -#define CFG_ATA_BASE_ADDR 0 - -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide unsupported... */ -#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ - -/************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI /* enable ATAPI Support */ - -/************************************************************ - * DISK Partition support - ************************************************************/ -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION /* Experimental */ - -/************************************************************ - * Video/Keyboard support - ************************************************************/ -#define CONFIG_VIDEO /* To enable video controller support */ -#define CONFIG_I8042_KBD -#define CFG_ISA_IO 0 - - -/************************************************************ - * RTC - ***********************************************************/ -#define CONFIG_RTC_MC146818 -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW - -#define CFG_FIRST_PCI_IRQ 10 -#define CFG_SECOND_PCI_IRQ 9 -#define CFG_THIRD_PCI_IRQ 11 -#define CFG_FORTH_PCI_IRQ 15 - -#endif /* __CONFIG_H */ diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h deleted file mode 100644 index a8e3555..0000000 --- a/include/configs/sc520_spunk.h +++ /dev/null @@ -1,225 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_X86 1 /* This is a X86 CPU */ -#define CONFIG_SC520 1 /* Include support for AMD SC520 */ - -#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */ -#define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */ -#define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */ - -/* define at most one of these */ -#undef CFG_SDRAM_CAS_LATENCY_2T -#define CFG_SDRAM_CAS_LATENCY_3T - -#define CFG_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ -#define CFG_RESET_GENERIC 1 /* use tripple-fault to reset cpu */ -#undef CFG_RESET_SC520 /* use SC520 MMCR's to reset cpu */ -#undef CFG_TIMER_SC520 /* use SC520 swtimers */ -#define CFG_TIMER_GENERIC 1 /* use the i8254 PIT timers */ -#undef CFG_TIMER_TSC /* use the Pentium TSC timers */ - -#define CFG_STACK_SIZE 0x8000 /* Size of bootloader stack */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 -#define CONFIG_LAST_STAGE_INIT 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) - - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_PCMCIA | CFG_CMD_EEPROM) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 15 -#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) " -#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "boot > " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1024 /* incrementer freq: 1kHz */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - - -#define CONFIG_SPI_EEPROM /* SPI EEPROMs such as AT25010 or AT25640 */ -#define CONFIG_MW_EEPROM /* MicroWire EEPROMS such as AT93LC46 */ -#define CONFIG_DS1722 /* Dallas DS1722 SPI Temperature probe */ - - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - - -#if 0 -/* Environment in flash */ -#define CFG_ENV_IS_IN_FLASH 1 -# define CFG_ENV_ADDR (0x387a0000) /* Addr of Environment Sector */ -# define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector (or 0x10000) */ -# define CFG_ENV_OFFSET 0 - -#else -/* Environment in EEPROM */ - -# define CFG_ENV_IS_IN_EEPROM 1 -# define CONFIG_SPI -# define CONFIG_SPI_X 1 -# define CFG_ENV_SIZE 0x2000 /* Total Size of Environment EEPROM */ -# define CFG_ENV_OFFSET 0x1c00 - -#endif - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=sc520_spunk-0" -#define MTDPARTS_DEFAULT "mtdparts=sc520_spunk-0:-(jffs2)" -*/ - -/*----------------------------------------------------------------------- - * Device drivers - */ -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -/************************************************************ - * IDE/ATA stuff - ************************************************************/ -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ -#define CFG_ATA_BASE_ADDR 0 -#define CFG_ATA_IDE0_OFFSET 0x01f0 /* ide0 offset */ -#define CFG_ATA_IDE1_OFFSET 0xe000 /* ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ - -#define CFG_FIRST_PCMCIA_BUS 1 - -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide unsupported... */ -#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ - -#define CONFIG_IDE_TI_CARDBUS -#define CFG_PCMCIA_CIS_WIN 0x27f00000 -#define CFG_PCMCIA_CIS_WIN_SIZE 0x00100000 -#define CFG_PCMCIA_IO_WIN 0xe000 -#define CFG_PCMCIA_IO_WIN_SIZE 16 - -/************************************************************ - * DISK Partition support - ************************************************************/ -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION /* Experimental */ - - -/************************************************************ - * RTC - ***********************************************************/ -#define CONFIG_RTC_MC146818 -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW - -#define CFG_FIRST_PCI_IRQ 9 -#define CFG_SECOND_PCI_IRQ 10 -#define CFG_THIRD_PCI_IRQ 11 -#define CFG_FORTH_PCI_IRQ 12 - -#endif /* __CONFIG_H */ diff --git a/include/configs/sc520_spunk_rel.h b/include/configs/sc520_spunk_rel.h deleted file mode 100644 index 2e7a7e1..0000000 --- a/include/configs/sc520_spunk_rel.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _outer_config -#define _outer_config - -#include "sc520_spunk.h" - -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "fsload boot/vmlinuz ; bootm" - -#endif diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h deleted file mode 100644 index a4249c4..0000000 --- a/include/configs/scb9328.h +++ /dev/null @@ -1,356 +0,0 @@ -/* - * Copyright (C) 2003 ETC s.r.o. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Written by Peter Figuli , 2003. - * - * 2003/13/06 Initial MP10 Support copied from wepep250 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ -#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ -#define CONFIG_SCB9328 1 /* on a scb9328tronix board */ -#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ - -#define CONFIG_IMX_SERIAL1 -/* - * Select serial console configuration - */ - - -/* - * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if - * neccessary in include/cmd_confdefs.h file. (Un)comment for getting - * functionality or size of u-boot code. - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - & ~CFG_CMD_LOADS \ - & ~CFG_CMD_CONSOLE \ - & ~CFG_CMD_AUTOSCRIPT \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - | CFG_CMD_DHCP \ - ) - -#include - -/* - * Boot options. Setting delay to -1 stops autostart count down. - * NOTE: Sending parameters to kernel depends on kernel version and - * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept - * parameters at all! Do not get confused by them so. - */ -#define CONFIG_BOOTDELAY -1 -#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328" -#define CONFIG_BOOTCOMMAND "bootm 10040000" -#define CONFIG_SHOW_BOOT_PROGRESS -#define CONFIG_ETHADDR 80:81:82:83:84:85 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.10.10.9 -#define CONFIG_SERVERIP 10.10.10.10 - -/* - * General options for u-boot. Modify to save memory foot print - */ -#define CFG_LONGHELP /* undef saves memory */ -#define CFG_PROMPT "scb9328> " /* prompt string */ -#define CFG_CBSIZE 256 /* console I/O buffer */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ -#define CFG_MAXARGS 16 /* max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ - -#define CFG_MEMTEST_START 0x08100000 /* memtest test area */ -#define CFG_MEMTEST_END 0x08F00000 - -#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x141 /* core clock - register value */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BAUDRATE 115200 -/* - * Definitions related to passing arguments to kernel. - */ -#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG 1 /* send initrd params */ -#undef CONFIG_VFD /* do not send framebuffer setup */ - - -/* - * Malloc pool need to host env + 128 Kb reserve for other allocations. - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CONFIG_STACKSIZE (120<<10) /* stack size */ - -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ -#endif - -/* SDRAM Setup Values -0x910a8300 Precharge Command CAS 3 -0x910a8200 Precharge Command CAS 2 - -0xa10a8300 AutoRefresh Command CAS 3 -0xa10a8200 Set AutoRefresh Command CAS 2 */ - -#define PRECHARGE_CMD 0x910a8200 -#define AUTOREFRESH_CMD 0xa10a8200 - -/* - * SDRAM Memory Map - */ -/* SH FIXME */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ -#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ - -/* - * Flash Controller settings - */ - -/* - * Hardware drivers - */ - - -/* - * Configuration for FLASH memory for the Synertronixx board - */ - -/* #define SCB9328_FLASH_32M */ - -/* 32MB */ -#ifdef SCB9328_FLASH_32M -#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ -#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ -#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ -#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */ -#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ -#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ -#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ -#else - -/* 16MB */ -#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ -#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ -#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ -#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */ -#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ -#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ -#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ -#endif /* SCB9328_FLASH_32M */ - -/* This should be defined if CFI FLASH device is present. Actually benefit - is not so clear to me. In other words we can provide more informations - to user, but this expects more complex flash handling we do not provide - now.*/ -#undef CFG_FLASH_CFI - -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ - -#define CFG_FLASH_BASE SCB9328_FLASH_BASE - -/* - * This is setting for JFFS2 support in u-boot. - * Right now there is no gain for user, but later on booting kernel might be - * possible. Consider using XIP kernel running from flash to save RAM - * footprint. - * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. - */ -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_FIRST_SECTOR 5 -#define CFG_JFFS2_NUM_BANKS 1 - -/* - * Environment setup. Definitions of monitor location and size with - * definition of environment setup ends up in 2 possibilities. - * 1. Embeded environment - in u-boot code is space for environment - * 2. Environment is read from predefined sector of flash - * Right now we support 2. possiblity, but expecting no env placed - * on mentioned address right now. This also needs to provide whole - * sector for it - for us 256Kb is really waste of memory. U-boot uses - * default env. and until kernel parameters could be sent to kernel - * env. has no sense to us. - */ - -/* Setup for PA23 which is Reset Default PA23 but has to become - CS5 */ - -#define CFG_GPR_A_VAL 0x00800000 -#define CFG_GIUS_A_VAL 0x0043fffe - -#define CFG_MONITOR_BASE 0x10000000 -#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */ -#define CFG_ENV_SIZE 0x20000 - -#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ - -/* - * CSxU_VAL: - * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 - * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | - * - * CSxL_VAL: - * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 - * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| - */ - -#define CFG_CS0U_VAL 0x000F2000 -#define CFG_CS0L_VAL 0x11110d01 -#define CFG_CS1U_VAL 0x000F0a00 -#define CFG_CS1L_VAL 0x11110601 -#define CFG_CS2U_VAL 0x0 -#define CFG_CS2L_VAL 0x0 - -#define CFG_CS3U_VAL 0x000FFFFF -#define CFG_CS3L_VAL 0x00000303 - -#define CFG_CS4U_VAL 0x000F0a00 -#define CFG_CS4L_VAL 0x11110301 - -/* CNC == 3 too long - #define CFG_CS5U_VAL 0x0000C210 */ - -/* #define CFG_CS5U_VAL 0x00008400 - mal laenger mahcen, ob der bei 150MHz laenger haelt dann und - kaum langsamer ist */ -/* #define CFG_CS5U_VAL 0x00009400 - #define CFG_CS5L_VAL 0x11010D03 */ - -#define CFG_CS5U_VAL 0x00008400 -#define CFG_CS5L_VAL 0x00000D03 - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x16000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE+4) -/* #define CONFIG_DM9000_USE_8BIT */ -#define CONFIG_DM9000_USE_16BIT -/* #define CONFIG_DM9000_USE_32BIT */ - -/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) - f_ref=16,777MHz - - 0x002a141f: 191,9944MHz - 0x040b2007: 144MHz - 0x042a141f: 96MHz - 0x0811140d: 64MHz - 0x040e200e: 150MHz - 0x00321431: 200MHz - - 0x08001800: 64MHz mit 16er Quarz - 0x04001800: 96MHz mit 16er Quarz - 0x04002400: 144MHz mit 16er Quarz - - 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 - |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ - -#define CPU200 - -#ifdef CPU200 -#define CFG_MPCTL0_VAL 0x00321431 -#else -#define CFG_MPCTL0_VAL 0x040e200e -#endif - -/* #define BUS64 */ -#define BUS72 - -#ifdef BUS72 -#define CFG_SPCTL0_VAL 0x04002400 -#endif - -#ifdef BUS96 -#define CFG_SPCTL0_VAL 0x04001800 -#endif - -#ifdef BUS64 -#define CFG_SPCTL0_VAL 0x08001800 -#endif - -/* Das ist der BCLK Divider, der aus der System PLL - BCLK und HCLK erzeugt: - 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 - 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 - 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 - 0x2f001003 : 192MHz/5=38,4MHz - 0x2f000003 : 64MHz/1 - Bit 22: SPLL Restart - Bit 21: MPLL Restart */ - -#ifdef BUS64 -#define CFG_CSCR_VAL 0x2f030003 -#endif - -#ifdef BUS72 -#define CFG_CSCR_VAL 0x2f030403 -#endif - -/* - * Well this has to be defined, but on the other hand it is used differently - * one may expect. For instance loadb command do not cares :-) - * So advice is - do not relay on this... - */ -#define CFG_LOAD_ADDR 0x08400000 - -#define MHZ16QUARZINUSE - -#ifdef MHZ16QUARZINUSE -#define CONFIG_SYSPLL_CLK_FREQ 16000000 -#else -#define CONFIG_SYSPLL_CLK_FREQ 16780000 -#endif - -#define CONFIG_SYS_CLK_FREQ 16780000 - -/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ -#define CFG_FMCR_VAL 0x00000001 - -/* Bit[0:3] contain PERCLK1DIV for UART 1 - 0x000b00b ->b<- -> 192MHz/12=16MHz - 0x000b00b ->8<- -> 144MHz/09=16MHz - 0x000b00b ->3<- -> 64MHz/4=16MHz */ - -#ifdef BUS96 -#define CFG_PCDR_VAL 0x000b00b5 -#endif - -#ifdef BUS64 -#define CFG_PCDR_VAL 0x000b00b3 -#endif - -#ifdef BUS72 -#define CFG_PCDR_VAL 0x000b00b8 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/shannon.h b/include/configs/shannon.h deleted file mode 100644 index 572985b..0000000 --- a/include/configs/shannon.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Configuation settings for the Shannon/TuxScreen/IS2630 WebPhone Board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Since we use the Inferno-Loader to bring us to live, - * we skip the lowlevel init stuff. - * But U-Boot still relocates itself into RAM - */ -#define CONFIG_INFERNO /* we are using the inferno bootldr */ -#define CONFIG_SKIP_LOWLEVEL_INIT 1 -#undef CONFIG_SKIP_RELOCATE_UBOOT - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SA1100 1 /* This is an SA1100 CPU */ -#define CONFIG_SHANNON 1 /* on an SHANNON/TuxScreen Board */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_3C589 1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL3 1 /* we use SERIAL 3 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#if 0 /* XXX - cannot test IDE anyway, so disabled for now - wd */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_IDE) -#endif /* 0 */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_BOOTCOMMAND "help" - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "TuxScreen # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xd0000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x09 /* 190 MHz for Shannon */ - - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_DOS_PARTITION 1 /* DOS partitiion support */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -/* BE CAREFUL */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of EDORAM */ -#define PHYS_SDRAM_1 0xc0000000 /* RAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x00400000 /* 4 MB */ -#define PHYS_SDRAM_2 0xc8000000 /* RAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00400000 /* 4 MB */ -#define PHYS_SDRAM_3 0xd0000000 /* RAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00400000 /* 4 MB */ -#define PHYS_SDRAM_4 0xd8000000 /* RAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00400000 /* 4 MB */ - - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (31+4) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_INFERNO -/* we take the last sector, 128 KB in size, but we only use 4 KB of it for stack reasons */ -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x003E0000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#else -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ - -/* we pick the upper one */ - -#define CONFIG_PCMCIA_SLOT_A - -#define CFG_PCMCIA_IO_ADDR (0x20000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0x24000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0x2C000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_MEM_ADDR (0x28000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) - -/* in fact, MEM and ATTRB are swapped - has to be corrected soon in cmd_pcmcia or so */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -/* it's simple, all regs are in I/O space */ -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_ATTRB_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET 0 - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET 0 - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0 - -/*----------------------------------------------------------------------- - */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h deleted file mode 100644 index a137f9d..0000000 --- a/include/configs/smdk2400.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Gary Jennejohn - * - * Configuation settings for the SAMSUNG board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM920T 1 /* This is an ARM920T core */ -#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ -#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */ -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SAMSUNG */ - -#undef CONFIG_HWFLOW /* include RTS/CTS flow control support */ - -#undef CONFIG_MODEM_SUPPORT /* enable modem initialization stuff */ - -/* - * The following enables modem debugging stuff. The dbg() and - * 'char screen[1024]' are used for debug printfs. Unfortunately, - * it is usable only from BDI - */ -#undef CONFIG_MODEM_SUPPORT_DEBUG - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - -/* Use s3c2400's RTC */ -#define CONFIG_RTC_S3C24X0 1 - -#ifndef USE_920T_MMU -#define CONFIG_COMMANDS_tmp ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \ - CFG_CMD_DATE | \ - CFG_CMD_SNTP ) -#else -#define CONFIG_COMMANDS_tmp (CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_SNTP ) -#endif - -#ifdef CONFIG_HWFLOW -#define CONFIG_COMMANDS (CONFIG_COMMANDS_tmp | CFG_CMD_HWFLOW) -#else -#define CONFIG_COMMANDS CONFIG_COMMANDS_tmp -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#if 0 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#endif -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 134.98.93.36 -#define CONFIG_SERVERIP 134.98.93.22 -#if 0 -#define CONFIG_BOOTFILE "elinos-lart" -#define CONFIG_BOOTCOMMAND "tftp; bootm" -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SMDK2400 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0c000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0e000000 /* 32 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x0cf00000 /* default load address */ - -/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ -/* it to wrap 100 times (total 1562500) to get 1 sec. */ -#define CFG_HZ 1562500 - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) -#define CFG_ENV_SIZE 0x40000 - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h deleted file mode 100644 index 7edec0d..0000000 --- a/include/configs/smdk2410.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Gary Jennejohn - * David Mueller - * - * Configuation settings for the SAMSUNG SMDK2410 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ -#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */ - - -#define USE_920T_MMU 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x19000300 -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */ - -/************************************************************ - * RTC - ************************************************************/ -#define CONFIG_RTC_S3C24X0 1 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - /*CFG_CMD_NAND |*/ \ - /*CFG_CMD_EEPROM |*/ \ - /*CFG_CMD_I2C |*/ \ - /*CFG_CMD_USB |*/ \ - CFG_CMD_REGINFO | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ -/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.0.110 -#define CONFIG_SERVERIP 10.0.0.1 -/*#define CONFIG_BOOTFILE "elinos-lart" */ -/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SMDK2410 # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x33000000 /* default load address */ - -/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ -/* it to wrap 100 times (total 1562500) to get 1 sec. */ -#define CFG_HZ 1562500 - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ -#endif - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h deleted file mode 100644 index 3d907f8..0000000 --- a/include/configs/sorcery.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * (C) Copyright 2004 - * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC8220 1 -#define CONFIG_SORCERY 1 /* Sorcery board */ - -/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to - determine the CPU speed. */ -#define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */ -#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC */ - -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* PCI */ -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 - -#define CONFIG_PCI_MEM_BUS 0x80000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x71000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_PCI_CFG_BUS 0x70000000 -#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS -#define CONFIG_PCI_CFG_SIZE 0x01000000 - -/* - * Supported commands - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CACHE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP | \ - 0) - -/* CFG_CMD_MII | \ */ -/* CFG_CMD_USB | \ */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Default Environment - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_HOSTNAME sorcery - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm $kernel_addr\0" \ - "flash_self=run ramargs addip;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/sorcery/uImage\0" \ - "kernel_addr=FFE00000\0" \ - "ramdisk_addr=FFB00000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_NET_MULTI -#define CONFIG_EEPRO100 - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_MODULE 1 -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* - * Flexbus Chipselect configuration - * Beware: Some CS# seem to be mandatory (if these CS# are not set, - * board can hang-up in unpredictable place). - * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS# - */ - -/* Flash */ -#define CFG_CS0_BASE 0xf800 -#define CFG_CS0_MASK 0x08000000 /* 128 MB (two chips) */ -#define CFG_CS0_CTRL 0x001019c0 - -/* NVM */ -#define CFG_CS1_BASE 0xf7e8 -#define CFG_CS1_MASK 0x00040000 /* 256K */ -#define CFG_CS1_CTRL 0x00101940 /* 8bit port size */ - -/* Atlas2 + Gemini */ -#define CFG_CS2_BASE 0xf7e7 -#define CFG_CS2_MASK 0x00010000 /* 64K*/ -#define CFG_CS2_CTRL 0x001011c0 /* 16bit port size */ - -/* CAN Controller */ -#define CFG_CS3_BASE 0xf7e6 -#define CFG_CS3_MASK 0x00010000 /* 64K */ -#define CFG_CS3_CTRL 0x00102140 /* 8Bit port size */ - -/* Foreign interface */ -#define CFG_CS4_BASE 0xf7e5 -#define CFG_CS4_MASK 0x00010000 /* 64K */ -#define CFG_CS4_CTRL 0x00101dc0 /* 16bit port size */ - -/* CPLD */ -#define CFG_CS5_BASE 0xf7e4 -#define CFG_CS5_MASK 0x00010000 /* 64K */ -#define CFG_CS5_CTRL 0x001000c0 /* 16bit port size */ - -#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) -#define CFG_FLASH_BASE (CFG_FLASH0_BASE) - -#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ - CFG_FLASH_BASE+0x04000000 } /* two banks */ - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000000 - 0x40000) -#define CFG_ENV_SIZE 0x4000 /* 16K */ -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + 0x20000) -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE - -#define CONFIG_ENV_OVERWRITE 1 - -#if defined CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_EEPROM -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#endif - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 -#define CFG_SRAM_BASE (CFG_MBAR + 0x20000) -#define CFG_SRAM_SIZE 0x8000 - -/* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) -#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* SDRAM configuration (for SPD) */ -#define CFG_SDRAM_TOTAL_BANKS 1 -#define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */ -#define CFG_SDRAM_SPD_SIZE 0x100 -#define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */ - -/* SDRAM drive strength register (for SSTL_2 class II)*/ -#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \ - (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ - (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \ - (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \ - (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT)) - -/* - * Ethernet configuration - */ -#define CONFIG_MPC8220_FEC 1 -#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ -#define CONFIG_PHY_ADDR 0x1F - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 - -/* -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h deleted file mode 100644 index 96cb6e4..0000000 --- a/include/configs/spieval.h +++ /dev/null @@ -1,548 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ -#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ - -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_STK52XX -#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ -#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ -#define CONFIG_BOARD_EARLY_INIT_R -#endif /* CONFIG_STK52XX */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#ifdef CONFIG_STK52XX -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_NET_MULTI 1 -#define CONFIG_EEPRO100 1 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif /* CONFIG_STK52XX */ - -#ifdef CONFIG_PCI -#define ADD_PCI_CMD CFG_CMD_PCI -#else -#define ADD_PCI_CMD 0 -#endif - -/* - * Video console - */ -#if 1 -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CFG_CONSOLE_IS_IN_ENV -#endif - -#ifdef CONFIG_VIDEO -#define ADD_BMP_CMD CFG_CMD_BMP -#else -#define ADD_BMP_CMD 0 -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* USB */ -#ifdef CONFIG_STK52XX -#define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT -#define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 -#endif - -/* POST support */ -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -/* IDE */ -#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) -#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) -#else -#define ADD_IDE_CMD 0 -#endif - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - ADD_IDE_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#if defined (CONFIG_TQM5200_AA) -# define CONFIG_U_BOOT_SUFFIX "-AA\0" -#elif defined (CONFIG_TQM5200_AB) -# define CONFIG_U_BOOT_SUFFIX "-AB\0" -#elif defined (CONFIG_TQM5200_AC) -# define CONFIG_U_BOOT_SUFFIX "-AC\0" -#else -# define CONFIG_U_BOOT_SUFFIX "\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ - -#if defined(CFG_IPBSPEED_133) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. - */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CFG_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * HW-Monitor configuration on Mini-FAP - */ -#if defined (CONFIG_MINIFAP) -#define CFG_I2C_HWMON_ADDR 0x2C -#endif - -/* List of I2C addresses to be verified by POST */ -#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB) -#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ - CFG_I2C_SLAVE } -#elif defined (CONFIG_TQM5200_AC) -#define I2C_ADDR_LIST { CFG_I2C_SLAVE } -#endif - -#if defined (CONFIG_MINIFAP) -#undef I2C_ADDR_LIST -#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \ - CFG_I2C_HWMON_ADDR, \ - CFG_I2C_SLAVE } -#endif - -/* - * Flash configuration - */ -#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CFG_LOWBOOT) -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CFG_LOWBOOT */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) -#endif /* CFG_LOWBOOT */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#if defined (CONFIG_MINIFAP) -# define CFG_GPS_PORT_CONFIG 0x91000004 -#elif defined (CONFIG_STK52XX) -# if defined (CONFIG_STK52XX_REV100) -# define CFG_GPS_PORT_CONFIG 0x81500014 -# else /* STK52xx REV200 and above */ -# if defined (CONFIG_TQM5200_REV100) -# error TQM5200 REV100 not supported on STK52XX REV200 or above -# else/* TQM5200 REV200 and above */ -# define CFG_GPS_PORT_CONFIG 0x91500004 -# endif -# endif -#else /* TMQ5200 Inbetriebnahme-Board */ -# define CFG_GPS_PORT_CONFIG 0x81000004 -#endif - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CFG_ALT_MEMTEST - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif - -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 -#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -/* automatic configuration of chip selects */ -#ifdef CONFIG_CS_AUTOCONF -#define CONFIG_LAST_STAGE_INIT -#endif - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF) -#define CFG_CS2_START 0xE5000000 -#ifdef CONFIG_TQM5200_AB -#define CFG_CS2_SIZE 0x80000 /* 512 kByte */ -#else /* CONFIG_CS_AUTOCONF */ -#define CFG_CS2_SIZE 0x100000 /* 1 MByte */ -#endif -#define CFG_CS2_CFG 0x0004D930 -#endif - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \ - defined (CONFIG_CS_AUTOCONF) -#define SM501_FB_BASE 0xE0000000 -#define CFG_CS1_START (SM501_FB_BASE) -#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CFG_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 -#endif - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CFG_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h deleted file mode 100644 index e218597..0000000 --- a/include/configs/stxgp3.h +++ /dev/null @@ -1,389 +0,0 @@ -/* - * (C) Copyright 2003 Embedded Edge, LLC - * Dan Malek - * Copied from ADS85xx. - * Updates for Silicon Tx GP3 8560 board. - * - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ - -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support*/ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - - -/* sysclk for MPC85xx - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */ - -/* Blinkin' LEDs for Robert :-) -*/ -#define CONFIG_SHOW_ACTIVITY 1 - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 - - -/* Localbus SDRAM is an option, not all boards have it. - * This address, however, is used to configure a 256M local bus - * window that includes the Config latch below. - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ - -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ - -#define CFG_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 136 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* The configuration latch is Chip Select 1. - * It's an 8-bit latch in the lower 8 bits of the word. - */ -#define CFG_BR1_PRELIM 0xfc001801 /* 32-bit port */ -#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ -#define CFG_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ - -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -#ifdef CFG_RAMBOOT -#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#else -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#endif -#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ - - -/* - * DDR Setup - */ - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE - -#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */ - -#undef CONFIG_CLOCKS_IN_MHZ - -/* local bus definitions */ -#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ -#define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* local bus freq */ -#define CFG_LBC_LBCR 0x00000000 -#define CFG_LBC_LSRT 0x20000000 -#define CFG_LBC_MRTPR 0x20000000 -#define CFG_LBC_LSDMR_1 0x2861b723 -#define CFG_LBC_LSDMR_2 0x0861b723 -#define CFG_LBC_LSDMR_3 0x0861b723 -#define CFG_LBC_LSDMR_4 0x1861b723 -#define CFG_LBC_LSDMR_5 0x4061b723 - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ - -#define CONFIG_BAUDRATE 38400 - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#if 0 -#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */ -#else -/* I did the 'if 0' so we could keep the syntax above if ever needed. */ -#undef CFG_I2C_NOPROBES -#endif - -/* RapdIO Map configuration, mapped 1:1. -*/ -#define CFG_RIO_MEM_BASE 0xc0000000 -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x200000000 /* 512 M */ - -/* Standard 8560 PCI addressing, mapped 1:1. -*/ -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x01000000 /* 16 M */ - -#if defined(CONFIG_PCI) /* PCI Ethernet card */ - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ - -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" -#undef CONFIG_MPS85XX_FEC - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 4 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define CONFIG_ETHPRIME "TSEC0" - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - -#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 -#if 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) -#else - #define CFG_FCC_PSMR 0 -#endif - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -/* MDIO is done through the TSEC0 control. -*/ -#define CONFIG_MII /* MII PHY management */ -#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -#endif - -/* Environment */ -/* We use the top boot sector flash, so we have some 16K sectors for env - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000) - #define CFG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" -#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000" -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \ - CFG_CMD_MII | CFG_CMD_I2C ) & \ - ~(CFG_CMD_ENV)) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \ - CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) - #endif -#endif -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "GPPP=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x1000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*Note: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c -#endif - -#define CONFIG_SERVERIP 192.168.85.1 -#define CONFIG_IPADDR 192.168.85.60 -#define CONFIG_GATEWAYIP 192.168.85.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME STX_GP3 -#define CONFIG_ROOTPATH /gppproot -#define CONFIG_BOOTFILE uImage -#define CONFIG_LOADADDR 0x1000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h deleted file mode 100644 index 3ffe6b2..0000000 --- a/include/configs/stxxtc.h +++ /dev/null @@ -1,588 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com - * U-Boot port on STx XTc 8xx board - * Mostly copied from Panto's NETTA2 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC875 1 /* This is a MPC875 CPU */ -#define CONFIG_STXXTC 1 /* ...on a STx XTc board */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */ - -#define CONFIG_XIN 10000000 /* 10 MHz input xtal */ - -/* Select one of few clock rates defined later in this file. -*/ -/* #define MPC8XX_HZ 50000000 */ -#define MPC8XX_HZ 66666666 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_AUTOSCRIPT -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) - -#undef CONFIG_MAC_PARTITION -#undef CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ -#define FEC_ENET 1 /* eth.c needs it that way... */ -#undef CFG_DISCOVER_PHY -#define CONFIG_MII 1 -#undef CONFIG_RMII - -#define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 1 /* phy address of FEC */ -#undef CONFIG_FEC1_PHY_NORXERR - -#define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 3 -#undef CONFIG_FEC2_PHY_NORXERR - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_NAND | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_MII | \ - CFG_CMD_NFS) - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "xtc> " /* Monitor Command Prompt */ - -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0300000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif - -/* yes this is weird, I know :) */ -#define CFG_MONITOR_BASE (CFG_FLASH_BASE | 0x00F00000) -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CFG_RESET_ADDRESS 0x80000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x10000 - -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 0x4000 - -#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x00010000) -#define CFG_ENV_OFFSET_REDUND 0 -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE - -#define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 -#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ - -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 } - -#define CFG_FLASH_PROTECTION - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - */ - -#if CONFIG_XIN == 10000000 - -#if MPC8XX_HZ == 50000000 -#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#elif MPC8XX_HZ == 66666666 -#define CFG_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \ - (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) -#else -#error unsupported CPU freq for XIN = 10MHz -#endif -#else -#error unsupported freq for XIN (must be 10MHz) -#endif - - -/* - *----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: When TBS == 0 the timebase is independent of current cpu clock. - */ - -#define SCCR_MASK SCCR_EBDF11 -#if MPC8XX_HZ > 66666666 -#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00 | SCCR_EBDF01) -#else -#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ - -#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */ - -#define CFG_REMAP_OR_AM 0x80000000 -#define CFG_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -#define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH) -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -/* - * BR4 and OR4 (SDRAM) - * - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) - -#define CFG_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) -#define CFG_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CFG_MAMR_PTA 234 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ - -/****************************************************************/ - -#define NAND_SIZE 0x00010000 /* 64K */ -#define NAND_BASE 0xF1000000 - -/****************************************************************/ - -/* NAND */ -#define CFG_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_ECC_JFFS2 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_MTD_NAND_UNSAFE - -#define CFG_MAX_NAND_DEVICE 1 -#undef NAND_NO_RB - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */ -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \ - } while(0) - -#ifndef NAND_NO_RB -#define NAND_WAIT_READY(nand) \ - do { \ - int _tries = 0; \ - while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \ - if (++_tries > 100000) \ - break; \ - } while (0) -#else -#define NAND_WAIT_READY(nand) udelay(12) -#endif - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - -/*****************************************************************************/ - -#define CFG_DIRECT_FLASH_TFTP -#define CFG_DIRECT_NAND_TFTP - -/*****************************************************************************/ - -/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB, - * CxOE and CxRESET. We use the CxOE. - */ -#define STATUS_LED_BIT 0x00000080 /* bit 24 */ - -#define STATUS_LED_PERIOD (CFG_HZ / 2) -#define STATUS_LED_STATE STATUS_LED_BLINKING - -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - -#ifndef __ASSEMBLY__ - -/* LEDs */ - -/* led_id_t is unsigned int mask */ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \ - else \ - ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \ - } while(0) - -#define __led_init(msk, st) __led_set(msk, st) - -#endif - -/******************************************************************************/ - -#define CFG_CONSOLE_IS_IN_ENV 1 -#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 -#define CFG_CONSOLE_ENV_OVERWRITE 1 - -/******************************************************************************/ - -/* use board specific hardware */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_SHOW_ACTIVITY - -/*****************************************************************************/ - -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_CRC32_VERIFY 1 -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 - -/*****************************************************************************/ - -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,MPC870@0" -#define OF_TBCLK (MPC8XX_HZ / 16) - -#endif /* __CONFIG_H */ diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h deleted file mode 100644 index 1ee6be1..0000000 --- a/include/configs/suzaku.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MICROBLAZE 1 /* This is an MicroBlaze CPU */ -#define CONFIG_SUZAKU 1 /* on an SUZAKU Board */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x80000000 -#define CFG_SDRAM_SIZE 0x01000000 -#define CFG_FLASH_BASE 0xfff00000 -#define CFG_FLASH_SIZE 0x00400000 -#define CFG_RESET_ADDRESS 0xfff00100 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024)) -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 115200 } - -#define CONFIG_COMMANDS (CONFIG__CMD_DFL) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CFG_UART1_BASE (0xFFFF2000) -#define CONFIG_SERIAL_BASE CFG_UART1_BASE - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "SUZAKU> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ - -#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* default load address */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 1 /* max number of sectors on one chip */ - -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_ENV_IS_NOWHERE 1 -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -#define CFG_INIT_RAM_ADDR 0x80000000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h deleted file mode 100644 index 7118f3f..0000000 --- a/include/configs/svm_sc8xx.h +++ /dev/null @@ -1,470 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific, - * for SinoVee Microsystems SC8xx series SBC - * http://www.fel.com.cn (Chinese) - * http://www.sinovee.com (English) - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Custom configuration */ -/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */ -/* SC85T,SC860T, FEL8xx-AT(855T/860T) */ -/*#define CONFIG_FEL8xx_AT */ -/*#define CONFIG_LCD */ -/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */ -/* #define CONFIG_50MHz */ -/* #define CONFIG_66MHz */ -/* #define CONFIG_75MHz */ -#define CONFIG_80MHz -/*#define CONFIG_100MHz */ -/* #define CONFIG_BUS_DIV2 1 */ -/* for BOOT device port size */ -/* #define CONFIG_BOOT_8B */ -#define CONFIG_BOOT_16B -/* #define CONFIG_BOOT_32B */ -/* #define CONFIG_CAN_DRIVER */ -/* #define DEBUG */ -#define CONFIG_FEC_ENET - -/* #define CONFIG_SDRAM_16M */ -#define CONFIG_SDRAM_32M -/* #define CONFIG_SDRAM_64M */ -#define CFG_RESET_ADDRESS 0xffffffff -/* - * High Level Configuration Options - * (easy to change) - */ - -/* #define CONFIG_MPC823 1 */ -/* #define CONFIG_MPC850 1 */ -#define CONFIG_MPC855 1 -/* #define CONFIG_MPC860 1 */ -/* #define CONFIG_MPC860T 1 */ - -#undef CONFIG_WATCHDOG /* watchdog */ - -#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \ - "bootfile=pImage-sc855t\0" \ - "kernel_addr=48000000\0" \ - "ramdisk_addr=48100000\0" \ - "" -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "tftpboot 0x210000 pImage-sc855t;bootm 0x210000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - - -#ifdef CONFIG_LCD -# undef CONFIG_STATUS_LED /* disturbs display */ -#else -# define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#endif /* CONFIG_LCD */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ -/* CFG_CMD_IDE |*/ \ - CFG_CMD_DATE ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_FLASH 1 - -#ifdef CONFIG_BOOT_8B -#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#elif defined (CONFIG_BOOT_16B) -#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#elif defined (CONFIG_BOOT_32B) -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CFG_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -/*#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -*/ -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR 0xffffff88 -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -/*#define CFG_SIUMCR 0x00610c00 */ -#define CFG_SIUMCR 0x00000000 -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR 0x0001 - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC 0x00c3 - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR 0x0000 - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#if defined (CONFIG_100MHz) -#define CFG_PLPRCR 0x06301000 -#define CONFIG_8xx_GCLK_FREQ 100000000 -#elif defined (CONFIG_80MHz) -#define CFG_PLPRCR 0x04f01000 -#define CONFIG_8xx_GCLK_FREQ 80000000 -#elif defined(CONFIG_75MHz) -#define CFG_PLPRCR 0x04a00100 -#define CONFIG_8xx_GCLK_FREQ 75000000 -#elif defined(CONFIG_66MHz) -#define CFG_PLPRCR 0x04101000 -#define CONFIG_8xx_GCLK_FREQ 66000000 -#elif defined(CONFIG_50MHz) -#define CFG_PLPRCR 0x03101000 -#define CONFIG_8xx_GCLK_FREQ 50000000 -#endif - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_BUS_DIV2 -#define CFG_SCCR 0x02020000 | SCCR_RTSEL -#else /* up to 50 MHz we use a 1:1 clock */ -#define CFG_SCCR 0x02000000 | SCCR_RTSEL -#endif - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0xFE100010 -#define CFG_ATA_IDE0_OFFSET 0x0000 -/*#define CFG_ATA_IDE1_OFFSET 0x0C00 */ -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O - */ -#define CFG_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses - */ -#define CFG_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers - */ -#define CONFIG_ATAPI -#define CFG_PIO_MODE 0 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -/*#define CFG_DER 0x2002000F*/ -#define CFG_DER 0x0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#if defined(CONFIG_100MHz) -#define CFG_OR_TIMING_FLASH 0x000002f4 -#define CFG_OR_TIMING_DOC 0x000002f4 -#define CFG_MxMR_PTx 0x61000000 -#define CFG_MPTPR 0x400 - -#elif defined(CONFIG_80MHz) -#define CFG_OR_TIMING_FLASH 0x00000ff4 -#define CFG_OR_TIMING_DOC 0x000001f4 -#define CFG_MxMR_PTx 0x4e000000 -#define CFG_MPTPR 0x400 - -#elif defined(CONFIG_75MHz) -#define CFG_OR_TIMING_FLASH 0x000008f4 -#define CFG_OR_TIMING_DOC 0x000002f4 -#define CFG_MxMR_PTx 0x49000000 -#define CFG_MPTPR 0x400 - -#elif defined(CONFIG_66MHz) -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) -/*#define CFG_OR_TIMING_FLASH 0x000001f4 */ -#define CFG_OR_TIMING_DOC 0x000003f4 -#define CFG_MxMR_PTx 0x40000000 -#define CFG_MPTPR 0x400 - -#else /* 50 MHz */ -#define CFG_OR_TIMING_FLASH 0x00000ff4 -#define CFG_OR_TIMING_DOC 0x000001f4 -#define CFG_MxMR_PTx 0x30000000 -#define CFG_MPTPR 0x400 -#endif /*CONFIG_??MHz */ - - -#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */ -#define CFG_OR0_PRELIM (0xffe00000 | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) -#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */ -#define CFG_OR0_PRELIM (0xffc00000 | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) -#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */ -#define CFG_OR0_PRELIM (0xfc000000 | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) -#else -#error Boot device port size missing. -#endif - -/* - * Disk-On-Chip configuration - */ - -#define CFG_DOC_SHORT_TIMEOUT -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM -#define CFG_DOC_BASE 0x80000000 - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h deleted file mode 100644 index dac1eb7..0000000 --- a/include/configs/tb0229.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * (C) Copyright 2003 - * Masami Komiya - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Config header file for TANBAC TB0229 board using an VR4131 CPU module - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ -#define CONFIG_TB0229 1 /* on a TB0229 Board */ - -#ifndef CPU_CLOCK_RATE -#define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */ -#endif -#define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"boot\" for the network boot using DHCP, TFTP and NFS;" \ - "echo Type \"run netboot_initrd\" for the network boot with initrd;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo Type \"run flash_local\" to mount local root filesystem;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netboot=dhcp;tftp;run netargs; bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \ - "localargs=setenv bootargs root=1F02 ip=dhcp\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "read-only=readonly\0" \ - "netargs=run nfsargs addmisc\0" \ - "flash_nfs=run nfsargs addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_local=run localargs addmisc;" \ - "bootm ${kernel_addr}\0" \ - "netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \ - "setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\ - "run addmisc;" \ - "bootm 80400000 80600000\0" \ - "rootpath=/export/miniroot-mipsel\0" \ - "autoload=no\0" \ - "kernel_addr=BFC60000\0" \ - "ramdisk_addr=B0100000\0" \ - "u-boot=u-boot.bin\0" \ - "bootfile=uImage\0" \ - "load=dhcp;tftp 80400000 ${u-boot}\0" \ - "load_kernel=dhcp;tftp 80400000 ${bootfile}\0" \ - "update_uboot=run load;" \ - "protect off BFC00000 BFC3FFFF;" \ - "erase BFC00000 BFC3FFFF;" \ - "cp.b 80400000 BFC00000 ${filesize}\0" \ - "update_kernel=run load_kernel;" \ - "erase BFC60000 BFD5FFFF;" \ - "cp.b 80400000 BFC60000 ${filesize}\0" \ - "initenv=erase bfc40000 bfc5ffff\0" \ - "" -/*#define CONFIG_BOOTCOMMAND "run flash_local" */ -#define CONFIG_BOOTCOMMAND "run netboot" - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_PCI | \ - CFG_CMD_ELF ) -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "# " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args*/ - -#define CFG_MALLOC_LEN 128*1024 - -#define CFG_BOOTPARAMS_LEN 128*1024 - -#define CFG_HZ (CPU_TCLOCK_RATE/4) - -#define CFG_SDRAM_BASE 0x80000000 - -#define CFG_LOAD_ADDR 0x80400000 /* default load address */ - -#define CFG_MEMTEST_START 0x80000000 -#define CFG_MEMTEST_END 0x80800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */ - -/* The following #defines are needed to get flash environment right */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) - -#define CFG_INIT_SP_OFFSET 0x400000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20 * CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR 0xBFC40000 -#define CFG_ENV_SIZE 0x20000 - -#define CFG_DIRECT_FLASH_TFTP - -#define CONFIG_NR_DRAM_BANKS 1 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_ICACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 16 - -/*----------------------------------------------------------------------- - * Serial Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 18432000 -#define CFG_NS16550_COM1 0xaf000800 - -/*----------------------------------------------------------------------- - * PCI stuff - */ -#define CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_NET_MULTI -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -#define CONFIG_RTL8139 - -#endif /* __CONFIG_H */ diff --git a/include/configs/trab.h b/include/configs/trab.h deleted file mode 100644 index 85ee756..0000000 --- a/include/configs/trab.h +++ /dev/null @@ -1,430 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Gary Jennejohn - * - * Configuation settings for the TRAB board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Default configuration is with 8 MB Flash, 32 MB RAM - */ -#if (!defined(CONFIG_FLASH_8MB)) && (!defined(CONFIG_FLASH_16MB)) -# define CONFIG_FLASH_8MB /* 8 MB Flash */ -#endif -#if (!defined(CONFIG_RAM_16MB)) && (!defined(CONFIG_RAM_32MB)) -# define CONFIG_RAM_32MB /* 32 MB SDRAM */ -#endif - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM920T 1 /* This is an arm920t CPU */ -#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ -#define CONFIG_TRAB 1 /* on a TRAB Board */ -#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */ -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ - -/* automatic software updates (see board/trab/auto_update.c) */ -#define CONFIG_AUTO_UPDATE 1 - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000 /* TRAB has 12 MHz input clock */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CFG_DEVICE_NULLDEV 1 /* enble null device */ -#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*********************************************************** - * I2C stuff: - * the TRAB is equipped with an ATMEL 24C04 EEPROM at - * address 0x54 with 8bit addressing - ***********************************************************/ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ - -#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM address */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* 1 address byte */ - -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 bytes page write mode on 24C04 */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* USB stuff */ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 - -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ -#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */ -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ - -#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ - -#define CONFIG_VFD 1 /* VFD linear frame buffer driver */ -#define VFD_TEST_LOGO 1 /* output a test logo to the VFDs */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on TRAB */ - -#define CONFIG_HWFLOW /* include RTS/CTS flow control support */ - -#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */ - -#define CONFIG_MODEM_KEY_MAGIC "23" /* hold down these keys to enable modem */ - -/* - * The following enables modem debugging stuff. The dbg() and - * 'char screen[1024]' are used for debug printfs. Unfortunately, - * it is usable only from BDI - */ -#undef CONFIG_MODEM_SUPPORT_DEBUG - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - -/* Use s3c2400's RTC */ -#define CONFIG_RTC_S3C24X0 1 - -#ifdef CONFIG_HWFLOW -#define CONFIG_COMMANDS_ADD_HWFLOW CFG_CMD_HWFLOW -#else -#define CONFIG_COMMANDS_ADD_HWFLOW 0 -#endif - -#ifdef CONFIG_VFD -#define CONFIG_COMMANDS_ADD_VFD CFG_CMD_VFD -#else -#define CONFIG_COMMANDS_ADD_VFD 0 -#endif - -#ifdef CONFIG_DRIVER_S3C24X0_I2C -#define CONFIG_COMMANDS_ADD_EEPROM CFG_CMD_EEPROM -#define CONFIG_COMMANDS_I2C CFG_CMD_I2C -#else -#define CONFIG_COMMANDS_ADD_EEPROM 0 -#define CONFIG_COMMANDS_I2C 0 -#endif - -#ifndef USE_920T_MMU -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \ - CONFIG_COMMANDS_ADD_HWFLOW | \ - CONFIG_COMMANDS_ADD_VFD | \ - CONFIG_COMMANDS_ADD_EEPROM | \ - CONFIG_COMMANDS_I2C | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - CFG_CMD_USB ) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CONFIG_COMMANDS_ADD_HWFLOW | \ - CONFIG_COMMANDS_ADD_VFD | \ - CONFIG_COMMANDS_ADD_EEPROM | \ - CONFIG_COMMANDS_I2C | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - CFG_CMD_USB ) -#endif - -/* moved up */ -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ -#define CONFIG_PREBOOT "echo;echo *** booting ***;echo" -#define CONFIG_BOOTARGS "console=ttyS0" -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_IPADDR 192.168.3.68 -#define CONFIG_HOSTNAME trab -#define CONFIG_SERVERIP 192.168.3.1 -#define CONFIG_BOOTCOMMAND "burn_in" - -#ifndef CONFIG_FLASH_8MB /* current config: 16 MB flash */ -#ifdef CFG_HUSH_PARSER -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfs_args=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "rootpath=/opt/eldk/arm_920TDI\0" \ - "ram_args=setenv bootargs root=/dev/ram rw\0" \ - "add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ - "add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \ - "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ - "load=tftp C100000 ${u-boot}\0" \ - "update=protect off 0 5FFFF;era 0 5FFFF;" \ - "cp.b C100000 0 $filesize\0" \ - "loadfile=/tftpboot/TRAB/uImage\0" \ - "loadaddr=c400000\0" \ - "net_load=tftpboot $loadaddr $loadfile\0" \ - "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ - "kernel_addr=00060000\0" \ - "flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \ - "mdm_init1=ATZ\0" \ - "mdm_init2=ATS0=1\0" \ - "mdm_flow_control=rts/cts\0" -#else /* !CFG_HUSH_PARSER */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfs_args=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "rootpath=/opt/eldk/arm_920TDI\0" \ - "ram_args=setenv bootargs root=/dev/ram rw\0" \ - "add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ - "add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \ - "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ - "load=tftp C100000 ${u-boot}\0" \ - "update=protect off 0 5FFFF;era 0 5FFFF;" \ - "cp.b C100000 0 ${filesize}\0" \ - "loadfile=/tftpboot/TRAB/uImage\0" \ - "loadaddr=c400000\0" \ - "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ - "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ - "kernel_addr=000C0000\0" \ - "flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \ - "mdm_init1=ATZ\0" \ - "mdm_init2=ATS0=1\0" \ - "mdm_flow_control=rts/cts\0" -#endif /* CFG_HUSH_PARSER */ -#else /* CONFIG_FLASH_8MB => 8 MB flash */ -#ifdef CFG_HUSH_PARSER -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfs_args=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "rootpath=/opt/eldk/arm_920TDI\0" \ - "ram_args=setenv bootargs root=/dev/ram rw\0" \ - "add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ - "add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \ - "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ - "load=tftp C100000 ${u-boot}\0" \ - "update=protect off 0 3FFFF;era 0 3FFFF;" \ - "cp.b C100000 0 $filesize;" \ - "setenv filesize;saveenv\0" \ - "loadfile=/tftpboot/TRAB/uImage\0" \ - "loadaddr=C400000\0" \ - "net_load=tftpboot $loadaddr $loadfile\0" \ - "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ - "kernel_addr=000C0000\0" \ - "flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \ - "mdm_init1=ATZ\0" \ - "mdm_init2=ATS0=1\0" \ - "mdm_flow_control=rts/cts\0" -#else /* !CFG_HUSH_PARSER */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "nfs_args=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "rootpath=/opt/eldk/arm_920TDI\0" \ - "ram_args=setenv bootargs root=/dev/ram rw\0" \ - "add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ - "add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \ - "u-boot=/tftpboot/TRAB/u-boot.bin\0" \ - "load=tftp C100000 ${u-boot}\0" \ - "update=protect off 0 3FFFF;era 0 3FFFF;" \ - "cp.b C100000 0 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "loadfile=/tftpboot/TRAB/uImage\0" \ - "loadaddr=C400000\0" \ - "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ - "net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \ - "kernel_addr=000C0000\0" \ - "flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \ - "mdm_init1=ATZ\0" \ - "mdm_init2=ATS0=1\0" \ - "mdm_flow_control=rts/cts\0" -#endif /* CFG_HUSH_PARSER */ -#endif /* CONFIG_FLASH_8MB */ - -#if 1 /* feel free to disable for development */ -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" -#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */ -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "TRAB # " /* Monitor Command Prompt */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0C000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0D000000 /* 16 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0x0CF00000 /* default load address */ - -#ifdef CONFIG_TRAB_50MHZ -/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ -/* it to wrap 100 times (total 1562500) to get 1 sec. */ -/* this should _really_ be calculated !! */ -#define CFG_HZ 1562500 -#else -/* the PWM TImer 4 uses a counter of 10390 for 10 ms, so we need */ -/* it to wrap 100 times (total 1039000) to get 1 sec. */ -/* this should _really_ be calculated !! */ -#define CFG_HZ 1039000 -#endif - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ - -/*----------------------------------------------------------------------- - * burn-in test stuff. - * - * BURN_IN_CYCLE_DELAY defines the seconds to wait between each burn-in cycle - * Because the burn-in test itself causes also an delay of about 4 seconds, - * this time must be subtracted from the desired overall burn-in cycle time. - */ -#define BURN_IN_CYCLE_DELAY 296 /* seconds between burn-in cycles */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x0C000000 /* SDRAM Bank #1 */ -#ifndef CONFIG_RAM_16MB -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#else -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ -#endif - -#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */ - -/* The following #defines are needed to get flash environment right */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (256 << 10) - -/* Dynamic MTD partition support */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=0" - -/* production flash layout */ -#define MTDPARTS_DEFAULT "mtdparts=0:32k(Firmware1)ro," \ - "16k(Env1)," \ - "16k(Env2)," \ - "320k(Firmware2)ro," \ - "896k(Kernel)," \ - "5376k(Root-FS)," \ - "1408k(JFFS2)," \ - "-(VFD)" - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifndef CONFIG_FLASH_8MB -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#else -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -#endif - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 - -/* Address and size of Primary Environment Sector */ -#ifndef CONFIG_FLASH_8MB -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) -#define CFG_ENV_SIZE 0x4000 -#define CFG_ENV_SECT_SIZE 0x20000 -#else -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) -#define CFG_ENV_SIZE 0x4000 -#define CFG_ENV_SECT_SIZE 0x4000 -#endif - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/* Initial value of the on-board touch screen brightness */ -#define CFG_BRIGHTNESS 0x20 - -#endif /* __CONFIG_H */ diff --git a/include/configs/uc100.h b/include/configs/uc100.h deleted file mode 100644 index c4e629a..0000000 --- a/include/configs/uc100.h +++ /dev/null @@ -1,507 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 /* enable 862 since the */ -#define CONFIG_MPC857 1 /* 857 is a variant of the 862 */ - -#define CONFIG_UC100 1 /* ...on a UC100 module */ - -#define MPC8XX_FACT 4 /* Multiply by 4 */ -#define MPC8XX_XIN 25000000 /* 25.0 MHz in */ -#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) - /* define if cant' use get_gclk_freq */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/uc100/uImage\0" \ - "kernel_addr=40000000\0" \ - "ramdisk_addr=40100000\0" \ - "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \ - "update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \ - "cp.b 100000 40700000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* no status-led */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_RTC_MPC8xx -#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -/* - * Power On Self Test support - */ -#define CONFIG_POST ( CFG_POST_CACHE | \ - CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_UART | \ - CFG_POST_SPR ) -#undef CONFIG_POST - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_SNTP ) - -#define CONFIG_NETCONSOLE - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE (CFG_FLASH_BASE+0x00700000) /* resetvec fff00100*/ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*----------------------------------------------------------------------- - * Address accessed to reset the board - must not be mapped/assigned - */ -#define CFG_RESET_ADDRESS 0x90000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN) -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK 0x00000000 -#define CFG_SCCR (SCCR_EBDF11) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (0x00000d24) - -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CFG_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */ -#define CFG_OR1_PRELIM 0xfc000a00 -#define CFG_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */ -#define CFG_OR2_PRELIM 0xfff00d24 -#define CFG_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */ -#define CFG_OR3_PRELIM 0xffff8f44 -#define CFG_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */ -#define CFG_OR4_PRELIM 0xffff0300 -#define CFG_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */ -#define CFG_OR5_PRELIM 0xffff8db0 - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CFG_MAMR_VAL 0x30904114 /* for SDRAM */ -#define CFG_MBMR_VAL 0xff001111 /* for Interbus-MPM */ - -/*----------------------------------------------------------------------- - * I2C stuff - */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CFG_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (24C164) - */ -#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define FEC_ENET -#define CONFIG_MII -#define CFG_DISCOVER_PHY 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h deleted file mode 100644 index d312b65..0000000 --- a/include/configs/utx8245.h +++ /dev/null @@ -1,420 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Gregory E. Allen, gallen@arlut.utexas.edu - * Matthew E. Karger, karger@arlut.utexas.edu - * Applied Research Laboratories, The University of Texas at Austin - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the utx8245 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_UTX8245 1 -#define DEBUG 1 - -#define CONFIG_IDENT_STRING " [UTX5] " - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 57600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_BOOTDELAY 2 -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" -#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */ -#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */ -#define CONFIG_SERVERIP 10.8.17.105 /* Spree */ -#define CFG_TFTP_LOADADDR 10000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr=FFA00000\0" \ - "ramdisk_addr=FF800000\0" \ - "u-boot_startaddr=FFB00000\0" \ - "u-boot_endaddr=FFB2FFFF\0" \ - "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \ -nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \ - "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \ - "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \ - "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \ - "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \ - "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \ -${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \ -${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\ -protect on ${u-boot_startaddr} ${u-boot_endaddr}" - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \ - | CFG_CMD_FLASH | CFG_CMD_MEMORY \ - | CFG_CMD_ENV | CFG_CMD_CONSOLE \ - | CFG_CMD_LOADS | CFG_CMD_LOADB \ - | CFG_CMD_IMI | CFG_CMD_CACHE \ - | CFG_CMD_RUN | CFG_CMD_ECHO \ - | CFG_CMD_REGINFO | CFG_CMD_NET\ - | CFG_CMD_DHCP | CFG_CMD_I2C \ - | CFG_CMD_DATE) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) - -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ - - -/*----------------------------------------------------------------------- - * PCI configuration - *----------------------------------------------------------------------- - */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_NET_MULTI -#define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_EEPRO100_SROM_WRITE - -#define PCI_ENET0_IOADDR 0xF0000000 -#define PCI_ENET0_MEMADDR 0xF0000000 - -#define PCI_FIREWIRE_IOADDR 0xF1000000 -#define PCI_FIREWIRE_MEMADDR 0xF1000000 -/* -#define PCI_ENET0_IOADDR 0xFE000000 -#define PCI_ENET0_MEMADDR 0x80000000 - -#define PCI_FIREWIRE_IOADDR 0x81000000 -#define PCI_FIREWIRE_MEMADDR 0x81000000 -*/ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x10000000 /* 256MB */ -/*#define CFG_VERY_BIG_RAM 1 */ - -/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector - * is actually located at FFF00100. Therefore, U-Boot is - * physically located at 0xFFB0_0000, but is also mirrored at - * 0xFFF0_0000. - */ -#define CFG_RESET_ADDRESS 0xFFF00100 - -#define CFG_EUMB_ADDR 0xFC000000 - -#define CFG_MONITOR_BASE TEXT_BASE - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/*#define CFG_DRAM_TEST 1 */ -#define CFG_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */ -#define CFG_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */ - /* vectors and U-Boot */ - - -/*-------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - *------------------------------------------------------------------*/ -#define CFG_INIT_DATA_SIZE 128 /* Size in bytes reserved for */ - /* initial data */ -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) -#define CFG_GBL_DATA_SIZE 128 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - -/*-------------------------------------------------------------------- - * NS16550 Configuration - *------------------------------------------------------------------*/ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL - -#define CFG_NS16550_REG_SIZE 1 - -#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2) -# define CFG_NS16550_CLK get_bus_freq(0) -#else -# define CFG_NS16550_CLK 33000000 -#endif - -#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) -#define CFG_NS16550_COM3 0xFF000000 -#define CFG_NS16550_COM4 0xFF000008 - -/*-------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - *------------------------------------------------------------------*/ - -#define CONFIG_SYS_CLK_FREQ 33000000 -#define CFG_HZ 1000 - -/*#define CFG_ETH_DEV_FN 0x7800 */ -/*#define CFG_ETH_IOBASE 0x00104000 */ - -/*-------------------------------------------------------------------- - * I2C Configuration - *------------------------------------------------------------------*/ -#if 1 -#define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#endif - -#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */ - /* Philips PCF8563 RTC */ -#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ - -/*-------------------------------------------------------------------- - * Memory Control Configuration Register values - * - see sec. 4.12 of MPC8245 UM - *------------------------------------------------------------------*/ - -/**** MCCR1 ****/ -#define CFG_ROMNAL 0 -#define CFG_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2, - mem_freq = 100MHz */ - -#define CFG_BANK7_ROW 0 /* SDRAM bank 7-0 row address */ -#define CFG_BANK6_ROW 0 /* bit count */ -#define CFG_BANK5_ROW 0 -#define CFG_BANK4_ROW 0 -#define CFG_BANK3_ROW 0 -#define CFG_BANK2_ROW 0 -#define CFG_BANK1_ROW 2 -#define CFG_BANK0_ROW 2 - -/**** MCCR2, refresh interval clock cycles ****/ -#define CFG_REFINT 480 /* 33 MHz SDRAM clock was 480 */ - -/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ -#define CFG_BSTOPRE 1023 /* burst to precharge[0..9], */ - /* sets open page interval */ - -/**** MCCR3 ****/ -#define CFG_REFREC 7 /* Refresh to activate interval, trc */ - -/**** MCCR4 ****/ -#define CFG_PRETOACT 2 /* trp */ -#define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */ -#define CFG_ACTORW 2 /* trcd min */ -#define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */ -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 0 /* we don't need extended ROM space */ -#define CFG_REGDIMM 0 - -/* calculate according to formula in sec. 6-22 of 8245 UM */ -#define CFG_PGMAX 50 /* how long the 8245 retains the */ - /* currently accessed page in memory */ - /* was 45 */ - -#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */ - /* bits 7,6, and 3-0 MUST be 0 */ - -#if 0 -#define CFG_DLL_MAX_DELAY 0x04 -#else -#define CFG_DLL_MAX_DELAY 0 -#endif -#if 0 /* need for 33MHz SDRAM */ -#define CFG_DLL_EXTEND 0x80 -#else -#define CFG_DLL_EXTEND 0 -#endif -#define CFG_PCI_HOLD_DEL 0x20 - - -/* Memory bank settings. - * Only bits 20-29 are actually used from these values to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8245 user manual. - */ - -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE/2 - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START CFG_MAX_RAM_SIZE/2 -#define CFG_BANK1_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK1_ENABLE 1 -#define CFG_BANK2_START 0x3ff00000 /* not available in this design */ -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x3ff00000 -#define CFG_BANK4_END 0x3fffffff -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x3ff00000 -#define CFG_BANK5_END 0x3fffffff -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x3ff00000 -#define CFG_BANK6_END 0x3fffffff -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x3ff00000 -#define CFG_BANK7_END 0x3fffffff -#define CFG_BANK7_ENABLE 0 - -/*--------------------------------------------------------------------*/ -/* 4.4 - Output Driver Control Register */ -/*--------------------------------------------------------------------*/ -#define CFG_ODCR 0xe5 - -/*--------------------------------------------------------------------*/ -/* 4.8 - Error Handling Registers */ -/*-------------------------------CFG_SDMODE_BURSTLEN-------------------------------------*/ -#define CFG_ERRENR1 0x11 /* enable SDRAM refresh overflow error */ - -/* SDRAM 0-256 MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -/*#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */ -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in dcache */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - - -#define CFG_IBAT2L (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT2U (CFG_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP) - -/* PCI memory */ -/*#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */ -/*#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */ - -/*Flash, config addrs, etc. */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - *----------------------------------------------------------------------*/ -#define CFG_FLASH_BASE 0xFF800000 -#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ - -/* NOTE: environment is not EMBEDDED in the u-boot code. - It's stored in flash in its own separate sector. */ -#define CFG_ENV_IS_IN_FLASH 1 - -#if 1 /* AMD AM29LV033C */ -#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */ -#define CFG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */ -#define CFG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */ -#else /* AMD AM29LV116D */ -#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */ -#define CFG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */ -#define CFG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */ -#endif /* #if */ - -#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE /* Size of the Environment */ -#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#undef CFG_RAMBOOT -#else -#define CFG_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/v37.h b/include/configs/v37.h deleted file mode 100644 index a2e99b5..0000000 --- a/include/configs/v37.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_V37 1 /* ...on a Marel V37 board */ - -#define CONFIG_LCD -#define CONFIG_SHARP_LQ084V1DG21 -#undef CONFIG_LCD_LOGO - -/*----------------------------------------------------------------------------- - * I2C Configuration - *----------------------------------------------------------------------------- - */ -#define CONFIG_I2C 1 -#define CFG_I2C_SLAVE 0x2 - -#define CONFIG_8xx_CONS_SMC1 1 -#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs console=tty0 " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ - -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DATE ) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor1=v37-1" -#define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)" -*/ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CFG_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE0 0x40000000 -#define CFG_FLASH_BASE1 0x60000000 -#define CFG_FLASH_BASE CFG_FLASH_BASE1 - -#if defined(DEBUG) -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE0 -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_ENV_IS_IN_NVRAM 1 -#define CFG_ENV_ADDR 0x80000000/* Address of Environment */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#define CFG_ENV_OFFSET 0 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CFG_SYPCR 0xFFFFFF88 -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) -/* -#define CFG_PISCR (PISCR_PS | PISCR_PITF) -*/ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_PLPRCR ( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS ) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -/* up to 50 MHz we use a 1:1 clock */ -#define CFG_SCCR (SCCR_COM00 | SCCR_TBS) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CFG_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ - -#define CFG_OR_TIMING_FLASH 0xF56 - -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V) - -#define CFG_OR5_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_BR5_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V) - -/* - * BR1 and OR1 (Battery backed SRAM) - */ -#define CFG_BR1_PRELIM 0x80000401 -#define CFG_OR1_PRELIM 0xFFC00736 - -/* - * BR2 and OR2 (SDRAM) - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB */ - -#define CFG_OR_TIMING_SDRAM 0x00000A00 - -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) -#define CFG_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* Marel V37 mem setting */ - -#define CFG_BR3_CAN 0xC0000401 -#define CFG_OR3_CAN 0xFFFF0724 - -/* -#define CFG_BR3_PRELIM 0xFA400001 -#define CFG_OR3_PRELIM 0xFFFF8910 -#define CFG_BR4_PRELIM 0xFA000401 -#define CFG_OR4_PRELIM 0xFFFE0970 -*/ - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* - * Refresh clock Prescalar - */ -#define CFG_MPTPR MPTPR_PTP_DIV16 - -/* - * MAMR settings for SDRAM - */ - -/* 10 column SDRAM */ -#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ - MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/versatile.h b/include/configs/versatile.h deleted file mode 100644 index 16db43b..0000000 --- a/include/configs/versatile.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta - * Configuation settings for the TI OMAP Innovator board. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * Configuration for Versatile PB. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */ -#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ - - -#define CFG_MEMTEST_START 0x100000 -#define CFG_MEMTEST_END 0x10000000 -#define CFG_HZ (1000000 / 256) -#define CFG_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */ - -#define CFG_TIMER_INTERVAL 10000 -#define CFG_TIMER_RELOAD (CFG_TIMER_INTERVAL >> 4) /* Divide by 16 */ -#define CFG_TIMER_CTRL 0x84 /* Enable, Clock / 16 */ - -/* - * control registers - */ -#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ - -/* - * System controller bit assignment - */ -#define VERSATILE_REFCLK 0 -#define VERSATILE_TIMCLK 1 - -#define VERSATILE_TIMER1_EnSel 15 -#define VERSATILE_TIMER2_EnSel 17 -#define VERSATILE_TIMER3_EnSel 19 -#define VERSATILE_TIMER4_EnSel 21 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ -/* - * Size of malloc() pool - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ - -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC91111_BASE 0x10010000 -#undef CONFIG_SMC91111_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CFG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } -#define CONFIG_CONS_INDEX 0 - -#define CONFIG_BAUDRATE 38400 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_SERIAL0 0x101F1000 -#define CFG_SERIAL1 0x101F2000 - -#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV) - -/*#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) */ - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0" -/*#define CONFIG_BOOTCOMMAND "bootp ; bootm" */ - -/* - * Static configuration when assigning fixed address - */ -/*#define CONFIG_NETMASK 255.255.255.0 /--* talk on MY local net */ -/*#define CONFIG_IPADDR xx.xx.xx.xx /--* static IP I currently own */ -/*#define CONFIG_SERVERIP xx.xx.xx.xx /--* current IP of my dev pc */ -#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */ - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "Versatile # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ - -#define CFG_FLASH_BASE 0x34000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define VERSATILE_SYS_BASE 0x10000000 -#define VERSATILE_SYS_FLASH_OFFSET 0x4C -#define VERSATILE_FLASHCTRL (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) -#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */ -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ -#define CFG_MAX_FLASH_SECT (256) - -#define PHYS_FLASH_1 (CFG_FLASH_BASE) - -#define CFG_ENV_IS_IN_FLASH 1 /* env in flash instead of CFG_ENV_IS_NOWHERE */ -#define CFG_ENV_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CFG_ENV_OFFSET 0x01f00000 /* environment starts here */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) - -#endif /* __CONFIG_H */ diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h deleted file mode 100644 index c5ee78f..0000000 --- a/include/configs/voiceblue.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl - * - * Configuation settings for the TI OMAP VoiceBlue board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1510 1 /* which is in a 5910 */ - -/* Input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ -#define CONFIG_XTAL_FREQ 12000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R /* There is nothing to really init */ -#define BOARD_LATE_INIT /* but we flash the LEDs here */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE SZ_64M - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x0c000000 - -#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ - -/* - * FLASH organization - */ -#define CFG_FLASH_CFI /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER /* Use the common driver */ -#define CFG_MAX_FLASH_BANKS 1 -#ifdef VOICEBLUE_SMALL_FLASH -#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_2 } -#else -#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } -#endif - -/* FIXME: Does not work on AMD flash */ -/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_SECT 512 /* max # of sectors on one chip */ - -#define CFG_MONITOR_BASE PHYS_FLASH_1 -#define CFG_MONITOR_LEN SZ_128K - -/* - * Environment settings - */ -#ifdef VOICEBLUE_SMALL_FLASH -#define CFG_ENV_IS_NOWHERE -#define CFG_ENV_SIZE SZ_1K -#else -#define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) -#define CFG_ENV_SIZE SZ_8K -#define CFG_ENV_SECT_SIZE SZ_64K -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE - -#define CONFIG_ENV_OVERWRITE - -#define CFG_JFFS_CUSTOM_PART /* see board/voiceblue/jffs2parts.c */ -#endif - -/* - * Size of malloc() pool and stack - */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#ifdef VOICEBLUE_SMALL_FLASH -#define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE) -#define CONFIG_STACKSIZE SZ_8K -#else -#define CFG_MALLOC_LEN SZ_4M -#define CONFIG_STACKSIZE SZ_1M -#endif - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE 0x08000300 - -/* - * NS16550 Configuration - */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#ifdef VOICEBLUE_SMALL_FLASH -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_LOADB | \ - CFG_CMD_IMI | \ - CFG_CMD_FLASH | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_BOOTD | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_RUN) -#else -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_LOADB | \ - CFG_CMD_IMI | \ - CFG_CMD_FLASH | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_ENV | \ - CFG_CMD_BOOTD | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_JFFS2) -#endif - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -#define CONFIG_LOOPW - -#ifdef VOICEBLUE_SMALL_FLASH -#define CONFIG_BOOTDELAY 0 -#undef CONFIG_BOOTARGS /* the preboot command will set bootargs*/ -#define CFG_AUTOLOAD "n" /* no autoload */ -#define CONFIG_PREBOOT "run setup" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "setup=setenv bootargs console=ttyS0,${baudrate} " \ - "root=/dev/nfs ip=dhcp\0" \ - "update=erase c000000 c03ffff; " \ - "cp.b 10400000 c000000 ${filesize}\0" -#else -#define CONFIG_BOOTDELAY 3 -#undef CONFIG_BOOTARGS /* boot command will set bootargs */ -#define CFG_AUTOLOAD "n" /* no autoload */ -#define CONFIG_BOOTCOMMAND "run nboot" -#define CONFIG_PREBOOT "run setup" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ospart=0\0" \ - "swapos=no\0" \ - "setpart=" \ - "if test $swapos = yes; then " \ - "if test $ospart -eq 0; then chpart 4; else chpart 3; fi; "\ - "setenv swapos no; saveenv; " \ - "else " \ - "if test $ospart -eq 0; then chpart 3; else chpart 4; fi; "\ - "fi\0" \ - "setup=setenv bootargs console=ttyS0,$baudrate " \ - "mtdparts=$mtdparts\0" \ - "nfsargs=run setpart; setenv bootargs $bootargs " \ - "root=/dev/nfs ip=dhcp\0" \ - "flashargs=run setpart; setenv bootargs $bootargs " \ - "root=/dev/mtdblock$partition ro " \ - "rootfstype=jffs2\0" \ - "nboot=run nfsargs; bootp; tftp; bootm\0" \ - "fboot=run flashargs; fsload /boot/uImage; bootm\0" -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#ifndef VOICEBLUE_SMALL_FLASH -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CONFIG_AUTO_COMPLETE -#endif -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "# " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START PHYS_SDRAM_1 -#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. - * This time is further subdivided by a local divisor. - */ -#define CFG_TIMERBASE OMAP1510_TIMER1_BASE -#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) - -#define OMAP5910_DPLL_DIV 1 -#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ - (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) - -#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ -#define OMAP5910_LCD_DIV 2 /* CKL/4 */ -#define OMAP5910_ARM_DIV 0 /* CKL/1 */ -#define OMAP5910_DSP_DIV 0 /* CKL/1 */ -#define OMAP5910_TC_DIV 1 /* CKL/2 */ -#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ -#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ - -#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ -#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ - (OMAP5910_LCD_DIV << 2) | \ - (OMAP5910_ARM_DIV << 4) | \ - (OMAP5910_DSP_DIV << 6) | \ - (OMAP5910_TC_DIV << 8) | \ - (OMAP5910_DSP_MMU_DIV << 10) | \ - (OMAP5910_ARM_TIM_SEL << 12)) - -#define VOICEBLUE_LED_REG 0x04030000 - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00040000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=voiceblue-0" -#define MTDPARTS_DEFAULT "mtdparts=voiceblue-0:128k(uboot),64k(env),64k(renv),-(jffs2)" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/walnut.h b/include/configs/walnut.h deleted file mode 100644 index 1171ee5..0000000 --- a/include/configs/walnut.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_WALNUT 1 /* ...on a WALNUT board */ - /* ...and on a SYCAMORE board */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=walnut\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/walnut/uImage\0" \ - "kernel_addr=fff80000\0" \ - "ramdisk_addr=fff80000\0" \ - "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ - -#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/* - * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CFG_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CFG_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - -/*----------------------------------------------------------------------- - * I2C stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) - -/* - * Define here the location of the environment variables (FLASH or NVRAM). - * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only - * supported for backward compatibility. - */ -#if 1 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CFG_FLASH_ADDR0 0x5555 -#define CFG_FLASH_ADDR1 0x2aaa -#define CFG_FLASH_WORD_SIZE unsigned char - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ - -#ifdef CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ -#define CFG_ENV_ADDR \ - (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CFG_EBC_PB0AP 0x9B015480 -#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ - -#define CFG_EBC_PB1AP 0x02815480 -#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -#define CFG_EBC_PB2AP 0x04815A80 -#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ - -#define CFG_EBC_PB3AP 0x01815280 -#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ - -#define CFG_EBC_PB7AP 0x01815280 -#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/*----------------------------------------------------------------------- - * External peripheral base address - *----------------------------------------------------------------------- - */ -#define CFG_KEY_REG_BASE_ADDR 0xF0100000 -#define CFG_IR_REG_BASE_ADDR 0xF0200000 -#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ - -#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h deleted file mode 100644 index 47251bb..0000000 --- a/include/configs/wepep250.h +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (C) 2003 ETC s.r.o. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Written by Peter Figuli , 2003. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PXA250 1 /* this is an PXA250 CPU */ -#define CONFIG_WEPEP250 1 /* config for wepep250 board */ -#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ - - -/* - * Select serial console configuration - */ -#define CONFIG_BTUART 1 /* BTUART is default on WEP dev board */ -#define CONFIG_BAUDRATE 115200 - - -/* - * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if - * neccessary in include/cmd_confdefs.h file. (Un)comment for getting - * functionality or size of u-boot code. - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - & ~CFG_CMD_NET \ - & ~CFG_CMD_LOADS \ - & ~CFG_CMD_CONSOLE \ - & ~CFG_CMD_AUTOSCRIPT \ -/* | CFG_CMD_JFFS2 */ \ - ) -#include - -/* - * Boot options. Setting delay to -1 stops autostart count down. - * NOTE: Sending parameters to kernel depends on kernel version and - * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept - * parameters at all! Do not get confused by them so. - */ -#define CONFIG_BOOTDELAY -1 -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8" -#define CONFIG_BOOTCOMMAND "bootm 40000" - - -/* - * General options for u-boot. Modify to save memory foot print - */ -#define CFG_LONGHELP /* undef saves memory */ -#define CFG_PROMPT "WEP> " /* prompt string */ -#define CFG_CBSIZE 256 /* console I/O buffer */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ -#define CFG_MAXARGS 16 /* max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ - -#define CFG_MEMTEST_START 0xa0400000 /* memtest test area */ -#define CFG_MEMTEST_END 0xa0800000 - -#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x141 /* core clock - register value */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Definitions related to passing arguments to kernel. - */ -#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ -#undef CONFIG_INITRD_TAG /* do not send initrd params */ -#undef CONFIG_VFD /* do not send framebuffer setup */ - - -/* - * Malloc pool need to host env + 128 Kb reserve for other allocations. - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -#define CONFIG_STACKSIZE (120<<10) /* stack size */ - -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ -#endif - -/* - * SDRAM Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define WEP_SDRAM_1 0xa0000000 /* SDRAM bank #1 */ -#define WEP_SDRAM_1_SIZE 0x02000000 /* 32 MB ( 2 chip ) */ -#define WEP_SDRAM_2 0xa2000000 /* SDRAM bank #2 */ -#define WEP_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define WEP_SDRAM_3 0xa8000000 /* SDRAM bank #3 */ -#define WEP_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define WEP_SDRAM_4 0xac000000 /* SDRAM bank #4 */ -#define WEP_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x02000000 - -/* Uncomment used SDRAM chip */ -#define WEP_SDRAM_K4S281633 -/*#define WEP_SDRAM_K4S561633*/ - - -/* - * Configuration for FLASH memory - */ -#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ -#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ -#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ -#define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/ -#define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */ -#define WEP_FLASH_BASE 0x0000000 /* location of flash memory */ -#define WEP_FLASH_UNLOCK 1 /* perform hw unlock first */ - - -/* This should be defined if CFI FLASH device is present. Actually benefit - is not so clear to me. In other words we can provide more informations - to user, but this expects more complex flash handling we do not provide - now.*/ -#undef CFG_FLASH_CFI - -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ - -#define CFG_FLASH_BASE WEP_FLASH_BASE - -/* - * This is setting for JFFS2 support in u-boot. - * Right now there is no gain for user, but later on booting kernel might be - * possible. Consider using XIP kernel running from flash to save RAM - * footprint. - * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. - */ -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_FIRST_SECTOR 5 -#define CFG_JFFS2_NUM_BANKS 1 - -/* - * Environment setup. Definitions of monitor location and size with - * definition of environment setup ends up in 2 possibilities. - * 1. Embeded environment - in u-boot code is space for environment - * 2. Environment is read from predefined sector of flash - * Right now we support 2. possiblity, but expecting no env placed - * on mentioned address right now. This also needs to provide whole - * sector for it - for us 256Kb is really waste of memory. U-boot uses - * default env. and until kernel parameters could be sent to kernel - * env. has no sense to us. - */ - -#define CFG_MONITOR_BASE PHYS_FLASH_1 -#define CFG_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0x20000 /* absolute address for now */ -#define CFG_ENV_SIZE 0x2000 - -#undef CONFIG_ENV_OVERWRITE /* env is not writable now */ - -/* - * Well this has to be defined, but on the other hand it is used differently - * one may expect. For instance loadb command do not cares :-) - * So advice is - do not relay on this... - */ -#define CFG_LOAD_ADDR 0x40000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h deleted file mode 100644 index 1039762..0000000 --- a/include/configs/xaeniax.h +++ /dev/null @@ -1,557 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2004 - * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Configuation settings for the xaeniax board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA255 CPU */ -#define CONFIG_XAENIAX 1 /* on a xaeniax board */ - - -#define BOARD_LATE_INIT 1 - - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * select serial console configuration - */ -#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */ - - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_BAUDRATE 115200 - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_DTT) | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_NFS | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.68.201 -#define CONFIG_SERVERIP 192.168.68.62 - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTCOMMAND "bootm 0x00100000" -#define CONFIG_BOOTARGS "console=ttyS1,115200" -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Size of malloc() pool; this lives below the uppermost 128 KiB which are - * used for the RAM copy of the uboot code - */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_HUSH_PARSER 1 - -#define CFG_PROMPT_HUSH_PS2 "> " - -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "u-boot$ " /* Monitor Command Prompt */ -#else -#define CFG_PROMPT "u-boot=> " /* Monitor Command Prompt */ -#endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - -/* FIXME */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * SMSC91C111 Network Card - */ -#define CONFIG_DRIVER_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */ -#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ -#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ -#undef CONFIG_SHOW_ACTIVITY -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ - -/* - * GPIO settings - */ - -/* - * GP05 == nUSBReset is 1 - * GP10 == CFReset is 1 - * GP13 == nCFDataEnable is 1 - * GP14 == nCFAddrEnable is 1 - * GP15 == nCS1 is 1 - * GP21 == ComBrdReset is 1 - * GP24 == SFRM is 1 - * GP25 == TXD is 1 - * GP31 == SYNC is 1 - * GP33 == nCS5 is 1 - * GP39 == FFTXD is 1 - * GP41 == RTS is 1 - * GP43 == BTTXD is 1 - * GP45 == BTRTS is 1 - * GP47 == TXD is 1 - * GP48 == nPOE is 1 - * GP49 == nPWE is 1 - * GP50 == nPIOR is 1 - * GP51 == nPIOW is 1 - * GP52 == nPCE[1] is 1 - * GP53 == nPCE[2] is 1 - * GP54 == nPSKTSEL is 1 - * GP55 == nPREG is 1 - * GP78 == nCS2 is 1 - * GP79 == nCS3 is 1 - * GP80 == nCS4 is 1 - * GP82 == NSSPSFRM is 1 - * GP83 == NSSPTXD is 1 - */ -#define CFG_GPSR0_VAL 0x8320E420 -#define CFG_GPSR1_VAL 0x00FFAA82 -#define CFG_GPSR2_VAL 0x000DC000 - -/* - * GP03 == LANReset is 0 - * GP06 == USBWakeUp is 0 - * GP11 == USBControl is 0 - * GP12 == Buzzer is 0 - * GP16 == PWM0 is 0 - * GP17 == PWM1 is 0 - * GP23 == SCLK is 0 - * GP30 == SDATA_OUT is 0 - * GP81 == NSSPCLK is 0 - */ -#define CFG_GPCR0_VAL 0x40C31848 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00020000 - -/* - * GP00 == CPUWakeUpUSB is input - * GP01 == GP reset is input - * GP02 == LANInterrupt is input - * GP03 == LANReset is output - * GP04 == USBInterrupt is input - * GP05 == nUSBReset is output - * GP06 == USBWakeUp is output - * GP07 == CFReady/nBusy is input - * GP08 == nCFCardDetect1 is input - * GP09 == nCFCardDetect2 is input - * GP10 == nCFReset is output - * GP11 == USBControl is output - * GP12 == Buzzer is output - * GP13 == CFDataEnable is output - * GP14 == CFAddressEnable is output - * GP15 == nCS1 is output - * GP16 == PWM0 is output - * GP17 == PWM1 is output - * GP18 == RDY is input - * GP19 == ReaderReady is input - * GP20 == ReaderReset is input - * GP21 == ComBrdReset is output - * GP23 == SCLK is output - * GP24 == SFRM is output - * GP25 == TXD is output - * GP26 == RXD is input - * GP27 == EXTCLK is input - * GP28 == BITCLK is output - * GP29 == SDATA_IN0 is input - * GP30 == SDATA_OUT is output - * GP31 == SYNC is output - * GP32 == SYSSCLK is output - * GP33 == nCS5 is output - * GP34 == FFRXD is input - * GP35 == CTS is input - * GP36 == DCD is input - * GP37 == DSR is input - * GP38 == RI is input - * GP39 == FFTXD is output - * GP40 == DTR is output - * GP41 == RTS is output - * GP42 == BTRXD is input - * GP43 == BTTXD is output - * GP44 == BTCTS is input - * GP45 == BTRTS is output - * GP46 == RXD is input - * GP47 == TXD is output - * GP48 == nPOE is output - * GP49 == nPWE is output - * GP50 == nPIOR is output - * GP51 == nPIOW is output - * GP52 == nPCE[1] is output - * GP53 == nPCE[2] is output - * GP54 == nPSKTSEL is output - * GP55 == nPREG is output - * GP56 == nPWAIT is input - * GP57 == nPIOS16 is input - * GP58 == LDD[0] is output - * GP59 == LDD[1] is output - * GP60 == LDD[2] is output - * GP61 == LDD[3] is output - * GP62 == LDD[4] is output - * GP63 == LDD[5] is output - * GP64 == LDD[6] is output - * GP65 == LDD[7] is output - * GP66 == LDD[8] is output - * GP67 == LDD[9] is output - * GP68 == LDD[10] is output - * GP69 == LDD[11] is output - * GP70 == LDD[12] is output - * GP71 == LDD[13] is output - * GP72 == LDD[14] is output - * GP73 == LDD[15] is output - * GP74 == LCD_FCLK is output - * GP75 == LCD_LCLK is output - * GP76 == LCD_PCLK is output - * GP77 == LCD_ACBIAS is output - * GP78 == nCS2 is output - * GP79 == nCS3 is output - * GP80 == nCS4 is output - * GP81 == NSSPCLK is output - * GP82 == NSSPSFRM is output - * GP83 == NSSPTXD is output - * GP84 == NSSPRXD is input - */ -#define CFG_GPDR0_VAL 0xD3E3FC68 -#define CFG_GPDR1_VAL 0xFCFFAB83 -#define CFG_GPDR2_VAL 0x000FFFFF - -/* - * GP01 == GP reset is AF01 - * GP15 == nCS1 is AF10 - * GP16 == PWM0 is AF10 - * GP17 == PWM1 is AF10 - * GP18 == RDY is AF01 - * GP23 == SCLK is AF10 - * GP24 == SFRM is AF10 - * GP25 == TXD is AF10 - * GP26 == RXD is AF01 - * GP27 == EXTCLK is AF01 - * GP28 == BITCLK is AF01 - * GP29 == SDATA_IN0 is AF10 - * GP30 == SDATA_OUT is AF01 - * GP31 == SYNC is AF01 - * GP32 == SYSCLK is AF01 - * GP33 == nCS5 is AF10 - * GP34 == FFRXD is AF01 - * GP35 == CTS is AF01 - * GP36 == DCD is AF01 - * GP37 == DSR is AF01 - * GP38 == RI is AF01 - * GP39 == FFTXD is AF10 - * GP40 == DTR is AF10 - * GP41 == RTS is AF10 - * GP42 == BTRXD is AF01 - * GP43 == BTTXD is AF10 - * GP44 == BTCTS is AF01 - * GP45 == BTRTS is AF10 - * GP46 == RXD is AF10 - * GP47 == TXD is AF01 - * GP48 == nPOE is AF10 - * GP49 == nPWE is AF10 - * GP50 == nPIOR is AF10 - * GP51 == nPIOW is AF10 - * GP52 == nPCE[1] is AF10 - * GP53 == nPCE[2] is AF10 - * GP54 == nPSKTSEL is AF10 - * GP55 == nPREG is AF10 - * GP56 == nPWAIT is AF01 - * GP57 == nPIOS16 is AF01 - * GP58 == LDD[0] is AF10 - * GP59 == LDD[1] is AF10 - * GP60 == LDD[2] is AF10 - * GP61 == LDD[3] is AF10 - * GP62 == LDD[4] is AF10 - * GP63 == LDD[5] is AF10 - * GP64 == LDD[6] is AF10 - * GP65 == LDD[7] is AF10 - * GP66 == LDD[8] is AF10 - * GP67 == LDD[9] is AF10 - * GP68 == LDD[10] is AF10 - * GP69 == LDD[11] is AF10 - * GP70 == LDD[12] is AF10 - * GP71 == LDD[13] is AF10 - * GP72 == LDD[14] is AF10 - * GP73 == LDD[15] is AF10 - * GP74 == LCD_FCLK is AF10 - * GP75 == LCD_LCLK is AF10 - * GP76 == LCD_PCLK is AF10 - * GP77 == LCD_ACBIAS is AF10 - * GP78 == nCS2 is AF10 - * GP79 == nCS3 is AF10 - * GP80 == nCS4 is AF10 - * GP81 == NSSPCLK is AF01 - * GP82 == NSSPSFRM is AF01 - * GP83 == NSSPTXD is AF01 - * GP84 == NSSPRXD is AF10 - */ -#define CFG_GAFR0_L_VAL 0x80000004 -#define CFG_GAFR0_U_VAL 0x595A801A -#define CFG_GAFR1_L_VAL 0x699A9559 -#define CFG_GAFR1_U_VAL 0xAAA5AAAA -#define CFG_GAFR2_L_VAL 0xAAAAAAAA -#define CFG_GAFR2_U_VAL 0x00000256 - -/* - * clock settings - */ -/* RDH = 1 - * PH = 0 - * VFS = 0 - * BFS = 0 - * SSS = 0 - */ -#define CFG_PSSR_VAL 0x00000030 - -#define CFG_CKEN_VAL 0x00000080 /* */ -#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ - - -/* - * Memory settings - * - * This is the configuration for nCS0/1 -> flash banks - * configuration for nCS1 : - * [31] 0 - - * [30:28] 000 - - * [27:24] 0000 - - * [23:20] 0000 - - * [19] 0 - - * [18:16] 000 - - * configuration for nCS0: - * [15] 0 - Slower Device - * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns - * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?) - * [03] 0 - 32 Bit bus width - * [02:00] 010 - burst OF 4 ROM or FLASH -*/ -#define CFG_MSC0_VAL 0x000023D2 - -/* This is the configuration for nCS2/3 -> USB controller, LAN - * configuration for nCS3: LAN - * [31] 0 - Slower Device - * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns - * [19] 0 - 32 Bit bus width - * [18:16] 100 - variable latency I/O - * configuration for nCS2: USB - * [15] 1 - Faster Device - * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns - * [03] 1 - 16 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CFG_MSC1_VAL 0x1224A26C - -/* This is the configuration for nCS4/5 -> LAN - * configuration for nCS5: - * [31] 0 - - * [30:28] 000 - - * [27:24] 0000 - - * [23:20] 0000 - - * [19] 0 - - * [18:16] 000 - - * configuration for nCS4: LAN - * [15] 1 - Faster Device - * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns - * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns - * [03] 0 - 32 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CFG_MSC2_VAL 0x00001224 - -/* MDCNFG: SDRAM Configuration Register - * - * [31:29] 000 - reserved - * [28] 0 - no SA1111 compatiblity mode - * [27] 0 - latch return data with return clock - * [26] 0 - alternate addressing for pair 2/3 - * [25:24] 00 - timings - * [23] 0 - internal banks in lower partition 2/3 (not used) - * [22:21] 00 - row address bits for partition 2/3 (not used) - * [20:19] 00 - column address bits for partition 2/3 (not used) - * [18] 0 - SDRAM partition 2/3 width is 32 bit - * [17] 0 - SDRAM partition 3 disabled - * [16] 0 - SDRAM partition 2 disabled - * [15:13] 000 - reserved - * [12] 0 - no SA1111 compatiblity mode - * [11] 1 - latch return data with return clock - * [10] 0 - no alternate addressing for pair 0/1 - * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk - * [7] 1 - 4 internal banks in lower partition pair - * [06:05] 10 - 13 row address bits for partition 0/1 - * [04:03] 01 - 9 column address bits for partition 0/1 - * [02] 0 - SDRAM partition 0/1 width is 32 bit - * [01] 0 - disable SDRAM partition 1 - * [00] 1 - enable SDRAM partition 0 - */ -/* use the configuration above but disable partition 0 */ -#define CFG_MDCNFG_VAL 0x00000AC9 - -/* MDREFR: SDRAM Refresh Control Register - * - * [32:26] 0 - reserved - * [25] 0 - K2FREE: not free running - * [24] 0 - K1FREE: not free running - * [23] 0 - K0FREE: not free running - * [22] 0 - SLFRSH: self refresh disabled - * [21] 0 - reserved - * [20] 1 - APD: auto power down - * [19] 0 - K2DB2: SDCLK2 is MemClk - * [18] 0 - K2RUN: disable SDCLK2 - * [17] 0 - K1DB2: SDCLK1 is MemClk - * [16] 1 - K1RUN: enable SDCLK1 - * [15] 1 - E1PIN: SDRAM clock enable - * [14] 0 - K0DB2: SDCLK0 is MemClk - * [13] 0 - K0RUN: disable SDCLK0 - * [12] 0 - E0PIN: disable SDCKE0 - * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 - */ -#define CFG_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */ - -/* MDMRS: Mode Register Set Configuration Register - * - * [31] 0 - reserved - * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) - * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used) - * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) - * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) - * [15] 0 - reserved - * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. - * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency. - * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. - * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. - */ -#define CFG_MDMRS_VAL 0x00320032 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 - - -#endif /* __CONFIG_H */ diff --git a/include/configs/xm250.h b/include/configs/xm250.h deleted file mode 100644 index 952f73b..0000000 --- a/include/configs/xm250.h +++ /dev/null @@ -1,349 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -/* - * Size of malloc() pool; this lives below the uppermost 128 KiB which are - * used for the RAM copy of the uboot code - * - */ -#define CFG_MALLOC_LEN (256*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* - * Hardware drivers - */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE 0x04000300 -#undef CONFIG_SMC91111_EXT_PHY -#define CONFIG_SMC_USE_32_BIT -#undef CONFIG_SHOW_ACTIVITY -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ - -/* - * I2C bus - */ -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xfe - -#define CONFIG_RTC_PCF8563 1 -#define CFG_I2C_RTC_ADDR 0x51 - -#define CFG_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */ -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* length of address */ -#define CFG_EEPROM_SIZE 2048 /* size in bytes */ -#undef CFG_I2C_INIT_BOARD /* board has no own init */ - -/* - * select serial console configuration - */ -#define CONFIG_FFUART 1 /* we use FFUART */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -#define CFG_LOAD_ADDR 0xa3000000 /* default load address */ - -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */ - - /* valid baudrates */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Definitions related to passing arguments to kernel. - */ -#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ -#undef CONFIG_INITRD_TAG /* do not send initrd params */ -#undef CONFIG_VFD /* do not send framebuffer setup */ - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 4 -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ -#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ - -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#define CFG_FLASH_LOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Set Lock Bit */ -#define CFG_FLASH_UNLOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Clear Lock Bits */ -#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 -#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ -#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ - -/****************************************************************************** - * - * CPU specific defines - * - ******************************************************************************/ - -/* - * GPIO settings - * - * GPIO pin assignments - * GPIO Name Dir Out AF - * 0 NC - * 1 NC - * 2 SIRQ1 I - * 3 SIRQ2 I - * 4 SIRQ3 I - * 5 DMAACK1 O 0 - * 6 DMAACK2 O 0 - * 7 DMAACK3 O 0 - * 8 TC1 O 0 - * 9 TC2 O 0 - * 10 TC3 O 0 - * 11 nDMAEN O 1 - * 12 AENCTRL O 0 - * 13 PLDTC O 0 - * 14 ETHIRQ I - * 15 NC - * 16 NC - * 17 NC - * 18 RDY I - * 19 DMASIO I - * 20 ETHIRQ NC - * 21 NC - * 22 PGMEN O 1 FIXME for debug only enable flash - * 23 NC - * 24 NC - * 25 NC - * 26 NC - * 27 NC - * 28 NC - * 29 NC - * 30 NC - * 31 NC - * 32 NC - * 33 NC - * 34 FFRXD I 01 - * 35 FFCTS I 01 - * 36 FFDCD I 01 - * 37 FFDSR I 01 - * 38 FFRI I 01 - * 39 FFTXD O 1 10 - * 40 FFDTR O 0 10 - * 41 FFRTS O 0 10 - * 42 RS232FOFF O 0 00 - * 43 NC - * 44 NC - * 45 IRSL0 O 0 - * 46 IRRX0 I 01 - * 47 IRTX0 O 0 10 - * 48 NC - * 49 nIOWE O 0 - * 50 NC - * 51 NC - * 52 NC - * 53 NC - * 54 NC - * 55 NC - * 56 NC - * 57 NC - * 58 DKDIRQ I - * 59 NC - * 60 NC - * 61 NC - * 62 NC - * 63 NC - * 64 COMLED O 0 - * 65 COMLED O 0 - * 66 COMLED O 0 - * 67 COMLED O 0 - * 68 COMLED O 0 - * 69 COMLED O 0 - * 70 COMLED O 0 - * 71 COMLED O 0 - * 72 NC - * 73 NC - * 74 NC - * 75 NC - * 76 NC - * 77 NC - * 78 CSIO O 1 - * 79 NC - * 80 CSETH O 1 - * - * NOTE: All NC's are defined to be outputs - * - */ -/* Pin direction control */ -#define CFG_GPDR0_VAL 0xd3808000 -#define CFG_GPDR1_VAL 0xfcffab83 -#define CFG_GPDR2_VAL 0x0001ffff -/* Set and Clear registers */ -#define CFG_GPSR0_VAL 0x00008000 -#define CFG_GPSR1_VAL 0x00ff0002 -#define CFG_GPSR2_VAL 0x0001c000 -#define CFG_GPCR0_VAL 0x00000000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 -/* Edge detect registers (these are set by the kernel) */ -#define CFG_GRER0_VAL 0x00002180 -#define CFG_GRER1_VAL 0x00000000 -#define CFG_GRER2_VAL 0x00000000 -#define CFG_GFER0_VAL 0x000043e0 -#define CFG_GFER1_VAL 0x00000000 -#define CFG_GFER2_VAL 0x00000000 -/* Alternate function registers */ -#define CFG_GAFR0_L_VAL 0x80000004 -#define CFG_GAFR0_U_VAL 0x595a8010 -#define CFG_GAFR1_L_VAL 0x699a9559 -#define CFG_GAFR1_U_VAL 0xaaa5aaaa -#define CFG_GAFR2_L_VAL 0xaaaaaaaa -#define CFG_GAFR2_U_VAL 0x00000002 - -/* - * Clocks, power control and interrupts - */ -#define CFG_PSSR_VAL 0x00000030 -#define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */ -#define CFG_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */ -#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ - -/* FIXME - * - * RTC settings - * Watchdog - * - */ - -/* - * Memory settings - * - */ -#define CFG_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */ -#define CFG_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */ -#define CFG_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */ -#define CFG_MDCNFG_VAL 0x000009c9 -#define CFG_MDMRS_VAL 0x00220022 -#define CFG_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */ - -/* - * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) - */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 - -/* Board specific defines */ - -#ifndef __ASSEMBLY__ - -/* global prototypes */ -void led_code(int code, int color); - -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h deleted file mode 100644 index dc702cf..0000000 --- a/include/configs/xsengine.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_XSENGINE 1 -#define CONFIG_MMC 1 -#define BOARD_POST_INIT 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 - -/* FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */ -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* - * JFFS2 partitions - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=xsengine-0" -#define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)" -*/ - -/* Environment settings */ -#define CONFIG_ENV_OVERWRITE -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/ -#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (75*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (50*CFG_HZ) /* Timeout for Flash Write */ - -/* Size of malloc() pool */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ - -/* Hardware drivers */ -#define CONFIG_DRIVER_SMC91111 -#define CONFIG_SMC91111_BASE 0x04000300 -#define CONFIG_SMC_USE_32_BIT 1 - -/* select serial console configuration */ -#define CONFIG_FFUART 1 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.1.50 -#define CONFIG_SERVERIP 192.168.1.2 -#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200" -#define CONFIG_CMDLINE_TAG - -/* Miscellaneous configurable options */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0xA0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */ -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ -#define CFG_MMC_BASE 0xF0000000 -#define CFG_LOAD_ADDR 0xA0000000 /* load kernel to this address */ - -/* Stack sizes - The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* GP set register */ -#define CFG_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */ -#define CFG_GPSR1_VAL 0x00020000 /* nPWE */ -#define CFG_GPSR2_VAL 0x0000C000 /* CS2, CS3 */ - -/* GP clear register */ -#define CFG_GPCR0_VAL 0x00000000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 - -/* GP direction register */ -#define CFG_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */ -#define CFG_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */ -#define CFG_GPDR2_VAL 0x0000C000 /* CS2, CS3 */ - -/* GP rising edge detect register */ -#define CFG_GRER0_VAL 0x00000000 -#define CFG_GRER1_VAL 0x00000000 -#define CFG_GRER2_VAL 0x00000000 - -/* GP falling edge detect register */ -#define CFG_GFER0_VAL 0x00000000 -#define CFG_GFER1_VAL 0x00000000 -#define CFG_GFER2_VAL 0x00000000 - -/* GP alternate function register */ -#define CFG_GAFR0_L_VAL 0x80000000 /* CS1 */ -#define CFG_GAFR0_U_VAL 0x00000010 /* RDY */ -#define CFG_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */ -#define CFG_GAFR1_U_VAL 0x00000008 /* nPWE */ -#define CFG_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */ -#define CFG_GAFR2_U_VAL 0x00000000 - -#define CFG_PSSR_VAL 0x00000020 /* Power manager sleep status */ -#define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */ -#define CFG_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */ -#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ - -/* Memory settings */ -#define CFG_MSC0_VAL 0x25F425F0 - -/* MDCNFG: SDRAM Configuration Register */ -#define CFG_MDCNFG_VAL 0x000009C9 - -/* MDREFR: SDRAM Refresh Control Register */ -#define CFG_MDREFR_VAL 0x00018018 - -/* MDMRS: Mode Register Set Configuration Register */ -#define CFG_MDMRS_VAL 0x00220022 - -#endif /* __CONFIG_H */ diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h deleted file mode 100644 index d3e9671..0000000 --- a/include/configs/yellowstone.h +++ /dev/null @@ -1,315 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * yellowstone.h - configuration for YELLOWSTONE board - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_YOLLOWSTONE 1 /* Board is Yellowstone */ -#define CONFIG_440GR 1 /* Specific PPC440EP support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 - -/*Don't change either of these*/ -#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ -#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ -/*Don't change either of these*/ - -#define CFG_USB_DEVICE 0x50000000 -#define CFG_NVRAM_BASE_ADDR 0x80000000 -#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) -#define CFG_BOOT_BASE_ADDR 0xf0000000 - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in SDRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CFG_INIT_RAM_END (8 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 -/*define this if you want console on UART1*/ -#undef CONFIG_UART1_CONSOLE - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or EEPROM). - * Note: DENX encourages to use redundant environment in FLASH. - */ -#if 1 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#endif - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ -#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ -#define CFG_SDRAM_BANKS (2) - - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ -#define CFG_ENV_OFFSET 0x0 -#endif /* CFG_ENV_IS_IN_EEPROM */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=yellowstone\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/yellowstone/uImage\0" \ - "kernel_addr=fc000000\0" \ - "ramdisk_addr=fc100000\0" \ - "load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0" \ - "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 100000 fff80000 80000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ -#define CONFIG_PHY1_ADDR 3 -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ - -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -#ifdef CONFIG_440EP -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/*Comment this out to enable USB 1.1 device*/ -#define USB_2_0_DEVICE -#endif /*CONFIG_440EP*/ - -#ifdef DEBUG -#define CONFIG_PANIC_HANG -#else -#define CONFIG_HW_WATCHDOG /* watchdog */ -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT -#define CFG_PCI_MASTER_INIT - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h deleted file mode 100644 index a67b834..0000000 --- a/include/configs/yosemite.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************ - * yosemite.h - configuration for YOSEMITE board - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_YOSEMITE 1 /* Board is Yosemite */ -#define CONFIG_440EP 1 /* Specific PPC440EP support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 - -/*Don't change either of these*/ -#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ -#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ -/*Don't change either of these*/ - -#define CFG_USB_DEVICE 0x50000000 -#define CFG_NVRAM_BASE_ADDR 0x80000000 -#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) -#define CFG_BOOT_BASE_ADDR 0xf0000000 - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in SDRAM) - *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CFG_INIT_RAM_END (8 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 -/*define this if you want console on UART1*/ -#undef CONFIG_UART1_CONSOLE - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or EEPROM). - * Note: DENX encourages to use redundant environment in FLASH. - */ -#if 1 -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#endif - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ - -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ -#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ -#define CFG_SDRAM_BANKS (2) - - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ -#define CFG_ENV_OFFSET 0x0 -#endif /* CFG_ENV_IS_IN_EEPROM */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=yosemite\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/yosemite/uImage\0" \ - "kernel_addr=fc000000\0" \ - "ramdisk_addr=fc100000\0" \ - "load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0" \ - "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 100000 fff80000 80000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ -#define CONFIG_PHY1_ADDR 3 -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ - -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -#ifdef CONFIG_440EP -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/*Comment this out to enable USB 1.1 device*/ -#define USB_2_0_DEVICE -#endif /*CONFIG_440EP*/ - -#ifdef DEBUG -#define CONFIG_PANIC_HANG -#else -#define CONFIG_HW_WATCHDOG /* watchdog */ -#endif - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_FAT | \ - CFG_CMD_EXT2 | \ - CFG_CMD_USB ) - -#define CONFIG_SUPPORT_VFAT - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ - -/* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT -#define CFG_PCI_MASTER_INIT - -#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/div64.h b/include/div64.h new file mode 100644 index 0000000..9e34767 --- /dev/null +++ b/include/div64.h @@ -0,0 +1,39 @@ +#ifndef _ASM_GENERIC_DIV64_H +#define _ASM_GENERIC_DIV64_H +/* + * Copyright (C) 2003 Bernardo Innocenti + * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h + * + * The semantics of do_div() are: + * + * uint32_t do_div(uint64_t *n, uint32_t base) + * { + * uint32_t remainder = *n % base; + * *n = *n / base; + * return remainder; + * } + * + * NOTE: macro parameter n is evaluated multiple times, + * beware of side effects! + */ + +#include + +extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor); + +/* The unnecessary pointer compare is there + * to check for type safety (n must be 64bit) + */ +# define do_div(n,base) ({ \ + uint32_t __base = (base); \ + uint32_t __rem; \ + (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \ + if (((n) >> 32) == 0) { \ + __rem = (uint32_t)(n) % __base; \ + (n) = (uint32_t)(n) / __base; \ + } else \ + __rem = __div64_32(&(n), __base); \ + __rem; \ + }) + +#endif /* _ASM_GENERIC_DIV64_H */ diff --git a/include/exports.h b/include/exports.h index 0eaf66e..7bcd080 100644 --- a/include/exports.h +++ b/include/exports.h @@ -20,6 +20,12 @@ void udelay(unsigned long); unsigned long get_timer(unsigned long); void vprintf(const char *, va_list); void do_reset (void); +#ifdef CONFIG_MARVELL +void *realloc(void*, size_t); +void *calloc(size_t, size_t); +void *memalign(size_t, size_t); +u32 mvGetRtcSec(void); +#endif #if (CONFIG_COMMANDS & CFG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); diff --git a/include/fat.h b/include/fat.h index 0645458..19a19a2 100644 --- a/include/fat.h +++ b/include/fat.h @@ -80,12 +80,13 @@ #define LS_DIR 1 #define LS_ROOT 2 +#undef DEBUG #ifdef DEBUG #define FAT_DPRINT(args...) printf(args) #else #define FAT_DPRINT(args...) #endif -#define FAT_ERROR(arg) printf(arg) +#define FAT_ERROR(arg...) printf(arg) #define ISDIRDELIM(c) ((c) == '/' || (c) == '\\') @@ -112,6 +113,8 @@ + (mydata->fatsize != 32 ? 0 : \ (FAT2CPU16((dent)->starthi) << 16))) +#define CHECK_CLUST(x, fatsize) ((x) <= 1 || \ + (x) >= ((fatsize) != 32 ? 0xfff0 : 0xffffff0)) typedef struct boot_sector { __u8 ignored[3]; /* Bootstrap code */ @@ -177,13 +180,13 @@ typedef struct dir_slot { /* Private filesystem parameters */ typedef struct { + __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ int fatsize; /* Size of FAT in bits */ __u16 fatlength; /* Length of FAT in sectors */ __u16 fat_sect; /* Starting sector of the FAT */ __u16 rootdir_sect; /* Start sector of root directory */ __u16 clust_size; /* Size of clusters in sectors */ short data_begin; /* The sector of the first cluster, can be negative */ - __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ int fatbufnum; /* Used by get_fatent, init to -1 */ } fsdata; diff --git a/include/flash.h b/include/flash.h index decb046..b6bc9b6 100644 --- a/include/flash.h +++ b/include/flash.h @@ -45,6 +45,12 @@ typedef struct { ushort vendor; /* the primary vendor id */ ushort cmd_reset; /* Vendor specific reset command */ ushort interface; /* used for x8/x16 adjustments */ + ushort legacy_unlock; /* support Intel legacy (un)locking */ + uchar manufacturer_id; /* manufacturer id */ + ushort device_id; /* device id */ + ushort device_id2; /* extended device id */ + ushort ext_addr; /* extended query table address */ + ushort cfi_version; /* cfi version */ #endif } flash_info_t; @@ -208,6 +214,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */ #define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */ #define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */ +#define AMD_ID_GL128N_2 0x22212221 /* 2nd ID word for S29GL128N */ +#define AMD_ID_GL128N_3 0x22012201 /* 3rd ID word for S29GL128N */ + #define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */ #define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */ @@ -233,6 +242,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define SST_ID_xF3202 0x235A235A /* 39xF3202 ID (32M = 2M x 16 ) */ #define SST_ID_xF6401 0x236B236B /* 39xF6401 ID (64M = 4M x 16 ) */ #define SST_ID_xF6402 0x236A236A /* 39xF6402 ID (64M = 4M x 16 ) */ +#define SST_ID_xF020 0xBFD6BFD6 /* 39xF020 ID (256KB = 2Mbit x 8) */ #define SST_ID_xF040 0xBFD7BFD7 /* 39xF040 ID (512KB = 4Mbit x 8) */ #define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */ @@ -242,6 +252,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */ #define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */ #define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */ +#define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */ #define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */ #define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */ @@ -269,10 +280,17 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */ #define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */ #define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */ +#define INTEL_ID_28F256J3A 0x001D001D /* 256M = 128K x 256 */ #define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */ #define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */ #define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */ #define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */ +#define INTEL_ID_28F64P30T 0x88178817 /* 64M = 32K x 255 + 32k x 4 */ +#define INTEL_ID_28F64P30B 0x881A881A /* 64M = 32K x 255 + 32k x 4 */ +#define INTEL_ID_28F128P30T 0x88188818 /* 128M = 64K x 255 + 32k x 4 */ +#define INTEL_ID_28F128P30B 0x881B881B /* 128M = 64K x 255 + 32k x 4 */ +#define INTEL_ID_28F256P30T 0x88198819 /* 256M = 128K x 255 + 32k x 4 */ +#define INTEL_ID_28F256P30B 0x881C881C /* 256M = 128K x 255 + 32k x 4 */ #define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */ #define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */ @@ -334,6 +352,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ #define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ #define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */ +#define FLASH_SST020 0x0024 /* SST 39xF020 ID (256KB = 2Mbit x 8 ) */ #define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */ #define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */ @@ -401,10 +420,12 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */ #define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */ #define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */ +#define FLASH_28F256J3A 0x00C6 /* INTEL 28F256J3A (256M = 128K x 256) */ #define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */ #define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */ #define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */ +#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */ #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ @@ -423,6 +444,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of #define FLASH_MAN_MT 0x00400000 #define FLASH_MAN_SHARP 0x00500000 #define FLASH_MAN_ATM 0x00600000 +#define FLASH_MAN_CFI 0x01000000 #define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ diff --git a/include/i2c.h b/include/i2c.h index 6d39080..629da27 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -59,7 +59,11 @@ void i2c_init_board(void); * Probe the given I2C chip address. Returns 0 if a chip responded, * not 0 on failure. */ +#if defined(CONFIG_MARVELL) +int i2c_probe (uchar chanNum, uchar chip); +#else int i2c_probe(uchar chip); +#endif /* * Read/Write interface: @@ -73,8 +77,8 @@ int i2c_probe(uchar chip); * * Returns: 0 on success, not 0 on failure */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); +int i2c_read(uchar channel, uchar chip, uint addr, int alen, uchar *buffer, int len); +int i2c_write(uchar channel, uchar chip, uint addr, int alen, uchar *buffer, int len); /* * Utility routines to read/write registers. diff --git a/include/ide.h b/include/ide.h index dfef32f..0d2c510 100644 --- a/include/ide.h +++ b/include/ide.h @@ -40,8 +40,16 @@ #ifdef CFG_64BIT_LBA typedef uint64_t lbaint_t; +#define IDE_BLOCK_NUMBER_MASK 0x0000fffff0000000 +#define LBA_LOW_REG_SHIFT 24 +#define LBA_MID_REG_SHIFT 32 +#define LBA_HIGH_REG_SHIFT 40 #else typedef ulong lbaint_t; +#define IDE_BLOCK_NUMBER_MASK 0xf0000000 +#define LBA_LOW_REG_SHIFT 24 +#define LBA_MID_REG_SHIFT 0 +#define LBA_HIGH_REG_SHIFT 0 #endif /* diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h new file mode 100644 index 0000000..6cdd1b8 --- /dev/null +++ b/include/linux/mtd/compat.h @@ -0,0 +1,46 @@ +#ifndef _LINUX_COMPAT_H_ +#define _LINUX_COMPAT_H_ + +#define __user +#define __iomem + +#define ndelay(x) udelay(1) + +#define printk printf + +#define KERN_EMERG +#define KERN_ALERT +#define KERN_CRIT +#define KERN_ERR +#define KERN_WARNING +#define KERN_NOTICE +#define KERN_INFO +#define KERN_DEBUG + +#define kmalloc(size, flags) malloc(size) +#define kfree(ptr) free(ptr) + +/* + * ..and if you can't take the strict + * types, you can specify one yourself. + * + * Or not use min/max at all, of course. + */ +#define min_t(type,x,y) \ + ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) +#define max_t(type,x,y) \ + ({ type __x = (x); type __y = (y); __x > __y ? __x: __y; }) + +#ifndef BUG +#define BUG() do { \ + printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \ +} while (0) + +#define BUG_ON(condition) do { if (condition) BUG(); } while(0) +#endif /* BUG */ + +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) + +//#define PAGE_SIZE 4096 +#endif diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h new file mode 100644 index 0000000..9c3393b --- /dev/null +++ b/include/linux/mtd/mtd-abi.h @@ -0,0 +1,99 @@ +/* + * $Id: mtd-abi.h,v 1.7 2004/11/23 15:37:32 gleixner Exp $ + * + * Portions of MTD ABI definition which are shared by kernel and user space + */ + +#ifndef __MTD_ABI_H__ +#define __MTD_ABI_H__ + +struct erase_info_user { + uint32_t start; + uint32_t length; +}; + +struct mtd_oob_buf { + uint32_t start; + uint32_t length; + unsigned char *ptr; +}; + +#define MTD_ABSENT 0 +#define MTD_RAM 1 +#define MTD_ROM 2 +#define MTD_NORFLASH 3 +#define MTD_NANDFLASH 4 +#define MTD_PEROM 5 +#define MTD_OTHER 14 +#define MTD_UNKNOWN 15 + +#define MTD_CLEAR_BITS 1 /* Bits can be cleared (flash) */ +#define MTD_SET_BITS 2 /* Bits can be set */ +#define MTD_ERASEABLE 4 /* Has an erase function */ +#define MTD_WRITEB_WRITEABLE 8 /* Direct IO is possible */ +#define MTD_VOLATILE 16 /* Set for RAMs */ +#define MTD_XIP 32 /* eXecute-In-Place possible */ +#define MTD_OOB 64 /* Out-of-band data (NAND flash) */ +#define MTD_ECC 128 /* Device capable of automatic ECC */ +#define MTD_NO_VIRTBLOCKS 256 /* Virtual blocks not allowed */ + +/* Some common devices / combinations of capabilities */ +#define MTD_CAP_ROM 0 +#define MTD_CAP_RAM (MTD_CLEAR_BITS|MTD_SET_BITS|MTD_WRITEB_WRITEABLE) +#define MTD_CAP_NORFLASH (MTD_CLEAR_BITS|MTD_ERASEABLE) +#define MTD_CAP_NANDFLASH (MTD_CLEAR_BITS|MTD_ERASEABLE|MTD_OOB) +#define MTD_WRITEABLE (MTD_CLEAR_BITS|MTD_SET_BITS) + + +/* Types of automatic ECC/Checksum available */ +#define MTD_ECC_NONE 0 /* No automatic ECC available */ +#define MTD_ECC_RS_DiskOnChip 1 /* Automatic ECC on DiskOnChip */ +#define MTD_ECC_SW 2 /* SW ECC for Toshiba & Samsung devices */ + +/* ECC byte placement */ +#define MTD_NANDECC_OFF 0 /* Switch off ECC (Not recommended) */ +#define MTD_NANDECC_PLACE 1 /* Use the given placement in the structure (YAFFS1 legacy mode) */ +#define MTD_NANDECC_AUTOPLACE 2 /* Use the default placement scheme */ +#define MTD_NANDECC_PLACEONLY 3 /* Use the given placement in the structure (Do not store ecc result on read) */ +#define MTD_NANDECC_AUTOPL_USR 4 /* Use the given autoplacement scheme rather than using the default */ + +struct mtd_info_user { + uint8_t type; + uint32_t flags; + uint32_t size; /* Total size of the MTD */ + uint32_t erasesize; + uint32_t oobblock; /* Size of OOB blocks (e.g. 512) */ + uint32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ + uint32_t ecctype; + uint32_t eccsize; +}; + +struct region_info_user { + uint32_t offset; /* At which this region starts, + * from the beginning of the MTD */ + uint32_t erasesize; /* For this region */ + uint32_t numblocks; /* Number of blocks in this region */ + uint32_t regionindex; +}; + +#define MEMGETINFO _IOR('M', 1, struct mtd_info_user) +#define MEMERASE _IOW('M', 2, struct erase_info_user) +#define MEMWRITEOOB _IOWR('M', 3, struct mtd_oob_buf) +#define MEMREADOOB _IOWR('M', 4, struct mtd_oob_buf) +#define MEMLOCK _IOW('M', 5, struct erase_info_user) +#define MEMUNLOCK _IOW('M', 6, struct erase_info_user) +#define MEMGETREGIONCOUNT _IOR('M', 7, int) +#define MEMGETREGIONINFO _IOWR('M', 8, struct region_info_user) +#define MEMSETOOBSEL _IOW('M', 9, struct nand_oobinfo) +#define MEMGETOOBSEL _IOR('M', 10, struct nand_oobinfo) +#define MEMGETBADBLOCK _IOW('M', 11, loff_t) +#define MEMSETBADBLOCK _IOW('M', 12, loff_t) + +struct nand_oobinfo { + uint32_t useecc; + uint32_t eccbytes; + uint32_t oobfree[8][2]; + uint32_t eccpos[80]; /* RS 218 ECC */ +}; + +#endif /* __MTD_ABI_H__ */ diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h new file mode 100644 index 0000000..13e9080 --- /dev/null +++ b/include/linux/mtd/mtd.h @@ -0,0 +1,214 @@ +/* + * $Id: mtd.h,v 1.56 2004/08/09 18:46:04 dmarlin Exp $ + * + * Copyright (C) 1999-2003 David Woodhouse et al. + * + * Released under GPL + */ + +#ifndef __MTD_MTD_H__ +#define __MTD_MTD_H__ +#include +#include + +#define MAX_MTD_DEVICES 16 + +#define MTD_ERASE_PENDING 0x01 +#define MTD_ERASING 0x02 +#define MTD_ERASE_SUSPEND 0x04 +#define MTD_ERASE_DONE 0x08 +#define MTD_ERASE_FAILED 0x10 + +/* If the erase fails, fail_addr might indicate exactly which block failed. If + fail_addr = 0xffffffff, the failure was not at the device level or was not + specific to any particular block. */ +struct erase_info { + struct mtd_info *mtd; + u_int32_t addr; + u_int32_t len; + u_int32_t fail_addr; + u_long time; + u_long retries; + u_int dev; + u_int cell; + void (*callback) (struct erase_info *self); + u_long priv; + u_char state; + struct erase_info *next; +}; + +struct mtd_erase_region_info { + u_int32_t offset; /* At which this region starts, from the beginning of the MTD */ + u_int32_t erasesize; /* For this region */ + u_int32_t numblocks; /* Number of blocks of erasesize in this region */ +}; + +struct mtd_info { + u_char type; + u_int32_t flags; + u_int32_t size; /* Total size of the MTD */ + + /* "Major" erase size for the device. Naïve users may take this + * to be the only erase size available, or may use the more detailed + * information below if they desire + */ + u_int32_t erasesize; + + u_int32_t oobblock; /* Size of OOB blocks (e.g. 512) */ + u_int32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ + u_int32_t oobavail; /* Number of bytes in OOB area available for fs */ + u_int32_t ecctype; + u_int32_t eccsize; + + + /* Kernel-only stuff starts here. */ + char *name; + int index; + + /* oobinfo is a nand_oobinfo structure, which can be set by iotcl (MEMSETOOBINFO) */ + struct nand_oobinfo oobinfo; + + /* Data for variable erase regions. If numeraseregions is zero, + * it means that the whole device has erasesize as given above. + */ + int numeraseregions; + struct mtd_erase_region_info *eraseregions; + + /* This really shouldn't be here. It can go away in 2.5 */ + u_int32_t bank_size; + + int (*erase) (struct mtd_info *mtd, struct erase_info *instr); + + /* This stuff for eXecute-In-Place */ + int (*point) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char **mtdbuf); + + /* We probably shouldn't allow XIP if the unpoint isn't a NULL */ + void (*unpoint) (struct mtd_info *mtd, u_char * addr, loff_t from, size_t len); + + + int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + + int (*read_ecc) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel); + int (*write_ecc) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel); + + int (*read_oob) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + int (*write_oob) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + + /* + * Methods to access the protection register area, present in some + * flash devices. The user data is one time programmable but the + * factory data is read only. + */ + int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + + int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + + /* This function is not yet implemented */ + int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); +#if 0 + /* kvec-based read/write methods. We need these especially for NAND flash, + with its limited number of write cycles per erase. + NB: The 'count' parameter is the number of _vectors_, each of + which contains an (ofs, len) tuple. + */ + int (*readv) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, size_t *retlen); + int (*readv_ecc) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, + size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); + int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen); + int (*writev_ecc) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, + size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); +#endif + /* Sync */ + void (*sync) (struct mtd_info *mtd); +#if 0 + /* Chip-supported device locking */ + int (*lock) (struct mtd_info *mtd, loff_t ofs, size_t len); + int (*unlock) (struct mtd_info *mtd, loff_t ofs, size_t len); + + /* Power Management functions */ + int (*suspend) (struct mtd_info *mtd); + void (*resume) (struct mtd_info *mtd); +#endif + /* Bad block management functions */ + int (*block_isbad) (struct mtd_info *mtd, loff_t ofs); + int (*block_markbad) (struct mtd_info *mtd, loff_t ofs); + + void *priv; + + struct module *owner; + int usecount; +}; + + + /* Kernel-side ioctl definitions */ + +extern int add_mtd_device(struct mtd_info *mtd); +extern int del_mtd_device (struct mtd_info *mtd); + +extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num); + +extern void put_mtd_device(struct mtd_info *mtd); + +#if 0 +struct mtd_notifier { + void (*add)(struct mtd_info *mtd); + void (*remove)(struct mtd_info *mtd); + struct list_head list; +}; + + +extern void register_mtd_user (struct mtd_notifier *new); +extern int unregister_mtd_user (struct mtd_notifier *old); + +int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t *retlen); + +int default_mtd_readv(struct mtd_info *mtd, struct kvec *vecs, + unsigned long count, loff_t from, size_t *retlen); +#endif + +#define MTD_ERASE(mtd, args...) (*(mtd->erase))(mtd, args) +#define MTD_POINT(mtd, a,b,c,d) (*(mtd->point))(mtd, a,b,c, (u_char **)(d)) +#define MTD_UNPOINT(mtd, arg) (*(mtd->unpoint))(mtd, (u_char *)arg) +#define MTD_READ(mtd, args...) (*(mtd->read))(mtd, args) +#define MTD_WRITE(mtd, args...) (*(mtd->write))(mtd, args) +#define MTD_READV(mtd, args...) (*(mtd->readv))(mtd, args) +#define MTD_WRITEV(mtd, args...) (*(mtd->writev))(mtd, args) +#define MTD_READECC(mtd, args...) (*(mtd->read_ecc))(mtd, args) +#define MTD_WRITEECC(mtd, args...) (*(mtd->write_ecc))(mtd, args) +#define MTD_READOOB(mtd, args...) (*(mtd->read_oob))(mtd, args) +#define MTD_WRITEOOB(mtd, args...) (*(mtd->write_oob))(mtd, args) +#define MTD_SYNC(mtd) do { if (mtd->sync) (*(mtd->sync))(mtd); } while (0) + + +#ifdef CONFIG_MTD_PARTITIONS +void mtd_erase_callback(struct erase_info *instr); +#else +static inline void mtd_erase_callback(struct erase_info *instr) +{ + if (instr->callback) + instr->callback(instr); +} +#endif + +/* + * Debugging macro and defines + */ +#define MTD_DEBUG_LEVEL0 (0) /* Quiet */ +#define MTD_DEBUG_LEVEL1 (1) /* Audible */ +#define MTD_DEBUG_LEVEL2 (2) /* Loud */ +#define MTD_DEBUG_LEVEL3 (3) /* Noisy */ + +#ifdef CONFIG_MTD_DEBUG +#define DEBUG(n, args...) \ + do { \ + if (n <= CONFIG_MTD_DEBUG_VERBOSE) \ + printk(KERN_INFO args); \ + } while(0) +#else /* CONFIG_MTD_DEBUG */ +#define DEBUG(n, args...) do { } while(0) + +#endif /* CONFIG_MTD_DEBUG */ + +#endif /* __MTD_MTD_H__ */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 5236904..d22ea25 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -2,10 +2,10 @@ * linux/include/linux/mtd/nand.h * * Copyright (c) 2000 David Woodhouse - * Steven J. Hill - * Thomas Gleixner + * Steven J. Hill + * Thomas Gleixner * - * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $ + * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,15 +15,15 @@ * Contains standard defines and IDs for NAND flash devices * * Changelog: - * 01-31-2000 DMW Created - * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers + * 01-31-2000 DMW Created + * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers * so it can be used by other NAND flash device * drivers. I also changed the copyright since none * of the original contents of this file are specific * to DoC devices. David can whack me with a baseball * bat later if I did something naughty. - * 10-11-2000 SJH Added private NAND flash structure for driver - * 10-24-2000 SJH Added prototype for 'nand_scan' function + * 10-11-2000 SJH Added private NAND flash structure for driver + * 10-24-2000 SJH Added prototype for 'nand_scan' function * 10-29-2001 TG changed nand_chip structure to support * hardwarespecific function for accessing control lines * 02-21-2002 TG added support for different read/write adress and @@ -32,10 +32,67 @@ * command delay times for different chips * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate * defines in jffs2/wbuf.c + * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if + * CONFIG_MTD_NAND_ECC_JFFS2 is not set + * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC + * + * 08-29-2002 tglx nand_chip structure: data_poi for selecting + * internal / fs-driver buffer + * support for 6byte/512byte hardware ECC + * read_ecc, write_ecc extended for different oob-layout + * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB, + * NAND_YAFFS_OOB + * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL + * Split manufacturer and device ID structures + * + * 02-08-2004 tglx added option field to nand structure for chip anomalities + * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id + * update of nand_chip structure description */ #ifndef __LINUX_MTD_NAND_H #define __LINUX_MTD_NAND_H +#include +#include + +struct mtd_info; +/* Scan and identify a NAND device */ +extern int nand_scan (struct mtd_info *mtd, int max_chips); +/* Free resources held by the NAND device */ +extern void nand_release (struct mtd_info *mtd); + +/* Read raw data from the device without ECC */ +extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen); + + +/* This constant declares the max. oobsize / page, which + * is supported now. If you add a chip with bigger oobsize/page + * adjust this accordingly. + */ + +#define NAND_MAX_OOBSIZE 218 +#define NAND_MAX_PAGESIZE 4096 + +/* + * Constants for hardware specific CLE/ALE/NCE function +*/ +/* Select the chip by setting nCE to low */ +#define NAND_CTL_SETNCE 1 +/* Deselect the chip by setting nCE to high */ +#define NAND_CTL_CLRNCE 2 +/* Select the command latch by setting CLE to high */ +#define NAND_CTL_SETCLE 3 +/* Deselect the command latch by setting CLE to low */ +#define NAND_CTL_CLRCLE 4 +/* Select the address latch by setting ALE to high */ +#define NAND_CTL_SETALE 5 +/* Deselect the address latch by setting ALE to low */ +#define NAND_CTL_CLRALE 6 +/* Set write protection by setting WP to high. Not used! */ +#define NAND_CTL_SETWP 7 +/* Clear write protection by setting WP to low. Not used! */ +#define NAND_CTL_CLRWP 8 + /* * Standard NAND flash commands */ @@ -45,12 +102,104 @@ #define NAND_CMD_READOOB 0x50 #define NAND_CMD_ERASE1 0x60 #define NAND_CMD_STATUS 0x70 +#define NAND_CMD_STATUS_MULTI 0x71 #define NAND_CMD_SEQIN 0x80 #define NAND_CMD_READID 0x90 #define NAND_CMD_ERASE2 0xd0 #define NAND_CMD_RESET 0xff +/* Extended commands for large page devices */ +#define NAND_CMD_READSTART 0x30 +#define NAND_CMD_CACHEDPROG 0x15 + +/* Status bits */ +#define NAND_STATUS_FAIL 0x01 +#define NAND_STATUS_FAIL_N1 0x02 +#define NAND_STATUS_TRUE_READY 0x20 +#define NAND_STATUS_READY 0x40 +#define NAND_STATUS_WP 0x80 + /* + * Constants for ECC_MODES + */ + +/* No ECC. Usage is not recommended ! */ +#define NAND_ECC_NONE 0 +/* Software ECC 3 byte ECC per 256 Byte data */ +#define NAND_ECC_SOFT 1 +/* Hardware ECC 3 byte ECC per 256 Byte data */ +#define NAND_ECC_HW3_256 2 +/* Hardware ECC 3 byte ECC per 512 Byte data */ +#define NAND_ECC_HW3_512 3 +/* Hardware ECC 3 byte ECC per 512 Byte data */ +#define NAND_ECC_HW6_512 4 +/* Hardware ECC 8 byte ECC per 512 Byte data */ +#define NAND_ECC_HW8_512 6 +/* Hardware ECC 12 byte ECC per 2048 Byte data */ +#define NAND_ECC_HW12_2048 7 + +/* + * Constants for Hardware ECC +*/ +/* Reset Hardware ECC for read */ +#define NAND_ECC_READ 0 +/* Reset Hardware ECC for write */ +#define NAND_ECC_WRITE 1 +/* Enable Hardware ECC before syndrom is read back from flash */ +#define NAND_ECC_READSYN 2 + +/* Option constants for bizarre disfunctionality and real +* features +*/ +/* Chip can not auto increment pages */ +#define NAND_NO_AUTOINCR 0x00000001 +/* Buswitdh is 16 bit */ +#define NAND_BUSWIDTH_16 0x00000002 +/* Device supports partial programming without padding */ +#define NAND_NO_PADDING 0x00000004 +/* Chip has cache program function */ +#define NAND_CACHEPRG 0x00000008 +/* Chip has copy back function */ +#define NAND_COPYBACK 0x00000010 +/* AND Chip which has 4 banks and a confusing page / block + * assignment. See Renesas datasheet for further information */ +#define NAND_IS_AND 0x00000020 +/* Chip has a array of 4 pages which can be read without + * additional ready /busy waits */ +#define NAND_4PAGE_ARRAY 0x00000040 + +/* Options valid for Samsung large page devices */ +#define NAND_SAMSUNG_LP_OPTIONS \ + (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) + +/* Macros to identify the above */ +#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) +#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) +#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) +#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) + +/* Mask to zero out the chip options, which come from the id table */ +#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) + +/* Non chip related options */ +/* Use a flash based bad block table. This option is passed to the + * default bad block table function. */ +#define NAND_USE_FLASH_BBT 0x00010000 +/* The hw ecc generator provides a syndrome instead a ecc value on read + * This can only work if we have the ecc bytes directly behind the + * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ +#define NAND_HWECC_SYNDROME 0x00020000 + + +/* Options set by nand scan */ +/* Nand scan has allocated oob_buf */ +#define NAND_OOBBUF_ALLOC 0x40000000 +/* Nand scan has allocated data_buf */ +#define NAND_DATABUF_ALLOC 0x80000000 + + +/* + * nand_state_t - chip states * Enumeration for NAND flash chip state */ typedef enum { @@ -58,71 +207,138 @@ typedef enum { FL_READING, FL_WRITING, FL_ERASING, - FL_SYNCING + FL_SYNCING, + FL_CACHEDPRG, } nand_state_t; +/* Keep gcc happy */ +struct nand_chip; -/* - * NAND Private Flash Chip Data - * - * Structure overview: - * - * IO_ADDR - address to access the 8 I/O lines of the flash device - * - * hwcontrol - hardwarespecific function for accesing control-lines - * - * dev_ready - hardwarespecific function for accesing device ready/busy line - * - * chip_lock - spinlock used to protect access to this structure - * - * wq - wait queue to sleep on if a NAND operation is in progress - * - * state - give the current state of the NAND device - * - * page_shift - number of address bits in a page (column address bits) - * - * data_buf - data buffer passed to/from MTD user modules - * - * data_cache - data cache for redundant page access and shadow for - * ECC failure - * - * ecc_code_buf - used only for holding calculated or read ECCs for - * a page read or written when ECC is in use - * - * reserved - padding to make structure fall on word boundary if - * when ECC is in use +#if 0 +/** + * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices + * @lock: protection lock + * @active: the mtd device which holds the controller currently */ -struct Nand { - char floor, chip; - unsigned long curadr; - unsigned char curmode; - /* Also some erase/write/pipeline info when we get that far */ +struct nand_hw_control { + spinlock_t lock; + struct nand_chip *active; }; +#endif + +/** + * struct nand_chip - NAND Private Flash Chip Data + * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device + * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device + * @read_byte: [REPLACEABLE] read one byte from the chip + * @write_byte: [REPLACEABLE] write one byte to the chip + * @read_word: [REPLACEABLE] read one word from the chip + * @write_word: [REPLACEABLE] write one word to the chip + * @write_buf: [REPLACEABLE] write data from the buffer to the chip + * @read_buf: [REPLACEABLE] read data from the chip into the buffer + * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data + * @select_chip: [REPLACEABLE] select chip nr + * @block_bad: [REPLACEABLE] check, if the block is bad + * @block_markbad: [REPLACEABLE] mark the block bad + * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines + * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line + * If set to NULL no access to ready/busy is available and the ready/busy information + * is read from the chip status register + * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip + * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready + * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware + * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw) + * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only + * be provided if a hardware ECC is available + * @erase_cmd: [INTERN] erase command write function, selectable due to AND support + * @scan_bbt: [REPLACEABLE] function to scan bad block table + * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines + * @eccsize: [INTERN] databytes used per ecc-calculation + * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step + * @eccsteps: [INTERN] number of ecc calculation steps per page + * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) + * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip + * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress + * @state: [INTERN] the current state of the NAND device + * @page_shift: [INTERN] number of address bits in a page (column address bits) + * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock + * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry + * @chip_shift: [INTERN] number of address bits in one chip + * @data_buf: [INTERN] internal buffer for one page + oob + * @oob_buf: [INTERN] oob buffer for one eraseblock + * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized + * @data_poi: [INTERN] pointer to a data buffer + * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about + * special functionality. See the defines for further explanation + * @badblockpos: [INTERN] position of the bad block marker in the oob area + * @numchips: [INTERN] number of physical chips + * @chipsize: [INTERN] the size of one chip for multichip arrays + * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 + * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf + * @autooob: [REPLACEABLE] the default (auto)placement scheme + * @bbt: [INTERN] bad block table pointer + * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup + * @bbt_md: [REPLACEABLE] bad block table mirror descriptor + * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan + * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices + * @priv: [OPTIONAL] pointer to private chip date + */ struct nand_chip { - int page_shift; - u_char *data_buf; - u_char *data_cache; - int cache_page; - u_char ecc_code_buf[6]; - u_char reserved[2]; - char ChipID; /* Type of DiskOnChip */ - struct Nand *chips; - int chipshift; - char* chips_name; - unsigned long erasesize; - unsigned long mfr; /* Flash IDs - only one type of flash per device */ - unsigned long id; - char* name; - int numchips; - char page256; - char pageadrlen; - unsigned long IO_ADDR; /* address to access the 8 I/O lines to the flash device */ - unsigned long totlen; - uint oobblock; /* Size of OOB blocks (e.g. 512) */ - uint oobsize; /* Amount of OOB data per block (e.g. 16) */ - uint eccsize; - int bus16; + void __iomem *IO_ADDR_R; + void __iomem *IO_ADDR_W; + + u_char (*read_byte)(struct mtd_info *mtd); + void (*write_byte)(struct mtd_info *mtd, u_char byte); + u16 (*read_word)(struct mtd_info *mtd); + void (*write_word)(struct mtd_info *mtd, u16 word); + + void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len); + void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len); + int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len); + void (*select_chip)(struct mtd_info *mtd, int chip); + int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); + int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); + void (*hwcontrol)(struct mtd_info *mtd, int cmd); + int (*dev_ready)(struct mtd_info *mtd); + void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); + int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state); + int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code); + int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); + void (*enable_hwecc)(struct mtd_info *mtd, int mode); + void (*erase_cmd)(struct mtd_info *mtd, int page); + int (*scan_bbt)(struct mtd_info *mtd); + int eccmode; + int eccsize; + int eccbytes; + int eccsteps; + int chip_delay; +#if 0 + spinlock_t chip_lock; + wait_queue_head_t wq; + nand_state_t state; +#endif + int page_shift; + int phys_erase_shift; + int bbt_erase_shift; + int chip_shift; + u_char *data_buf; + u_char *oob_buf; + int oobdirty; + u_char *data_poi; + unsigned int options; + int badblockpos; + int numchips; + unsigned long chipsize; + int pagemask; + int pagebuf; + struct nand_oobinfo *autooob; + uint8_t *bbt; + struct nand_bbt_descr *bbt_td; + struct nand_bbt_descr *bbt_md; + struct nand_bbt_descr *badblock_pattern; + struct nand_hw_control *controller; + void *priv; }; /* @@ -130,71 +346,128 @@ struct nand_chip { */ #define NAND_MFR_TOSHIBA 0x98 #define NAND_MFR_SAMSUNG 0xec +#define NAND_MFR_FUJITSU 0x04 +#define NAND_MFR_NATIONAL 0x8f +#define NAND_MFR_RENESAS 0x07 +#define NAND_MFR_STMICRO 0x20 +#define NAND_MFR_HYNIX 0xad +#define NAND_MFR_MICRON 0x2c +#define NAND_MFR_AMD 0x01 -/* - * NAND Flash Device ID Structure +/** + * struct nand_flash_dev - NAND Flash Device ID Structure * - * Structure overview: - * - * name - Complete name of device - * - * manufacture_id - manufacturer ID code of device. - * - * model_id - model ID code of device. - * - * chipshift - total number of address bits for the device which - * is used to calculate address offsets and the total - * number of bytes the device is capable of. - * - * page256 - denotes if flash device has 256 byte pages or not. - * - * pageadrlen - number of bytes minus one needed to hold the - * complete address into the flash array. Keep in - * mind that when a read or write is done to a - * specific address, the address is input serially - * 8 bits at a time. This structure member is used - * by the read/write routines as a loop index for - * shifting the address out 8 bits at a time. - * - * erasesize - size of an erase block in the flash device. + * @name: Identify the device type + * @id: device ID code + * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 + * If the pagesize is 0, then the real pagesize + * and the eraseize are determined from the + * extended id bytes in the chip + * @erasesize: Size of an erase block in the flash device. + * @chipsize: Total chipsize in Mega Bytes + * @options: Bitfield to store chip relevant options */ struct nand_flash_dev { - char * name; - int manufacture_id; - int model_id; - int chipshift; - char page256; - char pageadrlen; + char *name; + int id; + unsigned long pagesize; + unsigned long chipsize; unsigned long erasesize; - int bus16; + unsigned long options; }; +/** + * struct nand_manufacturers - NAND Flash Manufacturer ID Structure + * @name: Manufacturer name + * @id: manufacturer ID code of device. +*/ +struct nand_manufacturers { + int id; + char * name; +}; + +extern struct nand_flash_dev nand_flash_ids[]; +extern struct nand_manufacturers nand_manuf_ids[]; + +/** + * struct nand_bbt_descr - bad block table descriptor + * @options: options for this descriptor + * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE + * when bbt is searched, then we store the found bbts pages here. + * Its an array and supports up to 8 chips now + * @offs: offset of the pattern in the oob area of the page + * @veroffs: offset of the bbt version counter in the oob are of the page + * @version: version read from the bbt page during scan + * @len: length of the pattern, if 0 no pattern check is performed + * @maxblocks: maximum number of blocks to search for a bbt. This number of + * blocks is reserved at the end of the device where the tables are + * written. + * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than + * bad) block in the stored bbt + * @pattern: pattern to identify bad block table or factory marked good / + * bad blocks, can be NULL, if len = 0 + * + * Descriptor for the bad block table marker and the descriptor for the + * pattern which identifies good and bad blocks. The assumption is made + * that the pattern and the version count are always located in the oob area + * of the first block. + */ +struct nand_bbt_descr { + int options; + int pages[NAND_MAX_CHIPS]; + int offs; + int veroffs; + uint8_t version[NAND_MAX_CHIPS]; + int len; + int maxblocks; + int reserved_block_code; + uint8_t *pattern; +}; + +/* Options for the bad block table descriptors */ + +/* The number of bits used per block in the bbt on the device */ +#define NAND_BBT_NRBITS_MSK 0x0000000F +#define NAND_BBT_1BIT 0x00000001 +#define NAND_BBT_2BIT 0x00000002 +#define NAND_BBT_4BIT 0x00000004 +#define NAND_BBT_8BIT 0x00000008 +/* The bad block table is in the last good block of the device */ +#define NAND_BBT_LASTBLOCK 0x00000010 +/* The bbt is at the given page, else we must scan for the bbt */ +#define NAND_BBT_ABSPAGE 0x00000020 +/* The bbt is at the given page, else we must scan for the bbt */ +#define NAND_BBT_SEARCH 0x00000040 +/* bbt is stored per chip on multichip devices */ +#define NAND_BBT_PERCHIP 0x00000080 +/* bbt has a version counter at offset veroffs */ +#define NAND_BBT_VERSION 0x00000100 +/* Create a bbt if none axists */ +#define NAND_BBT_CREATE 0x00000200 +/* Search good / bad pattern through all pages of a block */ +#define NAND_BBT_SCANALLPAGES 0x00000400 +/* Scan block empty during good / bad block scan */ +#define NAND_BBT_SCANEMPTY 0x00000800 +/* Write bbt if neccecary */ +#define NAND_BBT_WRITE 0x00001000 +/* Read and write back block contents when writing bbt */ +#define NAND_BBT_SAVECONTENT 0x00002000 +/* Search good / bad pattern on the first and the second page */ +#define NAND_BBT_SCAN2NDPAGE 0x00004000 + +/* The maximum number of blocks to scan for a bbt */ +#define NAND_BBT_SCAN_MAXBLOCKS 4 + +extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd); +extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs); +extern int nand_default_bbt (struct mtd_info *mtd); +extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt); +extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt); + /* * Constants for oob configuration */ -#define NAND_NOOB_ECCPOS0 0 -#define NAND_NOOB_ECCPOS1 1 -#define NAND_NOOB_ECCPOS2 2 -#define NAND_NOOB_ECCPOS3 3 -#define NAND_NOOB_ECCPOS4 6 -#define NAND_NOOB_ECCPOS5 7 -#define NAND_NOOB_BADBPOS -1 -#define NAND_NOOB_ECCVPOS -1 - -#define NAND_JFFS2_OOB_ECCPOS0 0 -#define NAND_JFFS2_OOB_ECCPOS1 1 -#define NAND_JFFS2_OOB_ECCPOS2 2 -#define NAND_JFFS2_OOB_ECCPOS3 3 -#define NAND_JFFS2_OOB_ECCPOS4 6 -#define NAND_JFFS2_OOB_ECCPOS5 7 -#define NAND_JFFS2_OOB_BADBPOS 5 -#define NAND_JFFS2_OOB_ECCVPOS 4 - -#define NAND_JFFS2_OOB8_FSDAPOS 6 -#define NAND_JFFS2_OOB16_FSDAPOS 8 -#define NAND_JFFS2_OOB8_FSDALEN 2 -#define NAND_JFFS2_OOB16_FSDALEN 8 - -unsigned long nand_probe(unsigned long physadr); +#define NAND_SMALL_BADBLOCK_POS 5 +#define NAND_LARGE_BADBLOCK_POS 0 #endif /* __LINUX_MTD_NAND_H */ diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h new file mode 100644 index 0000000..12c5bc3 --- /dev/null +++ b/include/linux/mtd/nand_ecc.h @@ -0,0 +1,30 @@ +/* + * drivers/mtd/nand_ecc.h + * + * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) + * + * $Id: nand_ecc.h,v 1.4 2004/06/17 02:35:02 dbrown Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This file is the header for the ECC algorithm. + */ + +#ifndef __MTD_NAND_ECC_H__ +#define __MTD_NAND_ECC_H__ + +struct mtd_info; + +/* + * Calculate 3 byte ECC code for 256 byte block + */ +int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code); + +/* + * Detect and correct a 1 bit error for 256 byte block + */ +int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); + +#endif /* __MTD_NAND_ECC_H__ */ diff --git a/include/linux/mtd/nand_ecc_rs.h b/include/linux/mtd/nand_ecc_rs.h new file mode 100644 index 0000000..20e7094 --- /dev/null +++ b/include/linux/mtd/nand_ecc_rs.h @@ -0,0 +1,79 @@ +/******************************************************************************* + + + Filename: new_rs.h + Description: Global definitions for Reed-Solomon encoder/decoder + + + Author: STMicroelectronics + + + + You have a license to reproduce, display, perform, produce derivative works of, + and distribute (in original or modified form) the Program, provided that you + explicitly agree to the following disclaimer: + + THIS PROGRAM IS PROVIDED "AS IT IS" WITHOUT WARRANTY OF ANY KIND, EITHER + EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTY + OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE + PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, + REPAIR OR CORRECTION. + +********************************************************************************/ + +#ifndef __MTD_NAND_ECC_RS_H__ +#define __MTD_NAND_ECC_RS_H__ +#include + +//typedef unsigned int dtype; +typedef u_short dtype; + + +/* Initialization function */ +void init_rs(void); + +/* These two functions *must* be called in this order (e.g., + * by init_rs()) before any encoding/decoding + */ + +void generate_gf(void); /* Generate Galois Field */ +void gen_poly(void); /* Generate generator polynomial */ + +/* Reed-Solomon encoding + * data[] is the input block, parity symbols are placed in bb[] + * bb[] may lie past the end of the data, e.g., for (255,223): + * encode_rs(&data[0],&data[223]); + */ +char encode_rs(dtype data[], dtype bb[]); + + +/* Reed-Solomon errors decoding + * The received block goes into data[] + * + * The decoder corrects the symbols in place, if possible and returns + * the number of corrected symbols. If the codeword is illegal or + * uncorrectible, the data array is unchanged and -1 is returned + */ +int decode_rs(dtype data[]); + +/** + * nand_calculate_ecc - [NAND Interface] Calculate 3 byte ECC code for 256 byte block + * @mtd: MTD block structure + * @dat: raw data + * @ecc_code: buffer for ECC + */ +int nand_calculate_ecc_rs(struct mtd_info *mtd, const u_char *data, u_char *ecc_code); + +/** + * nand_correct_data - [NAND Interface] Detect and correct bit error(s) + * @mtd: MTD block structure + * @dat: raw data read from the chip + * @store_ecc: ECC from the chip + * @calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256 byte block + */ +int nand_correct_data_rs(struct mtd_info *mtd, u_char *data, u_char *store_ecc, u_char *calc_ecc); + +#endif diff --git a/include/linux/mtd/nand_ids.h b/include/linux/mtd/nand_ids.h index a3d0363..d9eb911 100644 --- a/include/linux/mtd/nand_ids.h +++ b/include/linux/mtd/nand_ids.h @@ -28,6 +28,10 @@ #ifndef __LINUX_MTD_NAND_IDS_H #define __LINUX_MTD_NAND_IDS_H +#ifndef CFG_NAND_LEGACY +#error This module is for the legacy NAND support +#endif + static struct nand_flash_dev nand_flash_ids[] = { {"Toshiba TC5816BDC", NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000, 0}, {"Toshiba TC5832DC", NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000, 0}, @@ -49,6 +53,7 @@ static struct nand_flash_dev nand_flash_ids[] = { {"Samsung KM29W16000", NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000, 0}, {"Samsung K9F5616Q0C", NAND_MFR_SAMSUNG, 0x45, 25, 0, 2, 0x4000, 1}, {"Samsung K9K1216Q0C", NAND_MFR_SAMSUNG, 0x46, 26, 0, 3, 0x4000, 1}, + {"Samsung K9F1G08U0M", NAND_MFR_SAMSUNG, 0xf1, 27, 0, 2, 0, 0}, {NULL,} }; diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h new file mode 100644 index 0000000..a8769e7 --- /dev/null +++ b/include/linux/mtd/nand_legacy.h @@ -0,0 +1,203 @@ +/* + * linux/include/linux/mtd/nand.h + * + * Copyright (c) 2000 David Woodhouse + * Steven J. Hill + * Thomas Gleixner + * + * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Info: + * Contains standard defines and IDs for NAND flash devices + * + * Changelog: + * 01-31-2000 DMW Created + * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers + * so it can be used by other NAND flash device + * drivers. I also changed the copyright since none + * of the original contents of this file are specific + * to DoC devices. David can whack me with a baseball + * bat later if I did something naughty. + * 10-11-2000 SJH Added private NAND flash structure for driver + * 10-24-2000 SJH Added prototype for 'nand_scan' function + * 10-29-2001 TG changed nand_chip structure to support + * hardwarespecific function for accessing control lines + * 02-21-2002 TG added support for different read/write adress and + * ready/busy line access function + * 02-26-2002 TG added chip_delay to nand_chip structure to optimize + * command delay times for different chips + * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate + * defines in jffs2/wbuf.c + */ +#ifndef __LINUX_MTD_NAND_LEGACY_H +#define __LINUX_MTD_NAND_LEGACY_H + +#ifndef CFG_NAND_LEGACY +#error This module is for the legacy NAND support +#endif + +/* + * Standard NAND flash commands + */ +#define NAND_CMD_READ0 0 +#define NAND_CMD_READ1 1 +#define NAND_CMD_PAGEPROG 0x10 +#define NAND_CMD_READOOB 0x50 +#define NAND_CMD_ERASE1 0x60 +#define NAND_CMD_STATUS 0x70 +#define NAND_CMD_SEQIN 0x80 +#define NAND_CMD_READID 0x90 +#define NAND_CMD_ERASE2 0xd0 +#define NAND_CMD_RESET 0xff + +/* + * Enumeration for NAND flash chip state + */ +typedef enum { + FL_READY, + FL_READING, + FL_WRITING, + FL_ERASING, + FL_SYNCING +} nand_state_t; + + +/* + * NAND Private Flash Chip Data + * + * Structure overview: + * + * IO_ADDR - address to access the 8 I/O lines of the flash device + * + * hwcontrol - hardwarespecific function for accesing control-lines + * + * dev_ready - hardwarespecific function for accesing device ready/busy line + * + * chip_lock - spinlock used to protect access to this structure + * + * wq - wait queue to sleep on if a NAND operation is in progress + * + * state - give the current state of the NAND device + * + * page_shift - number of address bits in a page (column address bits) + * + * data_buf - data buffer passed to/from MTD user modules + * + * data_cache - data cache for redundant page access and shadow for + * ECC failure + * + * ecc_code_buf - used only for holding calculated or read ECCs for + * a page read or written when ECC is in use + * + * reserved - padding to make structure fall on word boundary if + * when ECC is in use + */ +struct Nand { + char floor, chip; + unsigned long curadr; + unsigned char curmode; + /* Also some erase/write/pipeline info when we get that far */ +}; + +struct nand_chip { + int page_shift; + u_char *data_buf; + u_char *data_cache; + int cache_page; + u_char ecc_code_buf[6]; + u_char reserved[2]; + char ChipID; /* Type of DiskOnChip */ + struct Nand *chips; + int chipshift; + char* chips_name; + unsigned long erasesize; + unsigned long mfr; /* Flash IDs - only one type of flash per device */ + unsigned long id; + char* name; + int numchips; + char page256; + char pageadrlen; + unsigned long IO_ADDR; /* address to access the 8 I/O lines to the flash device */ + unsigned long totlen; + uint oobblock; /* Size of OOB blocks (e.g. 512) */ + uint oobsize; /* Amount of OOB data per block (e.g. 16) */ + uint eccsize; + int bus16; +}; + +/* + * NAND Flash Manufacturer ID Codes + */ +#define NAND_MFR_TOSHIBA 0x98 +#define NAND_MFR_SAMSUNG 0xec + +/* + * NAND Flash Device ID Structure + * + * Structure overview: + * + * name - Complete name of device + * + * manufacture_id - manufacturer ID code of device. + * + * model_id - model ID code of device. + * + * chipshift - total number of address bits for the device which + * is used to calculate address offsets and the total + * number of bytes the device is capable of. + * + * page256 - denotes if flash device has 256 byte pages or not. + * + * pageadrlen - number of bytes minus one needed to hold the + * complete address into the flash array. Keep in + * mind that when a read or write is done to a + * specific address, the address is input serially + * 8 bits at a time. This structure member is used + * by the read/write routines as a loop index for + * shifting the address out 8 bits at a time. + * + * erasesize - size of an erase block in the flash device. + */ +struct nand_flash_dev { + char * name; + int manufacture_id; + int model_id; + int chipshift; + char page256; + char pageadrlen; + unsigned long erasesize; + int bus16; +}; + +/* +* Constants for oob configuration +*/ +#define NAND_NOOB_ECCPOS0 0 +#define NAND_NOOB_ECCPOS1 1 +#define NAND_NOOB_ECCPOS2 2 +#define NAND_NOOB_ECCPOS3 3 +#define NAND_NOOB_ECCPOS4 6 +#define NAND_NOOB_ECCPOS5 7 +#define NAND_NOOB_BADBPOS -1 +#define NAND_NOOB_ECCVPOS -1 + +#define NAND_JFFS2_OOB_ECCPOS0 0 +#define NAND_JFFS2_OOB_ECCPOS1 1 +#define NAND_JFFS2_OOB_ECCPOS2 2 +#define NAND_JFFS2_OOB_ECCPOS3 3 +#define NAND_JFFS2_OOB_ECCPOS4 6 +#define NAND_JFFS2_OOB_ECCPOS5 7 +#define NAND_JFFS2_OOB_BADBPOS 5 +#define NAND_JFFS2_OOB_ECCVPOS 4 + +#define NAND_JFFS2_OOB8_FSDAPOS 6 +#define NAND_JFFS2_OOB16_FSDAPOS 8 +#define NAND_JFFS2_OOB8_FSDALEN 2 +#define NAND_JFFS2_OOB16_FSDALEN 8 + +unsigned long nand_probe(unsigned long physadr); +#endif /* __LINUX_MTD_NAND_LEGACY_H */ diff --git a/include/malloc.h b/include/malloc.h index 47154b0..97873cb 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -216,7 +216,8 @@ */ - +#ifndef _MALLOC_UBOOT_H_ +#define _MALLOC_UBOOT_H_ /* Preliminaries */ @@ -940,3 +941,5 @@ struct mallinfo mALLINFo(); #ifdef __cplusplus }; /* end of extern "C" */ #endif +#endif /* _MALLOC_UBOOT_H_ */ + diff --git a/include/mmc.h b/include/mmc.h index a271695..6605479 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -23,7 +23,7 @@ #ifndef _MMC_H_ #define _MMC_H_ -#include + int mmc_init(int verbose); int mmc_read(ulong src, uchar *dst, int size); diff --git a/include/nand.h b/include/nand.h new file mode 100644 index 0000000..23493f7 --- /dev/null +++ b/include/nand.h @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2005 + * 2N Telekomunikace, a.s. + * Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _NAND_H_ +#define _NAND_H_ + +#include +#include +#include + +typedef struct mtd_info nand_info_t; + +extern int nand_curr_device; +extern nand_info_t nand_info[]; + +static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf) +{ + return info->read(info, ofs, *len, (size_t *)len, buf); +} + +static inline int nand_write(nand_info_t *info, ulong ofs, ulong *len, u_char *buf) +{ + return info->write(info, ofs, *len, (size_t *)len, buf); +} + +static inline int nand_block_isbad(nand_info_t *info, ulong ofs) +{ + return info->block_isbad(info, ofs); +} + +static inline int nand_erase(nand_info_t *info, ulong off, ulong size) +{ + struct erase_info instr; + + instr.mtd = info; + instr.addr = off; + instr.len = size; + instr.callback = 0; + + return info->erase(info, &instr); +} + + +/***************************************************************************** + * declarations from nand_util.c + ****************************************************************************/ + +struct nand_write_options { + u_char *buffer; /* memory block containing image to write */ + ulong length; /* number of bytes to write */ + ulong offset; /* start address in NAND */ + int quiet; /* don't display progress messages */ + int autoplace; /* if true use auto oob layout */ + int forcejffs2; /* force jffs2 oob layout */ + int forceyaffs; /* force yaffs oob layout */ + int noecc; /* write without ecc */ + int writeoob; /* image contains oob data */ + int pad; /* pad to page size */ + int blockalign; /* 1|2|4 set multiple of eraseblocks + * to align to */ +}; + +typedef struct nand_write_options nand_write_options_t; + +struct nand_read_options { + u_char *buffer; /* memory block in which read image is written*/ + ulong length; /* number of bytes to read */ + ulong offset; /* start address in NAND */ + int quiet; /* don't display progress messages */ + int readoob; /* put oob data in image */ +}; + +typedef struct nand_read_options nand_read_options_t; + +struct nand_erase_options { + ulong length; /* number of bytes to erase */ + ulong offset; /* first address in NAND to erase */ + int quiet; /* don't display progress messages */ + int jffs2; /* if true: format for jffs2 usage + * (write appropriate cleanmarker blocks) */ + int scrub; /* if true, really clean NAND by erasing + * bad blocks (UNSAFE) */ +}; + +typedef struct nand_erase_options nand_erase_options_t; + +int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts); + +int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts); +int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); + +#define NAND_LOCK_STATUS_TIGHT 0x01 +#define NAND_LOCK_STATUS_LOCK 0x02 +#define NAND_LOCK_STATUS_UNLOCK 0x04 + +int nand_lock( nand_info_t *meminfo, int tight ); +int nand_unlock( nand_info_t *meminfo, ulong start, ulong length ); +int nand_get_lock_status(nand_info_t *meminfo, ulong offset); + +#ifdef CFG_NAND_SELECT_DEVICE +void board_nand_select_device(struct nand_chip *nand, int chip); +#endif + +#endif diff --git a/include/net.h b/include/net.h index 461e038..5822d4f 100644 --- a/include/net.h +++ b/include/net.h @@ -336,7 +336,7 @@ extern int NetState; /* Network loop state */ extern int NetRestartWrap; /* Tried all network devices */ #endif -typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP } proto_t; +typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP, RCVR } proto_t; /* from net/net.c */ extern char BootFile[128]; /* Boot File name */ diff --git a/include/part.h b/include/part.h index 318aa3c..d20df0b 100644 --- a/include/part.h +++ b/include/part.h @@ -40,9 +40,14 @@ typedef struct block_dev_desc { unsigned char vendor [40+1]; /* IDE model, SCSI Vendor */ unsigned char product[20+1]; /* IDE Serial no, SCSI product */ unsigned char revision[8+1]; /* firmware revision */ + //support 3TB HDD + //unsigned long (*block_read)(int dev, + // unsigned long start, + // lbaint_t blkcnt, + // unsigned long *buffer); unsigned long (*block_read)(int dev, - unsigned long start, - lbaint_t blkcnt, + lbaint_t start, + unsigned long blkcnt, unsigned long *buffer); }block_dev_desc_t; @@ -61,6 +66,7 @@ typedef struct block_dev_desc { #define PART_TYPE_DOS 0x02 #define PART_TYPE_ISO 0x03 #define PART_TYPE_AMIGA 0x04 +#define PART_TYPE_EFI 0x05 /* * Type string for U-Boot bootable partitions @@ -81,6 +87,7 @@ typedef struct disk_partition { ulong blksz; /* block size in bytes */ uchar name[32]; /* partition name */ uchar type[32]; /* string type description */ + uchar boot_ind; /* 0x1 - active */ } disk_partition_t; /* disk/part.c */ @@ -117,5 +124,11 @@ int get_partition_info_amiga (block_dev_desc_t * dev_desc, int part, disk_partit void print_part_amiga (block_dev_desc_t *dev_desc); int test_part_amiga (block_dev_desc_t *dev_desc); #endif +#ifdef CONFIG_EFI_PARTITION +/* disk/part_efi.c */ +int get_partition_info_efi (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +void print_part_efi (block_dev_desc_t *dev_desc); +int test_part_efi (block_dev_desc_t *dev_desc); +#endif #endif /* _PART_H */ diff --git a/include/usb.h b/include/usb.h index 39d7f23..4a68c7a 100644 --- a/include/usb.h +++ b/include/usb.h @@ -40,6 +40,7 @@ #define USB_MAX_HUB 16 #define USB_CNTL_TIMEOUT 100 /* 100ms timeout */ +#define USB_BULK_TIMEOUT 1000 /* String descriptor */ struct usb_string_descriptor { @@ -93,7 +94,7 @@ struct usb_endpoint_descriptor { unsigned char bInterval; unsigned char bRefresh; unsigned char bSynchAddress; - + unsigned char padding; } __attribute__ ((packed)); /* Interface descriptor */ struct usb_interface_descriptor { @@ -108,6 +109,7 @@ struct usb_interface_descriptor { unsigned char iInterface; unsigned char no_of_ep; + unsigned char num_altsetting; unsigned char act_altsetting; struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS]; } __attribute__ ((packed)); @@ -131,7 +133,7 @@ struct usb_config_descriptor { struct usb_device { int devnum; /* Device number on USB bus */ - int slow; /* Slow device? */ + int speed; /* full/low/high */ char mf[32]; /* manufacturer */ char prod[32]; /* product */ char serial[32]; /* serial number */ @@ -160,6 +162,7 @@ struct usb_device { unsigned long status; int act_len; /* transfered bytes */ int maxchild; /* Number of ports if hub */ + int portnr; struct usb_device *parent; struct usb_device *children[USB_MAXCHILDREN]; }; @@ -168,7 +171,10 @@ struct usb_device { * this is how the lowlevel part communicate with the outer world */ -#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined (CONFIG_USB_SL811HS) +#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) || \ + defined(CONFIG_USB_OHCI_NEW) || defined (CONFIG_USB_SL811HS) || \ + defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_R8A66597_HCD) + int usb_lowlevel_init(void); int usb_lowlevel_stop(void); int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len); @@ -176,6 +182,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len,struct devrequest *setup); int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval); +void usb_event_poll(void); /* Defines */ #define USB_UHCI_VEND_ID 0x8086 @@ -189,8 +196,8 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, #define USB_MAX_STOR_DEV 5 block_dev_desc_t *usb_stor_get_dev(int index); -int usb_stor_scan(int mode); -void usb_stor_info(void); +int usb_stor_scan(void); +int usb_stor_info(void); #endif @@ -229,16 +236,12 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); /* big endian -> little endian conversion */ /* some CPUs are already little endian e.g. the ARM920T */ -#ifdef LITTLEENDIAN -#define swap_16(x) ((unsigned short)(x)) -#define swap_32(x) ((unsigned long)(x)) -#else -#define swap_16(x) \ +#define __swap_16(x) \ ({ unsigned short x_ = (unsigned short)x; \ (unsigned short)( \ ((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8) ); \ }) -#define swap_32(x) \ +#define __swap_32(x) \ ({ unsigned long x_ = (unsigned long)x; \ (unsigned long)( \ ((x_ & 0x000000FFUL) << 24) | \ @@ -246,6 +249,16 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); ((x_ & 0x00FF0000UL) >> 8) | \ ((x_ & 0xFF000000UL) >> 24) ); \ }) +#if (!defined(__BE)) +#define LITTLEENDIAN +#endif + +#ifdef LITTLEENDIAN +# define swap_16(x) (x) +# define swap_32(x) (x) +#else +# define swap_16(x) __swap_16(x) +# define swap_32(x) __swap_32(x) #endif /* LITTLEENDIAN */ /* @@ -256,7 +269,7 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); * - endpoint number (4 bits) * - current Data0/1 state (1 bit) * - direction (1 bit) - * - speed (1 bit) + * - speed (2 bits) * - max packet size (2 bits: 8, 16, 32 or 64) * - pipe type (2 bits: control, interrupt, bulk, isochronous) * @@ -272,7 +285,7 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); * - device: bits 8-14 * - endpoint: bits 15-18 * - Data0/1: bit 19 - * - speed: bit 26 (0 = Full, 1 = Low Speed) + * - speed: bits 26-27 (0 = Full, 1 = Low, 2 = High) * - pipe type: bits 30-31 (00 = isochronous, 01 = interrupt, 10 = control, 11 = bulk) * * Why? Because it's arbitrary, and whatever encoding we select is really @@ -282,8 +295,8 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); */ /* Create various pipes... */ #define create_pipe(dev,endpoint) \ - (((dev)->devnum << 8) | (endpoint << 15) | ((dev)->slow << 26) | (dev)->maxpacketsize) -#define default_pipe(dev) ((dev)->slow <<26) + (((dev)->devnum << 8) | (endpoint << 15) | ((dev)->speed << 26) | (dev)->maxpacketsize) +#define default_pipe(dev) ((dev)->speed << 26) #define usb_sndctrlpipe(dev,endpoint) ((PIPE_CONTROL << 30) | create_pipe(dev,endpoint)) #define usb_rcvctrlpipe(dev,endpoint) ((PIPE_CONTROL << 30) | create_pipe(dev,endpoint) | USB_DIR_IN) @@ -315,7 +328,8 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); #define usb_pipe_endpdev(pipe) (((pipe) >> 8) & 0x7ff) #define usb_pipeendpoint(pipe) (((pipe) >> 15) & 0xf) #define usb_pipedata(pipe) (((pipe) >> 19) & 1) -#define usb_pipeslow(pipe) (((pipe) >> 26) & 1) +#define usb_pipespeed(pipe) (((pipe) >> 26) & 3) +#define usb_pipeslow(pipe) (usb_pipespeed(pipe) == USB_SPEED_LOW) #define usb_pipetype(pipe) (((pipe) >> 30) & 3) #define usb_pipeisoc(pipe) (usb_pipetype((pipe)) == PIPE_ISOCHRONOUS) #define usb_pipeint(pipe) (usb_pipetype((pipe)) == PIPE_INTERRUPT) diff --git a/include/usb_defs.h b/include/usb_defs.h index 353019f..8032e57 100644 --- a/include/usb_defs.h +++ b/include/usb_defs.h @@ -80,6 +80,12 @@ #define USB_DIR_OUT 0 #define USB_DIR_IN 0x80 +/* USB device speeds */ +#define USB_SPEED_FULL 0x0 /* 12Mbps */ +#define USB_SPEED_LOW 0x1 /* 1.5Mbps */ +#define USB_SPEED_HIGH 0x2 /* 480Mbps */ +#define USB_SPEED_RESERVED 0x3 + /* Descriptor types */ #define USB_DT_DEVICE 0x01 #define USB_DT_CONFIG 0x02 @@ -202,6 +208,7 @@ #define USB_PORT_FEAT_RESET 4 #define USB_PORT_FEAT_POWER 8 #define USB_PORT_FEAT_LOWSPEED 9 +#define USB_PORT_FEAT_HIGHSPEED 10 #define USB_PORT_FEAT_C_CONNECTION 16 #define USB_PORT_FEAT_C_ENABLE 17 #define USB_PORT_FEAT_C_SUSPEND 18 @@ -216,6 +223,9 @@ #define USB_PORT_STAT_RESET 0x0010 #define USB_PORT_STAT_POWER 0x0100 #define USB_PORT_STAT_LOW_SPEED 0x0200 +#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */ +#define USB_PORT_STAT_SPEED \ + (USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED) /* wPortChange bits */ #define USB_PORT_STAT_C_CONNECTION 0x0001 diff --git a/include/version.h b/include/version.h index 4f8b498..adab6a2 100644 --- a/include/version.h +++ b/include/version.h @@ -25,5 +25,8 @@ #define __VERSION_H__ #define U_BOOT_VERSION "U-Boot 1.1.4" +#if defined(CONFIG_BUFFALO_PLATFORM) +#define BUFFALO_VERSION "BOOTVER=0.27" +#endif #endif /* __VERSION_H__ */ diff --git a/lib_arm/.depend b/lib_arm/.depend new file mode 100644 index 0000000..e0106dd --- /dev/null +++ b/lib_arm/.depend @@ -0,0 +1,103 @@ +_udivsi3.o: _udivsi3.S +_umodsi3.o: _umodsi3.S +armlinux.o: armlinux.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/zlib.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/byteorder.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/little_endian.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/swab.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/generic.h +board.o: board.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/devices.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/lists.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/version.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/net.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/byteorder.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/little_endian.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/swab.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/generic.h +cache.o: cache.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +div0.o: div0.c diff --git a/lib_arm/armlinux.c b/lib_arm/armlinux.c index ca630b3..d2212a9 100644 --- a/lib_arm/armlinux.c +++ b/lib_arm/armlinux.c @@ -30,8 +30,11 @@ #include #endif +extern unsigned int whoAmI(void); + /*cmd_boot.c*/ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void mvEgigaStrToMac( char *source , char *dest ); #if defined (CONFIG_SETUP_MEMORY_TAGS) || \ defined (CONFIG_CMDLINE_TAG) || \ @@ -39,7 +42,10 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); defined (CONFIG_SERIAL_TAG) || \ defined (CONFIG_REVISION_TAG) || \ defined (CONFIG_VFD) || \ - defined (CONFIG_LCD) + defined (CONFIG_LCD) || \ + defined (CONFIG_MARVELL_TAG) + + static void setup_start_tag (bd_t *bd); # ifdef CONFIG_SETUP_MEMORY_TAGS @@ -60,8 +66,15 @@ static void setup_end_tag (bd_t *bd); static void setup_videolfb_tag (gd_t *gd); # endif +#if defined (CONFIG_MARVELL_TAG) +static void setup_marvell_tag(void); +#endif -static struct tag *params; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) +static struct tag *params[2]; +#else +static struct tag *params[1]; +#endif #endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ #ifdef CONFIG_SHOW_BOOT_PROGRESS @@ -71,8 +84,11 @@ static struct tag *params; # define SHOW_BOOT_PROGRESS(arg) #endif -extern image_header_t header; /* from cmd_bootm.c */ - +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) +extern image_header_t header[2]; /* from cmd_bootm.c */ +#else +extern image_header_t header[1]; /* from cmd_bootm.c */ +#endif void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong addr, ulong *len_ptr, int verify) @@ -83,15 +99,35 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong initrd_start, initrd_end; ulong data; void (*theKernel)(int zero, int arch, uint params); - image_header_t *hdr = &header; + image_header_t *hdr; bd_t *bd = gd->bd; + unsigned int cpu = 0; + unsigned int cpuindex = 0; #ifdef CONFIG_CMDLINE_TAG - char *commandline = getenv ("bootargs"); + char *commandline; +#ifdef CONFIG_MARVELL +#if defined(MV78200) + cpu = whoAmI(); + if (cpu == 0) #endif - + commandline = getenv ("bootargs"); +#if defined(MV78200) + else + commandline = getenv ("bootargs2"); +#endif +#else + commandline = getenv ("bootargs"); +#endif +#endif +#if defined(DUAL_OS_SHARED_MEM_78200) + cpuindex = cpu; +#endif + hdr = &header[cpuindex]; theKernel = (void (*)(int, int, uint))ntohl(hdr->ih_ep); + debug(" theKernel %x\n", theKernel); + /* * Check if there is an initrd image */ @@ -106,10 +142,10 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], #ifdef CONFIG_HAS_DATAFLASH if (addr_dataflash (addr)) { read_dataflash (addr, sizeof (image_header_t), - (char *) &header); + (char *) &header[cpuindex]); } else #endif - memcpy (&header, (char *) addr, + memcpy (&header[cpuindex], (char *) addr, sizeof (image_header_t)); if (ntohl (hdr->ih_magic) != IH_MAGIC) { @@ -118,13 +154,13 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], do_reset (cmdtp, flag, argc, argv); } - data = (ulong) & header; + data = (ulong) &header[cpuindex]; len = sizeof (image_header_t); checksum = ntohl (hdr->ih_hcrc); hdr->ih_hcrc = 0; - if (crc32 (0, (char *) data, len) != checksum) { + if (crc32 (0, (const char *) data, len) != checksum) { printf ("Bad Header Checksum\n"); SHOW_BOOT_PROGRESS (-11); do_reset (cmdtp, flag, argc, argv); @@ -148,7 +184,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong csum = 0; printf (" Verifying Checksum ... "); - csum = crc32 (0, (char *) data, len); + csum = crc32 (0, (const char *) data, len); if (csum != ntohl (hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); SHOW_BOOT_PROGRESS (-12); @@ -225,19 +261,25 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], debug ("## Transferring control to Linux (at address %08lx) ...\n", (ulong) theKernel); +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + /*Calculate boot params offset*/ + bd->bi_boot_params = ntohl(hdr->ih_ep)-0x8000+0x100; +#endif + #if defined (CONFIG_SETUP_MEMORY_TAGS) || \ defined (CONFIG_CMDLINE_TAG) || \ defined (CONFIG_INITRD_TAG) || \ defined (CONFIG_SERIAL_TAG) || \ defined (CONFIG_REVISION_TAG) || \ defined (CONFIG_LCD) || \ - defined (CONFIG_VFD) + defined (CONFIG_VFD) || \ + defined (CONFIG_MARVELL_TAG) setup_start_tag (bd); #ifdef CONFIG_SERIAL_TAG - setup_serial_tag (¶ms); + setup_serial_tag (¶ms[cpuindex]); #endif #ifdef CONFIG_REVISION_TAG - setup_revision_tag (¶ms); + setup_revision_tag (¶ms[cpuindex]); #endif #ifdef CONFIG_SETUP_MEMORY_TAGS setup_memory_tags (bd); @@ -251,6 +293,12 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], #endif #if defined (CONFIG_VFD) || defined (CONFIG_LCD) setup_videolfb_tag ((gd_t *) gd); +#endif +#if defined (CONFIG_MARVELL_TAG) + /* Linux open port doesn't support the Marvell TAG */ + char *env = getenv("mainlineLinux"); + if(!env || ((strcmp(env,"no") == 0) || (strcmp(env,"No") == 0))) + setup_marvell_tag (); #endif setup_end_tag (bd); #endif @@ -266,7 +314,9 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], #endif cleanup_before_linux (); - +#if defined(CONFIG_MARVELL) && defined(DUAL_OS_SHARED_MEM_78200) + mvSemaUnlock(1); +#endif theKernel (0, bd->bi_arch_number, bd->bi_boot_params); } @@ -277,19 +327,23 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], defined (CONFIG_SERIAL_TAG) || \ defined (CONFIG_REVISION_TAG) || \ defined (CONFIG_LCD) || \ - defined (CONFIG_VFD) + defined (CONFIG_VFD) || \ + defined (CONFIG_MARVELL_TAG) static void setup_start_tag (bd_t *bd) { - params = (struct tag *) bd->bi_boot_params; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + params[cpu] = (struct tag *) bd->bi_boot_params; + params[cpu]->hdr.tag = ATAG_CORE; + params[cpu]->hdr.size = tag_size (tag_core); - params->hdr.tag = ATAG_CORE; - params->hdr.size = tag_size (tag_core); + params[cpu]->u.core.flags = 0; + params[cpu]->u.core.pagesize = 0; + params[cpu]->u.core.rootdev = 0; - params->u.core.flags = 0; - params->u.core.pagesize = 0; - params->u.core.rootdev = 0; - - params = tag_next (params); + params[cpu] = tag_next (params[cpu]); } @@ -297,15 +351,19 @@ static void setup_start_tag (bd_t *bd) static void setup_memory_tags (bd_t *bd) { int i; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - params->hdr.tag = ATAG_MEM; - params->hdr.size = tag_size (tag_mem32); + params[cpu]->hdr.tag = ATAG_MEM; + params[cpu]->hdr.size = tag_size (tag_mem32); - params->u.mem.start = bd->bi_dram[i].start; - params->u.mem.size = bd->bi_dram[i].size; + params[cpu]->u.mem.start = bd->bi_dram[i].start; + params[cpu]->u.mem.size = bd->bi_dram[i].size; - params = tag_next (params); + params[cpu] = tag_next (params[cpu]); } } #endif /* CONFIG_SETUP_MEMORY_TAGS */ @@ -314,6 +372,10 @@ static void setup_memory_tags (bd_t *bd) static void setup_commandline_tag (bd_t *bd, char *commandline) { char *p; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif if (!commandline) return; @@ -327,29 +389,33 @@ static void setup_commandline_tag (bd_t *bd, char *commandline) if (*p == '\0') return; - params->hdr.tag = ATAG_CMDLINE; - params->hdr.size = + params[cpu]->hdr.tag = ATAG_CMDLINE; + params[cpu]->hdr.size = (sizeof (struct tag_header) + strlen (p) + 1 + 4) >> 2; - strcpy (params->u.cmdline.cmdline, p); - - params = tag_next (params); + strcpy (params[cpu]->u.cmdline.cmdline, p); + params[cpu] = tag_next (params[cpu]); } #ifdef CONFIG_INITRD_TAG static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end) { + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + /* an ATAG_INITRD node tells the kernel where the compressed * ramdisk can be found. ATAG_RDIMG is a better name, actually. */ - params->hdr.tag = ATAG_INITRD2; - params->hdr.size = tag_size (tag_initrd); + params[cpu]->hdr.tag = ATAG_INITRD2; + params[cpu]->hdr.size = tag_size (tag_initrd); - params->u.initrd.start = initrd_start; - params->u.initrd.size = initrd_end - initrd_start; + params[cpu]->u.initrd.start = initrd_start; + params[cpu]->u.initrd.size = initrd_end - initrd_start; - params = tag_next (params); + params[cpu] = tag_next (params[cpu]); } #endif /* CONFIG_INITRD_TAG */ @@ -358,6 +424,11 @@ static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end) extern ulong calc_fbsize (void); static void setup_videolfb_tag (gd_t *gd) { + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + /* An ATAG_VIDEOLFB node tells the kernel where and how large * the framebuffer for video was allocated (among other things). * Note that a _physical_ address is passed ! @@ -365,31 +436,145 @@ static void setup_videolfb_tag (gd_t *gd) * We only use it to pass the address and size, the other entries * in the tag_videolfb are not of interest. */ - params->hdr.tag = ATAG_VIDEOLFB; - params->hdr.size = tag_size (tag_videolfb); + params[cpu]->hdr.tag = ATAG_VIDEOLFB; + params[cpu]->hdr.size = tag_size (tag_videolfb); - params->u.videolfb.lfb_base = (u32) gd->fb_base; + params[cpu]->u.videolfb.lfb_base = (u32) gd->fb_base; /* Fb size is calculated according to parameters for our panel */ - params->u.videolfb.lfb_size = calc_fbsize(); + params[cpu]->u.videolfb.lfb_size = calc_fbsize(); - params = tag_next (params); + params[cpu] = tag_next (params[cpu]); } #endif /* CONFIG_VFD || CONFIG_LCD */ +#if defined(CONFIG_MARVELL_TAG) +static void setup_marvell_tag (void) +{ + char *env; + char temp[20]; + int i; + unsigned int boardId; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + + params[cpu]->hdr.tag = ATAG_MARVELL; + params[cpu]->hdr.size = tag_size (tag_mv_uboot); + + params[cpu]->u.mv_uboot.uboot_version = VER_NUM; + if(strcmp(getenv("nandEcc"), "4bit") == 0) + { + params[cpu]->u.mv_uboot.nand_ecc = 4; + } + else if(strcmp(getenv("nandEcc"), "1bit") == 0) + { + params[cpu]->u.mv_uboot.nand_ecc = 1; + } + + extern unsigned int mvBoardIdGet(void); + + boardId = mvBoardIdGet(); + params[cpu]->u.mv_uboot.uboot_version |= boardId; + + params[cpu]->u.mv_uboot.tclk = CFG_TCLK; + params[cpu]->u.mv_uboot.sysclk = CFG_BUS_CLK; + +#if defined(MV78XX0) + /* Dual CPU Firmware load address */ + env = getenv("fw_image_base"); + if(env) + params[cpu]->u.mv_uboot.fw_image_base = simple_strtoul(env, NULL, 16); + else + params[cpu]->u.mv_uboot.fw_image_base = 0; + + /* Dual CPU Firmware size */ + env = getenv("fw_image_size"); + if(env) + params[cpu]->u.mv_uboot.fw_image_size = simple_strtoul(env, NULL, 16); + else + params[cpu]->u.mv_uboot.fw_image_size = 0; +#endif + +#if defined(MV_INCLUDE_USB) + extern unsigned int mvCtrlUsbMaxGet(void); + + for (i = 0 ; i < mvCtrlUsbMaxGet(); i++) + { + sprintf( temp, "usb%dMode", i); + env = getenv(temp); + if((!env) || (strcmp(env,"Host") == 0 ) || (strcmp(env,"host") == 0) ) + params[cpu]->u.mv_uboot.isUsbHost |= (1 << i); + else + params[cpu]->u.mv_uboot.isUsbHost &= ~(1 << i); + + } +#endif /*#if defined(MV_INCLUDE_USB)*/ +#if defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) + extern unsigned int mvCtrlEthMaxPortGet(void); + extern int mvMacStrToHex(const char* macStr, unsigned char* macHex); + + for (i = 0 ;i < 4;i++) + { + memset(params[cpu]->u.mv_uboot.macAddr[i], 0, sizeof(params[cpu]->u.mv_uboot.macAddr[i])); + params[cpu]->u.mv_uboot.mtu[i] = 0; + } + + for (i = 0 ;i < mvCtrlEthMaxPortGet();i++) + { +/* only on RD-6281-A egiga0 defined as eth1 */ +#if defined (RD_88F6281A) + sprintf( temp,(i==0 ? "eth1addr" : "ethaddr")); +#else + sprintf( temp,(i ? "eth%daddr" : "ethaddr"), i); +#endif + + env = getenv(temp); + if (env) + mvMacStrToHex(env, params[cpu]->u.mv_uboot.macAddr[i]); + +/* only on RD-6281-A egiga0 defined as eth1 */ +#if defined (RD_88F6281A) + sprintf( temp,(i==0 ? "eth1mtu" : "ethmtu")); +#else + sprintf( temp,(i ? "eth%dmtu" : "ethmtu"), i); +#endif + + env = getenv(temp); + if (env) + params[cpu]->u.mv_uboot.mtu[i] = simple_strtoul(env, NULL, 10); + } +#endif /* (MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) */ + +#if defined(CONFIG_BUFFALO_PLATFORM) +#include + params[cpu]->u.mv_uboot.env_addr = CFG_ENV_ADDR; + params[cpu]->u.mv_uboot.env_size = CFG_ENV_SIZE; + params[cpu]->u.mv_uboot.env_offset = CFG_ENV_OFFSET; +#endif + params[cpu] = tag_next (params[cpu]); + +} +#endif + #ifdef CONFIG_SERIAL_TAG void setup_serial_tag (struct tag **tmp) { struct tag *params = *tmp; struct tag_serialnr serialnr; void get_board_serial(struct tag_serialnr *serialnr); + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif get_board_serial(&serialnr); - params->hdr.tag = ATAG_SERIAL; - params->hdr.size = tag_size (tag_serialnr); - params->u.serialnr.low = serialnr.low; - params->u.serialnr.high= serialnr.high; - params = tag_next (params); + params[cpu]->hdr.tag = ATAG_SERIAL; + params[cpu]->hdr.size = tag_size (tag_serialnr); + params[cpu]->u.serialnr.low = serialnr.low; + params[cpu]->u.serialnr.high= serialnr.high; + params[cpu] = tag_next (params[cpu]); *tmp = params; } #endif @@ -399,20 +584,29 @@ void setup_revision_tag(struct tag **in_params) { u32 rev = 0; u32 get_board_rev(void); + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif rev = get_board_rev(); - params->hdr.tag = ATAG_REVISION; - params->hdr.size = tag_size (tag_revision); - params->u.revision.rev = rev; - params = tag_next (params); + params[cpu]->hdr.tag = ATAG_REVISION; + params[cpu]->hdr.size = tag_size (tag_revision); + params[cpu]->u.revision.rev = rev; + params[cpu] = tag_next (params[cpu]); } #endif /* CONFIG_REVISION_TAG */ static void setup_end_tag (bd_t *bd) { - params->hdr.tag = ATAG_NONE; - params->hdr.size = 0; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + + params[cpu]->hdr.tag = ATAG_NONE; + params[cpu]->hdr.size = 0; } #endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ diff --git a/lib_arm/board.c b/lib_arm/board.c index fa3c92e..22ea8f0 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -32,6 +32,17 @@ #include #include +#if defined(CONFIG_MARVELL) + extern int PTexist(void); + extern unsigned long mvFlash_init (void); + extern unsigned int whoAmI(void); + extern int cpuMapInit (void); +#if defined(MV78200) + extern void second_cpu_realloc_and_load(void); +#include "../board/mv_feroceon/common/mvTypes.h" +#include "../board/mv_feroceon/mv_dd/dd_family/mv78200/mvSocUnitMap.h" +#endif +#endif #ifdef CONFIG_DRIVER_SMC91111 #include "../drivers/smc91111.h" #endif @@ -56,6 +67,9 @@ extern void dataflash_print_info(void); const char version_string[] = U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"CONFIG_IDENT_STRING; +#if defined(CONFIG_BUFFALO_PLATFORM) +const char buffalo_version_string[] = BUFFALO_VERSION; +#endif #ifdef CONFIG_DRIVER_CS8900 extern void cs8900_get_enetaddr (uchar * addr); @@ -65,6 +79,10 @@ extern void cs8900_get_enetaddr (uchar * addr); extern void rtl8019_get_enetaddr (uchar * addr); #endif +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) +extern void recoveryCheck(void); +#endif + /* * Begin and End of memory area for malloc(), and current "brk" */ @@ -75,12 +93,43 @@ static ulong mem_malloc_brk = 0; static void mem_malloc_init (ulong dest_addr) { +#ifndef CONFIG_MARVELL mem_malloc_start = dest_addr; mem_malloc_end = dest_addr + CFG_MALLOC_LEN; mem_malloc_brk = mem_malloc_start; memset ((void *) mem_malloc_start, 0, mem_malloc_end - mem_malloc_start); +#else + unsigned int malloc_len; + char *env; + +#if defined(CONFIG_MARVELL) && defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + unsigned int cfg_malloc_len = CFG_MALLOC_LEN/2; + unsigned int cfg_malloc_base = CFG_MALLOC_BASE+(whoAmI()*cfg_malloc_len); +#else + unsigned int cfg_malloc_len = CFG_MALLOC_LEN; + unsigned int cfg_malloc_base = CFG_MALLOC_BASE; +#endif + + env = getenv("MALLOC_len"); + malloc_len = simple_strtoul(env, NULL, 10) << 20; + if(malloc_len == 0) + malloc_len = cfg_malloc_len; + + mem_malloc_end = cfg_malloc_base + malloc_len; + printf("Addresses %dM - 0M are saved for the U-Boot usage.\n",mem_malloc_end >> 20); + + mem_malloc_start = cfg_malloc_base; + mem_malloc_brk = mem_malloc_start; + + printf("Mem malloc Initialization (%dM - %dM):",mem_malloc_end >> 20, + mem_malloc_start >>20 ); + memset ((void *) mem_malloc_start,0,mem_malloc_end - mem_malloc_start); + + printf(" Done\n"); + +#endif } void *sbrk (ptrdiff_t increment) @@ -129,6 +178,9 @@ static int display_banner (void) printf ("IRQ Stack: %08lx\n", IRQ_STACK_START); printf ("FIQ Stack: %08lx\n", FIQ_STACK_START); #endif +#if defined(CONFIG_BUFFALO_PLATFORM) + printf("BUFFALO_%s\n", buffalo_version_string); +#endif return (0); } @@ -140,6 +192,8 @@ static int display_banner (void) * gives a simple yet clear indication which part of the * initialization if failing. */ +#ifndef CONFIG_MARVELL + static int display_dram_config (void) { DECLARE_GLOBAL_DATA_PTR; @@ -155,6 +209,8 @@ static int display_dram_config (void) return (0); } +#endif + static void display_flash_config (ulong size) { puts ("Flash: "); @@ -196,14 +252,32 @@ init_fnc_t *init_sequence[] = { serial_init, /* serial communications setup */ console_init_f, /* stage 1 init of console */ display_banner, /* say that we are here */ +#if defined(CONFIG_MARVELL) && defined(MV78XX0) + cpuMapInit, +#endif dram_init, /* configure available RAM banks */ +#ifndef CONFIG_MARVELL display_dram_config, +#endif #if defined(CONFIG_VCMA9) || defined (CONFIG_CMC_PU2) checkboard, #endif NULL, }; +#if defined(CONFIG_MARVELL) && defined(MV78200) +init_fnc_t *init_sequence_slave[] = { + cpu_init, /* basic cpu dependent setup */ + board_init, /* basic board dependent setup */ + interrupt_init, /* set up exceptions */ + env_init, + serial_init, /* serial communications setup */ + console_init_f, /* stage 1 init of console */ + display_banner, /* say that we are here */ + NULL, /* Terminate this list */ +}; +#endif + void start_armboot (void) { DECLARE_GLOBAL_DATA_PTR; @@ -211,15 +285,35 @@ void start_armboot (void) ulong size; init_fnc_t **init_fnc_ptr; char *s; + char *env; + volatile unsigned int cpu = 0; + int nand_access = 0; #if defined(CONFIG_VFD) || defined(CONFIG_LCD) unsigned long addr; #endif - /* Pointer is writable since we allocated a register for it */ +#ifndef CONFIG_MARVELL gd = (gd_t*)(_armboot_start - CFG_MALLOC_LEN - sizeof(gd_t)); +#else +#if defined(CONFIG_MARVELL) && defined(MV78200) + /* Marvell Master CPU Boot */ + cpu = whoAmI(); +#if !defined(DUAL_OS_78200) + if(cpu == 0) +#endif +#endif + gd = (gd_t*)(_armboot_start - sizeof(gd_t)); +#endif /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); +#if defined(CONFIG_MARVELL) && defined(MV78200) + /* Marvell Master CPU Boot */ +#if !defined(DUAL_OS_78200) + if(cpu == 0) + { +#endif +#endif memset ((void*)gd, 0, sizeof (gd_t)); gd->bd = (bd_t*)((char*)gd - sizeof(bd_t)); memset (gd->bd, 0, sizeof (bd_t)); @@ -231,10 +325,37 @@ void start_armboot (void) hang (); } } + /* armboot_start is defined in the board-specific linker script */ + mem_malloc_init (_armboot_start - CFG_MALLOC_LEN); + +#if !(defined(MV78200) && (defined(DUAL_OS_78200) || \ + (defined(DUAL_OS_SHARED_MEM_78200) && !defined(MV_NAND_BOOT)))) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + puts ("NAND:"); + nand_init(); /* go init the NAND */ +#endif +#endif + /* initialize environment */ + env_relocate (); + +#if defined(MV78200) && (defined(DUAL_OS_78200) || defined(DUAL_OS_SHARED_MEM_78200)) + env = getenv("cpu0_res"); + if (env) + mvSocUnitMapFillTable(env, MASTER_CPU, strstr); + env = getenv("cpu1_res"); + if (env) + mvSocUnitMapFillTable(env, SLAVE_CPU, strstr); +#endif + +#ifndef CFG_NO_FLASH /* configure available FLASH banks */ size = flash_init (); +#if defined(CONFIG_MARVELL) + size += mvFlash_init (); +#endif display_flash_config (size); +#endif /* CFG_NO_FLASH */ #ifdef CONFIG_VFD # ifndef PAGE_SIZE @@ -262,12 +383,16 @@ void start_armboot (void) gd->fb_base = addr; #endif /* CONFIG_LCD */ - /* armboot_start is defined in the board-specific linker script */ - mem_malloc_init (_armboot_start - CFG_MALLOC_LEN); - +#if defined(MV78200) && (defined(DUAL_OS_78200) || \ + (defined(DUAL_OS_SHARED_MEM_78200) && !defined(MV_NAND_BOOT))) #if (CONFIG_COMMANDS & CFG_CMD_NAND) - puts ("NAND:"); - nand_init(); /* go init the NAND */ + /* Check in dual CPU system which CPU use nand */ + if (mvSocUnitIsMappedToThisCpu(NAND_FLASH)) + { + puts ("NAND:"); + nand_init(); /* go init the NAND */ + } +#endif #endif #ifdef CONFIG_HAS_DATAFLASH @@ -275,8 +400,14 @@ void start_armboot (void) dataflash_print_info(); #endif - /* initialize environment */ - env_relocate (); +#ifdef CFG_DIAG +#define DIAGNOSTICS +#ifdef DIAGNOSTICS + if( !strcmp(getenv("run_diag"), "yes") || + !strcmp(getenv("run_diag"), "YES")) + run_diag(); +#endif +#endif #ifdef CONFIG_VFD /* must do this after the framebuffer is allocated */ @@ -284,7 +415,14 @@ void start_armboot (void) #endif /* CONFIG_VFD */ /* IP Address */ +#if defined(CONFIG_MARVELL) && defined(DUAL_OS_78200) + if(cpu == 0) gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + else + gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr2"); +#else + gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); +#endif /* MAC Address */ { @@ -317,7 +455,6 @@ void start_armboot (void) /* miscellaneous platform dependent initialisations */ misc_init_r (); #endif - /* enable exceptions */ enable_interrupts (); @@ -345,11 +482,77 @@ void start_armboot (void) #ifdef BOARD_LATE_INIT board_late_init (); #endif +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + puts ("SCSI: "); + scsi_init (); +#endif #if (CONFIG_COMMANDS & CFG_CMD_NET) #if defined(CONFIG_NET_MULTI) puts ("Net: "); #endif eth_initialize(gd->bd); +#endif +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) + recoveryCheck(); +#endif +/* Cancle SILENT mode for prompt only */ +#if defined(CONFIG_MARVELL) && defined(CONFIG_SILENT_CONSOLE) + DECLARE_GLOBAL_DATA_PTR; + gd->flags &= ~GD_FLG_SILENT; +#endif +#if defined(CONFIG_MARVELL) && defined(MV78200) +#if !defined(DUAL_OS_78200) + /* Marvell Second CPU Boot */ + } + else + { + /* Master CPU global data */ + gd_t *gd_master; + gd_master = (gd_t*)(_armboot_start - sizeof(gd_t)); + /* Slave CPU global data */ + gd = (gd_t*)(_armboot_start - _1M - sizeof(gd_t)); + memset ((void *) gd, 0, sizeof (gd_t)); + memcpy ((void *)gd, (const void *)gd_master, sizeof (gd_t)); + gd->bd = (bd_t*)((char*)gd - sizeof(bd_t)); + memset ((void *) gd->bd, 0, sizeof (bd_t)); + + /*copy the Global Data from the Master. */ + memcpy ((void *)gd->bd, (const void *)gd_master->bd, sizeof (bd_t)); + for (init_fnc_ptr = init_sequence_slave; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) { + hang (); + } + } + gd->env_addr = gd_master->env_addr; +#if defined(DUAL_OS_SHARED_MEM_78200) + /* armboot_start is defined in the board-specific linker script */ + mem_malloc_init (_armboot_start - CFG_MALLOC_LEN); + env = getenv("cpu0_res"); + if (env) + mvSocUnitMapFillTable(env, MASTER_CPU, strstr); + env = getenv("cpu1_res"); + if (env) + mvSocUnitMapFillTable(env, SLAVE_CPU, strstr); + gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr2"); +#endif + misc_init_r (); +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + puts ("SCSI: "); + scsi_init (); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if defined(CONFIG_NET_MULTI) + puts ("Net: "); +#endif + eth_initialize(gd->bd); +#endif + + } +#endif + if (cpu == 0) { + second_cpu_realloc_and_load(); + } #endif /* main_loop() can return to retry autoboot, if so just run it again. */ for (;;) { diff --git a/lib_generic/.depend b/lib_generic/.depend new file mode 100644 index 0000000..6c22040 --- /dev/null +++ b/lib_generic/.depend @@ -0,0 +1,191 @@ +bzlib.o: bzlib.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h +ldiv.o: ldiv.c +div64.o: div64.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h +string.o: string.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/ctype.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h +vsprintf.o: vsprintf.c \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/ctype.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h +zlib.o: zlib.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/zlib.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h diff --git a/lib_generic/Makefile b/lib_generic/Makefile index 18c41b1..ce2c992 100644 --- a/lib_generic/Makefile +++ b/lib_generic/Makefile @@ -1,43 +1,43 @@ -# -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = libgeneric.a - -OBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \ - bzlib_randtable.o bzlib_huffman.o \ - crc32.o ctype.o display_options.o ldiv.o \ - string.o vsprintf.o zlib.o - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libgeneric.a + +OBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \ + bzlib_randtable.o bzlib_huffman.o \ + crc32.o ctype.o display_options.o ldiv.o div64.o \ + string.o vsprintf.o zlib.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c index 50ca4ff..386d18e 100644 --- a/lib_generic/crc32.c +++ b/lib_generic/crc32.c @@ -171,7 +171,7 @@ uLong ZEXPORT crc32(crc, buf, len) return crc ^ 0xffffffffL; } -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#if ((CONFIG_COMMANDS & CFG_CMD_JFFS2) | (CONFIG_COMMANDS & CFG_CMD_NAND)) /* No ones complement version. JFFS2 (and other things ?) * don't use ones compliment in their CRC calculations. @@ -194,4 +194,4 @@ uLong ZEXPORT crc32_no_comp(uLong crc, const Bytef *buf, uInt len) return crc; } -#endif /* CFG_CMD_JFFS2 */ +#endif /* CFG_CMD_JFFS2 CFG_CMD_NAND */ diff --git a/lib_generic/div64.c b/lib_generic/div64.c new file mode 100644 index 0000000..214fbdd --- /dev/null +++ b/lib_generic/div64.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2003 Bernardo Innocenti + * + * Based on former do_div() implementation from asm-parisc/div64.h: + * Copyright (C) 1999 Hewlett-Packard Co + * Copyright (C) 1999 David Mosberger-Tang + * + * + * Generic C version of 64bit/32bit division and modulo, with + * 64bit result and 32bit remainder. + * + * The fast case for (n>>32 == 0) is handled inline by do_div(). + * + * Code generated for this function might be very inefficient + * for some CPUs. __div64_32() can be overridden by linking arch-specific + * assembly versions such as arch/ppc/lib/div64.S and arch/sh/lib/div64.S. + */ + +#include + +uint32_t __div64_32(uint64_t *n, uint32_t base) +{ + uint64_t rem = *n; + uint64_t b = base; + uint64_t res, d = 1; + uint32_t high = rem >> 32; + + /* Reduce the thing a bit first */ + res = 0; + if (high >= base) { + high /= base; + res = (uint64_t) high << 32; + rem -= (uint64_t) (high*base) << 32; + } + + while ((int64_t)b > 0 && b < rem) { + b = b+b; + d = d+d; + } + + do { + if (rem >= b) { + rem -= b; + res += d; + } + b >>= 1; + d >>= 1; + } while (d); + + *n = res; + return rem; +} diff --git a/lib_i386/Makefile b/lib_i386/Makefile deleted file mode 100644 index e5925e5..0000000 --- a/lib_i386/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(ARCH).a - -AOBJS = bios.o bios_pci.o realmode_switch.o - -COBJS = board.o bios_setup.o i386_linux.o zimage.o realmode.o \ - pci_type1.o pci.o video_bios.o video.o - -OBJS = $(AOBJS) $(COBJS) - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/lib_i386/bios.S b/lib_i386/bios.S deleted file mode 100644 index 4606419..0000000 --- a/lib_i386/bios.S +++ /dev/null @@ -1,462 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Based on msbios.c from rolo 1.6: - *---------------------------------------------------------------------- - * (C) Copyright 2000 - * Sysgo Real-Time Solutions GmbH - * Klein-Winternheim, Germany - *---------------------------------------------------------------------- - */ - -#include "bios.h" - -/* - * During it's initialization phase, before switching to protected - * mode, the Linux Kernel makes a few BIOS calls. This won't work - * if the board does not have a BIOS. - * - * This is a very minimalisic BIOS that supplies just enough - * functionality to keep the Linux Kernel happy. It is NOT - * a general purpose replacement for a real BIOS !! - */ - - -.section .bios, "ax" -.code16 -.org 0 - /* a call to f000:0 should warmboot */ - jmp realmode_reset - -.globl rm_int00 -rm_int00: - pushw $0 - jmp any_interrupt16 -.globl rm_int01 -rm_int01: - pushw $1 - jmp any_interrupt16 -.globl rm_int02 -rm_int02: - pushw $2 - jmp any_interrupt16 -.globl rm_int03 -rm_int03: - pushw $3 - jmp any_interrupt16 -.globl rm_int04 -rm_int04: - pushw $4 - jmp any_interrupt16 -.globl rm_int05 -rm_int05: - pushw $5 - jmp any_interrupt16 -.globl rm_int06 -rm_int06: - pushw $6 - jmp any_interrupt16 -.globl rm_int07 -rm_int07: - pushw $7 - jmp any_interrupt16 -.globl rm_int08 -rm_int08: - pushw $8 - jmp any_interrupt16 -.globl rm_int09 -rm_int09: - pushw $9 - jmp any_interrupt16 -.globl rm_int0a -rm_int0a: - pushw $10 - jmp any_interrupt16 -.globl rm_int0b -rm_int0b: - pushw $11 - jmp any_interrupt16 -.globl rm_int0c -rm_int0c: - pushw $12 - jmp any_interrupt16 -.globl rm_int0d -rm_int0d: - pushw $13 - jmp any_interrupt16 -.globl rm_int0e -rm_int0e: - pushw $14 - jmp any_interrupt16 -.globl rm_int0f -rm_int0f: - pushw $15 - jmp any_interrupt16 -.globl rm_int10 -rm_int10: - pushw $16 - jmp any_interrupt16 -.globl rm_int11 -rm_int11: - pushw $17 - jmp any_interrupt16 -.globl rm_int12 -rm_int12: - pushw $18 - jmp any_interrupt16 -.globl rm_int13 -rm_int13: - pushw $19 - jmp any_interrupt16 -.globl rm_int14 -rm_int14: - pushw $20 - jmp any_interrupt16 -.globl rm_int15 -rm_int15: - pushw $21 - jmp any_interrupt16 -.globl rm_int16 -rm_int16: - pushw $22 - jmp any_interrupt16 -.globl rm_int17 -rm_int17: - pushw $23 - jmp any_interrupt16 -.globl rm_int18 -rm_int18: - pushw $24 - jmp any_interrupt16 -.globl rm_int19 -rm_int19: - pushw $25 - jmp any_interrupt16 -.globl rm_int1a -rm_int1a: - pushw $26 - jmp any_interrupt16 -.globl rm_int1b -rm_int1b: - pushw $27 - jmp any_interrupt16 -.globl rm_int1c -rm_int1c: - pushw $28 - jmp any_interrupt16 -.globl rm_int1d -rm_int1d: - pushw $29 - jmp any_interrupt16 -.globl rm_int1e -rm_int1e: - pushw $30 - jmp any_interrupt16 -.globl rm_int1f -rm_int1f: - pushw $31 - jmp any_interrupt16 -.globl rm_def_int -rm_def_int: - iret - - - /* - * All interrupt jumptable entries jump to here - * after pushing the interrupt vector number onto the - * stack. - */ -any_interrupt16: - MAKE_BIOS_STACK - -gs movw OFFS_VECTOR(%bp), %ax - cmpw $0x10, %ax - je Lint_10h - cmpw $0x11, %ax - je Lint_11h - cmpw $0x12, %ax - je Lint_12h - cmpw $0x13, %ax - je Lint_13h - cmpw $0x15, %ax - je Lint_15h - cmpw $0x16, %ax - je Lint_16h - cmpw $0x1a, %ax - je Lint_1ah - movw $0xffff, %ax - jmp Lout -Lint_10h: /* VGA BIOS services */ - call bios_10h - jmp Lout -Lint_11h: - call bios_11h - jmp Lout -Lint_12h: - call bios_12h - jmp Lout -Lint_13h: /* BIOS disk services */ - call bios_13h - jmp Lout -Lint_15h: /* Misc. BIOS services */ - call bios_15h - jmp Lout -Lint_16h: /* keyboard services */ - call bios_16h - jmp Lout -Lint_1ah: /* PCI bios */ - call bios_1ah - jmp Lout -Lout: - cmpw $0, %ax - je Lhandeled - - /* Insert code for unhandeled INTs here. - * - * ROLO prints a message to the console - * (we could do that but then we're in 16bit mode - * so we'll have to get back into 32bit mode - * to use the console I/O routines (if we do this - * we shuls make int 0x10 and int 0x16 work as well)) - */ -Lhandeled: - RESTORE_CALLERS_STACK - addw $2,%sp /* dump vector number */ - iret /* return from interrupt */ - - -/* - ************************************************************ - * BIOS interrupt 10h -- VGA services - ************************************************************ - */ -bios_10h: -gs movw OFFS_AX(%bp), %ax - shrw $8, %ax - cmpw $0x3, %ax - je Lcur_pos - cmpw $0xf, %ax - je Lvid_state - cmpw $0x12, %ax - je Lvid_cfg - movw $0xffff, %ax - ret -Lcur_pos: /* Read Cursor Position and Size */ -gs movw $0, OFFS_CX(%bp) -gs movw $0, OFFS_DX(%bp) - xorw %ax, %ax - ret -Lvid_state: /* Get Video State */ -gs movw $(80 << 8|0x03), OFFS_AX(%bp) /* 80 columns, 80x25, 16 colors */ -gs movw $0, OFFS_BX(%bp) - xorw %ax, %ax - ret -Lvid_cfg: /* Video Subsystem Configuration (EGA/VGA) */ -gs movw $0x10, OFFS_BX(%bp) /* indicate CGA/MDA/HGA */ - xorw %ax, %ax - ret - - -/* - ************************************************************ - * BIOS interrupt 11h -- Equipment determination - ************************************************************ - */ - -bios_11h: -cs movw bios_equipment, %ax -gs movw %ax, OFFS_AX(%bp) - xorw %ax, %ax - ret - - -/* - ************************************************************ - * BIOS interrupt 12h -- Get Memory Size - ************************************************************ - */ -bios_12h: -cs movw ram_in_64kb_chunks, %ax - cmpw $0xa, %ax - ja b12_more_than_640k - shlw $6, %ax - jmp b12_return -b12_more_than_640k: - movw $0x280, %ax -b12_return: -gs movw %ax, OFFS_AX(%bp) /* return number of kilobytes in ax */ - -gs movw OFFS_FLAGS(%bp), %ax - andw $0xfffe, %ax /* clear carry -- function succeeded */ -gs movw %ax, OFFS_FLAGS(%bp) - - xorw %ax, %ax - ret - - -/* - ************************************************************ - * BIOS interrupt 13h -- Disk services - ************************************************************ - */ -bios_13h: -gs movw OFFS_AX(%bp), %ax - shrw $8, %ax - cmpw $0x15, %ax - je Lfunc_15h - movw $0xffff, %ax - ret -Lfunc_15h: -gs movw OFFS_AX(%bp), %ax - andw $0xff, %ax /* return AH=0->drive not present */ -gs movw %ax, OFFS_AX(%bp) - xorw %ax, %ax - ret - - -/* - *********************************************************** - * BIOS interrupt 15h -- Miscellaneous services - *********************************************************** - */ -bios_15h: -gs movw OFFS_AX(%bp), %ax - shrw $8, %ax - cmpw $0xc0, %ax - je Lfunc_c0h - cmpw $0xe8, %ax - je Lfunc_e8h - cmpw $0x88, %ax - je Lfunc_88h - movw $0xffff, %ax - ret - -Lfunc_c0h: /* Return System Configuration Parameters (PS2 only) */ -gs movw OFFS_FLAGS(%bp), %ax - orw $1, %ax /* return carry -- function not supported */ -gs movw %ax, OFFS_FLAGS(%bp) - xorw %ax, %ax - ret - -Lfunc_e8h: -gs movw OFFS_AX(%bp), %ax - andw $0xff, %ax - cmpw $1, %ax - je Lfunc_e801h -gs movw OFFS_FLAGS(%bp), %ax - orw $1, %ax /* return carry -- function not supported */ -gs movw %ax, OFFS_FLAGS(%bp) - xorw %ax, %ax - ret - -Lfunc_e801h: /* Get memory size for >64M Configurations */ -cs movw ram_in_64kb_chunks, %ax - cmpw $0x100, %ax - ja e801_more_than_16mb - shlw $6, %ax /* multiply by 64 */ - subw $0x400, %ax /* 1st meg does not count */ - -gs movw %ax, OFFS_AX(%bp) /* return memory size between 1M and 16M in 1kb chunks in AX and CX */ -gs movw %ax, OFFS_CX(%bp) -gs movw $0, OFFS_BX(%bp) /* set BX and DX to 0*/ -gs movw $0, OFFS_DX(%bp) -gs movw OFFS_FLAGS(%bp), %ax - andw $0xfffe, %ax /* clear carry -- function succeeded */ -gs movw %ax, OFFS_FLAGS(%bp) - xorw %ax, %ax - ret - -e801_more_than_16mb: - subw $0x100, %ax /* subtract 16MB */ - -gs movw $0x3c00, OFFS_AX(%bp) /* return 0x3c00 (16MB-1MB) in AX and CX */ -gs movw $0x3c00, OFFS_CX(%bp) -gs movw %ax, OFFS_BX(%bp) /* set BX and DX to number of 64kb chunks above 16MB */ -gs movw %ax, OFFS_DX(%bp) - -gs movw OFFS_FLAGS(%bp), %ax - andw $0xfffe, %ax /* clear carry -- function succeeded */ -gs movw %ax, OFFS_FLAGS(%bp) - xorw %ax, %ax - ret - -Lfunc_88h: -cs movw ram_in_64kb_chunks, %ax - cmpw $0x100, %ax - jna b88_not_more_than16 - movw $0x100, %ax -b88_not_more_than16: - shlw $6, %ax - subw $0x400, %ax /* 1st meg does not count */ - -gs movw %ax, OFFS_AX(%bp) /* return number of kilobytes between 16MB and 16MB in ax */ - -gs movw OFFS_FLAGS(%bp), %ax - andw $0xfffe, %ax /* clear carry -- function succeeded */ -gs movw %ax, OFFS_FLAGS(%bp) - - xorw %ax, %ax - ret - - -/* - ************************************************************ - * BIOS interrupt 16h -- keyboard services - ************************************************************ - */ -bios_16h: -gs movw OFFS_AX(%bp), %ax - shrw $8, %ax - cmpw $0x03, %ax - je Lfunc_03h - movw $0xffff, %ax - ret -Lfunc_03h: - xorw %ax, %ax /* do nothing -- function not supported */ - ret - -/* - ************************************************************ - * BIOS interrupt 1ah -- PCI bios - ************************************************************ - */ -bios_1ah: -gs movw OFFS_AX(%bp), %ax - cmpb $0xb1, %ah - je Lfunc_b1h - movw $0xffff, %ax - ret -Lfunc_b1h: - call realmode_pci_bios - xorw %ax, %ax /* do nothing -- function not supported */ - ret - - -.globl ram_in_64kb_chunks -ram_in_64kb_chunks: - .word 0 - -.globl bios_equipment -bios_equipment: - .word 0 diff --git a/lib_i386/bios.h b/lib_i386/bios.h deleted file mode 100644 index 59143dd..0000000 --- a/lib_i386/bios.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BIOS_H_ -#define _BIOS_H_ - -#define OFFS_ES 0 /* 16bit */ -#define OFFS_GS 2 /* 16bit */ -#define OFFS_DS 4 /* 16bit */ -#define OFFS_EDI 6 /* 32bit */ -#define OFFS_DI 6 /* low 16 bits of EDI */ -#define OFFS_ESI 10 /* 32bit */ -#define OFFS_SI 10 /* low 16 bits of ESI */ -#define OFFS_EBP 14 /* 32bit */ -#define OFFS_BP 14 /* low 16 bits of EBP */ -#define OFFS_ESP 18 /* 32bit */ -#define OFFS_SP 18 /* low 16 bits of ESP */ -#define OFFS_EBX 22 /* 32bit */ -#define OFFS_BX 22 /* low 16 bits of EBX */ -#define OFFS_BL 22 /* low 8 bits of BX */ -#define OFFS_BH 23 /* high 8 bits of BX */ -#define OFFS_EDX 26 /* 32bit */ -#define OFFS_DX 26 /* low 16 bits of EBX */ -#define OFFS_DL 26 /* low 8 bits of BX */ -#define OFFS_DH 27 /* high 8 bits of BX */ -#define OFFS_ECX 30 /* 32bit */ -#define OFFS_CX 30 /* low 16 bits of EBX */ -#define OFFS_CL 30 /* low 8 bits of BX */ -#define OFFS_CH 31 /* high 8 bits of BX */ -#define OFFS_EAX 34 /* 32bit */ -#define OFFS_AX 34 /* low 16 bits of EBX */ -#define OFFS_AL 34 /* low 8 bits of BX */ -#define OFFS_AH 35 /* high 8 bits of BX */ -#define OFFS_VECTOR 38 /* 16bit */ -#define OFFS_IP 40 /* 16bit */ -#define OFFS_CS 42 /* 16bit */ -#define OFFS_FLAGS 44 /* 16bit */ - -#define SEGMENT 0x40 -#define STACK 0x800 /* stack at 0x40:0x800 -> 0x800 */ - -/* save general registers */ -/* save some segments */ -/* save callers stack segment .. */ -/* ... in gs */ - /* setup my segments */ - /* setup BIOS stackpointer */ - -#define MAKE_BIOS_STACK \ - pushal ; \ - pushw %ds ; \ - pushw %gs ; \ - pushw %es ; \ - pushw %ss ; \ - popw %gs ; \ - movw $SEGMENT,%ax ; \ - movw %ax,%ds ; \ - movw %ax,%es ; \ - movw %ax,%ss ; \ - movw %sp,%bp ; \ - movw $STACK,%sp - -#define RESTORE_CALLERS_STACK \ - pushw %gs ; /* restore callers stack segment */ \ - popw %ss ; \ - movw %bp,%sp ; /* restore stackpointer */ \ - \ - popw %es ; /* restore segment selectors */ \ - popw %gs ; \ - popw %ds ; \ - \ - popal /* restore GP registers */ - -#endif diff --git a/lib_i386/bios_pci.S b/lib_i386/bios_pci.S deleted file mode 100644 index b57b726..0000000 --- a/lib_i386/bios_pci.S +++ /dev/null @@ -1,411 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * x86 realmode assembly implementation of a PCI BIOS - * for platforms that use one PCI hose and configuration - * access type 1. (The common case for low-end PC's) - */ - -#include "bios.h" - -#define PCI_BIOS_DEBUG - -.section .bios, "ax" -.code16 -.globl realmode_pci_bios_call_entry -realmode_pci_bios_call_entry: - MAKE_BIOS_STACK - call realmode_pci_bios - RESTORE_CALLERS_STACK - ret - - -.globl realmode_pci_bios -realmode_pci_bios: -gs movw OFFS_AX(%bp), %ax - cmpb $1, %al - je pci_bios_present - cmpb $2, %al - je pci_bios_find_device - cmpb $3, %al - je pci_bios_find_class - cmpb $6, %al - je pci_bios_generate_special_cycle - cmpb $8, %al - je pci_bios_read_cfg_byte - cmpb $9, %al - je pci_bios_read_cfg_word - cmpb $10, %al - je pci_bios_read_cfg_dword - cmpb $11, %al - je pci_bios_write_cfg_byte - cmpb $12, %al - je pci_bios_write_cfg_word - cmpb $13, %al - je pci_bios_write_cfg_dword - cmpb $14, %al - je pci_bios_get_irq_routing - cmpb $15, %al - je pci_bios_set_irq - jmp unknown_function - -/*****************************************************************************/ - -pci_bios_present: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_present -#endif - movl $0x20494350, %eax -gs movl %eax, OFFS_EDX(%bp) - movb $0x01, %al -gs movb %al, OFFS_AL(%bp) /* We support cfg type 1 */ - movw $0x0210, %ax /* version 2.10 */ -gs movw %ax, OFFS_BX(%bp) -cs movb pci_last_bus, %al /* last bus number */ -gs movb %al, OFFS_CL(%bp) - jmp clear_carry - -/*****************************************************************************/ - -/* device 0-31, function 0-7 */ -pci_bios_find_device: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_find_device -#endif -gs movw OFFS_CX(%bp), %di - shll $16, %edi -gs movw OFFS_DX(%bp), %di /* edi now holds device in upper 16 - * bits and vendor in lower 16 bits */ -gs movw OFFS_SI(%bp), %si - xorw %bx, %bx /* start at bus 0 dev 0 function 0 */ -pfd_loop: - xorw %ax, %ax /* dword 0 is vendor/device */ - call __pci_bios_select_register - movw $0xcfc, %dx - inl %dx, %eax - cmpl %edi, %eax /* our device ? */ - je pfd_found_one -pfd_next_dev: - /* check for multi function devices */ - movw %bx, %ax - andw $3, %ax - jnz pfd_function_not_zero - movw $0x000c, %ax - call __pci_bios_select_register - movw $0xcfe, %dx - inb %dx, %al - andb $0x80, %al - jz pfd_not_multi_function -pfd_function_not_zero: - incw %bx /* next function, overflows in to - * device number, then bus number */ - jmp pfd_check_bus - -pfd_not_multi_function: - andw $0xfff8, %bx /* remove function bits */ - addw $0x0008, %bx /* next device, overflows in to bus number */ -pfd_check_bus: -cs movb pci_last_bus, %ah - cmpb %ah, %bh - ja pfd_not_found - jmp pfd_loop -pfd_found_one: - decw %si - js pfd_done - jmp pfd_next_dev - -pfd_done: -gs movw %bx, OFFS_BX(%bp) - jmp clear_carry - -pfd_not_found: - movb $0x86, %ah /* device not found */ - jmp set_carry - -/*****************************************************************************/ - -pci_bios_find_class: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_find_class -#endif -gs movl OFFS_ECX(%bp), %edi - andl $0x00ffffff, %edi /* edi now holds class-code in lower 24 bits */ -gs movw OFFS_SI(%bp), %si - xorw %bx, %bx /* start at bus 0 dev 0 function 0 */ -pfc_loop: - movw $8, %ax /* dword 8 is class-code high 24bits */ - call __pci_bios_select_register - movw $0xcfc, %dx - inl %dx, %eax - shrl $8, %eax - andl $0x00ffffff, %eax - cmpl %edi, %eax /* our device ? */ - je pfc_found_one -pfc_next_dev: - /* check for multi function devices */ - andw $3, %bx - jnz pfc_function_not_zero - movw $0x000c, %ax - call __pci_bios_select_register - movw $0xcfe, %dx - inb %dx, %al - andb $0x80, %al - jz pfc_not_multi_function -pfc_function_not_zero: - incw %bx /* next function, overflows in to - * device number, then bus number */ - jmp pfc_check_bus - -pfc_not_multi_function: - andw $0xfff8, %bx /* remove function bits */ - addw $0x0008, %bx /* next device, overflows in to bus number */ -pfc_check_bus: -cs movb pci_last_bus, %ah - cmpb %ah, %bh - ja pfc_not_found - jmp pfc_loop -pfc_found_one: - decw %si - js pfc_done - jmp pfc_next_dev - -pfc_done: -gs movw %bx, OFFS_BX(%bp) - jmp clear_carry - -pfc_not_found: - movb $0x86, %ah /* device not found */ - jmp set_carry - -/*****************************************************************************/ - -pci_bios_generate_special_cycle: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_generate_special_cycle -#endif - movb $0x81, %ah /* function not supported */ - jmp set_carry - -/*****************************************************************************/ - -pci_bios_read_cfg_byte: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_read_cfg_byte -#endif - call pci_bios_select_register -gs movw OFFS_DI(%bp), %dx - andw $3, %dx - addw $0xcfc, %dx - inb %dx, %al -gs movb %al, OFFS_CL(%bp) - jmp clear_carry - -/*****************************************************************************/ - -pci_bios_read_cfg_word: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_read_cfg_word -#endif - call pci_bios_select_register -gs movw OFFS_DI(%bp), %dx - andw $2, %dx - addw $0xcfc, %dx - inw %dx, %ax -gs movw %ax, OFFS_CX(%bp) - jmp clear_carry - - -/*****************************************************************************/ - -pci_bios_read_cfg_dword: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_read_cfg_dword -#endif - call pci_bios_select_register - movw $0xcfc, %dx - inl %dx, %eax -gs movl %eax, OFFS_ECX(%bp) - jmp clear_carry - -/*****************************************************************************/ - -pci_bios_write_cfg_byte: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_write_cfg_byte -#endif - call pci_bios_select_register -gs movw OFFS_DI(%bp), %dx -gs movb OFFS_CL(%bp), %al - andw $3, %dx - addw $0xcfc, %dx - outb %al, %dx - jmp clear_carry - -/*****************************************************************************/ - -pci_bios_write_cfg_word: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_write_cfg_word -#endif - call pci_bios_select_register -gs movw OFFS_DI(%bp), %dx -gs movw OFFS_CX(%bp), %ax - andw $2, %dx - addw $0xcfc, %dx - outw %ax, %dx - jmp clear_carry - -/*****************************************************************************/ - -pci_bios_write_cfg_dword: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_write_cfg_dword -#endif - call pci_bios_select_register -gs movl OFFS_ECX(%bp), %eax - movw $0xcfc, %dx - outl %eax, %dx - jmp clear_carry - -/*****************************************************************************/ - -pci_bios_get_irq_routing: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_get_irq_routing -#endif - movb $0x81, %ah /* function not supported */ - jmp set_carry - -/*****************************************************************************/ - -pci_bios_set_irq: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_set_irq -#endif - movb $0x81, %ah /* function not supported */ - jmp set_carry - -/*****************************************************************************/ - -unknown_function: -#ifdef PCI_BIOS_DEBUG -cs incl num_pci_bios_unknown_function -#endif - movb $0x81, %ah /* function not supported */ - jmp set_carry - -/*****************************************************************************/ - -pci_bios_select_register: -gs movw OFFS_BX(%bp), %bx -gs movw OFFS_DI(%bp), %ax -/* destroys eax, dx */ -__pci_bios_select_register: /* BX holds device id, AX holds register index */ - pushl %ebx - andl $0xfc, %eax - andl $0xffff, %ebx - shll $8, %ebx - orl %ebx, %eax - orl $0x80000000, %eax - movw $0xcf8, %dx - outl %eax, %dx - popl %ebx - ret - - -clear_carry: -gs movw OFFS_FLAGS(%bp), %ax - andw $0xfffe, %ax /* clear carry -- function succeeded */ -gs movw %ax, OFFS_FLAGS(%bp) - xorw %ax, %ax -gs movb %ah, OFFS_AH(%bp) - ret - -set_carry: -gs movb %ah, OFFS_AH(%bp) -gs movw OFFS_FLAGS(%bp), %ax - orw $1, %ax /* return carry -- function not supported */ -gs movw %ax, OFFS_FLAGS(%bp) - movw $-1, %ax - ret - -/*****************************************************************************/ - -.globl pci_last_bus -pci_last_bus: - .byte 0 - -#ifdef PCI_BIOS_DEBUG -.globl num_pci_bios_present -num_pci_bios_present: - .long 0 - -.globl num_pci_bios_find_device -num_pci_bios_find_device: - .long 0 - -.globl num_pci_bios_find_class -num_pci_bios_find_class: - .long 0 - -.globl num_pci_bios_generate_special_cycle -num_pci_bios_generate_special_cycle: - .long 0 - -.globl num_pci_bios_read_cfg_byte -num_pci_bios_read_cfg_byte: - .long 0 - -.globl num_pci_bios_read_cfg_word -num_pci_bios_read_cfg_word: - .long 0 - -.globl num_pci_bios_read_cfg_dword -num_pci_bios_read_cfg_dword: - .long 0 - -.globl num_pci_bios_write_cfg_byte -num_pci_bios_write_cfg_byte: - .long 0 - -.globl num_pci_bios_write_cfg_word -num_pci_bios_write_cfg_word: - .long 0 - -.globl num_pci_bios_write_cfg_dword -num_pci_bios_write_cfg_dword: - .long 0 - -.globl num_pci_bios_get_irq_routing -num_pci_bios_get_irq_routing: - .long 0 - -.globl num_pci_bios_set_irq -num_pci_bios_set_irq: - .long 0 - -.globl num_pci_bios_unknown_function -num_pci_bios_unknown_function: - .long 0 -#endif diff --git a/lib_i386/bios_setup.c b/lib_i386/bios_setup.c deleted file mode 100644 index bc97815..0000000 --- a/lib_i386/bios_setup.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -/* - * Partly based on msbios.c from rolo 1.6: - *---------------------------------------------------------------------- - * (C) Copyright 2000 - * Sysgo Real-Time Solutions GmbH - * Klein-Winternheim, Germany - *---------------------------------------------------------------------- - */ - -#include -#include -#include -#include - -#define NUMVECTS 256 - -#define BIOS_DATA ((char*)0x400) -#define BIOS_DATA_SIZE 256 -#define BIOS_BASE ((char*)0xf0000) -#define BIOS_CS 0xf000 - -/* these are defined in a 16bit segment and needs - * to be accessed with the RELOC_16_xxxx() macros below - */ -extern u16 ram_in_64kb_chunks; -extern u16 bios_equipment; -extern u8 pci_last_bus; - -extern void *rm_int00; -extern void *rm_int01; -extern void *rm_int02; -extern void *rm_int03; -extern void *rm_int04; -extern void *rm_int05; -extern void *rm_int06; -extern void *rm_int07; -extern void *rm_int08; -extern void *rm_int09; -extern void *rm_int0a; -extern void *rm_int0b; -extern void *rm_int0c; -extern void *rm_int0d; -extern void *rm_int0e; -extern void *rm_int0f; -extern void *rm_int10; -extern void *rm_int11; -extern void *rm_int12; -extern void *rm_int13; -extern void *rm_int14; -extern void *rm_int15; -extern void *rm_int16; -extern void *rm_int17; -extern void *rm_int18; -extern void *rm_int19; -extern void *rm_int1a; -extern void *rm_int1b; -extern void *rm_int1c; -extern void *rm_int1d; -extern void *rm_int1e; -extern void *rm_int1f; -extern void *rm_def_int; - -extern void *realmode_reset; -extern void *realmode_pci_bios_call_entry; - -static int set_jmp_vector(int entry_point, void *target) -{ - if (entry_point & ~0xffff) { - return -1; - } - - if (((u32)target-0xf0000) & ~0xffff) { - return -1; - } - printf("set_jmp_vector: 0xf000:%04x -> %p\n", - entry_point, target); - - /* jmp opcode */ - writeb(0xea, 0xf0000 + entry_point); - - /* offset */ - writew(((u32)target-0xf0000), 0xf0000 + entry_point + 1); - - /* segment */ - writew(0xf000, 0xf0000 + entry_point + 3); - - return 0; -} - - -/* - ************************************************************ - * Install an interrupt vector - ************************************************************ - */ - -static void setvector(int vector, u16 segment, void *handler) -{ - u16 *ptr = (u16*)(vector*4); - ptr[0] = ((u32)handler - (segment << 4))&0xffff; - ptr[1] = segment; - -#if 0 - printf("setvector: int%02x -> %04x:%04x\n", - vector, ptr[1], ptr[0]); -#endif -} - -#define RELOC_16_LONG(seg, off) *(u32*)(seg << 4 | (u32)&off) -#define RELOC_16_WORD(seg, off) *(u16*)(seg << 4 | (u32)&off) -#define RELOC_16_BYTE(seg, off) *(u8*)(seg << 4 | (u32)&off) - -int bios_setup(void) -{ - DECLARE_GLOBAL_DATA_PTR; - static int done=0; - int vector; - struct pci_controller *pri_hose; - - if (done) { - return 0; - } - done = 1; - - if (i386boot_bios_size > 65536) { - printf("BIOS too large (%ld bytes, max is 65536)\n", - i386boot_bios_size); - return -1; - } - - memcpy(BIOS_BASE, (void*)i386boot_bios, i386boot_bios_size); - - /* clear bda */ - memset(BIOS_DATA, 0, BIOS_DATA_SIZE); - - /* enter some values to the bda */ - writew(0x3f8, BIOS_DATA); /* com1 addr */ - writew(0x2f8, BIOS_DATA+2); /* com2 addr */ - writew(0x3e8, BIOS_DATA+4); /* com3 addr */ - writew(0x2e8, BIOS_DATA+6); /* com4 addr */ - writew(0x278, BIOS_DATA+8); /* lpt1 addr */ - /* - * The kernel wants to read the base memory size - * from 40:13. Put a zero there to avoid an error message - */ - writew(0, BIOS_DATA+0x13); /* base memory size */ - - - /* setup realmode interrupt vectors */ - for (vector = 0; vector < NUMVECTS; vector++) { - setvector(vector, BIOS_CS, &rm_def_int); - } - - setvector(0x00, BIOS_CS, &rm_int00); - setvector(0x01, BIOS_CS, &rm_int01); - setvector(0x02, BIOS_CS, &rm_int02); - setvector(0x03, BIOS_CS, &rm_int03); - setvector(0x04, BIOS_CS, &rm_int04); - setvector(0x05, BIOS_CS, &rm_int05); - setvector(0x06, BIOS_CS, &rm_int06); - setvector(0x07, BIOS_CS, &rm_int07); - setvector(0x08, BIOS_CS, &rm_int08); - setvector(0x09, BIOS_CS, &rm_int09); - setvector(0x0a, BIOS_CS, &rm_int0a); - setvector(0x0b, BIOS_CS, &rm_int0b); - setvector(0x0c, BIOS_CS, &rm_int0c); - setvector(0x0d, BIOS_CS, &rm_int0d); - setvector(0x0e, BIOS_CS, &rm_int0e); - setvector(0x0f, BIOS_CS, &rm_int0f); - setvector(0x10, BIOS_CS, &rm_int10); - setvector(0x11, BIOS_CS, &rm_int11); - setvector(0x12, BIOS_CS, &rm_int12); - setvector(0x13, BIOS_CS, &rm_int13); - setvector(0x14, BIOS_CS, &rm_int14); - setvector(0x15, BIOS_CS, &rm_int15); - setvector(0x16, BIOS_CS, &rm_int16); - setvector(0x17, BIOS_CS, &rm_int17); - setvector(0x18, BIOS_CS, &rm_int18); - setvector(0x19, BIOS_CS, &rm_int19); - setvector(0x1a, BIOS_CS, &rm_int1a); - setvector(0x1b, BIOS_CS, &rm_int1b); - setvector(0x1c, BIOS_CS, &rm_int1c); - setvector(0x1d, BIOS_CS, &rm_int1d); - setvector(0x1e, BIOS_CS, &rm_int1e); - setvector(0x1f, BIOS_CS, &rm_int1f); - - set_jmp_vector(0xfff0, &realmode_reset); - set_jmp_vector(0xfe6e, &realmode_pci_bios_call_entry); - - /* fill in data area */ - RELOC_16_WORD(0xf000, ram_in_64kb_chunks) = gd->ram_size >> 16; - RELOC_16_WORD(0xf000, bios_equipment) = 0; /* FixMe */ - - /* If we assume only one PCI hose, this PCI hose - * will own PCI bus #0, and the last PCI bus of - * that PCI hose will be the last PCI bus in the - * system. - * (This, ofcause break on multi hose systems, - * but our PCI BIOS only support one hose anyway) - */ - pri_hose = pci_bus_to_hose(0); - if (NULL != pri_hose) { - /* fill in last pci bus number for use by the realmode - * PCI BIOS */ - RELOC_16_BYTE(0xf000, pci_last_bus) = pri_hose->last_busno; - } - - return 0; -} diff --git a/lib_i386/board.c b/lib_i386/board.c deleted file mode 100644 index e90eb6e..0000000 --- a/lib_i386/board.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern long _i386boot_start; -extern long _i386boot_end; -extern long _i386boot_romdata_start; -extern long _i386boot_romdata_dest; -extern long _i386boot_romdata_size; -extern long _i386boot_bss_start; -extern long _i386boot_bss_size; - -extern long _i386boot_realmode; -extern long _i386boot_realmode_size; -extern long _i386boot_bios; -extern long _i386boot_bios_size; - -/* The symbols defined by the linker script becomes pointers - * which is somewhat inconveient ... */ -ulong i386boot_start = (ulong)&_i386boot_start; /* code start (in flash) defined in start.S */ -ulong i386boot_end = (ulong)&_i386boot_end; /* code end (in flash) */ -ulong i386boot_romdata_start = (ulong)&_i386boot_romdata_start; /* datasegment in flash (also code+rodata end) */ -ulong i386boot_romdata_dest = (ulong)&_i386boot_romdata_dest; /* data location segment in ram */ -ulong i386boot_romdata_size = (ulong)&_i386boot_romdata_size; /* size of data segment */ -ulong i386boot_bss_start = (ulong)&_i386boot_bss_start; /* bss start */ -ulong i386boot_bss_size = (ulong)&_i386boot_bss_size; /* bss size */ - -ulong i386boot_realmode = (ulong)&_i386boot_realmode; /* start of realmode entry code */ -ulong i386boot_realmode_size = (ulong)&_i386boot_realmode_size; /* size of realmode entry code */ -ulong i386boot_bios = (ulong)&_i386boot_bios; /* start of BIOS emulation code */ -ulong i386boot_bios_size = (ulong)&_i386boot_bios_size; /* size of BIOS emulation code */ - - -const char version_string[] = - U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"; - - -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - -static int mem_malloc_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* start malloc area right after the stack */ - mem_malloc_start = i386boot_bss_start + - i386boot_bss_size + CFG_STACK_SIZE; - mem_malloc_start = (mem_malloc_start+3)&~3; - - /* Use all available RAM for malloc() */ - mem_malloc_end = gd->ram_size; - - mem_malloc_brk = mem_malloc_start; - - return 0; -} - -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - - return ((void *) old); -} - -char *strmhz (char *buf, long hz) -{ - long l, n; - long m; - - n = hz / 1000000L; - l = sprintf (buf, "%ld", n); - m = (hz % 1000000L) / 1000L; - if (m != 0) - sprintf (buf + l, ".%03ld", m); - return (buf); -} - -/************************************************************************ - * Init Utilities * - ************************************************************************ - * Some of this code should be moved into the core functions, - * or dropped completely, - * but let's get it working (again) first... - */ -static int init_baudrate (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - char tmp[64]; /* long enough for environment variables */ - int i = getenv_r("baudrate", tmp, 64); - - gd->baudrate = (i != 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CONFIG_BAUDRATE; - - return (0); -} - -static int display_banner (void) -{ - - printf ("\n\n%s\n\n", version_string); - printf ("U-Boot code: %08lX -> %08lX data: %08lX -> %08lX\n" - " BSS: %08lX -> %08lX stack: %08lX -> %08lX\n", - i386boot_start, i386boot_romdata_start-1, - i386boot_romdata_dest, i386boot_romdata_dest+i386boot_romdata_size-1, - i386boot_bss_start, i386boot_bss_start+i386boot_bss_size-1, - i386boot_bss_start+i386boot_bss_size, - i386boot_bss_start+i386boot_bss_size+CFG_STACK_SIZE-1); - - - return (0); -} - -/* - * WARNING: this code looks "cleaner" than the PowerPC version, but - * has the disadvantage that you either get nothing, or everything. - * On PowerPC, you might see "DRAM: " before the system hangs - which - * gives a simple yet clear indication which part of the - * initialization if failing. - */ -static int display_dram_config (void) -{ - DECLARE_GLOBAL_DATA_PTR; - int i; - - puts ("DRAM Configuration:\n"); - - for (i=0; ibd->bi_dram[i].start); - print_size (gd->bd->bi_dram[i].size, "\n"); - } - - return (0); -} - -static void display_flash_config (ulong size) -{ - puts ("Flash: "); - print_size (size, "\n"); -} - - -/* - * Breath some life into the board... - * - * Initialize an SMC for serial comms, and carry out some hardware - * tests. - * - * The first part of initialization is running from Flash memory; - * its main purpose is to initialize the RAM so that we - * can relocate the monitor code to RAM. - */ - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ -typedef int (init_fnc_t) (void); - -init_fnc_t *init_sequence[] = { - cpu_init, /* basic cpu dependent setup */ - board_init, /* basic board dependent setup */ - dram_init, /* configure available RAM banks */ - mem_malloc_init, /* dependant on dram_init */ - interrupt_init, /* set up exceptions */ - timer_init, - serial_init, - env_init, /* initialize environment */ - init_baudrate, /* initialze baudrate settings */ - serial_init, /* serial communications setup */ - display_banner, - display_dram_config, - - NULL, -}; - -gd_t *global_data; - -void start_i386boot (void) -{ - DECLARE_GLOBAL_DATA_PTR; - char *s; - int i; - ulong size; - static gd_t gd_data; - static bd_t bd_data; - init_fnc_t **init_fnc_ptr; - - show_boot_progress(0x21); - - gd = global_data = &gd_data; - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); - - memset (gd, 0, sizeof (gd_t)); - gd->bd = &bd_data; - memset (gd->bd, 0, sizeof (bd_t)); - show_boot_progress(0x22); - - gd->baudrate = CONFIG_BAUDRATE; - - for (init_fnc_ptr = init_sequence, i=0; *init_fnc_ptr; ++init_fnc_ptr, i++) { - show_boot_progress(0xa130|i); - - if ((*init_fnc_ptr)() != 0) { - hang (); - } - } - show_boot_progress(0x23); - - /* configure available FLASH banks */ - size = flash_init(); - display_flash_config(size); - show_boot_progress(0x24); - - show_boot_progress(0x25); - - /* initialize environment */ - env_relocate (); - show_boot_progress(0x26); - - - /* IP Address */ - bd_data.bi_ip_addr = getenv_IPaddr ("ipaddr"); - - /* MAC Address */ - { - int i; - ulong reg; - char *s, *e; - uchar tmp[64]; - - i = getenv_r ("ethaddr", tmp, sizeof (tmp)); - s = (i > 0) ? tmp : NULL; - - for (reg = 0; reg < 6; ++reg) { - bd_data.bi_enetaddr[reg] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - } - -#if defined(CONFIG_PCI) - /* - * Do pci configuration - */ - pci_init(); -#endif - - show_boot_progress(0x27); - - - devices_init (); - - jumptable_init (); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r(); - -#ifdef CONFIG_MISC_INIT_R - /* miscellaneous platform dependent initialisations */ - misc_init_r(); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE) - WATCHDOG_RESET(); - puts ("PCMCIA:"); - pcmcia_init(); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - WATCHDOG_RESET(); - puts("KGDB: "); - kgdb_init(); -#endif - - /* enable exceptions */ - enable_interrupts(); - show_boot_progress(0x28); - - /* Must happen after interrupts are initialized since - * an irq handler gets installed - */ -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - serial_buffered_init(); -#endif - -#ifdef CONFIG_STATUS_LED - status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); -#endif - - udelay(20); - - set_timer (0); - - /* Initialize from environment */ - if ((s = getenv ("loadaddr")) != NULL) { - load_addr = simple_strtoul (s, NULL, 16); - } -#if (CONFIG_COMMANDS & CFG_CMD_NET) - if ((s = getenv ("bootfile")) != NULL) { - copy_filename (BootFile, s, sizeof (BootFile)); - } -#endif /* CFG_CMD_NET */ - - WATCHDOG_RESET(); - -#if (CONFIG_COMMANDS & CFG_CMD_IDE) - WATCHDOG_RESET(); - puts("IDE: "); - ide_init(); -#endif /* CFG_CMD_IDE */ - -#if (CONFIG_COMMANDS & CFG_CMD_SCSI) - WATCHDOG_RESET(); - puts("SCSI: "); - scsi_init(); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) - WATCHDOG_RESET(); - puts("DOC: "); - doc_init(); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NET) -#if defined(CONFIG_NET_MULTI) - WATCHDOG_RESET(); - puts("Net: "); -#endif - eth_initialize(gd->bd); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && (0) - WATCHDOG_RESET(); -# ifdef DEBUG - puts ("Reset Ethernet PHY\n"); -# endif - reset_phy(); -#endif - -#ifdef CONFIG_LAST_STAGE_INIT - WATCHDOG_RESET(); - /* - * Some parts can be only initialized if all others (like - * Interrupts) are up and running (i.e. the PC-style ISA - * keyboard). - */ - last_stage_init(); -#endif - - -#ifdef CONFIG_POST - post_run (NULL, POST_RAM | post_bootmode_get(0)); -#endif - - - show_boot_progress(0x29); - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) { - main_loop(); - } - - /* NOTREACHED - no way out of command loop except booting */ -} - -void hang (void) -{ - puts ("### ERROR ### Please RESET the board ###\n"); - for (;;); -} diff --git a/lib_i386/i386_linux.c b/lib_i386/i386_linux.c deleted file mode 100644 index e5d8eea..0000000 --- a/lib_i386/i386_linux.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include -#include - -/*cmd_boot.c*/ -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -extern image_header_t header; /* from cmd_bootm.c */ - - -image_header_t *fake_header(image_header_t *hdr, void *ptr, int size) -{ - /* try each supported image type in order */ - if (NULL != fake_zimage_header(hdr, ptr, size)) { - return hdr; - } - - return NULL; -} - - -void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], - ulong addr, ulong *len_ptr, int verify) -{ - void *base_ptr; - - ulong len = 0, checksum; - ulong initrd_start, initrd_end; - ulong data; - image_header_t *hdr = &header; - - /* - * Check if there is an initrd image - */ - if (argc >= 3) { - addr = simple_strtoul(argv[2], NULL, 16); - - printf ("## Loading Ramdisk Image at %08lx ...\n", addr); - - /* Copy header so we can blank CRC field for re-calculation */ - memcpy (&header, (char *)addr, sizeof(image_header_t)); - - if (ntohl(hdr->ih_magic) != IH_MAGIC) { - printf ("Bad Magic Number\n"); - do_reset (cmdtp, flag, argc, argv); - } - - data = (ulong)&header; - len = sizeof(image_header_t); - - checksum = ntohl(hdr->ih_hcrc); - hdr->ih_hcrc = 0; - - if (crc32 (0, (char *)data, len) != checksum) { - printf ("Bad Header Checksum\n"); - do_reset (cmdtp, flag, argc, argv); - } - - print_image_hdr (hdr); - - data = addr + sizeof(image_header_t); - len = ntohl(hdr->ih_size); - - if (verify) { - ulong csum = 0; - - printf (" Verifying Checksum ... "); - csum = crc32 (0, (char *)data, len); - if (csum != ntohl(hdr->ih_dcrc)) { - printf ("Bad Data CRC\n"); - do_reset (cmdtp, flag, argc, argv); - } - printf ("OK\n"); - } - - if ((hdr->ih_os != IH_OS_LINUX) || - (hdr->ih_arch != IH_CPU_I386) || - (hdr->ih_type != IH_TYPE_RAMDISK) ) { - printf ("No Linux i386 Ramdisk Image\n"); - do_reset (cmdtp, flag, argc, argv); - } - - /* - * Now check if we have a multifile image - */ - } else if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1])) { - ulong tail = ntohl(len_ptr[0]) % 4; - int i; - - /* skip kernel length and terminator */ - data = (ulong)(&len_ptr[2]); - /* skip any additional image length fields */ - for (i=1; len_ptr[i]; ++i) - data += 4; - /* add kernel length, and align */ - data += ntohl(len_ptr[0]); - if (tail) { - data += 4 - tail; - } - - len = ntohl(len_ptr[1]); - - } else { - /* - * no initrd image - */ - data = 0; - } - -#ifdef DEBUG - if (!data) { - printf ("No initrd\n"); - } -#endif - - if (data) { - initrd_start = data; - initrd_end = initrd_start + len; - printf (" Loading Ramdisk to %08lx, end %08lx ... ", - initrd_start, initrd_end); - memmove ((void *)initrd_start, (void *)data, len); - printf ("OK\n"); - } else { - initrd_start = 0; - initrd_end = 0; - } - - base_ptr = load_zimage((void*)addr + sizeof(image_header_t), ntohl(hdr->ih_size), - initrd_start, initrd_end-initrd_start, 0); - - if (NULL == base_ptr) { - printf ("## Kernel loading failed ...\n"); - do_reset(cmdtp, flag, argc, argv); - - } - -#ifdef DEBUG - printf ("## Transferring control to Linux (at address %08x) ...\n", - (u32)base_ptr); -#endif - - /* we assume that the kernel is in place */ - printf("\nStarting kernel ...\n\n"); - - boot_zimage(base_ptr); - -} diff --git a/lib_i386/pci.c b/lib_i386/pci.c deleted file mode 100644 index a7f16aa..0000000 --- a/lib_i386/pci.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#ifdef CONFIG_PCI -#undef PCI_ROM_SCAN_VERBOSE - -int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) -{ - struct pci_controller *hose; - int res = -1; - int i; - - u32 rom_addr; - u32 addr_reg; - u32 size; - - u16 vendor; - u16 device; - u32 class_code; - - hose = pci_bus_to_hose(PCI_BUS(dev)); -#if 0 - printf("pci_shadow_rom() asked to shadow device %x to %x\n", - dev, (u32)dest); -#endif - pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); - pci_read_config_word(dev, PCI_DEVICE_ID, &device); - pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_code); - - class_code &= 0xffffff00; - class_code >>= 8; - -#if 0 - printf("PCI Header Vendor %04x device %04x class %06x\n", - vendor, device, class_code); -#endif - /* Enable the rom addess decoder */ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, PCI_ROM_ADDRESS_MASK); - pci_read_config_dword(dev, PCI_ROM_ADDRESS, &addr_reg); - - if (!addr_reg) { - /* register unimplemented */ - printf("pci_chadow_rom: device do not seem to have a rom\n"); - return -1; - } - - size = (~(addr_reg&PCI_ROM_ADDRESS_MASK))+1; - -#if 0 - printf("ROM is %d bytes\n", size); -#endif - rom_addr = pci_get_rom_window(hose, size); -#if 0 - printf("ROM mapped at %x \n", rom_addr); -#endif - pci_write_config_dword(dev, PCI_ROM_ADDRESS, - pci_phys_to_mem(dev, rom_addr) - |PCI_ROM_ADDRESS_ENABLE); - - - for (i=rom_addr;i - -#ifdef CONFIG_PCI - -#include -#include - -#define cfg_read(val, addr, op) *val = op((int)(addr)) -#define cfg_write(val, addr, op) op((val), (int)(addr)) - -#define TYPE1_PCI_OP(rw, size, type, op, mask) \ -static int \ -type1_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - outl(dev | (offset & 0xfc) | 0x80000000, (int)hose->cfg_addr); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), op); \ - return 0; \ -} - - -TYPE1_PCI_OP(read, byte, u8 *, inb, 3) -TYPE1_PCI_OP(read, word, u16 *, inw, 2) -TYPE1_PCI_OP(read, dword, u32 *, inl, 0) - -TYPE1_PCI_OP(write, byte, u8, outb, 3) -TYPE1_PCI_OP(write, word, u16, outw, 2) -TYPE1_PCI_OP(write, dword, u32, outl, 0) - -void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) -{ - pci_set_ops(hose, - type1_read_config_byte, - type1_read_config_word, - type1_read_config_dword, - type1_write_config_byte, - type1_write_config_word, - type1_write_config_dword); - - hose->cfg_addr = (unsigned int *) cfg_addr; - hose->cfg_data = (unsigned char *) cfg_data; -} - -#endif diff --git a/lib_i386/realmode.c b/lib_i386/realmode.c deleted file mode 100644 index 6cf2738..0000000 --- a/lib_i386/realmode.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - - -#define REALMODE_BASE ((char*)0x7c0) -#define REALMODE_MAILBOX ((char*)0xe00) - - -extern char realmode_enter; - -int realmode_setup(void) -{ - /* copy the realmode switch code */ - if (i386boot_realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) { - printf("realmode switch too large (%ld bytes, max is %d)\n", - i386boot_realmode_size, (REALMODE_MAILBOX-REALMODE_BASE)); - return -1; - } - - memcpy(REALMODE_BASE, (void*)i386boot_realmode, i386boot_realmode_size); - asm("wbinvd\n"); - - return 0; -} - -int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out) -{ - - /* setup out thin bios emulation */ - if (bios_setup()) { - return -1; - } - - if (realmode_setup()) { - return -1; - } - - in->eip = off; - in->xcs = seg; - if (3>(in->esp & 0xffff)) { - printf("Warning: entering realmode with sp < 4 will fail\n"); - } - - memcpy(REALMODE_MAILBOX, in, sizeof(struct pt_regs)); - asm("wbinvd\n"); - - __asm__ volatile ( - "lcall $0x20,%0\n" : : "i" (&realmode_enter) ); - - asm("wbinvd\n"); - memcpy(out, REALMODE_MAILBOX, sizeof(struct pt_regs)); - - return out->eax; -} - - -/* This code is supposed to access a realmode interrupt - * it does currently not work for me */ -int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out) -{ - /* place two instructions at 0x700 */ - writeb(0xcd, 0x700); /* int $lvl */ - writeb(lvl, 0x701); - writeb(0xcb, 0x702); /* lret */ - asm("wbinvd\n"); - - enter_realmode(0x00, 0x700, in, out); - - return out->eflags&1; -} diff --git a/lib_i386/realmode_switch.S b/lib_i386/realmode_switch.S deleted file mode 100644 index 0433cd4..0000000 --- a/lib_i386/realmode_switch.S +++ /dev/null @@ -1,222 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -/* 32bit -> 16bit -> 32bit mode switch code */ - -/* - * Stack frame at 0xe00 - * e00 ebx; - * e04 ecx; - * e08 edx; - * e0c esi; - * e10 edi; - * e14 ebp; - * e18 eax; - * e1c ds; - * e20 es; - * e24 fs; - * e28 gs; - * e2c orig_eax; - * e30 eip; - * e34 cs; - * e38 eflags; - * e3c esp; - * e40 ss; - */ - -#define a32 .byte 0x67; /* address size prefix 32 */ -#define o32 .byte 0x66; /* operand size prefix 32 */ - -.section .realmode, "ax" -.code16 - /* 16bit protected mode code here */ -.globl realmode_enter -realmode_enter: -o32 pusha -o32 pushf - cli - sidt saved_idt - sgdt saved_gdt - movl %esp, %eax - movl %eax, saved_protected_mode_esp - - movl $0x10, %eax - movl %eax, %esp - movw $0x28, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %fs - movw %ax, %gs - - lidt realmode_idt_ptr - movl %cr0, %eax /* Go back into real mode by */ - andl $0x7ffffffe, %eax /* clearing PE to 0 */ - movl %eax, %cr0 - ljmp $0x0,$do_realmode /* switch to real mode */ - -do_realmode: /* realmode code from here */ - movw %cs,%ax - movw %ax,%ds - movw %ax,%es - movw %ax,%fs - movw %ax,%gs - - /* create a temporary stack */ - - movw $0xc0, %ax - movw %ax, %ss - movw $0x200, %ax - movw %ax, %sp - - popl %ebx - popl %ecx - popl %edx - popl %esi - popl %edi - popl %ebp - popl %eax - movl %eax, temp_eax - popl %eax - movw %ax, %ds - popl %eax - movw %ax, %es - popl %eax - movw %ax, %fs - popl %eax - movw %ax, %gs - popl %eax /* orig_eax */ - popl %eax -cs movw %ax, temp_ip - popl %eax -cs movw %ax, temp_cs -o32 popf - popl %eax - popw %ss - movl %eax, %esp -cs movl temp_eax, %eax - wbinvd /* self-modifying code, - * better flush the cache */ - - .byte 0x9a /* lcall */ -temp_ip: - .word 0 /* new ip */ -temp_cs: - .word 0 /* new cs */ -realmode_ret: - /* save eax, esp and ss */ -cs movl %eax, saved_eax - movl %esp, %eax -cs movl %eax, saved_esp - movw %ss, %ax -cs movw %ax, saved_ss - - /* restore the stack, note that we set sp to 0x244; - * pt_regs is 0x44 bytes long and we push the structure - * backwards on to the stack, bottom first */ - - movw $0xc0, %ax - movw %ax, %ss - movw $0x244, %ax - movw %ax, %sp - - xorl %eax,%eax -cs movw saved_ss, %ax - pushl %eax -cs movl saved_esp, %eax - pushl %eax -o32 pushf - xorl %eax,%eax -cs movw temp_cs, %ax - pushl %eax -cs movw temp_ip, %ax - pushl %eax - pushl $0 - movw %gs, %ax - pushl %eax - movw %fs, %ax - pushl %eax - movw %es, %ax - pushl %eax - movw %ds, %ax - pushl %eax - movl saved_eax, %eax - pushl %eax - pushl %ebp - pushl %edi - pushl %esi - pushl %edx - pushl %ecx - pushl %ebx - -o32 cs lidt saved_idt -o32 cs lgdt saved_gdt /* Set GDTR */ - - movl %cr0, %eax /* Go back into protected mode */ - orl $1,%eax /* reset PE to 1 */ - movl %eax, %cr0 - jmp next_line /* flush prefetch queue */ -next_line: - movw $return_ptr, %ax - movw %ax,%bp -o32 cs ljmp *(%bp) - -.code32 -protected_mode: - movl $0x18,%eax /* reload GDT[3] */ - movw %ax,%fs /* reset FS */ - movw %ax,%ds /* reset DS */ - movw %ax,%gs /* reset GS */ - movw %ax,%es /* reset ES */ - movw %ax,%ss /* reset SS */ - movl saved_protected_mode_esp, %eax - movl %eax, %esp - popf - popa - ret - -temp_eax: - .long 0 - -saved_ss: - .word 0 -saved_esp: - .long 0 -saved_eax: - .long 0 - -realmode_idt_ptr: - .word 0x400 - .word 0x0, 0x0 - -saved_gdt: - .word 0, 0, 0, 0 -saved_idt: - .word 0, 0, 0, 0 - -saved_protected_mode_esp: - .long 0 - -return_ptr: - .long protected_mode - .word 0x10 diff --git a/lib_i386/video.c b/lib_i386/video.c deleted file mode 100644 index cd89457..0000000 --- a/lib_i386/video.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include - - -/* basic textmode I/O from linux kernel */ -static char *vidmem = (char *)0xb8000; -static int vidport; -static int lines, cols; -static int orig_x, orig_y; - -static void beep(int dur) -{ - int i; - - outb_p(3, 0x61); - for (i=0;i<10*dur;i++) { - udelay(1000); - } - outb_p(0, 0x61); -} - -static void scroll(void) -{ - int i; - - memcpy ( vidmem, vidmem + cols * 2, ( lines - 1 ) * cols * 2 ); - for ( i = ( lines - 1 ) * cols * 2; i < lines * cols * 2; i += 2 ) - vidmem[i] = ' '; -} - -static void __video_putc(const char c, int *x, int *y) -{ - if (c == '\n') { - (*x) = 0; - if ( ++(*y) >= lines ) { - scroll(); - (*y)--; - } - } else if (c == '\b') { - if ((*x) != 0) { - --(*x); - vidmem [ ( (*x) + cols * (*y) ) * 2 ] = ' '; - } - } else if (c == '\r') { - (*x) = 0; - - } else if (c == '\a') { - beep(3); - - } else if (c == '\t') { - __video_putc(' ', x, y); - __video_putc(' ', x, y); - __video_putc(' ', x, y); - __video_putc(' ', x, y); - __video_putc(' ', x, y); - __video_putc(' ', x, y); - __video_putc(' ', x, y); - __video_putc(' ', x, y); - } else if (c == '\v') { - switch ((*x) % 8) { - case 0: - __video_putc(' ', x, y); - case 7: - __video_putc(' ', x, y); - case 6: - __video_putc(' ', x, y); - case 5: - __video_putc(' ', x, y); - case 4: - __video_putc(' ', x, y); - case 3: - __video_putc(' ', x, y); - case 2: - __video_putc(' ', x, y); - case 1: - __video_putc(' ', x, y); - } - } else if (c == '\f') { - int i; - for (i=0;i= cols ) { - (*x) = 0; - if ( ++(*y) >= lines ) { - scroll(); - (*y)--; - } - } - } -} - -static void video_putc(const char c) -{ - int x,y,pos; - - x = orig_x; - y = orig_y; - - __video_putc(c, &x, &y); - - orig_x = x; - orig_y = y; - - pos = (x + cols * y) * 2; /* Update cursor position */ - outb_p(14, vidport); - outb_p(0xff & (pos >> 9), vidport+1); - outb_p(15, vidport); - outb_p(0xff & (pos >> 1), vidport+1); -} - -static void video_puts(const char *s) -{ - int x,y,pos; - char c; - - x = orig_x; - y = orig_y; - - while ( ( c = *s++ ) != '\0' ) { - __video_putc(c, &x, &y); - } - - orig_x = x; - orig_y = y; - - pos = (x + cols * y) * 2; /* Update cursor position */ - outb_p(14, vidport); - outb_p(0xff & (pos >> 9), vidport+1); - outb_p(15, vidport); - outb_p(0xff & (pos >> 1), vidport+1); -} - -int video_init(void) -{ - u16 pos; - - static device_t vga_dev; - static device_t kbd_dev; - - vidmem = (char *) 0xb8000; - vidport = 0x3d4; - - lines = 25; - cols = 80; - - outb_p(14, vidport); - pos = inb_p(vidport+1); - pos <<= 8; - outb_p(15, vidport); - pos |= inb_p(vidport+1); - - orig_x = pos%cols; - orig_y = pos/cols; - -#if 0 - printf("pos %x %d %d\n", pos, orig_x, orig_y); -#endif - if (orig_y > lines) { - orig_x = orig_y =0; - } - - - memset(&vga_dev, 0, sizeof(vga_dev)); - strcpy(vga_dev.name, "vga"); - vga_dev.ext = 0; - vga_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; - vga_dev.putc = video_putc; /* 'putc' function */ - vga_dev.puts = video_puts; /* 'puts' function */ - vga_dev.tstc = NULL; /* 'tstc' function */ - vga_dev.getc = NULL; /* 'getc' function */ - - if (device_register(&vga_dev) == 0) { - return 1; - } - - if (i8042_kbd_init()) { - return 1; - } - - memset(&kbd_dev, 0, sizeof(kbd_dev)); - strcpy(kbd_dev.name, "kbd"); - kbd_dev.ext = 0; - kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbd_dev.putc = NULL; /* 'putc' function */ - kbd_dev.puts = NULL; /* 'puts' function */ - kbd_dev.tstc = i8042_tstc; /* 'tstc' function */ - kbd_dev.getc = i8042_getc; /* 'getc' function */ - - if (device_register(&kbd_dev) == 0) { - return 1; - } - return 0; -} - - -int drv_video_init(void) -{ - if (video_bios_init()) { - return 1; - } - - return video_init(); -} diff --git a/lib_i386/video_bios.c b/lib_i386/video_bios.c deleted file mode 100644 index 45f78e2..0000000 --- a/lib_i386/video_bios.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#undef PCI_BIOS_DEBUG -#undef VGA_BIOS_DEBUG - -#ifdef VGA_BIOS_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -#ifdef CONFIG_PCI - -#ifdef PCI_BIOS_DEBUG -#define RELOC_16(seg, off) *(u32*)(seg << 4 | (u32)&off) -extern u32 num_pci_bios_present; -extern u32 num_pci_bios_find_device; -extern u32 num_pci_bios_find_class; -extern u32 num_pci_bios_generate_special_cycle; -extern u32 num_pci_bios_read_cfg_byte; -extern u32 num_pci_bios_read_cfg_word; -extern u32 num_pci_bios_read_cfg_dword; -extern u32 num_pci_bios_write_cfg_byte; -extern u32 num_pci_bios_write_cfg_word; -extern u32 num_pci_bios_write_cfg_dword; -extern u32 num_pci_bios_get_irq_routing; -extern u32 num_pci_bios_set_irq; -extern u32 num_pci_bios_unknown_function; - -void print_bios_bios_stat(void) -{ - printf("16 bit functions:\n"); - printf("pci_bios_present: %d\n", RELOC_16(0xf000, num_pci_bios_present)); - printf("pci_bios_find_device: %d\n", RELOC_16(0xf000, num_pci_bios_find_device)); - printf("pci_bios_find_class: %d\n", RELOC_16(0xf000, num_pci_bios_find_class)); - printf("pci_bios_generate_special_cycle: %d\n", RELOC_16(0xf000, num_pci_bios_generate_special_cycle)); - printf("pci_bios_read_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_byte)); - printf("pci_bios_read_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_word)); - printf("pci_bios_read_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_read_cfg_dword)); - printf("pci_bios_write_cfg_byte: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_byte)); - printf("pci_bios_write_cfg_word: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_word)); - printf("pci_bios_write_cfg_dword: %d\n", RELOC_16(0xf000, num_pci_bios_write_cfg_dword)); - printf("pci_bios_get_irq_routing: %d\n", RELOC_16(0xf000, num_pci_bios_get_irq_routing)); - printf("pci_bios_set_irq: %d\n", RELOC_16(0xf000, num_pci_bios_set_irq)); - printf("pci_bios_unknown_function: %d\n", RELOC_16(0xf000, num_pci_bios_unknown_function)); - -} -#endif - -#define PCI_CLASS_VIDEO 3 -#define PCI_CLASS_VIDEO_STD 0 -#define PCI_CLASS_VIDEO_PROG_IF_VGA 0 - - -static u32 probe_pci_video(void) -{ - pci_dev_t devbusfn; - - if ((devbusfn = pci_find_class(PCI_CLASS_VIDEO, - PCI_CLASS_VIDEO_STD, - PCI_CLASS_VIDEO_PROG_IF_VGA, 0)) != -1) { - u32 old; - u32 addr; - - /* PCI video device detected */ - printf("Found PCI VGA device at %02x.%02x.%x\n", - PCI_BUS(devbusfn), PCI_DEV(devbusfn), PCI_FUNC(devbusfn)); - - /* Enable I/O decoding as well, PCI viudeo boards - * support I/O accesses, but they provide no - * bar register for this since the ports are fixed. - */ - pci_write_config_word(devbusfn, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER); - - /* Test the ROM decoder, do the device support a rom? */ - pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old); - pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, PCI_ROM_ADDRESS_MASK); - pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr); - pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old); - - if (!addr) { - printf("PCI VGA have no ROM?\n"); - return 0; - } - - /* device have a rom */ - if (pci_shadow_rom(devbusfn, (void*)0xc0000)) { - printf("Shadowing of PCI VGA BIOS failed\n"); - return 0; - } - - /* Now enable lagacy VGA port access */ - if (pci_enable_legacy_video_ports(pci_bus_to_hose(PCI_BUS(devbusfn)))) { - printf("PCI VGA enable failed\n"); - return 0; - } - - - /* return the pci device info, that we'll need later */ - return PCI_BUS(devbusfn) << 8 | - PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn)&7); - } - - return 0; -} - - -#endif - -static int probe_isa_video(void) -{ - u32 ptr; - char *buf; - - if (0 == (ptr = isa_map_rom(0xc0000, 0x8000))) { - return -1; - } - if (NULL == (buf=malloc(0x8000))) { - isa_unmap_rom(ptr); - return -1; - } - if (readw(ptr) != 0xaa55) { - free(buf); - isa_unmap_rom(ptr); - return -1; - } - - /* shadow the rom */ - memcpy(buf, (void*)ptr, 0x8000); - isa_unmap_rom(ptr); - memcpy((void*)0xc0000, buf, 0x8000); - - free(buf); - - return 0; -} - -int video_bios_init(void) -{ - struct pt_regs regs; - - /* clear the video bios area in case we warmbooted */ - memset((void*)0xc0000, 0, 0x8000); - memset(®s, 0, sizeof(struct pt_regs)); - - if (probe_isa_video()) { - /* No ISA board found, try the PCI bus */ - regs.eax = probe_pci_video(); - } - - /* Did we succeed in mapping any video bios */ - if (readw(0xc0000) == 0xaa55) { - int size; - int i; - u8 sum; - - PRINTF("Found video bios signature\n"); - size = 512*readb(0xc0002); - PRINTF("size %d\n", size); - sum=0; - for (i=0;i -#include -#include -#include -#include -#include - -/* - * Memory lay-out: - * - * relative to setup_base (which is 0x90000 currently) - * - * 0x0000-0x7FFF Real mode kernel - * 0x8000-0x8FFF Stack and heap - * 0x9000-0x90FF Kernel command line - */ -#define DEFAULT_SETUP_BASE 0x90000 -#define COMMAND_LINE_OFFSET 0x9000 -#define HEAP_END_OFFSET 0x8e00 - -#define COMMAND_LINE_SIZE 2048 - -static void build_command_line(char *command_line, int auto_boot) -{ - char *env_command_line; - - command_line[0] = '\0'; - - env_command_line = getenv("bootargs"); - - /* set console= argument if we use a serial console */ - if (NULL == strstr(env_command_line, "console=")) { - if (0==strcmp(getenv("stdout"), "serial")) { - - /* We seem to use serial console */ - sprintf(command_line, "console=ttyS0,%s ", - getenv("baudrate")); - } - } - - if (auto_boot) { - strcat(command_line, "auto "); - } - - if (NULL != env_command_line) { - strcat(command_line, env_command_line); - } - - - printf("Kernel command line: \"%s\"\n", command_line); -} - -void *load_zimage(char *image, unsigned long kernel_size, - unsigned long initrd_addr, unsigned long initrd_size, - int auto_boot) -{ - void *setup_base; - int setup_size; - int bootproto; - int big_image; - void *load_address; - - - setup_base = (void*)DEFAULT_SETUP_BASE; /* base address for real-mode segment */ - - if (KERNEL_MAGIC != *(u16*)(image + BOOT_FLAG_OFF)) { - printf("Error: Invalid kernel magic (found 0x%04x, expected 0xaa55)\n", - *(u16*)(image + BOOT_FLAG_OFF)); - return 0; - } - - - /* determine boot protocol version */ - if (KERNEL_V2_MAGIC == *(u32*)(image+HEADER_OFF)) { - bootproto = *(u16*)(image+VERSION_OFF); - } else { - /* Very old kernel */ - bootproto = 0x0100; - } - - /* determine size of setup */ - if (0 == *(u8*)(image + SETUP_SECTS_OFF)) { - setup_size = 5 * 512; - } else { - setup_size = (*(u8*)(image + SETUP_SECTS_OFF) + 1) * 512; - } - - if (setup_size > SETUP_MAX_SIZE) { - printf("Error: Setup is too large (%d bytes)\n", setup_size); - } - - /* Determine image type */ - big_image = (bootproto >= 0x0200) && (*(u8*)(image + LOADFLAGS_OFF) & BIG_KERNEL_FLAG); - - /* Derermine load address */ - load_address = (void*)(big_image ? BZIMAGE_LOAD_ADDR:ZIMAGE_LOAD_ADDR); - - /* load setup */ - memmove(setup_base, image, setup_size); - - printf("Using boot protocol version %x.%02x\n", - (bootproto & 0xff00) >> 8, bootproto & 0xff); - - - if (bootproto == 0x0100) { - - *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; - *(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; - - /* A very old kernel MUST have its real-mode code - * loaded at 0x90000 */ - - if ((u32)setup_base != 0x90000) { - /* Copy the real-mode kernel */ - memmove((void*)0x90000, setup_base, setup_size); - /* Copy the command line */ - memmove((void*)0x99000, setup_base+COMMAND_LINE_OFFSET, - COMMAND_LINE_SIZE); - - setup_base = (void*)0x90000; /* Relocated */ - } - - /* It is recommended to clear memory up to the 32K mark */ - memset((void*)0x90000 + setup_size, 0, SETUP_MAX_SIZE-setup_size); - } - - if (bootproto >= 0x0200) { - *(u8*)(setup_base + TYPE_OF_LOADER_OFF) = 0xff; - printf("Linux kernel version %s\n", - (char*)(setup_base + SETUP_START_OFFSET + - *(u16*)(setup_base + START_SYS_OFF + 2))); - - if (initrd_addr) { - printf("Initial RAM disk at linear address 0x%08lx, size %ld bytes\n", - initrd_addr, initrd_size); - - *(u32*)(setup_base + RAMDISK_IMAGE_OFF) = initrd_addr; - *(u32*)(setup_base + RAMDISK_SIZE_OFF)=initrd_size; - } - } - - if (bootproto >= 0x0201) { - *(u16*)(setup_base + HEAP_END_PTR_OFF) = HEAP_END_OFFSET; - - /* CAN_USE_HEAP */ - *(u8*)(setup_base + LOADFLAGS_OFF) = - *(u8*)(setup_base + LOADFLAGS_OFF) | HEAP_FLAG; - } - - if (bootproto >= 0x0202) { - *(u32*)(setup_base + CMD_LINE_PTR_OFF) = (u32)setup_base + COMMAND_LINE_OFFSET; - } else if (bootproto >= 0x0200) { - *(u16*)(setup_base + CMD_LINE_MAGIC_OFF) = COMMAND_LINE_MAGIC; - *(u16*)(setup_base + CMD_LINE_OFFSET_OFF) = COMMAND_LINE_OFFSET; - *(u16*)(setup_base + SETUP_MOVE_SIZE_OFF) = 0x9100; - } - - - if (big_image) { - if ((kernel_size - setup_size) > BZIMAGE_MAX_SIZE) { - printf("Error: bzImage kernel too big! (size: %ld, max: %d)\n", - kernel_size - setup_size, BZIMAGE_MAX_SIZE); - return 0; - } - - } else if ((kernel_size - setup_size) > ZIMAGE_MAX_SIZE) { - printf("Error: zImage kernel too big! (size: %ld, max: %d)\n", - kernel_size - setup_size, ZIMAGE_MAX_SIZE); - return 0; - } - - /* build command line at COMMAND_LINE_OFFSET */ - build_command_line(setup_base + COMMAND_LINE_OFFSET, auto_boot); - - printf("Loading %czImage at address 0x%08x (%ld bytes)\n", big_image ? 'b' : ' ', - (u32)load_address, kernel_size - setup_size); - - - memmove(load_address, image + setup_size, kernel_size - setup_size); - - /* ready for booting */ - return setup_base; -} - - -void boot_zimage(void *setup_base) -{ - struct pt_regs regs; - - memset(®s, 0, sizeof(struct pt_regs)); - regs.xds = (u32)setup_base >> 4; - regs.xss = 0x9000; - regs.esp = 0x9000; - regs.eflags = 0; - enter_realmode(((u32)setup_base+SETUP_START_OFFSET)>>4, 0, ®s, ®s); -} - - -image_header_t *fake_zimage_header(image_header_t *hdr, void *ptr, int size) -{ - /* There is no way to know the size of a zImage ... * - * so we assume that 2MB will be enough for now */ -#define ZIMAGE_SIZE 0x200000 - - /* load a 1MB, the loaded will have to be moved to its final - * position again later... */ -#define ZIMAGE_LOAD 0x100000 - - ulong checksum; - - if (KERNEL_MAGIC != *(u16*)(ptr + BOOT_FLAG_OFF)) { - /* not a zImage or bzImage */ - return NULL; - } - - if (-1 == size) { - size = ZIMAGE_SIZE; - } -#if 0 - checksum = crc32 (0, ptr, size); -#else - checksum = 0; -#endif - memset(hdr, 0, sizeof(image_header_t)); - - /* Build new header */ - hdr->ih_magic = htonl(IH_MAGIC); - hdr->ih_time = 0; - hdr->ih_size = htonl(size); - hdr->ih_load = htonl(ZIMAGE_LOAD); - hdr->ih_ep = 0; - hdr->ih_dcrc = htonl(checksum); - hdr->ih_os = IH_OS_LINUX; - hdr->ih_arch = IH_CPU_I386; - hdr->ih_type = IH_TYPE_KERNEL; - hdr->ih_comp = IH_COMP_NONE; - - strncpy((char *)hdr->ih_name, "(none)", IH_NMLEN); - - checksum = crc32(0,(const char *)hdr,sizeof(image_header_t)); - - hdr->ih_hcrc = htonl(checksum); - - return hdr; -} diff --git a/lib_m68k/Makefile b/lib_m68k/Makefile deleted file mode 100644 index 698da36..0000000 --- a/lib_m68k/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(ARCH).a - -AOBJS = -COBJS = cache.o traps.o time.o board.o m68k_linux.o -OBJS = $(AOBJS) $(COBJS) - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/lib_m68k/board.c b/lib_m68k/board.c deleted file mode 100644 index 6b3edd6..0000000 --- a/lib_m68k/board.c +++ /dev/null @@ -1,730 +0,0 @@ -/* - * (C) Copyright 2003 - * Josef Baumgartner - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_M5272 -#include -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_IDE) -#include -#endif -#if (CONFIG_COMMANDS & CFG_CMD_SCSI) -#include -#endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#include -#endif -#ifdef CONFIG_STATUS_LED -#include -#endif -#include -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) -#include -#endif -#ifdef CFG_ALLOC_DPRAM -#include -#endif -#include - -#if defined(CONFIG_HARD_I2C) || \ - defined(CONFIG_SOFT_I2C) -#include -#endif - -static char *failed = "*** failed ***\n"; - -#ifdef CONFIG_PCU_E -extern flash_info_t flash_info[]; -#endif - -#include - -#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \ - (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \ - defined(CFG_ENV_IS_IN_NVRAM) -#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) -#else -#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN -#endif - -extern ulong __init_end; -extern ulong _end; - -extern void timer_init(void); - -#if defined(CONFIG_WATCHDOG) -# define INIT_FUNC_WATCHDOG_INIT watchdog_init, -# define WATCHDOG_DISABLE watchdog_disable - -extern int watchdog_init(void); -extern int watchdog_disable(void); -#else -# define INIT_FUNC_WATCHDOG_INIT /* undef */ -# define WATCHDOG_DISABLE /* undef */ -#endif /* CONFIG_WATCHDOG */ - -ulong monitor_flash_len; - -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - -/************************************************************************ - * Utilities * - ************************************************************************ - */ - -/* - * The Malloc area is immediately below the monitor copy in DRAM - */ -static void mem_malloc_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off; - - mem_malloc_end = dest_addr; - mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; - - memset ((void *) mem_malloc_start, - 0, - mem_malloc_end - mem_malloc_start); -} - -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || - (new > mem_malloc_end) ) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *)old); -} - -char *strmhz(char *buf, long hz) -{ - long l, n; - long m; - - n = hz / 1000000L; - - l = sprintf (buf, "%ld", n); - - m = (hz % 1000000L) / 1000L; - - if (m != 0) - sprintf (buf+l, ".%03ld", m); - - return (buf); -} - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ -typedef int (init_fnc_t) (void); - -/************************************************************************ - * Init Utilities * - ************************************************************************ - * Some of this code should be moved into the core functions, - * but let's get it working (again) first... - */ - -static int init_baudrate (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - uchar tmp[64]; /* long enough for environment variables */ - int i = getenv_r ("baudrate", tmp, sizeof (tmp)); - - gd->baudrate = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CONFIG_BAUDRATE; - return (0); -} - -/***********************************************************************/ - -static int init_func_ram (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - int board_type = 0; /* use dummy arg */ - puts ("DRAM: "); - - if ((gd->ram_size = initdram (board_type)) > 0) { - print_size (gd->ram_size, "\n"); - return (0); - } - puts (failed); - return (1); -} - -/***********************************************************************/ - -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) -static int init_func_i2c (void) -{ - puts ("I2C: "); - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - puts ("ready\n"); - return (0); -} -#endif - -/***********************************************************************/ - -/************************************************************************ - * Initialization sequence * - ************************************************************************ - */ - -init_fnc_t *init_sequence[] = { - env_init, - init_baudrate, - serial_init, - console_init_f, - display_options, - checkcpu, - checkboard, -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) - init_func_i2c, -#endif - init_func_ram, -#if defined(CFG_DRAM_TEST) - testdram, -#endif /* CFG_DRAM_TEST */ - INIT_FUNC_WATCHDOG_INIT - NULL, /* Terminate this list */ -}; - - -/************************************************************************ - * - * This is the first part of the initialization sequence that is - * implemented in C, but still running from ROM. - * - * The main purpose is to provide a (serial) console interface as - * soon as possible (so we can see any error messages), and to - * initialize the RAM so that we can relocate the monitor code to - * RAM. - * - * Be aware of the restrictions: global data is read-only, BSS is not - * initialized, and stack space is limited to a few kB. - * - ************************************************************************ - */ - -void -board_init_f (ulong bootflag) -{ - DECLARE_GLOBAL_DATA_PTR; - - bd_t *bd; - ulong len, addr, addr_sp; - gd_t *id; - init_fnc_t **init_fnc_ptr; -#ifdef CONFIG_PRAM - int i; - ulong reg; - uchar tmp[64]; /* long enough for environment variables */ -#endif - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - if ((*init_fnc_ptr)() != 0) { - hang (); - } - } - - /* - * Now that we have DRAM mapped and working, we can - * relocate the code and continue running from DRAM. - * - * Reserve memory at end of RAM for (top down in that order): - * - protected RAM - * - LCD framebuffer - * - monitor code - * - board info struct - */ - len = (ulong)&_end - CFG_MONITOR_BASE; - - addr = CFG_SDRAM_BASE + gd->ram_size; - -#ifdef CONFIG_LOGBUFFER - /* reserve kernel log buffer */ - addr -= (LOGBUFF_RESERVE); - debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); -#endif - -#ifdef CONFIG_PRAM - /* - * reserve protected RAM - */ - i = getenv_r ("pram", tmp, sizeof (tmp)); - reg = (i > 0) ? simple_strtoul (tmp, NULL, 10) : CONFIG_PRAM; - addr -= (reg << 10); /* size is in kB */ - debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); -#endif /* CONFIG_PRAM */ - - /* - * reserve memory for U-Boot code, data & bss - * round down to next 4 kB limit - */ - addr -= len; - addr &= ~(4096 - 1); - - debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); - - /* - * reserve memory for malloc() arena - */ - addr_sp = addr - TOTAL_MALLOC_LEN; - debug ("Reserving %dk for malloc() at: %08lx\n", - TOTAL_MALLOC_LEN >> 10, addr_sp); - - /* - * (permanently) allocate a Board Info struct - * and a permanent copy of the "global" data - */ - addr_sp -= sizeof (bd_t); - bd = (bd_t *) addr_sp; - gd->bd = bd; - debug ("Reserving %d Bytes for Board Info at: %08lx\n", - sizeof (bd_t), addr_sp); - addr_sp -= sizeof (gd_t); - id = (gd_t *) addr_sp; - debug ("Reserving %d Bytes for Global Data at: %08lx\n", - sizeof (gd_t), addr_sp); - - /* Reserve memory for boot params. */ - addr_sp -= CFG_BOOTPARAMS_LEN; - bd->bi_boot_params = addr_sp; - debug ("Reserving %dk for boot parameters at: %08lx\n", - CFG_BOOTPARAMS_LEN >> 10, addr_sp); - - /* - * Finally, we set up a new (bigger) stack. - * - * Leave some safety gap for SP, force alignment on 16 byte boundary - * Clear initial stack frame - */ - addr_sp -= 16; - addr_sp &= ~0xF; - *((ulong *) addr_sp)-- = 0; - *((ulong *) addr_sp)-- = 0; - debug ("Stack Pointer at: %08lx\n", addr_sp); - - /* - * Save local variables to board info struct - */ - bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ - bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ - bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ - - bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ - - WATCHDOG_RESET (); - bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ - bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ - -#ifdef CFG_EXTBDINFO - strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); - strncpy (bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version)); -#endif - - WATCHDOG_RESET (); - -#ifdef CONFIG_POST - post_bootmode_init(); - post_run (NULL, POST_ROM | post_bootmode_get(0)); -#endif - - WATCHDOG_RESET(); - - memcpy (id, (void *)gd, sizeof (gd_t)); - - debug ("Start relocate of code from %08x to %08lx\n", CFG_MONITOR_BASE, addr); - relocate_code (addr_sp, id, addr); - - /* NOTREACHED - jump_to_ram() does not return */ -} - -/************************************************************************ - * - * This is the next part if the initialization sequence: we are now - * running from RAM and have a "normal" C environment, i. e. global - * data can be written, BSS has been cleared, the stack size in not - * that critical any more, etc. - * - ************************************************************************ - */ -void board_init_r (gd_t *id, ulong dest_addr) -{ - DECLARE_GLOBAL_DATA_PTR; - cmd_tbl_t *cmdtp; - char *s, *e; - bd_t *bd; - int i; - extern void malloc_bin_reloc (void); - -#ifndef CFG_ENV_IS_NOWHERE - extern char * env_name_spec; -#endif -#ifndef CFG_NO_FLASH - ulong flash_size; -#endif - gd = id; /* initialize RAM version of global data */ - bd = gd->bd; - - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - - debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); - - WATCHDOG_RESET (); - - gd->reloc_off = dest_addr - CFG_MONITOR_BASE; - - monitor_flash_len = (ulong)&__init_end - dest_addr; - - /* - * We have to relocate the command table manually - */ - for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { - ulong addr; - addr = (ulong) (cmdtp->cmd) + gd->reloc_off; -#if 0 - printf ("Command \"%s\": 0x%08lx => 0x%08lx\n", - cmdtp->name, (ulong) (cmdtp->cmd), addr); -#endif - cmdtp->cmd = - (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; - - addr = (ulong)(cmdtp->name) + gd->reloc_off; - cmdtp->name = (char *)addr; - - if (cmdtp->usage) { - addr = (ulong)(cmdtp->usage) + gd->reloc_off; - cmdtp->usage = (char *)addr; - } -#ifdef CFG_LONGHELP - if (cmdtp->help) { - addr = (ulong)(cmdtp->help) + gd->reloc_off; - cmdtp->help = (char *)addr; - } -#endif - } - /* there are some other pointer constants we must deal with */ -#ifndef CFG_ENV_IS_NOWHERE - env_name_spec += gd->reloc_off; -#endif - - WATCHDOG_RESET (); - -#ifdef CONFIG_LOGBUFFER - logbuff_init_ptrs (); -#endif -#ifdef CONFIG_POST - post_output_backlog (); - post_reloc (); -#endif - WATCHDOG_RESET(); - -#if 0 - /* instruction cache enabled in cpu_init_f() for faster relocation */ - icache_enable (); /* it's time to enable the instruction cache */ -#endif - - /* - * Setup trap handlers - */ - trap_init (0); - -#if !defined(CFG_NO_FLASH) - puts ("FLASH: "); - - if ((flash_size = flash_init ()) > 0) { -# ifdef CFG_FLASH_CHECKSUM - print_size (flash_size, ""); - /* - * Compute and print flash CRC if flashchecksum is set to 'y' - * - * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX - */ - s = getenv ("flashchecksum"); - if (s && (*s == 'y')) { - printf (" CRC: %08lX", - crc32 (0, - (const unsigned char *) CFG_FLASH_BASE, - flash_size) - ); - } - putc ('\n'); -# else /* !CFG_FLASH_CHECKSUM */ - print_size (flash_size, "\n"); -# endif /* CFG_FLASH_CHECKSUM */ - } else { - puts (failed); - hang (); - } - - bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */ - bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */ - bd->bi_flashoffset = 0; -#else /* CFG_NO_FLASH */ - bd->bi_flashsize = 0; - bd->bi_flashstart = 0; - bd->bi_flashoffset = 0; -#endif /* !CFG_NO_FLASH */ - - WATCHDOG_RESET (); - - /* initialize higher level parts of CPU like time base and timers */ - cpu_init_r (); - - WATCHDOG_RESET (); - - /* initialize malloc() area */ - mem_malloc_init (); - malloc_bin_reloc (); - -#ifdef CONFIG_SPI -# if !defined(CFG_ENV_IS_IN_EEPROM) - spi_init_f (); -# endif - spi_init_r (); -#endif - - /* relocate environment function pointers etc. */ - env_relocate (); - - /* - * Fill in missing fields of bd_info. - * We do this here, where we have "normal" access to the - * environment; we used to do this still running from ROM, - * where had to use getenv_r(), which can be pretty slow when - * the environment is in EEPROM. - */ - s = getenv ("ethaddr"); - for (i = 0; i < 6; ++i) { - bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - /* IP Address */ - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - - WATCHDOG_RESET (); - - - /** leave this here (after malloc(), environment and PCI are working) **/ - /* Initialize devices */ - devices_init (); - - /* Initialize the jump table for applications */ - jumptable_init (); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r (); - -#if defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r (); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - WATCHDOG_RESET (); - puts ("KGDB: "); - kgdb_init (); -#endif - - debug ("U-Boot relocated to %08lx\n", dest_addr); - - /* - * Enable Interrupts - */ - interrupt_init (); - - /* Must happen after interrupts are initialized since - * an irq handler gets installed - */ - timer_init(); - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - serial_buffered_init(); -#endif - -#ifdef CONFIG_STATUS_LED - status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); -#endif - - udelay (20); - - set_timer (0); - - /* Insert function pointers now that we have relocated the code */ - - /* Initialize from environment */ - if ((s = getenv ("loadaddr")) != NULL) { - load_addr = simple_strtoul (s, NULL, 16); - } -#if (CONFIG_COMMANDS & CFG_CMD_NET) - if ((s = getenv ("bootfile")) != NULL) { - copy_filename (BootFile, s, sizeof (BootFile)); - } -#endif /* CFG_CMD_NET */ - - WATCHDOG_RESET (); - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) - WATCHDOG_RESET (); - puts ("DOC: "); - doc_init (); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - WATCHDOG_RESET (); - puts ("NAND:"); - nand_init(); /* go init the NAND */ -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) - WATCHDOG_RESET(); - eth_init(bd); -#endif - -#ifdef CONFIG_POST - post_run (NULL, POST_RAM | post_bootmode_get(0)); -#endif - -#ifdef CONFIG_LAST_STAGE_INIT - WATCHDOG_RESET (); - /* - * Some parts can be only initialized if all others (like - * Interrupts) are up and running (i.e. the PC-style ISA - * keyboard). - */ - last_stage_init (); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - WATCHDOG_RESET (); - bedbug_init (); -#endif - -#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) - /* - * Export available size of memory for Linux, - * taking into account the protected RAM at top of memory - */ - { - ulong pram; - uchar memsz[32]; -#ifdef CONFIG_PRAM - char *s; - - if ((s = getenv ("pram")) != NULL) { - pram = simple_strtoul (s, NULL, 10); - } else { - pram = CONFIG_PRAM; - } -#else - pram=0; -#endif -#ifdef CONFIG_LOGBUFFER - /* Also take the logbuffer into account (pram is in kB) */ - pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024; -#endif - sprintf (memsz, "%ldk", (bd->bi_memsize / 1024) - pram); - setenv ("mem", memsz); - } -#endif - -#ifdef CONFIG_MODEM_SUPPORT - { - extern int do_mdm_init; - do_mdm_init = gd->do_mdm_init; - } -#endif - -#ifdef CONFIG_WATCHDOG - /* disable watchdog if environment is set */ - if ((s = getenv ("watchdog")) != NULL) { - if (strncmp (s, "off", 3) == 0) { - WATCHDOG_DISABLE (); - } - } -#endif /* CONFIG_WATCHDOG*/ - - - /* Initialization complete - start the monitor */ - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) { - WATCHDOG_RESET (); - main_loop (); - } - - /* NOTREACHED - no way out of command loop except booting */ -} - - -void hang(void) -{ - puts ("### ERROR ### Please RESET the board ###\n"); - for (;;); -} diff --git a/lib_m68k/cache.c b/lib_m68k/cache.c deleted file mode 100644 index 84fb6c2..0000000 --- a/lib_m68k/cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -void flush_cache (ulong start_addr, ulong size) -{ - /* Must be implemented for all M68k processors with copy-back data cache */ -} diff --git a/lib_m68k/m68k_linux.c b/lib_m68k/m68k_linux.c deleted file mode 100644 index a32de1a..0000000 --- a/lib_m68k/m68k_linux.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include - -#define PHYSADDR(x) x - -#define LINUX_MAX_ENVS 256 -#define LINUX_MAX_ARGS 256 - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -extern image_header_t header; /* from cmd_bootm.c */ - -extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); - -static int linux_argc; -static char **linux_argv; - -static char **linux_env; -static char *linux_env_p; -static int linux_env_idx; - -static void linux_params_init (ulong start, char *commandline); -static void linux_env_set (char *env_name, char *env_val); - -void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], - ulong addr, ulong * len_ptr, int verify) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong len = 0, checksum; - ulong initrd_start, initrd_end; - ulong data; - void (*theKernel) (int, char **, char **, int *); - image_header_t *hdr = &header; - char *commandline = getenv ("bootargs"); - char env_buf[12]; - - theKernel = - (void (*)(int, char **, char **, int *)) ntohl (hdr->ih_ep); - - /* - * Check if there is an initrd image - */ - if (argc >= 3) { - SHOW_BOOT_PROGRESS (9); - - addr = simple_strtoul (argv[2], NULL, 16); - - printf ("## Loading Ramdisk Image at %08lx ...\n", addr); - - /* Copy header so we can blank CRC field for re-calculation */ - memcpy (&header, (char *) addr, sizeof (image_header_t)); - - if (ntohl (hdr->ih_magic) != IH_MAGIC) { - printf ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); - do_reset (cmdtp, flag, argc, argv); - } - - data = (ulong) & header; - len = sizeof (image_header_t); - - checksum = ntohl (hdr->ih_hcrc); - hdr->ih_hcrc = 0; - - if (crc32 (0, (char *) data, len) != checksum) { - printf ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); - do_reset (cmdtp, flag, argc, argv); - } - - SHOW_BOOT_PROGRESS (10); - - print_image_hdr (hdr); - - data = addr + sizeof (image_header_t); - len = ntohl (hdr->ih_size); - - if (verify) { - ulong csum = 0; - - printf (" Verifying Checksum ... "); - csum = crc32 (0, (char *) data, len); - if (csum != ntohl (hdr->ih_dcrc)) { - printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); - do_reset (cmdtp, flag, argc, argv); - } - printf ("OK\n"); - } - - SHOW_BOOT_PROGRESS (11); - - if ((hdr->ih_os != IH_OS_LINUX) || - (hdr->ih_arch != IH_CPU_M68K) || - (hdr->ih_type != IH_TYPE_RAMDISK)) { - printf ("No Linux M68K Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); - do_reset (cmdtp, flag, argc, argv); - } - - /* - * Now check if we have a multifile image - */ - } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { - ulong tail = ntohl (len_ptr[0]) % 4; - int i; - - SHOW_BOOT_PROGRESS (13); - - /* skip kernel length and terminator */ - data = (ulong) (&len_ptr[2]); - /* skip any additional image length fields */ - for (i = 1; len_ptr[i]; ++i) - data += 4; - /* add kernel length, and align */ - data += ntohl (len_ptr[0]); - if (tail) { - data += 4 - tail; - } - - len = ntohl (len_ptr[1]); - - } else { - /* - * no initrd image - */ - SHOW_BOOT_PROGRESS (14); - - data = 0; - } - -#ifdef DEBUG - if (!data) { - printf ("No initrd\n"); - } -#endif - - if (data) { - initrd_start = data; - initrd_end = initrd_start + len; - } else { - initrd_start = 0; - initrd_end = 0; - } - - SHOW_BOOT_PROGRESS (15); - -#ifdef DEBUG - printf ("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) theKernel); -#endif - - linux_params_init (PHYSADDR (gd->bd->bi_boot_params), commandline); - - sprintf (env_buf, "%lu", gd->ram_size >> 20); - linux_env_set ("memsize", env_buf); - - sprintf (env_buf, "0x%08X", (uint) PHYSADDR (initrd_start)); - linux_env_set ("initrd_start", env_buf); - - sprintf (env_buf, "0x%X", (uint) (initrd_end - initrd_start)); - linux_env_set ("initrd_size", env_buf); - - sprintf (env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart)); - linux_env_set ("flash_start", env_buf); - - sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); - linux_env_set ("flash_size", env_buf); - - /* we assume that the kernel is in place */ - printf ("\nStarting kernel ...\n\n"); - - theKernel (linux_argc, linux_argv, linux_env, 0); -} - -static void linux_params_init (ulong start, char *line) -{ - char *next, *quote, *argp; - - linux_argc = 1; - linux_argv = (char **) start; - linux_argv[0] = 0; - argp = (char *) (linux_argv + LINUX_MAX_ARGS); - - next = line; - - while (line && *line && linux_argc < LINUX_MAX_ARGS) { - quote = strchr (line, '"'); - next = strchr (line, ' '); - - while (next != NULL && quote != NULL && quote < next) { - /* we found a left quote before the next blank - * now we have to find the matching right quote - */ - next = strchr (quote + 1, '"'); - if (next != NULL) { - quote = strchr (next + 1, '"'); - next = strchr (next + 1, ' '); - } - } - - if (next == NULL) { - next = line + strlen (line); - } - - linux_argv[linux_argc] = argp; - memcpy (argp, line, next - line); - argp[next - line] = 0; - - argp += next - line + 1; - linux_argc++; - - if (*next) - next++; - - line = next; - } - - linux_env = (char **) (((ulong) argp + 15) & ~15); - linux_env[0] = 0; - linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS); - linux_env_idx = 0; -} - -static void linux_env_set (char *env_name, char *env_val) -{ - if (linux_env_idx < LINUX_MAX_ENVS - 1) { - linux_env[linux_env_idx] = linux_env_p; - - strcpy (linux_env_p, env_name); - linux_env_p += strlen (env_name); - - strcpy (linux_env_p, "="); - linux_env_p += 1; - - strcpy (linux_env_p, env_val); - linux_env_p += strlen (env_val); - - linux_env_p++; - linux_env[++linux_env_idx] = 0; - } -} diff --git a/lib_m68k/time.c b/lib_m68k/time.c deleted file mode 100644 index 1d6d297..0000000 --- a/lib_m68k/time.c +++ /dev/null @@ -1,302 +0,0 @@ -/* - * (C) Copyright 2003 Josef Baumgartner - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#include - -#ifdef CONFIG_M5272 -#include -#include -#endif - -#ifdef CONFIG_M5282 -#include -#endif - -#ifdef CONFIG_M5249 -#include -#include -#endif - - -static ulong timestamp; -#ifdef CONFIG_M5282 -static unsigned short lastinc; -#endif - - -#if defined(CONFIG_M5272) -/* - * We use timer 3 which is running with a period of 1 us - */ -void udelay(unsigned long usec) -{ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3); - uint start, now, tmp; - - while (usec > 0) { - if (usec > 65000) - tmp = 65000; - else - tmp = usec; - usec = usec - tmp; - - /* Set up TIMER 3 as timebase clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; - timerp->timer_tcn = 0; - /* set period to 1 us */ - timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE; - - start = now = timerp->timer_tcn; - while (now < start + tmp) - now = timerp->timer_tcn; - } -} - -void mcf_timer_interrupt (void * not_used){ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4); - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); - - /* check for timer 4 interrupts */ - if ((intp->int_isr & 0x01000000) != 0) { - return; - } - - /* reset timer */ - timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; - timestamp ++; -} - -void timer_init (void) { - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4); - volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); - - timestamp = 0; - - /* Set up TIMER 4 as clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; - - /* initialize and enable timer 4 interrupt */ - irq_install_handler (72, mcf_timer_interrupt, 0); - intp->int_icr1 |= 0x0000000d; - - timerp->timer_tcn = 0; - timerp->timer_trr = 1000; /* Interrupt every ms */ - /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ - timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; -} - -void reset_timer (void) -{ - timestamp = 0; -} - -ulong get_timer (ulong base) -{ - return (timestamp - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} -#endif - -#if defined(CONFIG_M5282) - -void udelay(unsigned long usec) -{ - volatile unsigned short *timerp; - uint tmp; - - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3); - - while (usec > 0) { - if (usec > 65000) - tmp = 65000; - else - tmp = usec; - usec = usec - tmp; - - /* Set up TIMER 3 as timebase clock */ - timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW; - timerp[MCFTIMER_PMR] = 0; - /* set period to 1 us */ - timerp[MCFTIMER_PCSR] = - (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; - - timerp[MCFTIMER_PMR] = tmp; - while (timerp[MCFTIMER_PCNTR] > 0); - } -} - -void timer_init (void) -{ - volatile unsigned short *timerp; - - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); - timestamp = 0; - - /* Set up TIMER 4 as poll clock */ - timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW; - timerp[MCFTIMER_PMR] = lastinc = 0; - timerp[MCFTIMER_PCSR] = - (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; -} - -void set_timer (ulong t) -{ - volatile unsigned short *timerp; - - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); - timestamp = 0; - timerp[MCFTIMER_PMR] = lastinc = 0; -} - -ulong get_timer (ulong base) -{ - unsigned short now, diff; - volatile unsigned short *timerp; - - timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4); - now = timerp[MCFTIMER_PCNTR]; - diff = -(now - lastinc); - - timestamp += diff; - lastinc = now; - return timestamp - base; -} - -void wait_ticks (unsigned long ticks) -{ - set_timer (0); - while (get_timer (0) < ticks); -} -#endif - - -#if defined(CONFIG_M5249) -/* - * We use timer 1 which is running with a period of 1 us - */ -void udelay(unsigned long usec) -{ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1); - uint start, now, tmp; - - while (usec > 0) { - if (usec > 65000) - tmp = 65000; - else - tmp = usec; - usec = usec - tmp; - - /* Set up TIMER 1 as timebase clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; - timerp->timer_tcn = 0; - /* set period to 1 us */ - /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ - timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE; - - start = now = timerp->timer_tcn; - while (now < start + tmp) - now = timerp->timer_tcn; - } -} - -void mcf_timer_interrupt (void * not_used){ - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); - - /* check for timer 2 interrupts */ - if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) { - return; - } - - /* reset timer */ - timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; - timestamp ++; -} - -void timer_init (void) { - volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); - - timestamp = 0; - - /* Set up TIMER 2 as clock */ - timerp->timer_tmr = MCFTIMER_TMR_DISABLE; - - /* initialize and enable timer 2 interrupt */ - irq_install_handler (31, mcf_timer_interrupt, 0); - mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); - mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3); - - timerp->timer_tcn = 0; - timerp->timer_trr = 1000; /* Interrupt every ms */ - /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ - /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ - timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | - MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; -} - -void reset_timer (void) -{ - timestamp = 0; -} - -ulong get_timer (ulong base) -{ - return (timestamp - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} -#endif - - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On M68K it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On M68K it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - tbclk = CFG_HZ; - return tbclk; -} diff --git a/lib_m68k/traps.c b/lib_m68k/traps.c deleted file mode 100644 index 1ca94dc..0000000 --- a/lib_m68k/traps.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2003 - * Josef Baumgartner - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - - -extern void _exc_handler(void); -extern void _int_handler(void); - -static void show_frame(struct pt_regs *fp) -{ - printf ("Vector Number: %d Format: %02x Fault Status: %01x\n\n", (fp->vector & 0x3fc) >> 2, - fp->format, (fp->vector & 0x3) | ((fp->vector & 0xc00) >> 8)); - printf ("PC: %08lx SR: %08lx SP: %08lx\n", fp->pc, (long) fp->sr, (long) fp); - printf ("D0: %08lx D1: %08lx D2: %08lx D3: %08lx\n", - fp->d0, fp->d1, fp->d2, fp->d3); - printf ("D4: %08lx D5: %08lx D6: %08lx D7: %08lx\n", - fp->d4, fp->d5, fp->d6, fp->d7); - printf ("A0: %08lx A1: %08lx A2: %08lx A3: %08lx\n", - fp->a0, fp->a1, fp->a2, fp->a3); - printf ("A4: %08lx A5: %08lx A6: %08lx\n", - fp->a4, fp->a5, fp->a6); -} - -void exc_handler(struct pt_regs *fp) { - printf("\n\n*** Unexpected exception ***\n"); - show_frame (fp); - printf("\n*** Please Reset Board! ***\n"); - for(;;); -} - -void trap_init(ulong value) { - unsigned long *vec = (ulong *)value; - int i; - - for(i = 2; i < 25; i++) { - vec[i] = (unsigned long)_exc_handler; - } - for(i = 25; i < 32; i++) { - vec[i] = (unsigned long)_int_handler; - } - for(i = 32; i < 64; i++) { - vec[i] = (unsigned long)_exc_handler; - } - for(i = 64; i < 256; i++) { - vec[i] = (unsigned long)_int_handler; - } - - setvbr(value); /* set vector base register to new table */ -} diff --git a/lib_microblaze/Makefile b/lib_microblaze/Makefile deleted file mode 100644 index ec01722..0000000 --- a/lib_microblaze/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(ARCH).a - -AOBJS = - -COBJS = board.o microblaze_linux.o time.o cache.o - -OBJS = $(AOBJS) $(COBJS) - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c deleted file mode 100644 index bc987a3..0000000 --- a/lib_microblaze/board.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -const char version_string[] = - U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"; - -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start; -static ulong mem_malloc_end; -static ulong mem_malloc_brk; - - -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *) old); -} - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ -typedef int (init_fnc_t) (void); - -init_fnc_t *init_sequence[] = { - serial_init, /* serial communications setup */ - NULL, -}; - -void board_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - bd_t *bd; - init_fnc_t **init_fnc_ptr; - - /* Pointer is writable since we allocated a register for it. */ - gd = (gd_t *)CFG_GBL_DATA_OFFSET; - memset((void *)gd, 0, CFG_GBL_DATA_SIZE); - - gd->bd = (bd_t *)(gd+1); /* At end of global data */ - gd->baudrate = CONFIG_BAUDRATE; - - bd = gd->bd; - bd->bi_baudrate = CONFIG_BAUDRATE; - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - WATCHDOG_RESET (); - if ((*init_fnc_ptr) () != 0) { - hang (); - } - } - - /* main_loop */ - for (;;) { - WATCHDOG_RESET (); - main_loop (); - } -} - -void hang (void) -{ - puts ("### ERROR ### Please RESET the board ###\n"); - for (;;); -} diff --git a/lib_microblaze/cache.c b/lib_microblaze/cache.c deleted file mode 100644 index a2f7493..0000000 --- a/lib_microblaze/cache.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -void flush_cache (ulong addr, ulong size) -{ - /* MicroBlaze have write thruough cache. nothing to do. */ - return; -} diff --git a/lib_microblaze/microblaze_linux.c b/lib_microblaze/microblaze_linux.c deleted file mode 100644 index b3a0815..0000000 --- a/lib_microblaze/microblaze_linux.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], - ulong addr, ulong *len_ptr, int verify) -{ -} diff --git a/lib_microblaze/time.c b/lib_microblaze/time.c deleted file mode 100644 index 12e8488..0000000 --- a/lib_microblaze/time.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -void udelay(unsigned long usec) -{ -} diff --git a/lib_mips/Makefile b/lib_mips/Makefile deleted file mode 100644 index d5980e6..0000000 --- a/lib_mips/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(ARCH).a - -AOBJS = - -COBJS = board.o time.o mips_linux.o - -OBJS = $(AOBJS) $(COBJS) - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/lib_mips/board.c b/lib_mips/board.c deleted file mode 100644 index b7d3356..0000000 --- a/lib_mips/board.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \ - (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \ - defined(CFG_ENV_IS_IN_NVRAM) -#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) -#else -#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN -#endif - -#undef DEBUG - -extern int timer_init(void); - -extern int incaip_set_cpuclk(void); - -extern ulong uboot_end_data; -extern ulong uboot_end; - -ulong monitor_flash_len; - -const char version_string[] = - U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"; - -static char *failed = "*** failed ***\n"; - -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start; -static ulong mem_malloc_end; -static ulong mem_malloc_brk; - - -/* - * The Malloc area is immediately below the monitor copy in DRAM - */ -static void mem_malloc_init (void) -{ - ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off; - - mem_malloc_end = dest_addr; - mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; - - memset ((void *) mem_malloc_start, - 0, - mem_malloc_end - mem_malloc_start); -} - -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *) old); -} - - -static int init_func_ram (void) -{ -#ifdef CONFIG_BOARD_TYPES - int board_type = gd->board_type; -#else - int board_type = 0; /* use dummy arg */ -#endif - puts ("DRAM: "); - - if ((gd->ram_size = initdram (board_type)) > 0) { - print_size (gd->ram_size, "\n"); - return (0); - } - puts (failed); - return (1); -} - -static int display_banner(void) -{ - - printf ("\n\n%s\n\n", version_string); - return (0); -} - -static void display_flash_config(ulong size) -{ - puts ("Flash: "); - print_size (size, "\n"); -} - - -static int init_baudrate (void) -{ - char tmp[64]; /* long enough for environment variables */ - int i = getenv_r ("baudrate", tmp, sizeof (tmp)); - - gd->baudrate = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CONFIG_BAUDRATE; - - return (0); -} - - -/* - * Breath some life into the board... - * - * The first part of initialization is running from Flash memory; - * its main purpose is to initialize the RAM so that we - * can relocate the monitor code to RAM. - */ - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ -typedef int (init_fnc_t) (void); - -init_fnc_t *init_sequence[] = { - timer_init, - env_init, /* initialize environment */ -#ifdef CONFIG_INCA_IP - incaip_set_cpuclk, /* set cpu clock according to environment variable */ -#endif - init_baudrate, /* initialze baudrate settings */ - serial_init, /* serial communications setup */ - console_init_f, - display_banner, /* say that we are here */ - checkboard, - init_func_ram, - NULL, -}; - - -void board_init_f(ulong bootflag) -{ - gd_t gd_data, *id; - bd_t *bd; - init_fnc_t **init_fnc_ptr; - ulong addr, addr_sp, len = (ulong)&uboot_end - CFG_MONITOR_BASE; - ulong *s; -#ifdef CONFIG_PURPLE - void copy_code (ulong); -#endif - - /* Pointer is writable since we allocated a register for it. - */ - gd = &gd_data; - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); - - memset ((void *)gd, 0, sizeof (gd_t)); - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - if ((*init_fnc_ptr)() != 0) { - hang (); - } - } - - /* - * Now that we have DRAM mapped and working, we can - * relocate the code and continue running from DRAM. - */ - addr = CFG_SDRAM_BASE + gd->ram_size; - - /* We can reserve some RAM "on top" here. - */ - - /* round down to next 4 kB limit. - */ - addr &= ~(4096 - 1); - debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); - - /* Reserve memory for U-Boot code, data & bss - * round down to next 16 kB limit - */ - addr -= len; - addr &= ~(16 * 1024 - 1); - - debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); - - /* Reserve memory for malloc() arena. - */ - addr_sp = addr - TOTAL_MALLOC_LEN; - debug ("Reserving %dk for malloc() at: %08lx\n", - TOTAL_MALLOC_LEN >> 10, addr_sp); - - /* - * (permanently) allocate a Board Info struct - * and a permanent copy of the "global" data - */ - addr_sp -= sizeof(bd_t); - bd = (bd_t *)addr_sp; - gd->bd = bd; - debug ("Reserving %d Bytes for Board Info at: %08lx\n", - sizeof(bd_t), addr_sp); - - addr_sp -= sizeof(gd_t); - id = (gd_t *)addr_sp; - debug ("Reserving %d Bytes for Global Data at: %08lx\n", - sizeof (gd_t), addr_sp); - - /* Reserve memory for boot params. - */ - addr_sp -= CFG_BOOTPARAMS_LEN; - bd->bi_boot_params = addr_sp; - debug ("Reserving %dk for boot params() at: %08lx\n", - CFG_BOOTPARAMS_LEN >> 10, addr_sp); - - /* - * Finally, we set up a new (bigger) stack. - * - * Leave some safety gap for SP, force alignment on 16 byte boundary - * Clear initial stack frame - */ - addr_sp -= 16; - addr_sp &= ~0xF; - s = (ulong *)addr_sp; - *s-- = 0; - *s-- = 0; - addr_sp = (ulong)s; - debug ("Stack Pointer at: %08lx\n", addr_sp); - - /* - * Save local variables to board info struct - */ - bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ - bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ - - memcpy (id, (void *)gd, sizeof (gd_t)); - - /* On the purple board we copy the code in a special way - * in order to solve flash problems - */ -#ifdef CONFIG_PURPLE - copy_code(addr); -#endif - - relocate_code (addr_sp, id, addr); - - /* NOTREACHED - relocate_code() does not return */ -} -/************************************************************************ - * - * This is the next part if the initialization sequence: we are now - * running from RAM and have a "normal" C environment, i. e. global - * data can be written, BSS has been cleared, the stack size in not - * that critical any more, etc. - * - ************************************************************************ - */ - -void board_init_r (gd_t *id, ulong dest_addr) -{ - cmd_tbl_t *cmdtp; - ulong size; - extern void malloc_bin_reloc (void); -#ifndef CFG_ENV_IS_NOWHERE - extern char * env_name_spec; -#endif - char *s, *e; - bd_t *bd; - int i; - - gd = id; - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - - debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); - - gd->reloc_off = dest_addr - CFG_MONITOR_BASE; - - monitor_flash_len = (ulong)&uboot_end_data - dest_addr; - - /* - * We have to relocate the command table manually - */ - for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { - ulong addr; - - addr = (ulong) (cmdtp->cmd) + gd->reloc_off; -#if 0 - printf ("Command \"%s\": 0x%08lx => 0x%08lx\n", - cmdtp->name, (ulong) (cmdtp->cmd), addr); -#endif - cmdtp->cmd = - (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; - - addr = (ulong)(cmdtp->name) + gd->reloc_off; - cmdtp->name = (char *)addr; - - if (cmdtp->usage) { - addr = (ulong)(cmdtp->usage) + gd->reloc_off; - cmdtp->usage = (char *)addr; - } -#ifdef CFG_LONGHELP - if (cmdtp->help) { - addr = (ulong)(cmdtp->help) + gd->reloc_off; - cmdtp->help = (char *)addr; - } -#endif - } - /* there are some other pointer constants we must deal with */ -#ifndef CFG_ENV_IS_NOWHERE - env_name_spec += gd->reloc_off; -#endif - - /* configure available FLASH banks */ - size = flash_init(); - display_flash_config (size); - - bd = gd->bd; - bd->bi_flashstart = CFG_FLASH_BASE; - bd->bi_flashsize = size; -#if CFG_MONITOR_BASE == CFG_FLASH_BASE - bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */ -#else - bd->bi_flashoffset = 0; -#endif - - /* initialize malloc() area */ - mem_malloc_init(); - malloc_bin_reloc(); - - /* relocate environment function pointers etc. */ - env_relocate(); - - /* board MAC address */ - s = getenv ("ethaddr"); - for (i = 0; i < 6; ++i) { - bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - /* IP Address */ - bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - -#if defined(CONFIG_PCI) - /* - * Do pci configuration - */ - pci_init(); -#endif - -/** leave this here (after malloc(), environment and PCI are working) **/ - /* Initialize devices */ - devices_init (); - - jumptable_init (); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r (); -/** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/ - - /* Initialize from environment */ - if ((s = getenv ("loadaddr")) != NULL) { - load_addr = simple_strtoul (s, NULL, 16); - } -#if (CONFIG_COMMANDS & CFG_CMD_NET) - if ((s = getenv ("bootfile")) != NULL) { - copy_filename (BootFile, s, sizeof (BootFile)); - } -#endif /* CFG_CMD_NET */ - -#if defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r (); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NET) -#if defined(CONFIG_NET_MULTI) - puts ("Net: "); -#endif - eth_initialize(gd->bd); -#endif - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) { - main_loop (); - } - - /* NOTREACHED - no way out of command loop except booting */ -} - -void hang (void) -{ - puts ("### ERROR ### Please RESET the board ###\n"); - for (;;); -} diff --git a/lib_mips/mips_linux.c b/lib_mips/mips_linux.c deleted file mode 100644 index 12e8435..0000000 --- a/lib_mips/mips_linux.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include -#include - -#define LINUX_MAX_ENVS 256 -#define LINUX_MAX_ARGS 256 - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -extern image_header_t header; /* from cmd_bootm.c */ - -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -static int linux_argc; -static char ** linux_argv; - -static char ** linux_env; -static char * linux_env_p; -static int linux_env_idx; - -static void linux_params_init (ulong start, char * commandline); -static void linux_env_set (char * env_name, char * env_val); - - -void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], - ulong addr, ulong * len_ptr, int verify) -{ - DECLARE_GLOBAL_DATA_PTR; - - ulong len = 0, checksum; - ulong initrd_start, initrd_end; - ulong data; - void (*theKernel) (int, char **, char **, int *); - image_header_t *hdr = &header; - char *commandline = getenv ("bootargs"); - char env_buf[12]; - - theKernel = - (void (*)(int, char **, char **, int *)) ntohl (hdr->ih_ep); - - /* - * Check if there is an initrd image - */ - if (argc >= 3) { - SHOW_BOOT_PROGRESS (9); - - addr = simple_strtoul (argv[2], NULL, 16); - - printf ("## Loading Ramdisk Image at %08lx ...\n", addr); - - /* Copy header so we can blank CRC field for re-calculation */ - memcpy (&header, (char *) addr, sizeof (image_header_t)); - - if (ntohl (hdr->ih_magic) != IH_MAGIC) { - printf ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); - do_reset (cmdtp, flag, argc, argv); - } - - data = (ulong) & header; - len = sizeof (image_header_t); - - checksum = ntohl (hdr->ih_hcrc); - hdr->ih_hcrc = 0; - - if (crc32 (0, (uchar *) data, len) != checksum) { - printf ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); - do_reset (cmdtp, flag, argc, argv); - } - - SHOW_BOOT_PROGRESS (10); - - print_image_hdr (hdr); - - data = addr + sizeof (image_header_t); - len = ntohl (hdr->ih_size); - - if (verify) { - ulong csum = 0; - - printf (" Verifying Checksum ... "); - csum = crc32 (0, (uchar *) data, len); - if (csum != ntohl (hdr->ih_dcrc)) { - printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); - do_reset (cmdtp, flag, argc, argv); - } - printf ("OK\n"); - } - - SHOW_BOOT_PROGRESS (11); - - if ((hdr->ih_os != IH_OS_LINUX) || - (hdr->ih_arch != IH_CPU_MIPS) || - (hdr->ih_type != IH_TYPE_RAMDISK)) { - printf ("No Linux MIPS Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); - do_reset (cmdtp, flag, argc, argv); - } - - /* - * Now check if we have a multifile image - */ - } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { - ulong tail = ntohl (len_ptr[0]) % 4; - int i; - - SHOW_BOOT_PROGRESS (13); - - /* skip kernel length and terminator */ - data = (ulong) (&len_ptr[2]); - /* skip any additional image length fields */ - for (i = 1; len_ptr[i]; ++i) - data += 4; - /* add kernel length, and align */ - data += ntohl (len_ptr[0]); - if (tail) { - data += 4 - tail; - } - - len = ntohl (len_ptr[1]); - - } else { - /* - * no initrd image - */ - SHOW_BOOT_PROGRESS (14); - - data = 0; - } - -#ifdef DEBUG - if (!data) { - printf ("No initrd\n"); - } -#endif - - if (data) { - initrd_start = data; - initrd_end = initrd_start + len; - } else { - initrd_start = 0; - initrd_end = 0; - } - - SHOW_BOOT_PROGRESS (15); - -#ifdef DEBUG - printf ("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) theKernel); -#endif - - linux_params_init (UNCACHED_SDRAM (gd->bd->bi_boot_params), commandline); - -#ifdef CONFIG_MEMSIZE_IN_BYTES - sprintf (env_buf, "%lu", gd->ram_size); -#ifdef DEBUG - printf ("## Giving linux memsize in bytes, %lu\n", gd->ram_size); -#endif -#else - sprintf (env_buf, "%lu", gd->ram_size >> 20); -#ifdef DEBUG - printf ("## Giving linux memsize in MB, %lu\n", gd->ram_size >> 20); -#endif -#endif /* CONFIG_MEMSIZE_IN_BYTES */ - - linux_env_set ("memsize", env_buf); - - sprintf (env_buf, "0x%08X", (uint) UNCACHED_SDRAM (initrd_start)); - linux_env_set ("initrd_start", env_buf); - - sprintf (env_buf, "0x%X", (uint) (initrd_end - initrd_start)); - linux_env_set ("initrd_size", env_buf); - - sprintf (env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart)); - linux_env_set ("flash_start", env_buf); - - sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); - linux_env_set ("flash_size", env_buf); - - /* we assume that the kernel is in place */ - printf ("\nStarting kernel ...\n\n"); - - theKernel (linux_argc, linux_argv, linux_env, 0); -} - -static void linux_params_init (ulong start, char *line) -{ - char *next, *quote, *argp; - - linux_argc = 1; - linux_argv = (char **) start; - linux_argv[0] = 0; - argp = (char *) (linux_argv + LINUX_MAX_ARGS); - - next = line; - - while (line && *line && linux_argc < LINUX_MAX_ARGS) { - quote = strchr (line, '"'); - next = strchr (line, ' '); - - while (next != NULL && quote != NULL && quote < next) { - /* we found a left quote before the next blank - * now we have to find the matching right quote - */ - next = strchr (quote + 1, '"'); - if (next != NULL) { - quote = strchr (next + 1, '"'); - next = strchr (next + 1, ' '); - } - } - - if (next == NULL) { - next = line + strlen (line); - } - - linux_argv[linux_argc] = argp; - memcpy (argp, line, next - line); - argp[next - line] = 0; - - argp += next - line + 1; - linux_argc++; - - if (*next) - next++; - - line = next; - } - - linux_env = (char **) (((ulong) argp + 15) & ~15); - linux_env[0] = 0; - linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS); - linux_env_idx = 0; -} - -static void linux_env_set (char *env_name, char *env_val) -{ - if (linux_env_idx < LINUX_MAX_ENVS - 1) { - linux_env[linux_env_idx] = linux_env_p; - - strcpy (linux_env_p, env_name); - linux_env_p += strlen (env_name); - - strcpy (linux_env_p, "="); - linux_env_p += 1; - - strcpy (linux_env_p, env_val); - linux_env_p += strlen (env_val); - - linux_env_p++; - linux_env[++linux_env_idx] = 0; - } -} diff --git a/lib_mips/time.c b/lib_mips/time.c deleted file mode 100644 index cd8dc72..0000000 --- a/lib_mips/time.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - - -static inline void mips_compare_set(u32 v) -{ - asm volatile ("mtc0 %0, $11" : : "r" (v)); -} - -static inline void mips_count_set(u32 v) -{ - asm volatile ("mtc0 %0, $9" : : "r" (v)); -} - - -static inline u32 mips_count_get(void) -{ - u32 count; - - asm volatile ("mfc0 %0, $9" : "=r" (count) :); - return count; -} - -/* - * timer without interrupts - */ - -int timer_init(void) -{ - mips_compare_set(0); - mips_count_set(0); - - return 0; -} - -void reset_timer(void) -{ - mips_count_set(0); -} - -ulong get_timer(ulong base) -{ - return mips_count_get() - base; -} - -void set_timer(ulong t) -{ - mips_count_set(t); -} - -void udelay (unsigned long usec) -{ - ulong tmo; - ulong start = get_timer(0); - - tmo = usec * (CFG_HZ / 1000000); - while ((ulong)((mips_count_get() - start)) < tmo) - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On MIPS it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return mips_count_get(); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On MIPS it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CFG_HZ; -} diff --git a/lib_nios/Makefile b/lib_nios/Makefile deleted file mode 100644 index eff46db..0000000 --- a/lib_nios/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(ARCH).a - -AOBJS = - -COBJS = board.o cache.o divmod.o nios_linux.o mult.o time.o - -OBJS = $(AOBJS) $(COBJS) - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/lib_nios/board.c b/lib_nios/board.c deleted file mode 100644 index e6cda52..0000000 --- a/lib_nios/board.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif - - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ - - -extern void malloc_bin_reloc (void); -typedef int (init_fnc_t) (void); - -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - -/* - * The Malloc area is immediately below the monitor copy in RAM - */ -static void mem_malloc_init (void) -{ - mem_malloc_start = CFG_MALLOC_BASE; - mem_malloc_end = mem_malloc_start + CFG_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; - memset ((void *) mem_malloc_start, - 0, - mem_malloc_end - mem_malloc_start); -} - -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *) old); -} - - -/************************************************************************ - * Initialization sequence * - ***********************************************************************/ - -init_fnc_t *init_sequence[] = { - -#if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, /* Call board-specific init code early.*/ -#endif - - env_init, - serial_init, - console_init_f, - display_options, - checkcpu, - checkboard, - NULL, /* Terminate this list */ -}; - - -/***********************************************************************/ -void board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - bd_t *bd; - init_fnc_t **init_fnc_ptr; - char *s, *e; - int i; - - /* Pointer is writable since we allocated a register for it. - * Nios treats CFG_GBL_DATA_OFFSET as an address. - */ - gd = (gd_t *)CFG_GBL_DATA_OFFSET; - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); - - memset( gd, 0, CFG_GBL_DATA_SIZE ); - - gd->bd = (bd_t *)(gd+1); /* At end of global data */ - gd->baudrate = CONFIG_BAUDRATE; - gd->cpu_clk = CONFIG_SYS_CLK_FREQ; - - bd = gd->bd; - bd->bi_memstart = CFG_SDRAM_BASE; - bd->bi_memsize = CFG_SDRAM_SIZE; - bd->bi_flashstart = CFG_FLASH_BASE; -#if defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE) - bd->bi_sramstart= CFG_SRAM_BASE; - bd->bi_sramsize = CFG_SRAM_SIZE; -#endif - bd->bi_baudrate = CONFIG_BAUDRATE; - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - WATCHDOG_RESET (); - if ((*init_fnc_ptr) () != 0) { - hang (); - } - } - - WATCHDOG_RESET (); - bd->bi_flashsize = flash_init(); - - WATCHDOG_RESET (); - mem_malloc_init(); - malloc_bin_reloc(); - env_relocate(); - - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - s = getenv ("ethaddr"); - for (i = 0; i < 6; ++i) { - bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) s = (*e) ? e + 1 : e; - } - - WATCHDOG_RESET (); - devices_init(); - jumptable_init(); - console_init_r(); - /* - */ - - WATCHDOG_RESET (); - interrupt_init (); - -#ifdef CONFIG_STATUS_LED - status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); -#endif - - /* main_loop */ - for (;;) { - WATCHDOG_RESET (); - main_loop (); - } -} - - -/***********************************************************************/ - -void hang (void) -{ -#ifdef CONFIG_STATUS_LED - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING); -#endif - puts("### ERROR ### Please reset board ###\n"); - for (;;); -} diff --git a/lib_nios/cache.c b/lib_nios/cache.c deleted file mode 100644 index 87dbab1..0000000 --- a/lib_nios/cache.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - - -void flush_cache (ulong addr, ulong size) -{ - /* Nios cache is write-thru -- nothing to do here. - */ - return; -} diff --git a/lib_nios/divmod.c b/lib_nios/divmod.c deleted file mode 100644 index 3c7e71e..0000000 --- a/lib_nios/divmod.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of GNU CC. - * - * GNU CC is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundation; either version 2, or (at your - * option) any later version. - * - * GNU CC is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with GNU CC; see the file COPYING. If not, write - * to the Free Software Foundation, 59 Temple Place - Suite 330, - * Boston, MA 02111-1307, USA. - */ - - -#include "math.h" - -USItype udivmodsi4 (USItype num, USItype den, word_type modwanted) -{ - USItype bit = 1; - USItype res = 0; - - while (den < num && bit && !(den & (1L << 31))) { - den <<= 1; - bit <<= 1; - } - while (bit) { - if (num >= den) { - num -= den; - res |= bit; - } - bit >>= 1; - den >>= 1; - } - if (modwanted) - return num; - return res; -} - - -SItype __divsi3 (SItype a, SItype b) -{ - word_type neg = 0; - SItype res; - - if (a < 0) { - a = -a; - neg = !neg; - } - - if (b < 0) { - b = -b; - neg = !neg; - } - - res = udivmodsi4 (a, b, 0); - - if (neg) - res = -res; - - return res; -} - - -SItype __modsi3 (SItype a, SItype b) -{ - word_type neg = 0; - SItype res; - - if (a < 0) { - a = -a; - neg = 1; - } - - if (b < 0) - b = -b; - - res = udivmodsi4 (a, b, 1); - - if (neg) - res = -res; - - return res; -} - - -SItype __udivsi3 (SItype a, SItype b) -{ - return udivmodsi4 (a, b, 0); -} - - -SItype __umodsi3 (SItype a, SItype b) -{ - return udivmodsi4 (a, b, 1); -} diff --git a/lib_nios/math.h b/lib_nios/math.h deleted file mode 100644 index ccffbbc..0000000 --- a/lib_nios/math.h +++ /dev/null @@ -1,16 +0,0 @@ -#define BITS_PER_UNIT 8 - -typedef int HItype __attribute__ ((mode (HI))); -typedef unsigned int UHItype __attribute__ ((mode (HI))); - -typedef int SItype __attribute__ ((mode (SI))); -typedef unsigned int USItype __attribute__ ((mode (SI))); - -typedef int word_type __attribute__ ((mode (__word__))); - -struct SIstruct {HItype low, high;}; - -typedef union { - struct SIstruct s; - SItype ll; -} SIunion; diff --git a/lib_nios/mult.c b/lib_nios/mult.c deleted file mode 100644 index 66bb64d..0000000 --- a/lib_nios/mult.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of GNU CC. - * - * GNU CC is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundation; either version 2, or (at your - * option) any later version. - * - * GNU CC is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with GNU CC; see the file COPYING. If not, write - * to the Free Software Foundation, 59 Temple Place - Suite 330, - * Boston, MA 02111-1307, USA. - */ - - -#include - -#if !defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP) - -#include "math.h" - -USItype __mulsi3 (USItype a, USItype b) -{ - USItype c = 0; - - while (a != 0) { - if (a & 1) - c += b; - a >>= 1; - b <<= 1; - } - - return c; -} - - -UHItype __mulhi3 (UHItype a, UHItype b) -{ - UHItype c = 0; - - while (a != 0) { - if (a & 1) - c += b; - a >>= 1; - b <<= 1; - } - - return c; -} - -#endif /*!defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP) */ diff --git a/lib_nios/nios_linux.c b/lib_nios/nios_linux.c deleted file mode 100644 index eef1757..0000000 --- a/lib_nios/nios_linux.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* FIXME: Once we find a stable version of uC-linux for nios - * we can get this working. ;-) - * - */ -void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], - ulong addr, ulong *len_ptr, int verify) -{ -} diff --git a/lib_nios/time.c b/lib_nios/time.c deleted file mode 100644 index 25a233e..0000000 --- a/lib_nios/time.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -extern void dly_clks( unsigned long ticks ); - -void udelay(unsigned long usec) -{ - /* The Nios core doesn't have a timebase, so we do our - * best for now and call a low-level loop that counts - * cpu clocks. - */ - unsigned long cnt = (CONFIG_SYS_CLK_FREQ/1000000) * usec; - WATCHDOG_RESET (); /* trigger watchdog if needed */ - dly_clks (cnt); -} diff --git a/lib_nios2/Makefile b/lib_nios2/Makefile deleted file mode 100644 index 44b893c..0000000 --- a/lib_nios2/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(ARCH).a - -AOBJS = cache.o - -COBJS = board.o divmod.o nios_linux.o mult.o time.o - -OBJS = $(AOBJS) $(COBJS) - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/lib_nios2/board.c b/lib_nios2/board.c deleted file mode 100644 index 0e0b042..0000000 --- a/lib_nios2/board.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif - - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ - - -extern void malloc_bin_reloc (void); -typedef int (init_fnc_t) (void); - -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - -/* - * The Malloc area is immediately below the monitor copy in RAM - */ -static void mem_malloc_init (void) -{ - mem_malloc_start = CFG_MALLOC_BASE; - mem_malloc_end = mem_malloc_start + CFG_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; - memset ((void *) mem_malloc_start, - 0, - mem_malloc_end - mem_malloc_start); -} - -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *) old); -} - - -/************************************************************************ - * Initialization sequence * - ***********************************************************************/ - -init_fnc_t *init_sequence[] = { - -#if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, /* Call board-specific init code early.*/ -#endif - - env_init, - serial_init, - console_init_f, - display_options, - checkcpu, - checkboard, - NULL, /* Terminate this list */ -}; - - -/***********************************************************************/ -void board_init (void) -{ - DECLARE_GLOBAL_DATA_PTR; - - bd_t *bd; - init_fnc_t **init_fnc_ptr; - char *s, *e; - int i; - - /* Pointer is writable since we allocated a register for it. - * Nios treats CFG_GBL_DATA_OFFSET as an address. - */ - gd = (gd_t *)CFG_GBL_DATA_OFFSET; - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); - - memset( gd, 0, CFG_GBL_DATA_SIZE ); - - gd->bd = (bd_t *)(gd+1); /* At end of global data */ - gd->baudrate = CONFIG_BAUDRATE; - gd->cpu_clk = CONFIG_SYS_CLK_FREQ; - - bd = gd->bd; - bd->bi_memstart = CFG_SDRAM_BASE; - bd->bi_memsize = CFG_SDRAM_SIZE; - bd->bi_flashstart = CFG_FLASH_BASE; -#if defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE) - bd->bi_sramstart= CFG_SRAM_BASE; - bd->bi_sramsize = CFG_SRAM_SIZE; -#endif - bd->bi_baudrate = CONFIG_BAUDRATE; - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - WATCHDOG_RESET (); - if ((*init_fnc_ptr) () != 0) { - hang (); - } - } - - WATCHDOG_RESET (); - bd->bi_flashsize = flash_init(); - - WATCHDOG_RESET (); - mem_malloc_init(); - malloc_bin_reloc(); - env_relocate(); - - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - s = getenv ("ethaddr"); - for (i = 0; i < 6; ++i) { - bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) s = (*e) ? e + 1 : e; - } - - WATCHDOG_RESET (); - devices_init(); - jumptable_init(); - console_init_r(); - - WATCHDOG_RESET (); - interrupt_init (); - - /* main_loop */ - for (;;) { - WATCHDOG_RESET (); - main_loop (); - } -} - - -/***********************************************************************/ - -void hang (void) -{ - disable_interrupts (); - puts("### ERROR ### Please reset board ###\n"); - for (;;); -} diff --git a/lib_nios2/cache.S b/lib_nios2/cache.S deleted file mode 100644 index eb7735a..0000000 --- a/lib_nios2/cache.S +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2004, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - - .text - - .global flush_dcache - -flush_dcache: - add r5, r5, r4 - movhi r8, %hi(CFG_DCACHELINE_SIZE) - ori r8, r8, %lo(CFG_DCACHELINE_SIZE) -0: flushd 0(r4) - add r4, r4, r8 - bltu r4, r5, 0b - ret - - - .global flush_icache - -flush_icache: - add r5, r5, r4 - movhi r8, %hi(CFG_ICACHELINE_SIZE) - ori r8, r8, %lo(CFG_ICACHELINE_SIZE) -1: flushi r4 - add r4, r4, r8 - bltu r4, r5, 1b - ret - - .global flush_cache - -flush_cache: - add r5, r5, r4 - mov r9, r4 - mov r10, r5 - - movhi r8, %hi(CFG_DCACHELINE_SIZE) - ori r8, r8, %lo(CFG_DCACHELINE_SIZE) -0: flushd 0(r4) - add r4, r4, r8 - bltu r4, r5, 0b - - mov r4, r9 - mov r5, r10 - movhi r8, %hi(CFG_ICACHELINE_SIZE) - ori r8, r8, %lo(CFG_ICACHELINE_SIZE) -1: flushi r4 - add r4, r4, r8 - bltu r4, r5, 1b - - sync - flushp - ret diff --git a/lib_nios2/divmod.c b/lib_nios2/divmod.c deleted file mode 100644 index 3c7e71e..0000000 --- a/lib_nios2/divmod.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of GNU CC. - * - * GNU CC is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundation; either version 2, or (at your - * option) any later version. - * - * GNU CC is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with GNU CC; see the file COPYING. If not, write - * to the Free Software Foundation, 59 Temple Place - Suite 330, - * Boston, MA 02111-1307, USA. - */ - - -#include "math.h" - -USItype udivmodsi4 (USItype num, USItype den, word_type modwanted) -{ - USItype bit = 1; - USItype res = 0; - - while (den < num && bit && !(den & (1L << 31))) { - den <<= 1; - bit <<= 1; - } - while (bit) { - if (num >= den) { - num -= den; - res |= bit; - } - bit >>= 1; - den >>= 1; - } - if (modwanted) - return num; - return res; -} - - -SItype __divsi3 (SItype a, SItype b) -{ - word_type neg = 0; - SItype res; - - if (a < 0) { - a = -a; - neg = !neg; - } - - if (b < 0) { - b = -b; - neg = !neg; - } - - res = udivmodsi4 (a, b, 0); - - if (neg) - res = -res; - - return res; -} - - -SItype __modsi3 (SItype a, SItype b) -{ - word_type neg = 0; - SItype res; - - if (a < 0) { - a = -a; - neg = 1; - } - - if (b < 0) - b = -b; - - res = udivmodsi4 (a, b, 1); - - if (neg) - res = -res; - - return res; -} - - -SItype __udivsi3 (SItype a, SItype b) -{ - return udivmodsi4 (a, b, 0); -} - - -SItype __umodsi3 (SItype a, SItype b) -{ - return udivmodsi4 (a, b, 1); -} diff --git a/lib_nios2/math.h b/lib_nios2/math.h deleted file mode 100644 index ccffbbc..0000000 --- a/lib_nios2/math.h +++ /dev/null @@ -1,16 +0,0 @@ -#define BITS_PER_UNIT 8 - -typedef int HItype __attribute__ ((mode (HI))); -typedef unsigned int UHItype __attribute__ ((mode (HI))); - -typedef int SItype __attribute__ ((mode (SI))); -typedef unsigned int USItype __attribute__ ((mode (SI))); - -typedef int word_type __attribute__ ((mode (__word__))); - -struct SIstruct {HItype low, high;}; - -typedef union { - struct SIstruct s; - SItype ll; -} SIunion; diff --git a/lib_nios2/mult.c b/lib_nios2/mult.c deleted file mode 100644 index 66bb64d..0000000 --- a/lib_nios2/mult.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of GNU CC. - * - * GNU CC is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published - * by the Free Software Foundation; either version 2, or (at your - * option) any later version. - * - * GNU CC is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with GNU CC; see the file COPYING. If not, write - * to the Free Software Foundation, 59 Temple Place - Suite 330, - * Boston, MA 02111-1307, USA. - */ - - -#include - -#if !defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP) - -#include "math.h" - -USItype __mulsi3 (USItype a, USItype b) -{ - USItype c = 0; - - while (a != 0) { - if (a & 1) - c += b; - a >>= 1; - b <<= 1; - } - - return c; -} - - -UHItype __mulhi3 (UHItype a, UHItype b) -{ - UHItype c = 0; - - while (a != 0) { - if (a & 1) - c += b; - a >>= 1; - b <<= 1; - } - - return c; -} - -#endif /*!defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP) */ diff --git a/lib_nios2/nios_linux.c b/lib_nios2/nios_linux.c deleted file mode 100644 index 9eb3426..0000000 --- a/lib_nios2/nios_linux.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -extern image_header_t header; /* common/cmd_bootm.c */ - -void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], - ulong addr, ulong *len_ptr, int verify) -{ - image_header_t *hdr = &header; - void (*kernel)(void) = (void (*)(void))ntohl (hdr->ih_ep); - - /* For now we assume the Microtronix linux ... which only - * needs to be called ;-) - */ - kernel (); -} diff --git a/lib_nios2/time.c b/lib_nios2/time.c deleted file mode 100644 index 25a233e..0000000 --- a/lib_nios2/time.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation - * Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -extern void dly_clks( unsigned long ticks ); - -void udelay(unsigned long usec) -{ - /* The Nios core doesn't have a timebase, so we do our - * best for now and call a low-level loop that counts - * cpu clocks. - */ - unsigned long cnt = (CONFIG_SYS_CLK_FREQ/1000000) * usec; - WATCHDOG_RESET (); /* trigger watchdog if needed */ - dly_clks (cnt); -} diff --git a/lib_ppc/Makefile b/lib_ppc/Makefile deleted file mode 100644 index 652a419..0000000 --- a/lib_ppc/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(ARCH).a - -AOBJS = ppcstring.o ticks.o - -COBJS = board.o \ - bat_rw.o cache.o extable.o kgdb.o time.o interrupts.o - -OBJS = $(AOBJS) $(COBJS) - -$(LIB): .depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) - $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ - -sinclude .depend - -######################################################################### diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c deleted file mode 100644 index 912efa7..0000000 --- a/lib_ppc/bat_rw.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) -{ - switch (bat) { - case IBAT0: - mtspr (IBAT0L, lower); - mtspr (IBAT0U, upper); - break; - - case IBAT1: - mtspr (IBAT1L, lower); - mtspr (IBAT1U, upper); - break; - - case IBAT2: - mtspr (IBAT2L, lower); - mtspr (IBAT2U, upper); - break; - - case IBAT3: - mtspr (IBAT3L, lower); - mtspr (IBAT3U, upper); - break; - - case DBAT0: - mtspr (DBAT0L, lower); - mtspr (DBAT0U, upper); - break; - - case DBAT1: - mtspr (DBAT1L, lower); - mtspr (DBAT1U, upper); - break; - - case DBAT2: - mtspr (DBAT2L, lower); - mtspr (DBAT2U, upper); - break; - - case DBAT3: - mtspr (DBAT3L, lower); - mtspr (DBAT3U, upper); - break; - - default: - return (-1); - } - - return (0); -} - -int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower) -{ - unsigned long register u; - unsigned long register l; - - switch (bat) { - case IBAT0: - l = mfspr (IBAT0L); - u = mfspr (IBAT0U); - break; - - case IBAT1: - l = mfspr (IBAT1L); - u = mfspr (IBAT1U); - break; - - case IBAT2: - l = mfspr (IBAT2L); - u = mfspr (IBAT2U); - break; - - case IBAT3: - l = mfspr (IBAT3L); - u = mfspr (IBAT3U); - break; - - case DBAT0: - l = mfspr (DBAT0L); - u = mfspr (DBAT0U); - break; - - case DBAT1: - l = mfspr (DBAT1L); - u = mfspr (DBAT1U); - break; - - case DBAT2: - l = mfspr (DBAT2L); - u = mfspr (DBAT2U); - break; - - case DBAT3: - l = mfspr (DBAT3L); - u = mfspr (DBAT3U); - break; - - default: - return (-1); - } - - *upper = u; - *lower = l; - - return (0); -} diff --git a/lib_ppc/board.c b/lib_ppc/board.c deleted file mode 100644 index f40bb25..0000000 --- a/lib_ppc/board.c +++ /dev/null @@ -1,1199 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#ifdef CONFIG_8xx -#include -#endif -#ifdef CONFIG_5xx -#include -#endif -#ifdef CONFIG_MPC5xxx -#include -#endif -#if (CONFIG_COMMANDS & CFG_CMD_IDE) -#include -#endif -#if (CONFIG_COMMANDS & CFG_CMD_SCSI) -#include -#endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#include -#endif -#ifdef CONFIG_STATUS_LED -#include -#endif -#include -#include -#ifdef CFG_ALLOC_DPRAM -#if !defined(CONFIG_CPM2) -#include -#endif -#endif -#include -#if defined(CONFIG_BAB7xx) -#include -#endif -#include -#if defined(CONFIG_POST) -#include -#endif -#if defined(CONFIG_LOGBUFFER) -#include -#endif -#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500) -#include -#endif -#ifdef CONFIG_PS2KBD -#include -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -void doc_init (void); -#endif -#if defined(CONFIG_HARD_I2C) || \ - defined(CONFIG_SOFT_I2C) -#include -#endif -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -void nand_init (void); -#endif - -static char *failed = "*** failed ***\n"; - -#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU) -extern flash_info_t flash_info[]; -#endif - -#include -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CFG_ENV_IS_EMBEDDED) -#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN -#elif ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \ - (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \ - defined(CFG_ENV_IS_IN_NVRAM) -#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) -#else -#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN -#endif - -extern ulong __init_end; -extern ulong _end; -ulong monitor_flash_len; - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) -#include -#endif - -/* - * Begin and End of memory area for malloc(), and current "brk" - */ -static ulong mem_malloc_start = 0; -static ulong mem_malloc_end = 0; -static ulong mem_malloc_brk = 0; - -/************************************************************************ - * Utilities * - ************************************************************************ - */ - -/* - * The Malloc area is immediately below the monitor copy in DRAM - */ -static void mem_malloc_init (void) -{ - ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off; - - mem_malloc_end = dest_addr; - mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; - - memset ((void *) mem_malloc_start, - 0, - mem_malloc_end - mem_malloc_start); -} - -void *sbrk (ptrdiff_t increment) -{ - ulong old = mem_malloc_brk; - ulong new = old + increment; - - if ((new < mem_malloc_start) || (new > mem_malloc_end)) { - return (NULL); - } - mem_malloc_brk = new; - return ((void *) old); -} - -char *strmhz (char *buf, long hz) -{ - long l, n; - long m; - - n = hz / 1000000L; - l = sprintf (buf, "%ld", n); - m = (hz % 1000000L) / 1000L; - if (m != 0) - sprintf (buf + l, ".%03ld", m); - return (buf); -} - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ -typedef int (init_fnc_t) (void); - -/************************************************************************ - * Init Utilities * - ************************************************************************ - * Some of this code should be moved into the core functions, - * but let's get it working (again) first... - */ - -static int init_baudrate (void) -{ - char tmp[64]; /* long enough for environment variables */ - int i = getenv_r ("baudrate", tmp, sizeof (tmp)); - - gd->baudrate = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CONFIG_BAUDRATE; - return (0); -} - -/***********************************************************************/ - -#ifdef CONFIG_ADD_RAM_INFO -void board_add_ram_info(int); -#endif - -static int init_func_ram (void) -{ -#ifdef CONFIG_BOARD_TYPES - int board_type = gd->board_type; -#else - int board_type = 0; /* use dummy arg */ -#endif - puts ("DRAM: "); - - if ((gd->ram_size = initdram (board_type)) > 0) { - print_size (gd->ram_size, ""); -#ifdef CONFIG_ADD_RAM_INFO - board_add_ram_info(0); -#endif - putc('\n'); - return (0); - } - puts (failed); - return (1); -} - -/***********************************************************************/ - -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) -static int init_func_i2c (void) -{ - puts ("I2C: "); - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - puts ("ready\n"); - return (0); -} -#endif - -/***********************************************************************/ - -#if defined(CONFIG_WATCHDOG) -static int init_func_watchdog_init (void) -{ - puts (" Watchdog enabled\n"); - WATCHDOG_RESET (); - return (0); -} -# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init, - -static int init_func_watchdog_reset (void) -{ - WATCHDOG_RESET (); - return (0); -} -# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset, -#else -# define INIT_FUNC_WATCHDOG_INIT /* undef */ -# define INIT_FUNC_WATCHDOG_RESET /* undef */ -#endif /* CONFIG_WATCHDOG */ - -/************************************************************************ - * Initialization sequence * - ************************************************************************ - */ - -init_fnc_t *init_sequence[] = { - -#if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, -#endif - -#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) - get_clocks, /* get CPU and bus clocks (etc.) */ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) - adjust_sdram_tbs_8xx, -#endif - init_timebase, -#endif -#ifdef CFG_ALLOC_DPRAM -#if !defined(CONFIG_CPM2) - dpram_init, -#endif -#endif -#if defined(CONFIG_BOARD_POSTCLK_INIT) - board_postclk_init, -#endif - env_init, -#if defined(CONFIG_8xx_CPUCLK_DEFAULT) - get_clocks_866, /* get CPU and bus clocks according to the environment variable */ - sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */ - init_timebase, -#endif - init_baudrate, - serial_init, - console_init_f, - display_options, -#if defined(CONFIG_8260) - prt_8260_rsr, - prt_8260_clks, -#endif /* CONFIG_8260 */ - -#if defined(CONFIG_MPC83XX) - print_clock_conf, -#endif - - checkcpu, -#if defined(CONFIG_MPC5xxx) - prt_mpc5xxx_clks, -#endif /* CONFIG_MPC5xxx */ -#if defined(CONFIG_MPC8220) - prt_mpc8220_clks, -#endif - checkboard, - INIT_FUNC_WATCHDOG_INIT -#if defined(CONFIG_MISC_INIT_F) - misc_init_f, -#endif - INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) - init_func_i2c, -#endif -#if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */ - dtt_init, -#endif -#ifdef CONFIG_POST - post_init_f, -#endif - INIT_FUNC_WATCHDOG_RESET - init_func_ram, -#if defined(CFG_DRAM_TEST) - testdram, -#endif /* CFG_DRAM_TEST */ - INIT_FUNC_WATCHDOG_RESET - - NULL, /* Terminate this list */ -}; - -/************************************************************************ - * - * This is the first part of the initialization sequence that is - * implemented in C, but still running from ROM. - * - * The main purpose is to provide a (serial) console interface as - * soon as possible (so we can see any error messages), and to - * initialize the RAM so that we can relocate the monitor code to - * RAM. - * - * Be aware of the restrictions: global data is read-only, BSS is not - * initialized, and stack space is limited to a few kB. - * - ************************************************************************ - */ - -void board_init_f (ulong bootflag) -{ - bd_t *bd; - ulong len, addr, addr_sp; - ulong *s; - gd_t *id; - init_fnc_t **init_fnc_ptr; -#ifdef CONFIG_PRAM - int i; - ulong reg; - uchar tmp[64]; /* long enough for environment variables */ -#endif - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); - -#if !defined(CONFIG_CPM2) - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); -#endif - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - if ((*init_fnc_ptr) () != 0) { - hang (); - } - } - - /* - * Now that we have DRAM mapped and working, we can - * relocate the code and continue running from DRAM. - * - * Reserve memory at end of RAM for (top down in that order): - * - kernel log buffer - * - protected RAM - * - LCD framebuffer - * - monitor code - * - board info struct - */ - len = (ulong)&_end - CFG_MONITOR_BASE; - -#ifndef CONFIG_VERY_BIG_RAM - addr = CFG_SDRAM_BASE + gd->ram_size; -#else - /* only allow stack below 256M */ - addr = CFG_SDRAM_BASE + - (gd->ram_size > 256 << 20) ? 256 << 20 : gd->ram_size; -#endif - -#ifdef CONFIG_LOGBUFFER - /* reserve kernel log buffer */ - addr -= (LOGBUFF_RESERVE); - debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); -#endif - -#ifdef CONFIG_PRAM - /* - * reserve protected RAM - */ - i = getenv_r ("pram", (char *)tmp, sizeof (tmp)); - reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM; - addr -= (reg << 10); /* size is in kB */ - debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); -#endif /* CONFIG_PRAM */ - - /* round down to next 4 kB limit */ - addr &= ~(4096 - 1); - debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); - -#ifdef CONFIG_LCD - /* reserve memory for LCD display (always full pages) */ - addr = lcd_setmem (addr); - gd->fb_base = addr; -#endif /* CONFIG_LCD */ - -#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx) - /* reserve memory for video display (always full pages) */ - addr = video_setmem (addr); - gd->fb_base = addr; -#endif /* CONFIG_VIDEO */ - - /* - * reserve memory for U-Boot code, data & bss - * round down to next 4 kB limit - */ - addr -= len; - addr &= ~(4096 - 1); -#ifdef CONFIG_E500 - /* round down to next 64 kB limit so that IVPR stays aligned */ - addr &= ~(65536 - 1); -#endif - - debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); - -#ifdef CONFIG_AMIGAONEG3SE - gd->relocaddr = addr; -#endif - - /* - * reserve memory for malloc() arena - */ - addr_sp = addr - TOTAL_MALLOC_LEN; - debug ("Reserving %dk for malloc() at: %08lx\n", - TOTAL_MALLOC_LEN >> 10, addr_sp); - - /* - * (permanently) allocate a Board Info struct - * and a permanent copy of the "global" data - */ - addr_sp -= sizeof (bd_t); - bd = (bd_t *) addr_sp; - gd->bd = bd; - debug ("Reserving %d Bytes for Board Info at: %08lx\n", - sizeof (bd_t), addr_sp); - addr_sp -= sizeof (gd_t); - id = (gd_t *) addr_sp; - debug ("Reserving %d Bytes for Global Data at: %08lx\n", - sizeof (gd_t), addr_sp); - - /* - * Finally, we set up a new (bigger) stack. - * - * Leave some safety gap for SP, force alignment on 16 byte boundary - * Clear initial stack frame - */ - addr_sp -= 16; - addr_sp &= ~0xF; - s = (ulong *)addr_sp; - *s-- = 0; - *s-- = 0; - addr_sp = (ulong)s; - debug ("Stack Pointer at: %08lx\n", addr_sp); - - /* - * Save local variables to board info struct - */ - - bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ - bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ - -#ifdef CONFIG_IP860 - bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */ - bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */ -#elif defined CONFIG_MPC8220 - bd->bi_sramstart = CFG_SRAM_BASE; /* start of SRAM memory */ - bd->bi_sramsize = CFG_SRAM_SIZE; /* size of SRAM memory */ -#else - bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */ - bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */ -#endif - -#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ - defined(CONFIG_E500) - bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */ -#endif -#if defined(CONFIG_MPC5xxx) - bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ -#endif -#if defined(CONFIG_MPC83XX) - bd->bi_immrbar = CFG_IMMRBAR; -#endif -#if defined(CONFIG_MPC8220) - bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ - bd->bi_inpfreq = gd->inp_clk; - bd->bi_pcifreq = gd->pci_clk; - bd->bi_vcofreq = gd->vco_clk; - bd->bi_pevfreq = gd->pev_clk; - bd->bi_flbfreq = gd->flb_clk; - - /* store bootparam to sram (backward compatible), here? */ - { - u32 *sram = (u32 *)CFG_SRAM_BASE; - *sram++ = gd->ram_size; - *sram++ = gd->bus_clk; - *sram++ = gd->inp_clk; - *sram++ = gd->cpu_clk; - *sram++ = gd->vco_clk; - *sram++ = gd->flb_clk; - *sram++ = 0xb8c3ba11; /* boot signature */ - } -#endif - - bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ - - WATCHDOG_RESET (); - bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ - bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ -#if defined(CONFIG_CPM2) - bd->bi_cpmfreq = gd->cpm_clk; - bd->bi_brgfreq = gd->brg_clk; - bd->bi_sccfreq = gd->scc_clk; - bd->bi_vco = gd->vco_out; -#endif /* CONFIG_CPM2 */ -#if defined(CONFIG_MPC5xxx) - bd->bi_ipbfreq = gd->ipb_clk; - bd->bi_pcifreq = gd->pci_clk; -#endif /* CONFIG_MPC5xxx */ - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ - -#ifdef CFG_EXTBDINFO - strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); - strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version)); - - bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ - bd->bi_plb_busfreq = gd->bus_clk; -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - bd->bi_pci_busfreq = get_PCI_freq (); - bd->bi_opbfreq = get_OPB_freq (); -#elif defined(CONFIG_XILINX_ML300) - bd->bi_pci_busfreq = get_PCI_freq (); -#endif -#endif - - debug ("New Stack Pointer is: %08lx\n", addr_sp); - - WATCHDOG_RESET (); - -#ifdef CONFIG_POST - post_bootmode_init(); - post_run (NULL, POST_ROM | post_bootmode_get(0)); -#endif - - WATCHDOG_RESET(); - - memcpy (id, (void *)gd, sizeof (gd_t)); - - relocate_code (addr_sp, id, addr); - - /* NOTREACHED - relocate_code() does not return */ -} - -/************************************************************************ - * - * This is the next part if the initialization sequence: we are now - * running from RAM and have a "normal" C environment, i. e. global - * data can be written, BSS has been cleared, the stack size in not - * that critical any more, etc. - * - ************************************************************************ - */ -void board_init_r (gd_t *id, ulong dest_addr) -{ - cmd_tbl_t *cmdtp; - char *s, *e; - bd_t *bd; - int i; - extern void malloc_bin_reloc (void); -#ifndef CFG_ENV_IS_NOWHERE - extern char * env_name_spec; -#endif - -#ifndef CFG_NO_FLASH - ulong flash_size; -#endif - - gd = id; /* initialize RAM version of global data */ - bd = gd->bd; - - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - - debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); - - WATCHDOG_RESET (); - -#if defined(CONFIG_BOARD_EARLY_INIT_R) - board_early_init_r (); -#endif - - gd->reloc_off = dest_addr - CFG_MONITOR_BASE; - - monitor_flash_len = (ulong)&__init_end - dest_addr; - -#ifdef CONFIG_SERIAL_MULTI - serial_initialize(); -#endif - - /* - * We have to relocate the command table manually - */ - for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { - ulong addr; - addr = (ulong) (cmdtp->cmd) + gd->reloc_off; -#if 0 - printf ("Command \"%s\": 0x%08lx => 0x%08lx\n", - cmdtp->name, (ulong) (cmdtp->cmd), addr); -#endif - cmdtp->cmd = - (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; - - addr = (ulong)(cmdtp->name) + gd->reloc_off; - cmdtp->name = (char *)addr; - - if (cmdtp->usage) { - addr = (ulong)(cmdtp->usage) + gd->reloc_off; - cmdtp->usage = (char *)addr; - } -#ifdef CFG_LONGHELP - if (cmdtp->help) { - addr = (ulong)(cmdtp->help) + gd->reloc_off; - cmdtp->help = (char *)addr; - } -#endif - } - /* there are some other pointer constants we must deal with */ -#ifndef CFG_ENV_IS_NOWHERE - env_name_spec += gd->reloc_off; -#endif - - WATCHDOG_RESET (); - -#ifdef CONFIG_LOGBUFFER - logbuff_init_ptrs (); -#endif -#ifdef CONFIG_POST - post_output_backlog (); - post_reloc (); -#endif - - WATCHDOG_RESET(); - -#if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM) - icache_enable (); /* it's time to enable the instruction cache */ -#endif - -#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500) - unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ -#endif - -#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45) - /* - * Do PCI configuration on BAB7xx and CPC45 _before_ the flash - * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus - * bridge there. - */ - pci_init (); -#endif -#if defined(CONFIG_BAB7xx) - /* - * Initialise the ISA bridge - */ - initialise_w83c553f (); -#endif - - asm ("sync ; isync"); - - /* - * Setup trap handlers - */ - trap_init (dest_addr); - -#if !defined(CFG_NO_FLASH) - puts ("FLASH: "); - - if ((flash_size = flash_init ()) > 0) { -# ifdef CFG_FLASH_CHECKSUM - print_size (flash_size, ""); - /* - * Compute and print flash CRC if flashchecksum is set to 'y' - * - * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX - */ - s = getenv ("flashchecksum"); - if (s && (*s == 'y')) { - printf (" CRC: %08lX", - crc32 (0, (const unsigned char *) CFG_FLASH_BASE, flash_size) - ); - } - putc ('\n'); -# else /* !CFG_FLASH_CHECKSUM */ - print_size (flash_size, "\n"); -# endif /* CFG_FLASH_CHECKSUM */ - } else { - puts (failed); - hang (); - } - - bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */ - bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */ -# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU) - /* flash mapped at end of memory map */ - bd->bi_flashoffset = TEXT_BASE + flash_size; -# elif CFG_MONITOR_BASE == CFG_FLASH_BASE - bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */ -# else - bd->bi_flashoffset = 0; -# endif -#else /* CFG_NO_FLASH */ - - bd->bi_flashsize = 0; - bd->bi_flashstart = 0; - bd->bi_flashoffset = 0; -#endif /* !CFG_NO_FLASH */ - - WATCHDOG_RESET (); - - /* initialize higher level parts of CPU like time base and timers */ - cpu_init_r (); - - WATCHDOG_RESET (); - - /* initialize malloc() area */ - mem_malloc_init (); - malloc_bin_reloc (); - -#ifdef CONFIG_SPI -# if !defined(CFG_ENV_IS_IN_EEPROM) - spi_init_f (); -# endif - spi_init_r (); -#endif - - /* relocate environment function pointers etc. */ - env_relocate (); - - /* - * Fill in missing fields of bd_info. - * We do this here, where we have "normal" access to the - * environment; we used to do this still running from ROM, - * where had to use getenv_r(), which can be pretty slow when - * the environment is in EEPROM. - */ - -#if defined(CFG_EXTBDINFO) -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) -#if defined(CONFIG_I2CFAST) - /* - * set bi_iic_fast for linux taking environment variable - * "i2cfast" into account - */ - { - char *s = getenv ("i2cfast"); - if (s && ((*s == 'y') || (*s == 'Y'))) { - bd->bi_iic_fast[0] = 1; - bd->bi_iic_fast[1] = 1; - } else { - bd->bi_iic_fast[0] = 0; - bd->bi_iic_fast[1] = 0; - } - } -#else - bd->bi_iic_fast[0] = 0; - bd->bi_iic_fast[1] = 0; -#endif /* CONFIG_I2CFAST */ -#endif /* CONFIG_405GP, CONFIG_405EP */ -#endif /* CFG_EXTBDINFO */ - - s = getenv ("ethaddr"); -#if defined (CONFIG_MBX) || defined (CONFIG_RPXCLASSIC) || defined(CONFIG_IAD210) - if (s == NULL) - board_get_enetaddr (bd->bi_enetaddr); - else -#endif - for (i = 0; i < 6; ++i) { - bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } -#ifdef CONFIG_HERMES - if ((gd->board_type >> 16) == 2) - bd->bi_ethspeed = gd->board_type & 0xFFFF; - else - bd->bi_ethspeed = 0xFFFF; -#endif - -#ifdef CONFIG_NX823 - load_sernum_ethaddr (); -#endif - -#ifdef CONFIG_HAS_ETH1 - /* handle the 2nd ethernet address */ - - s = getenv ("eth1addr"); - - for (i = 0; i < 6; ++i) { - bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } -#endif -#ifdef CONFIG_HAS_ETH2 - /* handle the 3rd ethernet address */ - - s = getenv ("eth2addr"); -#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) - if (s == NULL) - board_get_enetaddr(bd->bi_enet2addr); - else -#endif - for (i = 0; i < 6; ++i) { - bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } -#endif - -#ifdef CONFIG_HAS_ETH3 - /* handle 4th ethernet address */ - s = getenv("eth3addr"); -#if defined(CONFIG_XPEDITE1K) || defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) - if (s == NULL) - board_get_enetaddr(bd->bi_enet3addr); - else -#endif - for (i = 0; i < 6; ++i) { - bd->bi_enet3addr[i] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } -#endif - -#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \ - defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) - load_sernum_ethaddr (); -#endif - /* IP Address */ - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); - - WATCHDOG_RESET (); - -#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45) - /* - * Do pci configuration - */ - pci_init (); -#endif - -/** leave this here (after malloc(), environment and PCI are working) **/ - /* Initialize devices */ - devices_init (); - - /* Initialize the jump table for applications */ - jumptable_init (); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r (); - -#if defined(CONFIG_CCM) || \ - defined(CONFIG_COGENT) || \ - defined(CONFIG_CPCI405) || \ - defined(CONFIG_EVB64260) || \ - defined(CONFIG_KUP4K) || \ - defined(CONFIG_KUP4X) || \ - defined(CONFIG_LWMON) || \ - defined(CONFIG_PCU_E) || \ - defined(CONFIG_W7O) || \ - defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r (); -#endif - -#ifdef CONFIG_HERMES - if (bd->bi_ethspeed != 0xFFFF) - hermes_start_lxt980 ((int) bd->bi_ethspeed); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - WATCHDOG_RESET (); - puts ("KGDB: "); - kgdb_init (); -#endif - - debug ("U-Boot relocated to %08lx\n", dest_addr); - - /* - * Enable Interrupts - */ - interrupt_init (); - - /* Must happen after interrupts are initialized since - * an irq handler gets installed - */ -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - serial_buffered_init(); -#endif - -#ifdef CONFIG_STATUS_LED - status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); -#endif - - udelay (20); - - set_timer (0); - - /* Initialize from environment */ - if ((s = getenv ("loadaddr")) != NULL) { - load_addr = simple_strtoul (s, NULL, 16); - } -#if (CONFIG_COMMANDS & CFG_CMD_NET) - if ((s = getenv ("bootfile")) != NULL) { - copy_filename (BootFile, s, sizeof (BootFile)); - } -#endif /* CFG_CMD_NET */ - - WATCHDOG_RESET (); - -#if (CONFIG_COMMANDS & CFG_CMD_SCSI) - WATCHDOG_RESET (); - puts ("SCSI: "); - scsi_init (); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) - WATCHDOG_RESET (); - puts ("DOC: "); - doc_init (); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) - WATCHDOG_RESET (); - puts ("NAND: "); - nand_init(); /* go init the NAND */ -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NET) -#if defined(CONFIG_NET_MULTI) - WATCHDOG_RESET (); - puts ("Net: "); -#endif - eth_initialize (bd); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \ - defined(CONFIG_CCM) || \ - defined(CONFIG_ELPT860) || \ - defined(CONFIG_EP8260) || \ - defined(CONFIG_IP860) || \ - defined(CONFIG_IVML24) || \ - defined(CONFIG_IVMS8) || \ - defined(CONFIG_MPC8260ADS) || \ - defined(CONFIG_MPC8266ADS) || \ - defined(CONFIG_MPC8560ADS) || \ - defined(CONFIG_PCU_E) || \ - defined(CONFIG_RPXSUPER) || \ - defined(CONFIG_STXGP3) || \ - defined(CONFIG_SPD823TS) || \ - defined(CONFIG_RESET_PHY_R) ) - - WATCHDOG_RESET (); - debug ("Reset Ethernet PHY\n"); - reset_phy (); -#endif - -#ifdef CONFIG_POST - post_run (NULL, POST_RAM | post_bootmode_get(0)); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE) - WATCHDOG_RESET (); - puts ("PCMCIA:"); - pcmcia_init (); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_IDE) - WATCHDOG_RESET (); -# ifdef CONFIG_IDE_8xx_PCCARD - puts ("PCMCIA:"); -# else - puts ("IDE: "); -#endif - ide_init (); -#endif /* CFG_CMD_IDE */ - -#ifdef CONFIG_LAST_STAGE_INIT - WATCHDOG_RESET (); - /* - * Some parts can be only initialized if all others (like - * Interrupts) are up and running (i.e. the PC-style ISA - * keyboard). - */ - last_stage_init (); -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - WATCHDOG_RESET (); - bedbug_init (); -#endif - -#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) - /* - * Export available size of memory for Linux, - * taking into account the protected RAM at top of memory - */ - { - ulong pram; - uchar memsz[32]; -#ifdef CONFIG_PRAM - char *s; - - if ((s = getenv ("pram")) != NULL) { - pram = simple_strtoul (s, NULL, 10); - } else { - pram = CONFIG_PRAM; - } -#else - pram=0; -#endif -#ifdef CONFIG_LOGBUFFER - /* Also take the logbuffer into account (pram is in kB) */ - pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024; -#endif - sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram); - setenv ("mem", (char *)memsz); - } -#endif - -#ifdef CONFIG_PS2KBD - puts ("PS/2: "); - kbd_init(); -#endif - -#ifdef CONFIG_MODEM_SUPPORT - { - extern int do_mdm_init; - do_mdm_init = gd->do_mdm_init; - } -#endif - - /* Initialization complete - start the monitor */ - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) { - WATCHDOG_RESET (); - main_loop (); - } - - /* NOTREACHED - no way out of command loop except booting */ -} - -void hang (void) -{ - puts ("### ERROR ### Please RESET the board ###\n"); -#ifdef CONFIG_SHOW_BOOT_PROGRESS - show_boot_progress(-30); -#endif - for (;;); -} - -#ifdef CONFIG_MODEM_SUPPORT -/* called from main loop (common/main.c) */ -/* 'inline' - We have to do it fast */ -static inline void mdm_readline(char *buf, int bufsiz) -{ - char c; - char *p; - int n; - - n = 0; - p = buf; - for(;;) { - c = serial_getc(); - - /* dbg("(%c)", c); */ - - switch(c) { - case '\r': - break; - case '\n': - *p = '\0'; - return; - - default: - if(n++ > bufsiz) { - *p = '\0'; - return; /* sanity check */ - } - *p = c; - p++; - break; - } - } -} - -extern void dbg(const char *fmt, ...); -int mdm_init (void) -{ - char env_str[16]; - char *init_str; - int i; - extern char console_buffer[]; - extern void enable_putc(void); - extern int hwflow_onoff(int); - - enable_putc(); /* enable serial_putc() */ - -#ifdef CONFIG_HWFLOW - init_str = getenv("mdm_flow_control"); - if (init_str && (strcmp(init_str, "rts/cts") == 0)) - hwflow_onoff (1); - else - hwflow_onoff(-1); -#endif - - for (i = 1;;i++) { - sprintf(env_str, "mdm_init%d", i); - if ((init_str = getenv(env_str)) != NULL) { - serial_puts(init_str); - serial_puts("\n"); - for(;;) { - mdm_readline(console_buffer, CFG_CBSIZE); - dbg("ini%d: [%s]", i, console_buffer); - - if ((strcmp(console_buffer, "OK") == 0) || - (strcmp(console_buffer, "ERROR") == 0)) { - dbg("ini%d: cmd done", i); - break; - } else /* in case we are originating call ... */ - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini%d: connect", i); - return 0; - } - } - } else - break; /* no init string - stop modem init */ - - udelay(100000); - } - - udelay(100000); - - /* final stage - wait for connect */ - for(;i > 1;) { /* if 'i' > 1 - wait for connection - message from modem */ - mdm_readline(console_buffer, CFG_CBSIZE); - dbg("ini_f: [%s]", console_buffer); - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini_f: connected"); - return 0; - } - } - - return 0; -} - -#endif - -#if 0 /* We could use plain global data, but the resulting code is bigger */ -/* - * Pointer to initial global data area - * - * Here we initialize it. - */ -#undef XTRN_DECLARE_GLOBAL_DATA_PTR -#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ -DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); -#endif /* 0 */ - -/************************************************************************/ diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c deleted file mode 100644 index a81ab5e..0000000 --- a/lib_ppc/cache.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - - -void flush_cache (ulong start_addr, ulong size) -{ -#ifndef CONFIG_5xx - ulong addr, end_addr = start_addr + size; - - if (CFG_CACHELINE_SIZE) { - addr = start_addr & (CFG_CACHELINE_SIZE - 1); - for (addr = start_addr; - addr < end_addr; - addr += CFG_CACHELINE_SIZE) { - asm ("dcbst 0,%0": :"r" (addr)); - } - asm ("sync"); /* Wait for all dcbst to complete on bus */ - - for (addr = start_addr; - addr < end_addr; - addr += CFG_CACHELINE_SIZE) { - asm ("icbi 0,%0": :"r" (addr)); - } - } - asm ("sync"); /* Always flush prefetch queue in any case */ - asm ("isync"); -#endif -} diff --git a/lib_ppc/extable.c b/lib_ppc/extable.c deleted file mode 100644 index d92f142..0000000 --- a/lib_ppc/extable.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (C) 1999 Magnus Damm - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include - -/* - * The exception table consists of pairs of addresses: the first is the - * address of an instruction that is allowed to fault, and the second is - * the address at which the program should continue. No registers are - * modified, so it is entirely up to the continuation code to figure out - * what to do. - * - * All the routines below use bits of fixup code that are out of line - * with the main instruction path. This means when everything is well, - * we don't even have to jump over them. Further, they do not intrude - * on our cache or tlb entries. - */ - -struct exception_table_entry -{ - unsigned long insn, fixup; -}; - -extern const struct exception_table_entry __start___ex_table[]; -extern const struct exception_table_entry __stop___ex_table[]; - -static inline unsigned long -search_one_table(const struct exception_table_entry *first, - const struct exception_table_entry *last, - unsigned long value) -{ - while (first <= last) { - const struct exception_table_entry *mid; - long diff; - - mid = (last - first) / 2 + first; - diff = mid->insn - value; - if (diff == 0) - return mid->fixup; - else if (diff < 0) - first = mid+1; - else - last = mid-1; - } - return 0; -} - -int ex_tab_message = 1; - -unsigned long -search_exception_table(unsigned long addr) -{ - unsigned long ret; - - /* There is only the kernel to search. */ - ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr); - if (ex_tab_message) - printf("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret); - if (ret) return ret; - - return 0; -} diff --git a/lib_ppc/interrupts.c b/lib_ppc/interrupts.c deleted file mode 100644 index b803952..0000000 --- a/lib_ppc/interrupts.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Gleb Natapov - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#ifdef CONFIG_STATUS_LED -#include -#endif - -#ifdef CONFIG_SHOW_ACTIVITY - extern void board_show_activity (ulong); -#endif /* CONFIG_SHOW_ACTIVITY */ - -#ifndef CFG_WATCHDOG_FREQ -#define CFG_WATCHDOG_FREQ (CFG_HZ / 2) -#endif - -extern int interrupt_init_cpu (unsigned *); -extern void timer_interrupt_cpu (struct pt_regs *); - -static unsigned decrementer_count; /* count value for 1e6/HZ microseconds */ - -static __inline__ unsigned long get_msr (void) -{ - unsigned long msr; - - asm volatile ("mfmsr %0":"=r" (msr):); - - return msr; -} - -static __inline__ void set_msr (unsigned long msr) -{ - asm volatile ("mtmsr %0"::"r" (msr)); -} - -static __inline__ unsigned long get_dec (void) -{ - unsigned long val; - - asm volatile ("mfdec %0":"=r" (val):); - - return val; -} - - -static __inline__ void set_dec (unsigned long val) -{ - if (val) - asm volatile ("mtdec %0"::"r" (val)); -} - - -void enable_interrupts (void) -{ - set_msr (get_msr () | MSR_EE); -} - -/* returns flag if MSR_EE was set before */ -int disable_interrupts (void) -{ - ulong msr = get_msr (); - - set_msr (msr & ~MSR_EE); - return ((msr & MSR_EE) != 0); -} - -int interrupt_init (void) -{ - int ret; - - /* call cpu specific function from $(CPU)/interrupts.c */ - ret = interrupt_init_cpu (&decrementer_count); - - if (ret) - return ret; - - set_dec (decrementer_count); - - set_msr (get_msr () | MSR_EE); - - return (0); -} - -static volatile ulong timestamp = 0; - -void timer_interrupt (struct pt_regs *regs) -{ - /* call cpu specific function from $(CPU)/interrupts.c */ - timer_interrupt_cpu (regs); - - /* Restore Decrementer Count */ - set_dec (decrementer_count); - - timestamp++; - -#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) - if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) - WATCHDOG_RESET (); -#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ - -#ifdef CONFIG_STATUS_LED - status_led_tick (timestamp); -#endif /* CONFIG_STATUS_LED */ - -#ifdef CONFIG_SHOW_ACTIVITY - board_show_activity (timestamp); -#endif /* CONFIG_SHOW_ACTIVITY */ -} - -void reset_timer (void) -{ - timestamp = 0; -} - -ulong get_timer (ulong base) -{ - return (timestamp - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} diff --git a/lib_ppc/kgdb.c b/lib_ppc/kgdb.c deleted file mode 100644 index 4c5d79a..0000000 --- a/lib_ppc/kgdb.c +++ /dev/null @@ -1,326 +0,0 @@ -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - -#include -#include -#include - -#define PC_REGNUM 64 -#define SP_REGNUM 1 - -void breakinst(void); - -int -kgdb_setjmp(long *buf) -{ - asm ("mflr 0; stw 0,0(%0);" - "stw 1,4(%0); stw 2,8(%0);" - "mfcr 0; stw 0,12(%0);" - "stmw 13,16(%0)" - : : "r" (buf)); - /* XXX should save fp regs as well */ - return 0; -} - -void -kgdb_longjmp(long *buf, int val) -{ - if (val == 0) - val = 1; - asm ("lmw 13,16(%0);" - "lwz 0,12(%0); mtcrf 0x38,0;" - "lwz 0,0(%0); lwz 1,4(%0); lwz 2,8(%0);" - "mtlr 0; mr 3,%1" - : : "r" (buf), "r" (val)); -} - -static inline unsigned long -get_msr(void) -{ - unsigned long msr; - asm volatile("mfmsr %0" : "=r" (msr):); - return msr; -} - -static inline void -set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -/* Convert the SPARC hardware trap type code to a unix signal number. */ -/* - * This table contains the mapping between PowerPC hardware trap types, and - * signals, which are primarily what GDB understands. - */ -static struct hard_trap_info -{ - unsigned int tt; /* Trap type code for powerpc */ - unsigned char signo; /* Signal that we map this trap into */ -} hard_trap_info[] = { - { 0x200, SIGSEGV }, /* machine check */ - { 0x300, SIGSEGV }, /* address error (store) */ - { 0x400, SIGBUS }, /* instruction bus error */ - { 0x500, SIGINT }, /* interrupt */ - { 0x600, SIGBUS }, /* alingment */ - { 0x700, SIGTRAP }, /* breakpoint trap */ - { 0x800, SIGFPE }, /* fpu unavail */ - { 0x900, SIGALRM }, /* decrementer */ - { 0xa00, SIGILL }, /* reserved */ - { 0xb00, SIGILL }, /* reserved */ - { 0xc00, SIGCHLD }, /* syscall */ - { 0xd00, SIGTRAP }, /* single-step/watch */ - { 0xe00, SIGFPE }, /* fp assist */ - { 0, 0} /* Must be last */ -}; - -static int -computeSignal(unsigned int tt) -{ - struct hard_trap_info *ht; - - for (ht = hard_trap_info; ht->tt && ht->signo; ht++) - if (ht->tt == tt) - return ht->signo; - - return SIGHUP; /* default for things we don't know about */ -} - -void -kgdb_enter(struct pt_regs *regs, kgdb_data *kdp) -{ - unsigned long msr; - - kdp->private[0] = msr = get_msr(); - set_msr(msr & ~MSR_EE); /* disable interrupts */ - - if (regs->nip == (unsigned long)breakinst) { - /* Skip over breakpoint trap insn */ - regs->nip += 4; - } - regs->msr &= ~MSR_SE; - - /* reply to host that an exception has occurred */ - kdp->sigval = computeSignal(regs->trap); - - kdp->nregs = 2; - - kdp->regs[0].num = PC_REGNUM; - kdp->regs[0].val = regs->nip; - - kdp->regs[1].num = SP_REGNUM; - kdp->regs[1].val = regs->gpr[SP_REGNUM]; -} - -void -kgdb_exit(struct pt_regs *regs, kgdb_data *kdp) -{ - unsigned long msr = kdp->private[0]; - - if (kdp->extype & KGDBEXIT_WITHADDR) - regs->nip = kdp->exaddr; - - switch (kdp->extype & KGDBEXIT_TYPEMASK) { - - case KGDBEXIT_KILL: - case KGDBEXIT_CONTINUE: - set_msr(msr); - break; - - case KGDBEXIT_SINGLE: - regs->msr |= MSR_SE; -#if 0 - set_msr(msr | MSR_SE); -#endif - break; - } -} - -int -kgdb_trap(struct pt_regs *regs) -{ - return (regs->trap); -} - -/* return the value of the CPU registers. - * some of them are non-PowerPC names :( - * they are stored in gdb like: - * struct { - * u32 gpr[32]; - * f64 fpr[32]; - * u32 pc, ps, cnd, lr; (ps=msr) - * u32 cnt, xer, mq; - * } - */ - -#define SPACE_REQUIRED ((32*4)+(32*8)+(6*4)) - -#ifdef CONFIG_8260 -/* store floating double indexed */ -#define STFDI(n,p) __asm__ __volatile__ ("stfd " #n ",%0" : "=o"(p[2*n])) -/* store floating double multiple */ -#define STFDM(p) { STFDI( 0,p); STFDI( 1,p); STFDI( 2,p); STFDI( 3,p); \ - STFDI( 4,p); STFDI( 5,p); STFDI( 6,p); STFDI( 7,p); \ - STFDI( 8,p); STFDI( 9,p); STFDI(10,p); STFDI(11,p); \ - STFDI(12,p); STFDI(13,p); STFDI(14,p); STFDI(15,p); \ - STFDI(16,p); STFDI(17,p); STFDI(18,p); STFDI(19,p); \ - STFDI(20,p); STFDI(21,p); STFDI(22,p); STFDI(23,p); \ - STFDI(24,p); STFDI(25,p); STFDI(26,p); STFDI(27,p); \ - STFDI(28,p); STFDI(29,p); STFDI(30,p); STFDI(31,p); } -#endif - -int -kgdb_getregs(struct pt_regs *regs, char *buf, int max) -{ - int i; - unsigned long *ptr = (unsigned long *)buf; - - if (max < SPACE_REQUIRED) - kgdb_error(KGDBERR_NOSPACE); - - if ((unsigned long)ptr & 3) - kgdb_error(KGDBERR_ALIGNFAULT); - - /* General Purpose Regs */ - for (i = 0; i < 32; i++) - *ptr++ = regs->gpr[i]; - - /* Floating Point Regs */ -#ifdef CONFIG_8260 - STFDM(ptr); - ptr += 32*2; -#else - for (i = 0; i < 32; i++) { - *ptr++ = 0; - *ptr++ = 0; - } -#endif - - /* pc, msr, cr, lr, ctr, xer, (mq is unused) */ - *ptr++ = regs->nip; - *ptr++ = regs->msr; - *ptr++ = regs->ccr; - *ptr++ = regs->link; - *ptr++ = regs->ctr; - *ptr++ = regs->xer; - - return (SPACE_REQUIRED); -} - -/* set the value of the CPU registers */ - -#ifdef CONFIG_8260 -/* load floating double */ -#define LFD(n,v) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"(v)) -/* load floating double indexed */ -#define LFDI(n,p) __asm__ __volatile__ ("lfd " #n ",%0" :: "o"((p)[2*n])) -/* load floating double multiple */ -#define LFDM(p) { LFDI( 0,p); LFDI( 1,p); LFDI( 2,p); LFDI( 3,p); \ - LFDI( 4,p); LFDI( 5,p); LFDI( 6,p); LFDI( 7,p); \ - LFDI( 8,p); LFDI( 9,p); LFDI(10,p); LFDI(11,p); \ - LFDI(12,p); LFDI(13,p); LFDI(14,p); LFDI(15,p); \ - LFDI(16,p); LFDI(17,p); LFDI(18,p); LFDI(19,p); \ - LFDI(20,p); LFDI(21,p); LFDI(22,p); LFDI(23,p); \ - LFDI(24,p); LFDI(25,p); LFDI(26,p); LFDI(27,p); \ - LFDI(28,p); LFDI(29,p); LFDI(30,p); LFDI(31,p); } -#endif - -void -kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length) -{ - unsigned long *ptr = (unsigned long *)buf; - - if (regno < 0 || regno >= 70) - kgdb_error(KGDBERR_BADPARAMS); - else if (regno >= 32 && regno < 64) { - if (length < 8) - kgdb_error(KGDBERR_NOSPACE); - } - else { - if (length < 4) - kgdb_error(KGDBERR_NOSPACE); - } - - if ((unsigned long)ptr & 3) - kgdb_error(KGDBERR_ALIGNFAULT); - - if (regno >= 0 && regno < 32) - regs->gpr[regno] = *ptr; - else switch (regno) { - -#ifdef CONFIG_8260 -#define caseF(n) \ - case (n) + 32: LFD(n, *ptr); break; - -caseF( 0) caseF( 1) caseF( 2) caseF( 3) caseF( 4) caseF( 5) caseF( 6) caseF( 7) -caseF( 8) caseF( 9) caseF(10) caseF(11) caseF(12) caseF(13) caseF(14) caseF(15) -caseF(16) caseF(17) caseF(18) caseF(19) caseF(20) caseF(21) caseF(22) caseF(23) -caseF(24) caseF(25) caseF(26) caseF(27) caseF(28) caseF(29) caseF(30) caseF(31) - -#undef caseF -#endif - - case 64: regs->nip = *ptr; break; - case 65: regs->msr = *ptr; break; - case 66: regs->ccr = *ptr; break; - case 67: regs->link = *ptr; break; - case 68: regs->ctr = *ptr; break; - case 69: regs->ctr = *ptr; break; - - default: - kgdb_error(KGDBERR_BADPARAMS); - } -} - -void -kgdb_putregs(struct pt_regs *regs, char *buf, int length) -{ - int i; - unsigned long *ptr = (unsigned long *)buf; - - if (length < SPACE_REQUIRED) - kgdb_error(KGDBERR_NOSPACE); - - if ((unsigned long)ptr & 3) - kgdb_error(KGDBERR_ALIGNFAULT); - - /* - * If the stack pointer has moved, you should pray. - * (cause only god can help you). - */ - - /* General Purpose Regs */ - for (i = 0; i < 32; i++) - regs->gpr[i] = *ptr++; - - /* Floating Point Regs */ -#ifdef CONFIG_8260 - LFDM(ptr); -#endif - ptr += 32*2; - - /* pc, msr, cr, lr, ctr, xer, (mq is unused) */ - regs->nip = *ptr++; - regs->msr = *ptr++; - regs->ccr = *ptr++; - regs->link = *ptr++; - regs->ctr = *ptr++; - regs->xer = *ptr++; -} - -/* This function will generate a breakpoint exception. It is used at the - beginning of a program to sync up with a debugger and can be used - otherwise as a quick means to stop program execution and "break" into - the debugger. */ - -void -kgdb_breakpoint(int argc, char *argv[]) -{ - asm(" .globl breakinst\n\ - breakinst: .long 0x7d821008\n\ - "); -} - -#endif /* CFG_CMD_KGDB */ diff --git a/lib_ppc/ppcstring.S b/lib_ppc/ppcstring.S deleted file mode 100644 index 97023a0..0000000 --- a/lib_ppc/ppcstring.S +++ /dev/null @@ -1,216 +0,0 @@ -/* - * String handling functions for PowerPC. - * - * Copyright (C) 1996 Paul Mackerras. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#include -#include - - .globl strcpy -strcpy: - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r5) - bne 1b - blr - - .globl strncpy -strncpy: - cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r6,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r6) - bdnzf 2,1b /* dec ctr, branch if ctr != 0 && !cr0.eq */ - blr - - .globl strcat -strcat: - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r5) - cmpwi 0,r0,0 - bne 1b - addi r5,r5,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r5) - bne 1b - blr - - .globl strcmp -strcmp: - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r3,1(r5) - cmpwi 1,r3,0 - lbzu r0,1(r4) - subf. r3,r0,r3 - beqlr 1 - beq 1b - blr - - .globl strlen -strlen: - addi r4,r3,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - bne 1b - subf r3,r3,r4 - blr - - .globl memset -memset: - rlwimi r4,r4,8,16,23 - rlwimi r4,r4,16,0,15 - addi r6,r3,-4 - cmplwi 0,r5,4 - blt 7f - stwu r4,4(r6) - beqlr - andi. r0,r6,3 - add r5,r0,r5 - subf r6,r0,r6 - rlwinm r0,r5,32-2,2,31 - mtctr r0 - bdz 6f -1: stwu r4,4(r6) - bdnz 1b -6: andi. r5,r5,3 -7: cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r6,r6,3 -8: stbu r4,1(r6) - bdnz 8b - blr - - .globl bcopy -bcopy: - mr r6,r3 - mr r3,r4 - mr r4,r6 - b memcpy - - .globl memmove -memmove: - cmplw 0,r3,r4 - bgt backwards_memcpy - /* fall through */ - - .globl memcpy -memcpy: - rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ - addi r6,r3,-4 - addi r4,r4,-4 - beq 2f /* if less than 8 bytes to do */ - andi. r0,r6,3 /* get dest word aligned */ - mtctr r7 - bne 5f -1: lwz r7,4(r4) - lwzu r8,8(r4) - stw r7,4(r6) - stwu r8,8(r6) - bdnz 1b - andi. r5,r5,7 -2: cmplwi 0,r5,4 - blt 3f - lwzu r0,4(r4) - addi r5,r5,-4 - stwu r0,4(r6) -3: cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r4,r4,3 - addi r6,r6,3 -4: lbzu r0,1(r4) - stbu r0,1(r6) - bdnz 4b - blr -5: subfic r0,r0,4 - mtctr r0 -6: lbz r7,4(r4) - addi r4,r4,1 - stb r7,4(r6) - addi r6,r6,1 - bdnz 6b - subf r5,r0,r5 - rlwinm. r7,r5,32-3,3,31 - beq 2b - mtctr r7 - b 1b - - .globl backwards_memcpy -backwards_memcpy: - rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ - add r6,r3,r5 - add r4,r4,r5 - beq 2f - andi. r0,r6,3 - mtctr r7 - bne 5f -1: lwz r7,-4(r4) - lwzu r8,-8(r4) - stw r7,-4(r6) - stwu r8,-8(r6) - bdnz 1b - andi. r5,r5,7 -2: cmplwi 0,r5,4 - blt 3f - lwzu r0,-4(r4) - subi r5,r5,4 - stwu r0,-4(r6) -3: cmpwi 0,r5,0 - beqlr - mtctr r5 -4: lbzu r0,-1(r4) - stbu r0,-1(r6) - bdnz 4b - blr -5: mtctr r0 -6: lbzu r7,-1(r4) - stbu r7,-1(r6) - bdnz 6b - subf r5,r0,r5 - rlwinm. r7,r5,32-3,3,31 - beq 2b - mtctr r7 - b 1b - - .globl memcmp -memcmp: - cmpwi 0,r5,0 - ble- 2f - mtctr r5 - addi r6,r3,-1 - addi r4,r4,-1 -1: lbzu r3,1(r6) - lbzu r0,1(r4) - subf. r3,r0,r3 - bdnzt 2,1b - blr -2: li r3,0 - blr - - .global memchr -memchr: - cmpwi 0,r5,0 - ble- 2f - mtctr r5 - addi r3,r3,-1 -1: lbzu r0,1(r3) - cmpw 0,r0,r4 - bdnzf 2,1b - beqlr -2: li r3,0 - blr diff --git a/lib_ppc/ticks.S b/lib_ppc/ticks.S deleted file mode 100644 index b8d25b7..0000000 --- a/lib_ppc/ticks.S +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * base on code by - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* - * unsigned long long get_ticks(void); - * - * read timebase as "long long" - */ - .globl get_ticks -get_ticks: -1: mftbu r3 - mftb r4 - mftbu r5 - cmp 0,r3,r5 - bne 1b - blr - -/* - * Delay for a number of ticks - */ - .globl wait_ticks -wait_ticks: - mflr r8 /* save link register */ - mr r7, r3 /* save tick count */ - bl get_ticks /* Get start time */ - - /* Calculate end time */ - addc r7, r4, r7 /* Compute end time lower */ - addze r6, r3 /* and end time upper */ - - WATCHDOG_RESET /* Trigger watchdog, if needed */ -1: bl get_ticks /* Get current time */ - subfc r4, r4, r7 /* Subtract current time from end time */ - subfe. r3, r3, r6 - bge 1b /* Loop until time expired */ - - mtlr r8 /* restore link register */ - blr diff --git a/lib_ppc/time.c b/lib_ppc/time.c deleted file mode 100644 index 51e8e840..0000000 --- a/lib_ppc/time.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - - -/* ------------------------------------------------------------------------- */ - -/* - * This function is intended for SHORT delays only. - * It will overflow at around 10 seconds @ 400MHz, - * or 20 seconds @ 200MHz. - */ -unsigned long usec2ticks(unsigned long usec) -{ - ulong ticks; - - if (usec < 1000) { - ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; - } else { - ticks = ((usec / 10) * (get_tbclk() / 100000)); - } - - return (ticks); -} - -/* ------------------------------------------------------------------------- */ - -/* - * We implement the delay by converting the delay (the number of - * microseconds to wait) into a number of time base ticks; then we - * watch the time base until it has incremented by that amount. - */ -void udelay(unsigned long usec) -{ - ulong ticks = usec2ticks (usec); - - wait_ticks (ticks); -} - -/* ------------------------------------------------------------------------- */ - -unsigned long ticks2usec(unsigned long ticks) -{ - ulong tbclk = get_tbclk(); - - /* usec = ticks * 1000000 / tbclk - * Multiplication would overflow at ~4.2e3 ticks, - * so we break it up into - * usec = ( ( ticks * 1000) / tbclk ) * 1000; - */ - ticks *= 1000L; - ticks /= tbclk; - ticks *= 1000L; - - return ((ulong)ticks); -} - -/* ------------------------------------------------------------------------- */ - -int init_timebase (void) -{ -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) - volatile immap_t *immap = (immap_t *) CFG_IMMR; - - /* unlock */ - immap->im_sitk.sitk_tbk = KAPWR_KEY; -#endif - - /* reset */ - asm ("li 3,0 ; mttbu 3 ; mttbl 3 ;"); - -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) - /* enable */ - immap->im_sit.sit_tbscr |= TBSCR_TBE; -#endif - return (0); -} -/* ------------------------------------------------------------------------- */ diff --git a/m68k_config.mk b/m68k_config.mk deleted file mode 100644 index 12bd27c..0000000 --- a/m68k_config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__ -PLATFORM_LDFLAGS += -n diff --git a/microblaze_config.mk b/microblaze_config.mk deleted file mode 100644 index b3ac8e0..0000000 --- a/microblaze_config.mk +++ /dev/null @@ -1,37 +0,0 @@ -# -# (C) Copyright 2004 Atmark Techno, Inc. -# -# Yasushi SHOJI -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_CPPFLAGS += -ffixed-r31 - -ifdef CONFIG_MICROBLAZE_HARD_MULT -PLATFORM_CPPFLAGS += -mno-xl-soft-mul -endif - -ifdef CONFIG_MICROBLAZE_HARD_DIV -PLATFORM_CPPFLAGS += -mno-xl-soft-div -endif - -ifdef CONFIG_MICROBLAZE_HARD_BARREL -PLATFORM_CPPFLAGS += -mxl-barrel-shift -endif diff --git a/mips_config.mk b/mips_config.mk deleted file mode 100644 index d8aa5fa..0000000 --- a/mips_config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ diff --git a/net/.depend b/net/.depend new file mode 100644 index 0000000..afeb0ac --- /dev/null +++ b/net/.depend @@ -0,0 +1,282 @@ +net.o: net.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/net.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/byteorder.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/little_endian.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/swab.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/generic.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/malloc.h \ + nfs.h bootp.h +sntp.o: sntp.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/net.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/byteorder.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/little_endian.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/swab.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/generic.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/rtc.h \ + sntp.h +rcvr.o: rcvr.c rcvr.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/net.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/byteorder.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/little_endian.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/swab.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/byteorder/generic.h diff --git a/net/Makefile b/net/Makefile index 7a70489..98827be 100644 --- a/net/Makefile +++ b/net/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = libnet.a -OBJS = net.o tftp.o bootp.o rarp.o eth.o nfs.o sntp.o +OBJS = net.o tftp.o bootp.o rarp.o eth.o nfs.o sntp.o rcvr.o all: $(LIB) $(LIB): $(START) $(OBJS) diff --git a/net/eth.c b/net/eth.c index 9341e20..4da52cb 100644 --- a/net/eth.c +++ b/net/eth.c @@ -53,12 +53,29 @@ extern int rtl8169_initialize(bd_t*); extern int scc_initialize(bd_t*); extern int skge_initialize(bd_t*); extern int tsec_initialize(bd_t*, int, char *); +extern int mv_eth_initialize(bd_t *); +#ifdef MV78200 +extern int mvSocUnitIsMappedToThisCpu(int unit); +#define GIGA0 4 +#endif -static struct eth_device *eth_devices, *eth_current; +extern unsigned int whoAmI(void); +static struct eth_device *eth_devices; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) +static struct eth_device *eth_current[2]; +static char* ethact[2] = {"ethact", "ethact2"}; +#else +static struct eth_device *eth_current[1]; +static char* ethact[1] = {"ethact"}; +#endif struct eth_device *eth_get_dev(void) { - return eth_current; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + return eth_current[cpu]; } struct eth_device *eth_get_dev_by_name(char *devname) @@ -85,13 +102,17 @@ int eth_get_dev_index (void) { struct eth_device *dev; int num = 0; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif if (!eth_devices) { return (-1); } for (dev = eth_devices; dev; dev = dev->next) { - if (dev == eth_current) + if (dev == eth_current[cpu]) break; ++num; } @@ -106,15 +127,19 @@ int eth_get_dev_index (void) int eth_register(struct eth_device* dev) { struct eth_device *d; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif if (!eth_devices) { - eth_current = eth_devices = dev; + eth_current[cpu] = eth_devices = dev; #ifdef CONFIG_NET_MULTI /* update current ethernet name */ { - char *act = getenv("ethact"); - if (act == NULL || strcmp(act, eth_current->name) != 0) - setenv("ethact", eth_current->name); + char *act = getenv(ethact[cpu]); + if (act == NULL || strcmp(act, eth_current[cpu]->name) != 0) + setenv(ethact[cpu], eth_current[cpu]->name); } #endif } else { @@ -130,13 +155,21 @@ int eth_register(struct eth_device* dev) int eth_initialize(bd_t *bis) { - char enetvar[32], env_enetaddr[6]; - int i, eth_number = 0; - char *tmp, *end; - + int eth_number = 0; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif eth_devices = NULL; - eth_current = NULL; + eth_current[cpu] = NULL; +#ifdef CONFIG_MARVELL +#if defined(MV_INCLUDE_GIG_ETH) || defined(MV_INCLUDE_UNM_ETH) + /* move to the begining so in case we have a PCI NIC it will + read the env mac addresses correctlly. */ + mv_eth_initialize(bis); +#endif +#endif #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_init(); #endif @@ -239,16 +272,18 @@ int eth_initialize(bd_t *bis) char *ethprime = getenv ("ethprime"); do { + if (eth_number) puts (", "); printf("%s", dev->name); if (ethprime && strcmp (dev->name, ethprime) == 0) { - eth_current = dev; + eth_current[cpu] = dev; puts (" [PRIME]"); } +#ifndef CONFIG_MARVELL sprintf(enetvar, eth_number ? "eth%daddr" : "ethaddr", eth_number); tmp = getenv (enetvar); @@ -278,19 +313,19 @@ int eth_initialize(bd_t *bis) memcpy(dev->enetaddr, env_enetaddr, 6); } - +#endif eth_number++; dev = dev->next; } while(dev != eth_devices); #ifdef CONFIG_NET_MULTI /* update current ethernet name */ - if (eth_current) { - char *act = getenv("ethact"); - if (act == NULL || strcmp(act, eth_current->name) != 0) - setenv("ethact", eth_current->name); + if (eth_current[cpu]) { + char *act = getenv(ethact[cpu]); + if (act == NULL || strcmp(act, eth_current[cpu]->name) != 0) + setenv(ethact[cpu], eth_current[cpu]->name); } else - setenv("ethact", NULL); + setenv(ethact[cpu], NULL); #endif putc ('\n'); @@ -337,76 +372,98 @@ void eth_set_enetaddr(int num, char *addr) { int eth_init(bd_t *bis) { struct eth_device* old_current; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif - if (!eth_current) + if (!eth_current[cpu]) return 0; - old_current = eth_current; + old_current = eth_current[cpu]; do { - debug ("Trying %s\n", eth_current->name); + debug ("Trying %s\n", eth_current[cpu]->name); - if (eth_current->init(eth_current, bis)) { - eth_current->state = ETH_STATE_ACTIVE; + if (eth_current[cpu]->init(eth_current[cpu], bis)) { + eth_current[cpu]->state = ETH_STATE_ACTIVE; return 1; } debug ("FAIL\n"); eth_try_another(0); - } while (old_current != eth_current); + } while (old_current != eth_current[cpu]); return 0; } void eth_halt(void) { - if (!eth_current) + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + + if (!eth_current[cpu]) return; - eth_current->halt(eth_current); + eth_current[cpu]->halt(eth_current[cpu]); - eth_current->state = ETH_STATE_PASSIVE; + eth_current[cpu]->state = ETH_STATE_PASSIVE; } int eth_send(volatile void *packet, int length) { - if (!eth_current) + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + + if (!eth_current[cpu]) return -1; - return eth_current->send(eth_current, packet, length); + return eth_current[cpu]->send(eth_current[cpu], packet, length); } int eth_rx(void) { - if (!eth_current) + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + if (!eth_current[cpu]) return -1; - return eth_current->recv(eth_current); + return eth_current[cpu]->recv(eth_current[cpu]); } void eth_try_another(int first_restart) { static struct eth_device *first_failed = NULL; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif - if (!eth_current) + if (!eth_current[cpu]) return; if (first_restart) { - first_failed = eth_current; + first_failed = eth_current[cpu]; } - eth_current = eth_current->next; + eth_current[cpu] = eth_current[cpu]->next; #ifdef CONFIG_NET_MULTI /* update current ethernet name */ { - char *act = getenv("ethact"); - if (act == NULL || strcmp(act, eth_current->name) != 0) - setenv("ethact", eth_current->name); + char *act = getenv(ethact[cpu]); + if (act == NULL || strcmp(act, eth_current[cpu]->name) != 0) + setenv(ethact[cpu], eth_current[cpu]->name); } #endif - if (first_failed == eth_current) { + if (first_failed == eth_current[cpu]) { NetRestartWrap = 1; } } @@ -416,27 +473,36 @@ void eth_set_current(void) { char *act; struct eth_device* old_current; + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif - if (!eth_current) /* XXX no current */ + if (!eth_current[cpu]) /* XXX no current */ return; - act = getenv("ethact"); + act = getenv(ethact[cpu]); if (act != NULL) { - old_current = eth_current; + old_current = eth_current[cpu]; do { - if (strcmp(eth_current->name, act) == 0) + if (strcmp(eth_current[cpu]->name, act) == 0) return; - eth_current = eth_current->next; - } while (old_current != eth_current); + eth_current[cpu] = eth_current[cpu]->next; + } while (old_current != eth_current[cpu]); } - setenv("ethact", eth_current->name); + setenv(ethact[cpu], eth_current[cpu]->name); } #endif char *eth_get_name (void) { - return (eth_current ? eth_current->name : "unknown"); + unsigned int cpu = 0; +#if defined(MV78200) && defined(DUAL_OS_SHARED_MEM_78200) + cpu = whoAmI(); +#endif + + return (eth_current[cpu] ? eth_current[cpu]->name : "unknown"); } #elif (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_NET_MULTI) diff --git a/net/net.c b/net/net.c index 37c5fb6..77e32fb 100644 --- a/net/net.c +++ b/net/net.c @@ -90,6 +90,10 @@ #include "sntp.h" #endif +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) +#include "rcvr.h" +#endif + #if (CONFIG_COMMANDS & CFG_CMD_NET) #define ARP_TIMEOUT 5 /* Seconds before trying ARP again */ @@ -378,6 +382,10 @@ restart: NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */ NetOurNativeVLAN = getenv_VLAN("nvlan"); break; +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) + case RCVR: + break; +#endif default: break; } @@ -447,6 +455,11 @@ restart: case SNTP: SntpStart(); break; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) + case RCVR: + RecoverRequest(); + break; #endif default: break; @@ -474,6 +487,7 @@ restart: * someone sets `NetState' to a state that terminates. */ for (;;) { + int timerVal; WATCHDOG_RESET(); #ifdef CONFIG_SHOW_ACTIVITY { @@ -502,7 +516,8 @@ restart: * Check for a timeout, and run the timeout handler * if we have one. */ - if (timeHandler && ((get_timer(0) - timeStart) > timeDelta)) { + timerVal = get_timer(0); + if (timeHandler && ((timerVal - timeStart) > timeDelta)) { thand_f *x; #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) @@ -1248,6 +1263,8 @@ NetReceive(volatile uchar * inpkt, int len) */ #ifdef ET_DEBUG puts ("Got ARP\n"); + printf (" Addr 0x%x\n", ip); + #endif arp = (ARP_t *)ip; if (len < ARP_HDR_SIZE) { @@ -1536,6 +1553,9 @@ static int net_check_prereq (proto_t protocol) case RARP: case BOOTP: case CDP: +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) + case RCVR: +#endif if (memcmp (NetOurEther, "\0\0\0\0\0\0", 6) == 0) { #ifdef CONFIG_NET_MULTI extern int eth_get_dev_index (void); diff --git a/net/rcvr.c b/net/rcvr.c new file mode 100644 index 0000000..cf8f976 --- /dev/null +++ b/net/rcvr.c @@ -0,0 +1,465 @@ +/* + * This file impliments TFTP server with the Distress Beacon UDP packet, that will be send + * as a notification for a system recovery process. + */ + +#include "rcvr.h" + +/* #define DEBUG_RCVR */ + +#ifdef DEBUG_RCVR +#define debug_rcvr(fmt,args...) printf (fmt ,##args) +#else +#define debug_rcvr(fmt,args...) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) + +/* Globals */ +rcvr_state_t rcvr_state = RCVR_INIT; +ulong myTID = 0; /* Transfer ID used by me as a TFPT server */ +ulong peerTID = 0; /* Transfer ID received from the peer */ +ulong packetNum = 0; /* Packet number expected */ +uchar * imagePtr = NULL; /* Pointer to the location to copy the uImage file */ + +static void +BeaconSend (void) +{ + DistressBeaconPacketStruct * bconpkt; + char *s; + + bconpkt = (DistressBeaconPacketStruct*) (NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE); + + /* clear the whole packet to zeros */ + memset(bconpkt, 0x0, sizeof(bconpkt)); + + /* Fill the packet with the information needed */ + bconpkt->Header.PacketType = RECOVERY_MODE; + bconpkt->Header.Version = BEACON_VERSION; + bconpkt->Payload.State = (((RECOVERY_STATE_FIRST & 0xFF) << 8) | ((RECOVERY_STATE_FIRST & 0xFF00) >> 8)); + NetCopyIP(&bconpkt->Payload.IPAddr.IPAddress, &NetOurIP); + memcpy (bconpkt->Payload.LinkAddr.LinkLevelAddr, NetOurEther, LL_ADDR_LEN); + + if ((s = getenv("deviceName")) != NULL) + { + ulong strln = strlen(s); + if (strln >= MAX_NAME_LEN) + strncpy(bconpkt->Payload.Name, s, MAX_NAME_LEN-1); /* keep space for null termination */ + else + strcpy(bconpkt->Payload.Name, s); + } + else + { + printf("Warning: Missing environment variable \"deviceName\". Assuming default!\n"); + strcpy(bconpkt->Payload.Name, "Unknown S/N"); + } + + if ((s = getenv("modelNumber")) != NULL) + { + ulong strln = strlen(s); + if (strln >= MAX_MODEL_NUMBER_LEN) + strncpy(bconpkt->Payload.ModelNumber, s, MAX_MODEL_NUMBER_LEN-1); /* keep space for null termination */ + else + strcpy(bconpkt->Payload.ModelNumber, s); + } + else + { + printf("Warning: Missing environment variable \"modelNumber\". Assuming default!\n"); + strcpy(bconpkt->Payload.ModelNumber, "Unknown Model # of NAS system"); + } + + printf("Broadcasting Distress Beacon Packet.\n"); + debug_rcvr("Sending Beacon packet with IP = 0x%08x and MAC = %02x:%02x:%02x:%02x:%02x:%02x\n", bconpkt->Payload.IPAddr.IPAddress, + bconpkt->Payload.LinkAddr.LinkLevelAddr[0], bconpkt->Payload.LinkAddr.LinkLevelAddr[1], bconpkt->Payload.LinkAddr.LinkLevelAddr[2], + bconpkt->Payload.LinkAddr.LinkLevelAddr[3], bconpkt->Payload.LinkAddr.LinkLevelAddr[4], bconpkt->Payload.LinkAddr.LinkLevelAddr[5]); + + NetSendUDPPacket(NetServerEther, 0, BEACON_UDP_PORT, BEACON_UDP_PORT, sizeof(DistressBeaconPacketStruct)); +} + + +/* + * Send an Error Reply. + */ +static void +SendTftpError(ushort error, unsigned src, unsigned dst, uchar * errStr) +{ + ushort * fld; + uchar *s; + + /* write first the opcode */ + fld = (ushort*) (NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE); + *fld = (((TFTP_OPCODE_ERR & 0xFF) << 8) | ((TFTP_OPCODE_ERR & 0xFF00) >> 8)); + + /* Write the error code */ + fld++; + *fld = (((error & 0xFF) << 8) | ((error & 0xFF00) >> 8)); + + /* Add a string to explain */ + s = (uchar*) ++fld; + sprintf(s, "%s", errStr); + + /* Transmit the error message */ + debug_rcvr("Sendin ERR packet (PeerTID = %d, MyTID = %d).\n", src, dst); + NetSendUDPPacket(NetServerEther, NetServerIP, src, dst, (strlen(s) + 5)); +} + +/* + * Send an Error Reply. + */ +static void +SendTftpAck(ushort block) +{ + ushort * fld; + + /* write first the opcode */ + fld = (ushort*) (NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE); + *fld = (((TFTP_OPCODE_ACK & 0xFF) << 8) | ((TFTP_OPCODE_ACK & 0xFF00) >> 8)); + + /* Write the error code */ + fld++; + *fld = (((block & 0xFF) << 8) | ((block & 0xFF00) >> 8)); + + /* Transmit the error message */ + debug_rcvr("Sendin ACK packet (PeerTID = %d, MyTID = %d, Block = %d).\n", peerTID, myTID, block); + NetSendUDPPacket(NetServerEther, NetServerIP, peerTID, myTID, 4); +} + + +/* + * Timeout on Distress Beacon Recovery request. + */ +static void +RecoverTimeout(void) +{ + switch (rcvr_state) + { + /* 5 seconds between Distress Beacon */ + case RCVR_WAIT_4_CNCT: + NetSetTimeout (RCVR_BEACON_TIMEOUT * CFG_HZ, RecoverTimeout); + BeaconSend(); + break; + + /* Timeout between data packets or between uImage and RamDisk files */ + case RCVR_IMAGE_DWNLD: + debug_rcvr("Timeout, Failing the recovery process!\n"); + SendTftpError(TFTP_ERROR_UNDEFINED, peerTID, myTID, "Data Packet TimeOut!"); + NetSetTimeout(0, (thand_f *)0); + NetState = NETLOOP_FAIL; + rcvr_state = RCVR_INIT; + break; + + /* Client finished successfully no retransmit requested */ + case RCVR_FINISHED: + debug_rcvr("Finished successfully.\n"); + NetSetTimeout(0, (thand_f *)0); + NetState = NETLOOP_SUCCESS; + rcvr_state = RCVR_INIT; + break; + + default: + debug_rcvr("Invalid state received in the Timeout routine~\n"); + } +} + + +/* + * Handle Recovery received packets. + */ +static void +RecoveryHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len) +{ + ushort opcode; + ushort * fld; + uchar * tftpfile = NULL; + uchar * tftpmode = NULL; + ushort rxPacketNumber; + unsigned dlen; + + fld = (ushort*) pkt; + opcode = (((*fld & 0xFF) << 8) | ((*fld & 0xFF00) >> 8)); + + switch (rcvr_state) + { + case RCVR_INIT: + break; + + case RCVR_WAIT_4_CNCT: + switch (opcode) + { + case TFTP_OPCODE_RRQ: + /* check that the destination port is correct */ + if (dest != TFTP_SERVER_PORT) + return; + + /* Copy the server IP and MAC address */ + memcpy (NetServerEther, (uchar*) &NetRxPkt[6], 6); + NetServerIP = NetRxPkt[26]; + NetServerIP |= (NetRxPkt[27] << 8); + NetServerIP |= (NetRxPkt[28] << 16); + NetServerIP |= (NetRxPkt[29] << 24); + debug_rcvr("New Peer Info (MAC %02x:%02x:%02x:%02x:%02x:%02x, IP %08x\n", NetServerEther[0], NetServerEther[1], + NetServerEther[2], NetServerEther[3], NetServerEther[4], NetServerEther[5], NetServerIP); + + printf("Unsupported TFTP GET request received from %d.%d.%d.%d (MAC %02x:%02x:%02x:%02x:%02x:%02x)\n", + (NetServerIP & 0xFF), ((NetServerIP >> 8) & 0xFF), ((NetServerIP >> 16) & 0xFF), ((NetServerIP >> 24) & 0xFF), + NetServerEther[0], NetServerEther[1], NetServerEther[2], NetServerEther[3], NetServerEther[4], + NetServerEther[5]); + + SendTftpError(TFTP_ERROR_ILLEGAL_OPERATION, src, TFTP_SERVER_PORT, "Request Not Supported"); + break; + + case TFTP_OPCODE_WRQ: + /* check that the destination port is correct */ + if (dest != TFTP_SERVER_PORT) + return; + + /* Copy the server IP and MAC address */ + memcpy (NetServerEther, (uchar*) &NetRxPkt[6], 6); + NetServerIP = NetRxPkt[26]; + NetServerIP |= (NetRxPkt[27] << 8); + NetServerIP |= (NetRxPkt[28] << 16); + NetServerIP |= (NetRxPkt[29] << 24); + debug_rcvr("New Peer Info (MAC %02x:%02x:%02x:%02x:%02x:%02x, IP %08x\n", NetServerEther[0], NetServerEther[1], + NetServerEther[2], NetServerEther[3], NetServerEther[4], NetServerEther[5], NetServerIP); + + printf("New TFTP PUT request received from %d.%d.%d.%d (MAC %02x:%02x:%02x:%02x:%02x:%02x)\n", + (NetServerIP & 0xFF), ((NetServerIP >> 8) & 0xFF), ((NetServerIP >> 16) & 0xFF), ((NetServerIP >> 24) & 0xFF), + NetServerEther[0], NetServerEther[1], NetServerEther[2], NetServerEther[3], NetServerEther[4], + NetServerEther[5]); + + tftpfile = pkt +2; + tftpmode = pkt + 3 + strlen (tftpfile); + debug_rcvr("TFTP WRQ received (Dest = %d, Src = %d, Len = %d, Opcode = %d, File = %s, Mode = %s, PeerTID = %d\n", + dest, src, len, opcode, tftpfile, tftpmode, src); + + /* save the peer port # as the peerTID */ + peerTID = src; + packetNum = 1; /* reset the packet numbering */ + debug_rcvr("Saving the PeerTID to used throughout the session (PeerTID = %d).\n", peerTID); + + /* received the request successfully */ + rcvr_state = RCVR_IMAGE_DWNLD; + NetSetTimeout (RCVR_DATA_TIMEOUT * CFG_HZ, RecoverTimeout); + + /* Send the ACK */ + SendTftpAck(0); + break; + + case TFTP_OPCODE_DATA: + case TFTP_OPCODE_ACK: + case TFTP_OPCODE_ERR: + debug_rcvr("ERROR: Invalid TFTP request while in WAIT_4_CNCT (opcode = %d)!\n",opcode); + break; + + default: + debug_rcvr("ERROR: Invalid TFTP opcode!\n"); + } + break; + + case RCVR_IMAGE_DWNLD: + switch (opcode) + { + case TFTP_OPCODE_RRQ: + debug_rcvr("TFTP GET requestes are not supported. Sendin Error!\n"); + break; + + case TFTP_OPCODE_WRQ: + /* check if the WRQ ACK was not received so we are having it again */ + if (packetNum == 1) /* we did not yeat receive any DATA packet */ + { + /* check that the destination port is correct */ + if (dest != TFTP_SERVER_PORT) + return; + + /* Copy the server IP and MAC address */ + memcpy (NetServerEther, (uchar*) &NetRxPkt[6], 6); + NetServerIP = NetRxPkt[26]; + NetServerIP |= (NetRxPkt[27] << 8); + NetServerIP |= (NetRxPkt[28] << 16); + NetServerIP |= (NetRxPkt[29] << 24); + debug_rcvr("New Peer Info (MAC %02x:%02x:%02x:%02x:%02x:%02x, IP %08x\n", NetServerEther[0], NetServerEther[1], + NetServerEther[2], NetServerEther[3], NetServerEther[4], NetServerEther[5], NetServerIP); + + printf("TFTP PUT request received again from %d.%d.%d.%d (MAC %02x:%02x:%02x:%02x:%02x:%02x)\n", + (NetServerIP & 0xFF), ((NetServerIP >> 8) & 0xFF), ((NetServerIP >> 16) & 0xFF), ((NetServerIP >> 24) & 0xFF), + NetServerEther[0], NetServerEther[1], NetServerEther[2], NetServerEther[3], NetServerEther[4], + NetServerEther[5]); + + tftpfile = pkt +2; + tftpmode = pkt + 3 + strlen (tftpfile); + debug_rcvr("TFTP WRQ received again (Dest = %d, Src = %d, Len = %d, Opcode = %d, File = %s, Mode = %s, PeerTID = %d\n", + dest, src, len, opcode, tftpfile, tftpmode, src); + + /* save the peer port # as the peerTID */ + peerTID = src; + debug_rcvr("Saving the PeerTID to used throughout the session (PeerTID = %d).\n", peerTID); + + /* Send the ACK */ + SendTftpAck(0); + } + else + debug_rcvr("ERROR: Invalid WRQ request while data transfer!\n"); + + break; + + case TFTP_OPCODE_DATA: + + /* check that the destination port is correct */ + if (dest != myTID) + { + debug_rcvr("ERROR: TFTP data packet not to my TID port (port = %d)!\n", dest); + return; + } + + fld = (ushort*) (pkt+2); + rxPacketNumber = (((*fld & 0xFF) << 8) | ((*fld & 0xFF00) >> 8)); + if (rxPacketNumber == (ushort)(packetNum & 0xffff)) + { + /* check the length of data */ + if (len == (TFTP_MAX_DATA_LEN + 4)) + { + /* print a progress message */ + if ((packetNum % 500) == 0) + printf("%dKB\r", (packetNum / 2)); + + dlen = TFTP_MAX_DATA_LEN; + NetSetTimeout (RCVR_DATA_TIMEOUT * CFG_HZ, RecoverTimeout); + } + else if (len < (TFTP_MAX_DATA_LEN + 4)) + { + dlen = (len - 4); + rcvr_state = RCVR_FINISHED; + NetSetTimeout (RCVR_FINISH_TIMEOUT * CFG_HZ, RecoverTimeout); + //debug_rcvr("Received the last packet in the uImage file, changing state to WAIT_4_RAMDISK.\n"); + printf("Recovery Image received (%d bytes).\n",((packetNum * TFTP_MAX_DATA_LEN) + dlen)); + } + else /* Fatal Error */ + { + debug_rcvr("ERROR: TFTP data packet larger that 512!\n"); + NetSetTimeout(0, (thand_f *)0); + NetState = NETLOOP_FAIL; + rcvr_state = RCVR_INIT; + return; + } + + debug_rcvr("Received uImage Packet #%d (length = %d). Sending Ack.\n", packetNum, dlen); + + /* copy the data to the RAM */ + memcpy(imagePtr, (pkt+4), dlen); + imagePtr += dlen; + NetBootFileXferSize += dlen; + + /* Send the Ack for the new packet */ + SendTftpAck(packetNum); + + /* increment the packet number */ + ++packetNum; + } + else if (rxPacketNumber == ((ushort)(packetNum & 0xffff)-1)) + { + debug_rcvr("Received Packet #%d AGAIN. Sending Ack.\n"); + + /* Seems that my last ACK was not delivered SO Send the Ack again */ + SendTftpAck(rxPacketNumber); + } + else + debug_rcvr("Invalid Packet #%d received (expecting %d)!\n", rxPacketNumber, packetNum); + + break; + + case TFTP_OPCODE_ACK: + case TFTP_OPCODE_ERR: + debug_rcvr("ERROR: Invalid TFTP request while in IMAGE_DWNLD (opcode = %d)!\n",opcode); + break; + + default: + debug_rcvr("ERROR: Invalid TFTP opcode!\n"); + } + break; + + case RCVR_FINISHED: + switch (opcode) + { + case TFTP_OPCODE_DATA: + /* check that the destination port is correct */ + if (dest != myTID) + { + debug_rcvr("ERROR: TFTP data packet not to my TID port (port = %d)!\n", dest); + return; + } + + fld = (ushort*) (pkt+2); + rxPacketNumber = (((*fld & 0xFF) << 8) | ((*fld & 0xFF00) >> 8)); + + /* check if the last ACK was not received; so retransmit it */ + if (rxPacketNumber == ((ushort)(packetNum & 0xffff)-1)) + { + debug_rcvr("Received Packet #%d AGAIN. Sending Ack.\n"); + + /* Seems that my last ACK was not delivered SO Send the Ack again */ + SendTftpAck(rxPacketNumber); + } + else + debug_rcvr("Invalid Packet #%d deceived (expecting %d)!\n", rxPacketNumber, packetNum); + + break; + + case TFTP_OPCODE_RRQ: + case TFTP_OPCODE_WRQ: + case TFTP_OPCODE_ACK: + case TFTP_OPCODE_ERR: + debug_rcvr("ERROR: Invalid TFTP request while in RCVR_FINISHED (opcode = %d)!\n",opcode); + break; + + default: + debug_rcvr("ERROR: Invalid TFTP opcode!\n"); + } + break; + + default: + debug_rcvr("ERROR: Invalid Recovery status!\n"); + } + + return; +} + + +/* + * Start a recovery process - Using Distress Beacon and TFTP server + */ +void RecoverRequest(void) +{ + uchar * s; + + /* get the uImage locations */ + if ((s = getenv("loadaddr")) != NULL) + { + imagePtr = (uchar *)simple_strtoul(s, NULL, 16); + printf("uImage load address 0x%08x\n", imagePtr); + } + else + { + printf("ERROR: Missing environment variable for \"loadaddr\"!\n"); + NetState = NETLOOP_FAIL; + return; + } + + /* Caculate the TID to be used */ + myTID = ((NetOurEther[4] << 8) | (NetOurEther[5])); + peerTID = 0; /* reset the peer TID */ + + /* Change the state for waiting to connect */ + rcvr_state = RCVR_WAIT_4_CNCT; + + /* Set the handler to the TFTP server */ + NetSetHandler(RecoveryHandler); + + /* Set the Timeout */ + NetSetTimeout(RCVR_BEACON_TIMEOUT * CFG_HZ, RecoverTimeout); + + /* Transmit the First Distress Beacon packet */ + BeaconSend(); +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_RCVR) */ + diff --git a/net/rcvr.h b/net/rcvr.h new file mode 100644 index 0000000..97cdf14 --- /dev/null +++ b/net/rcvr.h @@ -0,0 +1,124 @@ +/* + * This file provides the typedefs and constants for the TFTP server and Distress Beacon implimentation + */ + +#ifndef __RCVR_H__ +#define __RCVR_H__ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_RCVR) + +/********************************************************************************************************************/ +/* DISTRESS BEACON DEFINITIONS */ +/********************************************************************************************************************/ + +#define BEACON_UDP_PORT 3583 /* Destination UDP Port to broadcast the distress beacon to */ +#define RECOVERY_MODE 0xDE /* packet_type values/signatures */ +#define RECOVERY_STATE_FIRST 0x00001 /* First stage for loading the initrd */ +#define RECOVERY_STATE_SECOND 0x00002 /* Second stage for loading the firmware.bin - not used in UBoot */ +#define BEACON_VERSION 1 /* Current version of the Beacon Packet */ +#define LL_ADDR_LEN 6 /* Length of a link level address (in bytes) */ +#define IP_ADDR_LEN 4 /* Length of IP address in bytes */ +#define MAX_NAME_LEN 16 /* Length of name (NetBIOS) */ +#define MAX_MODEL_NUMBER_LEN 50 /* Length of model Number */ + +#pragma pack (1) + +/* LinkLevelAddrStruct - Defines the structure of a link level address */ +typedef struct +{ + uchar LinkLevelAddr[LL_ADDR_LEN]; +} LinkLevelAddrStruct; + +/* IPAddrStruct - Defines the structure of an IP address */ +typedef struct +{ + ulong IPAddress; +} IPAddressStruct; + +/* PacketHeaderStruct - Defines the structure of the beacon packet header + * - 16-bit value that specifies teh type of packet, (RECOVERY_MODE) + * - 8-bit version of packet for future extension + */ +typedef struct +{ + uchar PacketType; + uchar Version; +}PacketHeaderStruct; + +/* DistressBeaconPayloadStruct - Defines the structure of the beacon packet payload + * - 4 bytes IP address of the NAS in distress + * - 6 bytes LL address of the NAS in distress + * - 16 bytes string with the name of the NAS in distress + * - 50 bytes string with the NAS Model number + */ +typedef struct +{ + ushort State; + IPAddressStruct IPAddr; + LinkLevelAddrStruct LinkAddr; + uchar Name[MAX_NAME_LEN]; + uchar ModelNumber[MAX_MODEL_NUMBER_LEN]; +}DistressBeaconPayloadStruct; + +/* DistressBeaconPacketStruct - The structure with both the header and payload */ +typedef struct +{ + PacketHeaderStruct Header; + DistressBeaconPayloadStruct Payload; +}DistressBeaconPacketStruct; + +#pragma pack () + +/********************************************************************************************************************/ +/* RECOVERY DEFINITIONS */ +/********************************************************************************************************************/ + +#define RCVR_BEACON_TIMEOUT 5 /* timeout in seconds between Distress Beacon */ +#define RCVR_DATA_TIMEOUT 6 /* timeout in seconds to receive a data packet */ +#define RCVR_FINISH_TIMEOUT 2 /* timeout in seconds to verify that the client received the last ACK */ + +/* Recovery States */ +typedef enum +{ + RCVR_INIT, + RCVR_WAIT_4_CNCT, + RCVR_IMAGE_DWNLD, + RCVR_FINISHED +}rcvr_state_t; + +/* Function Prototypes */ +void RecoverRequest(void); + +/********************************************************************************************************************/ +/* TFTP SERVER DEFINITIONS */ +/********************************************************************************************************************/ + +/* TFTP ports */ +#define TFTP_SERVER_PORT 69 + +/* Length of the opcode field */ +#define TFTP_OPCODE_LEN 2 + +/* All possible TFTP opcodes */ +#define TFTP_OPCODE_RRQ 0x0001 +#define TFTP_OPCODE_WRQ 0x0002 +#define TFTP_OPCODE_DATA 0x0003 +#define TFTP_OPCODE_ACK 0x0004 +#define TFTP_OPCODE_ERR 0x0005 + +/* TFTP error codes supported */ +#define TFTP_ERROR_UNDEFINED 0 +#define TFTP_ERROR_ILLEGAL_OPERATION 4 + +/* MAX size of TFTP DATA */ +#define TFTP_MAX_DATA_LEN 512 + + + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_RCVR) */ + +#endif /* __RCVR_H__ */ diff --git a/nios2_config.mk b/nios2_config.mk deleted file mode 100644 index 03253a3..0000000 --- a/nios2_config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2004 -# Psyent Corporation -# Scott McNutt -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ -PLATFORM_CPPFLAGS += -ffixed-r15 diff --git a/nios_config.mk b/nios_config.mk deleted file mode 100644 index 1cf0f32..0000000 --- a/nios_config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2003 -# Psyent Corporation -# Scott McNutt -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7 -gstabs diff --git a/post/.depend b/post/.depend new file mode 100644 index 0000000..5de4d87 --- /dev/null +++ b/post/.depend @@ -0,0 +1,431 @@ +cache_8xx.o: cache_8xx.S \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h +cache.o: cache.c \ + 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Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ -PLATFORM_LDFLAGS += -n diff --git a/rtc/.depend b/rtc/.depend new file mode 100644 index 0000000..6315cf8 --- /dev/null +++ b/rtc/.depend @@ -0,0 +1,577 @@ +date.o: date.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + 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/home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/rtc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/i2c.h +s3c24x0_rtc.o: s3c24x0_rtc.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h +rs5c372.o: rs5c372.c \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/common.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/mv_kw.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/cmd_confdefs.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/bitops.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/config.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/stddef.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/posix_types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/linux/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/string.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/ptrace.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/proc/ptrace.h \ + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/include/stdarg.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/part.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/ide.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/flash.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/image.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/global_data.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/mach-types.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/setup.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/asm/u-boot-arm.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/command.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/rtc.h \ + /home/motomi/subversion/NasFirmware/u-boot/branches/u-boot-1.1.4_kw_testwol/include/i2c.h diff --git a/rules.mk b/rules.mk new file mode 100644 index 0000000..a77451b --- /dev/null +++ b/rules.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +_depend: $(obj).depend + +$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(SRCS) + @rm -f $@ + @for f in $(SRCS); do \ + g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \ + $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ + done + +######################################################################### diff --git a/tools/.depend b/tools/.depend new file mode 100644 index 0000000..e0ec6ac --- /dev/null +++ b/tools/.depend @@ -0,0 +1,161 @@ +environment.o: environment.c ../include/config.h \ + ../include/configs/mv_kw.h \ + ../include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + ../include/cmd_confdefs.h ../include/environment.h +img2srec.o: img2srec.c \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stddef.h \ + /usr/include/stdio.h /usr/include/features.h /usr/include/bits/predefs.h \ + /usr/include/sys/cdefs.h /usr/include/bits/wordsize.h \ + /usr/include/gnu/stubs.h /usr/include/gnu/stubs-32.h \ + /usr/include/bits/types.h /usr/include/bits/typesizes.h \ + /usr/include/libio.h /usr/include/_G_config.h /usr/include/wchar.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stdarg.h \ + /usr/include/bits/stdio_lim.h /usr/include/bits/sys_errlist.h \ + /usr/include/stdlib.h /usr/include/bits/waitflags.h \ + /usr/include/bits/waitstatus.h /usr/include/endian.h \ + /usr/include/bits/endian.h /usr/include/bits/byteswap.h \ + /usr/include/sys/types.h /usr/include/time.h /usr/include/sys/select.h \ + /usr/include/bits/select.h /usr/include/bits/sigset.h \ + /usr/include/bits/time.h /usr/include/sys/sysmacros.h \ + /usr/include/bits/pthreadtypes.h /usr/include/alloca.h \ + /usr/include/ctype.h /usr/include/xlocale.h /usr/include/string.h \ + /usr/include/elf.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stdint.h \ + /usr/include/stdint.h /usr/include/bits/wchar.h /usr/include/unistd.h \ + /usr/include/bits/posix_opt.h /usr/include/bits/environments.h \ + /usr/include/bits/confname.h /usr/include/getopt.h /usr/include/errno.h \ + /usr/include/bits/errno.h /usr/include/linux/errno.h \ + /usr/include/i386-linux-gnu/asm/errno.h /usr/include/asm-generic/errno.h \ + /usr/include/asm-generic/errno-base.h +mkimage.o: mkimage.c /usr/include/errno.h /usr/include/features.h \ + /usr/include/bits/predefs.h /usr/include/sys/cdefs.h \ + /usr/include/bits/wordsize.h /usr/include/gnu/stubs.h \ + /usr/include/gnu/stubs-32.h /usr/include/bits/errno.h \ + /usr/include/linux/errno.h /usr/include/i386-linux-gnu/asm/errno.h \ + /usr/include/asm-generic/errno.h /usr/include/asm-generic/errno-base.h \ + /usr/include/fcntl.h /usr/include/bits/fcntl.h /usr/include/sys/types.h \ + /usr/include/bits/types.h /usr/include/bits/typesizes.h \ + /usr/include/time.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stddef.h \ + /usr/include/endian.h /usr/include/bits/endian.h \ + /usr/include/bits/byteswap.h /usr/include/sys/select.h \ + /usr/include/bits/select.h /usr/include/bits/sigset.h \ + /usr/include/bits/time.h /usr/include/sys/sysmacros.h \ + /usr/include/bits/pthreadtypes.h /usr/include/bits/stat.h \ + /usr/include/stdio.h /usr/include/libio.h /usr/include/_G_config.h \ + /usr/include/wchar.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stdarg.h \ + /usr/include/bits/stdio_lim.h /usr/include/bits/sys_errlist.h \ + /usr/include/stdlib.h /usr/include/bits/waitflags.h \ + /usr/include/bits/waitstatus.h /usr/include/alloca.h \ + /usr/include/string.h /usr/include/xlocale.h /usr/include/netinet/in.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stdint.h \ + /usr/include/stdint.h /usr/include/bits/wchar.h \ + /usr/include/sys/socket.h /usr/include/sys/uio.h /usr/include/bits/uio.h \ + /usr/include/bits/socket.h /usr/include/bits/sockaddr.h \ + /usr/include/i386-linux-gnu/asm/socket.h \ + /usr/include/asm-generic/socket.h \ + /usr/include/i386-linux-gnu/asm/sockios.h \ + /usr/include/asm-generic/sockios.h /usr/include/bits/in.h \ + /usr/include/sys/mman.h /usr/include/bits/mman.h /usr/include/sys/stat.h \ + /usr/include/unistd.h /usr/include/bits/posix_opt.h \ + /usr/include/bits/environments.h /usr/include/bits/confname.h \ + /usr/include/getopt.h ../include/image.h +crc32.o: crc32.c /usr/include/zlib.h /usr/include/zconf.h \ + /usr/include/zlibdefs.h /usr/include/sys/types.h /usr/include/features.h \ + /usr/include/bits/predefs.h /usr/include/sys/cdefs.h \ + /usr/include/bits/wordsize.h /usr/include/gnu/stubs.h \ + /usr/include/gnu/stubs-32.h /usr/include/bits/types.h \ + /usr/include/bits/typesizes.h /usr/include/time.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stddef.h \ + /usr/include/endian.h /usr/include/bits/endian.h \ + /usr/include/bits/byteswap.h /usr/include/sys/select.h \ + /usr/include/bits/select.h /usr/include/bits/sigset.h \ + /usr/include/bits/time.h /usr/include/sys/sysmacros.h \ + /usr/include/bits/pthreadtypes.h /usr/include/unistd.h \ + /usr/include/bits/posix_opt.h /usr/include/bits/environments.h \ + /usr/include/bits/confname.h /usr/include/getopt.h +envcrc.o: envcrc.c /usr/include/stdio.h /usr/include/features.h \ + /usr/include/bits/predefs.h /usr/include/sys/cdefs.h \ + /usr/include/bits/wordsize.h /usr/include/gnu/stubs.h \ + /usr/include/gnu/stubs-32.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stddef.h \ + /usr/include/bits/types.h /usr/include/bits/typesizes.h \ + /usr/include/libio.h /usr/include/_G_config.h /usr/include/wchar.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stdarg.h \ + /usr/include/bits/stdio_lim.h /usr/include/bits/sys_errlist.h \ + /usr/include/stdlib.h /usr/include/bits/waitflags.h \ + /usr/include/bits/waitstatus.h /usr/include/endian.h \ + /usr/include/bits/endian.h /usr/include/bits/byteswap.h \ + /usr/include/sys/types.h /usr/include/time.h /usr/include/sys/select.h \ + /usr/include/bits/select.h /usr/include/bits/sigset.h \ + /usr/include/bits/time.h /usr/include/sys/sysmacros.h \ + /usr/include/bits/pthreadtypes.h /usr/include/alloca.h \ + /usr/include/unistd.h /usr/include/bits/posix_opt.h \ + /usr/include/bits/environments.h /usr/include/bits/confname.h \ + /usr/include/getopt.h ../include/config.h ../include/configs/mv_kw.h \ + ../include/configs/../../board/mv_feroceon/mv_kw/mvSysHwConfig.h \ + ../include/cmd_confdefs.h +gen_eth_addr.o: gen_eth_addr.c /usr/include/stdio.h \ + /usr/include/features.h /usr/include/bits/predefs.h \ + /usr/include/sys/cdefs.h /usr/include/bits/wordsize.h \ + /usr/include/gnu/stubs.h /usr/include/gnu/stubs-32.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stddef.h \ + /usr/include/bits/types.h /usr/include/bits/typesizes.h \ + /usr/include/libio.h /usr/include/_G_config.h /usr/include/wchar.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stdarg.h \ + /usr/include/bits/stdio_lim.h /usr/include/bits/sys_errlist.h \ + /usr/include/stdlib.h /usr/include/bits/waitflags.h \ + /usr/include/bits/waitstatus.h /usr/include/endian.h \ + /usr/include/bits/endian.h /usr/include/bits/byteswap.h \ + /usr/include/sys/types.h /usr/include/time.h /usr/include/sys/select.h \ + /usr/include/bits/select.h /usr/include/bits/sigset.h \ + /usr/include/bits/time.h /usr/include/sys/sysmacros.h \ + /usr/include/bits/pthreadtypes.h /usr/include/alloca.h \ + /usr/include/unistd.h /usr/include/bits/posix_opt.h \ + /usr/include/bits/environments.h /usr/include/bits/confname.h \ + /usr/include/getopt.h /usr/include/xlocale.h +bmp_logo.o: bmp_logo.c /usr/include/stdio.h /usr/include/features.h \ + /usr/include/bits/predefs.h /usr/include/sys/cdefs.h \ + /usr/include/bits/wordsize.h /usr/include/gnu/stubs.h \ + /usr/include/gnu/stubs-32.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stddef.h \ + /usr/include/bits/types.h /usr/include/bits/typesizes.h \ + /usr/include/libio.h /usr/include/_G_config.h /usr/include/wchar.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stdarg.h \ + /usr/include/bits/stdio_lim.h /usr/include/bits/sys_errlist.h \ + /usr/include/stdlib.h /usr/include/bits/waitflags.h \ + /usr/include/bits/waitstatus.h /usr/include/endian.h \ + /usr/include/bits/endian.h /usr/include/bits/byteswap.h \ + /usr/include/sys/types.h /usr/include/time.h /usr/include/sys/select.h \ + /usr/include/bits/select.h /usr/include/bits/sigset.h \ + /usr/include/bits/time.h /usr/include/sys/sysmacros.h \ + /usr/include/bits/pthreadtypes.h /usr/include/alloca.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stdint.h \ + /usr/include/stdint.h /usr/include/bits/wchar.h +doimage.o: doimage.c /usr/include/errno.h /usr/include/features.h \ + /usr/include/bits/predefs.h /usr/include/sys/cdefs.h \ + /usr/include/bits/wordsize.h /usr/include/gnu/stubs.h \ + /usr/include/gnu/stubs-32.h /usr/include/bits/errno.h \ + /usr/include/linux/errno.h /usr/include/i386-linux-gnu/asm/errno.h \ + /usr/include/asm-generic/errno.h /usr/include/asm-generic/errno-base.h \ + /usr/include/fcntl.h /usr/include/bits/fcntl.h /usr/include/sys/types.h \ + /usr/include/bits/types.h /usr/include/bits/typesizes.h \ + /usr/include/time.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stddef.h \ + /usr/include/endian.h /usr/include/bits/endian.h \ + /usr/include/bits/byteswap.h /usr/include/sys/select.h \ + /usr/include/bits/select.h /usr/include/bits/sigset.h \ + /usr/include/bits/time.h /usr/include/sys/sysmacros.h \ + /usr/include/bits/pthreadtypes.h /usr/include/bits/stat.h \ + /usr/include/stdio.h /usr/include/libio.h /usr/include/_G_config.h \ + /usr/include/wchar.h \ + /usr/lib/i386-linux-gnu/gcc/i686-linux-gnu/4.5.2/include/stdarg.h \ + /usr/include/bits/stdio_lim.h /usr/include/bits/sys_errlist.h \ + /usr/include/stdlib.h /usr/include/bits/waitflags.h \ + /usr/include/bits/waitstatus.h /usr/include/alloca.h \ + /usr/include/string.h /usr/include/xlocale.h /usr/include/sys/stat.h \ + /usr/include/unistd.h /usr/include/bits/posix_opt.h \ + /usr/include/bits/environments.h /usr/include/bits/confname.h \ + /usr/include/getopt.h /usr/include/sys/mman.h /usr/include/bits/mman.h \ + bootstrap_def.h bootstrap_os.h diff --git a/tools/Makefile b/tools/Makefile index d3dcc7d..9356634 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -21,9 +21,9 @@ # MA 02111-1307 USA # -BINS = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) +BINS = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) doimage$(SFX) -OBJS = environment.o img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o +OBJS = environment.o img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o doimage.o ifeq ($(ARCH),mips) BINS += inca-swap-bytes$(SFX) @@ -105,12 +105,13 @@ endif # so that we can act intelligently. # include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk # # Use native tools and options # -CPPFLAGS = -idirafter ../include -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC -CFLAGS = $(HOST_CFLAGS) $(CPPFLAGS) -O +CPPFLAGS = -idirafter ../include -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC $(MV_IMAGE_FLAGS) +CFLAGS = $(HOST_CFLAGS) $(CPPFLAGS) -O AFLAGS = -D__ASSEMBLY__ $(CPPFLAGS) CC = $(HOSTCC) STRIP = $(HOSTSTRIP) @@ -141,6 +142,10 @@ bmp_logo$(SFX): bmp_logo.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ +doimage$(SFX): doimage.o + $(CC) -DMV_CPU_LE $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + inca-swap-bytes$(SFX): inca-swap-bytes.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ @@ -198,6 +203,9 @@ crc32.c: $(LOGO_H): bmp_logo $(LOGO_BMP) ./bmp_logo $(LOGO_BMP) >$@ +doimage.o: doimage.c + $(CC) -g -DMV_CPU_LE -c $< + ######################################################################### .depend: Makefile $(OBJS:.o=.c) @@ -206,3 +214,11 @@ $(LOGO_H): bmp_logo $(LOGO_BMP) sinclude .depend ######################################################################### + + +clean: + find . -type f \ + \( -name 'core' -o -name '*.bak' -o -name '*~' \ + -o -name '*.o' -o -name '*.a' \) -print \ + | xargs rm -f + rm -f $(ELF) $(SREC) $(BIN) $(DIS) bootstrap.map diff --git a/tools/Makefile_doimage b/tools/Makefile_doimage new file mode 100644 index 0000000..9889afa --- /dev/null +++ b/tools/Makefile_doimage @@ -0,0 +1,41 @@ +STRIP = strip + +# +# Include the make variables (CC, etc...) +# +LD = ld +CC = gcc +OBJCOPY = objcopy +OBJDUMP = objdump + + +CFLAGS = -DMV_CPU_LE +LDFLAGS = + +BIN = doimage + +all: $(BIN) +doimage: doimage.o + $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ + $(STRIP) $@ + +doimage.o: doimage.c + $(CC) -g $(CFLAGS) -c $< + + +clean: + find . -type f \ + \( -name 'core' -o -name '*.bak' -o -name '*~' \ + -o -name '*.o' -o -name '*.a' \) -print \ + | xargs rm -f + rm -f $(ELF) $(SREC) $(BIN) $(DIS) bootstrap.map + + + + + + + + + + diff --git a/tools/bootstrap_def.h b/tools/bootstrap_def.h new file mode 100644 index 0000000..ad0ddb8 --- /dev/null +++ b/tools/bootstrap_def.h @@ -0,0 +1,122 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef _INC_BOOTSTRAP__DEF_H +#define _INC_BOOTSTRAP__DEF_H +#include "bootstrap_os.h" + +#ifndef MV_ASMLANGUAGE + +typedef struct BHR_t +{ +// type name byte order + MV_U8 blockID; //0 + MV_U8 nandEccMode; //1 + MV_U16 nandPageSize; //2-3 + MV_U32 blockSize; //4-7 + MV_U32 rsvd1; //8-11 + MV_U32 sourceAddr; //12-15 + MV_U32 destinationAddr; //16-19 + MV_U32 executionAddr; //20-23 + MV_U8 sataPioMode; //24 + MV_U8 rsvd3; //25 + MV_U16 ddrInitDelay; //26-27 + MV_U16 rsvd2; //28-29 + MV_U8 ext; //30 + MV_U8 checkSum; //31 +} BHR_t, * pBHR_t; + + +typedef struct ExtBHR_t +{ +// type name byte order + MV_U32 dramRegsOffs; //0-3 + MV_U32 rsrvd1; //4-7 + MV_U32 rsrvd2; //8-11 + MV_U32 rsrvd3; //12-15 + MV_U32 rsrvd4; //16-19 + MV_U32 rsrvd5; //20-23 + MV_U32 rsrvd6; //24-27 + MV_U16 rsrvd7; //28-29 + MV_U8 rsrvd8; //30 + MV_U8 checkSum; //31 +}ExtBHR_t, *pExtBHR_t; + +#define BOOTROM_SIZE (12 * 1024) +#define HEADER_SIZE 512 +#define BHR_HDR_SIZE 0x20 +#define EXT_HEADER_SIZE (HEADER_SIZE - BHR_HDR_SIZE) + +/* Boot Type - block ID */ +#define IBR_HDR_I2C_ID 0x4D +#define IBR_HDR_SPI_ID 0x5A +#define IBR_HDR_NAND_ID 0x8B +#define IBR_HDR_SATA_ID 0x78 +#define IBR_HDR_PEX_ID 0x9C +#define IBR_HDR_UART_ID 0x69 +#define IBR_DEF_ATTRIB 0x00 + +#endif /* MV_ASMLANGUAGE */ +#endif /* _INC_BOOTSTRAP_H */ + diff --git a/tools/bootstrap_os.h b/tools/bootstrap_os.h new file mode 100644 index 0000000..eff8ac3 --- /dev/null +++ b/tools/bootstrap_os.h @@ -0,0 +1,473 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef _INC_BOOTSTRAP_OS_H +#define _INC_BOOTSTRAP_OS_H + +/* BE/ LE swap for Asm */ +#if defined(MV_CPU_LE) + +#define htoll(x) x +#define HTOLL(sr,tr) + +#elif defined(MV_CPU_BE) + +#define htoll(x) ((((x) & 0x00ff) << 24) | \ + (((x) & 0xff00) << 8) | \ + (((x) >> 8) & 0xff00) | \ + (((x) >> 24) & 0x00ff)) + + +#define HTOLL(sr,temp) /*sr = A ,B ,C ,D */\ + eor temp, sr, sr, ROR #16 ; /*temp = A^C,B^D,C^A,D^B */\ + bic temp, temp, #0xFF0000 ; /*temp = A^C,0 ,C^A,D^B */\ + mov sr, sr, ROR #8 ; /*sr = D ,A ,B ,C */\ + eor sr, sr, temp, LSR #8 /*sr = D ,C ,B ,A */ + +#endif + +#define MV_REG_READ_ASM(toReg, tmpReg, regOffs) \ + ldr tmpReg, =(INTER_REGS_BASE + regOffs) ; \ + ldr toReg, [tmpReg] ; \ + HTOLL(toReg,tmpReg) + +#define MV_REG_WRITE_ASM(fromReg, tmpReg, regOffs) \ + HTOLL(fromReg,tmpReg) ; \ + ldr tmpReg, =(INTER_REGS_BASE + regOffs) ; \ + str fromReg, [tmpReg] + +#define MV_DV_REG_READ_ASM(toReg, tmpReg, regOffs) \ + ldr tmpReg, =(CFG_DFL_MV_REGS + regOffs) ; \ + ldr toReg, [tmpReg] ; \ + HTOLL(toReg,tmpReg) + +#define MV_DV_REG_WRITE_ASM(fromReg, tmpReg, regOffs) \ + HTOLL(fromReg,tmpReg) ; \ + ldr tmpReg, =(CFG_DFL_MV_REGS + regOffs) ; \ + str fromReg, [tmpReg] + + + + +/* Defines */ + +/* The following is a list of Marvell status */ +#define MV_ERROR (-1) +#define MV_OK (0x00) /* Operation succeeded */ +#define MV_FAIL (0x01) /* Operation failed */ +#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ +#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ +#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ +#define MV_BAD_PTR (0x05) /* Illegal pointer value */ +#define MV_BAD_SIZE (0x06) /* Illegal size */ +#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ +#define MV_SET_ERROR (0x08) /* Set operation failed */ +#define MV_GET_ERROR (0x09) /* Get operation failed */ +#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ +#define MV_NOT_FOUND (0x0B) /* Item not found */ +#define MV_NO_MORE (0x0C) /* No more items found */ +#define MV_NO_SUCH (0x0D) /* No such item */ +#define MV_TIMEOUT (0x0E) /* Time Out */ +#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ +#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ +#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ +#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ +#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ +#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ +#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ +#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ +#define MV_HW_ERROR (0x17) /* Hardware error */ +#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ +#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ +#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ +#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ +#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ +#define MV_NOT_STARTED (0x1D) /* Not started yet */ +#define MV_BUSY (0x1E) /* Item is busy. */ +#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ +#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ +#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ +#define MV_WRITE_PROTECT (0x22) /* Write protected */ + + +#define MV_INVALID (int)(-1) + +#define MV_FALSE 0 +#define MV_TRUE (!(MV_FALSE)) + + +#ifndef NULL +#define NULL ((void*)0) +#endif + + +#ifndef MV_ASMLANGUAGE +/* typedefs */ + +typedef char MV_8; +typedef unsigned char MV_U8; + +typedef int MV_32; +typedef unsigned int MV_U32; + +typedef short MV_16; +typedef unsigned short MV_U16; + +#ifdef MV_PPC64 +typedef long MV_64; +typedef unsigned long MV_U64; +#else +typedef long long MV_64; +typedef unsigned long long MV_U64; +#endif + +typedef long MV_LONG; /* 32/64 */ +typedef unsigned long MV_ULONG; /* 32/64 */ + +typedef int MV_STATUS; +typedef int MV_BOOL; +/*typedef void MV_VOID;*/ +#define MV_VOID void +typedef float MV_FLOAT; + +typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ +typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ +typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ +typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ + +typedef MV_U32 MV_KHZ; +typedef MV_U32 MV_MHZ; +typedef MV_U32 MV_HZ; +#if defined(_HOST_COMPILER) +#define __MV_PACKED +#else +#define __MV_PACKED /*__packed*/ +#endif + +#endif /* MV_ASMLANGUAGE */ + +/* Bit field definitions */ +#define NO_BIT 0x00000000 +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +/* includes */ +#define _1K 0x00000400 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 +/* Sizes */ +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 +#define _1G 0x40000000 +#define _2G 0x80000000 +/* Speed */ +#define _133MHZ 133333333 +#define _150MHZ 150000000 +#define _166MHZ 166666667 +#define _200MHZ 200000000 + +/* Swap tool */ + +/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ +#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ + ((X&0xf0) >> 4) | \ + ((X&0xf00) << 4) | \ + ((X&0xf000) >> 4)) + +/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ +#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ + ((X&0xf0) >> 4) | \ + ((X&0xf00) << 4) | \ + ((X&0xf000) >> 4) | \ + ((X&0xf0000) << 4) | \ + ((X&0xf00000) >> 4) | \ + ((X&0xf000000) << 4) | \ + ((X&0xf0000000) >> 4)) + +/* 16bit byte swap. For example 0x1122 -> 0x2211 */ +#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) + +/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ +#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ + (((X)&0xff00)<<8) | \ + (((X)&0xff0000)>>8) | \ + (((X)&0xff000000)>>24)) + +/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ +#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ + (((X)&0xff00ULL)<<40) | \ + (((X)&0xff0000ULL)<<24) | \ + (((X)&0xff000000ULL)<<8) | \ + (((X)&0xff00000000ULL)>>8) | \ + (((X)&0xff0000000000ULL)>>24) | \ + (((X)&0xff000000000000ULL)>>40) | \ + (((X)&0xff00000000000000ULL)>>56))) + +/* Endianess macros. */ +#if defined(MV_CPU_LE) + #define MV_16BIT_LE(X) (X) + #define MV_32BIT_LE(X) (X) + #define MV_64BIT_LE(X) (X) + #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) + #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) + #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) +#elif defined(MV_CPU_BE) + #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) + #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) + #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) + #define MV_16BIT_BE(X) (X) + #define MV_32BIT_BE(X) (X) + #define MV_64BIT_BE(X) (X) +#endif + + + +#ifndef MV_ASMLANGUAGE +/* Get the min between 'a' or 'b' */ +#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) + + +/* Marvell controller register read/write macros */ +#define CPU_PHY_MEM(x) (MV_U32)x +#define CPU_MEMIO_CACHED_ADDR(x) (void*)x +#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x + + +/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ +#define MV_MEMIO32_WRITE(addr, data) \ + ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) + +#define MV_MEMIO32_READ(addr) \ + ((*((volatile unsigned int*)(addr)))) + +#define MV_MEMIO16_WRITE(addr, data) \ + ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) + +#define MV_MEMIO16_READ(addr) \ + ((*((volatile unsigned short*)(addr)))) + +#define MV_MEMIO8_WRITE(addr, data) \ + ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) + +#define MV_MEMIO8_READ(addr) \ + ((*((volatile unsigned char*)(addr)))) + + +/* No Fast Swap implementation (in assembler) for ARM */ +#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) +#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) +#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) +#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) + +/* 32 and 16 bit read/write in big/little endian mode */ + +/* 16bit write in little endian mode */ +#define MV_MEMIO_LE16_WRITE(addr, data) \ + MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) + +/* 16bit read in little endian mode */ +static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) +{ + MV_U16 data; + + data= (MV_U16)MV_MEMIO16_READ(addr); + + return (MV_U16)MV_16BIT_LE_FAST(data); +} + +/* 32bit write in little endian mode */ +#define MV_MEMIO_LE32_WRITE(addr, data) \ + MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) + +/* 32bit read in little endian mode */ +static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) +{ + MV_U32 data; + + data= (MV_U32)MV_MEMIO32_READ(addr); + + return (MV_U32)MV_32BIT_LE_FAST(data); +} + +/* Flash APIs */ +#define MV_FL_8_READ MV_MEMIO8_READ +#define MV_FL_16_READ MV_MEMIO_LE16_READ +#define MV_FL_32_READ MV_MEMIO_LE32_READ +#define MV_FL_8_DATA_READ MV_MEMIO8_READ +#define MV_FL_16_DATA_READ MV_MEMIO16_READ +#define MV_FL_32_DATA_READ MV_MEMIO32_READ +#define MV_FL_8_WRITE MV_MEMIO8_WRITE +#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE +#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE +#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE +#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE +#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE + + +/* CPU cache information */ +#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ +#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ + + +#define MV_REG_VALUE(offset) \ + (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) + +#define MV_REG_READ(offset) \ + (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) + +#define MV_REG_WRITE(offset, val) \ + MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)) + +#define MV_REG_BYTE_READ(offset) \ + (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) + +#define MV_REG_BYTE_WRITE(offset, val) \ + MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) + +#define MV_REG_SHORT_READ(offset) \ + (MV_MEMIO_LE16_READ(INTER_REGS_BASE | (offset))) + + +#define MV_REG_BIT_SET(offset, bitMask) \ + (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ + (MV_MEMIO32_READ((INTER_REGS_BASE | (offset))) | \ + MV_32BIT_LE_FAST((bitMask))))) + +#define MV_REG_BIT_RESET(offset,bitMask) \ + (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ + (MV_MEMIO32_READ((INTER_REGS_BASE | (offset))) & \ + MV_32BIT_LE_FAST(~(bitMask))))) + + +#define mvOsDelay(us) uDelay(us*1000) +#define mvOsUDelay uDelay + + +#define u32 MV_U32 +#define u16 MV_U16 +#define u8 MV_U8 +#define s16 short +#define s32 long +#define s8 char + +#define UINT32 MV_U32 +#define UINT16 MV_U16 +#define UINT8 MV_U8 + +typedef UINT32* PUINT32; +typedef UINT16* PUINT16; +typedef UINT8* PUINT8; + +#define TRUE MV_TRUE +#define FALSE MV_FALSE + + + +#endif /* #ifndef MV_ASMLANGUAGE */ + +#endif /* _INC_BOOTSTRAP_OS_H */ + diff --git a/tools/crc32.c b/tools/crc32.c new file mode 120000 index 0000000..be36f5c --- /dev/null +++ b/tools/crc32.c @@ -0,0 +1 @@ +../lib_generic/crc32.c \ No newline at end of file diff --git a/tools/doimage b/tools/doimage new file mode 100755 index 0000000..8ea2093 Binary files /dev/null and b/tools/doimage differ diff --git a/tools/doimage.c b/tools/doimage.c new file mode 100644 index 0000000..27c4b8c --- /dev/null +++ b/tools/doimage.c @@ -0,0 +1,1263 @@ + +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define _HOST_COMPILER +#include "bootstrap_def.h" + +#ifndef O_BINARY /* should be define'd on __WIN32__ */ +#define O_BINARY 0 +#endif + +#define DOIMAGE_VERSION "1.00" + +void print_usage(void); + +int f_in = -1; +int f_out = -1; +int f_header = -1; + + +typedef enum +{ + IMG_SATA, + IMG_UART, + IMG_FLASH, + IMG_BOOTROM, + IMG_NAND, + IMG_HEX, + IMG_BIN, + IMG_PEX, + IMG_I2C +}IMG_TYPE; + +typedef enum +{ + HDR_IMG_ONE_FILE = 1, /* Create one file with header and image */ + HDR_IMG_TWO_FILES = 2, /* Create seperate header and image files */ + HDR_ONLY = 3, /* Create only header */ + IMG_ONLY = 4, /* Create only image */ + +}HEADER_MODE; + + +#define T_OPTION_MASK 0x1 /* image type */ +#define D_OPTION_MASK 0x2 /* image destination */ +#define E_OPTION_MASK 0x4 /* image execution address */ +#define S_OPTION_MASK 0x8 /* image source */ +#define R_OPTION_MASK 0x10 /* DRAM file */ +#define C_OPTION_MASK 0x20 /* NAND ECC mode */ +#define P_OPTION_MASK 0x40 /* NAND Page size */ +#define M_OPTION_MASK 0x80 /* TWSI serial init file */ +#define W_OPTION_MASK 0x100 /* HEX file width */ +#define H_OPTION_MASK 0x200 /* Header mode*/ +#define X_OPTION_MASK 0x400 /* Pre padding */ +#define Y_OPTION_MASK 0x800 /* Post padding*/ +#define I_OPTION_MASK 0x1000 /* SATA PIO mode*/ +#define L_OPTION_MASK 0x2000 /* delay time in mseconds*/ + + + +#define SATA_MUST_OPT (D_OPTION_MASK|T_OPTION_MASK|E_OPTION_MASK|S_OPTION_MASK) +#define UART_MUST_OPT (D_OPTION_MASK|T_OPTION_MASK|E_OPTION_MASK) +#define FLASH_MUST_OPT (D_OPTION_MASK|T_OPTION_MASK|E_OPTION_MASK) +#define PEX_MUST_OPT (D_OPTION_MASK|T_OPTION_MASK|E_OPTION_MASK) +#define I2C_MUST_OPT (D_OPTION_MASK|T_OPTION_MASK|E_OPTION_MASK|M_OPTION_MASK) +#define MAX_TWSI_HDR_SIZE (60*1024) /* MAX eeprom is 64K & leave 4K for image and header */ +#define BOOTROM_MUST_OPT (T_OPTION_MASK) + +#define NAND_MUST_OPT (D_OPTION_MASK|T_OPTION_MASK|E_OPTION_MASK|P_OPTION_MASK) +#define HEX_MUST_OPT (T_OPTION_MASK|W_OPTION_MASK) +#define BIN_MUST_OPT (T_OPTION_MASK|W_OPTION_MASK) + +/* 32 bit checksum */ +u32 checksum32(/*u32*/void* start, u32 len, u32 csum); +u8 checksum8(/*u32*/void* start, u32 len,u8 csum); +u32 crc32(u32 crc, volatile u32 *buf, u32 len); + +int main(int argc,char** argv) +{ + char *image_type = NULL; + IMG_TYPE img; + unsigned int image_dest=0,image_exec=0,header_size=0, image_source = 0, twsi_size=0; + char *fname_in,*fname_out=NULL,*fname_hdr_out=NULL,*fname_romc=NULL, + *fname_dram=NULL,*fname_twsi=NULL; + char *inst_set; + unsigned char *ptr; + BHR_t hdr; + ExtBHR_t extHdr; + struct stat fs_stat,fs_stat_code; + char *buf_in = NULL ,*buf_code = NULL; + int override[2]; + int err,size_written=0; + char *tmpHeader = NULL; + char *tmpTwsi = NULL; + unsigned int opts=0,required_opts = 0; + unsigned int chsum32 = 0; + unsigned int nandPageSize=0, nandEccMode=0, hex_width=0,header_mode = HDR_IMG_ONE_FILE,ms_delay=0; + FILE* f_dram, *f_hex,*f_hex2, *f_hex3, *f_twsi; + int f_code; + unsigned char *hex8=NULL, tmp8; + unsigned short *hex16=NULL, tmp16; + unsigned long *hex32=NULL, tmp32; + unsigned long lastDword = 0; + int i=0; + unsigned int bytesToAlign=0; + char** f_out_names[2]; + int pre_padding=0, post_padding=0, padding_size=0; + #define IMG_FILE_INDX 0 + #define HDR_FILE_INDX 1 + + f_out_names[IMG_FILE_INDX] = &fname_out; + f_out_names[HDR_FILE_INDX] = &fname_hdr_out; + + memset((void*)&hdr,0,sizeof(BHR_t)); + memset((void*)&extHdr,0,sizeof(ExtBHR_t)); + + if (argc ==1) + { + print_usage(); + exit(1); + } + + while (--argc > 0 && **++argv == '-') + { + while (*++*argv) + { + switch (**argv) + { + case 'T': /* image type */ + if (--argc <= 0) {print_usage();exit(1);} + image_type = *++argv; + if (opts & T_OPTION_MASK) {print_usage();exit(1);} + opts |= T_OPTION_MASK; + break; + case 'D': /* image destination */ + if (--argc <= 0) {print_usage();exit(1);} + image_dest = strtoul (*++argv, (char **)&ptr, 16); + if (*ptr) {print_usage();exit(1);} + if (opts & D_OPTION_MASK) {print_usage();exit(1);} + opts |= D_OPTION_MASK; + break; + case 'E': /* image execution */ + if (--argc <= 0) {print_usage();exit(1);} + image_exec = strtoul (*++argv, (char **)&ptr, 16); + if (*ptr) {print_usage();exit(1);} + if (opts & E_OPTION_MASK) {print_usage();exit(1);} + opts |= E_OPTION_MASK; + break; + case 'X': /* Pre - Padding */ + if (--argc <= 0) {print_usage();exit(1);} + padding_size = strtoul (*++argv, (char **)&ptr, 16); + pre_padding=1; + if (*ptr) {print_usage();exit(1);} + if (opts & X_OPTION_MASK) {print_usage();exit(1);} + opts |= X_OPTION_MASK; + break; + case 'Y': /* Post - Padding */ + if (--argc <= 0) {print_usage();exit(1);} + padding_size = strtoul (*++argv, (char **)&ptr, 16); + post_padding=1; + if (*ptr) {print_usage();exit(1);} + if (opts & Y_OPTION_MASK) {print_usage();exit(1);} + opts |= Y_OPTION_MASK; + break; + case 'I': /* PIO */ + if (argc <= 0) {print_usage();exit(1);} + if (opts & I_OPTION_MASK) {print_usage();exit(1);} + opts |= I_OPTION_MASK; + break; + case 'S': /* starting sector */ + if (--argc <= 0) {print_usage();exit(1);} + image_source = strtoul (*++argv, (char **)&ptr, 16); + if (*ptr) {print_usage();exit(1);} + if (opts & S_OPTION_MASK) {print_usage();exit(1);} + opts |= S_OPTION_MASK; + break; + case 'P': /* NAND Page Size */ + if (--argc <= 0) {print_usage();exit(1);} + nandPageSize = strtoul (*++argv, (char **)&ptr, 10); + if (*ptr) {print_usage();exit(1);} + if (opts & P_OPTION_MASK) {print_usage();exit(1);} + opts |= P_OPTION_MASK; + break; + case 'C': /* NAND ECC mode */ + if (--argc <= 0) {print_usage();exit(1);} + nandEccMode = strtoul (*++argv, (char **)&ptr, 10); + if (*ptr) {print_usage();exit(1);} + if (opts & C_OPTION_MASK) {print_usage();exit(1);} + opts |= C_OPTION_MASK; + break; + case 'L': /* Delay time */ + if (--argc <= 0) {print_usage();exit(1);} + ms_delay = strtoul (*++argv, (char **)&ptr, 10); + if (*ptr) {print_usage();exit(1);} + if (opts & L_OPTION_MASK) {print_usage();exit(1);} + opts |= L_OPTION_MASK; + break; + case 'W': /* HEX file width */ + if (--argc <= 0) {print_usage();exit(1);} + hex_width = strtoul (*++argv, (char **)&ptr, 10); + if (*ptr) {print_usage();exit(1);} + if (opts & W_OPTION_MASK) {print_usage();exit(1);} + opts |= W_OPTION_MASK; + break; + case 'H': /* Header file mode */ + if (--argc <= 0) {print_usage();exit(1);} + header_mode = strtoul (*++argv, (char **)&ptr, 10); + if (*ptr) {print_usage();exit(1);} + if (opts & H_OPTION_MASK) {print_usage();exit(1);} + opts |= H_OPTION_MASK; + break; + case 'R': /* dram file*/ + if (--argc <= 0) {print_usage();exit(1);} + fname_dram = *++argv; + if (opts & R_OPTION_MASK) {print_usage();exit(1);} + opts |= R_OPTION_MASK; + break; + case 'M': /* TWSI serial init file*/ + if (--argc <= 0) {print_usage();exit(1);} + fname_twsi = *++argv; + if (opts & M_OPTION_MASK) {print_usage();exit(1);} + opts |= M_OPTION_MASK; + break; + } + } + } + + /* 2 sperate images is used with SATA only */ + if (header_mode == HDR_IMG_TWO_FILES) + { + if (!(opts & S_OPTION_MASK)) + { + fprintf(stderr,"Error: -S option is missing\n\n\n\n\n"); + print_usage();exit(1); + } + } + + /* verify HEX file width selection to be valid */ + if (opts & W_OPTION_MASK) + { + if ((hex_width != 8)&&(hex_width != 16)&&(hex_width != 32)&&(hex_width != 64)) + {print_usage();exit(1);} + } + + /* get the minimum option set based on boot mode */ + if (opts & T_OPTION_MASK) + { + if (strcmp(image_type, "sata") == 0) + { + img=IMG_SATA; + required_opts = SATA_MUST_OPT; + } + else if (strcmp(image_type, "nand") == 0) + { + img=IMG_NAND; + required_opts = NAND_MUST_OPT; + } + else if (strcmp(image_type, "hex") == 0) + { + img=IMG_HEX; + required_opts = HEX_MUST_OPT; + } + else if (strcmp(image_type, "bin") == 0) + { + img=IMG_BIN; + required_opts = BIN_MUST_OPT; + } + else if (strcmp(image_type, "uart") == 0) + { + img=IMG_UART; + required_opts = UART_MUST_OPT; + } + else if (strcmp(image_type, "flash") == 0) + { + img=IMG_FLASH; + required_opts = FLASH_MUST_OPT; + } + else if (strcmp(image_type, "bootrom") == 0) + { + img=IMG_BOOTROM; + required_opts = BOOTROM_MUST_OPT; + } + else if (strcmp(image_type, "pex") == 0) + { + img=IMG_PEX; + required_opts = PEX_MUST_OPT; + } + else if (strcmp(image_type, "i2c") == 0) + { + img=IMG_I2C; + required_opts = I2C_MUST_OPT; + + } + else {print_usage();exit(1);} + + } + else + { + print_usage(); + exit(1); + } + + if (header_mode == IMG_ONLY) + { + required_opts &= ~(D_OPTION_MASK|E_OPTION_MASK|S_OPTION_MASK|R_OPTION_MASK|P_OPTION_MASK); + } + + if (required_opts != (opts & required_opts)) {print_usage();exit(1);} + + hdr.ddrInitDelay = ms_delay; + + hdr.destinationAddr = image_dest; + hdr.executionAddr = image_exec; + + switch (img) + { + case IMG_BOOTROM: + header_mode = IMG_ONLY; + break; + case IMG_HEX: + header_mode = IMG_ONLY; + break; + case IMG_BIN: + header_mode = IMG_ONLY; + break; + case IMG_SATA: + hdr.blockID = IBR_HDR_SATA_ID; + header_size = 512; + if (image_source) hdr.sourceAddr = image_source; + else hdr.sourceAddr = 2; /* default */ + + if (!(opts & H_OPTION_MASK)) + { + header_mode = HDR_IMG_TWO_FILES/*HDR_ONLY*/; + } + if (opts & I_OPTION_MASK) + { + hdr.sataPioMode = 1; + } + break; + case IMG_UART: + hdr.blockID = IBR_HDR_UART_ID; + if (opts & R_OPTION_MASK) + { + header_size = 512; + } else header_size = 128; + hdr.sourceAddr = header_size; + break; + case IMG_FLASH: + hdr.blockID = IBR_HDR_SPI_ID; + if (opts & R_OPTION_MASK) + { + header_size = 512; + } else header_size = sizeof(BHR_t); + if ((image_source)&&(image_source >= header_size)) + { + hdr.sourceAddr = image_source; + }else + { + hdr.sourceAddr = header_size; /* default */ + } + + break; + case IMG_NAND: + hdr.blockID = IBR_HDR_NAND_ID; + if (opts & R_OPTION_MASK) + { + header_size = 512; + } else header_size = sizeof(BHR_t); + if ((image_source)&&(image_source >= header_size)) + { + hdr.sourceAddr = image_source; + }else + { + hdr.sourceAddr = header_size; /* default */ + } + + hdr.nandPageSize = (MV_U16)nandPageSize; + hdr.nandEccMode = (MV_U8)nandEccMode; + break; + case IMG_PEX: + hdr.blockID = IBR_HDR_PEX_ID; + if (opts & R_OPTION_MASK) + { + header_size = 512; + } else header_size = sizeof(BHR_t); + if ((image_source)&&(image_source >= header_size)) + { + hdr.sourceAddr = image_source; + }else + { + hdr.sourceAddr = header_size; /* default */ + } + case IMG_I2C: + hdr.blockID = IBR_HDR_I2C_ID; + if (opts & R_OPTION_MASK) + { + header_size = 512; + } else header_size = sizeof(BHR_t); + if ((image_source)&&(image_source >= header_size)) + { + hdr.sourceAddr = image_source; + }else + { + hdr.sourceAddr = header_size; /* default */ + } + } + + if ((header_mode == HDR_IMG_TWO_FILES) || ((header_mode == IMG_ONLY) && (img == IMG_BIN))) + { + if (argc == 4) /* In case ROMC is needed */ + { + fname_in = *argv++; + fname_out = *argv++; + fname_hdr_out = *argv++; + fname_romc = *argv++; + + if ((0 == strcmp(fname_in, fname_out)) || + (0 == strcmp(fname_in, fname_hdr_out)) || + (0 == strcmp(fname_in, fname_romc)) || + (0 == strcmp(fname_out, fname_hdr_out)) || + (0 == strcmp(fname_out, fname_romc)) || + (0 == strcmp(fname_hdr_out, fname_romc))) + { + fprintf(stderr,"Error: Input and output images can't be the same\n"); + exit(1); + } + } + else if (argc == 3) + { + fname_in = *argv++; + fname_out = *argv++; + fname_hdr_out = *argv++; + + if ((0 == strcmp(fname_in, fname_out))|| + (0 == strcmp(fname_in, fname_hdr_out))|| + (0 == strcmp(fname_out, fname_hdr_out))) + { + fprintf(stderr,"Error: Input and output images can't be the same\n"); + exit(1); + } + } + else + { + print_usage(); + exit(1); + } + } + else + { + if (argc == 2) + { + fname_in = *argv++; + fname_out = *argv++; + + if (0 == strcmp(fname_in, fname_out)) + { + fprintf(stderr,"Error: Input and output images can't be the same\n"); + exit(1); + } + } + else + { + print_usage(); + exit(1); + } + } + + /* check if the output image exist */ + i = 0; + do + { + if (*f_out_names[i]) + { + f_out = open(*f_out_names[i],O_RDONLY|O_BINARY); + if (f_out != -1) + { + char c; + + close(f_out); + f_out = -1; + fprintf(stderr,"File '%s' already exist! override (y/n)?",*f_out_names[i]); + c = getc(stdin); + if ((c == 'N')||(c == 'n')) + { + printf("exit.. nothing done. \n"); + exit(0); + } + /* for the Enter */ + c = getc(stdin); + override[i] = 1; + } + else + { + override[i] = 0; + } + } + + i++; + if (i == 2) break; + }while(1); + if (header_mode != HDR_ONLY) + { + /* open input image */ + f_in = open(fname_in,O_RDONLY|O_BINARY); + if (f_in == -1) + { + fprintf(stderr,"File '%s' not found \n",fname_in); + exit(0); + } + + /* get the size of the input image */ + err = fstat(f_in, &fs_stat); + + if (0 != err) + { + close(f_in); + fprintf(stderr,"fstat failed for file: '%s' err=%d\n",fname_in,err); + exit(1); + } + + if ((fs_stat.st_size > BOOTROM_SIZE)&&(img == IMG_BOOTROM)) + { + printf("ERROR : bootstrap.bin size is bigger than %d bytes \n",BOOTROM_SIZE); + close(f_in); + exit(1); + } + /* map the input image */ + buf_in = mmap(0, fs_stat.st_size, PROT_READ, MAP_SHARED, f_in, 0); + if (!buf_in) + { + fprintf(stderr,"Error mapping %s file \n",fname_in); + goto end; + } + } + + /* open the output image */ + if (override[IMG_FILE_INDX] == 0) + { + f_out = open(fname_out,O_RDWR|O_TRUNC|O_CREAT|O_BINARY,0666); + } + else f_out = open(fname_out,O_RDWR|O_BINARY); + + if (f_out == -1) + { + fprintf(stderr,"Error openning %s file \n",fname_out); + } + + if (header_mode == HDR_IMG_TWO_FILES) + { + /* open the output header file */ + if (override[HDR_FILE_INDX] == 0) + { + f_header = open(fname_hdr_out,O_RDWR|O_TRUNC|O_CREAT|O_BINARY,0666); + } + else f_header = open(fname_hdr_out,O_RDWR|O_BINARY); + + if (f_header == -1) + { + fprintf(stderr,"Error openning %s file \n",fname_hdr_out); + } + } + + /* Image Header */ + if (header_mode != IMG_ONLY) + { + hdr.blockSize = fs_stat.st_size; + + if (opts & R_OPTION_MASK) + { + hdr.ext = 1; + } + + /* for FLASH\NAND , we have extra word for checksum */ + if ((img == IMG_FLASH)||(img == IMG_NAND)||(img == IMG_SATA)||(img == IMG_PEX)||(img == IMG_I2C)) + { + /*hdr.blockSize++;*/ + hdr.blockSize +=4; + } + + /* in sata headers, blocksize is in sectors (512 byte)*/ + if (img == IMG_SATA) + { + /*hdr.blockSize = (hdr.blockSize + 511) >> 9;*/ + } + + /* Update Block size address */ + if (padding_size) + { + /* Align padding to 32 bit */ + if (padding_size & 0x3) + { + padding_size += (4 - (padding_size & 0x3)); + } + hdr.blockSize += padding_size; + } + + /* Align size to 4 byte*/ + if (hdr.blockSize & 0x3) + { + printf("hdr.blockSize = 0x%x fs_stat.st_size = 0x%x\n", hdr.blockSize, fs_stat.st_size); + bytesToAlign = (4 - (hdr.blockSize & 0x3)); + hdr.blockSize += bytesToAlign; + } + + tmpTwsi = malloc(MAX_TWSI_HDR_SIZE); + memset(tmpTwsi, 0xFF, MAX_TWSI_HDR_SIZE); + + if (opts & M_OPTION_MASK) + { + if (fname_twsi) + { + int i; + unsigned int * twsi_reg = (unsigned int *)tmpTwsi;; + + f_twsi = fopen(fname_twsi, "r"); + if (f_twsi == NULL) + { + fprintf(stderr,"File '%s' not found \n",fname_twsi); + exit(1); + } + + for (i=0; i<(MAX_TWSI_HDR_SIZE/4); i++) + { + if (EOF == fscanf(f_twsi,"%x\n",twsi_reg)) + break; + + /* Swap Enianess */ + *twsi_reg = ( ((*twsi_reg >> 24) & 0xFF) | + ((*twsi_reg >> 8) & 0xFF00) | + ((*twsi_reg << 8) & 0xFF0000) | + ((*twsi_reg << 24) & 0xFF000000) ); + twsi_reg++; + } + + fclose(f_twsi); + + twsi_size = ((((i+2)*4) & ~0x1FF) + 0x200); /*size=512,1024,.. with at least 8 0xFF bytes */ + + if ((write(f_out, tmpTwsi, twsi_size)) != twsi_size) + { + fprintf(stderr,"Error writing %s file \n",fname_out); + goto end; + } + } + } + + tmpHeader = malloc(header_size); + memset(tmpHeader, 0 ,header_size); + + hdr.checkSum = checksum8((void*)&hdr, sizeof(BHR_t) ,0); + memcpy(tmpHeader, &hdr, sizeof(BHR_t)); + + /* Header extension */ + if (opts & R_OPTION_MASK) + { + int dram_buf_size=0,code_buf_size=0; + + /* First we will take of DRAM */ + if (fname_dram) + { + int i; + /*unsigned int dram_reg[DRAM_REGS_NUM];*/ + unsigned int dram_reg[(512>>2)]; + + f_dram = fopen(fname_dram, "r"); + + if (f_dram == NULL) + { + fprintf(stderr,"File '%s' not found \n",fname_dram); + exit(1); + } + + /*for (i=0; i< DRAM_REGS_NUM ; i++)*/ + i=0; + while (EOF != fscanf(f_dram,"%x\n",&dram_reg[i++])); + + fclose(f_dram); + + /*dram_buf_size = DRAM_REGS_NUM * 4;*/ + dram_buf_size = (i-1)*4; + memcpy(tmpHeader + sizeof(BHR_t) + sizeof(ExtBHR_t), + dram_reg, dram_buf_size); + + extHdr.dramRegsOffs = sizeof(BHR_t) + sizeof(ExtBHR_t); + } + + memcpy(tmpHeader + sizeof(BHR_t), &extHdr, sizeof(ExtBHR_t)); + *(MV_U8*)(tmpHeader + header_size - 1) = checksum8((u32)(tmpHeader + sizeof(BHR_t)), header_size - sizeof(BHR_t),0); + + } + + if (header_mode == HDR_IMG_TWO_FILES) + { + /* copy header to output image */ + size_written = write(f_header, tmpHeader, header_size); + if (size_written != header_size) + { + fprintf(stderr,"Error writing %s file \n",fname_hdr_out); + goto end; + } + + fprintf(stdout, "%s was created \n", *f_out_names[HDR_FILE_INDX]); + } + else + { + /* copy header to output image */ + size_written = write(f_out, tmpHeader, header_size); + if (size_written != header_size) + { + fprintf(stderr,"Error writing %s file \n",fname_out); + goto end; + } + } + } + + + if (header_mode != HDR_ONLY) + { + char *padding = NULL; + int new_file_size = 0; + + if (img == IMG_BOOTROM) + { + char *tmp1; + int tmpSize = BOOTROM_SIZE - sizeof(chsum32); + + /* PAD image with Zeros until BOOTROM_SIZE*/ + tmp1 = malloc(tmpSize); + + if (tmp1 == NULL) + goto end; + + memcpy(tmp1, buf_in, fs_stat.st_size); + memset(tmp1 + fs_stat.st_size, 0, tmpSize - fs_stat.st_size); + fs_stat.st_size = tmpSize; + + /* copy input image to output image */ + size_written = write(f_out, tmp1, fs_stat.st_size); + + /* calculate checsum */ + chsum32 = crc32(0, (u32*)tmp1, (fs_stat.st_size/4)); + printf("Image Chacksum (size = %d) = 0x%08x\n", fs_stat.st_size, chsum32); + fs_stat.st_size += sizeof(chsum32) ; + + size_written += write(f_out, &chsum32, sizeof(chsum32)); + + if (tmp1) + free(tmp1); + + new_file_size = fs_stat.st_size; + } + else if (img == IMG_HEX) + { + char *tmp1 = NULL; + + f_hex = fopen(fname_out, "w"); + if (f_hex == NULL) goto end; + + int hex_len = fs_stat.st_size; + int hex_unaligned_len = 0; + + switch (hex_width) + { + case 8: + hex8 = (unsigned char*)buf_in; + do + { + fprintf(f_hex,"%02X\n",*hex8); + hex8++; + size_written += 1; + hex_len--; + + }while(hex_len); + break; + case 16: + hex16 = (unsigned short*)buf_in; + hex_unaligned_len = (fs_stat.st_size & 0x1); + + if (hex_unaligned_len) + { + hex_len -= hex_unaligned_len; + hex_len += 2; + tmp1 = malloc(hex_len); + hex16 = (unsigned short*)tmp1; + memset(tmp1, 0, (hex_len)); + memcpy(tmp1, buf_in, fs_stat.st_size); + } + do + { + fprintf(f_hex,"%04X\n",*hex16++); + size_written += 2; + hex_len -= 2; + + }while(hex_len); + break; + case 32: + hex32 = (long*)buf_in; + hex_unaligned_len = (fs_stat.st_size & 0x3); + if (hex_unaligned_len) + { + hex_len -= hex_unaligned_len; + hex_len += 4; + tmp1 = malloc(hex_len); + hex16 = (unsigned short*)tmp1; + memset(tmp1, 0, (hex_len)); + memcpy(tmp1, buf_in, fs_stat.st_size); + } + do + { + fprintf(f_hex,"%08X\n",*hex32++); + size_written += 4; + hex_len -= 4; + + }while(hex_len); + break; + + case 64: + hex32 = (long*)buf_in; + hex_unaligned_len = (fs_stat.st_size & 0x7); + if (hex_unaligned_len) + { + hex_len -= hex_unaligned_len; + hex_len += 8; + tmp1 = malloc(hex_len); + hex16 = (unsigned short*)tmp1; + memset(tmp1, 0, (hex_len)); + memcpy(tmp1, buf_in, fs_stat.st_size); + } + do + { + fprintf(f_hex,"%08X%08X\n",*hex32++, *hex32++); + size_written += 8; + hex_len -= 8; + + }while(hex_len); + break; + } + size_written = fs_stat.st_size; + if (tmp1) free(tmp1); + fclose(f_hex); + + new_file_size = fs_stat.st_size; + } + else if (img == IMG_BIN) + { + char *tmp1 = NULL; + int one_file_len; + int hex_len = fs_stat.st_size; + + f_hex = fopen(fname_out, "w"); + if (f_hex == NULL) goto end; + f_hex2 = fopen(fname_hdr_out, "w"); + if (f_hex2 == NULL) goto end; + if (fname_romc) + { + f_hex3 = fopen(fname_romc, "w"); + if (f_hex3 == NULL) goto end; + one_file_len = (hex_len / 3); + } + else + { + one_file_len = hex_len * 0.5; + } + int hex_unaligned_len = 0; + + switch (hex_width) + { + case 8: + hex8 = (unsigned char*)buf_in; + do + { + tmp8 = *hex8; + if (hex_len > one_file_len) + { + for (i=0; i> 7)); + tmp8 <<= 1; + } + fprintf(f_hex,"\n"); + } + else + { + for (i=0; i> 7)); + tmp8 <<= 1; + } + fprintf(f_hex2,"\n"); + } + hex8++; + size_written += 1; + hex_len--; + }while(hex_len); + break; + case 16: + hex16 = (unsigned short*)buf_in; + hex_unaligned_len = (fs_stat.st_size & 0x1); + + if (hex_unaligned_len) + { + hex_len -= hex_unaligned_len; + hex_len += 2; + tmp1 = malloc(hex_len); + hex16 = (unsigned short*)tmp1; + memset(tmp1, 0, (hex_len)); + memcpy(tmp1, buf_in, fs_stat.st_size); + } + do + { + tmp16 = *hex16; + for (i=0; i> 15)); + tmp16 <<= 1; + } + fprintf(f_hex,"\n"); + + hex16++; + + size_written += 2; + hex_len -= 2; + + }while(hex_len); + break; + case 32: + hex32 = (long*)buf_in; + hex_unaligned_len = (fs_stat.st_size & 0x3); + if (hex_unaligned_len) + { + hex_len -= hex_unaligned_len; + hex_len += 4; + tmp1 = malloc(hex_len); + hex16 = (unsigned short*)tmp1; + memset(tmp1, 0, (hex_len)); + memcpy(tmp1, buf_in, fs_stat.st_size); + } + do + { + tmp32 = *hex32; + + if (fname_romc) + { + if (hex_len > (2 * one_file_len)) + { + for (i=0; i> 31)); + tmp32 <<= 1; + } + fprintf(f_hex,"\n"); + + } + else if (hex_len > one_file_len) + { + for (i=0; i> 31)); + tmp32 <<= 1; + } + fprintf(f_hex2,"\n"); + } + else + { + for (i=0; i> 31)); + tmp32 <<= 1; + } + fprintf(f_hex3,"\n"); + } + } + else + { + if (hex_len > one_file_len) + { + for (i=0; i> 31)); + tmp32 <<= 1; + } + fprintf(f_hex,"\n"); + } + else + { + for (i=0; i> 31)); + tmp32 <<= 1; + } + fprintf(f_hex2,"\n"); + } + } + hex32++; + size_written += 4; + hex_len -= 4; + + }while(hex_len); + break; + case 64: + fprintf(stderr,"Error: 64 Bit is not supported for binary files\n\n\n\n\n"); + break; + } + size_written = fs_stat.st_size; + if (tmp1) free(tmp1); + fclose(f_hex); + fclose(f_hex2); + + new_file_size = fs_stat.st_size; + } + else + { + + size_written = 0; + + if ((pre_padding)&&(padding_size)) + { + padding = malloc(padding_size); + if (padding) + { + new_file_size += padding_size; + memset((void*)padding, 0x5, padding_size); + size_written += write(f_out, padding, padding_size); + + chsum32 = checksum32(/*(u32)*/ (void*)padding, padding_size, chsum32); + } + + } + + new_file_size += fs_stat.st_size; + + /* Calculate checksum */ + chsum32 = checksum32(/*(u32)*/ (void*)buf_in, (u32)((u32)fs_stat.st_size - bytesToAlign), chsum32); + if (bytesToAlign) + { + memcpy(&lastDword, (buf_in + (fs_stat.st_size - bytesToAlign)) , bytesToAlign); + } + chsum32 = checksum32(/*(u32)*/ (void*)&lastDword, 4,chsum32); + + + /* copy input image to output image */ + size_written += write(f_out, buf_in, fs_stat.st_size); + if (bytesToAlign) + { + size_written += write(f_out, &lastDword, bytesToAlign); + } + + + if ((post_padding)&&(padding_size)) + { + padding = malloc(padding_size); + if (padding) + { + new_file_size += padding_size; + memset((void*)padding, 0xa, padding_size); + size_written += write(f_out, padding, padding_size); + chsum32 = checksum32(/*(u32)*/ (void*)padding, padding_size, chsum32); + } + } + + /* write checksum */ + size_written += write(f_out, &chsum32, sizeof(chsum32)); + new_file_size +=4 ; + } + + + if (size_written != new_file_size) + { + fprintf(stderr,"Error writing %s file \n",fname_out); + goto end; + } + + fprintf(stdout, "%s was created \n", *f_out_names[IMG_FILE_INDX]); + } + + +end: + if (tmpHeader) + free(tmpHeader); + + /* close handles */ + if (f_out != -1) + close(f_out); + if (f_header != -1) + close(f_header); + if (buf_in) + munmap((void*)buf_in, fs_stat.st_size); + if (f_in != -1) + close(f_in); + return 0; +} + + +void print_usage(void) +{ + printf("\n"); + printf("Marvell doimage Tool version %s\n", DOIMAGE_VERSION); + printf("Supported SoC devices: \n"); + printf(" Marvell 88F6082 - A1\n"); + printf(" Marvell 88F6180 - A1\n"); + printf(" Marvell 88F6280 - A1\n"); + printf(" Marvell 88F6192 - A1\n"); + printf(" Marvell 88F6190 - A1\n"); + printf(" Marvell 88F6281 - A1\n"); + printf(" Marvell 88F6282 - A1\n"); + printf("\n"); + printf("usage: \n"); + printf("doimage [other_options] image_in image_out [header_out]\n"); + printf("\n - can be one or more of the following:\n\n"); + printf("-T image_type: sata\\uart\\flash\\bootrom\\nand\\hex\\pex\n"); + printf(" if image_type is sata, the image_out will\n"); + printf(" include header only.\n"); + printf("-D image_dest: image destination in dram (in hex)\n"); + printf("-E image_exec: execution address in dram (in hex)\n"); + printf(" if image_type is 'flash' and image_dest is 0xffffffff\n"); + printf(" then execution address on the flash\n"); + printf("-S image_source: if image_type is sata then the starting sector of\n"); + printf(" the source image on the disk - mandatory for sata\n"); + printf(" if image_type is flash\\nand then the starting offset of\n"); + printf(" the source image at the flash - optional for flash\\nand\n"); + printf("-W hex_width : HEX file width, can be 8,16,32,64 \n"); + printf("-M twsi_file: ascii file name that contains the I2C init regs set by h/w.\n"); + printf(" this is used in i2c boot only\n"); + printf("\n - optional and can be one or more of the following:\n\n"); + printf("-R dram_file: ascii file name that contains the list of dram regs\n"); + printf("-P nand_page_size (decimal 512, 2048, ..): NAND Page size\n"); + printf("-C nand_ecc_mode (1=Hamming, 2=RS, 3=None)\n"); + printf("-L delay in mili seconds before DRAM init\n"); + printf("-I copy image in PIO mode (valid for SATA only)\n"); + printf("-X pre_padding_size (hex)\n"); + printf("-Y post_padding_size (hex)\n"); + printf("-H header_mode: Header mode, can be:\n"); + printf(" -H 1 :will create one file (image_out) for header and image\n"); + printf(" -H 2 :will create two files, (image_out) for image , (header_out) for header\n"); + printf(" -H 3 :will create one file (image_out) for header only \n"); + printf(" -H 4 :will create one file (image_out) for image only \n"); + printf("\ncommand possibilities: \n\n"); + printf("doimage -T hex -W width image_in image_out\n"); + printf("doimage -T bootrom image_in image_out\n"); + printf("doimage -T sata -S sector -D image_dest -E image_exec\n"); + printf(" [other_options] image_in image_out header_out\n\n"); + printf("doimage -T flash -D image_dest -E image_exec [-S address]\n"); + printf(" [other_options] image_in image_out\n\n"); + printf("doimage -T pex -D image_dest -E image_exec \n"); + printf(" [other_options] image_in image_out\n\n"); + printf("doimage -T nand -D image_dest -E image_exec [-S address] -P page_size\n"); + printf(" [other_options] image_in image_out\n\n"); + printf("doimage -T uart -D image_dest -E image_exec\n"); + printf(" [other_options] image_in image_out\n\n"); + printf("doimage -T pex -D image_dest -E image_exec \n"); + printf(" [other_options] image_in image_out\n\n"); + printf("doimage -T i2c -D image_dest -E image_exec -M twsi_init_file\n"); + printf(" [other_options] image_in image_out\n\n"); + printf("\n\n\n"); + +} + + +/* 8 bit checksum */ +u8 checksum8(void* /*u32*/ start, u32 len,u8 csum) +{ + register u8 sum = csum; + volatile u8* startp = (volatile u8*)start; + do{ + sum += *startp; + startp++; + }while(--len); + return (sum); +} + +/* 32 bit checksum */ +u32 checksum32(/*u32*/void* start, u32 len, u32 csum) +{ + register u32 sum = csum; + volatile u32* startp = (volatile u32*)start; + int currLen = len; + + do{ + sum += *(u32*)startp; + startp++; + currLen -= 4; + }while(currLen > 0); + + return (sum); +} + +void make_crc_table(MV_U32 *crc_table) +{ + MV_U32 c; + MV_32 n, k; + MV_U32 poly; + + /* terms of polynomial defining this crc (except x^32): */ + static const MV_U8 p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26}; + + /* make exclusive-or pattern from polynomial (0xedb88320L) */ + poly = 0L; + for (n = 0; n < sizeof(p)/sizeof(MV_U8); n++) + poly |= 1L << (31 - p[n]); + + for (n = 0; n < 256; n++) + { + c = (MV_U32)n; + for (k = 0; k < 8; k++) + c = c & 1 ? poly ^ (c >> 1) : c >> 1; + crc_table[n] = c; + } +} + +#define DO1(buf) crc = crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8); +#define DO2(buf) DO1(buf); DO1(buf); +#define DO4(buf) DO2(buf); DO2(buf); +#define DO8(buf) DO4(buf); DO4(buf); + +MV_U32 crc32(MV_U32 crc, volatile MV_U32 *buf, MV_U32 len) +{ + MV_U32 crc_table[256]; + + /* Create the CRC table */ + make_crc_table(crc_table); + + crc = crc ^ 0xffffffffL; + while (len >= 8) + { + DO8(buf); + len -= 8; + } + + if (len) do + { + DO1(buf); + } while (--len); + + return crc ^ 0xffffffffL; +} diff --git a/tools/environment.c b/tools/environment.c new file mode 120000 index 0000000..c67bdde --- /dev/null +++ b/tools/environment.c @@ -0,0 +1 @@ +../common/environment.c \ No newline at end of file diff --git a/u-boot b/u-boot new file mode 100755 index 0000000..7eae2e3 Binary files /dev/null and b/u-boot differ diff --git a/u-boot-buffalo_mvlsxh_6281 b/u-boot-buffalo_mvlsxh_6281 new file mode 100755 index 0000000..7eae2e3 Binary files /dev/null and b/u-boot-buffalo_mvlsxh_6281 differ diff --git a/u-boot-buffalo_mvlsxh_6281.bin b/u-boot-buffalo_mvlsxh_6281.bin new file mode 100755 index 0000000..577afcd Binary files /dev/null and b/u-boot-buffalo_mvlsxh_6281.bin differ diff --git a/u-boot-buffalo_mvlsxh_6281.srec b/u-boot-buffalo_mvlsxh_6281.srec new file mode 100755 index 0000000..d078ba0 --- /dev/null +++ b/u-boot-buffalo_mvlsxh_6281.srec @@ -0,0 +1,25092 @@ +S00E0000752D626F6F742E73726563C0 +S214600000120000EA14F09FE514F09FE514F09FE5F7 +S21460001014F09FE514F09FE514F09FE514F09FE55B +S214600020A00160000002600060026000C002600024 +S2146000302003600080036000E0036000EFBEADDE7A +S2146000400000600000006000F0FF660080CF6B007C +S21460005000000FE11F00C0E3D30080E300F029E159 +S214600060170000EB6C004FE230101FE5010050E116 +S2146000700700000A38201FE538301FE5022043E0FD +S214600080022080E0F807B0E8F807A1E8020050E137 +S214600090FBFFFFDA5C001FE5800040E210D040E224 +S2146000A060001FE560101FE50020A0E3002080E5EB +S2146000B0040080E2010050E1FBFFFFDA04F01FE578 +S2146000C058266200100F10EE2002A0E16C139FE528 +S2146000D0010000E068139FE5010050E10300000A9C +S2146000E00000A0E3170F07EE170F08EE020000EA05 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100644 index 0000000..fb0acc8 Binary files /dev/null and b/u-boot-buffalo_mvlsxh_6281_400mvlsxh_flash.bin differ diff --git a/u-boot-buffalo_mvlsxh_6281_400mvlsxh_uart.bin b/u-boot-buffalo_mvlsxh_6281_400mvlsxh_uart.bin new file mode 100644 index 0000000..bfc65a0 Binary files /dev/null and b/u-boot-buffalo_mvlsxh_6281_400mvlsxh_uart.bin differ diff --git a/u-boot.bin b/u-boot.bin new file mode 100755 index 0000000..577afcd Binary files /dev/null and b/u-boot.bin differ diff --git a/u-boot.map b/u-boot.map new file mode 100644 index 0000000..d7d010a --- /dev/null +++ b/u-boot.map @@ -0,0 +1,4624 @@ +Archive member included because of file (symbol) + +board/mv_feroceon/config_kw/libconfig_kw.a(platform.o) + cpu/arm926ejs/start.o (lowlevel_init) +board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsiEeprom.o) + board/mv_feroceon/config_kw/libconfig_kw.a(platform.o) (_i2cInit) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) + (__u_boot_cmd_bubt) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) (recoveryHandle) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_service.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (mvBoardEgigaPhySwitchInit) +board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (mvCtrlPwrClckSet) +board/mv_feroceon/config_kw/libconfig_kw.a(mvAhbToMbus.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) (mvAhbToMbusAddDecShow) +board/mv_feroceon/config_kw/libconfig_kw.a(mvCpuIf.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) (mvCpuIfAddDecShow) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSysXor.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) (mvXorAddrDecShow) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSysDram.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCpuIf.o) (mvDramIfWinGet) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSysGbe.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) (mvEthAddrDecShow) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSysAudio.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) (mvAudioAddrDecShow) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSysTs.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) (mvTsuAddrDecShow) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSysPex.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) (mvPexAddrDecShow) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSysSata.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) (mvSataAddrDecShow) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSysUsb.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) (mvUsbAddrDecShow) +board/mv_feroceon/config_kw/libconfig_kw.a(mvCpu.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (mvCpuNameGet) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSysLCD.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) (mvLcdAddrDecShow) +board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvLib.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (mvBoardTclkGet) +board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvSpec.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvLib.o) (boardInfoTbl) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_flash.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (getMvFlashInfo) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_pageTable.o) + (__u_boot_cmd_cpumap) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_rtc.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (rtc_get) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_mon_init.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_pageTable.o) (PTexist) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (ide_get_dev) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_protectionUnit.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_pageTable.o) (mpuMap) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_ext2_boot.o) + (__u_boot_cmd_bootext2) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSwitch.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) (mvEthSwitchRegRead) +board/mv_feroceon/config_kw/libconfig_kw.a(mvCommon.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvAhbToMbus.o) (mvSizePrint) +board/mv_feroceon/config_kw/libconfig_kw.a(mvOs.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvCpu.o) (mvOsCpuPartGet) +board/mv_feroceon/config_kw/libconfig_kw.a(mvFlashCom.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_flash.o) (mvFlashSecLockGet) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSata.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) (mvSataUnmaskAdapterInterrupt) +board/mv_feroceon/config_kw/libconfig_kw.a(mvStorageDev.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) (mvStorageDevSetDeviceType) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSFlash.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_flash.o) (mvSFlashSizeGet) +board/mv_feroceon/config_kw/libconfig_kw.a(mvEthPhy.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) (mvEthPhyRegRead) +board/mv_feroceon/config_kw/libconfig_kw.a(mvRtc.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_rtc.o) (mvRtcTimeSet) +board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsi.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (mvTwsiInit) +board/mv_feroceon/config_kw/libconfig_kw.a(mvGpp.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvLib.o) (mvGppValueGet) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSpi.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvSFlash.o) (mvSpiBaudRateSet) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSpiCmnd.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvSFlash.o) (mvSpiWriteThenRead) +board/mv_feroceon/config_kw/libconfig_kw.a(mvUsb.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvSysUsb.o) (mvUsbHalInit) +board/mv_feroceon/config_kw/libconfig_kw.a(mvXor.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvSysXor.o) (mvXorHalInit) +board/mv_feroceon/config_kw/libconfig_kw.a(mvEth.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvSysGbe.o) (mvEthHalInit) +board/mv_feroceon/config_kw/libconfig_kw.a(mvPex.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) (mvPexPhyRegWrite) +board/mv_feroceon/config_kw/libconfig_kw.a(mvAudio.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvSysAudio.o) (mvAudioHalInit) +board/mv_feroceon/config_kw/libconfig_kw.a(mvTsu.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvSysTs.o) (mvTsuHalInit) +board/mv_feroceon/config_kw/libconfig_kw.a(mvLcd.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvSysLCD.o) (mvLcdHalInit) +board/mv_feroceon/config_kw/libconfig_kw.a(BuffaloWol.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (bfIsSupportWol) +board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvAddrDec.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvAhbToMbus.o) (mvCtrlRegToAddrDec) +board/mv_feroceon/config_kw/libconfig_kw.a(mvOsSata.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvSata.o) (mvSwapShort) +cpu/arm926ejs/libarm926ejs.a(interrupts.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) (udelay) +cpu/arm926ejs/libarm926ejs.a(cpu.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) (do_reset) +lib_arm/libarm.a(board.o) cpu/arm926ejs/start.o (start_armboot) +lib_arm/libarm.a(cache.o) board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) (flush_cache) +fs/ext2/libext2fs.a(ext2fs.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (ext2fs_close) +fs/ext2/libext2fs.a(dev.o) board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (ext2fs_devread) +net/libnet.a(net.o) board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) (copy_filename) +net/libnet.a(tftp.o) net/libnet.a(net.o) (TftpStart) +net/libnet.a(bootp.o) net/libnet.a(net.o) (BootpRequest) +net/libnet.a(rarp.o) net/libnet.a(net.o) (RarpRequest) +net/libnet.a(eth.o) net/libnet.a(net.o) (eth_get_dev) +net/libnet.a(rcvr.o) net/libnet.a(net.o) (RecoverRequest) +disk/libdisk.a(part.o) board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) (print_part) +disk/libdisk.a(part_dos.o) disk/libdisk.a(part.o) (test_part_dos) +disk/libdisk.a(part_efi.o) disk/libdisk.a(part.o) (test_part_efi) +drivers/libdrivers.a(cfi_flash.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (flash_add_base_addr) +common/libcommon.a(main.o) board/mv_feroceon/config_kw/libconfig_kw.a(mv_ext2_boot.o) (run_command) +common/libcommon.a(cmd_boot.o) + (__u_boot_cmd_go) +common/libcommon.a(cmd_bootm.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) (print_image_hdr) +common/libcommon.a(cmd_date.o) + (__u_boot_cmd_date) +common/libcommon.a(cmd_ext2.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (do_ext2load) +common/libcommon.a(cmd_fat.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (do_fat_fsload) +common/libcommon.a(cmd_flash.o) + (__u_boot_cmd_flinfo) +common/libcommon.a(cmd_jffs2.o) + common/libcommon.a(cmd_flash.o) (id_parse) +common/libcommon.a(cmd_mem.o) + (__u_boot_cmd_md) +common/libcommon.a(cmd_mmc.o) + (__u_boot_cmd_mmcinit) +common/libcommon.a(cmd_net.o) + (__u_boot_cmd_bootp) +common/libcommon.a(cmd_nvedit.o) + lib_arm/libarm.a(board.o) (getenv_r) +common/libcommon.a(cmd_usb.o) + (__u_boot_cmd_usb) +common/libcommon.a(command.o) + common/libcommon.a(main.o) (find_cmd) +common/libcommon.a(console.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) (printf) +common/libcommon.a(devices.o) + lib_arm/libarm.a(board.o) (devices_init) +common/libcommon.a(dlmalloc.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvOs.o) (free) +common/libcommon.a(env_common.o) + common/libcommon.a(cmd_nvedit.o) (env_get_addr) +common/libcommon.a(env_flash.o) + common/libcommon.a(env_common.o) (env_get_char_spec) +common/libcommon.a(exports.o) + lib_arm/libarm.a(board.o) (jumptable_init) +common/libcommon.a(flash.o) common/libcommon.a(cmd_mem.o) (addr2info) +common/libcommon.a(hush.o) common/libcommon.a(main.o) (u_boot_hush_start) +common/libcommon.a(lists.o) common/libcommon.a(console.o) (ListGetPtrToItem) +common/libcommon.a(usb.o) common/libcommon.a(cmd_usb.o) (usb_get_dev_index) +common/libcommon.a(usb_storage.o) + common/libcommon.a(cmd_ext2.o) (usb_stor_get_dev) +lib_generic/libgeneric.a(crc32.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (crc32) +lib_generic/libgeneric.a(ctype.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (_ctype) +lib_generic/libgeneric.a(display_options.o) + lib_arm/libarm.a(board.o) (print_size) +lib_generic/libgeneric.a(string.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) (strcpy) +lib_generic/libgeneric.a(vsprintf.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) (simple_strtoul) +lib_generic/libgeneric.a(zlib.o) + common/libcommon.a(cmd_bootm.o) (inflateEnd) +board/mv_feroceon/config_kw/libconfig_kw.a(mvCntmr.o) + cpu/arm926ejs/libarm926ejs.a(interrupts.o) (mvCntmrStart) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_dram.o) + lib_arm/libarm.a(board.o) (dram_init) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_serial.o) + common/libcommon.a(cmd_nvedit.o) (serial_setbrg) +board/mv_feroceon/config_kw/libconfig_kw.a(mv_egiga.o) + net/libnet.a(eth.o) (mv_eth_initialize) +board/mv_feroceon/config_kw/libconfig_kw.a(mmc.o) + common/libcommon.a(cmd_ext2.o) (mmc_get_dev) +board/mv_feroceon/config_kw/libconfig_kw.a(mvDramIf.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_dram.o) (mvDramIfBankSizeGet) +board/mv_feroceon/config_kw/libconfig_kw.a(mvUart.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_serial.o) (mvUartInit) +board/mv_feroceon/config_kw/libconfig_kw.a(mvSpd.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mvDramIf.o) (dimmSpdGet) +lib_arm/libarm.a(armlinux.o) common/libcommon.a(cmd_bootm.o) (do_bootm_linux) +fs/cramfs/libcramfs.a(cramfs.o) + common/libcommon.a(cmd_jffs2.o) (cramfs_check) +fs/cramfs/libcramfs.a(uncompress.o) + fs/cramfs/libcramfs.a(cramfs.o) (cramfs_uncompress_exit) +fs/fat/libfat.a(fat.o) common/libcommon.a(cmd_fat.o) (file_fat_detectfs) +fs/jffs2/libjffs2.a(jffs2_1pass.o) + fs/cramfs/libcramfs.a(cramfs.o) (mkmodestr) +fs/jffs2/libjffs2.a(compr_rtime.o) + fs/jffs2/libjffs2.a(jffs2_1pass.o) (rtime_decompress) +fs/jffs2/libjffs2.a(compr_rubin.o) + fs/jffs2/libjffs2.a(jffs2_1pass.o) (dynrubin_decompress) +fs/jffs2/libjffs2.a(compr_zlib.o) + fs/jffs2/libjffs2.a(jffs2_1pass.o) (zlib_decompress) +fs/jffs2/libjffs2.a(mini_inflate.o) + fs/jffs2/libjffs2.a(compr_zlib.o) (decompress_block) +rtc/librtc.a(date.o) common/libcommon.a(cmd_date.o) (GregorianDay) +drivers/usb/libusb.a(usb_ehci.o) + common/libcommon.a(usb.o) (usb_lowlevel_stop) +/opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_udivsi3.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) (__aeabi_uidiv) +/opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_divsi3.o) + board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) (__aeabi_idiv) +/opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_dvmd_lnx.o) + /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_udivsi3.o) (__div0) + +Discarded input sections + + .stabstr 0x00000000 0x0 cpu/arm926ejs/start.o + .stabstr 0x00000000 0x0 board/mv_feroceon/USP/jump.o + .stabstr 0x00000000 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(platform.o) + .stabstr 0x00000000 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsiEeprom.o) + +Memory Configuration + +Name Origin Length Attributes +*default* 0x00000000 0xffffffff + +Linker script and memory map + + 0x00600000 . = _start + +.text 0x00600000 0x468ec + cpu/arm926ejs/start.o(.text) + .text 0x00600000 0x460 cpu/arm926ejs/start.o + 0x00600140 _dcache_index_max + 0x00600144 _dcache_index_inc + 0x0060014c _dcache_set_index + 0x00600048 _bss_start + 0x0060004c _bss_end + 0x00600044 _armboot_start + 0x00600000 _start + 0x00600150 cpu_dcache_flush_all + 0x0060018c cpu_icache_flush_invalidate_all + 0x00600040 _TEXT_BASE + 0x00600148 _dcache_set_max + *(.text) + .text 0x00600460 0x0 board/mv_feroceon/USP/jump.o + .text 0x00600460 0x68 board/mv_feroceon/config_kw/libconfig_kw.a(platform.o) + 0x00600460 lowlevel_init + .text 0x006004c8 0x304 board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsiEeprom.o) + 0x006004c8 _i2cInit + 0x00600510 _i2cRead + .text 0x006007cc 0x1534 board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) + 0x006010cc phy_write_cmd + 0x006011e0 pcie_phy_read_cmd + 0x00601380 fi_cmd + 0x00600b50 do_rcvr + 0x00600b68 do_satr + 0x00601660 clk_cmd + 0x00601058 switch_read_cmd + 0x0060154c g_cmd + 0x00600878 bfGetWolStatus + 0x006016bc resetenv_cmd + 0x00600fe0 switch_write_cmd + 0x00601770 nor_burn_uboot_cmd + 0x00601128 phy_read_cmd + 0x0060123c cmpm_cmd + 0x00601608 sg_cmd + 0x006014dc mv_go + 0x006015f0 displayMemoryMap_cmd + 0x00601b00 ir_cmd + 0x006009d8 bfTestWol + 0x00601184 pcie_phy_write_cmd + .text 0x00601d00 0x2a38 board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) + 0x00603d70 print_dev_id + 0x00602054 bfIsStartBootProcess + 0x00603e28 isMyDisk + 0x00603cec misc_init_r_dec_win + 0x00602244 bfEthPhyPolaritySet + 0x00602684 recoveryHandle + 0x00603dac print_mvBanner + 0x00602d1c recoveryCheck + 0x006030e0 mvGetRtcSec + 0x0060312c mvTclkGet + 0x00603150 misc_init_r_env + 0x00601d94 pcie_tune + 0x006022d4 mv_cpu_init + 0x00602db8 mv_set_power_scheme + 0x006030dc reset_cpu + 0x00603c48 board_init + 0x00601ec4 bfErrorCodeDisp + 0x00604424 board_late_init + 0x00602030 bfDispAllInitrdError + 0x00602f8c mvMppModuleTypePrint + 0x00601dd4 bfAllLedOff + 0x00601d6c maskAllInt + 0x00602d34 mvUpdateNorFlashBaseAddrBank + 0x00603f88 serch_boot_drv + 0x00602290 memcpyFlash + 0x006045ec misc_init_r + 0x00601d08 isValidMacAddr + 0x00603108 mvSysClkGet + 0x00601d00 raise + .text 0x00604738 0xd8 board/mv_feroceon/config_kw/libconfig_kw.a(mv_service.o) + 0x00604738 mvBoardEgigaPhySwitchInit + .text 0x00604810 0x1334 board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) + 0x00604960 mvCtrlTargetNameGet + 0x00604da0 mvCtrlModelGet + 0x00605100 mvCtrlEthMaxPortGet + 0x00605364 mvCtrlAddrDecShow + 0x00604f4c mvCtrlIsBootFromSPI + 0x00605014 mvCtrlAudioSupport + 0x00604fd0 mvCtrlTdmSupport + 0x00604810 mvCtrlMppRegGet + 0x006053fc mvCtrlModelRevNameGet + 0x00604898 ctrlWinOverlapTest + 0x00605738 mvCtrlEnvInit + 0x00604888 mvCtrlXorMaxChanGet + 0x006049d4 ctrlRegToSize + 0x00605600 mvCtrlPwrMemGet + 0x00604890 mvCtrlUsbMaxGet + 0x006056dc mvCtrlSysRstLengthCounterGet + 0x00604ef0 mvCtrlIsBootFromSPIUseNAND + 0x00604904 ctrlWinWithinWinTest + 0x00605578 mvMPPConfigToDefault + 0x00604ab0 mvCtrlPwrSaveOff + 0x00604e84 mvCtrlIsBootFromNAND + 0x00604a34 ctrlSizeRegRoundUp + 0x006051b4 mvCtrlPwrMemSet + 0x00604fb8 mvCtrlModelRevGet + 0x006050ac mvCtrlNandSupport + 0x0060497c ctrlSizeToReg + 0x006055c4 mvMPPConfigToSPI + 0x006053b8 mvCtrlNameGet + 0x00604d44 mvCtrlRevGet + 0x00605068 mvCtrlTsSupport + 0x0060517c mvCtrlPexMaxIfGet + 0x00604c7c mvCtrlPwrClckGet + 0x00604a84 mvCtrlPwrSaveOn + 0x00604adc mvCtrlPwrClckSet + .text 0x00605b44 0x820 board/mv_feroceon/config_kw/libconfig_kw.a(mvAhbToMbus.o) + 0x00605ee8 mvAhbToMbusWinTargetGet + 0x00605b44 mvAhbToMbusInit + 0x00606138 mvAhbToMbusWinTargetSwap + 0x00606098 mvAhbToMbusWinRemap + 0x00605c28 mvAhbToMbusWinNum + 0x00605f68 mvAhbToMbusWinSet + 0x00605cc4 mvAhbToMbusWinGet + 0x00605dbc mvAhbToMbusAddDecShow + 0x00605c50 mvAhbToMbusWinEnable + 0x00605e8c mvAhbToMbusWinAvailGet + .text 0x00606364 0xb14 board/mv_feroceon/config_kw/libconfig_kw.a(mvCpuIf.o) + 0x00606364 mvCpuIfEnablePex + 0x00606730 mvCpuIfTargetOfBaseAddressGet + 0x006068cc mvCpuIfTargetWinSet + 0x00606b84 mvCpuIfTargetWinSizeGet + 0x0060679c mvCpuIfTargetWinEnable + 0x00606a1c mvCpuIfTargetWinBaseHighGet + 0x00606ad0 mvCpuIfTargetWinBaseLowGet + 0x006063e8 mvCpuIfPexRemap + 0x00606468 mvCpuIfTargetWinGet + 0x00606450 mvCpuIfPciIfRemap + 0x006065d0 mvCpuIfAddDecShow + 0x00606c38 mvCpuIfInit + .text 0x00606e78 0x740 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysXor.o) + 0x00606e78 mvXorProtWinSet + 0x00606f64 mvXorTargetWinGet + 0x00607094 mvXorAddrDecShow + 0x006074b8 mvXorInit + 0x00607224 mvXorTargetWinEnable + 0x00607324 mvXorTargetWinSet + 0x00606f1c mvXorPciRemap + .text 0x006075b8 0x238 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysDram.o) + 0x006075b8 mvDramIfWinGet + 0x0060773c mvDramIfWinSet + 0x006076ac mvDramIfWinEnable + .text 0x006077f0 0x6e0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysGbe.o) + 0x00607960 mvEthPortAddrDecShow + 0x00607a70 mvEthWinTargetGet + 0x00607b74 mvEthWinEnable + 0x006077f0 mvEthProtWinSet + 0x00607c2c mvEthWinInit + 0x00607e88 mvEthInit + 0x00607a34 mvEthAddrDecShow + .text 0x00607ed0 0x304 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysAudio.o) + 0x00608124 mvAudioInit + 0x00607ed0 mvAudioWinGet + 0x00607f78 mvAudioAddrDecShow + 0x00608054 mvAudioWinSet + .text 0x006081d4 0x4cc board/mv_feroceon/config_kw/libconfig_kw.a(mvSysTs.o) + 0x00608670 mvTsuInit + 0x00608274 mvTsuAddrDecShow + 0x00608438 mvTsuWinEnable + 0x006084c8 mvTsuWinInit + 0x00608350 mvTsuWinTargetGet + .text 0x006086a0 0xf18 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysPex.o) + 0x00608d30 mvPexTargetWinGet + 0x00608bf4 mvPexBarEnable + 0x006087f8 mvPexTargetWinRemapEnable + 0x00609108 mvPexInit + 0x00609350 mvPexAddrDecShow + 0x00608e90 mvPexTargetWinEnable + 0x00608918 mvPexBarGet + 0x006087b8 pexBarNameGet + 0x0060886c mvPexTargetWinRemap + 0x00608a70 mvPexBarSet + 0x00608f90 mvPexTargetWinSet + .text 0x006095b8 0x3b4 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysSata.o) + 0x0060965c mvSataAddrDecShow + 0x00609754 mvSataWinSet + 0x006095b8 mvSataWinGet + 0x00609880 mvSataWinInit + .text 0x0060996c 0x3b8 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysUsb.o) + 0x00609aec mvUsbWinSet + 0x00609a00 mvUsbAddrDecShow + 0x00609bf8 mvUsbWinInit + 0x00609cec mvUsbInit + 0x0060996c mvUsbWinGet + .text 0x00609d24 0x3a8 board/mv_feroceon/config_kw/libconfig_kw.a(mvCpu.o) + 0x00609d24 whoAmI + 0x00609d2c mvCpuIfPrintSystemConfig + 0x00609f30 mvCpuPclkGet + 0x00609e74 mvCpuNameGet + 0x00609ffc mvCpuL2ClkGet + .text 0x0060a0cc 0x498 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysLCD.o) + 0x0060a478 mvLcdInit + 0x0060a308 mvLcdTargetWinEnable + 0x0060a1b0 mvLcdAddrDecShow + 0x0060a0f0 mvLcdTargetWinGet + 0x0060a394 mvLcdTargetWinSet + 0x0060a0cc mvLcdPciRemap + .text 0x0060a564 0x17dc board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvLib.o) + 0x0060af2c mvBoardMppMuxSet + 0x0060a628 mvBoardIdGet + 0x0060a9f8 mvBoardTwsiExpAddrTypeGet + 0x0060ad60 mvBoardNandWidthGet + 0x0060b2ac mvBoardUSBVbusGpioPinGet + 0x0060abf4 mvBoardRtcTwsiAddrTypeGet + 0x0060ae18 mvBoardTdmSpiModeGet + 0x0060ae38 mvBoardMppGroupTypeSet + 0x0060a598 mvBoardSpecInitGet + 0x0060bc40 mvBoardSysClkGet + 0x0060ae84 mvBoardMppGroupTypeGet + 0x0060b338 mvBoardRTCGpioPinGet + 0x0060bb60 mvBoardEnvInit + 0x0060aa64 mvBoarModuleTypeGet + 0x0060ba64 mvBoardDebugLed + 0x0060a5b4 mvBoardDebugLedNumGet + 0x0060a5a0 mvBoardPexBridgeIntPinGet + 0x0060a784 mvBoardSlicGpioPinGet + 0x0060bb08 mvBoardNameGet + 0x0060a5cc mvBoardTclkGet + 0x0060b0b8 mvBoardIsPortInGmii + 0x0060acc0 boardGetDevCSNum + 0x0060a808 mvBoardTwsiSatRAddrTypeGet + 0x0060b2c4 mvBoardResetGpioPinGet + 0x0060ab44 mvBoardA2DTwsiAddrTypeGet + 0x0060b508 mvBoardRevGet + 0x0060ad20 mvBoardGetDeviceWidth + 0x0060aed0 mvBoardMppModuleTypePrint + 0x0060b37c mvBoardIsSwitchConnected + 0x0060b46c mvBoardLinkStatusIrqGet + 0x0060b344 mvBoardSmiScanModeGet + 0x0060b2a0 mvBoardUSBVbusEnGpioPinGet + 0x0060aaec mvBoardA2DTwsiAddrGet + 0x0060b1a0 mvBoardGpioIntMaskLowGet + 0x0060ad00 mvBoardGetDeviceBusWidth + 0x0060a900 mvBoarTwsiSatRGet + 0x0060b0f4 mvBoardMppVoltageLevelGet + 0x0060b524 mvBoardModelGet + 0x0060b170 mvBoardGpioIntMaskHighGet + 0x0060b414 mvBoardSwitchPortGet + 0x0060b140 mvBoardMppGet + 0x0060b53c mvBoardGetDeviceWinSize + 0x0060a564 mvBoardIsPortInSgmii + 0x0060b5c0 mvBoardTdmMppSet + 0x0060b4a4 mvBoardMacSpeedGet + 0x0060ab9c mvBoardRtcTwsiAddrGet + 0x0060a98c mvBoardTwsiExpAddrGet + 0x0060b3dc mvBoardSwitchCpuPortGet + 0x0060b24c bfIsPWR_or_PWRAUTO_SignalAsserted + 0x0060a79c mvBoardTwsiSatRAddrGet + 0x0060b58c mvBoardGetDeviceBaseAddr + 0x0060b1d0 mvBoardGpioPinNumGet + 0x0060b4d4 mvBoardPhyAddrGet + 0x0060a874 mvBoarTwsiSatRSet + 0x0060b2d0 mvBoardReset + 0x0060adb8 mvBoardGetDevicesNumber + 0x0060b880 mvBoardMppGroupIdUpdate + 0x0060b2b8 mvBoardSDIOGpioPinGet + .text 0x0060bd40 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvSpec.o) + .text 0x0060bd40 0xd38 board/mv_feroceon/config_kw/libconfig_kw.a(mv_flash.o) + 0x0060c56c sflashInfoCopy + 0x0060bf68 sflash_print_info + 0x0060c0b8 sflash_cmd + 0x0060bec0 mv_write_buff + 0x0060c860 flashMvInfoCopy + 0x0060c744 mvFlash_init + 0x0060be68 mv_flash_real_protect + 0x0060c630 sflash_init + 0x0060bd40 getMvFlashInfo + 0x0060bd84 getMvFlashInfoNum + 0x0060bddc mv_flash_real_protect_bank + 0x0060c658 mv_flash_erase + 0x0060c510 mv_flash_print_info + 0x0060bf24 sflash_erase + 0x0060c988 flashInfoCopy + .text 0x0060ca78 0x67c board/mv_feroceon/config_kw/libconfig_kw.a(mv_pageTable.o) + 0x0060cb10 cpuCfgEnable + 0x0060cb38 disableIDCache + 0x0060ce4c pageTableInit + 0x0060ca88 mmuInvCache + 0x0060ca80 mmuSetDomainAccessControl + 0x0060cacc mmuFlushTLB + 0x0060cb54 getDCacheAssociativity + 0x0060cc04 cpumap_cmd + 0x0060cbe8 getDCacheLine + 0x0060ca78 mmuSetPageTabBase + 0x0060cbb8 getDCacheSize + .text 0x0060d0f4 0xe4 board/mv_feroceon/config_kw/libconfig_kw.a(mv_rtc.o) + 0x0060d0f8 rtc_set + 0x0060d0f4 rtc_reset + 0x0060d174 rtc_get + .text 0x0060d1d8 0x12c board/mv_feroceon/config_kw/libconfig_kw.a(mv_mon_init.o) + 0x0060d1d8 PTexist + 0x0060d228 mon_extension_after_relloc + .text 0x0060d304 0x1c4c board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) + 0x0060d324 mvGetSataDeviceType + 0x0060d5b0 ide_read_write + 0x0060dc3c ide_read + 0x0060e770 do_diskboot + 0x0060d394 InitChannel + 0x0060d474 mvSataEventNotify + 0x0060ea8c do_ide + 0x0060d3e4 ide_get_dev + 0x0060dc68 mvGetPMDeviceInfo + 0x0060dd78 ide_init + 0x0060dc10 ide_write + .text 0x0060ef50 0x9a4 board/mv_feroceon/config_kw/libconfig_kw.a(mv_protectionUnit.o) + 0x0060ef50 get_control + 0x0060f3c0 MPU_Init + 0x0060ef60 get_prot_attrib + 0x0060f0f8 mpuInvCache + 0x0060f180 mpuMap + 0x0060f164 _disableIDCache + 0x0060ef58 set_control + 0x0060f13c _cpuCfgEnable + .text 0x0060f8f4 0x38c board/mv_feroceon/config_kw/libconfig_kw.a(mv_ext2_boot.o) + 0x0060f8f4 do_bootext2 + .text 0x0060fc80 0x6ac board/mv_feroceon/config_kw/libconfig_kw.a(mvSwitch.o) + 0x00610074 mvEthE6063SwitchBasicInit + 0x0061009c mvEthE6065_61SwitchBasicInit + 0x006100c4 mvEthE6161SwitchBasicInit + 0x00610260 mvEthE6131SwitchBasicInit + 0x0060fc80 mvEthSwitchRegRead + 0x0060fd34 mvEthSwitchRegWrite + .text 0x0061032c 0x2e0 board/mv_feroceon/config_kw/libconfig_kw.a(mvCommon.o) + 0x00610358 mvBinToAscii + 0x0061032c mvLog2 + 0x006104ec mvMacStrToHex + 0x006103f0 mvAsciiToHex + 0x0061054c mvSizePrint + 0x0061043c mvMacHexToStr + 0x006103a4 mvBinToHex + 0x00610488 mvHexToBin + .text 0x0061060c 0xf8 board/mv_feroceon/config_kw/libconfig_kw.a(mvOs.o) + 0x0061060c mvOsCpuPartGet + 0x00610624 mvOsIoVirtToPhy + 0x006106b4 mvOsIoUncachedMalloc + 0x006106cc mvOsCpuRevGet + 0x006106d8 mvOsCpuAsciiGet + 0x00610644 mvOsStrCmp + 0x006106e4 mvOsCpuVarGet + 0x0061068c mvOsIoCachedFree + 0x00610634 mvOsCacheInvalidate + 0x0061069c mvOsIoCachedMalloc + 0x00610694 mvOsIoUncachedFree + 0x0061063c mvOsRand + 0x0061062c mvOsCacheFlush + 0x006106f4 mvOsCpuArchGet + .text 0x00610704 0x7c4 board/mv_feroceon/config_kw/libconfig_kw.a(mvFlashCom.o) + 0x00610874 flashAddrExt + 0x006107fc mvFlashVenIdGet + 0x00610814 mvFlashBaseAddrGet + 0x00610a18 flashPrint + 0x00610820 mvFlashBusWidthGet + 0x0061076c mvFlashSecSizeGet + 0x00610798 mvFlashNumOfSecsGet + 0x00610704 mvFlashNumOfDevGet + 0x0061082c mvFlashDevWidthGet + 0x006108f4 flashBusWidthWr + 0x006109b0 mvFlashInWhichSec + 0x006107a4 mvFlashSizeGet + 0x00610740 mvFlashSecLockGet + 0x0061097c flashBusWidthDataWr + 0x00610808 mvFlashDevIdGet + 0x006107f0 mvFlashSecTypeGet + 0x00610734 mvFlashIsHwLock + 0x006108bc flashBusWidthRd + 0x00610838 flashDataExt + 0x006107c4 mvFlashSecOffsGet + 0x00610928 flashCmdSet + .text 0x00610ec8 0x551c board/mv_feroceon/config_kw/libconfig_kw.a(mvSata.o) + 0x00614e28 mvSataChannelFarLoopbackDiagnostic + 0x00611c08 mvSataSetIntCoalParams + 0x00613584 mvSataChannelPhyPowerOn + 0x00614940 mvSataConfigureChannel + 0x00612b9c mvSata60X1B2CheckDevError + 0x006118a8 mvSataGetInterfaceSpeed + 0x006117fc mvSataSetInterruptsScheme + 0x00616370 mvSataGetInterfacePowerState + 0x006116bc mvSataShutdownAdapter + 0x006136c0 mvSataInitAdapter + 0x006150f4 mvSataInterruptServiceRoutine + 0x006119e8 mvSataCheckPendingInterrupt + 0x0061450c mvSataEnableStaggeredSpinUp + 0x006146e8 mvSataChannelHardReset + 0x00614acc mvSataDisableChannelDma + 0x00611a1c mvSataChannelPhyShutdown + 0x006121a4 _setActivePMPort + 0x006120d4 disableSaDevInterrupts + 0x00611834 mvSataUnmaskAdapterInterrupt + 0x00615eac mvSataQueueCommand + 0x00611aec mvSataSetChannelPhyParams + 0x006116f4 mvSataRemoveChannel + 0x0061191c mvSataDisableStaggeredSpinUp + 0x006143d8 mvSataSetInterfaceSpeed + 0x00611810 mvSataMaskAdapterInterrupt + 0x006125ac mvSataEnableChannelDma + 0x0061457c mvSataEnableStaggeredSpinUpAll + 0x0061185c mvSataIfD2HReceived + 0x006116e4 mvSataWriteReg + 0x00611724 mvSataSetFBSMode + 0x006126f0 mvSataIsStorageDeviceConnected + 0x00614dbc waitForBusyAfterHReset + 0x00611790 mvSataNumOfDmaCommands + 0x00616074 mvSataConfigEdmaMode + 0x006117b4 mvSataGetNumOfPortQueuedCommands + 0x006125f0 mvSataSetInterfacePowerState + 0x006148ec mvSataFlushDmaQueue + 0x00611994 mvSataDisableStaggeredSpinUpAll + 0x00611dd8 mvSataReadReg + .text 0x006163e4 0x116c board/mv_feroceon/config_kw/libconfig_kw.a(mvStorageDev.o) + 0x00616958 mvStorageDevATASoftResetDevice + 0x00617430 mvStorageDevATASetFeatures + 0x00617488 mvStorageDevATAIdentifyDevice + 0x006169d4 executeNonUDMACommand + 0x00616ef4 _PMAccessReg + 0x00616468 mvStorageDevSetDeviceType + 0x00616690 mvStorageDevATAIdleImmediate + 0x006171c8 mvPMDevEnableStaggeredSpinUpPort + 0x00616e3c mvStorageDevExecutePIO + 0x006165e8 waitForDRQ + 0x00616810 mvStorageIsDeviceBsyBitOff + 0x00616414 disableStorageDevInterrupt + 0x00617090 mvPMLinkUp + 0x006165a8 _startSoftResetDevice + 0x00616730 dumpAtaDeviceRegisters + 0x0061690c mvStorageDevATAStartSoftResetDevice + 0x006164b8 _doSoftReset + 0x0061710c mvPMDevReadReg + 0x00616554 waitForDRQToClear + 0x00617254 mvPMDevEnableStaggeredSpinUpAll + 0x00616870 waitWhileStorageDevIsBusy_88SX60X1 + 0x00616444 _isDeviceBsyBitOff + 0x006163e4 enableStorageDevInterrupt + 0x00617398 mvStorageDevATAExecuteNonUDMACommand + 0x0061702c mvPMDevWriteReg + 0x0061663c waitWhileStorageDevIsBusy + 0x00617104 mvPMDevEnableStaggeredSpinUp + 0x00616494 mvStorageDevGetDeviceType + .text 0x00617550 0xc38 board/mv_feroceon/config_kw/libconfig_kw.a(mvSFlash.o) + 0x00617d0c mvSFlashStatRegLock + 0x00617550 mvSFlashSizeGet + 0x006175f0 mvSFlashPowerSaveExit + 0x00617590 mvSFlashPowerSaveEnter + 0x00617f7c mvSFlashInit + 0x00617ecc mvSFlashFastBlockRd + 0x00618064 mvSFlashBlockWr + 0x0061780c mvSFlashWpRegionGet + 0x00617564 mvSFlashModelGet + 0x00617b44 mvSFlashSectorErase + 0x00617aa0 mvSFlashChipErase + 0x006176e0 mvSFlashIdGet + 0x0061766c mvSFlashBlockRd + 0x00617d70 mvSFlashWpRegionSet + .text 0x00618188 0x1584 board/mv_feroceon/config_kw/libconfig_kw.a(mvEthPhy.o) + 0x00618afc mvEthE1011PhyBasicInit + 0x00618c7c mvEthE1116PhyBasicInit + 0x00618ec0 Is_link_mvEthE1111Phy + 0x00619184 buffalo_all_link_led_off + 0x00618280 mvEthPhyRegWrite + 0x006191c8 mvEth1121PhyBasicInit + 0x00618398 mvEthSgmiiToCopperPhyBasicInit + 0x006184a0 buffalo_link_led_off_mvEthE111xPhy + 0x00618de4 mvEthE1112PhyBasicInit + 0x00619140 buffalo_all_link_led_on + 0x00618268 rdPhy + 0x00619440 mvEthPhyReset + 0x0061849c buffalo_link_led_on + 0x0061964c mvEthE1111PhyBasicInit + 0x00618f04 mvEthPhyPrintStatus + 0x00618530 buffalo_link_led_off + 0x00618300 mvEthPhyCheckLink + 0x00618af4 mvEthE1112PhyPowerDown + 0x00618534 Is_mvEthE111xPhy + 0x006192b4 mvEth1145PhyBasicInit + 0x006185b4 bfPhyPowerUp + 0x00618ffc mvEthPhyDisableAN + 0x006190ec buffalo_print_phy_addr + 0x00618aec mvEthE1112PhyPowerUp + 0x00618188 mvEthPhyRegRead + 0x00618b94 mvEthE3016PhyBasicInit + 0x00618774 mvEthE111xPhyBasicInit_internal + 0x00619398 mvEthPhyRestartAN + 0x0061840c buffalo_link_led_on_mvEthE111xPhy + 0x006194d8 mvEthPhyLoopback + .text 0x0061970c 0x4dc board/mv_feroceon/config_kw/libconfig_kw.a(mvRtc.o) + 0x0061986c mvRtcInit + 0x00619b8c buffalo_IsStopAtUbootStatus + 0x00619870 mvRtcAlarmSet + 0x00619a98 mvRtcAlarmGet + 0x006199d0 bfGetMagicKey + 0x006199e0 mvRtcTimeGet + 0x0061970c mvRtcTimeSet + 0x00619b50 bfSetMagicKey + .text 0x00619be8 0x940 board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsi.o) + 0x0061a320 mvTwsiRead + 0x0061a120 mvTwsiStopBitSet + 0x00619f18 mvTwsiAddrSet + 0x0061a268 mvTwsiWrite + 0x0061a1b8 mvTwsiStartBitSet + 0x00619c1c mvTwsiInit + .text 0x0061a528 0x5e8 board/mv_feroceon/config_kw/libconfig_kw.a(mvGpp.o) + 0x0061a99c bfGppOutEnableRegBitTest + 0x0061a528 mvGppValueGet + 0x0061a894 mvGppTypeSet + 0x0061a780 bfGppOutRegBitNagate + 0x0061a9f0 bfGppBlinkRegBitTest + 0x0061a5b0 mvGppBlinkEn + 0x0061a90c bfGppOutEnableRegBitClr + 0x0061a5f8 bfGppBlinkRegBitSet + 0x0061a6ac mvGppValueSet + 0x0061a7d8 bfGppOutRegBitAssert + 0x0061a568 mvGppPolaritySet + 0x0061aa68 bfGppOutRegBitTest + 0x0061a96c mvGppPolarityGet + 0x0061a834 bfGppOutRegBitClr + 0x0061a93c bfGppOutEnableRegBitSet + 0x0061a628 bfGppBlinkRegBitClr + 0x0061a658 bfGppDataInPolRegBitTest + 0x0061a864 bfGppOutRegBitSet + 0x0061aabc bfGppInRegBitTest + 0x0061aa44 bfGppOutRegBitInv + .text 0x0061ab10 0x4e0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpi.o) + 0x0061ae30 mvSpiCsAssert + 0x0061ad48 mvSpiReadWrite + 0x0061abe8 mvSpiRead + 0x0061ae18 mvSpiCsDeassert + 0x0061ac9c mvSpiWrite + 0x0061af0c mvSpiInit + 0x0061ae60 mvSpiBaudRateSet + .text 0x0061aff0 0x170 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpiCmnd.o) + 0x0061b098 mvSpiWriteThenWrite + 0x0061aff0 mvSpiWriteThenRead + 0x0061b110 mvSpiReadAndWrite + .text 0x0061b160 0x798 board/mv_feroceon/config_kw/libconfig_kw.a(mvUsb.o) + 0x0061b16c mvUsbRegs + 0x0061b1b0 mvUsbPowerUp + 0x0061b200 mvUsbHalInit + 0x0061b160 mvUsbGetCapRegAddr + 0x0061b170 mvUsbCoreRegs + 0x0061b1d8 mvUsbPowerDown + .text 0x0061b8f8 0x7c0 board/mv_feroceon/config_kw/libconfig_kw.a(mvXor.o) + 0x0061bb54 mvXorHalInit + 0x0061c098 mvXorEccCurrTimerGet + 0x0061b9b8 mvXorCommandSet + 0x0061bb98 mvXorEccClean + 0x0061b958 mvXorStateGet + 0x0061b8f8 mvXorCtrlSet + 0x0061be70 mvXorTransfer + 0x0061bf90 mvXorMemInit + 0x0061bd50 mvXorOverrideSet + .text 0x0061c0b8 0x23cc board/mv_feroceon/config_kw/libconfig_kw.a(mvEth.o) + 0x0061c95c mvEthMacAddrSet + 0x0061e208 mvEthCoalGet + 0x0061e0bc mvEthRxFilterModeSet + 0x0061df70 mvEthTosToRxqGet + 0x0061de68 mvEthVlanPrioRxQueue + 0x0061e35c mvEthRxCoalSet + 0x0061e1b0 mvEthMaxRxSizeSet + 0x0061da28 mvEthHeaderModeSet + 0x0061d874 mvEthPortPowerDown + 0x0061ddcc mvEthBpduRxQueue + 0x0061d74c mvEthHalInit + 0x0061c8fc mvEthSetOtherMcastTable + 0x0061cc00 mvEthMibCountersClear + 0x0061dd64 mvEthArpRxQueue + 0x0061e048 mvEthMacAddrGet + 0x0061d464 mvEthPortFinish + 0x0061c138 mvEthPortForceTxDone + 0x0061e2e0 mvEthTxCoalSet + 0x0061c89c mvEthSetSpecialMcastTable + 0x0061db88 mvEthSpeedDuplexSet + 0x0061c26c mvEthMcastCrc8Get + 0x0061ca60 mvEthMcastAddrSet + 0x0061ce58 mvEthEjpModeSet + 0x0061e3d8 mvEthPortForceRx + 0x0061dcfc mvEthTcpRxQueue + 0x0061cef0 mvEthPortDown + 0x0061cc30 mvEthPhyAddrSet + 0x0061d8e0 mvEthPortPowerUp + 0x0061cc64 ethResetRxDescRing + 0x0061c0b8 mvEthMemAttrGet + 0x0061dabc mvEthFlowCtrlSet + 0x0061ded4 mvEthTosToRxqSet + 0x0061dc94 mvEthUdpRxQueue + 0x0061d7ec mvEthPortEnable + 0x0061d4ec mvEthPortInit + 0x0061cd54 ethResetTxDescRing + 0x0061d178 mvEthDefaultsSet + 0x0061dfec mvEthMibCounterRead + 0x0061d984 mvEthPhyAddrGet + 0x0061d9b8 mvEthStatusGet + 0x0061c0d4 mvEthPortUp + 0x0061d0d8 mvEthPortDisable + .text 0x0061e484 0xae8 board/mv_feroceon/config_kw/libconfig_kw.a(mvPex.o) + 0x0061e6c4 mvPexLocalBusNumSet + 0x0061ec1c mvPexHalInit + 0x0061e650 mvPexLocalDevNumSet + 0x0061ea88 mvPexModeGet + 0x0061e8b8 mvPexConfigRead + 0x0061eb6c mvPexForceX1 + 0x0061e738 mvPexMasterEnable + 0x0061e798 mvPexConfigWrite + 0x0061e5d0 mvPexLocalDevNumGet + 0x0061e584 mvPexPhyRegRead + 0x0061eb40 mvPexIsPowerUp + 0x0061e544 mvPexPhyRegWrite + 0x0061ea00 mvPexSlaveEnable + 0x0061e484 mvPexPowerDown + 0x0061ebac mvPexActiveStateLinkPMEnable + 0x0061e610 mvPexLocalBusNumGet + .text 0x0061ef6c 0x9b8 board/mv_feroceon/config_kw/libconfig_kw.a(mvAudio.o) + 0x0061f110 mvI2SRecordCntrlGet + 0x0061f240 mvSPDIFRecordTclockSet + 0x0061f0c4 mvAudioDCOCtrlSet + 0x0061f3c0 mvI2SPlaybackCtrlSet + 0x0061f554 mvAudioSpcrCtrlGet + 0x0061f1d0 mvSPDIFRecordTclockGet + 0x0061f194 mvSPDIFRecordStatusGet + 0x0061f388 mvI2SPlaybackCtrlGet + 0x0061ef6c mvAudioHalInit + 0x0061f320 mvAudioRecordControlGet + 0x0061f138 mvI2SRecordCntrlSet + 0x0061efb8 mvAudioDCOCtrlGet + 0x0061f4a8 mvAudioPlaybackStatusGet + 0x0061f504 mvAudioPlaybackControlGet + 0x0061f440 mvSPDIFPlaybackCtrlGet + 0x0061f580 mvAudioRecordControlSet + 0x0061f2d4 mvAudioRecordStatusGet + 0x0061efe4 mvSPDIFPlaybackCtrlSet + 0x0061f768 mvAudioPlaybackControlSet + .text 0x0061f924 0x12d8 board/mv_feroceon/config_kw/libconfig_kw.a(mvTsu.o) + 0x0061fcc0 mvTsuRxNextBuffGet + 0x0061fbbc mvTsuTxFreeBuffCountGet + 0x0061fd98 mvTsuRxFullBuffCountGet + 0x0061fe90 mvTsuHalInit + 0x00620998 mvTsuPortSignalCfgSet + 0x006202a8 mvTsuRxTimestampCntEn + 0x00620238 mvTsuRxFlushErrorPackets + 0x0061ff88 mvTsuTxInitTimeStampSet + 0x0061f92c mvTsuPortReset + 0x0061fbfc mvTsuTxNextBuffGet + 0x006204c0 mvTsuBuffersInit + 0x0061f968 mvTsuRxBuffFree + 0x00620ac0 mvTsuPortInit + 0x006208a8 mvTsuPortSignalCfgGet + 0x006203dc mvTsuAggrMode1TmsOnPcktEn + 0x0061fa58 mvTsuTxStatusGet + 0x00620360 mvTsuRxSyncDetectionSet + 0x00620034 mvTsuTxBuffPut + 0x00620144 mvTsuTxClockFreqSet + 0x0061ff0c mvTsuTxDone + 0x00620308 mvTsuRxSyncDetectionGet + 0x0061f924 mvTsuShutdown + 0x00620840 mvTsuStatusGet + 0x0061fe20 mvTsuPortShutdown + 0x0062044c mvTsuDmaWatermarkSet + .text 0x00620bfc 0x4 board/mv_feroceon/config_kw/libconfig_kw.a(mvLcd.o) + 0x00620bfc mvLcdHalInit + .text 0x00620c00 0xd9c board/mv_feroceon/config_kw/libconfig_kw.a(BuffaloWol.o) + 0x00621258 bfGetWolPatternString + 0x00620f0c bfGetWolInterruptStatus + 0x00620e60 bfIsSupportWol + 0x00621880 bfSetWolMagicWaitMode + 0x00620da8 bfSetPowerSaveMode + 0x006214a8 bfSetWolFrameWaitMode + 0x00620c00 bfWriteWolFrameMatchingLen + 0x00621974 bfResetEthPhy + 0x006212fc bfControlWolInterrupt + 0x00621030 bfDumpSramData + .text 0x0062199c 0x474 board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvAddrDec.o) + 0x006219dc mvCtrlAddrDecToReg + 0x00621a20 mvCtrlTargetGet + 0x00621cf8 mvCtrlAttribGet + 0x00621b44 mvCtrlParamsToAddrDec + 0x0062199c mvCtrlRegToAddrDec + 0x00621bac mvCtrlAddrDecToParams + .text 0x00621e10 0x8 board/mv_feroceon/config_kw/libconfig_kw.a(mvOsSata.o) + 0x00621e14 mvSwapWord + 0x00621e10 mvSwapShort + .text 0x00621e18 0x48c cpu/arm926ejs/libarm926ejs.a(interrupts.o) + 0x00621e24 set_timer + 0x00621f90 reset_timer + 0x006221cc do_fiq + 0x00622010 interrupt_init + 0x00622280 do_undefined_instruction + 0x00622044 show_regs + 0x006221a8 do_irq + 0x00621e34 get_tbclk + 0x00621f18 get_timer + 0x00621f48 reset_timer_masked + 0x00622184 bad_mode + 0x00621e3c get_timer_masked + 0x00621f94 udelay + 0x00621ed0 udelay_masked + 0x00622238 do_prefetch_abort + 0x00621f2c get_ticks + 0x00621e1c disable_interrupts + 0x006221f0 do_not_used + 0x00622214 do_data_abort + 0x0062225c do_software_interrupt + 0x00621e18 enable_interrupts + .text 0x006222a4 0x2a8 cpu/arm926ejs/libarm926ejs.a(cpu.o) + 0x006222d8 cleanup_before_linux + 0x006222d0 cpu_init + 0x006223f8 icache_enable + 0x006223d8 do_reset + 0x006224f8 icache_disable + 0x00622478 dcache_status + 0x0062244c icache_status + 0x006224a4 dcache_disable + .text 0x0062254c 0x364 lib_arm/libarm.a(board.o) + 0x00622648 hang + 0x00622658 start_armboot + 0x0062254c sbrk + .text 0x006228b0 0x4 lib_arm/libarm.a(cache.o) + 0x006228b0 flush_cache + .text 0x006228b4 0xe58 fs/ext2/libext2fs.a(ext2fs.o) + 0x00622a64 ext2fs_read_file + 0x00622fbc ext2fs_close + 0x0062298c ext2fs_mount + 0x00623690 ext2fs_ls + 0x00623568 ext2fs_find_file + 0x006235f8 ext2fs_open + 0x00622f9c ext2fs_free_node + 0x00622f60 ext2fs_read + 0x006232c4 ext2fs_find_file1 + .text 0x0062370c 0x23c fs/ext2/libext2fs.a(dev.o) + 0x006238f4 ext2fs_set_blk_dev + 0x0062370c ext2fs_devread + .text 0x00623948 0x13d4 net/libnet.a(net.o) + 0x00623b48 getenv_IPaddr + 0x006239f0 NetCksumOk + 0x006245d0 NetSetTimeout + 0x00623a1c copy_filename + 0x00623b60 NetEthHdrSize + 0x00623c04 ip_to_string + 0x0062485c ArpTimeoutCheck + 0x00623fac NetReceive + 0x00623ad4 string_to_ip + 0x00624608 NetSendUDPPacket + 0x00623c50 print_IPaddr + 0x00623c74 NetSetEther + 0x006248d0 NetLoop + 0x00623ebc ArpRequest + 0x00623bac VLAN_to_string + 0x00623abc getenv_VLAN + 0x006239ac NetCksum + 0x00623d38 NetSetIP + 0x00623a6c string_to_VLAN + 0x0062476c NetStartAgain + 0x0062399c NetSetHandler + 0x00624490 PingSend + 0x00623eb8 NetSendPacket + .text 0x00624d1c 0x634 net/libnet.a(tftp.o) + 0x00624eac TftpStart + .text 0x00625350 0x6c4 net/libnet.a(bootp.o) + 0x00625410 BootpRequest + .text 0x00625a14 0x1ac net/libnet.a(rarp.o) + 0x00625a14 RarpRequest + .text 0x00625bc0 0x510 net/libnet.a(eth.o) + 0x00625ce0 eth_get_dev_by_name + 0x00625c1c eth_halt + 0x00625e84 eth_register + 0x00625bc0 eth_get_dev + 0x00625da0 eth_try_another + 0x00625f14 eth_set_enetaddr + 0x00625fcc eth_initialize + 0x00625d34 eth_set_current + 0x00625c8c eth_rx + 0x00625bd0 eth_get_dev_index + 0x00625e1c eth_init + 0x00625cc0 eth_get_name + 0x00625c50 eth_send + .text 0x006260d0 0x89c net/libnet.a(rcvr.o) + 0x006262a0 RecoverRequest + .text 0x0062696c 0x390 disk/libdisk.a(part.o) + 0x00626a7c dev_print + 0x00626a14 print_part + 0x00626c84 get_partition_info + 0x00626cc8 init_part + .text 0x00626cfc 0x5c0 disk/libdisk.a(part_dos.o) + 0x006270a0 get_partition_info_dos + 0x00627290 print_part_dos + 0x00626d44 test_part_dos + .text 0x006272bc 0x6f0 disk/libdisk.a(part_efi.o) + 0x00627874 print_part_efi + 0x00627394 test_part_efi + 0x0062777c get_partition_info_efi + .text 0x006279ac 0x1adc drivers/libdrivers.a(cfi_flash.o) + 0x00627dfc flash_get_size + 0x006279e8 flash_read_ushort + 0x00629160 flash_erase + 0x006293d0 flash_read_user_serial + 0x00629310 flash_init + 0x006279ac flash_add_base_addr + 0x00628fd0 flash_print_info + 0x00627a0c flash_read_long + 0x006287ac flash_real_protect + 0x006279d4 flash_read_uchar + 0x006279c0 flash_make_addr + 0x0062942c flash_read_factory_serial + 0x00628a30 write_buff + .text 0x00629488 0xac0 common/libcommon.a(main.o) + 0x006294fc run_command + 0x00629488 do_run + 0x00629ae8 readline + 0x00629dec main_loop + .text 0x00629f48 0x78 common/libcommon.a(cmd_boot.o) + 0x00629f48 do_go + .text 0x00629fc0 0xce8 common/libcommon.a(cmd_bootm.o) + 0x0062a158 print_image_hdr + 0x0062a690 do_bootd + 0x00629fe0 gunzip + 0x0062a6bc do_bootm + 0x0062a624 do_iminfo + .text 0x0062aca8 0x324 common/libcommon.a(cmd_date.o) + 0x0062aebc do_date + 0x0062acec mk_date + .text 0x0062afcc 0x4fc common/libcommon.a(cmd_ext2.o) + 0x0062b378 do_ext2ls + 0x0062b080 do_ext2load + .text 0x0062b4c8 0x418 common/libcommon.a(cmd_fat.o) + 0x0062b758 do_fat_fsload + 0x0062b564 do_fat_fsinfo + 0x0062b648 do_fat_ls + 0x0062b4c8 get_dev + .text 0x0062b8e0 0xf5c common/libcommon.a(cmd_flash.o) + 0x0062c770 do_flinfo + 0x0062c3a4 flash_sect_erase + 0x0062bf60 do_protect + 0x0062c4a4 do_flerase + 0x0062bae0 flash_sect_protect + .text 0x0062c83c 0x203c common/libcommon.a(cmd_jffs2.o) + 0x0062e530 do_jffs2_chpart + 0x0062d950 mtdparts_init + 0x0062ced0 id_parse + 0x0062cfb8 find_dev_and_part + 0x0062e5e8 do_jffs2_fsinfo + 0x0062e674 do_jffs2_ls + 0x0062dfa4 do_jffs2_mtdparts + 0x0062e6f4 do_jffs2_fsload + .text 0x0062e878 0xc38 common/libcommon.a(cmd_mem.o) + 0x0062e878 do_mem_base + 0x0062f1ec do_mem_mw + 0x0062e8c4 do_mem_crc + 0x0062ec98 do_mem_nm + 0x0062ecc0 do_mem_mm + 0x0062ede0 do_mem_cp + 0x0062e980 do_mem_mtest + 0x0062f048 do_mem_cmp + 0x0062eab0 cmd_get_data_size + 0x0062ece8 do_mem_loop + 0x0062f2c4 do_mem_md + .text 0x0062f4b0 0x30 common/libcommon.a(cmd_mmc.o) + 0x0062f4b0 do_mmc + .text 0x0062f4e0 0x374 common/libcommon.a(cmd_net.o) + 0x0062f830 do_rarpb + 0x0062f4e0 do_ping + 0x0062f83c do_tftpb + 0x0062f848 do_bootp + .text 0x0062f854 0x934 common/libcommon.a(cmd_nvedit.o) + 0x0062f9c8 getenv + 0x0062fa48 _do_setenv + 0x0062f8c4 getenv_r + 0x0062ffe8 do_printenv + 0x0062ffac setenv + 0x0062f994 do_saveenv + 0x0062ff60 do_setenv + .text 0x00630188 0x1354 common/libcommon.a(cmd_usb.o) + 0x00630ef4 usb_display_conf_desc + 0x006308f4 usb_show_tree_graph + 0x006301a8 usb_get_class_desc + 0x0063024c usb_display_ep_desc + 0x00630bf0 usb_display_desc + 0x00630320 usb_display_class_sub + 0x00630bbc usb_show_tree + 0x00630e24 usb_display_string + 0x00630e5c usb_display_if_desc + 0x00630fa4 usb_display_config + 0x00630530 do_usbboot + 0x00631038 do_usb + .text 0x006314dc 0xd1c common/libcommon.a(command.o) + 0x006314dc do_echo + 0x006316b4 cmd_auto_complete + 0x00631d48 do_exit + 0x00631618 find_cmd + 0x00631d80 do_test + 0x00631b64 install_auto_complete + 0x00631ba4 do_help + 0x00631590 var_complete + 0x00631568 do_version + .text 0x006321f8 0x510 common/libcommon.a(console.o) + 0x006323c0 console_init_r + 0x006325dc printf + 0x006324a8 console_assign + 0x006326a0 getc + 0x00632590 puts + 0x006323a4 dbg + 0x00632624 serial_printf + 0x006322d0 ftstc + 0x00632544 fprintf + 0x00632688 tstc + 0x006325ac vprintf + 0x006326b8 ctrlc + 0x0063266c putc + 0x00632368 disable_ctrlc + 0x006322a0 fgetc + 0x00632380 had_ctrlc + 0x00632300 fputc + 0x006323b0 console_init_f + 0x00632390 clear_ctrlc + 0x00632334 fputs + .text 0x00632708 0xfc common/libcommon.a(devices.o) + 0x0063272c device_register + 0x00632708 devices_done + 0x00632758 devices_init + .text 0x00632804 0x1100 common/libcommon.a(dlmalloc.o) + 0x00632c14 malloc + 0x00633364 pvalloc + 0x00633388 calloc + 0x0063283c malloc_usable_size + 0x00633470 realloc + 0x006328f8 malloc_trim + 0x00632804 malloc_bin_reloc + 0x00632880 mallopt + 0x00633248 memalign + 0x00632c10 cfree + 0x0063337c valloc + 0x006329c8 free + .text 0x00633904 0x3e8 common/libcommon.a(env_common.o) + 0x00633924 env_get_addr + 0x00633970 env_complete + 0x00633aec bfKeepEthAddr + 0x00633c54 env_relocate + 0x00633ac0 env_crc_update + 0x00633904 env_get_char_memory + .text 0x00633cec 0x18c common/libcommon.a(env_flash.o) + 0x00633cf8 env_relocate_spec + 0x00633d14 saveenv + 0x00633cec env_get_char_spec + 0x00633de0 env_init + .text 0x00633e78 0xd4 common/libcommon.a(exports.o) + 0x00633e84 jumptable_init + 0x00633e7c get_version + .text 0x00633f4c 0x3e4 common/libcommon.a(flash.o) + 0x006340a0 flash_write + 0x0063420c flash_protect + 0x00633f4c addr2info + 0x00633fc0 flash_perror + .text 0x00634330 0x1cdc common/libcommon.a(hush.o) + 0x006346e4 new_pipe + 0x00634458 mapset + 0x006356fc parse_string_outer + 0x00635070 update_ifs_map + 0x006356b4 parse_file_outer + 0x0063434c simple_itoa + 0x00634a58 reserved_word + 0x00634480 u_boot_hush_start + .text 0x0063600c 0x3e4 common/libcommon.a(lists.o) + 0x00636310 DisposeHandle + 0x00636330 ListDispose + 0x00636140 ListInsertItems + 0x00636014 ListSetAllocationPolicy + 0x00636064 ListGetItemSize + 0x00636058 ListGetDataPtr + 0x00636334 NewHandle + 0x006360c4 SetHandleSize + 0x00636308 ListInsertItem + 0x0063600c GetHandleSize + 0x00636070 ListNumItems + 0x00636028 ListGetPtrToItem + 0x00636390 ListCreate + 0x0063607c ListGetItems + .text 0x006363f0 0x1724 common/libcommon.a(usb.o) + 0x00636f80 usb_set_idle + 0x00636408 usb_maxpacket + 0x006378f4 usb_hub_probe + 0x00637aec usb_stop + 0x00637a70 usb_init + 0x006363f0 usb_disable_asynch + 0x006379c8 usb_clear_halt + 0x00636788 usb_bulk_msg + 0x00636ea0 usb_get_class_descriptor + 0x00637968 usb_scan_devices + 0x00636bb8 usb_get_hub_descriptor + 0x00636900 usb_get_port_status + 0x00636764 usb_submit_int_msg + 0x00636618 usb_parse_config + 0x006367f8 usb_control_msg + 0x00636fe4 usb_set_protocol + 0x006375b4 usb_hub_port_connect_change + 0x006370b8 usb_set_interface + 0x00636524 usb_hub_allocate + 0x00636da4 usb_string + 0x00636f10 usb_get_report + 0x006371c8 usb_get_descriptor + 0x006376e0 usb_hub_configure + 0x00636c18 usb_get_string + 0x00636768 wait_ms + 0x00636b60 usb_clear_hub_feature + 0x00637230 usb_get_configuration_no + 0x00636a58 usb_clear_port_feature + 0x006369b4 usb_set_port_feature + 0x006372d0 usb_new_device + 0x00636960 usb_get_hub_status + 0x00637044 usb_set_configuration + 0x0063642c usb_set_maxpacket + 0x00637180 usb_set_address + 0x0063656c usb_alloc_new_device + 0x00636510 usb_hub_reset + 0x006364e0 usb_get_dev_index + .text 0x00637b14 0x139c common/libcommon.a(usb_storage.o) + 0x00637eb0 usb_storage_probe + 0x00638c50 usb_stor_CB_transport + 0x00638934 usb_stor_CB_comdat + 0x00637b34 usb_stor_get_dev + 0x0063830c usb_stor_read + 0x00637b6c usb_show_progress + 0x00638524 usb_stor_scan + 0x00638664 usb_stor_BBB_comdat + 0x00638e40 usb_stor_info + 0x00637c6c usb_stor_get_info + 0x006380dc usb_stor_BBB_clear_endpt_stall + 0x00638b74 usb_stor_CBI_get_status + 0x00638758 usb_stor_BBB_transport + .text 0x00638eb0 0x200 lib_generic/libgeneric.a(crc32.o) + 0x00638eb0 crc32 + 0x00638fb0 crc32_no_comp + .text 0x006390b0 0x0 lib_generic/libgeneric.a(ctype.o) + .text 0x006390b0 0xc8 lib_generic/libgeneric.a(display_options.o) + 0x00639150 display_options + 0x006390b0 print_size + .text 0x00639178 0x5d4 lib_generic/libgeneric.a(string.o) + 0x00639178 strcpy + 0x006395d8 memscan + 0x00639554 memmove + 0x00639534 memcpy + 0x006394a0 strswab + 0x0063932c strnlen + 0x006392ec strrchr + 0x006391b8 strcat + 0x00639668 memchr + 0x006395fc strstr + 0x0063925c strncmp + 0x00639190 strncpy + 0x00639508 bcopy + 0x006393d8 strtok + 0x0063959c memcmp + 0x006391e4 strncat + 0x00639694 strdup + 0x006394ec memset + 0x00639230 strcmp + 0x00639464 strsep + 0x006396d0 strnicmp + 0x00639354 strspn + 0x006392cc strlen + 0x006392a0 strchr + 0x00639398 strpbrk + .text 0x0063974c 0x810 lib_generic/libgeneric.a(vsprintf.o) + 0x00639b3c vsprintf + 0x0063980c simple_strtol + 0x00639ae4 panic + 0x00639f2c sprintf + 0x0063974c simple_strtoul + .text 0x00639f5c 0x2d80 lib_generic/libgeneric.a(zlib.o) + 0x0063aebc inflate + 0x0063a920 inflateInit2 + 0x0063ad8c inflateIncomp + 0x0063aa70 adler32 + 0x0063a7ac inflateReset + 0x0063a814 inflateSync + 0x0063aa68 inflateInit + 0x0063a70c inflateEnd + .text 0x0063ccdc 0x1dc board/mv_feroceon/config_kw/libconfig_kw.a(mvCntmr.o) + 0x0063ccdc mvCntmrLoad + 0x0063cda4 mvCntmrCtrlGet + 0x0063ce30 mvCntmrRead + 0x0063ce88 mvCntmrEnable + 0x0063cdf0 mvCntmrStart + 0x0063ce58 mvCntmrDisable + 0x0063cd14 mvCntmrWrite + 0x0063cd3c mvCntmrCtrlSet + .text 0x0063ceb8 0x298 board/mv_feroceon/config_kw/libconfig_kw.a(mv_dram.o) + 0x0063cfdc dram_init + 0x0063cfd0 mvIntrfaceWidthPrint + 0x0063ceb8 mvIntrfaceParamPrint + .text 0x0063d150 0x104 board/mv_feroceon/config_kw/libconfig_kw.a(mv_serial.o) + 0x0063d150 serial_setbrg + 0x0063d194 serial_tstc + 0x0063d1b4 serial_putc + 0x0063d204 serial_init + 0x0063d1e0 serial_puts + 0x0063d19c serial_getc + .text 0x0063d254 0xa00 board/mv_feroceon/config_kw/libconfig_kw.a(mv_egiga.o) + 0x0063d300 mv_eth_initialize + .text 0x0063dc54 0xc44 board/mv_feroceon/config_kw/libconfig_kw.a(mmc.o) + 0x0063dc68 mmc_ident + 0x0063e5dc mmc_block_read + 0x0063e7bc mmc_write + 0x0063def4 mmc_init + 0x0063dc54 mmc_get_dev + 0x0063dc70 mmc2info + 0x0063e798 mmc_bread + 0x0063e670 mmc_read + 0x0063dc60 mmc_block_write + .text 0x0063e898 0x128c board/mv_feroceon/config_kw/libconfig_kw.a(mvDramIf.o) + 0x0063f98c mvDramIfShow + 0x0063e980 mvDramIfCalGet + 0x0063ea30 mvDramIfDetect + 0x0063e898 mvDramIfGetCSorder + 0x0063e9f4 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0x006468ec 0x0 lib_arm/libarm.a(armlinux.o) + .vfp11_veneer 0x006468ec 0x0 fs/cramfs/libcramfs.a(cramfs.o) + .vfp11_veneer 0x006468ec 0x0 fs/cramfs/libcramfs.a(uncompress.o) + .vfp11_veneer 0x006468ec 0x0 fs/fat/libfat.a(fat.o) + .vfp11_veneer 0x006468ec 0x0 fs/jffs2/libjffs2.a(jffs2_1pass.o) + .vfp11_veneer 0x006468ec 0x0 fs/jffs2/libjffs2.a(compr_rtime.o) + .vfp11_veneer 0x006468ec 0x0 fs/jffs2/libjffs2.a(compr_rubin.o) + .vfp11_veneer 0x006468ec 0x0 fs/jffs2/libjffs2.a(compr_zlib.o) + .vfp11_veneer 0x006468ec 0x0 fs/jffs2/libjffs2.a(mini_inflate.o) + .vfp11_veneer 0x006468ec 0x0 rtc/librtc.a(date.o) + .vfp11_veneer 0x006468ec 0x0 drivers/usb/libusb.a(usb_ehci.o) + .vfp11_veneer 0x006468ec 0x0 /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_udivsi3.o) + .vfp11_veneer 0x006468ec 0x0 /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_divsi3.o) + .vfp11_veneer 0x006468ec 0x0 /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_dvmd_lnx.o) + +.dummy 0x006468ec 0x10 + .dummy 0x006468ec 0x10 board/mv_feroceon/USP/jump.o + 0x006468fc . = ALIGN (0x4) + +.rodata 0x006468fc 0xfa4 + *(.rodata) + .rodata 0x006468fc 0x100 board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) + .rodata 0x006469fc 0x114 board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) + .rodata 0x00646b10 0x140 board/mv_feroceon/config_kw/libconfig_kw.a(mvCpu.o) + .rodata 0x00646c50 0x194 board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvLib.o) + .rodata 0x00646de4 0x10 board/mv_feroceon/config_kw/libconfig_kw.a(mv_flash.o) + .rodata 0x00646df4 0x14 board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) + .rodata 0x00646e08 0x214 board/mv_feroceon/config_kw/libconfig_kw.a(mvSFlash.o) + .rodata 0x0064701c 0x2c board/mv_feroceon/config_kw/libconfig_kw.a(mvRtc.o) + .rodata 0x00647048 0xe board/mv_feroceon/config_kw/libconfig_kw.a(mvSpi.o) + .rodata 0x00647056 0xd8 board/mv_feroceon/config_kw/libconfig_kw.a(BuffaloWol.o) + *fill* 0x0064712e 0x2 00 + .rodata 0x00647130 0x80 cpu/arm926ejs/libarm926ejs.a(interrupts.o) + .rodata 0x006471b0 0x50 lib_arm/libarm.a(board.o) + 0x006471b0 version_string + 0x006471f0 buffalo_version_string + .rodata 0x00647200 0x8 net/libnet.a(net.o) + .rodata 0x00647208 0x60 disk/libdisk.a(part_efi.o) + .rodata 0x00647268 0x20 common/libcommon.a(cmd_nvedit.o) + .rodata 0x00647288 0x10 common/libcommon.a(env_common.o) + .rodata 0x00647298 0x400 lib_generic/libgeneric.a(crc32.o) + .rodata 0x00647698 0x90 lib_generic/libgeneric.a(zlib.o) + .rodata 0x00647728 0x24 board/mv_feroceon/config_kw/libconfig_kw.a(mv_egiga.o) + .rodata 0x0064774c 0x20 board/mv_feroceon/config_kw/libconfig_kw.a(mvDramIf.o) + .rodata 0x0064776c 0xc8 fs/jffs2/libjffs2.a(jffs2_1pass.o) + .rodata 0x00647834 0x13 fs/jffs2/libjffs2.a(mini_inflate.o) + *fill* 0x00647847 0x1 00 + .rodata 0x00647848 0x30 rtc/librtc.a(date.o) + .rodata 0x00647878 0x28 drivers/usb/libusb.a(usb_ehci.o) + +.rodata.str1.4 0x006478a0 0xc9a4 + .rodata.str1.4 + 0x006478a0 0x1133 board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) + 0x1168 (size before relaxing) + *fill* 0x006489d3 0x1 00 + .rodata.str1.4 + 0x006489d4 0x11b5 board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) + 0x121c (size before relaxing) + *fill* 0x00649b89 0x3 00 + .rodata.str1.4 + 0x00649b8c 0x136 board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) + 0x13c (size before relaxing) + *fill* 0x00649cc2 0x2 00 + .rodata.str1.4 + 0x00649cc4 0x5d board/mv_feroceon/config_kw/libconfig_kw.a(mvAhbToMbus.o) + 0x64 (size before relaxing) + *fill* 0x00649d21 0x3 00 + .rodata.str1.4 + 0x00649d24 0x39 board/mv_feroceon/config_kw/libconfig_kw.a(mvCpuIf.o) + 0x54 (size before relaxing) + *fill* 0x00649d5d 0x3 00 + .rodata.str1.4 + 0x00649d60 0x21 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysXor.o) + 0x40 (size before relaxing) + *fill* 0x00649d81 0x3 00 + .rodata.str1.4 + 0x00649d84 0x9 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysGbe.o) + 0x48 (size before relaxing) + *fill* 0x00649d8d 0x3 00 + .rodata.str1.4 + 0x00649d90 0x8 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysAudio.o) + 0x44 (size before relaxing) + .rodata.str1.4 + 0x00649d98 0x6 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysTs.o) + 0x44 (size before relaxing) + *fill* 0x00649d9e 0x2 00 + .rodata.str1.4 + 0x00649da0 0xa5 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysPex.o) + 0xf4 (size before relaxing) + *fill* 0x00649e45 0x3 00 + .rodata.str1.4 + 0x00649e48 0xa board/mv_feroceon/config_kw/libconfig_kw.a(mvSysSata.o) + 0x48 (size before relaxing) + *fill* 0x00649e52 0x2 00 + .rodata.str1.4 + 0x00649e54 0x14 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysUsb.o) + 0x48 (size before relaxing) + .rodata.str1.4 + 0x00649e68 0x10a board/mv_feroceon/config_kw/libconfig_kw.a(mvCpu.o) + 0x110 (size before relaxing) + *fill* 0x00649f72 0x2 00 + .rodata.str1.4 + 0x00649f74 0x6 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysLCD.o) + 0x3c (size before relaxing) + *fill* 0x00649f7a 0x2 00 + .rodata.str1.4 + 0x00649f7c 0x10 board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvLib.o) + 0x14 (size before relaxing) + .rodata.str1.4 + 0x00649f8c 0x665 board/mv_feroceon/config_kw/libconfig_kw.a(mv_flash.o) + 0x690 (size before relaxing) + *fill* 0x0064a5f1 0x3 00 + .rodata.str1.4 + 0x0064a5f4 0x21a board/mv_feroceon/config_kw/libconfig_kw.a(mv_pageTable.o) + 0x250 (size before relaxing) + *fill* 0x0064a80e 0x2 00 + .rodata.str1.4 + 0x0064a810 0x38 board/mv_feroceon/config_kw/libconfig_kw.a(mv_rtc.o) + .rodata.str1.4 + 0x0064a848 0xf board/mv_feroceon/config_kw/libconfig_kw.a(mv_mon_init.o) + 0x1c (size before relaxing) + *fill* 0x0064a857 0x1 00 + .rodata.str1.4 + 0x0064a858 0xccb board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) + 0xd10 (size before relaxing) + *fill* 0x0064b523 0x1 00 + .rodata.str1.4 + 0x0064b524 0x166 board/mv_feroceon/config_kw/libconfig_kw.a(mv_protectionUnit.o) + 0x184 (size before relaxing) + *fill* 0x0064b68a 0x2 00 + .rodata.str1.4 + 0x0064b68c 0x1e3 board/mv_feroceon/config_kw/libconfig_kw.a(mv_ext2_boot.o) + 0x208 (size before relaxing) + *fill* 0x0064b86f 0x1 00 + .rodata.str1.4 + 0x0064b870 0x3a board/mv_feroceon/config_kw/libconfig_kw.a(mvCommon.o) + 0x40 (size before relaxing) + *fill* 0x0064b8aa 0x2 00 + .rodata.str1.4 + 0x0064b8ac 0x3a5 board/mv_feroceon/config_kw/libconfig_kw.a(mvFlashCom.o) + 0x3d4 (size before relaxing) + *fill* 0x0064bc51 0x3 00 + .rodata.str1.4 + 0x0064bc54 0xb0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSFlash.o) + .rodata.str1.4 + 0x0064bd04 0x108 board/mv_feroceon/config_kw/libconfig_kw.a(mvEthPhy.o) + 0x10c (size before relaxing) + .rodata.str1.4 + 0x0064be0c 0x3c board/mv_feroceon/config_kw/libconfig_kw.a(mvRtc.o) + .rodata.str1.4 + 0x0064be48 0x122 board/mv_feroceon/config_kw/libconfig_kw.a(BuffaloWol.o) + 0x130 (size before relaxing) + *fill* 0x0064bf6a 0x2 00 + .rodata.str1.4 + 0x0064bf6c 0x28f cpu/arm926ejs/libarm926ejs.a(interrupts.o) + 0x29c (size before relaxing) + *fill* 0x0064c1fb 0x1 00 + .rodata.str1.4 + 0x0064c1fc 0x100 lib_arm/libarm.a(board.o) + 0x124 (size before relaxing) + .rodata.str1.4 + 0x0064c2fc 0x1cf fs/ext2/libext2fs.a(ext2fs.o) + 0x1d0 (size before relaxing) + *fill* 0x0064c4cb 0x1 00 + .rodata.str1.4 + 0x0064c4cc 0xe1 fs/ext2/libext2fs.a(dev.o) + 0xe4 (size before relaxing) + *fill* 0x0064c5ad 0x3 00 + .rodata.str1.4 + 0x0064c5b0 0x221 net/libnet.a(net.o) + 0x244 (size before relaxing) + *fill* 0x0064c7d1 0x3 00 + .rodata.str1.4 + 0x0064c7d4 0x1c5 net/libnet.a(tftp.o) + 0x1e8 (size before relaxing) + *fill* 0x0064c999 0x3 00 + .rodata.str1.4 + 0x0064c99c 0x74 net/libnet.a(bootp.o) + 0xb4 (size before relaxing) + .rodata.str1.4 + 0x0064ca10 0x13 net/libnet.a(rarp.o) + 0x48 (size before relaxing) + *fill* 0x0064ca23 0x1 00 + .rodata.str1.4 + 0x0064ca24 0x31 net/libnet.a(eth.o) + 0x44 (size before relaxing) + *fill* 0x0064ca55 0x3 00 + .rodata.str1.4 + 0x0064ca58 0x2b5 net/libnet.a(rcvr.o) + 0x2c8 (size before relaxing) + *fill* 0x0064cd0d 0x3 00 + .rodata.str1.4 + 0x0064cd10 0x1b9 disk/libdisk.a(part.o) + 0x1c8 (size before relaxing) + *fill* 0x0064cec9 0x3 00 + .rodata.str1.4 + 0x0064cecc 0x111 disk/libdisk.a(part_dos.o) + 0x120 (size before relaxing) + *fill* 0x0064cfdd 0x3 00 + .rodata.str1.4 + 0x0064cfe0 0x27c disk/libdisk.a(part_efi.o) + 0x284 (size before relaxing) + .rodata.str1.4 + 0x0064d25c 0x263 drivers/libdrivers.a(cfi_flash.o) + 0x2bc (size before relaxing) + *fill* 0x0064d4bf 0x1 00 + .rodata.str1.4 + 0x0064d4c0 0x120 common/libcommon.a(main.o) + 0x174 (size before relaxing) + .rodata.str1.4 + 0x0064d5e0 0x104 common/libcommon.a(cmd_boot.o) + 0x118 (size before relaxing) + .rodata.str1.4 + 0x0064d6e4 0x816 common/libcommon.a(cmd_bootm.o) + 0x86c (size before relaxing) + *fill* 0x0064defa 0x2 00 + .rodata.str1.4 + 0x0064defc 0x16c common/libcommon.a(cmd_date.o) + 0x180 (size before relaxing) + .rodata.str1.4 + 0x0064e068 0x291 common/libcommon.a(cmd_ext2.o) + 0x340 (size before relaxing) + *fill* 0x0064e2f9 0x3 00 + .rodata.str1.4 + 0x0064e2fc 0x305 common/libcommon.a(cmd_fat.o) + 0x3fc (size before relaxing) + *fill* 0x0064e601 0x3 00 + .rodata.str1.4 + 0x0064e604 0x878 common/libcommon.a(cmd_flash.o) + 0x8cc (size before relaxing) + .rodata.str1.4 + 0x0064ee7c 0xf62 common/libcommon.a(cmd_jffs2.o) + 0xfbc (size before relaxing) + *fill* 0x0064fdde 0x2 00 + .rodata.str1.4 + 0x0064fde0 0x672 common/libcommon.a(cmd_mem.o) + 0x6bc (size before relaxing) + *fill* 0x00650452 0x2 00 + .rodata.str1.4 + 0x00650454 0x35 common/libcommon.a(cmd_mmc.o) + 0x38 (size before relaxing) + *fill* 0x00650489 0x3 00 + .rodata.str1.4 + 0x0065048c 0x195 common/libcommon.a(cmd_net.o) + 0x218 (size before relaxing) + *fill* 0x00650621 0x3 00 + .rodata.str1.4 + 0x00650624 0x31f common/libcommon.a(cmd_nvedit.o) + 0x384 (size before relaxing) + *fill* 0x00650943 0x1 00 + .rodata.str1.4 + 0x00650944 0x8c8 common/libcommon.a(cmd_usb.o) + 0xa84 (size before relaxing) + .rodata.str1.4 + 0x0065120c 0x358 common/libcommon.a(command.o) + 0x384 (size before relaxing) + .rodata.str1.4 + 0x00651564 0x2f common/libcommon.a(devices.o) + 0x48 (size before relaxing) + *fill* 0x00651593 0x1 00 + .rodata.str1.4 + 0x00651594 0x57 common/libcommon.a(env_common.o) + 0x70 (size before relaxing) + *fill* 0x006515eb 0x1 00 + .rodata.str1.4 + 0x006515ec 0x52 common/libcommon.a(env_flash.o) + 0x5c (size before relaxing) + *fill* 0x0065163e 0x2 00 + .rodata.str1.4 + 0x00651640 0x108 common/libcommon.a(flash.o) + 0x120 (size before relaxing) + .rodata.str1.4 + 0x00651748 0x17d common/libcommon.a(hush.o) + 0x1f0 (size before relaxing) + *fill* 0x006518c5 0x3 00 + .rodata.str1.4 + 0x006518c8 0x2c0 common/libcommon.a(usb.o) + .rodata.str1.4 + 0x00651b88 0x1e2 common/libcommon.a(usb_storage.o) + 0x1ec (size before relaxing) + *fill* 0x00651d6a 0x2 00 + .rodata.str1.4 + 0x00651d6c 0xd lib_generic/libgeneric.a(display_options.o) + 0x20 (size before relaxing) + *fill* 0x00651d79 0x3 00 + .rodata.str1.4 + 0x00651d7c 0x57 lib_generic/libgeneric.a(vsprintf.o) + 0x58 (size before relaxing) + *fill* 0x00651dd3 0x1 00 + .rodata.str1.4 + 0x00651dd4 0x20d lib_generic/libgeneric.a(zlib.o) + 0x214 (size before relaxing) + *fill* 0x00651fe1 0x3 00 + .rodata.str1.4 + 0x00651fe4 0x140 board/mv_feroceon/config_kw/libconfig_kw.a(mv_dram.o) + 0x144 (size before relaxing) + .rodata.str1.4 + 0x00652124 0x13b board/mv_feroceon/config_kw/libconfig_kw.a(mv_egiga.o) + 0x150 (size before relaxing) + *fill* 0x0065225f 0x1 00 + .rodata.str1.4 + 0x00652260 0x2be board/mv_feroceon/config_kw/libconfig_kw.a(mmc.o) + 0x2cc (size before relaxing) + *fill* 0x0065251e 0x2 00 + .rodata.str1.4 + 0x00652520 0x5fe board/mv_feroceon/config_kw/libconfig_kw.a(mvDramIf.o) + 0x604 (size before relaxing) + *fill* 0x00652b1e 0x2 00 + .rodata.str1.4 + 0x00652b20 0x1000 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpd.o) + 0x1008 (size before relaxing) + .rodata.str1.4 + 0x00653b20 0x93 lib_arm/libarm.a(armlinux.o) + 0x138 (size before relaxing) + *fill* 0x00653bb3 0x1 00 + .rodata.str1.4 + 0x00653bb4 0x1ab fs/cramfs/libcramfs.a(cramfs.o) + 0x1b4 (size before relaxing) + .rodata.str1.4 + 0x00000000 0x24 fs/cramfs/libcramfs.a(uncompress.o) + *fill* 0x00653d5f 0x1 00 + .rodata.str1.4 + 0x00653d60 0x17f fs/fat/libfat.a(fat.o) + 0x1ac (size before relaxing) + *fill* 0x00653edf 0x1 00 + .rodata.str1.4 + 0x00653ee0 0x364 fs/jffs2/libjffs2.a(jffs2_1pass.o) + 0x388 (size before relaxing) + .rodata.str1.4 + 0x00000000 0x4 drivers/usb/libusb.a(usb_ehci.o) + 0x00000004 . = ALIGN (0x4) + +.got + *(.got) + 0x00660000 . = (_start + 0x60000) + +.reset_vector_sect + 0x00660000 0x18c + board/mv_feroceon/USP/jump.o(.reset_vector_sect) + .reset_vector_sect + 0x00660000 0x18c board/mv_feroceon/USP/jump.o + 0x00660154 dramBoot + 0x0066018c . = ALIGN (0x4) + +.data 0x0066018c 0x16af + *(.data) + .data 0x0066018c 0x0 cpu/arm926ejs/start.o + .data 0x0066018c 0x0 board/mv_feroceon/USP/jump.o + .data 0x0066018c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(platform.o) + .data 0x0066018c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsiEeprom.o) + .data 0x0066018c 0x60 board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) + 0x0066018c _4BitSwapArry + 0x006601cc _3BitSwapArry + .data 0x006601ec 0x12c board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) + 0x006601ec mvCpuAddrWinMap + .data 0x00660318 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_service.o) + .data 0x00660318 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) + .data 0x00660318 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvAhbToMbus.o) + .data 0x00660318 0x40 board/mv_feroceon/config_kw/libconfig_kw.a(mvCpuIf.o) + 0x00660318 sampleAtResetTargetArray6180P + 0x00660338 sampleAtResetTargetArrayP + .data 0x00660358 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysXor.o) + 0x00660358 xorAddrDecPrioTap + .data 0x00660380 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysDram.o) + .data 0x00660380 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysGbe.o) + 0x00660380 ethAddrDecPrioTap + .data 0x006603a8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysAudio.o) + .data 0x006603a8 0x2c board/mv_feroceon/config_kw/libconfig_kw.a(mvSysTs.o) + 0x006603a8 tsuAddrDecPrioTap + .data 0x006603d4 0x14 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysPex.o) + 0x006603d4 pexDevBarPrioTable + .data 0x006603e8 0x18 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysSata.o) + 0x006603e8 sataAddrDecPrioTab + .data 0x00660400 0x18 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysUsb.o) + 0x00660400 usbAddrDecPrioTab + .data 0x00660418 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvCpu.o) + .data 0x00660418 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysLCD.o) + 0x00660418 lcdAddrDecPrioTap + .data 0x00660440 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0x00660ba8 mvlswvInfo + 0x00660dbc boardInfoTbl + 0x006604f4 mvlsxhInfoBoardDeCsInfo + 0x00660d10 mvlsqvInfoBoardDeCsInfo + 0x00660adc mvlswvInfoBoardMacInfo + 0x00660b5c mvlswvInfoBoardMppTypeInfo + 0x006609a4 mvlsvlInfoBoardGppInfo + 0x006604d8 mvlsxhInfoBoardMppConfigValue + 0x00660504 mvlsxhInfo + 0x00660d30 mvlsqvInfo + 0x00660a40 mvlsvlInfoBoardDeCsInfo + 0x006604c8 mvlsxhInfoBoardMppTypeInfo + 0x0066099c mvlsvlInfoBoardMacInfo + 0x00660c3c mvlsqvInfoBoardGppInfo + 0x00660590 mvlsxlInfo + 0x0066085c mvwssxInfoBoardGppInfo + 0x00660a14 mvlsvlInfoBoardMppTypeInfo + 0x00660644 mvlsxlGeV2InfoBoardMppConfigValue + .data 0x00660e00 0x18 board/mv_feroceon/config_kw/libconfig_kw.a(mv_flash.o) + .data 0x00660e18 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_pageTable.o) + .data 0x00660e18 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_rtc.o) + .data 0x00660e18 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_mon_init.o) + .data 0x00660e18 0x4 board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) + .data 0x00660e1c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_protectionUnit.o) + .data 0x00660e1c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_ext2_boot.o) + .data 0x00660e1c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSwitch.o) + .data 0x00660e1c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvCommon.o) + .data 0x00660e1c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvOs.o) + .data 0x00660e1c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvFlashCom.o) + .data 0x00660e1c 0x20 board/mv_feroceon/config_kw/libconfig_kw.a(mvSata.o) + 0x00660e1c edmaRegOffst + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvStorageDev.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSFlash.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvEthPhy.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvRtc.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsi.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvGpp.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpi.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpiCmnd.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvUsb.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvXor.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvEth.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvPex.o) + .data 0x00660e3c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvAudio.o) + .data 0x00660e3c 0x10 board/mv_feroceon/config_kw/libconfig_kw.a(mvTsu.o) + 0x00660e3c mvTsuCoreClock2Val + .data 0x00660e4c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvLcd.o) + .data 0x00660e4c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(BuffaloWol.o) + .data 0x00660e4c 0x78 board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvAddrDec.o) + 0x00660e4c mvTargetDefaultsArray + .data 0x00660ec4 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvOsSata.o) + .data 0x00660ec4 0x0 cpu/arm926ejs/libarm926ejs.a(interrupts.o) + .data 0x00660ec4 0x0 cpu/arm926ejs/libarm926ejs.a(cpu.o) + .data 0x00660ec4 0x28 lib_arm/libarm.a(board.o) + 0x00660ec4 init_sequence + .data 0x00660eec 0x0 lib_arm/libarm.a(cache.o) + .data 0x00660eec 0xc fs/ext2/libext2fs.a(ext2fs.o) + 0x00660ef0 indir1_blkno + 0x00660eec ext2_inode_size + 0x00660ef4 indir2_blkno + .data 0x00660ef8 0x0 fs/ext2/libext2fs.a(dev.o) + .data 0x00660ef8 0xa net/libnet.a(net.o) + 0x00660efa NetBcastAddr + 0x00660f00 NetOurNativeVLAN + 0x00660ef8 NetOurVLAN + .data 0x00660f02 0x0 net/libnet.a(tftp.o) + .data 0x00660f02 0x0 net/libnet.a(bootp.o) + .data 0x00660f02 0x0 net/libnet.a(rarp.o) + .data 0x00660f02 0x0 net/libnet.a(eth.o) + .data 0x00660f02 0x0 net/libnet.a(rcvr.o) + .data 0x00660f02 0x0 disk/libdisk.a(part.o) + .data 0x00660f02 0x0 disk/libdisk.a(part_dos.o) + .data 0x00660f02 0x0 disk/libdisk.a(part_efi.o) + *fill* 0x00660f02 0x2 00 + .data 0x00660f04 0x14 drivers/libdrivers.a(cfi_flash.o) + .data 0x00660f18 0x10 common/libcommon.a(main.o) + .data 0x00660f28 0x0 common/libcommon.a(cmd_boot.o) + .data 0x00660f28 0x4 common/libcommon.a(cmd_bootm.o) + 0x00660f28 load_addr + .data 0x00660f2c 0x1c common/libcommon.a(cmd_date.o) + 0x00660f2c weekdays + .data 0x00660f48 0x0 common/libcommon.a(cmd_ext2.o) + .data 0x00660f48 0x0 common/libcommon.a(cmd_fat.o) + .data 0x00660f48 0x0 common/libcommon.a(cmd_flash.o) + .data 0x00660f48 0x0 common/libcommon.a(cmd_jffs2.o) + .data 0x00660f48 0x4 common/libcommon.a(cmd_mem.o) + 0x00660f48 dp_last_length + .data 0x00660f4c 0x0 common/libcommon.a(cmd_mmc.o) + .data 0x00660f4c 0x0 common/libcommon.a(cmd_net.o) + .data 0x00660f4c 0x0 common/libcommon.a(cmd_nvedit.o) + .data 0x00660f4c 0x4 common/libcommon.a(cmd_usb.o) + .data 0x00660f50 0x0 common/libcommon.a(command.o) + .data 0x00660f50 0x0 common/libcommon.a(console.o) + .data 0x00660f50 0xc common/libcommon.a(devices.o) + 0x00660f50 stdio_names + .data 0x00660f5c 0x414 common/libcommon.a(dlmalloc.o) + .data 0x00661370 0x94 common/libcommon.a(env_common.o) + 0x00661400 env_get_char + 0x00661370 default_environment + .data 0x00661404 0x8 common/libcommon.a(env_flash.o) + 0x00661408 env_name_spec + 0x00661404 env_ptr + .data 0x0066140c 0x0 common/libcommon.a(exports.o) + .data 0x0066140c 0x0 common/libcommon.a(flash.o) + .data 0x0066140c 0x84 common/libcommon.a(hush.o) + .data 0x00661490 0x0 common/libcommon.a(lists.o) + .data 0x00661490 0x0 common/libcommon.a(usb.o) + .data 0x00661490 0x24 common/libcommon.a(usb_storage.o) + 0x00661490 us_direction + .data 0x006614b4 0x0 lib_generic/libgeneric.a(crc32.o) + .data 0x006614b4 0x100 lib_generic/libgeneric.a(ctype.o) + 0x006614b4 _ctype + .data 0x006615b4 0x0 lib_generic/libgeneric.a(display_options.o) + .data 0x006615b4 0x0 lib_generic/libgeneric.a(string.o) + .data 0x006615b4 0x0 lib_generic/libgeneric.a(vsprintf.o) + .data 0x006615b4 0x210 lib_generic/libgeneric.a(zlib.o) + 0x006617a0 zlib_version + 0x006617a4 z_errmsg + .data 0x006617c4 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvCntmr.o) + .data 0x006617c4 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_dram.o) + .data 0x006617c4 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_serial.o) + .data 0x006617c4 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_egiga.o) + .data 0x006617c4 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mmc.o) + .data 0x006617c4 0x10 board/mv_feroceon/config_kw/libconfig_kw.a(mvDramIf.o) + 0x006617c4 DRAM_CS_Order + .data 0x006617d4 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvUart.o) + .data 0x006617d4 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpd.o) + .data 0x006617d4 0x0 lib_arm/libarm.a(armlinux.o) + .data 0x006617d4 0x0 fs/cramfs/libcramfs.a(cramfs.o) + .data 0x006617d4 0x0 fs/cramfs/libcramfs.a(uncompress.o) + .data 0x006617d4 0x4 fs/fat/libfat.a(fat.o) + .data 0x006617d8 0x0 fs/jffs2/libjffs2.a(jffs2_1pass.o) + .data 0x006617d8 0x0 fs/jffs2/libjffs2.a(compr_rtime.o) + .data 0x006617d8 0x0 fs/jffs2/libjffs2.a(compr_rubin.o) + .data 0x006617d8 0x0 fs/jffs2/libjffs2.a(compr_zlib.o) + .data 0x006617d8 0x0 fs/jffs2/libjffs2.a(mini_inflate.o) + .data 0x006617d8 0x30 rtc/librtc.a(date.o) + .data 0x00661808 0x33 drivers/usb/libusb.a(usb_ehci.o) + .data 0x0066183b 0x0 /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_udivsi3.o) + .data 0x0066183b 0x0 /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_divsi3.o) + .data 0x0066183b 0x0 /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_dvmd_lnx.o) + 0x0066183c . = ALIGN (0x4) + 0x0066183c __u_boot_cmd_start = . + +.u_boot_cmd 0x0066183c 0x7a8 + *(.u_boot_cmd) + .u_boot_cmd 0x0066183c 0x1f8 board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) + 0x00661970 __u_boot_cmd_phyRead + 0x00661900 __u_boot_cmd_fi + 0x006618e4 __u_boot_cmd_g + 0x00661954 __u_boot_cmd_pciePhyWrite + 0x00661890 __u_boot_cmd_dclk + 0x006618c8 __u_boot_cmd_map + 0x006619fc __u_boot_cmd_test_wol + 0x006619e0 __u_boot_cmd_rcvr + 0x006618ac __u_boot_cmd_sg + 0x0066183c __u_boot_cmd_bubt + 0x0066198c __u_boot_cmd_phyWrite + 0x00661874 __u_boot_cmd_ir + 0x00661a18 __u_boot_cmd_chk_wol + 0x0066191c __u_boot_cmd_cmpm + 0x006619a8 __u_boot_cmd_switchRegRead + 0x00661858 __u_boot_cmd_resetenv + 0x00661938 __u_boot_cmd_pciePhyRead + 0x006619c4 __u_boot_cmd_switchRegWrite + .u_boot_cmd 0x00661a34 0x1c board/mv_feroceon/config_kw/libconfig_kw.a(mv_flash.o) + 0x00661a34 __u_boot_cmd_sflash + .u_boot_cmd 0x00661a50 0x1c board/mv_feroceon/config_kw/libconfig_kw.a(mv_pageTable.o) + 0x00661a50 __u_boot_cmd_cpumap + .u_boot_cmd 0x00661a6c 0x38 board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) + 0x00661a6c __u_boot_cmd_ide + 0x00661a88 __u_boot_cmd_diskboot + .u_boot_cmd 0x00661aa4 0x1c board/mv_feroceon/config_kw/libconfig_kw.a(mv_ext2_boot.o) + 0x00661aa4 __u_boot_cmd_bootext2 + .u_boot_cmd 0x00661ac0 0x38 common/libcommon.a(cmd_boot.o) + 0x00661adc __u_boot_cmd_reset + 0x00661ac0 __u_boot_cmd_go + .u_boot_cmd 0x00661af8 0x70 common/libcommon.a(cmd_bootm.o) + 0x00661af8 __u_boot_cmd_bootm + 0x00661b4c __u_boot_cmd_iminfo + 0x00661b30 __u_boot_cmd_bootd + 0x00661b14 __u_boot_cmd_boot + .u_boot_cmd 0x00661b68 0x1c common/libcommon.a(cmd_date.o) + 0x00661b68 __u_boot_cmd_date + .u_boot_cmd 0x00661b84 0x38 common/libcommon.a(cmd_ext2.o) + 0x00661ba0 __u_boot_cmd_ext2load + 0x00661b84 __u_boot_cmd_ext2ls + .u_boot_cmd 0x00661bbc 0x54 common/libcommon.a(cmd_fat.o) + 0x00661bf4 __u_boot_cmd_fatinfo + 0x00661bbc __u_boot_cmd_fatload + 0x00661bd8 __u_boot_cmd_fatls + .u_boot_cmd 0x00661c10 0x54 common/libcommon.a(cmd_flash.o) + 0x00661c10 __u_boot_cmd_flinfo + 0x00661c2c __u_boot_cmd_erase + 0x00661c48 __u_boot_cmd_protect + .u_boot_cmd 0x00661c64 0x8c common/libcommon.a(cmd_jffs2.o) + 0x00661c9c __u_boot_cmd_fsinfo + 0x00661c64 __u_boot_cmd_fsload + 0x00661cb8 __u_boot_cmd_chpart + 0x00661cd4 __u_boot_cmd_mtdparts + 0x00661c80 __u_boot_cmd_ls + .u_boot_cmd 0x00661cf0 0x118 common/libcommon.a(cmd_mem.o) + 0x00661cf0 __u_boot_cmd_md + 0x00661d7c __u_boot_cmd_cmp + 0x00661d44 __u_boot_cmd_mw + 0x00661dd0 __u_boot_cmd_loop + 0x00661db4 __u_boot_cmd_base + 0x00661d0c __u_boot_cmd_mm + 0x00661d98 __u_boot_cmd_crc32 + 0x00661d28 __u_boot_cmd_nm + 0x00661dec __u_boot_cmd_mtest + 0x00661d60 __u_boot_cmd_cp + .u_boot_cmd 0x00661e08 0x1c common/libcommon.a(cmd_mmc.o) + 0x00661e08 __u_boot_cmd_mmcinit + .u_boot_cmd 0x00661e24 0x70 common/libcommon.a(cmd_net.o) + 0x00661e78 __u_boot_cmd_ping + 0x00661e5c __u_boot_cmd_rarpboot + 0x00661e40 __u_boot_cmd_tftpboot + 0x00661e24 __u_boot_cmd_bootp + .u_boot_cmd 0x00661e94 0x70 common/libcommon.a(cmd_nvedit.o) + 0x00661ee8 __u_boot_cmd_run + 0x00661ecc __u_boot_cmd_saveenv + 0x00661e94 __u_boot_cmd_printenv + 0x00661eb0 __u_boot_cmd_setenv + .u_boot_cmd 0x00661f04 0x38 common/libcommon.a(cmd_usb.o) + 0x00661f04 __u_boot_cmd_usb + 0x00661f20 __u_boot_cmd_usbboot + .u_boot_cmd 0x00661f3c 0xa8 common/libcommon.a(command.o) + 0x00661f90 __u_boot_cmd_exit + 0x00661f58 __u_boot_cmd_echo + 0x00661fc8 __u_boot_cmd_question_mark + 0x00661f3c __u_boot_cmd_version + 0x00661fac __u_boot_cmd_help + 0x00661f74 __u_boot_cmd_test + 0x00661fe4 __u_boot_cmd_end = . + 0x0066fff0 . = (_start + 0x6fff0) + 0x0066fff0 __bss_start = . + +.bss 0x00670000 0x4cf80 + *(.bss) + .bss 0x00670000 0x0 cpu/arm926ejs/start.o + .bss 0x00670000 0x0 board/mv_feroceon/USP/jump.o + .bss 0x00670000 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(platform.o) + .bss 0x00670000 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsiEeprom.o) + .bss 0x00670000 0x4 board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) + 0x00670000 nandenvECC + .bss 0x00670004 0x2c board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) + 0x00670008 mv_board_num_flash_banks + 0x0067002a yuk_enetaddr + .bss 0x00670030 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_service.o) + .bss 0x00670030 0x4 board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) + .bss 0x00670034 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvAhbToMbus.o) + .bss 0x00670034 0x4 board/mv_feroceon/config_kw/libconfig_kw.a(mvCpuIf.o) + 0x00670034 sampleAtResetTargetArray + .bss 0x00670038 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysXor.o) + .bss 0x00670038 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysDram.o) + .bss 0x00670038 0x4 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysGbe.o) + .bss 0x0067003c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysAudio.o) + .bss 0x0067003c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysTs.o) + .bss 0x0067003c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysPex.o) + .bss 0x0067003c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysSata.o) + .bss 0x0067003c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysUsb.o) + .bss 0x0067003c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvCpu.o) + .bss 0x0067003c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysLCD.o) + .bss 0x0067003c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvLib.o) + .bss 0x0067003c 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvSpec.o) + .bss 0x0067003c 0x4744 board/mv_feroceon/config_kw/libconfig_kw.a(mv_flash.o) + .bss 0x00674780 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_pageTable.o) + .bss 0x00674780 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_rtc.o) + .bss 0x00674780 0x4 board/mv_feroceon/config_kw/libconfig_kw.a(mv_mon_init.o) + 0x00674780 g_stack_cachable + *fill* 0x00674784 0x7c 00 + .bss 0x00674800 0x3800 board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) + 0x00677e40 hdd_found + 0x00674800 request_q + 0x00675610 sataAdapters + 0x00674900 response_q + 0x00677e20 prd_table + .bss 0x00678000 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_protectionUnit.o) + .bss 0x00678000 0xc8 board/mv_feroceon/config_kw/libconfig_kw.a(mv_ext2_boot.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSwitch.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvCommon.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvOs.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvFlashCom.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSata.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvStorageDev.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSFlash.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvEthPhy.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvRtc.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsi.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvGpp.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpi.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpiCmnd.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvUsb.o) + .bss 0x006780c8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvXor.o) + .bss 0x006780c8 0x10 board/mv_feroceon/config_kw/libconfig_kw.a(mvEth.o) + 0x006780d0 ethDescInSram + 0x006780c8 ethPortCtrl + 0x006780d4 ethDescSwCoher + .bss 0x006780d8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvPex.o) + .bss 0x006780d8 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvAudio.o) + .bss 0x006780d8 0xa8 board/mv_feroceon/config_kw/libconfig_kw.a(mvTsu.o) + 0x006780d8 mvTsuCtrl + 0x006780e8 mvTsuPortCtrl + .bss 0x00678180 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvLcd.o) + .bss 0x00678180 0x80 board/mv_feroceon/config_kw/libconfig_kw.a(BuffaloWol.o) + .bss 0x00678200 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvAddrDec.o) + .bss 0x00678200 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvOsSata.o) + .bss 0x00678200 0x10 cpu/arm926ejs/libarm926ejs.a(interrupts.o) + .bss 0x00678210 0x0 cpu/arm926ejs/libarm926ejs.a(cpu.o) + .bss 0x00678210 0x10 lib_arm/libarm.a(board.o) + 0x0067821c monitor_flash_len + .bss 0x00678220 0x0 lib_arm/libarm.a(cache.o) + .bss 0x00678220 0x1c fs/ext2/libext2fs.a(ext2fs.o) + 0x00678234 ext2fs_file + 0x00678238 symlinknest + 0x00678228 indir1_size + 0x00678224 indir1_block + 0x0067822c indir2_block + 0x00678220 ext2fs_root + 0x00678230 indir2_size + .bss 0x0067823c 0x54 fs/ext2/libext2fs.a(dev.o) + .bss 0x00678290 0x25d8 net/libnet.a(net.o) + 0x006782ec NetArpWaitTry + 0x006782c8 NetArpWaitPacketMAC + 0x00678298 NetOurEther + 0x006782a4 NetOurIP + 0x006782a8 NetPingIP + 0x006782d4 NetServerIP + 0x006782d0 NetArpWaitTxPacketSize + 0x006782bc NetArpWaitReplyIP + 0x006782cc NetArpWaitTxPacket + 0x0067a12c NetRxPackets + 0x0067a764 NetOurNISDomain + 0x006782b0 NetArpWaitPacketIP + 0x00678290 NetState + 0x0067a7e6 BootFile + 0x006782d8 NetServerEther + 0x006782b4 NetOurSubnetMask + 0x0067a7e4 NetBootFileSize + 0x006782a0 NetIPID + 0x0067a784 NetOurHostName + 0x006782c0 NetRxPkt + 0x006782b8 NetOurGatewayIP + 0x006782e4 NetEtherNullAddr + 0x00678304 NetRestartWrap + 0x0067a13c NetArpWaitPacketBuf + 0x006782c4 NetRxPktLen + 0x006782ac NetTxPacket + 0x0067a75c NetBootFileXferSize + 0x0067a760 NetOurDNSIP + 0x0067830c PktBuf + 0x0067a7a4 NetOurRootPath + 0x006782f0 NetArpWaitTimerStart + .bss 0x0067a868 0x34 net/libnet.a(tftp.o) + .bss 0x0067a89c 0x8 net/libnet.a(bootp.o) + 0x0067a89c BootpTry + 0x0067a8a0 BootpID + .bss 0x0067a8a4 0x4 net/libnet.a(rarp.o) + 0x0067a8a4 RarpTry + .bss 0x0067a8a8 0xc net/libnet.a(eth.o) + .bss 0x0067a8b4 0x14 net/libnet.a(rcvr.o) + 0x0067a8b4 peerTID + 0x0067a8c0 rcvr_state + 0x0067a8b8 myTID + 0x0067a8bc imagePtr + 0x0067a8c4 packetNum + .bss 0x0067a8c8 0x0 disk/libdisk.a(part.o) + .bss 0x0067a8c8 0x0 disk/libdisk.a(part_dos.o) + .bss 0x0067a8c8 0x0 disk/libdisk.a(part_efi.o) + .bss 0x0067a8c8 0x1e3c drivers/libdrivers.a(cfi_flash.o) + 0x0067a8c8 flash_info + .bss 0x0067c704 0x400 common/libcommon.a(main.o) + 0x0067c704 console_buffer + .bss 0x0067cb04 0x0 common/libcommon.a(cmd_boot.o) + .bss 0x0067cb04 0x108 common/libcommon.a(cmd_bootm.o) + 0x0067cb44 extraBootArgs + 0x0067cb04 header + .bss 0x0067cc0c 0x0 common/libcommon.a(cmd_date.o) + .bss 0x0067cc0c 0x0 common/libcommon.a(cmd_ext2.o) + .bss 0x0067cc0c 0x0 common/libcommon.a(cmd_fat.o) + .bss 0x0067cc0c 0x0 common/libcommon.a(cmd_flash.o) + .bss 0x0067cc0c 0x2ac common/libcommon.a(cmd_jffs2.o) + 0x0067ce2c mtdids + 0x0067cc0c devices + .bss 0x0067ceb8 0x14 common/libcommon.a(cmd_mem.o) + 0x0067cec8 dp_last_size + 0x0067cec4 dp_last_addr + 0x0067cec0 mm_last_size + 0x0067cebc mm_last_addr + .bss 0x0067cecc 0x0 common/libcommon.a(cmd_mmc.o) + .bss 0x0067cecc 0x0 common/libcommon.a(cmd_net.o) + .bss 0x0067cecc 0x0 common/libcommon.a(cmd_nvedit.o) + .bss 0x0067cecc 0x0 common/libcommon.a(cmd_usb.o) + .bss 0x0067cecc 0x600 common/libcommon.a(command.o) + .bss 0x0067d4cc 0x8 common/libcommon.a(console.o) + .bss 0x0067d4d4 0x10 common/libcommon.a(devices.o) + 0x0067d4d4 devlist + 0x0067d4d8 stdio_devices + .bss 0x0067d4e4 0x38 common/libcommon.a(dlmalloc.o) + .bss 0x0067d51c 0x0 common/libcommon.a(env_common.o) + .bss 0x0067d51c 0x0 common/libcommon.a(env_flash.o) + .bss 0x0067d51c 0x0 common/libcommon.a(exports.o) + .bss 0x0067d51c 0x0 common/libcommon.a(flash.o) + .bss 0x0067d51c 0x558 common/libcommon.a(hush.o) + 0x0067da70 nesting_level + 0x0067da68 last_return_code + .bss 0x0067da74 0x0 common/libcommon.a(lists.o) + .bss 0x0067da74 0xda20 common/libcommon.a(usb.o) + 0x0068b490 usb_started + *fill* 0x0068b494 0x4 00 + .bss 0x0068b498 0x5a0 common/libcommon.a(usb_storage.o) + .bss 0x0068ba38 0x0 lib_generic/libgeneric.a(crc32.o) + .bss 0x0068ba38 0x0 lib_generic/libgeneric.a(ctype.o) + .bss 0x0068ba38 0x0 lib_generic/libgeneric.a(display_options.o) + .bss 0x0068ba38 0x4 lib_generic/libgeneric.a(string.o) + 0x0068ba38 ___strtok + .bss 0x0068ba3c 0x0 lib_generic/libgeneric.a(vsprintf.o) + .bss 0x0068ba3c 0x10a8 lib_generic/libgeneric.a(zlib.o) + .bss 0x0068cae4 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvCntmr.o) + .bss 0x0068cae4 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_dram.o) + .bss 0x0068cae4 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_serial.o) + .bss 0x0068cae4 0x4 board/mv_feroceon/config_kw/libconfig_kw.a(mv_egiga.o) + 0x0068cae4 egiga_init + .bss 0x0068cae8 0x2a0 board/mv_feroceon/config_kw/libconfig_kw.a(mmc.o) + .bss 0x0068cd88 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvDramIf.o) + .bss 0x0068cd88 0xc board/mv_feroceon/config_kw/libconfig_kw.a(mvUart.o) + .bss 0x0068cd94 0x0 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpd.o) + .bss 0x0068cd94 0x4 lib_arm/libarm.a(armlinux.o) + .bss 0x0068cd98 0x4c fs/cramfs/libcramfs.a(cramfs.o) + 0x0068cd98 super + .bss 0x0068cde4 0x34 fs/cramfs/libcramfs.a(uncompress.o) + .bss 0x0068ce18 0x30008 fs/fat/libfat.a(fat.o) + 0x0068ce20 get_vfatname_block + 0x006ace20 get_dentfromdir_block + 0x0069ce20 do_fat_read_block + .bss 0x006bce20 0x4 fs/jffs2/libjffs2.a(jffs2_1pass.o) + .bss 0x006bce24 0x0 fs/jffs2/libjffs2.a(compr_rtime.o) + .bss 0x006bce24 0x0 fs/jffs2/libjffs2.a(compr_rubin.o) + .bss 0x006bce24 0x0 fs/jffs2/libjffs2.a(compr_zlib.o) + .bss 0x006bce24 0x0 fs/jffs2/libjffs2.a(mini_inflate.o) + .bss 0x006bce24 0x0 rtc/librtc.a(date.o) + *fill* 0x006bce24 0x1c 00 + .bss 0x006bce40 0x140 drivers/usb/libusb.a(usb_ehci.o) + .bss 0x006bcf80 0x0 /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_udivsi3.o) + .bss 0x006bcf80 0x0 /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_divsi3.o) + .bss 0x006bcf80 0x0 /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_dvmd_lnx.o) + 0x006bcf80 _end = . +Address of section .text set to 0x600000 +LOAD cpu/arm926ejs/start.o +START GROUP +LOAD lib_generic/libgeneric.a +LOAD board/mv_feroceon/config_kw/libconfig_kw.a +LOAD cpu/arm926ejs/libarm926ejs.a +LOAD lib_arm/libarm.a +LOAD fs/cramfs/libcramfs.a +LOAD fs/fat/libfat.a +LOAD fs/fdos/libfdos.a +LOAD fs/jffs2/libjffs2.a +LOAD fs/reiserfs/libreiserfs.a +LOAD fs/ext2/libext2fs.a +LOAD net/libnet.a +LOAD disk/libdisk.a +LOAD rtc/librtc.a +LOAD dtt/libdtt.a +LOAD drivers/libdrivers.a +LOAD drivers/nand/libnand.a +LOAD drivers/usb/libusb.a +LOAD drivers/sk98lin/libsk98lin.a +LOAD post/libpost.a +LOAD post/cpu/libcpu.a +LOAD common/libcommon.a +END GROUP +LOAD /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a +OUTPUT(u-boot elf32-littlearm) + +.stab 0x00000000 0x1038 + .stab 0x00000000 0x534 cpu/arm926ejs/start.o + .stab 0x00000534 0x360 board/mv_feroceon/USP/jump.o + 0x36c (size before relaxing) + .stab 0x00000894 0xe4 board/mv_feroceon/config_kw/libconfig_kw.a(platform.o) + 0xf0 (size before relaxing) + .stab 0x00000978 0x6c0 board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsiEeprom.o) + 0x6cc (size before relaxing) + +.ARM.attributes + 0x00000000 0x18 + .ARM.attributes + 0x00000000 0x18 cpu/arm926ejs/start.o + .ARM.attributes + 0x00000018 0x18 board/mv_feroceon/USP/jump.o + .ARM.attributes + 0x00000030 0x18 board/mv_feroceon/config_kw/libconfig_kw.a(platform.o) + .ARM.attributes + 0x00000048 0x18 board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsiEeprom.o) + .ARM.attributes + 0x00000060 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) + .ARM.attributes + 0x00000088 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) + .ARM.attributes + 0x000000b0 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mv_service.o) + .ARM.attributes + 0x000000d8 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) + .ARM.attributes + 0x00000100 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvAhbToMbus.o) + .ARM.attributes + 0x00000128 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvCpuIf.o) + .ARM.attributes + 0x00000150 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysXor.o) + .ARM.attributes + 0x00000178 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysDram.o) + .ARM.attributes + 0x000001a0 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysGbe.o) + .ARM.attributes + 0x000001c8 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysAudio.o) + .ARM.attributes + 0x000001f0 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysTs.o) + .ARM.attributes + 0x00000218 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysPex.o) + .ARM.attributes + 0x00000240 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysSata.o) + .ARM.attributes + 0x00000268 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysUsb.o) + .ARM.attributes + 0x00000290 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvCpu.o) + .ARM.attributes + 0x000002b8 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysLCD.o) + .ARM.attributes + 0x000002e0 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvLib.o) + .ARM.attributes + 0x00000308 0x26 board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvSpec.o) + .ARM.attributes + 0x0000032e 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mv_flash.o) + .ARM.attributes + 0x00000356 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mv_pageTable.o) + .ARM.attributes + 0x0000037e 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mv_rtc.o) + .ARM.attributes + 0x000003a6 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mv_mon_init.o) + .ARM.attributes + 0x000003ce 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) + .ARM.attributes + 0x000003f6 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mv_protectionUnit.o) + .ARM.attributes + 0x0000041e 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mv_ext2_boot.o) + .ARM.attributes + 0x00000446 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSwitch.o) + .ARM.attributes + 0x0000046e 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvCommon.o) + .ARM.attributes + 0x00000496 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvOs.o) + .ARM.attributes + 0x000004be 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvFlashCom.o) + .ARM.attributes + 0x000004e6 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSata.o) + .ARM.attributes + 0x0000050e 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvStorageDev.o) + .ARM.attributes + 0x00000536 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSFlash.o) + .ARM.attributes + 0x0000055e 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvEthPhy.o) + .ARM.attributes + 0x00000586 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvRtc.o) + .ARM.attributes + 0x000005ae 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsi.o) + .ARM.attributes + 0x000005d6 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvGpp.o) + .ARM.attributes + 0x000005fe 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpi.o) + .ARM.attributes + 0x00000626 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpiCmnd.o) + .ARM.attributes + 0x0000064e 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvUsb.o) + .ARM.attributes + 0x00000676 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvXor.o) + .ARM.attributes + 0x0000069e 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvEth.o) + .ARM.attributes + 0x000006c6 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvPex.o) + .ARM.attributes + 0x000006ee 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvAudio.o) + .ARM.attributes + 0x00000716 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvTsu.o) + .ARM.attributes + 0x0000073e 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(mvLcd.o) + .ARM.attributes + 0x00000766 0x28 board/mv_feroceon/config_kw/libconfig_kw.a(BuffaloWol.o) + .ARM.attributes + 0x0000078e 0x28 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.ARM.attributes + 0x00001254 0x14 /opt/Orion-SDK/SDK-2.0-LE/tools/gcc/bin/../lib/gcc/arm-none-linux-gnueabi/4.2.0/libgcc.a(_dvmd_lnx.o) + +.stabstr 0x00000000 0x179 + .stabstr 0x00000000 0x179 cpu/arm926ejs/start.o + +.debug_abbrev 0x00000000 0x10294 + .debug_abbrev 0x00000000 0x31b board/mv_feroceon/config_kw/libconfig_kw.a(mv_cmd.o) + .debug_abbrev 0x0000031b 0x403 board/mv_feroceon/config_kw/libconfig_kw.a(mv_main.o) + .debug_abbrev 0x0000071e 0xd0 board/mv_feroceon/config_kw/libconfig_kw.a(mv_service.o) + .debug_abbrev 0x000007ee 0x337 board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvLib.o) + .debug_abbrev 0x00000b25 0x281 board/mv_feroceon/config_kw/libconfig_kw.a(mvAhbToMbus.o) + .debug_abbrev 0x00000da6 0x2a9 board/mv_feroceon/config_kw/libconfig_kw.a(mvCpuIf.o) + .debug_abbrev 0x0000104f 0x2bf board/mv_feroceon/config_kw/libconfig_kw.a(mvSysXor.o) + .debug_abbrev 0x0000130e 0x1b9 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysDram.o) + .debug_abbrev 0x000014c7 0x295 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysGbe.o) + .debug_abbrev 0x0000175c 0x1f5 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysAudio.o) + .debug_abbrev 0x00001951 0x266 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysTs.o) + .debug_abbrev 0x00001bb7 0x2f6 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysPex.o) + .debug_abbrev 0x00001ead 0x252 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysSata.o) + .debug_abbrev 0x000020ff 0x258 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysUsb.o) + .debug_abbrev 0x00002357 0x26d board/mv_feroceon/config_kw/libconfig_kw.a(mvCpu.o) + .debug_abbrev 0x000025c4 0x2b3 board/mv_feroceon/config_kw/libconfig_kw.a(mvSysLCD.o) + .debug_abbrev 0x00002877 0x341 board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvLib.o) + .debug_abbrev 0x00002bb8 0x11e board/mv_feroceon/config_kw/libconfig_kw.a(mvBoardEnvSpec.o) + .debug_abbrev 0x00002cd6 0x2f5 board/mv_feroceon/config_kw/libconfig_kw.a(mv_flash.o) + .debug_abbrev 0x00002fcb 0x2a7 board/mv_feroceon/config_kw/libconfig_kw.a(mv_pageTable.o) + .debug_abbrev 0x00003272 0x105 board/mv_feroceon/config_kw/libconfig_kw.a(mv_rtc.o) + .debug_abbrev 0x00003377 0x112 board/mv_feroceon/config_kw/libconfig_kw.a(mv_mon_init.o) + .debug_abbrev 0x00003489 0x424 board/mv_feroceon/config_kw/libconfig_kw.a(mv_ide.o) + .debug_abbrev 0x000038ad 0x2c9 board/mv_feroceon/config_kw/libconfig_kw.a(mv_protectionUnit.o) + .debug_abbrev 0x00003b76 0x14f board/mv_feroceon/config_kw/libconfig_kw.a(mv_ext2_boot.o) + .debug_abbrev 0x00003cc5 0x167 board/mv_feroceon/config_kw/libconfig_kw.a(mvSwitch.o) + .debug_abbrev 0x00003e2c 0x17f board/mv_feroceon/config_kw/libconfig_kw.a(mvCommon.o) + .debug_abbrev 0x00003fab 0x199 board/mv_feroceon/config_kw/libconfig_kw.a(mvOs.o) + .debug_abbrev 0x00004144 0x313 board/mv_feroceon/config_kw/libconfig_kw.a(mvFlashCom.o) + .debug_abbrev 0x00004457 0x3d4 board/mv_feroceon/config_kw/libconfig_kw.a(mvSata.o) + .debug_abbrev 0x0000482b 0x31a board/mv_feroceon/config_kw/libconfig_kw.a(mvStorageDev.o) + .debug_abbrev 0x00004b45 0x230 board/mv_feroceon/config_kw/libconfig_kw.a(mvSFlash.o) + .debug_abbrev 0x00004d75 0x2aa board/mv_feroceon/config_kw/libconfig_kw.a(mvEthPhy.o) + .debug_abbrev 0x0000501f 0x278 board/mv_feroceon/config_kw/libconfig_kw.a(mvRtc.o) + .debug_abbrev 0x00005297 0x2eb board/mv_feroceon/config_kw/libconfig_kw.a(mvTwsi.o) + .debug_abbrev 0x00005582 0x2e6 board/mv_feroceon/config_kw/libconfig_kw.a(mvGpp.o) + .debug_abbrev 0x00005868 0x235 board/mv_feroceon/config_kw/libconfig_kw.a(mvSpi.o) + .debug_abbrev 0x00005a9d 0x11f board/mv_feroceon/config_kw/libconfig_kw.a(mvSpiCmnd.o) + .debug_abbrev 0x00005bbc 0x272 board/mv_feroceon/config_kw/libconfig_kw.a(mvUsb.o) + .debug_abbrev 0x00005e2e 0x24b board/mv_feroceon/config_kw/libconfig_kw.a(mvXor.o) + .debug_abbrev 0x00006079 0x3b3 board/mv_feroceon/config_kw/libconfig_kw.a(mvEth.o) + .debug_abbrev 0x0000642c 0x278 board/mv_feroceon/config_kw/libconfig_kw.a(mvPex.o) + .debug_abbrev 0x000066a4 0x308 board/mv_feroceon/config_kw/libconfig_kw.a(mvAudio.o) + .debug_abbrev 0x000069ac 0x29a board/mv_feroceon/config_kw/libconfig_kw.a(mvTsu.o) + .debug_abbrev 0x00006c46 0xd0 board/mv_feroceon/config_kw/libconfig_kw.a(mvLcd.o) + .debug_abbrev 0x00006d16 0x289 board/mv_feroceon/config_kw/libconfig_kw.a(BuffaloWol.o) + .debug_abbrev 0x00006f9f 0x21b board/mv_feroceon/config_kw/libconfig_kw.a(mvCtrlEnvAddrDec.o) + .debug_abbrev 0x000071ba 0xe3 board/mv_feroceon/config_kw/libconfig_kw.a(mvOsSata.o) + .debug_abbrev 0x0000729d 0x24d cpu/arm926ejs/libarm926ejs.a(interrupts.o) + .debug_abbrev 0x000074ea 0x1fd cpu/arm926ejs/libarm926ejs.a(cpu.o) + .debug_abbrev 0x000076e7 0x271 lib_arm/libarm.a(board.o) + .debug_abbrev 0x00007958 0xe3 lib_arm/libarm.a(cache.o) + .debug_abbrev 0x00007a3b 0x2df fs/ext2/libext2fs.a(ext2fs.o) + .debug_abbrev 0x00007d1a 0x168 fs/ext2/libext2fs.a(dev.o) + .debug_abbrev 0x00007e82 0x3f7 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